2006.173.01:46:02.90;Log Opened: Mark IV Field System Version 9.7.7 2006.173.01:46:02.90;location,TSUKUB32,-140.09,36.10,61.0 2006.173.01:46:02.91;horizon1,0.,5.,360. 2006.173.01:46:02.91;antenna,32.0,180.0,180.0,10.0,710.0,5.0,88.0,azel 2006.173.01:46:02.92;equip,k42c/mk4,vlbab,vlbab,mk4,500.10,3,a/d,101,60,20,none,41,1,in,8bit,cdp,3 2006.173.01:46:02.92;drivev11,330,270,no 2006.173.01:46:02.92;drivev12,mvme117,0,11.400,2548.000,152.780,-6.655,0.014,152,10.000,54500 2006.173.01:46:02.93;drivev13,15.000,268,10.000,10.000,10.000 2006.173.01:46:02.93;drivev21,330,270,no 2006.173.01:46:02.99;drivev22,mvme117,0,11.500,2821.000,127.500,-8.640,0.015,152,14.000,54500 2006.173.01:46:03.00;drivev23,15.000,268,10.000,10.000,10.000 2006.173.01:46:03.00;head10,all,all,all,odd,adaptive,no,5.0000,1 2006.173.01:46:03.00;head11,131.5,16.4,-291.0,131.5,16.4,0.8,168.30,168.30 2006.173.01:46:03.01;head12,122.8,13.9,-150.8,122.8,14.7,2.5,167.61,167.61 2006.173.01:46:03.01;head20,all,all,all,odd,adaptive,no,5.0000,1 2006.173.01:46:03.02;head21,145.3,16.1,-209.3,137.2,16.1,58.9,165.28,165.28 2006.173.01:46:03.02;head22,157.5,17.4,-203.7,149.2,16.6,56.5,169.73,169.73 2006.173.01:46:03.02;time,-0.364,101.533,rate 2006.173.01:46:03.03;flagr,200 2006.173.01:46:03.08:" JD0606 2006 TSUKUB32 T Ts 2006.173.01:46:03.08:" T TSUKUB32 AZEL .0000 180.0 14 10.0 710.0 180.0 14 5.0 88.0 32.0 Ts 108 2006.173.01:46:03.09:" Ts TSUKUB32 -3957408.75120 3310229.34660 3737494.83600 73452301 2006.173.01:46:03.09:" 108 K4-TSUKB 0 9149 2006.173.01:46:03.10:" drudg version 050216 compiled under FS 9.7.07 2006.173.01:46:03.10:" Rack=K4-2/M4 Recorder 1=K4-2 Recorder 2=none 2006.173.01:46:03.11:exper_initi 2006.173.01:46:03.11&exper_initi/proc_library 2006.173.01:46:03.11&exper_initi/sched_initi 2006.173.01:46:03.11:scan_name=173-0200,jd0606,40 2006.173.01:46:03.11:source=4c39.25,092703.01,390220.9,2000.0,cw 2006.173.01:46:03.11#antcn#PM 1 00019 2005 228 00 22 31 00 2006.173.01:46:03.11#antcn#PM 2 90.0000 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 2006.173.01:46:03.11#antcn#PM 2 -0.0279715 0.0000000 -0.0282214 -0.0241630 -0.0014011 2006.173.01:46:03.11#antcn#PM 3 -0.0059899 0.0042895 -0.0643783 0.0000000 0.0000000 2006.173.01:46:03.11#antcn#PM 4 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.173.01:46:03.11#antcn#PM 5 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.173.01:46:03.14#flagr#flagr/antenna,new-source 2006.173.01:46:04.14:ready_k5 2006.173.01:46:04.14&ready_k5/obsinfo=st 2006.173.01:46:04.14&ready_k5/autoobs=1 2006.173.01:46:04.14&ready_k5/autoobs=2 2006.173.01:46:04.14&ready_k5/autoobs=3 2006.173.01:46:04.14&ready_k5/autoobs=4 2006.173.01:46:04.14&ready_k5/obsinfo 2006.173.01:46:04.14/obsinfo=st/error_log.tmp was not found (or not removed). 2006.173.01:46:07.78/autoobs//k5ts1/ autoobs started! 2006.173.01:46:11.31/autoobs//k5ts2/ autoobs started! 2006.173.01:46:15.26/autoobs//k5ts3/ autoobs started! 2006.173.01:46:18.83/autoobs//k5ts4/ autoobs started! 2006.173.01:46:18.90/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.01:46:18.90:setupk4=1 2006.173.01:46:18.90&setupk4/xlog=on 2006.173.01:46:18.90&setupk4/echo=on 2006.173.01:46:18.90&setupk4/pcalon 2006.173.01:46:18.90&setupk4/"tpicd=stop 2006.173.01:46:18.90&setupk4/"rec=synch_on 2006.173.01:46:18.90&setupk4/"rec_mode=128 2006.173.01:46:18.90&setupk4/!* 2006.173.01:46:18.90&setupk4/recpk4 2006.173.01:46:18.90&setupk4/vck44 2006.173.01:46:18.90&setupk4/ifdk4 2006.173.01:46:18.90&setupk4/!*+20s 2006.173.01:46:18.90&setupk4/"tpicd 2006.173.01:46:18.90&setupk4/echo=off 2006.173.01:46:18.90&setupk4/xlog=off 2006.173.01:46:18.90$setupk4/echo=on 2006.173.01:46:18.90$setupk4/pcalon 2006.173.01:46:18.90&pcalon/"no phase cal control is implemented here 2006.173.01:46:18.90$pcalon/"no phase cal control is implemented here 2006.173.01:46:18.90$setupk4/"tpicd=stop 2006.173.01:46:18.90$setupk4/"rec=synch_on 2006.173.01:46:18.90$setupk4/"rec_mode=128 2006.173.01:46:18.90$setupk4/!* 2006.173.01:46:18.90$setupk4/recpk4 2006.173.01:46:18.90&recpk4/recpatch= 2006.173.01:46:18.90&recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.01:46:18.90&recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.01:46:18.90$recpk4/recpatch= 2006.173.01:46:18.91$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.01:46:18.91$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.01:46:18.91$setupk4/vck44 2006.173.01:46:18.91&vck44/valo=1,524.99 2006.173.01:46:18.91&vck44/va=1,7 2006.173.01:46:18.91&vck44/valo=2,534.99 2006.173.01:46:18.91&vck44/va=2,6 2006.173.01:46:18.91&vck44/valo=3,564.99 2006.173.01:46:18.91&vck44/va=3,5 2006.173.01:46:18.91&vck44/valo=4,624.99 2006.173.01:46:18.91&vck44/va=4,6 2006.173.01:46:18.91&vck44/valo=5,734.99 2006.173.01:46:18.91&vck44/va=5,4 2006.173.01:46:18.91&vck44/valo=6,814.99 2006.173.01:46:18.91&vck44/va=6,3 2006.173.01:46:18.91&vck44/valo=7,864.99 2006.173.01:46:18.91&vck44/va=7,4 2006.173.01:46:18.91&vck44/valo=8,884.99 2006.173.01:46:18.91&vck44/va=8,4 2006.173.01:46:18.91&vck44/vblo=1,629.99 2006.173.01:46:18.91&vck44/vb=1,4 2006.173.01:46:18.91&vck44/vblo=2,634.99 2006.173.01:46:18.91&vck44/vb=2,4 2006.173.01:46:18.91&vck44/vblo=3,649.99 2006.173.01:46:18.91&vck44/vb=3,4 2006.173.01:46:18.91&vck44/vblo=4,679.99 2006.173.01:46:18.91&vck44/vb=4,4 2006.173.01:46:18.91&vck44/vblo=5,709.99 2006.173.01:46:18.91&vck44/vb=5,4 2006.173.01:46:18.91&vck44/vblo=6,719.99 2006.173.01:46:18.91&vck44/vb=6,4 2006.173.01:46:18.91&vck44/vblo=7,734.99 2006.173.01:46:18.91&vck44/vb=7,4 2006.173.01:46:18.91&vck44/vblo=8,744.99 2006.173.01:46:18.91&vck44/vb=8,4 2006.173.01:46:18.91&vck44/vabw=wide 2006.173.01:46:18.91&vck44/vbbw=wide 2006.173.01:46:18.91$vck44/valo=1,524.99 2006.173.01:46:18.91#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.01:46:18.91#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.01:46:18.91#ibcon#ireg 17 cls_cnt 0 2006.173.01:46:18.91#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.01:46:18.91#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.01:46:18.91#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.01:46:18.91#ibcon#enter wrdev, iclass 36, count 0 2006.173.01:46:18.91#ibcon#first serial, iclass 36, count 0 2006.173.01:46:18.91#ibcon#enter sib2, iclass 36, count 0 2006.173.01:46:18.91#ibcon#flushed, iclass 36, count 0 2006.173.01:46:18.91#ibcon#about to write, iclass 36, count 0 2006.173.01:46:18.91#ibcon#wrote, iclass 36, count 0 2006.173.01:46:18.91#ibcon#about to read 3, iclass 36, count 0 2006.173.01:46:18.93#ibcon#read 3, iclass 36, count 0 2006.173.01:46:18.93#ibcon#about to read 4, iclass 36, count 0 2006.173.01:46:18.93#ibcon#read 4, iclass 36, count 0 2006.173.01:46:18.93#ibcon#about to read 5, iclass 36, count 0 2006.173.01:46:18.93#ibcon#read 5, iclass 36, count 0 2006.173.01:46:18.93#ibcon#about to read 6, iclass 36, count 0 2006.173.01:46:18.93#ibcon#read 6, iclass 36, count 0 2006.173.01:46:18.93#ibcon#end of sib2, iclass 36, count 0 2006.173.01:46:18.93#ibcon#*mode == 0, iclass 36, count 0 2006.173.01:46:18.93#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.01:46:18.93#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.01:46:18.93#ibcon#*before write, iclass 36, count 0 2006.173.01:46:18.93#ibcon#enter sib2, iclass 36, count 0 2006.173.01:46:18.93#ibcon#flushed, iclass 36, count 0 2006.173.01:46:18.93#ibcon#about to write, iclass 36, count 0 2006.173.01:46:18.93#ibcon#wrote, iclass 36, count 0 2006.173.01:46:18.93#ibcon#about to read 3, iclass 36, count 0 2006.173.01:46:18.99#ibcon#read 3, iclass 36, count 0 2006.173.01:46:18.99#ibcon#about to read 4, iclass 36, count 0 2006.173.01:46:18.99#ibcon#read 4, iclass 36, count 0 2006.173.01:46:18.99#ibcon#about to read 5, iclass 36, count 0 2006.173.01:46:18.99#ibcon#read 5, iclass 36, count 0 2006.173.01:46:18.99#ibcon#about to read 6, iclass 36, count 0 2006.173.01:46:18.99#ibcon#read 6, iclass 36, count 0 2006.173.01:46:18.99#ibcon#end of sib2, iclass 36, count 0 2006.173.01:46:18.99#ibcon#*after write, iclass 36, count 0 2006.173.01:46:18.99#ibcon#*before return 0, iclass 36, count 0 2006.173.01:46:18.99#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.01:46:18.99#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.01:46:18.99#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.01:46:18.99#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.01:46:19.00$vck44/va=1,7 2006.173.01:46:19.00#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.01:46:19.00#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.01:46:19.00#ibcon#ireg 11 cls_cnt 2 2006.173.01:46:19.00#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.01:46:19.00#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.01:46:19.00#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.01:46:19.00#ibcon#enter wrdev, iclass 38, count 2 2006.173.01:46:19.00#ibcon#first serial, iclass 38, count 2 2006.173.01:46:19.00#ibcon#enter sib2, iclass 38, count 2 2006.173.01:46:19.00#ibcon#flushed, iclass 38, count 2 2006.173.01:46:19.00#ibcon#about to write, iclass 38, count 2 2006.173.01:46:19.00#ibcon#wrote, iclass 38, count 2 2006.173.01:46:19.00#ibcon#about to read 3, iclass 38, count 2 2006.173.01:46:19.01#ibcon#read 3, iclass 38, count 2 2006.173.01:46:19.01#ibcon#about to read 4, iclass 38, count 2 2006.173.01:46:19.01#ibcon#read 4, iclass 38, count 2 2006.173.01:46:19.01#ibcon#about to read 5, iclass 38, count 2 2006.173.01:46:19.01#ibcon#read 5, iclass 38, count 2 2006.173.01:46:19.01#ibcon#about to read 6, iclass 38, count 2 2006.173.01:46:19.01#ibcon#read 6, iclass 38, count 2 2006.173.01:46:19.01#ibcon#end of sib2, iclass 38, count 2 2006.173.01:46:19.01#ibcon#*mode == 0, iclass 38, count 2 2006.173.01:46:19.01#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.01:46:19.01#ibcon#[25=AT01-07\r\n] 2006.173.01:46:19.01#ibcon#*before write, iclass 38, count 2 2006.173.01:46:19.01#ibcon#enter sib2, iclass 38, count 2 2006.173.01:46:19.01#ibcon#flushed, iclass 38, count 2 2006.173.01:46:19.01#ibcon#about to write, iclass 38, count 2 2006.173.01:46:19.01#ibcon#wrote, iclass 38, count 2 2006.173.01:46:19.01#ibcon#about to read 3, iclass 38, count 2 2006.173.01:46:19.06#ibcon#read 3, iclass 38, count 2 2006.173.01:46:19.06#ibcon#about to read 4, iclass 38, count 2 2006.173.01:46:19.06#ibcon#read 4, iclass 38, count 2 2006.173.01:46:19.06#ibcon#about to read 5, iclass 38, count 2 2006.173.01:46:19.06#ibcon#read 5, iclass 38, count 2 2006.173.01:46:19.06#ibcon#about to read 6, iclass 38, count 2 2006.173.01:46:19.06#ibcon#read 6, iclass 38, count 2 2006.173.01:46:19.06#ibcon#end of sib2, iclass 38, count 2 2006.173.01:46:19.06#ibcon#*after write, iclass 38, count 2 2006.173.01:46:19.06#ibcon#*before return 0, iclass 38, count 2 2006.173.01:46:19.06#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.01:46:19.06#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.01:46:19.06#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.01:46:19.06#ibcon#ireg 7 cls_cnt 0 2006.173.01:46:19.06#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.01:46:19.18#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.01:46:19.18#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.01:46:19.18#ibcon#enter wrdev, iclass 38, count 0 2006.173.01:46:19.18#ibcon#first serial, iclass 38, count 0 2006.173.01:46:19.18#ibcon#enter sib2, iclass 38, count 0 2006.173.01:46:19.18#ibcon#flushed, iclass 38, count 0 2006.173.01:46:19.18#ibcon#about to write, iclass 38, count 0 2006.173.01:46:19.18#ibcon#wrote, iclass 38, count 0 2006.173.01:46:19.18#ibcon#about to read 3, iclass 38, count 0 2006.173.01:46:19.19#ibcon#read 3, iclass 38, count 0 2006.173.01:46:19.19#ibcon#about to read 4, iclass 38, count 0 2006.173.01:46:19.19#ibcon#read 4, iclass 38, count 0 2006.173.01:46:19.19#ibcon#about to read 5, iclass 38, count 0 2006.173.01:46:19.19#ibcon#read 5, iclass 38, count 0 2006.173.01:46:19.19#ibcon#about to read 6, iclass 38, count 0 2006.173.01:46:19.19#ibcon#read 6, iclass 38, count 0 2006.173.01:46:19.19#ibcon#end of sib2, iclass 38, count 0 2006.173.01:46:19.19#ibcon#*mode == 0, iclass 38, count 0 2006.173.01:46:19.19#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.01:46:19.19#ibcon#[25=USB\r\n] 2006.173.01:46:19.19#ibcon#*before write, iclass 38, count 0 2006.173.01:46:19.19#ibcon#enter sib2, iclass 38, count 0 2006.173.01:46:19.19#ibcon#flushed, iclass 38, count 0 2006.173.01:46:19.19#ibcon#about to write, iclass 38, count 0 2006.173.01:46:19.19#ibcon#wrote, iclass 38, count 0 2006.173.01:46:19.19#ibcon#about to read 3, iclass 38, count 0 2006.173.01:46:19.22#ibcon#read 3, iclass 38, count 0 2006.173.01:46:19.22#ibcon#about to read 4, iclass 38, count 0 2006.173.01:46:19.22#ibcon#read 4, iclass 38, count 0 2006.173.01:46:19.22#ibcon#about to read 5, iclass 38, count 0 2006.173.01:46:19.22#ibcon#read 5, iclass 38, count 0 2006.173.01:46:19.22#ibcon#about to read 6, iclass 38, count 0 2006.173.01:46:19.22#ibcon#read 6, iclass 38, count 0 2006.173.01:46:19.22#ibcon#end of sib2, iclass 38, count 0 2006.173.01:46:19.22#ibcon#*after write, iclass 38, count 0 2006.173.01:46:19.22#ibcon#*before return 0, iclass 38, count 0 2006.173.01:46:19.22#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.01:46:19.22#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.01:46:19.22#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.01:46:19.22#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.01:46:19.22$vck44/valo=2,534.99 2006.173.01:46:19.22#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.01:46:19.22#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.01:46:19.22#ibcon#ireg 17 cls_cnt 0 2006.173.01:46:19.22#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.01:46:19.22#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.01:46:19.22#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.01:46:19.22#ibcon#enter wrdev, iclass 40, count 0 2006.173.01:46:19.22#ibcon#first serial, iclass 40, count 0 2006.173.01:46:19.22#ibcon#enter sib2, iclass 40, count 0 2006.173.01:46:19.22#ibcon#flushed, iclass 40, count 0 2006.173.01:46:19.22#ibcon#about to write, iclass 40, count 0 2006.173.01:46:19.22#ibcon#wrote, iclass 40, count 0 2006.173.01:46:19.22#ibcon#about to read 3, iclass 40, count 0 2006.173.01:46:19.24#ibcon#read 3, iclass 40, count 0 2006.173.01:46:19.24#ibcon#about to read 4, iclass 40, count 0 2006.173.01:46:19.24#ibcon#read 4, iclass 40, count 0 2006.173.01:46:19.24#ibcon#about to read 5, iclass 40, count 0 2006.173.01:46:19.24#ibcon#read 5, iclass 40, count 0 2006.173.01:46:19.24#ibcon#about to read 6, iclass 40, count 0 2006.173.01:46:19.24#ibcon#read 6, iclass 40, count 0 2006.173.01:46:19.24#ibcon#end of sib2, iclass 40, count 0 2006.173.01:46:19.24#ibcon#*mode == 0, iclass 40, count 0 2006.173.01:46:19.24#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.01:46:19.24#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.01:46:19.24#ibcon#*before write, iclass 40, count 0 2006.173.01:46:19.24#ibcon#enter sib2, iclass 40, count 0 2006.173.01:46:19.24#ibcon#flushed, iclass 40, count 0 2006.173.01:46:19.24#ibcon#about to write, iclass 40, count 0 2006.173.01:46:19.24#ibcon#wrote, iclass 40, count 0 2006.173.01:46:19.24#ibcon#about to read 3, iclass 40, count 0 2006.173.01:46:19.29#ibcon#read 3, iclass 40, count 0 2006.173.01:46:19.29#ibcon#about to read 4, iclass 40, count 0 2006.173.01:46:19.29#ibcon#read 4, iclass 40, count 0 2006.173.01:46:19.29#ibcon#about to read 5, iclass 40, count 0 2006.173.01:46:19.29#ibcon#read 5, iclass 40, count 0 2006.173.01:46:19.29#ibcon#about to read 6, iclass 40, count 0 2006.173.01:46:19.29#ibcon#read 6, iclass 40, count 0 2006.173.01:46:19.29#ibcon#end of sib2, iclass 40, count 0 2006.173.01:46:19.29#ibcon#*after write, iclass 40, count 0 2006.173.01:46:19.29#ibcon#*before return 0, iclass 40, count 0 2006.173.01:46:19.29#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.01:46:19.29#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.01:46:19.29#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.01:46:19.29#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.01:46:19.29$vck44/va=2,6 2006.173.01:46:19.29#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.01:46:19.29#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.01:46:19.29#ibcon#ireg 11 cls_cnt 2 2006.173.01:46:19.29#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.01:46:19.33#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.01:46:19.33#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.01:46:19.33#ibcon#enter wrdev, iclass 4, count 2 2006.173.01:46:19.33#ibcon#first serial, iclass 4, count 2 2006.173.01:46:19.33#ibcon#enter sib2, iclass 4, count 2 2006.173.01:46:19.33#ibcon#flushed, iclass 4, count 2 2006.173.01:46:19.33#ibcon#about to write, iclass 4, count 2 2006.173.01:46:19.33#ibcon#wrote, iclass 4, count 2 2006.173.01:46:19.33#ibcon#about to read 3, iclass 4, count 2 2006.173.01:46:19.35#ibcon#read 3, iclass 4, count 2 2006.173.01:46:19.35#ibcon#about to read 4, iclass 4, count 2 2006.173.01:46:19.35#ibcon#read 4, iclass 4, count 2 2006.173.01:46:19.35#ibcon#about to read 5, iclass 4, count 2 2006.173.01:46:19.35#ibcon#read 5, iclass 4, count 2 2006.173.01:46:19.35#ibcon#about to read 6, iclass 4, count 2 2006.173.01:46:19.35#ibcon#read 6, iclass 4, count 2 2006.173.01:46:19.35#ibcon#end of sib2, iclass 4, count 2 2006.173.01:46:19.35#ibcon#*mode == 0, iclass 4, count 2 2006.173.01:46:19.35#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.01:46:19.35#ibcon#[25=AT02-06\r\n] 2006.173.01:46:19.35#ibcon#*before write, iclass 4, count 2 2006.173.01:46:19.35#ibcon#enter sib2, iclass 4, count 2 2006.173.01:46:19.35#ibcon#flushed, iclass 4, count 2 2006.173.01:46:19.35#ibcon#about to write, iclass 4, count 2 2006.173.01:46:19.35#ibcon#wrote, iclass 4, count 2 2006.173.01:46:19.35#ibcon#about to read 3, iclass 4, count 2 2006.173.01:46:19.38#ibcon#read 3, iclass 4, count 2 2006.173.01:46:19.38#ibcon#about to read 4, iclass 4, count 2 2006.173.01:46:19.38#ibcon#read 4, iclass 4, count 2 2006.173.01:46:19.38#ibcon#about to read 5, iclass 4, count 2 2006.173.01:46:19.38#ibcon#read 5, iclass 4, count 2 2006.173.01:46:19.38#ibcon#about to read 6, iclass 4, count 2 2006.173.01:46:19.38#ibcon#read 6, iclass 4, count 2 2006.173.01:46:19.38#ibcon#end of sib2, iclass 4, count 2 2006.173.01:46:19.38#ibcon#*after write, iclass 4, count 2 2006.173.01:46:19.38#ibcon#*before return 0, iclass 4, count 2 2006.173.01:46:19.38#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.01:46:19.38#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.01:46:19.38#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.01:46:19.38#ibcon#ireg 7 cls_cnt 0 2006.173.01:46:19.38#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.01:46:19.50#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.01:46:19.50#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.01:46:19.50#ibcon#enter wrdev, iclass 4, count 0 2006.173.01:46:19.50#ibcon#first serial, iclass 4, count 0 2006.173.01:46:19.50#ibcon#enter sib2, iclass 4, count 0 2006.173.01:46:19.50#ibcon#flushed, iclass 4, count 0 2006.173.01:46:19.50#ibcon#about to write, iclass 4, count 0 2006.173.01:46:19.50#ibcon#wrote, iclass 4, count 0 2006.173.01:46:19.50#ibcon#about to read 3, iclass 4, count 0 2006.173.01:46:19.52#ibcon#read 3, iclass 4, count 0 2006.173.01:46:19.52#ibcon#about to read 4, iclass 4, count 0 2006.173.01:46:19.52#ibcon#read 4, iclass 4, count 0 2006.173.01:46:19.52#ibcon#about to read 5, iclass 4, count 0 2006.173.01:46:19.52#ibcon#read 5, iclass 4, count 0 2006.173.01:46:19.52#ibcon#about to read 6, iclass 4, count 0 2006.173.01:46:19.52#ibcon#read 6, iclass 4, count 0 2006.173.01:46:19.52#ibcon#end of sib2, iclass 4, count 0 2006.173.01:46:19.52#ibcon#*mode == 0, iclass 4, count 0 2006.173.01:46:19.52#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.01:46:19.52#ibcon#[25=USB\r\n] 2006.173.01:46:19.52#ibcon#*before write, iclass 4, count 0 2006.173.01:46:19.52#ibcon#enter sib2, iclass 4, count 0 2006.173.01:46:19.52#ibcon#flushed, iclass 4, count 0 2006.173.01:46:19.52#ibcon#about to write, iclass 4, count 0 2006.173.01:46:19.52#ibcon#wrote, iclass 4, count 0 2006.173.01:46:19.52#ibcon#about to read 3, iclass 4, count 0 2006.173.01:46:19.55#ibcon#read 3, iclass 4, count 0 2006.173.01:46:19.55#ibcon#about to read 4, iclass 4, count 0 2006.173.01:46:19.55#ibcon#read 4, iclass 4, count 0 2006.173.01:46:19.55#ibcon#about to read 5, iclass 4, count 0 2006.173.01:46:19.55#ibcon#read 5, iclass 4, count 0 2006.173.01:46:19.55#ibcon#about to read 6, iclass 4, count 0 2006.173.01:46:19.55#ibcon#read 6, iclass 4, count 0 2006.173.01:46:19.55#ibcon#end of sib2, iclass 4, count 0 2006.173.01:46:19.55#ibcon#*after write, iclass 4, count 0 2006.173.01:46:19.55#ibcon#*before return 0, iclass 4, count 0 2006.173.01:46:19.55#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.01:46:19.55#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.01:46:19.55#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.01:46:19.55#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.01:46:19.55$vck44/valo=3,564.99 2006.173.01:46:19.55#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.01:46:19.55#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.01:46:19.55#ibcon#ireg 17 cls_cnt 0 2006.173.01:46:19.55#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.01:46:19.55#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.01:46:19.55#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.01:46:19.55#ibcon#enter wrdev, iclass 6, count 0 2006.173.01:46:19.55#ibcon#first serial, iclass 6, count 0 2006.173.01:46:19.55#ibcon#enter sib2, iclass 6, count 0 2006.173.01:46:19.55#ibcon#flushed, iclass 6, count 0 2006.173.01:46:19.55#ibcon#about to write, iclass 6, count 0 2006.173.01:46:19.55#ibcon#wrote, iclass 6, count 0 2006.173.01:46:19.55#ibcon#about to read 3, iclass 6, count 0 2006.173.01:46:19.57#ibcon#read 3, iclass 6, count 0 2006.173.01:46:19.57#ibcon#about to read 4, iclass 6, count 0 2006.173.01:46:19.57#ibcon#read 4, iclass 6, count 0 2006.173.01:46:19.57#ibcon#about to read 5, iclass 6, count 0 2006.173.01:46:19.57#ibcon#read 5, iclass 6, count 0 2006.173.01:46:19.57#ibcon#about to read 6, iclass 6, count 0 2006.173.01:46:19.57#ibcon#read 6, iclass 6, count 0 2006.173.01:46:19.57#ibcon#end of sib2, iclass 6, count 0 2006.173.01:46:19.57#ibcon#*mode == 0, iclass 6, count 0 2006.173.01:46:19.57#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.01:46:19.57#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.01:46:19.57#ibcon#*before write, iclass 6, count 0 2006.173.01:46:19.57#ibcon#enter sib2, iclass 6, count 0 2006.173.01:46:19.57#ibcon#flushed, iclass 6, count 0 2006.173.01:46:19.57#ibcon#about to write, iclass 6, count 0 2006.173.01:46:19.57#ibcon#wrote, iclass 6, count 0 2006.173.01:46:19.57#ibcon#about to read 3, iclass 6, count 0 2006.173.01:46:19.61#ibcon#read 3, iclass 6, count 0 2006.173.01:46:19.61#ibcon#about to read 4, iclass 6, count 0 2006.173.01:46:19.61#ibcon#read 4, iclass 6, count 0 2006.173.01:46:19.61#ibcon#about to read 5, iclass 6, count 0 2006.173.01:46:19.61#ibcon#read 5, iclass 6, count 0 2006.173.01:46:19.61#ibcon#about to read 6, iclass 6, count 0 2006.173.01:46:19.61#ibcon#read 6, iclass 6, count 0 2006.173.01:46:19.61#ibcon#end of sib2, iclass 6, count 0 2006.173.01:46:19.61#ibcon#*after write, iclass 6, count 0 2006.173.01:46:19.61#ibcon#*before return 0, iclass 6, count 0 2006.173.01:46:19.61#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.01:46:19.61#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.01:46:19.61#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.01:46:19.61#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.01:46:19.61$vck44/va=3,5 2006.173.01:46:19.61#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.01:46:19.61#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.01:46:19.61#ibcon#ireg 11 cls_cnt 2 2006.173.01:46:19.61#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.01:46:19.67#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.01:46:19.67#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.01:46:19.67#ibcon#enter wrdev, iclass 10, count 2 2006.173.01:46:19.67#ibcon#first serial, iclass 10, count 2 2006.173.01:46:19.67#ibcon#enter sib2, iclass 10, count 2 2006.173.01:46:19.67#ibcon#flushed, iclass 10, count 2 2006.173.01:46:19.67#ibcon#about to write, iclass 10, count 2 2006.173.01:46:19.67#ibcon#wrote, iclass 10, count 2 2006.173.01:46:19.67#ibcon#about to read 3, iclass 10, count 2 2006.173.01:46:19.69#ibcon#read 3, iclass 10, count 2 2006.173.01:46:19.69#ibcon#about to read 4, iclass 10, count 2 2006.173.01:46:19.69#ibcon#read 4, iclass 10, count 2 2006.173.01:46:19.69#ibcon#about to read 5, iclass 10, count 2 2006.173.01:46:19.69#ibcon#read 5, iclass 10, count 2 2006.173.01:46:19.69#ibcon#about to read 6, iclass 10, count 2 2006.173.01:46:19.69#ibcon#read 6, iclass 10, count 2 2006.173.01:46:19.69#ibcon#end of sib2, iclass 10, count 2 2006.173.01:46:19.69#ibcon#*mode == 0, iclass 10, count 2 2006.173.01:46:19.69#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.01:46:19.69#ibcon#[25=AT03-05\r\n] 2006.173.01:46:19.69#ibcon#*before write, iclass 10, count 2 2006.173.01:46:19.69#ibcon#enter sib2, iclass 10, count 2 2006.173.01:46:19.69#ibcon#flushed, iclass 10, count 2 2006.173.01:46:19.69#ibcon#about to write, iclass 10, count 2 2006.173.01:46:19.69#ibcon#wrote, iclass 10, count 2 2006.173.01:46:19.69#ibcon#about to read 3, iclass 10, count 2 2006.173.01:46:19.72#ibcon#read 3, iclass 10, count 2 2006.173.01:46:19.72#ibcon#about to read 4, iclass 10, count 2 2006.173.01:46:19.72#ibcon#read 4, iclass 10, count 2 2006.173.01:46:19.72#ibcon#about to read 5, iclass 10, count 2 2006.173.01:46:19.72#ibcon#read 5, iclass 10, count 2 2006.173.01:46:19.72#ibcon#about to read 6, iclass 10, count 2 2006.173.01:46:19.72#ibcon#read 6, iclass 10, count 2 2006.173.01:46:19.72#ibcon#end of sib2, iclass 10, count 2 2006.173.01:46:19.72#ibcon#*after write, iclass 10, count 2 2006.173.01:46:19.72#ibcon#*before return 0, iclass 10, count 2 2006.173.01:46:19.72#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.01:46:19.72#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.01:46:19.72#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.01:46:19.72#ibcon#ireg 7 cls_cnt 0 2006.173.01:46:19.72#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.01:46:19.84#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.01:46:19.84#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.01:46:19.84#ibcon#enter wrdev, iclass 10, count 0 2006.173.01:46:19.84#ibcon#first serial, iclass 10, count 0 2006.173.01:46:19.84#ibcon#enter sib2, iclass 10, count 0 2006.173.01:46:19.84#ibcon#flushed, iclass 10, count 0 2006.173.01:46:19.84#ibcon#about to write, iclass 10, count 0 2006.173.01:46:19.84#ibcon#wrote, iclass 10, count 0 2006.173.01:46:19.84#ibcon#about to read 3, iclass 10, count 0 2006.173.01:46:19.86#ibcon#read 3, iclass 10, count 0 2006.173.01:46:19.86#ibcon#about to read 4, iclass 10, count 0 2006.173.01:46:19.86#ibcon#read 4, iclass 10, count 0 2006.173.01:46:19.86#ibcon#about to read 5, iclass 10, count 0 2006.173.01:46:19.86#ibcon#read 5, iclass 10, count 0 2006.173.01:46:19.86#ibcon#about to read 6, iclass 10, count 0 2006.173.01:46:19.86#ibcon#read 6, iclass 10, count 0 2006.173.01:46:19.86#ibcon#end of sib2, iclass 10, count 0 2006.173.01:46:19.86#ibcon#*mode == 0, iclass 10, count 0 2006.173.01:46:19.86#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.01:46:19.86#ibcon#[25=USB\r\n] 2006.173.01:46:19.86#ibcon#*before write, iclass 10, count 0 2006.173.01:46:19.86#ibcon#enter sib2, iclass 10, count 0 2006.173.01:46:19.86#ibcon#flushed, iclass 10, count 0 2006.173.01:46:19.86#ibcon#about to write, iclass 10, count 0 2006.173.01:46:19.86#ibcon#wrote, iclass 10, count 0 2006.173.01:46:19.86#ibcon#about to read 3, iclass 10, count 0 2006.173.01:46:19.89#ibcon#read 3, iclass 10, count 0 2006.173.01:46:19.89#ibcon#about to read 4, iclass 10, count 0 2006.173.01:46:19.89#ibcon#read 4, iclass 10, count 0 2006.173.01:46:19.89#ibcon#about to read 5, iclass 10, count 0 2006.173.01:46:19.89#ibcon#read 5, iclass 10, count 0 2006.173.01:46:19.89#ibcon#about to read 6, iclass 10, count 0 2006.173.01:46:19.89#ibcon#read 6, iclass 10, count 0 2006.173.01:46:19.89#ibcon#end of sib2, iclass 10, count 0 2006.173.01:46:19.89#ibcon#*after write, iclass 10, count 0 2006.173.01:46:19.89#ibcon#*before return 0, iclass 10, count 0 2006.173.01:46:19.89#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.01:46:19.89#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.01:46:19.89#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.01:46:19.89#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.01:46:19.89$vck44/valo=4,624.99 2006.173.01:46:19.89#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.01:46:19.89#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.01:46:19.89#ibcon#ireg 17 cls_cnt 0 2006.173.01:46:19.89#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.01:46:19.89#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.01:46:19.89#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.01:46:19.89#ibcon#enter wrdev, iclass 12, count 0 2006.173.01:46:19.89#ibcon#first serial, iclass 12, count 0 2006.173.01:46:19.89#ibcon#enter sib2, iclass 12, count 0 2006.173.01:46:19.89#ibcon#flushed, iclass 12, count 0 2006.173.01:46:19.89#ibcon#about to write, iclass 12, count 0 2006.173.01:46:19.89#ibcon#wrote, iclass 12, count 0 2006.173.01:46:19.89#ibcon#about to read 3, iclass 12, count 0 2006.173.01:46:19.91#ibcon#read 3, iclass 12, count 0 2006.173.01:46:19.91#ibcon#about to read 4, iclass 12, count 0 2006.173.01:46:19.91#ibcon#read 4, iclass 12, count 0 2006.173.01:46:19.91#ibcon#about to read 5, iclass 12, count 0 2006.173.01:46:19.91#ibcon#read 5, iclass 12, count 0 2006.173.01:46:19.91#ibcon#about to read 6, iclass 12, count 0 2006.173.01:46:19.91#ibcon#read 6, iclass 12, count 0 2006.173.01:46:19.91#ibcon#end of sib2, iclass 12, count 0 2006.173.01:46:19.91#ibcon#*mode == 0, iclass 12, count 0 2006.173.01:46:19.91#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.01:46:19.91#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.01:46:19.91#ibcon#*before write, iclass 12, count 0 2006.173.01:46:19.91#ibcon#enter sib2, iclass 12, count 0 2006.173.01:46:19.91#ibcon#flushed, iclass 12, count 0 2006.173.01:46:19.91#ibcon#about to write, iclass 12, count 0 2006.173.01:46:19.91#ibcon#wrote, iclass 12, count 0 2006.173.01:46:19.91#ibcon#about to read 3, iclass 12, count 0 2006.173.01:46:19.95#ibcon#read 3, iclass 12, count 0 2006.173.01:46:19.95#ibcon#about to read 4, iclass 12, count 0 2006.173.01:46:19.95#ibcon#read 4, iclass 12, count 0 2006.173.01:46:19.95#ibcon#about to read 5, iclass 12, count 0 2006.173.01:46:19.95#ibcon#read 5, iclass 12, count 0 2006.173.01:46:19.95#ibcon#about to read 6, iclass 12, count 0 2006.173.01:46:19.95#ibcon#read 6, iclass 12, count 0 2006.173.01:46:19.95#ibcon#end of sib2, iclass 12, count 0 2006.173.01:46:19.95#ibcon#*after write, iclass 12, count 0 2006.173.01:46:19.95#ibcon#*before return 0, iclass 12, count 0 2006.173.01:46:19.95#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.01:46:19.95#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.01:46:19.95#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.01:46:19.95#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.01:46:19.95$vck44/va=4,6 2006.173.01:46:19.95#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.01:46:19.95#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.01:46:19.95#ibcon#ireg 11 cls_cnt 2 2006.173.01:46:19.95#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.01:46:20.02#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.01:46:20.02#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.01:46:20.02#ibcon#enter wrdev, iclass 14, count 2 2006.173.01:46:20.02#ibcon#first serial, iclass 14, count 2 2006.173.01:46:20.02#ibcon#enter sib2, iclass 14, count 2 2006.173.01:46:20.02#ibcon#flushed, iclass 14, count 2 2006.173.01:46:20.02#ibcon#about to write, iclass 14, count 2 2006.173.01:46:20.02#ibcon#wrote, iclass 14, count 2 2006.173.01:46:20.02#ibcon#about to read 3, iclass 14, count 2 2006.173.01:46:20.03#ibcon#read 3, iclass 14, count 2 2006.173.01:46:20.03#ibcon#about to read 4, iclass 14, count 2 2006.173.01:46:20.03#ibcon#read 4, iclass 14, count 2 2006.173.01:46:20.03#ibcon#about to read 5, iclass 14, count 2 2006.173.01:46:20.03#ibcon#read 5, iclass 14, count 2 2006.173.01:46:20.03#ibcon#about to read 6, iclass 14, count 2 2006.173.01:46:20.03#ibcon#read 6, iclass 14, count 2 2006.173.01:46:20.03#ibcon#end of sib2, iclass 14, count 2 2006.173.01:46:20.03#ibcon#*mode == 0, iclass 14, count 2 2006.173.01:46:20.03#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.01:46:20.03#ibcon#[25=AT04-06\r\n] 2006.173.01:46:20.03#ibcon#*before write, iclass 14, count 2 2006.173.01:46:20.03#ibcon#enter sib2, iclass 14, count 2 2006.173.01:46:20.03#ibcon#flushed, iclass 14, count 2 2006.173.01:46:20.03#ibcon#about to write, iclass 14, count 2 2006.173.01:46:20.03#ibcon#wrote, iclass 14, count 2 2006.173.01:46:20.03#ibcon#about to read 3, iclass 14, count 2 2006.173.01:46:20.06#ibcon#read 3, iclass 14, count 2 2006.173.01:46:20.06#ibcon#about to read 4, iclass 14, count 2 2006.173.01:46:20.06#ibcon#read 4, iclass 14, count 2 2006.173.01:46:20.06#ibcon#about to read 5, iclass 14, count 2 2006.173.01:46:20.06#ibcon#read 5, iclass 14, count 2 2006.173.01:46:20.06#ibcon#about to read 6, iclass 14, count 2 2006.173.01:46:20.06#ibcon#read 6, iclass 14, count 2 2006.173.01:46:20.06#ibcon#end of sib2, iclass 14, count 2 2006.173.01:46:20.06#ibcon#*after write, iclass 14, count 2 2006.173.01:46:20.06#ibcon#*before return 0, iclass 14, count 2 2006.173.01:46:20.06#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.01:46:20.06#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.01:46:20.06#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.01:46:20.06#ibcon#ireg 7 cls_cnt 0 2006.173.01:46:20.06#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.01:46:20.18#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.01:46:20.18#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.01:46:20.18#ibcon#enter wrdev, iclass 14, count 0 2006.173.01:46:20.18#ibcon#first serial, iclass 14, count 0 2006.173.01:46:20.18#ibcon#enter sib2, iclass 14, count 0 2006.173.01:46:20.18#ibcon#flushed, iclass 14, count 0 2006.173.01:46:20.18#ibcon#about to write, iclass 14, count 0 2006.173.01:46:20.18#ibcon#wrote, iclass 14, count 0 2006.173.01:46:20.18#ibcon#about to read 3, iclass 14, count 0 2006.173.01:46:20.20#ibcon#read 3, iclass 14, count 0 2006.173.01:46:20.20#ibcon#about to read 4, iclass 14, count 0 2006.173.01:46:20.20#ibcon#read 4, iclass 14, count 0 2006.173.01:46:20.20#ibcon#about to read 5, iclass 14, count 0 2006.173.01:46:20.20#ibcon#read 5, iclass 14, count 0 2006.173.01:46:20.20#ibcon#about to read 6, iclass 14, count 0 2006.173.01:46:20.20#ibcon#read 6, iclass 14, count 0 2006.173.01:46:20.20#ibcon#end of sib2, iclass 14, count 0 2006.173.01:46:20.20#ibcon#*mode == 0, iclass 14, count 0 2006.173.01:46:20.20#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.01:46:20.20#ibcon#[25=USB\r\n] 2006.173.01:46:20.20#ibcon#*before write, iclass 14, count 0 2006.173.01:46:20.20#ibcon#enter sib2, iclass 14, count 0 2006.173.01:46:20.20#ibcon#flushed, iclass 14, count 0 2006.173.01:46:20.20#ibcon#about to write, iclass 14, count 0 2006.173.01:46:20.20#ibcon#wrote, iclass 14, count 0 2006.173.01:46:20.20#ibcon#about to read 3, iclass 14, count 0 2006.173.01:46:20.23#ibcon#read 3, iclass 14, count 0 2006.173.01:46:20.23#ibcon#about to read 4, iclass 14, count 0 2006.173.01:46:20.23#ibcon#read 4, iclass 14, count 0 2006.173.01:46:20.23#ibcon#about to read 5, iclass 14, count 0 2006.173.01:46:20.23#ibcon#read 5, iclass 14, count 0 2006.173.01:46:20.23#ibcon#about to read 6, iclass 14, count 0 2006.173.01:46:20.23#ibcon#read 6, iclass 14, count 0 2006.173.01:46:20.23#ibcon#end of sib2, iclass 14, count 0 2006.173.01:46:20.23#ibcon#*after write, iclass 14, count 0 2006.173.01:46:20.23#ibcon#*before return 0, iclass 14, count 0 2006.173.01:46:20.23#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.01:46:20.23#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.01:46:20.23#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.01:46:20.23#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.01:46:20.23$vck44/valo=5,734.99 2006.173.01:46:20.23#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.01:46:20.23#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.01:46:20.23#ibcon#ireg 17 cls_cnt 0 2006.173.01:46:20.23#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.01:46:20.23#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.01:46:20.23#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.01:46:20.23#ibcon#enter wrdev, iclass 16, count 0 2006.173.01:46:20.23#ibcon#first serial, iclass 16, count 0 2006.173.01:46:20.23#ibcon#enter sib2, iclass 16, count 0 2006.173.01:46:20.23#ibcon#flushed, iclass 16, count 0 2006.173.01:46:20.23#ibcon#about to write, iclass 16, count 0 2006.173.01:46:20.23#ibcon#wrote, iclass 16, count 0 2006.173.01:46:20.23#ibcon#about to read 3, iclass 16, count 0 2006.173.01:46:20.25#ibcon#read 3, iclass 16, count 0 2006.173.01:46:20.25#ibcon#about to read 4, iclass 16, count 0 2006.173.01:46:20.25#ibcon#read 4, iclass 16, count 0 2006.173.01:46:20.25#ibcon#about to read 5, iclass 16, count 0 2006.173.01:46:20.25#ibcon#read 5, iclass 16, count 0 2006.173.01:46:20.25#ibcon#about to read 6, iclass 16, count 0 2006.173.01:46:20.25#ibcon#read 6, iclass 16, count 0 2006.173.01:46:20.25#ibcon#end of sib2, iclass 16, count 0 2006.173.01:46:20.25#ibcon#*mode == 0, iclass 16, count 0 2006.173.01:46:20.25#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.01:46:20.25#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.01:46:20.25#ibcon#*before write, iclass 16, count 0 2006.173.01:46:20.25#ibcon#enter sib2, iclass 16, count 0 2006.173.01:46:20.25#ibcon#flushed, iclass 16, count 0 2006.173.01:46:20.25#ibcon#about to write, iclass 16, count 0 2006.173.01:46:20.25#ibcon#wrote, iclass 16, count 0 2006.173.01:46:20.25#ibcon#about to read 3, iclass 16, count 0 2006.173.01:46:20.29#ibcon#read 3, iclass 16, count 0 2006.173.01:46:20.29#ibcon#about to read 4, iclass 16, count 0 2006.173.01:46:20.29#ibcon#read 4, iclass 16, count 0 2006.173.01:46:20.29#ibcon#about to read 5, iclass 16, count 0 2006.173.01:46:20.29#ibcon#read 5, iclass 16, count 0 2006.173.01:46:20.29#ibcon#about to read 6, iclass 16, count 0 2006.173.01:46:20.29#ibcon#read 6, iclass 16, count 0 2006.173.01:46:20.29#ibcon#end of sib2, iclass 16, count 0 2006.173.01:46:20.29#ibcon#*after write, iclass 16, count 0 2006.173.01:46:20.29#ibcon#*before return 0, iclass 16, count 0 2006.173.01:46:20.29#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.01:46:20.29#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.01:46:20.29#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.01:46:20.29#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.01:46:20.29$vck44/va=5,4 2006.173.01:46:20.29#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.01:46:20.29#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.01:46:20.29#ibcon#ireg 11 cls_cnt 2 2006.173.01:46:20.29#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.01:46:20.35#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.01:46:20.35#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.01:46:20.35#ibcon#enter wrdev, iclass 18, count 2 2006.173.01:46:20.35#ibcon#first serial, iclass 18, count 2 2006.173.01:46:20.35#ibcon#enter sib2, iclass 18, count 2 2006.173.01:46:20.35#ibcon#flushed, iclass 18, count 2 2006.173.01:46:20.35#ibcon#about to write, iclass 18, count 2 2006.173.01:46:20.35#ibcon#wrote, iclass 18, count 2 2006.173.01:46:20.35#ibcon#about to read 3, iclass 18, count 2 2006.173.01:46:20.37#ibcon#read 3, iclass 18, count 2 2006.173.01:46:20.37#ibcon#about to read 4, iclass 18, count 2 2006.173.01:46:20.37#ibcon#read 4, iclass 18, count 2 2006.173.01:46:20.37#ibcon#about to read 5, iclass 18, count 2 2006.173.01:46:20.37#ibcon#read 5, iclass 18, count 2 2006.173.01:46:20.37#ibcon#about to read 6, iclass 18, count 2 2006.173.01:46:20.37#ibcon#read 6, iclass 18, count 2 2006.173.01:46:20.37#ibcon#end of sib2, iclass 18, count 2 2006.173.01:46:20.37#ibcon#*mode == 0, iclass 18, count 2 2006.173.01:46:20.37#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.01:46:20.37#ibcon#[25=AT05-04\r\n] 2006.173.01:46:20.37#ibcon#*before write, iclass 18, count 2 2006.173.01:46:20.37#ibcon#enter sib2, iclass 18, count 2 2006.173.01:46:20.37#ibcon#flushed, iclass 18, count 2 2006.173.01:46:20.37#ibcon#about to write, iclass 18, count 2 2006.173.01:46:20.37#ibcon#wrote, iclass 18, count 2 2006.173.01:46:20.37#ibcon#about to read 3, iclass 18, count 2 2006.173.01:46:20.40#ibcon#read 3, iclass 18, count 2 2006.173.01:46:20.40#ibcon#about to read 4, iclass 18, count 2 2006.173.01:46:20.40#ibcon#read 4, iclass 18, count 2 2006.173.01:46:20.40#ibcon#about to read 5, iclass 18, count 2 2006.173.01:46:20.40#ibcon#read 5, iclass 18, count 2 2006.173.01:46:20.40#ibcon#about to read 6, iclass 18, count 2 2006.173.01:46:20.40#ibcon#read 6, iclass 18, count 2 2006.173.01:46:20.40#ibcon#end of sib2, iclass 18, count 2 2006.173.01:46:20.40#ibcon#*after write, iclass 18, count 2 2006.173.01:46:20.40#ibcon#*before return 0, iclass 18, count 2 2006.173.01:46:20.40#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.01:46:20.40#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.01:46:20.40#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.01:46:20.40#ibcon#ireg 7 cls_cnt 0 2006.173.01:46:20.40#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.01:46:20.52#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.01:46:20.52#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.01:46:20.52#ibcon#enter wrdev, iclass 18, count 0 2006.173.01:46:20.52#ibcon#first serial, iclass 18, count 0 2006.173.01:46:20.52#ibcon#enter sib2, iclass 18, count 0 2006.173.01:46:20.52#ibcon#flushed, iclass 18, count 0 2006.173.01:46:20.52#ibcon#about to write, iclass 18, count 0 2006.173.01:46:20.52#ibcon#wrote, iclass 18, count 0 2006.173.01:46:20.52#ibcon#about to read 3, iclass 18, count 0 2006.173.01:46:20.54#ibcon#read 3, iclass 18, count 0 2006.173.01:46:20.54#ibcon#about to read 4, iclass 18, count 0 2006.173.01:46:20.54#ibcon#read 4, iclass 18, count 0 2006.173.01:46:20.54#ibcon#about to read 5, iclass 18, count 0 2006.173.01:46:20.54#ibcon#read 5, iclass 18, count 0 2006.173.01:46:20.54#ibcon#about to read 6, iclass 18, count 0 2006.173.01:46:20.54#ibcon#read 6, iclass 18, count 0 2006.173.01:46:20.54#ibcon#end of sib2, iclass 18, count 0 2006.173.01:46:20.54#ibcon#*mode == 0, iclass 18, count 0 2006.173.01:46:20.54#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.01:46:20.54#ibcon#[25=USB\r\n] 2006.173.01:46:20.54#ibcon#*before write, iclass 18, count 0 2006.173.01:46:20.54#ibcon#enter sib2, iclass 18, count 0 2006.173.01:46:20.54#ibcon#flushed, iclass 18, count 0 2006.173.01:46:20.54#ibcon#about to write, iclass 18, count 0 2006.173.01:46:20.54#ibcon#wrote, iclass 18, count 0 2006.173.01:46:20.54#ibcon#about to read 3, iclass 18, count 0 2006.173.01:46:20.57#ibcon#read 3, iclass 18, count 0 2006.173.01:46:20.57#ibcon#about to read 4, iclass 18, count 0 2006.173.01:46:20.57#ibcon#read 4, iclass 18, count 0 2006.173.01:46:20.57#ibcon#about to read 5, iclass 18, count 0 2006.173.01:46:20.57#ibcon#read 5, iclass 18, count 0 2006.173.01:46:20.57#ibcon#about to read 6, iclass 18, count 0 2006.173.01:46:20.57#ibcon#read 6, iclass 18, count 0 2006.173.01:46:20.57#ibcon#end of sib2, iclass 18, count 0 2006.173.01:46:20.57#ibcon#*after write, iclass 18, count 0 2006.173.01:46:20.57#ibcon#*before return 0, iclass 18, count 0 2006.173.01:46:20.57#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.01:46:20.57#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.01:46:20.57#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.01:46:20.57#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.01:46:20.57$vck44/valo=6,814.99 2006.173.01:46:20.57#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.01:46:20.57#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.01:46:20.57#ibcon#ireg 17 cls_cnt 0 2006.173.01:46:20.57#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.01:46:20.57#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.01:46:20.57#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.01:46:20.57#ibcon#enter wrdev, iclass 20, count 0 2006.173.01:46:20.57#ibcon#first serial, iclass 20, count 0 2006.173.01:46:20.57#ibcon#enter sib2, iclass 20, count 0 2006.173.01:46:20.57#ibcon#flushed, iclass 20, count 0 2006.173.01:46:20.57#ibcon#about to write, iclass 20, count 0 2006.173.01:46:20.57#ibcon#wrote, iclass 20, count 0 2006.173.01:46:20.57#ibcon#about to read 3, iclass 20, count 0 2006.173.01:46:20.59#ibcon#read 3, iclass 20, count 0 2006.173.01:46:20.59#ibcon#about to read 4, iclass 20, count 0 2006.173.01:46:20.59#ibcon#read 4, iclass 20, count 0 2006.173.01:46:20.59#ibcon#about to read 5, iclass 20, count 0 2006.173.01:46:20.59#ibcon#read 5, iclass 20, count 0 2006.173.01:46:20.59#ibcon#about to read 6, iclass 20, count 0 2006.173.01:46:20.59#ibcon#read 6, iclass 20, count 0 2006.173.01:46:20.59#ibcon#end of sib2, iclass 20, count 0 2006.173.01:46:20.59#ibcon#*mode == 0, iclass 20, count 0 2006.173.01:46:20.59#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.01:46:20.59#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.01:46:20.59#ibcon#*before write, iclass 20, count 0 2006.173.01:46:20.59#ibcon#enter sib2, iclass 20, count 0 2006.173.01:46:20.59#ibcon#flushed, iclass 20, count 0 2006.173.01:46:20.59#ibcon#about to write, iclass 20, count 0 2006.173.01:46:20.59#ibcon#wrote, iclass 20, count 0 2006.173.01:46:20.59#ibcon#about to read 3, iclass 20, count 0 2006.173.01:46:20.63#ibcon#read 3, iclass 20, count 0 2006.173.01:46:20.63#ibcon#about to read 4, iclass 20, count 0 2006.173.01:46:20.63#ibcon#read 4, iclass 20, count 0 2006.173.01:46:20.63#ibcon#about to read 5, iclass 20, count 0 2006.173.01:46:20.63#ibcon#read 5, iclass 20, count 0 2006.173.01:46:20.63#ibcon#about to read 6, iclass 20, count 0 2006.173.01:46:20.63#ibcon#read 6, iclass 20, count 0 2006.173.01:46:20.63#ibcon#end of sib2, iclass 20, count 0 2006.173.01:46:20.63#ibcon#*after write, iclass 20, count 0 2006.173.01:46:20.63#ibcon#*before return 0, iclass 20, count 0 2006.173.01:46:20.63#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.01:46:20.63#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.01:46:20.63#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.01:46:20.63#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.01:46:20.63$vck44/va=6,3 2006.173.01:46:20.63#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.01:46:20.63#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.01:46:20.63#ibcon#ireg 11 cls_cnt 2 2006.173.01:46:20.63#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.01:46:20.69#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.01:46:20.69#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.01:46:20.69#ibcon#enter wrdev, iclass 22, count 2 2006.173.01:46:20.69#ibcon#first serial, iclass 22, count 2 2006.173.01:46:20.69#ibcon#enter sib2, iclass 22, count 2 2006.173.01:46:20.69#ibcon#flushed, iclass 22, count 2 2006.173.01:46:20.69#ibcon#about to write, iclass 22, count 2 2006.173.01:46:20.69#ibcon#wrote, iclass 22, count 2 2006.173.01:46:20.69#ibcon#about to read 3, iclass 22, count 2 2006.173.01:46:20.71#ibcon#read 3, iclass 22, count 2 2006.173.01:46:20.71#ibcon#about to read 4, iclass 22, count 2 2006.173.01:46:20.71#ibcon#read 4, iclass 22, count 2 2006.173.01:46:20.71#ibcon#about to read 5, iclass 22, count 2 2006.173.01:46:20.71#ibcon#read 5, iclass 22, count 2 2006.173.01:46:20.71#ibcon#about to read 6, iclass 22, count 2 2006.173.01:46:20.71#ibcon#read 6, iclass 22, count 2 2006.173.01:46:20.71#ibcon#end of sib2, iclass 22, count 2 2006.173.01:46:20.71#ibcon#*mode == 0, iclass 22, count 2 2006.173.01:46:20.71#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.01:46:20.71#ibcon#[25=AT06-03\r\n] 2006.173.01:46:20.71#ibcon#*before write, iclass 22, count 2 2006.173.01:46:20.71#ibcon#enter sib2, iclass 22, count 2 2006.173.01:46:20.71#ibcon#flushed, iclass 22, count 2 2006.173.01:46:20.71#ibcon#about to write, iclass 22, count 2 2006.173.01:46:20.71#ibcon#wrote, iclass 22, count 2 2006.173.01:46:20.71#ibcon#about to read 3, iclass 22, count 2 2006.173.01:46:20.74#ibcon#read 3, iclass 22, count 2 2006.173.01:46:20.74#ibcon#about to read 4, iclass 22, count 2 2006.173.01:46:20.74#ibcon#read 4, iclass 22, count 2 2006.173.01:46:20.74#ibcon#about to read 5, iclass 22, count 2 2006.173.01:46:20.74#ibcon#read 5, iclass 22, count 2 2006.173.01:46:20.74#ibcon#about to read 6, iclass 22, count 2 2006.173.01:46:20.74#ibcon#read 6, iclass 22, count 2 2006.173.01:46:20.74#ibcon#end of sib2, iclass 22, count 2 2006.173.01:46:20.74#ibcon#*after write, iclass 22, count 2 2006.173.01:46:20.74#ibcon#*before return 0, iclass 22, count 2 2006.173.01:46:20.74#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.01:46:20.74#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.01:46:20.74#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.01:46:20.74#ibcon#ireg 7 cls_cnt 0 2006.173.01:46:20.74#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.01:46:20.86#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.01:46:20.86#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.01:46:20.86#ibcon#enter wrdev, iclass 22, count 0 2006.173.01:46:20.86#ibcon#first serial, iclass 22, count 0 2006.173.01:46:20.86#ibcon#enter sib2, iclass 22, count 0 2006.173.01:46:20.86#ibcon#flushed, iclass 22, count 0 2006.173.01:46:20.86#ibcon#about to write, iclass 22, count 0 2006.173.01:46:20.86#ibcon#wrote, iclass 22, count 0 2006.173.01:46:20.86#ibcon#about to read 3, iclass 22, count 0 2006.173.01:46:20.88#ibcon#read 3, iclass 22, count 0 2006.173.01:46:20.88#ibcon#about to read 4, iclass 22, count 0 2006.173.01:46:20.88#ibcon#read 4, iclass 22, count 0 2006.173.01:46:20.88#ibcon#about to read 5, iclass 22, count 0 2006.173.01:46:20.88#ibcon#read 5, iclass 22, count 0 2006.173.01:46:20.88#ibcon#about to read 6, iclass 22, count 0 2006.173.01:46:20.88#ibcon#read 6, iclass 22, count 0 2006.173.01:46:20.88#ibcon#end of sib2, iclass 22, count 0 2006.173.01:46:20.88#ibcon#*mode == 0, iclass 22, count 0 2006.173.01:46:20.88#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.01:46:20.88#ibcon#[25=USB\r\n] 2006.173.01:46:20.88#ibcon#*before write, iclass 22, count 0 2006.173.01:46:20.88#ibcon#enter sib2, iclass 22, count 0 2006.173.01:46:20.88#ibcon#flushed, iclass 22, count 0 2006.173.01:46:20.88#ibcon#about to write, iclass 22, count 0 2006.173.01:46:20.88#ibcon#wrote, iclass 22, count 0 2006.173.01:46:20.88#ibcon#about to read 3, iclass 22, count 0 2006.173.01:46:20.91#ibcon#read 3, iclass 22, count 0 2006.173.01:46:20.91#ibcon#about to read 4, iclass 22, count 0 2006.173.01:46:20.91#ibcon#read 4, iclass 22, count 0 2006.173.01:46:20.91#ibcon#about to read 5, iclass 22, count 0 2006.173.01:46:20.91#ibcon#read 5, iclass 22, count 0 2006.173.01:46:20.91#ibcon#about to read 6, iclass 22, count 0 2006.173.01:46:20.91#ibcon#read 6, iclass 22, count 0 2006.173.01:46:20.91#ibcon#end of sib2, iclass 22, count 0 2006.173.01:46:20.91#ibcon#*after write, iclass 22, count 0 2006.173.01:46:20.91#ibcon#*before return 0, iclass 22, count 0 2006.173.01:46:20.91#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.01:46:20.91#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.01:46:20.91#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.01:46:20.91#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.01:46:20.91$vck44/valo=7,864.99 2006.173.01:46:20.91#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.01:46:20.91#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.01:46:20.91#ibcon#ireg 17 cls_cnt 0 2006.173.01:46:20.91#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.01:46:20.91#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.01:46:20.91#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.01:46:20.91#ibcon#enter wrdev, iclass 24, count 0 2006.173.01:46:20.91#ibcon#first serial, iclass 24, count 0 2006.173.01:46:20.91#ibcon#enter sib2, iclass 24, count 0 2006.173.01:46:20.91#ibcon#flushed, iclass 24, count 0 2006.173.01:46:20.91#ibcon#about to write, iclass 24, count 0 2006.173.01:46:20.91#ibcon#wrote, iclass 24, count 0 2006.173.01:46:20.91#ibcon#about to read 3, iclass 24, count 0 2006.173.01:46:20.93#ibcon#read 3, iclass 24, count 0 2006.173.01:46:20.93#ibcon#about to read 4, iclass 24, count 0 2006.173.01:46:20.93#ibcon#read 4, iclass 24, count 0 2006.173.01:46:20.93#ibcon#about to read 5, iclass 24, count 0 2006.173.01:46:20.93#ibcon#read 5, iclass 24, count 0 2006.173.01:46:20.93#ibcon#about to read 6, iclass 24, count 0 2006.173.01:46:20.93#ibcon#read 6, iclass 24, count 0 2006.173.01:46:20.93#ibcon#end of sib2, iclass 24, count 0 2006.173.01:46:20.93#ibcon#*mode == 0, iclass 24, count 0 2006.173.01:46:20.93#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.01:46:20.93#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.01:46:20.93#ibcon#*before write, iclass 24, count 0 2006.173.01:46:20.93#ibcon#enter sib2, iclass 24, count 0 2006.173.01:46:20.93#ibcon#flushed, iclass 24, count 0 2006.173.01:46:20.93#ibcon#about to write, iclass 24, count 0 2006.173.01:46:20.93#ibcon#wrote, iclass 24, count 0 2006.173.01:46:20.93#ibcon#about to read 3, iclass 24, count 0 2006.173.01:46:20.97#ibcon#read 3, iclass 24, count 0 2006.173.01:46:20.97#ibcon#about to read 4, iclass 24, count 0 2006.173.01:46:20.97#ibcon#read 4, iclass 24, count 0 2006.173.01:46:20.97#ibcon#about to read 5, iclass 24, count 0 2006.173.01:46:20.97#ibcon#read 5, iclass 24, count 0 2006.173.01:46:20.97#ibcon#about to read 6, iclass 24, count 0 2006.173.01:46:20.97#ibcon#read 6, iclass 24, count 0 2006.173.01:46:20.97#ibcon#end of sib2, iclass 24, count 0 2006.173.01:46:20.97#ibcon#*after write, iclass 24, count 0 2006.173.01:46:20.97#ibcon#*before return 0, iclass 24, count 0 2006.173.01:46:20.97#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.01:46:20.97#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.01:46:20.97#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.01:46:20.97#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.01:46:20.97$vck44/va=7,4 2006.173.01:46:20.97#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.01:46:20.97#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.01:46:20.97#ibcon#ireg 11 cls_cnt 2 2006.173.01:46:20.97#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.01:46:21.03#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.01:46:21.03#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.01:46:21.03#ibcon#enter wrdev, iclass 26, count 2 2006.173.01:46:21.03#ibcon#first serial, iclass 26, count 2 2006.173.01:46:21.03#ibcon#enter sib2, iclass 26, count 2 2006.173.01:46:21.03#ibcon#flushed, iclass 26, count 2 2006.173.01:46:21.03#ibcon#about to write, iclass 26, count 2 2006.173.01:46:21.03#ibcon#wrote, iclass 26, count 2 2006.173.01:46:21.03#ibcon#about to read 3, iclass 26, count 2 2006.173.01:46:21.05#ibcon#read 3, iclass 26, count 2 2006.173.01:46:21.05#ibcon#about to read 4, iclass 26, count 2 2006.173.01:46:21.05#ibcon#read 4, iclass 26, count 2 2006.173.01:46:21.05#ibcon#about to read 5, iclass 26, count 2 2006.173.01:46:21.05#ibcon#read 5, iclass 26, count 2 2006.173.01:46:21.05#ibcon#about to read 6, iclass 26, count 2 2006.173.01:46:21.05#ibcon#read 6, iclass 26, count 2 2006.173.01:46:21.05#ibcon#end of sib2, iclass 26, count 2 2006.173.01:46:21.05#ibcon#*mode == 0, iclass 26, count 2 2006.173.01:46:21.05#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.01:46:21.05#ibcon#[25=AT07-04\r\n] 2006.173.01:46:21.05#ibcon#*before write, iclass 26, count 2 2006.173.01:46:21.05#ibcon#enter sib2, iclass 26, count 2 2006.173.01:46:21.05#ibcon#flushed, iclass 26, count 2 2006.173.01:46:21.05#ibcon#about to write, iclass 26, count 2 2006.173.01:46:21.05#ibcon#wrote, iclass 26, count 2 2006.173.01:46:21.05#ibcon#about to read 3, iclass 26, count 2 2006.173.01:46:21.08#ibcon#read 3, iclass 26, count 2 2006.173.01:46:21.08#ibcon#about to read 4, iclass 26, count 2 2006.173.01:46:21.08#ibcon#read 4, iclass 26, count 2 2006.173.01:46:21.08#ibcon#about to read 5, iclass 26, count 2 2006.173.01:46:21.08#ibcon#read 5, iclass 26, count 2 2006.173.01:46:21.08#ibcon#about to read 6, iclass 26, count 2 2006.173.01:46:21.08#ibcon#read 6, iclass 26, count 2 2006.173.01:46:21.08#ibcon#end of sib2, iclass 26, count 2 2006.173.01:46:21.08#ibcon#*after write, iclass 26, count 2 2006.173.01:46:21.08#ibcon#*before return 0, iclass 26, count 2 2006.173.01:46:21.08#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.01:46:21.08#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.01:46:21.08#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.01:46:21.08#ibcon#ireg 7 cls_cnt 0 2006.173.01:46:21.08#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.01:46:21.20#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.01:46:21.20#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.01:46:21.20#ibcon#enter wrdev, iclass 26, count 0 2006.173.01:46:21.20#ibcon#first serial, iclass 26, count 0 2006.173.01:46:21.20#ibcon#enter sib2, iclass 26, count 0 2006.173.01:46:21.20#ibcon#flushed, iclass 26, count 0 2006.173.01:46:21.20#ibcon#about to write, iclass 26, count 0 2006.173.01:46:21.20#ibcon#wrote, iclass 26, count 0 2006.173.01:46:21.20#ibcon#about to read 3, iclass 26, count 0 2006.173.01:46:21.22#ibcon#read 3, iclass 26, count 0 2006.173.01:46:21.22#ibcon#about to read 4, iclass 26, count 0 2006.173.01:46:21.22#ibcon#read 4, iclass 26, count 0 2006.173.01:46:21.22#ibcon#about to read 5, iclass 26, count 0 2006.173.01:46:21.22#ibcon#read 5, iclass 26, count 0 2006.173.01:46:21.22#ibcon#about to read 6, iclass 26, count 0 2006.173.01:46:21.22#ibcon#read 6, iclass 26, count 0 2006.173.01:46:21.22#ibcon#end of sib2, iclass 26, count 0 2006.173.01:46:21.22#ibcon#*mode == 0, iclass 26, count 0 2006.173.01:46:21.22#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.01:46:21.22#ibcon#[25=USB\r\n] 2006.173.01:46:21.22#ibcon#*before write, iclass 26, count 0 2006.173.01:46:21.22#ibcon#enter sib2, iclass 26, count 0 2006.173.01:46:21.22#ibcon#flushed, iclass 26, count 0 2006.173.01:46:21.22#ibcon#about to write, iclass 26, count 0 2006.173.01:46:21.22#ibcon#wrote, iclass 26, count 0 2006.173.01:46:21.22#ibcon#about to read 3, iclass 26, count 0 2006.173.01:46:21.25#ibcon#read 3, iclass 26, count 0 2006.173.01:46:21.25#ibcon#about to read 4, iclass 26, count 0 2006.173.01:46:21.25#ibcon#read 4, iclass 26, count 0 2006.173.01:46:21.25#ibcon#about to read 5, iclass 26, count 0 2006.173.01:46:21.25#ibcon#read 5, iclass 26, count 0 2006.173.01:46:21.25#ibcon#about to read 6, iclass 26, count 0 2006.173.01:46:21.25#ibcon#read 6, iclass 26, count 0 2006.173.01:46:21.25#ibcon#end of sib2, iclass 26, count 0 2006.173.01:46:21.25#ibcon#*after write, iclass 26, count 0 2006.173.01:46:21.25#ibcon#*before return 0, iclass 26, count 0 2006.173.01:46:21.25#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.01:46:21.25#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.01:46:21.25#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.01:46:21.25#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.01:46:21.25$vck44/valo=8,884.99 2006.173.01:46:21.25#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.01:46:21.25#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.01:46:21.25#ibcon#ireg 17 cls_cnt 0 2006.173.01:46:21.25#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.01:46:21.25#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.01:46:21.25#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.01:46:21.25#ibcon#enter wrdev, iclass 28, count 0 2006.173.01:46:21.25#ibcon#first serial, iclass 28, count 0 2006.173.01:46:21.25#ibcon#enter sib2, iclass 28, count 0 2006.173.01:46:21.25#ibcon#flushed, iclass 28, count 0 2006.173.01:46:21.25#ibcon#about to write, iclass 28, count 0 2006.173.01:46:21.25#ibcon#wrote, iclass 28, count 0 2006.173.01:46:21.25#ibcon#about to read 3, iclass 28, count 0 2006.173.01:46:21.27#ibcon#read 3, iclass 28, count 0 2006.173.01:46:21.27#ibcon#about to read 4, iclass 28, count 0 2006.173.01:46:21.27#ibcon#read 4, iclass 28, count 0 2006.173.01:46:21.27#ibcon#about to read 5, iclass 28, count 0 2006.173.01:46:21.27#ibcon#read 5, iclass 28, count 0 2006.173.01:46:21.27#ibcon#about to read 6, iclass 28, count 0 2006.173.01:46:21.27#ibcon#read 6, iclass 28, count 0 2006.173.01:46:21.27#ibcon#end of sib2, iclass 28, count 0 2006.173.01:46:21.27#ibcon#*mode == 0, iclass 28, count 0 2006.173.01:46:21.27#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.01:46:21.27#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.01:46:21.27#ibcon#*before write, iclass 28, count 0 2006.173.01:46:21.27#ibcon#enter sib2, iclass 28, count 0 2006.173.01:46:21.27#ibcon#flushed, iclass 28, count 0 2006.173.01:46:21.27#ibcon#about to write, iclass 28, count 0 2006.173.01:46:21.27#ibcon#wrote, iclass 28, count 0 2006.173.01:46:21.27#ibcon#about to read 3, iclass 28, count 0 2006.173.01:46:21.31#ibcon#read 3, iclass 28, count 0 2006.173.01:46:21.31#ibcon#about to read 4, iclass 28, count 0 2006.173.01:46:21.31#ibcon#read 4, iclass 28, count 0 2006.173.01:46:21.31#ibcon#about to read 5, iclass 28, count 0 2006.173.01:46:21.31#ibcon#read 5, iclass 28, count 0 2006.173.01:46:21.31#ibcon#about to read 6, iclass 28, count 0 2006.173.01:46:21.31#ibcon#read 6, iclass 28, count 0 2006.173.01:46:21.31#ibcon#end of sib2, iclass 28, count 0 2006.173.01:46:21.31#ibcon#*after write, iclass 28, count 0 2006.173.01:46:21.31#ibcon#*before return 0, iclass 28, count 0 2006.173.01:46:21.31#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.01:46:21.31#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.01:46:21.31#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.01:46:21.31#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.01:46:21.31$vck44/va=8,4 2006.173.01:46:21.31#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.01:46:21.31#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.01:46:21.31#ibcon#ireg 11 cls_cnt 2 2006.173.01:46:21.31#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.01:46:21.37#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.01:46:21.37#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.01:46:21.37#ibcon#enter wrdev, iclass 30, count 2 2006.173.01:46:21.37#ibcon#first serial, iclass 30, count 2 2006.173.01:46:21.37#ibcon#enter sib2, iclass 30, count 2 2006.173.01:46:21.37#ibcon#flushed, iclass 30, count 2 2006.173.01:46:21.37#ibcon#about to write, iclass 30, count 2 2006.173.01:46:21.37#ibcon#wrote, iclass 30, count 2 2006.173.01:46:21.37#ibcon#about to read 3, iclass 30, count 2 2006.173.01:46:21.39#ibcon#read 3, iclass 30, count 2 2006.173.01:46:21.39#ibcon#about to read 4, iclass 30, count 2 2006.173.01:46:21.39#ibcon#read 4, iclass 30, count 2 2006.173.01:46:21.39#ibcon#about to read 5, iclass 30, count 2 2006.173.01:46:21.39#ibcon#read 5, iclass 30, count 2 2006.173.01:46:21.39#ibcon#about to read 6, iclass 30, count 2 2006.173.01:46:21.39#ibcon#read 6, iclass 30, count 2 2006.173.01:46:21.39#ibcon#end of sib2, iclass 30, count 2 2006.173.01:46:21.39#ibcon#*mode == 0, iclass 30, count 2 2006.173.01:46:21.39#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.01:46:21.39#ibcon#[25=AT08-04\r\n] 2006.173.01:46:21.39#ibcon#*before write, iclass 30, count 2 2006.173.01:46:21.39#ibcon#enter sib2, iclass 30, count 2 2006.173.01:46:21.39#ibcon#flushed, iclass 30, count 2 2006.173.01:46:21.39#ibcon#about to write, iclass 30, count 2 2006.173.01:46:21.39#ibcon#wrote, iclass 30, count 2 2006.173.01:46:21.39#ibcon#about to read 3, iclass 30, count 2 2006.173.01:46:21.42#ibcon#read 3, iclass 30, count 2 2006.173.01:46:21.42#ibcon#about to read 4, iclass 30, count 2 2006.173.01:46:21.42#ibcon#read 4, iclass 30, count 2 2006.173.01:46:21.42#ibcon#about to read 5, iclass 30, count 2 2006.173.01:46:21.42#ibcon#read 5, iclass 30, count 2 2006.173.01:46:21.42#ibcon#about to read 6, iclass 30, count 2 2006.173.01:46:21.42#ibcon#read 6, iclass 30, count 2 2006.173.01:46:21.42#ibcon#end of sib2, iclass 30, count 2 2006.173.01:46:21.42#ibcon#*after write, iclass 30, count 2 2006.173.01:46:21.42#ibcon#*before return 0, iclass 30, count 2 2006.173.01:46:21.42#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.01:46:21.42#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.01:46:21.42#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.01:46:21.42#ibcon#ireg 7 cls_cnt 0 2006.173.01:46:21.42#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.01:46:21.54#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.01:46:21.54#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.01:46:21.54#ibcon#enter wrdev, iclass 30, count 0 2006.173.01:46:21.54#ibcon#first serial, iclass 30, count 0 2006.173.01:46:21.54#ibcon#enter sib2, iclass 30, count 0 2006.173.01:46:21.54#ibcon#flushed, iclass 30, count 0 2006.173.01:46:21.54#ibcon#about to write, iclass 30, count 0 2006.173.01:46:21.54#ibcon#wrote, iclass 30, count 0 2006.173.01:46:21.54#ibcon#about to read 3, iclass 30, count 0 2006.173.01:46:21.56#ibcon#read 3, iclass 30, count 0 2006.173.01:46:21.56#ibcon#about to read 4, iclass 30, count 0 2006.173.01:46:21.56#ibcon#read 4, iclass 30, count 0 2006.173.01:46:21.56#ibcon#about to read 5, iclass 30, count 0 2006.173.01:46:21.56#ibcon#read 5, iclass 30, count 0 2006.173.01:46:21.56#ibcon#about to read 6, iclass 30, count 0 2006.173.01:46:21.56#ibcon#read 6, iclass 30, count 0 2006.173.01:46:21.56#ibcon#end of sib2, iclass 30, count 0 2006.173.01:46:21.56#ibcon#*mode == 0, iclass 30, count 0 2006.173.01:46:21.56#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.01:46:21.56#ibcon#[25=USB\r\n] 2006.173.01:46:21.56#ibcon#*before write, iclass 30, count 0 2006.173.01:46:21.56#ibcon#enter sib2, iclass 30, count 0 2006.173.01:46:21.56#ibcon#flushed, iclass 30, count 0 2006.173.01:46:21.56#ibcon#about to write, iclass 30, count 0 2006.173.01:46:21.56#ibcon#wrote, iclass 30, count 0 2006.173.01:46:21.56#ibcon#about to read 3, iclass 30, count 0 2006.173.01:46:21.59#ibcon#read 3, iclass 30, count 0 2006.173.01:46:21.59#ibcon#about to read 4, iclass 30, count 0 2006.173.01:46:21.59#ibcon#read 4, iclass 30, count 0 2006.173.01:46:21.59#ibcon#about to read 5, iclass 30, count 0 2006.173.01:46:21.59#ibcon#read 5, iclass 30, count 0 2006.173.01:46:21.59#ibcon#about to read 6, iclass 30, count 0 2006.173.01:46:21.59#ibcon#read 6, iclass 30, count 0 2006.173.01:46:21.59#ibcon#end of sib2, iclass 30, count 0 2006.173.01:46:21.59#ibcon#*after write, iclass 30, count 0 2006.173.01:46:21.59#ibcon#*before return 0, iclass 30, count 0 2006.173.01:46:21.59#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.01:46:21.59#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.01:46:21.59#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.01:46:21.59#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.01:46:21.59$vck44/vblo=1,629.99 2006.173.01:46:21.59#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.01:46:21.59#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.01:46:21.59#ibcon#ireg 17 cls_cnt 0 2006.173.01:46:21.59#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.01:46:21.59#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.01:46:21.59#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.01:46:21.59#ibcon#enter wrdev, iclass 32, count 0 2006.173.01:46:21.59#ibcon#first serial, iclass 32, count 0 2006.173.01:46:21.59#ibcon#enter sib2, iclass 32, count 0 2006.173.01:46:21.59#ibcon#flushed, iclass 32, count 0 2006.173.01:46:21.59#ibcon#about to write, iclass 32, count 0 2006.173.01:46:21.59#ibcon#wrote, iclass 32, count 0 2006.173.01:46:21.59#ibcon#about to read 3, iclass 32, count 0 2006.173.01:46:21.61#ibcon#read 3, iclass 32, count 0 2006.173.01:46:21.61#ibcon#about to read 4, iclass 32, count 0 2006.173.01:46:21.61#ibcon#read 4, iclass 32, count 0 2006.173.01:46:21.61#ibcon#about to read 5, iclass 32, count 0 2006.173.01:46:21.61#ibcon#read 5, iclass 32, count 0 2006.173.01:46:21.61#ibcon#about to read 6, iclass 32, count 0 2006.173.01:46:21.61#ibcon#read 6, iclass 32, count 0 2006.173.01:46:21.61#ibcon#end of sib2, iclass 32, count 0 2006.173.01:46:21.61#ibcon#*mode == 0, iclass 32, count 0 2006.173.01:46:21.61#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.01:46:21.61#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.01:46:21.61#ibcon#*before write, iclass 32, count 0 2006.173.01:46:21.61#ibcon#enter sib2, iclass 32, count 0 2006.173.01:46:21.61#ibcon#flushed, iclass 32, count 0 2006.173.01:46:21.61#ibcon#about to write, iclass 32, count 0 2006.173.01:46:21.61#ibcon#wrote, iclass 32, count 0 2006.173.01:46:21.61#ibcon#about to read 3, iclass 32, count 0 2006.173.01:46:21.67#ibcon#read 3, iclass 32, count 0 2006.173.01:46:21.67#ibcon#about to read 4, iclass 32, count 0 2006.173.01:46:21.67#ibcon#read 4, iclass 32, count 0 2006.173.01:46:21.67#ibcon#about to read 5, iclass 32, count 0 2006.173.01:46:21.67#ibcon#read 5, iclass 32, count 0 2006.173.01:46:21.67#ibcon#about to read 6, iclass 32, count 0 2006.173.01:46:21.67#ibcon#read 6, iclass 32, count 0 2006.173.01:46:21.67#ibcon#end of sib2, iclass 32, count 0 2006.173.01:46:21.67#ibcon#*after write, iclass 32, count 0 2006.173.01:46:21.67#ibcon#*before return 0, iclass 32, count 0 2006.173.01:46:21.67#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.01:46:21.67#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.01:46:21.67#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.01:46:21.67#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.01:46:21.67$vck44/vb=1,4 2006.173.01:46:21.67#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.01:46:21.67#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.01:46:21.67#ibcon#ireg 11 cls_cnt 2 2006.173.01:46:21.67#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.01:46:21.67#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.01:46:21.67#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.01:46:21.67#ibcon#enter wrdev, iclass 34, count 2 2006.173.01:46:21.67#ibcon#first serial, iclass 34, count 2 2006.173.01:46:21.67#ibcon#enter sib2, iclass 34, count 2 2006.173.01:46:21.67#ibcon#flushed, iclass 34, count 2 2006.173.01:46:21.67#ibcon#about to write, iclass 34, count 2 2006.173.01:46:21.67#ibcon#wrote, iclass 34, count 2 2006.173.01:46:21.67#ibcon#about to read 3, iclass 34, count 2 2006.173.01:46:21.69#ibcon#read 3, iclass 34, count 2 2006.173.01:46:21.69#ibcon#about to read 4, iclass 34, count 2 2006.173.01:46:21.69#ibcon#read 4, iclass 34, count 2 2006.173.01:46:21.69#ibcon#about to read 5, iclass 34, count 2 2006.173.01:46:21.69#ibcon#read 5, iclass 34, count 2 2006.173.01:46:21.69#ibcon#about to read 6, iclass 34, count 2 2006.173.01:46:21.69#ibcon#read 6, iclass 34, count 2 2006.173.01:46:21.69#ibcon#end of sib2, iclass 34, count 2 2006.173.01:46:21.69#ibcon#*mode == 0, iclass 34, count 2 2006.173.01:46:21.69#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.01:46:21.69#ibcon#[27=AT01-04\r\n] 2006.173.01:46:21.69#ibcon#*before write, iclass 34, count 2 2006.173.01:46:21.69#ibcon#enter sib2, iclass 34, count 2 2006.173.01:46:21.69#ibcon#flushed, iclass 34, count 2 2006.173.01:46:21.69#ibcon#about to write, iclass 34, count 2 2006.173.01:46:21.69#ibcon#wrote, iclass 34, count 2 2006.173.01:46:21.69#ibcon#about to read 3, iclass 34, count 2 2006.173.01:46:21.73#ibcon#read 3, iclass 34, count 2 2006.173.01:46:21.73#ibcon#about to read 4, iclass 34, count 2 2006.173.01:46:21.73#ibcon#read 4, iclass 34, count 2 2006.173.01:46:21.73#ibcon#about to read 5, iclass 34, count 2 2006.173.01:46:21.73#ibcon#read 5, iclass 34, count 2 2006.173.01:46:21.73#ibcon#about to read 6, iclass 34, count 2 2006.173.01:46:21.73#ibcon#read 6, iclass 34, count 2 2006.173.01:46:21.73#ibcon#end of sib2, iclass 34, count 2 2006.173.01:46:21.73#ibcon#*after write, iclass 34, count 2 2006.173.01:46:21.73#ibcon#*before return 0, iclass 34, count 2 2006.173.01:46:21.73#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.01:46:21.73#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.01:46:21.73#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.01:46:21.73#ibcon#ireg 7 cls_cnt 0 2006.173.01:46:21.73#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.01:46:21.85#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.01:46:21.85#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.01:46:21.85#ibcon#enter wrdev, iclass 34, count 0 2006.173.01:46:21.85#ibcon#first serial, iclass 34, count 0 2006.173.01:46:21.85#ibcon#enter sib2, iclass 34, count 0 2006.173.01:46:21.85#ibcon#flushed, iclass 34, count 0 2006.173.01:46:21.85#ibcon#about to write, iclass 34, count 0 2006.173.01:46:21.85#ibcon#wrote, iclass 34, count 0 2006.173.01:46:21.85#ibcon#about to read 3, iclass 34, count 0 2006.173.01:46:21.87#ibcon#read 3, iclass 34, count 0 2006.173.01:46:21.87#ibcon#about to read 4, iclass 34, count 0 2006.173.01:46:21.87#ibcon#read 4, iclass 34, count 0 2006.173.01:46:21.87#ibcon#about to read 5, iclass 34, count 0 2006.173.01:46:21.87#ibcon#read 5, iclass 34, count 0 2006.173.01:46:21.87#ibcon#about to read 6, iclass 34, count 0 2006.173.01:46:21.87#ibcon#read 6, iclass 34, count 0 2006.173.01:46:21.87#ibcon#end of sib2, iclass 34, count 0 2006.173.01:46:21.87#ibcon#*mode == 0, iclass 34, count 0 2006.173.01:46:21.87#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.01:46:21.87#ibcon#[27=USB\r\n] 2006.173.01:46:21.87#ibcon#*before write, iclass 34, count 0 2006.173.01:46:21.87#ibcon#enter sib2, iclass 34, count 0 2006.173.01:46:21.87#ibcon#flushed, iclass 34, count 0 2006.173.01:46:21.87#ibcon#about to write, iclass 34, count 0 2006.173.01:46:21.87#ibcon#wrote, iclass 34, count 0 2006.173.01:46:21.87#ibcon#about to read 3, iclass 34, count 0 2006.173.01:46:21.90#ibcon#read 3, iclass 34, count 0 2006.173.01:46:21.90#ibcon#about to read 4, iclass 34, count 0 2006.173.01:46:21.90#ibcon#read 4, iclass 34, count 0 2006.173.01:46:21.90#ibcon#about to read 5, iclass 34, count 0 2006.173.01:46:21.90#ibcon#read 5, iclass 34, count 0 2006.173.01:46:21.90#ibcon#about to read 6, iclass 34, count 0 2006.173.01:46:21.90#ibcon#read 6, iclass 34, count 0 2006.173.01:46:21.90#ibcon#end of sib2, iclass 34, count 0 2006.173.01:46:21.90#ibcon#*after write, iclass 34, count 0 2006.173.01:46:21.90#ibcon#*before return 0, iclass 34, count 0 2006.173.01:46:21.90#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.01:46:21.90#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.01:46:21.90#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.01:46:21.90#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.01:46:21.90$vck44/vblo=2,634.99 2006.173.01:46:21.90#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.01:46:21.90#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.01:46:21.90#ibcon#ireg 17 cls_cnt 0 2006.173.01:46:21.90#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.01:46:21.90#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.01:46:21.90#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.01:46:21.90#ibcon#enter wrdev, iclass 37, count 0 2006.173.01:46:21.90#ibcon#first serial, iclass 37, count 0 2006.173.01:46:21.90#ibcon#enter sib2, iclass 37, count 0 2006.173.01:46:21.90#ibcon#flushed, iclass 37, count 0 2006.173.01:46:21.90#ibcon#about to write, iclass 37, count 0 2006.173.01:46:21.90#ibcon#wrote, iclass 37, count 0 2006.173.01:46:21.90#ibcon#about to read 3, iclass 37, count 0 2006.173.01:46:21.92#ibcon#read 3, iclass 37, count 0 2006.173.01:46:21.92#ibcon#about to read 4, iclass 37, count 0 2006.173.01:46:21.92#ibcon#read 4, iclass 37, count 0 2006.173.01:46:21.92#ibcon#about to read 5, iclass 37, count 0 2006.173.01:46:21.92#ibcon#read 5, iclass 37, count 0 2006.173.01:46:21.92#ibcon#about to read 6, iclass 37, count 0 2006.173.01:46:21.92#ibcon#read 6, iclass 37, count 0 2006.173.01:46:21.92#ibcon#end of sib2, iclass 37, count 0 2006.173.01:46:21.92#ibcon#*mode == 0, iclass 37, count 0 2006.173.01:46:21.92#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.01:46:21.92#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.01:46:21.92#ibcon#*before write, iclass 37, count 0 2006.173.01:46:21.92#ibcon#enter sib2, iclass 37, count 0 2006.173.01:46:21.92#ibcon#flushed, iclass 37, count 0 2006.173.01:46:21.92#ibcon#about to write, iclass 37, count 0 2006.173.01:46:21.92#ibcon#wrote, iclass 37, count 0 2006.173.01:46:21.92#ibcon#about to read 3, iclass 37, count 0 2006.173.01:46:21.92#abcon#<5=/14 1.4 3.8 22.39 851006.9\r\n> 2006.173.01:46:21.95#abcon#{5=INTERFACE CLEAR} 2006.173.01:46:21.96#ibcon#read 3, iclass 37, count 0 2006.173.01:46:21.96#ibcon#about to read 4, iclass 37, count 0 2006.173.01:46:21.96#ibcon#read 4, iclass 37, count 0 2006.173.01:46:21.96#ibcon#about to read 5, iclass 37, count 0 2006.173.01:46:21.96#ibcon#read 5, iclass 37, count 0 2006.173.01:46:21.96#ibcon#about to read 6, iclass 37, count 0 2006.173.01:46:21.96#ibcon#read 6, iclass 37, count 0 2006.173.01:46:21.96#ibcon#end of sib2, iclass 37, count 0 2006.173.01:46:21.96#ibcon#*after write, iclass 37, count 0 2006.173.01:46:21.96#ibcon#*before return 0, iclass 37, count 0 2006.173.01:46:21.96#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.01:46:21.96#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.01:46:21.96#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.01:46:21.96#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.01:46:21.96$vck44/vb=2,4 2006.173.01:46:21.96#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.01:46:21.96#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.01:46:21.96#ibcon#ireg 11 cls_cnt 2 2006.173.01:46:21.96#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.01:46:22.01#abcon#[5=S1D000X0/0*\r\n] 2006.173.01:46:22.02#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.01:46:22.02#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.01:46:22.02#ibcon#enter wrdev, iclass 3, count 2 2006.173.01:46:22.02#ibcon#first serial, iclass 3, count 2 2006.173.01:46:22.02#ibcon#enter sib2, iclass 3, count 2 2006.173.01:46:22.02#ibcon#flushed, iclass 3, count 2 2006.173.01:46:22.02#ibcon#about to write, iclass 3, count 2 2006.173.01:46:22.02#ibcon#wrote, iclass 3, count 2 2006.173.01:46:22.02#ibcon#about to read 3, iclass 3, count 2 2006.173.01:46:22.04#ibcon#read 3, iclass 3, count 2 2006.173.01:46:22.04#ibcon#about to read 4, iclass 3, count 2 2006.173.01:46:22.04#ibcon#read 4, iclass 3, count 2 2006.173.01:46:22.04#ibcon#about to read 5, iclass 3, count 2 2006.173.01:46:22.04#ibcon#read 5, iclass 3, count 2 2006.173.01:46:22.04#ibcon#about to read 6, iclass 3, count 2 2006.173.01:46:22.04#ibcon#read 6, iclass 3, count 2 2006.173.01:46:22.04#ibcon#end of sib2, iclass 3, count 2 2006.173.01:46:22.04#ibcon#*mode == 0, iclass 3, count 2 2006.173.01:46:22.04#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.01:46:22.04#ibcon#[27=AT02-04\r\n] 2006.173.01:46:22.04#ibcon#*before write, iclass 3, count 2 2006.173.01:46:22.04#ibcon#enter sib2, iclass 3, count 2 2006.173.01:46:22.04#ibcon#flushed, iclass 3, count 2 2006.173.01:46:22.04#ibcon#about to write, iclass 3, count 2 2006.173.01:46:22.04#ibcon#wrote, iclass 3, count 2 2006.173.01:46:22.04#ibcon#about to read 3, iclass 3, count 2 2006.173.01:46:22.07#ibcon#read 3, iclass 3, count 2 2006.173.01:46:22.07#ibcon#about to read 4, iclass 3, count 2 2006.173.01:46:22.07#ibcon#read 4, iclass 3, count 2 2006.173.01:46:22.07#ibcon#about to read 5, iclass 3, count 2 2006.173.01:46:22.07#ibcon#read 5, iclass 3, count 2 2006.173.01:46:22.07#ibcon#about to read 6, iclass 3, count 2 2006.173.01:46:22.07#ibcon#read 6, iclass 3, count 2 2006.173.01:46:22.07#ibcon#end of sib2, iclass 3, count 2 2006.173.01:46:22.07#ibcon#*after write, iclass 3, count 2 2006.173.01:46:22.07#ibcon#*before return 0, iclass 3, count 2 2006.173.01:46:22.07#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.01:46:22.07#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.01:46:22.07#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.01:46:22.07#ibcon#ireg 7 cls_cnt 0 2006.173.01:46:22.07#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.01:46:22.19#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.01:46:22.19#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.01:46:22.19#ibcon#enter wrdev, iclass 3, count 0 2006.173.01:46:22.19#ibcon#first serial, iclass 3, count 0 2006.173.01:46:22.19#ibcon#enter sib2, iclass 3, count 0 2006.173.01:46:22.19#ibcon#flushed, iclass 3, count 0 2006.173.01:46:22.19#ibcon#about to write, iclass 3, count 0 2006.173.01:46:22.19#ibcon#wrote, iclass 3, count 0 2006.173.01:46:22.19#ibcon#about to read 3, iclass 3, count 0 2006.173.01:46:22.21#ibcon#read 3, iclass 3, count 0 2006.173.01:46:22.21#ibcon#about to read 4, iclass 3, count 0 2006.173.01:46:22.21#ibcon#read 4, iclass 3, count 0 2006.173.01:46:22.21#ibcon#about to read 5, iclass 3, count 0 2006.173.01:46:22.21#ibcon#read 5, iclass 3, count 0 2006.173.01:46:22.21#ibcon#about to read 6, iclass 3, count 0 2006.173.01:46:22.21#ibcon#read 6, iclass 3, count 0 2006.173.01:46:22.21#ibcon#end of sib2, iclass 3, count 0 2006.173.01:46:22.21#ibcon#*mode == 0, iclass 3, count 0 2006.173.01:46:22.21#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.01:46:22.21#ibcon#[27=USB\r\n] 2006.173.01:46:22.21#ibcon#*before write, iclass 3, count 0 2006.173.01:46:22.21#ibcon#enter sib2, iclass 3, count 0 2006.173.01:46:22.21#ibcon#flushed, iclass 3, count 0 2006.173.01:46:22.21#ibcon#about to write, iclass 3, count 0 2006.173.01:46:22.21#ibcon#wrote, iclass 3, count 0 2006.173.01:46:22.21#ibcon#about to read 3, iclass 3, count 0 2006.173.01:46:22.24#ibcon#read 3, iclass 3, count 0 2006.173.01:46:22.24#ibcon#about to read 4, iclass 3, count 0 2006.173.01:46:22.24#ibcon#read 4, iclass 3, count 0 2006.173.01:46:22.24#ibcon#about to read 5, iclass 3, count 0 2006.173.01:46:22.24#ibcon#read 5, iclass 3, count 0 2006.173.01:46:22.24#ibcon#about to read 6, iclass 3, count 0 2006.173.01:46:22.24#ibcon#read 6, iclass 3, count 0 2006.173.01:46:22.24#ibcon#end of sib2, iclass 3, count 0 2006.173.01:46:22.24#ibcon#*after write, iclass 3, count 0 2006.173.01:46:22.24#ibcon#*before return 0, iclass 3, count 0 2006.173.01:46:22.24#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.01:46:22.24#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.01:46:22.24#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.01:46:22.24#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.01:46:22.24$vck44/vblo=3,649.99 2006.173.01:46:22.24#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.01:46:22.24#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.01:46:22.24#ibcon#ireg 17 cls_cnt 0 2006.173.01:46:22.24#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.01:46:22.24#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.01:46:22.24#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.01:46:22.24#ibcon#enter wrdev, iclass 6, count 0 2006.173.01:46:22.24#ibcon#first serial, iclass 6, count 0 2006.173.01:46:22.24#ibcon#enter sib2, iclass 6, count 0 2006.173.01:46:22.24#ibcon#flushed, iclass 6, count 0 2006.173.01:46:22.24#ibcon#about to write, iclass 6, count 0 2006.173.01:46:22.24#ibcon#wrote, iclass 6, count 0 2006.173.01:46:22.24#ibcon#about to read 3, iclass 6, count 0 2006.173.01:46:22.26#ibcon#read 3, iclass 6, count 0 2006.173.01:46:22.26#ibcon#about to read 4, iclass 6, count 0 2006.173.01:46:22.26#ibcon#read 4, iclass 6, count 0 2006.173.01:46:22.26#ibcon#about to read 5, iclass 6, count 0 2006.173.01:46:22.26#ibcon#read 5, iclass 6, count 0 2006.173.01:46:22.26#ibcon#about to read 6, iclass 6, count 0 2006.173.01:46:22.26#ibcon#read 6, iclass 6, count 0 2006.173.01:46:22.26#ibcon#end of sib2, iclass 6, count 0 2006.173.01:46:22.26#ibcon#*mode == 0, iclass 6, count 0 2006.173.01:46:22.26#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.01:46:22.26#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.01:46:22.26#ibcon#*before write, iclass 6, count 0 2006.173.01:46:22.26#ibcon#enter sib2, iclass 6, count 0 2006.173.01:46:22.26#ibcon#flushed, iclass 6, count 0 2006.173.01:46:22.26#ibcon#about to write, iclass 6, count 0 2006.173.01:46:22.26#ibcon#wrote, iclass 6, count 0 2006.173.01:46:22.26#ibcon#about to read 3, iclass 6, count 0 2006.173.01:46:22.30#ibcon#read 3, iclass 6, count 0 2006.173.01:46:22.30#ibcon#about to read 4, iclass 6, count 0 2006.173.01:46:22.30#ibcon#read 4, iclass 6, count 0 2006.173.01:46:22.30#ibcon#about to read 5, iclass 6, count 0 2006.173.01:46:22.30#ibcon#read 5, iclass 6, count 0 2006.173.01:46:22.30#ibcon#about to read 6, iclass 6, count 0 2006.173.01:46:22.30#ibcon#read 6, iclass 6, count 0 2006.173.01:46:22.30#ibcon#end of sib2, iclass 6, count 0 2006.173.01:46:22.30#ibcon#*after write, iclass 6, count 0 2006.173.01:46:22.30#ibcon#*before return 0, iclass 6, count 0 2006.173.01:46:22.30#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.01:46:22.30#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.01:46:22.30#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.01:46:22.30#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.01:46:22.30$vck44/vb=3,4 2006.173.01:46:22.30#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.01:46:22.30#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.01:46:22.30#ibcon#ireg 11 cls_cnt 2 2006.173.01:46:22.30#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.01:46:22.36#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.01:46:22.36#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.01:46:22.36#ibcon#enter wrdev, iclass 10, count 2 2006.173.01:46:22.36#ibcon#first serial, iclass 10, count 2 2006.173.01:46:22.36#ibcon#enter sib2, iclass 10, count 2 2006.173.01:46:22.36#ibcon#flushed, iclass 10, count 2 2006.173.01:46:22.36#ibcon#about to write, iclass 10, count 2 2006.173.01:46:22.36#ibcon#wrote, iclass 10, count 2 2006.173.01:46:22.36#ibcon#about to read 3, iclass 10, count 2 2006.173.01:46:22.38#ibcon#read 3, iclass 10, count 2 2006.173.01:46:22.38#ibcon#about to read 4, iclass 10, count 2 2006.173.01:46:22.38#ibcon#read 4, iclass 10, count 2 2006.173.01:46:22.38#ibcon#about to read 5, iclass 10, count 2 2006.173.01:46:22.38#ibcon#read 5, iclass 10, count 2 2006.173.01:46:22.38#ibcon#about to read 6, iclass 10, count 2 2006.173.01:46:22.38#ibcon#read 6, iclass 10, count 2 2006.173.01:46:22.38#ibcon#end of sib2, iclass 10, count 2 2006.173.01:46:22.38#ibcon#*mode == 0, iclass 10, count 2 2006.173.01:46:22.38#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.01:46:22.38#ibcon#[27=AT03-04\r\n] 2006.173.01:46:22.38#ibcon#*before write, iclass 10, count 2 2006.173.01:46:22.38#ibcon#enter sib2, iclass 10, count 2 2006.173.01:46:22.38#ibcon#flushed, iclass 10, count 2 2006.173.01:46:22.38#ibcon#about to write, iclass 10, count 2 2006.173.01:46:22.38#ibcon#wrote, iclass 10, count 2 2006.173.01:46:22.38#ibcon#about to read 3, iclass 10, count 2 2006.173.01:46:22.41#ibcon#read 3, iclass 10, count 2 2006.173.01:46:22.41#ibcon#about to read 4, iclass 10, count 2 2006.173.01:46:22.41#ibcon#read 4, iclass 10, count 2 2006.173.01:46:22.41#ibcon#about to read 5, iclass 10, count 2 2006.173.01:46:22.41#ibcon#read 5, iclass 10, count 2 2006.173.01:46:22.41#ibcon#about to read 6, iclass 10, count 2 2006.173.01:46:22.41#ibcon#read 6, iclass 10, count 2 2006.173.01:46:22.41#ibcon#end of sib2, iclass 10, count 2 2006.173.01:46:22.41#ibcon#*after write, iclass 10, count 2 2006.173.01:46:22.41#ibcon#*before return 0, iclass 10, count 2 2006.173.01:46:22.41#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.01:46:22.41#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.01:46:22.41#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.01:46:22.41#ibcon#ireg 7 cls_cnt 0 2006.173.01:46:22.41#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.01:46:22.53#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.01:46:22.53#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.01:46:22.53#ibcon#enter wrdev, iclass 10, count 0 2006.173.01:46:22.53#ibcon#first serial, iclass 10, count 0 2006.173.01:46:22.53#ibcon#enter sib2, iclass 10, count 0 2006.173.01:46:22.53#ibcon#flushed, iclass 10, count 0 2006.173.01:46:22.53#ibcon#about to write, iclass 10, count 0 2006.173.01:46:22.53#ibcon#wrote, iclass 10, count 0 2006.173.01:46:22.53#ibcon#about to read 3, iclass 10, count 0 2006.173.01:46:22.55#ibcon#read 3, iclass 10, count 0 2006.173.01:46:22.55#ibcon#about to read 4, iclass 10, count 0 2006.173.01:46:22.55#ibcon#read 4, iclass 10, count 0 2006.173.01:46:22.55#ibcon#about to read 5, iclass 10, count 0 2006.173.01:46:22.55#ibcon#read 5, iclass 10, count 0 2006.173.01:46:22.55#ibcon#about to read 6, iclass 10, count 0 2006.173.01:46:22.55#ibcon#read 6, iclass 10, count 0 2006.173.01:46:22.55#ibcon#end of sib2, iclass 10, count 0 2006.173.01:46:22.55#ibcon#*mode == 0, iclass 10, count 0 2006.173.01:46:22.55#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.01:46:22.55#ibcon#[27=USB\r\n] 2006.173.01:46:22.55#ibcon#*before write, iclass 10, count 0 2006.173.01:46:22.55#ibcon#enter sib2, iclass 10, count 0 2006.173.01:46:22.55#ibcon#flushed, iclass 10, count 0 2006.173.01:46:22.55#ibcon#about to write, iclass 10, count 0 2006.173.01:46:22.55#ibcon#wrote, iclass 10, count 0 2006.173.01:46:22.55#ibcon#about to read 3, iclass 10, count 0 2006.173.01:46:22.58#ibcon#read 3, iclass 10, count 0 2006.173.01:46:22.58#ibcon#about to read 4, iclass 10, count 0 2006.173.01:46:22.58#ibcon#read 4, iclass 10, count 0 2006.173.01:46:22.58#ibcon#about to read 5, iclass 10, count 0 2006.173.01:46:22.58#ibcon#read 5, iclass 10, count 0 2006.173.01:46:22.58#ibcon#about to read 6, iclass 10, count 0 2006.173.01:46:22.58#ibcon#read 6, iclass 10, count 0 2006.173.01:46:22.58#ibcon#end of sib2, iclass 10, count 0 2006.173.01:46:22.58#ibcon#*after write, iclass 10, count 0 2006.173.01:46:22.58#ibcon#*before return 0, iclass 10, count 0 2006.173.01:46:22.58#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.01:46:22.58#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.01:46:22.58#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.01:46:22.58#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.01:46:22.58$vck44/vblo=4,679.99 2006.173.01:46:22.58#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.01:46:22.58#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.01:46:22.58#ibcon#ireg 17 cls_cnt 0 2006.173.01:46:22.58#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.01:46:22.58#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.01:46:22.58#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.01:46:22.58#ibcon#enter wrdev, iclass 12, count 0 2006.173.01:46:22.58#ibcon#first serial, iclass 12, count 0 2006.173.01:46:22.58#ibcon#enter sib2, iclass 12, count 0 2006.173.01:46:22.58#ibcon#flushed, iclass 12, count 0 2006.173.01:46:22.58#ibcon#about to write, iclass 12, count 0 2006.173.01:46:22.58#ibcon#wrote, iclass 12, count 0 2006.173.01:46:22.58#ibcon#about to read 3, iclass 12, count 0 2006.173.01:46:22.60#ibcon#read 3, iclass 12, count 0 2006.173.01:46:22.60#ibcon#about to read 4, iclass 12, count 0 2006.173.01:46:22.60#ibcon#read 4, iclass 12, count 0 2006.173.01:46:22.60#ibcon#about to read 5, iclass 12, count 0 2006.173.01:46:22.60#ibcon#read 5, iclass 12, count 0 2006.173.01:46:22.60#ibcon#about to read 6, iclass 12, count 0 2006.173.01:46:22.60#ibcon#read 6, iclass 12, count 0 2006.173.01:46:22.60#ibcon#end of sib2, iclass 12, count 0 2006.173.01:46:22.60#ibcon#*mode == 0, iclass 12, count 0 2006.173.01:46:22.60#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.01:46:22.60#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.01:46:22.60#ibcon#*before write, iclass 12, count 0 2006.173.01:46:22.60#ibcon#enter sib2, iclass 12, count 0 2006.173.01:46:22.60#ibcon#flushed, iclass 12, count 0 2006.173.01:46:22.60#ibcon#about to write, iclass 12, count 0 2006.173.01:46:22.60#ibcon#wrote, iclass 12, count 0 2006.173.01:46:22.60#ibcon#about to read 3, iclass 12, count 0 2006.173.01:46:22.64#ibcon#read 3, iclass 12, count 0 2006.173.01:46:22.64#ibcon#about to read 4, iclass 12, count 0 2006.173.01:46:22.64#ibcon#read 4, iclass 12, count 0 2006.173.01:46:22.64#ibcon#about to read 5, iclass 12, count 0 2006.173.01:46:22.64#ibcon#read 5, iclass 12, count 0 2006.173.01:46:22.64#ibcon#about to read 6, iclass 12, count 0 2006.173.01:46:22.64#ibcon#read 6, iclass 12, count 0 2006.173.01:46:22.64#ibcon#end of sib2, iclass 12, count 0 2006.173.01:46:22.64#ibcon#*after write, iclass 12, count 0 2006.173.01:46:22.64#ibcon#*before return 0, iclass 12, count 0 2006.173.01:46:22.64#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.01:46:22.64#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.01:46:22.64#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.01:46:22.64#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.01:46:22.64$vck44/vb=4,4 2006.173.01:46:22.64#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.01:46:22.64#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.01:46:22.64#ibcon#ireg 11 cls_cnt 2 2006.173.01:46:22.64#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.01:46:22.70#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.01:46:22.70#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.01:46:22.70#ibcon#enter wrdev, iclass 14, count 2 2006.173.01:46:22.70#ibcon#first serial, iclass 14, count 2 2006.173.01:46:22.70#ibcon#enter sib2, iclass 14, count 2 2006.173.01:46:22.70#ibcon#flushed, iclass 14, count 2 2006.173.01:46:22.70#ibcon#about to write, iclass 14, count 2 2006.173.01:46:22.70#ibcon#wrote, iclass 14, count 2 2006.173.01:46:22.70#ibcon#about to read 3, iclass 14, count 2 2006.173.01:46:22.72#ibcon#read 3, iclass 14, count 2 2006.173.01:46:22.72#ibcon#about to read 4, iclass 14, count 2 2006.173.01:46:22.72#ibcon#read 4, iclass 14, count 2 2006.173.01:46:22.72#ibcon#about to read 5, iclass 14, count 2 2006.173.01:46:22.72#ibcon#read 5, iclass 14, count 2 2006.173.01:46:22.72#ibcon#about to read 6, iclass 14, count 2 2006.173.01:46:22.72#ibcon#read 6, iclass 14, count 2 2006.173.01:46:22.72#ibcon#end of sib2, iclass 14, count 2 2006.173.01:46:22.72#ibcon#*mode == 0, iclass 14, count 2 2006.173.01:46:22.72#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.01:46:22.72#ibcon#[27=AT04-04\r\n] 2006.173.01:46:22.72#ibcon#*before write, iclass 14, count 2 2006.173.01:46:22.72#ibcon#enter sib2, iclass 14, count 2 2006.173.01:46:22.72#ibcon#flushed, iclass 14, count 2 2006.173.01:46:22.72#ibcon#about to write, iclass 14, count 2 2006.173.01:46:22.72#ibcon#wrote, iclass 14, count 2 2006.173.01:46:22.72#ibcon#about to read 3, iclass 14, count 2 2006.173.01:46:22.75#ibcon#read 3, iclass 14, count 2 2006.173.01:46:22.75#ibcon#about to read 4, iclass 14, count 2 2006.173.01:46:22.75#ibcon#read 4, iclass 14, count 2 2006.173.01:46:22.75#ibcon#about to read 5, iclass 14, count 2 2006.173.01:46:22.75#ibcon#read 5, iclass 14, count 2 2006.173.01:46:22.75#ibcon#about to read 6, iclass 14, count 2 2006.173.01:46:22.75#ibcon#read 6, iclass 14, count 2 2006.173.01:46:22.75#ibcon#end of sib2, iclass 14, count 2 2006.173.01:46:22.75#ibcon#*after write, iclass 14, count 2 2006.173.01:46:22.75#ibcon#*before return 0, iclass 14, count 2 2006.173.01:46:22.75#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.01:46:22.75#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.01:46:22.75#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.01:46:22.75#ibcon#ireg 7 cls_cnt 0 2006.173.01:46:22.75#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.01:46:22.87#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.01:46:22.87#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.01:46:22.87#ibcon#enter wrdev, iclass 14, count 0 2006.173.01:46:22.87#ibcon#first serial, iclass 14, count 0 2006.173.01:46:22.87#ibcon#enter sib2, iclass 14, count 0 2006.173.01:46:22.87#ibcon#flushed, iclass 14, count 0 2006.173.01:46:22.87#ibcon#about to write, iclass 14, count 0 2006.173.01:46:22.87#ibcon#wrote, iclass 14, count 0 2006.173.01:46:22.87#ibcon#about to read 3, iclass 14, count 0 2006.173.01:46:22.89#ibcon#read 3, iclass 14, count 0 2006.173.01:46:22.89#ibcon#about to read 4, iclass 14, count 0 2006.173.01:46:22.89#ibcon#read 4, iclass 14, count 0 2006.173.01:46:22.89#ibcon#about to read 5, iclass 14, count 0 2006.173.01:46:22.89#ibcon#read 5, iclass 14, count 0 2006.173.01:46:22.89#ibcon#about to read 6, iclass 14, count 0 2006.173.01:46:22.89#ibcon#read 6, iclass 14, count 0 2006.173.01:46:22.89#ibcon#end of sib2, iclass 14, count 0 2006.173.01:46:22.89#ibcon#*mode == 0, iclass 14, count 0 2006.173.01:46:22.89#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.01:46:22.89#ibcon#[27=USB\r\n] 2006.173.01:46:22.89#ibcon#*before write, iclass 14, count 0 2006.173.01:46:22.89#ibcon#enter sib2, iclass 14, count 0 2006.173.01:46:22.89#ibcon#flushed, iclass 14, count 0 2006.173.01:46:22.89#ibcon#about to write, iclass 14, count 0 2006.173.01:46:22.89#ibcon#wrote, iclass 14, count 0 2006.173.01:46:22.89#ibcon#about to read 3, iclass 14, count 0 2006.173.01:46:22.92#ibcon#read 3, iclass 14, count 0 2006.173.01:46:22.92#ibcon#about to read 4, iclass 14, count 0 2006.173.01:46:22.92#ibcon#read 4, iclass 14, count 0 2006.173.01:46:22.92#ibcon#about to read 5, iclass 14, count 0 2006.173.01:46:22.92#ibcon#read 5, iclass 14, count 0 2006.173.01:46:22.92#ibcon#about to read 6, iclass 14, count 0 2006.173.01:46:22.92#ibcon#read 6, iclass 14, count 0 2006.173.01:46:22.92#ibcon#end of sib2, iclass 14, count 0 2006.173.01:46:22.92#ibcon#*after write, iclass 14, count 0 2006.173.01:46:22.92#ibcon#*before return 0, iclass 14, count 0 2006.173.01:46:22.92#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.01:46:22.92#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.01:46:22.92#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.01:46:22.92#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.01:46:22.92$vck44/vblo=5,709.99 2006.173.01:46:22.92#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.01:46:22.92#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.01:46:22.92#ibcon#ireg 17 cls_cnt 0 2006.173.01:46:22.92#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.01:46:22.92#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.01:46:22.92#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.01:46:22.92#ibcon#enter wrdev, iclass 16, count 0 2006.173.01:46:22.92#ibcon#first serial, iclass 16, count 0 2006.173.01:46:22.92#ibcon#enter sib2, iclass 16, count 0 2006.173.01:46:22.92#ibcon#flushed, iclass 16, count 0 2006.173.01:46:22.92#ibcon#about to write, iclass 16, count 0 2006.173.01:46:22.92#ibcon#wrote, iclass 16, count 0 2006.173.01:46:22.92#ibcon#about to read 3, iclass 16, count 0 2006.173.01:46:22.94#ibcon#read 3, iclass 16, count 0 2006.173.01:46:22.94#ibcon#about to read 4, iclass 16, count 0 2006.173.01:46:22.94#ibcon#read 4, iclass 16, count 0 2006.173.01:46:22.94#ibcon#about to read 5, iclass 16, count 0 2006.173.01:46:22.94#ibcon#read 5, iclass 16, count 0 2006.173.01:46:22.94#ibcon#about to read 6, iclass 16, count 0 2006.173.01:46:22.94#ibcon#read 6, iclass 16, count 0 2006.173.01:46:22.94#ibcon#end of sib2, iclass 16, count 0 2006.173.01:46:22.94#ibcon#*mode == 0, iclass 16, count 0 2006.173.01:46:22.94#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.01:46:22.94#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.01:46:22.94#ibcon#*before write, iclass 16, count 0 2006.173.01:46:22.94#ibcon#enter sib2, iclass 16, count 0 2006.173.01:46:22.94#ibcon#flushed, iclass 16, count 0 2006.173.01:46:22.94#ibcon#about to write, iclass 16, count 0 2006.173.01:46:22.94#ibcon#wrote, iclass 16, count 0 2006.173.01:46:22.94#ibcon#about to read 3, iclass 16, count 0 2006.173.01:46:22.98#ibcon#read 3, iclass 16, count 0 2006.173.01:46:22.98#ibcon#about to read 4, iclass 16, count 0 2006.173.01:46:22.98#ibcon#read 4, iclass 16, count 0 2006.173.01:46:22.98#ibcon#about to read 5, iclass 16, count 0 2006.173.01:46:22.98#ibcon#read 5, iclass 16, count 0 2006.173.01:46:22.98#ibcon#about to read 6, iclass 16, count 0 2006.173.01:46:22.98#ibcon#read 6, iclass 16, count 0 2006.173.01:46:22.98#ibcon#end of sib2, iclass 16, count 0 2006.173.01:46:22.98#ibcon#*after write, iclass 16, count 0 2006.173.01:46:22.98#ibcon#*before return 0, iclass 16, count 0 2006.173.01:46:22.98#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.01:46:22.98#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.01:46:22.98#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.01:46:22.98#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.01:46:22.98$vck44/vb=5,4 2006.173.01:46:22.98#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.01:46:22.98#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.01:46:22.98#ibcon#ireg 11 cls_cnt 2 2006.173.01:46:22.98#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.01:46:23.04#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.01:46:23.04#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.01:46:23.04#ibcon#enter wrdev, iclass 18, count 2 2006.173.01:46:23.04#ibcon#first serial, iclass 18, count 2 2006.173.01:46:23.04#ibcon#enter sib2, iclass 18, count 2 2006.173.01:46:23.04#ibcon#flushed, iclass 18, count 2 2006.173.01:46:23.04#ibcon#about to write, iclass 18, count 2 2006.173.01:46:23.04#ibcon#wrote, iclass 18, count 2 2006.173.01:46:23.04#ibcon#about to read 3, iclass 18, count 2 2006.173.01:46:23.06#ibcon#read 3, iclass 18, count 2 2006.173.01:46:23.06#ibcon#about to read 4, iclass 18, count 2 2006.173.01:46:23.06#ibcon#read 4, iclass 18, count 2 2006.173.01:46:23.06#ibcon#about to read 5, iclass 18, count 2 2006.173.01:46:23.06#ibcon#read 5, iclass 18, count 2 2006.173.01:46:23.06#ibcon#about to read 6, iclass 18, count 2 2006.173.01:46:23.06#ibcon#read 6, iclass 18, count 2 2006.173.01:46:23.06#ibcon#end of sib2, iclass 18, count 2 2006.173.01:46:23.06#ibcon#*mode == 0, iclass 18, count 2 2006.173.01:46:23.06#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.01:46:23.06#ibcon#[27=AT05-04\r\n] 2006.173.01:46:23.06#ibcon#*before write, iclass 18, count 2 2006.173.01:46:23.06#ibcon#enter sib2, iclass 18, count 2 2006.173.01:46:23.06#ibcon#flushed, iclass 18, count 2 2006.173.01:46:23.06#ibcon#about to write, iclass 18, count 2 2006.173.01:46:23.06#ibcon#wrote, iclass 18, count 2 2006.173.01:46:23.06#ibcon#about to read 3, iclass 18, count 2 2006.173.01:46:23.09#ibcon#read 3, iclass 18, count 2 2006.173.01:46:23.09#ibcon#about to read 4, iclass 18, count 2 2006.173.01:46:23.09#ibcon#read 4, iclass 18, count 2 2006.173.01:46:23.09#ibcon#about to read 5, iclass 18, count 2 2006.173.01:46:23.09#ibcon#read 5, iclass 18, count 2 2006.173.01:46:23.09#ibcon#about to read 6, iclass 18, count 2 2006.173.01:46:23.09#ibcon#read 6, iclass 18, count 2 2006.173.01:46:23.09#ibcon#end of sib2, iclass 18, count 2 2006.173.01:46:23.09#ibcon#*after write, iclass 18, count 2 2006.173.01:46:23.09#ibcon#*before return 0, iclass 18, count 2 2006.173.01:46:23.09#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.01:46:23.09#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.01:46:23.09#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.01:46:23.09#ibcon#ireg 7 cls_cnt 0 2006.173.01:46:23.09#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.01:46:23.21#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.01:46:23.21#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.01:46:23.21#ibcon#enter wrdev, iclass 18, count 0 2006.173.01:46:23.21#ibcon#first serial, iclass 18, count 0 2006.173.01:46:23.21#ibcon#enter sib2, iclass 18, count 0 2006.173.01:46:23.21#ibcon#flushed, iclass 18, count 0 2006.173.01:46:23.21#ibcon#about to write, iclass 18, count 0 2006.173.01:46:23.21#ibcon#wrote, iclass 18, count 0 2006.173.01:46:23.21#ibcon#about to read 3, iclass 18, count 0 2006.173.01:46:23.23#ibcon#read 3, iclass 18, count 0 2006.173.01:46:23.23#ibcon#about to read 4, iclass 18, count 0 2006.173.01:46:23.23#ibcon#read 4, iclass 18, count 0 2006.173.01:46:23.23#ibcon#about to read 5, iclass 18, count 0 2006.173.01:46:23.23#ibcon#read 5, iclass 18, count 0 2006.173.01:46:23.23#ibcon#about to read 6, iclass 18, count 0 2006.173.01:46:23.23#ibcon#read 6, iclass 18, count 0 2006.173.01:46:23.23#ibcon#end of sib2, iclass 18, count 0 2006.173.01:46:23.23#ibcon#*mode == 0, iclass 18, count 0 2006.173.01:46:23.23#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.01:46:23.23#ibcon#[27=USB\r\n] 2006.173.01:46:23.23#ibcon#*before write, iclass 18, count 0 2006.173.01:46:23.23#ibcon#enter sib2, iclass 18, count 0 2006.173.01:46:23.23#ibcon#flushed, iclass 18, count 0 2006.173.01:46:23.23#ibcon#about to write, iclass 18, count 0 2006.173.01:46:23.23#ibcon#wrote, iclass 18, count 0 2006.173.01:46:23.23#ibcon#about to read 3, iclass 18, count 0 2006.173.01:46:23.26#ibcon#read 3, iclass 18, count 0 2006.173.01:46:23.26#ibcon#about to read 4, iclass 18, count 0 2006.173.01:46:23.26#ibcon#read 4, iclass 18, count 0 2006.173.01:46:23.26#ibcon#about to read 5, iclass 18, count 0 2006.173.01:46:23.26#ibcon#read 5, iclass 18, count 0 2006.173.01:46:23.26#ibcon#about to read 6, iclass 18, count 0 2006.173.01:46:23.26#ibcon#read 6, iclass 18, count 0 2006.173.01:46:23.26#ibcon#end of sib2, iclass 18, count 0 2006.173.01:46:23.26#ibcon#*after write, iclass 18, count 0 2006.173.01:46:23.26#ibcon#*before return 0, iclass 18, count 0 2006.173.01:46:23.26#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.01:46:23.26#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.01:46:23.26#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.01:46:23.26#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.01:46:23.26$vck44/vblo=6,719.99 2006.173.01:46:23.26#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.01:46:23.26#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.01:46:23.26#ibcon#ireg 17 cls_cnt 0 2006.173.01:46:23.26#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.01:46:23.26#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.01:46:23.26#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.01:46:23.26#ibcon#enter wrdev, iclass 20, count 0 2006.173.01:46:23.26#ibcon#first serial, iclass 20, count 0 2006.173.01:46:23.26#ibcon#enter sib2, iclass 20, count 0 2006.173.01:46:23.26#ibcon#flushed, iclass 20, count 0 2006.173.01:46:23.26#ibcon#about to write, iclass 20, count 0 2006.173.01:46:23.26#ibcon#wrote, iclass 20, count 0 2006.173.01:46:23.26#ibcon#about to read 3, iclass 20, count 0 2006.173.01:46:23.28#ibcon#read 3, iclass 20, count 0 2006.173.01:46:23.28#ibcon#about to read 4, iclass 20, count 0 2006.173.01:46:23.28#ibcon#read 4, iclass 20, count 0 2006.173.01:46:23.28#ibcon#about to read 5, iclass 20, count 0 2006.173.01:46:23.28#ibcon#read 5, iclass 20, count 0 2006.173.01:46:23.28#ibcon#about to read 6, iclass 20, count 0 2006.173.01:46:23.28#ibcon#read 6, iclass 20, count 0 2006.173.01:46:23.28#ibcon#end of sib2, iclass 20, count 0 2006.173.01:46:23.28#ibcon#*mode == 0, iclass 20, count 0 2006.173.01:46:23.28#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.01:46:23.28#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.01:46:23.28#ibcon#*before write, iclass 20, count 0 2006.173.01:46:23.28#ibcon#enter sib2, iclass 20, count 0 2006.173.01:46:23.28#ibcon#flushed, iclass 20, count 0 2006.173.01:46:23.28#ibcon#about to write, iclass 20, count 0 2006.173.01:46:23.28#ibcon#wrote, iclass 20, count 0 2006.173.01:46:23.28#ibcon#about to read 3, iclass 20, count 0 2006.173.01:46:23.32#ibcon#read 3, iclass 20, count 0 2006.173.01:46:23.32#ibcon#about to read 4, iclass 20, count 0 2006.173.01:46:23.32#ibcon#read 4, iclass 20, count 0 2006.173.01:46:23.32#ibcon#about to read 5, iclass 20, count 0 2006.173.01:46:23.32#ibcon#read 5, iclass 20, count 0 2006.173.01:46:23.32#ibcon#about to read 6, iclass 20, count 0 2006.173.01:46:23.32#ibcon#read 6, iclass 20, count 0 2006.173.01:46:23.32#ibcon#end of sib2, iclass 20, count 0 2006.173.01:46:23.32#ibcon#*after write, iclass 20, count 0 2006.173.01:46:23.32#ibcon#*before return 0, iclass 20, count 0 2006.173.01:46:23.32#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.01:46:23.32#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.01:46:23.32#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.01:46:23.32#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.01:46:23.32$vck44/vb=6,4 2006.173.01:46:23.32#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.01:46:23.32#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.01:46:23.32#ibcon#ireg 11 cls_cnt 2 2006.173.01:46:23.32#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.01:46:23.38#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.01:46:23.38#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.01:46:23.38#ibcon#enter wrdev, iclass 22, count 2 2006.173.01:46:23.38#ibcon#first serial, iclass 22, count 2 2006.173.01:46:23.38#ibcon#enter sib2, iclass 22, count 2 2006.173.01:46:23.38#ibcon#flushed, iclass 22, count 2 2006.173.01:46:23.38#ibcon#about to write, iclass 22, count 2 2006.173.01:46:23.38#ibcon#wrote, iclass 22, count 2 2006.173.01:46:23.38#ibcon#about to read 3, iclass 22, count 2 2006.173.01:46:23.40#ibcon#read 3, iclass 22, count 2 2006.173.01:46:23.40#ibcon#about to read 4, iclass 22, count 2 2006.173.01:46:23.40#ibcon#read 4, iclass 22, count 2 2006.173.01:46:23.40#ibcon#about to read 5, iclass 22, count 2 2006.173.01:46:23.40#ibcon#read 5, iclass 22, count 2 2006.173.01:46:23.40#ibcon#about to read 6, iclass 22, count 2 2006.173.01:46:23.40#ibcon#read 6, iclass 22, count 2 2006.173.01:46:23.40#ibcon#end of sib2, iclass 22, count 2 2006.173.01:46:23.40#ibcon#*mode == 0, iclass 22, count 2 2006.173.01:46:23.40#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.01:46:23.40#ibcon#[27=AT06-04\r\n] 2006.173.01:46:23.40#ibcon#*before write, iclass 22, count 2 2006.173.01:46:23.40#ibcon#enter sib2, iclass 22, count 2 2006.173.01:46:23.40#ibcon#flushed, iclass 22, count 2 2006.173.01:46:23.40#ibcon#about to write, iclass 22, count 2 2006.173.01:46:23.40#ibcon#wrote, iclass 22, count 2 2006.173.01:46:23.40#ibcon#about to read 3, iclass 22, count 2 2006.173.01:46:23.43#ibcon#read 3, iclass 22, count 2 2006.173.01:46:23.43#ibcon#about to read 4, iclass 22, count 2 2006.173.01:46:23.43#ibcon#read 4, iclass 22, count 2 2006.173.01:46:23.43#ibcon#about to read 5, iclass 22, count 2 2006.173.01:46:23.43#ibcon#read 5, iclass 22, count 2 2006.173.01:46:23.43#ibcon#about to read 6, iclass 22, count 2 2006.173.01:46:23.43#ibcon#read 6, iclass 22, count 2 2006.173.01:46:23.43#ibcon#end of sib2, iclass 22, count 2 2006.173.01:46:23.43#ibcon#*after write, iclass 22, count 2 2006.173.01:46:23.43#ibcon#*before return 0, iclass 22, count 2 2006.173.01:46:23.43#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.01:46:23.43#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.01:46:23.43#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.01:46:23.43#ibcon#ireg 7 cls_cnt 0 2006.173.01:46:23.43#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.01:46:23.55#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.01:46:23.55#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.01:46:23.55#ibcon#enter wrdev, iclass 22, count 0 2006.173.01:46:23.55#ibcon#first serial, iclass 22, count 0 2006.173.01:46:23.55#ibcon#enter sib2, iclass 22, count 0 2006.173.01:46:23.55#ibcon#flushed, iclass 22, count 0 2006.173.01:46:23.55#ibcon#about to write, iclass 22, count 0 2006.173.01:46:23.55#ibcon#wrote, iclass 22, count 0 2006.173.01:46:23.55#ibcon#about to read 3, iclass 22, count 0 2006.173.01:46:23.57#ibcon#read 3, iclass 22, count 0 2006.173.01:46:23.57#ibcon#about to read 4, iclass 22, count 0 2006.173.01:46:23.57#ibcon#read 4, iclass 22, count 0 2006.173.01:46:23.57#ibcon#about to read 5, iclass 22, count 0 2006.173.01:46:23.57#ibcon#read 5, iclass 22, count 0 2006.173.01:46:23.57#ibcon#about to read 6, iclass 22, count 0 2006.173.01:46:23.57#ibcon#read 6, iclass 22, count 0 2006.173.01:46:23.57#ibcon#end of sib2, iclass 22, count 0 2006.173.01:46:23.57#ibcon#*mode == 0, iclass 22, count 0 2006.173.01:46:23.57#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.01:46:23.57#ibcon#[27=USB\r\n] 2006.173.01:46:23.57#ibcon#*before write, iclass 22, count 0 2006.173.01:46:23.57#ibcon#enter sib2, iclass 22, count 0 2006.173.01:46:23.57#ibcon#flushed, iclass 22, count 0 2006.173.01:46:23.57#ibcon#about to write, iclass 22, count 0 2006.173.01:46:23.57#ibcon#wrote, iclass 22, count 0 2006.173.01:46:23.57#ibcon#about to read 3, iclass 22, count 0 2006.173.01:46:23.60#ibcon#read 3, iclass 22, count 0 2006.173.01:46:23.60#ibcon#about to read 4, iclass 22, count 0 2006.173.01:46:23.60#ibcon#read 4, iclass 22, count 0 2006.173.01:46:23.60#ibcon#about to read 5, iclass 22, count 0 2006.173.01:46:23.60#ibcon#read 5, iclass 22, count 0 2006.173.01:46:23.60#ibcon#about to read 6, iclass 22, count 0 2006.173.01:46:23.60#ibcon#read 6, iclass 22, count 0 2006.173.01:46:23.60#ibcon#end of sib2, iclass 22, count 0 2006.173.01:46:23.60#ibcon#*after write, iclass 22, count 0 2006.173.01:46:23.60#ibcon#*before return 0, iclass 22, count 0 2006.173.01:46:23.60#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.01:46:23.60#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.01:46:23.60#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.01:46:23.60#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.01:46:23.60$vck44/vblo=7,734.99 2006.173.01:46:23.60#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.01:46:23.60#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.01:46:23.60#ibcon#ireg 17 cls_cnt 0 2006.173.01:46:23.60#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.01:46:23.60#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.01:46:23.60#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.01:46:23.60#ibcon#enter wrdev, iclass 24, count 0 2006.173.01:46:23.60#ibcon#first serial, iclass 24, count 0 2006.173.01:46:23.60#ibcon#enter sib2, iclass 24, count 0 2006.173.01:46:23.60#ibcon#flushed, iclass 24, count 0 2006.173.01:46:23.60#ibcon#about to write, iclass 24, count 0 2006.173.01:46:23.60#ibcon#wrote, iclass 24, count 0 2006.173.01:46:23.60#ibcon#about to read 3, iclass 24, count 0 2006.173.01:46:23.62#ibcon#read 3, iclass 24, count 0 2006.173.01:46:23.62#ibcon#about to read 4, iclass 24, count 0 2006.173.01:46:23.62#ibcon#read 4, iclass 24, count 0 2006.173.01:46:23.62#ibcon#about to read 5, iclass 24, count 0 2006.173.01:46:23.62#ibcon#read 5, iclass 24, count 0 2006.173.01:46:23.62#ibcon#about to read 6, iclass 24, count 0 2006.173.01:46:23.62#ibcon#read 6, iclass 24, count 0 2006.173.01:46:23.62#ibcon#end of sib2, iclass 24, count 0 2006.173.01:46:23.62#ibcon#*mode == 0, iclass 24, count 0 2006.173.01:46:23.62#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.01:46:23.62#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.01:46:23.62#ibcon#*before write, iclass 24, count 0 2006.173.01:46:23.62#ibcon#enter sib2, iclass 24, count 0 2006.173.01:46:23.62#ibcon#flushed, iclass 24, count 0 2006.173.01:46:23.62#ibcon#about to write, iclass 24, count 0 2006.173.01:46:23.62#ibcon#wrote, iclass 24, count 0 2006.173.01:46:23.62#ibcon#about to read 3, iclass 24, count 0 2006.173.01:46:23.66#ibcon#read 3, iclass 24, count 0 2006.173.01:46:23.66#ibcon#about to read 4, iclass 24, count 0 2006.173.01:46:23.66#ibcon#read 4, iclass 24, count 0 2006.173.01:46:23.66#ibcon#about to read 5, iclass 24, count 0 2006.173.01:46:23.66#ibcon#read 5, iclass 24, count 0 2006.173.01:46:23.66#ibcon#about to read 6, iclass 24, count 0 2006.173.01:46:23.66#ibcon#read 6, iclass 24, count 0 2006.173.01:46:23.66#ibcon#end of sib2, iclass 24, count 0 2006.173.01:46:23.66#ibcon#*after write, iclass 24, count 0 2006.173.01:46:23.66#ibcon#*before return 0, iclass 24, count 0 2006.173.01:46:23.66#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.01:46:23.66#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.01:46:23.66#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.01:46:23.66#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.01:46:23.66$vck44/vb=7,4 2006.173.01:46:23.66#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.01:46:23.66#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.01:46:23.66#ibcon#ireg 11 cls_cnt 2 2006.173.01:46:23.66#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.01:46:23.72#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.01:46:23.72#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.01:46:23.72#ibcon#enter wrdev, iclass 26, count 2 2006.173.01:46:23.72#ibcon#first serial, iclass 26, count 2 2006.173.01:46:23.72#ibcon#enter sib2, iclass 26, count 2 2006.173.01:46:23.72#ibcon#flushed, iclass 26, count 2 2006.173.01:46:23.72#ibcon#about to write, iclass 26, count 2 2006.173.01:46:23.72#ibcon#wrote, iclass 26, count 2 2006.173.01:46:23.72#ibcon#about to read 3, iclass 26, count 2 2006.173.01:46:23.74#ibcon#read 3, iclass 26, count 2 2006.173.01:46:23.74#ibcon#about to read 4, iclass 26, count 2 2006.173.01:46:23.74#ibcon#read 4, iclass 26, count 2 2006.173.01:46:23.74#ibcon#about to read 5, iclass 26, count 2 2006.173.01:46:23.74#ibcon#read 5, iclass 26, count 2 2006.173.01:46:23.74#ibcon#about to read 6, iclass 26, count 2 2006.173.01:46:23.74#ibcon#read 6, iclass 26, count 2 2006.173.01:46:23.74#ibcon#end of sib2, iclass 26, count 2 2006.173.01:46:23.74#ibcon#*mode == 0, iclass 26, count 2 2006.173.01:46:23.74#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.01:46:23.74#ibcon#[27=AT07-04\r\n] 2006.173.01:46:23.74#ibcon#*before write, iclass 26, count 2 2006.173.01:46:23.74#ibcon#enter sib2, iclass 26, count 2 2006.173.01:46:23.74#ibcon#flushed, iclass 26, count 2 2006.173.01:46:23.74#ibcon#about to write, iclass 26, count 2 2006.173.01:46:23.74#ibcon#wrote, iclass 26, count 2 2006.173.01:46:23.74#ibcon#about to read 3, iclass 26, count 2 2006.173.01:46:23.77#ibcon#read 3, iclass 26, count 2 2006.173.01:46:23.77#ibcon#about to read 4, iclass 26, count 2 2006.173.01:46:23.77#ibcon#read 4, iclass 26, count 2 2006.173.01:46:23.77#ibcon#about to read 5, iclass 26, count 2 2006.173.01:46:23.77#ibcon#read 5, iclass 26, count 2 2006.173.01:46:23.77#ibcon#about to read 6, iclass 26, count 2 2006.173.01:46:23.77#ibcon#read 6, iclass 26, count 2 2006.173.01:46:23.77#ibcon#end of sib2, iclass 26, count 2 2006.173.01:46:23.77#ibcon#*after write, iclass 26, count 2 2006.173.01:46:23.77#ibcon#*before return 0, iclass 26, count 2 2006.173.01:46:23.77#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.01:46:23.77#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.01:46:23.77#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.01:46:23.77#ibcon#ireg 7 cls_cnt 0 2006.173.01:46:23.77#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.01:46:23.89#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.01:46:23.89#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.01:46:23.89#ibcon#enter wrdev, iclass 26, count 0 2006.173.01:46:23.89#ibcon#first serial, iclass 26, count 0 2006.173.01:46:23.89#ibcon#enter sib2, iclass 26, count 0 2006.173.01:46:23.89#ibcon#flushed, iclass 26, count 0 2006.173.01:46:23.89#ibcon#about to write, iclass 26, count 0 2006.173.01:46:23.89#ibcon#wrote, iclass 26, count 0 2006.173.01:46:23.89#ibcon#about to read 3, iclass 26, count 0 2006.173.01:46:23.91#ibcon#read 3, iclass 26, count 0 2006.173.01:46:23.91#ibcon#about to read 4, iclass 26, count 0 2006.173.01:46:23.91#ibcon#read 4, iclass 26, count 0 2006.173.01:46:23.91#ibcon#about to read 5, iclass 26, count 0 2006.173.01:46:23.91#ibcon#read 5, iclass 26, count 0 2006.173.01:46:23.91#ibcon#about to read 6, iclass 26, count 0 2006.173.01:46:23.91#ibcon#read 6, iclass 26, count 0 2006.173.01:46:23.91#ibcon#end of sib2, iclass 26, count 0 2006.173.01:46:23.91#ibcon#*mode == 0, iclass 26, count 0 2006.173.01:46:23.91#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.01:46:23.91#ibcon#[27=USB\r\n] 2006.173.01:46:23.91#ibcon#*before write, iclass 26, count 0 2006.173.01:46:23.91#ibcon#enter sib2, iclass 26, count 0 2006.173.01:46:23.91#ibcon#flushed, iclass 26, count 0 2006.173.01:46:23.91#ibcon#about to write, iclass 26, count 0 2006.173.01:46:23.91#ibcon#wrote, iclass 26, count 0 2006.173.01:46:23.91#ibcon#about to read 3, iclass 26, count 0 2006.173.01:46:23.94#ibcon#read 3, iclass 26, count 0 2006.173.01:46:23.94#ibcon#about to read 4, iclass 26, count 0 2006.173.01:46:23.94#ibcon#read 4, iclass 26, count 0 2006.173.01:46:23.94#ibcon#about to read 5, iclass 26, count 0 2006.173.01:46:23.94#ibcon#read 5, iclass 26, count 0 2006.173.01:46:23.94#ibcon#about to read 6, iclass 26, count 0 2006.173.01:46:23.94#ibcon#read 6, iclass 26, count 0 2006.173.01:46:23.94#ibcon#end of sib2, iclass 26, count 0 2006.173.01:46:23.94#ibcon#*after write, iclass 26, count 0 2006.173.01:46:23.94#ibcon#*before return 0, iclass 26, count 0 2006.173.01:46:23.94#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.01:46:23.94#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.01:46:23.94#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.01:46:23.94#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.01:46:23.94$vck44/vblo=8,744.99 2006.173.01:46:23.94#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.01:46:23.94#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.01:46:23.94#ibcon#ireg 17 cls_cnt 0 2006.173.01:46:23.94#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.01:46:23.94#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.01:46:23.94#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.01:46:23.94#ibcon#enter wrdev, iclass 28, count 0 2006.173.01:46:23.94#ibcon#first serial, iclass 28, count 0 2006.173.01:46:23.94#ibcon#enter sib2, iclass 28, count 0 2006.173.01:46:23.94#ibcon#flushed, iclass 28, count 0 2006.173.01:46:23.94#ibcon#about to write, iclass 28, count 0 2006.173.01:46:23.94#ibcon#wrote, iclass 28, count 0 2006.173.01:46:23.94#ibcon#about to read 3, iclass 28, count 0 2006.173.01:46:23.96#ibcon#read 3, iclass 28, count 0 2006.173.01:46:23.96#ibcon#about to read 4, iclass 28, count 0 2006.173.01:46:23.96#ibcon#read 4, iclass 28, count 0 2006.173.01:46:23.96#ibcon#about to read 5, iclass 28, count 0 2006.173.01:46:23.96#ibcon#read 5, iclass 28, count 0 2006.173.01:46:23.96#ibcon#about to read 6, iclass 28, count 0 2006.173.01:46:23.96#ibcon#read 6, iclass 28, count 0 2006.173.01:46:23.96#ibcon#end of sib2, iclass 28, count 0 2006.173.01:46:23.96#ibcon#*mode == 0, iclass 28, count 0 2006.173.01:46:23.96#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.01:46:23.96#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.01:46:23.96#ibcon#*before write, iclass 28, count 0 2006.173.01:46:23.96#ibcon#enter sib2, iclass 28, count 0 2006.173.01:46:23.96#ibcon#flushed, iclass 28, count 0 2006.173.01:46:23.96#ibcon#about to write, iclass 28, count 0 2006.173.01:46:23.96#ibcon#wrote, iclass 28, count 0 2006.173.01:46:23.96#ibcon#about to read 3, iclass 28, count 0 2006.173.01:46:24.00#ibcon#read 3, iclass 28, count 0 2006.173.01:46:24.00#ibcon#about to read 4, iclass 28, count 0 2006.173.01:46:24.00#ibcon#read 4, iclass 28, count 0 2006.173.01:46:24.00#ibcon#about to read 5, iclass 28, count 0 2006.173.01:46:24.00#ibcon#read 5, iclass 28, count 0 2006.173.01:46:24.00#ibcon#about to read 6, iclass 28, count 0 2006.173.01:46:24.00#ibcon#read 6, iclass 28, count 0 2006.173.01:46:24.00#ibcon#end of sib2, iclass 28, count 0 2006.173.01:46:24.00#ibcon#*after write, iclass 28, count 0 2006.173.01:46:24.00#ibcon#*before return 0, iclass 28, count 0 2006.173.01:46:24.00#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.01:46:24.00#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.01:46:24.00#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.01:46:24.00#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.01:46:24.00$vck44/vb=8,4 2006.173.01:46:24.00#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.01:46:24.00#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.01:46:24.00#ibcon#ireg 11 cls_cnt 2 2006.173.01:46:24.00#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.01:46:24.06#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.01:46:24.06#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.01:46:24.06#ibcon#enter wrdev, iclass 30, count 2 2006.173.01:46:24.06#ibcon#first serial, iclass 30, count 2 2006.173.01:46:24.06#ibcon#enter sib2, iclass 30, count 2 2006.173.01:46:24.06#ibcon#flushed, iclass 30, count 2 2006.173.01:46:24.06#ibcon#about to write, iclass 30, count 2 2006.173.01:46:24.06#ibcon#wrote, iclass 30, count 2 2006.173.01:46:24.06#ibcon#about to read 3, iclass 30, count 2 2006.173.01:46:24.08#ibcon#read 3, iclass 30, count 2 2006.173.01:46:24.08#ibcon#about to read 4, iclass 30, count 2 2006.173.01:46:24.08#ibcon#read 4, iclass 30, count 2 2006.173.01:46:24.08#ibcon#about to read 5, iclass 30, count 2 2006.173.01:46:24.08#ibcon#read 5, iclass 30, count 2 2006.173.01:46:24.08#ibcon#about to read 6, iclass 30, count 2 2006.173.01:46:24.08#ibcon#read 6, iclass 30, count 2 2006.173.01:46:24.08#ibcon#end of sib2, iclass 30, count 2 2006.173.01:46:24.08#ibcon#*mode == 0, iclass 30, count 2 2006.173.01:46:24.08#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.01:46:24.08#ibcon#[27=AT08-04\r\n] 2006.173.01:46:24.08#ibcon#*before write, iclass 30, count 2 2006.173.01:46:24.08#ibcon#enter sib2, iclass 30, count 2 2006.173.01:46:24.08#ibcon#flushed, iclass 30, count 2 2006.173.01:46:24.08#ibcon#about to write, iclass 30, count 2 2006.173.01:46:24.08#ibcon#wrote, iclass 30, count 2 2006.173.01:46:24.08#ibcon#about to read 3, iclass 30, count 2 2006.173.01:46:24.11#ibcon#read 3, iclass 30, count 2 2006.173.01:46:24.11#ibcon#about to read 4, iclass 30, count 2 2006.173.01:46:24.11#ibcon#read 4, iclass 30, count 2 2006.173.01:46:24.11#ibcon#about to read 5, iclass 30, count 2 2006.173.01:46:24.11#ibcon#read 5, iclass 30, count 2 2006.173.01:46:24.11#ibcon#about to read 6, iclass 30, count 2 2006.173.01:46:24.11#ibcon#read 6, iclass 30, count 2 2006.173.01:46:24.11#ibcon#end of sib2, iclass 30, count 2 2006.173.01:46:24.11#ibcon#*after write, iclass 30, count 2 2006.173.01:46:24.11#ibcon#*before return 0, iclass 30, count 2 2006.173.01:46:24.11#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.01:46:24.11#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.01:46:24.11#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.01:46:24.11#ibcon#ireg 7 cls_cnt 0 2006.173.01:46:24.11#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.01:46:24.23#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.01:46:24.23#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.01:46:24.23#ibcon#enter wrdev, iclass 30, count 0 2006.173.01:46:24.23#ibcon#first serial, iclass 30, count 0 2006.173.01:46:24.23#ibcon#enter sib2, iclass 30, count 0 2006.173.01:46:24.23#ibcon#flushed, iclass 30, count 0 2006.173.01:46:24.23#ibcon#about to write, iclass 30, count 0 2006.173.01:46:24.23#ibcon#wrote, iclass 30, count 0 2006.173.01:46:24.23#ibcon#about to read 3, iclass 30, count 0 2006.173.01:46:24.25#ibcon#read 3, iclass 30, count 0 2006.173.01:46:24.25#ibcon#about to read 4, iclass 30, count 0 2006.173.01:46:24.25#ibcon#read 4, iclass 30, count 0 2006.173.01:46:24.25#ibcon#about to read 5, iclass 30, count 0 2006.173.01:46:24.25#ibcon#read 5, iclass 30, count 0 2006.173.01:46:24.25#ibcon#about to read 6, iclass 30, count 0 2006.173.01:46:24.25#ibcon#read 6, iclass 30, count 0 2006.173.01:46:24.25#ibcon#end of sib2, iclass 30, count 0 2006.173.01:46:24.25#ibcon#*mode == 0, iclass 30, count 0 2006.173.01:46:24.25#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.01:46:24.25#ibcon#[27=USB\r\n] 2006.173.01:46:24.25#ibcon#*before write, iclass 30, count 0 2006.173.01:46:24.25#ibcon#enter sib2, iclass 30, count 0 2006.173.01:46:24.25#ibcon#flushed, iclass 30, count 0 2006.173.01:46:24.25#ibcon#about to write, iclass 30, count 0 2006.173.01:46:24.25#ibcon#wrote, iclass 30, count 0 2006.173.01:46:24.25#ibcon#about to read 3, iclass 30, count 0 2006.173.01:46:24.28#ibcon#read 3, iclass 30, count 0 2006.173.01:46:24.28#ibcon#about to read 4, iclass 30, count 0 2006.173.01:46:24.28#ibcon#read 4, iclass 30, count 0 2006.173.01:46:24.28#ibcon#about to read 5, iclass 30, count 0 2006.173.01:46:24.28#ibcon#read 5, iclass 30, count 0 2006.173.01:46:24.28#ibcon#about to read 6, iclass 30, count 0 2006.173.01:46:24.28#ibcon#read 6, iclass 30, count 0 2006.173.01:46:24.28#ibcon#end of sib2, iclass 30, count 0 2006.173.01:46:24.28#ibcon#*after write, iclass 30, count 0 2006.173.01:46:24.28#ibcon#*before return 0, iclass 30, count 0 2006.173.01:46:24.28#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.01:46:24.28#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.01:46:24.28#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.01:46:24.28#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.01:46:24.28$vck44/vabw=wide 2006.173.01:46:24.28#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.01:46:24.28#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.01:46:24.28#ibcon#ireg 8 cls_cnt 0 2006.173.01:46:24.28#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.01:46:24.28#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.01:46:24.28#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.01:46:24.28#ibcon#enter wrdev, iclass 32, count 0 2006.173.01:46:24.28#ibcon#first serial, iclass 32, count 0 2006.173.01:46:24.28#ibcon#enter sib2, iclass 32, count 0 2006.173.01:46:24.28#ibcon#flushed, iclass 32, count 0 2006.173.01:46:24.28#ibcon#about to write, iclass 32, count 0 2006.173.01:46:24.28#ibcon#wrote, iclass 32, count 0 2006.173.01:46:24.28#ibcon#about to read 3, iclass 32, count 0 2006.173.01:46:24.30#ibcon#read 3, iclass 32, count 0 2006.173.01:46:24.30#ibcon#about to read 4, iclass 32, count 0 2006.173.01:46:24.30#ibcon#read 4, iclass 32, count 0 2006.173.01:46:24.30#ibcon#about to read 5, iclass 32, count 0 2006.173.01:46:24.30#ibcon#read 5, iclass 32, count 0 2006.173.01:46:24.30#ibcon#about to read 6, iclass 32, count 0 2006.173.01:46:24.30#ibcon#read 6, iclass 32, count 0 2006.173.01:46:24.30#ibcon#end of sib2, iclass 32, count 0 2006.173.01:46:24.30#ibcon#*mode == 0, iclass 32, count 0 2006.173.01:46:24.30#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.01:46:24.30#ibcon#[25=BW32\r\n] 2006.173.01:46:24.30#ibcon#*before write, iclass 32, count 0 2006.173.01:46:24.30#ibcon#enter sib2, iclass 32, count 0 2006.173.01:46:24.30#ibcon#flushed, iclass 32, count 0 2006.173.01:46:24.30#ibcon#about to write, iclass 32, count 0 2006.173.01:46:24.30#ibcon#wrote, iclass 32, count 0 2006.173.01:46:24.30#ibcon#about to read 3, iclass 32, count 0 2006.173.01:46:24.33#ibcon#read 3, iclass 32, count 0 2006.173.01:46:24.33#ibcon#about to read 4, iclass 32, count 0 2006.173.01:46:24.33#ibcon#read 4, iclass 32, count 0 2006.173.01:46:24.33#ibcon#about to read 5, iclass 32, count 0 2006.173.01:46:24.33#ibcon#read 5, iclass 32, count 0 2006.173.01:46:24.33#ibcon#about to read 6, iclass 32, count 0 2006.173.01:46:24.33#ibcon#read 6, iclass 32, count 0 2006.173.01:46:24.33#ibcon#end of sib2, iclass 32, count 0 2006.173.01:46:24.33#ibcon#*after write, iclass 32, count 0 2006.173.01:46:24.33#ibcon#*before return 0, iclass 32, count 0 2006.173.01:46:24.33#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.01:46:24.33#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.01:46:24.33#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.01:46:24.33#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.01:46:24.33$vck44/vbbw=wide 2006.173.01:46:24.33#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.01:46:24.33#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.01:46:24.33#ibcon#ireg 8 cls_cnt 0 2006.173.01:46:24.33#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.01:46:24.40#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.01:46:24.40#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.01:46:24.40#ibcon#enter wrdev, iclass 34, count 0 2006.173.01:46:24.40#ibcon#first serial, iclass 34, count 0 2006.173.01:46:24.40#ibcon#enter sib2, iclass 34, count 0 2006.173.01:46:24.40#ibcon#flushed, iclass 34, count 0 2006.173.01:46:24.40#ibcon#about to write, iclass 34, count 0 2006.173.01:46:24.40#ibcon#wrote, iclass 34, count 0 2006.173.01:46:24.40#ibcon#about to read 3, iclass 34, count 0 2006.173.01:46:24.42#ibcon#read 3, iclass 34, count 0 2006.173.01:46:24.42#ibcon#about to read 4, iclass 34, count 0 2006.173.01:46:24.42#ibcon#read 4, iclass 34, count 0 2006.173.01:46:24.42#ibcon#about to read 5, iclass 34, count 0 2006.173.01:46:24.42#ibcon#read 5, iclass 34, count 0 2006.173.01:46:24.42#ibcon#about to read 6, iclass 34, count 0 2006.173.01:46:24.42#ibcon#read 6, iclass 34, count 0 2006.173.01:46:24.42#ibcon#end of sib2, iclass 34, count 0 2006.173.01:46:24.42#ibcon#*mode == 0, iclass 34, count 0 2006.173.01:46:24.42#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.01:46:24.42#ibcon#[27=BW32\r\n] 2006.173.01:46:24.42#ibcon#*before write, iclass 34, count 0 2006.173.01:46:24.42#ibcon#enter sib2, iclass 34, count 0 2006.173.01:46:24.42#ibcon#flushed, iclass 34, count 0 2006.173.01:46:24.42#ibcon#about to write, iclass 34, count 0 2006.173.01:46:24.42#ibcon#wrote, iclass 34, count 0 2006.173.01:46:24.42#ibcon#about to read 3, iclass 34, count 0 2006.173.01:46:24.45#ibcon#read 3, iclass 34, count 0 2006.173.01:46:24.45#ibcon#about to read 4, iclass 34, count 0 2006.173.01:46:24.45#ibcon#read 4, iclass 34, count 0 2006.173.01:46:24.45#ibcon#about to read 5, iclass 34, count 0 2006.173.01:46:24.45#ibcon#read 5, iclass 34, count 0 2006.173.01:46:24.45#ibcon#about to read 6, iclass 34, count 0 2006.173.01:46:24.45#ibcon#read 6, iclass 34, count 0 2006.173.01:46:24.45#ibcon#end of sib2, iclass 34, count 0 2006.173.01:46:24.45#ibcon#*after write, iclass 34, count 0 2006.173.01:46:24.45#ibcon#*before return 0, iclass 34, count 0 2006.173.01:46:24.45#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.01:46:24.45#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.01:46:24.45#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.01:46:24.45#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.01:46:24.45$setupk4/ifdk4 2006.173.01:46:24.45&ifdk4/lo= 2006.173.01:46:24.45&ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.01:46:24.45&ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.01:46:24.45&ifdk4/patch= 2006.173.01:46:24.45&ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.01:46:24.45&ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.01:46:24.45$ifdk4/lo= 2006.173.01:46:24.45$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.01:46:24.45$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.01:46:24.45$ifdk4/patch= 2006.173.01:46:24.45$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.01:46:24.45$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.01:46:24.45$setupk4/!*+20s 2006.173.01:46:24.45$exper_initi/proc_library 2006.173.01:46:24.45&proc_library/" jd0606 tsukub32 ts 2006.173.01:46:24.45&proc_library/" drudg version 050216 compiled under fs 9.7.7 2006.173.01:46:24.45&proc_library/"< k4-2/m4 rack >< k4-2 recorder 1> 2006.173.01:46:24.45$proc_library/" jd0606 tsukub32 ts 2006.173.01:46:24.45$proc_library/" drudg version 050216 compiled under fs 9.7.7 2006.173.01:46:24.45$proc_library/"< k4-2/m4 rack >< k4-2 recorder 1> 2006.173.01:46:24.45$exper_initi/sched_initi 2006.173.01:46:24.45&sched_initi/startcheck 2006.173.01:46:24.45$sched_initi/startcheck 2006.173.01:46:24.45&startcheck/sy=check_fsrun.pl & 2006.173.01:46:24.45&startcheck/" sy=/usr2/oper/temp/chmem.sh >& /dev/null & 2006.173.01:46:24.45$startcheck/sy=check_fsrun.pl & 2006.173.01:46:24.49$startcheck/" sy=/usr2/oper/temp/chmem.sh >& /dev/null & 2006.173.01:46:32.10#abcon#<5=/14 1.4 3.7 22.39 841006.9\r\n> 2006.173.01:46:32.12#abcon#{5=INTERFACE CLEAR} 2006.173.01:46:32.19#abcon#[5=S1D000X0/0*\r\n] 2006.173.01:46:34.14#trakl#Source acquired 2006.173.01:46:36.14#flagr#flagr/antenna,acquired 2006.173.01:46:38.92$setupk4/"tpicd 2006.173.01:46:38.92$setupk4/echo=off 2006.173.01:46:38.92$setupk4/xlog=off 2006.173.01:46:38.92:"ready=1 2006.173.01:46:38.92:setupk4=1 2006.173.01:46:38.92$setupk4/echo=on 2006.173.01:46:38.92$setupk4/pcalon 2006.173.01:46:38.92$pcalon/"no phase cal control is implemented here 2006.173.01:46:38.92$setupk4/"tpicd=stop 2006.173.01:46:38.92$setupk4/"rec=synch_on 2006.173.01:46:38.92$setupk4/"rec_mode=128 2006.173.01:46:38.92$setupk4/!* 2006.173.01:46:38.92$setupk4/recpk4 2006.173.01:46:38.92$recpk4/recpatch= 2006.173.01:46:38.92$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.01:46:38.92$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.01:46:38.92$setupk4/vck44 2006.173.01:46:38.92$vck44/valo=1,524.99 2006.173.01:46:38.92#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.01:46:38.92#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.01:46:38.92#ibcon#ireg 17 cls_cnt 0 2006.173.01:46:38.92#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.01:46:38.92#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.01:46:38.92#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.01:46:38.92#ibcon#enter wrdev, iclass 26, count 0 2006.173.01:46:38.92#ibcon#first serial, iclass 26, count 0 2006.173.01:46:38.92#ibcon#enter sib2, iclass 26, count 0 2006.173.01:46:38.92#ibcon#flushed, iclass 26, count 0 2006.173.01:46:38.92#ibcon#about to write, iclass 26, count 0 2006.173.01:46:38.92#ibcon#wrote, iclass 26, count 0 2006.173.01:46:38.92#ibcon#about to read 3, iclass 26, count 0 2006.173.01:46:38.94#ibcon#read 3, iclass 26, count 0 2006.173.01:46:38.94#ibcon#about to read 4, iclass 26, count 0 2006.173.01:46:38.94#ibcon#read 4, iclass 26, count 0 2006.173.01:46:38.94#ibcon#about to read 5, iclass 26, count 0 2006.173.01:46:38.94#ibcon#read 5, iclass 26, count 0 2006.173.01:46:38.94#ibcon#about to read 6, iclass 26, count 0 2006.173.01:46:38.94#ibcon#read 6, iclass 26, count 0 2006.173.01:46:38.94#ibcon#end of sib2, iclass 26, count 0 2006.173.01:46:38.94#ibcon#*mode == 0, iclass 26, count 0 2006.173.01:46:38.94#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.01:46:38.94#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.01:46:38.94#ibcon#*before write, iclass 26, count 0 2006.173.01:46:38.94#ibcon#enter sib2, iclass 26, count 0 2006.173.01:46:38.94#ibcon#flushed, iclass 26, count 0 2006.173.01:46:38.94#ibcon#about to write, iclass 26, count 0 2006.173.01:46:38.94#ibcon#wrote, iclass 26, count 0 2006.173.01:46:38.94#ibcon#about to read 3, iclass 26, count 0 2006.173.01:46:38.98#ibcon#read 3, iclass 26, count 0 2006.173.01:46:38.98#ibcon#about to read 4, iclass 26, count 0 2006.173.01:46:38.98#ibcon#read 4, iclass 26, count 0 2006.173.01:46:38.98#ibcon#about to read 5, iclass 26, count 0 2006.173.01:46:38.98#ibcon#read 5, iclass 26, count 0 2006.173.01:46:38.98#ibcon#about to read 6, iclass 26, count 0 2006.173.01:46:38.98#ibcon#read 6, iclass 26, count 0 2006.173.01:46:38.98#ibcon#end of sib2, iclass 26, count 0 2006.173.01:46:38.98#ibcon#*after write, iclass 26, count 0 2006.173.01:46:38.98#ibcon#*before return 0, iclass 26, count 0 2006.173.01:46:38.98#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.01:46:38.98#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.01:46:38.98#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.01:46:38.98#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.01:46:38.99$vck44/va=1,7 2006.173.01:46:38.99#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.01:46:38.99#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.01:46:38.99#ibcon#ireg 11 cls_cnt 2 2006.173.01:46:38.99#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.01:46:38.99#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.01:46:38.99#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.01:46:38.99#ibcon#enter wrdev, iclass 28, count 2 2006.173.01:46:38.99#ibcon#first serial, iclass 28, count 2 2006.173.01:46:38.99#ibcon#enter sib2, iclass 28, count 2 2006.173.01:46:38.99#ibcon#flushed, iclass 28, count 2 2006.173.01:46:38.99#ibcon#about to write, iclass 28, count 2 2006.173.01:46:38.99#ibcon#wrote, iclass 28, count 2 2006.173.01:46:38.99#ibcon#about to read 3, iclass 28, count 2 2006.173.01:46:39.01#ibcon#read 3, iclass 28, count 2 2006.173.01:46:39.01#ibcon#about to read 4, iclass 28, count 2 2006.173.01:46:39.01#ibcon#read 4, iclass 28, count 2 2006.173.01:46:39.01#ibcon#about to read 5, iclass 28, count 2 2006.173.01:46:39.01#ibcon#read 5, iclass 28, count 2 2006.173.01:46:39.01#ibcon#about to read 6, iclass 28, count 2 2006.173.01:46:39.01#ibcon#read 6, iclass 28, count 2 2006.173.01:46:39.01#ibcon#end of sib2, iclass 28, count 2 2006.173.01:46:39.01#ibcon#*mode == 0, iclass 28, count 2 2006.173.01:46:39.01#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.01:46:39.01#ibcon#[25=AT01-07\r\n] 2006.173.01:46:39.01#ibcon#*before write, iclass 28, count 2 2006.173.01:46:39.01#ibcon#enter sib2, iclass 28, count 2 2006.173.01:46:39.01#ibcon#flushed, iclass 28, count 2 2006.173.01:46:39.01#ibcon#about to write, iclass 28, count 2 2006.173.01:46:39.01#ibcon#wrote, iclass 28, count 2 2006.173.01:46:39.01#ibcon#about to read 3, iclass 28, count 2 2006.173.01:46:39.04#ibcon#read 3, iclass 28, count 2 2006.173.01:46:39.04#ibcon#about to read 4, iclass 28, count 2 2006.173.01:46:39.04#ibcon#read 4, iclass 28, count 2 2006.173.01:46:39.04#ibcon#about to read 5, iclass 28, count 2 2006.173.01:46:39.04#ibcon#read 5, iclass 28, count 2 2006.173.01:46:39.04#ibcon#about to read 6, iclass 28, count 2 2006.173.01:46:39.04#ibcon#read 6, iclass 28, count 2 2006.173.01:46:39.04#ibcon#end of sib2, iclass 28, count 2 2006.173.01:46:39.04#ibcon#*after write, iclass 28, count 2 2006.173.01:46:39.04#ibcon#*before return 0, iclass 28, count 2 2006.173.01:46:39.04#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.01:46:39.04#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.01:46:39.04#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.01:46:39.04#ibcon#ireg 7 cls_cnt 0 2006.173.01:46:39.04#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.01:46:39.16#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.01:46:39.16#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.01:46:39.16#ibcon#enter wrdev, iclass 28, count 0 2006.173.01:46:39.16#ibcon#first serial, iclass 28, count 0 2006.173.01:46:39.16#ibcon#enter sib2, iclass 28, count 0 2006.173.01:46:39.16#ibcon#flushed, iclass 28, count 0 2006.173.01:46:39.16#ibcon#about to write, iclass 28, count 0 2006.173.01:46:39.16#ibcon#wrote, iclass 28, count 0 2006.173.01:46:39.16#ibcon#about to read 3, iclass 28, count 0 2006.173.01:46:39.18#ibcon#read 3, iclass 28, count 0 2006.173.01:46:39.18#ibcon#about to read 4, iclass 28, count 0 2006.173.01:46:39.18#ibcon#read 4, iclass 28, count 0 2006.173.01:46:39.18#ibcon#about to read 5, iclass 28, count 0 2006.173.01:46:39.18#ibcon#read 5, iclass 28, count 0 2006.173.01:46:39.18#ibcon#about to read 6, iclass 28, count 0 2006.173.01:46:39.18#ibcon#read 6, iclass 28, count 0 2006.173.01:46:39.18#ibcon#end of sib2, iclass 28, count 0 2006.173.01:46:39.18#ibcon#*mode == 0, iclass 28, count 0 2006.173.01:46:39.18#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.01:46:39.18#ibcon#[25=USB\r\n] 2006.173.01:46:39.18#ibcon#*before write, iclass 28, count 0 2006.173.01:46:39.18#ibcon#enter sib2, iclass 28, count 0 2006.173.01:46:39.18#ibcon#flushed, iclass 28, count 0 2006.173.01:46:39.18#ibcon#about to write, iclass 28, count 0 2006.173.01:46:39.18#ibcon#wrote, iclass 28, count 0 2006.173.01:46:39.18#ibcon#about to read 3, iclass 28, count 0 2006.173.01:46:39.21#ibcon#read 3, iclass 28, count 0 2006.173.01:46:39.21#ibcon#about to read 4, iclass 28, count 0 2006.173.01:46:39.21#ibcon#read 4, iclass 28, count 0 2006.173.01:46:39.21#ibcon#about to read 5, iclass 28, count 0 2006.173.01:46:39.21#ibcon#read 5, iclass 28, count 0 2006.173.01:46:39.21#ibcon#about to read 6, iclass 28, count 0 2006.173.01:46:39.21#ibcon#read 6, iclass 28, count 0 2006.173.01:46:39.21#ibcon#end of sib2, iclass 28, count 0 2006.173.01:46:39.21#ibcon#*after write, iclass 28, count 0 2006.173.01:46:39.21#ibcon#*before return 0, iclass 28, count 0 2006.173.01:46:39.21#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.01:46:39.21#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.01:46:39.21#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.01:46:39.21#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.01:46:39.21$vck44/valo=2,534.99 2006.173.01:46:39.21#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.01:46:39.21#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.01:46:39.21#ibcon#ireg 17 cls_cnt 0 2006.173.01:46:39.21#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.01:46:39.21#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.01:46:39.21#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.01:46:39.21#ibcon#enter wrdev, iclass 30, count 0 2006.173.01:46:39.21#ibcon#first serial, iclass 30, count 0 2006.173.01:46:39.21#ibcon#enter sib2, iclass 30, count 0 2006.173.01:46:39.21#ibcon#flushed, iclass 30, count 0 2006.173.01:46:39.21#ibcon#about to write, iclass 30, count 0 2006.173.01:46:39.21#ibcon#wrote, iclass 30, count 0 2006.173.01:46:39.21#ibcon#about to read 3, iclass 30, count 0 2006.173.01:46:39.23#ibcon#read 3, iclass 30, count 0 2006.173.01:46:39.23#ibcon#about to read 4, iclass 30, count 0 2006.173.01:46:39.23#ibcon#read 4, iclass 30, count 0 2006.173.01:46:39.23#ibcon#about to read 5, iclass 30, count 0 2006.173.01:46:39.23#ibcon#read 5, iclass 30, count 0 2006.173.01:46:39.23#ibcon#about to read 6, iclass 30, count 0 2006.173.01:46:39.23#ibcon#read 6, iclass 30, count 0 2006.173.01:46:39.23#ibcon#end of sib2, iclass 30, count 0 2006.173.01:46:39.23#ibcon#*mode == 0, iclass 30, count 0 2006.173.01:46:39.23#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.01:46:39.23#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.01:46:39.23#ibcon#*before write, iclass 30, count 0 2006.173.01:46:39.23#ibcon#enter sib2, iclass 30, count 0 2006.173.01:46:39.23#ibcon#flushed, iclass 30, count 0 2006.173.01:46:39.23#ibcon#about to write, iclass 30, count 0 2006.173.01:46:39.23#ibcon#wrote, iclass 30, count 0 2006.173.01:46:39.23#ibcon#about to read 3, iclass 30, count 0 2006.173.01:46:39.27#ibcon#read 3, iclass 30, count 0 2006.173.01:46:39.27#ibcon#about to read 4, iclass 30, count 0 2006.173.01:46:39.27#ibcon#read 4, iclass 30, count 0 2006.173.01:46:39.27#ibcon#about to read 5, iclass 30, count 0 2006.173.01:46:39.27#ibcon#read 5, iclass 30, count 0 2006.173.01:46:39.27#ibcon#about to read 6, iclass 30, count 0 2006.173.01:46:39.27#ibcon#read 6, iclass 30, count 0 2006.173.01:46:39.27#ibcon#end of sib2, iclass 30, count 0 2006.173.01:46:39.27#ibcon#*after write, iclass 30, count 0 2006.173.01:46:39.27#ibcon#*before return 0, iclass 30, count 0 2006.173.01:46:39.27#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.01:46:39.27#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.01:46:39.27#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.01:46:39.27#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.01:46:39.27$vck44/va=2,6 2006.173.01:46:39.27#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.173.01:46:39.27#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.173.01:46:39.27#ibcon#ireg 11 cls_cnt 2 2006.173.01:46:39.27#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.01:46:39.33#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.01:46:39.33#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.01:46:39.33#ibcon#enter wrdev, iclass 32, count 2 2006.173.01:46:39.33#ibcon#first serial, iclass 32, count 2 2006.173.01:46:39.33#ibcon#enter sib2, iclass 32, count 2 2006.173.01:46:39.33#ibcon#flushed, iclass 32, count 2 2006.173.01:46:39.33#ibcon#about to write, iclass 32, count 2 2006.173.01:46:39.33#ibcon#wrote, iclass 32, count 2 2006.173.01:46:39.33#ibcon#about to read 3, iclass 32, count 2 2006.173.01:46:39.35#ibcon#read 3, iclass 32, count 2 2006.173.01:46:39.35#ibcon#about to read 4, iclass 32, count 2 2006.173.01:46:39.35#ibcon#read 4, iclass 32, count 2 2006.173.01:46:39.35#ibcon#about to read 5, iclass 32, count 2 2006.173.01:46:39.35#ibcon#read 5, iclass 32, count 2 2006.173.01:46:39.35#ibcon#about to read 6, iclass 32, count 2 2006.173.01:46:39.35#ibcon#read 6, iclass 32, count 2 2006.173.01:46:39.35#ibcon#end of sib2, iclass 32, count 2 2006.173.01:46:39.35#ibcon#*mode == 0, iclass 32, count 2 2006.173.01:46:39.35#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.173.01:46:39.35#ibcon#[25=AT02-06\r\n] 2006.173.01:46:39.35#ibcon#*before write, iclass 32, count 2 2006.173.01:46:39.35#ibcon#enter sib2, iclass 32, count 2 2006.173.01:46:39.35#ibcon#flushed, iclass 32, count 2 2006.173.01:46:39.35#ibcon#about to write, iclass 32, count 2 2006.173.01:46:39.35#ibcon#wrote, iclass 32, count 2 2006.173.01:46:39.35#ibcon#about to read 3, iclass 32, count 2 2006.173.01:46:39.38#ibcon#read 3, iclass 32, count 2 2006.173.01:46:39.38#ibcon#about to read 4, iclass 32, count 2 2006.173.01:46:39.38#ibcon#read 4, iclass 32, count 2 2006.173.01:46:39.38#ibcon#about to read 5, iclass 32, count 2 2006.173.01:46:39.38#ibcon#read 5, iclass 32, count 2 2006.173.01:46:39.38#ibcon#about to read 6, iclass 32, count 2 2006.173.01:46:39.38#ibcon#read 6, iclass 32, count 2 2006.173.01:46:39.38#ibcon#end of sib2, iclass 32, count 2 2006.173.01:46:39.38#ibcon#*after write, iclass 32, count 2 2006.173.01:46:39.38#ibcon#*before return 0, iclass 32, count 2 2006.173.01:46:39.38#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.01:46:39.38#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.173.01:46:39.38#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.173.01:46:39.38#ibcon#ireg 7 cls_cnt 0 2006.173.01:46:39.38#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.01:46:39.50#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.01:46:39.50#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.01:46:39.50#ibcon#enter wrdev, iclass 32, count 0 2006.173.01:46:39.50#ibcon#first serial, iclass 32, count 0 2006.173.01:46:39.50#ibcon#enter sib2, iclass 32, count 0 2006.173.01:46:39.50#ibcon#flushed, iclass 32, count 0 2006.173.01:46:39.50#ibcon#about to write, iclass 32, count 0 2006.173.01:46:39.50#ibcon#wrote, iclass 32, count 0 2006.173.01:46:39.50#ibcon#about to read 3, iclass 32, count 0 2006.173.01:46:39.52#ibcon#read 3, iclass 32, count 0 2006.173.01:46:39.52#ibcon#about to read 4, iclass 32, count 0 2006.173.01:46:39.52#ibcon#read 4, iclass 32, count 0 2006.173.01:46:39.52#ibcon#about to read 5, iclass 32, count 0 2006.173.01:46:39.52#ibcon#read 5, iclass 32, count 0 2006.173.01:46:39.52#ibcon#about to read 6, iclass 32, count 0 2006.173.01:46:39.52#ibcon#read 6, iclass 32, count 0 2006.173.01:46:39.52#ibcon#end of sib2, iclass 32, count 0 2006.173.01:46:39.52#ibcon#*mode == 0, iclass 32, count 0 2006.173.01:46:39.52#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.01:46:39.52#ibcon#[25=USB\r\n] 2006.173.01:46:39.52#ibcon#*before write, iclass 32, count 0 2006.173.01:46:39.52#ibcon#enter sib2, iclass 32, count 0 2006.173.01:46:39.52#ibcon#flushed, iclass 32, count 0 2006.173.01:46:39.52#ibcon#about to write, iclass 32, count 0 2006.173.01:46:39.52#ibcon#wrote, iclass 32, count 0 2006.173.01:46:39.52#ibcon#about to read 3, iclass 32, count 0 2006.173.01:46:39.55#ibcon#read 3, iclass 32, count 0 2006.173.01:46:39.55#ibcon#about to read 4, iclass 32, count 0 2006.173.01:46:39.55#ibcon#read 4, iclass 32, count 0 2006.173.01:46:39.55#ibcon#about to read 5, iclass 32, count 0 2006.173.01:46:39.55#ibcon#read 5, iclass 32, count 0 2006.173.01:46:39.55#ibcon#about to read 6, iclass 32, count 0 2006.173.01:46:39.55#ibcon#read 6, iclass 32, count 0 2006.173.01:46:39.55#ibcon#end of sib2, iclass 32, count 0 2006.173.01:46:39.55#ibcon#*after write, iclass 32, count 0 2006.173.01:46:39.55#ibcon#*before return 0, iclass 32, count 0 2006.173.01:46:39.55#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.01:46:39.55#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.173.01:46:39.55#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.01:46:39.55#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.01:46:39.55$vck44/valo=3,564.99 2006.173.01:46:39.55#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.01:46:39.55#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.01:46:39.55#ibcon#ireg 17 cls_cnt 0 2006.173.01:46:39.55#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.01:46:39.55#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.01:46:39.55#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.01:46:39.55#ibcon#enter wrdev, iclass 34, count 0 2006.173.01:46:39.55#ibcon#first serial, iclass 34, count 0 2006.173.01:46:39.55#ibcon#enter sib2, iclass 34, count 0 2006.173.01:46:39.55#ibcon#flushed, iclass 34, count 0 2006.173.01:46:39.55#ibcon#about to write, iclass 34, count 0 2006.173.01:46:39.55#ibcon#wrote, iclass 34, count 0 2006.173.01:46:39.55#ibcon#about to read 3, iclass 34, count 0 2006.173.01:46:39.57#ibcon#read 3, iclass 34, count 0 2006.173.01:46:39.57#ibcon#about to read 4, iclass 34, count 0 2006.173.01:46:39.57#ibcon#read 4, iclass 34, count 0 2006.173.01:46:39.57#ibcon#about to read 5, iclass 34, count 0 2006.173.01:46:39.57#ibcon#read 5, iclass 34, count 0 2006.173.01:46:39.57#ibcon#about to read 6, iclass 34, count 0 2006.173.01:46:39.57#ibcon#read 6, iclass 34, count 0 2006.173.01:46:39.57#ibcon#end of sib2, iclass 34, count 0 2006.173.01:46:39.57#ibcon#*mode == 0, iclass 34, count 0 2006.173.01:46:39.57#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.01:46:39.57#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.01:46:39.57#ibcon#*before write, iclass 34, count 0 2006.173.01:46:39.57#ibcon#enter sib2, iclass 34, count 0 2006.173.01:46:39.57#ibcon#flushed, iclass 34, count 0 2006.173.01:46:39.57#ibcon#about to write, iclass 34, count 0 2006.173.01:46:39.57#ibcon#wrote, iclass 34, count 0 2006.173.01:46:39.57#ibcon#about to read 3, iclass 34, count 0 2006.173.01:46:39.61#ibcon#read 3, iclass 34, count 0 2006.173.01:46:39.61#ibcon#about to read 4, iclass 34, count 0 2006.173.01:46:39.61#ibcon#read 4, iclass 34, count 0 2006.173.01:46:39.61#ibcon#about to read 5, iclass 34, count 0 2006.173.01:46:39.61#ibcon#read 5, iclass 34, count 0 2006.173.01:46:39.61#ibcon#about to read 6, iclass 34, count 0 2006.173.01:46:39.61#ibcon#read 6, iclass 34, count 0 2006.173.01:46:39.61#ibcon#end of sib2, iclass 34, count 0 2006.173.01:46:39.61#ibcon#*after write, iclass 34, count 0 2006.173.01:46:39.61#ibcon#*before return 0, iclass 34, count 0 2006.173.01:46:39.61#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.01:46:39.61#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.01:46:39.61#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.01:46:39.61#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.01:46:39.61$vck44/va=3,5 2006.173.01:46:39.61#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.01:46:39.61#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.01:46:39.62#ibcon#ireg 11 cls_cnt 2 2006.173.01:46:39.62#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.01:46:39.66#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.01:46:39.66#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.01:46:39.66#ibcon#enter wrdev, iclass 36, count 2 2006.173.01:46:39.66#ibcon#first serial, iclass 36, count 2 2006.173.01:46:39.66#ibcon#enter sib2, iclass 36, count 2 2006.173.01:46:39.66#ibcon#flushed, iclass 36, count 2 2006.173.01:46:39.66#ibcon#about to write, iclass 36, count 2 2006.173.01:46:39.66#ibcon#wrote, iclass 36, count 2 2006.173.01:46:39.66#ibcon#about to read 3, iclass 36, count 2 2006.173.01:46:39.68#ibcon#read 3, iclass 36, count 2 2006.173.01:46:39.68#ibcon#about to read 4, iclass 36, count 2 2006.173.01:46:39.68#ibcon#read 4, iclass 36, count 2 2006.173.01:46:39.68#ibcon#about to read 5, iclass 36, count 2 2006.173.01:46:39.68#ibcon#read 5, iclass 36, count 2 2006.173.01:46:39.68#ibcon#about to read 6, iclass 36, count 2 2006.173.01:46:39.68#ibcon#read 6, iclass 36, count 2 2006.173.01:46:39.68#ibcon#end of sib2, iclass 36, count 2 2006.173.01:46:39.68#ibcon#*mode == 0, iclass 36, count 2 2006.173.01:46:39.68#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.01:46:39.68#ibcon#[25=AT03-05\r\n] 2006.173.01:46:39.68#ibcon#*before write, iclass 36, count 2 2006.173.01:46:39.68#ibcon#enter sib2, iclass 36, count 2 2006.173.01:46:39.68#ibcon#flushed, iclass 36, count 2 2006.173.01:46:39.68#ibcon#about to write, iclass 36, count 2 2006.173.01:46:39.68#ibcon#wrote, iclass 36, count 2 2006.173.01:46:39.68#ibcon#about to read 3, iclass 36, count 2 2006.173.01:46:39.71#ibcon#read 3, iclass 36, count 2 2006.173.01:46:39.71#ibcon#about to read 4, iclass 36, count 2 2006.173.01:46:39.71#ibcon#read 4, iclass 36, count 2 2006.173.01:46:39.71#ibcon#about to read 5, iclass 36, count 2 2006.173.01:46:39.71#ibcon#read 5, iclass 36, count 2 2006.173.01:46:39.71#ibcon#about to read 6, iclass 36, count 2 2006.173.01:46:39.71#ibcon#read 6, iclass 36, count 2 2006.173.01:46:39.71#ibcon#end of sib2, iclass 36, count 2 2006.173.01:46:39.71#ibcon#*after write, iclass 36, count 2 2006.173.01:46:39.71#ibcon#*before return 0, iclass 36, count 2 2006.173.01:46:39.71#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.01:46:39.71#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.01:46:39.71#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.01:46:39.71#ibcon#ireg 7 cls_cnt 0 2006.173.01:46:39.71#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.01:46:39.83#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.01:46:39.83#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.01:46:39.83#ibcon#enter wrdev, iclass 36, count 0 2006.173.01:46:39.83#ibcon#first serial, iclass 36, count 0 2006.173.01:46:39.83#ibcon#enter sib2, iclass 36, count 0 2006.173.01:46:39.83#ibcon#flushed, iclass 36, count 0 2006.173.01:46:39.83#ibcon#about to write, iclass 36, count 0 2006.173.01:46:39.83#ibcon#wrote, iclass 36, count 0 2006.173.01:46:39.83#ibcon#about to read 3, iclass 36, count 0 2006.173.01:46:39.85#ibcon#read 3, iclass 36, count 0 2006.173.01:46:39.85#ibcon#about to read 4, iclass 36, count 0 2006.173.01:46:39.85#ibcon#read 4, iclass 36, count 0 2006.173.01:46:39.85#ibcon#about to read 5, iclass 36, count 0 2006.173.01:46:39.85#ibcon#read 5, iclass 36, count 0 2006.173.01:46:39.85#ibcon#about to read 6, iclass 36, count 0 2006.173.01:46:39.85#ibcon#read 6, iclass 36, count 0 2006.173.01:46:39.85#ibcon#end of sib2, iclass 36, count 0 2006.173.01:46:39.85#ibcon#*mode == 0, iclass 36, count 0 2006.173.01:46:39.85#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.01:46:39.85#ibcon#[25=USB\r\n] 2006.173.01:46:39.85#ibcon#*before write, iclass 36, count 0 2006.173.01:46:39.85#ibcon#enter sib2, iclass 36, count 0 2006.173.01:46:39.85#ibcon#flushed, iclass 36, count 0 2006.173.01:46:39.85#ibcon#about to write, iclass 36, count 0 2006.173.01:46:39.85#ibcon#wrote, iclass 36, count 0 2006.173.01:46:39.85#ibcon#about to read 3, iclass 36, count 0 2006.173.01:46:39.88#ibcon#read 3, iclass 36, count 0 2006.173.01:46:39.88#ibcon#about to read 4, iclass 36, count 0 2006.173.01:46:39.88#ibcon#read 4, iclass 36, count 0 2006.173.01:46:39.88#ibcon#about to read 5, iclass 36, count 0 2006.173.01:46:39.88#ibcon#read 5, iclass 36, count 0 2006.173.01:46:39.88#ibcon#about to read 6, iclass 36, count 0 2006.173.01:46:39.88#ibcon#read 6, iclass 36, count 0 2006.173.01:46:39.88#ibcon#end of sib2, iclass 36, count 0 2006.173.01:46:39.88#ibcon#*after write, iclass 36, count 0 2006.173.01:46:39.88#ibcon#*before return 0, iclass 36, count 0 2006.173.01:46:39.88#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.01:46:39.88#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.01:46:39.88#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.01:46:39.88#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.01:46:39.88$vck44/valo=4,624.99 2006.173.01:46:39.88#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.01:46:39.88#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.01:46:39.88#ibcon#ireg 17 cls_cnt 0 2006.173.01:46:39.88#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.01:46:39.88#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.01:46:39.88#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.01:46:39.88#ibcon#enter wrdev, iclass 38, count 0 2006.173.01:46:39.88#ibcon#first serial, iclass 38, count 0 2006.173.01:46:39.88#ibcon#enter sib2, iclass 38, count 0 2006.173.01:46:39.88#ibcon#flushed, iclass 38, count 0 2006.173.01:46:39.88#ibcon#about to write, iclass 38, count 0 2006.173.01:46:39.88#ibcon#wrote, iclass 38, count 0 2006.173.01:46:39.88#ibcon#about to read 3, iclass 38, count 0 2006.173.01:46:39.90#ibcon#read 3, iclass 38, count 0 2006.173.01:46:39.90#ibcon#about to read 4, iclass 38, count 0 2006.173.01:46:39.90#ibcon#read 4, iclass 38, count 0 2006.173.01:46:39.90#ibcon#about to read 5, iclass 38, count 0 2006.173.01:46:39.90#ibcon#read 5, iclass 38, count 0 2006.173.01:46:39.90#ibcon#about to read 6, iclass 38, count 0 2006.173.01:46:39.90#ibcon#read 6, iclass 38, count 0 2006.173.01:46:39.90#ibcon#end of sib2, iclass 38, count 0 2006.173.01:46:39.90#ibcon#*mode == 0, iclass 38, count 0 2006.173.01:46:39.90#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.01:46:39.90#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.01:46:39.90#ibcon#*before write, iclass 38, count 0 2006.173.01:46:39.90#ibcon#enter sib2, iclass 38, count 0 2006.173.01:46:39.90#ibcon#flushed, iclass 38, count 0 2006.173.01:46:39.90#ibcon#about to write, iclass 38, count 0 2006.173.01:46:39.90#ibcon#wrote, iclass 38, count 0 2006.173.01:46:39.90#ibcon#about to read 3, iclass 38, count 0 2006.173.01:46:39.94#ibcon#read 3, iclass 38, count 0 2006.173.01:46:39.94#ibcon#about to read 4, iclass 38, count 0 2006.173.01:46:39.94#ibcon#read 4, iclass 38, count 0 2006.173.01:46:39.94#ibcon#about to read 5, iclass 38, count 0 2006.173.01:46:39.94#ibcon#read 5, iclass 38, count 0 2006.173.01:46:39.94#ibcon#about to read 6, iclass 38, count 0 2006.173.01:46:39.94#ibcon#read 6, iclass 38, count 0 2006.173.01:46:39.94#ibcon#end of sib2, iclass 38, count 0 2006.173.01:46:39.94#ibcon#*after write, iclass 38, count 0 2006.173.01:46:39.94#ibcon#*before return 0, iclass 38, count 0 2006.173.01:46:39.94#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.01:46:39.94#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.01:46:39.94#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.01:46:39.94#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.01:46:39.94$vck44/va=4,6 2006.173.01:46:39.94#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.01:46:39.94#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.01:46:39.94#ibcon#ireg 11 cls_cnt 2 2006.173.01:46:39.94#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.01:46:40.00#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.01:46:40.00#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.01:46:40.00#ibcon#enter wrdev, iclass 40, count 2 2006.173.01:46:40.00#ibcon#first serial, iclass 40, count 2 2006.173.01:46:40.00#ibcon#enter sib2, iclass 40, count 2 2006.173.01:46:40.00#ibcon#flushed, iclass 40, count 2 2006.173.01:46:40.00#ibcon#about to write, iclass 40, count 2 2006.173.01:46:40.00#ibcon#wrote, iclass 40, count 2 2006.173.01:46:40.00#ibcon#about to read 3, iclass 40, count 2 2006.173.01:46:40.02#ibcon#read 3, iclass 40, count 2 2006.173.01:46:40.02#ibcon#about to read 4, iclass 40, count 2 2006.173.01:46:40.02#ibcon#read 4, iclass 40, count 2 2006.173.01:46:40.02#ibcon#about to read 5, iclass 40, count 2 2006.173.01:46:40.02#ibcon#read 5, iclass 40, count 2 2006.173.01:46:40.02#ibcon#about to read 6, iclass 40, count 2 2006.173.01:46:40.02#ibcon#read 6, iclass 40, count 2 2006.173.01:46:40.02#ibcon#end of sib2, iclass 40, count 2 2006.173.01:46:40.02#ibcon#*mode == 0, iclass 40, count 2 2006.173.01:46:40.02#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.01:46:40.02#ibcon#[25=AT04-06\r\n] 2006.173.01:46:40.02#ibcon#*before write, iclass 40, count 2 2006.173.01:46:40.02#ibcon#enter sib2, iclass 40, count 2 2006.173.01:46:40.02#ibcon#flushed, iclass 40, count 2 2006.173.01:46:40.02#ibcon#about to write, iclass 40, count 2 2006.173.01:46:40.02#ibcon#wrote, iclass 40, count 2 2006.173.01:46:40.02#ibcon#about to read 3, iclass 40, count 2 2006.173.01:46:40.05#ibcon#read 3, iclass 40, count 2 2006.173.01:46:40.05#ibcon#about to read 4, iclass 40, count 2 2006.173.01:46:40.05#ibcon#read 4, iclass 40, count 2 2006.173.01:46:40.05#ibcon#about to read 5, iclass 40, count 2 2006.173.01:46:40.05#ibcon#read 5, iclass 40, count 2 2006.173.01:46:40.05#ibcon#about to read 6, iclass 40, count 2 2006.173.01:46:40.05#ibcon#read 6, iclass 40, count 2 2006.173.01:46:40.05#ibcon#end of sib2, iclass 40, count 2 2006.173.01:46:40.05#ibcon#*after write, iclass 40, count 2 2006.173.01:46:40.05#ibcon#*before return 0, iclass 40, count 2 2006.173.01:46:40.05#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.01:46:40.05#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.01:46:40.05#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.01:46:40.05#ibcon#ireg 7 cls_cnt 0 2006.173.01:46:40.05#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.01:46:40.17#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.01:46:40.17#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.01:46:40.17#ibcon#enter wrdev, iclass 40, count 0 2006.173.01:46:40.17#ibcon#first serial, iclass 40, count 0 2006.173.01:46:40.17#ibcon#enter sib2, iclass 40, count 0 2006.173.01:46:40.17#ibcon#flushed, iclass 40, count 0 2006.173.01:46:40.17#ibcon#about to write, iclass 40, count 0 2006.173.01:46:40.17#ibcon#wrote, iclass 40, count 0 2006.173.01:46:40.17#ibcon#about to read 3, iclass 40, count 0 2006.173.01:46:40.19#ibcon#read 3, iclass 40, count 0 2006.173.01:46:40.19#ibcon#about to read 4, iclass 40, count 0 2006.173.01:46:40.19#ibcon#read 4, iclass 40, count 0 2006.173.01:46:40.19#ibcon#about to read 5, iclass 40, count 0 2006.173.01:46:40.19#ibcon#read 5, iclass 40, count 0 2006.173.01:46:40.19#ibcon#about to read 6, iclass 40, count 0 2006.173.01:46:40.19#ibcon#read 6, iclass 40, count 0 2006.173.01:46:40.19#ibcon#end of sib2, iclass 40, count 0 2006.173.01:46:40.19#ibcon#*mode == 0, iclass 40, count 0 2006.173.01:46:40.19#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.01:46:40.19#ibcon#[25=USB\r\n] 2006.173.01:46:40.19#ibcon#*before write, iclass 40, count 0 2006.173.01:46:40.19#ibcon#enter sib2, iclass 40, count 0 2006.173.01:46:40.19#ibcon#flushed, iclass 40, count 0 2006.173.01:46:40.19#ibcon#about to write, iclass 40, count 0 2006.173.01:46:40.19#ibcon#wrote, iclass 40, count 0 2006.173.01:46:40.19#ibcon#about to read 3, iclass 40, count 0 2006.173.01:46:40.22#ibcon#read 3, iclass 40, count 0 2006.173.01:46:40.22#ibcon#about to read 4, iclass 40, count 0 2006.173.01:46:40.22#ibcon#read 4, iclass 40, count 0 2006.173.01:46:40.22#ibcon#about to read 5, iclass 40, count 0 2006.173.01:46:40.22#ibcon#read 5, iclass 40, count 0 2006.173.01:46:40.22#ibcon#about to read 6, iclass 40, count 0 2006.173.01:46:40.22#ibcon#read 6, iclass 40, count 0 2006.173.01:46:40.22#ibcon#end of sib2, iclass 40, count 0 2006.173.01:46:40.22#ibcon#*after write, iclass 40, count 0 2006.173.01:46:40.22#ibcon#*before return 0, iclass 40, count 0 2006.173.01:46:40.22#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.01:46:40.22#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.01:46:40.22#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.01:46:40.22#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.01:46:40.22$vck44/valo=5,734.99 2006.173.01:46:40.22#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.01:46:40.22#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.01:46:40.22#ibcon#ireg 17 cls_cnt 0 2006.173.01:46:40.22#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.01:46:40.22#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.01:46:40.22#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.01:46:40.22#ibcon#enter wrdev, iclass 4, count 0 2006.173.01:46:40.22#ibcon#first serial, iclass 4, count 0 2006.173.01:46:40.22#ibcon#enter sib2, iclass 4, count 0 2006.173.01:46:40.22#ibcon#flushed, iclass 4, count 0 2006.173.01:46:40.22#ibcon#about to write, iclass 4, count 0 2006.173.01:46:40.22#ibcon#wrote, iclass 4, count 0 2006.173.01:46:40.22#ibcon#about to read 3, iclass 4, count 0 2006.173.01:46:40.24#ibcon#read 3, iclass 4, count 0 2006.173.01:46:40.24#ibcon#about to read 4, iclass 4, count 0 2006.173.01:46:40.24#ibcon#read 4, iclass 4, count 0 2006.173.01:46:40.24#ibcon#about to read 5, iclass 4, count 0 2006.173.01:46:40.24#ibcon#read 5, iclass 4, count 0 2006.173.01:46:40.24#ibcon#about to read 6, iclass 4, count 0 2006.173.01:46:40.24#ibcon#read 6, iclass 4, count 0 2006.173.01:46:40.24#ibcon#end of sib2, iclass 4, count 0 2006.173.01:46:40.24#ibcon#*mode == 0, iclass 4, count 0 2006.173.01:46:40.24#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.01:46:40.24#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.01:46:40.24#ibcon#*before write, iclass 4, count 0 2006.173.01:46:40.24#ibcon#enter sib2, iclass 4, count 0 2006.173.01:46:40.24#ibcon#flushed, iclass 4, count 0 2006.173.01:46:40.24#ibcon#about to write, iclass 4, count 0 2006.173.01:46:40.24#ibcon#wrote, iclass 4, count 0 2006.173.01:46:40.24#ibcon#about to read 3, iclass 4, count 0 2006.173.01:46:40.28#ibcon#read 3, iclass 4, count 0 2006.173.01:46:40.28#ibcon#about to read 4, iclass 4, count 0 2006.173.01:46:40.28#ibcon#read 4, iclass 4, count 0 2006.173.01:46:40.28#ibcon#about to read 5, iclass 4, count 0 2006.173.01:46:40.28#ibcon#read 5, iclass 4, count 0 2006.173.01:46:40.28#ibcon#about to read 6, iclass 4, count 0 2006.173.01:46:40.28#ibcon#read 6, iclass 4, count 0 2006.173.01:46:40.28#ibcon#end of sib2, iclass 4, count 0 2006.173.01:46:40.28#ibcon#*after write, iclass 4, count 0 2006.173.01:46:40.28#ibcon#*before return 0, iclass 4, count 0 2006.173.01:46:40.28#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.01:46:40.28#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.01:46:40.28#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.01:46:40.28#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.01:46:40.28$vck44/va=5,4 2006.173.01:46:40.28#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.01:46:40.28#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.01:46:40.28#ibcon#ireg 11 cls_cnt 2 2006.173.01:46:40.28#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.01:46:40.34#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.01:46:40.34#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.01:46:40.34#ibcon#enter wrdev, iclass 6, count 2 2006.173.01:46:40.34#ibcon#first serial, iclass 6, count 2 2006.173.01:46:40.34#ibcon#enter sib2, iclass 6, count 2 2006.173.01:46:40.34#ibcon#flushed, iclass 6, count 2 2006.173.01:46:40.34#ibcon#about to write, iclass 6, count 2 2006.173.01:46:40.34#ibcon#wrote, iclass 6, count 2 2006.173.01:46:40.34#ibcon#about to read 3, iclass 6, count 2 2006.173.01:46:40.36#ibcon#read 3, iclass 6, count 2 2006.173.01:46:40.36#ibcon#about to read 4, iclass 6, count 2 2006.173.01:46:40.36#ibcon#read 4, iclass 6, count 2 2006.173.01:46:40.36#ibcon#about to read 5, iclass 6, count 2 2006.173.01:46:40.36#ibcon#read 5, iclass 6, count 2 2006.173.01:46:40.36#ibcon#about to read 6, iclass 6, count 2 2006.173.01:46:40.36#ibcon#read 6, iclass 6, count 2 2006.173.01:46:40.36#ibcon#end of sib2, iclass 6, count 2 2006.173.01:46:40.36#ibcon#*mode == 0, iclass 6, count 2 2006.173.01:46:40.36#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.01:46:40.36#ibcon#[25=AT05-04\r\n] 2006.173.01:46:40.36#ibcon#*before write, iclass 6, count 2 2006.173.01:46:40.36#ibcon#enter sib2, iclass 6, count 2 2006.173.01:46:40.36#ibcon#flushed, iclass 6, count 2 2006.173.01:46:40.36#ibcon#about to write, iclass 6, count 2 2006.173.01:46:40.36#ibcon#wrote, iclass 6, count 2 2006.173.01:46:40.36#ibcon#about to read 3, iclass 6, count 2 2006.173.01:46:40.39#ibcon#read 3, iclass 6, count 2 2006.173.01:46:40.39#ibcon#about to read 4, iclass 6, count 2 2006.173.01:46:40.39#ibcon#read 4, iclass 6, count 2 2006.173.01:46:40.39#ibcon#about to read 5, iclass 6, count 2 2006.173.01:46:40.39#ibcon#read 5, iclass 6, count 2 2006.173.01:46:40.39#ibcon#about to read 6, iclass 6, count 2 2006.173.01:46:40.39#ibcon#read 6, iclass 6, count 2 2006.173.01:46:40.39#ibcon#end of sib2, iclass 6, count 2 2006.173.01:46:40.39#ibcon#*after write, iclass 6, count 2 2006.173.01:46:40.39#ibcon#*before return 0, iclass 6, count 2 2006.173.01:46:40.39#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.01:46:40.39#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.01:46:40.39#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.01:46:40.39#ibcon#ireg 7 cls_cnt 0 2006.173.01:46:40.39#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.01:46:40.51#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.01:46:40.51#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.01:46:40.51#ibcon#enter wrdev, iclass 6, count 0 2006.173.01:46:40.51#ibcon#first serial, iclass 6, count 0 2006.173.01:46:40.51#ibcon#enter sib2, iclass 6, count 0 2006.173.01:46:40.51#ibcon#flushed, iclass 6, count 0 2006.173.01:46:40.51#ibcon#about to write, iclass 6, count 0 2006.173.01:46:40.51#ibcon#wrote, iclass 6, count 0 2006.173.01:46:40.51#ibcon#about to read 3, iclass 6, count 0 2006.173.01:46:40.53#ibcon#read 3, iclass 6, count 0 2006.173.01:46:40.53#ibcon#about to read 4, iclass 6, count 0 2006.173.01:46:40.53#ibcon#read 4, iclass 6, count 0 2006.173.01:46:40.53#ibcon#about to read 5, iclass 6, count 0 2006.173.01:46:40.53#ibcon#read 5, iclass 6, count 0 2006.173.01:46:40.53#ibcon#about to read 6, iclass 6, count 0 2006.173.01:46:40.53#ibcon#read 6, iclass 6, count 0 2006.173.01:46:40.53#ibcon#end of sib2, iclass 6, count 0 2006.173.01:46:40.53#ibcon#*mode == 0, iclass 6, count 0 2006.173.01:46:40.53#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.01:46:40.53#ibcon#[25=USB\r\n] 2006.173.01:46:40.53#ibcon#*before write, iclass 6, count 0 2006.173.01:46:40.53#ibcon#enter sib2, iclass 6, count 0 2006.173.01:46:40.53#ibcon#flushed, iclass 6, count 0 2006.173.01:46:40.53#ibcon#about to write, iclass 6, count 0 2006.173.01:46:40.53#ibcon#wrote, iclass 6, count 0 2006.173.01:46:40.53#ibcon#about to read 3, iclass 6, count 0 2006.173.01:46:40.56#ibcon#read 3, iclass 6, count 0 2006.173.01:46:40.56#ibcon#about to read 4, iclass 6, count 0 2006.173.01:46:40.56#ibcon#read 4, iclass 6, count 0 2006.173.01:46:40.56#ibcon#about to read 5, iclass 6, count 0 2006.173.01:46:40.56#ibcon#read 5, iclass 6, count 0 2006.173.01:46:40.56#ibcon#about to read 6, iclass 6, count 0 2006.173.01:46:40.56#ibcon#read 6, iclass 6, count 0 2006.173.01:46:40.56#ibcon#end of sib2, iclass 6, count 0 2006.173.01:46:40.56#ibcon#*after write, iclass 6, count 0 2006.173.01:46:40.56#ibcon#*before return 0, iclass 6, count 0 2006.173.01:46:40.56#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.01:46:40.56#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.01:46:40.56#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.01:46:40.56#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.01:46:40.56$vck44/valo=6,814.99 2006.173.01:46:40.56#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.01:46:40.56#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.01:46:40.56#ibcon#ireg 17 cls_cnt 0 2006.173.01:46:40.56#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.01:46:40.56#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.01:46:40.56#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.01:46:40.56#ibcon#enter wrdev, iclass 10, count 0 2006.173.01:46:40.56#ibcon#first serial, iclass 10, count 0 2006.173.01:46:40.56#ibcon#enter sib2, iclass 10, count 0 2006.173.01:46:40.56#ibcon#flushed, iclass 10, count 0 2006.173.01:46:40.56#ibcon#about to write, iclass 10, count 0 2006.173.01:46:40.56#ibcon#wrote, iclass 10, count 0 2006.173.01:46:40.56#ibcon#about to read 3, iclass 10, count 0 2006.173.01:46:40.58#ibcon#read 3, iclass 10, count 0 2006.173.01:46:40.58#ibcon#about to read 4, iclass 10, count 0 2006.173.01:46:40.58#ibcon#read 4, iclass 10, count 0 2006.173.01:46:40.58#ibcon#about to read 5, iclass 10, count 0 2006.173.01:46:40.58#ibcon#read 5, iclass 10, count 0 2006.173.01:46:40.58#ibcon#about to read 6, iclass 10, count 0 2006.173.01:46:40.58#ibcon#read 6, iclass 10, count 0 2006.173.01:46:40.58#ibcon#end of sib2, iclass 10, count 0 2006.173.01:46:40.58#ibcon#*mode == 0, iclass 10, count 0 2006.173.01:46:40.58#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.01:46:40.58#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.01:46:40.58#ibcon#*before write, iclass 10, count 0 2006.173.01:46:40.58#ibcon#enter sib2, iclass 10, count 0 2006.173.01:46:40.58#ibcon#flushed, iclass 10, count 0 2006.173.01:46:40.58#ibcon#about to write, iclass 10, count 0 2006.173.01:46:40.58#ibcon#wrote, iclass 10, count 0 2006.173.01:46:40.58#ibcon#about to read 3, iclass 10, count 0 2006.173.01:46:40.62#ibcon#read 3, iclass 10, count 0 2006.173.01:46:40.62#ibcon#about to read 4, iclass 10, count 0 2006.173.01:46:40.62#ibcon#read 4, iclass 10, count 0 2006.173.01:46:40.62#ibcon#about to read 5, iclass 10, count 0 2006.173.01:46:40.62#ibcon#read 5, iclass 10, count 0 2006.173.01:46:40.62#ibcon#about to read 6, iclass 10, count 0 2006.173.01:46:40.62#ibcon#read 6, iclass 10, count 0 2006.173.01:46:40.62#ibcon#end of sib2, iclass 10, count 0 2006.173.01:46:40.62#ibcon#*after write, iclass 10, count 0 2006.173.01:46:40.62#ibcon#*before return 0, iclass 10, count 0 2006.173.01:46:40.62#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.01:46:40.62#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.01:46:40.62#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.01:46:40.62#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.01:46:40.62$vck44/va=6,3 2006.173.01:46:40.62#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.01:46:40.62#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.01:46:40.62#ibcon#ireg 11 cls_cnt 2 2006.173.01:46:40.62#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.01:46:40.68#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.01:46:40.68#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.01:46:40.68#ibcon#enter wrdev, iclass 12, count 2 2006.173.01:46:40.68#ibcon#first serial, iclass 12, count 2 2006.173.01:46:40.68#ibcon#enter sib2, iclass 12, count 2 2006.173.01:46:40.68#ibcon#flushed, iclass 12, count 2 2006.173.01:46:40.68#ibcon#about to write, iclass 12, count 2 2006.173.01:46:40.68#ibcon#wrote, iclass 12, count 2 2006.173.01:46:40.68#ibcon#about to read 3, iclass 12, count 2 2006.173.01:46:40.70#ibcon#read 3, iclass 12, count 2 2006.173.01:46:40.70#ibcon#about to read 4, iclass 12, count 2 2006.173.01:46:40.70#ibcon#read 4, iclass 12, count 2 2006.173.01:46:40.70#ibcon#about to read 5, iclass 12, count 2 2006.173.01:46:40.70#ibcon#read 5, iclass 12, count 2 2006.173.01:46:40.70#ibcon#about to read 6, iclass 12, count 2 2006.173.01:46:40.70#ibcon#read 6, iclass 12, count 2 2006.173.01:46:40.70#ibcon#end of sib2, iclass 12, count 2 2006.173.01:46:40.70#ibcon#*mode == 0, iclass 12, count 2 2006.173.01:46:40.70#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.01:46:40.70#ibcon#[25=AT06-03\r\n] 2006.173.01:46:40.70#ibcon#*before write, iclass 12, count 2 2006.173.01:46:40.70#ibcon#enter sib2, iclass 12, count 2 2006.173.01:46:40.70#ibcon#flushed, iclass 12, count 2 2006.173.01:46:40.70#ibcon#about to write, iclass 12, count 2 2006.173.01:46:40.70#ibcon#wrote, iclass 12, count 2 2006.173.01:46:40.70#ibcon#about to read 3, iclass 12, count 2 2006.173.01:46:40.73#ibcon#read 3, iclass 12, count 2 2006.173.01:46:40.73#ibcon#about to read 4, iclass 12, count 2 2006.173.01:46:40.73#ibcon#read 4, iclass 12, count 2 2006.173.01:46:40.73#ibcon#about to read 5, iclass 12, count 2 2006.173.01:46:40.73#ibcon#read 5, iclass 12, count 2 2006.173.01:46:40.73#ibcon#about to read 6, iclass 12, count 2 2006.173.01:46:40.73#ibcon#read 6, iclass 12, count 2 2006.173.01:46:40.73#ibcon#end of sib2, iclass 12, count 2 2006.173.01:46:40.73#ibcon#*after write, iclass 12, count 2 2006.173.01:46:40.73#ibcon#*before return 0, iclass 12, count 2 2006.173.01:46:40.73#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.01:46:40.73#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.01:46:40.73#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.01:46:40.73#ibcon#ireg 7 cls_cnt 0 2006.173.01:46:40.73#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.01:46:40.85#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.01:46:40.85#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.01:46:40.85#ibcon#enter wrdev, iclass 12, count 0 2006.173.01:46:40.85#ibcon#first serial, iclass 12, count 0 2006.173.01:46:40.85#ibcon#enter sib2, iclass 12, count 0 2006.173.01:46:40.85#ibcon#flushed, iclass 12, count 0 2006.173.01:46:40.85#ibcon#about to write, iclass 12, count 0 2006.173.01:46:40.85#ibcon#wrote, iclass 12, count 0 2006.173.01:46:40.85#ibcon#about to read 3, iclass 12, count 0 2006.173.01:46:40.87#ibcon#read 3, iclass 12, count 0 2006.173.01:46:40.87#ibcon#about to read 4, iclass 12, count 0 2006.173.01:46:40.87#ibcon#read 4, iclass 12, count 0 2006.173.01:46:40.87#ibcon#about to read 5, iclass 12, count 0 2006.173.01:46:40.87#ibcon#read 5, iclass 12, count 0 2006.173.01:46:40.87#ibcon#about to read 6, iclass 12, count 0 2006.173.01:46:40.87#ibcon#read 6, iclass 12, count 0 2006.173.01:46:40.87#ibcon#end of sib2, iclass 12, count 0 2006.173.01:46:40.87#ibcon#*mode == 0, iclass 12, count 0 2006.173.01:46:40.87#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.01:46:40.87#ibcon#[25=USB\r\n] 2006.173.01:46:40.87#ibcon#*before write, iclass 12, count 0 2006.173.01:46:40.87#ibcon#enter sib2, iclass 12, count 0 2006.173.01:46:40.87#ibcon#flushed, iclass 12, count 0 2006.173.01:46:40.87#ibcon#about to write, iclass 12, count 0 2006.173.01:46:40.87#ibcon#wrote, iclass 12, count 0 2006.173.01:46:40.87#ibcon#about to read 3, iclass 12, count 0 2006.173.01:46:40.90#ibcon#read 3, iclass 12, count 0 2006.173.01:46:40.90#ibcon#about to read 4, iclass 12, count 0 2006.173.01:46:40.90#ibcon#read 4, iclass 12, count 0 2006.173.01:46:40.90#ibcon#about to read 5, iclass 12, count 0 2006.173.01:46:40.90#ibcon#read 5, iclass 12, count 0 2006.173.01:46:40.90#ibcon#about to read 6, iclass 12, count 0 2006.173.01:46:40.90#ibcon#read 6, iclass 12, count 0 2006.173.01:46:40.90#ibcon#end of sib2, iclass 12, count 0 2006.173.01:46:40.90#ibcon#*after write, iclass 12, count 0 2006.173.01:46:40.90#ibcon#*before return 0, iclass 12, count 0 2006.173.01:46:40.90#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.01:46:40.90#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.01:46:40.90#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.01:46:40.90#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.01:46:40.90$vck44/valo=7,864.99 2006.173.01:46:40.90#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.01:46:40.90#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.01:46:40.90#ibcon#ireg 17 cls_cnt 0 2006.173.01:46:40.90#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.01:46:40.90#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.01:46:40.90#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.01:46:40.90#ibcon#enter wrdev, iclass 14, count 0 2006.173.01:46:40.90#ibcon#first serial, iclass 14, count 0 2006.173.01:46:40.90#ibcon#enter sib2, iclass 14, count 0 2006.173.01:46:40.90#ibcon#flushed, iclass 14, count 0 2006.173.01:46:40.90#ibcon#about to write, iclass 14, count 0 2006.173.01:46:40.90#ibcon#wrote, iclass 14, count 0 2006.173.01:46:40.90#ibcon#about to read 3, iclass 14, count 0 2006.173.01:46:40.92#ibcon#read 3, iclass 14, count 0 2006.173.01:46:40.92#ibcon#about to read 4, iclass 14, count 0 2006.173.01:46:40.92#ibcon#read 4, iclass 14, count 0 2006.173.01:46:40.92#ibcon#about to read 5, iclass 14, count 0 2006.173.01:46:40.92#ibcon#read 5, iclass 14, count 0 2006.173.01:46:40.92#ibcon#about to read 6, iclass 14, count 0 2006.173.01:46:40.92#ibcon#read 6, iclass 14, count 0 2006.173.01:46:40.92#ibcon#end of sib2, iclass 14, count 0 2006.173.01:46:40.92#ibcon#*mode == 0, iclass 14, count 0 2006.173.01:46:40.92#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.01:46:40.92#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.01:46:40.92#ibcon#*before write, iclass 14, count 0 2006.173.01:46:40.92#ibcon#enter sib2, iclass 14, count 0 2006.173.01:46:40.92#ibcon#flushed, iclass 14, count 0 2006.173.01:46:40.92#ibcon#about to write, iclass 14, count 0 2006.173.01:46:40.92#ibcon#wrote, iclass 14, count 0 2006.173.01:46:40.92#ibcon#about to read 3, iclass 14, count 0 2006.173.01:46:40.96#ibcon#read 3, iclass 14, count 0 2006.173.01:46:40.96#ibcon#about to read 4, iclass 14, count 0 2006.173.01:46:40.96#ibcon#read 4, iclass 14, count 0 2006.173.01:46:40.96#ibcon#about to read 5, iclass 14, count 0 2006.173.01:46:40.96#ibcon#read 5, iclass 14, count 0 2006.173.01:46:40.96#ibcon#about to read 6, iclass 14, count 0 2006.173.01:46:40.96#ibcon#read 6, iclass 14, count 0 2006.173.01:46:40.96#ibcon#end of sib2, iclass 14, count 0 2006.173.01:46:40.96#ibcon#*after write, iclass 14, count 0 2006.173.01:46:40.96#ibcon#*before return 0, iclass 14, count 0 2006.173.01:46:40.96#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.01:46:40.96#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.01:46:40.96#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.01:46:40.96#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.01:46:40.96$vck44/va=7,4 2006.173.01:46:40.96#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.01:46:40.96#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.01:46:40.96#ibcon#ireg 11 cls_cnt 2 2006.173.01:46:40.96#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.01:46:41.02#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.01:46:41.02#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.01:46:41.02#ibcon#enter wrdev, iclass 16, count 2 2006.173.01:46:41.02#ibcon#first serial, iclass 16, count 2 2006.173.01:46:41.02#ibcon#enter sib2, iclass 16, count 2 2006.173.01:46:41.02#ibcon#flushed, iclass 16, count 2 2006.173.01:46:41.02#ibcon#about to write, iclass 16, count 2 2006.173.01:46:41.02#ibcon#wrote, iclass 16, count 2 2006.173.01:46:41.02#ibcon#about to read 3, iclass 16, count 2 2006.173.01:46:41.04#ibcon#read 3, iclass 16, count 2 2006.173.01:46:41.04#ibcon#about to read 4, iclass 16, count 2 2006.173.01:46:41.04#ibcon#read 4, iclass 16, count 2 2006.173.01:46:41.04#ibcon#about to read 5, iclass 16, count 2 2006.173.01:46:41.04#ibcon#read 5, iclass 16, count 2 2006.173.01:46:41.04#ibcon#about to read 6, iclass 16, count 2 2006.173.01:46:41.04#ibcon#read 6, iclass 16, count 2 2006.173.01:46:41.04#ibcon#end of sib2, iclass 16, count 2 2006.173.01:46:41.04#ibcon#*mode == 0, iclass 16, count 2 2006.173.01:46:41.04#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.01:46:41.04#ibcon#[25=AT07-04\r\n] 2006.173.01:46:41.04#ibcon#*before write, iclass 16, count 2 2006.173.01:46:41.04#ibcon#enter sib2, iclass 16, count 2 2006.173.01:46:41.04#ibcon#flushed, iclass 16, count 2 2006.173.01:46:41.04#ibcon#about to write, iclass 16, count 2 2006.173.01:46:41.04#ibcon#wrote, iclass 16, count 2 2006.173.01:46:41.04#ibcon#about to read 3, iclass 16, count 2 2006.173.01:46:41.07#ibcon#read 3, iclass 16, count 2 2006.173.01:46:41.07#ibcon#about to read 4, iclass 16, count 2 2006.173.01:46:41.07#ibcon#read 4, iclass 16, count 2 2006.173.01:46:41.07#ibcon#about to read 5, iclass 16, count 2 2006.173.01:46:41.07#ibcon#read 5, iclass 16, count 2 2006.173.01:46:41.07#ibcon#about to read 6, iclass 16, count 2 2006.173.01:46:41.07#ibcon#read 6, iclass 16, count 2 2006.173.01:46:41.07#ibcon#end of sib2, iclass 16, count 2 2006.173.01:46:41.07#ibcon#*after write, iclass 16, count 2 2006.173.01:46:41.07#ibcon#*before return 0, iclass 16, count 2 2006.173.01:46:41.07#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.01:46:41.07#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.01:46:41.07#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.01:46:41.07#ibcon#ireg 7 cls_cnt 0 2006.173.01:46:41.07#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.01:46:41.19#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.01:46:41.19#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.01:46:41.19#ibcon#enter wrdev, iclass 16, count 0 2006.173.01:46:41.19#ibcon#first serial, iclass 16, count 0 2006.173.01:46:41.19#ibcon#enter sib2, iclass 16, count 0 2006.173.01:46:41.19#ibcon#flushed, iclass 16, count 0 2006.173.01:46:41.19#ibcon#about to write, iclass 16, count 0 2006.173.01:46:41.19#ibcon#wrote, iclass 16, count 0 2006.173.01:46:41.19#ibcon#about to read 3, iclass 16, count 0 2006.173.01:46:41.21#ibcon#read 3, iclass 16, count 0 2006.173.01:46:41.21#ibcon#about to read 4, iclass 16, count 0 2006.173.01:46:41.21#ibcon#read 4, iclass 16, count 0 2006.173.01:46:41.21#ibcon#about to read 5, iclass 16, count 0 2006.173.01:46:41.21#ibcon#read 5, iclass 16, count 0 2006.173.01:46:41.21#ibcon#about to read 6, iclass 16, count 0 2006.173.01:46:41.21#ibcon#read 6, iclass 16, count 0 2006.173.01:46:41.21#ibcon#end of sib2, iclass 16, count 0 2006.173.01:46:41.21#ibcon#*mode == 0, iclass 16, count 0 2006.173.01:46:41.21#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.01:46:41.21#ibcon#[25=USB\r\n] 2006.173.01:46:41.21#ibcon#*before write, iclass 16, count 0 2006.173.01:46:41.21#ibcon#enter sib2, iclass 16, count 0 2006.173.01:46:41.21#ibcon#flushed, iclass 16, count 0 2006.173.01:46:41.21#ibcon#about to write, iclass 16, count 0 2006.173.01:46:41.21#ibcon#wrote, iclass 16, count 0 2006.173.01:46:41.21#ibcon#about to read 3, iclass 16, count 0 2006.173.01:46:41.24#ibcon#read 3, iclass 16, count 0 2006.173.01:46:41.24#ibcon#about to read 4, iclass 16, count 0 2006.173.01:46:41.24#ibcon#read 4, iclass 16, count 0 2006.173.01:46:41.24#ibcon#about to read 5, iclass 16, count 0 2006.173.01:46:41.24#ibcon#read 5, iclass 16, count 0 2006.173.01:46:41.24#ibcon#about to read 6, iclass 16, count 0 2006.173.01:46:41.24#ibcon#read 6, iclass 16, count 0 2006.173.01:46:41.24#ibcon#end of sib2, iclass 16, count 0 2006.173.01:46:41.24#ibcon#*after write, iclass 16, count 0 2006.173.01:46:41.24#ibcon#*before return 0, iclass 16, count 0 2006.173.01:46:41.24#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.01:46:41.24#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.01:46:41.24#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.01:46:41.24#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.01:46:41.24$vck44/valo=8,884.99 2006.173.01:46:41.24#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.01:46:41.24#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.01:46:41.24#ibcon#ireg 17 cls_cnt 0 2006.173.01:46:41.24#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.01:46:41.24#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.01:46:41.24#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.01:46:41.24#ibcon#enter wrdev, iclass 18, count 0 2006.173.01:46:41.24#ibcon#first serial, iclass 18, count 0 2006.173.01:46:41.24#ibcon#enter sib2, iclass 18, count 0 2006.173.01:46:41.24#ibcon#flushed, iclass 18, count 0 2006.173.01:46:41.24#ibcon#about to write, iclass 18, count 0 2006.173.01:46:41.24#ibcon#wrote, iclass 18, count 0 2006.173.01:46:41.24#ibcon#about to read 3, iclass 18, count 0 2006.173.01:46:41.26#ibcon#read 3, iclass 18, count 0 2006.173.01:46:41.26#ibcon#about to read 4, iclass 18, count 0 2006.173.01:46:41.26#ibcon#read 4, iclass 18, count 0 2006.173.01:46:41.26#ibcon#about to read 5, iclass 18, count 0 2006.173.01:46:41.26#ibcon#read 5, iclass 18, count 0 2006.173.01:46:41.26#ibcon#about to read 6, iclass 18, count 0 2006.173.01:46:41.26#ibcon#read 6, iclass 18, count 0 2006.173.01:46:41.26#ibcon#end of sib2, iclass 18, count 0 2006.173.01:46:41.26#ibcon#*mode == 0, iclass 18, count 0 2006.173.01:46:41.26#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.01:46:41.26#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.01:46:41.26#ibcon#*before write, iclass 18, count 0 2006.173.01:46:41.26#ibcon#enter sib2, iclass 18, count 0 2006.173.01:46:41.26#ibcon#flushed, iclass 18, count 0 2006.173.01:46:41.26#ibcon#about to write, iclass 18, count 0 2006.173.01:46:41.26#ibcon#wrote, iclass 18, count 0 2006.173.01:46:41.26#ibcon#about to read 3, iclass 18, count 0 2006.173.01:46:41.30#ibcon#read 3, iclass 18, count 0 2006.173.01:46:41.30#ibcon#about to read 4, iclass 18, count 0 2006.173.01:46:41.30#ibcon#read 4, iclass 18, count 0 2006.173.01:46:41.30#ibcon#about to read 5, iclass 18, count 0 2006.173.01:46:41.30#ibcon#read 5, iclass 18, count 0 2006.173.01:46:41.30#ibcon#about to read 6, iclass 18, count 0 2006.173.01:46:41.30#ibcon#read 6, iclass 18, count 0 2006.173.01:46:41.30#ibcon#end of sib2, iclass 18, count 0 2006.173.01:46:41.30#ibcon#*after write, iclass 18, count 0 2006.173.01:46:41.30#ibcon#*before return 0, iclass 18, count 0 2006.173.01:46:41.30#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.01:46:41.30#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.01:46:41.30#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.01:46:41.30#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.01:46:41.30$vck44/va=8,4 2006.173.01:46:41.30#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.01:46:41.30#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.01:46:41.30#ibcon#ireg 11 cls_cnt 2 2006.173.01:46:41.30#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.01:46:41.36#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.01:46:41.36#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.01:46:41.36#ibcon#enter wrdev, iclass 20, count 2 2006.173.01:46:41.36#ibcon#first serial, iclass 20, count 2 2006.173.01:46:41.36#ibcon#enter sib2, iclass 20, count 2 2006.173.01:46:41.36#ibcon#flushed, iclass 20, count 2 2006.173.01:46:41.36#ibcon#about to write, iclass 20, count 2 2006.173.01:46:41.36#ibcon#wrote, iclass 20, count 2 2006.173.01:46:41.36#ibcon#about to read 3, iclass 20, count 2 2006.173.01:46:41.38#ibcon#read 3, iclass 20, count 2 2006.173.01:46:41.38#ibcon#about to read 4, iclass 20, count 2 2006.173.01:46:41.38#ibcon#read 4, iclass 20, count 2 2006.173.01:46:41.38#ibcon#about to read 5, iclass 20, count 2 2006.173.01:46:41.38#ibcon#read 5, iclass 20, count 2 2006.173.01:46:41.38#ibcon#about to read 6, iclass 20, count 2 2006.173.01:46:41.38#ibcon#read 6, iclass 20, count 2 2006.173.01:46:41.38#ibcon#end of sib2, iclass 20, count 2 2006.173.01:46:41.38#ibcon#*mode == 0, iclass 20, count 2 2006.173.01:46:41.38#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.01:46:41.38#ibcon#[25=AT08-04\r\n] 2006.173.01:46:41.38#ibcon#*before write, iclass 20, count 2 2006.173.01:46:41.38#ibcon#enter sib2, iclass 20, count 2 2006.173.01:46:41.38#ibcon#flushed, iclass 20, count 2 2006.173.01:46:41.38#ibcon#about to write, iclass 20, count 2 2006.173.01:46:41.38#ibcon#wrote, iclass 20, count 2 2006.173.01:46:41.38#ibcon#about to read 3, iclass 20, count 2 2006.173.01:46:41.41#ibcon#read 3, iclass 20, count 2 2006.173.01:46:41.41#ibcon#about to read 4, iclass 20, count 2 2006.173.01:46:41.41#ibcon#read 4, iclass 20, count 2 2006.173.01:46:41.41#ibcon#about to read 5, iclass 20, count 2 2006.173.01:46:41.41#ibcon#read 5, iclass 20, count 2 2006.173.01:46:41.41#ibcon#about to read 6, iclass 20, count 2 2006.173.01:46:41.41#ibcon#read 6, iclass 20, count 2 2006.173.01:46:41.41#ibcon#end of sib2, iclass 20, count 2 2006.173.01:46:41.41#ibcon#*after write, iclass 20, count 2 2006.173.01:46:41.41#ibcon#*before return 0, iclass 20, count 2 2006.173.01:46:41.41#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.01:46:41.41#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.01:46:41.41#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.01:46:41.41#ibcon#ireg 7 cls_cnt 0 2006.173.01:46:41.41#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.01:46:41.53#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.01:46:41.53#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.01:46:41.53#ibcon#enter wrdev, iclass 20, count 0 2006.173.01:46:41.53#ibcon#first serial, iclass 20, count 0 2006.173.01:46:41.53#ibcon#enter sib2, iclass 20, count 0 2006.173.01:46:41.53#ibcon#flushed, iclass 20, count 0 2006.173.01:46:41.53#ibcon#about to write, iclass 20, count 0 2006.173.01:46:41.53#ibcon#wrote, iclass 20, count 0 2006.173.01:46:41.53#ibcon#about to read 3, iclass 20, count 0 2006.173.01:46:41.55#ibcon#read 3, iclass 20, count 0 2006.173.01:46:41.55#ibcon#about to read 4, iclass 20, count 0 2006.173.01:46:41.55#ibcon#read 4, iclass 20, count 0 2006.173.01:46:41.55#ibcon#about to read 5, iclass 20, count 0 2006.173.01:46:41.55#ibcon#read 5, iclass 20, count 0 2006.173.01:46:41.55#ibcon#about to read 6, iclass 20, count 0 2006.173.01:46:41.55#ibcon#read 6, iclass 20, count 0 2006.173.01:46:41.55#ibcon#end of sib2, iclass 20, count 0 2006.173.01:46:41.55#ibcon#*mode == 0, iclass 20, count 0 2006.173.01:46:41.55#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.01:46:41.55#ibcon#[25=USB\r\n] 2006.173.01:46:41.55#ibcon#*before write, iclass 20, count 0 2006.173.01:46:41.55#ibcon#enter sib2, iclass 20, count 0 2006.173.01:46:41.55#ibcon#flushed, iclass 20, count 0 2006.173.01:46:41.55#ibcon#about to write, iclass 20, count 0 2006.173.01:46:41.55#ibcon#wrote, iclass 20, count 0 2006.173.01:46:41.55#ibcon#about to read 3, iclass 20, count 0 2006.173.01:46:41.58#ibcon#read 3, iclass 20, count 0 2006.173.01:46:41.58#ibcon#about to read 4, iclass 20, count 0 2006.173.01:46:41.58#ibcon#read 4, iclass 20, count 0 2006.173.01:46:41.58#ibcon#about to read 5, iclass 20, count 0 2006.173.01:46:41.58#ibcon#read 5, iclass 20, count 0 2006.173.01:46:41.58#ibcon#about to read 6, iclass 20, count 0 2006.173.01:46:41.58#ibcon#read 6, iclass 20, count 0 2006.173.01:46:41.58#ibcon#end of sib2, iclass 20, count 0 2006.173.01:46:41.58#ibcon#*after write, iclass 20, count 0 2006.173.01:46:41.58#ibcon#*before return 0, iclass 20, count 0 2006.173.01:46:41.58#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.01:46:41.58#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.01:46:41.58#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.01:46:41.58#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.01:46:41.58$vck44/vblo=1,629.99 2006.173.01:46:41.58#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.01:46:41.58#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.01:46:41.58#ibcon#ireg 17 cls_cnt 0 2006.173.01:46:41.58#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.01:46:41.58#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.01:46:41.58#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.01:46:41.58#ibcon#enter wrdev, iclass 22, count 0 2006.173.01:46:41.58#ibcon#first serial, iclass 22, count 0 2006.173.01:46:41.58#ibcon#enter sib2, iclass 22, count 0 2006.173.01:46:41.58#ibcon#flushed, iclass 22, count 0 2006.173.01:46:41.58#ibcon#about to write, iclass 22, count 0 2006.173.01:46:41.58#ibcon#wrote, iclass 22, count 0 2006.173.01:46:41.58#ibcon#about to read 3, iclass 22, count 0 2006.173.01:46:41.60#ibcon#read 3, iclass 22, count 0 2006.173.01:46:41.60#ibcon#about to read 4, iclass 22, count 0 2006.173.01:46:41.60#ibcon#read 4, iclass 22, count 0 2006.173.01:46:41.60#ibcon#about to read 5, iclass 22, count 0 2006.173.01:46:41.60#ibcon#read 5, iclass 22, count 0 2006.173.01:46:41.60#ibcon#about to read 6, iclass 22, count 0 2006.173.01:46:41.60#ibcon#read 6, iclass 22, count 0 2006.173.01:46:41.60#ibcon#end of sib2, iclass 22, count 0 2006.173.01:46:41.60#ibcon#*mode == 0, iclass 22, count 0 2006.173.01:46:41.60#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.01:46:41.60#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.01:46:41.60#ibcon#*before write, iclass 22, count 0 2006.173.01:46:41.60#ibcon#enter sib2, iclass 22, count 0 2006.173.01:46:41.60#ibcon#flushed, iclass 22, count 0 2006.173.01:46:41.60#ibcon#about to write, iclass 22, count 0 2006.173.01:46:41.60#ibcon#wrote, iclass 22, count 0 2006.173.01:46:41.60#ibcon#about to read 3, iclass 22, count 0 2006.173.01:46:41.64#ibcon#read 3, iclass 22, count 0 2006.173.01:46:41.64#ibcon#about to read 4, iclass 22, count 0 2006.173.01:46:41.64#ibcon#read 4, iclass 22, count 0 2006.173.01:46:41.64#ibcon#about to read 5, iclass 22, count 0 2006.173.01:46:41.64#ibcon#read 5, iclass 22, count 0 2006.173.01:46:41.64#ibcon#about to read 6, iclass 22, count 0 2006.173.01:46:41.64#ibcon#read 6, iclass 22, count 0 2006.173.01:46:41.64#ibcon#end of sib2, iclass 22, count 0 2006.173.01:46:41.64#ibcon#*after write, iclass 22, count 0 2006.173.01:46:41.64#ibcon#*before return 0, iclass 22, count 0 2006.173.01:46:41.64#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.01:46:41.64#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.01:46:41.64#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.01:46:41.64#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.01:46:41.64$vck44/vb=1,4 2006.173.01:46:41.64#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.01:46:41.64#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.01:46:41.64#ibcon#ireg 11 cls_cnt 2 2006.173.01:46:41.64#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.01:46:41.64#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.01:46:41.64#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.01:46:41.64#ibcon#enter wrdev, iclass 24, count 2 2006.173.01:46:41.64#ibcon#first serial, iclass 24, count 2 2006.173.01:46:41.64#ibcon#enter sib2, iclass 24, count 2 2006.173.01:46:41.64#ibcon#flushed, iclass 24, count 2 2006.173.01:46:41.64#ibcon#about to write, iclass 24, count 2 2006.173.01:46:41.64#ibcon#wrote, iclass 24, count 2 2006.173.01:46:41.64#ibcon#about to read 3, iclass 24, count 2 2006.173.01:46:41.66#ibcon#read 3, iclass 24, count 2 2006.173.01:46:41.66#ibcon#about to read 4, iclass 24, count 2 2006.173.01:46:41.66#ibcon#read 4, iclass 24, count 2 2006.173.01:46:41.66#ibcon#about to read 5, iclass 24, count 2 2006.173.01:46:41.66#ibcon#read 5, iclass 24, count 2 2006.173.01:46:41.66#ibcon#about to read 6, iclass 24, count 2 2006.173.01:46:41.66#ibcon#read 6, iclass 24, count 2 2006.173.01:46:41.66#ibcon#end of sib2, iclass 24, count 2 2006.173.01:46:41.66#ibcon#*mode == 0, iclass 24, count 2 2006.173.01:46:41.66#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.01:46:41.66#ibcon#[27=AT01-04\r\n] 2006.173.01:46:41.66#ibcon#*before write, iclass 24, count 2 2006.173.01:46:41.66#ibcon#enter sib2, iclass 24, count 2 2006.173.01:46:41.66#ibcon#flushed, iclass 24, count 2 2006.173.01:46:41.66#ibcon#about to write, iclass 24, count 2 2006.173.01:46:41.66#ibcon#wrote, iclass 24, count 2 2006.173.01:46:41.66#ibcon#about to read 3, iclass 24, count 2 2006.173.01:46:41.69#ibcon#read 3, iclass 24, count 2 2006.173.01:46:41.69#ibcon#about to read 4, iclass 24, count 2 2006.173.01:46:41.69#ibcon#read 4, iclass 24, count 2 2006.173.01:46:41.69#ibcon#about to read 5, iclass 24, count 2 2006.173.01:46:41.69#ibcon#read 5, iclass 24, count 2 2006.173.01:46:41.69#ibcon#about to read 6, iclass 24, count 2 2006.173.01:46:41.69#ibcon#read 6, iclass 24, count 2 2006.173.01:46:41.69#ibcon#end of sib2, iclass 24, count 2 2006.173.01:46:41.69#ibcon#*after write, iclass 24, count 2 2006.173.01:46:41.69#ibcon#*before return 0, iclass 24, count 2 2006.173.01:46:41.69#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.01:46:41.69#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.01:46:41.69#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.01:46:41.69#ibcon#ireg 7 cls_cnt 0 2006.173.01:46:41.69#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.01:46:41.81#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.01:46:41.81#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.01:46:41.81#ibcon#enter wrdev, iclass 24, count 0 2006.173.01:46:41.81#ibcon#first serial, iclass 24, count 0 2006.173.01:46:41.81#ibcon#enter sib2, iclass 24, count 0 2006.173.01:46:41.81#ibcon#flushed, iclass 24, count 0 2006.173.01:46:41.81#ibcon#about to write, iclass 24, count 0 2006.173.01:46:41.81#ibcon#wrote, iclass 24, count 0 2006.173.01:46:41.81#ibcon#about to read 3, iclass 24, count 0 2006.173.01:46:41.83#ibcon#read 3, iclass 24, count 0 2006.173.01:46:41.83#ibcon#about to read 4, iclass 24, count 0 2006.173.01:46:41.83#ibcon#read 4, iclass 24, count 0 2006.173.01:46:41.83#ibcon#about to read 5, iclass 24, count 0 2006.173.01:46:41.83#ibcon#read 5, iclass 24, count 0 2006.173.01:46:41.83#ibcon#about to read 6, iclass 24, count 0 2006.173.01:46:41.83#ibcon#read 6, iclass 24, count 0 2006.173.01:46:41.83#ibcon#end of sib2, iclass 24, count 0 2006.173.01:46:41.83#ibcon#*mode == 0, iclass 24, count 0 2006.173.01:46:41.83#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.01:46:41.83#ibcon#[27=USB\r\n] 2006.173.01:46:41.83#ibcon#*before write, iclass 24, count 0 2006.173.01:46:41.83#ibcon#enter sib2, iclass 24, count 0 2006.173.01:46:41.83#ibcon#flushed, iclass 24, count 0 2006.173.01:46:41.83#ibcon#about to write, iclass 24, count 0 2006.173.01:46:41.83#ibcon#wrote, iclass 24, count 0 2006.173.01:46:41.83#ibcon#about to read 3, iclass 24, count 0 2006.173.01:46:41.86#ibcon#read 3, iclass 24, count 0 2006.173.01:46:41.86#ibcon#about to read 4, iclass 24, count 0 2006.173.01:46:41.86#ibcon#read 4, iclass 24, count 0 2006.173.01:46:41.86#ibcon#about to read 5, iclass 24, count 0 2006.173.01:46:41.86#ibcon#read 5, iclass 24, count 0 2006.173.01:46:41.86#ibcon#about to read 6, iclass 24, count 0 2006.173.01:46:41.86#ibcon#read 6, iclass 24, count 0 2006.173.01:46:41.86#ibcon#end of sib2, iclass 24, count 0 2006.173.01:46:41.86#ibcon#*after write, iclass 24, count 0 2006.173.01:46:41.86#ibcon#*before return 0, iclass 24, count 0 2006.173.01:46:41.86#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.01:46:41.86#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.01:46:41.86#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.01:46:41.86#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.01:46:41.86$vck44/vblo=2,634.99 2006.173.01:46:41.86#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.01:46:41.86#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.01:46:41.86#ibcon#ireg 17 cls_cnt 0 2006.173.01:46:41.86#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.01:46:41.86#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.01:46:41.86#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.01:46:41.86#ibcon#enter wrdev, iclass 26, count 0 2006.173.01:46:41.86#ibcon#first serial, iclass 26, count 0 2006.173.01:46:41.86#ibcon#enter sib2, iclass 26, count 0 2006.173.01:46:41.86#ibcon#flushed, iclass 26, count 0 2006.173.01:46:41.86#ibcon#about to write, iclass 26, count 0 2006.173.01:46:41.86#ibcon#wrote, iclass 26, count 0 2006.173.01:46:41.86#ibcon#about to read 3, iclass 26, count 0 2006.173.01:46:41.88#ibcon#read 3, iclass 26, count 0 2006.173.01:46:41.88#ibcon#about to read 4, iclass 26, count 0 2006.173.01:46:41.88#ibcon#read 4, iclass 26, count 0 2006.173.01:46:41.88#ibcon#about to read 5, iclass 26, count 0 2006.173.01:46:41.88#ibcon#read 5, iclass 26, count 0 2006.173.01:46:41.88#ibcon#about to read 6, iclass 26, count 0 2006.173.01:46:41.88#ibcon#read 6, iclass 26, count 0 2006.173.01:46:41.88#ibcon#end of sib2, iclass 26, count 0 2006.173.01:46:41.88#ibcon#*mode == 0, iclass 26, count 0 2006.173.01:46:41.88#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.01:46:41.88#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.01:46:41.88#ibcon#*before write, iclass 26, count 0 2006.173.01:46:41.88#ibcon#enter sib2, iclass 26, count 0 2006.173.01:46:41.88#ibcon#flushed, iclass 26, count 0 2006.173.01:46:41.88#ibcon#about to write, iclass 26, count 0 2006.173.01:46:41.88#ibcon#wrote, iclass 26, count 0 2006.173.01:46:41.88#ibcon#about to read 3, iclass 26, count 0 2006.173.01:46:41.92#ibcon#read 3, iclass 26, count 0 2006.173.01:46:41.92#ibcon#about to read 4, iclass 26, count 0 2006.173.01:46:41.92#ibcon#read 4, iclass 26, count 0 2006.173.01:46:41.92#ibcon#about to read 5, iclass 26, count 0 2006.173.01:46:41.92#ibcon#read 5, iclass 26, count 0 2006.173.01:46:41.92#ibcon#about to read 6, iclass 26, count 0 2006.173.01:46:41.92#ibcon#read 6, iclass 26, count 0 2006.173.01:46:41.92#ibcon#end of sib2, iclass 26, count 0 2006.173.01:46:41.92#ibcon#*after write, iclass 26, count 0 2006.173.01:46:41.92#ibcon#*before return 0, iclass 26, count 0 2006.173.01:46:41.92#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.01:46:41.92#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.01:46:41.92#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.01:46:41.92#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.01:46:41.92$vck44/vb=2,4 2006.173.01:46:41.92#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.01:46:41.92#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.01:46:41.92#ibcon#ireg 11 cls_cnt 2 2006.173.01:46:41.92#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.01:46:41.98#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.01:46:41.98#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.01:46:41.98#ibcon#enter wrdev, iclass 28, count 2 2006.173.01:46:41.98#ibcon#first serial, iclass 28, count 2 2006.173.01:46:41.98#ibcon#enter sib2, iclass 28, count 2 2006.173.01:46:41.98#ibcon#flushed, iclass 28, count 2 2006.173.01:46:41.98#ibcon#about to write, iclass 28, count 2 2006.173.01:46:41.98#ibcon#wrote, iclass 28, count 2 2006.173.01:46:41.98#ibcon#about to read 3, iclass 28, count 2 2006.173.01:46:42.00#ibcon#read 3, iclass 28, count 2 2006.173.01:46:42.00#ibcon#about to read 4, iclass 28, count 2 2006.173.01:46:42.00#ibcon#read 4, iclass 28, count 2 2006.173.01:46:42.00#ibcon#about to read 5, iclass 28, count 2 2006.173.01:46:42.00#ibcon#read 5, iclass 28, count 2 2006.173.01:46:42.00#ibcon#about to read 6, iclass 28, count 2 2006.173.01:46:42.00#ibcon#read 6, iclass 28, count 2 2006.173.01:46:42.00#ibcon#end of sib2, iclass 28, count 2 2006.173.01:46:42.00#ibcon#*mode == 0, iclass 28, count 2 2006.173.01:46:42.00#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.01:46:42.00#ibcon#[27=AT02-04\r\n] 2006.173.01:46:42.00#ibcon#*before write, iclass 28, count 2 2006.173.01:46:42.00#ibcon#enter sib2, iclass 28, count 2 2006.173.01:46:42.00#ibcon#flushed, iclass 28, count 2 2006.173.01:46:42.00#ibcon#about to write, iclass 28, count 2 2006.173.01:46:42.00#ibcon#wrote, iclass 28, count 2 2006.173.01:46:42.00#ibcon#about to read 3, iclass 28, count 2 2006.173.01:46:42.03#ibcon#read 3, iclass 28, count 2 2006.173.01:46:42.03#ibcon#about to read 4, iclass 28, count 2 2006.173.01:46:42.03#ibcon#read 4, iclass 28, count 2 2006.173.01:46:42.03#ibcon#about to read 5, iclass 28, count 2 2006.173.01:46:42.03#ibcon#read 5, iclass 28, count 2 2006.173.01:46:42.03#ibcon#about to read 6, iclass 28, count 2 2006.173.01:46:42.03#ibcon#read 6, iclass 28, count 2 2006.173.01:46:42.03#ibcon#end of sib2, iclass 28, count 2 2006.173.01:46:42.03#ibcon#*after write, iclass 28, count 2 2006.173.01:46:42.03#ibcon#*before return 0, iclass 28, count 2 2006.173.01:46:42.03#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.01:46:42.03#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.01:46:42.03#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.01:46:42.03#ibcon#ireg 7 cls_cnt 0 2006.173.01:46:42.03#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.01:46:42.15#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.01:46:42.15#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.01:46:42.15#ibcon#enter wrdev, iclass 28, count 0 2006.173.01:46:42.15#ibcon#first serial, iclass 28, count 0 2006.173.01:46:42.15#ibcon#enter sib2, iclass 28, count 0 2006.173.01:46:42.15#ibcon#flushed, iclass 28, count 0 2006.173.01:46:42.15#ibcon#about to write, iclass 28, count 0 2006.173.01:46:42.15#ibcon#wrote, iclass 28, count 0 2006.173.01:46:42.15#ibcon#about to read 3, iclass 28, count 0 2006.173.01:46:42.17#ibcon#read 3, iclass 28, count 0 2006.173.01:46:42.17#ibcon#about to read 4, iclass 28, count 0 2006.173.01:46:42.17#ibcon#read 4, iclass 28, count 0 2006.173.01:46:42.17#ibcon#about to read 5, iclass 28, count 0 2006.173.01:46:42.17#ibcon#read 5, iclass 28, count 0 2006.173.01:46:42.17#ibcon#about to read 6, iclass 28, count 0 2006.173.01:46:42.17#ibcon#read 6, iclass 28, count 0 2006.173.01:46:42.17#ibcon#end of sib2, iclass 28, count 0 2006.173.01:46:42.17#ibcon#*mode == 0, iclass 28, count 0 2006.173.01:46:42.17#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.01:46:42.17#ibcon#[27=USB\r\n] 2006.173.01:46:42.17#ibcon#*before write, iclass 28, count 0 2006.173.01:46:42.17#ibcon#enter sib2, iclass 28, count 0 2006.173.01:46:42.17#ibcon#flushed, iclass 28, count 0 2006.173.01:46:42.17#ibcon#about to write, iclass 28, count 0 2006.173.01:46:42.17#ibcon#wrote, iclass 28, count 0 2006.173.01:46:42.17#ibcon#about to read 3, iclass 28, count 0 2006.173.01:46:42.20#ibcon#read 3, iclass 28, count 0 2006.173.01:46:42.20#ibcon#about to read 4, iclass 28, count 0 2006.173.01:46:42.20#ibcon#read 4, iclass 28, count 0 2006.173.01:46:42.20#ibcon#about to read 5, iclass 28, count 0 2006.173.01:46:42.20#ibcon#read 5, iclass 28, count 0 2006.173.01:46:42.20#ibcon#about to read 6, iclass 28, count 0 2006.173.01:46:42.20#ibcon#read 6, iclass 28, count 0 2006.173.01:46:42.20#ibcon#end of sib2, iclass 28, count 0 2006.173.01:46:42.20#ibcon#*after write, iclass 28, count 0 2006.173.01:46:42.20#ibcon#*before return 0, iclass 28, count 0 2006.173.01:46:42.20#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.01:46:42.20#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.01:46:42.20#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.01:46:42.20#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.01:46:42.20$vck44/vblo=3,649.99 2006.173.01:46:42.20#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.01:46:42.20#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.01:46:42.20#ibcon#ireg 17 cls_cnt 0 2006.173.01:46:42.20#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.01:46:42.20#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.01:46:42.20#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.01:46:42.20#ibcon#enter wrdev, iclass 30, count 0 2006.173.01:46:42.20#ibcon#first serial, iclass 30, count 0 2006.173.01:46:42.20#ibcon#enter sib2, iclass 30, count 0 2006.173.01:46:42.20#ibcon#flushed, iclass 30, count 0 2006.173.01:46:42.20#ibcon#about to write, iclass 30, count 0 2006.173.01:46:42.20#ibcon#wrote, iclass 30, count 0 2006.173.01:46:42.20#ibcon#about to read 3, iclass 30, count 0 2006.173.01:46:42.22#ibcon#read 3, iclass 30, count 0 2006.173.01:46:42.22#ibcon#about to read 4, iclass 30, count 0 2006.173.01:46:42.22#ibcon#read 4, iclass 30, count 0 2006.173.01:46:42.22#ibcon#about to read 5, iclass 30, count 0 2006.173.01:46:42.22#ibcon#read 5, iclass 30, count 0 2006.173.01:46:42.22#ibcon#about to read 6, iclass 30, count 0 2006.173.01:46:42.22#ibcon#read 6, iclass 30, count 0 2006.173.01:46:42.22#ibcon#end of sib2, iclass 30, count 0 2006.173.01:46:42.22#ibcon#*mode == 0, iclass 30, count 0 2006.173.01:46:42.22#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.01:46:42.22#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.01:46:42.22#ibcon#*before write, iclass 30, count 0 2006.173.01:46:42.22#ibcon#enter sib2, iclass 30, count 0 2006.173.01:46:42.22#ibcon#flushed, iclass 30, count 0 2006.173.01:46:42.22#ibcon#about to write, iclass 30, count 0 2006.173.01:46:42.22#ibcon#wrote, iclass 30, count 0 2006.173.01:46:42.22#ibcon#about to read 3, iclass 30, count 0 2006.173.01:46:42.26#ibcon#read 3, iclass 30, count 0 2006.173.01:46:42.26#ibcon#about to read 4, iclass 30, count 0 2006.173.01:46:42.26#ibcon#read 4, iclass 30, count 0 2006.173.01:46:42.26#ibcon#about to read 5, iclass 30, count 0 2006.173.01:46:42.26#ibcon#read 5, iclass 30, count 0 2006.173.01:46:42.26#ibcon#about to read 6, iclass 30, count 0 2006.173.01:46:42.26#ibcon#read 6, iclass 30, count 0 2006.173.01:46:42.26#ibcon#end of sib2, iclass 30, count 0 2006.173.01:46:42.26#ibcon#*after write, iclass 30, count 0 2006.173.01:46:42.26#ibcon#*before return 0, iclass 30, count 0 2006.173.01:46:42.26#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.01:46:42.26#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.01:46:42.26#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.01:46:42.26#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.01:46:42.26$vck44/vb=3,4 2006.173.01:46:42.26#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.173.01:46:42.26#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.173.01:46:42.26#ibcon#ireg 11 cls_cnt 2 2006.173.01:46:42.26#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.01:46:42.28#abcon#<5=/14 1.5 3.8 22.40 841006.9\r\n> 2006.173.01:46:42.30#abcon#{5=INTERFACE CLEAR} 2006.173.01:46:42.32#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.01:46:42.32#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.01:46:42.32#ibcon#enter wrdev, iclass 33, count 2 2006.173.01:46:42.32#ibcon#first serial, iclass 33, count 2 2006.173.01:46:42.32#ibcon#enter sib2, iclass 33, count 2 2006.173.01:46:42.32#ibcon#flushed, iclass 33, count 2 2006.173.01:46:42.32#ibcon#about to write, iclass 33, count 2 2006.173.01:46:42.32#ibcon#wrote, iclass 33, count 2 2006.173.01:46:42.32#ibcon#about to read 3, iclass 33, count 2 2006.173.01:46:42.34#ibcon#read 3, iclass 33, count 2 2006.173.01:46:42.34#ibcon#about to read 4, iclass 33, count 2 2006.173.01:46:42.34#ibcon#read 4, iclass 33, count 2 2006.173.01:46:42.34#ibcon#about to read 5, iclass 33, count 2 2006.173.01:46:42.34#ibcon#read 5, iclass 33, count 2 2006.173.01:46:42.34#ibcon#about to read 6, iclass 33, count 2 2006.173.01:46:42.34#ibcon#read 6, iclass 33, count 2 2006.173.01:46:42.34#ibcon#end of sib2, iclass 33, count 2 2006.173.01:46:42.34#ibcon#*mode == 0, iclass 33, count 2 2006.173.01:46:42.34#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.173.01:46:42.34#ibcon#[27=AT03-04\r\n] 2006.173.01:46:42.34#ibcon#*before write, iclass 33, count 2 2006.173.01:46:42.34#ibcon#enter sib2, iclass 33, count 2 2006.173.01:46:42.34#ibcon#flushed, iclass 33, count 2 2006.173.01:46:42.34#ibcon#about to write, iclass 33, count 2 2006.173.01:46:42.34#ibcon#wrote, iclass 33, count 2 2006.173.01:46:42.34#ibcon#about to read 3, iclass 33, count 2 2006.173.01:46:42.36#abcon#[5=S1D000X0/0*\r\n] 2006.173.01:46:42.37#ibcon#read 3, iclass 33, count 2 2006.173.01:46:42.37#ibcon#about to read 4, iclass 33, count 2 2006.173.01:46:42.37#ibcon#read 4, iclass 33, count 2 2006.173.01:46:42.37#ibcon#about to read 5, iclass 33, count 2 2006.173.01:46:42.37#ibcon#read 5, iclass 33, count 2 2006.173.01:46:42.37#ibcon#about to read 6, iclass 33, count 2 2006.173.01:46:42.37#ibcon#read 6, iclass 33, count 2 2006.173.01:46:42.37#ibcon#end of sib2, iclass 33, count 2 2006.173.01:46:42.37#ibcon#*after write, iclass 33, count 2 2006.173.01:46:42.37#ibcon#*before return 0, iclass 33, count 2 2006.173.01:46:42.37#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.01:46:42.37#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.173.01:46:42.37#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.173.01:46:42.37#ibcon#ireg 7 cls_cnt 0 2006.173.01:46:42.37#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.01:46:42.49#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.01:46:42.49#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.01:46:42.49#ibcon#enter wrdev, iclass 33, count 0 2006.173.01:46:42.49#ibcon#first serial, iclass 33, count 0 2006.173.01:46:42.49#ibcon#enter sib2, iclass 33, count 0 2006.173.01:46:42.49#ibcon#flushed, iclass 33, count 0 2006.173.01:46:42.49#ibcon#about to write, iclass 33, count 0 2006.173.01:46:42.49#ibcon#wrote, iclass 33, count 0 2006.173.01:46:42.49#ibcon#about to read 3, iclass 33, count 0 2006.173.01:46:42.51#ibcon#read 3, iclass 33, count 0 2006.173.01:46:42.51#ibcon#about to read 4, iclass 33, count 0 2006.173.01:46:42.51#ibcon#read 4, iclass 33, count 0 2006.173.01:46:42.51#ibcon#about to read 5, iclass 33, count 0 2006.173.01:46:42.51#ibcon#read 5, iclass 33, count 0 2006.173.01:46:42.51#ibcon#about to read 6, iclass 33, count 0 2006.173.01:46:42.51#ibcon#read 6, iclass 33, count 0 2006.173.01:46:42.51#ibcon#end of sib2, iclass 33, count 0 2006.173.01:46:42.51#ibcon#*mode == 0, iclass 33, count 0 2006.173.01:46:42.51#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.01:46:42.51#ibcon#[27=USB\r\n] 2006.173.01:46:42.51#ibcon#*before write, iclass 33, count 0 2006.173.01:46:42.51#ibcon#enter sib2, iclass 33, count 0 2006.173.01:46:42.51#ibcon#flushed, iclass 33, count 0 2006.173.01:46:42.51#ibcon#about to write, iclass 33, count 0 2006.173.01:46:42.51#ibcon#wrote, iclass 33, count 0 2006.173.01:46:42.51#ibcon#about to read 3, iclass 33, count 0 2006.173.01:46:42.54#ibcon#read 3, iclass 33, count 0 2006.173.01:46:42.54#ibcon#about to read 4, iclass 33, count 0 2006.173.01:46:42.54#ibcon#read 4, iclass 33, count 0 2006.173.01:46:42.54#ibcon#about to read 5, iclass 33, count 0 2006.173.01:46:42.54#ibcon#read 5, iclass 33, count 0 2006.173.01:46:42.54#ibcon#about to read 6, iclass 33, count 0 2006.173.01:46:42.54#ibcon#read 6, iclass 33, count 0 2006.173.01:46:42.54#ibcon#end of sib2, iclass 33, count 0 2006.173.01:46:42.54#ibcon#*after write, iclass 33, count 0 2006.173.01:46:42.54#ibcon#*before return 0, iclass 33, count 0 2006.173.01:46:42.54#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.01:46:42.54#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.173.01:46:42.54#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.01:46:42.54#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.01:46:42.54$vck44/vblo=4,679.99 2006.173.01:46:42.54#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.01:46:42.54#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.01:46:42.54#ibcon#ireg 17 cls_cnt 0 2006.173.01:46:42.54#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.01:46:42.54#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.01:46:42.54#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.01:46:42.54#ibcon#enter wrdev, iclass 38, count 0 2006.173.01:46:42.54#ibcon#first serial, iclass 38, count 0 2006.173.01:46:42.54#ibcon#enter sib2, iclass 38, count 0 2006.173.01:46:42.54#ibcon#flushed, iclass 38, count 0 2006.173.01:46:42.54#ibcon#about to write, iclass 38, count 0 2006.173.01:46:42.54#ibcon#wrote, iclass 38, count 0 2006.173.01:46:42.54#ibcon#about to read 3, iclass 38, count 0 2006.173.01:46:42.56#ibcon#read 3, iclass 38, count 0 2006.173.01:46:42.56#ibcon#about to read 4, iclass 38, count 0 2006.173.01:46:42.56#ibcon#read 4, iclass 38, count 0 2006.173.01:46:42.56#ibcon#about to read 5, iclass 38, count 0 2006.173.01:46:42.56#ibcon#read 5, iclass 38, count 0 2006.173.01:46:42.56#ibcon#about to read 6, iclass 38, count 0 2006.173.01:46:42.56#ibcon#read 6, iclass 38, count 0 2006.173.01:46:42.56#ibcon#end of sib2, iclass 38, count 0 2006.173.01:46:42.56#ibcon#*mode == 0, iclass 38, count 0 2006.173.01:46:42.56#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.01:46:42.56#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.01:46:42.56#ibcon#*before write, iclass 38, count 0 2006.173.01:46:42.56#ibcon#enter sib2, iclass 38, count 0 2006.173.01:46:42.56#ibcon#flushed, iclass 38, count 0 2006.173.01:46:42.56#ibcon#about to write, iclass 38, count 0 2006.173.01:46:42.56#ibcon#wrote, iclass 38, count 0 2006.173.01:46:42.56#ibcon#about to read 3, iclass 38, count 0 2006.173.01:46:42.60#ibcon#read 3, iclass 38, count 0 2006.173.01:46:42.60#ibcon#about to read 4, iclass 38, count 0 2006.173.01:46:42.60#ibcon#read 4, iclass 38, count 0 2006.173.01:46:42.60#ibcon#about to read 5, iclass 38, count 0 2006.173.01:46:42.60#ibcon#read 5, iclass 38, count 0 2006.173.01:46:42.60#ibcon#about to read 6, iclass 38, count 0 2006.173.01:46:42.60#ibcon#read 6, iclass 38, count 0 2006.173.01:46:42.60#ibcon#end of sib2, iclass 38, count 0 2006.173.01:46:42.60#ibcon#*after write, iclass 38, count 0 2006.173.01:46:42.60#ibcon#*before return 0, iclass 38, count 0 2006.173.01:46:42.60#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.01:46:42.60#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.01:46:42.60#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.01:46:42.60#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.01:46:42.60$vck44/vb=4,4 2006.173.01:46:42.60#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.01:46:42.60#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.01:46:42.60#ibcon#ireg 11 cls_cnt 2 2006.173.01:46:42.60#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.01:46:42.66#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.01:46:42.66#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.01:46:42.66#ibcon#enter wrdev, iclass 40, count 2 2006.173.01:46:42.66#ibcon#first serial, iclass 40, count 2 2006.173.01:46:42.66#ibcon#enter sib2, iclass 40, count 2 2006.173.01:46:42.66#ibcon#flushed, iclass 40, count 2 2006.173.01:46:42.66#ibcon#about to write, iclass 40, count 2 2006.173.01:46:42.66#ibcon#wrote, iclass 40, count 2 2006.173.01:46:42.66#ibcon#about to read 3, iclass 40, count 2 2006.173.01:46:42.68#ibcon#read 3, iclass 40, count 2 2006.173.01:46:42.68#ibcon#about to read 4, iclass 40, count 2 2006.173.01:46:42.68#ibcon#read 4, iclass 40, count 2 2006.173.01:46:42.68#ibcon#about to read 5, iclass 40, count 2 2006.173.01:46:42.68#ibcon#read 5, iclass 40, count 2 2006.173.01:46:42.68#ibcon#about to read 6, iclass 40, count 2 2006.173.01:46:42.68#ibcon#read 6, iclass 40, count 2 2006.173.01:46:42.68#ibcon#end of sib2, iclass 40, count 2 2006.173.01:46:42.68#ibcon#*mode == 0, iclass 40, count 2 2006.173.01:46:42.68#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.01:46:42.68#ibcon#[27=AT04-04\r\n] 2006.173.01:46:42.68#ibcon#*before write, iclass 40, count 2 2006.173.01:46:42.68#ibcon#enter sib2, iclass 40, count 2 2006.173.01:46:42.68#ibcon#flushed, iclass 40, count 2 2006.173.01:46:42.68#ibcon#about to write, iclass 40, count 2 2006.173.01:46:42.68#ibcon#wrote, iclass 40, count 2 2006.173.01:46:42.68#ibcon#about to read 3, iclass 40, count 2 2006.173.01:46:42.71#ibcon#read 3, iclass 40, count 2 2006.173.01:46:42.71#ibcon#about to read 4, iclass 40, count 2 2006.173.01:46:42.71#ibcon#read 4, iclass 40, count 2 2006.173.01:46:42.71#ibcon#about to read 5, iclass 40, count 2 2006.173.01:46:42.71#ibcon#read 5, iclass 40, count 2 2006.173.01:46:42.71#ibcon#about to read 6, iclass 40, count 2 2006.173.01:46:42.71#ibcon#read 6, iclass 40, count 2 2006.173.01:46:42.71#ibcon#end of sib2, iclass 40, count 2 2006.173.01:46:42.71#ibcon#*after write, iclass 40, count 2 2006.173.01:46:42.71#ibcon#*before return 0, iclass 40, count 2 2006.173.01:46:42.71#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.01:46:42.71#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.01:46:42.71#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.01:46:42.71#ibcon#ireg 7 cls_cnt 0 2006.173.01:46:42.71#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.01:46:42.83#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.01:46:42.83#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.01:46:42.83#ibcon#enter wrdev, iclass 40, count 0 2006.173.01:46:42.83#ibcon#first serial, iclass 40, count 0 2006.173.01:46:42.83#ibcon#enter sib2, iclass 40, count 0 2006.173.01:46:42.83#ibcon#flushed, iclass 40, count 0 2006.173.01:46:42.83#ibcon#about to write, iclass 40, count 0 2006.173.01:46:42.83#ibcon#wrote, iclass 40, count 0 2006.173.01:46:42.83#ibcon#about to read 3, iclass 40, count 0 2006.173.01:46:42.85#ibcon#read 3, iclass 40, count 0 2006.173.01:46:42.85#ibcon#about to read 4, iclass 40, count 0 2006.173.01:46:42.85#ibcon#read 4, iclass 40, count 0 2006.173.01:46:42.85#ibcon#about to read 5, iclass 40, count 0 2006.173.01:46:42.85#ibcon#read 5, iclass 40, count 0 2006.173.01:46:42.85#ibcon#about to read 6, iclass 40, count 0 2006.173.01:46:42.85#ibcon#read 6, iclass 40, count 0 2006.173.01:46:42.85#ibcon#end of sib2, iclass 40, count 0 2006.173.01:46:42.85#ibcon#*mode == 0, iclass 40, count 0 2006.173.01:46:42.85#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.01:46:42.85#ibcon#[27=USB\r\n] 2006.173.01:46:42.85#ibcon#*before write, iclass 40, count 0 2006.173.01:46:42.85#ibcon#enter sib2, iclass 40, count 0 2006.173.01:46:42.85#ibcon#flushed, iclass 40, count 0 2006.173.01:46:42.85#ibcon#about to write, iclass 40, count 0 2006.173.01:46:42.85#ibcon#wrote, iclass 40, count 0 2006.173.01:46:42.85#ibcon#about to read 3, iclass 40, count 0 2006.173.01:46:42.88#ibcon#read 3, iclass 40, count 0 2006.173.01:46:42.88#ibcon#about to read 4, iclass 40, count 0 2006.173.01:46:42.88#ibcon#read 4, iclass 40, count 0 2006.173.01:46:42.88#ibcon#about to read 5, iclass 40, count 0 2006.173.01:46:42.88#ibcon#read 5, iclass 40, count 0 2006.173.01:46:42.88#ibcon#about to read 6, iclass 40, count 0 2006.173.01:46:42.88#ibcon#read 6, iclass 40, count 0 2006.173.01:46:42.88#ibcon#end of sib2, iclass 40, count 0 2006.173.01:46:42.88#ibcon#*after write, iclass 40, count 0 2006.173.01:46:42.88#ibcon#*before return 0, iclass 40, count 0 2006.173.01:46:42.88#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.01:46:42.88#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.01:46:42.88#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.01:46:42.88#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.01:46:42.88$vck44/vblo=5,709.99 2006.173.01:46:42.88#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.01:46:42.88#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.01:46:42.88#ibcon#ireg 17 cls_cnt 0 2006.173.01:46:42.88#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.01:46:42.88#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.01:46:42.88#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.01:46:42.88#ibcon#enter wrdev, iclass 4, count 0 2006.173.01:46:42.88#ibcon#first serial, iclass 4, count 0 2006.173.01:46:42.88#ibcon#enter sib2, iclass 4, count 0 2006.173.01:46:42.88#ibcon#flushed, iclass 4, count 0 2006.173.01:46:42.88#ibcon#about to write, iclass 4, count 0 2006.173.01:46:42.88#ibcon#wrote, iclass 4, count 0 2006.173.01:46:42.88#ibcon#about to read 3, iclass 4, count 0 2006.173.01:46:42.90#ibcon#read 3, iclass 4, count 0 2006.173.01:46:42.90#ibcon#about to read 4, iclass 4, count 0 2006.173.01:46:42.90#ibcon#read 4, iclass 4, count 0 2006.173.01:46:42.90#ibcon#about to read 5, iclass 4, count 0 2006.173.01:46:42.90#ibcon#read 5, iclass 4, count 0 2006.173.01:46:42.90#ibcon#about to read 6, iclass 4, count 0 2006.173.01:46:42.90#ibcon#read 6, iclass 4, count 0 2006.173.01:46:42.90#ibcon#end of sib2, iclass 4, count 0 2006.173.01:46:42.90#ibcon#*mode == 0, iclass 4, count 0 2006.173.01:46:42.90#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.01:46:42.90#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.01:46:42.90#ibcon#*before write, iclass 4, count 0 2006.173.01:46:42.90#ibcon#enter sib2, iclass 4, count 0 2006.173.01:46:42.90#ibcon#flushed, iclass 4, count 0 2006.173.01:46:42.90#ibcon#about to write, iclass 4, count 0 2006.173.01:46:42.90#ibcon#wrote, iclass 4, count 0 2006.173.01:46:42.90#ibcon#about to read 3, iclass 4, count 0 2006.173.01:46:42.94#ibcon#read 3, iclass 4, count 0 2006.173.01:46:42.94#ibcon#about to read 4, iclass 4, count 0 2006.173.01:46:42.94#ibcon#read 4, iclass 4, count 0 2006.173.01:46:42.94#ibcon#about to read 5, iclass 4, count 0 2006.173.01:46:42.94#ibcon#read 5, iclass 4, count 0 2006.173.01:46:42.94#ibcon#about to read 6, iclass 4, count 0 2006.173.01:46:42.94#ibcon#read 6, iclass 4, count 0 2006.173.01:46:42.94#ibcon#end of sib2, iclass 4, count 0 2006.173.01:46:42.94#ibcon#*after write, iclass 4, count 0 2006.173.01:46:42.94#ibcon#*before return 0, iclass 4, count 0 2006.173.01:46:42.94#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.01:46:42.94#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.01:46:42.94#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.01:46:42.94#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.01:46:42.94$vck44/vb=5,4 2006.173.01:46:42.94#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.01:46:42.94#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.01:46:42.94#ibcon#ireg 11 cls_cnt 2 2006.173.01:46:42.94#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.01:46:43.00#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.01:46:43.00#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.01:46:43.00#ibcon#enter wrdev, iclass 6, count 2 2006.173.01:46:43.00#ibcon#first serial, iclass 6, count 2 2006.173.01:46:43.00#ibcon#enter sib2, iclass 6, count 2 2006.173.01:46:43.00#ibcon#flushed, iclass 6, count 2 2006.173.01:46:43.00#ibcon#about to write, iclass 6, count 2 2006.173.01:46:43.00#ibcon#wrote, iclass 6, count 2 2006.173.01:46:43.00#ibcon#about to read 3, iclass 6, count 2 2006.173.01:46:43.02#ibcon#read 3, iclass 6, count 2 2006.173.01:46:43.02#ibcon#about to read 4, iclass 6, count 2 2006.173.01:46:43.02#ibcon#read 4, iclass 6, count 2 2006.173.01:46:43.02#ibcon#about to read 5, iclass 6, count 2 2006.173.01:46:43.02#ibcon#read 5, iclass 6, count 2 2006.173.01:46:43.02#ibcon#about to read 6, iclass 6, count 2 2006.173.01:46:43.02#ibcon#read 6, iclass 6, count 2 2006.173.01:46:43.02#ibcon#end of sib2, iclass 6, count 2 2006.173.01:46:43.02#ibcon#*mode == 0, iclass 6, count 2 2006.173.01:46:43.02#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.01:46:43.02#ibcon#[27=AT05-04\r\n] 2006.173.01:46:43.02#ibcon#*before write, iclass 6, count 2 2006.173.01:46:43.02#ibcon#enter sib2, iclass 6, count 2 2006.173.01:46:43.02#ibcon#flushed, iclass 6, count 2 2006.173.01:46:43.02#ibcon#about to write, iclass 6, count 2 2006.173.01:46:43.02#ibcon#wrote, iclass 6, count 2 2006.173.01:46:43.02#ibcon#about to read 3, iclass 6, count 2 2006.173.01:46:43.05#ibcon#read 3, iclass 6, count 2 2006.173.01:46:43.05#ibcon#about to read 4, iclass 6, count 2 2006.173.01:46:43.05#ibcon#read 4, iclass 6, count 2 2006.173.01:46:43.05#ibcon#about to read 5, iclass 6, count 2 2006.173.01:46:43.05#ibcon#read 5, iclass 6, count 2 2006.173.01:46:43.05#ibcon#about to read 6, iclass 6, count 2 2006.173.01:46:43.05#ibcon#read 6, iclass 6, count 2 2006.173.01:46:43.05#ibcon#end of sib2, iclass 6, count 2 2006.173.01:46:43.05#ibcon#*after write, iclass 6, count 2 2006.173.01:46:43.05#ibcon#*before return 0, iclass 6, count 2 2006.173.01:46:43.05#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.01:46:43.05#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.01:46:43.05#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.01:46:43.05#ibcon#ireg 7 cls_cnt 0 2006.173.01:46:43.05#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.01:46:43.17#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.01:46:43.17#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.01:46:43.17#ibcon#enter wrdev, iclass 6, count 0 2006.173.01:46:43.17#ibcon#first serial, iclass 6, count 0 2006.173.01:46:43.17#ibcon#enter sib2, iclass 6, count 0 2006.173.01:46:43.17#ibcon#flushed, iclass 6, count 0 2006.173.01:46:43.17#ibcon#about to write, iclass 6, count 0 2006.173.01:46:43.17#ibcon#wrote, iclass 6, count 0 2006.173.01:46:43.17#ibcon#about to read 3, iclass 6, count 0 2006.173.01:46:43.19#ibcon#read 3, iclass 6, count 0 2006.173.01:46:43.19#ibcon#about to read 4, iclass 6, count 0 2006.173.01:46:43.19#ibcon#read 4, iclass 6, count 0 2006.173.01:46:43.19#ibcon#about to read 5, iclass 6, count 0 2006.173.01:46:43.19#ibcon#read 5, iclass 6, count 0 2006.173.01:46:43.19#ibcon#about to read 6, iclass 6, count 0 2006.173.01:46:43.19#ibcon#read 6, iclass 6, count 0 2006.173.01:46:43.19#ibcon#end of sib2, iclass 6, count 0 2006.173.01:46:43.19#ibcon#*mode == 0, iclass 6, count 0 2006.173.01:46:43.19#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.01:46:43.19#ibcon#[27=USB\r\n] 2006.173.01:46:43.19#ibcon#*before write, iclass 6, count 0 2006.173.01:46:43.19#ibcon#enter sib2, iclass 6, count 0 2006.173.01:46:43.19#ibcon#flushed, iclass 6, count 0 2006.173.01:46:43.19#ibcon#about to write, iclass 6, count 0 2006.173.01:46:43.19#ibcon#wrote, iclass 6, count 0 2006.173.01:46:43.19#ibcon#about to read 3, iclass 6, count 0 2006.173.01:46:43.22#ibcon#read 3, iclass 6, count 0 2006.173.01:46:43.22#ibcon#about to read 4, iclass 6, count 0 2006.173.01:46:43.22#ibcon#read 4, iclass 6, count 0 2006.173.01:46:43.22#ibcon#about to read 5, iclass 6, count 0 2006.173.01:46:43.22#ibcon#read 5, iclass 6, count 0 2006.173.01:46:43.22#ibcon#about to read 6, iclass 6, count 0 2006.173.01:46:43.22#ibcon#read 6, iclass 6, count 0 2006.173.01:46:43.22#ibcon#end of sib2, iclass 6, count 0 2006.173.01:46:43.22#ibcon#*after write, iclass 6, count 0 2006.173.01:46:43.22#ibcon#*before return 0, iclass 6, count 0 2006.173.01:46:43.22#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.01:46:43.22#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.01:46:43.22#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.01:46:43.22#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.01:46:43.22$vck44/vblo=6,719.99 2006.173.01:46:43.22#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.01:46:43.22#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.01:46:43.22#ibcon#ireg 17 cls_cnt 0 2006.173.01:46:43.22#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.01:46:43.22#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.01:46:43.22#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.01:46:43.22#ibcon#enter wrdev, iclass 10, count 0 2006.173.01:46:43.22#ibcon#first serial, iclass 10, count 0 2006.173.01:46:43.22#ibcon#enter sib2, iclass 10, count 0 2006.173.01:46:43.22#ibcon#flushed, iclass 10, count 0 2006.173.01:46:43.22#ibcon#about to write, iclass 10, count 0 2006.173.01:46:43.22#ibcon#wrote, iclass 10, count 0 2006.173.01:46:43.22#ibcon#about to read 3, iclass 10, count 0 2006.173.01:46:43.24#ibcon#read 3, iclass 10, count 0 2006.173.01:46:43.24#ibcon#about to read 4, iclass 10, count 0 2006.173.01:46:43.24#ibcon#read 4, iclass 10, count 0 2006.173.01:46:43.24#ibcon#about to read 5, iclass 10, count 0 2006.173.01:46:43.24#ibcon#read 5, iclass 10, count 0 2006.173.01:46:43.24#ibcon#about to read 6, iclass 10, count 0 2006.173.01:46:43.24#ibcon#read 6, iclass 10, count 0 2006.173.01:46:43.24#ibcon#end of sib2, iclass 10, count 0 2006.173.01:46:43.24#ibcon#*mode == 0, iclass 10, count 0 2006.173.01:46:43.24#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.01:46:43.24#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.01:46:43.24#ibcon#*before write, iclass 10, count 0 2006.173.01:46:43.24#ibcon#enter sib2, iclass 10, count 0 2006.173.01:46:43.24#ibcon#flushed, iclass 10, count 0 2006.173.01:46:43.24#ibcon#about to write, iclass 10, count 0 2006.173.01:46:43.24#ibcon#wrote, iclass 10, count 0 2006.173.01:46:43.24#ibcon#about to read 3, iclass 10, count 0 2006.173.01:46:43.28#ibcon#read 3, iclass 10, count 0 2006.173.01:46:43.28#ibcon#about to read 4, iclass 10, count 0 2006.173.01:46:43.28#ibcon#read 4, iclass 10, count 0 2006.173.01:46:43.28#ibcon#about to read 5, iclass 10, count 0 2006.173.01:46:43.28#ibcon#read 5, iclass 10, count 0 2006.173.01:46:43.28#ibcon#about to read 6, iclass 10, count 0 2006.173.01:46:43.28#ibcon#read 6, iclass 10, count 0 2006.173.01:46:43.28#ibcon#end of sib2, iclass 10, count 0 2006.173.01:46:43.28#ibcon#*after write, iclass 10, count 0 2006.173.01:46:43.28#ibcon#*before return 0, iclass 10, count 0 2006.173.01:46:43.28#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.01:46:43.28#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.01:46:43.28#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.01:46:43.28#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.01:46:43.28$vck44/vb=6,4 2006.173.01:46:43.28#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.01:46:43.28#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.01:46:43.28#ibcon#ireg 11 cls_cnt 2 2006.173.01:46:43.28#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.01:46:43.34#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.01:46:43.34#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.01:46:43.34#ibcon#enter wrdev, iclass 12, count 2 2006.173.01:46:43.34#ibcon#first serial, iclass 12, count 2 2006.173.01:46:43.34#ibcon#enter sib2, iclass 12, count 2 2006.173.01:46:43.34#ibcon#flushed, iclass 12, count 2 2006.173.01:46:43.34#ibcon#about to write, iclass 12, count 2 2006.173.01:46:43.34#ibcon#wrote, iclass 12, count 2 2006.173.01:46:43.34#ibcon#about to read 3, iclass 12, count 2 2006.173.01:46:43.36#ibcon#read 3, iclass 12, count 2 2006.173.01:46:43.36#ibcon#about to read 4, iclass 12, count 2 2006.173.01:46:43.36#ibcon#read 4, iclass 12, count 2 2006.173.01:46:43.36#ibcon#about to read 5, iclass 12, count 2 2006.173.01:46:43.36#ibcon#read 5, iclass 12, count 2 2006.173.01:46:43.36#ibcon#about to read 6, iclass 12, count 2 2006.173.01:46:43.36#ibcon#read 6, iclass 12, count 2 2006.173.01:46:43.36#ibcon#end of sib2, iclass 12, count 2 2006.173.01:46:43.36#ibcon#*mode == 0, iclass 12, count 2 2006.173.01:46:43.36#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.01:46:43.36#ibcon#[27=AT06-04\r\n] 2006.173.01:46:43.36#ibcon#*before write, iclass 12, count 2 2006.173.01:46:43.36#ibcon#enter sib2, iclass 12, count 2 2006.173.01:46:43.36#ibcon#flushed, iclass 12, count 2 2006.173.01:46:43.36#ibcon#about to write, iclass 12, count 2 2006.173.01:46:43.36#ibcon#wrote, iclass 12, count 2 2006.173.01:46:43.36#ibcon#about to read 3, iclass 12, count 2 2006.173.01:46:43.39#ibcon#read 3, iclass 12, count 2 2006.173.01:46:43.39#ibcon#about to read 4, iclass 12, count 2 2006.173.01:46:43.39#ibcon#read 4, iclass 12, count 2 2006.173.01:46:43.39#ibcon#about to read 5, iclass 12, count 2 2006.173.01:46:43.39#ibcon#read 5, iclass 12, count 2 2006.173.01:46:43.39#ibcon#about to read 6, iclass 12, count 2 2006.173.01:46:43.39#ibcon#read 6, iclass 12, count 2 2006.173.01:46:43.39#ibcon#end of sib2, iclass 12, count 2 2006.173.01:46:43.39#ibcon#*after write, iclass 12, count 2 2006.173.01:46:43.39#ibcon#*before return 0, iclass 12, count 2 2006.173.01:46:43.39#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.01:46:43.39#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.01:46:43.39#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.01:46:43.39#ibcon#ireg 7 cls_cnt 0 2006.173.01:46:43.39#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.01:46:43.51#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.01:46:43.51#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.01:46:43.51#ibcon#enter wrdev, iclass 12, count 0 2006.173.01:46:43.51#ibcon#first serial, iclass 12, count 0 2006.173.01:46:43.51#ibcon#enter sib2, iclass 12, count 0 2006.173.01:46:43.51#ibcon#flushed, iclass 12, count 0 2006.173.01:46:43.51#ibcon#about to write, iclass 12, count 0 2006.173.01:46:43.51#ibcon#wrote, iclass 12, count 0 2006.173.01:46:43.51#ibcon#about to read 3, iclass 12, count 0 2006.173.01:46:43.53#ibcon#read 3, iclass 12, count 0 2006.173.01:46:43.53#ibcon#about to read 4, iclass 12, count 0 2006.173.01:46:43.53#ibcon#read 4, iclass 12, count 0 2006.173.01:46:43.53#ibcon#about to read 5, iclass 12, count 0 2006.173.01:46:43.53#ibcon#read 5, iclass 12, count 0 2006.173.01:46:43.53#ibcon#about to read 6, iclass 12, count 0 2006.173.01:46:43.53#ibcon#read 6, iclass 12, count 0 2006.173.01:46:43.53#ibcon#end of sib2, iclass 12, count 0 2006.173.01:46:43.53#ibcon#*mode == 0, iclass 12, count 0 2006.173.01:46:43.53#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.01:46:43.53#ibcon#[27=USB\r\n] 2006.173.01:46:43.53#ibcon#*before write, iclass 12, count 0 2006.173.01:46:43.53#ibcon#enter sib2, iclass 12, count 0 2006.173.01:46:43.53#ibcon#flushed, iclass 12, count 0 2006.173.01:46:43.53#ibcon#about to write, iclass 12, count 0 2006.173.01:46:43.53#ibcon#wrote, iclass 12, count 0 2006.173.01:46:43.53#ibcon#about to read 3, iclass 12, count 0 2006.173.01:46:43.56#ibcon#read 3, iclass 12, count 0 2006.173.01:46:43.56#ibcon#about to read 4, iclass 12, count 0 2006.173.01:46:43.56#ibcon#read 4, iclass 12, count 0 2006.173.01:46:43.56#ibcon#about to read 5, iclass 12, count 0 2006.173.01:46:43.56#ibcon#read 5, iclass 12, count 0 2006.173.01:46:43.56#ibcon#about to read 6, iclass 12, count 0 2006.173.01:46:43.56#ibcon#read 6, iclass 12, count 0 2006.173.01:46:43.56#ibcon#end of sib2, iclass 12, count 0 2006.173.01:46:43.56#ibcon#*after write, iclass 12, count 0 2006.173.01:46:43.56#ibcon#*before return 0, iclass 12, count 0 2006.173.01:46:43.56#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.01:46:43.56#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.01:46:43.56#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.01:46:43.56#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.01:46:43.56$vck44/vblo=7,734.99 2006.173.01:46:43.56#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.01:46:43.56#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.01:46:43.56#ibcon#ireg 17 cls_cnt 0 2006.173.01:46:43.56#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.01:46:43.56#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.01:46:43.56#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.01:46:43.56#ibcon#enter wrdev, iclass 14, count 0 2006.173.01:46:43.56#ibcon#first serial, iclass 14, count 0 2006.173.01:46:43.56#ibcon#enter sib2, iclass 14, count 0 2006.173.01:46:43.56#ibcon#flushed, iclass 14, count 0 2006.173.01:46:43.56#ibcon#about to write, iclass 14, count 0 2006.173.01:46:43.56#ibcon#wrote, iclass 14, count 0 2006.173.01:46:43.56#ibcon#about to read 3, iclass 14, count 0 2006.173.01:46:43.58#ibcon#read 3, iclass 14, count 0 2006.173.01:46:43.58#ibcon#about to read 4, iclass 14, count 0 2006.173.01:46:43.58#ibcon#read 4, iclass 14, count 0 2006.173.01:46:43.58#ibcon#about to read 5, iclass 14, count 0 2006.173.01:46:43.58#ibcon#read 5, iclass 14, count 0 2006.173.01:46:43.58#ibcon#about to read 6, iclass 14, count 0 2006.173.01:46:43.58#ibcon#read 6, iclass 14, count 0 2006.173.01:46:43.58#ibcon#end of sib2, iclass 14, count 0 2006.173.01:46:43.58#ibcon#*mode == 0, iclass 14, count 0 2006.173.01:46:43.58#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.01:46:43.58#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.01:46:43.58#ibcon#*before write, iclass 14, count 0 2006.173.01:46:43.58#ibcon#enter sib2, iclass 14, count 0 2006.173.01:46:43.58#ibcon#flushed, iclass 14, count 0 2006.173.01:46:43.58#ibcon#about to write, iclass 14, count 0 2006.173.01:46:43.58#ibcon#wrote, iclass 14, count 0 2006.173.01:46:43.58#ibcon#about to read 3, iclass 14, count 0 2006.173.01:46:43.62#ibcon#read 3, iclass 14, count 0 2006.173.01:46:43.62#ibcon#about to read 4, iclass 14, count 0 2006.173.01:46:43.62#ibcon#read 4, iclass 14, count 0 2006.173.01:46:43.62#ibcon#about to read 5, iclass 14, count 0 2006.173.01:46:43.62#ibcon#read 5, iclass 14, count 0 2006.173.01:46:43.62#ibcon#about to read 6, iclass 14, count 0 2006.173.01:46:43.62#ibcon#read 6, iclass 14, count 0 2006.173.01:46:43.62#ibcon#end of sib2, iclass 14, count 0 2006.173.01:46:43.62#ibcon#*after write, iclass 14, count 0 2006.173.01:46:43.62#ibcon#*before return 0, iclass 14, count 0 2006.173.01:46:43.62#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.01:46:43.62#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.01:46:43.62#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.01:46:43.62#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.01:46:43.62$vck44/vb=7,4 2006.173.01:46:43.62#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.01:46:43.62#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.01:46:43.62#ibcon#ireg 11 cls_cnt 2 2006.173.01:46:43.62#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.01:46:43.68#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.01:46:43.68#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.01:46:43.68#ibcon#enter wrdev, iclass 16, count 2 2006.173.01:46:43.68#ibcon#first serial, iclass 16, count 2 2006.173.01:46:43.68#ibcon#enter sib2, iclass 16, count 2 2006.173.01:46:43.68#ibcon#flushed, iclass 16, count 2 2006.173.01:46:43.68#ibcon#about to write, iclass 16, count 2 2006.173.01:46:43.68#ibcon#wrote, iclass 16, count 2 2006.173.01:46:43.68#ibcon#about to read 3, iclass 16, count 2 2006.173.01:46:43.70#ibcon#read 3, iclass 16, count 2 2006.173.01:46:43.70#ibcon#about to read 4, iclass 16, count 2 2006.173.01:46:43.70#ibcon#read 4, iclass 16, count 2 2006.173.01:46:43.70#ibcon#about to read 5, iclass 16, count 2 2006.173.01:46:43.70#ibcon#read 5, iclass 16, count 2 2006.173.01:46:43.70#ibcon#about to read 6, iclass 16, count 2 2006.173.01:46:43.70#ibcon#read 6, iclass 16, count 2 2006.173.01:46:43.70#ibcon#end of sib2, iclass 16, count 2 2006.173.01:46:43.70#ibcon#*mode == 0, iclass 16, count 2 2006.173.01:46:43.70#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.01:46:43.70#ibcon#[27=AT07-04\r\n] 2006.173.01:46:43.70#ibcon#*before write, iclass 16, count 2 2006.173.01:46:43.70#ibcon#enter sib2, iclass 16, count 2 2006.173.01:46:43.70#ibcon#flushed, iclass 16, count 2 2006.173.01:46:43.70#ibcon#about to write, iclass 16, count 2 2006.173.01:46:43.70#ibcon#wrote, iclass 16, count 2 2006.173.01:46:43.70#ibcon#about to read 3, iclass 16, count 2 2006.173.01:46:43.73#ibcon#read 3, iclass 16, count 2 2006.173.01:46:43.73#ibcon#about to read 4, iclass 16, count 2 2006.173.01:46:43.73#ibcon#read 4, iclass 16, count 2 2006.173.01:46:43.73#ibcon#about to read 5, iclass 16, count 2 2006.173.01:46:43.73#ibcon#read 5, iclass 16, count 2 2006.173.01:46:43.73#ibcon#about to read 6, iclass 16, count 2 2006.173.01:46:43.73#ibcon#read 6, iclass 16, count 2 2006.173.01:46:43.73#ibcon#end of sib2, iclass 16, count 2 2006.173.01:46:43.73#ibcon#*after write, iclass 16, count 2 2006.173.01:46:43.73#ibcon#*before return 0, iclass 16, count 2 2006.173.01:46:43.73#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.01:46:43.73#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.01:46:43.73#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.01:46:43.73#ibcon#ireg 7 cls_cnt 0 2006.173.01:46:43.73#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.01:46:43.85#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.01:46:43.85#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.01:46:43.85#ibcon#enter wrdev, iclass 16, count 0 2006.173.01:46:43.85#ibcon#first serial, iclass 16, count 0 2006.173.01:46:43.85#ibcon#enter sib2, iclass 16, count 0 2006.173.01:46:43.85#ibcon#flushed, iclass 16, count 0 2006.173.01:46:43.85#ibcon#about to write, iclass 16, count 0 2006.173.01:46:43.85#ibcon#wrote, iclass 16, count 0 2006.173.01:46:43.85#ibcon#about to read 3, iclass 16, count 0 2006.173.01:46:43.87#ibcon#read 3, iclass 16, count 0 2006.173.01:46:43.87#ibcon#about to read 4, iclass 16, count 0 2006.173.01:46:43.87#ibcon#read 4, iclass 16, count 0 2006.173.01:46:43.87#ibcon#about to read 5, iclass 16, count 0 2006.173.01:46:43.87#ibcon#read 5, iclass 16, count 0 2006.173.01:46:43.87#ibcon#about to read 6, iclass 16, count 0 2006.173.01:46:43.87#ibcon#read 6, iclass 16, count 0 2006.173.01:46:43.87#ibcon#end of sib2, iclass 16, count 0 2006.173.01:46:43.87#ibcon#*mode == 0, iclass 16, count 0 2006.173.01:46:43.87#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.01:46:43.87#ibcon#[27=USB\r\n] 2006.173.01:46:43.87#ibcon#*before write, iclass 16, count 0 2006.173.01:46:43.87#ibcon#enter sib2, iclass 16, count 0 2006.173.01:46:43.87#ibcon#flushed, iclass 16, count 0 2006.173.01:46:43.87#ibcon#about to write, iclass 16, count 0 2006.173.01:46:43.87#ibcon#wrote, iclass 16, count 0 2006.173.01:46:43.87#ibcon#about to read 3, iclass 16, count 0 2006.173.01:46:43.90#ibcon#read 3, iclass 16, count 0 2006.173.01:46:43.90#ibcon#about to read 4, iclass 16, count 0 2006.173.01:46:43.90#ibcon#read 4, iclass 16, count 0 2006.173.01:46:43.90#ibcon#about to read 5, iclass 16, count 0 2006.173.01:46:43.90#ibcon#read 5, iclass 16, count 0 2006.173.01:46:43.90#ibcon#about to read 6, iclass 16, count 0 2006.173.01:46:43.90#ibcon#read 6, iclass 16, count 0 2006.173.01:46:43.90#ibcon#end of sib2, iclass 16, count 0 2006.173.01:46:43.90#ibcon#*after write, iclass 16, count 0 2006.173.01:46:43.90#ibcon#*before return 0, iclass 16, count 0 2006.173.01:46:43.90#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.01:46:43.90#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.01:46:43.90#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.01:46:43.90#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.01:46:43.90$vck44/vblo=8,744.99 2006.173.01:46:43.90#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.01:46:43.90#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.01:46:43.90#ibcon#ireg 17 cls_cnt 0 2006.173.01:46:43.90#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.01:46:43.90#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.01:46:43.90#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.01:46:43.90#ibcon#enter wrdev, iclass 18, count 0 2006.173.01:46:43.90#ibcon#first serial, iclass 18, count 0 2006.173.01:46:43.90#ibcon#enter sib2, iclass 18, count 0 2006.173.01:46:43.90#ibcon#flushed, iclass 18, count 0 2006.173.01:46:43.90#ibcon#about to write, iclass 18, count 0 2006.173.01:46:43.90#ibcon#wrote, iclass 18, count 0 2006.173.01:46:43.90#ibcon#about to read 3, iclass 18, count 0 2006.173.01:46:43.92#ibcon#read 3, iclass 18, count 0 2006.173.01:46:43.92#ibcon#about to read 4, iclass 18, count 0 2006.173.01:46:43.92#ibcon#read 4, iclass 18, count 0 2006.173.01:46:43.92#ibcon#about to read 5, iclass 18, count 0 2006.173.01:46:43.92#ibcon#read 5, iclass 18, count 0 2006.173.01:46:43.92#ibcon#about to read 6, iclass 18, count 0 2006.173.01:46:43.92#ibcon#read 6, iclass 18, count 0 2006.173.01:46:43.92#ibcon#end of sib2, iclass 18, count 0 2006.173.01:46:43.92#ibcon#*mode == 0, iclass 18, count 0 2006.173.01:46:43.92#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.01:46:43.92#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.01:46:43.92#ibcon#*before write, iclass 18, count 0 2006.173.01:46:43.92#ibcon#enter sib2, iclass 18, count 0 2006.173.01:46:43.92#ibcon#flushed, iclass 18, count 0 2006.173.01:46:43.92#ibcon#about to write, iclass 18, count 0 2006.173.01:46:43.92#ibcon#wrote, iclass 18, count 0 2006.173.01:46:43.92#ibcon#about to read 3, iclass 18, count 0 2006.173.01:46:43.96#ibcon#read 3, iclass 18, count 0 2006.173.01:46:43.96#ibcon#about to read 4, iclass 18, count 0 2006.173.01:46:43.96#ibcon#read 4, iclass 18, count 0 2006.173.01:46:43.96#ibcon#about to read 5, iclass 18, count 0 2006.173.01:46:43.96#ibcon#read 5, iclass 18, count 0 2006.173.01:46:43.96#ibcon#about to read 6, iclass 18, count 0 2006.173.01:46:43.96#ibcon#read 6, iclass 18, count 0 2006.173.01:46:43.96#ibcon#end of sib2, iclass 18, count 0 2006.173.01:46:43.96#ibcon#*after write, iclass 18, count 0 2006.173.01:46:43.96#ibcon#*before return 0, iclass 18, count 0 2006.173.01:46:43.96#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.01:46:43.96#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.01:46:43.96#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.01:46:43.96#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.01:46:43.96$vck44/vb=8,4 2006.173.01:46:43.96#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.01:46:43.96#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.01:46:43.96#ibcon#ireg 11 cls_cnt 2 2006.173.01:46:43.96#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.01:46:44.02#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.01:46:44.02#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.01:46:44.02#ibcon#enter wrdev, iclass 20, count 2 2006.173.01:46:44.02#ibcon#first serial, iclass 20, count 2 2006.173.01:46:44.02#ibcon#enter sib2, iclass 20, count 2 2006.173.01:46:44.02#ibcon#flushed, iclass 20, count 2 2006.173.01:46:44.02#ibcon#about to write, iclass 20, count 2 2006.173.01:46:44.02#ibcon#wrote, iclass 20, count 2 2006.173.01:46:44.02#ibcon#about to read 3, iclass 20, count 2 2006.173.01:46:44.04#ibcon#read 3, iclass 20, count 2 2006.173.01:46:44.04#ibcon#about to read 4, iclass 20, count 2 2006.173.01:46:44.04#ibcon#read 4, iclass 20, count 2 2006.173.01:46:44.04#ibcon#about to read 5, iclass 20, count 2 2006.173.01:46:44.04#ibcon#read 5, iclass 20, count 2 2006.173.01:46:44.04#ibcon#about to read 6, iclass 20, count 2 2006.173.01:46:44.04#ibcon#read 6, iclass 20, count 2 2006.173.01:46:44.04#ibcon#end of sib2, iclass 20, count 2 2006.173.01:46:44.04#ibcon#*mode == 0, iclass 20, count 2 2006.173.01:46:44.04#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.01:46:44.04#ibcon#[27=AT08-04\r\n] 2006.173.01:46:44.04#ibcon#*before write, iclass 20, count 2 2006.173.01:46:44.04#ibcon#enter sib2, iclass 20, count 2 2006.173.01:46:44.04#ibcon#flushed, iclass 20, count 2 2006.173.01:46:44.04#ibcon#about to write, iclass 20, count 2 2006.173.01:46:44.04#ibcon#wrote, iclass 20, count 2 2006.173.01:46:44.04#ibcon#about to read 3, iclass 20, count 2 2006.173.01:46:44.07#ibcon#read 3, iclass 20, count 2 2006.173.01:46:44.07#ibcon#about to read 4, iclass 20, count 2 2006.173.01:46:44.07#ibcon#read 4, iclass 20, count 2 2006.173.01:46:44.07#ibcon#about to read 5, iclass 20, count 2 2006.173.01:46:44.07#ibcon#read 5, iclass 20, count 2 2006.173.01:46:44.07#ibcon#about to read 6, iclass 20, count 2 2006.173.01:46:44.07#ibcon#read 6, iclass 20, count 2 2006.173.01:46:44.07#ibcon#end of sib2, iclass 20, count 2 2006.173.01:46:44.07#ibcon#*after write, iclass 20, count 2 2006.173.01:46:44.07#ibcon#*before return 0, iclass 20, count 2 2006.173.01:46:44.07#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.01:46:44.07#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.01:46:44.07#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.01:46:44.07#ibcon#ireg 7 cls_cnt 0 2006.173.01:46:44.07#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.01:46:44.19#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.01:46:44.19#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.01:46:44.19#ibcon#enter wrdev, iclass 20, count 0 2006.173.01:46:44.19#ibcon#first serial, iclass 20, count 0 2006.173.01:46:44.19#ibcon#enter sib2, iclass 20, count 0 2006.173.01:46:44.19#ibcon#flushed, iclass 20, count 0 2006.173.01:46:44.19#ibcon#about to write, iclass 20, count 0 2006.173.01:46:44.19#ibcon#wrote, iclass 20, count 0 2006.173.01:46:44.19#ibcon#about to read 3, iclass 20, count 0 2006.173.01:46:44.21#ibcon#read 3, iclass 20, count 0 2006.173.01:46:44.21#ibcon#about to read 4, iclass 20, count 0 2006.173.01:46:44.21#ibcon#read 4, iclass 20, count 0 2006.173.01:46:44.21#ibcon#about to read 5, iclass 20, count 0 2006.173.01:46:44.21#ibcon#read 5, iclass 20, count 0 2006.173.01:46:44.21#ibcon#about to read 6, iclass 20, count 0 2006.173.01:46:44.21#ibcon#read 6, iclass 20, count 0 2006.173.01:46:44.21#ibcon#end of sib2, iclass 20, count 0 2006.173.01:46:44.21#ibcon#*mode == 0, iclass 20, count 0 2006.173.01:46:44.21#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.01:46:44.21#ibcon#[27=USB\r\n] 2006.173.01:46:44.21#ibcon#*before write, iclass 20, count 0 2006.173.01:46:44.21#ibcon#enter sib2, iclass 20, count 0 2006.173.01:46:44.21#ibcon#flushed, iclass 20, count 0 2006.173.01:46:44.21#ibcon#about to write, iclass 20, count 0 2006.173.01:46:44.21#ibcon#wrote, iclass 20, count 0 2006.173.01:46:44.21#ibcon#about to read 3, iclass 20, count 0 2006.173.01:46:44.24#ibcon#read 3, iclass 20, count 0 2006.173.01:46:44.24#ibcon#about to read 4, iclass 20, count 0 2006.173.01:46:44.24#ibcon#read 4, iclass 20, count 0 2006.173.01:46:44.24#ibcon#about to read 5, iclass 20, count 0 2006.173.01:46:44.24#ibcon#read 5, iclass 20, count 0 2006.173.01:46:44.24#ibcon#about to read 6, iclass 20, count 0 2006.173.01:46:44.24#ibcon#read 6, iclass 20, count 0 2006.173.01:46:44.24#ibcon#end of sib2, iclass 20, count 0 2006.173.01:46:44.24#ibcon#*after write, iclass 20, count 0 2006.173.01:46:44.24#ibcon#*before return 0, iclass 20, count 0 2006.173.01:46:44.24#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.01:46:44.24#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.01:46:44.24#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.01:46:44.24#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.01:46:44.24$vck44/vabw=wide 2006.173.01:46:44.24#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.01:46:44.24#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.01:46:44.24#ibcon#ireg 8 cls_cnt 0 2006.173.01:46:44.24#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.01:46:44.24#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.01:46:44.24#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.01:46:44.24#ibcon#enter wrdev, iclass 22, count 0 2006.173.01:46:44.24#ibcon#first serial, iclass 22, count 0 2006.173.01:46:44.24#ibcon#enter sib2, iclass 22, count 0 2006.173.01:46:44.24#ibcon#flushed, iclass 22, count 0 2006.173.01:46:44.24#ibcon#about to write, iclass 22, count 0 2006.173.01:46:44.24#ibcon#wrote, iclass 22, count 0 2006.173.01:46:44.24#ibcon#about to read 3, iclass 22, count 0 2006.173.01:46:44.26#ibcon#read 3, iclass 22, count 0 2006.173.01:46:44.26#ibcon#about to read 4, iclass 22, count 0 2006.173.01:46:44.26#ibcon#read 4, iclass 22, count 0 2006.173.01:46:44.26#ibcon#about to read 5, iclass 22, count 0 2006.173.01:46:44.26#ibcon#read 5, iclass 22, count 0 2006.173.01:46:44.26#ibcon#about to read 6, iclass 22, count 0 2006.173.01:46:44.26#ibcon#read 6, iclass 22, count 0 2006.173.01:46:44.26#ibcon#end of sib2, iclass 22, count 0 2006.173.01:46:44.26#ibcon#*mode == 0, iclass 22, count 0 2006.173.01:46:44.26#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.01:46:44.26#ibcon#[25=BW32\r\n] 2006.173.01:46:44.26#ibcon#*before write, iclass 22, count 0 2006.173.01:46:44.26#ibcon#enter sib2, iclass 22, count 0 2006.173.01:46:44.26#ibcon#flushed, iclass 22, count 0 2006.173.01:46:44.26#ibcon#about to write, iclass 22, count 0 2006.173.01:46:44.26#ibcon#wrote, iclass 22, count 0 2006.173.01:46:44.26#ibcon#about to read 3, iclass 22, count 0 2006.173.01:46:44.29#ibcon#read 3, iclass 22, count 0 2006.173.01:46:44.29#ibcon#about to read 4, iclass 22, count 0 2006.173.01:46:44.29#ibcon#read 4, iclass 22, count 0 2006.173.01:46:44.29#ibcon#about to read 5, iclass 22, count 0 2006.173.01:46:44.29#ibcon#read 5, iclass 22, count 0 2006.173.01:46:44.29#ibcon#about to read 6, iclass 22, count 0 2006.173.01:46:44.29#ibcon#read 6, iclass 22, count 0 2006.173.01:46:44.29#ibcon#end of sib2, iclass 22, count 0 2006.173.01:46:44.29#ibcon#*after write, iclass 22, count 0 2006.173.01:46:44.29#ibcon#*before return 0, iclass 22, count 0 2006.173.01:46:44.29#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.01:46:44.29#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.01:46:44.29#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.01:46:44.29#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.01:46:44.29$vck44/vbbw=wide 2006.173.01:46:44.29#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.01:46:44.29#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.01:46:44.29#ibcon#ireg 8 cls_cnt 0 2006.173.01:46:44.29#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.01:46:44.36#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.01:46:44.36#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.01:46:44.36#ibcon#enter wrdev, iclass 24, count 0 2006.173.01:46:44.36#ibcon#first serial, iclass 24, count 0 2006.173.01:46:44.36#ibcon#enter sib2, iclass 24, count 0 2006.173.01:46:44.36#ibcon#flushed, iclass 24, count 0 2006.173.01:46:44.36#ibcon#about to write, iclass 24, count 0 2006.173.01:46:44.36#ibcon#wrote, iclass 24, count 0 2006.173.01:46:44.36#ibcon#about to read 3, iclass 24, count 0 2006.173.01:46:44.38#ibcon#read 3, iclass 24, count 0 2006.173.01:46:44.38#ibcon#about to read 4, iclass 24, count 0 2006.173.01:46:44.38#ibcon#read 4, iclass 24, count 0 2006.173.01:46:44.38#ibcon#about to read 5, iclass 24, count 0 2006.173.01:46:44.38#ibcon#read 5, iclass 24, count 0 2006.173.01:46:44.38#ibcon#about to read 6, iclass 24, count 0 2006.173.01:46:44.38#ibcon#read 6, iclass 24, count 0 2006.173.01:46:44.38#ibcon#end of sib2, iclass 24, count 0 2006.173.01:46:44.38#ibcon#*mode == 0, iclass 24, count 0 2006.173.01:46:44.38#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.01:46:44.38#ibcon#[27=BW32\r\n] 2006.173.01:46:44.38#ibcon#*before write, iclass 24, count 0 2006.173.01:46:44.38#ibcon#enter sib2, iclass 24, count 0 2006.173.01:46:44.38#ibcon#flushed, iclass 24, count 0 2006.173.01:46:44.38#ibcon#about to write, iclass 24, count 0 2006.173.01:46:44.38#ibcon#wrote, iclass 24, count 0 2006.173.01:46:44.38#ibcon#about to read 3, iclass 24, count 0 2006.173.01:46:44.41#ibcon#read 3, iclass 24, count 0 2006.173.01:46:44.41#ibcon#about to read 4, iclass 24, count 0 2006.173.01:46:44.41#ibcon#read 4, iclass 24, count 0 2006.173.01:46:44.41#ibcon#about to read 5, iclass 24, count 0 2006.173.01:46:44.41#ibcon#read 5, iclass 24, count 0 2006.173.01:46:44.41#ibcon#about to read 6, iclass 24, count 0 2006.173.01:46:44.41#ibcon#read 6, iclass 24, count 0 2006.173.01:46:44.41#ibcon#end of sib2, iclass 24, count 0 2006.173.01:46:44.41#ibcon#*after write, iclass 24, count 0 2006.173.01:46:44.41#ibcon#*before return 0, iclass 24, count 0 2006.173.01:46:44.41#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.01:46:44.41#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.01:46:44.41#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.01:46:44.41#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.01:46:44.41$setupk4/ifdk4 2006.173.01:46:44.41$ifdk4/lo= 2006.173.01:46:44.41$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.01:46:44.41$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.01:46:44.41$ifdk4/patch= 2006.173.01:46:44.41$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.01:46:44.41$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.01:46:44.41$setupk4/!*+20s 2006.173.01:46:52.45#abcon#<5=/14 1.5 3.8 22.40 841006.9\r\n> 2006.173.01:46:52.47#abcon#{5=INTERFACE CLEAR} 2006.173.01:46:52.55#abcon#[5=S1D000X0/0*\r\n] 2006.173.01:46:58.93$setupk4/"tpicd 2006.173.01:46:58.93$setupk4/echo=off 2006.173.01:46:58.93$setupk4/xlog=off 2006.173.01:46:58.93:!2006.173.01:59:50 2006.173.01:47:26.17;cable 2006.173.01:47:26.36/cable/+6.5139E-03 2006.173.01:48:08.17;cablelong 2006.173.01:48:08.25/cablelong/+7.0629E-03 2006.173.01:48:13.28;cablediff 2006.173.01:48:13.28/cablediff/549.0e-6,+ 2006.173.01:48:47.53;cable 2006.173.01:48:47.60/cable/+6.5143E-03 2006.173.01:49:04.86;wx 2006.173.01:49:04.86/wx/22.42,1006.9,85 2006.173.01:49:29.27;"Sky is cloudy. 2006.173.01:49:32.38;xfe 2006.173.01:49:32.47/xfe/off,on,15.2 2006.173.01:49:36.35;clockoff 2006.173.01:49:36.35&clockoff/"gps-fmout=1p 2006.173.01:49:36.35&clockoff/fmout-gps=1p 2006.173.01:49:37.08/fmout-gps/S +3.93E-07 2006.173.01:59:50.00:preob 2006.173.01:59:50.00&preob/onsource 2006.173.01:59:50.14/onsource/TRACKING 2006.173.01:59:50.14:!2006.173.02:00:00 2006.173.02:00:00.00:"tape 2006.173.02:00:00.00:"st=record 2006.173.02:00:00.00:data_valid=on 2006.173.02:00:00.00:midob 2006.173.02:00:00.00&midob/onsource 2006.173.02:00:00.00&midob/wx 2006.173.02:00:00.00&midob/cable 2006.173.02:00:00.00&midob/va 2006.173.02:00:00.00&midob/valo 2006.173.02:00:00.00&midob/vb 2006.173.02:00:00.00&midob/vblo 2006.173.02:00:00.00&midob/vabw 2006.173.02:00:00.00&midob/vbbw 2006.173.02:00:00.00&midob/"form 2006.173.02:00:00.00&midob/xfe 2006.173.02:00:00.00&midob/ifatt 2006.173.02:00:00.00&midob/clockoff 2006.173.02:00:00.00&midob/sy=logmail 2006.173.02:00:00.00&midob/"sy=run setcl adapt & 2006.173.02:00:00.13/onsource/TRACKING 2006.173.02:00:00.13/wx/22.62,1006.8,82 2006.173.02:00:00.22/cable/+6.5096E-03 2006.173.02:00:01.31/va/01,07,usb,yes,36,39 2006.173.02:00:01.31/va/02,06,usb,yes,36,37 2006.173.02:00:01.31/va/03,05,usb,yes,45,47 2006.173.02:00:01.31/va/04,06,usb,yes,36,38 2006.173.02:00:01.31/va/05,04,usb,yes,29,29 2006.173.02:00:01.31/va/06,03,usb,yes,40,40 2006.173.02:00:01.31/va/07,04,usb,yes,32,34 2006.173.02:00:01.31/va/08,04,usb,yes,28,33 2006.173.02:00:01.54/valo/01,524.99,yes,locked 2006.173.02:00:01.54/valo/02,534.99,yes,locked 2006.173.02:00:01.54/valo/03,564.99,yes,locked 2006.173.02:00:01.54/valo/04,624.99,yes,locked 2006.173.02:00:01.54/valo/05,734.99,yes,locked 2006.173.02:00:01.54/valo/06,814.99,yes,locked 2006.173.02:00:01.54/valo/07,864.99,yes,locked 2006.173.02:00:01.54/valo/08,884.99,yes,locked 2006.173.02:00:02.63/vb/01,04,usb,yes,29,27 2006.173.02:00:02.63/vb/02,04,usb,yes,31,31 2006.173.02:00:02.63/vb/03,04,usb,yes,28,31 2006.173.02:00:02.63/vb/04,04,usb,yes,32,31 2006.173.02:00:02.63/vb/05,04,usb,yes,25,28 2006.173.02:00:02.63/vb/06,04,usb,yes,30,26 2006.173.02:00:02.63/vb/07,04,usb,yes,29,29 2006.173.02:00:02.63/vb/08,04,usb,yes,27,30 2006.173.02:00:02.86/vblo/01,629.99,yes,locked 2006.173.02:00:02.86/vblo/02,634.99,yes,locked 2006.173.02:00:02.86/vblo/03,649.99,yes,locked 2006.173.02:00:02.86/vblo/04,679.99,yes,locked 2006.173.02:00:02.86/vblo/05,709.99,yes,locked 2006.173.02:00:02.86/vblo/06,719.99,yes,locked 2006.173.02:00:02.86/vblo/07,734.99,yes,locked 2006.173.02:00:02.86/vblo/08,744.99,yes,locked 2006.173.02:00:03.01/vabw/8 2006.173.02:00:03.16/vbbw/8 2006.173.02:00:03.25/xfe/off,on,15.0 2006.173.02:00:03.64/ifatt/23,28,28,28 2006.173.02:00:04.08/fmout-gps/S +3.94E-07 2006.173.02:00:04.16:!2006.173.02:00:40 2006.173.02:00:40.00:data_valid=off 2006.173.02:00:40.00:"et 2006.173.02:00:40.00:!+3s 2006.173.02:00:43.02:"tape 2006.173.02:00:43.02:postob 2006.173.02:00:43.02&postob/cable 2006.173.02:00:43.03&postob/wx 2006.173.02:00:43.03&postob/clockoff 2006.173.02:00:43.16/cable/+6.5123E-03 2006.173.02:00:43.16/wx/22.62,1006.7,83 2006.173.02:00:43.22/fmout-gps/S +3.94E-07 2006.173.02:00:43.22:scan_name=173-0201,jd0606,40 2006.173.02:00:43.22:source=0537-441,053850.36,-440508.9,2000.0,cw 2006.173.02:00:45.13#flagr#flagr/antenna,new-source 2006.173.02:00:45.13:checkk5 2006.173.02:00:45.13&checkk5/chk_autoobs=1 2006.173.02:00:45.14&checkk5/chk_autoobs=2 2006.173.02:00:45.14&checkk5/chk_autoobs=3 2006.173.02:00:45.14&checkk5/chk_autoobs=4 2006.173.02:00:45.15&checkk5/chk_obsdata=1 2006.173.02:00:45.15&checkk5/chk_obsdata=2 2006.173.02:00:45.15&checkk5/chk_obsdata=3 2006.173.02:00:45.16&checkk5/chk_obsdata=4 2006.173.02:00:45.16&checkk5/k5log=1 2006.173.02:00:45.16&checkk5/k5log=2 2006.173.02:00:45.17&checkk5/k5log=3 2006.173.02:00:45.17&checkk5/k5log=4 2006.173.02:00:45.17&checkk5/obsinfo 2006.173.02:00:45.60/chk_autoobs//k5ts1/ autoobs is running! 2006.173.02:00:46.05/chk_autoobs//k5ts2/ autoobs is running! 2006.173.02:00:49.51/chk_autoobs//k5ts3/ autoobs is running! 2006.173.02:00:50.16/chk_autoobs//k5ts4/ autoobs is running! 2006.173.02:00:50.61/chk_obsdata//k5ts1/T1730200??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.02:00:50.99/chk_obsdata//k5ts2/T1730200??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.02:00:51.42/chk_obsdata//k5ts3/T1730200??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.02:00:51.88/chk_obsdata//k5ts4/T1730200??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.02:00:52.98/k5log//k5ts1_log_newline 2006.173.02:00:53.93/k5log//k5ts2_log_newline 2006.173.02:00:54.74/k5log//k5ts3_log_newline 2006.173.02:00:55.56/k5log//k5ts4_log_newline 2006.173.02:00:55.63/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.02:00:55.63:setupk4=1 2006.173.02:00:55.63$setupk4/echo=on 2006.173.02:00:55.63$setupk4/pcalon 2006.173.02:00:55.63$pcalon/"no phase cal control is implemented here 2006.173.02:00:55.63$setupk4/"tpicd=stop 2006.173.02:00:55.63$setupk4/"rec=synch_on 2006.173.02:00:55.63$setupk4/"rec_mode=128 2006.173.02:00:55.63$setupk4/!* 2006.173.02:00:55.63$setupk4/recpk4 2006.173.02:00:55.63$recpk4/recpatch= 2006.173.02:00:55.64$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.02:00:55.64$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.02:00:55.64$setupk4/vck44 2006.173.02:00:55.64$vck44/valo=1,524.99 2006.173.02:00:55.64#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.02:00:55.64#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.02:00:55.64#ibcon#ireg 17 cls_cnt 0 2006.173.02:00:55.64#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.02:00:55.64#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.02:00:55.64#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.02:00:55.64#ibcon#enter wrdev, iclass 21, count 0 2006.173.02:00:55.64#ibcon#first serial, iclass 21, count 0 2006.173.02:00:55.64#ibcon#enter sib2, iclass 21, count 0 2006.173.02:00:55.64#ibcon#flushed, iclass 21, count 0 2006.173.02:00:55.64#ibcon#about to write, iclass 21, count 0 2006.173.02:00:55.64#ibcon#wrote, iclass 21, count 0 2006.173.02:00:55.64#ibcon#about to read 3, iclass 21, count 0 2006.173.02:00:55.68#ibcon#read 3, iclass 21, count 0 2006.173.02:00:55.68#ibcon#about to read 4, iclass 21, count 0 2006.173.02:00:55.68#ibcon#read 4, iclass 21, count 0 2006.173.02:00:55.68#ibcon#about to read 5, iclass 21, count 0 2006.173.02:00:55.68#ibcon#read 5, iclass 21, count 0 2006.173.02:00:55.68#ibcon#about to read 6, iclass 21, count 0 2006.173.02:00:55.68#ibcon#read 6, iclass 21, count 0 2006.173.02:00:55.68#ibcon#end of sib2, iclass 21, count 0 2006.173.02:00:55.68#ibcon#*mode == 0, iclass 21, count 0 2006.173.02:00:55.68#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.02:00:55.68#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.02:00:55.68#ibcon#*before write, iclass 21, count 0 2006.173.02:00:55.68#ibcon#enter sib2, iclass 21, count 0 2006.173.02:00:55.68#ibcon#flushed, iclass 21, count 0 2006.173.02:00:55.68#ibcon#about to write, iclass 21, count 0 2006.173.02:00:55.68#ibcon#wrote, iclass 21, count 0 2006.173.02:00:55.68#ibcon#about to read 3, iclass 21, count 0 2006.173.02:00:55.73#ibcon#read 3, iclass 21, count 0 2006.173.02:00:55.73#ibcon#about to read 4, iclass 21, count 0 2006.173.02:00:55.73#ibcon#read 4, iclass 21, count 0 2006.173.02:00:55.73#ibcon#about to read 5, iclass 21, count 0 2006.173.02:00:55.73#ibcon#read 5, iclass 21, count 0 2006.173.02:00:55.73#ibcon#about to read 6, iclass 21, count 0 2006.173.02:00:55.73#ibcon#read 6, iclass 21, count 0 2006.173.02:00:55.73#ibcon#end of sib2, iclass 21, count 0 2006.173.02:00:55.73#ibcon#*after write, iclass 21, count 0 2006.173.02:00:55.73#ibcon#*before return 0, iclass 21, count 0 2006.173.02:00:55.73#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.02:00:55.73#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.02:00:55.73#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.02:00:55.73#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.02:00:55.73$vck44/va=1,7 2006.173.02:00:55.73#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.02:00:55.73#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.02:00:55.73#ibcon#ireg 11 cls_cnt 2 2006.173.02:00:55.73#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.02:00:55.73#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.02:00:55.73#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.02:00:55.73#ibcon#enter wrdev, iclass 23, count 2 2006.173.02:00:55.73#ibcon#first serial, iclass 23, count 2 2006.173.02:00:55.73#ibcon#enter sib2, iclass 23, count 2 2006.173.02:00:55.73#ibcon#flushed, iclass 23, count 2 2006.173.02:00:55.73#ibcon#about to write, iclass 23, count 2 2006.173.02:00:55.73#ibcon#wrote, iclass 23, count 2 2006.173.02:00:55.73#ibcon#about to read 3, iclass 23, count 2 2006.173.02:00:55.78#ibcon#read 3, iclass 23, count 2 2006.173.02:00:55.78#ibcon#about to read 4, iclass 23, count 2 2006.173.02:00:55.78#ibcon#read 4, iclass 23, count 2 2006.173.02:00:55.78#ibcon#about to read 5, iclass 23, count 2 2006.173.02:00:55.78#ibcon#read 5, iclass 23, count 2 2006.173.02:00:55.78#ibcon#about to read 6, iclass 23, count 2 2006.173.02:00:55.78#ibcon#read 6, iclass 23, count 2 2006.173.02:00:55.78#ibcon#end of sib2, iclass 23, count 2 2006.173.02:00:55.78#ibcon#*mode == 0, iclass 23, count 2 2006.173.02:00:55.78#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.02:00:55.78#ibcon#[25=AT01-07\r\n] 2006.173.02:00:55.78#ibcon#*before write, iclass 23, count 2 2006.173.02:00:55.78#ibcon#enter sib2, iclass 23, count 2 2006.173.02:00:55.78#ibcon#flushed, iclass 23, count 2 2006.173.02:00:55.78#ibcon#about to write, iclass 23, count 2 2006.173.02:00:55.78#ibcon#wrote, iclass 23, count 2 2006.173.02:00:55.78#ibcon#about to read 3, iclass 23, count 2 2006.173.02:00:55.82#ibcon#read 3, iclass 23, count 2 2006.173.02:00:55.82#ibcon#about to read 4, iclass 23, count 2 2006.173.02:00:55.82#ibcon#read 4, iclass 23, count 2 2006.173.02:00:55.82#ibcon#about to read 5, iclass 23, count 2 2006.173.02:00:55.82#ibcon#read 5, iclass 23, count 2 2006.173.02:00:55.82#ibcon#about to read 6, iclass 23, count 2 2006.173.02:00:55.82#ibcon#read 6, iclass 23, count 2 2006.173.02:00:55.82#ibcon#end of sib2, iclass 23, count 2 2006.173.02:00:55.82#ibcon#*after write, iclass 23, count 2 2006.173.02:00:55.82#ibcon#*before return 0, iclass 23, count 2 2006.173.02:00:55.82#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.02:00:55.82#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.02:00:55.82#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.02:00:55.82#ibcon#ireg 7 cls_cnt 0 2006.173.02:00:55.82#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.02:00:55.94#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.02:00:55.94#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.02:00:55.94#ibcon#enter wrdev, iclass 23, count 0 2006.173.02:00:55.94#ibcon#first serial, iclass 23, count 0 2006.173.02:00:55.94#ibcon#enter sib2, iclass 23, count 0 2006.173.02:00:55.94#ibcon#flushed, iclass 23, count 0 2006.173.02:00:55.94#ibcon#about to write, iclass 23, count 0 2006.173.02:00:55.94#ibcon#wrote, iclass 23, count 0 2006.173.02:00:55.94#ibcon#about to read 3, iclass 23, count 0 2006.173.02:00:55.96#ibcon#read 3, iclass 23, count 0 2006.173.02:00:55.96#ibcon#about to read 4, iclass 23, count 0 2006.173.02:00:55.96#ibcon#read 4, iclass 23, count 0 2006.173.02:00:55.96#ibcon#about to read 5, iclass 23, count 0 2006.173.02:00:55.96#ibcon#read 5, iclass 23, count 0 2006.173.02:00:55.96#ibcon#about to read 6, iclass 23, count 0 2006.173.02:00:55.96#ibcon#read 6, iclass 23, count 0 2006.173.02:00:55.96#ibcon#end of sib2, iclass 23, count 0 2006.173.02:00:55.96#ibcon#*mode == 0, iclass 23, count 0 2006.173.02:00:55.96#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.02:00:55.96#ibcon#[25=USB\r\n] 2006.173.02:00:55.96#ibcon#*before write, iclass 23, count 0 2006.173.02:00:55.96#ibcon#enter sib2, iclass 23, count 0 2006.173.02:00:55.96#ibcon#flushed, iclass 23, count 0 2006.173.02:00:55.96#ibcon#about to write, iclass 23, count 0 2006.173.02:00:55.96#ibcon#wrote, iclass 23, count 0 2006.173.02:00:55.96#ibcon#about to read 3, iclass 23, count 0 2006.173.02:00:55.99#ibcon#read 3, iclass 23, count 0 2006.173.02:00:55.99#ibcon#about to read 4, iclass 23, count 0 2006.173.02:00:55.99#ibcon#read 4, iclass 23, count 0 2006.173.02:00:55.99#ibcon#about to read 5, iclass 23, count 0 2006.173.02:00:55.99#ibcon#read 5, iclass 23, count 0 2006.173.02:00:55.99#ibcon#about to read 6, iclass 23, count 0 2006.173.02:00:55.99#ibcon#read 6, iclass 23, count 0 2006.173.02:00:55.99#ibcon#end of sib2, iclass 23, count 0 2006.173.02:00:55.99#ibcon#*after write, iclass 23, count 0 2006.173.02:00:55.99#ibcon#*before return 0, iclass 23, count 0 2006.173.02:00:55.99#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.02:00:55.99#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.02:00:55.99#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.02:00:55.99#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.02:00:55.99$vck44/valo=2,534.99 2006.173.02:00:55.99#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.02:00:55.99#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.02:00:55.99#ibcon#ireg 17 cls_cnt 0 2006.173.02:00:55.99#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.02:00:55.99#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.02:00:55.99#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.02:00:55.99#ibcon#enter wrdev, iclass 25, count 0 2006.173.02:00:55.99#ibcon#first serial, iclass 25, count 0 2006.173.02:00:55.99#ibcon#enter sib2, iclass 25, count 0 2006.173.02:00:55.99#ibcon#flushed, iclass 25, count 0 2006.173.02:00:55.99#ibcon#about to write, iclass 25, count 0 2006.173.02:00:55.99#ibcon#wrote, iclass 25, count 0 2006.173.02:00:55.99#ibcon#about to read 3, iclass 25, count 0 2006.173.02:00:56.01#ibcon#read 3, iclass 25, count 0 2006.173.02:00:56.01#ibcon#about to read 4, iclass 25, count 0 2006.173.02:00:56.01#ibcon#read 4, iclass 25, count 0 2006.173.02:00:56.01#ibcon#about to read 5, iclass 25, count 0 2006.173.02:00:56.01#ibcon#read 5, iclass 25, count 0 2006.173.02:00:56.01#ibcon#about to read 6, iclass 25, count 0 2006.173.02:00:56.01#ibcon#read 6, iclass 25, count 0 2006.173.02:00:56.01#ibcon#end of sib2, iclass 25, count 0 2006.173.02:00:56.01#ibcon#*mode == 0, iclass 25, count 0 2006.173.02:00:56.01#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.02:00:56.01#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.02:00:56.01#ibcon#*before write, iclass 25, count 0 2006.173.02:00:56.01#ibcon#enter sib2, iclass 25, count 0 2006.173.02:00:56.01#ibcon#flushed, iclass 25, count 0 2006.173.02:00:56.01#ibcon#about to write, iclass 25, count 0 2006.173.02:00:56.01#ibcon#wrote, iclass 25, count 0 2006.173.02:00:56.01#ibcon#about to read 3, iclass 25, count 0 2006.173.02:00:56.05#ibcon#read 3, iclass 25, count 0 2006.173.02:00:56.05#ibcon#about to read 4, iclass 25, count 0 2006.173.02:00:56.05#ibcon#read 4, iclass 25, count 0 2006.173.02:00:56.05#ibcon#about to read 5, iclass 25, count 0 2006.173.02:00:56.05#ibcon#read 5, iclass 25, count 0 2006.173.02:00:56.05#ibcon#about to read 6, iclass 25, count 0 2006.173.02:00:56.05#ibcon#read 6, iclass 25, count 0 2006.173.02:00:56.05#ibcon#end of sib2, iclass 25, count 0 2006.173.02:00:56.05#ibcon#*after write, iclass 25, count 0 2006.173.02:00:56.05#ibcon#*before return 0, iclass 25, count 0 2006.173.02:00:56.05#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.02:00:56.05#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.02:00:56.05#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.02:00:56.05#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.02:00:56.05$vck44/va=2,6 2006.173.02:00:56.05#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.02:00:56.05#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.02:00:56.05#ibcon#ireg 11 cls_cnt 2 2006.173.02:00:56.05#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.02:00:56.11#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.02:00:56.11#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.02:00:56.11#ibcon#enter wrdev, iclass 27, count 2 2006.173.02:00:56.11#ibcon#first serial, iclass 27, count 2 2006.173.02:00:56.11#ibcon#enter sib2, iclass 27, count 2 2006.173.02:00:56.11#ibcon#flushed, iclass 27, count 2 2006.173.02:00:56.11#ibcon#about to write, iclass 27, count 2 2006.173.02:00:56.11#ibcon#wrote, iclass 27, count 2 2006.173.02:00:56.11#ibcon#about to read 3, iclass 27, count 2 2006.173.02:00:56.13#ibcon#read 3, iclass 27, count 2 2006.173.02:00:56.13#ibcon#about to read 4, iclass 27, count 2 2006.173.02:00:56.13#ibcon#read 4, iclass 27, count 2 2006.173.02:00:56.13#ibcon#about to read 5, iclass 27, count 2 2006.173.02:00:56.13#ibcon#read 5, iclass 27, count 2 2006.173.02:00:56.13#ibcon#about to read 6, iclass 27, count 2 2006.173.02:00:56.13#ibcon#read 6, iclass 27, count 2 2006.173.02:00:56.13#ibcon#end of sib2, iclass 27, count 2 2006.173.02:00:56.13#ibcon#*mode == 0, iclass 27, count 2 2006.173.02:00:56.13#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.02:00:56.13#ibcon#[25=AT02-06\r\n] 2006.173.02:00:56.13#ibcon#*before write, iclass 27, count 2 2006.173.02:00:56.13#ibcon#enter sib2, iclass 27, count 2 2006.173.02:00:56.13#ibcon#flushed, iclass 27, count 2 2006.173.02:00:56.13#ibcon#about to write, iclass 27, count 2 2006.173.02:00:56.13#ibcon#wrote, iclass 27, count 2 2006.173.02:00:56.13#ibcon#about to read 3, iclass 27, count 2 2006.173.02:00:56.16#ibcon#read 3, iclass 27, count 2 2006.173.02:00:56.16#ibcon#about to read 4, iclass 27, count 2 2006.173.02:00:56.16#ibcon#read 4, iclass 27, count 2 2006.173.02:00:56.16#ibcon#about to read 5, iclass 27, count 2 2006.173.02:00:56.16#ibcon#read 5, iclass 27, count 2 2006.173.02:00:56.16#ibcon#about to read 6, iclass 27, count 2 2006.173.02:00:56.16#ibcon#read 6, iclass 27, count 2 2006.173.02:00:56.16#ibcon#end of sib2, iclass 27, count 2 2006.173.02:00:56.16#ibcon#*after write, iclass 27, count 2 2006.173.02:00:56.16#ibcon#*before return 0, iclass 27, count 2 2006.173.02:00:56.16#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.02:00:56.16#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.02:00:56.16#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.02:00:56.16#ibcon#ireg 7 cls_cnt 0 2006.173.02:00:56.16#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.02:00:56.28#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.02:00:56.28#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.02:00:56.28#ibcon#enter wrdev, iclass 27, count 0 2006.173.02:00:56.28#ibcon#first serial, iclass 27, count 0 2006.173.02:00:56.28#ibcon#enter sib2, iclass 27, count 0 2006.173.02:00:56.28#ibcon#flushed, iclass 27, count 0 2006.173.02:00:56.28#ibcon#about to write, iclass 27, count 0 2006.173.02:00:56.28#ibcon#wrote, iclass 27, count 0 2006.173.02:00:56.28#ibcon#about to read 3, iclass 27, count 0 2006.173.02:00:56.30#ibcon#read 3, iclass 27, count 0 2006.173.02:00:56.30#ibcon#about to read 4, iclass 27, count 0 2006.173.02:00:56.30#ibcon#read 4, iclass 27, count 0 2006.173.02:00:56.30#ibcon#about to read 5, iclass 27, count 0 2006.173.02:00:56.30#ibcon#read 5, iclass 27, count 0 2006.173.02:00:56.30#ibcon#about to read 6, iclass 27, count 0 2006.173.02:00:56.30#ibcon#read 6, iclass 27, count 0 2006.173.02:00:56.30#ibcon#end of sib2, iclass 27, count 0 2006.173.02:00:56.30#ibcon#*mode == 0, iclass 27, count 0 2006.173.02:00:56.30#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.02:00:56.30#ibcon#[25=USB\r\n] 2006.173.02:00:56.30#ibcon#*before write, iclass 27, count 0 2006.173.02:00:56.30#ibcon#enter sib2, iclass 27, count 0 2006.173.02:00:56.30#ibcon#flushed, iclass 27, count 0 2006.173.02:00:56.30#ibcon#about to write, iclass 27, count 0 2006.173.02:00:56.30#ibcon#wrote, iclass 27, count 0 2006.173.02:00:56.30#ibcon#about to read 3, iclass 27, count 0 2006.173.02:00:56.33#ibcon#read 3, iclass 27, count 0 2006.173.02:00:56.33#ibcon#about to read 4, iclass 27, count 0 2006.173.02:00:56.33#ibcon#read 4, iclass 27, count 0 2006.173.02:00:56.33#ibcon#about to read 5, iclass 27, count 0 2006.173.02:00:56.33#ibcon#read 5, iclass 27, count 0 2006.173.02:00:56.33#ibcon#about to read 6, iclass 27, count 0 2006.173.02:00:56.33#ibcon#read 6, iclass 27, count 0 2006.173.02:00:56.33#ibcon#end of sib2, iclass 27, count 0 2006.173.02:00:56.33#ibcon#*after write, iclass 27, count 0 2006.173.02:00:56.33#ibcon#*before return 0, iclass 27, count 0 2006.173.02:00:56.33#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.02:00:56.33#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.02:00:56.33#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.02:00:56.33#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.02:00:56.33$vck44/valo=3,564.99 2006.173.02:00:56.33#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.02:00:56.33#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.02:00:56.33#ibcon#ireg 17 cls_cnt 0 2006.173.02:00:56.33#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.02:00:56.33#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.02:00:56.33#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.02:00:56.33#ibcon#enter wrdev, iclass 29, count 0 2006.173.02:00:56.33#ibcon#first serial, iclass 29, count 0 2006.173.02:00:56.33#ibcon#enter sib2, iclass 29, count 0 2006.173.02:00:56.33#ibcon#flushed, iclass 29, count 0 2006.173.02:00:56.33#ibcon#about to write, iclass 29, count 0 2006.173.02:00:56.33#ibcon#wrote, iclass 29, count 0 2006.173.02:00:56.33#ibcon#about to read 3, iclass 29, count 0 2006.173.02:00:56.35#ibcon#read 3, iclass 29, count 0 2006.173.02:00:56.35#ibcon#about to read 4, iclass 29, count 0 2006.173.02:00:56.35#ibcon#read 4, iclass 29, count 0 2006.173.02:00:56.35#ibcon#about to read 5, iclass 29, count 0 2006.173.02:00:56.35#ibcon#read 5, iclass 29, count 0 2006.173.02:00:56.35#ibcon#about to read 6, iclass 29, count 0 2006.173.02:00:56.35#ibcon#read 6, iclass 29, count 0 2006.173.02:00:56.35#ibcon#end of sib2, iclass 29, count 0 2006.173.02:00:56.35#ibcon#*mode == 0, iclass 29, count 0 2006.173.02:00:56.35#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.02:00:56.35#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.02:00:56.35#ibcon#*before write, iclass 29, count 0 2006.173.02:00:56.35#ibcon#enter sib2, iclass 29, count 0 2006.173.02:00:56.35#ibcon#flushed, iclass 29, count 0 2006.173.02:00:56.35#ibcon#about to write, iclass 29, count 0 2006.173.02:00:56.35#ibcon#wrote, iclass 29, count 0 2006.173.02:00:56.35#ibcon#about to read 3, iclass 29, count 0 2006.173.02:00:56.39#ibcon#read 3, iclass 29, count 0 2006.173.02:00:56.39#ibcon#about to read 4, iclass 29, count 0 2006.173.02:00:56.39#ibcon#read 4, iclass 29, count 0 2006.173.02:00:56.39#ibcon#about to read 5, iclass 29, count 0 2006.173.02:00:56.39#ibcon#read 5, iclass 29, count 0 2006.173.02:00:56.39#ibcon#about to read 6, iclass 29, count 0 2006.173.02:00:56.39#ibcon#read 6, iclass 29, count 0 2006.173.02:00:56.39#ibcon#end of sib2, iclass 29, count 0 2006.173.02:00:56.39#ibcon#*after write, iclass 29, count 0 2006.173.02:00:56.39#ibcon#*before return 0, iclass 29, count 0 2006.173.02:00:56.39#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.02:00:56.39#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.02:00:56.39#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.02:00:56.39#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.02:00:56.39$vck44/va=3,5 2006.173.02:00:56.39#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.02:00:56.39#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.02:00:56.39#ibcon#ireg 11 cls_cnt 2 2006.173.02:00:56.39#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.02:00:56.45#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.02:00:56.45#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.02:00:56.45#ibcon#enter wrdev, iclass 31, count 2 2006.173.02:00:56.45#ibcon#first serial, iclass 31, count 2 2006.173.02:00:56.45#ibcon#enter sib2, iclass 31, count 2 2006.173.02:00:56.45#ibcon#flushed, iclass 31, count 2 2006.173.02:00:56.45#ibcon#about to write, iclass 31, count 2 2006.173.02:00:56.45#ibcon#wrote, iclass 31, count 2 2006.173.02:00:56.45#ibcon#about to read 3, iclass 31, count 2 2006.173.02:00:56.47#ibcon#read 3, iclass 31, count 2 2006.173.02:00:56.47#ibcon#about to read 4, iclass 31, count 2 2006.173.02:00:56.47#ibcon#read 4, iclass 31, count 2 2006.173.02:00:56.47#ibcon#about to read 5, iclass 31, count 2 2006.173.02:00:56.47#ibcon#read 5, iclass 31, count 2 2006.173.02:00:56.47#ibcon#about to read 6, iclass 31, count 2 2006.173.02:00:56.47#ibcon#read 6, iclass 31, count 2 2006.173.02:00:56.47#ibcon#end of sib2, iclass 31, count 2 2006.173.02:00:56.47#ibcon#*mode == 0, iclass 31, count 2 2006.173.02:00:56.47#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.02:00:56.47#ibcon#[25=AT03-05\r\n] 2006.173.02:00:56.47#ibcon#*before write, iclass 31, count 2 2006.173.02:00:56.47#ibcon#enter sib2, iclass 31, count 2 2006.173.02:00:56.47#ibcon#flushed, iclass 31, count 2 2006.173.02:00:56.47#ibcon#about to write, iclass 31, count 2 2006.173.02:00:56.47#ibcon#wrote, iclass 31, count 2 2006.173.02:00:56.47#ibcon#about to read 3, iclass 31, count 2 2006.173.02:00:56.50#ibcon#read 3, iclass 31, count 2 2006.173.02:00:56.50#ibcon#about to read 4, iclass 31, count 2 2006.173.02:00:56.50#ibcon#read 4, iclass 31, count 2 2006.173.02:00:56.50#ibcon#about to read 5, iclass 31, count 2 2006.173.02:00:56.50#ibcon#read 5, iclass 31, count 2 2006.173.02:00:56.50#ibcon#about to read 6, iclass 31, count 2 2006.173.02:00:56.50#ibcon#read 6, iclass 31, count 2 2006.173.02:00:56.50#ibcon#end of sib2, iclass 31, count 2 2006.173.02:00:56.50#ibcon#*after write, iclass 31, count 2 2006.173.02:00:56.50#ibcon#*before return 0, iclass 31, count 2 2006.173.02:00:56.50#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.02:00:56.50#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.02:00:56.50#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.02:00:56.50#ibcon#ireg 7 cls_cnt 0 2006.173.02:00:56.50#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.02:00:56.62#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.02:00:56.62#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.02:00:56.62#ibcon#enter wrdev, iclass 31, count 0 2006.173.02:00:56.62#ibcon#first serial, iclass 31, count 0 2006.173.02:00:56.62#ibcon#enter sib2, iclass 31, count 0 2006.173.02:00:56.62#ibcon#flushed, iclass 31, count 0 2006.173.02:00:56.62#ibcon#about to write, iclass 31, count 0 2006.173.02:00:56.62#ibcon#wrote, iclass 31, count 0 2006.173.02:00:56.62#ibcon#about to read 3, iclass 31, count 0 2006.173.02:00:56.64#ibcon#read 3, iclass 31, count 0 2006.173.02:00:56.64#ibcon#about to read 4, iclass 31, count 0 2006.173.02:00:56.64#ibcon#read 4, iclass 31, count 0 2006.173.02:00:56.64#ibcon#about to read 5, iclass 31, count 0 2006.173.02:00:56.64#ibcon#read 5, iclass 31, count 0 2006.173.02:00:56.64#ibcon#about to read 6, iclass 31, count 0 2006.173.02:00:56.64#ibcon#read 6, iclass 31, count 0 2006.173.02:00:56.64#ibcon#end of sib2, iclass 31, count 0 2006.173.02:00:56.64#ibcon#*mode == 0, iclass 31, count 0 2006.173.02:00:56.64#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.02:00:56.64#ibcon#[25=USB\r\n] 2006.173.02:00:56.64#ibcon#*before write, iclass 31, count 0 2006.173.02:00:56.64#ibcon#enter sib2, iclass 31, count 0 2006.173.02:00:56.64#ibcon#flushed, iclass 31, count 0 2006.173.02:00:56.64#ibcon#about to write, iclass 31, count 0 2006.173.02:00:56.64#ibcon#wrote, iclass 31, count 0 2006.173.02:00:56.64#ibcon#about to read 3, iclass 31, count 0 2006.173.02:00:56.67#ibcon#read 3, iclass 31, count 0 2006.173.02:00:56.67#ibcon#about to read 4, iclass 31, count 0 2006.173.02:00:56.67#ibcon#read 4, iclass 31, count 0 2006.173.02:00:56.67#ibcon#about to read 5, iclass 31, count 0 2006.173.02:00:56.67#ibcon#read 5, iclass 31, count 0 2006.173.02:00:56.67#ibcon#about to read 6, iclass 31, count 0 2006.173.02:00:56.67#ibcon#read 6, iclass 31, count 0 2006.173.02:00:56.67#ibcon#end of sib2, iclass 31, count 0 2006.173.02:00:56.67#ibcon#*after write, iclass 31, count 0 2006.173.02:00:56.67#ibcon#*before return 0, iclass 31, count 0 2006.173.02:00:56.67#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.02:00:56.67#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.02:00:56.67#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.02:00:56.67#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.02:00:56.67$vck44/valo=4,624.99 2006.173.02:00:56.67#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.02:00:56.67#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.02:00:56.67#ibcon#ireg 17 cls_cnt 0 2006.173.02:00:56.67#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.02:00:56.67#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.02:00:56.67#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.02:00:56.67#ibcon#enter wrdev, iclass 33, count 0 2006.173.02:00:56.67#ibcon#first serial, iclass 33, count 0 2006.173.02:00:56.67#ibcon#enter sib2, iclass 33, count 0 2006.173.02:00:56.67#ibcon#flushed, iclass 33, count 0 2006.173.02:00:56.67#ibcon#about to write, iclass 33, count 0 2006.173.02:00:56.67#ibcon#wrote, iclass 33, count 0 2006.173.02:00:56.67#ibcon#about to read 3, iclass 33, count 0 2006.173.02:00:56.69#ibcon#read 3, iclass 33, count 0 2006.173.02:00:56.69#ibcon#about to read 4, iclass 33, count 0 2006.173.02:00:56.69#ibcon#read 4, iclass 33, count 0 2006.173.02:00:56.69#ibcon#about to read 5, iclass 33, count 0 2006.173.02:00:56.69#ibcon#read 5, iclass 33, count 0 2006.173.02:00:56.69#ibcon#about to read 6, iclass 33, count 0 2006.173.02:00:56.69#ibcon#read 6, iclass 33, count 0 2006.173.02:00:56.69#ibcon#end of sib2, iclass 33, count 0 2006.173.02:00:56.69#ibcon#*mode == 0, iclass 33, count 0 2006.173.02:00:56.69#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.02:00:56.69#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.02:00:56.69#ibcon#*before write, iclass 33, count 0 2006.173.02:00:56.69#ibcon#enter sib2, iclass 33, count 0 2006.173.02:00:56.69#ibcon#flushed, iclass 33, count 0 2006.173.02:00:56.69#ibcon#about to write, iclass 33, count 0 2006.173.02:00:56.69#ibcon#wrote, iclass 33, count 0 2006.173.02:00:56.69#ibcon#about to read 3, iclass 33, count 0 2006.173.02:00:56.73#ibcon#read 3, iclass 33, count 0 2006.173.02:00:56.73#ibcon#about to read 4, iclass 33, count 0 2006.173.02:00:56.73#ibcon#read 4, iclass 33, count 0 2006.173.02:00:56.73#ibcon#about to read 5, iclass 33, count 0 2006.173.02:00:56.73#ibcon#read 5, iclass 33, count 0 2006.173.02:00:56.73#ibcon#about to read 6, iclass 33, count 0 2006.173.02:00:56.73#ibcon#read 6, iclass 33, count 0 2006.173.02:00:56.73#ibcon#end of sib2, iclass 33, count 0 2006.173.02:00:56.73#ibcon#*after write, iclass 33, count 0 2006.173.02:00:56.73#ibcon#*before return 0, iclass 33, count 0 2006.173.02:00:56.73#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.02:00:56.73#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.02:00:56.73#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.02:00:56.73#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.02:00:56.73$vck44/va=4,6 2006.173.02:00:56.73#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.02:00:56.73#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.02:00:56.73#ibcon#ireg 11 cls_cnt 2 2006.173.02:00:56.73#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.02:00:56.79#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.02:00:56.79#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.02:00:56.79#ibcon#enter wrdev, iclass 35, count 2 2006.173.02:00:56.79#ibcon#first serial, iclass 35, count 2 2006.173.02:00:56.79#ibcon#enter sib2, iclass 35, count 2 2006.173.02:00:56.79#ibcon#flushed, iclass 35, count 2 2006.173.02:00:56.79#ibcon#about to write, iclass 35, count 2 2006.173.02:00:56.79#ibcon#wrote, iclass 35, count 2 2006.173.02:00:56.79#ibcon#about to read 3, iclass 35, count 2 2006.173.02:00:56.81#ibcon#read 3, iclass 35, count 2 2006.173.02:00:56.81#ibcon#about to read 4, iclass 35, count 2 2006.173.02:00:56.81#ibcon#read 4, iclass 35, count 2 2006.173.02:00:56.81#ibcon#about to read 5, iclass 35, count 2 2006.173.02:00:56.81#ibcon#read 5, iclass 35, count 2 2006.173.02:00:56.81#ibcon#about to read 6, iclass 35, count 2 2006.173.02:00:56.81#ibcon#read 6, iclass 35, count 2 2006.173.02:00:56.81#ibcon#end of sib2, iclass 35, count 2 2006.173.02:00:56.81#ibcon#*mode == 0, iclass 35, count 2 2006.173.02:00:56.81#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.02:00:56.81#ibcon#[25=AT04-06\r\n] 2006.173.02:00:56.81#ibcon#*before write, iclass 35, count 2 2006.173.02:00:56.81#ibcon#enter sib2, iclass 35, count 2 2006.173.02:00:56.81#ibcon#flushed, iclass 35, count 2 2006.173.02:00:56.81#ibcon#about to write, iclass 35, count 2 2006.173.02:00:56.81#ibcon#wrote, iclass 35, count 2 2006.173.02:00:56.81#ibcon#about to read 3, iclass 35, count 2 2006.173.02:00:56.84#ibcon#read 3, iclass 35, count 2 2006.173.02:00:56.84#ibcon#about to read 4, iclass 35, count 2 2006.173.02:00:56.84#ibcon#read 4, iclass 35, count 2 2006.173.02:00:56.84#ibcon#about to read 5, iclass 35, count 2 2006.173.02:00:56.84#ibcon#read 5, iclass 35, count 2 2006.173.02:00:56.84#ibcon#about to read 6, iclass 35, count 2 2006.173.02:00:56.84#ibcon#read 6, iclass 35, count 2 2006.173.02:00:56.84#ibcon#end of sib2, iclass 35, count 2 2006.173.02:00:56.84#ibcon#*after write, iclass 35, count 2 2006.173.02:00:56.84#ibcon#*before return 0, iclass 35, count 2 2006.173.02:00:56.84#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.02:00:56.84#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.02:00:56.84#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.02:00:56.84#ibcon#ireg 7 cls_cnt 0 2006.173.02:00:56.84#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.02:00:56.96#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.02:00:56.96#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.02:00:56.96#ibcon#enter wrdev, iclass 35, count 0 2006.173.02:00:56.96#ibcon#first serial, iclass 35, count 0 2006.173.02:00:56.96#ibcon#enter sib2, iclass 35, count 0 2006.173.02:00:56.96#ibcon#flushed, iclass 35, count 0 2006.173.02:00:56.96#ibcon#about to write, iclass 35, count 0 2006.173.02:00:56.96#ibcon#wrote, iclass 35, count 0 2006.173.02:00:56.96#ibcon#about to read 3, iclass 35, count 0 2006.173.02:00:56.98#ibcon#read 3, iclass 35, count 0 2006.173.02:00:56.98#ibcon#about to read 4, iclass 35, count 0 2006.173.02:00:56.98#ibcon#read 4, iclass 35, count 0 2006.173.02:00:56.98#ibcon#about to read 5, iclass 35, count 0 2006.173.02:00:56.98#ibcon#read 5, iclass 35, count 0 2006.173.02:00:56.98#ibcon#about to read 6, iclass 35, count 0 2006.173.02:00:56.98#ibcon#read 6, iclass 35, count 0 2006.173.02:00:56.98#ibcon#end of sib2, iclass 35, count 0 2006.173.02:00:56.98#ibcon#*mode == 0, iclass 35, count 0 2006.173.02:00:56.98#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.02:00:56.98#ibcon#[25=USB\r\n] 2006.173.02:00:56.98#ibcon#*before write, iclass 35, count 0 2006.173.02:00:56.98#ibcon#enter sib2, iclass 35, count 0 2006.173.02:00:56.98#ibcon#flushed, iclass 35, count 0 2006.173.02:00:56.98#ibcon#about to write, iclass 35, count 0 2006.173.02:00:56.98#ibcon#wrote, iclass 35, count 0 2006.173.02:00:56.98#ibcon#about to read 3, iclass 35, count 0 2006.173.02:00:57.01#ibcon#read 3, iclass 35, count 0 2006.173.02:00:57.01#ibcon#about to read 4, iclass 35, count 0 2006.173.02:00:57.01#ibcon#read 4, iclass 35, count 0 2006.173.02:00:57.01#ibcon#about to read 5, iclass 35, count 0 2006.173.02:00:57.01#ibcon#read 5, iclass 35, count 0 2006.173.02:00:57.01#ibcon#about to read 6, iclass 35, count 0 2006.173.02:00:57.01#ibcon#read 6, iclass 35, count 0 2006.173.02:00:57.01#ibcon#end of sib2, iclass 35, count 0 2006.173.02:00:57.01#ibcon#*after write, iclass 35, count 0 2006.173.02:00:57.01#ibcon#*before return 0, iclass 35, count 0 2006.173.02:00:57.01#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.02:00:57.01#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.02:00:57.01#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.02:00:57.01#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.02:00:57.01$vck44/valo=5,734.99 2006.173.02:00:57.01#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.02:00:57.01#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.02:00:57.01#ibcon#ireg 17 cls_cnt 0 2006.173.02:00:57.01#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.02:00:57.01#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.02:00:57.01#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.02:00:57.01#ibcon#enter wrdev, iclass 37, count 0 2006.173.02:00:57.01#ibcon#first serial, iclass 37, count 0 2006.173.02:00:57.01#ibcon#enter sib2, iclass 37, count 0 2006.173.02:00:57.01#ibcon#flushed, iclass 37, count 0 2006.173.02:00:57.01#ibcon#about to write, iclass 37, count 0 2006.173.02:00:57.01#ibcon#wrote, iclass 37, count 0 2006.173.02:00:57.01#ibcon#about to read 3, iclass 37, count 0 2006.173.02:00:57.03#ibcon#read 3, iclass 37, count 0 2006.173.02:00:57.03#ibcon#about to read 4, iclass 37, count 0 2006.173.02:00:57.03#ibcon#read 4, iclass 37, count 0 2006.173.02:00:57.03#ibcon#about to read 5, iclass 37, count 0 2006.173.02:00:57.03#ibcon#read 5, iclass 37, count 0 2006.173.02:00:57.03#ibcon#about to read 6, iclass 37, count 0 2006.173.02:00:57.03#ibcon#read 6, iclass 37, count 0 2006.173.02:00:57.03#ibcon#end of sib2, iclass 37, count 0 2006.173.02:00:57.03#ibcon#*mode == 0, iclass 37, count 0 2006.173.02:00:57.03#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.02:00:57.03#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.02:00:57.03#ibcon#*before write, iclass 37, count 0 2006.173.02:00:57.03#ibcon#enter sib2, iclass 37, count 0 2006.173.02:00:57.03#ibcon#flushed, iclass 37, count 0 2006.173.02:00:57.03#ibcon#about to write, iclass 37, count 0 2006.173.02:00:57.03#ibcon#wrote, iclass 37, count 0 2006.173.02:00:57.03#ibcon#about to read 3, iclass 37, count 0 2006.173.02:00:57.07#ibcon#read 3, iclass 37, count 0 2006.173.02:00:57.07#ibcon#about to read 4, iclass 37, count 0 2006.173.02:00:57.07#ibcon#read 4, iclass 37, count 0 2006.173.02:00:57.07#ibcon#about to read 5, iclass 37, count 0 2006.173.02:00:57.07#ibcon#read 5, iclass 37, count 0 2006.173.02:00:57.07#ibcon#about to read 6, iclass 37, count 0 2006.173.02:00:57.07#ibcon#read 6, iclass 37, count 0 2006.173.02:00:57.07#ibcon#end of sib2, iclass 37, count 0 2006.173.02:00:57.07#ibcon#*after write, iclass 37, count 0 2006.173.02:00:57.07#ibcon#*before return 0, iclass 37, count 0 2006.173.02:00:57.07#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.02:00:57.07#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.02:00:57.07#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.02:00:57.07#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.02:00:57.07$vck44/va=5,4 2006.173.02:00:57.07#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.02:00:57.07#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.02:00:57.07#ibcon#ireg 11 cls_cnt 2 2006.173.02:00:57.07#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.02:00:57.13#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.02:00:57.13#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.02:00:57.13#ibcon#enter wrdev, iclass 39, count 2 2006.173.02:00:57.13#ibcon#first serial, iclass 39, count 2 2006.173.02:00:57.13#ibcon#enter sib2, iclass 39, count 2 2006.173.02:00:57.13#ibcon#flushed, iclass 39, count 2 2006.173.02:00:57.13#ibcon#about to write, iclass 39, count 2 2006.173.02:00:57.13#ibcon#wrote, iclass 39, count 2 2006.173.02:00:57.13#ibcon#about to read 3, iclass 39, count 2 2006.173.02:00:57.15#ibcon#read 3, iclass 39, count 2 2006.173.02:00:57.15#ibcon#about to read 4, iclass 39, count 2 2006.173.02:00:57.15#ibcon#read 4, iclass 39, count 2 2006.173.02:00:57.15#ibcon#about to read 5, iclass 39, count 2 2006.173.02:00:57.15#ibcon#read 5, iclass 39, count 2 2006.173.02:00:57.15#ibcon#about to read 6, iclass 39, count 2 2006.173.02:00:57.15#ibcon#read 6, iclass 39, count 2 2006.173.02:00:57.15#ibcon#end of sib2, iclass 39, count 2 2006.173.02:00:57.15#ibcon#*mode == 0, iclass 39, count 2 2006.173.02:00:57.15#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.02:00:57.15#ibcon#[25=AT05-04\r\n] 2006.173.02:00:57.15#ibcon#*before write, iclass 39, count 2 2006.173.02:00:57.15#ibcon#enter sib2, iclass 39, count 2 2006.173.02:00:57.15#ibcon#flushed, iclass 39, count 2 2006.173.02:00:57.15#ibcon#about to write, iclass 39, count 2 2006.173.02:00:57.15#ibcon#wrote, iclass 39, count 2 2006.173.02:00:57.15#ibcon#about to read 3, iclass 39, count 2 2006.173.02:00:57.18#ibcon#read 3, iclass 39, count 2 2006.173.02:00:57.18#ibcon#about to read 4, iclass 39, count 2 2006.173.02:00:57.18#ibcon#read 4, iclass 39, count 2 2006.173.02:00:57.18#ibcon#about to read 5, iclass 39, count 2 2006.173.02:00:57.18#ibcon#read 5, iclass 39, count 2 2006.173.02:00:57.18#ibcon#about to read 6, iclass 39, count 2 2006.173.02:00:57.18#ibcon#read 6, iclass 39, count 2 2006.173.02:00:57.18#ibcon#end of sib2, iclass 39, count 2 2006.173.02:00:57.18#ibcon#*after write, iclass 39, count 2 2006.173.02:00:57.18#ibcon#*before return 0, iclass 39, count 2 2006.173.02:00:57.18#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.02:00:57.18#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.02:00:57.18#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.02:00:57.18#ibcon#ireg 7 cls_cnt 0 2006.173.02:00:57.18#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.02:00:57.30#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.02:00:57.30#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.02:00:57.30#ibcon#enter wrdev, iclass 39, count 0 2006.173.02:00:57.30#ibcon#first serial, iclass 39, count 0 2006.173.02:00:57.30#ibcon#enter sib2, iclass 39, count 0 2006.173.02:00:57.30#ibcon#flushed, iclass 39, count 0 2006.173.02:00:57.30#ibcon#about to write, iclass 39, count 0 2006.173.02:00:57.30#ibcon#wrote, iclass 39, count 0 2006.173.02:00:57.30#ibcon#about to read 3, iclass 39, count 0 2006.173.02:00:57.32#ibcon#read 3, iclass 39, count 0 2006.173.02:00:57.32#ibcon#about to read 4, iclass 39, count 0 2006.173.02:00:57.32#ibcon#read 4, iclass 39, count 0 2006.173.02:00:57.32#ibcon#about to read 5, iclass 39, count 0 2006.173.02:00:57.32#ibcon#read 5, iclass 39, count 0 2006.173.02:00:57.32#ibcon#about to read 6, iclass 39, count 0 2006.173.02:00:57.32#ibcon#read 6, iclass 39, count 0 2006.173.02:00:57.32#ibcon#end of sib2, iclass 39, count 0 2006.173.02:00:57.32#ibcon#*mode == 0, iclass 39, count 0 2006.173.02:00:57.32#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.02:00:57.32#ibcon#[25=USB\r\n] 2006.173.02:00:57.32#ibcon#*before write, iclass 39, count 0 2006.173.02:00:57.32#ibcon#enter sib2, iclass 39, count 0 2006.173.02:00:57.32#ibcon#flushed, iclass 39, count 0 2006.173.02:00:57.32#ibcon#about to write, iclass 39, count 0 2006.173.02:00:57.32#ibcon#wrote, iclass 39, count 0 2006.173.02:00:57.32#ibcon#about to read 3, iclass 39, count 0 2006.173.02:00:57.36#ibcon#read 3, iclass 39, count 0 2006.173.02:00:57.36#ibcon#about to read 4, iclass 39, count 0 2006.173.02:00:57.36#ibcon#read 4, iclass 39, count 0 2006.173.02:00:57.36#ibcon#about to read 5, iclass 39, count 0 2006.173.02:00:57.36#ibcon#read 5, iclass 39, count 0 2006.173.02:00:57.36#ibcon#about to read 6, iclass 39, count 0 2006.173.02:00:57.36#ibcon#read 6, iclass 39, count 0 2006.173.02:00:57.36#ibcon#end of sib2, iclass 39, count 0 2006.173.02:00:57.36#ibcon#*after write, iclass 39, count 0 2006.173.02:00:57.36#ibcon#*before return 0, iclass 39, count 0 2006.173.02:00:57.36#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.02:00:57.36#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.02:00:57.36#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.02:00:57.36#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.02:00:57.36$vck44/valo=6,814.99 2006.173.02:00:57.36#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.02:00:57.36#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.02:00:57.36#ibcon#ireg 17 cls_cnt 0 2006.173.02:00:57.36#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.02:00:57.36#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.02:00:57.36#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.02:00:57.36#ibcon#enter wrdev, iclass 3, count 0 2006.173.02:00:57.36#ibcon#first serial, iclass 3, count 0 2006.173.02:00:57.36#ibcon#enter sib2, iclass 3, count 0 2006.173.02:00:57.36#ibcon#flushed, iclass 3, count 0 2006.173.02:00:57.36#ibcon#about to write, iclass 3, count 0 2006.173.02:00:57.36#ibcon#wrote, iclass 3, count 0 2006.173.02:00:57.36#ibcon#about to read 3, iclass 3, count 0 2006.173.02:00:57.38#ibcon#read 3, iclass 3, count 0 2006.173.02:00:57.38#ibcon#about to read 4, iclass 3, count 0 2006.173.02:00:57.38#ibcon#read 4, iclass 3, count 0 2006.173.02:00:57.38#ibcon#about to read 5, iclass 3, count 0 2006.173.02:00:57.38#ibcon#read 5, iclass 3, count 0 2006.173.02:00:57.38#ibcon#about to read 6, iclass 3, count 0 2006.173.02:00:57.38#ibcon#read 6, iclass 3, count 0 2006.173.02:00:57.38#ibcon#end of sib2, iclass 3, count 0 2006.173.02:00:57.38#ibcon#*mode == 0, iclass 3, count 0 2006.173.02:00:57.38#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.02:00:57.38#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.02:00:57.38#ibcon#*before write, iclass 3, count 0 2006.173.02:00:57.38#ibcon#enter sib2, iclass 3, count 0 2006.173.02:00:57.38#ibcon#flushed, iclass 3, count 0 2006.173.02:00:57.38#ibcon#about to write, iclass 3, count 0 2006.173.02:00:57.38#ibcon#wrote, iclass 3, count 0 2006.173.02:00:57.38#ibcon#about to read 3, iclass 3, count 0 2006.173.02:00:57.42#ibcon#read 3, iclass 3, count 0 2006.173.02:00:57.42#ibcon#about to read 4, iclass 3, count 0 2006.173.02:00:57.42#ibcon#read 4, iclass 3, count 0 2006.173.02:00:57.42#ibcon#about to read 5, iclass 3, count 0 2006.173.02:00:57.42#ibcon#read 5, iclass 3, count 0 2006.173.02:00:57.42#ibcon#about to read 6, iclass 3, count 0 2006.173.02:00:57.42#ibcon#read 6, iclass 3, count 0 2006.173.02:00:57.42#ibcon#end of sib2, iclass 3, count 0 2006.173.02:00:57.42#ibcon#*after write, iclass 3, count 0 2006.173.02:00:57.42#ibcon#*before return 0, iclass 3, count 0 2006.173.02:00:57.42#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.02:00:57.42#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.02:00:57.42#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.02:00:57.42#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.02:00:57.42$vck44/va=6,3 2006.173.02:00:57.42#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.02:00:57.42#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.02:00:57.42#ibcon#ireg 11 cls_cnt 2 2006.173.02:00:57.42#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.02:00:57.48#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.02:00:57.48#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.02:00:57.48#ibcon#enter wrdev, iclass 5, count 2 2006.173.02:00:57.48#ibcon#first serial, iclass 5, count 2 2006.173.02:00:57.48#ibcon#enter sib2, iclass 5, count 2 2006.173.02:00:57.48#ibcon#flushed, iclass 5, count 2 2006.173.02:00:57.48#ibcon#about to write, iclass 5, count 2 2006.173.02:00:57.48#ibcon#wrote, iclass 5, count 2 2006.173.02:00:57.48#ibcon#about to read 3, iclass 5, count 2 2006.173.02:00:57.50#ibcon#read 3, iclass 5, count 2 2006.173.02:00:57.50#ibcon#about to read 4, iclass 5, count 2 2006.173.02:00:57.50#ibcon#read 4, iclass 5, count 2 2006.173.02:00:57.50#ibcon#about to read 5, iclass 5, count 2 2006.173.02:00:57.50#ibcon#read 5, iclass 5, count 2 2006.173.02:00:57.50#ibcon#about to read 6, iclass 5, count 2 2006.173.02:00:57.50#ibcon#read 6, iclass 5, count 2 2006.173.02:00:57.50#ibcon#end of sib2, iclass 5, count 2 2006.173.02:00:57.50#ibcon#*mode == 0, iclass 5, count 2 2006.173.02:00:57.50#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.02:00:57.50#ibcon#[25=AT06-03\r\n] 2006.173.02:00:57.50#ibcon#*before write, iclass 5, count 2 2006.173.02:00:57.50#ibcon#enter sib2, iclass 5, count 2 2006.173.02:00:57.50#ibcon#flushed, iclass 5, count 2 2006.173.02:00:57.50#ibcon#about to write, iclass 5, count 2 2006.173.02:00:57.50#ibcon#wrote, iclass 5, count 2 2006.173.02:00:57.50#ibcon#about to read 3, iclass 5, count 2 2006.173.02:00:57.53#ibcon#read 3, iclass 5, count 2 2006.173.02:00:57.53#ibcon#about to read 4, iclass 5, count 2 2006.173.02:00:57.53#ibcon#read 4, iclass 5, count 2 2006.173.02:00:57.53#ibcon#about to read 5, iclass 5, count 2 2006.173.02:00:57.53#ibcon#read 5, iclass 5, count 2 2006.173.02:00:57.53#ibcon#about to read 6, iclass 5, count 2 2006.173.02:00:57.53#ibcon#read 6, iclass 5, count 2 2006.173.02:00:57.53#ibcon#end of sib2, iclass 5, count 2 2006.173.02:00:57.53#ibcon#*after write, iclass 5, count 2 2006.173.02:00:57.53#ibcon#*before return 0, iclass 5, count 2 2006.173.02:00:57.53#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.02:00:57.53#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.02:00:57.53#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.02:00:57.53#ibcon#ireg 7 cls_cnt 0 2006.173.02:00:57.53#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.02:00:57.65#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.02:00:57.65#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.02:00:57.65#ibcon#enter wrdev, iclass 5, count 0 2006.173.02:00:57.65#ibcon#first serial, iclass 5, count 0 2006.173.02:00:57.65#ibcon#enter sib2, iclass 5, count 0 2006.173.02:00:57.65#ibcon#flushed, iclass 5, count 0 2006.173.02:00:57.65#ibcon#about to write, iclass 5, count 0 2006.173.02:00:57.65#ibcon#wrote, iclass 5, count 0 2006.173.02:00:57.65#ibcon#about to read 3, iclass 5, count 0 2006.173.02:00:57.67#ibcon#read 3, iclass 5, count 0 2006.173.02:00:57.67#ibcon#about to read 4, iclass 5, count 0 2006.173.02:00:57.67#ibcon#read 4, iclass 5, count 0 2006.173.02:00:57.67#ibcon#about to read 5, iclass 5, count 0 2006.173.02:00:57.67#ibcon#read 5, iclass 5, count 0 2006.173.02:00:57.67#ibcon#about to read 6, iclass 5, count 0 2006.173.02:00:57.67#ibcon#read 6, iclass 5, count 0 2006.173.02:00:57.67#ibcon#end of sib2, iclass 5, count 0 2006.173.02:00:57.67#ibcon#*mode == 0, iclass 5, count 0 2006.173.02:00:57.67#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.02:00:57.67#ibcon#[25=USB\r\n] 2006.173.02:00:57.67#ibcon#*before write, iclass 5, count 0 2006.173.02:00:57.67#ibcon#enter sib2, iclass 5, count 0 2006.173.02:00:57.67#ibcon#flushed, iclass 5, count 0 2006.173.02:00:57.67#ibcon#about to write, iclass 5, count 0 2006.173.02:00:57.67#ibcon#wrote, iclass 5, count 0 2006.173.02:00:57.67#ibcon#about to read 3, iclass 5, count 0 2006.173.02:00:57.70#ibcon#read 3, iclass 5, count 0 2006.173.02:00:57.70#ibcon#about to read 4, iclass 5, count 0 2006.173.02:00:57.70#ibcon#read 4, iclass 5, count 0 2006.173.02:00:57.70#ibcon#about to read 5, iclass 5, count 0 2006.173.02:00:57.70#ibcon#read 5, iclass 5, count 0 2006.173.02:00:57.70#ibcon#about to read 6, iclass 5, count 0 2006.173.02:00:57.70#ibcon#read 6, iclass 5, count 0 2006.173.02:00:57.70#ibcon#end of sib2, iclass 5, count 0 2006.173.02:00:57.70#ibcon#*after write, iclass 5, count 0 2006.173.02:00:57.70#ibcon#*before return 0, iclass 5, count 0 2006.173.02:00:57.70#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.02:00:57.70#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.02:00:57.70#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.02:00:57.70#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.02:00:57.70$vck44/valo=7,864.99 2006.173.02:00:57.70#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.02:00:57.70#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.02:00:57.70#ibcon#ireg 17 cls_cnt 0 2006.173.02:00:57.70#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.02:00:57.70#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.02:00:57.70#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.02:00:57.70#ibcon#enter wrdev, iclass 7, count 0 2006.173.02:00:57.70#ibcon#first serial, iclass 7, count 0 2006.173.02:00:57.70#ibcon#enter sib2, iclass 7, count 0 2006.173.02:00:57.70#ibcon#flushed, iclass 7, count 0 2006.173.02:00:57.70#ibcon#about to write, iclass 7, count 0 2006.173.02:00:57.70#ibcon#wrote, iclass 7, count 0 2006.173.02:00:57.70#ibcon#about to read 3, iclass 7, count 0 2006.173.02:00:57.72#ibcon#read 3, iclass 7, count 0 2006.173.02:00:57.72#ibcon#about to read 4, iclass 7, count 0 2006.173.02:00:57.72#ibcon#read 4, iclass 7, count 0 2006.173.02:00:57.72#ibcon#about to read 5, iclass 7, count 0 2006.173.02:00:57.72#ibcon#read 5, iclass 7, count 0 2006.173.02:00:57.72#ibcon#about to read 6, iclass 7, count 0 2006.173.02:00:57.72#ibcon#read 6, iclass 7, count 0 2006.173.02:00:57.72#ibcon#end of sib2, iclass 7, count 0 2006.173.02:00:57.72#ibcon#*mode == 0, iclass 7, count 0 2006.173.02:00:57.72#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.02:00:57.72#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.02:00:57.72#ibcon#*before write, iclass 7, count 0 2006.173.02:00:57.72#ibcon#enter sib2, iclass 7, count 0 2006.173.02:00:57.72#ibcon#flushed, iclass 7, count 0 2006.173.02:00:57.72#ibcon#about to write, iclass 7, count 0 2006.173.02:00:57.72#ibcon#wrote, iclass 7, count 0 2006.173.02:00:57.72#ibcon#about to read 3, iclass 7, count 0 2006.173.02:00:57.76#ibcon#read 3, iclass 7, count 0 2006.173.02:00:57.76#ibcon#about to read 4, iclass 7, count 0 2006.173.02:00:57.76#ibcon#read 4, iclass 7, count 0 2006.173.02:00:57.76#ibcon#about to read 5, iclass 7, count 0 2006.173.02:00:57.76#ibcon#read 5, iclass 7, count 0 2006.173.02:00:57.76#ibcon#about to read 6, iclass 7, count 0 2006.173.02:00:57.76#ibcon#read 6, iclass 7, count 0 2006.173.02:00:57.76#ibcon#end of sib2, iclass 7, count 0 2006.173.02:00:57.76#ibcon#*after write, iclass 7, count 0 2006.173.02:00:57.76#ibcon#*before return 0, iclass 7, count 0 2006.173.02:00:57.76#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.02:00:57.76#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.02:00:57.76#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.02:00:57.76#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.02:00:57.76$vck44/va=7,4 2006.173.02:00:57.76#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.02:00:57.76#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.02:00:57.76#ibcon#ireg 11 cls_cnt 2 2006.173.02:00:57.76#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.02:00:57.82#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.02:00:57.82#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.02:00:57.82#ibcon#enter wrdev, iclass 11, count 2 2006.173.02:00:57.82#ibcon#first serial, iclass 11, count 2 2006.173.02:00:57.82#ibcon#enter sib2, iclass 11, count 2 2006.173.02:00:57.82#ibcon#flushed, iclass 11, count 2 2006.173.02:00:57.82#ibcon#about to write, iclass 11, count 2 2006.173.02:00:57.82#ibcon#wrote, iclass 11, count 2 2006.173.02:00:57.82#ibcon#about to read 3, iclass 11, count 2 2006.173.02:00:57.84#ibcon#read 3, iclass 11, count 2 2006.173.02:00:57.84#ibcon#about to read 4, iclass 11, count 2 2006.173.02:00:57.84#ibcon#read 4, iclass 11, count 2 2006.173.02:00:57.84#ibcon#about to read 5, iclass 11, count 2 2006.173.02:00:57.84#ibcon#read 5, iclass 11, count 2 2006.173.02:00:57.84#ibcon#about to read 6, iclass 11, count 2 2006.173.02:00:57.84#ibcon#read 6, iclass 11, count 2 2006.173.02:00:57.84#ibcon#end of sib2, iclass 11, count 2 2006.173.02:00:57.84#ibcon#*mode == 0, iclass 11, count 2 2006.173.02:00:57.84#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.02:00:57.84#ibcon#[25=AT07-04\r\n] 2006.173.02:00:57.84#ibcon#*before write, iclass 11, count 2 2006.173.02:00:57.84#ibcon#enter sib2, iclass 11, count 2 2006.173.02:00:57.84#ibcon#flushed, iclass 11, count 2 2006.173.02:00:57.84#ibcon#about to write, iclass 11, count 2 2006.173.02:00:57.84#ibcon#wrote, iclass 11, count 2 2006.173.02:00:57.84#ibcon#about to read 3, iclass 11, count 2 2006.173.02:00:57.87#ibcon#read 3, iclass 11, count 2 2006.173.02:00:57.87#ibcon#about to read 4, iclass 11, count 2 2006.173.02:00:57.87#ibcon#read 4, iclass 11, count 2 2006.173.02:00:57.87#ibcon#about to read 5, iclass 11, count 2 2006.173.02:00:57.87#ibcon#read 5, iclass 11, count 2 2006.173.02:00:57.87#ibcon#about to read 6, iclass 11, count 2 2006.173.02:00:57.87#ibcon#read 6, iclass 11, count 2 2006.173.02:00:57.87#ibcon#end of sib2, iclass 11, count 2 2006.173.02:00:57.87#ibcon#*after write, iclass 11, count 2 2006.173.02:00:57.87#ibcon#*before return 0, iclass 11, count 2 2006.173.02:00:57.87#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.02:00:57.87#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.02:00:57.87#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.02:00:57.87#ibcon#ireg 7 cls_cnt 0 2006.173.02:00:57.87#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.02:00:57.99#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.02:00:57.99#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.02:00:57.99#ibcon#enter wrdev, iclass 11, count 0 2006.173.02:00:57.99#ibcon#first serial, iclass 11, count 0 2006.173.02:00:57.99#ibcon#enter sib2, iclass 11, count 0 2006.173.02:00:57.99#ibcon#flushed, iclass 11, count 0 2006.173.02:00:57.99#ibcon#about to write, iclass 11, count 0 2006.173.02:00:57.99#ibcon#wrote, iclass 11, count 0 2006.173.02:00:57.99#ibcon#about to read 3, iclass 11, count 0 2006.173.02:00:58.01#ibcon#read 3, iclass 11, count 0 2006.173.02:00:58.01#ibcon#about to read 4, iclass 11, count 0 2006.173.02:00:58.01#ibcon#read 4, iclass 11, count 0 2006.173.02:00:58.01#ibcon#about to read 5, iclass 11, count 0 2006.173.02:00:58.01#ibcon#read 5, iclass 11, count 0 2006.173.02:00:58.01#ibcon#about to read 6, iclass 11, count 0 2006.173.02:00:58.01#ibcon#read 6, iclass 11, count 0 2006.173.02:00:58.01#ibcon#end of sib2, iclass 11, count 0 2006.173.02:00:58.01#ibcon#*mode == 0, iclass 11, count 0 2006.173.02:00:58.01#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.02:00:58.01#ibcon#[25=USB\r\n] 2006.173.02:00:58.01#ibcon#*before write, iclass 11, count 0 2006.173.02:00:58.01#ibcon#enter sib2, iclass 11, count 0 2006.173.02:00:58.01#ibcon#flushed, iclass 11, count 0 2006.173.02:00:58.01#ibcon#about to write, iclass 11, count 0 2006.173.02:00:58.01#ibcon#wrote, iclass 11, count 0 2006.173.02:00:58.01#ibcon#about to read 3, iclass 11, count 0 2006.173.02:00:58.04#ibcon#read 3, iclass 11, count 0 2006.173.02:00:58.04#ibcon#about to read 4, iclass 11, count 0 2006.173.02:00:58.04#ibcon#read 4, iclass 11, count 0 2006.173.02:00:58.04#ibcon#about to read 5, iclass 11, count 0 2006.173.02:00:58.04#ibcon#read 5, iclass 11, count 0 2006.173.02:00:58.04#ibcon#about to read 6, iclass 11, count 0 2006.173.02:00:58.04#ibcon#read 6, iclass 11, count 0 2006.173.02:00:58.04#ibcon#end of sib2, iclass 11, count 0 2006.173.02:00:58.04#ibcon#*after write, iclass 11, count 0 2006.173.02:00:58.04#ibcon#*before return 0, iclass 11, count 0 2006.173.02:00:58.04#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.02:00:58.04#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.02:00:58.04#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.02:00:58.04#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.02:00:58.04$vck44/valo=8,884.99 2006.173.02:00:58.04#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.02:00:58.04#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.02:00:58.04#ibcon#ireg 17 cls_cnt 0 2006.173.02:00:58.04#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.02:00:58.04#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.02:00:58.04#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.02:00:58.04#ibcon#enter wrdev, iclass 13, count 0 2006.173.02:00:58.04#ibcon#first serial, iclass 13, count 0 2006.173.02:00:58.04#ibcon#enter sib2, iclass 13, count 0 2006.173.02:00:58.04#ibcon#flushed, iclass 13, count 0 2006.173.02:00:58.04#ibcon#about to write, iclass 13, count 0 2006.173.02:00:58.04#ibcon#wrote, iclass 13, count 0 2006.173.02:00:58.04#ibcon#about to read 3, iclass 13, count 0 2006.173.02:00:58.06#ibcon#read 3, iclass 13, count 0 2006.173.02:00:58.06#ibcon#about to read 4, iclass 13, count 0 2006.173.02:00:58.06#ibcon#read 4, iclass 13, count 0 2006.173.02:00:58.06#ibcon#about to read 5, iclass 13, count 0 2006.173.02:00:58.06#ibcon#read 5, iclass 13, count 0 2006.173.02:00:58.06#ibcon#about to read 6, iclass 13, count 0 2006.173.02:00:58.06#ibcon#read 6, iclass 13, count 0 2006.173.02:00:58.06#ibcon#end of sib2, iclass 13, count 0 2006.173.02:00:58.06#ibcon#*mode == 0, iclass 13, count 0 2006.173.02:00:58.06#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.02:00:58.06#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.02:00:58.06#ibcon#*before write, iclass 13, count 0 2006.173.02:00:58.06#ibcon#enter sib2, iclass 13, count 0 2006.173.02:00:58.06#ibcon#flushed, iclass 13, count 0 2006.173.02:00:58.06#ibcon#about to write, iclass 13, count 0 2006.173.02:00:58.06#ibcon#wrote, iclass 13, count 0 2006.173.02:00:58.06#ibcon#about to read 3, iclass 13, count 0 2006.173.02:00:58.10#ibcon#read 3, iclass 13, count 0 2006.173.02:00:58.10#ibcon#about to read 4, iclass 13, count 0 2006.173.02:00:58.10#ibcon#read 4, iclass 13, count 0 2006.173.02:00:58.10#ibcon#about to read 5, iclass 13, count 0 2006.173.02:00:58.10#ibcon#read 5, iclass 13, count 0 2006.173.02:00:58.10#ibcon#about to read 6, iclass 13, count 0 2006.173.02:00:58.10#ibcon#read 6, iclass 13, count 0 2006.173.02:00:58.10#ibcon#end of sib2, iclass 13, count 0 2006.173.02:00:58.10#ibcon#*after write, iclass 13, count 0 2006.173.02:00:58.10#ibcon#*before return 0, iclass 13, count 0 2006.173.02:00:58.10#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.02:00:58.10#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.02:00:58.10#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.02:00:58.10#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.02:00:58.10$vck44/va=8,4 2006.173.02:00:58.10#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.02:00:58.10#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.02:00:58.10#ibcon#ireg 11 cls_cnt 2 2006.173.02:00:58.10#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.02:00:58.16#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.02:00:58.16#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.02:00:58.16#ibcon#enter wrdev, iclass 15, count 2 2006.173.02:00:58.16#ibcon#first serial, iclass 15, count 2 2006.173.02:00:58.16#ibcon#enter sib2, iclass 15, count 2 2006.173.02:00:58.16#ibcon#flushed, iclass 15, count 2 2006.173.02:00:58.16#ibcon#about to write, iclass 15, count 2 2006.173.02:00:58.16#ibcon#wrote, iclass 15, count 2 2006.173.02:00:58.16#ibcon#about to read 3, iclass 15, count 2 2006.173.02:00:58.18#ibcon#read 3, iclass 15, count 2 2006.173.02:00:58.18#ibcon#about to read 4, iclass 15, count 2 2006.173.02:00:58.18#ibcon#read 4, iclass 15, count 2 2006.173.02:00:58.18#ibcon#about to read 5, iclass 15, count 2 2006.173.02:00:58.18#ibcon#read 5, iclass 15, count 2 2006.173.02:00:58.18#ibcon#about to read 6, iclass 15, count 2 2006.173.02:00:58.18#ibcon#read 6, iclass 15, count 2 2006.173.02:00:58.18#ibcon#end of sib2, iclass 15, count 2 2006.173.02:00:58.18#ibcon#*mode == 0, iclass 15, count 2 2006.173.02:00:58.18#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.02:00:58.18#ibcon#[25=AT08-04\r\n] 2006.173.02:00:58.18#ibcon#*before write, iclass 15, count 2 2006.173.02:00:58.18#ibcon#enter sib2, iclass 15, count 2 2006.173.02:00:58.18#ibcon#flushed, iclass 15, count 2 2006.173.02:00:58.18#ibcon#about to write, iclass 15, count 2 2006.173.02:00:58.18#ibcon#wrote, iclass 15, count 2 2006.173.02:00:58.18#ibcon#about to read 3, iclass 15, count 2 2006.173.02:00:58.21#ibcon#read 3, iclass 15, count 2 2006.173.02:00:58.21#ibcon#about to read 4, iclass 15, count 2 2006.173.02:00:58.21#ibcon#read 4, iclass 15, count 2 2006.173.02:00:58.21#ibcon#about to read 5, iclass 15, count 2 2006.173.02:00:58.21#ibcon#read 5, iclass 15, count 2 2006.173.02:00:58.21#ibcon#about to read 6, iclass 15, count 2 2006.173.02:00:58.21#ibcon#read 6, iclass 15, count 2 2006.173.02:00:58.21#ibcon#end of sib2, iclass 15, count 2 2006.173.02:00:58.21#ibcon#*after write, iclass 15, count 2 2006.173.02:00:58.21#ibcon#*before return 0, iclass 15, count 2 2006.173.02:00:58.21#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.02:00:58.21#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.02:00:58.21#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.02:00:58.21#ibcon#ireg 7 cls_cnt 0 2006.173.02:00:58.21#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.02:00:58.33#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.02:00:58.33#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.02:00:58.33#ibcon#enter wrdev, iclass 15, count 0 2006.173.02:00:58.33#ibcon#first serial, iclass 15, count 0 2006.173.02:00:58.33#ibcon#enter sib2, iclass 15, count 0 2006.173.02:00:58.33#ibcon#flushed, iclass 15, count 0 2006.173.02:00:58.33#ibcon#about to write, iclass 15, count 0 2006.173.02:00:58.33#ibcon#wrote, iclass 15, count 0 2006.173.02:00:58.33#ibcon#about to read 3, iclass 15, count 0 2006.173.02:00:58.35#ibcon#read 3, iclass 15, count 0 2006.173.02:00:58.35#ibcon#about to read 4, iclass 15, count 0 2006.173.02:00:58.35#ibcon#read 4, iclass 15, count 0 2006.173.02:00:58.35#ibcon#about to read 5, iclass 15, count 0 2006.173.02:00:58.35#ibcon#read 5, iclass 15, count 0 2006.173.02:00:58.35#ibcon#about to read 6, iclass 15, count 0 2006.173.02:00:58.35#ibcon#read 6, iclass 15, count 0 2006.173.02:00:58.35#ibcon#end of sib2, iclass 15, count 0 2006.173.02:00:58.35#ibcon#*mode == 0, iclass 15, count 0 2006.173.02:00:58.35#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.02:00:58.35#ibcon#[25=USB\r\n] 2006.173.02:00:58.35#ibcon#*before write, iclass 15, count 0 2006.173.02:00:58.35#ibcon#enter sib2, iclass 15, count 0 2006.173.02:00:58.35#ibcon#flushed, iclass 15, count 0 2006.173.02:00:58.35#ibcon#about to write, iclass 15, count 0 2006.173.02:00:58.35#ibcon#wrote, iclass 15, count 0 2006.173.02:00:58.35#ibcon#about to read 3, iclass 15, count 0 2006.173.02:00:58.38#ibcon#read 3, iclass 15, count 0 2006.173.02:00:58.38#ibcon#about to read 4, iclass 15, count 0 2006.173.02:00:58.38#ibcon#read 4, iclass 15, count 0 2006.173.02:00:58.38#ibcon#about to read 5, iclass 15, count 0 2006.173.02:00:58.38#ibcon#read 5, iclass 15, count 0 2006.173.02:00:58.38#ibcon#about to read 6, iclass 15, count 0 2006.173.02:00:58.38#ibcon#read 6, iclass 15, count 0 2006.173.02:00:58.38#ibcon#end of sib2, iclass 15, count 0 2006.173.02:00:58.38#ibcon#*after write, iclass 15, count 0 2006.173.02:00:58.38#ibcon#*before return 0, iclass 15, count 0 2006.173.02:00:58.38#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.02:00:58.38#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.02:00:58.38#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.02:00:58.38#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.02:00:58.38$vck44/vblo=1,629.99 2006.173.02:00:58.38#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.02:00:58.38#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.02:00:58.38#ibcon#ireg 17 cls_cnt 0 2006.173.02:00:58.38#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.02:00:58.38#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.02:00:58.38#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.02:00:58.38#ibcon#enter wrdev, iclass 17, count 0 2006.173.02:00:58.38#ibcon#first serial, iclass 17, count 0 2006.173.02:00:58.38#ibcon#enter sib2, iclass 17, count 0 2006.173.02:00:58.38#ibcon#flushed, iclass 17, count 0 2006.173.02:00:58.38#ibcon#about to write, iclass 17, count 0 2006.173.02:00:58.38#ibcon#wrote, iclass 17, count 0 2006.173.02:00:58.38#ibcon#about to read 3, iclass 17, count 0 2006.173.02:00:58.40#ibcon#read 3, iclass 17, count 0 2006.173.02:00:58.40#ibcon#about to read 4, iclass 17, count 0 2006.173.02:00:58.40#ibcon#read 4, iclass 17, count 0 2006.173.02:00:58.40#ibcon#about to read 5, iclass 17, count 0 2006.173.02:00:58.40#ibcon#read 5, iclass 17, count 0 2006.173.02:00:58.40#ibcon#about to read 6, iclass 17, count 0 2006.173.02:00:58.40#ibcon#read 6, iclass 17, count 0 2006.173.02:00:58.40#ibcon#end of sib2, iclass 17, count 0 2006.173.02:00:58.40#ibcon#*mode == 0, iclass 17, count 0 2006.173.02:00:58.40#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.02:00:58.40#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.02:00:58.40#ibcon#*before write, iclass 17, count 0 2006.173.02:00:58.40#ibcon#enter sib2, iclass 17, count 0 2006.173.02:00:58.40#ibcon#flushed, iclass 17, count 0 2006.173.02:00:58.40#ibcon#about to write, iclass 17, count 0 2006.173.02:00:58.40#ibcon#wrote, iclass 17, count 0 2006.173.02:00:58.40#ibcon#about to read 3, iclass 17, count 0 2006.173.02:00:58.44#ibcon#read 3, iclass 17, count 0 2006.173.02:00:58.44#ibcon#about to read 4, iclass 17, count 0 2006.173.02:00:58.44#ibcon#read 4, iclass 17, count 0 2006.173.02:00:58.44#ibcon#about to read 5, iclass 17, count 0 2006.173.02:00:58.44#ibcon#read 5, iclass 17, count 0 2006.173.02:00:58.44#ibcon#about to read 6, iclass 17, count 0 2006.173.02:00:58.44#ibcon#read 6, iclass 17, count 0 2006.173.02:00:58.44#ibcon#end of sib2, iclass 17, count 0 2006.173.02:00:58.44#ibcon#*after write, iclass 17, count 0 2006.173.02:00:58.44#ibcon#*before return 0, iclass 17, count 0 2006.173.02:00:58.44#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.02:00:58.44#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.02:00:58.44#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.02:00:58.44#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.02:00:58.44$vck44/vb=1,4 2006.173.02:00:58.44#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.02:00:58.44#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.02:00:58.44#ibcon#ireg 11 cls_cnt 2 2006.173.02:00:58.44#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.02:00:58.44#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.02:00:58.44#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.02:00:58.44#ibcon#enter wrdev, iclass 19, count 2 2006.173.02:00:58.44#ibcon#first serial, iclass 19, count 2 2006.173.02:00:58.44#ibcon#enter sib2, iclass 19, count 2 2006.173.02:00:58.44#ibcon#flushed, iclass 19, count 2 2006.173.02:00:58.44#ibcon#about to write, iclass 19, count 2 2006.173.02:00:58.44#ibcon#wrote, iclass 19, count 2 2006.173.02:00:58.44#ibcon#about to read 3, iclass 19, count 2 2006.173.02:00:58.46#ibcon#read 3, iclass 19, count 2 2006.173.02:00:58.46#ibcon#about to read 4, iclass 19, count 2 2006.173.02:00:58.46#ibcon#read 4, iclass 19, count 2 2006.173.02:00:58.46#ibcon#about to read 5, iclass 19, count 2 2006.173.02:00:58.46#ibcon#read 5, iclass 19, count 2 2006.173.02:00:58.46#ibcon#about to read 6, iclass 19, count 2 2006.173.02:00:58.46#ibcon#read 6, iclass 19, count 2 2006.173.02:00:58.46#ibcon#end of sib2, iclass 19, count 2 2006.173.02:00:58.46#ibcon#*mode == 0, iclass 19, count 2 2006.173.02:00:58.46#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.02:00:58.46#ibcon#[27=AT01-04\r\n] 2006.173.02:00:58.46#ibcon#*before write, iclass 19, count 2 2006.173.02:00:58.46#ibcon#enter sib2, iclass 19, count 2 2006.173.02:00:58.46#ibcon#flushed, iclass 19, count 2 2006.173.02:00:58.46#ibcon#about to write, iclass 19, count 2 2006.173.02:00:58.46#ibcon#wrote, iclass 19, count 2 2006.173.02:00:58.46#ibcon#about to read 3, iclass 19, count 2 2006.173.02:00:58.49#ibcon#read 3, iclass 19, count 2 2006.173.02:00:58.49#ibcon#about to read 4, iclass 19, count 2 2006.173.02:00:58.49#ibcon#read 4, iclass 19, count 2 2006.173.02:00:58.49#ibcon#about to read 5, iclass 19, count 2 2006.173.02:00:58.49#ibcon#read 5, iclass 19, count 2 2006.173.02:00:58.49#ibcon#about to read 6, iclass 19, count 2 2006.173.02:00:58.49#ibcon#read 6, iclass 19, count 2 2006.173.02:00:58.49#ibcon#end of sib2, iclass 19, count 2 2006.173.02:00:58.49#ibcon#*after write, iclass 19, count 2 2006.173.02:00:58.49#ibcon#*before return 0, iclass 19, count 2 2006.173.02:00:58.49#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.02:00:58.49#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.02:00:58.49#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.02:00:58.49#ibcon#ireg 7 cls_cnt 0 2006.173.02:00:58.49#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.02:00:58.61#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.02:00:58.61#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.02:00:58.61#ibcon#enter wrdev, iclass 19, count 0 2006.173.02:00:58.61#ibcon#first serial, iclass 19, count 0 2006.173.02:00:58.61#ibcon#enter sib2, iclass 19, count 0 2006.173.02:00:58.61#ibcon#flushed, iclass 19, count 0 2006.173.02:00:58.61#ibcon#about to write, iclass 19, count 0 2006.173.02:00:58.61#ibcon#wrote, iclass 19, count 0 2006.173.02:00:58.61#ibcon#about to read 3, iclass 19, count 0 2006.173.02:00:58.63#ibcon#read 3, iclass 19, count 0 2006.173.02:00:58.63#ibcon#about to read 4, iclass 19, count 0 2006.173.02:00:58.63#ibcon#read 4, iclass 19, count 0 2006.173.02:00:58.63#ibcon#about to read 5, iclass 19, count 0 2006.173.02:00:58.63#ibcon#read 5, iclass 19, count 0 2006.173.02:00:58.63#ibcon#about to read 6, iclass 19, count 0 2006.173.02:00:58.63#ibcon#read 6, iclass 19, count 0 2006.173.02:00:58.63#ibcon#end of sib2, iclass 19, count 0 2006.173.02:00:58.63#ibcon#*mode == 0, iclass 19, count 0 2006.173.02:00:58.63#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.02:00:58.63#ibcon#[27=USB\r\n] 2006.173.02:00:58.63#ibcon#*before write, iclass 19, count 0 2006.173.02:00:58.63#ibcon#enter sib2, iclass 19, count 0 2006.173.02:00:58.63#ibcon#flushed, iclass 19, count 0 2006.173.02:00:58.63#ibcon#about to write, iclass 19, count 0 2006.173.02:00:58.63#ibcon#wrote, iclass 19, count 0 2006.173.02:00:58.63#ibcon#about to read 3, iclass 19, count 0 2006.173.02:00:58.66#ibcon#read 3, iclass 19, count 0 2006.173.02:00:58.66#ibcon#about to read 4, iclass 19, count 0 2006.173.02:00:58.66#ibcon#read 4, iclass 19, count 0 2006.173.02:00:58.66#ibcon#about to read 5, iclass 19, count 0 2006.173.02:00:58.66#ibcon#read 5, iclass 19, count 0 2006.173.02:00:58.66#ibcon#about to read 6, iclass 19, count 0 2006.173.02:00:58.66#ibcon#read 6, iclass 19, count 0 2006.173.02:00:58.66#ibcon#end of sib2, iclass 19, count 0 2006.173.02:00:58.66#ibcon#*after write, iclass 19, count 0 2006.173.02:00:58.66#ibcon#*before return 0, iclass 19, count 0 2006.173.02:00:58.66#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.02:00:58.66#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.02:00:58.66#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.02:00:58.66#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.02:00:58.66$vck44/vblo=2,634.99 2006.173.02:00:58.66#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.02:00:58.66#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.02:00:58.66#ibcon#ireg 17 cls_cnt 0 2006.173.02:00:58.66#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.02:00:58.66#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.02:00:58.66#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.02:00:58.66#ibcon#enter wrdev, iclass 21, count 0 2006.173.02:00:58.66#ibcon#first serial, iclass 21, count 0 2006.173.02:00:58.66#ibcon#enter sib2, iclass 21, count 0 2006.173.02:00:58.66#ibcon#flushed, iclass 21, count 0 2006.173.02:00:58.66#ibcon#about to write, iclass 21, count 0 2006.173.02:00:58.66#ibcon#wrote, iclass 21, count 0 2006.173.02:00:58.66#ibcon#about to read 3, iclass 21, count 0 2006.173.02:00:58.68#ibcon#read 3, iclass 21, count 0 2006.173.02:00:58.68#ibcon#about to read 4, iclass 21, count 0 2006.173.02:00:58.68#ibcon#read 4, iclass 21, count 0 2006.173.02:00:58.68#ibcon#about to read 5, iclass 21, count 0 2006.173.02:00:58.68#ibcon#read 5, iclass 21, count 0 2006.173.02:00:58.68#ibcon#about to read 6, iclass 21, count 0 2006.173.02:00:58.68#ibcon#read 6, iclass 21, count 0 2006.173.02:00:58.68#ibcon#end of sib2, iclass 21, count 0 2006.173.02:00:58.68#ibcon#*mode == 0, iclass 21, count 0 2006.173.02:00:58.68#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.02:00:58.68#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.02:00:58.68#ibcon#*before write, iclass 21, count 0 2006.173.02:00:58.68#ibcon#enter sib2, iclass 21, count 0 2006.173.02:00:58.68#ibcon#flushed, iclass 21, count 0 2006.173.02:00:58.68#ibcon#about to write, iclass 21, count 0 2006.173.02:00:58.68#ibcon#wrote, iclass 21, count 0 2006.173.02:00:58.68#ibcon#about to read 3, iclass 21, count 0 2006.173.02:00:58.72#ibcon#read 3, iclass 21, count 0 2006.173.02:00:58.72#ibcon#about to read 4, iclass 21, count 0 2006.173.02:00:58.72#ibcon#read 4, iclass 21, count 0 2006.173.02:00:58.72#ibcon#about to read 5, iclass 21, count 0 2006.173.02:00:58.72#ibcon#read 5, iclass 21, count 0 2006.173.02:00:58.72#ibcon#about to read 6, iclass 21, count 0 2006.173.02:00:58.72#ibcon#read 6, iclass 21, count 0 2006.173.02:00:58.72#ibcon#end of sib2, iclass 21, count 0 2006.173.02:00:58.72#ibcon#*after write, iclass 21, count 0 2006.173.02:00:58.72#ibcon#*before return 0, iclass 21, count 0 2006.173.02:00:58.72#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.02:00:58.72#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.02:00:58.72#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.02:00:58.72#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.02:00:58.72$vck44/vb=2,4 2006.173.02:00:58.72#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.02:00:58.72#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.02:00:58.72#ibcon#ireg 11 cls_cnt 2 2006.173.02:00:58.72#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.02:00:58.78#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.02:00:58.78#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.02:00:58.78#ibcon#enter wrdev, iclass 23, count 2 2006.173.02:00:58.78#ibcon#first serial, iclass 23, count 2 2006.173.02:00:58.78#ibcon#enter sib2, iclass 23, count 2 2006.173.02:00:58.78#ibcon#flushed, iclass 23, count 2 2006.173.02:00:58.78#ibcon#about to write, iclass 23, count 2 2006.173.02:00:58.78#ibcon#wrote, iclass 23, count 2 2006.173.02:00:58.78#ibcon#about to read 3, iclass 23, count 2 2006.173.02:00:58.80#ibcon#read 3, iclass 23, count 2 2006.173.02:00:58.80#ibcon#about to read 4, iclass 23, count 2 2006.173.02:00:58.80#ibcon#read 4, iclass 23, count 2 2006.173.02:00:58.80#ibcon#about to read 5, iclass 23, count 2 2006.173.02:00:58.80#ibcon#read 5, iclass 23, count 2 2006.173.02:00:58.80#ibcon#about to read 6, iclass 23, count 2 2006.173.02:00:58.80#ibcon#read 6, iclass 23, count 2 2006.173.02:00:58.80#ibcon#end of sib2, iclass 23, count 2 2006.173.02:00:58.80#ibcon#*mode == 0, iclass 23, count 2 2006.173.02:00:58.80#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.02:00:58.80#ibcon#[27=AT02-04\r\n] 2006.173.02:00:58.80#ibcon#*before write, iclass 23, count 2 2006.173.02:00:58.80#ibcon#enter sib2, iclass 23, count 2 2006.173.02:00:58.80#ibcon#flushed, iclass 23, count 2 2006.173.02:00:58.80#ibcon#about to write, iclass 23, count 2 2006.173.02:00:58.80#ibcon#wrote, iclass 23, count 2 2006.173.02:00:58.80#ibcon#about to read 3, iclass 23, count 2 2006.173.02:00:58.83#ibcon#read 3, iclass 23, count 2 2006.173.02:00:58.83#ibcon#about to read 4, iclass 23, count 2 2006.173.02:00:58.83#ibcon#read 4, iclass 23, count 2 2006.173.02:00:58.83#ibcon#about to read 5, iclass 23, count 2 2006.173.02:00:58.83#ibcon#read 5, iclass 23, count 2 2006.173.02:00:58.83#ibcon#about to read 6, iclass 23, count 2 2006.173.02:00:58.83#ibcon#read 6, iclass 23, count 2 2006.173.02:00:58.83#ibcon#end of sib2, iclass 23, count 2 2006.173.02:00:58.83#ibcon#*after write, iclass 23, count 2 2006.173.02:00:58.83#ibcon#*before return 0, iclass 23, count 2 2006.173.02:00:58.83#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.02:00:58.83#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.02:00:58.83#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.02:00:58.83#ibcon#ireg 7 cls_cnt 0 2006.173.02:00:58.83#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.02:00:58.95#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.02:00:58.95#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.02:00:58.95#ibcon#enter wrdev, iclass 23, count 0 2006.173.02:00:58.95#ibcon#first serial, iclass 23, count 0 2006.173.02:00:58.95#ibcon#enter sib2, iclass 23, count 0 2006.173.02:00:58.95#ibcon#flushed, iclass 23, count 0 2006.173.02:00:58.95#ibcon#about to write, iclass 23, count 0 2006.173.02:00:58.95#ibcon#wrote, iclass 23, count 0 2006.173.02:00:58.95#ibcon#about to read 3, iclass 23, count 0 2006.173.02:00:58.97#ibcon#read 3, iclass 23, count 0 2006.173.02:00:58.97#ibcon#about to read 4, iclass 23, count 0 2006.173.02:00:58.97#ibcon#read 4, iclass 23, count 0 2006.173.02:00:58.97#ibcon#about to read 5, iclass 23, count 0 2006.173.02:00:58.97#ibcon#read 5, iclass 23, count 0 2006.173.02:00:58.97#ibcon#about to read 6, iclass 23, count 0 2006.173.02:00:58.97#ibcon#read 6, iclass 23, count 0 2006.173.02:00:58.97#ibcon#end of sib2, iclass 23, count 0 2006.173.02:00:58.97#ibcon#*mode == 0, iclass 23, count 0 2006.173.02:00:58.97#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.02:00:58.97#ibcon#[27=USB\r\n] 2006.173.02:00:58.97#ibcon#*before write, iclass 23, count 0 2006.173.02:00:58.97#ibcon#enter sib2, iclass 23, count 0 2006.173.02:00:58.97#ibcon#flushed, iclass 23, count 0 2006.173.02:00:58.97#ibcon#about to write, iclass 23, count 0 2006.173.02:00:58.97#ibcon#wrote, iclass 23, count 0 2006.173.02:00:58.97#ibcon#about to read 3, iclass 23, count 0 2006.173.02:00:59.00#ibcon#read 3, iclass 23, count 0 2006.173.02:00:59.00#ibcon#about to read 4, iclass 23, count 0 2006.173.02:00:59.00#ibcon#read 4, iclass 23, count 0 2006.173.02:00:59.00#ibcon#about to read 5, iclass 23, count 0 2006.173.02:00:59.00#ibcon#read 5, iclass 23, count 0 2006.173.02:00:59.00#ibcon#about to read 6, iclass 23, count 0 2006.173.02:00:59.00#ibcon#read 6, iclass 23, count 0 2006.173.02:00:59.00#ibcon#end of sib2, iclass 23, count 0 2006.173.02:00:59.00#ibcon#*after write, iclass 23, count 0 2006.173.02:00:59.00#ibcon#*before return 0, iclass 23, count 0 2006.173.02:00:59.00#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.02:00:59.00#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.02:00:59.00#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.02:00:59.00#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.02:00:59.00$vck44/vblo=3,649.99 2006.173.02:00:59.00#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.02:00:59.00#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.02:00:59.00#ibcon#ireg 17 cls_cnt 0 2006.173.02:00:59.00#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.02:00:59.00#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.02:00:59.00#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.02:00:59.00#ibcon#enter wrdev, iclass 25, count 0 2006.173.02:00:59.00#ibcon#first serial, iclass 25, count 0 2006.173.02:00:59.00#ibcon#enter sib2, iclass 25, count 0 2006.173.02:00:59.00#ibcon#flushed, iclass 25, count 0 2006.173.02:00:59.00#ibcon#about to write, iclass 25, count 0 2006.173.02:00:59.00#ibcon#wrote, iclass 25, count 0 2006.173.02:00:59.00#ibcon#about to read 3, iclass 25, count 0 2006.173.02:00:59.02#ibcon#read 3, iclass 25, count 0 2006.173.02:00:59.02#ibcon#about to read 4, iclass 25, count 0 2006.173.02:00:59.02#ibcon#read 4, iclass 25, count 0 2006.173.02:00:59.02#ibcon#about to read 5, iclass 25, count 0 2006.173.02:00:59.02#ibcon#read 5, iclass 25, count 0 2006.173.02:00:59.02#ibcon#about to read 6, iclass 25, count 0 2006.173.02:00:59.02#ibcon#read 6, iclass 25, count 0 2006.173.02:00:59.02#ibcon#end of sib2, iclass 25, count 0 2006.173.02:00:59.02#ibcon#*mode == 0, iclass 25, count 0 2006.173.02:00:59.02#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.02:00:59.02#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.02:00:59.02#ibcon#*before write, iclass 25, count 0 2006.173.02:00:59.02#ibcon#enter sib2, iclass 25, count 0 2006.173.02:00:59.02#ibcon#flushed, iclass 25, count 0 2006.173.02:00:59.02#ibcon#about to write, iclass 25, count 0 2006.173.02:00:59.02#ibcon#wrote, iclass 25, count 0 2006.173.02:00:59.02#ibcon#about to read 3, iclass 25, count 0 2006.173.02:00:59.06#ibcon#read 3, iclass 25, count 0 2006.173.02:00:59.06#ibcon#about to read 4, iclass 25, count 0 2006.173.02:00:59.06#ibcon#read 4, iclass 25, count 0 2006.173.02:00:59.06#ibcon#about to read 5, iclass 25, count 0 2006.173.02:00:59.06#ibcon#read 5, iclass 25, count 0 2006.173.02:00:59.06#ibcon#about to read 6, iclass 25, count 0 2006.173.02:00:59.06#ibcon#read 6, iclass 25, count 0 2006.173.02:00:59.06#ibcon#end of sib2, iclass 25, count 0 2006.173.02:00:59.06#ibcon#*after write, iclass 25, count 0 2006.173.02:00:59.06#ibcon#*before return 0, iclass 25, count 0 2006.173.02:00:59.06#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.02:00:59.06#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.02:00:59.06#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.02:00:59.06#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.02:00:59.06$vck44/vb=3,4 2006.173.02:00:59.06#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.02:00:59.06#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.02:00:59.06#ibcon#ireg 11 cls_cnt 2 2006.173.02:00:59.06#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.02:00:59.12#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.02:00:59.12#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.02:00:59.12#ibcon#enter wrdev, iclass 27, count 2 2006.173.02:00:59.12#ibcon#first serial, iclass 27, count 2 2006.173.02:00:59.12#ibcon#enter sib2, iclass 27, count 2 2006.173.02:00:59.12#ibcon#flushed, iclass 27, count 2 2006.173.02:00:59.12#ibcon#about to write, iclass 27, count 2 2006.173.02:00:59.12#ibcon#wrote, iclass 27, count 2 2006.173.02:00:59.12#ibcon#about to read 3, iclass 27, count 2 2006.173.02:00:59.14#ibcon#read 3, iclass 27, count 2 2006.173.02:00:59.14#ibcon#about to read 4, iclass 27, count 2 2006.173.02:00:59.14#ibcon#read 4, iclass 27, count 2 2006.173.02:00:59.14#ibcon#about to read 5, iclass 27, count 2 2006.173.02:00:59.14#ibcon#read 5, iclass 27, count 2 2006.173.02:00:59.14#ibcon#about to read 6, iclass 27, count 2 2006.173.02:00:59.14#ibcon#read 6, iclass 27, count 2 2006.173.02:00:59.14#ibcon#end of sib2, iclass 27, count 2 2006.173.02:00:59.14#ibcon#*mode == 0, iclass 27, count 2 2006.173.02:00:59.14#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.02:00:59.14#ibcon#[27=AT03-04\r\n] 2006.173.02:00:59.14#ibcon#*before write, iclass 27, count 2 2006.173.02:00:59.14#ibcon#enter sib2, iclass 27, count 2 2006.173.02:00:59.14#ibcon#flushed, iclass 27, count 2 2006.173.02:00:59.14#ibcon#about to write, iclass 27, count 2 2006.173.02:00:59.14#ibcon#wrote, iclass 27, count 2 2006.173.02:00:59.14#ibcon#about to read 3, iclass 27, count 2 2006.173.02:00:59.17#ibcon#read 3, iclass 27, count 2 2006.173.02:00:59.17#ibcon#about to read 4, iclass 27, count 2 2006.173.02:00:59.17#ibcon#read 4, iclass 27, count 2 2006.173.02:00:59.17#ibcon#about to read 5, iclass 27, count 2 2006.173.02:00:59.17#ibcon#read 5, iclass 27, count 2 2006.173.02:00:59.17#ibcon#about to read 6, iclass 27, count 2 2006.173.02:00:59.17#ibcon#read 6, iclass 27, count 2 2006.173.02:00:59.17#ibcon#end of sib2, iclass 27, count 2 2006.173.02:00:59.17#ibcon#*after write, iclass 27, count 2 2006.173.02:00:59.17#ibcon#*before return 0, iclass 27, count 2 2006.173.02:00:59.17#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.02:00:59.17#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.02:00:59.17#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.02:00:59.17#ibcon#ireg 7 cls_cnt 0 2006.173.02:00:59.17#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.02:00:59.29#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.02:00:59.29#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.02:00:59.29#ibcon#enter wrdev, iclass 27, count 0 2006.173.02:00:59.29#ibcon#first serial, iclass 27, count 0 2006.173.02:00:59.29#ibcon#enter sib2, iclass 27, count 0 2006.173.02:00:59.29#ibcon#flushed, iclass 27, count 0 2006.173.02:00:59.29#ibcon#about to write, iclass 27, count 0 2006.173.02:00:59.29#ibcon#wrote, iclass 27, count 0 2006.173.02:00:59.29#ibcon#about to read 3, iclass 27, count 0 2006.173.02:00:59.31#ibcon#read 3, iclass 27, count 0 2006.173.02:00:59.31#ibcon#about to read 4, iclass 27, count 0 2006.173.02:00:59.31#ibcon#read 4, iclass 27, count 0 2006.173.02:00:59.31#ibcon#about to read 5, iclass 27, count 0 2006.173.02:00:59.31#ibcon#read 5, iclass 27, count 0 2006.173.02:00:59.31#ibcon#about to read 6, iclass 27, count 0 2006.173.02:00:59.31#ibcon#read 6, iclass 27, count 0 2006.173.02:00:59.31#ibcon#end of sib2, iclass 27, count 0 2006.173.02:00:59.31#ibcon#*mode == 0, iclass 27, count 0 2006.173.02:00:59.31#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.02:00:59.31#ibcon#[27=USB\r\n] 2006.173.02:00:59.31#ibcon#*before write, iclass 27, count 0 2006.173.02:00:59.31#ibcon#enter sib2, iclass 27, count 0 2006.173.02:00:59.31#ibcon#flushed, iclass 27, count 0 2006.173.02:00:59.31#ibcon#about to write, iclass 27, count 0 2006.173.02:00:59.31#ibcon#wrote, iclass 27, count 0 2006.173.02:00:59.31#ibcon#about to read 3, iclass 27, count 0 2006.173.02:00:59.34#ibcon#read 3, iclass 27, count 0 2006.173.02:00:59.34#ibcon#about to read 4, iclass 27, count 0 2006.173.02:00:59.34#ibcon#read 4, iclass 27, count 0 2006.173.02:00:59.34#ibcon#about to read 5, iclass 27, count 0 2006.173.02:00:59.34#ibcon#read 5, iclass 27, count 0 2006.173.02:00:59.34#ibcon#about to read 6, iclass 27, count 0 2006.173.02:00:59.34#ibcon#read 6, iclass 27, count 0 2006.173.02:00:59.34#ibcon#end of sib2, iclass 27, count 0 2006.173.02:00:59.34#ibcon#*after write, iclass 27, count 0 2006.173.02:00:59.34#ibcon#*before return 0, iclass 27, count 0 2006.173.02:00:59.34#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.02:00:59.34#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.02:00:59.34#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.02:00:59.34#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.02:00:59.34$vck44/vblo=4,679.99 2006.173.02:00:59.34#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.02:00:59.34#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.02:00:59.34#ibcon#ireg 17 cls_cnt 0 2006.173.02:00:59.34#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.02:00:59.34#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.02:00:59.34#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.02:00:59.34#ibcon#enter wrdev, iclass 29, count 0 2006.173.02:00:59.34#ibcon#first serial, iclass 29, count 0 2006.173.02:00:59.34#ibcon#enter sib2, iclass 29, count 0 2006.173.02:00:59.34#ibcon#flushed, iclass 29, count 0 2006.173.02:00:59.34#ibcon#about to write, iclass 29, count 0 2006.173.02:00:59.34#ibcon#wrote, iclass 29, count 0 2006.173.02:00:59.34#ibcon#about to read 3, iclass 29, count 0 2006.173.02:00:59.36#ibcon#read 3, iclass 29, count 0 2006.173.02:00:59.36#ibcon#about to read 4, iclass 29, count 0 2006.173.02:00:59.36#ibcon#read 4, iclass 29, count 0 2006.173.02:00:59.36#ibcon#about to read 5, iclass 29, count 0 2006.173.02:00:59.36#ibcon#read 5, iclass 29, count 0 2006.173.02:00:59.36#ibcon#about to read 6, iclass 29, count 0 2006.173.02:00:59.36#ibcon#read 6, iclass 29, count 0 2006.173.02:00:59.36#ibcon#end of sib2, iclass 29, count 0 2006.173.02:00:59.36#ibcon#*mode == 0, iclass 29, count 0 2006.173.02:00:59.36#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.02:00:59.36#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.02:00:59.36#ibcon#*before write, iclass 29, count 0 2006.173.02:00:59.36#ibcon#enter sib2, iclass 29, count 0 2006.173.02:00:59.36#ibcon#flushed, iclass 29, count 0 2006.173.02:00:59.36#ibcon#about to write, iclass 29, count 0 2006.173.02:00:59.36#ibcon#wrote, iclass 29, count 0 2006.173.02:00:59.36#ibcon#about to read 3, iclass 29, count 0 2006.173.02:00:59.40#ibcon#read 3, iclass 29, count 0 2006.173.02:00:59.40#ibcon#about to read 4, iclass 29, count 0 2006.173.02:00:59.40#ibcon#read 4, iclass 29, count 0 2006.173.02:00:59.40#ibcon#about to read 5, iclass 29, count 0 2006.173.02:00:59.40#ibcon#read 5, iclass 29, count 0 2006.173.02:00:59.40#ibcon#about to read 6, iclass 29, count 0 2006.173.02:00:59.40#ibcon#read 6, iclass 29, count 0 2006.173.02:00:59.40#ibcon#end of sib2, iclass 29, count 0 2006.173.02:00:59.40#ibcon#*after write, iclass 29, count 0 2006.173.02:00:59.40#ibcon#*before return 0, iclass 29, count 0 2006.173.02:00:59.40#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.02:00:59.40#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.02:00:59.40#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.02:00:59.40#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.02:00:59.40$vck44/vb=4,4 2006.173.02:00:59.40#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.02:00:59.40#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.02:00:59.40#ibcon#ireg 11 cls_cnt 2 2006.173.02:00:59.40#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.02:00:59.46#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.02:00:59.46#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.02:00:59.46#ibcon#enter wrdev, iclass 31, count 2 2006.173.02:00:59.46#ibcon#first serial, iclass 31, count 2 2006.173.02:00:59.46#ibcon#enter sib2, iclass 31, count 2 2006.173.02:00:59.46#ibcon#flushed, iclass 31, count 2 2006.173.02:00:59.46#ibcon#about to write, iclass 31, count 2 2006.173.02:00:59.46#ibcon#wrote, iclass 31, count 2 2006.173.02:00:59.46#ibcon#about to read 3, iclass 31, count 2 2006.173.02:00:59.48#ibcon#read 3, iclass 31, count 2 2006.173.02:00:59.48#ibcon#about to read 4, iclass 31, count 2 2006.173.02:00:59.48#ibcon#read 4, iclass 31, count 2 2006.173.02:00:59.48#ibcon#about to read 5, iclass 31, count 2 2006.173.02:00:59.48#ibcon#read 5, iclass 31, count 2 2006.173.02:00:59.48#ibcon#about to read 6, iclass 31, count 2 2006.173.02:00:59.48#ibcon#read 6, iclass 31, count 2 2006.173.02:00:59.48#ibcon#end of sib2, iclass 31, count 2 2006.173.02:00:59.48#ibcon#*mode == 0, iclass 31, count 2 2006.173.02:00:59.48#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.02:00:59.48#ibcon#[27=AT04-04\r\n] 2006.173.02:00:59.48#ibcon#*before write, iclass 31, count 2 2006.173.02:00:59.48#ibcon#enter sib2, iclass 31, count 2 2006.173.02:00:59.48#ibcon#flushed, iclass 31, count 2 2006.173.02:00:59.48#ibcon#about to write, iclass 31, count 2 2006.173.02:00:59.48#ibcon#wrote, iclass 31, count 2 2006.173.02:00:59.48#ibcon#about to read 3, iclass 31, count 2 2006.173.02:00:59.51#ibcon#read 3, iclass 31, count 2 2006.173.02:00:59.51#ibcon#about to read 4, iclass 31, count 2 2006.173.02:00:59.51#ibcon#read 4, iclass 31, count 2 2006.173.02:00:59.51#ibcon#about to read 5, iclass 31, count 2 2006.173.02:00:59.51#ibcon#read 5, iclass 31, count 2 2006.173.02:00:59.51#ibcon#about to read 6, iclass 31, count 2 2006.173.02:00:59.51#ibcon#read 6, iclass 31, count 2 2006.173.02:00:59.51#ibcon#end of sib2, iclass 31, count 2 2006.173.02:00:59.51#ibcon#*after write, iclass 31, count 2 2006.173.02:00:59.51#ibcon#*before return 0, iclass 31, count 2 2006.173.02:00:59.51#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.02:00:59.51#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.02:00:59.51#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.02:00:59.51#ibcon#ireg 7 cls_cnt 0 2006.173.02:00:59.51#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.02:00:59.55#abcon#<5=/13 1.1 2.7 22.63 831006.7\r\n> 2006.173.02:00:59.57#abcon#{5=INTERFACE CLEAR} 2006.173.02:00:59.63#abcon#[5=S1D000X0/0*\r\n] 2006.173.02:00:59.63#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.02:00:59.63#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.02:00:59.63#ibcon#enter wrdev, iclass 31, count 0 2006.173.02:00:59.63#ibcon#first serial, iclass 31, count 0 2006.173.02:00:59.63#ibcon#enter sib2, iclass 31, count 0 2006.173.02:00:59.63#ibcon#flushed, iclass 31, count 0 2006.173.02:00:59.63#ibcon#about to write, iclass 31, count 0 2006.173.02:00:59.63#ibcon#wrote, iclass 31, count 0 2006.173.02:00:59.63#ibcon#about to read 3, iclass 31, count 0 2006.173.02:00:59.65#ibcon#read 3, iclass 31, count 0 2006.173.02:00:59.65#ibcon#about to read 4, iclass 31, count 0 2006.173.02:00:59.65#ibcon#read 4, iclass 31, count 0 2006.173.02:00:59.65#ibcon#about to read 5, iclass 31, count 0 2006.173.02:00:59.65#ibcon#read 5, iclass 31, count 0 2006.173.02:00:59.65#ibcon#about to read 6, iclass 31, count 0 2006.173.02:00:59.65#ibcon#read 6, iclass 31, count 0 2006.173.02:00:59.65#ibcon#end of sib2, iclass 31, count 0 2006.173.02:00:59.65#ibcon#*mode == 0, iclass 31, count 0 2006.173.02:00:59.65#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.02:00:59.65#ibcon#[27=USB\r\n] 2006.173.02:00:59.65#ibcon#*before write, iclass 31, count 0 2006.173.02:00:59.65#ibcon#enter sib2, iclass 31, count 0 2006.173.02:00:59.65#ibcon#flushed, iclass 31, count 0 2006.173.02:00:59.65#ibcon#about to write, iclass 31, count 0 2006.173.02:00:59.65#ibcon#wrote, iclass 31, count 0 2006.173.02:00:59.65#ibcon#about to read 3, iclass 31, count 0 2006.173.02:00:59.68#ibcon#read 3, iclass 31, count 0 2006.173.02:00:59.68#ibcon#about to read 4, iclass 31, count 0 2006.173.02:00:59.68#ibcon#read 4, iclass 31, count 0 2006.173.02:00:59.68#ibcon#about to read 5, iclass 31, count 0 2006.173.02:00:59.68#ibcon#read 5, iclass 31, count 0 2006.173.02:00:59.68#ibcon#about to read 6, iclass 31, count 0 2006.173.02:00:59.68#ibcon#read 6, iclass 31, count 0 2006.173.02:00:59.68#ibcon#end of sib2, iclass 31, count 0 2006.173.02:00:59.68#ibcon#*after write, iclass 31, count 0 2006.173.02:00:59.68#ibcon#*before return 0, iclass 31, count 0 2006.173.02:00:59.68#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.02:00:59.68#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.02:00:59.68#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.02:00:59.68#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.02:00:59.68$vck44/vblo=5,709.99 2006.173.02:00:59.68#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.02:00:59.68#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.02:00:59.68#ibcon#ireg 17 cls_cnt 0 2006.173.02:00:59.68#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.02:00:59.68#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.02:00:59.68#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.02:00:59.68#ibcon#enter wrdev, iclass 37, count 0 2006.173.02:00:59.68#ibcon#first serial, iclass 37, count 0 2006.173.02:00:59.68#ibcon#enter sib2, iclass 37, count 0 2006.173.02:00:59.68#ibcon#flushed, iclass 37, count 0 2006.173.02:00:59.68#ibcon#about to write, iclass 37, count 0 2006.173.02:00:59.68#ibcon#wrote, iclass 37, count 0 2006.173.02:00:59.68#ibcon#about to read 3, iclass 37, count 0 2006.173.02:00:59.70#ibcon#read 3, iclass 37, count 0 2006.173.02:00:59.70#ibcon#about to read 4, iclass 37, count 0 2006.173.02:00:59.70#ibcon#read 4, iclass 37, count 0 2006.173.02:00:59.70#ibcon#about to read 5, iclass 37, count 0 2006.173.02:00:59.70#ibcon#read 5, iclass 37, count 0 2006.173.02:00:59.70#ibcon#about to read 6, iclass 37, count 0 2006.173.02:00:59.70#ibcon#read 6, iclass 37, count 0 2006.173.02:00:59.70#ibcon#end of sib2, iclass 37, count 0 2006.173.02:00:59.70#ibcon#*mode == 0, iclass 37, count 0 2006.173.02:00:59.70#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.02:00:59.70#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.02:00:59.70#ibcon#*before write, iclass 37, count 0 2006.173.02:00:59.70#ibcon#enter sib2, iclass 37, count 0 2006.173.02:00:59.70#ibcon#flushed, iclass 37, count 0 2006.173.02:00:59.70#ibcon#about to write, iclass 37, count 0 2006.173.02:00:59.70#ibcon#wrote, iclass 37, count 0 2006.173.02:00:59.70#ibcon#about to read 3, iclass 37, count 0 2006.173.02:00:59.74#ibcon#read 3, iclass 37, count 0 2006.173.02:00:59.74#ibcon#about to read 4, iclass 37, count 0 2006.173.02:00:59.74#ibcon#read 4, iclass 37, count 0 2006.173.02:00:59.74#ibcon#about to read 5, iclass 37, count 0 2006.173.02:00:59.74#ibcon#read 5, iclass 37, count 0 2006.173.02:00:59.74#ibcon#about to read 6, iclass 37, count 0 2006.173.02:00:59.74#ibcon#read 6, iclass 37, count 0 2006.173.02:00:59.74#ibcon#end of sib2, iclass 37, count 0 2006.173.02:00:59.74#ibcon#*after write, iclass 37, count 0 2006.173.02:00:59.74#ibcon#*before return 0, iclass 37, count 0 2006.173.02:00:59.74#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.02:00:59.74#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.02:00:59.74#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.02:00:59.74#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.02:00:59.74$vck44/vb=5,4 2006.173.02:00:59.74#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.02:00:59.74#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.02:00:59.74#ibcon#ireg 11 cls_cnt 2 2006.173.02:00:59.74#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.02:00:59.80#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.02:00:59.80#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.02:00:59.80#ibcon#enter wrdev, iclass 39, count 2 2006.173.02:00:59.80#ibcon#first serial, iclass 39, count 2 2006.173.02:00:59.80#ibcon#enter sib2, iclass 39, count 2 2006.173.02:00:59.80#ibcon#flushed, iclass 39, count 2 2006.173.02:00:59.80#ibcon#about to write, iclass 39, count 2 2006.173.02:00:59.80#ibcon#wrote, iclass 39, count 2 2006.173.02:00:59.80#ibcon#about to read 3, iclass 39, count 2 2006.173.02:00:59.82#ibcon#read 3, iclass 39, count 2 2006.173.02:00:59.82#ibcon#about to read 4, iclass 39, count 2 2006.173.02:00:59.82#ibcon#read 4, iclass 39, count 2 2006.173.02:00:59.82#ibcon#about to read 5, iclass 39, count 2 2006.173.02:00:59.82#ibcon#read 5, iclass 39, count 2 2006.173.02:00:59.82#ibcon#about to read 6, iclass 39, count 2 2006.173.02:00:59.82#ibcon#read 6, iclass 39, count 2 2006.173.02:00:59.82#ibcon#end of sib2, iclass 39, count 2 2006.173.02:00:59.82#ibcon#*mode == 0, iclass 39, count 2 2006.173.02:00:59.82#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.02:00:59.82#ibcon#[27=AT05-04\r\n] 2006.173.02:00:59.82#ibcon#*before write, iclass 39, count 2 2006.173.02:00:59.82#ibcon#enter sib2, iclass 39, count 2 2006.173.02:00:59.82#ibcon#flushed, iclass 39, count 2 2006.173.02:00:59.82#ibcon#about to write, iclass 39, count 2 2006.173.02:00:59.82#ibcon#wrote, iclass 39, count 2 2006.173.02:00:59.82#ibcon#about to read 3, iclass 39, count 2 2006.173.02:00:59.85#ibcon#read 3, iclass 39, count 2 2006.173.02:00:59.85#ibcon#about to read 4, iclass 39, count 2 2006.173.02:00:59.85#ibcon#read 4, iclass 39, count 2 2006.173.02:00:59.85#ibcon#about to read 5, iclass 39, count 2 2006.173.02:00:59.85#ibcon#read 5, iclass 39, count 2 2006.173.02:00:59.85#ibcon#about to read 6, iclass 39, count 2 2006.173.02:00:59.85#ibcon#read 6, iclass 39, count 2 2006.173.02:00:59.85#ibcon#end of sib2, iclass 39, count 2 2006.173.02:00:59.85#ibcon#*after write, iclass 39, count 2 2006.173.02:00:59.85#ibcon#*before return 0, iclass 39, count 2 2006.173.02:00:59.85#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.02:00:59.85#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.02:00:59.85#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.02:00:59.85#ibcon#ireg 7 cls_cnt 0 2006.173.02:00:59.85#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.02:00:59.97#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.02:00:59.97#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.02:00:59.97#ibcon#enter wrdev, iclass 39, count 0 2006.173.02:00:59.97#ibcon#first serial, iclass 39, count 0 2006.173.02:00:59.97#ibcon#enter sib2, iclass 39, count 0 2006.173.02:00:59.97#ibcon#flushed, iclass 39, count 0 2006.173.02:00:59.97#ibcon#about to write, iclass 39, count 0 2006.173.02:00:59.97#ibcon#wrote, iclass 39, count 0 2006.173.02:00:59.97#ibcon#about to read 3, iclass 39, count 0 2006.173.02:00:59.99#ibcon#read 3, iclass 39, count 0 2006.173.02:00:59.99#ibcon#about to read 4, iclass 39, count 0 2006.173.02:00:59.99#ibcon#read 4, iclass 39, count 0 2006.173.02:00:59.99#ibcon#about to read 5, iclass 39, count 0 2006.173.02:00:59.99#ibcon#read 5, iclass 39, count 0 2006.173.02:00:59.99#ibcon#about to read 6, iclass 39, count 0 2006.173.02:00:59.99#ibcon#read 6, iclass 39, count 0 2006.173.02:00:59.99#ibcon#end of sib2, iclass 39, count 0 2006.173.02:00:59.99#ibcon#*mode == 0, iclass 39, count 0 2006.173.02:00:59.99#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.02:00:59.99#ibcon#[27=USB\r\n] 2006.173.02:00:59.99#ibcon#*before write, iclass 39, count 0 2006.173.02:00:59.99#ibcon#enter sib2, iclass 39, count 0 2006.173.02:00:59.99#ibcon#flushed, iclass 39, count 0 2006.173.02:00:59.99#ibcon#about to write, iclass 39, count 0 2006.173.02:00:59.99#ibcon#wrote, iclass 39, count 0 2006.173.02:00:59.99#ibcon#about to read 3, iclass 39, count 0 2006.173.02:01:00.02#ibcon#read 3, iclass 39, count 0 2006.173.02:01:00.02#ibcon#about to read 4, iclass 39, count 0 2006.173.02:01:00.02#ibcon#read 4, iclass 39, count 0 2006.173.02:01:00.02#ibcon#about to read 5, iclass 39, count 0 2006.173.02:01:00.02#ibcon#read 5, iclass 39, count 0 2006.173.02:01:00.02#ibcon#about to read 6, iclass 39, count 0 2006.173.02:01:00.02#ibcon#read 6, iclass 39, count 0 2006.173.02:01:00.02#ibcon#end of sib2, iclass 39, count 0 2006.173.02:01:00.02#ibcon#*after write, iclass 39, count 0 2006.173.02:01:00.02#ibcon#*before return 0, iclass 39, count 0 2006.173.02:01:00.02#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.02:01:00.02#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.02:01:00.02#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.02:01:00.02#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.02:01:00.02$vck44/vblo=6,719.99 2006.173.02:01:00.02#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.02:01:00.02#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.02:01:00.02#ibcon#ireg 17 cls_cnt 0 2006.173.02:01:00.02#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.02:01:00.02#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.02:01:00.02#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.02:01:00.02#ibcon#enter wrdev, iclass 3, count 0 2006.173.02:01:00.02#ibcon#first serial, iclass 3, count 0 2006.173.02:01:00.02#ibcon#enter sib2, iclass 3, count 0 2006.173.02:01:00.02#ibcon#flushed, iclass 3, count 0 2006.173.02:01:00.02#ibcon#about to write, iclass 3, count 0 2006.173.02:01:00.02#ibcon#wrote, iclass 3, count 0 2006.173.02:01:00.02#ibcon#about to read 3, iclass 3, count 0 2006.173.02:01:00.04#ibcon#read 3, iclass 3, count 0 2006.173.02:01:00.04#ibcon#about to read 4, iclass 3, count 0 2006.173.02:01:00.04#ibcon#read 4, iclass 3, count 0 2006.173.02:01:00.04#ibcon#about to read 5, iclass 3, count 0 2006.173.02:01:00.04#ibcon#read 5, iclass 3, count 0 2006.173.02:01:00.04#ibcon#about to read 6, iclass 3, count 0 2006.173.02:01:00.04#ibcon#read 6, iclass 3, count 0 2006.173.02:01:00.04#ibcon#end of sib2, iclass 3, count 0 2006.173.02:01:00.04#ibcon#*mode == 0, iclass 3, count 0 2006.173.02:01:00.04#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.02:01:00.04#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.02:01:00.04#ibcon#*before write, iclass 3, count 0 2006.173.02:01:00.04#ibcon#enter sib2, iclass 3, count 0 2006.173.02:01:00.04#ibcon#flushed, iclass 3, count 0 2006.173.02:01:00.04#ibcon#about to write, iclass 3, count 0 2006.173.02:01:00.04#ibcon#wrote, iclass 3, count 0 2006.173.02:01:00.04#ibcon#about to read 3, iclass 3, count 0 2006.173.02:01:00.08#ibcon#read 3, iclass 3, count 0 2006.173.02:01:00.08#ibcon#about to read 4, iclass 3, count 0 2006.173.02:01:00.08#ibcon#read 4, iclass 3, count 0 2006.173.02:01:00.08#ibcon#about to read 5, iclass 3, count 0 2006.173.02:01:00.08#ibcon#read 5, iclass 3, count 0 2006.173.02:01:00.08#ibcon#about to read 6, iclass 3, count 0 2006.173.02:01:00.08#ibcon#read 6, iclass 3, count 0 2006.173.02:01:00.08#ibcon#end of sib2, iclass 3, count 0 2006.173.02:01:00.08#ibcon#*after write, iclass 3, count 0 2006.173.02:01:00.08#ibcon#*before return 0, iclass 3, count 0 2006.173.02:01:00.08#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.02:01:00.08#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.02:01:00.08#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.02:01:00.08#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.02:01:00.08$vck44/vb=6,4 2006.173.02:01:00.08#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.02:01:00.08#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.02:01:00.08#ibcon#ireg 11 cls_cnt 2 2006.173.02:01:00.08#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.02:01:00.14#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.02:01:00.14#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.02:01:00.14#ibcon#enter wrdev, iclass 5, count 2 2006.173.02:01:00.14#ibcon#first serial, iclass 5, count 2 2006.173.02:01:00.14#ibcon#enter sib2, iclass 5, count 2 2006.173.02:01:00.14#ibcon#flushed, iclass 5, count 2 2006.173.02:01:00.14#ibcon#about to write, iclass 5, count 2 2006.173.02:01:00.14#ibcon#wrote, iclass 5, count 2 2006.173.02:01:00.14#ibcon#about to read 3, iclass 5, count 2 2006.173.02:01:00.16#ibcon#read 3, iclass 5, count 2 2006.173.02:01:00.16#ibcon#about to read 4, iclass 5, count 2 2006.173.02:01:00.16#ibcon#read 4, iclass 5, count 2 2006.173.02:01:00.16#ibcon#about to read 5, iclass 5, count 2 2006.173.02:01:00.16#ibcon#read 5, iclass 5, count 2 2006.173.02:01:00.16#ibcon#about to read 6, iclass 5, count 2 2006.173.02:01:00.16#ibcon#read 6, iclass 5, count 2 2006.173.02:01:00.16#ibcon#end of sib2, iclass 5, count 2 2006.173.02:01:00.16#ibcon#*mode == 0, iclass 5, count 2 2006.173.02:01:00.16#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.02:01:00.16#ibcon#[27=AT06-04\r\n] 2006.173.02:01:00.16#ibcon#*before write, iclass 5, count 2 2006.173.02:01:00.16#ibcon#enter sib2, iclass 5, count 2 2006.173.02:01:00.16#ibcon#flushed, iclass 5, count 2 2006.173.02:01:00.16#ibcon#about to write, iclass 5, count 2 2006.173.02:01:00.16#ibcon#wrote, iclass 5, count 2 2006.173.02:01:00.16#ibcon#about to read 3, iclass 5, count 2 2006.173.02:01:00.19#ibcon#read 3, iclass 5, count 2 2006.173.02:01:00.19#ibcon#about to read 4, iclass 5, count 2 2006.173.02:01:00.19#ibcon#read 4, iclass 5, count 2 2006.173.02:01:00.19#ibcon#about to read 5, iclass 5, count 2 2006.173.02:01:00.19#ibcon#read 5, iclass 5, count 2 2006.173.02:01:00.19#ibcon#about to read 6, iclass 5, count 2 2006.173.02:01:00.19#ibcon#read 6, iclass 5, count 2 2006.173.02:01:00.19#ibcon#end of sib2, iclass 5, count 2 2006.173.02:01:00.19#ibcon#*after write, iclass 5, count 2 2006.173.02:01:00.19#ibcon#*before return 0, iclass 5, count 2 2006.173.02:01:00.19#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.02:01:00.19#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.02:01:00.19#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.02:01:00.19#ibcon#ireg 7 cls_cnt 0 2006.173.02:01:00.19#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.02:01:00.31#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.02:01:00.31#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.02:01:00.31#ibcon#enter wrdev, iclass 5, count 0 2006.173.02:01:00.31#ibcon#first serial, iclass 5, count 0 2006.173.02:01:00.31#ibcon#enter sib2, iclass 5, count 0 2006.173.02:01:00.31#ibcon#flushed, iclass 5, count 0 2006.173.02:01:00.31#ibcon#about to write, iclass 5, count 0 2006.173.02:01:00.31#ibcon#wrote, iclass 5, count 0 2006.173.02:01:00.31#ibcon#about to read 3, iclass 5, count 0 2006.173.02:01:00.33#ibcon#read 3, iclass 5, count 0 2006.173.02:01:00.33#ibcon#about to read 4, iclass 5, count 0 2006.173.02:01:00.33#ibcon#read 4, iclass 5, count 0 2006.173.02:01:00.33#ibcon#about to read 5, iclass 5, count 0 2006.173.02:01:00.33#ibcon#read 5, iclass 5, count 0 2006.173.02:01:00.33#ibcon#about to read 6, iclass 5, count 0 2006.173.02:01:00.33#ibcon#read 6, iclass 5, count 0 2006.173.02:01:00.33#ibcon#end of sib2, iclass 5, count 0 2006.173.02:01:00.33#ibcon#*mode == 0, iclass 5, count 0 2006.173.02:01:00.33#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.02:01:00.33#ibcon#[27=USB\r\n] 2006.173.02:01:00.33#ibcon#*before write, iclass 5, count 0 2006.173.02:01:00.33#ibcon#enter sib2, iclass 5, count 0 2006.173.02:01:00.33#ibcon#flushed, iclass 5, count 0 2006.173.02:01:00.33#ibcon#about to write, iclass 5, count 0 2006.173.02:01:00.33#ibcon#wrote, iclass 5, count 0 2006.173.02:01:00.33#ibcon#about to read 3, iclass 5, count 0 2006.173.02:01:00.36#ibcon#read 3, iclass 5, count 0 2006.173.02:01:00.36#ibcon#about to read 4, iclass 5, count 0 2006.173.02:01:00.36#ibcon#read 4, iclass 5, count 0 2006.173.02:01:00.36#ibcon#about to read 5, iclass 5, count 0 2006.173.02:01:00.36#ibcon#read 5, iclass 5, count 0 2006.173.02:01:00.36#ibcon#about to read 6, iclass 5, count 0 2006.173.02:01:00.36#ibcon#read 6, iclass 5, count 0 2006.173.02:01:00.36#ibcon#end of sib2, iclass 5, count 0 2006.173.02:01:00.36#ibcon#*after write, iclass 5, count 0 2006.173.02:01:00.36#ibcon#*before return 0, iclass 5, count 0 2006.173.02:01:00.36#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.02:01:00.36#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.02:01:00.36#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.02:01:00.36#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.02:01:00.36$vck44/vblo=7,734.99 2006.173.02:01:00.36#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.02:01:00.36#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.02:01:00.36#ibcon#ireg 17 cls_cnt 0 2006.173.02:01:00.36#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.02:01:00.36#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.02:01:00.36#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.02:01:00.36#ibcon#enter wrdev, iclass 7, count 0 2006.173.02:01:00.36#ibcon#first serial, iclass 7, count 0 2006.173.02:01:00.36#ibcon#enter sib2, iclass 7, count 0 2006.173.02:01:00.36#ibcon#flushed, iclass 7, count 0 2006.173.02:01:00.36#ibcon#about to write, iclass 7, count 0 2006.173.02:01:00.36#ibcon#wrote, iclass 7, count 0 2006.173.02:01:00.36#ibcon#about to read 3, iclass 7, count 0 2006.173.02:01:00.38#ibcon#read 3, iclass 7, count 0 2006.173.02:01:00.38#ibcon#about to read 4, iclass 7, count 0 2006.173.02:01:00.38#ibcon#read 4, iclass 7, count 0 2006.173.02:01:00.38#ibcon#about to read 5, iclass 7, count 0 2006.173.02:01:00.38#ibcon#read 5, iclass 7, count 0 2006.173.02:01:00.38#ibcon#about to read 6, iclass 7, count 0 2006.173.02:01:00.38#ibcon#read 6, iclass 7, count 0 2006.173.02:01:00.38#ibcon#end of sib2, iclass 7, count 0 2006.173.02:01:00.38#ibcon#*mode == 0, iclass 7, count 0 2006.173.02:01:00.38#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.02:01:00.38#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.02:01:00.38#ibcon#*before write, iclass 7, count 0 2006.173.02:01:00.38#ibcon#enter sib2, iclass 7, count 0 2006.173.02:01:00.38#ibcon#flushed, iclass 7, count 0 2006.173.02:01:00.38#ibcon#about to write, iclass 7, count 0 2006.173.02:01:00.38#ibcon#wrote, iclass 7, count 0 2006.173.02:01:00.38#ibcon#about to read 3, iclass 7, count 0 2006.173.02:01:00.42#ibcon#read 3, iclass 7, count 0 2006.173.02:01:00.42#ibcon#about to read 4, iclass 7, count 0 2006.173.02:01:00.42#ibcon#read 4, iclass 7, count 0 2006.173.02:01:00.42#ibcon#about to read 5, iclass 7, count 0 2006.173.02:01:00.42#ibcon#read 5, iclass 7, count 0 2006.173.02:01:00.42#ibcon#about to read 6, iclass 7, count 0 2006.173.02:01:00.42#ibcon#read 6, iclass 7, count 0 2006.173.02:01:00.42#ibcon#end of sib2, iclass 7, count 0 2006.173.02:01:00.42#ibcon#*after write, iclass 7, count 0 2006.173.02:01:00.42#ibcon#*before return 0, iclass 7, count 0 2006.173.02:01:00.42#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.02:01:00.42#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.02:01:00.42#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.02:01:00.42#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.02:01:00.42$vck44/vb=7,4 2006.173.02:01:00.42#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.02:01:00.42#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.02:01:00.42#ibcon#ireg 11 cls_cnt 2 2006.173.02:01:00.42#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.02:01:00.48#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.02:01:00.48#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.02:01:00.48#ibcon#enter wrdev, iclass 11, count 2 2006.173.02:01:00.48#ibcon#first serial, iclass 11, count 2 2006.173.02:01:00.48#ibcon#enter sib2, iclass 11, count 2 2006.173.02:01:00.48#ibcon#flushed, iclass 11, count 2 2006.173.02:01:00.48#ibcon#about to write, iclass 11, count 2 2006.173.02:01:00.48#ibcon#wrote, iclass 11, count 2 2006.173.02:01:00.48#ibcon#about to read 3, iclass 11, count 2 2006.173.02:01:00.50#ibcon#read 3, iclass 11, count 2 2006.173.02:01:00.50#ibcon#about to read 4, iclass 11, count 2 2006.173.02:01:00.50#ibcon#read 4, iclass 11, count 2 2006.173.02:01:00.50#ibcon#about to read 5, iclass 11, count 2 2006.173.02:01:00.50#ibcon#read 5, iclass 11, count 2 2006.173.02:01:00.50#ibcon#about to read 6, iclass 11, count 2 2006.173.02:01:00.50#ibcon#read 6, iclass 11, count 2 2006.173.02:01:00.50#ibcon#end of sib2, iclass 11, count 2 2006.173.02:01:00.50#ibcon#*mode == 0, iclass 11, count 2 2006.173.02:01:00.50#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.02:01:00.50#ibcon#[27=AT07-04\r\n] 2006.173.02:01:00.50#ibcon#*before write, iclass 11, count 2 2006.173.02:01:00.50#ibcon#enter sib2, iclass 11, count 2 2006.173.02:01:00.50#ibcon#flushed, iclass 11, count 2 2006.173.02:01:00.50#ibcon#about to write, iclass 11, count 2 2006.173.02:01:00.50#ibcon#wrote, iclass 11, count 2 2006.173.02:01:00.50#ibcon#about to read 3, iclass 11, count 2 2006.173.02:01:00.53#ibcon#read 3, iclass 11, count 2 2006.173.02:01:00.53#ibcon#about to read 4, iclass 11, count 2 2006.173.02:01:00.53#ibcon#read 4, iclass 11, count 2 2006.173.02:01:00.53#ibcon#about to read 5, iclass 11, count 2 2006.173.02:01:00.53#ibcon#read 5, iclass 11, count 2 2006.173.02:01:00.53#ibcon#about to read 6, iclass 11, count 2 2006.173.02:01:00.53#ibcon#read 6, iclass 11, count 2 2006.173.02:01:00.53#ibcon#end of sib2, iclass 11, count 2 2006.173.02:01:00.53#ibcon#*after write, iclass 11, count 2 2006.173.02:01:00.53#ibcon#*before return 0, iclass 11, count 2 2006.173.02:01:00.53#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.02:01:00.53#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.02:01:00.53#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.02:01:00.53#ibcon#ireg 7 cls_cnt 0 2006.173.02:01:00.53#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.02:01:00.65#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.02:01:00.65#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.02:01:00.65#ibcon#enter wrdev, iclass 11, count 0 2006.173.02:01:00.65#ibcon#first serial, iclass 11, count 0 2006.173.02:01:00.65#ibcon#enter sib2, iclass 11, count 0 2006.173.02:01:00.65#ibcon#flushed, iclass 11, count 0 2006.173.02:01:00.65#ibcon#about to write, iclass 11, count 0 2006.173.02:01:00.65#ibcon#wrote, iclass 11, count 0 2006.173.02:01:00.65#ibcon#about to read 3, iclass 11, count 0 2006.173.02:01:00.67#ibcon#read 3, iclass 11, count 0 2006.173.02:01:00.67#ibcon#about to read 4, iclass 11, count 0 2006.173.02:01:00.67#ibcon#read 4, iclass 11, count 0 2006.173.02:01:00.67#ibcon#about to read 5, iclass 11, count 0 2006.173.02:01:00.67#ibcon#read 5, iclass 11, count 0 2006.173.02:01:00.67#ibcon#about to read 6, iclass 11, count 0 2006.173.02:01:00.67#ibcon#read 6, iclass 11, count 0 2006.173.02:01:00.67#ibcon#end of sib2, iclass 11, count 0 2006.173.02:01:00.67#ibcon#*mode == 0, iclass 11, count 0 2006.173.02:01:00.67#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.02:01:00.67#ibcon#[27=USB\r\n] 2006.173.02:01:00.67#ibcon#*before write, iclass 11, count 0 2006.173.02:01:00.67#ibcon#enter sib2, iclass 11, count 0 2006.173.02:01:00.67#ibcon#flushed, iclass 11, count 0 2006.173.02:01:00.67#ibcon#about to write, iclass 11, count 0 2006.173.02:01:00.67#ibcon#wrote, iclass 11, count 0 2006.173.02:01:00.67#ibcon#about to read 3, iclass 11, count 0 2006.173.02:01:00.70#ibcon#read 3, iclass 11, count 0 2006.173.02:01:00.70#ibcon#about to read 4, iclass 11, count 0 2006.173.02:01:00.70#ibcon#read 4, iclass 11, count 0 2006.173.02:01:00.70#ibcon#about to read 5, iclass 11, count 0 2006.173.02:01:00.70#ibcon#read 5, iclass 11, count 0 2006.173.02:01:00.70#ibcon#about to read 6, iclass 11, count 0 2006.173.02:01:00.70#ibcon#read 6, iclass 11, count 0 2006.173.02:01:00.70#ibcon#end of sib2, iclass 11, count 0 2006.173.02:01:00.70#ibcon#*after write, iclass 11, count 0 2006.173.02:01:00.70#ibcon#*before return 0, iclass 11, count 0 2006.173.02:01:00.70#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.02:01:00.70#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.02:01:00.70#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.02:01:00.70#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.02:01:00.70$vck44/vblo=8,744.99 2006.173.02:01:00.70#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.02:01:00.70#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.02:01:00.70#ibcon#ireg 17 cls_cnt 0 2006.173.02:01:00.70#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.02:01:00.70#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.02:01:00.70#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.02:01:00.70#ibcon#enter wrdev, iclass 13, count 0 2006.173.02:01:00.70#ibcon#first serial, iclass 13, count 0 2006.173.02:01:00.70#ibcon#enter sib2, iclass 13, count 0 2006.173.02:01:00.70#ibcon#flushed, iclass 13, count 0 2006.173.02:01:00.70#ibcon#about to write, iclass 13, count 0 2006.173.02:01:00.70#ibcon#wrote, iclass 13, count 0 2006.173.02:01:00.70#ibcon#about to read 3, iclass 13, count 0 2006.173.02:01:00.72#ibcon#read 3, iclass 13, count 0 2006.173.02:01:00.72#ibcon#about to read 4, iclass 13, count 0 2006.173.02:01:00.72#ibcon#read 4, iclass 13, count 0 2006.173.02:01:00.72#ibcon#about to read 5, iclass 13, count 0 2006.173.02:01:00.72#ibcon#read 5, iclass 13, count 0 2006.173.02:01:00.72#ibcon#about to read 6, iclass 13, count 0 2006.173.02:01:00.72#ibcon#read 6, iclass 13, count 0 2006.173.02:01:00.72#ibcon#end of sib2, iclass 13, count 0 2006.173.02:01:00.72#ibcon#*mode == 0, iclass 13, count 0 2006.173.02:01:00.72#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.02:01:00.72#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.02:01:00.72#ibcon#*before write, iclass 13, count 0 2006.173.02:01:00.72#ibcon#enter sib2, iclass 13, count 0 2006.173.02:01:00.72#ibcon#flushed, iclass 13, count 0 2006.173.02:01:00.72#ibcon#about to write, iclass 13, count 0 2006.173.02:01:00.72#ibcon#wrote, iclass 13, count 0 2006.173.02:01:00.72#ibcon#about to read 3, iclass 13, count 0 2006.173.02:01:00.76#ibcon#read 3, iclass 13, count 0 2006.173.02:01:00.76#ibcon#about to read 4, iclass 13, count 0 2006.173.02:01:00.76#ibcon#read 4, iclass 13, count 0 2006.173.02:01:00.76#ibcon#about to read 5, iclass 13, count 0 2006.173.02:01:00.76#ibcon#read 5, iclass 13, count 0 2006.173.02:01:00.76#ibcon#about to read 6, iclass 13, count 0 2006.173.02:01:00.76#ibcon#read 6, iclass 13, count 0 2006.173.02:01:00.76#ibcon#end of sib2, iclass 13, count 0 2006.173.02:01:00.76#ibcon#*after write, iclass 13, count 0 2006.173.02:01:00.76#ibcon#*before return 0, iclass 13, count 0 2006.173.02:01:00.76#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.02:01:00.76#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.02:01:00.76#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.02:01:00.76#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.02:01:00.76$vck44/vb=8,4 2006.173.02:01:00.76#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.02:01:00.76#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.02:01:00.76#ibcon#ireg 11 cls_cnt 2 2006.173.02:01:00.76#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.02:01:00.82#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.02:01:00.82#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.02:01:00.82#ibcon#enter wrdev, iclass 15, count 2 2006.173.02:01:00.82#ibcon#first serial, iclass 15, count 2 2006.173.02:01:00.82#ibcon#enter sib2, iclass 15, count 2 2006.173.02:01:00.82#ibcon#flushed, iclass 15, count 2 2006.173.02:01:00.82#ibcon#about to write, iclass 15, count 2 2006.173.02:01:00.82#ibcon#wrote, iclass 15, count 2 2006.173.02:01:00.82#ibcon#about to read 3, iclass 15, count 2 2006.173.02:01:00.84#ibcon#read 3, iclass 15, count 2 2006.173.02:01:00.84#ibcon#about to read 4, iclass 15, count 2 2006.173.02:01:00.84#ibcon#read 4, iclass 15, count 2 2006.173.02:01:00.84#ibcon#about to read 5, iclass 15, count 2 2006.173.02:01:00.84#ibcon#read 5, iclass 15, count 2 2006.173.02:01:00.84#ibcon#about to read 6, iclass 15, count 2 2006.173.02:01:00.84#ibcon#read 6, iclass 15, count 2 2006.173.02:01:00.84#ibcon#end of sib2, iclass 15, count 2 2006.173.02:01:00.84#ibcon#*mode == 0, iclass 15, count 2 2006.173.02:01:00.84#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.02:01:00.84#ibcon#[27=AT08-04\r\n] 2006.173.02:01:00.84#ibcon#*before write, iclass 15, count 2 2006.173.02:01:00.84#ibcon#enter sib2, iclass 15, count 2 2006.173.02:01:00.84#ibcon#flushed, iclass 15, count 2 2006.173.02:01:00.84#ibcon#about to write, iclass 15, count 2 2006.173.02:01:00.84#ibcon#wrote, iclass 15, count 2 2006.173.02:01:00.84#ibcon#about to read 3, iclass 15, count 2 2006.173.02:01:00.87#ibcon#read 3, iclass 15, count 2 2006.173.02:01:00.87#ibcon#about to read 4, iclass 15, count 2 2006.173.02:01:00.87#ibcon#read 4, iclass 15, count 2 2006.173.02:01:00.87#ibcon#about to read 5, iclass 15, count 2 2006.173.02:01:00.87#ibcon#read 5, iclass 15, count 2 2006.173.02:01:00.87#ibcon#about to read 6, iclass 15, count 2 2006.173.02:01:00.87#ibcon#read 6, iclass 15, count 2 2006.173.02:01:00.87#ibcon#end of sib2, iclass 15, count 2 2006.173.02:01:00.87#ibcon#*after write, iclass 15, count 2 2006.173.02:01:00.87#ibcon#*before return 0, iclass 15, count 2 2006.173.02:01:00.87#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.02:01:00.87#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.02:01:00.87#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.02:01:00.87#ibcon#ireg 7 cls_cnt 0 2006.173.02:01:00.87#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.02:01:00.99#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.02:01:00.99#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.02:01:00.99#ibcon#enter wrdev, iclass 15, count 0 2006.173.02:01:00.99#ibcon#first serial, iclass 15, count 0 2006.173.02:01:00.99#ibcon#enter sib2, iclass 15, count 0 2006.173.02:01:00.99#ibcon#flushed, iclass 15, count 0 2006.173.02:01:00.99#ibcon#about to write, iclass 15, count 0 2006.173.02:01:00.99#ibcon#wrote, iclass 15, count 0 2006.173.02:01:00.99#ibcon#about to read 3, iclass 15, count 0 2006.173.02:01:01.01#ibcon#read 3, iclass 15, count 0 2006.173.02:01:01.01#ibcon#about to read 4, iclass 15, count 0 2006.173.02:01:01.01#ibcon#read 4, iclass 15, count 0 2006.173.02:01:01.01#ibcon#about to read 5, iclass 15, count 0 2006.173.02:01:01.01#ibcon#read 5, iclass 15, count 0 2006.173.02:01:01.01#ibcon#about to read 6, iclass 15, count 0 2006.173.02:01:01.01#ibcon#read 6, iclass 15, count 0 2006.173.02:01:01.01#ibcon#end of sib2, iclass 15, count 0 2006.173.02:01:01.01#ibcon#*mode == 0, iclass 15, count 0 2006.173.02:01:01.01#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.02:01:01.01#ibcon#[27=USB\r\n] 2006.173.02:01:01.01#ibcon#*before write, iclass 15, count 0 2006.173.02:01:01.01#ibcon#enter sib2, iclass 15, count 0 2006.173.02:01:01.01#ibcon#flushed, iclass 15, count 0 2006.173.02:01:01.01#ibcon#about to write, iclass 15, count 0 2006.173.02:01:01.01#ibcon#wrote, iclass 15, count 0 2006.173.02:01:01.01#ibcon#about to read 3, iclass 15, count 0 2006.173.02:01:01.04#ibcon#read 3, iclass 15, count 0 2006.173.02:01:01.04#ibcon#about to read 4, iclass 15, count 0 2006.173.02:01:01.04#ibcon#read 4, iclass 15, count 0 2006.173.02:01:01.04#ibcon#about to read 5, iclass 15, count 0 2006.173.02:01:01.04#ibcon#read 5, iclass 15, count 0 2006.173.02:01:01.04#ibcon#about to read 6, iclass 15, count 0 2006.173.02:01:01.04#ibcon#read 6, iclass 15, count 0 2006.173.02:01:01.04#ibcon#end of sib2, iclass 15, count 0 2006.173.02:01:01.04#ibcon#*after write, iclass 15, count 0 2006.173.02:01:01.04#ibcon#*before return 0, iclass 15, count 0 2006.173.02:01:01.04#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.02:01:01.04#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.02:01:01.04#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.02:01:01.04#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.02:01:01.04$vck44/vabw=wide 2006.173.02:01:01.04#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.02:01:01.04#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.02:01:01.04#ibcon#ireg 8 cls_cnt 0 2006.173.02:01:01.04#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.02:01:01.04#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.02:01:01.04#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.02:01:01.04#ibcon#enter wrdev, iclass 17, count 0 2006.173.02:01:01.04#ibcon#first serial, iclass 17, count 0 2006.173.02:01:01.04#ibcon#enter sib2, iclass 17, count 0 2006.173.02:01:01.04#ibcon#flushed, iclass 17, count 0 2006.173.02:01:01.04#ibcon#about to write, iclass 17, count 0 2006.173.02:01:01.04#ibcon#wrote, iclass 17, count 0 2006.173.02:01:01.04#ibcon#about to read 3, iclass 17, count 0 2006.173.02:01:01.06#ibcon#read 3, iclass 17, count 0 2006.173.02:01:01.06#ibcon#about to read 4, iclass 17, count 0 2006.173.02:01:01.06#ibcon#read 4, iclass 17, count 0 2006.173.02:01:01.06#ibcon#about to read 5, iclass 17, count 0 2006.173.02:01:01.06#ibcon#read 5, iclass 17, count 0 2006.173.02:01:01.06#ibcon#about to read 6, iclass 17, count 0 2006.173.02:01:01.06#ibcon#read 6, iclass 17, count 0 2006.173.02:01:01.06#ibcon#end of sib2, iclass 17, count 0 2006.173.02:01:01.06#ibcon#*mode == 0, iclass 17, count 0 2006.173.02:01:01.06#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.02:01:01.06#ibcon#[25=BW32\r\n] 2006.173.02:01:01.06#ibcon#*before write, iclass 17, count 0 2006.173.02:01:01.06#ibcon#enter sib2, iclass 17, count 0 2006.173.02:01:01.06#ibcon#flushed, iclass 17, count 0 2006.173.02:01:01.06#ibcon#about to write, iclass 17, count 0 2006.173.02:01:01.06#ibcon#wrote, iclass 17, count 0 2006.173.02:01:01.06#ibcon#about to read 3, iclass 17, count 0 2006.173.02:01:01.09#ibcon#read 3, iclass 17, count 0 2006.173.02:01:01.09#ibcon#about to read 4, iclass 17, count 0 2006.173.02:01:01.09#ibcon#read 4, iclass 17, count 0 2006.173.02:01:01.09#ibcon#about to read 5, iclass 17, count 0 2006.173.02:01:01.09#ibcon#read 5, iclass 17, count 0 2006.173.02:01:01.09#ibcon#about to read 6, iclass 17, count 0 2006.173.02:01:01.09#ibcon#read 6, iclass 17, count 0 2006.173.02:01:01.09#ibcon#end of sib2, iclass 17, count 0 2006.173.02:01:01.09#ibcon#*after write, iclass 17, count 0 2006.173.02:01:01.09#ibcon#*before return 0, iclass 17, count 0 2006.173.02:01:01.09#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.02:01:01.09#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.02:01:01.09#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.02:01:01.09#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.02:01:01.09$vck44/vbbw=wide 2006.173.02:01:01.09#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.02:01:01.09#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.02:01:01.09#ibcon#ireg 8 cls_cnt 0 2006.173.02:01:01.09#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.02:01:01.16#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.02:01:01.16#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.02:01:01.16#ibcon#enter wrdev, iclass 19, count 0 2006.173.02:01:01.16#ibcon#first serial, iclass 19, count 0 2006.173.02:01:01.16#ibcon#enter sib2, iclass 19, count 0 2006.173.02:01:01.16#ibcon#flushed, iclass 19, count 0 2006.173.02:01:01.16#ibcon#about to write, iclass 19, count 0 2006.173.02:01:01.16#ibcon#wrote, iclass 19, count 0 2006.173.02:01:01.16#ibcon#about to read 3, iclass 19, count 0 2006.173.02:01:01.18#ibcon#read 3, iclass 19, count 0 2006.173.02:01:01.18#ibcon#about to read 4, iclass 19, count 0 2006.173.02:01:01.18#ibcon#read 4, iclass 19, count 0 2006.173.02:01:01.18#ibcon#about to read 5, iclass 19, count 0 2006.173.02:01:01.18#ibcon#read 5, iclass 19, count 0 2006.173.02:01:01.18#ibcon#about to read 6, iclass 19, count 0 2006.173.02:01:01.18#ibcon#read 6, iclass 19, count 0 2006.173.02:01:01.18#ibcon#end of sib2, iclass 19, count 0 2006.173.02:01:01.18#ibcon#*mode == 0, iclass 19, count 0 2006.173.02:01:01.18#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.02:01:01.18#ibcon#[27=BW32\r\n] 2006.173.02:01:01.18#ibcon#*before write, iclass 19, count 0 2006.173.02:01:01.18#ibcon#enter sib2, iclass 19, count 0 2006.173.02:01:01.18#ibcon#flushed, iclass 19, count 0 2006.173.02:01:01.18#ibcon#about to write, iclass 19, count 0 2006.173.02:01:01.18#ibcon#wrote, iclass 19, count 0 2006.173.02:01:01.18#ibcon#about to read 3, iclass 19, count 0 2006.173.02:01:01.21#ibcon#read 3, iclass 19, count 0 2006.173.02:01:01.21#ibcon#about to read 4, iclass 19, count 0 2006.173.02:01:01.21#ibcon#read 4, iclass 19, count 0 2006.173.02:01:01.21#ibcon#about to read 5, iclass 19, count 0 2006.173.02:01:01.21#ibcon#read 5, iclass 19, count 0 2006.173.02:01:01.21#ibcon#about to read 6, iclass 19, count 0 2006.173.02:01:01.21#ibcon#read 6, iclass 19, count 0 2006.173.02:01:01.21#ibcon#end of sib2, iclass 19, count 0 2006.173.02:01:01.21#ibcon#*after write, iclass 19, count 0 2006.173.02:01:01.21#ibcon#*before return 0, iclass 19, count 0 2006.173.02:01:01.21#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.02:01:01.21#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.02:01:01.21#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.02:01:01.21#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.02:01:01.21$setupk4/ifdk4 2006.173.02:01:01.21$ifdk4/lo= 2006.173.02:01:01.21$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.02:01:01.21$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.02:01:01.21$ifdk4/patch= 2006.173.02:01:01.21$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.02:01:01.21$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.02:01:01.21$setupk4/!*+20s 2006.173.02:01:09.72#abcon#<5=/13 1.0 2.7 22.64 831006.7\r\n> 2006.173.02:01:09.74#abcon#{5=INTERFACE CLEAR} 2006.173.02:01:09.80#abcon#[5=S1D000X0/0*\r\n] 2006.173.02:01:15.64$setupk4/"tpicd 2006.173.02:01:15.64$setupk4/echo=off 2006.173.02:01:15.64$setupk4/xlog=off 2006.173.02:01:15.64:!2006.173.02:01:31 2006.173.02:01:28.13#trakl#Source acquired 2006.173.02:01:28.13#flagr#flagr/antenna,acquired 2006.173.02:01:31.00:preob 2006.173.02:01:32.13/onsource/TRACKING 2006.173.02:01:32.13:!2006.173.02:01:41 2006.173.02:01:41.00:"tape 2006.173.02:01:41.00:"st=record 2006.173.02:01:41.00:data_valid=on 2006.173.02:01:41.00:midob 2006.173.02:01:41.13/onsource/TRACKING 2006.173.02:01:41.13/wx/22.65,1006.7,81 2006.173.02:01:41.30/cable/+6.5140E-03 2006.173.02:01:42.39/va/01,07,usb,yes,44,47 2006.173.02:01:42.39/va/02,06,usb,yes,44,45 2006.173.02:01:42.39/va/03,05,usb,yes,55,57 2006.173.02:01:42.39/va/04,06,usb,yes,45,47 2006.173.02:01:42.39/va/05,04,usb,yes,35,36 2006.173.02:01:42.39/va/06,03,usb,yes,49,49 2006.173.02:01:42.39/va/07,04,usb,yes,40,42 2006.173.02:01:42.39/va/08,04,usb,yes,35,41 2006.173.02:01:42.62/valo/01,524.99,yes,locked 2006.173.02:01:42.62/valo/02,534.99,yes,locked 2006.173.02:01:42.62/valo/03,564.99,yes,locked 2006.173.02:01:42.62/valo/04,624.99,yes,locked 2006.173.02:01:42.62/valo/05,734.99,yes,locked 2006.173.02:01:42.62/valo/06,814.99,yes,locked 2006.173.02:01:42.62/valo/07,864.99,yes,locked 2006.173.02:01:42.62/valo/08,884.99,yes,locked 2006.173.02:01:43.71/vb/01,04,usb,yes,32,29 2006.173.02:01:43.71/vb/02,04,usb,yes,34,34 2006.173.02:01:43.71/vb/03,04,usb,yes,31,34 2006.173.02:01:43.71/vb/04,04,usb,yes,35,34 2006.173.02:01:43.71/vb/05,04,usb,yes,28,30 2006.173.02:01:43.71/vb/06,04,usb,yes,33,29 2006.173.02:01:43.71/vb/07,04,usb,yes,32,32 2006.173.02:01:43.71/vb/08,04,usb,yes,30,33 2006.173.02:01:43.94/vblo/01,629.99,yes,locked 2006.173.02:01:43.94/vblo/02,634.99,yes,locked 2006.173.02:01:43.94/vblo/03,649.99,yes,locked 2006.173.02:01:43.94/vblo/04,679.99,yes,locked 2006.173.02:01:43.94/vblo/05,709.99,yes,locked 2006.173.02:01:43.94/vblo/06,719.99,yes,locked 2006.173.02:01:43.94/vblo/07,734.99,yes,locked 2006.173.02:01:43.94/vblo/08,744.99,yes,locked 2006.173.02:01:44.09/vabw/8 2006.173.02:01:44.24/vbbw/8 2006.173.02:01:44.33/xfe/off,on,15.2 2006.173.02:01:44.70/ifatt/23,28,28,28 2006.173.02:01:45.08/fmout-gps/S +3.94E-07 2006.173.02:01:45.16:!2006.173.02:02:21 2006.173.02:02:21.00:data_valid=off 2006.173.02:02:21.00:"et 2006.173.02:02:21.00:!+3s 2006.173.02:02:24.02:"tape 2006.173.02:02:24.02:postob 2006.173.02:02:24.10/cable/+6.5129E-03 2006.173.02:02:24.10/wx/22.65,1006.7,81 2006.173.02:02:25.08/fmout-gps/S +3.94E-07 2006.173.02:02:25.08:scan_name=173-0205,jd0606,60 2006.173.02:02:25.08:source=0727-115,073019.11,-114112.6,2000.0,cw 2006.173.02:02:26.14#flagr#flagr/antenna,new-source 2006.173.02:02:26.14:checkk5 2006.173.02:02:26.56/chk_autoobs//k5ts1/ autoobs is running! 2006.173.02:02:26.98/chk_autoobs//k5ts2/ autoobs is running! 2006.173.02:02:27.60/chk_autoobs//k5ts3/ autoobs is running! 2006.173.02:02:28.04/chk_autoobs//k5ts4/ autoobs is running! 2006.173.02:02:28.44/chk_obsdata//k5ts1/T1730201??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.02:02:28.89/chk_obsdata//k5ts2/T1730201??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.02:02:29.34/chk_obsdata//k5ts3/T1730201??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.02:02:29.74/chk_obsdata//k5ts4/T1730201??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.02:02:30.56/k5log//k5ts1_log_newline 2006.173.02:02:31.33/k5log//k5ts2_log_newline 2006.173.02:02:32.12/k5log//k5ts3_log_newline 2006.173.02:02:32.89/k5log//k5ts4_log_newline 2006.173.02:02:32.91/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.02:02:32.91:setupk4=1 2006.173.02:02:32.91$setupk4/echo=on 2006.173.02:02:32.91$setupk4/pcalon 2006.173.02:02:32.91$pcalon/"no phase cal control is implemented here 2006.173.02:02:32.91$setupk4/"tpicd=stop 2006.173.02:02:32.91$setupk4/"rec=synch_on 2006.173.02:02:32.91$setupk4/"rec_mode=128 2006.173.02:02:32.91$setupk4/!* 2006.173.02:02:32.91$setupk4/recpk4 2006.173.02:02:32.92$recpk4/recpatch= 2006.173.02:02:32.92$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.02:02:32.92$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.02:02:32.92$setupk4/vck44 2006.173.02:02:32.92$vck44/valo=1,524.99 2006.173.02:02:32.92#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.02:02:32.92#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.02:02:32.92#ibcon#ireg 17 cls_cnt 0 2006.173.02:02:32.92#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.02:02:32.92#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.02:02:32.92#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.02:02:32.92#ibcon#enter wrdev, iclass 24, count 0 2006.173.02:02:32.92#ibcon#first serial, iclass 24, count 0 2006.173.02:02:32.92#ibcon#enter sib2, iclass 24, count 0 2006.173.02:02:32.92#ibcon#flushed, iclass 24, count 0 2006.173.02:02:32.92#ibcon#about to write, iclass 24, count 0 2006.173.02:02:32.92#ibcon#wrote, iclass 24, count 0 2006.173.02:02:32.92#ibcon#about to read 3, iclass 24, count 0 2006.173.02:02:32.97#ibcon#read 3, iclass 24, count 0 2006.173.02:02:32.97#ibcon#about to read 4, iclass 24, count 0 2006.173.02:02:32.97#ibcon#read 4, iclass 24, count 0 2006.173.02:02:32.97#ibcon#about to read 5, iclass 24, count 0 2006.173.02:02:32.97#ibcon#read 5, iclass 24, count 0 2006.173.02:02:32.97#ibcon#about to read 6, iclass 24, count 0 2006.173.02:02:32.97#ibcon#read 6, iclass 24, count 0 2006.173.02:02:32.97#ibcon#end of sib2, iclass 24, count 0 2006.173.02:02:32.97#ibcon#*mode == 0, iclass 24, count 0 2006.173.02:02:32.97#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.02:02:32.97#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.02:02:32.97#ibcon#*before write, iclass 24, count 0 2006.173.02:02:32.97#ibcon#enter sib2, iclass 24, count 0 2006.173.02:02:32.97#ibcon#flushed, iclass 24, count 0 2006.173.02:02:32.97#ibcon#about to write, iclass 24, count 0 2006.173.02:02:32.97#ibcon#wrote, iclass 24, count 0 2006.173.02:02:32.97#ibcon#about to read 3, iclass 24, count 0 2006.173.02:02:33.02#ibcon#read 3, iclass 24, count 0 2006.173.02:02:33.02#ibcon#about to read 4, iclass 24, count 0 2006.173.02:02:33.02#ibcon#read 4, iclass 24, count 0 2006.173.02:02:33.02#ibcon#about to read 5, iclass 24, count 0 2006.173.02:02:33.02#ibcon#read 5, iclass 24, count 0 2006.173.02:02:33.02#ibcon#about to read 6, iclass 24, count 0 2006.173.02:02:33.02#ibcon#read 6, iclass 24, count 0 2006.173.02:02:33.02#ibcon#end of sib2, iclass 24, count 0 2006.173.02:02:33.02#ibcon#*after write, iclass 24, count 0 2006.173.02:02:33.02#ibcon#*before return 0, iclass 24, count 0 2006.173.02:02:33.02#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.02:02:33.02#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.02:02:33.02#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.02:02:33.02#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.02:02:33.02$vck44/va=1,7 2006.173.02:02:33.02#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.02:02:33.02#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.02:02:33.02#ibcon#ireg 11 cls_cnt 2 2006.173.02:02:33.02#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.02:02:33.02#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.02:02:33.02#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.02:02:33.02#ibcon#enter wrdev, iclass 26, count 2 2006.173.02:02:33.02#ibcon#first serial, iclass 26, count 2 2006.173.02:02:33.02#ibcon#enter sib2, iclass 26, count 2 2006.173.02:02:33.02#ibcon#flushed, iclass 26, count 2 2006.173.02:02:33.02#ibcon#about to write, iclass 26, count 2 2006.173.02:02:33.02#ibcon#wrote, iclass 26, count 2 2006.173.02:02:33.02#ibcon#about to read 3, iclass 26, count 2 2006.173.02:02:33.04#ibcon#read 3, iclass 26, count 2 2006.173.02:02:33.04#ibcon#about to read 4, iclass 26, count 2 2006.173.02:02:33.04#ibcon#read 4, iclass 26, count 2 2006.173.02:02:33.04#ibcon#about to read 5, iclass 26, count 2 2006.173.02:02:33.04#ibcon#read 5, iclass 26, count 2 2006.173.02:02:33.04#ibcon#about to read 6, iclass 26, count 2 2006.173.02:02:33.04#ibcon#read 6, iclass 26, count 2 2006.173.02:02:33.04#ibcon#end of sib2, iclass 26, count 2 2006.173.02:02:33.04#ibcon#*mode == 0, iclass 26, count 2 2006.173.02:02:33.04#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.02:02:33.04#ibcon#[25=AT01-07\r\n] 2006.173.02:02:33.04#ibcon#*before write, iclass 26, count 2 2006.173.02:02:33.04#ibcon#enter sib2, iclass 26, count 2 2006.173.02:02:33.04#ibcon#flushed, iclass 26, count 2 2006.173.02:02:33.04#ibcon#about to write, iclass 26, count 2 2006.173.02:02:33.04#ibcon#wrote, iclass 26, count 2 2006.173.02:02:33.04#ibcon#about to read 3, iclass 26, count 2 2006.173.02:02:33.07#ibcon#read 3, iclass 26, count 2 2006.173.02:02:33.07#ibcon#about to read 4, iclass 26, count 2 2006.173.02:02:33.07#ibcon#read 4, iclass 26, count 2 2006.173.02:02:33.07#ibcon#about to read 5, iclass 26, count 2 2006.173.02:02:33.07#ibcon#read 5, iclass 26, count 2 2006.173.02:02:33.07#ibcon#about to read 6, iclass 26, count 2 2006.173.02:02:33.07#ibcon#read 6, iclass 26, count 2 2006.173.02:02:33.07#ibcon#end of sib2, iclass 26, count 2 2006.173.02:02:33.07#ibcon#*after write, iclass 26, count 2 2006.173.02:02:33.07#ibcon#*before return 0, iclass 26, count 2 2006.173.02:02:33.07#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.02:02:33.07#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.02:02:33.07#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.02:02:33.07#ibcon#ireg 7 cls_cnt 0 2006.173.02:02:33.07#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.02:02:33.19#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.02:02:33.19#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.02:02:33.19#ibcon#enter wrdev, iclass 26, count 0 2006.173.02:02:33.19#ibcon#first serial, iclass 26, count 0 2006.173.02:02:33.19#ibcon#enter sib2, iclass 26, count 0 2006.173.02:02:33.19#ibcon#flushed, iclass 26, count 0 2006.173.02:02:33.19#ibcon#about to write, iclass 26, count 0 2006.173.02:02:33.19#ibcon#wrote, iclass 26, count 0 2006.173.02:02:33.19#ibcon#about to read 3, iclass 26, count 0 2006.173.02:02:33.21#ibcon#read 3, iclass 26, count 0 2006.173.02:02:33.21#ibcon#about to read 4, iclass 26, count 0 2006.173.02:02:33.21#ibcon#read 4, iclass 26, count 0 2006.173.02:02:33.21#ibcon#about to read 5, iclass 26, count 0 2006.173.02:02:33.21#ibcon#read 5, iclass 26, count 0 2006.173.02:02:33.21#ibcon#about to read 6, iclass 26, count 0 2006.173.02:02:33.21#ibcon#read 6, iclass 26, count 0 2006.173.02:02:33.21#ibcon#end of sib2, iclass 26, count 0 2006.173.02:02:33.21#ibcon#*mode == 0, iclass 26, count 0 2006.173.02:02:33.21#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.02:02:33.21#ibcon#[25=USB\r\n] 2006.173.02:02:33.21#ibcon#*before write, iclass 26, count 0 2006.173.02:02:33.21#ibcon#enter sib2, iclass 26, count 0 2006.173.02:02:33.21#ibcon#flushed, iclass 26, count 0 2006.173.02:02:33.21#ibcon#about to write, iclass 26, count 0 2006.173.02:02:33.21#ibcon#wrote, iclass 26, count 0 2006.173.02:02:33.21#ibcon#about to read 3, iclass 26, count 0 2006.173.02:02:33.24#ibcon#read 3, iclass 26, count 0 2006.173.02:02:33.24#ibcon#about to read 4, iclass 26, count 0 2006.173.02:02:33.24#ibcon#read 4, iclass 26, count 0 2006.173.02:02:33.24#ibcon#about to read 5, iclass 26, count 0 2006.173.02:02:33.24#ibcon#read 5, iclass 26, count 0 2006.173.02:02:33.24#ibcon#about to read 6, iclass 26, count 0 2006.173.02:02:33.24#ibcon#read 6, iclass 26, count 0 2006.173.02:02:33.24#ibcon#end of sib2, iclass 26, count 0 2006.173.02:02:33.24#ibcon#*after write, iclass 26, count 0 2006.173.02:02:33.24#ibcon#*before return 0, iclass 26, count 0 2006.173.02:02:33.24#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.02:02:33.24#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.02:02:33.24#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.02:02:33.24#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.02:02:33.24$vck44/valo=2,534.99 2006.173.02:02:33.24#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.02:02:33.24#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.02:02:33.24#ibcon#ireg 17 cls_cnt 0 2006.173.02:02:33.24#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.02:02:33.24#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.02:02:33.24#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.02:02:33.24#ibcon#enter wrdev, iclass 28, count 0 2006.173.02:02:33.24#ibcon#first serial, iclass 28, count 0 2006.173.02:02:33.24#ibcon#enter sib2, iclass 28, count 0 2006.173.02:02:33.24#ibcon#flushed, iclass 28, count 0 2006.173.02:02:33.24#ibcon#about to write, iclass 28, count 0 2006.173.02:02:33.24#ibcon#wrote, iclass 28, count 0 2006.173.02:02:33.24#ibcon#about to read 3, iclass 28, count 0 2006.173.02:02:33.26#ibcon#read 3, iclass 28, count 0 2006.173.02:02:33.26#ibcon#about to read 4, iclass 28, count 0 2006.173.02:02:33.26#ibcon#read 4, iclass 28, count 0 2006.173.02:02:33.26#ibcon#about to read 5, iclass 28, count 0 2006.173.02:02:33.26#ibcon#read 5, iclass 28, count 0 2006.173.02:02:33.26#ibcon#about to read 6, iclass 28, count 0 2006.173.02:02:33.26#ibcon#read 6, iclass 28, count 0 2006.173.02:02:33.26#ibcon#end of sib2, iclass 28, count 0 2006.173.02:02:33.26#ibcon#*mode == 0, iclass 28, count 0 2006.173.02:02:33.26#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.02:02:33.26#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.02:02:33.26#ibcon#*before write, iclass 28, count 0 2006.173.02:02:33.26#ibcon#enter sib2, iclass 28, count 0 2006.173.02:02:33.26#ibcon#flushed, iclass 28, count 0 2006.173.02:02:33.26#ibcon#about to write, iclass 28, count 0 2006.173.02:02:33.26#ibcon#wrote, iclass 28, count 0 2006.173.02:02:33.26#ibcon#about to read 3, iclass 28, count 0 2006.173.02:02:33.30#ibcon#read 3, iclass 28, count 0 2006.173.02:02:33.30#ibcon#about to read 4, iclass 28, count 0 2006.173.02:02:33.30#ibcon#read 4, iclass 28, count 0 2006.173.02:02:33.30#ibcon#about to read 5, iclass 28, count 0 2006.173.02:02:33.30#ibcon#read 5, iclass 28, count 0 2006.173.02:02:33.30#ibcon#about to read 6, iclass 28, count 0 2006.173.02:02:33.30#ibcon#read 6, iclass 28, count 0 2006.173.02:02:33.30#ibcon#end of sib2, iclass 28, count 0 2006.173.02:02:33.30#ibcon#*after write, iclass 28, count 0 2006.173.02:02:33.30#ibcon#*before return 0, iclass 28, count 0 2006.173.02:02:33.30#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.02:02:33.30#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.02:02:33.30#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.02:02:33.30#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.02:02:33.30$vck44/va=2,6 2006.173.02:02:33.30#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.02:02:33.30#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.02:02:33.30#ibcon#ireg 11 cls_cnt 2 2006.173.02:02:33.30#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.02:02:33.36#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.02:02:33.36#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.02:02:33.36#ibcon#enter wrdev, iclass 30, count 2 2006.173.02:02:33.36#ibcon#first serial, iclass 30, count 2 2006.173.02:02:33.36#ibcon#enter sib2, iclass 30, count 2 2006.173.02:02:33.36#ibcon#flushed, iclass 30, count 2 2006.173.02:02:33.36#ibcon#about to write, iclass 30, count 2 2006.173.02:02:33.36#ibcon#wrote, iclass 30, count 2 2006.173.02:02:33.36#ibcon#about to read 3, iclass 30, count 2 2006.173.02:02:33.38#ibcon#read 3, iclass 30, count 2 2006.173.02:02:33.38#ibcon#about to read 4, iclass 30, count 2 2006.173.02:02:33.38#ibcon#read 4, iclass 30, count 2 2006.173.02:02:33.38#ibcon#about to read 5, iclass 30, count 2 2006.173.02:02:33.38#ibcon#read 5, iclass 30, count 2 2006.173.02:02:33.38#ibcon#about to read 6, iclass 30, count 2 2006.173.02:02:33.38#ibcon#read 6, iclass 30, count 2 2006.173.02:02:33.38#ibcon#end of sib2, iclass 30, count 2 2006.173.02:02:33.38#ibcon#*mode == 0, iclass 30, count 2 2006.173.02:02:33.38#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.02:02:33.38#ibcon#[25=AT02-06\r\n] 2006.173.02:02:33.38#ibcon#*before write, iclass 30, count 2 2006.173.02:02:33.38#ibcon#enter sib2, iclass 30, count 2 2006.173.02:02:33.38#ibcon#flushed, iclass 30, count 2 2006.173.02:02:33.38#ibcon#about to write, iclass 30, count 2 2006.173.02:02:33.38#ibcon#wrote, iclass 30, count 2 2006.173.02:02:33.38#ibcon#about to read 3, iclass 30, count 2 2006.173.02:02:33.41#ibcon#read 3, iclass 30, count 2 2006.173.02:02:33.41#ibcon#about to read 4, iclass 30, count 2 2006.173.02:02:33.41#ibcon#read 4, iclass 30, count 2 2006.173.02:02:33.41#ibcon#about to read 5, iclass 30, count 2 2006.173.02:02:33.41#ibcon#read 5, iclass 30, count 2 2006.173.02:02:33.41#ibcon#about to read 6, iclass 30, count 2 2006.173.02:02:33.41#ibcon#read 6, iclass 30, count 2 2006.173.02:02:33.41#ibcon#end of sib2, iclass 30, count 2 2006.173.02:02:33.41#ibcon#*after write, iclass 30, count 2 2006.173.02:02:33.41#ibcon#*before return 0, iclass 30, count 2 2006.173.02:02:33.41#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.02:02:33.41#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.02:02:33.41#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.02:02:33.41#ibcon#ireg 7 cls_cnt 0 2006.173.02:02:33.41#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.02:02:33.53#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.02:02:33.53#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.02:02:33.53#ibcon#enter wrdev, iclass 30, count 0 2006.173.02:02:33.53#ibcon#first serial, iclass 30, count 0 2006.173.02:02:33.53#ibcon#enter sib2, iclass 30, count 0 2006.173.02:02:33.53#ibcon#flushed, iclass 30, count 0 2006.173.02:02:33.53#ibcon#about to write, iclass 30, count 0 2006.173.02:02:33.53#ibcon#wrote, iclass 30, count 0 2006.173.02:02:33.53#ibcon#about to read 3, iclass 30, count 0 2006.173.02:02:33.55#ibcon#read 3, iclass 30, count 0 2006.173.02:02:33.55#ibcon#about to read 4, iclass 30, count 0 2006.173.02:02:33.55#ibcon#read 4, iclass 30, count 0 2006.173.02:02:33.55#ibcon#about to read 5, iclass 30, count 0 2006.173.02:02:33.55#ibcon#read 5, iclass 30, count 0 2006.173.02:02:33.55#ibcon#about to read 6, iclass 30, count 0 2006.173.02:02:33.55#ibcon#read 6, iclass 30, count 0 2006.173.02:02:33.55#ibcon#end of sib2, iclass 30, count 0 2006.173.02:02:33.55#ibcon#*mode == 0, iclass 30, count 0 2006.173.02:02:33.55#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.02:02:33.55#ibcon#[25=USB\r\n] 2006.173.02:02:33.55#ibcon#*before write, iclass 30, count 0 2006.173.02:02:33.55#ibcon#enter sib2, iclass 30, count 0 2006.173.02:02:33.55#ibcon#flushed, iclass 30, count 0 2006.173.02:02:33.55#ibcon#about to write, iclass 30, count 0 2006.173.02:02:33.55#ibcon#wrote, iclass 30, count 0 2006.173.02:02:33.55#ibcon#about to read 3, iclass 30, count 0 2006.173.02:02:33.58#ibcon#read 3, iclass 30, count 0 2006.173.02:02:33.58#ibcon#about to read 4, iclass 30, count 0 2006.173.02:02:33.58#ibcon#read 4, iclass 30, count 0 2006.173.02:02:33.58#ibcon#about to read 5, iclass 30, count 0 2006.173.02:02:33.58#ibcon#read 5, iclass 30, count 0 2006.173.02:02:33.58#ibcon#about to read 6, iclass 30, count 0 2006.173.02:02:33.58#ibcon#read 6, iclass 30, count 0 2006.173.02:02:33.58#ibcon#end of sib2, iclass 30, count 0 2006.173.02:02:33.58#ibcon#*after write, iclass 30, count 0 2006.173.02:02:33.58#ibcon#*before return 0, iclass 30, count 0 2006.173.02:02:33.58#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.02:02:33.58#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.02:02:33.58#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.02:02:33.58#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.02:02:33.58$vck44/valo=3,564.99 2006.173.02:02:33.58#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.02:02:33.58#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.02:02:33.58#ibcon#ireg 17 cls_cnt 0 2006.173.02:02:33.58#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.02:02:33.58#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.02:02:33.58#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.02:02:33.58#ibcon#enter wrdev, iclass 32, count 0 2006.173.02:02:33.58#ibcon#first serial, iclass 32, count 0 2006.173.02:02:33.58#ibcon#enter sib2, iclass 32, count 0 2006.173.02:02:33.58#ibcon#flushed, iclass 32, count 0 2006.173.02:02:33.58#ibcon#about to write, iclass 32, count 0 2006.173.02:02:33.58#ibcon#wrote, iclass 32, count 0 2006.173.02:02:33.58#ibcon#about to read 3, iclass 32, count 0 2006.173.02:02:33.60#ibcon#read 3, iclass 32, count 0 2006.173.02:02:33.60#ibcon#about to read 4, iclass 32, count 0 2006.173.02:02:33.60#ibcon#read 4, iclass 32, count 0 2006.173.02:02:33.60#ibcon#about to read 5, iclass 32, count 0 2006.173.02:02:33.60#ibcon#read 5, iclass 32, count 0 2006.173.02:02:33.60#ibcon#about to read 6, iclass 32, count 0 2006.173.02:02:33.60#ibcon#read 6, iclass 32, count 0 2006.173.02:02:33.60#ibcon#end of sib2, iclass 32, count 0 2006.173.02:02:33.60#ibcon#*mode == 0, iclass 32, count 0 2006.173.02:02:33.60#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.02:02:33.60#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.02:02:33.60#ibcon#*before write, iclass 32, count 0 2006.173.02:02:33.60#ibcon#enter sib2, iclass 32, count 0 2006.173.02:02:33.60#ibcon#flushed, iclass 32, count 0 2006.173.02:02:33.60#ibcon#about to write, iclass 32, count 0 2006.173.02:02:33.60#ibcon#wrote, iclass 32, count 0 2006.173.02:02:33.60#ibcon#about to read 3, iclass 32, count 0 2006.173.02:02:33.64#ibcon#read 3, iclass 32, count 0 2006.173.02:02:33.64#ibcon#about to read 4, iclass 32, count 0 2006.173.02:02:33.64#ibcon#read 4, iclass 32, count 0 2006.173.02:02:33.64#ibcon#about to read 5, iclass 32, count 0 2006.173.02:02:33.64#ibcon#read 5, iclass 32, count 0 2006.173.02:02:33.64#ibcon#about to read 6, iclass 32, count 0 2006.173.02:02:33.64#ibcon#read 6, iclass 32, count 0 2006.173.02:02:33.64#ibcon#end of sib2, iclass 32, count 0 2006.173.02:02:33.64#ibcon#*after write, iclass 32, count 0 2006.173.02:02:33.64#ibcon#*before return 0, iclass 32, count 0 2006.173.02:02:33.64#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.02:02:33.64#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.02:02:33.64#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.02:02:33.64#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.02:02:33.64$vck44/va=3,5 2006.173.02:02:33.64#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.02:02:33.64#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.02:02:33.64#ibcon#ireg 11 cls_cnt 2 2006.173.02:02:33.64#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.02:02:33.70#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.02:02:33.70#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.02:02:33.70#ibcon#enter wrdev, iclass 34, count 2 2006.173.02:02:33.70#ibcon#first serial, iclass 34, count 2 2006.173.02:02:33.70#ibcon#enter sib2, iclass 34, count 2 2006.173.02:02:33.70#ibcon#flushed, iclass 34, count 2 2006.173.02:02:33.70#ibcon#about to write, iclass 34, count 2 2006.173.02:02:33.70#ibcon#wrote, iclass 34, count 2 2006.173.02:02:33.70#ibcon#about to read 3, iclass 34, count 2 2006.173.02:02:33.72#ibcon#read 3, iclass 34, count 2 2006.173.02:02:33.72#ibcon#about to read 4, iclass 34, count 2 2006.173.02:02:33.72#ibcon#read 4, iclass 34, count 2 2006.173.02:02:33.72#ibcon#about to read 5, iclass 34, count 2 2006.173.02:02:33.72#ibcon#read 5, iclass 34, count 2 2006.173.02:02:33.72#ibcon#about to read 6, iclass 34, count 2 2006.173.02:02:33.72#ibcon#read 6, iclass 34, count 2 2006.173.02:02:33.72#ibcon#end of sib2, iclass 34, count 2 2006.173.02:02:33.72#ibcon#*mode == 0, iclass 34, count 2 2006.173.02:02:33.72#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.02:02:33.72#ibcon#[25=AT03-05\r\n] 2006.173.02:02:33.72#ibcon#*before write, iclass 34, count 2 2006.173.02:02:33.72#ibcon#enter sib2, iclass 34, count 2 2006.173.02:02:33.72#ibcon#flushed, iclass 34, count 2 2006.173.02:02:33.72#ibcon#about to write, iclass 34, count 2 2006.173.02:02:33.72#ibcon#wrote, iclass 34, count 2 2006.173.02:02:33.72#ibcon#about to read 3, iclass 34, count 2 2006.173.02:02:33.75#ibcon#read 3, iclass 34, count 2 2006.173.02:02:33.75#ibcon#about to read 4, iclass 34, count 2 2006.173.02:02:33.75#ibcon#read 4, iclass 34, count 2 2006.173.02:02:33.75#ibcon#about to read 5, iclass 34, count 2 2006.173.02:02:33.75#ibcon#read 5, iclass 34, count 2 2006.173.02:02:33.75#ibcon#about to read 6, iclass 34, count 2 2006.173.02:02:33.75#ibcon#read 6, iclass 34, count 2 2006.173.02:02:33.75#ibcon#end of sib2, iclass 34, count 2 2006.173.02:02:33.75#ibcon#*after write, iclass 34, count 2 2006.173.02:02:33.75#ibcon#*before return 0, iclass 34, count 2 2006.173.02:02:33.75#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.02:02:33.75#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.02:02:33.75#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.02:02:33.75#ibcon#ireg 7 cls_cnt 0 2006.173.02:02:33.75#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.02:02:33.87#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.02:02:33.87#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.02:02:33.87#ibcon#enter wrdev, iclass 34, count 0 2006.173.02:02:33.87#ibcon#first serial, iclass 34, count 0 2006.173.02:02:33.87#ibcon#enter sib2, iclass 34, count 0 2006.173.02:02:33.87#ibcon#flushed, iclass 34, count 0 2006.173.02:02:33.87#ibcon#about to write, iclass 34, count 0 2006.173.02:02:33.87#ibcon#wrote, iclass 34, count 0 2006.173.02:02:33.87#ibcon#about to read 3, iclass 34, count 0 2006.173.02:02:33.89#ibcon#read 3, iclass 34, count 0 2006.173.02:02:33.89#ibcon#about to read 4, iclass 34, count 0 2006.173.02:02:33.89#ibcon#read 4, iclass 34, count 0 2006.173.02:02:33.89#ibcon#about to read 5, iclass 34, count 0 2006.173.02:02:33.89#ibcon#read 5, iclass 34, count 0 2006.173.02:02:33.89#ibcon#about to read 6, iclass 34, count 0 2006.173.02:02:33.89#ibcon#read 6, iclass 34, count 0 2006.173.02:02:33.89#ibcon#end of sib2, iclass 34, count 0 2006.173.02:02:33.89#ibcon#*mode == 0, iclass 34, count 0 2006.173.02:02:33.89#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.02:02:33.89#ibcon#[25=USB\r\n] 2006.173.02:02:33.89#ibcon#*before write, iclass 34, count 0 2006.173.02:02:33.89#ibcon#enter sib2, iclass 34, count 0 2006.173.02:02:33.89#ibcon#flushed, iclass 34, count 0 2006.173.02:02:33.89#ibcon#about to write, iclass 34, count 0 2006.173.02:02:33.89#ibcon#wrote, iclass 34, count 0 2006.173.02:02:33.89#ibcon#about to read 3, iclass 34, count 0 2006.173.02:02:33.92#ibcon#read 3, iclass 34, count 0 2006.173.02:02:33.92#ibcon#about to read 4, iclass 34, count 0 2006.173.02:02:33.92#ibcon#read 4, iclass 34, count 0 2006.173.02:02:33.92#ibcon#about to read 5, iclass 34, count 0 2006.173.02:02:33.92#ibcon#read 5, iclass 34, count 0 2006.173.02:02:33.92#ibcon#about to read 6, iclass 34, count 0 2006.173.02:02:33.92#ibcon#read 6, iclass 34, count 0 2006.173.02:02:33.92#ibcon#end of sib2, iclass 34, count 0 2006.173.02:02:33.92#ibcon#*after write, iclass 34, count 0 2006.173.02:02:33.92#ibcon#*before return 0, iclass 34, count 0 2006.173.02:02:33.92#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.02:02:33.92#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.02:02:33.92#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.02:02:33.92#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.02:02:33.92$vck44/valo=4,624.99 2006.173.02:02:33.92#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.02:02:33.92#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.02:02:33.92#ibcon#ireg 17 cls_cnt 0 2006.173.02:02:33.92#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.02:02:33.92#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.02:02:33.92#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.02:02:33.92#ibcon#enter wrdev, iclass 36, count 0 2006.173.02:02:33.92#ibcon#first serial, iclass 36, count 0 2006.173.02:02:33.92#ibcon#enter sib2, iclass 36, count 0 2006.173.02:02:33.92#ibcon#flushed, iclass 36, count 0 2006.173.02:02:33.92#ibcon#about to write, iclass 36, count 0 2006.173.02:02:33.92#ibcon#wrote, iclass 36, count 0 2006.173.02:02:33.92#ibcon#about to read 3, iclass 36, count 0 2006.173.02:02:33.94#ibcon#read 3, iclass 36, count 0 2006.173.02:02:33.94#ibcon#about to read 4, iclass 36, count 0 2006.173.02:02:33.94#ibcon#read 4, iclass 36, count 0 2006.173.02:02:33.94#ibcon#about to read 5, iclass 36, count 0 2006.173.02:02:33.94#ibcon#read 5, iclass 36, count 0 2006.173.02:02:33.94#ibcon#about to read 6, iclass 36, count 0 2006.173.02:02:33.94#ibcon#read 6, iclass 36, count 0 2006.173.02:02:33.94#ibcon#end of sib2, iclass 36, count 0 2006.173.02:02:33.94#ibcon#*mode == 0, iclass 36, count 0 2006.173.02:02:33.94#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.02:02:33.94#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.02:02:33.94#ibcon#*before write, iclass 36, count 0 2006.173.02:02:33.94#ibcon#enter sib2, iclass 36, count 0 2006.173.02:02:33.94#ibcon#flushed, iclass 36, count 0 2006.173.02:02:33.94#ibcon#about to write, iclass 36, count 0 2006.173.02:02:33.94#ibcon#wrote, iclass 36, count 0 2006.173.02:02:33.94#ibcon#about to read 3, iclass 36, count 0 2006.173.02:02:33.98#ibcon#read 3, iclass 36, count 0 2006.173.02:02:33.98#ibcon#about to read 4, iclass 36, count 0 2006.173.02:02:33.98#ibcon#read 4, iclass 36, count 0 2006.173.02:02:33.98#ibcon#about to read 5, iclass 36, count 0 2006.173.02:02:33.98#ibcon#read 5, iclass 36, count 0 2006.173.02:02:33.98#ibcon#about to read 6, iclass 36, count 0 2006.173.02:02:33.98#ibcon#read 6, iclass 36, count 0 2006.173.02:02:33.98#ibcon#end of sib2, iclass 36, count 0 2006.173.02:02:33.98#ibcon#*after write, iclass 36, count 0 2006.173.02:02:33.98#ibcon#*before return 0, iclass 36, count 0 2006.173.02:02:33.98#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.02:02:33.98#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.02:02:33.98#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.02:02:33.98#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.02:02:33.98$vck44/va=4,6 2006.173.02:02:33.98#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.02:02:33.98#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.02:02:33.98#ibcon#ireg 11 cls_cnt 2 2006.173.02:02:33.98#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.02:02:34.04#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.02:02:34.04#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.02:02:34.04#ibcon#enter wrdev, iclass 38, count 2 2006.173.02:02:34.04#ibcon#first serial, iclass 38, count 2 2006.173.02:02:34.04#ibcon#enter sib2, iclass 38, count 2 2006.173.02:02:34.04#ibcon#flushed, iclass 38, count 2 2006.173.02:02:34.04#ibcon#about to write, iclass 38, count 2 2006.173.02:02:34.04#ibcon#wrote, iclass 38, count 2 2006.173.02:02:34.04#ibcon#about to read 3, iclass 38, count 2 2006.173.02:02:34.06#ibcon#read 3, iclass 38, count 2 2006.173.02:02:34.06#ibcon#about to read 4, iclass 38, count 2 2006.173.02:02:34.06#ibcon#read 4, iclass 38, count 2 2006.173.02:02:34.06#ibcon#about to read 5, iclass 38, count 2 2006.173.02:02:34.06#ibcon#read 5, iclass 38, count 2 2006.173.02:02:34.06#ibcon#about to read 6, iclass 38, count 2 2006.173.02:02:34.06#ibcon#read 6, iclass 38, count 2 2006.173.02:02:34.06#ibcon#end of sib2, iclass 38, count 2 2006.173.02:02:34.06#ibcon#*mode == 0, iclass 38, count 2 2006.173.02:02:34.06#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.02:02:34.06#ibcon#[25=AT04-06\r\n] 2006.173.02:02:34.06#ibcon#*before write, iclass 38, count 2 2006.173.02:02:34.06#ibcon#enter sib2, iclass 38, count 2 2006.173.02:02:34.06#ibcon#flushed, iclass 38, count 2 2006.173.02:02:34.06#ibcon#about to write, iclass 38, count 2 2006.173.02:02:34.06#ibcon#wrote, iclass 38, count 2 2006.173.02:02:34.06#ibcon#about to read 3, iclass 38, count 2 2006.173.02:02:34.09#ibcon#read 3, iclass 38, count 2 2006.173.02:02:34.09#ibcon#about to read 4, iclass 38, count 2 2006.173.02:02:34.09#ibcon#read 4, iclass 38, count 2 2006.173.02:02:34.09#ibcon#about to read 5, iclass 38, count 2 2006.173.02:02:34.09#ibcon#read 5, iclass 38, count 2 2006.173.02:02:34.09#ibcon#about to read 6, iclass 38, count 2 2006.173.02:02:34.09#ibcon#read 6, iclass 38, count 2 2006.173.02:02:34.09#ibcon#end of sib2, iclass 38, count 2 2006.173.02:02:34.09#ibcon#*after write, iclass 38, count 2 2006.173.02:02:34.09#ibcon#*before return 0, iclass 38, count 2 2006.173.02:02:34.09#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.02:02:34.09#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.02:02:34.09#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.02:02:34.09#ibcon#ireg 7 cls_cnt 0 2006.173.02:02:34.09#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.02:02:34.21#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.02:02:34.21#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.02:02:34.21#ibcon#enter wrdev, iclass 38, count 0 2006.173.02:02:34.21#ibcon#first serial, iclass 38, count 0 2006.173.02:02:34.21#ibcon#enter sib2, iclass 38, count 0 2006.173.02:02:34.21#ibcon#flushed, iclass 38, count 0 2006.173.02:02:34.21#ibcon#about to write, iclass 38, count 0 2006.173.02:02:34.21#ibcon#wrote, iclass 38, count 0 2006.173.02:02:34.21#ibcon#about to read 3, iclass 38, count 0 2006.173.02:02:34.23#ibcon#read 3, iclass 38, count 0 2006.173.02:02:34.23#ibcon#about to read 4, iclass 38, count 0 2006.173.02:02:34.23#ibcon#read 4, iclass 38, count 0 2006.173.02:02:34.23#ibcon#about to read 5, iclass 38, count 0 2006.173.02:02:34.23#ibcon#read 5, iclass 38, count 0 2006.173.02:02:34.23#ibcon#about to read 6, iclass 38, count 0 2006.173.02:02:34.23#ibcon#read 6, iclass 38, count 0 2006.173.02:02:34.23#ibcon#end of sib2, iclass 38, count 0 2006.173.02:02:34.23#ibcon#*mode == 0, iclass 38, count 0 2006.173.02:02:34.23#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.02:02:34.23#ibcon#[25=USB\r\n] 2006.173.02:02:34.23#ibcon#*before write, iclass 38, count 0 2006.173.02:02:34.23#ibcon#enter sib2, iclass 38, count 0 2006.173.02:02:34.23#ibcon#flushed, iclass 38, count 0 2006.173.02:02:34.23#ibcon#about to write, iclass 38, count 0 2006.173.02:02:34.23#ibcon#wrote, iclass 38, count 0 2006.173.02:02:34.23#ibcon#about to read 3, iclass 38, count 0 2006.173.02:02:34.26#ibcon#read 3, iclass 38, count 0 2006.173.02:02:34.26#ibcon#about to read 4, iclass 38, count 0 2006.173.02:02:34.26#ibcon#read 4, iclass 38, count 0 2006.173.02:02:34.26#ibcon#about to read 5, iclass 38, count 0 2006.173.02:02:34.26#ibcon#read 5, iclass 38, count 0 2006.173.02:02:34.26#ibcon#about to read 6, iclass 38, count 0 2006.173.02:02:34.26#ibcon#read 6, iclass 38, count 0 2006.173.02:02:34.26#ibcon#end of sib2, iclass 38, count 0 2006.173.02:02:34.26#ibcon#*after write, iclass 38, count 0 2006.173.02:02:34.26#ibcon#*before return 0, iclass 38, count 0 2006.173.02:02:34.26#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.02:02:34.26#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.02:02:34.26#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.02:02:34.26#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.02:02:34.26$vck44/valo=5,734.99 2006.173.02:02:34.26#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.02:02:34.26#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.02:02:34.26#ibcon#ireg 17 cls_cnt 0 2006.173.02:02:34.26#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.02:02:34.26#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.02:02:34.26#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.02:02:34.26#ibcon#enter wrdev, iclass 40, count 0 2006.173.02:02:34.26#ibcon#first serial, iclass 40, count 0 2006.173.02:02:34.26#ibcon#enter sib2, iclass 40, count 0 2006.173.02:02:34.26#ibcon#flushed, iclass 40, count 0 2006.173.02:02:34.26#ibcon#about to write, iclass 40, count 0 2006.173.02:02:34.26#ibcon#wrote, iclass 40, count 0 2006.173.02:02:34.26#ibcon#about to read 3, iclass 40, count 0 2006.173.02:02:34.28#ibcon#read 3, iclass 40, count 0 2006.173.02:02:34.28#ibcon#about to read 4, iclass 40, count 0 2006.173.02:02:34.28#ibcon#read 4, iclass 40, count 0 2006.173.02:02:34.28#ibcon#about to read 5, iclass 40, count 0 2006.173.02:02:34.28#ibcon#read 5, iclass 40, count 0 2006.173.02:02:34.28#ibcon#about to read 6, iclass 40, count 0 2006.173.02:02:34.28#ibcon#read 6, iclass 40, count 0 2006.173.02:02:34.28#ibcon#end of sib2, iclass 40, count 0 2006.173.02:02:34.28#ibcon#*mode == 0, iclass 40, count 0 2006.173.02:02:34.28#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.02:02:34.28#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.02:02:34.28#ibcon#*before write, iclass 40, count 0 2006.173.02:02:34.28#ibcon#enter sib2, iclass 40, count 0 2006.173.02:02:34.28#ibcon#flushed, iclass 40, count 0 2006.173.02:02:34.28#ibcon#about to write, iclass 40, count 0 2006.173.02:02:34.28#ibcon#wrote, iclass 40, count 0 2006.173.02:02:34.28#ibcon#about to read 3, iclass 40, count 0 2006.173.02:02:34.32#ibcon#read 3, iclass 40, count 0 2006.173.02:02:34.32#ibcon#about to read 4, iclass 40, count 0 2006.173.02:02:34.32#ibcon#read 4, iclass 40, count 0 2006.173.02:02:34.32#ibcon#about to read 5, iclass 40, count 0 2006.173.02:02:34.32#ibcon#read 5, iclass 40, count 0 2006.173.02:02:34.32#ibcon#about to read 6, iclass 40, count 0 2006.173.02:02:34.32#ibcon#read 6, iclass 40, count 0 2006.173.02:02:34.32#ibcon#end of sib2, iclass 40, count 0 2006.173.02:02:34.32#ibcon#*after write, iclass 40, count 0 2006.173.02:02:34.32#ibcon#*before return 0, iclass 40, count 0 2006.173.02:02:34.32#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.02:02:34.32#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.02:02:34.32#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.02:02:34.32#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.02:02:34.32$vck44/va=5,4 2006.173.02:02:34.32#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.02:02:34.32#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.02:02:34.32#ibcon#ireg 11 cls_cnt 2 2006.173.02:02:34.32#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.02:02:34.38#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.02:02:34.38#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.02:02:34.38#ibcon#enter wrdev, iclass 4, count 2 2006.173.02:02:34.38#ibcon#first serial, iclass 4, count 2 2006.173.02:02:34.38#ibcon#enter sib2, iclass 4, count 2 2006.173.02:02:34.38#ibcon#flushed, iclass 4, count 2 2006.173.02:02:34.38#ibcon#about to write, iclass 4, count 2 2006.173.02:02:34.38#ibcon#wrote, iclass 4, count 2 2006.173.02:02:34.38#ibcon#about to read 3, iclass 4, count 2 2006.173.02:02:34.40#ibcon#read 3, iclass 4, count 2 2006.173.02:02:34.40#ibcon#about to read 4, iclass 4, count 2 2006.173.02:02:34.40#ibcon#read 4, iclass 4, count 2 2006.173.02:02:34.40#ibcon#about to read 5, iclass 4, count 2 2006.173.02:02:34.40#ibcon#read 5, iclass 4, count 2 2006.173.02:02:34.40#ibcon#about to read 6, iclass 4, count 2 2006.173.02:02:34.40#ibcon#read 6, iclass 4, count 2 2006.173.02:02:34.40#ibcon#end of sib2, iclass 4, count 2 2006.173.02:02:34.40#ibcon#*mode == 0, iclass 4, count 2 2006.173.02:02:34.40#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.02:02:34.40#ibcon#[25=AT05-04\r\n] 2006.173.02:02:34.40#ibcon#*before write, iclass 4, count 2 2006.173.02:02:34.40#ibcon#enter sib2, iclass 4, count 2 2006.173.02:02:34.40#ibcon#flushed, iclass 4, count 2 2006.173.02:02:34.40#ibcon#about to write, iclass 4, count 2 2006.173.02:02:34.40#ibcon#wrote, iclass 4, count 2 2006.173.02:02:34.40#ibcon#about to read 3, iclass 4, count 2 2006.173.02:02:34.43#ibcon#read 3, iclass 4, count 2 2006.173.02:02:34.43#ibcon#about to read 4, iclass 4, count 2 2006.173.02:02:34.43#ibcon#read 4, iclass 4, count 2 2006.173.02:02:34.43#ibcon#about to read 5, iclass 4, count 2 2006.173.02:02:34.43#ibcon#read 5, iclass 4, count 2 2006.173.02:02:34.43#ibcon#about to read 6, iclass 4, count 2 2006.173.02:02:34.43#ibcon#read 6, iclass 4, count 2 2006.173.02:02:34.43#ibcon#end of sib2, iclass 4, count 2 2006.173.02:02:34.43#ibcon#*after write, iclass 4, count 2 2006.173.02:02:34.43#ibcon#*before return 0, iclass 4, count 2 2006.173.02:02:34.43#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.02:02:34.43#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.02:02:34.43#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.02:02:34.43#ibcon#ireg 7 cls_cnt 0 2006.173.02:02:34.43#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.02:02:34.55#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.02:02:34.55#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.02:02:34.55#ibcon#enter wrdev, iclass 4, count 0 2006.173.02:02:34.55#ibcon#first serial, iclass 4, count 0 2006.173.02:02:34.55#ibcon#enter sib2, iclass 4, count 0 2006.173.02:02:34.55#ibcon#flushed, iclass 4, count 0 2006.173.02:02:34.55#ibcon#about to write, iclass 4, count 0 2006.173.02:02:34.55#ibcon#wrote, iclass 4, count 0 2006.173.02:02:34.55#ibcon#about to read 3, iclass 4, count 0 2006.173.02:02:34.57#ibcon#read 3, iclass 4, count 0 2006.173.02:02:34.57#ibcon#about to read 4, iclass 4, count 0 2006.173.02:02:34.57#ibcon#read 4, iclass 4, count 0 2006.173.02:02:34.57#ibcon#about to read 5, iclass 4, count 0 2006.173.02:02:34.57#ibcon#read 5, iclass 4, count 0 2006.173.02:02:34.57#ibcon#about to read 6, iclass 4, count 0 2006.173.02:02:34.57#ibcon#read 6, iclass 4, count 0 2006.173.02:02:34.57#ibcon#end of sib2, iclass 4, count 0 2006.173.02:02:34.57#ibcon#*mode == 0, iclass 4, count 0 2006.173.02:02:34.57#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.02:02:34.57#ibcon#[25=USB\r\n] 2006.173.02:02:34.57#ibcon#*before write, iclass 4, count 0 2006.173.02:02:34.57#ibcon#enter sib2, iclass 4, count 0 2006.173.02:02:34.57#ibcon#flushed, iclass 4, count 0 2006.173.02:02:34.57#ibcon#about to write, iclass 4, count 0 2006.173.02:02:34.57#ibcon#wrote, iclass 4, count 0 2006.173.02:02:34.57#ibcon#about to read 3, iclass 4, count 0 2006.173.02:02:34.60#ibcon#read 3, iclass 4, count 0 2006.173.02:02:34.60#ibcon#about to read 4, iclass 4, count 0 2006.173.02:02:34.60#ibcon#read 4, iclass 4, count 0 2006.173.02:02:34.60#ibcon#about to read 5, iclass 4, count 0 2006.173.02:02:34.60#ibcon#read 5, iclass 4, count 0 2006.173.02:02:34.60#ibcon#about to read 6, iclass 4, count 0 2006.173.02:02:34.60#ibcon#read 6, iclass 4, count 0 2006.173.02:02:34.60#ibcon#end of sib2, iclass 4, count 0 2006.173.02:02:34.60#ibcon#*after write, iclass 4, count 0 2006.173.02:02:34.60#ibcon#*before return 0, iclass 4, count 0 2006.173.02:02:34.60#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.02:02:34.60#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.02:02:34.60#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.02:02:34.60#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.02:02:34.60$vck44/valo=6,814.99 2006.173.02:02:34.60#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.02:02:34.60#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.02:02:34.60#ibcon#ireg 17 cls_cnt 0 2006.173.02:02:34.60#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.02:02:34.60#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.02:02:34.60#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.02:02:34.60#ibcon#enter wrdev, iclass 6, count 0 2006.173.02:02:34.60#ibcon#first serial, iclass 6, count 0 2006.173.02:02:34.60#ibcon#enter sib2, iclass 6, count 0 2006.173.02:02:34.60#ibcon#flushed, iclass 6, count 0 2006.173.02:02:34.60#ibcon#about to write, iclass 6, count 0 2006.173.02:02:34.60#ibcon#wrote, iclass 6, count 0 2006.173.02:02:34.60#ibcon#about to read 3, iclass 6, count 0 2006.173.02:02:34.62#ibcon#read 3, iclass 6, count 0 2006.173.02:02:34.62#ibcon#about to read 4, iclass 6, count 0 2006.173.02:02:34.62#ibcon#read 4, iclass 6, count 0 2006.173.02:02:34.62#ibcon#about to read 5, iclass 6, count 0 2006.173.02:02:34.62#ibcon#read 5, iclass 6, count 0 2006.173.02:02:34.62#ibcon#about to read 6, iclass 6, count 0 2006.173.02:02:34.62#ibcon#read 6, iclass 6, count 0 2006.173.02:02:34.62#ibcon#end of sib2, iclass 6, count 0 2006.173.02:02:34.62#ibcon#*mode == 0, iclass 6, count 0 2006.173.02:02:34.62#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.02:02:34.62#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.02:02:34.62#ibcon#*before write, iclass 6, count 0 2006.173.02:02:34.62#ibcon#enter sib2, iclass 6, count 0 2006.173.02:02:34.62#ibcon#flushed, iclass 6, count 0 2006.173.02:02:34.62#ibcon#about to write, iclass 6, count 0 2006.173.02:02:34.62#ibcon#wrote, iclass 6, count 0 2006.173.02:02:34.62#ibcon#about to read 3, iclass 6, count 0 2006.173.02:02:34.66#ibcon#read 3, iclass 6, count 0 2006.173.02:02:34.66#ibcon#about to read 4, iclass 6, count 0 2006.173.02:02:34.66#ibcon#read 4, iclass 6, count 0 2006.173.02:02:34.66#ibcon#about to read 5, iclass 6, count 0 2006.173.02:02:34.66#ibcon#read 5, iclass 6, count 0 2006.173.02:02:34.66#ibcon#about to read 6, iclass 6, count 0 2006.173.02:02:34.66#ibcon#read 6, iclass 6, count 0 2006.173.02:02:34.66#ibcon#end of sib2, iclass 6, count 0 2006.173.02:02:34.66#ibcon#*after write, iclass 6, count 0 2006.173.02:02:34.66#ibcon#*before return 0, iclass 6, count 0 2006.173.02:02:34.66#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.02:02:34.66#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.02:02:34.66#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.02:02:34.66#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.02:02:34.66$vck44/va=6,3 2006.173.02:02:34.66#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.02:02:34.66#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.02:02:34.66#ibcon#ireg 11 cls_cnt 2 2006.173.02:02:34.66#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.02:02:34.72#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.02:02:34.72#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.02:02:34.72#ibcon#enter wrdev, iclass 10, count 2 2006.173.02:02:34.72#ibcon#first serial, iclass 10, count 2 2006.173.02:02:34.72#ibcon#enter sib2, iclass 10, count 2 2006.173.02:02:34.72#ibcon#flushed, iclass 10, count 2 2006.173.02:02:34.72#ibcon#about to write, iclass 10, count 2 2006.173.02:02:34.72#ibcon#wrote, iclass 10, count 2 2006.173.02:02:34.72#ibcon#about to read 3, iclass 10, count 2 2006.173.02:02:34.74#ibcon#read 3, iclass 10, count 2 2006.173.02:02:34.74#ibcon#about to read 4, iclass 10, count 2 2006.173.02:02:34.74#ibcon#read 4, iclass 10, count 2 2006.173.02:02:34.74#ibcon#about to read 5, iclass 10, count 2 2006.173.02:02:34.74#ibcon#read 5, iclass 10, count 2 2006.173.02:02:34.74#ibcon#about to read 6, iclass 10, count 2 2006.173.02:02:34.74#ibcon#read 6, iclass 10, count 2 2006.173.02:02:34.74#ibcon#end of sib2, iclass 10, count 2 2006.173.02:02:34.74#ibcon#*mode == 0, iclass 10, count 2 2006.173.02:02:34.74#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.02:02:34.74#ibcon#[25=AT06-03\r\n] 2006.173.02:02:34.74#ibcon#*before write, iclass 10, count 2 2006.173.02:02:34.74#ibcon#enter sib2, iclass 10, count 2 2006.173.02:02:34.74#ibcon#flushed, iclass 10, count 2 2006.173.02:02:34.74#ibcon#about to write, iclass 10, count 2 2006.173.02:02:34.74#ibcon#wrote, iclass 10, count 2 2006.173.02:02:34.74#ibcon#about to read 3, iclass 10, count 2 2006.173.02:02:34.77#ibcon#read 3, iclass 10, count 2 2006.173.02:02:34.77#ibcon#about to read 4, iclass 10, count 2 2006.173.02:02:34.77#ibcon#read 4, iclass 10, count 2 2006.173.02:02:34.77#ibcon#about to read 5, iclass 10, count 2 2006.173.02:02:34.77#ibcon#read 5, iclass 10, count 2 2006.173.02:02:34.77#ibcon#about to read 6, iclass 10, count 2 2006.173.02:02:34.77#ibcon#read 6, iclass 10, count 2 2006.173.02:02:34.77#ibcon#end of sib2, iclass 10, count 2 2006.173.02:02:34.77#ibcon#*after write, iclass 10, count 2 2006.173.02:02:34.77#ibcon#*before return 0, iclass 10, count 2 2006.173.02:02:34.77#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.02:02:34.77#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.02:02:34.77#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.02:02:34.77#ibcon#ireg 7 cls_cnt 0 2006.173.02:02:34.77#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.02:02:34.89#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.02:02:34.89#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.02:02:34.89#ibcon#enter wrdev, iclass 10, count 0 2006.173.02:02:34.89#ibcon#first serial, iclass 10, count 0 2006.173.02:02:34.89#ibcon#enter sib2, iclass 10, count 0 2006.173.02:02:34.89#ibcon#flushed, iclass 10, count 0 2006.173.02:02:34.89#ibcon#about to write, iclass 10, count 0 2006.173.02:02:34.89#ibcon#wrote, iclass 10, count 0 2006.173.02:02:34.89#ibcon#about to read 3, iclass 10, count 0 2006.173.02:02:34.91#ibcon#read 3, iclass 10, count 0 2006.173.02:02:34.91#ibcon#about to read 4, iclass 10, count 0 2006.173.02:02:34.91#ibcon#read 4, iclass 10, count 0 2006.173.02:02:34.91#ibcon#about to read 5, iclass 10, count 0 2006.173.02:02:34.91#ibcon#read 5, iclass 10, count 0 2006.173.02:02:34.91#ibcon#about to read 6, iclass 10, count 0 2006.173.02:02:34.91#ibcon#read 6, iclass 10, count 0 2006.173.02:02:34.91#ibcon#end of sib2, iclass 10, count 0 2006.173.02:02:34.91#ibcon#*mode == 0, iclass 10, count 0 2006.173.02:02:34.91#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.02:02:34.91#ibcon#[25=USB\r\n] 2006.173.02:02:34.91#ibcon#*before write, iclass 10, count 0 2006.173.02:02:34.91#ibcon#enter sib2, iclass 10, count 0 2006.173.02:02:34.91#ibcon#flushed, iclass 10, count 0 2006.173.02:02:34.91#ibcon#about to write, iclass 10, count 0 2006.173.02:02:34.91#ibcon#wrote, iclass 10, count 0 2006.173.02:02:34.91#ibcon#about to read 3, iclass 10, count 0 2006.173.02:02:34.94#ibcon#read 3, iclass 10, count 0 2006.173.02:02:34.94#ibcon#about to read 4, iclass 10, count 0 2006.173.02:02:34.94#ibcon#read 4, iclass 10, count 0 2006.173.02:02:34.94#ibcon#about to read 5, iclass 10, count 0 2006.173.02:02:34.94#ibcon#read 5, iclass 10, count 0 2006.173.02:02:34.94#ibcon#about to read 6, iclass 10, count 0 2006.173.02:02:34.94#ibcon#read 6, iclass 10, count 0 2006.173.02:02:34.94#ibcon#end of sib2, iclass 10, count 0 2006.173.02:02:34.94#ibcon#*after write, iclass 10, count 0 2006.173.02:02:34.94#ibcon#*before return 0, iclass 10, count 0 2006.173.02:02:34.94#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.02:02:34.94#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.02:02:34.94#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.02:02:34.94#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.02:02:34.94$vck44/valo=7,864.99 2006.173.02:02:34.94#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.02:02:34.94#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.02:02:34.94#ibcon#ireg 17 cls_cnt 0 2006.173.02:02:34.94#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.02:02:34.94#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.02:02:34.94#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.02:02:34.94#ibcon#enter wrdev, iclass 12, count 0 2006.173.02:02:34.94#ibcon#first serial, iclass 12, count 0 2006.173.02:02:34.94#ibcon#enter sib2, iclass 12, count 0 2006.173.02:02:34.94#ibcon#flushed, iclass 12, count 0 2006.173.02:02:34.94#ibcon#about to write, iclass 12, count 0 2006.173.02:02:34.94#ibcon#wrote, iclass 12, count 0 2006.173.02:02:34.94#ibcon#about to read 3, iclass 12, count 0 2006.173.02:02:34.96#ibcon#read 3, iclass 12, count 0 2006.173.02:02:34.96#ibcon#about to read 4, iclass 12, count 0 2006.173.02:02:34.96#ibcon#read 4, iclass 12, count 0 2006.173.02:02:34.96#ibcon#about to read 5, iclass 12, count 0 2006.173.02:02:34.96#ibcon#read 5, iclass 12, count 0 2006.173.02:02:34.96#ibcon#about to read 6, iclass 12, count 0 2006.173.02:02:34.96#ibcon#read 6, iclass 12, count 0 2006.173.02:02:34.96#ibcon#end of sib2, iclass 12, count 0 2006.173.02:02:34.96#ibcon#*mode == 0, iclass 12, count 0 2006.173.02:02:34.96#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.02:02:34.96#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.02:02:34.96#ibcon#*before write, iclass 12, count 0 2006.173.02:02:34.96#ibcon#enter sib2, iclass 12, count 0 2006.173.02:02:34.96#ibcon#flushed, iclass 12, count 0 2006.173.02:02:34.96#ibcon#about to write, iclass 12, count 0 2006.173.02:02:34.96#ibcon#wrote, iclass 12, count 0 2006.173.02:02:34.96#ibcon#about to read 3, iclass 12, count 0 2006.173.02:02:35.00#ibcon#read 3, iclass 12, count 0 2006.173.02:02:35.00#ibcon#about to read 4, iclass 12, count 0 2006.173.02:02:35.00#ibcon#read 4, iclass 12, count 0 2006.173.02:02:35.00#ibcon#about to read 5, iclass 12, count 0 2006.173.02:02:35.00#ibcon#read 5, iclass 12, count 0 2006.173.02:02:35.00#ibcon#about to read 6, iclass 12, count 0 2006.173.02:02:35.00#ibcon#read 6, iclass 12, count 0 2006.173.02:02:35.00#ibcon#end of sib2, iclass 12, count 0 2006.173.02:02:35.00#ibcon#*after write, iclass 12, count 0 2006.173.02:02:35.00#ibcon#*before return 0, iclass 12, count 0 2006.173.02:02:35.00#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.02:02:35.00#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.02:02:35.00#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.02:02:35.00#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.02:02:35.00$vck44/va=7,4 2006.173.02:02:35.00#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.02:02:35.00#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.02:02:35.00#ibcon#ireg 11 cls_cnt 2 2006.173.02:02:35.00#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.02:02:35.06#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.02:02:35.06#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.02:02:35.06#ibcon#enter wrdev, iclass 14, count 2 2006.173.02:02:35.06#ibcon#first serial, iclass 14, count 2 2006.173.02:02:35.06#ibcon#enter sib2, iclass 14, count 2 2006.173.02:02:35.06#ibcon#flushed, iclass 14, count 2 2006.173.02:02:35.06#ibcon#about to write, iclass 14, count 2 2006.173.02:02:35.06#ibcon#wrote, iclass 14, count 2 2006.173.02:02:35.06#ibcon#about to read 3, iclass 14, count 2 2006.173.02:02:35.08#ibcon#read 3, iclass 14, count 2 2006.173.02:02:35.08#ibcon#about to read 4, iclass 14, count 2 2006.173.02:02:35.08#ibcon#read 4, iclass 14, count 2 2006.173.02:02:35.08#ibcon#about to read 5, iclass 14, count 2 2006.173.02:02:35.08#ibcon#read 5, iclass 14, count 2 2006.173.02:02:35.08#ibcon#about to read 6, iclass 14, count 2 2006.173.02:02:35.08#ibcon#read 6, iclass 14, count 2 2006.173.02:02:35.08#ibcon#end of sib2, iclass 14, count 2 2006.173.02:02:35.08#ibcon#*mode == 0, iclass 14, count 2 2006.173.02:02:35.08#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.02:02:35.08#ibcon#[25=AT07-04\r\n] 2006.173.02:02:35.08#ibcon#*before write, iclass 14, count 2 2006.173.02:02:35.08#ibcon#enter sib2, iclass 14, count 2 2006.173.02:02:35.08#ibcon#flushed, iclass 14, count 2 2006.173.02:02:35.08#ibcon#about to write, iclass 14, count 2 2006.173.02:02:35.08#ibcon#wrote, iclass 14, count 2 2006.173.02:02:35.08#ibcon#about to read 3, iclass 14, count 2 2006.173.02:02:35.11#ibcon#read 3, iclass 14, count 2 2006.173.02:02:35.11#ibcon#about to read 4, iclass 14, count 2 2006.173.02:02:35.11#ibcon#read 4, iclass 14, count 2 2006.173.02:02:35.11#ibcon#about to read 5, iclass 14, count 2 2006.173.02:02:35.11#ibcon#read 5, iclass 14, count 2 2006.173.02:02:35.11#ibcon#about to read 6, iclass 14, count 2 2006.173.02:02:35.11#ibcon#read 6, iclass 14, count 2 2006.173.02:02:35.11#ibcon#end of sib2, iclass 14, count 2 2006.173.02:02:35.11#ibcon#*after write, iclass 14, count 2 2006.173.02:02:35.11#ibcon#*before return 0, iclass 14, count 2 2006.173.02:02:35.11#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.02:02:35.11#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.02:02:35.11#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.02:02:35.11#ibcon#ireg 7 cls_cnt 0 2006.173.02:02:35.11#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.02:02:35.23#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.02:02:35.23#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.02:02:35.23#ibcon#enter wrdev, iclass 14, count 0 2006.173.02:02:35.23#ibcon#first serial, iclass 14, count 0 2006.173.02:02:35.23#ibcon#enter sib2, iclass 14, count 0 2006.173.02:02:35.23#ibcon#flushed, iclass 14, count 0 2006.173.02:02:35.23#ibcon#about to write, iclass 14, count 0 2006.173.02:02:35.23#ibcon#wrote, iclass 14, count 0 2006.173.02:02:35.23#ibcon#about to read 3, iclass 14, count 0 2006.173.02:02:35.25#ibcon#read 3, iclass 14, count 0 2006.173.02:02:35.25#ibcon#about to read 4, iclass 14, count 0 2006.173.02:02:35.25#ibcon#read 4, iclass 14, count 0 2006.173.02:02:35.25#ibcon#about to read 5, iclass 14, count 0 2006.173.02:02:35.25#ibcon#read 5, iclass 14, count 0 2006.173.02:02:35.25#ibcon#about to read 6, iclass 14, count 0 2006.173.02:02:35.25#ibcon#read 6, iclass 14, count 0 2006.173.02:02:35.25#ibcon#end of sib2, iclass 14, count 0 2006.173.02:02:35.25#ibcon#*mode == 0, iclass 14, count 0 2006.173.02:02:35.25#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.02:02:35.25#ibcon#[25=USB\r\n] 2006.173.02:02:35.25#ibcon#*before write, iclass 14, count 0 2006.173.02:02:35.25#ibcon#enter sib2, iclass 14, count 0 2006.173.02:02:35.25#ibcon#flushed, iclass 14, count 0 2006.173.02:02:35.25#ibcon#about to write, iclass 14, count 0 2006.173.02:02:35.25#ibcon#wrote, iclass 14, count 0 2006.173.02:02:35.25#ibcon#about to read 3, iclass 14, count 0 2006.173.02:02:35.28#ibcon#read 3, iclass 14, count 0 2006.173.02:02:35.28#ibcon#about to read 4, iclass 14, count 0 2006.173.02:02:35.28#ibcon#read 4, iclass 14, count 0 2006.173.02:02:35.28#ibcon#about to read 5, iclass 14, count 0 2006.173.02:02:35.28#ibcon#read 5, iclass 14, count 0 2006.173.02:02:35.28#ibcon#about to read 6, iclass 14, count 0 2006.173.02:02:35.28#ibcon#read 6, iclass 14, count 0 2006.173.02:02:35.28#ibcon#end of sib2, iclass 14, count 0 2006.173.02:02:35.28#ibcon#*after write, iclass 14, count 0 2006.173.02:02:35.28#ibcon#*before return 0, iclass 14, count 0 2006.173.02:02:35.28#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.02:02:35.28#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.02:02:35.28#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.02:02:35.28#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.02:02:35.28$vck44/valo=8,884.99 2006.173.02:02:35.28#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.02:02:35.28#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.02:02:35.28#ibcon#ireg 17 cls_cnt 0 2006.173.02:02:35.28#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.02:02:35.28#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.02:02:35.28#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.02:02:35.28#ibcon#enter wrdev, iclass 16, count 0 2006.173.02:02:35.28#ibcon#first serial, iclass 16, count 0 2006.173.02:02:35.28#ibcon#enter sib2, iclass 16, count 0 2006.173.02:02:35.28#ibcon#flushed, iclass 16, count 0 2006.173.02:02:35.28#ibcon#about to write, iclass 16, count 0 2006.173.02:02:35.28#ibcon#wrote, iclass 16, count 0 2006.173.02:02:35.28#ibcon#about to read 3, iclass 16, count 0 2006.173.02:02:35.30#ibcon#read 3, iclass 16, count 0 2006.173.02:02:35.30#ibcon#about to read 4, iclass 16, count 0 2006.173.02:02:35.30#ibcon#read 4, iclass 16, count 0 2006.173.02:02:35.30#ibcon#about to read 5, iclass 16, count 0 2006.173.02:02:35.30#ibcon#read 5, iclass 16, count 0 2006.173.02:02:35.30#ibcon#about to read 6, iclass 16, count 0 2006.173.02:02:35.30#ibcon#read 6, iclass 16, count 0 2006.173.02:02:35.30#ibcon#end of sib2, iclass 16, count 0 2006.173.02:02:35.30#ibcon#*mode == 0, iclass 16, count 0 2006.173.02:02:35.30#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.02:02:35.30#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.02:02:35.30#ibcon#*before write, iclass 16, count 0 2006.173.02:02:35.30#ibcon#enter sib2, iclass 16, count 0 2006.173.02:02:35.30#ibcon#flushed, iclass 16, count 0 2006.173.02:02:35.30#ibcon#about to write, iclass 16, count 0 2006.173.02:02:35.30#ibcon#wrote, iclass 16, count 0 2006.173.02:02:35.30#ibcon#about to read 3, iclass 16, count 0 2006.173.02:02:35.34#ibcon#read 3, iclass 16, count 0 2006.173.02:02:35.34#ibcon#about to read 4, iclass 16, count 0 2006.173.02:02:35.34#ibcon#read 4, iclass 16, count 0 2006.173.02:02:35.34#ibcon#about to read 5, iclass 16, count 0 2006.173.02:02:35.34#ibcon#read 5, iclass 16, count 0 2006.173.02:02:35.34#ibcon#about to read 6, iclass 16, count 0 2006.173.02:02:35.34#ibcon#read 6, iclass 16, count 0 2006.173.02:02:35.34#ibcon#end of sib2, iclass 16, count 0 2006.173.02:02:35.34#ibcon#*after write, iclass 16, count 0 2006.173.02:02:35.34#ibcon#*before return 0, iclass 16, count 0 2006.173.02:02:35.34#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.02:02:35.34#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.02:02:35.34#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.02:02:35.34#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.02:02:35.34$vck44/va=8,4 2006.173.02:02:35.34#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.02:02:35.34#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.02:02:35.34#ibcon#ireg 11 cls_cnt 2 2006.173.02:02:35.34#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.02:02:35.40#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.02:02:35.40#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.02:02:35.40#ibcon#enter wrdev, iclass 18, count 2 2006.173.02:02:35.40#ibcon#first serial, iclass 18, count 2 2006.173.02:02:35.40#ibcon#enter sib2, iclass 18, count 2 2006.173.02:02:35.40#ibcon#flushed, iclass 18, count 2 2006.173.02:02:35.40#ibcon#about to write, iclass 18, count 2 2006.173.02:02:35.40#ibcon#wrote, iclass 18, count 2 2006.173.02:02:35.40#ibcon#about to read 3, iclass 18, count 2 2006.173.02:02:35.42#ibcon#read 3, iclass 18, count 2 2006.173.02:02:35.42#ibcon#about to read 4, iclass 18, count 2 2006.173.02:02:35.42#ibcon#read 4, iclass 18, count 2 2006.173.02:02:35.42#ibcon#about to read 5, iclass 18, count 2 2006.173.02:02:35.42#ibcon#read 5, iclass 18, count 2 2006.173.02:02:35.42#ibcon#about to read 6, iclass 18, count 2 2006.173.02:02:35.42#ibcon#read 6, iclass 18, count 2 2006.173.02:02:35.42#ibcon#end of sib2, iclass 18, count 2 2006.173.02:02:35.42#ibcon#*mode == 0, iclass 18, count 2 2006.173.02:02:35.42#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.02:02:35.42#ibcon#[25=AT08-04\r\n] 2006.173.02:02:35.42#ibcon#*before write, iclass 18, count 2 2006.173.02:02:35.42#ibcon#enter sib2, iclass 18, count 2 2006.173.02:02:35.42#ibcon#flushed, iclass 18, count 2 2006.173.02:02:35.42#ibcon#about to write, iclass 18, count 2 2006.173.02:02:35.42#ibcon#wrote, iclass 18, count 2 2006.173.02:02:35.42#ibcon#about to read 3, iclass 18, count 2 2006.173.02:02:35.45#ibcon#read 3, iclass 18, count 2 2006.173.02:02:35.45#ibcon#about to read 4, iclass 18, count 2 2006.173.02:02:35.45#ibcon#read 4, iclass 18, count 2 2006.173.02:02:35.45#ibcon#about to read 5, iclass 18, count 2 2006.173.02:02:35.45#ibcon#read 5, iclass 18, count 2 2006.173.02:02:35.45#ibcon#about to read 6, iclass 18, count 2 2006.173.02:02:35.45#ibcon#read 6, iclass 18, count 2 2006.173.02:02:35.45#ibcon#end of sib2, iclass 18, count 2 2006.173.02:02:35.45#ibcon#*after write, iclass 18, count 2 2006.173.02:02:35.45#ibcon#*before return 0, iclass 18, count 2 2006.173.02:02:35.45#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.02:02:35.45#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.02:02:35.45#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.02:02:35.45#ibcon#ireg 7 cls_cnt 0 2006.173.02:02:35.45#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.02:02:35.57#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.02:02:35.57#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.02:02:35.57#ibcon#enter wrdev, iclass 18, count 0 2006.173.02:02:35.57#ibcon#first serial, iclass 18, count 0 2006.173.02:02:35.57#ibcon#enter sib2, iclass 18, count 0 2006.173.02:02:35.57#ibcon#flushed, iclass 18, count 0 2006.173.02:02:35.57#ibcon#about to write, iclass 18, count 0 2006.173.02:02:35.57#ibcon#wrote, iclass 18, count 0 2006.173.02:02:35.57#ibcon#about to read 3, iclass 18, count 0 2006.173.02:02:35.59#ibcon#read 3, iclass 18, count 0 2006.173.02:02:35.59#ibcon#about to read 4, iclass 18, count 0 2006.173.02:02:35.59#ibcon#read 4, iclass 18, count 0 2006.173.02:02:35.59#ibcon#about to read 5, iclass 18, count 0 2006.173.02:02:35.59#ibcon#read 5, iclass 18, count 0 2006.173.02:02:35.59#ibcon#about to read 6, iclass 18, count 0 2006.173.02:02:35.59#ibcon#read 6, iclass 18, count 0 2006.173.02:02:35.59#ibcon#end of sib2, iclass 18, count 0 2006.173.02:02:35.59#ibcon#*mode == 0, iclass 18, count 0 2006.173.02:02:35.59#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.02:02:35.59#ibcon#[25=USB\r\n] 2006.173.02:02:35.59#ibcon#*before write, iclass 18, count 0 2006.173.02:02:35.59#ibcon#enter sib2, iclass 18, count 0 2006.173.02:02:35.59#ibcon#flushed, iclass 18, count 0 2006.173.02:02:35.59#ibcon#about to write, iclass 18, count 0 2006.173.02:02:35.59#ibcon#wrote, iclass 18, count 0 2006.173.02:02:35.59#ibcon#about to read 3, iclass 18, count 0 2006.173.02:02:35.62#ibcon#read 3, iclass 18, count 0 2006.173.02:02:35.62#ibcon#about to read 4, iclass 18, count 0 2006.173.02:02:35.62#ibcon#read 4, iclass 18, count 0 2006.173.02:02:35.62#ibcon#about to read 5, iclass 18, count 0 2006.173.02:02:35.62#ibcon#read 5, iclass 18, count 0 2006.173.02:02:35.62#ibcon#about to read 6, iclass 18, count 0 2006.173.02:02:35.62#ibcon#read 6, iclass 18, count 0 2006.173.02:02:35.62#ibcon#end of sib2, iclass 18, count 0 2006.173.02:02:35.62#ibcon#*after write, iclass 18, count 0 2006.173.02:02:35.62#ibcon#*before return 0, iclass 18, count 0 2006.173.02:02:35.62#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.02:02:35.62#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.02:02:35.62#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.02:02:35.62#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.02:02:35.62$vck44/vblo=1,629.99 2006.173.02:02:35.62#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.02:02:35.62#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.02:02:35.62#ibcon#ireg 17 cls_cnt 0 2006.173.02:02:35.62#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.02:02:35.62#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.02:02:35.62#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.02:02:35.62#ibcon#enter wrdev, iclass 20, count 0 2006.173.02:02:35.62#ibcon#first serial, iclass 20, count 0 2006.173.02:02:35.62#ibcon#enter sib2, iclass 20, count 0 2006.173.02:02:35.62#ibcon#flushed, iclass 20, count 0 2006.173.02:02:35.62#ibcon#about to write, iclass 20, count 0 2006.173.02:02:35.62#ibcon#wrote, iclass 20, count 0 2006.173.02:02:35.62#ibcon#about to read 3, iclass 20, count 0 2006.173.02:02:35.64#ibcon#read 3, iclass 20, count 0 2006.173.02:02:35.64#ibcon#about to read 4, iclass 20, count 0 2006.173.02:02:35.64#ibcon#read 4, iclass 20, count 0 2006.173.02:02:35.64#ibcon#about to read 5, iclass 20, count 0 2006.173.02:02:35.64#ibcon#read 5, iclass 20, count 0 2006.173.02:02:35.64#ibcon#about to read 6, iclass 20, count 0 2006.173.02:02:35.64#ibcon#read 6, iclass 20, count 0 2006.173.02:02:35.64#ibcon#end of sib2, iclass 20, count 0 2006.173.02:02:35.64#ibcon#*mode == 0, iclass 20, count 0 2006.173.02:02:35.64#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.02:02:35.64#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.02:02:35.64#ibcon#*before write, iclass 20, count 0 2006.173.02:02:35.64#ibcon#enter sib2, iclass 20, count 0 2006.173.02:02:35.64#ibcon#flushed, iclass 20, count 0 2006.173.02:02:35.64#ibcon#about to write, iclass 20, count 0 2006.173.02:02:35.64#ibcon#wrote, iclass 20, count 0 2006.173.02:02:35.64#ibcon#about to read 3, iclass 20, count 0 2006.173.02:02:35.68#ibcon#read 3, iclass 20, count 0 2006.173.02:02:35.68#ibcon#about to read 4, iclass 20, count 0 2006.173.02:02:35.68#ibcon#read 4, iclass 20, count 0 2006.173.02:02:35.68#ibcon#about to read 5, iclass 20, count 0 2006.173.02:02:35.68#ibcon#read 5, iclass 20, count 0 2006.173.02:02:35.68#ibcon#about to read 6, iclass 20, count 0 2006.173.02:02:35.68#ibcon#read 6, iclass 20, count 0 2006.173.02:02:35.68#ibcon#end of sib2, iclass 20, count 0 2006.173.02:02:35.68#ibcon#*after write, iclass 20, count 0 2006.173.02:02:35.68#ibcon#*before return 0, iclass 20, count 0 2006.173.02:02:35.68#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.02:02:35.68#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.02:02:35.68#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.02:02:35.68#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.02:02:35.68$vck44/vb=1,4 2006.173.02:02:35.68#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.02:02:35.68#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.02:02:35.68#ibcon#ireg 11 cls_cnt 2 2006.173.02:02:35.68#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.02:02:35.68#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.02:02:35.68#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.02:02:35.68#ibcon#enter wrdev, iclass 22, count 2 2006.173.02:02:35.68#ibcon#first serial, iclass 22, count 2 2006.173.02:02:35.68#ibcon#enter sib2, iclass 22, count 2 2006.173.02:02:35.68#ibcon#flushed, iclass 22, count 2 2006.173.02:02:35.68#ibcon#about to write, iclass 22, count 2 2006.173.02:02:35.68#ibcon#wrote, iclass 22, count 2 2006.173.02:02:35.68#ibcon#about to read 3, iclass 22, count 2 2006.173.02:02:35.70#ibcon#read 3, iclass 22, count 2 2006.173.02:02:35.70#ibcon#about to read 4, iclass 22, count 2 2006.173.02:02:35.70#ibcon#read 4, iclass 22, count 2 2006.173.02:02:35.70#ibcon#about to read 5, iclass 22, count 2 2006.173.02:02:35.70#ibcon#read 5, iclass 22, count 2 2006.173.02:02:35.70#ibcon#about to read 6, iclass 22, count 2 2006.173.02:02:35.70#ibcon#read 6, iclass 22, count 2 2006.173.02:02:35.70#ibcon#end of sib2, iclass 22, count 2 2006.173.02:02:35.70#ibcon#*mode == 0, iclass 22, count 2 2006.173.02:02:35.70#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.02:02:35.70#ibcon#[27=AT01-04\r\n] 2006.173.02:02:35.70#ibcon#*before write, iclass 22, count 2 2006.173.02:02:35.70#ibcon#enter sib2, iclass 22, count 2 2006.173.02:02:35.70#ibcon#flushed, iclass 22, count 2 2006.173.02:02:35.70#ibcon#about to write, iclass 22, count 2 2006.173.02:02:35.70#ibcon#wrote, iclass 22, count 2 2006.173.02:02:35.70#ibcon#about to read 3, iclass 22, count 2 2006.173.02:02:35.73#ibcon#read 3, iclass 22, count 2 2006.173.02:02:35.73#ibcon#about to read 4, iclass 22, count 2 2006.173.02:02:35.73#ibcon#read 4, iclass 22, count 2 2006.173.02:02:35.73#ibcon#about to read 5, iclass 22, count 2 2006.173.02:02:35.73#ibcon#read 5, iclass 22, count 2 2006.173.02:02:35.73#ibcon#about to read 6, iclass 22, count 2 2006.173.02:02:35.73#ibcon#read 6, iclass 22, count 2 2006.173.02:02:35.73#ibcon#end of sib2, iclass 22, count 2 2006.173.02:02:35.73#ibcon#*after write, iclass 22, count 2 2006.173.02:02:35.73#ibcon#*before return 0, iclass 22, count 2 2006.173.02:02:35.73#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.02:02:35.73#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.02:02:35.73#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.02:02:35.73#ibcon#ireg 7 cls_cnt 0 2006.173.02:02:35.73#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.02:02:35.85#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.02:02:35.85#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.02:02:35.85#ibcon#enter wrdev, iclass 22, count 0 2006.173.02:02:35.85#ibcon#first serial, iclass 22, count 0 2006.173.02:02:35.85#ibcon#enter sib2, iclass 22, count 0 2006.173.02:02:35.85#ibcon#flushed, iclass 22, count 0 2006.173.02:02:35.85#ibcon#about to write, iclass 22, count 0 2006.173.02:02:35.85#ibcon#wrote, iclass 22, count 0 2006.173.02:02:35.85#ibcon#about to read 3, iclass 22, count 0 2006.173.02:02:35.87#ibcon#read 3, iclass 22, count 0 2006.173.02:02:35.87#ibcon#about to read 4, iclass 22, count 0 2006.173.02:02:35.87#ibcon#read 4, iclass 22, count 0 2006.173.02:02:35.87#ibcon#about to read 5, iclass 22, count 0 2006.173.02:02:35.87#ibcon#read 5, iclass 22, count 0 2006.173.02:02:35.87#ibcon#about to read 6, iclass 22, count 0 2006.173.02:02:35.87#ibcon#read 6, iclass 22, count 0 2006.173.02:02:35.87#ibcon#end of sib2, iclass 22, count 0 2006.173.02:02:35.87#ibcon#*mode == 0, iclass 22, count 0 2006.173.02:02:35.87#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.02:02:35.87#ibcon#[27=USB\r\n] 2006.173.02:02:35.87#ibcon#*before write, iclass 22, count 0 2006.173.02:02:35.87#ibcon#enter sib2, iclass 22, count 0 2006.173.02:02:35.87#ibcon#flushed, iclass 22, count 0 2006.173.02:02:35.87#ibcon#about to write, iclass 22, count 0 2006.173.02:02:35.87#ibcon#wrote, iclass 22, count 0 2006.173.02:02:35.87#ibcon#about to read 3, iclass 22, count 0 2006.173.02:02:35.90#ibcon#read 3, iclass 22, count 0 2006.173.02:02:35.90#ibcon#about to read 4, iclass 22, count 0 2006.173.02:02:35.90#ibcon#read 4, iclass 22, count 0 2006.173.02:02:35.90#ibcon#about to read 5, iclass 22, count 0 2006.173.02:02:35.90#ibcon#read 5, iclass 22, count 0 2006.173.02:02:35.90#ibcon#about to read 6, iclass 22, count 0 2006.173.02:02:35.90#ibcon#read 6, iclass 22, count 0 2006.173.02:02:35.90#ibcon#end of sib2, iclass 22, count 0 2006.173.02:02:35.90#ibcon#*after write, iclass 22, count 0 2006.173.02:02:35.90#ibcon#*before return 0, iclass 22, count 0 2006.173.02:02:35.90#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.02:02:35.90#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.02:02:35.90#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.02:02:35.90#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.02:02:35.90$vck44/vblo=2,634.99 2006.173.02:02:35.90#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.02:02:35.90#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.02:02:35.90#ibcon#ireg 17 cls_cnt 0 2006.173.02:02:35.90#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.02:02:35.90#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.02:02:35.90#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.02:02:35.90#ibcon#enter wrdev, iclass 24, count 0 2006.173.02:02:35.90#ibcon#first serial, iclass 24, count 0 2006.173.02:02:35.90#ibcon#enter sib2, iclass 24, count 0 2006.173.02:02:35.90#ibcon#flushed, iclass 24, count 0 2006.173.02:02:35.90#ibcon#about to write, iclass 24, count 0 2006.173.02:02:35.90#ibcon#wrote, iclass 24, count 0 2006.173.02:02:35.90#ibcon#about to read 3, iclass 24, count 0 2006.173.02:02:35.92#ibcon#read 3, iclass 24, count 0 2006.173.02:02:35.92#ibcon#about to read 4, iclass 24, count 0 2006.173.02:02:35.92#ibcon#read 4, iclass 24, count 0 2006.173.02:02:35.92#ibcon#about to read 5, iclass 24, count 0 2006.173.02:02:35.92#ibcon#read 5, iclass 24, count 0 2006.173.02:02:35.92#ibcon#about to read 6, iclass 24, count 0 2006.173.02:02:35.92#ibcon#read 6, iclass 24, count 0 2006.173.02:02:35.92#ibcon#end of sib2, iclass 24, count 0 2006.173.02:02:35.92#ibcon#*mode == 0, iclass 24, count 0 2006.173.02:02:35.92#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.02:02:35.92#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.02:02:35.92#ibcon#*before write, iclass 24, count 0 2006.173.02:02:35.92#ibcon#enter sib2, iclass 24, count 0 2006.173.02:02:35.92#ibcon#flushed, iclass 24, count 0 2006.173.02:02:35.92#ibcon#about to write, iclass 24, count 0 2006.173.02:02:35.92#ibcon#wrote, iclass 24, count 0 2006.173.02:02:35.92#ibcon#about to read 3, iclass 24, count 0 2006.173.02:02:35.96#ibcon#read 3, iclass 24, count 0 2006.173.02:02:35.96#ibcon#about to read 4, iclass 24, count 0 2006.173.02:02:35.96#ibcon#read 4, iclass 24, count 0 2006.173.02:02:35.96#ibcon#about to read 5, iclass 24, count 0 2006.173.02:02:35.96#ibcon#read 5, iclass 24, count 0 2006.173.02:02:35.96#ibcon#about to read 6, iclass 24, count 0 2006.173.02:02:35.96#ibcon#read 6, iclass 24, count 0 2006.173.02:02:35.96#ibcon#end of sib2, iclass 24, count 0 2006.173.02:02:35.96#ibcon#*after write, iclass 24, count 0 2006.173.02:02:35.96#ibcon#*before return 0, iclass 24, count 0 2006.173.02:02:35.96#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.02:02:35.96#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.02:02:35.96#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.02:02:35.96#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.02:02:35.96$vck44/vb=2,4 2006.173.02:02:35.96#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.02:02:35.96#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.02:02:35.96#ibcon#ireg 11 cls_cnt 2 2006.173.02:02:35.96#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.02:02:36.02#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.02:02:36.02#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.02:02:36.02#ibcon#enter wrdev, iclass 26, count 2 2006.173.02:02:36.02#ibcon#first serial, iclass 26, count 2 2006.173.02:02:36.02#ibcon#enter sib2, iclass 26, count 2 2006.173.02:02:36.02#ibcon#flushed, iclass 26, count 2 2006.173.02:02:36.02#ibcon#about to write, iclass 26, count 2 2006.173.02:02:36.02#ibcon#wrote, iclass 26, count 2 2006.173.02:02:36.02#ibcon#about to read 3, iclass 26, count 2 2006.173.02:02:36.04#ibcon#read 3, iclass 26, count 2 2006.173.02:02:36.04#ibcon#about to read 4, iclass 26, count 2 2006.173.02:02:36.04#ibcon#read 4, iclass 26, count 2 2006.173.02:02:36.04#ibcon#about to read 5, iclass 26, count 2 2006.173.02:02:36.04#ibcon#read 5, iclass 26, count 2 2006.173.02:02:36.04#ibcon#about to read 6, iclass 26, count 2 2006.173.02:02:36.04#ibcon#read 6, iclass 26, count 2 2006.173.02:02:36.04#ibcon#end of sib2, iclass 26, count 2 2006.173.02:02:36.04#ibcon#*mode == 0, iclass 26, count 2 2006.173.02:02:36.04#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.02:02:36.04#ibcon#[27=AT02-04\r\n] 2006.173.02:02:36.04#ibcon#*before write, iclass 26, count 2 2006.173.02:02:36.04#ibcon#enter sib2, iclass 26, count 2 2006.173.02:02:36.04#ibcon#flushed, iclass 26, count 2 2006.173.02:02:36.04#ibcon#about to write, iclass 26, count 2 2006.173.02:02:36.04#ibcon#wrote, iclass 26, count 2 2006.173.02:02:36.04#ibcon#about to read 3, iclass 26, count 2 2006.173.02:02:36.07#ibcon#read 3, iclass 26, count 2 2006.173.02:02:36.07#ibcon#about to read 4, iclass 26, count 2 2006.173.02:02:36.07#ibcon#read 4, iclass 26, count 2 2006.173.02:02:36.07#ibcon#about to read 5, iclass 26, count 2 2006.173.02:02:36.07#ibcon#read 5, iclass 26, count 2 2006.173.02:02:36.07#ibcon#about to read 6, iclass 26, count 2 2006.173.02:02:36.07#ibcon#read 6, iclass 26, count 2 2006.173.02:02:36.07#ibcon#end of sib2, iclass 26, count 2 2006.173.02:02:36.07#ibcon#*after write, iclass 26, count 2 2006.173.02:02:36.07#ibcon#*before return 0, iclass 26, count 2 2006.173.02:02:36.07#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.02:02:36.07#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.02:02:36.07#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.02:02:36.07#ibcon#ireg 7 cls_cnt 0 2006.173.02:02:36.07#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.02:02:36.19#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.02:02:36.19#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.02:02:36.19#ibcon#enter wrdev, iclass 26, count 0 2006.173.02:02:36.19#ibcon#first serial, iclass 26, count 0 2006.173.02:02:36.19#ibcon#enter sib2, iclass 26, count 0 2006.173.02:02:36.19#ibcon#flushed, iclass 26, count 0 2006.173.02:02:36.19#ibcon#about to write, iclass 26, count 0 2006.173.02:02:36.19#ibcon#wrote, iclass 26, count 0 2006.173.02:02:36.19#ibcon#about to read 3, iclass 26, count 0 2006.173.02:02:36.21#ibcon#read 3, iclass 26, count 0 2006.173.02:02:36.21#ibcon#about to read 4, iclass 26, count 0 2006.173.02:02:36.21#ibcon#read 4, iclass 26, count 0 2006.173.02:02:36.21#ibcon#about to read 5, iclass 26, count 0 2006.173.02:02:36.21#ibcon#read 5, iclass 26, count 0 2006.173.02:02:36.21#ibcon#about to read 6, iclass 26, count 0 2006.173.02:02:36.21#ibcon#read 6, iclass 26, count 0 2006.173.02:02:36.21#ibcon#end of sib2, iclass 26, count 0 2006.173.02:02:36.21#ibcon#*mode == 0, iclass 26, count 0 2006.173.02:02:36.21#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.02:02:36.21#ibcon#[27=USB\r\n] 2006.173.02:02:36.21#ibcon#*before write, iclass 26, count 0 2006.173.02:02:36.21#ibcon#enter sib2, iclass 26, count 0 2006.173.02:02:36.21#ibcon#flushed, iclass 26, count 0 2006.173.02:02:36.21#ibcon#about to write, iclass 26, count 0 2006.173.02:02:36.21#ibcon#wrote, iclass 26, count 0 2006.173.02:02:36.21#ibcon#about to read 3, iclass 26, count 0 2006.173.02:02:36.24#ibcon#read 3, iclass 26, count 0 2006.173.02:02:36.24#ibcon#about to read 4, iclass 26, count 0 2006.173.02:02:36.24#ibcon#read 4, iclass 26, count 0 2006.173.02:02:36.24#ibcon#about to read 5, iclass 26, count 0 2006.173.02:02:36.24#ibcon#read 5, iclass 26, count 0 2006.173.02:02:36.24#ibcon#about to read 6, iclass 26, count 0 2006.173.02:02:36.24#ibcon#read 6, iclass 26, count 0 2006.173.02:02:36.24#ibcon#end of sib2, iclass 26, count 0 2006.173.02:02:36.24#ibcon#*after write, iclass 26, count 0 2006.173.02:02:36.24#ibcon#*before return 0, iclass 26, count 0 2006.173.02:02:36.24#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.02:02:36.24#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.02:02:36.24#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.02:02:36.24#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.02:02:36.24$vck44/vblo=3,649.99 2006.173.02:02:36.24#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.02:02:36.24#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.02:02:36.24#ibcon#ireg 17 cls_cnt 0 2006.173.02:02:36.24#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.02:02:36.24#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.02:02:36.24#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.02:02:36.24#ibcon#enter wrdev, iclass 28, count 0 2006.173.02:02:36.24#ibcon#first serial, iclass 28, count 0 2006.173.02:02:36.24#ibcon#enter sib2, iclass 28, count 0 2006.173.02:02:36.24#ibcon#flushed, iclass 28, count 0 2006.173.02:02:36.24#ibcon#about to write, iclass 28, count 0 2006.173.02:02:36.24#ibcon#wrote, iclass 28, count 0 2006.173.02:02:36.24#ibcon#about to read 3, iclass 28, count 0 2006.173.02:02:36.26#ibcon#read 3, iclass 28, count 0 2006.173.02:02:36.26#ibcon#about to read 4, iclass 28, count 0 2006.173.02:02:36.26#ibcon#read 4, iclass 28, count 0 2006.173.02:02:36.26#ibcon#about to read 5, iclass 28, count 0 2006.173.02:02:36.26#ibcon#read 5, iclass 28, count 0 2006.173.02:02:36.26#ibcon#about to read 6, iclass 28, count 0 2006.173.02:02:36.26#ibcon#read 6, iclass 28, count 0 2006.173.02:02:36.26#ibcon#end of sib2, iclass 28, count 0 2006.173.02:02:36.26#ibcon#*mode == 0, iclass 28, count 0 2006.173.02:02:36.26#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.02:02:36.26#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.02:02:36.26#ibcon#*before write, iclass 28, count 0 2006.173.02:02:36.26#ibcon#enter sib2, iclass 28, count 0 2006.173.02:02:36.26#ibcon#flushed, iclass 28, count 0 2006.173.02:02:36.26#ibcon#about to write, iclass 28, count 0 2006.173.02:02:36.26#ibcon#wrote, iclass 28, count 0 2006.173.02:02:36.26#ibcon#about to read 3, iclass 28, count 0 2006.173.02:02:36.30#ibcon#read 3, iclass 28, count 0 2006.173.02:02:36.30#ibcon#about to read 4, iclass 28, count 0 2006.173.02:02:36.30#ibcon#read 4, iclass 28, count 0 2006.173.02:02:36.30#ibcon#about to read 5, iclass 28, count 0 2006.173.02:02:36.30#ibcon#read 5, iclass 28, count 0 2006.173.02:02:36.30#ibcon#about to read 6, iclass 28, count 0 2006.173.02:02:36.30#ibcon#read 6, iclass 28, count 0 2006.173.02:02:36.30#ibcon#end of sib2, iclass 28, count 0 2006.173.02:02:36.30#ibcon#*after write, iclass 28, count 0 2006.173.02:02:36.30#ibcon#*before return 0, iclass 28, count 0 2006.173.02:02:36.30#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.02:02:36.30#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.02:02:36.30#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.02:02:36.30#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.02:02:36.30$vck44/vb=3,4 2006.173.02:02:36.30#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.02:02:36.30#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.02:02:36.30#ibcon#ireg 11 cls_cnt 2 2006.173.02:02:36.30#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.02:02:36.36#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.02:02:36.36#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.02:02:36.36#ibcon#enter wrdev, iclass 30, count 2 2006.173.02:02:36.36#ibcon#first serial, iclass 30, count 2 2006.173.02:02:36.36#ibcon#enter sib2, iclass 30, count 2 2006.173.02:02:36.36#ibcon#flushed, iclass 30, count 2 2006.173.02:02:36.36#ibcon#about to write, iclass 30, count 2 2006.173.02:02:36.36#ibcon#wrote, iclass 30, count 2 2006.173.02:02:36.36#ibcon#about to read 3, iclass 30, count 2 2006.173.02:02:36.38#ibcon#read 3, iclass 30, count 2 2006.173.02:02:36.38#ibcon#about to read 4, iclass 30, count 2 2006.173.02:02:36.38#ibcon#read 4, iclass 30, count 2 2006.173.02:02:36.38#ibcon#about to read 5, iclass 30, count 2 2006.173.02:02:36.38#ibcon#read 5, iclass 30, count 2 2006.173.02:02:36.38#ibcon#about to read 6, iclass 30, count 2 2006.173.02:02:36.38#ibcon#read 6, iclass 30, count 2 2006.173.02:02:36.38#ibcon#end of sib2, iclass 30, count 2 2006.173.02:02:36.38#ibcon#*mode == 0, iclass 30, count 2 2006.173.02:02:36.38#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.02:02:36.38#ibcon#[27=AT03-04\r\n] 2006.173.02:02:36.38#ibcon#*before write, iclass 30, count 2 2006.173.02:02:36.38#ibcon#enter sib2, iclass 30, count 2 2006.173.02:02:36.38#ibcon#flushed, iclass 30, count 2 2006.173.02:02:36.38#ibcon#about to write, iclass 30, count 2 2006.173.02:02:36.38#ibcon#wrote, iclass 30, count 2 2006.173.02:02:36.38#ibcon#about to read 3, iclass 30, count 2 2006.173.02:02:36.41#ibcon#read 3, iclass 30, count 2 2006.173.02:02:36.41#ibcon#about to read 4, iclass 30, count 2 2006.173.02:02:36.41#ibcon#read 4, iclass 30, count 2 2006.173.02:02:36.41#ibcon#about to read 5, iclass 30, count 2 2006.173.02:02:36.41#ibcon#read 5, iclass 30, count 2 2006.173.02:02:36.41#ibcon#about to read 6, iclass 30, count 2 2006.173.02:02:36.41#ibcon#read 6, iclass 30, count 2 2006.173.02:02:36.41#ibcon#end of sib2, iclass 30, count 2 2006.173.02:02:36.41#ibcon#*after write, iclass 30, count 2 2006.173.02:02:36.41#ibcon#*before return 0, iclass 30, count 2 2006.173.02:02:36.41#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.02:02:36.41#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.02:02:36.41#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.02:02:36.41#ibcon#ireg 7 cls_cnt 0 2006.173.02:02:36.41#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.02:02:36.53#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.02:02:36.53#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.02:02:36.53#ibcon#enter wrdev, iclass 30, count 0 2006.173.02:02:36.53#ibcon#first serial, iclass 30, count 0 2006.173.02:02:36.53#ibcon#enter sib2, iclass 30, count 0 2006.173.02:02:36.53#ibcon#flushed, iclass 30, count 0 2006.173.02:02:36.53#ibcon#about to write, iclass 30, count 0 2006.173.02:02:36.53#ibcon#wrote, iclass 30, count 0 2006.173.02:02:36.53#ibcon#about to read 3, iclass 30, count 0 2006.173.02:02:36.55#ibcon#read 3, iclass 30, count 0 2006.173.02:02:36.55#ibcon#about to read 4, iclass 30, count 0 2006.173.02:02:36.55#ibcon#read 4, iclass 30, count 0 2006.173.02:02:36.55#ibcon#about to read 5, iclass 30, count 0 2006.173.02:02:36.55#ibcon#read 5, iclass 30, count 0 2006.173.02:02:36.55#ibcon#about to read 6, iclass 30, count 0 2006.173.02:02:36.55#ibcon#read 6, iclass 30, count 0 2006.173.02:02:36.55#ibcon#end of sib2, iclass 30, count 0 2006.173.02:02:36.55#ibcon#*mode == 0, iclass 30, count 0 2006.173.02:02:36.55#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.02:02:36.55#ibcon#[27=USB\r\n] 2006.173.02:02:36.55#ibcon#*before write, iclass 30, count 0 2006.173.02:02:36.55#ibcon#enter sib2, iclass 30, count 0 2006.173.02:02:36.55#ibcon#flushed, iclass 30, count 0 2006.173.02:02:36.55#ibcon#about to write, iclass 30, count 0 2006.173.02:02:36.55#ibcon#wrote, iclass 30, count 0 2006.173.02:02:36.55#ibcon#about to read 3, iclass 30, count 0 2006.173.02:02:36.58#ibcon#read 3, iclass 30, count 0 2006.173.02:02:36.58#ibcon#about to read 4, iclass 30, count 0 2006.173.02:02:36.58#ibcon#read 4, iclass 30, count 0 2006.173.02:02:36.58#ibcon#about to read 5, iclass 30, count 0 2006.173.02:02:36.58#ibcon#read 5, iclass 30, count 0 2006.173.02:02:36.58#ibcon#about to read 6, iclass 30, count 0 2006.173.02:02:36.58#ibcon#read 6, iclass 30, count 0 2006.173.02:02:36.58#ibcon#end of sib2, iclass 30, count 0 2006.173.02:02:36.58#ibcon#*after write, iclass 30, count 0 2006.173.02:02:36.58#ibcon#*before return 0, iclass 30, count 0 2006.173.02:02:36.58#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.02:02:36.58#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.02:02:36.58#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.02:02:36.58#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.02:02:36.58$vck44/vblo=4,679.99 2006.173.02:02:36.58#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.02:02:36.58#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.02:02:36.58#ibcon#ireg 17 cls_cnt 0 2006.173.02:02:36.58#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.02:02:36.58#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.02:02:36.58#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.02:02:36.58#ibcon#enter wrdev, iclass 32, count 0 2006.173.02:02:36.58#ibcon#first serial, iclass 32, count 0 2006.173.02:02:36.58#ibcon#enter sib2, iclass 32, count 0 2006.173.02:02:36.58#ibcon#flushed, iclass 32, count 0 2006.173.02:02:36.58#ibcon#about to write, iclass 32, count 0 2006.173.02:02:36.58#ibcon#wrote, iclass 32, count 0 2006.173.02:02:36.58#ibcon#about to read 3, iclass 32, count 0 2006.173.02:02:36.60#ibcon#read 3, iclass 32, count 0 2006.173.02:02:36.60#ibcon#about to read 4, iclass 32, count 0 2006.173.02:02:36.60#ibcon#read 4, iclass 32, count 0 2006.173.02:02:36.60#ibcon#about to read 5, iclass 32, count 0 2006.173.02:02:36.60#ibcon#read 5, iclass 32, count 0 2006.173.02:02:36.60#ibcon#about to read 6, iclass 32, count 0 2006.173.02:02:36.60#ibcon#read 6, iclass 32, count 0 2006.173.02:02:36.60#ibcon#end of sib2, iclass 32, count 0 2006.173.02:02:36.60#ibcon#*mode == 0, iclass 32, count 0 2006.173.02:02:36.60#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.02:02:36.60#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.02:02:36.60#ibcon#*before write, iclass 32, count 0 2006.173.02:02:36.60#ibcon#enter sib2, iclass 32, count 0 2006.173.02:02:36.60#ibcon#flushed, iclass 32, count 0 2006.173.02:02:36.60#ibcon#about to write, iclass 32, count 0 2006.173.02:02:36.60#ibcon#wrote, iclass 32, count 0 2006.173.02:02:36.60#ibcon#about to read 3, iclass 32, count 0 2006.173.02:02:36.64#ibcon#read 3, iclass 32, count 0 2006.173.02:02:36.64#ibcon#about to read 4, iclass 32, count 0 2006.173.02:02:36.64#ibcon#read 4, iclass 32, count 0 2006.173.02:02:36.64#ibcon#about to read 5, iclass 32, count 0 2006.173.02:02:36.64#ibcon#read 5, iclass 32, count 0 2006.173.02:02:36.64#ibcon#about to read 6, iclass 32, count 0 2006.173.02:02:36.64#ibcon#read 6, iclass 32, count 0 2006.173.02:02:36.64#ibcon#end of sib2, iclass 32, count 0 2006.173.02:02:36.64#ibcon#*after write, iclass 32, count 0 2006.173.02:02:36.64#ibcon#*before return 0, iclass 32, count 0 2006.173.02:02:36.64#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.02:02:36.64#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.02:02:36.64#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.02:02:36.64#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.02:02:36.64$vck44/vb=4,4 2006.173.02:02:36.64#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.02:02:36.64#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.02:02:36.64#ibcon#ireg 11 cls_cnt 2 2006.173.02:02:36.64#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.02:02:36.70#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.02:02:36.70#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.02:02:36.70#ibcon#enter wrdev, iclass 34, count 2 2006.173.02:02:36.70#ibcon#first serial, iclass 34, count 2 2006.173.02:02:36.70#ibcon#enter sib2, iclass 34, count 2 2006.173.02:02:36.70#ibcon#flushed, iclass 34, count 2 2006.173.02:02:36.70#ibcon#about to write, iclass 34, count 2 2006.173.02:02:36.70#ibcon#wrote, iclass 34, count 2 2006.173.02:02:36.70#ibcon#about to read 3, iclass 34, count 2 2006.173.02:02:36.72#ibcon#read 3, iclass 34, count 2 2006.173.02:02:36.72#ibcon#about to read 4, iclass 34, count 2 2006.173.02:02:36.72#ibcon#read 4, iclass 34, count 2 2006.173.02:02:36.72#ibcon#about to read 5, iclass 34, count 2 2006.173.02:02:36.72#ibcon#read 5, iclass 34, count 2 2006.173.02:02:36.72#ibcon#about to read 6, iclass 34, count 2 2006.173.02:02:36.72#ibcon#read 6, iclass 34, count 2 2006.173.02:02:36.72#ibcon#end of sib2, iclass 34, count 2 2006.173.02:02:36.72#ibcon#*mode == 0, iclass 34, count 2 2006.173.02:02:36.72#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.02:02:36.72#ibcon#[27=AT04-04\r\n] 2006.173.02:02:36.72#ibcon#*before write, iclass 34, count 2 2006.173.02:02:36.72#ibcon#enter sib2, iclass 34, count 2 2006.173.02:02:36.72#ibcon#flushed, iclass 34, count 2 2006.173.02:02:36.72#ibcon#about to write, iclass 34, count 2 2006.173.02:02:36.72#ibcon#wrote, iclass 34, count 2 2006.173.02:02:36.72#ibcon#about to read 3, iclass 34, count 2 2006.173.02:02:36.75#ibcon#read 3, iclass 34, count 2 2006.173.02:02:36.75#ibcon#about to read 4, iclass 34, count 2 2006.173.02:02:36.75#ibcon#read 4, iclass 34, count 2 2006.173.02:02:36.75#ibcon#about to read 5, iclass 34, count 2 2006.173.02:02:36.75#ibcon#read 5, iclass 34, count 2 2006.173.02:02:36.75#ibcon#about to read 6, iclass 34, count 2 2006.173.02:02:36.75#ibcon#read 6, iclass 34, count 2 2006.173.02:02:36.75#ibcon#end of sib2, iclass 34, count 2 2006.173.02:02:36.75#ibcon#*after write, iclass 34, count 2 2006.173.02:02:36.75#ibcon#*before return 0, iclass 34, count 2 2006.173.02:02:36.75#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.02:02:36.75#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.02:02:36.75#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.02:02:36.75#ibcon#ireg 7 cls_cnt 0 2006.173.02:02:36.75#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.02:02:36.87#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.02:02:36.87#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.02:02:36.87#ibcon#enter wrdev, iclass 34, count 0 2006.173.02:02:36.87#ibcon#first serial, iclass 34, count 0 2006.173.02:02:36.87#ibcon#enter sib2, iclass 34, count 0 2006.173.02:02:36.87#ibcon#flushed, iclass 34, count 0 2006.173.02:02:36.87#ibcon#about to write, iclass 34, count 0 2006.173.02:02:36.87#ibcon#wrote, iclass 34, count 0 2006.173.02:02:36.87#ibcon#about to read 3, iclass 34, count 0 2006.173.02:02:36.89#ibcon#read 3, iclass 34, count 0 2006.173.02:02:36.89#ibcon#about to read 4, iclass 34, count 0 2006.173.02:02:36.89#ibcon#read 4, iclass 34, count 0 2006.173.02:02:36.89#ibcon#about to read 5, iclass 34, count 0 2006.173.02:02:36.89#ibcon#read 5, iclass 34, count 0 2006.173.02:02:36.89#ibcon#about to read 6, iclass 34, count 0 2006.173.02:02:36.89#ibcon#read 6, iclass 34, count 0 2006.173.02:02:36.89#ibcon#end of sib2, iclass 34, count 0 2006.173.02:02:36.89#ibcon#*mode == 0, iclass 34, count 0 2006.173.02:02:36.89#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.02:02:36.89#ibcon#[27=USB\r\n] 2006.173.02:02:36.89#ibcon#*before write, iclass 34, count 0 2006.173.02:02:36.89#ibcon#enter sib2, iclass 34, count 0 2006.173.02:02:36.89#ibcon#flushed, iclass 34, count 0 2006.173.02:02:36.89#ibcon#about to write, iclass 34, count 0 2006.173.02:02:36.89#ibcon#wrote, iclass 34, count 0 2006.173.02:02:36.89#ibcon#about to read 3, iclass 34, count 0 2006.173.02:02:36.92#ibcon#read 3, iclass 34, count 0 2006.173.02:02:36.92#ibcon#about to read 4, iclass 34, count 0 2006.173.02:02:36.92#ibcon#read 4, iclass 34, count 0 2006.173.02:02:36.92#ibcon#about to read 5, iclass 34, count 0 2006.173.02:02:36.92#ibcon#read 5, iclass 34, count 0 2006.173.02:02:36.92#ibcon#about to read 6, iclass 34, count 0 2006.173.02:02:36.92#ibcon#read 6, iclass 34, count 0 2006.173.02:02:36.92#ibcon#end of sib2, iclass 34, count 0 2006.173.02:02:36.92#ibcon#*after write, iclass 34, count 0 2006.173.02:02:36.92#ibcon#*before return 0, iclass 34, count 0 2006.173.02:02:36.92#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.02:02:36.92#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.02:02:36.92#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.02:02:36.92#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.02:02:36.92$vck44/vblo=5,709.99 2006.173.02:02:36.92#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.02:02:36.92#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.02:02:36.92#ibcon#ireg 17 cls_cnt 0 2006.173.02:02:36.92#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.02:02:36.92#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.02:02:36.92#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.02:02:36.92#ibcon#enter wrdev, iclass 36, count 0 2006.173.02:02:36.92#ibcon#first serial, iclass 36, count 0 2006.173.02:02:36.92#ibcon#enter sib2, iclass 36, count 0 2006.173.02:02:36.92#ibcon#flushed, iclass 36, count 0 2006.173.02:02:36.92#ibcon#about to write, iclass 36, count 0 2006.173.02:02:36.92#ibcon#wrote, iclass 36, count 0 2006.173.02:02:36.92#ibcon#about to read 3, iclass 36, count 0 2006.173.02:02:36.94#ibcon#read 3, iclass 36, count 0 2006.173.02:02:36.94#ibcon#about to read 4, iclass 36, count 0 2006.173.02:02:36.94#ibcon#read 4, iclass 36, count 0 2006.173.02:02:36.94#ibcon#about to read 5, iclass 36, count 0 2006.173.02:02:36.94#ibcon#read 5, iclass 36, count 0 2006.173.02:02:36.94#ibcon#about to read 6, iclass 36, count 0 2006.173.02:02:36.94#ibcon#read 6, iclass 36, count 0 2006.173.02:02:36.94#ibcon#end of sib2, iclass 36, count 0 2006.173.02:02:36.94#ibcon#*mode == 0, iclass 36, count 0 2006.173.02:02:36.94#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.02:02:36.94#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.02:02:36.94#ibcon#*before write, iclass 36, count 0 2006.173.02:02:36.94#ibcon#enter sib2, iclass 36, count 0 2006.173.02:02:36.94#ibcon#flushed, iclass 36, count 0 2006.173.02:02:36.94#ibcon#about to write, iclass 36, count 0 2006.173.02:02:36.94#ibcon#wrote, iclass 36, count 0 2006.173.02:02:36.94#ibcon#about to read 3, iclass 36, count 0 2006.173.02:02:36.98#ibcon#read 3, iclass 36, count 0 2006.173.02:02:36.98#ibcon#about to read 4, iclass 36, count 0 2006.173.02:02:36.98#ibcon#read 4, iclass 36, count 0 2006.173.02:02:36.98#ibcon#about to read 5, iclass 36, count 0 2006.173.02:02:36.98#ibcon#read 5, iclass 36, count 0 2006.173.02:02:36.98#ibcon#about to read 6, iclass 36, count 0 2006.173.02:02:36.98#ibcon#read 6, iclass 36, count 0 2006.173.02:02:36.98#ibcon#end of sib2, iclass 36, count 0 2006.173.02:02:36.98#ibcon#*after write, iclass 36, count 0 2006.173.02:02:36.98#ibcon#*before return 0, iclass 36, count 0 2006.173.02:02:36.98#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.02:02:36.98#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.02:02:36.98#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.02:02:36.98#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.02:02:36.98$vck44/vb=5,4 2006.173.02:02:36.98#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.02:02:36.98#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.02:02:36.98#ibcon#ireg 11 cls_cnt 2 2006.173.02:02:36.98#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.02:02:37.04#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.02:02:37.04#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.02:02:37.04#ibcon#enter wrdev, iclass 38, count 2 2006.173.02:02:37.04#ibcon#first serial, iclass 38, count 2 2006.173.02:02:37.04#ibcon#enter sib2, iclass 38, count 2 2006.173.02:02:37.04#ibcon#flushed, iclass 38, count 2 2006.173.02:02:37.04#ibcon#about to write, iclass 38, count 2 2006.173.02:02:37.04#ibcon#wrote, iclass 38, count 2 2006.173.02:02:37.04#ibcon#about to read 3, iclass 38, count 2 2006.173.02:02:37.06#ibcon#read 3, iclass 38, count 2 2006.173.02:02:37.06#ibcon#about to read 4, iclass 38, count 2 2006.173.02:02:37.06#ibcon#read 4, iclass 38, count 2 2006.173.02:02:37.06#ibcon#about to read 5, iclass 38, count 2 2006.173.02:02:37.06#ibcon#read 5, iclass 38, count 2 2006.173.02:02:37.06#ibcon#about to read 6, iclass 38, count 2 2006.173.02:02:37.06#ibcon#read 6, iclass 38, count 2 2006.173.02:02:37.06#ibcon#end of sib2, iclass 38, count 2 2006.173.02:02:37.06#ibcon#*mode == 0, iclass 38, count 2 2006.173.02:02:37.06#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.02:02:37.06#ibcon#[27=AT05-04\r\n] 2006.173.02:02:37.06#ibcon#*before write, iclass 38, count 2 2006.173.02:02:37.06#ibcon#enter sib2, iclass 38, count 2 2006.173.02:02:37.06#ibcon#flushed, iclass 38, count 2 2006.173.02:02:37.06#ibcon#about to write, iclass 38, count 2 2006.173.02:02:37.06#ibcon#wrote, iclass 38, count 2 2006.173.02:02:37.06#ibcon#about to read 3, iclass 38, count 2 2006.173.02:02:37.09#ibcon#read 3, iclass 38, count 2 2006.173.02:02:37.09#ibcon#about to read 4, iclass 38, count 2 2006.173.02:02:37.09#ibcon#read 4, iclass 38, count 2 2006.173.02:02:37.09#ibcon#about to read 5, iclass 38, count 2 2006.173.02:02:37.09#ibcon#read 5, iclass 38, count 2 2006.173.02:02:37.09#ibcon#about to read 6, iclass 38, count 2 2006.173.02:02:37.09#ibcon#read 6, iclass 38, count 2 2006.173.02:02:37.09#ibcon#end of sib2, iclass 38, count 2 2006.173.02:02:37.09#ibcon#*after write, iclass 38, count 2 2006.173.02:02:37.09#ibcon#*before return 0, iclass 38, count 2 2006.173.02:02:37.09#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.02:02:37.09#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.02:02:37.09#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.02:02:37.09#ibcon#ireg 7 cls_cnt 0 2006.173.02:02:37.09#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.02:02:37.21#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.02:02:37.21#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.02:02:37.21#ibcon#enter wrdev, iclass 38, count 0 2006.173.02:02:37.21#ibcon#first serial, iclass 38, count 0 2006.173.02:02:37.21#ibcon#enter sib2, iclass 38, count 0 2006.173.02:02:37.21#ibcon#flushed, iclass 38, count 0 2006.173.02:02:37.21#ibcon#about to write, iclass 38, count 0 2006.173.02:02:37.21#ibcon#wrote, iclass 38, count 0 2006.173.02:02:37.21#ibcon#about to read 3, iclass 38, count 0 2006.173.02:02:37.23#ibcon#read 3, iclass 38, count 0 2006.173.02:02:37.23#ibcon#about to read 4, iclass 38, count 0 2006.173.02:02:37.23#ibcon#read 4, iclass 38, count 0 2006.173.02:02:37.23#ibcon#about to read 5, iclass 38, count 0 2006.173.02:02:37.23#ibcon#read 5, iclass 38, count 0 2006.173.02:02:37.23#ibcon#about to read 6, iclass 38, count 0 2006.173.02:02:37.23#ibcon#read 6, iclass 38, count 0 2006.173.02:02:37.23#ibcon#end of sib2, iclass 38, count 0 2006.173.02:02:37.23#ibcon#*mode == 0, iclass 38, count 0 2006.173.02:02:37.23#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.02:02:37.23#ibcon#[27=USB\r\n] 2006.173.02:02:37.23#ibcon#*before write, iclass 38, count 0 2006.173.02:02:37.23#ibcon#enter sib2, iclass 38, count 0 2006.173.02:02:37.23#ibcon#flushed, iclass 38, count 0 2006.173.02:02:37.23#ibcon#about to write, iclass 38, count 0 2006.173.02:02:37.23#ibcon#wrote, iclass 38, count 0 2006.173.02:02:37.23#ibcon#about to read 3, iclass 38, count 0 2006.173.02:02:37.26#ibcon#read 3, iclass 38, count 0 2006.173.02:02:37.26#ibcon#about to read 4, iclass 38, count 0 2006.173.02:02:37.26#ibcon#read 4, iclass 38, count 0 2006.173.02:02:37.26#ibcon#about to read 5, iclass 38, count 0 2006.173.02:02:37.26#ibcon#read 5, iclass 38, count 0 2006.173.02:02:37.26#ibcon#about to read 6, iclass 38, count 0 2006.173.02:02:37.26#ibcon#read 6, iclass 38, count 0 2006.173.02:02:37.26#ibcon#end of sib2, iclass 38, count 0 2006.173.02:02:37.26#ibcon#*after write, iclass 38, count 0 2006.173.02:02:37.26#ibcon#*before return 0, iclass 38, count 0 2006.173.02:02:37.26#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.02:02:37.26#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.02:02:37.26#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.02:02:37.26#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.02:02:37.26$vck44/vblo=6,719.99 2006.173.02:02:37.26#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.02:02:37.26#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.02:02:37.26#ibcon#ireg 17 cls_cnt 0 2006.173.02:02:37.26#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.02:02:37.26#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.02:02:37.26#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.02:02:37.26#ibcon#enter wrdev, iclass 40, count 0 2006.173.02:02:37.26#ibcon#first serial, iclass 40, count 0 2006.173.02:02:37.26#ibcon#enter sib2, iclass 40, count 0 2006.173.02:02:37.26#ibcon#flushed, iclass 40, count 0 2006.173.02:02:37.26#ibcon#about to write, iclass 40, count 0 2006.173.02:02:37.26#ibcon#wrote, iclass 40, count 0 2006.173.02:02:37.26#ibcon#about to read 3, iclass 40, count 0 2006.173.02:02:37.28#ibcon#read 3, iclass 40, count 0 2006.173.02:02:37.28#ibcon#about to read 4, iclass 40, count 0 2006.173.02:02:37.28#ibcon#read 4, iclass 40, count 0 2006.173.02:02:37.28#ibcon#about to read 5, iclass 40, count 0 2006.173.02:02:37.28#ibcon#read 5, iclass 40, count 0 2006.173.02:02:37.28#ibcon#about to read 6, iclass 40, count 0 2006.173.02:02:37.28#ibcon#read 6, iclass 40, count 0 2006.173.02:02:37.28#ibcon#end of sib2, iclass 40, count 0 2006.173.02:02:37.28#ibcon#*mode == 0, iclass 40, count 0 2006.173.02:02:37.28#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.02:02:37.28#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.02:02:37.28#ibcon#*before write, iclass 40, count 0 2006.173.02:02:37.28#ibcon#enter sib2, iclass 40, count 0 2006.173.02:02:37.28#ibcon#flushed, iclass 40, count 0 2006.173.02:02:37.28#ibcon#about to write, iclass 40, count 0 2006.173.02:02:37.28#ibcon#wrote, iclass 40, count 0 2006.173.02:02:37.28#ibcon#about to read 3, iclass 40, count 0 2006.173.02:02:37.32#ibcon#read 3, iclass 40, count 0 2006.173.02:02:37.32#ibcon#about to read 4, iclass 40, count 0 2006.173.02:02:37.32#ibcon#read 4, iclass 40, count 0 2006.173.02:02:37.32#ibcon#about to read 5, iclass 40, count 0 2006.173.02:02:37.32#ibcon#read 5, iclass 40, count 0 2006.173.02:02:37.32#ibcon#about to read 6, iclass 40, count 0 2006.173.02:02:37.32#ibcon#read 6, iclass 40, count 0 2006.173.02:02:37.32#ibcon#end of sib2, iclass 40, count 0 2006.173.02:02:37.32#ibcon#*after write, iclass 40, count 0 2006.173.02:02:37.32#ibcon#*before return 0, iclass 40, count 0 2006.173.02:02:37.32#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.02:02:37.32#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.02:02:37.32#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.02:02:37.32#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.02:02:37.32$vck44/vb=6,4 2006.173.02:02:37.32#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.02:02:37.32#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.02:02:37.32#ibcon#ireg 11 cls_cnt 2 2006.173.02:02:37.32#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.02:02:37.38#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.02:02:37.38#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.02:02:37.38#ibcon#enter wrdev, iclass 4, count 2 2006.173.02:02:37.38#ibcon#first serial, iclass 4, count 2 2006.173.02:02:37.38#ibcon#enter sib2, iclass 4, count 2 2006.173.02:02:37.38#ibcon#flushed, iclass 4, count 2 2006.173.02:02:37.38#ibcon#about to write, iclass 4, count 2 2006.173.02:02:37.38#ibcon#wrote, iclass 4, count 2 2006.173.02:02:37.38#ibcon#about to read 3, iclass 4, count 2 2006.173.02:02:37.40#ibcon#read 3, iclass 4, count 2 2006.173.02:02:37.40#ibcon#about to read 4, iclass 4, count 2 2006.173.02:02:37.40#ibcon#read 4, iclass 4, count 2 2006.173.02:02:37.40#ibcon#about to read 5, iclass 4, count 2 2006.173.02:02:37.40#ibcon#read 5, iclass 4, count 2 2006.173.02:02:37.40#ibcon#about to read 6, iclass 4, count 2 2006.173.02:02:37.40#ibcon#read 6, iclass 4, count 2 2006.173.02:02:37.40#ibcon#end of sib2, iclass 4, count 2 2006.173.02:02:37.40#ibcon#*mode == 0, iclass 4, count 2 2006.173.02:02:37.40#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.02:02:37.40#ibcon#[27=AT06-04\r\n] 2006.173.02:02:37.40#ibcon#*before write, iclass 4, count 2 2006.173.02:02:37.40#ibcon#enter sib2, iclass 4, count 2 2006.173.02:02:37.40#ibcon#flushed, iclass 4, count 2 2006.173.02:02:37.40#ibcon#about to write, iclass 4, count 2 2006.173.02:02:37.40#ibcon#wrote, iclass 4, count 2 2006.173.02:02:37.40#ibcon#about to read 3, iclass 4, count 2 2006.173.02:02:37.43#ibcon#read 3, iclass 4, count 2 2006.173.02:02:37.43#ibcon#about to read 4, iclass 4, count 2 2006.173.02:02:37.43#ibcon#read 4, iclass 4, count 2 2006.173.02:02:37.43#ibcon#about to read 5, iclass 4, count 2 2006.173.02:02:37.43#ibcon#read 5, iclass 4, count 2 2006.173.02:02:37.43#ibcon#about to read 6, iclass 4, count 2 2006.173.02:02:37.43#ibcon#read 6, iclass 4, count 2 2006.173.02:02:37.43#ibcon#end of sib2, iclass 4, count 2 2006.173.02:02:37.43#ibcon#*after write, iclass 4, count 2 2006.173.02:02:37.43#ibcon#*before return 0, iclass 4, count 2 2006.173.02:02:37.43#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.02:02:37.43#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.02:02:37.43#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.02:02:37.43#ibcon#ireg 7 cls_cnt 0 2006.173.02:02:37.43#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.02:02:37.55#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.02:02:37.55#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.02:02:37.55#ibcon#enter wrdev, iclass 4, count 0 2006.173.02:02:37.55#ibcon#first serial, iclass 4, count 0 2006.173.02:02:37.55#ibcon#enter sib2, iclass 4, count 0 2006.173.02:02:37.55#ibcon#flushed, iclass 4, count 0 2006.173.02:02:37.55#ibcon#about to write, iclass 4, count 0 2006.173.02:02:37.55#ibcon#wrote, iclass 4, count 0 2006.173.02:02:37.55#ibcon#about to read 3, iclass 4, count 0 2006.173.02:02:37.57#ibcon#read 3, iclass 4, count 0 2006.173.02:02:37.57#ibcon#about to read 4, iclass 4, count 0 2006.173.02:02:37.57#ibcon#read 4, iclass 4, count 0 2006.173.02:02:37.57#ibcon#about to read 5, iclass 4, count 0 2006.173.02:02:37.57#ibcon#read 5, iclass 4, count 0 2006.173.02:02:37.57#ibcon#about to read 6, iclass 4, count 0 2006.173.02:02:37.57#ibcon#read 6, iclass 4, count 0 2006.173.02:02:37.57#ibcon#end of sib2, iclass 4, count 0 2006.173.02:02:37.57#ibcon#*mode == 0, iclass 4, count 0 2006.173.02:02:37.57#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.02:02:37.57#ibcon#[27=USB\r\n] 2006.173.02:02:37.57#ibcon#*before write, iclass 4, count 0 2006.173.02:02:37.57#ibcon#enter sib2, iclass 4, count 0 2006.173.02:02:37.57#ibcon#flushed, iclass 4, count 0 2006.173.02:02:37.57#ibcon#about to write, iclass 4, count 0 2006.173.02:02:37.57#ibcon#wrote, iclass 4, count 0 2006.173.02:02:37.57#ibcon#about to read 3, iclass 4, count 0 2006.173.02:02:37.60#ibcon#read 3, iclass 4, count 0 2006.173.02:02:37.60#ibcon#about to read 4, iclass 4, count 0 2006.173.02:02:37.60#ibcon#read 4, iclass 4, count 0 2006.173.02:02:37.60#ibcon#about to read 5, iclass 4, count 0 2006.173.02:02:37.60#ibcon#read 5, iclass 4, count 0 2006.173.02:02:37.60#ibcon#about to read 6, iclass 4, count 0 2006.173.02:02:37.60#ibcon#read 6, iclass 4, count 0 2006.173.02:02:37.60#ibcon#end of sib2, iclass 4, count 0 2006.173.02:02:37.60#ibcon#*after write, iclass 4, count 0 2006.173.02:02:37.60#ibcon#*before return 0, iclass 4, count 0 2006.173.02:02:37.60#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.02:02:37.60#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.02:02:37.60#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.02:02:37.60#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.02:02:37.60$vck44/vblo=7,734.99 2006.173.02:02:37.60#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.02:02:37.60#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.02:02:37.60#ibcon#ireg 17 cls_cnt 0 2006.173.02:02:37.60#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.02:02:37.60#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.02:02:37.60#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.02:02:37.60#ibcon#enter wrdev, iclass 6, count 0 2006.173.02:02:37.60#ibcon#first serial, iclass 6, count 0 2006.173.02:02:37.60#ibcon#enter sib2, iclass 6, count 0 2006.173.02:02:37.60#ibcon#flushed, iclass 6, count 0 2006.173.02:02:37.60#ibcon#about to write, iclass 6, count 0 2006.173.02:02:37.60#ibcon#wrote, iclass 6, count 0 2006.173.02:02:37.60#ibcon#about to read 3, iclass 6, count 0 2006.173.02:02:37.62#ibcon#read 3, iclass 6, count 0 2006.173.02:02:37.62#ibcon#about to read 4, iclass 6, count 0 2006.173.02:02:37.62#ibcon#read 4, iclass 6, count 0 2006.173.02:02:37.62#ibcon#about to read 5, iclass 6, count 0 2006.173.02:02:37.62#ibcon#read 5, iclass 6, count 0 2006.173.02:02:37.62#ibcon#about to read 6, iclass 6, count 0 2006.173.02:02:37.62#ibcon#read 6, iclass 6, count 0 2006.173.02:02:37.62#ibcon#end of sib2, iclass 6, count 0 2006.173.02:02:37.62#ibcon#*mode == 0, iclass 6, count 0 2006.173.02:02:37.62#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.02:02:37.62#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.02:02:37.62#ibcon#*before write, iclass 6, count 0 2006.173.02:02:37.62#ibcon#enter sib2, iclass 6, count 0 2006.173.02:02:37.62#ibcon#flushed, iclass 6, count 0 2006.173.02:02:37.62#ibcon#about to write, iclass 6, count 0 2006.173.02:02:37.62#ibcon#wrote, iclass 6, count 0 2006.173.02:02:37.62#ibcon#about to read 3, iclass 6, count 0 2006.173.02:02:37.66#ibcon#read 3, iclass 6, count 0 2006.173.02:02:37.66#ibcon#about to read 4, iclass 6, count 0 2006.173.02:02:37.66#ibcon#read 4, iclass 6, count 0 2006.173.02:02:37.66#ibcon#about to read 5, iclass 6, count 0 2006.173.02:02:37.66#ibcon#read 5, iclass 6, count 0 2006.173.02:02:37.66#ibcon#about to read 6, iclass 6, count 0 2006.173.02:02:37.66#ibcon#read 6, iclass 6, count 0 2006.173.02:02:37.66#ibcon#end of sib2, iclass 6, count 0 2006.173.02:02:37.66#ibcon#*after write, iclass 6, count 0 2006.173.02:02:37.66#ibcon#*before return 0, iclass 6, count 0 2006.173.02:02:37.66#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.02:02:37.66#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.02:02:37.66#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.02:02:37.66#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.02:02:37.66$vck44/vb=7,4 2006.173.02:02:37.66#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.02:02:37.66#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.02:02:37.66#ibcon#ireg 11 cls_cnt 2 2006.173.02:02:37.66#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.02:02:37.72#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.02:02:37.72#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.02:02:37.72#ibcon#enter wrdev, iclass 10, count 2 2006.173.02:02:37.72#ibcon#first serial, iclass 10, count 2 2006.173.02:02:37.72#ibcon#enter sib2, iclass 10, count 2 2006.173.02:02:37.72#ibcon#flushed, iclass 10, count 2 2006.173.02:02:37.72#ibcon#about to write, iclass 10, count 2 2006.173.02:02:37.72#ibcon#wrote, iclass 10, count 2 2006.173.02:02:37.72#ibcon#about to read 3, iclass 10, count 2 2006.173.02:02:37.74#ibcon#read 3, iclass 10, count 2 2006.173.02:02:37.74#ibcon#about to read 4, iclass 10, count 2 2006.173.02:02:37.74#ibcon#read 4, iclass 10, count 2 2006.173.02:02:37.74#ibcon#about to read 5, iclass 10, count 2 2006.173.02:02:37.74#ibcon#read 5, iclass 10, count 2 2006.173.02:02:37.74#ibcon#about to read 6, iclass 10, count 2 2006.173.02:02:37.74#ibcon#read 6, iclass 10, count 2 2006.173.02:02:37.74#ibcon#end of sib2, iclass 10, count 2 2006.173.02:02:37.74#ibcon#*mode == 0, iclass 10, count 2 2006.173.02:02:37.74#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.02:02:37.74#ibcon#[27=AT07-04\r\n] 2006.173.02:02:37.74#ibcon#*before write, iclass 10, count 2 2006.173.02:02:37.74#ibcon#enter sib2, iclass 10, count 2 2006.173.02:02:37.74#ibcon#flushed, iclass 10, count 2 2006.173.02:02:37.74#ibcon#about to write, iclass 10, count 2 2006.173.02:02:37.74#ibcon#wrote, iclass 10, count 2 2006.173.02:02:37.74#ibcon#about to read 3, iclass 10, count 2 2006.173.02:02:37.77#ibcon#read 3, iclass 10, count 2 2006.173.02:02:37.77#ibcon#about to read 4, iclass 10, count 2 2006.173.02:02:37.77#ibcon#read 4, iclass 10, count 2 2006.173.02:02:37.77#ibcon#about to read 5, iclass 10, count 2 2006.173.02:02:37.77#ibcon#read 5, iclass 10, count 2 2006.173.02:02:37.77#ibcon#about to read 6, iclass 10, count 2 2006.173.02:02:37.77#ibcon#read 6, iclass 10, count 2 2006.173.02:02:37.77#ibcon#end of sib2, iclass 10, count 2 2006.173.02:02:37.77#ibcon#*after write, iclass 10, count 2 2006.173.02:02:37.77#ibcon#*before return 0, iclass 10, count 2 2006.173.02:02:37.77#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.02:02:37.77#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.02:02:37.77#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.02:02:37.77#ibcon#ireg 7 cls_cnt 0 2006.173.02:02:37.77#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.02:02:37.89#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.02:02:37.89#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.02:02:37.89#ibcon#enter wrdev, iclass 10, count 0 2006.173.02:02:37.89#ibcon#first serial, iclass 10, count 0 2006.173.02:02:37.89#ibcon#enter sib2, iclass 10, count 0 2006.173.02:02:37.89#ibcon#flushed, iclass 10, count 0 2006.173.02:02:37.89#ibcon#about to write, iclass 10, count 0 2006.173.02:02:37.89#ibcon#wrote, iclass 10, count 0 2006.173.02:02:37.89#ibcon#about to read 3, iclass 10, count 0 2006.173.02:02:37.91#ibcon#read 3, iclass 10, count 0 2006.173.02:02:37.91#ibcon#about to read 4, iclass 10, count 0 2006.173.02:02:37.91#ibcon#read 4, iclass 10, count 0 2006.173.02:02:37.91#ibcon#about to read 5, iclass 10, count 0 2006.173.02:02:37.91#ibcon#read 5, iclass 10, count 0 2006.173.02:02:37.91#ibcon#about to read 6, iclass 10, count 0 2006.173.02:02:37.91#ibcon#read 6, iclass 10, count 0 2006.173.02:02:37.91#ibcon#end of sib2, iclass 10, count 0 2006.173.02:02:37.91#ibcon#*mode == 0, iclass 10, count 0 2006.173.02:02:37.91#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.02:02:37.91#ibcon#[27=USB\r\n] 2006.173.02:02:37.91#ibcon#*before write, iclass 10, count 0 2006.173.02:02:37.91#ibcon#enter sib2, iclass 10, count 0 2006.173.02:02:37.91#ibcon#flushed, iclass 10, count 0 2006.173.02:02:37.91#ibcon#about to write, iclass 10, count 0 2006.173.02:02:37.91#ibcon#wrote, iclass 10, count 0 2006.173.02:02:37.91#ibcon#about to read 3, iclass 10, count 0 2006.173.02:02:37.94#ibcon#read 3, iclass 10, count 0 2006.173.02:02:37.94#ibcon#about to read 4, iclass 10, count 0 2006.173.02:02:37.94#ibcon#read 4, iclass 10, count 0 2006.173.02:02:37.94#ibcon#about to read 5, iclass 10, count 0 2006.173.02:02:37.94#ibcon#read 5, iclass 10, count 0 2006.173.02:02:37.94#ibcon#about to read 6, iclass 10, count 0 2006.173.02:02:37.94#ibcon#read 6, iclass 10, count 0 2006.173.02:02:37.94#ibcon#end of sib2, iclass 10, count 0 2006.173.02:02:37.94#ibcon#*after write, iclass 10, count 0 2006.173.02:02:37.94#ibcon#*before return 0, iclass 10, count 0 2006.173.02:02:37.94#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.02:02:37.94#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.02:02:37.94#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.02:02:37.94#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.02:02:37.94$vck44/vblo=8,744.99 2006.173.02:02:37.94#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.02:02:37.94#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.02:02:37.94#ibcon#ireg 17 cls_cnt 0 2006.173.02:02:37.94#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.02:02:37.94#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.02:02:37.94#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.02:02:37.94#ibcon#enter wrdev, iclass 12, count 0 2006.173.02:02:37.94#ibcon#first serial, iclass 12, count 0 2006.173.02:02:37.94#ibcon#enter sib2, iclass 12, count 0 2006.173.02:02:37.94#ibcon#flushed, iclass 12, count 0 2006.173.02:02:37.94#ibcon#about to write, iclass 12, count 0 2006.173.02:02:37.94#ibcon#wrote, iclass 12, count 0 2006.173.02:02:37.94#ibcon#about to read 3, iclass 12, count 0 2006.173.02:02:37.96#ibcon#read 3, iclass 12, count 0 2006.173.02:02:37.96#ibcon#about to read 4, iclass 12, count 0 2006.173.02:02:37.96#ibcon#read 4, iclass 12, count 0 2006.173.02:02:37.96#ibcon#about to read 5, iclass 12, count 0 2006.173.02:02:37.96#ibcon#read 5, iclass 12, count 0 2006.173.02:02:37.96#ibcon#about to read 6, iclass 12, count 0 2006.173.02:02:37.96#ibcon#read 6, iclass 12, count 0 2006.173.02:02:37.96#ibcon#end of sib2, iclass 12, count 0 2006.173.02:02:37.96#ibcon#*mode == 0, iclass 12, count 0 2006.173.02:02:37.96#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.02:02:37.96#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.02:02:37.96#ibcon#*before write, iclass 12, count 0 2006.173.02:02:37.96#ibcon#enter sib2, iclass 12, count 0 2006.173.02:02:37.96#ibcon#flushed, iclass 12, count 0 2006.173.02:02:37.96#ibcon#about to write, iclass 12, count 0 2006.173.02:02:37.96#ibcon#wrote, iclass 12, count 0 2006.173.02:02:37.96#ibcon#about to read 3, iclass 12, count 0 2006.173.02:02:38.00#ibcon#read 3, iclass 12, count 0 2006.173.02:02:38.00#ibcon#about to read 4, iclass 12, count 0 2006.173.02:02:38.00#ibcon#read 4, iclass 12, count 0 2006.173.02:02:38.00#ibcon#about to read 5, iclass 12, count 0 2006.173.02:02:38.00#ibcon#read 5, iclass 12, count 0 2006.173.02:02:38.00#ibcon#about to read 6, iclass 12, count 0 2006.173.02:02:38.00#ibcon#read 6, iclass 12, count 0 2006.173.02:02:38.00#ibcon#end of sib2, iclass 12, count 0 2006.173.02:02:38.00#ibcon#*after write, iclass 12, count 0 2006.173.02:02:38.00#ibcon#*before return 0, iclass 12, count 0 2006.173.02:02:38.00#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.02:02:38.00#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.02:02:38.00#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.02:02:38.00#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.02:02:38.00$vck44/vb=8,4 2006.173.02:02:38.00#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.02:02:38.00#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.02:02:38.00#ibcon#ireg 11 cls_cnt 2 2006.173.02:02:38.00#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.02:02:38.06#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.02:02:38.06#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.02:02:38.06#ibcon#enter wrdev, iclass 14, count 2 2006.173.02:02:38.06#ibcon#first serial, iclass 14, count 2 2006.173.02:02:38.06#ibcon#enter sib2, iclass 14, count 2 2006.173.02:02:38.06#ibcon#flushed, iclass 14, count 2 2006.173.02:02:38.06#ibcon#about to write, iclass 14, count 2 2006.173.02:02:38.06#ibcon#wrote, iclass 14, count 2 2006.173.02:02:38.06#ibcon#about to read 3, iclass 14, count 2 2006.173.02:02:38.08#ibcon#read 3, iclass 14, count 2 2006.173.02:02:38.08#ibcon#about to read 4, iclass 14, count 2 2006.173.02:02:38.08#ibcon#read 4, iclass 14, count 2 2006.173.02:02:38.08#ibcon#about to read 5, iclass 14, count 2 2006.173.02:02:38.08#ibcon#read 5, iclass 14, count 2 2006.173.02:02:38.08#ibcon#about to read 6, iclass 14, count 2 2006.173.02:02:38.08#ibcon#read 6, iclass 14, count 2 2006.173.02:02:38.08#ibcon#end of sib2, iclass 14, count 2 2006.173.02:02:38.08#ibcon#*mode == 0, iclass 14, count 2 2006.173.02:02:38.08#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.02:02:38.08#ibcon#[27=AT08-04\r\n] 2006.173.02:02:38.08#ibcon#*before write, iclass 14, count 2 2006.173.02:02:38.08#ibcon#enter sib2, iclass 14, count 2 2006.173.02:02:38.08#ibcon#flushed, iclass 14, count 2 2006.173.02:02:38.08#ibcon#about to write, iclass 14, count 2 2006.173.02:02:38.08#ibcon#wrote, iclass 14, count 2 2006.173.02:02:38.08#ibcon#about to read 3, iclass 14, count 2 2006.173.02:02:38.11#ibcon#read 3, iclass 14, count 2 2006.173.02:02:38.11#ibcon#about to read 4, iclass 14, count 2 2006.173.02:02:38.11#ibcon#read 4, iclass 14, count 2 2006.173.02:02:38.11#ibcon#about to read 5, iclass 14, count 2 2006.173.02:02:38.11#ibcon#read 5, iclass 14, count 2 2006.173.02:02:38.11#ibcon#about to read 6, iclass 14, count 2 2006.173.02:02:38.11#ibcon#read 6, iclass 14, count 2 2006.173.02:02:38.11#ibcon#end of sib2, iclass 14, count 2 2006.173.02:02:38.11#ibcon#*after write, iclass 14, count 2 2006.173.02:02:38.11#ibcon#*before return 0, iclass 14, count 2 2006.173.02:02:38.11#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.02:02:38.11#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.02:02:38.11#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.02:02:38.11#ibcon#ireg 7 cls_cnt 0 2006.173.02:02:38.11#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.02:02:38.23#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.02:02:38.23#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.02:02:38.23#ibcon#enter wrdev, iclass 14, count 0 2006.173.02:02:38.23#ibcon#first serial, iclass 14, count 0 2006.173.02:02:38.23#ibcon#enter sib2, iclass 14, count 0 2006.173.02:02:38.23#ibcon#flushed, iclass 14, count 0 2006.173.02:02:38.23#ibcon#about to write, iclass 14, count 0 2006.173.02:02:38.23#ibcon#wrote, iclass 14, count 0 2006.173.02:02:38.23#ibcon#about to read 3, iclass 14, count 0 2006.173.02:02:38.25#ibcon#read 3, iclass 14, count 0 2006.173.02:02:38.25#ibcon#about to read 4, iclass 14, count 0 2006.173.02:02:38.25#ibcon#read 4, iclass 14, count 0 2006.173.02:02:38.25#ibcon#about to read 5, iclass 14, count 0 2006.173.02:02:38.25#ibcon#read 5, iclass 14, count 0 2006.173.02:02:38.25#ibcon#about to read 6, iclass 14, count 0 2006.173.02:02:38.25#ibcon#read 6, iclass 14, count 0 2006.173.02:02:38.25#ibcon#end of sib2, iclass 14, count 0 2006.173.02:02:38.25#ibcon#*mode == 0, iclass 14, count 0 2006.173.02:02:38.25#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.02:02:38.25#ibcon#[27=USB\r\n] 2006.173.02:02:38.25#ibcon#*before write, iclass 14, count 0 2006.173.02:02:38.25#ibcon#enter sib2, iclass 14, count 0 2006.173.02:02:38.25#ibcon#flushed, iclass 14, count 0 2006.173.02:02:38.25#ibcon#about to write, iclass 14, count 0 2006.173.02:02:38.25#ibcon#wrote, iclass 14, count 0 2006.173.02:02:38.25#ibcon#about to read 3, iclass 14, count 0 2006.173.02:02:38.28#ibcon#read 3, iclass 14, count 0 2006.173.02:02:38.28#ibcon#about to read 4, iclass 14, count 0 2006.173.02:02:38.28#ibcon#read 4, iclass 14, count 0 2006.173.02:02:38.28#ibcon#about to read 5, iclass 14, count 0 2006.173.02:02:38.28#ibcon#read 5, iclass 14, count 0 2006.173.02:02:38.28#ibcon#about to read 6, iclass 14, count 0 2006.173.02:02:38.28#ibcon#read 6, iclass 14, count 0 2006.173.02:02:38.28#ibcon#end of sib2, iclass 14, count 0 2006.173.02:02:38.28#ibcon#*after write, iclass 14, count 0 2006.173.02:02:38.28#ibcon#*before return 0, iclass 14, count 0 2006.173.02:02:38.28#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.02:02:38.28#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.02:02:38.28#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.02:02:38.28#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.02:02:38.28$vck44/vabw=wide 2006.173.02:02:38.28#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.02:02:38.28#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.02:02:38.28#ibcon#ireg 8 cls_cnt 0 2006.173.02:02:38.28#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.02:02:38.28#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.02:02:38.28#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.02:02:38.28#ibcon#enter wrdev, iclass 16, count 0 2006.173.02:02:38.28#ibcon#first serial, iclass 16, count 0 2006.173.02:02:38.28#ibcon#enter sib2, iclass 16, count 0 2006.173.02:02:38.28#ibcon#flushed, iclass 16, count 0 2006.173.02:02:38.28#ibcon#about to write, iclass 16, count 0 2006.173.02:02:38.28#ibcon#wrote, iclass 16, count 0 2006.173.02:02:38.28#ibcon#about to read 3, iclass 16, count 0 2006.173.02:02:38.30#ibcon#read 3, iclass 16, count 0 2006.173.02:02:38.30#ibcon#about to read 4, iclass 16, count 0 2006.173.02:02:38.30#ibcon#read 4, iclass 16, count 0 2006.173.02:02:38.30#ibcon#about to read 5, iclass 16, count 0 2006.173.02:02:38.30#ibcon#read 5, iclass 16, count 0 2006.173.02:02:38.30#ibcon#about to read 6, iclass 16, count 0 2006.173.02:02:38.30#ibcon#read 6, iclass 16, count 0 2006.173.02:02:38.30#ibcon#end of sib2, iclass 16, count 0 2006.173.02:02:38.30#ibcon#*mode == 0, iclass 16, count 0 2006.173.02:02:38.30#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.02:02:38.30#ibcon#[25=BW32\r\n] 2006.173.02:02:38.30#ibcon#*before write, iclass 16, count 0 2006.173.02:02:38.30#ibcon#enter sib2, iclass 16, count 0 2006.173.02:02:38.30#ibcon#flushed, iclass 16, count 0 2006.173.02:02:38.30#ibcon#about to write, iclass 16, count 0 2006.173.02:02:38.30#ibcon#wrote, iclass 16, count 0 2006.173.02:02:38.30#ibcon#about to read 3, iclass 16, count 0 2006.173.02:02:38.33#ibcon#read 3, iclass 16, count 0 2006.173.02:02:38.33#ibcon#about to read 4, iclass 16, count 0 2006.173.02:02:38.33#ibcon#read 4, iclass 16, count 0 2006.173.02:02:38.33#ibcon#about to read 5, iclass 16, count 0 2006.173.02:02:38.33#ibcon#read 5, iclass 16, count 0 2006.173.02:02:38.33#ibcon#about to read 6, iclass 16, count 0 2006.173.02:02:38.33#ibcon#read 6, iclass 16, count 0 2006.173.02:02:38.33#ibcon#end of sib2, iclass 16, count 0 2006.173.02:02:38.33#ibcon#*after write, iclass 16, count 0 2006.173.02:02:38.33#ibcon#*before return 0, iclass 16, count 0 2006.173.02:02:38.33#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.02:02:38.33#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.02:02:38.33#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.02:02:38.33#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.02:02:38.33$vck44/vbbw=wide 2006.173.02:02:38.33#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.02:02:38.33#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.02:02:38.33#ibcon#ireg 8 cls_cnt 0 2006.173.02:02:38.33#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.02:02:38.40#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.02:02:38.40#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.02:02:38.40#ibcon#enter wrdev, iclass 18, count 0 2006.173.02:02:38.40#ibcon#first serial, iclass 18, count 0 2006.173.02:02:38.40#ibcon#enter sib2, iclass 18, count 0 2006.173.02:02:38.40#ibcon#flushed, iclass 18, count 0 2006.173.02:02:38.40#ibcon#about to write, iclass 18, count 0 2006.173.02:02:38.40#ibcon#wrote, iclass 18, count 0 2006.173.02:02:38.40#ibcon#about to read 3, iclass 18, count 0 2006.173.02:02:38.42#ibcon#read 3, iclass 18, count 0 2006.173.02:02:38.42#ibcon#about to read 4, iclass 18, count 0 2006.173.02:02:38.42#ibcon#read 4, iclass 18, count 0 2006.173.02:02:38.42#ibcon#about to read 5, iclass 18, count 0 2006.173.02:02:38.42#ibcon#read 5, iclass 18, count 0 2006.173.02:02:38.42#ibcon#about to read 6, iclass 18, count 0 2006.173.02:02:38.42#ibcon#read 6, iclass 18, count 0 2006.173.02:02:38.42#ibcon#end of sib2, iclass 18, count 0 2006.173.02:02:38.42#ibcon#*mode == 0, iclass 18, count 0 2006.173.02:02:38.42#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.02:02:38.42#ibcon#[27=BW32\r\n] 2006.173.02:02:38.42#ibcon#*before write, iclass 18, count 0 2006.173.02:02:38.42#ibcon#enter sib2, iclass 18, count 0 2006.173.02:02:38.42#ibcon#flushed, iclass 18, count 0 2006.173.02:02:38.42#ibcon#about to write, iclass 18, count 0 2006.173.02:02:38.42#ibcon#wrote, iclass 18, count 0 2006.173.02:02:38.42#ibcon#about to read 3, iclass 18, count 0 2006.173.02:02:38.45#ibcon#read 3, iclass 18, count 0 2006.173.02:02:38.45#ibcon#about to read 4, iclass 18, count 0 2006.173.02:02:38.45#ibcon#read 4, iclass 18, count 0 2006.173.02:02:38.45#ibcon#about to read 5, iclass 18, count 0 2006.173.02:02:38.45#ibcon#read 5, iclass 18, count 0 2006.173.02:02:38.45#ibcon#about to read 6, iclass 18, count 0 2006.173.02:02:38.45#ibcon#read 6, iclass 18, count 0 2006.173.02:02:38.45#ibcon#end of sib2, iclass 18, count 0 2006.173.02:02:38.45#ibcon#*after write, iclass 18, count 0 2006.173.02:02:38.45#ibcon#*before return 0, iclass 18, count 0 2006.173.02:02:38.45#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.02:02:38.45#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.02:02:38.45#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.02:02:38.45#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.02:02:38.45$setupk4/ifdk4 2006.173.02:02:38.45$ifdk4/lo= 2006.173.02:02:38.45$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.02:02:38.45$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.02:02:38.45$ifdk4/patch= 2006.173.02:02:38.45$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.02:02:38.45$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.02:02:38.45$setupk4/!*+20s 2006.173.02:02:41.25#abcon#<5=/13 0.9 2.7 22.66 821006.6\r\n> 2006.173.02:02:41.27#abcon#{5=INTERFACE CLEAR} 2006.173.02:02:41.33#abcon#[5=S1D000X0/0*\r\n] 2006.173.02:02:47.14#trakl#Source acquired 2006.173.02:02:48.14#flagr#flagr/antenna,acquired 2006.173.02:02:51.42#abcon#<5=/13 1.0 2.7 22.66 821006.6\r\n> 2006.173.02:02:51.44#abcon#{5=INTERFACE CLEAR} 2006.173.02:02:51.50#abcon#[5=S1D000X0/0*\r\n] 2006.173.02:02:52.92$setupk4/"tpicd 2006.173.02:02:52.92$setupk4/echo=off 2006.173.02:02:52.92$setupk4/xlog=off 2006.173.02:02:52.92:!2006.173.02:05:27 2006.173.02:05:27.02:preob 2006.173.02:05:28.15/onsource/TRACKING 2006.173.02:05:28.15:!2006.173.02:05:37 2006.173.02:05:37.02:"tape 2006.173.02:05:37.02:"st=record 2006.173.02:05:37.02:data_valid=on 2006.173.02:05:37.02:midob 2006.173.02:05:38.15/onsource/TRACKING 2006.173.02:05:38.15/wx/22.70,1006.6,82 2006.173.02:05:38.24/cable/+6.5116E-03 2006.173.02:05:39.33/va/01,07,usb,yes,36,39 2006.173.02:05:39.33/va/02,06,usb,yes,36,37 2006.173.02:05:39.33/va/03,05,usb,yes,46,48 2006.173.02:05:39.33/va/04,06,usb,yes,37,39 2006.173.02:05:39.34/va/05,04,usb,yes,29,30 2006.173.02:05:39.34/va/06,03,usb,yes,41,41 2006.173.02:05:39.34/va/07,04,usb,yes,33,34 2006.173.02:05:39.34/va/08,04,usb,yes,28,34 2006.173.02:05:39.56/valo/01,524.99,yes,locked 2006.173.02:05:39.57/valo/02,534.99,yes,locked 2006.173.02:05:39.57/valo/03,564.99,yes,locked 2006.173.02:05:39.57/valo/04,624.99,yes,locked 2006.173.02:05:39.57/valo/05,734.99,yes,locked 2006.173.02:05:39.57/valo/06,814.99,yes,locked 2006.173.02:05:39.57/valo/07,864.99,yes,locked 2006.173.02:05:39.57/valo/08,884.99,yes,locked 2006.173.02:05:40.65/vb/01,04,usb,yes,29,27 2006.173.02:05:40.65/vb/02,04,usb,yes,31,31 2006.173.02:05:40.65/vb/03,04,usb,yes,28,31 2006.173.02:05:40.65/vb/04,04,usb,yes,33,32 2006.173.02:05:40.65/vb/05,04,usb,yes,25,28 2006.173.02:05:40.66/vb/06,04,usb,yes,30,26 2006.173.02:05:40.66/vb/07,04,usb,yes,29,29 2006.173.02:05:40.66/vb/08,04,usb,yes,27,30 2006.173.02:05:40.88/vblo/01,629.99,yes,locked 2006.173.02:05:40.89/vblo/02,634.99,yes,locked 2006.173.02:05:40.89/vblo/03,649.99,yes,locked 2006.173.02:05:40.89/vblo/04,679.99,yes,locked 2006.173.02:05:40.89/vblo/05,709.99,yes,locked 2006.173.02:05:40.89/vblo/06,719.99,yes,locked 2006.173.02:05:40.89/vblo/07,734.99,yes,locked 2006.173.02:05:40.89/vblo/08,744.99,yes,locked 2006.173.02:05:41.03/vabw/8 2006.173.02:05:41.18/vbbw/8 2006.173.02:05:41.27/xfe/off,on,14.7 2006.173.02:05:41.65/ifatt/23,28,28,28 2006.173.02:05:42.07/fmout-gps/S +3.94E-07 2006.173.02:05:42.16:!2006.173.02:06:37 2006.173.02:06:37.02:data_valid=off 2006.173.02:06:37.02:"et 2006.173.02:06:37.02:!+3s 2006.173.02:06:40.05:"tape 2006.173.02:06:40.09:postob 2006.173.02:06:40.15/cable/+6.5125E-03 2006.173.02:06:40.16/wx/22.69,1006.6,82 2006.173.02:06:40.21/fmout-gps/S +3.93E-07 2006.173.02:06:40.22:scan_name=173-0209,jd0606,220 2006.173.02:06:40.22:source=0059+581,010245.76,582411.1,2000.0,cw 2006.173.02:06:41.15#flagr#flagr/antenna,new-source 2006.173.02:06:41.15:checkk5 2006.173.02:06:41.57/chk_autoobs//k5ts1/ autoobs is running! 2006.173.02:06:42.02/chk_autoobs//k5ts2/ autoobs is running! 2006.173.02:06:42.76/chk_autoobs//k5ts3/ autoobs is running! 2006.173.02:06:43.40/chk_autoobs//k5ts4/ autoobs is running! 2006.173.02:06:43.79/chk_obsdata//k5ts1/T1730205??a.dat file size is correct (nominal:240MB, actual:236MB). 2006.173.02:06:44.23/chk_obsdata//k5ts2/T1730205??b.dat file size is correct (nominal:240MB, actual:236MB). 2006.173.02:06:44.63/chk_obsdata//k5ts3/T1730205??c.dat file size is correct (nominal:240MB, actual:236MB). 2006.173.02:06:45.00/chk_obsdata//k5ts4/T1730205??d.dat file size is correct (nominal:240MB, actual:236MB). 2006.173.02:06:45.98/k5log//k5ts1_log_newline 2006.173.02:06:46.82/k5log//k5ts2_log_newline 2006.173.02:06:47.66/k5log//k5ts3_log_newline 2006.173.02:06:48.64/k5log//k5ts4_log_newline 2006.173.02:06:48.67/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.02:06:48.67:setupk4=1 2006.173.02:06:48.67$setupk4/echo=on 2006.173.02:06:48.67$setupk4/pcalon 2006.173.02:06:48.67$pcalon/"no phase cal control is implemented here 2006.173.02:06:48.67$setupk4/"tpicd=stop 2006.173.02:06:48.67$setupk4/"rec=synch_on 2006.173.02:06:48.67$setupk4/"rec_mode=128 2006.173.02:06:48.67$setupk4/!* 2006.173.02:06:48.67$setupk4/recpk4 2006.173.02:06:48.67$recpk4/recpatch= 2006.173.02:06:48.67$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.02:06:48.67$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.02:06:48.67$setupk4/vck44 2006.173.02:06:48.67$vck44/valo=1,524.99 2006.173.02:06:48.67#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.02:06:48.67#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.02:06:48.67#ibcon#ireg 17 cls_cnt 0 2006.173.02:06:48.67#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.02:06:48.67#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.02:06:48.67#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.02:06:48.67#ibcon#enter wrdev, iclass 15, count 0 2006.173.02:06:48.67#ibcon#first serial, iclass 15, count 0 2006.173.02:06:48.67#ibcon#enter sib2, iclass 15, count 0 2006.173.02:06:48.67#ibcon#flushed, iclass 15, count 0 2006.173.02:06:48.67#ibcon#about to write, iclass 15, count 0 2006.173.02:06:48.67#ibcon#wrote, iclass 15, count 0 2006.173.02:06:48.67#ibcon#about to read 3, iclass 15, count 0 2006.173.02:06:48.72#ibcon#read 3, iclass 15, count 0 2006.173.02:06:48.72#ibcon#about to read 4, iclass 15, count 0 2006.173.02:06:48.72#ibcon#read 4, iclass 15, count 0 2006.173.02:06:48.72#ibcon#about to read 5, iclass 15, count 0 2006.173.02:06:48.72#ibcon#read 5, iclass 15, count 0 2006.173.02:06:48.72#ibcon#about to read 6, iclass 15, count 0 2006.173.02:06:48.72#ibcon#read 6, iclass 15, count 0 2006.173.02:06:48.72#ibcon#end of sib2, iclass 15, count 0 2006.173.02:06:48.72#ibcon#*mode == 0, iclass 15, count 0 2006.173.02:06:48.72#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.02:06:48.72#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.02:06:48.72#ibcon#*before write, iclass 15, count 0 2006.173.02:06:48.72#ibcon#enter sib2, iclass 15, count 0 2006.173.02:06:48.72#ibcon#flushed, iclass 15, count 0 2006.173.02:06:48.72#ibcon#about to write, iclass 15, count 0 2006.173.02:06:48.72#ibcon#wrote, iclass 15, count 0 2006.173.02:06:48.72#ibcon#about to read 3, iclass 15, count 0 2006.173.02:06:48.76#ibcon#read 3, iclass 15, count 0 2006.173.02:06:48.76#ibcon#about to read 4, iclass 15, count 0 2006.173.02:06:48.76#ibcon#read 4, iclass 15, count 0 2006.173.02:06:48.76#ibcon#about to read 5, iclass 15, count 0 2006.173.02:06:48.76#ibcon#read 5, iclass 15, count 0 2006.173.02:06:48.76#ibcon#about to read 6, iclass 15, count 0 2006.173.02:06:48.76#ibcon#read 6, iclass 15, count 0 2006.173.02:06:48.76#ibcon#end of sib2, iclass 15, count 0 2006.173.02:06:48.76#ibcon#*after write, iclass 15, count 0 2006.173.02:06:48.76#ibcon#*before return 0, iclass 15, count 0 2006.173.02:06:48.76#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.02:06:48.76#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.02:06:48.76#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.02:06:48.76#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.02:06:48.77$vck44/va=1,7 2006.173.02:06:48.77#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.02:06:48.77#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.02:06:48.77#ibcon#ireg 11 cls_cnt 2 2006.173.02:06:48.77#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.02:06:48.77#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.02:06:48.77#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.02:06:48.77#ibcon#enter wrdev, iclass 17, count 2 2006.173.02:06:48.77#ibcon#first serial, iclass 17, count 2 2006.173.02:06:48.77#ibcon#enter sib2, iclass 17, count 2 2006.173.02:06:48.77#ibcon#flushed, iclass 17, count 2 2006.173.02:06:48.77#ibcon#about to write, iclass 17, count 2 2006.173.02:06:48.77#ibcon#wrote, iclass 17, count 2 2006.173.02:06:48.77#ibcon#about to read 3, iclass 17, count 2 2006.173.02:06:48.78#ibcon#read 3, iclass 17, count 2 2006.173.02:06:48.78#ibcon#about to read 4, iclass 17, count 2 2006.173.02:06:48.78#ibcon#read 4, iclass 17, count 2 2006.173.02:06:48.78#ibcon#about to read 5, iclass 17, count 2 2006.173.02:06:48.78#ibcon#read 5, iclass 17, count 2 2006.173.02:06:48.78#ibcon#about to read 6, iclass 17, count 2 2006.173.02:06:48.78#ibcon#read 6, iclass 17, count 2 2006.173.02:06:48.78#ibcon#end of sib2, iclass 17, count 2 2006.173.02:06:48.78#ibcon#*mode == 0, iclass 17, count 2 2006.173.02:06:48.78#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.02:06:48.78#ibcon#[25=AT01-07\r\n] 2006.173.02:06:48.78#ibcon#*before write, iclass 17, count 2 2006.173.02:06:48.78#ibcon#enter sib2, iclass 17, count 2 2006.173.02:06:48.78#ibcon#flushed, iclass 17, count 2 2006.173.02:06:48.78#ibcon#about to write, iclass 17, count 2 2006.173.02:06:48.78#ibcon#wrote, iclass 17, count 2 2006.173.02:06:48.78#ibcon#about to read 3, iclass 17, count 2 2006.173.02:06:48.81#ibcon#read 3, iclass 17, count 2 2006.173.02:06:48.81#ibcon#about to read 4, iclass 17, count 2 2006.173.02:06:48.81#ibcon#read 4, iclass 17, count 2 2006.173.02:06:48.81#ibcon#about to read 5, iclass 17, count 2 2006.173.02:06:48.81#ibcon#read 5, iclass 17, count 2 2006.173.02:06:48.81#ibcon#about to read 6, iclass 17, count 2 2006.173.02:06:48.81#ibcon#read 6, iclass 17, count 2 2006.173.02:06:48.81#ibcon#end of sib2, iclass 17, count 2 2006.173.02:06:48.81#ibcon#*after write, iclass 17, count 2 2006.173.02:06:48.81#ibcon#*before return 0, iclass 17, count 2 2006.173.02:06:48.81#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.02:06:48.81#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.02:06:48.81#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.02:06:48.81#ibcon#ireg 7 cls_cnt 0 2006.173.02:06:48.81#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.02:06:48.93#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.02:06:48.93#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.02:06:48.93#ibcon#enter wrdev, iclass 17, count 0 2006.173.02:06:48.93#ibcon#first serial, iclass 17, count 0 2006.173.02:06:48.93#ibcon#enter sib2, iclass 17, count 0 2006.173.02:06:48.93#ibcon#flushed, iclass 17, count 0 2006.173.02:06:48.93#ibcon#about to write, iclass 17, count 0 2006.173.02:06:48.93#ibcon#wrote, iclass 17, count 0 2006.173.02:06:48.93#ibcon#about to read 3, iclass 17, count 0 2006.173.02:06:48.95#ibcon#read 3, iclass 17, count 0 2006.173.02:06:48.95#ibcon#about to read 4, iclass 17, count 0 2006.173.02:06:48.95#ibcon#read 4, iclass 17, count 0 2006.173.02:06:48.95#ibcon#about to read 5, iclass 17, count 0 2006.173.02:06:48.95#ibcon#read 5, iclass 17, count 0 2006.173.02:06:48.95#ibcon#about to read 6, iclass 17, count 0 2006.173.02:06:48.95#ibcon#read 6, iclass 17, count 0 2006.173.02:06:48.95#ibcon#end of sib2, iclass 17, count 0 2006.173.02:06:48.95#ibcon#*mode == 0, iclass 17, count 0 2006.173.02:06:48.95#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.02:06:48.95#ibcon#[25=USB\r\n] 2006.173.02:06:48.95#ibcon#*before write, iclass 17, count 0 2006.173.02:06:48.95#ibcon#enter sib2, iclass 17, count 0 2006.173.02:06:48.95#ibcon#flushed, iclass 17, count 0 2006.173.02:06:48.95#ibcon#about to write, iclass 17, count 0 2006.173.02:06:48.95#ibcon#wrote, iclass 17, count 0 2006.173.02:06:48.95#ibcon#about to read 3, iclass 17, count 0 2006.173.02:06:48.98#ibcon#read 3, iclass 17, count 0 2006.173.02:06:48.98#ibcon#about to read 4, iclass 17, count 0 2006.173.02:06:48.98#ibcon#read 4, iclass 17, count 0 2006.173.02:06:48.98#ibcon#about to read 5, iclass 17, count 0 2006.173.02:06:48.98#ibcon#read 5, iclass 17, count 0 2006.173.02:06:48.98#ibcon#about to read 6, iclass 17, count 0 2006.173.02:06:48.98#ibcon#read 6, iclass 17, count 0 2006.173.02:06:48.98#ibcon#end of sib2, iclass 17, count 0 2006.173.02:06:48.98#ibcon#*after write, iclass 17, count 0 2006.173.02:06:48.98#ibcon#*before return 0, iclass 17, count 0 2006.173.02:06:48.98#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.02:06:48.98#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.02:06:48.98#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.02:06:48.98#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.02:06:48.99$vck44/valo=2,534.99 2006.173.02:06:48.99#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.02:06:48.99#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.02:06:48.99#ibcon#ireg 17 cls_cnt 0 2006.173.02:06:48.99#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.02:06:48.99#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.02:06:48.99#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.02:06:48.99#ibcon#enter wrdev, iclass 19, count 0 2006.173.02:06:48.99#ibcon#first serial, iclass 19, count 0 2006.173.02:06:48.99#ibcon#enter sib2, iclass 19, count 0 2006.173.02:06:48.99#ibcon#flushed, iclass 19, count 0 2006.173.02:06:48.99#ibcon#about to write, iclass 19, count 0 2006.173.02:06:48.99#ibcon#wrote, iclass 19, count 0 2006.173.02:06:48.99#ibcon#about to read 3, iclass 19, count 0 2006.173.02:06:49.00#ibcon#read 3, iclass 19, count 0 2006.173.02:06:49.00#ibcon#about to read 4, iclass 19, count 0 2006.173.02:06:49.00#ibcon#read 4, iclass 19, count 0 2006.173.02:06:49.00#ibcon#about to read 5, iclass 19, count 0 2006.173.02:06:49.00#ibcon#read 5, iclass 19, count 0 2006.173.02:06:49.00#ibcon#about to read 6, iclass 19, count 0 2006.173.02:06:49.00#ibcon#read 6, iclass 19, count 0 2006.173.02:06:49.00#ibcon#end of sib2, iclass 19, count 0 2006.173.02:06:49.00#ibcon#*mode == 0, iclass 19, count 0 2006.173.02:06:49.00#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.02:06:49.00#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.02:06:49.00#ibcon#*before write, iclass 19, count 0 2006.173.02:06:49.00#ibcon#enter sib2, iclass 19, count 0 2006.173.02:06:49.00#ibcon#flushed, iclass 19, count 0 2006.173.02:06:49.00#ibcon#about to write, iclass 19, count 0 2006.173.02:06:49.00#ibcon#wrote, iclass 19, count 0 2006.173.02:06:49.00#ibcon#about to read 3, iclass 19, count 0 2006.173.02:06:49.05#ibcon#read 3, iclass 19, count 0 2006.173.02:06:49.05#ibcon#about to read 4, iclass 19, count 0 2006.173.02:06:49.05#ibcon#read 4, iclass 19, count 0 2006.173.02:06:49.05#ibcon#about to read 5, iclass 19, count 0 2006.173.02:06:49.05#ibcon#read 5, iclass 19, count 0 2006.173.02:06:49.05#ibcon#about to read 6, iclass 19, count 0 2006.173.02:06:49.05#ibcon#read 6, iclass 19, count 0 2006.173.02:06:49.05#ibcon#end of sib2, iclass 19, count 0 2006.173.02:06:49.05#ibcon#*after write, iclass 19, count 0 2006.173.02:06:49.05#ibcon#*before return 0, iclass 19, count 0 2006.173.02:06:49.05#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.02:06:49.05#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.02:06:49.05#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.02:06:49.05#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.02:06:49.05$vck44/va=2,6 2006.173.02:06:49.05#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.02:06:49.05#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.02:06:49.05#ibcon#ireg 11 cls_cnt 2 2006.173.02:06:49.05#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.02:06:49.09#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.02:06:49.09#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.02:06:49.09#ibcon#enter wrdev, iclass 21, count 2 2006.173.02:06:49.09#ibcon#first serial, iclass 21, count 2 2006.173.02:06:49.09#ibcon#enter sib2, iclass 21, count 2 2006.173.02:06:49.09#ibcon#flushed, iclass 21, count 2 2006.173.02:06:49.09#ibcon#about to write, iclass 21, count 2 2006.173.02:06:49.09#ibcon#wrote, iclass 21, count 2 2006.173.02:06:49.09#ibcon#about to read 3, iclass 21, count 2 2006.173.02:06:49.11#ibcon#read 3, iclass 21, count 2 2006.173.02:06:49.11#ibcon#about to read 4, iclass 21, count 2 2006.173.02:06:49.11#ibcon#read 4, iclass 21, count 2 2006.173.02:06:49.11#ibcon#about to read 5, iclass 21, count 2 2006.173.02:06:49.11#ibcon#read 5, iclass 21, count 2 2006.173.02:06:49.11#ibcon#about to read 6, iclass 21, count 2 2006.173.02:06:49.11#ibcon#read 6, iclass 21, count 2 2006.173.02:06:49.11#ibcon#end of sib2, iclass 21, count 2 2006.173.02:06:49.11#ibcon#*mode == 0, iclass 21, count 2 2006.173.02:06:49.11#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.02:06:49.11#ibcon#[25=AT02-06\r\n] 2006.173.02:06:49.11#ibcon#*before write, iclass 21, count 2 2006.173.02:06:49.11#ibcon#enter sib2, iclass 21, count 2 2006.173.02:06:49.11#ibcon#flushed, iclass 21, count 2 2006.173.02:06:49.11#ibcon#about to write, iclass 21, count 2 2006.173.02:06:49.11#ibcon#wrote, iclass 21, count 2 2006.173.02:06:49.11#ibcon#about to read 3, iclass 21, count 2 2006.173.02:06:49.15#ibcon#read 3, iclass 21, count 2 2006.173.02:06:49.15#ibcon#about to read 4, iclass 21, count 2 2006.173.02:06:49.15#ibcon#read 4, iclass 21, count 2 2006.173.02:06:49.15#ibcon#about to read 5, iclass 21, count 2 2006.173.02:06:49.15#ibcon#read 5, iclass 21, count 2 2006.173.02:06:49.15#ibcon#about to read 6, iclass 21, count 2 2006.173.02:06:49.15#ibcon#read 6, iclass 21, count 2 2006.173.02:06:49.15#ibcon#end of sib2, iclass 21, count 2 2006.173.02:06:49.15#ibcon#*after write, iclass 21, count 2 2006.173.02:06:49.15#ibcon#*before return 0, iclass 21, count 2 2006.173.02:06:49.15#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.02:06:49.15#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.02:06:49.15#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.02:06:49.15#ibcon#ireg 7 cls_cnt 0 2006.173.02:06:49.15#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.02:06:49.26#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.02:06:49.26#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.02:06:49.26#ibcon#enter wrdev, iclass 21, count 0 2006.173.02:06:49.26#ibcon#first serial, iclass 21, count 0 2006.173.02:06:49.26#ibcon#enter sib2, iclass 21, count 0 2006.173.02:06:49.26#ibcon#flushed, iclass 21, count 0 2006.173.02:06:49.26#ibcon#about to write, iclass 21, count 0 2006.173.02:06:49.26#ibcon#wrote, iclass 21, count 0 2006.173.02:06:49.26#ibcon#about to read 3, iclass 21, count 0 2006.173.02:06:49.28#ibcon#read 3, iclass 21, count 0 2006.173.02:06:49.28#ibcon#about to read 4, iclass 21, count 0 2006.173.02:06:49.28#ibcon#read 4, iclass 21, count 0 2006.173.02:06:49.28#ibcon#about to read 5, iclass 21, count 0 2006.173.02:06:49.28#ibcon#read 5, iclass 21, count 0 2006.173.02:06:49.28#ibcon#about to read 6, iclass 21, count 0 2006.173.02:06:49.28#ibcon#read 6, iclass 21, count 0 2006.173.02:06:49.28#ibcon#end of sib2, iclass 21, count 0 2006.173.02:06:49.28#ibcon#*mode == 0, iclass 21, count 0 2006.173.02:06:49.28#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.02:06:49.28#ibcon#[25=USB\r\n] 2006.173.02:06:49.28#ibcon#*before write, iclass 21, count 0 2006.173.02:06:49.28#ibcon#enter sib2, iclass 21, count 0 2006.173.02:06:49.28#ibcon#flushed, iclass 21, count 0 2006.173.02:06:49.28#ibcon#about to write, iclass 21, count 0 2006.173.02:06:49.28#ibcon#wrote, iclass 21, count 0 2006.173.02:06:49.28#ibcon#about to read 3, iclass 21, count 0 2006.173.02:06:49.31#ibcon#read 3, iclass 21, count 0 2006.173.02:06:49.31#ibcon#about to read 4, iclass 21, count 0 2006.173.02:06:49.31#ibcon#read 4, iclass 21, count 0 2006.173.02:06:49.31#ibcon#about to read 5, iclass 21, count 0 2006.173.02:06:49.31#ibcon#read 5, iclass 21, count 0 2006.173.02:06:49.31#ibcon#about to read 6, iclass 21, count 0 2006.173.02:06:49.31#ibcon#read 6, iclass 21, count 0 2006.173.02:06:49.31#ibcon#end of sib2, iclass 21, count 0 2006.173.02:06:49.31#ibcon#*after write, iclass 21, count 0 2006.173.02:06:49.31#ibcon#*before return 0, iclass 21, count 0 2006.173.02:06:49.31#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.02:06:49.31#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.02:06:49.31#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.02:06:49.31#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.02:06:49.32$vck44/valo=3,564.99 2006.173.02:06:49.32#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.02:06:49.32#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.02:06:49.32#ibcon#ireg 17 cls_cnt 0 2006.173.02:06:49.32#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.02:06:49.32#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.02:06:49.32#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.02:06:49.32#ibcon#enter wrdev, iclass 23, count 0 2006.173.02:06:49.32#ibcon#first serial, iclass 23, count 0 2006.173.02:06:49.32#ibcon#enter sib2, iclass 23, count 0 2006.173.02:06:49.32#ibcon#flushed, iclass 23, count 0 2006.173.02:06:49.32#ibcon#about to write, iclass 23, count 0 2006.173.02:06:49.32#ibcon#wrote, iclass 23, count 0 2006.173.02:06:49.32#ibcon#about to read 3, iclass 23, count 0 2006.173.02:06:49.33#ibcon#read 3, iclass 23, count 0 2006.173.02:06:49.33#ibcon#about to read 4, iclass 23, count 0 2006.173.02:06:49.33#ibcon#read 4, iclass 23, count 0 2006.173.02:06:49.33#ibcon#about to read 5, iclass 23, count 0 2006.173.02:06:49.33#ibcon#read 5, iclass 23, count 0 2006.173.02:06:49.33#ibcon#about to read 6, iclass 23, count 0 2006.173.02:06:49.33#ibcon#read 6, iclass 23, count 0 2006.173.02:06:49.33#ibcon#end of sib2, iclass 23, count 0 2006.173.02:06:49.33#ibcon#*mode == 0, iclass 23, count 0 2006.173.02:06:49.33#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.02:06:49.33#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.02:06:49.33#ibcon#*before write, iclass 23, count 0 2006.173.02:06:49.33#ibcon#enter sib2, iclass 23, count 0 2006.173.02:06:49.33#ibcon#flushed, iclass 23, count 0 2006.173.02:06:49.33#ibcon#about to write, iclass 23, count 0 2006.173.02:06:49.33#ibcon#wrote, iclass 23, count 0 2006.173.02:06:49.33#ibcon#about to read 3, iclass 23, count 0 2006.173.02:06:49.38#ibcon#read 3, iclass 23, count 0 2006.173.02:06:49.38#ibcon#about to read 4, iclass 23, count 0 2006.173.02:06:49.38#ibcon#read 4, iclass 23, count 0 2006.173.02:06:49.38#ibcon#about to read 5, iclass 23, count 0 2006.173.02:06:49.38#ibcon#read 5, iclass 23, count 0 2006.173.02:06:49.38#ibcon#about to read 6, iclass 23, count 0 2006.173.02:06:49.38#ibcon#read 6, iclass 23, count 0 2006.173.02:06:49.38#ibcon#end of sib2, iclass 23, count 0 2006.173.02:06:49.38#ibcon#*after write, iclass 23, count 0 2006.173.02:06:49.38#ibcon#*before return 0, iclass 23, count 0 2006.173.02:06:49.38#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.02:06:49.38#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.02:06:49.38#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.02:06:49.38#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.02:06:49.38$vck44/va=3,5 2006.173.02:06:49.38#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.02:06:49.38#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.02:06:49.38#ibcon#ireg 11 cls_cnt 2 2006.173.02:06:49.38#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.02:06:49.42#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.02:06:49.42#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.02:06:49.42#ibcon#enter wrdev, iclass 25, count 2 2006.173.02:06:49.42#ibcon#first serial, iclass 25, count 2 2006.173.02:06:49.42#ibcon#enter sib2, iclass 25, count 2 2006.173.02:06:49.42#ibcon#flushed, iclass 25, count 2 2006.173.02:06:49.42#ibcon#about to write, iclass 25, count 2 2006.173.02:06:49.42#ibcon#wrote, iclass 25, count 2 2006.173.02:06:49.42#ibcon#about to read 3, iclass 25, count 2 2006.173.02:06:49.44#ibcon#read 3, iclass 25, count 2 2006.173.02:06:49.44#ibcon#about to read 4, iclass 25, count 2 2006.173.02:06:49.44#ibcon#read 4, iclass 25, count 2 2006.173.02:06:49.44#ibcon#about to read 5, iclass 25, count 2 2006.173.02:06:49.44#ibcon#read 5, iclass 25, count 2 2006.173.02:06:49.44#ibcon#about to read 6, iclass 25, count 2 2006.173.02:06:49.44#ibcon#read 6, iclass 25, count 2 2006.173.02:06:49.44#ibcon#end of sib2, iclass 25, count 2 2006.173.02:06:49.44#ibcon#*mode == 0, iclass 25, count 2 2006.173.02:06:49.44#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.02:06:49.44#ibcon#[25=AT03-05\r\n] 2006.173.02:06:49.44#ibcon#*before write, iclass 25, count 2 2006.173.02:06:49.44#ibcon#enter sib2, iclass 25, count 2 2006.173.02:06:49.44#ibcon#flushed, iclass 25, count 2 2006.173.02:06:49.44#ibcon#about to write, iclass 25, count 2 2006.173.02:06:49.44#ibcon#wrote, iclass 25, count 2 2006.173.02:06:49.44#ibcon#about to read 3, iclass 25, count 2 2006.173.02:06:49.47#ibcon#read 3, iclass 25, count 2 2006.173.02:06:49.47#ibcon#about to read 4, iclass 25, count 2 2006.173.02:06:49.47#ibcon#read 4, iclass 25, count 2 2006.173.02:06:49.47#ibcon#about to read 5, iclass 25, count 2 2006.173.02:06:49.47#ibcon#read 5, iclass 25, count 2 2006.173.02:06:49.47#ibcon#about to read 6, iclass 25, count 2 2006.173.02:06:49.47#ibcon#read 6, iclass 25, count 2 2006.173.02:06:49.47#ibcon#end of sib2, iclass 25, count 2 2006.173.02:06:49.47#ibcon#*after write, iclass 25, count 2 2006.173.02:06:49.47#ibcon#*before return 0, iclass 25, count 2 2006.173.02:06:49.47#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.02:06:49.47#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.02:06:49.47#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.02:06:49.47#ibcon#ireg 7 cls_cnt 0 2006.173.02:06:49.47#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.02:06:49.59#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.02:06:49.59#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.02:06:49.59#ibcon#enter wrdev, iclass 25, count 0 2006.173.02:06:49.59#ibcon#first serial, iclass 25, count 0 2006.173.02:06:49.59#ibcon#enter sib2, iclass 25, count 0 2006.173.02:06:49.59#ibcon#flushed, iclass 25, count 0 2006.173.02:06:49.59#ibcon#about to write, iclass 25, count 0 2006.173.02:06:49.59#ibcon#wrote, iclass 25, count 0 2006.173.02:06:49.59#ibcon#about to read 3, iclass 25, count 0 2006.173.02:06:49.61#ibcon#read 3, iclass 25, count 0 2006.173.02:06:49.61#ibcon#about to read 4, iclass 25, count 0 2006.173.02:06:49.61#ibcon#read 4, iclass 25, count 0 2006.173.02:06:49.61#ibcon#about to read 5, iclass 25, count 0 2006.173.02:06:49.61#ibcon#read 5, iclass 25, count 0 2006.173.02:06:49.61#ibcon#about to read 6, iclass 25, count 0 2006.173.02:06:49.61#ibcon#read 6, iclass 25, count 0 2006.173.02:06:49.61#ibcon#end of sib2, iclass 25, count 0 2006.173.02:06:49.61#ibcon#*mode == 0, iclass 25, count 0 2006.173.02:06:49.61#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.02:06:49.61#ibcon#[25=USB\r\n] 2006.173.02:06:49.61#ibcon#*before write, iclass 25, count 0 2006.173.02:06:49.61#ibcon#enter sib2, iclass 25, count 0 2006.173.02:06:49.61#ibcon#flushed, iclass 25, count 0 2006.173.02:06:49.61#ibcon#about to write, iclass 25, count 0 2006.173.02:06:49.61#ibcon#wrote, iclass 25, count 0 2006.173.02:06:49.61#ibcon#about to read 3, iclass 25, count 0 2006.173.02:06:49.64#ibcon#read 3, iclass 25, count 0 2006.173.02:06:49.64#ibcon#about to read 4, iclass 25, count 0 2006.173.02:06:49.64#ibcon#read 4, iclass 25, count 0 2006.173.02:06:49.64#ibcon#about to read 5, iclass 25, count 0 2006.173.02:06:49.64#ibcon#read 5, iclass 25, count 0 2006.173.02:06:49.64#ibcon#about to read 6, iclass 25, count 0 2006.173.02:06:49.64#ibcon#read 6, iclass 25, count 0 2006.173.02:06:49.64#ibcon#end of sib2, iclass 25, count 0 2006.173.02:06:49.64#ibcon#*after write, iclass 25, count 0 2006.173.02:06:49.64#ibcon#*before return 0, iclass 25, count 0 2006.173.02:06:49.64#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.02:06:49.64#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.02:06:49.64#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.02:06:49.64#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.02:06:49.65$vck44/valo=4,624.99 2006.173.02:06:49.65#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.02:06:49.65#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.02:06:49.65#ibcon#ireg 17 cls_cnt 0 2006.173.02:06:49.65#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.02:06:49.65#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.02:06:49.65#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.02:06:49.65#ibcon#enter wrdev, iclass 27, count 0 2006.173.02:06:49.65#ibcon#first serial, iclass 27, count 0 2006.173.02:06:49.65#ibcon#enter sib2, iclass 27, count 0 2006.173.02:06:49.65#ibcon#flushed, iclass 27, count 0 2006.173.02:06:49.65#ibcon#about to write, iclass 27, count 0 2006.173.02:06:49.65#ibcon#wrote, iclass 27, count 0 2006.173.02:06:49.65#ibcon#about to read 3, iclass 27, count 0 2006.173.02:06:49.66#ibcon#read 3, iclass 27, count 0 2006.173.02:06:49.66#ibcon#about to read 4, iclass 27, count 0 2006.173.02:06:49.66#ibcon#read 4, iclass 27, count 0 2006.173.02:06:49.66#ibcon#about to read 5, iclass 27, count 0 2006.173.02:06:49.66#ibcon#read 5, iclass 27, count 0 2006.173.02:06:49.66#ibcon#about to read 6, iclass 27, count 0 2006.173.02:06:49.66#ibcon#read 6, iclass 27, count 0 2006.173.02:06:49.66#ibcon#end of sib2, iclass 27, count 0 2006.173.02:06:49.66#ibcon#*mode == 0, iclass 27, count 0 2006.173.02:06:49.66#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.02:06:49.66#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.02:06:49.66#ibcon#*before write, iclass 27, count 0 2006.173.02:06:49.66#ibcon#enter sib2, iclass 27, count 0 2006.173.02:06:49.66#ibcon#flushed, iclass 27, count 0 2006.173.02:06:49.66#ibcon#about to write, iclass 27, count 0 2006.173.02:06:49.66#ibcon#wrote, iclass 27, count 0 2006.173.02:06:49.66#ibcon#about to read 3, iclass 27, count 0 2006.173.02:06:49.70#ibcon#read 3, iclass 27, count 0 2006.173.02:06:49.70#ibcon#about to read 4, iclass 27, count 0 2006.173.02:06:49.70#ibcon#read 4, iclass 27, count 0 2006.173.02:06:49.70#ibcon#about to read 5, iclass 27, count 0 2006.173.02:06:49.70#ibcon#read 5, iclass 27, count 0 2006.173.02:06:49.70#ibcon#about to read 6, iclass 27, count 0 2006.173.02:06:49.70#ibcon#read 6, iclass 27, count 0 2006.173.02:06:49.70#ibcon#end of sib2, iclass 27, count 0 2006.173.02:06:49.70#ibcon#*after write, iclass 27, count 0 2006.173.02:06:49.70#ibcon#*before return 0, iclass 27, count 0 2006.173.02:06:49.70#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.02:06:49.70#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.02:06:49.70#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.02:06:49.70#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.02:06:49.71$vck44/va=4,6 2006.173.02:06:49.71#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.02:06:49.71#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.02:06:49.71#ibcon#ireg 11 cls_cnt 2 2006.173.02:06:49.71#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.02:06:49.75#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.02:06:49.75#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.02:06:49.75#ibcon#enter wrdev, iclass 29, count 2 2006.173.02:06:49.75#ibcon#first serial, iclass 29, count 2 2006.173.02:06:49.75#ibcon#enter sib2, iclass 29, count 2 2006.173.02:06:49.75#ibcon#flushed, iclass 29, count 2 2006.173.02:06:49.75#ibcon#about to write, iclass 29, count 2 2006.173.02:06:49.75#ibcon#wrote, iclass 29, count 2 2006.173.02:06:49.75#ibcon#about to read 3, iclass 29, count 2 2006.173.02:06:49.77#ibcon#read 3, iclass 29, count 2 2006.173.02:06:49.77#ibcon#about to read 4, iclass 29, count 2 2006.173.02:06:49.77#ibcon#read 4, iclass 29, count 2 2006.173.02:06:49.77#ibcon#about to read 5, iclass 29, count 2 2006.173.02:06:49.77#ibcon#read 5, iclass 29, count 2 2006.173.02:06:49.77#ibcon#about to read 6, iclass 29, count 2 2006.173.02:06:49.77#ibcon#read 6, iclass 29, count 2 2006.173.02:06:49.77#ibcon#end of sib2, iclass 29, count 2 2006.173.02:06:49.77#ibcon#*mode == 0, iclass 29, count 2 2006.173.02:06:49.77#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.02:06:49.77#ibcon#[25=AT04-06\r\n] 2006.173.02:06:49.77#ibcon#*before write, iclass 29, count 2 2006.173.02:06:49.77#ibcon#enter sib2, iclass 29, count 2 2006.173.02:06:49.77#ibcon#flushed, iclass 29, count 2 2006.173.02:06:49.77#ibcon#about to write, iclass 29, count 2 2006.173.02:06:49.77#ibcon#wrote, iclass 29, count 2 2006.173.02:06:49.77#ibcon#about to read 3, iclass 29, count 2 2006.173.02:06:49.80#ibcon#read 3, iclass 29, count 2 2006.173.02:06:49.80#ibcon#about to read 4, iclass 29, count 2 2006.173.02:06:49.80#ibcon#read 4, iclass 29, count 2 2006.173.02:06:49.80#ibcon#about to read 5, iclass 29, count 2 2006.173.02:06:49.80#ibcon#read 5, iclass 29, count 2 2006.173.02:06:49.80#ibcon#about to read 6, iclass 29, count 2 2006.173.02:06:49.80#ibcon#read 6, iclass 29, count 2 2006.173.02:06:49.80#ibcon#end of sib2, iclass 29, count 2 2006.173.02:06:49.80#ibcon#*after write, iclass 29, count 2 2006.173.02:06:49.80#ibcon#*before return 0, iclass 29, count 2 2006.173.02:06:49.80#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.02:06:49.80#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.02:06:49.80#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.02:06:49.80#ibcon#ireg 7 cls_cnt 0 2006.173.02:06:49.80#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.02:06:49.92#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.02:06:49.92#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.02:06:49.92#ibcon#enter wrdev, iclass 29, count 0 2006.173.02:06:49.92#ibcon#first serial, iclass 29, count 0 2006.173.02:06:49.92#ibcon#enter sib2, iclass 29, count 0 2006.173.02:06:49.92#ibcon#flushed, iclass 29, count 0 2006.173.02:06:49.92#ibcon#about to write, iclass 29, count 0 2006.173.02:06:49.92#ibcon#wrote, iclass 29, count 0 2006.173.02:06:49.92#ibcon#about to read 3, iclass 29, count 0 2006.173.02:06:49.94#ibcon#read 3, iclass 29, count 0 2006.173.02:06:49.94#ibcon#about to read 4, iclass 29, count 0 2006.173.02:06:49.94#ibcon#read 4, iclass 29, count 0 2006.173.02:06:49.94#ibcon#about to read 5, iclass 29, count 0 2006.173.02:06:49.94#ibcon#read 5, iclass 29, count 0 2006.173.02:06:49.94#ibcon#about to read 6, iclass 29, count 0 2006.173.02:06:49.94#ibcon#read 6, iclass 29, count 0 2006.173.02:06:49.94#ibcon#end of sib2, iclass 29, count 0 2006.173.02:06:49.94#ibcon#*mode == 0, iclass 29, count 0 2006.173.02:06:49.94#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.02:06:49.94#ibcon#[25=USB\r\n] 2006.173.02:06:49.94#ibcon#*before write, iclass 29, count 0 2006.173.02:06:49.94#ibcon#enter sib2, iclass 29, count 0 2006.173.02:06:49.94#ibcon#flushed, iclass 29, count 0 2006.173.02:06:49.94#ibcon#about to write, iclass 29, count 0 2006.173.02:06:49.94#ibcon#wrote, iclass 29, count 0 2006.173.02:06:49.94#ibcon#about to read 3, iclass 29, count 0 2006.173.02:06:49.97#ibcon#read 3, iclass 29, count 0 2006.173.02:06:49.97#ibcon#about to read 4, iclass 29, count 0 2006.173.02:06:49.97#ibcon#read 4, iclass 29, count 0 2006.173.02:06:49.97#ibcon#about to read 5, iclass 29, count 0 2006.173.02:06:49.97#ibcon#read 5, iclass 29, count 0 2006.173.02:06:49.97#ibcon#about to read 6, iclass 29, count 0 2006.173.02:06:49.97#ibcon#read 6, iclass 29, count 0 2006.173.02:06:49.97#ibcon#end of sib2, iclass 29, count 0 2006.173.02:06:49.97#ibcon#*after write, iclass 29, count 0 2006.173.02:06:49.97#ibcon#*before return 0, iclass 29, count 0 2006.173.02:06:49.97#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.02:06:49.97#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.02:06:49.97#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.02:06:49.97#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.02:06:49.98$vck44/valo=5,734.99 2006.173.02:06:49.98#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.02:06:49.98#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.02:06:49.98#ibcon#ireg 17 cls_cnt 0 2006.173.02:06:49.98#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.02:06:49.98#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.02:06:49.98#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.02:06:49.98#ibcon#enter wrdev, iclass 31, count 0 2006.173.02:06:49.98#ibcon#first serial, iclass 31, count 0 2006.173.02:06:49.98#ibcon#enter sib2, iclass 31, count 0 2006.173.02:06:49.98#ibcon#flushed, iclass 31, count 0 2006.173.02:06:49.98#ibcon#about to write, iclass 31, count 0 2006.173.02:06:49.98#ibcon#wrote, iclass 31, count 0 2006.173.02:06:49.98#ibcon#about to read 3, iclass 31, count 0 2006.173.02:06:49.99#ibcon#read 3, iclass 31, count 0 2006.173.02:06:49.99#ibcon#about to read 4, iclass 31, count 0 2006.173.02:06:49.99#ibcon#read 4, iclass 31, count 0 2006.173.02:06:49.99#ibcon#about to read 5, iclass 31, count 0 2006.173.02:06:49.99#ibcon#read 5, iclass 31, count 0 2006.173.02:06:49.99#ibcon#about to read 6, iclass 31, count 0 2006.173.02:06:49.99#ibcon#read 6, iclass 31, count 0 2006.173.02:06:49.99#ibcon#end of sib2, iclass 31, count 0 2006.173.02:06:49.99#ibcon#*mode == 0, iclass 31, count 0 2006.173.02:06:49.99#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.02:06:49.99#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.02:06:49.99#ibcon#*before write, iclass 31, count 0 2006.173.02:06:49.99#ibcon#enter sib2, iclass 31, count 0 2006.173.02:06:49.99#ibcon#flushed, iclass 31, count 0 2006.173.02:06:49.99#ibcon#about to write, iclass 31, count 0 2006.173.02:06:49.99#ibcon#wrote, iclass 31, count 0 2006.173.02:06:49.99#ibcon#about to read 3, iclass 31, count 0 2006.173.02:06:50.03#ibcon#read 3, iclass 31, count 0 2006.173.02:06:50.03#ibcon#about to read 4, iclass 31, count 0 2006.173.02:06:50.03#ibcon#read 4, iclass 31, count 0 2006.173.02:06:50.03#ibcon#about to read 5, iclass 31, count 0 2006.173.02:06:50.03#ibcon#read 5, iclass 31, count 0 2006.173.02:06:50.03#ibcon#about to read 6, iclass 31, count 0 2006.173.02:06:50.03#ibcon#read 6, iclass 31, count 0 2006.173.02:06:50.03#ibcon#end of sib2, iclass 31, count 0 2006.173.02:06:50.03#ibcon#*after write, iclass 31, count 0 2006.173.02:06:50.03#ibcon#*before return 0, iclass 31, count 0 2006.173.02:06:50.03#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.02:06:50.03#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.02:06:50.03#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.02:06:50.03#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.02:06:50.04$vck44/va=5,4 2006.173.02:06:50.04#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.173.02:06:50.04#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.173.02:06:50.04#ibcon#ireg 11 cls_cnt 2 2006.173.02:06:50.04#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.02:06:50.08#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.02:06:50.08#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.02:06:50.08#ibcon#enter wrdev, iclass 33, count 2 2006.173.02:06:50.08#ibcon#first serial, iclass 33, count 2 2006.173.02:06:50.08#ibcon#enter sib2, iclass 33, count 2 2006.173.02:06:50.08#ibcon#flushed, iclass 33, count 2 2006.173.02:06:50.08#ibcon#about to write, iclass 33, count 2 2006.173.02:06:50.08#ibcon#wrote, iclass 33, count 2 2006.173.02:06:50.08#ibcon#about to read 3, iclass 33, count 2 2006.173.02:06:50.10#ibcon#read 3, iclass 33, count 2 2006.173.02:06:50.10#ibcon#about to read 4, iclass 33, count 2 2006.173.02:06:50.10#ibcon#read 4, iclass 33, count 2 2006.173.02:06:50.10#ibcon#about to read 5, iclass 33, count 2 2006.173.02:06:50.10#ibcon#read 5, iclass 33, count 2 2006.173.02:06:50.10#ibcon#about to read 6, iclass 33, count 2 2006.173.02:06:50.10#ibcon#read 6, iclass 33, count 2 2006.173.02:06:50.10#ibcon#end of sib2, iclass 33, count 2 2006.173.02:06:50.10#ibcon#*mode == 0, iclass 33, count 2 2006.173.02:06:50.10#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.173.02:06:50.10#ibcon#[25=AT05-04\r\n] 2006.173.02:06:50.10#ibcon#*before write, iclass 33, count 2 2006.173.02:06:50.10#ibcon#enter sib2, iclass 33, count 2 2006.173.02:06:50.10#ibcon#flushed, iclass 33, count 2 2006.173.02:06:50.10#ibcon#about to write, iclass 33, count 2 2006.173.02:06:50.10#ibcon#wrote, iclass 33, count 2 2006.173.02:06:50.10#ibcon#about to read 3, iclass 33, count 2 2006.173.02:06:50.14#ibcon#read 3, iclass 33, count 2 2006.173.02:06:50.14#ibcon#about to read 4, iclass 33, count 2 2006.173.02:06:50.14#ibcon#read 4, iclass 33, count 2 2006.173.02:06:50.14#ibcon#about to read 5, iclass 33, count 2 2006.173.02:06:50.14#ibcon#read 5, iclass 33, count 2 2006.173.02:06:50.14#ibcon#about to read 6, iclass 33, count 2 2006.173.02:06:50.14#ibcon#read 6, iclass 33, count 2 2006.173.02:06:50.14#ibcon#end of sib2, iclass 33, count 2 2006.173.02:06:50.14#ibcon#*after write, iclass 33, count 2 2006.173.02:06:50.14#ibcon#*before return 0, iclass 33, count 2 2006.173.02:06:50.14#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.02:06:50.14#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.173.02:06:50.14#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.173.02:06:50.14#ibcon#ireg 7 cls_cnt 0 2006.173.02:06:50.14#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.02:06:50.25#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.02:06:50.25#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.02:06:50.25#ibcon#enter wrdev, iclass 33, count 0 2006.173.02:06:50.25#ibcon#first serial, iclass 33, count 0 2006.173.02:06:50.25#ibcon#enter sib2, iclass 33, count 0 2006.173.02:06:50.25#ibcon#flushed, iclass 33, count 0 2006.173.02:06:50.25#ibcon#about to write, iclass 33, count 0 2006.173.02:06:50.25#ibcon#wrote, iclass 33, count 0 2006.173.02:06:50.25#ibcon#about to read 3, iclass 33, count 0 2006.173.02:06:50.27#ibcon#read 3, iclass 33, count 0 2006.173.02:06:50.27#ibcon#about to read 4, iclass 33, count 0 2006.173.02:06:50.27#ibcon#read 4, iclass 33, count 0 2006.173.02:06:50.27#ibcon#about to read 5, iclass 33, count 0 2006.173.02:06:50.27#ibcon#read 5, iclass 33, count 0 2006.173.02:06:50.27#ibcon#about to read 6, iclass 33, count 0 2006.173.02:06:50.27#ibcon#read 6, iclass 33, count 0 2006.173.02:06:50.27#ibcon#end of sib2, iclass 33, count 0 2006.173.02:06:50.27#ibcon#*mode == 0, iclass 33, count 0 2006.173.02:06:50.27#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.02:06:50.27#ibcon#[25=USB\r\n] 2006.173.02:06:50.27#ibcon#*before write, iclass 33, count 0 2006.173.02:06:50.27#ibcon#enter sib2, iclass 33, count 0 2006.173.02:06:50.27#ibcon#flushed, iclass 33, count 0 2006.173.02:06:50.27#ibcon#about to write, iclass 33, count 0 2006.173.02:06:50.27#ibcon#wrote, iclass 33, count 0 2006.173.02:06:50.27#ibcon#about to read 3, iclass 33, count 0 2006.173.02:06:50.30#ibcon#read 3, iclass 33, count 0 2006.173.02:06:50.30#ibcon#about to read 4, iclass 33, count 0 2006.173.02:06:50.30#ibcon#read 4, iclass 33, count 0 2006.173.02:06:50.30#ibcon#about to read 5, iclass 33, count 0 2006.173.02:06:50.30#ibcon#read 5, iclass 33, count 0 2006.173.02:06:50.30#ibcon#about to read 6, iclass 33, count 0 2006.173.02:06:50.30#ibcon#read 6, iclass 33, count 0 2006.173.02:06:50.30#ibcon#end of sib2, iclass 33, count 0 2006.173.02:06:50.30#ibcon#*after write, iclass 33, count 0 2006.173.02:06:50.30#ibcon#*before return 0, iclass 33, count 0 2006.173.02:06:50.30#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.02:06:50.30#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.173.02:06:50.30#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.02:06:50.30#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.02:06:50.31$vck44/valo=6,814.99 2006.173.02:06:50.31#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.02:06:50.31#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.02:06:50.31#ibcon#ireg 17 cls_cnt 0 2006.173.02:06:50.31#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.02:06:50.31#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.02:06:50.31#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.02:06:50.31#ibcon#enter wrdev, iclass 35, count 0 2006.173.02:06:50.31#ibcon#first serial, iclass 35, count 0 2006.173.02:06:50.31#ibcon#enter sib2, iclass 35, count 0 2006.173.02:06:50.31#ibcon#flushed, iclass 35, count 0 2006.173.02:06:50.31#ibcon#about to write, iclass 35, count 0 2006.173.02:06:50.31#ibcon#wrote, iclass 35, count 0 2006.173.02:06:50.31#ibcon#about to read 3, iclass 35, count 0 2006.173.02:06:50.32#ibcon#read 3, iclass 35, count 0 2006.173.02:06:50.32#ibcon#about to read 4, iclass 35, count 0 2006.173.02:06:50.32#ibcon#read 4, iclass 35, count 0 2006.173.02:06:50.32#ibcon#about to read 5, iclass 35, count 0 2006.173.02:06:50.32#ibcon#read 5, iclass 35, count 0 2006.173.02:06:50.32#ibcon#about to read 6, iclass 35, count 0 2006.173.02:06:50.32#ibcon#read 6, iclass 35, count 0 2006.173.02:06:50.32#ibcon#end of sib2, iclass 35, count 0 2006.173.02:06:50.32#ibcon#*mode == 0, iclass 35, count 0 2006.173.02:06:50.32#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.02:06:50.32#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.02:06:50.32#ibcon#*before write, iclass 35, count 0 2006.173.02:06:50.32#ibcon#enter sib2, iclass 35, count 0 2006.173.02:06:50.32#ibcon#flushed, iclass 35, count 0 2006.173.02:06:50.32#ibcon#about to write, iclass 35, count 0 2006.173.02:06:50.32#ibcon#wrote, iclass 35, count 0 2006.173.02:06:50.32#ibcon#about to read 3, iclass 35, count 0 2006.173.02:06:50.36#ibcon#read 3, iclass 35, count 0 2006.173.02:06:50.36#ibcon#about to read 4, iclass 35, count 0 2006.173.02:06:50.36#ibcon#read 4, iclass 35, count 0 2006.173.02:06:50.36#ibcon#about to read 5, iclass 35, count 0 2006.173.02:06:50.36#ibcon#read 5, iclass 35, count 0 2006.173.02:06:50.36#ibcon#about to read 6, iclass 35, count 0 2006.173.02:06:50.36#ibcon#read 6, iclass 35, count 0 2006.173.02:06:50.36#ibcon#end of sib2, iclass 35, count 0 2006.173.02:06:50.36#ibcon#*after write, iclass 35, count 0 2006.173.02:06:50.36#ibcon#*before return 0, iclass 35, count 0 2006.173.02:06:50.36#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.02:06:50.36#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.02:06:50.36#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.02:06:50.36#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.02:06:50.37$vck44/va=6,3 2006.173.02:06:50.37#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.173.02:06:50.37#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.173.02:06:50.37#ibcon#ireg 11 cls_cnt 2 2006.173.02:06:50.37#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.02:06:50.41#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.02:06:50.41#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.02:06:50.41#ibcon#enter wrdev, iclass 37, count 2 2006.173.02:06:50.41#ibcon#first serial, iclass 37, count 2 2006.173.02:06:50.41#ibcon#enter sib2, iclass 37, count 2 2006.173.02:06:50.41#ibcon#flushed, iclass 37, count 2 2006.173.02:06:50.41#ibcon#about to write, iclass 37, count 2 2006.173.02:06:50.41#ibcon#wrote, iclass 37, count 2 2006.173.02:06:50.41#ibcon#about to read 3, iclass 37, count 2 2006.173.02:06:50.43#ibcon#read 3, iclass 37, count 2 2006.173.02:06:50.43#ibcon#about to read 4, iclass 37, count 2 2006.173.02:06:50.43#ibcon#read 4, iclass 37, count 2 2006.173.02:06:50.43#ibcon#about to read 5, iclass 37, count 2 2006.173.02:06:50.43#ibcon#read 5, iclass 37, count 2 2006.173.02:06:50.43#ibcon#about to read 6, iclass 37, count 2 2006.173.02:06:50.43#ibcon#read 6, iclass 37, count 2 2006.173.02:06:50.43#ibcon#end of sib2, iclass 37, count 2 2006.173.02:06:50.43#ibcon#*mode == 0, iclass 37, count 2 2006.173.02:06:50.43#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.173.02:06:50.43#ibcon#[25=AT06-03\r\n] 2006.173.02:06:50.43#ibcon#*before write, iclass 37, count 2 2006.173.02:06:50.43#ibcon#enter sib2, iclass 37, count 2 2006.173.02:06:50.43#ibcon#flushed, iclass 37, count 2 2006.173.02:06:50.43#ibcon#about to write, iclass 37, count 2 2006.173.02:06:50.43#ibcon#wrote, iclass 37, count 2 2006.173.02:06:50.43#ibcon#about to read 3, iclass 37, count 2 2006.173.02:06:50.46#ibcon#read 3, iclass 37, count 2 2006.173.02:06:50.46#ibcon#about to read 4, iclass 37, count 2 2006.173.02:06:50.46#ibcon#read 4, iclass 37, count 2 2006.173.02:06:50.46#ibcon#about to read 5, iclass 37, count 2 2006.173.02:06:50.46#ibcon#read 5, iclass 37, count 2 2006.173.02:06:50.46#ibcon#about to read 6, iclass 37, count 2 2006.173.02:06:50.46#ibcon#read 6, iclass 37, count 2 2006.173.02:06:50.46#ibcon#end of sib2, iclass 37, count 2 2006.173.02:06:50.46#ibcon#*after write, iclass 37, count 2 2006.173.02:06:50.46#ibcon#*before return 0, iclass 37, count 2 2006.173.02:06:50.46#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.02:06:50.46#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.173.02:06:50.46#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.173.02:06:50.46#ibcon#ireg 7 cls_cnt 0 2006.173.02:06:50.46#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.02:06:50.58#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.02:06:50.58#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.02:06:50.58#ibcon#enter wrdev, iclass 37, count 0 2006.173.02:06:50.58#ibcon#first serial, iclass 37, count 0 2006.173.02:06:50.58#ibcon#enter sib2, iclass 37, count 0 2006.173.02:06:50.58#ibcon#flushed, iclass 37, count 0 2006.173.02:06:50.58#ibcon#about to write, iclass 37, count 0 2006.173.02:06:50.58#ibcon#wrote, iclass 37, count 0 2006.173.02:06:50.58#ibcon#about to read 3, iclass 37, count 0 2006.173.02:06:50.60#ibcon#read 3, iclass 37, count 0 2006.173.02:06:50.60#ibcon#about to read 4, iclass 37, count 0 2006.173.02:06:50.60#ibcon#read 4, iclass 37, count 0 2006.173.02:06:50.60#ibcon#about to read 5, iclass 37, count 0 2006.173.02:06:50.60#ibcon#read 5, iclass 37, count 0 2006.173.02:06:50.60#ibcon#about to read 6, iclass 37, count 0 2006.173.02:06:50.60#ibcon#read 6, iclass 37, count 0 2006.173.02:06:50.60#ibcon#end of sib2, iclass 37, count 0 2006.173.02:06:50.60#ibcon#*mode == 0, iclass 37, count 0 2006.173.02:06:50.60#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.02:06:50.60#ibcon#[25=USB\r\n] 2006.173.02:06:50.60#ibcon#*before write, iclass 37, count 0 2006.173.02:06:50.60#ibcon#enter sib2, iclass 37, count 0 2006.173.02:06:50.60#ibcon#flushed, iclass 37, count 0 2006.173.02:06:50.60#ibcon#about to write, iclass 37, count 0 2006.173.02:06:50.60#ibcon#wrote, iclass 37, count 0 2006.173.02:06:50.60#ibcon#about to read 3, iclass 37, count 0 2006.173.02:06:50.63#ibcon#read 3, iclass 37, count 0 2006.173.02:06:50.63#ibcon#about to read 4, iclass 37, count 0 2006.173.02:06:50.63#ibcon#read 4, iclass 37, count 0 2006.173.02:06:50.63#ibcon#about to read 5, iclass 37, count 0 2006.173.02:06:50.63#ibcon#read 5, iclass 37, count 0 2006.173.02:06:50.63#ibcon#about to read 6, iclass 37, count 0 2006.173.02:06:50.63#ibcon#read 6, iclass 37, count 0 2006.173.02:06:50.63#ibcon#end of sib2, iclass 37, count 0 2006.173.02:06:50.63#ibcon#*after write, iclass 37, count 0 2006.173.02:06:50.63#ibcon#*before return 0, iclass 37, count 0 2006.173.02:06:50.63#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.02:06:50.63#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.173.02:06:50.63#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.02:06:50.63#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.02:06:50.64$vck44/valo=7,864.99 2006.173.02:06:50.64#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.02:06:50.64#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.02:06:50.64#ibcon#ireg 17 cls_cnt 0 2006.173.02:06:50.64#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.02:06:50.64#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.02:06:50.64#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.02:06:50.64#ibcon#enter wrdev, iclass 39, count 0 2006.173.02:06:50.64#ibcon#first serial, iclass 39, count 0 2006.173.02:06:50.64#ibcon#enter sib2, iclass 39, count 0 2006.173.02:06:50.64#ibcon#flushed, iclass 39, count 0 2006.173.02:06:50.64#ibcon#about to write, iclass 39, count 0 2006.173.02:06:50.64#ibcon#wrote, iclass 39, count 0 2006.173.02:06:50.64#ibcon#about to read 3, iclass 39, count 0 2006.173.02:06:50.65#ibcon#read 3, iclass 39, count 0 2006.173.02:06:50.65#ibcon#about to read 4, iclass 39, count 0 2006.173.02:06:50.65#ibcon#read 4, iclass 39, count 0 2006.173.02:06:50.65#ibcon#about to read 5, iclass 39, count 0 2006.173.02:06:50.65#ibcon#read 5, iclass 39, count 0 2006.173.02:06:50.65#ibcon#about to read 6, iclass 39, count 0 2006.173.02:06:50.65#ibcon#read 6, iclass 39, count 0 2006.173.02:06:50.65#ibcon#end of sib2, iclass 39, count 0 2006.173.02:06:50.65#ibcon#*mode == 0, iclass 39, count 0 2006.173.02:06:50.65#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.02:06:50.65#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.02:06:50.65#ibcon#*before write, iclass 39, count 0 2006.173.02:06:50.65#ibcon#enter sib2, iclass 39, count 0 2006.173.02:06:50.65#ibcon#flushed, iclass 39, count 0 2006.173.02:06:50.65#ibcon#about to write, iclass 39, count 0 2006.173.02:06:50.65#ibcon#wrote, iclass 39, count 0 2006.173.02:06:50.65#ibcon#about to read 3, iclass 39, count 0 2006.173.02:06:50.69#ibcon#read 3, iclass 39, count 0 2006.173.02:06:50.69#ibcon#about to read 4, iclass 39, count 0 2006.173.02:06:50.69#ibcon#read 4, iclass 39, count 0 2006.173.02:06:50.69#ibcon#about to read 5, iclass 39, count 0 2006.173.02:06:50.69#ibcon#read 5, iclass 39, count 0 2006.173.02:06:50.69#ibcon#about to read 6, iclass 39, count 0 2006.173.02:06:50.69#ibcon#read 6, iclass 39, count 0 2006.173.02:06:50.69#ibcon#end of sib2, iclass 39, count 0 2006.173.02:06:50.69#ibcon#*after write, iclass 39, count 0 2006.173.02:06:50.69#ibcon#*before return 0, iclass 39, count 0 2006.173.02:06:50.69#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.02:06:50.69#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.02:06:50.69#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.02:06:50.69#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.02:06:50.70$vck44/va=7,4 2006.173.02:06:50.70#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.02:06:50.70#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.02:06:50.70#ibcon#ireg 11 cls_cnt 2 2006.173.02:06:50.70#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.02:06:50.74#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.02:06:50.74#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.02:06:50.74#ibcon#enter wrdev, iclass 3, count 2 2006.173.02:06:50.74#ibcon#first serial, iclass 3, count 2 2006.173.02:06:50.74#ibcon#enter sib2, iclass 3, count 2 2006.173.02:06:50.74#ibcon#flushed, iclass 3, count 2 2006.173.02:06:50.74#ibcon#about to write, iclass 3, count 2 2006.173.02:06:50.74#ibcon#wrote, iclass 3, count 2 2006.173.02:06:50.74#ibcon#about to read 3, iclass 3, count 2 2006.173.02:06:50.76#ibcon#read 3, iclass 3, count 2 2006.173.02:06:50.76#ibcon#about to read 4, iclass 3, count 2 2006.173.02:06:50.76#ibcon#read 4, iclass 3, count 2 2006.173.02:06:50.76#ibcon#about to read 5, iclass 3, count 2 2006.173.02:06:50.76#ibcon#read 5, iclass 3, count 2 2006.173.02:06:50.76#ibcon#about to read 6, iclass 3, count 2 2006.173.02:06:50.76#ibcon#read 6, iclass 3, count 2 2006.173.02:06:50.76#ibcon#end of sib2, iclass 3, count 2 2006.173.02:06:50.76#ibcon#*mode == 0, iclass 3, count 2 2006.173.02:06:50.76#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.02:06:50.76#ibcon#[25=AT07-04\r\n] 2006.173.02:06:50.76#ibcon#*before write, iclass 3, count 2 2006.173.02:06:50.76#ibcon#enter sib2, iclass 3, count 2 2006.173.02:06:50.76#ibcon#flushed, iclass 3, count 2 2006.173.02:06:50.76#ibcon#about to write, iclass 3, count 2 2006.173.02:06:50.76#ibcon#wrote, iclass 3, count 2 2006.173.02:06:50.76#ibcon#about to read 3, iclass 3, count 2 2006.173.02:06:50.79#ibcon#read 3, iclass 3, count 2 2006.173.02:06:50.79#ibcon#about to read 4, iclass 3, count 2 2006.173.02:06:50.79#ibcon#read 4, iclass 3, count 2 2006.173.02:06:50.79#ibcon#about to read 5, iclass 3, count 2 2006.173.02:06:50.79#ibcon#read 5, iclass 3, count 2 2006.173.02:06:50.79#ibcon#about to read 6, iclass 3, count 2 2006.173.02:06:50.79#ibcon#read 6, iclass 3, count 2 2006.173.02:06:50.79#ibcon#end of sib2, iclass 3, count 2 2006.173.02:06:50.79#ibcon#*after write, iclass 3, count 2 2006.173.02:06:50.79#ibcon#*before return 0, iclass 3, count 2 2006.173.02:06:50.79#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.02:06:50.79#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.02:06:50.79#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.02:06:50.79#ibcon#ireg 7 cls_cnt 0 2006.173.02:06:50.79#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.02:06:50.91#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.02:06:50.91#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.02:06:50.91#ibcon#enter wrdev, iclass 3, count 0 2006.173.02:06:50.91#ibcon#first serial, iclass 3, count 0 2006.173.02:06:50.91#ibcon#enter sib2, iclass 3, count 0 2006.173.02:06:50.91#ibcon#flushed, iclass 3, count 0 2006.173.02:06:50.91#ibcon#about to write, iclass 3, count 0 2006.173.02:06:50.91#ibcon#wrote, iclass 3, count 0 2006.173.02:06:50.91#ibcon#about to read 3, iclass 3, count 0 2006.173.02:06:50.93#ibcon#read 3, iclass 3, count 0 2006.173.02:06:50.93#ibcon#about to read 4, iclass 3, count 0 2006.173.02:06:50.93#ibcon#read 4, iclass 3, count 0 2006.173.02:06:50.93#ibcon#about to read 5, iclass 3, count 0 2006.173.02:06:50.93#ibcon#read 5, iclass 3, count 0 2006.173.02:06:50.93#ibcon#about to read 6, iclass 3, count 0 2006.173.02:06:50.93#ibcon#read 6, iclass 3, count 0 2006.173.02:06:50.93#ibcon#end of sib2, iclass 3, count 0 2006.173.02:06:50.93#ibcon#*mode == 0, iclass 3, count 0 2006.173.02:06:50.93#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.02:06:50.93#ibcon#[25=USB\r\n] 2006.173.02:06:50.93#ibcon#*before write, iclass 3, count 0 2006.173.02:06:50.93#ibcon#enter sib2, iclass 3, count 0 2006.173.02:06:50.93#ibcon#flushed, iclass 3, count 0 2006.173.02:06:50.93#ibcon#about to write, iclass 3, count 0 2006.173.02:06:50.93#ibcon#wrote, iclass 3, count 0 2006.173.02:06:50.93#ibcon#about to read 3, iclass 3, count 0 2006.173.02:06:50.96#ibcon#read 3, iclass 3, count 0 2006.173.02:06:50.96#ibcon#about to read 4, iclass 3, count 0 2006.173.02:06:50.96#ibcon#read 4, iclass 3, count 0 2006.173.02:06:50.96#ibcon#about to read 5, iclass 3, count 0 2006.173.02:06:50.96#ibcon#read 5, iclass 3, count 0 2006.173.02:06:50.96#ibcon#about to read 6, iclass 3, count 0 2006.173.02:06:50.96#ibcon#read 6, iclass 3, count 0 2006.173.02:06:50.96#ibcon#end of sib2, iclass 3, count 0 2006.173.02:06:50.96#ibcon#*after write, iclass 3, count 0 2006.173.02:06:50.96#ibcon#*before return 0, iclass 3, count 0 2006.173.02:06:50.96#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.02:06:50.96#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.02:06:50.96#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.02:06:50.96#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.02:06:50.97$vck44/valo=8,884.99 2006.173.02:06:50.97#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.02:06:50.97#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.02:06:50.97#ibcon#ireg 17 cls_cnt 0 2006.173.02:06:50.97#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.02:06:50.97#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.02:06:50.97#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.02:06:50.97#ibcon#enter wrdev, iclass 5, count 0 2006.173.02:06:50.97#ibcon#first serial, iclass 5, count 0 2006.173.02:06:50.97#ibcon#enter sib2, iclass 5, count 0 2006.173.02:06:50.97#ibcon#flushed, iclass 5, count 0 2006.173.02:06:50.97#ibcon#about to write, iclass 5, count 0 2006.173.02:06:50.97#ibcon#wrote, iclass 5, count 0 2006.173.02:06:50.97#ibcon#about to read 3, iclass 5, count 0 2006.173.02:06:50.98#ibcon#read 3, iclass 5, count 0 2006.173.02:06:50.98#ibcon#about to read 4, iclass 5, count 0 2006.173.02:06:50.98#ibcon#read 4, iclass 5, count 0 2006.173.02:06:50.98#ibcon#about to read 5, iclass 5, count 0 2006.173.02:06:50.98#ibcon#read 5, iclass 5, count 0 2006.173.02:06:50.98#ibcon#about to read 6, iclass 5, count 0 2006.173.02:06:50.98#ibcon#read 6, iclass 5, count 0 2006.173.02:06:50.98#ibcon#end of sib2, iclass 5, count 0 2006.173.02:06:50.98#ibcon#*mode == 0, iclass 5, count 0 2006.173.02:06:50.98#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.02:06:50.98#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.02:06:50.98#ibcon#*before write, iclass 5, count 0 2006.173.02:06:50.98#ibcon#enter sib2, iclass 5, count 0 2006.173.02:06:50.98#ibcon#flushed, iclass 5, count 0 2006.173.02:06:50.98#ibcon#about to write, iclass 5, count 0 2006.173.02:06:50.98#ibcon#wrote, iclass 5, count 0 2006.173.02:06:50.98#ibcon#about to read 3, iclass 5, count 0 2006.173.02:06:51.03#ibcon#read 3, iclass 5, count 0 2006.173.02:06:51.03#ibcon#about to read 4, iclass 5, count 0 2006.173.02:06:51.03#ibcon#read 4, iclass 5, count 0 2006.173.02:06:51.03#ibcon#about to read 5, iclass 5, count 0 2006.173.02:06:51.03#ibcon#read 5, iclass 5, count 0 2006.173.02:06:51.03#ibcon#about to read 6, iclass 5, count 0 2006.173.02:06:51.03#ibcon#read 6, iclass 5, count 0 2006.173.02:06:51.03#ibcon#end of sib2, iclass 5, count 0 2006.173.02:06:51.03#ibcon#*after write, iclass 5, count 0 2006.173.02:06:51.03#ibcon#*before return 0, iclass 5, count 0 2006.173.02:06:51.03#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.02:06:51.03#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.02:06:51.03#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.02:06:51.03#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.02:06:51.03$vck44/va=8,4 2006.173.02:06:51.03#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.173.02:06:51.03#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.173.02:06:51.03#ibcon#ireg 11 cls_cnt 2 2006.173.02:06:51.03#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.02:06:51.07#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.02:06:51.07#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.02:06:51.07#ibcon#enter wrdev, iclass 7, count 2 2006.173.02:06:51.07#ibcon#first serial, iclass 7, count 2 2006.173.02:06:51.07#ibcon#enter sib2, iclass 7, count 2 2006.173.02:06:51.07#ibcon#flushed, iclass 7, count 2 2006.173.02:06:51.07#ibcon#about to write, iclass 7, count 2 2006.173.02:06:51.07#ibcon#wrote, iclass 7, count 2 2006.173.02:06:51.07#ibcon#about to read 3, iclass 7, count 2 2006.173.02:06:51.09#ibcon#read 3, iclass 7, count 2 2006.173.02:06:51.09#ibcon#about to read 4, iclass 7, count 2 2006.173.02:06:51.09#ibcon#read 4, iclass 7, count 2 2006.173.02:06:51.09#ibcon#about to read 5, iclass 7, count 2 2006.173.02:06:51.09#ibcon#read 5, iclass 7, count 2 2006.173.02:06:51.09#ibcon#about to read 6, iclass 7, count 2 2006.173.02:06:51.09#ibcon#read 6, iclass 7, count 2 2006.173.02:06:51.09#ibcon#end of sib2, iclass 7, count 2 2006.173.02:06:51.09#ibcon#*mode == 0, iclass 7, count 2 2006.173.02:06:51.09#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.173.02:06:51.09#ibcon#[25=AT08-04\r\n] 2006.173.02:06:51.09#ibcon#*before write, iclass 7, count 2 2006.173.02:06:51.09#ibcon#enter sib2, iclass 7, count 2 2006.173.02:06:51.09#ibcon#flushed, iclass 7, count 2 2006.173.02:06:51.09#ibcon#about to write, iclass 7, count 2 2006.173.02:06:51.09#ibcon#wrote, iclass 7, count 2 2006.173.02:06:51.09#ibcon#about to read 3, iclass 7, count 2 2006.173.02:06:51.12#ibcon#read 3, iclass 7, count 2 2006.173.02:06:51.12#ibcon#about to read 4, iclass 7, count 2 2006.173.02:06:51.12#ibcon#read 4, iclass 7, count 2 2006.173.02:06:51.12#ibcon#about to read 5, iclass 7, count 2 2006.173.02:06:51.12#ibcon#read 5, iclass 7, count 2 2006.173.02:06:51.12#ibcon#about to read 6, iclass 7, count 2 2006.173.02:06:51.12#ibcon#read 6, iclass 7, count 2 2006.173.02:06:51.12#ibcon#end of sib2, iclass 7, count 2 2006.173.02:06:51.12#ibcon#*after write, iclass 7, count 2 2006.173.02:06:51.12#ibcon#*before return 0, iclass 7, count 2 2006.173.02:06:51.12#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.02:06:51.12#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.173.02:06:51.12#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.173.02:06:51.12#ibcon#ireg 7 cls_cnt 0 2006.173.02:06:51.12#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.02:06:51.24#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.02:06:51.24#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.02:06:51.24#ibcon#enter wrdev, iclass 7, count 0 2006.173.02:06:51.24#ibcon#first serial, iclass 7, count 0 2006.173.02:06:51.24#ibcon#enter sib2, iclass 7, count 0 2006.173.02:06:51.24#ibcon#flushed, iclass 7, count 0 2006.173.02:06:51.24#ibcon#about to write, iclass 7, count 0 2006.173.02:06:51.24#ibcon#wrote, iclass 7, count 0 2006.173.02:06:51.24#ibcon#about to read 3, iclass 7, count 0 2006.173.02:06:51.26#ibcon#read 3, iclass 7, count 0 2006.173.02:06:51.26#ibcon#about to read 4, iclass 7, count 0 2006.173.02:06:51.26#ibcon#read 4, iclass 7, count 0 2006.173.02:06:51.26#ibcon#about to read 5, iclass 7, count 0 2006.173.02:06:51.26#ibcon#read 5, iclass 7, count 0 2006.173.02:06:51.26#ibcon#about to read 6, iclass 7, count 0 2006.173.02:06:51.26#ibcon#read 6, iclass 7, count 0 2006.173.02:06:51.26#ibcon#end of sib2, iclass 7, count 0 2006.173.02:06:51.26#ibcon#*mode == 0, iclass 7, count 0 2006.173.02:06:51.26#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.02:06:51.26#ibcon#[25=USB\r\n] 2006.173.02:06:51.26#ibcon#*before write, iclass 7, count 0 2006.173.02:06:51.26#ibcon#enter sib2, iclass 7, count 0 2006.173.02:06:51.26#ibcon#flushed, iclass 7, count 0 2006.173.02:06:51.26#ibcon#about to write, iclass 7, count 0 2006.173.02:06:51.26#ibcon#wrote, iclass 7, count 0 2006.173.02:06:51.26#ibcon#about to read 3, iclass 7, count 0 2006.173.02:06:51.29#ibcon#read 3, iclass 7, count 0 2006.173.02:06:51.29#ibcon#about to read 4, iclass 7, count 0 2006.173.02:06:51.29#ibcon#read 4, iclass 7, count 0 2006.173.02:06:51.29#ibcon#about to read 5, iclass 7, count 0 2006.173.02:06:51.29#ibcon#read 5, iclass 7, count 0 2006.173.02:06:51.29#ibcon#about to read 6, iclass 7, count 0 2006.173.02:06:51.29#ibcon#read 6, iclass 7, count 0 2006.173.02:06:51.29#ibcon#end of sib2, iclass 7, count 0 2006.173.02:06:51.29#ibcon#*after write, iclass 7, count 0 2006.173.02:06:51.29#ibcon#*before return 0, iclass 7, count 0 2006.173.02:06:51.29#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.02:06:51.29#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.173.02:06:51.29#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.02:06:51.29#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.02:06:51.30$vck44/vblo=1,629.99 2006.173.02:06:51.30#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.02:06:51.30#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.02:06:51.30#ibcon#ireg 17 cls_cnt 0 2006.173.02:06:51.30#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.02:06:51.30#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.02:06:51.30#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.02:06:51.30#ibcon#enter wrdev, iclass 11, count 0 2006.173.02:06:51.30#ibcon#first serial, iclass 11, count 0 2006.173.02:06:51.30#ibcon#enter sib2, iclass 11, count 0 2006.173.02:06:51.30#ibcon#flushed, iclass 11, count 0 2006.173.02:06:51.30#ibcon#about to write, iclass 11, count 0 2006.173.02:06:51.30#ibcon#wrote, iclass 11, count 0 2006.173.02:06:51.30#ibcon#about to read 3, iclass 11, count 0 2006.173.02:06:51.31#ibcon#read 3, iclass 11, count 0 2006.173.02:06:51.31#ibcon#about to read 4, iclass 11, count 0 2006.173.02:06:51.31#ibcon#read 4, iclass 11, count 0 2006.173.02:06:51.31#ibcon#about to read 5, iclass 11, count 0 2006.173.02:06:51.31#ibcon#read 5, iclass 11, count 0 2006.173.02:06:51.31#ibcon#about to read 6, iclass 11, count 0 2006.173.02:06:51.31#ibcon#read 6, iclass 11, count 0 2006.173.02:06:51.31#ibcon#end of sib2, iclass 11, count 0 2006.173.02:06:51.31#ibcon#*mode == 0, iclass 11, count 0 2006.173.02:06:51.31#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.02:06:51.31#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.02:06:51.31#ibcon#*before write, iclass 11, count 0 2006.173.02:06:51.31#ibcon#enter sib2, iclass 11, count 0 2006.173.02:06:51.31#ibcon#flushed, iclass 11, count 0 2006.173.02:06:51.31#ibcon#about to write, iclass 11, count 0 2006.173.02:06:51.31#ibcon#wrote, iclass 11, count 0 2006.173.02:06:51.31#ibcon#about to read 3, iclass 11, count 0 2006.173.02:06:51.35#ibcon#read 3, iclass 11, count 0 2006.173.02:06:51.35#ibcon#about to read 4, iclass 11, count 0 2006.173.02:06:51.35#ibcon#read 4, iclass 11, count 0 2006.173.02:06:51.35#ibcon#about to read 5, iclass 11, count 0 2006.173.02:06:51.35#ibcon#read 5, iclass 11, count 0 2006.173.02:06:51.35#ibcon#about to read 6, iclass 11, count 0 2006.173.02:06:51.35#ibcon#read 6, iclass 11, count 0 2006.173.02:06:51.35#ibcon#end of sib2, iclass 11, count 0 2006.173.02:06:51.35#ibcon#*after write, iclass 11, count 0 2006.173.02:06:51.35#ibcon#*before return 0, iclass 11, count 0 2006.173.02:06:51.35#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.02:06:51.35#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.02:06:51.35#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.02:06:51.35#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.02:06:51.36$vck44/vb=1,4 2006.173.02:06:51.36#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.173.02:06:51.36#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.173.02:06:51.36#ibcon#ireg 11 cls_cnt 2 2006.173.02:06:51.36#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.02:06:51.36#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.02:06:51.36#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.02:06:51.36#ibcon#enter wrdev, iclass 13, count 2 2006.173.02:06:51.36#ibcon#first serial, iclass 13, count 2 2006.173.02:06:51.36#ibcon#enter sib2, iclass 13, count 2 2006.173.02:06:51.36#ibcon#flushed, iclass 13, count 2 2006.173.02:06:51.36#ibcon#about to write, iclass 13, count 2 2006.173.02:06:51.36#ibcon#wrote, iclass 13, count 2 2006.173.02:06:51.36#ibcon#about to read 3, iclass 13, count 2 2006.173.02:06:51.37#ibcon#read 3, iclass 13, count 2 2006.173.02:06:51.37#ibcon#about to read 4, iclass 13, count 2 2006.173.02:06:51.37#ibcon#read 4, iclass 13, count 2 2006.173.02:06:51.37#ibcon#about to read 5, iclass 13, count 2 2006.173.02:06:51.37#ibcon#read 5, iclass 13, count 2 2006.173.02:06:51.37#ibcon#about to read 6, iclass 13, count 2 2006.173.02:06:51.37#ibcon#read 6, iclass 13, count 2 2006.173.02:06:51.37#ibcon#end of sib2, iclass 13, count 2 2006.173.02:06:51.37#ibcon#*mode == 0, iclass 13, count 2 2006.173.02:06:51.37#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.173.02:06:51.37#ibcon#[27=AT01-04\r\n] 2006.173.02:06:51.37#ibcon#*before write, iclass 13, count 2 2006.173.02:06:51.37#ibcon#enter sib2, iclass 13, count 2 2006.173.02:06:51.37#ibcon#flushed, iclass 13, count 2 2006.173.02:06:51.37#ibcon#about to write, iclass 13, count 2 2006.173.02:06:51.37#ibcon#wrote, iclass 13, count 2 2006.173.02:06:51.37#ibcon#about to read 3, iclass 13, count 2 2006.173.02:06:51.40#ibcon#read 3, iclass 13, count 2 2006.173.02:06:51.40#ibcon#about to read 4, iclass 13, count 2 2006.173.02:06:51.40#ibcon#read 4, iclass 13, count 2 2006.173.02:06:51.40#ibcon#about to read 5, iclass 13, count 2 2006.173.02:06:51.40#ibcon#read 5, iclass 13, count 2 2006.173.02:06:51.40#ibcon#about to read 6, iclass 13, count 2 2006.173.02:06:51.40#ibcon#read 6, iclass 13, count 2 2006.173.02:06:51.40#ibcon#end of sib2, iclass 13, count 2 2006.173.02:06:51.40#ibcon#*after write, iclass 13, count 2 2006.173.02:06:51.40#ibcon#*before return 0, iclass 13, count 2 2006.173.02:06:51.40#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.02:06:51.40#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.173.02:06:51.40#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.173.02:06:51.40#ibcon#ireg 7 cls_cnt 0 2006.173.02:06:51.40#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.02:06:51.52#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.02:06:51.52#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.02:06:51.52#ibcon#enter wrdev, iclass 13, count 0 2006.173.02:06:51.52#ibcon#first serial, iclass 13, count 0 2006.173.02:06:51.52#ibcon#enter sib2, iclass 13, count 0 2006.173.02:06:51.52#ibcon#flushed, iclass 13, count 0 2006.173.02:06:51.52#ibcon#about to write, iclass 13, count 0 2006.173.02:06:51.52#ibcon#wrote, iclass 13, count 0 2006.173.02:06:51.52#ibcon#about to read 3, iclass 13, count 0 2006.173.02:06:51.54#ibcon#read 3, iclass 13, count 0 2006.173.02:06:51.54#ibcon#about to read 4, iclass 13, count 0 2006.173.02:06:51.54#ibcon#read 4, iclass 13, count 0 2006.173.02:06:51.54#ibcon#about to read 5, iclass 13, count 0 2006.173.02:06:51.54#ibcon#read 5, iclass 13, count 0 2006.173.02:06:51.54#ibcon#about to read 6, iclass 13, count 0 2006.173.02:06:51.54#ibcon#read 6, iclass 13, count 0 2006.173.02:06:51.54#ibcon#end of sib2, iclass 13, count 0 2006.173.02:06:51.54#ibcon#*mode == 0, iclass 13, count 0 2006.173.02:06:51.54#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.02:06:51.54#ibcon#[27=USB\r\n] 2006.173.02:06:51.54#ibcon#*before write, iclass 13, count 0 2006.173.02:06:51.54#ibcon#enter sib2, iclass 13, count 0 2006.173.02:06:51.54#ibcon#flushed, iclass 13, count 0 2006.173.02:06:51.54#ibcon#about to write, iclass 13, count 0 2006.173.02:06:51.54#ibcon#wrote, iclass 13, count 0 2006.173.02:06:51.54#ibcon#about to read 3, iclass 13, count 0 2006.173.02:06:51.57#ibcon#read 3, iclass 13, count 0 2006.173.02:06:51.57#ibcon#about to read 4, iclass 13, count 0 2006.173.02:06:51.57#ibcon#read 4, iclass 13, count 0 2006.173.02:06:51.57#ibcon#about to read 5, iclass 13, count 0 2006.173.02:06:51.57#ibcon#read 5, iclass 13, count 0 2006.173.02:06:51.57#ibcon#about to read 6, iclass 13, count 0 2006.173.02:06:51.57#ibcon#read 6, iclass 13, count 0 2006.173.02:06:51.57#ibcon#end of sib2, iclass 13, count 0 2006.173.02:06:51.57#ibcon#*after write, iclass 13, count 0 2006.173.02:06:51.57#ibcon#*before return 0, iclass 13, count 0 2006.173.02:06:51.57#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.02:06:51.57#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.173.02:06:51.57#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.02:06:51.57#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.02:06:51.58$vck44/vblo=2,634.99 2006.173.02:06:51.58#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.02:06:51.58#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.02:06:51.58#ibcon#ireg 17 cls_cnt 0 2006.173.02:06:51.58#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.02:06:51.58#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.02:06:51.58#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.02:06:51.58#ibcon#enter wrdev, iclass 15, count 0 2006.173.02:06:51.58#ibcon#first serial, iclass 15, count 0 2006.173.02:06:51.58#ibcon#enter sib2, iclass 15, count 0 2006.173.02:06:51.58#ibcon#flushed, iclass 15, count 0 2006.173.02:06:51.58#ibcon#about to write, iclass 15, count 0 2006.173.02:06:51.58#ibcon#wrote, iclass 15, count 0 2006.173.02:06:51.58#ibcon#about to read 3, iclass 15, count 0 2006.173.02:06:51.59#ibcon#read 3, iclass 15, count 0 2006.173.02:06:51.59#ibcon#about to read 4, iclass 15, count 0 2006.173.02:06:51.59#ibcon#read 4, iclass 15, count 0 2006.173.02:06:51.59#ibcon#about to read 5, iclass 15, count 0 2006.173.02:06:51.59#ibcon#read 5, iclass 15, count 0 2006.173.02:06:51.59#ibcon#about to read 6, iclass 15, count 0 2006.173.02:06:51.59#ibcon#read 6, iclass 15, count 0 2006.173.02:06:51.59#ibcon#end of sib2, iclass 15, count 0 2006.173.02:06:51.59#ibcon#*mode == 0, iclass 15, count 0 2006.173.02:06:51.59#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.02:06:51.59#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.02:06:51.59#ibcon#*before write, iclass 15, count 0 2006.173.02:06:51.59#ibcon#enter sib2, iclass 15, count 0 2006.173.02:06:51.59#ibcon#flushed, iclass 15, count 0 2006.173.02:06:51.59#ibcon#about to write, iclass 15, count 0 2006.173.02:06:51.59#ibcon#wrote, iclass 15, count 0 2006.173.02:06:51.59#ibcon#about to read 3, iclass 15, count 0 2006.173.02:06:51.63#ibcon#read 3, iclass 15, count 0 2006.173.02:06:51.63#ibcon#about to read 4, iclass 15, count 0 2006.173.02:06:51.63#ibcon#read 4, iclass 15, count 0 2006.173.02:06:51.63#ibcon#about to read 5, iclass 15, count 0 2006.173.02:06:51.63#ibcon#read 5, iclass 15, count 0 2006.173.02:06:51.63#ibcon#about to read 6, iclass 15, count 0 2006.173.02:06:51.63#ibcon#read 6, iclass 15, count 0 2006.173.02:06:51.63#ibcon#end of sib2, iclass 15, count 0 2006.173.02:06:51.63#ibcon#*after write, iclass 15, count 0 2006.173.02:06:51.63#ibcon#*before return 0, iclass 15, count 0 2006.173.02:06:51.63#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.02:06:51.63#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.02:06:51.63#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.02:06:51.63#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.02:06:51.64$vck44/vb=2,4 2006.173.02:06:51.64#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.02:06:51.64#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.02:06:51.64#ibcon#ireg 11 cls_cnt 2 2006.173.02:06:51.64#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.02:06:51.68#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.02:06:51.68#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.02:06:51.68#ibcon#enter wrdev, iclass 17, count 2 2006.173.02:06:51.68#ibcon#first serial, iclass 17, count 2 2006.173.02:06:51.68#ibcon#enter sib2, iclass 17, count 2 2006.173.02:06:51.68#ibcon#flushed, iclass 17, count 2 2006.173.02:06:51.68#ibcon#about to write, iclass 17, count 2 2006.173.02:06:51.68#ibcon#wrote, iclass 17, count 2 2006.173.02:06:51.68#ibcon#about to read 3, iclass 17, count 2 2006.173.02:06:51.70#ibcon#read 3, iclass 17, count 2 2006.173.02:06:51.70#ibcon#about to read 4, iclass 17, count 2 2006.173.02:06:51.70#ibcon#read 4, iclass 17, count 2 2006.173.02:06:51.70#ibcon#about to read 5, iclass 17, count 2 2006.173.02:06:51.70#ibcon#read 5, iclass 17, count 2 2006.173.02:06:51.70#ibcon#about to read 6, iclass 17, count 2 2006.173.02:06:51.70#ibcon#read 6, iclass 17, count 2 2006.173.02:06:51.70#ibcon#end of sib2, iclass 17, count 2 2006.173.02:06:51.70#ibcon#*mode == 0, iclass 17, count 2 2006.173.02:06:51.70#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.02:06:51.70#ibcon#[27=AT02-04\r\n] 2006.173.02:06:51.70#ibcon#*before write, iclass 17, count 2 2006.173.02:06:51.70#ibcon#enter sib2, iclass 17, count 2 2006.173.02:06:51.70#ibcon#flushed, iclass 17, count 2 2006.173.02:06:51.70#ibcon#about to write, iclass 17, count 2 2006.173.02:06:51.70#ibcon#wrote, iclass 17, count 2 2006.173.02:06:51.70#ibcon#about to read 3, iclass 17, count 2 2006.173.02:06:51.73#ibcon#read 3, iclass 17, count 2 2006.173.02:06:51.73#ibcon#about to read 4, iclass 17, count 2 2006.173.02:06:51.73#ibcon#read 4, iclass 17, count 2 2006.173.02:06:51.73#ibcon#about to read 5, iclass 17, count 2 2006.173.02:06:51.73#ibcon#read 5, iclass 17, count 2 2006.173.02:06:51.73#ibcon#about to read 6, iclass 17, count 2 2006.173.02:06:51.73#ibcon#read 6, iclass 17, count 2 2006.173.02:06:51.73#ibcon#end of sib2, iclass 17, count 2 2006.173.02:06:51.73#ibcon#*after write, iclass 17, count 2 2006.173.02:06:51.73#ibcon#*before return 0, iclass 17, count 2 2006.173.02:06:51.73#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.02:06:51.73#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.02:06:51.73#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.02:06:51.73#ibcon#ireg 7 cls_cnt 0 2006.173.02:06:51.73#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.02:06:51.85#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.02:06:51.85#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.02:06:51.85#ibcon#enter wrdev, iclass 17, count 0 2006.173.02:06:51.85#ibcon#first serial, iclass 17, count 0 2006.173.02:06:51.85#ibcon#enter sib2, iclass 17, count 0 2006.173.02:06:51.85#ibcon#flushed, iclass 17, count 0 2006.173.02:06:51.85#ibcon#about to write, iclass 17, count 0 2006.173.02:06:51.85#ibcon#wrote, iclass 17, count 0 2006.173.02:06:51.85#ibcon#about to read 3, iclass 17, count 0 2006.173.02:06:51.87#ibcon#read 3, iclass 17, count 0 2006.173.02:06:51.87#ibcon#about to read 4, iclass 17, count 0 2006.173.02:06:51.87#ibcon#read 4, iclass 17, count 0 2006.173.02:06:51.87#ibcon#about to read 5, iclass 17, count 0 2006.173.02:06:51.87#ibcon#read 5, iclass 17, count 0 2006.173.02:06:51.87#ibcon#about to read 6, iclass 17, count 0 2006.173.02:06:51.87#ibcon#read 6, iclass 17, count 0 2006.173.02:06:51.87#ibcon#end of sib2, iclass 17, count 0 2006.173.02:06:51.87#ibcon#*mode == 0, iclass 17, count 0 2006.173.02:06:51.87#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.02:06:51.87#ibcon#[27=USB\r\n] 2006.173.02:06:51.87#ibcon#*before write, iclass 17, count 0 2006.173.02:06:51.87#ibcon#enter sib2, iclass 17, count 0 2006.173.02:06:51.87#ibcon#flushed, iclass 17, count 0 2006.173.02:06:51.87#ibcon#about to write, iclass 17, count 0 2006.173.02:06:51.87#ibcon#wrote, iclass 17, count 0 2006.173.02:06:51.87#ibcon#about to read 3, iclass 17, count 0 2006.173.02:06:51.90#ibcon#read 3, iclass 17, count 0 2006.173.02:06:51.90#ibcon#about to read 4, iclass 17, count 0 2006.173.02:06:51.90#ibcon#read 4, iclass 17, count 0 2006.173.02:06:51.90#ibcon#about to read 5, iclass 17, count 0 2006.173.02:06:51.90#ibcon#read 5, iclass 17, count 0 2006.173.02:06:51.90#ibcon#about to read 6, iclass 17, count 0 2006.173.02:06:51.90#ibcon#read 6, iclass 17, count 0 2006.173.02:06:51.90#ibcon#end of sib2, iclass 17, count 0 2006.173.02:06:51.90#ibcon#*after write, iclass 17, count 0 2006.173.02:06:51.90#ibcon#*before return 0, iclass 17, count 0 2006.173.02:06:51.90#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.02:06:51.90#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.02:06:51.90#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.02:06:51.90#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.02:06:51.91$vck44/vblo=3,649.99 2006.173.02:06:51.91#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.02:06:51.91#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.02:06:51.91#ibcon#ireg 17 cls_cnt 0 2006.173.02:06:51.91#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.02:06:51.91#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.02:06:51.91#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.02:06:51.91#ibcon#enter wrdev, iclass 19, count 0 2006.173.02:06:51.91#ibcon#first serial, iclass 19, count 0 2006.173.02:06:51.91#ibcon#enter sib2, iclass 19, count 0 2006.173.02:06:51.91#ibcon#flushed, iclass 19, count 0 2006.173.02:06:51.91#ibcon#about to write, iclass 19, count 0 2006.173.02:06:51.91#ibcon#wrote, iclass 19, count 0 2006.173.02:06:51.91#ibcon#about to read 3, iclass 19, count 0 2006.173.02:06:51.92#ibcon#read 3, iclass 19, count 0 2006.173.02:06:51.92#ibcon#about to read 4, iclass 19, count 0 2006.173.02:06:51.92#ibcon#read 4, iclass 19, count 0 2006.173.02:06:51.92#ibcon#about to read 5, iclass 19, count 0 2006.173.02:06:51.92#ibcon#read 5, iclass 19, count 0 2006.173.02:06:51.92#ibcon#about to read 6, iclass 19, count 0 2006.173.02:06:51.92#ibcon#read 6, iclass 19, count 0 2006.173.02:06:51.92#ibcon#end of sib2, iclass 19, count 0 2006.173.02:06:51.92#ibcon#*mode == 0, iclass 19, count 0 2006.173.02:06:51.92#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.02:06:51.92#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.02:06:51.92#ibcon#*before write, iclass 19, count 0 2006.173.02:06:51.92#ibcon#enter sib2, iclass 19, count 0 2006.173.02:06:51.92#ibcon#flushed, iclass 19, count 0 2006.173.02:06:51.92#ibcon#about to write, iclass 19, count 0 2006.173.02:06:51.92#ibcon#wrote, iclass 19, count 0 2006.173.02:06:51.92#ibcon#about to read 3, iclass 19, count 0 2006.173.02:06:51.96#ibcon#read 3, iclass 19, count 0 2006.173.02:06:51.96#ibcon#about to read 4, iclass 19, count 0 2006.173.02:06:51.96#ibcon#read 4, iclass 19, count 0 2006.173.02:06:51.96#ibcon#about to read 5, iclass 19, count 0 2006.173.02:06:51.96#ibcon#read 5, iclass 19, count 0 2006.173.02:06:51.96#ibcon#about to read 6, iclass 19, count 0 2006.173.02:06:51.96#ibcon#read 6, iclass 19, count 0 2006.173.02:06:51.96#ibcon#end of sib2, iclass 19, count 0 2006.173.02:06:51.96#ibcon#*after write, iclass 19, count 0 2006.173.02:06:51.96#ibcon#*before return 0, iclass 19, count 0 2006.173.02:06:51.96#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.02:06:51.96#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.02:06:51.96#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.02:06:51.96#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.02:06:51.97$vck44/vb=3,4 2006.173.02:06:51.97#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.02:06:51.97#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.02:06:51.97#ibcon#ireg 11 cls_cnt 2 2006.173.02:06:51.97#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.02:06:52.02#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.02:06:52.02#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.02:06:52.02#ibcon#enter wrdev, iclass 21, count 2 2006.173.02:06:52.02#ibcon#first serial, iclass 21, count 2 2006.173.02:06:52.02#ibcon#enter sib2, iclass 21, count 2 2006.173.02:06:52.02#ibcon#flushed, iclass 21, count 2 2006.173.02:06:52.02#ibcon#about to write, iclass 21, count 2 2006.173.02:06:52.02#ibcon#wrote, iclass 21, count 2 2006.173.02:06:52.02#ibcon#about to read 3, iclass 21, count 2 2006.173.02:06:52.03#ibcon#read 3, iclass 21, count 2 2006.173.02:06:52.03#ibcon#about to read 4, iclass 21, count 2 2006.173.02:06:52.03#ibcon#read 4, iclass 21, count 2 2006.173.02:06:52.03#ibcon#about to read 5, iclass 21, count 2 2006.173.02:06:52.03#ibcon#read 5, iclass 21, count 2 2006.173.02:06:52.03#ibcon#about to read 6, iclass 21, count 2 2006.173.02:06:52.03#ibcon#read 6, iclass 21, count 2 2006.173.02:06:52.03#ibcon#end of sib2, iclass 21, count 2 2006.173.02:06:52.03#ibcon#*mode == 0, iclass 21, count 2 2006.173.02:06:52.03#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.02:06:52.03#ibcon#[27=AT03-04\r\n] 2006.173.02:06:52.03#ibcon#*before write, iclass 21, count 2 2006.173.02:06:52.03#ibcon#enter sib2, iclass 21, count 2 2006.173.02:06:52.03#ibcon#flushed, iclass 21, count 2 2006.173.02:06:52.03#ibcon#about to write, iclass 21, count 2 2006.173.02:06:52.03#ibcon#wrote, iclass 21, count 2 2006.173.02:06:52.03#ibcon#about to read 3, iclass 21, count 2 2006.173.02:06:52.06#ibcon#read 3, iclass 21, count 2 2006.173.02:06:52.06#ibcon#about to read 4, iclass 21, count 2 2006.173.02:06:52.06#ibcon#read 4, iclass 21, count 2 2006.173.02:06:52.06#ibcon#about to read 5, iclass 21, count 2 2006.173.02:06:52.06#ibcon#read 5, iclass 21, count 2 2006.173.02:06:52.06#ibcon#about to read 6, iclass 21, count 2 2006.173.02:06:52.06#ibcon#read 6, iclass 21, count 2 2006.173.02:06:52.06#ibcon#end of sib2, iclass 21, count 2 2006.173.02:06:52.06#ibcon#*after write, iclass 21, count 2 2006.173.02:06:52.06#ibcon#*before return 0, iclass 21, count 2 2006.173.02:06:52.06#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.02:06:52.06#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.02:06:52.06#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.02:06:52.06#ibcon#ireg 7 cls_cnt 0 2006.173.02:06:52.06#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.02:06:52.18#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.02:06:52.18#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.02:06:52.18#ibcon#enter wrdev, iclass 21, count 0 2006.173.02:06:52.18#ibcon#first serial, iclass 21, count 0 2006.173.02:06:52.18#ibcon#enter sib2, iclass 21, count 0 2006.173.02:06:52.18#ibcon#flushed, iclass 21, count 0 2006.173.02:06:52.18#ibcon#about to write, iclass 21, count 0 2006.173.02:06:52.18#ibcon#wrote, iclass 21, count 0 2006.173.02:06:52.18#ibcon#about to read 3, iclass 21, count 0 2006.173.02:06:52.20#ibcon#read 3, iclass 21, count 0 2006.173.02:06:52.20#ibcon#about to read 4, iclass 21, count 0 2006.173.02:06:52.20#ibcon#read 4, iclass 21, count 0 2006.173.02:06:52.20#ibcon#about to read 5, iclass 21, count 0 2006.173.02:06:52.20#ibcon#read 5, iclass 21, count 0 2006.173.02:06:52.20#ibcon#about to read 6, iclass 21, count 0 2006.173.02:06:52.20#ibcon#read 6, iclass 21, count 0 2006.173.02:06:52.20#ibcon#end of sib2, iclass 21, count 0 2006.173.02:06:52.20#ibcon#*mode == 0, iclass 21, count 0 2006.173.02:06:52.20#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.02:06:52.20#ibcon#[27=USB\r\n] 2006.173.02:06:52.20#ibcon#*before write, iclass 21, count 0 2006.173.02:06:52.20#ibcon#enter sib2, iclass 21, count 0 2006.173.02:06:52.20#ibcon#flushed, iclass 21, count 0 2006.173.02:06:52.20#ibcon#about to write, iclass 21, count 0 2006.173.02:06:52.20#ibcon#wrote, iclass 21, count 0 2006.173.02:06:52.20#ibcon#about to read 3, iclass 21, count 0 2006.173.02:06:52.23#ibcon#read 3, iclass 21, count 0 2006.173.02:06:52.23#ibcon#about to read 4, iclass 21, count 0 2006.173.02:06:52.23#ibcon#read 4, iclass 21, count 0 2006.173.02:06:52.23#ibcon#about to read 5, iclass 21, count 0 2006.173.02:06:52.23#ibcon#read 5, iclass 21, count 0 2006.173.02:06:52.23#ibcon#about to read 6, iclass 21, count 0 2006.173.02:06:52.23#ibcon#read 6, iclass 21, count 0 2006.173.02:06:52.23#ibcon#end of sib2, iclass 21, count 0 2006.173.02:06:52.23#ibcon#*after write, iclass 21, count 0 2006.173.02:06:52.23#ibcon#*before return 0, iclass 21, count 0 2006.173.02:06:52.23#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.02:06:52.23#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.02:06:52.23#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.02:06:52.23#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.02:06:52.24$vck44/vblo=4,679.99 2006.173.02:06:52.24#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.02:06:52.24#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.02:06:52.24#ibcon#ireg 17 cls_cnt 0 2006.173.02:06:52.24#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.02:06:52.24#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.02:06:52.24#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.02:06:52.24#ibcon#enter wrdev, iclass 23, count 0 2006.173.02:06:52.24#ibcon#first serial, iclass 23, count 0 2006.173.02:06:52.24#ibcon#enter sib2, iclass 23, count 0 2006.173.02:06:52.24#ibcon#flushed, iclass 23, count 0 2006.173.02:06:52.24#ibcon#about to write, iclass 23, count 0 2006.173.02:06:52.24#ibcon#wrote, iclass 23, count 0 2006.173.02:06:52.24#ibcon#about to read 3, iclass 23, count 0 2006.173.02:06:52.25#ibcon#read 3, iclass 23, count 0 2006.173.02:06:52.25#ibcon#about to read 4, iclass 23, count 0 2006.173.02:06:52.25#ibcon#read 4, iclass 23, count 0 2006.173.02:06:52.25#ibcon#about to read 5, iclass 23, count 0 2006.173.02:06:52.25#ibcon#read 5, iclass 23, count 0 2006.173.02:06:52.25#ibcon#about to read 6, iclass 23, count 0 2006.173.02:06:52.25#ibcon#read 6, iclass 23, count 0 2006.173.02:06:52.25#ibcon#end of sib2, iclass 23, count 0 2006.173.02:06:52.25#ibcon#*mode == 0, iclass 23, count 0 2006.173.02:06:52.25#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.02:06:52.25#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.02:06:52.25#ibcon#*before write, iclass 23, count 0 2006.173.02:06:52.25#ibcon#enter sib2, iclass 23, count 0 2006.173.02:06:52.25#ibcon#flushed, iclass 23, count 0 2006.173.02:06:52.25#ibcon#about to write, iclass 23, count 0 2006.173.02:06:52.25#ibcon#wrote, iclass 23, count 0 2006.173.02:06:52.25#ibcon#about to read 3, iclass 23, count 0 2006.173.02:06:52.29#ibcon#read 3, iclass 23, count 0 2006.173.02:06:52.29#ibcon#about to read 4, iclass 23, count 0 2006.173.02:06:52.29#ibcon#read 4, iclass 23, count 0 2006.173.02:06:52.29#ibcon#about to read 5, iclass 23, count 0 2006.173.02:06:52.29#ibcon#read 5, iclass 23, count 0 2006.173.02:06:52.29#ibcon#about to read 6, iclass 23, count 0 2006.173.02:06:52.29#ibcon#read 6, iclass 23, count 0 2006.173.02:06:52.29#ibcon#end of sib2, iclass 23, count 0 2006.173.02:06:52.29#ibcon#*after write, iclass 23, count 0 2006.173.02:06:52.29#ibcon#*before return 0, iclass 23, count 0 2006.173.02:06:52.29#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.02:06:52.29#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.02:06:52.29#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.02:06:52.29#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.02:06:52.30$vck44/vb=4,4 2006.173.02:06:52.30#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.02:06:52.30#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.02:06:52.30#ibcon#ireg 11 cls_cnt 2 2006.173.02:06:52.30#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.02:06:52.34#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.02:06:52.34#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.02:06:52.34#ibcon#enter wrdev, iclass 25, count 2 2006.173.02:06:52.34#ibcon#first serial, iclass 25, count 2 2006.173.02:06:52.34#ibcon#enter sib2, iclass 25, count 2 2006.173.02:06:52.34#ibcon#flushed, iclass 25, count 2 2006.173.02:06:52.34#ibcon#about to write, iclass 25, count 2 2006.173.02:06:52.34#ibcon#wrote, iclass 25, count 2 2006.173.02:06:52.34#ibcon#about to read 3, iclass 25, count 2 2006.173.02:06:52.36#ibcon#read 3, iclass 25, count 2 2006.173.02:06:52.36#ibcon#about to read 4, iclass 25, count 2 2006.173.02:06:52.36#ibcon#read 4, iclass 25, count 2 2006.173.02:06:52.36#ibcon#about to read 5, iclass 25, count 2 2006.173.02:06:52.36#ibcon#read 5, iclass 25, count 2 2006.173.02:06:52.36#ibcon#about to read 6, iclass 25, count 2 2006.173.02:06:52.36#ibcon#read 6, iclass 25, count 2 2006.173.02:06:52.36#ibcon#end of sib2, iclass 25, count 2 2006.173.02:06:52.36#ibcon#*mode == 0, iclass 25, count 2 2006.173.02:06:52.36#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.02:06:52.36#ibcon#[27=AT04-04\r\n] 2006.173.02:06:52.36#ibcon#*before write, iclass 25, count 2 2006.173.02:06:52.36#ibcon#enter sib2, iclass 25, count 2 2006.173.02:06:52.36#ibcon#flushed, iclass 25, count 2 2006.173.02:06:52.36#ibcon#about to write, iclass 25, count 2 2006.173.02:06:52.36#ibcon#wrote, iclass 25, count 2 2006.173.02:06:52.36#ibcon#about to read 3, iclass 25, count 2 2006.173.02:06:52.39#ibcon#read 3, iclass 25, count 2 2006.173.02:06:52.39#ibcon#about to read 4, iclass 25, count 2 2006.173.02:06:52.39#ibcon#read 4, iclass 25, count 2 2006.173.02:06:52.39#ibcon#about to read 5, iclass 25, count 2 2006.173.02:06:52.39#ibcon#read 5, iclass 25, count 2 2006.173.02:06:52.39#ibcon#about to read 6, iclass 25, count 2 2006.173.02:06:52.39#ibcon#read 6, iclass 25, count 2 2006.173.02:06:52.39#ibcon#end of sib2, iclass 25, count 2 2006.173.02:06:52.39#ibcon#*after write, iclass 25, count 2 2006.173.02:06:52.39#ibcon#*before return 0, iclass 25, count 2 2006.173.02:06:52.39#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.02:06:52.39#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.02:06:52.39#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.02:06:52.39#ibcon#ireg 7 cls_cnt 0 2006.173.02:06:52.39#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.02:06:52.51#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.02:06:52.51#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.02:06:52.51#ibcon#enter wrdev, iclass 25, count 0 2006.173.02:06:52.51#ibcon#first serial, iclass 25, count 0 2006.173.02:06:52.51#ibcon#enter sib2, iclass 25, count 0 2006.173.02:06:52.51#ibcon#flushed, iclass 25, count 0 2006.173.02:06:52.51#ibcon#about to write, iclass 25, count 0 2006.173.02:06:52.51#ibcon#wrote, iclass 25, count 0 2006.173.02:06:52.51#ibcon#about to read 3, iclass 25, count 0 2006.173.02:06:52.53#ibcon#read 3, iclass 25, count 0 2006.173.02:06:52.53#ibcon#about to read 4, iclass 25, count 0 2006.173.02:06:52.53#ibcon#read 4, iclass 25, count 0 2006.173.02:06:52.53#ibcon#about to read 5, iclass 25, count 0 2006.173.02:06:52.53#ibcon#read 5, iclass 25, count 0 2006.173.02:06:52.53#ibcon#about to read 6, iclass 25, count 0 2006.173.02:06:52.53#ibcon#read 6, iclass 25, count 0 2006.173.02:06:52.53#ibcon#end of sib2, iclass 25, count 0 2006.173.02:06:52.53#ibcon#*mode == 0, iclass 25, count 0 2006.173.02:06:52.53#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.02:06:52.53#ibcon#[27=USB\r\n] 2006.173.02:06:52.53#ibcon#*before write, iclass 25, count 0 2006.173.02:06:52.53#ibcon#enter sib2, iclass 25, count 0 2006.173.02:06:52.53#ibcon#flushed, iclass 25, count 0 2006.173.02:06:52.53#ibcon#about to write, iclass 25, count 0 2006.173.02:06:52.53#ibcon#wrote, iclass 25, count 0 2006.173.02:06:52.53#ibcon#about to read 3, iclass 25, count 0 2006.173.02:06:52.56#ibcon#read 3, iclass 25, count 0 2006.173.02:06:52.56#ibcon#about to read 4, iclass 25, count 0 2006.173.02:06:52.56#ibcon#read 4, iclass 25, count 0 2006.173.02:06:52.56#ibcon#about to read 5, iclass 25, count 0 2006.173.02:06:52.56#ibcon#read 5, iclass 25, count 0 2006.173.02:06:52.56#ibcon#about to read 6, iclass 25, count 0 2006.173.02:06:52.56#ibcon#read 6, iclass 25, count 0 2006.173.02:06:52.56#ibcon#end of sib2, iclass 25, count 0 2006.173.02:06:52.56#ibcon#*after write, iclass 25, count 0 2006.173.02:06:52.56#ibcon#*before return 0, iclass 25, count 0 2006.173.02:06:52.56#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.02:06:52.56#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.02:06:52.56#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.02:06:52.56#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.02:06:52.57$vck44/vblo=5,709.99 2006.173.02:06:52.57#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.02:06:52.57#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.02:06:52.57#ibcon#ireg 17 cls_cnt 0 2006.173.02:06:52.57#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.02:06:52.57#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.02:06:52.57#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.02:06:52.57#ibcon#enter wrdev, iclass 27, count 0 2006.173.02:06:52.57#ibcon#first serial, iclass 27, count 0 2006.173.02:06:52.57#ibcon#enter sib2, iclass 27, count 0 2006.173.02:06:52.57#ibcon#flushed, iclass 27, count 0 2006.173.02:06:52.57#ibcon#about to write, iclass 27, count 0 2006.173.02:06:52.57#ibcon#wrote, iclass 27, count 0 2006.173.02:06:52.57#ibcon#about to read 3, iclass 27, count 0 2006.173.02:06:52.58#ibcon#read 3, iclass 27, count 0 2006.173.02:06:52.58#ibcon#about to read 4, iclass 27, count 0 2006.173.02:06:52.58#ibcon#read 4, iclass 27, count 0 2006.173.02:06:52.58#ibcon#about to read 5, iclass 27, count 0 2006.173.02:06:52.58#ibcon#read 5, iclass 27, count 0 2006.173.02:06:52.58#ibcon#about to read 6, iclass 27, count 0 2006.173.02:06:52.58#ibcon#read 6, iclass 27, count 0 2006.173.02:06:52.58#ibcon#end of sib2, iclass 27, count 0 2006.173.02:06:52.58#ibcon#*mode == 0, iclass 27, count 0 2006.173.02:06:52.58#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.02:06:52.58#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.02:06:52.58#ibcon#*before write, iclass 27, count 0 2006.173.02:06:52.58#ibcon#enter sib2, iclass 27, count 0 2006.173.02:06:52.58#ibcon#flushed, iclass 27, count 0 2006.173.02:06:52.58#ibcon#about to write, iclass 27, count 0 2006.173.02:06:52.58#ibcon#wrote, iclass 27, count 0 2006.173.02:06:52.58#ibcon#about to read 3, iclass 27, count 0 2006.173.02:06:52.62#ibcon#read 3, iclass 27, count 0 2006.173.02:06:52.62#ibcon#about to read 4, iclass 27, count 0 2006.173.02:06:52.62#ibcon#read 4, iclass 27, count 0 2006.173.02:06:52.62#ibcon#about to read 5, iclass 27, count 0 2006.173.02:06:52.62#ibcon#read 5, iclass 27, count 0 2006.173.02:06:52.62#ibcon#about to read 6, iclass 27, count 0 2006.173.02:06:52.62#ibcon#read 6, iclass 27, count 0 2006.173.02:06:52.62#ibcon#end of sib2, iclass 27, count 0 2006.173.02:06:52.62#ibcon#*after write, iclass 27, count 0 2006.173.02:06:52.62#ibcon#*before return 0, iclass 27, count 0 2006.173.02:06:52.62#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.02:06:52.62#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.02:06:52.62#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.02:06:52.62#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.02:06:52.63$vck44/vb=5,4 2006.173.02:06:52.63#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.02:06:52.63#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.02:06:52.63#ibcon#ireg 11 cls_cnt 2 2006.173.02:06:52.63#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.02:06:52.67#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.02:06:52.67#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.02:06:52.67#ibcon#enter wrdev, iclass 29, count 2 2006.173.02:06:52.67#ibcon#first serial, iclass 29, count 2 2006.173.02:06:52.67#ibcon#enter sib2, iclass 29, count 2 2006.173.02:06:52.67#ibcon#flushed, iclass 29, count 2 2006.173.02:06:52.67#ibcon#about to write, iclass 29, count 2 2006.173.02:06:52.67#ibcon#wrote, iclass 29, count 2 2006.173.02:06:52.67#ibcon#about to read 3, iclass 29, count 2 2006.173.02:06:52.69#ibcon#read 3, iclass 29, count 2 2006.173.02:06:52.69#ibcon#about to read 4, iclass 29, count 2 2006.173.02:06:52.69#ibcon#read 4, iclass 29, count 2 2006.173.02:06:52.69#ibcon#about to read 5, iclass 29, count 2 2006.173.02:06:52.69#ibcon#read 5, iclass 29, count 2 2006.173.02:06:52.69#ibcon#about to read 6, iclass 29, count 2 2006.173.02:06:52.69#ibcon#read 6, iclass 29, count 2 2006.173.02:06:52.69#ibcon#end of sib2, iclass 29, count 2 2006.173.02:06:52.69#ibcon#*mode == 0, iclass 29, count 2 2006.173.02:06:52.69#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.02:06:52.69#ibcon#[27=AT05-04\r\n] 2006.173.02:06:52.69#ibcon#*before write, iclass 29, count 2 2006.173.02:06:52.69#ibcon#enter sib2, iclass 29, count 2 2006.173.02:06:52.69#ibcon#flushed, iclass 29, count 2 2006.173.02:06:52.69#ibcon#about to write, iclass 29, count 2 2006.173.02:06:52.69#ibcon#wrote, iclass 29, count 2 2006.173.02:06:52.69#ibcon#about to read 3, iclass 29, count 2 2006.173.02:06:52.72#ibcon#read 3, iclass 29, count 2 2006.173.02:06:52.72#ibcon#about to read 4, iclass 29, count 2 2006.173.02:06:52.72#ibcon#read 4, iclass 29, count 2 2006.173.02:06:52.72#ibcon#about to read 5, iclass 29, count 2 2006.173.02:06:52.72#ibcon#read 5, iclass 29, count 2 2006.173.02:06:52.72#ibcon#about to read 6, iclass 29, count 2 2006.173.02:06:52.72#ibcon#read 6, iclass 29, count 2 2006.173.02:06:52.72#ibcon#end of sib2, iclass 29, count 2 2006.173.02:06:52.72#ibcon#*after write, iclass 29, count 2 2006.173.02:06:52.72#ibcon#*before return 0, iclass 29, count 2 2006.173.02:06:52.72#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.02:06:52.72#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.02:06:52.72#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.02:06:52.72#ibcon#ireg 7 cls_cnt 0 2006.173.02:06:52.72#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.02:06:52.84#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.02:06:52.84#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.02:06:52.84#ibcon#enter wrdev, iclass 29, count 0 2006.173.02:06:52.84#ibcon#first serial, iclass 29, count 0 2006.173.02:06:52.84#ibcon#enter sib2, iclass 29, count 0 2006.173.02:06:52.84#ibcon#flushed, iclass 29, count 0 2006.173.02:06:52.84#ibcon#about to write, iclass 29, count 0 2006.173.02:06:52.84#ibcon#wrote, iclass 29, count 0 2006.173.02:06:52.84#ibcon#about to read 3, iclass 29, count 0 2006.173.02:06:52.86#ibcon#read 3, iclass 29, count 0 2006.173.02:06:52.86#ibcon#about to read 4, iclass 29, count 0 2006.173.02:06:52.86#ibcon#read 4, iclass 29, count 0 2006.173.02:06:52.86#ibcon#about to read 5, iclass 29, count 0 2006.173.02:06:52.86#ibcon#read 5, iclass 29, count 0 2006.173.02:06:52.86#ibcon#about to read 6, iclass 29, count 0 2006.173.02:06:52.86#ibcon#read 6, iclass 29, count 0 2006.173.02:06:52.86#ibcon#end of sib2, iclass 29, count 0 2006.173.02:06:52.86#ibcon#*mode == 0, iclass 29, count 0 2006.173.02:06:52.86#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.02:06:52.86#ibcon#[27=USB\r\n] 2006.173.02:06:52.86#ibcon#*before write, iclass 29, count 0 2006.173.02:06:52.86#ibcon#enter sib2, iclass 29, count 0 2006.173.02:06:52.86#ibcon#flushed, iclass 29, count 0 2006.173.02:06:52.86#ibcon#about to write, iclass 29, count 0 2006.173.02:06:52.86#ibcon#wrote, iclass 29, count 0 2006.173.02:06:52.86#ibcon#about to read 3, iclass 29, count 0 2006.173.02:06:52.89#ibcon#read 3, iclass 29, count 0 2006.173.02:06:52.89#ibcon#about to read 4, iclass 29, count 0 2006.173.02:06:52.89#ibcon#read 4, iclass 29, count 0 2006.173.02:06:52.89#ibcon#about to read 5, iclass 29, count 0 2006.173.02:06:52.89#ibcon#read 5, iclass 29, count 0 2006.173.02:06:52.89#ibcon#about to read 6, iclass 29, count 0 2006.173.02:06:52.89#ibcon#read 6, iclass 29, count 0 2006.173.02:06:52.89#ibcon#end of sib2, iclass 29, count 0 2006.173.02:06:52.89#ibcon#*after write, iclass 29, count 0 2006.173.02:06:52.89#ibcon#*before return 0, iclass 29, count 0 2006.173.02:06:52.89#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.02:06:52.89#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.02:06:52.89#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.02:06:52.89#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.02:06:52.90$vck44/vblo=6,719.99 2006.173.02:06:52.90#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.02:06:52.90#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.02:06:52.90#ibcon#ireg 17 cls_cnt 0 2006.173.02:06:52.90#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.02:06:52.90#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.02:06:52.90#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.02:06:52.90#ibcon#enter wrdev, iclass 31, count 0 2006.173.02:06:52.90#ibcon#first serial, iclass 31, count 0 2006.173.02:06:52.90#ibcon#enter sib2, iclass 31, count 0 2006.173.02:06:52.90#ibcon#flushed, iclass 31, count 0 2006.173.02:06:52.90#ibcon#about to write, iclass 31, count 0 2006.173.02:06:52.90#ibcon#wrote, iclass 31, count 0 2006.173.02:06:52.90#ibcon#about to read 3, iclass 31, count 0 2006.173.02:06:52.91#ibcon#read 3, iclass 31, count 0 2006.173.02:06:52.91#ibcon#about to read 4, iclass 31, count 0 2006.173.02:06:52.91#ibcon#read 4, iclass 31, count 0 2006.173.02:06:52.91#ibcon#about to read 5, iclass 31, count 0 2006.173.02:06:52.91#ibcon#read 5, iclass 31, count 0 2006.173.02:06:52.91#ibcon#about to read 6, iclass 31, count 0 2006.173.02:06:52.91#ibcon#read 6, iclass 31, count 0 2006.173.02:06:52.91#ibcon#end of sib2, iclass 31, count 0 2006.173.02:06:52.91#ibcon#*mode == 0, iclass 31, count 0 2006.173.02:06:52.91#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.02:06:52.91#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.02:06:52.91#ibcon#*before write, iclass 31, count 0 2006.173.02:06:52.91#ibcon#enter sib2, iclass 31, count 0 2006.173.02:06:52.91#ibcon#flushed, iclass 31, count 0 2006.173.02:06:52.91#ibcon#about to write, iclass 31, count 0 2006.173.02:06:52.91#ibcon#wrote, iclass 31, count 0 2006.173.02:06:52.91#ibcon#about to read 3, iclass 31, count 0 2006.173.02:06:52.95#ibcon#read 3, iclass 31, count 0 2006.173.02:06:52.95#ibcon#about to read 4, iclass 31, count 0 2006.173.02:06:52.95#ibcon#read 4, iclass 31, count 0 2006.173.02:06:52.95#ibcon#about to read 5, iclass 31, count 0 2006.173.02:06:52.95#ibcon#read 5, iclass 31, count 0 2006.173.02:06:52.95#ibcon#about to read 6, iclass 31, count 0 2006.173.02:06:52.95#ibcon#read 6, iclass 31, count 0 2006.173.02:06:52.95#ibcon#end of sib2, iclass 31, count 0 2006.173.02:06:52.95#ibcon#*after write, iclass 31, count 0 2006.173.02:06:52.95#ibcon#*before return 0, iclass 31, count 0 2006.173.02:06:52.95#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.02:06:52.95#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.02:06:52.95#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.02:06:52.95#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.02:06:52.96$vck44/vb=6,4 2006.173.02:06:52.96#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.173.02:06:52.96#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.173.02:06:52.96#ibcon#ireg 11 cls_cnt 2 2006.173.02:06:52.96#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.02:06:53.00#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.02:06:53.00#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.02:06:53.00#ibcon#enter wrdev, iclass 33, count 2 2006.173.02:06:53.00#ibcon#first serial, iclass 33, count 2 2006.173.02:06:53.00#ibcon#enter sib2, iclass 33, count 2 2006.173.02:06:53.00#ibcon#flushed, iclass 33, count 2 2006.173.02:06:53.00#ibcon#about to write, iclass 33, count 2 2006.173.02:06:53.00#ibcon#wrote, iclass 33, count 2 2006.173.02:06:53.00#ibcon#about to read 3, iclass 33, count 2 2006.173.02:06:53.02#ibcon#read 3, iclass 33, count 2 2006.173.02:06:53.02#ibcon#about to read 4, iclass 33, count 2 2006.173.02:06:53.02#ibcon#read 4, iclass 33, count 2 2006.173.02:06:53.02#ibcon#about to read 5, iclass 33, count 2 2006.173.02:06:53.02#ibcon#read 5, iclass 33, count 2 2006.173.02:06:53.02#ibcon#about to read 6, iclass 33, count 2 2006.173.02:06:53.02#ibcon#read 6, iclass 33, count 2 2006.173.02:06:53.02#ibcon#end of sib2, iclass 33, count 2 2006.173.02:06:53.02#ibcon#*mode == 0, iclass 33, count 2 2006.173.02:06:53.02#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.173.02:06:53.02#ibcon#[27=AT06-04\r\n] 2006.173.02:06:53.02#ibcon#*before write, iclass 33, count 2 2006.173.02:06:53.02#ibcon#enter sib2, iclass 33, count 2 2006.173.02:06:53.02#ibcon#flushed, iclass 33, count 2 2006.173.02:06:53.02#ibcon#about to write, iclass 33, count 2 2006.173.02:06:53.02#ibcon#wrote, iclass 33, count 2 2006.173.02:06:53.02#ibcon#about to read 3, iclass 33, count 2 2006.173.02:06:53.05#ibcon#read 3, iclass 33, count 2 2006.173.02:06:53.05#ibcon#about to read 4, iclass 33, count 2 2006.173.02:06:53.05#ibcon#read 4, iclass 33, count 2 2006.173.02:06:53.05#ibcon#about to read 5, iclass 33, count 2 2006.173.02:06:53.05#ibcon#read 5, iclass 33, count 2 2006.173.02:06:53.05#ibcon#about to read 6, iclass 33, count 2 2006.173.02:06:53.05#ibcon#read 6, iclass 33, count 2 2006.173.02:06:53.05#ibcon#end of sib2, iclass 33, count 2 2006.173.02:06:53.05#ibcon#*after write, iclass 33, count 2 2006.173.02:06:53.05#ibcon#*before return 0, iclass 33, count 2 2006.173.02:06:53.05#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.02:06:53.05#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.173.02:06:53.05#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.173.02:06:53.05#ibcon#ireg 7 cls_cnt 0 2006.173.02:06:53.05#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.02:06:53.17#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.02:06:53.17#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.02:06:53.17#ibcon#enter wrdev, iclass 33, count 0 2006.173.02:06:53.17#ibcon#first serial, iclass 33, count 0 2006.173.02:06:53.17#ibcon#enter sib2, iclass 33, count 0 2006.173.02:06:53.17#ibcon#flushed, iclass 33, count 0 2006.173.02:06:53.17#ibcon#about to write, iclass 33, count 0 2006.173.02:06:53.17#ibcon#wrote, iclass 33, count 0 2006.173.02:06:53.17#ibcon#about to read 3, iclass 33, count 0 2006.173.02:06:53.19#ibcon#read 3, iclass 33, count 0 2006.173.02:06:53.19#ibcon#about to read 4, iclass 33, count 0 2006.173.02:06:53.19#ibcon#read 4, iclass 33, count 0 2006.173.02:06:53.19#ibcon#about to read 5, iclass 33, count 0 2006.173.02:06:53.19#ibcon#read 5, iclass 33, count 0 2006.173.02:06:53.19#ibcon#about to read 6, iclass 33, count 0 2006.173.02:06:53.19#ibcon#read 6, iclass 33, count 0 2006.173.02:06:53.19#ibcon#end of sib2, iclass 33, count 0 2006.173.02:06:53.19#ibcon#*mode == 0, iclass 33, count 0 2006.173.02:06:53.19#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.02:06:53.19#ibcon#[27=USB\r\n] 2006.173.02:06:53.19#ibcon#*before write, iclass 33, count 0 2006.173.02:06:53.19#ibcon#enter sib2, iclass 33, count 0 2006.173.02:06:53.19#ibcon#flushed, iclass 33, count 0 2006.173.02:06:53.19#ibcon#about to write, iclass 33, count 0 2006.173.02:06:53.19#ibcon#wrote, iclass 33, count 0 2006.173.02:06:53.19#ibcon#about to read 3, iclass 33, count 0 2006.173.02:06:53.22#ibcon#read 3, iclass 33, count 0 2006.173.02:06:53.22#ibcon#about to read 4, iclass 33, count 0 2006.173.02:06:53.22#ibcon#read 4, iclass 33, count 0 2006.173.02:06:53.22#ibcon#about to read 5, iclass 33, count 0 2006.173.02:06:53.22#ibcon#read 5, iclass 33, count 0 2006.173.02:06:53.22#ibcon#about to read 6, iclass 33, count 0 2006.173.02:06:53.22#ibcon#read 6, iclass 33, count 0 2006.173.02:06:53.22#ibcon#end of sib2, iclass 33, count 0 2006.173.02:06:53.22#ibcon#*after write, iclass 33, count 0 2006.173.02:06:53.22#ibcon#*before return 0, iclass 33, count 0 2006.173.02:06:53.22#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.02:06:53.22#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.173.02:06:53.22#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.02:06:53.22#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.02:06:53.23$vck44/vblo=7,734.99 2006.173.02:06:53.23#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.02:06:53.23#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.02:06:53.23#ibcon#ireg 17 cls_cnt 0 2006.173.02:06:53.23#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.02:06:53.23#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.02:06:53.23#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.02:06:53.23#ibcon#enter wrdev, iclass 35, count 0 2006.173.02:06:53.23#ibcon#first serial, iclass 35, count 0 2006.173.02:06:53.23#ibcon#enter sib2, iclass 35, count 0 2006.173.02:06:53.23#ibcon#flushed, iclass 35, count 0 2006.173.02:06:53.23#ibcon#about to write, iclass 35, count 0 2006.173.02:06:53.23#ibcon#wrote, iclass 35, count 0 2006.173.02:06:53.23#ibcon#about to read 3, iclass 35, count 0 2006.173.02:06:53.24#ibcon#read 3, iclass 35, count 0 2006.173.02:06:53.24#ibcon#about to read 4, iclass 35, count 0 2006.173.02:06:53.24#ibcon#read 4, iclass 35, count 0 2006.173.02:06:53.24#ibcon#about to read 5, iclass 35, count 0 2006.173.02:06:53.24#ibcon#read 5, iclass 35, count 0 2006.173.02:06:53.24#ibcon#about to read 6, iclass 35, count 0 2006.173.02:06:53.24#ibcon#read 6, iclass 35, count 0 2006.173.02:06:53.24#ibcon#end of sib2, iclass 35, count 0 2006.173.02:06:53.24#ibcon#*mode == 0, iclass 35, count 0 2006.173.02:06:53.24#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.02:06:53.24#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.02:06:53.24#ibcon#*before write, iclass 35, count 0 2006.173.02:06:53.24#ibcon#enter sib2, iclass 35, count 0 2006.173.02:06:53.24#ibcon#flushed, iclass 35, count 0 2006.173.02:06:53.24#ibcon#about to write, iclass 35, count 0 2006.173.02:06:53.24#ibcon#wrote, iclass 35, count 0 2006.173.02:06:53.24#ibcon#about to read 3, iclass 35, count 0 2006.173.02:06:53.28#ibcon#read 3, iclass 35, count 0 2006.173.02:06:53.28#ibcon#about to read 4, iclass 35, count 0 2006.173.02:06:53.28#ibcon#read 4, iclass 35, count 0 2006.173.02:06:53.28#ibcon#about to read 5, iclass 35, count 0 2006.173.02:06:53.28#ibcon#read 5, iclass 35, count 0 2006.173.02:06:53.28#ibcon#about to read 6, iclass 35, count 0 2006.173.02:06:53.28#ibcon#read 6, iclass 35, count 0 2006.173.02:06:53.28#ibcon#end of sib2, iclass 35, count 0 2006.173.02:06:53.28#ibcon#*after write, iclass 35, count 0 2006.173.02:06:53.28#ibcon#*before return 0, iclass 35, count 0 2006.173.02:06:53.28#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.02:06:53.28#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.02:06:53.28#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.02:06:53.28#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.02:06:53.29$vck44/vb=7,4 2006.173.02:06:53.29#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.173.02:06:53.29#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.173.02:06:53.29#ibcon#ireg 11 cls_cnt 2 2006.173.02:06:53.29#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.02:06:53.33#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.02:06:53.33#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.02:06:53.33#ibcon#enter wrdev, iclass 37, count 2 2006.173.02:06:53.33#ibcon#first serial, iclass 37, count 2 2006.173.02:06:53.33#ibcon#enter sib2, iclass 37, count 2 2006.173.02:06:53.33#ibcon#flushed, iclass 37, count 2 2006.173.02:06:53.33#ibcon#about to write, iclass 37, count 2 2006.173.02:06:53.33#ibcon#wrote, iclass 37, count 2 2006.173.02:06:53.33#ibcon#about to read 3, iclass 37, count 2 2006.173.02:06:53.35#ibcon#read 3, iclass 37, count 2 2006.173.02:06:53.35#ibcon#about to read 4, iclass 37, count 2 2006.173.02:06:53.35#ibcon#read 4, iclass 37, count 2 2006.173.02:06:53.35#ibcon#about to read 5, iclass 37, count 2 2006.173.02:06:53.35#ibcon#read 5, iclass 37, count 2 2006.173.02:06:53.35#ibcon#about to read 6, iclass 37, count 2 2006.173.02:06:53.35#ibcon#read 6, iclass 37, count 2 2006.173.02:06:53.35#ibcon#end of sib2, iclass 37, count 2 2006.173.02:06:53.35#ibcon#*mode == 0, iclass 37, count 2 2006.173.02:06:53.35#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.173.02:06:53.35#ibcon#[27=AT07-04\r\n] 2006.173.02:06:53.35#ibcon#*before write, iclass 37, count 2 2006.173.02:06:53.35#ibcon#enter sib2, iclass 37, count 2 2006.173.02:06:53.35#ibcon#flushed, iclass 37, count 2 2006.173.02:06:53.35#ibcon#about to write, iclass 37, count 2 2006.173.02:06:53.35#ibcon#wrote, iclass 37, count 2 2006.173.02:06:53.35#ibcon#about to read 3, iclass 37, count 2 2006.173.02:06:53.38#ibcon#read 3, iclass 37, count 2 2006.173.02:06:53.38#ibcon#about to read 4, iclass 37, count 2 2006.173.02:06:53.38#ibcon#read 4, iclass 37, count 2 2006.173.02:06:53.38#ibcon#about to read 5, iclass 37, count 2 2006.173.02:06:53.38#ibcon#read 5, iclass 37, count 2 2006.173.02:06:53.38#ibcon#about to read 6, iclass 37, count 2 2006.173.02:06:53.38#ibcon#read 6, iclass 37, count 2 2006.173.02:06:53.38#ibcon#end of sib2, iclass 37, count 2 2006.173.02:06:53.38#ibcon#*after write, iclass 37, count 2 2006.173.02:06:53.38#ibcon#*before return 0, iclass 37, count 2 2006.173.02:06:53.38#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.02:06:53.38#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.173.02:06:53.38#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.173.02:06:53.38#ibcon#ireg 7 cls_cnt 0 2006.173.02:06:53.38#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.02:06:53.50#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.02:06:53.50#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.02:06:53.50#ibcon#enter wrdev, iclass 37, count 0 2006.173.02:06:53.50#ibcon#first serial, iclass 37, count 0 2006.173.02:06:53.50#ibcon#enter sib2, iclass 37, count 0 2006.173.02:06:53.50#ibcon#flushed, iclass 37, count 0 2006.173.02:06:53.50#ibcon#about to write, iclass 37, count 0 2006.173.02:06:53.50#ibcon#wrote, iclass 37, count 0 2006.173.02:06:53.50#ibcon#about to read 3, iclass 37, count 0 2006.173.02:06:53.52#ibcon#read 3, iclass 37, count 0 2006.173.02:06:53.52#ibcon#about to read 4, iclass 37, count 0 2006.173.02:06:53.52#ibcon#read 4, iclass 37, count 0 2006.173.02:06:53.52#ibcon#about to read 5, iclass 37, count 0 2006.173.02:06:53.52#ibcon#read 5, iclass 37, count 0 2006.173.02:06:53.52#ibcon#about to read 6, iclass 37, count 0 2006.173.02:06:53.52#ibcon#read 6, iclass 37, count 0 2006.173.02:06:53.52#ibcon#end of sib2, iclass 37, count 0 2006.173.02:06:53.52#ibcon#*mode == 0, iclass 37, count 0 2006.173.02:06:53.52#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.02:06:53.52#ibcon#[27=USB\r\n] 2006.173.02:06:53.52#ibcon#*before write, iclass 37, count 0 2006.173.02:06:53.52#ibcon#enter sib2, iclass 37, count 0 2006.173.02:06:53.52#ibcon#flushed, iclass 37, count 0 2006.173.02:06:53.52#ibcon#about to write, iclass 37, count 0 2006.173.02:06:53.52#ibcon#wrote, iclass 37, count 0 2006.173.02:06:53.52#ibcon#about to read 3, iclass 37, count 0 2006.173.02:06:53.55#ibcon#read 3, iclass 37, count 0 2006.173.02:06:53.55#ibcon#about to read 4, iclass 37, count 0 2006.173.02:06:53.55#ibcon#read 4, iclass 37, count 0 2006.173.02:06:53.55#ibcon#about to read 5, iclass 37, count 0 2006.173.02:06:53.55#ibcon#read 5, iclass 37, count 0 2006.173.02:06:53.55#ibcon#about to read 6, iclass 37, count 0 2006.173.02:06:53.55#ibcon#read 6, iclass 37, count 0 2006.173.02:06:53.55#ibcon#end of sib2, iclass 37, count 0 2006.173.02:06:53.55#ibcon#*after write, iclass 37, count 0 2006.173.02:06:53.55#ibcon#*before return 0, iclass 37, count 0 2006.173.02:06:53.55#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.02:06:53.55#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.173.02:06:53.55#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.02:06:53.55#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.02:06:53.56$vck44/vblo=8,744.99 2006.173.02:06:53.56#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.02:06:53.56#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.02:06:53.56#ibcon#ireg 17 cls_cnt 0 2006.173.02:06:53.56#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.02:06:53.56#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.02:06:53.56#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.02:06:53.56#ibcon#enter wrdev, iclass 39, count 0 2006.173.02:06:53.56#ibcon#first serial, iclass 39, count 0 2006.173.02:06:53.56#ibcon#enter sib2, iclass 39, count 0 2006.173.02:06:53.56#ibcon#flushed, iclass 39, count 0 2006.173.02:06:53.56#ibcon#about to write, iclass 39, count 0 2006.173.02:06:53.56#ibcon#wrote, iclass 39, count 0 2006.173.02:06:53.56#ibcon#about to read 3, iclass 39, count 0 2006.173.02:06:53.57#ibcon#read 3, iclass 39, count 0 2006.173.02:06:53.57#ibcon#about to read 4, iclass 39, count 0 2006.173.02:06:53.57#ibcon#read 4, iclass 39, count 0 2006.173.02:06:53.57#ibcon#about to read 5, iclass 39, count 0 2006.173.02:06:53.57#ibcon#read 5, iclass 39, count 0 2006.173.02:06:53.57#ibcon#about to read 6, iclass 39, count 0 2006.173.02:06:53.57#ibcon#read 6, iclass 39, count 0 2006.173.02:06:53.57#ibcon#end of sib2, iclass 39, count 0 2006.173.02:06:53.57#ibcon#*mode == 0, iclass 39, count 0 2006.173.02:06:53.57#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.02:06:53.57#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.02:06:53.57#ibcon#*before write, iclass 39, count 0 2006.173.02:06:53.57#ibcon#enter sib2, iclass 39, count 0 2006.173.02:06:53.57#ibcon#flushed, iclass 39, count 0 2006.173.02:06:53.57#ibcon#about to write, iclass 39, count 0 2006.173.02:06:53.57#ibcon#wrote, iclass 39, count 0 2006.173.02:06:53.57#ibcon#about to read 3, iclass 39, count 0 2006.173.02:06:53.61#ibcon#read 3, iclass 39, count 0 2006.173.02:06:53.61#ibcon#about to read 4, iclass 39, count 0 2006.173.02:06:53.61#ibcon#read 4, iclass 39, count 0 2006.173.02:06:53.61#ibcon#about to read 5, iclass 39, count 0 2006.173.02:06:53.61#ibcon#read 5, iclass 39, count 0 2006.173.02:06:53.61#ibcon#about to read 6, iclass 39, count 0 2006.173.02:06:53.61#ibcon#read 6, iclass 39, count 0 2006.173.02:06:53.61#ibcon#end of sib2, iclass 39, count 0 2006.173.02:06:53.61#ibcon#*after write, iclass 39, count 0 2006.173.02:06:53.61#ibcon#*before return 0, iclass 39, count 0 2006.173.02:06:53.61#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.02:06:53.61#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.02:06:53.61#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.02:06:53.61#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.02:06:53.61$vck44/vb=8,4 2006.173.02:06:53.62#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.02:06:53.62#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.02:06:53.62#ibcon#ireg 11 cls_cnt 2 2006.173.02:06:53.62#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.02:06:53.66#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.02:06:53.66#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.02:06:53.66#ibcon#enter wrdev, iclass 3, count 2 2006.173.02:06:53.66#ibcon#first serial, iclass 3, count 2 2006.173.02:06:53.66#ibcon#enter sib2, iclass 3, count 2 2006.173.02:06:53.66#ibcon#flushed, iclass 3, count 2 2006.173.02:06:53.66#ibcon#about to write, iclass 3, count 2 2006.173.02:06:53.66#ibcon#wrote, iclass 3, count 2 2006.173.02:06:53.66#ibcon#about to read 3, iclass 3, count 2 2006.173.02:06:53.68#ibcon#read 3, iclass 3, count 2 2006.173.02:06:53.68#ibcon#about to read 4, iclass 3, count 2 2006.173.02:06:53.68#ibcon#read 4, iclass 3, count 2 2006.173.02:06:53.68#ibcon#about to read 5, iclass 3, count 2 2006.173.02:06:53.68#ibcon#read 5, iclass 3, count 2 2006.173.02:06:53.68#ibcon#about to read 6, iclass 3, count 2 2006.173.02:06:53.68#ibcon#read 6, iclass 3, count 2 2006.173.02:06:53.68#ibcon#end of sib2, iclass 3, count 2 2006.173.02:06:53.68#ibcon#*mode == 0, iclass 3, count 2 2006.173.02:06:53.68#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.02:06:53.68#ibcon#[27=AT08-04\r\n] 2006.173.02:06:53.68#ibcon#*before write, iclass 3, count 2 2006.173.02:06:53.68#ibcon#enter sib2, iclass 3, count 2 2006.173.02:06:53.68#ibcon#flushed, iclass 3, count 2 2006.173.02:06:53.68#ibcon#about to write, iclass 3, count 2 2006.173.02:06:53.68#ibcon#wrote, iclass 3, count 2 2006.173.02:06:53.68#ibcon#about to read 3, iclass 3, count 2 2006.173.02:06:53.71#ibcon#read 3, iclass 3, count 2 2006.173.02:06:53.71#ibcon#about to read 4, iclass 3, count 2 2006.173.02:06:53.71#ibcon#read 4, iclass 3, count 2 2006.173.02:06:53.71#ibcon#about to read 5, iclass 3, count 2 2006.173.02:06:53.71#ibcon#read 5, iclass 3, count 2 2006.173.02:06:53.71#ibcon#about to read 6, iclass 3, count 2 2006.173.02:06:53.71#ibcon#read 6, iclass 3, count 2 2006.173.02:06:53.71#ibcon#end of sib2, iclass 3, count 2 2006.173.02:06:53.71#ibcon#*after write, iclass 3, count 2 2006.173.02:06:53.71#ibcon#*before return 0, iclass 3, count 2 2006.173.02:06:53.71#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.02:06:53.71#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.02:06:53.71#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.02:06:53.71#ibcon#ireg 7 cls_cnt 0 2006.173.02:06:53.71#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.02:06:53.83#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.02:06:53.83#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.02:06:53.83#ibcon#enter wrdev, iclass 3, count 0 2006.173.02:06:53.83#ibcon#first serial, iclass 3, count 0 2006.173.02:06:53.83#ibcon#enter sib2, iclass 3, count 0 2006.173.02:06:53.83#ibcon#flushed, iclass 3, count 0 2006.173.02:06:53.83#ibcon#about to write, iclass 3, count 0 2006.173.02:06:53.83#ibcon#wrote, iclass 3, count 0 2006.173.02:06:53.83#ibcon#about to read 3, iclass 3, count 0 2006.173.02:06:53.85#ibcon#read 3, iclass 3, count 0 2006.173.02:06:53.85#ibcon#about to read 4, iclass 3, count 0 2006.173.02:06:53.85#ibcon#read 4, iclass 3, count 0 2006.173.02:06:53.85#ibcon#about to read 5, iclass 3, count 0 2006.173.02:06:53.85#ibcon#read 5, iclass 3, count 0 2006.173.02:06:53.85#ibcon#about to read 6, iclass 3, count 0 2006.173.02:06:53.85#ibcon#read 6, iclass 3, count 0 2006.173.02:06:53.85#ibcon#end of sib2, iclass 3, count 0 2006.173.02:06:53.85#ibcon#*mode == 0, iclass 3, count 0 2006.173.02:06:53.85#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.02:06:53.85#ibcon#[27=USB\r\n] 2006.173.02:06:53.85#ibcon#*before write, iclass 3, count 0 2006.173.02:06:53.85#ibcon#enter sib2, iclass 3, count 0 2006.173.02:06:53.85#ibcon#flushed, iclass 3, count 0 2006.173.02:06:53.85#ibcon#about to write, iclass 3, count 0 2006.173.02:06:53.85#ibcon#wrote, iclass 3, count 0 2006.173.02:06:53.85#ibcon#about to read 3, iclass 3, count 0 2006.173.02:06:53.88#ibcon#read 3, iclass 3, count 0 2006.173.02:06:53.88#ibcon#about to read 4, iclass 3, count 0 2006.173.02:06:53.88#ibcon#read 4, iclass 3, count 0 2006.173.02:06:53.88#ibcon#about to read 5, iclass 3, count 0 2006.173.02:06:53.88#ibcon#read 5, iclass 3, count 0 2006.173.02:06:53.88#ibcon#about to read 6, iclass 3, count 0 2006.173.02:06:53.88#ibcon#read 6, iclass 3, count 0 2006.173.02:06:53.88#ibcon#end of sib2, iclass 3, count 0 2006.173.02:06:53.88#ibcon#*after write, iclass 3, count 0 2006.173.02:06:53.88#ibcon#*before return 0, iclass 3, count 0 2006.173.02:06:53.88#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.02:06:53.88#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.02:06:53.88#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.02:06:53.88#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.02:06:53.89$vck44/vabw=wide 2006.173.02:06:53.89#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.02:06:53.89#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.02:06:53.89#ibcon#ireg 8 cls_cnt 0 2006.173.02:06:53.89#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.02:06:53.89#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.02:06:53.89#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.02:06:53.89#ibcon#enter wrdev, iclass 5, count 0 2006.173.02:06:53.89#ibcon#first serial, iclass 5, count 0 2006.173.02:06:53.89#ibcon#enter sib2, iclass 5, count 0 2006.173.02:06:53.89#ibcon#flushed, iclass 5, count 0 2006.173.02:06:53.89#ibcon#about to write, iclass 5, count 0 2006.173.02:06:53.89#ibcon#wrote, iclass 5, count 0 2006.173.02:06:53.89#ibcon#about to read 3, iclass 5, count 0 2006.173.02:06:53.90#ibcon#read 3, iclass 5, count 0 2006.173.02:06:53.90#ibcon#about to read 4, iclass 5, count 0 2006.173.02:06:53.90#ibcon#read 4, iclass 5, count 0 2006.173.02:06:53.90#ibcon#about to read 5, iclass 5, count 0 2006.173.02:06:53.90#ibcon#read 5, iclass 5, count 0 2006.173.02:06:53.90#ibcon#about to read 6, iclass 5, count 0 2006.173.02:06:53.90#ibcon#read 6, iclass 5, count 0 2006.173.02:06:53.90#ibcon#end of sib2, iclass 5, count 0 2006.173.02:06:53.90#ibcon#*mode == 0, iclass 5, count 0 2006.173.02:06:53.90#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.02:06:53.90#ibcon#[25=BW32\r\n] 2006.173.02:06:53.90#ibcon#*before write, iclass 5, count 0 2006.173.02:06:53.90#ibcon#enter sib2, iclass 5, count 0 2006.173.02:06:53.90#ibcon#flushed, iclass 5, count 0 2006.173.02:06:53.90#ibcon#about to write, iclass 5, count 0 2006.173.02:06:53.90#ibcon#wrote, iclass 5, count 0 2006.173.02:06:53.90#ibcon#about to read 3, iclass 5, count 0 2006.173.02:06:53.93#ibcon#read 3, iclass 5, count 0 2006.173.02:06:53.93#ibcon#about to read 4, iclass 5, count 0 2006.173.02:06:53.93#ibcon#read 4, iclass 5, count 0 2006.173.02:06:53.93#ibcon#about to read 5, iclass 5, count 0 2006.173.02:06:53.93#ibcon#read 5, iclass 5, count 0 2006.173.02:06:53.93#ibcon#about to read 6, iclass 5, count 0 2006.173.02:06:53.93#ibcon#read 6, iclass 5, count 0 2006.173.02:06:53.93#ibcon#end of sib2, iclass 5, count 0 2006.173.02:06:53.93#ibcon#*after write, iclass 5, count 0 2006.173.02:06:53.93#ibcon#*before return 0, iclass 5, count 0 2006.173.02:06:53.93#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.02:06:53.93#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.02:06:53.93#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.02:06:53.93#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.02:06:53.94$vck44/vbbw=wide 2006.173.02:06:53.94#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.02:06:53.94#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.02:06:53.94#ibcon#ireg 8 cls_cnt 0 2006.173.02:06:53.94#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.02:06:53.99#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.02:06:53.99#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.02:06:53.99#ibcon#enter wrdev, iclass 7, count 0 2006.173.02:06:53.99#ibcon#first serial, iclass 7, count 0 2006.173.02:06:53.99#ibcon#enter sib2, iclass 7, count 0 2006.173.02:06:53.99#ibcon#flushed, iclass 7, count 0 2006.173.02:06:53.99#ibcon#about to write, iclass 7, count 0 2006.173.02:06:53.99#ibcon#wrote, iclass 7, count 0 2006.173.02:06:53.99#ibcon#about to read 3, iclass 7, count 0 2006.173.02:06:54.01#ibcon#read 3, iclass 7, count 0 2006.173.02:06:54.01#ibcon#about to read 4, iclass 7, count 0 2006.173.02:06:54.01#ibcon#read 4, iclass 7, count 0 2006.173.02:06:54.01#ibcon#about to read 5, iclass 7, count 0 2006.173.02:06:54.01#ibcon#read 5, iclass 7, count 0 2006.173.02:06:54.01#ibcon#about to read 6, iclass 7, count 0 2006.173.02:06:54.01#ibcon#read 6, iclass 7, count 0 2006.173.02:06:54.01#ibcon#end of sib2, iclass 7, count 0 2006.173.02:06:54.01#ibcon#*mode == 0, iclass 7, count 0 2006.173.02:06:54.01#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.02:06:54.01#ibcon#[27=BW32\r\n] 2006.173.02:06:54.01#ibcon#*before write, iclass 7, count 0 2006.173.02:06:54.01#ibcon#enter sib2, iclass 7, count 0 2006.173.02:06:54.01#ibcon#flushed, iclass 7, count 0 2006.173.02:06:54.01#ibcon#about to write, iclass 7, count 0 2006.173.02:06:54.01#ibcon#wrote, iclass 7, count 0 2006.173.02:06:54.01#ibcon#about to read 3, iclass 7, count 0 2006.173.02:06:54.05#ibcon#read 3, iclass 7, count 0 2006.173.02:06:54.05#ibcon#about to read 4, iclass 7, count 0 2006.173.02:06:54.05#ibcon#read 4, iclass 7, count 0 2006.173.02:06:54.05#ibcon#about to read 5, iclass 7, count 0 2006.173.02:06:54.05#ibcon#read 5, iclass 7, count 0 2006.173.02:06:54.05#ibcon#about to read 6, iclass 7, count 0 2006.173.02:06:54.05#ibcon#read 6, iclass 7, count 0 2006.173.02:06:54.05#ibcon#end of sib2, iclass 7, count 0 2006.173.02:06:54.05#ibcon#*after write, iclass 7, count 0 2006.173.02:06:54.05#ibcon#*before return 0, iclass 7, count 0 2006.173.02:06:54.05#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.02:06:54.05#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.02:06:54.05#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.02:06:54.05#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.02:06:54.05$setupk4/ifdk4 2006.173.02:06:54.05$ifdk4/lo= 2006.173.02:06:54.05$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.02:06:54.05$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.02:06:54.05$ifdk4/patch= 2006.173.02:06:54.05$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.02:06:54.05$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.02:06:54.05$setupk4/!*+20s 2006.173.02:06:55.50#abcon#<5=/13 1.0 2.7 22.69 821006.6\r\n> 2006.173.02:06:55.52#abcon#{5=INTERFACE CLEAR} 2006.173.02:06:55.58#abcon#[5=S1D000X0/0*\r\n] 2006.173.02:07:05.67#abcon#<5=/13 1.0 2.7 22.69 831006.5\r\n> 2006.173.02:07:05.69#abcon#{5=INTERFACE CLEAR} 2006.173.02:07:05.75#abcon#[5=S1D000X0/0*\r\n] 2006.173.02:07:08.69$setupk4/"tpicd 2006.173.02:07:08.69$setupk4/echo=off 2006.173.02:07:08.69$setupk4/xlog=off 2006.173.02:07:08.69:!2006.173.02:09:25 2006.173.02:07:45.14#trakl#Source acquired 2006.173.02:07:45.14#flagr#flagr/antenna,acquired 2006.173.02:09:25.00:preob 2006.173.02:09:25.13/onsource/TRACKING 2006.173.02:09:25.13:!2006.173.02:09:35 2006.173.02:09:35.00:"tape 2006.173.02:09:35.00:"st=record 2006.173.02:09:35.00:data_valid=on 2006.173.02:09:35.00:midob 2006.173.02:09:36.13/onsource/TRACKING 2006.173.02:09:36.13/wx/22.67,1006.5,81 2006.173.02:09:36.22/cable/+6.5121E-03 2006.173.02:09:37.31/va/01,07,usb,yes,36,39 2006.173.02:09:37.31/va/02,06,usb,yes,36,37 2006.173.02:09:37.31/va/03,05,usb,yes,46,48 2006.173.02:09:37.31/va/04,06,usb,yes,37,39 2006.173.02:09:37.31/va/05,04,usb,yes,29,29 2006.173.02:09:37.31/va/06,03,usb,yes,41,40 2006.173.02:09:37.31/va/07,04,usb,yes,33,34 2006.173.02:09:37.31/va/08,04,usb,yes,28,34 2006.173.02:09:37.54/valo/01,524.99,yes,locked 2006.173.02:09:37.54/valo/02,534.99,yes,locked 2006.173.02:09:37.54/valo/03,564.99,yes,locked 2006.173.02:09:37.54/valo/04,624.99,yes,locked 2006.173.02:09:37.54/valo/05,734.99,yes,locked 2006.173.02:09:37.54/valo/06,814.99,yes,locked 2006.173.02:09:37.54/valo/07,864.99,yes,locked 2006.173.02:09:37.54/valo/08,884.99,yes,locked 2006.173.02:09:38.63/vb/01,04,usb,yes,29,27 2006.173.02:09:38.63/vb/02,04,usb,yes,31,31 2006.173.02:09:38.63/vb/03,04,usb,yes,28,31 2006.173.02:09:38.63/vb/04,04,usb,yes,33,32 2006.173.02:09:38.63/vb/05,04,usb,yes,25,28 2006.173.02:09:38.63/vb/06,04,usb,yes,30,26 2006.173.02:09:38.63/vb/07,04,usb,yes,30,29 2006.173.02:09:38.63/vb/08,04,usb,yes,27,31 2006.173.02:09:38.86/vblo/01,629.99,yes,locked 2006.173.02:09:38.86/vblo/02,634.99,yes,locked 2006.173.02:09:38.86/vblo/03,649.99,yes,locked 2006.173.02:09:38.86/vblo/04,679.99,yes,locked 2006.173.02:09:38.86/vblo/05,709.99,yes,locked 2006.173.02:09:38.86/vblo/06,719.99,yes,locked 2006.173.02:09:38.86/vblo/07,734.99,yes,locked 2006.173.02:09:38.86/vblo/08,744.99,yes,locked 2006.173.02:09:39.01/vabw/8 2006.173.02:09:39.16/vbbw/8 2006.173.02:09:39.25/xfe/off,on,15.0 2006.173.02:09:39.64/ifatt/23,28,28,28 2006.173.02:09:40.07/fmout-gps/S +3.93E-07 2006.173.02:09:40.16:!2006.173.02:13:15 2006.173.02:13:15.01:data_valid=off 2006.173.02:13:15.02:"et 2006.173.02:13:15.02:!+3s 2006.173.02:13:18.04:"tape 2006.173.02:13:18.05:postob 2006.173.02:13:18.16/cable/+6.5125E-03 2006.173.02:13:18.17/wx/22.69,1006.5,84 2006.173.02:13:18.22/fmout-gps/S +3.94E-07 2006.173.02:13:18.23:scan_name=173-0216,jd0606,50 2006.173.02:13:18.23:source=0552+398,055530.81,394849.2,2000.0,cw 2006.173.02:13:20.14#flagr#flagr/antenna,new-source 2006.173.02:13:20.15:checkk5 2006.173.02:13:20.61/chk_autoobs//k5ts1/ autoobs is running! 2006.173.02:13:21.04/chk_autoobs//k5ts2/ autoobs is running! 2006.173.02:13:21.47/chk_autoobs//k5ts3/ autoobs is running! 2006.173.02:13:21.90/chk_autoobs//k5ts4/ autoobs is running! 2006.173.02:13:22.29/chk_obsdata//k5ts1/T1730209??a.dat file size is correct (nominal:880MB, actual:876MB). 2006.173.02:13:22.71/chk_obsdata//k5ts2/T1730209??b.dat file size is correct (nominal:880MB, actual:876MB). 2006.173.02:13:23.11/chk_obsdata//k5ts3/T1730209??c.dat file size is correct (nominal:880MB, actual:876MB). 2006.173.02:13:23.51/chk_obsdata//k5ts4/T1730209??d.dat file size is correct (nominal:880MB, actual:876MB). 2006.173.02:13:24.33/k5log//k5ts1_log_newline 2006.173.02:13:25.07/k5log//k5ts2_log_newline 2006.173.02:13:25.90/k5log//k5ts3_log_newline 2006.173.02:13:26.62/k5log//k5ts4_log_newline 2006.173.02:13:26.65/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.02:13:26.65:setupk4=1 2006.173.02:13:26.65$setupk4/echo=on 2006.173.02:13:26.65$setupk4/pcalon 2006.173.02:13:26.65$pcalon/"no phase cal control is implemented here 2006.173.02:13:26.65$setupk4/"tpicd=stop 2006.173.02:13:26.65$setupk4/"rec=synch_on 2006.173.02:13:26.65$setupk4/"rec_mode=128 2006.173.02:13:26.65$setupk4/!* 2006.173.02:13:26.65$setupk4/recpk4 2006.173.02:13:26.65$recpk4/recpatch= 2006.173.02:13:26.65$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.02:13:26.65$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.02:13:26.65$setupk4/vck44 2006.173.02:13:26.65$vck44/valo=1,524.99 2006.173.02:13:26.66#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.02:13:26.66#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.02:13:26.66#ibcon#ireg 17 cls_cnt 0 2006.173.02:13:26.66#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.02:13:26.66#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.02:13:26.66#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.02:13:26.66#ibcon#enter wrdev, iclass 26, count 0 2006.173.02:13:26.66#ibcon#first serial, iclass 26, count 0 2006.173.02:13:26.66#ibcon#enter sib2, iclass 26, count 0 2006.173.02:13:26.66#ibcon#flushed, iclass 26, count 0 2006.173.02:13:26.66#ibcon#about to write, iclass 26, count 0 2006.173.02:13:26.66#ibcon#wrote, iclass 26, count 0 2006.173.02:13:26.66#ibcon#about to read 3, iclass 26, count 0 2006.173.02:13:26.70#ibcon#read 3, iclass 26, count 0 2006.173.02:13:26.70#ibcon#about to read 4, iclass 26, count 0 2006.173.02:13:26.70#ibcon#read 4, iclass 26, count 0 2006.173.02:13:26.70#ibcon#about to read 5, iclass 26, count 0 2006.173.02:13:26.70#ibcon#read 5, iclass 26, count 0 2006.173.02:13:26.70#ibcon#about to read 6, iclass 26, count 0 2006.173.02:13:26.70#ibcon#read 6, iclass 26, count 0 2006.173.02:13:26.70#ibcon#end of sib2, iclass 26, count 0 2006.173.02:13:26.70#ibcon#*mode == 0, iclass 26, count 0 2006.173.02:13:26.70#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.02:13:26.70#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.02:13:26.70#ibcon#*before write, iclass 26, count 0 2006.173.02:13:26.70#ibcon#enter sib2, iclass 26, count 0 2006.173.02:13:26.70#ibcon#flushed, iclass 26, count 0 2006.173.02:13:26.70#ibcon#about to write, iclass 26, count 0 2006.173.02:13:26.70#ibcon#wrote, iclass 26, count 0 2006.173.02:13:26.70#ibcon#about to read 3, iclass 26, count 0 2006.173.02:13:26.74#ibcon#read 3, iclass 26, count 0 2006.173.02:13:26.74#ibcon#about to read 4, iclass 26, count 0 2006.173.02:13:26.74#ibcon#read 4, iclass 26, count 0 2006.173.02:13:26.74#ibcon#about to read 5, iclass 26, count 0 2006.173.02:13:26.74#ibcon#read 5, iclass 26, count 0 2006.173.02:13:26.74#ibcon#about to read 6, iclass 26, count 0 2006.173.02:13:26.74#ibcon#read 6, iclass 26, count 0 2006.173.02:13:26.74#ibcon#end of sib2, iclass 26, count 0 2006.173.02:13:26.74#ibcon#*after write, iclass 26, count 0 2006.173.02:13:26.74#ibcon#*before return 0, iclass 26, count 0 2006.173.02:13:26.74#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.02:13:26.74#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.02:13:26.74#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.02:13:26.74#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.02:13:26.74$vck44/va=1,7 2006.173.02:13:26.74#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.02:13:26.74#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.02:13:26.74#ibcon#ireg 11 cls_cnt 2 2006.173.02:13:26.74#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.02:13:26.74#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.02:13:26.74#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.02:13:26.74#ibcon#enter wrdev, iclass 28, count 2 2006.173.02:13:26.74#ibcon#first serial, iclass 28, count 2 2006.173.02:13:26.74#ibcon#enter sib2, iclass 28, count 2 2006.173.02:13:26.74#ibcon#flushed, iclass 28, count 2 2006.173.02:13:26.74#ibcon#about to write, iclass 28, count 2 2006.173.02:13:26.74#ibcon#wrote, iclass 28, count 2 2006.173.02:13:26.74#ibcon#about to read 3, iclass 28, count 2 2006.173.02:13:26.77#ibcon#read 3, iclass 28, count 2 2006.173.02:13:26.77#ibcon#about to read 4, iclass 28, count 2 2006.173.02:13:26.77#ibcon#read 4, iclass 28, count 2 2006.173.02:13:26.77#ibcon#about to read 5, iclass 28, count 2 2006.173.02:13:26.77#ibcon#read 5, iclass 28, count 2 2006.173.02:13:26.77#ibcon#about to read 6, iclass 28, count 2 2006.173.02:13:26.77#ibcon#read 6, iclass 28, count 2 2006.173.02:13:26.77#ibcon#end of sib2, iclass 28, count 2 2006.173.02:13:26.77#ibcon#*mode == 0, iclass 28, count 2 2006.173.02:13:26.77#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.02:13:26.77#ibcon#[25=AT01-07\r\n] 2006.173.02:13:26.77#ibcon#*before write, iclass 28, count 2 2006.173.02:13:26.77#ibcon#enter sib2, iclass 28, count 2 2006.173.02:13:26.77#ibcon#flushed, iclass 28, count 2 2006.173.02:13:26.77#ibcon#about to write, iclass 28, count 2 2006.173.02:13:26.77#ibcon#wrote, iclass 28, count 2 2006.173.02:13:26.77#ibcon#about to read 3, iclass 28, count 2 2006.173.02:13:26.80#ibcon#read 3, iclass 28, count 2 2006.173.02:13:26.80#ibcon#about to read 4, iclass 28, count 2 2006.173.02:13:26.80#ibcon#read 4, iclass 28, count 2 2006.173.02:13:26.80#ibcon#about to read 5, iclass 28, count 2 2006.173.02:13:26.80#ibcon#read 5, iclass 28, count 2 2006.173.02:13:26.80#ibcon#about to read 6, iclass 28, count 2 2006.173.02:13:26.80#ibcon#read 6, iclass 28, count 2 2006.173.02:13:26.80#ibcon#end of sib2, iclass 28, count 2 2006.173.02:13:26.80#ibcon#*after write, iclass 28, count 2 2006.173.02:13:26.80#ibcon#*before return 0, iclass 28, count 2 2006.173.02:13:26.80#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.02:13:26.80#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.02:13:26.80#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.02:13:26.80#ibcon#ireg 7 cls_cnt 0 2006.173.02:13:26.80#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.02:13:26.92#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.02:13:26.92#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.02:13:26.92#ibcon#enter wrdev, iclass 28, count 0 2006.173.02:13:26.92#ibcon#first serial, iclass 28, count 0 2006.173.02:13:26.92#ibcon#enter sib2, iclass 28, count 0 2006.173.02:13:26.92#ibcon#flushed, iclass 28, count 0 2006.173.02:13:26.92#ibcon#about to write, iclass 28, count 0 2006.173.02:13:26.92#ibcon#wrote, iclass 28, count 0 2006.173.02:13:26.92#ibcon#about to read 3, iclass 28, count 0 2006.173.02:13:26.94#ibcon#read 3, iclass 28, count 0 2006.173.02:13:26.94#ibcon#about to read 4, iclass 28, count 0 2006.173.02:13:26.94#ibcon#read 4, iclass 28, count 0 2006.173.02:13:26.94#ibcon#about to read 5, iclass 28, count 0 2006.173.02:13:26.94#ibcon#read 5, iclass 28, count 0 2006.173.02:13:26.94#ibcon#about to read 6, iclass 28, count 0 2006.173.02:13:26.94#ibcon#read 6, iclass 28, count 0 2006.173.02:13:26.94#ibcon#end of sib2, iclass 28, count 0 2006.173.02:13:26.94#ibcon#*mode == 0, iclass 28, count 0 2006.173.02:13:26.94#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.02:13:26.94#ibcon#[25=USB\r\n] 2006.173.02:13:26.94#ibcon#*before write, iclass 28, count 0 2006.173.02:13:26.94#ibcon#enter sib2, iclass 28, count 0 2006.173.02:13:26.94#ibcon#flushed, iclass 28, count 0 2006.173.02:13:26.94#ibcon#about to write, iclass 28, count 0 2006.173.02:13:26.94#ibcon#wrote, iclass 28, count 0 2006.173.02:13:26.94#ibcon#about to read 3, iclass 28, count 0 2006.173.02:13:26.97#ibcon#read 3, iclass 28, count 0 2006.173.02:13:26.97#ibcon#about to read 4, iclass 28, count 0 2006.173.02:13:26.97#ibcon#read 4, iclass 28, count 0 2006.173.02:13:26.97#ibcon#about to read 5, iclass 28, count 0 2006.173.02:13:26.97#ibcon#read 5, iclass 28, count 0 2006.173.02:13:26.97#ibcon#about to read 6, iclass 28, count 0 2006.173.02:13:26.97#ibcon#read 6, iclass 28, count 0 2006.173.02:13:26.97#ibcon#end of sib2, iclass 28, count 0 2006.173.02:13:26.97#ibcon#*after write, iclass 28, count 0 2006.173.02:13:26.97#ibcon#*before return 0, iclass 28, count 0 2006.173.02:13:26.97#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.02:13:26.97#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.02:13:26.97#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.02:13:26.97#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.02:13:26.97$vck44/valo=2,534.99 2006.173.02:13:26.97#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.02:13:26.97#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.02:13:26.97#ibcon#ireg 17 cls_cnt 0 2006.173.02:13:26.97#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.02:13:26.97#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.02:13:26.97#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.02:13:26.97#ibcon#enter wrdev, iclass 30, count 0 2006.173.02:13:26.97#ibcon#first serial, iclass 30, count 0 2006.173.02:13:26.97#ibcon#enter sib2, iclass 30, count 0 2006.173.02:13:26.97#ibcon#flushed, iclass 30, count 0 2006.173.02:13:26.97#ibcon#about to write, iclass 30, count 0 2006.173.02:13:26.97#ibcon#wrote, iclass 30, count 0 2006.173.02:13:26.97#ibcon#about to read 3, iclass 30, count 0 2006.173.02:13:26.99#ibcon#read 3, iclass 30, count 0 2006.173.02:13:26.99#ibcon#about to read 4, iclass 30, count 0 2006.173.02:13:26.99#ibcon#read 4, iclass 30, count 0 2006.173.02:13:26.99#ibcon#about to read 5, iclass 30, count 0 2006.173.02:13:26.99#ibcon#read 5, iclass 30, count 0 2006.173.02:13:26.99#ibcon#about to read 6, iclass 30, count 0 2006.173.02:13:26.99#ibcon#read 6, iclass 30, count 0 2006.173.02:13:26.99#ibcon#end of sib2, iclass 30, count 0 2006.173.02:13:26.99#ibcon#*mode == 0, iclass 30, count 0 2006.173.02:13:26.99#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.02:13:26.99#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.02:13:26.99#ibcon#*before write, iclass 30, count 0 2006.173.02:13:26.99#ibcon#enter sib2, iclass 30, count 0 2006.173.02:13:26.99#ibcon#flushed, iclass 30, count 0 2006.173.02:13:26.99#ibcon#about to write, iclass 30, count 0 2006.173.02:13:26.99#ibcon#wrote, iclass 30, count 0 2006.173.02:13:26.99#ibcon#about to read 3, iclass 30, count 0 2006.173.02:13:27.03#ibcon#read 3, iclass 30, count 0 2006.173.02:13:27.03#ibcon#about to read 4, iclass 30, count 0 2006.173.02:13:27.03#ibcon#read 4, iclass 30, count 0 2006.173.02:13:27.03#ibcon#about to read 5, iclass 30, count 0 2006.173.02:13:27.03#ibcon#read 5, iclass 30, count 0 2006.173.02:13:27.03#ibcon#about to read 6, iclass 30, count 0 2006.173.02:13:27.03#ibcon#read 6, iclass 30, count 0 2006.173.02:13:27.03#ibcon#end of sib2, iclass 30, count 0 2006.173.02:13:27.03#ibcon#*after write, iclass 30, count 0 2006.173.02:13:27.03#ibcon#*before return 0, iclass 30, count 0 2006.173.02:13:27.03#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.02:13:27.03#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.02:13:27.03#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.02:13:27.03#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.02:13:27.03$vck44/va=2,6 2006.173.02:13:27.03#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.173.02:13:27.03#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.173.02:13:27.03#ibcon#ireg 11 cls_cnt 2 2006.173.02:13:27.03#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.02:13:27.09#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.02:13:27.09#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.02:13:27.09#ibcon#enter wrdev, iclass 32, count 2 2006.173.02:13:27.09#ibcon#first serial, iclass 32, count 2 2006.173.02:13:27.09#ibcon#enter sib2, iclass 32, count 2 2006.173.02:13:27.09#ibcon#flushed, iclass 32, count 2 2006.173.02:13:27.09#ibcon#about to write, iclass 32, count 2 2006.173.02:13:27.09#ibcon#wrote, iclass 32, count 2 2006.173.02:13:27.09#ibcon#about to read 3, iclass 32, count 2 2006.173.02:13:27.11#ibcon#read 3, iclass 32, count 2 2006.173.02:13:27.11#ibcon#about to read 4, iclass 32, count 2 2006.173.02:13:27.11#ibcon#read 4, iclass 32, count 2 2006.173.02:13:27.11#ibcon#about to read 5, iclass 32, count 2 2006.173.02:13:27.11#ibcon#read 5, iclass 32, count 2 2006.173.02:13:27.11#ibcon#about to read 6, iclass 32, count 2 2006.173.02:13:27.11#ibcon#read 6, iclass 32, count 2 2006.173.02:13:27.11#ibcon#end of sib2, iclass 32, count 2 2006.173.02:13:27.11#ibcon#*mode == 0, iclass 32, count 2 2006.173.02:13:27.11#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.173.02:13:27.11#ibcon#[25=AT02-06\r\n] 2006.173.02:13:27.11#ibcon#*before write, iclass 32, count 2 2006.173.02:13:27.11#ibcon#enter sib2, iclass 32, count 2 2006.173.02:13:27.11#ibcon#flushed, iclass 32, count 2 2006.173.02:13:27.11#ibcon#about to write, iclass 32, count 2 2006.173.02:13:27.11#ibcon#wrote, iclass 32, count 2 2006.173.02:13:27.11#ibcon#about to read 3, iclass 32, count 2 2006.173.02:13:27.14#ibcon#read 3, iclass 32, count 2 2006.173.02:13:27.14#ibcon#about to read 4, iclass 32, count 2 2006.173.02:13:27.14#ibcon#read 4, iclass 32, count 2 2006.173.02:13:27.14#ibcon#about to read 5, iclass 32, count 2 2006.173.02:13:27.14#ibcon#read 5, iclass 32, count 2 2006.173.02:13:27.14#ibcon#about to read 6, iclass 32, count 2 2006.173.02:13:27.14#ibcon#read 6, iclass 32, count 2 2006.173.02:13:27.14#ibcon#end of sib2, iclass 32, count 2 2006.173.02:13:27.14#ibcon#*after write, iclass 32, count 2 2006.173.02:13:27.14#ibcon#*before return 0, iclass 32, count 2 2006.173.02:13:27.14#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.02:13:27.14#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.173.02:13:27.14#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.173.02:13:27.14#ibcon#ireg 7 cls_cnt 0 2006.173.02:13:27.14#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.02:13:27.26#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.02:13:27.26#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.02:13:27.26#ibcon#enter wrdev, iclass 32, count 0 2006.173.02:13:27.26#ibcon#first serial, iclass 32, count 0 2006.173.02:13:27.26#ibcon#enter sib2, iclass 32, count 0 2006.173.02:13:27.26#ibcon#flushed, iclass 32, count 0 2006.173.02:13:27.26#ibcon#about to write, iclass 32, count 0 2006.173.02:13:27.26#ibcon#wrote, iclass 32, count 0 2006.173.02:13:27.26#ibcon#about to read 3, iclass 32, count 0 2006.173.02:13:27.28#ibcon#read 3, iclass 32, count 0 2006.173.02:13:27.28#ibcon#about to read 4, iclass 32, count 0 2006.173.02:13:27.28#ibcon#read 4, iclass 32, count 0 2006.173.02:13:27.28#ibcon#about to read 5, iclass 32, count 0 2006.173.02:13:27.28#ibcon#read 5, iclass 32, count 0 2006.173.02:13:27.28#ibcon#about to read 6, iclass 32, count 0 2006.173.02:13:27.28#ibcon#read 6, iclass 32, count 0 2006.173.02:13:27.28#ibcon#end of sib2, iclass 32, count 0 2006.173.02:13:27.28#ibcon#*mode == 0, iclass 32, count 0 2006.173.02:13:27.28#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.02:13:27.28#ibcon#[25=USB\r\n] 2006.173.02:13:27.28#ibcon#*before write, iclass 32, count 0 2006.173.02:13:27.28#ibcon#enter sib2, iclass 32, count 0 2006.173.02:13:27.28#ibcon#flushed, iclass 32, count 0 2006.173.02:13:27.28#ibcon#about to write, iclass 32, count 0 2006.173.02:13:27.28#ibcon#wrote, iclass 32, count 0 2006.173.02:13:27.28#ibcon#about to read 3, iclass 32, count 0 2006.173.02:13:27.31#ibcon#read 3, iclass 32, count 0 2006.173.02:13:27.31#ibcon#about to read 4, iclass 32, count 0 2006.173.02:13:27.31#ibcon#read 4, iclass 32, count 0 2006.173.02:13:27.31#ibcon#about to read 5, iclass 32, count 0 2006.173.02:13:27.31#ibcon#read 5, iclass 32, count 0 2006.173.02:13:27.31#ibcon#about to read 6, iclass 32, count 0 2006.173.02:13:27.31#ibcon#read 6, iclass 32, count 0 2006.173.02:13:27.31#ibcon#end of sib2, iclass 32, count 0 2006.173.02:13:27.31#ibcon#*after write, iclass 32, count 0 2006.173.02:13:27.31#ibcon#*before return 0, iclass 32, count 0 2006.173.02:13:27.31#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.02:13:27.31#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.173.02:13:27.31#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.02:13:27.31#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.02:13:27.31$vck44/valo=3,564.99 2006.173.02:13:27.31#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.02:13:27.31#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.02:13:27.31#ibcon#ireg 17 cls_cnt 0 2006.173.02:13:27.31#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.02:13:27.31#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.02:13:27.31#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.02:13:27.31#ibcon#enter wrdev, iclass 34, count 0 2006.173.02:13:27.31#ibcon#first serial, iclass 34, count 0 2006.173.02:13:27.31#ibcon#enter sib2, iclass 34, count 0 2006.173.02:13:27.31#ibcon#flushed, iclass 34, count 0 2006.173.02:13:27.31#ibcon#about to write, iclass 34, count 0 2006.173.02:13:27.31#ibcon#wrote, iclass 34, count 0 2006.173.02:13:27.31#ibcon#about to read 3, iclass 34, count 0 2006.173.02:13:27.34#ibcon#read 3, iclass 34, count 0 2006.173.02:13:27.34#ibcon#about to read 4, iclass 34, count 0 2006.173.02:13:27.34#ibcon#read 4, iclass 34, count 0 2006.173.02:13:27.34#ibcon#about to read 5, iclass 34, count 0 2006.173.02:13:27.34#ibcon#read 5, iclass 34, count 0 2006.173.02:13:27.34#ibcon#about to read 6, iclass 34, count 0 2006.173.02:13:27.34#ibcon#read 6, iclass 34, count 0 2006.173.02:13:27.34#ibcon#end of sib2, iclass 34, count 0 2006.173.02:13:27.34#ibcon#*mode == 0, iclass 34, count 0 2006.173.02:13:27.34#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.02:13:27.34#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.02:13:27.34#ibcon#*before write, iclass 34, count 0 2006.173.02:13:27.34#ibcon#enter sib2, iclass 34, count 0 2006.173.02:13:27.34#ibcon#flushed, iclass 34, count 0 2006.173.02:13:27.34#ibcon#about to write, iclass 34, count 0 2006.173.02:13:27.34#ibcon#wrote, iclass 34, count 0 2006.173.02:13:27.34#ibcon#about to read 3, iclass 34, count 0 2006.173.02:13:27.38#ibcon#read 3, iclass 34, count 0 2006.173.02:13:27.38#ibcon#about to read 4, iclass 34, count 0 2006.173.02:13:27.38#ibcon#read 4, iclass 34, count 0 2006.173.02:13:27.38#ibcon#about to read 5, iclass 34, count 0 2006.173.02:13:27.38#ibcon#read 5, iclass 34, count 0 2006.173.02:13:27.38#ibcon#about to read 6, iclass 34, count 0 2006.173.02:13:27.38#ibcon#read 6, iclass 34, count 0 2006.173.02:13:27.38#ibcon#end of sib2, iclass 34, count 0 2006.173.02:13:27.38#ibcon#*after write, iclass 34, count 0 2006.173.02:13:27.38#ibcon#*before return 0, iclass 34, count 0 2006.173.02:13:27.38#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.02:13:27.38#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.02:13:27.38#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.02:13:27.38#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.02:13:27.38$vck44/va=3,5 2006.173.02:13:27.38#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.02:13:27.38#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.02:13:27.38#ibcon#ireg 11 cls_cnt 2 2006.173.02:13:27.38#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.02:13:27.43#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.02:13:27.43#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.02:13:27.43#ibcon#enter wrdev, iclass 36, count 2 2006.173.02:13:27.43#ibcon#first serial, iclass 36, count 2 2006.173.02:13:27.43#ibcon#enter sib2, iclass 36, count 2 2006.173.02:13:27.43#ibcon#flushed, iclass 36, count 2 2006.173.02:13:27.43#ibcon#about to write, iclass 36, count 2 2006.173.02:13:27.43#ibcon#wrote, iclass 36, count 2 2006.173.02:13:27.43#ibcon#about to read 3, iclass 36, count 2 2006.173.02:13:27.46#ibcon#read 3, iclass 36, count 2 2006.173.02:13:27.46#ibcon#about to read 4, iclass 36, count 2 2006.173.02:13:27.46#ibcon#read 4, iclass 36, count 2 2006.173.02:13:27.46#ibcon#about to read 5, iclass 36, count 2 2006.173.02:13:27.46#ibcon#read 5, iclass 36, count 2 2006.173.02:13:27.46#ibcon#about to read 6, iclass 36, count 2 2006.173.02:13:27.46#ibcon#read 6, iclass 36, count 2 2006.173.02:13:27.46#ibcon#end of sib2, iclass 36, count 2 2006.173.02:13:27.46#ibcon#*mode == 0, iclass 36, count 2 2006.173.02:13:27.46#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.02:13:27.46#ibcon#[25=AT03-05\r\n] 2006.173.02:13:27.46#ibcon#*before write, iclass 36, count 2 2006.173.02:13:27.46#ibcon#enter sib2, iclass 36, count 2 2006.173.02:13:27.46#ibcon#flushed, iclass 36, count 2 2006.173.02:13:27.46#ibcon#about to write, iclass 36, count 2 2006.173.02:13:27.46#ibcon#wrote, iclass 36, count 2 2006.173.02:13:27.46#ibcon#about to read 3, iclass 36, count 2 2006.173.02:13:27.49#ibcon#read 3, iclass 36, count 2 2006.173.02:13:27.49#ibcon#about to read 4, iclass 36, count 2 2006.173.02:13:27.49#ibcon#read 4, iclass 36, count 2 2006.173.02:13:27.49#ibcon#about to read 5, iclass 36, count 2 2006.173.02:13:27.49#ibcon#read 5, iclass 36, count 2 2006.173.02:13:27.49#ibcon#about to read 6, iclass 36, count 2 2006.173.02:13:27.49#ibcon#read 6, iclass 36, count 2 2006.173.02:13:27.49#ibcon#end of sib2, iclass 36, count 2 2006.173.02:13:27.49#ibcon#*after write, iclass 36, count 2 2006.173.02:13:27.49#ibcon#*before return 0, iclass 36, count 2 2006.173.02:13:27.49#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.02:13:27.49#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.02:13:27.49#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.02:13:27.49#ibcon#ireg 7 cls_cnt 0 2006.173.02:13:27.49#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.02:13:27.61#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.02:13:27.61#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.02:13:27.61#ibcon#enter wrdev, iclass 36, count 0 2006.173.02:13:27.61#ibcon#first serial, iclass 36, count 0 2006.173.02:13:27.61#ibcon#enter sib2, iclass 36, count 0 2006.173.02:13:27.61#ibcon#flushed, iclass 36, count 0 2006.173.02:13:27.61#ibcon#about to write, iclass 36, count 0 2006.173.02:13:27.61#ibcon#wrote, iclass 36, count 0 2006.173.02:13:27.61#ibcon#about to read 3, iclass 36, count 0 2006.173.02:13:27.63#ibcon#read 3, iclass 36, count 0 2006.173.02:13:27.63#ibcon#about to read 4, iclass 36, count 0 2006.173.02:13:27.63#ibcon#read 4, iclass 36, count 0 2006.173.02:13:27.63#ibcon#about to read 5, iclass 36, count 0 2006.173.02:13:27.63#ibcon#read 5, iclass 36, count 0 2006.173.02:13:27.63#ibcon#about to read 6, iclass 36, count 0 2006.173.02:13:27.63#ibcon#read 6, iclass 36, count 0 2006.173.02:13:27.63#ibcon#end of sib2, iclass 36, count 0 2006.173.02:13:27.63#ibcon#*mode == 0, iclass 36, count 0 2006.173.02:13:27.63#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.02:13:27.63#ibcon#[25=USB\r\n] 2006.173.02:13:27.63#ibcon#*before write, iclass 36, count 0 2006.173.02:13:27.63#ibcon#enter sib2, iclass 36, count 0 2006.173.02:13:27.63#ibcon#flushed, iclass 36, count 0 2006.173.02:13:27.63#ibcon#about to write, iclass 36, count 0 2006.173.02:13:27.63#ibcon#wrote, iclass 36, count 0 2006.173.02:13:27.63#ibcon#about to read 3, iclass 36, count 0 2006.173.02:13:27.66#ibcon#read 3, iclass 36, count 0 2006.173.02:13:27.66#ibcon#about to read 4, iclass 36, count 0 2006.173.02:13:27.66#ibcon#read 4, iclass 36, count 0 2006.173.02:13:27.66#ibcon#about to read 5, iclass 36, count 0 2006.173.02:13:27.66#ibcon#read 5, iclass 36, count 0 2006.173.02:13:27.66#ibcon#about to read 6, iclass 36, count 0 2006.173.02:13:27.66#ibcon#read 6, iclass 36, count 0 2006.173.02:13:27.66#ibcon#end of sib2, iclass 36, count 0 2006.173.02:13:27.66#ibcon#*after write, iclass 36, count 0 2006.173.02:13:27.66#ibcon#*before return 0, iclass 36, count 0 2006.173.02:13:27.66#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.02:13:27.66#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.02:13:27.66#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.02:13:27.66#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.02:13:27.66$vck44/valo=4,624.99 2006.173.02:13:27.66#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.02:13:27.66#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.02:13:27.66#ibcon#ireg 17 cls_cnt 0 2006.173.02:13:27.66#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.02:13:27.66#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.02:13:27.66#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.02:13:27.66#ibcon#enter wrdev, iclass 38, count 0 2006.173.02:13:27.66#ibcon#first serial, iclass 38, count 0 2006.173.02:13:27.66#ibcon#enter sib2, iclass 38, count 0 2006.173.02:13:27.66#ibcon#flushed, iclass 38, count 0 2006.173.02:13:27.66#ibcon#about to write, iclass 38, count 0 2006.173.02:13:27.66#ibcon#wrote, iclass 38, count 0 2006.173.02:13:27.66#ibcon#about to read 3, iclass 38, count 0 2006.173.02:13:27.68#ibcon#read 3, iclass 38, count 0 2006.173.02:13:27.68#ibcon#about to read 4, iclass 38, count 0 2006.173.02:13:27.68#ibcon#read 4, iclass 38, count 0 2006.173.02:13:27.68#ibcon#about to read 5, iclass 38, count 0 2006.173.02:13:27.68#ibcon#read 5, iclass 38, count 0 2006.173.02:13:27.68#ibcon#about to read 6, iclass 38, count 0 2006.173.02:13:27.68#ibcon#read 6, iclass 38, count 0 2006.173.02:13:27.68#ibcon#end of sib2, iclass 38, count 0 2006.173.02:13:27.68#ibcon#*mode == 0, iclass 38, count 0 2006.173.02:13:27.68#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.02:13:27.68#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.02:13:27.68#ibcon#*before write, iclass 38, count 0 2006.173.02:13:27.68#ibcon#enter sib2, iclass 38, count 0 2006.173.02:13:27.68#ibcon#flushed, iclass 38, count 0 2006.173.02:13:27.68#ibcon#about to write, iclass 38, count 0 2006.173.02:13:27.68#ibcon#wrote, iclass 38, count 0 2006.173.02:13:27.68#ibcon#about to read 3, iclass 38, count 0 2006.173.02:13:27.72#ibcon#read 3, iclass 38, count 0 2006.173.02:13:27.72#ibcon#about to read 4, iclass 38, count 0 2006.173.02:13:27.72#ibcon#read 4, iclass 38, count 0 2006.173.02:13:27.72#ibcon#about to read 5, iclass 38, count 0 2006.173.02:13:27.72#ibcon#read 5, iclass 38, count 0 2006.173.02:13:27.72#ibcon#about to read 6, iclass 38, count 0 2006.173.02:13:27.72#ibcon#read 6, iclass 38, count 0 2006.173.02:13:27.72#ibcon#end of sib2, iclass 38, count 0 2006.173.02:13:27.72#ibcon#*after write, iclass 38, count 0 2006.173.02:13:27.72#ibcon#*before return 0, iclass 38, count 0 2006.173.02:13:27.72#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.02:13:27.72#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.02:13:27.72#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.02:13:27.72#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.02:13:27.72$vck44/va=4,6 2006.173.02:13:27.72#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.02:13:27.72#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.02:13:27.72#ibcon#ireg 11 cls_cnt 2 2006.173.02:13:27.72#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.02:13:27.78#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.02:13:27.78#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.02:13:27.78#ibcon#enter wrdev, iclass 40, count 2 2006.173.02:13:27.78#ibcon#first serial, iclass 40, count 2 2006.173.02:13:27.78#ibcon#enter sib2, iclass 40, count 2 2006.173.02:13:27.78#ibcon#flushed, iclass 40, count 2 2006.173.02:13:27.78#ibcon#about to write, iclass 40, count 2 2006.173.02:13:27.78#ibcon#wrote, iclass 40, count 2 2006.173.02:13:27.78#ibcon#about to read 3, iclass 40, count 2 2006.173.02:13:27.80#ibcon#read 3, iclass 40, count 2 2006.173.02:13:27.80#ibcon#about to read 4, iclass 40, count 2 2006.173.02:13:27.80#ibcon#read 4, iclass 40, count 2 2006.173.02:13:27.80#ibcon#about to read 5, iclass 40, count 2 2006.173.02:13:27.80#ibcon#read 5, iclass 40, count 2 2006.173.02:13:27.80#ibcon#about to read 6, iclass 40, count 2 2006.173.02:13:27.80#ibcon#read 6, iclass 40, count 2 2006.173.02:13:27.80#ibcon#end of sib2, iclass 40, count 2 2006.173.02:13:27.80#ibcon#*mode == 0, iclass 40, count 2 2006.173.02:13:27.80#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.02:13:27.80#ibcon#[25=AT04-06\r\n] 2006.173.02:13:27.80#ibcon#*before write, iclass 40, count 2 2006.173.02:13:27.80#ibcon#enter sib2, iclass 40, count 2 2006.173.02:13:27.80#ibcon#flushed, iclass 40, count 2 2006.173.02:13:27.80#ibcon#about to write, iclass 40, count 2 2006.173.02:13:27.80#ibcon#wrote, iclass 40, count 2 2006.173.02:13:27.80#ibcon#about to read 3, iclass 40, count 2 2006.173.02:13:27.83#ibcon#read 3, iclass 40, count 2 2006.173.02:13:27.83#ibcon#about to read 4, iclass 40, count 2 2006.173.02:13:27.83#ibcon#read 4, iclass 40, count 2 2006.173.02:13:27.83#ibcon#about to read 5, iclass 40, count 2 2006.173.02:13:27.83#ibcon#read 5, iclass 40, count 2 2006.173.02:13:27.83#ibcon#about to read 6, iclass 40, count 2 2006.173.02:13:27.83#ibcon#read 6, iclass 40, count 2 2006.173.02:13:27.83#ibcon#end of sib2, iclass 40, count 2 2006.173.02:13:27.83#ibcon#*after write, iclass 40, count 2 2006.173.02:13:27.83#ibcon#*before return 0, iclass 40, count 2 2006.173.02:13:27.83#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.02:13:27.83#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.02:13:27.83#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.02:13:27.83#ibcon#ireg 7 cls_cnt 0 2006.173.02:13:27.83#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.02:13:27.95#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.02:13:27.95#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.02:13:27.95#ibcon#enter wrdev, iclass 40, count 0 2006.173.02:13:27.95#ibcon#first serial, iclass 40, count 0 2006.173.02:13:27.95#ibcon#enter sib2, iclass 40, count 0 2006.173.02:13:27.95#ibcon#flushed, iclass 40, count 0 2006.173.02:13:27.95#ibcon#about to write, iclass 40, count 0 2006.173.02:13:27.95#ibcon#wrote, iclass 40, count 0 2006.173.02:13:27.95#ibcon#about to read 3, iclass 40, count 0 2006.173.02:13:27.97#ibcon#read 3, iclass 40, count 0 2006.173.02:13:27.97#ibcon#about to read 4, iclass 40, count 0 2006.173.02:13:27.97#ibcon#read 4, iclass 40, count 0 2006.173.02:13:27.97#ibcon#about to read 5, iclass 40, count 0 2006.173.02:13:27.97#ibcon#read 5, iclass 40, count 0 2006.173.02:13:27.97#ibcon#about to read 6, iclass 40, count 0 2006.173.02:13:27.97#ibcon#read 6, iclass 40, count 0 2006.173.02:13:27.97#ibcon#end of sib2, iclass 40, count 0 2006.173.02:13:27.97#ibcon#*mode == 0, iclass 40, count 0 2006.173.02:13:27.97#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.02:13:27.97#ibcon#[25=USB\r\n] 2006.173.02:13:27.97#ibcon#*before write, iclass 40, count 0 2006.173.02:13:27.97#ibcon#enter sib2, iclass 40, count 0 2006.173.02:13:27.97#ibcon#flushed, iclass 40, count 0 2006.173.02:13:27.97#ibcon#about to write, iclass 40, count 0 2006.173.02:13:27.97#ibcon#wrote, iclass 40, count 0 2006.173.02:13:27.97#ibcon#about to read 3, iclass 40, count 0 2006.173.02:13:28.00#ibcon#read 3, iclass 40, count 0 2006.173.02:13:28.00#ibcon#about to read 4, iclass 40, count 0 2006.173.02:13:28.00#ibcon#read 4, iclass 40, count 0 2006.173.02:13:28.00#ibcon#about to read 5, iclass 40, count 0 2006.173.02:13:28.00#ibcon#read 5, iclass 40, count 0 2006.173.02:13:28.00#ibcon#about to read 6, iclass 40, count 0 2006.173.02:13:28.00#ibcon#read 6, iclass 40, count 0 2006.173.02:13:28.00#ibcon#end of sib2, iclass 40, count 0 2006.173.02:13:28.00#ibcon#*after write, iclass 40, count 0 2006.173.02:13:28.00#ibcon#*before return 0, iclass 40, count 0 2006.173.02:13:28.00#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.02:13:28.00#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.02:13:28.00#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.02:13:28.00#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.02:13:28.00$vck44/valo=5,734.99 2006.173.02:13:28.00#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.02:13:28.00#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.02:13:28.00#ibcon#ireg 17 cls_cnt 0 2006.173.02:13:28.00#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.02:13:28.00#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.02:13:28.00#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.02:13:28.00#ibcon#enter wrdev, iclass 4, count 0 2006.173.02:13:28.00#ibcon#first serial, iclass 4, count 0 2006.173.02:13:28.00#ibcon#enter sib2, iclass 4, count 0 2006.173.02:13:28.00#ibcon#flushed, iclass 4, count 0 2006.173.02:13:28.00#ibcon#about to write, iclass 4, count 0 2006.173.02:13:28.00#ibcon#wrote, iclass 4, count 0 2006.173.02:13:28.00#ibcon#about to read 3, iclass 4, count 0 2006.173.02:13:28.02#ibcon#read 3, iclass 4, count 0 2006.173.02:13:28.02#ibcon#about to read 4, iclass 4, count 0 2006.173.02:13:28.02#ibcon#read 4, iclass 4, count 0 2006.173.02:13:28.02#ibcon#about to read 5, iclass 4, count 0 2006.173.02:13:28.02#ibcon#read 5, iclass 4, count 0 2006.173.02:13:28.02#ibcon#about to read 6, iclass 4, count 0 2006.173.02:13:28.02#ibcon#read 6, iclass 4, count 0 2006.173.02:13:28.02#ibcon#end of sib2, iclass 4, count 0 2006.173.02:13:28.02#ibcon#*mode == 0, iclass 4, count 0 2006.173.02:13:28.02#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.02:13:28.02#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.02:13:28.02#ibcon#*before write, iclass 4, count 0 2006.173.02:13:28.02#ibcon#enter sib2, iclass 4, count 0 2006.173.02:13:28.02#ibcon#flushed, iclass 4, count 0 2006.173.02:13:28.02#ibcon#about to write, iclass 4, count 0 2006.173.02:13:28.02#ibcon#wrote, iclass 4, count 0 2006.173.02:13:28.02#ibcon#about to read 3, iclass 4, count 0 2006.173.02:13:28.06#ibcon#read 3, iclass 4, count 0 2006.173.02:13:28.06#ibcon#about to read 4, iclass 4, count 0 2006.173.02:13:28.06#ibcon#read 4, iclass 4, count 0 2006.173.02:13:28.06#ibcon#about to read 5, iclass 4, count 0 2006.173.02:13:28.06#ibcon#read 5, iclass 4, count 0 2006.173.02:13:28.06#ibcon#about to read 6, iclass 4, count 0 2006.173.02:13:28.06#ibcon#read 6, iclass 4, count 0 2006.173.02:13:28.06#ibcon#end of sib2, iclass 4, count 0 2006.173.02:13:28.06#ibcon#*after write, iclass 4, count 0 2006.173.02:13:28.06#ibcon#*before return 0, iclass 4, count 0 2006.173.02:13:28.06#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.02:13:28.06#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.02:13:28.06#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.02:13:28.06#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.02:13:28.06$vck44/va=5,4 2006.173.02:13:28.06#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.02:13:28.06#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.02:13:28.06#ibcon#ireg 11 cls_cnt 2 2006.173.02:13:28.06#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.02:13:28.12#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.02:13:28.12#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.02:13:28.12#ibcon#enter wrdev, iclass 6, count 2 2006.173.02:13:28.12#ibcon#first serial, iclass 6, count 2 2006.173.02:13:28.12#ibcon#enter sib2, iclass 6, count 2 2006.173.02:13:28.12#ibcon#flushed, iclass 6, count 2 2006.173.02:13:28.12#ibcon#about to write, iclass 6, count 2 2006.173.02:13:28.12#ibcon#wrote, iclass 6, count 2 2006.173.02:13:28.12#ibcon#about to read 3, iclass 6, count 2 2006.173.02:13:28.14#ibcon#read 3, iclass 6, count 2 2006.173.02:13:28.14#ibcon#about to read 4, iclass 6, count 2 2006.173.02:13:28.14#ibcon#read 4, iclass 6, count 2 2006.173.02:13:28.14#ibcon#about to read 5, iclass 6, count 2 2006.173.02:13:28.14#ibcon#read 5, iclass 6, count 2 2006.173.02:13:28.14#ibcon#about to read 6, iclass 6, count 2 2006.173.02:13:28.14#ibcon#read 6, iclass 6, count 2 2006.173.02:13:28.14#ibcon#end of sib2, iclass 6, count 2 2006.173.02:13:28.14#ibcon#*mode == 0, iclass 6, count 2 2006.173.02:13:28.14#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.02:13:28.14#ibcon#[25=AT05-04\r\n] 2006.173.02:13:28.14#ibcon#*before write, iclass 6, count 2 2006.173.02:13:28.14#ibcon#enter sib2, iclass 6, count 2 2006.173.02:13:28.14#ibcon#flushed, iclass 6, count 2 2006.173.02:13:28.14#ibcon#about to write, iclass 6, count 2 2006.173.02:13:28.14#ibcon#wrote, iclass 6, count 2 2006.173.02:13:28.14#ibcon#about to read 3, iclass 6, count 2 2006.173.02:13:28.17#ibcon#read 3, iclass 6, count 2 2006.173.02:13:28.17#ibcon#about to read 4, iclass 6, count 2 2006.173.02:13:28.17#ibcon#read 4, iclass 6, count 2 2006.173.02:13:28.17#ibcon#about to read 5, iclass 6, count 2 2006.173.02:13:28.17#ibcon#read 5, iclass 6, count 2 2006.173.02:13:28.17#ibcon#about to read 6, iclass 6, count 2 2006.173.02:13:28.17#ibcon#read 6, iclass 6, count 2 2006.173.02:13:28.17#ibcon#end of sib2, iclass 6, count 2 2006.173.02:13:28.17#ibcon#*after write, iclass 6, count 2 2006.173.02:13:28.17#ibcon#*before return 0, iclass 6, count 2 2006.173.02:13:28.17#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.02:13:28.17#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.02:13:28.17#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.02:13:28.17#ibcon#ireg 7 cls_cnt 0 2006.173.02:13:28.17#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.02:13:28.29#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.02:13:28.29#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.02:13:28.29#ibcon#enter wrdev, iclass 6, count 0 2006.173.02:13:28.29#ibcon#first serial, iclass 6, count 0 2006.173.02:13:28.29#ibcon#enter sib2, iclass 6, count 0 2006.173.02:13:28.29#ibcon#flushed, iclass 6, count 0 2006.173.02:13:28.29#ibcon#about to write, iclass 6, count 0 2006.173.02:13:28.29#ibcon#wrote, iclass 6, count 0 2006.173.02:13:28.29#ibcon#about to read 3, iclass 6, count 0 2006.173.02:13:28.31#ibcon#read 3, iclass 6, count 0 2006.173.02:13:28.31#ibcon#about to read 4, iclass 6, count 0 2006.173.02:13:28.31#ibcon#read 4, iclass 6, count 0 2006.173.02:13:28.31#ibcon#about to read 5, iclass 6, count 0 2006.173.02:13:28.31#ibcon#read 5, iclass 6, count 0 2006.173.02:13:28.31#ibcon#about to read 6, iclass 6, count 0 2006.173.02:13:28.31#ibcon#read 6, iclass 6, count 0 2006.173.02:13:28.31#ibcon#end of sib2, iclass 6, count 0 2006.173.02:13:28.31#ibcon#*mode == 0, iclass 6, count 0 2006.173.02:13:28.31#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.02:13:28.31#ibcon#[25=USB\r\n] 2006.173.02:13:28.31#ibcon#*before write, iclass 6, count 0 2006.173.02:13:28.31#ibcon#enter sib2, iclass 6, count 0 2006.173.02:13:28.31#ibcon#flushed, iclass 6, count 0 2006.173.02:13:28.31#ibcon#about to write, iclass 6, count 0 2006.173.02:13:28.31#ibcon#wrote, iclass 6, count 0 2006.173.02:13:28.31#ibcon#about to read 3, iclass 6, count 0 2006.173.02:13:28.34#ibcon#read 3, iclass 6, count 0 2006.173.02:13:28.34#ibcon#about to read 4, iclass 6, count 0 2006.173.02:13:28.34#ibcon#read 4, iclass 6, count 0 2006.173.02:13:28.34#ibcon#about to read 5, iclass 6, count 0 2006.173.02:13:28.34#ibcon#read 5, iclass 6, count 0 2006.173.02:13:28.34#ibcon#about to read 6, iclass 6, count 0 2006.173.02:13:28.34#ibcon#read 6, iclass 6, count 0 2006.173.02:13:28.34#ibcon#end of sib2, iclass 6, count 0 2006.173.02:13:28.34#ibcon#*after write, iclass 6, count 0 2006.173.02:13:28.34#ibcon#*before return 0, iclass 6, count 0 2006.173.02:13:28.34#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.02:13:28.34#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.02:13:28.34#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.02:13:28.34#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.02:13:28.34$vck44/valo=6,814.99 2006.173.02:13:28.34#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.02:13:28.34#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.02:13:28.34#ibcon#ireg 17 cls_cnt 0 2006.173.02:13:28.34#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.02:13:28.34#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.02:13:28.34#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.02:13:28.34#ibcon#enter wrdev, iclass 10, count 0 2006.173.02:13:28.34#ibcon#first serial, iclass 10, count 0 2006.173.02:13:28.34#ibcon#enter sib2, iclass 10, count 0 2006.173.02:13:28.34#ibcon#flushed, iclass 10, count 0 2006.173.02:13:28.34#ibcon#about to write, iclass 10, count 0 2006.173.02:13:28.34#ibcon#wrote, iclass 10, count 0 2006.173.02:13:28.34#ibcon#about to read 3, iclass 10, count 0 2006.173.02:13:28.37#ibcon#read 3, iclass 10, count 0 2006.173.02:13:28.37#ibcon#about to read 4, iclass 10, count 0 2006.173.02:13:28.37#ibcon#read 4, iclass 10, count 0 2006.173.02:13:28.37#ibcon#about to read 5, iclass 10, count 0 2006.173.02:13:28.37#ibcon#read 5, iclass 10, count 0 2006.173.02:13:28.37#ibcon#about to read 6, iclass 10, count 0 2006.173.02:13:28.37#ibcon#read 6, iclass 10, count 0 2006.173.02:13:28.37#ibcon#end of sib2, iclass 10, count 0 2006.173.02:13:28.37#ibcon#*mode == 0, iclass 10, count 0 2006.173.02:13:28.37#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.02:13:28.37#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.02:13:28.37#ibcon#*before write, iclass 10, count 0 2006.173.02:13:28.37#ibcon#enter sib2, iclass 10, count 0 2006.173.02:13:28.37#ibcon#flushed, iclass 10, count 0 2006.173.02:13:28.37#ibcon#about to write, iclass 10, count 0 2006.173.02:13:28.37#ibcon#wrote, iclass 10, count 0 2006.173.02:13:28.37#ibcon#about to read 3, iclass 10, count 0 2006.173.02:13:28.41#ibcon#read 3, iclass 10, count 0 2006.173.02:13:28.41#ibcon#about to read 4, iclass 10, count 0 2006.173.02:13:28.41#ibcon#read 4, iclass 10, count 0 2006.173.02:13:28.41#ibcon#about to read 5, iclass 10, count 0 2006.173.02:13:28.41#ibcon#read 5, iclass 10, count 0 2006.173.02:13:28.41#ibcon#about to read 6, iclass 10, count 0 2006.173.02:13:28.41#ibcon#read 6, iclass 10, count 0 2006.173.02:13:28.41#ibcon#end of sib2, iclass 10, count 0 2006.173.02:13:28.41#ibcon#*after write, iclass 10, count 0 2006.173.02:13:28.41#ibcon#*before return 0, iclass 10, count 0 2006.173.02:13:28.41#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.02:13:28.41#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.02:13:28.41#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.02:13:28.41#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.02:13:28.41$vck44/va=6,3 2006.173.02:13:28.41#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.02:13:28.41#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.02:13:28.41#ibcon#ireg 11 cls_cnt 2 2006.173.02:13:28.41#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.02:13:28.46#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.02:13:28.46#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.02:13:28.46#ibcon#enter wrdev, iclass 12, count 2 2006.173.02:13:28.46#ibcon#first serial, iclass 12, count 2 2006.173.02:13:28.46#ibcon#enter sib2, iclass 12, count 2 2006.173.02:13:28.46#ibcon#flushed, iclass 12, count 2 2006.173.02:13:28.46#ibcon#about to write, iclass 12, count 2 2006.173.02:13:28.46#ibcon#wrote, iclass 12, count 2 2006.173.02:13:28.46#ibcon#about to read 3, iclass 12, count 2 2006.173.02:13:28.48#ibcon#read 3, iclass 12, count 2 2006.173.02:13:28.48#ibcon#about to read 4, iclass 12, count 2 2006.173.02:13:28.48#ibcon#read 4, iclass 12, count 2 2006.173.02:13:28.48#ibcon#about to read 5, iclass 12, count 2 2006.173.02:13:28.48#ibcon#read 5, iclass 12, count 2 2006.173.02:13:28.48#ibcon#about to read 6, iclass 12, count 2 2006.173.02:13:28.48#ibcon#read 6, iclass 12, count 2 2006.173.02:13:28.48#ibcon#end of sib2, iclass 12, count 2 2006.173.02:13:28.48#ibcon#*mode == 0, iclass 12, count 2 2006.173.02:13:28.48#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.02:13:28.48#ibcon#[25=AT06-03\r\n] 2006.173.02:13:28.48#ibcon#*before write, iclass 12, count 2 2006.173.02:13:28.48#ibcon#enter sib2, iclass 12, count 2 2006.173.02:13:28.48#ibcon#flushed, iclass 12, count 2 2006.173.02:13:28.48#ibcon#about to write, iclass 12, count 2 2006.173.02:13:28.48#ibcon#wrote, iclass 12, count 2 2006.173.02:13:28.48#ibcon#about to read 3, iclass 12, count 2 2006.173.02:13:28.51#ibcon#read 3, iclass 12, count 2 2006.173.02:13:28.51#ibcon#about to read 4, iclass 12, count 2 2006.173.02:13:28.51#ibcon#read 4, iclass 12, count 2 2006.173.02:13:28.51#ibcon#about to read 5, iclass 12, count 2 2006.173.02:13:28.51#ibcon#read 5, iclass 12, count 2 2006.173.02:13:28.51#ibcon#about to read 6, iclass 12, count 2 2006.173.02:13:28.51#ibcon#read 6, iclass 12, count 2 2006.173.02:13:28.51#ibcon#end of sib2, iclass 12, count 2 2006.173.02:13:28.51#ibcon#*after write, iclass 12, count 2 2006.173.02:13:28.51#ibcon#*before return 0, iclass 12, count 2 2006.173.02:13:28.51#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.02:13:28.51#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.02:13:28.51#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.02:13:28.51#ibcon#ireg 7 cls_cnt 0 2006.173.02:13:28.51#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.02:13:28.63#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.02:13:28.63#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.02:13:28.63#ibcon#enter wrdev, iclass 12, count 0 2006.173.02:13:28.63#ibcon#first serial, iclass 12, count 0 2006.173.02:13:28.63#ibcon#enter sib2, iclass 12, count 0 2006.173.02:13:28.63#ibcon#flushed, iclass 12, count 0 2006.173.02:13:28.63#ibcon#about to write, iclass 12, count 0 2006.173.02:13:28.63#ibcon#wrote, iclass 12, count 0 2006.173.02:13:28.63#ibcon#about to read 3, iclass 12, count 0 2006.173.02:13:28.65#ibcon#read 3, iclass 12, count 0 2006.173.02:13:28.65#ibcon#about to read 4, iclass 12, count 0 2006.173.02:13:28.65#ibcon#read 4, iclass 12, count 0 2006.173.02:13:28.65#ibcon#about to read 5, iclass 12, count 0 2006.173.02:13:28.65#ibcon#read 5, iclass 12, count 0 2006.173.02:13:28.65#ibcon#about to read 6, iclass 12, count 0 2006.173.02:13:28.65#ibcon#read 6, iclass 12, count 0 2006.173.02:13:28.65#ibcon#end of sib2, iclass 12, count 0 2006.173.02:13:28.65#ibcon#*mode == 0, iclass 12, count 0 2006.173.02:13:28.65#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.02:13:28.65#ibcon#[25=USB\r\n] 2006.173.02:13:28.65#ibcon#*before write, iclass 12, count 0 2006.173.02:13:28.65#ibcon#enter sib2, iclass 12, count 0 2006.173.02:13:28.65#ibcon#flushed, iclass 12, count 0 2006.173.02:13:28.65#ibcon#about to write, iclass 12, count 0 2006.173.02:13:28.65#ibcon#wrote, iclass 12, count 0 2006.173.02:13:28.65#ibcon#about to read 3, iclass 12, count 0 2006.173.02:13:28.68#ibcon#read 3, iclass 12, count 0 2006.173.02:13:28.68#ibcon#about to read 4, iclass 12, count 0 2006.173.02:13:28.68#ibcon#read 4, iclass 12, count 0 2006.173.02:13:28.68#ibcon#about to read 5, iclass 12, count 0 2006.173.02:13:28.68#ibcon#read 5, iclass 12, count 0 2006.173.02:13:28.68#ibcon#about to read 6, iclass 12, count 0 2006.173.02:13:28.68#ibcon#read 6, iclass 12, count 0 2006.173.02:13:28.68#ibcon#end of sib2, iclass 12, count 0 2006.173.02:13:28.68#ibcon#*after write, iclass 12, count 0 2006.173.02:13:28.68#ibcon#*before return 0, iclass 12, count 0 2006.173.02:13:28.68#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.02:13:28.68#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.02:13:28.68#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.02:13:28.68#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.02:13:28.68$vck44/valo=7,864.99 2006.173.02:13:28.68#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.02:13:28.68#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.02:13:28.68#ibcon#ireg 17 cls_cnt 0 2006.173.02:13:28.68#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.02:13:28.68#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.02:13:28.68#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.02:13:28.68#ibcon#enter wrdev, iclass 14, count 0 2006.173.02:13:28.68#ibcon#first serial, iclass 14, count 0 2006.173.02:13:28.68#ibcon#enter sib2, iclass 14, count 0 2006.173.02:13:28.68#ibcon#flushed, iclass 14, count 0 2006.173.02:13:28.68#ibcon#about to write, iclass 14, count 0 2006.173.02:13:28.68#ibcon#wrote, iclass 14, count 0 2006.173.02:13:28.68#ibcon#about to read 3, iclass 14, count 0 2006.173.02:13:28.70#ibcon#read 3, iclass 14, count 0 2006.173.02:13:28.70#ibcon#about to read 4, iclass 14, count 0 2006.173.02:13:28.70#ibcon#read 4, iclass 14, count 0 2006.173.02:13:28.70#ibcon#about to read 5, iclass 14, count 0 2006.173.02:13:28.70#ibcon#read 5, iclass 14, count 0 2006.173.02:13:28.70#ibcon#about to read 6, iclass 14, count 0 2006.173.02:13:28.70#ibcon#read 6, iclass 14, count 0 2006.173.02:13:28.70#ibcon#end of sib2, iclass 14, count 0 2006.173.02:13:28.70#ibcon#*mode == 0, iclass 14, count 0 2006.173.02:13:28.70#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.02:13:28.70#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.02:13:28.70#ibcon#*before write, iclass 14, count 0 2006.173.02:13:28.70#ibcon#enter sib2, iclass 14, count 0 2006.173.02:13:28.70#ibcon#flushed, iclass 14, count 0 2006.173.02:13:28.70#ibcon#about to write, iclass 14, count 0 2006.173.02:13:28.70#ibcon#wrote, iclass 14, count 0 2006.173.02:13:28.70#ibcon#about to read 3, iclass 14, count 0 2006.173.02:13:28.74#ibcon#read 3, iclass 14, count 0 2006.173.02:13:28.74#ibcon#about to read 4, iclass 14, count 0 2006.173.02:13:28.74#ibcon#read 4, iclass 14, count 0 2006.173.02:13:28.74#ibcon#about to read 5, iclass 14, count 0 2006.173.02:13:28.74#ibcon#read 5, iclass 14, count 0 2006.173.02:13:28.74#ibcon#about to read 6, iclass 14, count 0 2006.173.02:13:28.74#ibcon#read 6, iclass 14, count 0 2006.173.02:13:28.74#ibcon#end of sib2, iclass 14, count 0 2006.173.02:13:28.74#ibcon#*after write, iclass 14, count 0 2006.173.02:13:28.74#ibcon#*before return 0, iclass 14, count 0 2006.173.02:13:28.74#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.02:13:28.74#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.02:13:28.74#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.02:13:28.74#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.02:13:28.74$vck44/va=7,4 2006.173.02:13:28.74#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.02:13:28.74#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.02:13:28.74#ibcon#ireg 11 cls_cnt 2 2006.173.02:13:28.74#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.02:13:28.80#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.02:13:28.80#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.02:13:28.80#ibcon#enter wrdev, iclass 16, count 2 2006.173.02:13:28.80#ibcon#first serial, iclass 16, count 2 2006.173.02:13:28.80#ibcon#enter sib2, iclass 16, count 2 2006.173.02:13:28.80#ibcon#flushed, iclass 16, count 2 2006.173.02:13:28.80#ibcon#about to write, iclass 16, count 2 2006.173.02:13:28.80#ibcon#wrote, iclass 16, count 2 2006.173.02:13:28.80#ibcon#about to read 3, iclass 16, count 2 2006.173.02:13:28.82#ibcon#read 3, iclass 16, count 2 2006.173.02:13:28.82#ibcon#about to read 4, iclass 16, count 2 2006.173.02:13:28.82#ibcon#read 4, iclass 16, count 2 2006.173.02:13:28.82#ibcon#about to read 5, iclass 16, count 2 2006.173.02:13:28.82#ibcon#read 5, iclass 16, count 2 2006.173.02:13:28.82#ibcon#about to read 6, iclass 16, count 2 2006.173.02:13:28.82#ibcon#read 6, iclass 16, count 2 2006.173.02:13:28.82#ibcon#end of sib2, iclass 16, count 2 2006.173.02:13:28.82#ibcon#*mode == 0, iclass 16, count 2 2006.173.02:13:28.82#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.02:13:28.82#ibcon#[25=AT07-04\r\n] 2006.173.02:13:28.82#ibcon#*before write, iclass 16, count 2 2006.173.02:13:28.82#ibcon#enter sib2, iclass 16, count 2 2006.173.02:13:28.82#ibcon#flushed, iclass 16, count 2 2006.173.02:13:28.82#ibcon#about to write, iclass 16, count 2 2006.173.02:13:28.82#ibcon#wrote, iclass 16, count 2 2006.173.02:13:28.82#ibcon#about to read 3, iclass 16, count 2 2006.173.02:13:28.85#ibcon#read 3, iclass 16, count 2 2006.173.02:13:28.85#ibcon#about to read 4, iclass 16, count 2 2006.173.02:13:28.85#ibcon#read 4, iclass 16, count 2 2006.173.02:13:28.85#ibcon#about to read 5, iclass 16, count 2 2006.173.02:13:28.85#ibcon#read 5, iclass 16, count 2 2006.173.02:13:28.85#ibcon#about to read 6, iclass 16, count 2 2006.173.02:13:28.85#ibcon#read 6, iclass 16, count 2 2006.173.02:13:28.85#ibcon#end of sib2, iclass 16, count 2 2006.173.02:13:28.85#ibcon#*after write, iclass 16, count 2 2006.173.02:13:28.85#ibcon#*before return 0, iclass 16, count 2 2006.173.02:13:28.85#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.02:13:28.85#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.02:13:28.85#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.02:13:28.85#ibcon#ireg 7 cls_cnt 0 2006.173.02:13:28.85#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.02:13:28.97#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.02:13:28.97#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.02:13:28.97#ibcon#enter wrdev, iclass 16, count 0 2006.173.02:13:28.97#ibcon#first serial, iclass 16, count 0 2006.173.02:13:28.97#ibcon#enter sib2, iclass 16, count 0 2006.173.02:13:28.97#ibcon#flushed, iclass 16, count 0 2006.173.02:13:28.97#ibcon#about to write, iclass 16, count 0 2006.173.02:13:28.97#ibcon#wrote, iclass 16, count 0 2006.173.02:13:28.97#ibcon#about to read 3, iclass 16, count 0 2006.173.02:13:28.99#ibcon#read 3, iclass 16, count 0 2006.173.02:13:28.99#ibcon#about to read 4, iclass 16, count 0 2006.173.02:13:28.99#ibcon#read 4, iclass 16, count 0 2006.173.02:13:28.99#ibcon#about to read 5, iclass 16, count 0 2006.173.02:13:28.99#ibcon#read 5, iclass 16, count 0 2006.173.02:13:28.99#ibcon#about to read 6, iclass 16, count 0 2006.173.02:13:28.99#ibcon#read 6, iclass 16, count 0 2006.173.02:13:28.99#ibcon#end of sib2, iclass 16, count 0 2006.173.02:13:28.99#ibcon#*mode == 0, iclass 16, count 0 2006.173.02:13:28.99#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.02:13:28.99#ibcon#[25=USB\r\n] 2006.173.02:13:28.99#ibcon#*before write, iclass 16, count 0 2006.173.02:13:28.99#ibcon#enter sib2, iclass 16, count 0 2006.173.02:13:28.99#ibcon#flushed, iclass 16, count 0 2006.173.02:13:28.99#ibcon#about to write, iclass 16, count 0 2006.173.02:13:28.99#ibcon#wrote, iclass 16, count 0 2006.173.02:13:28.99#ibcon#about to read 3, iclass 16, count 0 2006.173.02:13:29.02#ibcon#read 3, iclass 16, count 0 2006.173.02:13:29.02#ibcon#about to read 4, iclass 16, count 0 2006.173.02:13:29.02#ibcon#read 4, iclass 16, count 0 2006.173.02:13:29.02#ibcon#about to read 5, iclass 16, count 0 2006.173.02:13:29.02#ibcon#read 5, iclass 16, count 0 2006.173.02:13:29.02#ibcon#about to read 6, iclass 16, count 0 2006.173.02:13:29.02#ibcon#read 6, iclass 16, count 0 2006.173.02:13:29.02#ibcon#end of sib2, iclass 16, count 0 2006.173.02:13:29.02#ibcon#*after write, iclass 16, count 0 2006.173.02:13:29.02#ibcon#*before return 0, iclass 16, count 0 2006.173.02:13:29.02#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.02:13:29.02#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.02:13:29.02#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.02:13:29.02#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.02:13:29.02$vck44/valo=8,884.99 2006.173.02:13:29.02#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.02:13:29.02#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.02:13:29.02#ibcon#ireg 17 cls_cnt 0 2006.173.02:13:29.02#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.02:13:29.02#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.02:13:29.02#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.02:13:29.02#ibcon#enter wrdev, iclass 18, count 0 2006.173.02:13:29.02#ibcon#first serial, iclass 18, count 0 2006.173.02:13:29.02#ibcon#enter sib2, iclass 18, count 0 2006.173.02:13:29.02#ibcon#flushed, iclass 18, count 0 2006.173.02:13:29.02#ibcon#about to write, iclass 18, count 0 2006.173.02:13:29.02#ibcon#wrote, iclass 18, count 0 2006.173.02:13:29.02#ibcon#about to read 3, iclass 18, count 0 2006.173.02:13:29.04#ibcon#read 3, iclass 18, count 0 2006.173.02:13:29.04#ibcon#about to read 4, iclass 18, count 0 2006.173.02:13:29.04#ibcon#read 4, iclass 18, count 0 2006.173.02:13:29.04#ibcon#about to read 5, iclass 18, count 0 2006.173.02:13:29.04#ibcon#read 5, iclass 18, count 0 2006.173.02:13:29.04#ibcon#about to read 6, iclass 18, count 0 2006.173.02:13:29.04#ibcon#read 6, iclass 18, count 0 2006.173.02:13:29.04#ibcon#end of sib2, iclass 18, count 0 2006.173.02:13:29.04#ibcon#*mode == 0, iclass 18, count 0 2006.173.02:13:29.04#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.02:13:29.04#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.02:13:29.04#ibcon#*before write, iclass 18, count 0 2006.173.02:13:29.04#ibcon#enter sib2, iclass 18, count 0 2006.173.02:13:29.04#ibcon#flushed, iclass 18, count 0 2006.173.02:13:29.04#ibcon#about to write, iclass 18, count 0 2006.173.02:13:29.04#ibcon#wrote, iclass 18, count 0 2006.173.02:13:29.04#ibcon#about to read 3, iclass 18, count 0 2006.173.02:13:29.08#ibcon#read 3, iclass 18, count 0 2006.173.02:13:29.08#ibcon#about to read 4, iclass 18, count 0 2006.173.02:13:29.08#ibcon#read 4, iclass 18, count 0 2006.173.02:13:29.08#ibcon#about to read 5, iclass 18, count 0 2006.173.02:13:29.08#ibcon#read 5, iclass 18, count 0 2006.173.02:13:29.08#ibcon#about to read 6, iclass 18, count 0 2006.173.02:13:29.08#ibcon#read 6, iclass 18, count 0 2006.173.02:13:29.08#ibcon#end of sib2, iclass 18, count 0 2006.173.02:13:29.08#ibcon#*after write, iclass 18, count 0 2006.173.02:13:29.08#ibcon#*before return 0, iclass 18, count 0 2006.173.02:13:29.08#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.02:13:29.08#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.02:13:29.08#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.02:13:29.08#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.02:13:29.08$vck44/va=8,4 2006.173.02:13:29.08#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.02:13:29.08#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.02:13:29.08#ibcon#ireg 11 cls_cnt 2 2006.173.02:13:29.08#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.02:13:29.15#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.02:13:29.15#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.02:13:29.15#ibcon#enter wrdev, iclass 20, count 2 2006.173.02:13:29.15#ibcon#first serial, iclass 20, count 2 2006.173.02:13:29.15#ibcon#enter sib2, iclass 20, count 2 2006.173.02:13:29.15#ibcon#flushed, iclass 20, count 2 2006.173.02:13:29.15#ibcon#about to write, iclass 20, count 2 2006.173.02:13:29.15#ibcon#wrote, iclass 20, count 2 2006.173.02:13:29.15#ibcon#about to read 3, iclass 20, count 2 2006.173.02:13:29.17#ibcon#read 3, iclass 20, count 2 2006.173.02:13:29.17#ibcon#about to read 4, iclass 20, count 2 2006.173.02:13:29.17#ibcon#read 4, iclass 20, count 2 2006.173.02:13:29.17#ibcon#about to read 5, iclass 20, count 2 2006.173.02:13:29.17#ibcon#read 5, iclass 20, count 2 2006.173.02:13:29.17#ibcon#about to read 6, iclass 20, count 2 2006.173.02:13:29.17#ibcon#read 6, iclass 20, count 2 2006.173.02:13:29.17#ibcon#end of sib2, iclass 20, count 2 2006.173.02:13:29.17#ibcon#*mode == 0, iclass 20, count 2 2006.173.02:13:29.17#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.02:13:29.17#ibcon#[25=AT08-04\r\n] 2006.173.02:13:29.17#ibcon#*before write, iclass 20, count 2 2006.173.02:13:29.17#ibcon#enter sib2, iclass 20, count 2 2006.173.02:13:29.17#ibcon#flushed, iclass 20, count 2 2006.173.02:13:29.17#ibcon#about to write, iclass 20, count 2 2006.173.02:13:29.17#ibcon#wrote, iclass 20, count 2 2006.173.02:13:29.17#ibcon#about to read 3, iclass 20, count 2 2006.173.02:13:29.19#ibcon#read 3, iclass 20, count 2 2006.173.02:13:29.19#ibcon#about to read 4, iclass 20, count 2 2006.173.02:13:29.19#ibcon#read 4, iclass 20, count 2 2006.173.02:13:29.19#ibcon#about to read 5, iclass 20, count 2 2006.173.02:13:29.19#ibcon#read 5, iclass 20, count 2 2006.173.02:13:29.19#ibcon#about to read 6, iclass 20, count 2 2006.173.02:13:29.19#ibcon#read 6, iclass 20, count 2 2006.173.02:13:29.19#ibcon#end of sib2, iclass 20, count 2 2006.173.02:13:29.19#ibcon#*after write, iclass 20, count 2 2006.173.02:13:29.19#ibcon#*before return 0, iclass 20, count 2 2006.173.02:13:29.19#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.02:13:29.19#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.02:13:29.19#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.02:13:29.19#ibcon#ireg 7 cls_cnt 0 2006.173.02:13:29.19#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.02:13:29.31#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.02:13:29.31#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.02:13:29.31#ibcon#enter wrdev, iclass 20, count 0 2006.173.02:13:29.31#ibcon#first serial, iclass 20, count 0 2006.173.02:13:29.31#ibcon#enter sib2, iclass 20, count 0 2006.173.02:13:29.31#ibcon#flushed, iclass 20, count 0 2006.173.02:13:29.31#ibcon#about to write, iclass 20, count 0 2006.173.02:13:29.31#ibcon#wrote, iclass 20, count 0 2006.173.02:13:29.31#ibcon#about to read 3, iclass 20, count 0 2006.173.02:13:29.33#ibcon#read 3, iclass 20, count 0 2006.173.02:13:29.33#ibcon#about to read 4, iclass 20, count 0 2006.173.02:13:29.33#ibcon#read 4, iclass 20, count 0 2006.173.02:13:29.33#ibcon#about to read 5, iclass 20, count 0 2006.173.02:13:29.33#ibcon#read 5, iclass 20, count 0 2006.173.02:13:29.33#ibcon#about to read 6, iclass 20, count 0 2006.173.02:13:29.33#ibcon#read 6, iclass 20, count 0 2006.173.02:13:29.33#ibcon#end of sib2, iclass 20, count 0 2006.173.02:13:29.33#ibcon#*mode == 0, iclass 20, count 0 2006.173.02:13:29.33#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.02:13:29.33#ibcon#[25=USB\r\n] 2006.173.02:13:29.33#ibcon#*before write, iclass 20, count 0 2006.173.02:13:29.33#ibcon#enter sib2, iclass 20, count 0 2006.173.02:13:29.33#ibcon#flushed, iclass 20, count 0 2006.173.02:13:29.33#ibcon#about to write, iclass 20, count 0 2006.173.02:13:29.33#ibcon#wrote, iclass 20, count 0 2006.173.02:13:29.33#ibcon#about to read 3, iclass 20, count 0 2006.173.02:13:29.36#ibcon#read 3, iclass 20, count 0 2006.173.02:13:29.36#ibcon#about to read 4, iclass 20, count 0 2006.173.02:13:29.36#ibcon#read 4, iclass 20, count 0 2006.173.02:13:29.36#ibcon#about to read 5, iclass 20, count 0 2006.173.02:13:29.36#ibcon#read 5, iclass 20, count 0 2006.173.02:13:29.36#ibcon#about to read 6, iclass 20, count 0 2006.173.02:13:29.36#ibcon#read 6, iclass 20, count 0 2006.173.02:13:29.36#ibcon#end of sib2, iclass 20, count 0 2006.173.02:13:29.36#ibcon#*after write, iclass 20, count 0 2006.173.02:13:29.36#ibcon#*before return 0, iclass 20, count 0 2006.173.02:13:29.36#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.02:13:29.36#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.02:13:29.36#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.02:13:29.36#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.02:13:29.36$vck44/vblo=1,629.99 2006.173.02:13:29.36#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.02:13:29.36#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.02:13:29.36#ibcon#ireg 17 cls_cnt 0 2006.173.02:13:29.36#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.02:13:29.36#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.02:13:29.36#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.02:13:29.36#ibcon#enter wrdev, iclass 22, count 0 2006.173.02:13:29.36#ibcon#first serial, iclass 22, count 0 2006.173.02:13:29.36#ibcon#enter sib2, iclass 22, count 0 2006.173.02:13:29.36#ibcon#flushed, iclass 22, count 0 2006.173.02:13:29.36#ibcon#about to write, iclass 22, count 0 2006.173.02:13:29.36#ibcon#wrote, iclass 22, count 0 2006.173.02:13:29.36#ibcon#about to read 3, iclass 22, count 0 2006.173.02:13:29.38#ibcon#read 3, iclass 22, count 0 2006.173.02:13:29.38#ibcon#about to read 4, iclass 22, count 0 2006.173.02:13:29.38#ibcon#read 4, iclass 22, count 0 2006.173.02:13:29.38#ibcon#about to read 5, iclass 22, count 0 2006.173.02:13:29.38#ibcon#read 5, iclass 22, count 0 2006.173.02:13:29.38#ibcon#about to read 6, iclass 22, count 0 2006.173.02:13:29.38#ibcon#read 6, iclass 22, count 0 2006.173.02:13:29.38#ibcon#end of sib2, iclass 22, count 0 2006.173.02:13:29.38#ibcon#*mode == 0, iclass 22, count 0 2006.173.02:13:29.38#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.02:13:29.38#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.02:13:29.38#ibcon#*before write, iclass 22, count 0 2006.173.02:13:29.38#ibcon#enter sib2, iclass 22, count 0 2006.173.02:13:29.38#ibcon#flushed, iclass 22, count 0 2006.173.02:13:29.38#ibcon#about to write, iclass 22, count 0 2006.173.02:13:29.38#ibcon#wrote, iclass 22, count 0 2006.173.02:13:29.38#ibcon#about to read 3, iclass 22, count 0 2006.173.02:13:29.42#ibcon#read 3, iclass 22, count 0 2006.173.02:13:29.42#ibcon#about to read 4, iclass 22, count 0 2006.173.02:13:29.42#ibcon#read 4, iclass 22, count 0 2006.173.02:13:29.42#ibcon#about to read 5, iclass 22, count 0 2006.173.02:13:29.42#ibcon#read 5, iclass 22, count 0 2006.173.02:13:29.42#ibcon#about to read 6, iclass 22, count 0 2006.173.02:13:29.42#ibcon#read 6, iclass 22, count 0 2006.173.02:13:29.42#ibcon#end of sib2, iclass 22, count 0 2006.173.02:13:29.42#ibcon#*after write, iclass 22, count 0 2006.173.02:13:29.42#ibcon#*before return 0, iclass 22, count 0 2006.173.02:13:29.42#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.02:13:29.42#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.02:13:29.42#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.02:13:29.42#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.02:13:29.42$vck44/vb=1,4 2006.173.02:13:29.42#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.02:13:29.42#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.02:13:29.42#ibcon#ireg 11 cls_cnt 2 2006.173.02:13:29.42#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.02:13:29.42#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.02:13:29.42#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.02:13:29.42#ibcon#enter wrdev, iclass 24, count 2 2006.173.02:13:29.42#ibcon#first serial, iclass 24, count 2 2006.173.02:13:29.42#ibcon#enter sib2, iclass 24, count 2 2006.173.02:13:29.42#ibcon#flushed, iclass 24, count 2 2006.173.02:13:29.42#ibcon#about to write, iclass 24, count 2 2006.173.02:13:29.42#ibcon#wrote, iclass 24, count 2 2006.173.02:13:29.42#ibcon#about to read 3, iclass 24, count 2 2006.173.02:13:29.44#ibcon#read 3, iclass 24, count 2 2006.173.02:13:29.44#ibcon#about to read 4, iclass 24, count 2 2006.173.02:13:29.44#ibcon#read 4, iclass 24, count 2 2006.173.02:13:29.44#ibcon#about to read 5, iclass 24, count 2 2006.173.02:13:29.44#ibcon#read 5, iclass 24, count 2 2006.173.02:13:29.44#ibcon#about to read 6, iclass 24, count 2 2006.173.02:13:29.44#ibcon#read 6, iclass 24, count 2 2006.173.02:13:29.44#ibcon#end of sib2, iclass 24, count 2 2006.173.02:13:29.44#ibcon#*mode == 0, iclass 24, count 2 2006.173.02:13:29.44#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.02:13:29.44#ibcon#[27=AT01-04\r\n] 2006.173.02:13:29.44#ibcon#*before write, iclass 24, count 2 2006.173.02:13:29.44#ibcon#enter sib2, iclass 24, count 2 2006.173.02:13:29.44#ibcon#flushed, iclass 24, count 2 2006.173.02:13:29.44#ibcon#about to write, iclass 24, count 2 2006.173.02:13:29.44#ibcon#wrote, iclass 24, count 2 2006.173.02:13:29.44#ibcon#about to read 3, iclass 24, count 2 2006.173.02:13:29.47#ibcon#read 3, iclass 24, count 2 2006.173.02:13:29.47#ibcon#about to read 4, iclass 24, count 2 2006.173.02:13:29.47#ibcon#read 4, iclass 24, count 2 2006.173.02:13:29.47#ibcon#about to read 5, iclass 24, count 2 2006.173.02:13:29.47#ibcon#read 5, iclass 24, count 2 2006.173.02:13:29.47#ibcon#about to read 6, iclass 24, count 2 2006.173.02:13:29.47#ibcon#read 6, iclass 24, count 2 2006.173.02:13:29.47#ibcon#end of sib2, iclass 24, count 2 2006.173.02:13:29.47#ibcon#*after write, iclass 24, count 2 2006.173.02:13:29.47#ibcon#*before return 0, iclass 24, count 2 2006.173.02:13:29.47#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.02:13:29.47#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.02:13:29.47#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.02:13:29.47#ibcon#ireg 7 cls_cnt 0 2006.173.02:13:29.47#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.02:13:29.59#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.02:13:29.59#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.02:13:29.59#ibcon#enter wrdev, iclass 24, count 0 2006.173.02:13:29.59#ibcon#first serial, iclass 24, count 0 2006.173.02:13:29.59#ibcon#enter sib2, iclass 24, count 0 2006.173.02:13:29.59#ibcon#flushed, iclass 24, count 0 2006.173.02:13:29.59#ibcon#about to write, iclass 24, count 0 2006.173.02:13:29.59#ibcon#wrote, iclass 24, count 0 2006.173.02:13:29.59#ibcon#about to read 3, iclass 24, count 0 2006.173.02:13:29.61#ibcon#read 3, iclass 24, count 0 2006.173.02:13:29.61#ibcon#about to read 4, iclass 24, count 0 2006.173.02:13:29.61#ibcon#read 4, iclass 24, count 0 2006.173.02:13:29.61#ibcon#about to read 5, iclass 24, count 0 2006.173.02:13:29.61#ibcon#read 5, iclass 24, count 0 2006.173.02:13:29.61#ibcon#about to read 6, iclass 24, count 0 2006.173.02:13:29.61#ibcon#read 6, iclass 24, count 0 2006.173.02:13:29.61#ibcon#end of sib2, iclass 24, count 0 2006.173.02:13:29.61#ibcon#*mode == 0, iclass 24, count 0 2006.173.02:13:29.61#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.02:13:29.61#ibcon#[27=USB\r\n] 2006.173.02:13:29.61#ibcon#*before write, iclass 24, count 0 2006.173.02:13:29.61#ibcon#enter sib2, iclass 24, count 0 2006.173.02:13:29.61#ibcon#flushed, iclass 24, count 0 2006.173.02:13:29.61#ibcon#about to write, iclass 24, count 0 2006.173.02:13:29.61#ibcon#wrote, iclass 24, count 0 2006.173.02:13:29.61#ibcon#about to read 3, iclass 24, count 0 2006.173.02:13:29.64#ibcon#read 3, iclass 24, count 0 2006.173.02:13:29.64#ibcon#about to read 4, iclass 24, count 0 2006.173.02:13:29.64#ibcon#read 4, iclass 24, count 0 2006.173.02:13:29.64#ibcon#about to read 5, iclass 24, count 0 2006.173.02:13:29.64#ibcon#read 5, iclass 24, count 0 2006.173.02:13:29.64#ibcon#about to read 6, iclass 24, count 0 2006.173.02:13:29.64#ibcon#read 6, iclass 24, count 0 2006.173.02:13:29.64#ibcon#end of sib2, iclass 24, count 0 2006.173.02:13:29.64#ibcon#*after write, iclass 24, count 0 2006.173.02:13:29.64#ibcon#*before return 0, iclass 24, count 0 2006.173.02:13:29.64#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.02:13:29.64#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.02:13:29.64#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.02:13:29.64#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.02:13:29.64$vck44/vblo=2,634.99 2006.173.02:13:29.64#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.02:13:29.64#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.02:13:29.64#ibcon#ireg 17 cls_cnt 0 2006.173.02:13:29.64#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.02:13:29.64#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.02:13:29.64#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.02:13:29.64#ibcon#enter wrdev, iclass 26, count 0 2006.173.02:13:29.64#ibcon#first serial, iclass 26, count 0 2006.173.02:13:29.64#ibcon#enter sib2, iclass 26, count 0 2006.173.02:13:29.64#ibcon#flushed, iclass 26, count 0 2006.173.02:13:29.64#ibcon#about to write, iclass 26, count 0 2006.173.02:13:29.64#ibcon#wrote, iclass 26, count 0 2006.173.02:13:29.64#ibcon#about to read 3, iclass 26, count 0 2006.173.02:13:29.66#ibcon#read 3, iclass 26, count 0 2006.173.02:13:29.66#ibcon#about to read 4, iclass 26, count 0 2006.173.02:13:29.66#ibcon#read 4, iclass 26, count 0 2006.173.02:13:29.66#ibcon#about to read 5, iclass 26, count 0 2006.173.02:13:29.66#ibcon#read 5, iclass 26, count 0 2006.173.02:13:29.66#ibcon#about to read 6, iclass 26, count 0 2006.173.02:13:29.66#ibcon#read 6, iclass 26, count 0 2006.173.02:13:29.66#ibcon#end of sib2, iclass 26, count 0 2006.173.02:13:29.66#ibcon#*mode == 0, iclass 26, count 0 2006.173.02:13:29.66#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.02:13:29.66#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.02:13:29.66#ibcon#*before write, iclass 26, count 0 2006.173.02:13:29.66#ibcon#enter sib2, iclass 26, count 0 2006.173.02:13:29.66#ibcon#flushed, iclass 26, count 0 2006.173.02:13:29.66#ibcon#about to write, iclass 26, count 0 2006.173.02:13:29.66#ibcon#wrote, iclass 26, count 0 2006.173.02:13:29.66#ibcon#about to read 3, iclass 26, count 0 2006.173.02:13:29.70#ibcon#read 3, iclass 26, count 0 2006.173.02:13:29.70#ibcon#about to read 4, iclass 26, count 0 2006.173.02:13:29.70#ibcon#read 4, iclass 26, count 0 2006.173.02:13:29.70#ibcon#about to read 5, iclass 26, count 0 2006.173.02:13:29.70#ibcon#read 5, iclass 26, count 0 2006.173.02:13:29.70#ibcon#about to read 6, iclass 26, count 0 2006.173.02:13:29.70#ibcon#read 6, iclass 26, count 0 2006.173.02:13:29.70#ibcon#end of sib2, iclass 26, count 0 2006.173.02:13:29.70#ibcon#*after write, iclass 26, count 0 2006.173.02:13:29.70#ibcon#*before return 0, iclass 26, count 0 2006.173.02:13:29.70#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.02:13:29.70#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.02:13:29.70#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.02:13:29.70#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.02:13:29.70$vck44/vb=2,4 2006.173.02:13:29.70#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.02:13:29.70#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.02:13:29.70#ibcon#ireg 11 cls_cnt 2 2006.173.02:13:29.70#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.02:13:29.76#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.02:13:29.76#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.02:13:29.76#ibcon#enter wrdev, iclass 28, count 2 2006.173.02:13:29.76#ibcon#first serial, iclass 28, count 2 2006.173.02:13:29.76#ibcon#enter sib2, iclass 28, count 2 2006.173.02:13:29.76#ibcon#flushed, iclass 28, count 2 2006.173.02:13:29.76#ibcon#about to write, iclass 28, count 2 2006.173.02:13:29.76#ibcon#wrote, iclass 28, count 2 2006.173.02:13:29.76#ibcon#about to read 3, iclass 28, count 2 2006.173.02:13:29.78#ibcon#read 3, iclass 28, count 2 2006.173.02:13:29.78#ibcon#about to read 4, iclass 28, count 2 2006.173.02:13:29.78#ibcon#read 4, iclass 28, count 2 2006.173.02:13:29.78#ibcon#about to read 5, iclass 28, count 2 2006.173.02:13:29.78#ibcon#read 5, iclass 28, count 2 2006.173.02:13:29.78#ibcon#about to read 6, iclass 28, count 2 2006.173.02:13:29.78#ibcon#read 6, iclass 28, count 2 2006.173.02:13:29.78#ibcon#end of sib2, iclass 28, count 2 2006.173.02:13:29.78#ibcon#*mode == 0, iclass 28, count 2 2006.173.02:13:29.78#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.02:13:29.78#ibcon#[27=AT02-04\r\n] 2006.173.02:13:29.78#ibcon#*before write, iclass 28, count 2 2006.173.02:13:29.78#ibcon#enter sib2, iclass 28, count 2 2006.173.02:13:29.78#ibcon#flushed, iclass 28, count 2 2006.173.02:13:29.78#ibcon#about to write, iclass 28, count 2 2006.173.02:13:29.78#ibcon#wrote, iclass 28, count 2 2006.173.02:13:29.78#ibcon#about to read 3, iclass 28, count 2 2006.173.02:13:29.81#ibcon#read 3, iclass 28, count 2 2006.173.02:13:29.81#ibcon#about to read 4, iclass 28, count 2 2006.173.02:13:29.81#ibcon#read 4, iclass 28, count 2 2006.173.02:13:29.81#ibcon#about to read 5, iclass 28, count 2 2006.173.02:13:29.81#ibcon#read 5, iclass 28, count 2 2006.173.02:13:29.81#ibcon#about to read 6, iclass 28, count 2 2006.173.02:13:29.81#ibcon#read 6, iclass 28, count 2 2006.173.02:13:29.81#ibcon#end of sib2, iclass 28, count 2 2006.173.02:13:29.81#ibcon#*after write, iclass 28, count 2 2006.173.02:13:29.81#ibcon#*before return 0, iclass 28, count 2 2006.173.02:13:29.81#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.02:13:29.81#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.02:13:29.81#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.02:13:29.81#ibcon#ireg 7 cls_cnt 0 2006.173.02:13:29.81#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.02:13:29.93#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.02:13:29.93#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.02:13:29.93#ibcon#enter wrdev, iclass 28, count 0 2006.173.02:13:29.93#ibcon#first serial, iclass 28, count 0 2006.173.02:13:29.93#ibcon#enter sib2, iclass 28, count 0 2006.173.02:13:29.93#ibcon#flushed, iclass 28, count 0 2006.173.02:13:29.93#ibcon#about to write, iclass 28, count 0 2006.173.02:13:29.93#ibcon#wrote, iclass 28, count 0 2006.173.02:13:29.93#ibcon#about to read 3, iclass 28, count 0 2006.173.02:13:29.95#ibcon#read 3, iclass 28, count 0 2006.173.02:13:29.95#ibcon#about to read 4, iclass 28, count 0 2006.173.02:13:29.95#ibcon#read 4, iclass 28, count 0 2006.173.02:13:29.95#ibcon#about to read 5, iclass 28, count 0 2006.173.02:13:29.95#ibcon#read 5, iclass 28, count 0 2006.173.02:13:29.95#ibcon#about to read 6, iclass 28, count 0 2006.173.02:13:29.95#ibcon#read 6, iclass 28, count 0 2006.173.02:13:29.95#ibcon#end of sib2, iclass 28, count 0 2006.173.02:13:29.95#ibcon#*mode == 0, iclass 28, count 0 2006.173.02:13:29.95#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.02:13:29.95#ibcon#[27=USB\r\n] 2006.173.02:13:29.95#ibcon#*before write, iclass 28, count 0 2006.173.02:13:29.95#ibcon#enter sib2, iclass 28, count 0 2006.173.02:13:29.95#ibcon#flushed, iclass 28, count 0 2006.173.02:13:29.95#ibcon#about to write, iclass 28, count 0 2006.173.02:13:29.95#ibcon#wrote, iclass 28, count 0 2006.173.02:13:29.95#ibcon#about to read 3, iclass 28, count 0 2006.173.02:13:29.98#ibcon#read 3, iclass 28, count 0 2006.173.02:13:29.98#ibcon#about to read 4, iclass 28, count 0 2006.173.02:13:29.98#ibcon#read 4, iclass 28, count 0 2006.173.02:13:29.98#ibcon#about to read 5, iclass 28, count 0 2006.173.02:13:29.98#ibcon#read 5, iclass 28, count 0 2006.173.02:13:29.98#ibcon#about to read 6, iclass 28, count 0 2006.173.02:13:29.98#ibcon#read 6, iclass 28, count 0 2006.173.02:13:29.98#ibcon#end of sib2, iclass 28, count 0 2006.173.02:13:29.98#ibcon#*after write, iclass 28, count 0 2006.173.02:13:29.98#ibcon#*before return 0, iclass 28, count 0 2006.173.02:13:29.98#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.02:13:29.98#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.02:13:29.98#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.02:13:29.98#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.02:13:29.98$vck44/vblo=3,649.99 2006.173.02:13:29.98#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.02:13:29.98#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.02:13:29.98#ibcon#ireg 17 cls_cnt 0 2006.173.02:13:29.98#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.02:13:29.98#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.02:13:29.98#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.02:13:29.98#ibcon#enter wrdev, iclass 30, count 0 2006.173.02:13:29.98#ibcon#first serial, iclass 30, count 0 2006.173.02:13:29.98#ibcon#enter sib2, iclass 30, count 0 2006.173.02:13:29.98#ibcon#flushed, iclass 30, count 0 2006.173.02:13:29.98#ibcon#about to write, iclass 30, count 0 2006.173.02:13:29.98#ibcon#wrote, iclass 30, count 0 2006.173.02:13:29.98#ibcon#about to read 3, iclass 30, count 0 2006.173.02:13:30.00#ibcon#read 3, iclass 30, count 0 2006.173.02:13:30.00#ibcon#about to read 4, iclass 30, count 0 2006.173.02:13:30.00#ibcon#read 4, iclass 30, count 0 2006.173.02:13:30.00#ibcon#about to read 5, iclass 30, count 0 2006.173.02:13:30.00#ibcon#read 5, iclass 30, count 0 2006.173.02:13:30.00#ibcon#about to read 6, iclass 30, count 0 2006.173.02:13:30.00#ibcon#read 6, iclass 30, count 0 2006.173.02:13:30.00#ibcon#end of sib2, iclass 30, count 0 2006.173.02:13:30.00#ibcon#*mode == 0, iclass 30, count 0 2006.173.02:13:30.00#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.02:13:30.00#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.02:13:30.00#ibcon#*before write, iclass 30, count 0 2006.173.02:13:30.00#ibcon#enter sib2, iclass 30, count 0 2006.173.02:13:30.00#ibcon#flushed, iclass 30, count 0 2006.173.02:13:30.00#ibcon#about to write, iclass 30, count 0 2006.173.02:13:30.00#ibcon#wrote, iclass 30, count 0 2006.173.02:13:30.00#ibcon#about to read 3, iclass 30, count 0 2006.173.02:13:30.04#ibcon#read 3, iclass 30, count 0 2006.173.02:13:30.04#ibcon#about to read 4, iclass 30, count 0 2006.173.02:13:30.04#ibcon#read 4, iclass 30, count 0 2006.173.02:13:30.04#ibcon#about to read 5, iclass 30, count 0 2006.173.02:13:30.04#ibcon#read 5, iclass 30, count 0 2006.173.02:13:30.04#ibcon#about to read 6, iclass 30, count 0 2006.173.02:13:30.04#ibcon#read 6, iclass 30, count 0 2006.173.02:13:30.04#ibcon#end of sib2, iclass 30, count 0 2006.173.02:13:30.04#ibcon#*after write, iclass 30, count 0 2006.173.02:13:30.04#ibcon#*before return 0, iclass 30, count 0 2006.173.02:13:30.04#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.02:13:30.04#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.02:13:30.04#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.02:13:30.04#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.02:13:30.04$vck44/vb=3,4 2006.173.02:13:30.04#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.173.02:13:30.04#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.173.02:13:30.04#ibcon#ireg 11 cls_cnt 2 2006.173.02:13:30.04#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.02:13:30.10#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.02:13:30.10#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.02:13:30.10#ibcon#enter wrdev, iclass 32, count 2 2006.173.02:13:30.10#ibcon#first serial, iclass 32, count 2 2006.173.02:13:30.10#ibcon#enter sib2, iclass 32, count 2 2006.173.02:13:30.10#ibcon#flushed, iclass 32, count 2 2006.173.02:13:30.10#ibcon#about to write, iclass 32, count 2 2006.173.02:13:30.10#ibcon#wrote, iclass 32, count 2 2006.173.02:13:30.10#ibcon#about to read 3, iclass 32, count 2 2006.173.02:13:30.12#ibcon#read 3, iclass 32, count 2 2006.173.02:13:30.12#ibcon#about to read 4, iclass 32, count 2 2006.173.02:13:30.12#ibcon#read 4, iclass 32, count 2 2006.173.02:13:30.12#ibcon#about to read 5, iclass 32, count 2 2006.173.02:13:30.12#ibcon#read 5, iclass 32, count 2 2006.173.02:13:30.12#ibcon#about to read 6, iclass 32, count 2 2006.173.02:13:30.12#ibcon#read 6, iclass 32, count 2 2006.173.02:13:30.12#ibcon#end of sib2, iclass 32, count 2 2006.173.02:13:30.12#ibcon#*mode == 0, iclass 32, count 2 2006.173.02:13:30.12#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.173.02:13:30.12#ibcon#[27=AT03-04\r\n] 2006.173.02:13:30.12#ibcon#*before write, iclass 32, count 2 2006.173.02:13:30.12#ibcon#enter sib2, iclass 32, count 2 2006.173.02:13:30.12#ibcon#flushed, iclass 32, count 2 2006.173.02:13:30.12#ibcon#about to write, iclass 32, count 2 2006.173.02:13:30.12#ibcon#wrote, iclass 32, count 2 2006.173.02:13:30.12#ibcon#about to read 3, iclass 32, count 2 2006.173.02:13:30.15#ibcon#read 3, iclass 32, count 2 2006.173.02:13:30.15#ibcon#about to read 4, iclass 32, count 2 2006.173.02:13:30.15#ibcon#read 4, iclass 32, count 2 2006.173.02:13:30.15#ibcon#about to read 5, iclass 32, count 2 2006.173.02:13:30.15#ibcon#read 5, iclass 32, count 2 2006.173.02:13:30.15#ibcon#about to read 6, iclass 32, count 2 2006.173.02:13:30.15#ibcon#read 6, iclass 32, count 2 2006.173.02:13:30.15#ibcon#end of sib2, iclass 32, count 2 2006.173.02:13:30.15#ibcon#*after write, iclass 32, count 2 2006.173.02:13:30.15#ibcon#*before return 0, iclass 32, count 2 2006.173.02:13:30.15#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.02:13:30.15#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.173.02:13:30.15#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.173.02:13:30.15#ibcon#ireg 7 cls_cnt 0 2006.173.02:13:30.15#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.02:13:30.27#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.02:13:30.27#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.02:13:30.27#ibcon#enter wrdev, iclass 32, count 0 2006.173.02:13:30.27#ibcon#first serial, iclass 32, count 0 2006.173.02:13:30.27#ibcon#enter sib2, iclass 32, count 0 2006.173.02:13:30.27#ibcon#flushed, iclass 32, count 0 2006.173.02:13:30.27#ibcon#about to write, iclass 32, count 0 2006.173.02:13:30.27#ibcon#wrote, iclass 32, count 0 2006.173.02:13:30.27#ibcon#about to read 3, iclass 32, count 0 2006.173.02:13:30.29#ibcon#read 3, iclass 32, count 0 2006.173.02:13:30.29#ibcon#about to read 4, iclass 32, count 0 2006.173.02:13:30.29#ibcon#read 4, iclass 32, count 0 2006.173.02:13:30.29#ibcon#about to read 5, iclass 32, count 0 2006.173.02:13:30.29#ibcon#read 5, iclass 32, count 0 2006.173.02:13:30.29#ibcon#about to read 6, iclass 32, count 0 2006.173.02:13:30.29#ibcon#read 6, iclass 32, count 0 2006.173.02:13:30.29#ibcon#end of sib2, iclass 32, count 0 2006.173.02:13:30.29#ibcon#*mode == 0, iclass 32, count 0 2006.173.02:13:30.29#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.02:13:30.29#ibcon#[27=USB\r\n] 2006.173.02:13:30.29#ibcon#*before write, iclass 32, count 0 2006.173.02:13:30.29#ibcon#enter sib2, iclass 32, count 0 2006.173.02:13:30.29#ibcon#flushed, iclass 32, count 0 2006.173.02:13:30.29#ibcon#about to write, iclass 32, count 0 2006.173.02:13:30.29#ibcon#wrote, iclass 32, count 0 2006.173.02:13:30.29#ibcon#about to read 3, iclass 32, count 0 2006.173.02:13:30.32#ibcon#read 3, iclass 32, count 0 2006.173.02:13:30.32#ibcon#about to read 4, iclass 32, count 0 2006.173.02:13:30.32#ibcon#read 4, iclass 32, count 0 2006.173.02:13:30.32#ibcon#about to read 5, iclass 32, count 0 2006.173.02:13:30.32#ibcon#read 5, iclass 32, count 0 2006.173.02:13:30.32#ibcon#about to read 6, iclass 32, count 0 2006.173.02:13:30.32#ibcon#read 6, iclass 32, count 0 2006.173.02:13:30.32#ibcon#end of sib2, iclass 32, count 0 2006.173.02:13:30.32#ibcon#*after write, iclass 32, count 0 2006.173.02:13:30.32#ibcon#*before return 0, iclass 32, count 0 2006.173.02:13:30.32#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.02:13:30.32#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.173.02:13:30.32#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.02:13:30.32#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.02:13:30.32$vck44/vblo=4,679.99 2006.173.02:13:30.32#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.02:13:30.32#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.02:13:30.32#ibcon#ireg 17 cls_cnt 0 2006.173.02:13:30.32#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.02:13:30.32#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.02:13:30.32#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.02:13:30.32#ibcon#enter wrdev, iclass 34, count 0 2006.173.02:13:30.32#ibcon#first serial, iclass 34, count 0 2006.173.02:13:30.32#ibcon#enter sib2, iclass 34, count 0 2006.173.02:13:30.32#ibcon#flushed, iclass 34, count 0 2006.173.02:13:30.32#ibcon#about to write, iclass 34, count 0 2006.173.02:13:30.32#ibcon#wrote, iclass 34, count 0 2006.173.02:13:30.32#ibcon#about to read 3, iclass 34, count 0 2006.173.02:13:30.34#ibcon#read 3, iclass 34, count 0 2006.173.02:13:30.34#ibcon#about to read 4, iclass 34, count 0 2006.173.02:13:30.34#ibcon#read 4, iclass 34, count 0 2006.173.02:13:30.34#ibcon#about to read 5, iclass 34, count 0 2006.173.02:13:30.34#ibcon#read 5, iclass 34, count 0 2006.173.02:13:30.34#ibcon#about to read 6, iclass 34, count 0 2006.173.02:13:30.34#ibcon#read 6, iclass 34, count 0 2006.173.02:13:30.34#ibcon#end of sib2, iclass 34, count 0 2006.173.02:13:30.34#ibcon#*mode == 0, iclass 34, count 0 2006.173.02:13:30.34#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.02:13:30.34#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.02:13:30.34#ibcon#*before write, iclass 34, count 0 2006.173.02:13:30.34#ibcon#enter sib2, iclass 34, count 0 2006.173.02:13:30.34#ibcon#flushed, iclass 34, count 0 2006.173.02:13:30.34#ibcon#about to write, iclass 34, count 0 2006.173.02:13:30.34#ibcon#wrote, iclass 34, count 0 2006.173.02:13:30.34#ibcon#about to read 3, iclass 34, count 0 2006.173.02:13:30.38#ibcon#read 3, iclass 34, count 0 2006.173.02:13:30.38#ibcon#about to read 4, iclass 34, count 0 2006.173.02:13:30.38#ibcon#read 4, iclass 34, count 0 2006.173.02:13:30.38#ibcon#about to read 5, iclass 34, count 0 2006.173.02:13:30.38#ibcon#read 5, iclass 34, count 0 2006.173.02:13:30.38#ibcon#about to read 6, iclass 34, count 0 2006.173.02:13:30.38#ibcon#read 6, iclass 34, count 0 2006.173.02:13:30.38#ibcon#end of sib2, iclass 34, count 0 2006.173.02:13:30.38#ibcon#*after write, iclass 34, count 0 2006.173.02:13:30.38#ibcon#*before return 0, iclass 34, count 0 2006.173.02:13:30.38#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.02:13:30.38#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.02:13:30.38#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.02:13:30.38#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.02:13:30.38$vck44/vb=4,4 2006.173.02:13:30.38#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.02:13:30.38#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.02:13:30.38#ibcon#ireg 11 cls_cnt 2 2006.173.02:13:30.38#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.02:13:30.44#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.02:13:30.44#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.02:13:30.44#ibcon#enter wrdev, iclass 36, count 2 2006.173.02:13:30.44#ibcon#first serial, iclass 36, count 2 2006.173.02:13:30.44#ibcon#enter sib2, iclass 36, count 2 2006.173.02:13:30.44#ibcon#flushed, iclass 36, count 2 2006.173.02:13:30.44#ibcon#about to write, iclass 36, count 2 2006.173.02:13:30.44#ibcon#wrote, iclass 36, count 2 2006.173.02:13:30.44#ibcon#about to read 3, iclass 36, count 2 2006.173.02:13:30.46#ibcon#read 3, iclass 36, count 2 2006.173.02:13:30.46#ibcon#about to read 4, iclass 36, count 2 2006.173.02:13:30.46#ibcon#read 4, iclass 36, count 2 2006.173.02:13:30.46#ibcon#about to read 5, iclass 36, count 2 2006.173.02:13:30.46#ibcon#read 5, iclass 36, count 2 2006.173.02:13:30.46#ibcon#about to read 6, iclass 36, count 2 2006.173.02:13:30.46#ibcon#read 6, iclass 36, count 2 2006.173.02:13:30.46#ibcon#end of sib2, iclass 36, count 2 2006.173.02:13:30.46#ibcon#*mode == 0, iclass 36, count 2 2006.173.02:13:30.46#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.02:13:30.46#ibcon#[27=AT04-04\r\n] 2006.173.02:13:30.46#ibcon#*before write, iclass 36, count 2 2006.173.02:13:30.46#ibcon#enter sib2, iclass 36, count 2 2006.173.02:13:30.46#ibcon#flushed, iclass 36, count 2 2006.173.02:13:30.46#ibcon#about to write, iclass 36, count 2 2006.173.02:13:30.46#ibcon#wrote, iclass 36, count 2 2006.173.02:13:30.46#ibcon#about to read 3, iclass 36, count 2 2006.173.02:13:30.49#ibcon#read 3, iclass 36, count 2 2006.173.02:13:30.49#ibcon#about to read 4, iclass 36, count 2 2006.173.02:13:30.49#ibcon#read 4, iclass 36, count 2 2006.173.02:13:30.49#ibcon#about to read 5, iclass 36, count 2 2006.173.02:13:30.49#ibcon#read 5, iclass 36, count 2 2006.173.02:13:30.49#ibcon#about to read 6, iclass 36, count 2 2006.173.02:13:30.49#ibcon#read 6, iclass 36, count 2 2006.173.02:13:30.49#ibcon#end of sib2, iclass 36, count 2 2006.173.02:13:30.49#ibcon#*after write, iclass 36, count 2 2006.173.02:13:30.49#ibcon#*before return 0, iclass 36, count 2 2006.173.02:13:30.49#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.02:13:30.49#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.02:13:30.49#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.02:13:30.49#ibcon#ireg 7 cls_cnt 0 2006.173.02:13:30.49#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.02:13:30.61#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.02:13:30.61#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.02:13:30.61#ibcon#enter wrdev, iclass 36, count 0 2006.173.02:13:30.61#ibcon#first serial, iclass 36, count 0 2006.173.02:13:30.61#ibcon#enter sib2, iclass 36, count 0 2006.173.02:13:30.61#ibcon#flushed, iclass 36, count 0 2006.173.02:13:30.61#ibcon#about to write, iclass 36, count 0 2006.173.02:13:30.61#ibcon#wrote, iclass 36, count 0 2006.173.02:13:30.61#ibcon#about to read 3, iclass 36, count 0 2006.173.02:13:30.63#ibcon#read 3, iclass 36, count 0 2006.173.02:13:30.63#ibcon#about to read 4, iclass 36, count 0 2006.173.02:13:30.63#ibcon#read 4, iclass 36, count 0 2006.173.02:13:30.63#ibcon#about to read 5, iclass 36, count 0 2006.173.02:13:30.63#ibcon#read 5, iclass 36, count 0 2006.173.02:13:30.63#ibcon#about to read 6, iclass 36, count 0 2006.173.02:13:30.63#ibcon#read 6, iclass 36, count 0 2006.173.02:13:30.63#ibcon#end of sib2, iclass 36, count 0 2006.173.02:13:30.63#ibcon#*mode == 0, iclass 36, count 0 2006.173.02:13:30.63#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.02:13:30.63#ibcon#[27=USB\r\n] 2006.173.02:13:30.63#ibcon#*before write, iclass 36, count 0 2006.173.02:13:30.63#ibcon#enter sib2, iclass 36, count 0 2006.173.02:13:30.63#ibcon#flushed, iclass 36, count 0 2006.173.02:13:30.63#ibcon#about to write, iclass 36, count 0 2006.173.02:13:30.63#ibcon#wrote, iclass 36, count 0 2006.173.02:13:30.63#ibcon#about to read 3, iclass 36, count 0 2006.173.02:13:30.66#ibcon#read 3, iclass 36, count 0 2006.173.02:13:30.66#ibcon#about to read 4, iclass 36, count 0 2006.173.02:13:30.66#ibcon#read 4, iclass 36, count 0 2006.173.02:13:30.66#ibcon#about to read 5, iclass 36, count 0 2006.173.02:13:30.66#ibcon#read 5, iclass 36, count 0 2006.173.02:13:30.66#ibcon#about to read 6, iclass 36, count 0 2006.173.02:13:30.66#ibcon#read 6, iclass 36, count 0 2006.173.02:13:30.66#ibcon#end of sib2, iclass 36, count 0 2006.173.02:13:30.66#ibcon#*after write, iclass 36, count 0 2006.173.02:13:30.66#ibcon#*before return 0, iclass 36, count 0 2006.173.02:13:30.66#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.02:13:30.66#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.02:13:30.66#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.02:13:30.66#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.02:13:30.66$vck44/vblo=5,709.99 2006.173.02:13:30.66#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.02:13:30.66#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.02:13:30.66#ibcon#ireg 17 cls_cnt 0 2006.173.02:13:30.66#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.02:13:30.66#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.02:13:30.66#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.02:13:30.66#ibcon#enter wrdev, iclass 38, count 0 2006.173.02:13:30.66#ibcon#first serial, iclass 38, count 0 2006.173.02:13:30.66#ibcon#enter sib2, iclass 38, count 0 2006.173.02:13:30.66#ibcon#flushed, iclass 38, count 0 2006.173.02:13:30.66#ibcon#about to write, iclass 38, count 0 2006.173.02:13:30.66#ibcon#wrote, iclass 38, count 0 2006.173.02:13:30.66#ibcon#about to read 3, iclass 38, count 0 2006.173.02:13:30.68#ibcon#read 3, iclass 38, count 0 2006.173.02:13:30.68#ibcon#about to read 4, iclass 38, count 0 2006.173.02:13:30.68#ibcon#read 4, iclass 38, count 0 2006.173.02:13:30.68#ibcon#about to read 5, iclass 38, count 0 2006.173.02:13:30.68#ibcon#read 5, iclass 38, count 0 2006.173.02:13:30.68#ibcon#about to read 6, iclass 38, count 0 2006.173.02:13:30.68#ibcon#read 6, iclass 38, count 0 2006.173.02:13:30.68#ibcon#end of sib2, iclass 38, count 0 2006.173.02:13:30.68#ibcon#*mode == 0, iclass 38, count 0 2006.173.02:13:30.68#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.02:13:30.68#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.02:13:30.68#ibcon#*before write, iclass 38, count 0 2006.173.02:13:30.68#ibcon#enter sib2, iclass 38, count 0 2006.173.02:13:30.68#ibcon#flushed, iclass 38, count 0 2006.173.02:13:30.68#ibcon#about to write, iclass 38, count 0 2006.173.02:13:30.68#ibcon#wrote, iclass 38, count 0 2006.173.02:13:30.68#ibcon#about to read 3, iclass 38, count 0 2006.173.02:13:30.72#ibcon#read 3, iclass 38, count 0 2006.173.02:13:30.72#ibcon#about to read 4, iclass 38, count 0 2006.173.02:13:30.72#ibcon#read 4, iclass 38, count 0 2006.173.02:13:30.72#ibcon#about to read 5, iclass 38, count 0 2006.173.02:13:30.72#ibcon#read 5, iclass 38, count 0 2006.173.02:13:30.72#ibcon#about to read 6, iclass 38, count 0 2006.173.02:13:30.72#ibcon#read 6, iclass 38, count 0 2006.173.02:13:30.72#ibcon#end of sib2, iclass 38, count 0 2006.173.02:13:30.72#ibcon#*after write, iclass 38, count 0 2006.173.02:13:30.72#ibcon#*before return 0, iclass 38, count 0 2006.173.02:13:30.72#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.02:13:30.72#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.02:13:30.72#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.02:13:30.72#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.02:13:30.72$vck44/vb=5,4 2006.173.02:13:30.72#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.02:13:30.72#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.02:13:30.72#ibcon#ireg 11 cls_cnt 2 2006.173.02:13:30.72#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.02:13:30.78#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.02:13:30.78#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.02:13:30.78#ibcon#enter wrdev, iclass 40, count 2 2006.173.02:13:30.78#ibcon#first serial, iclass 40, count 2 2006.173.02:13:30.78#ibcon#enter sib2, iclass 40, count 2 2006.173.02:13:30.78#ibcon#flushed, iclass 40, count 2 2006.173.02:13:30.78#ibcon#about to write, iclass 40, count 2 2006.173.02:13:30.78#ibcon#wrote, iclass 40, count 2 2006.173.02:13:30.78#ibcon#about to read 3, iclass 40, count 2 2006.173.02:13:30.81#ibcon#read 3, iclass 40, count 2 2006.173.02:13:30.81#ibcon#about to read 4, iclass 40, count 2 2006.173.02:13:30.81#ibcon#read 4, iclass 40, count 2 2006.173.02:13:30.81#ibcon#about to read 5, iclass 40, count 2 2006.173.02:13:30.81#ibcon#read 5, iclass 40, count 2 2006.173.02:13:30.81#ibcon#about to read 6, iclass 40, count 2 2006.173.02:13:30.81#ibcon#read 6, iclass 40, count 2 2006.173.02:13:30.81#ibcon#end of sib2, iclass 40, count 2 2006.173.02:13:30.81#ibcon#*mode == 0, iclass 40, count 2 2006.173.02:13:30.81#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.02:13:30.81#ibcon#[27=AT05-04\r\n] 2006.173.02:13:30.81#ibcon#*before write, iclass 40, count 2 2006.173.02:13:30.81#ibcon#enter sib2, iclass 40, count 2 2006.173.02:13:30.81#ibcon#flushed, iclass 40, count 2 2006.173.02:13:30.81#ibcon#about to write, iclass 40, count 2 2006.173.02:13:30.81#ibcon#wrote, iclass 40, count 2 2006.173.02:13:30.81#ibcon#about to read 3, iclass 40, count 2 2006.173.02:13:30.84#ibcon#read 3, iclass 40, count 2 2006.173.02:13:30.84#ibcon#about to read 4, iclass 40, count 2 2006.173.02:13:30.84#ibcon#read 4, iclass 40, count 2 2006.173.02:13:30.84#ibcon#about to read 5, iclass 40, count 2 2006.173.02:13:30.84#ibcon#read 5, iclass 40, count 2 2006.173.02:13:30.84#ibcon#about to read 6, iclass 40, count 2 2006.173.02:13:30.84#ibcon#read 6, iclass 40, count 2 2006.173.02:13:30.84#ibcon#end of sib2, iclass 40, count 2 2006.173.02:13:30.84#ibcon#*after write, iclass 40, count 2 2006.173.02:13:30.84#ibcon#*before return 0, iclass 40, count 2 2006.173.02:13:30.84#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.02:13:30.84#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.02:13:30.84#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.02:13:30.84#ibcon#ireg 7 cls_cnt 0 2006.173.02:13:30.84#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.02:13:30.96#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.02:13:30.96#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.02:13:30.96#ibcon#enter wrdev, iclass 40, count 0 2006.173.02:13:30.96#ibcon#first serial, iclass 40, count 0 2006.173.02:13:30.96#ibcon#enter sib2, iclass 40, count 0 2006.173.02:13:30.96#ibcon#flushed, iclass 40, count 0 2006.173.02:13:30.96#ibcon#about to write, iclass 40, count 0 2006.173.02:13:30.96#ibcon#wrote, iclass 40, count 0 2006.173.02:13:30.96#ibcon#about to read 3, iclass 40, count 0 2006.173.02:13:30.98#ibcon#read 3, iclass 40, count 0 2006.173.02:13:30.98#ibcon#about to read 4, iclass 40, count 0 2006.173.02:13:30.98#ibcon#read 4, iclass 40, count 0 2006.173.02:13:30.98#ibcon#about to read 5, iclass 40, count 0 2006.173.02:13:30.98#ibcon#read 5, iclass 40, count 0 2006.173.02:13:30.98#ibcon#about to read 6, iclass 40, count 0 2006.173.02:13:30.98#ibcon#read 6, iclass 40, count 0 2006.173.02:13:30.98#ibcon#end of sib2, iclass 40, count 0 2006.173.02:13:30.98#ibcon#*mode == 0, iclass 40, count 0 2006.173.02:13:30.98#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.02:13:30.98#ibcon#[27=USB\r\n] 2006.173.02:13:30.98#ibcon#*before write, iclass 40, count 0 2006.173.02:13:30.98#ibcon#enter sib2, iclass 40, count 0 2006.173.02:13:30.98#ibcon#flushed, iclass 40, count 0 2006.173.02:13:30.98#ibcon#about to write, iclass 40, count 0 2006.173.02:13:30.98#ibcon#wrote, iclass 40, count 0 2006.173.02:13:30.98#ibcon#about to read 3, iclass 40, count 0 2006.173.02:13:31.01#ibcon#read 3, iclass 40, count 0 2006.173.02:13:31.01#ibcon#about to read 4, iclass 40, count 0 2006.173.02:13:31.01#ibcon#read 4, iclass 40, count 0 2006.173.02:13:31.01#ibcon#about to read 5, iclass 40, count 0 2006.173.02:13:31.01#ibcon#read 5, iclass 40, count 0 2006.173.02:13:31.01#ibcon#about to read 6, iclass 40, count 0 2006.173.02:13:31.01#ibcon#read 6, iclass 40, count 0 2006.173.02:13:31.01#ibcon#end of sib2, iclass 40, count 0 2006.173.02:13:31.01#ibcon#*after write, iclass 40, count 0 2006.173.02:13:31.01#ibcon#*before return 0, iclass 40, count 0 2006.173.02:13:31.01#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.02:13:31.01#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.02:13:31.01#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.02:13:31.01#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.02:13:31.01$vck44/vblo=6,719.99 2006.173.02:13:31.01#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.02:13:31.01#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.02:13:31.01#ibcon#ireg 17 cls_cnt 0 2006.173.02:13:31.01#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.02:13:31.01#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.02:13:31.01#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.02:13:31.01#ibcon#enter wrdev, iclass 4, count 0 2006.173.02:13:31.01#ibcon#first serial, iclass 4, count 0 2006.173.02:13:31.01#ibcon#enter sib2, iclass 4, count 0 2006.173.02:13:31.01#ibcon#flushed, iclass 4, count 0 2006.173.02:13:31.01#ibcon#about to write, iclass 4, count 0 2006.173.02:13:31.01#ibcon#wrote, iclass 4, count 0 2006.173.02:13:31.01#ibcon#about to read 3, iclass 4, count 0 2006.173.02:13:31.03#ibcon#read 3, iclass 4, count 0 2006.173.02:13:31.03#ibcon#about to read 4, iclass 4, count 0 2006.173.02:13:31.03#ibcon#read 4, iclass 4, count 0 2006.173.02:13:31.03#ibcon#about to read 5, iclass 4, count 0 2006.173.02:13:31.03#ibcon#read 5, iclass 4, count 0 2006.173.02:13:31.03#ibcon#about to read 6, iclass 4, count 0 2006.173.02:13:31.03#ibcon#read 6, iclass 4, count 0 2006.173.02:13:31.03#ibcon#end of sib2, iclass 4, count 0 2006.173.02:13:31.03#ibcon#*mode == 0, iclass 4, count 0 2006.173.02:13:31.03#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.02:13:31.03#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.02:13:31.03#ibcon#*before write, iclass 4, count 0 2006.173.02:13:31.03#ibcon#enter sib2, iclass 4, count 0 2006.173.02:13:31.03#ibcon#flushed, iclass 4, count 0 2006.173.02:13:31.03#ibcon#about to write, iclass 4, count 0 2006.173.02:13:31.03#ibcon#wrote, iclass 4, count 0 2006.173.02:13:31.03#ibcon#about to read 3, iclass 4, count 0 2006.173.02:13:31.07#ibcon#read 3, iclass 4, count 0 2006.173.02:13:31.07#ibcon#about to read 4, iclass 4, count 0 2006.173.02:13:31.07#ibcon#read 4, iclass 4, count 0 2006.173.02:13:31.07#ibcon#about to read 5, iclass 4, count 0 2006.173.02:13:31.07#ibcon#read 5, iclass 4, count 0 2006.173.02:13:31.07#ibcon#about to read 6, iclass 4, count 0 2006.173.02:13:31.07#ibcon#read 6, iclass 4, count 0 2006.173.02:13:31.07#ibcon#end of sib2, iclass 4, count 0 2006.173.02:13:31.07#ibcon#*after write, iclass 4, count 0 2006.173.02:13:31.07#ibcon#*before return 0, iclass 4, count 0 2006.173.02:13:31.07#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.02:13:31.07#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.02:13:31.07#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.02:13:31.07#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.02:13:31.07$vck44/vb=6,4 2006.173.02:13:31.07#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.02:13:31.07#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.02:13:31.07#ibcon#ireg 11 cls_cnt 2 2006.173.02:13:31.07#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.02:13:31.13#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.02:13:31.13#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.02:13:31.13#ibcon#enter wrdev, iclass 6, count 2 2006.173.02:13:31.13#ibcon#first serial, iclass 6, count 2 2006.173.02:13:31.13#ibcon#enter sib2, iclass 6, count 2 2006.173.02:13:31.13#ibcon#flushed, iclass 6, count 2 2006.173.02:13:31.13#ibcon#about to write, iclass 6, count 2 2006.173.02:13:31.13#ibcon#wrote, iclass 6, count 2 2006.173.02:13:31.13#ibcon#about to read 3, iclass 6, count 2 2006.173.02:13:31.15#ibcon#read 3, iclass 6, count 2 2006.173.02:13:31.15#ibcon#about to read 4, iclass 6, count 2 2006.173.02:13:31.15#ibcon#read 4, iclass 6, count 2 2006.173.02:13:31.15#ibcon#about to read 5, iclass 6, count 2 2006.173.02:13:31.15#ibcon#read 5, iclass 6, count 2 2006.173.02:13:31.15#ibcon#about to read 6, iclass 6, count 2 2006.173.02:13:31.15#ibcon#read 6, iclass 6, count 2 2006.173.02:13:31.15#ibcon#end of sib2, iclass 6, count 2 2006.173.02:13:31.15#ibcon#*mode == 0, iclass 6, count 2 2006.173.02:13:31.15#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.02:13:31.15#ibcon#[27=AT06-04\r\n] 2006.173.02:13:31.15#ibcon#*before write, iclass 6, count 2 2006.173.02:13:31.15#ibcon#enter sib2, iclass 6, count 2 2006.173.02:13:31.15#ibcon#flushed, iclass 6, count 2 2006.173.02:13:31.15#ibcon#about to write, iclass 6, count 2 2006.173.02:13:31.15#ibcon#wrote, iclass 6, count 2 2006.173.02:13:31.15#ibcon#about to read 3, iclass 6, count 2 2006.173.02:13:31.18#ibcon#read 3, iclass 6, count 2 2006.173.02:13:31.18#ibcon#about to read 4, iclass 6, count 2 2006.173.02:13:31.18#ibcon#read 4, iclass 6, count 2 2006.173.02:13:31.18#ibcon#about to read 5, iclass 6, count 2 2006.173.02:13:31.18#ibcon#read 5, iclass 6, count 2 2006.173.02:13:31.18#ibcon#about to read 6, iclass 6, count 2 2006.173.02:13:31.18#ibcon#read 6, iclass 6, count 2 2006.173.02:13:31.18#ibcon#end of sib2, iclass 6, count 2 2006.173.02:13:31.18#ibcon#*after write, iclass 6, count 2 2006.173.02:13:31.18#ibcon#*before return 0, iclass 6, count 2 2006.173.02:13:31.18#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.02:13:31.18#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.02:13:31.18#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.02:13:31.18#ibcon#ireg 7 cls_cnt 0 2006.173.02:13:31.18#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.02:13:31.30#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.02:13:31.30#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.02:13:31.30#ibcon#enter wrdev, iclass 6, count 0 2006.173.02:13:31.30#ibcon#first serial, iclass 6, count 0 2006.173.02:13:31.30#ibcon#enter sib2, iclass 6, count 0 2006.173.02:13:31.30#ibcon#flushed, iclass 6, count 0 2006.173.02:13:31.30#ibcon#about to write, iclass 6, count 0 2006.173.02:13:31.30#ibcon#wrote, iclass 6, count 0 2006.173.02:13:31.30#ibcon#about to read 3, iclass 6, count 0 2006.173.02:13:31.32#ibcon#read 3, iclass 6, count 0 2006.173.02:13:31.32#ibcon#about to read 4, iclass 6, count 0 2006.173.02:13:31.32#ibcon#read 4, iclass 6, count 0 2006.173.02:13:31.32#ibcon#about to read 5, iclass 6, count 0 2006.173.02:13:31.32#ibcon#read 5, iclass 6, count 0 2006.173.02:13:31.32#ibcon#about to read 6, iclass 6, count 0 2006.173.02:13:31.32#ibcon#read 6, iclass 6, count 0 2006.173.02:13:31.32#ibcon#end of sib2, iclass 6, count 0 2006.173.02:13:31.32#ibcon#*mode == 0, iclass 6, count 0 2006.173.02:13:31.32#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.02:13:31.32#ibcon#[27=USB\r\n] 2006.173.02:13:31.32#ibcon#*before write, iclass 6, count 0 2006.173.02:13:31.32#ibcon#enter sib2, iclass 6, count 0 2006.173.02:13:31.32#ibcon#flushed, iclass 6, count 0 2006.173.02:13:31.32#ibcon#about to write, iclass 6, count 0 2006.173.02:13:31.32#ibcon#wrote, iclass 6, count 0 2006.173.02:13:31.32#ibcon#about to read 3, iclass 6, count 0 2006.173.02:13:31.35#ibcon#read 3, iclass 6, count 0 2006.173.02:13:31.35#ibcon#about to read 4, iclass 6, count 0 2006.173.02:13:31.35#ibcon#read 4, iclass 6, count 0 2006.173.02:13:31.35#ibcon#about to read 5, iclass 6, count 0 2006.173.02:13:31.35#ibcon#read 5, iclass 6, count 0 2006.173.02:13:31.35#ibcon#about to read 6, iclass 6, count 0 2006.173.02:13:31.35#ibcon#read 6, iclass 6, count 0 2006.173.02:13:31.35#ibcon#end of sib2, iclass 6, count 0 2006.173.02:13:31.35#ibcon#*after write, iclass 6, count 0 2006.173.02:13:31.35#ibcon#*before return 0, iclass 6, count 0 2006.173.02:13:31.35#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.02:13:31.35#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.02:13:31.35#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.02:13:31.35#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.02:13:31.35$vck44/vblo=7,734.99 2006.173.02:13:31.35#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.02:13:31.35#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.02:13:31.35#ibcon#ireg 17 cls_cnt 0 2006.173.02:13:31.35#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.02:13:31.35#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.02:13:31.35#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.02:13:31.35#ibcon#enter wrdev, iclass 10, count 0 2006.173.02:13:31.35#ibcon#first serial, iclass 10, count 0 2006.173.02:13:31.35#ibcon#enter sib2, iclass 10, count 0 2006.173.02:13:31.35#ibcon#flushed, iclass 10, count 0 2006.173.02:13:31.35#ibcon#about to write, iclass 10, count 0 2006.173.02:13:31.35#ibcon#wrote, iclass 10, count 0 2006.173.02:13:31.35#ibcon#about to read 3, iclass 10, count 0 2006.173.02:13:31.37#ibcon#read 3, iclass 10, count 0 2006.173.02:13:31.37#ibcon#about to read 4, iclass 10, count 0 2006.173.02:13:31.37#ibcon#read 4, iclass 10, count 0 2006.173.02:13:31.37#ibcon#about to read 5, iclass 10, count 0 2006.173.02:13:31.37#ibcon#read 5, iclass 10, count 0 2006.173.02:13:31.37#ibcon#about to read 6, iclass 10, count 0 2006.173.02:13:31.37#ibcon#read 6, iclass 10, count 0 2006.173.02:13:31.37#ibcon#end of sib2, iclass 10, count 0 2006.173.02:13:31.37#ibcon#*mode == 0, iclass 10, count 0 2006.173.02:13:31.37#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.02:13:31.37#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.02:13:31.37#ibcon#*before write, iclass 10, count 0 2006.173.02:13:31.37#ibcon#enter sib2, iclass 10, count 0 2006.173.02:13:31.37#ibcon#flushed, iclass 10, count 0 2006.173.02:13:31.37#ibcon#about to write, iclass 10, count 0 2006.173.02:13:31.37#ibcon#wrote, iclass 10, count 0 2006.173.02:13:31.37#ibcon#about to read 3, iclass 10, count 0 2006.173.02:13:31.41#ibcon#read 3, iclass 10, count 0 2006.173.02:13:31.41#ibcon#about to read 4, iclass 10, count 0 2006.173.02:13:31.41#ibcon#read 4, iclass 10, count 0 2006.173.02:13:31.41#ibcon#about to read 5, iclass 10, count 0 2006.173.02:13:31.41#ibcon#read 5, iclass 10, count 0 2006.173.02:13:31.41#ibcon#about to read 6, iclass 10, count 0 2006.173.02:13:31.41#ibcon#read 6, iclass 10, count 0 2006.173.02:13:31.41#ibcon#end of sib2, iclass 10, count 0 2006.173.02:13:31.41#ibcon#*after write, iclass 10, count 0 2006.173.02:13:31.41#ibcon#*before return 0, iclass 10, count 0 2006.173.02:13:31.41#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.02:13:31.41#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.02:13:31.41#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.02:13:31.41#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.02:13:31.41$vck44/vb=7,4 2006.173.02:13:31.41#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.02:13:31.41#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.02:13:31.41#ibcon#ireg 11 cls_cnt 2 2006.173.02:13:31.41#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.02:13:31.47#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.02:13:31.47#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.02:13:31.47#ibcon#enter wrdev, iclass 12, count 2 2006.173.02:13:31.47#ibcon#first serial, iclass 12, count 2 2006.173.02:13:31.47#ibcon#enter sib2, iclass 12, count 2 2006.173.02:13:31.47#ibcon#flushed, iclass 12, count 2 2006.173.02:13:31.47#ibcon#about to write, iclass 12, count 2 2006.173.02:13:31.47#ibcon#wrote, iclass 12, count 2 2006.173.02:13:31.47#ibcon#about to read 3, iclass 12, count 2 2006.173.02:13:31.49#ibcon#read 3, iclass 12, count 2 2006.173.02:13:31.49#ibcon#about to read 4, iclass 12, count 2 2006.173.02:13:31.49#ibcon#read 4, iclass 12, count 2 2006.173.02:13:31.49#ibcon#about to read 5, iclass 12, count 2 2006.173.02:13:31.49#ibcon#read 5, iclass 12, count 2 2006.173.02:13:31.49#ibcon#about to read 6, iclass 12, count 2 2006.173.02:13:31.49#ibcon#read 6, iclass 12, count 2 2006.173.02:13:31.49#ibcon#end of sib2, iclass 12, count 2 2006.173.02:13:31.49#ibcon#*mode == 0, iclass 12, count 2 2006.173.02:13:31.49#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.02:13:31.49#ibcon#[27=AT07-04\r\n] 2006.173.02:13:31.49#ibcon#*before write, iclass 12, count 2 2006.173.02:13:31.49#ibcon#enter sib2, iclass 12, count 2 2006.173.02:13:31.49#ibcon#flushed, iclass 12, count 2 2006.173.02:13:31.49#ibcon#about to write, iclass 12, count 2 2006.173.02:13:31.49#ibcon#wrote, iclass 12, count 2 2006.173.02:13:31.49#ibcon#about to read 3, iclass 12, count 2 2006.173.02:13:31.52#ibcon#read 3, iclass 12, count 2 2006.173.02:13:31.52#ibcon#about to read 4, iclass 12, count 2 2006.173.02:13:31.52#ibcon#read 4, iclass 12, count 2 2006.173.02:13:31.52#ibcon#about to read 5, iclass 12, count 2 2006.173.02:13:31.52#ibcon#read 5, iclass 12, count 2 2006.173.02:13:31.52#ibcon#about to read 6, iclass 12, count 2 2006.173.02:13:31.52#ibcon#read 6, iclass 12, count 2 2006.173.02:13:31.52#ibcon#end of sib2, iclass 12, count 2 2006.173.02:13:31.52#ibcon#*after write, iclass 12, count 2 2006.173.02:13:31.52#ibcon#*before return 0, iclass 12, count 2 2006.173.02:13:31.52#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.02:13:31.52#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.02:13:31.52#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.02:13:31.52#ibcon#ireg 7 cls_cnt 0 2006.173.02:13:31.52#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.02:13:31.64#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.02:13:31.64#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.02:13:31.64#ibcon#enter wrdev, iclass 12, count 0 2006.173.02:13:31.64#ibcon#first serial, iclass 12, count 0 2006.173.02:13:31.64#ibcon#enter sib2, iclass 12, count 0 2006.173.02:13:31.64#ibcon#flushed, iclass 12, count 0 2006.173.02:13:31.64#ibcon#about to write, iclass 12, count 0 2006.173.02:13:31.64#ibcon#wrote, iclass 12, count 0 2006.173.02:13:31.64#ibcon#about to read 3, iclass 12, count 0 2006.173.02:13:31.66#ibcon#read 3, iclass 12, count 0 2006.173.02:13:31.66#ibcon#about to read 4, iclass 12, count 0 2006.173.02:13:31.66#ibcon#read 4, iclass 12, count 0 2006.173.02:13:31.66#ibcon#about to read 5, iclass 12, count 0 2006.173.02:13:31.66#ibcon#read 5, iclass 12, count 0 2006.173.02:13:31.66#ibcon#about to read 6, iclass 12, count 0 2006.173.02:13:31.66#ibcon#read 6, iclass 12, count 0 2006.173.02:13:31.66#ibcon#end of sib2, iclass 12, count 0 2006.173.02:13:31.66#ibcon#*mode == 0, iclass 12, count 0 2006.173.02:13:31.66#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.02:13:31.66#ibcon#[27=USB\r\n] 2006.173.02:13:31.66#ibcon#*before write, iclass 12, count 0 2006.173.02:13:31.66#ibcon#enter sib2, iclass 12, count 0 2006.173.02:13:31.66#ibcon#flushed, iclass 12, count 0 2006.173.02:13:31.66#ibcon#about to write, iclass 12, count 0 2006.173.02:13:31.66#ibcon#wrote, iclass 12, count 0 2006.173.02:13:31.66#ibcon#about to read 3, iclass 12, count 0 2006.173.02:13:31.69#ibcon#read 3, iclass 12, count 0 2006.173.02:13:31.69#ibcon#about to read 4, iclass 12, count 0 2006.173.02:13:31.69#ibcon#read 4, iclass 12, count 0 2006.173.02:13:31.69#ibcon#about to read 5, iclass 12, count 0 2006.173.02:13:31.69#ibcon#read 5, iclass 12, count 0 2006.173.02:13:31.69#ibcon#about to read 6, iclass 12, count 0 2006.173.02:13:31.69#ibcon#read 6, iclass 12, count 0 2006.173.02:13:31.69#ibcon#end of sib2, iclass 12, count 0 2006.173.02:13:31.69#ibcon#*after write, iclass 12, count 0 2006.173.02:13:31.69#ibcon#*before return 0, iclass 12, count 0 2006.173.02:13:31.69#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.02:13:31.69#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.02:13:31.69#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.02:13:31.69#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.02:13:31.69$vck44/vblo=8,744.99 2006.173.02:13:31.69#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.02:13:31.69#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.02:13:31.69#ibcon#ireg 17 cls_cnt 0 2006.173.02:13:31.69#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.02:13:31.69#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.02:13:31.69#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.02:13:31.69#ibcon#enter wrdev, iclass 14, count 0 2006.173.02:13:31.69#ibcon#first serial, iclass 14, count 0 2006.173.02:13:31.69#ibcon#enter sib2, iclass 14, count 0 2006.173.02:13:31.69#ibcon#flushed, iclass 14, count 0 2006.173.02:13:31.69#ibcon#about to write, iclass 14, count 0 2006.173.02:13:31.69#ibcon#wrote, iclass 14, count 0 2006.173.02:13:31.69#ibcon#about to read 3, iclass 14, count 0 2006.173.02:13:31.71#ibcon#read 3, iclass 14, count 0 2006.173.02:13:31.71#ibcon#about to read 4, iclass 14, count 0 2006.173.02:13:31.71#ibcon#read 4, iclass 14, count 0 2006.173.02:13:31.71#ibcon#about to read 5, iclass 14, count 0 2006.173.02:13:31.71#ibcon#read 5, iclass 14, count 0 2006.173.02:13:31.71#ibcon#about to read 6, iclass 14, count 0 2006.173.02:13:31.71#ibcon#read 6, iclass 14, count 0 2006.173.02:13:31.71#ibcon#end of sib2, iclass 14, count 0 2006.173.02:13:31.71#ibcon#*mode == 0, iclass 14, count 0 2006.173.02:13:31.71#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.02:13:31.71#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.02:13:31.71#ibcon#*before write, iclass 14, count 0 2006.173.02:13:31.71#ibcon#enter sib2, iclass 14, count 0 2006.173.02:13:31.71#ibcon#flushed, iclass 14, count 0 2006.173.02:13:31.71#ibcon#about to write, iclass 14, count 0 2006.173.02:13:31.71#ibcon#wrote, iclass 14, count 0 2006.173.02:13:31.71#ibcon#about to read 3, iclass 14, count 0 2006.173.02:13:31.75#ibcon#read 3, iclass 14, count 0 2006.173.02:13:31.75#ibcon#about to read 4, iclass 14, count 0 2006.173.02:13:31.75#ibcon#read 4, iclass 14, count 0 2006.173.02:13:31.75#ibcon#about to read 5, iclass 14, count 0 2006.173.02:13:31.75#ibcon#read 5, iclass 14, count 0 2006.173.02:13:31.75#ibcon#about to read 6, iclass 14, count 0 2006.173.02:13:31.75#ibcon#read 6, iclass 14, count 0 2006.173.02:13:31.75#ibcon#end of sib2, iclass 14, count 0 2006.173.02:13:31.75#ibcon#*after write, iclass 14, count 0 2006.173.02:13:31.75#ibcon#*before return 0, iclass 14, count 0 2006.173.02:13:31.75#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.02:13:31.75#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.02:13:31.75#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.02:13:31.75#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.02:13:31.75$vck44/vb=8,4 2006.173.02:13:31.75#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.02:13:31.75#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.02:13:31.75#ibcon#ireg 11 cls_cnt 2 2006.173.02:13:31.75#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.02:13:31.81#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.02:13:31.81#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.02:13:31.81#ibcon#enter wrdev, iclass 16, count 2 2006.173.02:13:31.81#ibcon#first serial, iclass 16, count 2 2006.173.02:13:31.81#ibcon#enter sib2, iclass 16, count 2 2006.173.02:13:31.81#ibcon#flushed, iclass 16, count 2 2006.173.02:13:31.81#ibcon#about to write, iclass 16, count 2 2006.173.02:13:31.81#ibcon#wrote, iclass 16, count 2 2006.173.02:13:31.81#ibcon#about to read 3, iclass 16, count 2 2006.173.02:13:31.83#ibcon#read 3, iclass 16, count 2 2006.173.02:13:31.83#ibcon#about to read 4, iclass 16, count 2 2006.173.02:13:31.83#ibcon#read 4, iclass 16, count 2 2006.173.02:13:31.83#ibcon#about to read 5, iclass 16, count 2 2006.173.02:13:31.83#ibcon#read 5, iclass 16, count 2 2006.173.02:13:31.83#ibcon#about to read 6, iclass 16, count 2 2006.173.02:13:31.83#ibcon#read 6, iclass 16, count 2 2006.173.02:13:31.83#ibcon#end of sib2, iclass 16, count 2 2006.173.02:13:31.83#ibcon#*mode == 0, iclass 16, count 2 2006.173.02:13:31.83#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.02:13:31.83#ibcon#[27=AT08-04\r\n] 2006.173.02:13:31.83#ibcon#*before write, iclass 16, count 2 2006.173.02:13:31.83#ibcon#enter sib2, iclass 16, count 2 2006.173.02:13:31.83#ibcon#flushed, iclass 16, count 2 2006.173.02:13:31.83#ibcon#about to write, iclass 16, count 2 2006.173.02:13:31.83#ibcon#wrote, iclass 16, count 2 2006.173.02:13:31.83#ibcon#about to read 3, iclass 16, count 2 2006.173.02:13:31.86#ibcon#read 3, iclass 16, count 2 2006.173.02:13:31.86#ibcon#about to read 4, iclass 16, count 2 2006.173.02:13:31.86#ibcon#read 4, iclass 16, count 2 2006.173.02:13:31.86#ibcon#about to read 5, iclass 16, count 2 2006.173.02:13:31.86#ibcon#read 5, iclass 16, count 2 2006.173.02:13:31.86#ibcon#about to read 6, iclass 16, count 2 2006.173.02:13:31.86#ibcon#read 6, iclass 16, count 2 2006.173.02:13:31.86#ibcon#end of sib2, iclass 16, count 2 2006.173.02:13:31.86#ibcon#*after write, iclass 16, count 2 2006.173.02:13:31.86#ibcon#*before return 0, iclass 16, count 2 2006.173.02:13:31.86#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.02:13:31.86#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.02:13:31.86#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.02:13:31.86#ibcon#ireg 7 cls_cnt 0 2006.173.02:13:31.86#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.02:13:31.98#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.02:13:31.98#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.02:13:31.98#ibcon#enter wrdev, iclass 16, count 0 2006.173.02:13:31.98#ibcon#first serial, iclass 16, count 0 2006.173.02:13:31.98#ibcon#enter sib2, iclass 16, count 0 2006.173.02:13:31.98#ibcon#flushed, iclass 16, count 0 2006.173.02:13:31.98#ibcon#about to write, iclass 16, count 0 2006.173.02:13:31.98#ibcon#wrote, iclass 16, count 0 2006.173.02:13:31.98#ibcon#about to read 3, iclass 16, count 0 2006.173.02:13:32.00#ibcon#read 3, iclass 16, count 0 2006.173.02:13:32.00#ibcon#about to read 4, iclass 16, count 0 2006.173.02:13:32.00#ibcon#read 4, iclass 16, count 0 2006.173.02:13:32.00#ibcon#about to read 5, iclass 16, count 0 2006.173.02:13:32.00#ibcon#read 5, iclass 16, count 0 2006.173.02:13:32.00#ibcon#about to read 6, iclass 16, count 0 2006.173.02:13:32.00#ibcon#read 6, iclass 16, count 0 2006.173.02:13:32.00#ibcon#end of sib2, iclass 16, count 0 2006.173.02:13:32.00#ibcon#*mode == 0, iclass 16, count 0 2006.173.02:13:32.00#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.02:13:32.00#ibcon#[27=USB\r\n] 2006.173.02:13:32.00#ibcon#*before write, iclass 16, count 0 2006.173.02:13:32.00#ibcon#enter sib2, iclass 16, count 0 2006.173.02:13:32.00#ibcon#flushed, iclass 16, count 0 2006.173.02:13:32.00#ibcon#about to write, iclass 16, count 0 2006.173.02:13:32.00#ibcon#wrote, iclass 16, count 0 2006.173.02:13:32.00#ibcon#about to read 3, iclass 16, count 0 2006.173.02:13:32.03#ibcon#read 3, iclass 16, count 0 2006.173.02:13:32.03#ibcon#about to read 4, iclass 16, count 0 2006.173.02:13:32.03#ibcon#read 4, iclass 16, count 0 2006.173.02:13:32.03#ibcon#about to read 5, iclass 16, count 0 2006.173.02:13:32.03#ibcon#read 5, iclass 16, count 0 2006.173.02:13:32.03#ibcon#about to read 6, iclass 16, count 0 2006.173.02:13:32.03#ibcon#read 6, iclass 16, count 0 2006.173.02:13:32.03#ibcon#end of sib2, iclass 16, count 0 2006.173.02:13:32.03#ibcon#*after write, iclass 16, count 0 2006.173.02:13:32.03#ibcon#*before return 0, iclass 16, count 0 2006.173.02:13:32.03#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.02:13:32.03#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.02:13:32.03#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.02:13:32.03#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.02:13:32.03$vck44/vabw=wide 2006.173.02:13:32.03#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.02:13:32.03#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.02:13:32.03#ibcon#ireg 8 cls_cnt 0 2006.173.02:13:32.03#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.02:13:32.03#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.02:13:32.03#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.02:13:32.03#ibcon#enter wrdev, iclass 18, count 0 2006.173.02:13:32.03#ibcon#first serial, iclass 18, count 0 2006.173.02:13:32.03#ibcon#enter sib2, iclass 18, count 0 2006.173.02:13:32.03#ibcon#flushed, iclass 18, count 0 2006.173.02:13:32.03#ibcon#about to write, iclass 18, count 0 2006.173.02:13:32.03#ibcon#wrote, iclass 18, count 0 2006.173.02:13:32.03#ibcon#about to read 3, iclass 18, count 0 2006.173.02:13:32.05#ibcon#read 3, iclass 18, count 0 2006.173.02:13:32.05#ibcon#about to read 4, iclass 18, count 0 2006.173.02:13:32.05#ibcon#read 4, iclass 18, count 0 2006.173.02:13:32.05#ibcon#about to read 5, iclass 18, count 0 2006.173.02:13:32.05#ibcon#read 5, iclass 18, count 0 2006.173.02:13:32.05#ibcon#about to read 6, iclass 18, count 0 2006.173.02:13:32.05#ibcon#read 6, iclass 18, count 0 2006.173.02:13:32.05#ibcon#end of sib2, iclass 18, count 0 2006.173.02:13:32.05#ibcon#*mode == 0, iclass 18, count 0 2006.173.02:13:32.05#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.02:13:32.05#ibcon#[25=BW32\r\n] 2006.173.02:13:32.05#ibcon#*before write, iclass 18, count 0 2006.173.02:13:32.05#ibcon#enter sib2, iclass 18, count 0 2006.173.02:13:32.05#ibcon#flushed, iclass 18, count 0 2006.173.02:13:32.05#ibcon#about to write, iclass 18, count 0 2006.173.02:13:32.05#ibcon#wrote, iclass 18, count 0 2006.173.02:13:32.05#ibcon#about to read 3, iclass 18, count 0 2006.173.02:13:32.08#ibcon#read 3, iclass 18, count 0 2006.173.02:13:32.08#ibcon#about to read 4, iclass 18, count 0 2006.173.02:13:32.08#ibcon#read 4, iclass 18, count 0 2006.173.02:13:32.08#ibcon#about to read 5, iclass 18, count 0 2006.173.02:13:32.08#ibcon#read 5, iclass 18, count 0 2006.173.02:13:32.08#ibcon#about to read 6, iclass 18, count 0 2006.173.02:13:32.08#ibcon#read 6, iclass 18, count 0 2006.173.02:13:32.08#ibcon#end of sib2, iclass 18, count 0 2006.173.02:13:32.08#ibcon#*after write, iclass 18, count 0 2006.173.02:13:32.08#ibcon#*before return 0, iclass 18, count 0 2006.173.02:13:32.08#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.02:13:32.08#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.02:13:32.08#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.02:13:32.08#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.02:13:32.08$vck44/vbbw=wide 2006.173.02:13:32.08#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.02:13:32.08#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.02:13:32.08#ibcon#ireg 8 cls_cnt 0 2006.173.02:13:32.08#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.02:13:32.15#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.02:13:32.15#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.02:13:32.15#ibcon#enter wrdev, iclass 20, count 0 2006.173.02:13:32.15#ibcon#first serial, iclass 20, count 0 2006.173.02:13:32.15#ibcon#enter sib2, iclass 20, count 0 2006.173.02:13:32.15#ibcon#flushed, iclass 20, count 0 2006.173.02:13:32.15#ibcon#about to write, iclass 20, count 0 2006.173.02:13:32.15#ibcon#wrote, iclass 20, count 0 2006.173.02:13:32.15#ibcon#about to read 3, iclass 20, count 0 2006.173.02:13:32.17#ibcon#read 3, iclass 20, count 0 2006.173.02:13:32.17#ibcon#about to read 4, iclass 20, count 0 2006.173.02:13:32.17#ibcon#read 4, iclass 20, count 0 2006.173.02:13:32.17#ibcon#about to read 5, iclass 20, count 0 2006.173.02:13:32.17#ibcon#read 5, iclass 20, count 0 2006.173.02:13:32.17#ibcon#about to read 6, iclass 20, count 0 2006.173.02:13:32.17#ibcon#read 6, iclass 20, count 0 2006.173.02:13:32.17#ibcon#end of sib2, iclass 20, count 0 2006.173.02:13:32.17#ibcon#*mode == 0, iclass 20, count 0 2006.173.02:13:32.17#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.02:13:32.17#ibcon#[27=BW32\r\n] 2006.173.02:13:32.17#ibcon#*before write, iclass 20, count 0 2006.173.02:13:32.17#ibcon#enter sib2, iclass 20, count 0 2006.173.02:13:32.17#ibcon#flushed, iclass 20, count 0 2006.173.02:13:32.17#ibcon#about to write, iclass 20, count 0 2006.173.02:13:32.17#ibcon#wrote, iclass 20, count 0 2006.173.02:13:32.17#ibcon#about to read 3, iclass 20, count 0 2006.173.02:13:32.20#ibcon#read 3, iclass 20, count 0 2006.173.02:13:32.20#ibcon#about to read 4, iclass 20, count 0 2006.173.02:13:32.20#ibcon#read 4, iclass 20, count 0 2006.173.02:13:32.20#ibcon#about to read 5, iclass 20, count 0 2006.173.02:13:32.20#ibcon#read 5, iclass 20, count 0 2006.173.02:13:32.20#ibcon#about to read 6, iclass 20, count 0 2006.173.02:13:32.20#ibcon#read 6, iclass 20, count 0 2006.173.02:13:32.20#ibcon#end of sib2, iclass 20, count 0 2006.173.02:13:32.20#ibcon#*after write, iclass 20, count 0 2006.173.02:13:32.20#ibcon#*before return 0, iclass 20, count 0 2006.173.02:13:32.20#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.02:13:32.20#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.02:13:32.20#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.02:13:32.20#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.02:13:32.20$setupk4/ifdk4 2006.173.02:13:32.20$ifdk4/lo= 2006.173.02:13:32.20$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.02:13:32.20$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.02:13:32.20$ifdk4/patch= 2006.173.02:13:32.20$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.02:13:32.20$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.02:13:32.20$setupk4/!*+20s 2006.173.02:13:32.26#abcon#<5=/14 1.2 2.4 22.69 831006.5\r\n> 2006.173.02:13:32.28#abcon#{5=INTERFACE CLEAR} 2006.173.02:13:32.34#abcon#[5=S1D000X0/0*\r\n] 2006.173.02:13:42.43#abcon#<5=/14 1.2 2.4 22.70 831006.5\r\n> 2006.173.02:13:42.45#abcon#{5=INTERFACE CLEAR} 2006.173.02:13:42.51#abcon#[5=S1D000X0/0*\r\n] 2006.173.02:13:46.66$setupk4/"tpicd 2006.173.02:13:46.66$setupk4/echo=off 2006.173.02:13:46.66$setupk4/xlog=off 2006.173.02:13:46.66:!2006.173.02:16:35 2006.173.02:14:53.14#trakl#Source acquired 2006.173.02:14:54.14#flagr#flagr/antenna,acquired 2006.173.02:16:35.00:preob 2006.173.02:16:35.13/onsource/TRACKING 2006.173.02:16:35.13:!2006.173.02:16:45 2006.173.02:16:45.00:"tape 2006.173.02:16:45.00:"st=record 2006.173.02:16:45.00:data_valid=on 2006.173.02:16:45.00:midob 2006.173.02:16:46.13/onsource/TRACKING 2006.173.02:16:46.13/wx/22.65,1006.5,82 2006.173.02:16:46.20/cable/+6.5117E-03 2006.173.02:16:47.29/va/01,07,usb,yes,36,38 2006.173.02:16:47.29/va/02,06,usb,yes,35,36 2006.173.02:16:47.29/va/03,05,usb,yes,45,47 2006.173.02:16:47.29/va/04,06,usb,yes,36,38 2006.173.02:16:47.29/va/05,04,usb,yes,28,29 2006.173.02:16:47.29/va/06,03,usb,yes,40,40 2006.173.02:16:47.29/va/07,04,usb,yes,32,33 2006.173.02:16:47.29/va/08,04,usb,yes,27,33 2006.173.02:16:47.52/valo/01,524.99,yes,locked 2006.173.02:16:47.52/valo/02,534.99,yes,locked 2006.173.02:16:47.52/valo/03,564.99,yes,locked 2006.173.02:16:47.52/valo/04,624.99,yes,locked 2006.173.02:16:47.52/valo/05,734.99,yes,locked 2006.173.02:16:47.52/valo/06,814.99,yes,locked 2006.173.02:16:47.52/valo/07,864.99,yes,locked 2006.173.02:16:47.52/valo/08,884.99,yes,locked 2006.173.02:16:48.61/vb/01,04,usb,yes,29,27 2006.173.02:16:48.61/vb/02,04,usb,yes,31,31 2006.173.02:16:48.61/vb/03,04,usb,yes,28,31 2006.173.02:16:48.61/vb/04,04,usb,yes,33,32 2006.173.02:16:48.61/vb/05,04,usb,yes,25,28 2006.173.02:16:48.61/vb/06,04,usb,yes,30,26 2006.173.02:16:48.61/vb/07,04,usb,yes,29,29 2006.173.02:16:48.61/vb/08,04,usb,yes,27,30 2006.173.02:16:48.85/vblo/01,629.99,yes,locked 2006.173.02:16:48.85/vblo/02,634.99,yes,locked 2006.173.02:16:48.85/vblo/03,649.99,yes,locked 2006.173.02:16:48.85/vblo/04,679.99,yes,locked 2006.173.02:16:48.85/vblo/05,709.99,yes,locked 2006.173.02:16:48.85/vblo/06,719.99,yes,locked 2006.173.02:16:48.85/vblo/07,734.99,yes,locked 2006.173.02:16:48.85/vblo/08,744.99,yes,locked 2006.173.02:16:49.00/vabw/8 2006.173.02:16:49.15/vbbw/8 2006.173.02:16:49.30/xfe/off,on,15.2 2006.173.02:16:49.67/ifatt/23,28,28,28 2006.173.02:16:50.07/fmout-gps/S +3.93E-07 2006.173.02:16:50.15:!2006.173.02:17:35 2006.173.02:17:35.01:data_valid=off 2006.173.02:17:35.02:"et 2006.173.02:17:35.02:!+3s 2006.173.02:17:38.03:"tape 2006.173.02:17:38.04:postob 2006.173.02:17:38.16/cable/+6.5113E-03 2006.173.02:17:38.17/wx/22.66,1006.5,83 2006.173.02:17:38.22/fmout-gps/S +3.92E-07 2006.173.02:17:38.23:scan_name=173-0219,jd0606,220 2006.173.02:17:38.23:source=1044+719,104827.62,714335.9,2000.0,cw 2006.173.02:17:39.13#flagr#flagr/antenna,new-source 2006.173.02:17:39.14:checkk5 2006.173.02:17:39.54/chk_autoobs//k5ts1/ autoobs is running! 2006.173.02:17:39.96/chk_autoobs//k5ts2/ autoobs is running! 2006.173.02:17:40.38/chk_autoobs//k5ts3/ autoobs is running! 2006.173.02:17:41.01/chk_autoobs//k5ts4/ autoobs is running! 2006.173.02:17:41.63/chk_obsdata//k5ts1/T1730216??a.dat file size is correct (nominal:200MB, actual:196MB). 2006.173.02:17:42.07/chk_obsdata//k5ts2/T1730216??b.dat file size is correct (nominal:200MB, actual:196MB). 2006.173.02:17:42.49/chk_obsdata//k5ts3/T1730216??c.dat file size is correct (nominal:200MB, actual:196MB). 2006.173.02:17:42.86/chk_obsdata//k5ts4/T1730216??d.dat file size is correct (nominal:200MB, actual:196MB). 2006.173.02:17:43.75/k5log//k5ts1_log_newline 2006.173.02:17:44.79/k5log//k5ts2_log_newline 2006.173.02:17:45.77/k5log//k5ts3_log_newline 2006.173.02:17:46.57/k5log//k5ts4_log_newline 2006.173.02:17:46.59/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.02:17:46.59:setupk4=1 2006.173.02:17:46.59$setupk4/echo=on 2006.173.02:17:46.59$setupk4/pcalon 2006.173.02:17:46.59$pcalon/"no phase cal control is implemented here 2006.173.02:17:46.59$setupk4/"tpicd=stop 2006.173.02:17:46.59$setupk4/"rec=synch_on 2006.173.02:17:46.59$setupk4/"rec_mode=128 2006.173.02:17:46.59$setupk4/!* 2006.173.02:17:46.59$setupk4/recpk4 2006.173.02:17:46.59$recpk4/recpatch= 2006.173.02:17:46.59$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.02:17:46.59$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.02:17:46.59$setupk4/vck44 2006.173.02:17:46.59$vck44/valo=1,524.99 2006.173.02:17:46.59#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.02:17:46.59#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.02:17:46.59#ibcon#ireg 17 cls_cnt 0 2006.173.02:17:46.59#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.02:17:46.60#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.02:17:46.60#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.02:17:46.60#ibcon#enter wrdev, iclass 21, count 0 2006.173.02:17:46.60#ibcon#first serial, iclass 21, count 0 2006.173.02:17:46.60#ibcon#enter sib2, iclass 21, count 0 2006.173.02:17:46.60#ibcon#flushed, iclass 21, count 0 2006.173.02:17:46.60#ibcon#about to write, iclass 21, count 0 2006.173.02:17:46.60#ibcon#wrote, iclass 21, count 0 2006.173.02:17:46.60#ibcon#about to read 3, iclass 21, count 0 2006.173.02:17:46.64#ibcon#read 3, iclass 21, count 0 2006.173.02:17:46.64#ibcon#about to read 4, iclass 21, count 0 2006.173.02:17:46.64#ibcon#read 4, iclass 21, count 0 2006.173.02:17:46.64#ibcon#about to read 5, iclass 21, count 0 2006.173.02:17:46.64#ibcon#read 5, iclass 21, count 0 2006.173.02:17:46.64#ibcon#about to read 6, iclass 21, count 0 2006.173.02:17:46.64#ibcon#read 6, iclass 21, count 0 2006.173.02:17:46.64#ibcon#end of sib2, iclass 21, count 0 2006.173.02:17:46.64#ibcon#*mode == 0, iclass 21, count 0 2006.173.02:17:46.64#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.02:17:46.64#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.02:17:46.64#ibcon#*before write, iclass 21, count 0 2006.173.02:17:46.64#ibcon#enter sib2, iclass 21, count 0 2006.173.02:17:46.64#ibcon#flushed, iclass 21, count 0 2006.173.02:17:46.64#ibcon#about to write, iclass 21, count 0 2006.173.02:17:46.64#ibcon#wrote, iclass 21, count 0 2006.173.02:17:46.64#ibcon#about to read 3, iclass 21, count 0 2006.173.02:17:46.68#ibcon#read 3, iclass 21, count 0 2006.173.02:17:46.68#ibcon#about to read 4, iclass 21, count 0 2006.173.02:17:46.68#ibcon#read 4, iclass 21, count 0 2006.173.02:17:46.68#ibcon#about to read 5, iclass 21, count 0 2006.173.02:17:46.68#ibcon#read 5, iclass 21, count 0 2006.173.02:17:46.68#ibcon#about to read 6, iclass 21, count 0 2006.173.02:17:46.68#ibcon#read 6, iclass 21, count 0 2006.173.02:17:46.68#ibcon#end of sib2, iclass 21, count 0 2006.173.02:17:46.68#ibcon#*after write, iclass 21, count 0 2006.173.02:17:46.68#ibcon#*before return 0, iclass 21, count 0 2006.173.02:17:46.68#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.02:17:46.68#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.02:17:46.68#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.02:17:46.68#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.02:17:46.68$vck44/va=1,7 2006.173.02:17:46.68#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.02:17:46.68#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.02:17:46.68#ibcon#ireg 11 cls_cnt 2 2006.173.02:17:46.68#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.02:17:46.68#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.02:17:46.68#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.02:17:46.68#ibcon#enter wrdev, iclass 23, count 2 2006.173.02:17:46.68#ibcon#first serial, iclass 23, count 2 2006.173.02:17:46.68#ibcon#enter sib2, iclass 23, count 2 2006.173.02:17:46.68#ibcon#flushed, iclass 23, count 2 2006.173.02:17:46.68#ibcon#about to write, iclass 23, count 2 2006.173.02:17:46.68#ibcon#wrote, iclass 23, count 2 2006.173.02:17:46.68#ibcon#about to read 3, iclass 23, count 2 2006.173.02:17:46.70#ibcon#read 3, iclass 23, count 2 2006.173.02:17:46.70#ibcon#about to read 4, iclass 23, count 2 2006.173.02:17:46.70#ibcon#read 4, iclass 23, count 2 2006.173.02:17:46.70#ibcon#about to read 5, iclass 23, count 2 2006.173.02:17:46.70#ibcon#read 5, iclass 23, count 2 2006.173.02:17:46.70#ibcon#about to read 6, iclass 23, count 2 2006.173.02:17:46.70#ibcon#read 6, iclass 23, count 2 2006.173.02:17:46.70#ibcon#end of sib2, iclass 23, count 2 2006.173.02:17:46.70#ibcon#*mode == 0, iclass 23, count 2 2006.173.02:17:46.70#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.02:17:46.70#ibcon#[25=AT01-07\r\n] 2006.173.02:17:46.70#ibcon#*before write, iclass 23, count 2 2006.173.02:17:46.70#ibcon#enter sib2, iclass 23, count 2 2006.173.02:17:46.70#ibcon#flushed, iclass 23, count 2 2006.173.02:17:46.70#ibcon#about to write, iclass 23, count 2 2006.173.02:17:46.70#ibcon#wrote, iclass 23, count 2 2006.173.02:17:46.70#ibcon#about to read 3, iclass 23, count 2 2006.173.02:17:46.73#ibcon#read 3, iclass 23, count 2 2006.173.02:17:46.73#ibcon#about to read 4, iclass 23, count 2 2006.173.02:17:46.73#ibcon#read 4, iclass 23, count 2 2006.173.02:17:46.73#ibcon#about to read 5, iclass 23, count 2 2006.173.02:17:46.73#ibcon#read 5, iclass 23, count 2 2006.173.02:17:46.73#ibcon#about to read 6, iclass 23, count 2 2006.173.02:17:46.73#ibcon#read 6, iclass 23, count 2 2006.173.02:17:46.73#ibcon#end of sib2, iclass 23, count 2 2006.173.02:17:46.73#ibcon#*after write, iclass 23, count 2 2006.173.02:17:46.73#ibcon#*before return 0, iclass 23, count 2 2006.173.02:17:46.73#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.02:17:46.73#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.02:17:46.73#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.02:17:46.73#ibcon#ireg 7 cls_cnt 0 2006.173.02:17:46.73#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.02:17:46.85#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.02:17:46.85#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.02:17:46.85#ibcon#enter wrdev, iclass 23, count 0 2006.173.02:17:46.85#ibcon#first serial, iclass 23, count 0 2006.173.02:17:46.85#ibcon#enter sib2, iclass 23, count 0 2006.173.02:17:46.85#ibcon#flushed, iclass 23, count 0 2006.173.02:17:46.85#ibcon#about to write, iclass 23, count 0 2006.173.02:17:46.85#ibcon#wrote, iclass 23, count 0 2006.173.02:17:46.85#ibcon#about to read 3, iclass 23, count 0 2006.173.02:17:46.87#ibcon#read 3, iclass 23, count 0 2006.173.02:17:46.87#ibcon#about to read 4, iclass 23, count 0 2006.173.02:17:46.87#ibcon#read 4, iclass 23, count 0 2006.173.02:17:46.87#ibcon#about to read 5, iclass 23, count 0 2006.173.02:17:46.87#ibcon#read 5, iclass 23, count 0 2006.173.02:17:46.87#ibcon#about to read 6, iclass 23, count 0 2006.173.02:17:46.87#ibcon#read 6, iclass 23, count 0 2006.173.02:17:46.87#ibcon#end of sib2, iclass 23, count 0 2006.173.02:17:46.87#ibcon#*mode == 0, iclass 23, count 0 2006.173.02:17:46.87#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.02:17:46.87#ibcon#[25=USB\r\n] 2006.173.02:17:46.87#ibcon#*before write, iclass 23, count 0 2006.173.02:17:46.87#ibcon#enter sib2, iclass 23, count 0 2006.173.02:17:46.87#ibcon#flushed, iclass 23, count 0 2006.173.02:17:46.87#ibcon#about to write, iclass 23, count 0 2006.173.02:17:46.87#ibcon#wrote, iclass 23, count 0 2006.173.02:17:46.87#ibcon#about to read 3, iclass 23, count 0 2006.173.02:17:46.90#ibcon#read 3, iclass 23, count 0 2006.173.02:17:46.90#ibcon#about to read 4, iclass 23, count 0 2006.173.02:17:46.90#ibcon#read 4, iclass 23, count 0 2006.173.02:17:46.90#ibcon#about to read 5, iclass 23, count 0 2006.173.02:17:46.90#ibcon#read 5, iclass 23, count 0 2006.173.02:17:46.90#ibcon#about to read 6, iclass 23, count 0 2006.173.02:17:46.90#ibcon#read 6, iclass 23, count 0 2006.173.02:17:46.90#ibcon#end of sib2, iclass 23, count 0 2006.173.02:17:46.90#ibcon#*after write, iclass 23, count 0 2006.173.02:17:46.90#ibcon#*before return 0, iclass 23, count 0 2006.173.02:17:46.90#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.02:17:46.90#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.02:17:46.90#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.02:17:46.90#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.02:17:46.90$vck44/valo=2,534.99 2006.173.02:17:46.90#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.02:17:46.90#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.02:17:46.90#ibcon#ireg 17 cls_cnt 0 2006.173.02:17:46.90#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.02:17:46.90#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.02:17:46.90#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.02:17:46.90#ibcon#enter wrdev, iclass 25, count 0 2006.173.02:17:46.90#ibcon#first serial, iclass 25, count 0 2006.173.02:17:46.90#ibcon#enter sib2, iclass 25, count 0 2006.173.02:17:46.90#ibcon#flushed, iclass 25, count 0 2006.173.02:17:46.90#ibcon#about to write, iclass 25, count 0 2006.173.02:17:46.90#ibcon#wrote, iclass 25, count 0 2006.173.02:17:46.90#ibcon#about to read 3, iclass 25, count 0 2006.173.02:17:46.92#ibcon#read 3, iclass 25, count 0 2006.173.02:17:46.92#ibcon#about to read 4, iclass 25, count 0 2006.173.02:17:46.92#ibcon#read 4, iclass 25, count 0 2006.173.02:17:46.92#ibcon#about to read 5, iclass 25, count 0 2006.173.02:17:46.92#ibcon#read 5, iclass 25, count 0 2006.173.02:17:46.92#ibcon#about to read 6, iclass 25, count 0 2006.173.02:17:46.92#ibcon#read 6, iclass 25, count 0 2006.173.02:17:46.92#ibcon#end of sib2, iclass 25, count 0 2006.173.02:17:46.92#ibcon#*mode == 0, iclass 25, count 0 2006.173.02:17:46.92#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.02:17:46.92#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.02:17:46.92#ibcon#*before write, iclass 25, count 0 2006.173.02:17:46.92#ibcon#enter sib2, iclass 25, count 0 2006.173.02:17:46.92#ibcon#flushed, iclass 25, count 0 2006.173.02:17:46.92#ibcon#about to write, iclass 25, count 0 2006.173.02:17:46.92#ibcon#wrote, iclass 25, count 0 2006.173.02:17:46.92#ibcon#about to read 3, iclass 25, count 0 2006.173.02:17:46.96#ibcon#read 3, iclass 25, count 0 2006.173.02:17:46.96#ibcon#about to read 4, iclass 25, count 0 2006.173.02:17:46.96#ibcon#read 4, iclass 25, count 0 2006.173.02:17:46.96#ibcon#about to read 5, iclass 25, count 0 2006.173.02:17:46.96#ibcon#read 5, iclass 25, count 0 2006.173.02:17:46.96#ibcon#about to read 6, iclass 25, count 0 2006.173.02:17:46.96#ibcon#read 6, iclass 25, count 0 2006.173.02:17:46.96#ibcon#end of sib2, iclass 25, count 0 2006.173.02:17:46.96#ibcon#*after write, iclass 25, count 0 2006.173.02:17:46.96#ibcon#*before return 0, iclass 25, count 0 2006.173.02:17:46.96#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.02:17:46.96#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.02:17:46.96#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.02:17:46.96#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.02:17:46.96$vck44/va=2,6 2006.173.02:17:46.96#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.02:17:46.96#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.02:17:46.96#ibcon#ireg 11 cls_cnt 2 2006.173.02:17:46.96#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.02:17:47.02#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.02:17:47.02#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.02:17:47.02#ibcon#enter wrdev, iclass 27, count 2 2006.173.02:17:47.02#ibcon#first serial, iclass 27, count 2 2006.173.02:17:47.02#ibcon#enter sib2, iclass 27, count 2 2006.173.02:17:47.02#ibcon#flushed, iclass 27, count 2 2006.173.02:17:47.02#ibcon#about to write, iclass 27, count 2 2006.173.02:17:47.02#ibcon#wrote, iclass 27, count 2 2006.173.02:17:47.02#ibcon#about to read 3, iclass 27, count 2 2006.173.02:17:47.04#ibcon#read 3, iclass 27, count 2 2006.173.02:17:47.04#ibcon#about to read 4, iclass 27, count 2 2006.173.02:17:47.04#ibcon#read 4, iclass 27, count 2 2006.173.02:17:47.04#ibcon#about to read 5, iclass 27, count 2 2006.173.02:17:47.04#ibcon#read 5, iclass 27, count 2 2006.173.02:17:47.04#ibcon#about to read 6, iclass 27, count 2 2006.173.02:17:47.04#ibcon#read 6, iclass 27, count 2 2006.173.02:17:47.04#ibcon#end of sib2, iclass 27, count 2 2006.173.02:17:47.04#ibcon#*mode == 0, iclass 27, count 2 2006.173.02:17:47.04#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.02:17:47.04#ibcon#[25=AT02-06\r\n] 2006.173.02:17:47.04#ibcon#*before write, iclass 27, count 2 2006.173.02:17:47.04#ibcon#enter sib2, iclass 27, count 2 2006.173.02:17:47.04#ibcon#flushed, iclass 27, count 2 2006.173.02:17:47.04#ibcon#about to write, iclass 27, count 2 2006.173.02:17:47.04#ibcon#wrote, iclass 27, count 2 2006.173.02:17:47.04#ibcon#about to read 3, iclass 27, count 2 2006.173.02:17:47.07#ibcon#read 3, iclass 27, count 2 2006.173.02:17:47.07#ibcon#about to read 4, iclass 27, count 2 2006.173.02:17:47.07#ibcon#read 4, iclass 27, count 2 2006.173.02:17:47.07#ibcon#about to read 5, iclass 27, count 2 2006.173.02:17:47.07#ibcon#read 5, iclass 27, count 2 2006.173.02:17:47.07#ibcon#about to read 6, iclass 27, count 2 2006.173.02:17:47.07#ibcon#read 6, iclass 27, count 2 2006.173.02:17:47.07#ibcon#end of sib2, iclass 27, count 2 2006.173.02:17:47.07#ibcon#*after write, iclass 27, count 2 2006.173.02:17:47.07#ibcon#*before return 0, iclass 27, count 2 2006.173.02:17:47.07#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.02:17:47.07#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.02:17:47.07#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.02:17:47.07#ibcon#ireg 7 cls_cnt 0 2006.173.02:17:47.07#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.02:17:47.19#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.02:17:47.19#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.02:17:47.19#ibcon#enter wrdev, iclass 27, count 0 2006.173.02:17:47.19#ibcon#first serial, iclass 27, count 0 2006.173.02:17:47.19#ibcon#enter sib2, iclass 27, count 0 2006.173.02:17:47.19#ibcon#flushed, iclass 27, count 0 2006.173.02:17:47.19#ibcon#about to write, iclass 27, count 0 2006.173.02:17:47.19#ibcon#wrote, iclass 27, count 0 2006.173.02:17:47.19#ibcon#about to read 3, iclass 27, count 0 2006.173.02:17:47.21#ibcon#read 3, iclass 27, count 0 2006.173.02:17:47.21#ibcon#about to read 4, iclass 27, count 0 2006.173.02:17:47.21#ibcon#read 4, iclass 27, count 0 2006.173.02:17:47.21#ibcon#about to read 5, iclass 27, count 0 2006.173.02:17:47.21#ibcon#read 5, iclass 27, count 0 2006.173.02:17:47.21#ibcon#about to read 6, iclass 27, count 0 2006.173.02:17:47.21#ibcon#read 6, iclass 27, count 0 2006.173.02:17:47.21#ibcon#end of sib2, iclass 27, count 0 2006.173.02:17:47.21#ibcon#*mode == 0, iclass 27, count 0 2006.173.02:17:47.21#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.02:17:47.21#ibcon#[25=USB\r\n] 2006.173.02:17:47.21#ibcon#*before write, iclass 27, count 0 2006.173.02:17:47.21#ibcon#enter sib2, iclass 27, count 0 2006.173.02:17:47.21#ibcon#flushed, iclass 27, count 0 2006.173.02:17:47.21#ibcon#about to write, iclass 27, count 0 2006.173.02:17:47.21#ibcon#wrote, iclass 27, count 0 2006.173.02:17:47.21#ibcon#about to read 3, iclass 27, count 0 2006.173.02:17:47.24#ibcon#read 3, iclass 27, count 0 2006.173.02:17:47.24#ibcon#about to read 4, iclass 27, count 0 2006.173.02:17:47.24#ibcon#read 4, iclass 27, count 0 2006.173.02:17:47.24#ibcon#about to read 5, iclass 27, count 0 2006.173.02:17:47.24#ibcon#read 5, iclass 27, count 0 2006.173.02:17:47.24#ibcon#about to read 6, iclass 27, count 0 2006.173.02:17:47.24#ibcon#read 6, iclass 27, count 0 2006.173.02:17:47.24#ibcon#end of sib2, iclass 27, count 0 2006.173.02:17:47.24#ibcon#*after write, iclass 27, count 0 2006.173.02:17:47.24#ibcon#*before return 0, iclass 27, count 0 2006.173.02:17:47.24#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.02:17:47.24#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.02:17:47.24#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.02:17:47.24#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.02:17:47.24$vck44/valo=3,564.99 2006.173.02:17:47.24#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.02:17:47.24#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.02:17:47.24#ibcon#ireg 17 cls_cnt 0 2006.173.02:17:47.24#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.02:17:47.24#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.02:17:47.24#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.02:17:47.24#ibcon#enter wrdev, iclass 29, count 0 2006.173.02:17:47.24#ibcon#first serial, iclass 29, count 0 2006.173.02:17:47.24#ibcon#enter sib2, iclass 29, count 0 2006.173.02:17:47.24#ibcon#flushed, iclass 29, count 0 2006.173.02:17:47.24#ibcon#about to write, iclass 29, count 0 2006.173.02:17:47.24#ibcon#wrote, iclass 29, count 0 2006.173.02:17:47.24#ibcon#about to read 3, iclass 29, count 0 2006.173.02:17:47.26#ibcon#read 3, iclass 29, count 0 2006.173.02:17:47.26#ibcon#about to read 4, iclass 29, count 0 2006.173.02:17:47.26#ibcon#read 4, iclass 29, count 0 2006.173.02:17:47.26#ibcon#about to read 5, iclass 29, count 0 2006.173.02:17:47.26#ibcon#read 5, iclass 29, count 0 2006.173.02:17:47.26#ibcon#about to read 6, iclass 29, count 0 2006.173.02:17:47.26#ibcon#read 6, iclass 29, count 0 2006.173.02:17:47.26#ibcon#end of sib2, iclass 29, count 0 2006.173.02:17:47.26#ibcon#*mode == 0, iclass 29, count 0 2006.173.02:17:47.26#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.02:17:47.26#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.02:17:47.26#ibcon#*before write, iclass 29, count 0 2006.173.02:17:47.26#ibcon#enter sib2, iclass 29, count 0 2006.173.02:17:47.26#ibcon#flushed, iclass 29, count 0 2006.173.02:17:47.26#ibcon#about to write, iclass 29, count 0 2006.173.02:17:47.26#ibcon#wrote, iclass 29, count 0 2006.173.02:17:47.26#ibcon#about to read 3, iclass 29, count 0 2006.173.02:17:47.30#ibcon#read 3, iclass 29, count 0 2006.173.02:17:47.30#ibcon#about to read 4, iclass 29, count 0 2006.173.02:17:47.30#ibcon#read 4, iclass 29, count 0 2006.173.02:17:47.30#ibcon#about to read 5, iclass 29, count 0 2006.173.02:17:47.30#ibcon#read 5, iclass 29, count 0 2006.173.02:17:47.30#ibcon#about to read 6, iclass 29, count 0 2006.173.02:17:47.30#ibcon#read 6, iclass 29, count 0 2006.173.02:17:47.30#ibcon#end of sib2, iclass 29, count 0 2006.173.02:17:47.30#ibcon#*after write, iclass 29, count 0 2006.173.02:17:47.30#ibcon#*before return 0, iclass 29, count 0 2006.173.02:17:47.30#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.02:17:47.30#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.02:17:47.30#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.02:17:47.30#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.02:17:47.30$vck44/va=3,5 2006.173.02:17:47.30#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.02:17:47.30#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.02:17:47.30#ibcon#ireg 11 cls_cnt 2 2006.173.02:17:47.30#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.02:17:47.37#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.02:17:47.37#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.02:17:47.37#ibcon#enter wrdev, iclass 31, count 2 2006.173.02:17:47.37#ibcon#first serial, iclass 31, count 2 2006.173.02:17:47.37#ibcon#enter sib2, iclass 31, count 2 2006.173.02:17:47.37#ibcon#flushed, iclass 31, count 2 2006.173.02:17:47.37#ibcon#about to write, iclass 31, count 2 2006.173.02:17:47.37#ibcon#wrote, iclass 31, count 2 2006.173.02:17:47.37#ibcon#about to read 3, iclass 31, count 2 2006.173.02:17:47.38#ibcon#read 3, iclass 31, count 2 2006.173.02:17:47.38#ibcon#about to read 4, iclass 31, count 2 2006.173.02:17:47.38#ibcon#read 4, iclass 31, count 2 2006.173.02:17:47.38#ibcon#about to read 5, iclass 31, count 2 2006.173.02:17:47.38#ibcon#read 5, iclass 31, count 2 2006.173.02:17:47.38#ibcon#about to read 6, iclass 31, count 2 2006.173.02:17:47.38#ibcon#read 6, iclass 31, count 2 2006.173.02:17:47.38#ibcon#end of sib2, iclass 31, count 2 2006.173.02:17:47.38#ibcon#*mode == 0, iclass 31, count 2 2006.173.02:17:47.38#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.02:17:47.38#ibcon#[25=AT03-05\r\n] 2006.173.02:17:47.38#ibcon#*before write, iclass 31, count 2 2006.173.02:17:47.38#ibcon#enter sib2, iclass 31, count 2 2006.173.02:17:47.38#ibcon#flushed, iclass 31, count 2 2006.173.02:17:47.38#ibcon#about to write, iclass 31, count 2 2006.173.02:17:47.38#ibcon#wrote, iclass 31, count 2 2006.173.02:17:47.38#ibcon#about to read 3, iclass 31, count 2 2006.173.02:17:47.41#ibcon#read 3, iclass 31, count 2 2006.173.02:17:47.41#ibcon#about to read 4, iclass 31, count 2 2006.173.02:17:47.41#ibcon#read 4, iclass 31, count 2 2006.173.02:17:47.41#ibcon#about to read 5, iclass 31, count 2 2006.173.02:17:47.41#ibcon#read 5, iclass 31, count 2 2006.173.02:17:47.41#ibcon#about to read 6, iclass 31, count 2 2006.173.02:17:47.41#ibcon#read 6, iclass 31, count 2 2006.173.02:17:47.41#ibcon#end of sib2, iclass 31, count 2 2006.173.02:17:47.41#ibcon#*after write, iclass 31, count 2 2006.173.02:17:47.41#ibcon#*before return 0, iclass 31, count 2 2006.173.02:17:47.41#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.02:17:47.41#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.02:17:47.41#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.02:17:47.41#ibcon#ireg 7 cls_cnt 0 2006.173.02:17:47.41#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.02:17:47.53#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.02:17:47.53#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.02:17:47.53#ibcon#enter wrdev, iclass 31, count 0 2006.173.02:17:47.53#ibcon#first serial, iclass 31, count 0 2006.173.02:17:47.53#ibcon#enter sib2, iclass 31, count 0 2006.173.02:17:47.53#ibcon#flushed, iclass 31, count 0 2006.173.02:17:47.53#ibcon#about to write, iclass 31, count 0 2006.173.02:17:47.53#ibcon#wrote, iclass 31, count 0 2006.173.02:17:47.53#ibcon#about to read 3, iclass 31, count 0 2006.173.02:17:47.55#ibcon#read 3, iclass 31, count 0 2006.173.02:17:47.55#ibcon#about to read 4, iclass 31, count 0 2006.173.02:17:47.55#ibcon#read 4, iclass 31, count 0 2006.173.02:17:47.55#ibcon#about to read 5, iclass 31, count 0 2006.173.02:17:47.55#ibcon#read 5, iclass 31, count 0 2006.173.02:17:47.55#ibcon#about to read 6, iclass 31, count 0 2006.173.02:17:47.55#ibcon#read 6, iclass 31, count 0 2006.173.02:17:47.55#ibcon#end of sib2, iclass 31, count 0 2006.173.02:17:47.55#ibcon#*mode == 0, iclass 31, count 0 2006.173.02:17:47.55#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.02:17:47.55#ibcon#[25=USB\r\n] 2006.173.02:17:47.55#ibcon#*before write, iclass 31, count 0 2006.173.02:17:47.55#ibcon#enter sib2, iclass 31, count 0 2006.173.02:17:47.55#ibcon#flushed, iclass 31, count 0 2006.173.02:17:47.55#ibcon#about to write, iclass 31, count 0 2006.173.02:17:47.55#ibcon#wrote, iclass 31, count 0 2006.173.02:17:47.55#ibcon#about to read 3, iclass 31, count 0 2006.173.02:17:47.58#ibcon#read 3, iclass 31, count 0 2006.173.02:17:47.58#ibcon#about to read 4, iclass 31, count 0 2006.173.02:17:47.58#ibcon#read 4, iclass 31, count 0 2006.173.02:17:47.58#ibcon#about to read 5, iclass 31, count 0 2006.173.02:17:47.58#ibcon#read 5, iclass 31, count 0 2006.173.02:17:47.58#ibcon#about to read 6, iclass 31, count 0 2006.173.02:17:47.58#ibcon#read 6, iclass 31, count 0 2006.173.02:17:47.58#ibcon#end of sib2, iclass 31, count 0 2006.173.02:17:47.58#ibcon#*after write, iclass 31, count 0 2006.173.02:17:47.58#ibcon#*before return 0, iclass 31, count 0 2006.173.02:17:47.58#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.02:17:47.58#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.02:17:47.58#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.02:17:47.58#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.02:17:47.58$vck44/valo=4,624.99 2006.173.02:17:47.58#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.02:17:47.58#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.02:17:47.58#ibcon#ireg 17 cls_cnt 0 2006.173.02:17:47.58#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.02:17:47.58#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.02:17:47.58#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.02:17:47.58#ibcon#enter wrdev, iclass 33, count 0 2006.173.02:17:47.58#ibcon#first serial, iclass 33, count 0 2006.173.02:17:47.58#ibcon#enter sib2, iclass 33, count 0 2006.173.02:17:47.58#ibcon#flushed, iclass 33, count 0 2006.173.02:17:47.58#ibcon#about to write, iclass 33, count 0 2006.173.02:17:47.58#ibcon#wrote, iclass 33, count 0 2006.173.02:17:47.58#ibcon#about to read 3, iclass 33, count 0 2006.173.02:17:47.60#ibcon#read 3, iclass 33, count 0 2006.173.02:17:47.60#ibcon#about to read 4, iclass 33, count 0 2006.173.02:17:47.60#ibcon#read 4, iclass 33, count 0 2006.173.02:17:47.60#ibcon#about to read 5, iclass 33, count 0 2006.173.02:17:47.60#ibcon#read 5, iclass 33, count 0 2006.173.02:17:47.60#ibcon#about to read 6, iclass 33, count 0 2006.173.02:17:47.60#ibcon#read 6, iclass 33, count 0 2006.173.02:17:47.60#ibcon#end of sib2, iclass 33, count 0 2006.173.02:17:47.60#ibcon#*mode == 0, iclass 33, count 0 2006.173.02:17:47.60#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.02:17:47.60#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.02:17:47.60#ibcon#*before write, iclass 33, count 0 2006.173.02:17:47.60#ibcon#enter sib2, iclass 33, count 0 2006.173.02:17:47.60#ibcon#flushed, iclass 33, count 0 2006.173.02:17:47.60#ibcon#about to write, iclass 33, count 0 2006.173.02:17:47.60#ibcon#wrote, iclass 33, count 0 2006.173.02:17:47.60#ibcon#about to read 3, iclass 33, count 0 2006.173.02:17:47.64#ibcon#read 3, iclass 33, count 0 2006.173.02:17:47.64#ibcon#about to read 4, iclass 33, count 0 2006.173.02:17:47.64#ibcon#read 4, iclass 33, count 0 2006.173.02:17:47.64#ibcon#about to read 5, iclass 33, count 0 2006.173.02:17:47.64#ibcon#read 5, iclass 33, count 0 2006.173.02:17:47.64#ibcon#about to read 6, iclass 33, count 0 2006.173.02:17:47.64#ibcon#read 6, iclass 33, count 0 2006.173.02:17:47.64#ibcon#end of sib2, iclass 33, count 0 2006.173.02:17:47.64#ibcon#*after write, iclass 33, count 0 2006.173.02:17:47.64#ibcon#*before return 0, iclass 33, count 0 2006.173.02:17:47.64#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.02:17:47.64#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.02:17:47.64#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.02:17:47.64#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.02:17:47.64$vck44/va=4,6 2006.173.02:17:47.64#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.02:17:47.64#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.02:17:47.64#ibcon#ireg 11 cls_cnt 2 2006.173.02:17:47.64#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.02:17:47.70#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.02:17:47.70#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.02:17:47.70#ibcon#enter wrdev, iclass 35, count 2 2006.173.02:17:47.70#ibcon#first serial, iclass 35, count 2 2006.173.02:17:47.70#ibcon#enter sib2, iclass 35, count 2 2006.173.02:17:47.70#ibcon#flushed, iclass 35, count 2 2006.173.02:17:47.70#ibcon#about to write, iclass 35, count 2 2006.173.02:17:47.70#ibcon#wrote, iclass 35, count 2 2006.173.02:17:47.70#ibcon#about to read 3, iclass 35, count 2 2006.173.02:17:47.72#ibcon#read 3, iclass 35, count 2 2006.173.02:17:47.72#ibcon#about to read 4, iclass 35, count 2 2006.173.02:17:47.72#ibcon#read 4, iclass 35, count 2 2006.173.02:17:47.72#ibcon#about to read 5, iclass 35, count 2 2006.173.02:17:47.72#ibcon#read 5, iclass 35, count 2 2006.173.02:17:47.72#ibcon#about to read 6, iclass 35, count 2 2006.173.02:17:47.72#ibcon#read 6, iclass 35, count 2 2006.173.02:17:47.72#ibcon#end of sib2, iclass 35, count 2 2006.173.02:17:47.72#ibcon#*mode == 0, iclass 35, count 2 2006.173.02:17:47.72#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.02:17:47.72#ibcon#[25=AT04-06\r\n] 2006.173.02:17:47.72#ibcon#*before write, iclass 35, count 2 2006.173.02:17:47.72#ibcon#enter sib2, iclass 35, count 2 2006.173.02:17:47.72#ibcon#flushed, iclass 35, count 2 2006.173.02:17:47.72#ibcon#about to write, iclass 35, count 2 2006.173.02:17:47.72#ibcon#wrote, iclass 35, count 2 2006.173.02:17:47.72#ibcon#about to read 3, iclass 35, count 2 2006.173.02:17:47.75#ibcon#read 3, iclass 35, count 2 2006.173.02:17:47.75#ibcon#about to read 4, iclass 35, count 2 2006.173.02:17:47.75#ibcon#read 4, iclass 35, count 2 2006.173.02:17:47.75#ibcon#about to read 5, iclass 35, count 2 2006.173.02:17:47.75#ibcon#read 5, iclass 35, count 2 2006.173.02:17:47.75#ibcon#about to read 6, iclass 35, count 2 2006.173.02:17:47.75#ibcon#read 6, iclass 35, count 2 2006.173.02:17:47.75#ibcon#end of sib2, iclass 35, count 2 2006.173.02:17:47.75#ibcon#*after write, iclass 35, count 2 2006.173.02:17:47.75#ibcon#*before return 0, iclass 35, count 2 2006.173.02:17:47.75#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.02:17:47.75#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.02:17:47.75#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.02:17:47.75#ibcon#ireg 7 cls_cnt 0 2006.173.02:17:47.75#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.02:17:47.87#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.02:17:47.87#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.02:17:47.87#ibcon#enter wrdev, iclass 35, count 0 2006.173.02:17:47.87#ibcon#first serial, iclass 35, count 0 2006.173.02:17:47.87#ibcon#enter sib2, iclass 35, count 0 2006.173.02:17:47.87#ibcon#flushed, iclass 35, count 0 2006.173.02:17:47.87#ibcon#about to write, iclass 35, count 0 2006.173.02:17:47.87#ibcon#wrote, iclass 35, count 0 2006.173.02:17:47.87#ibcon#about to read 3, iclass 35, count 0 2006.173.02:17:47.89#ibcon#read 3, iclass 35, count 0 2006.173.02:17:47.89#ibcon#about to read 4, iclass 35, count 0 2006.173.02:17:47.89#ibcon#read 4, iclass 35, count 0 2006.173.02:17:47.89#ibcon#about to read 5, iclass 35, count 0 2006.173.02:17:47.89#ibcon#read 5, iclass 35, count 0 2006.173.02:17:47.89#ibcon#about to read 6, iclass 35, count 0 2006.173.02:17:47.89#ibcon#read 6, iclass 35, count 0 2006.173.02:17:47.89#ibcon#end of sib2, iclass 35, count 0 2006.173.02:17:47.89#ibcon#*mode == 0, iclass 35, count 0 2006.173.02:17:47.89#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.02:17:47.89#ibcon#[25=USB\r\n] 2006.173.02:17:47.89#ibcon#*before write, iclass 35, count 0 2006.173.02:17:47.89#ibcon#enter sib2, iclass 35, count 0 2006.173.02:17:47.89#ibcon#flushed, iclass 35, count 0 2006.173.02:17:47.89#ibcon#about to write, iclass 35, count 0 2006.173.02:17:47.89#ibcon#wrote, iclass 35, count 0 2006.173.02:17:47.89#ibcon#about to read 3, iclass 35, count 0 2006.173.02:17:47.92#ibcon#read 3, iclass 35, count 0 2006.173.02:17:47.92#ibcon#about to read 4, iclass 35, count 0 2006.173.02:17:47.92#ibcon#read 4, iclass 35, count 0 2006.173.02:17:47.92#ibcon#about to read 5, iclass 35, count 0 2006.173.02:17:47.92#ibcon#read 5, iclass 35, count 0 2006.173.02:17:47.92#ibcon#about to read 6, iclass 35, count 0 2006.173.02:17:47.92#ibcon#read 6, iclass 35, count 0 2006.173.02:17:47.92#ibcon#end of sib2, iclass 35, count 0 2006.173.02:17:47.92#ibcon#*after write, iclass 35, count 0 2006.173.02:17:47.92#ibcon#*before return 0, iclass 35, count 0 2006.173.02:17:47.92#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.02:17:47.92#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.02:17:47.92#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.02:17:47.92#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.02:17:47.92$vck44/valo=5,734.99 2006.173.02:17:47.92#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.02:17:47.92#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.02:17:47.92#ibcon#ireg 17 cls_cnt 0 2006.173.02:17:47.92#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.02:17:47.92#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.02:17:47.92#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.02:17:47.92#ibcon#enter wrdev, iclass 37, count 0 2006.173.02:17:47.92#ibcon#first serial, iclass 37, count 0 2006.173.02:17:47.92#ibcon#enter sib2, iclass 37, count 0 2006.173.02:17:47.92#ibcon#flushed, iclass 37, count 0 2006.173.02:17:47.92#ibcon#about to write, iclass 37, count 0 2006.173.02:17:47.92#ibcon#wrote, iclass 37, count 0 2006.173.02:17:47.92#ibcon#about to read 3, iclass 37, count 0 2006.173.02:17:47.94#ibcon#read 3, iclass 37, count 0 2006.173.02:17:47.94#ibcon#about to read 4, iclass 37, count 0 2006.173.02:17:47.94#ibcon#read 4, iclass 37, count 0 2006.173.02:17:47.94#ibcon#about to read 5, iclass 37, count 0 2006.173.02:17:47.94#ibcon#read 5, iclass 37, count 0 2006.173.02:17:47.94#ibcon#about to read 6, iclass 37, count 0 2006.173.02:17:47.94#ibcon#read 6, iclass 37, count 0 2006.173.02:17:47.94#ibcon#end of sib2, iclass 37, count 0 2006.173.02:17:47.94#ibcon#*mode == 0, iclass 37, count 0 2006.173.02:17:47.94#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.02:17:47.94#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.02:17:47.94#ibcon#*before write, iclass 37, count 0 2006.173.02:17:47.94#ibcon#enter sib2, iclass 37, count 0 2006.173.02:17:47.94#ibcon#flushed, iclass 37, count 0 2006.173.02:17:47.94#ibcon#about to write, iclass 37, count 0 2006.173.02:17:47.94#ibcon#wrote, iclass 37, count 0 2006.173.02:17:47.94#ibcon#about to read 3, iclass 37, count 0 2006.173.02:17:47.98#ibcon#read 3, iclass 37, count 0 2006.173.02:17:47.98#ibcon#about to read 4, iclass 37, count 0 2006.173.02:17:47.98#ibcon#read 4, iclass 37, count 0 2006.173.02:17:47.98#ibcon#about to read 5, iclass 37, count 0 2006.173.02:17:47.98#ibcon#read 5, iclass 37, count 0 2006.173.02:17:47.98#ibcon#about to read 6, iclass 37, count 0 2006.173.02:17:47.98#ibcon#read 6, iclass 37, count 0 2006.173.02:17:47.98#ibcon#end of sib2, iclass 37, count 0 2006.173.02:17:47.98#ibcon#*after write, iclass 37, count 0 2006.173.02:17:47.98#ibcon#*before return 0, iclass 37, count 0 2006.173.02:17:47.98#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.02:17:47.98#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.02:17:47.98#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.02:17:47.98#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.02:17:47.98$vck44/va=5,4 2006.173.02:17:47.98#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.02:17:47.98#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.02:17:47.98#ibcon#ireg 11 cls_cnt 2 2006.173.02:17:47.98#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.02:17:48.04#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.02:17:48.04#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.02:17:48.04#ibcon#enter wrdev, iclass 39, count 2 2006.173.02:17:48.04#ibcon#first serial, iclass 39, count 2 2006.173.02:17:48.04#ibcon#enter sib2, iclass 39, count 2 2006.173.02:17:48.04#ibcon#flushed, iclass 39, count 2 2006.173.02:17:48.04#ibcon#about to write, iclass 39, count 2 2006.173.02:17:48.04#ibcon#wrote, iclass 39, count 2 2006.173.02:17:48.04#ibcon#about to read 3, iclass 39, count 2 2006.173.02:17:48.06#ibcon#read 3, iclass 39, count 2 2006.173.02:17:48.06#ibcon#about to read 4, iclass 39, count 2 2006.173.02:17:48.06#ibcon#read 4, iclass 39, count 2 2006.173.02:17:48.06#ibcon#about to read 5, iclass 39, count 2 2006.173.02:17:48.06#ibcon#read 5, iclass 39, count 2 2006.173.02:17:48.06#ibcon#about to read 6, iclass 39, count 2 2006.173.02:17:48.06#ibcon#read 6, iclass 39, count 2 2006.173.02:17:48.06#ibcon#end of sib2, iclass 39, count 2 2006.173.02:17:48.06#ibcon#*mode == 0, iclass 39, count 2 2006.173.02:17:48.06#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.02:17:48.06#ibcon#[25=AT05-04\r\n] 2006.173.02:17:48.06#ibcon#*before write, iclass 39, count 2 2006.173.02:17:48.06#ibcon#enter sib2, iclass 39, count 2 2006.173.02:17:48.06#ibcon#flushed, iclass 39, count 2 2006.173.02:17:48.06#ibcon#about to write, iclass 39, count 2 2006.173.02:17:48.06#ibcon#wrote, iclass 39, count 2 2006.173.02:17:48.06#ibcon#about to read 3, iclass 39, count 2 2006.173.02:17:48.09#ibcon#read 3, iclass 39, count 2 2006.173.02:17:48.09#ibcon#about to read 4, iclass 39, count 2 2006.173.02:17:48.09#ibcon#read 4, iclass 39, count 2 2006.173.02:17:48.09#ibcon#about to read 5, iclass 39, count 2 2006.173.02:17:48.09#ibcon#read 5, iclass 39, count 2 2006.173.02:17:48.09#ibcon#about to read 6, iclass 39, count 2 2006.173.02:17:48.09#ibcon#read 6, iclass 39, count 2 2006.173.02:17:48.09#ibcon#end of sib2, iclass 39, count 2 2006.173.02:17:48.09#ibcon#*after write, iclass 39, count 2 2006.173.02:17:48.09#ibcon#*before return 0, iclass 39, count 2 2006.173.02:17:48.09#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.02:17:48.09#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.02:17:48.09#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.02:17:48.09#ibcon#ireg 7 cls_cnt 0 2006.173.02:17:48.09#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.02:17:48.21#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.02:17:48.21#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.02:17:48.21#ibcon#enter wrdev, iclass 39, count 0 2006.173.02:17:48.21#ibcon#first serial, iclass 39, count 0 2006.173.02:17:48.21#ibcon#enter sib2, iclass 39, count 0 2006.173.02:17:48.21#ibcon#flushed, iclass 39, count 0 2006.173.02:17:48.21#ibcon#about to write, iclass 39, count 0 2006.173.02:17:48.21#ibcon#wrote, iclass 39, count 0 2006.173.02:17:48.21#ibcon#about to read 3, iclass 39, count 0 2006.173.02:17:48.23#ibcon#read 3, iclass 39, count 0 2006.173.02:17:48.23#ibcon#about to read 4, iclass 39, count 0 2006.173.02:17:48.23#ibcon#read 4, iclass 39, count 0 2006.173.02:17:48.23#ibcon#about to read 5, iclass 39, count 0 2006.173.02:17:48.23#ibcon#read 5, iclass 39, count 0 2006.173.02:17:48.23#ibcon#about to read 6, iclass 39, count 0 2006.173.02:17:48.23#ibcon#read 6, iclass 39, count 0 2006.173.02:17:48.23#ibcon#end of sib2, iclass 39, count 0 2006.173.02:17:48.23#ibcon#*mode == 0, iclass 39, count 0 2006.173.02:17:48.23#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.02:17:48.23#ibcon#[25=USB\r\n] 2006.173.02:17:48.23#ibcon#*before write, iclass 39, count 0 2006.173.02:17:48.23#ibcon#enter sib2, iclass 39, count 0 2006.173.02:17:48.23#ibcon#flushed, iclass 39, count 0 2006.173.02:17:48.23#ibcon#about to write, iclass 39, count 0 2006.173.02:17:48.23#ibcon#wrote, iclass 39, count 0 2006.173.02:17:48.23#ibcon#about to read 3, iclass 39, count 0 2006.173.02:17:48.26#ibcon#read 3, iclass 39, count 0 2006.173.02:17:48.26#ibcon#about to read 4, iclass 39, count 0 2006.173.02:17:48.26#ibcon#read 4, iclass 39, count 0 2006.173.02:17:48.26#ibcon#about to read 5, iclass 39, count 0 2006.173.02:17:48.26#ibcon#read 5, iclass 39, count 0 2006.173.02:17:48.26#ibcon#about to read 6, iclass 39, count 0 2006.173.02:17:48.26#ibcon#read 6, iclass 39, count 0 2006.173.02:17:48.26#ibcon#end of sib2, iclass 39, count 0 2006.173.02:17:48.26#ibcon#*after write, iclass 39, count 0 2006.173.02:17:48.26#ibcon#*before return 0, iclass 39, count 0 2006.173.02:17:48.26#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.02:17:48.26#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.02:17:48.26#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.02:17:48.26#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.02:17:48.26$vck44/valo=6,814.99 2006.173.02:17:48.26#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.02:17:48.26#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.02:17:48.26#ibcon#ireg 17 cls_cnt 0 2006.173.02:17:48.26#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.02:17:48.26#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.02:17:48.26#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.02:17:48.26#ibcon#enter wrdev, iclass 3, count 0 2006.173.02:17:48.26#ibcon#first serial, iclass 3, count 0 2006.173.02:17:48.26#ibcon#enter sib2, iclass 3, count 0 2006.173.02:17:48.26#ibcon#flushed, iclass 3, count 0 2006.173.02:17:48.26#ibcon#about to write, iclass 3, count 0 2006.173.02:17:48.26#ibcon#wrote, iclass 3, count 0 2006.173.02:17:48.26#ibcon#about to read 3, iclass 3, count 0 2006.173.02:17:48.28#ibcon#read 3, iclass 3, count 0 2006.173.02:17:48.28#ibcon#about to read 4, iclass 3, count 0 2006.173.02:17:48.28#ibcon#read 4, iclass 3, count 0 2006.173.02:17:48.28#ibcon#about to read 5, iclass 3, count 0 2006.173.02:17:48.28#ibcon#read 5, iclass 3, count 0 2006.173.02:17:48.28#ibcon#about to read 6, iclass 3, count 0 2006.173.02:17:48.28#ibcon#read 6, iclass 3, count 0 2006.173.02:17:48.28#ibcon#end of sib2, iclass 3, count 0 2006.173.02:17:48.28#ibcon#*mode == 0, iclass 3, count 0 2006.173.02:17:48.28#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.02:17:48.28#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.02:17:48.28#ibcon#*before write, iclass 3, count 0 2006.173.02:17:48.28#ibcon#enter sib2, iclass 3, count 0 2006.173.02:17:48.28#ibcon#flushed, iclass 3, count 0 2006.173.02:17:48.28#ibcon#about to write, iclass 3, count 0 2006.173.02:17:48.28#ibcon#wrote, iclass 3, count 0 2006.173.02:17:48.28#ibcon#about to read 3, iclass 3, count 0 2006.173.02:17:48.32#ibcon#read 3, iclass 3, count 0 2006.173.02:17:48.32#ibcon#about to read 4, iclass 3, count 0 2006.173.02:17:48.32#ibcon#read 4, iclass 3, count 0 2006.173.02:17:48.32#ibcon#about to read 5, iclass 3, count 0 2006.173.02:17:48.32#ibcon#read 5, iclass 3, count 0 2006.173.02:17:48.32#ibcon#about to read 6, iclass 3, count 0 2006.173.02:17:48.32#ibcon#read 6, iclass 3, count 0 2006.173.02:17:48.32#ibcon#end of sib2, iclass 3, count 0 2006.173.02:17:48.32#ibcon#*after write, iclass 3, count 0 2006.173.02:17:48.32#ibcon#*before return 0, iclass 3, count 0 2006.173.02:17:48.32#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.02:17:48.32#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.02:17:48.32#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.02:17:48.32#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.02:17:48.32$vck44/va=6,3 2006.173.02:17:48.32#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.02:17:48.32#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.02:17:48.32#ibcon#ireg 11 cls_cnt 2 2006.173.02:17:48.32#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.02:17:48.38#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.02:17:48.38#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.02:17:48.38#ibcon#enter wrdev, iclass 5, count 2 2006.173.02:17:48.38#ibcon#first serial, iclass 5, count 2 2006.173.02:17:48.38#ibcon#enter sib2, iclass 5, count 2 2006.173.02:17:48.38#ibcon#flushed, iclass 5, count 2 2006.173.02:17:48.38#ibcon#about to write, iclass 5, count 2 2006.173.02:17:48.38#ibcon#wrote, iclass 5, count 2 2006.173.02:17:48.38#ibcon#about to read 3, iclass 5, count 2 2006.173.02:17:48.40#ibcon#read 3, iclass 5, count 2 2006.173.02:17:48.40#ibcon#about to read 4, iclass 5, count 2 2006.173.02:17:48.40#ibcon#read 4, iclass 5, count 2 2006.173.02:17:48.40#ibcon#about to read 5, iclass 5, count 2 2006.173.02:17:48.40#ibcon#read 5, iclass 5, count 2 2006.173.02:17:48.40#ibcon#about to read 6, iclass 5, count 2 2006.173.02:17:48.40#ibcon#read 6, iclass 5, count 2 2006.173.02:17:48.40#ibcon#end of sib2, iclass 5, count 2 2006.173.02:17:48.40#ibcon#*mode == 0, iclass 5, count 2 2006.173.02:17:48.40#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.02:17:48.40#ibcon#[25=AT06-03\r\n] 2006.173.02:17:48.40#ibcon#*before write, iclass 5, count 2 2006.173.02:17:48.40#ibcon#enter sib2, iclass 5, count 2 2006.173.02:17:48.40#ibcon#flushed, iclass 5, count 2 2006.173.02:17:48.40#ibcon#about to write, iclass 5, count 2 2006.173.02:17:48.40#ibcon#wrote, iclass 5, count 2 2006.173.02:17:48.40#ibcon#about to read 3, iclass 5, count 2 2006.173.02:17:48.43#ibcon#read 3, iclass 5, count 2 2006.173.02:17:48.43#ibcon#about to read 4, iclass 5, count 2 2006.173.02:17:48.43#ibcon#read 4, iclass 5, count 2 2006.173.02:17:48.43#ibcon#about to read 5, iclass 5, count 2 2006.173.02:17:48.43#ibcon#read 5, iclass 5, count 2 2006.173.02:17:48.43#ibcon#about to read 6, iclass 5, count 2 2006.173.02:17:48.43#ibcon#read 6, iclass 5, count 2 2006.173.02:17:48.43#ibcon#end of sib2, iclass 5, count 2 2006.173.02:17:48.43#ibcon#*after write, iclass 5, count 2 2006.173.02:17:48.43#ibcon#*before return 0, iclass 5, count 2 2006.173.02:17:48.43#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.02:17:48.43#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.02:17:48.43#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.02:17:48.43#ibcon#ireg 7 cls_cnt 0 2006.173.02:17:48.43#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.02:17:48.55#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.02:17:48.55#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.02:17:48.55#ibcon#enter wrdev, iclass 5, count 0 2006.173.02:17:48.55#ibcon#first serial, iclass 5, count 0 2006.173.02:17:48.55#ibcon#enter sib2, iclass 5, count 0 2006.173.02:17:48.55#ibcon#flushed, iclass 5, count 0 2006.173.02:17:48.55#ibcon#about to write, iclass 5, count 0 2006.173.02:17:48.55#ibcon#wrote, iclass 5, count 0 2006.173.02:17:48.55#ibcon#about to read 3, iclass 5, count 0 2006.173.02:17:48.57#ibcon#read 3, iclass 5, count 0 2006.173.02:17:48.57#ibcon#about to read 4, iclass 5, count 0 2006.173.02:17:48.57#ibcon#read 4, iclass 5, count 0 2006.173.02:17:48.57#ibcon#about to read 5, iclass 5, count 0 2006.173.02:17:48.57#ibcon#read 5, iclass 5, count 0 2006.173.02:17:48.57#ibcon#about to read 6, iclass 5, count 0 2006.173.02:17:48.57#ibcon#read 6, iclass 5, count 0 2006.173.02:17:48.57#ibcon#end of sib2, iclass 5, count 0 2006.173.02:17:48.57#ibcon#*mode == 0, iclass 5, count 0 2006.173.02:17:48.57#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.02:17:48.57#ibcon#[25=USB\r\n] 2006.173.02:17:48.57#ibcon#*before write, iclass 5, count 0 2006.173.02:17:48.57#ibcon#enter sib2, iclass 5, count 0 2006.173.02:17:48.57#ibcon#flushed, iclass 5, count 0 2006.173.02:17:48.57#ibcon#about to write, iclass 5, count 0 2006.173.02:17:48.57#ibcon#wrote, iclass 5, count 0 2006.173.02:17:48.57#ibcon#about to read 3, iclass 5, count 0 2006.173.02:17:48.60#ibcon#read 3, iclass 5, count 0 2006.173.02:17:48.60#ibcon#about to read 4, iclass 5, count 0 2006.173.02:17:48.60#ibcon#read 4, iclass 5, count 0 2006.173.02:17:48.60#ibcon#about to read 5, iclass 5, count 0 2006.173.02:17:48.60#ibcon#read 5, iclass 5, count 0 2006.173.02:17:48.60#ibcon#about to read 6, iclass 5, count 0 2006.173.02:17:48.60#ibcon#read 6, iclass 5, count 0 2006.173.02:17:48.60#ibcon#end of sib2, iclass 5, count 0 2006.173.02:17:48.60#ibcon#*after write, iclass 5, count 0 2006.173.02:17:48.60#ibcon#*before return 0, iclass 5, count 0 2006.173.02:17:48.60#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.02:17:48.60#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.02:17:48.60#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.02:17:48.60#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.02:17:48.60$vck44/valo=7,864.99 2006.173.02:17:48.60#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.02:17:48.60#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.02:17:48.60#ibcon#ireg 17 cls_cnt 0 2006.173.02:17:48.60#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.02:17:48.60#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.02:17:48.60#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.02:17:48.60#ibcon#enter wrdev, iclass 7, count 0 2006.173.02:17:48.60#ibcon#first serial, iclass 7, count 0 2006.173.02:17:48.60#ibcon#enter sib2, iclass 7, count 0 2006.173.02:17:48.60#ibcon#flushed, iclass 7, count 0 2006.173.02:17:48.60#ibcon#about to write, iclass 7, count 0 2006.173.02:17:48.60#ibcon#wrote, iclass 7, count 0 2006.173.02:17:48.60#ibcon#about to read 3, iclass 7, count 0 2006.173.02:17:48.62#ibcon#read 3, iclass 7, count 0 2006.173.02:17:48.62#ibcon#about to read 4, iclass 7, count 0 2006.173.02:17:48.62#ibcon#read 4, iclass 7, count 0 2006.173.02:17:48.62#ibcon#about to read 5, iclass 7, count 0 2006.173.02:17:48.62#ibcon#read 5, iclass 7, count 0 2006.173.02:17:48.62#ibcon#about to read 6, iclass 7, count 0 2006.173.02:17:48.62#ibcon#read 6, iclass 7, count 0 2006.173.02:17:48.62#ibcon#end of sib2, iclass 7, count 0 2006.173.02:17:48.62#ibcon#*mode == 0, iclass 7, count 0 2006.173.02:17:48.62#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.02:17:48.62#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.02:17:48.62#ibcon#*before write, iclass 7, count 0 2006.173.02:17:48.62#ibcon#enter sib2, iclass 7, count 0 2006.173.02:17:48.62#ibcon#flushed, iclass 7, count 0 2006.173.02:17:48.62#ibcon#about to write, iclass 7, count 0 2006.173.02:17:48.62#ibcon#wrote, iclass 7, count 0 2006.173.02:17:48.62#ibcon#about to read 3, iclass 7, count 0 2006.173.02:17:48.66#ibcon#read 3, iclass 7, count 0 2006.173.02:17:48.66#ibcon#about to read 4, iclass 7, count 0 2006.173.02:17:48.66#ibcon#read 4, iclass 7, count 0 2006.173.02:17:48.66#ibcon#about to read 5, iclass 7, count 0 2006.173.02:17:48.66#ibcon#read 5, iclass 7, count 0 2006.173.02:17:48.66#ibcon#about to read 6, iclass 7, count 0 2006.173.02:17:48.66#ibcon#read 6, iclass 7, count 0 2006.173.02:17:48.66#ibcon#end of sib2, iclass 7, count 0 2006.173.02:17:48.66#ibcon#*after write, iclass 7, count 0 2006.173.02:17:48.66#ibcon#*before return 0, iclass 7, count 0 2006.173.02:17:48.66#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.02:17:48.66#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.02:17:48.66#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.02:17:48.66#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.02:17:48.66$vck44/va=7,4 2006.173.02:17:48.66#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.02:17:48.66#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.02:17:48.66#ibcon#ireg 11 cls_cnt 2 2006.173.02:17:48.66#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.02:17:48.72#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.02:17:48.72#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.02:17:48.72#ibcon#enter wrdev, iclass 11, count 2 2006.173.02:17:48.72#ibcon#first serial, iclass 11, count 2 2006.173.02:17:48.72#ibcon#enter sib2, iclass 11, count 2 2006.173.02:17:48.72#ibcon#flushed, iclass 11, count 2 2006.173.02:17:48.72#ibcon#about to write, iclass 11, count 2 2006.173.02:17:48.72#ibcon#wrote, iclass 11, count 2 2006.173.02:17:48.72#ibcon#about to read 3, iclass 11, count 2 2006.173.02:17:48.74#ibcon#read 3, iclass 11, count 2 2006.173.02:17:48.74#ibcon#about to read 4, iclass 11, count 2 2006.173.02:17:48.74#ibcon#read 4, iclass 11, count 2 2006.173.02:17:48.74#ibcon#about to read 5, iclass 11, count 2 2006.173.02:17:48.74#ibcon#read 5, iclass 11, count 2 2006.173.02:17:48.74#ibcon#about to read 6, iclass 11, count 2 2006.173.02:17:48.74#ibcon#read 6, iclass 11, count 2 2006.173.02:17:48.74#ibcon#end of sib2, iclass 11, count 2 2006.173.02:17:48.74#ibcon#*mode == 0, iclass 11, count 2 2006.173.02:17:48.74#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.02:17:48.74#ibcon#[25=AT07-04\r\n] 2006.173.02:17:48.74#ibcon#*before write, iclass 11, count 2 2006.173.02:17:48.74#ibcon#enter sib2, iclass 11, count 2 2006.173.02:17:48.74#ibcon#flushed, iclass 11, count 2 2006.173.02:17:48.74#ibcon#about to write, iclass 11, count 2 2006.173.02:17:48.74#ibcon#wrote, iclass 11, count 2 2006.173.02:17:48.74#ibcon#about to read 3, iclass 11, count 2 2006.173.02:17:48.77#ibcon#read 3, iclass 11, count 2 2006.173.02:17:48.77#ibcon#about to read 4, iclass 11, count 2 2006.173.02:17:48.77#ibcon#read 4, iclass 11, count 2 2006.173.02:17:48.77#ibcon#about to read 5, iclass 11, count 2 2006.173.02:17:48.77#ibcon#read 5, iclass 11, count 2 2006.173.02:17:48.77#ibcon#about to read 6, iclass 11, count 2 2006.173.02:17:48.77#ibcon#read 6, iclass 11, count 2 2006.173.02:17:48.77#ibcon#end of sib2, iclass 11, count 2 2006.173.02:17:48.77#ibcon#*after write, iclass 11, count 2 2006.173.02:17:48.77#ibcon#*before return 0, iclass 11, count 2 2006.173.02:17:48.77#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.02:17:48.77#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.02:17:48.77#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.02:17:48.77#ibcon#ireg 7 cls_cnt 0 2006.173.02:17:48.77#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.02:17:48.89#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.02:17:48.89#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.02:17:48.89#ibcon#enter wrdev, iclass 11, count 0 2006.173.02:17:48.89#ibcon#first serial, iclass 11, count 0 2006.173.02:17:48.89#ibcon#enter sib2, iclass 11, count 0 2006.173.02:17:48.89#ibcon#flushed, iclass 11, count 0 2006.173.02:17:48.89#ibcon#about to write, iclass 11, count 0 2006.173.02:17:48.89#ibcon#wrote, iclass 11, count 0 2006.173.02:17:48.89#ibcon#about to read 3, iclass 11, count 0 2006.173.02:17:48.91#ibcon#read 3, iclass 11, count 0 2006.173.02:17:48.91#ibcon#about to read 4, iclass 11, count 0 2006.173.02:17:48.91#ibcon#read 4, iclass 11, count 0 2006.173.02:17:48.91#ibcon#about to read 5, iclass 11, count 0 2006.173.02:17:48.91#ibcon#read 5, iclass 11, count 0 2006.173.02:17:48.91#ibcon#about to read 6, iclass 11, count 0 2006.173.02:17:48.91#ibcon#read 6, iclass 11, count 0 2006.173.02:17:48.91#ibcon#end of sib2, iclass 11, count 0 2006.173.02:17:48.91#ibcon#*mode == 0, iclass 11, count 0 2006.173.02:17:48.91#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.02:17:48.91#ibcon#[25=USB\r\n] 2006.173.02:17:48.91#ibcon#*before write, iclass 11, count 0 2006.173.02:17:48.91#ibcon#enter sib2, iclass 11, count 0 2006.173.02:17:48.91#ibcon#flushed, iclass 11, count 0 2006.173.02:17:48.91#ibcon#about to write, iclass 11, count 0 2006.173.02:17:48.91#ibcon#wrote, iclass 11, count 0 2006.173.02:17:48.91#ibcon#about to read 3, iclass 11, count 0 2006.173.02:17:48.94#ibcon#read 3, iclass 11, count 0 2006.173.02:17:48.94#ibcon#about to read 4, iclass 11, count 0 2006.173.02:17:48.94#ibcon#read 4, iclass 11, count 0 2006.173.02:17:48.94#ibcon#about to read 5, iclass 11, count 0 2006.173.02:17:48.94#ibcon#read 5, iclass 11, count 0 2006.173.02:17:48.94#ibcon#about to read 6, iclass 11, count 0 2006.173.02:17:48.94#ibcon#read 6, iclass 11, count 0 2006.173.02:17:48.94#ibcon#end of sib2, iclass 11, count 0 2006.173.02:17:48.94#ibcon#*after write, iclass 11, count 0 2006.173.02:17:48.94#ibcon#*before return 0, iclass 11, count 0 2006.173.02:17:48.94#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.02:17:48.94#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.02:17:48.94#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.02:17:48.94#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.02:17:48.94$vck44/valo=8,884.99 2006.173.02:17:48.94#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.02:17:48.94#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.02:17:48.94#ibcon#ireg 17 cls_cnt 0 2006.173.02:17:48.94#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.02:17:48.94#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.02:17:48.94#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.02:17:48.94#ibcon#enter wrdev, iclass 13, count 0 2006.173.02:17:48.94#ibcon#first serial, iclass 13, count 0 2006.173.02:17:48.94#ibcon#enter sib2, iclass 13, count 0 2006.173.02:17:48.94#ibcon#flushed, iclass 13, count 0 2006.173.02:17:48.94#ibcon#about to write, iclass 13, count 0 2006.173.02:17:48.94#ibcon#wrote, iclass 13, count 0 2006.173.02:17:48.94#ibcon#about to read 3, iclass 13, count 0 2006.173.02:17:48.96#ibcon#read 3, iclass 13, count 0 2006.173.02:17:48.96#ibcon#about to read 4, iclass 13, count 0 2006.173.02:17:48.96#ibcon#read 4, iclass 13, count 0 2006.173.02:17:48.96#ibcon#about to read 5, iclass 13, count 0 2006.173.02:17:48.96#ibcon#read 5, iclass 13, count 0 2006.173.02:17:48.96#ibcon#about to read 6, iclass 13, count 0 2006.173.02:17:48.96#ibcon#read 6, iclass 13, count 0 2006.173.02:17:48.96#ibcon#end of sib2, iclass 13, count 0 2006.173.02:17:48.96#ibcon#*mode == 0, iclass 13, count 0 2006.173.02:17:48.96#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.02:17:48.96#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.02:17:48.96#ibcon#*before write, iclass 13, count 0 2006.173.02:17:48.96#ibcon#enter sib2, iclass 13, count 0 2006.173.02:17:48.96#ibcon#flushed, iclass 13, count 0 2006.173.02:17:48.96#ibcon#about to write, iclass 13, count 0 2006.173.02:17:48.96#ibcon#wrote, iclass 13, count 0 2006.173.02:17:48.96#ibcon#about to read 3, iclass 13, count 0 2006.173.02:17:49.00#ibcon#read 3, iclass 13, count 0 2006.173.02:17:49.00#ibcon#about to read 4, iclass 13, count 0 2006.173.02:17:49.00#ibcon#read 4, iclass 13, count 0 2006.173.02:17:49.00#ibcon#about to read 5, iclass 13, count 0 2006.173.02:17:49.00#ibcon#read 5, iclass 13, count 0 2006.173.02:17:49.00#ibcon#about to read 6, iclass 13, count 0 2006.173.02:17:49.00#ibcon#read 6, iclass 13, count 0 2006.173.02:17:49.00#ibcon#end of sib2, iclass 13, count 0 2006.173.02:17:49.00#ibcon#*after write, iclass 13, count 0 2006.173.02:17:49.00#ibcon#*before return 0, iclass 13, count 0 2006.173.02:17:49.00#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.02:17:49.00#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.02:17:49.00#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.02:17:49.00#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.02:17:49.00$vck44/va=8,4 2006.173.02:17:49.00#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.02:17:49.00#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.02:17:49.00#ibcon#ireg 11 cls_cnt 2 2006.173.02:17:49.00#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.02:17:49.06#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.02:17:49.06#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.02:17:49.06#ibcon#enter wrdev, iclass 15, count 2 2006.173.02:17:49.06#ibcon#first serial, iclass 15, count 2 2006.173.02:17:49.06#ibcon#enter sib2, iclass 15, count 2 2006.173.02:17:49.06#ibcon#flushed, iclass 15, count 2 2006.173.02:17:49.06#ibcon#about to write, iclass 15, count 2 2006.173.02:17:49.06#ibcon#wrote, iclass 15, count 2 2006.173.02:17:49.06#ibcon#about to read 3, iclass 15, count 2 2006.173.02:17:49.08#ibcon#read 3, iclass 15, count 2 2006.173.02:17:49.08#ibcon#about to read 4, iclass 15, count 2 2006.173.02:17:49.08#ibcon#read 4, iclass 15, count 2 2006.173.02:17:49.08#ibcon#about to read 5, iclass 15, count 2 2006.173.02:17:49.08#ibcon#read 5, iclass 15, count 2 2006.173.02:17:49.08#ibcon#about to read 6, iclass 15, count 2 2006.173.02:17:49.08#ibcon#read 6, iclass 15, count 2 2006.173.02:17:49.08#ibcon#end of sib2, iclass 15, count 2 2006.173.02:17:49.08#ibcon#*mode == 0, iclass 15, count 2 2006.173.02:17:49.08#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.02:17:49.08#ibcon#[25=AT08-04\r\n] 2006.173.02:17:49.08#ibcon#*before write, iclass 15, count 2 2006.173.02:17:49.08#ibcon#enter sib2, iclass 15, count 2 2006.173.02:17:49.08#ibcon#flushed, iclass 15, count 2 2006.173.02:17:49.08#ibcon#about to write, iclass 15, count 2 2006.173.02:17:49.08#ibcon#wrote, iclass 15, count 2 2006.173.02:17:49.08#ibcon#about to read 3, iclass 15, count 2 2006.173.02:17:49.11#ibcon#read 3, iclass 15, count 2 2006.173.02:17:49.11#ibcon#about to read 4, iclass 15, count 2 2006.173.02:17:49.11#ibcon#read 4, iclass 15, count 2 2006.173.02:17:49.11#ibcon#about to read 5, iclass 15, count 2 2006.173.02:17:49.11#ibcon#read 5, iclass 15, count 2 2006.173.02:17:49.11#ibcon#about to read 6, iclass 15, count 2 2006.173.02:17:49.11#ibcon#read 6, iclass 15, count 2 2006.173.02:17:49.11#ibcon#end of sib2, iclass 15, count 2 2006.173.02:17:49.11#ibcon#*after write, iclass 15, count 2 2006.173.02:17:49.11#ibcon#*before return 0, iclass 15, count 2 2006.173.02:17:49.11#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.02:17:49.11#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.02:17:49.11#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.02:17:49.11#ibcon#ireg 7 cls_cnt 0 2006.173.02:17:49.11#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.02:17:49.23#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.02:17:49.23#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.02:17:49.23#ibcon#enter wrdev, iclass 15, count 0 2006.173.02:17:49.23#ibcon#first serial, iclass 15, count 0 2006.173.02:17:49.23#ibcon#enter sib2, iclass 15, count 0 2006.173.02:17:49.23#ibcon#flushed, iclass 15, count 0 2006.173.02:17:49.23#ibcon#about to write, iclass 15, count 0 2006.173.02:17:49.23#ibcon#wrote, iclass 15, count 0 2006.173.02:17:49.23#ibcon#about to read 3, iclass 15, count 0 2006.173.02:17:49.25#ibcon#read 3, iclass 15, count 0 2006.173.02:17:49.25#ibcon#about to read 4, iclass 15, count 0 2006.173.02:17:49.25#ibcon#read 4, iclass 15, count 0 2006.173.02:17:49.25#ibcon#about to read 5, iclass 15, count 0 2006.173.02:17:49.25#ibcon#read 5, iclass 15, count 0 2006.173.02:17:49.25#ibcon#about to read 6, iclass 15, count 0 2006.173.02:17:49.25#ibcon#read 6, iclass 15, count 0 2006.173.02:17:49.25#ibcon#end of sib2, iclass 15, count 0 2006.173.02:17:49.25#ibcon#*mode == 0, iclass 15, count 0 2006.173.02:17:49.25#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.02:17:49.25#ibcon#[25=USB\r\n] 2006.173.02:17:49.25#ibcon#*before write, iclass 15, count 0 2006.173.02:17:49.25#ibcon#enter sib2, iclass 15, count 0 2006.173.02:17:49.25#ibcon#flushed, iclass 15, count 0 2006.173.02:17:49.25#ibcon#about to write, iclass 15, count 0 2006.173.02:17:49.25#ibcon#wrote, iclass 15, count 0 2006.173.02:17:49.25#ibcon#about to read 3, iclass 15, count 0 2006.173.02:17:49.28#ibcon#read 3, iclass 15, count 0 2006.173.02:17:49.28#ibcon#about to read 4, iclass 15, count 0 2006.173.02:17:49.28#ibcon#read 4, iclass 15, count 0 2006.173.02:17:49.28#ibcon#about to read 5, iclass 15, count 0 2006.173.02:17:49.28#ibcon#read 5, iclass 15, count 0 2006.173.02:17:49.28#ibcon#about to read 6, iclass 15, count 0 2006.173.02:17:49.28#ibcon#read 6, iclass 15, count 0 2006.173.02:17:49.28#ibcon#end of sib2, iclass 15, count 0 2006.173.02:17:49.28#ibcon#*after write, iclass 15, count 0 2006.173.02:17:49.28#ibcon#*before return 0, iclass 15, count 0 2006.173.02:17:49.28#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.02:17:49.28#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.02:17:49.28#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.02:17:49.28#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.02:17:49.28$vck44/vblo=1,629.99 2006.173.02:17:49.28#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.02:17:49.28#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.02:17:49.28#ibcon#ireg 17 cls_cnt 0 2006.173.02:17:49.28#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.02:17:49.28#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.02:17:49.28#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.02:17:49.28#ibcon#enter wrdev, iclass 17, count 0 2006.173.02:17:49.28#ibcon#first serial, iclass 17, count 0 2006.173.02:17:49.28#ibcon#enter sib2, iclass 17, count 0 2006.173.02:17:49.28#ibcon#flushed, iclass 17, count 0 2006.173.02:17:49.28#ibcon#about to write, iclass 17, count 0 2006.173.02:17:49.28#ibcon#wrote, iclass 17, count 0 2006.173.02:17:49.28#ibcon#about to read 3, iclass 17, count 0 2006.173.02:17:49.30#ibcon#read 3, iclass 17, count 0 2006.173.02:17:49.30#ibcon#about to read 4, iclass 17, count 0 2006.173.02:17:49.30#ibcon#read 4, iclass 17, count 0 2006.173.02:17:49.30#ibcon#about to read 5, iclass 17, count 0 2006.173.02:17:49.30#ibcon#read 5, iclass 17, count 0 2006.173.02:17:49.30#ibcon#about to read 6, iclass 17, count 0 2006.173.02:17:49.30#ibcon#read 6, iclass 17, count 0 2006.173.02:17:49.30#ibcon#end of sib2, iclass 17, count 0 2006.173.02:17:49.30#ibcon#*mode == 0, iclass 17, count 0 2006.173.02:17:49.30#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.02:17:49.30#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.02:17:49.30#ibcon#*before write, iclass 17, count 0 2006.173.02:17:49.30#ibcon#enter sib2, iclass 17, count 0 2006.173.02:17:49.30#ibcon#flushed, iclass 17, count 0 2006.173.02:17:49.30#ibcon#about to write, iclass 17, count 0 2006.173.02:17:49.30#ibcon#wrote, iclass 17, count 0 2006.173.02:17:49.30#ibcon#about to read 3, iclass 17, count 0 2006.173.02:17:49.34#ibcon#read 3, iclass 17, count 0 2006.173.02:17:49.34#ibcon#about to read 4, iclass 17, count 0 2006.173.02:17:49.34#ibcon#read 4, iclass 17, count 0 2006.173.02:17:49.34#ibcon#about to read 5, iclass 17, count 0 2006.173.02:17:49.34#ibcon#read 5, iclass 17, count 0 2006.173.02:17:49.34#ibcon#about to read 6, iclass 17, count 0 2006.173.02:17:49.34#ibcon#read 6, iclass 17, count 0 2006.173.02:17:49.34#ibcon#end of sib2, iclass 17, count 0 2006.173.02:17:49.34#ibcon#*after write, iclass 17, count 0 2006.173.02:17:49.34#ibcon#*before return 0, iclass 17, count 0 2006.173.02:17:49.34#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.02:17:49.34#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.02:17:49.34#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.02:17:49.34#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.02:17:49.34$vck44/vb=1,4 2006.173.02:17:49.34#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.02:17:49.34#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.02:17:49.34#ibcon#ireg 11 cls_cnt 2 2006.173.02:17:49.34#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.02:17:49.34#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.02:17:49.34#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.02:17:49.34#ibcon#enter wrdev, iclass 19, count 2 2006.173.02:17:49.34#ibcon#first serial, iclass 19, count 2 2006.173.02:17:49.34#ibcon#enter sib2, iclass 19, count 2 2006.173.02:17:49.34#ibcon#flushed, iclass 19, count 2 2006.173.02:17:49.34#ibcon#about to write, iclass 19, count 2 2006.173.02:17:49.34#ibcon#wrote, iclass 19, count 2 2006.173.02:17:49.34#ibcon#about to read 3, iclass 19, count 2 2006.173.02:17:49.36#ibcon#read 3, iclass 19, count 2 2006.173.02:17:49.36#ibcon#about to read 4, iclass 19, count 2 2006.173.02:17:49.36#ibcon#read 4, iclass 19, count 2 2006.173.02:17:49.36#ibcon#about to read 5, iclass 19, count 2 2006.173.02:17:49.36#ibcon#read 5, iclass 19, count 2 2006.173.02:17:49.36#ibcon#about to read 6, iclass 19, count 2 2006.173.02:17:49.36#ibcon#read 6, iclass 19, count 2 2006.173.02:17:49.36#ibcon#end of sib2, iclass 19, count 2 2006.173.02:17:49.36#ibcon#*mode == 0, iclass 19, count 2 2006.173.02:17:49.36#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.02:17:49.36#ibcon#[27=AT01-04\r\n] 2006.173.02:17:49.36#ibcon#*before write, iclass 19, count 2 2006.173.02:17:49.36#ibcon#enter sib2, iclass 19, count 2 2006.173.02:17:49.36#ibcon#flushed, iclass 19, count 2 2006.173.02:17:49.36#ibcon#about to write, iclass 19, count 2 2006.173.02:17:49.36#ibcon#wrote, iclass 19, count 2 2006.173.02:17:49.36#ibcon#about to read 3, iclass 19, count 2 2006.173.02:17:49.39#ibcon#read 3, iclass 19, count 2 2006.173.02:17:49.39#ibcon#about to read 4, iclass 19, count 2 2006.173.02:17:49.39#ibcon#read 4, iclass 19, count 2 2006.173.02:17:49.39#ibcon#about to read 5, iclass 19, count 2 2006.173.02:17:49.39#ibcon#read 5, iclass 19, count 2 2006.173.02:17:49.39#ibcon#about to read 6, iclass 19, count 2 2006.173.02:17:49.39#ibcon#read 6, iclass 19, count 2 2006.173.02:17:49.39#ibcon#end of sib2, iclass 19, count 2 2006.173.02:17:49.39#ibcon#*after write, iclass 19, count 2 2006.173.02:17:49.39#ibcon#*before return 0, iclass 19, count 2 2006.173.02:17:49.39#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.02:17:49.39#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.02:17:49.39#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.02:17:49.39#ibcon#ireg 7 cls_cnt 0 2006.173.02:17:49.39#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.02:17:49.51#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.02:17:49.51#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.02:17:49.51#ibcon#enter wrdev, iclass 19, count 0 2006.173.02:17:49.51#ibcon#first serial, iclass 19, count 0 2006.173.02:17:49.51#ibcon#enter sib2, iclass 19, count 0 2006.173.02:17:49.51#ibcon#flushed, iclass 19, count 0 2006.173.02:17:49.51#ibcon#about to write, iclass 19, count 0 2006.173.02:17:49.51#ibcon#wrote, iclass 19, count 0 2006.173.02:17:49.51#ibcon#about to read 3, iclass 19, count 0 2006.173.02:17:49.53#ibcon#read 3, iclass 19, count 0 2006.173.02:17:49.53#ibcon#about to read 4, iclass 19, count 0 2006.173.02:17:49.53#ibcon#read 4, iclass 19, count 0 2006.173.02:17:49.53#ibcon#about to read 5, iclass 19, count 0 2006.173.02:17:49.53#ibcon#read 5, iclass 19, count 0 2006.173.02:17:49.53#ibcon#about to read 6, iclass 19, count 0 2006.173.02:17:49.53#ibcon#read 6, iclass 19, count 0 2006.173.02:17:49.53#ibcon#end of sib2, iclass 19, count 0 2006.173.02:17:49.53#ibcon#*mode == 0, iclass 19, count 0 2006.173.02:17:49.53#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.02:17:49.53#ibcon#[27=USB\r\n] 2006.173.02:17:49.53#ibcon#*before write, iclass 19, count 0 2006.173.02:17:49.53#ibcon#enter sib2, iclass 19, count 0 2006.173.02:17:49.53#ibcon#flushed, iclass 19, count 0 2006.173.02:17:49.53#ibcon#about to write, iclass 19, count 0 2006.173.02:17:49.53#ibcon#wrote, iclass 19, count 0 2006.173.02:17:49.53#ibcon#about to read 3, iclass 19, count 0 2006.173.02:17:49.56#ibcon#read 3, iclass 19, count 0 2006.173.02:17:49.56#ibcon#about to read 4, iclass 19, count 0 2006.173.02:17:49.56#ibcon#read 4, iclass 19, count 0 2006.173.02:17:49.56#ibcon#about to read 5, iclass 19, count 0 2006.173.02:17:49.56#ibcon#read 5, iclass 19, count 0 2006.173.02:17:49.56#ibcon#about to read 6, iclass 19, count 0 2006.173.02:17:49.56#ibcon#read 6, iclass 19, count 0 2006.173.02:17:49.56#ibcon#end of sib2, iclass 19, count 0 2006.173.02:17:49.56#ibcon#*after write, iclass 19, count 0 2006.173.02:17:49.56#ibcon#*before return 0, iclass 19, count 0 2006.173.02:17:49.56#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.02:17:49.56#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.02:17:49.56#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.02:17:49.56#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.02:17:49.56$vck44/vblo=2,634.99 2006.173.02:17:49.56#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.02:17:49.56#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.02:17:49.56#ibcon#ireg 17 cls_cnt 0 2006.173.02:17:49.56#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.02:17:49.56#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.02:17:49.56#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.02:17:49.56#ibcon#enter wrdev, iclass 21, count 0 2006.173.02:17:49.56#ibcon#first serial, iclass 21, count 0 2006.173.02:17:49.56#ibcon#enter sib2, iclass 21, count 0 2006.173.02:17:49.56#ibcon#flushed, iclass 21, count 0 2006.173.02:17:49.56#ibcon#about to write, iclass 21, count 0 2006.173.02:17:49.56#ibcon#wrote, iclass 21, count 0 2006.173.02:17:49.56#ibcon#about to read 3, iclass 21, count 0 2006.173.02:17:49.58#ibcon#read 3, iclass 21, count 0 2006.173.02:17:49.58#ibcon#about to read 4, iclass 21, count 0 2006.173.02:17:49.58#ibcon#read 4, iclass 21, count 0 2006.173.02:17:49.58#ibcon#about to read 5, iclass 21, count 0 2006.173.02:17:49.58#ibcon#read 5, iclass 21, count 0 2006.173.02:17:49.58#ibcon#about to read 6, iclass 21, count 0 2006.173.02:17:49.58#ibcon#read 6, iclass 21, count 0 2006.173.02:17:49.58#ibcon#end of sib2, iclass 21, count 0 2006.173.02:17:49.58#ibcon#*mode == 0, iclass 21, count 0 2006.173.02:17:49.58#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.02:17:49.58#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.02:17:49.58#ibcon#*before write, iclass 21, count 0 2006.173.02:17:49.58#ibcon#enter sib2, iclass 21, count 0 2006.173.02:17:49.58#ibcon#flushed, iclass 21, count 0 2006.173.02:17:49.58#ibcon#about to write, iclass 21, count 0 2006.173.02:17:49.58#ibcon#wrote, iclass 21, count 0 2006.173.02:17:49.58#ibcon#about to read 3, iclass 21, count 0 2006.173.02:17:49.62#ibcon#read 3, iclass 21, count 0 2006.173.02:17:49.62#ibcon#about to read 4, iclass 21, count 0 2006.173.02:17:49.62#ibcon#read 4, iclass 21, count 0 2006.173.02:17:49.62#ibcon#about to read 5, iclass 21, count 0 2006.173.02:17:49.62#ibcon#read 5, iclass 21, count 0 2006.173.02:17:49.62#ibcon#about to read 6, iclass 21, count 0 2006.173.02:17:49.62#ibcon#read 6, iclass 21, count 0 2006.173.02:17:49.62#ibcon#end of sib2, iclass 21, count 0 2006.173.02:17:49.62#ibcon#*after write, iclass 21, count 0 2006.173.02:17:49.62#ibcon#*before return 0, iclass 21, count 0 2006.173.02:17:49.62#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.02:17:49.62#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.02:17:49.62#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.02:17:49.62#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.02:17:49.62$vck44/vb=2,4 2006.173.02:17:49.62#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.02:17:49.62#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.02:17:49.62#ibcon#ireg 11 cls_cnt 2 2006.173.02:17:49.62#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.02:17:49.68#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.02:17:49.68#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.02:17:49.68#ibcon#enter wrdev, iclass 23, count 2 2006.173.02:17:49.68#ibcon#first serial, iclass 23, count 2 2006.173.02:17:49.68#ibcon#enter sib2, iclass 23, count 2 2006.173.02:17:49.68#ibcon#flushed, iclass 23, count 2 2006.173.02:17:49.68#ibcon#about to write, iclass 23, count 2 2006.173.02:17:49.68#ibcon#wrote, iclass 23, count 2 2006.173.02:17:49.68#ibcon#about to read 3, iclass 23, count 2 2006.173.02:17:49.70#ibcon#read 3, iclass 23, count 2 2006.173.02:17:49.70#ibcon#about to read 4, iclass 23, count 2 2006.173.02:17:49.70#ibcon#read 4, iclass 23, count 2 2006.173.02:17:49.70#ibcon#about to read 5, iclass 23, count 2 2006.173.02:17:49.70#ibcon#read 5, iclass 23, count 2 2006.173.02:17:49.70#ibcon#about to read 6, iclass 23, count 2 2006.173.02:17:49.70#ibcon#read 6, iclass 23, count 2 2006.173.02:17:49.70#ibcon#end of sib2, iclass 23, count 2 2006.173.02:17:49.70#ibcon#*mode == 0, iclass 23, count 2 2006.173.02:17:49.70#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.02:17:49.70#ibcon#[27=AT02-04\r\n] 2006.173.02:17:49.70#ibcon#*before write, iclass 23, count 2 2006.173.02:17:49.70#ibcon#enter sib2, iclass 23, count 2 2006.173.02:17:49.70#ibcon#flushed, iclass 23, count 2 2006.173.02:17:49.70#ibcon#about to write, iclass 23, count 2 2006.173.02:17:49.70#ibcon#wrote, iclass 23, count 2 2006.173.02:17:49.70#ibcon#about to read 3, iclass 23, count 2 2006.173.02:17:49.73#ibcon#read 3, iclass 23, count 2 2006.173.02:17:49.73#ibcon#about to read 4, iclass 23, count 2 2006.173.02:17:49.73#ibcon#read 4, iclass 23, count 2 2006.173.02:17:49.73#ibcon#about to read 5, iclass 23, count 2 2006.173.02:17:49.73#ibcon#read 5, iclass 23, count 2 2006.173.02:17:49.73#ibcon#about to read 6, iclass 23, count 2 2006.173.02:17:49.73#ibcon#read 6, iclass 23, count 2 2006.173.02:17:49.73#ibcon#end of sib2, iclass 23, count 2 2006.173.02:17:49.73#ibcon#*after write, iclass 23, count 2 2006.173.02:17:49.73#ibcon#*before return 0, iclass 23, count 2 2006.173.02:17:49.73#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.02:17:49.73#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.02:17:49.73#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.02:17:49.73#ibcon#ireg 7 cls_cnt 0 2006.173.02:17:49.73#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.02:17:49.85#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.02:17:49.85#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.02:17:49.85#ibcon#enter wrdev, iclass 23, count 0 2006.173.02:17:49.85#ibcon#first serial, iclass 23, count 0 2006.173.02:17:49.85#ibcon#enter sib2, iclass 23, count 0 2006.173.02:17:49.85#ibcon#flushed, iclass 23, count 0 2006.173.02:17:49.85#ibcon#about to write, iclass 23, count 0 2006.173.02:17:49.85#ibcon#wrote, iclass 23, count 0 2006.173.02:17:49.85#ibcon#about to read 3, iclass 23, count 0 2006.173.02:17:49.87#ibcon#read 3, iclass 23, count 0 2006.173.02:17:49.87#ibcon#about to read 4, iclass 23, count 0 2006.173.02:17:49.87#ibcon#read 4, iclass 23, count 0 2006.173.02:17:49.87#ibcon#about to read 5, iclass 23, count 0 2006.173.02:17:49.87#ibcon#read 5, iclass 23, count 0 2006.173.02:17:49.87#ibcon#about to read 6, iclass 23, count 0 2006.173.02:17:49.87#ibcon#read 6, iclass 23, count 0 2006.173.02:17:49.87#ibcon#end of sib2, iclass 23, count 0 2006.173.02:17:49.87#ibcon#*mode == 0, iclass 23, count 0 2006.173.02:17:49.87#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.02:17:49.87#ibcon#[27=USB\r\n] 2006.173.02:17:49.87#ibcon#*before write, iclass 23, count 0 2006.173.02:17:49.87#ibcon#enter sib2, iclass 23, count 0 2006.173.02:17:49.87#ibcon#flushed, iclass 23, count 0 2006.173.02:17:49.87#ibcon#about to write, iclass 23, count 0 2006.173.02:17:49.87#ibcon#wrote, iclass 23, count 0 2006.173.02:17:49.87#ibcon#about to read 3, iclass 23, count 0 2006.173.02:17:49.90#ibcon#read 3, iclass 23, count 0 2006.173.02:17:49.90#ibcon#about to read 4, iclass 23, count 0 2006.173.02:17:49.90#ibcon#read 4, iclass 23, count 0 2006.173.02:17:49.90#ibcon#about to read 5, iclass 23, count 0 2006.173.02:17:49.90#ibcon#read 5, iclass 23, count 0 2006.173.02:17:49.90#ibcon#about to read 6, iclass 23, count 0 2006.173.02:17:49.90#ibcon#read 6, iclass 23, count 0 2006.173.02:17:49.90#ibcon#end of sib2, iclass 23, count 0 2006.173.02:17:49.90#ibcon#*after write, iclass 23, count 0 2006.173.02:17:49.90#ibcon#*before return 0, iclass 23, count 0 2006.173.02:17:49.90#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.02:17:49.90#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.02:17:49.90#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.02:17:49.90#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.02:17:49.90$vck44/vblo=3,649.99 2006.173.02:17:49.90#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.02:17:49.90#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.02:17:49.90#ibcon#ireg 17 cls_cnt 0 2006.173.02:17:49.90#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.02:17:49.90#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.02:17:49.90#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.02:17:49.90#ibcon#enter wrdev, iclass 25, count 0 2006.173.02:17:49.90#ibcon#first serial, iclass 25, count 0 2006.173.02:17:49.90#ibcon#enter sib2, iclass 25, count 0 2006.173.02:17:49.90#ibcon#flushed, iclass 25, count 0 2006.173.02:17:49.90#ibcon#about to write, iclass 25, count 0 2006.173.02:17:49.90#ibcon#wrote, iclass 25, count 0 2006.173.02:17:49.90#ibcon#about to read 3, iclass 25, count 0 2006.173.02:17:49.92#ibcon#read 3, iclass 25, count 0 2006.173.02:17:49.92#ibcon#about to read 4, iclass 25, count 0 2006.173.02:17:49.92#ibcon#read 4, iclass 25, count 0 2006.173.02:17:49.92#ibcon#about to read 5, iclass 25, count 0 2006.173.02:17:49.92#ibcon#read 5, iclass 25, count 0 2006.173.02:17:49.92#ibcon#about to read 6, iclass 25, count 0 2006.173.02:17:49.92#ibcon#read 6, iclass 25, count 0 2006.173.02:17:49.92#ibcon#end of sib2, iclass 25, count 0 2006.173.02:17:49.92#ibcon#*mode == 0, iclass 25, count 0 2006.173.02:17:49.92#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.02:17:49.92#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.02:17:49.92#ibcon#*before write, iclass 25, count 0 2006.173.02:17:49.92#ibcon#enter sib2, iclass 25, count 0 2006.173.02:17:49.92#ibcon#flushed, iclass 25, count 0 2006.173.02:17:49.92#ibcon#about to write, iclass 25, count 0 2006.173.02:17:49.92#ibcon#wrote, iclass 25, count 0 2006.173.02:17:49.92#ibcon#about to read 3, iclass 25, count 0 2006.173.02:17:49.96#ibcon#read 3, iclass 25, count 0 2006.173.02:17:49.96#ibcon#about to read 4, iclass 25, count 0 2006.173.02:17:49.96#ibcon#read 4, iclass 25, count 0 2006.173.02:17:49.96#ibcon#about to read 5, iclass 25, count 0 2006.173.02:17:49.96#ibcon#read 5, iclass 25, count 0 2006.173.02:17:49.96#ibcon#about to read 6, iclass 25, count 0 2006.173.02:17:49.96#ibcon#read 6, iclass 25, count 0 2006.173.02:17:49.96#ibcon#end of sib2, iclass 25, count 0 2006.173.02:17:49.96#ibcon#*after write, iclass 25, count 0 2006.173.02:17:49.96#ibcon#*before return 0, iclass 25, count 0 2006.173.02:17:49.96#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.02:17:49.96#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.02:17:49.96#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.02:17:49.96#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.02:17:49.96$vck44/vb=3,4 2006.173.02:17:49.96#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.02:17:49.96#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.02:17:49.96#ibcon#ireg 11 cls_cnt 2 2006.173.02:17:49.96#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.02:17:50.02#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.02:17:50.02#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.02:17:50.02#ibcon#enter wrdev, iclass 27, count 2 2006.173.02:17:50.02#ibcon#first serial, iclass 27, count 2 2006.173.02:17:50.02#ibcon#enter sib2, iclass 27, count 2 2006.173.02:17:50.02#ibcon#flushed, iclass 27, count 2 2006.173.02:17:50.02#ibcon#about to write, iclass 27, count 2 2006.173.02:17:50.02#ibcon#wrote, iclass 27, count 2 2006.173.02:17:50.02#ibcon#about to read 3, iclass 27, count 2 2006.173.02:17:50.04#ibcon#read 3, iclass 27, count 2 2006.173.02:17:50.04#ibcon#about to read 4, iclass 27, count 2 2006.173.02:17:50.04#ibcon#read 4, iclass 27, count 2 2006.173.02:17:50.04#ibcon#about to read 5, iclass 27, count 2 2006.173.02:17:50.04#ibcon#read 5, iclass 27, count 2 2006.173.02:17:50.04#ibcon#about to read 6, iclass 27, count 2 2006.173.02:17:50.04#ibcon#read 6, iclass 27, count 2 2006.173.02:17:50.04#ibcon#end of sib2, iclass 27, count 2 2006.173.02:17:50.04#ibcon#*mode == 0, iclass 27, count 2 2006.173.02:17:50.04#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.02:17:50.04#ibcon#[27=AT03-04\r\n] 2006.173.02:17:50.04#ibcon#*before write, iclass 27, count 2 2006.173.02:17:50.04#ibcon#enter sib2, iclass 27, count 2 2006.173.02:17:50.04#ibcon#flushed, iclass 27, count 2 2006.173.02:17:50.04#ibcon#about to write, iclass 27, count 2 2006.173.02:17:50.04#ibcon#wrote, iclass 27, count 2 2006.173.02:17:50.04#ibcon#about to read 3, iclass 27, count 2 2006.173.02:17:50.07#ibcon#read 3, iclass 27, count 2 2006.173.02:17:50.07#ibcon#about to read 4, iclass 27, count 2 2006.173.02:17:50.07#ibcon#read 4, iclass 27, count 2 2006.173.02:17:50.07#ibcon#about to read 5, iclass 27, count 2 2006.173.02:17:50.07#ibcon#read 5, iclass 27, count 2 2006.173.02:17:50.07#ibcon#about to read 6, iclass 27, count 2 2006.173.02:17:50.07#ibcon#read 6, iclass 27, count 2 2006.173.02:17:50.07#ibcon#end of sib2, iclass 27, count 2 2006.173.02:17:50.07#ibcon#*after write, iclass 27, count 2 2006.173.02:17:50.07#ibcon#*before return 0, iclass 27, count 2 2006.173.02:17:50.07#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.02:17:50.07#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.02:17:50.07#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.02:17:50.07#ibcon#ireg 7 cls_cnt 0 2006.173.02:17:50.07#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.02:17:50.19#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.02:17:50.19#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.02:17:50.19#ibcon#enter wrdev, iclass 27, count 0 2006.173.02:17:50.19#ibcon#first serial, iclass 27, count 0 2006.173.02:17:50.19#ibcon#enter sib2, iclass 27, count 0 2006.173.02:17:50.19#ibcon#flushed, iclass 27, count 0 2006.173.02:17:50.19#ibcon#about to write, iclass 27, count 0 2006.173.02:17:50.19#ibcon#wrote, iclass 27, count 0 2006.173.02:17:50.19#ibcon#about to read 3, iclass 27, count 0 2006.173.02:17:50.21#ibcon#read 3, iclass 27, count 0 2006.173.02:17:50.21#ibcon#about to read 4, iclass 27, count 0 2006.173.02:17:50.21#ibcon#read 4, iclass 27, count 0 2006.173.02:17:50.21#ibcon#about to read 5, iclass 27, count 0 2006.173.02:17:50.21#ibcon#read 5, iclass 27, count 0 2006.173.02:17:50.21#ibcon#about to read 6, iclass 27, count 0 2006.173.02:17:50.21#ibcon#read 6, iclass 27, count 0 2006.173.02:17:50.21#ibcon#end of sib2, iclass 27, count 0 2006.173.02:17:50.21#ibcon#*mode == 0, iclass 27, count 0 2006.173.02:17:50.21#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.02:17:50.21#ibcon#[27=USB\r\n] 2006.173.02:17:50.21#ibcon#*before write, iclass 27, count 0 2006.173.02:17:50.21#ibcon#enter sib2, iclass 27, count 0 2006.173.02:17:50.21#ibcon#flushed, iclass 27, count 0 2006.173.02:17:50.21#ibcon#about to write, iclass 27, count 0 2006.173.02:17:50.21#ibcon#wrote, iclass 27, count 0 2006.173.02:17:50.21#ibcon#about to read 3, iclass 27, count 0 2006.173.02:17:50.24#ibcon#read 3, iclass 27, count 0 2006.173.02:17:50.24#ibcon#about to read 4, iclass 27, count 0 2006.173.02:17:50.24#ibcon#read 4, iclass 27, count 0 2006.173.02:17:50.24#ibcon#about to read 5, iclass 27, count 0 2006.173.02:17:50.24#ibcon#read 5, iclass 27, count 0 2006.173.02:17:50.24#ibcon#about to read 6, iclass 27, count 0 2006.173.02:17:50.24#ibcon#read 6, iclass 27, count 0 2006.173.02:17:50.24#ibcon#end of sib2, iclass 27, count 0 2006.173.02:17:50.24#ibcon#*after write, iclass 27, count 0 2006.173.02:17:50.24#ibcon#*before return 0, iclass 27, count 0 2006.173.02:17:50.24#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.02:17:50.24#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.02:17:50.24#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.02:17:50.24#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.02:17:50.24$vck44/vblo=4,679.99 2006.173.02:17:50.24#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.02:17:50.24#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.02:17:50.24#ibcon#ireg 17 cls_cnt 0 2006.173.02:17:50.24#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.02:17:50.24#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.02:17:50.24#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.02:17:50.24#ibcon#enter wrdev, iclass 29, count 0 2006.173.02:17:50.24#ibcon#first serial, iclass 29, count 0 2006.173.02:17:50.24#ibcon#enter sib2, iclass 29, count 0 2006.173.02:17:50.24#ibcon#flushed, iclass 29, count 0 2006.173.02:17:50.24#ibcon#about to write, iclass 29, count 0 2006.173.02:17:50.24#ibcon#wrote, iclass 29, count 0 2006.173.02:17:50.24#ibcon#about to read 3, iclass 29, count 0 2006.173.02:17:50.26#ibcon#read 3, iclass 29, count 0 2006.173.02:17:50.26#ibcon#about to read 4, iclass 29, count 0 2006.173.02:17:50.26#ibcon#read 4, iclass 29, count 0 2006.173.02:17:50.26#ibcon#about to read 5, iclass 29, count 0 2006.173.02:17:50.26#ibcon#read 5, iclass 29, count 0 2006.173.02:17:50.26#ibcon#about to read 6, iclass 29, count 0 2006.173.02:17:50.26#ibcon#read 6, iclass 29, count 0 2006.173.02:17:50.26#ibcon#end of sib2, iclass 29, count 0 2006.173.02:17:50.26#ibcon#*mode == 0, iclass 29, count 0 2006.173.02:17:50.26#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.02:17:50.26#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.02:17:50.26#ibcon#*before write, iclass 29, count 0 2006.173.02:17:50.26#ibcon#enter sib2, iclass 29, count 0 2006.173.02:17:50.26#ibcon#flushed, iclass 29, count 0 2006.173.02:17:50.26#ibcon#about to write, iclass 29, count 0 2006.173.02:17:50.26#ibcon#wrote, iclass 29, count 0 2006.173.02:17:50.26#ibcon#about to read 3, iclass 29, count 0 2006.173.02:17:50.30#ibcon#read 3, iclass 29, count 0 2006.173.02:17:50.30#ibcon#about to read 4, iclass 29, count 0 2006.173.02:17:50.30#ibcon#read 4, iclass 29, count 0 2006.173.02:17:50.30#ibcon#about to read 5, iclass 29, count 0 2006.173.02:17:50.30#ibcon#read 5, iclass 29, count 0 2006.173.02:17:50.30#ibcon#about to read 6, iclass 29, count 0 2006.173.02:17:50.30#ibcon#read 6, iclass 29, count 0 2006.173.02:17:50.30#ibcon#end of sib2, iclass 29, count 0 2006.173.02:17:50.30#ibcon#*after write, iclass 29, count 0 2006.173.02:17:50.30#ibcon#*before return 0, iclass 29, count 0 2006.173.02:17:50.30#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.02:17:50.30#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.02:17:50.30#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.02:17:50.30#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.02:17:50.30$vck44/vb=4,4 2006.173.02:17:50.30#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.02:17:50.30#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.02:17:50.30#ibcon#ireg 11 cls_cnt 2 2006.173.02:17:50.30#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.02:17:50.36#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.02:17:50.36#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.02:17:50.36#ibcon#enter wrdev, iclass 31, count 2 2006.173.02:17:50.36#ibcon#first serial, iclass 31, count 2 2006.173.02:17:50.36#ibcon#enter sib2, iclass 31, count 2 2006.173.02:17:50.36#ibcon#flushed, iclass 31, count 2 2006.173.02:17:50.36#ibcon#about to write, iclass 31, count 2 2006.173.02:17:50.36#ibcon#wrote, iclass 31, count 2 2006.173.02:17:50.36#ibcon#about to read 3, iclass 31, count 2 2006.173.02:17:50.38#ibcon#read 3, iclass 31, count 2 2006.173.02:17:50.38#ibcon#about to read 4, iclass 31, count 2 2006.173.02:17:50.38#ibcon#read 4, iclass 31, count 2 2006.173.02:17:50.38#ibcon#about to read 5, iclass 31, count 2 2006.173.02:17:50.38#ibcon#read 5, iclass 31, count 2 2006.173.02:17:50.38#ibcon#about to read 6, iclass 31, count 2 2006.173.02:17:50.38#ibcon#read 6, iclass 31, count 2 2006.173.02:17:50.38#ibcon#end of sib2, iclass 31, count 2 2006.173.02:17:50.38#ibcon#*mode == 0, iclass 31, count 2 2006.173.02:17:50.38#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.02:17:50.38#ibcon#[27=AT04-04\r\n] 2006.173.02:17:50.38#ibcon#*before write, iclass 31, count 2 2006.173.02:17:50.38#ibcon#enter sib2, iclass 31, count 2 2006.173.02:17:50.38#ibcon#flushed, iclass 31, count 2 2006.173.02:17:50.38#ibcon#about to write, iclass 31, count 2 2006.173.02:17:50.38#ibcon#wrote, iclass 31, count 2 2006.173.02:17:50.38#ibcon#about to read 3, iclass 31, count 2 2006.173.02:17:50.41#ibcon#read 3, iclass 31, count 2 2006.173.02:17:50.41#ibcon#about to read 4, iclass 31, count 2 2006.173.02:17:50.41#ibcon#read 4, iclass 31, count 2 2006.173.02:17:50.41#ibcon#about to read 5, iclass 31, count 2 2006.173.02:17:50.41#ibcon#read 5, iclass 31, count 2 2006.173.02:17:50.41#ibcon#about to read 6, iclass 31, count 2 2006.173.02:17:50.41#ibcon#read 6, iclass 31, count 2 2006.173.02:17:50.41#ibcon#end of sib2, iclass 31, count 2 2006.173.02:17:50.41#ibcon#*after write, iclass 31, count 2 2006.173.02:17:50.41#ibcon#*before return 0, iclass 31, count 2 2006.173.02:17:50.41#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.02:17:50.41#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.02:17:50.41#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.02:17:50.41#ibcon#ireg 7 cls_cnt 0 2006.173.02:17:50.41#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.02:17:50.53#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.02:17:50.53#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.02:17:50.53#ibcon#enter wrdev, iclass 31, count 0 2006.173.02:17:50.53#ibcon#first serial, iclass 31, count 0 2006.173.02:17:50.53#ibcon#enter sib2, iclass 31, count 0 2006.173.02:17:50.53#ibcon#flushed, iclass 31, count 0 2006.173.02:17:50.53#ibcon#about to write, iclass 31, count 0 2006.173.02:17:50.53#ibcon#wrote, iclass 31, count 0 2006.173.02:17:50.53#ibcon#about to read 3, iclass 31, count 0 2006.173.02:17:50.55#ibcon#read 3, iclass 31, count 0 2006.173.02:17:50.55#ibcon#about to read 4, iclass 31, count 0 2006.173.02:17:50.55#ibcon#read 4, iclass 31, count 0 2006.173.02:17:50.55#ibcon#about to read 5, iclass 31, count 0 2006.173.02:17:50.55#ibcon#read 5, iclass 31, count 0 2006.173.02:17:50.55#ibcon#about to read 6, iclass 31, count 0 2006.173.02:17:50.55#ibcon#read 6, iclass 31, count 0 2006.173.02:17:50.55#ibcon#end of sib2, iclass 31, count 0 2006.173.02:17:50.55#ibcon#*mode == 0, iclass 31, count 0 2006.173.02:17:50.55#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.02:17:50.55#ibcon#[27=USB\r\n] 2006.173.02:17:50.55#ibcon#*before write, iclass 31, count 0 2006.173.02:17:50.55#ibcon#enter sib2, iclass 31, count 0 2006.173.02:17:50.55#ibcon#flushed, iclass 31, count 0 2006.173.02:17:50.55#ibcon#about to write, iclass 31, count 0 2006.173.02:17:50.55#ibcon#wrote, iclass 31, count 0 2006.173.02:17:50.55#ibcon#about to read 3, iclass 31, count 0 2006.173.02:17:50.58#ibcon#read 3, iclass 31, count 0 2006.173.02:17:50.58#ibcon#about to read 4, iclass 31, count 0 2006.173.02:17:50.58#ibcon#read 4, iclass 31, count 0 2006.173.02:17:50.58#ibcon#about to read 5, iclass 31, count 0 2006.173.02:17:50.58#ibcon#read 5, iclass 31, count 0 2006.173.02:17:50.58#ibcon#about to read 6, iclass 31, count 0 2006.173.02:17:50.58#ibcon#read 6, iclass 31, count 0 2006.173.02:17:50.58#ibcon#end of sib2, iclass 31, count 0 2006.173.02:17:50.58#ibcon#*after write, iclass 31, count 0 2006.173.02:17:50.58#ibcon#*before return 0, iclass 31, count 0 2006.173.02:17:50.58#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.02:17:50.58#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.02:17:50.58#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.02:17:50.58#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.02:17:50.58$vck44/vblo=5,709.99 2006.173.02:17:50.58#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.02:17:50.58#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.02:17:50.58#ibcon#ireg 17 cls_cnt 0 2006.173.02:17:50.58#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.02:17:50.58#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.02:17:50.58#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.02:17:50.58#ibcon#enter wrdev, iclass 33, count 0 2006.173.02:17:50.58#ibcon#first serial, iclass 33, count 0 2006.173.02:17:50.58#ibcon#enter sib2, iclass 33, count 0 2006.173.02:17:50.58#ibcon#flushed, iclass 33, count 0 2006.173.02:17:50.58#ibcon#about to write, iclass 33, count 0 2006.173.02:17:50.58#ibcon#wrote, iclass 33, count 0 2006.173.02:17:50.58#ibcon#about to read 3, iclass 33, count 0 2006.173.02:17:50.60#ibcon#read 3, iclass 33, count 0 2006.173.02:17:50.60#ibcon#about to read 4, iclass 33, count 0 2006.173.02:17:50.60#ibcon#read 4, iclass 33, count 0 2006.173.02:17:50.60#ibcon#about to read 5, iclass 33, count 0 2006.173.02:17:50.60#ibcon#read 5, iclass 33, count 0 2006.173.02:17:50.60#ibcon#about to read 6, iclass 33, count 0 2006.173.02:17:50.60#ibcon#read 6, iclass 33, count 0 2006.173.02:17:50.60#ibcon#end of sib2, iclass 33, count 0 2006.173.02:17:50.60#ibcon#*mode == 0, iclass 33, count 0 2006.173.02:17:50.60#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.02:17:50.60#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.02:17:50.60#ibcon#*before write, iclass 33, count 0 2006.173.02:17:50.60#ibcon#enter sib2, iclass 33, count 0 2006.173.02:17:50.60#ibcon#flushed, iclass 33, count 0 2006.173.02:17:50.60#ibcon#about to write, iclass 33, count 0 2006.173.02:17:50.60#ibcon#wrote, iclass 33, count 0 2006.173.02:17:50.60#ibcon#about to read 3, iclass 33, count 0 2006.173.02:17:50.65#ibcon#read 3, iclass 33, count 0 2006.173.02:17:50.65#ibcon#about to read 4, iclass 33, count 0 2006.173.02:17:50.65#ibcon#read 4, iclass 33, count 0 2006.173.02:17:50.65#ibcon#about to read 5, iclass 33, count 0 2006.173.02:17:50.65#ibcon#read 5, iclass 33, count 0 2006.173.02:17:50.65#ibcon#about to read 6, iclass 33, count 0 2006.173.02:17:50.65#ibcon#read 6, iclass 33, count 0 2006.173.02:17:50.65#ibcon#end of sib2, iclass 33, count 0 2006.173.02:17:50.65#ibcon#*after write, iclass 33, count 0 2006.173.02:17:50.65#ibcon#*before return 0, iclass 33, count 0 2006.173.02:17:50.65#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.02:17:50.65#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.02:17:50.65#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.02:17:50.65#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.02:17:50.65$vck44/vb=5,4 2006.173.02:17:50.65#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.02:17:50.65#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.02:17:50.65#ibcon#ireg 11 cls_cnt 2 2006.173.02:17:50.65#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.02:17:50.69#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.02:17:50.69#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.02:17:50.69#ibcon#enter wrdev, iclass 35, count 2 2006.173.02:17:50.69#ibcon#first serial, iclass 35, count 2 2006.173.02:17:50.69#ibcon#enter sib2, iclass 35, count 2 2006.173.02:17:50.69#ibcon#flushed, iclass 35, count 2 2006.173.02:17:50.69#ibcon#about to write, iclass 35, count 2 2006.173.02:17:50.69#ibcon#wrote, iclass 35, count 2 2006.173.02:17:50.69#ibcon#about to read 3, iclass 35, count 2 2006.173.02:17:50.71#ibcon#read 3, iclass 35, count 2 2006.173.02:17:50.71#ibcon#about to read 4, iclass 35, count 2 2006.173.02:17:50.71#ibcon#read 4, iclass 35, count 2 2006.173.02:17:50.71#ibcon#about to read 5, iclass 35, count 2 2006.173.02:17:50.71#ibcon#read 5, iclass 35, count 2 2006.173.02:17:50.71#ibcon#about to read 6, iclass 35, count 2 2006.173.02:17:50.71#ibcon#read 6, iclass 35, count 2 2006.173.02:17:50.71#ibcon#end of sib2, iclass 35, count 2 2006.173.02:17:50.71#ibcon#*mode == 0, iclass 35, count 2 2006.173.02:17:50.71#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.02:17:50.71#ibcon#[27=AT05-04\r\n] 2006.173.02:17:50.71#ibcon#*before write, iclass 35, count 2 2006.173.02:17:50.71#ibcon#enter sib2, iclass 35, count 2 2006.173.02:17:50.71#ibcon#flushed, iclass 35, count 2 2006.173.02:17:50.71#ibcon#about to write, iclass 35, count 2 2006.173.02:17:50.71#ibcon#wrote, iclass 35, count 2 2006.173.02:17:50.71#ibcon#about to read 3, iclass 35, count 2 2006.173.02:17:50.74#ibcon#read 3, iclass 35, count 2 2006.173.02:17:50.74#ibcon#about to read 4, iclass 35, count 2 2006.173.02:17:50.74#ibcon#read 4, iclass 35, count 2 2006.173.02:17:50.74#ibcon#about to read 5, iclass 35, count 2 2006.173.02:17:50.74#ibcon#read 5, iclass 35, count 2 2006.173.02:17:50.74#ibcon#about to read 6, iclass 35, count 2 2006.173.02:17:50.74#ibcon#read 6, iclass 35, count 2 2006.173.02:17:50.74#ibcon#end of sib2, iclass 35, count 2 2006.173.02:17:50.74#ibcon#*after write, iclass 35, count 2 2006.173.02:17:50.74#ibcon#*before return 0, iclass 35, count 2 2006.173.02:17:50.74#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.02:17:50.74#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.02:17:50.74#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.02:17:50.74#ibcon#ireg 7 cls_cnt 0 2006.173.02:17:50.74#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.02:17:50.86#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.02:17:50.86#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.02:17:50.86#ibcon#enter wrdev, iclass 35, count 0 2006.173.02:17:50.86#ibcon#first serial, iclass 35, count 0 2006.173.02:17:50.86#ibcon#enter sib2, iclass 35, count 0 2006.173.02:17:50.86#ibcon#flushed, iclass 35, count 0 2006.173.02:17:50.86#ibcon#about to write, iclass 35, count 0 2006.173.02:17:50.86#ibcon#wrote, iclass 35, count 0 2006.173.02:17:50.86#ibcon#about to read 3, iclass 35, count 0 2006.173.02:17:50.88#ibcon#read 3, iclass 35, count 0 2006.173.02:17:50.88#ibcon#about to read 4, iclass 35, count 0 2006.173.02:17:50.88#ibcon#read 4, iclass 35, count 0 2006.173.02:17:50.88#ibcon#about to read 5, iclass 35, count 0 2006.173.02:17:50.88#ibcon#read 5, iclass 35, count 0 2006.173.02:17:50.88#ibcon#about to read 6, iclass 35, count 0 2006.173.02:17:50.88#ibcon#read 6, iclass 35, count 0 2006.173.02:17:50.88#ibcon#end of sib2, iclass 35, count 0 2006.173.02:17:50.88#ibcon#*mode == 0, iclass 35, count 0 2006.173.02:17:50.88#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.02:17:50.88#ibcon#[27=USB\r\n] 2006.173.02:17:50.88#ibcon#*before write, iclass 35, count 0 2006.173.02:17:50.88#ibcon#enter sib2, iclass 35, count 0 2006.173.02:17:50.88#ibcon#flushed, iclass 35, count 0 2006.173.02:17:50.88#ibcon#about to write, iclass 35, count 0 2006.173.02:17:50.88#ibcon#wrote, iclass 35, count 0 2006.173.02:17:50.88#ibcon#about to read 3, iclass 35, count 0 2006.173.02:17:50.91#ibcon#read 3, iclass 35, count 0 2006.173.02:17:50.91#ibcon#about to read 4, iclass 35, count 0 2006.173.02:17:50.91#ibcon#read 4, iclass 35, count 0 2006.173.02:17:50.91#ibcon#about to read 5, iclass 35, count 0 2006.173.02:17:50.91#ibcon#read 5, iclass 35, count 0 2006.173.02:17:50.91#ibcon#about to read 6, iclass 35, count 0 2006.173.02:17:50.91#ibcon#read 6, iclass 35, count 0 2006.173.02:17:50.91#ibcon#end of sib2, iclass 35, count 0 2006.173.02:17:50.91#ibcon#*after write, iclass 35, count 0 2006.173.02:17:50.91#ibcon#*before return 0, iclass 35, count 0 2006.173.02:17:50.91#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.02:17:50.91#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.02:17:50.91#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.02:17:50.91#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.02:17:50.91$vck44/vblo=6,719.99 2006.173.02:17:50.91#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.02:17:50.91#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.02:17:50.91#ibcon#ireg 17 cls_cnt 0 2006.173.02:17:50.91#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.02:17:50.91#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.02:17:50.91#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.02:17:50.91#ibcon#enter wrdev, iclass 37, count 0 2006.173.02:17:50.91#ibcon#first serial, iclass 37, count 0 2006.173.02:17:50.91#ibcon#enter sib2, iclass 37, count 0 2006.173.02:17:50.91#ibcon#flushed, iclass 37, count 0 2006.173.02:17:50.91#ibcon#about to write, iclass 37, count 0 2006.173.02:17:50.91#ibcon#wrote, iclass 37, count 0 2006.173.02:17:50.91#ibcon#about to read 3, iclass 37, count 0 2006.173.02:17:50.93#ibcon#read 3, iclass 37, count 0 2006.173.02:17:50.93#ibcon#about to read 4, iclass 37, count 0 2006.173.02:17:50.93#ibcon#read 4, iclass 37, count 0 2006.173.02:17:50.93#ibcon#about to read 5, iclass 37, count 0 2006.173.02:17:50.93#ibcon#read 5, iclass 37, count 0 2006.173.02:17:50.93#ibcon#about to read 6, iclass 37, count 0 2006.173.02:17:50.93#ibcon#read 6, iclass 37, count 0 2006.173.02:17:50.93#ibcon#end of sib2, iclass 37, count 0 2006.173.02:17:50.93#ibcon#*mode == 0, iclass 37, count 0 2006.173.02:17:50.93#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.02:17:50.93#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.02:17:50.93#ibcon#*before write, iclass 37, count 0 2006.173.02:17:50.93#ibcon#enter sib2, iclass 37, count 0 2006.173.02:17:50.93#ibcon#flushed, iclass 37, count 0 2006.173.02:17:50.93#ibcon#about to write, iclass 37, count 0 2006.173.02:17:50.93#ibcon#wrote, iclass 37, count 0 2006.173.02:17:50.93#ibcon#about to read 3, iclass 37, count 0 2006.173.02:17:50.97#ibcon#read 3, iclass 37, count 0 2006.173.02:17:50.97#ibcon#about to read 4, iclass 37, count 0 2006.173.02:17:50.97#ibcon#read 4, iclass 37, count 0 2006.173.02:17:50.97#ibcon#about to read 5, iclass 37, count 0 2006.173.02:17:50.97#ibcon#read 5, iclass 37, count 0 2006.173.02:17:50.97#ibcon#about to read 6, iclass 37, count 0 2006.173.02:17:50.97#ibcon#read 6, iclass 37, count 0 2006.173.02:17:50.97#ibcon#end of sib2, iclass 37, count 0 2006.173.02:17:50.97#ibcon#*after write, iclass 37, count 0 2006.173.02:17:50.97#ibcon#*before return 0, iclass 37, count 0 2006.173.02:17:50.97#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.02:17:50.97#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.02:17:50.97#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.02:17:50.97#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.02:17:50.97$vck44/vb=6,4 2006.173.02:17:50.97#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.02:17:50.97#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.02:17:50.97#ibcon#ireg 11 cls_cnt 2 2006.173.02:17:50.97#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.02:17:51.03#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.02:17:51.03#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.02:17:51.03#ibcon#enter wrdev, iclass 39, count 2 2006.173.02:17:51.03#ibcon#first serial, iclass 39, count 2 2006.173.02:17:51.03#ibcon#enter sib2, iclass 39, count 2 2006.173.02:17:51.03#ibcon#flushed, iclass 39, count 2 2006.173.02:17:51.03#ibcon#about to write, iclass 39, count 2 2006.173.02:17:51.03#ibcon#wrote, iclass 39, count 2 2006.173.02:17:51.03#ibcon#about to read 3, iclass 39, count 2 2006.173.02:17:51.05#ibcon#read 3, iclass 39, count 2 2006.173.02:17:51.05#ibcon#about to read 4, iclass 39, count 2 2006.173.02:17:51.05#ibcon#read 4, iclass 39, count 2 2006.173.02:17:51.05#ibcon#about to read 5, iclass 39, count 2 2006.173.02:17:51.05#ibcon#read 5, iclass 39, count 2 2006.173.02:17:51.05#ibcon#about to read 6, iclass 39, count 2 2006.173.02:17:51.05#ibcon#read 6, iclass 39, count 2 2006.173.02:17:51.05#ibcon#end of sib2, iclass 39, count 2 2006.173.02:17:51.05#ibcon#*mode == 0, iclass 39, count 2 2006.173.02:17:51.05#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.02:17:51.05#ibcon#[27=AT06-04\r\n] 2006.173.02:17:51.05#ibcon#*before write, iclass 39, count 2 2006.173.02:17:51.05#ibcon#enter sib2, iclass 39, count 2 2006.173.02:17:51.05#ibcon#flushed, iclass 39, count 2 2006.173.02:17:51.05#ibcon#about to write, iclass 39, count 2 2006.173.02:17:51.05#ibcon#wrote, iclass 39, count 2 2006.173.02:17:51.05#ibcon#about to read 3, iclass 39, count 2 2006.173.02:17:51.08#ibcon#read 3, iclass 39, count 2 2006.173.02:17:51.08#ibcon#about to read 4, iclass 39, count 2 2006.173.02:17:51.08#ibcon#read 4, iclass 39, count 2 2006.173.02:17:51.08#ibcon#about to read 5, iclass 39, count 2 2006.173.02:17:51.08#ibcon#read 5, iclass 39, count 2 2006.173.02:17:51.08#ibcon#about to read 6, iclass 39, count 2 2006.173.02:17:51.08#ibcon#read 6, iclass 39, count 2 2006.173.02:17:51.08#ibcon#end of sib2, iclass 39, count 2 2006.173.02:17:51.08#ibcon#*after write, iclass 39, count 2 2006.173.02:17:51.08#ibcon#*before return 0, iclass 39, count 2 2006.173.02:17:51.08#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.02:17:51.08#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.02:17:51.08#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.02:17:51.08#ibcon#ireg 7 cls_cnt 0 2006.173.02:17:51.08#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.02:17:51.20#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.02:17:51.20#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.02:17:51.20#ibcon#enter wrdev, iclass 39, count 0 2006.173.02:17:51.20#ibcon#first serial, iclass 39, count 0 2006.173.02:17:51.20#ibcon#enter sib2, iclass 39, count 0 2006.173.02:17:51.20#ibcon#flushed, iclass 39, count 0 2006.173.02:17:51.20#ibcon#about to write, iclass 39, count 0 2006.173.02:17:51.20#ibcon#wrote, iclass 39, count 0 2006.173.02:17:51.20#ibcon#about to read 3, iclass 39, count 0 2006.173.02:17:51.22#ibcon#read 3, iclass 39, count 0 2006.173.02:17:51.22#ibcon#about to read 4, iclass 39, count 0 2006.173.02:17:51.22#ibcon#read 4, iclass 39, count 0 2006.173.02:17:51.22#ibcon#about to read 5, iclass 39, count 0 2006.173.02:17:51.22#ibcon#read 5, iclass 39, count 0 2006.173.02:17:51.22#ibcon#about to read 6, iclass 39, count 0 2006.173.02:17:51.22#ibcon#read 6, iclass 39, count 0 2006.173.02:17:51.22#ibcon#end of sib2, iclass 39, count 0 2006.173.02:17:51.22#ibcon#*mode == 0, iclass 39, count 0 2006.173.02:17:51.22#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.02:17:51.22#ibcon#[27=USB\r\n] 2006.173.02:17:51.22#ibcon#*before write, iclass 39, count 0 2006.173.02:17:51.22#ibcon#enter sib2, iclass 39, count 0 2006.173.02:17:51.22#ibcon#flushed, iclass 39, count 0 2006.173.02:17:51.22#ibcon#about to write, iclass 39, count 0 2006.173.02:17:51.22#ibcon#wrote, iclass 39, count 0 2006.173.02:17:51.22#ibcon#about to read 3, iclass 39, count 0 2006.173.02:17:51.25#ibcon#read 3, iclass 39, count 0 2006.173.02:17:51.25#ibcon#about to read 4, iclass 39, count 0 2006.173.02:17:51.25#ibcon#read 4, iclass 39, count 0 2006.173.02:17:51.25#ibcon#about to read 5, iclass 39, count 0 2006.173.02:17:51.25#ibcon#read 5, iclass 39, count 0 2006.173.02:17:51.25#ibcon#about to read 6, iclass 39, count 0 2006.173.02:17:51.25#ibcon#read 6, iclass 39, count 0 2006.173.02:17:51.25#ibcon#end of sib2, iclass 39, count 0 2006.173.02:17:51.25#ibcon#*after write, iclass 39, count 0 2006.173.02:17:51.25#ibcon#*before return 0, iclass 39, count 0 2006.173.02:17:51.25#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.02:17:51.25#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.02:17:51.25#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.02:17:51.25#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.02:17:51.25$vck44/vblo=7,734.99 2006.173.02:17:51.25#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.02:17:51.25#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.02:17:51.25#ibcon#ireg 17 cls_cnt 0 2006.173.02:17:51.25#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.02:17:51.25#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.02:17:51.25#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.02:17:51.25#ibcon#enter wrdev, iclass 3, count 0 2006.173.02:17:51.25#ibcon#first serial, iclass 3, count 0 2006.173.02:17:51.25#ibcon#enter sib2, iclass 3, count 0 2006.173.02:17:51.25#ibcon#flushed, iclass 3, count 0 2006.173.02:17:51.25#ibcon#about to write, iclass 3, count 0 2006.173.02:17:51.25#ibcon#wrote, iclass 3, count 0 2006.173.02:17:51.25#ibcon#about to read 3, iclass 3, count 0 2006.173.02:17:51.27#ibcon#read 3, iclass 3, count 0 2006.173.02:17:51.27#ibcon#about to read 4, iclass 3, count 0 2006.173.02:17:51.27#ibcon#read 4, iclass 3, count 0 2006.173.02:17:51.27#ibcon#about to read 5, iclass 3, count 0 2006.173.02:17:51.27#ibcon#read 5, iclass 3, count 0 2006.173.02:17:51.27#ibcon#about to read 6, iclass 3, count 0 2006.173.02:17:51.27#ibcon#read 6, iclass 3, count 0 2006.173.02:17:51.27#ibcon#end of sib2, iclass 3, count 0 2006.173.02:17:51.27#ibcon#*mode == 0, iclass 3, count 0 2006.173.02:17:51.27#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.02:17:51.27#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.02:17:51.27#ibcon#*before write, iclass 3, count 0 2006.173.02:17:51.27#ibcon#enter sib2, iclass 3, count 0 2006.173.02:17:51.27#ibcon#flushed, iclass 3, count 0 2006.173.02:17:51.27#ibcon#about to write, iclass 3, count 0 2006.173.02:17:51.27#ibcon#wrote, iclass 3, count 0 2006.173.02:17:51.27#ibcon#about to read 3, iclass 3, count 0 2006.173.02:17:51.31#ibcon#read 3, iclass 3, count 0 2006.173.02:17:51.31#ibcon#about to read 4, iclass 3, count 0 2006.173.02:17:51.31#ibcon#read 4, iclass 3, count 0 2006.173.02:17:51.31#ibcon#about to read 5, iclass 3, count 0 2006.173.02:17:51.31#ibcon#read 5, iclass 3, count 0 2006.173.02:17:51.31#ibcon#about to read 6, iclass 3, count 0 2006.173.02:17:51.31#ibcon#read 6, iclass 3, count 0 2006.173.02:17:51.31#ibcon#end of sib2, iclass 3, count 0 2006.173.02:17:51.31#ibcon#*after write, iclass 3, count 0 2006.173.02:17:51.31#ibcon#*before return 0, iclass 3, count 0 2006.173.02:17:51.31#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.02:17:51.31#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.02:17:51.31#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.02:17:51.31#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.02:17:51.31$vck44/vb=7,4 2006.173.02:17:51.31#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.02:17:51.31#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.02:17:51.31#ibcon#ireg 11 cls_cnt 2 2006.173.02:17:51.31#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.02:17:51.37#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.02:17:51.37#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.02:17:51.37#ibcon#enter wrdev, iclass 5, count 2 2006.173.02:17:51.37#ibcon#first serial, iclass 5, count 2 2006.173.02:17:51.37#ibcon#enter sib2, iclass 5, count 2 2006.173.02:17:51.37#ibcon#flushed, iclass 5, count 2 2006.173.02:17:51.37#ibcon#about to write, iclass 5, count 2 2006.173.02:17:51.37#ibcon#wrote, iclass 5, count 2 2006.173.02:17:51.37#ibcon#about to read 3, iclass 5, count 2 2006.173.02:17:51.39#ibcon#read 3, iclass 5, count 2 2006.173.02:17:51.39#ibcon#about to read 4, iclass 5, count 2 2006.173.02:17:51.39#ibcon#read 4, iclass 5, count 2 2006.173.02:17:51.39#ibcon#about to read 5, iclass 5, count 2 2006.173.02:17:51.39#ibcon#read 5, iclass 5, count 2 2006.173.02:17:51.39#ibcon#about to read 6, iclass 5, count 2 2006.173.02:17:51.39#ibcon#read 6, iclass 5, count 2 2006.173.02:17:51.39#ibcon#end of sib2, iclass 5, count 2 2006.173.02:17:51.39#ibcon#*mode == 0, iclass 5, count 2 2006.173.02:17:51.39#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.02:17:51.39#ibcon#[27=AT07-04\r\n] 2006.173.02:17:51.39#ibcon#*before write, iclass 5, count 2 2006.173.02:17:51.39#ibcon#enter sib2, iclass 5, count 2 2006.173.02:17:51.39#ibcon#flushed, iclass 5, count 2 2006.173.02:17:51.39#ibcon#about to write, iclass 5, count 2 2006.173.02:17:51.39#ibcon#wrote, iclass 5, count 2 2006.173.02:17:51.39#ibcon#about to read 3, iclass 5, count 2 2006.173.02:17:51.42#ibcon#read 3, iclass 5, count 2 2006.173.02:17:51.42#ibcon#about to read 4, iclass 5, count 2 2006.173.02:17:51.42#ibcon#read 4, iclass 5, count 2 2006.173.02:17:51.42#ibcon#about to read 5, iclass 5, count 2 2006.173.02:17:51.42#ibcon#read 5, iclass 5, count 2 2006.173.02:17:51.42#ibcon#about to read 6, iclass 5, count 2 2006.173.02:17:51.42#ibcon#read 6, iclass 5, count 2 2006.173.02:17:51.42#ibcon#end of sib2, iclass 5, count 2 2006.173.02:17:51.42#ibcon#*after write, iclass 5, count 2 2006.173.02:17:51.42#ibcon#*before return 0, iclass 5, count 2 2006.173.02:17:51.42#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.02:17:51.42#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.02:17:51.42#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.02:17:51.42#ibcon#ireg 7 cls_cnt 0 2006.173.02:17:51.42#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.02:17:51.54#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.02:17:51.54#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.02:17:51.54#ibcon#enter wrdev, iclass 5, count 0 2006.173.02:17:51.54#ibcon#first serial, iclass 5, count 0 2006.173.02:17:51.54#ibcon#enter sib2, iclass 5, count 0 2006.173.02:17:51.54#ibcon#flushed, iclass 5, count 0 2006.173.02:17:51.54#ibcon#about to write, iclass 5, count 0 2006.173.02:17:51.54#ibcon#wrote, iclass 5, count 0 2006.173.02:17:51.54#ibcon#about to read 3, iclass 5, count 0 2006.173.02:17:51.56#ibcon#read 3, iclass 5, count 0 2006.173.02:17:51.56#ibcon#about to read 4, iclass 5, count 0 2006.173.02:17:51.56#ibcon#read 4, iclass 5, count 0 2006.173.02:17:51.56#ibcon#about to read 5, iclass 5, count 0 2006.173.02:17:51.56#ibcon#read 5, iclass 5, count 0 2006.173.02:17:51.56#ibcon#about to read 6, iclass 5, count 0 2006.173.02:17:51.56#ibcon#read 6, iclass 5, count 0 2006.173.02:17:51.56#ibcon#end of sib2, iclass 5, count 0 2006.173.02:17:51.56#ibcon#*mode == 0, iclass 5, count 0 2006.173.02:17:51.56#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.02:17:51.56#ibcon#[27=USB\r\n] 2006.173.02:17:51.56#ibcon#*before write, iclass 5, count 0 2006.173.02:17:51.56#ibcon#enter sib2, iclass 5, count 0 2006.173.02:17:51.56#ibcon#flushed, iclass 5, count 0 2006.173.02:17:51.56#ibcon#about to write, iclass 5, count 0 2006.173.02:17:51.56#ibcon#wrote, iclass 5, count 0 2006.173.02:17:51.56#ibcon#about to read 3, iclass 5, count 0 2006.173.02:17:51.59#ibcon#read 3, iclass 5, count 0 2006.173.02:17:51.59#ibcon#about to read 4, iclass 5, count 0 2006.173.02:17:51.59#ibcon#read 4, iclass 5, count 0 2006.173.02:17:51.59#ibcon#about to read 5, iclass 5, count 0 2006.173.02:17:51.59#ibcon#read 5, iclass 5, count 0 2006.173.02:17:51.59#ibcon#about to read 6, iclass 5, count 0 2006.173.02:17:51.59#ibcon#read 6, iclass 5, count 0 2006.173.02:17:51.59#ibcon#end of sib2, iclass 5, count 0 2006.173.02:17:51.59#ibcon#*after write, iclass 5, count 0 2006.173.02:17:51.59#ibcon#*before return 0, iclass 5, count 0 2006.173.02:17:51.59#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.02:17:51.59#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.02:17:51.59#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.02:17:51.59#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.02:17:51.59$vck44/vblo=8,744.99 2006.173.02:17:51.59#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.02:17:51.59#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.02:17:51.59#ibcon#ireg 17 cls_cnt 0 2006.173.02:17:51.59#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.02:17:51.59#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.02:17:51.59#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.02:17:51.59#ibcon#enter wrdev, iclass 7, count 0 2006.173.02:17:51.59#ibcon#first serial, iclass 7, count 0 2006.173.02:17:51.59#ibcon#enter sib2, iclass 7, count 0 2006.173.02:17:51.59#ibcon#flushed, iclass 7, count 0 2006.173.02:17:51.59#ibcon#about to write, iclass 7, count 0 2006.173.02:17:51.59#ibcon#wrote, iclass 7, count 0 2006.173.02:17:51.59#ibcon#about to read 3, iclass 7, count 0 2006.173.02:17:51.61#ibcon#read 3, iclass 7, count 0 2006.173.02:17:51.61#ibcon#about to read 4, iclass 7, count 0 2006.173.02:17:51.61#ibcon#read 4, iclass 7, count 0 2006.173.02:17:51.61#ibcon#about to read 5, iclass 7, count 0 2006.173.02:17:51.61#ibcon#read 5, iclass 7, count 0 2006.173.02:17:51.61#ibcon#about to read 6, iclass 7, count 0 2006.173.02:17:51.61#ibcon#read 6, iclass 7, count 0 2006.173.02:17:51.61#ibcon#end of sib2, iclass 7, count 0 2006.173.02:17:51.61#ibcon#*mode == 0, iclass 7, count 0 2006.173.02:17:51.61#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.02:17:51.61#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.02:17:51.61#ibcon#*before write, iclass 7, count 0 2006.173.02:17:51.61#ibcon#enter sib2, iclass 7, count 0 2006.173.02:17:51.61#ibcon#flushed, iclass 7, count 0 2006.173.02:17:51.61#ibcon#about to write, iclass 7, count 0 2006.173.02:17:51.61#ibcon#wrote, iclass 7, count 0 2006.173.02:17:51.61#ibcon#about to read 3, iclass 7, count 0 2006.173.02:17:51.65#ibcon#read 3, iclass 7, count 0 2006.173.02:17:51.65#ibcon#about to read 4, iclass 7, count 0 2006.173.02:17:51.65#ibcon#read 4, iclass 7, count 0 2006.173.02:17:51.65#ibcon#about to read 5, iclass 7, count 0 2006.173.02:17:51.65#ibcon#read 5, iclass 7, count 0 2006.173.02:17:51.65#ibcon#about to read 6, iclass 7, count 0 2006.173.02:17:51.65#ibcon#read 6, iclass 7, count 0 2006.173.02:17:51.65#ibcon#end of sib2, iclass 7, count 0 2006.173.02:17:51.65#ibcon#*after write, iclass 7, count 0 2006.173.02:17:51.65#ibcon#*before return 0, iclass 7, count 0 2006.173.02:17:51.65#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.02:17:51.65#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.02:17:51.65#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.02:17:51.65#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.02:17:51.65$vck44/vb=8,4 2006.173.02:17:51.65#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.02:17:51.65#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.02:17:51.65#ibcon#ireg 11 cls_cnt 2 2006.173.02:17:51.65#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.02:17:51.71#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.02:17:51.71#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.02:17:51.71#ibcon#enter wrdev, iclass 11, count 2 2006.173.02:17:51.71#ibcon#first serial, iclass 11, count 2 2006.173.02:17:51.71#ibcon#enter sib2, iclass 11, count 2 2006.173.02:17:51.71#ibcon#flushed, iclass 11, count 2 2006.173.02:17:51.71#ibcon#about to write, iclass 11, count 2 2006.173.02:17:51.71#ibcon#wrote, iclass 11, count 2 2006.173.02:17:51.71#ibcon#about to read 3, iclass 11, count 2 2006.173.02:17:51.73#ibcon#read 3, iclass 11, count 2 2006.173.02:17:51.73#ibcon#about to read 4, iclass 11, count 2 2006.173.02:17:51.73#ibcon#read 4, iclass 11, count 2 2006.173.02:17:51.73#ibcon#about to read 5, iclass 11, count 2 2006.173.02:17:51.73#ibcon#read 5, iclass 11, count 2 2006.173.02:17:51.73#ibcon#about to read 6, iclass 11, count 2 2006.173.02:17:51.73#ibcon#read 6, iclass 11, count 2 2006.173.02:17:51.73#ibcon#end of sib2, iclass 11, count 2 2006.173.02:17:51.73#ibcon#*mode == 0, iclass 11, count 2 2006.173.02:17:51.73#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.02:17:51.73#ibcon#[27=AT08-04\r\n] 2006.173.02:17:51.73#ibcon#*before write, iclass 11, count 2 2006.173.02:17:51.73#ibcon#enter sib2, iclass 11, count 2 2006.173.02:17:51.73#ibcon#flushed, iclass 11, count 2 2006.173.02:17:51.73#ibcon#about to write, iclass 11, count 2 2006.173.02:17:51.73#ibcon#wrote, iclass 11, count 2 2006.173.02:17:51.73#ibcon#about to read 3, iclass 11, count 2 2006.173.02:17:51.76#ibcon#read 3, iclass 11, count 2 2006.173.02:17:51.76#ibcon#about to read 4, iclass 11, count 2 2006.173.02:17:51.76#ibcon#read 4, iclass 11, count 2 2006.173.02:17:51.76#ibcon#about to read 5, iclass 11, count 2 2006.173.02:17:51.76#ibcon#read 5, iclass 11, count 2 2006.173.02:17:51.76#ibcon#about to read 6, iclass 11, count 2 2006.173.02:17:51.76#ibcon#read 6, iclass 11, count 2 2006.173.02:17:51.76#ibcon#end of sib2, iclass 11, count 2 2006.173.02:17:51.76#ibcon#*after write, iclass 11, count 2 2006.173.02:17:51.76#ibcon#*before return 0, iclass 11, count 2 2006.173.02:17:51.76#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.02:17:51.76#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.02:17:51.76#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.02:17:51.76#ibcon#ireg 7 cls_cnt 0 2006.173.02:17:51.76#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.02:17:51.88#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.02:17:51.88#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.02:17:51.88#ibcon#enter wrdev, iclass 11, count 0 2006.173.02:17:51.88#ibcon#first serial, iclass 11, count 0 2006.173.02:17:51.88#ibcon#enter sib2, iclass 11, count 0 2006.173.02:17:51.88#ibcon#flushed, iclass 11, count 0 2006.173.02:17:51.88#ibcon#about to write, iclass 11, count 0 2006.173.02:17:51.88#ibcon#wrote, iclass 11, count 0 2006.173.02:17:51.88#ibcon#about to read 3, iclass 11, count 0 2006.173.02:17:51.90#ibcon#read 3, iclass 11, count 0 2006.173.02:17:51.90#ibcon#about to read 4, iclass 11, count 0 2006.173.02:17:51.90#ibcon#read 4, iclass 11, count 0 2006.173.02:17:51.90#ibcon#about to read 5, iclass 11, count 0 2006.173.02:17:51.90#ibcon#read 5, iclass 11, count 0 2006.173.02:17:51.90#ibcon#about to read 6, iclass 11, count 0 2006.173.02:17:51.90#ibcon#read 6, iclass 11, count 0 2006.173.02:17:51.90#ibcon#end of sib2, iclass 11, count 0 2006.173.02:17:51.90#ibcon#*mode == 0, iclass 11, count 0 2006.173.02:17:51.90#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.02:17:51.90#ibcon#[27=USB\r\n] 2006.173.02:17:51.90#ibcon#*before write, iclass 11, count 0 2006.173.02:17:51.90#ibcon#enter sib2, iclass 11, count 0 2006.173.02:17:51.90#ibcon#flushed, iclass 11, count 0 2006.173.02:17:51.90#ibcon#about to write, iclass 11, count 0 2006.173.02:17:51.90#ibcon#wrote, iclass 11, count 0 2006.173.02:17:51.90#ibcon#about to read 3, iclass 11, count 0 2006.173.02:17:51.93#ibcon#read 3, iclass 11, count 0 2006.173.02:17:51.93#ibcon#about to read 4, iclass 11, count 0 2006.173.02:17:51.93#ibcon#read 4, iclass 11, count 0 2006.173.02:17:51.93#ibcon#about to read 5, iclass 11, count 0 2006.173.02:17:51.93#ibcon#read 5, iclass 11, count 0 2006.173.02:17:51.93#ibcon#about to read 6, iclass 11, count 0 2006.173.02:17:51.93#ibcon#read 6, iclass 11, count 0 2006.173.02:17:51.93#ibcon#end of sib2, iclass 11, count 0 2006.173.02:17:51.93#ibcon#*after write, iclass 11, count 0 2006.173.02:17:51.93#ibcon#*before return 0, iclass 11, count 0 2006.173.02:17:51.93#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.02:17:51.93#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.02:17:51.93#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.02:17:51.93#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.02:17:51.93$vck44/vabw=wide 2006.173.02:17:51.93#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.02:17:51.93#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.02:17:51.93#ibcon#ireg 8 cls_cnt 0 2006.173.02:17:51.93#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.02:17:51.93#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.02:17:51.93#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.02:17:51.93#ibcon#enter wrdev, iclass 13, count 0 2006.173.02:17:51.93#ibcon#first serial, iclass 13, count 0 2006.173.02:17:51.93#ibcon#enter sib2, iclass 13, count 0 2006.173.02:17:51.93#ibcon#flushed, iclass 13, count 0 2006.173.02:17:51.93#ibcon#about to write, iclass 13, count 0 2006.173.02:17:51.93#ibcon#wrote, iclass 13, count 0 2006.173.02:17:51.93#ibcon#about to read 3, iclass 13, count 0 2006.173.02:17:51.95#ibcon#read 3, iclass 13, count 0 2006.173.02:17:51.95#ibcon#about to read 4, iclass 13, count 0 2006.173.02:17:51.95#ibcon#read 4, iclass 13, count 0 2006.173.02:17:51.95#ibcon#about to read 5, iclass 13, count 0 2006.173.02:17:51.95#ibcon#read 5, iclass 13, count 0 2006.173.02:17:51.95#ibcon#about to read 6, iclass 13, count 0 2006.173.02:17:51.95#ibcon#read 6, iclass 13, count 0 2006.173.02:17:51.95#ibcon#end of sib2, iclass 13, count 0 2006.173.02:17:51.95#ibcon#*mode == 0, iclass 13, count 0 2006.173.02:17:51.95#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.02:17:51.95#ibcon#[25=BW32\r\n] 2006.173.02:17:51.95#ibcon#*before write, iclass 13, count 0 2006.173.02:17:51.95#ibcon#enter sib2, iclass 13, count 0 2006.173.02:17:51.95#ibcon#flushed, iclass 13, count 0 2006.173.02:17:51.95#ibcon#about to write, iclass 13, count 0 2006.173.02:17:51.95#ibcon#wrote, iclass 13, count 0 2006.173.02:17:51.95#ibcon#about to read 3, iclass 13, count 0 2006.173.02:17:51.98#ibcon#read 3, iclass 13, count 0 2006.173.02:17:51.98#ibcon#about to read 4, iclass 13, count 0 2006.173.02:17:51.98#ibcon#read 4, iclass 13, count 0 2006.173.02:17:51.98#ibcon#about to read 5, iclass 13, count 0 2006.173.02:17:51.98#ibcon#read 5, iclass 13, count 0 2006.173.02:17:51.98#ibcon#about to read 6, iclass 13, count 0 2006.173.02:17:51.98#ibcon#read 6, iclass 13, count 0 2006.173.02:17:51.98#ibcon#end of sib2, iclass 13, count 0 2006.173.02:17:51.98#ibcon#*after write, iclass 13, count 0 2006.173.02:17:51.98#ibcon#*before return 0, iclass 13, count 0 2006.173.02:17:51.98#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.02:17:51.98#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.02:17:51.98#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.02:17:51.98#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.02:17:51.98$vck44/vbbw=wide 2006.173.02:17:51.98#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.02:17:51.98#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.02:17:51.98#ibcon#ireg 8 cls_cnt 0 2006.173.02:17:51.98#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.02:17:52.05#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.02:17:52.05#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.02:17:52.05#ibcon#enter wrdev, iclass 15, count 0 2006.173.02:17:52.05#ibcon#first serial, iclass 15, count 0 2006.173.02:17:52.05#ibcon#enter sib2, iclass 15, count 0 2006.173.02:17:52.05#ibcon#flushed, iclass 15, count 0 2006.173.02:17:52.05#ibcon#about to write, iclass 15, count 0 2006.173.02:17:52.05#ibcon#wrote, iclass 15, count 0 2006.173.02:17:52.05#ibcon#about to read 3, iclass 15, count 0 2006.173.02:17:52.07#ibcon#read 3, iclass 15, count 0 2006.173.02:17:52.07#ibcon#about to read 4, iclass 15, count 0 2006.173.02:17:52.07#ibcon#read 4, iclass 15, count 0 2006.173.02:17:52.07#ibcon#about to read 5, iclass 15, count 0 2006.173.02:17:52.07#ibcon#read 5, iclass 15, count 0 2006.173.02:17:52.07#ibcon#about to read 6, iclass 15, count 0 2006.173.02:17:52.07#ibcon#read 6, iclass 15, count 0 2006.173.02:17:52.07#ibcon#end of sib2, iclass 15, count 0 2006.173.02:17:52.07#ibcon#*mode == 0, iclass 15, count 0 2006.173.02:17:52.07#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.02:17:52.07#ibcon#[27=BW32\r\n] 2006.173.02:17:52.07#ibcon#*before write, iclass 15, count 0 2006.173.02:17:52.07#ibcon#enter sib2, iclass 15, count 0 2006.173.02:17:52.07#ibcon#flushed, iclass 15, count 0 2006.173.02:17:52.07#ibcon#about to write, iclass 15, count 0 2006.173.02:17:52.07#ibcon#wrote, iclass 15, count 0 2006.173.02:17:52.07#ibcon#about to read 3, iclass 15, count 0 2006.173.02:17:52.10#ibcon#read 3, iclass 15, count 0 2006.173.02:17:52.10#ibcon#about to read 4, iclass 15, count 0 2006.173.02:17:52.10#ibcon#read 4, iclass 15, count 0 2006.173.02:17:52.10#ibcon#about to read 5, iclass 15, count 0 2006.173.02:17:52.10#ibcon#read 5, iclass 15, count 0 2006.173.02:17:52.10#ibcon#about to read 6, iclass 15, count 0 2006.173.02:17:52.10#ibcon#read 6, iclass 15, count 0 2006.173.02:17:52.10#ibcon#end of sib2, iclass 15, count 0 2006.173.02:17:52.10#ibcon#*after write, iclass 15, count 0 2006.173.02:17:52.10#ibcon#*before return 0, iclass 15, count 0 2006.173.02:17:52.10#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.02:17:52.10#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.02:17:52.10#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.02:17:52.10#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.02:17:52.10$setupk4/ifdk4 2006.173.02:17:52.10$ifdk4/lo= 2006.173.02:17:52.10$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.02:17:52.10$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.02:17:52.10$ifdk4/patch= 2006.173.02:17:52.10$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.02:17:52.10$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.02:17:52.10$setupk4/!*+20s 2006.173.02:17:56.70#abcon#<5=/14 1.1 2.2 22.66 831006.5\r\n> 2006.173.02:17:56.72#abcon#{5=INTERFACE CLEAR} 2006.173.02:17:56.78#abcon#[5=S1D000X0/0*\r\n] 2006.173.02:18:06.13#trakl#Source acquired 2006.173.02:18:06.60$setupk4/"tpicd 2006.173.02:18:06.60$setupk4/echo=off 2006.173.02:18:06.60$setupk4/xlog=off 2006.173.02:18:06.60:!2006.173.02:19:41 2006.173.02:18:07.13#flagr#flagr/antenna,acquired 2006.173.02:19:41.00:preob 2006.173.02:19:41.14/onsource/TRACKING 2006.173.02:19:41.14:!2006.173.02:19:51 2006.173.02:19:51.00:"tape 2006.173.02:19:51.00:"st=record 2006.173.02:19:51.00:data_valid=on 2006.173.02:19:51.00:midob 2006.173.02:19:52.14/onsource/TRACKING 2006.173.02:19:52.14/wx/22.68,1006.5,82 2006.173.02:19:52.24/cable/+6.5132E-03 2006.173.02:19:53.33/va/01,07,usb,yes,36,38 2006.173.02:19:53.33/va/02,06,usb,yes,35,36 2006.173.02:19:53.33/va/03,05,usb,yes,45,47 2006.173.02:19:53.33/va/04,06,usb,yes,36,38 2006.173.02:19:53.33/va/05,04,usb,yes,28,29 2006.173.02:19:53.33/va/06,03,usb,yes,40,40 2006.173.02:19:53.33/va/07,04,usb,yes,32,34 2006.173.02:19:53.33/va/08,04,usb,yes,27,33 2006.173.02:19:53.56/valo/01,524.99,yes,locked 2006.173.02:19:53.56/valo/02,534.99,yes,locked 2006.173.02:19:53.56/valo/03,564.99,yes,locked 2006.173.02:19:53.56/valo/04,624.99,yes,locked 2006.173.02:19:53.56/valo/05,734.99,yes,locked 2006.173.02:19:53.56/valo/06,814.99,yes,locked 2006.173.02:19:53.56/valo/07,864.99,yes,locked 2006.173.02:19:53.56/valo/08,884.99,yes,locked 2006.173.02:19:54.65/vb/01,04,usb,yes,29,27 2006.173.02:19:54.65/vb/02,04,usb,yes,32,31 2006.173.02:19:54.65/vb/03,04,usb,yes,29,31 2006.173.02:19:54.65/vb/04,04,usb,yes,33,32 2006.173.02:19:54.65/vb/05,04,usb,yes,25,28 2006.173.02:19:54.65/vb/06,04,usb,yes,30,26 2006.173.02:19:54.65/vb/07,04,usb,yes,30,30 2006.173.02:19:54.65/vb/08,04,usb,yes,27,31 2006.173.02:19:54.88/vblo/01,629.99,yes,locked 2006.173.02:19:54.88/vblo/02,634.99,yes,locked 2006.173.02:19:54.88/vblo/03,649.99,yes,locked 2006.173.02:19:54.88/vblo/04,679.99,yes,locked 2006.173.02:19:54.88/vblo/05,709.99,yes,locked 2006.173.02:19:54.88/vblo/06,719.99,yes,locked 2006.173.02:19:54.88/vblo/07,734.99,yes,locked 2006.173.02:19:54.88/vblo/08,744.99,yes,locked 2006.173.02:19:55.03/vabw/8 2006.173.02:19:55.18/vbbw/8 2006.173.02:19:55.34/xfe/off,on,15.0 2006.173.02:19:55.72/ifatt/23,28,28,28 2006.173.02:19:56.07/fmout-gps/S +3.91E-07 2006.173.02:19:56.11:!2006.173.02:23:31 2006.173.02:23:31.01:data_valid=off 2006.173.02:23:31.02:"et 2006.173.02:23:31.02:!+3s 2006.173.02:23:34.03:"tape 2006.173.02:23:34.03:postob 2006.173.02:23:34.16/cable/+6.5088E-03 2006.173.02:23:34.16/wx/22.60,1006.5,77 2006.173.02:23:34.22/fmout-gps/S +3.91E-07 2006.173.02:23:34.22:scan_name=173-0227,jd0606,190 2006.173.02:23:34.23:source=0642+449,064632.03,445116.6,2000.0,cw 2006.173.02:23:36.14#flagr#flagr/antenna,new-source 2006.173.02:23:36.14:checkk5 2006.173.02:23:36.59/chk_autoobs//k5ts1/ autoobs is running! 2006.173.02:23:37.09/chk_autoobs//k5ts2/ autoobs is running! 2006.173.02:23:37.47/chk_autoobs//k5ts3/ autoobs is running! 2006.173.02:23:38.13/chk_autoobs//k5ts4/ autoobs is running! 2006.173.02:23:38.54/chk_obsdata//k5ts1/T1730219??a.dat file size is correct (nominal:880MB, actual:876MB). 2006.173.02:23:39.18/chk_obsdata//k5ts2/T1730219??b.dat file size is correct (nominal:880MB, actual:876MB). 2006.173.02:23:39.63/chk_obsdata//k5ts3/T1730219??c.dat file size is correct (nominal:880MB, actual:876MB). 2006.173.02:23:40.06/chk_obsdata//k5ts4/T1730219??d.dat file size is correct (nominal:880MB, actual:876MB). 2006.173.02:23:40.82/k5log//k5ts1_log_newline 2006.173.02:23:41.65/k5log//k5ts2_log_newline 2006.173.02:23:42.78/k5log//k5ts3_log_newline 2006.173.02:23:43.59/k5log//k5ts4_log_newline 2006.173.02:23:43.62/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.02:23:43.62:setupk4=1 2006.173.02:23:43.62$setupk4/echo=on 2006.173.02:23:43.62$setupk4/pcalon 2006.173.02:23:43.62$pcalon/"no phase cal control is implemented here 2006.173.02:23:43.62$setupk4/"tpicd=stop 2006.173.02:23:43.62$setupk4/"rec=synch_on 2006.173.02:23:43.62$setupk4/"rec_mode=128 2006.173.02:23:43.62$setupk4/!* 2006.173.02:23:43.62$setupk4/recpk4 2006.173.02:23:43.62$recpk4/recpatch= 2006.173.02:23:43.62$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.02:23:43.62$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.02:23:43.62$setupk4/vck44 2006.173.02:23:43.62$vck44/valo=1,524.99 2006.173.02:23:43.62#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.02:23:43.62#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.02:23:43.62#ibcon#ireg 17 cls_cnt 0 2006.173.02:23:43.62#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.02:23:43.62#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.02:23:43.62#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.02:23:43.62#ibcon#enter wrdev, iclass 16, count 0 2006.173.02:23:43.62#ibcon#first serial, iclass 16, count 0 2006.173.02:23:43.62#ibcon#enter sib2, iclass 16, count 0 2006.173.02:23:43.62#ibcon#flushed, iclass 16, count 0 2006.173.02:23:43.62#ibcon#about to write, iclass 16, count 0 2006.173.02:23:43.62#ibcon#wrote, iclass 16, count 0 2006.173.02:23:43.62#ibcon#about to read 3, iclass 16, count 0 2006.173.02:23:43.67#ibcon#read 3, iclass 16, count 0 2006.173.02:23:43.67#ibcon#about to read 4, iclass 16, count 0 2006.173.02:23:43.67#ibcon#read 4, iclass 16, count 0 2006.173.02:23:43.67#ibcon#about to read 5, iclass 16, count 0 2006.173.02:23:43.67#ibcon#read 5, iclass 16, count 0 2006.173.02:23:43.67#ibcon#about to read 6, iclass 16, count 0 2006.173.02:23:43.67#ibcon#read 6, iclass 16, count 0 2006.173.02:23:43.67#ibcon#end of sib2, iclass 16, count 0 2006.173.02:23:43.67#ibcon#*mode == 0, iclass 16, count 0 2006.173.02:23:43.67#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.02:23:43.67#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.02:23:43.67#ibcon#*before write, iclass 16, count 0 2006.173.02:23:43.67#ibcon#enter sib2, iclass 16, count 0 2006.173.02:23:43.67#ibcon#flushed, iclass 16, count 0 2006.173.02:23:43.67#ibcon#about to write, iclass 16, count 0 2006.173.02:23:43.67#ibcon#wrote, iclass 16, count 0 2006.173.02:23:43.67#ibcon#about to read 3, iclass 16, count 0 2006.173.02:23:43.71#ibcon#read 3, iclass 16, count 0 2006.173.02:23:43.71#ibcon#about to read 4, iclass 16, count 0 2006.173.02:23:43.71#ibcon#read 4, iclass 16, count 0 2006.173.02:23:43.71#ibcon#about to read 5, iclass 16, count 0 2006.173.02:23:43.71#ibcon#read 5, iclass 16, count 0 2006.173.02:23:43.71#ibcon#about to read 6, iclass 16, count 0 2006.173.02:23:43.71#ibcon#read 6, iclass 16, count 0 2006.173.02:23:43.71#ibcon#end of sib2, iclass 16, count 0 2006.173.02:23:43.71#ibcon#*after write, iclass 16, count 0 2006.173.02:23:43.71#ibcon#*before return 0, iclass 16, count 0 2006.173.02:23:43.71#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.02:23:43.71#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.02:23:43.71#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.02:23:43.71#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.02:23:43.71$vck44/va=1,7 2006.173.02:23:43.71#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.02:23:43.71#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.02:23:43.71#ibcon#ireg 11 cls_cnt 2 2006.173.02:23:43.71#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.02:23:43.71#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.02:23:43.71#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.02:23:43.71#ibcon#enter wrdev, iclass 18, count 2 2006.173.02:23:43.71#ibcon#first serial, iclass 18, count 2 2006.173.02:23:43.71#ibcon#enter sib2, iclass 18, count 2 2006.173.02:23:43.71#ibcon#flushed, iclass 18, count 2 2006.173.02:23:43.71#ibcon#about to write, iclass 18, count 2 2006.173.02:23:43.71#ibcon#wrote, iclass 18, count 2 2006.173.02:23:43.71#ibcon#about to read 3, iclass 18, count 2 2006.173.02:23:43.73#ibcon#read 3, iclass 18, count 2 2006.173.02:23:43.73#ibcon#about to read 4, iclass 18, count 2 2006.173.02:23:43.73#ibcon#read 4, iclass 18, count 2 2006.173.02:23:43.73#ibcon#about to read 5, iclass 18, count 2 2006.173.02:23:43.73#ibcon#read 5, iclass 18, count 2 2006.173.02:23:43.73#ibcon#about to read 6, iclass 18, count 2 2006.173.02:23:43.73#ibcon#read 6, iclass 18, count 2 2006.173.02:23:43.73#ibcon#end of sib2, iclass 18, count 2 2006.173.02:23:43.73#ibcon#*mode == 0, iclass 18, count 2 2006.173.02:23:43.73#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.02:23:43.73#ibcon#[25=AT01-07\r\n] 2006.173.02:23:43.73#ibcon#*before write, iclass 18, count 2 2006.173.02:23:43.73#ibcon#enter sib2, iclass 18, count 2 2006.173.02:23:43.73#ibcon#flushed, iclass 18, count 2 2006.173.02:23:43.73#ibcon#about to write, iclass 18, count 2 2006.173.02:23:43.73#ibcon#wrote, iclass 18, count 2 2006.173.02:23:43.73#ibcon#about to read 3, iclass 18, count 2 2006.173.02:23:43.76#ibcon#read 3, iclass 18, count 2 2006.173.02:23:43.76#ibcon#about to read 4, iclass 18, count 2 2006.173.02:23:43.76#ibcon#read 4, iclass 18, count 2 2006.173.02:23:43.76#ibcon#about to read 5, iclass 18, count 2 2006.173.02:23:43.76#ibcon#read 5, iclass 18, count 2 2006.173.02:23:43.76#ibcon#about to read 6, iclass 18, count 2 2006.173.02:23:43.76#ibcon#read 6, iclass 18, count 2 2006.173.02:23:43.76#ibcon#end of sib2, iclass 18, count 2 2006.173.02:23:43.76#ibcon#*after write, iclass 18, count 2 2006.173.02:23:43.76#ibcon#*before return 0, iclass 18, count 2 2006.173.02:23:43.76#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.02:23:43.76#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.02:23:43.76#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.02:23:43.76#ibcon#ireg 7 cls_cnt 0 2006.173.02:23:43.76#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.02:23:43.88#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.02:23:43.88#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.02:23:43.88#ibcon#enter wrdev, iclass 18, count 0 2006.173.02:23:43.88#ibcon#first serial, iclass 18, count 0 2006.173.02:23:43.88#ibcon#enter sib2, iclass 18, count 0 2006.173.02:23:43.88#ibcon#flushed, iclass 18, count 0 2006.173.02:23:43.88#ibcon#about to write, iclass 18, count 0 2006.173.02:23:43.88#ibcon#wrote, iclass 18, count 0 2006.173.02:23:43.88#ibcon#about to read 3, iclass 18, count 0 2006.173.02:23:43.90#ibcon#read 3, iclass 18, count 0 2006.173.02:23:43.90#ibcon#about to read 4, iclass 18, count 0 2006.173.02:23:43.90#ibcon#read 4, iclass 18, count 0 2006.173.02:23:43.90#ibcon#about to read 5, iclass 18, count 0 2006.173.02:23:43.90#ibcon#read 5, iclass 18, count 0 2006.173.02:23:43.90#ibcon#about to read 6, iclass 18, count 0 2006.173.02:23:43.90#ibcon#read 6, iclass 18, count 0 2006.173.02:23:43.90#ibcon#end of sib2, iclass 18, count 0 2006.173.02:23:43.90#ibcon#*mode == 0, iclass 18, count 0 2006.173.02:23:43.90#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.02:23:43.90#ibcon#[25=USB\r\n] 2006.173.02:23:43.90#ibcon#*before write, iclass 18, count 0 2006.173.02:23:43.90#ibcon#enter sib2, iclass 18, count 0 2006.173.02:23:43.90#ibcon#flushed, iclass 18, count 0 2006.173.02:23:43.90#ibcon#about to write, iclass 18, count 0 2006.173.02:23:43.90#ibcon#wrote, iclass 18, count 0 2006.173.02:23:43.90#ibcon#about to read 3, iclass 18, count 0 2006.173.02:23:43.93#ibcon#read 3, iclass 18, count 0 2006.173.02:23:43.93#ibcon#about to read 4, iclass 18, count 0 2006.173.02:23:43.93#ibcon#read 4, iclass 18, count 0 2006.173.02:23:43.93#ibcon#about to read 5, iclass 18, count 0 2006.173.02:23:43.93#ibcon#read 5, iclass 18, count 0 2006.173.02:23:43.93#ibcon#about to read 6, iclass 18, count 0 2006.173.02:23:43.93#ibcon#read 6, iclass 18, count 0 2006.173.02:23:43.93#ibcon#end of sib2, iclass 18, count 0 2006.173.02:23:43.93#ibcon#*after write, iclass 18, count 0 2006.173.02:23:43.93#ibcon#*before return 0, iclass 18, count 0 2006.173.02:23:43.93#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.02:23:43.93#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.02:23:43.93#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.02:23:43.93#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.02:23:43.93$vck44/valo=2,534.99 2006.173.02:23:43.93#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.02:23:43.93#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.02:23:43.93#ibcon#ireg 17 cls_cnt 0 2006.173.02:23:43.93#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.02:23:43.93#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.02:23:43.93#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.02:23:43.93#ibcon#enter wrdev, iclass 20, count 0 2006.173.02:23:43.93#ibcon#first serial, iclass 20, count 0 2006.173.02:23:43.93#ibcon#enter sib2, iclass 20, count 0 2006.173.02:23:43.93#ibcon#flushed, iclass 20, count 0 2006.173.02:23:43.93#ibcon#about to write, iclass 20, count 0 2006.173.02:23:43.93#ibcon#wrote, iclass 20, count 0 2006.173.02:23:43.93#ibcon#about to read 3, iclass 20, count 0 2006.173.02:23:43.95#ibcon#read 3, iclass 20, count 0 2006.173.02:23:43.95#ibcon#about to read 4, iclass 20, count 0 2006.173.02:23:43.95#ibcon#read 4, iclass 20, count 0 2006.173.02:23:43.95#ibcon#about to read 5, iclass 20, count 0 2006.173.02:23:43.95#ibcon#read 5, iclass 20, count 0 2006.173.02:23:43.95#ibcon#about to read 6, iclass 20, count 0 2006.173.02:23:43.95#ibcon#read 6, iclass 20, count 0 2006.173.02:23:43.95#ibcon#end of sib2, iclass 20, count 0 2006.173.02:23:43.95#ibcon#*mode == 0, iclass 20, count 0 2006.173.02:23:43.95#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.02:23:43.95#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.02:23:43.95#ibcon#*before write, iclass 20, count 0 2006.173.02:23:43.95#ibcon#enter sib2, iclass 20, count 0 2006.173.02:23:43.95#ibcon#flushed, iclass 20, count 0 2006.173.02:23:43.95#ibcon#about to write, iclass 20, count 0 2006.173.02:23:43.95#ibcon#wrote, iclass 20, count 0 2006.173.02:23:43.95#ibcon#about to read 3, iclass 20, count 0 2006.173.02:23:43.99#ibcon#read 3, iclass 20, count 0 2006.173.02:23:43.99#ibcon#about to read 4, iclass 20, count 0 2006.173.02:23:43.99#ibcon#read 4, iclass 20, count 0 2006.173.02:23:43.99#ibcon#about to read 5, iclass 20, count 0 2006.173.02:23:43.99#ibcon#read 5, iclass 20, count 0 2006.173.02:23:43.99#ibcon#about to read 6, iclass 20, count 0 2006.173.02:23:43.99#ibcon#read 6, iclass 20, count 0 2006.173.02:23:43.99#ibcon#end of sib2, iclass 20, count 0 2006.173.02:23:43.99#ibcon#*after write, iclass 20, count 0 2006.173.02:23:43.99#ibcon#*before return 0, iclass 20, count 0 2006.173.02:23:43.99#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.02:23:43.99#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.02:23:43.99#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.02:23:43.99#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.02:23:43.99$vck44/va=2,6 2006.173.02:23:43.99#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.02:23:43.99#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.02:23:43.99#ibcon#ireg 11 cls_cnt 2 2006.173.02:23:43.99#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.02:23:44.06#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.02:23:44.06#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.02:23:44.06#ibcon#enter wrdev, iclass 22, count 2 2006.173.02:23:44.06#ibcon#first serial, iclass 22, count 2 2006.173.02:23:44.06#ibcon#enter sib2, iclass 22, count 2 2006.173.02:23:44.06#ibcon#flushed, iclass 22, count 2 2006.173.02:23:44.06#ibcon#about to write, iclass 22, count 2 2006.173.02:23:44.06#ibcon#wrote, iclass 22, count 2 2006.173.02:23:44.06#ibcon#about to read 3, iclass 22, count 2 2006.173.02:23:44.07#ibcon#read 3, iclass 22, count 2 2006.173.02:23:44.07#ibcon#about to read 4, iclass 22, count 2 2006.173.02:23:44.07#ibcon#read 4, iclass 22, count 2 2006.173.02:23:44.07#ibcon#about to read 5, iclass 22, count 2 2006.173.02:23:44.07#ibcon#read 5, iclass 22, count 2 2006.173.02:23:44.07#ibcon#about to read 6, iclass 22, count 2 2006.173.02:23:44.07#ibcon#read 6, iclass 22, count 2 2006.173.02:23:44.07#ibcon#end of sib2, iclass 22, count 2 2006.173.02:23:44.07#ibcon#*mode == 0, iclass 22, count 2 2006.173.02:23:44.07#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.02:23:44.07#ibcon#[25=AT02-06\r\n] 2006.173.02:23:44.07#ibcon#*before write, iclass 22, count 2 2006.173.02:23:44.07#ibcon#enter sib2, iclass 22, count 2 2006.173.02:23:44.07#ibcon#flushed, iclass 22, count 2 2006.173.02:23:44.07#ibcon#about to write, iclass 22, count 2 2006.173.02:23:44.07#ibcon#wrote, iclass 22, count 2 2006.173.02:23:44.07#ibcon#about to read 3, iclass 22, count 2 2006.173.02:23:44.10#ibcon#read 3, iclass 22, count 2 2006.173.02:23:44.10#ibcon#about to read 4, iclass 22, count 2 2006.173.02:23:44.10#ibcon#read 4, iclass 22, count 2 2006.173.02:23:44.10#ibcon#about to read 5, iclass 22, count 2 2006.173.02:23:44.10#ibcon#read 5, iclass 22, count 2 2006.173.02:23:44.10#ibcon#about to read 6, iclass 22, count 2 2006.173.02:23:44.10#ibcon#read 6, iclass 22, count 2 2006.173.02:23:44.10#ibcon#end of sib2, iclass 22, count 2 2006.173.02:23:44.10#ibcon#*after write, iclass 22, count 2 2006.173.02:23:44.10#ibcon#*before return 0, iclass 22, count 2 2006.173.02:23:44.10#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.02:23:44.10#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.02:23:44.10#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.02:23:44.10#ibcon#ireg 7 cls_cnt 0 2006.173.02:23:44.10#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.02:23:44.22#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.02:23:44.22#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.02:23:44.22#ibcon#enter wrdev, iclass 22, count 0 2006.173.02:23:44.22#ibcon#first serial, iclass 22, count 0 2006.173.02:23:44.22#ibcon#enter sib2, iclass 22, count 0 2006.173.02:23:44.22#ibcon#flushed, iclass 22, count 0 2006.173.02:23:44.22#ibcon#about to write, iclass 22, count 0 2006.173.02:23:44.22#ibcon#wrote, iclass 22, count 0 2006.173.02:23:44.22#ibcon#about to read 3, iclass 22, count 0 2006.173.02:23:44.26#ibcon#read 3, iclass 22, count 0 2006.173.02:23:44.26#ibcon#about to read 4, iclass 22, count 0 2006.173.02:23:44.26#ibcon#read 4, iclass 22, count 0 2006.173.02:23:44.26#ibcon#about to read 5, iclass 22, count 0 2006.173.02:23:44.26#ibcon#read 5, iclass 22, count 0 2006.173.02:23:44.26#ibcon#about to read 6, iclass 22, count 0 2006.173.02:23:44.26#ibcon#read 6, iclass 22, count 0 2006.173.02:23:44.26#ibcon#end of sib2, iclass 22, count 0 2006.173.02:23:44.26#ibcon#*mode == 0, iclass 22, count 0 2006.173.02:23:44.26#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.02:23:44.26#ibcon#[25=USB\r\n] 2006.173.02:23:44.26#ibcon#*before write, iclass 22, count 0 2006.173.02:23:44.26#ibcon#enter sib2, iclass 22, count 0 2006.173.02:23:44.26#ibcon#flushed, iclass 22, count 0 2006.173.02:23:44.26#ibcon#about to write, iclass 22, count 0 2006.173.02:23:44.26#ibcon#wrote, iclass 22, count 0 2006.173.02:23:44.26#ibcon#about to read 3, iclass 22, count 0 2006.173.02:23:44.29#ibcon#read 3, iclass 22, count 0 2006.173.02:23:44.29#ibcon#about to read 4, iclass 22, count 0 2006.173.02:23:44.29#ibcon#read 4, iclass 22, count 0 2006.173.02:23:44.29#ibcon#about to read 5, iclass 22, count 0 2006.173.02:23:44.29#ibcon#read 5, iclass 22, count 0 2006.173.02:23:44.29#ibcon#about to read 6, iclass 22, count 0 2006.173.02:23:44.29#ibcon#read 6, iclass 22, count 0 2006.173.02:23:44.29#ibcon#end of sib2, iclass 22, count 0 2006.173.02:23:44.29#ibcon#*after write, iclass 22, count 0 2006.173.02:23:44.29#ibcon#*before return 0, iclass 22, count 0 2006.173.02:23:44.29#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.02:23:44.29#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.02:23:44.29#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.02:23:44.29#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.02:23:44.29$vck44/valo=3,564.99 2006.173.02:23:44.29#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.02:23:44.29#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.02:23:44.29#ibcon#ireg 17 cls_cnt 0 2006.173.02:23:44.29#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.02:23:44.29#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.02:23:44.29#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.02:23:44.29#ibcon#enter wrdev, iclass 24, count 0 2006.173.02:23:44.29#ibcon#first serial, iclass 24, count 0 2006.173.02:23:44.29#ibcon#enter sib2, iclass 24, count 0 2006.173.02:23:44.29#ibcon#flushed, iclass 24, count 0 2006.173.02:23:44.29#ibcon#about to write, iclass 24, count 0 2006.173.02:23:44.29#ibcon#wrote, iclass 24, count 0 2006.173.02:23:44.29#ibcon#about to read 3, iclass 24, count 0 2006.173.02:23:44.31#ibcon#read 3, iclass 24, count 0 2006.173.02:23:44.31#ibcon#about to read 4, iclass 24, count 0 2006.173.02:23:44.31#ibcon#read 4, iclass 24, count 0 2006.173.02:23:44.31#ibcon#about to read 5, iclass 24, count 0 2006.173.02:23:44.31#ibcon#read 5, iclass 24, count 0 2006.173.02:23:44.31#ibcon#about to read 6, iclass 24, count 0 2006.173.02:23:44.31#ibcon#read 6, iclass 24, count 0 2006.173.02:23:44.31#ibcon#end of sib2, iclass 24, count 0 2006.173.02:23:44.31#ibcon#*mode == 0, iclass 24, count 0 2006.173.02:23:44.31#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.02:23:44.31#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.02:23:44.31#ibcon#*before write, iclass 24, count 0 2006.173.02:23:44.31#ibcon#enter sib2, iclass 24, count 0 2006.173.02:23:44.31#ibcon#flushed, iclass 24, count 0 2006.173.02:23:44.31#ibcon#about to write, iclass 24, count 0 2006.173.02:23:44.31#ibcon#wrote, iclass 24, count 0 2006.173.02:23:44.31#ibcon#about to read 3, iclass 24, count 0 2006.173.02:23:44.36#ibcon#read 3, iclass 24, count 0 2006.173.02:23:44.36#ibcon#about to read 4, iclass 24, count 0 2006.173.02:23:44.36#ibcon#read 4, iclass 24, count 0 2006.173.02:23:44.36#ibcon#about to read 5, iclass 24, count 0 2006.173.02:23:44.36#ibcon#read 5, iclass 24, count 0 2006.173.02:23:44.36#ibcon#about to read 6, iclass 24, count 0 2006.173.02:23:44.36#ibcon#read 6, iclass 24, count 0 2006.173.02:23:44.36#ibcon#end of sib2, iclass 24, count 0 2006.173.02:23:44.36#ibcon#*after write, iclass 24, count 0 2006.173.02:23:44.36#ibcon#*before return 0, iclass 24, count 0 2006.173.02:23:44.36#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.02:23:44.36#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.02:23:44.36#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.02:23:44.36#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.02:23:44.36$vck44/va=3,5 2006.173.02:23:44.36#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.02:23:44.36#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.02:23:44.36#ibcon#ireg 11 cls_cnt 2 2006.173.02:23:44.36#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.02:23:44.40#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.02:23:44.40#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.02:23:44.40#ibcon#enter wrdev, iclass 26, count 2 2006.173.02:23:44.40#ibcon#first serial, iclass 26, count 2 2006.173.02:23:44.40#ibcon#enter sib2, iclass 26, count 2 2006.173.02:23:44.40#ibcon#flushed, iclass 26, count 2 2006.173.02:23:44.40#ibcon#about to write, iclass 26, count 2 2006.173.02:23:44.40#ibcon#wrote, iclass 26, count 2 2006.173.02:23:44.40#ibcon#about to read 3, iclass 26, count 2 2006.173.02:23:44.42#ibcon#read 3, iclass 26, count 2 2006.173.02:23:44.42#ibcon#about to read 4, iclass 26, count 2 2006.173.02:23:44.42#ibcon#read 4, iclass 26, count 2 2006.173.02:23:44.42#ibcon#about to read 5, iclass 26, count 2 2006.173.02:23:44.42#ibcon#read 5, iclass 26, count 2 2006.173.02:23:44.42#ibcon#about to read 6, iclass 26, count 2 2006.173.02:23:44.42#ibcon#read 6, iclass 26, count 2 2006.173.02:23:44.42#ibcon#end of sib2, iclass 26, count 2 2006.173.02:23:44.42#ibcon#*mode == 0, iclass 26, count 2 2006.173.02:23:44.42#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.02:23:44.42#ibcon#[25=AT03-05\r\n] 2006.173.02:23:44.42#ibcon#*before write, iclass 26, count 2 2006.173.02:23:44.42#ibcon#enter sib2, iclass 26, count 2 2006.173.02:23:44.42#ibcon#flushed, iclass 26, count 2 2006.173.02:23:44.42#ibcon#about to write, iclass 26, count 2 2006.173.02:23:44.42#ibcon#wrote, iclass 26, count 2 2006.173.02:23:44.42#ibcon#about to read 3, iclass 26, count 2 2006.173.02:23:44.45#ibcon#read 3, iclass 26, count 2 2006.173.02:23:44.45#ibcon#about to read 4, iclass 26, count 2 2006.173.02:23:44.45#ibcon#read 4, iclass 26, count 2 2006.173.02:23:44.45#ibcon#about to read 5, iclass 26, count 2 2006.173.02:23:44.45#ibcon#read 5, iclass 26, count 2 2006.173.02:23:44.45#ibcon#about to read 6, iclass 26, count 2 2006.173.02:23:44.45#ibcon#read 6, iclass 26, count 2 2006.173.02:23:44.45#ibcon#end of sib2, iclass 26, count 2 2006.173.02:23:44.45#ibcon#*after write, iclass 26, count 2 2006.173.02:23:44.45#ibcon#*before return 0, iclass 26, count 2 2006.173.02:23:44.45#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.02:23:44.45#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.02:23:44.45#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.02:23:44.45#ibcon#ireg 7 cls_cnt 0 2006.173.02:23:44.45#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.02:23:44.57#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.02:23:44.57#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.02:23:44.57#ibcon#enter wrdev, iclass 26, count 0 2006.173.02:23:44.57#ibcon#first serial, iclass 26, count 0 2006.173.02:23:44.57#ibcon#enter sib2, iclass 26, count 0 2006.173.02:23:44.57#ibcon#flushed, iclass 26, count 0 2006.173.02:23:44.57#ibcon#about to write, iclass 26, count 0 2006.173.02:23:44.57#ibcon#wrote, iclass 26, count 0 2006.173.02:23:44.57#ibcon#about to read 3, iclass 26, count 0 2006.173.02:23:44.59#ibcon#read 3, iclass 26, count 0 2006.173.02:23:44.59#ibcon#about to read 4, iclass 26, count 0 2006.173.02:23:44.59#ibcon#read 4, iclass 26, count 0 2006.173.02:23:44.59#ibcon#about to read 5, iclass 26, count 0 2006.173.02:23:44.59#ibcon#read 5, iclass 26, count 0 2006.173.02:23:44.59#ibcon#about to read 6, iclass 26, count 0 2006.173.02:23:44.59#ibcon#read 6, iclass 26, count 0 2006.173.02:23:44.59#ibcon#end of sib2, iclass 26, count 0 2006.173.02:23:44.59#ibcon#*mode == 0, iclass 26, count 0 2006.173.02:23:44.59#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.02:23:44.59#ibcon#[25=USB\r\n] 2006.173.02:23:44.59#ibcon#*before write, iclass 26, count 0 2006.173.02:23:44.59#ibcon#enter sib2, iclass 26, count 0 2006.173.02:23:44.59#ibcon#flushed, iclass 26, count 0 2006.173.02:23:44.59#ibcon#about to write, iclass 26, count 0 2006.173.02:23:44.59#ibcon#wrote, iclass 26, count 0 2006.173.02:23:44.59#ibcon#about to read 3, iclass 26, count 0 2006.173.02:23:44.62#ibcon#read 3, iclass 26, count 0 2006.173.02:23:44.62#ibcon#about to read 4, iclass 26, count 0 2006.173.02:23:44.62#ibcon#read 4, iclass 26, count 0 2006.173.02:23:44.62#ibcon#about to read 5, iclass 26, count 0 2006.173.02:23:44.62#ibcon#read 5, iclass 26, count 0 2006.173.02:23:44.62#ibcon#about to read 6, iclass 26, count 0 2006.173.02:23:44.62#ibcon#read 6, iclass 26, count 0 2006.173.02:23:44.62#ibcon#end of sib2, iclass 26, count 0 2006.173.02:23:44.62#ibcon#*after write, iclass 26, count 0 2006.173.02:23:44.62#ibcon#*before return 0, iclass 26, count 0 2006.173.02:23:44.62#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.02:23:44.62#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.02:23:44.62#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.02:23:44.62#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.02:23:44.62$vck44/valo=4,624.99 2006.173.02:23:44.62#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.02:23:44.62#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.02:23:44.62#ibcon#ireg 17 cls_cnt 0 2006.173.02:23:44.62#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.02:23:44.62#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.02:23:44.62#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.02:23:44.62#ibcon#enter wrdev, iclass 28, count 0 2006.173.02:23:44.62#ibcon#first serial, iclass 28, count 0 2006.173.02:23:44.62#ibcon#enter sib2, iclass 28, count 0 2006.173.02:23:44.62#ibcon#flushed, iclass 28, count 0 2006.173.02:23:44.62#ibcon#about to write, iclass 28, count 0 2006.173.02:23:44.62#ibcon#wrote, iclass 28, count 0 2006.173.02:23:44.62#ibcon#about to read 3, iclass 28, count 0 2006.173.02:23:44.64#ibcon#read 3, iclass 28, count 0 2006.173.02:23:44.64#ibcon#about to read 4, iclass 28, count 0 2006.173.02:23:44.64#ibcon#read 4, iclass 28, count 0 2006.173.02:23:44.64#ibcon#about to read 5, iclass 28, count 0 2006.173.02:23:44.64#ibcon#read 5, iclass 28, count 0 2006.173.02:23:44.64#ibcon#about to read 6, iclass 28, count 0 2006.173.02:23:44.64#ibcon#read 6, iclass 28, count 0 2006.173.02:23:44.64#ibcon#end of sib2, iclass 28, count 0 2006.173.02:23:44.64#ibcon#*mode == 0, iclass 28, count 0 2006.173.02:23:44.64#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.02:23:44.64#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.02:23:44.64#ibcon#*before write, iclass 28, count 0 2006.173.02:23:44.64#ibcon#enter sib2, iclass 28, count 0 2006.173.02:23:44.64#ibcon#flushed, iclass 28, count 0 2006.173.02:23:44.64#ibcon#about to write, iclass 28, count 0 2006.173.02:23:44.64#ibcon#wrote, iclass 28, count 0 2006.173.02:23:44.64#ibcon#about to read 3, iclass 28, count 0 2006.173.02:23:44.68#ibcon#read 3, iclass 28, count 0 2006.173.02:23:44.68#ibcon#about to read 4, iclass 28, count 0 2006.173.02:23:44.68#ibcon#read 4, iclass 28, count 0 2006.173.02:23:44.68#ibcon#about to read 5, iclass 28, count 0 2006.173.02:23:44.68#ibcon#read 5, iclass 28, count 0 2006.173.02:23:44.68#ibcon#about to read 6, iclass 28, count 0 2006.173.02:23:44.68#ibcon#read 6, iclass 28, count 0 2006.173.02:23:44.68#ibcon#end of sib2, iclass 28, count 0 2006.173.02:23:44.68#ibcon#*after write, iclass 28, count 0 2006.173.02:23:44.68#ibcon#*before return 0, iclass 28, count 0 2006.173.02:23:44.68#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.02:23:44.68#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.02:23:44.68#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.02:23:44.68#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.02:23:44.68$vck44/va=4,6 2006.173.02:23:44.68#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.02:23:44.68#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.02:23:44.68#ibcon#ireg 11 cls_cnt 2 2006.173.02:23:44.68#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.02:23:44.74#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.02:23:44.74#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.02:23:44.74#ibcon#enter wrdev, iclass 30, count 2 2006.173.02:23:44.74#ibcon#first serial, iclass 30, count 2 2006.173.02:23:44.74#ibcon#enter sib2, iclass 30, count 2 2006.173.02:23:44.74#ibcon#flushed, iclass 30, count 2 2006.173.02:23:44.74#ibcon#about to write, iclass 30, count 2 2006.173.02:23:44.74#ibcon#wrote, iclass 30, count 2 2006.173.02:23:44.74#ibcon#about to read 3, iclass 30, count 2 2006.173.02:23:44.76#ibcon#read 3, iclass 30, count 2 2006.173.02:23:44.76#ibcon#about to read 4, iclass 30, count 2 2006.173.02:23:44.76#ibcon#read 4, iclass 30, count 2 2006.173.02:23:44.76#ibcon#about to read 5, iclass 30, count 2 2006.173.02:23:44.76#ibcon#read 5, iclass 30, count 2 2006.173.02:23:44.76#ibcon#about to read 6, iclass 30, count 2 2006.173.02:23:44.76#ibcon#read 6, iclass 30, count 2 2006.173.02:23:44.76#ibcon#end of sib2, iclass 30, count 2 2006.173.02:23:44.76#ibcon#*mode == 0, iclass 30, count 2 2006.173.02:23:44.76#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.02:23:44.76#ibcon#[25=AT04-06\r\n] 2006.173.02:23:44.76#ibcon#*before write, iclass 30, count 2 2006.173.02:23:44.76#ibcon#enter sib2, iclass 30, count 2 2006.173.02:23:44.76#ibcon#flushed, iclass 30, count 2 2006.173.02:23:44.76#ibcon#about to write, iclass 30, count 2 2006.173.02:23:44.76#ibcon#wrote, iclass 30, count 2 2006.173.02:23:44.76#ibcon#about to read 3, iclass 30, count 2 2006.173.02:23:44.79#ibcon#read 3, iclass 30, count 2 2006.173.02:23:44.79#ibcon#about to read 4, iclass 30, count 2 2006.173.02:23:44.79#ibcon#read 4, iclass 30, count 2 2006.173.02:23:44.79#ibcon#about to read 5, iclass 30, count 2 2006.173.02:23:44.79#ibcon#read 5, iclass 30, count 2 2006.173.02:23:44.79#ibcon#about to read 6, iclass 30, count 2 2006.173.02:23:44.79#ibcon#read 6, iclass 30, count 2 2006.173.02:23:44.79#ibcon#end of sib2, iclass 30, count 2 2006.173.02:23:44.79#ibcon#*after write, iclass 30, count 2 2006.173.02:23:44.79#ibcon#*before return 0, iclass 30, count 2 2006.173.02:23:44.79#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.02:23:44.79#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.02:23:44.79#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.02:23:44.79#ibcon#ireg 7 cls_cnt 0 2006.173.02:23:44.79#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.02:23:44.91#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.02:23:44.91#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.02:23:44.91#ibcon#enter wrdev, iclass 30, count 0 2006.173.02:23:44.91#ibcon#first serial, iclass 30, count 0 2006.173.02:23:44.91#ibcon#enter sib2, iclass 30, count 0 2006.173.02:23:44.91#ibcon#flushed, iclass 30, count 0 2006.173.02:23:44.91#ibcon#about to write, iclass 30, count 0 2006.173.02:23:44.91#ibcon#wrote, iclass 30, count 0 2006.173.02:23:44.91#ibcon#about to read 3, iclass 30, count 0 2006.173.02:23:44.93#ibcon#read 3, iclass 30, count 0 2006.173.02:23:44.93#ibcon#about to read 4, iclass 30, count 0 2006.173.02:23:44.93#ibcon#read 4, iclass 30, count 0 2006.173.02:23:44.93#ibcon#about to read 5, iclass 30, count 0 2006.173.02:23:44.93#ibcon#read 5, iclass 30, count 0 2006.173.02:23:44.93#ibcon#about to read 6, iclass 30, count 0 2006.173.02:23:44.93#ibcon#read 6, iclass 30, count 0 2006.173.02:23:44.93#ibcon#end of sib2, iclass 30, count 0 2006.173.02:23:44.93#ibcon#*mode == 0, iclass 30, count 0 2006.173.02:23:44.93#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.02:23:44.93#ibcon#[25=USB\r\n] 2006.173.02:23:44.93#ibcon#*before write, iclass 30, count 0 2006.173.02:23:44.93#ibcon#enter sib2, iclass 30, count 0 2006.173.02:23:44.93#ibcon#flushed, iclass 30, count 0 2006.173.02:23:44.93#ibcon#about to write, iclass 30, count 0 2006.173.02:23:44.93#ibcon#wrote, iclass 30, count 0 2006.173.02:23:44.93#ibcon#about to read 3, iclass 30, count 0 2006.173.02:23:44.96#ibcon#read 3, iclass 30, count 0 2006.173.02:23:44.96#ibcon#about to read 4, iclass 30, count 0 2006.173.02:23:44.96#ibcon#read 4, iclass 30, count 0 2006.173.02:23:44.96#ibcon#about to read 5, iclass 30, count 0 2006.173.02:23:44.96#ibcon#read 5, iclass 30, count 0 2006.173.02:23:44.96#ibcon#about to read 6, iclass 30, count 0 2006.173.02:23:44.96#ibcon#read 6, iclass 30, count 0 2006.173.02:23:44.96#ibcon#end of sib2, iclass 30, count 0 2006.173.02:23:44.96#ibcon#*after write, iclass 30, count 0 2006.173.02:23:44.96#ibcon#*before return 0, iclass 30, count 0 2006.173.02:23:44.96#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.02:23:44.96#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.02:23:44.96#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.02:23:44.96#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.02:23:44.96$vck44/valo=5,734.99 2006.173.02:23:44.96#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.02:23:44.96#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.02:23:44.96#ibcon#ireg 17 cls_cnt 0 2006.173.02:23:44.96#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.02:23:44.96#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.02:23:44.96#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.02:23:44.96#ibcon#enter wrdev, iclass 32, count 0 2006.173.02:23:44.96#ibcon#first serial, iclass 32, count 0 2006.173.02:23:44.96#ibcon#enter sib2, iclass 32, count 0 2006.173.02:23:44.96#ibcon#flushed, iclass 32, count 0 2006.173.02:23:44.96#ibcon#about to write, iclass 32, count 0 2006.173.02:23:44.96#ibcon#wrote, iclass 32, count 0 2006.173.02:23:44.96#ibcon#about to read 3, iclass 32, count 0 2006.173.02:23:44.98#ibcon#read 3, iclass 32, count 0 2006.173.02:23:44.98#ibcon#about to read 4, iclass 32, count 0 2006.173.02:23:44.98#ibcon#read 4, iclass 32, count 0 2006.173.02:23:44.98#ibcon#about to read 5, iclass 32, count 0 2006.173.02:23:44.98#ibcon#read 5, iclass 32, count 0 2006.173.02:23:44.98#ibcon#about to read 6, iclass 32, count 0 2006.173.02:23:44.98#ibcon#read 6, iclass 32, count 0 2006.173.02:23:44.98#ibcon#end of sib2, iclass 32, count 0 2006.173.02:23:44.98#ibcon#*mode == 0, iclass 32, count 0 2006.173.02:23:44.98#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.02:23:44.98#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.02:23:44.98#ibcon#*before write, iclass 32, count 0 2006.173.02:23:44.98#ibcon#enter sib2, iclass 32, count 0 2006.173.02:23:44.98#ibcon#flushed, iclass 32, count 0 2006.173.02:23:44.98#ibcon#about to write, iclass 32, count 0 2006.173.02:23:44.98#ibcon#wrote, iclass 32, count 0 2006.173.02:23:44.98#ibcon#about to read 3, iclass 32, count 0 2006.173.02:23:45.02#ibcon#read 3, iclass 32, count 0 2006.173.02:23:45.02#ibcon#about to read 4, iclass 32, count 0 2006.173.02:23:45.02#ibcon#read 4, iclass 32, count 0 2006.173.02:23:45.02#ibcon#about to read 5, iclass 32, count 0 2006.173.02:23:45.02#ibcon#read 5, iclass 32, count 0 2006.173.02:23:45.02#ibcon#about to read 6, iclass 32, count 0 2006.173.02:23:45.02#ibcon#read 6, iclass 32, count 0 2006.173.02:23:45.02#ibcon#end of sib2, iclass 32, count 0 2006.173.02:23:45.02#ibcon#*after write, iclass 32, count 0 2006.173.02:23:45.02#ibcon#*before return 0, iclass 32, count 0 2006.173.02:23:45.02#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.02:23:45.02#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.02:23:45.02#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.02:23:45.02#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.02:23:45.02$vck44/va=5,4 2006.173.02:23:45.02#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.02:23:45.02#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.02:23:45.02#ibcon#ireg 11 cls_cnt 2 2006.173.02:23:45.02#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.02:23:45.09#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.02:23:45.09#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.02:23:45.09#ibcon#enter wrdev, iclass 34, count 2 2006.173.02:23:45.09#ibcon#first serial, iclass 34, count 2 2006.173.02:23:45.09#ibcon#enter sib2, iclass 34, count 2 2006.173.02:23:45.09#ibcon#flushed, iclass 34, count 2 2006.173.02:23:45.09#ibcon#about to write, iclass 34, count 2 2006.173.02:23:45.09#ibcon#wrote, iclass 34, count 2 2006.173.02:23:45.09#ibcon#about to read 3, iclass 34, count 2 2006.173.02:23:45.10#ibcon#read 3, iclass 34, count 2 2006.173.02:23:45.10#ibcon#about to read 4, iclass 34, count 2 2006.173.02:23:45.10#ibcon#read 4, iclass 34, count 2 2006.173.02:23:45.10#ibcon#about to read 5, iclass 34, count 2 2006.173.02:23:45.10#ibcon#read 5, iclass 34, count 2 2006.173.02:23:45.10#ibcon#about to read 6, iclass 34, count 2 2006.173.02:23:45.10#ibcon#read 6, iclass 34, count 2 2006.173.02:23:45.10#ibcon#end of sib2, iclass 34, count 2 2006.173.02:23:45.10#ibcon#*mode == 0, iclass 34, count 2 2006.173.02:23:45.10#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.02:23:45.10#ibcon#[25=AT05-04\r\n] 2006.173.02:23:45.10#ibcon#*before write, iclass 34, count 2 2006.173.02:23:45.10#ibcon#enter sib2, iclass 34, count 2 2006.173.02:23:45.10#ibcon#flushed, iclass 34, count 2 2006.173.02:23:45.10#ibcon#about to write, iclass 34, count 2 2006.173.02:23:45.10#ibcon#wrote, iclass 34, count 2 2006.173.02:23:45.10#ibcon#about to read 3, iclass 34, count 2 2006.173.02:23:45.13#ibcon#read 3, iclass 34, count 2 2006.173.02:23:45.13#ibcon#about to read 4, iclass 34, count 2 2006.173.02:23:45.13#ibcon#read 4, iclass 34, count 2 2006.173.02:23:45.13#ibcon#about to read 5, iclass 34, count 2 2006.173.02:23:45.13#ibcon#read 5, iclass 34, count 2 2006.173.02:23:45.13#ibcon#about to read 6, iclass 34, count 2 2006.173.02:23:45.13#ibcon#read 6, iclass 34, count 2 2006.173.02:23:45.13#ibcon#end of sib2, iclass 34, count 2 2006.173.02:23:45.13#ibcon#*after write, iclass 34, count 2 2006.173.02:23:45.13#ibcon#*before return 0, iclass 34, count 2 2006.173.02:23:45.13#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.02:23:45.13#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.02:23:45.13#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.02:23:45.13#ibcon#ireg 7 cls_cnt 0 2006.173.02:23:45.13#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.02:23:45.25#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.02:23:45.25#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.02:23:45.25#ibcon#enter wrdev, iclass 34, count 0 2006.173.02:23:45.25#ibcon#first serial, iclass 34, count 0 2006.173.02:23:45.25#ibcon#enter sib2, iclass 34, count 0 2006.173.02:23:45.25#ibcon#flushed, iclass 34, count 0 2006.173.02:23:45.25#ibcon#about to write, iclass 34, count 0 2006.173.02:23:45.25#ibcon#wrote, iclass 34, count 0 2006.173.02:23:45.25#ibcon#about to read 3, iclass 34, count 0 2006.173.02:23:45.27#ibcon#read 3, iclass 34, count 0 2006.173.02:23:45.27#ibcon#about to read 4, iclass 34, count 0 2006.173.02:23:45.27#ibcon#read 4, iclass 34, count 0 2006.173.02:23:45.27#ibcon#about to read 5, iclass 34, count 0 2006.173.02:23:45.27#ibcon#read 5, iclass 34, count 0 2006.173.02:23:45.27#ibcon#about to read 6, iclass 34, count 0 2006.173.02:23:45.27#ibcon#read 6, iclass 34, count 0 2006.173.02:23:45.27#ibcon#end of sib2, iclass 34, count 0 2006.173.02:23:45.27#ibcon#*mode == 0, iclass 34, count 0 2006.173.02:23:45.27#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.02:23:45.27#ibcon#[25=USB\r\n] 2006.173.02:23:45.27#ibcon#*before write, iclass 34, count 0 2006.173.02:23:45.27#ibcon#enter sib2, iclass 34, count 0 2006.173.02:23:45.27#ibcon#flushed, iclass 34, count 0 2006.173.02:23:45.27#ibcon#about to write, iclass 34, count 0 2006.173.02:23:45.27#ibcon#wrote, iclass 34, count 0 2006.173.02:23:45.27#ibcon#about to read 3, iclass 34, count 0 2006.173.02:23:45.30#ibcon#read 3, iclass 34, count 0 2006.173.02:23:45.30#ibcon#about to read 4, iclass 34, count 0 2006.173.02:23:45.30#ibcon#read 4, iclass 34, count 0 2006.173.02:23:45.30#ibcon#about to read 5, iclass 34, count 0 2006.173.02:23:45.30#ibcon#read 5, iclass 34, count 0 2006.173.02:23:45.30#ibcon#about to read 6, iclass 34, count 0 2006.173.02:23:45.30#ibcon#read 6, iclass 34, count 0 2006.173.02:23:45.30#ibcon#end of sib2, iclass 34, count 0 2006.173.02:23:45.30#ibcon#*after write, iclass 34, count 0 2006.173.02:23:45.30#ibcon#*before return 0, iclass 34, count 0 2006.173.02:23:45.30#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.02:23:45.30#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.02:23:45.30#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.02:23:45.30#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.02:23:45.30$vck44/valo=6,814.99 2006.173.02:23:45.30#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.02:23:45.30#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.02:23:45.30#ibcon#ireg 17 cls_cnt 0 2006.173.02:23:45.30#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.02:23:45.30#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.02:23:45.30#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.02:23:45.30#ibcon#enter wrdev, iclass 36, count 0 2006.173.02:23:45.30#ibcon#first serial, iclass 36, count 0 2006.173.02:23:45.30#ibcon#enter sib2, iclass 36, count 0 2006.173.02:23:45.30#ibcon#flushed, iclass 36, count 0 2006.173.02:23:45.30#ibcon#about to write, iclass 36, count 0 2006.173.02:23:45.30#ibcon#wrote, iclass 36, count 0 2006.173.02:23:45.30#ibcon#about to read 3, iclass 36, count 0 2006.173.02:23:45.32#ibcon#read 3, iclass 36, count 0 2006.173.02:23:45.32#ibcon#about to read 4, iclass 36, count 0 2006.173.02:23:45.32#ibcon#read 4, iclass 36, count 0 2006.173.02:23:45.32#ibcon#about to read 5, iclass 36, count 0 2006.173.02:23:45.32#ibcon#read 5, iclass 36, count 0 2006.173.02:23:45.32#ibcon#about to read 6, iclass 36, count 0 2006.173.02:23:45.32#ibcon#read 6, iclass 36, count 0 2006.173.02:23:45.32#ibcon#end of sib2, iclass 36, count 0 2006.173.02:23:45.32#ibcon#*mode == 0, iclass 36, count 0 2006.173.02:23:45.32#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.02:23:45.32#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.02:23:45.32#ibcon#*before write, iclass 36, count 0 2006.173.02:23:45.32#ibcon#enter sib2, iclass 36, count 0 2006.173.02:23:45.32#ibcon#flushed, iclass 36, count 0 2006.173.02:23:45.32#ibcon#about to write, iclass 36, count 0 2006.173.02:23:45.32#ibcon#wrote, iclass 36, count 0 2006.173.02:23:45.32#ibcon#about to read 3, iclass 36, count 0 2006.173.02:23:45.36#ibcon#read 3, iclass 36, count 0 2006.173.02:23:45.36#ibcon#about to read 4, iclass 36, count 0 2006.173.02:23:45.36#ibcon#read 4, iclass 36, count 0 2006.173.02:23:45.36#ibcon#about to read 5, iclass 36, count 0 2006.173.02:23:45.36#ibcon#read 5, iclass 36, count 0 2006.173.02:23:45.36#ibcon#about to read 6, iclass 36, count 0 2006.173.02:23:45.36#ibcon#read 6, iclass 36, count 0 2006.173.02:23:45.36#ibcon#end of sib2, iclass 36, count 0 2006.173.02:23:45.36#ibcon#*after write, iclass 36, count 0 2006.173.02:23:45.36#ibcon#*before return 0, iclass 36, count 0 2006.173.02:23:45.36#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.02:23:45.36#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.02:23:45.36#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.02:23:45.36#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.02:23:45.36$vck44/va=6,3 2006.173.02:23:45.36#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.02:23:45.36#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.02:23:45.36#ibcon#ireg 11 cls_cnt 2 2006.173.02:23:45.36#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.02:23:45.42#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.02:23:45.42#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.02:23:45.42#ibcon#enter wrdev, iclass 38, count 2 2006.173.02:23:45.42#ibcon#first serial, iclass 38, count 2 2006.173.02:23:45.42#ibcon#enter sib2, iclass 38, count 2 2006.173.02:23:45.42#ibcon#flushed, iclass 38, count 2 2006.173.02:23:45.42#ibcon#about to write, iclass 38, count 2 2006.173.02:23:45.42#ibcon#wrote, iclass 38, count 2 2006.173.02:23:45.42#ibcon#about to read 3, iclass 38, count 2 2006.173.02:23:45.44#ibcon#read 3, iclass 38, count 2 2006.173.02:23:45.44#ibcon#about to read 4, iclass 38, count 2 2006.173.02:23:45.44#ibcon#read 4, iclass 38, count 2 2006.173.02:23:45.44#ibcon#about to read 5, iclass 38, count 2 2006.173.02:23:45.44#ibcon#read 5, iclass 38, count 2 2006.173.02:23:45.44#ibcon#about to read 6, iclass 38, count 2 2006.173.02:23:45.44#ibcon#read 6, iclass 38, count 2 2006.173.02:23:45.44#ibcon#end of sib2, iclass 38, count 2 2006.173.02:23:45.44#ibcon#*mode == 0, iclass 38, count 2 2006.173.02:23:45.44#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.02:23:45.44#ibcon#[25=AT06-03\r\n] 2006.173.02:23:45.44#ibcon#*before write, iclass 38, count 2 2006.173.02:23:45.44#ibcon#enter sib2, iclass 38, count 2 2006.173.02:23:45.44#ibcon#flushed, iclass 38, count 2 2006.173.02:23:45.44#ibcon#about to write, iclass 38, count 2 2006.173.02:23:45.44#ibcon#wrote, iclass 38, count 2 2006.173.02:23:45.44#ibcon#about to read 3, iclass 38, count 2 2006.173.02:23:45.47#ibcon#read 3, iclass 38, count 2 2006.173.02:23:45.47#ibcon#about to read 4, iclass 38, count 2 2006.173.02:23:45.47#ibcon#read 4, iclass 38, count 2 2006.173.02:23:45.47#ibcon#about to read 5, iclass 38, count 2 2006.173.02:23:45.47#ibcon#read 5, iclass 38, count 2 2006.173.02:23:45.47#ibcon#about to read 6, iclass 38, count 2 2006.173.02:23:45.47#ibcon#read 6, iclass 38, count 2 2006.173.02:23:45.47#ibcon#end of sib2, iclass 38, count 2 2006.173.02:23:45.47#ibcon#*after write, iclass 38, count 2 2006.173.02:23:45.47#ibcon#*before return 0, iclass 38, count 2 2006.173.02:23:45.47#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.02:23:45.47#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.02:23:45.47#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.02:23:45.47#ibcon#ireg 7 cls_cnt 0 2006.173.02:23:45.47#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.02:23:45.59#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.02:23:45.59#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.02:23:45.59#ibcon#enter wrdev, iclass 38, count 0 2006.173.02:23:45.59#ibcon#first serial, iclass 38, count 0 2006.173.02:23:45.59#ibcon#enter sib2, iclass 38, count 0 2006.173.02:23:45.59#ibcon#flushed, iclass 38, count 0 2006.173.02:23:45.59#ibcon#about to write, iclass 38, count 0 2006.173.02:23:45.59#ibcon#wrote, iclass 38, count 0 2006.173.02:23:45.59#ibcon#about to read 3, iclass 38, count 0 2006.173.02:23:45.61#ibcon#read 3, iclass 38, count 0 2006.173.02:23:45.61#ibcon#about to read 4, iclass 38, count 0 2006.173.02:23:45.61#ibcon#read 4, iclass 38, count 0 2006.173.02:23:45.61#ibcon#about to read 5, iclass 38, count 0 2006.173.02:23:45.61#ibcon#read 5, iclass 38, count 0 2006.173.02:23:45.61#ibcon#about to read 6, iclass 38, count 0 2006.173.02:23:45.61#ibcon#read 6, iclass 38, count 0 2006.173.02:23:45.61#ibcon#end of sib2, iclass 38, count 0 2006.173.02:23:45.61#ibcon#*mode == 0, iclass 38, count 0 2006.173.02:23:45.61#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.02:23:45.61#ibcon#[25=USB\r\n] 2006.173.02:23:45.61#ibcon#*before write, iclass 38, count 0 2006.173.02:23:45.61#ibcon#enter sib2, iclass 38, count 0 2006.173.02:23:45.61#ibcon#flushed, iclass 38, count 0 2006.173.02:23:45.61#ibcon#about to write, iclass 38, count 0 2006.173.02:23:45.61#ibcon#wrote, iclass 38, count 0 2006.173.02:23:45.61#ibcon#about to read 3, iclass 38, count 0 2006.173.02:23:45.64#ibcon#read 3, iclass 38, count 0 2006.173.02:23:45.64#ibcon#about to read 4, iclass 38, count 0 2006.173.02:23:45.64#ibcon#read 4, iclass 38, count 0 2006.173.02:23:45.64#ibcon#about to read 5, iclass 38, count 0 2006.173.02:23:45.64#ibcon#read 5, iclass 38, count 0 2006.173.02:23:45.64#ibcon#about to read 6, iclass 38, count 0 2006.173.02:23:45.64#ibcon#read 6, iclass 38, count 0 2006.173.02:23:45.64#ibcon#end of sib2, iclass 38, count 0 2006.173.02:23:45.64#ibcon#*after write, iclass 38, count 0 2006.173.02:23:45.64#ibcon#*before return 0, iclass 38, count 0 2006.173.02:23:45.64#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.02:23:45.64#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.02:23:45.64#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.02:23:45.64#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.02:23:45.64$vck44/valo=7,864.99 2006.173.02:23:45.64#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.02:23:45.64#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.02:23:45.64#ibcon#ireg 17 cls_cnt 0 2006.173.02:23:45.64#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.02:23:45.64#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.02:23:45.64#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.02:23:45.64#ibcon#enter wrdev, iclass 40, count 0 2006.173.02:23:45.64#ibcon#first serial, iclass 40, count 0 2006.173.02:23:45.64#ibcon#enter sib2, iclass 40, count 0 2006.173.02:23:45.64#ibcon#flushed, iclass 40, count 0 2006.173.02:23:45.64#ibcon#about to write, iclass 40, count 0 2006.173.02:23:45.64#ibcon#wrote, iclass 40, count 0 2006.173.02:23:45.64#ibcon#about to read 3, iclass 40, count 0 2006.173.02:23:45.66#ibcon#read 3, iclass 40, count 0 2006.173.02:23:45.66#ibcon#about to read 4, iclass 40, count 0 2006.173.02:23:45.66#ibcon#read 4, iclass 40, count 0 2006.173.02:23:45.66#ibcon#about to read 5, iclass 40, count 0 2006.173.02:23:45.66#ibcon#read 5, iclass 40, count 0 2006.173.02:23:45.66#ibcon#about to read 6, iclass 40, count 0 2006.173.02:23:45.66#ibcon#read 6, iclass 40, count 0 2006.173.02:23:45.66#ibcon#end of sib2, iclass 40, count 0 2006.173.02:23:45.66#ibcon#*mode == 0, iclass 40, count 0 2006.173.02:23:45.66#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.02:23:45.66#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.02:23:45.66#ibcon#*before write, iclass 40, count 0 2006.173.02:23:45.66#ibcon#enter sib2, iclass 40, count 0 2006.173.02:23:45.66#ibcon#flushed, iclass 40, count 0 2006.173.02:23:45.66#ibcon#about to write, iclass 40, count 0 2006.173.02:23:45.66#ibcon#wrote, iclass 40, count 0 2006.173.02:23:45.66#ibcon#about to read 3, iclass 40, count 0 2006.173.02:23:45.70#ibcon#read 3, iclass 40, count 0 2006.173.02:23:45.70#ibcon#about to read 4, iclass 40, count 0 2006.173.02:23:45.70#ibcon#read 4, iclass 40, count 0 2006.173.02:23:45.70#ibcon#about to read 5, iclass 40, count 0 2006.173.02:23:45.70#ibcon#read 5, iclass 40, count 0 2006.173.02:23:45.70#ibcon#about to read 6, iclass 40, count 0 2006.173.02:23:45.70#ibcon#read 6, iclass 40, count 0 2006.173.02:23:45.70#ibcon#end of sib2, iclass 40, count 0 2006.173.02:23:45.70#ibcon#*after write, iclass 40, count 0 2006.173.02:23:45.70#ibcon#*before return 0, iclass 40, count 0 2006.173.02:23:45.70#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.02:23:45.70#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.02:23:45.70#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.02:23:45.70#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.02:23:45.70$vck44/va=7,4 2006.173.02:23:45.70#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.02:23:45.70#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.02:23:45.70#ibcon#ireg 11 cls_cnt 2 2006.173.02:23:45.70#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.02:23:45.77#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.02:23:45.77#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.02:23:45.77#ibcon#enter wrdev, iclass 4, count 2 2006.173.02:23:45.77#ibcon#first serial, iclass 4, count 2 2006.173.02:23:45.77#ibcon#enter sib2, iclass 4, count 2 2006.173.02:23:45.77#ibcon#flushed, iclass 4, count 2 2006.173.02:23:45.77#ibcon#about to write, iclass 4, count 2 2006.173.02:23:45.77#ibcon#wrote, iclass 4, count 2 2006.173.02:23:45.77#ibcon#about to read 3, iclass 4, count 2 2006.173.02:23:45.78#ibcon#read 3, iclass 4, count 2 2006.173.02:23:45.78#ibcon#about to read 4, iclass 4, count 2 2006.173.02:23:45.78#ibcon#read 4, iclass 4, count 2 2006.173.02:23:45.78#ibcon#about to read 5, iclass 4, count 2 2006.173.02:23:45.78#ibcon#read 5, iclass 4, count 2 2006.173.02:23:45.78#ibcon#about to read 6, iclass 4, count 2 2006.173.02:23:45.78#ibcon#read 6, iclass 4, count 2 2006.173.02:23:45.78#ibcon#end of sib2, iclass 4, count 2 2006.173.02:23:45.78#ibcon#*mode == 0, iclass 4, count 2 2006.173.02:23:45.78#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.02:23:45.78#ibcon#[25=AT07-04\r\n] 2006.173.02:23:45.78#ibcon#*before write, iclass 4, count 2 2006.173.02:23:45.78#ibcon#enter sib2, iclass 4, count 2 2006.173.02:23:45.78#ibcon#flushed, iclass 4, count 2 2006.173.02:23:45.78#ibcon#about to write, iclass 4, count 2 2006.173.02:23:45.78#ibcon#wrote, iclass 4, count 2 2006.173.02:23:45.78#ibcon#about to read 3, iclass 4, count 2 2006.173.02:23:45.81#ibcon#read 3, iclass 4, count 2 2006.173.02:23:45.81#ibcon#about to read 4, iclass 4, count 2 2006.173.02:23:45.81#ibcon#read 4, iclass 4, count 2 2006.173.02:23:45.81#ibcon#about to read 5, iclass 4, count 2 2006.173.02:23:45.81#ibcon#read 5, iclass 4, count 2 2006.173.02:23:45.81#ibcon#about to read 6, iclass 4, count 2 2006.173.02:23:45.81#ibcon#read 6, iclass 4, count 2 2006.173.02:23:45.81#ibcon#end of sib2, iclass 4, count 2 2006.173.02:23:45.81#ibcon#*after write, iclass 4, count 2 2006.173.02:23:45.81#ibcon#*before return 0, iclass 4, count 2 2006.173.02:23:45.81#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.02:23:45.81#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.02:23:45.81#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.02:23:45.81#ibcon#ireg 7 cls_cnt 0 2006.173.02:23:45.81#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.02:23:45.93#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.02:23:45.93#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.02:23:45.93#ibcon#enter wrdev, iclass 4, count 0 2006.173.02:23:45.93#ibcon#first serial, iclass 4, count 0 2006.173.02:23:45.93#ibcon#enter sib2, iclass 4, count 0 2006.173.02:23:45.93#ibcon#flushed, iclass 4, count 0 2006.173.02:23:45.93#ibcon#about to write, iclass 4, count 0 2006.173.02:23:45.93#ibcon#wrote, iclass 4, count 0 2006.173.02:23:45.93#ibcon#about to read 3, iclass 4, count 0 2006.173.02:23:45.95#ibcon#read 3, iclass 4, count 0 2006.173.02:23:45.95#ibcon#about to read 4, iclass 4, count 0 2006.173.02:23:45.95#ibcon#read 4, iclass 4, count 0 2006.173.02:23:45.95#ibcon#about to read 5, iclass 4, count 0 2006.173.02:23:45.95#ibcon#read 5, iclass 4, count 0 2006.173.02:23:45.95#ibcon#about to read 6, iclass 4, count 0 2006.173.02:23:45.95#ibcon#read 6, iclass 4, count 0 2006.173.02:23:45.95#ibcon#end of sib2, iclass 4, count 0 2006.173.02:23:45.95#ibcon#*mode == 0, iclass 4, count 0 2006.173.02:23:45.95#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.02:23:45.95#ibcon#[25=USB\r\n] 2006.173.02:23:45.95#ibcon#*before write, iclass 4, count 0 2006.173.02:23:45.95#ibcon#enter sib2, iclass 4, count 0 2006.173.02:23:45.95#ibcon#flushed, iclass 4, count 0 2006.173.02:23:45.95#ibcon#about to write, iclass 4, count 0 2006.173.02:23:45.95#ibcon#wrote, iclass 4, count 0 2006.173.02:23:45.95#ibcon#about to read 3, iclass 4, count 0 2006.173.02:23:45.98#ibcon#read 3, iclass 4, count 0 2006.173.02:23:45.98#ibcon#about to read 4, iclass 4, count 0 2006.173.02:23:45.98#ibcon#read 4, iclass 4, count 0 2006.173.02:23:45.98#ibcon#about to read 5, iclass 4, count 0 2006.173.02:23:45.98#ibcon#read 5, iclass 4, count 0 2006.173.02:23:45.98#ibcon#about to read 6, iclass 4, count 0 2006.173.02:23:45.98#ibcon#read 6, iclass 4, count 0 2006.173.02:23:45.98#ibcon#end of sib2, iclass 4, count 0 2006.173.02:23:45.98#ibcon#*after write, iclass 4, count 0 2006.173.02:23:45.98#ibcon#*before return 0, iclass 4, count 0 2006.173.02:23:45.98#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.02:23:45.98#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.02:23:45.98#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.02:23:45.98#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.02:23:45.98$vck44/valo=8,884.99 2006.173.02:23:45.98#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.02:23:45.98#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.02:23:45.98#ibcon#ireg 17 cls_cnt 0 2006.173.02:23:45.98#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.02:23:45.98#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.02:23:45.98#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.02:23:45.98#ibcon#enter wrdev, iclass 6, count 0 2006.173.02:23:45.98#ibcon#first serial, iclass 6, count 0 2006.173.02:23:45.98#ibcon#enter sib2, iclass 6, count 0 2006.173.02:23:45.98#ibcon#flushed, iclass 6, count 0 2006.173.02:23:45.98#ibcon#about to write, iclass 6, count 0 2006.173.02:23:45.98#ibcon#wrote, iclass 6, count 0 2006.173.02:23:45.98#ibcon#about to read 3, iclass 6, count 0 2006.173.02:23:46.00#ibcon#read 3, iclass 6, count 0 2006.173.02:23:46.00#ibcon#about to read 4, iclass 6, count 0 2006.173.02:23:46.00#ibcon#read 4, iclass 6, count 0 2006.173.02:23:46.00#ibcon#about to read 5, iclass 6, count 0 2006.173.02:23:46.00#ibcon#read 5, iclass 6, count 0 2006.173.02:23:46.00#ibcon#about to read 6, iclass 6, count 0 2006.173.02:23:46.00#ibcon#read 6, iclass 6, count 0 2006.173.02:23:46.00#ibcon#end of sib2, iclass 6, count 0 2006.173.02:23:46.00#ibcon#*mode == 0, iclass 6, count 0 2006.173.02:23:46.00#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.02:23:46.00#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.02:23:46.00#ibcon#*before write, iclass 6, count 0 2006.173.02:23:46.00#ibcon#enter sib2, iclass 6, count 0 2006.173.02:23:46.00#ibcon#flushed, iclass 6, count 0 2006.173.02:23:46.00#ibcon#about to write, iclass 6, count 0 2006.173.02:23:46.00#ibcon#wrote, iclass 6, count 0 2006.173.02:23:46.00#ibcon#about to read 3, iclass 6, count 0 2006.173.02:23:46.04#ibcon#read 3, iclass 6, count 0 2006.173.02:23:46.04#ibcon#about to read 4, iclass 6, count 0 2006.173.02:23:46.04#ibcon#read 4, iclass 6, count 0 2006.173.02:23:46.04#ibcon#about to read 5, iclass 6, count 0 2006.173.02:23:46.04#ibcon#read 5, iclass 6, count 0 2006.173.02:23:46.04#ibcon#about to read 6, iclass 6, count 0 2006.173.02:23:46.04#ibcon#read 6, iclass 6, count 0 2006.173.02:23:46.04#ibcon#end of sib2, iclass 6, count 0 2006.173.02:23:46.04#ibcon#*after write, iclass 6, count 0 2006.173.02:23:46.04#ibcon#*before return 0, iclass 6, count 0 2006.173.02:23:46.04#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.02:23:46.04#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.02:23:46.04#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.02:23:46.04#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.02:23:46.04$vck44/va=8,4 2006.173.02:23:46.04#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.02:23:46.04#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.02:23:46.04#ibcon#ireg 11 cls_cnt 2 2006.173.02:23:46.04#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.02:23:46.11#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.02:23:46.11#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.02:23:46.11#ibcon#enter wrdev, iclass 10, count 2 2006.173.02:23:46.11#ibcon#first serial, iclass 10, count 2 2006.173.02:23:46.11#ibcon#enter sib2, iclass 10, count 2 2006.173.02:23:46.11#ibcon#flushed, iclass 10, count 2 2006.173.02:23:46.11#ibcon#about to write, iclass 10, count 2 2006.173.02:23:46.11#ibcon#wrote, iclass 10, count 2 2006.173.02:23:46.11#ibcon#about to read 3, iclass 10, count 2 2006.173.02:23:46.12#ibcon#read 3, iclass 10, count 2 2006.173.02:23:46.12#ibcon#about to read 4, iclass 10, count 2 2006.173.02:23:46.12#ibcon#read 4, iclass 10, count 2 2006.173.02:23:46.12#ibcon#about to read 5, iclass 10, count 2 2006.173.02:23:46.12#ibcon#read 5, iclass 10, count 2 2006.173.02:23:46.12#ibcon#about to read 6, iclass 10, count 2 2006.173.02:23:46.12#ibcon#read 6, iclass 10, count 2 2006.173.02:23:46.12#ibcon#end of sib2, iclass 10, count 2 2006.173.02:23:46.12#ibcon#*mode == 0, iclass 10, count 2 2006.173.02:23:46.12#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.02:23:46.12#ibcon#[25=AT08-04\r\n] 2006.173.02:23:46.12#ibcon#*before write, iclass 10, count 2 2006.173.02:23:46.12#ibcon#enter sib2, iclass 10, count 2 2006.173.02:23:46.12#ibcon#flushed, iclass 10, count 2 2006.173.02:23:46.12#ibcon#about to write, iclass 10, count 2 2006.173.02:23:46.12#ibcon#wrote, iclass 10, count 2 2006.173.02:23:46.12#ibcon#about to read 3, iclass 10, count 2 2006.173.02:23:46.15#ibcon#read 3, iclass 10, count 2 2006.173.02:23:46.15#ibcon#about to read 4, iclass 10, count 2 2006.173.02:23:46.15#ibcon#read 4, iclass 10, count 2 2006.173.02:23:46.15#ibcon#about to read 5, iclass 10, count 2 2006.173.02:23:46.15#ibcon#read 5, iclass 10, count 2 2006.173.02:23:46.15#ibcon#about to read 6, iclass 10, count 2 2006.173.02:23:46.15#ibcon#read 6, iclass 10, count 2 2006.173.02:23:46.15#ibcon#end of sib2, iclass 10, count 2 2006.173.02:23:46.15#ibcon#*after write, iclass 10, count 2 2006.173.02:23:46.15#ibcon#*before return 0, iclass 10, count 2 2006.173.02:23:46.15#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.02:23:46.15#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.02:23:46.15#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.02:23:46.15#ibcon#ireg 7 cls_cnt 0 2006.173.02:23:46.15#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.02:23:46.27#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.02:23:46.27#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.02:23:46.27#ibcon#enter wrdev, iclass 10, count 0 2006.173.02:23:46.27#ibcon#first serial, iclass 10, count 0 2006.173.02:23:46.27#ibcon#enter sib2, iclass 10, count 0 2006.173.02:23:46.27#ibcon#flushed, iclass 10, count 0 2006.173.02:23:46.27#ibcon#about to write, iclass 10, count 0 2006.173.02:23:46.27#ibcon#wrote, iclass 10, count 0 2006.173.02:23:46.27#ibcon#about to read 3, iclass 10, count 0 2006.173.02:23:46.29#ibcon#read 3, iclass 10, count 0 2006.173.02:23:46.29#ibcon#about to read 4, iclass 10, count 0 2006.173.02:23:46.29#ibcon#read 4, iclass 10, count 0 2006.173.02:23:46.29#ibcon#about to read 5, iclass 10, count 0 2006.173.02:23:46.29#ibcon#read 5, iclass 10, count 0 2006.173.02:23:46.29#ibcon#about to read 6, iclass 10, count 0 2006.173.02:23:46.29#ibcon#read 6, iclass 10, count 0 2006.173.02:23:46.29#ibcon#end of sib2, iclass 10, count 0 2006.173.02:23:46.29#ibcon#*mode == 0, iclass 10, count 0 2006.173.02:23:46.29#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.02:23:46.29#ibcon#[25=USB\r\n] 2006.173.02:23:46.29#ibcon#*before write, iclass 10, count 0 2006.173.02:23:46.29#ibcon#enter sib2, iclass 10, count 0 2006.173.02:23:46.29#ibcon#flushed, iclass 10, count 0 2006.173.02:23:46.29#ibcon#about to write, iclass 10, count 0 2006.173.02:23:46.29#ibcon#wrote, iclass 10, count 0 2006.173.02:23:46.29#ibcon#about to read 3, iclass 10, count 0 2006.173.02:23:46.32#ibcon#read 3, iclass 10, count 0 2006.173.02:23:46.32#ibcon#about to read 4, iclass 10, count 0 2006.173.02:23:46.32#ibcon#read 4, iclass 10, count 0 2006.173.02:23:46.32#ibcon#about to read 5, iclass 10, count 0 2006.173.02:23:46.32#ibcon#read 5, iclass 10, count 0 2006.173.02:23:46.32#ibcon#about to read 6, iclass 10, count 0 2006.173.02:23:46.32#ibcon#read 6, iclass 10, count 0 2006.173.02:23:46.32#ibcon#end of sib2, iclass 10, count 0 2006.173.02:23:46.32#ibcon#*after write, iclass 10, count 0 2006.173.02:23:46.32#ibcon#*before return 0, iclass 10, count 0 2006.173.02:23:46.32#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.02:23:46.32#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.02:23:46.32#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.02:23:46.32#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.02:23:46.32$vck44/vblo=1,629.99 2006.173.02:23:46.32#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.02:23:46.32#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.02:23:46.32#ibcon#ireg 17 cls_cnt 0 2006.173.02:23:46.32#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.02:23:46.32#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.02:23:46.32#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.02:23:46.32#ibcon#enter wrdev, iclass 12, count 0 2006.173.02:23:46.32#ibcon#first serial, iclass 12, count 0 2006.173.02:23:46.32#ibcon#enter sib2, iclass 12, count 0 2006.173.02:23:46.32#ibcon#flushed, iclass 12, count 0 2006.173.02:23:46.32#ibcon#about to write, iclass 12, count 0 2006.173.02:23:46.32#ibcon#wrote, iclass 12, count 0 2006.173.02:23:46.32#ibcon#about to read 3, iclass 12, count 0 2006.173.02:23:46.34#ibcon#read 3, iclass 12, count 0 2006.173.02:23:46.34#ibcon#about to read 4, iclass 12, count 0 2006.173.02:23:46.34#ibcon#read 4, iclass 12, count 0 2006.173.02:23:46.34#ibcon#about to read 5, iclass 12, count 0 2006.173.02:23:46.34#ibcon#read 5, iclass 12, count 0 2006.173.02:23:46.34#ibcon#about to read 6, iclass 12, count 0 2006.173.02:23:46.34#ibcon#read 6, iclass 12, count 0 2006.173.02:23:46.34#ibcon#end of sib2, iclass 12, count 0 2006.173.02:23:46.34#ibcon#*mode == 0, iclass 12, count 0 2006.173.02:23:46.34#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.02:23:46.34#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.02:23:46.34#ibcon#*before write, iclass 12, count 0 2006.173.02:23:46.34#ibcon#enter sib2, iclass 12, count 0 2006.173.02:23:46.34#ibcon#flushed, iclass 12, count 0 2006.173.02:23:46.34#ibcon#about to write, iclass 12, count 0 2006.173.02:23:46.34#ibcon#wrote, iclass 12, count 0 2006.173.02:23:46.34#ibcon#about to read 3, iclass 12, count 0 2006.173.02:23:46.38#ibcon#read 3, iclass 12, count 0 2006.173.02:23:46.38#ibcon#about to read 4, iclass 12, count 0 2006.173.02:23:46.38#ibcon#read 4, iclass 12, count 0 2006.173.02:23:46.38#ibcon#about to read 5, iclass 12, count 0 2006.173.02:23:46.38#ibcon#read 5, iclass 12, count 0 2006.173.02:23:46.38#ibcon#about to read 6, iclass 12, count 0 2006.173.02:23:46.38#ibcon#read 6, iclass 12, count 0 2006.173.02:23:46.38#ibcon#end of sib2, iclass 12, count 0 2006.173.02:23:46.38#ibcon#*after write, iclass 12, count 0 2006.173.02:23:46.38#ibcon#*before return 0, iclass 12, count 0 2006.173.02:23:46.38#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.02:23:46.38#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.02:23:46.38#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.02:23:46.38#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.02:23:46.38$vck44/vb=1,4 2006.173.02:23:46.38#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.02:23:46.38#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.02:23:46.38#ibcon#ireg 11 cls_cnt 2 2006.173.02:23:46.38#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.02:23:46.38#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.02:23:46.38#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.02:23:46.38#ibcon#enter wrdev, iclass 14, count 2 2006.173.02:23:46.38#ibcon#first serial, iclass 14, count 2 2006.173.02:23:46.38#ibcon#enter sib2, iclass 14, count 2 2006.173.02:23:46.38#ibcon#flushed, iclass 14, count 2 2006.173.02:23:46.38#ibcon#about to write, iclass 14, count 2 2006.173.02:23:46.38#ibcon#wrote, iclass 14, count 2 2006.173.02:23:46.38#ibcon#about to read 3, iclass 14, count 2 2006.173.02:23:46.40#ibcon#read 3, iclass 14, count 2 2006.173.02:23:46.40#ibcon#about to read 4, iclass 14, count 2 2006.173.02:23:46.40#ibcon#read 4, iclass 14, count 2 2006.173.02:23:46.40#ibcon#about to read 5, iclass 14, count 2 2006.173.02:23:46.40#ibcon#read 5, iclass 14, count 2 2006.173.02:23:46.40#ibcon#about to read 6, iclass 14, count 2 2006.173.02:23:46.40#ibcon#read 6, iclass 14, count 2 2006.173.02:23:46.40#ibcon#end of sib2, iclass 14, count 2 2006.173.02:23:46.40#ibcon#*mode == 0, iclass 14, count 2 2006.173.02:23:46.40#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.02:23:46.40#ibcon#[27=AT01-04\r\n] 2006.173.02:23:46.40#ibcon#*before write, iclass 14, count 2 2006.173.02:23:46.40#ibcon#enter sib2, iclass 14, count 2 2006.173.02:23:46.40#ibcon#flushed, iclass 14, count 2 2006.173.02:23:46.40#ibcon#about to write, iclass 14, count 2 2006.173.02:23:46.40#ibcon#wrote, iclass 14, count 2 2006.173.02:23:46.40#ibcon#about to read 3, iclass 14, count 2 2006.173.02:23:46.43#ibcon#read 3, iclass 14, count 2 2006.173.02:23:46.43#ibcon#about to read 4, iclass 14, count 2 2006.173.02:23:46.43#ibcon#read 4, iclass 14, count 2 2006.173.02:23:46.43#ibcon#about to read 5, iclass 14, count 2 2006.173.02:23:46.43#ibcon#read 5, iclass 14, count 2 2006.173.02:23:46.43#ibcon#about to read 6, iclass 14, count 2 2006.173.02:23:46.43#ibcon#read 6, iclass 14, count 2 2006.173.02:23:46.43#ibcon#end of sib2, iclass 14, count 2 2006.173.02:23:46.43#ibcon#*after write, iclass 14, count 2 2006.173.02:23:46.43#ibcon#*before return 0, iclass 14, count 2 2006.173.02:23:46.43#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.02:23:46.43#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.02:23:46.43#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.02:23:46.43#ibcon#ireg 7 cls_cnt 0 2006.173.02:23:46.43#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.02:23:46.55#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.02:23:46.55#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.02:23:46.55#ibcon#enter wrdev, iclass 14, count 0 2006.173.02:23:46.55#ibcon#first serial, iclass 14, count 0 2006.173.02:23:46.55#ibcon#enter sib2, iclass 14, count 0 2006.173.02:23:46.55#ibcon#flushed, iclass 14, count 0 2006.173.02:23:46.55#ibcon#about to write, iclass 14, count 0 2006.173.02:23:46.55#ibcon#wrote, iclass 14, count 0 2006.173.02:23:46.55#ibcon#about to read 3, iclass 14, count 0 2006.173.02:23:46.57#ibcon#read 3, iclass 14, count 0 2006.173.02:23:46.57#ibcon#about to read 4, iclass 14, count 0 2006.173.02:23:46.57#ibcon#read 4, iclass 14, count 0 2006.173.02:23:46.57#ibcon#about to read 5, iclass 14, count 0 2006.173.02:23:46.57#ibcon#read 5, iclass 14, count 0 2006.173.02:23:46.57#ibcon#about to read 6, iclass 14, count 0 2006.173.02:23:46.57#ibcon#read 6, iclass 14, count 0 2006.173.02:23:46.57#ibcon#end of sib2, iclass 14, count 0 2006.173.02:23:46.57#ibcon#*mode == 0, iclass 14, count 0 2006.173.02:23:46.57#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.02:23:46.57#ibcon#[27=USB\r\n] 2006.173.02:23:46.57#ibcon#*before write, iclass 14, count 0 2006.173.02:23:46.57#ibcon#enter sib2, iclass 14, count 0 2006.173.02:23:46.57#ibcon#flushed, iclass 14, count 0 2006.173.02:23:46.57#ibcon#about to write, iclass 14, count 0 2006.173.02:23:46.57#ibcon#wrote, iclass 14, count 0 2006.173.02:23:46.57#ibcon#about to read 3, iclass 14, count 0 2006.173.02:23:46.60#ibcon#read 3, iclass 14, count 0 2006.173.02:23:46.60#ibcon#about to read 4, iclass 14, count 0 2006.173.02:23:46.60#ibcon#read 4, iclass 14, count 0 2006.173.02:23:46.60#ibcon#about to read 5, iclass 14, count 0 2006.173.02:23:46.60#ibcon#read 5, iclass 14, count 0 2006.173.02:23:46.60#ibcon#about to read 6, iclass 14, count 0 2006.173.02:23:46.60#ibcon#read 6, iclass 14, count 0 2006.173.02:23:46.60#ibcon#end of sib2, iclass 14, count 0 2006.173.02:23:46.60#ibcon#*after write, iclass 14, count 0 2006.173.02:23:46.60#ibcon#*before return 0, iclass 14, count 0 2006.173.02:23:46.60#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.02:23:46.60#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.02:23:46.60#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.02:23:46.60#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.02:23:46.60$vck44/vblo=2,634.99 2006.173.02:23:46.60#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.02:23:46.60#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.02:23:46.60#ibcon#ireg 17 cls_cnt 0 2006.173.02:23:46.60#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.02:23:46.60#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.02:23:46.60#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.02:23:46.60#ibcon#enter wrdev, iclass 16, count 0 2006.173.02:23:46.60#ibcon#first serial, iclass 16, count 0 2006.173.02:23:46.60#ibcon#enter sib2, iclass 16, count 0 2006.173.02:23:46.60#ibcon#flushed, iclass 16, count 0 2006.173.02:23:46.60#ibcon#about to write, iclass 16, count 0 2006.173.02:23:46.60#ibcon#wrote, iclass 16, count 0 2006.173.02:23:46.60#ibcon#about to read 3, iclass 16, count 0 2006.173.02:23:46.62#ibcon#read 3, iclass 16, count 0 2006.173.02:23:46.62#ibcon#about to read 4, iclass 16, count 0 2006.173.02:23:46.62#ibcon#read 4, iclass 16, count 0 2006.173.02:23:46.62#ibcon#about to read 5, iclass 16, count 0 2006.173.02:23:46.62#ibcon#read 5, iclass 16, count 0 2006.173.02:23:46.62#ibcon#about to read 6, iclass 16, count 0 2006.173.02:23:46.62#ibcon#read 6, iclass 16, count 0 2006.173.02:23:46.62#ibcon#end of sib2, iclass 16, count 0 2006.173.02:23:46.62#ibcon#*mode == 0, iclass 16, count 0 2006.173.02:23:46.62#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.02:23:46.62#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.02:23:46.62#ibcon#*before write, iclass 16, count 0 2006.173.02:23:46.62#ibcon#enter sib2, iclass 16, count 0 2006.173.02:23:46.62#ibcon#flushed, iclass 16, count 0 2006.173.02:23:46.62#ibcon#about to write, iclass 16, count 0 2006.173.02:23:46.62#ibcon#wrote, iclass 16, count 0 2006.173.02:23:46.62#ibcon#about to read 3, iclass 16, count 0 2006.173.02:23:46.66#ibcon#read 3, iclass 16, count 0 2006.173.02:23:46.66#ibcon#about to read 4, iclass 16, count 0 2006.173.02:23:46.66#ibcon#read 4, iclass 16, count 0 2006.173.02:23:46.66#ibcon#about to read 5, iclass 16, count 0 2006.173.02:23:46.66#ibcon#read 5, iclass 16, count 0 2006.173.02:23:46.66#ibcon#about to read 6, iclass 16, count 0 2006.173.02:23:46.66#ibcon#read 6, iclass 16, count 0 2006.173.02:23:46.66#ibcon#end of sib2, iclass 16, count 0 2006.173.02:23:46.66#ibcon#*after write, iclass 16, count 0 2006.173.02:23:46.66#ibcon#*before return 0, iclass 16, count 0 2006.173.02:23:46.66#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.02:23:46.66#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.02:23:46.66#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.02:23:46.66#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.02:23:46.66$vck44/vb=2,4 2006.173.02:23:46.66#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.02:23:46.66#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.02:23:46.66#ibcon#ireg 11 cls_cnt 2 2006.173.02:23:46.66#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.02:23:46.72#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.02:23:46.72#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.02:23:46.72#ibcon#enter wrdev, iclass 18, count 2 2006.173.02:23:46.72#ibcon#first serial, iclass 18, count 2 2006.173.02:23:46.72#ibcon#enter sib2, iclass 18, count 2 2006.173.02:23:46.72#ibcon#flushed, iclass 18, count 2 2006.173.02:23:46.72#ibcon#about to write, iclass 18, count 2 2006.173.02:23:46.72#ibcon#wrote, iclass 18, count 2 2006.173.02:23:46.72#ibcon#about to read 3, iclass 18, count 2 2006.173.02:23:46.74#ibcon#read 3, iclass 18, count 2 2006.173.02:23:46.74#ibcon#about to read 4, iclass 18, count 2 2006.173.02:23:46.74#ibcon#read 4, iclass 18, count 2 2006.173.02:23:46.74#ibcon#about to read 5, iclass 18, count 2 2006.173.02:23:46.74#ibcon#read 5, iclass 18, count 2 2006.173.02:23:46.74#ibcon#about to read 6, iclass 18, count 2 2006.173.02:23:46.74#ibcon#read 6, iclass 18, count 2 2006.173.02:23:46.74#ibcon#end of sib2, iclass 18, count 2 2006.173.02:23:46.74#ibcon#*mode == 0, iclass 18, count 2 2006.173.02:23:46.74#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.02:23:46.74#ibcon#[27=AT02-04\r\n] 2006.173.02:23:46.74#ibcon#*before write, iclass 18, count 2 2006.173.02:23:46.74#ibcon#enter sib2, iclass 18, count 2 2006.173.02:23:46.74#ibcon#flushed, iclass 18, count 2 2006.173.02:23:46.74#ibcon#about to write, iclass 18, count 2 2006.173.02:23:46.74#ibcon#wrote, iclass 18, count 2 2006.173.02:23:46.74#ibcon#about to read 3, iclass 18, count 2 2006.173.02:23:46.77#ibcon#read 3, iclass 18, count 2 2006.173.02:23:46.77#ibcon#about to read 4, iclass 18, count 2 2006.173.02:23:46.77#ibcon#read 4, iclass 18, count 2 2006.173.02:23:46.77#ibcon#about to read 5, iclass 18, count 2 2006.173.02:23:46.77#ibcon#read 5, iclass 18, count 2 2006.173.02:23:46.77#ibcon#about to read 6, iclass 18, count 2 2006.173.02:23:46.77#ibcon#read 6, iclass 18, count 2 2006.173.02:23:46.77#ibcon#end of sib2, iclass 18, count 2 2006.173.02:23:46.77#ibcon#*after write, iclass 18, count 2 2006.173.02:23:46.77#ibcon#*before return 0, iclass 18, count 2 2006.173.02:23:46.77#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.02:23:46.77#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.02:23:46.77#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.02:23:46.77#ibcon#ireg 7 cls_cnt 0 2006.173.02:23:46.77#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.02:23:46.89#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.02:23:46.89#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.02:23:46.89#ibcon#enter wrdev, iclass 18, count 0 2006.173.02:23:46.89#ibcon#first serial, iclass 18, count 0 2006.173.02:23:46.89#ibcon#enter sib2, iclass 18, count 0 2006.173.02:23:46.89#ibcon#flushed, iclass 18, count 0 2006.173.02:23:46.89#ibcon#about to write, iclass 18, count 0 2006.173.02:23:46.89#ibcon#wrote, iclass 18, count 0 2006.173.02:23:46.89#ibcon#about to read 3, iclass 18, count 0 2006.173.02:23:46.91#ibcon#read 3, iclass 18, count 0 2006.173.02:23:46.91#ibcon#about to read 4, iclass 18, count 0 2006.173.02:23:46.91#ibcon#read 4, iclass 18, count 0 2006.173.02:23:46.91#ibcon#about to read 5, iclass 18, count 0 2006.173.02:23:46.91#ibcon#read 5, iclass 18, count 0 2006.173.02:23:46.91#ibcon#about to read 6, iclass 18, count 0 2006.173.02:23:46.91#ibcon#read 6, iclass 18, count 0 2006.173.02:23:46.91#ibcon#end of sib2, iclass 18, count 0 2006.173.02:23:46.91#ibcon#*mode == 0, iclass 18, count 0 2006.173.02:23:46.91#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.02:23:46.91#ibcon#[27=USB\r\n] 2006.173.02:23:46.91#ibcon#*before write, iclass 18, count 0 2006.173.02:23:46.91#ibcon#enter sib2, iclass 18, count 0 2006.173.02:23:46.91#ibcon#flushed, iclass 18, count 0 2006.173.02:23:46.91#ibcon#about to write, iclass 18, count 0 2006.173.02:23:46.91#ibcon#wrote, iclass 18, count 0 2006.173.02:23:46.91#ibcon#about to read 3, iclass 18, count 0 2006.173.02:23:46.94#ibcon#read 3, iclass 18, count 0 2006.173.02:23:46.94#ibcon#about to read 4, iclass 18, count 0 2006.173.02:23:46.94#ibcon#read 4, iclass 18, count 0 2006.173.02:23:46.94#ibcon#about to read 5, iclass 18, count 0 2006.173.02:23:46.94#ibcon#read 5, iclass 18, count 0 2006.173.02:23:46.94#ibcon#about to read 6, iclass 18, count 0 2006.173.02:23:46.94#ibcon#read 6, iclass 18, count 0 2006.173.02:23:46.94#ibcon#end of sib2, iclass 18, count 0 2006.173.02:23:46.94#ibcon#*after write, iclass 18, count 0 2006.173.02:23:46.94#ibcon#*before return 0, iclass 18, count 0 2006.173.02:23:46.94#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.02:23:46.94#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.02:23:46.94#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.02:23:46.94#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.02:23:46.94$vck44/vblo=3,649.99 2006.173.02:23:46.94#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.02:23:46.94#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.02:23:46.94#ibcon#ireg 17 cls_cnt 0 2006.173.02:23:46.94#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.02:23:46.94#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.02:23:46.94#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.02:23:46.94#ibcon#enter wrdev, iclass 20, count 0 2006.173.02:23:46.94#ibcon#first serial, iclass 20, count 0 2006.173.02:23:46.94#ibcon#enter sib2, iclass 20, count 0 2006.173.02:23:46.94#ibcon#flushed, iclass 20, count 0 2006.173.02:23:46.94#ibcon#about to write, iclass 20, count 0 2006.173.02:23:46.94#ibcon#wrote, iclass 20, count 0 2006.173.02:23:46.94#ibcon#about to read 3, iclass 20, count 0 2006.173.02:23:46.96#ibcon#read 3, iclass 20, count 0 2006.173.02:23:46.96#ibcon#about to read 4, iclass 20, count 0 2006.173.02:23:46.96#ibcon#read 4, iclass 20, count 0 2006.173.02:23:46.96#ibcon#about to read 5, iclass 20, count 0 2006.173.02:23:46.96#ibcon#read 5, iclass 20, count 0 2006.173.02:23:46.96#ibcon#about to read 6, iclass 20, count 0 2006.173.02:23:46.96#ibcon#read 6, iclass 20, count 0 2006.173.02:23:46.96#ibcon#end of sib2, iclass 20, count 0 2006.173.02:23:46.96#ibcon#*mode == 0, iclass 20, count 0 2006.173.02:23:46.96#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.02:23:46.96#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.02:23:46.96#ibcon#*before write, iclass 20, count 0 2006.173.02:23:46.96#ibcon#enter sib2, iclass 20, count 0 2006.173.02:23:46.96#ibcon#flushed, iclass 20, count 0 2006.173.02:23:46.96#ibcon#about to write, iclass 20, count 0 2006.173.02:23:46.96#ibcon#wrote, iclass 20, count 0 2006.173.02:23:46.96#ibcon#about to read 3, iclass 20, count 0 2006.173.02:23:47.00#ibcon#read 3, iclass 20, count 0 2006.173.02:23:47.00#ibcon#about to read 4, iclass 20, count 0 2006.173.02:23:47.00#ibcon#read 4, iclass 20, count 0 2006.173.02:23:47.00#ibcon#about to read 5, iclass 20, count 0 2006.173.02:23:47.00#ibcon#read 5, iclass 20, count 0 2006.173.02:23:47.00#ibcon#about to read 6, iclass 20, count 0 2006.173.02:23:47.00#ibcon#read 6, iclass 20, count 0 2006.173.02:23:47.00#ibcon#end of sib2, iclass 20, count 0 2006.173.02:23:47.00#ibcon#*after write, iclass 20, count 0 2006.173.02:23:47.00#ibcon#*before return 0, iclass 20, count 0 2006.173.02:23:47.00#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.02:23:47.00#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.02:23:47.00#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.02:23:47.00#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.02:23:47.00$vck44/vb=3,4 2006.173.02:23:47.00#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.02:23:47.00#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.02:23:47.00#ibcon#ireg 11 cls_cnt 2 2006.173.02:23:47.00#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.02:23:47.06#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.02:23:47.06#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.02:23:47.06#ibcon#enter wrdev, iclass 22, count 2 2006.173.02:23:47.06#ibcon#first serial, iclass 22, count 2 2006.173.02:23:47.06#ibcon#enter sib2, iclass 22, count 2 2006.173.02:23:47.06#ibcon#flushed, iclass 22, count 2 2006.173.02:23:47.06#ibcon#about to write, iclass 22, count 2 2006.173.02:23:47.06#ibcon#wrote, iclass 22, count 2 2006.173.02:23:47.06#ibcon#about to read 3, iclass 22, count 2 2006.173.02:23:47.08#ibcon#read 3, iclass 22, count 2 2006.173.02:23:47.08#ibcon#about to read 4, iclass 22, count 2 2006.173.02:23:47.08#ibcon#read 4, iclass 22, count 2 2006.173.02:23:47.08#ibcon#about to read 5, iclass 22, count 2 2006.173.02:23:47.08#ibcon#read 5, iclass 22, count 2 2006.173.02:23:47.08#ibcon#about to read 6, iclass 22, count 2 2006.173.02:23:47.08#ibcon#read 6, iclass 22, count 2 2006.173.02:23:47.08#ibcon#end of sib2, iclass 22, count 2 2006.173.02:23:47.08#ibcon#*mode == 0, iclass 22, count 2 2006.173.02:23:47.08#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.02:23:47.08#ibcon#[27=AT03-04\r\n] 2006.173.02:23:47.08#ibcon#*before write, iclass 22, count 2 2006.173.02:23:47.08#ibcon#enter sib2, iclass 22, count 2 2006.173.02:23:47.08#ibcon#flushed, iclass 22, count 2 2006.173.02:23:47.08#ibcon#about to write, iclass 22, count 2 2006.173.02:23:47.08#ibcon#wrote, iclass 22, count 2 2006.173.02:23:47.08#ibcon#about to read 3, iclass 22, count 2 2006.173.02:23:47.11#ibcon#read 3, iclass 22, count 2 2006.173.02:23:47.11#ibcon#about to read 4, iclass 22, count 2 2006.173.02:23:47.11#ibcon#read 4, iclass 22, count 2 2006.173.02:23:47.11#ibcon#about to read 5, iclass 22, count 2 2006.173.02:23:47.11#ibcon#read 5, iclass 22, count 2 2006.173.02:23:47.11#ibcon#about to read 6, iclass 22, count 2 2006.173.02:23:47.11#ibcon#read 6, iclass 22, count 2 2006.173.02:23:47.11#ibcon#end of sib2, iclass 22, count 2 2006.173.02:23:47.11#ibcon#*after write, iclass 22, count 2 2006.173.02:23:47.11#ibcon#*before return 0, iclass 22, count 2 2006.173.02:23:47.11#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.02:23:47.11#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.02:23:47.11#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.02:23:47.11#ibcon#ireg 7 cls_cnt 0 2006.173.02:23:47.11#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.02:23:47.23#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.02:23:47.23#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.02:23:47.23#ibcon#enter wrdev, iclass 22, count 0 2006.173.02:23:47.23#ibcon#first serial, iclass 22, count 0 2006.173.02:23:47.23#ibcon#enter sib2, iclass 22, count 0 2006.173.02:23:47.23#ibcon#flushed, iclass 22, count 0 2006.173.02:23:47.23#ibcon#about to write, iclass 22, count 0 2006.173.02:23:47.23#ibcon#wrote, iclass 22, count 0 2006.173.02:23:47.23#ibcon#about to read 3, iclass 22, count 0 2006.173.02:23:47.27#ibcon#read 3, iclass 22, count 0 2006.173.02:23:47.27#ibcon#about to read 4, iclass 22, count 0 2006.173.02:23:47.27#ibcon#read 4, iclass 22, count 0 2006.173.02:23:47.27#ibcon#about to read 5, iclass 22, count 0 2006.173.02:23:47.27#ibcon#read 5, iclass 22, count 0 2006.173.02:23:47.27#ibcon#about to read 6, iclass 22, count 0 2006.173.02:23:47.27#ibcon#read 6, iclass 22, count 0 2006.173.02:23:47.27#ibcon#end of sib2, iclass 22, count 0 2006.173.02:23:47.27#ibcon#*mode == 0, iclass 22, count 0 2006.173.02:23:47.27#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.02:23:47.27#ibcon#[27=USB\r\n] 2006.173.02:23:47.27#ibcon#*before write, iclass 22, count 0 2006.173.02:23:47.27#ibcon#enter sib2, iclass 22, count 0 2006.173.02:23:47.27#ibcon#flushed, iclass 22, count 0 2006.173.02:23:47.27#ibcon#about to write, iclass 22, count 0 2006.173.02:23:47.27#ibcon#wrote, iclass 22, count 0 2006.173.02:23:47.27#ibcon#about to read 3, iclass 22, count 0 2006.173.02:23:47.30#ibcon#read 3, iclass 22, count 0 2006.173.02:23:47.30#ibcon#about to read 4, iclass 22, count 0 2006.173.02:23:47.30#ibcon#read 4, iclass 22, count 0 2006.173.02:23:47.30#ibcon#about to read 5, iclass 22, count 0 2006.173.02:23:47.30#ibcon#read 5, iclass 22, count 0 2006.173.02:23:47.30#ibcon#about to read 6, iclass 22, count 0 2006.173.02:23:47.30#ibcon#read 6, iclass 22, count 0 2006.173.02:23:47.30#ibcon#end of sib2, iclass 22, count 0 2006.173.02:23:47.30#ibcon#*after write, iclass 22, count 0 2006.173.02:23:47.30#ibcon#*before return 0, iclass 22, count 0 2006.173.02:23:47.30#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.02:23:47.30#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.02:23:47.30#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.02:23:47.30#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.02:23:47.30$vck44/vblo=4,679.99 2006.173.02:23:47.30#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.02:23:47.30#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.02:23:47.30#ibcon#ireg 17 cls_cnt 0 2006.173.02:23:47.30#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.02:23:47.30#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.02:23:47.30#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.02:23:47.30#ibcon#enter wrdev, iclass 24, count 0 2006.173.02:23:47.30#ibcon#first serial, iclass 24, count 0 2006.173.02:23:47.30#ibcon#enter sib2, iclass 24, count 0 2006.173.02:23:47.30#ibcon#flushed, iclass 24, count 0 2006.173.02:23:47.30#ibcon#about to write, iclass 24, count 0 2006.173.02:23:47.30#ibcon#wrote, iclass 24, count 0 2006.173.02:23:47.30#ibcon#about to read 3, iclass 24, count 0 2006.173.02:23:47.32#ibcon#read 3, iclass 24, count 0 2006.173.02:23:47.32#ibcon#about to read 4, iclass 24, count 0 2006.173.02:23:47.32#ibcon#read 4, iclass 24, count 0 2006.173.02:23:47.32#ibcon#about to read 5, iclass 24, count 0 2006.173.02:23:47.32#ibcon#read 5, iclass 24, count 0 2006.173.02:23:47.32#ibcon#about to read 6, iclass 24, count 0 2006.173.02:23:47.32#ibcon#read 6, iclass 24, count 0 2006.173.02:23:47.32#ibcon#end of sib2, iclass 24, count 0 2006.173.02:23:47.32#ibcon#*mode == 0, iclass 24, count 0 2006.173.02:23:47.32#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.02:23:47.32#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.02:23:47.32#ibcon#*before write, iclass 24, count 0 2006.173.02:23:47.32#ibcon#enter sib2, iclass 24, count 0 2006.173.02:23:47.32#ibcon#flushed, iclass 24, count 0 2006.173.02:23:47.32#ibcon#about to write, iclass 24, count 0 2006.173.02:23:47.32#ibcon#wrote, iclass 24, count 0 2006.173.02:23:47.32#ibcon#about to read 3, iclass 24, count 0 2006.173.02:23:47.36#ibcon#read 3, iclass 24, count 0 2006.173.02:23:47.36#ibcon#about to read 4, iclass 24, count 0 2006.173.02:23:47.36#ibcon#read 4, iclass 24, count 0 2006.173.02:23:47.36#ibcon#about to read 5, iclass 24, count 0 2006.173.02:23:47.36#ibcon#read 5, iclass 24, count 0 2006.173.02:23:47.36#ibcon#about to read 6, iclass 24, count 0 2006.173.02:23:47.36#ibcon#read 6, iclass 24, count 0 2006.173.02:23:47.36#ibcon#end of sib2, iclass 24, count 0 2006.173.02:23:47.36#ibcon#*after write, iclass 24, count 0 2006.173.02:23:47.36#ibcon#*before return 0, iclass 24, count 0 2006.173.02:23:47.36#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.02:23:47.36#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.02:23:47.36#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.02:23:47.36#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.02:23:47.36$vck44/vb=4,4 2006.173.02:23:47.36#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.02:23:47.36#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.02:23:47.36#ibcon#ireg 11 cls_cnt 2 2006.173.02:23:47.36#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.02:23:47.42#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.02:23:47.42#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.02:23:47.42#ibcon#enter wrdev, iclass 26, count 2 2006.173.02:23:47.42#ibcon#first serial, iclass 26, count 2 2006.173.02:23:47.42#ibcon#enter sib2, iclass 26, count 2 2006.173.02:23:47.42#ibcon#flushed, iclass 26, count 2 2006.173.02:23:47.42#ibcon#about to write, iclass 26, count 2 2006.173.02:23:47.42#ibcon#wrote, iclass 26, count 2 2006.173.02:23:47.42#ibcon#about to read 3, iclass 26, count 2 2006.173.02:23:47.44#ibcon#read 3, iclass 26, count 2 2006.173.02:23:47.44#ibcon#about to read 4, iclass 26, count 2 2006.173.02:23:47.44#ibcon#read 4, iclass 26, count 2 2006.173.02:23:47.44#ibcon#about to read 5, iclass 26, count 2 2006.173.02:23:47.44#ibcon#read 5, iclass 26, count 2 2006.173.02:23:47.44#ibcon#about to read 6, iclass 26, count 2 2006.173.02:23:47.44#ibcon#read 6, iclass 26, count 2 2006.173.02:23:47.44#ibcon#end of sib2, iclass 26, count 2 2006.173.02:23:47.44#ibcon#*mode == 0, iclass 26, count 2 2006.173.02:23:47.44#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.02:23:47.44#ibcon#[27=AT04-04\r\n] 2006.173.02:23:47.44#ibcon#*before write, iclass 26, count 2 2006.173.02:23:47.44#ibcon#enter sib2, iclass 26, count 2 2006.173.02:23:47.44#ibcon#flushed, iclass 26, count 2 2006.173.02:23:47.44#ibcon#about to write, iclass 26, count 2 2006.173.02:23:47.44#ibcon#wrote, iclass 26, count 2 2006.173.02:23:47.44#ibcon#about to read 3, iclass 26, count 2 2006.173.02:23:47.47#ibcon#read 3, iclass 26, count 2 2006.173.02:23:47.47#ibcon#about to read 4, iclass 26, count 2 2006.173.02:23:47.47#ibcon#read 4, iclass 26, count 2 2006.173.02:23:47.47#ibcon#about to read 5, iclass 26, count 2 2006.173.02:23:47.47#ibcon#read 5, iclass 26, count 2 2006.173.02:23:47.47#ibcon#about to read 6, iclass 26, count 2 2006.173.02:23:47.47#ibcon#read 6, iclass 26, count 2 2006.173.02:23:47.47#ibcon#end of sib2, iclass 26, count 2 2006.173.02:23:47.47#ibcon#*after write, iclass 26, count 2 2006.173.02:23:47.47#ibcon#*before return 0, iclass 26, count 2 2006.173.02:23:47.47#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.02:23:47.47#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.02:23:47.47#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.02:23:47.47#ibcon#ireg 7 cls_cnt 0 2006.173.02:23:47.47#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.02:23:47.59#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.02:23:47.59#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.02:23:47.59#ibcon#enter wrdev, iclass 26, count 0 2006.173.02:23:47.59#ibcon#first serial, iclass 26, count 0 2006.173.02:23:47.59#ibcon#enter sib2, iclass 26, count 0 2006.173.02:23:47.59#ibcon#flushed, iclass 26, count 0 2006.173.02:23:47.59#ibcon#about to write, iclass 26, count 0 2006.173.02:23:47.59#ibcon#wrote, iclass 26, count 0 2006.173.02:23:47.59#ibcon#about to read 3, iclass 26, count 0 2006.173.02:23:47.61#ibcon#read 3, iclass 26, count 0 2006.173.02:23:47.61#ibcon#about to read 4, iclass 26, count 0 2006.173.02:23:47.61#ibcon#read 4, iclass 26, count 0 2006.173.02:23:47.61#ibcon#about to read 5, iclass 26, count 0 2006.173.02:23:47.61#ibcon#read 5, iclass 26, count 0 2006.173.02:23:47.61#ibcon#about to read 6, iclass 26, count 0 2006.173.02:23:47.61#ibcon#read 6, iclass 26, count 0 2006.173.02:23:47.61#ibcon#end of sib2, iclass 26, count 0 2006.173.02:23:47.61#ibcon#*mode == 0, iclass 26, count 0 2006.173.02:23:47.61#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.02:23:47.61#ibcon#[27=USB\r\n] 2006.173.02:23:47.61#ibcon#*before write, iclass 26, count 0 2006.173.02:23:47.61#ibcon#enter sib2, iclass 26, count 0 2006.173.02:23:47.61#ibcon#flushed, iclass 26, count 0 2006.173.02:23:47.61#ibcon#about to write, iclass 26, count 0 2006.173.02:23:47.61#ibcon#wrote, iclass 26, count 0 2006.173.02:23:47.61#ibcon#about to read 3, iclass 26, count 0 2006.173.02:23:47.64#ibcon#read 3, iclass 26, count 0 2006.173.02:23:47.64#ibcon#about to read 4, iclass 26, count 0 2006.173.02:23:47.64#ibcon#read 4, iclass 26, count 0 2006.173.02:23:47.64#ibcon#about to read 5, iclass 26, count 0 2006.173.02:23:47.64#ibcon#read 5, iclass 26, count 0 2006.173.02:23:47.64#ibcon#about to read 6, iclass 26, count 0 2006.173.02:23:47.64#ibcon#read 6, iclass 26, count 0 2006.173.02:23:47.64#ibcon#end of sib2, iclass 26, count 0 2006.173.02:23:47.64#ibcon#*after write, iclass 26, count 0 2006.173.02:23:47.64#ibcon#*before return 0, iclass 26, count 0 2006.173.02:23:47.64#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.02:23:47.64#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.02:23:47.64#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.02:23:47.64#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.02:23:47.64$vck44/vblo=5,709.99 2006.173.02:23:47.64#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.02:23:47.64#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.02:23:47.64#ibcon#ireg 17 cls_cnt 0 2006.173.02:23:47.64#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.02:23:47.64#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.02:23:47.64#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.02:23:47.64#ibcon#enter wrdev, iclass 28, count 0 2006.173.02:23:47.64#ibcon#first serial, iclass 28, count 0 2006.173.02:23:47.64#ibcon#enter sib2, iclass 28, count 0 2006.173.02:23:47.64#ibcon#flushed, iclass 28, count 0 2006.173.02:23:47.64#ibcon#about to write, iclass 28, count 0 2006.173.02:23:47.64#ibcon#wrote, iclass 28, count 0 2006.173.02:23:47.64#ibcon#about to read 3, iclass 28, count 0 2006.173.02:23:47.66#ibcon#read 3, iclass 28, count 0 2006.173.02:23:47.66#ibcon#about to read 4, iclass 28, count 0 2006.173.02:23:47.66#ibcon#read 4, iclass 28, count 0 2006.173.02:23:47.66#ibcon#about to read 5, iclass 28, count 0 2006.173.02:23:47.66#ibcon#read 5, iclass 28, count 0 2006.173.02:23:47.66#ibcon#about to read 6, iclass 28, count 0 2006.173.02:23:47.66#ibcon#read 6, iclass 28, count 0 2006.173.02:23:47.66#ibcon#end of sib2, iclass 28, count 0 2006.173.02:23:47.66#ibcon#*mode == 0, iclass 28, count 0 2006.173.02:23:47.66#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.02:23:47.66#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.02:23:47.66#ibcon#*before write, iclass 28, count 0 2006.173.02:23:47.66#ibcon#enter sib2, iclass 28, count 0 2006.173.02:23:47.66#ibcon#flushed, iclass 28, count 0 2006.173.02:23:47.66#ibcon#about to write, iclass 28, count 0 2006.173.02:23:47.66#ibcon#wrote, iclass 28, count 0 2006.173.02:23:47.66#ibcon#about to read 3, iclass 28, count 0 2006.173.02:23:47.70#ibcon#read 3, iclass 28, count 0 2006.173.02:23:47.70#ibcon#about to read 4, iclass 28, count 0 2006.173.02:23:47.70#ibcon#read 4, iclass 28, count 0 2006.173.02:23:47.70#ibcon#about to read 5, iclass 28, count 0 2006.173.02:23:47.70#ibcon#read 5, iclass 28, count 0 2006.173.02:23:47.70#ibcon#about to read 6, iclass 28, count 0 2006.173.02:23:47.70#ibcon#read 6, iclass 28, count 0 2006.173.02:23:47.70#ibcon#end of sib2, iclass 28, count 0 2006.173.02:23:47.70#ibcon#*after write, iclass 28, count 0 2006.173.02:23:47.70#ibcon#*before return 0, iclass 28, count 0 2006.173.02:23:47.70#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.02:23:47.70#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.02:23:47.70#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.02:23:47.70#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.02:23:47.70$vck44/vb=5,4 2006.173.02:23:47.70#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.02:23:47.70#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.02:23:47.70#ibcon#ireg 11 cls_cnt 2 2006.173.02:23:47.70#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.02:23:47.76#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.02:23:47.76#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.02:23:47.76#ibcon#enter wrdev, iclass 30, count 2 2006.173.02:23:47.76#ibcon#first serial, iclass 30, count 2 2006.173.02:23:47.76#ibcon#enter sib2, iclass 30, count 2 2006.173.02:23:47.76#ibcon#flushed, iclass 30, count 2 2006.173.02:23:47.76#ibcon#about to write, iclass 30, count 2 2006.173.02:23:47.76#ibcon#wrote, iclass 30, count 2 2006.173.02:23:47.76#ibcon#about to read 3, iclass 30, count 2 2006.173.02:23:47.78#ibcon#read 3, iclass 30, count 2 2006.173.02:23:47.78#ibcon#about to read 4, iclass 30, count 2 2006.173.02:23:47.78#ibcon#read 4, iclass 30, count 2 2006.173.02:23:47.78#ibcon#about to read 5, iclass 30, count 2 2006.173.02:23:47.78#ibcon#read 5, iclass 30, count 2 2006.173.02:23:47.78#ibcon#about to read 6, iclass 30, count 2 2006.173.02:23:47.78#ibcon#read 6, iclass 30, count 2 2006.173.02:23:47.78#ibcon#end of sib2, iclass 30, count 2 2006.173.02:23:47.78#ibcon#*mode == 0, iclass 30, count 2 2006.173.02:23:47.78#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.02:23:47.78#ibcon#[27=AT05-04\r\n] 2006.173.02:23:47.78#ibcon#*before write, iclass 30, count 2 2006.173.02:23:47.78#ibcon#enter sib2, iclass 30, count 2 2006.173.02:23:47.78#ibcon#flushed, iclass 30, count 2 2006.173.02:23:47.78#ibcon#about to write, iclass 30, count 2 2006.173.02:23:47.78#ibcon#wrote, iclass 30, count 2 2006.173.02:23:47.78#ibcon#about to read 3, iclass 30, count 2 2006.173.02:23:47.81#ibcon#read 3, iclass 30, count 2 2006.173.02:23:47.81#ibcon#about to read 4, iclass 30, count 2 2006.173.02:23:47.81#ibcon#read 4, iclass 30, count 2 2006.173.02:23:47.81#ibcon#about to read 5, iclass 30, count 2 2006.173.02:23:47.81#ibcon#read 5, iclass 30, count 2 2006.173.02:23:47.81#ibcon#about to read 6, iclass 30, count 2 2006.173.02:23:47.81#ibcon#read 6, iclass 30, count 2 2006.173.02:23:47.81#ibcon#end of sib2, iclass 30, count 2 2006.173.02:23:47.81#ibcon#*after write, iclass 30, count 2 2006.173.02:23:47.81#ibcon#*before return 0, iclass 30, count 2 2006.173.02:23:47.81#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.02:23:47.81#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.02:23:47.81#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.02:23:47.81#ibcon#ireg 7 cls_cnt 0 2006.173.02:23:47.81#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.02:23:47.93#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.02:23:47.93#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.02:23:47.93#ibcon#enter wrdev, iclass 30, count 0 2006.173.02:23:47.93#ibcon#first serial, iclass 30, count 0 2006.173.02:23:47.93#ibcon#enter sib2, iclass 30, count 0 2006.173.02:23:47.93#ibcon#flushed, iclass 30, count 0 2006.173.02:23:47.93#ibcon#about to write, iclass 30, count 0 2006.173.02:23:47.93#ibcon#wrote, iclass 30, count 0 2006.173.02:23:47.93#ibcon#about to read 3, iclass 30, count 0 2006.173.02:23:47.95#ibcon#read 3, iclass 30, count 0 2006.173.02:23:47.95#ibcon#about to read 4, iclass 30, count 0 2006.173.02:23:47.95#ibcon#read 4, iclass 30, count 0 2006.173.02:23:47.95#ibcon#about to read 5, iclass 30, count 0 2006.173.02:23:47.95#ibcon#read 5, iclass 30, count 0 2006.173.02:23:47.95#ibcon#about to read 6, iclass 30, count 0 2006.173.02:23:47.95#ibcon#read 6, iclass 30, count 0 2006.173.02:23:47.95#ibcon#end of sib2, iclass 30, count 0 2006.173.02:23:47.95#ibcon#*mode == 0, iclass 30, count 0 2006.173.02:23:47.95#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.02:23:47.95#ibcon#[27=USB\r\n] 2006.173.02:23:47.95#ibcon#*before write, iclass 30, count 0 2006.173.02:23:47.95#ibcon#enter sib2, iclass 30, count 0 2006.173.02:23:47.95#ibcon#flushed, iclass 30, count 0 2006.173.02:23:47.95#ibcon#about to write, iclass 30, count 0 2006.173.02:23:47.95#ibcon#wrote, iclass 30, count 0 2006.173.02:23:47.95#ibcon#about to read 3, iclass 30, count 0 2006.173.02:23:47.98#ibcon#read 3, iclass 30, count 0 2006.173.02:23:47.98#ibcon#about to read 4, iclass 30, count 0 2006.173.02:23:47.98#ibcon#read 4, iclass 30, count 0 2006.173.02:23:47.98#ibcon#about to read 5, iclass 30, count 0 2006.173.02:23:47.98#ibcon#read 5, iclass 30, count 0 2006.173.02:23:47.98#ibcon#about to read 6, iclass 30, count 0 2006.173.02:23:47.98#ibcon#read 6, iclass 30, count 0 2006.173.02:23:47.98#ibcon#end of sib2, iclass 30, count 0 2006.173.02:23:47.98#ibcon#*after write, iclass 30, count 0 2006.173.02:23:47.98#ibcon#*before return 0, iclass 30, count 0 2006.173.02:23:47.98#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.02:23:47.98#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.02:23:47.98#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.02:23:47.98#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.02:23:47.98$vck44/vblo=6,719.99 2006.173.02:23:47.98#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.02:23:47.98#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.02:23:47.98#ibcon#ireg 17 cls_cnt 0 2006.173.02:23:47.98#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.02:23:47.98#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.02:23:47.98#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.02:23:47.98#ibcon#enter wrdev, iclass 32, count 0 2006.173.02:23:47.98#ibcon#first serial, iclass 32, count 0 2006.173.02:23:47.98#ibcon#enter sib2, iclass 32, count 0 2006.173.02:23:47.98#ibcon#flushed, iclass 32, count 0 2006.173.02:23:47.98#ibcon#about to write, iclass 32, count 0 2006.173.02:23:47.98#ibcon#wrote, iclass 32, count 0 2006.173.02:23:47.98#ibcon#about to read 3, iclass 32, count 0 2006.173.02:23:48.00#ibcon#read 3, iclass 32, count 0 2006.173.02:23:48.00#ibcon#about to read 4, iclass 32, count 0 2006.173.02:23:48.00#ibcon#read 4, iclass 32, count 0 2006.173.02:23:48.00#ibcon#about to read 5, iclass 32, count 0 2006.173.02:23:48.00#ibcon#read 5, iclass 32, count 0 2006.173.02:23:48.00#ibcon#about to read 6, iclass 32, count 0 2006.173.02:23:48.00#ibcon#read 6, iclass 32, count 0 2006.173.02:23:48.00#ibcon#end of sib2, iclass 32, count 0 2006.173.02:23:48.00#ibcon#*mode == 0, iclass 32, count 0 2006.173.02:23:48.00#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.02:23:48.00#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.02:23:48.00#ibcon#*before write, iclass 32, count 0 2006.173.02:23:48.00#ibcon#enter sib2, iclass 32, count 0 2006.173.02:23:48.00#ibcon#flushed, iclass 32, count 0 2006.173.02:23:48.00#ibcon#about to write, iclass 32, count 0 2006.173.02:23:48.00#ibcon#wrote, iclass 32, count 0 2006.173.02:23:48.00#ibcon#about to read 3, iclass 32, count 0 2006.173.02:23:48.04#ibcon#read 3, iclass 32, count 0 2006.173.02:23:48.04#ibcon#about to read 4, iclass 32, count 0 2006.173.02:23:48.04#ibcon#read 4, iclass 32, count 0 2006.173.02:23:48.04#ibcon#about to read 5, iclass 32, count 0 2006.173.02:23:48.04#ibcon#read 5, iclass 32, count 0 2006.173.02:23:48.04#ibcon#about to read 6, iclass 32, count 0 2006.173.02:23:48.04#ibcon#read 6, iclass 32, count 0 2006.173.02:23:48.04#ibcon#end of sib2, iclass 32, count 0 2006.173.02:23:48.04#ibcon#*after write, iclass 32, count 0 2006.173.02:23:48.04#ibcon#*before return 0, iclass 32, count 0 2006.173.02:23:48.04#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.02:23:48.04#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.02:23:48.04#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.02:23:48.04#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.02:23:48.04$vck44/vb=6,4 2006.173.02:23:48.04#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.02:23:48.04#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.02:23:48.04#ibcon#ireg 11 cls_cnt 2 2006.173.02:23:48.04#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.02:23:48.11#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.02:23:48.11#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.02:23:48.11#ibcon#enter wrdev, iclass 34, count 2 2006.173.02:23:48.11#ibcon#first serial, iclass 34, count 2 2006.173.02:23:48.11#ibcon#enter sib2, iclass 34, count 2 2006.173.02:23:48.11#ibcon#flushed, iclass 34, count 2 2006.173.02:23:48.11#ibcon#about to write, iclass 34, count 2 2006.173.02:23:48.11#ibcon#wrote, iclass 34, count 2 2006.173.02:23:48.11#ibcon#about to read 3, iclass 34, count 2 2006.173.02:23:48.12#ibcon#read 3, iclass 34, count 2 2006.173.02:23:48.12#ibcon#about to read 4, iclass 34, count 2 2006.173.02:23:48.12#ibcon#read 4, iclass 34, count 2 2006.173.02:23:48.12#ibcon#about to read 5, iclass 34, count 2 2006.173.02:23:48.12#ibcon#read 5, iclass 34, count 2 2006.173.02:23:48.12#ibcon#about to read 6, iclass 34, count 2 2006.173.02:23:48.12#ibcon#read 6, iclass 34, count 2 2006.173.02:23:48.12#ibcon#end of sib2, iclass 34, count 2 2006.173.02:23:48.12#ibcon#*mode == 0, iclass 34, count 2 2006.173.02:23:48.12#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.02:23:48.12#ibcon#[27=AT06-04\r\n] 2006.173.02:23:48.12#ibcon#*before write, iclass 34, count 2 2006.173.02:23:48.12#ibcon#enter sib2, iclass 34, count 2 2006.173.02:23:48.12#ibcon#flushed, iclass 34, count 2 2006.173.02:23:48.12#ibcon#about to write, iclass 34, count 2 2006.173.02:23:48.12#ibcon#wrote, iclass 34, count 2 2006.173.02:23:48.12#ibcon#about to read 3, iclass 34, count 2 2006.173.02:23:48.15#ibcon#read 3, iclass 34, count 2 2006.173.02:23:48.15#ibcon#about to read 4, iclass 34, count 2 2006.173.02:23:48.15#ibcon#read 4, iclass 34, count 2 2006.173.02:23:48.15#ibcon#about to read 5, iclass 34, count 2 2006.173.02:23:48.15#ibcon#read 5, iclass 34, count 2 2006.173.02:23:48.15#ibcon#about to read 6, iclass 34, count 2 2006.173.02:23:48.15#ibcon#read 6, iclass 34, count 2 2006.173.02:23:48.15#ibcon#end of sib2, iclass 34, count 2 2006.173.02:23:48.15#ibcon#*after write, iclass 34, count 2 2006.173.02:23:48.15#ibcon#*before return 0, iclass 34, count 2 2006.173.02:23:48.15#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.02:23:48.15#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.02:23:48.15#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.02:23:48.15#ibcon#ireg 7 cls_cnt 0 2006.173.02:23:48.15#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.02:23:48.27#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.02:23:48.27#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.02:23:48.27#ibcon#enter wrdev, iclass 34, count 0 2006.173.02:23:48.27#ibcon#first serial, iclass 34, count 0 2006.173.02:23:48.27#ibcon#enter sib2, iclass 34, count 0 2006.173.02:23:48.27#ibcon#flushed, iclass 34, count 0 2006.173.02:23:48.27#ibcon#about to write, iclass 34, count 0 2006.173.02:23:48.27#ibcon#wrote, iclass 34, count 0 2006.173.02:23:48.27#ibcon#about to read 3, iclass 34, count 0 2006.173.02:23:48.29#ibcon#read 3, iclass 34, count 0 2006.173.02:23:48.29#ibcon#about to read 4, iclass 34, count 0 2006.173.02:23:48.29#ibcon#read 4, iclass 34, count 0 2006.173.02:23:48.29#ibcon#about to read 5, iclass 34, count 0 2006.173.02:23:48.29#ibcon#read 5, iclass 34, count 0 2006.173.02:23:48.29#ibcon#about to read 6, iclass 34, count 0 2006.173.02:23:48.29#ibcon#read 6, iclass 34, count 0 2006.173.02:23:48.29#ibcon#end of sib2, iclass 34, count 0 2006.173.02:23:48.29#ibcon#*mode == 0, iclass 34, count 0 2006.173.02:23:48.29#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.02:23:48.29#ibcon#[27=USB\r\n] 2006.173.02:23:48.29#ibcon#*before write, iclass 34, count 0 2006.173.02:23:48.29#ibcon#enter sib2, iclass 34, count 0 2006.173.02:23:48.29#ibcon#flushed, iclass 34, count 0 2006.173.02:23:48.29#ibcon#about to write, iclass 34, count 0 2006.173.02:23:48.29#ibcon#wrote, iclass 34, count 0 2006.173.02:23:48.29#ibcon#about to read 3, iclass 34, count 0 2006.173.02:23:48.32#ibcon#read 3, iclass 34, count 0 2006.173.02:23:48.32#ibcon#about to read 4, iclass 34, count 0 2006.173.02:23:48.32#ibcon#read 4, iclass 34, count 0 2006.173.02:23:48.32#ibcon#about to read 5, iclass 34, count 0 2006.173.02:23:48.32#ibcon#read 5, iclass 34, count 0 2006.173.02:23:48.32#ibcon#about to read 6, iclass 34, count 0 2006.173.02:23:48.32#ibcon#read 6, iclass 34, count 0 2006.173.02:23:48.32#ibcon#end of sib2, iclass 34, count 0 2006.173.02:23:48.32#ibcon#*after write, iclass 34, count 0 2006.173.02:23:48.32#ibcon#*before return 0, iclass 34, count 0 2006.173.02:23:48.32#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.02:23:48.32#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.02:23:48.32#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.02:23:48.32#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.02:23:48.32$vck44/vblo=7,734.99 2006.173.02:23:48.32#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.02:23:48.32#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.02:23:48.32#ibcon#ireg 17 cls_cnt 0 2006.173.02:23:48.32#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.02:23:48.32#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.02:23:48.32#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.02:23:48.32#ibcon#enter wrdev, iclass 36, count 0 2006.173.02:23:48.32#ibcon#first serial, iclass 36, count 0 2006.173.02:23:48.32#ibcon#enter sib2, iclass 36, count 0 2006.173.02:23:48.32#ibcon#flushed, iclass 36, count 0 2006.173.02:23:48.32#ibcon#about to write, iclass 36, count 0 2006.173.02:23:48.32#ibcon#wrote, iclass 36, count 0 2006.173.02:23:48.32#ibcon#about to read 3, iclass 36, count 0 2006.173.02:23:48.34#ibcon#read 3, iclass 36, count 0 2006.173.02:23:48.34#ibcon#about to read 4, iclass 36, count 0 2006.173.02:23:48.34#ibcon#read 4, iclass 36, count 0 2006.173.02:23:48.34#ibcon#about to read 5, iclass 36, count 0 2006.173.02:23:48.34#ibcon#read 5, iclass 36, count 0 2006.173.02:23:48.34#ibcon#about to read 6, iclass 36, count 0 2006.173.02:23:48.34#ibcon#read 6, iclass 36, count 0 2006.173.02:23:48.34#ibcon#end of sib2, iclass 36, count 0 2006.173.02:23:48.34#ibcon#*mode == 0, iclass 36, count 0 2006.173.02:23:48.34#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.02:23:48.34#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.02:23:48.34#ibcon#*before write, iclass 36, count 0 2006.173.02:23:48.34#ibcon#enter sib2, iclass 36, count 0 2006.173.02:23:48.34#ibcon#flushed, iclass 36, count 0 2006.173.02:23:48.34#ibcon#about to write, iclass 36, count 0 2006.173.02:23:48.34#ibcon#wrote, iclass 36, count 0 2006.173.02:23:48.34#ibcon#about to read 3, iclass 36, count 0 2006.173.02:23:48.38#ibcon#read 3, iclass 36, count 0 2006.173.02:23:48.38#ibcon#about to read 4, iclass 36, count 0 2006.173.02:23:48.38#ibcon#read 4, iclass 36, count 0 2006.173.02:23:48.38#ibcon#about to read 5, iclass 36, count 0 2006.173.02:23:48.38#ibcon#read 5, iclass 36, count 0 2006.173.02:23:48.38#ibcon#about to read 6, iclass 36, count 0 2006.173.02:23:48.38#ibcon#read 6, iclass 36, count 0 2006.173.02:23:48.38#ibcon#end of sib2, iclass 36, count 0 2006.173.02:23:48.38#ibcon#*after write, iclass 36, count 0 2006.173.02:23:48.38#ibcon#*before return 0, iclass 36, count 0 2006.173.02:23:48.38#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.02:23:48.38#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.02:23:48.38#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.02:23:48.38#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.02:23:48.38$vck44/vb=7,4 2006.173.02:23:48.38#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.02:23:48.38#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.02:23:48.38#ibcon#ireg 11 cls_cnt 2 2006.173.02:23:48.38#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.02:23:48.44#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.02:23:48.44#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.02:23:48.44#ibcon#enter wrdev, iclass 38, count 2 2006.173.02:23:48.44#ibcon#first serial, iclass 38, count 2 2006.173.02:23:48.44#ibcon#enter sib2, iclass 38, count 2 2006.173.02:23:48.44#ibcon#flushed, iclass 38, count 2 2006.173.02:23:48.44#ibcon#about to write, iclass 38, count 2 2006.173.02:23:48.44#ibcon#wrote, iclass 38, count 2 2006.173.02:23:48.44#ibcon#about to read 3, iclass 38, count 2 2006.173.02:23:48.46#ibcon#read 3, iclass 38, count 2 2006.173.02:23:48.46#ibcon#about to read 4, iclass 38, count 2 2006.173.02:23:48.46#ibcon#read 4, iclass 38, count 2 2006.173.02:23:48.46#ibcon#about to read 5, iclass 38, count 2 2006.173.02:23:48.46#ibcon#read 5, iclass 38, count 2 2006.173.02:23:48.46#ibcon#about to read 6, iclass 38, count 2 2006.173.02:23:48.46#ibcon#read 6, iclass 38, count 2 2006.173.02:23:48.46#ibcon#end of sib2, iclass 38, count 2 2006.173.02:23:48.46#ibcon#*mode == 0, iclass 38, count 2 2006.173.02:23:48.46#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.02:23:48.46#ibcon#[27=AT07-04\r\n] 2006.173.02:23:48.46#ibcon#*before write, iclass 38, count 2 2006.173.02:23:48.46#ibcon#enter sib2, iclass 38, count 2 2006.173.02:23:48.46#ibcon#flushed, iclass 38, count 2 2006.173.02:23:48.46#ibcon#about to write, iclass 38, count 2 2006.173.02:23:48.46#ibcon#wrote, iclass 38, count 2 2006.173.02:23:48.46#ibcon#about to read 3, iclass 38, count 2 2006.173.02:23:48.49#ibcon#read 3, iclass 38, count 2 2006.173.02:23:48.49#ibcon#about to read 4, iclass 38, count 2 2006.173.02:23:48.49#ibcon#read 4, iclass 38, count 2 2006.173.02:23:48.49#ibcon#about to read 5, iclass 38, count 2 2006.173.02:23:48.49#ibcon#read 5, iclass 38, count 2 2006.173.02:23:48.49#ibcon#about to read 6, iclass 38, count 2 2006.173.02:23:48.49#ibcon#read 6, iclass 38, count 2 2006.173.02:23:48.49#ibcon#end of sib2, iclass 38, count 2 2006.173.02:23:48.49#ibcon#*after write, iclass 38, count 2 2006.173.02:23:48.49#ibcon#*before return 0, iclass 38, count 2 2006.173.02:23:48.49#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.02:23:48.49#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.02:23:48.49#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.02:23:48.49#ibcon#ireg 7 cls_cnt 0 2006.173.02:23:48.49#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.02:23:48.61#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.02:23:48.61#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.02:23:48.61#ibcon#enter wrdev, iclass 38, count 0 2006.173.02:23:48.61#ibcon#first serial, iclass 38, count 0 2006.173.02:23:48.61#ibcon#enter sib2, iclass 38, count 0 2006.173.02:23:48.61#ibcon#flushed, iclass 38, count 0 2006.173.02:23:48.61#ibcon#about to write, iclass 38, count 0 2006.173.02:23:48.61#ibcon#wrote, iclass 38, count 0 2006.173.02:23:48.61#ibcon#about to read 3, iclass 38, count 0 2006.173.02:23:48.63#ibcon#read 3, iclass 38, count 0 2006.173.02:23:48.63#ibcon#about to read 4, iclass 38, count 0 2006.173.02:23:48.63#ibcon#read 4, iclass 38, count 0 2006.173.02:23:48.63#ibcon#about to read 5, iclass 38, count 0 2006.173.02:23:48.63#ibcon#read 5, iclass 38, count 0 2006.173.02:23:48.63#ibcon#about to read 6, iclass 38, count 0 2006.173.02:23:48.63#ibcon#read 6, iclass 38, count 0 2006.173.02:23:48.63#ibcon#end of sib2, iclass 38, count 0 2006.173.02:23:48.63#ibcon#*mode == 0, iclass 38, count 0 2006.173.02:23:48.63#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.02:23:48.63#ibcon#[27=USB\r\n] 2006.173.02:23:48.63#ibcon#*before write, iclass 38, count 0 2006.173.02:23:48.63#ibcon#enter sib2, iclass 38, count 0 2006.173.02:23:48.63#ibcon#flushed, iclass 38, count 0 2006.173.02:23:48.63#ibcon#about to write, iclass 38, count 0 2006.173.02:23:48.63#ibcon#wrote, iclass 38, count 0 2006.173.02:23:48.63#ibcon#about to read 3, iclass 38, count 0 2006.173.02:23:48.66#ibcon#read 3, iclass 38, count 0 2006.173.02:23:48.66#ibcon#about to read 4, iclass 38, count 0 2006.173.02:23:48.66#ibcon#read 4, iclass 38, count 0 2006.173.02:23:48.66#ibcon#about to read 5, iclass 38, count 0 2006.173.02:23:48.66#ibcon#read 5, iclass 38, count 0 2006.173.02:23:48.66#ibcon#about to read 6, iclass 38, count 0 2006.173.02:23:48.66#ibcon#read 6, iclass 38, count 0 2006.173.02:23:48.66#ibcon#end of sib2, iclass 38, count 0 2006.173.02:23:48.66#ibcon#*after write, iclass 38, count 0 2006.173.02:23:48.66#ibcon#*before return 0, iclass 38, count 0 2006.173.02:23:48.66#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.02:23:48.66#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.02:23:48.66#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.02:23:48.66#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.02:23:48.66$vck44/vblo=8,744.99 2006.173.02:23:48.66#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.02:23:48.66#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.02:23:48.66#ibcon#ireg 17 cls_cnt 0 2006.173.02:23:48.66#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.02:23:48.66#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.02:23:48.66#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.02:23:48.66#ibcon#enter wrdev, iclass 40, count 0 2006.173.02:23:48.66#ibcon#first serial, iclass 40, count 0 2006.173.02:23:48.66#ibcon#enter sib2, iclass 40, count 0 2006.173.02:23:48.66#ibcon#flushed, iclass 40, count 0 2006.173.02:23:48.66#ibcon#about to write, iclass 40, count 0 2006.173.02:23:48.66#ibcon#wrote, iclass 40, count 0 2006.173.02:23:48.66#ibcon#about to read 3, iclass 40, count 0 2006.173.02:23:48.68#ibcon#read 3, iclass 40, count 0 2006.173.02:23:48.68#ibcon#about to read 4, iclass 40, count 0 2006.173.02:23:48.68#ibcon#read 4, iclass 40, count 0 2006.173.02:23:48.68#ibcon#about to read 5, iclass 40, count 0 2006.173.02:23:48.68#ibcon#read 5, iclass 40, count 0 2006.173.02:23:48.68#ibcon#about to read 6, iclass 40, count 0 2006.173.02:23:48.68#ibcon#read 6, iclass 40, count 0 2006.173.02:23:48.68#ibcon#end of sib2, iclass 40, count 0 2006.173.02:23:48.68#ibcon#*mode == 0, iclass 40, count 0 2006.173.02:23:48.68#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.02:23:48.68#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.02:23:48.68#ibcon#*before write, iclass 40, count 0 2006.173.02:23:48.68#ibcon#enter sib2, iclass 40, count 0 2006.173.02:23:48.68#ibcon#flushed, iclass 40, count 0 2006.173.02:23:48.68#ibcon#about to write, iclass 40, count 0 2006.173.02:23:48.68#ibcon#wrote, iclass 40, count 0 2006.173.02:23:48.68#ibcon#about to read 3, iclass 40, count 0 2006.173.02:23:48.72#ibcon#read 3, iclass 40, count 0 2006.173.02:23:48.72#ibcon#about to read 4, iclass 40, count 0 2006.173.02:23:48.72#ibcon#read 4, iclass 40, count 0 2006.173.02:23:48.72#ibcon#about to read 5, iclass 40, count 0 2006.173.02:23:48.72#ibcon#read 5, iclass 40, count 0 2006.173.02:23:48.72#ibcon#about to read 6, iclass 40, count 0 2006.173.02:23:48.72#ibcon#read 6, iclass 40, count 0 2006.173.02:23:48.72#ibcon#end of sib2, iclass 40, count 0 2006.173.02:23:48.72#ibcon#*after write, iclass 40, count 0 2006.173.02:23:48.72#ibcon#*before return 0, iclass 40, count 0 2006.173.02:23:48.72#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.02:23:48.72#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.02:23:48.72#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.02:23:48.72#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.02:23:48.72$vck44/vb=8,4 2006.173.02:23:48.72#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.02:23:48.72#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.02:23:48.72#ibcon#ireg 11 cls_cnt 2 2006.173.02:23:48.72#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.02:23:48.79#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.02:23:48.79#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.02:23:48.79#ibcon#enter wrdev, iclass 4, count 2 2006.173.02:23:48.79#ibcon#first serial, iclass 4, count 2 2006.173.02:23:48.79#ibcon#enter sib2, iclass 4, count 2 2006.173.02:23:48.79#ibcon#flushed, iclass 4, count 2 2006.173.02:23:48.79#ibcon#about to write, iclass 4, count 2 2006.173.02:23:48.79#ibcon#wrote, iclass 4, count 2 2006.173.02:23:48.79#ibcon#about to read 3, iclass 4, count 2 2006.173.02:23:48.80#ibcon#read 3, iclass 4, count 2 2006.173.02:23:48.80#ibcon#about to read 4, iclass 4, count 2 2006.173.02:23:48.80#ibcon#read 4, iclass 4, count 2 2006.173.02:23:48.80#ibcon#about to read 5, iclass 4, count 2 2006.173.02:23:48.80#ibcon#read 5, iclass 4, count 2 2006.173.02:23:48.80#ibcon#about to read 6, iclass 4, count 2 2006.173.02:23:48.80#ibcon#read 6, iclass 4, count 2 2006.173.02:23:48.80#ibcon#end of sib2, iclass 4, count 2 2006.173.02:23:48.80#ibcon#*mode == 0, iclass 4, count 2 2006.173.02:23:48.80#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.02:23:48.80#ibcon#[27=AT08-04\r\n] 2006.173.02:23:48.80#ibcon#*before write, iclass 4, count 2 2006.173.02:23:48.80#ibcon#enter sib2, iclass 4, count 2 2006.173.02:23:48.80#ibcon#flushed, iclass 4, count 2 2006.173.02:23:48.80#ibcon#about to write, iclass 4, count 2 2006.173.02:23:48.80#ibcon#wrote, iclass 4, count 2 2006.173.02:23:48.80#ibcon#about to read 3, iclass 4, count 2 2006.173.02:23:48.83#ibcon#read 3, iclass 4, count 2 2006.173.02:23:48.83#ibcon#about to read 4, iclass 4, count 2 2006.173.02:23:48.83#ibcon#read 4, iclass 4, count 2 2006.173.02:23:48.83#ibcon#about to read 5, iclass 4, count 2 2006.173.02:23:48.83#ibcon#read 5, iclass 4, count 2 2006.173.02:23:48.83#ibcon#about to read 6, iclass 4, count 2 2006.173.02:23:48.83#ibcon#read 6, iclass 4, count 2 2006.173.02:23:48.83#ibcon#end of sib2, iclass 4, count 2 2006.173.02:23:48.83#ibcon#*after write, iclass 4, count 2 2006.173.02:23:48.83#ibcon#*before return 0, iclass 4, count 2 2006.173.02:23:48.83#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.02:23:48.83#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.02:23:48.83#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.02:23:48.83#ibcon#ireg 7 cls_cnt 0 2006.173.02:23:48.83#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.02:23:48.95#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.02:23:48.95#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.02:23:48.95#ibcon#enter wrdev, iclass 4, count 0 2006.173.02:23:48.95#ibcon#first serial, iclass 4, count 0 2006.173.02:23:48.95#ibcon#enter sib2, iclass 4, count 0 2006.173.02:23:48.95#ibcon#flushed, iclass 4, count 0 2006.173.02:23:48.95#ibcon#about to write, iclass 4, count 0 2006.173.02:23:48.95#ibcon#wrote, iclass 4, count 0 2006.173.02:23:48.95#ibcon#about to read 3, iclass 4, count 0 2006.173.02:23:48.97#ibcon#read 3, iclass 4, count 0 2006.173.02:23:48.97#ibcon#about to read 4, iclass 4, count 0 2006.173.02:23:48.97#ibcon#read 4, iclass 4, count 0 2006.173.02:23:48.97#ibcon#about to read 5, iclass 4, count 0 2006.173.02:23:48.97#ibcon#read 5, iclass 4, count 0 2006.173.02:23:48.97#ibcon#about to read 6, iclass 4, count 0 2006.173.02:23:48.97#ibcon#read 6, iclass 4, count 0 2006.173.02:23:48.97#ibcon#end of sib2, iclass 4, count 0 2006.173.02:23:48.97#ibcon#*mode == 0, iclass 4, count 0 2006.173.02:23:48.97#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.02:23:48.97#ibcon#[27=USB\r\n] 2006.173.02:23:48.97#ibcon#*before write, iclass 4, count 0 2006.173.02:23:48.97#ibcon#enter sib2, iclass 4, count 0 2006.173.02:23:48.97#ibcon#flushed, iclass 4, count 0 2006.173.02:23:48.97#ibcon#about to write, iclass 4, count 0 2006.173.02:23:48.97#ibcon#wrote, iclass 4, count 0 2006.173.02:23:48.97#ibcon#about to read 3, iclass 4, count 0 2006.173.02:23:49.00#ibcon#read 3, iclass 4, count 0 2006.173.02:23:49.00#ibcon#about to read 4, iclass 4, count 0 2006.173.02:23:49.00#ibcon#read 4, iclass 4, count 0 2006.173.02:23:49.00#ibcon#about to read 5, iclass 4, count 0 2006.173.02:23:49.00#ibcon#read 5, iclass 4, count 0 2006.173.02:23:49.00#ibcon#about to read 6, iclass 4, count 0 2006.173.02:23:49.00#ibcon#read 6, iclass 4, count 0 2006.173.02:23:49.00#ibcon#end of sib2, iclass 4, count 0 2006.173.02:23:49.00#ibcon#*after write, iclass 4, count 0 2006.173.02:23:49.00#ibcon#*before return 0, iclass 4, count 0 2006.173.02:23:49.00#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.02:23:49.00#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.02:23:49.00#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.02:23:49.00#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.02:23:49.00$vck44/vabw=wide 2006.173.02:23:49.00#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.02:23:49.00#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.02:23:49.00#ibcon#ireg 8 cls_cnt 0 2006.173.02:23:49.00#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.02:23:49.00#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.02:23:49.00#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.02:23:49.00#ibcon#enter wrdev, iclass 6, count 0 2006.173.02:23:49.00#ibcon#first serial, iclass 6, count 0 2006.173.02:23:49.00#ibcon#enter sib2, iclass 6, count 0 2006.173.02:23:49.00#ibcon#flushed, iclass 6, count 0 2006.173.02:23:49.00#ibcon#about to write, iclass 6, count 0 2006.173.02:23:49.00#ibcon#wrote, iclass 6, count 0 2006.173.02:23:49.00#ibcon#about to read 3, iclass 6, count 0 2006.173.02:23:49.02#ibcon#read 3, iclass 6, count 0 2006.173.02:23:49.02#ibcon#about to read 4, iclass 6, count 0 2006.173.02:23:49.02#ibcon#read 4, iclass 6, count 0 2006.173.02:23:49.02#ibcon#about to read 5, iclass 6, count 0 2006.173.02:23:49.02#ibcon#read 5, iclass 6, count 0 2006.173.02:23:49.02#ibcon#about to read 6, iclass 6, count 0 2006.173.02:23:49.02#ibcon#read 6, iclass 6, count 0 2006.173.02:23:49.02#ibcon#end of sib2, iclass 6, count 0 2006.173.02:23:49.02#ibcon#*mode == 0, iclass 6, count 0 2006.173.02:23:49.02#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.02:23:49.02#ibcon#[25=BW32\r\n] 2006.173.02:23:49.02#ibcon#*before write, iclass 6, count 0 2006.173.02:23:49.02#ibcon#enter sib2, iclass 6, count 0 2006.173.02:23:49.02#ibcon#flushed, iclass 6, count 0 2006.173.02:23:49.02#ibcon#about to write, iclass 6, count 0 2006.173.02:23:49.02#ibcon#wrote, iclass 6, count 0 2006.173.02:23:49.02#ibcon#about to read 3, iclass 6, count 0 2006.173.02:23:49.05#ibcon#read 3, iclass 6, count 0 2006.173.02:23:49.05#ibcon#about to read 4, iclass 6, count 0 2006.173.02:23:49.05#ibcon#read 4, iclass 6, count 0 2006.173.02:23:49.05#ibcon#about to read 5, iclass 6, count 0 2006.173.02:23:49.05#ibcon#read 5, iclass 6, count 0 2006.173.02:23:49.05#ibcon#about to read 6, iclass 6, count 0 2006.173.02:23:49.05#ibcon#read 6, iclass 6, count 0 2006.173.02:23:49.05#ibcon#end of sib2, iclass 6, count 0 2006.173.02:23:49.05#ibcon#*after write, iclass 6, count 0 2006.173.02:23:49.05#ibcon#*before return 0, iclass 6, count 0 2006.173.02:23:49.05#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.02:23:49.05#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.02:23:49.05#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.02:23:49.05#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.02:23:49.05$vck44/vbbw=wide 2006.173.02:23:49.05#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.02:23:49.05#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.02:23:49.05#ibcon#ireg 8 cls_cnt 0 2006.173.02:23:49.05#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.02:23:49.13#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.02:23:49.13#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.02:23:49.13#ibcon#enter wrdev, iclass 10, count 0 2006.173.02:23:49.13#ibcon#first serial, iclass 10, count 0 2006.173.02:23:49.13#ibcon#enter sib2, iclass 10, count 0 2006.173.02:23:49.13#ibcon#flushed, iclass 10, count 0 2006.173.02:23:49.13#ibcon#about to write, iclass 10, count 0 2006.173.02:23:49.13#ibcon#wrote, iclass 10, count 0 2006.173.02:23:49.13#ibcon#about to read 3, iclass 10, count 0 2006.173.02:23:49.14#ibcon#read 3, iclass 10, count 0 2006.173.02:23:49.14#ibcon#about to read 4, iclass 10, count 0 2006.173.02:23:49.14#ibcon#read 4, iclass 10, count 0 2006.173.02:23:49.14#ibcon#about to read 5, iclass 10, count 0 2006.173.02:23:49.14#ibcon#read 5, iclass 10, count 0 2006.173.02:23:49.14#ibcon#about to read 6, iclass 10, count 0 2006.173.02:23:49.14#ibcon#read 6, iclass 10, count 0 2006.173.02:23:49.14#ibcon#end of sib2, iclass 10, count 0 2006.173.02:23:49.14#ibcon#*mode == 0, iclass 10, count 0 2006.173.02:23:49.14#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.02:23:49.14#ibcon#[27=BW32\r\n] 2006.173.02:23:49.14#ibcon#*before write, iclass 10, count 0 2006.173.02:23:49.14#ibcon#enter sib2, iclass 10, count 0 2006.173.02:23:49.14#ibcon#flushed, iclass 10, count 0 2006.173.02:23:49.14#ibcon#about to write, iclass 10, count 0 2006.173.02:23:49.14#ibcon#wrote, iclass 10, count 0 2006.173.02:23:49.14#ibcon#about to read 3, iclass 10, count 0 2006.173.02:23:49.17#ibcon#read 3, iclass 10, count 0 2006.173.02:23:49.17#ibcon#about to read 4, iclass 10, count 0 2006.173.02:23:49.17#ibcon#read 4, iclass 10, count 0 2006.173.02:23:49.17#ibcon#about to read 5, iclass 10, count 0 2006.173.02:23:49.17#ibcon#read 5, iclass 10, count 0 2006.173.02:23:49.17#ibcon#about to read 6, iclass 10, count 0 2006.173.02:23:49.17#ibcon#read 6, iclass 10, count 0 2006.173.02:23:49.17#ibcon#end of sib2, iclass 10, count 0 2006.173.02:23:49.17#ibcon#*after write, iclass 10, count 0 2006.173.02:23:49.17#ibcon#*before return 0, iclass 10, count 0 2006.173.02:23:49.17#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.02:23:49.17#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.02:23:49.17#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.02:23:49.17#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.02:23:49.17$setupk4/ifdk4 2006.173.02:23:49.17$ifdk4/lo= 2006.173.02:23:49.17$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.02:23:49.17$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.02:23:49.17$ifdk4/patch= 2006.173.02:23:49.17$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.02:23:49.17$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.02:23:49.17$setupk4/!*+20s 2006.173.02:23:52.76#abcon#<5=/15 1.1 2.1 22.60 771006.5\r\n> 2006.173.02:23:52.78#abcon#{5=INTERFACE CLEAR} 2006.173.02:23:52.85#abcon#[5=S1D000X0/0*\r\n] 2006.173.02:24:01.14#trakl#Source acquired 2006.173.02:24:01.14#flagr#flagr/antenna,acquired 2006.173.02:24:02.94#abcon#<5=/15 1.0 2.1 22.60 771006.5\r\n> 2006.173.02:24:02.96#abcon#{5=INTERFACE CLEAR} 2006.173.02:24:03.02#abcon#[5=S1D000X0/0*\r\n] 2006.173.02:24:03.63$setupk4/"tpicd 2006.173.02:24:03.63$setupk4/echo=off 2006.173.02:24:03.63$setupk4/xlog=off 2006.173.02:24:03.63:!2006.173.02:26:57 2006.173.02:26:57.00:preob 2006.173.02:26:57.13/onsource/TRACKING 2006.173.02:26:57.13:!2006.173.02:27:07 2006.173.02:27:07.00:"tape 2006.173.02:27:07.00:"st=record 2006.173.02:27:07.00:data_valid=on 2006.173.02:27:07.00:midob 2006.173.02:27:07.14/onsource/TRACKING 2006.173.02:27:07.14/wx/22.63,1006.5,80 2006.173.02:27:07.32/cable/+6.5108E-03 2006.173.02:27:08.41/va/01,07,usb,yes,34,37 2006.173.02:27:08.41/va/02,06,usb,yes,34,35 2006.173.02:27:08.41/va/03,05,usb,yes,44,46 2006.173.02:27:08.41/va/04,06,usb,yes,35,37 2006.173.02:27:08.41/va/05,04,usb,yes,27,28 2006.173.02:27:08.41/va/06,03,usb,yes,39,38 2006.173.02:27:08.41/va/07,04,usb,yes,31,32 2006.173.02:27:08.41/va/08,04,usb,yes,26,32 2006.173.02:27:08.64/valo/01,524.99,yes,locked 2006.173.02:27:08.64/valo/02,534.99,yes,locked 2006.173.02:27:08.64/valo/03,564.99,yes,locked 2006.173.02:27:08.64/valo/04,624.99,yes,locked 2006.173.02:27:08.64/valo/05,734.99,yes,locked 2006.173.02:27:08.64/valo/06,814.99,yes,locked 2006.173.02:27:08.64/valo/07,864.99,yes,locked 2006.173.02:27:08.64/valo/08,884.99,yes,locked 2006.173.02:27:09.73/vb/01,04,usb,yes,29,27 2006.173.02:27:09.73/vb/02,04,usb,yes,31,31 2006.173.02:27:09.73/vb/03,04,usb,yes,28,31 2006.173.02:27:09.73/vb/04,04,usb,yes,32,31 2006.173.02:27:09.73/vb/05,04,usb,yes,26,28 2006.173.02:27:09.73/vb/06,04,usb,yes,29,26 2006.173.02:27:09.73/vb/07,04,usb,yes,29,29 2006.173.02:27:09.73/vb/08,04,usb,yes,27,30 2006.173.02:27:09.96/vblo/01,629.99,yes,locked 2006.173.02:27:09.96/vblo/02,634.99,yes,locked 2006.173.02:27:09.96/vblo/03,649.99,yes,locked 2006.173.02:27:09.96/vblo/04,679.99,yes,locked 2006.173.02:27:09.96/vblo/05,709.99,yes,locked 2006.173.02:27:09.96/vblo/06,719.99,yes,locked 2006.173.02:27:09.96/vblo/07,734.99,yes,locked 2006.173.02:27:09.96/vblo/08,744.99,yes,locked 2006.173.02:27:10.11/vabw/8 2006.173.02:27:10.26/vbbw/8 2006.173.02:27:10.35/xfe/off,on,15.2 2006.173.02:27:10.73/ifatt/23,28,28,28 2006.173.02:27:11.08/fmout-gps/S +3.89E-07 2006.173.02:27:11.12:!2006.173.02:30:17 2006.173.02:30:17.01:data_valid=off 2006.173.02:30:17.01:"et 2006.173.02:30:17.02:!+3s 2006.173.02:30:20.03:"tape 2006.173.02:30:20.03:postob 2006.173.02:30:20.20/cable/+6.5106E-03 2006.173.02:30:20.20/wx/22.63,1006.5,79 2006.173.02:30:20.29/fmout-gps/S +3.88E-07 2006.173.02:30:20.29:scan_name=173-0233,jd0606,240 2006.173.02:30:20.29:source=cta26,033930.94,-014635.8,2000.0,ccw 2006.173.02:30:22.14#flagr#flagr/antenna,new-source 2006.173.02:30:22.14:checkk5 2006.173.02:30:22.59/chk_autoobs//k5ts1/ autoobs is running! 2006.173.02:30:22.97/chk_autoobs//k5ts2/ autoobs is running! 2006.173.02:30:23.45/chk_autoobs//k5ts3/ autoobs is running! 2006.173.02:30:24.09/chk_autoobs//k5ts4/ autoobs is running! 2006.173.02:30:24.53/chk_obsdata//k5ts1/T1730227??a.dat file size is correct (nominal:760MB, actual:756MB). 2006.173.02:30:24.95/chk_obsdata//k5ts2/T1730227??b.dat file size is correct (nominal:760MB, actual:756MB). 2006.173.02:30:25.35/chk_obsdata//k5ts3/T1730227??c.dat file size is correct (nominal:760MB, actual:756MB). 2006.173.02:30:25.81/chk_obsdata//k5ts4/T1730227??d.dat file size is correct (nominal:760MB, actual:756MB). 2006.173.02:30:26.82/k5log//k5ts1_log_newline 2006.173.02:30:27.65/k5log//k5ts2_log_newline 2006.173.02:30:28.68/k5log//k5ts3_log_newline 2006.173.02:30:29.47/k5log//k5ts4_log_newline 2006.173.02:30:29.50/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.02:30:29.50:setupk4=1 2006.173.02:30:29.50$setupk4/echo=on 2006.173.02:30:29.50$setupk4/pcalon 2006.173.02:30:29.50$pcalon/"no phase cal control is implemented here 2006.173.02:30:29.50$setupk4/"tpicd=stop 2006.173.02:30:29.50$setupk4/"rec=synch_on 2006.173.02:30:29.50$setupk4/"rec_mode=128 2006.173.02:30:29.50$setupk4/!* 2006.173.02:30:29.50$setupk4/recpk4 2006.173.02:30:29.50$recpk4/recpatch= 2006.173.02:30:29.50$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.02:30:29.50$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.02:30:29.50$setupk4/vck44 2006.173.02:30:29.50$vck44/valo=1,524.99 2006.173.02:30:29.50#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.02:30:29.50#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.02:30:29.50#ibcon#ireg 17 cls_cnt 0 2006.173.02:30:29.50#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.02:30:29.50#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.02:30:29.50#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.02:30:29.50#ibcon#enter wrdev, iclass 22, count 0 2006.173.02:30:29.50#ibcon#first serial, iclass 22, count 0 2006.173.02:30:29.50#ibcon#enter sib2, iclass 22, count 0 2006.173.02:30:29.50#ibcon#flushed, iclass 22, count 0 2006.173.02:30:29.50#ibcon#about to write, iclass 22, count 0 2006.173.02:30:29.50#ibcon#wrote, iclass 22, count 0 2006.173.02:30:29.50#ibcon#about to read 3, iclass 22, count 0 2006.173.02:30:29.55#ibcon#read 3, iclass 22, count 0 2006.173.02:30:29.55#ibcon#about to read 4, iclass 22, count 0 2006.173.02:30:29.55#ibcon#read 4, iclass 22, count 0 2006.173.02:30:29.55#ibcon#about to read 5, iclass 22, count 0 2006.173.02:30:29.55#ibcon#read 5, iclass 22, count 0 2006.173.02:30:29.55#ibcon#about to read 6, iclass 22, count 0 2006.173.02:30:29.55#ibcon#read 6, iclass 22, count 0 2006.173.02:30:29.55#ibcon#end of sib2, iclass 22, count 0 2006.173.02:30:29.55#ibcon#*mode == 0, iclass 22, count 0 2006.173.02:30:29.55#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.02:30:29.55#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.02:30:29.55#ibcon#*before write, iclass 22, count 0 2006.173.02:30:29.55#ibcon#enter sib2, iclass 22, count 0 2006.173.02:30:29.55#ibcon#flushed, iclass 22, count 0 2006.173.02:30:29.55#ibcon#about to write, iclass 22, count 0 2006.173.02:30:29.55#ibcon#wrote, iclass 22, count 0 2006.173.02:30:29.55#ibcon#about to read 3, iclass 22, count 0 2006.173.02:30:29.60#ibcon#read 3, iclass 22, count 0 2006.173.02:30:29.60#ibcon#about to read 4, iclass 22, count 0 2006.173.02:30:29.60#ibcon#read 4, iclass 22, count 0 2006.173.02:30:29.60#ibcon#about to read 5, iclass 22, count 0 2006.173.02:30:29.60#ibcon#read 5, iclass 22, count 0 2006.173.02:30:29.60#ibcon#about to read 6, iclass 22, count 0 2006.173.02:30:29.60#ibcon#read 6, iclass 22, count 0 2006.173.02:30:29.60#ibcon#end of sib2, iclass 22, count 0 2006.173.02:30:29.60#ibcon#*after write, iclass 22, count 0 2006.173.02:30:29.60#ibcon#*before return 0, iclass 22, count 0 2006.173.02:30:29.60#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.02:30:29.60#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.02:30:29.60#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.02:30:29.60#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.02:30:29.60$vck44/va=1,7 2006.173.02:30:29.60#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.02:30:29.60#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.02:30:29.60#ibcon#ireg 11 cls_cnt 2 2006.173.02:30:29.60#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.02:30:29.60#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.02:30:29.60#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.02:30:29.60#ibcon#enter wrdev, iclass 24, count 2 2006.173.02:30:29.60#ibcon#first serial, iclass 24, count 2 2006.173.02:30:29.60#ibcon#enter sib2, iclass 24, count 2 2006.173.02:30:29.60#ibcon#flushed, iclass 24, count 2 2006.173.02:30:29.60#ibcon#about to write, iclass 24, count 2 2006.173.02:30:29.60#ibcon#wrote, iclass 24, count 2 2006.173.02:30:29.60#ibcon#about to read 3, iclass 24, count 2 2006.173.02:30:29.62#ibcon#read 3, iclass 24, count 2 2006.173.02:30:29.62#ibcon#about to read 4, iclass 24, count 2 2006.173.02:30:29.62#ibcon#read 4, iclass 24, count 2 2006.173.02:30:29.62#ibcon#about to read 5, iclass 24, count 2 2006.173.02:30:29.62#ibcon#read 5, iclass 24, count 2 2006.173.02:30:29.62#ibcon#about to read 6, iclass 24, count 2 2006.173.02:30:29.62#ibcon#read 6, iclass 24, count 2 2006.173.02:30:29.62#ibcon#end of sib2, iclass 24, count 2 2006.173.02:30:29.62#ibcon#*mode == 0, iclass 24, count 2 2006.173.02:30:29.62#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.02:30:29.62#ibcon#[25=AT01-07\r\n] 2006.173.02:30:29.62#ibcon#*before write, iclass 24, count 2 2006.173.02:30:29.62#ibcon#enter sib2, iclass 24, count 2 2006.173.02:30:29.62#ibcon#flushed, iclass 24, count 2 2006.173.02:30:29.63#ibcon#about to write, iclass 24, count 2 2006.173.02:30:29.63#ibcon#wrote, iclass 24, count 2 2006.173.02:30:29.63#ibcon#about to read 3, iclass 24, count 2 2006.173.02:30:29.66#ibcon#read 3, iclass 24, count 2 2006.173.02:30:29.66#ibcon#about to read 4, iclass 24, count 2 2006.173.02:30:29.66#ibcon#read 4, iclass 24, count 2 2006.173.02:30:29.66#ibcon#about to read 5, iclass 24, count 2 2006.173.02:30:29.66#ibcon#read 5, iclass 24, count 2 2006.173.02:30:29.66#ibcon#about to read 6, iclass 24, count 2 2006.173.02:30:29.66#ibcon#read 6, iclass 24, count 2 2006.173.02:30:29.66#ibcon#end of sib2, iclass 24, count 2 2006.173.02:30:29.66#ibcon#*after write, iclass 24, count 2 2006.173.02:30:29.66#ibcon#*before return 0, iclass 24, count 2 2006.173.02:30:29.66#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.02:30:29.66#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.02:30:29.66#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.02:30:29.66#ibcon#ireg 7 cls_cnt 0 2006.173.02:30:29.66#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.02:30:29.78#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.02:30:29.78#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.02:30:29.78#ibcon#enter wrdev, iclass 24, count 0 2006.173.02:30:29.78#ibcon#first serial, iclass 24, count 0 2006.173.02:30:29.78#ibcon#enter sib2, iclass 24, count 0 2006.173.02:30:29.78#ibcon#flushed, iclass 24, count 0 2006.173.02:30:29.78#ibcon#about to write, iclass 24, count 0 2006.173.02:30:29.78#ibcon#wrote, iclass 24, count 0 2006.173.02:30:29.78#ibcon#about to read 3, iclass 24, count 0 2006.173.02:30:29.80#ibcon#read 3, iclass 24, count 0 2006.173.02:30:29.80#ibcon#about to read 4, iclass 24, count 0 2006.173.02:30:29.80#ibcon#read 4, iclass 24, count 0 2006.173.02:30:29.80#ibcon#about to read 5, iclass 24, count 0 2006.173.02:30:29.80#ibcon#read 5, iclass 24, count 0 2006.173.02:30:29.80#ibcon#about to read 6, iclass 24, count 0 2006.173.02:30:29.80#ibcon#read 6, iclass 24, count 0 2006.173.02:30:29.80#ibcon#end of sib2, iclass 24, count 0 2006.173.02:30:29.80#ibcon#*mode == 0, iclass 24, count 0 2006.173.02:30:29.80#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.02:30:29.80#ibcon#[25=USB\r\n] 2006.173.02:30:29.80#ibcon#*before write, iclass 24, count 0 2006.173.02:30:29.80#ibcon#enter sib2, iclass 24, count 0 2006.173.02:30:29.80#ibcon#flushed, iclass 24, count 0 2006.173.02:30:29.80#ibcon#about to write, iclass 24, count 0 2006.173.02:30:29.80#ibcon#wrote, iclass 24, count 0 2006.173.02:30:29.80#ibcon#about to read 3, iclass 24, count 0 2006.173.02:30:29.83#ibcon#read 3, iclass 24, count 0 2006.173.02:30:29.83#ibcon#about to read 4, iclass 24, count 0 2006.173.02:30:29.83#ibcon#read 4, iclass 24, count 0 2006.173.02:30:29.83#ibcon#about to read 5, iclass 24, count 0 2006.173.02:30:29.83#ibcon#read 5, iclass 24, count 0 2006.173.02:30:29.83#ibcon#about to read 6, iclass 24, count 0 2006.173.02:30:29.83#ibcon#read 6, iclass 24, count 0 2006.173.02:30:29.83#ibcon#end of sib2, iclass 24, count 0 2006.173.02:30:29.83#ibcon#*after write, iclass 24, count 0 2006.173.02:30:29.83#ibcon#*before return 0, iclass 24, count 0 2006.173.02:30:29.83#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.02:30:29.83#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.02:30:29.83#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.02:30:29.83#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.02:30:29.83$vck44/valo=2,534.99 2006.173.02:30:29.83#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.02:30:29.83#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.02:30:29.83#ibcon#ireg 17 cls_cnt 0 2006.173.02:30:29.83#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.02:30:29.83#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.02:30:29.83#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.02:30:29.83#ibcon#enter wrdev, iclass 26, count 0 2006.173.02:30:29.83#ibcon#first serial, iclass 26, count 0 2006.173.02:30:29.83#ibcon#enter sib2, iclass 26, count 0 2006.173.02:30:29.83#ibcon#flushed, iclass 26, count 0 2006.173.02:30:29.83#ibcon#about to write, iclass 26, count 0 2006.173.02:30:29.83#ibcon#wrote, iclass 26, count 0 2006.173.02:30:29.83#ibcon#about to read 3, iclass 26, count 0 2006.173.02:30:29.85#ibcon#read 3, iclass 26, count 0 2006.173.02:30:29.85#ibcon#about to read 4, iclass 26, count 0 2006.173.02:30:29.85#ibcon#read 4, iclass 26, count 0 2006.173.02:30:29.85#ibcon#about to read 5, iclass 26, count 0 2006.173.02:30:29.85#ibcon#read 5, iclass 26, count 0 2006.173.02:30:29.85#ibcon#about to read 6, iclass 26, count 0 2006.173.02:30:29.85#ibcon#read 6, iclass 26, count 0 2006.173.02:30:29.85#ibcon#end of sib2, iclass 26, count 0 2006.173.02:30:29.85#ibcon#*mode == 0, iclass 26, count 0 2006.173.02:30:29.85#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.02:30:29.85#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.02:30:29.85#ibcon#*before write, iclass 26, count 0 2006.173.02:30:29.85#ibcon#enter sib2, iclass 26, count 0 2006.173.02:30:29.85#ibcon#flushed, iclass 26, count 0 2006.173.02:30:29.85#ibcon#about to write, iclass 26, count 0 2006.173.02:30:29.85#ibcon#wrote, iclass 26, count 0 2006.173.02:30:29.85#ibcon#about to read 3, iclass 26, count 0 2006.173.02:30:29.89#ibcon#read 3, iclass 26, count 0 2006.173.02:30:29.89#ibcon#about to read 4, iclass 26, count 0 2006.173.02:30:29.89#ibcon#read 4, iclass 26, count 0 2006.173.02:30:29.89#ibcon#about to read 5, iclass 26, count 0 2006.173.02:30:29.89#ibcon#read 5, iclass 26, count 0 2006.173.02:30:29.89#ibcon#about to read 6, iclass 26, count 0 2006.173.02:30:29.89#ibcon#read 6, iclass 26, count 0 2006.173.02:30:29.89#ibcon#end of sib2, iclass 26, count 0 2006.173.02:30:29.89#ibcon#*after write, iclass 26, count 0 2006.173.02:30:29.89#ibcon#*before return 0, iclass 26, count 0 2006.173.02:30:29.89#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.02:30:29.89#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.02:30:29.89#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.02:30:29.89#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.02:30:29.89$vck44/va=2,6 2006.173.02:30:29.89#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.02:30:29.89#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.02:30:29.89#ibcon#ireg 11 cls_cnt 2 2006.173.02:30:29.89#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.02:30:29.95#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.02:30:29.95#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.02:30:29.95#ibcon#enter wrdev, iclass 28, count 2 2006.173.02:30:29.95#ibcon#first serial, iclass 28, count 2 2006.173.02:30:29.95#ibcon#enter sib2, iclass 28, count 2 2006.173.02:30:29.95#ibcon#flushed, iclass 28, count 2 2006.173.02:30:29.95#ibcon#about to write, iclass 28, count 2 2006.173.02:30:29.95#ibcon#wrote, iclass 28, count 2 2006.173.02:30:29.95#ibcon#about to read 3, iclass 28, count 2 2006.173.02:30:29.98#ibcon#read 3, iclass 28, count 2 2006.173.02:30:29.98#ibcon#about to read 4, iclass 28, count 2 2006.173.02:30:29.98#ibcon#read 4, iclass 28, count 2 2006.173.02:30:29.98#ibcon#about to read 5, iclass 28, count 2 2006.173.02:30:29.98#ibcon#read 5, iclass 28, count 2 2006.173.02:30:29.98#ibcon#about to read 6, iclass 28, count 2 2006.173.02:30:29.98#ibcon#read 6, iclass 28, count 2 2006.173.02:30:29.98#ibcon#end of sib2, iclass 28, count 2 2006.173.02:30:29.98#ibcon#*mode == 0, iclass 28, count 2 2006.173.02:30:29.98#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.02:30:29.98#ibcon#[25=AT02-06\r\n] 2006.173.02:30:29.98#ibcon#*before write, iclass 28, count 2 2006.173.02:30:29.98#ibcon#enter sib2, iclass 28, count 2 2006.173.02:30:29.98#ibcon#flushed, iclass 28, count 2 2006.173.02:30:29.98#ibcon#about to write, iclass 28, count 2 2006.173.02:30:29.98#ibcon#wrote, iclass 28, count 2 2006.173.02:30:29.98#ibcon#about to read 3, iclass 28, count 2 2006.173.02:30:30.01#ibcon#read 3, iclass 28, count 2 2006.173.02:30:30.01#ibcon#about to read 4, iclass 28, count 2 2006.173.02:30:30.01#ibcon#read 4, iclass 28, count 2 2006.173.02:30:30.01#ibcon#about to read 5, iclass 28, count 2 2006.173.02:30:30.01#ibcon#read 5, iclass 28, count 2 2006.173.02:30:30.01#ibcon#about to read 6, iclass 28, count 2 2006.173.02:30:30.01#ibcon#read 6, iclass 28, count 2 2006.173.02:30:30.01#ibcon#end of sib2, iclass 28, count 2 2006.173.02:30:30.01#ibcon#*after write, iclass 28, count 2 2006.173.02:30:30.01#ibcon#*before return 0, iclass 28, count 2 2006.173.02:30:30.01#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.02:30:30.01#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.02:30:30.01#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.02:30:30.01#ibcon#ireg 7 cls_cnt 0 2006.173.02:30:30.01#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.02:30:30.13#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.02:30:30.13#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.02:30:30.13#ibcon#enter wrdev, iclass 28, count 0 2006.173.02:30:30.13#ibcon#first serial, iclass 28, count 0 2006.173.02:30:30.13#ibcon#enter sib2, iclass 28, count 0 2006.173.02:30:30.13#ibcon#flushed, iclass 28, count 0 2006.173.02:30:30.13#ibcon#about to write, iclass 28, count 0 2006.173.02:30:30.13#ibcon#wrote, iclass 28, count 0 2006.173.02:30:30.13#ibcon#about to read 3, iclass 28, count 0 2006.173.02:30:30.15#ibcon#read 3, iclass 28, count 0 2006.173.02:30:30.15#ibcon#about to read 4, iclass 28, count 0 2006.173.02:30:30.15#ibcon#read 4, iclass 28, count 0 2006.173.02:30:30.15#ibcon#about to read 5, iclass 28, count 0 2006.173.02:30:30.15#ibcon#read 5, iclass 28, count 0 2006.173.02:30:30.15#ibcon#about to read 6, iclass 28, count 0 2006.173.02:30:30.15#ibcon#read 6, iclass 28, count 0 2006.173.02:30:30.15#ibcon#end of sib2, iclass 28, count 0 2006.173.02:30:30.15#ibcon#*mode == 0, iclass 28, count 0 2006.173.02:30:30.15#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.02:30:30.15#ibcon#[25=USB\r\n] 2006.173.02:30:30.15#ibcon#*before write, iclass 28, count 0 2006.173.02:30:30.15#ibcon#enter sib2, iclass 28, count 0 2006.173.02:30:30.15#ibcon#flushed, iclass 28, count 0 2006.173.02:30:30.15#ibcon#about to write, iclass 28, count 0 2006.173.02:30:30.15#ibcon#wrote, iclass 28, count 0 2006.173.02:30:30.15#ibcon#about to read 3, iclass 28, count 0 2006.173.02:30:30.18#ibcon#read 3, iclass 28, count 0 2006.173.02:30:30.18#ibcon#about to read 4, iclass 28, count 0 2006.173.02:30:30.18#ibcon#read 4, iclass 28, count 0 2006.173.02:30:30.18#ibcon#about to read 5, iclass 28, count 0 2006.173.02:30:30.18#ibcon#read 5, iclass 28, count 0 2006.173.02:30:30.18#ibcon#about to read 6, iclass 28, count 0 2006.173.02:30:30.18#ibcon#read 6, iclass 28, count 0 2006.173.02:30:30.18#ibcon#end of sib2, iclass 28, count 0 2006.173.02:30:30.18#ibcon#*after write, iclass 28, count 0 2006.173.02:30:30.18#ibcon#*before return 0, iclass 28, count 0 2006.173.02:30:30.18#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.02:30:30.18#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.02:30:30.18#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.02:30:30.18#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.02:30:30.18$vck44/valo=3,564.99 2006.173.02:30:30.18#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.02:30:30.18#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.02:30:30.18#ibcon#ireg 17 cls_cnt 0 2006.173.02:30:30.18#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.02:30:30.18#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.02:30:30.18#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.02:30:30.18#ibcon#enter wrdev, iclass 30, count 0 2006.173.02:30:30.18#ibcon#first serial, iclass 30, count 0 2006.173.02:30:30.18#ibcon#enter sib2, iclass 30, count 0 2006.173.02:30:30.18#ibcon#flushed, iclass 30, count 0 2006.173.02:30:30.18#ibcon#about to write, iclass 30, count 0 2006.173.02:30:30.18#ibcon#wrote, iclass 30, count 0 2006.173.02:30:30.18#ibcon#about to read 3, iclass 30, count 0 2006.173.02:30:30.21#ibcon#read 3, iclass 30, count 0 2006.173.02:30:30.21#ibcon#about to read 4, iclass 30, count 0 2006.173.02:30:30.21#ibcon#read 4, iclass 30, count 0 2006.173.02:30:30.21#ibcon#about to read 5, iclass 30, count 0 2006.173.02:30:30.21#ibcon#read 5, iclass 30, count 0 2006.173.02:30:30.21#ibcon#about to read 6, iclass 30, count 0 2006.173.02:30:30.21#ibcon#read 6, iclass 30, count 0 2006.173.02:30:30.21#ibcon#end of sib2, iclass 30, count 0 2006.173.02:30:30.21#ibcon#*mode == 0, iclass 30, count 0 2006.173.02:30:30.21#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.02:30:30.21#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.02:30:30.21#ibcon#*before write, iclass 30, count 0 2006.173.02:30:30.21#ibcon#enter sib2, iclass 30, count 0 2006.173.02:30:30.21#ibcon#flushed, iclass 30, count 0 2006.173.02:30:30.21#ibcon#about to write, iclass 30, count 0 2006.173.02:30:30.21#ibcon#wrote, iclass 30, count 0 2006.173.02:30:30.21#ibcon#about to read 3, iclass 30, count 0 2006.173.02:30:30.25#ibcon#read 3, iclass 30, count 0 2006.173.02:30:30.25#ibcon#about to read 4, iclass 30, count 0 2006.173.02:30:30.25#ibcon#read 4, iclass 30, count 0 2006.173.02:30:30.25#ibcon#about to read 5, iclass 30, count 0 2006.173.02:30:30.25#ibcon#read 5, iclass 30, count 0 2006.173.02:30:30.25#ibcon#about to read 6, iclass 30, count 0 2006.173.02:30:30.25#ibcon#read 6, iclass 30, count 0 2006.173.02:30:30.25#ibcon#end of sib2, iclass 30, count 0 2006.173.02:30:30.25#ibcon#*after write, iclass 30, count 0 2006.173.02:30:30.25#ibcon#*before return 0, iclass 30, count 0 2006.173.02:30:30.25#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.02:30:30.25#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.02:30:30.25#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.02:30:30.25#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.02:30:30.25$vck44/va=3,5 2006.173.02:30:30.25#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.173.02:30:30.25#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.173.02:30:30.25#ibcon#ireg 11 cls_cnt 2 2006.173.02:30:30.25#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.02:30:30.30#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.02:30:30.30#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.02:30:30.30#ibcon#enter wrdev, iclass 32, count 2 2006.173.02:30:30.30#ibcon#first serial, iclass 32, count 2 2006.173.02:30:30.30#ibcon#enter sib2, iclass 32, count 2 2006.173.02:30:30.30#ibcon#flushed, iclass 32, count 2 2006.173.02:30:30.30#ibcon#about to write, iclass 32, count 2 2006.173.02:30:30.30#ibcon#wrote, iclass 32, count 2 2006.173.02:30:30.30#ibcon#about to read 3, iclass 32, count 2 2006.173.02:30:30.33#ibcon#read 3, iclass 32, count 2 2006.173.02:30:30.33#ibcon#about to read 4, iclass 32, count 2 2006.173.02:30:30.33#ibcon#read 4, iclass 32, count 2 2006.173.02:30:30.33#ibcon#about to read 5, iclass 32, count 2 2006.173.02:30:30.33#ibcon#read 5, iclass 32, count 2 2006.173.02:30:30.33#ibcon#about to read 6, iclass 32, count 2 2006.173.02:30:30.33#ibcon#read 6, iclass 32, count 2 2006.173.02:30:30.33#ibcon#end of sib2, iclass 32, count 2 2006.173.02:30:30.33#ibcon#*mode == 0, iclass 32, count 2 2006.173.02:30:30.33#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.173.02:30:30.33#ibcon#[25=AT03-05\r\n] 2006.173.02:30:30.33#ibcon#*before write, iclass 32, count 2 2006.173.02:30:30.33#ibcon#enter sib2, iclass 32, count 2 2006.173.02:30:30.33#ibcon#flushed, iclass 32, count 2 2006.173.02:30:30.33#ibcon#about to write, iclass 32, count 2 2006.173.02:30:30.33#ibcon#wrote, iclass 32, count 2 2006.173.02:30:30.33#ibcon#about to read 3, iclass 32, count 2 2006.173.02:30:30.36#ibcon#read 3, iclass 32, count 2 2006.173.02:30:30.36#ibcon#about to read 4, iclass 32, count 2 2006.173.02:30:30.36#ibcon#read 4, iclass 32, count 2 2006.173.02:30:30.36#ibcon#about to read 5, iclass 32, count 2 2006.173.02:30:30.36#ibcon#read 5, iclass 32, count 2 2006.173.02:30:30.36#ibcon#about to read 6, iclass 32, count 2 2006.173.02:30:30.36#ibcon#read 6, iclass 32, count 2 2006.173.02:30:30.36#ibcon#end of sib2, iclass 32, count 2 2006.173.02:30:30.36#ibcon#*after write, iclass 32, count 2 2006.173.02:30:30.36#ibcon#*before return 0, iclass 32, count 2 2006.173.02:30:30.36#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.02:30:30.36#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.173.02:30:30.36#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.173.02:30:30.36#ibcon#ireg 7 cls_cnt 0 2006.173.02:30:30.36#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.02:30:30.48#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.02:30:30.48#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.02:30:30.48#ibcon#enter wrdev, iclass 32, count 0 2006.173.02:30:30.48#ibcon#first serial, iclass 32, count 0 2006.173.02:30:30.48#ibcon#enter sib2, iclass 32, count 0 2006.173.02:30:30.48#ibcon#flushed, iclass 32, count 0 2006.173.02:30:30.48#ibcon#about to write, iclass 32, count 0 2006.173.02:30:30.48#ibcon#wrote, iclass 32, count 0 2006.173.02:30:30.48#ibcon#about to read 3, iclass 32, count 0 2006.173.02:30:30.50#ibcon#read 3, iclass 32, count 0 2006.173.02:30:30.50#ibcon#about to read 4, iclass 32, count 0 2006.173.02:30:30.50#ibcon#read 4, iclass 32, count 0 2006.173.02:30:30.50#ibcon#about to read 5, iclass 32, count 0 2006.173.02:30:30.50#ibcon#read 5, iclass 32, count 0 2006.173.02:30:30.50#ibcon#about to read 6, iclass 32, count 0 2006.173.02:30:30.50#ibcon#read 6, iclass 32, count 0 2006.173.02:30:30.50#ibcon#end of sib2, iclass 32, count 0 2006.173.02:30:30.50#ibcon#*mode == 0, iclass 32, count 0 2006.173.02:30:30.50#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.02:30:30.50#ibcon#[25=USB\r\n] 2006.173.02:30:30.50#ibcon#*before write, iclass 32, count 0 2006.173.02:30:30.50#ibcon#enter sib2, iclass 32, count 0 2006.173.02:30:30.50#ibcon#flushed, iclass 32, count 0 2006.173.02:30:30.50#ibcon#about to write, iclass 32, count 0 2006.173.02:30:30.50#ibcon#wrote, iclass 32, count 0 2006.173.02:30:30.50#ibcon#about to read 3, iclass 32, count 0 2006.173.02:30:30.53#ibcon#read 3, iclass 32, count 0 2006.173.02:30:30.53#ibcon#about to read 4, iclass 32, count 0 2006.173.02:30:30.53#ibcon#read 4, iclass 32, count 0 2006.173.02:30:30.53#ibcon#about to read 5, iclass 32, count 0 2006.173.02:30:30.53#ibcon#read 5, iclass 32, count 0 2006.173.02:30:30.53#ibcon#about to read 6, iclass 32, count 0 2006.173.02:30:30.53#ibcon#read 6, iclass 32, count 0 2006.173.02:30:30.53#ibcon#end of sib2, iclass 32, count 0 2006.173.02:30:30.53#ibcon#*after write, iclass 32, count 0 2006.173.02:30:30.53#ibcon#*before return 0, iclass 32, count 0 2006.173.02:30:30.53#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.02:30:30.53#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.173.02:30:30.53#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.02:30:30.53#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.02:30:30.53$vck44/valo=4,624.99 2006.173.02:30:30.53#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.02:30:30.53#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.02:30:30.53#ibcon#ireg 17 cls_cnt 0 2006.173.02:30:30.53#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.02:30:30.53#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.02:30:30.53#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.02:30:30.53#ibcon#enter wrdev, iclass 34, count 0 2006.173.02:30:30.53#ibcon#first serial, iclass 34, count 0 2006.173.02:30:30.53#ibcon#enter sib2, iclass 34, count 0 2006.173.02:30:30.53#ibcon#flushed, iclass 34, count 0 2006.173.02:30:30.53#ibcon#about to write, iclass 34, count 0 2006.173.02:30:30.53#ibcon#wrote, iclass 34, count 0 2006.173.02:30:30.53#ibcon#about to read 3, iclass 34, count 0 2006.173.02:30:30.55#ibcon#read 3, iclass 34, count 0 2006.173.02:30:30.55#ibcon#about to read 4, iclass 34, count 0 2006.173.02:30:30.55#ibcon#read 4, iclass 34, count 0 2006.173.02:30:30.55#ibcon#about to read 5, iclass 34, count 0 2006.173.02:30:30.55#ibcon#read 5, iclass 34, count 0 2006.173.02:30:30.55#ibcon#about to read 6, iclass 34, count 0 2006.173.02:30:30.55#ibcon#read 6, iclass 34, count 0 2006.173.02:30:30.55#ibcon#end of sib2, iclass 34, count 0 2006.173.02:30:30.55#ibcon#*mode == 0, iclass 34, count 0 2006.173.02:30:30.55#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.02:30:30.55#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.02:30:30.55#ibcon#*before write, iclass 34, count 0 2006.173.02:30:30.55#ibcon#enter sib2, iclass 34, count 0 2006.173.02:30:30.55#ibcon#flushed, iclass 34, count 0 2006.173.02:30:30.55#ibcon#about to write, iclass 34, count 0 2006.173.02:30:30.55#ibcon#wrote, iclass 34, count 0 2006.173.02:30:30.55#ibcon#about to read 3, iclass 34, count 0 2006.173.02:30:30.59#ibcon#read 3, iclass 34, count 0 2006.173.02:30:30.59#ibcon#about to read 4, iclass 34, count 0 2006.173.02:30:30.59#ibcon#read 4, iclass 34, count 0 2006.173.02:30:30.59#ibcon#about to read 5, iclass 34, count 0 2006.173.02:30:30.59#ibcon#read 5, iclass 34, count 0 2006.173.02:30:30.59#ibcon#about to read 6, iclass 34, count 0 2006.173.02:30:30.59#ibcon#read 6, iclass 34, count 0 2006.173.02:30:30.59#ibcon#end of sib2, iclass 34, count 0 2006.173.02:30:30.59#ibcon#*after write, iclass 34, count 0 2006.173.02:30:30.59#ibcon#*before return 0, iclass 34, count 0 2006.173.02:30:30.59#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.02:30:30.59#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.02:30:30.59#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.02:30:30.59#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.02:30:30.59$vck44/va=4,6 2006.173.02:30:30.59#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.02:30:30.59#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.02:30:30.59#ibcon#ireg 11 cls_cnt 2 2006.173.02:30:30.59#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.02:30:30.65#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.02:30:30.65#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.02:30:30.65#ibcon#enter wrdev, iclass 36, count 2 2006.173.02:30:30.65#ibcon#first serial, iclass 36, count 2 2006.173.02:30:30.65#ibcon#enter sib2, iclass 36, count 2 2006.173.02:30:30.65#ibcon#flushed, iclass 36, count 2 2006.173.02:30:30.65#ibcon#about to write, iclass 36, count 2 2006.173.02:30:30.65#ibcon#wrote, iclass 36, count 2 2006.173.02:30:30.65#ibcon#about to read 3, iclass 36, count 2 2006.173.02:30:30.67#ibcon#read 3, iclass 36, count 2 2006.173.02:30:30.67#ibcon#about to read 4, iclass 36, count 2 2006.173.02:30:30.67#ibcon#read 4, iclass 36, count 2 2006.173.02:30:30.67#ibcon#about to read 5, iclass 36, count 2 2006.173.02:30:30.67#ibcon#read 5, iclass 36, count 2 2006.173.02:30:30.67#ibcon#about to read 6, iclass 36, count 2 2006.173.02:30:30.67#ibcon#read 6, iclass 36, count 2 2006.173.02:30:30.67#ibcon#end of sib2, iclass 36, count 2 2006.173.02:30:30.67#ibcon#*mode == 0, iclass 36, count 2 2006.173.02:30:30.67#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.02:30:30.67#ibcon#[25=AT04-06\r\n] 2006.173.02:30:30.67#ibcon#*before write, iclass 36, count 2 2006.173.02:30:30.67#ibcon#enter sib2, iclass 36, count 2 2006.173.02:30:30.67#ibcon#flushed, iclass 36, count 2 2006.173.02:30:30.67#ibcon#about to write, iclass 36, count 2 2006.173.02:30:30.67#ibcon#wrote, iclass 36, count 2 2006.173.02:30:30.67#ibcon#about to read 3, iclass 36, count 2 2006.173.02:30:30.70#ibcon#read 3, iclass 36, count 2 2006.173.02:30:30.70#ibcon#about to read 4, iclass 36, count 2 2006.173.02:30:30.70#ibcon#read 4, iclass 36, count 2 2006.173.02:30:30.70#ibcon#about to read 5, iclass 36, count 2 2006.173.02:30:30.70#ibcon#read 5, iclass 36, count 2 2006.173.02:30:30.70#ibcon#about to read 6, iclass 36, count 2 2006.173.02:30:30.70#ibcon#read 6, iclass 36, count 2 2006.173.02:30:30.70#ibcon#end of sib2, iclass 36, count 2 2006.173.02:30:30.70#ibcon#*after write, iclass 36, count 2 2006.173.02:30:30.70#ibcon#*before return 0, iclass 36, count 2 2006.173.02:30:30.70#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.02:30:30.70#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.02:30:30.70#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.02:30:30.70#ibcon#ireg 7 cls_cnt 0 2006.173.02:30:30.70#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.02:30:30.82#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.02:30:30.82#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.02:30:30.82#ibcon#enter wrdev, iclass 36, count 0 2006.173.02:30:30.82#ibcon#first serial, iclass 36, count 0 2006.173.02:30:30.82#ibcon#enter sib2, iclass 36, count 0 2006.173.02:30:30.82#ibcon#flushed, iclass 36, count 0 2006.173.02:30:30.82#ibcon#about to write, iclass 36, count 0 2006.173.02:30:30.82#ibcon#wrote, iclass 36, count 0 2006.173.02:30:30.82#ibcon#about to read 3, iclass 36, count 0 2006.173.02:30:30.84#ibcon#read 3, iclass 36, count 0 2006.173.02:30:30.84#ibcon#about to read 4, iclass 36, count 0 2006.173.02:30:30.84#ibcon#read 4, iclass 36, count 0 2006.173.02:30:30.84#ibcon#about to read 5, iclass 36, count 0 2006.173.02:30:30.84#ibcon#read 5, iclass 36, count 0 2006.173.02:30:30.84#ibcon#about to read 6, iclass 36, count 0 2006.173.02:30:30.84#ibcon#read 6, iclass 36, count 0 2006.173.02:30:30.84#ibcon#end of sib2, iclass 36, count 0 2006.173.02:30:30.84#ibcon#*mode == 0, iclass 36, count 0 2006.173.02:30:30.84#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.02:30:30.84#ibcon#[25=USB\r\n] 2006.173.02:30:30.84#ibcon#*before write, iclass 36, count 0 2006.173.02:30:30.84#ibcon#enter sib2, iclass 36, count 0 2006.173.02:30:30.84#ibcon#flushed, iclass 36, count 0 2006.173.02:30:30.84#ibcon#about to write, iclass 36, count 0 2006.173.02:30:30.84#ibcon#wrote, iclass 36, count 0 2006.173.02:30:30.84#ibcon#about to read 3, iclass 36, count 0 2006.173.02:30:30.87#ibcon#read 3, iclass 36, count 0 2006.173.02:30:30.87#ibcon#about to read 4, iclass 36, count 0 2006.173.02:30:30.87#ibcon#read 4, iclass 36, count 0 2006.173.02:30:30.87#ibcon#about to read 5, iclass 36, count 0 2006.173.02:30:30.87#ibcon#read 5, iclass 36, count 0 2006.173.02:30:30.87#ibcon#about to read 6, iclass 36, count 0 2006.173.02:30:30.87#ibcon#read 6, iclass 36, count 0 2006.173.02:30:30.87#ibcon#end of sib2, iclass 36, count 0 2006.173.02:30:30.87#ibcon#*after write, iclass 36, count 0 2006.173.02:30:30.87#ibcon#*before return 0, iclass 36, count 0 2006.173.02:30:30.87#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.02:30:30.87#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.02:30:30.87#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.02:30:30.87#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.02:30:30.87$vck44/valo=5,734.99 2006.173.02:30:30.87#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.02:30:30.87#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.02:30:30.87#ibcon#ireg 17 cls_cnt 0 2006.173.02:30:30.87#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.02:30:30.87#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.02:30:30.87#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.02:30:30.87#ibcon#enter wrdev, iclass 38, count 0 2006.173.02:30:30.87#ibcon#first serial, iclass 38, count 0 2006.173.02:30:30.87#ibcon#enter sib2, iclass 38, count 0 2006.173.02:30:30.87#ibcon#flushed, iclass 38, count 0 2006.173.02:30:30.87#ibcon#about to write, iclass 38, count 0 2006.173.02:30:30.87#ibcon#wrote, iclass 38, count 0 2006.173.02:30:30.87#ibcon#about to read 3, iclass 38, count 0 2006.173.02:30:30.89#ibcon#read 3, iclass 38, count 0 2006.173.02:30:30.89#ibcon#about to read 4, iclass 38, count 0 2006.173.02:30:30.89#ibcon#read 4, iclass 38, count 0 2006.173.02:30:30.89#ibcon#about to read 5, iclass 38, count 0 2006.173.02:30:30.89#ibcon#read 5, iclass 38, count 0 2006.173.02:30:30.89#ibcon#about to read 6, iclass 38, count 0 2006.173.02:30:30.89#ibcon#read 6, iclass 38, count 0 2006.173.02:30:30.89#ibcon#end of sib2, iclass 38, count 0 2006.173.02:30:30.89#ibcon#*mode == 0, iclass 38, count 0 2006.173.02:30:30.89#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.02:30:30.89#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.02:30:30.89#ibcon#*before write, iclass 38, count 0 2006.173.02:30:30.89#ibcon#enter sib2, iclass 38, count 0 2006.173.02:30:30.89#ibcon#flushed, iclass 38, count 0 2006.173.02:30:30.89#ibcon#about to write, iclass 38, count 0 2006.173.02:30:30.89#ibcon#wrote, iclass 38, count 0 2006.173.02:30:30.89#ibcon#about to read 3, iclass 38, count 0 2006.173.02:30:30.93#ibcon#read 3, iclass 38, count 0 2006.173.02:30:30.93#ibcon#about to read 4, iclass 38, count 0 2006.173.02:30:30.93#ibcon#read 4, iclass 38, count 0 2006.173.02:30:30.93#ibcon#about to read 5, iclass 38, count 0 2006.173.02:30:30.93#ibcon#read 5, iclass 38, count 0 2006.173.02:30:30.93#ibcon#about to read 6, iclass 38, count 0 2006.173.02:30:30.93#ibcon#read 6, iclass 38, count 0 2006.173.02:30:30.93#ibcon#end of sib2, iclass 38, count 0 2006.173.02:30:30.93#ibcon#*after write, iclass 38, count 0 2006.173.02:30:30.93#ibcon#*before return 0, iclass 38, count 0 2006.173.02:30:30.93#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.02:30:30.93#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.02:30:30.93#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.02:30:30.93#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.02:30:30.93$vck44/va=5,4 2006.173.02:30:30.93#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.02:30:30.93#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.02:30:30.93#ibcon#ireg 11 cls_cnt 2 2006.173.02:30:30.93#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.02:30:30.99#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.02:30:30.99#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.02:30:30.99#ibcon#enter wrdev, iclass 40, count 2 2006.173.02:30:30.99#ibcon#first serial, iclass 40, count 2 2006.173.02:30:30.99#ibcon#enter sib2, iclass 40, count 2 2006.173.02:30:30.99#ibcon#flushed, iclass 40, count 2 2006.173.02:30:30.99#ibcon#about to write, iclass 40, count 2 2006.173.02:30:30.99#ibcon#wrote, iclass 40, count 2 2006.173.02:30:30.99#ibcon#about to read 3, iclass 40, count 2 2006.173.02:30:31.02#ibcon#read 3, iclass 40, count 2 2006.173.02:30:31.02#ibcon#about to read 4, iclass 40, count 2 2006.173.02:30:31.02#ibcon#read 4, iclass 40, count 2 2006.173.02:30:31.02#ibcon#about to read 5, iclass 40, count 2 2006.173.02:30:31.02#ibcon#read 5, iclass 40, count 2 2006.173.02:30:31.02#ibcon#about to read 6, iclass 40, count 2 2006.173.02:30:31.02#ibcon#read 6, iclass 40, count 2 2006.173.02:30:31.02#ibcon#end of sib2, iclass 40, count 2 2006.173.02:30:31.02#ibcon#*mode == 0, iclass 40, count 2 2006.173.02:30:31.02#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.02:30:31.02#ibcon#[25=AT05-04\r\n] 2006.173.02:30:31.02#ibcon#*before write, iclass 40, count 2 2006.173.02:30:31.02#ibcon#enter sib2, iclass 40, count 2 2006.173.02:30:31.02#ibcon#flushed, iclass 40, count 2 2006.173.02:30:31.02#ibcon#about to write, iclass 40, count 2 2006.173.02:30:31.02#ibcon#wrote, iclass 40, count 2 2006.173.02:30:31.02#ibcon#about to read 3, iclass 40, count 2 2006.173.02:30:31.05#ibcon#read 3, iclass 40, count 2 2006.173.02:30:31.05#ibcon#about to read 4, iclass 40, count 2 2006.173.02:30:31.05#ibcon#read 4, iclass 40, count 2 2006.173.02:30:31.05#ibcon#about to read 5, iclass 40, count 2 2006.173.02:30:31.05#ibcon#read 5, iclass 40, count 2 2006.173.02:30:31.05#ibcon#about to read 6, iclass 40, count 2 2006.173.02:30:31.05#ibcon#read 6, iclass 40, count 2 2006.173.02:30:31.05#ibcon#end of sib2, iclass 40, count 2 2006.173.02:30:31.05#ibcon#*after write, iclass 40, count 2 2006.173.02:30:31.05#ibcon#*before return 0, iclass 40, count 2 2006.173.02:30:31.05#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.02:30:31.05#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.02:30:31.05#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.02:30:31.05#ibcon#ireg 7 cls_cnt 0 2006.173.02:30:31.05#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.02:30:31.17#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.02:30:31.17#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.02:30:31.17#ibcon#enter wrdev, iclass 40, count 0 2006.173.02:30:31.17#ibcon#first serial, iclass 40, count 0 2006.173.02:30:31.17#ibcon#enter sib2, iclass 40, count 0 2006.173.02:30:31.17#ibcon#flushed, iclass 40, count 0 2006.173.02:30:31.17#ibcon#about to write, iclass 40, count 0 2006.173.02:30:31.17#ibcon#wrote, iclass 40, count 0 2006.173.02:30:31.17#ibcon#about to read 3, iclass 40, count 0 2006.173.02:30:31.19#ibcon#read 3, iclass 40, count 0 2006.173.02:30:31.19#ibcon#about to read 4, iclass 40, count 0 2006.173.02:30:31.19#ibcon#read 4, iclass 40, count 0 2006.173.02:30:31.19#ibcon#about to read 5, iclass 40, count 0 2006.173.02:30:31.19#ibcon#read 5, iclass 40, count 0 2006.173.02:30:31.19#ibcon#about to read 6, iclass 40, count 0 2006.173.02:30:31.19#ibcon#read 6, iclass 40, count 0 2006.173.02:30:31.19#ibcon#end of sib2, iclass 40, count 0 2006.173.02:30:31.19#ibcon#*mode == 0, iclass 40, count 0 2006.173.02:30:31.19#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.02:30:31.19#ibcon#[25=USB\r\n] 2006.173.02:30:31.19#ibcon#*before write, iclass 40, count 0 2006.173.02:30:31.19#ibcon#enter sib2, iclass 40, count 0 2006.173.02:30:31.19#ibcon#flushed, iclass 40, count 0 2006.173.02:30:31.19#ibcon#about to write, iclass 40, count 0 2006.173.02:30:31.19#ibcon#wrote, iclass 40, count 0 2006.173.02:30:31.19#ibcon#about to read 3, iclass 40, count 0 2006.173.02:30:31.22#ibcon#read 3, iclass 40, count 0 2006.173.02:30:31.22#ibcon#about to read 4, iclass 40, count 0 2006.173.02:30:31.22#ibcon#read 4, iclass 40, count 0 2006.173.02:30:31.22#ibcon#about to read 5, iclass 40, count 0 2006.173.02:30:31.22#ibcon#read 5, iclass 40, count 0 2006.173.02:30:31.22#ibcon#about to read 6, iclass 40, count 0 2006.173.02:30:31.22#ibcon#read 6, iclass 40, count 0 2006.173.02:30:31.22#ibcon#end of sib2, iclass 40, count 0 2006.173.02:30:31.22#ibcon#*after write, iclass 40, count 0 2006.173.02:30:31.22#ibcon#*before return 0, iclass 40, count 0 2006.173.02:30:31.22#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.02:30:31.22#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.02:30:31.22#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.02:30:31.22#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.02:30:31.22$vck44/valo=6,814.99 2006.173.02:30:31.22#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.02:30:31.22#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.02:30:31.22#ibcon#ireg 17 cls_cnt 0 2006.173.02:30:31.22#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.02:30:31.22#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.02:30:31.22#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.02:30:31.22#ibcon#enter wrdev, iclass 4, count 0 2006.173.02:30:31.22#ibcon#first serial, iclass 4, count 0 2006.173.02:30:31.22#ibcon#enter sib2, iclass 4, count 0 2006.173.02:30:31.22#ibcon#flushed, iclass 4, count 0 2006.173.02:30:31.22#ibcon#about to write, iclass 4, count 0 2006.173.02:30:31.22#ibcon#wrote, iclass 4, count 0 2006.173.02:30:31.22#ibcon#about to read 3, iclass 4, count 0 2006.173.02:30:31.24#ibcon#read 3, iclass 4, count 0 2006.173.02:30:31.24#ibcon#about to read 4, iclass 4, count 0 2006.173.02:30:31.24#ibcon#read 4, iclass 4, count 0 2006.173.02:30:31.24#ibcon#about to read 5, iclass 4, count 0 2006.173.02:30:31.24#ibcon#read 5, iclass 4, count 0 2006.173.02:30:31.24#ibcon#about to read 6, iclass 4, count 0 2006.173.02:30:31.24#ibcon#read 6, iclass 4, count 0 2006.173.02:30:31.24#ibcon#end of sib2, iclass 4, count 0 2006.173.02:30:31.24#ibcon#*mode == 0, iclass 4, count 0 2006.173.02:30:31.24#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.02:30:31.24#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.02:30:31.24#ibcon#*before write, iclass 4, count 0 2006.173.02:30:31.24#ibcon#enter sib2, iclass 4, count 0 2006.173.02:30:31.24#ibcon#flushed, iclass 4, count 0 2006.173.02:30:31.24#ibcon#about to write, iclass 4, count 0 2006.173.02:30:31.24#ibcon#wrote, iclass 4, count 0 2006.173.02:30:31.24#ibcon#about to read 3, iclass 4, count 0 2006.173.02:30:31.28#ibcon#read 3, iclass 4, count 0 2006.173.02:30:31.28#ibcon#about to read 4, iclass 4, count 0 2006.173.02:30:31.28#ibcon#read 4, iclass 4, count 0 2006.173.02:30:31.28#ibcon#about to read 5, iclass 4, count 0 2006.173.02:30:31.28#ibcon#read 5, iclass 4, count 0 2006.173.02:30:31.28#ibcon#about to read 6, iclass 4, count 0 2006.173.02:30:31.28#ibcon#read 6, iclass 4, count 0 2006.173.02:30:31.28#ibcon#end of sib2, iclass 4, count 0 2006.173.02:30:31.28#ibcon#*after write, iclass 4, count 0 2006.173.02:30:31.28#ibcon#*before return 0, iclass 4, count 0 2006.173.02:30:31.28#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.02:30:31.28#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.02:30:31.28#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.02:30:31.28#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.02:30:31.28$vck44/va=6,3 2006.173.02:30:31.28#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.02:30:31.28#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.02:30:31.28#ibcon#ireg 11 cls_cnt 2 2006.173.02:30:31.28#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.02:30:31.34#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.02:30:31.34#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.02:30:31.34#ibcon#enter wrdev, iclass 6, count 2 2006.173.02:30:31.34#ibcon#first serial, iclass 6, count 2 2006.173.02:30:31.34#ibcon#enter sib2, iclass 6, count 2 2006.173.02:30:31.34#ibcon#flushed, iclass 6, count 2 2006.173.02:30:31.34#ibcon#about to write, iclass 6, count 2 2006.173.02:30:31.34#ibcon#wrote, iclass 6, count 2 2006.173.02:30:31.34#ibcon#about to read 3, iclass 6, count 2 2006.173.02:30:31.36#ibcon#read 3, iclass 6, count 2 2006.173.02:30:31.36#ibcon#about to read 4, iclass 6, count 2 2006.173.02:30:31.36#ibcon#read 4, iclass 6, count 2 2006.173.02:30:31.36#ibcon#about to read 5, iclass 6, count 2 2006.173.02:30:31.36#ibcon#read 5, iclass 6, count 2 2006.173.02:30:31.36#ibcon#about to read 6, iclass 6, count 2 2006.173.02:30:31.36#ibcon#read 6, iclass 6, count 2 2006.173.02:30:31.36#ibcon#end of sib2, iclass 6, count 2 2006.173.02:30:31.36#ibcon#*mode == 0, iclass 6, count 2 2006.173.02:30:31.36#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.02:30:31.36#ibcon#[25=AT06-03\r\n] 2006.173.02:30:31.36#ibcon#*before write, iclass 6, count 2 2006.173.02:30:31.36#ibcon#enter sib2, iclass 6, count 2 2006.173.02:30:31.36#ibcon#flushed, iclass 6, count 2 2006.173.02:30:31.36#ibcon#about to write, iclass 6, count 2 2006.173.02:30:31.36#ibcon#wrote, iclass 6, count 2 2006.173.02:30:31.36#ibcon#about to read 3, iclass 6, count 2 2006.173.02:30:31.39#ibcon#read 3, iclass 6, count 2 2006.173.02:30:31.39#ibcon#about to read 4, iclass 6, count 2 2006.173.02:30:31.39#ibcon#read 4, iclass 6, count 2 2006.173.02:30:31.39#ibcon#about to read 5, iclass 6, count 2 2006.173.02:30:31.39#ibcon#read 5, iclass 6, count 2 2006.173.02:30:31.39#ibcon#about to read 6, iclass 6, count 2 2006.173.02:30:31.39#ibcon#read 6, iclass 6, count 2 2006.173.02:30:31.39#ibcon#end of sib2, iclass 6, count 2 2006.173.02:30:31.39#ibcon#*after write, iclass 6, count 2 2006.173.02:30:31.39#ibcon#*before return 0, iclass 6, count 2 2006.173.02:30:31.39#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.02:30:31.39#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.02:30:31.39#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.02:30:31.39#ibcon#ireg 7 cls_cnt 0 2006.173.02:30:31.39#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.02:30:31.51#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.02:30:31.51#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.02:30:31.51#ibcon#enter wrdev, iclass 6, count 0 2006.173.02:30:31.51#ibcon#first serial, iclass 6, count 0 2006.173.02:30:31.51#ibcon#enter sib2, iclass 6, count 0 2006.173.02:30:31.51#ibcon#flushed, iclass 6, count 0 2006.173.02:30:31.51#ibcon#about to write, iclass 6, count 0 2006.173.02:30:31.51#ibcon#wrote, iclass 6, count 0 2006.173.02:30:31.51#ibcon#about to read 3, iclass 6, count 0 2006.173.02:30:31.53#ibcon#read 3, iclass 6, count 0 2006.173.02:30:31.53#ibcon#about to read 4, iclass 6, count 0 2006.173.02:30:31.53#ibcon#read 4, iclass 6, count 0 2006.173.02:30:31.53#ibcon#about to read 5, iclass 6, count 0 2006.173.02:30:31.53#ibcon#read 5, iclass 6, count 0 2006.173.02:30:31.53#ibcon#about to read 6, iclass 6, count 0 2006.173.02:30:31.53#ibcon#read 6, iclass 6, count 0 2006.173.02:30:31.53#ibcon#end of sib2, iclass 6, count 0 2006.173.02:30:31.53#ibcon#*mode == 0, iclass 6, count 0 2006.173.02:30:31.53#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.02:30:31.53#ibcon#[25=USB\r\n] 2006.173.02:30:31.53#ibcon#*before write, iclass 6, count 0 2006.173.02:30:31.53#ibcon#enter sib2, iclass 6, count 0 2006.173.02:30:31.53#ibcon#flushed, iclass 6, count 0 2006.173.02:30:31.53#ibcon#about to write, iclass 6, count 0 2006.173.02:30:31.53#ibcon#wrote, iclass 6, count 0 2006.173.02:30:31.53#ibcon#about to read 3, iclass 6, count 0 2006.173.02:30:31.56#ibcon#read 3, iclass 6, count 0 2006.173.02:30:31.56#ibcon#about to read 4, iclass 6, count 0 2006.173.02:30:31.56#ibcon#read 4, iclass 6, count 0 2006.173.02:30:31.56#ibcon#about to read 5, iclass 6, count 0 2006.173.02:30:31.56#ibcon#read 5, iclass 6, count 0 2006.173.02:30:31.56#ibcon#about to read 6, iclass 6, count 0 2006.173.02:30:31.56#ibcon#read 6, iclass 6, count 0 2006.173.02:30:31.56#ibcon#end of sib2, iclass 6, count 0 2006.173.02:30:31.56#ibcon#*after write, iclass 6, count 0 2006.173.02:30:31.56#ibcon#*before return 0, iclass 6, count 0 2006.173.02:30:31.56#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.02:30:31.56#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.02:30:31.56#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.02:30:31.56#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.02:30:31.56$vck44/valo=7,864.99 2006.173.02:30:31.56#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.02:30:31.56#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.02:30:31.56#ibcon#ireg 17 cls_cnt 0 2006.173.02:30:31.56#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.02:30:31.56#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.02:30:31.56#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.02:30:31.56#ibcon#enter wrdev, iclass 10, count 0 2006.173.02:30:31.56#ibcon#first serial, iclass 10, count 0 2006.173.02:30:31.56#ibcon#enter sib2, iclass 10, count 0 2006.173.02:30:31.56#ibcon#flushed, iclass 10, count 0 2006.173.02:30:31.56#ibcon#about to write, iclass 10, count 0 2006.173.02:30:31.56#ibcon#wrote, iclass 10, count 0 2006.173.02:30:31.56#ibcon#about to read 3, iclass 10, count 0 2006.173.02:30:31.58#ibcon#read 3, iclass 10, count 0 2006.173.02:30:31.58#ibcon#about to read 4, iclass 10, count 0 2006.173.02:30:31.58#ibcon#read 4, iclass 10, count 0 2006.173.02:30:31.58#ibcon#about to read 5, iclass 10, count 0 2006.173.02:30:31.58#ibcon#read 5, iclass 10, count 0 2006.173.02:30:31.58#ibcon#about to read 6, iclass 10, count 0 2006.173.02:30:31.58#ibcon#read 6, iclass 10, count 0 2006.173.02:30:31.58#ibcon#end of sib2, iclass 10, count 0 2006.173.02:30:31.58#ibcon#*mode == 0, iclass 10, count 0 2006.173.02:30:31.58#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.02:30:31.58#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.02:30:31.58#ibcon#*before write, iclass 10, count 0 2006.173.02:30:31.58#ibcon#enter sib2, iclass 10, count 0 2006.173.02:30:31.58#ibcon#flushed, iclass 10, count 0 2006.173.02:30:31.58#ibcon#about to write, iclass 10, count 0 2006.173.02:30:31.58#ibcon#wrote, iclass 10, count 0 2006.173.02:30:31.58#ibcon#about to read 3, iclass 10, count 0 2006.173.02:30:31.62#ibcon#read 3, iclass 10, count 0 2006.173.02:30:31.62#ibcon#about to read 4, iclass 10, count 0 2006.173.02:30:31.62#ibcon#read 4, iclass 10, count 0 2006.173.02:30:31.62#ibcon#about to read 5, iclass 10, count 0 2006.173.02:30:31.62#ibcon#read 5, iclass 10, count 0 2006.173.02:30:31.62#ibcon#about to read 6, iclass 10, count 0 2006.173.02:30:31.62#ibcon#read 6, iclass 10, count 0 2006.173.02:30:31.62#ibcon#end of sib2, iclass 10, count 0 2006.173.02:30:31.62#ibcon#*after write, iclass 10, count 0 2006.173.02:30:31.62#ibcon#*before return 0, iclass 10, count 0 2006.173.02:30:31.62#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.02:30:31.62#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.02:30:31.62#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.02:30:31.62#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.02:30:31.62$vck44/va=7,4 2006.173.02:30:31.62#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.02:30:31.62#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.02:30:31.62#ibcon#ireg 11 cls_cnt 2 2006.173.02:30:31.62#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.02:30:31.68#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.02:30:31.68#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.02:30:31.68#ibcon#enter wrdev, iclass 12, count 2 2006.173.02:30:31.68#ibcon#first serial, iclass 12, count 2 2006.173.02:30:31.68#ibcon#enter sib2, iclass 12, count 2 2006.173.02:30:31.68#ibcon#flushed, iclass 12, count 2 2006.173.02:30:31.68#ibcon#about to write, iclass 12, count 2 2006.173.02:30:31.68#ibcon#wrote, iclass 12, count 2 2006.173.02:30:31.68#ibcon#about to read 3, iclass 12, count 2 2006.173.02:30:31.70#ibcon#read 3, iclass 12, count 2 2006.173.02:30:31.70#ibcon#about to read 4, iclass 12, count 2 2006.173.02:30:31.70#ibcon#read 4, iclass 12, count 2 2006.173.02:30:31.70#ibcon#about to read 5, iclass 12, count 2 2006.173.02:30:31.70#ibcon#read 5, iclass 12, count 2 2006.173.02:30:31.70#ibcon#about to read 6, iclass 12, count 2 2006.173.02:30:31.70#ibcon#read 6, iclass 12, count 2 2006.173.02:30:31.70#ibcon#end of sib2, iclass 12, count 2 2006.173.02:30:31.70#ibcon#*mode == 0, iclass 12, count 2 2006.173.02:30:31.70#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.02:30:31.70#ibcon#[25=AT07-04\r\n] 2006.173.02:30:31.70#ibcon#*before write, iclass 12, count 2 2006.173.02:30:31.70#ibcon#enter sib2, iclass 12, count 2 2006.173.02:30:31.70#ibcon#flushed, iclass 12, count 2 2006.173.02:30:31.70#ibcon#about to write, iclass 12, count 2 2006.173.02:30:31.70#ibcon#wrote, iclass 12, count 2 2006.173.02:30:31.70#ibcon#about to read 3, iclass 12, count 2 2006.173.02:30:31.73#ibcon#read 3, iclass 12, count 2 2006.173.02:30:31.73#ibcon#about to read 4, iclass 12, count 2 2006.173.02:30:31.73#ibcon#read 4, iclass 12, count 2 2006.173.02:30:31.73#ibcon#about to read 5, iclass 12, count 2 2006.173.02:30:31.73#ibcon#read 5, iclass 12, count 2 2006.173.02:30:31.73#ibcon#about to read 6, iclass 12, count 2 2006.173.02:30:31.73#ibcon#read 6, iclass 12, count 2 2006.173.02:30:31.73#ibcon#end of sib2, iclass 12, count 2 2006.173.02:30:31.73#ibcon#*after write, iclass 12, count 2 2006.173.02:30:31.73#ibcon#*before return 0, iclass 12, count 2 2006.173.02:30:31.73#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.02:30:31.73#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.02:30:31.73#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.02:30:31.73#ibcon#ireg 7 cls_cnt 0 2006.173.02:30:31.73#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.02:30:31.85#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.02:30:31.85#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.02:30:31.85#ibcon#enter wrdev, iclass 12, count 0 2006.173.02:30:31.85#ibcon#first serial, iclass 12, count 0 2006.173.02:30:31.85#ibcon#enter sib2, iclass 12, count 0 2006.173.02:30:31.85#ibcon#flushed, iclass 12, count 0 2006.173.02:30:31.85#ibcon#about to write, iclass 12, count 0 2006.173.02:30:31.85#ibcon#wrote, iclass 12, count 0 2006.173.02:30:31.85#ibcon#about to read 3, iclass 12, count 0 2006.173.02:30:31.87#ibcon#read 3, iclass 12, count 0 2006.173.02:30:31.87#ibcon#about to read 4, iclass 12, count 0 2006.173.02:30:31.87#ibcon#read 4, iclass 12, count 0 2006.173.02:30:31.87#ibcon#about to read 5, iclass 12, count 0 2006.173.02:30:31.87#ibcon#read 5, iclass 12, count 0 2006.173.02:30:31.87#ibcon#about to read 6, iclass 12, count 0 2006.173.02:30:31.87#ibcon#read 6, iclass 12, count 0 2006.173.02:30:31.87#ibcon#end of sib2, iclass 12, count 0 2006.173.02:30:31.87#ibcon#*mode == 0, iclass 12, count 0 2006.173.02:30:31.87#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.02:30:31.87#ibcon#[25=USB\r\n] 2006.173.02:30:31.87#ibcon#*before write, iclass 12, count 0 2006.173.02:30:31.87#ibcon#enter sib2, iclass 12, count 0 2006.173.02:30:31.87#ibcon#flushed, iclass 12, count 0 2006.173.02:30:31.87#ibcon#about to write, iclass 12, count 0 2006.173.02:30:31.87#ibcon#wrote, iclass 12, count 0 2006.173.02:30:31.87#ibcon#about to read 3, iclass 12, count 0 2006.173.02:30:31.90#ibcon#read 3, iclass 12, count 0 2006.173.02:30:31.90#ibcon#about to read 4, iclass 12, count 0 2006.173.02:30:31.90#ibcon#read 4, iclass 12, count 0 2006.173.02:30:31.90#ibcon#about to read 5, iclass 12, count 0 2006.173.02:30:31.90#ibcon#read 5, iclass 12, count 0 2006.173.02:30:31.90#ibcon#about to read 6, iclass 12, count 0 2006.173.02:30:31.90#ibcon#read 6, iclass 12, count 0 2006.173.02:30:31.90#ibcon#end of sib2, iclass 12, count 0 2006.173.02:30:31.90#ibcon#*after write, iclass 12, count 0 2006.173.02:30:31.90#ibcon#*before return 0, iclass 12, count 0 2006.173.02:30:31.90#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.02:30:31.90#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.02:30:31.90#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.02:30:31.90#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.02:30:31.90$vck44/valo=8,884.99 2006.173.02:30:31.90#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.02:30:31.90#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.02:30:31.90#ibcon#ireg 17 cls_cnt 0 2006.173.02:30:31.90#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.02:30:31.90#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.02:30:31.90#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.02:30:31.90#ibcon#enter wrdev, iclass 14, count 0 2006.173.02:30:31.90#ibcon#first serial, iclass 14, count 0 2006.173.02:30:31.90#ibcon#enter sib2, iclass 14, count 0 2006.173.02:30:31.90#ibcon#flushed, iclass 14, count 0 2006.173.02:30:31.90#ibcon#about to write, iclass 14, count 0 2006.173.02:30:31.90#ibcon#wrote, iclass 14, count 0 2006.173.02:30:31.90#ibcon#about to read 3, iclass 14, count 0 2006.173.02:30:31.92#ibcon#read 3, iclass 14, count 0 2006.173.02:30:31.92#ibcon#about to read 4, iclass 14, count 0 2006.173.02:30:31.92#ibcon#read 4, iclass 14, count 0 2006.173.02:30:31.92#ibcon#about to read 5, iclass 14, count 0 2006.173.02:30:31.92#ibcon#read 5, iclass 14, count 0 2006.173.02:30:31.92#ibcon#about to read 6, iclass 14, count 0 2006.173.02:30:31.92#ibcon#read 6, iclass 14, count 0 2006.173.02:30:31.92#ibcon#end of sib2, iclass 14, count 0 2006.173.02:30:31.92#ibcon#*mode == 0, iclass 14, count 0 2006.173.02:30:31.92#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.02:30:31.92#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.02:30:31.92#ibcon#*before write, iclass 14, count 0 2006.173.02:30:31.92#ibcon#enter sib2, iclass 14, count 0 2006.173.02:30:31.92#ibcon#flushed, iclass 14, count 0 2006.173.02:30:31.92#ibcon#about to write, iclass 14, count 0 2006.173.02:30:31.92#ibcon#wrote, iclass 14, count 0 2006.173.02:30:31.92#ibcon#about to read 3, iclass 14, count 0 2006.173.02:30:31.96#ibcon#read 3, iclass 14, count 0 2006.173.02:30:31.96#ibcon#about to read 4, iclass 14, count 0 2006.173.02:30:31.96#ibcon#read 4, iclass 14, count 0 2006.173.02:30:31.96#ibcon#about to read 5, iclass 14, count 0 2006.173.02:30:31.96#ibcon#read 5, iclass 14, count 0 2006.173.02:30:31.96#ibcon#about to read 6, iclass 14, count 0 2006.173.02:30:31.96#ibcon#read 6, iclass 14, count 0 2006.173.02:30:31.96#ibcon#end of sib2, iclass 14, count 0 2006.173.02:30:31.96#ibcon#*after write, iclass 14, count 0 2006.173.02:30:31.96#ibcon#*before return 0, iclass 14, count 0 2006.173.02:30:31.96#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.02:30:31.96#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.02:30:31.96#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.02:30:31.96#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.02:30:31.96$vck44/va=8,4 2006.173.02:30:31.96#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.02:30:31.96#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.02:30:31.96#ibcon#ireg 11 cls_cnt 2 2006.173.02:30:31.96#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.02:30:32.02#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.02:30:32.02#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.02:30:32.02#ibcon#enter wrdev, iclass 16, count 2 2006.173.02:30:32.02#ibcon#first serial, iclass 16, count 2 2006.173.02:30:32.02#ibcon#enter sib2, iclass 16, count 2 2006.173.02:30:32.02#ibcon#flushed, iclass 16, count 2 2006.173.02:30:32.02#ibcon#about to write, iclass 16, count 2 2006.173.02:30:32.02#ibcon#wrote, iclass 16, count 2 2006.173.02:30:32.02#ibcon#about to read 3, iclass 16, count 2 2006.173.02:30:32.04#ibcon#read 3, iclass 16, count 2 2006.173.02:30:32.04#ibcon#about to read 4, iclass 16, count 2 2006.173.02:30:32.04#ibcon#read 4, iclass 16, count 2 2006.173.02:30:32.04#ibcon#about to read 5, iclass 16, count 2 2006.173.02:30:32.04#ibcon#read 5, iclass 16, count 2 2006.173.02:30:32.04#ibcon#about to read 6, iclass 16, count 2 2006.173.02:30:32.04#ibcon#read 6, iclass 16, count 2 2006.173.02:30:32.04#ibcon#end of sib2, iclass 16, count 2 2006.173.02:30:32.04#ibcon#*mode == 0, iclass 16, count 2 2006.173.02:30:32.04#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.02:30:32.04#ibcon#[25=AT08-04\r\n] 2006.173.02:30:32.04#ibcon#*before write, iclass 16, count 2 2006.173.02:30:32.04#ibcon#enter sib2, iclass 16, count 2 2006.173.02:30:32.04#ibcon#flushed, iclass 16, count 2 2006.173.02:30:32.04#ibcon#about to write, iclass 16, count 2 2006.173.02:30:32.04#ibcon#wrote, iclass 16, count 2 2006.173.02:30:32.04#ibcon#about to read 3, iclass 16, count 2 2006.173.02:30:32.07#ibcon#read 3, iclass 16, count 2 2006.173.02:30:32.07#ibcon#about to read 4, iclass 16, count 2 2006.173.02:30:32.07#ibcon#read 4, iclass 16, count 2 2006.173.02:30:32.07#ibcon#about to read 5, iclass 16, count 2 2006.173.02:30:32.07#ibcon#read 5, iclass 16, count 2 2006.173.02:30:32.07#ibcon#about to read 6, iclass 16, count 2 2006.173.02:30:32.07#ibcon#read 6, iclass 16, count 2 2006.173.02:30:32.07#ibcon#end of sib2, iclass 16, count 2 2006.173.02:30:32.07#ibcon#*after write, iclass 16, count 2 2006.173.02:30:32.07#ibcon#*before return 0, iclass 16, count 2 2006.173.02:30:32.07#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.02:30:32.07#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.02:30:32.07#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.02:30:32.07#ibcon#ireg 7 cls_cnt 0 2006.173.02:30:32.07#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.02:30:32.19#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.02:30:32.19#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.02:30:32.19#ibcon#enter wrdev, iclass 16, count 0 2006.173.02:30:32.19#ibcon#first serial, iclass 16, count 0 2006.173.02:30:32.19#ibcon#enter sib2, iclass 16, count 0 2006.173.02:30:32.19#ibcon#flushed, iclass 16, count 0 2006.173.02:30:32.19#ibcon#about to write, iclass 16, count 0 2006.173.02:30:32.19#ibcon#wrote, iclass 16, count 0 2006.173.02:30:32.19#ibcon#about to read 3, iclass 16, count 0 2006.173.02:30:32.21#ibcon#read 3, iclass 16, count 0 2006.173.02:30:32.21#ibcon#about to read 4, iclass 16, count 0 2006.173.02:30:32.21#ibcon#read 4, iclass 16, count 0 2006.173.02:30:32.21#ibcon#about to read 5, iclass 16, count 0 2006.173.02:30:32.21#ibcon#read 5, iclass 16, count 0 2006.173.02:30:32.21#ibcon#about to read 6, iclass 16, count 0 2006.173.02:30:32.21#ibcon#read 6, iclass 16, count 0 2006.173.02:30:32.21#ibcon#end of sib2, iclass 16, count 0 2006.173.02:30:32.21#ibcon#*mode == 0, iclass 16, count 0 2006.173.02:30:32.21#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.02:30:32.21#ibcon#[25=USB\r\n] 2006.173.02:30:32.21#ibcon#*before write, iclass 16, count 0 2006.173.02:30:32.21#ibcon#enter sib2, iclass 16, count 0 2006.173.02:30:32.21#ibcon#flushed, iclass 16, count 0 2006.173.02:30:32.21#ibcon#about to write, iclass 16, count 0 2006.173.02:30:32.21#ibcon#wrote, iclass 16, count 0 2006.173.02:30:32.21#ibcon#about to read 3, iclass 16, count 0 2006.173.02:30:32.24#abcon#<5=/15 1.3 2.1 22.63 781006.5\r\n> 2006.173.02:30:32.24#ibcon#read 3, iclass 16, count 0 2006.173.02:30:32.24#ibcon#about to read 4, iclass 16, count 0 2006.173.02:30:32.24#ibcon#read 4, iclass 16, count 0 2006.173.02:30:32.24#ibcon#about to read 5, iclass 16, count 0 2006.173.02:30:32.24#ibcon#read 5, iclass 16, count 0 2006.173.02:30:32.24#ibcon#about to read 6, iclass 16, count 0 2006.173.02:30:32.24#ibcon#read 6, iclass 16, count 0 2006.173.02:30:32.24#ibcon#end of sib2, iclass 16, count 0 2006.173.02:30:32.24#ibcon#*after write, iclass 16, count 0 2006.173.02:30:32.24#ibcon#*before return 0, iclass 16, count 0 2006.173.02:30:32.24#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.02:30:32.24#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.02:30:32.24#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.02:30:32.24#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.02:30:32.24$vck44/vblo=1,629.99 2006.173.02:30:32.24#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.02:30:32.24#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.02:30:32.24#ibcon#ireg 17 cls_cnt 0 2006.173.02:30:32.24#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.02:30:32.24#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.02:30:32.24#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.02:30:32.24#ibcon#enter wrdev, iclass 21, count 0 2006.173.02:30:32.24#ibcon#first serial, iclass 21, count 0 2006.173.02:30:32.24#ibcon#enter sib2, iclass 21, count 0 2006.173.02:30:32.24#ibcon#flushed, iclass 21, count 0 2006.173.02:30:32.24#ibcon#about to write, iclass 21, count 0 2006.173.02:30:32.24#ibcon#wrote, iclass 21, count 0 2006.173.02:30:32.24#ibcon#about to read 3, iclass 21, count 0 2006.173.02:30:32.26#ibcon#read 3, iclass 21, count 0 2006.173.02:30:32.26#ibcon#about to read 4, iclass 21, count 0 2006.173.02:30:32.26#ibcon#read 4, iclass 21, count 0 2006.173.02:30:32.26#ibcon#about to read 5, iclass 21, count 0 2006.173.02:30:32.26#ibcon#read 5, iclass 21, count 0 2006.173.02:30:32.26#ibcon#about to read 6, iclass 21, count 0 2006.173.02:30:32.26#ibcon#read 6, iclass 21, count 0 2006.173.02:30:32.26#ibcon#end of sib2, iclass 21, count 0 2006.173.02:30:32.26#ibcon#*mode == 0, iclass 21, count 0 2006.173.02:30:32.26#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.02:30:32.26#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.02:30:32.26#ibcon#*before write, iclass 21, count 0 2006.173.02:30:32.26#ibcon#enter sib2, iclass 21, count 0 2006.173.02:30:32.26#ibcon#flushed, iclass 21, count 0 2006.173.02:30:32.26#ibcon#about to write, iclass 21, count 0 2006.173.02:30:32.26#ibcon#wrote, iclass 21, count 0 2006.173.02:30:32.26#ibcon#about to read 3, iclass 21, count 0 2006.173.02:30:32.26#abcon#{5=INTERFACE CLEAR} 2006.173.02:30:32.30#ibcon#read 3, iclass 21, count 0 2006.173.02:30:32.30#ibcon#about to read 4, iclass 21, count 0 2006.173.02:30:32.30#ibcon#read 4, iclass 21, count 0 2006.173.02:30:32.30#ibcon#about to read 5, iclass 21, count 0 2006.173.02:30:32.30#ibcon#read 5, iclass 21, count 0 2006.173.02:30:32.30#ibcon#about to read 6, iclass 21, count 0 2006.173.02:30:32.30#ibcon#read 6, iclass 21, count 0 2006.173.02:30:32.30#ibcon#end of sib2, iclass 21, count 0 2006.173.02:30:32.30#ibcon#*after write, iclass 21, count 0 2006.173.02:30:32.30#ibcon#*before return 0, iclass 21, count 0 2006.173.02:30:32.30#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.02:30:32.30#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.02:30:32.30#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.02:30:32.30#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.02:30:32.30$vck44/vb=1,4 2006.173.02:30:32.30#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.02:30:32.30#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.02:30:32.30#ibcon#ireg 11 cls_cnt 2 2006.173.02:30:32.30#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.02:30:32.30#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.02:30:32.30#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.02:30:32.30#ibcon#enter wrdev, iclass 23, count 2 2006.173.02:30:32.30#ibcon#first serial, iclass 23, count 2 2006.173.02:30:32.30#ibcon#enter sib2, iclass 23, count 2 2006.173.02:30:32.30#ibcon#flushed, iclass 23, count 2 2006.173.02:30:32.30#ibcon#about to write, iclass 23, count 2 2006.173.02:30:32.30#ibcon#wrote, iclass 23, count 2 2006.173.02:30:32.30#ibcon#about to read 3, iclass 23, count 2 2006.173.02:30:32.32#ibcon#read 3, iclass 23, count 2 2006.173.02:30:32.32#ibcon#about to read 4, iclass 23, count 2 2006.173.02:30:32.32#ibcon#read 4, iclass 23, count 2 2006.173.02:30:32.32#ibcon#about to read 5, iclass 23, count 2 2006.173.02:30:32.32#ibcon#read 5, iclass 23, count 2 2006.173.02:30:32.32#ibcon#about to read 6, iclass 23, count 2 2006.173.02:30:32.32#ibcon#read 6, iclass 23, count 2 2006.173.02:30:32.32#ibcon#end of sib2, iclass 23, count 2 2006.173.02:30:32.32#ibcon#*mode == 0, iclass 23, count 2 2006.173.02:30:32.32#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.02:30:32.32#ibcon#[27=AT01-04\r\n] 2006.173.02:30:32.32#ibcon#*before write, iclass 23, count 2 2006.173.02:30:32.32#ibcon#enter sib2, iclass 23, count 2 2006.173.02:30:32.32#ibcon#flushed, iclass 23, count 2 2006.173.02:30:32.32#ibcon#about to write, iclass 23, count 2 2006.173.02:30:32.32#ibcon#wrote, iclass 23, count 2 2006.173.02:30:32.32#ibcon#about to read 3, iclass 23, count 2 2006.173.02:30:32.32#abcon#[5=S1D000X0/0*\r\n] 2006.173.02:30:32.35#ibcon#read 3, iclass 23, count 2 2006.173.02:30:32.35#ibcon#about to read 4, iclass 23, count 2 2006.173.02:30:32.35#ibcon#read 4, iclass 23, count 2 2006.173.02:30:32.35#ibcon#about to read 5, iclass 23, count 2 2006.173.02:30:32.35#ibcon#read 5, iclass 23, count 2 2006.173.02:30:32.35#ibcon#about to read 6, iclass 23, count 2 2006.173.02:30:32.35#ibcon#read 6, iclass 23, count 2 2006.173.02:30:32.35#ibcon#end of sib2, iclass 23, count 2 2006.173.02:30:32.35#ibcon#*after write, iclass 23, count 2 2006.173.02:30:32.35#ibcon#*before return 0, iclass 23, count 2 2006.173.02:30:32.35#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.02:30:32.35#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.02:30:32.35#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.02:30:32.35#ibcon#ireg 7 cls_cnt 0 2006.173.02:30:32.35#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.02:30:32.47#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.02:30:32.47#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.02:30:32.47#ibcon#enter wrdev, iclass 23, count 0 2006.173.02:30:32.47#ibcon#first serial, iclass 23, count 0 2006.173.02:30:32.47#ibcon#enter sib2, iclass 23, count 0 2006.173.02:30:32.47#ibcon#flushed, iclass 23, count 0 2006.173.02:30:32.47#ibcon#about to write, iclass 23, count 0 2006.173.02:30:32.47#ibcon#wrote, iclass 23, count 0 2006.173.02:30:32.47#ibcon#about to read 3, iclass 23, count 0 2006.173.02:30:32.49#ibcon#read 3, iclass 23, count 0 2006.173.02:30:32.49#ibcon#about to read 4, iclass 23, count 0 2006.173.02:30:32.49#ibcon#read 4, iclass 23, count 0 2006.173.02:30:32.49#ibcon#about to read 5, iclass 23, count 0 2006.173.02:30:32.49#ibcon#read 5, iclass 23, count 0 2006.173.02:30:32.49#ibcon#about to read 6, iclass 23, count 0 2006.173.02:30:32.49#ibcon#read 6, iclass 23, count 0 2006.173.02:30:32.49#ibcon#end of sib2, iclass 23, count 0 2006.173.02:30:32.49#ibcon#*mode == 0, iclass 23, count 0 2006.173.02:30:32.49#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.02:30:32.49#ibcon#[27=USB\r\n] 2006.173.02:30:32.49#ibcon#*before write, iclass 23, count 0 2006.173.02:30:32.49#ibcon#enter sib2, iclass 23, count 0 2006.173.02:30:32.49#ibcon#flushed, iclass 23, count 0 2006.173.02:30:32.49#ibcon#about to write, iclass 23, count 0 2006.173.02:30:32.49#ibcon#wrote, iclass 23, count 0 2006.173.02:30:32.49#ibcon#about to read 3, iclass 23, count 0 2006.173.02:30:32.52#ibcon#read 3, iclass 23, count 0 2006.173.02:30:32.52#ibcon#about to read 4, iclass 23, count 0 2006.173.02:30:32.52#ibcon#read 4, iclass 23, count 0 2006.173.02:30:32.52#ibcon#about to read 5, iclass 23, count 0 2006.173.02:30:32.52#ibcon#read 5, iclass 23, count 0 2006.173.02:30:32.52#ibcon#about to read 6, iclass 23, count 0 2006.173.02:30:32.52#ibcon#read 6, iclass 23, count 0 2006.173.02:30:32.52#ibcon#end of sib2, iclass 23, count 0 2006.173.02:30:32.52#ibcon#*after write, iclass 23, count 0 2006.173.02:30:32.52#ibcon#*before return 0, iclass 23, count 0 2006.173.02:30:32.52#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.02:30:32.52#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.02:30:32.52#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.02:30:32.52#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.02:30:32.52$vck44/vblo=2,634.99 2006.173.02:30:32.52#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.02:30:32.52#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.02:30:32.52#ibcon#ireg 17 cls_cnt 0 2006.173.02:30:32.52#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.02:30:32.52#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.02:30:32.52#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.02:30:32.52#ibcon#enter wrdev, iclass 26, count 0 2006.173.02:30:32.52#ibcon#first serial, iclass 26, count 0 2006.173.02:30:32.52#ibcon#enter sib2, iclass 26, count 0 2006.173.02:30:32.52#ibcon#flushed, iclass 26, count 0 2006.173.02:30:32.52#ibcon#about to write, iclass 26, count 0 2006.173.02:30:32.52#ibcon#wrote, iclass 26, count 0 2006.173.02:30:32.52#ibcon#about to read 3, iclass 26, count 0 2006.173.02:30:32.54#ibcon#read 3, iclass 26, count 0 2006.173.02:30:32.54#ibcon#about to read 4, iclass 26, count 0 2006.173.02:30:32.54#ibcon#read 4, iclass 26, count 0 2006.173.02:30:32.54#ibcon#about to read 5, iclass 26, count 0 2006.173.02:30:32.54#ibcon#read 5, iclass 26, count 0 2006.173.02:30:32.54#ibcon#about to read 6, iclass 26, count 0 2006.173.02:30:32.54#ibcon#read 6, iclass 26, count 0 2006.173.02:30:32.54#ibcon#end of sib2, iclass 26, count 0 2006.173.02:30:32.54#ibcon#*mode == 0, iclass 26, count 0 2006.173.02:30:32.54#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.02:30:32.54#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.02:30:32.54#ibcon#*before write, iclass 26, count 0 2006.173.02:30:32.54#ibcon#enter sib2, iclass 26, count 0 2006.173.02:30:32.54#ibcon#flushed, iclass 26, count 0 2006.173.02:30:32.54#ibcon#about to write, iclass 26, count 0 2006.173.02:30:32.54#ibcon#wrote, iclass 26, count 0 2006.173.02:30:32.54#ibcon#about to read 3, iclass 26, count 0 2006.173.02:30:32.58#ibcon#read 3, iclass 26, count 0 2006.173.02:30:32.58#ibcon#about to read 4, iclass 26, count 0 2006.173.02:30:32.58#ibcon#read 4, iclass 26, count 0 2006.173.02:30:32.58#ibcon#about to read 5, iclass 26, count 0 2006.173.02:30:32.58#ibcon#read 5, iclass 26, count 0 2006.173.02:30:32.58#ibcon#about to read 6, iclass 26, count 0 2006.173.02:30:32.58#ibcon#read 6, iclass 26, count 0 2006.173.02:30:32.58#ibcon#end of sib2, iclass 26, count 0 2006.173.02:30:32.58#ibcon#*after write, iclass 26, count 0 2006.173.02:30:32.58#ibcon#*before return 0, iclass 26, count 0 2006.173.02:30:32.58#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.02:30:32.58#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.02:30:32.58#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.02:30:32.58#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.02:30:32.58$vck44/vb=2,4 2006.173.02:30:32.58#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.02:30:32.58#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.02:30:32.58#ibcon#ireg 11 cls_cnt 2 2006.173.02:30:32.58#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.02:30:32.64#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.02:30:32.64#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.02:30:32.64#ibcon#enter wrdev, iclass 28, count 2 2006.173.02:30:32.64#ibcon#first serial, iclass 28, count 2 2006.173.02:30:32.64#ibcon#enter sib2, iclass 28, count 2 2006.173.02:30:32.64#ibcon#flushed, iclass 28, count 2 2006.173.02:30:32.64#ibcon#about to write, iclass 28, count 2 2006.173.02:30:32.64#ibcon#wrote, iclass 28, count 2 2006.173.02:30:32.64#ibcon#about to read 3, iclass 28, count 2 2006.173.02:30:32.67#ibcon#read 3, iclass 28, count 2 2006.173.02:30:32.67#ibcon#about to read 4, iclass 28, count 2 2006.173.02:30:32.67#ibcon#read 4, iclass 28, count 2 2006.173.02:30:32.67#ibcon#about to read 5, iclass 28, count 2 2006.173.02:30:32.67#ibcon#read 5, iclass 28, count 2 2006.173.02:30:32.67#ibcon#about to read 6, iclass 28, count 2 2006.173.02:30:32.67#ibcon#read 6, iclass 28, count 2 2006.173.02:30:32.67#ibcon#end of sib2, iclass 28, count 2 2006.173.02:30:32.67#ibcon#*mode == 0, iclass 28, count 2 2006.173.02:30:32.67#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.02:30:32.67#ibcon#[27=AT02-04\r\n] 2006.173.02:30:32.67#ibcon#*before write, iclass 28, count 2 2006.173.02:30:32.67#ibcon#enter sib2, iclass 28, count 2 2006.173.02:30:32.67#ibcon#flushed, iclass 28, count 2 2006.173.02:30:32.67#ibcon#about to write, iclass 28, count 2 2006.173.02:30:32.67#ibcon#wrote, iclass 28, count 2 2006.173.02:30:32.67#ibcon#about to read 3, iclass 28, count 2 2006.173.02:30:32.70#ibcon#read 3, iclass 28, count 2 2006.173.02:30:32.70#ibcon#about to read 4, iclass 28, count 2 2006.173.02:30:32.70#ibcon#read 4, iclass 28, count 2 2006.173.02:30:32.70#ibcon#about to read 5, iclass 28, count 2 2006.173.02:30:32.70#ibcon#read 5, iclass 28, count 2 2006.173.02:30:32.70#ibcon#about to read 6, iclass 28, count 2 2006.173.02:30:32.70#ibcon#read 6, iclass 28, count 2 2006.173.02:30:32.70#ibcon#end of sib2, iclass 28, count 2 2006.173.02:30:32.70#ibcon#*after write, iclass 28, count 2 2006.173.02:30:32.70#ibcon#*before return 0, iclass 28, count 2 2006.173.02:30:32.70#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.02:30:32.70#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.02:30:32.70#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.02:30:32.70#ibcon#ireg 7 cls_cnt 0 2006.173.02:30:32.70#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.02:30:32.82#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.02:30:32.82#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.02:30:32.82#ibcon#enter wrdev, iclass 28, count 0 2006.173.02:30:32.82#ibcon#first serial, iclass 28, count 0 2006.173.02:30:32.82#ibcon#enter sib2, iclass 28, count 0 2006.173.02:30:32.82#ibcon#flushed, iclass 28, count 0 2006.173.02:30:32.82#ibcon#about to write, iclass 28, count 0 2006.173.02:30:32.82#ibcon#wrote, iclass 28, count 0 2006.173.02:30:32.82#ibcon#about to read 3, iclass 28, count 0 2006.173.02:30:32.84#ibcon#read 3, iclass 28, count 0 2006.173.02:30:32.84#ibcon#about to read 4, iclass 28, count 0 2006.173.02:30:32.84#ibcon#read 4, iclass 28, count 0 2006.173.02:30:32.84#ibcon#about to read 5, iclass 28, count 0 2006.173.02:30:32.84#ibcon#read 5, iclass 28, count 0 2006.173.02:30:32.84#ibcon#about to read 6, iclass 28, count 0 2006.173.02:30:32.84#ibcon#read 6, iclass 28, count 0 2006.173.02:30:32.84#ibcon#end of sib2, iclass 28, count 0 2006.173.02:30:32.84#ibcon#*mode == 0, iclass 28, count 0 2006.173.02:30:32.84#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.02:30:32.84#ibcon#[27=USB\r\n] 2006.173.02:30:32.84#ibcon#*before write, iclass 28, count 0 2006.173.02:30:32.84#ibcon#enter sib2, iclass 28, count 0 2006.173.02:30:32.84#ibcon#flushed, iclass 28, count 0 2006.173.02:30:32.84#ibcon#about to write, iclass 28, count 0 2006.173.02:30:32.84#ibcon#wrote, iclass 28, count 0 2006.173.02:30:32.84#ibcon#about to read 3, iclass 28, count 0 2006.173.02:30:32.87#ibcon#read 3, iclass 28, count 0 2006.173.02:30:32.87#ibcon#about to read 4, iclass 28, count 0 2006.173.02:30:32.87#ibcon#read 4, iclass 28, count 0 2006.173.02:30:32.87#ibcon#about to read 5, iclass 28, count 0 2006.173.02:30:32.87#ibcon#read 5, iclass 28, count 0 2006.173.02:30:32.87#ibcon#about to read 6, iclass 28, count 0 2006.173.02:30:32.87#ibcon#read 6, iclass 28, count 0 2006.173.02:30:32.87#ibcon#end of sib2, iclass 28, count 0 2006.173.02:30:32.87#ibcon#*after write, iclass 28, count 0 2006.173.02:30:32.87#ibcon#*before return 0, iclass 28, count 0 2006.173.02:30:32.87#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.02:30:32.87#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.02:30:32.87#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.02:30:32.87#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.02:30:32.87$vck44/vblo=3,649.99 2006.173.02:30:32.87#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.02:30:32.87#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.02:30:32.87#ibcon#ireg 17 cls_cnt 0 2006.173.02:30:32.87#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.02:30:32.87#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.02:30:32.87#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.02:30:32.87#ibcon#enter wrdev, iclass 30, count 0 2006.173.02:30:32.87#ibcon#first serial, iclass 30, count 0 2006.173.02:30:32.87#ibcon#enter sib2, iclass 30, count 0 2006.173.02:30:32.87#ibcon#flushed, iclass 30, count 0 2006.173.02:30:32.87#ibcon#about to write, iclass 30, count 0 2006.173.02:30:32.87#ibcon#wrote, iclass 30, count 0 2006.173.02:30:32.87#ibcon#about to read 3, iclass 30, count 0 2006.173.02:30:32.89#ibcon#read 3, iclass 30, count 0 2006.173.02:30:32.89#ibcon#about to read 4, iclass 30, count 0 2006.173.02:30:32.89#ibcon#read 4, iclass 30, count 0 2006.173.02:30:32.89#ibcon#about to read 5, iclass 30, count 0 2006.173.02:30:32.89#ibcon#read 5, iclass 30, count 0 2006.173.02:30:32.89#ibcon#about to read 6, iclass 30, count 0 2006.173.02:30:32.89#ibcon#read 6, iclass 30, count 0 2006.173.02:30:32.89#ibcon#end of sib2, iclass 30, count 0 2006.173.02:30:32.89#ibcon#*mode == 0, iclass 30, count 0 2006.173.02:30:32.89#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.02:30:32.89#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.02:30:32.89#ibcon#*before write, iclass 30, count 0 2006.173.02:30:32.89#ibcon#enter sib2, iclass 30, count 0 2006.173.02:30:32.89#ibcon#flushed, iclass 30, count 0 2006.173.02:30:32.89#ibcon#about to write, iclass 30, count 0 2006.173.02:30:32.89#ibcon#wrote, iclass 30, count 0 2006.173.02:30:32.89#ibcon#about to read 3, iclass 30, count 0 2006.173.02:30:32.93#ibcon#read 3, iclass 30, count 0 2006.173.02:30:32.93#ibcon#about to read 4, iclass 30, count 0 2006.173.02:30:32.93#ibcon#read 4, iclass 30, count 0 2006.173.02:30:32.93#ibcon#about to read 5, iclass 30, count 0 2006.173.02:30:32.93#ibcon#read 5, iclass 30, count 0 2006.173.02:30:32.93#ibcon#about to read 6, iclass 30, count 0 2006.173.02:30:32.93#ibcon#read 6, iclass 30, count 0 2006.173.02:30:32.93#ibcon#end of sib2, iclass 30, count 0 2006.173.02:30:32.93#ibcon#*after write, iclass 30, count 0 2006.173.02:30:32.93#ibcon#*before return 0, iclass 30, count 0 2006.173.02:30:32.93#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.02:30:32.93#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.02:30:32.93#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.02:30:32.93#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.02:30:32.93$vck44/vb=3,4 2006.173.02:30:32.93#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.173.02:30:32.93#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.173.02:30:32.93#ibcon#ireg 11 cls_cnt 2 2006.173.02:30:32.93#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.02:30:32.99#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.02:30:32.99#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.02:30:32.99#ibcon#enter wrdev, iclass 32, count 2 2006.173.02:30:32.99#ibcon#first serial, iclass 32, count 2 2006.173.02:30:32.99#ibcon#enter sib2, iclass 32, count 2 2006.173.02:30:32.99#ibcon#flushed, iclass 32, count 2 2006.173.02:30:32.99#ibcon#about to write, iclass 32, count 2 2006.173.02:30:32.99#ibcon#wrote, iclass 32, count 2 2006.173.02:30:32.99#ibcon#about to read 3, iclass 32, count 2 2006.173.02:30:33.01#ibcon#read 3, iclass 32, count 2 2006.173.02:30:33.01#ibcon#about to read 4, iclass 32, count 2 2006.173.02:30:33.01#ibcon#read 4, iclass 32, count 2 2006.173.02:30:33.01#ibcon#about to read 5, iclass 32, count 2 2006.173.02:30:33.01#ibcon#read 5, iclass 32, count 2 2006.173.02:30:33.01#ibcon#about to read 6, iclass 32, count 2 2006.173.02:30:33.01#ibcon#read 6, iclass 32, count 2 2006.173.02:30:33.01#ibcon#end of sib2, iclass 32, count 2 2006.173.02:30:33.01#ibcon#*mode == 0, iclass 32, count 2 2006.173.02:30:33.01#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.173.02:30:33.01#ibcon#[27=AT03-04\r\n] 2006.173.02:30:33.01#ibcon#*before write, iclass 32, count 2 2006.173.02:30:33.01#ibcon#enter sib2, iclass 32, count 2 2006.173.02:30:33.01#ibcon#flushed, iclass 32, count 2 2006.173.02:30:33.01#ibcon#about to write, iclass 32, count 2 2006.173.02:30:33.01#ibcon#wrote, iclass 32, count 2 2006.173.02:30:33.01#ibcon#about to read 3, iclass 32, count 2 2006.173.02:30:33.04#ibcon#read 3, iclass 32, count 2 2006.173.02:30:33.04#ibcon#about to read 4, iclass 32, count 2 2006.173.02:30:33.04#ibcon#read 4, iclass 32, count 2 2006.173.02:30:33.04#ibcon#about to read 5, iclass 32, count 2 2006.173.02:30:33.04#ibcon#read 5, iclass 32, count 2 2006.173.02:30:33.04#ibcon#about to read 6, iclass 32, count 2 2006.173.02:30:33.04#ibcon#read 6, iclass 32, count 2 2006.173.02:30:33.04#ibcon#end of sib2, iclass 32, count 2 2006.173.02:30:33.04#ibcon#*after write, iclass 32, count 2 2006.173.02:30:33.04#ibcon#*before return 0, iclass 32, count 2 2006.173.02:30:33.04#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.02:30:33.04#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.173.02:30:33.04#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.173.02:30:33.04#ibcon#ireg 7 cls_cnt 0 2006.173.02:30:33.04#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.02:30:33.16#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.02:30:33.16#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.02:30:33.16#ibcon#enter wrdev, iclass 32, count 0 2006.173.02:30:33.16#ibcon#first serial, iclass 32, count 0 2006.173.02:30:33.16#ibcon#enter sib2, iclass 32, count 0 2006.173.02:30:33.16#ibcon#flushed, iclass 32, count 0 2006.173.02:30:33.16#ibcon#about to write, iclass 32, count 0 2006.173.02:30:33.16#ibcon#wrote, iclass 32, count 0 2006.173.02:30:33.16#ibcon#about to read 3, iclass 32, count 0 2006.173.02:30:33.18#ibcon#read 3, iclass 32, count 0 2006.173.02:30:33.18#ibcon#about to read 4, iclass 32, count 0 2006.173.02:30:33.18#ibcon#read 4, iclass 32, count 0 2006.173.02:30:33.18#ibcon#about to read 5, iclass 32, count 0 2006.173.02:30:33.18#ibcon#read 5, iclass 32, count 0 2006.173.02:30:33.18#ibcon#about to read 6, iclass 32, count 0 2006.173.02:30:33.18#ibcon#read 6, iclass 32, count 0 2006.173.02:30:33.18#ibcon#end of sib2, iclass 32, count 0 2006.173.02:30:33.18#ibcon#*mode == 0, iclass 32, count 0 2006.173.02:30:33.18#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.02:30:33.18#ibcon#[27=USB\r\n] 2006.173.02:30:33.18#ibcon#*before write, iclass 32, count 0 2006.173.02:30:33.18#ibcon#enter sib2, iclass 32, count 0 2006.173.02:30:33.18#ibcon#flushed, iclass 32, count 0 2006.173.02:30:33.18#ibcon#about to write, iclass 32, count 0 2006.173.02:30:33.18#ibcon#wrote, iclass 32, count 0 2006.173.02:30:33.18#ibcon#about to read 3, iclass 32, count 0 2006.173.02:30:33.21#ibcon#read 3, iclass 32, count 0 2006.173.02:30:33.21#ibcon#about to read 4, iclass 32, count 0 2006.173.02:30:33.21#ibcon#read 4, iclass 32, count 0 2006.173.02:30:33.21#ibcon#about to read 5, iclass 32, count 0 2006.173.02:30:33.21#ibcon#read 5, iclass 32, count 0 2006.173.02:30:33.21#ibcon#about to read 6, iclass 32, count 0 2006.173.02:30:33.21#ibcon#read 6, iclass 32, count 0 2006.173.02:30:33.21#ibcon#end of sib2, iclass 32, count 0 2006.173.02:30:33.21#ibcon#*after write, iclass 32, count 0 2006.173.02:30:33.21#ibcon#*before return 0, iclass 32, count 0 2006.173.02:30:33.21#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.02:30:33.21#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.173.02:30:33.21#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.02:30:33.21#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.02:30:33.21$vck44/vblo=4,679.99 2006.173.02:30:33.21#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.02:30:33.21#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.02:30:33.21#ibcon#ireg 17 cls_cnt 0 2006.173.02:30:33.21#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.02:30:33.21#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.02:30:33.21#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.02:30:33.21#ibcon#enter wrdev, iclass 34, count 0 2006.173.02:30:33.21#ibcon#first serial, iclass 34, count 0 2006.173.02:30:33.21#ibcon#enter sib2, iclass 34, count 0 2006.173.02:30:33.21#ibcon#flushed, iclass 34, count 0 2006.173.02:30:33.21#ibcon#about to write, iclass 34, count 0 2006.173.02:30:33.21#ibcon#wrote, iclass 34, count 0 2006.173.02:30:33.21#ibcon#about to read 3, iclass 34, count 0 2006.173.02:30:33.23#ibcon#read 3, iclass 34, count 0 2006.173.02:30:33.23#ibcon#about to read 4, iclass 34, count 0 2006.173.02:30:33.23#ibcon#read 4, iclass 34, count 0 2006.173.02:30:33.23#ibcon#about to read 5, iclass 34, count 0 2006.173.02:30:33.23#ibcon#read 5, iclass 34, count 0 2006.173.02:30:33.23#ibcon#about to read 6, iclass 34, count 0 2006.173.02:30:33.23#ibcon#read 6, iclass 34, count 0 2006.173.02:30:33.23#ibcon#end of sib2, iclass 34, count 0 2006.173.02:30:33.23#ibcon#*mode == 0, iclass 34, count 0 2006.173.02:30:33.23#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.02:30:33.23#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.02:30:33.23#ibcon#*before write, iclass 34, count 0 2006.173.02:30:33.23#ibcon#enter sib2, iclass 34, count 0 2006.173.02:30:33.23#ibcon#flushed, iclass 34, count 0 2006.173.02:30:33.23#ibcon#about to write, iclass 34, count 0 2006.173.02:30:33.23#ibcon#wrote, iclass 34, count 0 2006.173.02:30:33.23#ibcon#about to read 3, iclass 34, count 0 2006.173.02:30:33.27#ibcon#read 3, iclass 34, count 0 2006.173.02:30:33.27#ibcon#about to read 4, iclass 34, count 0 2006.173.02:30:33.27#ibcon#read 4, iclass 34, count 0 2006.173.02:30:33.27#ibcon#about to read 5, iclass 34, count 0 2006.173.02:30:33.27#ibcon#read 5, iclass 34, count 0 2006.173.02:30:33.27#ibcon#about to read 6, iclass 34, count 0 2006.173.02:30:33.27#ibcon#read 6, iclass 34, count 0 2006.173.02:30:33.27#ibcon#end of sib2, iclass 34, count 0 2006.173.02:30:33.27#ibcon#*after write, iclass 34, count 0 2006.173.02:30:33.27#ibcon#*before return 0, iclass 34, count 0 2006.173.02:30:33.27#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.02:30:33.27#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.02:30:33.27#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.02:30:33.27#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.02:30:33.27$vck44/vb=4,4 2006.173.02:30:33.27#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.02:30:33.27#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.02:30:33.27#ibcon#ireg 11 cls_cnt 2 2006.173.02:30:33.27#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.02:30:33.33#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.02:30:33.33#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.02:30:33.33#ibcon#enter wrdev, iclass 36, count 2 2006.173.02:30:33.33#ibcon#first serial, iclass 36, count 2 2006.173.02:30:33.33#ibcon#enter sib2, iclass 36, count 2 2006.173.02:30:33.33#ibcon#flushed, iclass 36, count 2 2006.173.02:30:33.33#ibcon#about to write, iclass 36, count 2 2006.173.02:30:33.33#ibcon#wrote, iclass 36, count 2 2006.173.02:30:33.33#ibcon#about to read 3, iclass 36, count 2 2006.173.02:30:33.35#ibcon#read 3, iclass 36, count 2 2006.173.02:30:33.35#ibcon#about to read 4, iclass 36, count 2 2006.173.02:30:33.35#ibcon#read 4, iclass 36, count 2 2006.173.02:30:33.35#ibcon#about to read 5, iclass 36, count 2 2006.173.02:30:33.35#ibcon#read 5, iclass 36, count 2 2006.173.02:30:33.35#ibcon#about to read 6, iclass 36, count 2 2006.173.02:30:33.35#ibcon#read 6, iclass 36, count 2 2006.173.02:30:33.35#ibcon#end of sib2, iclass 36, count 2 2006.173.02:30:33.35#ibcon#*mode == 0, iclass 36, count 2 2006.173.02:30:33.35#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.02:30:33.35#ibcon#[27=AT04-04\r\n] 2006.173.02:30:33.35#ibcon#*before write, iclass 36, count 2 2006.173.02:30:33.35#ibcon#enter sib2, iclass 36, count 2 2006.173.02:30:33.35#ibcon#flushed, iclass 36, count 2 2006.173.02:30:33.35#ibcon#about to write, iclass 36, count 2 2006.173.02:30:33.35#ibcon#wrote, iclass 36, count 2 2006.173.02:30:33.35#ibcon#about to read 3, iclass 36, count 2 2006.173.02:30:33.38#ibcon#read 3, iclass 36, count 2 2006.173.02:30:33.38#ibcon#about to read 4, iclass 36, count 2 2006.173.02:30:33.38#ibcon#read 4, iclass 36, count 2 2006.173.02:30:33.38#ibcon#about to read 5, iclass 36, count 2 2006.173.02:30:33.38#ibcon#read 5, iclass 36, count 2 2006.173.02:30:33.38#ibcon#about to read 6, iclass 36, count 2 2006.173.02:30:33.38#ibcon#read 6, iclass 36, count 2 2006.173.02:30:33.38#ibcon#end of sib2, iclass 36, count 2 2006.173.02:30:33.38#ibcon#*after write, iclass 36, count 2 2006.173.02:30:33.38#ibcon#*before return 0, iclass 36, count 2 2006.173.02:30:33.38#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.02:30:33.38#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.02:30:33.38#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.02:30:33.38#ibcon#ireg 7 cls_cnt 0 2006.173.02:30:33.38#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.02:30:33.50#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.02:30:33.50#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.02:30:33.50#ibcon#enter wrdev, iclass 36, count 0 2006.173.02:30:33.50#ibcon#first serial, iclass 36, count 0 2006.173.02:30:33.50#ibcon#enter sib2, iclass 36, count 0 2006.173.02:30:33.50#ibcon#flushed, iclass 36, count 0 2006.173.02:30:33.50#ibcon#about to write, iclass 36, count 0 2006.173.02:30:33.50#ibcon#wrote, iclass 36, count 0 2006.173.02:30:33.50#ibcon#about to read 3, iclass 36, count 0 2006.173.02:30:33.52#ibcon#read 3, iclass 36, count 0 2006.173.02:30:33.52#ibcon#about to read 4, iclass 36, count 0 2006.173.02:30:33.52#ibcon#read 4, iclass 36, count 0 2006.173.02:30:33.52#ibcon#about to read 5, iclass 36, count 0 2006.173.02:30:33.52#ibcon#read 5, iclass 36, count 0 2006.173.02:30:33.52#ibcon#about to read 6, iclass 36, count 0 2006.173.02:30:33.52#ibcon#read 6, iclass 36, count 0 2006.173.02:30:33.52#ibcon#end of sib2, iclass 36, count 0 2006.173.02:30:33.52#ibcon#*mode == 0, iclass 36, count 0 2006.173.02:30:33.52#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.02:30:33.52#ibcon#[27=USB\r\n] 2006.173.02:30:33.52#ibcon#*before write, iclass 36, count 0 2006.173.02:30:33.52#ibcon#enter sib2, iclass 36, count 0 2006.173.02:30:33.52#ibcon#flushed, iclass 36, count 0 2006.173.02:30:33.52#ibcon#about to write, iclass 36, count 0 2006.173.02:30:33.52#ibcon#wrote, iclass 36, count 0 2006.173.02:30:33.52#ibcon#about to read 3, iclass 36, count 0 2006.173.02:30:33.55#ibcon#read 3, iclass 36, count 0 2006.173.02:30:33.55#ibcon#about to read 4, iclass 36, count 0 2006.173.02:30:33.55#ibcon#read 4, iclass 36, count 0 2006.173.02:30:33.55#ibcon#about to read 5, iclass 36, count 0 2006.173.02:30:33.55#ibcon#read 5, iclass 36, count 0 2006.173.02:30:33.55#ibcon#about to read 6, iclass 36, count 0 2006.173.02:30:33.55#ibcon#read 6, iclass 36, count 0 2006.173.02:30:33.55#ibcon#end of sib2, iclass 36, count 0 2006.173.02:30:33.55#ibcon#*after write, iclass 36, count 0 2006.173.02:30:33.55#ibcon#*before return 0, iclass 36, count 0 2006.173.02:30:33.55#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.02:30:33.55#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.02:30:33.55#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.02:30:33.55#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.02:30:33.55$vck44/vblo=5,709.99 2006.173.02:30:33.55#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.02:30:33.55#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.02:30:33.55#ibcon#ireg 17 cls_cnt 0 2006.173.02:30:33.55#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.02:30:33.55#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.02:30:33.55#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.02:30:33.55#ibcon#enter wrdev, iclass 38, count 0 2006.173.02:30:33.55#ibcon#first serial, iclass 38, count 0 2006.173.02:30:33.55#ibcon#enter sib2, iclass 38, count 0 2006.173.02:30:33.55#ibcon#flushed, iclass 38, count 0 2006.173.02:30:33.55#ibcon#about to write, iclass 38, count 0 2006.173.02:30:33.55#ibcon#wrote, iclass 38, count 0 2006.173.02:30:33.55#ibcon#about to read 3, iclass 38, count 0 2006.173.02:30:33.57#ibcon#read 3, iclass 38, count 0 2006.173.02:30:33.57#ibcon#about to read 4, iclass 38, count 0 2006.173.02:30:33.57#ibcon#read 4, iclass 38, count 0 2006.173.02:30:33.57#ibcon#about to read 5, iclass 38, count 0 2006.173.02:30:33.57#ibcon#read 5, iclass 38, count 0 2006.173.02:30:33.57#ibcon#about to read 6, iclass 38, count 0 2006.173.02:30:33.57#ibcon#read 6, iclass 38, count 0 2006.173.02:30:33.57#ibcon#end of sib2, iclass 38, count 0 2006.173.02:30:33.57#ibcon#*mode == 0, iclass 38, count 0 2006.173.02:30:33.57#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.02:30:33.57#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.02:30:33.57#ibcon#*before write, iclass 38, count 0 2006.173.02:30:33.57#ibcon#enter sib2, iclass 38, count 0 2006.173.02:30:33.57#ibcon#flushed, iclass 38, count 0 2006.173.02:30:33.57#ibcon#about to write, iclass 38, count 0 2006.173.02:30:33.57#ibcon#wrote, iclass 38, count 0 2006.173.02:30:33.57#ibcon#about to read 3, iclass 38, count 0 2006.173.02:30:33.61#ibcon#read 3, iclass 38, count 0 2006.173.02:30:33.61#ibcon#about to read 4, iclass 38, count 0 2006.173.02:30:33.61#ibcon#read 4, iclass 38, count 0 2006.173.02:30:33.61#ibcon#about to read 5, iclass 38, count 0 2006.173.02:30:33.61#ibcon#read 5, iclass 38, count 0 2006.173.02:30:33.61#ibcon#about to read 6, iclass 38, count 0 2006.173.02:30:33.61#ibcon#read 6, iclass 38, count 0 2006.173.02:30:33.61#ibcon#end of sib2, iclass 38, count 0 2006.173.02:30:33.61#ibcon#*after write, iclass 38, count 0 2006.173.02:30:33.61#ibcon#*before return 0, iclass 38, count 0 2006.173.02:30:33.61#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.02:30:33.61#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.02:30:33.61#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.02:30:33.61#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.02:30:33.61$vck44/vb=5,4 2006.173.02:30:33.61#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.02:30:33.61#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.02:30:33.61#ibcon#ireg 11 cls_cnt 2 2006.173.02:30:33.61#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.02:30:33.67#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.02:30:33.67#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.02:30:33.67#ibcon#enter wrdev, iclass 40, count 2 2006.173.02:30:33.67#ibcon#first serial, iclass 40, count 2 2006.173.02:30:33.67#ibcon#enter sib2, iclass 40, count 2 2006.173.02:30:33.67#ibcon#flushed, iclass 40, count 2 2006.173.02:30:33.67#ibcon#about to write, iclass 40, count 2 2006.173.02:30:33.67#ibcon#wrote, iclass 40, count 2 2006.173.02:30:33.67#ibcon#about to read 3, iclass 40, count 2 2006.173.02:30:33.69#ibcon#read 3, iclass 40, count 2 2006.173.02:30:33.69#ibcon#about to read 4, iclass 40, count 2 2006.173.02:30:33.69#ibcon#read 4, iclass 40, count 2 2006.173.02:30:33.69#ibcon#about to read 5, iclass 40, count 2 2006.173.02:30:33.69#ibcon#read 5, iclass 40, count 2 2006.173.02:30:33.69#ibcon#about to read 6, iclass 40, count 2 2006.173.02:30:33.69#ibcon#read 6, iclass 40, count 2 2006.173.02:30:33.69#ibcon#end of sib2, iclass 40, count 2 2006.173.02:30:33.69#ibcon#*mode == 0, iclass 40, count 2 2006.173.02:30:33.69#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.02:30:33.69#ibcon#[27=AT05-04\r\n] 2006.173.02:30:33.69#ibcon#*before write, iclass 40, count 2 2006.173.02:30:33.69#ibcon#enter sib2, iclass 40, count 2 2006.173.02:30:33.69#ibcon#flushed, iclass 40, count 2 2006.173.02:30:33.69#ibcon#about to write, iclass 40, count 2 2006.173.02:30:33.69#ibcon#wrote, iclass 40, count 2 2006.173.02:30:33.69#ibcon#about to read 3, iclass 40, count 2 2006.173.02:30:33.72#ibcon#read 3, iclass 40, count 2 2006.173.02:30:33.72#ibcon#about to read 4, iclass 40, count 2 2006.173.02:30:33.72#ibcon#read 4, iclass 40, count 2 2006.173.02:30:33.72#ibcon#about to read 5, iclass 40, count 2 2006.173.02:30:33.72#ibcon#read 5, iclass 40, count 2 2006.173.02:30:33.72#ibcon#about to read 6, iclass 40, count 2 2006.173.02:30:33.72#ibcon#read 6, iclass 40, count 2 2006.173.02:30:33.72#ibcon#end of sib2, iclass 40, count 2 2006.173.02:30:33.72#ibcon#*after write, iclass 40, count 2 2006.173.02:30:33.72#ibcon#*before return 0, iclass 40, count 2 2006.173.02:30:33.72#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.02:30:33.72#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.02:30:33.72#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.02:30:33.72#ibcon#ireg 7 cls_cnt 0 2006.173.02:30:33.72#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.02:30:33.84#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.02:30:33.84#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.02:30:33.84#ibcon#enter wrdev, iclass 40, count 0 2006.173.02:30:33.84#ibcon#first serial, iclass 40, count 0 2006.173.02:30:33.84#ibcon#enter sib2, iclass 40, count 0 2006.173.02:30:33.84#ibcon#flushed, iclass 40, count 0 2006.173.02:30:33.84#ibcon#about to write, iclass 40, count 0 2006.173.02:30:33.84#ibcon#wrote, iclass 40, count 0 2006.173.02:30:33.84#ibcon#about to read 3, iclass 40, count 0 2006.173.02:30:33.86#ibcon#read 3, iclass 40, count 0 2006.173.02:30:33.86#ibcon#about to read 4, iclass 40, count 0 2006.173.02:30:33.86#ibcon#read 4, iclass 40, count 0 2006.173.02:30:33.86#ibcon#about to read 5, iclass 40, count 0 2006.173.02:30:33.86#ibcon#read 5, iclass 40, count 0 2006.173.02:30:33.86#ibcon#about to read 6, iclass 40, count 0 2006.173.02:30:33.86#ibcon#read 6, iclass 40, count 0 2006.173.02:30:33.86#ibcon#end of sib2, iclass 40, count 0 2006.173.02:30:33.86#ibcon#*mode == 0, iclass 40, count 0 2006.173.02:30:33.86#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.02:30:33.86#ibcon#[27=USB\r\n] 2006.173.02:30:33.86#ibcon#*before write, iclass 40, count 0 2006.173.02:30:33.86#ibcon#enter sib2, iclass 40, count 0 2006.173.02:30:33.86#ibcon#flushed, iclass 40, count 0 2006.173.02:30:33.86#ibcon#about to write, iclass 40, count 0 2006.173.02:30:33.86#ibcon#wrote, iclass 40, count 0 2006.173.02:30:33.86#ibcon#about to read 3, iclass 40, count 0 2006.173.02:30:33.89#ibcon#read 3, iclass 40, count 0 2006.173.02:30:33.89#ibcon#about to read 4, iclass 40, count 0 2006.173.02:30:33.89#ibcon#read 4, iclass 40, count 0 2006.173.02:30:33.89#ibcon#about to read 5, iclass 40, count 0 2006.173.02:30:33.89#ibcon#read 5, iclass 40, count 0 2006.173.02:30:33.89#ibcon#about to read 6, iclass 40, count 0 2006.173.02:30:33.89#ibcon#read 6, iclass 40, count 0 2006.173.02:30:33.89#ibcon#end of sib2, iclass 40, count 0 2006.173.02:30:33.89#ibcon#*after write, iclass 40, count 0 2006.173.02:30:33.89#ibcon#*before return 0, iclass 40, count 0 2006.173.02:30:33.89#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.02:30:33.89#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.02:30:33.89#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.02:30:33.89#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.02:30:33.89$vck44/vblo=6,719.99 2006.173.02:30:33.89#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.02:30:33.89#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.02:30:33.89#ibcon#ireg 17 cls_cnt 0 2006.173.02:30:33.89#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.02:30:33.89#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.02:30:33.89#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.02:30:33.89#ibcon#enter wrdev, iclass 4, count 0 2006.173.02:30:33.89#ibcon#first serial, iclass 4, count 0 2006.173.02:30:33.89#ibcon#enter sib2, iclass 4, count 0 2006.173.02:30:33.89#ibcon#flushed, iclass 4, count 0 2006.173.02:30:33.89#ibcon#about to write, iclass 4, count 0 2006.173.02:30:33.89#ibcon#wrote, iclass 4, count 0 2006.173.02:30:33.89#ibcon#about to read 3, iclass 4, count 0 2006.173.02:30:33.91#ibcon#read 3, iclass 4, count 0 2006.173.02:30:33.91#ibcon#about to read 4, iclass 4, count 0 2006.173.02:30:33.91#ibcon#read 4, iclass 4, count 0 2006.173.02:30:33.91#ibcon#about to read 5, iclass 4, count 0 2006.173.02:30:33.91#ibcon#read 5, iclass 4, count 0 2006.173.02:30:33.91#ibcon#about to read 6, iclass 4, count 0 2006.173.02:30:33.91#ibcon#read 6, iclass 4, count 0 2006.173.02:30:33.91#ibcon#end of sib2, iclass 4, count 0 2006.173.02:30:33.91#ibcon#*mode == 0, iclass 4, count 0 2006.173.02:30:33.91#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.02:30:33.91#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.02:30:33.91#ibcon#*before write, iclass 4, count 0 2006.173.02:30:33.91#ibcon#enter sib2, iclass 4, count 0 2006.173.02:30:33.91#ibcon#flushed, iclass 4, count 0 2006.173.02:30:33.91#ibcon#about to write, iclass 4, count 0 2006.173.02:30:33.91#ibcon#wrote, iclass 4, count 0 2006.173.02:30:33.91#ibcon#about to read 3, iclass 4, count 0 2006.173.02:30:33.95#ibcon#read 3, iclass 4, count 0 2006.173.02:30:33.95#ibcon#about to read 4, iclass 4, count 0 2006.173.02:30:33.95#ibcon#read 4, iclass 4, count 0 2006.173.02:30:33.95#ibcon#about to read 5, iclass 4, count 0 2006.173.02:30:33.95#ibcon#read 5, iclass 4, count 0 2006.173.02:30:33.95#ibcon#about to read 6, iclass 4, count 0 2006.173.02:30:33.95#ibcon#read 6, iclass 4, count 0 2006.173.02:30:33.95#ibcon#end of sib2, iclass 4, count 0 2006.173.02:30:33.95#ibcon#*after write, iclass 4, count 0 2006.173.02:30:33.95#ibcon#*before return 0, iclass 4, count 0 2006.173.02:30:33.95#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.02:30:33.95#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.02:30:33.95#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.02:30:33.95#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.02:30:33.95$vck44/vb=6,4 2006.173.02:30:33.95#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.02:30:33.95#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.02:30:33.95#ibcon#ireg 11 cls_cnt 2 2006.173.02:30:33.95#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.02:30:34.01#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.02:30:34.01#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.02:30:34.01#ibcon#enter wrdev, iclass 6, count 2 2006.173.02:30:34.01#ibcon#first serial, iclass 6, count 2 2006.173.02:30:34.01#ibcon#enter sib2, iclass 6, count 2 2006.173.02:30:34.01#ibcon#flushed, iclass 6, count 2 2006.173.02:30:34.01#ibcon#about to write, iclass 6, count 2 2006.173.02:30:34.01#ibcon#wrote, iclass 6, count 2 2006.173.02:30:34.01#ibcon#about to read 3, iclass 6, count 2 2006.173.02:30:34.03#ibcon#read 3, iclass 6, count 2 2006.173.02:30:34.03#ibcon#about to read 4, iclass 6, count 2 2006.173.02:30:34.03#ibcon#read 4, iclass 6, count 2 2006.173.02:30:34.03#ibcon#about to read 5, iclass 6, count 2 2006.173.02:30:34.03#ibcon#read 5, iclass 6, count 2 2006.173.02:30:34.03#ibcon#about to read 6, iclass 6, count 2 2006.173.02:30:34.03#ibcon#read 6, iclass 6, count 2 2006.173.02:30:34.03#ibcon#end of sib2, iclass 6, count 2 2006.173.02:30:34.03#ibcon#*mode == 0, iclass 6, count 2 2006.173.02:30:34.03#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.02:30:34.03#ibcon#[27=AT06-04\r\n] 2006.173.02:30:34.03#ibcon#*before write, iclass 6, count 2 2006.173.02:30:34.03#ibcon#enter sib2, iclass 6, count 2 2006.173.02:30:34.03#ibcon#flushed, iclass 6, count 2 2006.173.02:30:34.03#ibcon#about to write, iclass 6, count 2 2006.173.02:30:34.03#ibcon#wrote, iclass 6, count 2 2006.173.02:30:34.03#ibcon#about to read 3, iclass 6, count 2 2006.173.02:30:34.06#ibcon#read 3, iclass 6, count 2 2006.173.02:30:34.06#ibcon#about to read 4, iclass 6, count 2 2006.173.02:30:34.06#ibcon#read 4, iclass 6, count 2 2006.173.02:30:34.06#ibcon#about to read 5, iclass 6, count 2 2006.173.02:30:34.06#ibcon#read 5, iclass 6, count 2 2006.173.02:30:34.06#ibcon#about to read 6, iclass 6, count 2 2006.173.02:30:34.06#ibcon#read 6, iclass 6, count 2 2006.173.02:30:34.06#ibcon#end of sib2, iclass 6, count 2 2006.173.02:30:34.06#ibcon#*after write, iclass 6, count 2 2006.173.02:30:34.06#ibcon#*before return 0, iclass 6, count 2 2006.173.02:30:34.06#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.02:30:34.06#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.02:30:34.06#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.02:30:34.06#ibcon#ireg 7 cls_cnt 0 2006.173.02:30:34.06#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.02:30:34.18#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.02:30:34.18#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.02:30:34.18#ibcon#enter wrdev, iclass 6, count 0 2006.173.02:30:34.18#ibcon#first serial, iclass 6, count 0 2006.173.02:30:34.18#ibcon#enter sib2, iclass 6, count 0 2006.173.02:30:34.18#ibcon#flushed, iclass 6, count 0 2006.173.02:30:34.18#ibcon#about to write, iclass 6, count 0 2006.173.02:30:34.18#ibcon#wrote, iclass 6, count 0 2006.173.02:30:34.18#ibcon#about to read 3, iclass 6, count 0 2006.173.02:30:34.20#ibcon#read 3, iclass 6, count 0 2006.173.02:30:34.20#ibcon#about to read 4, iclass 6, count 0 2006.173.02:30:34.20#ibcon#read 4, iclass 6, count 0 2006.173.02:30:34.20#ibcon#about to read 5, iclass 6, count 0 2006.173.02:30:34.20#ibcon#read 5, iclass 6, count 0 2006.173.02:30:34.20#ibcon#about to read 6, iclass 6, count 0 2006.173.02:30:34.20#ibcon#read 6, iclass 6, count 0 2006.173.02:30:34.20#ibcon#end of sib2, iclass 6, count 0 2006.173.02:30:34.20#ibcon#*mode == 0, iclass 6, count 0 2006.173.02:30:34.20#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.02:30:34.20#ibcon#[27=USB\r\n] 2006.173.02:30:34.20#ibcon#*before write, iclass 6, count 0 2006.173.02:30:34.20#ibcon#enter sib2, iclass 6, count 0 2006.173.02:30:34.20#ibcon#flushed, iclass 6, count 0 2006.173.02:30:34.20#ibcon#about to write, iclass 6, count 0 2006.173.02:30:34.20#ibcon#wrote, iclass 6, count 0 2006.173.02:30:34.20#ibcon#about to read 3, iclass 6, count 0 2006.173.02:30:34.23#ibcon#read 3, iclass 6, count 0 2006.173.02:30:34.23#ibcon#about to read 4, iclass 6, count 0 2006.173.02:30:34.23#ibcon#read 4, iclass 6, count 0 2006.173.02:30:34.23#ibcon#about to read 5, iclass 6, count 0 2006.173.02:30:34.23#ibcon#read 5, iclass 6, count 0 2006.173.02:30:34.23#ibcon#about to read 6, iclass 6, count 0 2006.173.02:30:34.23#ibcon#read 6, iclass 6, count 0 2006.173.02:30:34.23#ibcon#end of sib2, iclass 6, count 0 2006.173.02:30:34.23#ibcon#*after write, iclass 6, count 0 2006.173.02:30:34.23#ibcon#*before return 0, iclass 6, count 0 2006.173.02:30:34.23#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.02:30:34.23#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.02:30:34.23#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.02:30:34.23#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.02:30:34.23$vck44/vblo=7,734.99 2006.173.02:30:34.23#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.02:30:34.23#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.02:30:34.23#ibcon#ireg 17 cls_cnt 0 2006.173.02:30:34.23#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.02:30:34.23#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.02:30:34.23#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.02:30:34.23#ibcon#enter wrdev, iclass 10, count 0 2006.173.02:30:34.23#ibcon#first serial, iclass 10, count 0 2006.173.02:30:34.23#ibcon#enter sib2, iclass 10, count 0 2006.173.02:30:34.23#ibcon#flushed, iclass 10, count 0 2006.173.02:30:34.23#ibcon#about to write, iclass 10, count 0 2006.173.02:30:34.23#ibcon#wrote, iclass 10, count 0 2006.173.02:30:34.23#ibcon#about to read 3, iclass 10, count 0 2006.173.02:30:34.25#ibcon#read 3, iclass 10, count 0 2006.173.02:30:34.25#ibcon#about to read 4, iclass 10, count 0 2006.173.02:30:34.25#ibcon#read 4, iclass 10, count 0 2006.173.02:30:34.25#ibcon#about to read 5, iclass 10, count 0 2006.173.02:30:34.25#ibcon#read 5, iclass 10, count 0 2006.173.02:30:34.25#ibcon#about to read 6, iclass 10, count 0 2006.173.02:30:34.25#ibcon#read 6, iclass 10, count 0 2006.173.02:30:34.25#ibcon#end of sib2, iclass 10, count 0 2006.173.02:30:34.25#ibcon#*mode == 0, iclass 10, count 0 2006.173.02:30:34.25#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.02:30:34.25#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.02:30:34.25#ibcon#*before write, iclass 10, count 0 2006.173.02:30:34.25#ibcon#enter sib2, iclass 10, count 0 2006.173.02:30:34.25#ibcon#flushed, iclass 10, count 0 2006.173.02:30:34.25#ibcon#about to write, iclass 10, count 0 2006.173.02:30:34.25#ibcon#wrote, iclass 10, count 0 2006.173.02:30:34.25#ibcon#about to read 3, iclass 10, count 0 2006.173.02:30:34.29#ibcon#read 3, iclass 10, count 0 2006.173.02:30:34.29#ibcon#about to read 4, iclass 10, count 0 2006.173.02:30:34.29#ibcon#read 4, iclass 10, count 0 2006.173.02:30:34.29#ibcon#about to read 5, iclass 10, count 0 2006.173.02:30:34.29#ibcon#read 5, iclass 10, count 0 2006.173.02:30:34.29#ibcon#about to read 6, iclass 10, count 0 2006.173.02:30:34.29#ibcon#read 6, iclass 10, count 0 2006.173.02:30:34.29#ibcon#end of sib2, iclass 10, count 0 2006.173.02:30:34.29#ibcon#*after write, iclass 10, count 0 2006.173.02:30:34.29#ibcon#*before return 0, iclass 10, count 0 2006.173.02:30:34.29#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.02:30:34.29#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.02:30:34.29#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.02:30:34.29#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.02:30:34.29$vck44/vb=7,4 2006.173.02:30:34.29#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.02:30:34.29#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.02:30:34.29#ibcon#ireg 11 cls_cnt 2 2006.173.02:30:34.29#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.02:30:34.35#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.02:30:34.35#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.02:30:34.35#ibcon#enter wrdev, iclass 12, count 2 2006.173.02:30:34.35#ibcon#first serial, iclass 12, count 2 2006.173.02:30:34.35#ibcon#enter sib2, iclass 12, count 2 2006.173.02:30:34.35#ibcon#flushed, iclass 12, count 2 2006.173.02:30:34.35#ibcon#about to write, iclass 12, count 2 2006.173.02:30:34.35#ibcon#wrote, iclass 12, count 2 2006.173.02:30:34.35#ibcon#about to read 3, iclass 12, count 2 2006.173.02:30:34.37#ibcon#read 3, iclass 12, count 2 2006.173.02:30:34.37#ibcon#about to read 4, iclass 12, count 2 2006.173.02:30:34.37#ibcon#read 4, iclass 12, count 2 2006.173.02:30:34.37#ibcon#about to read 5, iclass 12, count 2 2006.173.02:30:34.37#ibcon#read 5, iclass 12, count 2 2006.173.02:30:34.37#ibcon#about to read 6, iclass 12, count 2 2006.173.02:30:34.37#ibcon#read 6, iclass 12, count 2 2006.173.02:30:34.37#ibcon#end of sib2, iclass 12, count 2 2006.173.02:30:34.37#ibcon#*mode == 0, iclass 12, count 2 2006.173.02:30:34.37#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.02:30:34.37#ibcon#[27=AT07-04\r\n] 2006.173.02:30:34.37#ibcon#*before write, iclass 12, count 2 2006.173.02:30:34.37#ibcon#enter sib2, iclass 12, count 2 2006.173.02:30:34.37#ibcon#flushed, iclass 12, count 2 2006.173.02:30:34.37#ibcon#about to write, iclass 12, count 2 2006.173.02:30:34.37#ibcon#wrote, iclass 12, count 2 2006.173.02:30:34.37#ibcon#about to read 3, iclass 12, count 2 2006.173.02:30:34.40#ibcon#read 3, iclass 12, count 2 2006.173.02:30:34.40#ibcon#about to read 4, iclass 12, count 2 2006.173.02:30:34.40#ibcon#read 4, iclass 12, count 2 2006.173.02:30:34.40#ibcon#about to read 5, iclass 12, count 2 2006.173.02:30:34.40#ibcon#read 5, iclass 12, count 2 2006.173.02:30:34.40#ibcon#about to read 6, iclass 12, count 2 2006.173.02:30:34.40#ibcon#read 6, iclass 12, count 2 2006.173.02:30:34.40#ibcon#end of sib2, iclass 12, count 2 2006.173.02:30:34.40#ibcon#*after write, iclass 12, count 2 2006.173.02:30:34.40#ibcon#*before return 0, iclass 12, count 2 2006.173.02:30:34.40#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.02:30:34.40#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.02:30:34.40#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.02:30:34.40#ibcon#ireg 7 cls_cnt 0 2006.173.02:30:34.40#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.02:30:34.52#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.02:30:34.52#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.02:30:34.52#ibcon#enter wrdev, iclass 12, count 0 2006.173.02:30:34.52#ibcon#first serial, iclass 12, count 0 2006.173.02:30:34.52#ibcon#enter sib2, iclass 12, count 0 2006.173.02:30:34.52#ibcon#flushed, iclass 12, count 0 2006.173.02:30:34.52#ibcon#about to write, iclass 12, count 0 2006.173.02:30:34.52#ibcon#wrote, iclass 12, count 0 2006.173.02:30:34.52#ibcon#about to read 3, iclass 12, count 0 2006.173.02:30:34.54#ibcon#read 3, iclass 12, count 0 2006.173.02:30:34.54#ibcon#about to read 4, iclass 12, count 0 2006.173.02:30:34.54#ibcon#read 4, iclass 12, count 0 2006.173.02:30:34.54#ibcon#about to read 5, iclass 12, count 0 2006.173.02:30:34.54#ibcon#read 5, iclass 12, count 0 2006.173.02:30:34.54#ibcon#about to read 6, iclass 12, count 0 2006.173.02:30:34.54#ibcon#read 6, iclass 12, count 0 2006.173.02:30:34.54#ibcon#end of sib2, iclass 12, count 0 2006.173.02:30:34.54#ibcon#*mode == 0, iclass 12, count 0 2006.173.02:30:34.54#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.02:30:34.54#ibcon#[27=USB\r\n] 2006.173.02:30:34.54#ibcon#*before write, iclass 12, count 0 2006.173.02:30:34.54#ibcon#enter sib2, iclass 12, count 0 2006.173.02:30:34.54#ibcon#flushed, iclass 12, count 0 2006.173.02:30:34.54#ibcon#about to write, iclass 12, count 0 2006.173.02:30:34.54#ibcon#wrote, iclass 12, count 0 2006.173.02:30:34.54#ibcon#about to read 3, iclass 12, count 0 2006.173.02:30:34.57#ibcon#read 3, iclass 12, count 0 2006.173.02:30:34.57#ibcon#about to read 4, iclass 12, count 0 2006.173.02:30:34.57#ibcon#read 4, iclass 12, count 0 2006.173.02:30:34.57#ibcon#about to read 5, iclass 12, count 0 2006.173.02:30:34.57#ibcon#read 5, iclass 12, count 0 2006.173.02:30:34.57#ibcon#about to read 6, iclass 12, count 0 2006.173.02:30:34.57#ibcon#read 6, iclass 12, count 0 2006.173.02:30:34.57#ibcon#end of sib2, iclass 12, count 0 2006.173.02:30:34.57#ibcon#*after write, iclass 12, count 0 2006.173.02:30:34.57#ibcon#*before return 0, iclass 12, count 0 2006.173.02:30:34.57#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.02:30:34.57#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.02:30:34.57#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.02:30:34.57#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.02:30:34.57$vck44/vblo=8,744.99 2006.173.02:30:34.57#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.02:30:34.57#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.02:30:34.57#ibcon#ireg 17 cls_cnt 0 2006.173.02:30:34.57#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.02:30:34.57#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.02:30:34.57#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.02:30:34.57#ibcon#enter wrdev, iclass 14, count 0 2006.173.02:30:34.57#ibcon#first serial, iclass 14, count 0 2006.173.02:30:34.57#ibcon#enter sib2, iclass 14, count 0 2006.173.02:30:34.57#ibcon#flushed, iclass 14, count 0 2006.173.02:30:34.57#ibcon#about to write, iclass 14, count 0 2006.173.02:30:34.57#ibcon#wrote, iclass 14, count 0 2006.173.02:30:34.57#ibcon#about to read 3, iclass 14, count 0 2006.173.02:30:34.59#ibcon#read 3, iclass 14, count 0 2006.173.02:30:34.59#ibcon#about to read 4, iclass 14, count 0 2006.173.02:30:34.59#ibcon#read 4, iclass 14, count 0 2006.173.02:30:34.59#ibcon#about to read 5, iclass 14, count 0 2006.173.02:30:34.59#ibcon#read 5, iclass 14, count 0 2006.173.02:30:34.59#ibcon#about to read 6, iclass 14, count 0 2006.173.02:30:34.59#ibcon#read 6, iclass 14, count 0 2006.173.02:30:34.59#ibcon#end of sib2, iclass 14, count 0 2006.173.02:30:34.59#ibcon#*mode == 0, iclass 14, count 0 2006.173.02:30:34.59#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.02:30:34.59#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.02:30:34.59#ibcon#*before write, iclass 14, count 0 2006.173.02:30:34.59#ibcon#enter sib2, iclass 14, count 0 2006.173.02:30:34.59#ibcon#flushed, iclass 14, count 0 2006.173.02:30:34.59#ibcon#about to write, iclass 14, count 0 2006.173.02:30:34.59#ibcon#wrote, iclass 14, count 0 2006.173.02:30:34.59#ibcon#about to read 3, iclass 14, count 0 2006.173.02:30:34.63#ibcon#read 3, iclass 14, count 0 2006.173.02:30:34.63#ibcon#about to read 4, iclass 14, count 0 2006.173.02:30:34.63#ibcon#read 4, iclass 14, count 0 2006.173.02:30:34.63#ibcon#about to read 5, iclass 14, count 0 2006.173.02:30:34.63#ibcon#read 5, iclass 14, count 0 2006.173.02:30:34.63#ibcon#about to read 6, iclass 14, count 0 2006.173.02:30:34.63#ibcon#read 6, iclass 14, count 0 2006.173.02:30:34.63#ibcon#end of sib2, iclass 14, count 0 2006.173.02:30:34.63#ibcon#*after write, iclass 14, count 0 2006.173.02:30:34.63#ibcon#*before return 0, iclass 14, count 0 2006.173.02:30:34.63#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.02:30:34.63#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.02:30:34.63#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.02:30:34.63#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.02:30:34.63$vck44/vb=8,4 2006.173.02:30:34.63#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.02:30:34.63#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.02:30:34.63#ibcon#ireg 11 cls_cnt 2 2006.173.02:30:34.63#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.02:30:34.69#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.02:30:34.69#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.02:30:34.69#ibcon#enter wrdev, iclass 16, count 2 2006.173.02:30:34.69#ibcon#first serial, iclass 16, count 2 2006.173.02:30:34.69#ibcon#enter sib2, iclass 16, count 2 2006.173.02:30:34.69#ibcon#flushed, iclass 16, count 2 2006.173.02:30:34.69#ibcon#about to write, iclass 16, count 2 2006.173.02:30:34.69#ibcon#wrote, iclass 16, count 2 2006.173.02:30:34.69#ibcon#about to read 3, iclass 16, count 2 2006.173.02:30:34.71#ibcon#read 3, iclass 16, count 2 2006.173.02:30:34.71#ibcon#about to read 4, iclass 16, count 2 2006.173.02:30:34.71#ibcon#read 4, iclass 16, count 2 2006.173.02:30:34.71#ibcon#about to read 5, iclass 16, count 2 2006.173.02:30:34.71#ibcon#read 5, iclass 16, count 2 2006.173.02:30:34.71#ibcon#about to read 6, iclass 16, count 2 2006.173.02:30:34.71#ibcon#read 6, iclass 16, count 2 2006.173.02:30:34.71#ibcon#end of sib2, iclass 16, count 2 2006.173.02:30:34.71#ibcon#*mode == 0, iclass 16, count 2 2006.173.02:30:34.71#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.02:30:34.71#ibcon#[27=AT08-04\r\n] 2006.173.02:30:34.71#ibcon#*before write, iclass 16, count 2 2006.173.02:30:34.71#ibcon#enter sib2, iclass 16, count 2 2006.173.02:30:34.71#ibcon#flushed, iclass 16, count 2 2006.173.02:30:34.71#ibcon#about to write, iclass 16, count 2 2006.173.02:30:34.71#ibcon#wrote, iclass 16, count 2 2006.173.02:30:34.71#ibcon#about to read 3, iclass 16, count 2 2006.173.02:30:34.74#ibcon#read 3, iclass 16, count 2 2006.173.02:30:34.74#ibcon#about to read 4, iclass 16, count 2 2006.173.02:30:34.74#ibcon#read 4, iclass 16, count 2 2006.173.02:30:34.74#ibcon#about to read 5, iclass 16, count 2 2006.173.02:30:34.74#ibcon#read 5, iclass 16, count 2 2006.173.02:30:34.74#ibcon#about to read 6, iclass 16, count 2 2006.173.02:30:34.74#ibcon#read 6, iclass 16, count 2 2006.173.02:30:34.74#ibcon#end of sib2, iclass 16, count 2 2006.173.02:30:34.74#ibcon#*after write, iclass 16, count 2 2006.173.02:30:34.74#ibcon#*before return 0, iclass 16, count 2 2006.173.02:30:34.74#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.02:30:34.74#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.02:30:34.74#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.02:30:34.74#ibcon#ireg 7 cls_cnt 0 2006.173.02:30:34.74#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.02:30:34.86#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.02:30:34.86#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.02:30:34.86#ibcon#enter wrdev, iclass 16, count 0 2006.173.02:30:34.86#ibcon#first serial, iclass 16, count 0 2006.173.02:30:34.86#ibcon#enter sib2, iclass 16, count 0 2006.173.02:30:34.86#ibcon#flushed, iclass 16, count 0 2006.173.02:30:34.86#ibcon#about to write, iclass 16, count 0 2006.173.02:30:34.86#ibcon#wrote, iclass 16, count 0 2006.173.02:30:34.86#ibcon#about to read 3, iclass 16, count 0 2006.173.02:30:34.88#ibcon#read 3, iclass 16, count 0 2006.173.02:30:34.88#ibcon#about to read 4, iclass 16, count 0 2006.173.02:30:34.88#ibcon#read 4, iclass 16, count 0 2006.173.02:30:34.88#ibcon#about to read 5, iclass 16, count 0 2006.173.02:30:34.88#ibcon#read 5, iclass 16, count 0 2006.173.02:30:34.88#ibcon#about to read 6, iclass 16, count 0 2006.173.02:30:34.88#ibcon#read 6, iclass 16, count 0 2006.173.02:30:34.88#ibcon#end of sib2, iclass 16, count 0 2006.173.02:30:34.88#ibcon#*mode == 0, iclass 16, count 0 2006.173.02:30:34.88#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.02:30:34.88#ibcon#[27=USB\r\n] 2006.173.02:30:34.88#ibcon#*before write, iclass 16, count 0 2006.173.02:30:34.88#ibcon#enter sib2, iclass 16, count 0 2006.173.02:30:34.88#ibcon#flushed, iclass 16, count 0 2006.173.02:30:34.88#ibcon#about to write, iclass 16, count 0 2006.173.02:30:34.88#ibcon#wrote, iclass 16, count 0 2006.173.02:30:34.88#ibcon#about to read 3, iclass 16, count 0 2006.173.02:30:34.91#ibcon#read 3, iclass 16, count 0 2006.173.02:30:34.91#ibcon#about to read 4, iclass 16, count 0 2006.173.02:30:34.91#ibcon#read 4, iclass 16, count 0 2006.173.02:30:34.91#ibcon#about to read 5, iclass 16, count 0 2006.173.02:30:34.91#ibcon#read 5, iclass 16, count 0 2006.173.02:30:34.91#ibcon#about to read 6, iclass 16, count 0 2006.173.02:30:34.91#ibcon#read 6, iclass 16, count 0 2006.173.02:30:34.91#ibcon#end of sib2, iclass 16, count 0 2006.173.02:30:34.91#ibcon#*after write, iclass 16, count 0 2006.173.02:30:34.91#ibcon#*before return 0, iclass 16, count 0 2006.173.02:30:34.91#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.02:30:34.91#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.02:30:34.91#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.02:30:34.91#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.02:30:34.91$vck44/vabw=wide 2006.173.02:30:34.91#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.02:30:34.91#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.02:30:34.91#ibcon#ireg 8 cls_cnt 0 2006.173.02:30:34.91#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.02:30:34.91#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.02:30:34.91#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.02:30:34.91#ibcon#enter wrdev, iclass 18, count 0 2006.173.02:30:34.91#ibcon#first serial, iclass 18, count 0 2006.173.02:30:34.91#ibcon#enter sib2, iclass 18, count 0 2006.173.02:30:34.91#ibcon#flushed, iclass 18, count 0 2006.173.02:30:34.91#ibcon#about to write, iclass 18, count 0 2006.173.02:30:34.91#ibcon#wrote, iclass 18, count 0 2006.173.02:30:34.91#ibcon#about to read 3, iclass 18, count 0 2006.173.02:30:34.93#ibcon#read 3, iclass 18, count 0 2006.173.02:30:34.93#ibcon#about to read 4, iclass 18, count 0 2006.173.02:30:34.93#ibcon#read 4, iclass 18, count 0 2006.173.02:30:34.93#ibcon#about to read 5, iclass 18, count 0 2006.173.02:30:34.93#ibcon#read 5, iclass 18, count 0 2006.173.02:30:34.93#ibcon#about to read 6, iclass 18, count 0 2006.173.02:30:34.93#ibcon#read 6, iclass 18, count 0 2006.173.02:30:34.93#ibcon#end of sib2, iclass 18, count 0 2006.173.02:30:34.93#ibcon#*mode == 0, iclass 18, count 0 2006.173.02:30:34.93#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.02:30:34.93#ibcon#[25=BW32\r\n] 2006.173.02:30:34.93#ibcon#*before write, iclass 18, count 0 2006.173.02:30:34.93#ibcon#enter sib2, iclass 18, count 0 2006.173.02:30:34.93#ibcon#flushed, iclass 18, count 0 2006.173.02:30:34.93#ibcon#about to write, iclass 18, count 0 2006.173.02:30:34.93#ibcon#wrote, iclass 18, count 0 2006.173.02:30:34.93#ibcon#about to read 3, iclass 18, count 0 2006.173.02:30:34.96#ibcon#read 3, iclass 18, count 0 2006.173.02:30:34.96#ibcon#about to read 4, iclass 18, count 0 2006.173.02:30:34.96#ibcon#read 4, iclass 18, count 0 2006.173.02:30:34.96#ibcon#about to read 5, iclass 18, count 0 2006.173.02:30:34.96#ibcon#read 5, iclass 18, count 0 2006.173.02:30:34.96#ibcon#about to read 6, iclass 18, count 0 2006.173.02:30:34.96#ibcon#read 6, iclass 18, count 0 2006.173.02:30:34.96#ibcon#end of sib2, iclass 18, count 0 2006.173.02:30:34.96#ibcon#*after write, iclass 18, count 0 2006.173.02:30:34.96#ibcon#*before return 0, iclass 18, count 0 2006.173.02:30:34.96#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.02:30:34.96#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.02:30:34.96#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.02:30:34.96#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.02:30:34.96$vck44/vbbw=wide 2006.173.02:30:34.96#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.02:30:34.96#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.02:30:34.96#ibcon#ireg 8 cls_cnt 0 2006.173.02:30:34.96#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.02:30:35.03#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.02:30:35.03#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.02:30:35.03#ibcon#enter wrdev, iclass 20, count 0 2006.173.02:30:35.03#ibcon#first serial, iclass 20, count 0 2006.173.02:30:35.03#ibcon#enter sib2, iclass 20, count 0 2006.173.02:30:35.03#ibcon#flushed, iclass 20, count 0 2006.173.02:30:35.03#ibcon#about to write, iclass 20, count 0 2006.173.02:30:35.03#ibcon#wrote, iclass 20, count 0 2006.173.02:30:35.03#ibcon#about to read 3, iclass 20, count 0 2006.173.02:30:35.05#ibcon#read 3, iclass 20, count 0 2006.173.02:30:35.05#ibcon#about to read 4, iclass 20, count 0 2006.173.02:30:35.05#ibcon#read 4, iclass 20, count 0 2006.173.02:30:35.05#ibcon#about to read 5, iclass 20, count 0 2006.173.02:30:35.05#ibcon#read 5, iclass 20, count 0 2006.173.02:30:35.05#ibcon#about to read 6, iclass 20, count 0 2006.173.02:30:35.05#ibcon#read 6, iclass 20, count 0 2006.173.02:30:35.05#ibcon#end of sib2, iclass 20, count 0 2006.173.02:30:35.05#ibcon#*mode == 0, iclass 20, count 0 2006.173.02:30:35.05#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.02:30:35.05#ibcon#[27=BW32\r\n] 2006.173.02:30:35.05#ibcon#*before write, iclass 20, count 0 2006.173.02:30:35.05#ibcon#enter sib2, iclass 20, count 0 2006.173.02:30:35.05#ibcon#flushed, iclass 20, count 0 2006.173.02:30:35.05#ibcon#about to write, iclass 20, count 0 2006.173.02:30:35.05#ibcon#wrote, iclass 20, count 0 2006.173.02:30:35.05#ibcon#about to read 3, iclass 20, count 0 2006.173.02:30:35.08#ibcon#read 3, iclass 20, count 0 2006.173.02:30:35.08#ibcon#about to read 4, iclass 20, count 0 2006.173.02:30:35.08#ibcon#read 4, iclass 20, count 0 2006.173.02:30:35.08#ibcon#about to read 5, iclass 20, count 0 2006.173.02:30:35.08#ibcon#read 5, iclass 20, count 0 2006.173.02:30:35.08#ibcon#about to read 6, iclass 20, count 0 2006.173.02:30:35.08#ibcon#read 6, iclass 20, count 0 2006.173.02:30:35.08#ibcon#end of sib2, iclass 20, count 0 2006.173.02:30:35.08#ibcon#*after write, iclass 20, count 0 2006.173.02:30:35.08#ibcon#*before return 0, iclass 20, count 0 2006.173.02:30:35.08#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.02:30:35.08#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.02:30:35.08#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.02:30:35.08#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.02:30:35.08$setupk4/ifdk4 2006.173.02:30:35.08$ifdk4/lo= 2006.173.02:30:35.08$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.02:30:35.08$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.02:30:35.08$ifdk4/patch= 2006.173.02:30:35.08$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.02:30:35.08$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.02:30:35.08$setupk4/!*+20s 2006.173.02:30:42.41#abcon#<5=/15 1.3 2.1 22.63 781006.5\r\n> 2006.173.02:30:42.43#abcon#{5=INTERFACE CLEAR} 2006.173.02:30:42.49#abcon#[5=S1D000X0/0*\r\n] 2006.173.02:30:49.51$setupk4/"tpicd 2006.173.02:30:49.51$setupk4/echo=off 2006.173.02:30:49.51$setupk4/xlog=off 2006.173.02:30:49.51:!2006.173.02:33:35 2006.173.02:31:29.14#trakl#Source acquired 2006.173.02:31:29.14#flagr#flagr/antenna,acquired 2006.173.02:33:35.00:preob 2006.173.02:33:36.13/onsource/TRACKING 2006.173.02:33:36.13:!2006.173.02:33:45 2006.173.02:33:45.00:"tape 2006.173.02:33:45.00:"st=record 2006.173.02:33:45.00:data_valid=on 2006.173.02:33:45.00:midob 2006.173.02:33:45.13/onsource/TRACKING 2006.173.02:33:45.13/wx/22.65,1006.5,81 2006.173.02:33:45.33/cable/+6.5103E-03 2006.173.02:33:46.42/va/01,07,usb,yes,35,38 2006.173.02:33:46.42/va/02,06,usb,yes,35,36 2006.173.02:33:46.42/va/03,05,usb,yes,45,47 2006.173.02:33:46.42/va/04,06,usb,yes,36,38 2006.173.02:33:46.42/va/05,04,usb,yes,28,29 2006.173.02:33:46.42/va/06,03,usb,yes,39,39 2006.173.02:33:46.42/va/07,04,usb,yes,32,33 2006.173.02:33:46.42/va/08,04,usb,yes,27,33 2006.173.02:33:46.65/valo/01,524.99,yes,locked 2006.173.02:33:46.65/valo/02,534.99,yes,locked 2006.173.02:33:46.65/valo/03,564.99,yes,locked 2006.173.02:33:46.65/valo/04,624.99,yes,locked 2006.173.02:33:46.65/valo/05,734.99,yes,locked 2006.173.02:33:46.65/valo/06,814.99,yes,locked 2006.173.02:33:46.65/valo/07,864.99,yes,locked 2006.173.02:33:46.65/valo/08,884.99,yes,locked 2006.173.02:33:47.74/vb/01,04,usb,yes,29,27 2006.173.02:33:47.74/vb/02,04,usb,yes,32,32 2006.173.02:33:47.74/vb/03,04,usb,yes,28,31 2006.173.02:33:47.74/vb/04,04,usb,yes,33,32 2006.173.02:33:47.74/vb/05,04,usb,yes,25,28 2006.173.02:33:47.74/vb/06,04,usb,yes,30,26 2006.173.02:33:47.74/vb/07,04,usb,yes,30,29 2006.173.02:33:47.74/vb/08,04,usb,yes,27,30 2006.173.02:33:47.97/vblo/01,629.99,yes,locked 2006.173.02:33:47.97/vblo/02,634.99,yes,locked 2006.173.02:33:47.97/vblo/03,649.99,yes,locked 2006.173.02:33:47.97/vblo/04,679.99,yes,locked 2006.173.02:33:47.97/vblo/05,709.99,yes,locked 2006.173.02:33:47.97/vblo/06,719.99,yes,locked 2006.173.02:33:47.97/vblo/07,734.99,yes,locked 2006.173.02:33:47.97/vblo/08,744.99,yes,locked 2006.173.02:33:48.12/vabw/8 2006.173.02:33:48.27/vbbw/8 2006.173.02:33:48.36/xfe/off,on,15.2 2006.173.02:33:48.74/ifatt/23,28,28,28 2006.173.02:33:49.08/fmout-gps/S +3.89E-07 2006.173.02:33:49.16:!2006.173.02:37:45 2006.173.02:37:45.00:data_valid=off 2006.173.02:37:45.00:"et 2006.173.02:37:45.00:!+3s 2006.173.02:37:48.02:"tape 2006.173.02:37:48.02:postob 2006.173.02:37:48.22/cable/+6.5123E-03 2006.173.02:37:48.22/wx/22.69,1006.6,82 2006.173.02:37:48.30/fmout-gps/S +3.89E-07 2006.173.02:37:48.31:scan_name=173-0240,jd0606,670 2006.173.02:37:48.31:source=1308+326,131028.66,322043.8,2000.0,ccw 2006.173.02:37:49.14#flagr#flagr/antenna,new-source 2006.173.02:37:49.14:checkk5 2006.173.02:37:49.55/chk_autoobs//k5ts1/ autoobs is running! 2006.173.02:37:50.11/chk_autoobs//k5ts2/ autoobs is running! 2006.173.02:37:50.53/chk_autoobs//k5ts3/ autoobs is running! 2006.173.02:37:50.94/chk_autoobs//k5ts4/ autoobs is running! 2006.173.02:37:51.32/chk_obsdata//k5ts1/T1730233??a.dat file size is correct (nominal:960MB, actual:956MB). 2006.173.02:37:51.77/chk_obsdata//k5ts2/T1730233??b.dat file size is correct (nominal:960MB, actual:956MB). 2006.173.02:37:52.16/chk_obsdata//k5ts3/T1730233??c.dat file size is correct (nominal:960MB, actual:956MB). 2006.173.02:37:52.54/chk_obsdata//k5ts4/T1730233??d.dat file size is correct (nominal:960MB, actual:956MB). 2006.173.02:37:53.24/k5log//k5ts1_log_newline 2006.173.02:37:53.93/k5log//k5ts2_log_newline 2006.173.02:37:54.62/k5log//k5ts3_log_newline 2006.173.02:37:55.32/k5log//k5ts4_log_newline 2006.173.02:37:55.34/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.02:37:55.34:setupk4=1 2006.173.02:37:55.34$setupk4/echo=on 2006.173.02:37:55.34$setupk4/pcalon 2006.173.02:37:55.34$pcalon/"no phase cal control is implemented here 2006.173.02:37:55.34$setupk4/"tpicd=stop 2006.173.02:37:55.34$setupk4/"rec=synch_on 2006.173.02:37:55.34$setupk4/"rec_mode=128 2006.173.02:37:55.34$setupk4/!* 2006.173.02:37:55.34$setupk4/recpk4 2006.173.02:37:55.34$recpk4/recpatch= 2006.173.02:37:55.34$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.02:37:55.34$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.02:37:55.34$setupk4/vck44 2006.173.02:37:55.34$vck44/valo=1,524.99 2006.173.02:37:55.34#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.02:37:55.34#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.02:37:55.34#ibcon#ireg 17 cls_cnt 0 2006.173.02:37:55.34#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.02:37:55.34#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.02:37:55.34#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.02:37:55.34#ibcon#enter wrdev, iclass 12, count 0 2006.173.02:37:55.34#ibcon#first serial, iclass 12, count 0 2006.173.02:37:55.34#ibcon#enter sib2, iclass 12, count 0 2006.173.02:37:55.34#ibcon#flushed, iclass 12, count 0 2006.173.02:37:55.34#ibcon#about to write, iclass 12, count 0 2006.173.02:37:55.34#ibcon#wrote, iclass 12, count 0 2006.173.02:37:55.34#ibcon#about to read 3, iclass 12, count 0 2006.173.02:37:55.36#ibcon#read 3, iclass 12, count 0 2006.173.02:37:55.36#ibcon#about to read 4, iclass 12, count 0 2006.173.02:37:55.36#ibcon#read 4, iclass 12, count 0 2006.173.02:37:55.36#ibcon#about to read 5, iclass 12, count 0 2006.173.02:37:55.36#ibcon#read 5, iclass 12, count 0 2006.173.02:37:55.36#ibcon#about to read 6, iclass 12, count 0 2006.173.02:37:55.36#ibcon#read 6, iclass 12, count 0 2006.173.02:37:55.36#ibcon#end of sib2, iclass 12, count 0 2006.173.02:37:55.36#ibcon#*mode == 0, iclass 12, count 0 2006.173.02:37:55.36#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.02:37:55.36#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.02:37:55.36#ibcon#*before write, iclass 12, count 0 2006.173.02:37:55.36#ibcon#enter sib2, iclass 12, count 0 2006.173.02:37:55.36#ibcon#flushed, iclass 12, count 0 2006.173.02:37:55.36#ibcon#about to write, iclass 12, count 0 2006.173.02:37:55.36#ibcon#wrote, iclass 12, count 0 2006.173.02:37:55.36#ibcon#about to read 3, iclass 12, count 0 2006.173.02:37:55.41#ibcon#read 3, iclass 12, count 0 2006.173.02:37:55.41#ibcon#about to read 4, iclass 12, count 0 2006.173.02:37:55.41#ibcon#read 4, iclass 12, count 0 2006.173.02:37:55.41#ibcon#about to read 5, iclass 12, count 0 2006.173.02:37:55.41#ibcon#read 5, iclass 12, count 0 2006.173.02:37:55.41#ibcon#about to read 6, iclass 12, count 0 2006.173.02:37:55.41#ibcon#read 6, iclass 12, count 0 2006.173.02:37:55.41#ibcon#end of sib2, iclass 12, count 0 2006.173.02:37:55.41#ibcon#*after write, iclass 12, count 0 2006.173.02:37:55.41#ibcon#*before return 0, iclass 12, count 0 2006.173.02:37:55.41#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.02:37:55.41#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.02:37:55.41#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.02:37:55.41#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.02:37:55.41$vck44/va=1,7 2006.173.02:37:55.41#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.02:37:55.41#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.02:37:55.41#ibcon#ireg 11 cls_cnt 2 2006.173.02:37:55.41#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.02:37:55.41#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.02:37:55.41#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.02:37:55.41#ibcon#enter wrdev, iclass 14, count 2 2006.173.02:37:55.41#ibcon#first serial, iclass 14, count 2 2006.173.02:37:55.41#ibcon#enter sib2, iclass 14, count 2 2006.173.02:37:55.41#ibcon#flushed, iclass 14, count 2 2006.173.02:37:55.41#ibcon#about to write, iclass 14, count 2 2006.173.02:37:55.41#ibcon#wrote, iclass 14, count 2 2006.173.02:37:55.41#ibcon#about to read 3, iclass 14, count 2 2006.173.02:37:55.43#ibcon#read 3, iclass 14, count 2 2006.173.02:37:55.43#ibcon#about to read 4, iclass 14, count 2 2006.173.02:37:55.43#ibcon#read 4, iclass 14, count 2 2006.173.02:37:55.43#ibcon#about to read 5, iclass 14, count 2 2006.173.02:37:55.43#ibcon#read 5, iclass 14, count 2 2006.173.02:37:55.43#ibcon#about to read 6, iclass 14, count 2 2006.173.02:37:55.43#ibcon#read 6, iclass 14, count 2 2006.173.02:37:55.43#ibcon#end of sib2, iclass 14, count 2 2006.173.02:37:55.43#ibcon#*mode == 0, iclass 14, count 2 2006.173.02:37:55.43#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.02:37:55.43#ibcon#[25=AT01-07\r\n] 2006.173.02:37:55.43#ibcon#*before write, iclass 14, count 2 2006.173.02:37:55.43#ibcon#enter sib2, iclass 14, count 2 2006.173.02:37:55.43#ibcon#flushed, iclass 14, count 2 2006.173.02:37:55.43#ibcon#about to write, iclass 14, count 2 2006.173.02:37:55.43#ibcon#wrote, iclass 14, count 2 2006.173.02:37:55.43#ibcon#about to read 3, iclass 14, count 2 2006.173.02:37:55.46#ibcon#read 3, iclass 14, count 2 2006.173.02:37:55.46#ibcon#about to read 4, iclass 14, count 2 2006.173.02:37:55.46#ibcon#read 4, iclass 14, count 2 2006.173.02:37:55.46#ibcon#about to read 5, iclass 14, count 2 2006.173.02:37:55.46#ibcon#read 5, iclass 14, count 2 2006.173.02:37:55.46#ibcon#about to read 6, iclass 14, count 2 2006.173.02:37:55.46#ibcon#read 6, iclass 14, count 2 2006.173.02:37:55.46#ibcon#end of sib2, iclass 14, count 2 2006.173.02:37:55.46#ibcon#*after write, iclass 14, count 2 2006.173.02:37:55.46#ibcon#*before return 0, iclass 14, count 2 2006.173.02:37:55.46#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.02:37:55.46#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.02:37:55.46#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.02:37:55.46#ibcon#ireg 7 cls_cnt 0 2006.173.02:37:55.46#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.02:37:55.58#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.02:37:55.58#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.02:37:55.58#ibcon#enter wrdev, iclass 14, count 0 2006.173.02:37:55.58#ibcon#first serial, iclass 14, count 0 2006.173.02:37:55.58#ibcon#enter sib2, iclass 14, count 0 2006.173.02:37:55.58#ibcon#flushed, iclass 14, count 0 2006.173.02:37:55.58#ibcon#about to write, iclass 14, count 0 2006.173.02:37:55.58#ibcon#wrote, iclass 14, count 0 2006.173.02:37:55.58#ibcon#about to read 3, iclass 14, count 0 2006.173.02:37:55.60#ibcon#read 3, iclass 14, count 0 2006.173.02:37:55.60#ibcon#about to read 4, iclass 14, count 0 2006.173.02:37:55.60#ibcon#read 4, iclass 14, count 0 2006.173.02:37:55.60#ibcon#about to read 5, iclass 14, count 0 2006.173.02:37:55.60#ibcon#read 5, iclass 14, count 0 2006.173.02:37:55.60#ibcon#about to read 6, iclass 14, count 0 2006.173.02:37:55.60#ibcon#read 6, iclass 14, count 0 2006.173.02:37:55.60#ibcon#end of sib2, iclass 14, count 0 2006.173.02:37:55.60#ibcon#*mode == 0, iclass 14, count 0 2006.173.02:37:55.60#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.02:37:55.60#ibcon#[25=USB\r\n] 2006.173.02:37:55.60#ibcon#*before write, iclass 14, count 0 2006.173.02:37:55.60#ibcon#enter sib2, iclass 14, count 0 2006.173.02:37:55.60#ibcon#flushed, iclass 14, count 0 2006.173.02:37:55.60#ibcon#about to write, iclass 14, count 0 2006.173.02:37:55.60#ibcon#wrote, iclass 14, count 0 2006.173.02:37:55.60#ibcon#about to read 3, iclass 14, count 0 2006.173.02:37:55.63#ibcon#read 3, iclass 14, count 0 2006.173.02:37:55.63#ibcon#about to read 4, iclass 14, count 0 2006.173.02:37:55.63#ibcon#read 4, iclass 14, count 0 2006.173.02:37:55.63#ibcon#about to read 5, iclass 14, count 0 2006.173.02:37:55.63#ibcon#read 5, iclass 14, count 0 2006.173.02:37:55.63#ibcon#about to read 6, iclass 14, count 0 2006.173.02:37:55.63#ibcon#read 6, iclass 14, count 0 2006.173.02:37:55.63#ibcon#end of sib2, iclass 14, count 0 2006.173.02:37:55.63#ibcon#*after write, iclass 14, count 0 2006.173.02:37:55.63#ibcon#*before return 0, iclass 14, count 0 2006.173.02:37:55.63#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.02:37:55.63#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.02:37:55.63#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.02:37:55.63#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.02:37:55.63$vck44/valo=2,534.99 2006.173.02:37:55.63#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.02:37:55.63#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.02:37:55.63#ibcon#ireg 17 cls_cnt 0 2006.173.02:37:55.63#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.02:37:55.63#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.02:37:55.63#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.02:37:55.63#ibcon#enter wrdev, iclass 16, count 0 2006.173.02:37:55.63#ibcon#first serial, iclass 16, count 0 2006.173.02:37:55.63#ibcon#enter sib2, iclass 16, count 0 2006.173.02:37:55.63#ibcon#flushed, iclass 16, count 0 2006.173.02:37:55.63#ibcon#about to write, iclass 16, count 0 2006.173.02:37:55.63#ibcon#wrote, iclass 16, count 0 2006.173.02:37:55.63#ibcon#about to read 3, iclass 16, count 0 2006.173.02:37:55.65#ibcon#read 3, iclass 16, count 0 2006.173.02:37:55.65#ibcon#about to read 4, iclass 16, count 0 2006.173.02:37:55.65#ibcon#read 4, iclass 16, count 0 2006.173.02:37:55.65#ibcon#about to read 5, iclass 16, count 0 2006.173.02:37:55.65#ibcon#read 5, iclass 16, count 0 2006.173.02:37:55.65#ibcon#about to read 6, iclass 16, count 0 2006.173.02:37:55.65#ibcon#read 6, iclass 16, count 0 2006.173.02:37:55.65#ibcon#end of sib2, iclass 16, count 0 2006.173.02:37:55.65#ibcon#*mode == 0, iclass 16, count 0 2006.173.02:37:55.65#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.02:37:55.65#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.02:37:55.65#ibcon#*before write, iclass 16, count 0 2006.173.02:37:55.65#ibcon#enter sib2, iclass 16, count 0 2006.173.02:37:55.65#ibcon#flushed, iclass 16, count 0 2006.173.02:37:55.65#ibcon#about to write, iclass 16, count 0 2006.173.02:37:55.65#ibcon#wrote, iclass 16, count 0 2006.173.02:37:55.65#ibcon#about to read 3, iclass 16, count 0 2006.173.02:37:55.69#ibcon#read 3, iclass 16, count 0 2006.173.02:37:55.69#ibcon#about to read 4, iclass 16, count 0 2006.173.02:37:55.69#ibcon#read 4, iclass 16, count 0 2006.173.02:37:55.69#ibcon#about to read 5, iclass 16, count 0 2006.173.02:37:55.69#ibcon#read 5, iclass 16, count 0 2006.173.02:37:55.69#ibcon#about to read 6, iclass 16, count 0 2006.173.02:37:55.69#ibcon#read 6, iclass 16, count 0 2006.173.02:37:55.69#ibcon#end of sib2, iclass 16, count 0 2006.173.02:37:55.69#ibcon#*after write, iclass 16, count 0 2006.173.02:37:55.69#ibcon#*before return 0, iclass 16, count 0 2006.173.02:37:55.69#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.02:37:55.69#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.02:37:55.69#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.02:37:55.69#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.02:37:55.69$vck44/va=2,6 2006.173.02:37:55.69#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.02:37:55.69#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.02:37:55.69#ibcon#ireg 11 cls_cnt 2 2006.173.02:37:55.69#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.02:37:55.75#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.02:37:55.75#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.02:37:55.75#ibcon#enter wrdev, iclass 18, count 2 2006.173.02:37:55.75#ibcon#first serial, iclass 18, count 2 2006.173.02:37:55.75#ibcon#enter sib2, iclass 18, count 2 2006.173.02:37:55.75#ibcon#flushed, iclass 18, count 2 2006.173.02:37:55.75#ibcon#about to write, iclass 18, count 2 2006.173.02:37:55.75#ibcon#wrote, iclass 18, count 2 2006.173.02:37:55.75#ibcon#about to read 3, iclass 18, count 2 2006.173.02:37:55.77#ibcon#read 3, iclass 18, count 2 2006.173.02:37:55.77#ibcon#about to read 4, iclass 18, count 2 2006.173.02:37:55.77#ibcon#read 4, iclass 18, count 2 2006.173.02:37:55.77#ibcon#about to read 5, iclass 18, count 2 2006.173.02:37:55.77#ibcon#read 5, iclass 18, count 2 2006.173.02:37:55.77#ibcon#about to read 6, iclass 18, count 2 2006.173.02:37:55.77#ibcon#read 6, iclass 18, count 2 2006.173.02:37:55.77#ibcon#end of sib2, iclass 18, count 2 2006.173.02:37:55.77#ibcon#*mode == 0, iclass 18, count 2 2006.173.02:37:55.77#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.02:37:55.77#ibcon#[25=AT02-06\r\n] 2006.173.02:37:55.77#ibcon#*before write, iclass 18, count 2 2006.173.02:37:55.77#ibcon#enter sib2, iclass 18, count 2 2006.173.02:37:55.77#ibcon#flushed, iclass 18, count 2 2006.173.02:37:55.77#ibcon#about to write, iclass 18, count 2 2006.173.02:37:55.77#ibcon#wrote, iclass 18, count 2 2006.173.02:37:55.77#ibcon#about to read 3, iclass 18, count 2 2006.173.02:37:55.81#ibcon#read 3, iclass 18, count 2 2006.173.02:37:55.81#ibcon#about to read 4, iclass 18, count 2 2006.173.02:37:55.81#ibcon#read 4, iclass 18, count 2 2006.173.02:37:55.81#ibcon#about to read 5, iclass 18, count 2 2006.173.02:37:55.81#ibcon#read 5, iclass 18, count 2 2006.173.02:37:55.81#ibcon#about to read 6, iclass 18, count 2 2006.173.02:37:55.81#ibcon#read 6, iclass 18, count 2 2006.173.02:37:55.81#ibcon#end of sib2, iclass 18, count 2 2006.173.02:37:55.81#ibcon#*after write, iclass 18, count 2 2006.173.02:37:55.81#ibcon#*before return 0, iclass 18, count 2 2006.173.02:37:55.81#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.02:37:55.81#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.02:37:55.81#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.02:37:55.81#ibcon#ireg 7 cls_cnt 0 2006.173.02:37:55.81#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.02:37:55.93#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.02:37:55.93#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.02:37:55.93#ibcon#enter wrdev, iclass 18, count 0 2006.173.02:37:55.93#ibcon#first serial, iclass 18, count 0 2006.173.02:37:55.93#ibcon#enter sib2, iclass 18, count 0 2006.173.02:37:55.93#ibcon#flushed, iclass 18, count 0 2006.173.02:37:55.93#ibcon#about to write, iclass 18, count 0 2006.173.02:37:55.93#ibcon#wrote, iclass 18, count 0 2006.173.02:37:55.93#ibcon#about to read 3, iclass 18, count 0 2006.173.02:37:55.95#ibcon#read 3, iclass 18, count 0 2006.173.02:37:55.95#ibcon#about to read 4, iclass 18, count 0 2006.173.02:37:55.95#ibcon#read 4, iclass 18, count 0 2006.173.02:37:55.95#ibcon#about to read 5, iclass 18, count 0 2006.173.02:37:55.95#ibcon#read 5, iclass 18, count 0 2006.173.02:37:55.95#ibcon#about to read 6, iclass 18, count 0 2006.173.02:37:55.95#ibcon#read 6, iclass 18, count 0 2006.173.02:37:55.95#ibcon#end of sib2, iclass 18, count 0 2006.173.02:37:55.95#ibcon#*mode == 0, iclass 18, count 0 2006.173.02:37:55.95#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.02:37:55.95#ibcon#[25=USB\r\n] 2006.173.02:37:55.95#ibcon#*before write, iclass 18, count 0 2006.173.02:37:55.95#ibcon#enter sib2, iclass 18, count 0 2006.173.02:37:55.95#ibcon#flushed, iclass 18, count 0 2006.173.02:37:55.95#ibcon#about to write, iclass 18, count 0 2006.173.02:37:55.95#ibcon#wrote, iclass 18, count 0 2006.173.02:37:55.95#ibcon#about to read 3, iclass 18, count 0 2006.173.02:37:55.98#ibcon#read 3, iclass 18, count 0 2006.173.02:37:55.98#ibcon#about to read 4, iclass 18, count 0 2006.173.02:37:55.98#ibcon#read 4, iclass 18, count 0 2006.173.02:37:55.98#ibcon#about to read 5, iclass 18, count 0 2006.173.02:37:55.98#ibcon#read 5, iclass 18, count 0 2006.173.02:37:55.98#ibcon#about to read 6, iclass 18, count 0 2006.173.02:37:55.98#ibcon#read 6, iclass 18, count 0 2006.173.02:37:55.98#ibcon#end of sib2, iclass 18, count 0 2006.173.02:37:55.98#ibcon#*after write, iclass 18, count 0 2006.173.02:37:55.98#ibcon#*before return 0, iclass 18, count 0 2006.173.02:37:55.98#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.02:37:55.98#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.02:37:55.98#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.02:37:55.98#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.02:37:55.98$vck44/valo=3,564.99 2006.173.02:37:55.98#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.02:37:55.98#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.02:37:55.98#ibcon#ireg 17 cls_cnt 0 2006.173.02:37:55.98#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.02:37:55.98#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.02:37:55.98#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.02:37:55.98#ibcon#enter wrdev, iclass 20, count 0 2006.173.02:37:55.98#ibcon#first serial, iclass 20, count 0 2006.173.02:37:55.98#ibcon#enter sib2, iclass 20, count 0 2006.173.02:37:55.98#ibcon#flushed, iclass 20, count 0 2006.173.02:37:55.98#ibcon#about to write, iclass 20, count 0 2006.173.02:37:55.98#ibcon#wrote, iclass 20, count 0 2006.173.02:37:55.98#ibcon#about to read 3, iclass 20, count 0 2006.173.02:37:56.00#ibcon#read 3, iclass 20, count 0 2006.173.02:37:56.00#ibcon#about to read 4, iclass 20, count 0 2006.173.02:37:56.00#ibcon#read 4, iclass 20, count 0 2006.173.02:37:56.00#ibcon#about to read 5, iclass 20, count 0 2006.173.02:37:56.00#ibcon#read 5, iclass 20, count 0 2006.173.02:37:56.00#ibcon#about to read 6, iclass 20, count 0 2006.173.02:37:56.00#ibcon#read 6, iclass 20, count 0 2006.173.02:37:56.00#ibcon#end of sib2, iclass 20, count 0 2006.173.02:37:56.00#ibcon#*mode == 0, iclass 20, count 0 2006.173.02:37:56.00#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.02:37:56.00#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.02:37:56.00#ibcon#*before write, iclass 20, count 0 2006.173.02:37:56.00#ibcon#enter sib2, iclass 20, count 0 2006.173.02:37:56.00#ibcon#flushed, iclass 20, count 0 2006.173.02:37:56.00#ibcon#about to write, iclass 20, count 0 2006.173.02:37:56.00#ibcon#wrote, iclass 20, count 0 2006.173.02:37:56.00#ibcon#about to read 3, iclass 20, count 0 2006.173.02:37:56.04#ibcon#read 3, iclass 20, count 0 2006.173.02:37:56.04#ibcon#about to read 4, iclass 20, count 0 2006.173.02:37:56.04#ibcon#read 4, iclass 20, count 0 2006.173.02:37:56.04#ibcon#about to read 5, iclass 20, count 0 2006.173.02:37:56.04#ibcon#read 5, iclass 20, count 0 2006.173.02:37:56.04#ibcon#about to read 6, iclass 20, count 0 2006.173.02:37:56.04#ibcon#read 6, iclass 20, count 0 2006.173.02:37:56.04#ibcon#end of sib2, iclass 20, count 0 2006.173.02:37:56.04#ibcon#*after write, iclass 20, count 0 2006.173.02:37:56.04#ibcon#*before return 0, iclass 20, count 0 2006.173.02:37:56.04#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.02:37:56.04#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.02:37:56.04#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.02:37:56.04#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.02:37:56.04$vck44/va=3,5 2006.173.02:37:56.04#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.02:37:56.04#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.02:37:56.04#ibcon#ireg 11 cls_cnt 2 2006.173.02:37:56.04#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.02:37:56.10#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.02:37:56.10#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.02:37:56.10#ibcon#enter wrdev, iclass 22, count 2 2006.173.02:37:56.10#ibcon#first serial, iclass 22, count 2 2006.173.02:37:56.10#ibcon#enter sib2, iclass 22, count 2 2006.173.02:37:56.10#ibcon#flushed, iclass 22, count 2 2006.173.02:37:56.10#ibcon#about to write, iclass 22, count 2 2006.173.02:37:56.10#ibcon#wrote, iclass 22, count 2 2006.173.02:37:56.10#ibcon#about to read 3, iclass 22, count 2 2006.173.02:37:56.12#ibcon#read 3, iclass 22, count 2 2006.173.02:37:56.12#ibcon#about to read 4, iclass 22, count 2 2006.173.02:37:56.12#ibcon#read 4, iclass 22, count 2 2006.173.02:37:56.12#ibcon#about to read 5, iclass 22, count 2 2006.173.02:37:56.12#ibcon#read 5, iclass 22, count 2 2006.173.02:37:56.12#ibcon#about to read 6, iclass 22, count 2 2006.173.02:37:56.12#ibcon#read 6, iclass 22, count 2 2006.173.02:37:56.12#ibcon#end of sib2, iclass 22, count 2 2006.173.02:37:56.12#ibcon#*mode == 0, iclass 22, count 2 2006.173.02:37:56.12#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.02:37:56.12#ibcon#[25=AT03-05\r\n] 2006.173.02:37:56.12#ibcon#*before write, iclass 22, count 2 2006.173.02:37:56.12#ibcon#enter sib2, iclass 22, count 2 2006.173.02:37:56.12#ibcon#flushed, iclass 22, count 2 2006.173.02:37:56.12#ibcon#about to write, iclass 22, count 2 2006.173.02:37:56.12#ibcon#wrote, iclass 22, count 2 2006.173.02:37:56.12#ibcon#about to read 3, iclass 22, count 2 2006.173.02:37:56.15#ibcon#read 3, iclass 22, count 2 2006.173.02:37:56.15#ibcon#about to read 4, iclass 22, count 2 2006.173.02:37:56.15#ibcon#read 4, iclass 22, count 2 2006.173.02:37:56.15#ibcon#about to read 5, iclass 22, count 2 2006.173.02:37:56.15#ibcon#read 5, iclass 22, count 2 2006.173.02:37:56.15#ibcon#about to read 6, iclass 22, count 2 2006.173.02:37:56.15#ibcon#read 6, iclass 22, count 2 2006.173.02:37:56.15#ibcon#end of sib2, iclass 22, count 2 2006.173.02:37:56.15#ibcon#*after write, iclass 22, count 2 2006.173.02:37:56.15#ibcon#*before return 0, iclass 22, count 2 2006.173.02:37:56.15#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.02:37:56.15#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.02:37:56.15#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.02:37:56.15#ibcon#ireg 7 cls_cnt 0 2006.173.02:37:56.15#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.02:37:56.27#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.02:37:56.27#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.02:37:56.27#ibcon#enter wrdev, iclass 22, count 0 2006.173.02:37:56.27#ibcon#first serial, iclass 22, count 0 2006.173.02:37:56.27#ibcon#enter sib2, iclass 22, count 0 2006.173.02:37:56.27#ibcon#flushed, iclass 22, count 0 2006.173.02:37:56.27#ibcon#about to write, iclass 22, count 0 2006.173.02:37:56.27#ibcon#wrote, iclass 22, count 0 2006.173.02:37:56.27#ibcon#about to read 3, iclass 22, count 0 2006.173.02:37:56.29#ibcon#read 3, iclass 22, count 0 2006.173.02:37:56.29#ibcon#about to read 4, iclass 22, count 0 2006.173.02:37:56.29#ibcon#read 4, iclass 22, count 0 2006.173.02:37:56.29#ibcon#about to read 5, iclass 22, count 0 2006.173.02:37:56.29#ibcon#read 5, iclass 22, count 0 2006.173.02:37:56.29#ibcon#about to read 6, iclass 22, count 0 2006.173.02:37:56.29#ibcon#read 6, iclass 22, count 0 2006.173.02:37:56.29#ibcon#end of sib2, iclass 22, count 0 2006.173.02:37:56.29#ibcon#*mode == 0, iclass 22, count 0 2006.173.02:37:56.29#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.02:37:56.29#ibcon#[25=USB\r\n] 2006.173.02:37:56.29#ibcon#*before write, iclass 22, count 0 2006.173.02:37:56.29#ibcon#enter sib2, iclass 22, count 0 2006.173.02:37:56.29#ibcon#flushed, iclass 22, count 0 2006.173.02:37:56.29#ibcon#about to write, iclass 22, count 0 2006.173.02:37:56.29#ibcon#wrote, iclass 22, count 0 2006.173.02:37:56.29#ibcon#about to read 3, iclass 22, count 0 2006.173.02:37:56.32#ibcon#read 3, iclass 22, count 0 2006.173.02:37:56.32#ibcon#about to read 4, iclass 22, count 0 2006.173.02:37:56.32#ibcon#read 4, iclass 22, count 0 2006.173.02:37:56.32#ibcon#about to read 5, iclass 22, count 0 2006.173.02:37:56.32#ibcon#read 5, iclass 22, count 0 2006.173.02:37:56.32#ibcon#about to read 6, iclass 22, count 0 2006.173.02:37:56.32#ibcon#read 6, iclass 22, count 0 2006.173.02:37:56.32#ibcon#end of sib2, iclass 22, count 0 2006.173.02:37:56.32#ibcon#*after write, iclass 22, count 0 2006.173.02:37:56.32#ibcon#*before return 0, iclass 22, count 0 2006.173.02:37:56.32#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.02:37:56.32#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.02:37:56.32#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.02:37:56.32#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.02:37:56.32$vck44/valo=4,624.99 2006.173.02:37:56.32#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.02:37:56.32#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.02:37:56.32#ibcon#ireg 17 cls_cnt 0 2006.173.02:37:56.32#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.02:37:56.32#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.02:37:56.32#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.02:37:56.32#ibcon#enter wrdev, iclass 24, count 0 2006.173.02:37:56.32#ibcon#first serial, iclass 24, count 0 2006.173.02:37:56.32#ibcon#enter sib2, iclass 24, count 0 2006.173.02:37:56.32#ibcon#flushed, iclass 24, count 0 2006.173.02:37:56.32#ibcon#about to write, iclass 24, count 0 2006.173.02:37:56.32#ibcon#wrote, iclass 24, count 0 2006.173.02:37:56.32#ibcon#about to read 3, iclass 24, count 0 2006.173.02:37:56.34#ibcon#read 3, iclass 24, count 0 2006.173.02:37:56.34#ibcon#about to read 4, iclass 24, count 0 2006.173.02:37:56.34#ibcon#read 4, iclass 24, count 0 2006.173.02:37:56.34#ibcon#about to read 5, iclass 24, count 0 2006.173.02:37:56.34#ibcon#read 5, iclass 24, count 0 2006.173.02:37:56.34#ibcon#about to read 6, iclass 24, count 0 2006.173.02:37:56.34#ibcon#read 6, iclass 24, count 0 2006.173.02:37:56.34#ibcon#end of sib2, iclass 24, count 0 2006.173.02:37:56.34#ibcon#*mode == 0, iclass 24, count 0 2006.173.02:37:56.34#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.02:37:56.34#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.02:37:56.34#ibcon#*before write, iclass 24, count 0 2006.173.02:37:56.34#ibcon#enter sib2, iclass 24, count 0 2006.173.02:37:56.34#ibcon#flushed, iclass 24, count 0 2006.173.02:37:56.34#ibcon#about to write, iclass 24, count 0 2006.173.02:37:56.34#ibcon#wrote, iclass 24, count 0 2006.173.02:37:56.34#ibcon#about to read 3, iclass 24, count 0 2006.173.02:37:56.38#ibcon#read 3, iclass 24, count 0 2006.173.02:37:56.38#ibcon#about to read 4, iclass 24, count 0 2006.173.02:37:56.38#ibcon#read 4, iclass 24, count 0 2006.173.02:37:56.38#ibcon#about to read 5, iclass 24, count 0 2006.173.02:37:56.38#ibcon#read 5, iclass 24, count 0 2006.173.02:37:56.38#ibcon#about to read 6, iclass 24, count 0 2006.173.02:37:56.38#ibcon#read 6, iclass 24, count 0 2006.173.02:37:56.38#ibcon#end of sib2, iclass 24, count 0 2006.173.02:37:56.38#ibcon#*after write, iclass 24, count 0 2006.173.02:37:56.38#ibcon#*before return 0, iclass 24, count 0 2006.173.02:37:56.38#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.02:37:56.38#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.02:37:56.38#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.02:37:56.38#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.02:37:56.38$vck44/va=4,6 2006.173.02:37:56.38#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.02:37:56.38#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.02:37:56.38#ibcon#ireg 11 cls_cnt 2 2006.173.02:37:56.38#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.02:37:56.44#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.02:37:56.44#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.02:37:56.44#ibcon#enter wrdev, iclass 26, count 2 2006.173.02:37:56.44#ibcon#first serial, iclass 26, count 2 2006.173.02:37:56.44#ibcon#enter sib2, iclass 26, count 2 2006.173.02:37:56.44#ibcon#flushed, iclass 26, count 2 2006.173.02:37:56.44#ibcon#about to write, iclass 26, count 2 2006.173.02:37:56.44#ibcon#wrote, iclass 26, count 2 2006.173.02:37:56.44#ibcon#about to read 3, iclass 26, count 2 2006.173.02:37:56.46#ibcon#read 3, iclass 26, count 2 2006.173.02:37:56.46#ibcon#about to read 4, iclass 26, count 2 2006.173.02:37:56.46#ibcon#read 4, iclass 26, count 2 2006.173.02:37:56.46#ibcon#about to read 5, iclass 26, count 2 2006.173.02:37:56.46#ibcon#read 5, iclass 26, count 2 2006.173.02:37:56.46#ibcon#about to read 6, iclass 26, count 2 2006.173.02:37:56.46#ibcon#read 6, iclass 26, count 2 2006.173.02:37:56.46#ibcon#end of sib2, iclass 26, count 2 2006.173.02:37:56.46#ibcon#*mode == 0, iclass 26, count 2 2006.173.02:37:56.46#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.02:37:56.46#ibcon#[25=AT04-06\r\n] 2006.173.02:37:56.46#ibcon#*before write, iclass 26, count 2 2006.173.02:37:56.46#ibcon#enter sib2, iclass 26, count 2 2006.173.02:37:56.46#ibcon#flushed, iclass 26, count 2 2006.173.02:37:56.46#ibcon#about to write, iclass 26, count 2 2006.173.02:37:56.46#ibcon#wrote, iclass 26, count 2 2006.173.02:37:56.46#ibcon#about to read 3, iclass 26, count 2 2006.173.02:37:56.49#ibcon#read 3, iclass 26, count 2 2006.173.02:37:56.49#ibcon#about to read 4, iclass 26, count 2 2006.173.02:37:56.49#ibcon#read 4, iclass 26, count 2 2006.173.02:37:56.49#ibcon#about to read 5, iclass 26, count 2 2006.173.02:37:56.49#ibcon#read 5, iclass 26, count 2 2006.173.02:37:56.49#ibcon#about to read 6, iclass 26, count 2 2006.173.02:37:56.49#ibcon#read 6, iclass 26, count 2 2006.173.02:37:56.49#ibcon#end of sib2, iclass 26, count 2 2006.173.02:37:56.49#ibcon#*after write, iclass 26, count 2 2006.173.02:37:56.49#ibcon#*before return 0, iclass 26, count 2 2006.173.02:37:56.49#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.02:37:56.49#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.02:37:56.49#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.02:37:56.49#ibcon#ireg 7 cls_cnt 0 2006.173.02:37:56.49#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.02:37:56.61#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.02:37:56.61#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.02:37:56.61#ibcon#enter wrdev, iclass 26, count 0 2006.173.02:37:56.61#ibcon#first serial, iclass 26, count 0 2006.173.02:37:56.61#ibcon#enter sib2, iclass 26, count 0 2006.173.02:37:56.61#ibcon#flushed, iclass 26, count 0 2006.173.02:37:56.61#ibcon#about to write, iclass 26, count 0 2006.173.02:37:56.61#ibcon#wrote, iclass 26, count 0 2006.173.02:37:56.61#ibcon#about to read 3, iclass 26, count 0 2006.173.02:37:56.63#ibcon#read 3, iclass 26, count 0 2006.173.02:37:56.63#ibcon#about to read 4, iclass 26, count 0 2006.173.02:37:56.63#ibcon#read 4, iclass 26, count 0 2006.173.02:37:56.63#ibcon#about to read 5, iclass 26, count 0 2006.173.02:37:56.63#ibcon#read 5, iclass 26, count 0 2006.173.02:37:56.63#ibcon#about to read 6, iclass 26, count 0 2006.173.02:37:56.63#ibcon#read 6, iclass 26, count 0 2006.173.02:37:56.63#ibcon#end of sib2, iclass 26, count 0 2006.173.02:37:56.63#ibcon#*mode == 0, iclass 26, count 0 2006.173.02:37:56.63#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.02:37:56.63#ibcon#[25=USB\r\n] 2006.173.02:37:56.63#ibcon#*before write, iclass 26, count 0 2006.173.02:37:56.63#ibcon#enter sib2, iclass 26, count 0 2006.173.02:37:56.63#ibcon#flushed, iclass 26, count 0 2006.173.02:37:56.63#ibcon#about to write, iclass 26, count 0 2006.173.02:37:56.63#ibcon#wrote, iclass 26, count 0 2006.173.02:37:56.63#ibcon#about to read 3, iclass 26, count 0 2006.173.02:37:56.66#ibcon#read 3, iclass 26, count 0 2006.173.02:37:56.66#ibcon#about to read 4, iclass 26, count 0 2006.173.02:37:56.66#ibcon#read 4, iclass 26, count 0 2006.173.02:37:56.66#ibcon#about to read 5, iclass 26, count 0 2006.173.02:37:56.66#ibcon#read 5, iclass 26, count 0 2006.173.02:37:56.66#ibcon#about to read 6, iclass 26, count 0 2006.173.02:37:56.66#ibcon#read 6, iclass 26, count 0 2006.173.02:37:56.66#ibcon#end of sib2, iclass 26, count 0 2006.173.02:37:56.66#ibcon#*after write, iclass 26, count 0 2006.173.02:37:56.66#ibcon#*before return 0, iclass 26, count 0 2006.173.02:37:56.66#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.02:37:56.66#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.02:37:56.66#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.02:37:56.66#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.02:37:56.66$vck44/valo=5,734.99 2006.173.02:37:56.66#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.02:37:56.66#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.02:37:56.66#ibcon#ireg 17 cls_cnt 0 2006.173.02:37:56.66#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.02:37:56.66#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.02:37:56.66#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.02:37:56.66#ibcon#enter wrdev, iclass 28, count 0 2006.173.02:37:56.66#ibcon#first serial, iclass 28, count 0 2006.173.02:37:56.66#ibcon#enter sib2, iclass 28, count 0 2006.173.02:37:56.66#ibcon#flushed, iclass 28, count 0 2006.173.02:37:56.66#ibcon#about to write, iclass 28, count 0 2006.173.02:37:56.66#ibcon#wrote, iclass 28, count 0 2006.173.02:37:56.66#ibcon#about to read 3, iclass 28, count 0 2006.173.02:37:56.68#ibcon#read 3, iclass 28, count 0 2006.173.02:37:56.68#ibcon#about to read 4, iclass 28, count 0 2006.173.02:37:56.68#ibcon#read 4, iclass 28, count 0 2006.173.02:37:56.68#ibcon#about to read 5, iclass 28, count 0 2006.173.02:37:56.68#ibcon#read 5, iclass 28, count 0 2006.173.02:37:56.68#ibcon#about to read 6, iclass 28, count 0 2006.173.02:37:56.68#ibcon#read 6, iclass 28, count 0 2006.173.02:37:56.68#ibcon#end of sib2, iclass 28, count 0 2006.173.02:37:56.68#ibcon#*mode == 0, iclass 28, count 0 2006.173.02:37:56.68#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.02:37:56.68#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.02:37:56.68#ibcon#*before write, iclass 28, count 0 2006.173.02:37:56.68#ibcon#enter sib2, iclass 28, count 0 2006.173.02:37:56.68#ibcon#flushed, iclass 28, count 0 2006.173.02:37:56.68#ibcon#about to write, iclass 28, count 0 2006.173.02:37:56.68#ibcon#wrote, iclass 28, count 0 2006.173.02:37:56.68#ibcon#about to read 3, iclass 28, count 0 2006.173.02:37:56.72#ibcon#read 3, iclass 28, count 0 2006.173.02:37:56.72#ibcon#about to read 4, iclass 28, count 0 2006.173.02:37:56.72#ibcon#read 4, iclass 28, count 0 2006.173.02:37:56.72#ibcon#about to read 5, iclass 28, count 0 2006.173.02:37:56.72#ibcon#read 5, iclass 28, count 0 2006.173.02:37:56.72#ibcon#about to read 6, iclass 28, count 0 2006.173.02:37:56.72#ibcon#read 6, iclass 28, count 0 2006.173.02:37:56.72#ibcon#end of sib2, iclass 28, count 0 2006.173.02:37:56.72#ibcon#*after write, iclass 28, count 0 2006.173.02:37:56.72#ibcon#*before return 0, iclass 28, count 0 2006.173.02:37:56.72#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.02:37:56.72#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.02:37:56.72#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.02:37:56.72#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.02:37:56.72$vck44/va=5,4 2006.173.02:37:56.72#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.02:37:56.72#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.02:37:56.72#ibcon#ireg 11 cls_cnt 2 2006.173.02:37:56.72#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.02:37:56.78#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.02:37:56.78#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.02:37:56.78#ibcon#enter wrdev, iclass 30, count 2 2006.173.02:37:56.78#ibcon#first serial, iclass 30, count 2 2006.173.02:37:56.78#ibcon#enter sib2, iclass 30, count 2 2006.173.02:37:56.78#ibcon#flushed, iclass 30, count 2 2006.173.02:37:56.78#ibcon#about to write, iclass 30, count 2 2006.173.02:37:56.78#ibcon#wrote, iclass 30, count 2 2006.173.02:37:56.78#ibcon#about to read 3, iclass 30, count 2 2006.173.02:37:56.80#ibcon#read 3, iclass 30, count 2 2006.173.02:37:56.80#ibcon#about to read 4, iclass 30, count 2 2006.173.02:37:56.80#ibcon#read 4, iclass 30, count 2 2006.173.02:37:56.80#ibcon#about to read 5, iclass 30, count 2 2006.173.02:37:56.80#ibcon#read 5, iclass 30, count 2 2006.173.02:37:56.80#ibcon#about to read 6, iclass 30, count 2 2006.173.02:37:56.80#ibcon#read 6, iclass 30, count 2 2006.173.02:37:56.80#ibcon#end of sib2, iclass 30, count 2 2006.173.02:37:56.80#ibcon#*mode == 0, iclass 30, count 2 2006.173.02:37:56.80#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.02:37:56.80#ibcon#[25=AT05-04\r\n] 2006.173.02:37:56.80#ibcon#*before write, iclass 30, count 2 2006.173.02:37:56.80#ibcon#enter sib2, iclass 30, count 2 2006.173.02:37:56.80#ibcon#flushed, iclass 30, count 2 2006.173.02:37:56.80#ibcon#about to write, iclass 30, count 2 2006.173.02:37:56.80#ibcon#wrote, iclass 30, count 2 2006.173.02:37:56.80#ibcon#about to read 3, iclass 30, count 2 2006.173.02:37:56.84#ibcon#read 3, iclass 30, count 2 2006.173.02:37:56.84#ibcon#about to read 4, iclass 30, count 2 2006.173.02:37:56.84#ibcon#read 4, iclass 30, count 2 2006.173.02:37:56.84#ibcon#about to read 5, iclass 30, count 2 2006.173.02:37:56.84#ibcon#read 5, iclass 30, count 2 2006.173.02:37:56.84#ibcon#about to read 6, iclass 30, count 2 2006.173.02:37:56.84#ibcon#read 6, iclass 30, count 2 2006.173.02:37:56.84#ibcon#end of sib2, iclass 30, count 2 2006.173.02:37:56.84#ibcon#*after write, iclass 30, count 2 2006.173.02:37:56.84#ibcon#*before return 0, iclass 30, count 2 2006.173.02:37:56.84#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.02:37:56.84#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.02:37:56.84#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.02:37:56.84#ibcon#ireg 7 cls_cnt 0 2006.173.02:37:56.84#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.02:37:56.96#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.02:37:56.96#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.02:37:56.96#ibcon#enter wrdev, iclass 30, count 0 2006.173.02:37:56.96#ibcon#first serial, iclass 30, count 0 2006.173.02:37:56.96#ibcon#enter sib2, iclass 30, count 0 2006.173.02:37:56.96#ibcon#flushed, iclass 30, count 0 2006.173.02:37:56.96#ibcon#about to write, iclass 30, count 0 2006.173.02:37:56.96#ibcon#wrote, iclass 30, count 0 2006.173.02:37:56.96#ibcon#about to read 3, iclass 30, count 0 2006.173.02:37:56.98#ibcon#read 3, iclass 30, count 0 2006.173.02:37:56.98#ibcon#about to read 4, iclass 30, count 0 2006.173.02:37:56.98#ibcon#read 4, iclass 30, count 0 2006.173.02:37:56.98#ibcon#about to read 5, iclass 30, count 0 2006.173.02:37:56.98#ibcon#read 5, iclass 30, count 0 2006.173.02:37:56.98#ibcon#about to read 6, iclass 30, count 0 2006.173.02:37:56.98#ibcon#read 6, iclass 30, count 0 2006.173.02:37:56.98#ibcon#end of sib2, iclass 30, count 0 2006.173.02:37:56.98#ibcon#*mode == 0, iclass 30, count 0 2006.173.02:37:56.98#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.02:37:56.98#ibcon#[25=USB\r\n] 2006.173.02:37:56.98#ibcon#*before write, iclass 30, count 0 2006.173.02:37:56.98#ibcon#enter sib2, iclass 30, count 0 2006.173.02:37:56.98#ibcon#flushed, iclass 30, count 0 2006.173.02:37:56.98#ibcon#about to write, iclass 30, count 0 2006.173.02:37:56.98#ibcon#wrote, iclass 30, count 0 2006.173.02:37:56.98#ibcon#about to read 3, iclass 30, count 0 2006.173.02:37:57.01#ibcon#read 3, iclass 30, count 0 2006.173.02:37:57.01#ibcon#about to read 4, iclass 30, count 0 2006.173.02:37:57.01#ibcon#read 4, iclass 30, count 0 2006.173.02:37:57.01#ibcon#about to read 5, iclass 30, count 0 2006.173.02:37:57.01#ibcon#read 5, iclass 30, count 0 2006.173.02:37:57.01#ibcon#about to read 6, iclass 30, count 0 2006.173.02:37:57.01#ibcon#read 6, iclass 30, count 0 2006.173.02:37:57.01#ibcon#end of sib2, iclass 30, count 0 2006.173.02:37:57.01#ibcon#*after write, iclass 30, count 0 2006.173.02:37:57.01#ibcon#*before return 0, iclass 30, count 0 2006.173.02:37:57.01#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.02:37:57.01#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.02:37:57.01#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.02:37:57.01#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.02:37:57.01$vck44/valo=6,814.99 2006.173.02:37:57.01#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.02:37:57.01#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.02:37:57.01#ibcon#ireg 17 cls_cnt 0 2006.173.02:37:57.01#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.02:37:57.01#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.02:37:57.01#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.02:37:57.01#ibcon#enter wrdev, iclass 32, count 0 2006.173.02:37:57.01#ibcon#first serial, iclass 32, count 0 2006.173.02:37:57.01#ibcon#enter sib2, iclass 32, count 0 2006.173.02:37:57.01#ibcon#flushed, iclass 32, count 0 2006.173.02:37:57.01#ibcon#about to write, iclass 32, count 0 2006.173.02:37:57.01#ibcon#wrote, iclass 32, count 0 2006.173.02:37:57.01#ibcon#about to read 3, iclass 32, count 0 2006.173.02:37:57.03#ibcon#read 3, iclass 32, count 0 2006.173.02:37:57.03#ibcon#about to read 4, iclass 32, count 0 2006.173.02:37:57.03#ibcon#read 4, iclass 32, count 0 2006.173.02:37:57.03#ibcon#about to read 5, iclass 32, count 0 2006.173.02:37:57.03#ibcon#read 5, iclass 32, count 0 2006.173.02:37:57.03#ibcon#about to read 6, iclass 32, count 0 2006.173.02:37:57.03#ibcon#read 6, iclass 32, count 0 2006.173.02:37:57.03#ibcon#end of sib2, iclass 32, count 0 2006.173.02:37:57.03#ibcon#*mode == 0, iclass 32, count 0 2006.173.02:37:57.03#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.02:37:57.03#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.02:37:57.03#ibcon#*before write, iclass 32, count 0 2006.173.02:37:57.03#ibcon#enter sib2, iclass 32, count 0 2006.173.02:37:57.03#ibcon#flushed, iclass 32, count 0 2006.173.02:37:57.03#ibcon#about to write, iclass 32, count 0 2006.173.02:37:57.03#ibcon#wrote, iclass 32, count 0 2006.173.02:37:57.03#ibcon#about to read 3, iclass 32, count 0 2006.173.02:37:57.07#ibcon#read 3, iclass 32, count 0 2006.173.02:37:57.07#ibcon#about to read 4, iclass 32, count 0 2006.173.02:37:57.07#ibcon#read 4, iclass 32, count 0 2006.173.02:37:57.07#ibcon#about to read 5, iclass 32, count 0 2006.173.02:37:57.07#ibcon#read 5, iclass 32, count 0 2006.173.02:37:57.07#ibcon#about to read 6, iclass 32, count 0 2006.173.02:37:57.07#ibcon#read 6, iclass 32, count 0 2006.173.02:37:57.07#ibcon#end of sib2, iclass 32, count 0 2006.173.02:37:57.07#ibcon#*after write, iclass 32, count 0 2006.173.02:37:57.07#ibcon#*before return 0, iclass 32, count 0 2006.173.02:37:57.07#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.02:37:57.07#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.02:37:57.07#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.02:37:57.07#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.02:37:57.07$vck44/va=6,3 2006.173.02:37:57.07#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.02:37:57.07#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.02:37:57.07#ibcon#ireg 11 cls_cnt 2 2006.173.02:37:57.07#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.02:37:57.13#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.02:37:57.13#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.02:37:57.13#ibcon#enter wrdev, iclass 34, count 2 2006.173.02:37:57.13#ibcon#first serial, iclass 34, count 2 2006.173.02:37:57.13#ibcon#enter sib2, iclass 34, count 2 2006.173.02:37:57.13#ibcon#flushed, iclass 34, count 2 2006.173.02:37:57.13#ibcon#about to write, iclass 34, count 2 2006.173.02:37:57.13#ibcon#wrote, iclass 34, count 2 2006.173.02:37:57.13#ibcon#about to read 3, iclass 34, count 2 2006.173.02:37:57.15#ibcon#read 3, iclass 34, count 2 2006.173.02:37:57.15#ibcon#about to read 4, iclass 34, count 2 2006.173.02:37:57.15#ibcon#read 4, iclass 34, count 2 2006.173.02:37:57.15#ibcon#about to read 5, iclass 34, count 2 2006.173.02:37:57.15#ibcon#read 5, iclass 34, count 2 2006.173.02:37:57.15#ibcon#about to read 6, iclass 34, count 2 2006.173.02:37:57.15#ibcon#read 6, iclass 34, count 2 2006.173.02:37:57.15#ibcon#end of sib2, iclass 34, count 2 2006.173.02:37:57.15#ibcon#*mode == 0, iclass 34, count 2 2006.173.02:37:57.15#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.02:37:57.15#ibcon#[25=AT06-03\r\n] 2006.173.02:37:57.15#ibcon#*before write, iclass 34, count 2 2006.173.02:37:57.15#ibcon#enter sib2, iclass 34, count 2 2006.173.02:37:57.15#ibcon#flushed, iclass 34, count 2 2006.173.02:37:57.15#ibcon#about to write, iclass 34, count 2 2006.173.02:37:57.15#ibcon#wrote, iclass 34, count 2 2006.173.02:37:57.15#ibcon#about to read 3, iclass 34, count 2 2006.173.02:37:57.18#ibcon#read 3, iclass 34, count 2 2006.173.02:37:57.18#ibcon#about to read 4, iclass 34, count 2 2006.173.02:37:57.18#ibcon#read 4, iclass 34, count 2 2006.173.02:37:57.18#ibcon#about to read 5, iclass 34, count 2 2006.173.02:37:57.18#ibcon#read 5, iclass 34, count 2 2006.173.02:37:57.18#ibcon#about to read 6, iclass 34, count 2 2006.173.02:37:57.18#ibcon#read 6, iclass 34, count 2 2006.173.02:37:57.18#ibcon#end of sib2, iclass 34, count 2 2006.173.02:37:57.18#ibcon#*after write, iclass 34, count 2 2006.173.02:37:57.18#ibcon#*before return 0, iclass 34, count 2 2006.173.02:37:57.18#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.02:37:57.18#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.02:37:57.18#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.02:37:57.18#ibcon#ireg 7 cls_cnt 0 2006.173.02:37:57.18#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.02:37:57.30#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.02:37:57.30#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.02:37:57.30#ibcon#enter wrdev, iclass 34, count 0 2006.173.02:37:57.30#ibcon#first serial, iclass 34, count 0 2006.173.02:37:57.30#ibcon#enter sib2, iclass 34, count 0 2006.173.02:37:57.30#ibcon#flushed, iclass 34, count 0 2006.173.02:37:57.30#ibcon#about to write, iclass 34, count 0 2006.173.02:37:57.30#ibcon#wrote, iclass 34, count 0 2006.173.02:37:57.30#ibcon#about to read 3, iclass 34, count 0 2006.173.02:37:57.32#ibcon#read 3, iclass 34, count 0 2006.173.02:37:57.32#ibcon#about to read 4, iclass 34, count 0 2006.173.02:37:57.32#ibcon#read 4, iclass 34, count 0 2006.173.02:37:57.32#ibcon#about to read 5, iclass 34, count 0 2006.173.02:37:57.32#ibcon#read 5, iclass 34, count 0 2006.173.02:37:57.32#ibcon#about to read 6, iclass 34, count 0 2006.173.02:37:57.32#ibcon#read 6, iclass 34, count 0 2006.173.02:37:57.32#ibcon#end of sib2, iclass 34, count 0 2006.173.02:37:57.32#ibcon#*mode == 0, iclass 34, count 0 2006.173.02:37:57.32#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.02:37:57.32#ibcon#[25=USB\r\n] 2006.173.02:37:57.32#ibcon#*before write, iclass 34, count 0 2006.173.02:37:57.32#ibcon#enter sib2, iclass 34, count 0 2006.173.02:37:57.32#ibcon#flushed, iclass 34, count 0 2006.173.02:37:57.32#ibcon#about to write, iclass 34, count 0 2006.173.02:37:57.32#ibcon#wrote, iclass 34, count 0 2006.173.02:37:57.32#ibcon#about to read 3, iclass 34, count 0 2006.173.02:37:57.35#ibcon#read 3, iclass 34, count 0 2006.173.02:37:57.35#ibcon#about to read 4, iclass 34, count 0 2006.173.02:37:57.35#ibcon#read 4, iclass 34, count 0 2006.173.02:37:57.35#ibcon#about to read 5, iclass 34, count 0 2006.173.02:37:57.35#ibcon#read 5, iclass 34, count 0 2006.173.02:37:57.35#ibcon#about to read 6, iclass 34, count 0 2006.173.02:37:57.35#ibcon#read 6, iclass 34, count 0 2006.173.02:37:57.35#ibcon#end of sib2, iclass 34, count 0 2006.173.02:37:57.35#ibcon#*after write, iclass 34, count 0 2006.173.02:37:57.35#ibcon#*before return 0, iclass 34, count 0 2006.173.02:37:57.35#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.02:37:57.35#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.02:37:57.35#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.02:37:57.35#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.02:37:57.35$vck44/valo=7,864.99 2006.173.02:37:57.35#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.02:37:57.35#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.02:37:57.35#ibcon#ireg 17 cls_cnt 0 2006.173.02:37:57.35#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.02:37:57.35#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.02:37:57.35#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.02:37:57.35#ibcon#enter wrdev, iclass 36, count 0 2006.173.02:37:57.35#ibcon#first serial, iclass 36, count 0 2006.173.02:37:57.35#ibcon#enter sib2, iclass 36, count 0 2006.173.02:37:57.35#ibcon#flushed, iclass 36, count 0 2006.173.02:37:57.35#ibcon#about to write, iclass 36, count 0 2006.173.02:37:57.35#ibcon#wrote, iclass 36, count 0 2006.173.02:37:57.35#ibcon#about to read 3, iclass 36, count 0 2006.173.02:37:57.37#ibcon#read 3, iclass 36, count 0 2006.173.02:37:57.37#ibcon#about to read 4, iclass 36, count 0 2006.173.02:37:57.37#ibcon#read 4, iclass 36, count 0 2006.173.02:37:57.37#ibcon#about to read 5, iclass 36, count 0 2006.173.02:37:57.37#ibcon#read 5, iclass 36, count 0 2006.173.02:37:57.37#ibcon#about to read 6, iclass 36, count 0 2006.173.02:37:57.37#ibcon#read 6, iclass 36, count 0 2006.173.02:37:57.37#ibcon#end of sib2, iclass 36, count 0 2006.173.02:37:57.37#ibcon#*mode == 0, iclass 36, count 0 2006.173.02:37:57.37#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.02:37:57.37#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.02:37:57.37#ibcon#*before write, iclass 36, count 0 2006.173.02:37:57.37#ibcon#enter sib2, iclass 36, count 0 2006.173.02:37:57.37#ibcon#flushed, iclass 36, count 0 2006.173.02:37:57.37#ibcon#about to write, iclass 36, count 0 2006.173.02:37:57.37#ibcon#wrote, iclass 36, count 0 2006.173.02:37:57.37#ibcon#about to read 3, iclass 36, count 0 2006.173.02:37:57.41#ibcon#read 3, iclass 36, count 0 2006.173.02:37:57.41#ibcon#about to read 4, iclass 36, count 0 2006.173.02:37:57.41#ibcon#read 4, iclass 36, count 0 2006.173.02:37:57.41#ibcon#about to read 5, iclass 36, count 0 2006.173.02:37:57.41#ibcon#read 5, iclass 36, count 0 2006.173.02:37:57.41#ibcon#about to read 6, iclass 36, count 0 2006.173.02:37:57.41#ibcon#read 6, iclass 36, count 0 2006.173.02:37:57.41#ibcon#end of sib2, iclass 36, count 0 2006.173.02:37:57.41#ibcon#*after write, iclass 36, count 0 2006.173.02:37:57.41#ibcon#*before return 0, iclass 36, count 0 2006.173.02:37:57.41#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.02:37:57.41#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.02:37:57.41#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.02:37:57.41#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.02:37:57.41$vck44/va=7,4 2006.173.02:37:57.41#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.02:37:57.41#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.02:37:57.41#ibcon#ireg 11 cls_cnt 2 2006.173.02:37:57.41#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.02:37:57.47#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.02:37:57.47#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.02:37:57.47#ibcon#enter wrdev, iclass 38, count 2 2006.173.02:37:57.47#ibcon#first serial, iclass 38, count 2 2006.173.02:37:57.47#ibcon#enter sib2, iclass 38, count 2 2006.173.02:37:57.47#ibcon#flushed, iclass 38, count 2 2006.173.02:37:57.47#ibcon#about to write, iclass 38, count 2 2006.173.02:37:57.47#ibcon#wrote, iclass 38, count 2 2006.173.02:37:57.47#ibcon#about to read 3, iclass 38, count 2 2006.173.02:37:57.49#ibcon#read 3, iclass 38, count 2 2006.173.02:37:57.49#ibcon#about to read 4, iclass 38, count 2 2006.173.02:37:57.49#ibcon#read 4, iclass 38, count 2 2006.173.02:37:57.49#ibcon#about to read 5, iclass 38, count 2 2006.173.02:37:57.49#ibcon#read 5, iclass 38, count 2 2006.173.02:37:57.49#ibcon#about to read 6, iclass 38, count 2 2006.173.02:37:57.49#ibcon#read 6, iclass 38, count 2 2006.173.02:37:57.49#ibcon#end of sib2, iclass 38, count 2 2006.173.02:37:57.49#ibcon#*mode == 0, iclass 38, count 2 2006.173.02:37:57.49#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.02:37:57.49#ibcon#[25=AT07-04\r\n] 2006.173.02:37:57.49#ibcon#*before write, iclass 38, count 2 2006.173.02:37:57.49#ibcon#enter sib2, iclass 38, count 2 2006.173.02:37:57.49#ibcon#flushed, iclass 38, count 2 2006.173.02:37:57.49#ibcon#about to write, iclass 38, count 2 2006.173.02:37:57.49#ibcon#wrote, iclass 38, count 2 2006.173.02:37:57.49#ibcon#about to read 3, iclass 38, count 2 2006.173.02:37:57.52#ibcon#read 3, iclass 38, count 2 2006.173.02:37:57.52#ibcon#about to read 4, iclass 38, count 2 2006.173.02:37:57.52#ibcon#read 4, iclass 38, count 2 2006.173.02:37:57.52#ibcon#about to read 5, iclass 38, count 2 2006.173.02:37:57.52#ibcon#read 5, iclass 38, count 2 2006.173.02:37:57.52#ibcon#about to read 6, iclass 38, count 2 2006.173.02:37:57.52#ibcon#read 6, iclass 38, count 2 2006.173.02:37:57.52#ibcon#end of sib2, iclass 38, count 2 2006.173.02:37:57.52#ibcon#*after write, iclass 38, count 2 2006.173.02:37:57.52#ibcon#*before return 0, iclass 38, count 2 2006.173.02:37:57.52#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.02:37:57.52#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.02:37:57.52#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.02:37:57.52#ibcon#ireg 7 cls_cnt 0 2006.173.02:37:57.52#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.02:37:57.64#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.02:37:57.64#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.02:37:57.64#ibcon#enter wrdev, iclass 38, count 0 2006.173.02:37:57.64#ibcon#first serial, iclass 38, count 0 2006.173.02:37:57.64#ibcon#enter sib2, iclass 38, count 0 2006.173.02:37:57.64#ibcon#flushed, iclass 38, count 0 2006.173.02:37:57.64#ibcon#about to write, iclass 38, count 0 2006.173.02:37:57.64#ibcon#wrote, iclass 38, count 0 2006.173.02:37:57.64#ibcon#about to read 3, iclass 38, count 0 2006.173.02:37:57.66#ibcon#read 3, iclass 38, count 0 2006.173.02:37:57.66#ibcon#about to read 4, iclass 38, count 0 2006.173.02:37:57.66#ibcon#read 4, iclass 38, count 0 2006.173.02:37:57.66#ibcon#about to read 5, iclass 38, count 0 2006.173.02:37:57.66#ibcon#read 5, iclass 38, count 0 2006.173.02:37:57.66#ibcon#about to read 6, iclass 38, count 0 2006.173.02:37:57.66#ibcon#read 6, iclass 38, count 0 2006.173.02:37:57.66#ibcon#end of sib2, iclass 38, count 0 2006.173.02:37:57.66#ibcon#*mode == 0, iclass 38, count 0 2006.173.02:37:57.66#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.02:37:57.66#ibcon#[25=USB\r\n] 2006.173.02:37:57.66#ibcon#*before write, iclass 38, count 0 2006.173.02:37:57.66#ibcon#enter sib2, iclass 38, count 0 2006.173.02:37:57.66#ibcon#flushed, iclass 38, count 0 2006.173.02:37:57.66#ibcon#about to write, iclass 38, count 0 2006.173.02:37:57.66#ibcon#wrote, iclass 38, count 0 2006.173.02:37:57.66#ibcon#about to read 3, iclass 38, count 0 2006.173.02:37:57.69#ibcon#read 3, iclass 38, count 0 2006.173.02:37:57.69#ibcon#about to read 4, iclass 38, count 0 2006.173.02:37:57.69#ibcon#read 4, iclass 38, count 0 2006.173.02:37:57.69#ibcon#about to read 5, iclass 38, count 0 2006.173.02:37:57.69#ibcon#read 5, iclass 38, count 0 2006.173.02:37:57.69#ibcon#about to read 6, iclass 38, count 0 2006.173.02:37:57.69#ibcon#read 6, iclass 38, count 0 2006.173.02:37:57.69#ibcon#end of sib2, iclass 38, count 0 2006.173.02:37:57.69#ibcon#*after write, iclass 38, count 0 2006.173.02:37:57.69#ibcon#*before return 0, iclass 38, count 0 2006.173.02:37:57.69#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.02:37:57.69#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.02:37:57.69#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.02:37:57.69#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.02:37:57.69$vck44/valo=8,884.99 2006.173.02:37:57.69#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.02:37:57.69#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.02:37:57.69#ibcon#ireg 17 cls_cnt 0 2006.173.02:37:57.69#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.02:37:57.69#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.02:37:57.69#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.02:37:57.69#ibcon#enter wrdev, iclass 40, count 0 2006.173.02:37:57.69#ibcon#first serial, iclass 40, count 0 2006.173.02:37:57.69#ibcon#enter sib2, iclass 40, count 0 2006.173.02:37:57.69#ibcon#flushed, iclass 40, count 0 2006.173.02:37:57.69#ibcon#about to write, iclass 40, count 0 2006.173.02:37:57.69#ibcon#wrote, iclass 40, count 0 2006.173.02:37:57.69#ibcon#about to read 3, iclass 40, count 0 2006.173.02:37:57.71#ibcon#read 3, iclass 40, count 0 2006.173.02:37:57.71#ibcon#about to read 4, iclass 40, count 0 2006.173.02:37:57.71#ibcon#read 4, iclass 40, count 0 2006.173.02:37:57.71#ibcon#about to read 5, iclass 40, count 0 2006.173.02:37:57.71#ibcon#read 5, iclass 40, count 0 2006.173.02:37:57.71#ibcon#about to read 6, iclass 40, count 0 2006.173.02:37:57.71#ibcon#read 6, iclass 40, count 0 2006.173.02:37:57.71#ibcon#end of sib2, iclass 40, count 0 2006.173.02:37:57.71#ibcon#*mode == 0, iclass 40, count 0 2006.173.02:37:57.71#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.02:37:57.71#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.02:37:57.71#ibcon#*before write, iclass 40, count 0 2006.173.02:37:57.71#ibcon#enter sib2, iclass 40, count 0 2006.173.02:37:57.71#ibcon#flushed, iclass 40, count 0 2006.173.02:37:57.71#ibcon#about to write, iclass 40, count 0 2006.173.02:37:57.71#ibcon#wrote, iclass 40, count 0 2006.173.02:37:57.71#ibcon#about to read 3, iclass 40, count 0 2006.173.02:37:57.75#ibcon#read 3, iclass 40, count 0 2006.173.02:37:57.75#ibcon#about to read 4, iclass 40, count 0 2006.173.02:37:57.75#ibcon#read 4, iclass 40, count 0 2006.173.02:37:57.75#ibcon#about to read 5, iclass 40, count 0 2006.173.02:37:57.75#ibcon#read 5, iclass 40, count 0 2006.173.02:37:57.75#ibcon#about to read 6, iclass 40, count 0 2006.173.02:37:57.75#ibcon#read 6, iclass 40, count 0 2006.173.02:37:57.75#ibcon#end of sib2, iclass 40, count 0 2006.173.02:37:57.75#ibcon#*after write, iclass 40, count 0 2006.173.02:37:57.75#ibcon#*before return 0, iclass 40, count 0 2006.173.02:37:57.75#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.02:37:57.75#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.02:37:57.75#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.02:37:57.75#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.02:37:57.75$vck44/va=8,4 2006.173.02:37:57.75#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.02:37:57.75#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.02:37:57.75#ibcon#ireg 11 cls_cnt 2 2006.173.02:37:57.75#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.02:37:57.81#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.02:37:57.81#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.02:37:57.81#ibcon#enter wrdev, iclass 4, count 2 2006.173.02:37:57.81#ibcon#first serial, iclass 4, count 2 2006.173.02:37:57.81#ibcon#enter sib2, iclass 4, count 2 2006.173.02:37:57.81#ibcon#flushed, iclass 4, count 2 2006.173.02:37:57.81#ibcon#about to write, iclass 4, count 2 2006.173.02:37:57.81#ibcon#wrote, iclass 4, count 2 2006.173.02:37:57.81#ibcon#about to read 3, iclass 4, count 2 2006.173.02:37:57.83#ibcon#read 3, iclass 4, count 2 2006.173.02:37:57.83#ibcon#about to read 4, iclass 4, count 2 2006.173.02:37:57.83#ibcon#read 4, iclass 4, count 2 2006.173.02:37:57.83#ibcon#about to read 5, iclass 4, count 2 2006.173.02:37:57.83#ibcon#read 5, iclass 4, count 2 2006.173.02:37:57.83#ibcon#about to read 6, iclass 4, count 2 2006.173.02:37:57.83#ibcon#read 6, iclass 4, count 2 2006.173.02:37:57.83#ibcon#end of sib2, iclass 4, count 2 2006.173.02:37:57.83#ibcon#*mode == 0, iclass 4, count 2 2006.173.02:37:57.83#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.02:37:57.83#ibcon#[25=AT08-04\r\n] 2006.173.02:37:57.83#ibcon#*before write, iclass 4, count 2 2006.173.02:37:57.83#ibcon#enter sib2, iclass 4, count 2 2006.173.02:37:57.83#ibcon#flushed, iclass 4, count 2 2006.173.02:37:57.83#ibcon#about to write, iclass 4, count 2 2006.173.02:37:57.83#ibcon#wrote, iclass 4, count 2 2006.173.02:37:57.83#ibcon#about to read 3, iclass 4, count 2 2006.173.02:37:57.86#ibcon#read 3, iclass 4, count 2 2006.173.02:37:57.86#ibcon#about to read 4, iclass 4, count 2 2006.173.02:37:57.86#ibcon#read 4, iclass 4, count 2 2006.173.02:37:57.86#ibcon#about to read 5, iclass 4, count 2 2006.173.02:37:57.86#ibcon#read 5, iclass 4, count 2 2006.173.02:37:57.86#ibcon#about to read 6, iclass 4, count 2 2006.173.02:37:57.86#ibcon#read 6, iclass 4, count 2 2006.173.02:37:57.86#ibcon#end of sib2, iclass 4, count 2 2006.173.02:37:57.86#ibcon#*after write, iclass 4, count 2 2006.173.02:37:57.86#ibcon#*before return 0, iclass 4, count 2 2006.173.02:37:57.86#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.02:37:57.86#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.02:37:57.86#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.02:37:57.86#ibcon#ireg 7 cls_cnt 0 2006.173.02:37:57.86#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.02:37:57.98#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.02:37:57.98#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.02:37:57.98#ibcon#enter wrdev, iclass 4, count 0 2006.173.02:37:57.98#ibcon#first serial, iclass 4, count 0 2006.173.02:37:57.98#ibcon#enter sib2, iclass 4, count 0 2006.173.02:37:57.98#ibcon#flushed, iclass 4, count 0 2006.173.02:37:57.98#ibcon#about to write, iclass 4, count 0 2006.173.02:37:57.98#ibcon#wrote, iclass 4, count 0 2006.173.02:37:57.98#ibcon#about to read 3, iclass 4, count 0 2006.173.02:37:58.00#ibcon#read 3, iclass 4, count 0 2006.173.02:37:58.00#ibcon#about to read 4, iclass 4, count 0 2006.173.02:37:58.00#ibcon#read 4, iclass 4, count 0 2006.173.02:37:58.00#ibcon#about to read 5, iclass 4, count 0 2006.173.02:37:58.00#ibcon#read 5, iclass 4, count 0 2006.173.02:37:58.00#ibcon#about to read 6, iclass 4, count 0 2006.173.02:37:58.00#ibcon#read 6, iclass 4, count 0 2006.173.02:37:58.00#ibcon#end of sib2, iclass 4, count 0 2006.173.02:37:58.00#ibcon#*mode == 0, iclass 4, count 0 2006.173.02:37:58.00#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.02:37:58.00#ibcon#[25=USB\r\n] 2006.173.02:37:58.00#ibcon#*before write, iclass 4, count 0 2006.173.02:37:58.00#ibcon#enter sib2, iclass 4, count 0 2006.173.02:37:58.00#ibcon#flushed, iclass 4, count 0 2006.173.02:37:58.00#ibcon#about to write, iclass 4, count 0 2006.173.02:37:58.00#ibcon#wrote, iclass 4, count 0 2006.173.02:37:58.00#ibcon#about to read 3, iclass 4, count 0 2006.173.02:37:58.03#ibcon#read 3, iclass 4, count 0 2006.173.02:37:58.03#ibcon#about to read 4, iclass 4, count 0 2006.173.02:37:58.03#ibcon#read 4, iclass 4, count 0 2006.173.02:37:58.03#ibcon#about to read 5, iclass 4, count 0 2006.173.02:37:58.03#ibcon#read 5, iclass 4, count 0 2006.173.02:37:58.03#ibcon#about to read 6, iclass 4, count 0 2006.173.02:37:58.03#ibcon#read 6, iclass 4, count 0 2006.173.02:37:58.03#ibcon#end of sib2, iclass 4, count 0 2006.173.02:37:58.03#ibcon#*after write, iclass 4, count 0 2006.173.02:37:58.03#ibcon#*before return 0, iclass 4, count 0 2006.173.02:37:58.03#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.02:37:58.03#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.02:37:58.03#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.02:37:58.03#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.02:37:58.03$vck44/vblo=1,629.99 2006.173.02:37:58.03#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.02:37:58.03#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.02:37:58.03#ibcon#ireg 17 cls_cnt 0 2006.173.02:37:58.03#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.02:37:58.03#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.02:37:58.03#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.02:37:58.03#ibcon#enter wrdev, iclass 6, count 0 2006.173.02:37:58.03#ibcon#first serial, iclass 6, count 0 2006.173.02:37:58.03#ibcon#enter sib2, iclass 6, count 0 2006.173.02:37:58.03#ibcon#flushed, iclass 6, count 0 2006.173.02:37:58.03#ibcon#about to write, iclass 6, count 0 2006.173.02:37:58.03#ibcon#wrote, iclass 6, count 0 2006.173.02:37:58.03#ibcon#about to read 3, iclass 6, count 0 2006.173.02:37:58.05#ibcon#read 3, iclass 6, count 0 2006.173.02:37:58.05#ibcon#about to read 4, iclass 6, count 0 2006.173.02:37:58.05#ibcon#read 4, iclass 6, count 0 2006.173.02:37:58.05#ibcon#about to read 5, iclass 6, count 0 2006.173.02:37:58.05#ibcon#read 5, iclass 6, count 0 2006.173.02:37:58.05#ibcon#about to read 6, iclass 6, count 0 2006.173.02:37:58.05#ibcon#read 6, iclass 6, count 0 2006.173.02:37:58.05#ibcon#end of sib2, iclass 6, count 0 2006.173.02:37:58.05#ibcon#*mode == 0, iclass 6, count 0 2006.173.02:37:58.05#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.02:37:58.05#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.02:37:58.05#ibcon#*before write, iclass 6, count 0 2006.173.02:37:58.05#ibcon#enter sib2, iclass 6, count 0 2006.173.02:37:58.05#ibcon#flushed, iclass 6, count 0 2006.173.02:37:58.05#ibcon#about to write, iclass 6, count 0 2006.173.02:37:58.05#ibcon#wrote, iclass 6, count 0 2006.173.02:37:58.05#ibcon#about to read 3, iclass 6, count 0 2006.173.02:37:58.09#ibcon#read 3, iclass 6, count 0 2006.173.02:37:58.09#ibcon#about to read 4, iclass 6, count 0 2006.173.02:37:58.09#ibcon#read 4, iclass 6, count 0 2006.173.02:37:58.09#ibcon#about to read 5, iclass 6, count 0 2006.173.02:37:58.09#ibcon#read 5, iclass 6, count 0 2006.173.02:37:58.09#ibcon#about to read 6, iclass 6, count 0 2006.173.02:37:58.09#ibcon#read 6, iclass 6, count 0 2006.173.02:37:58.09#ibcon#end of sib2, iclass 6, count 0 2006.173.02:37:58.09#ibcon#*after write, iclass 6, count 0 2006.173.02:37:58.09#ibcon#*before return 0, iclass 6, count 0 2006.173.02:37:58.09#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.02:37:58.09#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.02:37:58.09#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.02:37:58.09#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.02:37:58.09$vck44/vb=1,4 2006.173.02:37:58.09#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.02:37:58.09#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.02:37:58.09#ibcon#ireg 11 cls_cnt 2 2006.173.02:37:58.09#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.02:37:58.09#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.02:37:58.09#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.02:37:58.09#ibcon#enter wrdev, iclass 10, count 2 2006.173.02:37:58.09#ibcon#first serial, iclass 10, count 2 2006.173.02:37:58.09#ibcon#enter sib2, iclass 10, count 2 2006.173.02:37:58.09#ibcon#flushed, iclass 10, count 2 2006.173.02:37:58.09#ibcon#about to write, iclass 10, count 2 2006.173.02:37:58.09#ibcon#wrote, iclass 10, count 2 2006.173.02:37:58.09#ibcon#about to read 3, iclass 10, count 2 2006.173.02:37:58.11#ibcon#read 3, iclass 10, count 2 2006.173.02:37:58.11#ibcon#about to read 4, iclass 10, count 2 2006.173.02:37:58.11#ibcon#read 4, iclass 10, count 2 2006.173.02:37:58.11#ibcon#about to read 5, iclass 10, count 2 2006.173.02:37:58.11#ibcon#read 5, iclass 10, count 2 2006.173.02:37:58.11#ibcon#about to read 6, iclass 10, count 2 2006.173.02:37:58.11#ibcon#read 6, iclass 10, count 2 2006.173.02:37:58.11#ibcon#end of sib2, iclass 10, count 2 2006.173.02:37:58.11#ibcon#*mode == 0, iclass 10, count 2 2006.173.02:37:58.11#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.02:37:58.11#ibcon#[27=AT01-04\r\n] 2006.173.02:37:58.11#ibcon#*before write, iclass 10, count 2 2006.173.02:37:58.11#ibcon#enter sib2, iclass 10, count 2 2006.173.02:37:58.11#ibcon#flushed, iclass 10, count 2 2006.173.02:37:58.11#ibcon#about to write, iclass 10, count 2 2006.173.02:37:58.11#ibcon#wrote, iclass 10, count 2 2006.173.02:37:58.11#ibcon#about to read 3, iclass 10, count 2 2006.173.02:37:58.14#ibcon#read 3, iclass 10, count 2 2006.173.02:37:58.14#ibcon#about to read 4, iclass 10, count 2 2006.173.02:37:58.14#ibcon#read 4, iclass 10, count 2 2006.173.02:37:58.14#ibcon#about to read 5, iclass 10, count 2 2006.173.02:37:58.14#ibcon#read 5, iclass 10, count 2 2006.173.02:37:58.14#ibcon#about to read 6, iclass 10, count 2 2006.173.02:37:58.14#ibcon#read 6, iclass 10, count 2 2006.173.02:37:58.14#ibcon#end of sib2, iclass 10, count 2 2006.173.02:37:58.14#ibcon#*after write, iclass 10, count 2 2006.173.02:37:58.14#ibcon#*before return 0, iclass 10, count 2 2006.173.02:37:58.14#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.02:37:58.14#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.02:37:58.14#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.02:37:58.14#ibcon#ireg 7 cls_cnt 0 2006.173.02:37:58.14#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.02:37:58.26#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.02:37:58.26#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.02:37:58.26#ibcon#enter wrdev, iclass 10, count 0 2006.173.02:37:58.26#ibcon#first serial, iclass 10, count 0 2006.173.02:37:58.26#ibcon#enter sib2, iclass 10, count 0 2006.173.02:37:58.26#ibcon#flushed, iclass 10, count 0 2006.173.02:37:58.26#ibcon#about to write, iclass 10, count 0 2006.173.02:37:58.26#ibcon#wrote, iclass 10, count 0 2006.173.02:37:58.26#ibcon#about to read 3, iclass 10, count 0 2006.173.02:37:58.28#ibcon#read 3, iclass 10, count 0 2006.173.02:37:58.28#ibcon#about to read 4, iclass 10, count 0 2006.173.02:37:58.28#ibcon#read 4, iclass 10, count 0 2006.173.02:37:58.28#ibcon#about to read 5, iclass 10, count 0 2006.173.02:37:58.28#ibcon#read 5, iclass 10, count 0 2006.173.02:37:58.28#ibcon#about to read 6, iclass 10, count 0 2006.173.02:37:58.28#ibcon#read 6, iclass 10, count 0 2006.173.02:37:58.28#ibcon#end of sib2, iclass 10, count 0 2006.173.02:37:58.28#ibcon#*mode == 0, iclass 10, count 0 2006.173.02:37:58.28#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.02:37:58.28#ibcon#[27=USB\r\n] 2006.173.02:37:58.28#ibcon#*before write, iclass 10, count 0 2006.173.02:37:58.28#ibcon#enter sib2, iclass 10, count 0 2006.173.02:37:58.28#ibcon#flushed, iclass 10, count 0 2006.173.02:37:58.28#ibcon#about to write, iclass 10, count 0 2006.173.02:37:58.28#ibcon#wrote, iclass 10, count 0 2006.173.02:37:58.28#ibcon#about to read 3, iclass 10, count 0 2006.173.02:37:58.31#ibcon#read 3, iclass 10, count 0 2006.173.02:37:58.31#ibcon#about to read 4, iclass 10, count 0 2006.173.02:37:58.31#ibcon#read 4, iclass 10, count 0 2006.173.02:37:58.31#ibcon#about to read 5, iclass 10, count 0 2006.173.02:37:58.31#ibcon#read 5, iclass 10, count 0 2006.173.02:37:58.31#ibcon#about to read 6, iclass 10, count 0 2006.173.02:37:58.31#ibcon#read 6, iclass 10, count 0 2006.173.02:37:58.31#ibcon#end of sib2, iclass 10, count 0 2006.173.02:37:58.31#ibcon#*after write, iclass 10, count 0 2006.173.02:37:58.31#ibcon#*before return 0, iclass 10, count 0 2006.173.02:37:58.31#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.02:37:58.31#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.02:37:58.31#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.02:37:58.31#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.02:37:58.31$vck44/vblo=2,634.99 2006.173.02:37:58.31#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.02:37:58.31#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.02:37:58.31#ibcon#ireg 17 cls_cnt 0 2006.173.02:37:58.31#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.02:37:58.31#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.02:37:58.31#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.02:37:58.31#ibcon#enter wrdev, iclass 12, count 0 2006.173.02:37:58.31#ibcon#first serial, iclass 12, count 0 2006.173.02:37:58.31#ibcon#enter sib2, iclass 12, count 0 2006.173.02:37:58.31#ibcon#flushed, iclass 12, count 0 2006.173.02:37:58.31#ibcon#about to write, iclass 12, count 0 2006.173.02:37:58.31#ibcon#wrote, iclass 12, count 0 2006.173.02:37:58.31#ibcon#about to read 3, iclass 12, count 0 2006.173.02:37:58.33#ibcon#read 3, iclass 12, count 0 2006.173.02:37:58.33#ibcon#about to read 4, iclass 12, count 0 2006.173.02:37:58.33#ibcon#read 4, iclass 12, count 0 2006.173.02:37:58.33#ibcon#about to read 5, iclass 12, count 0 2006.173.02:37:58.33#ibcon#read 5, iclass 12, count 0 2006.173.02:37:58.33#ibcon#about to read 6, iclass 12, count 0 2006.173.02:37:58.33#ibcon#read 6, iclass 12, count 0 2006.173.02:37:58.33#ibcon#end of sib2, iclass 12, count 0 2006.173.02:37:58.33#ibcon#*mode == 0, iclass 12, count 0 2006.173.02:37:58.33#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.02:37:58.33#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.02:37:58.33#ibcon#*before write, iclass 12, count 0 2006.173.02:37:58.33#ibcon#enter sib2, iclass 12, count 0 2006.173.02:37:58.33#ibcon#flushed, iclass 12, count 0 2006.173.02:37:58.33#ibcon#about to write, iclass 12, count 0 2006.173.02:37:58.33#ibcon#wrote, iclass 12, count 0 2006.173.02:37:58.33#ibcon#about to read 3, iclass 12, count 0 2006.173.02:37:58.37#ibcon#read 3, iclass 12, count 0 2006.173.02:37:58.37#ibcon#about to read 4, iclass 12, count 0 2006.173.02:37:58.37#ibcon#read 4, iclass 12, count 0 2006.173.02:37:58.37#ibcon#about to read 5, iclass 12, count 0 2006.173.02:37:58.37#ibcon#read 5, iclass 12, count 0 2006.173.02:37:58.37#ibcon#about to read 6, iclass 12, count 0 2006.173.02:37:58.37#ibcon#read 6, iclass 12, count 0 2006.173.02:37:58.37#ibcon#end of sib2, iclass 12, count 0 2006.173.02:37:58.37#ibcon#*after write, iclass 12, count 0 2006.173.02:37:58.37#ibcon#*before return 0, iclass 12, count 0 2006.173.02:37:58.37#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.02:37:58.37#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.02:37:58.37#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.02:37:58.37#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.02:37:58.37$vck44/vb=2,4 2006.173.02:37:58.37#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.02:37:58.37#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.02:37:58.37#ibcon#ireg 11 cls_cnt 2 2006.173.02:37:58.37#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.02:37:58.43#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.02:37:58.43#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.02:37:58.43#ibcon#enter wrdev, iclass 14, count 2 2006.173.02:37:58.43#ibcon#first serial, iclass 14, count 2 2006.173.02:37:58.43#ibcon#enter sib2, iclass 14, count 2 2006.173.02:37:58.43#ibcon#flushed, iclass 14, count 2 2006.173.02:37:58.43#ibcon#about to write, iclass 14, count 2 2006.173.02:37:58.43#ibcon#wrote, iclass 14, count 2 2006.173.02:37:58.43#ibcon#about to read 3, iclass 14, count 2 2006.173.02:37:58.45#ibcon#read 3, iclass 14, count 2 2006.173.02:37:58.45#ibcon#about to read 4, iclass 14, count 2 2006.173.02:37:58.45#ibcon#read 4, iclass 14, count 2 2006.173.02:37:58.45#ibcon#about to read 5, iclass 14, count 2 2006.173.02:37:58.45#ibcon#read 5, iclass 14, count 2 2006.173.02:37:58.45#ibcon#about to read 6, iclass 14, count 2 2006.173.02:37:58.45#ibcon#read 6, iclass 14, count 2 2006.173.02:37:58.45#ibcon#end of sib2, iclass 14, count 2 2006.173.02:37:58.45#ibcon#*mode == 0, iclass 14, count 2 2006.173.02:37:58.45#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.02:37:58.45#ibcon#[27=AT02-04\r\n] 2006.173.02:37:58.45#ibcon#*before write, iclass 14, count 2 2006.173.02:37:58.45#ibcon#enter sib2, iclass 14, count 2 2006.173.02:37:58.45#ibcon#flushed, iclass 14, count 2 2006.173.02:37:58.45#ibcon#about to write, iclass 14, count 2 2006.173.02:37:58.45#ibcon#wrote, iclass 14, count 2 2006.173.02:37:58.45#ibcon#about to read 3, iclass 14, count 2 2006.173.02:37:58.48#ibcon#read 3, iclass 14, count 2 2006.173.02:37:58.48#ibcon#about to read 4, iclass 14, count 2 2006.173.02:37:58.48#ibcon#read 4, iclass 14, count 2 2006.173.02:37:58.48#ibcon#about to read 5, iclass 14, count 2 2006.173.02:37:58.48#ibcon#read 5, iclass 14, count 2 2006.173.02:37:58.48#ibcon#about to read 6, iclass 14, count 2 2006.173.02:37:58.48#ibcon#read 6, iclass 14, count 2 2006.173.02:37:58.48#ibcon#end of sib2, iclass 14, count 2 2006.173.02:37:58.48#ibcon#*after write, iclass 14, count 2 2006.173.02:37:58.48#ibcon#*before return 0, iclass 14, count 2 2006.173.02:37:58.48#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.02:37:58.48#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.02:37:58.48#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.02:37:58.48#ibcon#ireg 7 cls_cnt 0 2006.173.02:37:58.48#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.02:37:58.60#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.02:37:58.60#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.02:37:58.60#ibcon#enter wrdev, iclass 14, count 0 2006.173.02:37:58.60#ibcon#first serial, iclass 14, count 0 2006.173.02:37:58.60#ibcon#enter sib2, iclass 14, count 0 2006.173.02:37:58.60#ibcon#flushed, iclass 14, count 0 2006.173.02:37:58.60#ibcon#about to write, iclass 14, count 0 2006.173.02:37:58.60#ibcon#wrote, iclass 14, count 0 2006.173.02:37:58.60#ibcon#about to read 3, iclass 14, count 0 2006.173.02:37:58.62#ibcon#read 3, iclass 14, count 0 2006.173.02:37:58.62#ibcon#about to read 4, iclass 14, count 0 2006.173.02:37:58.62#ibcon#read 4, iclass 14, count 0 2006.173.02:37:58.62#ibcon#about to read 5, iclass 14, count 0 2006.173.02:37:58.62#ibcon#read 5, iclass 14, count 0 2006.173.02:37:58.62#ibcon#about to read 6, iclass 14, count 0 2006.173.02:37:58.62#ibcon#read 6, iclass 14, count 0 2006.173.02:37:58.62#ibcon#end of sib2, iclass 14, count 0 2006.173.02:37:58.62#ibcon#*mode == 0, iclass 14, count 0 2006.173.02:37:58.62#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.02:37:58.62#ibcon#[27=USB\r\n] 2006.173.02:37:58.62#ibcon#*before write, iclass 14, count 0 2006.173.02:37:58.62#ibcon#enter sib2, iclass 14, count 0 2006.173.02:37:58.62#ibcon#flushed, iclass 14, count 0 2006.173.02:37:58.62#ibcon#about to write, iclass 14, count 0 2006.173.02:37:58.62#ibcon#wrote, iclass 14, count 0 2006.173.02:37:58.62#ibcon#about to read 3, iclass 14, count 0 2006.173.02:37:58.65#ibcon#read 3, iclass 14, count 0 2006.173.02:37:58.65#ibcon#about to read 4, iclass 14, count 0 2006.173.02:37:58.65#ibcon#read 4, iclass 14, count 0 2006.173.02:37:58.65#ibcon#about to read 5, iclass 14, count 0 2006.173.02:37:58.65#ibcon#read 5, iclass 14, count 0 2006.173.02:37:58.65#ibcon#about to read 6, iclass 14, count 0 2006.173.02:37:58.65#ibcon#read 6, iclass 14, count 0 2006.173.02:37:58.65#ibcon#end of sib2, iclass 14, count 0 2006.173.02:37:58.65#ibcon#*after write, iclass 14, count 0 2006.173.02:37:58.65#ibcon#*before return 0, iclass 14, count 0 2006.173.02:37:58.65#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.02:37:58.65#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.02:37:58.65#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.02:37:58.65#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.02:37:58.65$vck44/vblo=3,649.99 2006.173.02:37:58.65#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.02:37:58.65#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.02:37:58.65#ibcon#ireg 17 cls_cnt 0 2006.173.02:37:58.65#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.02:37:58.65#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.02:37:58.65#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.02:37:58.65#ibcon#enter wrdev, iclass 16, count 0 2006.173.02:37:58.65#ibcon#first serial, iclass 16, count 0 2006.173.02:37:58.65#ibcon#enter sib2, iclass 16, count 0 2006.173.02:37:58.65#ibcon#flushed, iclass 16, count 0 2006.173.02:37:58.65#ibcon#about to write, iclass 16, count 0 2006.173.02:37:58.65#ibcon#wrote, iclass 16, count 0 2006.173.02:37:58.65#ibcon#about to read 3, iclass 16, count 0 2006.173.02:37:58.67#ibcon#read 3, iclass 16, count 0 2006.173.02:37:58.67#ibcon#about to read 4, iclass 16, count 0 2006.173.02:37:58.67#ibcon#read 4, iclass 16, count 0 2006.173.02:37:58.67#ibcon#about to read 5, iclass 16, count 0 2006.173.02:37:58.67#ibcon#read 5, iclass 16, count 0 2006.173.02:37:58.67#ibcon#about to read 6, iclass 16, count 0 2006.173.02:37:58.67#ibcon#read 6, iclass 16, count 0 2006.173.02:37:58.67#ibcon#end of sib2, iclass 16, count 0 2006.173.02:37:58.67#ibcon#*mode == 0, iclass 16, count 0 2006.173.02:37:58.67#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.02:37:58.67#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.02:37:58.67#ibcon#*before write, iclass 16, count 0 2006.173.02:37:58.67#ibcon#enter sib2, iclass 16, count 0 2006.173.02:37:58.67#ibcon#flushed, iclass 16, count 0 2006.173.02:37:58.67#ibcon#about to write, iclass 16, count 0 2006.173.02:37:58.67#ibcon#wrote, iclass 16, count 0 2006.173.02:37:58.67#ibcon#about to read 3, iclass 16, count 0 2006.173.02:37:58.71#ibcon#read 3, iclass 16, count 0 2006.173.02:37:58.71#ibcon#about to read 4, iclass 16, count 0 2006.173.02:37:58.71#ibcon#read 4, iclass 16, count 0 2006.173.02:37:58.71#ibcon#about to read 5, iclass 16, count 0 2006.173.02:37:58.71#ibcon#read 5, iclass 16, count 0 2006.173.02:37:58.71#ibcon#about to read 6, iclass 16, count 0 2006.173.02:37:58.71#ibcon#read 6, iclass 16, count 0 2006.173.02:37:58.71#ibcon#end of sib2, iclass 16, count 0 2006.173.02:37:58.71#ibcon#*after write, iclass 16, count 0 2006.173.02:37:58.71#ibcon#*before return 0, iclass 16, count 0 2006.173.02:37:58.71#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.02:37:58.71#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.02:37:58.71#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.02:37:58.71#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.02:37:58.71$vck44/vb=3,4 2006.173.02:37:58.71#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.02:37:58.71#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.02:37:58.71#ibcon#ireg 11 cls_cnt 2 2006.173.02:37:58.71#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.02:37:58.77#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.02:37:58.77#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.02:37:58.77#ibcon#enter wrdev, iclass 18, count 2 2006.173.02:37:58.77#ibcon#first serial, iclass 18, count 2 2006.173.02:37:58.77#ibcon#enter sib2, iclass 18, count 2 2006.173.02:37:58.77#ibcon#flushed, iclass 18, count 2 2006.173.02:37:58.77#ibcon#about to write, iclass 18, count 2 2006.173.02:37:58.77#ibcon#wrote, iclass 18, count 2 2006.173.02:37:58.77#ibcon#about to read 3, iclass 18, count 2 2006.173.02:37:58.79#ibcon#read 3, iclass 18, count 2 2006.173.02:37:58.79#ibcon#about to read 4, iclass 18, count 2 2006.173.02:37:58.79#ibcon#read 4, iclass 18, count 2 2006.173.02:37:58.79#ibcon#about to read 5, iclass 18, count 2 2006.173.02:37:58.79#ibcon#read 5, iclass 18, count 2 2006.173.02:37:58.79#ibcon#about to read 6, iclass 18, count 2 2006.173.02:37:58.79#ibcon#read 6, iclass 18, count 2 2006.173.02:37:58.79#ibcon#end of sib2, iclass 18, count 2 2006.173.02:37:58.79#ibcon#*mode == 0, iclass 18, count 2 2006.173.02:37:58.79#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.02:37:58.79#ibcon#[27=AT03-04\r\n] 2006.173.02:37:58.79#ibcon#*before write, iclass 18, count 2 2006.173.02:37:58.79#ibcon#enter sib2, iclass 18, count 2 2006.173.02:37:58.79#ibcon#flushed, iclass 18, count 2 2006.173.02:37:58.79#ibcon#about to write, iclass 18, count 2 2006.173.02:37:58.79#ibcon#wrote, iclass 18, count 2 2006.173.02:37:58.79#ibcon#about to read 3, iclass 18, count 2 2006.173.02:37:58.82#ibcon#read 3, iclass 18, count 2 2006.173.02:37:58.82#ibcon#about to read 4, iclass 18, count 2 2006.173.02:37:58.82#ibcon#read 4, iclass 18, count 2 2006.173.02:37:58.82#ibcon#about to read 5, iclass 18, count 2 2006.173.02:37:58.82#ibcon#read 5, iclass 18, count 2 2006.173.02:37:58.82#ibcon#about to read 6, iclass 18, count 2 2006.173.02:37:58.82#ibcon#read 6, iclass 18, count 2 2006.173.02:37:58.82#ibcon#end of sib2, iclass 18, count 2 2006.173.02:37:58.82#ibcon#*after write, iclass 18, count 2 2006.173.02:37:58.82#ibcon#*before return 0, iclass 18, count 2 2006.173.02:37:58.82#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.02:37:58.82#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.02:37:58.82#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.02:37:58.82#ibcon#ireg 7 cls_cnt 0 2006.173.02:37:58.82#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.02:37:58.94#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.02:37:58.94#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.02:37:58.94#ibcon#enter wrdev, iclass 18, count 0 2006.173.02:37:58.94#ibcon#first serial, iclass 18, count 0 2006.173.02:37:58.94#ibcon#enter sib2, iclass 18, count 0 2006.173.02:37:58.94#ibcon#flushed, iclass 18, count 0 2006.173.02:37:58.94#ibcon#about to write, iclass 18, count 0 2006.173.02:37:58.94#ibcon#wrote, iclass 18, count 0 2006.173.02:37:58.94#ibcon#about to read 3, iclass 18, count 0 2006.173.02:37:58.96#ibcon#read 3, iclass 18, count 0 2006.173.02:37:58.96#ibcon#about to read 4, iclass 18, count 0 2006.173.02:37:58.96#ibcon#read 4, iclass 18, count 0 2006.173.02:37:58.96#ibcon#about to read 5, iclass 18, count 0 2006.173.02:37:58.96#ibcon#read 5, iclass 18, count 0 2006.173.02:37:58.96#ibcon#about to read 6, iclass 18, count 0 2006.173.02:37:58.96#ibcon#read 6, iclass 18, count 0 2006.173.02:37:58.96#ibcon#end of sib2, iclass 18, count 0 2006.173.02:37:58.96#ibcon#*mode == 0, iclass 18, count 0 2006.173.02:37:58.96#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.02:37:58.96#ibcon#[27=USB\r\n] 2006.173.02:37:58.96#ibcon#*before write, iclass 18, count 0 2006.173.02:37:58.96#ibcon#enter sib2, iclass 18, count 0 2006.173.02:37:58.96#ibcon#flushed, iclass 18, count 0 2006.173.02:37:58.96#ibcon#about to write, iclass 18, count 0 2006.173.02:37:58.96#ibcon#wrote, iclass 18, count 0 2006.173.02:37:58.96#ibcon#about to read 3, iclass 18, count 0 2006.173.02:37:58.99#ibcon#read 3, iclass 18, count 0 2006.173.02:37:58.99#ibcon#about to read 4, iclass 18, count 0 2006.173.02:37:58.99#ibcon#read 4, iclass 18, count 0 2006.173.02:37:58.99#ibcon#about to read 5, iclass 18, count 0 2006.173.02:37:58.99#ibcon#read 5, iclass 18, count 0 2006.173.02:37:58.99#ibcon#about to read 6, iclass 18, count 0 2006.173.02:37:58.99#ibcon#read 6, iclass 18, count 0 2006.173.02:37:58.99#ibcon#end of sib2, iclass 18, count 0 2006.173.02:37:58.99#ibcon#*after write, iclass 18, count 0 2006.173.02:37:58.99#ibcon#*before return 0, iclass 18, count 0 2006.173.02:37:58.99#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.02:37:58.99#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.02:37:58.99#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.02:37:58.99#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.02:37:58.99$vck44/vblo=4,679.99 2006.173.02:37:58.99#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.02:37:58.99#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.02:37:58.99#ibcon#ireg 17 cls_cnt 0 2006.173.02:37:58.99#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.02:37:58.99#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.02:37:58.99#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.02:37:58.99#ibcon#enter wrdev, iclass 20, count 0 2006.173.02:37:58.99#ibcon#first serial, iclass 20, count 0 2006.173.02:37:58.99#ibcon#enter sib2, iclass 20, count 0 2006.173.02:37:58.99#ibcon#flushed, iclass 20, count 0 2006.173.02:37:58.99#ibcon#about to write, iclass 20, count 0 2006.173.02:37:58.99#ibcon#wrote, iclass 20, count 0 2006.173.02:37:58.99#ibcon#about to read 3, iclass 20, count 0 2006.173.02:37:59.01#ibcon#read 3, iclass 20, count 0 2006.173.02:37:59.01#ibcon#about to read 4, iclass 20, count 0 2006.173.02:37:59.01#ibcon#read 4, iclass 20, count 0 2006.173.02:37:59.01#ibcon#about to read 5, iclass 20, count 0 2006.173.02:37:59.01#ibcon#read 5, iclass 20, count 0 2006.173.02:37:59.01#ibcon#about to read 6, iclass 20, count 0 2006.173.02:37:59.01#ibcon#read 6, iclass 20, count 0 2006.173.02:37:59.01#ibcon#end of sib2, iclass 20, count 0 2006.173.02:37:59.01#ibcon#*mode == 0, iclass 20, count 0 2006.173.02:37:59.01#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.02:37:59.01#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.02:37:59.01#ibcon#*before write, iclass 20, count 0 2006.173.02:37:59.01#ibcon#enter sib2, iclass 20, count 0 2006.173.02:37:59.01#ibcon#flushed, iclass 20, count 0 2006.173.02:37:59.01#ibcon#about to write, iclass 20, count 0 2006.173.02:37:59.01#ibcon#wrote, iclass 20, count 0 2006.173.02:37:59.01#ibcon#about to read 3, iclass 20, count 0 2006.173.02:37:59.05#ibcon#read 3, iclass 20, count 0 2006.173.02:37:59.05#ibcon#about to read 4, iclass 20, count 0 2006.173.02:37:59.05#ibcon#read 4, iclass 20, count 0 2006.173.02:37:59.05#ibcon#about to read 5, iclass 20, count 0 2006.173.02:37:59.05#ibcon#read 5, iclass 20, count 0 2006.173.02:37:59.05#ibcon#about to read 6, iclass 20, count 0 2006.173.02:37:59.05#ibcon#read 6, iclass 20, count 0 2006.173.02:37:59.05#ibcon#end of sib2, iclass 20, count 0 2006.173.02:37:59.05#ibcon#*after write, iclass 20, count 0 2006.173.02:37:59.05#ibcon#*before return 0, iclass 20, count 0 2006.173.02:37:59.05#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.02:37:59.05#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.02:37:59.05#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.02:37:59.05#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.02:37:59.05$vck44/vb=4,4 2006.173.02:37:59.05#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.02:37:59.05#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.02:37:59.05#ibcon#ireg 11 cls_cnt 2 2006.173.02:37:59.05#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.02:37:59.11#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.02:37:59.11#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.02:37:59.11#ibcon#enter wrdev, iclass 22, count 2 2006.173.02:37:59.11#ibcon#first serial, iclass 22, count 2 2006.173.02:37:59.11#ibcon#enter sib2, iclass 22, count 2 2006.173.02:37:59.11#ibcon#flushed, iclass 22, count 2 2006.173.02:37:59.11#ibcon#about to write, iclass 22, count 2 2006.173.02:37:59.11#ibcon#wrote, iclass 22, count 2 2006.173.02:37:59.11#ibcon#about to read 3, iclass 22, count 2 2006.173.02:37:59.13#ibcon#read 3, iclass 22, count 2 2006.173.02:37:59.13#ibcon#about to read 4, iclass 22, count 2 2006.173.02:37:59.13#ibcon#read 4, iclass 22, count 2 2006.173.02:37:59.13#ibcon#about to read 5, iclass 22, count 2 2006.173.02:37:59.13#ibcon#read 5, iclass 22, count 2 2006.173.02:37:59.13#ibcon#about to read 6, iclass 22, count 2 2006.173.02:37:59.13#ibcon#read 6, iclass 22, count 2 2006.173.02:37:59.13#ibcon#end of sib2, iclass 22, count 2 2006.173.02:37:59.13#ibcon#*mode == 0, iclass 22, count 2 2006.173.02:37:59.13#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.02:37:59.13#ibcon#[27=AT04-04\r\n] 2006.173.02:37:59.13#ibcon#*before write, iclass 22, count 2 2006.173.02:37:59.13#ibcon#enter sib2, iclass 22, count 2 2006.173.02:37:59.13#ibcon#flushed, iclass 22, count 2 2006.173.02:37:59.13#ibcon#about to write, iclass 22, count 2 2006.173.02:37:59.13#ibcon#wrote, iclass 22, count 2 2006.173.02:37:59.13#ibcon#about to read 3, iclass 22, count 2 2006.173.02:37:59.16#ibcon#read 3, iclass 22, count 2 2006.173.02:37:59.16#ibcon#about to read 4, iclass 22, count 2 2006.173.02:37:59.16#ibcon#read 4, iclass 22, count 2 2006.173.02:37:59.16#ibcon#about to read 5, iclass 22, count 2 2006.173.02:37:59.16#ibcon#read 5, iclass 22, count 2 2006.173.02:37:59.16#ibcon#about to read 6, iclass 22, count 2 2006.173.02:37:59.16#ibcon#read 6, iclass 22, count 2 2006.173.02:37:59.16#ibcon#end of sib2, iclass 22, count 2 2006.173.02:37:59.16#ibcon#*after write, iclass 22, count 2 2006.173.02:37:59.16#ibcon#*before return 0, iclass 22, count 2 2006.173.02:37:59.16#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.02:37:59.16#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.02:37:59.16#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.02:37:59.16#ibcon#ireg 7 cls_cnt 0 2006.173.02:37:59.16#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.02:37:59.28#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.02:37:59.28#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.02:37:59.28#ibcon#enter wrdev, iclass 22, count 0 2006.173.02:37:59.28#ibcon#first serial, iclass 22, count 0 2006.173.02:37:59.28#ibcon#enter sib2, iclass 22, count 0 2006.173.02:37:59.28#ibcon#flushed, iclass 22, count 0 2006.173.02:37:59.28#ibcon#about to write, iclass 22, count 0 2006.173.02:37:59.28#ibcon#wrote, iclass 22, count 0 2006.173.02:37:59.28#ibcon#about to read 3, iclass 22, count 0 2006.173.02:37:59.30#ibcon#read 3, iclass 22, count 0 2006.173.02:37:59.30#ibcon#about to read 4, iclass 22, count 0 2006.173.02:37:59.30#ibcon#read 4, iclass 22, count 0 2006.173.02:37:59.30#ibcon#about to read 5, iclass 22, count 0 2006.173.02:37:59.30#ibcon#read 5, iclass 22, count 0 2006.173.02:37:59.30#ibcon#about to read 6, iclass 22, count 0 2006.173.02:37:59.30#ibcon#read 6, iclass 22, count 0 2006.173.02:37:59.30#ibcon#end of sib2, iclass 22, count 0 2006.173.02:37:59.30#ibcon#*mode == 0, iclass 22, count 0 2006.173.02:37:59.30#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.02:37:59.30#ibcon#[27=USB\r\n] 2006.173.02:37:59.30#ibcon#*before write, iclass 22, count 0 2006.173.02:37:59.30#ibcon#enter sib2, iclass 22, count 0 2006.173.02:37:59.30#ibcon#flushed, iclass 22, count 0 2006.173.02:37:59.30#ibcon#about to write, iclass 22, count 0 2006.173.02:37:59.30#ibcon#wrote, iclass 22, count 0 2006.173.02:37:59.30#ibcon#about to read 3, iclass 22, count 0 2006.173.02:37:59.33#ibcon#read 3, iclass 22, count 0 2006.173.02:37:59.33#ibcon#about to read 4, iclass 22, count 0 2006.173.02:37:59.33#ibcon#read 4, iclass 22, count 0 2006.173.02:37:59.33#ibcon#about to read 5, iclass 22, count 0 2006.173.02:37:59.33#ibcon#read 5, iclass 22, count 0 2006.173.02:37:59.33#ibcon#about to read 6, iclass 22, count 0 2006.173.02:37:59.33#ibcon#read 6, iclass 22, count 0 2006.173.02:37:59.33#ibcon#end of sib2, iclass 22, count 0 2006.173.02:37:59.33#ibcon#*after write, iclass 22, count 0 2006.173.02:37:59.33#ibcon#*before return 0, iclass 22, count 0 2006.173.02:37:59.33#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.02:37:59.33#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.02:37:59.33#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.02:37:59.33#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.02:37:59.33$vck44/vblo=5,709.99 2006.173.02:37:59.33#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.02:37:59.33#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.02:37:59.33#ibcon#ireg 17 cls_cnt 0 2006.173.02:37:59.33#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.02:37:59.33#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.02:37:59.33#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.02:37:59.33#ibcon#enter wrdev, iclass 24, count 0 2006.173.02:37:59.33#ibcon#first serial, iclass 24, count 0 2006.173.02:37:59.33#ibcon#enter sib2, iclass 24, count 0 2006.173.02:37:59.33#ibcon#flushed, iclass 24, count 0 2006.173.02:37:59.33#ibcon#about to write, iclass 24, count 0 2006.173.02:37:59.33#ibcon#wrote, iclass 24, count 0 2006.173.02:37:59.33#ibcon#about to read 3, iclass 24, count 0 2006.173.02:37:59.35#ibcon#read 3, iclass 24, count 0 2006.173.02:37:59.35#ibcon#about to read 4, iclass 24, count 0 2006.173.02:37:59.35#ibcon#read 4, iclass 24, count 0 2006.173.02:37:59.35#ibcon#about to read 5, iclass 24, count 0 2006.173.02:37:59.35#ibcon#read 5, iclass 24, count 0 2006.173.02:37:59.35#ibcon#about to read 6, iclass 24, count 0 2006.173.02:37:59.35#ibcon#read 6, iclass 24, count 0 2006.173.02:37:59.35#ibcon#end of sib2, iclass 24, count 0 2006.173.02:37:59.35#ibcon#*mode == 0, iclass 24, count 0 2006.173.02:37:59.35#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.02:37:59.35#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.02:37:59.35#ibcon#*before write, iclass 24, count 0 2006.173.02:37:59.35#ibcon#enter sib2, iclass 24, count 0 2006.173.02:37:59.35#ibcon#flushed, iclass 24, count 0 2006.173.02:37:59.35#ibcon#about to write, iclass 24, count 0 2006.173.02:37:59.35#ibcon#wrote, iclass 24, count 0 2006.173.02:37:59.35#ibcon#about to read 3, iclass 24, count 0 2006.173.02:37:59.39#ibcon#read 3, iclass 24, count 0 2006.173.02:37:59.39#ibcon#about to read 4, iclass 24, count 0 2006.173.02:37:59.39#ibcon#read 4, iclass 24, count 0 2006.173.02:37:59.39#ibcon#about to read 5, iclass 24, count 0 2006.173.02:37:59.39#ibcon#read 5, iclass 24, count 0 2006.173.02:37:59.39#ibcon#about to read 6, iclass 24, count 0 2006.173.02:37:59.39#ibcon#read 6, iclass 24, count 0 2006.173.02:37:59.39#ibcon#end of sib2, iclass 24, count 0 2006.173.02:37:59.39#ibcon#*after write, iclass 24, count 0 2006.173.02:37:59.39#ibcon#*before return 0, iclass 24, count 0 2006.173.02:37:59.39#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.02:37:59.39#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.02:37:59.39#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.02:37:59.39#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.02:37:59.39$vck44/vb=5,4 2006.173.02:37:59.39#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.02:37:59.39#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.02:37:59.39#ibcon#ireg 11 cls_cnt 2 2006.173.02:37:59.39#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.02:37:59.45#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.02:37:59.45#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.02:37:59.45#ibcon#enter wrdev, iclass 26, count 2 2006.173.02:37:59.45#ibcon#first serial, iclass 26, count 2 2006.173.02:37:59.45#ibcon#enter sib2, iclass 26, count 2 2006.173.02:37:59.45#ibcon#flushed, iclass 26, count 2 2006.173.02:37:59.45#ibcon#about to write, iclass 26, count 2 2006.173.02:37:59.45#ibcon#wrote, iclass 26, count 2 2006.173.02:37:59.45#ibcon#about to read 3, iclass 26, count 2 2006.173.02:37:59.47#ibcon#read 3, iclass 26, count 2 2006.173.02:37:59.47#ibcon#about to read 4, iclass 26, count 2 2006.173.02:37:59.47#ibcon#read 4, iclass 26, count 2 2006.173.02:37:59.47#ibcon#about to read 5, iclass 26, count 2 2006.173.02:37:59.47#ibcon#read 5, iclass 26, count 2 2006.173.02:37:59.47#ibcon#about to read 6, iclass 26, count 2 2006.173.02:37:59.47#ibcon#read 6, iclass 26, count 2 2006.173.02:37:59.47#ibcon#end of sib2, iclass 26, count 2 2006.173.02:37:59.47#ibcon#*mode == 0, iclass 26, count 2 2006.173.02:37:59.47#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.02:37:59.47#ibcon#[27=AT05-04\r\n] 2006.173.02:37:59.47#ibcon#*before write, iclass 26, count 2 2006.173.02:37:59.47#ibcon#enter sib2, iclass 26, count 2 2006.173.02:37:59.47#ibcon#flushed, iclass 26, count 2 2006.173.02:37:59.47#ibcon#about to write, iclass 26, count 2 2006.173.02:37:59.47#ibcon#wrote, iclass 26, count 2 2006.173.02:37:59.47#ibcon#about to read 3, iclass 26, count 2 2006.173.02:37:59.50#ibcon#read 3, iclass 26, count 2 2006.173.02:37:59.50#ibcon#about to read 4, iclass 26, count 2 2006.173.02:37:59.50#ibcon#read 4, iclass 26, count 2 2006.173.02:37:59.50#ibcon#about to read 5, iclass 26, count 2 2006.173.02:37:59.50#ibcon#read 5, iclass 26, count 2 2006.173.02:37:59.50#ibcon#about to read 6, iclass 26, count 2 2006.173.02:37:59.50#ibcon#read 6, iclass 26, count 2 2006.173.02:37:59.50#ibcon#end of sib2, iclass 26, count 2 2006.173.02:37:59.50#ibcon#*after write, iclass 26, count 2 2006.173.02:37:59.50#ibcon#*before return 0, iclass 26, count 2 2006.173.02:37:59.50#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.02:37:59.50#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.02:37:59.50#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.02:37:59.50#ibcon#ireg 7 cls_cnt 0 2006.173.02:37:59.50#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.02:37:59.62#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.02:37:59.62#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.02:37:59.62#ibcon#enter wrdev, iclass 26, count 0 2006.173.02:37:59.62#ibcon#first serial, iclass 26, count 0 2006.173.02:37:59.62#ibcon#enter sib2, iclass 26, count 0 2006.173.02:37:59.62#ibcon#flushed, iclass 26, count 0 2006.173.02:37:59.62#ibcon#about to write, iclass 26, count 0 2006.173.02:37:59.62#ibcon#wrote, iclass 26, count 0 2006.173.02:37:59.62#ibcon#about to read 3, iclass 26, count 0 2006.173.02:37:59.64#ibcon#read 3, iclass 26, count 0 2006.173.02:37:59.64#ibcon#about to read 4, iclass 26, count 0 2006.173.02:37:59.64#ibcon#read 4, iclass 26, count 0 2006.173.02:37:59.64#ibcon#about to read 5, iclass 26, count 0 2006.173.02:37:59.64#ibcon#read 5, iclass 26, count 0 2006.173.02:37:59.64#ibcon#about to read 6, iclass 26, count 0 2006.173.02:37:59.64#ibcon#read 6, iclass 26, count 0 2006.173.02:37:59.64#ibcon#end of sib2, iclass 26, count 0 2006.173.02:37:59.64#ibcon#*mode == 0, iclass 26, count 0 2006.173.02:37:59.64#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.02:37:59.64#ibcon#[27=USB\r\n] 2006.173.02:37:59.64#ibcon#*before write, iclass 26, count 0 2006.173.02:37:59.64#ibcon#enter sib2, iclass 26, count 0 2006.173.02:37:59.64#ibcon#flushed, iclass 26, count 0 2006.173.02:37:59.64#ibcon#about to write, iclass 26, count 0 2006.173.02:37:59.64#ibcon#wrote, iclass 26, count 0 2006.173.02:37:59.64#ibcon#about to read 3, iclass 26, count 0 2006.173.02:37:59.67#ibcon#read 3, iclass 26, count 0 2006.173.02:37:59.67#ibcon#about to read 4, iclass 26, count 0 2006.173.02:37:59.67#ibcon#read 4, iclass 26, count 0 2006.173.02:37:59.67#ibcon#about to read 5, iclass 26, count 0 2006.173.02:37:59.67#ibcon#read 5, iclass 26, count 0 2006.173.02:37:59.67#ibcon#about to read 6, iclass 26, count 0 2006.173.02:37:59.67#ibcon#read 6, iclass 26, count 0 2006.173.02:37:59.67#ibcon#end of sib2, iclass 26, count 0 2006.173.02:37:59.67#ibcon#*after write, iclass 26, count 0 2006.173.02:37:59.67#ibcon#*before return 0, iclass 26, count 0 2006.173.02:37:59.67#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.02:37:59.67#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.02:37:59.67#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.02:37:59.67#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.02:37:59.67$vck44/vblo=6,719.99 2006.173.02:37:59.67#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.02:37:59.67#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.02:37:59.67#ibcon#ireg 17 cls_cnt 0 2006.173.02:37:59.67#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.02:37:59.67#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.02:37:59.67#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.02:37:59.67#ibcon#enter wrdev, iclass 28, count 0 2006.173.02:37:59.67#ibcon#first serial, iclass 28, count 0 2006.173.02:37:59.67#ibcon#enter sib2, iclass 28, count 0 2006.173.02:37:59.67#ibcon#flushed, iclass 28, count 0 2006.173.02:37:59.67#ibcon#about to write, iclass 28, count 0 2006.173.02:37:59.67#ibcon#wrote, iclass 28, count 0 2006.173.02:37:59.67#ibcon#about to read 3, iclass 28, count 0 2006.173.02:37:59.69#ibcon#read 3, iclass 28, count 0 2006.173.02:37:59.69#ibcon#about to read 4, iclass 28, count 0 2006.173.02:37:59.69#ibcon#read 4, iclass 28, count 0 2006.173.02:37:59.69#ibcon#about to read 5, iclass 28, count 0 2006.173.02:37:59.69#ibcon#read 5, iclass 28, count 0 2006.173.02:37:59.69#ibcon#about to read 6, iclass 28, count 0 2006.173.02:37:59.69#ibcon#read 6, iclass 28, count 0 2006.173.02:37:59.69#ibcon#end of sib2, iclass 28, count 0 2006.173.02:37:59.69#ibcon#*mode == 0, iclass 28, count 0 2006.173.02:37:59.69#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.02:37:59.69#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.02:37:59.69#ibcon#*before write, iclass 28, count 0 2006.173.02:37:59.69#ibcon#enter sib2, iclass 28, count 0 2006.173.02:37:59.69#ibcon#flushed, iclass 28, count 0 2006.173.02:37:59.69#ibcon#about to write, iclass 28, count 0 2006.173.02:37:59.69#ibcon#wrote, iclass 28, count 0 2006.173.02:37:59.69#ibcon#about to read 3, iclass 28, count 0 2006.173.02:37:59.73#ibcon#read 3, iclass 28, count 0 2006.173.02:37:59.73#ibcon#about to read 4, iclass 28, count 0 2006.173.02:37:59.73#ibcon#read 4, iclass 28, count 0 2006.173.02:37:59.73#ibcon#about to read 5, iclass 28, count 0 2006.173.02:37:59.73#ibcon#read 5, iclass 28, count 0 2006.173.02:37:59.73#ibcon#about to read 6, iclass 28, count 0 2006.173.02:37:59.73#ibcon#read 6, iclass 28, count 0 2006.173.02:37:59.73#ibcon#end of sib2, iclass 28, count 0 2006.173.02:37:59.73#ibcon#*after write, iclass 28, count 0 2006.173.02:37:59.73#ibcon#*before return 0, iclass 28, count 0 2006.173.02:37:59.73#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.02:37:59.73#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.02:37:59.73#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.02:37:59.73#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.02:37:59.73$vck44/vb=6,4 2006.173.02:37:59.73#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.02:37:59.73#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.02:37:59.73#ibcon#ireg 11 cls_cnt 2 2006.173.02:37:59.73#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.02:37:59.79#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.02:37:59.79#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.02:37:59.79#ibcon#enter wrdev, iclass 30, count 2 2006.173.02:37:59.79#ibcon#first serial, iclass 30, count 2 2006.173.02:37:59.79#ibcon#enter sib2, iclass 30, count 2 2006.173.02:37:59.79#ibcon#flushed, iclass 30, count 2 2006.173.02:37:59.79#ibcon#about to write, iclass 30, count 2 2006.173.02:37:59.79#ibcon#wrote, iclass 30, count 2 2006.173.02:37:59.79#ibcon#about to read 3, iclass 30, count 2 2006.173.02:37:59.81#ibcon#read 3, iclass 30, count 2 2006.173.02:37:59.81#ibcon#about to read 4, iclass 30, count 2 2006.173.02:37:59.81#ibcon#read 4, iclass 30, count 2 2006.173.02:37:59.81#ibcon#about to read 5, iclass 30, count 2 2006.173.02:37:59.81#ibcon#read 5, iclass 30, count 2 2006.173.02:37:59.81#ibcon#about to read 6, iclass 30, count 2 2006.173.02:37:59.81#ibcon#read 6, iclass 30, count 2 2006.173.02:37:59.81#ibcon#end of sib2, iclass 30, count 2 2006.173.02:37:59.81#ibcon#*mode == 0, iclass 30, count 2 2006.173.02:37:59.81#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.02:37:59.81#ibcon#[27=AT06-04\r\n] 2006.173.02:37:59.81#ibcon#*before write, iclass 30, count 2 2006.173.02:37:59.81#ibcon#enter sib2, iclass 30, count 2 2006.173.02:37:59.81#ibcon#flushed, iclass 30, count 2 2006.173.02:37:59.81#ibcon#about to write, iclass 30, count 2 2006.173.02:37:59.81#ibcon#wrote, iclass 30, count 2 2006.173.02:37:59.81#ibcon#about to read 3, iclass 30, count 2 2006.173.02:37:59.84#ibcon#read 3, iclass 30, count 2 2006.173.02:37:59.84#ibcon#about to read 4, iclass 30, count 2 2006.173.02:37:59.84#ibcon#read 4, iclass 30, count 2 2006.173.02:37:59.84#ibcon#about to read 5, iclass 30, count 2 2006.173.02:37:59.84#ibcon#read 5, iclass 30, count 2 2006.173.02:37:59.84#ibcon#about to read 6, iclass 30, count 2 2006.173.02:37:59.84#ibcon#read 6, iclass 30, count 2 2006.173.02:37:59.84#ibcon#end of sib2, iclass 30, count 2 2006.173.02:37:59.84#ibcon#*after write, iclass 30, count 2 2006.173.02:37:59.84#ibcon#*before return 0, iclass 30, count 2 2006.173.02:37:59.84#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.02:37:59.84#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.02:37:59.84#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.02:37:59.84#ibcon#ireg 7 cls_cnt 0 2006.173.02:37:59.84#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.02:37:59.96#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.02:37:59.96#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.02:37:59.96#ibcon#enter wrdev, iclass 30, count 0 2006.173.02:37:59.96#ibcon#first serial, iclass 30, count 0 2006.173.02:37:59.96#ibcon#enter sib2, iclass 30, count 0 2006.173.02:37:59.96#ibcon#flushed, iclass 30, count 0 2006.173.02:37:59.96#ibcon#about to write, iclass 30, count 0 2006.173.02:37:59.96#ibcon#wrote, iclass 30, count 0 2006.173.02:37:59.96#ibcon#about to read 3, iclass 30, count 0 2006.173.02:37:59.98#ibcon#read 3, iclass 30, count 0 2006.173.02:37:59.98#ibcon#about to read 4, iclass 30, count 0 2006.173.02:37:59.98#ibcon#read 4, iclass 30, count 0 2006.173.02:37:59.98#ibcon#about to read 5, iclass 30, count 0 2006.173.02:37:59.98#ibcon#read 5, iclass 30, count 0 2006.173.02:37:59.98#ibcon#about to read 6, iclass 30, count 0 2006.173.02:37:59.98#ibcon#read 6, iclass 30, count 0 2006.173.02:37:59.98#ibcon#end of sib2, iclass 30, count 0 2006.173.02:37:59.98#ibcon#*mode == 0, iclass 30, count 0 2006.173.02:37:59.98#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.02:37:59.98#ibcon#[27=USB\r\n] 2006.173.02:37:59.98#ibcon#*before write, iclass 30, count 0 2006.173.02:37:59.98#ibcon#enter sib2, iclass 30, count 0 2006.173.02:37:59.98#ibcon#flushed, iclass 30, count 0 2006.173.02:37:59.98#ibcon#about to write, iclass 30, count 0 2006.173.02:37:59.98#ibcon#wrote, iclass 30, count 0 2006.173.02:37:59.98#ibcon#about to read 3, iclass 30, count 0 2006.173.02:38:00.01#ibcon#read 3, iclass 30, count 0 2006.173.02:38:00.01#ibcon#about to read 4, iclass 30, count 0 2006.173.02:38:00.01#ibcon#read 4, iclass 30, count 0 2006.173.02:38:00.01#ibcon#about to read 5, iclass 30, count 0 2006.173.02:38:00.01#ibcon#read 5, iclass 30, count 0 2006.173.02:38:00.01#ibcon#about to read 6, iclass 30, count 0 2006.173.02:38:00.01#ibcon#read 6, iclass 30, count 0 2006.173.02:38:00.01#ibcon#end of sib2, iclass 30, count 0 2006.173.02:38:00.01#ibcon#*after write, iclass 30, count 0 2006.173.02:38:00.01#ibcon#*before return 0, iclass 30, count 0 2006.173.02:38:00.01#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.02:38:00.01#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.02:38:00.01#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.02:38:00.01#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.02:38:00.01$vck44/vblo=7,734.99 2006.173.02:38:00.01#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.02:38:00.01#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.02:38:00.01#ibcon#ireg 17 cls_cnt 0 2006.173.02:38:00.01#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.02:38:00.01#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.02:38:00.01#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.02:38:00.01#ibcon#enter wrdev, iclass 32, count 0 2006.173.02:38:00.01#ibcon#first serial, iclass 32, count 0 2006.173.02:38:00.01#ibcon#enter sib2, iclass 32, count 0 2006.173.02:38:00.01#ibcon#flushed, iclass 32, count 0 2006.173.02:38:00.01#ibcon#about to write, iclass 32, count 0 2006.173.02:38:00.01#ibcon#wrote, iclass 32, count 0 2006.173.02:38:00.01#ibcon#about to read 3, iclass 32, count 0 2006.173.02:38:00.03#ibcon#read 3, iclass 32, count 0 2006.173.02:38:00.03#ibcon#about to read 4, iclass 32, count 0 2006.173.02:38:00.03#ibcon#read 4, iclass 32, count 0 2006.173.02:38:00.03#ibcon#about to read 5, iclass 32, count 0 2006.173.02:38:00.03#ibcon#read 5, iclass 32, count 0 2006.173.02:38:00.03#ibcon#about to read 6, iclass 32, count 0 2006.173.02:38:00.03#ibcon#read 6, iclass 32, count 0 2006.173.02:38:00.03#ibcon#end of sib2, iclass 32, count 0 2006.173.02:38:00.03#ibcon#*mode == 0, iclass 32, count 0 2006.173.02:38:00.03#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.02:38:00.03#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.02:38:00.03#ibcon#*before write, iclass 32, count 0 2006.173.02:38:00.03#ibcon#enter sib2, iclass 32, count 0 2006.173.02:38:00.03#ibcon#flushed, iclass 32, count 0 2006.173.02:38:00.03#ibcon#about to write, iclass 32, count 0 2006.173.02:38:00.03#ibcon#wrote, iclass 32, count 0 2006.173.02:38:00.03#ibcon#about to read 3, iclass 32, count 0 2006.173.02:38:00.07#ibcon#read 3, iclass 32, count 0 2006.173.02:38:00.07#ibcon#about to read 4, iclass 32, count 0 2006.173.02:38:00.07#ibcon#read 4, iclass 32, count 0 2006.173.02:38:00.07#ibcon#about to read 5, iclass 32, count 0 2006.173.02:38:00.07#ibcon#read 5, iclass 32, count 0 2006.173.02:38:00.07#ibcon#about to read 6, iclass 32, count 0 2006.173.02:38:00.07#ibcon#read 6, iclass 32, count 0 2006.173.02:38:00.07#ibcon#end of sib2, iclass 32, count 0 2006.173.02:38:00.07#ibcon#*after write, iclass 32, count 0 2006.173.02:38:00.07#ibcon#*before return 0, iclass 32, count 0 2006.173.02:38:00.07#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.02:38:00.07#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.02:38:00.07#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.02:38:00.07#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.02:38:00.07$vck44/vb=7,4 2006.173.02:38:00.07#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.02:38:00.07#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.02:38:00.07#ibcon#ireg 11 cls_cnt 2 2006.173.02:38:00.07#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.02:38:00.13#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.02:38:00.13#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.02:38:00.13#ibcon#enter wrdev, iclass 34, count 2 2006.173.02:38:00.13#ibcon#first serial, iclass 34, count 2 2006.173.02:38:00.13#ibcon#enter sib2, iclass 34, count 2 2006.173.02:38:00.13#ibcon#flushed, iclass 34, count 2 2006.173.02:38:00.13#ibcon#about to write, iclass 34, count 2 2006.173.02:38:00.13#ibcon#wrote, iclass 34, count 2 2006.173.02:38:00.13#ibcon#about to read 3, iclass 34, count 2 2006.173.02:38:00.15#ibcon#read 3, iclass 34, count 2 2006.173.02:38:00.15#ibcon#about to read 4, iclass 34, count 2 2006.173.02:38:00.15#ibcon#read 4, iclass 34, count 2 2006.173.02:38:00.15#ibcon#about to read 5, iclass 34, count 2 2006.173.02:38:00.15#ibcon#read 5, iclass 34, count 2 2006.173.02:38:00.15#ibcon#about to read 6, iclass 34, count 2 2006.173.02:38:00.15#ibcon#read 6, iclass 34, count 2 2006.173.02:38:00.15#ibcon#end of sib2, iclass 34, count 2 2006.173.02:38:00.15#ibcon#*mode == 0, iclass 34, count 2 2006.173.02:38:00.15#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.02:38:00.15#ibcon#[27=AT07-04\r\n] 2006.173.02:38:00.15#ibcon#*before write, iclass 34, count 2 2006.173.02:38:00.15#ibcon#enter sib2, iclass 34, count 2 2006.173.02:38:00.15#ibcon#flushed, iclass 34, count 2 2006.173.02:38:00.15#ibcon#about to write, iclass 34, count 2 2006.173.02:38:00.15#ibcon#wrote, iclass 34, count 2 2006.173.02:38:00.15#ibcon#about to read 3, iclass 34, count 2 2006.173.02:38:00.18#ibcon#read 3, iclass 34, count 2 2006.173.02:38:00.18#ibcon#about to read 4, iclass 34, count 2 2006.173.02:38:00.18#ibcon#read 4, iclass 34, count 2 2006.173.02:38:00.18#ibcon#about to read 5, iclass 34, count 2 2006.173.02:38:00.18#ibcon#read 5, iclass 34, count 2 2006.173.02:38:00.18#ibcon#about to read 6, iclass 34, count 2 2006.173.02:38:00.18#ibcon#read 6, iclass 34, count 2 2006.173.02:38:00.18#ibcon#end of sib2, iclass 34, count 2 2006.173.02:38:00.18#ibcon#*after write, iclass 34, count 2 2006.173.02:38:00.18#ibcon#*before return 0, iclass 34, count 2 2006.173.02:38:00.18#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.02:38:00.18#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.02:38:00.18#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.02:38:00.18#ibcon#ireg 7 cls_cnt 0 2006.173.02:38:00.18#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.02:38:00.30#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.02:38:00.30#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.02:38:00.30#ibcon#enter wrdev, iclass 34, count 0 2006.173.02:38:00.30#ibcon#first serial, iclass 34, count 0 2006.173.02:38:00.30#ibcon#enter sib2, iclass 34, count 0 2006.173.02:38:00.30#ibcon#flushed, iclass 34, count 0 2006.173.02:38:00.30#ibcon#about to write, iclass 34, count 0 2006.173.02:38:00.30#ibcon#wrote, iclass 34, count 0 2006.173.02:38:00.30#ibcon#about to read 3, iclass 34, count 0 2006.173.02:38:00.32#ibcon#read 3, iclass 34, count 0 2006.173.02:38:00.32#ibcon#about to read 4, iclass 34, count 0 2006.173.02:38:00.32#ibcon#read 4, iclass 34, count 0 2006.173.02:38:00.32#ibcon#about to read 5, iclass 34, count 0 2006.173.02:38:00.32#ibcon#read 5, iclass 34, count 0 2006.173.02:38:00.32#ibcon#about to read 6, iclass 34, count 0 2006.173.02:38:00.32#ibcon#read 6, iclass 34, count 0 2006.173.02:38:00.32#ibcon#end of sib2, iclass 34, count 0 2006.173.02:38:00.32#ibcon#*mode == 0, iclass 34, count 0 2006.173.02:38:00.32#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.02:38:00.32#ibcon#[27=USB\r\n] 2006.173.02:38:00.32#ibcon#*before write, iclass 34, count 0 2006.173.02:38:00.32#ibcon#enter sib2, iclass 34, count 0 2006.173.02:38:00.32#ibcon#flushed, iclass 34, count 0 2006.173.02:38:00.32#ibcon#about to write, iclass 34, count 0 2006.173.02:38:00.32#ibcon#wrote, iclass 34, count 0 2006.173.02:38:00.32#ibcon#about to read 3, iclass 34, count 0 2006.173.02:38:00.35#ibcon#read 3, iclass 34, count 0 2006.173.02:38:00.35#ibcon#about to read 4, iclass 34, count 0 2006.173.02:38:00.35#ibcon#read 4, iclass 34, count 0 2006.173.02:38:00.35#ibcon#about to read 5, iclass 34, count 0 2006.173.02:38:00.35#ibcon#read 5, iclass 34, count 0 2006.173.02:38:00.35#ibcon#about to read 6, iclass 34, count 0 2006.173.02:38:00.35#ibcon#read 6, iclass 34, count 0 2006.173.02:38:00.35#ibcon#end of sib2, iclass 34, count 0 2006.173.02:38:00.35#ibcon#*after write, iclass 34, count 0 2006.173.02:38:00.35#ibcon#*before return 0, iclass 34, count 0 2006.173.02:38:00.35#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.02:38:00.35#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.02:38:00.35#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.02:38:00.35#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.02:38:00.35$vck44/vblo=8,744.99 2006.173.02:38:00.35#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.02:38:00.35#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.02:38:00.35#ibcon#ireg 17 cls_cnt 0 2006.173.02:38:00.35#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.02:38:00.35#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.02:38:00.35#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.02:38:00.35#ibcon#enter wrdev, iclass 36, count 0 2006.173.02:38:00.35#ibcon#first serial, iclass 36, count 0 2006.173.02:38:00.35#ibcon#enter sib2, iclass 36, count 0 2006.173.02:38:00.35#ibcon#flushed, iclass 36, count 0 2006.173.02:38:00.35#ibcon#about to write, iclass 36, count 0 2006.173.02:38:00.35#ibcon#wrote, iclass 36, count 0 2006.173.02:38:00.35#ibcon#about to read 3, iclass 36, count 0 2006.173.02:38:00.37#ibcon#read 3, iclass 36, count 0 2006.173.02:38:00.37#ibcon#about to read 4, iclass 36, count 0 2006.173.02:38:00.37#ibcon#read 4, iclass 36, count 0 2006.173.02:38:00.37#ibcon#about to read 5, iclass 36, count 0 2006.173.02:38:00.37#ibcon#read 5, iclass 36, count 0 2006.173.02:38:00.37#ibcon#about to read 6, iclass 36, count 0 2006.173.02:38:00.37#ibcon#read 6, iclass 36, count 0 2006.173.02:38:00.37#ibcon#end of sib2, iclass 36, count 0 2006.173.02:38:00.37#ibcon#*mode == 0, iclass 36, count 0 2006.173.02:38:00.37#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.02:38:00.37#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.02:38:00.37#ibcon#*before write, iclass 36, count 0 2006.173.02:38:00.37#ibcon#enter sib2, iclass 36, count 0 2006.173.02:38:00.37#ibcon#flushed, iclass 36, count 0 2006.173.02:38:00.37#ibcon#about to write, iclass 36, count 0 2006.173.02:38:00.37#ibcon#wrote, iclass 36, count 0 2006.173.02:38:00.37#ibcon#about to read 3, iclass 36, count 0 2006.173.02:38:00.41#ibcon#read 3, iclass 36, count 0 2006.173.02:38:00.41#ibcon#about to read 4, iclass 36, count 0 2006.173.02:38:00.41#ibcon#read 4, iclass 36, count 0 2006.173.02:38:00.41#ibcon#about to read 5, iclass 36, count 0 2006.173.02:38:00.41#ibcon#read 5, iclass 36, count 0 2006.173.02:38:00.41#ibcon#about to read 6, iclass 36, count 0 2006.173.02:38:00.41#ibcon#read 6, iclass 36, count 0 2006.173.02:38:00.41#ibcon#end of sib2, iclass 36, count 0 2006.173.02:38:00.41#ibcon#*after write, iclass 36, count 0 2006.173.02:38:00.41#ibcon#*before return 0, iclass 36, count 0 2006.173.02:38:00.41#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.02:38:00.41#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.02:38:00.41#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.02:38:00.41#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.02:38:00.41$vck44/vb=8,4 2006.173.02:38:00.41#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.02:38:00.41#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.02:38:00.41#ibcon#ireg 11 cls_cnt 2 2006.173.02:38:00.41#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.02:38:00.47#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.02:38:00.47#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.02:38:00.47#ibcon#enter wrdev, iclass 38, count 2 2006.173.02:38:00.47#ibcon#first serial, iclass 38, count 2 2006.173.02:38:00.47#ibcon#enter sib2, iclass 38, count 2 2006.173.02:38:00.47#ibcon#flushed, iclass 38, count 2 2006.173.02:38:00.47#ibcon#about to write, iclass 38, count 2 2006.173.02:38:00.47#ibcon#wrote, iclass 38, count 2 2006.173.02:38:00.47#ibcon#about to read 3, iclass 38, count 2 2006.173.02:38:00.49#ibcon#read 3, iclass 38, count 2 2006.173.02:38:00.49#ibcon#about to read 4, iclass 38, count 2 2006.173.02:38:00.49#ibcon#read 4, iclass 38, count 2 2006.173.02:38:00.49#ibcon#about to read 5, iclass 38, count 2 2006.173.02:38:00.49#ibcon#read 5, iclass 38, count 2 2006.173.02:38:00.49#ibcon#about to read 6, iclass 38, count 2 2006.173.02:38:00.49#ibcon#read 6, iclass 38, count 2 2006.173.02:38:00.49#ibcon#end of sib2, iclass 38, count 2 2006.173.02:38:00.49#ibcon#*mode == 0, iclass 38, count 2 2006.173.02:38:00.49#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.02:38:00.49#ibcon#[27=AT08-04\r\n] 2006.173.02:38:00.49#ibcon#*before write, iclass 38, count 2 2006.173.02:38:00.49#ibcon#enter sib2, iclass 38, count 2 2006.173.02:38:00.49#ibcon#flushed, iclass 38, count 2 2006.173.02:38:00.49#ibcon#about to write, iclass 38, count 2 2006.173.02:38:00.49#ibcon#wrote, iclass 38, count 2 2006.173.02:38:00.49#ibcon#about to read 3, iclass 38, count 2 2006.173.02:38:00.52#ibcon#read 3, iclass 38, count 2 2006.173.02:38:00.52#ibcon#about to read 4, iclass 38, count 2 2006.173.02:38:00.52#ibcon#read 4, iclass 38, count 2 2006.173.02:38:00.52#ibcon#about to read 5, iclass 38, count 2 2006.173.02:38:00.52#ibcon#read 5, iclass 38, count 2 2006.173.02:38:00.52#ibcon#about to read 6, iclass 38, count 2 2006.173.02:38:00.52#ibcon#read 6, iclass 38, count 2 2006.173.02:38:00.52#ibcon#end of sib2, iclass 38, count 2 2006.173.02:38:00.52#ibcon#*after write, iclass 38, count 2 2006.173.02:38:00.52#ibcon#*before return 0, iclass 38, count 2 2006.173.02:38:00.52#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.02:38:00.52#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.02:38:00.52#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.02:38:00.52#ibcon#ireg 7 cls_cnt 0 2006.173.02:38:00.52#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.02:38:00.64#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.02:38:00.64#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.02:38:00.64#ibcon#enter wrdev, iclass 38, count 0 2006.173.02:38:00.64#ibcon#first serial, iclass 38, count 0 2006.173.02:38:00.64#ibcon#enter sib2, iclass 38, count 0 2006.173.02:38:00.64#ibcon#flushed, iclass 38, count 0 2006.173.02:38:00.64#ibcon#about to write, iclass 38, count 0 2006.173.02:38:00.64#ibcon#wrote, iclass 38, count 0 2006.173.02:38:00.64#ibcon#about to read 3, iclass 38, count 0 2006.173.02:38:00.66#ibcon#read 3, iclass 38, count 0 2006.173.02:38:00.66#ibcon#about to read 4, iclass 38, count 0 2006.173.02:38:00.66#ibcon#read 4, iclass 38, count 0 2006.173.02:38:00.66#ibcon#about to read 5, iclass 38, count 0 2006.173.02:38:00.66#ibcon#read 5, iclass 38, count 0 2006.173.02:38:00.66#ibcon#about to read 6, iclass 38, count 0 2006.173.02:38:00.66#ibcon#read 6, iclass 38, count 0 2006.173.02:38:00.66#ibcon#end of sib2, iclass 38, count 0 2006.173.02:38:00.66#ibcon#*mode == 0, iclass 38, count 0 2006.173.02:38:00.66#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.02:38:00.66#ibcon#[27=USB\r\n] 2006.173.02:38:00.66#ibcon#*before write, iclass 38, count 0 2006.173.02:38:00.66#ibcon#enter sib2, iclass 38, count 0 2006.173.02:38:00.66#ibcon#flushed, iclass 38, count 0 2006.173.02:38:00.66#ibcon#about to write, iclass 38, count 0 2006.173.02:38:00.66#ibcon#wrote, iclass 38, count 0 2006.173.02:38:00.66#ibcon#about to read 3, iclass 38, count 0 2006.173.02:38:00.69#ibcon#read 3, iclass 38, count 0 2006.173.02:38:00.69#ibcon#about to read 4, iclass 38, count 0 2006.173.02:38:00.69#ibcon#read 4, iclass 38, count 0 2006.173.02:38:00.69#ibcon#about to read 5, iclass 38, count 0 2006.173.02:38:00.69#ibcon#read 5, iclass 38, count 0 2006.173.02:38:00.69#ibcon#about to read 6, iclass 38, count 0 2006.173.02:38:00.69#ibcon#read 6, iclass 38, count 0 2006.173.02:38:00.69#ibcon#end of sib2, iclass 38, count 0 2006.173.02:38:00.69#ibcon#*after write, iclass 38, count 0 2006.173.02:38:00.69#ibcon#*before return 0, iclass 38, count 0 2006.173.02:38:00.69#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.02:38:00.69#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.02:38:00.69#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.02:38:00.69#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.02:38:00.69$vck44/vabw=wide 2006.173.02:38:00.69#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.02:38:00.69#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.02:38:00.69#ibcon#ireg 8 cls_cnt 0 2006.173.02:38:00.69#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.02:38:00.69#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.02:38:00.69#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.02:38:00.69#ibcon#enter wrdev, iclass 40, count 0 2006.173.02:38:00.69#ibcon#first serial, iclass 40, count 0 2006.173.02:38:00.69#ibcon#enter sib2, iclass 40, count 0 2006.173.02:38:00.69#ibcon#flushed, iclass 40, count 0 2006.173.02:38:00.69#ibcon#about to write, iclass 40, count 0 2006.173.02:38:00.69#ibcon#wrote, iclass 40, count 0 2006.173.02:38:00.69#ibcon#about to read 3, iclass 40, count 0 2006.173.02:38:00.71#ibcon#read 3, iclass 40, count 0 2006.173.02:38:00.71#ibcon#about to read 4, iclass 40, count 0 2006.173.02:38:00.71#ibcon#read 4, iclass 40, count 0 2006.173.02:38:00.71#ibcon#about to read 5, iclass 40, count 0 2006.173.02:38:00.71#ibcon#read 5, iclass 40, count 0 2006.173.02:38:00.71#ibcon#about to read 6, iclass 40, count 0 2006.173.02:38:00.71#ibcon#read 6, iclass 40, count 0 2006.173.02:38:00.71#ibcon#end of sib2, iclass 40, count 0 2006.173.02:38:00.71#ibcon#*mode == 0, iclass 40, count 0 2006.173.02:38:00.71#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.02:38:00.71#ibcon#[25=BW32\r\n] 2006.173.02:38:00.71#ibcon#*before write, iclass 40, count 0 2006.173.02:38:00.71#ibcon#enter sib2, iclass 40, count 0 2006.173.02:38:00.71#ibcon#flushed, iclass 40, count 0 2006.173.02:38:00.71#ibcon#about to write, iclass 40, count 0 2006.173.02:38:00.71#ibcon#wrote, iclass 40, count 0 2006.173.02:38:00.71#ibcon#about to read 3, iclass 40, count 0 2006.173.02:38:00.74#ibcon#read 3, iclass 40, count 0 2006.173.02:38:00.74#ibcon#about to read 4, iclass 40, count 0 2006.173.02:38:00.74#ibcon#read 4, iclass 40, count 0 2006.173.02:38:00.74#ibcon#about to read 5, iclass 40, count 0 2006.173.02:38:00.74#ibcon#read 5, iclass 40, count 0 2006.173.02:38:00.74#ibcon#about to read 6, iclass 40, count 0 2006.173.02:38:00.74#ibcon#read 6, iclass 40, count 0 2006.173.02:38:00.74#ibcon#end of sib2, iclass 40, count 0 2006.173.02:38:00.74#ibcon#*after write, iclass 40, count 0 2006.173.02:38:00.74#ibcon#*before return 0, iclass 40, count 0 2006.173.02:38:00.74#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.02:38:00.74#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.02:38:00.74#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.02:38:00.74#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.02:38:00.74$vck44/vbbw=wide 2006.173.02:38:00.74#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.02:38:00.74#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.02:38:00.74#ibcon#ireg 8 cls_cnt 0 2006.173.02:38:00.74#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.02:38:00.81#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.02:38:00.81#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.02:38:00.81#ibcon#enter wrdev, iclass 4, count 0 2006.173.02:38:00.81#ibcon#first serial, iclass 4, count 0 2006.173.02:38:00.81#ibcon#enter sib2, iclass 4, count 0 2006.173.02:38:00.81#ibcon#flushed, iclass 4, count 0 2006.173.02:38:00.81#ibcon#about to write, iclass 4, count 0 2006.173.02:38:00.81#ibcon#wrote, iclass 4, count 0 2006.173.02:38:00.81#ibcon#about to read 3, iclass 4, count 0 2006.173.02:38:00.83#ibcon#read 3, iclass 4, count 0 2006.173.02:38:00.83#ibcon#about to read 4, iclass 4, count 0 2006.173.02:38:00.83#ibcon#read 4, iclass 4, count 0 2006.173.02:38:00.83#ibcon#about to read 5, iclass 4, count 0 2006.173.02:38:00.83#ibcon#read 5, iclass 4, count 0 2006.173.02:38:00.83#ibcon#about to read 6, iclass 4, count 0 2006.173.02:38:00.83#ibcon#read 6, iclass 4, count 0 2006.173.02:38:00.83#ibcon#end of sib2, iclass 4, count 0 2006.173.02:38:00.83#ibcon#*mode == 0, iclass 4, count 0 2006.173.02:38:00.83#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.02:38:00.83#ibcon#[27=BW32\r\n] 2006.173.02:38:00.83#ibcon#*before write, iclass 4, count 0 2006.173.02:38:00.83#ibcon#enter sib2, iclass 4, count 0 2006.173.02:38:00.83#ibcon#flushed, iclass 4, count 0 2006.173.02:38:00.83#ibcon#about to write, iclass 4, count 0 2006.173.02:38:00.83#ibcon#wrote, iclass 4, count 0 2006.173.02:38:00.83#ibcon#about to read 3, iclass 4, count 0 2006.173.02:38:00.86#ibcon#read 3, iclass 4, count 0 2006.173.02:38:00.86#ibcon#about to read 4, iclass 4, count 0 2006.173.02:38:00.86#ibcon#read 4, iclass 4, count 0 2006.173.02:38:00.86#ibcon#about to read 5, iclass 4, count 0 2006.173.02:38:00.86#ibcon#read 5, iclass 4, count 0 2006.173.02:38:00.86#ibcon#about to read 6, iclass 4, count 0 2006.173.02:38:00.86#ibcon#read 6, iclass 4, count 0 2006.173.02:38:00.86#ibcon#end of sib2, iclass 4, count 0 2006.173.02:38:00.86#ibcon#*after write, iclass 4, count 0 2006.173.02:38:00.86#ibcon#*before return 0, iclass 4, count 0 2006.173.02:38:00.86#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.02:38:00.86#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.02:38:00.86#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.02:38:00.86#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.02:38:00.86$setupk4/ifdk4 2006.173.02:38:00.86$ifdk4/lo= 2006.173.02:38:00.86$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.02:38:00.86$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.02:38:00.86$ifdk4/patch= 2006.173.02:38:00.86$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.02:38:00.86$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.02:38:00.86$setupk4/!*+20s 2006.173.02:38:02.74#abcon#<5=/15 1.0 2.3 22.69 821006.5\r\n> 2006.173.02:38:02.76#abcon#{5=INTERFACE CLEAR} 2006.173.02:38:02.83#abcon#[5=S1D000X0/0*\r\n] 2006.173.02:38:12.92#abcon#<5=/15 0.9 2.3 22.69 821006.5\r\n> 2006.173.02:38:12.94#abcon#{5=INTERFACE CLEAR} 2006.173.02:38:13.01#abcon#[5=S1D000X0/0*\r\n] 2006.173.02:38:15.35$setupk4/"tpicd 2006.173.02:38:15.35$setupk4/echo=off 2006.173.02:38:15.35$setupk4/xlog=off 2006.173.02:38:15.35:!2006.173.02:40:35 2006.173.02:38:52.14#trakl#Source acquired 2006.173.02:38:54.14#flagr#flagr/antenna,acquired 2006.173.02:40:35.00:preob 2006.173.02:40:35.14/onsource/TRACKING 2006.173.02:40:35.14:!2006.173.02:40:45 2006.173.02:40:45.00:"tape 2006.173.02:40:45.00:"st=record 2006.173.02:40:45.00:data_valid=on 2006.173.02:40:45.00:midob 2006.173.02:40:45.14/onsource/TRACKING 2006.173.02:40:45.14/wx/22.69,1006.5,82 2006.173.02:40:45.30/cable/+6.5092E-03 2006.173.02:40:46.39/va/01,07,usb,yes,47,51 2006.173.02:40:46.39/va/02,06,usb,yes,47,48 2006.173.02:40:46.39/va/03,05,usb,yes,60,62 2006.173.02:40:46.39/va/04,06,usb,yes,48,51 2006.173.02:40:46.39/va/05,04,usb,yes,38,39 2006.173.02:40:46.39/va/06,03,usb,yes,53,53 2006.173.02:40:46.39/va/07,04,usb,yes,43,45 2006.173.02:40:46.39/va/08,04,usb,yes,37,44 2006.173.02:40:46.62/valo/01,524.99,yes,locked 2006.173.02:40:46.62/valo/02,534.99,yes,locked 2006.173.02:40:46.62/valo/03,564.99,yes,locked 2006.173.02:40:46.62/valo/04,624.99,yes,locked 2006.173.02:40:46.62/valo/05,734.99,yes,locked 2006.173.02:40:46.62/valo/06,814.99,yes,locked 2006.173.02:40:46.62/valo/07,864.99,yes,locked 2006.173.02:40:46.62/valo/08,884.99,yes,locked 2006.173.02:40:47.71/vb/01,04,usb,yes,34,32 2006.173.02:40:47.71/vb/02,04,usb,yes,37,36 2006.173.02:40:47.71/vb/03,04,usb,yes,33,37 2006.173.02:40:47.71/vb/04,04,usb,yes,38,37 2006.173.02:40:47.71/vb/05,04,usb,yes,30,33 2006.173.02:40:47.71/vb/06,04,usb,yes,35,31 2006.173.02:40:47.71/vb/07,04,usb,yes,35,35 2006.173.02:40:47.71/vb/08,04,usb,yes,32,36 2006.173.02:40:47.94/vblo/01,629.99,yes,locked 2006.173.02:40:47.94/vblo/02,634.99,yes,locked 2006.173.02:40:47.94/vblo/03,649.99,yes,locked 2006.173.02:40:47.94/vblo/04,679.99,yes,locked 2006.173.02:40:47.94/vblo/05,709.99,yes,locked 2006.173.02:40:47.94/vblo/06,719.99,yes,locked 2006.173.02:40:47.94/vblo/07,734.99,yes,locked 2006.173.02:40:47.94/vblo/08,744.99,yes,locked 2006.173.02:40:48.09/vabw/8 2006.173.02:40:48.24/vbbw/8 2006.173.02:40:48.33/xfe/off,on,15.0 2006.173.02:40:48.73/ifatt/23,28,28,28 2006.173.02:40:49.07/fmout-gps/S +3.88E-07 2006.173.02:40:49.15:!2006.173.02:51:55 2006.173.02:51:55.00:data_valid=off 2006.173.02:51:55.01:"et 2006.173.02:51:55.01:!+3s 2006.173.02:51:58.03:"tape 2006.173.02:51:58.04:postob 2006.173.02:51:58.20/cable/+6.5118E-03 2006.173.02:51:58.21/wx/22.48,1006.4,84 2006.173.02:51:58.29/fmout-gps/S +3.89E-07 2006.173.02:51:58.29:scan_name=173-0252,jd0606,720 2006.173.02:51:58.30:source=1418+546,141946.60,542314.8,2000.0,ccw 2006.173.02:52:00.13#flagr#flagr/antenna,new-source 2006.173.02:52:00.14:checkk5 2006.173.02:52:00.52/chk_autoobs//k5ts1/ autoobs is running! 2006.173.02:52:00.92/chk_autoobs//k5ts2/ autoobs is running! 2006.173.02:52:01.30/chk_autoobs//k5ts3/ autoobs is running! 2006.173.02:52:01.68/chk_autoobs//k5ts4/ autoobs is running! 2006.173.02:52:02.37/chk_obsdata//k5ts1/T1730240??a.dat file size is correct (nominal:2680MB, actual:2676MB). 2006.173.02:52:03.05/chk_obsdata//k5ts2/T1730240??b.dat file size is correct (nominal:2680MB, actual:2676MB). 2006.173.02:52:03.73/chk_obsdata//k5ts3/T1730240??c.dat file size is correct (nominal:2680MB, actual:2676MB). 2006.173.02:52:04.41/chk_obsdata//k5ts4/T1730240??d.dat file size is correct (nominal:2680MB, actual:2676MB). 2006.173.02:52:05.11/k5log//k5ts1_log_newline 2006.173.02:52:05.80/k5log//k5ts2_log_newline 2006.173.02:52:06.49/k5log//k5ts3_log_newline 2006.173.02:52:07.19/k5log//k5ts4_log_newline 2006.173.02:52:07.25/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.02:52:07.25:setupk4=1 2006.173.02:52:07.25$setupk4/echo=on 2006.173.02:52:07.25$setupk4/pcalon 2006.173.02:52:07.25$pcalon/"no phase cal control is implemented here 2006.173.02:52:07.25$setupk4/"tpicd=stop 2006.173.02:52:07.25$setupk4/"rec=synch_on 2006.173.02:52:07.25$setupk4/"rec_mode=128 2006.173.02:52:07.25$setupk4/!* 2006.173.02:52:07.25$setupk4/recpk4 2006.173.02:52:07.25$recpk4/recpatch= 2006.173.02:52:07.26$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.02:52:07.26$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.02:52:07.26$setupk4/vck44 2006.173.02:52:07.26$vck44/valo=1,524.99 2006.173.02:52:07.26#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.02:52:07.26#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.02:52:07.26#ibcon#ireg 17 cls_cnt 0 2006.173.02:52:07.26#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.02:52:07.26#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.02:52:07.26#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.02:52:07.26#ibcon#enter wrdev, iclass 23, count 0 2006.173.02:52:07.26#ibcon#first serial, iclass 23, count 0 2006.173.02:52:07.26#ibcon#enter sib2, iclass 23, count 0 2006.173.02:52:07.26#ibcon#flushed, iclass 23, count 0 2006.173.02:52:07.26#ibcon#about to write, iclass 23, count 0 2006.173.02:52:07.26#ibcon#wrote, iclass 23, count 0 2006.173.02:52:07.26#ibcon#about to read 3, iclass 23, count 0 2006.173.02:52:07.27#ibcon#read 3, iclass 23, count 0 2006.173.02:52:07.27#ibcon#about to read 4, iclass 23, count 0 2006.173.02:52:07.27#ibcon#read 4, iclass 23, count 0 2006.173.02:52:07.27#ibcon#about to read 5, iclass 23, count 0 2006.173.02:52:07.27#ibcon#read 5, iclass 23, count 0 2006.173.02:52:07.27#ibcon#about to read 6, iclass 23, count 0 2006.173.02:52:07.27#ibcon#read 6, iclass 23, count 0 2006.173.02:52:07.27#ibcon#end of sib2, iclass 23, count 0 2006.173.02:52:07.27#ibcon#*mode == 0, iclass 23, count 0 2006.173.02:52:07.27#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.02:52:07.27#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.02:52:07.27#ibcon#*before write, iclass 23, count 0 2006.173.02:52:07.27#ibcon#enter sib2, iclass 23, count 0 2006.173.02:52:07.27#ibcon#flushed, iclass 23, count 0 2006.173.02:52:07.27#ibcon#about to write, iclass 23, count 0 2006.173.02:52:07.27#ibcon#wrote, iclass 23, count 0 2006.173.02:52:07.27#ibcon#about to read 3, iclass 23, count 0 2006.173.02:52:07.32#ibcon#read 3, iclass 23, count 0 2006.173.02:52:07.32#ibcon#about to read 4, iclass 23, count 0 2006.173.02:52:07.32#ibcon#read 4, iclass 23, count 0 2006.173.02:52:07.32#ibcon#about to read 5, iclass 23, count 0 2006.173.02:52:07.32#ibcon#read 5, iclass 23, count 0 2006.173.02:52:07.32#ibcon#about to read 6, iclass 23, count 0 2006.173.02:52:07.32#ibcon#read 6, iclass 23, count 0 2006.173.02:52:07.32#ibcon#end of sib2, iclass 23, count 0 2006.173.02:52:07.32#ibcon#*after write, iclass 23, count 0 2006.173.02:52:07.32#ibcon#*before return 0, iclass 23, count 0 2006.173.02:52:07.32#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.02:52:07.32#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.02:52:07.32#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.02:52:07.32#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.02:52:07.32$vck44/va=1,7 2006.173.02:52:07.32#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.02:52:07.32#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.02:52:07.32#ibcon#ireg 11 cls_cnt 2 2006.173.02:52:07.32#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.02:52:07.32#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.02:52:07.32#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.02:52:07.32#ibcon#enter wrdev, iclass 25, count 2 2006.173.02:52:07.32#ibcon#first serial, iclass 25, count 2 2006.173.02:52:07.32#ibcon#enter sib2, iclass 25, count 2 2006.173.02:52:07.32#ibcon#flushed, iclass 25, count 2 2006.173.02:52:07.32#ibcon#about to write, iclass 25, count 2 2006.173.02:52:07.32#ibcon#wrote, iclass 25, count 2 2006.173.02:52:07.32#ibcon#about to read 3, iclass 25, count 2 2006.173.02:52:07.34#ibcon#read 3, iclass 25, count 2 2006.173.02:52:07.34#ibcon#about to read 4, iclass 25, count 2 2006.173.02:52:07.34#ibcon#read 4, iclass 25, count 2 2006.173.02:52:07.34#ibcon#about to read 5, iclass 25, count 2 2006.173.02:52:07.34#ibcon#read 5, iclass 25, count 2 2006.173.02:52:07.34#ibcon#about to read 6, iclass 25, count 2 2006.173.02:52:07.34#ibcon#read 6, iclass 25, count 2 2006.173.02:52:07.34#ibcon#end of sib2, iclass 25, count 2 2006.173.02:52:07.34#ibcon#*mode == 0, iclass 25, count 2 2006.173.02:52:07.34#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.02:52:07.34#ibcon#[25=AT01-07\r\n] 2006.173.02:52:07.34#ibcon#*before write, iclass 25, count 2 2006.173.02:52:07.34#ibcon#enter sib2, iclass 25, count 2 2006.173.02:52:07.34#ibcon#flushed, iclass 25, count 2 2006.173.02:52:07.34#ibcon#about to write, iclass 25, count 2 2006.173.02:52:07.34#ibcon#wrote, iclass 25, count 2 2006.173.02:52:07.34#ibcon#about to read 3, iclass 25, count 2 2006.173.02:52:07.37#ibcon#read 3, iclass 25, count 2 2006.173.02:52:07.37#ibcon#about to read 4, iclass 25, count 2 2006.173.02:52:07.37#ibcon#read 4, iclass 25, count 2 2006.173.02:52:07.37#ibcon#about to read 5, iclass 25, count 2 2006.173.02:52:07.37#ibcon#read 5, iclass 25, count 2 2006.173.02:52:07.37#ibcon#about to read 6, iclass 25, count 2 2006.173.02:52:07.37#ibcon#read 6, iclass 25, count 2 2006.173.02:52:07.37#ibcon#end of sib2, iclass 25, count 2 2006.173.02:52:07.37#ibcon#*after write, iclass 25, count 2 2006.173.02:52:07.37#ibcon#*before return 0, iclass 25, count 2 2006.173.02:52:07.37#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.02:52:07.37#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.02:52:07.37#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.02:52:07.37#ibcon#ireg 7 cls_cnt 0 2006.173.02:52:07.37#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.02:52:07.49#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.02:52:07.49#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.02:52:07.49#ibcon#enter wrdev, iclass 25, count 0 2006.173.02:52:07.49#ibcon#first serial, iclass 25, count 0 2006.173.02:52:07.49#ibcon#enter sib2, iclass 25, count 0 2006.173.02:52:07.49#ibcon#flushed, iclass 25, count 0 2006.173.02:52:07.49#ibcon#about to write, iclass 25, count 0 2006.173.02:52:07.49#ibcon#wrote, iclass 25, count 0 2006.173.02:52:07.49#ibcon#about to read 3, iclass 25, count 0 2006.173.02:52:07.52#ibcon#read 3, iclass 25, count 0 2006.173.02:52:07.52#ibcon#about to read 4, iclass 25, count 0 2006.173.02:52:07.52#ibcon#read 4, iclass 25, count 0 2006.173.02:52:07.52#ibcon#about to read 5, iclass 25, count 0 2006.173.02:52:07.52#ibcon#read 5, iclass 25, count 0 2006.173.02:52:07.52#ibcon#about to read 6, iclass 25, count 0 2006.173.02:52:07.52#ibcon#read 6, iclass 25, count 0 2006.173.02:52:07.52#ibcon#end of sib2, iclass 25, count 0 2006.173.02:52:07.52#ibcon#*mode == 0, iclass 25, count 0 2006.173.02:52:07.52#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.02:52:07.52#ibcon#[25=USB\r\n] 2006.173.02:52:07.52#ibcon#*before write, iclass 25, count 0 2006.173.02:52:07.52#ibcon#enter sib2, iclass 25, count 0 2006.173.02:52:07.52#ibcon#flushed, iclass 25, count 0 2006.173.02:52:07.52#ibcon#about to write, iclass 25, count 0 2006.173.02:52:07.52#ibcon#wrote, iclass 25, count 0 2006.173.02:52:07.52#ibcon#about to read 3, iclass 25, count 0 2006.173.02:52:07.55#ibcon#read 3, iclass 25, count 0 2006.173.02:52:07.55#ibcon#about to read 4, iclass 25, count 0 2006.173.02:52:07.55#ibcon#read 4, iclass 25, count 0 2006.173.02:52:07.55#ibcon#about to read 5, iclass 25, count 0 2006.173.02:52:07.55#ibcon#read 5, iclass 25, count 0 2006.173.02:52:07.55#ibcon#about to read 6, iclass 25, count 0 2006.173.02:52:07.55#ibcon#read 6, iclass 25, count 0 2006.173.02:52:07.55#ibcon#end of sib2, iclass 25, count 0 2006.173.02:52:07.55#ibcon#*after write, iclass 25, count 0 2006.173.02:52:07.55#ibcon#*before return 0, iclass 25, count 0 2006.173.02:52:07.55#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.02:52:07.55#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.02:52:07.55#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.02:52:07.55#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.02:52:07.55$vck44/valo=2,534.99 2006.173.02:52:07.55#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.02:52:07.55#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.02:52:07.55#ibcon#ireg 17 cls_cnt 0 2006.173.02:52:07.55#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.02:52:07.55#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.02:52:07.55#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.02:52:07.55#ibcon#enter wrdev, iclass 27, count 0 2006.173.02:52:07.55#ibcon#first serial, iclass 27, count 0 2006.173.02:52:07.55#ibcon#enter sib2, iclass 27, count 0 2006.173.02:52:07.55#ibcon#flushed, iclass 27, count 0 2006.173.02:52:07.55#ibcon#about to write, iclass 27, count 0 2006.173.02:52:07.55#ibcon#wrote, iclass 27, count 0 2006.173.02:52:07.55#ibcon#about to read 3, iclass 27, count 0 2006.173.02:52:07.57#ibcon#read 3, iclass 27, count 0 2006.173.02:52:07.57#ibcon#about to read 4, iclass 27, count 0 2006.173.02:52:07.57#ibcon#read 4, iclass 27, count 0 2006.173.02:52:07.57#ibcon#about to read 5, iclass 27, count 0 2006.173.02:52:07.57#ibcon#read 5, iclass 27, count 0 2006.173.02:52:07.57#ibcon#about to read 6, iclass 27, count 0 2006.173.02:52:07.57#ibcon#read 6, iclass 27, count 0 2006.173.02:52:07.57#ibcon#end of sib2, iclass 27, count 0 2006.173.02:52:07.57#ibcon#*mode == 0, iclass 27, count 0 2006.173.02:52:07.57#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.02:52:07.57#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.02:52:07.57#ibcon#*before write, iclass 27, count 0 2006.173.02:52:07.57#ibcon#enter sib2, iclass 27, count 0 2006.173.02:52:07.57#ibcon#flushed, iclass 27, count 0 2006.173.02:52:07.57#ibcon#about to write, iclass 27, count 0 2006.173.02:52:07.57#ibcon#wrote, iclass 27, count 0 2006.173.02:52:07.57#ibcon#about to read 3, iclass 27, count 0 2006.173.02:52:07.62#ibcon#read 3, iclass 27, count 0 2006.173.02:52:07.62#ibcon#about to read 4, iclass 27, count 0 2006.173.02:52:07.62#ibcon#read 4, iclass 27, count 0 2006.173.02:52:07.62#ibcon#about to read 5, iclass 27, count 0 2006.173.02:52:07.62#ibcon#read 5, iclass 27, count 0 2006.173.02:52:07.62#ibcon#about to read 6, iclass 27, count 0 2006.173.02:52:07.62#ibcon#read 6, iclass 27, count 0 2006.173.02:52:07.62#ibcon#end of sib2, iclass 27, count 0 2006.173.02:52:07.62#ibcon#*after write, iclass 27, count 0 2006.173.02:52:07.62#ibcon#*before return 0, iclass 27, count 0 2006.173.02:52:07.62#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.02:52:07.62#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.02:52:07.62#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.02:52:07.62#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.02:52:07.62$vck44/va=2,6 2006.173.02:52:07.62#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.02:52:07.62#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.02:52:07.62#ibcon#ireg 11 cls_cnt 2 2006.173.02:52:07.62#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.02:52:07.66#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.02:52:07.66#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.02:52:07.66#ibcon#enter wrdev, iclass 29, count 2 2006.173.02:52:07.66#ibcon#first serial, iclass 29, count 2 2006.173.02:52:07.66#ibcon#enter sib2, iclass 29, count 2 2006.173.02:52:07.66#ibcon#flushed, iclass 29, count 2 2006.173.02:52:07.66#ibcon#about to write, iclass 29, count 2 2006.173.02:52:07.66#ibcon#wrote, iclass 29, count 2 2006.173.02:52:07.66#ibcon#about to read 3, iclass 29, count 2 2006.173.02:52:07.68#ibcon#read 3, iclass 29, count 2 2006.173.02:52:07.68#ibcon#about to read 4, iclass 29, count 2 2006.173.02:52:07.68#ibcon#read 4, iclass 29, count 2 2006.173.02:52:07.68#ibcon#about to read 5, iclass 29, count 2 2006.173.02:52:07.68#ibcon#read 5, iclass 29, count 2 2006.173.02:52:07.68#ibcon#about to read 6, iclass 29, count 2 2006.173.02:52:07.68#ibcon#read 6, iclass 29, count 2 2006.173.02:52:07.68#ibcon#end of sib2, iclass 29, count 2 2006.173.02:52:07.68#ibcon#*mode == 0, iclass 29, count 2 2006.173.02:52:07.68#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.02:52:07.68#ibcon#[25=AT02-06\r\n] 2006.173.02:52:07.68#ibcon#*before write, iclass 29, count 2 2006.173.02:52:07.68#ibcon#enter sib2, iclass 29, count 2 2006.173.02:52:07.68#ibcon#flushed, iclass 29, count 2 2006.173.02:52:07.68#ibcon#about to write, iclass 29, count 2 2006.173.02:52:07.68#ibcon#wrote, iclass 29, count 2 2006.173.02:52:07.68#ibcon#about to read 3, iclass 29, count 2 2006.173.02:52:07.71#ibcon#read 3, iclass 29, count 2 2006.173.02:52:07.71#ibcon#about to read 4, iclass 29, count 2 2006.173.02:52:07.71#ibcon#read 4, iclass 29, count 2 2006.173.02:52:07.71#ibcon#about to read 5, iclass 29, count 2 2006.173.02:52:07.71#ibcon#read 5, iclass 29, count 2 2006.173.02:52:07.71#ibcon#about to read 6, iclass 29, count 2 2006.173.02:52:07.71#ibcon#read 6, iclass 29, count 2 2006.173.02:52:07.71#ibcon#end of sib2, iclass 29, count 2 2006.173.02:52:07.71#ibcon#*after write, iclass 29, count 2 2006.173.02:52:07.71#ibcon#*before return 0, iclass 29, count 2 2006.173.02:52:07.71#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.02:52:07.71#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.02:52:07.71#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.02:52:07.71#ibcon#ireg 7 cls_cnt 0 2006.173.02:52:07.71#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.02:52:07.83#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.02:52:07.83#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.02:52:07.83#ibcon#enter wrdev, iclass 29, count 0 2006.173.02:52:07.83#ibcon#first serial, iclass 29, count 0 2006.173.02:52:07.83#ibcon#enter sib2, iclass 29, count 0 2006.173.02:52:07.83#ibcon#flushed, iclass 29, count 0 2006.173.02:52:07.83#ibcon#about to write, iclass 29, count 0 2006.173.02:52:07.83#ibcon#wrote, iclass 29, count 0 2006.173.02:52:07.83#ibcon#about to read 3, iclass 29, count 0 2006.173.02:52:07.85#ibcon#read 3, iclass 29, count 0 2006.173.02:52:07.85#ibcon#about to read 4, iclass 29, count 0 2006.173.02:52:07.85#ibcon#read 4, iclass 29, count 0 2006.173.02:52:07.85#ibcon#about to read 5, iclass 29, count 0 2006.173.02:52:07.85#ibcon#read 5, iclass 29, count 0 2006.173.02:52:07.85#ibcon#about to read 6, iclass 29, count 0 2006.173.02:52:07.85#ibcon#read 6, iclass 29, count 0 2006.173.02:52:07.85#ibcon#end of sib2, iclass 29, count 0 2006.173.02:52:07.85#ibcon#*mode == 0, iclass 29, count 0 2006.173.02:52:07.85#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.02:52:07.85#ibcon#[25=USB\r\n] 2006.173.02:52:07.85#ibcon#*before write, iclass 29, count 0 2006.173.02:52:07.85#ibcon#enter sib2, iclass 29, count 0 2006.173.02:52:07.85#ibcon#flushed, iclass 29, count 0 2006.173.02:52:07.85#ibcon#about to write, iclass 29, count 0 2006.173.02:52:07.85#ibcon#wrote, iclass 29, count 0 2006.173.02:52:07.85#ibcon#about to read 3, iclass 29, count 0 2006.173.02:52:07.88#ibcon#read 3, iclass 29, count 0 2006.173.02:52:07.88#ibcon#about to read 4, iclass 29, count 0 2006.173.02:52:07.88#ibcon#read 4, iclass 29, count 0 2006.173.02:52:07.88#ibcon#about to read 5, iclass 29, count 0 2006.173.02:52:07.88#ibcon#read 5, iclass 29, count 0 2006.173.02:52:07.88#ibcon#about to read 6, iclass 29, count 0 2006.173.02:52:07.88#ibcon#read 6, iclass 29, count 0 2006.173.02:52:07.88#ibcon#end of sib2, iclass 29, count 0 2006.173.02:52:07.88#ibcon#*after write, iclass 29, count 0 2006.173.02:52:07.88#ibcon#*before return 0, iclass 29, count 0 2006.173.02:52:07.88#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.02:52:07.88#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.02:52:07.88#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.02:52:07.88#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.02:52:07.88$vck44/valo=3,564.99 2006.173.02:52:07.88#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.02:52:07.88#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.02:52:07.88#ibcon#ireg 17 cls_cnt 0 2006.173.02:52:07.88#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.02:52:07.88#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.02:52:07.88#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.02:52:07.88#ibcon#enter wrdev, iclass 31, count 0 2006.173.02:52:07.88#ibcon#first serial, iclass 31, count 0 2006.173.02:52:07.88#ibcon#enter sib2, iclass 31, count 0 2006.173.02:52:07.88#ibcon#flushed, iclass 31, count 0 2006.173.02:52:07.88#ibcon#about to write, iclass 31, count 0 2006.173.02:52:07.88#ibcon#wrote, iclass 31, count 0 2006.173.02:52:07.88#ibcon#about to read 3, iclass 31, count 0 2006.173.02:52:07.90#ibcon#read 3, iclass 31, count 0 2006.173.02:52:07.90#ibcon#about to read 4, iclass 31, count 0 2006.173.02:52:07.90#ibcon#read 4, iclass 31, count 0 2006.173.02:52:07.90#ibcon#about to read 5, iclass 31, count 0 2006.173.02:52:07.90#ibcon#read 5, iclass 31, count 0 2006.173.02:52:07.90#ibcon#about to read 6, iclass 31, count 0 2006.173.02:52:07.90#ibcon#read 6, iclass 31, count 0 2006.173.02:52:07.90#ibcon#end of sib2, iclass 31, count 0 2006.173.02:52:07.90#ibcon#*mode == 0, iclass 31, count 0 2006.173.02:52:07.90#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.02:52:07.90#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.02:52:07.90#ibcon#*before write, iclass 31, count 0 2006.173.02:52:07.90#ibcon#enter sib2, iclass 31, count 0 2006.173.02:52:07.90#ibcon#flushed, iclass 31, count 0 2006.173.02:52:07.90#ibcon#about to write, iclass 31, count 0 2006.173.02:52:07.90#ibcon#wrote, iclass 31, count 0 2006.173.02:52:07.90#ibcon#about to read 3, iclass 31, count 0 2006.173.02:52:07.94#ibcon#read 3, iclass 31, count 0 2006.173.02:52:07.94#ibcon#about to read 4, iclass 31, count 0 2006.173.02:52:07.94#ibcon#read 4, iclass 31, count 0 2006.173.02:52:07.94#ibcon#about to read 5, iclass 31, count 0 2006.173.02:52:07.94#ibcon#read 5, iclass 31, count 0 2006.173.02:52:07.94#ibcon#about to read 6, iclass 31, count 0 2006.173.02:52:07.94#ibcon#read 6, iclass 31, count 0 2006.173.02:52:07.94#ibcon#end of sib2, iclass 31, count 0 2006.173.02:52:07.94#ibcon#*after write, iclass 31, count 0 2006.173.02:52:07.94#ibcon#*before return 0, iclass 31, count 0 2006.173.02:52:07.94#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.02:52:07.94#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.02:52:07.94#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.02:52:07.94#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.02:52:07.94$vck44/va=3,5 2006.173.02:52:07.94#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.173.02:52:07.94#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.173.02:52:07.94#ibcon#ireg 11 cls_cnt 2 2006.173.02:52:07.94#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.02:52:08.00#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.02:52:08.00#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.02:52:08.00#ibcon#enter wrdev, iclass 33, count 2 2006.173.02:52:08.00#ibcon#first serial, iclass 33, count 2 2006.173.02:52:08.00#ibcon#enter sib2, iclass 33, count 2 2006.173.02:52:08.00#ibcon#flushed, iclass 33, count 2 2006.173.02:52:08.00#ibcon#about to write, iclass 33, count 2 2006.173.02:52:08.00#ibcon#wrote, iclass 33, count 2 2006.173.02:52:08.00#ibcon#about to read 3, iclass 33, count 2 2006.173.02:52:08.02#ibcon#read 3, iclass 33, count 2 2006.173.02:52:08.02#ibcon#about to read 4, iclass 33, count 2 2006.173.02:52:08.02#ibcon#read 4, iclass 33, count 2 2006.173.02:52:08.02#ibcon#about to read 5, iclass 33, count 2 2006.173.02:52:08.02#ibcon#read 5, iclass 33, count 2 2006.173.02:52:08.02#ibcon#about to read 6, iclass 33, count 2 2006.173.02:52:08.02#ibcon#read 6, iclass 33, count 2 2006.173.02:52:08.02#ibcon#end of sib2, iclass 33, count 2 2006.173.02:52:08.02#ibcon#*mode == 0, iclass 33, count 2 2006.173.02:52:08.02#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.173.02:52:08.02#ibcon#[25=AT03-05\r\n] 2006.173.02:52:08.02#ibcon#*before write, iclass 33, count 2 2006.173.02:52:08.02#ibcon#enter sib2, iclass 33, count 2 2006.173.02:52:08.02#ibcon#flushed, iclass 33, count 2 2006.173.02:52:08.02#ibcon#about to write, iclass 33, count 2 2006.173.02:52:08.02#ibcon#wrote, iclass 33, count 2 2006.173.02:52:08.02#ibcon#about to read 3, iclass 33, count 2 2006.173.02:52:08.05#ibcon#read 3, iclass 33, count 2 2006.173.02:52:08.05#ibcon#about to read 4, iclass 33, count 2 2006.173.02:52:08.05#ibcon#read 4, iclass 33, count 2 2006.173.02:52:08.05#ibcon#about to read 5, iclass 33, count 2 2006.173.02:52:08.05#ibcon#read 5, iclass 33, count 2 2006.173.02:52:08.05#ibcon#about to read 6, iclass 33, count 2 2006.173.02:52:08.05#ibcon#read 6, iclass 33, count 2 2006.173.02:52:08.05#ibcon#end of sib2, iclass 33, count 2 2006.173.02:52:08.05#ibcon#*after write, iclass 33, count 2 2006.173.02:52:08.05#ibcon#*before return 0, iclass 33, count 2 2006.173.02:52:08.05#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.02:52:08.05#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.173.02:52:08.05#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.173.02:52:08.05#ibcon#ireg 7 cls_cnt 0 2006.173.02:52:08.05#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.02:52:08.17#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.02:52:08.17#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.02:52:08.17#ibcon#enter wrdev, iclass 33, count 0 2006.173.02:52:08.17#ibcon#first serial, iclass 33, count 0 2006.173.02:52:08.17#ibcon#enter sib2, iclass 33, count 0 2006.173.02:52:08.17#ibcon#flushed, iclass 33, count 0 2006.173.02:52:08.17#ibcon#about to write, iclass 33, count 0 2006.173.02:52:08.17#ibcon#wrote, iclass 33, count 0 2006.173.02:52:08.17#ibcon#about to read 3, iclass 33, count 0 2006.173.02:52:08.19#ibcon#read 3, iclass 33, count 0 2006.173.02:52:08.19#ibcon#about to read 4, iclass 33, count 0 2006.173.02:52:08.19#ibcon#read 4, iclass 33, count 0 2006.173.02:52:08.19#ibcon#about to read 5, iclass 33, count 0 2006.173.02:52:08.19#ibcon#read 5, iclass 33, count 0 2006.173.02:52:08.19#ibcon#about to read 6, iclass 33, count 0 2006.173.02:52:08.19#ibcon#read 6, iclass 33, count 0 2006.173.02:52:08.19#ibcon#end of sib2, iclass 33, count 0 2006.173.02:52:08.19#ibcon#*mode == 0, iclass 33, count 0 2006.173.02:52:08.19#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.02:52:08.19#ibcon#[25=USB\r\n] 2006.173.02:52:08.19#ibcon#*before write, iclass 33, count 0 2006.173.02:52:08.19#ibcon#enter sib2, iclass 33, count 0 2006.173.02:52:08.19#ibcon#flushed, iclass 33, count 0 2006.173.02:52:08.19#ibcon#about to write, iclass 33, count 0 2006.173.02:52:08.19#ibcon#wrote, iclass 33, count 0 2006.173.02:52:08.19#ibcon#about to read 3, iclass 33, count 0 2006.173.02:52:08.22#ibcon#read 3, iclass 33, count 0 2006.173.02:52:08.22#ibcon#about to read 4, iclass 33, count 0 2006.173.02:52:08.22#ibcon#read 4, iclass 33, count 0 2006.173.02:52:08.22#ibcon#about to read 5, iclass 33, count 0 2006.173.02:52:08.22#ibcon#read 5, iclass 33, count 0 2006.173.02:52:08.22#ibcon#about to read 6, iclass 33, count 0 2006.173.02:52:08.22#ibcon#read 6, iclass 33, count 0 2006.173.02:52:08.22#ibcon#end of sib2, iclass 33, count 0 2006.173.02:52:08.22#ibcon#*after write, iclass 33, count 0 2006.173.02:52:08.22#ibcon#*before return 0, iclass 33, count 0 2006.173.02:52:08.22#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.02:52:08.22#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.173.02:52:08.22#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.02:52:08.22#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.02:52:08.22$vck44/valo=4,624.99 2006.173.02:52:08.22#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.02:52:08.22#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.02:52:08.22#ibcon#ireg 17 cls_cnt 0 2006.173.02:52:08.22#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.02:52:08.22#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.02:52:08.22#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.02:52:08.22#ibcon#enter wrdev, iclass 35, count 0 2006.173.02:52:08.22#ibcon#first serial, iclass 35, count 0 2006.173.02:52:08.22#ibcon#enter sib2, iclass 35, count 0 2006.173.02:52:08.22#ibcon#flushed, iclass 35, count 0 2006.173.02:52:08.22#ibcon#about to write, iclass 35, count 0 2006.173.02:52:08.22#ibcon#wrote, iclass 35, count 0 2006.173.02:52:08.22#ibcon#about to read 3, iclass 35, count 0 2006.173.02:52:08.24#ibcon#read 3, iclass 35, count 0 2006.173.02:52:08.24#ibcon#about to read 4, iclass 35, count 0 2006.173.02:52:08.24#ibcon#read 4, iclass 35, count 0 2006.173.02:52:08.24#ibcon#about to read 5, iclass 35, count 0 2006.173.02:52:08.24#ibcon#read 5, iclass 35, count 0 2006.173.02:52:08.24#ibcon#about to read 6, iclass 35, count 0 2006.173.02:52:08.24#ibcon#read 6, iclass 35, count 0 2006.173.02:52:08.24#ibcon#end of sib2, iclass 35, count 0 2006.173.02:52:08.24#ibcon#*mode == 0, iclass 35, count 0 2006.173.02:52:08.24#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.02:52:08.24#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.02:52:08.24#ibcon#*before write, iclass 35, count 0 2006.173.02:52:08.24#ibcon#enter sib2, iclass 35, count 0 2006.173.02:52:08.24#ibcon#flushed, iclass 35, count 0 2006.173.02:52:08.24#ibcon#about to write, iclass 35, count 0 2006.173.02:52:08.24#ibcon#wrote, iclass 35, count 0 2006.173.02:52:08.24#ibcon#about to read 3, iclass 35, count 0 2006.173.02:52:08.28#ibcon#read 3, iclass 35, count 0 2006.173.02:52:08.28#ibcon#about to read 4, iclass 35, count 0 2006.173.02:52:08.28#ibcon#read 4, iclass 35, count 0 2006.173.02:52:08.28#ibcon#about to read 5, iclass 35, count 0 2006.173.02:52:08.28#ibcon#read 5, iclass 35, count 0 2006.173.02:52:08.28#ibcon#about to read 6, iclass 35, count 0 2006.173.02:52:08.28#ibcon#read 6, iclass 35, count 0 2006.173.02:52:08.28#ibcon#end of sib2, iclass 35, count 0 2006.173.02:52:08.28#ibcon#*after write, iclass 35, count 0 2006.173.02:52:08.28#ibcon#*before return 0, iclass 35, count 0 2006.173.02:52:08.28#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.02:52:08.28#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.02:52:08.28#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.02:52:08.28#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.02:52:08.28$vck44/va=4,6 2006.173.02:52:08.28#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.173.02:52:08.28#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.173.02:52:08.28#ibcon#ireg 11 cls_cnt 2 2006.173.02:52:08.28#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.02:52:08.34#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.02:52:08.34#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.02:52:08.34#ibcon#enter wrdev, iclass 37, count 2 2006.173.02:52:08.34#ibcon#first serial, iclass 37, count 2 2006.173.02:52:08.34#ibcon#enter sib2, iclass 37, count 2 2006.173.02:52:08.34#ibcon#flushed, iclass 37, count 2 2006.173.02:52:08.34#ibcon#about to write, iclass 37, count 2 2006.173.02:52:08.34#ibcon#wrote, iclass 37, count 2 2006.173.02:52:08.34#ibcon#about to read 3, iclass 37, count 2 2006.173.02:52:08.36#ibcon#read 3, iclass 37, count 2 2006.173.02:52:08.36#ibcon#about to read 4, iclass 37, count 2 2006.173.02:52:08.36#ibcon#read 4, iclass 37, count 2 2006.173.02:52:08.36#ibcon#about to read 5, iclass 37, count 2 2006.173.02:52:08.36#ibcon#read 5, iclass 37, count 2 2006.173.02:52:08.36#ibcon#about to read 6, iclass 37, count 2 2006.173.02:52:08.36#ibcon#read 6, iclass 37, count 2 2006.173.02:52:08.36#ibcon#end of sib2, iclass 37, count 2 2006.173.02:52:08.36#ibcon#*mode == 0, iclass 37, count 2 2006.173.02:52:08.36#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.173.02:52:08.36#ibcon#[25=AT04-06\r\n] 2006.173.02:52:08.36#ibcon#*before write, iclass 37, count 2 2006.173.02:52:08.36#ibcon#enter sib2, iclass 37, count 2 2006.173.02:52:08.36#ibcon#flushed, iclass 37, count 2 2006.173.02:52:08.36#ibcon#about to write, iclass 37, count 2 2006.173.02:52:08.36#ibcon#wrote, iclass 37, count 2 2006.173.02:52:08.36#ibcon#about to read 3, iclass 37, count 2 2006.173.02:52:08.39#ibcon#read 3, iclass 37, count 2 2006.173.02:52:08.39#ibcon#about to read 4, iclass 37, count 2 2006.173.02:52:08.39#ibcon#read 4, iclass 37, count 2 2006.173.02:52:08.39#ibcon#about to read 5, iclass 37, count 2 2006.173.02:52:08.39#ibcon#read 5, iclass 37, count 2 2006.173.02:52:08.39#ibcon#about to read 6, iclass 37, count 2 2006.173.02:52:08.39#ibcon#read 6, iclass 37, count 2 2006.173.02:52:08.39#ibcon#end of sib2, iclass 37, count 2 2006.173.02:52:08.39#ibcon#*after write, iclass 37, count 2 2006.173.02:52:08.39#ibcon#*before return 0, iclass 37, count 2 2006.173.02:52:08.39#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.02:52:08.39#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.173.02:52:08.39#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.173.02:52:08.39#ibcon#ireg 7 cls_cnt 0 2006.173.02:52:08.39#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.02:52:08.51#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.02:52:08.51#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.02:52:08.51#ibcon#enter wrdev, iclass 37, count 0 2006.173.02:52:08.51#ibcon#first serial, iclass 37, count 0 2006.173.02:52:08.51#ibcon#enter sib2, iclass 37, count 0 2006.173.02:52:08.51#ibcon#flushed, iclass 37, count 0 2006.173.02:52:08.51#ibcon#about to write, iclass 37, count 0 2006.173.02:52:08.51#ibcon#wrote, iclass 37, count 0 2006.173.02:52:08.51#ibcon#about to read 3, iclass 37, count 0 2006.173.02:52:08.53#ibcon#read 3, iclass 37, count 0 2006.173.02:52:08.53#ibcon#about to read 4, iclass 37, count 0 2006.173.02:52:08.53#ibcon#read 4, iclass 37, count 0 2006.173.02:52:08.53#ibcon#about to read 5, iclass 37, count 0 2006.173.02:52:08.53#ibcon#read 5, iclass 37, count 0 2006.173.02:52:08.53#ibcon#about to read 6, iclass 37, count 0 2006.173.02:52:08.53#ibcon#read 6, iclass 37, count 0 2006.173.02:52:08.53#ibcon#end of sib2, iclass 37, count 0 2006.173.02:52:08.53#ibcon#*mode == 0, iclass 37, count 0 2006.173.02:52:08.53#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.02:52:08.53#ibcon#[25=USB\r\n] 2006.173.02:52:08.53#ibcon#*before write, iclass 37, count 0 2006.173.02:52:08.53#ibcon#enter sib2, iclass 37, count 0 2006.173.02:52:08.53#ibcon#flushed, iclass 37, count 0 2006.173.02:52:08.53#ibcon#about to write, iclass 37, count 0 2006.173.02:52:08.53#ibcon#wrote, iclass 37, count 0 2006.173.02:52:08.53#ibcon#about to read 3, iclass 37, count 0 2006.173.02:52:08.56#ibcon#read 3, iclass 37, count 0 2006.173.02:52:08.56#ibcon#about to read 4, iclass 37, count 0 2006.173.02:52:08.56#ibcon#read 4, iclass 37, count 0 2006.173.02:52:08.56#ibcon#about to read 5, iclass 37, count 0 2006.173.02:52:08.56#ibcon#read 5, iclass 37, count 0 2006.173.02:52:08.56#ibcon#about to read 6, iclass 37, count 0 2006.173.02:52:08.56#ibcon#read 6, iclass 37, count 0 2006.173.02:52:08.56#ibcon#end of sib2, iclass 37, count 0 2006.173.02:52:08.56#ibcon#*after write, iclass 37, count 0 2006.173.02:52:08.56#ibcon#*before return 0, iclass 37, count 0 2006.173.02:52:08.56#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.02:52:08.56#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.173.02:52:08.56#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.02:52:08.56#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.02:52:08.56$vck44/valo=5,734.99 2006.173.02:52:08.56#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.02:52:08.56#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.02:52:08.56#ibcon#ireg 17 cls_cnt 0 2006.173.02:52:08.56#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.02:52:08.56#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.02:52:08.56#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.02:52:08.56#ibcon#enter wrdev, iclass 39, count 0 2006.173.02:52:08.56#ibcon#first serial, iclass 39, count 0 2006.173.02:52:08.56#ibcon#enter sib2, iclass 39, count 0 2006.173.02:52:08.56#ibcon#flushed, iclass 39, count 0 2006.173.02:52:08.56#ibcon#about to write, iclass 39, count 0 2006.173.02:52:08.56#ibcon#wrote, iclass 39, count 0 2006.173.02:52:08.56#ibcon#about to read 3, iclass 39, count 0 2006.173.02:52:08.58#ibcon#read 3, iclass 39, count 0 2006.173.02:52:08.58#ibcon#about to read 4, iclass 39, count 0 2006.173.02:52:08.58#ibcon#read 4, iclass 39, count 0 2006.173.02:52:08.58#ibcon#about to read 5, iclass 39, count 0 2006.173.02:52:08.58#ibcon#read 5, iclass 39, count 0 2006.173.02:52:08.58#ibcon#about to read 6, iclass 39, count 0 2006.173.02:52:08.58#ibcon#read 6, iclass 39, count 0 2006.173.02:52:08.58#ibcon#end of sib2, iclass 39, count 0 2006.173.02:52:08.58#ibcon#*mode == 0, iclass 39, count 0 2006.173.02:52:08.58#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.02:52:08.58#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.02:52:08.58#ibcon#*before write, iclass 39, count 0 2006.173.02:52:08.58#ibcon#enter sib2, iclass 39, count 0 2006.173.02:52:08.58#ibcon#flushed, iclass 39, count 0 2006.173.02:52:08.58#ibcon#about to write, iclass 39, count 0 2006.173.02:52:08.58#ibcon#wrote, iclass 39, count 0 2006.173.02:52:08.58#ibcon#about to read 3, iclass 39, count 0 2006.173.02:52:08.62#ibcon#read 3, iclass 39, count 0 2006.173.02:52:08.62#ibcon#about to read 4, iclass 39, count 0 2006.173.02:52:08.62#ibcon#read 4, iclass 39, count 0 2006.173.02:52:08.62#ibcon#about to read 5, iclass 39, count 0 2006.173.02:52:08.62#ibcon#read 5, iclass 39, count 0 2006.173.02:52:08.62#ibcon#about to read 6, iclass 39, count 0 2006.173.02:52:08.62#ibcon#read 6, iclass 39, count 0 2006.173.02:52:08.62#ibcon#end of sib2, iclass 39, count 0 2006.173.02:52:08.62#ibcon#*after write, iclass 39, count 0 2006.173.02:52:08.62#ibcon#*before return 0, iclass 39, count 0 2006.173.02:52:08.62#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.02:52:08.62#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.02:52:08.62#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.02:52:08.62#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.02:52:08.62$vck44/va=5,4 2006.173.02:52:08.62#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.02:52:08.62#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.02:52:08.62#ibcon#ireg 11 cls_cnt 2 2006.173.02:52:08.62#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.02:52:08.68#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.02:52:08.68#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.02:52:08.68#ibcon#enter wrdev, iclass 3, count 2 2006.173.02:52:08.68#ibcon#first serial, iclass 3, count 2 2006.173.02:52:08.68#ibcon#enter sib2, iclass 3, count 2 2006.173.02:52:08.68#ibcon#flushed, iclass 3, count 2 2006.173.02:52:08.68#ibcon#about to write, iclass 3, count 2 2006.173.02:52:08.68#ibcon#wrote, iclass 3, count 2 2006.173.02:52:08.68#ibcon#about to read 3, iclass 3, count 2 2006.173.02:52:08.70#ibcon#read 3, iclass 3, count 2 2006.173.02:52:08.70#ibcon#about to read 4, iclass 3, count 2 2006.173.02:52:08.70#ibcon#read 4, iclass 3, count 2 2006.173.02:52:08.70#ibcon#about to read 5, iclass 3, count 2 2006.173.02:52:08.70#ibcon#read 5, iclass 3, count 2 2006.173.02:52:08.70#ibcon#about to read 6, iclass 3, count 2 2006.173.02:52:08.70#ibcon#read 6, iclass 3, count 2 2006.173.02:52:08.70#ibcon#end of sib2, iclass 3, count 2 2006.173.02:52:08.70#ibcon#*mode == 0, iclass 3, count 2 2006.173.02:52:08.70#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.02:52:08.70#ibcon#[25=AT05-04\r\n] 2006.173.02:52:08.70#ibcon#*before write, iclass 3, count 2 2006.173.02:52:08.70#ibcon#enter sib2, iclass 3, count 2 2006.173.02:52:08.70#ibcon#flushed, iclass 3, count 2 2006.173.02:52:08.70#ibcon#about to write, iclass 3, count 2 2006.173.02:52:08.70#ibcon#wrote, iclass 3, count 2 2006.173.02:52:08.70#ibcon#about to read 3, iclass 3, count 2 2006.173.02:52:08.73#ibcon#read 3, iclass 3, count 2 2006.173.02:52:08.73#ibcon#about to read 4, iclass 3, count 2 2006.173.02:52:08.73#ibcon#read 4, iclass 3, count 2 2006.173.02:52:08.73#ibcon#about to read 5, iclass 3, count 2 2006.173.02:52:08.73#ibcon#read 5, iclass 3, count 2 2006.173.02:52:08.73#ibcon#about to read 6, iclass 3, count 2 2006.173.02:52:08.73#ibcon#read 6, iclass 3, count 2 2006.173.02:52:08.73#ibcon#end of sib2, iclass 3, count 2 2006.173.02:52:08.73#ibcon#*after write, iclass 3, count 2 2006.173.02:52:08.73#ibcon#*before return 0, iclass 3, count 2 2006.173.02:52:08.73#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.02:52:08.73#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.02:52:08.73#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.02:52:08.73#ibcon#ireg 7 cls_cnt 0 2006.173.02:52:08.73#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.02:52:08.85#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.02:52:08.85#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.02:52:08.85#ibcon#enter wrdev, iclass 3, count 0 2006.173.02:52:08.85#ibcon#first serial, iclass 3, count 0 2006.173.02:52:08.85#ibcon#enter sib2, iclass 3, count 0 2006.173.02:52:08.85#ibcon#flushed, iclass 3, count 0 2006.173.02:52:08.85#ibcon#about to write, iclass 3, count 0 2006.173.02:52:08.85#ibcon#wrote, iclass 3, count 0 2006.173.02:52:08.85#ibcon#about to read 3, iclass 3, count 0 2006.173.02:52:08.87#ibcon#read 3, iclass 3, count 0 2006.173.02:52:08.87#ibcon#about to read 4, iclass 3, count 0 2006.173.02:52:08.87#ibcon#read 4, iclass 3, count 0 2006.173.02:52:08.87#ibcon#about to read 5, iclass 3, count 0 2006.173.02:52:08.87#ibcon#read 5, iclass 3, count 0 2006.173.02:52:08.87#ibcon#about to read 6, iclass 3, count 0 2006.173.02:52:08.87#ibcon#read 6, iclass 3, count 0 2006.173.02:52:08.87#ibcon#end of sib2, iclass 3, count 0 2006.173.02:52:08.87#ibcon#*mode == 0, iclass 3, count 0 2006.173.02:52:08.87#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.02:52:08.87#ibcon#[25=USB\r\n] 2006.173.02:52:08.87#ibcon#*before write, iclass 3, count 0 2006.173.02:52:08.87#ibcon#enter sib2, iclass 3, count 0 2006.173.02:52:08.87#ibcon#flushed, iclass 3, count 0 2006.173.02:52:08.87#ibcon#about to write, iclass 3, count 0 2006.173.02:52:08.87#ibcon#wrote, iclass 3, count 0 2006.173.02:52:08.87#ibcon#about to read 3, iclass 3, count 0 2006.173.02:52:08.90#ibcon#read 3, iclass 3, count 0 2006.173.02:52:08.90#ibcon#about to read 4, iclass 3, count 0 2006.173.02:52:08.90#ibcon#read 4, iclass 3, count 0 2006.173.02:52:08.90#ibcon#about to read 5, iclass 3, count 0 2006.173.02:52:08.90#ibcon#read 5, iclass 3, count 0 2006.173.02:52:08.90#ibcon#about to read 6, iclass 3, count 0 2006.173.02:52:08.90#ibcon#read 6, iclass 3, count 0 2006.173.02:52:08.90#ibcon#end of sib2, iclass 3, count 0 2006.173.02:52:08.90#ibcon#*after write, iclass 3, count 0 2006.173.02:52:08.90#ibcon#*before return 0, iclass 3, count 0 2006.173.02:52:08.90#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.02:52:08.90#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.02:52:08.90#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.02:52:08.90#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.02:52:08.90$vck44/valo=6,814.99 2006.173.02:52:08.90#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.02:52:08.90#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.02:52:08.90#ibcon#ireg 17 cls_cnt 0 2006.173.02:52:08.90#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.02:52:08.90#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.02:52:08.90#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.02:52:08.90#ibcon#enter wrdev, iclass 5, count 0 2006.173.02:52:08.90#ibcon#first serial, iclass 5, count 0 2006.173.02:52:08.90#ibcon#enter sib2, iclass 5, count 0 2006.173.02:52:08.90#ibcon#flushed, iclass 5, count 0 2006.173.02:52:08.90#ibcon#about to write, iclass 5, count 0 2006.173.02:52:08.90#ibcon#wrote, iclass 5, count 0 2006.173.02:52:08.90#ibcon#about to read 3, iclass 5, count 0 2006.173.02:52:08.92#ibcon#read 3, iclass 5, count 0 2006.173.02:52:08.92#ibcon#about to read 4, iclass 5, count 0 2006.173.02:52:08.92#ibcon#read 4, iclass 5, count 0 2006.173.02:52:08.92#ibcon#about to read 5, iclass 5, count 0 2006.173.02:52:08.92#ibcon#read 5, iclass 5, count 0 2006.173.02:52:08.92#ibcon#about to read 6, iclass 5, count 0 2006.173.02:52:08.92#ibcon#read 6, iclass 5, count 0 2006.173.02:52:08.92#ibcon#end of sib2, iclass 5, count 0 2006.173.02:52:08.92#ibcon#*mode == 0, iclass 5, count 0 2006.173.02:52:08.92#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.02:52:08.92#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.02:52:08.92#ibcon#*before write, iclass 5, count 0 2006.173.02:52:08.92#ibcon#enter sib2, iclass 5, count 0 2006.173.02:52:08.92#ibcon#flushed, iclass 5, count 0 2006.173.02:52:08.92#ibcon#about to write, iclass 5, count 0 2006.173.02:52:08.92#ibcon#wrote, iclass 5, count 0 2006.173.02:52:08.92#ibcon#about to read 3, iclass 5, count 0 2006.173.02:52:08.96#ibcon#read 3, iclass 5, count 0 2006.173.02:52:08.96#ibcon#about to read 4, iclass 5, count 0 2006.173.02:52:08.96#ibcon#read 4, iclass 5, count 0 2006.173.02:52:08.96#ibcon#about to read 5, iclass 5, count 0 2006.173.02:52:08.96#ibcon#read 5, iclass 5, count 0 2006.173.02:52:08.96#ibcon#about to read 6, iclass 5, count 0 2006.173.02:52:08.96#ibcon#read 6, iclass 5, count 0 2006.173.02:52:08.96#ibcon#end of sib2, iclass 5, count 0 2006.173.02:52:08.96#ibcon#*after write, iclass 5, count 0 2006.173.02:52:08.96#ibcon#*before return 0, iclass 5, count 0 2006.173.02:52:08.96#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.02:52:08.96#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.02:52:08.96#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.02:52:08.96#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.02:52:08.96$vck44/va=6,3 2006.173.02:52:08.96#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.173.02:52:08.96#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.173.02:52:08.96#ibcon#ireg 11 cls_cnt 2 2006.173.02:52:08.96#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.02:52:09.02#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.02:52:09.02#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.02:52:09.02#ibcon#enter wrdev, iclass 7, count 2 2006.173.02:52:09.02#ibcon#first serial, iclass 7, count 2 2006.173.02:52:09.02#ibcon#enter sib2, iclass 7, count 2 2006.173.02:52:09.02#ibcon#flushed, iclass 7, count 2 2006.173.02:52:09.02#ibcon#about to write, iclass 7, count 2 2006.173.02:52:09.02#ibcon#wrote, iclass 7, count 2 2006.173.02:52:09.02#ibcon#about to read 3, iclass 7, count 2 2006.173.02:52:09.04#ibcon#read 3, iclass 7, count 2 2006.173.02:52:09.04#ibcon#about to read 4, iclass 7, count 2 2006.173.02:52:09.04#ibcon#read 4, iclass 7, count 2 2006.173.02:52:09.04#ibcon#about to read 5, iclass 7, count 2 2006.173.02:52:09.04#ibcon#read 5, iclass 7, count 2 2006.173.02:52:09.04#ibcon#about to read 6, iclass 7, count 2 2006.173.02:52:09.04#ibcon#read 6, iclass 7, count 2 2006.173.02:52:09.04#ibcon#end of sib2, iclass 7, count 2 2006.173.02:52:09.04#ibcon#*mode == 0, iclass 7, count 2 2006.173.02:52:09.04#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.173.02:52:09.04#ibcon#[25=AT06-03\r\n] 2006.173.02:52:09.04#ibcon#*before write, iclass 7, count 2 2006.173.02:52:09.04#ibcon#enter sib2, iclass 7, count 2 2006.173.02:52:09.04#ibcon#flushed, iclass 7, count 2 2006.173.02:52:09.04#ibcon#about to write, iclass 7, count 2 2006.173.02:52:09.04#ibcon#wrote, iclass 7, count 2 2006.173.02:52:09.04#ibcon#about to read 3, iclass 7, count 2 2006.173.02:52:09.07#ibcon#read 3, iclass 7, count 2 2006.173.02:52:09.07#ibcon#about to read 4, iclass 7, count 2 2006.173.02:52:09.07#ibcon#read 4, iclass 7, count 2 2006.173.02:52:09.07#ibcon#about to read 5, iclass 7, count 2 2006.173.02:52:09.07#ibcon#read 5, iclass 7, count 2 2006.173.02:52:09.07#ibcon#about to read 6, iclass 7, count 2 2006.173.02:52:09.07#ibcon#read 6, iclass 7, count 2 2006.173.02:52:09.07#ibcon#end of sib2, iclass 7, count 2 2006.173.02:52:09.07#ibcon#*after write, iclass 7, count 2 2006.173.02:52:09.07#ibcon#*before return 0, iclass 7, count 2 2006.173.02:52:09.07#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.02:52:09.07#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.173.02:52:09.07#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.173.02:52:09.07#ibcon#ireg 7 cls_cnt 0 2006.173.02:52:09.07#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.02:52:09.19#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.02:52:09.19#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.02:52:09.19#ibcon#enter wrdev, iclass 7, count 0 2006.173.02:52:09.19#ibcon#first serial, iclass 7, count 0 2006.173.02:52:09.19#ibcon#enter sib2, iclass 7, count 0 2006.173.02:52:09.19#ibcon#flushed, iclass 7, count 0 2006.173.02:52:09.19#ibcon#about to write, iclass 7, count 0 2006.173.02:52:09.19#ibcon#wrote, iclass 7, count 0 2006.173.02:52:09.19#ibcon#about to read 3, iclass 7, count 0 2006.173.02:52:09.21#ibcon#read 3, iclass 7, count 0 2006.173.02:52:09.21#ibcon#about to read 4, iclass 7, count 0 2006.173.02:52:09.21#ibcon#read 4, iclass 7, count 0 2006.173.02:52:09.21#ibcon#about to read 5, iclass 7, count 0 2006.173.02:52:09.21#ibcon#read 5, iclass 7, count 0 2006.173.02:52:09.21#ibcon#about to read 6, iclass 7, count 0 2006.173.02:52:09.21#ibcon#read 6, iclass 7, count 0 2006.173.02:52:09.21#ibcon#end of sib2, iclass 7, count 0 2006.173.02:52:09.21#ibcon#*mode == 0, iclass 7, count 0 2006.173.02:52:09.21#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.02:52:09.21#ibcon#[25=USB\r\n] 2006.173.02:52:09.21#ibcon#*before write, iclass 7, count 0 2006.173.02:52:09.21#ibcon#enter sib2, iclass 7, count 0 2006.173.02:52:09.21#ibcon#flushed, iclass 7, count 0 2006.173.02:52:09.21#ibcon#about to write, iclass 7, count 0 2006.173.02:52:09.21#ibcon#wrote, iclass 7, count 0 2006.173.02:52:09.21#ibcon#about to read 3, iclass 7, count 0 2006.173.02:52:09.24#ibcon#read 3, iclass 7, count 0 2006.173.02:52:09.24#ibcon#about to read 4, iclass 7, count 0 2006.173.02:52:09.24#ibcon#read 4, iclass 7, count 0 2006.173.02:52:09.24#ibcon#about to read 5, iclass 7, count 0 2006.173.02:52:09.24#ibcon#read 5, iclass 7, count 0 2006.173.02:52:09.24#ibcon#about to read 6, iclass 7, count 0 2006.173.02:52:09.24#ibcon#read 6, iclass 7, count 0 2006.173.02:52:09.24#ibcon#end of sib2, iclass 7, count 0 2006.173.02:52:09.24#ibcon#*after write, iclass 7, count 0 2006.173.02:52:09.24#ibcon#*before return 0, iclass 7, count 0 2006.173.02:52:09.24#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.02:52:09.24#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.173.02:52:09.24#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.02:52:09.24#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.02:52:09.24$vck44/valo=7,864.99 2006.173.02:52:09.24#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.02:52:09.24#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.02:52:09.24#ibcon#ireg 17 cls_cnt 0 2006.173.02:52:09.24#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.02:52:09.24#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.02:52:09.24#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.02:52:09.24#ibcon#enter wrdev, iclass 11, count 0 2006.173.02:52:09.24#ibcon#first serial, iclass 11, count 0 2006.173.02:52:09.24#ibcon#enter sib2, iclass 11, count 0 2006.173.02:52:09.24#ibcon#flushed, iclass 11, count 0 2006.173.02:52:09.24#ibcon#about to write, iclass 11, count 0 2006.173.02:52:09.24#ibcon#wrote, iclass 11, count 0 2006.173.02:52:09.24#ibcon#about to read 3, iclass 11, count 0 2006.173.02:52:09.26#ibcon#read 3, iclass 11, count 0 2006.173.02:52:09.26#ibcon#about to read 4, iclass 11, count 0 2006.173.02:52:09.26#ibcon#read 4, iclass 11, count 0 2006.173.02:52:09.26#ibcon#about to read 5, iclass 11, count 0 2006.173.02:52:09.26#ibcon#read 5, iclass 11, count 0 2006.173.02:52:09.26#ibcon#about to read 6, iclass 11, count 0 2006.173.02:52:09.26#ibcon#read 6, iclass 11, count 0 2006.173.02:52:09.26#ibcon#end of sib2, iclass 11, count 0 2006.173.02:52:09.26#ibcon#*mode == 0, iclass 11, count 0 2006.173.02:52:09.26#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.02:52:09.26#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.02:52:09.26#ibcon#*before write, iclass 11, count 0 2006.173.02:52:09.26#ibcon#enter sib2, iclass 11, count 0 2006.173.02:52:09.26#ibcon#flushed, iclass 11, count 0 2006.173.02:52:09.26#ibcon#about to write, iclass 11, count 0 2006.173.02:52:09.26#ibcon#wrote, iclass 11, count 0 2006.173.02:52:09.26#ibcon#about to read 3, iclass 11, count 0 2006.173.02:52:09.30#ibcon#read 3, iclass 11, count 0 2006.173.02:52:09.30#ibcon#about to read 4, iclass 11, count 0 2006.173.02:52:09.30#ibcon#read 4, iclass 11, count 0 2006.173.02:52:09.30#ibcon#about to read 5, iclass 11, count 0 2006.173.02:52:09.30#ibcon#read 5, iclass 11, count 0 2006.173.02:52:09.30#ibcon#about to read 6, iclass 11, count 0 2006.173.02:52:09.30#ibcon#read 6, iclass 11, count 0 2006.173.02:52:09.30#ibcon#end of sib2, iclass 11, count 0 2006.173.02:52:09.30#ibcon#*after write, iclass 11, count 0 2006.173.02:52:09.30#ibcon#*before return 0, iclass 11, count 0 2006.173.02:52:09.30#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.02:52:09.30#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.02:52:09.30#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.02:52:09.30#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.02:52:09.30$vck44/va=7,4 2006.173.02:52:09.30#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.173.02:52:09.30#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.173.02:52:09.30#ibcon#ireg 11 cls_cnt 2 2006.173.02:52:09.30#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.02:52:09.36#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.02:52:09.36#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.02:52:09.36#ibcon#enter wrdev, iclass 13, count 2 2006.173.02:52:09.36#ibcon#first serial, iclass 13, count 2 2006.173.02:52:09.36#ibcon#enter sib2, iclass 13, count 2 2006.173.02:52:09.36#ibcon#flushed, iclass 13, count 2 2006.173.02:52:09.36#ibcon#about to write, iclass 13, count 2 2006.173.02:52:09.36#ibcon#wrote, iclass 13, count 2 2006.173.02:52:09.36#ibcon#about to read 3, iclass 13, count 2 2006.173.02:52:09.38#ibcon#read 3, iclass 13, count 2 2006.173.02:52:09.38#ibcon#about to read 4, iclass 13, count 2 2006.173.02:52:09.38#ibcon#read 4, iclass 13, count 2 2006.173.02:52:09.38#ibcon#about to read 5, iclass 13, count 2 2006.173.02:52:09.38#ibcon#read 5, iclass 13, count 2 2006.173.02:52:09.38#ibcon#about to read 6, iclass 13, count 2 2006.173.02:52:09.38#ibcon#read 6, iclass 13, count 2 2006.173.02:52:09.38#ibcon#end of sib2, iclass 13, count 2 2006.173.02:52:09.38#ibcon#*mode == 0, iclass 13, count 2 2006.173.02:52:09.38#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.173.02:52:09.38#ibcon#[25=AT07-04\r\n] 2006.173.02:52:09.38#ibcon#*before write, iclass 13, count 2 2006.173.02:52:09.38#ibcon#enter sib2, iclass 13, count 2 2006.173.02:52:09.38#ibcon#flushed, iclass 13, count 2 2006.173.02:52:09.38#ibcon#about to write, iclass 13, count 2 2006.173.02:52:09.38#ibcon#wrote, iclass 13, count 2 2006.173.02:52:09.38#ibcon#about to read 3, iclass 13, count 2 2006.173.02:52:09.41#ibcon#read 3, iclass 13, count 2 2006.173.02:52:09.41#ibcon#about to read 4, iclass 13, count 2 2006.173.02:52:09.41#ibcon#read 4, iclass 13, count 2 2006.173.02:52:09.41#ibcon#about to read 5, iclass 13, count 2 2006.173.02:52:09.41#ibcon#read 5, iclass 13, count 2 2006.173.02:52:09.41#ibcon#about to read 6, iclass 13, count 2 2006.173.02:52:09.41#ibcon#read 6, iclass 13, count 2 2006.173.02:52:09.41#ibcon#end of sib2, iclass 13, count 2 2006.173.02:52:09.41#ibcon#*after write, iclass 13, count 2 2006.173.02:52:09.41#ibcon#*before return 0, iclass 13, count 2 2006.173.02:52:09.41#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.02:52:09.41#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.173.02:52:09.41#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.173.02:52:09.41#ibcon#ireg 7 cls_cnt 0 2006.173.02:52:09.41#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.02:52:09.55#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.02:52:09.55#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.02:52:09.55#ibcon#enter wrdev, iclass 13, count 0 2006.173.02:52:09.55#ibcon#first serial, iclass 13, count 0 2006.173.02:52:09.55#ibcon#enter sib2, iclass 13, count 0 2006.173.02:52:09.55#ibcon#flushed, iclass 13, count 0 2006.173.02:52:09.55#ibcon#about to write, iclass 13, count 0 2006.173.02:52:09.55#ibcon#wrote, iclass 13, count 0 2006.173.02:52:09.55#ibcon#about to read 3, iclass 13, count 0 2006.173.02:52:09.56#ibcon#read 3, iclass 13, count 0 2006.173.02:52:09.56#ibcon#about to read 4, iclass 13, count 0 2006.173.02:52:09.56#ibcon#read 4, iclass 13, count 0 2006.173.02:52:09.56#ibcon#about to read 5, iclass 13, count 0 2006.173.02:52:09.56#ibcon#read 5, iclass 13, count 0 2006.173.02:52:09.56#ibcon#about to read 6, iclass 13, count 0 2006.173.02:52:09.56#ibcon#read 6, iclass 13, count 0 2006.173.02:52:09.56#ibcon#end of sib2, iclass 13, count 0 2006.173.02:52:09.56#ibcon#*mode == 0, iclass 13, count 0 2006.173.02:52:09.56#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.02:52:09.56#ibcon#[25=USB\r\n] 2006.173.02:52:09.56#ibcon#*before write, iclass 13, count 0 2006.173.02:52:09.56#ibcon#enter sib2, iclass 13, count 0 2006.173.02:52:09.56#ibcon#flushed, iclass 13, count 0 2006.173.02:52:09.56#ibcon#about to write, iclass 13, count 0 2006.173.02:52:09.56#ibcon#wrote, iclass 13, count 0 2006.173.02:52:09.56#ibcon#about to read 3, iclass 13, count 0 2006.173.02:52:09.59#ibcon#read 3, iclass 13, count 0 2006.173.02:52:09.59#ibcon#about to read 4, iclass 13, count 0 2006.173.02:52:09.59#ibcon#read 4, iclass 13, count 0 2006.173.02:52:09.59#ibcon#about to read 5, iclass 13, count 0 2006.173.02:52:09.59#ibcon#read 5, iclass 13, count 0 2006.173.02:52:09.59#ibcon#about to read 6, iclass 13, count 0 2006.173.02:52:09.59#ibcon#read 6, iclass 13, count 0 2006.173.02:52:09.59#ibcon#end of sib2, iclass 13, count 0 2006.173.02:52:09.59#ibcon#*after write, iclass 13, count 0 2006.173.02:52:09.59#ibcon#*before return 0, iclass 13, count 0 2006.173.02:52:09.59#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.02:52:09.59#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.173.02:52:09.59#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.02:52:09.59#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.02:52:09.59$vck44/valo=8,884.99 2006.173.02:52:09.59#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.02:52:09.59#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.02:52:09.59#ibcon#ireg 17 cls_cnt 0 2006.173.02:52:09.59#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.02:52:09.59#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.02:52:09.59#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.02:52:09.59#ibcon#enter wrdev, iclass 15, count 0 2006.173.02:52:09.59#ibcon#first serial, iclass 15, count 0 2006.173.02:52:09.59#ibcon#enter sib2, iclass 15, count 0 2006.173.02:52:09.59#ibcon#flushed, iclass 15, count 0 2006.173.02:52:09.59#ibcon#about to write, iclass 15, count 0 2006.173.02:52:09.59#ibcon#wrote, iclass 15, count 0 2006.173.02:52:09.59#ibcon#about to read 3, iclass 15, count 0 2006.173.02:52:09.61#ibcon#read 3, iclass 15, count 0 2006.173.02:52:09.61#ibcon#about to read 4, iclass 15, count 0 2006.173.02:52:09.61#ibcon#read 4, iclass 15, count 0 2006.173.02:52:09.61#ibcon#about to read 5, iclass 15, count 0 2006.173.02:52:09.61#ibcon#read 5, iclass 15, count 0 2006.173.02:52:09.61#ibcon#about to read 6, iclass 15, count 0 2006.173.02:52:09.61#ibcon#read 6, iclass 15, count 0 2006.173.02:52:09.61#ibcon#end of sib2, iclass 15, count 0 2006.173.02:52:09.61#ibcon#*mode == 0, iclass 15, count 0 2006.173.02:52:09.61#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.02:52:09.61#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.02:52:09.61#ibcon#*before write, iclass 15, count 0 2006.173.02:52:09.61#ibcon#enter sib2, iclass 15, count 0 2006.173.02:52:09.61#ibcon#flushed, iclass 15, count 0 2006.173.02:52:09.61#ibcon#about to write, iclass 15, count 0 2006.173.02:52:09.61#ibcon#wrote, iclass 15, count 0 2006.173.02:52:09.61#ibcon#about to read 3, iclass 15, count 0 2006.173.02:52:09.65#ibcon#read 3, iclass 15, count 0 2006.173.02:52:09.65#ibcon#about to read 4, iclass 15, count 0 2006.173.02:52:09.65#ibcon#read 4, iclass 15, count 0 2006.173.02:52:09.65#ibcon#about to read 5, iclass 15, count 0 2006.173.02:52:09.65#ibcon#read 5, iclass 15, count 0 2006.173.02:52:09.65#ibcon#about to read 6, iclass 15, count 0 2006.173.02:52:09.65#ibcon#read 6, iclass 15, count 0 2006.173.02:52:09.65#ibcon#end of sib2, iclass 15, count 0 2006.173.02:52:09.65#ibcon#*after write, iclass 15, count 0 2006.173.02:52:09.65#ibcon#*before return 0, iclass 15, count 0 2006.173.02:52:09.65#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.02:52:09.65#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.02:52:09.65#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.02:52:09.65#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.02:52:09.65$vck44/va=8,4 2006.173.02:52:09.65#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.02:52:09.65#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.02:52:09.65#ibcon#ireg 11 cls_cnt 2 2006.173.02:52:09.65#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.02:52:09.71#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.02:52:09.71#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.02:52:09.71#ibcon#enter wrdev, iclass 17, count 2 2006.173.02:52:09.71#ibcon#first serial, iclass 17, count 2 2006.173.02:52:09.71#ibcon#enter sib2, iclass 17, count 2 2006.173.02:52:09.71#ibcon#flushed, iclass 17, count 2 2006.173.02:52:09.71#ibcon#about to write, iclass 17, count 2 2006.173.02:52:09.71#ibcon#wrote, iclass 17, count 2 2006.173.02:52:09.71#ibcon#about to read 3, iclass 17, count 2 2006.173.02:52:09.73#ibcon#read 3, iclass 17, count 2 2006.173.02:52:09.73#ibcon#about to read 4, iclass 17, count 2 2006.173.02:52:09.73#ibcon#read 4, iclass 17, count 2 2006.173.02:52:09.73#ibcon#about to read 5, iclass 17, count 2 2006.173.02:52:09.73#ibcon#read 5, iclass 17, count 2 2006.173.02:52:09.73#ibcon#about to read 6, iclass 17, count 2 2006.173.02:52:09.73#ibcon#read 6, iclass 17, count 2 2006.173.02:52:09.73#ibcon#end of sib2, iclass 17, count 2 2006.173.02:52:09.73#ibcon#*mode == 0, iclass 17, count 2 2006.173.02:52:09.73#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.02:52:09.73#ibcon#[25=AT08-04\r\n] 2006.173.02:52:09.73#ibcon#*before write, iclass 17, count 2 2006.173.02:52:09.73#ibcon#enter sib2, iclass 17, count 2 2006.173.02:52:09.73#ibcon#flushed, iclass 17, count 2 2006.173.02:52:09.73#ibcon#about to write, iclass 17, count 2 2006.173.02:52:09.73#ibcon#wrote, iclass 17, count 2 2006.173.02:52:09.73#ibcon#about to read 3, iclass 17, count 2 2006.173.02:52:09.76#ibcon#read 3, iclass 17, count 2 2006.173.02:52:09.76#ibcon#about to read 4, iclass 17, count 2 2006.173.02:52:09.76#ibcon#read 4, iclass 17, count 2 2006.173.02:52:09.76#ibcon#about to read 5, iclass 17, count 2 2006.173.02:52:09.76#ibcon#read 5, iclass 17, count 2 2006.173.02:52:09.76#ibcon#about to read 6, iclass 17, count 2 2006.173.02:52:09.76#ibcon#read 6, iclass 17, count 2 2006.173.02:52:09.76#ibcon#end of sib2, iclass 17, count 2 2006.173.02:52:09.76#ibcon#*after write, iclass 17, count 2 2006.173.02:52:09.76#ibcon#*before return 0, iclass 17, count 2 2006.173.02:52:09.76#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.02:52:09.76#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.02:52:09.76#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.02:52:09.76#ibcon#ireg 7 cls_cnt 0 2006.173.02:52:09.76#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.02:52:09.88#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.02:52:09.88#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.02:52:09.88#ibcon#enter wrdev, iclass 17, count 0 2006.173.02:52:09.88#ibcon#first serial, iclass 17, count 0 2006.173.02:52:09.88#ibcon#enter sib2, iclass 17, count 0 2006.173.02:52:09.88#ibcon#flushed, iclass 17, count 0 2006.173.02:52:09.88#ibcon#about to write, iclass 17, count 0 2006.173.02:52:09.88#ibcon#wrote, iclass 17, count 0 2006.173.02:52:09.88#ibcon#about to read 3, iclass 17, count 0 2006.173.02:52:09.90#ibcon#read 3, iclass 17, count 0 2006.173.02:52:09.90#ibcon#about to read 4, iclass 17, count 0 2006.173.02:52:09.90#ibcon#read 4, iclass 17, count 0 2006.173.02:52:09.90#ibcon#about to read 5, iclass 17, count 0 2006.173.02:52:09.90#ibcon#read 5, iclass 17, count 0 2006.173.02:52:09.90#ibcon#about to read 6, iclass 17, count 0 2006.173.02:52:09.90#ibcon#read 6, iclass 17, count 0 2006.173.02:52:09.90#ibcon#end of sib2, iclass 17, count 0 2006.173.02:52:09.90#ibcon#*mode == 0, iclass 17, count 0 2006.173.02:52:09.90#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.02:52:09.90#ibcon#[25=USB\r\n] 2006.173.02:52:09.90#ibcon#*before write, iclass 17, count 0 2006.173.02:52:09.90#ibcon#enter sib2, iclass 17, count 0 2006.173.02:52:09.90#ibcon#flushed, iclass 17, count 0 2006.173.02:52:09.90#ibcon#about to write, iclass 17, count 0 2006.173.02:52:09.90#ibcon#wrote, iclass 17, count 0 2006.173.02:52:09.90#ibcon#about to read 3, iclass 17, count 0 2006.173.02:52:09.93#ibcon#read 3, iclass 17, count 0 2006.173.02:52:09.93#ibcon#about to read 4, iclass 17, count 0 2006.173.02:52:09.93#ibcon#read 4, iclass 17, count 0 2006.173.02:52:09.93#ibcon#about to read 5, iclass 17, count 0 2006.173.02:52:09.93#ibcon#read 5, iclass 17, count 0 2006.173.02:52:09.93#ibcon#about to read 6, iclass 17, count 0 2006.173.02:52:09.93#ibcon#read 6, iclass 17, count 0 2006.173.02:52:09.93#ibcon#end of sib2, iclass 17, count 0 2006.173.02:52:09.93#ibcon#*after write, iclass 17, count 0 2006.173.02:52:09.93#ibcon#*before return 0, iclass 17, count 0 2006.173.02:52:09.93#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.02:52:09.93#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.02:52:09.93#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.02:52:09.93#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.02:52:09.93$vck44/vblo=1,629.99 2006.173.02:52:09.93#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.02:52:09.93#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.02:52:09.93#ibcon#ireg 17 cls_cnt 0 2006.173.02:52:09.93#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.02:52:09.93#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.02:52:09.93#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.02:52:09.93#ibcon#enter wrdev, iclass 19, count 0 2006.173.02:52:09.93#ibcon#first serial, iclass 19, count 0 2006.173.02:52:09.93#ibcon#enter sib2, iclass 19, count 0 2006.173.02:52:09.93#ibcon#flushed, iclass 19, count 0 2006.173.02:52:09.93#ibcon#about to write, iclass 19, count 0 2006.173.02:52:09.93#ibcon#wrote, iclass 19, count 0 2006.173.02:52:09.93#ibcon#about to read 3, iclass 19, count 0 2006.173.02:52:09.95#ibcon#read 3, iclass 19, count 0 2006.173.02:52:09.95#ibcon#about to read 4, iclass 19, count 0 2006.173.02:52:09.95#ibcon#read 4, iclass 19, count 0 2006.173.02:52:09.95#ibcon#about to read 5, iclass 19, count 0 2006.173.02:52:09.95#ibcon#read 5, iclass 19, count 0 2006.173.02:52:09.95#ibcon#about to read 6, iclass 19, count 0 2006.173.02:52:09.95#ibcon#read 6, iclass 19, count 0 2006.173.02:52:09.95#ibcon#end of sib2, iclass 19, count 0 2006.173.02:52:09.95#ibcon#*mode == 0, iclass 19, count 0 2006.173.02:52:09.95#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.02:52:09.95#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.02:52:09.95#ibcon#*before write, iclass 19, count 0 2006.173.02:52:09.95#ibcon#enter sib2, iclass 19, count 0 2006.173.02:52:09.95#ibcon#flushed, iclass 19, count 0 2006.173.02:52:09.95#ibcon#about to write, iclass 19, count 0 2006.173.02:52:09.95#ibcon#wrote, iclass 19, count 0 2006.173.02:52:09.95#ibcon#about to read 3, iclass 19, count 0 2006.173.02:52:09.99#ibcon#read 3, iclass 19, count 0 2006.173.02:52:09.99#ibcon#about to read 4, iclass 19, count 0 2006.173.02:52:09.99#ibcon#read 4, iclass 19, count 0 2006.173.02:52:09.99#ibcon#about to read 5, iclass 19, count 0 2006.173.02:52:09.99#ibcon#read 5, iclass 19, count 0 2006.173.02:52:09.99#ibcon#about to read 6, iclass 19, count 0 2006.173.02:52:09.99#ibcon#read 6, iclass 19, count 0 2006.173.02:52:09.99#ibcon#end of sib2, iclass 19, count 0 2006.173.02:52:09.99#ibcon#*after write, iclass 19, count 0 2006.173.02:52:09.99#ibcon#*before return 0, iclass 19, count 0 2006.173.02:52:09.99#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.02:52:09.99#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.02:52:09.99#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.02:52:09.99#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.02:52:09.99$vck44/vb=1,4 2006.173.02:52:09.99#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.02:52:09.99#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.02:52:09.99#ibcon#ireg 11 cls_cnt 2 2006.173.02:52:09.99#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.02:52:09.99#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.02:52:09.99#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.02:52:09.99#ibcon#enter wrdev, iclass 21, count 2 2006.173.02:52:09.99#ibcon#first serial, iclass 21, count 2 2006.173.02:52:09.99#ibcon#enter sib2, iclass 21, count 2 2006.173.02:52:09.99#ibcon#flushed, iclass 21, count 2 2006.173.02:52:09.99#ibcon#about to write, iclass 21, count 2 2006.173.02:52:09.99#ibcon#wrote, iclass 21, count 2 2006.173.02:52:09.99#ibcon#about to read 3, iclass 21, count 2 2006.173.02:52:10.01#ibcon#read 3, iclass 21, count 2 2006.173.02:52:10.01#ibcon#about to read 4, iclass 21, count 2 2006.173.02:52:10.01#ibcon#read 4, iclass 21, count 2 2006.173.02:52:10.01#ibcon#about to read 5, iclass 21, count 2 2006.173.02:52:10.01#ibcon#read 5, iclass 21, count 2 2006.173.02:52:10.01#ibcon#about to read 6, iclass 21, count 2 2006.173.02:52:10.01#ibcon#read 6, iclass 21, count 2 2006.173.02:52:10.01#ibcon#end of sib2, iclass 21, count 2 2006.173.02:52:10.01#ibcon#*mode == 0, iclass 21, count 2 2006.173.02:52:10.01#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.02:52:10.01#ibcon#[27=AT01-04\r\n] 2006.173.02:52:10.01#ibcon#*before write, iclass 21, count 2 2006.173.02:52:10.01#ibcon#enter sib2, iclass 21, count 2 2006.173.02:52:10.01#ibcon#flushed, iclass 21, count 2 2006.173.02:52:10.01#ibcon#about to write, iclass 21, count 2 2006.173.02:52:10.01#ibcon#wrote, iclass 21, count 2 2006.173.02:52:10.01#ibcon#about to read 3, iclass 21, count 2 2006.173.02:52:10.04#ibcon#read 3, iclass 21, count 2 2006.173.02:52:10.04#ibcon#about to read 4, iclass 21, count 2 2006.173.02:52:10.04#ibcon#read 4, iclass 21, count 2 2006.173.02:52:10.04#ibcon#about to read 5, iclass 21, count 2 2006.173.02:52:10.04#ibcon#read 5, iclass 21, count 2 2006.173.02:52:10.04#ibcon#about to read 6, iclass 21, count 2 2006.173.02:52:10.04#ibcon#read 6, iclass 21, count 2 2006.173.02:52:10.04#ibcon#end of sib2, iclass 21, count 2 2006.173.02:52:10.04#ibcon#*after write, iclass 21, count 2 2006.173.02:52:10.04#ibcon#*before return 0, iclass 21, count 2 2006.173.02:52:10.04#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.02:52:10.04#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.02:52:10.04#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.02:52:10.04#ibcon#ireg 7 cls_cnt 0 2006.173.02:52:10.04#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.02:52:10.16#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.02:52:10.16#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.02:52:10.16#ibcon#enter wrdev, iclass 21, count 0 2006.173.02:52:10.16#ibcon#first serial, iclass 21, count 0 2006.173.02:52:10.16#ibcon#enter sib2, iclass 21, count 0 2006.173.02:52:10.16#ibcon#flushed, iclass 21, count 0 2006.173.02:52:10.16#ibcon#about to write, iclass 21, count 0 2006.173.02:52:10.16#ibcon#wrote, iclass 21, count 0 2006.173.02:52:10.16#ibcon#about to read 3, iclass 21, count 0 2006.173.02:52:10.18#ibcon#read 3, iclass 21, count 0 2006.173.02:52:10.18#ibcon#about to read 4, iclass 21, count 0 2006.173.02:52:10.18#ibcon#read 4, iclass 21, count 0 2006.173.02:52:10.18#ibcon#about to read 5, iclass 21, count 0 2006.173.02:52:10.18#ibcon#read 5, iclass 21, count 0 2006.173.02:52:10.18#ibcon#about to read 6, iclass 21, count 0 2006.173.02:52:10.18#ibcon#read 6, iclass 21, count 0 2006.173.02:52:10.18#ibcon#end of sib2, iclass 21, count 0 2006.173.02:52:10.18#ibcon#*mode == 0, iclass 21, count 0 2006.173.02:52:10.18#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.02:52:10.18#ibcon#[27=USB\r\n] 2006.173.02:52:10.18#ibcon#*before write, iclass 21, count 0 2006.173.02:52:10.18#ibcon#enter sib2, iclass 21, count 0 2006.173.02:52:10.18#ibcon#flushed, iclass 21, count 0 2006.173.02:52:10.18#ibcon#about to write, iclass 21, count 0 2006.173.02:52:10.18#ibcon#wrote, iclass 21, count 0 2006.173.02:52:10.18#ibcon#about to read 3, iclass 21, count 0 2006.173.02:52:10.21#ibcon#read 3, iclass 21, count 0 2006.173.02:52:10.21#ibcon#about to read 4, iclass 21, count 0 2006.173.02:52:10.21#ibcon#read 4, iclass 21, count 0 2006.173.02:52:10.21#ibcon#about to read 5, iclass 21, count 0 2006.173.02:52:10.21#ibcon#read 5, iclass 21, count 0 2006.173.02:52:10.21#ibcon#about to read 6, iclass 21, count 0 2006.173.02:52:10.21#ibcon#read 6, iclass 21, count 0 2006.173.02:52:10.21#ibcon#end of sib2, iclass 21, count 0 2006.173.02:52:10.21#ibcon#*after write, iclass 21, count 0 2006.173.02:52:10.21#ibcon#*before return 0, iclass 21, count 0 2006.173.02:52:10.21#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.02:52:10.21#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.02:52:10.21#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.02:52:10.21#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.02:52:10.21$vck44/vblo=2,634.99 2006.173.02:52:10.21#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.02:52:10.21#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.02:52:10.21#ibcon#ireg 17 cls_cnt 0 2006.173.02:52:10.21#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.02:52:10.21#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.02:52:10.21#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.02:52:10.21#ibcon#enter wrdev, iclass 23, count 0 2006.173.02:52:10.21#ibcon#first serial, iclass 23, count 0 2006.173.02:52:10.21#ibcon#enter sib2, iclass 23, count 0 2006.173.02:52:10.21#ibcon#flushed, iclass 23, count 0 2006.173.02:52:10.21#ibcon#about to write, iclass 23, count 0 2006.173.02:52:10.21#ibcon#wrote, iclass 23, count 0 2006.173.02:52:10.21#ibcon#about to read 3, iclass 23, count 0 2006.173.02:52:10.23#ibcon#read 3, iclass 23, count 0 2006.173.02:52:10.23#ibcon#about to read 4, iclass 23, count 0 2006.173.02:52:10.23#ibcon#read 4, iclass 23, count 0 2006.173.02:52:10.23#ibcon#about to read 5, iclass 23, count 0 2006.173.02:52:10.23#ibcon#read 5, iclass 23, count 0 2006.173.02:52:10.23#ibcon#about to read 6, iclass 23, count 0 2006.173.02:52:10.23#ibcon#read 6, iclass 23, count 0 2006.173.02:52:10.23#ibcon#end of sib2, iclass 23, count 0 2006.173.02:52:10.23#ibcon#*mode == 0, iclass 23, count 0 2006.173.02:52:10.23#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.02:52:10.23#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.02:52:10.23#ibcon#*before write, iclass 23, count 0 2006.173.02:52:10.23#ibcon#enter sib2, iclass 23, count 0 2006.173.02:52:10.23#ibcon#flushed, iclass 23, count 0 2006.173.02:52:10.23#ibcon#about to write, iclass 23, count 0 2006.173.02:52:10.23#ibcon#wrote, iclass 23, count 0 2006.173.02:52:10.23#ibcon#about to read 3, iclass 23, count 0 2006.173.02:52:10.27#ibcon#read 3, iclass 23, count 0 2006.173.02:52:10.27#ibcon#about to read 4, iclass 23, count 0 2006.173.02:52:10.27#ibcon#read 4, iclass 23, count 0 2006.173.02:52:10.27#ibcon#about to read 5, iclass 23, count 0 2006.173.02:52:10.27#ibcon#read 5, iclass 23, count 0 2006.173.02:52:10.27#ibcon#about to read 6, iclass 23, count 0 2006.173.02:52:10.27#ibcon#read 6, iclass 23, count 0 2006.173.02:52:10.27#ibcon#end of sib2, iclass 23, count 0 2006.173.02:52:10.27#ibcon#*after write, iclass 23, count 0 2006.173.02:52:10.27#ibcon#*before return 0, iclass 23, count 0 2006.173.02:52:10.27#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.02:52:10.27#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.02:52:10.27#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.02:52:10.27#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.02:52:10.27$vck44/vb=2,4 2006.173.02:52:10.27#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.02:52:10.27#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.02:52:10.27#ibcon#ireg 11 cls_cnt 2 2006.173.02:52:10.27#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.02:52:10.33#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.02:52:10.33#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.02:52:10.33#ibcon#enter wrdev, iclass 25, count 2 2006.173.02:52:10.33#ibcon#first serial, iclass 25, count 2 2006.173.02:52:10.33#ibcon#enter sib2, iclass 25, count 2 2006.173.02:52:10.33#ibcon#flushed, iclass 25, count 2 2006.173.02:52:10.33#ibcon#about to write, iclass 25, count 2 2006.173.02:52:10.33#ibcon#wrote, iclass 25, count 2 2006.173.02:52:10.33#ibcon#about to read 3, iclass 25, count 2 2006.173.02:52:10.35#ibcon#read 3, iclass 25, count 2 2006.173.02:52:10.35#ibcon#about to read 4, iclass 25, count 2 2006.173.02:52:10.35#ibcon#read 4, iclass 25, count 2 2006.173.02:52:10.35#ibcon#about to read 5, iclass 25, count 2 2006.173.02:52:10.35#ibcon#read 5, iclass 25, count 2 2006.173.02:52:10.35#ibcon#about to read 6, iclass 25, count 2 2006.173.02:52:10.35#ibcon#read 6, iclass 25, count 2 2006.173.02:52:10.35#ibcon#end of sib2, iclass 25, count 2 2006.173.02:52:10.35#ibcon#*mode == 0, iclass 25, count 2 2006.173.02:52:10.35#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.02:52:10.35#ibcon#[27=AT02-04\r\n] 2006.173.02:52:10.35#ibcon#*before write, iclass 25, count 2 2006.173.02:52:10.35#ibcon#enter sib2, iclass 25, count 2 2006.173.02:52:10.35#ibcon#flushed, iclass 25, count 2 2006.173.02:52:10.35#ibcon#about to write, iclass 25, count 2 2006.173.02:52:10.35#ibcon#wrote, iclass 25, count 2 2006.173.02:52:10.35#ibcon#about to read 3, iclass 25, count 2 2006.173.02:52:10.38#ibcon#read 3, iclass 25, count 2 2006.173.02:52:10.38#ibcon#about to read 4, iclass 25, count 2 2006.173.02:52:10.38#ibcon#read 4, iclass 25, count 2 2006.173.02:52:10.38#ibcon#about to read 5, iclass 25, count 2 2006.173.02:52:10.38#ibcon#read 5, iclass 25, count 2 2006.173.02:52:10.38#ibcon#about to read 6, iclass 25, count 2 2006.173.02:52:10.38#ibcon#read 6, iclass 25, count 2 2006.173.02:52:10.38#ibcon#end of sib2, iclass 25, count 2 2006.173.02:52:10.38#ibcon#*after write, iclass 25, count 2 2006.173.02:52:10.38#ibcon#*before return 0, iclass 25, count 2 2006.173.02:52:10.38#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.02:52:10.38#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.02:52:10.38#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.02:52:10.38#ibcon#ireg 7 cls_cnt 0 2006.173.02:52:10.38#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.02:52:10.50#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.02:52:10.50#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.02:52:10.50#ibcon#enter wrdev, iclass 25, count 0 2006.173.02:52:10.50#ibcon#first serial, iclass 25, count 0 2006.173.02:52:10.50#ibcon#enter sib2, iclass 25, count 0 2006.173.02:52:10.50#ibcon#flushed, iclass 25, count 0 2006.173.02:52:10.50#ibcon#about to write, iclass 25, count 0 2006.173.02:52:10.50#ibcon#wrote, iclass 25, count 0 2006.173.02:52:10.50#ibcon#about to read 3, iclass 25, count 0 2006.173.02:52:10.52#ibcon#read 3, iclass 25, count 0 2006.173.02:52:10.52#ibcon#about to read 4, iclass 25, count 0 2006.173.02:52:10.52#ibcon#read 4, iclass 25, count 0 2006.173.02:52:10.52#ibcon#about to read 5, iclass 25, count 0 2006.173.02:52:10.52#ibcon#read 5, iclass 25, count 0 2006.173.02:52:10.52#ibcon#about to read 6, iclass 25, count 0 2006.173.02:52:10.52#ibcon#read 6, iclass 25, count 0 2006.173.02:52:10.52#ibcon#end of sib2, iclass 25, count 0 2006.173.02:52:10.52#ibcon#*mode == 0, iclass 25, count 0 2006.173.02:52:10.52#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.02:52:10.52#ibcon#[27=USB\r\n] 2006.173.02:52:10.52#ibcon#*before write, iclass 25, count 0 2006.173.02:52:10.52#ibcon#enter sib2, iclass 25, count 0 2006.173.02:52:10.52#ibcon#flushed, iclass 25, count 0 2006.173.02:52:10.52#ibcon#about to write, iclass 25, count 0 2006.173.02:52:10.52#ibcon#wrote, iclass 25, count 0 2006.173.02:52:10.52#ibcon#about to read 3, iclass 25, count 0 2006.173.02:52:10.55#ibcon#read 3, iclass 25, count 0 2006.173.02:52:10.55#ibcon#about to read 4, iclass 25, count 0 2006.173.02:52:10.55#ibcon#read 4, iclass 25, count 0 2006.173.02:52:10.55#ibcon#about to read 5, iclass 25, count 0 2006.173.02:52:10.55#ibcon#read 5, iclass 25, count 0 2006.173.02:52:10.55#ibcon#about to read 6, iclass 25, count 0 2006.173.02:52:10.55#ibcon#read 6, iclass 25, count 0 2006.173.02:52:10.55#ibcon#end of sib2, iclass 25, count 0 2006.173.02:52:10.55#ibcon#*after write, iclass 25, count 0 2006.173.02:52:10.55#ibcon#*before return 0, iclass 25, count 0 2006.173.02:52:10.55#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.02:52:10.55#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.02:52:10.55#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.02:52:10.55#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.02:52:10.55$vck44/vblo=3,649.99 2006.173.02:52:10.55#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.02:52:10.55#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.02:52:10.55#ibcon#ireg 17 cls_cnt 0 2006.173.02:52:10.55#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.02:52:10.55#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.02:52:10.55#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.02:52:10.55#ibcon#enter wrdev, iclass 27, count 0 2006.173.02:52:10.55#ibcon#first serial, iclass 27, count 0 2006.173.02:52:10.55#ibcon#enter sib2, iclass 27, count 0 2006.173.02:52:10.55#ibcon#flushed, iclass 27, count 0 2006.173.02:52:10.55#ibcon#about to write, iclass 27, count 0 2006.173.02:52:10.55#ibcon#wrote, iclass 27, count 0 2006.173.02:52:10.55#ibcon#about to read 3, iclass 27, count 0 2006.173.02:52:10.57#ibcon#read 3, iclass 27, count 0 2006.173.02:52:10.57#ibcon#about to read 4, iclass 27, count 0 2006.173.02:52:10.57#ibcon#read 4, iclass 27, count 0 2006.173.02:52:10.57#ibcon#about to read 5, iclass 27, count 0 2006.173.02:52:10.57#ibcon#read 5, iclass 27, count 0 2006.173.02:52:10.57#ibcon#about to read 6, iclass 27, count 0 2006.173.02:52:10.57#ibcon#read 6, iclass 27, count 0 2006.173.02:52:10.57#ibcon#end of sib2, iclass 27, count 0 2006.173.02:52:10.57#ibcon#*mode == 0, iclass 27, count 0 2006.173.02:52:10.57#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.02:52:10.57#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.02:52:10.57#ibcon#*before write, iclass 27, count 0 2006.173.02:52:10.57#ibcon#enter sib2, iclass 27, count 0 2006.173.02:52:10.57#ibcon#flushed, iclass 27, count 0 2006.173.02:52:10.57#ibcon#about to write, iclass 27, count 0 2006.173.02:52:10.57#ibcon#wrote, iclass 27, count 0 2006.173.02:52:10.57#ibcon#about to read 3, iclass 27, count 0 2006.173.02:52:10.61#ibcon#read 3, iclass 27, count 0 2006.173.02:52:10.61#ibcon#about to read 4, iclass 27, count 0 2006.173.02:52:10.61#ibcon#read 4, iclass 27, count 0 2006.173.02:52:10.61#ibcon#about to read 5, iclass 27, count 0 2006.173.02:52:10.61#ibcon#read 5, iclass 27, count 0 2006.173.02:52:10.61#ibcon#about to read 6, iclass 27, count 0 2006.173.02:52:10.61#ibcon#read 6, iclass 27, count 0 2006.173.02:52:10.61#ibcon#end of sib2, iclass 27, count 0 2006.173.02:52:10.61#ibcon#*after write, iclass 27, count 0 2006.173.02:52:10.61#ibcon#*before return 0, iclass 27, count 0 2006.173.02:52:10.61#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.02:52:10.61#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.02:52:10.61#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.02:52:10.61#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.02:52:10.61$vck44/vb=3,4 2006.173.02:52:10.61#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.02:52:10.61#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.02:52:10.61#ibcon#ireg 11 cls_cnt 2 2006.173.02:52:10.61#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.02:52:10.67#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.02:52:10.67#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.02:52:10.67#ibcon#enter wrdev, iclass 29, count 2 2006.173.02:52:10.67#ibcon#first serial, iclass 29, count 2 2006.173.02:52:10.67#ibcon#enter sib2, iclass 29, count 2 2006.173.02:52:10.67#ibcon#flushed, iclass 29, count 2 2006.173.02:52:10.67#ibcon#about to write, iclass 29, count 2 2006.173.02:52:10.67#ibcon#wrote, iclass 29, count 2 2006.173.02:52:10.67#ibcon#about to read 3, iclass 29, count 2 2006.173.02:52:10.69#ibcon#read 3, iclass 29, count 2 2006.173.02:52:10.69#ibcon#about to read 4, iclass 29, count 2 2006.173.02:52:10.69#ibcon#read 4, iclass 29, count 2 2006.173.02:52:10.69#ibcon#about to read 5, iclass 29, count 2 2006.173.02:52:10.69#ibcon#read 5, iclass 29, count 2 2006.173.02:52:10.69#ibcon#about to read 6, iclass 29, count 2 2006.173.02:52:10.69#ibcon#read 6, iclass 29, count 2 2006.173.02:52:10.69#ibcon#end of sib2, iclass 29, count 2 2006.173.02:52:10.69#ibcon#*mode == 0, iclass 29, count 2 2006.173.02:52:10.69#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.02:52:10.69#ibcon#[27=AT03-04\r\n] 2006.173.02:52:10.69#ibcon#*before write, iclass 29, count 2 2006.173.02:52:10.69#ibcon#enter sib2, iclass 29, count 2 2006.173.02:52:10.69#ibcon#flushed, iclass 29, count 2 2006.173.02:52:10.69#ibcon#about to write, iclass 29, count 2 2006.173.02:52:10.69#ibcon#wrote, iclass 29, count 2 2006.173.02:52:10.69#ibcon#about to read 3, iclass 29, count 2 2006.173.02:52:10.72#ibcon#read 3, iclass 29, count 2 2006.173.02:52:10.72#ibcon#about to read 4, iclass 29, count 2 2006.173.02:52:10.72#ibcon#read 4, iclass 29, count 2 2006.173.02:52:10.72#ibcon#about to read 5, iclass 29, count 2 2006.173.02:52:10.72#ibcon#read 5, iclass 29, count 2 2006.173.02:52:10.72#ibcon#about to read 6, iclass 29, count 2 2006.173.02:52:10.72#ibcon#read 6, iclass 29, count 2 2006.173.02:52:10.72#ibcon#end of sib2, iclass 29, count 2 2006.173.02:52:10.72#ibcon#*after write, iclass 29, count 2 2006.173.02:52:10.72#ibcon#*before return 0, iclass 29, count 2 2006.173.02:52:10.72#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.02:52:10.72#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.02:52:10.72#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.02:52:10.72#ibcon#ireg 7 cls_cnt 0 2006.173.02:52:10.72#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.02:52:10.84#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.02:52:10.84#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.02:52:10.84#ibcon#enter wrdev, iclass 29, count 0 2006.173.02:52:10.84#ibcon#first serial, iclass 29, count 0 2006.173.02:52:10.84#ibcon#enter sib2, iclass 29, count 0 2006.173.02:52:10.84#ibcon#flushed, iclass 29, count 0 2006.173.02:52:10.84#ibcon#about to write, iclass 29, count 0 2006.173.02:52:10.84#ibcon#wrote, iclass 29, count 0 2006.173.02:52:10.84#ibcon#about to read 3, iclass 29, count 0 2006.173.02:52:10.86#ibcon#read 3, iclass 29, count 0 2006.173.02:52:10.86#ibcon#about to read 4, iclass 29, count 0 2006.173.02:52:10.86#ibcon#read 4, iclass 29, count 0 2006.173.02:52:10.86#ibcon#about to read 5, iclass 29, count 0 2006.173.02:52:10.86#ibcon#read 5, iclass 29, count 0 2006.173.02:52:10.86#ibcon#about to read 6, iclass 29, count 0 2006.173.02:52:10.86#ibcon#read 6, iclass 29, count 0 2006.173.02:52:10.86#ibcon#end of sib2, iclass 29, count 0 2006.173.02:52:10.86#ibcon#*mode == 0, iclass 29, count 0 2006.173.02:52:10.86#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.02:52:10.86#ibcon#[27=USB\r\n] 2006.173.02:52:10.86#ibcon#*before write, iclass 29, count 0 2006.173.02:52:10.86#ibcon#enter sib2, iclass 29, count 0 2006.173.02:52:10.86#ibcon#flushed, iclass 29, count 0 2006.173.02:52:10.86#ibcon#about to write, iclass 29, count 0 2006.173.02:52:10.86#ibcon#wrote, iclass 29, count 0 2006.173.02:52:10.86#ibcon#about to read 3, iclass 29, count 0 2006.173.02:52:10.89#ibcon#read 3, iclass 29, count 0 2006.173.02:52:10.89#ibcon#about to read 4, iclass 29, count 0 2006.173.02:52:10.89#ibcon#read 4, iclass 29, count 0 2006.173.02:52:10.89#ibcon#about to read 5, iclass 29, count 0 2006.173.02:52:10.89#ibcon#read 5, iclass 29, count 0 2006.173.02:52:10.89#ibcon#about to read 6, iclass 29, count 0 2006.173.02:52:10.89#ibcon#read 6, iclass 29, count 0 2006.173.02:52:10.89#ibcon#end of sib2, iclass 29, count 0 2006.173.02:52:10.89#ibcon#*after write, iclass 29, count 0 2006.173.02:52:10.89#ibcon#*before return 0, iclass 29, count 0 2006.173.02:52:10.89#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.02:52:10.89#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.02:52:10.89#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.02:52:10.89#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.02:52:10.89$vck44/vblo=4,679.99 2006.173.02:52:10.89#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.02:52:10.89#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.02:52:10.89#ibcon#ireg 17 cls_cnt 0 2006.173.02:52:10.89#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.02:52:10.89#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.02:52:10.89#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.02:52:10.89#ibcon#enter wrdev, iclass 31, count 0 2006.173.02:52:10.89#ibcon#first serial, iclass 31, count 0 2006.173.02:52:10.89#ibcon#enter sib2, iclass 31, count 0 2006.173.02:52:10.89#ibcon#flushed, iclass 31, count 0 2006.173.02:52:10.89#ibcon#about to write, iclass 31, count 0 2006.173.02:52:10.89#ibcon#wrote, iclass 31, count 0 2006.173.02:52:10.89#ibcon#about to read 3, iclass 31, count 0 2006.173.02:52:10.91#ibcon#read 3, iclass 31, count 0 2006.173.02:52:10.91#ibcon#about to read 4, iclass 31, count 0 2006.173.02:52:10.91#ibcon#read 4, iclass 31, count 0 2006.173.02:52:10.91#ibcon#about to read 5, iclass 31, count 0 2006.173.02:52:10.91#ibcon#read 5, iclass 31, count 0 2006.173.02:52:10.91#ibcon#about to read 6, iclass 31, count 0 2006.173.02:52:10.91#ibcon#read 6, iclass 31, count 0 2006.173.02:52:10.91#ibcon#end of sib2, iclass 31, count 0 2006.173.02:52:10.91#ibcon#*mode == 0, iclass 31, count 0 2006.173.02:52:10.91#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.02:52:10.91#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.02:52:10.91#ibcon#*before write, iclass 31, count 0 2006.173.02:52:10.91#ibcon#enter sib2, iclass 31, count 0 2006.173.02:52:10.91#ibcon#flushed, iclass 31, count 0 2006.173.02:52:10.91#ibcon#about to write, iclass 31, count 0 2006.173.02:52:10.91#ibcon#wrote, iclass 31, count 0 2006.173.02:52:10.91#ibcon#about to read 3, iclass 31, count 0 2006.173.02:52:10.95#ibcon#read 3, iclass 31, count 0 2006.173.02:52:10.95#ibcon#about to read 4, iclass 31, count 0 2006.173.02:52:10.95#ibcon#read 4, iclass 31, count 0 2006.173.02:52:10.95#ibcon#about to read 5, iclass 31, count 0 2006.173.02:52:10.95#ibcon#read 5, iclass 31, count 0 2006.173.02:52:10.95#ibcon#about to read 6, iclass 31, count 0 2006.173.02:52:10.95#ibcon#read 6, iclass 31, count 0 2006.173.02:52:10.95#ibcon#end of sib2, iclass 31, count 0 2006.173.02:52:10.95#ibcon#*after write, iclass 31, count 0 2006.173.02:52:10.95#ibcon#*before return 0, iclass 31, count 0 2006.173.02:52:10.95#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.02:52:10.95#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.02:52:10.95#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.02:52:10.95#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.02:52:10.95$vck44/vb=4,4 2006.173.02:52:10.95#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.173.02:52:10.95#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.173.02:52:10.95#ibcon#ireg 11 cls_cnt 2 2006.173.02:52:10.95#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.02:52:11.01#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.02:52:11.01#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.02:52:11.01#ibcon#enter wrdev, iclass 33, count 2 2006.173.02:52:11.01#ibcon#first serial, iclass 33, count 2 2006.173.02:52:11.01#ibcon#enter sib2, iclass 33, count 2 2006.173.02:52:11.01#ibcon#flushed, iclass 33, count 2 2006.173.02:52:11.01#ibcon#about to write, iclass 33, count 2 2006.173.02:52:11.01#ibcon#wrote, iclass 33, count 2 2006.173.02:52:11.01#ibcon#about to read 3, iclass 33, count 2 2006.173.02:52:11.03#ibcon#read 3, iclass 33, count 2 2006.173.02:52:11.03#ibcon#about to read 4, iclass 33, count 2 2006.173.02:52:11.03#ibcon#read 4, iclass 33, count 2 2006.173.02:52:11.03#ibcon#about to read 5, iclass 33, count 2 2006.173.02:52:11.03#ibcon#read 5, iclass 33, count 2 2006.173.02:52:11.03#ibcon#about to read 6, iclass 33, count 2 2006.173.02:52:11.03#ibcon#read 6, iclass 33, count 2 2006.173.02:52:11.03#ibcon#end of sib2, iclass 33, count 2 2006.173.02:52:11.03#ibcon#*mode == 0, iclass 33, count 2 2006.173.02:52:11.03#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.173.02:52:11.03#ibcon#[27=AT04-04\r\n] 2006.173.02:52:11.03#ibcon#*before write, iclass 33, count 2 2006.173.02:52:11.03#ibcon#enter sib2, iclass 33, count 2 2006.173.02:52:11.03#ibcon#flushed, iclass 33, count 2 2006.173.02:52:11.03#ibcon#about to write, iclass 33, count 2 2006.173.02:52:11.03#ibcon#wrote, iclass 33, count 2 2006.173.02:52:11.03#ibcon#about to read 3, iclass 33, count 2 2006.173.02:52:11.06#ibcon#read 3, iclass 33, count 2 2006.173.02:52:11.06#ibcon#about to read 4, iclass 33, count 2 2006.173.02:52:11.06#ibcon#read 4, iclass 33, count 2 2006.173.02:52:11.06#ibcon#about to read 5, iclass 33, count 2 2006.173.02:52:11.06#ibcon#read 5, iclass 33, count 2 2006.173.02:52:11.06#ibcon#about to read 6, iclass 33, count 2 2006.173.02:52:11.06#ibcon#read 6, iclass 33, count 2 2006.173.02:52:11.06#ibcon#end of sib2, iclass 33, count 2 2006.173.02:52:11.06#ibcon#*after write, iclass 33, count 2 2006.173.02:52:11.06#ibcon#*before return 0, iclass 33, count 2 2006.173.02:52:11.06#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.02:52:11.06#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.173.02:52:11.06#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.173.02:52:11.06#ibcon#ireg 7 cls_cnt 0 2006.173.02:52:11.06#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.02:52:11.18#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.02:52:11.18#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.02:52:11.18#ibcon#enter wrdev, iclass 33, count 0 2006.173.02:52:11.18#ibcon#first serial, iclass 33, count 0 2006.173.02:52:11.18#ibcon#enter sib2, iclass 33, count 0 2006.173.02:52:11.18#ibcon#flushed, iclass 33, count 0 2006.173.02:52:11.18#ibcon#about to write, iclass 33, count 0 2006.173.02:52:11.18#ibcon#wrote, iclass 33, count 0 2006.173.02:52:11.18#ibcon#about to read 3, iclass 33, count 0 2006.173.02:52:11.20#ibcon#read 3, iclass 33, count 0 2006.173.02:52:11.20#ibcon#about to read 4, iclass 33, count 0 2006.173.02:52:11.20#ibcon#read 4, iclass 33, count 0 2006.173.02:52:11.20#ibcon#about to read 5, iclass 33, count 0 2006.173.02:52:11.20#ibcon#read 5, iclass 33, count 0 2006.173.02:52:11.20#ibcon#about to read 6, iclass 33, count 0 2006.173.02:52:11.20#ibcon#read 6, iclass 33, count 0 2006.173.02:52:11.20#ibcon#end of sib2, iclass 33, count 0 2006.173.02:52:11.20#ibcon#*mode == 0, iclass 33, count 0 2006.173.02:52:11.20#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.02:52:11.20#ibcon#[27=USB\r\n] 2006.173.02:52:11.20#ibcon#*before write, iclass 33, count 0 2006.173.02:52:11.20#ibcon#enter sib2, iclass 33, count 0 2006.173.02:52:11.20#ibcon#flushed, iclass 33, count 0 2006.173.02:52:11.20#ibcon#about to write, iclass 33, count 0 2006.173.02:52:11.20#ibcon#wrote, iclass 33, count 0 2006.173.02:52:11.20#ibcon#about to read 3, iclass 33, count 0 2006.173.02:52:11.23#ibcon#read 3, iclass 33, count 0 2006.173.02:52:11.23#ibcon#about to read 4, iclass 33, count 0 2006.173.02:52:11.23#ibcon#read 4, iclass 33, count 0 2006.173.02:52:11.23#ibcon#about to read 5, iclass 33, count 0 2006.173.02:52:11.23#ibcon#read 5, iclass 33, count 0 2006.173.02:52:11.23#ibcon#about to read 6, iclass 33, count 0 2006.173.02:52:11.23#ibcon#read 6, iclass 33, count 0 2006.173.02:52:11.23#ibcon#end of sib2, iclass 33, count 0 2006.173.02:52:11.23#ibcon#*after write, iclass 33, count 0 2006.173.02:52:11.23#ibcon#*before return 0, iclass 33, count 0 2006.173.02:52:11.23#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.02:52:11.23#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.173.02:52:11.23#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.02:52:11.23#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.02:52:11.23$vck44/vblo=5,709.99 2006.173.02:52:11.23#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.02:52:11.23#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.02:52:11.23#ibcon#ireg 17 cls_cnt 0 2006.173.02:52:11.23#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.02:52:11.23#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.02:52:11.23#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.02:52:11.23#ibcon#enter wrdev, iclass 35, count 0 2006.173.02:52:11.23#ibcon#first serial, iclass 35, count 0 2006.173.02:52:11.23#ibcon#enter sib2, iclass 35, count 0 2006.173.02:52:11.23#ibcon#flushed, iclass 35, count 0 2006.173.02:52:11.23#ibcon#about to write, iclass 35, count 0 2006.173.02:52:11.23#ibcon#wrote, iclass 35, count 0 2006.173.02:52:11.23#ibcon#about to read 3, iclass 35, count 0 2006.173.02:52:11.25#ibcon#read 3, iclass 35, count 0 2006.173.02:52:11.25#ibcon#about to read 4, iclass 35, count 0 2006.173.02:52:11.25#ibcon#read 4, iclass 35, count 0 2006.173.02:52:11.25#ibcon#about to read 5, iclass 35, count 0 2006.173.02:52:11.25#ibcon#read 5, iclass 35, count 0 2006.173.02:52:11.25#ibcon#about to read 6, iclass 35, count 0 2006.173.02:52:11.25#ibcon#read 6, iclass 35, count 0 2006.173.02:52:11.25#ibcon#end of sib2, iclass 35, count 0 2006.173.02:52:11.25#ibcon#*mode == 0, iclass 35, count 0 2006.173.02:52:11.25#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.02:52:11.25#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.02:52:11.25#ibcon#*before write, iclass 35, count 0 2006.173.02:52:11.25#ibcon#enter sib2, iclass 35, count 0 2006.173.02:52:11.25#ibcon#flushed, iclass 35, count 0 2006.173.02:52:11.25#ibcon#about to write, iclass 35, count 0 2006.173.02:52:11.25#ibcon#wrote, iclass 35, count 0 2006.173.02:52:11.25#ibcon#about to read 3, iclass 35, count 0 2006.173.02:52:11.29#ibcon#read 3, iclass 35, count 0 2006.173.02:52:11.29#ibcon#about to read 4, iclass 35, count 0 2006.173.02:52:11.29#ibcon#read 4, iclass 35, count 0 2006.173.02:52:11.29#ibcon#about to read 5, iclass 35, count 0 2006.173.02:52:11.29#ibcon#read 5, iclass 35, count 0 2006.173.02:52:11.29#ibcon#about to read 6, iclass 35, count 0 2006.173.02:52:11.29#ibcon#read 6, iclass 35, count 0 2006.173.02:52:11.29#ibcon#end of sib2, iclass 35, count 0 2006.173.02:52:11.29#ibcon#*after write, iclass 35, count 0 2006.173.02:52:11.29#ibcon#*before return 0, iclass 35, count 0 2006.173.02:52:11.29#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.02:52:11.29#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.02:52:11.29#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.02:52:11.29#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.02:52:11.29$vck44/vb=5,4 2006.173.02:52:11.29#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.173.02:52:11.29#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.173.02:52:11.29#ibcon#ireg 11 cls_cnt 2 2006.173.02:52:11.29#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.02:52:11.35#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.02:52:11.35#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.02:52:11.35#ibcon#enter wrdev, iclass 37, count 2 2006.173.02:52:11.35#ibcon#first serial, iclass 37, count 2 2006.173.02:52:11.35#ibcon#enter sib2, iclass 37, count 2 2006.173.02:52:11.35#ibcon#flushed, iclass 37, count 2 2006.173.02:52:11.35#ibcon#about to write, iclass 37, count 2 2006.173.02:52:11.35#ibcon#wrote, iclass 37, count 2 2006.173.02:52:11.35#ibcon#about to read 3, iclass 37, count 2 2006.173.02:52:11.37#ibcon#read 3, iclass 37, count 2 2006.173.02:52:11.37#ibcon#about to read 4, iclass 37, count 2 2006.173.02:52:11.37#ibcon#read 4, iclass 37, count 2 2006.173.02:52:11.37#ibcon#about to read 5, iclass 37, count 2 2006.173.02:52:11.37#ibcon#read 5, iclass 37, count 2 2006.173.02:52:11.37#ibcon#about to read 6, iclass 37, count 2 2006.173.02:52:11.37#ibcon#read 6, iclass 37, count 2 2006.173.02:52:11.37#ibcon#end of sib2, iclass 37, count 2 2006.173.02:52:11.37#ibcon#*mode == 0, iclass 37, count 2 2006.173.02:52:11.37#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.173.02:52:11.37#ibcon#[27=AT05-04\r\n] 2006.173.02:52:11.37#ibcon#*before write, iclass 37, count 2 2006.173.02:52:11.37#ibcon#enter sib2, iclass 37, count 2 2006.173.02:52:11.37#ibcon#flushed, iclass 37, count 2 2006.173.02:52:11.37#ibcon#about to write, iclass 37, count 2 2006.173.02:52:11.37#ibcon#wrote, iclass 37, count 2 2006.173.02:52:11.37#ibcon#about to read 3, iclass 37, count 2 2006.173.02:52:11.40#ibcon#read 3, iclass 37, count 2 2006.173.02:52:11.40#ibcon#about to read 4, iclass 37, count 2 2006.173.02:52:11.40#ibcon#read 4, iclass 37, count 2 2006.173.02:52:11.40#ibcon#about to read 5, iclass 37, count 2 2006.173.02:52:11.40#ibcon#read 5, iclass 37, count 2 2006.173.02:52:11.40#ibcon#about to read 6, iclass 37, count 2 2006.173.02:52:11.40#ibcon#read 6, iclass 37, count 2 2006.173.02:52:11.40#ibcon#end of sib2, iclass 37, count 2 2006.173.02:52:11.40#ibcon#*after write, iclass 37, count 2 2006.173.02:52:11.40#ibcon#*before return 0, iclass 37, count 2 2006.173.02:52:11.40#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.02:52:11.40#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.173.02:52:11.40#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.173.02:52:11.40#ibcon#ireg 7 cls_cnt 0 2006.173.02:52:11.40#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.02:52:11.52#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.02:52:11.52#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.02:52:11.52#ibcon#enter wrdev, iclass 37, count 0 2006.173.02:52:11.52#ibcon#first serial, iclass 37, count 0 2006.173.02:52:11.52#ibcon#enter sib2, iclass 37, count 0 2006.173.02:52:11.52#ibcon#flushed, iclass 37, count 0 2006.173.02:52:11.52#ibcon#about to write, iclass 37, count 0 2006.173.02:52:11.52#ibcon#wrote, iclass 37, count 0 2006.173.02:52:11.52#ibcon#about to read 3, iclass 37, count 0 2006.173.02:52:11.54#ibcon#read 3, iclass 37, count 0 2006.173.02:52:11.54#ibcon#about to read 4, iclass 37, count 0 2006.173.02:52:11.54#ibcon#read 4, iclass 37, count 0 2006.173.02:52:11.54#ibcon#about to read 5, iclass 37, count 0 2006.173.02:52:11.54#ibcon#read 5, iclass 37, count 0 2006.173.02:52:11.54#ibcon#about to read 6, iclass 37, count 0 2006.173.02:52:11.54#ibcon#read 6, iclass 37, count 0 2006.173.02:52:11.54#ibcon#end of sib2, iclass 37, count 0 2006.173.02:52:11.54#ibcon#*mode == 0, iclass 37, count 0 2006.173.02:52:11.54#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.02:52:11.54#ibcon#[27=USB\r\n] 2006.173.02:52:11.54#ibcon#*before write, iclass 37, count 0 2006.173.02:52:11.54#ibcon#enter sib2, iclass 37, count 0 2006.173.02:52:11.54#ibcon#flushed, iclass 37, count 0 2006.173.02:52:11.54#ibcon#about to write, iclass 37, count 0 2006.173.02:52:11.54#ibcon#wrote, iclass 37, count 0 2006.173.02:52:11.54#ibcon#about to read 3, iclass 37, count 0 2006.173.02:52:11.57#ibcon#read 3, iclass 37, count 0 2006.173.02:52:11.57#ibcon#about to read 4, iclass 37, count 0 2006.173.02:52:11.57#ibcon#read 4, iclass 37, count 0 2006.173.02:52:11.57#ibcon#about to read 5, iclass 37, count 0 2006.173.02:52:11.57#ibcon#read 5, iclass 37, count 0 2006.173.02:52:11.57#ibcon#about to read 6, iclass 37, count 0 2006.173.02:52:11.57#ibcon#read 6, iclass 37, count 0 2006.173.02:52:11.57#ibcon#end of sib2, iclass 37, count 0 2006.173.02:52:11.57#ibcon#*after write, iclass 37, count 0 2006.173.02:52:11.57#ibcon#*before return 0, iclass 37, count 0 2006.173.02:52:11.57#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.02:52:11.57#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.173.02:52:11.57#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.02:52:11.57#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.02:52:11.57$vck44/vblo=6,719.99 2006.173.02:52:11.57#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.02:52:11.57#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.02:52:11.57#ibcon#ireg 17 cls_cnt 0 2006.173.02:52:11.57#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.02:52:11.57#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.02:52:11.57#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.02:52:11.57#ibcon#enter wrdev, iclass 39, count 0 2006.173.02:52:11.57#ibcon#first serial, iclass 39, count 0 2006.173.02:52:11.57#ibcon#enter sib2, iclass 39, count 0 2006.173.02:52:11.57#ibcon#flushed, iclass 39, count 0 2006.173.02:52:11.57#ibcon#about to write, iclass 39, count 0 2006.173.02:52:11.57#ibcon#wrote, iclass 39, count 0 2006.173.02:52:11.57#ibcon#about to read 3, iclass 39, count 0 2006.173.02:52:11.59#ibcon#read 3, iclass 39, count 0 2006.173.02:52:11.59#ibcon#about to read 4, iclass 39, count 0 2006.173.02:52:11.59#ibcon#read 4, iclass 39, count 0 2006.173.02:52:11.59#ibcon#about to read 5, iclass 39, count 0 2006.173.02:52:11.59#ibcon#read 5, iclass 39, count 0 2006.173.02:52:11.59#ibcon#about to read 6, iclass 39, count 0 2006.173.02:52:11.59#ibcon#read 6, iclass 39, count 0 2006.173.02:52:11.59#ibcon#end of sib2, iclass 39, count 0 2006.173.02:52:11.59#ibcon#*mode == 0, iclass 39, count 0 2006.173.02:52:11.59#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.02:52:11.59#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.02:52:11.59#ibcon#*before write, iclass 39, count 0 2006.173.02:52:11.59#ibcon#enter sib2, iclass 39, count 0 2006.173.02:52:11.59#ibcon#flushed, iclass 39, count 0 2006.173.02:52:11.59#ibcon#about to write, iclass 39, count 0 2006.173.02:52:11.59#ibcon#wrote, iclass 39, count 0 2006.173.02:52:11.59#ibcon#about to read 3, iclass 39, count 0 2006.173.02:52:11.63#ibcon#read 3, iclass 39, count 0 2006.173.02:52:11.63#ibcon#about to read 4, iclass 39, count 0 2006.173.02:52:11.63#ibcon#read 4, iclass 39, count 0 2006.173.02:52:11.63#ibcon#about to read 5, iclass 39, count 0 2006.173.02:52:11.63#ibcon#read 5, iclass 39, count 0 2006.173.02:52:11.63#ibcon#about to read 6, iclass 39, count 0 2006.173.02:52:11.63#ibcon#read 6, iclass 39, count 0 2006.173.02:52:11.63#ibcon#end of sib2, iclass 39, count 0 2006.173.02:52:11.63#ibcon#*after write, iclass 39, count 0 2006.173.02:52:11.63#ibcon#*before return 0, iclass 39, count 0 2006.173.02:52:11.63#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.02:52:11.63#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.02:52:11.63#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.02:52:11.63#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.02:52:11.63$vck44/vb=6,4 2006.173.02:52:11.63#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.02:52:11.63#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.02:52:11.63#ibcon#ireg 11 cls_cnt 2 2006.173.02:52:11.63#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.02:52:11.69#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.02:52:11.69#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.02:52:11.69#ibcon#enter wrdev, iclass 3, count 2 2006.173.02:52:11.69#ibcon#first serial, iclass 3, count 2 2006.173.02:52:11.69#ibcon#enter sib2, iclass 3, count 2 2006.173.02:52:11.69#ibcon#flushed, iclass 3, count 2 2006.173.02:52:11.69#ibcon#about to write, iclass 3, count 2 2006.173.02:52:11.69#ibcon#wrote, iclass 3, count 2 2006.173.02:52:11.69#ibcon#about to read 3, iclass 3, count 2 2006.173.02:52:11.71#ibcon#read 3, iclass 3, count 2 2006.173.02:52:11.71#ibcon#about to read 4, iclass 3, count 2 2006.173.02:52:11.71#ibcon#read 4, iclass 3, count 2 2006.173.02:52:11.71#ibcon#about to read 5, iclass 3, count 2 2006.173.02:52:11.71#ibcon#read 5, iclass 3, count 2 2006.173.02:52:11.71#ibcon#about to read 6, iclass 3, count 2 2006.173.02:52:11.71#ibcon#read 6, iclass 3, count 2 2006.173.02:52:11.71#ibcon#end of sib2, iclass 3, count 2 2006.173.02:52:11.71#ibcon#*mode == 0, iclass 3, count 2 2006.173.02:52:11.71#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.02:52:11.71#ibcon#[27=AT06-04\r\n] 2006.173.02:52:11.71#ibcon#*before write, iclass 3, count 2 2006.173.02:52:11.71#ibcon#enter sib2, iclass 3, count 2 2006.173.02:52:11.71#ibcon#flushed, iclass 3, count 2 2006.173.02:52:11.71#ibcon#about to write, iclass 3, count 2 2006.173.02:52:11.71#ibcon#wrote, iclass 3, count 2 2006.173.02:52:11.71#ibcon#about to read 3, iclass 3, count 2 2006.173.02:52:11.74#ibcon#read 3, iclass 3, count 2 2006.173.02:52:11.74#ibcon#about to read 4, iclass 3, count 2 2006.173.02:52:11.74#ibcon#read 4, iclass 3, count 2 2006.173.02:52:11.74#ibcon#about to read 5, iclass 3, count 2 2006.173.02:52:11.74#ibcon#read 5, iclass 3, count 2 2006.173.02:52:11.74#ibcon#about to read 6, iclass 3, count 2 2006.173.02:52:11.74#ibcon#read 6, iclass 3, count 2 2006.173.02:52:11.74#ibcon#end of sib2, iclass 3, count 2 2006.173.02:52:11.74#ibcon#*after write, iclass 3, count 2 2006.173.02:52:11.74#ibcon#*before return 0, iclass 3, count 2 2006.173.02:52:11.74#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.02:52:11.74#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.02:52:11.74#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.02:52:11.74#ibcon#ireg 7 cls_cnt 0 2006.173.02:52:11.74#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.02:52:11.86#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.02:52:11.86#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.02:52:11.86#ibcon#enter wrdev, iclass 3, count 0 2006.173.02:52:11.86#ibcon#first serial, iclass 3, count 0 2006.173.02:52:11.86#ibcon#enter sib2, iclass 3, count 0 2006.173.02:52:11.86#ibcon#flushed, iclass 3, count 0 2006.173.02:52:11.86#ibcon#about to write, iclass 3, count 0 2006.173.02:52:11.86#ibcon#wrote, iclass 3, count 0 2006.173.02:52:11.86#ibcon#about to read 3, iclass 3, count 0 2006.173.02:52:11.88#ibcon#read 3, iclass 3, count 0 2006.173.02:52:11.88#ibcon#about to read 4, iclass 3, count 0 2006.173.02:52:11.88#ibcon#read 4, iclass 3, count 0 2006.173.02:52:11.88#ibcon#about to read 5, iclass 3, count 0 2006.173.02:52:11.88#ibcon#read 5, iclass 3, count 0 2006.173.02:52:11.88#ibcon#about to read 6, iclass 3, count 0 2006.173.02:52:11.88#ibcon#read 6, iclass 3, count 0 2006.173.02:52:11.88#ibcon#end of sib2, iclass 3, count 0 2006.173.02:52:11.88#ibcon#*mode == 0, iclass 3, count 0 2006.173.02:52:11.88#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.02:52:11.88#ibcon#[27=USB\r\n] 2006.173.02:52:11.88#ibcon#*before write, iclass 3, count 0 2006.173.02:52:11.88#ibcon#enter sib2, iclass 3, count 0 2006.173.02:52:11.88#ibcon#flushed, iclass 3, count 0 2006.173.02:52:11.88#ibcon#about to write, iclass 3, count 0 2006.173.02:52:11.88#ibcon#wrote, iclass 3, count 0 2006.173.02:52:11.88#ibcon#about to read 3, iclass 3, count 0 2006.173.02:52:11.91#ibcon#read 3, iclass 3, count 0 2006.173.02:52:11.91#ibcon#about to read 4, iclass 3, count 0 2006.173.02:52:11.91#ibcon#read 4, iclass 3, count 0 2006.173.02:52:11.91#ibcon#about to read 5, iclass 3, count 0 2006.173.02:52:11.91#ibcon#read 5, iclass 3, count 0 2006.173.02:52:11.91#ibcon#about to read 6, iclass 3, count 0 2006.173.02:52:11.91#ibcon#read 6, iclass 3, count 0 2006.173.02:52:11.91#ibcon#end of sib2, iclass 3, count 0 2006.173.02:52:11.91#ibcon#*after write, iclass 3, count 0 2006.173.02:52:11.91#ibcon#*before return 0, iclass 3, count 0 2006.173.02:52:11.91#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.02:52:11.91#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.02:52:11.91#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.02:52:11.91#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.02:52:11.91$vck44/vblo=7,734.99 2006.173.02:52:11.91#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.02:52:11.91#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.02:52:11.91#ibcon#ireg 17 cls_cnt 0 2006.173.02:52:11.91#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.02:52:11.91#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.02:52:11.91#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.02:52:11.91#ibcon#enter wrdev, iclass 5, count 0 2006.173.02:52:11.91#ibcon#first serial, iclass 5, count 0 2006.173.02:52:11.91#ibcon#enter sib2, iclass 5, count 0 2006.173.02:52:11.91#ibcon#flushed, iclass 5, count 0 2006.173.02:52:11.91#ibcon#about to write, iclass 5, count 0 2006.173.02:52:11.91#ibcon#wrote, iclass 5, count 0 2006.173.02:52:11.91#ibcon#about to read 3, iclass 5, count 0 2006.173.02:52:11.93#ibcon#read 3, iclass 5, count 0 2006.173.02:52:11.93#ibcon#about to read 4, iclass 5, count 0 2006.173.02:52:11.93#ibcon#read 4, iclass 5, count 0 2006.173.02:52:11.93#ibcon#about to read 5, iclass 5, count 0 2006.173.02:52:11.93#ibcon#read 5, iclass 5, count 0 2006.173.02:52:11.93#ibcon#about to read 6, iclass 5, count 0 2006.173.02:52:11.93#ibcon#read 6, iclass 5, count 0 2006.173.02:52:11.93#ibcon#end of sib2, iclass 5, count 0 2006.173.02:52:11.93#ibcon#*mode == 0, iclass 5, count 0 2006.173.02:52:11.93#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.02:52:11.93#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.02:52:11.93#ibcon#*before write, iclass 5, count 0 2006.173.02:52:11.93#ibcon#enter sib2, iclass 5, count 0 2006.173.02:52:11.93#ibcon#flushed, iclass 5, count 0 2006.173.02:52:11.93#ibcon#about to write, iclass 5, count 0 2006.173.02:52:11.93#ibcon#wrote, iclass 5, count 0 2006.173.02:52:11.93#ibcon#about to read 3, iclass 5, count 0 2006.173.02:52:11.97#ibcon#read 3, iclass 5, count 0 2006.173.02:52:11.97#ibcon#about to read 4, iclass 5, count 0 2006.173.02:52:11.97#ibcon#read 4, iclass 5, count 0 2006.173.02:52:11.97#ibcon#about to read 5, iclass 5, count 0 2006.173.02:52:11.97#ibcon#read 5, iclass 5, count 0 2006.173.02:52:11.97#ibcon#about to read 6, iclass 5, count 0 2006.173.02:52:11.97#ibcon#read 6, iclass 5, count 0 2006.173.02:52:11.97#ibcon#end of sib2, iclass 5, count 0 2006.173.02:52:11.97#ibcon#*after write, iclass 5, count 0 2006.173.02:52:11.97#ibcon#*before return 0, iclass 5, count 0 2006.173.02:52:11.97#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.02:52:11.97#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.02:52:11.97#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.02:52:11.97#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.02:52:11.97$vck44/vb=7,4 2006.173.02:52:11.97#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.173.02:52:11.97#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.173.02:52:11.97#ibcon#ireg 11 cls_cnt 2 2006.173.02:52:11.97#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.02:52:12.03#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.02:52:12.03#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.02:52:12.03#ibcon#enter wrdev, iclass 7, count 2 2006.173.02:52:12.03#ibcon#first serial, iclass 7, count 2 2006.173.02:52:12.03#ibcon#enter sib2, iclass 7, count 2 2006.173.02:52:12.03#ibcon#flushed, iclass 7, count 2 2006.173.02:52:12.03#ibcon#about to write, iclass 7, count 2 2006.173.02:52:12.03#ibcon#wrote, iclass 7, count 2 2006.173.02:52:12.03#ibcon#about to read 3, iclass 7, count 2 2006.173.02:52:12.05#ibcon#read 3, iclass 7, count 2 2006.173.02:52:12.05#ibcon#about to read 4, iclass 7, count 2 2006.173.02:52:12.05#ibcon#read 4, iclass 7, count 2 2006.173.02:52:12.05#ibcon#about to read 5, iclass 7, count 2 2006.173.02:52:12.05#ibcon#read 5, iclass 7, count 2 2006.173.02:52:12.05#ibcon#about to read 6, iclass 7, count 2 2006.173.02:52:12.05#ibcon#read 6, iclass 7, count 2 2006.173.02:52:12.05#ibcon#end of sib2, iclass 7, count 2 2006.173.02:52:12.05#ibcon#*mode == 0, iclass 7, count 2 2006.173.02:52:12.05#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.173.02:52:12.05#ibcon#[27=AT07-04\r\n] 2006.173.02:52:12.05#ibcon#*before write, iclass 7, count 2 2006.173.02:52:12.05#ibcon#enter sib2, iclass 7, count 2 2006.173.02:52:12.05#ibcon#flushed, iclass 7, count 2 2006.173.02:52:12.05#ibcon#about to write, iclass 7, count 2 2006.173.02:52:12.05#ibcon#wrote, iclass 7, count 2 2006.173.02:52:12.05#ibcon#about to read 3, iclass 7, count 2 2006.173.02:52:12.08#ibcon#read 3, iclass 7, count 2 2006.173.02:52:12.08#ibcon#about to read 4, iclass 7, count 2 2006.173.02:52:12.08#ibcon#read 4, iclass 7, count 2 2006.173.02:52:12.08#ibcon#about to read 5, iclass 7, count 2 2006.173.02:52:12.08#ibcon#read 5, iclass 7, count 2 2006.173.02:52:12.08#ibcon#about to read 6, iclass 7, count 2 2006.173.02:52:12.08#ibcon#read 6, iclass 7, count 2 2006.173.02:52:12.08#ibcon#end of sib2, iclass 7, count 2 2006.173.02:52:12.08#ibcon#*after write, iclass 7, count 2 2006.173.02:52:12.08#ibcon#*before return 0, iclass 7, count 2 2006.173.02:52:12.08#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.02:52:12.08#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.173.02:52:12.08#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.173.02:52:12.08#ibcon#ireg 7 cls_cnt 0 2006.173.02:52:12.08#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.02:52:12.20#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.02:52:12.20#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.02:52:12.20#ibcon#enter wrdev, iclass 7, count 0 2006.173.02:52:12.20#ibcon#first serial, iclass 7, count 0 2006.173.02:52:12.20#ibcon#enter sib2, iclass 7, count 0 2006.173.02:52:12.20#ibcon#flushed, iclass 7, count 0 2006.173.02:52:12.20#ibcon#about to write, iclass 7, count 0 2006.173.02:52:12.20#ibcon#wrote, iclass 7, count 0 2006.173.02:52:12.20#ibcon#about to read 3, iclass 7, count 0 2006.173.02:52:12.22#ibcon#read 3, iclass 7, count 0 2006.173.02:52:12.22#ibcon#about to read 4, iclass 7, count 0 2006.173.02:52:12.22#ibcon#read 4, iclass 7, count 0 2006.173.02:52:12.22#ibcon#about to read 5, iclass 7, count 0 2006.173.02:52:12.22#ibcon#read 5, iclass 7, count 0 2006.173.02:52:12.22#ibcon#about to read 6, iclass 7, count 0 2006.173.02:52:12.22#ibcon#read 6, iclass 7, count 0 2006.173.02:52:12.22#ibcon#end of sib2, iclass 7, count 0 2006.173.02:52:12.22#ibcon#*mode == 0, iclass 7, count 0 2006.173.02:52:12.22#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.02:52:12.22#ibcon#[27=USB\r\n] 2006.173.02:52:12.22#ibcon#*before write, iclass 7, count 0 2006.173.02:52:12.22#ibcon#enter sib2, iclass 7, count 0 2006.173.02:52:12.22#ibcon#flushed, iclass 7, count 0 2006.173.02:52:12.22#ibcon#about to write, iclass 7, count 0 2006.173.02:52:12.22#ibcon#wrote, iclass 7, count 0 2006.173.02:52:12.22#ibcon#about to read 3, iclass 7, count 0 2006.173.02:52:12.25#ibcon#read 3, iclass 7, count 0 2006.173.02:52:12.25#ibcon#about to read 4, iclass 7, count 0 2006.173.02:52:12.25#ibcon#read 4, iclass 7, count 0 2006.173.02:52:12.25#ibcon#about to read 5, iclass 7, count 0 2006.173.02:52:12.25#ibcon#read 5, iclass 7, count 0 2006.173.02:52:12.25#ibcon#about to read 6, iclass 7, count 0 2006.173.02:52:12.25#ibcon#read 6, iclass 7, count 0 2006.173.02:52:12.25#ibcon#end of sib2, iclass 7, count 0 2006.173.02:52:12.25#ibcon#*after write, iclass 7, count 0 2006.173.02:52:12.25#ibcon#*before return 0, iclass 7, count 0 2006.173.02:52:12.25#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.02:52:12.25#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.173.02:52:12.25#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.02:52:12.25#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.02:52:12.25$vck44/vblo=8,744.99 2006.173.02:52:12.25#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.02:52:12.25#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.02:52:12.25#ibcon#ireg 17 cls_cnt 0 2006.173.02:52:12.25#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.02:52:12.25#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.02:52:12.25#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.02:52:12.25#ibcon#enter wrdev, iclass 11, count 0 2006.173.02:52:12.25#ibcon#first serial, iclass 11, count 0 2006.173.02:52:12.25#ibcon#enter sib2, iclass 11, count 0 2006.173.02:52:12.25#ibcon#flushed, iclass 11, count 0 2006.173.02:52:12.25#ibcon#about to write, iclass 11, count 0 2006.173.02:52:12.25#ibcon#wrote, iclass 11, count 0 2006.173.02:52:12.25#ibcon#about to read 3, iclass 11, count 0 2006.173.02:52:12.27#ibcon#read 3, iclass 11, count 0 2006.173.02:52:12.27#ibcon#about to read 4, iclass 11, count 0 2006.173.02:52:12.27#ibcon#read 4, iclass 11, count 0 2006.173.02:52:12.27#ibcon#about to read 5, iclass 11, count 0 2006.173.02:52:12.27#ibcon#read 5, iclass 11, count 0 2006.173.02:52:12.27#ibcon#about to read 6, iclass 11, count 0 2006.173.02:52:12.27#ibcon#read 6, iclass 11, count 0 2006.173.02:52:12.27#ibcon#end of sib2, iclass 11, count 0 2006.173.02:52:12.27#ibcon#*mode == 0, iclass 11, count 0 2006.173.02:52:12.27#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.02:52:12.27#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.02:52:12.27#ibcon#*before write, iclass 11, count 0 2006.173.02:52:12.27#ibcon#enter sib2, iclass 11, count 0 2006.173.02:52:12.27#ibcon#flushed, iclass 11, count 0 2006.173.02:52:12.27#ibcon#about to write, iclass 11, count 0 2006.173.02:52:12.27#ibcon#wrote, iclass 11, count 0 2006.173.02:52:12.27#ibcon#about to read 3, iclass 11, count 0 2006.173.02:52:12.31#ibcon#read 3, iclass 11, count 0 2006.173.02:52:12.31#ibcon#about to read 4, iclass 11, count 0 2006.173.02:52:12.31#ibcon#read 4, iclass 11, count 0 2006.173.02:52:12.31#ibcon#about to read 5, iclass 11, count 0 2006.173.02:52:12.31#ibcon#read 5, iclass 11, count 0 2006.173.02:52:12.31#ibcon#about to read 6, iclass 11, count 0 2006.173.02:52:12.31#ibcon#read 6, iclass 11, count 0 2006.173.02:52:12.31#ibcon#end of sib2, iclass 11, count 0 2006.173.02:52:12.31#ibcon#*after write, iclass 11, count 0 2006.173.02:52:12.31#ibcon#*before return 0, iclass 11, count 0 2006.173.02:52:12.31#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.02:52:12.31#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.02:52:12.31#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.02:52:12.31#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.02:52:12.31$vck44/vb=8,4 2006.173.02:52:12.31#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.173.02:52:12.31#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.173.02:52:12.31#ibcon#ireg 11 cls_cnt 2 2006.173.02:52:12.31#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.02:52:12.37#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.02:52:12.37#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.02:52:12.37#ibcon#enter wrdev, iclass 13, count 2 2006.173.02:52:12.37#ibcon#first serial, iclass 13, count 2 2006.173.02:52:12.37#ibcon#enter sib2, iclass 13, count 2 2006.173.02:52:12.37#ibcon#flushed, iclass 13, count 2 2006.173.02:52:12.37#ibcon#about to write, iclass 13, count 2 2006.173.02:52:12.37#ibcon#wrote, iclass 13, count 2 2006.173.02:52:12.37#ibcon#about to read 3, iclass 13, count 2 2006.173.02:52:12.39#ibcon#read 3, iclass 13, count 2 2006.173.02:52:12.39#ibcon#about to read 4, iclass 13, count 2 2006.173.02:52:12.39#ibcon#read 4, iclass 13, count 2 2006.173.02:52:12.39#ibcon#about to read 5, iclass 13, count 2 2006.173.02:52:12.39#ibcon#read 5, iclass 13, count 2 2006.173.02:52:12.39#ibcon#about to read 6, iclass 13, count 2 2006.173.02:52:12.39#ibcon#read 6, iclass 13, count 2 2006.173.02:52:12.39#ibcon#end of sib2, iclass 13, count 2 2006.173.02:52:12.39#ibcon#*mode == 0, iclass 13, count 2 2006.173.02:52:12.39#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.173.02:52:12.39#ibcon#[27=AT08-04\r\n] 2006.173.02:52:12.39#ibcon#*before write, iclass 13, count 2 2006.173.02:52:12.39#ibcon#enter sib2, iclass 13, count 2 2006.173.02:52:12.39#ibcon#flushed, iclass 13, count 2 2006.173.02:52:12.39#ibcon#about to write, iclass 13, count 2 2006.173.02:52:12.39#ibcon#wrote, iclass 13, count 2 2006.173.02:52:12.39#ibcon#about to read 3, iclass 13, count 2 2006.173.02:52:12.42#ibcon#read 3, iclass 13, count 2 2006.173.02:52:12.42#ibcon#about to read 4, iclass 13, count 2 2006.173.02:52:12.42#ibcon#read 4, iclass 13, count 2 2006.173.02:52:12.42#ibcon#about to read 5, iclass 13, count 2 2006.173.02:52:12.42#ibcon#read 5, iclass 13, count 2 2006.173.02:52:12.42#ibcon#about to read 6, iclass 13, count 2 2006.173.02:52:12.42#ibcon#read 6, iclass 13, count 2 2006.173.02:52:12.42#ibcon#end of sib2, iclass 13, count 2 2006.173.02:52:12.42#ibcon#*after write, iclass 13, count 2 2006.173.02:52:12.42#ibcon#*before return 0, iclass 13, count 2 2006.173.02:52:12.42#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.02:52:12.42#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.173.02:52:12.42#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.173.02:52:12.42#ibcon#ireg 7 cls_cnt 0 2006.173.02:52:12.42#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.02:52:12.54#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.02:52:12.54#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.02:52:12.54#ibcon#enter wrdev, iclass 13, count 0 2006.173.02:52:12.54#ibcon#first serial, iclass 13, count 0 2006.173.02:52:12.54#ibcon#enter sib2, iclass 13, count 0 2006.173.02:52:12.54#ibcon#flushed, iclass 13, count 0 2006.173.02:52:12.54#ibcon#about to write, iclass 13, count 0 2006.173.02:52:12.54#ibcon#wrote, iclass 13, count 0 2006.173.02:52:12.54#ibcon#about to read 3, iclass 13, count 0 2006.173.02:52:12.56#ibcon#read 3, iclass 13, count 0 2006.173.02:52:12.56#ibcon#about to read 4, iclass 13, count 0 2006.173.02:52:12.56#ibcon#read 4, iclass 13, count 0 2006.173.02:52:12.56#ibcon#about to read 5, iclass 13, count 0 2006.173.02:52:12.56#ibcon#read 5, iclass 13, count 0 2006.173.02:52:12.56#ibcon#about to read 6, iclass 13, count 0 2006.173.02:52:12.56#ibcon#read 6, iclass 13, count 0 2006.173.02:52:12.56#ibcon#end of sib2, iclass 13, count 0 2006.173.02:52:12.56#ibcon#*mode == 0, iclass 13, count 0 2006.173.02:52:12.56#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.02:52:12.56#ibcon#[27=USB\r\n] 2006.173.02:52:12.56#ibcon#*before write, iclass 13, count 0 2006.173.02:52:12.56#ibcon#enter sib2, iclass 13, count 0 2006.173.02:52:12.56#ibcon#flushed, iclass 13, count 0 2006.173.02:52:12.56#ibcon#about to write, iclass 13, count 0 2006.173.02:52:12.56#ibcon#wrote, iclass 13, count 0 2006.173.02:52:12.56#ibcon#about to read 3, iclass 13, count 0 2006.173.02:52:12.59#ibcon#read 3, iclass 13, count 0 2006.173.02:52:12.59#ibcon#about to read 4, iclass 13, count 0 2006.173.02:52:12.59#ibcon#read 4, iclass 13, count 0 2006.173.02:52:12.59#ibcon#about to read 5, iclass 13, count 0 2006.173.02:52:12.59#ibcon#read 5, iclass 13, count 0 2006.173.02:52:12.59#ibcon#about to read 6, iclass 13, count 0 2006.173.02:52:12.59#ibcon#read 6, iclass 13, count 0 2006.173.02:52:12.59#ibcon#end of sib2, iclass 13, count 0 2006.173.02:52:12.59#ibcon#*after write, iclass 13, count 0 2006.173.02:52:12.59#ibcon#*before return 0, iclass 13, count 0 2006.173.02:52:12.59#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.02:52:12.59#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.173.02:52:12.59#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.02:52:12.59#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.02:52:12.59$vck44/vabw=wide 2006.173.02:52:12.59#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.02:52:12.59#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.02:52:12.59#ibcon#ireg 8 cls_cnt 0 2006.173.02:52:12.59#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.02:52:12.59#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.02:52:12.59#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.02:52:12.59#ibcon#enter wrdev, iclass 15, count 0 2006.173.02:52:12.59#ibcon#first serial, iclass 15, count 0 2006.173.02:52:12.59#ibcon#enter sib2, iclass 15, count 0 2006.173.02:52:12.59#ibcon#flushed, iclass 15, count 0 2006.173.02:52:12.59#ibcon#about to write, iclass 15, count 0 2006.173.02:52:12.59#ibcon#wrote, iclass 15, count 0 2006.173.02:52:12.59#ibcon#about to read 3, iclass 15, count 0 2006.173.02:52:12.61#ibcon#read 3, iclass 15, count 0 2006.173.02:52:12.61#ibcon#about to read 4, iclass 15, count 0 2006.173.02:52:12.61#ibcon#read 4, iclass 15, count 0 2006.173.02:52:12.61#ibcon#about to read 5, iclass 15, count 0 2006.173.02:52:12.61#ibcon#read 5, iclass 15, count 0 2006.173.02:52:12.61#ibcon#about to read 6, iclass 15, count 0 2006.173.02:52:12.61#ibcon#read 6, iclass 15, count 0 2006.173.02:52:12.61#ibcon#end of sib2, iclass 15, count 0 2006.173.02:52:12.61#ibcon#*mode == 0, iclass 15, count 0 2006.173.02:52:12.61#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.02:52:12.61#ibcon#[25=BW32\r\n] 2006.173.02:52:12.61#ibcon#*before write, iclass 15, count 0 2006.173.02:52:12.61#ibcon#enter sib2, iclass 15, count 0 2006.173.02:52:12.61#ibcon#flushed, iclass 15, count 0 2006.173.02:52:12.61#ibcon#about to write, iclass 15, count 0 2006.173.02:52:12.61#ibcon#wrote, iclass 15, count 0 2006.173.02:52:12.61#ibcon#about to read 3, iclass 15, count 0 2006.173.02:52:12.64#ibcon#read 3, iclass 15, count 0 2006.173.02:52:12.64#ibcon#about to read 4, iclass 15, count 0 2006.173.02:52:12.64#ibcon#read 4, iclass 15, count 0 2006.173.02:52:12.64#ibcon#about to read 5, iclass 15, count 0 2006.173.02:52:12.64#ibcon#read 5, iclass 15, count 0 2006.173.02:52:12.64#ibcon#about to read 6, iclass 15, count 0 2006.173.02:52:12.64#ibcon#read 6, iclass 15, count 0 2006.173.02:52:12.64#ibcon#end of sib2, iclass 15, count 0 2006.173.02:52:12.64#ibcon#*after write, iclass 15, count 0 2006.173.02:52:12.64#ibcon#*before return 0, iclass 15, count 0 2006.173.02:52:12.64#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.02:52:12.64#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.02:52:12.64#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.02:52:12.64#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.02:52:12.64$vck44/vbbw=wide 2006.173.02:52:12.64#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.02:52:12.64#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.02:52:12.64#ibcon#ireg 8 cls_cnt 0 2006.173.02:52:12.64#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.02:52:12.71#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.02:52:12.71#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.02:52:12.71#ibcon#enter wrdev, iclass 17, count 0 2006.173.02:52:12.71#ibcon#first serial, iclass 17, count 0 2006.173.02:52:12.71#ibcon#enter sib2, iclass 17, count 0 2006.173.02:52:12.71#ibcon#flushed, iclass 17, count 0 2006.173.02:52:12.71#ibcon#about to write, iclass 17, count 0 2006.173.02:52:12.71#ibcon#wrote, iclass 17, count 0 2006.173.02:52:12.71#ibcon#about to read 3, iclass 17, count 0 2006.173.02:52:12.73#ibcon#read 3, iclass 17, count 0 2006.173.02:52:12.73#ibcon#about to read 4, iclass 17, count 0 2006.173.02:52:12.73#ibcon#read 4, iclass 17, count 0 2006.173.02:52:12.73#ibcon#about to read 5, iclass 17, count 0 2006.173.02:52:12.73#ibcon#read 5, iclass 17, count 0 2006.173.02:52:12.73#ibcon#about to read 6, iclass 17, count 0 2006.173.02:52:12.73#ibcon#read 6, iclass 17, count 0 2006.173.02:52:12.73#ibcon#end of sib2, iclass 17, count 0 2006.173.02:52:12.73#ibcon#*mode == 0, iclass 17, count 0 2006.173.02:52:12.73#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.02:52:12.73#ibcon#[27=BW32\r\n] 2006.173.02:52:12.73#ibcon#*before write, iclass 17, count 0 2006.173.02:52:12.73#ibcon#enter sib2, iclass 17, count 0 2006.173.02:52:12.73#ibcon#flushed, iclass 17, count 0 2006.173.02:52:12.73#ibcon#about to write, iclass 17, count 0 2006.173.02:52:12.73#ibcon#wrote, iclass 17, count 0 2006.173.02:52:12.73#ibcon#about to read 3, iclass 17, count 0 2006.173.02:52:12.76#ibcon#read 3, iclass 17, count 0 2006.173.02:52:12.76#ibcon#about to read 4, iclass 17, count 0 2006.173.02:52:12.76#ibcon#read 4, iclass 17, count 0 2006.173.02:52:12.76#ibcon#about to read 5, iclass 17, count 0 2006.173.02:52:12.76#ibcon#read 5, iclass 17, count 0 2006.173.02:52:12.76#ibcon#about to read 6, iclass 17, count 0 2006.173.02:52:12.76#ibcon#read 6, iclass 17, count 0 2006.173.02:52:12.76#ibcon#end of sib2, iclass 17, count 0 2006.173.02:52:12.76#ibcon#*after write, iclass 17, count 0 2006.173.02:52:12.76#ibcon#*before return 0, iclass 17, count 0 2006.173.02:52:12.76#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.02:52:12.76#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.02:52:12.76#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.02:52:12.76#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.02:52:12.76$setupk4/ifdk4 2006.173.02:52:12.76$ifdk4/lo= 2006.173.02:52:12.76$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.02:52:12.76$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.02:52:12.76$ifdk4/patch= 2006.173.02:52:12.76$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.02:52:12.76$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.02:52:12.76$setupk4/!*+20s 2006.173.02:52:17.18#abcon#<5=/15 1.2 2.5 22.48 841006.4\r\n> 2006.173.02:52:17.20#abcon#{5=INTERFACE CLEAR} 2006.173.02:52:17.26#abcon#[5=S1D000X0/0*\r\n] 2006.173.02:52:20.14#trakl#Source acquired 2006.173.02:52:22.14#flagr#flagr/antenna,acquired 2006.173.02:52:27.26$setupk4/"tpicd 2006.173.02:52:27.26$setupk4/echo=off 2006.173.02:52:27.26$setupk4/xlog=off 2006.173.02:52:27.26:!2006.173.02:52:21 2006.173.02:52:27.26:preob 2006.173.02:52:29.14/onsource/TRACKING 2006.173.02:52:29.14:!2006.173.02:52:31 2006.173.02:52:31.00:"tape 2006.173.02:52:31.00:"st=record 2006.173.02:52:31.00:data_valid=on 2006.173.02:52:31.00:midob 2006.173.02:52:31.14/onsource/TRACKING 2006.173.02:52:31.14/wx/22.48,1006.4,84 2006.173.02:52:31.25/cable/+6.5098E-03 2006.173.02:52:32.34/va/01,07,usb,yes,39,42 2006.173.02:52:32.34/va/02,06,usb,yes,39,40 2006.173.02:52:32.34/va/03,05,usb,yes,50,52 2006.173.02:52:32.34/va/04,06,usb,yes,40,42 2006.173.02:52:32.34/va/05,04,usb,yes,32,32 2006.173.02:52:32.34/va/06,03,usb,yes,44,44 2006.173.02:52:32.34/va/07,04,usb,yes,36,37 2006.173.02:52:32.34/va/08,04,usb,yes,30,37 2006.173.02:52:32.57/valo/01,524.99,yes,locked 2006.173.02:52:32.57/valo/02,534.99,yes,locked 2006.173.02:52:32.57/valo/03,564.99,yes,locked 2006.173.02:52:32.57/valo/04,624.99,yes,locked 2006.173.02:52:32.57/valo/05,734.99,yes,locked 2006.173.02:52:32.57/valo/06,814.99,yes,locked 2006.173.02:52:32.57/valo/07,864.99,yes,locked 2006.173.02:52:32.57/valo/08,884.99,yes,locked 2006.173.02:52:33.66/vb/01,04,usb,yes,31,29 2006.173.02:52:33.66/vb/02,04,usb,yes,34,34 2006.173.02:52:33.66/vb/03,04,usb,yes,31,34 2006.173.02:52:33.66/vb/04,04,usb,yes,35,34 2006.173.02:52:33.66/vb/05,04,usb,yes,28,30 2006.173.02:52:33.66/vb/06,04,usb,yes,32,28 2006.173.02:52:33.66/vb/07,04,usb,yes,32,32 2006.173.02:52:33.66/vb/08,04,usb,yes,29,33 2006.173.02:52:33.89/vblo/01,629.99,yes,locked 2006.173.02:52:33.89/vblo/02,634.99,yes,locked 2006.173.02:52:33.89/vblo/03,649.99,yes,locked 2006.173.02:52:33.89/vblo/04,679.99,yes,locked 2006.173.02:52:33.89/vblo/05,709.99,yes,locked 2006.173.02:52:33.89/vblo/06,719.99,yes,locked 2006.173.02:52:33.89/vblo/07,734.99,yes,locked 2006.173.02:52:33.89/vblo/08,744.99,yes,locked 2006.173.02:52:34.04/vabw/8 2006.173.02:52:34.19/vbbw/8 2006.173.02:52:34.28/xfe/off,on,15.0 2006.173.02:52:34.66/ifatt/23,28,28,28 2006.173.02:52:35.07/fmout-gps/S +3.90E-07 2006.173.02:52:35.15:!2006.173.03:04:31 2006.173.03:04:31.00:data_valid=off 2006.173.03:04:31.00:"et 2006.173.03:04:31.00:!+3s 2006.173.03:04:34.01:"tape 2006.173.03:04:34.01:postob 2006.173.03:04:34.20/cable/+6.5097E-03 2006.173.03:04:34.20/wx/22.30,1006.4,84 2006.173.03:04:35.08/fmout-gps/S +3.92E-07 2006.173.03:04:35.08:scan_name=173-0306,jd0606,310 2006.173.03:04:35.08:source=nrao150,035929.75,505750.2,2000.0,ccw 2006.173.03:04:36.14#flagr#flagr/antenna,new-source 2006.173.03:04:36.14:checkk5 2006.173.03:04:36.50/chk_autoobs//k5ts1/ autoobs is running! 2006.173.03:04:36.84/chk_autoobs//k5ts2/ autoobs is running! 2006.173.03:04:37.19/chk_autoobs//k5ts3/ autoobs is running! 2006.173.03:04:37.54/chk_autoobs//k5ts4/ autoobs is running! 2006.173.03:04:38.18/chk_obsdata//k5ts1/T1730252??a.dat file size is correct (nominal:2880MB, actual:2876MB). 2006.173.03:04:38.80/chk_obsdata//k5ts2/T1730252??b.dat file size is correct (nominal:2880MB, actual:2876MB). 2006.173.03:04:39.45/chk_obsdata//k5ts3/T1730252??c.dat file size is correct (nominal:2880MB, actual:2876MB). 2006.173.03:04:40.09/chk_obsdata//k5ts4/T1730252??d.dat file size is correct (nominal:2880MB, actual:2876MB). 2006.173.03:04:40.75/k5log//k5ts1_log_newline 2006.173.03:04:41.40/k5log//k5ts2_log_newline 2006.173.03:04:42.06/k5log//k5ts3_log_newline 2006.173.03:04:42.71/k5log//k5ts4_log_newline 2006.173.03:04:42.74/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.03:04:42.74:setupk4=1 2006.173.03:04:42.74$setupk4/echo=on 2006.173.03:04:42.74$setupk4/pcalon 2006.173.03:04:42.74$pcalon/"no phase cal control is implemented here 2006.173.03:04:42.74$setupk4/"tpicd=stop 2006.173.03:04:42.74$setupk4/"rec=synch_on 2006.173.03:04:42.74$setupk4/"rec_mode=128 2006.173.03:04:42.74$setupk4/!* 2006.173.03:04:42.74$setupk4/recpk4 2006.173.03:04:42.74$recpk4/recpatch= 2006.173.03:04:42.75$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.03:04:42.75$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.03:04:42.75$setupk4/vck44 2006.173.03:04:42.75$vck44/valo=1,524.99 2006.173.03:04:42.75#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.03:04:42.75#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.03:04:42.75#ibcon#ireg 17 cls_cnt 0 2006.173.03:04:42.75#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.03:04:42.75#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.03:04:42.75#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.03:04:42.75#ibcon#enter wrdev, iclass 30, count 0 2006.173.03:04:42.75#ibcon#first serial, iclass 30, count 0 2006.173.03:04:42.75#ibcon#enter sib2, iclass 30, count 0 2006.173.03:04:42.75#ibcon#flushed, iclass 30, count 0 2006.173.03:04:42.75#ibcon#about to write, iclass 30, count 0 2006.173.03:04:42.75#ibcon#wrote, iclass 30, count 0 2006.173.03:04:42.75#ibcon#about to read 3, iclass 30, count 0 2006.173.03:04:42.77#ibcon#read 3, iclass 30, count 0 2006.173.03:04:42.77#ibcon#about to read 4, iclass 30, count 0 2006.173.03:04:42.77#ibcon#read 4, iclass 30, count 0 2006.173.03:04:42.77#ibcon#about to read 5, iclass 30, count 0 2006.173.03:04:42.77#ibcon#read 5, iclass 30, count 0 2006.173.03:04:42.77#ibcon#about to read 6, iclass 30, count 0 2006.173.03:04:42.77#ibcon#read 6, iclass 30, count 0 2006.173.03:04:42.77#ibcon#end of sib2, iclass 30, count 0 2006.173.03:04:42.77#ibcon#*mode == 0, iclass 30, count 0 2006.173.03:04:42.77#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.03:04:42.77#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.03:04:42.77#ibcon#*before write, iclass 30, count 0 2006.173.03:04:42.77#ibcon#enter sib2, iclass 30, count 0 2006.173.03:04:42.77#ibcon#flushed, iclass 30, count 0 2006.173.03:04:42.77#ibcon#about to write, iclass 30, count 0 2006.173.03:04:42.77#ibcon#wrote, iclass 30, count 0 2006.173.03:04:42.77#ibcon#about to read 3, iclass 30, count 0 2006.173.03:04:42.82#ibcon#read 3, iclass 30, count 0 2006.173.03:04:42.82#ibcon#about to read 4, iclass 30, count 0 2006.173.03:04:42.82#ibcon#read 4, iclass 30, count 0 2006.173.03:04:42.82#ibcon#about to read 5, iclass 30, count 0 2006.173.03:04:42.82#ibcon#read 5, iclass 30, count 0 2006.173.03:04:42.82#ibcon#about to read 6, iclass 30, count 0 2006.173.03:04:42.82#ibcon#read 6, iclass 30, count 0 2006.173.03:04:42.82#ibcon#end of sib2, iclass 30, count 0 2006.173.03:04:42.82#ibcon#*after write, iclass 30, count 0 2006.173.03:04:42.82#ibcon#*before return 0, iclass 30, count 0 2006.173.03:04:42.82#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.03:04:42.82#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.03:04:42.82#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.03:04:42.82#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.03:04:42.82$vck44/va=1,7 2006.173.03:04:42.82#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.173.03:04:42.82#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.173.03:04:42.82#ibcon#ireg 11 cls_cnt 2 2006.173.03:04:42.82#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.03:04:42.82#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.03:04:42.82#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.03:04:42.82#ibcon#enter wrdev, iclass 32, count 2 2006.173.03:04:42.82#ibcon#first serial, iclass 32, count 2 2006.173.03:04:42.82#ibcon#enter sib2, iclass 32, count 2 2006.173.03:04:42.82#ibcon#flushed, iclass 32, count 2 2006.173.03:04:42.82#ibcon#about to write, iclass 32, count 2 2006.173.03:04:42.82#ibcon#wrote, iclass 32, count 2 2006.173.03:04:42.82#ibcon#about to read 3, iclass 32, count 2 2006.173.03:04:42.84#ibcon#read 3, iclass 32, count 2 2006.173.03:04:42.84#ibcon#about to read 4, iclass 32, count 2 2006.173.03:04:42.84#ibcon#read 4, iclass 32, count 2 2006.173.03:04:42.84#ibcon#about to read 5, iclass 32, count 2 2006.173.03:04:42.84#ibcon#read 5, iclass 32, count 2 2006.173.03:04:42.84#ibcon#about to read 6, iclass 32, count 2 2006.173.03:04:42.84#ibcon#read 6, iclass 32, count 2 2006.173.03:04:42.84#ibcon#end of sib2, iclass 32, count 2 2006.173.03:04:42.84#ibcon#*mode == 0, iclass 32, count 2 2006.173.03:04:42.84#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.173.03:04:42.84#ibcon#[25=AT01-07\r\n] 2006.173.03:04:42.84#ibcon#*before write, iclass 32, count 2 2006.173.03:04:42.84#ibcon#enter sib2, iclass 32, count 2 2006.173.03:04:42.84#ibcon#flushed, iclass 32, count 2 2006.173.03:04:42.84#ibcon#about to write, iclass 32, count 2 2006.173.03:04:42.84#ibcon#wrote, iclass 32, count 2 2006.173.03:04:42.84#ibcon#about to read 3, iclass 32, count 2 2006.173.03:04:42.87#ibcon#read 3, iclass 32, count 2 2006.173.03:04:42.87#ibcon#about to read 4, iclass 32, count 2 2006.173.03:04:42.87#ibcon#read 4, iclass 32, count 2 2006.173.03:04:42.87#ibcon#about to read 5, iclass 32, count 2 2006.173.03:04:42.87#ibcon#read 5, iclass 32, count 2 2006.173.03:04:42.87#ibcon#about to read 6, iclass 32, count 2 2006.173.03:04:42.87#ibcon#read 6, iclass 32, count 2 2006.173.03:04:42.87#ibcon#end of sib2, iclass 32, count 2 2006.173.03:04:42.87#ibcon#*after write, iclass 32, count 2 2006.173.03:04:42.87#ibcon#*before return 0, iclass 32, count 2 2006.173.03:04:42.87#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.03:04:42.87#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.173.03:04:42.87#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.173.03:04:42.87#ibcon#ireg 7 cls_cnt 0 2006.173.03:04:42.87#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.03:04:42.99#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.03:04:42.99#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.03:04:42.99#ibcon#enter wrdev, iclass 32, count 0 2006.173.03:04:42.99#ibcon#first serial, iclass 32, count 0 2006.173.03:04:42.99#ibcon#enter sib2, iclass 32, count 0 2006.173.03:04:42.99#ibcon#flushed, iclass 32, count 0 2006.173.03:04:42.99#ibcon#about to write, iclass 32, count 0 2006.173.03:04:42.99#ibcon#wrote, iclass 32, count 0 2006.173.03:04:42.99#ibcon#about to read 3, iclass 32, count 0 2006.173.03:04:43.01#ibcon#read 3, iclass 32, count 0 2006.173.03:04:43.01#ibcon#about to read 4, iclass 32, count 0 2006.173.03:04:43.01#ibcon#read 4, iclass 32, count 0 2006.173.03:04:43.01#ibcon#about to read 5, iclass 32, count 0 2006.173.03:04:43.01#ibcon#read 5, iclass 32, count 0 2006.173.03:04:43.01#ibcon#about to read 6, iclass 32, count 0 2006.173.03:04:43.01#ibcon#read 6, iclass 32, count 0 2006.173.03:04:43.01#ibcon#end of sib2, iclass 32, count 0 2006.173.03:04:43.01#ibcon#*mode == 0, iclass 32, count 0 2006.173.03:04:43.01#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.03:04:43.01#ibcon#[25=USB\r\n] 2006.173.03:04:43.01#ibcon#*before write, iclass 32, count 0 2006.173.03:04:43.01#ibcon#enter sib2, iclass 32, count 0 2006.173.03:04:43.01#ibcon#flushed, iclass 32, count 0 2006.173.03:04:43.01#ibcon#about to write, iclass 32, count 0 2006.173.03:04:43.01#ibcon#wrote, iclass 32, count 0 2006.173.03:04:43.01#ibcon#about to read 3, iclass 32, count 0 2006.173.03:04:43.04#ibcon#read 3, iclass 32, count 0 2006.173.03:04:43.04#ibcon#about to read 4, iclass 32, count 0 2006.173.03:04:43.04#ibcon#read 4, iclass 32, count 0 2006.173.03:04:43.04#ibcon#about to read 5, iclass 32, count 0 2006.173.03:04:43.04#ibcon#read 5, iclass 32, count 0 2006.173.03:04:43.04#ibcon#about to read 6, iclass 32, count 0 2006.173.03:04:43.04#ibcon#read 6, iclass 32, count 0 2006.173.03:04:43.04#ibcon#end of sib2, iclass 32, count 0 2006.173.03:04:43.04#ibcon#*after write, iclass 32, count 0 2006.173.03:04:43.04#ibcon#*before return 0, iclass 32, count 0 2006.173.03:04:43.04#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.03:04:43.04#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.173.03:04:43.04#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.03:04:43.04#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.03:04:43.04$vck44/valo=2,534.99 2006.173.03:04:43.04#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.03:04:43.04#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.03:04:43.04#ibcon#ireg 17 cls_cnt 0 2006.173.03:04:43.04#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.03:04:43.04#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.03:04:43.04#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.03:04:43.04#ibcon#enter wrdev, iclass 34, count 0 2006.173.03:04:43.04#ibcon#first serial, iclass 34, count 0 2006.173.03:04:43.04#ibcon#enter sib2, iclass 34, count 0 2006.173.03:04:43.04#ibcon#flushed, iclass 34, count 0 2006.173.03:04:43.04#ibcon#about to write, iclass 34, count 0 2006.173.03:04:43.04#ibcon#wrote, iclass 34, count 0 2006.173.03:04:43.04#ibcon#about to read 3, iclass 34, count 0 2006.173.03:04:43.06#ibcon#read 3, iclass 34, count 0 2006.173.03:04:43.06#ibcon#about to read 4, iclass 34, count 0 2006.173.03:04:43.06#ibcon#read 4, iclass 34, count 0 2006.173.03:04:43.06#ibcon#about to read 5, iclass 34, count 0 2006.173.03:04:43.06#ibcon#read 5, iclass 34, count 0 2006.173.03:04:43.06#ibcon#about to read 6, iclass 34, count 0 2006.173.03:04:43.06#ibcon#read 6, iclass 34, count 0 2006.173.03:04:43.06#ibcon#end of sib2, iclass 34, count 0 2006.173.03:04:43.06#ibcon#*mode == 0, iclass 34, count 0 2006.173.03:04:43.06#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.03:04:43.06#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.03:04:43.06#ibcon#*before write, iclass 34, count 0 2006.173.03:04:43.06#ibcon#enter sib2, iclass 34, count 0 2006.173.03:04:43.06#ibcon#flushed, iclass 34, count 0 2006.173.03:04:43.06#ibcon#about to write, iclass 34, count 0 2006.173.03:04:43.06#ibcon#wrote, iclass 34, count 0 2006.173.03:04:43.06#ibcon#about to read 3, iclass 34, count 0 2006.173.03:04:43.10#ibcon#read 3, iclass 34, count 0 2006.173.03:04:43.10#ibcon#about to read 4, iclass 34, count 0 2006.173.03:04:43.10#ibcon#read 4, iclass 34, count 0 2006.173.03:04:43.10#ibcon#about to read 5, iclass 34, count 0 2006.173.03:04:43.10#ibcon#read 5, iclass 34, count 0 2006.173.03:04:43.10#ibcon#about to read 6, iclass 34, count 0 2006.173.03:04:43.10#ibcon#read 6, iclass 34, count 0 2006.173.03:04:43.10#ibcon#end of sib2, iclass 34, count 0 2006.173.03:04:43.10#ibcon#*after write, iclass 34, count 0 2006.173.03:04:43.10#ibcon#*before return 0, iclass 34, count 0 2006.173.03:04:43.10#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.03:04:43.10#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.03:04:43.10#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.03:04:43.10#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.03:04:43.10$vck44/va=2,6 2006.173.03:04:43.10#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.03:04:43.10#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.03:04:43.10#ibcon#ireg 11 cls_cnt 2 2006.173.03:04:43.10#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.03:04:43.16#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.03:04:43.16#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.03:04:43.16#ibcon#enter wrdev, iclass 36, count 2 2006.173.03:04:43.16#ibcon#first serial, iclass 36, count 2 2006.173.03:04:43.16#ibcon#enter sib2, iclass 36, count 2 2006.173.03:04:43.16#ibcon#flushed, iclass 36, count 2 2006.173.03:04:43.16#ibcon#about to write, iclass 36, count 2 2006.173.03:04:43.16#ibcon#wrote, iclass 36, count 2 2006.173.03:04:43.16#ibcon#about to read 3, iclass 36, count 2 2006.173.03:04:43.18#ibcon#read 3, iclass 36, count 2 2006.173.03:04:43.18#ibcon#about to read 4, iclass 36, count 2 2006.173.03:04:43.18#ibcon#read 4, iclass 36, count 2 2006.173.03:04:43.18#ibcon#about to read 5, iclass 36, count 2 2006.173.03:04:43.18#ibcon#read 5, iclass 36, count 2 2006.173.03:04:43.18#ibcon#about to read 6, iclass 36, count 2 2006.173.03:04:43.18#ibcon#read 6, iclass 36, count 2 2006.173.03:04:43.18#ibcon#end of sib2, iclass 36, count 2 2006.173.03:04:43.18#ibcon#*mode == 0, iclass 36, count 2 2006.173.03:04:43.18#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.03:04:43.18#ibcon#[25=AT02-06\r\n] 2006.173.03:04:43.18#ibcon#*before write, iclass 36, count 2 2006.173.03:04:43.18#ibcon#enter sib2, iclass 36, count 2 2006.173.03:04:43.18#ibcon#flushed, iclass 36, count 2 2006.173.03:04:43.18#ibcon#about to write, iclass 36, count 2 2006.173.03:04:43.18#ibcon#wrote, iclass 36, count 2 2006.173.03:04:43.18#ibcon#about to read 3, iclass 36, count 2 2006.173.03:04:43.21#ibcon#read 3, iclass 36, count 2 2006.173.03:04:43.21#ibcon#about to read 4, iclass 36, count 2 2006.173.03:04:43.21#ibcon#read 4, iclass 36, count 2 2006.173.03:04:43.21#ibcon#about to read 5, iclass 36, count 2 2006.173.03:04:43.21#ibcon#read 5, iclass 36, count 2 2006.173.03:04:43.21#ibcon#about to read 6, iclass 36, count 2 2006.173.03:04:43.21#ibcon#read 6, iclass 36, count 2 2006.173.03:04:43.21#ibcon#end of sib2, iclass 36, count 2 2006.173.03:04:43.21#ibcon#*after write, iclass 36, count 2 2006.173.03:04:43.21#ibcon#*before return 0, iclass 36, count 2 2006.173.03:04:43.21#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.03:04:43.21#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.03:04:43.21#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.03:04:43.21#ibcon#ireg 7 cls_cnt 0 2006.173.03:04:43.21#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.03:04:43.33#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.03:04:43.33#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.03:04:43.33#ibcon#enter wrdev, iclass 36, count 0 2006.173.03:04:43.33#ibcon#first serial, iclass 36, count 0 2006.173.03:04:43.33#ibcon#enter sib2, iclass 36, count 0 2006.173.03:04:43.33#ibcon#flushed, iclass 36, count 0 2006.173.03:04:43.33#ibcon#about to write, iclass 36, count 0 2006.173.03:04:43.33#ibcon#wrote, iclass 36, count 0 2006.173.03:04:43.33#ibcon#about to read 3, iclass 36, count 0 2006.173.03:04:43.35#ibcon#read 3, iclass 36, count 0 2006.173.03:04:43.35#ibcon#about to read 4, iclass 36, count 0 2006.173.03:04:43.35#ibcon#read 4, iclass 36, count 0 2006.173.03:04:43.35#ibcon#about to read 5, iclass 36, count 0 2006.173.03:04:43.35#ibcon#read 5, iclass 36, count 0 2006.173.03:04:43.35#ibcon#about to read 6, iclass 36, count 0 2006.173.03:04:43.35#ibcon#read 6, iclass 36, count 0 2006.173.03:04:43.35#ibcon#end of sib2, iclass 36, count 0 2006.173.03:04:43.35#ibcon#*mode == 0, iclass 36, count 0 2006.173.03:04:43.35#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.03:04:43.35#ibcon#[25=USB\r\n] 2006.173.03:04:43.35#ibcon#*before write, iclass 36, count 0 2006.173.03:04:43.35#ibcon#enter sib2, iclass 36, count 0 2006.173.03:04:43.35#ibcon#flushed, iclass 36, count 0 2006.173.03:04:43.35#ibcon#about to write, iclass 36, count 0 2006.173.03:04:43.35#ibcon#wrote, iclass 36, count 0 2006.173.03:04:43.35#ibcon#about to read 3, iclass 36, count 0 2006.173.03:04:43.38#ibcon#read 3, iclass 36, count 0 2006.173.03:04:43.38#ibcon#about to read 4, iclass 36, count 0 2006.173.03:04:43.38#ibcon#read 4, iclass 36, count 0 2006.173.03:04:43.38#ibcon#about to read 5, iclass 36, count 0 2006.173.03:04:43.38#ibcon#read 5, iclass 36, count 0 2006.173.03:04:43.38#ibcon#about to read 6, iclass 36, count 0 2006.173.03:04:43.38#ibcon#read 6, iclass 36, count 0 2006.173.03:04:43.38#ibcon#end of sib2, iclass 36, count 0 2006.173.03:04:43.38#ibcon#*after write, iclass 36, count 0 2006.173.03:04:43.38#ibcon#*before return 0, iclass 36, count 0 2006.173.03:04:43.38#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.03:04:43.38#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.03:04:43.38#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.03:04:43.38#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.03:04:43.38$vck44/valo=3,564.99 2006.173.03:04:43.38#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.03:04:43.38#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.03:04:43.38#ibcon#ireg 17 cls_cnt 0 2006.173.03:04:43.38#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.03:04:43.38#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.03:04:43.38#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.03:04:43.38#ibcon#enter wrdev, iclass 38, count 0 2006.173.03:04:43.38#ibcon#first serial, iclass 38, count 0 2006.173.03:04:43.38#ibcon#enter sib2, iclass 38, count 0 2006.173.03:04:43.38#ibcon#flushed, iclass 38, count 0 2006.173.03:04:43.38#ibcon#about to write, iclass 38, count 0 2006.173.03:04:43.38#ibcon#wrote, iclass 38, count 0 2006.173.03:04:43.38#ibcon#about to read 3, iclass 38, count 0 2006.173.03:04:43.40#ibcon#read 3, iclass 38, count 0 2006.173.03:04:43.40#ibcon#about to read 4, iclass 38, count 0 2006.173.03:04:43.40#ibcon#read 4, iclass 38, count 0 2006.173.03:04:43.40#ibcon#about to read 5, iclass 38, count 0 2006.173.03:04:43.40#ibcon#read 5, iclass 38, count 0 2006.173.03:04:43.40#ibcon#about to read 6, iclass 38, count 0 2006.173.03:04:43.40#ibcon#read 6, iclass 38, count 0 2006.173.03:04:43.40#ibcon#end of sib2, iclass 38, count 0 2006.173.03:04:43.40#ibcon#*mode == 0, iclass 38, count 0 2006.173.03:04:43.40#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.03:04:43.40#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.03:04:43.40#ibcon#*before write, iclass 38, count 0 2006.173.03:04:43.40#ibcon#enter sib2, iclass 38, count 0 2006.173.03:04:43.40#ibcon#flushed, iclass 38, count 0 2006.173.03:04:43.40#ibcon#about to write, iclass 38, count 0 2006.173.03:04:43.40#ibcon#wrote, iclass 38, count 0 2006.173.03:04:43.40#ibcon#about to read 3, iclass 38, count 0 2006.173.03:04:43.44#ibcon#read 3, iclass 38, count 0 2006.173.03:04:43.44#ibcon#about to read 4, iclass 38, count 0 2006.173.03:04:43.44#ibcon#read 4, iclass 38, count 0 2006.173.03:04:43.44#ibcon#about to read 5, iclass 38, count 0 2006.173.03:04:43.44#ibcon#read 5, iclass 38, count 0 2006.173.03:04:43.44#ibcon#about to read 6, iclass 38, count 0 2006.173.03:04:43.44#ibcon#read 6, iclass 38, count 0 2006.173.03:04:43.44#ibcon#end of sib2, iclass 38, count 0 2006.173.03:04:43.44#ibcon#*after write, iclass 38, count 0 2006.173.03:04:43.44#ibcon#*before return 0, iclass 38, count 0 2006.173.03:04:43.44#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.03:04:43.44#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.03:04:43.44#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.03:04:43.44#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.03:04:43.44$vck44/va=3,5 2006.173.03:04:43.44#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.03:04:43.44#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.03:04:43.44#ibcon#ireg 11 cls_cnt 2 2006.173.03:04:43.44#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.03:04:43.50#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.03:04:43.50#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.03:04:43.50#ibcon#enter wrdev, iclass 40, count 2 2006.173.03:04:43.50#ibcon#first serial, iclass 40, count 2 2006.173.03:04:43.50#ibcon#enter sib2, iclass 40, count 2 2006.173.03:04:43.50#ibcon#flushed, iclass 40, count 2 2006.173.03:04:43.50#ibcon#about to write, iclass 40, count 2 2006.173.03:04:43.50#ibcon#wrote, iclass 40, count 2 2006.173.03:04:43.50#ibcon#about to read 3, iclass 40, count 2 2006.173.03:04:43.52#ibcon#read 3, iclass 40, count 2 2006.173.03:04:43.52#ibcon#about to read 4, iclass 40, count 2 2006.173.03:04:43.52#ibcon#read 4, iclass 40, count 2 2006.173.03:04:43.52#ibcon#about to read 5, iclass 40, count 2 2006.173.03:04:43.52#ibcon#read 5, iclass 40, count 2 2006.173.03:04:43.52#ibcon#about to read 6, iclass 40, count 2 2006.173.03:04:43.52#ibcon#read 6, iclass 40, count 2 2006.173.03:04:43.52#ibcon#end of sib2, iclass 40, count 2 2006.173.03:04:43.52#ibcon#*mode == 0, iclass 40, count 2 2006.173.03:04:43.52#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.03:04:43.52#ibcon#[25=AT03-05\r\n] 2006.173.03:04:43.52#ibcon#*before write, iclass 40, count 2 2006.173.03:04:43.52#ibcon#enter sib2, iclass 40, count 2 2006.173.03:04:43.52#ibcon#flushed, iclass 40, count 2 2006.173.03:04:43.52#ibcon#about to write, iclass 40, count 2 2006.173.03:04:43.52#ibcon#wrote, iclass 40, count 2 2006.173.03:04:43.52#ibcon#about to read 3, iclass 40, count 2 2006.173.03:04:43.55#ibcon#read 3, iclass 40, count 2 2006.173.03:04:43.55#ibcon#about to read 4, iclass 40, count 2 2006.173.03:04:43.55#ibcon#read 4, iclass 40, count 2 2006.173.03:04:43.55#ibcon#about to read 5, iclass 40, count 2 2006.173.03:04:43.55#ibcon#read 5, iclass 40, count 2 2006.173.03:04:43.55#ibcon#about to read 6, iclass 40, count 2 2006.173.03:04:43.55#ibcon#read 6, iclass 40, count 2 2006.173.03:04:43.55#ibcon#end of sib2, iclass 40, count 2 2006.173.03:04:43.55#ibcon#*after write, iclass 40, count 2 2006.173.03:04:43.55#ibcon#*before return 0, iclass 40, count 2 2006.173.03:04:43.55#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.03:04:43.55#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.03:04:43.55#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.03:04:43.55#ibcon#ireg 7 cls_cnt 0 2006.173.03:04:43.55#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.03:04:43.67#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.03:04:43.67#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.03:04:43.67#ibcon#enter wrdev, iclass 40, count 0 2006.173.03:04:43.67#ibcon#first serial, iclass 40, count 0 2006.173.03:04:43.67#ibcon#enter sib2, iclass 40, count 0 2006.173.03:04:43.67#ibcon#flushed, iclass 40, count 0 2006.173.03:04:43.67#ibcon#about to write, iclass 40, count 0 2006.173.03:04:43.67#ibcon#wrote, iclass 40, count 0 2006.173.03:04:43.67#ibcon#about to read 3, iclass 40, count 0 2006.173.03:04:43.69#ibcon#read 3, iclass 40, count 0 2006.173.03:04:43.69#ibcon#about to read 4, iclass 40, count 0 2006.173.03:04:43.69#ibcon#read 4, iclass 40, count 0 2006.173.03:04:43.69#ibcon#about to read 5, iclass 40, count 0 2006.173.03:04:43.69#ibcon#read 5, iclass 40, count 0 2006.173.03:04:43.69#ibcon#about to read 6, iclass 40, count 0 2006.173.03:04:43.69#ibcon#read 6, iclass 40, count 0 2006.173.03:04:43.69#ibcon#end of sib2, iclass 40, count 0 2006.173.03:04:43.69#ibcon#*mode == 0, iclass 40, count 0 2006.173.03:04:43.69#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.03:04:43.69#ibcon#[25=USB\r\n] 2006.173.03:04:43.69#ibcon#*before write, iclass 40, count 0 2006.173.03:04:43.69#ibcon#enter sib2, iclass 40, count 0 2006.173.03:04:43.69#ibcon#flushed, iclass 40, count 0 2006.173.03:04:43.69#ibcon#about to write, iclass 40, count 0 2006.173.03:04:43.69#ibcon#wrote, iclass 40, count 0 2006.173.03:04:43.69#ibcon#about to read 3, iclass 40, count 0 2006.173.03:04:43.72#ibcon#read 3, iclass 40, count 0 2006.173.03:04:43.72#ibcon#about to read 4, iclass 40, count 0 2006.173.03:04:43.72#ibcon#read 4, iclass 40, count 0 2006.173.03:04:43.72#ibcon#about to read 5, iclass 40, count 0 2006.173.03:04:43.72#ibcon#read 5, iclass 40, count 0 2006.173.03:04:43.72#ibcon#about to read 6, iclass 40, count 0 2006.173.03:04:43.72#ibcon#read 6, iclass 40, count 0 2006.173.03:04:43.72#ibcon#end of sib2, iclass 40, count 0 2006.173.03:04:43.72#ibcon#*after write, iclass 40, count 0 2006.173.03:04:43.72#ibcon#*before return 0, iclass 40, count 0 2006.173.03:04:43.72#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.03:04:43.72#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.03:04:43.72#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.03:04:43.72#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.03:04:43.72$vck44/valo=4,624.99 2006.173.03:04:43.72#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.03:04:43.72#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.03:04:43.72#ibcon#ireg 17 cls_cnt 0 2006.173.03:04:43.72#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.03:04:43.72#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.03:04:43.72#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.03:04:43.72#ibcon#enter wrdev, iclass 4, count 0 2006.173.03:04:43.72#ibcon#first serial, iclass 4, count 0 2006.173.03:04:43.72#ibcon#enter sib2, iclass 4, count 0 2006.173.03:04:43.72#ibcon#flushed, iclass 4, count 0 2006.173.03:04:43.72#ibcon#about to write, iclass 4, count 0 2006.173.03:04:43.72#ibcon#wrote, iclass 4, count 0 2006.173.03:04:43.72#ibcon#about to read 3, iclass 4, count 0 2006.173.03:04:43.74#ibcon#read 3, iclass 4, count 0 2006.173.03:04:43.74#ibcon#about to read 4, iclass 4, count 0 2006.173.03:04:43.74#ibcon#read 4, iclass 4, count 0 2006.173.03:04:43.74#ibcon#about to read 5, iclass 4, count 0 2006.173.03:04:43.74#ibcon#read 5, iclass 4, count 0 2006.173.03:04:43.74#ibcon#about to read 6, iclass 4, count 0 2006.173.03:04:43.74#ibcon#read 6, iclass 4, count 0 2006.173.03:04:43.74#ibcon#end of sib2, iclass 4, count 0 2006.173.03:04:43.74#ibcon#*mode == 0, iclass 4, count 0 2006.173.03:04:43.74#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.03:04:43.74#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.03:04:43.74#ibcon#*before write, iclass 4, count 0 2006.173.03:04:43.74#ibcon#enter sib2, iclass 4, count 0 2006.173.03:04:43.74#ibcon#flushed, iclass 4, count 0 2006.173.03:04:43.74#ibcon#about to write, iclass 4, count 0 2006.173.03:04:43.74#ibcon#wrote, iclass 4, count 0 2006.173.03:04:43.74#ibcon#about to read 3, iclass 4, count 0 2006.173.03:04:43.78#ibcon#read 3, iclass 4, count 0 2006.173.03:04:43.78#ibcon#about to read 4, iclass 4, count 0 2006.173.03:04:43.78#ibcon#read 4, iclass 4, count 0 2006.173.03:04:43.78#ibcon#about to read 5, iclass 4, count 0 2006.173.03:04:43.78#ibcon#read 5, iclass 4, count 0 2006.173.03:04:43.78#ibcon#about to read 6, iclass 4, count 0 2006.173.03:04:43.78#ibcon#read 6, iclass 4, count 0 2006.173.03:04:43.78#ibcon#end of sib2, iclass 4, count 0 2006.173.03:04:43.78#ibcon#*after write, iclass 4, count 0 2006.173.03:04:43.78#ibcon#*before return 0, iclass 4, count 0 2006.173.03:04:43.78#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.03:04:43.78#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.03:04:43.78#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.03:04:43.78#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.03:04:43.78$vck44/va=4,6 2006.173.03:04:43.78#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.03:04:43.78#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.03:04:43.78#ibcon#ireg 11 cls_cnt 2 2006.173.03:04:43.78#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.03:04:43.84#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.03:04:43.84#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.03:04:43.84#ibcon#enter wrdev, iclass 6, count 2 2006.173.03:04:43.84#ibcon#first serial, iclass 6, count 2 2006.173.03:04:43.84#ibcon#enter sib2, iclass 6, count 2 2006.173.03:04:43.84#ibcon#flushed, iclass 6, count 2 2006.173.03:04:43.84#ibcon#about to write, iclass 6, count 2 2006.173.03:04:43.84#ibcon#wrote, iclass 6, count 2 2006.173.03:04:43.84#ibcon#about to read 3, iclass 6, count 2 2006.173.03:04:43.86#ibcon#read 3, iclass 6, count 2 2006.173.03:04:43.86#ibcon#about to read 4, iclass 6, count 2 2006.173.03:04:43.86#ibcon#read 4, iclass 6, count 2 2006.173.03:04:43.86#ibcon#about to read 5, iclass 6, count 2 2006.173.03:04:43.86#ibcon#read 5, iclass 6, count 2 2006.173.03:04:43.86#ibcon#about to read 6, iclass 6, count 2 2006.173.03:04:43.86#ibcon#read 6, iclass 6, count 2 2006.173.03:04:43.86#ibcon#end of sib2, iclass 6, count 2 2006.173.03:04:43.86#ibcon#*mode == 0, iclass 6, count 2 2006.173.03:04:43.86#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.03:04:43.86#ibcon#[25=AT04-06\r\n] 2006.173.03:04:43.86#ibcon#*before write, iclass 6, count 2 2006.173.03:04:43.86#ibcon#enter sib2, iclass 6, count 2 2006.173.03:04:43.86#ibcon#flushed, iclass 6, count 2 2006.173.03:04:43.86#ibcon#about to write, iclass 6, count 2 2006.173.03:04:43.86#ibcon#wrote, iclass 6, count 2 2006.173.03:04:43.86#ibcon#about to read 3, iclass 6, count 2 2006.173.03:04:43.89#ibcon#read 3, iclass 6, count 2 2006.173.03:04:43.89#ibcon#about to read 4, iclass 6, count 2 2006.173.03:04:43.89#ibcon#read 4, iclass 6, count 2 2006.173.03:04:43.89#ibcon#about to read 5, iclass 6, count 2 2006.173.03:04:43.89#ibcon#read 5, iclass 6, count 2 2006.173.03:04:43.89#ibcon#about to read 6, iclass 6, count 2 2006.173.03:04:43.89#ibcon#read 6, iclass 6, count 2 2006.173.03:04:43.89#ibcon#end of sib2, iclass 6, count 2 2006.173.03:04:43.89#ibcon#*after write, iclass 6, count 2 2006.173.03:04:43.89#ibcon#*before return 0, iclass 6, count 2 2006.173.03:04:43.89#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.03:04:43.89#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.03:04:43.89#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.03:04:43.89#ibcon#ireg 7 cls_cnt 0 2006.173.03:04:43.89#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.03:04:44.01#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.03:04:44.01#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.03:04:44.01#ibcon#enter wrdev, iclass 6, count 0 2006.173.03:04:44.01#ibcon#first serial, iclass 6, count 0 2006.173.03:04:44.01#ibcon#enter sib2, iclass 6, count 0 2006.173.03:04:44.01#ibcon#flushed, iclass 6, count 0 2006.173.03:04:44.01#ibcon#about to write, iclass 6, count 0 2006.173.03:04:44.01#ibcon#wrote, iclass 6, count 0 2006.173.03:04:44.01#ibcon#about to read 3, iclass 6, count 0 2006.173.03:04:44.03#ibcon#read 3, iclass 6, count 0 2006.173.03:04:44.03#ibcon#about to read 4, iclass 6, count 0 2006.173.03:04:44.03#ibcon#read 4, iclass 6, count 0 2006.173.03:04:44.03#ibcon#about to read 5, iclass 6, count 0 2006.173.03:04:44.03#ibcon#read 5, iclass 6, count 0 2006.173.03:04:44.03#ibcon#about to read 6, iclass 6, count 0 2006.173.03:04:44.03#ibcon#read 6, iclass 6, count 0 2006.173.03:04:44.03#ibcon#end of sib2, iclass 6, count 0 2006.173.03:04:44.03#ibcon#*mode == 0, iclass 6, count 0 2006.173.03:04:44.03#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.03:04:44.03#ibcon#[25=USB\r\n] 2006.173.03:04:44.03#ibcon#*before write, iclass 6, count 0 2006.173.03:04:44.03#ibcon#enter sib2, iclass 6, count 0 2006.173.03:04:44.03#ibcon#flushed, iclass 6, count 0 2006.173.03:04:44.03#ibcon#about to write, iclass 6, count 0 2006.173.03:04:44.03#ibcon#wrote, iclass 6, count 0 2006.173.03:04:44.03#ibcon#about to read 3, iclass 6, count 0 2006.173.03:04:44.06#ibcon#read 3, iclass 6, count 0 2006.173.03:04:44.06#ibcon#about to read 4, iclass 6, count 0 2006.173.03:04:44.06#ibcon#read 4, iclass 6, count 0 2006.173.03:04:44.06#ibcon#about to read 5, iclass 6, count 0 2006.173.03:04:44.06#ibcon#read 5, iclass 6, count 0 2006.173.03:04:44.06#ibcon#about to read 6, iclass 6, count 0 2006.173.03:04:44.06#ibcon#read 6, iclass 6, count 0 2006.173.03:04:44.06#ibcon#end of sib2, iclass 6, count 0 2006.173.03:04:44.06#ibcon#*after write, iclass 6, count 0 2006.173.03:04:44.06#ibcon#*before return 0, iclass 6, count 0 2006.173.03:04:44.06#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.03:04:44.06#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.03:04:44.06#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.03:04:44.06#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.03:04:44.06$vck44/valo=5,734.99 2006.173.03:04:44.06#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.03:04:44.06#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.03:04:44.06#ibcon#ireg 17 cls_cnt 0 2006.173.03:04:44.06#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.03:04:44.06#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.03:04:44.06#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.03:04:44.06#ibcon#enter wrdev, iclass 10, count 0 2006.173.03:04:44.06#ibcon#first serial, iclass 10, count 0 2006.173.03:04:44.06#ibcon#enter sib2, iclass 10, count 0 2006.173.03:04:44.06#ibcon#flushed, iclass 10, count 0 2006.173.03:04:44.06#ibcon#about to write, iclass 10, count 0 2006.173.03:04:44.06#ibcon#wrote, iclass 10, count 0 2006.173.03:04:44.06#ibcon#about to read 3, iclass 10, count 0 2006.173.03:04:44.08#ibcon#read 3, iclass 10, count 0 2006.173.03:04:44.08#ibcon#about to read 4, iclass 10, count 0 2006.173.03:04:44.08#ibcon#read 4, iclass 10, count 0 2006.173.03:04:44.08#ibcon#about to read 5, iclass 10, count 0 2006.173.03:04:44.08#ibcon#read 5, iclass 10, count 0 2006.173.03:04:44.08#ibcon#about to read 6, iclass 10, count 0 2006.173.03:04:44.08#ibcon#read 6, iclass 10, count 0 2006.173.03:04:44.08#ibcon#end of sib2, iclass 10, count 0 2006.173.03:04:44.08#ibcon#*mode == 0, iclass 10, count 0 2006.173.03:04:44.08#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.03:04:44.08#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.03:04:44.08#ibcon#*before write, iclass 10, count 0 2006.173.03:04:44.08#ibcon#enter sib2, iclass 10, count 0 2006.173.03:04:44.08#ibcon#flushed, iclass 10, count 0 2006.173.03:04:44.08#ibcon#about to write, iclass 10, count 0 2006.173.03:04:44.08#ibcon#wrote, iclass 10, count 0 2006.173.03:04:44.08#ibcon#about to read 3, iclass 10, count 0 2006.173.03:04:44.12#ibcon#read 3, iclass 10, count 0 2006.173.03:04:44.12#ibcon#about to read 4, iclass 10, count 0 2006.173.03:04:44.12#ibcon#read 4, iclass 10, count 0 2006.173.03:04:44.12#ibcon#about to read 5, iclass 10, count 0 2006.173.03:04:44.12#ibcon#read 5, iclass 10, count 0 2006.173.03:04:44.12#ibcon#about to read 6, iclass 10, count 0 2006.173.03:04:44.12#ibcon#read 6, iclass 10, count 0 2006.173.03:04:44.12#ibcon#end of sib2, iclass 10, count 0 2006.173.03:04:44.12#ibcon#*after write, iclass 10, count 0 2006.173.03:04:44.12#ibcon#*before return 0, iclass 10, count 0 2006.173.03:04:44.12#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.03:04:44.12#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.03:04:44.12#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.03:04:44.12#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.03:04:44.12$vck44/va=5,4 2006.173.03:04:44.12#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.03:04:44.12#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.03:04:44.12#ibcon#ireg 11 cls_cnt 2 2006.173.03:04:44.12#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.03:04:44.18#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.03:04:44.18#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.03:04:44.18#ibcon#enter wrdev, iclass 12, count 2 2006.173.03:04:44.18#ibcon#first serial, iclass 12, count 2 2006.173.03:04:44.18#ibcon#enter sib2, iclass 12, count 2 2006.173.03:04:44.18#ibcon#flushed, iclass 12, count 2 2006.173.03:04:44.18#ibcon#about to write, iclass 12, count 2 2006.173.03:04:44.18#ibcon#wrote, iclass 12, count 2 2006.173.03:04:44.18#ibcon#about to read 3, iclass 12, count 2 2006.173.03:04:44.20#ibcon#read 3, iclass 12, count 2 2006.173.03:04:44.20#ibcon#about to read 4, iclass 12, count 2 2006.173.03:04:44.20#ibcon#read 4, iclass 12, count 2 2006.173.03:04:44.20#ibcon#about to read 5, iclass 12, count 2 2006.173.03:04:44.20#ibcon#read 5, iclass 12, count 2 2006.173.03:04:44.20#ibcon#about to read 6, iclass 12, count 2 2006.173.03:04:44.20#ibcon#read 6, iclass 12, count 2 2006.173.03:04:44.20#ibcon#end of sib2, iclass 12, count 2 2006.173.03:04:44.20#ibcon#*mode == 0, iclass 12, count 2 2006.173.03:04:44.20#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.03:04:44.20#ibcon#[25=AT05-04\r\n] 2006.173.03:04:44.20#ibcon#*before write, iclass 12, count 2 2006.173.03:04:44.20#ibcon#enter sib2, iclass 12, count 2 2006.173.03:04:44.20#ibcon#flushed, iclass 12, count 2 2006.173.03:04:44.20#ibcon#about to write, iclass 12, count 2 2006.173.03:04:44.20#ibcon#wrote, iclass 12, count 2 2006.173.03:04:44.20#ibcon#about to read 3, iclass 12, count 2 2006.173.03:04:44.23#ibcon#read 3, iclass 12, count 2 2006.173.03:04:44.23#ibcon#about to read 4, iclass 12, count 2 2006.173.03:04:44.23#ibcon#read 4, iclass 12, count 2 2006.173.03:04:44.23#ibcon#about to read 5, iclass 12, count 2 2006.173.03:04:44.23#ibcon#read 5, iclass 12, count 2 2006.173.03:04:44.23#ibcon#about to read 6, iclass 12, count 2 2006.173.03:04:44.23#ibcon#read 6, iclass 12, count 2 2006.173.03:04:44.23#ibcon#end of sib2, iclass 12, count 2 2006.173.03:04:44.23#ibcon#*after write, iclass 12, count 2 2006.173.03:04:44.23#ibcon#*before return 0, iclass 12, count 2 2006.173.03:04:44.23#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.03:04:44.23#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.03:04:44.23#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.03:04:44.23#ibcon#ireg 7 cls_cnt 0 2006.173.03:04:44.23#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.03:04:44.35#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.03:04:44.35#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.03:04:44.35#ibcon#enter wrdev, iclass 12, count 0 2006.173.03:04:44.35#ibcon#first serial, iclass 12, count 0 2006.173.03:04:44.35#ibcon#enter sib2, iclass 12, count 0 2006.173.03:04:44.35#ibcon#flushed, iclass 12, count 0 2006.173.03:04:44.35#ibcon#about to write, iclass 12, count 0 2006.173.03:04:44.35#ibcon#wrote, iclass 12, count 0 2006.173.03:04:44.35#ibcon#about to read 3, iclass 12, count 0 2006.173.03:04:44.37#ibcon#read 3, iclass 12, count 0 2006.173.03:04:44.37#ibcon#about to read 4, iclass 12, count 0 2006.173.03:04:44.37#ibcon#read 4, iclass 12, count 0 2006.173.03:04:44.37#ibcon#about to read 5, iclass 12, count 0 2006.173.03:04:44.37#ibcon#read 5, iclass 12, count 0 2006.173.03:04:44.37#ibcon#about to read 6, iclass 12, count 0 2006.173.03:04:44.37#ibcon#read 6, iclass 12, count 0 2006.173.03:04:44.37#ibcon#end of sib2, iclass 12, count 0 2006.173.03:04:44.37#ibcon#*mode == 0, iclass 12, count 0 2006.173.03:04:44.37#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.03:04:44.37#ibcon#[25=USB\r\n] 2006.173.03:04:44.37#ibcon#*before write, iclass 12, count 0 2006.173.03:04:44.37#ibcon#enter sib2, iclass 12, count 0 2006.173.03:04:44.37#ibcon#flushed, iclass 12, count 0 2006.173.03:04:44.37#ibcon#about to write, iclass 12, count 0 2006.173.03:04:44.37#ibcon#wrote, iclass 12, count 0 2006.173.03:04:44.37#ibcon#about to read 3, iclass 12, count 0 2006.173.03:04:44.40#ibcon#read 3, iclass 12, count 0 2006.173.03:04:44.40#ibcon#about to read 4, iclass 12, count 0 2006.173.03:04:44.40#ibcon#read 4, iclass 12, count 0 2006.173.03:04:44.40#ibcon#about to read 5, iclass 12, count 0 2006.173.03:04:44.40#ibcon#read 5, iclass 12, count 0 2006.173.03:04:44.40#ibcon#about to read 6, iclass 12, count 0 2006.173.03:04:44.40#ibcon#read 6, iclass 12, count 0 2006.173.03:04:44.40#ibcon#end of sib2, iclass 12, count 0 2006.173.03:04:44.40#ibcon#*after write, iclass 12, count 0 2006.173.03:04:44.40#ibcon#*before return 0, iclass 12, count 0 2006.173.03:04:44.40#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.03:04:44.40#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.03:04:44.40#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.03:04:44.40#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.03:04:44.40$vck44/valo=6,814.99 2006.173.03:04:44.40#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.03:04:44.40#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.03:04:44.40#ibcon#ireg 17 cls_cnt 0 2006.173.03:04:44.40#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.03:04:44.40#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.03:04:44.40#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.03:04:44.40#ibcon#enter wrdev, iclass 14, count 0 2006.173.03:04:44.40#ibcon#first serial, iclass 14, count 0 2006.173.03:04:44.40#ibcon#enter sib2, iclass 14, count 0 2006.173.03:04:44.40#ibcon#flushed, iclass 14, count 0 2006.173.03:04:44.40#ibcon#about to write, iclass 14, count 0 2006.173.03:04:44.40#ibcon#wrote, iclass 14, count 0 2006.173.03:04:44.40#ibcon#about to read 3, iclass 14, count 0 2006.173.03:04:44.42#ibcon#read 3, iclass 14, count 0 2006.173.03:04:44.42#ibcon#about to read 4, iclass 14, count 0 2006.173.03:04:44.42#ibcon#read 4, iclass 14, count 0 2006.173.03:04:44.42#ibcon#about to read 5, iclass 14, count 0 2006.173.03:04:44.42#ibcon#read 5, iclass 14, count 0 2006.173.03:04:44.42#ibcon#about to read 6, iclass 14, count 0 2006.173.03:04:44.42#ibcon#read 6, iclass 14, count 0 2006.173.03:04:44.42#ibcon#end of sib2, iclass 14, count 0 2006.173.03:04:44.42#ibcon#*mode == 0, iclass 14, count 0 2006.173.03:04:44.42#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.03:04:44.42#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.03:04:44.42#ibcon#*before write, iclass 14, count 0 2006.173.03:04:44.42#ibcon#enter sib2, iclass 14, count 0 2006.173.03:04:44.42#ibcon#flushed, iclass 14, count 0 2006.173.03:04:44.42#ibcon#about to write, iclass 14, count 0 2006.173.03:04:44.42#ibcon#wrote, iclass 14, count 0 2006.173.03:04:44.42#ibcon#about to read 3, iclass 14, count 0 2006.173.03:04:44.46#ibcon#read 3, iclass 14, count 0 2006.173.03:04:44.46#ibcon#about to read 4, iclass 14, count 0 2006.173.03:04:44.46#ibcon#read 4, iclass 14, count 0 2006.173.03:04:44.46#ibcon#about to read 5, iclass 14, count 0 2006.173.03:04:44.46#ibcon#read 5, iclass 14, count 0 2006.173.03:04:44.46#ibcon#about to read 6, iclass 14, count 0 2006.173.03:04:44.46#ibcon#read 6, iclass 14, count 0 2006.173.03:04:44.46#ibcon#end of sib2, iclass 14, count 0 2006.173.03:04:44.46#ibcon#*after write, iclass 14, count 0 2006.173.03:04:44.46#ibcon#*before return 0, iclass 14, count 0 2006.173.03:04:44.46#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.03:04:44.46#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.03:04:44.46#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.03:04:44.46#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.03:04:44.46$vck44/va=6,3 2006.173.03:04:44.46#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.03:04:44.46#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.03:04:44.46#ibcon#ireg 11 cls_cnt 2 2006.173.03:04:44.46#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.03:04:44.52#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.03:04:44.52#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.03:04:44.52#ibcon#enter wrdev, iclass 16, count 2 2006.173.03:04:44.52#ibcon#first serial, iclass 16, count 2 2006.173.03:04:44.52#ibcon#enter sib2, iclass 16, count 2 2006.173.03:04:44.52#ibcon#flushed, iclass 16, count 2 2006.173.03:04:44.52#ibcon#about to write, iclass 16, count 2 2006.173.03:04:44.52#ibcon#wrote, iclass 16, count 2 2006.173.03:04:44.52#ibcon#about to read 3, iclass 16, count 2 2006.173.03:04:44.54#ibcon#read 3, iclass 16, count 2 2006.173.03:04:44.54#ibcon#about to read 4, iclass 16, count 2 2006.173.03:04:44.54#ibcon#read 4, iclass 16, count 2 2006.173.03:04:44.54#ibcon#about to read 5, iclass 16, count 2 2006.173.03:04:44.54#ibcon#read 5, iclass 16, count 2 2006.173.03:04:44.54#ibcon#about to read 6, iclass 16, count 2 2006.173.03:04:44.54#ibcon#read 6, iclass 16, count 2 2006.173.03:04:44.54#ibcon#end of sib2, iclass 16, count 2 2006.173.03:04:44.54#ibcon#*mode == 0, iclass 16, count 2 2006.173.03:04:44.54#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.03:04:44.54#ibcon#[25=AT06-03\r\n] 2006.173.03:04:44.54#ibcon#*before write, iclass 16, count 2 2006.173.03:04:44.54#ibcon#enter sib2, iclass 16, count 2 2006.173.03:04:44.54#ibcon#flushed, iclass 16, count 2 2006.173.03:04:44.54#ibcon#about to write, iclass 16, count 2 2006.173.03:04:44.54#ibcon#wrote, iclass 16, count 2 2006.173.03:04:44.54#ibcon#about to read 3, iclass 16, count 2 2006.173.03:04:44.57#ibcon#read 3, iclass 16, count 2 2006.173.03:04:44.57#ibcon#about to read 4, iclass 16, count 2 2006.173.03:04:44.57#ibcon#read 4, iclass 16, count 2 2006.173.03:04:44.57#ibcon#about to read 5, iclass 16, count 2 2006.173.03:04:44.57#ibcon#read 5, iclass 16, count 2 2006.173.03:04:44.57#ibcon#about to read 6, iclass 16, count 2 2006.173.03:04:44.57#ibcon#read 6, iclass 16, count 2 2006.173.03:04:44.57#ibcon#end of sib2, iclass 16, count 2 2006.173.03:04:44.57#ibcon#*after write, iclass 16, count 2 2006.173.03:04:44.57#ibcon#*before return 0, iclass 16, count 2 2006.173.03:04:44.57#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.03:04:44.57#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.03:04:44.57#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.03:04:44.57#ibcon#ireg 7 cls_cnt 0 2006.173.03:04:44.57#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.03:04:44.69#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.03:04:44.69#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.03:04:44.69#ibcon#enter wrdev, iclass 16, count 0 2006.173.03:04:44.69#ibcon#first serial, iclass 16, count 0 2006.173.03:04:44.69#ibcon#enter sib2, iclass 16, count 0 2006.173.03:04:44.69#ibcon#flushed, iclass 16, count 0 2006.173.03:04:44.69#ibcon#about to write, iclass 16, count 0 2006.173.03:04:44.69#ibcon#wrote, iclass 16, count 0 2006.173.03:04:44.69#ibcon#about to read 3, iclass 16, count 0 2006.173.03:04:44.71#ibcon#read 3, iclass 16, count 0 2006.173.03:04:44.71#ibcon#about to read 4, iclass 16, count 0 2006.173.03:04:44.71#ibcon#read 4, iclass 16, count 0 2006.173.03:04:44.71#ibcon#about to read 5, iclass 16, count 0 2006.173.03:04:44.71#ibcon#read 5, iclass 16, count 0 2006.173.03:04:44.71#ibcon#about to read 6, iclass 16, count 0 2006.173.03:04:44.71#ibcon#read 6, iclass 16, count 0 2006.173.03:04:44.71#ibcon#end of sib2, iclass 16, count 0 2006.173.03:04:44.71#ibcon#*mode == 0, iclass 16, count 0 2006.173.03:04:44.71#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.03:04:44.71#ibcon#[25=USB\r\n] 2006.173.03:04:44.71#ibcon#*before write, iclass 16, count 0 2006.173.03:04:44.71#ibcon#enter sib2, iclass 16, count 0 2006.173.03:04:44.71#ibcon#flushed, iclass 16, count 0 2006.173.03:04:44.71#ibcon#about to write, iclass 16, count 0 2006.173.03:04:44.71#ibcon#wrote, iclass 16, count 0 2006.173.03:04:44.71#ibcon#about to read 3, iclass 16, count 0 2006.173.03:04:44.74#ibcon#read 3, iclass 16, count 0 2006.173.03:04:44.74#ibcon#about to read 4, iclass 16, count 0 2006.173.03:04:44.74#ibcon#read 4, iclass 16, count 0 2006.173.03:04:44.74#ibcon#about to read 5, iclass 16, count 0 2006.173.03:04:44.74#ibcon#read 5, iclass 16, count 0 2006.173.03:04:44.74#ibcon#about to read 6, iclass 16, count 0 2006.173.03:04:44.74#ibcon#read 6, iclass 16, count 0 2006.173.03:04:44.74#ibcon#end of sib2, iclass 16, count 0 2006.173.03:04:44.74#ibcon#*after write, iclass 16, count 0 2006.173.03:04:44.74#ibcon#*before return 0, iclass 16, count 0 2006.173.03:04:44.74#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.03:04:44.74#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.03:04:44.74#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.03:04:44.74#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.03:04:44.74$vck44/valo=7,864.99 2006.173.03:04:44.74#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.03:04:44.74#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.03:04:44.74#ibcon#ireg 17 cls_cnt 0 2006.173.03:04:44.74#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.03:04:44.74#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.03:04:44.74#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.03:04:44.74#ibcon#enter wrdev, iclass 18, count 0 2006.173.03:04:44.74#ibcon#first serial, iclass 18, count 0 2006.173.03:04:44.74#ibcon#enter sib2, iclass 18, count 0 2006.173.03:04:44.74#ibcon#flushed, iclass 18, count 0 2006.173.03:04:44.74#ibcon#about to write, iclass 18, count 0 2006.173.03:04:44.74#ibcon#wrote, iclass 18, count 0 2006.173.03:04:44.74#ibcon#about to read 3, iclass 18, count 0 2006.173.03:04:44.76#ibcon#read 3, iclass 18, count 0 2006.173.03:04:44.76#ibcon#about to read 4, iclass 18, count 0 2006.173.03:04:44.76#ibcon#read 4, iclass 18, count 0 2006.173.03:04:44.76#ibcon#about to read 5, iclass 18, count 0 2006.173.03:04:44.76#ibcon#read 5, iclass 18, count 0 2006.173.03:04:44.76#ibcon#about to read 6, iclass 18, count 0 2006.173.03:04:44.76#ibcon#read 6, iclass 18, count 0 2006.173.03:04:44.76#ibcon#end of sib2, iclass 18, count 0 2006.173.03:04:44.76#ibcon#*mode == 0, iclass 18, count 0 2006.173.03:04:44.76#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.03:04:44.76#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.03:04:44.76#ibcon#*before write, iclass 18, count 0 2006.173.03:04:44.76#ibcon#enter sib2, iclass 18, count 0 2006.173.03:04:44.76#ibcon#flushed, iclass 18, count 0 2006.173.03:04:44.76#ibcon#about to write, iclass 18, count 0 2006.173.03:04:44.76#ibcon#wrote, iclass 18, count 0 2006.173.03:04:44.76#ibcon#about to read 3, iclass 18, count 0 2006.173.03:04:44.80#ibcon#read 3, iclass 18, count 0 2006.173.03:04:44.80#ibcon#about to read 4, iclass 18, count 0 2006.173.03:04:44.80#ibcon#read 4, iclass 18, count 0 2006.173.03:04:44.80#ibcon#about to read 5, iclass 18, count 0 2006.173.03:04:44.80#ibcon#read 5, iclass 18, count 0 2006.173.03:04:44.80#ibcon#about to read 6, iclass 18, count 0 2006.173.03:04:44.80#ibcon#read 6, iclass 18, count 0 2006.173.03:04:44.80#ibcon#end of sib2, iclass 18, count 0 2006.173.03:04:44.80#ibcon#*after write, iclass 18, count 0 2006.173.03:04:44.80#ibcon#*before return 0, iclass 18, count 0 2006.173.03:04:44.80#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.03:04:44.80#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.03:04:44.80#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.03:04:44.80#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.03:04:44.80$vck44/va=7,4 2006.173.03:04:44.80#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.03:04:44.80#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.03:04:44.80#ibcon#ireg 11 cls_cnt 2 2006.173.03:04:44.80#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.03:04:44.86#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.03:04:44.86#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.03:04:44.86#ibcon#enter wrdev, iclass 20, count 2 2006.173.03:04:44.86#ibcon#first serial, iclass 20, count 2 2006.173.03:04:44.86#ibcon#enter sib2, iclass 20, count 2 2006.173.03:04:44.86#ibcon#flushed, iclass 20, count 2 2006.173.03:04:44.86#ibcon#about to write, iclass 20, count 2 2006.173.03:04:44.86#ibcon#wrote, iclass 20, count 2 2006.173.03:04:44.86#ibcon#about to read 3, iclass 20, count 2 2006.173.03:04:44.88#ibcon#read 3, iclass 20, count 2 2006.173.03:04:44.88#ibcon#about to read 4, iclass 20, count 2 2006.173.03:04:44.88#ibcon#read 4, iclass 20, count 2 2006.173.03:04:44.88#ibcon#about to read 5, iclass 20, count 2 2006.173.03:04:44.88#ibcon#read 5, iclass 20, count 2 2006.173.03:04:44.88#ibcon#about to read 6, iclass 20, count 2 2006.173.03:04:44.88#ibcon#read 6, iclass 20, count 2 2006.173.03:04:44.88#ibcon#end of sib2, iclass 20, count 2 2006.173.03:04:44.88#ibcon#*mode == 0, iclass 20, count 2 2006.173.03:04:44.88#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.03:04:44.88#ibcon#[25=AT07-04\r\n] 2006.173.03:04:44.88#ibcon#*before write, iclass 20, count 2 2006.173.03:04:44.88#ibcon#enter sib2, iclass 20, count 2 2006.173.03:04:44.88#ibcon#flushed, iclass 20, count 2 2006.173.03:04:44.88#ibcon#about to write, iclass 20, count 2 2006.173.03:04:44.88#ibcon#wrote, iclass 20, count 2 2006.173.03:04:44.88#ibcon#about to read 3, iclass 20, count 2 2006.173.03:04:44.91#ibcon#read 3, iclass 20, count 2 2006.173.03:04:44.91#ibcon#about to read 4, iclass 20, count 2 2006.173.03:04:44.91#ibcon#read 4, iclass 20, count 2 2006.173.03:04:44.91#ibcon#about to read 5, iclass 20, count 2 2006.173.03:04:44.91#ibcon#read 5, iclass 20, count 2 2006.173.03:04:44.91#ibcon#about to read 6, iclass 20, count 2 2006.173.03:04:44.91#ibcon#read 6, iclass 20, count 2 2006.173.03:04:44.91#ibcon#end of sib2, iclass 20, count 2 2006.173.03:04:44.91#ibcon#*after write, iclass 20, count 2 2006.173.03:04:44.91#ibcon#*before return 0, iclass 20, count 2 2006.173.03:04:44.91#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.03:04:44.91#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.03:04:44.91#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.03:04:44.91#ibcon#ireg 7 cls_cnt 0 2006.173.03:04:44.91#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.03:04:45.03#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.03:04:45.03#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.03:04:45.03#ibcon#enter wrdev, iclass 20, count 0 2006.173.03:04:45.03#ibcon#first serial, iclass 20, count 0 2006.173.03:04:45.03#ibcon#enter sib2, iclass 20, count 0 2006.173.03:04:45.03#ibcon#flushed, iclass 20, count 0 2006.173.03:04:45.03#ibcon#about to write, iclass 20, count 0 2006.173.03:04:45.03#ibcon#wrote, iclass 20, count 0 2006.173.03:04:45.03#ibcon#about to read 3, iclass 20, count 0 2006.173.03:04:45.05#ibcon#read 3, iclass 20, count 0 2006.173.03:04:45.05#ibcon#about to read 4, iclass 20, count 0 2006.173.03:04:45.05#ibcon#read 4, iclass 20, count 0 2006.173.03:04:45.05#ibcon#about to read 5, iclass 20, count 0 2006.173.03:04:45.05#ibcon#read 5, iclass 20, count 0 2006.173.03:04:45.05#ibcon#about to read 6, iclass 20, count 0 2006.173.03:04:45.05#ibcon#read 6, iclass 20, count 0 2006.173.03:04:45.05#ibcon#end of sib2, iclass 20, count 0 2006.173.03:04:45.05#ibcon#*mode == 0, iclass 20, count 0 2006.173.03:04:45.05#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.03:04:45.05#ibcon#[25=USB\r\n] 2006.173.03:04:45.05#ibcon#*before write, iclass 20, count 0 2006.173.03:04:45.05#ibcon#enter sib2, iclass 20, count 0 2006.173.03:04:45.05#ibcon#flushed, iclass 20, count 0 2006.173.03:04:45.05#ibcon#about to write, iclass 20, count 0 2006.173.03:04:45.05#ibcon#wrote, iclass 20, count 0 2006.173.03:04:45.05#ibcon#about to read 3, iclass 20, count 0 2006.173.03:04:45.08#ibcon#read 3, iclass 20, count 0 2006.173.03:04:45.08#ibcon#about to read 4, iclass 20, count 0 2006.173.03:04:45.08#ibcon#read 4, iclass 20, count 0 2006.173.03:04:45.08#ibcon#about to read 5, iclass 20, count 0 2006.173.03:04:45.08#ibcon#read 5, iclass 20, count 0 2006.173.03:04:45.08#ibcon#about to read 6, iclass 20, count 0 2006.173.03:04:45.08#ibcon#read 6, iclass 20, count 0 2006.173.03:04:45.08#ibcon#end of sib2, iclass 20, count 0 2006.173.03:04:45.08#ibcon#*after write, iclass 20, count 0 2006.173.03:04:45.08#ibcon#*before return 0, iclass 20, count 0 2006.173.03:04:45.08#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.03:04:45.08#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.03:04:45.08#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.03:04:45.08#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.03:04:45.08$vck44/valo=8,884.99 2006.173.03:04:45.08#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.03:04:45.08#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.03:04:45.08#ibcon#ireg 17 cls_cnt 0 2006.173.03:04:45.08#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.03:04:45.08#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.03:04:45.08#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.03:04:45.08#ibcon#enter wrdev, iclass 22, count 0 2006.173.03:04:45.08#ibcon#first serial, iclass 22, count 0 2006.173.03:04:45.08#ibcon#enter sib2, iclass 22, count 0 2006.173.03:04:45.08#ibcon#flushed, iclass 22, count 0 2006.173.03:04:45.08#ibcon#about to write, iclass 22, count 0 2006.173.03:04:45.08#ibcon#wrote, iclass 22, count 0 2006.173.03:04:45.08#ibcon#about to read 3, iclass 22, count 0 2006.173.03:04:45.10#ibcon#read 3, iclass 22, count 0 2006.173.03:04:45.10#ibcon#about to read 4, iclass 22, count 0 2006.173.03:04:45.10#ibcon#read 4, iclass 22, count 0 2006.173.03:04:45.10#ibcon#about to read 5, iclass 22, count 0 2006.173.03:04:45.10#ibcon#read 5, iclass 22, count 0 2006.173.03:04:45.10#ibcon#about to read 6, iclass 22, count 0 2006.173.03:04:45.10#ibcon#read 6, iclass 22, count 0 2006.173.03:04:45.10#ibcon#end of sib2, iclass 22, count 0 2006.173.03:04:45.10#ibcon#*mode == 0, iclass 22, count 0 2006.173.03:04:45.10#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.03:04:45.10#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.03:04:45.10#ibcon#*before write, iclass 22, count 0 2006.173.03:04:45.10#ibcon#enter sib2, iclass 22, count 0 2006.173.03:04:45.10#ibcon#flushed, iclass 22, count 0 2006.173.03:04:45.10#ibcon#about to write, iclass 22, count 0 2006.173.03:04:45.10#ibcon#wrote, iclass 22, count 0 2006.173.03:04:45.10#ibcon#about to read 3, iclass 22, count 0 2006.173.03:04:45.14#ibcon#read 3, iclass 22, count 0 2006.173.03:04:45.14#ibcon#about to read 4, iclass 22, count 0 2006.173.03:04:45.14#ibcon#read 4, iclass 22, count 0 2006.173.03:04:45.14#ibcon#about to read 5, iclass 22, count 0 2006.173.03:04:45.14#ibcon#read 5, iclass 22, count 0 2006.173.03:04:45.14#ibcon#about to read 6, iclass 22, count 0 2006.173.03:04:45.14#ibcon#read 6, iclass 22, count 0 2006.173.03:04:45.14#ibcon#end of sib2, iclass 22, count 0 2006.173.03:04:45.14#ibcon#*after write, iclass 22, count 0 2006.173.03:04:45.14#ibcon#*before return 0, iclass 22, count 0 2006.173.03:04:45.14#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.03:04:45.14#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.03:04:45.14#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.03:04:45.14#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.03:04:45.14$vck44/va=8,4 2006.173.03:04:45.14#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.03:04:45.14#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.03:04:45.14#ibcon#ireg 11 cls_cnt 2 2006.173.03:04:45.14#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.03:04:45.20#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.03:04:45.20#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.03:04:45.20#ibcon#enter wrdev, iclass 24, count 2 2006.173.03:04:45.20#ibcon#first serial, iclass 24, count 2 2006.173.03:04:45.20#ibcon#enter sib2, iclass 24, count 2 2006.173.03:04:45.20#ibcon#flushed, iclass 24, count 2 2006.173.03:04:45.20#ibcon#about to write, iclass 24, count 2 2006.173.03:04:45.20#ibcon#wrote, iclass 24, count 2 2006.173.03:04:45.20#ibcon#about to read 3, iclass 24, count 2 2006.173.03:04:45.22#ibcon#read 3, iclass 24, count 2 2006.173.03:04:45.22#ibcon#about to read 4, iclass 24, count 2 2006.173.03:04:45.22#ibcon#read 4, iclass 24, count 2 2006.173.03:04:45.22#ibcon#about to read 5, iclass 24, count 2 2006.173.03:04:45.22#ibcon#read 5, iclass 24, count 2 2006.173.03:04:45.22#ibcon#about to read 6, iclass 24, count 2 2006.173.03:04:45.22#ibcon#read 6, iclass 24, count 2 2006.173.03:04:45.22#ibcon#end of sib2, iclass 24, count 2 2006.173.03:04:45.22#ibcon#*mode == 0, iclass 24, count 2 2006.173.03:04:45.22#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.03:04:45.22#ibcon#[25=AT08-04\r\n] 2006.173.03:04:45.22#ibcon#*before write, iclass 24, count 2 2006.173.03:04:45.22#ibcon#enter sib2, iclass 24, count 2 2006.173.03:04:45.22#ibcon#flushed, iclass 24, count 2 2006.173.03:04:45.22#ibcon#about to write, iclass 24, count 2 2006.173.03:04:45.22#ibcon#wrote, iclass 24, count 2 2006.173.03:04:45.22#ibcon#about to read 3, iclass 24, count 2 2006.173.03:04:45.25#ibcon#read 3, iclass 24, count 2 2006.173.03:04:45.25#ibcon#about to read 4, iclass 24, count 2 2006.173.03:04:45.25#ibcon#read 4, iclass 24, count 2 2006.173.03:04:45.25#ibcon#about to read 5, iclass 24, count 2 2006.173.03:04:45.25#ibcon#read 5, iclass 24, count 2 2006.173.03:04:45.25#ibcon#about to read 6, iclass 24, count 2 2006.173.03:04:45.25#ibcon#read 6, iclass 24, count 2 2006.173.03:04:45.25#ibcon#end of sib2, iclass 24, count 2 2006.173.03:04:45.25#ibcon#*after write, iclass 24, count 2 2006.173.03:04:45.25#ibcon#*before return 0, iclass 24, count 2 2006.173.03:04:45.25#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.03:04:45.25#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.03:04:45.25#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.03:04:45.25#ibcon#ireg 7 cls_cnt 0 2006.173.03:04:45.25#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.03:04:45.37#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.03:04:45.37#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.03:04:45.37#ibcon#enter wrdev, iclass 24, count 0 2006.173.03:04:45.37#ibcon#first serial, iclass 24, count 0 2006.173.03:04:45.37#ibcon#enter sib2, iclass 24, count 0 2006.173.03:04:45.37#ibcon#flushed, iclass 24, count 0 2006.173.03:04:45.37#ibcon#about to write, iclass 24, count 0 2006.173.03:04:45.37#ibcon#wrote, iclass 24, count 0 2006.173.03:04:45.37#ibcon#about to read 3, iclass 24, count 0 2006.173.03:04:45.39#ibcon#read 3, iclass 24, count 0 2006.173.03:04:45.39#ibcon#about to read 4, iclass 24, count 0 2006.173.03:04:45.39#ibcon#read 4, iclass 24, count 0 2006.173.03:04:45.39#ibcon#about to read 5, iclass 24, count 0 2006.173.03:04:45.39#ibcon#read 5, iclass 24, count 0 2006.173.03:04:45.39#ibcon#about to read 6, iclass 24, count 0 2006.173.03:04:45.39#ibcon#read 6, iclass 24, count 0 2006.173.03:04:45.39#ibcon#end of sib2, iclass 24, count 0 2006.173.03:04:45.39#ibcon#*mode == 0, iclass 24, count 0 2006.173.03:04:45.39#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.03:04:45.39#ibcon#[25=USB\r\n] 2006.173.03:04:45.39#ibcon#*before write, iclass 24, count 0 2006.173.03:04:45.39#ibcon#enter sib2, iclass 24, count 0 2006.173.03:04:45.39#ibcon#flushed, iclass 24, count 0 2006.173.03:04:45.39#ibcon#about to write, iclass 24, count 0 2006.173.03:04:45.39#ibcon#wrote, iclass 24, count 0 2006.173.03:04:45.39#ibcon#about to read 3, iclass 24, count 0 2006.173.03:04:45.42#ibcon#read 3, iclass 24, count 0 2006.173.03:04:45.42#ibcon#about to read 4, iclass 24, count 0 2006.173.03:04:45.42#ibcon#read 4, iclass 24, count 0 2006.173.03:04:45.42#ibcon#about to read 5, iclass 24, count 0 2006.173.03:04:45.42#ibcon#read 5, iclass 24, count 0 2006.173.03:04:45.42#ibcon#about to read 6, iclass 24, count 0 2006.173.03:04:45.42#ibcon#read 6, iclass 24, count 0 2006.173.03:04:45.42#ibcon#end of sib2, iclass 24, count 0 2006.173.03:04:45.42#ibcon#*after write, iclass 24, count 0 2006.173.03:04:45.42#ibcon#*before return 0, iclass 24, count 0 2006.173.03:04:45.42#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.03:04:45.42#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.03:04:45.42#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.03:04:45.42#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.03:04:45.42$vck44/vblo=1,629.99 2006.173.03:04:45.42#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.03:04:45.42#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.03:04:45.42#ibcon#ireg 17 cls_cnt 0 2006.173.03:04:45.42#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.03:04:45.42#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.03:04:45.42#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.03:04:45.42#ibcon#enter wrdev, iclass 26, count 0 2006.173.03:04:45.42#ibcon#first serial, iclass 26, count 0 2006.173.03:04:45.42#ibcon#enter sib2, iclass 26, count 0 2006.173.03:04:45.42#ibcon#flushed, iclass 26, count 0 2006.173.03:04:45.42#ibcon#about to write, iclass 26, count 0 2006.173.03:04:45.42#ibcon#wrote, iclass 26, count 0 2006.173.03:04:45.42#ibcon#about to read 3, iclass 26, count 0 2006.173.03:04:45.44#ibcon#read 3, iclass 26, count 0 2006.173.03:04:45.44#ibcon#about to read 4, iclass 26, count 0 2006.173.03:04:45.44#ibcon#read 4, iclass 26, count 0 2006.173.03:04:45.44#ibcon#about to read 5, iclass 26, count 0 2006.173.03:04:45.44#ibcon#read 5, iclass 26, count 0 2006.173.03:04:45.44#ibcon#about to read 6, iclass 26, count 0 2006.173.03:04:45.44#ibcon#read 6, iclass 26, count 0 2006.173.03:04:45.44#ibcon#end of sib2, iclass 26, count 0 2006.173.03:04:45.44#ibcon#*mode == 0, iclass 26, count 0 2006.173.03:04:45.44#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.03:04:45.44#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.03:04:45.44#ibcon#*before write, iclass 26, count 0 2006.173.03:04:45.44#ibcon#enter sib2, iclass 26, count 0 2006.173.03:04:45.44#ibcon#flushed, iclass 26, count 0 2006.173.03:04:45.44#ibcon#about to write, iclass 26, count 0 2006.173.03:04:45.44#ibcon#wrote, iclass 26, count 0 2006.173.03:04:45.44#ibcon#about to read 3, iclass 26, count 0 2006.173.03:04:45.48#ibcon#read 3, iclass 26, count 0 2006.173.03:04:45.48#ibcon#about to read 4, iclass 26, count 0 2006.173.03:04:45.48#ibcon#read 4, iclass 26, count 0 2006.173.03:04:45.48#ibcon#about to read 5, iclass 26, count 0 2006.173.03:04:45.48#ibcon#read 5, iclass 26, count 0 2006.173.03:04:45.48#ibcon#about to read 6, iclass 26, count 0 2006.173.03:04:45.48#ibcon#read 6, iclass 26, count 0 2006.173.03:04:45.48#ibcon#end of sib2, iclass 26, count 0 2006.173.03:04:45.48#ibcon#*after write, iclass 26, count 0 2006.173.03:04:45.48#ibcon#*before return 0, iclass 26, count 0 2006.173.03:04:45.48#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.03:04:45.48#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.03:04:45.48#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.03:04:45.48#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.03:04:45.48$vck44/vb=1,4 2006.173.03:04:45.48#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.03:04:45.48#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.03:04:45.48#ibcon#ireg 11 cls_cnt 2 2006.173.03:04:45.48#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.03:04:45.48#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.03:04:45.48#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.03:04:45.48#ibcon#enter wrdev, iclass 28, count 2 2006.173.03:04:45.48#ibcon#first serial, iclass 28, count 2 2006.173.03:04:45.48#ibcon#enter sib2, iclass 28, count 2 2006.173.03:04:45.48#ibcon#flushed, iclass 28, count 2 2006.173.03:04:45.48#ibcon#about to write, iclass 28, count 2 2006.173.03:04:45.48#ibcon#wrote, iclass 28, count 2 2006.173.03:04:45.48#ibcon#about to read 3, iclass 28, count 2 2006.173.03:04:45.50#ibcon#read 3, iclass 28, count 2 2006.173.03:04:45.50#ibcon#about to read 4, iclass 28, count 2 2006.173.03:04:45.50#ibcon#read 4, iclass 28, count 2 2006.173.03:04:45.50#ibcon#about to read 5, iclass 28, count 2 2006.173.03:04:45.50#ibcon#read 5, iclass 28, count 2 2006.173.03:04:45.50#ibcon#about to read 6, iclass 28, count 2 2006.173.03:04:45.50#ibcon#read 6, iclass 28, count 2 2006.173.03:04:45.50#ibcon#end of sib2, iclass 28, count 2 2006.173.03:04:45.50#ibcon#*mode == 0, iclass 28, count 2 2006.173.03:04:45.50#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.03:04:45.50#ibcon#[27=AT01-04\r\n] 2006.173.03:04:45.50#ibcon#*before write, iclass 28, count 2 2006.173.03:04:45.50#ibcon#enter sib2, iclass 28, count 2 2006.173.03:04:45.50#ibcon#flushed, iclass 28, count 2 2006.173.03:04:45.50#ibcon#about to write, iclass 28, count 2 2006.173.03:04:45.50#ibcon#wrote, iclass 28, count 2 2006.173.03:04:45.50#ibcon#about to read 3, iclass 28, count 2 2006.173.03:04:45.53#ibcon#read 3, iclass 28, count 2 2006.173.03:04:45.53#ibcon#about to read 4, iclass 28, count 2 2006.173.03:04:45.53#ibcon#read 4, iclass 28, count 2 2006.173.03:04:45.53#ibcon#about to read 5, iclass 28, count 2 2006.173.03:04:45.53#ibcon#read 5, iclass 28, count 2 2006.173.03:04:45.53#ibcon#about to read 6, iclass 28, count 2 2006.173.03:04:45.53#ibcon#read 6, iclass 28, count 2 2006.173.03:04:45.53#ibcon#end of sib2, iclass 28, count 2 2006.173.03:04:45.53#ibcon#*after write, iclass 28, count 2 2006.173.03:04:45.53#ibcon#*before return 0, iclass 28, count 2 2006.173.03:04:45.53#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.03:04:45.53#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.03:04:45.53#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.03:04:45.53#ibcon#ireg 7 cls_cnt 0 2006.173.03:04:45.53#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.03:04:45.65#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.03:04:45.65#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.03:04:45.65#ibcon#enter wrdev, iclass 28, count 0 2006.173.03:04:45.65#ibcon#first serial, iclass 28, count 0 2006.173.03:04:45.65#ibcon#enter sib2, iclass 28, count 0 2006.173.03:04:45.65#ibcon#flushed, iclass 28, count 0 2006.173.03:04:45.65#ibcon#about to write, iclass 28, count 0 2006.173.03:04:45.65#ibcon#wrote, iclass 28, count 0 2006.173.03:04:45.65#ibcon#about to read 3, iclass 28, count 0 2006.173.03:04:45.67#ibcon#read 3, iclass 28, count 0 2006.173.03:04:45.67#ibcon#about to read 4, iclass 28, count 0 2006.173.03:04:45.67#ibcon#read 4, iclass 28, count 0 2006.173.03:04:45.67#ibcon#about to read 5, iclass 28, count 0 2006.173.03:04:45.67#ibcon#read 5, iclass 28, count 0 2006.173.03:04:45.67#ibcon#about to read 6, iclass 28, count 0 2006.173.03:04:45.67#ibcon#read 6, iclass 28, count 0 2006.173.03:04:45.67#ibcon#end of sib2, iclass 28, count 0 2006.173.03:04:45.67#ibcon#*mode == 0, iclass 28, count 0 2006.173.03:04:45.67#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.03:04:45.67#ibcon#[27=USB\r\n] 2006.173.03:04:45.67#ibcon#*before write, iclass 28, count 0 2006.173.03:04:45.67#ibcon#enter sib2, iclass 28, count 0 2006.173.03:04:45.67#ibcon#flushed, iclass 28, count 0 2006.173.03:04:45.67#ibcon#about to write, iclass 28, count 0 2006.173.03:04:45.67#ibcon#wrote, iclass 28, count 0 2006.173.03:04:45.67#ibcon#about to read 3, iclass 28, count 0 2006.173.03:04:45.70#ibcon#read 3, iclass 28, count 0 2006.173.03:04:45.70#ibcon#about to read 4, iclass 28, count 0 2006.173.03:04:45.70#ibcon#read 4, iclass 28, count 0 2006.173.03:04:45.70#ibcon#about to read 5, iclass 28, count 0 2006.173.03:04:45.70#ibcon#read 5, iclass 28, count 0 2006.173.03:04:45.70#ibcon#about to read 6, iclass 28, count 0 2006.173.03:04:45.70#ibcon#read 6, iclass 28, count 0 2006.173.03:04:45.70#ibcon#end of sib2, iclass 28, count 0 2006.173.03:04:45.70#ibcon#*after write, iclass 28, count 0 2006.173.03:04:45.70#ibcon#*before return 0, iclass 28, count 0 2006.173.03:04:45.70#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.03:04:45.70#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.03:04:45.70#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.03:04:45.70#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.03:04:45.70$vck44/vblo=2,634.99 2006.173.03:04:45.70#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.03:04:45.70#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.03:04:45.70#ibcon#ireg 17 cls_cnt 0 2006.173.03:04:45.70#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.03:04:45.70#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.03:04:45.70#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.03:04:45.70#ibcon#enter wrdev, iclass 30, count 0 2006.173.03:04:45.70#ibcon#first serial, iclass 30, count 0 2006.173.03:04:45.70#ibcon#enter sib2, iclass 30, count 0 2006.173.03:04:45.70#ibcon#flushed, iclass 30, count 0 2006.173.03:04:45.70#ibcon#about to write, iclass 30, count 0 2006.173.03:04:45.70#ibcon#wrote, iclass 30, count 0 2006.173.03:04:45.70#ibcon#about to read 3, iclass 30, count 0 2006.173.03:04:45.72#ibcon#read 3, iclass 30, count 0 2006.173.03:04:45.72#ibcon#about to read 4, iclass 30, count 0 2006.173.03:04:45.72#ibcon#read 4, iclass 30, count 0 2006.173.03:04:45.72#ibcon#about to read 5, iclass 30, count 0 2006.173.03:04:45.72#ibcon#read 5, iclass 30, count 0 2006.173.03:04:45.72#ibcon#about to read 6, iclass 30, count 0 2006.173.03:04:45.72#ibcon#read 6, iclass 30, count 0 2006.173.03:04:45.72#ibcon#end of sib2, iclass 30, count 0 2006.173.03:04:45.72#ibcon#*mode == 0, iclass 30, count 0 2006.173.03:04:45.72#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.03:04:45.72#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.03:04:45.72#ibcon#*before write, iclass 30, count 0 2006.173.03:04:45.72#ibcon#enter sib2, iclass 30, count 0 2006.173.03:04:45.72#ibcon#flushed, iclass 30, count 0 2006.173.03:04:45.72#ibcon#about to write, iclass 30, count 0 2006.173.03:04:45.72#ibcon#wrote, iclass 30, count 0 2006.173.03:04:45.72#ibcon#about to read 3, iclass 30, count 0 2006.173.03:04:45.76#ibcon#read 3, iclass 30, count 0 2006.173.03:04:45.76#ibcon#about to read 4, iclass 30, count 0 2006.173.03:04:45.76#ibcon#read 4, iclass 30, count 0 2006.173.03:04:45.76#ibcon#about to read 5, iclass 30, count 0 2006.173.03:04:45.76#ibcon#read 5, iclass 30, count 0 2006.173.03:04:45.76#ibcon#about to read 6, iclass 30, count 0 2006.173.03:04:45.76#ibcon#read 6, iclass 30, count 0 2006.173.03:04:45.76#ibcon#end of sib2, iclass 30, count 0 2006.173.03:04:45.76#ibcon#*after write, iclass 30, count 0 2006.173.03:04:45.76#ibcon#*before return 0, iclass 30, count 0 2006.173.03:04:45.76#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.03:04:45.76#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.03:04:45.76#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.03:04:45.76#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.03:04:45.76$vck44/vb=2,4 2006.173.03:04:45.76#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.173.03:04:45.76#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.173.03:04:45.76#ibcon#ireg 11 cls_cnt 2 2006.173.03:04:45.76#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.03:04:45.82#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.03:04:45.82#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.03:04:45.82#ibcon#enter wrdev, iclass 32, count 2 2006.173.03:04:45.82#ibcon#first serial, iclass 32, count 2 2006.173.03:04:45.82#ibcon#enter sib2, iclass 32, count 2 2006.173.03:04:45.82#ibcon#flushed, iclass 32, count 2 2006.173.03:04:45.82#ibcon#about to write, iclass 32, count 2 2006.173.03:04:45.82#ibcon#wrote, iclass 32, count 2 2006.173.03:04:45.82#ibcon#about to read 3, iclass 32, count 2 2006.173.03:04:45.84#ibcon#read 3, iclass 32, count 2 2006.173.03:04:45.84#ibcon#about to read 4, iclass 32, count 2 2006.173.03:04:45.84#ibcon#read 4, iclass 32, count 2 2006.173.03:04:45.84#ibcon#about to read 5, iclass 32, count 2 2006.173.03:04:45.84#ibcon#read 5, iclass 32, count 2 2006.173.03:04:45.84#ibcon#about to read 6, iclass 32, count 2 2006.173.03:04:45.84#ibcon#read 6, iclass 32, count 2 2006.173.03:04:45.84#ibcon#end of sib2, iclass 32, count 2 2006.173.03:04:45.84#ibcon#*mode == 0, iclass 32, count 2 2006.173.03:04:45.84#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.173.03:04:45.84#ibcon#[27=AT02-04\r\n] 2006.173.03:04:45.84#ibcon#*before write, iclass 32, count 2 2006.173.03:04:45.84#ibcon#enter sib2, iclass 32, count 2 2006.173.03:04:45.84#ibcon#flushed, iclass 32, count 2 2006.173.03:04:45.84#ibcon#about to write, iclass 32, count 2 2006.173.03:04:45.84#ibcon#wrote, iclass 32, count 2 2006.173.03:04:45.84#ibcon#about to read 3, iclass 32, count 2 2006.173.03:04:45.87#ibcon#read 3, iclass 32, count 2 2006.173.03:04:45.87#ibcon#about to read 4, iclass 32, count 2 2006.173.03:04:45.87#ibcon#read 4, iclass 32, count 2 2006.173.03:04:45.87#ibcon#about to read 5, iclass 32, count 2 2006.173.03:04:45.87#ibcon#read 5, iclass 32, count 2 2006.173.03:04:45.87#ibcon#about to read 6, iclass 32, count 2 2006.173.03:04:45.87#ibcon#read 6, iclass 32, count 2 2006.173.03:04:45.87#ibcon#end of sib2, iclass 32, count 2 2006.173.03:04:45.87#ibcon#*after write, iclass 32, count 2 2006.173.03:04:45.87#ibcon#*before return 0, iclass 32, count 2 2006.173.03:04:45.87#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.03:04:45.87#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.173.03:04:45.87#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.173.03:04:45.87#ibcon#ireg 7 cls_cnt 0 2006.173.03:04:45.87#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.03:04:45.99#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.03:04:45.99#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.03:04:45.99#ibcon#enter wrdev, iclass 32, count 0 2006.173.03:04:45.99#ibcon#first serial, iclass 32, count 0 2006.173.03:04:45.99#ibcon#enter sib2, iclass 32, count 0 2006.173.03:04:45.99#ibcon#flushed, iclass 32, count 0 2006.173.03:04:45.99#ibcon#about to write, iclass 32, count 0 2006.173.03:04:45.99#ibcon#wrote, iclass 32, count 0 2006.173.03:04:45.99#ibcon#about to read 3, iclass 32, count 0 2006.173.03:04:46.01#ibcon#read 3, iclass 32, count 0 2006.173.03:04:46.01#ibcon#about to read 4, iclass 32, count 0 2006.173.03:04:46.01#ibcon#read 4, iclass 32, count 0 2006.173.03:04:46.01#ibcon#about to read 5, iclass 32, count 0 2006.173.03:04:46.01#ibcon#read 5, iclass 32, count 0 2006.173.03:04:46.01#ibcon#about to read 6, iclass 32, count 0 2006.173.03:04:46.01#ibcon#read 6, iclass 32, count 0 2006.173.03:04:46.01#ibcon#end of sib2, iclass 32, count 0 2006.173.03:04:46.01#ibcon#*mode == 0, iclass 32, count 0 2006.173.03:04:46.01#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.03:04:46.01#ibcon#[27=USB\r\n] 2006.173.03:04:46.01#ibcon#*before write, iclass 32, count 0 2006.173.03:04:46.01#ibcon#enter sib2, iclass 32, count 0 2006.173.03:04:46.01#ibcon#flushed, iclass 32, count 0 2006.173.03:04:46.01#ibcon#about to write, iclass 32, count 0 2006.173.03:04:46.01#ibcon#wrote, iclass 32, count 0 2006.173.03:04:46.01#ibcon#about to read 3, iclass 32, count 0 2006.173.03:04:46.04#ibcon#read 3, iclass 32, count 0 2006.173.03:04:46.04#ibcon#about to read 4, iclass 32, count 0 2006.173.03:04:46.04#ibcon#read 4, iclass 32, count 0 2006.173.03:04:46.04#ibcon#about to read 5, iclass 32, count 0 2006.173.03:04:46.04#ibcon#read 5, iclass 32, count 0 2006.173.03:04:46.04#ibcon#about to read 6, iclass 32, count 0 2006.173.03:04:46.04#ibcon#read 6, iclass 32, count 0 2006.173.03:04:46.04#ibcon#end of sib2, iclass 32, count 0 2006.173.03:04:46.04#ibcon#*after write, iclass 32, count 0 2006.173.03:04:46.04#ibcon#*before return 0, iclass 32, count 0 2006.173.03:04:46.04#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.03:04:46.04#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.173.03:04:46.04#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.03:04:46.04#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.03:04:46.04$vck44/vblo=3,649.99 2006.173.03:04:46.04#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.03:04:46.04#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.03:04:46.04#ibcon#ireg 17 cls_cnt 0 2006.173.03:04:46.04#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.03:04:46.04#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.03:04:46.04#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.03:04:46.04#ibcon#enter wrdev, iclass 34, count 0 2006.173.03:04:46.04#ibcon#first serial, iclass 34, count 0 2006.173.03:04:46.04#ibcon#enter sib2, iclass 34, count 0 2006.173.03:04:46.04#ibcon#flushed, iclass 34, count 0 2006.173.03:04:46.04#ibcon#about to write, iclass 34, count 0 2006.173.03:04:46.04#ibcon#wrote, iclass 34, count 0 2006.173.03:04:46.04#ibcon#about to read 3, iclass 34, count 0 2006.173.03:04:46.06#ibcon#read 3, iclass 34, count 0 2006.173.03:04:46.06#ibcon#about to read 4, iclass 34, count 0 2006.173.03:04:46.06#ibcon#read 4, iclass 34, count 0 2006.173.03:04:46.06#ibcon#about to read 5, iclass 34, count 0 2006.173.03:04:46.06#ibcon#read 5, iclass 34, count 0 2006.173.03:04:46.06#ibcon#about to read 6, iclass 34, count 0 2006.173.03:04:46.06#ibcon#read 6, iclass 34, count 0 2006.173.03:04:46.06#ibcon#end of sib2, iclass 34, count 0 2006.173.03:04:46.06#ibcon#*mode == 0, iclass 34, count 0 2006.173.03:04:46.06#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.03:04:46.06#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.03:04:46.06#ibcon#*before write, iclass 34, count 0 2006.173.03:04:46.06#ibcon#enter sib2, iclass 34, count 0 2006.173.03:04:46.06#ibcon#flushed, iclass 34, count 0 2006.173.03:04:46.06#ibcon#about to write, iclass 34, count 0 2006.173.03:04:46.06#ibcon#wrote, iclass 34, count 0 2006.173.03:04:46.06#ibcon#about to read 3, iclass 34, count 0 2006.173.03:04:46.10#ibcon#read 3, iclass 34, count 0 2006.173.03:04:46.10#ibcon#about to read 4, iclass 34, count 0 2006.173.03:04:46.10#ibcon#read 4, iclass 34, count 0 2006.173.03:04:46.10#ibcon#about to read 5, iclass 34, count 0 2006.173.03:04:46.10#ibcon#read 5, iclass 34, count 0 2006.173.03:04:46.10#ibcon#about to read 6, iclass 34, count 0 2006.173.03:04:46.10#ibcon#read 6, iclass 34, count 0 2006.173.03:04:46.10#ibcon#end of sib2, iclass 34, count 0 2006.173.03:04:46.10#ibcon#*after write, iclass 34, count 0 2006.173.03:04:46.10#ibcon#*before return 0, iclass 34, count 0 2006.173.03:04:46.10#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.03:04:46.10#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.03:04:46.10#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.03:04:46.10#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.03:04:46.10$vck44/vb=3,4 2006.173.03:04:46.10#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.03:04:46.10#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.03:04:46.10#ibcon#ireg 11 cls_cnt 2 2006.173.03:04:46.10#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.03:04:46.16#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.03:04:46.16#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.03:04:46.16#ibcon#enter wrdev, iclass 36, count 2 2006.173.03:04:46.16#ibcon#first serial, iclass 36, count 2 2006.173.03:04:46.16#ibcon#enter sib2, iclass 36, count 2 2006.173.03:04:46.16#ibcon#flushed, iclass 36, count 2 2006.173.03:04:46.16#ibcon#about to write, iclass 36, count 2 2006.173.03:04:46.16#ibcon#wrote, iclass 36, count 2 2006.173.03:04:46.16#ibcon#about to read 3, iclass 36, count 2 2006.173.03:04:46.18#ibcon#read 3, iclass 36, count 2 2006.173.03:04:46.18#ibcon#about to read 4, iclass 36, count 2 2006.173.03:04:46.18#ibcon#read 4, iclass 36, count 2 2006.173.03:04:46.18#ibcon#about to read 5, iclass 36, count 2 2006.173.03:04:46.18#ibcon#read 5, iclass 36, count 2 2006.173.03:04:46.18#ibcon#about to read 6, iclass 36, count 2 2006.173.03:04:46.18#ibcon#read 6, iclass 36, count 2 2006.173.03:04:46.18#ibcon#end of sib2, iclass 36, count 2 2006.173.03:04:46.18#ibcon#*mode == 0, iclass 36, count 2 2006.173.03:04:46.18#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.03:04:46.18#ibcon#[27=AT03-04\r\n] 2006.173.03:04:46.18#ibcon#*before write, iclass 36, count 2 2006.173.03:04:46.18#ibcon#enter sib2, iclass 36, count 2 2006.173.03:04:46.18#ibcon#flushed, iclass 36, count 2 2006.173.03:04:46.18#ibcon#about to write, iclass 36, count 2 2006.173.03:04:46.18#ibcon#wrote, iclass 36, count 2 2006.173.03:04:46.18#ibcon#about to read 3, iclass 36, count 2 2006.173.03:04:46.21#ibcon#read 3, iclass 36, count 2 2006.173.03:04:46.21#ibcon#about to read 4, iclass 36, count 2 2006.173.03:04:46.21#ibcon#read 4, iclass 36, count 2 2006.173.03:04:46.21#ibcon#about to read 5, iclass 36, count 2 2006.173.03:04:46.21#ibcon#read 5, iclass 36, count 2 2006.173.03:04:46.21#ibcon#about to read 6, iclass 36, count 2 2006.173.03:04:46.21#ibcon#read 6, iclass 36, count 2 2006.173.03:04:46.21#ibcon#end of sib2, iclass 36, count 2 2006.173.03:04:46.21#ibcon#*after write, iclass 36, count 2 2006.173.03:04:46.21#ibcon#*before return 0, iclass 36, count 2 2006.173.03:04:46.21#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.03:04:46.21#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.03:04:46.21#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.03:04:46.21#ibcon#ireg 7 cls_cnt 0 2006.173.03:04:46.21#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.03:04:46.33#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.03:04:46.33#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.03:04:46.33#ibcon#enter wrdev, iclass 36, count 0 2006.173.03:04:46.33#ibcon#first serial, iclass 36, count 0 2006.173.03:04:46.33#ibcon#enter sib2, iclass 36, count 0 2006.173.03:04:46.33#ibcon#flushed, iclass 36, count 0 2006.173.03:04:46.33#ibcon#about to write, iclass 36, count 0 2006.173.03:04:46.33#ibcon#wrote, iclass 36, count 0 2006.173.03:04:46.33#ibcon#about to read 3, iclass 36, count 0 2006.173.03:04:46.35#ibcon#read 3, iclass 36, count 0 2006.173.03:04:46.35#ibcon#about to read 4, iclass 36, count 0 2006.173.03:04:46.35#ibcon#read 4, iclass 36, count 0 2006.173.03:04:46.35#ibcon#about to read 5, iclass 36, count 0 2006.173.03:04:46.35#ibcon#read 5, iclass 36, count 0 2006.173.03:04:46.35#ibcon#about to read 6, iclass 36, count 0 2006.173.03:04:46.35#ibcon#read 6, iclass 36, count 0 2006.173.03:04:46.35#ibcon#end of sib2, iclass 36, count 0 2006.173.03:04:46.35#ibcon#*mode == 0, iclass 36, count 0 2006.173.03:04:46.35#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.03:04:46.35#ibcon#[27=USB\r\n] 2006.173.03:04:46.35#ibcon#*before write, iclass 36, count 0 2006.173.03:04:46.35#ibcon#enter sib2, iclass 36, count 0 2006.173.03:04:46.35#ibcon#flushed, iclass 36, count 0 2006.173.03:04:46.35#ibcon#about to write, iclass 36, count 0 2006.173.03:04:46.35#ibcon#wrote, iclass 36, count 0 2006.173.03:04:46.35#ibcon#about to read 3, iclass 36, count 0 2006.173.03:04:46.38#ibcon#read 3, iclass 36, count 0 2006.173.03:04:46.38#ibcon#about to read 4, iclass 36, count 0 2006.173.03:04:46.38#ibcon#read 4, iclass 36, count 0 2006.173.03:04:46.38#ibcon#about to read 5, iclass 36, count 0 2006.173.03:04:46.38#ibcon#read 5, iclass 36, count 0 2006.173.03:04:46.38#ibcon#about to read 6, iclass 36, count 0 2006.173.03:04:46.38#ibcon#read 6, iclass 36, count 0 2006.173.03:04:46.38#ibcon#end of sib2, iclass 36, count 0 2006.173.03:04:46.38#ibcon#*after write, iclass 36, count 0 2006.173.03:04:46.38#ibcon#*before return 0, iclass 36, count 0 2006.173.03:04:46.38#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.03:04:46.38#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.03:04:46.38#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.03:04:46.38#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.03:04:46.38$vck44/vblo=4,679.99 2006.173.03:04:46.38#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.03:04:46.38#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.03:04:46.38#ibcon#ireg 17 cls_cnt 0 2006.173.03:04:46.38#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.03:04:46.38#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.03:04:46.38#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.03:04:46.38#ibcon#enter wrdev, iclass 38, count 0 2006.173.03:04:46.38#ibcon#first serial, iclass 38, count 0 2006.173.03:04:46.38#ibcon#enter sib2, iclass 38, count 0 2006.173.03:04:46.38#ibcon#flushed, iclass 38, count 0 2006.173.03:04:46.38#ibcon#about to write, iclass 38, count 0 2006.173.03:04:46.38#ibcon#wrote, iclass 38, count 0 2006.173.03:04:46.38#ibcon#about to read 3, iclass 38, count 0 2006.173.03:04:46.40#ibcon#read 3, iclass 38, count 0 2006.173.03:04:46.40#ibcon#about to read 4, iclass 38, count 0 2006.173.03:04:46.40#ibcon#read 4, iclass 38, count 0 2006.173.03:04:46.40#ibcon#about to read 5, iclass 38, count 0 2006.173.03:04:46.40#ibcon#read 5, iclass 38, count 0 2006.173.03:04:46.40#ibcon#about to read 6, iclass 38, count 0 2006.173.03:04:46.40#ibcon#read 6, iclass 38, count 0 2006.173.03:04:46.40#ibcon#end of sib2, iclass 38, count 0 2006.173.03:04:46.40#ibcon#*mode == 0, iclass 38, count 0 2006.173.03:04:46.40#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.03:04:46.40#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.03:04:46.40#ibcon#*before write, iclass 38, count 0 2006.173.03:04:46.40#ibcon#enter sib2, iclass 38, count 0 2006.173.03:04:46.40#ibcon#flushed, iclass 38, count 0 2006.173.03:04:46.40#ibcon#about to write, iclass 38, count 0 2006.173.03:04:46.40#ibcon#wrote, iclass 38, count 0 2006.173.03:04:46.40#ibcon#about to read 3, iclass 38, count 0 2006.173.03:04:46.44#ibcon#read 3, iclass 38, count 0 2006.173.03:04:46.44#ibcon#about to read 4, iclass 38, count 0 2006.173.03:04:46.44#ibcon#read 4, iclass 38, count 0 2006.173.03:04:46.44#ibcon#about to read 5, iclass 38, count 0 2006.173.03:04:46.44#ibcon#read 5, iclass 38, count 0 2006.173.03:04:46.44#ibcon#about to read 6, iclass 38, count 0 2006.173.03:04:46.44#ibcon#read 6, iclass 38, count 0 2006.173.03:04:46.44#ibcon#end of sib2, iclass 38, count 0 2006.173.03:04:46.44#ibcon#*after write, iclass 38, count 0 2006.173.03:04:46.44#ibcon#*before return 0, iclass 38, count 0 2006.173.03:04:46.44#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.03:04:46.44#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.03:04:46.44#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.03:04:46.44#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.03:04:46.44$vck44/vb=4,4 2006.173.03:04:46.44#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.03:04:46.44#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.03:04:46.44#ibcon#ireg 11 cls_cnt 2 2006.173.03:04:46.44#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.03:04:46.50#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.03:04:46.50#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.03:04:46.50#ibcon#enter wrdev, iclass 40, count 2 2006.173.03:04:46.50#ibcon#first serial, iclass 40, count 2 2006.173.03:04:46.50#ibcon#enter sib2, iclass 40, count 2 2006.173.03:04:46.50#ibcon#flushed, iclass 40, count 2 2006.173.03:04:46.50#ibcon#about to write, iclass 40, count 2 2006.173.03:04:46.50#ibcon#wrote, iclass 40, count 2 2006.173.03:04:46.50#ibcon#about to read 3, iclass 40, count 2 2006.173.03:04:46.52#ibcon#read 3, iclass 40, count 2 2006.173.03:04:46.52#ibcon#about to read 4, iclass 40, count 2 2006.173.03:04:46.52#ibcon#read 4, iclass 40, count 2 2006.173.03:04:46.52#ibcon#about to read 5, iclass 40, count 2 2006.173.03:04:46.52#ibcon#read 5, iclass 40, count 2 2006.173.03:04:46.52#ibcon#about to read 6, iclass 40, count 2 2006.173.03:04:46.52#ibcon#read 6, iclass 40, count 2 2006.173.03:04:46.52#ibcon#end of sib2, iclass 40, count 2 2006.173.03:04:46.52#ibcon#*mode == 0, iclass 40, count 2 2006.173.03:04:46.52#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.03:04:46.52#ibcon#[27=AT04-04\r\n] 2006.173.03:04:46.52#ibcon#*before write, iclass 40, count 2 2006.173.03:04:46.52#ibcon#enter sib2, iclass 40, count 2 2006.173.03:04:46.52#ibcon#flushed, iclass 40, count 2 2006.173.03:04:46.52#ibcon#about to write, iclass 40, count 2 2006.173.03:04:46.52#ibcon#wrote, iclass 40, count 2 2006.173.03:04:46.52#ibcon#about to read 3, iclass 40, count 2 2006.173.03:04:46.55#ibcon#read 3, iclass 40, count 2 2006.173.03:04:46.55#ibcon#about to read 4, iclass 40, count 2 2006.173.03:04:46.55#ibcon#read 4, iclass 40, count 2 2006.173.03:04:46.55#ibcon#about to read 5, iclass 40, count 2 2006.173.03:04:46.55#ibcon#read 5, iclass 40, count 2 2006.173.03:04:46.55#ibcon#about to read 6, iclass 40, count 2 2006.173.03:04:46.55#ibcon#read 6, iclass 40, count 2 2006.173.03:04:46.55#ibcon#end of sib2, iclass 40, count 2 2006.173.03:04:46.55#ibcon#*after write, iclass 40, count 2 2006.173.03:04:46.55#ibcon#*before return 0, iclass 40, count 2 2006.173.03:04:46.55#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.03:04:46.55#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.03:04:46.55#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.03:04:46.55#ibcon#ireg 7 cls_cnt 0 2006.173.03:04:46.55#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.03:04:46.67#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.03:04:46.67#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.03:04:46.67#ibcon#enter wrdev, iclass 40, count 0 2006.173.03:04:46.67#ibcon#first serial, iclass 40, count 0 2006.173.03:04:46.67#ibcon#enter sib2, iclass 40, count 0 2006.173.03:04:46.67#ibcon#flushed, iclass 40, count 0 2006.173.03:04:46.67#ibcon#about to write, iclass 40, count 0 2006.173.03:04:46.67#ibcon#wrote, iclass 40, count 0 2006.173.03:04:46.67#ibcon#about to read 3, iclass 40, count 0 2006.173.03:04:46.69#ibcon#read 3, iclass 40, count 0 2006.173.03:04:46.69#ibcon#about to read 4, iclass 40, count 0 2006.173.03:04:46.69#ibcon#read 4, iclass 40, count 0 2006.173.03:04:46.69#ibcon#about to read 5, iclass 40, count 0 2006.173.03:04:46.69#ibcon#read 5, iclass 40, count 0 2006.173.03:04:46.69#ibcon#about to read 6, iclass 40, count 0 2006.173.03:04:46.69#ibcon#read 6, iclass 40, count 0 2006.173.03:04:46.69#ibcon#end of sib2, iclass 40, count 0 2006.173.03:04:46.69#ibcon#*mode == 0, iclass 40, count 0 2006.173.03:04:46.69#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.03:04:46.69#ibcon#[27=USB\r\n] 2006.173.03:04:46.69#ibcon#*before write, iclass 40, count 0 2006.173.03:04:46.69#ibcon#enter sib2, iclass 40, count 0 2006.173.03:04:46.69#ibcon#flushed, iclass 40, count 0 2006.173.03:04:46.69#ibcon#about to write, iclass 40, count 0 2006.173.03:04:46.69#ibcon#wrote, iclass 40, count 0 2006.173.03:04:46.69#ibcon#about to read 3, iclass 40, count 0 2006.173.03:04:46.72#ibcon#read 3, iclass 40, count 0 2006.173.03:04:46.72#ibcon#about to read 4, iclass 40, count 0 2006.173.03:04:46.72#ibcon#read 4, iclass 40, count 0 2006.173.03:04:46.72#ibcon#about to read 5, iclass 40, count 0 2006.173.03:04:46.72#ibcon#read 5, iclass 40, count 0 2006.173.03:04:46.72#ibcon#about to read 6, iclass 40, count 0 2006.173.03:04:46.72#ibcon#read 6, iclass 40, count 0 2006.173.03:04:46.72#ibcon#end of sib2, iclass 40, count 0 2006.173.03:04:46.72#ibcon#*after write, iclass 40, count 0 2006.173.03:04:46.72#ibcon#*before return 0, iclass 40, count 0 2006.173.03:04:46.72#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.03:04:46.72#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.03:04:46.72#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.03:04:46.72#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.03:04:46.72$vck44/vblo=5,709.99 2006.173.03:04:46.72#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.03:04:46.72#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.03:04:46.72#ibcon#ireg 17 cls_cnt 0 2006.173.03:04:46.72#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.03:04:46.72#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.03:04:46.72#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.03:04:46.72#ibcon#enter wrdev, iclass 4, count 0 2006.173.03:04:46.72#ibcon#first serial, iclass 4, count 0 2006.173.03:04:46.72#ibcon#enter sib2, iclass 4, count 0 2006.173.03:04:46.72#ibcon#flushed, iclass 4, count 0 2006.173.03:04:46.72#ibcon#about to write, iclass 4, count 0 2006.173.03:04:46.72#ibcon#wrote, iclass 4, count 0 2006.173.03:04:46.72#ibcon#about to read 3, iclass 4, count 0 2006.173.03:04:46.74#ibcon#read 3, iclass 4, count 0 2006.173.03:04:46.74#ibcon#about to read 4, iclass 4, count 0 2006.173.03:04:46.74#ibcon#read 4, iclass 4, count 0 2006.173.03:04:46.74#ibcon#about to read 5, iclass 4, count 0 2006.173.03:04:46.74#ibcon#read 5, iclass 4, count 0 2006.173.03:04:46.74#ibcon#about to read 6, iclass 4, count 0 2006.173.03:04:46.74#ibcon#read 6, iclass 4, count 0 2006.173.03:04:46.74#ibcon#end of sib2, iclass 4, count 0 2006.173.03:04:46.74#ibcon#*mode == 0, iclass 4, count 0 2006.173.03:04:46.74#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.03:04:46.74#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.03:04:46.74#ibcon#*before write, iclass 4, count 0 2006.173.03:04:46.74#ibcon#enter sib2, iclass 4, count 0 2006.173.03:04:46.74#ibcon#flushed, iclass 4, count 0 2006.173.03:04:46.74#ibcon#about to write, iclass 4, count 0 2006.173.03:04:46.74#ibcon#wrote, iclass 4, count 0 2006.173.03:04:46.74#ibcon#about to read 3, iclass 4, count 0 2006.173.03:04:46.78#ibcon#read 3, iclass 4, count 0 2006.173.03:04:46.78#ibcon#about to read 4, iclass 4, count 0 2006.173.03:04:46.78#ibcon#read 4, iclass 4, count 0 2006.173.03:04:46.78#ibcon#about to read 5, iclass 4, count 0 2006.173.03:04:46.78#ibcon#read 5, iclass 4, count 0 2006.173.03:04:46.78#ibcon#about to read 6, iclass 4, count 0 2006.173.03:04:46.78#ibcon#read 6, iclass 4, count 0 2006.173.03:04:46.78#ibcon#end of sib2, iclass 4, count 0 2006.173.03:04:46.78#ibcon#*after write, iclass 4, count 0 2006.173.03:04:46.78#ibcon#*before return 0, iclass 4, count 0 2006.173.03:04:46.78#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.03:04:46.78#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.03:04:46.78#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.03:04:46.78#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.03:04:46.78$vck44/vb=5,4 2006.173.03:04:46.78#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.03:04:46.78#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.03:04:46.78#ibcon#ireg 11 cls_cnt 2 2006.173.03:04:46.78#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.03:04:46.84#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.03:04:46.84#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.03:04:46.84#ibcon#enter wrdev, iclass 6, count 2 2006.173.03:04:46.84#ibcon#first serial, iclass 6, count 2 2006.173.03:04:46.84#ibcon#enter sib2, iclass 6, count 2 2006.173.03:04:46.84#ibcon#flushed, iclass 6, count 2 2006.173.03:04:46.84#ibcon#about to write, iclass 6, count 2 2006.173.03:04:46.84#ibcon#wrote, iclass 6, count 2 2006.173.03:04:46.84#ibcon#about to read 3, iclass 6, count 2 2006.173.03:04:46.86#ibcon#read 3, iclass 6, count 2 2006.173.03:04:46.86#ibcon#about to read 4, iclass 6, count 2 2006.173.03:04:46.86#ibcon#read 4, iclass 6, count 2 2006.173.03:04:46.86#ibcon#about to read 5, iclass 6, count 2 2006.173.03:04:46.86#ibcon#read 5, iclass 6, count 2 2006.173.03:04:46.86#ibcon#about to read 6, iclass 6, count 2 2006.173.03:04:46.86#ibcon#read 6, iclass 6, count 2 2006.173.03:04:46.86#ibcon#end of sib2, iclass 6, count 2 2006.173.03:04:46.86#ibcon#*mode == 0, iclass 6, count 2 2006.173.03:04:46.86#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.03:04:46.86#ibcon#[27=AT05-04\r\n] 2006.173.03:04:46.86#ibcon#*before write, iclass 6, count 2 2006.173.03:04:46.86#ibcon#enter sib2, iclass 6, count 2 2006.173.03:04:46.86#ibcon#flushed, iclass 6, count 2 2006.173.03:04:46.86#ibcon#about to write, iclass 6, count 2 2006.173.03:04:46.86#ibcon#wrote, iclass 6, count 2 2006.173.03:04:46.86#ibcon#about to read 3, iclass 6, count 2 2006.173.03:04:46.89#ibcon#read 3, iclass 6, count 2 2006.173.03:04:46.89#ibcon#about to read 4, iclass 6, count 2 2006.173.03:04:46.89#ibcon#read 4, iclass 6, count 2 2006.173.03:04:46.89#ibcon#about to read 5, iclass 6, count 2 2006.173.03:04:46.89#ibcon#read 5, iclass 6, count 2 2006.173.03:04:46.89#ibcon#about to read 6, iclass 6, count 2 2006.173.03:04:46.89#ibcon#read 6, iclass 6, count 2 2006.173.03:04:46.89#ibcon#end of sib2, iclass 6, count 2 2006.173.03:04:46.89#ibcon#*after write, iclass 6, count 2 2006.173.03:04:46.89#ibcon#*before return 0, iclass 6, count 2 2006.173.03:04:46.89#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.03:04:46.89#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.03:04:46.89#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.03:04:46.89#ibcon#ireg 7 cls_cnt 0 2006.173.03:04:46.89#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.03:04:47.01#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.03:04:47.01#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.03:04:47.01#ibcon#enter wrdev, iclass 6, count 0 2006.173.03:04:47.01#ibcon#first serial, iclass 6, count 0 2006.173.03:04:47.01#ibcon#enter sib2, iclass 6, count 0 2006.173.03:04:47.01#ibcon#flushed, iclass 6, count 0 2006.173.03:04:47.01#ibcon#about to write, iclass 6, count 0 2006.173.03:04:47.01#ibcon#wrote, iclass 6, count 0 2006.173.03:04:47.01#ibcon#about to read 3, iclass 6, count 0 2006.173.03:04:47.03#ibcon#read 3, iclass 6, count 0 2006.173.03:04:47.03#ibcon#about to read 4, iclass 6, count 0 2006.173.03:04:47.03#ibcon#read 4, iclass 6, count 0 2006.173.03:04:47.03#ibcon#about to read 5, iclass 6, count 0 2006.173.03:04:47.03#ibcon#read 5, iclass 6, count 0 2006.173.03:04:47.03#ibcon#about to read 6, iclass 6, count 0 2006.173.03:04:47.03#ibcon#read 6, iclass 6, count 0 2006.173.03:04:47.03#ibcon#end of sib2, iclass 6, count 0 2006.173.03:04:47.03#ibcon#*mode == 0, iclass 6, count 0 2006.173.03:04:47.03#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.03:04:47.03#ibcon#[27=USB\r\n] 2006.173.03:04:47.03#ibcon#*before write, iclass 6, count 0 2006.173.03:04:47.03#ibcon#enter sib2, iclass 6, count 0 2006.173.03:04:47.03#ibcon#flushed, iclass 6, count 0 2006.173.03:04:47.03#ibcon#about to write, iclass 6, count 0 2006.173.03:04:47.03#ibcon#wrote, iclass 6, count 0 2006.173.03:04:47.03#ibcon#about to read 3, iclass 6, count 0 2006.173.03:04:47.06#ibcon#read 3, iclass 6, count 0 2006.173.03:04:47.06#ibcon#about to read 4, iclass 6, count 0 2006.173.03:04:47.06#ibcon#read 4, iclass 6, count 0 2006.173.03:04:47.06#ibcon#about to read 5, iclass 6, count 0 2006.173.03:04:47.06#ibcon#read 5, iclass 6, count 0 2006.173.03:04:47.06#ibcon#about to read 6, iclass 6, count 0 2006.173.03:04:47.06#ibcon#read 6, iclass 6, count 0 2006.173.03:04:47.06#ibcon#end of sib2, iclass 6, count 0 2006.173.03:04:47.06#ibcon#*after write, iclass 6, count 0 2006.173.03:04:47.06#ibcon#*before return 0, iclass 6, count 0 2006.173.03:04:47.06#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.03:04:47.06#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.03:04:47.06#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.03:04:47.06#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.03:04:47.06$vck44/vblo=6,719.99 2006.173.03:04:47.06#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.03:04:47.06#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.03:04:47.06#ibcon#ireg 17 cls_cnt 0 2006.173.03:04:47.06#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.03:04:47.06#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.03:04:47.06#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.03:04:47.06#ibcon#enter wrdev, iclass 10, count 0 2006.173.03:04:47.06#ibcon#first serial, iclass 10, count 0 2006.173.03:04:47.06#ibcon#enter sib2, iclass 10, count 0 2006.173.03:04:47.06#ibcon#flushed, iclass 10, count 0 2006.173.03:04:47.06#ibcon#about to write, iclass 10, count 0 2006.173.03:04:47.06#ibcon#wrote, iclass 10, count 0 2006.173.03:04:47.06#ibcon#about to read 3, iclass 10, count 0 2006.173.03:04:47.08#ibcon#read 3, iclass 10, count 0 2006.173.03:04:47.08#ibcon#about to read 4, iclass 10, count 0 2006.173.03:04:47.08#ibcon#read 4, iclass 10, count 0 2006.173.03:04:47.08#ibcon#about to read 5, iclass 10, count 0 2006.173.03:04:47.08#ibcon#read 5, iclass 10, count 0 2006.173.03:04:47.08#ibcon#about to read 6, iclass 10, count 0 2006.173.03:04:47.08#ibcon#read 6, iclass 10, count 0 2006.173.03:04:47.08#ibcon#end of sib2, iclass 10, count 0 2006.173.03:04:47.08#ibcon#*mode == 0, iclass 10, count 0 2006.173.03:04:47.08#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.03:04:47.08#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.03:04:47.08#ibcon#*before write, iclass 10, count 0 2006.173.03:04:47.08#ibcon#enter sib2, iclass 10, count 0 2006.173.03:04:47.08#ibcon#flushed, iclass 10, count 0 2006.173.03:04:47.08#ibcon#about to write, iclass 10, count 0 2006.173.03:04:47.08#ibcon#wrote, iclass 10, count 0 2006.173.03:04:47.08#ibcon#about to read 3, iclass 10, count 0 2006.173.03:04:47.12#ibcon#read 3, iclass 10, count 0 2006.173.03:04:47.12#ibcon#about to read 4, iclass 10, count 0 2006.173.03:04:47.12#ibcon#read 4, iclass 10, count 0 2006.173.03:04:47.12#ibcon#about to read 5, iclass 10, count 0 2006.173.03:04:47.12#ibcon#read 5, iclass 10, count 0 2006.173.03:04:47.12#ibcon#about to read 6, iclass 10, count 0 2006.173.03:04:47.12#ibcon#read 6, iclass 10, count 0 2006.173.03:04:47.12#ibcon#end of sib2, iclass 10, count 0 2006.173.03:04:47.12#ibcon#*after write, iclass 10, count 0 2006.173.03:04:47.12#ibcon#*before return 0, iclass 10, count 0 2006.173.03:04:47.12#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.03:04:47.12#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.03:04:47.12#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.03:04:47.12#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.03:04:47.12$vck44/vb=6,4 2006.173.03:04:47.12#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.03:04:47.12#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.03:04:47.12#ibcon#ireg 11 cls_cnt 2 2006.173.03:04:47.12#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.03:04:47.18#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.03:04:47.18#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.03:04:47.18#ibcon#enter wrdev, iclass 12, count 2 2006.173.03:04:47.18#ibcon#first serial, iclass 12, count 2 2006.173.03:04:47.18#ibcon#enter sib2, iclass 12, count 2 2006.173.03:04:47.18#ibcon#flushed, iclass 12, count 2 2006.173.03:04:47.18#ibcon#about to write, iclass 12, count 2 2006.173.03:04:47.18#ibcon#wrote, iclass 12, count 2 2006.173.03:04:47.18#ibcon#about to read 3, iclass 12, count 2 2006.173.03:04:47.20#ibcon#read 3, iclass 12, count 2 2006.173.03:04:47.20#ibcon#about to read 4, iclass 12, count 2 2006.173.03:04:47.20#ibcon#read 4, iclass 12, count 2 2006.173.03:04:47.20#ibcon#about to read 5, iclass 12, count 2 2006.173.03:04:47.20#ibcon#read 5, iclass 12, count 2 2006.173.03:04:47.20#ibcon#about to read 6, iclass 12, count 2 2006.173.03:04:47.20#ibcon#read 6, iclass 12, count 2 2006.173.03:04:47.20#ibcon#end of sib2, iclass 12, count 2 2006.173.03:04:47.20#ibcon#*mode == 0, iclass 12, count 2 2006.173.03:04:47.20#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.03:04:47.20#ibcon#[27=AT06-04\r\n] 2006.173.03:04:47.20#ibcon#*before write, iclass 12, count 2 2006.173.03:04:47.20#ibcon#enter sib2, iclass 12, count 2 2006.173.03:04:47.20#ibcon#flushed, iclass 12, count 2 2006.173.03:04:47.20#ibcon#about to write, iclass 12, count 2 2006.173.03:04:47.20#ibcon#wrote, iclass 12, count 2 2006.173.03:04:47.20#ibcon#about to read 3, iclass 12, count 2 2006.173.03:04:47.23#ibcon#read 3, iclass 12, count 2 2006.173.03:04:47.23#ibcon#about to read 4, iclass 12, count 2 2006.173.03:04:47.23#ibcon#read 4, iclass 12, count 2 2006.173.03:04:47.23#ibcon#about to read 5, iclass 12, count 2 2006.173.03:04:47.23#ibcon#read 5, iclass 12, count 2 2006.173.03:04:47.23#ibcon#about to read 6, iclass 12, count 2 2006.173.03:04:47.23#ibcon#read 6, iclass 12, count 2 2006.173.03:04:47.23#ibcon#end of sib2, iclass 12, count 2 2006.173.03:04:47.23#ibcon#*after write, iclass 12, count 2 2006.173.03:04:47.23#ibcon#*before return 0, iclass 12, count 2 2006.173.03:04:47.23#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.03:04:47.23#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.03:04:47.23#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.03:04:47.23#ibcon#ireg 7 cls_cnt 0 2006.173.03:04:47.23#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.03:04:47.35#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.03:04:47.35#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.03:04:47.35#ibcon#enter wrdev, iclass 12, count 0 2006.173.03:04:47.35#ibcon#first serial, iclass 12, count 0 2006.173.03:04:47.35#ibcon#enter sib2, iclass 12, count 0 2006.173.03:04:47.35#ibcon#flushed, iclass 12, count 0 2006.173.03:04:47.35#ibcon#about to write, iclass 12, count 0 2006.173.03:04:47.35#ibcon#wrote, iclass 12, count 0 2006.173.03:04:47.35#ibcon#about to read 3, iclass 12, count 0 2006.173.03:04:47.37#ibcon#read 3, iclass 12, count 0 2006.173.03:04:47.37#ibcon#about to read 4, iclass 12, count 0 2006.173.03:04:47.37#ibcon#read 4, iclass 12, count 0 2006.173.03:04:47.37#ibcon#about to read 5, iclass 12, count 0 2006.173.03:04:47.37#ibcon#read 5, iclass 12, count 0 2006.173.03:04:47.37#ibcon#about to read 6, iclass 12, count 0 2006.173.03:04:47.37#ibcon#read 6, iclass 12, count 0 2006.173.03:04:47.37#ibcon#end of sib2, iclass 12, count 0 2006.173.03:04:47.37#ibcon#*mode == 0, iclass 12, count 0 2006.173.03:04:47.37#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.03:04:47.37#ibcon#[27=USB\r\n] 2006.173.03:04:47.37#ibcon#*before write, iclass 12, count 0 2006.173.03:04:47.37#ibcon#enter sib2, iclass 12, count 0 2006.173.03:04:47.37#ibcon#flushed, iclass 12, count 0 2006.173.03:04:47.37#ibcon#about to write, iclass 12, count 0 2006.173.03:04:47.37#ibcon#wrote, iclass 12, count 0 2006.173.03:04:47.37#ibcon#about to read 3, iclass 12, count 0 2006.173.03:04:47.40#ibcon#read 3, iclass 12, count 0 2006.173.03:04:47.40#ibcon#about to read 4, iclass 12, count 0 2006.173.03:04:47.40#ibcon#read 4, iclass 12, count 0 2006.173.03:04:47.40#ibcon#about to read 5, iclass 12, count 0 2006.173.03:04:47.40#ibcon#read 5, iclass 12, count 0 2006.173.03:04:47.40#ibcon#about to read 6, iclass 12, count 0 2006.173.03:04:47.40#ibcon#read 6, iclass 12, count 0 2006.173.03:04:47.40#ibcon#end of sib2, iclass 12, count 0 2006.173.03:04:47.40#ibcon#*after write, iclass 12, count 0 2006.173.03:04:47.40#ibcon#*before return 0, iclass 12, count 0 2006.173.03:04:47.40#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.03:04:47.40#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.03:04:47.40#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.03:04:47.40#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.03:04:47.40$vck44/vblo=7,734.99 2006.173.03:04:47.40#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.03:04:47.40#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.03:04:47.40#ibcon#ireg 17 cls_cnt 0 2006.173.03:04:47.40#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.03:04:47.40#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.03:04:47.40#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.03:04:47.40#ibcon#enter wrdev, iclass 14, count 0 2006.173.03:04:47.40#ibcon#first serial, iclass 14, count 0 2006.173.03:04:47.40#ibcon#enter sib2, iclass 14, count 0 2006.173.03:04:47.40#ibcon#flushed, iclass 14, count 0 2006.173.03:04:47.40#ibcon#about to write, iclass 14, count 0 2006.173.03:04:47.40#ibcon#wrote, iclass 14, count 0 2006.173.03:04:47.40#ibcon#about to read 3, iclass 14, count 0 2006.173.03:04:47.42#ibcon#read 3, iclass 14, count 0 2006.173.03:04:47.42#ibcon#about to read 4, iclass 14, count 0 2006.173.03:04:47.42#ibcon#read 4, iclass 14, count 0 2006.173.03:04:47.42#ibcon#about to read 5, iclass 14, count 0 2006.173.03:04:47.42#ibcon#read 5, iclass 14, count 0 2006.173.03:04:47.42#ibcon#about to read 6, iclass 14, count 0 2006.173.03:04:47.42#ibcon#read 6, iclass 14, count 0 2006.173.03:04:47.42#ibcon#end of sib2, iclass 14, count 0 2006.173.03:04:47.42#ibcon#*mode == 0, iclass 14, count 0 2006.173.03:04:47.42#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.03:04:47.42#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.03:04:47.42#ibcon#*before write, iclass 14, count 0 2006.173.03:04:47.42#ibcon#enter sib2, iclass 14, count 0 2006.173.03:04:47.42#ibcon#flushed, iclass 14, count 0 2006.173.03:04:47.42#ibcon#about to write, iclass 14, count 0 2006.173.03:04:47.42#ibcon#wrote, iclass 14, count 0 2006.173.03:04:47.42#ibcon#about to read 3, iclass 14, count 0 2006.173.03:04:47.46#ibcon#read 3, iclass 14, count 0 2006.173.03:04:47.46#ibcon#about to read 4, iclass 14, count 0 2006.173.03:04:47.46#ibcon#read 4, iclass 14, count 0 2006.173.03:04:47.46#ibcon#about to read 5, iclass 14, count 0 2006.173.03:04:47.46#ibcon#read 5, iclass 14, count 0 2006.173.03:04:47.46#ibcon#about to read 6, iclass 14, count 0 2006.173.03:04:47.46#ibcon#read 6, iclass 14, count 0 2006.173.03:04:47.46#ibcon#end of sib2, iclass 14, count 0 2006.173.03:04:47.46#ibcon#*after write, iclass 14, count 0 2006.173.03:04:47.46#ibcon#*before return 0, iclass 14, count 0 2006.173.03:04:47.46#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.03:04:47.46#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.03:04:47.46#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.03:04:47.46#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.03:04:47.46$vck44/vb=7,4 2006.173.03:04:47.46#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.03:04:47.46#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.03:04:47.46#ibcon#ireg 11 cls_cnt 2 2006.173.03:04:47.46#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.03:04:47.52#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.03:04:47.52#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.03:04:47.52#ibcon#enter wrdev, iclass 16, count 2 2006.173.03:04:47.52#ibcon#first serial, iclass 16, count 2 2006.173.03:04:47.52#ibcon#enter sib2, iclass 16, count 2 2006.173.03:04:47.52#ibcon#flushed, iclass 16, count 2 2006.173.03:04:47.52#ibcon#about to write, iclass 16, count 2 2006.173.03:04:47.52#ibcon#wrote, iclass 16, count 2 2006.173.03:04:47.52#ibcon#about to read 3, iclass 16, count 2 2006.173.03:04:47.54#ibcon#read 3, iclass 16, count 2 2006.173.03:04:47.54#ibcon#about to read 4, iclass 16, count 2 2006.173.03:04:47.54#ibcon#read 4, iclass 16, count 2 2006.173.03:04:47.54#ibcon#about to read 5, iclass 16, count 2 2006.173.03:04:47.54#ibcon#read 5, iclass 16, count 2 2006.173.03:04:47.54#ibcon#about to read 6, iclass 16, count 2 2006.173.03:04:47.54#ibcon#read 6, iclass 16, count 2 2006.173.03:04:47.54#ibcon#end of sib2, iclass 16, count 2 2006.173.03:04:47.54#ibcon#*mode == 0, iclass 16, count 2 2006.173.03:04:47.54#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.03:04:47.54#ibcon#[27=AT07-04\r\n] 2006.173.03:04:47.54#ibcon#*before write, iclass 16, count 2 2006.173.03:04:47.54#ibcon#enter sib2, iclass 16, count 2 2006.173.03:04:47.54#ibcon#flushed, iclass 16, count 2 2006.173.03:04:47.54#ibcon#about to write, iclass 16, count 2 2006.173.03:04:47.54#ibcon#wrote, iclass 16, count 2 2006.173.03:04:47.54#ibcon#about to read 3, iclass 16, count 2 2006.173.03:04:47.57#ibcon#read 3, iclass 16, count 2 2006.173.03:04:47.57#ibcon#about to read 4, iclass 16, count 2 2006.173.03:04:47.57#ibcon#read 4, iclass 16, count 2 2006.173.03:04:47.57#ibcon#about to read 5, iclass 16, count 2 2006.173.03:04:47.57#ibcon#read 5, iclass 16, count 2 2006.173.03:04:47.57#ibcon#about to read 6, iclass 16, count 2 2006.173.03:04:47.57#ibcon#read 6, iclass 16, count 2 2006.173.03:04:47.57#ibcon#end of sib2, iclass 16, count 2 2006.173.03:04:47.57#ibcon#*after write, iclass 16, count 2 2006.173.03:04:47.57#ibcon#*before return 0, iclass 16, count 2 2006.173.03:04:47.57#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.03:04:47.57#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.03:04:47.57#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.03:04:47.57#ibcon#ireg 7 cls_cnt 0 2006.173.03:04:47.57#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.03:04:47.69#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.03:04:47.69#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.03:04:47.69#ibcon#enter wrdev, iclass 16, count 0 2006.173.03:04:47.69#ibcon#first serial, iclass 16, count 0 2006.173.03:04:47.69#ibcon#enter sib2, iclass 16, count 0 2006.173.03:04:47.69#ibcon#flushed, iclass 16, count 0 2006.173.03:04:47.69#ibcon#about to write, iclass 16, count 0 2006.173.03:04:47.69#ibcon#wrote, iclass 16, count 0 2006.173.03:04:47.69#ibcon#about to read 3, iclass 16, count 0 2006.173.03:04:47.71#ibcon#read 3, iclass 16, count 0 2006.173.03:04:47.71#ibcon#about to read 4, iclass 16, count 0 2006.173.03:04:47.71#ibcon#read 4, iclass 16, count 0 2006.173.03:04:47.71#ibcon#about to read 5, iclass 16, count 0 2006.173.03:04:47.71#ibcon#read 5, iclass 16, count 0 2006.173.03:04:47.71#ibcon#about to read 6, iclass 16, count 0 2006.173.03:04:47.71#ibcon#read 6, iclass 16, count 0 2006.173.03:04:47.71#ibcon#end of sib2, iclass 16, count 0 2006.173.03:04:47.71#ibcon#*mode == 0, iclass 16, count 0 2006.173.03:04:47.71#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.03:04:47.71#ibcon#[27=USB\r\n] 2006.173.03:04:47.71#ibcon#*before write, iclass 16, count 0 2006.173.03:04:47.71#ibcon#enter sib2, iclass 16, count 0 2006.173.03:04:47.71#ibcon#flushed, iclass 16, count 0 2006.173.03:04:47.71#ibcon#about to write, iclass 16, count 0 2006.173.03:04:47.71#ibcon#wrote, iclass 16, count 0 2006.173.03:04:47.71#ibcon#about to read 3, iclass 16, count 0 2006.173.03:04:47.74#ibcon#read 3, iclass 16, count 0 2006.173.03:04:47.74#ibcon#about to read 4, iclass 16, count 0 2006.173.03:04:47.74#ibcon#read 4, iclass 16, count 0 2006.173.03:04:47.74#ibcon#about to read 5, iclass 16, count 0 2006.173.03:04:47.74#ibcon#read 5, iclass 16, count 0 2006.173.03:04:47.74#ibcon#about to read 6, iclass 16, count 0 2006.173.03:04:47.74#ibcon#read 6, iclass 16, count 0 2006.173.03:04:47.74#ibcon#end of sib2, iclass 16, count 0 2006.173.03:04:47.74#ibcon#*after write, iclass 16, count 0 2006.173.03:04:47.74#ibcon#*before return 0, iclass 16, count 0 2006.173.03:04:47.74#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.03:04:47.74#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.03:04:47.74#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.03:04:47.74#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.03:04:47.74$vck44/vblo=8,744.99 2006.173.03:04:47.74#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.03:04:47.74#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.03:04:47.74#ibcon#ireg 17 cls_cnt 0 2006.173.03:04:47.74#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.03:04:47.74#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.03:04:47.74#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.03:04:47.74#ibcon#enter wrdev, iclass 18, count 0 2006.173.03:04:47.74#ibcon#first serial, iclass 18, count 0 2006.173.03:04:47.74#ibcon#enter sib2, iclass 18, count 0 2006.173.03:04:47.74#ibcon#flushed, iclass 18, count 0 2006.173.03:04:47.74#ibcon#about to write, iclass 18, count 0 2006.173.03:04:47.74#ibcon#wrote, iclass 18, count 0 2006.173.03:04:47.74#ibcon#about to read 3, iclass 18, count 0 2006.173.03:04:47.76#ibcon#read 3, iclass 18, count 0 2006.173.03:04:47.76#ibcon#about to read 4, iclass 18, count 0 2006.173.03:04:47.76#ibcon#read 4, iclass 18, count 0 2006.173.03:04:47.76#ibcon#about to read 5, iclass 18, count 0 2006.173.03:04:47.76#ibcon#read 5, iclass 18, count 0 2006.173.03:04:47.76#ibcon#about to read 6, iclass 18, count 0 2006.173.03:04:47.76#ibcon#read 6, iclass 18, count 0 2006.173.03:04:47.76#ibcon#end of sib2, iclass 18, count 0 2006.173.03:04:47.76#ibcon#*mode == 0, iclass 18, count 0 2006.173.03:04:47.76#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.03:04:47.76#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.03:04:47.76#ibcon#*before write, iclass 18, count 0 2006.173.03:04:47.76#ibcon#enter sib2, iclass 18, count 0 2006.173.03:04:47.76#ibcon#flushed, iclass 18, count 0 2006.173.03:04:47.76#ibcon#about to write, iclass 18, count 0 2006.173.03:04:47.76#ibcon#wrote, iclass 18, count 0 2006.173.03:04:47.76#ibcon#about to read 3, iclass 18, count 0 2006.173.03:04:47.80#ibcon#read 3, iclass 18, count 0 2006.173.03:04:47.80#ibcon#about to read 4, iclass 18, count 0 2006.173.03:04:47.80#ibcon#read 4, iclass 18, count 0 2006.173.03:04:47.80#ibcon#about to read 5, iclass 18, count 0 2006.173.03:04:47.80#ibcon#read 5, iclass 18, count 0 2006.173.03:04:47.80#ibcon#about to read 6, iclass 18, count 0 2006.173.03:04:47.80#ibcon#read 6, iclass 18, count 0 2006.173.03:04:47.80#ibcon#end of sib2, iclass 18, count 0 2006.173.03:04:47.80#ibcon#*after write, iclass 18, count 0 2006.173.03:04:47.80#ibcon#*before return 0, iclass 18, count 0 2006.173.03:04:47.80#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.03:04:47.80#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.03:04:47.80#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.03:04:47.80#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.03:04:47.80$vck44/vb=8,4 2006.173.03:04:47.80#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.03:04:47.80#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.03:04:47.80#ibcon#ireg 11 cls_cnt 2 2006.173.03:04:47.80#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.03:04:47.86#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.03:04:47.86#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.03:04:47.86#ibcon#enter wrdev, iclass 20, count 2 2006.173.03:04:47.86#ibcon#first serial, iclass 20, count 2 2006.173.03:04:47.86#ibcon#enter sib2, iclass 20, count 2 2006.173.03:04:47.86#ibcon#flushed, iclass 20, count 2 2006.173.03:04:47.86#ibcon#about to write, iclass 20, count 2 2006.173.03:04:47.86#ibcon#wrote, iclass 20, count 2 2006.173.03:04:47.86#ibcon#about to read 3, iclass 20, count 2 2006.173.03:04:47.88#ibcon#read 3, iclass 20, count 2 2006.173.03:04:47.88#ibcon#about to read 4, iclass 20, count 2 2006.173.03:04:47.88#ibcon#read 4, iclass 20, count 2 2006.173.03:04:47.88#ibcon#about to read 5, iclass 20, count 2 2006.173.03:04:47.88#ibcon#read 5, iclass 20, count 2 2006.173.03:04:47.88#ibcon#about to read 6, iclass 20, count 2 2006.173.03:04:47.88#ibcon#read 6, iclass 20, count 2 2006.173.03:04:47.88#ibcon#end of sib2, iclass 20, count 2 2006.173.03:04:47.88#ibcon#*mode == 0, iclass 20, count 2 2006.173.03:04:47.88#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.03:04:47.88#ibcon#[27=AT08-04\r\n] 2006.173.03:04:47.88#ibcon#*before write, iclass 20, count 2 2006.173.03:04:47.88#ibcon#enter sib2, iclass 20, count 2 2006.173.03:04:47.88#ibcon#flushed, iclass 20, count 2 2006.173.03:04:47.88#ibcon#about to write, iclass 20, count 2 2006.173.03:04:47.88#ibcon#wrote, iclass 20, count 2 2006.173.03:04:47.88#ibcon#about to read 3, iclass 20, count 2 2006.173.03:04:47.91#ibcon#read 3, iclass 20, count 2 2006.173.03:04:47.91#ibcon#about to read 4, iclass 20, count 2 2006.173.03:04:47.91#ibcon#read 4, iclass 20, count 2 2006.173.03:04:47.91#ibcon#about to read 5, iclass 20, count 2 2006.173.03:04:47.91#ibcon#read 5, iclass 20, count 2 2006.173.03:04:47.91#ibcon#about to read 6, iclass 20, count 2 2006.173.03:04:47.91#ibcon#read 6, iclass 20, count 2 2006.173.03:04:47.91#ibcon#end of sib2, iclass 20, count 2 2006.173.03:04:47.91#ibcon#*after write, iclass 20, count 2 2006.173.03:04:47.91#ibcon#*before return 0, iclass 20, count 2 2006.173.03:04:47.91#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.03:04:47.91#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.03:04:47.91#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.03:04:47.91#ibcon#ireg 7 cls_cnt 0 2006.173.03:04:47.91#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.03:04:48.03#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.03:04:48.03#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.03:04:48.03#ibcon#enter wrdev, iclass 20, count 0 2006.173.03:04:48.03#ibcon#first serial, iclass 20, count 0 2006.173.03:04:48.03#ibcon#enter sib2, iclass 20, count 0 2006.173.03:04:48.03#ibcon#flushed, iclass 20, count 0 2006.173.03:04:48.03#ibcon#about to write, iclass 20, count 0 2006.173.03:04:48.03#ibcon#wrote, iclass 20, count 0 2006.173.03:04:48.03#ibcon#about to read 3, iclass 20, count 0 2006.173.03:04:48.05#ibcon#read 3, iclass 20, count 0 2006.173.03:04:48.05#ibcon#about to read 4, iclass 20, count 0 2006.173.03:04:48.05#ibcon#read 4, iclass 20, count 0 2006.173.03:04:48.05#ibcon#about to read 5, iclass 20, count 0 2006.173.03:04:48.05#ibcon#read 5, iclass 20, count 0 2006.173.03:04:48.05#ibcon#about to read 6, iclass 20, count 0 2006.173.03:04:48.05#ibcon#read 6, iclass 20, count 0 2006.173.03:04:48.05#ibcon#end of sib2, iclass 20, count 0 2006.173.03:04:48.05#ibcon#*mode == 0, iclass 20, count 0 2006.173.03:04:48.05#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.03:04:48.05#ibcon#[27=USB\r\n] 2006.173.03:04:48.05#ibcon#*before write, iclass 20, count 0 2006.173.03:04:48.05#ibcon#enter sib2, iclass 20, count 0 2006.173.03:04:48.05#ibcon#flushed, iclass 20, count 0 2006.173.03:04:48.05#ibcon#about to write, iclass 20, count 0 2006.173.03:04:48.05#ibcon#wrote, iclass 20, count 0 2006.173.03:04:48.05#ibcon#about to read 3, iclass 20, count 0 2006.173.03:04:48.08#ibcon#read 3, iclass 20, count 0 2006.173.03:04:48.08#ibcon#about to read 4, iclass 20, count 0 2006.173.03:04:48.08#ibcon#read 4, iclass 20, count 0 2006.173.03:04:48.08#ibcon#about to read 5, iclass 20, count 0 2006.173.03:04:48.08#ibcon#read 5, iclass 20, count 0 2006.173.03:04:48.08#ibcon#about to read 6, iclass 20, count 0 2006.173.03:04:48.08#ibcon#read 6, iclass 20, count 0 2006.173.03:04:48.08#ibcon#end of sib2, iclass 20, count 0 2006.173.03:04:48.08#ibcon#*after write, iclass 20, count 0 2006.173.03:04:48.08#ibcon#*before return 0, iclass 20, count 0 2006.173.03:04:48.08#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.03:04:48.08#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.03:04:48.08#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.03:04:48.08#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.03:04:48.08$vck44/vabw=wide 2006.173.03:04:48.08#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.03:04:48.08#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.03:04:48.08#ibcon#ireg 8 cls_cnt 0 2006.173.03:04:48.08#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.03:04:48.08#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.03:04:48.08#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.03:04:48.08#ibcon#enter wrdev, iclass 22, count 0 2006.173.03:04:48.08#ibcon#first serial, iclass 22, count 0 2006.173.03:04:48.08#ibcon#enter sib2, iclass 22, count 0 2006.173.03:04:48.08#ibcon#flushed, iclass 22, count 0 2006.173.03:04:48.08#ibcon#about to write, iclass 22, count 0 2006.173.03:04:48.08#ibcon#wrote, iclass 22, count 0 2006.173.03:04:48.08#ibcon#about to read 3, iclass 22, count 0 2006.173.03:04:48.10#ibcon#read 3, iclass 22, count 0 2006.173.03:04:48.10#ibcon#about to read 4, iclass 22, count 0 2006.173.03:04:48.10#ibcon#read 4, iclass 22, count 0 2006.173.03:04:48.10#ibcon#about to read 5, iclass 22, count 0 2006.173.03:04:48.10#ibcon#read 5, iclass 22, count 0 2006.173.03:04:48.10#ibcon#about to read 6, iclass 22, count 0 2006.173.03:04:48.10#ibcon#read 6, iclass 22, count 0 2006.173.03:04:48.10#ibcon#end of sib2, iclass 22, count 0 2006.173.03:04:48.10#ibcon#*mode == 0, iclass 22, count 0 2006.173.03:04:48.10#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.03:04:48.10#ibcon#[25=BW32\r\n] 2006.173.03:04:48.10#ibcon#*before write, iclass 22, count 0 2006.173.03:04:48.10#ibcon#enter sib2, iclass 22, count 0 2006.173.03:04:48.10#ibcon#flushed, iclass 22, count 0 2006.173.03:04:48.10#ibcon#about to write, iclass 22, count 0 2006.173.03:04:48.10#ibcon#wrote, iclass 22, count 0 2006.173.03:04:48.10#ibcon#about to read 3, iclass 22, count 0 2006.173.03:04:48.13#ibcon#read 3, iclass 22, count 0 2006.173.03:04:48.13#ibcon#about to read 4, iclass 22, count 0 2006.173.03:04:48.13#ibcon#read 4, iclass 22, count 0 2006.173.03:04:48.13#ibcon#about to read 5, iclass 22, count 0 2006.173.03:04:48.13#ibcon#read 5, iclass 22, count 0 2006.173.03:04:48.13#ibcon#about to read 6, iclass 22, count 0 2006.173.03:04:48.13#ibcon#read 6, iclass 22, count 0 2006.173.03:04:48.13#ibcon#end of sib2, iclass 22, count 0 2006.173.03:04:48.13#ibcon#*after write, iclass 22, count 0 2006.173.03:04:48.13#ibcon#*before return 0, iclass 22, count 0 2006.173.03:04:48.13#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.03:04:48.13#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.03:04:48.13#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.03:04:48.13#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.03:04:48.13$vck44/vbbw=wide 2006.173.03:04:48.13#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.03:04:48.13#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.03:04:48.13#ibcon#ireg 8 cls_cnt 0 2006.173.03:04:48.13#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.03:04:48.20#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.03:04:48.20#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.03:04:48.20#ibcon#enter wrdev, iclass 24, count 0 2006.173.03:04:48.20#ibcon#first serial, iclass 24, count 0 2006.173.03:04:48.20#ibcon#enter sib2, iclass 24, count 0 2006.173.03:04:48.20#ibcon#flushed, iclass 24, count 0 2006.173.03:04:48.20#ibcon#about to write, iclass 24, count 0 2006.173.03:04:48.20#ibcon#wrote, iclass 24, count 0 2006.173.03:04:48.20#ibcon#about to read 3, iclass 24, count 0 2006.173.03:04:48.22#ibcon#read 3, iclass 24, count 0 2006.173.03:04:48.22#ibcon#about to read 4, iclass 24, count 0 2006.173.03:04:48.22#ibcon#read 4, iclass 24, count 0 2006.173.03:04:48.22#ibcon#about to read 5, iclass 24, count 0 2006.173.03:04:48.22#ibcon#read 5, iclass 24, count 0 2006.173.03:04:48.22#ibcon#about to read 6, iclass 24, count 0 2006.173.03:04:48.22#ibcon#read 6, iclass 24, count 0 2006.173.03:04:48.22#ibcon#end of sib2, iclass 24, count 0 2006.173.03:04:48.22#ibcon#*mode == 0, iclass 24, count 0 2006.173.03:04:48.22#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.03:04:48.22#ibcon#[27=BW32\r\n] 2006.173.03:04:48.22#ibcon#*before write, iclass 24, count 0 2006.173.03:04:48.22#ibcon#enter sib2, iclass 24, count 0 2006.173.03:04:48.22#ibcon#flushed, iclass 24, count 0 2006.173.03:04:48.22#ibcon#about to write, iclass 24, count 0 2006.173.03:04:48.22#ibcon#wrote, iclass 24, count 0 2006.173.03:04:48.22#ibcon#about to read 3, iclass 24, count 0 2006.173.03:04:48.25#ibcon#read 3, iclass 24, count 0 2006.173.03:04:48.25#ibcon#about to read 4, iclass 24, count 0 2006.173.03:04:48.25#ibcon#read 4, iclass 24, count 0 2006.173.03:04:48.25#ibcon#about to read 5, iclass 24, count 0 2006.173.03:04:48.25#ibcon#read 5, iclass 24, count 0 2006.173.03:04:48.25#ibcon#about to read 6, iclass 24, count 0 2006.173.03:04:48.25#ibcon#read 6, iclass 24, count 0 2006.173.03:04:48.25#ibcon#end of sib2, iclass 24, count 0 2006.173.03:04:48.25#ibcon#*after write, iclass 24, count 0 2006.173.03:04:48.25#ibcon#*before return 0, iclass 24, count 0 2006.173.03:04:48.25#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.03:04:48.25#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.03:04:48.25#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.03:04:48.25#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.03:04:48.25$setupk4/ifdk4 2006.173.03:04:48.25$ifdk4/lo= 2006.173.03:04:48.25$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.03:04:48.25$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.03:04:48.25$ifdk4/patch= 2006.173.03:04:48.25$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.03:04:48.25$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.03:04:48.25$setupk4/!*+20s 2006.173.03:04:50.05#abcon#<5=/14 1.4 3.0 22.30 841006.4\r\n> 2006.173.03:04:50.07#abcon#{5=INTERFACE CLEAR} 2006.173.03:04:50.13#abcon#[5=S1D000X0/0*\r\n] 2006.173.03:05:00.22#abcon#<5=/14 1.4 2.9 22.30 841006.4\r\n> 2006.173.03:05:00.24#abcon#{5=INTERFACE CLEAR} 2006.173.03:05:00.30#abcon#[5=S1D000X0/0*\r\n] 2006.173.03:05:02.75$setupk4/"tpicd 2006.173.03:05:02.75$setupk4/echo=off 2006.173.03:05:02.75$setupk4/xlog=off 2006.173.03:05:02.75:!2006.173.03:06:19 2006.173.03:06:12.14#trakl#Source acquired 2006.173.03:06:13.14#flagr#flagr/antenna,acquired 2006.173.03:06:19.00:preob 2006.173.03:06:20.14/onsource/TRACKING 2006.173.03:06:20.14:!2006.173.03:06:29 2006.173.03:06:29.00:"tape 2006.173.03:06:29.00:"st=record 2006.173.03:06:29.00:data_valid=on 2006.173.03:06:29.00:midob 2006.173.03:06:29.14/onsource/TRACKING 2006.173.03:06:29.14/wx/22.28,1006.4,84 2006.173.03:06:29.21/cable/+6.5128E-03 2006.173.03:06:30.30/va/01,07,usb,yes,36,39 2006.173.03:06:30.30/va/02,06,usb,yes,36,36 2006.173.03:06:30.30/va/03,05,usb,yes,45,47 2006.173.03:06:30.30/va/04,06,usb,yes,36,38 2006.173.03:06:30.30/va/05,04,usb,yes,29,29 2006.173.03:06:30.30/va/06,03,usb,yes,40,40 2006.173.03:06:30.30/va/07,04,usb,yes,32,34 2006.173.03:06:30.30/va/08,04,usb,yes,28,33 2006.173.03:06:30.53/valo/01,524.99,yes,locked 2006.173.03:06:30.53/valo/02,534.99,yes,locked 2006.173.03:06:30.53/valo/03,564.99,yes,locked 2006.173.03:06:30.53/valo/04,624.99,yes,locked 2006.173.03:06:30.53/valo/05,734.99,yes,locked 2006.173.03:06:30.53/valo/06,814.99,yes,locked 2006.173.03:06:30.53/valo/07,864.99,yes,locked 2006.173.03:06:30.53/valo/08,884.99,yes,locked 2006.173.03:06:31.62/vb/01,04,usb,yes,29,27 2006.173.03:06:31.62/vb/02,04,usb,yes,31,31 2006.173.03:06:31.62/vb/03,04,usb,yes,28,31 2006.173.03:06:31.62/vb/04,04,usb,yes,33,32 2006.173.03:06:31.62/vb/05,04,usb,yes,26,28 2006.173.03:06:31.62/vb/06,04,usb,yes,30,26 2006.173.03:06:31.62/vb/07,04,usb,yes,29,29 2006.173.03:06:31.62/vb/08,04,usb,yes,27,30 2006.173.03:06:31.85/vblo/01,629.99,yes,locked 2006.173.03:06:31.85/vblo/02,634.99,yes,locked 2006.173.03:06:31.85/vblo/03,649.99,yes,locked 2006.173.03:06:31.85/vblo/04,679.99,yes,locked 2006.173.03:06:31.85/vblo/05,709.99,yes,locked 2006.173.03:06:31.85/vblo/06,719.99,yes,locked 2006.173.03:06:31.85/vblo/07,734.99,yes,locked 2006.173.03:06:31.85/vblo/08,744.99,yes,locked 2006.173.03:06:32.00/vabw/8 2006.173.03:06:32.15/vbbw/8 2006.173.03:06:32.24/xfe/off,on,14.2 2006.173.03:06:32.63/ifatt/23,28,28,28 2006.173.03:06:33.07/fmout-gps/S +3.91E-07 2006.173.03:06:33.11:!2006.173.03:11:39 2006.173.03:11:39.00:data_valid=off 2006.173.03:11:39.00:"et 2006.173.03:11:39.01:!+3s 2006.173.03:11:42.02:"tape 2006.173.03:11:42.02:postob 2006.173.03:11:42.12/cable/+6.5119E-03 2006.173.03:11:42.12/wx/22.28,1006.3,85 2006.173.03:11:42.18/fmout-gps/S +3.90E-07 2006.173.03:11:42.18:scan_name=173-0316,jd0606,40 2006.173.03:11:42.19:source=4c39.25,092703.01,390220.9,2000.0,cw 2006.173.03:11:44.14#flagr#flagr/antenna,new-source 2006.173.03:11:44.14:checkk5 2006.173.03:11:44.49/chk_autoobs//k5ts1/ autoobs is running! 2006.173.03:11:44.84/chk_autoobs//k5ts2/ autoobs is running! 2006.173.03:11:45.17/chk_autoobs//k5ts3/ autoobs is running! 2006.173.03:11:45.52/chk_autoobs//k5ts4/ autoobs is running! 2006.173.03:11:45.85/chk_obsdata//k5ts1/T1730306??a.dat file size is correct (nominal:1240MB, actual:1236MB). 2006.173.03:11:46.19/chk_obsdata//k5ts2/T1730306??b.dat file size is correct (nominal:1240MB, actual:1236MB). 2006.173.03:11:46.52/chk_obsdata//k5ts3/T1730306??c.dat file size is correct (nominal:1240MB, actual:1236MB). 2006.173.03:11:46.86/chk_obsdata//k5ts4/T1730306??d.dat file size is correct (nominal:1240MB, actual:1236MB). 2006.173.03:11:47.51/k5log//k5ts1_log_newline 2006.173.03:11:48.17/k5log//k5ts2_log_newline 2006.173.03:11:48.82/k5log//k5ts3_log_newline 2006.173.03:11:49.48/k5log//k5ts4_log_newline 2006.173.03:11:49.51/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.03:11:49.51:setupk4=1 2006.173.03:11:49.51$setupk4/echo=on 2006.173.03:11:49.51$setupk4/pcalon 2006.173.03:11:49.51$pcalon/"no phase cal control is implemented here 2006.173.03:11:49.51$setupk4/"tpicd=stop 2006.173.03:11:49.51$setupk4/"rec=synch_on 2006.173.03:11:49.51$setupk4/"rec_mode=128 2006.173.03:11:49.51$setupk4/!* 2006.173.03:11:49.51$setupk4/recpk4 2006.173.03:11:49.51$recpk4/recpatch= 2006.173.03:11:49.51$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.03:11:49.51$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.03:11:49.51$setupk4/vck44 2006.173.03:11:49.51$vck44/valo=1,524.99 2006.173.03:11:49.51#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.03:11:49.51#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.03:11:49.51#ibcon#ireg 17 cls_cnt 0 2006.173.03:11:49.51#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.03:11:49.51#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.03:11:49.51#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.03:11:49.51#ibcon#enter wrdev, iclass 17, count 0 2006.173.03:11:49.51#ibcon#first serial, iclass 17, count 0 2006.173.03:11:49.51#ibcon#enter sib2, iclass 17, count 0 2006.173.03:11:49.51#ibcon#flushed, iclass 17, count 0 2006.173.03:11:49.51#ibcon#about to write, iclass 17, count 0 2006.173.03:11:49.51#ibcon#wrote, iclass 17, count 0 2006.173.03:11:49.51#ibcon#about to read 3, iclass 17, count 0 2006.173.03:11:49.53#ibcon#read 3, iclass 17, count 0 2006.173.03:11:49.53#ibcon#about to read 4, iclass 17, count 0 2006.173.03:11:49.53#ibcon#read 4, iclass 17, count 0 2006.173.03:11:49.53#ibcon#about to read 5, iclass 17, count 0 2006.173.03:11:49.53#ibcon#read 5, iclass 17, count 0 2006.173.03:11:49.53#ibcon#about to read 6, iclass 17, count 0 2006.173.03:11:49.53#ibcon#read 6, iclass 17, count 0 2006.173.03:11:49.53#ibcon#end of sib2, iclass 17, count 0 2006.173.03:11:49.53#ibcon#*mode == 0, iclass 17, count 0 2006.173.03:11:49.53#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.03:11:49.53#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.03:11:49.53#ibcon#*before write, iclass 17, count 0 2006.173.03:11:49.53#ibcon#enter sib2, iclass 17, count 0 2006.173.03:11:49.53#ibcon#flushed, iclass 17, count 0 2006.173.03:11:49.53#ibcon#about to write, iclass 17, count 0 2006.173.03:11:49.53#ibcon#wrote, iclass 17, count 0 2006.173.03:11:49.53#ibcon#about to read 3, iclass 17, count 0 2006.173.03:11:49.58#ibcon#read 3, iclass 17, count 0 2006.173.03:11:49.58#ibcon#about to read 4, iclass 17, count 0 2006.173.03:11:49.58#ibcon#read 4, iclass 17, count 0 2006.173.03:11:49.58#ibcon#about to read 5, iclass 17, count 0 2006.173.03:11:49.58#ibcon#read 5, iclass 17, count 0 2006.173.03:11:49.58#ibcon#about to read 6, iclass 17, count 0 2006.173.03:11:49.58#ibcon#read 6, iclass 17, count 0 2006.173.03:11:49.58#ibcon#end of sib2, iclass 17, count 0 2006.173.03:11:49.58#ibcon#*after write, iclass 17, count 0 2006.173.03:11:49.58#ibcon#*before return 0, iclass 17, count 0 2006.173.03:11:49.58#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.03:11:49.58#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.03:11:49.58#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.03:11:49.58#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.03:11:49.58$vck44/va=1,7 2006.173.03:11:49.58#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.03:11:49.58#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.03:11:49.58#ibcon#ireg 11 cls_cnt 2 2006.173.03:11:49.58#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.03:11:49.58#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.03:11:49.58#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.03:11:49.58#ibcon#enter wrdev, iclass 19, count 2 2006.173.03:11:49.58#ibcon#first serial, iclass 19, count 2 2006.173.03:11:49.58#ibcon#enter sib2, iclass 19, count 2 2006.173.03:11:49.58#ibcon#flushed, iclass 19, count 2 2006.173.03:11:49.58#ibcon#about to write, iclass 19, count 2 2006.173.03:11:49.58#ibcon#wrote, iclass 19, count 2 2006.173.03:11:49.58#ibcon#about to read 3, iclass 19, count 2 2006.173.03:11:49.60#ibcon#read 3, iclass 19, count 2 2006.173.03:11:49.60#ibcon#about to read 4, iclass 19, count 2 2006.173.03:11:49.60#ibcon#read 4, iclass 19, count 2 2006.173.03:11:49.60#ibcon#about to read 5, iclass 19, count 2 2006.173.03:11:49.60#ibcon#read 5, iclass 19, count 2 2006.173.03:11:49.60#ibcon#about to read 6, iclass 19, count 2 2006.173.03:11:49.60#ibcon#read 6, iclass 19, count 2 2006.173.03:11:49.60#ibcon#end of sib2, iclass 19, count 2 2006.173.03:11:49.60#ibcon#*mode == 0, iclass 19, count 2 2006.173.03:11:49.60#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.03:11:49.60#ibcon#[25=AT01-07\r\n] 2006.173.03:11:49.60#ibcon#*before write, iclass 19, count 2 2006.173.03:11:49.60#ibcon#enter sib2, iclass 19, count 2 2006.173.03:11:49.60#ibcon#flushed, iclass 19, count 2 2006.173.03:11:49.60#ibcon#about to write, iclass 19, count 2 2006.173.03:11:49.60#ibcon#wrote, iclass 19, count 2 2006.173.03:11:49.60#ibcon#about to read 3, iclass 19, count 2 2006.173.03:11:49.63#ibcon#read 3, iclass 19, count 2 2006.173.03:11:49.63#ibcon#about to read 4, iclass 19, count 2 2006.173.03:11:49.63#ibcon#read 4, iclass 19, count 2 2006.173.03:11:49.63#ibcon#about to read 5, iclass 19, count 2 2006.173.03:11:49.63#ibcon#read 5, iclass 19, count 2 2006.173.03:11:49.63#ibcon#about to read 6, iclass 19, count 2 2006.173.03:11:49.63#ibcon#read 6, iclass 19, count 2 2006.173.03:11:49.63#ibcon#end of sib2, iclass 19, count 2 2006.173.03:11:49.63#ibcon#*after write, iclass 19, count 2 2006.173.03:11:49.63#ibcon#*before return 0, iclass 19, count 2 2006.173.03:11:49.63#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.03:11:49.63#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.03:11:49.63#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.03:11:49.63#ibcon#ireg 7 cls_cnt 0 2006.173.03:11:49.63#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.03:11:49.75#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.03:11:49.75#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.03:11:49.75#ibcon#enter wrdev, iclass 19, count 0 2006.173.03:11:49.75#ibcon#first serial, iclass 19, count 0 2006.173.03:11:49.75#ibcon#enter sib2, iclass 19, count 0 2006.173.03:11:49.75#ibcon#flushed, iclass 19, count 0 2006.173.03:11:49.75#ibcon#about to write, iclass 19, count 0 2006.173.03:11:49.75#ibcon#wrote, iclass 19, count 0 2006.173.03:11:49.75#ibcon#about to read 3, iclass 19, count 0 2006.173.03:11:49.77#ibcon#read 3, iclass 19, count 0 2006.173.03:11:49.77#ibcon#about to read 4, iclass 19, count 0 2006.173.03:11:49.77#ibcon#read 4, iclass 19, count 0 2006.173.03:11:49.77#ibcon#about to read 5, iclass 19, count 0 2006.173.03:11:49.77#ibcon#read 5, iclass 19, count 0 2006.173.03:11:49.77#ibcon#about to read 6, iclass 19, count 0 2006.173.03:11:49.77#ibcon#read 6, iclass 19, count 0 2006.173.03:11:49.77#ibcon#end of sib2, iclass 19, count 0 2006.173.03:11:49.77#ibcon#*mode == 0, iclass 19, count 0 2006.173.03:11:49.77#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.03:11:49.77#ibcon#[25=USB\r\n] 2006.173.03:11:49.77#ibcon#*before write, iclass 19, count 0 2006.173.03:11:49.77#ibcon#enter sib2, iclass 19, count 0 2006.173.03:11:49.77#ibcon#flushed, iclass 19, count 0 2006.173.03:11:49.77#ibcon#about to write, iclass 19, count 0 2006.173.03:11:49.77#ibcon#wrote, iclass 19, count 0 2006.173.03:11:49.77#ibcon#about to read 3, iclass 19, count 0 2006.173.03:11:49.80#ibcon#read 3, iclass 19, count 0 2006.173.03:11:49.80#ibcon#about to read 4, iclass 19, count 0 2006.173.03:11:49.80#ibcon#read 4, iclass 19, count 0 2006.173.03:11:49.80#ibcon#about to read 5, iclass 19, count 0 2006.173.03:11:49.80#ibcon#read 5, iclass 19, count 0 2006.173.03:11:49.80#ibcon#about to read 6, iclass 19, count 0 2006.173.03:11:49.80#ibcon#read 6, iclass 19, count 0 2006.173.03:11:49.80#ibcon#end of sib2, iclass 19, count 0 2006.173.03:11:49.80#ibcon#*after write, iclass 19, count 0 2006.173.03:11:49.80#ibcon#*before return 0, iclass 19, count 0 2006.173.03:11:49.80#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.03:11:49.80#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.03:11:49.80#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.03:11:49.80#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.03:11:49.80$vck44/valo=2,534.99 2006.173.03:11:49.80#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.03:11:49.80#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.03:11:49.80#ibcon#ireg 17 cls_cnt 0 2006.173.03:11:49.80#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.03:11:49.80#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.03:11:49.80#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.03:11:49.80#ibcon#enter wrdev, iclass 21, count 0 2006.173.03:11:49.80#ibcon#first serial, iclass 21, count 0 2006.173.03:11:49.80#ibcon#enter sib2, iclass 21, count 0 2006.173.03:11:49.80#ibcon#flushed, iclass 21, count 0 2006.173.03:11:49.80#ibcon#about to write, iclass 21, count 0 2006.173.03:11:49.80#ibcon#wrote, iclass 21, count 0 2006.173.03:11:49.80#ibcon#about to read 3, iclass 21, count 0 2006.173.03:11:49.82#ibcon#read 3, iclass 21, count 0 2006.173.03:11:49.82#ibcon#about to read 4, iclass 21, count 0 2006.173.03:11:49.82#ibcon#read 4, iclass 21, count 0 2006.173.03:11:49.82#ibcon#about to read 5, iclass 21, count 0 2006.173.03:11:49.82#ibcon#read 5, iclass 21, count 0 2006.173.03:11:49.82#ibcon#about to read 6, iclass 21, count 0 2006.173.03:11:49.82#ibcon#read 6, iclass 21, count 0 2006.173.03:11:49.82#ibcon#end of sib2, iclass 21, count 0 2006.173.03:11:49.82#ibcon#*mode == 0, iclass 21, count 0 2006.173.03:11:49.82#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.03:11:49.82#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.03:11:49.82#ibcon#*before write, iclass 21, count 0 2006.173.03:11:49.82#ibcon#enter sib2, iclass 21, count 0 2006.173.03:11:49.82#ibcon#flushed, iclass 21, count 0 2006.173.03:11:49.82#ibcon#about to write, iclass 21, count 0 2006.173.03:11:49.82#ibcon#wrote, iclass 21, count 0 2006.173.03:11:49.82#ibcon#about to read 3, iclass 21, count 0 2006.173.03:11:49.86#ibcon#read 3, iclass 21, count 0 2006.173.03:11:49.86#ibcon#about to read 4, iclass 21, count 0 2006.173.03:11:49.86#ibcon#read 4, iclass 21, count 0 2006.173.03:11:49.86#ibcon#about to read 5, iclass 21, count 0 2006.173.03:11:49.86#ibcon#read 5, iclass 21, count 0 2006.173.03:11:49.86#ibcon#about to read 6, iclass 21, count 0 2006.173.03:11:49.86#ibcon#read 6, iclass 21, count 0 2006.173.03:11:49.86#ibcon#end of sib2, iclass 21, count 0 2006.173.03:11:49.86#ibcon#*after write, iclass 21, count 0 2006.173.03:11:49.86#ibcon#*before return 0, iclass 21, count 0 2006.173.03:11:49.86#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.03:11:49.86#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.03:11:49.86#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.03:11:49.86#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.03:11:49.86$vck44/va=2,6 2006.173.03:11:49.86#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.03:11:49.86#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.03:11:49.86#ibcon#ireg 11 cls_cnt 2 2006.173.03:11:49.86#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.03:11:49.92#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.03:11:49.92#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.03:11:49.92#ibcon#enter wrdev, iclass 23, count 2 2006.173.03:11:49.92#ibcon#first serial, iclass 23, count 2 2006.173.03:11:49.92#ibcon#enter sib2, iclass 23, count 2 2006.173.03:11:49.92#ibcon#flushed, iclass 23, count 2 2006.173.03:11:49.92#ibcon#about to write, iclass 23, count 2 2006.173.03:11:49.92#ibcon#wrote, iclass 23, count 2 2006.173.03:11:49.92#ibcon#about to read 3, iclass 23, count 2 2006.173.03:11:49.94#ibcon#read 3, iclass 23, count 2 2006.173.03:11:49.94#ibcon#about to read 4, iclass 23, count 2 2006.173.03:11:49.94#ibcon#read 4, iclass 23, count 2 2006.173.03:11:49.94#ibcon#about to read 5, iclass 23, count 2 2006.173.03:11:49.94#ibcon#read 5, iclass 23, count 2 2006.173.03:11:49.94#ibcon#about to read 6, iclass 23, count 2 2006.173.03:11:49.94#ibcon#read 6, iclass 23, count 2 2006.173.03:11:49.94#ibcon#end of sib2, iclass 23, count 2 2006.173.03:11:49.94#ibcon#*mode == 0, iclass 23, count 2 2006.173.03:11:49.94#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.03:11:49.94#ibcon#[25=AT02-06\r\n] 2006.173.03:11:49.94#ibcon#*before write, iclass 23, count 2 2006.173.03:11:49.94#ibcon#enter sib2, iclass 23, count 2 2006.173.03:11:49.94#ibcon#flushed, iclass 23, count 2 2006.173.03:11:49.94#ibcon#about to write, iclass 23, count 2 2006.173.03:11:49.94#ibcon#wrote, iclass 23, count 2 2006.173.03:11:49.94#ibcon#about to read 3, iclass 23, count 2 2006.173.03:11:49.97#ibcon#read 3, iclass 23, count 2 2006.173.03:11:49.97#ibcon#about to read 4, iclass 23, count 2 2006.173.03:11:49.97#ibcon#read 4, iclass 23, count 2 2006.173.03:11:49.97#ibcon#about to read 5, iclass 23, count 2 2006.173.03:11:49.97#ibcon#read 5, iclass 23, count 2 2006.173.03:11:49.97#ibcon#about to read 6, iclass 23, count 2 2006.173.03:11:49.97#ibcon#read 6, iclass 23, count 2 2006.173.03:11:49.97#ibcon#end of sib2, iclass 23, count 2 2006.173.03:11:49.97#ibcon#*after write, iclass 23, count 2 2006.173.03:11:49.97#ibcon#*before return 0, iclass 23, count 2 2006.173.03:11:49.97#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.03:11:49.97#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.03:11:49.97#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.03:11:49.97#ibcon#ireg 7 cls_cnt 0 2006.173.03:11:49.97#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.03:11:50.09#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.03:11:50.09#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.03:11:50.09#ibcon#enter wrdev, iclass 23, count 0 2006.173.03:11:50.09#ibcon#first serial, iclass 23, count 0 2006.173.03:11:50.09#ibcon#enter sib2, iclass 23, count 0 2006.173.03:11:50.09#ibcon#flushed, iclass 23, count 0 2006.173.03:11:50.09#ibcon#about to write, iclass 23, count 0 2006.173.03:11:50.09#ibcon#wrote, iclass 23, count 0 2006.173.03:11:50.09#ibcon#about to read 3, iclass 23, count 0 2006.173.03:11:50.11#ibcon#read 3, iclass 23, count 0 2006.173.03:11:50.11#ibcon#about to read 4, iclass 23, count 0 2006.173.03:11:50.11#ibcon#read 4, iclass 23, count 0 2006.173.03:11:50.11#ibcon#about to read 5, iclass 23, count 0 2006.173.03:11:50.11#ibcon#read 5, iclass 23, count 0 2006.173.03:11:50.11#ibcon#about to read 6, iclass 23, count 0 2006.173.03:11:50.11#ibcon#read 6, iclass 23, count 0 2006.173.03:11:50.11#ibcon#end of sib2, iclass 23, count 0 2006.173.03:11:50.11#ibcon#*mode == 0, iclass 23, count 0 2006.173.03:11:50.11#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.03:11:50.11#ibcon#[25=USB\r\n] 2006.173.03:11:50.11#ibcon#*before write, iclass 23, count 0 2006.173.03:11:50.11#ibcon#enter sib2, iclass 23, count 0 2006.173.03:11:50.11#ibcon#flushed, iclass 23, count 0 2006.173.03:11:50.11#ibcon#about to write, iclass 23, count 0 2006.173.03:11:50.11#ibcon#wrote, iclass 23, count 0 2006.173.03:11:50.11#ibcon#about to read 3, iclass 23, count 0 2006.173.03:11:50.14#ibcon#read 3, iclass 23, count 0 2006.173.03:11:50.14#ibcon#about to read 4, iclass 23, count 0 2006.173.03:11:50.14#ibcon#read 4, iclass 23, count 0 2006.173.03:11:50.14#ibcon#about to read 5, iclass 23, count 0 2006.173.03:11:50.14#ibcon#read 5, iclass 23, count 0 2006.173.03:11:50.14#ibcon#about to read 6, iclass 23, count 0 2006.173.03:11:50.14#ibcon#read 6, iclass 23, count 0 2006.173.03:11:50.14#ibcon#end of sib2, iclass 23, count 0 2006.173.03:11:50.14#ibcon#*after write, iclass 23, count 0 2006.173.03:11:50.14#ibcon#*before return 0, iclass 23, count 0 2006.173.03:11:50.14#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.03:11:50.14#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.03:11:50.14#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.03:11:50.14#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.03:11:50.14$vck44/valo=3,564.99 2006.173.03:11:50.14#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.03:11:50.14#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.03:11:50.14#ibcon#ireg 17 cls_cnt 0 2006.173.03:11:50.14#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.03:11:50.14#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.03:11:50.14#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.03:11:50.14#ibcon#enter wrdev, iclass 25, count 0 2006.173.03:11:50.14#ibcon#first serial, iclass 25, count 0 2006.173.03:11:50.14#ibcon#enter sib2, iclass 25, count 0 2006.173.03:11:50.14#ibcon#flushed, iclass 25, count 0 2006.173.03:11:50.14#ibcon#about to write, iclass 25, count 0 2006.173.03:11:50.14#ibcon#wrote, iclass 25, count 0 2006.173.03:11:50.14#ibcon#about to read 3, iclass 25, count 0 2006.173.03:11:50.16#ibcon#read 3, iclass 25, count 0 2006.173.03:11:50.16#ibcon#about to read 4, iclass 25, count 0 2006.173.03:11:50.16#ibcon#read 4, iclass 25, count 0 2006.173.03:11:50.16#ibcon#about to read 5, iclass 25, count 0 2006.173.03:11:50.16#ibcon#read 5, iclass 25, count 0 2006.173.03:11:50.16#ibcon#about to read 6, iclass 25, count 0 2006.173.03:11:50.16#ibcon#read 6, iclass 25, count 0 2006.173.03:11:50.16#ibcon#end of sib2, iclass 25, count 0 2006.173.03:11:50.16#ibcon#*mode == 0, iclass 25, count 0 2006.173.03:11:50.16#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.03:11:50.16#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.03:11:50.16#ibcon#*before write, iclass 25, count 0 2006.173.03:11:50.16#ibcon#enter sib2, iclass 25, count 0 2006.173.03:11:50.16#ibcon#flushed, iclass 25, count 0 2006.173.03:11:50.16#ibcon#about to write, iclass 25, count 0 2006.173.03:11:50.16#ibcon#wrote, iclass 25, count 0 2006.173.03:11:50.16#ibcon#about to read 3, iclass 25, count 0 2006.173.03:11:50.20#ibcon#read 3, iclass 25, count 0 2006.173.03:11:50.20#ibcon#about to read 4, iclass 25, count 0 2006.173.03:11:50.20#ibcon#read 4, iclass 25, count 0 2006.173.03:11:50.20#ibcon#about to read 5, iclass 25, count 0 2006.173.03:11:50.20#ibcon#read 5, iclass 25, count 0 2006.173.03:11:50.20#ibcon#about to read 6, iclass 25, count 0 2006.173.03:11:50.20#ibcon#read 6, iclass 25, count 0 2006.173.03:11:50.20#ibcon#end of sib2, iclass 25, count 0 2006.173.03:11:50.20#ibcon#*after write, iclass 25, count 0 2006.173.03:11:50.20#ibcon#*before return 0, iclass 25, count 0 2006.173.03:11:50.20#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.03:11:50.20#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.03:11:50.20#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.03:11:50.20#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.03:11:50.20$vck44/va=3,5 2006.173.03:11:50.20#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.03:11:50.20#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.03:11:50.20#ibcon#ireg 11 cls_cnt 2 2006.173.03:11:50.20#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.03:11:50.26#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.03:11:50.26#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.03:11:50.26#ibcon#enter wrdev, iclass 27, count 2 2006.173.03:11:50.26#ibcon#first serial, iclass 27, count 2 2006.173.03:11:50.26#ibcon#enter sib2, iclass 27, count 2 2006.173.03:11:50.26#ibcon#flushed, iclass 27, count 2 2006.173.03:11:50.26#ibcon#about to write, iclass 27, count 2 2006.173.03:11:50.26#ibcon#wrote, iclass 27, count 2 2006.173.03:11:50.26#ibcon#about to read 3, iclass 27, count 2 2006.173.03:11:50.28#ibcon#read 3, iclass 27, count 2 2006.173.03:11:50.28#ibcon#about to read 4, iclass 27, count 2 2006.173.03:11:50.28#ibcon#read 4, iclass 27, count 2 2006.173.03:11:50.28#ibcon#about to read 5, iclass 27, count 2 2006.173.03:11:50.28#ibcon#read 5, iclass 27, count 2 2006.173.03:11:50.28#ibcon#about to read 6, iclass 27, count 2 2006.173.03:11:50.28#ibcon#read 6, iclass 27, count 2 2006.173.03:11:50.28#ibcon#end of sib2, iclass 27, count 2 2006.173.03:11:50.28#ibcon#*mode == 0, iclass 27, count 2 2006.173.03:11:50.28#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.03:11:50.28#ibcon#[25=AT03-05\r\n] 2006.173.03:11:50.28#ibcon#*before write, iclass 27, count 2 2006.173.03:11:50.28#ibcon#enter sib2, iclass 27, count 2 2006.173.03:11:50.28#ibcon#flushed, iclass 27, count 2 2006.173.03:11:50.28#ibcon#about to write, iclass 27, count 2 2006.173.03:11:50.28#ibcon#wrote, iclass 27, count 2 2006.173.03:11:50.28#ibcon#about to read 3, iclass 27, count 2 2006.173.03:11:50.31#ibcon#read 3, iclass 27, count 2 2006.173.03:11:50.31#ibcon#about to read 4, iclass 27, count 2 2006.173.03:11:50.31#ibcon#read 4, iclass 27, count 2 2006.173.03:11:50.31#ibcon#about to read 5, iclass 27, count 2 2006.173.03:11:50.31#ibcon#read 5, iclass 27, count 2 2006.173.03:11:50.31#ibcon#about to read 6, iclass 27, count 2 2006.173.03:11:50.31#ibcon#read 6, iclass 27, count 2 2006.173.03:11:50.31#ibcon#end of sib2, iclass 27, count 2 2006.173.03:11:50.31#ibcon#*after write, iclass 27, count 2 2006.173.03:11:50.31#ibcon#*before return 0, iclass 27, count 2 2006.173.03:11:50.31#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.03:11:50.31#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.03:11:50.31#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.03:11:50.31#ibcon#ireg 7 cls_cnt 0 2006.173.03:11:50.31#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.03:11:50.43#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.03:11:50.43#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.03:11:50.43#ibcon#enter wrdev, iclass 27, count 0 2006.173.03:11:50.43#ibcon#first serial, iclass 27, count 0 2006.173.03:11:50.43#ibcon#enter sib2, iclass 27, count 0 2006.173.03:11:50.43#ibcon#flushed, iclass 27, count 0 2006.173.03:11:50.43#ibcon#about to write, iclass 27, count 0 2006.173.03:11:50.43#ibcon#wrote, iclass 27, count 0 2006.173.03:11:50.43#ibcon#about to read 3, iclass 27, count 0 2006.173.03:11:50.45#ibcon#read 3, iclass 27, count 0 2006.173.03:11:50.45#ibcon#about to read 4, iclass 27, count 0 2006.173.03:11:50.45#ibcon#read 4, iclass 27, count 0 2006.173.03:11:50.45#ibcon#about to read 5, iclass 27, count 0 2006.173.03:11:50.45#ibcon#read 5, iclass 27, count 0 2006.173.03:11:50.45#ibcon#about to read 6, iclass 27, count 0 2006.173.03:11:50.45#ibcon#read 6, iclass 27, count 0 2006.173.03:11:50.45#ibcon#end of sib2, iclass 27, count 0 2006.173.03:11:50.45#ibcon#*mode == 0, iclass 27, count 0 2006.173.03:11:50.45#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.03:11:50.45#ibcon#[25=USB\r\n] 2006.173.03:11:50.45#ibcon#*before write, iclass 27, count 0 2006.173.03:11:50.45#ibcon#enter sib2, iclass 27, count 0 2006.173.03:11:50.45#ibcon#flushed, iclass 27, count 0 2006.173.03:11:50.45#ibcon#about to write, iclass 27, count 0 2006.173.03:11:50.45#ibcon#wrote, iclass 27, count 0 2006.173.03:11:50.45#ibcon#about to read 3, iclass 27, count 0 2006.173.03:11:50.48#ibcon#read 3, iclass 27, count 0 2006.173.03:11:50.48#ibcon#about to read 4, iclass 27, count 0 2006.173.03:11:50.48#ibcon#read 4, iclass 27, count 0 2006.173.03:11:50.48#ibcon#about to read 5, iclass 27, count 0 2006.173.03:11:50.48#ibcon#read 5, iclass 27, count 0 2006.173.03:11:50.48#ibcon#about to read 6, iclass 27, count 0 2006.173.03:11:50.48#ibcon#read 6, iclass 27, count 0 2006.173.03:11:50.48#ibcon#end of sib2, iclass 27, count 0 2006.173.03:11:50.48#ibcon#*after write, iclass 27, count 0 2006.173.03:11:50.48#ibcon#*before return 0, iclass 27, count 0 2006.173.03:11:50.48#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.03:11:50.48#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.03:11:50.48#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.03:11:50.48#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.03:11:50.48$vck44/valo=4,624.99 2006.173.03:11:50.48#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.03:11:50.48#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.03:11:50.48#ibcon#ireg 17 cls_cnt 0 2006.173.03:11:50.48#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.03:11:50.48#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.03:11:50.48#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.03:11:50.48#ibcon#enter wrdev, iclass 29, count 0 2006.173.03:11:50.48#ibcon#first serial, iclass 29, count 0 2006.173.03:11:50.48#ibcon#enter sib2, iclass 29, count 0 2006.173.03:11:50.48#ibcon#flushed, iclass 29, count 0 2006.173.03:11:50.48#ibcon#about to write, iclass 29, count 0 2006.173.03:11:50.48#ibcon#wrote, iclass 29, count 0 2006.173.03:11:50.48#ibcon#about to read 3, iclass 29, count 0 2006.173.03:11:50.50#ibcon#read 3, iclass 29, count 0 2006.173.03:11:50.50#ibcon#about to read 4, iclass 29, count 0 2006.173.03:11:50.50#ibcon#read 4, iclass 29, count 0 2006.173.03:11:50.50#ibcon#about to read 5, iclass 29, count 0 2006.173.03:11:50.50#ibcon#read 5, iclass 29, count 0 2006.173.03:11:50.50#ibcon#about to read 6, iclass 29, count 0 2006.173.03:11:50.50#ibcon#read 6, iclass 29, count 0 2006.173.03:11:50.50#ibcon#end of sib2, iclass 29, count 0 2006.173.03:11:50.50#ibcon#*mode == 0, iclass 29, count 0 2006.173.03:11:50.50#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.03:11:50.50#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.03:11:50.50#ibcon#*before write, iclass 29, count 0 2006.173.03:11:50.50#ibcon#enter sib2, iclass 29, count 0 2006.173.03:11:50.50#ibcon#flushed, iclass 29, count 0 2006.173.03:11:50.50#ibcon#about to write, iclass 29, count 0 2006.173.03:11:50.50#ibcon#wrote, iclass 29, count 0 2006.173.03:11:50.50#ibcon#about to read 3, iclass 29, count 0 2006.173.03:11:50.54#ibcon#read 3, iclass 29, count 0 2006.173.03:11:50.54#ibcon#about to read 4, iclass 29, count 0 2006.173.03:11:50.54#ibcon#read 4, iclass 29, count 0 2006.173.03:11:50.54#ibcon#about to read 5, iclass 29, count 0 2006.173.03:11:50.54#ibcon#read 5, iclass 29, count 0 2006.173.03:11:50.54#ibcon#about to read 6, iclass 29, count 0 2006.173.03:11:50.54#ibcon#read 6, iclass 29, count 0 2006.173.03:11:50.54#ibcon#end of sib2, iclass 29, count 0 2006.173.03:11:50.54#ibcon#*after write, iclass 29, count 0 2006.173.03:11:50.54#ibcon#*before return 0, iclass 29, count 0 2006.173.03:11:50.54#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.03:11:50.54#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.03:11:50.54#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.03:11:50.54#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.03:11:50.54$vck44/va=4,6 2006.173.03:11:50.54#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.03:11:50.54#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.03:11:50.54#ibcon#ireg 11 cls_cnt 2 2006.173.03:11:50.54#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.03:11:50.60#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.03:11:50.60#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.03:11:50.60#ibcon#enter wrdev, iclass 31, count 2 2006.173.03:11:50.60#ibcon#first serial, iclass 31, count 2 2006.173.03:11:50.60#ibcon#enter sib2, iclass 31, count 2 2006.173.03:11:50.60#ibcon#flushed, iclass 31, count 2 2006.173.03:11:50.60#ibcon#about to write, iclass 31, count 2 2006.173.03:11:50.60#ibcon#wrote, iclass 31, count 2 2006.173.03:11:50.60#ibcon#about to read 3, iclass 31, count 2 2006.173.03:11:50.62#ibcon#read 3, iclass 31, count 2 2006.173.03:11:50.62#ibcon#about to read 4, iclass 31, count 2 2006.173.03:11:50.62#ibcon#read 4, iclass 31, count 2 2006.173.03:11:50.62#ibcon#about to read 5, iclass 31, count 2 2006.173.03:11:50.62#ibcon#read 5, iclass 31, count 2 2006.173.03:11:50.62#ibcon#about to read 6, iclass 31, count 2 2006.173.03:11:50.62#ibcon#read 6, iclass 31, count 2 2006.173.03:11:50.62#ibcon#end of sib2, iclass 31, count 2 2006.173.03:11:50.62#ibcon#*mode == 0, iclass 31, count 2 2006.173.03:11:50.62#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.03:11:50.62#ibcon#[25=AT04-06\r\n] 2006.173.03:11:50.62#ibcon#*before write, iclass 31, count 2 2006.173.03:11:50.62#ibcon#enter sib2, iclass 31, count 2 2006.173.03:11:50.62#ibcon#flushed, iclass 31, count 2 2006.173.03:11:50.62#ibcon#about to write, iclass 31, count 2 2006.173.03:11:50.62#ibcon#wrote, iclass 31, count 2 2006.173.03:11:50.62#ibcon#about to read 3, iclass 31, count 2 2006.173.03:11:50.65#ibcon#read 3, iclass 31, count 2 2006.173.03:11:50.65#ibcon#about to read 4, iclass 31, count 2 2006.173.03:11:50.65#ibcon#read 4, iclass 31, count 2 2006.173.03:11:50.65#ibcon#about to read 5, iclass 31, count 2 2006.173.03:11:50.65#ibcon#read 5, iclass 31, count 2 2006.173.03:11:50.65#ibcon#about to read 6, iclass 31, count 2 2006.173.03:11:50.65#ibcon#read 6, iclass 31, count 2 2006.173.03:11:50.65#ibcon#end of sib2, iclass 31, count 2 2006.173.03:11:50.65#ibcon#*after write, iclass 31, count 2 2006.173.03:11:50.65#ibcon#*before return 0, iclass 31, count 2 2006.173.03:11:50.65#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.03:11:50.65#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.03:11:50.65#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.03:11:50.65#ibcon#ireg 7 cls_cnt 0 2006.173.03:11:50.65#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.03:11:50.77#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.03:11:50.77#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.03:11:50.77#ibcon#enter wrdev, iclass 31, count 0 2006.173.03:11:50.77#ibcon#first serial, iclass 31, count 0 2006.173.03:11:50.77#ibcon#enter sib2, iclass 31, count 0 2006.173.03:11:50.77#ibcon#flushed, iclass 31, count 0 2006.173.03:11:50.77#ibcon#about to write, iclass 31, count 0 2006.173.03:11:50.77#ibcon#wrote, iclass 31, count 0 2006.173.03:11:50.77#ibcon#about to read 3, iclass 31, count 0 2006.173.03:11:50.79#ibcon#read 3, iclass 31, count 0 2006.173.03:11:50.79#ibcon#about to read 4, iclass 31, count 0 2006.173.03:11:50.79#ibcon#read 4, iclass 31, count 0 2006.173.03:11:50.79#ibcon#about to read 5, iclass 31, count 0 2006.173.03:11:50.79#ibcon#read 5, iclass 31, count 0 2006.173.03:11:50.79#ibcon#about to read 6, iclass 31, count 0 2006.173.03:11:50.79#ibcon#read 6, iclass 31, count 0 2006.173.03:11:50.79#ibcon#end of sib2, iclass 31, count 0 2006.173.03:11:50.79#ibcon#*mode == 0, iclass 31, count 0 2006.173.03:11:50.79#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.03:11:50.79#ibcon#[25=USB\r\n] 2006.173.03:11:50.79#ibcon#*before write, iclass 31, count 0 2006.173.03:11:50.79#ibcon#enter sib2, iclass 31, count 0 2006.173.03:11:50.79#ibcon#flushed, iclass 31, count 0 2006.173.03:11:50.79#ibcon#about to write, iclass 31, count 0 2006.173.03:11:50.79#ibcon#wrote, iclass 31, count 0 2006.173.03:11:50.79#ibcon#about to read 3, iclass 31, count 0 2006.173.03:11:50.82#ibcon#read 3, iclass 31, count 0 2006.173.03:11:50.82#ibcon#about to read 4, iclass 31, count 0 2006.173.03:11:50.82#ibcon#read 4, iclass 31, count 0 2006.173.03:11:50.82#ibcon#about to read 5, iclass 31, count 0 2006.173.03:11:50.82#ibcon#read 5, iclass 31, count 0 2006.173.03:11:50.82#ibcon#about to read 6, iclass 31, count 0 2006.173.03:11:50.82#ibcon#read 6, iclass 31, count 0 2006.173.03:11:50.82#ibcon#end of sib2, iclass 31, count 0 2006.173.03:11:50.82#ibcon#*after write, iclass 31, count 0 2006.173.03:11:50.82#ibcon#*before return 0, iclass 31, count 0 2006.173.03:11:50.82#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.03:11:50.82#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.03:11:50.82#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.03:11:50.82#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.03:11:50.82$vck44/valo=5,734.99 2006.173.03:11:50.82#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.03:11:50.82#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.03:11:50.82#ibcon#ireg 17 cls_cnt 0 2006.173.03:11:50.82#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.03:11:50.82#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.03:11:50.82#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.03:11:50.82#ibcon#enter wrdev, iclass 33, count 0 2006.173.03:11:50.82#ibcon#first serial, iclass 33, count 0 2006.173.03:11:50.82#ibcon#enter sib2, iclass 33, count 0 2006.173.03:11:50.82#ibcon#flushed, iclass 33, count 0 2006.173.03:11:50.82#ibcon#about to write, iclass 33, count 0 2006.173.03:11:50.82#ibcon#wrote, iclass 33, count 0 2006.173.03:11:50.82#ibcon#about to read 3, iclass 33, count 0 2006.173.03:11:50.84#ibcon#read 3, iclass 33, count 0 2006.173.03:11:50.84#ibcon#about to read 4, iclass 33, count 0 2006.173.03:11:50.84#ibcon#read 4, iclass 33, count 0 2006.173.03:11:50.84#ibcon#about to read 5, iclass 33, count 0 2006.173.03:11:50.84#ibcon#read 5, iclass 33, count 0 2006.173.03:11:50.84#ibcon#about to read 6, iclass 33, count 0 2006.173.03:11:50.84#ibcon#read 6, iclass 33, count 0 2006.173.03:11:50.84#ibcon#end of sib2, iclass 33, count 0 2006.173.03:11:50.84#ibcon#*mode == 0, iclass 33, count 0 2006.173.03:11:50.84#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.03:11:50.84#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.03:11:50.84#ibcon#*before write, iclass 33, count 0 2006.173.03:11:50.84#ibcon#enter sib2, iclass 33, count 0 2006.173.03:11:50.84#ibcon#flushed, iclass 33, count 0 2006.173.03:11:50.84#ibcon#about to write, iclass 33, count 0 2006.173.03:11:50.84#ibcon#wrote, iclass 33, count 0 2006.173.03:11:50.84#ibcon#about to read 3, iclass 33, count 0 2006.173.03:11:50.88#ibcon#read 3, iclass 33, count 0 2006.173.03:11:50.88#ibcon#about to read 4, iclass 33, count 0 2006.173.03:11:50.88#ibcon#read 4, iclass 33, count 0 2006.173.03:11:50.88#ibcon#about to read 5, iclass 33, count 0 2006.173.03:11:50.88#ibcon#read 5, iclass 33, count 0 2006.173.03:11:50.88#ibcon#about to read 6, iclass 33, count 0 2006.173.03:11:50.88#ibcon#read 6, iclass 33, count 0 2006.173.03:11:50.88#ibcon#end of sib2, iclass 33, count 0 2006.173.03:11:50.88#ibcon#*after write, iclass 33, count 0 2006.173.03:11:50.88#ibcon#*before return 0, iclass 33, count 0 2006.173.03:11:50.88#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.03:11:50.88#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.03:11:50.88#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.03:11:50.88#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.03:11:50.88$vck44/va=5,4 2006.173.03:11:50.88#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.03:11:50.88#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.03:11:50.88#ibcon#ireg 11 cls_cnt 2 2006.173.03:11:50.88#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.03:11:50.94#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.03:11:50.94#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.03:11:50.94#ibcon#enter wrdev, iclass 35, count 2 2006.173.03:11:50.94#ibcon#first serial, iclass 35, count 2 2006.173.03:11:50.94#ibcon#enter sib2, iclass 35, count 2 2006.173.03:11:50.94#ibcon#flushed, iclass 35, count 2 2006.173.03:11:50.94#ibcon#about to write, iclass 35, count 2 2006.173.03:11:50.94#ibcon#wrote, iclass 35, count 2 2006.173.03:11:50.94#ibcon#about to read 3, iclass 35, count 2 2006.173.03:11:50.96#ibcon#read 3, iclass 35, count 2 2006.173.03:11:50.96#ibcon#about to read 4, iclass 35, count 2 2006.173.03:11:50.96#ibcon#read 4, iclass 35, count 2 2006.173.03:11:50.96#ibcon#about to read 5, iclass 35, count 2 2006.173.03:11:50.96#ibcon#read 5, iclass 35, count 2 2006.173.03:11:50.96#ibcon#about to read 6, iclass 35, count 2 2006.173.03:11:50.96#ibcon#read 6, iclass 35, count 2 2006.173.03:11:50.96#ibcon#end of sib2, iclass 35, count 2 2006.173.03:11:50.96#ibcon#*mode == 0, iclass 35, count 2 2006.173.03:11:50.96#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.03:11:50.96#ibcon#[25=AT05-04\r\n] 2006.173.03:11:50.96#ibcon#*before write, iclass 35, count 2 2006.173.03:11:50.96#ibcon#enter sib2, iclass 35, count 2 2006.173.03:11:50.96#ibcon#flushed, iclass 35, count 2 2006.173.03:11:50.96#ibcon#about to write, iclass 35, count 2 2006.173.03:11:50.96#ibcon#wrote, iclass 35, count 2 2006.173.03:11:50.96#ibcon#about to read 3, iclass 35, count 2 2006.173.03:11:50.99#ibcon#read 3, iclass 35, count 2 2006.173.03:11:50.99#ibcon#about to read 4, iclass 35, count 2 2006.173.03:11:50.99#ibcon#read 4, iclass 35, count 2 2006.173.03:11:50.99#ibcon#about to read 5, iclass 35, count 2 2006.173.03:11:50.99#ibcon#read 5, iclass 35, count 2 2006.173.03:11:50.99#ibcon#about to read 6, iclass 35, count 2 2006.173.03:11:50.99#ibcon#read 6, iclass 35, count 2 2006.173.03:11:50.99#ibcon#end of sib2, iclass 35, count 2 2006.173.03:11:50.99#ibcon#*after write, iclass 35, count 2 2006.173.03:11:50.99#ibcon#*before return 0, iclass 35, count 2 2006.173.03:11:50.99#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.03:11:50.99#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.03:11:50.99#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.03:11:50.99#ibcon#ireg 7 cls_cnt 0 2006.173.03:11:50.99#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.03:11:51.11#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.03:11:51.11#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.03:11:51.11#ibcon#enter wrdev, iclass 35, count 0 2006.173.03:11:51.11#ibcon#first serial, iclass 35, count 0 2006.173.03:11:51.11#ibcon#enter sib2, iclass 35, count 0 2006.173.03:11:51.11#ibcon#flushed, iclass 35, count 0 2006.173.03:11:51.11#ibcon#about to write, iclass 35, count 0 2006.173.03:11:51.11#ibcon#wrote, iclass 35, count 0 2006.173.03:11:51.11#ibcon#about to read 3, iclass 35, count 0 2006.173.03:11:51.13#ibcon#read 3, iclass 35, count 0 2006.173.03:11:51.13#ibcon#about to read 4, iclass 35, count 0 2006.173.03:11:51.13#ibcon#read 4, iclass 35, count 0 2006.173.03:11:51.13#ibcon#about to read 5, iclass 35, count 0 2006.173.03:11:51.13#ibcon#read 5, iclass 35, count 0 2006.173.03:11:51.13#ibcon#about to read 6, iclass 35, count 0 2006.173.03:11:51.13#ibcon#read 6, iclass 35, count 0 2006.173.03:11:51.13#ibcon#end of sib2, iclass 35, count 0 2006.173.03:11:51.13#ibcon#*mode == 0, iclass 35, count 0 2006.173.03:11:51.13#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.03:11:51.13#ibcon#[25=USB\r\n] 2006.173.03:11:51.13#ibcon#*before write, iclass 35, count 0 2006.173.03:11:51.13#ibcon#enter sib2, iclass 35, count 0 2006.173.03:11:51.13#ibcon#flushed, iclass 35, count 0 2006.173.03:11:51.13#ibcon#about to write, iclass 35, count 0 2006.173.03:11:51.13#ibcon#wrote, iclass 35, count 0 2006.173.03:11:51.13#ibcon#about to read 3, iclass 35, count 0 2006.173.03:11:51.16#ibcon#read 3, iclass 35, count 0 2006.173.03:11:51.16#ibcon#about to read 4, iclass 35, count 0 2006.173.03:11:51.16#ibcon#read 4, iclass 35, count 0 2006.173.03:11:51.16#ibcon#about to read 5, iclass 35, count 0 2006.173.03:11:51.16#ibcon#read 5, iclass 35, count 0 2006.173.03:11:51.16#ibcon#about to read 6, iclass 35, count 0 2006.173.03:11:51.16#ibcon#read 6, iclass 35, count 0 2006.173.03:11:51.16#ibcon#end of sib2, iclass 35, count 0 2006.173.03:11:51.16#ibcon#*after write, iclass 35, count 0 2006.173.03:11:51.16#ibcon#*before return 0, iclass 35, count 0 2006.173.03:11:51.16#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.03:11:51.16#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.03:11:51.16#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.03:11:51.16#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.03:11:51.16$vck44/valo=6,814.99 2006.173.03:11:51.16#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.03:11:51.16#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.03:11:51.16#ibcon#ireg 17 cls_cnt 0 2006.173.03:11:51.16#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.03:11:51.16#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.03:11:51.16#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.03:11:51.16#ibcon#enter wrdev, iclass 37, count 0 2006.173.03:11:51.16#ibcon#first serial, iclass 37, count 0 2006.173.03:11:51.16#ibcon#enter sib2, iclass 37, count 0 2006.173.03:11:51.16#ibcon#flushed, iclass 37, count 0 2006.173.03:11:51.16#ibcon#about to write, iclass 37, count 0 2006.173.03:11:51.16#ibcon#wrote, iclass 37, count 0 2006.173.03:11:51.16#ibcon#about to read 3, iclass 37, count 0 2006.173.03:11:51.18#ibcon#read 3, iclass 37, count 0 2006.173.03:11:51.18#ibcon#about to read 4, iclass 37, count 0 2006.173.03:11:51.18#ibcon#read 4, iclass 37, count 0 2006.173.03:11:51.18#ibcon#about to read 5, iclass 37, count 0 2006.173.03:11:51.18#ibcon#read 5, iclass 37, count 0 2006.173.03:11:51.18#ibcon#about to read 6, iclass 37, count 0 2006.173.03:11:51.18#ibcon#read 6, iclass 37, count 0 2006.173.03:11:51.18#ibcon#end of sib2, iclass 37, count 0 2006.173.03:11:51.18#ibcon#*mode == 0, iclass 37, count 0 2006.173.03:11:51.18#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.03:11:51.18#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.03:11:51.18#ibcon#*before write, iclass 37, count 0 2006.173.03:11:51.18#ibcon#enter sib2, iclass 37, count 0 2006.173.03:11:51.18#ibcon#flushed, iclass 37, count 0 2006.173.03:11:51.18#ibcon#about to write, iclass 37, count 0 2006.173.03:11:51.18#ibcon#wrote, iclass 37, count 0 2006.173.03:11:51.18#ibcon#about to read 3, iclass 37, count 0 2006.173.03:11:51.22#ibcon#read 3, iclass 37, count 0 2006.173.03:11:51.22#ibcon#about to read 4, iclass 37, count 0 2006.173.03:11:51.22#ibcon#read 4, iclass 37, count 0 2006.173.03:11:51.22#ibcon#about to read 5, iclass 37, count 0 2006.173.03:11:51.22#ibcon#read 5, iclass 37, count 0 2006.173.03:11:51.22#ibcon#about to read 6, iclass 37, count 0 2006.173.03:11:51.22#ibcon#read 6, iclass 37, count 0 2006.173.03:11:51.22#ibcon#end of sib2, iclass 37, count 0 2006.173.03:11:51.22#ibcon#*after write, iclass 37, count 0 2006.173.03:11:51.22#ibcon#*before return 0, iclass 37, count 0 2006.173.03:11:51.22#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.03:11:51.22#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.03:11:51.22#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.03:11:51.22#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.03:11:51.22$vck44/va=6,3 2006.173.03:11:51.22#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.03:11:51.22#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.03:11:51.22#ibcon#ireg 11 cls_cnt 2 2006.173.03:11:51.22#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.03:11:51.28#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.03:11:51.28#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.03:11:51.28#ibcon#enter wrdev, iclass 39, count 2 2006.173.03:11:51.28#ibcon#first serial, iclass 39, count 2 2006.173.03:11:51.28#ibcon#enter sib2, iclass 39, count 2 2006.173.03:11:51.28#ibcon#flushed, iclass 39, count 2 2006.173.03:11:51.28#ibcon#about to write, iclass 39, count 2 2006.173.03:11:51.28#ibcon#wrote, iclass 39, count 2 2006.173.03:11:51.28#ibcon#about to read 3, iclass 39, count 2 2006.173.03:11:51.30#ibcon#read 3, iclass 39, count 2 2006.173.03:11:51.30#ibcon#about to read 4, iclass 39, count 2 2006.173.03:11:51.30#ibcon#read 4, iclass 39, count 2 2006.173.03:11:51.30#ibcon#about to read 5, iclass 39, count 2 2006.173.03:11:51.30#ibcon#read 5, iclass 39, count 2 2006.173.03:11:51.30#ibcon#about to read 6, iclass 39, count 2 2006.173.03:11:51.30#ibcon#read 6, iclass 39, count 2 2006.173.03:11:51.30#ibcon#end of sib2, iclass 39, count 2 2006.173.03:11:51.30#ibcon#*mode == 0, iclass 39, count 2 2006.173.03:11:51.30#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.03:11:51.30#ibcon#[25=AT06-03\r\n] 2006.173.03:11:51.30#ibcon#*before write, iclass 39, count 2 2006.173.03:11:51.30#ibcon#enter sib2, iclass 39, count 2 2006.173.03:11:51.30#ibcon#flushed, iclass 39, count 2 2006.173.03:11:51.30#ibcon#about to write, iclass 39, count 2 2006.173.03:11:51.30#ibcon#wrote, iclass 39, count 2 2006.173.03:11:51.30#ibcon#about to read 3, iclass 39, count 2 2006.173.03:11:51.33#ibcon#read 3, iclass 39, count 2 2006.173.03:11:51.33#ibcon#about to read 4, iclass 39, count 2 2006.173.03:11:51.33#ibcon#read 4, iclass 39, count 2 2006.173.03:11:51.33#ibcon#about to read 5, iclass 39, count 2 2006.173.03:11:51.33#ibcon#read 5, iclass 39, count 2 2006.173.03:11:51.33#ibcon#about to read 6, iclass 39, count 2 2006.173.03:11:51.33#ibcon#read 6, iclass 39, count 2 2006.173.03:11:51.33#ibcon#end of sib2, iclass 39, count 2 2006.173.03:11:51.33#ibcon#*after write, iclass 39, count 2 2006.173.03:11:51.33#ibcon#*before return 0, iclass 39, count 2 2006.173.03:11:51.33#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.03:11:51.33#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.03:11:51.33#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.03:11:51.33#ibcon#ireg 7 cls_cnt 0 2006.173.03:11:51.33#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.03:11:51.45#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.03:11:51.45#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.03:11:51.45#ibcon#enter wrdev, iclass 39, count 0 2006.173.03:11:51.45#ibcon#first serial, iclass 39, count 0 2006.173.03:11:51.45#ibcon#enter sib2, iclass 39, count 0 2006.173.03:11:51.45#ibcon#flushed, iclass 39, count 0 2006.173.03:11:51.45#ibcon#about to write, iclass 39, count 0 2006.173.03:11:51.45#ibcon#wrote, iclass 39, count 0 2006.173.03:11:51.45#ibcon#about to read 3, iclass 39, count 0 2006.173.03:11:51.47#ibcon#read 3, iclass 39, count 0 2006.173.03:11:51.47#ibcon#about to read 4, iclass 39, count 0 2006.173.03:11:51.47#ibcon#read 4, iclass 39, count 0 2006.173.03:11:51.47#ibcon#about to read 5, iclass 39, count 0 2006.173.03:11:51.47#ibcon#read 5, iclass 39, count 0 2006.173.03:11:51.47#ibcon#about to read 6, iclass 39, count 0 2006.173.03:11:51.47#ibcon#read 6, iclass 39, count 0 2006.173.03:11:51.47#ibcon#end of sib2, iclass 39, count 0 2006.173.03:11:51.47#ibcon#*mode == 0, iclass 39, count 0 2006.173.03:11:51.47#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.03:11:51.47#ibcon#[25=USB\r\n] 2006.173.03:11:51.47#ibcon#*before write, iclass 39, count 0 2006.173.03:11:51.47#ibcon#enter sib2, iclass 39, count 0 2006.173.03:11:51.47#ibcon#flushed, iclass 39, count 0 2006.173.03:11:51.47#ibcon#about to write, iclass 39, count 0 2006.173.03:11:51.47#ibcon#wrote, iclass 39, count 0 2006.173.03:11:51.47#ibcon#about to read 3, iclass 39, count 0 2006.173.03:11:51.50#ibcon#read 3, iclass 39, count 0 2006.173.03:11:51.50#ibcon#about to read 4, iclass 39, count 0 2006.173.03:11:51.50#ibcon#read 4, iclass 39, count 0 2006.173.03:11:51.50#ibcon#about to read 5, iclass 39, count 0 2006.173.03:11:51.50#ibcon#read 5, iclass 39, count 0 2006.173.03:11:51.50#ibcon#about to read 6, iclass 39, count 0 2006.173.03:11:51.50#ibcon#read 6, iclass 39, count 0 2006.173.03:11:51.50#ibcon#end of sib2, iclass 39, count 0 2006.173.03:11:51.50#ibcon#*after write, iclass 39, count 0 2006.173.03:11:51.50#ibcon#*before return 0, iclass 39, count 0 2006.173.03:11:51.50#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.03:11:51.50#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.03:11:51.50#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.03:11:51.50#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.03:11:51.50$vck44/valo=7,864.99 2006.173.03:11:51.50#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.03:11:51.50#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.03:11:51.50#ibcon#ireg 17 cls_cnt 0 2006.173.03:11:51.50#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.03:11:51.50#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.03:11:51.50#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.03:11:51.50#ibcon#enter wrdev, iclass 3, count 0 2006.173.03:11:51.50#ibcon#first serial, iclass 3, count 0 2006.173.03:11:51.50#ibcon#enter sib2, iclass 3, count 0 2006.173.03:11:51.50#ibcon#flushed, iclass 3, count 0 2006.173.03:11:51.50#ibcon#about to write, iclass 3, count 0 2006.173.03:11:51.50#ibcon#wrote, iclass 3, count 0 2006.173.03:11:51.50#ibcon#about to read 3, iclass 3, count 0 2006.173.03:11:51.52#ibcon#read 3, iclass 3, count 0 2006.173.03:11:51.52#ibcon#about to read 4, iclass 3, count 0 2006.173.03:11:51.52#ibcon#read 4, iclass 3, count 0 2006.173.03:11:51.52#ibcon#about to read 5, iclass 3, count 0 2006.173.03:11:51.52#ibcon#read 5, iclass 3, count 0 2006.173.03:11:51.52#ibcon#about to read 6, iclass 3, count 0 2006.173.03:11:51.52#ibcon#read 6, iclass 3, count 0 2006.173.03:11:51.52#ibcon#end of sib2, iclass 3, count 0 2006.173.03:11:51.52#ibcon#*mode == 0, iclass 3, count 0 2006.173.03:11:51.52#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.03:11:51.52#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.03:11:51.52#ibcon#*before write, iclass 3, count 0 2006.173.03:11:51.52#ibcon#enter sib2, iclass 3, count 0 2006.173.03:11:51.52#ibcon#flushed, iclass 3, count 0 2006.173.03:11:51.52#ibcon#about to write, iclass 3, count 0 2006.173.03:11:51.52#ibcon#wrote, iclass 3, count 0 2006.173.03:11:51.52#ibcon#about to read 3, iclass 3, count 0 2006.173.03:11:51.56#ibcon#read 3, iclass 3, count 0 2006.173.03:11:51.56#ibcon#about to read 4, iclass 3, count 0 2006.173.03:11:51.56#ibcon#read 4, iclass 3, count 0 2006.173.03:11:51.56#ibcon#about to read 5, iclass 3, count 0 2006.173.03:11:51.56#ibcon#read 5, iclass 3, count 0 2006.173.03:11:51.56#ibcon#about to read 6, iclass 3, count 0 2006.173.03:11:51.56#ibcon#read 6, iclass 3, count 0 2006.173.03:11:51.56#ibcon#end of sib2, iclass 3, count 0 2006.173.03:11:51.56#ibcon#*after write, iclass 3, count 0 2006.173.03:11:51.56#ibcon#*before return 0, iclass 3, count 0 2006.173.03:11:51.56#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.03:11:51.56#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.03:11:51.56#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.03:11:51.56#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.03:11:51.56$vck44/va=7,4 2006.173.03:11:51.56#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.03:11:51.56#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.03:11:51.56#ibcon#ireg 11 cls_cnt 2 2006.173.03:11:51.56#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.03:11:51.62#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.03:11:51.62#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.03:11:51.62#ibcon#enter wrdev, iclass 5, count 2 2006.173.03:11:51.62#ibcon#first serial, iclass 5, count 2 2006.173.03:11:51.62#ibcon#enter sib2, iclass 5, count 2 2006.173.03:11:51.62#ibcon#flushed, iclass 5, count 2 2006.173.03:11:51.62#ibcon#about to write, iclass 5, count 2 2006.173.03:11:51.62#ibcon#wrote, iclass 5, count 2 2006.173.03:11:51.62#ibcon#about to read 3, iclass 5, count 2 2006.173.03:11:51.64#ibcon#read 3, iclass 5, count 2 2006.173.03:11:51.64#ibcon#about to read 4, iclass 5, count 2 2006.173.03:11:51.64#ibcon#read 4, iclass 5, count 2 2006.173.03:11:51.64#ibcon#about to read 5, iclass 5, count 2 2006.173.03:11:51.64#ibcon#read 5, iclass 5, count 2 2006.173.03:11:51.64#ibcon#about to read 6, iclass 5, count 2 2006.173.03:11:51.64#ibcon#read 6, iclass 5, count 2 2006.173.03:11:51.64#ibcon#end of sib2, iclass 5, count 2 2006.173.03:11:51.64#ibcon#*mode == 0, iclass 5, count 2 2006.173.03:11:51.64#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.03:11:51.64#ibcon#[25=AT07-04\r\n] 2006.173.03:11:51.64#ibcon#*before write, iclass 5, count 2 2006.173.03:11:51.64#ibcon#enter sib2, iclass 5, count 2 2006.173.03:11:51.64#ibcon#flushed, iclass 5, count 2 2006.173.03:11:51.64#ibcon#about to write, iclass 5, count 2 2006.173.03:11:51.64#ibcon#wrote, iclass 5, count 2 2006.173.03:11:51.64#ibcon#about to read 3, iclass 5, count 2 2006.173.03:11:51.67#ibcon#read 3, iclass 5, count 2 2006.173.03:11:51.67#ibcon#about to read 4, iclass 5, count 2 2006.173.03:11:51.67#ibcon#read 4, iclass 5, count 2 2006.173.03:11:51.67#ibcon#about to read 5, iclass 5, count 2 2006.173.03:11:51.67#ibcon#read 5, iclass 5, count 2 2006.173.03:11:51.67#ibcon#about to read 6, iclass 5, count 2 2006.173.03:11:51.67#ibcon#read 6, iclass 5, count 2 2006.173.03:11:51.67#ibcon#end of sib2, iclass 5, count 2 2006.173.03:11:51.67#ibcon#*after write, iclass 5, count 2 2006.173.03:11:51.67#ibcon#*before return 0, iclass 5, count 2 2006.173.03:11:51.67#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.03:11:51.67#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.03:11:51.67#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.03:11:51.67#ibcon#ireg 7 cls_cnt 0 2006.173.03:11:51.67#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.03:11:51.79#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.03:11:51.79#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.03:11:51.79#ibcon#enter wrdev, iclass 5, count 0 2006.173.03:11:51.79#ibcon#first serial, iclass 5, count 0 2006.173.03:11:51.79#ibcon#enter sib2, iclass 5, count 0 2006.173.03:11:51.79#ibcon#flushed, iclass 5, count 0 2006.173.03:11:51.79#ibcon#about to write, iclass 5, count 0 2006.173.03:11:51.79#ibcon#wrote, iclass 5, count 0 2006.173.03:11:51.79#ibcon#about to read 3, iclass 5, count 0 2006.173.03:11:51.81#ibcon#read 3, iclass 5, count 0 2006.173.03:11:51.81#ibcon#about to read 4, iclass 5, count 0 2006.173.03:11:51.81#ibcon#read 4, iclass 5, count 0 2006.173.03:11:51.81#ibcon#about to read 5, iclass 5, count 0 2006.173.03:11:51.81#ibcon#read 5, iclass 5, count 0 2006.173.03:11:51.81#ibcon#about to read 6, iclass 5, count 0 2006.173.03:11:51.81#ibcon#read 6, iclass 5, count 0 2006.173.03:11:51.81#ibcon#end of sib2, iclass 5, count 0 2006.173.03:11:51.81#ibcon#*mode == 0, iclass 5, count 0 2006.173.03:11:51.81#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.03:11:51.81#ibcon#[25=USB\r\n] 2006.173.03:11:51.81#ibcon#*before write, iclass 5, count 0 2006.173.03:11:51.81#ibcon#enter sib2, iclass 5, count 0 2006.173.03:11:51.81#ibcon#flushed, iclass 5, count 0 2006.173.03:11:51.81#ibcon#about to write, iclass 5, count 0 2006.173.03:11:51.81#ibcon#wrote, iclass 5, count 0 2006.173.03:11:51.81#ibcon#about to read 3, iclass 5, count 0 2006.173.03:11:51.84#ibcon#read 3, iclass 5, count 0 2006.173.03:11:51.84#ibcon#about to read 4, iclass 5, count 0 2006.173.03:11:51.84#ibcon#read 4, iclass 5, count 0 2006.173.03:11:51.84#ibcon#about to read 5, iclass 5, count 0 2006.173.03:11:51.84#ibcon#read 5, iclass 5, count 0 2006.173.03:11:51.84#ibcon#about to read 6, iclass 5, count 0 2006.173.03:11:51.84#ibcon#read 6, iclass 5, count 0 2006.173.03:11:51.84#ibcon#end of sib2, iclass 5, count 0 2006.173.03:11:51.84#ibcon#*after write, iclass 5, count 0 2006.173.03:11:51.84#ibcon#*before return 0, iclass 5, count 0 2006.173.03:11:51.84#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.03:11:51.84#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.03:11:51.84#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.03:11:51.84#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.03:11:51.84$vck44/valo=8,884.99 2006.173.03:11:51.84#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.03:11:51.84#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.03:11:51.84#ibcon#ireg 17 cls_cnt 0 2006.173.03:11:51.84#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.03:11:51.84#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.03:11:51.84#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.03:11:51.84#ibcon#enter wrdev, iclass 7, count 0 2006.173.03:11:51.84#ibcon#first serial, iclass 7, count 0 2006.173.03:11:51.84#ibcon#enter sib2, iclass 7, count 0 2006.173.03:11:51.84#ibcon#flushed, iclass 7, count 0 2006.173.03:11:51.84#ibcon#about to write, iclass 7, count 0 2006.173.03:11:51.84#ibcon#wrote, iclass 7, count 0 2006.173.03:11:51.84#ibcon#about to read 3, iclass 7, count 0 2006.173.03:11:51.86#ibcon#read 3, iclass 7, count 0 2006.173.03:11:51.86#ibcon#about to read 4, iclass 7, count 0 2006.173.03:11:51.86#ibcon#read 4, iclass 7, count 0 2006.173.03:11:51.86#ibcon#about to read 5, iclass 7, count 0 2006.173.03:11:51.86#ibcon#read 5, iclass 7, count 0 2006.173.03:11:51.86#ibcon#about to read 6, iclass 7, count 0 2006.173.03:11:51.86#ibcon#read 6, iclass 7, count 0 2006.173.03:11:51.86#ibcon#end of sib2, iclass 7, count 0 2006.173.03:11:51.86#ibcon#*mode == 0, iclass 7, count 0 2006.173.03:11:51.86#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.03:11:51.86#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.03:11:51.86#ibcon#*before write, iclass 7, count 0 2006.173.03:11:51.86#ibcon#enter sib2, iclass 7, count 0 2006.173.03:11:51.86#ibcon#flushed, iclass 7, count 0 2006.173.03:11:51.86#ibcon#about to write, iclass 7, count 0 2006.173.03:11:51.86#ibcon#wrote, iclass 7, count 0 2006.173.03:11:51.86#ibcon#about to read 3, iclass 7, count 0 2006.173.03:11:51.90#ibcon#read 3, iclass 7, count 0 2006.173.03:11:51.90#ibcon#about to read 4, iclass 7, count 0 2006.173.03:11:51.90#ibcon#read 4, iclass 7, count 0 2006.173.03:11:51.90#ibcon#about to read 5, iclass 7, count 0 2006.173.03:11:51.90#ibcon#read 5, iclass 7, count 0 2006.173.03:11:51.90#ibcon#about to read 6, iclass 7, count 0 2006.173.03:11:51.90#ibcon#read 6, iclass 7, count 0 2006.173.03:11:51.90#ibcon#end of sib2, iclass 7, count 0 2006.173.03:11:51.90#ibcon#*after write, iclass 7, count 0 2006.173.03:11:51.90#ibcon#*before return 0, iclass 7, count 0 2006.173.03:11:51.90#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.03:11:51.90#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.03:11:51.90#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.03:11:51.90#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.03:11:51.90$vck44/va=8,4 2006.173.03:11:51.90#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.03:11:51.90#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.03:11:51.90#ibcon#ireg 11 cls_cnt 2 2006.173.03:11:51.90#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.03:11:51.96#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.03:11:51.96#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.03:11:51.96#ibcon#enter wrdev, iclass 11, count 2 2006.173.03:11:51.96#ibcon#first serial, iclass 11, count 2 2006.173.03:11:51.96#ibcon#enter sib2, iclass 11, count 2 2006.173.03:11:51.96#ibcon#flushed, iclass 11, count 2 2006.173.03:11:51.96#ibcon#about to write, iclass 11, count 2 2006.173.03:11:51.96#ibcon#wrote, iclass 11, count 2 2006.173.03:11:51.96#ibcon#about to read 3, iclass 11, count 2 2006.173.03:11:51.98#ibcon#read 3, iclass 11, count 2 2006.173.03:11:51.98#ibcon#about to read 4, iclass 11, count 2 2006.173.03:11:51.98#ibcon#read 4, iclass 11, count 2 2006.173.03:11:51.98#ibcon#about to read 5, iclass 11, count 2 2006.173.03:11:51.98#ibcon#read 5, iclass 11, count 2 2006.173.03:11:51.98#ibcon#about to read 6, iclass 11, count 2 2006.173.03:11:51.98#ibcon#read 6, iclass 11, count 2 2006.173.03:11:51.98#ibcon#end of sib2, iclass 11, count 2 2006.173.03:11:51.98#ibcon#*mode == 0, iclass 11, count 2 2006.173.03:11:51.98#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.03:11:51.98#ibcon#[25=AT08-04\r\n] 2006.173.03:11:51.98#ibcon#*before write, iclass 11, count 2 2006.173.03:11:51.98#ibcon#enter sib2, iclass 11, count 2 2006.173.03:11:51.98#ibcon#flushed, iclass 11, count 2 2006.173.03:11:51.98#ibcon#about to write, iclass 11, count 2 2006.173.03:11:51.98#ibcon#wrote, iclass 11, count 2 2006.173.03:11:51.98#ibcon#about to read 3, iclass 11, count 2 2006.173.03:11:52.01#ibcon#read 3, iclass 11, count 2 2006.173.03:11:52.01#ibcon#about to read 4, iclass 11, count 2 2006.173.03:11:52.01#ibcon#read 4, iclass 11, count 2 2006.173.03:11:52.01#ibcon#about to read 5, iclass 11, count 2 2006.173.03:11:52.01#ibcon#read 5, iclass 11, count 2 2006.173.03:11:52.01#ibcon#about to read 6, iclass 11, count 2 2006.173.03:11:52.01#ibcon#read 6, iclass 11, count 2 2006.173.03:11:52.01#ibcon#end of sib2, iclass 11, count 2 2006.173.03:11:52.01#ibcon#*after write, iclass 11, count 2 2006.173.03:11:52.01#ibcon#*before return 0, iclass 11, count 2 2006.173.03:11:52.01#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.03:11:52.01#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.03:11:52.01#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.03:11:52.01#ibcon#ireg 7 cls_cnt 0 2006.173.03:11:52.01#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.03:11:52.13#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.03:11:52.13#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.03:11:52.13#ibcon#enter wrdev, iclass 11, count 0 2006.173.03:11:52.13#ibcon#first serial, iclass 11, count 0 2006.173.03:11:52.13#ibcon#enter sib2, iclass 11, count 0 2006.173.03:11:52.13#ibcon#flushed, iclass 11, count 0 2006.173.03:11:52.13#ibcon#about to write, iclass 11, count 0 2006.173.03:11:52.13#ibcon#wrote, iclass 11, count 0 2006.173.03:11:52.13#ibcon#about to read 3, iclass 11, count 0 2006.173.03:11:52.15#ibcon#read 3, iclass 11, count 0 2006.173.03:11:52.15#ibcon#about to read 4, iclass 11, count 0 2006.173.03:11:52.15#ibcon#read 4, iclass 11, count 0 2006.173.03:11:52.15#ibcon#about to read 5, iclass 11, count 0 2006.173.03:11:52.15#ibcon#read 5, iclass 11, count 0 2006.173.03:11:52.15#ibcon#about to read 6, iclass 11, count 0 2006.173.03:11:52.15#ibcon#read 6, iclass 11, count 0 2006.173.03:11:52.15#ibcon#end of sib2, iclass 11, count 0 2006.173.03:11:52.15#ibcon#*mode == 0, iclass 11, count 0 2006.173.03:11:52.15#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.03:11:52.15#ibcon#[25=USB\r\n] 2006.173.03:11:52.15#ibcon#*before write, iclass 11, count 0 2006.173.03:11:52.15#ibcon#enter sib2, iclass 11, count 0 2006.173.03:11:52.15#ibcon#flushed, iclass 11, count 0 2006.173.03:11:52.15#ibcon#about to write, iclass 11, count 0 2006.173.03:11:52.15#ibcon#wrote, iclass 11, count 0 2006.173.03:11:52.15#ibcon#about to read 3, iclass 11, count 0 2006.173.03:11:52.18#ibcon#read 3, iclass 11, count 0 2006.173.03:11:52.18#ibcon#about to read 4, iclass 11, count 0 2006.173.03:11:52.18#ibcon#read 4, iclass 11, count 0 2006.173.03:11:52.18#ibcon#about to read 5, iclass 11, count 0 2006.173.03:11:52.18#ibcon#read 5, iclass 11, count 0 2006.173.03:11:52.18#ibcon#about to read 6, iclass 11, count 0 2006.173.03:11:52.18#ibcon#read 6, iclass 11, count 0 2006.173.03:11:52.18#ibcon#end of sib2, iclass 11, count 0 2006.173.03:11:52.18#ibcon#*after write, iclass 11, count 0 2006.173.03:11:52.18#ibcon#*before return 0, iclass 11, count 0 2006.173.03:11:52.18#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.03:11:52.18#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.03:11:52.18#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.03:11:52.18#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.03:11:52.18$vck44/vblo=1,629.99 2006.173.03:11:52.18#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.03:11:52.18#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.03:11:52.18#ibcon#ireg 17 cls_cnt 0 2006.173.03:11:52.18#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.03:11:52.18#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.03:11:52.18#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.03:11:52.18#ibcon#enter wrdev, iclass 13, count 0 2006.173.03:11:52.18#ibcon#first serial, iclass 13, count 0 2006.173.03:11:52.18#ibcon#enter sib2, iclass 13, count 0 2006.173.03:11:52.18#ibcon#flushed, iclass 13, count 0 2006.173.03:11:52.18#ibcon#about to write, iclass 13, count 0 2006.173.03:11:52.18#ibcon#wrote, iclass 13, count 0 2006.173.03:11:52.18#ibcon#about to read 3, iclass 13, count 0 2006.173.03:11:52.20#ibcon#read 3, iclass 13, count 0 2006.173.03:11:52.20#ibcon#about to read 4, iclass 13, count 0 2006.173.03:11:52.20#ibcon#read 4, iclass 13, count 0 2006.173.03:11:52.20#ibcon#about to read 5, iclass 13, count 0 2006.173.03:11:52.20#ibcon#read 5, iclass 13, count 0 2006.173.03:11:52.20#ibcon#about to read 6, iclass 13, count 0 2006.173.03:11:52.20#ibcon#read 6, iclass 13, count 0 2006.173.03:11:52.20#ibcon#end of sib2, iclass 13, count 0 2006.173.03:11:52.20#ibcon#*mode == 0, iclass 13, count 0 2006.173.03:11:52.20#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.03:11:52.20#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.03:11:52.20#ibcon#*before write, iclass 13, count 0 2006.173.03:11:52.20#ibcon#enter sib2, iclass 13, count 0 2006.173.03:11:52.20#ibcon#flushed, iclass 13, count 0 2006.173.03:11:52.20#ibcon#about to write, iclass 13, count 0 2006.173.03:11:52.20#ibcon#wrote, iclass 13, count 0 2006.173.03:11:52.20#ibcon#about to read 3, iclass 13, count 0 2006.173.03:11:52.24#ibcon#read 3, iclass 13, count 0 2006.173.03:11:52.24#ibcon#about to read 4, iclass 13, count 0 2006.173.03:11:52.24#ibcon#read 4, iclass 13, count 0 2006.173.03:11:52.24#ibcon#about to read 5, iclass 13, count 0 2006.173.03:11:52.24#ibcon#read 5, iclass 13, count 0 2006.173.03:11:52.24#ibcon#about to read 6, iclass 13, count 0 2006.173.03:11:52.24#ibcon#read 6, iclass 13, count 0 2006.173.03:11:52.24#ibcon#end of sib2, iclass 13, count 0 2006.173.03:11:52.24#ibcon#*after write, iclass 13, count 0 2006.173.03:11:52.24#ibcon#*before return 0, iclass 13, count 0 2006.173.03:11:52.24#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.03:11:52.24#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.03:11:52.24#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.03:11:52.24#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.03:11:52.24$vck44/vb=1,4 2006.173.03:11:52.24#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.03:11:52.24#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.03:11:52.24#ibcon#ireg 11 cls_cnt 2 2006.173.03:11:52.24#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.03:11:52.24#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.03:11:52.24#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.03:11:52.24#ibcon#enter wrdev, iclass 15, count 2 2006.173.03:11:52.24#ibcon#first serial, iclass 15, count 2 2006.173.03:11:52.24#ibcon#enter sib2, iclass 15, count 2 2006.173.03:11:52.24#ibcon#flushed, iclass 15, count 2 2006.173.03:11:52.24#ibcon#about to write, iclass 15, count 2 2006.173.03:11:52.24#ibcon#wrote, iclass 15, count 2 2006.173.03:11:52.24#ibcon#about to read 3, iclass 15, count 2 2006.173.03:11:52.26#ibcon#read 3, iclass 15, count 2 2006.173.03:11:52.26#ibcon#about to read 4, iclass 15, count 2 2006.173.03:11:52.26#ibcon#read 4, iclass 15, count 2 2006.173.03:11:52.26#ibcon#about to read 5, iclass 15, count 2 2006.173.03:11:52.26#ibcon#read 5, iclass 15, count 2 2006.173.03:11:52.26#ibcon#about to read 6, iclass 15, count 2 2006.173.03:11:52.26#ibcon#read 6, iclass 15, count 2 2006.173.03:11:52.26#ibcon#end of sib2, iclass 15, count 2 2006.173.03:11:52.26#ibcon#*mode == 0, iclass 15, count 2 2006.173.03:11:52.26#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.03:11:52.26#ibcon#[27=AT01-04\r\n] 2006.173.03:11:52.26#ibcon#*before write, iclass 15, count 2 2006.173.03:11:52.26#ibcon#enter sib2, iclass 15, count 2 2006.173.03:11:52.26#ibcon#flushed, iclass 15, count 2 2006.173.03:11:52.26#ibcon#about to write, iclass 15, count 2 2006.173.03:11:52.26#ibcon#wrote, iclass 15, count 2 2006.173.03:11:52.26#ibcon#about to read 3, iclass 15, count 2 2006.173.03:11:52.29#ibcon#read 3, iclass 15, count 2 2006.173.03:11:52.29#ibcon#about to read 4, iclass 15, count 2 2006.173.03:11:52.29#ibcon#read 4, iclass 15, count 2 2006.173.03:11:52.29#ibcon#about to read 5, iclass 15, count 2 2006.173.03:11:52.29#ibcon#read 5, iclass 15, count 2 2006.173.03:11:52.29#ibcon#about to read 6, iclass 15, count 2 2006.173.03:11:52.29#ibcon#read 6, iclass 15, count 2 2006.173.03:11:52.29#ibcon#end of sib2, iclass 15, count 2 2006.173.03:11:52.29#ibcon#*after write, iclass 15, count 2 2006.173.03:11:52.29#ibcon#*before return 0, iclass 15, count 2 2006.173.03:11:52.29#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.03:11:52.29#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.03:11:52.29#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.03:11:52.29#ibcon#ireg 7 cls_cnt 0 2006.173.03:11:52.29#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.03:11:52.41#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.03:11:52.41#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.03:11:52.41#ibcon#enter wrdev, iclass 15, count 0 2006.173.03:11:52.41#ibcon#first serial, iclass 15, count 0 2006.173.03:11:52.41#ibcon#enter sib2, iclass 15, count 0 2006.173.03:11:52.41#ibcon#flushed, iclass 15, count 0 2006.173.03:11:52.41#ibcon#about to write, iclass 15, count 0 2006.173.03:11:52.41#ibcon#wrote, iclass 15, count 0 2006.173.03:11:52.41#ibcon#about to read 3, iclass 15, count 0 2006.173.03:11:52.43#ibcon#read 3, iclass 15, count 0 2006.173.03:11:52.43#ibcon#about to read 4, iclass 15, count 0 2006.173.03:11:52.43#ibcon#read 4, iclass 15, count 0 2006.173.03:11:52.43#ibcon#about to read 5, iclass 15, count 0 2006.173.03:11:52.43#ibcon#read 5, iclass 15, count 0 2006.173.03:11:52.43#ibcon#about to read 6, iclass 15, count 0 2006.173.03:11:52.43#ibcon#read 6, iclass 15, count 0 2006.173.03:11:52.43#ibcon#end of sib2, iclass 15, count 0 2006.173.03:11:52.43#ibcon#*mode == 0, iclass 15, count 0 2006.173.03:11:52.43#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.03:11:52.43#ibcon#[27=USB\r\n] 2006.173.03:11:52.43#ibcon#*before write, iclass 15, count 0 2006.173.03:11:52.43#ibcon#enter sib2, iclass 15, count 0 2006.173.03:11:52.43#ibcon#flushed, iclass 15, count 0 2006.173.03:11:52.43#ibcon#about to write, iclass 15, count 0 2006.173.03:11:52.43#ibcon#wrote, iclass 15, count 0 2006.173.03:11:52.43#ibcon#about to read 3, iclass 15, count 0 2006.173.03:11:52.46#ibcon#read 3, iclass 15, count 0 2006.173.03:11:52.46#ibcon#about to read 4, iclass 15, count 0 2006.173.03:11:52.46#ibcon#read 4, iclass 15, count 0 2006.173.03:11:52.46#ibcon#about to read 5, iclass 15, count 0 2006.173.03:11:52.46#ibcon#read 5, iclass 15, count 0 2006.173.03:11:52.46#ibcon#about to read 6, iclass 15, count 0 2006.173.03:11:52.46#ibcon#read 6, iclass 15, count 0 2006.173.03:11:52.46#ibcon#end of sib2, iclass 15, count 0 2006.173.03:11:52.46#ibcon#*after write, iclass 15, count 0 2006.173.03:11:52.46#ibcon#*before return 0, iclass 15, count 0 2006.173.03:11:52.46#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.03:11:52.46#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.03:11:52.46#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.03:11:52.46#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.03:11:52.46$vck44/vblo=2,634.99 2006.173.03:11:52.46#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.03:11:52.46#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.03:11:52.46#ibcon#ireg 17 cls_cnt 0 2006.173.03:11:52.46#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.03:11:52.46#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.03:11:52.46#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.03:11:52.46#ibcon#enter wrdev, iclass 17, count 0 2006.173.03:11:52.46#ibcon#first serial, iclass 17, count 0 2006.173.03:11:52.46#ibcon#enter sib2, iclass 17, count 0 2006.173.03:11:52.46#ibcon#flushed, iclass 17, count 0 2006.173.03:11:52.46#ibcon#about to write, iclass 17, count 0 2006.173.03:11:52.46#ibcon#wrote, iclass 17, count 0 2006.173.03:11:52.46#ibcon#about to read 3, iclass 17, count 0 2006.173.03:11:52.48#ibcon#read 3, iclass 17, count 0 2006.173.03:11:52.48#ibcon#about to read 4, iclass 17, count 0 2006.173.03:11:52.48#ibcon#read 4, iclass 17, count 0 2006.173.03:11:52.48#ibcon#about to read 5, iclass 17, count 0 2006.173.03:11:52.48#ibcon#read 5, iclass 17, count 0 2006.173.03:11:52.48#ibcon#about to read 6, iclass 17, count 0 2006.173.03:11:52.48#ibcon#read 6, iclass 17, count 0 2006.173.03:11:52.48#ibcon#end of sib2, iclass 17, count 0 2006.173.03:11:52.48#ibcon#*mode == 0, iclass 17, count 0 2006.173.03:11:52.48#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.03:11:52.48#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.03:11:52.48#ibcon#*before write, iclass 17, count 0 2006.173.03:11:52.48#ibcon#enter sib2, iclass 17, count 0 2006.173.03:11:52.48#ibcon#flushed, iclass 17, count 0 2006.173.03:11:52.48#ibcon#about to write, iclass 17, count 0 2006.173.03:11:52.48#ibcon#wrote, iclass 17, count 0 2006.173.03:11:52.48#ibcon#about to read 3, iclass 17, count 0 2006.173.03:11:52.52#ibcon#read 3, iclass 17, count 0 2006.173.03:11:52.52#ibcon#about to read 4, iclass 17, count 0 2006.173.03:11:52.52#ibcon#read 4, iclass 17, count 0 2006.173.03:11:52.52#ibcon#about to read 5, iclass 17, count 0 2006.173.03:11:52.52#ibcon#read 5, iclass 17, count 0 2006.173.03:11:52.52#ibcon#about to read 6, iclass 17, count 0 2006.173.03:11:52.52#ibcon#read 6, iclass 17, count 0 2006.173.03:11:52.52#ibcon#end of sib2, iclass 17, count 0 2006.173.03:11:52.52#ibcon#*after write, iclass 17, count 0 2006.173.03:11:52.52#ibcon#*before return 0, iclass 17, count 0 2006.173.03:11:52.52#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.03:11:52.52#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.03:11:52.52#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.03:11:52.52#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.03:11:52.52$vck44/vb=2,4 2006.173.03:11:52.52#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.03:11:52.52#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.03:11:52.52#ibcon#ireg 11 cls_cnt 2 2006.173.03:11:52.52#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.03:11:52.58#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.03:11:52.58#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.03:11:52.58#ibcon#enter wrdev, iclass 19, count 2 2006.173.03:11:52.58#ibcon#first serial, iclass 19, count 2 2006.173.03:11:52.58#ibcon#enter sib2, iclass 19, count 2 2006.173.03:11:52.58#ibcon#flushed, iclass 19, count 2 2006.173.03:11:52.58#ibcon#about to write, iclass 19, count 2 2006.173.03:11:52.58#ibcon#wrote, iclass 19, count 2 2006.173.03:11:52.58#ibcon#about to read 3, iclass 19, count 2 2006.173.03:11:52.60#ibcon#read 3, iclass 19, count 2 2006.173.03:11:52.60#ibcon#about to read 4, iclass 19, count 2 2006.173.03:11:52.60#ibcon#read 4, iclass 19, count 2 2006.173.03:11:52.60#ibcon#about to read 5, iclass 19, count 2 2006.173.03:11:52.60#ibcon#read 5, iclass 19, count 2 2006.173.03:11:52.60#ibcon#about to read 6, iclass 19, count 2 2006.173.03:11:52.60#ibcon#read 6, iclass 19, count 2 2006.173.03:11:52.60#ibcon#end of sib2, iclass 19, count 2 2006.173.03:11:52.60#ibcon#*mode == 0, iclass 19, count 2 2006.173.03:11:52.60#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.03:11:52.60#ibcon#[27=AT02-04\r\n] 2006.173.03:11:52.60#ibcon#*before write, iclass 19, count 2 2006.173.03:11:52.60#ibcon#enter sib2, iclass 19, count 2 2006.173.03:11:52.60#ibcon#flushed, iclass 19, count 2 2006.173.03:11:52.60#ibcon#about to write, iclass 19, count 2 2006.173.03:11:52.60#ibcon#wrote, iclass 19, count 2 2006.173.03:11:52.60#ibcon#about to read 3, iclass 19, count 2 2006.173.03:11:52.63#ibcon#read 3, iclass 19, count 2 2006.173.03:11:52.63#ibcon#about to read 4, iclass 19, count 2 2006.173.03:11:52.63#ibcon#read 4, iclass 19, count 2 2006.173.03:11:52.63#ibcon#about to read 5, iclass 19, count 2 2006.173.03:11:52.63#ibcon#read 5, iclass 19, count 2 2006.173.03:11:52.63#ibcon#about to read 6, iclass 19, count 2 2006.173.03:11:52.63#ibcon#read 6, iclass 19, count 2 2006.173.03:11:52.63#ibcon#end of sib2, iclass 19, count 2 2006.173.03:11:52.63#ibcon#*after write, iclass 19, count 2 2006.173.03:11:52.63#ibcon#*before return 0, iclass 19, count 2 2006.173.03:11:52.63#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.03:11:52.63#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.03:11:52.63#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.03:11:52.63#ibcon#ireg 7 cls_cnt 0 2006.173.03:11:52.63#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.03:11:52.75#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.03:11:52.75#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.03:11:52.75#ibcon#enter wrdev, iclass 19, count 0 2006.173.03:11:52.75#ibcon#first serial, iclass 19, count 0 2006.173.03:11:52.75#ibcon#enter sib2, iclass 19, count 0 2006.173.03:11:52.75#ibcon#flushed, iclass 19, count 0 2006.173.03:11:52.75#ibcon#about to write, iclass 19, count 0 2006.173.03:11:52.75#ibcon#wrote, iclass 19, count 0 2006.173.03:11:52.75#ibcon#about to read 3, iclass 19, count 0 2006.173.03:11:52.77#ibcon#read 3, iclass 19, count 0 2006.173.03:11:52.77#ibcon#about to read 4, iclass 19, count 0 2006.173.03:11:52.77#ibcon#read 4, iclass 19, count 0 2006.173.03:11:52.77#ibcon#about to read 5, iclass 19, count 0 2006.173.03:11:52.77#ibcon#read 5, iclass 19, count 0 2006.173.03:11:52.77#ibcon#about to read 6, iclass 19, count 0 2006.173.03:11:52.77#ibcon#read 6, iclass 19, count 0 2006.173.03:11:52.77#ibcon#end of sib2, iclass 19, count 0 2006.173.03:11:52.77#ibcon#*mode == 0, iclass 19, count 0 2006.173.03:11:52.77#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.03:11:52.77#ibcon#[27=USB\r\n] 2006.173.03:11:52.77#ibcon#*before write, iclass 19, count 0 2006.173.03:11:52.77#ibcon#enter sib2, iclass 19, count 0 2006.173.03:11:52.77#ibcon#flushed, iclass 19, count 0 2006.173.03:11:52.77#ibcon#about to write, iclass 19, count 0 2006.173.03:11:52.77#ibcon#wrote, iclass 19, count 0 2006.173.03:11:52.77#ibcon#about to read 3, iclass 19, count 0 2006.173.03:11:52.80#ibcon#read 3, iclass 19, count 0 2006.173.03:11:52.80#ibcon#about to read 4, iclass 19, count 0 2006.173.03:11:52.80#ibcon#read 4, iclass 19, count 0 2006.173.03:11:52.80#ibcon#about to read 5, iclass 19, count 0 2006.173.03:11:52.80#ibcon#read 5, iclass 19, count 0 2006.173.03:11:52.80#ibcon#about to read 6, iclass 19, count 0 2006.173.03:11:52.80#ibcon#read 6, iclass 19, count 0 2006.173.03:11:52.80#ibcon#end of sib2, iclass 19, count 0 2006.173.03:11:52.80#ibcon#*after write, iclass 19, count 0 2006.173.03:11:52.80#ibcon#*before return 0, iclass 19, count 0 2006.173.03:11:52.80#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.03:11:52.80#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.03:11:52.80#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.03:11:52.80#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.03:11:52.80$vck44/vblo=3,649.99 2006.173.03:11:52.80#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.03:11:52.80#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.03:11:52.80#ibcon#ireg 17 cls_cnt 0 2006.173.03:11:52.80#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.03:11:52.80#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.03:11:52.80#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.03:11:52.80#ibcon#enter wrdev, iclass 21, count 0 2006.173.03:11:52.80#ibcon#first serial, iclass 21, count 0 2006.173.03:11:52.80#ibcon#enter sib2, iclass 21, count 0 2006.173.03:11:52.80#ibcon#flushed, iclass 21, count 0 2006.173.03:11:52.80#ibcon#about to write, iclass 21, count 0 2006.173.03:11:52.80#ibcon#wrote, iclass 21, count 0 2006.173.03:11:52.80#ibcon#about to read 3, iclass 21, count 0 2006.173.03:11:52.82#ibcon#read 3, iclass 21, count 0 2006.173.03:11:52.82#ibcon#about to read 4, iclass 21, count 0 2006.173.03:11:52.82#ibcon#read 4, iclass 21, count 0 2006.173.03:11:52.82#ibcon#about to read 5, iclass 21, count 0 2006.173.03:11:52.82#ibcon#read 5, iclass 21, count 0 2006.173.03:11:52.82#ibcon#about to read 6, iclass 21, count 0 2006.173.03:11:52.82#ibcon#read 6, iclass 21, count 0 2006.173.03:11:52.82#ibcon#end of sib2, iclass 21, count 0 2006.173.03:11:52.82#ibcon#*mode == 0, iclass 21, count 0 2006.173.03:11:52.82#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.03:11:52.82#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.03:11:52.82#ibcon#*before write, iclass 21, count 0 2006.173.03:11:52.82#ibcon#enter sib2, iclass 21, count 0 2006.173.03:11:52.82#ibcon#flushed, iclass 21, count 0 2006.173.03:11:52.82#ibcon#about to write, iclass 21, count 0 2006.173.03:11:52.82#ibcon#wrote, iclass 21, count 0 2006.173.03:11:52.82#ibcon#about to read 3, iclass 21, count 0 2006.173.03:11:52.86#ibcon#read 3, iclass 21, count 0 2006.173.03:11:52.86#ibcon#about to read 4, iclass 21, count 0 2006.173.03:11:52.86#ibcon#read 4, iclass 21, count 0 2006.173.03:11:52.86#ibcon#about to read 5, iclass 21, count 0 2006.173.03:11:52.86#ibcon#read 5, iclass 21, count 0 2006.173.03:11:52.86#ibcon#about to read 6, iclass 21, count 0 2006.173.03:11:52.86#ibcon#read 6, iclass 21, count 0 2006.173.03:11:52.86#ibcon#end of sib2, iclass 21, count 0 2006.173.03:11:52.86#ibcon#*after write, iclass 21, count 0 2006.173.03:11:52.86#ibcon#*before return 0, iclass 21, count 0 2006.173.03:11:52.86#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.03:11:52.86#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.03:11:52.86#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.03:11:52.86#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.03:11:52.86$vck44/vb=3,4 2006.173.03:11:52.86#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.03:11:52.86#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.03:11:52.86#ibcon#ireg 11 cls_cnt 2 2006.173.03:11:52.86#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.03:11:52.92#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.03:11:52.92#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.03:11:52.92#ibcon#enter wrdev, iclass 23, count 2 2006.173.03:11:52.92#ibcon#first serial, iclass 23, count 2 2006.173.03:11:52.92#ibcon#enter sib2, iclass 23, count 2 2006.173.03:11:52.92#ibcon#flushed, iclass 23, count 2 2006.173.03:11:52.92#ibcon#about to write, iclass 23, count 2 2006.173.03:11:52.92#ibcon#wrote, iclass 23, count 2 2006.173.03:11:52.92#ibcon#about to read 3, iclass 23, count 2 2006.173.03:11:52.94#ibcon#read 3, iclass 23, count 2 2006.173.03:11:52.94#ibcon#about to read 4, iclass 23, count 2 2006.173.03:11:52.94#ibcon#read 4, iclass 23, count 2 2006.173.03:11:52.94#ibcon#about to read 5, iclass 23, count 2 2006.173.03:11:52.94#ibcon#read 5, iclass 23, count 2 2006.173.03:11:52.94#ibcon#about to read 6, iclass 23, count 2 2006.173.03:11:52.94#ibcon#read 6, iclass 23, count 2 2006.173.03:11:52.94#ibcon#end of sib2, iclass 23, count 2 2006.173.03:11:52.94#ibcon#*mode == 0, iclass 23, count 2 2006.173.03:11:52.94#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.03:11:52.94#ibcon#[27=AT03-04\r\n] 2006.173.03:11:52.94#ibcon#*before write, iclass 23, count 2 2006.173.03:11:52.94#ibcon#enter sib2, iclass 23, count 2 2006.173.03:11:52.94#ibcon#flushed, iclass 23, count 2 2006.173.03:11:52.94#ibcon#about to write, iclass 23, count 2 2006.173.03:11:52.94#ibcon#wrote, iclass 23, count 2 2006.173.03:11:52.94#ibcon#about to read 3, iclass 23, count 2 2006.173.03:11:52.97#ibcon#read 3, iclass 23, count 2 2006.173.03:11:52.97#ibcon#about to read 4, iclass 23, count 2 2006.173.03:11:52.97#ibcon#read 4, iclass 23, count 2 2006.173.03:11:52.97#ibcon#about to read 5, iclass 23, count 2 2006.173.03:11:52.97#ibcon#read 5, iclass 23, count 2 2006.173.03:11:52.97#ibcon#about to read 6, iclass 23, count 2 2006.173.03:11:52.97#ibcon#read 6, iclass 23, count 2 2006.173.03:11:52.97#ibcon#end of sib2, iclass 23, count 2 2006.173.03:11:52.97#ibcon#*after write, iclass 23, count 2 2006.173.03:11:52.97#ibcon#*before return 0, iclass 23, count 2 2006.173.03:11:52.97#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.03:11:52.97#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.03:11:52.97#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.03:11:52.97#ibcon#ireg 7 cls_cnt 0 2006.173.03:11:52.97#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.03:11:53.09#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.03:11:53.09#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.03:11:53.09#ibcon#enter wrdev, iclass 23, count 0 2006.173.03:11:53.09#ibcon#first serial, iclass 23, count 0 2006.173.03:11:53.09#ibcon#enter sib2, iclass 23, count 0 2006.173.03:11:53.09#ibcon#flushed, iclass 23, count 0 2006.173.03:11:53.09#ibcon#about to write, iclass 23, count 0 2006.173.03:11:53.09#ibcon#wrote, iclass 23, count 0 2006.173.03:11:53.09#ibcon#about to read 3, iclass 23, count 0 2006.173.03:11:53.11#ibcon#read 3, iclass 23, count 0 2006.173.03:11:53.11#ibcon#about to read 4, iclass 23, count 0 2006.173.03:11:53.11#ibcon#read 4, iclass 23, count 0 2006.173.03:11:53.11#ibcon#about to read 5, iclass 23, count 0 2006.173.03:11:53.11#ibcon#read 5, iclass 23, count 0 2006.173.03:11:53.11#ibcon#about to read 6, iclass 23, count 0 2006.173.03:11:53.11#ibcon#read 6, iclass 23, count 0 2006.173.03:11:53.11#ibcon#end of sib2, iclass 23, count 0 2006.173.03:11:53.11#ibcon#*mode == 0, iclass 23, count 0 2006.173.03:11:53.11#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.03:11:53.11#ibcon#[27=USB\r\n] 2006.173.03:11:53.11#ibcon#*before write, iclass 23, count 0 2006.173.03:11:53.11#ibcon#enter sib2, iclass 23, count 0 2006.173.03:11:53.11#ibcon#flushed, iclass 23, count 0 2006.173.03:11:53.11#ibcon#about to write, iclass 23, count 0 2006.173.03:11:53.11#ibcon#wrote, iclass 23, count 0 2006.173.03:11:53.11#ibcon#about to read 3, iclass 23, count 0 2006.173.03:11:53.14#ibcon#read 3, iclass 23, count 0 2006.173.03:11:53.14#ibcon#about to read 4, iclass 23, count 0 2006.173.03:11:53.14#ibcon#read 4, iclass 23, count 0 2006.173.03:11:53.14#ibcon#about to read 5, iclass 23, count 0 2006.173.03:11:53.14#ibcon#read 5, iclass 23, count 0 2006.173.03:11:53.14#ibcon#about to read 6, iclass 23, count 0 2006.173.03:11:53.14#ibcon#read 6, iclass 23, count 0 2006.173.03:11:53.14#ibcon#end of sib2, iclass 23, count 0 2006.173.03:11:53.14#ibcon#*after write, iclass 23, count 0 2006.173.03:11:53.14#ibcon#*before return 0, iclass 23, count 0 2006.173.03:11:53.14#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.03:11:53.14#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.03:11:53.14#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.03:11:53.14#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.03:11:53.14$vck44/vblo=4,679.99 2006.173.03:11:53.14#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.03:11:53.14#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.03:11:53.14#ibcon#ireg 17 cls_cnt 0 2006.173.03:11:53.14#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.03:11:53.14#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.03:11:53.14#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.03:11:53.14#ibcon#enter wrdev, iclass 25, count 0 2006.173.03:11:53.14#ibcon#first serial, iclass 25, count 0 2006.173.03:11:53.14#ibcon#enter sib2, iclass 25, count 0 2006.173.03:11:53.14#ibcon#flushed, iclass 25, count 0 2006.173.03:11:53.14#ibcon#about to write, iclass 25, count 0 2006.173.03:11:53.14#ibcon#wrote, iclass 25, count 0 2006.173.03:11:53.14#ibcon#about to read 3, iclass 25, count 0 2006.173.03:11:53.16#ibcon#read 3, iclass 25, count 0 2006.173.03:11:53.16#ibcon#about to read 4, iclass 25, count 0 2006.173.03:11:53.16#ibcon#read 4, iclass 25, count 0 2006.173.03:11:53.16#ibcon#about to read 5, iclass 25, count 0 2006.173.03:11:53.16#ibcon#read 5, iclass 25, count 0 2006.173.03:11:53.16#ibcon#about to read 6, iclass 25, count 0 2006.173.03:11:53.16#ibcon#read 6, iclass 25, count 0 2006.173.03:11:53.16#ibcon#end of sib2, iclass 25, count 0 2006.173.03:11:53.16#ibcon#*mode == 0, iclass 25, count 0 2006.173.03:11:53.16#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.03:11:53.16#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.03:11:53.16#ibcon#*before write, iclass 25, count 0 2006.173.03:11:53.16#ibcon#enter sib2, iclass 25, count 0 2006.173.03:11:53.16#ibcon#flushed, iclass 25, count 0 2006.173.03:11:53.16#ibcon#about to write, iclass 25, count 0 2006.173.03:11:53.16#ibcon#wrote, iclass 25, count 0 2006.173.03:11:53.16#ibcon#about to read 3, iclass 25, count 0 2006.173.03:11:53.20#ibcon#read 3, iclass 25, count 0 2006.173.03:11:53.20#ibcon#about to read 4, iclass 25, count 0 2006.173.03:11:53.20#ibcon#read 4, iclass 25, count 0 2006.173.03:11:53.20#ibcon#about to read 5, iclass 25, count 0 2006.173.03:11:53.20#ibcon#read 5, iclass 25, count 0 2006.173.03:11:53.20#ibcon#about to read 6, iclass 25, count 0 2006.173.03:11:53.20#ibcon#read 6, iclass 25, count 0 2006.173.03:11:53.20#ibcon#end of sib2, iclass 25, count 0 2006.173.03:11:53.20#ibcon#*after write, iclass 25, count 0 2006.173.03:11:53.20#ibcon#*before return 0, iclass 25, count 0 2006.173.03:11:53.20#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.03:11:53.20#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.03:11:53.20#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.03:11:53.20#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.03:11:53.20$vck44/vb=4,4 2006.173.03:11:53.20#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.03:11:53.20#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.03:11:53.20#ibcon#ireg 11 cls_cnt 2 2006.173.03:11:53.20#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.03:11:53.26#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.03:11:53.26#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.03:11:53.26#ibcon#enter wrdev, iclass 27, count 2 2006.173.03:11:53.26#ibcon#first serial, iclass 27, count 2 2006.173.03:11:53.26#ibcon#enter sib2, iclass 27, count 2 2006.173.03:11:53.26#ibcon#flushed, iclass 27, count 2 2006.173.03:11:53.26#ibcon#about to write, iclass 27, count 2 2006.173.03:11:53.26#ibcon#wrote, iclass 27, count 2 2006.173.03:11:53.26#ibcon#about to read 3, iclass 27, count 2 2006.173.03:11:53.28#ibcon#read 3, iclass 27, count 2 2006.173.03:11:53.28#ibcon#about to read 4, iclass 27, count 2 2006.173.03:11:53.28#ibcon#read 4, iclass 27, count 2 2006.173.03:11:53.28#ibcon#about to read 5, iclass 27, count 2 2006.173.03:11:53.28#ibcon#read 5, iclass 27, count 2 2006.173.03:11:53.28#ibcon#about to read 6, iclass 27, count 2 2006.173.03:11:53.28#ibcon#read 6, iclass 27, count 2 2006.173.03:11:53.28#ibcon#end of sib2, iclass 27, count 2 2006.173.03:11:53.28#ibcon#*mode == 0, iclass 27, count 2 2006.173.03:11:53.28#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.03:11:53.28#ibcon#[27=AT04-04\r\n] 2006.173.03:11:53.28#ibcon#*before write, iclass 27, count 2 2006.173.03:11:53.28#ibcon#enter sib2, iclass 27, count 2 2006.173.03:11:53.28#ibcon#flushed, iclass 27, count 2 2006.173.03:11:53.28#ibcon#about to write, iclass 27, count 2 2006.173.03:11:53.28#ibcon#wrote, iclass 27, count 2 2006.173.03:11:53.28#ibcon#about to read 3, iclass 27, count 2 2006.173.03:11:53.31#ibcon#read 3, iclass 27, count 2 2006.173.03:11:53.31#ibcon#about to read 4, iclass 27, count 2 2006.173.03:11:53.31#ibcon#read 4, iclass 27, count 2 2006.173.03:11:53.31#ibcon#about to read 5, iclass 27, count 2 2006.173.03:11:53.31#ibcon#read 5, iclass 27, count 2 2006.173.03:11:53.31#ibcon#about to read 6, iclass 27, count 2 2006.173.03:11:53.31#ibcon#read 6, iclass 27, count 2 2006.173.03:11:53.31#ibcon#end of sib2, iclass 27, count 2 2006.173.03:11:53.31#ibcon#*after write, iclass 27, count 2 2006.173.03:11:53.31#ibcon#*before return 0, iclass 27, count 2 2006.173.03:11:53.31#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.03:11:53.31#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.03:11:53.31#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.03:11:53.31#ibcon#ireg 7 cls_cnt 0 2006.173.03:11:53.31#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.03:11:53.43#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.03:11:53.43#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.03:11:53.43#ibcon#enter wrdev, iclass 27, count 0 2006.173.03:11:53.43#ibcon#first serial, iclass 27, count 0 2006.173.03:11:53.43#ibcon#enter sib2, iclass 27, count 0 2006.173.03:11:53.43#ibcon#flushed, iclass 27, count 0 2006.173.03:11:53.43#ibcon#about to write, iclass 27, count 0 2006.173.03:11:53.43#ibcon#wrote, iclass 27, count 0 2006.173.03:11:53.43#ibcon#about to read 3, iclass 27, count 0 2006.173.03:11:53.45#ibcon#read 3, iclass 27, count 0 2006.173.03:11:53.45#ibcon#about to read 4, iclass 27, count 0 2006.173.03:11:53.45#ibcon#read 4, iclass 27, count 0 2006.173.03:11:53.45#ibcon#about to read 5, iclass 27, count 0 2006.173.03:11:53.45#ibcon#read 5, iclass 27, count 0 2006.173.03:11:53.45#ibcon#about to read 6, iclass 27, count 0 2006.173.03:11:53.45#ibcon#read 6, iclass 27, count 0 2006.173.03:11:53.45#ibcon#end of sib2, iclass 27, count 0 2006.173.03:11:53.45#ibcon#*mode == 0, iclass 27, count 0 2006.173.03:11:53.45#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.03:11:53.45#ibcon#[27=USB\r\n] 2006.173.03:11:53.45#ibcon#*before write, iclass 27, count 0 2006.173.03:11:53.45#ibcon#enter sib2, iclass 27, count 0 2006.173.03:11:53.45#ibcon#flushed, iclass 27, count 0 2006.173.03:11:53.45#ibcon#about to write, iclass 27, count 0 2006.173.03:11:53.45#ibcon#wrote, iclass 27, count 0 2006.173.03:11:53.45#ibcon#about to read 3, iclass 27, count 0 2006.173.03:11:53.48#ibcon#read 3, iclass 27, count 0 2006.173.03:11:53.48#ibcon#about to read 4, iclass 27, count 0 2006.173.03:11:53.48#ibcon#read 4, iclass 27, count 0 2006.173.03:11:53.48#ibcon#about to read 5, iclass 27, count 0 2006.173.03:11:53.48#ibcon#read 5, iclass 27, count 0 2006.173.03:11:53.48#ibcon#about to read 6, iclass 27, count 0 2006.173.03:11:53.48#ibcon#read 6, iclass 27, count 0 2006.173.03:11:53.48#ibcon#end of sib2, iclass 27, count 0 2006.173.03:11:53.48#ibcon#*after write, iclass 27, count 0 2006.173.03:11:53.48#ibcon#*before return 0, iclass 27, count 0 2006.173.03:11:53.48#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.03:11:53.48#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.03:11:53.48#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.03:11:53.48#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.03:11:53.48$vck44/vblo=5,709.99 2006.173.03:11:53.48#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.03:11:53.48#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.03:11:53.48#ibcon#ireg 17 cls_cnt 0 2006.173.03:11:53.48#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.03:11:53.48#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.03:11:53.48#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.03:11:53.48#ibcon#enter wrdev, iclass 29, count 0 2006.173.03:11:53.48#ibcon#first serial, iclass 29, count 0 2006.173.03:11:53.48#ibcon#enter sib2, iclass 29, count 0 2006.173.03:11:53.48#ibcon#flushed, iclass 29, count 0 2006.173.03:11:53.48#ibcon#about to write, iclass 29, count 0 2006.173.03:11:53.48#ibcon#wrote, iclass 29, count 0 2006.173.03:11:53.48#ibcon#about to read 3, iclass 29, count 0 2006.173.03:11:53.50#ibcon#read 3, iclass 29, count 0 2006.173.03:11:53.50#ibcon#about to read 4, iclass 29, count 0 2006.173.03:11:53.50#ibcon#read 4, iclass 29, count 0 2006.173.03:11:53.50#ibcon#about to read 5, iclass 29, count 0 2006.173.03:11:53.50#ibcon#read 5, iclass 29, count 0 2006.173.03:11:53.50#ibcon#about to read 6, iclass 29, count 0 2006.173.03:11:53.50#ibcon#read 6, iclass 29, count 0 2006.173.03:11:53.50#ibcon#end of sib2, iclass 29, count 0 2006.173.03:11:53.50#ibcon#*mode == 0, iclass 29, count 0 2006.173.03:11:53.50#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.03:11:53.50#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.03:11:53.50#ibcon#*before write, iclass 29, count 0 2006.173.03:11:53.50#ibcon#enter sib2, iclass 29, count 0 2006.173.03:11:53.50#ibcon#flushed, iclass 29, count 0 2006.173.03:11:53.50#ibcon#about to write, iclass 29, count 0 2006.173.03:11:53.50#ibcon#wrote, iclass 29, count 0 2006.173.03:11:53.50#ibcon#about to read 3, iclass 29, count 0 2006.173.03:11:53.54#ibcon#read 3, iclass 29, count 0 2006.173.03:11:53.54#ibcon#about to read 4, iclass 29, count 0 2006.173.03:11:53.54#ibcon#read 4, iclass 29, count 0 2006.173.03:11:53.54#ibcon#about to read 5, iclass 29, count 0 2006.173.03:11:53.54#ibcon#read 5, iclass 29, count 0 2006.173.03:11:53.54#ibcon#about to read 6, iclass 29, count 0 2006.173.03:11:53.54#ibcon#read 6, iclass 29, count 0 2006.173.03:11:53.54#ibcon#end of sib2, iclass 29, count 0 2006.173.03:11:53.54#ibcon#*after write, iclass 29, count 0 2006.173.03:11:53.54#ibcon#*before return 0, iclass 29, count 0 2006.173.03:11:53.54#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.03:11:53.54#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.03:11:53.54#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.03:11:53.54#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.03:11:53.54$vck44/vb=5,4 2006.173.03:11:53.54#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.03:11:53.54#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.03:11:53.54#ibcon#ireg 11 cls_cnt 2 2006.173.03:11:53.54#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.03:11:53.60#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.03:11:53.60#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.03:11:53.60#ibcon#enter wrdev, iclass 31, count 2 2006.173.03:11:53.60#ibcon#first serial, iclass 31, count 2 2006.173.03:11:53.60#ibcon#enter sib2, iclass 31, count 2 2006.173.03:11:53.60#ibcon#flushed, iclass 31, count 2 2006.173.03:11:53.60#ibcon#about to write, iclass 31, count 2 2006.173.03:11:53.60#ibcon#wrote, iclass 31, count 2 2006.173.03:11:53.60#ibcon#about to read 3, iclass 31, count 2 2006.173.03:11:53.62#ibcon#read 3, iclass 31, count 2 2006.173.03:11:53.62#ibcon#about to read 4, iclass 31, count 2 2006.173.03:11:53.62#ibcon#read 4, iclass 31, count 2 2006.173.03:11:53.62#ibcon#about to read 5, iclass 31, count 2 2006.173.03:11:53.62#ibcon#read 5, iclass 31, count 2 2006.173.03:11:53.62#ibcon#about to read 6, iclass 31, count 2 2006.173.03:11:53.62#ibcon#read 6, iclass 31, count 2 2006.173.03:11:53.62#ibcon#end of sib2, iclass 31, count 2 2006.173.03:11:53.62#ibcon#*mode == 0, iclass 31, count 2 2006.173.03:11:53.62#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.03:11:53.62#ibcon#[27=AT05-04\r\n] 2006.173.03:11:53.62#ibcon#*before write, iclass 31, count 2 2006.173.03:11:53.62#ibcon#enter sib2, iclass 31, count 2 2006.173.03:11:53.62#ibcon#flushed, iclass 31, count 2 2006.173.03:11:53.62#ibcon#about to write, iclass 31, count 2 2006.173.03:11:53.62#ibcon#wrote, iclass 31, count 2 2006.173.03:11:53.62#ibcon#about to read 3, iclass 31, count 2 2006.173.03:11:53.65#ibcon#read 3, iclass 31, count 2 2006.173.03:11:53.65#ibcon#about to read 4, iclass 31, count 2 2006.173.03:11:53.65#ibcon#read 4, iclass 31, count 2 2006.173.03:11:53.65#ibcon#about to read 5, iclass 31, count 2 2006.173.03:11:53.65#ibcon#read 5, iclass 31, count 2 2006.173.03:11:53.65#ibcon#about to read 6, iclass 31, count 2 2006.173.03:11:53.65#ibcon#read 6, iclass 31, count 2 2006.173.03:11:53.65#ibcon#end of sib2, iclass 31, count 2 2006.173.03:11:53.65#ibcon#*after write, iclass 31, count 2 2006.173.03:11:53.65#ibcon#*before return 0, iclass 31, count 2 2006.173.03:11:53.65#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.03:11:53.65#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.03:11:53.65#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.03:11:53.65#ibcon#ireg 7 cls_cnt 0 2006.173.03:11:53.65#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.03:11:53.77#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.03:11:53.77#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.03:11:53.77#ibcon#enter wrdev, iclass 31, count 0 2006.173.03:11:53.77#ibcon#first serial, iclass 31, count 0 2006.173.03:11:53.77#ibcon#enter sib2, iclass 31, count 0 2006.173.03:11:53.77#ibcon#flushed, iclass 31, count 0 2006.173.03:11:53.77#ibcon#about to write, iclass 31, count 0 2006.173.03:11:53.77#ibcon#wrote, iclass 31, count 0 2006.173.03:11:53.77#ibcon#about to read 3, iclass 31, count 0 2006.173.03:11:53.79#ibcon#read 3, iclass 31, count 0 2006.173.03:11:53.79#ibcon#about to read 4, iclass 31, count 0 2006.173.03:11:53.79#ibcon#read 4, iclass 31, count 0 2006.173.03:11:53.79#ibcon#about to read 5, iclass 31, count 0 2006.173.03:11:53.79#ibcon#read 5, iclass 31, count 0 2006.173.03:11:53.79#ibcon#about to read 6, iclass 31, count 0 2006.173.03:11:53.79#ibcon#read 6, iclass 31, count 0 2006.173.03:11:53.79#ibcon#end of sib2, iclass 31, count 0 2006.173.03:11:53.79#ibcon#*mode == 0, iclass 31, count 0 2006.173.03:11:53.79#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.03:11:53.79#ibcon#[27=USB\r\n] 2006.173.03:11:53.79#ibcon#*before write, iclass 31, count 0 2006.173.03:11:53.79#ibcon#enter sib2, iclass 31, count 0 2006.173.03:11:53.79#ibcon#flushed, iclass 31, count 0 2006.173.03:11:53.79#ibcon#about to write, iclass 31, count 0 2006.173.03:11:53.79#ibcon#wrote, iclass 31, count 0 2006.173.03:11:53.79#ibcon#about to read 3, iclass 31, count 0 2006.173.03:11:53.82#ibcon#read 3, iclass 31, count 0 2006.173.03:11:53.82#ibcon#about to read 4, iclass 31, count 0 2006.173.03:11:53.82#ibcon#read 4, iclass 31, count 0 2006.173.03:11:53.82#ibcon#about to read 5, iclass 31, count 0 2006.173.03:11:53.82#ibcon#read 5, iclass 31, count 0 2006.173.03:11:53.82#ibcon#about to read 6, iclass 31, count 0 2006.173.03:11:53.82#ibcon#read 6, iclass 31, count 0 2006.173.03:11:53.82#ibcon#end of sib2, iclass 31, count 0 2006.173.03:11:53.82#ibcon#*after write, iclass 31, count 0 2006.173.03:11:53.82#ibcon#*before return 0, iclass 31, count 0 2006.173.03:11:53.82#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.03:11:53.82#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.03:11:53.82#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.03:11:53.82#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.03:11:53.82$vck44/vblo=6,719.99 2006.173.03:11:53.82#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.03:11:53.82#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.03:11:53.82#ibcon#ireg 17 cls_cnt 0 2006.173.03:11:53.82#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.03:11:53.82#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.03:11:53.82#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.03:11:53.82#ibcon#enter wrdev, iclass 33, count 0 2006.173.03:11:53.82#ibcon#first serial, iclass 33, count 0 2006.173.03:11:53.82#ibcon#enter sib2, iclass 33, count 0 2006.173.03:11:53.82#ibcon#flushed, iclass 33, count 0 2006.173.03:11:53.82#ibcon#about to write, iclass 33, count 0 2006.173.03:11:53.82#ibcon#wrote, iclass 33, count 0 2006.173.03:11:53.82#ibcon#about to read 3, iclass 33, count 0 2006.173.03:11:53.84#ibcon#read 3, iclass 33, count 0 2006.173.03:11:53.84#ibcon#about to read 4, iclass 33, count 0 2006.173.03:11:53.84#ibcon#read 4, iclass 33, count 0 2006.173.03:11:53.84#ibcon#about to read 5, iclass 33, count 0 2006.173.03:11:53.84#ibcon#read 5, iclass 33, count 0 2006.173.03:11:53.84#ibcon#about to read 6, iclass 33, count 0 2006.173.03:11:53.84#ibcon#read 6, iclass 33, count 0 2006.173.03:11:53.84#ibcon#end of sib2, iclass 33, count 0 2006.173.03:11:53.84#ibcon#*mode == 0, iclass 33, count 0 2006.173.03:11:53.84#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.03:11:53.84#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.03:11:53.84#ibcon#*before write, iclass 33, count 0 2006.173.03:11:53.84#ibcon#enter sib2, iclass 33, count 0 2006.173.03:11:53.84#ibcon#flushed, iclass 33, count 0 2006.173.03:11:53.84#ibcon#about to write, iclass 33, count 0 2006.173.03:11:53.84#ibcon#wrote, iclass 33, count 0 2006.173.03:11:53.84#ibcon#about to read 3, iclass 33, count 0 2006.173.03:11:53.88#ibcon#read 3, iclass 33, count 0 2006.173.03:11:53.88#ibcon#about to read 4, iclass 33, count 0 2006.173.03:11:53.88#ibcon#read 4, iclass 33, count 0 2006.173.03:11:53.88#ibcon#about to read 5, iclass 33, count 0 2006.173.03:11:53.88#ibcon#read 5, iclass 33, count 0 2006.173.03:11:53.88#ibcon#about to read 6, iclass 33, count 0 2006.173.03:11:53.88#ibcon#read 6, iclass 33, count 0 2006.173.03:11:53.88#ibcon#end of sib2, iclass 33, count 0 2006.173.03:11:53.88#ibcon#*after write, iclass 33, count 0 2006.173.03:11:53.88#ibcon#*before return 0, iclass 33, count 0 2006.173.03:11:53.88#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.03:11:53.88#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.03:11:53.88#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.03:11:53.88#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.03:11:53.88$vck44/vb=6,4 2006.173.03:11:53.88#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.03:11:53.88#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.03:11:53.88#ibcon#ireg 11 cls_cnt 2 2006.173.03:11:53.88#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.03:11:53.94#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.03:11:53.94#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.03:11:53.94#ibcon#enter wrdev, iclass 35, count 2 2006.173.03:11:53.94#ibcon#first serial, iclass 35, count 2 2006.173.03:11:53.94#ibcon#enter sib2, iclass 35, count 2 2006.173.03:11:53.94#ibcon#flushed, iclass 35, count 2 2006.173.03:11:53.94#ibcon#about to write, iclass 35, count 2 2006.173.03:11:53.94#ibcon#wrote, iclass 35, count 2 2006.173.03:11:53.94#ibcon#about to read 3, iclass 35, count 2 2006.173.03:11:53.96#ibcon#read 3, iclass 35, count 2 2006.173.03:11:53.96#ibcon#about to read 4, iclass 35, count 2 2006.173.03:11:53.96#ibcon#read 4, iclass 35, count 2 2006.173.03:11:53.96#ibcon#about to read 5, iclass 35, count 2 2006.173.03:11:53.96#ibcon#read 5, iclass 35, count 2 2006.173.03:11:53.96#ibcon#about to read 6, iclass 35, count 2 2006.173.03:11:53.96#ibcon#read 6, iclass 35, count 2 2006.173.03:11:53.96#ibcon#end of sib2, iclass 35, count 2 2006.173.03:11:53.96#ibcon#*mode == 0, iclass 35, count 2 2006.173.03:11:53.96#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.03:11:53.96#ibcon#[27=AT06-04\r\n] 2006.173.03:11:53.96#ibcon#*before write, iclass 35, count 2 2006.173.03:11:53.96#ibcon#enter sib2, iclass 35, count 2 2006.173.03:11:53.96#ibcon#flushed, iclass 35, count 2 2006.173.03:11:53.96#ibcon#about to write, iclass 35, count 2 2006.173.03:11:53.96#ibcon#wrote, iclass 35, count 2 2006.173.03:11:53.96#ibcon#about to read 3, iclass 35, count 2 2006.173.03:11:53.99#ibcon#read 3, iclass 35, count 2 2006.173.03:11:53.99#ibcon#about to read 4, iclass 35, count 2 2006.173.03:11:53.99#ibcon#read 4, iclass 35, count 2 2006.173.03:11:53.99#ibcon#about to read 5, iclass 35, count 2 2006.173.03:11:53.99#ibcon#read 5, iclass 35, count 2 2006.173.03:11:53.99#ibcon#about to read 6, iclass 35, count 2 2006.173.03:11:53.99#ibcon#read 6, iclass 35, count 2 2006.173.03:11:53.99#ibcon#end of sib2, iclass 35, count 2 2006.173.03:11:53.99#ibcon#*after write, iclass 35, count 2 2006.173.03:11:53.99#ibcon#*before return 0, iclass 35, count 2 2006.173.03:11:53.99#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.03:11:53.99#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.03:11:53.99#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.03:11:53.99#ibcon#ireg 7 cls_cnt 0 2006.173.03:11:53.99#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.03:11:54.11#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.03:11:54.11#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.03:11:54.11#ibcon#enter wrdev, iclass 35, count 0 2006.173.03:11:54.11#ibcon#first serial, iclass 35, count 0 2006.173.03:11:54.11#ibcon#enter sib2, iclass 35, count 0 2006.173.03:11:54.11#ibcon#flushed, iclass 35, count 0 2006.173.03:11:54.11#ibcon#about to write, iclass 35, count 0 2006.173.03:11:54.11#ibcon#wrote, iclass 35, count 0 2006.173.03:11:54.11#ibcon#about to read 3, iclass 35, count 0 2006.173.03:11:54.13#ibcon#read 3, iclass 35, count 0 2006.173.03:11:54.13#ibcon#about to read 4, iclass 35, count 0 2006.173.03:11:54.13#ibcon#read 4, iclass 35, count 0 2006.173.03:11:54.13#ibcon#about to read 5, iclass 35, count 0 2006.173.03:11:54.13#ibcon#read 5, iclass 35, count 0 2006.173.03:11:54.13#ibcon#about to read 6, iclass 35, count 0 2006.173.03:11:54.13#ibcon#read 6, iclass 35, count 0 2006.173.03:11:54.13#ibcon#end of sib2, iclass 35, count 0 2006.173.03:11:54.13#ibcon#*mode == 0, iclass 35, count 0 2006.173.03:11:54.13#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.03:11:54.13#ibcon#[27=USB\r\n] 2006.173.03:11:54.13#ibcon#*before write, iclass 35, count 0 2006.173.03:11:54.13#ibcon#enter sib2, iclass 35, count 0 2006.173.03:11:54.13#ibcon#flushed, iclass 35, count 0 2006.173.03:11:54.13#ibcon#about to write, iclass 35, count 0 2006.173.03:11:54.13#ibcon#wrote, iclass 35, count 0 2006.173.03:11:54.13#ibcon#about to read 3, iclass 35, count 0 2006.173.03:11:54.16#ibcon#read 3, iclass 35, count 0 2006.173.03:11:54.16#ibcon#about to read 4, iclass 35, count 0 2006.173.03:11:54.16#ibcon#read 4, iclass 35, count 0 2006.173.03:11:54.16#ibcon#about to read 5, iclass 35, count 0 2006.173.03:11:54.16#ibcon#read 5, iclass 35, count 0 2006.173.03:11:54.16#ibcon#about to read 6, iclass 35, count 0 2006.173.03:11:54.16#ibcon#read 6, iclass 35, count 0 2006.173.03:11:54.16#ibcon#end of sib2, iclass 35, count 0 2006.173.03:11:54.16#ibcon#*after write, iclass 35, count 0 2006.173.03:11:54.16#ibcon#*before return 0, iclass 35, count 0 2006.173.03:11:54.16#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.03:11:54.16#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.03:11:54.16#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.03:11:54.16#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.03:11:54.16$vck44/vblo=7,734.99 2006.173.03:11:54.16#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.03:11:54.16#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.03:11:54.16#ibcon#ireg 17 cls_cnt 0 2006.173.03:11:54.16#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.03:11:54.16#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.03:11:54.16#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.03:11:54.16#ibcon#enter wrdev, iclass 37, count 0 2006.173.03:11:54.16#ibcon#first serial, iclass 37, count 0 2006.173.03:11:54.16#ibcon#enter sib2, iclass 37, count 0 2006.173.03:11:54.16#ibcon#flushed, iclass 37, count 0 2006.173.03:11:54.16#ibcon#about to write, iclass 37, count 0 2006.173.03:11:54.16#ibcon#wrote, iclass 37, count 0 2006.173.03:11:54.16#ibcon#about to read 3, iclass 37, count 0 2006.173.03:11:54.18#ibcon#read 3, iclass 37, count 0 2006.173.03:11:54.18#ibcon#about to read 4, iclass 37, count 0 2006.173.03:11:54.18#ibcon#read 4, iclass 37, count 0 2006.173.03:11:54.18#ibcon#about to read 5, iclass 37, count 0 2006.173.03:11:54.18#ibcon#read 5, iclass 37, count 0 2006.173.03:11:54.18#ibcon#about to read 6, iclass 37, count 0 2006.173.03:11:54.18#ibcon#read 6, iclass 37, count 0 2006.173.03:11:54.18#ibcon#end of sib2, iclass 37, count 0 2006.173.03:11:54.18#ibcon#*mode == 0, iclass 37, count 0 2006.173.03:11:54.18#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.03:11:54.18#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.03:11:54.18#ibcon#*before write, iclass 37, count 0 2006.173.03:11:54.18#ibcon#enter sib2, iclass 37, count 0 2006.173.03:11:54.18#ibcon#flushed, iclass 37, count 0 2006.173.03:11:54.18#ibcon#about to write, iclass 37, count 0 2006.173.03:11:54.18#ibcon#wrote, iclass 37, count 0 2006.173.03:11:54.18#ibcon#about to read 3, iclass 37, count 0 2006.173.03:11:54.22#ibcon#read 3, iclass 37, count 0 2006.173.03:11:54.22#ibcon#about to read 4, iclass 37, count 0 2006.173.03:11:54.22#ibcon#read 4, iclass 37, count 0 2006.173.03:11:54.22#ibcon#about to read 5, iclass 37, count 0 2006.173.03:11:54.22#ibcon#read 5, iclass 37, count 0 2006.173.03:11:54.22#ibcon#about to read 6, iclass 37, count 0 2006.173.03:11:54.22#ibcon#read 6, iclass 37, count 0 2006.173.03:11:54.22#ibcon#end of sib2, iclass 37, count 0 2006.173.03:11:54.22#ibcon#*after write, iclass 37, count 0 2006.173.03:11:54.22#ibcon#*before return 0, iclass 37, count 0 2006.173.03:11:54.22#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.03:11:54.22#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.03:11:54.22#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.03:11:54.22#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.03:11:54.22$vck44/vb=7,4 2006.173.03:11:54.22#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.03:11:54.22#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.03:11:54.22#ibcon#ireg 11 cls_cnt 2 2006.173.03:11:54.22#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.03:11:54.28#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.03:11:54.28#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.03:11:54.28#ibcon#enter wrdev, iclass 39, count 2 2006.173.03:11:54.28#ibcon#first serial, iclass 39, count 2 2006.173.03:11:54.28#ibcon#enter sib2, iclass 39, count 2 2006.173.03:11:54.28#ibcon#flushed, iclass 39, count 2 2006.173.03:11:54.28#ibcon#about to write, iclass 39, count 2 2006.173.03:11:54.28#ibcon#wrote, iclass 39, count 2 2006.173.03:11:54.28#ibcon#about to read 3, iclass 39, count 2 2006.173.03:11:54.30#ibcon#read 3, iclass 39, count 2 2006.173.03:11:54.30#ibcon#about to read 4, iclass 39, count 2 2006.173.03:11:54.30#ibcon#read 4, iclass 39, count 2 2006.173.03:11:54.30#ibcon#about to read 5, iclass 39, count 2 2006.173.03:11:54.30#ibcon#read 5, iclass 39, count 2 2006.173.03:11:54.30#ibcon#about to read 6, iclass 39, count 2 2006.173.03:11:54.30#ibcon#read 6, iclass 39, count 2 2006.173.03:11:54.30#ibcon#end of sib2, iclass 39, count 2 2006.173.03:11:54.30#ibcon#*mode == 0, iclass 39, count 2 2006.173.03:11:54.30#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.03:11:54.30#ibcon#[27=AT07-04\r\n] 2006.173.03:11:54.30#ibcon#*before write, iclass 39, count 2 2006.173.03:11:54.30#ibcon#enter sib2, iclass 39, count 2 2006.173.03:11:54.30#ibcon#flushed, iclass 39, count 2 2006.173.03:11:54.30#ibcon#about to write, iclass 39, count 2 2006.173.03:11:54.30#ibcon#wrote, iclass 39, count 2 2006.173.03:11:54.30#ibcon#about to read 3, iclass 39, count 2 2006.173.03:11:54.33#ibcon#read 3, iclass 39, count 2 2006.173.03:11:54.33#ibcon#about to read 4, iclass 39, count 2 2006.173.03:11:54.33#ibcon#read 4, iclass 39, count 2 2006.173.03:11:54.33#ibcon#about to read 5, iclass 39, count 2 2006.173.03:11:54.33#ibcon#read 5, iclass 39, count 2 2006.173.03:11:54.33#ibcon#about to read 6, iclass 39, count 2 2006.173.03:11:54.33#ibcon#read 6, iclass 39, count 2 2006.173.03:11:54.33#ibcon#end of sib2, iclass 39, count 2 2006.173.03:11:54.33#ibcon#*after write, iclass 39, count 2 2006.173.03:11:54.33#ibcon#*before return 0, iclass 39, count 2 2006.173.03:11:54.33#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.03:11:54.33#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.03:11:54.33#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.03:11:54.33#ibcon#ireg 7 cls_cnt 0 2006.173.03:11:54.33#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.03:11:54.45#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.03:11:54.45#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.03:11:54.45#ibcon#enter wrdev, iclass 39, count 0 2006.173.03:11:54.45#ibcon#first serial, iclass 39, count 0 2006.173.03:11:54.45#ibcon#enter sib2, iclass 39, count 0 2006.173.03:11:54.45#ibcon#flushed, iclass 39, count 0 2006.173.03:11:54.45#ibcon#about to write, iclass 39, count 0 2006.173.03:11:54.45#ibcon#wrote, iclass 39, count 0 2006.173.03:11:54.45#ibcon#about to read 3, iclass 39, count 0 2006.173.03:11:54.47#ibcon#read 3, iclass 39, count 0 2006.173.03:11:54.47#ibcon#about to read 4, iclass 39, count 0 2006.173.03:11:54.47#ibcon#read 4, iclass 39, count 0 2006.173.03:11:54.47#ibcon#about to read 5, iclass 39, count 0 2006.173.03:11:54.47#ibcon#read 5, iclass 39, count 0 2006.173.03:11:54.47#ibcon#about to read 6, iclass 39, count 0 2006.173.03:11:54.47#ibcon#read 6, iclass 39, count 0 2006.173.03:11:54.47#ibcon#end of sib2, iclass 39, count 0 2006.173.03:11:54.47#ibcon#*mode == 0, iclass 39, count 0 2006.173.03:11:54.47#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.03:11:54.47#ibcon#[27=USB\r\n] 2006.173.03:11:54.47#ibcon#*before write, iclass 39, count 0 2006.173.03:11:54.47#ibcon#enter sib2, iclass 39, count 0 2006.173.03:11:54.47#ibcon#flushed, iclass 39, count 0 2006.173.03:11:54.47#ibcon#about to write, iclass 39, count 0 2006.173.03:11:54.47#ibcon#wrote, iclass 39, count 0 2006.173.03:11:54.47#ibcon#about to read 3, iclass 39, count 0 2006.173.03:11:54.50#ibcon#read 3, iclass 39, count 0 2006.173.03:11:54.50#ibcon#about to read 4, iclass 39, count 0 2006.173.03:11:54.50#ibcon#read 4, iclass 39, count 0 2006.173.03:11:54.50#ibcon#about to read 5, iclass 39, count 0 2006.173.03:11:54.50#ibcon#read 5, iclass 39, count 0 2006.173.03:11:54.50#ibcon#about to read 6, iclass 39, count 0 2006.173.03:11:54.50#ibcon#read 6, iclass 39, count 0 2006.173.03:11:54.50#ibcon#end of sib2, iclass 39, count 0 2006.173.03:11:54.50#ibcon#*after write, iclass 39, count 0 2006.173.03:11:54.50#ibcon#*before return 0, iclass 39, count 0 2006.173.03:11:54.50#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.03:11:54.50#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.03:11:54.50#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.03:11:54.50#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.03:11:54.50$vck44/vblo=8,744.99 2006.173.03:11:54.50#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.03:11:54.50#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.03:11:54.50#ibcon#ireg 17 cls_cnt 0 2006.173.03:11:54.50#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.03:11:54.50#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.03:11:54.50#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.03:11:54.50#ibcon#enter wrdev, iclass 3, count 0 2006.173.03:11:54.50#ibcon#first serial, iclass 3, count 0 2006.173.03:11:54.50#ibcon#enter sib2, iclass 3, count 0 2006.173.03:11:54.50#ibcon#flushed, iclass 3, count 0 2006.173.03:11:54.50#ibcon#about to write, iclass 3, count 0 2006.173.03:11:54.50#ibcon#wrote, iclass 3, count 0 2006.173.03:11:54.50#ibcon#about to read 3, iclass 3, count 0 2006.173.03:11:54.52#ibcon#read 3, iclass 3, count 0 2006.173.03:11:54.52#ibcon#about to read 4, iclass 3, count 0 2006.173.03:11:54.52#ibcon#read 4, iclass 3, count 0 2006.173.03:11:54.52#ibcon#about to read 5, iclass 3, count 0 2006.173.03:11:54.52#ibcon#read 5, iclass 3, count 0 2006.173.03:11:54.52#ibcon#about to read 6, iclass 3, count 0 2006.173.03:11:54.52#ibcon#read 6, iclass 3, count 0 2006.173.03:11:54.52#ibcon#end of sib2, iclass 3, count 0 2006.173.03:11:54.52#ibcon#*mode == 0, iclass 3, count 0 2006.173.03:11:54.52#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.03:11:54.52#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.03:11:54.52#ibcon#*before write, iclass 3, count 0 2006.173.03:11:54.52#ibcon#enter sib2, iclass 3, count 0 2006.173.03:11:54.52#ibcon#flushed, iclass 3, count 0 2006.173.03:11:54.52#ibcon#about to write, iclass 3, count 0 2006.173.03:11:54.52#ibcon#wrote, iclass 3, count 0 2006.173.03:11:54.52#ibcon#about to read 3, iclass 3, count 0 2006.173.03:11:54.56#ibcon#read 3, iclass 3, count 0 2006.173.03:11:54.56#ibcon#about to read 4, iclass 3, count 0 2006.173.03:11:54.56#ibcon#read 4, iclass 3, count 0 2006.173.03:11:54.56#ibcon#about to read 5, iclass 3, count 0 2006.173.03:11:54.56#ibcon#read 5, iclass 3, count 0 2006.173.03:11:54.56#ibcon#about to read 6, iclass 3, count 0 2006.173.03:11:54.56#ibcon#read 6, iclass 3, count 0 2006.173.03:11:54.56#ibcon#end of sib2, iclass 3, count 0 2006.173.03:11:54.56#ibcon#*after write, iclass 3, count 0 2006.173.03:11:54.56#ibcon#*before return 0, iclass 3, count 0 2006.173.03:11:54.56#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.03:11:54.56#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.03:11:54.56#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.03:11:54.56#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.03:11:54.56$vck44/vb=8,4 2006.173.03:11:54.56#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.03:11:54.56#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.03:11:54.56#ibcon#ireg 11 cls_cnt 2 2006.173.03:11:54.56#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.03:11:54.62#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.03:11:54.62#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.03:11:54.62#ibcon#enter wrdev, iclass 5, count 2 2006.173.03:11:54.62#ibcon#first serial, iclass 5, count 2 2006.173.03:11:54.62#ibcon#enter sib2, iclass 5, count 2 2006.173.03:11:54.62#ibcon#flushed, iclass 5, count 2 2006.173.03:11:54.62#ibcon#about to write, iclass 5, count 2 2006.173.03:11:54.62#ibcon#wrote, iclass 5, count 2 2006.173.03:11:54.62#ibcon#about to read 3, iclass 5, count 2 2006.173.03:11:54.64#ibcon#read 3, iclass 5, count 2 2006.173.03:11:54.64#ibcon#about to read 4, iclass 5, count 2 2006.173.03:11:54.64#ibcon#read 4, iclass 5, count 2 2006.173.03:11:54.64#ibcon#about to read 5, iclass 5, count 2 2006.173.03:11:54.64#ibcon#read 5, iclass 5, count 2 2006.173.03:11:54.64#ibcon#about to read 6, iclass 5, count 2 2006.173.03:11:54.64#ibcon#read 6, iclass 5, count 2 2006.173.03:11:54.64#ibcon#end of sib2, iclass 5, count 2 2006.173.03:11:54.64#ibcon#*mode == 0, iclass 5, count 2 2006.173.03:11:54.64#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.03:11:54.64#ibcon#[27=AT08-04\r\n] 2006.173.03:11:54.64#ibcon#*before write, iclass 5, count 2 2006.173.03:11:54.64#ibcon#enter sib2, iclass 5, count 2 2006.173.03:11:54.64#ibcon#flushed, iclass 5, count 2 2006.173.03:11:54.64#ibcon#about to write, iclass 5, count 2 2006.173.03:11:54.64#ibcon#wrote, iclass 5, count 2 2006.173.03:11:54.64#ibcon#about to read 3, iclass 5, count 2 2006.173.03:11:54.67#ibcon#read 3, iclass 5, count 2 2006.173.03:11:54.67#ibcon#about to read 4, iclass 5, count 2 2006.173.03:11:54.67#ibcon#read 4, iclass 5, count 2 2006.173.03:11:54.67#ibcon#about to read 5, iclass 5, count 2 2006.173.03:11:54.67#ibcon#read 5, iclass 5, count 2 2006.173.03:11:54.67#ibcon#about to read 6, iclass 5, count 2 2006.173.03:11:54.67#ibcon#read 6, iclass 5, count 2 2006.173.03:11:54.67#ibcon#end of sib2, iclass 5, count 2 2006.173.03:11:54.67#ibcon#*after write, iclass 5, count 2 2006.173.03:11:54.67#ibcon#*before return 0, iclass 5, count 2 2006.173.03:11:54.67#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.03:11:54.67#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.03:11:54.67#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.03:11:54.67#ibcon#ireg 7 cls_cnt 0 2006.173.03:11:54.67#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.03:11:54.79#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.03:11:54.79#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.03:11:54.79#ibcon#enter wrdev, iclass 5, count 0 2006.173.03:11:54.79#ibcon#first serial, iclass 5, count 0 2006.173.03:11:54.79#ibcon#enter sib2, iclass 5, count 0 2006.173.03:11:54.79#ibcon#flushed, iclass 5, count 0 2006.173.03:11:54.79#ibcon#about to write, iclass 5, count 0 2006.173.03:11:54.79#ibcon#wrote, iclass 5, count 0 2006.173.03:11:54.79#ibcon#about to read 3, iclass 5, count 0 2006.173.03:11:54.81#ibcon#read 3, iclass 5, count 0 2006.173.03:11:54.81#ibcon#about to read 4, iclass 5, count 0 2006.173.03:11:54.81#ibcon#read 4, iclass 5, count 0 2006.173.03:11:54.81#ibcon#about to read 5, iclass 5, count 0 2006.173.03:11:54.81#ibcon#read 5, iclass 5, count 0 2006.173.03:11:54.81#ibcon#about to read 6, iclass 5, count 0 2006.173.03:11:54.81#ibcon#read 6, iclass 5, count 0 2006.173.03:11:54.81#ibcon#end of sib2, iclass 5, count 0 2006.173.03:11:54.81#ibcon#*mode == 0, iclass 5, count 0 2006.173.03:11:54.81#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.03:11:54.81#ibcon#[27=USB\r\n] 2006.173.03:11:54.81#ibcon#*before write, iclass 5, count 0 2006.173.03:11:54.81#ibcon#enter sib2, iclass 5, count 0 2006.173.03:11:54.81#ibcon#flushed, iclass 5, count 0 2006.173.03:11:54.81#ibcon#about to write, iclass 5, count 0 2006.173.03:11:54.81#ibcon#wrote, iclass 5, count 0 2006.173.03:11:54.81#ibcon#about to read 3, iclass 5, count 0 2006.173.03:11:54.84#ibcon#read 3, iclass 5, count 0 2006.173.03:11:54.84#ibcon#about to read 4, iclass 5, count 0 2006.173.03:11:54.84#ibcon#read 4, iclass 5, count 0 2006.173.03:11:54.84#ibcon#about to read 5, iclass 5, count 0 2006.173.03:11:54.84#ibcon#read 5, iclass 5, count 0 2006.173.03:11:54.84#ibcon#about to read 6, iclass 5, count 0 2006.173.03:11:54.84#ibcon#read 6, iclass 5, count 0 2006.173.03:11:54.84#ibcon#end of sib2, iclass 5, count 0 2006.173.03:11:54.84#ibcon#*after write, iclass 5, count 0 2006.173.03:11:54.84#ibcon#*before return 0, iclass 5, count 0 2006.173.03:11:54.84#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.03:11:54.84#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.03:11:54.84#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.03:11:54.84#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.03:11:54.84$vck44/vabw=wide 2006.173.03:11:54.84#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.03:11:54.84#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.03:11:54.84#ibcon#ireg 8 cls_cnt 0 2006.173.03:11:54.84#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.03:11:54.84#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.03:11:54.84#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.03:11:54.84#ibcon#enter wrdev, iclass 7, count 0 2006.173.03:11:54.84#ibcon#first serial, iclass 7, count 0 2006.173.03:11:54.84#ibcon#enter sib2, iclass 7, count 0 2006.173.03:11:54.84#ibcon#flushed, iclass 7, count 0 2006.173.03:11:54.84#ibcon#about to write, iclass 7, count 0 2006.173.03:11:54.84#ibcon#wrote, iclass 7, count 0 2006.173.03:11:54.84#ibcon#about to read 3, iclass 7, count 0 2006.173.03:11:54.86#ibcon#read 3, iclass 7, count 0 2006.173.03:11:54.86#ibcon#about to read 4, iclass 7, count 0 2006.173.03:11:54.86#ibcon#read 4, iclass 7, count 0 2006.173.03:11:54.86#ibcon#about to read 5, iclass 7, count 0 2006.173.03:11:54.86#ibcon#read 5, iclass 7, count 0 2006.173.03:11:54.86#ibcon#about to read 6, iclass 7, count 0 2006.173.03:11:54.86#ibcon#read 6, iclass 7, count 0 2006.173.03:11:54.86#ibcon#end of sib2, iclass 7, count 0 2006.173.03:11:54.86#ibcon#*mode == 0, iclass 7, count 0 2006.173.03:11:54.86#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.03:11:54.86#ibcon#[25=BW32\r\n] 2006.173.03:11:54.86#ibcon#*before write, iclass 7, count 0 2006.173.03:11:54.86#ibcon#enter sib2, iclass 7, count 0 2006.173.03:11:54.86#ibcon#flushed, iclass 7, count 0 2006.173.03:11:54.86#ibcon#about to write, iclass 7, count 0 2006.173.03:11:54.86#ibcon#wrote, iclass 7, count 0 2006.173.03:11:54.86#ibcon#about to read 3, iclass 7, count 0 2006.173.03:11:54.89#ibcon#read 3, iclass 7, count 0 2006.173.03:11:54.89#ibcon#about to read 4, iclass 7, count 0 2006.173.03:11:54.89#ibcon#read 4, iclass 7, count 0 2006.173.03:11:54.89#ibcon#about to read 5, iclass 7, count 0 2006.173.03:11:54.89#ibcon#read 5, iclass 7, count 0 2006.173.03:11:54.89#ibcon#about to read 6, iclass 7, count 0 2006.173.03:11:54.89#ibcon#read 6, iclass 7, count 0 2006.173.03:11:54.89#ibcon#end of sib2, iclass 7, count 0 2006.173.03:11:54.89#ibcon#*after write, iclass 7, count 0 2006.173.03:11:54.89#ibcon#*before return 0, iclass 7, count 0 2006.173.03:11:54.89#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.03:11:54.89#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.03:11:54.89#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.03:11:54.89#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.03:11:54.89$vck44/vbbw=wide 2006.173.03:11:54.89#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.03:11:54.89#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.03:11:54.89#ibcon#ireg 8 cls_cnt 0 2006.173.03:11:54.89#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.03:11:54.96#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.03:11:54.96#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.03:11:54.96#ibcon#enter wrdev, iclass 11, count 0 2006.173.03:11:54.96#ibcon#first serial, iclass 11, count 0 2006.173.03:11:54.96#ibcon#enter sib2, iclass 11, count 0 2006.173.03:11:54.96#ibcon#flushed, iclass 11, count 0 2006.173.03:11:54.96#ibcon#about to write, iclass 11, count 0 2006.173.03:11:54.96#ibcon#wrote, iclass 11, count 0 2006.173.03:11:54.96#ibcon#about to read 3, iclass 11, count 0 2006.173.03:11:54.98#ibcon#read 3, iclass 11, count 0 2006.173.03:11:54.98#ibcon#about to read 4, iclass 11, count 0 2006.173.03:11:54.98#ibcon#read 4, iclass 11, count 0 2006.173.03:11:54.98#ibcon#about to read 5, iclass 11, count 0 2006.173.03:11:54.98#ibcon#read 5, iclass 11, count 0 2006.173.03:11:54.98#ibcon#about to read 6, iclass 11, count 0 2006.173.03:11:54.98#ibcon#read 6, iclass 11, count 0 2006.173.03:11:54.98#ibcon#end of sib2, iclass 11, count 0 2006.173.03:11:54.98#ibcon#*mode == 0, iclass 11, count 0 2006.173.03:11:54.98#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.03:11:54.98#ibcon#[27=BW32\r\n] 2006.173.03:11:54.98#ibcon#*before write, iclass 11, count 0 2006.173.03:11:54.98#ibcon#enter sib2, iclass 11, count 0 2006.173.03:11:54.98#ibcon#flushed, iclass 11, count 0 2006.173.03:11:54.98#ibcon#about to write, iclass 11, count 0 2006.173.03:11:54.98#ibcon#wrote, iclass 11, count 0 2006.173.03:11:54.98#ibcon#about to read 3, iclass 11, count 0 2006.173.03:11:55.01#ibcon#read 3, iclass 11, count 0 2006.173.03:11:55.01#ibcon#about to read 4, iclass 11, count 0 2006.173.03:11:55.01#ibcon#read 4, iclass 11, count 0 2006.173.03:11:55.01#ibcon#about to read 5, iclass 11, count 0 2006.173.03:11:55.01#ibcon#read 5, iclass 11, count 0 2006.173.03:11:55.01#ibcon#about to read 6, iclass 11, count 0 2006.173.03:11:55.01#ibcon#read 6, iclass 11, count 0 2006.173.03:11:55.01#ibcon#end of sib2, iclass 11, count 0 2006.173.03:11:55.01#ibcon#*after write, iclass 11, count 0 2006.173.03:11:55.01#ibcon#*before return 0, iclass 11, count 0 2006.173.03:11:55.01#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.03:11:55.01#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.03:11:55.01#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.03:11:55.01#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.03:11:55.01$setupk4/ifdk4 2006.173.03:11:55.01$ifdk4/lo= 2006.173.03:11:55.01$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.03:11:55.01$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.03:11:55.01$ifdk4/patch= 2006.173.03:11:55.01$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.03:11:55.01$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.03:11:55.01$setupk4/!*+20s 2006.173.03:11:57.29#abcon#<5=/14 1.1 2.4 22.28 841006.3\r\n> 2006.173.03:11:57.31#abcon#{5=INTERFACE CLEAR} 2006.173.03:11:57.37#abcon#[5=S1D000X0/0*\r\n] 2006.173.03:12:07.46#abcon#<5=/14 1.1 2.4 22.28 841006.3\r\n> 2006.173.03:12:07.48#abcon#{5=INTERFACE CLEAR} 2006.173.03:12:07.54#abcon#[5=S1D000X0/0*\r\n] 2006.173.03:12:09.52$setupk4/"tpicd 2006.173.03:12:09.52$setupk4/echo=off 2006.173.03:12:09.52$setupk4/xlog=off 2006.173.03:12:09.52:!2006.173.03:16:05 2006.173.03:12:31.14#trakl#Source acquired 2006.173.03:12:33.14#flagr#flagr/antenna,acquired 2006.173.03:16:05.00:preob 2006.173.03:16:05.13/onsource/TRACKING 2006.173.03:16:05.13:!2006.173.03:16:15 2006.173.03:16:15.00:"tape 2006.173.03:16:15.00:"st=record 2006.173.03:16:15.00:data_valid=on 2006.173.03:16:15.00:midob 2006.173.03:16:15.13/onsource/TRACKING 2006.173.03:16:15.13/wx/22.30,1006.2,85 2006.173.03:16:15.32/cable/+6.5123E-03 2006.173.03:16:16.41/va/01,07,usb,yes,36,38 2006.173.03:16:16.41/va/02,06,usb,yes,36,36 2006.173.03:16:16.41/va/03,05,usb,yes,45,47 2006.173.03:16:16.41/va/04,06,usb,yes,36,38 2006.173.03:16:16.41/va/05,04,usb,yes,28,29 2006.173.03:16:16.41/va/06,03,usb,yes,40,40 2006.173.03:16:16.41/va/07,04,usb,yes,32,33 2006.173.03:16:16.41/va/08,04,usb,yes,27,33 2006.173.03:16:16.64/valo/01,524.99,yes,locked 2006.173.03:16:16.64/valo/02,534.99,yes,locked 2006.173.03:16:16.64/valo/03,564.99,yes,locked 2006.173.03:16:16.64/valo/04,624.99,yes,locked 2006.173.03:16:16.64/valo/05,734.99,yes,locked 2006.173.03:16:16.64/valo/06,814.99,yes,locked 2006.173.03:16:16.64/valo/07,864.99,yes,locked 2006.173.03:16:16.64/valo/08,884.99,yes,locked 2006.173.03:16:17.73/vb/01,04,usb,yes,28,26 2006.173.03:16:17.73/vb/02,04,usb,yes,31,31 2006.173.03:16:17.73/vb/03,04,usb,yes,28,31 2006.173.03:16:17.73/vb/04,04,usb,yes,32,31 2006.173.03:16:17.73/vb/05,04,usb,yes,25,27 2006.173.03:16:17.73/vb/06,04,usb,yes,29,25 2006.173.03:16:17.73/vb/07,04,usb,yes,29,29 2006.173.03:16:17.73/vb/08,04,usb,yes,26,30 2006.173.03:16:17.96/vblo/01,629.99,yes,locked 2006.173.03:16:17.96/vblo/02,634.99,yes,locked 2006.173.03:16:17.96/vblo/03,649.99,yes,locked 2006.173.03:16:17.96/vblo/04,679.99,yes,locked 2006.173.03:16:17.96/vblo/05,709.99,yes,locked 2006.173.03:16:17.96/vblo/06,719.99,yes,locked 2006.173.03:16:17.96/vblo/07,734.99,yes,locked 2006.173.03:16:17.96/vblo/08,744.99,yes,locked 2006.173.03:16:18.11/vabw/8 2006.173.03:16:18.26/vbbw/8 2006.173.03:16:18.35/xfe/off,on,15.0 2006.173.03:16:18.72/ifatt/23,28,28,28 2006.173.03:16:19.08/fmout-gps/S +3.89E-07 2006.173.03:16:19.12:!2006.173.03:16:55 2006.173.03:16:55.00:data_valid=off 2006.173.03:16:55.00:"et 2006.173.03:16:55.00:!+3s 2006.173.03:16:58.02:"tape 2006.173.03:16:58.02:postob 2006.173.03:16:58.17/cable/+6.5097E-03 2006.173.03:16:58.17/wx/22.30,1006.2,84 2006.173.03:16:59.08/fmout-gps/S +3.90E-07 2006.173.03:16:59.08:scan_name=173-0317,jd0606,180 2006.173.03:16:59.08:source=3c274,123049.42,122328.0,2000.0,cw 2006.173.03:17:00.13#flagr#flagr/antenna,new-source 2006.173.03:17:00.13:checkk5 2006.173.03:17:00.47/chk_autoobs//k5ts1/ autoobs is running! 2006.173.03:17:00.82/chk_autoobs//k5ts2/ autoobs is running! 2006.173.03:17:01.15/chk_autoobs//k5ts3/ autoobs is running! 2006.173.03:17:01.49/chk_autoobs//k5ts4/ autoobs is running! 2006.173.03:17:01.83/chk_obsdata//k5ts1/T1730316??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.03:17:02.16/chk_obsdata//k5ts2/T1730316??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.03:17:02.50/chk_obsdata//k5ts3/T1730316??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.03:17:02.83/chk_obsdata//k5ts4/T1730316??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.03:17:03.49/k5log//k5ts1_log_newline 2006.173.03:17:04.14/k5log//k5ts2_log_newline 2006.173.03:17:04.80/k5log//k5ts3_log_newline 2006.173.03:17:05.45/k5log//k5ts4_log_newline 2006.173.03:17:05.47/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.03:17:05.47:setupk4=1 2006.173.03:17:05.47$setupk4/echo=on 2006.173.03:17:05.47$setupk4/pcalon 2006.173.03:17:05.47$pcalon/"no phase cal control is implemented here 2006.173.03:17:05.47$setupk4/"tpicd=stop 2006.173.03:17:05.47$setupk4/"rec=synch_on 2006.173.03:17:05.47$setupk4/"rec_mode=128 2006.173.03:17:05.47$setupk4/!* 2006.173.03:17:05.47$setupk4/recpk4 2006.173.03:17:05.47$recpk4/recpatch= 2006.173.03:17:05.48$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.03:17:05.48$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.03:17:05.48$setupk4/vck44 2006.173.03:17:05.48$vck44/valo=1,524.99 2006.173.03:17:05.48#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.03:17:05.48#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.03:17:05.48#ibcon#ireg 17 cls_cnt 0 2006.173.03:17:05.48#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.03:17:05.48#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.03:17:05.48#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.03:17:05.48#ibcon#enter wrdev, iclass 32, count 0 2006.173.03:17:05.48#ibcon#first serial, iclass 32, count 0 2006.173.03:17:05.48#ibcon#enter sib2, iclass 32, count 0 2006.173.03:17:05.48#ibcon#flushed, iclass 32, count 0 2006.173.03:17:05.48#ibcon#about to write, iclass 32, count 0 2006.173.03:17:05.48#ibcon#wrote, iclass 32, count 0 2006.173.03:17:05.48#ibcon#about to read 3, iclass 32, count 0 2006.173.03:17:05.50#ibcon#read 3, iclass 32, count 0 2006.173.03:17:05.50#ibcon#about to read 4, iclass 32, count 0 2006.173.03:17:05.50#ibcon#read 4, iclass 32, count 0 2006.173.03:17:05.50#ibcon#about to read 5, iclass 32, count 0 2006.173.03:17:05.50#ibcon#read 5, iclass 32, count 0 2006.173.03:17:05.50#ibcon#about to read 6, iclass 32, count 0 2006.173.03:17:05.50#ibcon#read 6, iclass 32, count 0 2006.173.03:17:05.50#ibcon#end of sib2, iclass 32, count 0 2006.173.03:17:05.50#ibcon#*mode == 0, iclass 32, count 0 2006.173.03:17:05.50#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.03:17:05.50#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.03:17:05.50#ibcon#*before write, iclass 32, count 0 2006.173.03:17:05.50#ibcon#enter sib2, iclass 32, count 0 2006.173.03:17:05.50#ibcon#flushed, iclass 32, count 0 2006.173.03:17:05.50#ibcon#about to write, iclass 32, count 0 2006.173.03:17:05.50#ibcon#wrote, iclass 32, count 0 2006.173.03:17:05.50#ibcon#about to read 3, iclass 32, count 0 2006.173.03:17:05.55#ibcon#read 3, iclass 32, count 0 2006.173.03:17:05.55#ibcon#about to read 4, iclass 32, count 0 2006.173.03:17:05.55#ibcon#read 4, iclass 32, count 0 2006.173.03:17:05.55#ibcon#about to read 5, iclass 32, count 0 2006.173.03:17:05.55#ibcon#read 5, iclass 32, count 0 2006.173.03:17:05.55#ibcon#about to read 6, iclass 32, count 0 2006.173.03:17:05.55#ibcon#read 6, iclass 32, count 0 2006.173.03:17:05.55#ibcon#end of sib2, iclass 32, count 0 2006.173.03:17:05.55#ibcon#*after write, iclass 32, count 0 2006.173.03:17:05.55#ibcon#*before return 0, iclass 32, count 0 2006.173.03:17:05.55#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.03:17:05.55#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.03:17:05.55#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.03:17:05.55#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.03:17:05.55$vck44/va=1,7 2006.173.03:17:05.55#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.03:17:05.55#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.03:17:05.55#ibcon#ireg 11 cls_cnt 2 2006.173.03:17:05.55#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.03:17:05.55#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.03:17:05.55#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.03:17:05.55#ibcon#enter wrdev, iclass 34, count 2 2006.173.03:17:05.55#ibcon#first serial, iclass 34, count 2 2006.173.03:17:05.55#ibcon#enter sib2, iclass 34, count 2 2006.173.03:17:05.55#ibcon#flushed, iclass 34, count 2 2006.173.03:17:05.55#ibcon#about to write, iclass 34, count 2 2006.173.03:17:05.55#ibcon#wrote, iclass 34, count 2 2006.173.03:17:05.55#ibcon#about to read 3, iclass 34, count 2 2006.173.03:17:05.57#ibcon#read 3, iclass 34, count 2 2006.173.03:17:05.57#ibcon#about to read 4, iclass 34, count 2 2006.173.03:17:05.57#ibcon#read 4, iclass 34, count 2 2006.173.03:17:05.57#ibcon#about to read 5, iclass 34, count 2 2006.173.03:17:05.57#ibcon#read 5, iclass 34, count 2 2006.173.03:17:05.57#ibcon#about to read 6, iclass 34, count 2 2006.173.03:17:05.57#ibcon#read 6, iclass 34, count 2 2006.173.03:17:05.57#ibcon#end of sib2, iclass 34, count 2 2006.173.03:17:05.57#ibcon#*mode == 0, iclass 34, count 2 2006.173.03:17:05.57#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.03:17:05.57#ibcon#[25=AT01-07\r\n] 2006.173.03:17:05.57#ibcon#*before write, iclass 34, count 2 2006.173.03:17:05.57#ibcon#enter sib2, iclass 34, count 2 2006.173.03:17:05.57#ibcon#flushed, iclass 34, count 2 2006.173.03:17:05.57#ibcon#about to write, iclass 34, count 2 2006.173.03:17:05.57#ibcon#wrote, iclass 34, count 2 2006.173.03:17:05.57#ibcon#about to read 3, iclass 34, count 2 2006.173.03:17:05.60#ibcon#read 3, iclass 34, count 2 2006.173.03:17:05.60#ibcon#about to read 4, iclass 34, count 2 2006.173.03:17:05.60#ibcon#read 4, iclass 34, count 2 2006.173.03:17:05.60#ibcon#about to read 5, iclass 34, count 2 2006.173.03:17:05.60#ibcon#read 5, iclass 34, count 2 2006.173.03:17:05.60#ibcon#about to read 6, iclass 34, count 2 2006.173.03:17:05.60#ibcon#read 6, iclass 34, count 2 2006.173.03:17:05.60#ibcon#end of sib2, iclass 34, count 2 2006.173.03:17:05.60#ibcon#*after write, iclass 34, count 2 2006.173.03:17:05.60#ibcon#*before return 0, iclass 34, count 2 2006.173.03:17:05.60#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.03:17:05.60#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.03:17:05.60#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.03:17:05.60#ibcon#ireg 7 cls_cnt 0 2006.173.03:17:05.60#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.03:17:05.72#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.03:17:05.72#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.03:17:05.72#ibcon#enter wrdev, iclass 34, count 0 2006.173.03:17:05.72#ibcon#first serial, iclass 34, count 0 2006.173.03:17:05.72#ibcon#enter sib2, iclass 34, count 0 2006.173.03:17:05.72#ibcon#flushed, iclass 34, count 0 2006.173.03:17:05.72#ibcon#about to write, iclass 34, count 0 2006.173.03:17:05.72#ibcon#wrote, iclass 34, count 0 2006.173.03:17:05.72#ibcon#about to read 3, iclass 34, count 0 2006.173.03:17:05.74#ibcon#read 3, iclass 34, count 0 2006.173.03:17:05.74#ibcon#about to read 4, iclass 34, count 0 2006.173.03:17:05.74#ibcon#read 4, iclass 34, count 0 2006.173.03:17:05.74#ibcon#about to read 5, iclass 34, count 0 2006.173.03:17:05.74#ibcon#read 5, iclass 34, count 0 2006.173.03:17:05.74#ibcon#about to read 6, iclass 34, count 0 2006.173.03:17:05.74#ibcon#read 6, iclass 34, count 0 2006.173.03:17:05.74#ibcon#end of sib2, iclass 34, count 0 2006.173.03:17:05.74#ibcon#*mode == 0, iclass 34, count 0 2006.173.03:17:05.74#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.03:17:05.74#ibcon#[25=USB\r\n] 2006.173.03:17:05.74#ibcon#*before write, iclass 34, count 0 2006.173.03:17:05.74#ibcon#enter sib2, iclass 34, count 0 2006.173.03:17:05.74#ibcon#flushed, iclass 34, count 0 2006.173.03:17:05.74#ibcon#about to write, iclass 34, count 0 2006.173.03:17:05.74#ibcon#wrote, iclass 34, count 0 2006.173.03:17:05.74#ibcon#about to read 3, iclass 34, count 0 2006.173.03:17:05.77#ibcon#read 3, iclass 34, count 0 2006.173.03:17:05.77#ibcon#about to read 4, iclass 34, count 0 2006.173.03:17:05.77#ibcon#read 4, iclass 34, count 0 2006.173.03:17:05.77#ibcon#about to read 5, iclass 34, count 0 2006.173.03:17:05.77#ibcon#read 5, iclass 34, count 0 2006.173.03:17:05.77#ibcon#about to read 6, iclass 34, count 0 2006.173.03:17:05.77#ibcon#read 6, iclass 34, count 0 2006.173.03:17:05.77#ibcon#end of sib2, iclass 34, count 0 2006.173.03:17:05.77#ibcon#*after write, iclass 34, count 0 2006.173.03:17:05.77#ibcon#*before return 0, iclass 34, count 0 2006.173.03:17:05.77#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.03:17:05.77#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.03:17:05.77#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.03:17:05.77#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.03:17:05.77$vck44/valo=2,534.99 2006.173.03:17:05.77#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.03:17:05.77#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.03:17:05.77#ibcon#ireg 17 cls_cnt 0 2006.173.03:17:05.77#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.03:17:05.77#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.03:17:05.77#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.03:17:05.77#ibcon#enter wrdev, iclass 36, count 0 2006.173.03:17:05.77#ibcon#first serial, iclass 36, count 0 2006.173.03:17:05.77#ibcon#enter sib2, iclass 36, count 0 2006.173.03:17:05.77#ibcon#flushed, iclass 36, count 0 2006.173.03:17:05.77#ibcon#about to write, iclass 36, count 0 2006.173.03:17:05.77#ibcon#wrote, iclass 36, count 0 2006.173.03:17:05.77#ibcon#about to read 3, iclass 36, count 0 2006.173.03:17:05.79#ibcon#read 3, iclass 36, count 0 2006.173.03:17:05.79#ibcon#about to read 4, iclass 36, count 0 2006.173.03:17:05.79#ibcon#read 4, iclass 36, count 0 2006.173.03:17:05.79#ibcon#about to read 5, iclass 36, count 0 2006.173.03:17:05.79#ibcon#read 5, iclass 36, count 0 2006.173.03:17:05.79#ibcon#about to read 6, iclass 36, count 0 2006.173.03:17:05.79#ibcon#read 6, iclass 36, count 0 2006.173.03:17:05.79#ibcon#end of sib2, iclass 36, count 0 2006.173.03:17:05.79#ibcon#*mode == 0, iclass 36, count 0 2006.173.03:17:05.79#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.03:17:05.79#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.03:17:05.79#ibcon#*before write, iclass 36, count 0 2006.173.03:17:05.79#ibcon#enter sib2, iclass 36, count 0 2006.173.03:17:05.79#ibcon#flushed, iclass 36, count 0 2006.173.03:17:05.79#ibcon#about to write, iclass 36, count 0 2006.173.03:17:05.79#ibcon#wrote, iclass 36, count 0 2006.173.03:17:05.79#ibcon#about to read 3, iclass 36, count 0 2006.173.03:17:05.83#ibcon#read 3, iclass 36, count 0 2006.173.03:17:05.83#ibcon#about to read 4, iclass 36, count 0 2006.173.03:17:05.83#ibcon#read 4, iclass 36, count 0 2006.173.03:17:05.83#ibcon#about to read 5, iclass 36, count 0 2006.173.03:17:05.83#ibcon#read 5, iclass 36, count 0 2006.173.03:17:05.83#ibcon#about to read 6, iclass 36, count 0 2006.173.03:17:05.83#ibcon#read 6, iclass 36, count 0 2006.173.03:17:05.83#ibcon#end of sib2, iclass 36, count 0 2006.173.03:17:05.83#ibcon#*after write, iclass 36, count 0 2006.173.03:17:05.83#ibcon#*before return 0, iclass 36, count 0 2006.173.03:17:05.83#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.03:17:05.83#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.03:17:05.83#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.03:17:05.83#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.03:17:05.83$vck44/va=2,6 2006.173.03:17:05.83#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.03:17:05.83#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.03:17:05.83#ibcon#ireg 11 cls_cnt 2 2006.173.03:17:05.83#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.03:17:05.89#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.03:17:05.89#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.03:17:05.89#ibcon#enter wrdev, iclass 38, count 2 2006.173.03:17:05.89#ibcon#first serial, iclass 38, count 2 2006.173.03:17:05.89#ibcon#enter sib2, iclass 38, count 2 2006.173.03:17:05.89#ibcon#flushed, iclass 38, count 2 2006.173.03:17:05.89#ibcon#about to write, iclass 38, count 2 2006.173.03:17:05.89#ibcon#wrote, iclass 38, count 2 2006.173.03:17:05.89#ibcon#about to read 3, iclass 38, count 2 2006.173.03:17:05.91#ibcon#read 3, iclass 38, count 2 2006.173.03:17:05.91#ibcon#about to read 4, iclass 38, count 2 2006.173.03:17:05.91#ibcon#read 4, iclass 38, count 2 2006.173.03:17:05.91#ibcon#about to read 5, iclass 38, count 2 2006.173.03:17:05.91#ibcon#read 5, iclass 38, count 2 2006.173.03:17:05.91#ibcon#about to read 6, iclass 38, count 2 2006.173.03:17:05.91#ibcon#read 6, iclass 38, count 2 2006.173.03:17:05.91#ibcon#end of sib2, iclass 38, count 2 2006.173.03:17:05.91#ibcon#*mode == 0, iclass 38, count 2 2006.173.03:17:05.91#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.03:17:05.91#ibcon#[25=AT02-06\r\n] 2006.173.03:17:05.91#ibcon#*before write, iclass 38, count 2 2006.173.03:17:05.91#ibcon#enter sib2, iclass 38, count 2 2006.173.03:17:05.91#ibcon#flushed, iclass 38, count 2 2006.173.03:17:05.91#ibcon#about to write, iclass 38, count 2 2006.173.03:17:05.91#ibcon#wrote, iclass 38, count 2 2006.173.03:17:05.91#ibcon#about to read 3, iclass 38, count 2 2006.173.03:17:05.94#ibcon#read 3, iclass 38, count 2 2006.173.03:17:05.94#ibcon#about to read 4, iclass 38, count 2 2006.173.03:17:05.94#ibcon#read 4, iclass 38, count 2 2006.173.03:17:05.94#ibcon#about to read 5, iclass 38, count 2 2006.173.03:17:05.94#ibcon#read 5, iclass 38, count 2 2006.173.03:17:05.94#ibcon#about to read 6, iclass 38, count 2 2006.173.03:17:05.94#ibcon#read 6, iclass 38, count 2 2006.173.03:17:05.94#ibcon#end of sib2, iclass 38, count 2 2006.173.03:17:05.94#ibcon#*after write, iclass 38, count 2 2006.173.03:17:05.94#ibcon#*before return 0, iclass 38, count 2 2006.173.03:17:05.94#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.03:17:05.94#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.03:17:05.94#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.03:17:05.94#ibcon#ireg 7 cls_cnt 0 2006.173.03:17:05.94#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.03:17:06.06#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.03:17:06.06#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.03:17:06.06#ibcon#enter wrdev, iclass 38, count 0 2006.173.03:17:06.06#ibcon#first serial, iclass 38, count 0 2006.173.03:17:06.06#ibcon#enter sib2, iclass 38, count 0 2006.173.03:17:06.06#ibcon#flushed, iclass 38, count 0 2006.173.03:17:06.06#ibcon#about to write, iclass 38, count 0 2006.173.03:17:06.06#ibcon#wrote, iclass 38, count 0 2006.173.03:17:06.06#ibcon#about to read 3, iclass 38, count 0 2006.173.03:17:06.08#ibcon#read 3, iclass 38, count 0 2006.173.03:17:06.08#ibcon#about to read 4, iclass 38, count 0 2006.173.03:17:06.08#ibcon#read 4, iclass 38, count 0 2006.173.03:17:06.08#ibcon#about to read 5, iclass 38, count 0 2006.173.03:17:06.08#ibcon#read 5, iclass 38, count 0 2006.173.03:17:06.08#ibcon#about to read 6, iclass 38, count 0 2006.173.03:17:06.08#ibcon#read 6, iclass 38, count 0 2006.173.03:17:06.08#ibcon#end of sib2, iclass 38, count 0 2006.173.03:17:06.08#ibcon#*mode == 0, iclass 38, count 0 2006.173.03:17:06.08#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.03:17:06.08#ibcon#[25=USB\r\n] 2006.173.03:17:06.08#ibcon#*before write, iclass 38, count 0 2006.173.03:17:06.08#ibcon#enter sib2, iclass 38, count 0 2006.173.03:17:06.08#ibcon#flushed, iclass 38, count 0 2006.173.03:17:06.08#ibcon#about to write, iclass 38, count 0 2006.173.03:17:06.08#ibcon#wrote, iclass 38, count 0 2006.173.03:17:06.08#ibcon#about to read 3, iclass 38, count 0 2006.173.03:17:06.11#ibcon#read 3, iclass 38, count 0 2006.173.03:17:06.11#ibcon#about to read 4, iclass 38, count 0 2006.173.03:17:06.11#ibcon#read 4, iclass 38, count 0 2006.173.03:17:06.11#ibcon#about to read 5, iclass 38, count 0 2006.173.03:17:06.11#ibcon#read 5, iclass 38, count 0 2006.173.03:17:06.11#ibcon#about to read 6, iclass 38, count 0 2006.173.03:17:06.11#ibcon#read 6, iclass 38, count 0 2006.173.03:17:06.11#ibcon#end of sib2, iclass 38, count 0 2006.173.03:17:06.11#ibcon#*after write, iclass 38, count 0 2006.173.03:17:06.11#ibcon#*before return 0, iclass 38, count 0 2006.173.03:17:06.11#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.03:17:06.11#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.03:17:06.11#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.03:17:06.11#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.03:17:06.11$vck44/valo=3,564.99 2006.173.03:17:06.11#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.03:17:06.11#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.03:17:06.11#ibcon#ireg 17 cls_cnt 0 2006.173.03:17:06.11#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.03:17:06.11#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.03:17:06.11#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.03:17:06.11#ibcon#enter wrdev, iclass 40, count 0 2006.173.03:17:06.11#ibcon#first serial, iclass 40, count 0 2006.173.03:17:06.11#ibcon#enter sib2, iclass 40, count 0 2006.173.03:17:06.11#ibcon#flushed, iclass 40, count 0 2006.173.03:17:06.11#ibcon#about to write, iclass 40, count 0 2006.173.03:17:06.11#ibcon#wrote, iclass 40, count 0 2006.173.03:17:06.11#ibcon#about to read 3, iclass 40, count 0 2006.173.03:17:06.13#ibcon#read 3, iclass 40, count 0 2006.173.03:17:06.13#ibcon#about to read 4, iclass 40, count 0 2006.173.03:17:06.13#ibcon#read 4, iclass 40, count 0 2006.173.03:17:06.13#ibcon#about to read 5, iclass 40, count 0 2006.173.03:17:06.13#ibcon#read 5, iclass 40, count 0 2006.173.03:17:06.13#ibcon#about to read 6, iclass 40, count 0 2006.173.03:17:06.13#ibcon#read 6, iclass 40, count 0 2006.173.03:17:06.13#ibcon#end of sib2, iclass 40, count 0 2006.173.03:17:06.13#ibcon#*mode == 0, iclass 40, count 0 2006.173.03:17:06.13#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.03:17:06.13#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.03:17:06.13#ibcon#*before write, iclass 40, count 0 2006.173.03:17:06.13#ibcon#enter sib2, iclass 40, count 0 2006.173.03:17:06.13#ibcon#flushed, iclass 40, count 0 2006.173.03:17:06.13#ibcon#about to write, iclass 40, count 0 2006.173.03:17:06.13#ibcon#wrote, iclass 40, count 0 2006.173.03:17:06.13#ibcon#about to read 3, iclass 40, count 0 2006.173.03:17:06.17#ibcon#read 3, iclass 40, count 0 2006.173.03:17:06.17#ibcon#about to read 4, iclass 40, count 0 2006.173.03:17:06.17#ibcon#read 4, iclass 40, count 0 2006.173.03:17:06.17#ibcon#about to read 5, iclass 40, count 0 2006.173.03:17:06.17#ibcon#read 5, iclass 40, count 0 2006.173.03:17:06.17#ibcon#about to read 6, iclass 40, count 0 2006.173.03:17:06.17#ibcon#read 6, iclass 40, count 0 2006.173.03:17:06.17#ibcon#end of sib2, iclass 40, count 0 2006.173.03:17:06.17#ibcon#*after write, iclass 40, count 0 2006.173.03:17:06.17#ibcon#*before return 0, iclass 40, count 0 2006.173.03:17:06.17#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.03:17:06.17#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.03:17:06.17#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.03:17:06.17#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.03:17:06.17$vck44/va=3,5 2006.173.03:17:06.17#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.03:17:06.17#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.03:17:06.17#ibcon#ireg 11 cls_cnt 2 2006.173.03:17:06.17#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.03:17:06.23#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.03:17:06.23#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.03:17:06.23#ibcon#enter wrdev, iclass 4, count 2 2006.173.03:17:06.23#ibcon#first serial, iclass 4, count 2 2006.173.03:17:06.23#ibcon#enter sib2, iclass 4, count 2 2006.173.03:17:06.23#ibcon#flushed, iclass 4, count 2 2006.173.03:17:06.23#ibcon#about to write, iclass 4, count 2 2006.173.03:17:06.23#ibcon#wrote, iclass 4, count 2 2006.173.03:17:06.23#ibcon#about to read 3, iclass 4, count 2 2006.173.03:17:06.25#ibcon#read 3, iclass 4, count 2 2006.173.03:17:06.25#ibcon#about to read 4, iclass 4, count 2 2006.173.03:17:06.25#ibcon#read 4, iclass 4, count 2 2006.173.03:17:06.25#ibcon#about to read 5, iclass 4, count 2 2006.173.03:17:06.25#ibcon#read 5, iclass 4, count 2 2006.173.03:17:06.25#ibcon#about to read 6, iclass 4, count 2 2006.173.03:17:06.25#ibcon#read 6, iclass 4, count 2 2006.173.03:17:06.25#ibcon#end of sib2, iclass 4, count 2 2006.173.03:17:06.25#ibcon#*mode == 0, iclass 4, count 2 2006.173.03:17:06.25#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.03:17:06.25#ibcon#[25=AT03-05\r\n] 2006.173.03:17:06.25#ibcon#*before write, iclass 4, count 2 2006.173.03:17:06.25#ibcon#enter sib2, iclass 4, count 2 2006.173.03:17:06.25#ibcon#flushed, iclass 4, count 2 2006.173.03:17:06.25#ibcon#about to write, iclass 4, count 2 2006.173.03:17:06.25#ibcon#wrote, iclass 4, count 2 2006.173.03:17:06.25#ibcon#about to read 3, iclass 4, count 2 2006.173.03:17:06.28#ibcon#read 3, iclass 4, count 2 2006.173.03:17:06.28#ibcon#about to read 4, iclass 4, count 2 2006.173.03:17:06.28#ibcon#read 4, iclass 4, count 2 2006.173.03:17:06.28#ibcon#about to read 5, iclass 4, count 2 2006.173.03:17:06.28#ibcon#read 5, iclass 4, count 2 2006.173.03:17:06.28#ibcon#about to read 6, iclass 4, count 2 2006.173.03:17:06.28#ibcon#read 6, iclass 4, count 2 2006.173.03:17:06.28#ibcon#end of sib2, iclass 4, count 2 2006.173.03:17:06.28#ibcon#*after write, iclass 4, count 2 2006.173.03:17:06.28#ibcon#*before return 0, iclass 4, count 2 2006.173.03:17:06.28#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.03:17:06.28#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.03:17:06.28#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.03:17:06.28#ibcon#ireg 7 cls_cnt 0 2006.173.03:17:06.28#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.03:17:06.40#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.03:17:06.40#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.03:17:06.40#ibcon#enter wrdev, iclass 4, count 0 2006.173.03:17:06.40#ibcon#first serial, iclass 4, count 0 2006.173.03:17:06.40#ibcon#enter sib2, iclass 4, count 0 2006.173.03:17:06.40#ibcon#flushed, iclass 4, count 0 2006.173.03:17:06.40#ibcon#about to write, iclass 4, count 0 2006.173.03:17:06.40#ibcon#wrote, iclass 4, count 0 2006.173.03:17:06.40#ibcon#about to read 3, iclass 4, count 0 2006.173.03:17:06.42#ibcon#read 3, iclass 4, count 0 2006.173.03:17:06.42#ibcon#about to read 4, iclass 4, count 0 2006.173.03:17:06.42#ibcon#read 4, iclass 4, count 0 2006.173.03:17:06.42#ibcon#about to read 5, iclass 4, count 0 2006.173.03:17:06.42#ibcon#read 5, iclass 4, count 0 2006.173.03:17:06.42#ibcon#about to read 6, iclass 4, count 0 2006.173.03:17:06.42#ibcon#read 6, iclass 4, count 0 2006.173.03:17:06.42#ibcon#end of sib2, iclass 4, count 0 2006.173.03:17:06.42#ibcon#*mode == 0, iclass 4, count 0 2006.173.03:17:06.42#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.03:17:06.42#ibcon#[25=USB\r\n] 2006.173.03:17:06.42#ibcon#*before write, iclass 4, count 0 2006.173.03:17:06.42#ibcon#enter sib2, iclass 4, count 0 2006.173.03:17:06.42#ibcon#flushed, iclass 4, count 0 2006.173.03:17:06.42#ibcon#about to write, iclass 4, count 0 2006.173.03:17:06.42#ibcon#wrote, iclass 4, count 0 2006.173.03:17:06.42#ibcon#about to read 3, iclass 4, count 0 2006.173.03:17:06.45#ibcon#read 3, iclass 4, count 0 2006.173.03:17:06.45#ibcon#about to read 4, iclass 4, count 0 2006.173.03:17:06.45#ibcon#read 4, iclass 4, count 0 2006.173.03:17:06.45#ibcon#about to read 5, iclass 4, count 0 2006.173.03:17:06.45#ibcon#read 5, iclass 4, count 0 2006.173.03:17:06.45#ibcon#about to read 6, iclass 4, count 0 2006.173.03:17:06.45#ibcon#read 6, iclass 4, count 0 2006.173.03:17:06.45#ibcon#end of sib2, iclass 4, count 0 2006.173.03:17:06.45#ibcon#*after write, iclass 4, count 0 2006.173.03:17:06.45#ibcon#*before return 0, iclass 4, count 0 2006.173.03:17:06.45#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.03:17:06.45#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.03:17:06.45#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.03:17:06.45#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.03:17:06.45$vck44/valo=4,624.99 2006.173.03:17:06.45#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.03:17:06.45#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.03:17:06.45#ibcon#ireg 17 cls_cnt 0 2006.173.03:17:06.45#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.03:17:06.45#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.03:17:06.45#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.03:17:06.45#ibcon#enter wrdev, iclass 6, count 0 2006.173.03:17:06.45#ibcon#first serial, iclass 6, count 0 2006.173.03:17:06.45#ibcon#enter sib2, iclass 6, count 0 2006.173.03:17:06.45#ibcon#flushed, iclass 6, count 0 2006.173.03:17:06.45#ibcon#about to write, iclass 6, count 0 2006.173.03:17:06.45#ibcon#wrote, iclass 6, count 0 2006.173.03:17:06.45#ibcon#about to read 3, iclass 6, count 0 2006.173.03:17:06.47#ibcon#read 3, iclass 6, count 0 2006.173.03:17:06.47#ibcon#about to read 4, iclass 6, count 0 2006.173.03:17:06.47#ibcon#read 4, iclass 6, count 0 2006.173.03:17:06.47#ibcon#about to read 5, iclass 6, count 0 2006.173.03:17:06.47#ibcon#read 5, iclass 6, count 0 2006.173.03:17:06.47#ibcon#about to read 6, iclass 6, count 0 2006.173.03:17:06.47#ibcon#read 6, iclass 6, count 0 2006.173.03:17:06.47#ibcon#end of sib2, iclass 6, count 0 2006.173.03:17:06.47#ibcon#*mode == 0, iclass 6, count 0 2006.173.03:17:06.47#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.03:17:06.47#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.03:17:06.47#ibcon#*before write, iclass 6, count 0 2006.173.03:17:06.47#ibcon#enter sib2, iclass 6, count 0 2006.173.03:17:06.47#ibcon#flushed, iclass 6, count 0 2006.173.03:17:06.47#ibcon#about to write, iclass 6, count 0 2006.173.03:17:06.47#ibcon#wrote, iclass 6, count 0 2006.173.03:17:06.47#ibcon#about to read 3, iclass 6, count 0 2006.173.03:17:06.51#ibcon#read 3, iclass 6, count 0 2006.173.03:17:06.51#ibcon#about to read 4, iclass 6, count 0 2006.173.03:17:06.51#ibcon#read 4, iclass 6, count 0 2006.173.03:17:06.51#ibcon#about to read 5, iclass 6, count 0 2006.173.03:17:06.51#ibcon#read 5, iclass 6, count 0 2006.173.03:17:06.51#ibcon#about to read 6, iclass 6, count 0 2006.173.03:17:06.51#ibcon#read 6, iclass 6, count 0 2006.173.03:17:06.51#ibcon#end of sib2, iclass 6, count 0 2006.173.03:17:06.51#ibcon#*after write, iclass 6, count 0 2006.173.03:17:06.51#ibcon#*before return 0, iclass 6, count 0 2006.173.03:17:06.51#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.03:17:06.51#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.03:17:06.51#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.03:17:06.51#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.03:17:06.51$vck44/va=4,6 2006.173.03:17:06.51#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.03:17:06.51#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.03:17:06.51#ibcon#ireg 11 cls_cnt 2 2006.173.03:17:06.51#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.03:17:06.57#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.03:17:06.57#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.03:17:06.57#ibcon#enter wrdev, iclass 10, count 2 2006.173.03:17:06.57#ibcon#first serial, iclass 10, count 2 2006.173.03:17:06.57#ibcon#enter sib2, iclass 10, count 2 2006.173.03:17:06.57#ibcon#flushed, iclass 10, count 2 2006.173.03:17:06.57#ibcon#about to write, iclass 10, count 2 2006.173.03:17:06.57#ibcon#wrote, iclass 10, count 2 2006.173.03:17:06.57#ibcon#about to read 3, iclass 10, count 2 2006.173.03:17:06.59#ibcon#read 3, iclass 10, count 2 2006.173.03:17:06.59#ibcon#about to read 4, iclass 10, count 2 2006.173.03:17:06.59#ibcon#read 4, iclass 10, count 2 2006.173.03:17:06.59#ibcon#about to read 5, iclass 10, count 2 2006.173.03:17:06.59#ibcon#read 5, iclass 10, count 2 2006.173.03:17:06.59#ibcon#about to read 6, iclass 10, count 2 2006.173.03:17:06.59#ibcon#read 6, iclass 10, count 2 2006.173.03:17:06.59#ibcon#end of sib2, iclass 10, count 2 2006.173.03:17:06.59#ibcon#*mode == 0, iclass 10, count 2 2006.173.03:17:06.59#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.03:17:06.59#ibcon#[25=AT04-06\r\n] 2006.173.03:17:06.59#ibcon#*before write, iclass 10, count 2 2006.173.03:17:06.59#ibcon#enter sib2, iclass 10, count 2 2006.173.03:17:06.59#ibcon#flushed, iclass 10, count 2 2006.173.03:17:06.59#ibcon#about to write, iclass 10, count 2 2006.173.03:17:06.59#ibcon#wrote, iclass 10, count 2 2006.173.03:17:06.59#ibcon#about to read 3, iclass 10, count 2 2006.173.03:17:06.62#ibcon#read 3, iclass 10, count 2 2006.173.03:17:06.62#ibcon#about to read 4, iclass 10, count 2 2006.173.03:17:06.62#ibcon#read 4, iclass 10, count 2 2006.173.03:17:06.62#ibcon#about to read 5, iclass 10, count 2 2006.173.03:17:06.62#ibcon#read 5, iclass 10, count 2 2006.173.03:17:06.62#ibcon#about to read 6, iclass 10, count 2 2006.173.03:17:06.62#ibcon#read 6, iclass 10, count 2 2006.173.03:17:06.62#ibcon#end of sib2, iclass 10, count 2 2006.173.03:17:06.62#ibcon#*after write, iclass 10, count 2 2006.173.03:17:06.62#ibcon#*before return 0, iclass 10, count 2 2006.173.03:17:06.62#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.03:17:06.62#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.03:17:06.62#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.03:17:06.62#ibcon#ireg 7 cls_cnt 0 2006.173.03:17:06.62#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.03:17:06.74#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.03:17:06.74#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.03:17:06.74#ibcon#enter wrdev, iclass 10, count 0 2006.173.03:17:06.74#ibcon#first serial, iclass 10, count 0 2006.173.03:17:06.74#ibcon#enter sib2, iclass 10, count 0 2006.173.03:17:06.74#ibcon#flushed, iclass 10, count 0 2006.173.03:17:06.74#ibcon#about to write, iclass 10, count 0 2006.173.03:17:06.74#ibcon#wrote, iclass 10, count 0 2006.173.03:17:06.74#ibcon#about to read 3, iclass 10, count 0 2006.173.03:17:06.76#ibcon#read 3, iclass 10, count 0 2006.173.03:17:06.76#ibcon#about to read 4, iclass 10, count 0 2006.173.03:17:06.76#ibcon#read 4, iclass 10, count 0 2006.173.03:17:06.76#ibcon#about to read 5, iclass 10, count 0 2006.173.03:17:06.76#ibcon#read 5, iclass 10, count 0 2006.173.03:17:06.76#ibcon#about to read 6, iclass 10, count 0 2006.173.03:17:06.76#ibcon#read 6, iclass 10, count 0 2006.173.03:17:06.76#ibcon#end of sib2, iclass 10, count 0 2006.173.03:17:06.76#ibcon#*mode == 0, iclass 10, count 0 2006.173.03:17:06.76#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.03:17:06.76#ibcon#[25=USB\r\n] 2006.173.03:17:06.76#ibcon#*before write, iclass 10, count 0 2006.173.03:17:06.76#ibcon#enter sib2, iclass 10, count 0 2006.173.03:17:06.76#ibcon#flushed, iclass 10, count 0 2006.173.03:17:06.76#ibcon#about to write, iclass 10, count 0 2006.173.03:17:06.76#ibcon#wrote, iclass 10, count 0 2006.173.03:17:06.76#ibcon#about to read 3, iclass 10, count 0 2006.173.03:17:06.79#ibcon#read 3, iclass 10, count 0 2006.173.03:17:06.79#ibcon#about to read 4, iclass 10, count 0 2006.173.03:17:06.79#ibcon#read 4, iclass 10, count 0 2006.173.03:17:06.79#ibcon#about to read 5, iclass 10, count 0 2006.173.03:17:06.79#ibcon#read 5, iclass 10, count 0 2006.173.03:17:06.79#ibcon#about to read 6, iclass 10, count 0 2006.173.03:17:06.79#ibcon#read 6, iclass 10, count 0 2006.173.03:17:06.79#ibcon#end of sib2, iclass 10, count 0 2006.173.03:17:06.79#ibcon#*after write, iclass 10, count 0 2006.173.03:17:06.79#ibcon#*before return 0, iclass 10, count 0 2006.173.03:17:06.79#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.03:17:06.79#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.03:17:06.79#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.03:17:06.79#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.03:17:06.79$vck44/valo=5,734.99 2006.173.03:17:06.79#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.03:17:06.79#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.03:17:06.79#ibcon#ireg 17 cls_cnt 0 2006.173.03:17:06.79#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.03:17:06.79#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.03:17:06.79#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.03:17:06.79#ibcon#enter wrdev, iclass 12, count 0 2006.173.03:17:06.79#ibcon#first serial, iclass 12, count 0 2006.173.03:17:06.79#ibcon#enter sib2, iclass 12, count 0 2006.173.03:17:06.79#ibcon#flushed, iclass 12, count 0 2006.173.03:17:06.79#ibcon#about to write, iclass 12, count 0 2006.173.03:17:06.79#ibcon#wrote, iclass 12, count 0 2006.173.03:17:06.79#ibcon#about to read 3, iclass 12, count 0 2006.173.03:17:06.81#ibcon#read 3, iclass 12, count 0 2006.173.03:17:06.81#ibcon#about to read 4, iclass 12, count 0 2006.173.03:17:06.81#ibcon#read 4, iclass 12, count 0 2006.173.03:17:06.81#ibcon#about to read 5, iclass 12, count 0 2006.173.03:17:06.81#ibcon#read 5, iclass 12, count 0 2006.173.03:17:06.81#ibcon#about to read 6, iclass 12, count 0 2006.173.03:17:06.81#ibcon#read 6, iclass 12, count 0 2006.173.03:17:06.81#ibcon#end of sib2, iclass 12, count 0 2006.173.03:17:06.81#ibcon#*mode == 0, iclass 12, count 0 2006.173.03:17:06.81#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.03:17:06.81#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.03:17:06.81#ibcon#*before write, iclass 12, count 0 2006.173.03:17:06.81#ibcon#enter sib2, iclass 12, count 0 2006.173.03:17:06.81#ibcon#flushed, iclass 12, count 0 2006.173.03:17:06.81#ibcon#about to write, iclass 12, count 0 2006.173.03:17:06.81#ibcon#wrote, iclass 12, count 0 2006.173.03:17:06.81#ibcon#about to read 3, iclass 12, count 0 2006.173.03:17:06.85#ibcon#read 3, iclass 12, count 0 2006.173.03:17:06.85#ibcon#about to read 4, iclass 12, count 0 2006.173.03:17:06.85#ibcon#read 4, iclass 12, count 0 2006.173.03:17:06.85#ibcon#about to read 5, iclass 12, count 0 2006.173.03:17:06.85#ibcon#read 5, iclass 12, count 0 2006.173.03:17:06.85#ibcon#about to read 6, iclass 12, count 0 2006.173.03:17:06.85#ibcon#read 6, iclass 12, count 0 2006.173.03:17:06.85#ibcon#end of sib2, iclass 12, count 0 2006.173.03:17:06.85#ibcon#*after write, iclass 12, count 0 2006.173.03:17:06.85#ibcon#*before return 0, iclass 12, count 0 2006.173.03:17:06.85#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.03:17:06.85#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.03:17:06.85#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.03:17:06.85#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.03:17:06.85$vck44/va=5,4 2006.173.03:17:06.85#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.03:17:06.85#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.03:17:06.85#ibcon#ireg 11 cls_cnt 2 2006.173.03:17:06.85#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.03:17:06.91#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.03:17:06.91#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.03:17:06.91#ibcon#enter wrdev, iclass 14, count 2 2006.173.03:17:06.91#ibcon#first serial, iclass 14, count 2 2006.173.03:17:06.91#ibcon#enter sib2, iclass 14, count 2 2006.173.03:17:06.91#ibcon#flushed, iclass 14, count 2 2006.173.03:17:06.91#ibcon#about to write, iclass 14, count 2 2006.173.03:17:06.91#ibcon#wrote, iclass 14, count 2 2006.173.03:17:06.91#ibcon#about to read 3, iclass 14, count 2 2006.173.03:17:06.93#ibcon#read 3, iclass 14, count 2 2006.173.03:17:06.93#ibcon#about to read 4, iclass 14, count 2 2006.173.03:17:06.93#ibcon#read 4, iclass 14, count 2 2006.173.03:17:06.93#ibcon#about to read 5, iclass 14, count 2 2006.173.03:17:06.93#ibcon#read 5, iclass 14, count 2 2006.173.03:17:06.93#ibcon#about to read 6, iclass 14, count 2 2006.173.03:17:06.93#ibcon#read 6, iclass 14, count 2 2006.173.03:17:06.93#ibcon#end of sib2, iclass 14, count 2 2006.173.03:17:06.93#ibcon#*mode == 0, iclass 14, count 2 2006.173.03:17:06.93#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.03:17:06.93#ibcon#[25=AT05-04\r\n] 2006.173.03:17:06.93#ibcon#*before write, iclass 14, count 2 2006.173.03:17:06.93#ibcon#enter sib2, iclass 14, count 2 2006.173.03:17:06.93#ibcon#flushed, iclass 14, count 2 2006.173.03:17:06.93#ibcon#about to write, iclass 14, count 2 2006.173.03:17:06.93#ibcon#wrote, iclass 14, count 2 2006.173.03:17:06.93#ibcon#about to read 3, iclass 14, count 2 2006.173.03:17:06.96#ibcon#read 3, iclass 14, count 2 2006.173.03:17:06.96#ibcon#about to read 4, iclass 14, count 2 2006.173.03:17:06.96#ibcon#read 4, iclass 14, count 2 2006.173.03:17:06.96#ibcon#about to read 5, iclass 14, count 2 2006.173.03:17:06.96#ibcon#read 5, iclass 14, count 2 2006.173.03:17:06.96#ibcon#about to read 6, iclass 14, count 2 2006.173.03:17:06.96#ibcon#read 6, iclass 14, count 2 2006.173.03:17:06.96#ibcon#end of sib2, iclass 14, count 2 2006.173.03:17:06.96#ibcon#*after write, iclass 14, count 2 2006.173.03:17:06.96#ibcon#*before return 0, iclass 14, count 2 2006.173.03:17:06.96#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.03:17:06.96#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.03:17:06.96#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.03:17:06.96#ibcon#ireg 7 cls_cnt 0 2006.173.03:17:06.96#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.03:17:07.08#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.03:17:07.08#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.03:17:07.08#ibcon#enter wrdev, iclass 14, count 0 2006.173.03:17:07.08#ibcon#first serial, iclass 14, count 0 2006.173.03:17:07.08#ibcon#enter sib2, iclass 14, count 0 2006.173.03:17:07.08#ibcon#flushed, iclass 14, count 0 2006.173.03:17:07.08#ibcon#about to write, iclass 14, count 0 2006.173.03:17:07.08#ibcon#wrote, iclass 14, count 0 2006.173.03:17:07.08#ibcon#about to read 3, iclass 14, count 0 2006.173.03:17:07.10#ibcon#read 3, iclass 14, count 0 2006.173.03:17:07.10#ibcon#about to read 4, iclass 14, count 0 2006.173.03:17:07.10#ibcon#read 4, iclass 14, count 0 2006.173.03:17:07.10#ibcon#about to read 5, iclass 14, count 0 2006.173.03:17:07.10#ibcon#read 5, iclass 14, count 0 2006.173.03:17:07.10#ibcon#about to read 6, iclass 14, count 0 2006.173.03:17:07.10#ibcon#read 6, iclass 14, count 0 2006.173.03:17:07.10#ibcon#end of sib2, iclass 14, count 0 2006.173.03:17:07.10#ibcon#*mode == 0, iclass 14, count 0 2006.173.03:17:07.10#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.03:17:07.10#ibcon#[25=USB\r\n] 2006.173.03:17:07.10#ibcon#*before write, iclass 14, count 0 2006.173.03:17:07.10#ibcon#enter sib2, iclass 14, count 0 2006.173.03:17:07.10#ibcon#flushed, iclass 14, count 0 2006.173.03:17:07.10#ibcon#about to write, iclass 14, count 0 2006.173.03:17:07.10#ibcon#wrote, iclass 14, count 0 2006.173.03:17:07.10#ibcon#about to read 3, iclass 14, count 0 2006.173.03:17:07.13#ibcon#read 3, iclass 14, count 0 2006.173.03:17:07.13#ibcon#about to read 4, iclass 14, count 0 2006.173.03:17:07.13#ibcon#read 4, iclass 14, count 0 2006.173.03:17:07.13#ibcon#about to read 5, iclass 14, count 0 2006.173.03:17:07.13#ibcon#read 5, iclass 14, count 0 2006.173.03:17:07.13#ibcon#about to read 6, iclass 14, count 0 2006.173.03:17:07.13#ibcon#read 6, iclass 14, count 0 2006.173.03:17:07.13#ibcon#end of sib2, iclass 14, count 0 2006.173.03:17:07.13#ibcon#*after write, iclass 14, count 0 2006.173.03:17:07.13#ibcon#*before return 0, iclass 14, count 0 2006.173.03:17:07.13#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.03:17:07.13#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.03:17:07.13#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.03:17:07.13#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.03:17:07.13$vck44/valo=6,814.99 2006.173.03:17:07.13#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.03:17:07.13#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.03:17:07.13#ibcon#ireg 17 cls_cnt 0 2006.173.03:17:07.13#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.03:17:07.13#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.03:17:07.13#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.03:17:07.13#ibcon#enter wrdev, iclass 16, count 0 2006.173.03:17:07.13#ibcon#first serial, iclass 16, count 0 2006.173.03:17:07.13#ibcon#enter sib2, iclass 16, count 0 2006.173.03:17:07.13#ibcon#flushed, iclass 16, count 0 2006.173.03:17:07.13#ibcon#about to write, iclass 16, count 0 2006.173.03:17:07.13#ibcon#wrote, iclass 16, count 0 2006.173.03:17:07.13#ibcon#about to read 3, iclass 16, count 0 2006.173.03:17:07.15#ibcon#read 3, iclass 16, count 0 2006.173.03:17:07.15#ibcon#about to read 4, iclass 16, count 0 2006.173.03:17:07.15#ibcon#read 4, iclass 16, count 0 2006.173.03:17:07.15#ibcon#about to read 5, iclass 16, count 0 2006.173.03:17:07.15#ibcon#read 5, iclass 16, count 0 2006.173.03:17:07.15#ibcon#about to read 6, iclass 16, count 0 2006.173.03:17:07.15#ibcon#read 6, iclass 16, count 0 2006.173.03:17:07.15#ibcon#end of sib2, iclass 16, count 0 2006.173.03:17:07.15#ibcon#*mode == 0, iclass 16, count 0 2006.173.03:17:07.15#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.03:17:07.15#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.03:17:07.15#ibcon#*before write, iclass 16, count 0 2006.173.03:17:07.15#ibcon#enter sib2, iclass 16, count 0 2006.173.03:17:07.15#ibcon#flushed, iclass 16, count 0 2006.173.03:17:07.15#ibcon#about to write, iclass 16, count 0 2006.173.03:17:07.15#ibcon#wrote, iclass 16, count 0 2006.173.03:17:07.15#ibcon#about to read 3, iclass 16, count 0 2006.173.03:17:07.19#ibcon#read 3, iclass 16, count 0 2006.173.03:17:07.19#ibcon#about to read 4, iclass 16, count 0 2006.173.03:17:07.19#ibcon#read 4, iclass 16, count 0 2006.173.03:17:07.19#ibcon#about to read 5, iclass 16, count 0 2006.173.03:17:07.19#ibcon#read 5, iclass 16, count 0 2006.173.03:17:07.19#ibcon#about to read 6, iclass 16, count 0 2006.173.03:17:07.19#ibcon#read 6, iclass 16, count 0 2006.173.03:17:07.19#ibcon#end of sib2, iclass 16, count 0 2006.173.03:17:07.19#ibcon#*after write, iclass 16, count 0 2006.173.03:17:07.19#ibcon#*before return 0, iclass 16, count 0 2006.173.03:17:07.19#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.03:17:07.19#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.03:17:07.19#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.03:17:07.19#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.03:17:07.19$vck44/va=6,3 2006.173.03:17:07.19#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.03:17:07.19#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.03:17:07.19#ibcon#ireg 11 cls_cnt 2 2006.173.03:17:07.19#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.03:17:07.25#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.03:17:07.25#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.03:17:07.25#ibcon#enter wrdev, iclass 18, count 2 2006.173.03:17:07.25#ibcon#first serial, iclass 18, count 2 2006.173.03:17:07.25#ibcon#enter sib2, iclass 18, count 2 2006.173.03:17:07.25#ibcon#flushed, iclass 18, count 2 2006.173.03:17:07.25#ibcon#about to write, iclass 18, count 2 2006.173.03:17:07.25#ibcon#wrote, iclass 18, count 2 2006.173.03:17:07.25#ibcon#about to read 3, iclass 18, count 2 2006.173.03:17:07.27#ibcon#read 3, iclass 18, count 2 2006.173.03:17:07.27#ibcon#about to read 4, iclass 18, count 2 2006.173.03:17:07.27#ibcon#read 4, iclass 18, count 2 2006.173.03:17:07.27#ibcon#about to read 5, iclass 18, count 2 2006.173.03:17:07.27#ibcon#read 5, iclass 18, count 2 2006.173.03:17:07.27#ibcon#about to read 6, iclass 18, count 2 2006.173.03:17:07.27#ibcon#read 6, iclass 18, count 2 2006.173.03:17:07.27#ibcon#end of sib2, iclass 18, count 2 2006.173.03:17:07.27#ibcon#*mode == 0, iclass 18, count 2 2006.173.03:17:07.27#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.03:17:07.27#ibcon#[25=AT06-03\r\n] 2006.173.03:17:07.27#ibcon#*before write, iclass 18, count 2 2006.173.03:17:07.27#ibcon#enter sib2, iclass 18, count 2 2006.173.03:17:07.27#ibcon#flushed, iclass 18, count 2 2006.173.03:17:07.27#ibcon#about to write, iclass 18, count 2 2006.173.03:17:07.27#ibcon#wrote, iclass 18, count 2 2006.173.03:17:07.27#ibcon#about to read 3, iclass 18, count 2 2006.173.03:17:07.30#ibcon#read 3, iclass 18, count 2 2006.173.03:17:07.30#ibcon#about to read 4, iclass 18, count 2 2006.173.03:17:07.30#ibcon#read 4, iclass 18, count 2 2006.173.03:17:07.30#ibcon#about to read 5, iclass 18, count 2 2006.173.03:17:07.30#ibcon#read 5, iclass 18, count 2 2006.173.03:17:07.30#ibcon#about to read 6, iclass 18, count 2 2006.173.03:17:07.30#ibcon#read 6, iclass 18, count 2 2006.173.03:17:07.30#ibcon#end of sib2, iclass 18, count 2 2006.173.03:17:07.30#ibcon#*after write, iclass 18, count 2 2006.173.03:17:07.30#ibcon#*before return 0, iclass 18, count 2 2006.173.03:17:07.30#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.03:17:07.30#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.03:17:07.30#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.03:17:07.30#ibcon#ireg 7 cls_cnt 0 2006.173.03:17:07.30#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.03:17:07.42#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.03:17:07.42#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.03:17:07.42#ibcon#enter wrdev, iclass 18, count 0 2006.173.03:17:07.42#ibcon#first serial, iclass 18, count 0 2006.173.03:17:07.42#ibcon#enter sib2, iclass 18, count 0 2006.173.03:17:07.42#ibcon#flushed, iclass 18, count 0 2006.173.03:17:07.42#ibcon#about to write, iclass 18, count 0 2006.173.03:17:07.42#ibcon#wrote, iclass 18, count 0 2006.173.03:17:07.42#ibcon#about to read 3, iclass 18, count 0 2006.173.03:17:07.44#ibcon#read 3, iclass 18, count 0 2006.173.03:17:07.44#ibcon#about to read 4, iclass 18, count 0 2006.173.03:17:07.44#ibcon#read 4, iclass 18, count 0 2006.173.03:17:07.44#ibcon#about to read 5, iclass 18, count 0 2006.173.03:17:07.44#ibcon#read 5, iclass 18, count 0 2006.173.03:17:07.44#ibcon#about to read 6, iclass 18, count 0 2006.173.03:17:07.44#ibcon#read 6, iclass 18, count 0 2006.173.03:17:07.44#ibcon#end of sib2, iclass 18, count 0 2006.173.03:17:07.44#ibcon#*mode == 0, iclass 18, count 0 2006.173.03:17:07.44#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.03:17:07.44#ibcon#[25=USB\r\n] 2006.173.03:17:07.44#ibcon#*before write, iclass 18, count 0 2006.173.03:17:07.44#ibcon#enter sib2, iclass 18, count 0 2006.173.03:17:07.44#ibcon#flushed, iclass 18, count 0 2006.173.03:17:07.44#ibcon#about to write, iclass 18, count 0 2006.173.03:17:07.44#ibcon#wrote, iclass 18, count 0 2006.173.03:17:07.44#ibcon#about to read 3, iclass 18, count 0 2006.173.03:17:07.47#ibcon#read 3, iclass 18, count 0 2006.173.03:17:07.47#ibcon#about to read 4, iclass 18, count 0 2006.173.03:17:07.47#ibcon#read 4, iclass 18, count 0 2006.173.03:17:07.47#ibcon#about to read 5, iclass 18, count 0 2006.173.03:17:07.47#ibcon#read 5, iclass 18, count 0 2006.173.03:17:07.47#ibcon#about to read 6, iclass 18, count 0 2006.173.03:17:07.47#ibcon#read 6, iclass 18, count 0 2006.173.03:17:07.47#ibcon#end of sib2, iclass 18, count 0 2006.173.03:17:07.47#ibcon#*after write, iclass 18, count 0 2006.173.03:17:07.47#ibcon#*before return 0, iclass 18, count 0 2006.173.03:17:07.47#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.03:17:07.47#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.03:17:07.47#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.03:17:07.47#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.03:17:07.47$vck44/valo=7,864.99 2006.173.03:17:07.47#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.03:17:07.47#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.03:17:07.47#ibcon#ireg 17 cls_cnt 0 2006.173.03:17:07.47#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.03:17:07.47#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.03:17:07.47#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.03:17:07.47#ibcon#enter wrdev, iclass 20, count 0 2006.173.03:17:07.47#ibcon#first serial, iclass 20, count 0 2006.173.03:17:07.47#ibcon#enter sib2, iclass 20, count 0 2006.173.03:17:07.47#ibcon#flushed, iclass 20, count 0 2006.173.03:17:07.47#ibcon#about to write, iclass 20, count 0 2006.173.03:17:07.47#ibcon#wrote, iclass 20, count 0 2006.173.03:17:07.47#ibcon#about to read 3, iclass 20, count 0 2006.173.03:17:07.49#ibcon#read 3, iclass 20, count 0 2006.173.03:17:07.49#ibcon#about to read 4, iclass 20, count 0 2006.173.03:17:07.49#ibcon#read 4, iclass 20, count 0 2006.173.03:17:07.49#ibcon#about to read 5, iclass 20, count 0 2006.173.03:17:07.49#ibcon#read 5, iclass 20, count 0 2006.173.03:17:07.49#ibcon#about to read 6, iclass 20, count 0 2006.173.03:17:07.49#ibcon#read 6, iclass 20, count 0 2006.173.03:17:07.49#ibcon#end of sib2, iclass 20, count 0 2006.173.03:17:07.49#ibcon#*mode == 0, iclass 20, count 0 2006.173.03:17:07.49#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.03:17:07.49#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.03:17:07.49#ibcon#*before write, iclass 20, count 0 2006.173.03:17:07.49#ibcon#enter sib2, iclass 20, count 0 2006.173.03:17:07.49#ibcon#flushed, iclass 20, count 0 2006.173.03:17:07.49#ibcon#about to write, iclass 20, count 0 2006.173.03:17:07.49#ibcon#wrote, iclass 20, count 0 2006.173.03:17:07.49#ibcon#about to read 3, iclass 20, count 0 2006.173.03:17:07.53#ibcon#read 3, iclass 20, count 0 2006.173.03:17:07.53#ibcon#about to read 4, iclass 20, count 0 2006.173.03:17:07.53#ibcon#read 4, iclass 20, count 0 2006.173.03:17:07.53#ibcon#about to read 5, iclass 20, count 0 2006.173.03:17:07.53#ibcon#read 5, iclass 20, count 0 2006.173.03:17:07.53#ibcon#about to read 6, iclass 20, count 0 2006.173.03:17:07.53#ibcon#read 6, iclass 20, count 0 2006.173.03:17:07.53#ibcon#end of sib2, iclass 20, count 0 2006.173.03:17:07.53#ibcon#*after write, iclass 20, count 0 2006.173.03:17:07.53#ibcon#*before return 0, iclass 20, count 0 2006.173.03:17:07.53#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.03:17:07.53#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.03:17:07.53#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.03:17:07.53#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.03:17:07.53$vck44/va=7,4 2006.173.03:17:07.53#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.03:17:07.53#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.03:17:07.53#ibcon#ireg 11 cls_cnt 2 2006.173.03:17:07.53#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.03:17:07.59#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.03:17:07.59#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.03:17:07.59#ibcon#enter wrdev, iclass 22, count 2 2006.173.03:17:07.59#ibcon#first serial, iclass 22, count 2 2006.173.03:17:07.59#ibcon#enter sib2, iclass 22, count 2 2006.173.03:17:07.59#ibcon#flushed, iclass 22, count 2 2006.173.03:17:07.59#ibcon#about to write, iclass 22, count 2 2006.173.03:17:07.59#ibcon#wrote, iclass 22, count 2 2006.173.03:17:07.59#ibcon#about to read 3, iclass 22, count 2 2006.173.03:17:07.61#ibcon#read 3, iclass 22, count 2 2006.173.03:17:07.61#ibcon#about to read 4, iclass 22, count 2 2006.173.03:17:07.61#ibcon#read 4, iclass 22, count 2 2006.173.03:17:07.61#ibcon#about to read 5, iclass 22, count 2 2006.173.03:17:07.61#ibcon#read 5, iclass 22, count 2 2006.173.03:17:07.61#ibcon#about to read 6, iclass 22, count 2 2006.173.03:17:07.61#ibcon#read 6, iclass 22, count 2 2006.173.03:17:07.61#ibcon#end of sib2, iclass 22, count 2 2006.173.03:17:07.61#ibcon#*mode == 0, iclass 22, count 2 2006.173.03:17:07.61#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.03:17:07.61#ibcon#[25=AT07-04\r\n] 2006.173.03:17:07.61#ibcon#*before write, iclass 22, count 2 2006.173.03:17:07.61#ibcon#enter sib2, iclass 22, count 2 2006.173.03:17:07.61#ibcon#flushed, iclass 22, count 2 2006.173.03:17:07.61#ibcon#about to write, iclass 22, count 2 2006.173.03:17:07.61#ibcon#wrote, iclass 22, count 2 2006.173.03:17:07.61#ibcon#about to read 3, iclass 22, count 2 2006.173.03:17:07.64#ibcon#read 3, iclass 22, count 2 2006.173.03:17:07.64#ibcon#about to read 4, iclass 22, count 2 2006.173.03:17:07.64#ibcon#read 4, iclass 22, count 2 2006.173.03:17:07.64#ibcon#about to read 5, iclass 22, count 2 2006.173.03:17:07.64#ibcon#read 5, iclass 22, count 2 2006.173.03:17:07.64#ibcon#about to read 6, iclass 22, count 2 2006.173.03:17:07.64#ibcon#read 6, iclass 22, count 2 2006.173.03:17:07.64#ibcon#end of sib2, iclass 22, count 2 2006.173.03:17:07.64#ibcon#*after write, iclass 22, count 2 2006.173.03:17:07.64#ibcon#*before return 0, iclass 22, count 2 2006.173.03:17:07.64#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.03:17:07.64#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.03:17:07.64#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.03:17:07.64#ibcon#ireg 7 cls_cnt 0 2006.173.03:17:07.64#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.03:17:07.76#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.03:17:07.76#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.03:17:07.76#ibcon#enter wrdev, iclass 22, count 0 2006.173.03:17:07.76#ibcon#first serial, iclass 22, count 0 2006.173.03:17:07.76#ibcon#enter sib2, iclass 22, count 0 2006.173.03:17:07.76#ibcon#flushed, iclass 22, count 0 2006.173.03:17:07.76#ibcon#about to write, iclass 22, count 0 2006.173.03:17:07.76#ibcon#wrote, iclass 22, count 0 2006.173.03:17:07.76#ibcon#about to read 3, iclass 22, count 0 2006.173.03:17:07.78#ibcon#read 3, iclass 22, count 0 2006.173.03:17:07.78#ibcon#about to read 4, iclass 22, count 0 2006.173.03:17:07.78#ibcon#read 4, iclass 22, count 0 2006.173.03:17:07.78#ibcon#about to read 5, iclass 22, count 0 2006.173.03:17:07.78#ibcon#read 5, iclass 22, count 0 2006.173.03:17:07.78#ibcon#about to read 6, iclass 22, count 0 2006.173.03:17:07.78#ibcon#read 6, iclass 22, count 0 2006.173.03:17:07.78#ibcon#end of sib2, iclass 22, count 0 2006.173.03:17:07.78#ibcon#*mode == 0, iclass 22, count 0 2006.173.03:17:07.78#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.03:17:07.78#ibcon#[25=USB\r\n] 2006.173.03:17:07.78#ibcon#*before write, iclass 22, count 0 2006.173.03:17:07.78#ibcon#enter sib2, iclass 22, count 0 2006.173.03:17:07.78#ibcon#flushed, iclass 22, count 0 2006.173.03:17:07.78#ibcon#about to write, iclass 22, count 0 2006.173.03:17:07.78#ibcon#wrote, iclass 22, count 0 2006.173.03:17:07.78#ibcon#about to read 3, iclass 22, count 0 2006.173.03:17:07.81#ibcon#read 3, iclass 22, count 0 2006.173.03:17:07.81#ibcon#about to read 4, iclass 22, count 0 2006.173.03:17:07.81#ibcon#read 4, iclass 22, count 0 2006.173.03:17:07.81#ibcon#about to read 5, iclass 22, count 0 2006.173.03:17:07.81#ibcon#read 5, iclass 22, count 0 2006.173.03:17:07.81#ibcon#about to read 6, iclass 22, count 0 2006.173.03:17:07.81#ibcon#read 6, iclass 22, count 0 2006.173.03:17:07.81#ibcon#end of sib2, iclass 22, count 0 2006.173.03:17:07.81#ibcon#*after write, iclass 22, count 0 2006.173.03:17:07.81#ibcon#*before return 0, iclass 22, count 0 2006.173.03:17:07.81#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.03:17:07.81#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.03:17:07.81#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.03:17:07.81#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.03:17:07.81$vck44/valo=8,884.99 2006.173.03:17:07.81#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.03:17:07.81#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.03:17:07.81#ibcon#ireg 17 cls_cnt 0 2006.173.03:17:07.81#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.03:17:07.81#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.03:17:07.81#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.03:17:07.81#ibcon#enter wrdev, iclass 24, count 0 2006.173.03:17:07.81#ibcon#first serial, iclass 24, count 0 2006.173.03:17:07.81#ibcon#enter sib2, iclass 24, count 0 2006.173.03:17:07.81#ibcon#flushed, iclass 24, count 0 2006.173.03:17:07.81#ibcon#about to write, iclass 24, count 0 2006.173.03:17:07.81#ibcon#wrote, iclass 24, count 0 2006.173.03:17:07.81#ibcon#about to read 3, iclass 24, count 0 2006.173.03:17:07.83#ibcon#read 3, iclass 24, count 0 2006.173.03:17:07.83#ibcon#about to read 4, iclass 24, count 0 2006.173.03:17:07.83#ibcon#read 4, iclass 24, count 0 2006.173.03:17:07.83#ibcon#about to read 5, iclass 24, count 0 2006.173.03:17:07.83#ibcon#read 5, iclass 24, count 0 2006.173.03:17:07.83#ibcon#about to read 6, iclass 24, count 0 2006.173.03:17:07.83#ibcon#read 6, iclass 24, count 0 2006.173.03:17:07.83#ibcon#end of sib2, iclass 24, count 0 2006.173.03:17:07.83#ibcon#*mode == 0, iclass 24, count 0 2006.173.03:17:07.83#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.03:17:07.83#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.03:17:07.83#ibcon#*before write, iclass 24, count 0 2006.173.03:17:07.83#ibcon#enter sib2, iclass 24, count 0 2006.173.03:17:07.83#ibcon#flushed, iclass 24, count 0 2006.173.03:17:07.83#ibcon#about to write, iclass 24, count 0 2006.173.03:17:07.83#ibcon#wrote, iclass 24, count 0 2006.173.03:17:07.83#ibcon#about to read 3, iclass 24, count 0 2006.173.03:17:07.87#ibcon#read 3, iclass 24, count 0 2006.173.03:17:07.87#ibcon#about to read 4, iclass 24, count 0 2006.173.03:17:07.87#ibcon#read 4, iclass 24, count 0 2006.173.03:17:07.87#ibcon#about to read 5, iclass 24, count 0 2006.173.03:17:07.87#ibcon#read 5, iclass 24, count 0 2006.173.03:17:07.87#ibcon#about to read 6, iclass 24, count 0 2006.173.03:17:07.87#ibcon#read 6, iclass 24, count 0 2006.173.03:17:07.87#ibcon#end of sib2, iclass 24, count 0 2006.173.03:17:07.87#ibcon#*after write, iclass 24, count 0 2006.173.03:17:07.87#ibcon#*before return 0, iclass 24, count 0 2006.173.03:17:07.87#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.03:17:07.87#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.03:17:07.87#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.03:17:07.87#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.03:17:07.87$vck44/va=8,4 2006.173.03:17:07.87#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.03:17:07.87#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.03:17:07.87#ibcon#ireg 11 cls_cnt 2 2006.173.03:17:07.87#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.03:17:07.93#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.03:17:07.93#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.03:17:07.93#ibcon#enter wrdev, iclass 26, count 2 2006.173.03:17:07.93#ibcon#first serial, iclass 26, count 2 2006.173.03:17:07.93#ibcon#enter sib2, iclass 26, count 2 2006.173.03:17:07.93#ibcon#flushed, iclass 26, count 2 2006.173.03:17:07.93#ibcon#about to write, iclass 26, count 2 2006.173.03:17:07.93#ibcon#wrote, iclass 26, count 2 2006.173.03:17:07.93#ibcon#about to read 3, iclass 26, count 2 2006.173.03:17:07.95#ibcon#read 3, iclass 26, count 2 2006.173.03:17:07.95#ibcon#about to read 4, iclass 26, count 2 2006.173.03:17:07.95#ibcon#read 4, iclass 26, count 2 2006.173.03:17:07.95#ibcon#about to read 5, iclass 26, count 2 2006.173.03:17:07.95#ibcon#read 5, iclass 26, count 2 2006.173.03:17:07.95#ibcon#about to read 6, iclass 26, count 2 2006.173.03:17:07.95#ibcon#read 6, iclass 26, count 2 2006.173.03:17:07.95#ibcon#end of sib2, iclass 26, count 2 2006.173.03:17:07.95#ibcon#*mode == 0, iclass 26, count 2 2006.173.03:17:07.95#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.03:17:07.95#ibcon#[25=AT08-04\r\n] 2006.173.03:17:07.95#ibcon#*before write, iclass 26, count 2 2006.173.03:17:07.95#ibcon#enter sib2, iclass 26, count 2 2006.173.03:17:07.95#ibcon#flushed, iclass 26, count 2 2006.173.03:17:07.95#ibcon#about to write, iclass 26, count 2 2006.173.03:17:07.95#ibcon#wrote, iclass 26, count 2 2006.173.03:17:07.95#ibcon#about to read 3, iclass 26, count 2 2006.173.03:17:07.98#ibcon#read 3, iclass 26, count 2 2006.173.03:17:07.98#ibcon#about to read 4, iclass 26, count 2 2006.173.03:17:07.98#ibcon#read 4, iclass 26, count 2 2006.173.03:17:07.98#ibcon#about to read 5, iclass 26, count 2 2006.173.03:17:07.98#ibcon#read 5, iclass 26, count 2 2006.173.03:17:07.98#ibcon#about to read 6, iclass 26, count 2 2006.173.03:17:07.98#ibcon#read 6, iclass 26, count 2 2006.173.03:17:07.98#ibcon#end of sib2, iclass 26, count 2 2006.173.03:17:07.98#ibcon#*after write, iclass 26, count 2 2006.173.03:17:07.98#ibcon#*before return 0, iclass 26, count 2 2006.173.03:17:07.98#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.03:17:07.98#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.03:17:07.98#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.03:17:07.98#ibcon#ireg 7 cls_cnt 0 2006.173.03:17:07.98#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.03:17:08.10#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.03:17:08.10#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.03:17:08.10#ibcon#enter wrdev, iclass 26, count 0 2006.173.03:17:08.10#ibcon#first serial, iclass 26, count 0 2006.173.03:17:08.10#ibcon#enter sib2, iclass 26, count 0 2006.173.03:17:08.10#ibcon#flushed, iclass 26, count 0 2006.173.03:17:08.10#ibcon#about to write, iclass 26, count 0 2006.173.03:17:08.10#ibcon#wrote, iclass 26, count 0 2006.173.03:17:08.10#ibcon#about to read 3, iclass 26, count 0 2006.173.03:17:08.12#ibcon#read 3, iclass 26, count 0 2006.173.03:17:08.12#ibcon#about to read 4, iclass 26, count 0 2006.173.03:17:08.12#ibcon#read 4, iclass 26, count 0 2006.173.03:17:08.12#ibcon#about to read 5, iclass 26, count 0 2006.173.03:17:08.12#ibcon#read 5, iclass 26, count 0 2006.173.03:17:08.12#ibcon#about to read 6, iclass 26, count 0 2006.173.03:17:08.12#ibcon#read 6, iclass 26, count 0 2006.173.03:17:08.12#ibcon#end of sib2, iclass 26, count 0 2006.173.03:17:08.12#ibcon#*mode == 0, iclass 26, count 0 2006.173.03:17:08.12#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.03:17:08.12#ibcon#[25=USB\r\n] 2006.173.03:17:08.12#ibcon#*before write, iclass 26, count 0 2006.173.03:17:08.12#ibcon#enter sib2, iclass 26, count 0 2006.173.03:17:08.12#ibcon#flushed, iclass 26, count 0 2006.173.03:17:08.12#ibcon#about to write, iclass 26, count 0 2006.173.03:17:08.12#ibcon#wrote, iclass 26, count 0 2006.173.03:17:08.12#ibcon#about to read 3, iclass 26, count 0 2006.173.03:17:08.15#ibcon#read 3, iclass 26, count 0 2006.173.03:17:08.15#ibcon#about to read 4, iclass 26, count 0 2006.173.03:17:08.15#ibcon#read 4, iclass 26, count 0 2006.173.03:17:08.15#ibcon#about to read 5, iclass 26, count 0 2006.173.03:17:08.15#ibcon#read 5, iclass 26, count 0 2006.173.03:17:08.15#ibcon#about to read 6, iclass 26, count 0 2006.173.03:17:08.15#ibcon#read 6, iclass 26, count 0 2006.173.03:17:08.15#ibcon#end of sib2, iclass 26, count 0 2006.173.03:17:08.15#ibcon#*after write, iclass 26, count 0 2006.173.03:17:08.15#ibcon#*before return 0, iclass 26, count 0 2006.173.03:17:08.15#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.03:17:08.15#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.03:17:08.15#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.03:17:08.15#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.03:17:08.15$vck44/vblo=1,629.99 2006.173.03:17:08.15#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.03:17:08.15#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.03:17:08.15#ibcon#ireg 17 cls_cnt 0 2006.173.03:17:08.15#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.03:17:08.15#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.03:17:08.15#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.03:17:08.15#ibcon#enter wrdev, iclass 28, count 0 2006.173.03:17:08.15#ibcon#first serial, iclass 28, count 0 2006.173.03:17:08.15#ibcon#enter sib2, iclass 28, count 0 2006.173.03:17:08.15#ibcon#flushed, iclass 28, count 0 2006.173.03:17:08.15#ibcon#about to write, iclass 28, count 0 2006.173.03:17:08.15#ibcon#wrote, iclass 28, count 0 2006.173.03:17:08.15#ibcon#about to read 3, iclass 28, count 0 2006.173.03:17:08.17#ibcon#read 3, iclass 28, count 0 2006.173.03:17:08.17#ibcon#about to read 4, iclass 28, count 0 2006.173.03:17:08.17#ibcon#read 4, iclass 28, count 0 2006.173.03:17:08.17#ibcon#about to read 5, iclass 28, count 0 2006.173.03:17:08.17#ibcon#read 5, iclass 28, count 0 2006.173.03:17:08.17#ibcon#about to read 6, iclass 28, count 0 2006.173.03:17:08.17#ibcon#read 6, iclass 28, count 0 2006.173.03:17:08.17#ibcon#end of sib2, iclass 28, count 0 2006.173.03:17:08.17#ibcon#*mode == 0, iclass 28, count 0 2006.173.03:17:08.17#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.03:17:08.17#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.03:17:08.17#ibcon#*before write, iclass 28, count 0 2006.173.03:17:08.17#ibcon#enter sib2, iclass 28, count 0 2006.173.03:17:08.17#ibcon#flushed, iclass 28, count 0 2006.173.03:17:08.17#ibcon#about to write, iclass 28, count 0 2006.173.03:17:08.17#ibcon#wrote, iclass 28, count 0 2006.173.03:17:08.17#ibcon#about to read 3, iclass 28, count 0 2006.173.03:17:08.21#ibcon#read 3, iclass 28, count 0 2006.173.03:17:08.21#ibcon#about to read 4, iclass 28, count 0 2006.173.03:17:08.21#ibcon#read 4, iclass 28, count 0 2006.173.03:17:08.21#ibcon#about to read 5, iclass 28, count 0 2006.173.03:17:08.21#ibcon#read 5, iclass 28, count 0 2006.173.03:17:08.21#ibcon#about to read 6, iclass 28, count 0 2006.173.03:17:08.21#ibcon#read 6, iclass 28, count 0 2006.173.03:17:08.21#ibcon#end of sib2, iclass 28, count 0 2006.173.03:17:08.21#ibcon#*after write, iclass 28, count 0 2006.173.03:17:08.21#ibcon#*before return 0, iclass 28, count 0 2006.173.03:17:08.21#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.03:17:08.21#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.03:17:08.21#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.03:17:08.21#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.03:17:08.21$vck44/vb=1,4 2006.173.03:17:08.21#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.03:17:08.21#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.03:17:08.21#ibcon#ireg 11 cls_cnt 2 2006.173.03:17:08.21#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.03:17:08.21#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.03:17:08.21#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.03:17:08.21#ibcon#enter wrdev, iclass 30, count 2 2006.173.03:17:08.21#ibcon#first serial, iclass 30, count 2 2006.173.03:17:08.21#ibcon#enter sib2, iclass 30, count 2 2006.173.03:17:08.21#ibcon#flushed, iclass 30, count 2 2006.173.03:17:08.21#ibcon#about to write, iclass 30, count 2 2006.173.03:17:08.21#ibcon#wrote, iclass 30, count 2 2006.173.03:17:08.21#ibcon#about to read 3, iclass 30, count 2 2006.173.03:17:08.23#ibcon#read 3, iclass 30, count 2 2006.173.03:17:08.23#ibcon#about to read 4, iclass 30, count 2 2006.173.03:17:08.23#ibcon#read 4, iclass 30, count 2 2006.173.03:17:08.23#ibcon#about to read 5, iclass 30, count 2 2006.173.03:17:08.23#ibcon#read 5, iclass 30, count 2 2006.173.03:17:08.23#ibcon#about to read 6, iclass 30, count 2 2006.173.03:17:08.23#ibcon#read 6, iclass 30, count 2 2006.173.03:17:08.23#ibcon#end of sib2, iclass 30, count 2 2006.173.03:17:08.23#ibcon#*mode == 0, iclass 30, count 2 2006.173.03:17:08.23#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.03:17:08.23#ibcon#[27=AT01-04\r\n] 2006.173.03:17:08.23#ibcon#*before write, iclass 30, count 2 2006.173.03:17:08.23#ibcon#enter sib2, iclass 30, count 2 2006.173.03:17:08.23#ibcon#flushed, iclass 30, count 2 2006.173.03:17:08.23#ibcon#about to write, iclass 30, count 2 2006.173.03:17:08.23#ibcon#wrote, iclass 30, count 2 2006.173.03:17:08.23#ibcon#about to read 3, iclass 30, count 2 2006.173.03:17:08.26#ibcon#read 3, iclass 30, count 2 2006.173.03:17:08.26#ibcon#about to read 4, iclass 30, count 2 2006.173.03:17:08.26#ibcon#read 4, iclass 30, count 2 2006.173.03:17:08.26#ibcon#about to read 5, iclass 30, count 2 2006.173.03:17:08.26#ibcon#read 5, iclass 30, count 2 2006.173.03:17:08.26#ibcon#about to read 6, iclass 30, count 2 2006.173.03:17:08.26#ibcon#read 6, iclass 30, count 2 2006.173.03:17:08.26#ibcon#end of sib2, iclass 30, count 2 2006.173.03:17:08.26#ibcon#*after write, iclass 30, count 2 2006.173.03:17:08.26#ibcon#*before return 0, iclass 30, count 2 2006.173.03:17:08.26#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.03:17:08.26#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.03:17:08.26#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.03:17:08.26#ibcon#ireg 7 cls_cnt 0 2006.173.03:17:08.26#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.03:17:08.38#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.03:17:08.38#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.03:17:08.38#ibcon#enter wrdev, iclass 30, count 0 2006.173.03:17:08.38#ibcon#first serial, iclass 30, count 0 2006.173.03:17:08.38#ibcon#enter sib2, iclass 30, count 0 2006.173.03:17:08.38#ibcon#flushed, iclass 30, count 0 2006.173.03:17:08.38#ibcon#about to write, iclass 30, count 0 2006.173.03:17:08.38#ibcon#wrote, iclass 30, count 0 2006.173.03:17:08.38#ibcon#about to read 3, iclass 30, count 0 2006.173.03:17:08.40#ibcon#read 3, iclass 30, count 0 2006.173.03:17:08.40#ibcon#about to read 4, iclass 30, count 0 2006.173.03:17:08.40#ibcon#read 4, iclass 30, count 0 2006.173.03:17:08.40#ibcon#about to read 5, iclass 30, count 0 2006.173.03:17:08.40#ibcon#read 5, iclass 30, count 0 2006.173.03:17:08.40#ibcon#about to read 6, iclass 30, count 0 2006.173.03:17:08.40#ibcon#read 6, iclass 30, count 0 2006.173.03:17:08.40#ibcon#end of sib2, iclass 30, count 0 2006.173.03:17:08.40#ibcon#*mode == 0, iclass 30, count 0 2006.173.03:17:08.40#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.03:17:08.40#ibcon#[27=USB\r\n] 2006.173.03:17:08.40#ibcon#*before write, iclass 30, count 0 2006.173.03:17:08.40#ibcon#enter sib2, iclass 30, count 0 2006.173.03:17:08.40#ibcon#flushed, iclass 30, count 0 2006.173.03:17:08.40#ibcon#about to write, iclass 30, count 0 2006.173.03:17:08.40#ibcon#wrote, iclass 30, count 0 2006.173.03:17:08.40#ibcon#about to read 3, iclass 30, count 0 2006.173.03:17:08.43#ibcon#read 3, iclass 30, count 0 2006.173.03:17:08.43#ibcon#about to read 4, iclass 30, count 0 2006.173.03:17:08.43#ibcon#read 4, iclass 30, count 0 2006.173.03:17:08.43#ibcon#about to read 5, iclass 30, count 0 2006.173.03:17:08.43#ibcon#read 5, iclass 30, count 0 2006.173.03:17:08.43#ibcon#about to read 6, iclass 30, count 0 2006.173.03:17:08.43#ibcon#read 6, iclass 30, count 0 2006.173.03:17:08.43#ibcon#end of sib2, iclass 30, count 0 2006.173.03:17:08.43#ibcon#*after write, iclass 30, count 0 2006.173.03:17:08.43#ibcon#*before return 0, iclass 30, count 0 2006.173.03:17:08.43#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.03:17:08.43#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.03:17:08.43#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.03:17:08.43#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.03:17:08.43$vck44/vblo=2,634.99 2006.173.03:17:08.43#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.03:17:08.43#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.03:17:08.43#ibcon#ireg 17 cls_cnt 0 2006.173.03:17:08.43#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.03:17:08.43#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.03:17:08.43#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.03:17:08.43#ibcon#enter wrdev, iclass 32, count 0 2006.173.03:17:08.43#ibcon#first serial, iclass 32, count 0 2006.173.03:17:08.43#ibcon#enter sib2, iclass 32, count 0 2006.173.03:17:08.43#ibcon#flushed, iclass 32, count 0 2006.173.03:17:08.43#ibcon#about to write, iclass 32, count 0 2006.173.03:17:08.43#ibcon#wrote, iclass 32, count 0 2006.173.03:17:08.43#ibcon#about to read 3, iclass 32, count 0 2006.173.03:17:08.45#ibcon#read 3, iclass 32, count 0 2006.173.03:17:08.45#ibcon#about to read 4, iclass 32, count 0 2006.173.03:17:08.45#ibcon#read 4, iclass 32, count 0 2006.173.03:17:08.45#ibcon#about to read 5, iclass 32, count 0 2006.173.03:17:08.45#ibcon#read 5, iclass 32, count 0 2006.173.03:17:08.45#ibcon#about to read 6, iclass 32, count 0 2006.173.03:17:08.45#ibcon#read 6, iclass 32, count 0 2006.173.03:17:08.45#ibcon#end of sib2, iclass 32, count 0 2006.173.03:17:08.45#ibcon#*mode == 0, iclass 32, count 0 2006.173.03:17:08.45#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.03:17:08.45#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.03:17:08.45#ibcon#*before write, iclass 32, count 0 2006.173.03:17:08.45#ibcon#enter sib2, iclass 32, count 0 2006.173.03:17:08.45#ibcon#flushed, iclass 32, count 0 2006.173.03:17:08.45#ibcon#about to write, iclass 32, count 0 2006.173.03:17:08.45#ibcon#wrote, iclass 32, count 0 2006.173.03:17:08.45#ibcon#about to read 3, iclass 32, count 0 2006.173.03:17:08.49#ibcon#read 3, iclass 32, count 0 2006.173.03:17:08.49#ibcon#about to read 4, iclass 32, count 0 2006.173.03:17:08.49#ibcon#read 4, iclass 32, count 0 2006.173.03:17:08.49#ibcon#about to read 5, iclass 32, count 0 2006.173.03:17:08.49#ibcon#read 5, iclass 32, count 0 2006.173.03:17:08.49#ibcon#about to read 6, iclass 32, count 0 2006.173.03:17:08.49#ibcon#read 6, iclass 32, count 0 2006.173.03:17:08.49#ibcon#end of sib2, iclass 32, count 0 2006.173.03:17:08.49#ibcon#*after write, iclass 32, count 0 2006.173.03:17:08.49#ibcon#*before return 0, iclass 32, count 0 2006.173.03:17:08.49#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.03:17:08.49#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.03:17:08.49#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.03:17:08.49#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.03:17:08.49$vck44/vb=2,4 2006.173.03:17:08.49#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.03:17:08.49#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.03:17:08.49#ibcon#ireg 11 cls_cnt 2 2006.173.03:17:08.49#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.03:17:08.55#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.03:17:08.55#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.03:17:08.55#ibcon#enter wrdev, iclass 34, count 2 2006.173.03:17:08.55#ibcon#first serial, iclass 34, count 2 2006.173.03:17:08.55#ibcon#enter sib2, iclass 34, count 2 2006.173.03:17:08.55#ibcon#flushed, iclass 34, count 2 2006.173.03:17:08.55#ibcon#about to write, iclass 34, count 2 2006.173.03:17:08.55#ibcon#wrote, iclass 34, count 2 2006.173.03:17:08.55#ibcon#about to read 3, iclass 34, count 2 2006.173.03:17:08.57#ibcon#read 3, iclass 34, count 2 2006.173.03:17:08.57#ibcon#about to read 4, iclass 34, count 2 2006.173.03:17:08.57#ibcon#read 4, iclass 34, count 2 2006.173.03:17:08.57#ibcon#about to read 5, iclass 34, count 2 2006.173.03:17:08.57#ibcon#read 5, iclass 34, count 2 2006.173.03:17:08.57#ibcon#about to read 6, iclass 34, count 2 2006.173.03:17:08.57#ibcon#read 6, iclass 34, count 2 2006.173.03:17:08.57#ibcon#end of sib2, iclass 34, count 2 2006.173.03:17:08.57#ibcon#*mode == 0, iclass 34, count 2 2006.173.03:17:08.57#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.03:17:08.57#ibcon#[27=AT02-04\r\n] 2006.173.03:17:08.57#ibcon#*before write, iclass 34, count 2 2006.173.03:17:08.57#ibcon#enter sib2, iclass 34, count 2 2006.173.03:17:08.57#ibcon#flushed, iclass 34, count 2 2006.173.03:17:08.57#ibcon#about to write, iclass 34, count 2 2006.173.03:17:08.57#ibcon#wrote, iclass 34, count 2 2006.173.03:17:08.57#ibcon#about to read 3, iclass 34, count 2 2006.173.03:17:08.60#ibcon#read 3, iclass 34, count 2 2006.173.03:17:08.60#ibcon#about to read 4, iclass 34, count 2 2006.173.03:17:08.60#ibcon#read 4, iclass 34, count 2 2006.173.03:17:08.60#ibcon#about to read 5, iclass 34, count 2 2006.173.03:17:08.60#ibcon#read 5, iclass 34, count 2 2006.173.03:17:08.60#ibcon#about to read 6, iclass 34, count 2 2006.173.03:17:08.60#ibcon#read 6, iclass 34, count 2 2006.173.03:17:08.60#ibcon#end of sib2, iclass 34, count 2 2006.173.03:17:08.60#ibcon#*after write, iclass 34, count 2 2006.173.03:17:08.60#ibcon#*before return 0, iclass 34, count 2 2006.173.03:17:08.60#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.03:17:08.60#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.03:17:08.60#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.03:17:08.60#ibcon#ireg 7 cls_cnt 0 2006.173.03:17:08.60#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.03:17:08.72#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.03:17:08.72#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.03:17:08.72#ibcon#enter wrdev, iclass 34, count 0 2006.173.03:17:08.72#ibcon#first serial, iclass 34, count 0 2006.173.03:17:08.72#ibcon#enter sib2, iclass 34, count 0 2006.173.03:17:08.72#ibcon#flushed, iclass 34, count 0 2006.173.03:17:08.72#ibcon#about to write, iclass 34, count 0 2006.173.03:17:08.72#ibcon#wrote, iclass 34, count 0 2006.173.03:17:08.72#ibcon#about to read 3, iclass 34, count 0 2006.173.03:17:08.74#ibcon#read 3, iclass 34, count 0 2006.173.03:17:08.74#ibcon#about to read 4, iclass 34, count 0 2006.173.03:17:08.74#ibcon#read 4, iclass 34, count 0 2006.173.03:17:08.74#ibcon#about to read 5, iclass 34, count 0 2006.173.03:17:08.74#ibcon#read 5, iclass 34, count 0 2006.173.03:17:08.74#ibcon#about to read 6, iclass 34, count 0 2006.173.03:17:08.74#ibcon#read 6, iclass 34, count 0 2006.173.03:17:08.74#ibcon#end of sib2, iclass 34, count 0 2006.173.03:17:08.74#ibcon#*mode == 0, iclass 34, count 0 2006.173.03:17:08.74#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.03:17:08.74#ibcon#[27=USB\r\n] 2006.173.03:17:08.74#ibcon#*before write, iclass 34, count 0 2006.173.03:17:08.74#ibcon#enter sib2, iclass 34, count 0 2006.173.03:17:08.74#ibcon#flushed, iclass 34, count 0 2006.173.03:17:08.74#ibcon#about to write, iclass 34, count 0 2006.173.03:17:08.74#ibcon#wrote, iclass 34, count 0 2006.173.03:17:08.74#ibcon#about to read 3, iclass 34, count 0 2006.173.03:17:08.77#ibcon#read 3, iclass 34, count 0 2006.173.03:17:08.77#ibcon#about to read 4, iclass 34, count 0 2006.173.03:17:08.77#ibcon#read 4, iclass 34, count 0 2006.173.03:17:08.77#ibcon#about to read 5, iclass 34, count 0 2006.173.03:17:08.77#ibcon#read 5, iclass 34, count 0 2006.173.03:17:08.77#ibcon#about to read 6, iclass 34, count 0 2006.173.03:17:08.77#ibcon#read 6, iclass 34, count 0 2006.173.03:17:08.77#ibcon#end of sib2, iclass 34, count 0 2006.173.03:17:08.77#ibcon#*after write, iclass 34, count 0 2006.173.03:17:08.77#ibcon#*before return 0, iclass 34, count 0 2006.173.03:17:08.77#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.03:17:08.77#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.03:17:08.77#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.03:17:08.77#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.03:17:08.77$vck44/vblo=3,649.99 2006.173.03:17:08.77#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.03:17:08.77#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.03:17:08.77#ibcon#ireg 17 cls_cnt 0 2006.173.03:17:08.77#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.03:17:08.77#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.03:17:08.77#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.03:17:08.77#ibcon#enter wrdev, iclass 36, count 0 2006.173.03:17:08.77#ibcon#first serial, iclass 36, count 0 2006.173.03:17:08.77#ibcon#enter sib2, iclass 36, count 0 2006.173.03:17:08.77#ibcon#flushed, iclass 36, count 0 2006.173.03:17:08.77#ibcon#about to write, iclass 36, count 0 2006.173.03:17:08.77#ibcon#wrote, iclass 36, count 0 2006.173.03:17:08.77#ibcon#about to read 3, iclass 36, count 0 2006.173.03:17:08.79#ibcon#read 3, iclass 36, count 0 2006.173.03:17:08.79#ibcon#about to read 4, iclass 36, count 0 2006.173.03:17:08.79#ibcon#read 4, iclass 36, count 0 2006.173.03:17:08.79#ibcon#about to read 5, iclass 36, count 0 2006.173.03:17:08.79#ibcon#read 5, iclass 36, count 0 2006.173.03:17:08.79#ibcon#about to read 6, iclass 36, count 0 2006.173.03:17:08.79#ibcon#read 6, iclass 36, count 0 2006.173.03:17:08.79#ibcon#end of sib2, iclass 36, count 0 2006.173.03:17:08.79#ibcon#*mode == 0, iclass 36, count 0 2006.173.03:17:08.79#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.03:17:08.79#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.03:17:08.79#ibcon#*before write, iclass 36, count 0 2006.173.03:17:08.79#ibcon#enter sib2, iclass 36, count 0 2006.173.03:17:08.79#ibcon#flushed, iclass 36, count 0 2006.173.03:17:08.79#ibcon#about to write, iclass 36, count 0 2006.173.03:17:08.79#ibcon#wrote, iclass 36, count 0 2006.173.03:17:08.79#ibcon#about to read 3, iclass 36, count 0 2006.173.03:17:08.83#ibcon#read 3, iclass 36, count 0 2006.173.03:17:08.83#ibcon#about to read 4, iclass 36, count 0 2006.173.03:17:08.83#ibcon#read 4, iclass 36, count 0 2006.173.03:17:08.83#ibcon#about to read 5, iclass 36, count 0 2006.173.03:17:08.83#ibcon#read 5, iclass 36, count 0 2006.173.03:17:08.83#ibcon#about to read 6, iclass 36, count 0 2006.173.03:17:08.83#ibcon#read 6, iclass 36, count 0 2006.173.03:17:08.83#ibcon#end of sib2, iclass 36, count 0 2006.173.03:17:08.83#ibcon#*after write, iclass 36, count 0 2006.173.03:17:08.83#ibcon#*before return 0, iclass 36, count 0 2006.173.03:17:08.83#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.03:17:08.83#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.03:17:08.83#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.03:17:08.83#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.03:17:08.83$vck44/vb=3,4 2006.173.03:17:08.83#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.03:17:08.83#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.03:17:08.83#ibcon#ireg 11 cls_cnt 2 2006.173.03:17:08.83#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.03:17:08.89#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.03:17:08.89#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.03:17:08.89#ibcon#enter wrdev, iclass 38, count 2 2006.173.03:17:08.89#ibcon#first serial, iclass 38, count 2 2006.173.03:17:08.89#ibcon#enter sib2, iclass 38, count 2 2006.173.03:17:08.89#ibcon#flushed, iclass 38, count 2 2006.173.03:17:08.89#ibcon#about to write, iclass 38, count 2 2006.173.03:17:08.89#ibcon#wrote, iclass 38, count 2 2006.173.03:17:08.89#ibcon#about to read 3, iclass 38, count 2 2006.173.03:17:08.91#ibcon#read 3, iclass 38, count 2 2006.173.03:17:08.91#ibcon#about to read 4, iclass 38, count 2 2006.173.03:17:08.91#ibcon#read 4, iclass 38, count 2 2006.173.03:17:08.91#ibcon#about to read 5, iclass 38, count 2 2006.173.03:17:08.91#ibcon#read 5, iclass 38, count 2 2006.173.03:17:08.91#ibcon#about to read 6, iclass 38, count 2 2006.173.03:17:08.91#ibcon#read 6, iclass 38, count 2 2006.173.03:17:08.91#ibcon#end of sib2, iclass 38, count 2 2006.173.03:17:08.91#ibcon#*mode == 0, iclass 38, count 2 2006.173.03:17:08.91#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.03:17:08.91#ibcon#[27=AT03-04\r\n] 2006.173.03:17:08.91#ibcon#*before write, iclass 38, count 2 2006.173.03:17:08.91#ibcon#enter sib2, iclass 38, count 2 2006.173.03:17:08.91#ibcon#flushed, iclass 38, count 2 2006.173.03:17:08.91#ibcon#about to write, iclass 38, count 2 2006.173.03:17:08.91#ibcon#wrote, iclass 38, count 2 2006.173.03:17:08.91#ibcon#about to read 3, iclass 38, count 2 2006.173.03:17:08.94#ibcon#read 3, iclass 38, count 2 2006.173.03:17:08.94#ibcon#about to read 4, iclass 38, count 2 2006.173.03:17:08.94#ibcon#read 4, iclass 38, count 2 2006.173.03:17:08.94#ibcon#about to read 5, iclass 38, count 2 2006.173.03:17:08.94#ibcon#read 5, iclass 38, count 2 2006.173.03:17:08.94#ibcon#about to read 6, iclass 38, count 2 2006.173.03:17:08.94#ibcon#read 6, iclass 38, count 2 2006.173.03:17:08.94#ibcon#end of sib2, iclass 38, count 2 2006.173.03:17:08.94#ibcon#*after write, iclass 38, count 2 2006.173.03:17:08.94#ibcon#*before return 0, iclass 38, count 2 2006.173.03:17:08.94#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.03:17:08.94#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.03:17:08.94#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.03:17:08.94#ibcon#ireg 7 cls_cnt 0 2006.173.03:17:08.94#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.03:17:09.06#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.03:17:09.06#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.03:17:09.06#ibcon#enter wrdev, iclass 38, count 0 2006.173.03:17:09.06#ibcon#first serial, iclass 38, count 0 2006.173.03:17:09.06#ibcon#enter sib2, iclass 38, count 0 2006.173.03:17:09.06#ibcon#flushed, iclass 38, count 0 2006.173.03:17:09.06#ibcon#about to write, iclass 38, count 0 2006.173.03:17:09.06#ibcon#wrote, iclass 38, count 0 2006.173.03:17:09.06#ibcon#about to read 3, iclass 38, count 0 2006.173.03:17:09.08#ibcon#read 3, iclass 38, count 0 2006.173.03:17:09.08#ibcon#about to read 4, iclass 38, count 0 2006.173.03:17:09.08#ibcon#read 4, iclass 38, count 0 2006.173.03:17:09.08#ibcon#about to read 5, iclass 38, count 0 2006.173.03:17:09.08#ibcon#read 5, iclass 38, count 0 2006.173.03:17:09.08#ibcon#about to read 6, iclass 38, count 0 2006.173.03:17:09.08#ibcon#read 6, iclass 38, count 0 2006.173.03:17:09.08#ibcon#end of sib2, iclass 38, count 0 2006.173.03:17:09.08#ibcon#*mode == 0, iclass 38, count 0 2006.173.03:17:09.08#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.03:17:09.08#ibcon#[27=USB\r\n] 2006.173.03:17:09.08#ibcon#*before write, iclass 38, count 0 2006.173.03:17:09.08#ibcon#enter sib2, iclass 38, count 0 2006.173.03:17:09.08#ibcon#flushed, iclass 38, count 0 2006.173.03:17:09.08#ibcon#about to write, iclass 38, count 0 2006.173.03:17:09.08#ibcon#wrote, iclass 38, count 0 2006.173.03:17:09.08#ibcon#about to read 3, iclass 38, count 0 2006.173.03:17:09.11#ibcon#read 3, iclass 38, count 0 2006.173.03:17:09.11#ibcon#about to read 4, iclass 38, count 0 2006.173.03:17:09.11#ibcon#read 4, iclass 38, count 0 2006.173.03:17:09.11#ibcon#about to read 5, iclass 38, count 0 2006.173.03:17:09.11#ibcon#read 5, iclass 38, count 0 2006.173.03:17:09.11#ibcon#about to read 6, iclass 38, count 0 2006.173.03:17:09.11#ibcon#read 6, iclass 38, count 0 2006.173.03:17:09.11#ibcon#end of sib2, iclass 38, count 0 2006.173.03:17:09.11#ibcon#*after write, iclass 38, count 0 2006.173.03:17:09.11#ibcon#*before return 0, iclass 38, count 0 2006.173.03:17:09.11#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.03:17:09.11#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.03:17:09.11#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.03:17:09.11#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.03:17:09.11$vck44/vblo=4,679.99 2006.173.03:17:09.11#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.03:17:09.11#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.03:17:09.11#ibcon#ireg 17 cls_cnt 0 2006.173.03:17:09.11#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.03:17:09.11#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.03:17:09.11#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.03:17:09.11#ibcon#enter wrdev, iclass 40, count 0 2006.173.03:17:09.11#ibcon#first serial, iclass 40, count 0 2006.173.03:17:09.11#ibcon#enter sib2, iclass 40, count 0 2006.173.03:17:09.11#ibcon#flushed, iclass 40, count 0 2006.173.03:17:09.11#ibcon#about to write, iclass 40, count 0 2006.173.03:17:09.11#ibcon#wrote, iclass 40, count 0 2006.173.03:17:09.11#ibcon#about to read 3, iclass 40, count 0 2006.173.03:17:09.13#ibcon#read 3, iclass 40, count 0 2006.173.03:17:09.13#ibcon#about to read 4, iclass 40, count 0 2006.173.03:17:09.13#ibcon#read 4, iclass 40, count 0 2006.173.03:17:09.13#ibcon#about to read 5, iclass 40, count 0 2006.173.03:17:09.13#ibcon#read 5, iclass 40, count 0 2006.173.03:17:09.13#ibcon#about to read 6, iclass 40, count 0 2006.173.03:17:09.13#ibcon#read 6, iclass 40, count 0 2006.173.03:17:09.13#ibcon#end of sib2, iclass 40, count 0 2006.173.03:17:09.13#ibcon#*mode == 0, iclass 40, count 0 2006.173.03:17:09.13#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.03:17:09.13#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.03:17:09.13#ibcon#*before write, iclass 40, count 0 2006.173.03:17:09.13#ibcon#enter sib2, iclass 40, count 0 2006.173.03:17:09.13#ibcon#flushed, iclass 40, count 0 2006.173.03:17:09.13#ibcon#about to write, iclass 40, count 0 2006.173.03:17:09.13#ibcon#wrote, iclass 40, count 0 2006.173.03:17:09.13#ibcon#about to read 3, iclass 40, count 0 2006.173.03:17:09.17#ibcon#read 3, iclass 40, count 0 2006.173.03:17:09.17#ibcon#about to read 4, iclass 40, count 0 2006.173.03:17:09.17#ibcon#read 4, iclass 40, count 0 2006.173.03:17:09.17#ibcon#about to read 5, iclass 40, count 0 2006.173.03:17:09.17#ibcon#read 5, iclass 40, count 0 2006.173.03:17:09.17#ibcon#about to read 6, iclass 40, count 0 2006.173.03:17:09.17#ibcon#read 6, iclass 40, count 0 2006.173.03:17:09.17#ibcon#end of sib2, iclass 40, count 0 2006.173.03:17:09.17#ibcon#*after write, iclass 40, count 0 2006.173.03:17:09.17#ibcon#*before return 0, iclass 40, count 0 2006.173.03:17:09.17#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.03:17:09.17#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.03:17:09.17#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.03:17:09.17#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.03:17:09.17$vck44/vb=4,4 2006.173.03:17:09.17#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.03:17:09.17#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.03:17:09.17#ibcon#ireg 11 cls_cnt 2 2006.173.03:17:09.17#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.03:17:09.23#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.03:17:09.23#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.03:17:09.23#ibcon#enter wrdev, iclass 4, count 2 2006.173.03:17:09.23#ibcon#first serial, iclass 4, count 2 2006.173.03:17:09.23#ibcon#enter sib2, iclass 4, count 2 2006.173.03:17:09.23#ibcon#flushed, iclass 4, count 2 2006.173.03:17:09.23#ibcon#about to write, iclass 4, count 2 2006.173.03:17:09.23#ibcon#wrote, iclass 4, count 2 2006.173.03:17:09.23#ibcon#about to read 3, iclass 4, count 2 2006.173.03:17:09.25#ibcon#read 3, iclass 4, count 2 2006.173.03:17:09.25#ibcon#about to read 4, iclass 4, count 2 2006.173.03:17:09.25#ibcon#read 4, iclass 4, count 2 2006.173.03:17:09.25#ibcon#about to read 5, iclass 4, count 2 2006.173.03:17:09.25#ibcon#read 5, iclass 4, count 2 2006.173.03:17:09.25#ibcon#about to read 6, iclass 4, count 2 2006.173.03:17:09.25#ibcon#read 6, iclass 4, count 2 2006.173.03:17:09.25#ibcon#end of sib2, iclass 4, count 2 2006.173.03:17:09.25#ibcon#*mode == 0, iclass 4, count 2 2006.173.03:17:09.25#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.03:17:09.25#ibcon#[27=AT04-04\r\n] 2006.173.03:17:09.25#ibcon#*before write, iclass 4, count 2 2006.173.03:17:09.25#ibcon#enter sib2, iclass 4, count 2 2006.173.03:17:09.25#ibcon#flushed, iclass 4, count 2 2006.173.03:17:09.25#ibcon#about to write, iclass 4, count 2 2006.173.03:17:09.25#ibcon#wrote, iclass 4, count 2 2006.173.03:17:09.25#ibcon#about to read 3, iclass 4, count 2 2006.173.03:17:09.28#ibcon#read 3, iclass 4, count 2 2006.173.03:17:09.28#ibcon#about to read 4, iclass 4, count 2 2006.173.03:17:09.28#ibcon#read 4, iclass 4, count 2 2006.173.03:17:09.28#ibcon#about to read 5, iclass 4, count 2 2006.173.03:17:09.28#ibcon#read 5, iclass 4, count 2 2006.173.03:17:09.28#ibcon#about to read 6, iclass 4, count 2 2006.173.03:17:09.28#ibcon#read 6, iclass 4, count 2 2006.173.03:17:09.28#ibcon#end of sib2, iclass 4, count 2 2006.173.03:17:09.28#ibcon#*after write, iclass 4, count 2 2006.173.03:17:09.28#ibcon#*before return 0, iclass 4, count 2 2006.173.03:17:09.28#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.03:17:09.28#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.03:17:09.28#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.03:17:09.28#ibcon#ireg 7 cls_cnt 0 2006.173.03:17:09.28#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.03:17:09.40#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.03:17:09.40#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.03:17:09.40#ibcon#enter wrdev, iclass 4, count 0 2006.173.03:17:09.40#ibcon#first serial, iclass 4, count 0 2006.173.03:17:09.40#ibcon#enter sib2, iclass 4, count 0 2006.173.03:17:09.40#ibcon#flushed, iclass 4, count 0 2006.173.03:17:09.40#ibcon#about to write, iclass 4, count 0 2006.173.03:17:09.40#ibcon#wrote, iclass 4, count 0 2006.173.03:17:09.40#ibcon#about to read 3, iclass 4, count 0 2006.173.03:17:09.42#ibcon#read 3, iclass 4, count 0 2006.173.03:17:09.42#ibcon#about to read 4, iclass 4, count 0 2006.173.03:17:09.42#ibcon#read 4, iclass 4, count 0 2006.173.03:17:09.42#ibcon#about to read 5, iclass 4, count 0 2006.173.03:17:09.42#ibcon#read 5, iclass 4, count 0 2006.173.03:17:09.42#ibcon#about to read 6, iclass 4, count 0 2006.173.03:17:09.42#ibcon#read 6, iclass 4, count 0 2006.173.03:17:09.42#ibcon#end of sib2, iclass 4, count 0 2006.173.03:17:09.42#ibcon#*mode == 0, iclass 4, count 0 2006.173.03:17:09.42#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.03:17:09.42#ibcon#[27=USB\r\n] 2006.173.03:17:09.42#ibcon#*before write, iclass 4, count 0 2006.173.03:17:09.42#ibcon#enter sib2, iclass 4, count 0 2006.173.03:17:09.42#ibcon#flushed, iclass 4, count 0 2006.173.03:17:09.42#ibcon#about to write, iclass 4, count 0 2006.173.03:17:09.42#ibcon#wrote, iclass 4, count 0 2006.173.03:17:09.42#ibcon#about to read 3, iclass 4, count 0 2006.173.03:17:09.45#ibcon#read 3, iclass 4, count 0 2006.173.03:17:09.45#ibcon#about to read 4, iclass 4, count 0 2006.173.03:17:09.45#ibcon#read 4, iclass 4, count 0 2006.173.03:17:09.45#ibcon#about to read 5, iclass 4, count 0 2006.173.03:17:09.45#ibcon#read 5, iclass 4, count 0 2006.173.03:17:09.45#ibcon#about to read 6, iclass 4, count 0 2006.173.03:17:09.45#ibcon#read 6, iclass 4, count 0 2006.173.03:17:09.45#ibcon#end of sib2, iclass 4, count 0 2006.173.03:17:09.45#ibcon#*after write, iclass 4, count 0 2006.173.03:17:09.45#ibcon#*before return 0, iclass 4, count 0 2006.173.03:17:09.45#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.03:17:09.45#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.03:17:09.45#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.03:17:09.45#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.03:17:09.45$vck44/vblo=5,709.99 2006.173.03:17:09.45#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.03:17:09.45#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.03:17:09.45#ibcon#ireg 17 cls_cnt 0 2006.173.03:17:09.45#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.03:17:09.45#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.03:17:09.45#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.03:17:09.45#ibcon#enter wrdev, iclass 6, count 0 2006.173.03:17:09.45#ibcon#first serial, iclass 6, count 0 2006.173.03:17:09.45#ibcon#enter sib2, iclass 6, count 0 2006.173.03:17:09.45#ibcon#flushed, iclass 6, count 0 2006.173.03:17:09.45#ibcon#about to write, iclass 6, count 0 2006.173.03:17:09.45#ibcon#wrote, iclass 6, count 0 2006.173.03:17:09.45#ibcon#about to read 3, iclass 6, count 0 2006.173.03:17:09.47#ibcon#read 3, iclass 6, count 0 2006.173.03:17:09.47#ibcon#about to read 4, iclass 6, count 0 2006.173.03:17:09.47#ibcon#read 4, iclass 6, count 0 2006.173.03:17:09.47#ibcon#about to read 5, iclass 6, count 0 2006.173.03:17:09.47#ibcon#read 5, iclass 6, count 0 2006.173.03:17:09.47#ibcon#about to read 6, iclass 6, count 0 2006.173.03:17:09.47#ibcon#read 6, iclass 6, count 0 2006.173.03:17:09.47#ibcon#end of sib2, iclass 6, count 0 2006.173.03:17:09.47#ibcon#*mode == 0, iclass 6, count 0 2006.173.03:17:09.47#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.03:17:09.47#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.03:17:09.47#ibcon#*before write, iclass 6, count 0 2006.173.03:17:09.47#ibcon#enter sib2, iclass 6, count 0 2006.173.03:17:09.47#ibcon#flushed, iclass 6, count 0 2006.173.03:17:09.47#ibcon#about to write, iclass 6, count 0 2006.173.03:17:09.47#ibcon#wrote, iclass 6, count 0 2006.173.03:17:09.47#ibcon#about to read 3, iclass 6, count 0 2006.173.03:17:09.51#ibcon#read 3, iclass 6, count 0 2006.173.03:17:09.51#ibcon#about to read 4, iclass 6, count 0 2006.173.03:17:09.51#ibcon#read 4, iclass 6, count 0 2006.173.03:17:09.51#ibcon#about to read 5, iclass 6, count 0 2006.173.03:17:09.51#ibcon#read 5, iclass 6, count 0 2006.173.03:17:09.51#ibcon#about to read 6, iclass 6, count 0 2006.173.03:17:09.51#ibcon#read 6, iclass 6, count 0 2006.173.03:17:09.51#ibcon#end of sib2, iclass 6, count 0 2006.173.03:17:09.51#ibcon#*after write, iclass 6, count 0 2006.173.03:17:09.51#ibcon#*before return 0, iclass 6, count 0 2006.173.03:17:09.51#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.03:17:09.51#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.03:17:09.51#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.03:17:09.51#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.03:17:09.51$vck44/vb=5,4 2006.173.03:17:09.51#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.03:17:09.51#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.03:17:09.51#ibcon#ireg 11 cls_cnt 2 2006.173.03:17:09.51#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.03:17:09.57#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.03:17:09.57#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.03:17:09.57#ibcon#enter wrdev, iclass 10, count 2 2006.173.03:17:09.57#ibcon#first serial, iclass 10, count 2 2006.173.03:17:09.57#ibcon#enter sib2, iclass 10, count 2 2006.173.03:17:09.57#ibcon#flushed, iclass 10, count 2 2006.173.03:17:09.57#ibcon#about to write, iclass 10, count 2 2006.173.03:17:09.57#ibcon#wrote, iclass 10, count 2 2006.173.03:17:09.57#ibcon#about to read 3, iclass 10, count 2 2006.173.03:17:09.59#ibcon#read 3, iclass 10, count 2 2006.173.03:17:09.59#ibcon#about to read 4, iclass 10, count 2 2006.173.03:17:09.59#ibcon#read 4, iclass 10, count 2 2006.173.03:17:09.59#ibcon#about to read 5, iclass 10, count 2 2006.173.03:17:09.59#ibcon#read 5, iclass 10, count 2 2006.173.03:17:09.59#ibcon#about to read 6, iclass 10, count 2 2006.173.03:17:09.59#ibcon#read 6, iclass 10, count 2 2006.173.03:17:09.59#ibcon#end of sib2, iclass 10, count 2 2006.173.03:17:09.59#ibcon#*mode == 0, iclass 10, count 2 2006.173.03:17:09.59#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.03:17:09.59#ibcon#[27=AT05-04\r\n] 2006.173.03:17:09.59#ibcon#*before write, iclass 10, count 2 2006.173.03:17:09.59#ibcon#enter sib2, iclass 10, count 2 2006.173.03:17:09.59#ibcon#flushed, iclass 10, count 2 2006.173.03:17:09.59#ibcon#about to write, iclass 10, count 2 2006.173.03:17:09.59#ibcon#wrote, iclass 10, count 2 2006.173.03:17:09.59#ibcon#about to read 3, iclass 10, count 2 2006.173.03:17:09.62#ibcon#read 3, iclass 10, count 2 2006.173.03:17:09.62#ibcon#about to read 4, iclass 10, count 2 2006.173.03:17:09.62#ibcon#read 4, iclass 10, count 2 2006.173.03:17:09.62#ibcon#about to read 5, iclass 10, count 2 2006.173.03:17:09.62#ibcon#read 5, iclass 10, count 2 2006.173.03:17:09.62#ibcon#about to read 6, iclass 10, count 2 2006.173.03:17:09.62#ibcon#read 6, iclass 10, count 2 2006.173.03:17:09.62#ibcon#end of sib2, iclass 10, count 2 2006.173.03:17:09.62#ibcon#*after write, iclass 10, count 2 2006.173.03:17:09.62#ibcon#*before return 0, iclass 10, count 2 2006.173.03:17:09.62#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.03:17:09.62#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.03:17:09.62#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.03:17:09.62#ibcon#ireg 7 cls_cnt 0 2006.173.03:17:09.62#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.03:17:09.74#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.03:17:09.74#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.03:17:09.74#ibcon#enter wrdev, iclass 10, count 0 2006.173.03:17:09.74#ibcon#first serial, iclass 10, count 0 2006.173.03:17:09.74#ibcon#enter sib2, iclass 10, count 0 2006.173.03:17:09.74#ibcon#flushed, iclass 10, count 0 2006.173.03:17:09.74#ibcon#about to write, iclass 10, count 0 2006.173.03:17:09.74#ibcon#wrote, iclass 10, count 0 2006.173.03:17:09.74#ibcon#about to read 3, iclass 10, count 0 2006.173.03:17:09.76#ibcon#read 3, iclass 10, count 0 2006.173.03:17:09.76#ibcon#about to read 4, iclass 10, count 0 2006.173.03:17:09.76#ibcon#read 4, iclass 10, count 0 2006.173.03:17:09.76#ibcon#about to read 5, iclass 10, count 0 2006.173.03:17:09.76#ibcon#read 5, iclass 10, count 0 2006.173.03:17:09.76#ibcon#about to read 6, iclass 10, count 0 2006.173.03:17:09.76#ibcon#read 6, iclass 10, count 0 2006.173.03:17:09.76#ibcon#end of sib2, iclass 10, count 0 2006.173.03:17:09.76#ibcon#*mode == 0, iclass 10, count 0 2006.173.03:17:09.76#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.03:17:09.76#ibcon#[27=USB\r\n] 2006.173.03:17:09.76#ibcon#*before write, iclass 10, count 0 2006.173.03:17:09.76#ibcon#enter sib2, iclass 10, count 0 2006.173.03:17:09.76#ibcon#flushed, iclass 10, count 0 2006.173.03:17:09.76#ibcon#about to write, iclass 10, count 0 2006.173.03:17:09.76#ibcon#wrote, iclass 10, count 0 2006.173.03:17:09.76#ibcon#about to read 3, iclass 10, count 0 2006.173.03:17:09.79#ibcon#read 3, iclass 10, count 0 2006.173.03:17:09.79#ibcon#about to read 4, iclass 10, count 0 2006.173.03:17:09.79#ibcon#read 4, iclass 10, count 0 2006.173.03:17:09.79#ibcon#about to read 5, iclass 10, count 0 2006.173.03:17:09.79#ibcon#read 5, iclass 10, count 0 2006.173.03:17:09.79#ibcon#about to read 6, iclass 10, count 0 2006.173.03:17:09.79#ibcon#read 6, iclass 10, count 0 2006.173.03:17:09.79#ibcon#end of sib2, iclass 10, count 0 2006.173.03:17:09.79#ibcon#*after write, iclass 10, count 0 2006.173.03:17:09.79#ibcon#*before return 0, iclass 10, count 0 2006.173.03:17:09.79#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.03:17:09.79#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.03:17:09.79#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.03:17:09.79#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.03:17:09.79$vck44/vblo=6,719.99 2006.173.03:17:09.79#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.03:17:09.79#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.03:17:09.79#ibcon#ireg 17 cls_cnt 0 2006.173.03:17:09.79#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.03:17:09.79#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.03:17:09.79#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.03:17:09.79#ibcon#enter wrdev, iclass 12, count 0 2006.173.03:17:09.79#ibcon#first serial, iclass 12, count 0 2006.173.03:17:09.79#ibcon#enter sib2, iclass 12, count 0 2006.173.03:17:09.79#ibcon#flushed, iclass 12, count 0 2006.173.03:17:09.79#ibcon#about to write, iclass 12, count 0 2006.173.03:17:09.79#ibcon#wrote, iclass 12, count 0 2006.173.03:17:09.79#ibcon#about to read 3, iclass 12, count 0 2006.173.03:17:09.81#ibcon#read 3, iclass 12, count 0 2006.173.03:17:09.81#ibcon#about to read 4, iclass 12, count 0 2006.173.03:17:09.81#ibcon#read 4, iclass 12, count 0 2006.173.03:17:09.81#ibcon#about to read 5, iclass 12, count 0 2006.173.03:17:09.81#ibcon#read 5, iclass 12, count 0 2006.173.03:17:09.81#ibcon#about to read 6, iclass 12, count 0 2006.173.03:17:09.81#ibcon#read 6, iclass 12, count 0 2006.173.03:17:09.81#ibcon#end of sib2, iclass 12, count 0 2006.173.03:17:09.81#ibcon#*mode == 0, iclass 12, count 0 2006.173.03:17:09.81#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.03:17:09.81#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.03:17:09.81#ibcon#*before write, iclass 12, count 0 2006.173.03:17:09.81#ibcon#enter sib2, iclass 12, count 0 2006.173.03:17:09.81#ibcon#flushed, iclass 12, count 0 2006.173.03:17:09.81#ibcon#about to write, iclass 12, count 0 2006.173.03:17:09.81#ibcon#wrote, iclass 12, count 0 2006.173.03:17:09.81#ibcon#about to read 3, iclass 12, count 0 2006.173.03:17:09.85#ibcon#read 3, iclass 12, count 0 2006.173.03:17:09.85#ibcon#about to read 4, iclass 12, count 0 2006.173.03:17:09.85#ibcon#read 4, iclass 12, count 0 2006.173.03:17:09.85#ibcon#about to read 5, iclass 12, count 0 2006.173.03:17:09.85#ibcon#read 5, iclass 12, count 0 2006.173.03:17:09.85#ibcon#about to read 6, iclass 12, count 0 2006.173.03:17:09.85#ibcon#read 6, iclass 12, count 0 2006.173.03:17:09.85#ibcon#end of sib2, iclass 12, count 0 2006.173.03:17:09.85#ibcon#*after write, iclass 12, count 0 2006.173.03:17:09.85#ibcon#*before return 0, iclass 12, count 0 2006.173.03:17:09.85#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.03:17:09.85#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.03:17:09.85#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.03:17:09.85#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.03:17:09.85$vck44/vb=6,4 2006.173.03:17:09.85#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.03:17:09.85#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.03:17:09.85#ibcon#ireg 11 cls_cnt 2 2006.173.03:17:09.85#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.03:17:09.91#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.03:17:09.91#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.03:17:09.91#ibcon#enter wrdev, iclass 14, count 2 2006.173.03:17:09.91#ibcon#first serial, iclass 14, count 2 2006.173.03:17:09.91#ibcon#enter sib2, iclass 14, count 2 2006.173.03:17:09.91#ibcon#flushed, iclass 14, count 2 2006.173.03:17:09.91#ibcon#about to write, iclass 14, count 2 2006.173.03:17:09.91#ibcon#wrote, iclass 14, count 2 2006.173.03:17:09.91#ibcon#about to read 3, iclass 14, count 2 2006.173.03:17:09.93#ibcon#read 3, iclass 14, count 2 2006.173.03:17:09.93#ibcon#about to read 4, iclass 14, count 2 2006.173.03:17:09.93#ibcon#read 4, iclass 14, count 2 2006.173.03:17:09.93#ibcon#about to read 5, iclass 14, count 2 2006.173.03:17:09.93#ibcon#read 5, iclass 14, count 2 2006.173.03:17:09.93#ibcon#about to read 6, iclass 14, count 2 2006.173.03:17:09.93#ibcon#read 6, iclass 14, count 2 2006.173.03:17:09.93#ibcon#end of sib2, iclass 14, count 2 2006.173.03:17:09.93#ibcon#*mode == 0, iclass 14, count 2 2006.173.03:17:09.93#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.03:17:09.93#ibcon#[27=AT06-04\r\n] 2006.173.03:17:09.93#ibcon#*before write, iclass 14, count 2 2006.173.03:17:09.93#ibcon#enter sib2, iclass 14, count 2 2006.173.03:17:09.93#ibcon#flushed, iclass 14, count 2 2006.173.03:17:09.93#ibcon#about to write, iclass 14, count 2 2006.173.03:17:09.93#ibcon#wrote, iclass 14, count 2 2006.173.03:17:09.93#ibcon#about to read 3, iclass 14, count 2 2006.173.03:17:09.96#ibcon#read 3, iclass 14, count 2 2006.173.03:17:09.96#ibcon#about to read 4, iclass 14, count 2 2006.173.03:17:09.96#ibcon#read 4, iclass 14, count 2 2006.173.03:17:09.96#ibcon#about to read 5, iclass 14, count 2 2006.173.03:17:09.96#ibcon#read 5, iclass 14, count 2 2006.173.03:17:09.96#ibcon#about to read 6, iclass 14, count 2 2006.173.03:17:09.96#ibcon#read 6, iclass 14, count 2 2006.173.03:17:09.96#ibcon#end of sib2, iclass 14, count 2 2006.173.03:17:09.96#ibcon#*after write, iclass 14, count 2 2006.173.03:17:09.96#ibcon#*before return 0, iclass 14, count 2 2006.173.03:17:09.96#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.03:17:09.96#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.03:17:09.96#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.03:17:09.96#ibcon#ireg 7 cls_cnt 0 2006.173.03:17:09.96#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.03:17:10.08#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.03:17:10.08#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.03:17:10.08#ibcon#enter wrdev, iclass 14, count 0 2006.173.03:17:10.08#ibcon#first serial, iclass 14, count 0 2006.173.03:17:10.08#ibcon#enter sib2, iclass 14, count 0 2006.173.03:17:10.08#ibcon#flushed, iclass 14, count 0 2006.173.03:17:10.08#ibcon#about to write, iclass 14, count 0 2006.173.03:17:10.08#ibcon#wrote, iclass 14, count 0 2006.173.03:17:10.08#ibcon#about to read 3, iclass 14, count 0 2006.173.03:17:10.10#ibcon#read 3, iclass 14, count 0 2006.173.03:17:10.10#ibcon#about to read 4, iclass 14, count 0 2006.173.03:17:10.10#ibcon#read 4, iclass 14, count 0 2006.173.03:17:10.10#ibcon#about to read 5, iclass 14, count 0 2006.173.03:17:10.10#ibcon#read 5, iclass 14, count 0 2006.173.03:17:10.10#ibcon#about to read 6, iclass 14, count 0 2006.173.03:17:10.10#ibcon#read 6, iclass 14, count 0 2006.173.03:17:10.10#ibcon#end of sib2, iclass 14, count 0 2006.173.03:17:10.10#ibcon#*mode == 0, iclass 14, count 0 2006.173.03:17:10.10#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.03:17:10.10#ibcon#[27=USB\r\n] 2006.173.03:17:10.10#ibcon#*before write, iclass 14, count 0 2006.173.03:17:10.10#ibcon#enter sib2, iclass 14, count 0 2006.173.03:17:10.10#ibcon#flushed, iclass 14, count 0 2006.173.03:17:10.10#ibcon#about to write, iclass 14, count 0 2006.173.03:17:10.10#ibcon#wrote, iclass 14, count 0 2006.173.03:17:10.10#ibcon#about to read 3, iclass 14, count 0 2006.173.03:17:10.13#ibcon#read 3, iclass 14, count 0 2006.173.03:17:10.13#ibcon#about to read 4, iclass 14, count 0 2006.173.03:17:10.13#ibcon#read 4, iclass 14, count 0 2006.173.03:17:10.13#ibcon#about to read 5, iclass 14, count 0 2006.173.03:17:10.13#ibcon#read 5, iclass 14, count 0 2006.173.03:17:10.13#ibcon#about to read 6, iclass 14, count 0 2006.173.03:17:10.13#ibcon#read 6, iclass 14, count 0 2006.173.03:17:10.13#ibcon#end of sib2, iclass 14, count 0 2006.173.03:17:10.13#ibcon#*after write, iclass 14, count 0 2006.173.03:17:10.13#ibcon#*before return 0, iclass 14, count 0 2006.173.03:17:10.13#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.03:17:10.13#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.03:17:10.13#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.03:17:10.13#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.03:17:10.13$vck44/vblo=7,734.99 2006.173.03:17:10.13#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.03:17:10.13#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.03:17:10.13#ibcon#ireg 17 cls_cnt 0 2006.173.03:17:10.13#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.03:17:10.13#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.03:17:10.13#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.03:17:10.13#ibcon#enter wrdev, iclass 16, count 0 2006.173.03:17:10.13#ibcon#first serial, iclass 16, count 0 2006.173.03:17:10.13#ibcon#enter sib2, iclass 16, count 0 2006.173.03:17:10.13#ibcon#flushed, iclass 16, count 0 2006.173.03:17:10.13#ibcon#about to write, iclass 16, count 0 2006.173.03:17:10.13#ibcon#wrote, iclass 16, count 0 2006.173.03:17:10.13#ibcon#about to read 3, iclass 16, count 0 2006.173.03:17:10.15#ibcon#read 3, iclass 16, count 0 2006.173.03:17:10.15#ibcon#about to read 4, iclass 16, count 0 2006.173.03:17:10.15#ibcon#read 4, iclass 16, count 0 2006.173.03:17:10.15#ibcon#about to read 5, iclass 16, count 0 2006.173.03:17:10.15#ibcon#read 5, iclass 16, count 0 2006.173.03:17:10.15#ibcon#about to read 6, iclass 16, count 0 2006.173.03:17:10.15#ibcon#read 6, iclass 16, count 0 2006.173.03:17:10.15#ibcon#end of sib2, iclass 16, count 0 2006.173.03:17:10.15#ibcon#*mode == 0, iclass 16, count 0 2006.173.03:17:10.15#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.03:17:10.15#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.03:17:10.15#ibcon#*before write, iclass 16, count 0 2006.173.03:17:10.15#ibcon#enter sib2, iclass 16, count 0 2006.173.03:17:10.15#ibcon#flushed, iclass 16, count 0 2006.173.03:17:10.15#ibcon#about to write, iclass 16, count 0 2006.173.03:17:10.15#ibcon#wrote, iclass 16, count 0 2006.173.03:17:10.15#ibcon#about to read 3, iclass 16, count 0 2006.173.03:17:10.19#ibcon#read 3, iclass 16, count 0 2006.173.03:17:10.19#ibcon#about to read 4, iclass 16, count 0 2006.173.03:17:10.19#ibcon#read 4, iclass 16, count 0 2006.173.03:17:10.19#ibcon#about to read 5, iclass 16, count 0 2006.173.03:17:10.19#ibcon#read 5, iclass 16, count 0 2006.173.03:17:10.19#ibcon#about to read 6, iclass 16, count 0 2006.173.03:17:10.19#ibcon#read 6, iclass 16, count 0 2006.173.03:17:10.19#ibcon#end of sib2, iclass 16, count 0 2006.173.03:17:10.19#ibcon#*after write, iclass 16, count 0 2006.173.03:17:10.19#ibcon#*before return 0, iclass 16, count 0 2006.173.03:17:10.19#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.03:17:10.19#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.03:17:10.19#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.03:17:10.19#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.03:17:10.19$vck44/vb=7,4 2006.173.03:17:10.19#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.03:17:10.19#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.03:17:10.19#ibcon#ireg 11 cls_cnt 2 2006.173.03:17:10.19#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.03:17:10.25#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.03:17:10.25#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.03:17:10.25#ibcon#enter wrdev, iclass 18, count 2 2006.173.03:17:10.25#ibcon#first serial, iclass 18, count 2 2006.173.03:17:10.25#ibcon#enter sib2, iclass 18, count 2 2006.173.03:17:10.25#ibcon#flushed, iclass 18, count 2 2006.173.03:17:10.25#ibcon#about to write, iclass 18, count 2 2006.173.03:17:10.25#ibcon#wrote, iclass 18, count 2 2006.173.03:17:10.25#ibcon#about to read 3, iclass 18, count 2 2006.173.03:17:10.27#ibcon#read 3, iclass 18, count 2 2006.173.03:17:10.27#ibcon#about to read 4, iclass 18, count 2 2006.173.03:17:10.27#ibcon#read 4, iclass 18, count 2 2006.173.03:17:10.27#ibcon#about to read 5, iclass 18, count 2 2006.173.03:17:10.27#ibcon#read 5, iclass 18, count 2 2006.173.03:17:10.27#ibcon#about to read 6, iclass 18, count 2 2006.173.03:17:10.27#ibcon#read 6, iclass 18, count 2 2006.173.03:17:10.27#ibcon#end of sib2, iclass 18, count 2 2006.173.03:17:10.27#ibcon#*mode == 0, iclass 18, count 2 2006.173.03:17:10.27#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.03:17:10.27#ibcon#[27=AT07-04\r\n] 2006.173.03:17:10.27#ibcon#*before write, iclass 18, count 2 2006.173.03:17:10.27#ibcon#enter sib2, iclass 18, count 2 2006.173.03:17:10.27#ibcon#flushed, iclass 18, count 2 2006.173.03:17:10.27#ibcon#about to write, iclass 18, count 2 2006.173.03:17:10.27#ibcon#wrote, iclass 18, count 2 2006.173.03:17:10.27#ibcon#about to read 3, iclass 18, count 2 2006.173.03:17:10.30#ibcon#read 3, iclass 18, count 2 2006.173.03:17:10.30#ibcon#about to read 4, iclass 18, count 2 2006.173.03:17:10.30#ibcon#read 4, iclass 18, count 2 2006.173.03:17:10.30#ibcon#about to read 5, iclass 18, count 2 2006.173.03:17:10.30#ibcon#read 5, iclass 18, count 2 2006.173.03:17:10.30#ibcon#about to read 6, iclass 18, count 2 2006.173.03:17:10.30#ibcon#read 6, iclass 18, count 2 2006.173.03:17:10.30#ibcon#end of sib2, iclass 18, count 2 2006.173.03:17:10.30#ibcon#*after write, iclass 18, count 2 2006.173.03:17:10.30#ibcon#*before return 0, iclass 18, count 2 2006.173.03:17:10.30#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.03:17:10.30#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.03:17:10.30#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.03:17:10.30#ibcon#ireg 7 cls_cnt 0 2006.173.03:17:10.30#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.03:17:10.42#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.03:17:10.42#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.03:17:10.42#ibcon#enter wrdev, iclass 18, count 0 2006.173.03:17:10.42#ibcon#first serial, iclass 18, count 0 2006.173.03:17:10.42#ibcon#enter sib2, iclass 18, count 0 2006.173.03:17:10.42#ibcon#flushed, iclass 18, count 0 2006.173.03:17:10.42#ibcon#about to write, iclass 18, count 0 2006.173.03:17:10.42#ibcon#wrote, iclass 18, count 0 2006.173.03:17:10.42#ibcon#about to read 3, iclass 18, count 0 2006.173.03:17:10.44#ibcon#read 3, iclass 18, count 0 2006.173.03:17:10.44#ibcon#about to read 4, iclass 18, count 0 2006.173.03:17:10.44#ibcon#read 4, iclass 18, count 0 2006.173.03:17:10.44#ibcon#about to read 5, iclass 18, count 0 2006.173.03:17:10.44#ibcon#read 5, iclass 18, count 0 2006.173.03:17:10.44#ibcon#about to read 6, iclass 18, count 0 2006.173.03:17:10.44#ibcon#read 6, iclass 18, count 0 2006.173.03:17:10.44#ibcon#end of sib2, iclass 18, count 0 2006.173.03:17:10.44#ibcon#*mode == 0, iclass 18, count 0 2006.173.03:17:10.44#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.03:17:10.44#ibcon#[27=USB\r\n] 2006.173.03:17:10.44#ibcon#*before write, iclass 18, count 0 2006.173.03:17:10.44#ibcon#enter sib2, iclass 18, count 0 2006.173.03:17:10.44#ibcon#flushed, iclass 18, count 0 2006.173.03:17:10.44#ibcon#about to write, iclass 18, count 0 2006.173.03:17:10.44#ibcon#wrote, iclass 18, count 0 2006.173.03:17:10.44#ibcon#about to read 3, iclass 18, count 0 2006.173.03:17:10.47#ibcon#read 3, iclass 18, count 0 2006.173.03:17:10.47#ibcon#about to read 4, iclass 18, count 0 2006.173.03:17:10.47#ibcon#read 4, iclass 18, count 0 2006.173.03:17:10.47#ibcon#about to read 5, iclass 18, count 0 2006.173.03:17:10.47#ibcon#read 5, iclass 18, count 0 2006.173.03:17:10.47#ibcon#about to read 6, iclass 18, count 0 2006.173.03:17:10.47#ibcon#read 6, iclass 18, count 0 2006.173.03:17:10.47#ibcon#end of sib2, iclass 18, count 0 2006.173.03:17:10.47#ibcon#*after write, iclass 18, count 0 2006.173.03:17:10.47#ibcon#*before return 0, iclass 18, count 0 2006.173.03:17:10.47#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.03:17:10.47#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.03:17:10.47#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.03:17:10.47#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.03:17:10.47$vck44/vblo=8,744.99 2006.173.03:17:10.47#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.03:17:10.47#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.03:17:10.47#ibcon#ireg 17 cls_cnt 0 2006.173.03:17:10.47#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.03:17:10.47#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.03:17:10.47#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.03:17:10.47#ibcon#enter wrdev, iclass 20, count 0 2006.173.03:17:10.47#ibcon#first serial, iclass 20, count 0 2006.173.03:17:10.47#ibcon#enter sib2, iclass 20, count 0 2006.173.03:17:10.47#ibcon#flushed, iclass 20, count 0 2006.173.03:17:10.47#ibcon#about to write, iclass 20, count 0 2006.173.03:17:10.47#ibcon#wrote, iclass 20, count 0 2006.173.03:17:10.47#ibcon#about to read 3, iclass 20, count 0 2006.173.03:17:10.49#ibcon#read 3, iclass 20, count 0 2006.173.03:17:10.49#ibcon#about to read 4, iclass 20, count 0 2006.173.03:17:10.49#ibcon#read 4, iclass 20, count 0 2006.173.03:17:10.49#ibcon#about to read 5, iclass 20, count 0 2006.173.03:17:10.49#ibcon#read 5, iclass 20, count 0 2006.173.03:17:10.49#ibcon#about to read 6, iclass 20, count 0 2006.173.03:17:10.49#ibcon#read 6, iclass 20, count 0 2006.173.03:17:10.49#ibcon#end of sib2, iclass 20, count 0 2006.173.03:17:10.49#ibcon#*mode == 0, iclass 20, count 0 2006.173.03:17:10.49#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.03:17:10.49#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.03:17:10.49#ibcon#*before write, iclass 20, count 0 2006.173.03:17:10.49#ibcon#enter sib2, iclass 20, count 0 2006.173.03:17:10.49#ibcon#flushed, iclass 20, count 0 2006.173.03:17:10.49#ibcon#about to write, iclass 20, count 0 2006.173.03:17:10.49#ibcon#wrote, iclass 20, count 0 2006.173.03:17:10.49#ibcon#about to read 3, iclass 20, count 0 2006.173.03:17:10.53#ibcon#read 3, iclass 20, count 0 2006.173.03:17:10.53#ibcon#about to read 4, iclass 20, count 0 2006.173.03:17:10.53#ibcon#read 4, iclass 20, count 0 2006.173.03:17:10.53#ibcon#about to read 5, iclass 20, count 0 2006.173.03:17:10.53#ibcon#read 5, iclass 20, count 0 2006.173.03:17:10.53#ibcon#about to read 6, iclass 20, count 0 2006.173.03:17:10.53#ibcon#read 6, iclass 20, count 0 2006.173.03:17:10.53#ibcon#end of sib2, iclass 20, count 0 2006.173.03:17:10.53#ibcon#*after write, iclass 20, count 0 2006.173.03:17:10.53#ibcon#*before return 0, iclass 20, count 0 2006.173.03:17:10.53#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.03:17:10.53#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.03:17:10.53#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.03:17:10.53#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.03:17:10.53$vck44/vb=8,4 2006.173.03:17:10.53#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.03:17:10.53#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.03:17:10.53#ibcon#ireg 11 cls_cnt 2 2006.173.03:17:10.53#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.03:17:10.59#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.03:17:10.59#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.03:17:10.59#ibcon#enter wrdev, iclass 22, count 2 2006.173.03:17:10.59#ibcon#first serial, iclass 22, count 2 2006.173.03:17:10.59#ibcon#enter sib2, iclass 22, count 2 2006.173.03:17:10.59#ibcon#flushed, iclass 22, count 2 2006.173.03:17:10.59#ibcon#about to write, iclass 22, count 2 2006.173.03:17:10.59#ibcon#wrote, iclass 22, count 2 2006.173.03:17:10.59#ibcon#about to read 3, iclass 22, count 2 2006.173.03:17:10.61#ibcon#read 3, iclass 22, count 2 2006.173.03:17:10.61#ibcon#about to read 4, iclass 22, count 2 2006.173.03:17:10.61#ibcon#read 4, iclass 22, count 2 2006.173.03:17:10.61#ibcon#about to read 5, iclass 22, count 2 2006.173.03:17:10.61#ibcon#read 5, iclass 22, count 2 2006.173.03:17:10.61#ibcon#about to read 6, iclass 22, count 2 2006.173.03:17:10.61#ibcon#read 6, iclass 22, count 2 2006.173.03:17:10.61#ibcon#end of sib2, iclass 22, count 2 2006.173.03:17:10.61#ibcon#*mode == 0, iclass 22, count 2 2006.173.03:17:10.61#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.03:17:10.61#ibcon#[27=AT08-04\r\n] 2006.173.03:17:10.61#ibcon#*before write, iclass 22, count 2 2006.173.03:17:10.61#ibcon#enter sib2, iclass 22, count 2 2006.173.03:17:10.61#ibcon#flushed, iclass 22, count 2 2006.173.03:17:10.61#ibcon#about to write, iclass 22, count 2 2006.173.03:17:10.61#ibcon#wrote, iclass 22, count 2 2006.173.03:17:10.61#ibcon#about to read 3, iclass 22, count 2 2006.173.03:17:10.64#ibcon#read 3, iclass 22, count 2 2006.173.03:17:10.64#ibcon#about to read 4, iclass 22, count 2 2006.173.03:17:10.64#ibcon#read 4, iclass 22, count 2 2006.173.03:17:10.64#ibcon#about to read 5, iclass 22, count 2 2006.173.03:17:10.64#ibcon#read 5, iclass 22, count 2 2006.173.03:17:10.64#ibcon#about to read 6, iclass 22, count 2 2006.173.03:17:10.64#ibcon#read 6, iclass 22, count 2 2006.173.03:17:10.64#ibcon#end of sib2, iclass 22, count 2 2006.173.03:17:10.64#ibcon#*after write, iclass 22, count 2 2006.173.03:17:10.64#ibcon#*before return 0, iclass 22, count 2 2006.173.03:17:10.64#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.03:17:10.64#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.03:17:10.64#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.03:17:10.64#ibcon#ireg 7 cls_cnt 0 2006.173.03:17:10.64#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.03:17:10.76#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.03:17:10.76#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.03:17:10.76#ibcon#enter wrdev, iclass 22, count 0 2006.173.03:17:10.76#ibcon#first serial, iclass 22, count 0 2006.173.03:17:10.76#ibcon#enter sib2, iclass 22, count 0 2006.173.03:17:10.76#ibcon#flushed, iclass 22, count 0 2006.173.03:17:10.76#ibcon#about to write, iclass 22, count 0 2006.173.03:17:10.76#ibcon#wrote, iclass 22, count 0 2006.173.03:17:10.76#ibcon#about to read 3, iclass 22, count 0 2006.173.03:17:10.78#ibcon#read 3, iclass 22, count 0 2006.173.03:17:10.78#ibcon#about to read 4, iclass 22, count 0 2006.173.03:17:10.78#ibcon#read 4, iclass 22, count 0 2006.173.03:17:10.78#ibcon#about to read 5, iclass 22, count 0 2006.173.03:17:10.78#ibcon#read 5, iclass 22, count 0 2006.173.03:17:10.78#ibcon#about to read 6, iclass 22, count 0 2006.173.03:17:10.78#ibcon#read 6, iclass 22, count 0 2006.173.03:17:10.78#ibcon#end of sib2, iclass 22, count 0 2006.173.03:17:10.78#ibcon#*mode == 0, iclass 22, count 0 2006.173.03:17:10.78#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.03:17:10.78#ibcon#[27=USB\r\n] 2006.173.03:17:10.78#ibcon#*before write, iclass 22, count 0 2006.173.03:17:10.78#ibcon#enter sib2, iclass 22, count 0 2006.173.03:17:10.78#ibcon#flushed, iclass 22, count 0 2006.173.03:17:10.78#ibcon#about to write, iclass 22, count 0 2006.173.03:17:10.78#ibcon#wrote, iclass 22, count 0 2006.173.03:17:10.78#ibcon#about to read 3, iclass 22, count 0 2006.173.03:17:10.81#ibcon#read 3, iclass 22, count 0 2006.173.03:17:10.81#ibcon#about to read 4, iclass 22, count 0 2006.173.03:17:10.81#ibcon#read 4, iclass 22, count 0 2006.173.03:17:10.81#ibcon#about to read 5, iclass 22, count 0 2006.173.03:17:10.81#ibcon#read 5, iclass 22, count 0 2006.173.03:17:10.81#ibcon#about to read 6, iclass 22, count 0 2006.173.03:17:10.81#ibcon#read 6, iclass 22, count 0 2006.173.03:17:10.81#ibcon#end of sib2, iclass 22, count 0 2006.173.03:17:10.81#ibcon#*after write, iclass 22, count 0 2006.173.03:17:10.81#ibcon#*before return 0, iclass 22, count 0 2006.173.03:17:10.81#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.03:17:10.81#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.03:17:10.81#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.03:17:10.81#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.03:17:10.81$vck44/vabw=wide 2006.173.03:17:10.81#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.03:17:10.81#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.03:17:10.81#ibcon#ireg 8 cls_cnt 0 2006.173.03:17:10.81#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.03:17:10.81#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.03:17:10.81#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.03:17:10.81#ibcon#enter wrdev, iclass 24, count 0 2006.173.03:17:10.81#ibcon#first serial, iclass 24, count 0 2006.173.03:17:10.81#ibcon#enter sib2, iclass 24, count 0 2006.173.03:17:10.81#ibcon#flushed, iclass 24, count 0 2006.173.03:17:10.81#ibcon#about to write, iclass 24, count 0 2006.173.03:17:10.81#ibcon#wrote, iclass 24, count 0 2006.173.03:17:10.81#ibcon#about to read 3, iclass 24, count 0 2006.173.03:17:10.83#ibcon#read 3, iclass 24, count 0 2006.173.03:17:10.83#ibcon#about to read 4, iclass 24, count 0 2006.173.03:17:10.83#ibcon#read 4, iclass 24, count 0 2006.173.03:17:10.83#ibcon#about to read 5, iclass 24, count 0 2006.173.03:17:10.83#ibcon#read 5, iclass 24, count 0 2006.173.03:17:10.83#ibcon#about to read 6, iclass 24, count 0 2006.173.03:17:10.83#ibcon#read 6, iclass 24, count 0 2006.173.03:17:10.83#ibcon#end of sib2, iclass 24, count 0 2006.173.03:17:10.83#ibcon#*mode == 0, iclass 24, count 0 2006.173.03:17:10.83#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.03:17:10.83#ibcon#[25=BW32\r\n] 2006.173.03:17:10.83#ibcon#*before write, iclass 24, count 0 2006.173.03:17:10.83#ibcon#enter sib2, iclass 24, count 0 2006.173.03:17:10.83#ibcon#flushed, iclass 24, count 0 2006.173.03:17:10.83#ibcon#about to write, iclass 24, count 0 2006.173.03:17:10.83#ibcon#wrote, iclass 24, count 0 2006.173.03:17:10.83#ibcon#about to read 3, iclass 24, count 0 2006.173.03:17:10.86#ibcon#read 3, iclass 24, count 0 2006.173.03:17:10.86#ibcon#about to read 4, iclass 24, count 0 2006.173.03:17:10.86#ibcon#read 4, iclass 24, count 0 2006.173.03:17:10.86#ibcon#about to read 5, iclass 24, count 0 2006.173.03:17:10.86#ibcon#read 5, iclass 24, count 0 2006.173.03:17:10.86#ibcon#about to read 6, iclass 24, count 0 2006.173.03:17:10.86#ibcon#read 6, iclass 24, count 0 2006.173.03:17:10.86#ibcon#end of sib2, iclass 24, count 0 2006.173.03:17:10.86#ibcon#*after write, iclass 24, count 0 2006.173.03:17:10.86#ibcon#*before return 0, iclass 24, count 0 2006.173.03:17:10.86#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.03:17:10.86#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.03:17:10.86#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.03:17:10.86#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.03:17:10.86$vck44/vbbw=wide 2006.173.03:17:10.86#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.03:17:10.86#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.03:17:10.86#ibcon#ireg 8 cls_cnt 0 2006.173.03:17:10.86#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.03:17:10.93#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.03:17:10.93#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.03:17:10.93#ibcon#enter wrdev, iclass 26, count 0 2006.173.03:17:10.93#ibcon#first serial, iclass 26, count 0 2006.173.03:17:10.93#ibcon#enter sib2, iclass 26, count 0 2006.173.03:17:10.93#ibcon#flushed, iclass 26, count 0 2006.173.03:17:10.93#ibcon#about to write, iclass 26, count 0 2006.173.03:17:10.93#ibcon#wrote, iclass 26, count 0 2006.173.03:17:10.93#ibcon#about to read 3, iclass 26, count 0 2006.173.03:17:10.95#ibcon#read 3, iclass 26, count 0 2006.173.03:17:10.95#ibcon#about to read 4, iclass 26, count 0 2006.173.03:17:10.95#ibcon#read 4, iclass 26, count 0 2006.173.03:17:10.95#ibcon#about to read 5, iclass 26, count 0 2006.173.03:17:10.95#ibcon#read 5, iclass 26, count 0 2006.173.03:17:10.95#ibcon#about to read 6, iclass 26, count 0 2006.173.03:17:10.95#ibcon#read 6, iclass 26, count 0 2006.173.03:17:10.95#ibcon#end of sib2, iclass 26, count 0 2006.173.03:17:10.95#ibcon#*mode == 0, iclass 26, count 0 2006.173.03:17:10.95#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.03:17:10.95#ibcon#[27=BW32\r\n] 2006.173.03:17:10.95#ibcon#*before write, iclass 26, count 0 2006.173.03:17:10.95#ibcon#enter sib2, iclass 26, count 0 2006.173.03:17:10.95#ibcon#flushed, iclass 26, count 0 2006.173.03:17:10.95#ibcon#about to write, iclass 26, count 0 2006.173.03:17:10.95#ibcon#wrote, iclass 26, count 0 2006.173.03:17:10.95#ibcon#about to read 3, iclass 26, count 0 2006.173.03:17:10.98#ibcon#read 3, iclass 26, count 0 2006.173.03:17:10.98#ibcon#about to read 4, iclass 26, count 0 2006.173.03:17:10.98#ibcon#read 4, iclass 26, count 0 2006.173.03:17:10.98#ibcon#about to read 5, iclass 26, count 0 2006.173.03:17:10.98#ibcon#read 5, iclass 26, count 0 2006.173.03:17:10.98#ibcon#about to read 6, iclass 26, count 0 2006.173.03:17:10.98#ibcon#read 6, iclass 26, count 0 2006.173.03:17:10.98#ibcon#end of sib2, iclass 26, count 0 2006.173.03:17:10.98#ibcon#*after write, iclass 26, count 0 2006.173.03:17:10.98#ibcon#*before return 0, iclass 26, count 0 2006.173.03:17:10.98#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.03:17:10.98#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.03:17:10.98#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.03:17:10.98#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.03:17:10.98$setupk4/ifdk4 2006.173.03:17:10.98$ifdk4/lo= 2006.173.03:17:10.98$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.03:17:10.98$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.03:17:10.98$ifdk4/patch= 2006.173.03:17:10.98$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.03:17:10.98$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.03:17:10.98$setupk4/!*+20s 2006.173.03:17:12.77#abcon#<5=/14 1.1 2.3 22.30 841006.2\r\n> 2006.173.03:17:12.79#abcon#{5=INTERFACE CLEAR} 2006.173.03:17:12.85#abcon#[5=S1D000X0/0*\r\n] 2006.173.03:17:22.94#abcon#<5=/14 1.1 2.3 22.30 841006.2\r\n> 2006.173.03:17:22.96#abcon#{5=INTERFACE CLEAR} 2006.173.03:17:23.02#abcon#[5=S1D000X0/0*\r\n] 2006.173.03:17:25.48$setupk4/"tpicd 2006.173.03:17:25.48$setupk4/echo=off 2006.173.03:17:25.48$setupk4/xlog=off 2006.173.03:17:25.48:!2006.173.03:17:44 2006.173.03:17:27.13#trakl#Source acquired 2006.173.03:17:28.14#flagr#flagr/antenna,acquired 2006.173.03:17:44.00:preob 2006.173.03:17:44.14/onsource/TRACKING 2006.173.03:17:44.14:!2006.173.03:17:54 2006.173.03:17:54.00:"tape 2006.173.03:17:54.00:"st=record 2006.173.03:17:54.00:data_valid=on 2006.173.03:17:54.00:midob 2006.173.03:17:55.14/onsource/TRACKING 2006.173.03:17:55.14/wx/22.31,1006.2,85 2006.173.03:17:55.29/cable/+6.5095E-03 2006.173.03:17:56.38/va/01,07,usb,yes,48,52 2006.173.03:17:56.38/va/02,06,usb,yes,48,49 2006.173.03:17:56.38/va/03,05,usb,yes,61,63 2006.173.03:17:56.38/va/04,06,usb,yes,49,52 2006.173.03:17:56.38/va/05,04,usb,yes,39,40 2006.173.03:17:56.38/va/06,03,usb,yes,54,54 2006.173.03:17:56.38/va/07,04,usb,yes,44,46 2006.173.03:17:56.38/va/08,04,usb,yes,38,45 2006.173.03:17:56.61/valo/01,524.99,yes,locked 2006.173.03:17:56.61/valo/02,534.99,yes,locked 2006.173.03:17:56.61/valo/03,564.99,yes,locked 2006.173.03:17:56.61/valo/04,624.99,yes,locked 2006.173.03:17:56.61/valo/05,734.99,yes,locked 2006.173.03:17:56.61/valo/06,814.99,yes,locked 2006.173.03:17:56.61/valo/07,864.99,yes,locked 2006.173.03:17:56.61/valo/08,884.99,yes,locked 2006.173.03:17:57.70/vb/01,04,usb,yes,38,35 2006.173.03:17:57.70/vb/02,04,usb,yes,41,41 2006.173.03:17:57.70/vb/03,04,usb,yes,37,41 2006.173.03:17:57.70/vb/04,04,usb,yes,42,41 2006.173.03:17:57.70/vb/05,04,usb,yes,34,37 2006.173.03:17:57.70/vb/06,04,usb,yes,39,35 2006.173.03:17:57.70/vb/07,04,usb,yes,39,39 2006.173.03:17:57.70/vb/08,04,usb,yes,35,40 2006.173.03:17:57.94/vblo/01,629.99,yes,locked 2006.173.03:17:57.94/vblo/02,634.99,yes,locked 2006.173.03:17:57.94/vblo/03,649.99,yes,locked 2006.173.03:17:57.94/vblo/04,679.99,yes,locked 2006.173.03:17:57.94/vblo/05,709.99,yes,locked 2006.173.03:17:57.94/vblo/06,719.99,yes,locked 2006.173.03:17:57.94/vblo/07,734.99,yes,locked 2006.173.03:17:57.94/vblo/08,744.99,yes,locked 2006.173.03:17:58.09/vabw/8 2006.173.03:17:58.24/vbbw/8 2006.173.03:17:58.33/xfe/off,on,14.7 2006.173.03:17:58.72/ifatt/23,28,28,28 2006.173.03:17:59.08/fmout-gps/S +3.89E-07 2006.173.03:17:59.12:!2006.173.03:20:54 2006.173.03:20:54.00:data_valid=off 2006.173.03:20:54.00:"et 2006.173.03:20:54.00:!+3s 2006.173.03:20:57.02:"tape 2006.173.03:20:57.02:postob 2006.173.03:20:57.21/cable/+6.5099E-03 2006.173.03:20:57.21/wx/22.38,1006.3,85 2006.173.03:20:58.08/fmout-gps/S +3.91E-07 2006.173.03:20:58.08:scan_name=173-0321,jd0606,40 2006.173.03:20:58.08:source=0537-441,053850.36,-440508.9,2000.0,cw 2006.173.03:20:58.14#flagr#flagr/antenna,new-source 2006.173.03:20:59.14:checkk5 2006.173.03:20:59.48/chk_autoobs//k5ts1/ autoobs is running! 2006.173.03:20:59.82/chk_autoobs//k5ts2/ autoobs is running! 2006.173.03:21:00.15/chk_autoobs//k5ts3/ autoobs is running! 2006.173.03:21:00.50/chk_autoobs//k5ts4/ autoobs is running! 2006.173.03:21:00.83/chk_obsdata//k5ts1/T1730317??a.dat file size is correct (nominal:720MB, actual:716MB). 2006.173.03:21:01.17/chk_obsdata//k5ts2/T1730317??b.dat file size is correct (nominal:720MB, actual:716MB). 2006.173.03:21:01.50/chk_obsdata//k5ts3/T1730317??c.dat file size is correct (nominal:720MB, actual:716MB). 2006.173.03:21:01.83/chk_obsdata//k5ts4/T1730317??d.dat file size is correct (nominal:720MB, actual:716MB). 2006.173.03:21:02.48/k5log//k5ts1_log_newline 2006.173.03:21:03.14/k5log//k5ts2_log_newline 2006.173.03:21:03.80/k5log//k5ts3_log_newline 2006.173.03:21:04.46/k5log//k5ts4_log_newline 2006.173.03:21:04.48/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.03:21:04.48:setupk4=1 2006.173.03:21:04.48$setupk4/echo=on 2006.173.03:21:04.48$setupk4/pcalon 2006.173.03:21:04.49$pcalon/"no phase cal control is implemented here 2006.173.03:21:04.49$setupk4/"tpicd=stop 2006.173.03:21:04.49$setupk4/"rec=synch_on 2006.173.03:21:04.49$setupk4/"rec_mode=128 2006.173.03:21:04.49$setupk4/!* 2006.173.03:21:04.49$setupk4/recpk4 2006.173.03:21:04.49$recpk4/recpatch= 2006.173.03:21:04.49$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.03:21:04.49$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.03:21:04.49$setupk4/vck44 2006.173.03:21:04.49$vck44/valo=1,524.99 2006.173.03:21:04.49#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.03:21:04.49#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.03:21:04.49#ibcon#ireg 17 cls_cnt 0 2006.173.03:21:04.49#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.03:21:04.49#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.03:21:04.49#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.03:21:04.49#ibcon#enter wrdev, iclass 15, count 0 2006.173.03:21:04.49#ibcon#first serial, iclass 15, count 0 2006.173.03:21:04.49#ibcon#enter sib2, iclass 15, count 0 2006.173.03:21:04.49#ibcon#flushed, iclass 15, count 0 2006.173.03:21:04.49#ibcon#about to write, iclass 15, count 0 2006.173.03:21:04.49#ibcon#wrote, iclass 15, count 0 2006.173.03:21:04.49#ibcon#about to read 3, iclass 15, count 0 2006.173.03:21:04.51#ibcon#read 3, iclass 15, count 0 2006.173.03:21:04.51#ibcon#about to read 4, iclass 15, count 0 2006.173.03:21:04.51#ibcon#read 4, iclass 15, count 0 2006.173.03:21:04.51#ibcon#about to read 5, iclass 15, count 0 2006.173.03:21:04.51#ibcon#read 5, iclass 15, count 0 2006.173.03:21:04.51#ibcon#about to read 6, iclass 15, count 0 2006.173.03:21:04.51#ibcon#read 6, iclass 15, count 0 2006.173.03:21:04.51#ibcon#end of sib2, iclass 15, count 0 2006.173.03:21:04.51#ibcon#*mode == 0, iclass 15, count 0 2006.173.03:21:04.51#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.03:21:04.51#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.03:21:04.51#ibcon#*before write, iclass 15, count 0 2006.173.03:21:04.51#ibcon#enter sib2, iclass 15, count 0 2006.173.03:21:04.51#ibcon#flushed, iclass 15, count 0 2006.173.03:21:04.51#ibcon#about to write, iclass 15, count 0 2006.173.03:21:04.51#ibcon#wrote, iclass 15, count 0 2006.173.03:21:04.51#ibcon#about to read 3, iclass 15, count 0 2006.173.03:21:04.56#ibcon#read 3, iclass 15, count 0 2006.173.03:21:04.56#ibcon#about to read 4, iclass 15, count 0 2006.173.03:21:04.56#ibcon#read 4, iclass 15, count 0 2006.173.03:21:04.56#ibcon#about to read 5, iclass 15, count 0 2006.173.03:21:04.56#ibcon#read 5, iclass 15, count 0 2006.173.03:21:04.56#ibcon#about to read 6, iclass 15, count 0 2006.173.03:21:04.56#ibcon#read 6, iclass 15, count 0 2006.173.03:21:04.56#ibcon#end of sib2, iclass 15, count 0 2006.173.03:21:04.56#ibcon#*after write, iclass 15, count 0 2006.173.03:21:04.56#ibcon#*before return 0, iclass 15, count 0 2006.173.03:21:04.56#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.03:21:04.56#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.03:21:04.56#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.03:21:04.56#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.03:21:04.56$vck44/va=1,7 2006.173.03:21:04.56#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.03:21:04.56#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.03:21:04.56#ibcon#ireg 11 cls_cnt 2 2006.173.03:21:04.56#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.03:21:04.56#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.03:21:04.56#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.03:21:04.56#ibcon#enter wrdev, iclass 17, count 2 2006.173.03:21:04.56#ibcon#first serial, iclass 17, count 2 2006.173.03:21:04.56#ibcon#enter sib2, iclass 17, count 2 2006.173.03:21:04.56#ibcon#flushed, iclass 17, count 2 2006.173.03:21:04.56#ibcon#about to write, iclass 17, count 2 2006.173.03:21:04.56#ibcon#wrote, iclass 17, count 2 2006.173.03:21:04.56#ibcon#about to read 3, iclass 17, count 2 2006.173.03:21:04.58#ibcon#read 3, iclass 17, count 2 2006.173.03:21:04.58#ibcon#about to read 4, iclass 17, count 2 2006.173.03:21:04.58#ibcon#read 4, iclass 17, count 2 2006.173.03:21:04.58#ibcon#about to read 5, iclass 17, count 2 2006.173.03:21:04.58#ibcon#read 5, iclass 17, count 2 2006.173.03:21:04.58#ibcon#about to read 6, iclass 17, count 2 2006.173.03:21:04.58#ibcon#read 6, iclass 17, count 2 2006.173.03:21:04.58#ibcon#end of sib2, iclass 17, count 2 2006.173.03:21:04.58#ibcon#*mode == 0, iclass 17, count 2 2006.173.03:21:04.58#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.03:21:04.58#ibcon#[25=AT01-07\r\n] 2006.173.03:21:04.58#ibcon#*before write, iclass 17, count 2 2006.173.03:21:04.58#ibcon#enter sib2, iclass 17, count 2 2006.173.03:21:04.58#ibcon#flushed, iclass 17, count 2 2006.173.03:21:04.58#ibcon#about to write, iclass 17, count 2 2006.173.03:21:04.58#ibcon#wrote, iclass 17, count 2 2006.173.03:21:04.58#ibcon#about to read 3, iclass 17, count 2 2006.173.03:21:04.61#ibcon#read 3, iclass 17, count 2 2006.173.03:21:04.61#ibcon#about to read 4, iclass 17, count 2 2006.173.03:21:04.61#ibcon#read 4, iclass 17, count 2 2006.173.03:21:04.61#ibcon#about to read 5, iclass 17, count 2 2006.173.03:21:04.61#ibcon#read 5, iclass 17, count 2 2006.173.03:21:04.61#ibcon#about to read 6, iclass 17, count 2 2006.173.03:21:04.61#ibcon#read 6, iclass 17, count 2 2006.173.03:21:04.61#ibcon#end of sib2, iclass 17, count 2 2006.173.03:21:04.61#ibcon#*after write, iclass 17, count 2 2006.173.03:21:04.61#ibcon#*before return 0, iclass 17, count 2 2006.173.03:21:04.61#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.03:21:04.61#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.03:21:04.61#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.03:21:04.61#ibcon#ireg 7 cls_cnt 0 2006.173.03:21:04.61#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.03:21:04.73#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.03:21:04.73#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.03:21:04.73#ibcon#enter wrdev, iclass 17, count 0 2006.173.03:21:04.73#ibcon#first serial, iclass 17, count 0 2006.173.03:21:04.73#ibcon#enter sib2, iclass 17, count 0 2006.173.03:21:04.73#ibcon#flushed, iclass 17, count 0 2006.173.03:21:04.73#ibcon#about to write, iclass 17, count 0 2006.173.03:21:04.73#ibcon#wrote, iclass 17, count 0 2006.173.03:21:04.73#ibcon#about to read 3, iclass 17, count 0 2006.173.03:21:04.75#ibcon#read 3, iclass 17, count 0 2006.173.03:21:04.75#ibcon#about to read 4, iclass 17, count 0 2006.173.03:21:04.75#ibcon#read 4, iclass 17, count 0 2006.173.03:21:04.75#ibcon#about to read 5, iclass 17, count 0 2006.173.03:21:04.75#ibcon#read 5, iclass 17, count 0 2006.173.03:21:04.75#ibcon#about to read 6, iclass 17, count 0 2006.173.03:21:04.75#ibcon#read 6, iclass 17, count 0 2006.173.03:21:04.75#ibcon#end of sib2, iclass 17, count 0 2006.173.03:21:04.75#ibcon#*mode == 0, iclass 17, count 0 2006.173.03:21:04.75#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.03:21:04.75#ibcon#[25=USB\r\n] 2006.173.03:21:04.75#ibcon#*before write, iclass 17, count 0 2006.173.03:21:04.75#ibcon#enter sib2, iclass 17, count 0 2006.173.03:21:04.75#ibcon#flushed, iclass 17, count 0 2006.173.03:21:04.75#ibcon#about to write, iclass 17, count 0 2006.173.03:21:04.75#ibcon#wrote, iclass 17, count 0 2006.173.03:21:04.75#ibcon#about to read 3, iclass 17, count 0 2006.173.03:21:04.78#ibcon#read 3, iclass 17, count 0 2006.173.03:21:04.78#ibcon#about to read 4, iclass 17, count 0 2006.173.03:21:04.78#ibcon#read 4, iclass 17, count 0 2006.173.03:21:04.78#ibcon#about to read 5, iclass 17, count 0 2006.173.03:21:04.78#ibcon#read 5, iclass 17, count 0 2006.173.03:21:04.78#ibcon#about to read 6, iclass 17, count 0 2006.173.03:21:04.78#ibcon#read 6, iclass 17, count 0 2006.173.03:21:04.78#ibcon#end of sib2, iclass 17, count 0 2006.173.03:21:04.78#ibcon#*after write, iclass 17, count 0 2006.173.03:21:04.78#ibcon#*before return 0, iclass 17, count 0 2006.173.03:21:04.78#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.03:21:04.78#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.03:21:04.78#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.03:21:04.78#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.03:21:04.78$vck44/valo=2,534.99 2006.173.03:21:04.78#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.03:21:04.78#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.03:21:04.78#ibcon#ireg 17 cls_cnt 0 2006.173.03:21:04.78#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.03:21:04.78#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.03:21:04.78#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.03:21:04.78#ibcon#enter wrdev, iclass 19, count 0 2006.173.03:21:04.78#ibcon#first serial, iclass 19, count 0 2006.173.03:21:04.78#ibcon#enter sib2, iclass 19, count 0 2006.173.03:21:04.78#ibcon#flushed, iclass 19, count 0 2006.173.03:21:04.78#ibcon#about to write, iclass 19, count 0 2006.173.03:21:04.78#ibcon#wrote, iclass 19, count 0 2006.173.03:21:04.78#ibcon#about to read 3, iclass 19, count 0 2006.173.03:21:04.80#ibcon#read 3, iclass 19, count 0 2006.173.03:21:04.80#ibcon#about to read 4, iclass 19, count 0 2006.173.03:21:04.80#ibcon#read 4, iclass 19, count 0 2006.173.03:21:04.80#ibcon#about to read 5, iclass 19, count 0 2006.173.03:21:04.80#ibcon#read 5, iclass 19, count 0 2006.173.03:21:04.80#ibcon#about to read 6, iclass 19, count 0 2006.173.03:21:04.80#ibcon#read 6, iclass 19, count 0 2006.173.03:21:04.80#ibcon#end of sib2, iclass 19, count 0 2006.173.03:21:04.80#ibcon#*mode == 0, iclass 19, count 0 2006.173.03:21:04.80#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.03:21:04.80#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.03:21:04.80#ibcon#*before write, iclass 19, count 0 2006.173.03:21:04.80#ibcon#enter sib2, iclass 19, count 0 2006.173.03:21:04.80#ibcon#flushed, iclass 19, count 0 2006.173.03:21:04.80#ibcon#about to write, iclass 19, count 0 2006.173.03:21:04.80#ibcon#wrote, iclass 19, count 0 2006.173.03:21:04.80#ibcon#about to read 3, iclass 19, count 0 2006.173.03:21:04.84#ibcon#read 3, iclass 19, count 0 2006.173.03:21:04.84#ibcon#about to read 4, iclass 19, count 0 2006.173.03:21:04.84#ibcon#read 4, iclass 19, count 0 2006.173.03:21:04.84#ibcon#about to read 5, iclass 19, count 0 2006.173.03:21:04.84#ibcon#read 5, iclass 19, count 0 2006.173.03:21:04.84#ibcon#about to read 6, iclass 19, count 0 2006.173.03:21:04.84#ibcon#read 6, iclass 19, count 0 2006.173.03:21:04.84#ibcon#end of sib2, iclass 19, count 0 2006.173.03:21:04.84#ibcon#*after write, iclass 19, count 0 2006.173.03:21:04.84#ibcon#*before return 0, iclass 19, count 0 2006.173.03:21:04.84#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.03:21:04.84#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.03:21:04.84#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.03:21:04.84#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.03:21:04.84$vck44/va=2,6 2006.173.03:21:04.84#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.03:21:04.84#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.03:21:04.84#ibcon#ireg 11 cls_cnt 2 2006.173.03:21:04.84#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.03:21:04.90#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.03:21:04.90#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.03:21:04.90#ibcon#enter wrdev, iclass 21, count 2 2006.173.03:21:04.90#ibcon#first serial, iclass 21, count 2 2006.173.03:21:04.90#ibcon#enter sib2, iclass 21, count 2 2006.173.03:21:04.90#ibcon#flushed, iclass 21, count 2 2006.173.03:21:04.90#ibcon#about to write, iclass 21, count 2 2006.173.03:21:04.90#ibcon#wrote, iclass 21, count 2 2006.173.03:21:04.90#ibcon#about to read 3, iclass 21, count 2 2006.173.03:21:04.92#ibcon#read 3, iclass 21, count 2 2006.173.03:21:04.92#ibcon#about to read 4, iclass 21, count 2 2006.173.03:21:04.92#ibcon#read 4, iclass 21, count 2 2006.173.03:21:04.92#ibcon#about to read 5, iclass 21, count 2 2006.173.03:21:04.92#ibcon#read 5, iclass 21, count 2 2006.173.03:21:04.92#ibcon#about to read 6, iclass 21, count 2 2006.173.03:21:04.92#ibcon#read 6, iclass 21, count 2 2006.173.03:21:04.92#ibcon#end of sib2, iclass 21, count 2 2006.173.03:21:04.92#ibcon#*mode == 0, iclass 21, count 2 2006.173.03:21:04.92#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.03:21:04.92#ibcon#[25=AT02-06\r\n] 2006.173.03:21:04.92#ibcon#*before write, iclass 21, count 2 2006.173.03:21:04.92#ibcon#enter sib2, iclass 21, count 2 2006.173.03:21:04.92#ibcon#flushed, iclass 21, count 2 2006.173.03:21:04.92#ibcon#about to write, iclass 21, count 2 2006.173.03:21:04.92#ibcon#wrote, iclass 21, count 2 2006.173.03:21:04.92#ibcon#about to read 3, iclass 21, count 2 2006.173.03:21:04.95#ibcon#read 3, iclass 21, count 2 2006.173.03:21:04.95#ibcon#about to read 4, iclass 21, count 2 2006.173.03:21:04.95#ibcon#read 4, iclass 21, count 2 2006.173.03:21:04.95#ibcon#about to read 5, iclass 21, count 2 2006.173.03:21:04.95#ibcon#read 5, iclass 21, count 2 2006.173.03:21:04.95#ibcon#about to read 6, iclass 21, count 2 2006.173.03:21:04.95#ibcon#read 6, iclass 21, count 2 2006.173.03:21:04.95#ibcon#end of sib2, iclass 21, count 2 2006.173.03:21:04.95#ibcon#*after write, iclass 21, count 2 2006.173.03:21:04.95#ibcon#*before return 0, iclass 21, count 2 2006.173.03:21:04.95#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.03:21:04.95#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.03:21:04.95#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.03:21:04.95#ibcon#ireg 7 cls_cnt 0 2006.173.03:21:04.95#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.03:21:05.07#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.03:21:05.07#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.03:21:05.07#ibcon#enter wrdev, iclass 21, count 0 2006.173.03:21:05.07#ibcon#first serial, iclass 21, count 0 2006.173.03:21:05.07#ibcon#enter sib2, iclass 21, count 0 2006.173.03:21:05.07#ibcon#flushed, iclass 21, count 0 2006.173.03:21:05.07#ibcon#about to write, iclass 21, count 0 2006.173.03:21:05.07#ibcon#wrote, iclass 21, count 0 2006.173.03:21:05.07#ibcon#about to read 3, iclass 21, count 0 2006.173.03:21:05.09#ibcon#read 3, iclass 21, count 0 2006.173.03:21:05.09#ibcon#about to read 4, iclass 21, count 0 2006.173.03:21:05.09#ibcon#read 4, iclass 21, count 0 2006.173.03:21:05.09#ibcon#about to read 5, iclass 21, count 0 2006.173.03:21:05.09#ibcon#read 5, iclass 21, count 0 2006.173.03:21:05.09#ibcon#about to read 6, iclass 21, count 0 2006.173.03:21:05.09#ibcon#read 6, iclass 21, count 0 2006.173.03:21:05.09#ibcon#end of sib2, iclass 21, count 0 2006.173.03:21:05.09#ibcon#*mode == 0, iclass 21, count 0 2006.173.03:21:05.09#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.03:21:05.09#ibcon#[25=USB\r\n] 2006.173.03:21:05.09#ibcon#*before write, iclass 21, count 0 2006.173.03:21:05.09#ibcon#enter sib2, iclass 21, count 0 2006.173.03:21:05.09#ibcon#flushed, iclass 21, count 0 2006.173.03:21:05.09#ibcon#about to write, iclass 21, count 0 2006.173.03:21:05.09#ibcon#wrote, iclass 21, count 0 2006.173.03:21:05.09#ibcon#about to read 3, iclass 21, count 0 2006.173.03:21:05.12#ibcon#read 3, iclass 21, count 0 2006.173.03:21:05.12#ibcon#about to read 4, iclass 21, count 0 2006.173.03:21:05.12#ibcon#read 4, iclass 21, count 0 2006.173.03:21:05.12#ibcon#about to read 5, iclass 21, count 0 2006.173.03:21:05.12#ibcon#read 5, iclass 21, count 0 2006.173.03:21:05.12#ibcon#about to read 6, iclass 21, count 0 2006.173.03:21:05.12#ibcon#read 6, iclass 21, count 0 2006.173.03:21:05.12#ibcon#end of sib2, iclass 21, count 0 2006.173.03:21:05.12#ibcon#*after write, iclass 21, count 0 2006.173.03:21:05.12#ibcon#*before return 0, iclass 21, count 0 2006.173.03:21:05.12#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.03:21:05.12#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.03:21:05.12#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.03:21:05.12#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.03:21:05.12$vck44/valo=3,564.99 2006.173.03:21:05.12#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.03:21:05.12#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.03:21:05.12#ibcon#ireg 17 cls_cnt 0 2006.173.03:21:05.12#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.03:21:05.12#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.03:21:05.12#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.03:21:05.12#ibcon#enter wrdev, iclass 23, count 0 2006.173.03:21:05.12#ibcon#first serial, iclass 23, count 0 2006.173.03:21:05.12#ibcon#enter sib2, iclass 23, count 0 2006.173.03:21:05.12#ibcon#flushed, iclass 23, count 0 2006.173.03:21:05.12#ibcon#about to write, iclass 23, count 0 2006.173.03:21:05.12#ibcon#wrote, iclass 23, count 0 2006.173.03:21:05.12#ibcon#about to read 3, iclass 23, count 0 2006.173.03:21:05.14#ibcon#read 3, iclass 23, count 0 2006.173.03:21:05.14#ibcon#about to read 4, iclass 23, count 0 2006.173.03:21:05.14#ibcon#read 4, iclass 23, count 0 2006.173.03:21:05.14#ibcon#about to read 5, iclass 23, count 0 2006.173.03:21:05.14#ibcon#read 5, iclass 23, count 0 2006.173.03:21:05.14#ibcon#about to read 6, iclass 23, count 0 2006.173.03:21:05.14#ibcon#read 6, iclass 23, count 0 2006.173.03:21:05.14#ibcon#end of sib2, iclass 23, count 0 2006.173.03:21:05.14#ibcon#*mode == 0, iclass 23, count 0 2006.173.03:21:05.14#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.03:21:05.14#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.03:21:05.14#ibcon#*before write, iclass 23, count 0 2006.173.03:21:05.14#ibcon#enter sib2, iclass 23, count 0 2006.173.03:21:05.14#ibcon#flushed, iclass 23, count 0 2006.173.03:21:05.14#ibcon#about to write, iclass 23, count 0 2006.173.03:21:05.14#ibcon#wrote, iclass 23, count 0 2006.173.03:21:05.14#ibcon#about to read 3, iclass 23, count 0 2006.173.03:21:05.18#ibcon#read 3, iclass 23, count 0 2006.173.03:21:05.18#ibcon#about to read 4, iclass 23, count 0 2006.173.03:21:05.18#ibcon#read 4, iclass 23, count 0 2006.173.03:21:05.18#ibcon#about to read 5, iclass 23, count 0 2006.173.03:21:05.18#ibcon#read 5, iclass 23, count 0 2006.173.03:21:05.18#ibcon#about to read 6, iclass 23, count 0 2006.173.03:21:05.18#ibcon#read 6, iclass 23, count 0 2006.173.03:21:05.18#ibcon#end of sib2, iclass 23, count 0 2006.173.03:21:05.18#ibcon#*after write, iclass 23, count 0 2006.173.03:21:05.18#ibcon#*before return 0, iclass 23, count 0 2006.173.03:21:05.18#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.03:21:05.18#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.03:21:05.18#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.03:21:05.18#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.03:21:05.18$vck44/va=3,5 2006.173.03:21:05.18#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.03:21:05.18#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.03:21:05.18#ibcon#ireg 11 cls_cnt 2 2006.173.03:21:05.18#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.03:21:05.24#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.03:21:05.24#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.03:21:05.24#ibcon#enter wrdev, iclass 25, count 2 2006.173.03:21:05.24#ibcon#first serial, iclass 25, count 2 2006.173.03:21:05.24#ibcon#enter sib2, iclass 25, count 2 2006.173.03:21:05.24#ibcon#flushed, iclass 25, count 2 2006.173.03:21:05.24#ibcon#about to write, iclass 25, count 2 2006.173.03:21:05.24#ibcon#wrote, iclass 25, count 2 2006.173.03:21:05.24#ibcon#about to read 3, iclass 25, count 2 2006.173.03:21:05.26#ibcon#read 3, iclass 25, count 2 2006.173.03:21:05.26#ibcon#about to read 4, iclass 25, count 2 2006.173.03:21:05.26#ibcon#read 4, iclass 25, count 2 2006.173.03:21:05.26#ibcon#about to read 5, iclass 25, count 2 2006.173.03:21:05.26#ibcon#read 5, iclass 25, count 2 2006.173.03:21:05.26#ibcon#about to read 6, iclass 25, count 2 2006.173.03:21:05.26#ibcon#read 6, iclass 25, count 2 2006.173.03:21:05.26#ibcon#end of sib2, iclass 25, count 2 2006.173.03:21:05.26#ibcon#*mode == 0, iclass 25, count 2 2006.173.03:21:05.26#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.03:21:05.26#ibcon#[25=AT03-05\r\n] 2006.173.03:21:05.26#ibcon#*before write, iclass 25, count 2 2006.173.03:21:05.26#ibcon#enter sib2, iclass 25, count 2 2006.173.03:21:05.26#ibcon#flushed, iclass 25, count 2 2006.173.03:21:05.26#ibcon#about to write, iclass 25, count 2 2006.173.03:21:05.26#ibcon#wrote, iclass 25, count 2 2006.173.03:21:05.26#ibcon#about to read 3, iclass 25, count 2 2006.173.03:21:05.29#ibcon#read 3, iclass 25, count 2 2006.173.03:21:05.29#ibcon#about to read 4, iclass 25, count 2 2006.173.03:21:05.29#ibcon#read 4, iclass 25, count 2 2006.173.03:21:05.29#ibcon#about to read 5, iclass 25, count 2 2006.173.03:21:05.29#ibcon#read 5, iclass 25, count 2 2006.173.03:21:05.29#ibcon#about to read 6, iclass 25, count 2 2006.173.03:21:05.29#ibcon#read 6, iclass 25, count 2 2006.173.03:21:05.29#ibcon#end of sib2, iclass 25, count 2 2006.173.03:21:05.29#ibcon#*after write, iclass 25, count 2 2006.173.03:21:05.29#ibcon#*before return 0, iclass 25, count 2 2006.173.03:21:05.29#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.03:21:05.29#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.03:21:05.29#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.03:21:05.29#ibcon#ireg 7 cls_cnt 0 2006.173.03:21:05.29#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.03:21:05.41#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.03:21:05.41#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.03:21:05.41#ibcon#enter wrdev, iclass 25, count 0 2006.173.03:21:05.41#ibcon#first serial, iclass 25, count 0 2006.173.03:21:05.41#ibcon#enter sib2, iclass 25, count 0 2006.173.03:21:05.41#ibcon#flushed, iclass 25, count 0 2006.173.03:21:05.41#ibcon#about to write, iclass 25, count 0 2006.173.03:21:05.41#ibcon#wrote, iclass 25, count 0 2006.173.03:21:05.41#ibcon#about to read 3, iclass 25, count 0 2006.173.03:21:05.43#ibcon#read 3, iclass 25, count 0 2006.173.03:21:05.43#ibcon#about to read 4, iclass 25, count 0 2006.173.03:21:05.43#ibcon#read 4, iclass 25, count 0 2006.173.03:21:05.43#ibcon#about to read 5, iclass 25, count 0 2006.173.03:21:05.43#ibcon#read 5, iclass 25, count 0 2006.173.03:21:05.43#ibcon#about to read 6, iclass 25, count 0 2006.173.03:21:05.43#ibcon#read 6, iclass 25, count 0 2006.173.03:21:05.43#ibcon#end of sib2, iclass 25, count 0 2006.173.03:21:05.43#ibcon#*mode == 0, iclass 25, count 0 2006.173.03:21:05.43#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.03:21:05.43#ibcon#[25=USB\r\n] 2006.173.03:21:05.43#ibcon#*before write, iclass 25, count 0 2006.173.03:21:05.43#ibcon#enter sib2, iclass 25, count 0 2006.173.03:21:05.43#ibcon#flushed, iclass 25, count 0 2006.173.03:21:05.43#ibcon#about to write, iclass 25, count 0 2006.173.03:21:05.43#ibcon#wrote, iclass 25, count 0 2006.173.03:21:05.43#ibcon#about to read 3, iclass 25, count 0 2006.173.03:21:05.46#ibcon#read 3, iclass 25, count 0 2006.173.03:21:05.46#ibcon#about to read 4, iclass 25, count 0 2006.173.03:21:05.46#ibcon#read 4, iclass 25, count 0 2006.173.03:21:05.46#ibcon#about to read 5, iclass 25, count 0 2006.173.03:21:05.46#ibcon#read 5, iclass 25, count 0 2006.173.03:21:05.46#ibcon#about to read 6, iclass 25, count 0 2006.173.03:21:05.46#ibcon#read 6, iclass 25, count 0 2006.173.03:21:05.46#ibcon#end of sib2, iclass 25, count 0 2006.173.03:21:05.46#ibcon#*after write, iclass 25, count 0 2006.173.03:21:05.46#ibcon#*before return 0, iclass 25, count 0 2006.173.03:21:05.46#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.03:21:05.46#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.03:21:05.46#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.03:21:05.46#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.03:21:05.46$vck44/valo=4,624.99 2006.173.03:21:05.46#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.03:21:05.46#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.03:21:05.46#ibcon#ireg 17 cls_cnt 0 2006.173.03:21:05.46#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.03:21:05.46#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.03:21:05.46#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.03:21:05.46#ibcon#enter wrdev, iclass 27, count 0 2006.173.03:21:05.46#ibcon#first serial, iclass 27, count 0 2006.173.03:21:05.46#ibcon#enter sib2, iclass 27, count 0 2006.173.03:21:05.46#ibcon#flushed, iclass 27, count 0 2006.173.03:21:05.46#ibcon#about to write, iclass 27, count 0 2006.173.03:21:05.46#ibcon#wrote, iclass 27, count 0 2006.173.03:21:05.46#ibcon#about to read 3, iclass 27, count 0 2006.173.03:21:05.48#ibcon#read 3, iclass 27, count 0 2006.173.03:21:05.48#ibcon#about to read 4, iclass 27, count 0 2006.173.03:21:05.48#ibcon#read 4, iclass 27, count 0 2006.173.03:21:05.48#ibcon#about to read 5, iclass 27, count 0 2006.173.03:21:05.48#ibcon#read 5, iclass 27, count 0 2006.173.03:21:05.48#ibcon#about to read 6, iclass 27, count 0 2006.173.03:21:05.48#ibcon#read 6, iclass 27, count 0 2006.173.03:21:05.48#ibcon#end of sib2, iclass 27, count 0 2006.173.03:21:05.48#ibcon#*mode == 0, iclass 27, count 0 2006.173.03:21:05.48#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.03:21:05.48#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.03:21:05.48#ibcon#*before write, iclass 27, count 0 2006.173.03:21:05.48#ibcon#enter sib2, iclass 27, count 0 2006.173.03:21:05.48#ibcon#flushed, iclass 27, count 0 2006.173.03:21:05.48#ibcon#about to write, iclass 27, count 0 2006.173.03:21:05.48#ibcon#wrote, iclass 27, count 0 2006.173.03:21:05.48#ibcon#about to read 3, iclass 27, count 0 2006.173.03:21:05.52#ibcon#read 3, iclass 27, count 0 2006.173.03:21:05.52#ibcon#about to read 4, iclass 27, count 0 2006.173.03:21:05.52#ibcon#read 4, iclass 27, count 0 2006.173.03:21:05.52#ibcon#about to read 5, iclass 27, count 0 2006.173.03:21:05.52#ibcon#read 5, iclass 27, count 0 2006.173.03:21:05.52#ibcon#about to read 6, iclass 27, count 0 2006.173.03:21:05.52#ibcon#read 6, iclass 27, count 0 2006.173.03:21:05.52#ibcon#end of sib2, iclass 27, count 0 2006.173.03:21:05.52#ibcon#*after write, iclass 27, count 0 2006.173.03:21:05.52#ibcon#*before return 0, iclass 27, count 0 2006.173.03:21:05.52#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.03:21:05.52#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.03:21:05.52#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.03:21:05.52#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.03:21:05.52$vck44/va=4,6 2006.173.03:21:05.52#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.03:21:05.52#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.03:21:05.52#ibcon#ireg 11 cls_cnt 2 2006.173.03:21:05.52#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.03:21:05.58#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.03:21:05.58#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.03:21:05.58#ibcon#enter wrdev, iclass 29, count 2 2006.173.03:21:05.58#ibcon#first serial, iclass 29, count 2 2006.173.03:21:05.58#ibcon#enter sib2, iclass 29, count 2 2006.173.03:21:05.58#ibcon#flushed, iclass 29, count 2 2006.173.03:21:05.58#ibcon#about to write, iclass 29, count 2 2006.173.03:21:05.58#ibcon#wrote, iclass 29, count 2 2006.173.03:21:05.58#ibcon#about to read 3, iclass 29, count 2 2006.173.03:21:05.60#ibcon#read 3, iclass 29, count 2 2006.173.03:21:05.60#ibcon#about to read 4, iclass 29, count 2 2006.173.03:21:05.60#ibcon#read 4, iclass 29, count 2 2006.173.03:21:05.60#ibcon#about to read 5, iclass 29, count 2 2006.173.03:21:05.60#ibcon#read 5, iclass 29, count 2 2006.173.03:21:05.60#ibcon#about to read 6, iclass 29, count 2 2006.173.03:21:05.60#ibcon#read 6, iclass 29, count 2 2006.173.03:21:05.60#ibcon#end of sib2, iclass 29, count 2 2006.173.03:21:05.60#ibcon#*mode == 0, iclass 29, count 2 2006.173.03:21:05.60#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.03:21:05.60#ibcon#[25=AT04-06\r\n] 2006.173.03:21:05.60#ibcon#*before write, iclass 29, count 2 2006.173.03:21:05.60#ibcon#enter sib2, iclass 29, count 2 2006.173.03:21:05.60#ibcon#flushed, iclass 29, count 2 2006.173.03:21:05.60#ibcon#about to write, iclass 29, count 2 2006.173.03:21:05.60#ibcon#wrote, iclass 29, count 2 2006.173.03:21:05.60#ibcon#about to read 3, iclass 29, count 2 2006.173.03:21:05.63#ibcon#read 3, iclass 29, count 2 2006.173.03:21:05.63#ibcon#about to read 4, iclass 29, count 2 2006.173.03:21:05.63#ibcon#read 4, iclass 29, count 2 2006.173.03:21:05.63#ibcon#about to read 5, iclass 29, count 2 2006.173.03:21:05.63#ibcon#read 5, iclass 29, count 2 2006.173.03:21:05.63#ibcon#about to read 6, iclass 29, count 2 2006.173.03:21:05.63#ibcon#read 6, iclass 29, count 2 2006.173.03:21:05.63#ibcon#end of sib2, iclass 29, count 2 2006.173.03:21:05.63#ibcon#*after write, iclass 29, count 2 2006.173.03:21:05.63#ibcon#*before return 0, iclass 29, count 2 2006.173.03:21:05.63#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.03:21:05.63#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.03:21:05.63#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.03:21:05.63#ibcon#ireg 7 cls_cnt 0 2006.173.03:21:05.63#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.03:21:05.75#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.03:21:05.75#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.03:21:05.75#ibcon#enter wrdev, iclass 29, count 0 2006.173.03:21:05.75#ibcon#first serial, iclass 29, count 0 2006.173.03:21:05.75#ibcon#enter sib2, iclass 29, count 0 2006.173.03:21:05.75#ibcon#flushed, iclass 29, count 0 2006.173.03:21:05.75#ibcon#about to write, iclass 29, count 0 2006.173.03:21:05.75#ibcon#wrote, iclass 29, count 0 2006.173.03:21:05.75#ibcon#about to read 3, iclass 29, count 0 2006.173.03:21:05.77#ibcon#read 3, iclass 29, count 0 2006.173.03:21:05.77#ibcon#about to read 4, iclass 29, count 0 2006.173.03:21:05.77#ibcon#read 4, iclass 29, count 0 2006.173.03:21:05.77#ibcon#about to read 5, iclass 29, count 0 2006.173.03:21:05.77#ibcon#read 5, iclass 29, count 0 2006.173.03:21:05.77#ibcon#about to read 6, iclass 29, count 0 2006.173.03:21:05.77#ibcon#read 6, iclass 29, count 0 2006.173.03:21:05.77#ibcon#end of sib2, iclass 29, count 0 2006.173.03:21:05.77#ibcon#*mode == 0, iclass 29, count 0 2006.173.03:21:05.77#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.03:21:05.77#ibcon#[25=USB\r\n] 2006.173.03:21:05.77#ibcon#*before write, iclass 29, count 0 2006.173.03:21:05.77#ibcon#enter sib2, iclass 29, count 0 2006.173.03:21:05.77#ibcon#flushed, iclass 29, count 0 2006.173.03:21:05.77#ibcon#about to write, iclass 29, count 0 2006.173.03:21:05.77#ibcon#wrote, iclass 29, count 0 2006.173.03:21:05.77#ibcon#about to read 3, iclass 29, count 0 2006.173.03:21:05.80#ibcon#read 3, iclass 29, count 0 2006.173.03:21:05.80#ibcon#about to read 4, iclass 29, count 0 2006.173.03:21:05.80#ibcon#read 4, iclass 29, count 0 2006.173.03:21:05.80#ibcon#about to read 5, iclass 29, count 0 2006.173.03:21:05.80#ibcon#read 5, iclass 29, count 0 2006.173.03:21:05.80#ibcon#about to read 6, iclass 29, count 0 2006.173.03:21:05.80#ibcon#read 6, iclass 29, count 0 2006.173.03:21:05.80#ibcon#end of sib2, iclass 29, count 0 2006.173.03:21:05.80#ibcon#*after write, iclass 29, count 0 2006.173.03:21:05.80#ibcon#*before return 0, iclass 29, count 0 2006.173.03:21:05.80#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.03:21:05.80#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.03:21:05.80#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.03:21:05.80#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.03:21:05.80$vck44/valo=5,734.99 2006.173.03:21:05.80#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.03:21:05.80#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.03:21:05.80#ibcon#ireg 17 cls_cnt 0 2006.173.03:21:05.80#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.03:21:05.80#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.03:21:05.80#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.03:21:05.80#ibcon#enter wrdev, iclass 31, count 0 2006.173.03:21:05.80#ibcon#first serial, iclass 31, count 0 2006.173.03:21:05.80#ibcon#enter sib2, iclass 31, count 0 2006.173.03:21:05.80#ibcon#flushed, iclass 31, count 0 2006.173.03:21:05.80#ibcon#about to write, iclass 31, count 0 2006.173.03:21:05.80#ibcon#wrote, iclass 31, count 0 2006.173.03:21:05.80#ibcon#about to read 3, iclass 31, count 0 2006.173.03:21:05.82#ibcon#read 3, iclass 31, count 0 2006.173.03:21:05.82#ibcon#about to read 4, iclass 31, count 0 2006.173.03:21:05.82#ibcon#read 4, iclass 31, count 0 2006.173.03:21:05.82#ibcon#about to read 5, iclass 31, count 0 2006.173.03:21:05.82#ibcon#read 5, iclass 31, count 0 2006.173.03:21:05.82#ibcon#about to read 6, iclass 31, count 0 2006.173.03:21:05.82#ibcon#read 6, iclass 31, count 0 2006.173.03:21:05.82#ibcon#end of sib2, iclass 31, count 0 2006.173.03:21:05.82#ibcon#*mode == 0, iclass 31, count 0 2006.173.03:21:05.82#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.03:21:05.82#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.03:21:05.82#ibcon#*before write, iclass 31, count 0 2006.173.03:21:05.82#ibcon#enter sib2, iclass 31, count 0 2006.173.03:21:05.82#ibcon#flushed, iclass 31, count 0 2006.173.03:21:05.82#ibcon#about to write, iclass 31, count 0 2006.173.03:21:05.82#ibcon#wrote, iclass 31, count 0 2006.173.03:21:05.82#ibcon#about to read 3, iclass 31, count 0 2006.173.03:21:05.86#ibcon#read 3, iclass 31, count 0 2006.173.03:21:05.86#ibcon#about to read 4, iclass 31, count 0 2006.173.03:21:05.86#ibcon#read 4, iclass 31, count 0 2006.173.03:21:05.86#ibcon#about to read 5, iclass 31, count 0 2006.173.03:21:05.86#ibcon#read 5, iclass 31, count 0 2006.173.03:21:05.86#ibcon#about to read 6, iclass 31, count 0 2006.173.03:21:05.86#ibcon#read 6, iclass 31, count 0 2006.173.03:21:05.86#ibcon#end of sib2, iclass 31, count 0 2006.173.03:21:05.86#ibcon#*after write, iclass 31, count 0 2006.173.03:21:05.86#ibcon#*before return 0, iclass 31, count 0 2006.173.03:21:05.86#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.03:21:05.86#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.03:21:05.86#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.03:21:05.86#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.03:21:05.86$vck44/va=5,4 2006.173.03:21:05.86#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.173.03:21:05.86#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.173.03:21:05.86#ibcon#ireg 11 cls_cnt 2 2006.173.03:21:05.86#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.03:21:05.92#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.03:21:05.92#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.03:21:05.92#ibcon#enter wrdev, iclass 33, count 2 2006.173.03:21:05.92#ibcon#first serial, iclass 33, count 2 2006.173.03:21:05.92#ibcon#enter sib2, iclass 33, count 2 2006.173.03:21:05.92#ibcon#flushed, iclass 33, count 2 2006.173.03:21:05.92#ibcon#about to write, iclass 33, count 2 2006.173.03:21:05.92#ibcon#wrote, iclass 33, count 2 2006.173.03:21:05.92#ibcon#about to read 3, iclass 33, count 2 2006.173.03:21:05.94#ibcon#read 3, iclass 33, count 2 2006.173.03:21:05.94#ibcon#about to read 4, iclass 33, count 2 2006.173.03:21:05.94#ibcon#read 4, iclass 33, count 2 2006.173.03:21:05.94#ibcon#about to read 5, iclass 33, count 2 2006.173.03:21:05.94#ibcon#read 5, iclass 33, count 2 2006.173.03:21:05.94#ibcon#about to read 6, iclass 33, count 2 2006.173.03:21:05.94#ibcon#read 6, iclass 33, count 2 2006.173.03:21:05.94#ibcon#end of sib2, iclass 33, count 2 2006.173.03:21:05.94#ibcon#*mode == 0, iclass 33, count 2 2006.173.03:21:05.94#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.173.03:21:05.94#ibcon#[25=AT05-04\r\n] 2006.173.03:21:05.94#ibcon#*before write, iclass 33, count 2 2006.173.03:21:05.94#ibcon#enter sib2, iclass 33, count 2 2006.173.03:21:05.94#ibcon#flushed, iclass 33, count 2 2006.173.03:21:05.94#ibcon#about to write, iclass 33, count 2 2006.173.03:21:05.94#ibcon#wrote, iclass 33, count 2 2006.173.03:21:05.94#ibcon#about to read 3, iclass 33, count 2 2006.173.03:21:05.97#ibcon#read 3, iclass 33, count 2 2006.173.03:21:05.97#ibcon#about to read 4, iclass 33, count 2 2006.173.03:21:05.97#ibcon#read 4, iclass 33, count 2 2006.173.03:21:05.97#ibcon#about to read 5, iclass 33, count 2 2006.173.03:21:05.97#ibcon#read 5, iclass 33, count 2 2006.173.03:21:05.97#ibcon#about to read 6, iclass 33, count 2 2006.173.03:21:05.97#ibcon#read 6, iclass 33, count 2 2006.173.03:21:05.97#ibcon#end of sib2, iclass 33, count 2 2006.173.03:21:05.97#ibcon#*after write, iclass 33, count 2 2006.173.03:21:05.97#ibcon#*before return 0, iclass 33, count 2 2006.173.03:21:05.97#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.03:21:05.97#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.173.03:21:05.97#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.173.03:21:05.97#ibcon#ireg 7 cls_cnt 0 2006.173.03:21:05.97#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.03:21:06.09#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.03:21:06.09#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.03:21:06.09#ibcon#enter wrdev, iclass 33, count 0 2006.173.03:21:06.09#ibcon#first serial, iclass 33, count 0 2006.173.03:21:06.09#ibcon#enter sib2, iclass 33, count 0 2006.173.03:21:06.09#ibcon#flushed, iclass 33, count 0 2006.173.03:21:06.09#ibcon#about to write, iclass 33, count 0 2006.173.03:21:06.09#ibcon#wrote, iclass 33, count 0 2006.173.03:21:06.09#ibcon#about to read 3, iclass 33, count 0 2006.173.03:21:06.11#ibcon#read 3, iclass 33, count 0 2006.173.03:21:06.11#ibcon#about to read 4, iclass 33, count 0 2006.173.03:21:06.11#ibcon#read 4, iclass 33, count 0 2006.173.03:21:06.11#ibcon#about to read 5, iclass 33, count 0 2006.173.03:21:06.11#ibcon#read 5, iclass 33, count 0 2006.173.03:21:06.11#ibcon#about to read 6, iclass 33, count 0 2006.173.03:21:06.11#ibcon#read 6, iclass 33, count 0 2006.173.03:21:06.11#ibcon#end of sib2, iclass 33, count 0 2006.173.03:21:06.11#ibcon#*mode == 0, iclass 33, count 0 2006.173.03:21:06.11#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.03:21:06.11#ibcon#[25=USB\r\n] 2006.173.03:21:06.11#ibcon#*before write, iclass 33, count 0 2006.173.03:21:06.11#ibcon#enter sib2, iclass 33, count 0 2006.173.03:21:06.11#ibcon#flushed, iclass 33, count 0 2006.173.03:21:06.11#ibcon#about to write, iclass 33, count 0 2006.173.03:21:06.11#ibcon#wrote, iclass 33, count 0 2006.173.03:21:06.11#ibcon#about to read 3, iclass 33, count 0 2006.173.03:21:06.14#ibcon#read 3, iclass 33, count 0 2006.173.03:21:06.14#ibcon#about to read 4, iclass 33, count 0 2006.173.03:21:06.14#ibcon#read 4, iclass 33, count 0 2006.173.03:21:06.14#ibcon#about to read 5, iclass 33, count 0 2006.173.03:21:06.14#ibcon#read 5, iclass 33, count 0 2006.173.03:21:06.14#ibcon#about to read 6, iclass 33, count 0 2006.173.03:21:06.14#ibcon#read 6, iclass 33, count 0 2006.173.03:21:06.14#ibcon#end of sib2, iclass 33, count 0 2006.173.03:21:06.14#ibcon#*after write, iclass 33, count 0 2006.173.03:21:06.14#ibcon#*before return 0, iclass 33, count 0 2006.173.03:21:06.14#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.03:21:06.14#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.173.03:21:06.14#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.03:21:06.14#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.03:21:06.14$vck44/valo=6,814.99 2006.173.03:21:06.14#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.03:21:06.14#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.03:21:06.14#ibcon#ireg 17 cls_cnt 0 2006.173.03:21:06.14#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.03:21:06.14#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.03:21:06.14#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.03:21:06.14#ibcon#enter wrdev, iclass 35, count 0 2006.173.03:21:06.14#ibcon#first serial, iclass 35, count 0 2006.173.03:21:06.14#ibcon#enter sib2, iclass 35, count 0 2006.173.03:21:06.14#ibcon#flushed, iclass 35, count 0 2006.173.03:21:06.14#ibcon#about to write, iclass 35, count 0 2006.173.03:21:06.14#ibcon#wrote, iclass 35, count 0 2006.173.03:21:06.14#ibcon#about to read 3, iclass 35, count 0 2006.173.03:21:06.16#ibcon#read 3, iclass 35, count 0 2006.173.03:21:06.16#ibcon#about to read 4, iclass 35, count 0 2006.173.03:21:06.16#ibcon#read 4, iclass 35, count 0 2006.173.03:21:06.16#ibcon#about to read 5, iclass 35, count 0 2006.173.03:21:06.16#ibcon#read 5, iclass 35, count 0 2006.173.03:21:06.16#ibcon#about to read 6, iclass 35, count 0 2006.173.03:21:06.16#ibcon#read 6, iclass 35, count 0 2006.173.03:21:06.16#ibcon#end of sib2, iclass 35, count 0 2006.173.03:21:06.16#ibcon#*mode == 0, iclass 35, count 0 2006.173.03:21:06.16#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.03:21:06.16#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.03:21:06.16#ibcon#*before write, iclass 35, count 0 2006.173.03:21:06.16#ibcon#enter sib2, iclass 35, count 0 2006.173.03:21:06.16#ibcon#flushed, iclass 35, count 0 2006.173.03:21:06.16#ibcon#about to write, iclass 35, count 0 2006.173.03:21:06.16#ibcon#wrote, iclass 35, count 0 2006.173.03:21:06.16#ibcon#about to read 3, iclass 35, count 0 2006.173.03:21:06.20#ibcon#read 3, iclass 35, count 0 2006.173.03:21:06.20#ibcon#about to read 4, iclass 35, count 0 2006.173.03:21:06.20#ibcon#read 4, iclass 35, count 0 2006.173.03:21:06.20#ibcon#about to read 5, iclass 35, count 0 2006.173.03:21:06.20#ibcon#read 5, iclass 35, count 0 2006.173.03:21:06.20#ibcon#about to read 6, iclass 35, count 0 2006.173.03:21:06.20#ibcon#read 6, iclass 35, count 0 2006.173.03:21:06.20#ibcon#end of sib2, iclass 35, count 0 2006.173.03:21:06.20#ibcon#*after write, iclass 35, count 0 2006.173.03:21:06.20#ibcon#*before return 0, iclass 35, count 0 2006.173.03:21:06.20#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.03:21:06.20#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.03:21:06.20#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.03:21:06.20#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.03:21:06.20$vck44/va=6,3 2006.173.03:21:06.20#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.173.03:21:06.20#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.173.03:21:06.20#ibcon#ireg 11 cls_cnt 2 2006.173.03:21:06.20#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.03:21:06.26#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.03:21:06.26#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.03:21:06.26#ibcon#enter wrdev, iclass 37, count 2 2006.173.03:21:06.26#ibcon#first serial, iclass 37, count 2 2006.173.03:21:06.26#ibcon#enter sib2, iclass 37, count 2 2006.173.03:21:06.26#ibcon#flushed, iclass 37, count 2 2006.173.03:21:06.26#ibcon#about to write, iclass 37, count 2 2006.173.03:21:06.26#ibcon#wrote, iclass 37, count 2 2006.173.03:21:06.26#ibcon#about to read 3, iclass 37, count 2 2006.173.03:21:06.28#ibcon#read 3, iclass 37, count 2 2006.173.03:21:06.28#ibcon#about to read 4, iclass 37, count 2 2006.173.03:21:06.28#ibcon#read 4, iclass 37, count 2 2006.173.03:21:06.28#ibcon#about to read 5, iclass 37, count 2 2006.173.03:21:06.28#ibcon#read 5, iclass 37, count 2 2006.173.03:21:06.28#ibcon#about to read 6, iclass 37, count 2 2006.173.03:21:06.28#ibcon#read 6, iclass 37, count 2 2006.173.03:21:06.28#ibcon#end of sib2, iclass 37, count 2 2006.173.03:21:06.28#ibcon#*mode == 0, iclass 37, count 2 2006.173.03:21:06.28#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.173.03:21:06.28#ibcon#[25=AT06-03\r\n] 2006.173.03:21:06.28#ibcon#*before write, iclass 37, count 2 2006.173.03:21:06.28#ibcon#enter sib2, iclass 37, count 2 2006.173.03:21:06.28#ibcon#flushed, iclass 37, count 2 2006.173.03:21:06.28#ibcon#about to write, iclass 37, count 2 2006.173.03:21:06.28#ibcon#wrote, iclass 37, count 2 2006.173.03:21:06.28#ibcon#about to read 3, iclass 37, count 2 2006.173.03:21:06.31#ibcon#read 3, iclass 37, count 2 2006.173.03:21:06.31#ibcon#about to read 4, iclass 37, count 2 2006.173.03:21:06.31#ibcon#read 4, iclass 37, count 2 2006.173.03:21:06.31#ibcon#about to read 5, iclass 37, count 2 2006.173.03:21:06.31#ibcon#read 5, iclass 37, count 2 2006.173.03:21:06.31#ibcon#about to read 6, iclass 37, count 2 2006.173.03:21:06.31#ibcon#read 6, iclass 37, count 2 2006.173.03:21:06.31#ibcon#end of sib2, iclass 37, count 2 2006.173.03:21:06.31#ibcon#*after write, iclass 37, count 2 2006.173.03:21:06.31#ibcon#*before return 0, iclass 37, count 2 2006.173.03:21:06.31#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.03:21:06.31#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.173.03:21:06.31#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.173.03:21:06.31#ibcon#ireg 7 cls_cnt 0 2006.173.03:21:06.31#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.03:21:06.43#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.03:21:06.43#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.03:21:06.43#ibcon#enter wrdev, iclass 37, count 0 2006.173.03:21:06.43#ibcon#first serial, iclass 37, count 0 2006.173.03:21:06.43#ibcon#enter sib2, iclass 37, count 0 2006.173.03:21:06.43#ibcon#flushed, iclass 37, count 0 2006.173.03:21:06.43#ibcon#about to write, iclass 37, count 0 2006.173.03:21:06.43#ibcon#wrote, iclass 37, count 0 2006.173.03:21:06.43#ibcon#about to read 3, iclass 37, count 0 2006.173.03:21:06.45#ibcon#read 3, iclass 37, count 0 2006.173.03:21:06.45#ibcon#about to read 4, iclass 37, count 0 2006.173.03:21:06.45#ibcon#read 4, iclass 37, count 0 2006.173.03:21:06.45#ibcon#about to read 5, iclass 37, count 0 2006.173.03:21:06.45#ibcon#read 5, iclass 37, count 0 2006.173.03:21:06.45#ibcon#about to read 6, iclass 37, count 0 2006.173.03:21:06.45#ibcon#read 6, iclass 37, count 0 2006.173.03:21:06.45#ibcon#end of sib2, iclass 37, count 0 2006.173.03:21:06.45#ibcon#*mode == 0, iclass 37, count 0 2006.173.03:21:06.45#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.03:21:06.45#ibcon#[25=USB\r\n] 2006.173.03:21:06.45#ibcon#*before write, iclass 37, count 0 2006.173.03:21:06.45#ibcon#enter sib2, iclass 37, count 0 2006.173.03:21:06.45#ibcon#flushed, iclass 37, count 0 2006.173.03:21:06.45#ibcon#about to write, iclass 37, count 0 2006.173.03:21:06.45#ibcon#wrote, iclass 37, count 0 2006.173.03:21:06.45#ibcon#about to read 3, iclass 37, count 0 2006.173.03:21:06.48#ibcon#read 3, iclass 37, count 0 2006.173.03:21:06.48#ibcon#about to read 4, iclass 37, count 0 2006.173.03:21:06.48#ibcon#read 4, iclass 37, count 0 2006.173.03:21:06.48#ibcon#about to read 5, iclass 37, count 0 2006.173.03:21:06.48#ibcon#read 5, iclass 37, count 0 2006.173.03:21:06.48#ibcon#about to read 6, iclass 37, count 0 2006.173.03:21:06.48#ibcon#read 6, iclass 37, count 0 2006.173.03:21:06.48#ibcon#end of sib2, iclass 37, count 0 2006.173.03:21:06.48#ibcon#*after write, iclass 37, count 0 2006.173.03:21:06.48#ibcon#*before return 0, iclass 37, count 0 2006.173.03:21:06.48#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.03:21:06.48#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.173.03:21:06.48#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.03:21:06.48#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.03:21:06.48$vck44/valo=7,864.99 2006.173.03:21:06.48#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.03:21:06.48#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.03:21:06.48#ibcon#ireg 17 cls_cnt 0 2006.173.03:21:06.48#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.03:21:06.48#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.03:21:06.48#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.03:21:06.48#ibcon#enter wrdev, iclass 39, count 0 2006.173.03:21:06.48#ibcon#first serial, iclass 39, count 0 2006.173.03:21:06.48#ibcon#enter sib2, iclass 39, count 0 2006.173.03:21:06.48#ibcon#flushed, iclass 39, count 0 2006.173.03:21:06.48#ibcon#about to write, iclass 39, count 0 2006.173.03:21:06.48#ibcon#wrote, iclass 39, count 0 2006.173.03:21:06.48#ibcon#about to read 3, iclass 39, count 0 2006.173.03:21:06.50#ibcon#read 3, iclass 39, count 0 2006.173.03:21:06.50#ibcon#about to read 4, iclass 39, count 0 2006.173.03:21:06.50#ibcon#read 4, iclass 39, count 0 2006.173.03:21:06.50#ibcon#about to read 5, iclass 39, count 0 2006.173.03:21:06.50#ibcon#read 5, iclass 39, count 0 2006.173.03:21:06.50#ibcon#about to read 6, iclass 39, count 0 2006.173.03:21:06.50#ibcon#read 6, iclass 39, count 0 2006.173.03:21:06.50#ibcon#end of sib2, iclass 39, count 0 2006.173.03:21:06.50#ibcon#*mode == 0, iclass 39, count 0 2006.173.03:21:06.50#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.03:21:06.50#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.03:21:06.50#ibcon#*before write, iclass 39, count 0 2006.173.03:21:06.50#ibcon#enter sib2, iclass 39, count 0 2006.173.03:21:06.50#ibcon#flushed, iclass 39, count 0 2006.173.03:21:06.50#ibcon#about to write, iclass 39, count 0 2006.173.03:21:06.50#ibcon#wrote, iclass 39, count 0 2006.173.03:21:06.50#ibcon#about to read 3, iclass 39, count 0 2006.173.03:21:06.54#ibcon#read 3, iclass 39, count 0 2006.173.03:21:06.54#ibcon#about to read 4, iclass 39, count 0 2006.173.03:21:06.54#ibcon#read 4, iclass 39, count 0 2006.173.03:21:06.54#ibcon#about to read 5, iclass 39, count 0 2006.173.03:21:06.54#ibcon#read 5, iclass 39, count 0 2006.173.03:21:06.54#ibcon#about to read 6, iclass 39, count 0 2006.173.03:21:06.54#ibcon#read 6, iclass 39, count 0 2006.173.03:21:06.54#ibcon#end of sib2, iclass 39, count 0 2006.173.03:21:06.54#ibcon#*after write, iclass 39, count 0 2006.173.03:21:06.54#ibcon#*before return 0, iclass 39, count 0 2006.173.03:21:06.54#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.03:21:06.54#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.03:21:06.54#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.03:21:06.54#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.03:21:06.54$vck44/va=7,4 2006.173.03:21:06.54#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.03:21:06.54#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.03:21:06.54#ibcon#ireg 11 cls_cnt 2 2006.173.03:21:06.54#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.03:21:06.60#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.03:21:06.60#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.03:21:06.60#ibcon#enter wrdev, iclass 3, count 2 2006.173.03:21:06.60#ibcon#first serial, iclass 3, count 2 2006.173.03:21:06.60#ibcon#enter sib2, iclass 3, count 2 2006.173.03:21:06.60#ibcon#flushed, iclass 3, count 2 2006.173.03:21:06.60#ibcon#about to write, iclass 3, count 2 2006.173.03:21:06.60#ibcon#wrote, iclass 3, count 2 2006.173.03:21:06.60#ibcon#about to read 3, iclass 3, count 2 2006.173.03:21:06.62#ibcon#read 3, iclass 3, count 2 2006.173.03:21:06.62#ibcon#about to read 4, iclass 3, count 2 2006.173.03:21:06.62#ibcon#read 4, iclass 3, count 2 2006.173.03:21:06.62#ibcon#about to read 5, iclass 3, count 2 2006.173.03:21:06.62#ibcon#read 5, iclass 3, count 2 2006.173.03:21:06.62#ibcon#about to read 6, iclass 3, count 2 2006.173.03:21:06.62#ibcon#read 6, iclass 3, count 2 2006.173.03:21:06.62#ibcon#end of sib2, iclass 3, count 2 2006.173.03:21:06.62#ibcon#*mode == 0, iclass 3, count 2 2006.173.03:21:06.62#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.03:21:06.62#ibcon#[25=AT07-04\r\n] 2006.173.03:21:06.62#ibcon#*before write, iclass 3, count 2 2006.173.03:21:06.62#ibcon#enter sib2, iclass 3, count 2 2006.173.03:21:06.62#ibcon#flushed, iclass 3, count 2 2006.173.03:21:06.62#ibcon#about to write, iclass 3, count 2 2006.173.03:21:06.62#ibcon#wrote, iclass 3, count 2 2006.173.03:21:06.62#ibcon#about to read 3, iclass 3, count 2 2006.173.03:21:06.65#ibcon#read 3, iclass 3, count 2 2006.173.03:21:06.65#ibcon#about to read 4, iclass 3, count 2 2006.173.03:21:06.65#ibcon#read 4, iclass 3, count 2 2006.173.03:21:06.65#ibcon#about to read 5, iclass 3, count 2 2006.173.03:21:06.65#ibcon#read 5, iclass 3, count 2 2006.173.03:21:06.65#ibcon#about to read 6, iclass 3, count 2 2006.173.03:21:06.65#ibcon#read 6, iclass 3, count 2 2006.173.03:21:06.65#ibcon#end of sib2, iclass 3, count 2 2006.173.03:21:06.65#ibcon#*after write, iclass 3, count 2 2006.173.03:21:06.65#ibcon#*before return 0, iclass 3, count 2 2006.173.03:21:06.65#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.03:21:06.65#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.03:21:06.65#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.03:21:06.65#ibcon#ireg 7 cls_cnt 0 2006.173.03:21:06.65#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.03:21:06.68#abcon#<5=/14 1.2 2.5 22.39 851006.3\r\n> 2006.173.03:21:06.70#abcon#{5=INTERFACE CLEAR} 2006.173.03:21:06.76#abcon#[5=S1D000X0/0*\r\n] 2006.173.03:21:06.77#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.03:21:06.77#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.03:21:06.77#ibcon#enter wrdev, iclass 3, count 0 2006.173.03:21:06.77#ibcon#first serial, iclass 3, count 0 2006.173.03:21:06.77#ibcon#enter sib2, iclass 3, count 0 2006.173.03:21:06.77#ibcon#flushed, iclass 3, count 0 2006.173.03:21:06.77#ibcon#about to write, iclass 3, count 0 2006.173.03:21:06.77#ibcon#wrote, iclass 3, count 0 2006.173.03:21:06.77#ibcon#about to read 3, iclass 3, count 0 2006.173.03:21:06.79#ibcon#read 3, iclass 3, count 0 2006.173.03:21:06.79#ibcon#about to read 4, iclass 3, count 0 2006.173.03:21:06.79#ibcon#read 4, iclass 3, count 0 2006.173.03:21:06.79#ibcon#about to read 5, iclass 3, count 0 2006.173.03:21:06.79#ibcon#read 5, iclass 3, count 0 2006.173.03:21:06.79#ibcon#about to read 6, iclass 3, count 0 2006.173.03:21:06.79#ibcon#read 6, iclass 3, count 0 2006.173.03:21:06.79#ibcon#end of sib2, iclass 3, count 0 2006.173.03:21:06.79#ibcon#*mode == 0, iclass 3, count 0 2006.173.03:21:06.79#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.03:21:06.79#ibcon#[25=USB\r\n] 2006.173.03:21:06.79#ibcon#*before write, iclass 3, count 0 2006.173.03:21:06.79#ibcon#enter sib2, iclass 3, count 0 2006.173.03:21:06.79#ibcon#flushed, iclass 3, count 0 2006.173.03:21:06.79#ibcon#about to write, iclass 3, count 0 2006.173.03:21:06.79#ibcon#wrote, iclass 3, count 0 2006.173.03:21:06.79#ibcon#about to read 3, iclass 3, count 0 2006.173.03:21:06.82#ibcon#read 3, iclass 3, count 0 2006.173.03:21:06.82#ibcon#about to read 4, iclass 3, count 0 2006.173.03:21:06.82#ibcon#read 4, iclass 3, count 0 2006.173.03:21:06.82#ibcon#about to read 5, iclass 3, count 0 2006.173.03:21:06.82#ibcon#read 5, iclass 3, count 0 2006.173.03:21:06.82#ibcon#about to read 6, iclass 3, count 0 2006.173.03:21:06.82#ibcon#read 6, iclass 3, count 0 2006.173.03:21:06.82#ibcon#end of sib2, iclass 3, count 0 2006.173.03:21:06.82#ibcon#*after write, iclass 3, count 0 2006.173.03:21:06.82#ibcon#*before return 0, iclass 3, count 0 2006.173.03:21:06.82#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.03:21:06.82#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.03:21:06.82#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.03:21:06.82#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.03:21:06.82$vck44/valo=8,884.99 2006.173.03:21:06.82#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.03:21:06.82#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.03:21:06.82#ibcon#ireg 17 cls_cnt 0 2006.173.03:21:06.82#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.03:21:06.82#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.03:21:06.82#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.03:21:06.82#ibcon#enter wrdev, iclass 11, count 0 2006.173.03:21:06.82#ibcon#first serial, iclass 11, count 0 2006.173.03:21:06.82#ibcon#enter sib2, iclass 11, count 0 2006.173.03:21:06.82#ibcon#flushed, iclass 11, count 0 2006.173.03:21:06.82#ibcon#about to write, iclass 11, count 0 2006.173.03:21:06.82#ibcon#wrote, iclass 11, count 0 2006.173.03:21:06.82#ibcon#about to read 3, iclass 11, count 0 2006.173.03:21:06.84#ibcon#read 3, iclass 11, count 0 2006.173.03:21:06.84#ibcon#about to read 4, iclass 11, count 0 2006.173.03:21:06.84#ibcon#read 4, iclass 11, count 0 2006.173.03:21:06.84#ibcon#about to read 5, iclass 11, count 0 2006.173.03:21:06.84#ibcon#read 5, iclass 11, count 0 2006.173.03:21:06.84#ibcon#about to read 6, iclass 11, count 0 2006.173.03:21:06.84#ibcon#read 6, iclass 11, count 0 2006.173.03:21:06.84#ibcon#end of sib2, iclass 11, count 0 2006.173.03:21:06.84#ibcon#*mode == 0, iclass 11, count 0 2006.173.03:21:06.84#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.03:21:06.84#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.03:21:06.84#ibcon#*before write, iclass 11, count 0 2006.173.03:21:06.84#ibcon#enter sib2, iclass 11, count 0 2006.173.03:21:06.84#ibcon#flushed, iclass 11, count 0 2006.173.03:21:06.84#ibcon#about to write, iclass 11, count 0 2006.173.03:21:06.84#ibcon#wrote, iclass 11, count 0 2006.173.03:21:06.84#ibcon#about to read 3, iclass 11, count 0 2006.173.03:21:06.88#ibcon#read 3, iclass 11, count 0 2006.173.03:21:06.88#ibcon#about to read 4, iclass 11, count 0 2006.173.03:21:06.88#ibcon#read 4, iclass 11, count 0 2006.173.03:21:06.88#ibcon#about to read 5, iclass 11, count 0 2006.173.03:21:06.88#ibcon#read 5, iclass 11, count 0 2006.173.03:21:06.88#ibcon#about to read 6, iclass 11, count 0 2006.173.03:21:06.88#ibcon#read 6, iclass 11, count 0 2006.173.03:21:06.88#ibcon#end of sib2, iclass 11, count 0 2006.173.03:21:06.88#ibcon#*after write, iclass 11, count 0 2006.173.03:21:06.88#ibcon#*before return 0, iclass 11, count 0 2006.173.03:21:06.88#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.03:21:06.88#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.03:21:06.88#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.03:21:06.88#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.03:21:06.88$vck44/va=8,4 2006.173.03:21:06.88#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.173.03:21:06.88#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.173.03:21:06.88#ibcon#ireg 11 cls_cnt 2 2006.173.03:21:06.88#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.03:21:06.94#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.03:21:06.94#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.03:21:06.94#ibcon#enter wrdev, iclass 13, count 2 2006.173.03:21:06.94#ibcon#first serial, iclass 13, count 2 2006.173.03:21:06.94#ibcon#enter sib2, iclass 13, count 2 2006.173.03:21:06.94#ibcon#flushed, iclass 13, count 2 2006.173.03:21:06.94#ibcon#about to write, iclass 13, count 2 2006.173.03:21:06.94#ibcon#wrote, iclass 13, count 2 2006.173.03:21:06.94#ibcon#about to read 3, iclass 13, count 2 2006.173.03:21:06.96#ibcon#read 3, iclass 13, count 2 2006.173.03:21:06.96#ibcon#about to read 4, iclass 13, count 2 2006.173.03:21:06.96#ibcon#read 4, iclass 13, count 2 2006.173.03:21:06.96#ibcon#about to read 5, iclass 13, count 2 2006.173.03:21:06.96#ibcon#read 5, iclass 13, count 2 2006.173.03:21:06.96#ibcon#about to read 6, iclass 13, count 2 2006.173.03:21:06.96#ibcon#read 6, iclass 13, count 2 2006.173.03:21:06.96#ibcon#end of sib2, iclass 13, count 2 2006.173.03:21:06.96#ibcon#*mode == 0, iclass 13, count 2 2006.173.03:21:06.96#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.173.03:21:06.96#ibcon#[25=AT08-04\r\n] 2006.173.03:21:06.96#ibcon#*before write, iclass 13, count 2 2006.173.03:21:06.96#ibcon#enter sib2, iclass 13, count 2 2006.173.03:21:06.96#ibcon#flushed, iclass 13, count 2 2006.173.03:21:06.96#ibcon#about to write, iclass 13, count 2 2006.173.03:21:06.96#ibcon#wrote, iclass 13, count 2 2006.173.03:21:06.96#ibcon#about to read 3, iclass 13, count 2 2006.173.03:21:06.99#ibcon#read 3, iclass 13, count 2 2006.173.03:21:06.99#ibcon#about to read 4, iclass 13, count 2 2006.173.03:21:06.99#ibcon#read 4, iclass 13, count 2 2006.173.03:21:06.99#ibcon#about to read 5, iclass 13, count 2 2006.173.03:21:06.99#ibcon#read 5, iclass 13, count 2 2006.173.03:21:06.99#ibcon#about to read 6, iclass 13, count 2 2006.173.03:21:06.99#ibcon#read 6, iclass 13, count 2 2006.173.03:21:06.99#ibcon#end of sib2, iclass 13, count 2 2006.173.03:21:06.99#ibcon#*after write, iclass 13, count 2 2006.173.03:21:06.99#ibcon#*before return 0, iclass 13, count 2 2006.173.03:21:06.99#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.03:21:06.99#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.173.03:21:06.99#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.173.03:21:06.99#ibcon#ireg 7 cls_cnt 0 2006.173.03:21:06.99#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.03:21:07.11#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.03:21:07.11#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.03:21:07.11#ibcon#enter wrdev, iclass 13, count 0 2006.173.03:21:07.11#ibcon#first serial, iclass 13, count 0 2006.173.03:21:07.11#ibcon#enter sib2, iclass 13, count 0 2006.173.03:21:07.11#ibcon#flushed, iclass 13, count 0 2006.173.03:21:07.11#ibcon#about to write, iclass 13, count 0 2006.173.03:21:07.11#ibcon#wrote, iclass 13, count 0 2006.173.03:21:07.11#ibcon#about to read 3, iclass 13, count 0 2006.173.03:21:07.13#ibcon#read 3, iclass 13, count 0 2006.173.03:21:07.13#ibcon#about to read 4, iclass 13, count 0 2006.173.03:21:07.13#ibcon#read 4, iclass 13, count 0 2006.173.03:21:07.13#ibcon#about to read 5, iclass 13, count 0 2006.173.03:21:07.13#ibcon#read 5, iclass 13, count 0 2006.173.03:21:07.13#ibcon#about to read 6, iclass 13, count 0 2006.173.03:21:07.13#ibcon#read 6, iclass 13, count 0 2006.173.03:21:07.13#ibcon#end of sib2, iclass 13, count 0 2006.173.03:21:07.13#ibcon#*mode == 0, iclass 13, count 0 2006.173.03:21:07.13#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.03:21:07.13#ibcon#[25=USB\r\n] 2006.173.03:21:07.13#ibcon#*before write, iclass 13, count 0 2006.173.03:21:07.13#ibcon#enter sib2, iclass 13, count 0 2006.173.03:21:07.13#ibcon#flushed, iclass 13, count 0 2006.173.03:21:07.13#ibcon#about to write, iclass 13, count 0 2006.173.03:21:07.13#ibcon#wrote, iclass 13, count 0 2006.173.03:21:07.13#ibcon#about to read 3, iclass 13, count 0 2006.173.03:21:07.16#ibcon#read 3, iclass 13, count 0 2006.173.03:21:07.16#ibcon#about to read 4, iclass 13, count 0 2006.173.03:21:07.16#ibcon#read 4, iclass 13, count 0 2006.173.03:21:07.16#ibcon#about to read 5, iclass 13, count 0 2006.173.03:21:07.16#ibcon#read 5, iclass 13, count 0 2006.173.03:21:07.16#ibcon#about to read 6, iclass 13, count 0 2006.173.03:21:07.16#ibcon#read 6, iclass 13, count 0 2006.173.03:21:07.16#ibcon#end of sib2, iclass 13, count 0 2006.173.03:21:07.16#ibcon#*after write, iclass 13, count 0 2006.173.03:21:07.16#ibcon#*before return 0, iclass 13, count 0 2006.173.03:21:07.16#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.03:21:07.16#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.173.03:21:07.16#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.03:21:07.16#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.03:21:07.16$vck44/vblo=1,629.99 2006.173.03:21:07.16#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.03:21:07.16#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.03:21:07.16#ibcon#ireg 17 cls_cnt 0 2006.173.03:21:07.16#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.03:21:07.16#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.03:21:07.16#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.03:21:07.16#ibcon#enter wrdev, iclass 15, count 0 2006.173.03:21:07.16#ibcon#first serial, iclass 15, count 0 2006.173.03:21:07.16#ibcon#enter sib2, iclass 15, count 0 2006.173.03:21:07.16#ibcon#flushed, iclass 15, count 0 2006.173.03:21:07.16#ibcon#about to write, iclass 15, count 0 2006.173.03:21:07.16#ibcon#wrote, iclass 15, count 0 2006.173.03:21:07.16#ibcon#about to read 3, iclass 15, count 0 2006.173.03:21:07.18#ibcon#read 3, iclass 15, count 0 2006.173.03:21:07.18#ibcon#about to read 4, iclass 15, count 0 2006.173.03:21:07.18#ibcon#read 4, iclass 15, count 0 2006.173.03:21:07.18#ibcon#about to read 5, iclass 15, count 0 2006.173.03:21:07.18#ibcon#read 5, iclass 15, count 0 2006.173.03:21:07.18#ibcon#about to read 6, iclass 15, count 0 2006.173.03:21:07.18#ibcon#read 6, iclass 15, count 0 2006.173.03:21:07.18#ibcon#end of sib2, iclass 15, count 0 2006.173.03:21:07.18#ibcon#*mode == 0, iclass 15, count 0 2006.173.03:21:07.18#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.03:21:07.18#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.03:21:07.18#ibcon#*before write, iclass 15, count 0 2006.173.03:21:07.18#ibcon#enter sib2, iclass 15, count 0 2006.173.03:21:07.18#ibcon#flushed, iclass 15, count 0 2006.173.03:21:07.18#ibcon#about to write, iclass 15, count 0 2006.173.03:21:07.18#ibcon#wrote, iclass 15, count 0 2006.173.03:21:07.18#ibcon#about to read 3, iclass 15, count 0 2006.173.03:21:07.22#ibcon#read 3, iclass 15, count 0 2006.173.03:21:07.22#ibcon#about to read 4, iclass 15, count 0 2006.173.03:21:07.22#ibcon#read 4, iclass 15, count 0 2006.173.03:21:07.22#ibcon#about to read 5, iclass 15, count 0 2006.173.03:21:07.22#ibcon#read 5, iclass 15, count 0 2006.173.03:21:07.22#ibcon#about to read 6, iclass 15, count 0 2006.173.03:21:07.22#ibcon#read 6, iclass 15, count 0 2006.173.03:21:07.22#ibcon#end of sib2, iclass 15, count 0 2006.173.03:21:07.22#ibcon#*after write, iclass 15, count 0 2006.173.03:21:07.22#ibcon#*before return 0, iclass 15, count 0 2006.173.03:21:07.22#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.03:21:07.22#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.03:21:07.22#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.03:21:07.22#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.03:21:07.22$vck44/vb=1,4 2006.173.03:21:07.22#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.03:21:07.22#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.03:21:07.22#ibcon#ireg 11 cls_cnt 2 2006.173.03:21:07.22#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.03:21:07.22#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.03:21:07.22#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.03:21:07.22#ibcon#enter wrdev, iclass 17, count 2 2006.173.03:21:07.22#ibcon#first serial, iclass 17, count 2 2006.173.03:21:07.22#ibcon#enter sib2, iclass 17, count 2 2006.173.03:21:07.22#ibcon#flushed, iclass 17, count 2 2006.173.03:21:07.22#ibcon#about to write, iclass 17, count 2 2006.173.03:21:07.22#ibcon#wrote, iclass 17, count 2 2006.173.03:21:07.22#ibcon#about to read 3, iclass 17, count 2 2006.173.03:21:07.24#ibcon#read 3, iclass 17, count 2 2006.173.03:21:07.24#ibcon#about to read 4, iclass 17, count 2 2006.173.03:21:07.24#ibcon#read 4, iclass 17, count 2 2006.173.03:21:07.24#ibcon#about to read 5, iclass 17, count 2 2006.173.03:21:07.24#ibcon#read 5, iclass 17, count 2 2006.173.03:21:07.24#ibcon#about to read 6, iclass 17, count 2 2006.173.03:21:07.24#ibcon#read 6, iclass 17, count 2 2006.173.03:21:07.24#ibcon#end of sib2, iclass 17, count 2 2006.173.03:21:07.24#ibcon#*mode == 0, iclass 17, count 2 2006.173.03:21:07.24#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.03:21:07.24#ibcon#[27=AT01-04\r\n] 2006.173.03:21:07.24#ibcon#*before write, iclass 17, count 2 2006.173.03:21:07.24#ibcon#enter sib2, iclass 17, count 2 2006.173.03:21:07.24#ibcon#flushed, iclass 17, count 2 2006.173.03:21:07.24#ibcon#about to write, iclass 17, count 2 2006.173.03:21:07.24#ibcon#wrote, iclass 17, count 2 2006.173.03:21:07.24#ibcon#about to read 3, iclass 17, count 2 2006.173.03:21:07.27#ibcon#read 3, iclass 17, count 2 2006.173.03:21:07.27#ibcon#about to read 4, iclass 17, count 2 2006.173.03:21:07.27#ibcon#read 4, iclass 17, count 2 2006.173.03:21:07.27#ibcon#about to read 5, iclass 17, count 2 2006.173.03:21:07.27#ibcon#read 5, iclass 17, count 2 2006.173.03:21:07.27#ibcon#about to read 6, iclass 17, count 2 2006.173.03:21:07.27#ibcon#read 6, iclass 17, count 2 2006.173.03:21:07.27#ibcon#end of sib2, iclass 17, count 2 2006.173.03:21:07.27#ibcon#*after write, iclass 17, count 2 2006.173.03:21:07.27#ibcon#*before return 0, iclass 17, count 2 2006.173.03:21:07.27#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.03:21:07.27#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.03:21:07.27#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.03:21:07.27#ibcon#ireg 7 cls_cnt 0 2006.173.03:21:07.27#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.03:21:07.39#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.03:21:07.39#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.03:21:07.39#ibcon#enter wrdev, iclass 17, count 0 2006.173.03:21:07.39#ibcon#first serial, iclass 17, count 0 2006.173.03:21:07.39#ibcon#enter sib2, iclass 17, count 0 2006.173.03:21:07.39#ibcon#flushed, iclass 17, count 0 2006.173.03:21:07.39#ibcon#about to write, iclass 17, count 0 2006.173.03:21:07.39#ibcon#wrote, iclass 17, count 0 2006.173.03:21:07.39#ibcon#about to read 3, iclass 17, count 0 2006.173.03:21:07.41#ibcon#read 3, iclass 17, count 0 2006.173.03:21:07.41#ibcon#about to read 4, iclass 17, count 0 2006.173.03:21:07.41#ibcon#read 4, iclass 17, count 0 2006.173.03:21:07.41#ibcon#about to read 5, iclass 17, count 0 2006.173.03:21:07.41#ibcon#read 5, iclass 17, count 0 2006.173.03:21:07.41#ibcon#about to read 6, iclass 17, count 0 2006.173.03:21:07.41#ibcon#read 6, iclass 17, count 0 2006.173.03:21:07.41#ibcon#end of sib2, iclass 17, count 0 2006.173.03:21:07.41#ibcon#*mode == 0, iclass 17, count 0 2006.173.03:21:07.41#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.03:21:07.41#ibcon#[27=USB\r\n] 2006.173.03:21:07.41#ibcon#*before write, iclass 17, count 0 2006.173.03:21:07.41#ibcon#enter sib2, iclass 17, count 0 2006.173.03:21:07.41#ibcon#flushed, iclass 17, count 0 2006.173.03:21:07.41#ibcon#about to write, iclass 17, count 0 2006.173.03:21:07.41#ibcon#wrote, iclass 17, count 0 2006.173.03:21:07.41#ibcon#about to read 3, iclass 17, count 0 2006.173.03:21:07.44#ibcon#read 3, iclass 17, count 0 2006.173.03:21:07.44#ibcon#about to read 4, iclass 17, count 0 2006.173.03:21:07.44#ibcon#read 4, iclass 17, count 0 2006.173.03:21:07.44#ibcon#about to read 5, iclass 17, count 0 2006.173.03:21:07.44#ibcon#read 5, iclass 17, count 0 2006.173.03:21:07.44#ibcon#about to read 6, iclass 17, count 0 2006.173.03:21:07.44#ibcon#read 6, iclass 17, count 0 2006.173.03:21:07.44#ibcon#end of sib2, iclass 17, count 0 2006.173.03:21:07.44#ibcon#*after write, iclass 17, count 0 2006.173.03:21:07.44#ibcon#*before return 0, iclass 17, count 0 2006.173.03:21:07.44#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.03:21:07.44#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.03:21:07.44#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.03:21:07.44#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.03:21:07.44$vck44/vblo=2,634.99 2006.173.03:21:07.44#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.03:21:07.44#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.03:21:07.44#ibcon#ireg 17 cls_cnt 0 2006.173.03:21:07.44#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.03:21:07.44#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.03:21:07.44#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.03:21:07.44#ibcon#enter wrdev, iclass 19, count 0 2006.173.03:21:07.44#ibcon#first serial, iclass 19, count 0 2006.173.03:21:07.44#ibcon#enter sib2, iclass 19, count 0 2006.173.03:21:07.44#ibcon#flushed, iclass 19, count 0 2006.173.03:21:07.44#ibcon#about to write, iclass 19, count 0 2006.173.03:21:07.44#ibcon#wrote, iclass 19, count 0 2006.173.03:21:07.44#ibcon#about to read 3, iclass 19, count 0 2006.173.03:21:07.46#ibcon#read 3, iclass 19, count 0 2006.173.03:21:07.46#ibcon#about to read 4, iclass 19, count 0 2006.173.03:21:07.46#ibcon#read 4, iclass 19, count 0 2006.173.03:21:07.46#ibcon#about to read 5, iclass 19, count 0 2006.173.03:21:07.46#ibcon#read 5, iclass 19, count 0 2006.173.03:21:07.46#ibcon#about to read 6, iclass 19, count 0 2006.173.03:21:07.46#ibcon#read 6, iclass 19, count 0 2006.173.03:21:07.46#ibcon#end of sib2, iclass 19, count 0 2006.173.03:21:07.46#ibcon#*mode == 0, iclass 19, count 0 2006.173.03:21:07.46#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.03:21:07.46#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.03:21:07.46#ibcon#*before write, iclass 19, count 0 2006.173.03:21:07.46#ibcon#enter sib2, iclass 19, count 0 2006.173.03:21:07.46#ibcon#flushed, iclass 19, count 0 2006.173.03:21:07.46#ibcon#about to write, iclass 19, count 0 2006.173.03:21:07.46#ibcon#wrote, iclass 19, count 0 2006.173.03:21:07.46#ibcon#about to read 3, iclass 19, count 0 2006.173.03:21:07.50#ibcon#read 3, iclass 19, count 0 2006.173.03:21:07.50#ibcon#about to read 4, iclass 19, count 0 2006.173.03:21:07.50#ibcon#read 4, iclass 19, count 0 2006.173.03:21:07.50#ibcon#about to read 5, iclass 19, count 0 2006.173.03:21:07.50#ibcon#read 5, iclass 19, count 0 2006.173.03:21:07.50#ibcon#about to read 6, iclass 19, count 0 2006.173.03:21:07.50#ibcon#read 6, iclass 19, count 0 2006.173.03:21:07.50#ibcon#end of sib2, iclass 19, count 0 2006.173.03:21:07.50#ibcon#*after write, iclass 19, count 0 2006.173.03:21:07.50#ibcon#*before return 0, iclass 19, count 0 2006.173.03:21:07.50#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.03:21:07.50#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.03:21:07.50#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.03:21:07.50#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.03:21:07.50$vck44/vb=2,4 2006.173.03:21:07.50#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.03:21:07.50#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.03:21:07.50#ibcon#ireg 11 cls_cnt 2 2006.173.03:21:07.50#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.03:21:07.56#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.03:21:07.56#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.03:21:07.56#ibcon#enter wrdev, iclass 21, count 2 2006.173.03:21:07.56#ibcon#first serial, iclass 21, count 2 2006.173.03:21:07.56#ibcon#enter sib2, iclass 21, count 2 2006.173.03:21:07.56#ibcon#flushed, iclass 21, count 2 2006.173.03:21:07.56#ibcon#about to write, iclass 21, count 2 2006.173.03:21:07.56#ibcon#wrote, iclass 21, count 2 2006.173.03:21:07.56#ibcon#about to read 3, iclass 21, count 2 2006.173.03:21:07.58#ibcon#read 3, iclass 21, count 2 2006.173.03:21:07.58#ibcon#about to read 4, iclass 21, count 2 2006.173.03:21:07.58#ibcon#read 4, iclass 21, count 2 2006.173.03:21:07.58#ibcon#about to read 5, iclass 21, count 2 2006.173.03:21:07.58#ibcon#read 5, iclass 21, count 2 2006.173.03:21:07.58#ibcon#about to read 6, iclass 21, count 2 2006.173.03:21:07.58#ibcon#read 6, iclass 21, count 2 2006.173.03:21:07.58#ibcon#end of sib2, iclass 21, count 2 2006.173.03:21:07.58#ibcon#*mode == 0, iclass 21, count 2 2006.173.03:21:07.58#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.03:21:07.58#ibcon#[27=AT02-04\r\n] 2006.173.03:21:07.58#ibcon#*before write, iclass 21, count 2 2006.173.03:21:07.58#ibcon#enter sib2, iclass 21, count 2 2006.173.03:21:07.58#ibcon#flushed, iclass 21, count 2 2006.173.03:21:07.58#ibcon#about to write, iclass 21, count 2 2006.173.03:21:07.58#ibcon#wrote, iclass 21, count 2 2006.173.03:21:07.58#ibcon#about to read 3, iclass 21, count 2 2006.173.03:21:07.61#ibcon#read 3, iclass 21, count 2 2006.173.03:21:07.61#ibcon#about to read 4, iclass 21, count 2 2006.173.03:21:07.61#ibcon#read 4, iclass 21, count 2 2006.173.03:21:07.61#ibcon#about to read 5, iclass 21, count 2 2006.173.03:21:07.61#ibcon#read 5, iclass 21, count 2 2006.173.03:21:07.61#ibcon#about to read 6, iclass 21, count 2 2006.173.03:21:07.61#ibcon#read 6, iclass 21, count 2 2006.173.03:21:07.61#ibcon#end of sib2, iclass 21, count 2 2006.173.03:21:07.61#ibcon#*after write, iclass 21, count 2 2006.173.03:21:07.61#ibcon#*before return 0, iclass 21, count 2 2006.173.03:21:07.61#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.03:21:07.61#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.03:21:07.61#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.03:21:07.61#ibcon#ireg 7 cls_cnt 0 2006.173.03:21:07.61#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.03:21:07.73#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.03:21:07.73#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.03:21:07.73#ibcon#enter wrdev, iclass 21, count 0 2006.173.03:21:07.73#ibcon#first serial, iclass 21, count 0 2006.173.03:21:07.73#ibcon#enter sib2, iclass 21, count 0 2006.173.03:21:07.73#ibcon#flushed, iclass 21, count 0 2006.173.03:21:07.73#ibcon#about to write, iclass 21, count 0 2006.173.03:21:07.73#ibcon#wrote, iclass 21, count 0 2006.173.03:21:07.73#ibcon#about to read 3, iclass 21, count 0 2006.173.03:21:07.75#ibcon#read 3, iclass 21, count 0 2006.173.03:21:07.75#ibcon#about to read 4, iclass 21, count 0 2006.173.03:21:07.75#ibcon#read 4, iclass 21, count 0 2006.173.03:21:07.75#ibcon#about to read 5, iclass 21, count 0 2006.173.03:21:07.75#ibcon#read 5, iclass 21, count 0 2006.173.03:21:07.75#ibcon#about to read 6, iclass 21, count 0 2006.173.03:21:07.75#ibcon#read 6, iclass 21, count 0 2006.173.03:21:07.75#ibcon#end of sib2, iclass 21, count 0 2006.173.03:21:07.75#ibcon#*mode == 0, iclass 21, count 0 2006.173.03:21:07.75#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.03:21:07.75#ibcon#[27=USB\r\n] 2006.173.03:21:07.75#ibcon#*before write, iclass 21, count 0 2006.173.03:21:07.75#ibcon#enter sib2, iclass 21, count 0 2006.173.03:21:07.75#ibcon#flushed, iclass 21, count 0 2006.173.03:21:07.75#ibcon#about to write, iclass 21, count 0 2006.173.03:21:07.75#ibcon#wrote, iclass 21, count 0 2006.173.03:21:07.75#ibcon#about to read 3, iclass 21, count 0 2006.173.03:21:07.78#ibcon#read 3, iclass 21, count 0 2006.173.03:21:07.78#ibcon#about to read 4, iclass 21, count 0 2006.173.03:21:07.78#ibcon#read 4, iclass 21, count 0 2006.173.03:21:07.78#ibcon#about to read 5, iclass 21, count 0 2006.173.03:21:07.78#ibcon#read 5, iclass 21, count 0 2006.173.03:21:07.78#ibcon#about to read 6, iclass 21, count 0 2006.173.03:21:07.78#ibcon#read 6, iclass 21, count 0 2006.173.03:21:07.78#ibcon#end of sib2, iclass 21, count 0 2006.173.03:21:07.78#ibcon#*after write, iclass 21, count 0 2006.173.03:21:07.78#ibcon#*before return 0, iclass 21, count 0 2006.173.03:21:07.78#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.03:21:07.78#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.03:21:07.78#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.03:21:07.78#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.03:21:07.78$vck44/vblo=3,649.99 2006.173.03:21:07.78#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.03:21:07.78#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.03:21:07.78#ibcon#ireg 17 cls_cnt 0 2006.173.03:21:07.78#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.03:21:07.78#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.03:21:07.78#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.03:21:07.78#ibcon#enter wrdev, iclass 23, count 0 2006.173.03:21:07.78#ibcon#first serial, iclass 23, count 0 2006.173.03:21:07.78#ibcon#enter sib2, iclass 23, count 0 2006.173.03:21:07.78#ibcon#flushed, iclass 23, count 0 2006.173.03:21:07.78#ibcon#about to write, iclass 23, count 0 2006.173.03:21:07.78#ibcon#wrote, iclass 23, count 0 2006.173.03:21:07.78#ibcon#about to read 3, iclass 23, count 0 2006.173.03:21:07.80#ibcon#read 3, iclass 23, count 0 2006.173.03:21:07.80#ibcon#about to read 4, iclass 23, count 0 2006.173.03:21:07.80#ibcon#read 4, iclass 23, count 0 2006.173.03:21:07.80#ibcon#about to read 5, iclass 23, count 0 2006.173.03:21:07.80#ibcon#read 5, iclass 23, count 0 2006.173.03:21:07.80#ibcon#about to read 6, iclass 23, count 0 2006.173.03:21:07.80#ibcon#read 6, iclass 23, count 0 2006.173.03:21:07.80#ibcon#end of sib2, iclass 23, count 0 2006.173.03:21:07.80#ibcon#*mode == 0, iclass 23, count 0 2006.173.03:21:07.80#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.03:21:07.80#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.03:21:07.80#ibcon#*before write, iclass 23, count 0 2006.173.03:21:07.80#ibcon#enter sib2, iclass 23, count 0 2006.173.03:21:07.80#ibcon#flushed, iclass 23, count 0 2006.173.03:21:07.80#ibcon#about to write, iclass 23, count 0 2006.173.03:21:07.80#ibcon#wrote, iclass 23, count 0 2006.173.03:21:07.80#ibcon#about to read 3, iclass 23, count 0 2006.173.03:21:07.84#ibcon#read 3, iclass 23, count 0 2006.173.03:21:07.84#ibcon#about to read 4, iclass 23, count 0 2006.173.03:21:07.84#ibcon#read 4, iclass 23, count 0 2006.173.03:21:07.84#ibcon#about to read 5, iclass 23, count 0 2006.173.03:21:07.84#ibcon#read 5, iclass 23, count 0 2006.173.03:21:07.84#ibcon#about to read 6, iclass 23, count 0 2006.173.03:21:07.84#ibcon#read 6, iclass 23, count 0 2006.173.03:21:07.84#ibcon#end of sib2, iclass 23, count 0 2006.173.03:21:07.84#ibcon#*after write, iclass 23, count 0 2006.173.03:21:07.84#ibcon#*before return 0, iclass 23, count 0 2006.173.03:21:07.84#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.03:21:07.84#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.03:21:07.84#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.03:21:07.84#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.03:21:07.84$vck44/vb=3,4 2006.173.03:21:07.84#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.03:21:07.84#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.03:21:07.84#ibcon#ireg 11 cls_cnt 2 2006.173.03:21:07.84#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.03:21:07.90#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.03:21:07.90#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.03:21:07.90#ibcon#enter wrdev, iclass 25, count 2 2006.173.03:21:07.90#ibcon#first serial, iclass 25, count 2 2006.173.03:21:07.90#ibcon#enter sib2, iclass 25, count 2 2006.173.03:21:07.90#ibcon#flushed, iclass 25, count 2 2006.173.03:21:07.90#ibcon#about to write, iclass 25, count 2 2006.173.03:21:07.90#ibcon#wrote, iclass 25, count 2 2006.173.03:21:07.90#ibcon#about to read 3, iclass 25, count 2 2006.173.03:21:07.92#ibcon#read 3, iclass 25, count 2 2006.173.03:21:07.92#ibcon#about to read 4, iclass 25, count 2 2006.173.03:21:07.92#ibcon#read 4, iclass 25, count 2 2006.173.03:21:07.92#ibcon#about to read 5, iclass 25, count 2 2006.173.03:21:07.92#ibcon#read 5, iclass 25, count 2 2006.173.03:21:07.92#ibcon#about to read 6, iclass 25, count 2 2006.173.03:21:07.92#ibcon#read 6, iclass 25, count 2 2006.173.03:21:07.92#ibcon#end of sib2, iclass 25, count 2 2006.173.03:21:07.92#ibcon#*mode == 0, iclass 25, count 2 2006.173.03:21:07.92#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.03:21:07.92#ibcon#[27=AT03-04\r\n] 2006.173.03:21:07.92#ibcon#*before write, iclass 25, count 2 2006.173.03:21:07.92#ibcon#enter sib2, iclass 25, count 2 2006.173.03:21:07.92#ibcon#flushed, iclass 25, count 2 2006.173.03:21:07.92#ibcon#about to write, iclass 25, count 2 2006.173.03:21:07.92#ibcon#wrote, iclass 25, count 2 2006.173.03:21:07.92#ibcon#about to read 3, iclass 25, count 2 2006.173.03:21:07.95#ibcon#read 3, iclass 25, count 2 2006.173.03:21:07.95#ibcon#about to read 4, iclass 25, count 2 2006.173.03:21:07.95#ibcon#read 4, iclass 25, count 2 2006.173.03:21:07.95#ibcon#about to read 5, iclass 25, count 2 2006.173.03:21:07.95#ibcon#read 5, iclass 25, count 2 2006.173.03:21:07.95#ibcon#about to read 6, iclass 25, count 2 2006.173.03:21:07.95#ibcon#read 6, iclass 25, count 2 2006.173.03:21:07.95#ibcon#end of sib2, iclass 25, count 2 2006.173.03:21:07.95#ibcon#*after write, iclass 25, count 2 2006.173.03:21:07.95#ibcon#*before return 0, iclass 25, count 2 2006.173.03:21:07.95#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.03:21:07.95#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.03:21:07.95#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.03:21:07.95#ibcon#ireg 7 cls_cnt 0 2006.173.03:21:07.95#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.03:21:08.07#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.03:21:08.07#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.03:21:08.07#ibcon#enter wrdev, iclass 25, count 0 2006.173.03:21:08.07#ibcon#first serial, iclass 25, count 0 2006.173.03:21:08.07#ibcon#enter sib2, iclass 25, count 0 2006.173.03:21:08.07#ibcon#flushed, iclass 25, count 0 2006.173.03:21:08.07#ibcon#about to write, iclass 25, count 0 2006.173.03:21:08.07#ibcon#wrote, iclass 25, count 0 2006.173.03:21:08.07#ibcon#about to read 3, iclass 25, count 0 2006.173.03:21:08.09#ibcon#read 3, iclass 25, count 0 2006.173.03:21:08.09#ibcon#about to read 4, iclass 25, count 0 2006.173.03:21:08.09#ibcon#read 4, iclass 25, count 0 2006.173.03:21:08.09#ibcon#about to read 5, iclass 25, count 0 2006.173.03:21:08.09#ibcon#read 5, iclass 25, count 0 2006.173.03:21:08.09#ibcon#about to read 6, iclass 25, count 0 2006.173.03:21:08.09#ibcon#read 6, iclass 25, count 0 2006.173.03:21:08.09#ibcon#end of sib2, iclass 25, count 0 2006.173.03:21:08.09#ibcon#*mode == 0, iclass 25, count 0 2006.173.03:21:08.09#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.03:21:08.09#ibcon#[27=USB\r\n] 2006.173.03:21:08.09#ibcon#*before write, iclass 25, count 0 2006.173.03:21:08.09#ibcon#enter sib2, iclass 25, count 0 2006.173.03:21:08.09#ibcon#flushed, iclass 25, count 0 2006.173.03:21:08.09#ibcon#about to write, iclass 25, count 0 2006.173.03:21:08.09#ibcon#wrote, iclass 25, count 0 2006.173.03:21:08.09#ibcon#about to read 3, iclass 25, count 0 2006.173.03:21:08.12#ibcon#read 3, iclass 25, count 0 2006.173.03:21:08.12#ibcon#about to read 4, iclass 25, count 0 2006.173.03:21:08.12#ibcon#read 4, iclass 25, count 0 2006.173.03:21:08.12#ibcon#about to read 5, iclass 25, count 0 2006.173.03:21:08.12#ibcon#read 5, iclass 25, count 0 2006.173.03:21:08.12#ibcon#about to read 6, iclass 25, count 0 2006.173.03:21:08.12#ibcon#read 6, iclass 25, count 0 2006.173.03:21:08.12#ibcon#end of sib2, iclass 25, count 0 2006.173.03:21:08.12#ibcon#*after write, iclass 25, count 0 2006.173.03:21:08.12#ibcon#*before return 0, iclass 25, count 0 2006.173.03:21:08.12#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.03:21:08.12#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.03:21:08.12#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.03:21:08.12#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.03:21:08.12$vck44/vblo=4,679.99 2006.173.03:21:08.12#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.03:21:08.12#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.03:21:08.12#ibcon#ireg 17 cls_cnt 0 2006.173.03:21:08.12#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.03:21:08.12#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.03:21:08.12#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.03:21:08.12#ibcon#enter wrdev, iclass 27, count 0 2006.173.03:21:08.12#ibcon#first serial, iclass 27, count 0 2006.173.03:21:08.12#ibcon#enter sib2, iclass 27, count 0 2006.173.03:21:08.12#ibcon#flushed, iclass 27, count 0 2006.173.03:21:08.12#ibcon#about to write, iclass 27, count 0 2006.173.03:21:08.12#ibcon#wrote, iclass 27, count 0 2006.173.03:21:08.12#ibcon#about to read 3, iclass 27, count 0 2006.173.03:21:08.14#ibcon#read 3, iclass 27, count 0 2006.173.03:21:08.14#ibcon#about to read 4, iclass 27, count 0 2006.173.03:21:08.14#ibcon#read 4, iclass 27, count 0 2006.173.03:21:08.14#ibcon#about to read 5, iclass 27, count 0 2006.173.03:21:08.14#ibcon#read 5, iclass 27, count 0 2006.173.03:21:08.14#ibcon#about to read 6, iclass 27, count 0 2006.173.03:21:08.14#ibcon#read 6, iclass 27, count 0 2006.173.03:21:08.14#ibcon#end of sib2, iclass 27, count 0 2006.173.03:21:08.14#ibcon#*mode == 0, iclass 27, count 0 2006.173.03:21:08.14#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.03:21:08.14#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.03:21:08.14#ibcon#*before write, iclass 27, count 0 2006.173.03:21:08.14#ibcon#enter sib2, iclass 27, count 0 2006.173.03:21:08.14#ibcon#flushed, iclass 27, count 0 2006.173.03:21:08.14#ibcon#about to write, iclass 27, count 0 2006.173.03:21:08.14#ibcon#wrote, iclass 27, count 0 2006.173.03:21:08.14#ibcon#about to read 3, iclass 27, count 0 2006.173.03:21:08.18#ibcon#read 3, iclass 27, count 0 2006.173.03:21:08.18#ibcon#about to read 4, iclass 27, count 0 2006.173.03:21:08.18#ibcon#read 4, iclass 27, count 0 2006.173.03:21:08.18#ibcon#about to read 5, iclass 27, count 0 2006.173.03:21:08.18#ibcon#read 5, iclass 27, count 0 2006.173.03:21:08.18#ibcon#about to read 6, iclass 27, count 0 2006.173.03:21:08.18#ibcon#read 6, iclass 27, count 0 2006.173.03:21:08.18#ibcon#end of sib2, iclass 27, count 0 2006.173.03:21:08.18#ibcon#*after write, iclass 27, count 0 2006.173.03:21:08.18#ibcon#*before return 0, iclass 27, count 0 2006.173.03:21:08.18#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.03:21:08.18#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.03:21:08.18#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.03:21:08.18#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.03:21:08.18$vck44/vb=4,4 2006.173.03:21:08.18#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.03:21:08.18#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.03:21:08.18#ibcon#ireg 11 cls_cnt 2 2006.173.03:21:08.18#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.03:21:08.24#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.03:21:08.24#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.03:21:08.24#ibcon#enter wrdev, iclass 29, count 2 2006.173.03:21:08.24#ibcon#first serial, iclass 29, count 2 2006.173.03:21:08.24#ibcon#enter sib2, iclass 29, count 2 2006.173.03:21:08.24#ibcon#flushed, iclass 29, count 2 2006.173.03:21:08.24#ibcon#about to write, iclass 29, count 2 2006.173.03:21:08.24#ibcon#wrote, iclass 29, count 2 2006.173.03:21:08.24#ibcon#about to read 3, iclass 29, count 2 2006.173.03:21:08.26#ibcon#read 3, iclass 29, count 2 2006.173.03:21:08.26#ibcon#about to read 4, iclass 29, count 2 2006.173.03:21:08.26#ibcon#read 4, iclass 29, count 2 2006.173.03:21:08.26#ibcon#about to read 5, iclass 29, count 2 2006.173.03:21:08.26#ibcon#read 5, iclass 29, count 2 2006.173.03:21:08.26#ibcon#about to read 6, iclass 29, count 2 2006.173.03:21:08.26#ibcon#read 6, iclass 29, count 2 2006.173.03:21:08.26#ibcon#end of sib2, iclass 29, count 2 2006.173.03:21:08.26#ibcon#*mode == 0, iclass 29, count 2 2006.173.03:21:08.26#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.03:21:08.26#ibcon#[27=AT04-04\r\n] 2006.173.03:21:08.26#ibcon#*before write, iclass 29, count 2 2006.173.03:21:08.26#ibcon#enter sib2, iclass 29, count 2 2006.173.03:21:08.26#ibcon#flushed, iclass 29, count 2 2006.173.03:21:08.26#ibcon#about to write, iclass 29, count 2 2006.173.03:21:08.26#ibcon#wrote, iclass 29, count 2 2006.173.03:21:08.26#ibcon#about to read 3, iclass 29, count 2 2006.173.03:21:08.29#ibcon#read 3, iclass 29, count 2 2006.173.03:21:08.29#ibcon#about to read 4, iclass 29, count 2 2006.173.03:21:08.29#ibcon#read 4, iclass 29, count 2 2006.173.03:21:08.29#ibcon#about to read 5, iclass 29, count 2 2006.173.03:21:08.29#ibcon#read 5, iclass 29, count 2 2006.173.03:21:08.29#ibcon#about to read 6, iclass 29, count 2 2006.173.03:21:08.29#ibcon#read 6, iclass 29, count 2 2006.173.03:21:08.29#ibcon#end of sib2, iclass 29, count 2 2006.173.03:21:08.29#ibcon#*after write, iclass 29, count 2 2006.173.03:21:08.29#ibcon#*before return 0, iclass 29, count 2 2006.173.03:21:08.29#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.03:21:08.29#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.03:21:08.29#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.03:21:08.29#ibcon#ireg 7 cls_cnt 0 2006.173.03:21:08.29#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.03:21:08.41#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.03:21:08.41#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.03:21:08.41#ibcon#enter wrdev, iclass 29, count 0 2006.173.03:21:08.41#ibcon#first serial, iclass 29, count 0 2006.173.03:21:08.41#ibcon#enter sib2, iclass 29, count 0 2006.173.03:21:08.41#ibcon#flushed, iclass 29, count 0 2006.173.03:21:08.41#ibcon#about to write, iclass 29, count 0 2006.173.03:21:08.41#ibcon#wrote, iclass 29, count 0 2006.173.03:21:08.41#ibcon#about to read 3, iclass 29, count 0 2006.173.03:21:08.43#ibcon#read 3, iclass 29, count 0 2006.173.03:21:08.43#ibcon#about to read 4, iclass 29, count 0 2006.173.03:21:08.43#ibcon#read 4, iclass 29, count 0 2006.173.03:21:08.43#ibcon#about to read 5, iclass 29, count 0 2006.173.03:21:08.43#ibcon#read 5, iclass 29, count 0 2006.173.03:21:08.43#ibcon#about to read 6, iclass 29, count 0 2006.173.03:21:08.43#ibcon#read 6, iclass 29, count 0 2006.173.03:21:08.43#ibcon#end of sib2, iclass 29, count 0 2006.173.03:21:08.43#ibcon#*mode == 0, iclass 29, count 0 2006.173.03:21:08.43#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.03:21:08.43#ibcon#[27=USB\r\n] 2006.173.03:21:08.43#ibcon#*before write, iclass 29, count 0 2006.173.03:21:08.43#ibcon#enter sib2, iclass 29, count 0 2006.173.03:21:08.43#ibcon#flushed, iclass 29, count 0 2006.173.03:21:08.43#ibcon#about to write, iclass 29, count 0 2006.173.03:21:08.43#ibcon#wrote, iclass 29, count 0 2006.173.03:21:08.43#ibcon#about to read 3, iclass 29, count 0 2006.173.03:21:08.46#ibcon#read 3, iclass 29, count 0 2006.173.03:21:08.46#ibcon#about to read 4, iclass 29, count 0 2006.173.03:21:08.46#ibcon#read 4, iclass 29, count 0 2006.173.03:21:08.46#ibcon#about to read 5, iclass 29, count 0 2006.173.03:21:08.46#ibcon#read 5, iclass 29, count 0 2006.173.03:21:08.46#ibcon#about to read 6, iclass 29, count 0 2006.173.03:21:08.46#ibcon#read 6, iclass 29, count 0 2006.173.03:21:08.46#ibcon#end of sib2, iclass 29, count 0 2006.173.03:21:08.46#ibcon#*after write, iclass 29, count 0 2006.173.03:21:08.46#ibcon#*before return 0, iclass 29, count 0 2006.173.03:21:08.46#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.03:21:08.46#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.03:21:08.46#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.03:21:08.46#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.03:21:08.46$vck44/vblo=5,709.99 2006.173.03:21:08.46#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.03:21:08.46#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.03:21:08.46#ibcon#ireg 17 cls_cnt 0 2006.173.03:21:08.46#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.03:21:08.46#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.03:21:08.46#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.03:21:08.46#ibcon#enter wrdev, iclass 31, count 0 2006.173.03:21:08.46#ibcon#first serial, iclass 31, count 0 2006.173.03:21:08.46#ibcon#enter sib2, iclass 31, count 0 2006.173.03:21:08.46#ibcon#flushed, iclass 31, count 0 2006.173.03:21:08.46#ibcon#about to write, iclass 31, count 0 2006.173.03:21:08.46#ibcon#wrote, iclass 31, count 0 2006.173.03:21:08.46#ibcon#about to read 3, iclass 31, count 0 2006.173.03:21:08.48#ibcon#read 3, iclass 31, count 0 2006.173.03:21:08.48#ibcon#about to read 4, iclass 31, count 0 2006.173.03:21:08.48#ibcon#read 4, iclass 31, count 0 2006.173.03:21:08.48#ibcon#about to read 5, iclass 31, count 0 2006.173.03:21:08.48#ibcon#read 5, iclass 31, count 0 2006.173.03:21:08.48#ibcon#about to read 6, iclass 31, count 0 2006.173.03:21:08.48#ibcon#read 6, iclass 31, count 0 2006.173.03:21:08.48#ibcon#end of sib2, iclass 31, count 0 2006.173.03:21:08.48#ibcon#*mode == 0, iclass 31, count 0 2006.173.03:21:08.48#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.03:21:08.48#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.03:21:08.48#ibcon#*before write, iclass 31, count 0 2006.173.03:21:08.48#ibcon#enter sib2, iclass 31, count 0 2006.173.03:21:08.48#ibcon#flushed, iclass 31, count 0 2006.173.03:21:08.48#ibcon#about to write, iclass 31, count 0 2006.173.03:21:08.48#ibcon#wrote, iclass 31, count 0 2006.173.03:21:08.48#ibcon#about to read 3, iclass 31, count 0 2006.173.03:21:08.52#ibcon#read 3, iclass 31, count 0 2006.173.03:21:08.52#ibcon#about to read 4, iclass 31, count 0 2006.173.03:21:08.52#ibcon#read 4, iclass 31, count 0 2006.173.03:21:08.52#ibcon#about to read 5, iclass 31, count 0 2006.173.03:21:08.52#ibcon#read 5, iclass 31, count 0 2006.173.03:21:08.52#ibcon#about to read 6, iclass 31, count 0 2006.173.03:21:08.52#ibcon#read 6, iclass 31, count 0 2006.173.03:21:08.52#ibcon#end of sib2, iclass 31, count 0 2006.173.03:21:08.52#ibcon#*after write, iclass 31, count 0 2006.173.03:21:08.52#ibcon#*before return 0, iclass 31, count 0 2006.173.03:21:08.52#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.03:21:08.52#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.03:21:08.52#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.03:21:08.52#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.03:21:08.52$vck44/vb=5,4 2006.173.03:21:08.52#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.173.03:21:08.52#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.173.03:21:08.52#ibcon#ireg 11 cls_cnt 2 2006.173.03:21:08.52#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.03:21:08.58#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.03:21:08.58#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.03:21:08.58#ibcon#enter wrdev, iclass 33, count 2 2006.173.03:21:08.58#ibcon#first serial, iclass 33, count 2 2006.173.03:21:08.58#ibcon#enter sib2, iclass 33, count 2 2006.173.03:21:08.58#ibcon#flushed, iclass 33, count 2 2006.173.03:21:08.58#ibcon#about to write, iclass 33, count 2 2006.173.03:21:08.58#ibcon#wrote, iclass 33, count 2 2006.173.03:21:08.58#ibcon#about to read 3, iclass 33, count 2 2006.173.03:21:08.60#ibcon#read 3, iclass 33, count 2 2006.173.03:21:08.60#ibcon#about to read 4, iclass 33, count 2 2006.173.03:21:08.60#ibcon#read 4, iclass 33, count 2 2006.173.03:21:08.60#ibcon#about to read 5, iclass 33, count 2 2006.173.03:21:08.60#ibcon#read 5, iclass 33, count 2 2006.173.03:21:08.60#ibcon#about to read 6, iclass 33, count 2 2006.173.03:21:08.60#ibcon#read 6, iclass 33, count 2 2006.173.03:21:08.60#ibcon#end of sib2, iclass 33, count 2 2006.173.03:21:08.60#ibcon#*mode == 0, iclass 33, count 2 2006.173.03:21:08.60#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.173.03:21:08.60#ibcon#[27=AT05-04\r\n] 2006.173.03:21:08.60#ibcon#*before write, iclass 33, count 2 2006.173.03:21:08.60#ibcon#enter sib2, iclass 33, count 2 2006.173.03:21:08.60#ibcon#flushed, iclass 33, count 2 2006.173.03:21:08.60#ibcon#about to write, iclass 33, count 2 2006.173.03:21:08.60#ibcon#wrote, iclass 33, count 2 2006.173.03:21:08.60#ibcon#about to read 3, iclass 33, count 2 2006.173.03:21:08.63#ibcon#read 3, iclass 33, count 2 2006.173.03:21:08.63#ibcon#about to read 4, iclass 33, count 2 2006.173.03:21:08.63#ibcon#read 4, iclass 33, count 2 2006.173.03:21:08.63#ibcon#about to read 5, iclass 33, count 2 2006.173.03:21:08.63#ibcon#read 5, iclass 33, count 2 2006.173.03:21:08.63#ibcon#about to read 6, iclass 33, count 2 2006.173.03:21:08.63#ibcon#read 6, iclass 33, count 2 2006.173.03:21:08.63#ibcon#end of sib2, iclass 33, count 2 2006.173.03:21:08.63#ibcon#*after write, iclass 33, count 2 2006.173.03:21:08.63#ibcon#*before return 0, iclass 33, count 2 2006.173.03:21:08.63#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.03:21:08.63#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.173.03:21:08.63#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.173.03:21:08.63#ibcon#ireg 7 cls_cnt 0 2006.173.03:21:08.63#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.03:21:08.75#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.03:21:08.75#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.03:21:08.75#ibcon#enter wrdev, iclass 33, count 0 2006.173.03:21:08.75#ibcon#first serial, iclass 33, count 0 2006.173.03:21:08.75#ibcon#enter sib2, iclass 33, count 0 2006.173.03:21:08.75#ibcon#flushed, iclass 33, count 0 2006.173.03:21:08.75#ibcon#about to write, iclass 33, count 0 2006.173.03:21:08.75#ibcon#wrote, iclass 33, count 0 2006.173.03:21:08.75#ibcon#about to read 3, iclass 33, count 0 2006.173.03:21:08.77#ibcon#read 3, iclass 33, count 0 2006.173.03:21:08.77#ibcon#about to read 4, iclass 33, count 0 2006.173.03:21:08.77#ibcon#read 4, iclass 33, count 0 2006.173.03:21:08.77#ibcon#about to read 5, iclass 33, count 0 2006.173.03:21:08.77#ibcon#read 5, iclass 33, count 0 2006.173.03:21:08.77#ibcon#about to read 6, iclass 33, count 0 2006.173.03:21:08.77#ibcon#read 6, iclass 33, count 0 2006.173.03:21:08.77#ibcon#end of sib2, iclass 33, count 0 2006.173.03:21:08.77#ibcon#*mode == 0, iclass 33, count 0 2006.173.03:21:08.77#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.03:21:08.77#ibcon#[27=USB\r\n] 2006.173.03:21:08.77#ibcon#*before write, iclass 33, count 0 2006.173.03:21:08.77#ibcon#enter sib2, iclass 33, count 0 2006.173.03:21:08.77#ibcon#flushed, iclass 33, count 0 2006.173.03:21:08.77#ibcon#about to write, iclass 33, count 0 2006.173.03:21:08.77#ibcon#wrote, iclass 33, count 0 2006.173.03:21:08.77#ibcon#about to read 3, iclass 33, count 0 2006.173.03:21:08.80#ibcon#read 3, iclass 33, count 0 2006.173.03:21:08.80#ibcon#about to read 4, iclass 33, count 0 2006.173.03:21:08.80#ibcon#read 4, iclass 33, count 0 2006.173.03:21:08.80#ibcon#about to read 5, iclass 33, count 0 2006.173.03:21:08.80#ibcon#read 5, iclass 33, count 0 2006.173.03:21:08.80#ibcon#about to read 6, iclass 33, count 0 2006.173.03:21:08.80#ibcon#read 6, iclass 33, count 0 2006.173.03:21:08.80#ibcon#end of sib2, iclass 33, count 0 2006.173.03:21:08.80#ibcon#*after write, iclass 33, count 0 2006.173.03:21:08.80#ibcon#*before return 0, iclass 33, count 0 2006.173.03:21:08.80#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.03:21:08.80#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.173.03:21:08.80#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.03:21:08.80#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.03:21:08.80$vck44/vblo=6,719.99 2006.173.03:21:08.80#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.03:21:08.80#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.03:21:08.80#ibcon#ireg 17 cls_cnt 0 2006.173.03:21:08.80#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.03:21:08.80#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.03:21:08.80#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.03:21:08.80#ibcon#enter wrdev, iclass 35, count 0 2006.173.03:21:08.80#ibcon#first serial, iclass 35, count 0 2006.173.03:21:08.80#ibcon#enter sib2, iclass 35, count 0 2006.173.03:21:08.80#ibcon#flushed, iclass 35, count 0 2006.173.03:21:08.80#ibcon#about to write, iclass 35, count 0 2006.173.03:21:08.80#ibcon#wrote, iclass 35, count 0 2006.173.03:21:08.80#ibcon#about to read 3, iclass 35, count 0 2006.173.03:21:08.82#ibcon#read 3, iclass 35, count 0 2006.173.03:21:08.82#ibcon#about to read 4, iclass 35, count 0 2006.173.03:21:08.82#ibcon#read 4, iclass 35, count 0 2006.173.03:21:08.82#ibcon#about to read 5, iclass 35, count 0 2006.173.03:21:08.82#ibcon#read 5, iclass 35, count 0 2006.173.03:21:08.82#ibcon#about to read 6, iclass 35, count 0 2006.173.03:21:08.82#ibcon#read 6, iclass 35, count 0 2006.173.03:21:08.82#ibcon#end of sib2, iclass 35, count 0 2006.173.03:21:08.82#ibcon#*mode == 0, iclass 35, count 0 2006.173.03:21:08.82#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.03:21:08.82#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.03:21:08.82#ibcon#*before write, iclass 35, count 0 2006.173.03:21:08.82#ibcon#enter sib2, iclass 35, count 0 2006.173.03:21:08.82#ibcon#flushed, iclass 35, count 0 2006.173.03:21:08.82#ibcon#about to write, iclass 35, count 0 2006.173.03:21:08.82#ibcon#wrote, iclass 35, count 0 2006.173.03:21:08.82#ibcon#about to read 3, iclass 35, count 0 2006.173.03:21:08.86#ibcon#read 3, iclass 35, count 0 2006.173.03:21:08.86#ibcon#about to read 4, iclass 35, count 0 2006.173.03:21:08.86#ibcon#read 4, iclass 35, count 0 2006.173.03:21:08.86#ibcon#about to read 5, iclass 35, count 0 2006.173.03:21:08.86#ibcon#read 5, iclass 35, count 0 2006.173.03:21:08.86#ibcon#about to read 6, iclass 35, count 0 2006.173.03:21:08.86#ibcon#read 6, iclass 35, count 0 2006.173.03:21:08.86#ibcon#end of sib2, iclass 35, count 0 2006.173.03:21:08.86#ibcon#*after write, iclass 35, count 0 2006.173.03:21:08.86#ibcon#*before return 0, iclass 35, count 0 2006.173.03:21:08.86#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.03:21:08.86#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.03:21:08.86#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.03:21:08.86#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.03:21:08.86$vck44/vb=6,4 2006.173.03:21:08.86#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.173.03:21:08.86#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.173.03:21:08.86#ibcon#ireg 11 cls_cnt 2 2006.173.03:21:08.86#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.03:21:08.92#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.03:21:08.92#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.03:21:08.92#ibcon#enter wrdev, iclass 37, count 2 2006.173.03:21:08.92#ibcon#first serial, iclass 37, count 2 2006.173.03:21:08.92#ibcon#enter sib2, iclass 37, count 2 2006.173.03:21:08.92#ibcon#flushed, iclass 37, count 2 2006.173.03:21:08.92#ibcon#about to write, iclass 37, count 2 2006.173.03:21:08.92#ibcon#wrote, iclass 37, count 2 2006.173.03:21:08.92#ibcon#about to read 3, iclass 37, count 2 2006.173.03:21:08.94#ibcon#read 3, iclass 37, count 2 2006.173.03:21:08.94#ibcon#about to read 4, iclass 37, count 2 2006.173.03:21:08.94#ibcon#read 4, iclass 37, count 2 2006.173.03:21:08.94#ibcon#about to read 5, iclass 37, count 2 2006.173.03:21:08.94#ibcon#read 5, iclass 37, count 2 2006.173.03:21:08.94#ibcon#about to read 6, iclass 37, count 2 2006.173.03:21:08.94#ibcon#read 6, iclass 37, count 2 2006.173.03:21:08.94#ibcon#end of sib2, iclass 37, count 2 2006.173.03:21:08.94#ibcon#*mode == 0, iclass 37, count 2 2006.173.03:21:08.94#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.173.03:21:08.94#ibcon#[27=AT06-04\r\n] 2006.173.03:21:08.94#ibcon#*before write, iclass 37, count 2 2006.173.03:21:08.94#ibcon#enter sib2, iclass 37, count 2 2006.173.03:21:08.94#ibcon#flushed, iclass 37, count 2 2006.173.03:21:08.94#ibcon#about to write, iclass 37, count 2 2006.173.03:21:08.94#ibcon#wrote, iclass 37, count 2 2006.173.03:21:08.94#ibcon#about to read 3, iclass 37, count 2 2006.173.03:21:08.97#ibcon#read 3, iclass 37, count 2 2006.173.03:21:08.97#ibcon#about to read 4, iclass 37, count 2 2006.173.03:21:08.97#ibcon#read 4, iclass 37, count 2 2006.173.03:21:08.97#ibcon#about to read 5, iclass 37, count 2 2006.173.03:21:08.97#ibcon#read 5, iclass 37, count 2 2006.173.03:21:08.97#ibcon#about to read 6, iclass 37, count 2 2006.173.03:21:08.97#ibcon#read 6, iclass 37, count 2 2006.173.03:21:08.97#ibcon#end of sib2, iclass 37, count 2 2006.173.03:21:08.97#ibcon#*after write, iclass 37, count 2 2006.173.03:21:08.97#ibcon#*before return 0, iclass 37, count 2 2006.173.03:21:08.97#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.03:21:08.97#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.173.03:21:08.97#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.173.03:21:08.97#ibcon#ireg 7 cls_cnt 0 2006.173.03:21:08.97#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.03:21:09.09#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.03:21:09.09#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.03:21:09.09#ibcon#enter wrdev, iclass 37, count 0 2006.173.03:21:09.09#ibcon#first serial, iclass 37, count 0 2006.173.03:21:09.09#ibcon#enter sib2, iclass 37, count 0 2006.173.03:21:09.09#ibcon#flushed, iclass 37, count 0 2006.173.03:21:09.09#ibcon#about to write, iclass 37, count 0 2006.173.03:21:09.09#ibcon#wrote, iclass 37, count 0 2006.173.03:21:09.09#ibcon#about to read 3, iclass 37, count 0 2006.173.03:21:09.11#ibcon#read 3, iclass 37, count 0 2006.173.03:21:09.11#ibcon#about to read 4, iclass 37, count 0 2006.173.03:21:09.11#ibcon#read 4, iclass 37, count 0 2006.173.03:21:09.11#ibcon#about to read 5, iclass 37, count 0 2006.173.03:21:09.11#ibcon#read 5, iclass 37, count 0 2006.173.03:21:09.11#ibcon#about to read 6, iclass 37, count 0 2006.173.03:21:09.11#ibcon#read 6, iclass 37, count 0 2006.173.03:21:09.11#ibcon#end of sib2, iclass 37, count 0 2006.173.03:21:09.11#ibcon#*mode == 0, iclass 37, count 0 2006.173.03:21:09.11#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.03:21:09.11#ibcon#[27=USB\r\n] 2006.173.03:21:09.11#ibcon#*before write, iclass 37, count 0 2006.173.03:21:09.11#ibcon#enter sib2, iclass 37, count 0 2006.173.03:21:09.11#ibcon#flushed, iclass 37, count 0 2006.173.03:21:09.11#ibcon#about to write, iclass 37, count 0 2006.173.03:21:09.11#ibcon#wrote, iclass 37, count 0 2006.173.03:21:09.11#ibcon#about to read 3, iclass 37, count 0 2006.173.03:21:09.14#ibcon#read 3, iclass 37, count 0 2006.173.03:21:09.14#ibcon#about to read 4, iclass 37, count 0 2006.173.03:21:09.14#ibcon#read 4, iclass 37, count 0 2006.173.03:21:09.14#ibcon#about to read 5, iclass 37, count 0 2006.173.03:21:09.14#ibcon#read 5, iclass 37, count 0 2006.173.03:21:09.14#ibcon#about to read 6, iclass 37, count 0 2006.173.03:21:09.14#ibcon#read 6, iclass 37, count 0 2006.173.03:21:09.14#ibcon#end of sib2, iclass 37, count 0 2006.173.03:21:09.14#ibcon#*after write, iclass 37, count 0 2006.173.03:21:09.14#ibcon#*before return 0, iclass 37, count 0 2006.173.03:21:09.14#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.03:21:09.14#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.173.03:21:09.14#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.03:21:09.14#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.03:21:09.14$vck44/vblo=7,734.99 2006.173.03:21:09.14#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.03:21:09.14#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.03:21:09.14#ibcon#ireg 17 cls_cnt 0 2006.173.03:21:09.14#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.03:21:09.14#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.03:21:09.14#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.03:21:09.14#ibcon#enter wrdev, iclass 39, count 0 2006.173.03:21:09.14#ibcon#first serial, iclass 39, count 0 2006.173.03:21:09.14#ibcon#enter sib2, iclass 39, count 0 2006.173.03:21:09.14#ibcon#flushed, iclass 39, count 0 2006.173.03:21:09.14#ibcon#about to write, iclass 39, count 0 2006.173.03:21:09.14#ibcon#wrote, iclass 39, count 0 2006.173.03:21:09.14#ibcon#about to read 3, iclass 39, count 0 2006.173.03:21:09.16#ibcon#read 3, iclass 39, count 0 2006.173.03:21:09.16#ibcon#about to read 4, iclass 39, count 0 2006.173.03:21:09.16#ibcon#read 4, iclass 39, count 0 2006.173.03:21:09.16#ibcon#about to read 5, iclass 39, count 0 2006.173.03:21:09.16#ibcon#read 5, iclass 39, count 0 2006.173.03:21:09.16#ibcon#about to read 6, iclass 39, count 0 2006.173.03:21:09.16#ibcon#read 6, iclass 39, count 0 2006.173.03:21:09.16#ibcon#end of sib2, iclass 39, count 0 2006.173.03:21:09.16#ibcon#*mode == 0, iclass 39, count 0 2006.173.03:21:09.16#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.03:21:09.16#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.03:21:09.16#ibcon#*before write, iclass 39, count 0 2006.173.03:21:09.16#ibcon#enter sib2, iclass 39, count 0 2006.173.03:21:09.16#ibcon#flushed, iclass 39, count 0 2006.173.03:21:09.16#ibcon#about to write, iclass 39, count 0 2006.173.03:21:09.16#ibcon#wrote, iclass 39, count 0 2006.173.03:21:09.16#ibcon#about to read 3, iclass 39, count 0 2006.173.03:21:09.20#ibcon#read 3, iclass 39, count 0 2006.173.03:21:09.20#ibcon#about to read 4, iclass 39, count 0 2006.173.03:21:09.20#ibcon#read 4, iclass 39, count 0 2006.173.03:21:09.20#ibcon#about to read 5, iclass 39, count 0 2006.173.03:21:09.20#ibcon#read 5, iclass 39, count 0 2006.173.03:21:09.20#ibcon#about to read 6, iclass 39, count 0 2006.173.03:21:09.20#ibcon#read 6, iclass 39, count 0 2006.173.03:21:09.20#ibcon#end of sib2, iclass 39, count 0 2006.173.03:21:09.20#ibcon#*after write, iclass 39, count 0 2006.173.03:21:09.20#ibcon#*before return 0, iclass 39, count 0 2006.173.03:21:09.20#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.03:21:09.20#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.03:21:09.20#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.03:21:09.20#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.03:21:09.20$vck44/vb=7,4 2006.173.03:21:09.20#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.03:21:09.20#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.03:21:09.20#ibcon#ireg 11 cls_cnt 2 2006.173.03:21:09.20#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.03:21:09.26#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.03:21:09.26#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.03:21:09.26#ibcon#enter wrdev, iclass 3, count 2 2006.173.03:21:09.26#ibcon#first serial, iclass 3, count 2 2006.173.03:21:09.26#ibcon#enter sib2, iclass 3, count 2 2006.173.03:21:09.26#ibcon#flushed, iclass 3, count 2 2006.173.03:21:09.26#ibcon#about to write, iclass 3, count 2 2006.173.03:21:09.26#ibcon#wrote, iclass 3, count 2 2006.173.03:21:09.26#ibcon#about to read 3, iclass 3, count 2 2006.173.03:21:09.28#ibcon#read 3, iclass 3, count 2 2006.173.03:21:09.28#ibcon#about to read 4, iclass 3, count 2 2006.173.03:21:09.28#ibcon#read 4, iclass 3, count 2 2006.173.03:21:09.28#ibcon#about to read 5, iclass 3, count 2 2006.173.03:21:09.28#ibcon#read 5, iclass 3, count 2 2006.173.03:21:09.28#ibcon#about to read 6, iclass 3, count 2 2006.173.03:21:09.28#ibcon#read 6, iclass 3, count 2 2006.173.03:21:09.28#ibcon#end of sib2, iclass 3, count 2 2006.173.03:21:09.28#ibcon#*mode == 0, iclass 3, count 2 2006.173.03:21:09.28#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.03:21:09.28#ibcon#[27=AT07-04\r\n] 2006.173.03:21:09.28#ibcon#*before write, iclass 3, count 2 2006.173.03:21:09.28#ibcon#enter sib2, iclass 3, count 2 2006.173.03:21:09.28#ibcon#flushed, iclass 3, count 2 2006.173.03:21:09.28#ibcon#about to write, iclass 3, count 2 2006.173.03:21:09.28#ibcon#wrote, iclass 3, count 2 2006.173.03:21:09.28#ibcon#about to read 3, iclass 3, count 2 2006.173.03:21:09.31#ibcon#read 3, iclass 3, count 2 2006.173.03:21:09.31#ibcon#about to read 4, iclass 3, count 2 2006.173.03:21:09.31#ibcon#read 4, iclass 3, count 2 2006.173.03:21:09.31#ibcon#about to read 5, iclass 3, count 2 2006.173.03:21:09.31#ibcon#read 5, iclass 3, count 2 2006.173.03:21:09.31#ibcon#about to read 6, iclass 3, count 2 2006.173.03:21:09.31#ibcon#read 6, iclass 3, count 2 2006.173.03:21:09.31#ibcon#end of sib2, iclass 3, count 2 2006.173.03:21:09.31#ibcon#*after write, iclass 3, count 2 2006.173.03:21:09.31#ibcon#*before return 0, iclass 3, count 2 2006.173.03:21:09.31#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.03:21:09.31#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.03:21:09.31#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.03:21:09.31#ibcon#ireg 7 cls_cnt 0 2006.173.03:21:09.31#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.03:21:09.43#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.03:21:09.43#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.03:21:09.43#ibcon#enter wrdev, iclass 3, count 0 2006.173.03:21:09.43#ibcon#first serial, iclass 3, count 0 2006.173.03:21:09.43#ibcon#enter sib2, iclass 3, count 0 2006.173.03:21:09.43#ibcon#flushed, iclass 3, count 0 2006.173.03:21:09.43#ibcon#about to write, iclass 3, count 0 2006.173.03:21:09.43#ibcon#wrote, iclass 3, count 0 2006.173.03:21:09.43#ibcon#about to read 3, iclass 3, count 0 2006.173.03:21:09.45#ibcon#read 3, iclass 3, count 0 2006.173.03:21:09.45#ibcon#about to read 4, iclass 3, count 0 2006.173.03:21:09.45#ibcon#read 4, iclass 3, count 0 2006.173.03:21:09.45#ibcon#about to read 5, iclass 3, count 0 2006.173.03:21:09.45#ibcon#read 5, iclass 3, count 0 2006.173.03:21:09.45#ibcon#about to read 6, iclass 3, count 0 2006.173.03:21:09.45#ibcon#read 6, iclass 3, count 0 2006.173.03:21:09.45#ibcon#end of sib2, iclass 3, count 0 2006.173.03:21:09.45#ibcon#*mode == 0, iclass 3, count 0 2006.173.03:21:09.45#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.03:21:09.45#ibcon#[27=USB\r\n] 2006.173.03:21:09.45#ibcon#*before write, iclass 3, count 0 2006.173.03:21:09.45#ibcon#enter sib2, iclass 3, count 0 2006.173.03:21:09.45#ibcon#flushed, iclass 3, count 0 2006.173.03:21:09.45#ibcon#about to write, iclass 3, count 0 2006.173.03:21:09.45#ibcon#wrote, iclass 3, count 0 2006.173.03:21:09.45#ibcon#about to read 3, iclass 3, count 0 2006.173.03:21:09.48#ibcon#read 3, iclass 3, count 0 2006.173.03:21:09.48#ibcon#about to read 4, iclass 3, count 0 2006.173.03:21:09.48#ibcon#read 4, iclass 3, count 0 2006.173.03:21:09.48#ibcon#about to read 5, iclass 3, count 0 2006.173.03:21:09.48#ibcon#read 5, iclass 3, count 0 2006.173.03:21:09.48#ibcon#about to read 6, iclass 3, count 0 2006.173.03:21:09.48#ibcon#read 6, iclass 3, count 0 2006.173.03:21:09.48#ibcon#end of sib2, iclass 3, count 0 2006.173.03:21:09.48#ibcon#*after write, iclass 3, count 0 2006.173.03:21:09.48#ibcon#*before return 0, iclass 3, count 0 2006.173.03:21:09.48#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.03:21:09.48#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.03:21:09.48#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.03:21:09.48#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.03:21:09.48$vck44/vblo=8,744.99 2006.173.03:21:09.48#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.03:21:09.48#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.03:21:09.48#ibcon#ireg 17 cls_cnt 0 2006.173.03:21:09.48#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.03:21:09.48#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.03:21:09.48#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.03:21:09.48#ibcon#enter wrdev, iclass 5, count 0 2006.173.03:21:09.48#ibcon#first serial, iclass 5, count 0 2006.173.03:21:09.48#ibcon#enter sib2, iclass 5, count 0 2006.173.03:21:09.48#ibcon#flushed, iclass 5, count 0 2006.173.03:21:09.48#ibcon#about to write, iclass 5, count 0 2006.173.03:21:09.48#ibcon#wrote, iclass 5, count 0 2006.173.03:21:09.48#ibcon#about to read 3, iclass 5, count 0 2006.173.03:21:09.50#ibcon#read 3, iclass 5, count 0 2006.173.03:21:09.50#ibcon#about to read 4, iclass 5, count 0 2006.173.03:21:09.50#ibcon#read 4, iclass 5, count 0 2006.173.03:21:09.50#ibcon#about to read 5, iclass 5, count 0 2006.173.03:21:09.50#ibcon#read 5, iclass 5, count 0 2006.173.03:21:09.50#ibcon#about to read 6, iclass 5, count 0 2006.173.03:21:09.50#ibcon#read 6, iclass 5, count 0 2006.173.03:21:09.50#ibcon#end of sib2, iclass 5, count 0 2006.173.03:21:09.50#ibcon#*mode == 0, iclass 5, count 0 2006.173.03:21:09.50#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.03:21:09.50#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.03:21:09.50#ibcon#*before write, iclass 5, count 0 2006.173.03:21:09.50#ibcon#enter sib2, iclass 5, count 0 2006.173.03:21:09.50#ibcon#flushed, iclass 5, count 0 2006.173.03:21:09.50#ibcon#about to write, iclass 5, count 0 2006.173.03:21:09.50#ibcon#wrote, iclass 5, count 0 2006.173.03:21:09.50#ibcon#about to read 3, iclass 5, count 0 2006.173.03:21:09.54#ibcon#read 3, iclass 5, count 0 2006.173.03:21:09.54#ibcon#about to read 4, iclass 5, count 0 2006.173.03:21:09.54#ibcon#read 4, iclass 5, count 0 2006.173.03:21:09.54#ibcon#about to read 5, iclass 5, count 0 2006.173.03:21:09.54#ibcon#read 5, iclass 5, count 0 2006.173.03:21:09.54#ibcon#about to read 6, iclass 5, count 0 2006.173.03:21:09.54#ibcon#read 6, iclass 5, count 0 2006.173.03:21:09.54#ibcon#end of sib2, iclass 5, count 0 2006.173.03:21:09.54#ibcon#*after write, iclass 5, count 0 2006.173.03:21:09.54#ibcon#*before return 0, iclass 5, count 0 2006.173.03:21:09.54#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.03:21:09.54#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.03:21:09.54#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.03:21:09.54#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.03:21:09.54$vck44/vb=8,4 2006.173.03:21:09.54#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.173.03:21:09.54#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.173.03:21:09.54#ibcon#ireg 11 cls_cnt 2 2006.173.03:21:09.54#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.03:21:09.60#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.03:21:09.60#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.03:21:09.60#ibcon#enter wrdev, iclass 7, count 2 2006.173.03:21:09.60#ibcon#first serial, iclass 7, count 2 2006.173.03:21:09.60#ibcon#enter sib2, iclass 7, count 2 2006.173.03:21:09.60#ibcon#flushed, iclass 7, count 2 2006.173.03:21:09.60#ibcon#about to write, iclass 7, count 2 2006.173.03:21:09.60#ibcon#wrote, iclass 7, count 2 2006.173.03:21:09.60#ibcon#about to read 3, iclass 7, count 2 2006.173.03:21:09.62#ibcon#read 3, iclass 7, count 2 2006.173.03:21:09.62#ibcon#about to read 4, iclass 7, count 2 2006.173.03:21:09.62#ibcon#read 4, iclass 7, count 2 2006.173.03:21:09.62#ibcon#about to read 5, iclass 7, count 2 2006.173.03:21:09.62#ibcon#read 5, iclass 7, count 2 2006.173.03:21:09.62#ibcon#about to read 6, iclass 7, count 2 2006.173.03:21:09.62#ibcon#read 6, iclass 7, count 2 2006.173.03:21:09.62#ibcon#end of sib2, iclass 7, count 2 2006.173.03:21:09.62#ibcon#*mode == 0, iclass 7, count 2 2006.173.03:21:09.62#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.173.03:21:09.62#ibcon#[27=AT08-04\r\n] 2006.173.03:21:09.62#ibcon#*before write, iclass 7, count 2 2006.173.03:21:09.62#ibcon#enter sib2, iclass 7, count 2 2006.173.03:21:09.62#ibcon#flushed, iclass 7, count 2 2006.173.03:21:09.62#ibcon#about to write, iclass 7, count 2 2006.173.03:21:09.62#ibcon#wrote, iclass 7, count 2 2006.173.03:21:09.62#ibcon#about to read 3, iclass 7, count 2 2006.173.03:21:09.65#ibcon#read 3, iclass 7, count 2 2006.173.03:21:09.65#ibcon#about to read 4, iclass 7, count 2 2006.173.03:21:09.65#ibcon#read 4, iclass 7, count 2 2006.173.03:21:09.65#ibcon#about to read 5, iclass 7, count 2 2006.173.03:21:09.65#ibcon#read 5, iclass 7, count 2 2006.173.03:21:09.65#ibcon#about to read 6, iclass 7, count 2 2006.173.03:21:09.65#ibcon#read 6, iclass 7, count 2 2006.173.03:21:09.65#ibcon#end of sib2, iclass 7, count 2 2006.173.03:21:09.65#ibcon#*after write, iclass 7, count 2 2006.173.03:21:09.65#ibcon#*before return 0, iclass 7, count 2 2006.173.03:21:09.65#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.03:21:09.65#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.173.03:21:09.65#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.173.03:21:09.65#ibcon#ireg 7 cls_cnt 0 2006.173.03:21:09.65#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.03:21:09.77#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.03:21:09.77#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.03:21:09.77#ibcon#enter wrdev, iclass 7, count 0 2006.173.03:21:09.77#ibcon#first serial, iclass 7, count 0 2006.173.03:21:09.77#ibcon#enter sib2, iclass 7, count 0 2006.173.03:21:09.77#ibcon#flushed, iclass 7, count 0 2006.173.03:21:09.77#ibcon#about to write, iclass 7, count 0 2006.173.03:21:09.77#ibcon#wrote, iclass 7, count 0 2006.173.03:21:09.77#ibcon#about to read 3, iclass 7, count 0 2006.173.03:21:09.79#ibcon#read 3, iclass 7, count 0 2006.173.03:21:09.79#ibcon#about to read 4, iclass 7, count 0 2006.173.03:21:09.79#ibcon#read 4, iclass 7, count 0 2006.173.03:21:09.79#ibcon#about to read 5, iclass 7, count 0 2006.173.03:21:09.79#ibcon#read 5, iclass 7, count 0 2006.173.03:21:09.79#ibcon#about to read 6, iclass 7, count 0 2006.173.03:21:09.79#ibcon#read 6, iclass 7, count 0 2006.173.03:21:09.79#ibcon#end of sib2, iclass 7, count 0 2006.173.03:21:09.79#ibcon#*mode == 0, iclass 7, count 0 2006.173.03:21:09.79#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.03:21:09.79#ibcon#[27=USB\r\n] 2006.173.03:21:09.79#ibcon#*before write, iclass 7, count 0 2006.173.03:21:09.79#ibcon#enter sib2, iclass 7, count 0 2006.173.03:21:09.79#ibcon#flushed, iclass 7, count 0 2006.173.03:21:09.79#ibcon#about to write, iclass 7, count 0 2006.173.03:21:09.79#ibcon#wrote, iclass 7, count 0 2006.173.03:21:09.79#ibcon#about to read 3, iclass 7, count 0 2006.173.03:21:09.82#ibcon#read 3, iclass 7, count 0 2006.173.03:21:09.82#ibcon#about to read 4, iclass 7, count 0 2006.173.03:21:09.82#ibcon#read 4, iclass 7, count 0 2006.173.03:21:09.82#ibcon#about to read 5, iclass 7, count 0 2006.173.03:21:09.82#ibcon#read 5, iclass 7, count 0 2006.173.03:21:09.82#ibcon#about to read 6, iclass 7, count 0 2006.173.03:21:09.82#ibcon#read 6, iclass 7, count 0 2006.173.03:21:09.82#ibcon#end of sib2, iclass 7, count 0 2006.173.03:21:09.82#ibcon#*after write, iclass 7, count 0 2006.173.03:21:09.82#ibcon#*before return 0, iclass 7, count 0 2006.173.03:21:09.82#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.03:21:09.82#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.173.03:21:09.82#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.03:21:09.82#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.03:21:09.82$vck44/vabw=wide 2006.173.03:21:09.82#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.03:21:09.82#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.03:21:09.82#ibcon#ireg 8 cls_cnt 0 2006.173.03:21:09.82#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.03:21:09.82#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.03:21:09.82#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.03:21:09.82#ibcon#enter wrdev, iclass 11, count 0 2006.173.03:21:09.82#ibcon#first serial, iclass 11, count 0 2006.173.03:21:09.82#ibcon#enter sib2, iclass 11, count 0 2006.173.03:21:09.82#ibcon#flushed, iclass 11, count 0 2006.173.03:21:09.82#ibcon#about to write, iclass 11, count 0 2006.173.03:21:09.82#ibcon#wrote, iclass 11, count 0 2006.173.03:21:09.82#ibcon#about to read 3, iclass 11, count 0 2006.173.03:21:09.84#ibcon#read 3, iclass 11, count 0 2006.173.03:21:09.84#ibcon#about to read 4, iclass 11, count 0 2006.173.03:21:09.84#ibcon#read 4, iclass 11, count 0 2006.173.03:21:09.84#ibcon#about to read 5, iclass 11, count 0 2006.173.03:21:09.84#ibcon#read 5, iclass 11, count 0 2006.173.03:21:09.84#ibcon#about to read 6, iclass 11, count 0 2006.173.03:21:09.84#ibcon#read 6, iclass 11, count 0 2006.173.03:21:09.84#ibcon#end of sib2, iclass 11, count 0 2006.173.03:21:09.84#ibcon#*mode == 0, iclass 11, count 0 2006.173.03:21:09.84#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.03:21:09.84#ibcon#[25=BW32\r\n] 2006.173.03:21:09.84#ibcon#*before write, iclass 11, count 0 2006.173.03:21:09.84#ibcon#enter sib2, iclass 11, count 0 2006.173.03:21:09.84#ibcon#flushed, iclass 11, count 0 2006.173.03:21:09.84#ibcon#about to write, iclass 11, count 0 2006.173.03:21:09.84#ibcon#wrote, iclass 11, count 0 2006.173.03:21:09.84#ibcon#about to read 3, iclass 11, count 0 2006.173.03:21:09.87#ibcon#read 3, iclass 11, count 0 2006.173.03:21:09.87#ibcon#about to read 4, iclass 11, count 0 2006.173.03:21:09.87#ibcon#read 4, iclass 11, count 0 2006.173.03:21:09.87#ibcon#about to read 5, iclass 11, count 0 2006.173.03:21:09.87#ibcon#read 5, iclass 11, count 0 2006.173.03:21:09.87#ibcon#about to read 6, iclass 11, count 0 2006.173.03:21:09.87#ibcon#read 6, iclass 11, count 0 2006.173.03:21:09.87#ibcon#end of sib2, iclass 11, count 0 2006.173.03:21:09.87#ibcon#*after write, iclass 11, count 0 2006.173.03:21:09.87#ibcon#*before return 0, iclass 11, count 0 2006.173.03:21:09.87#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.03:21:09.87#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.03:21:09.87#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.03:21:09.87#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.03:21:09.87$vck44/vbbw=wide 2006.173.03:21:09.87#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.03:21:09.87#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.03:21:09.87#ibcon#ireg 8 cls_cnt 0 2006.173.03:21:09.87#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.03:21:09.94#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.03:21:09.94#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.03:21:09.94#ibcon#enter wrdev, iclass 13, count 0 2006.173.03:21:09.94#ibcon#first serial, iclass 13, count 0 2006.173.03:21:09.94#ibcon#enter sib2, iclass 13, count 0 2006.173.03:21:09.94#ibcon#flushed, iclass 13, count 0 2006.173.03:21:09.94#ibcon#about to write, iclass 13, count 0 2006.173.03:21:09.94#ibcon#wrote, iclass 13, count 0 2006.173.03:21:09.94#ibcon#about to read 3, iclass 13, count 0 2006.173.03:21:09.96#ibcon#read 3, iclass 13, count 0 2006.173.03:21:09.96#ibcon#about to read 4, iclass 13, count 0 2006.173.03:21:09.96#ibcon#read 4, iclass 13, count 0 2006.173.03:21:09.96#ibcon#about to read 5, iclass 13, count 0 2006.173.03:21:09.96#ibcon#read 5, iclass 13, count 0 2006.173.03:21:09.96#ibcon#about to read 6, iclass 13, count 0 2006.173.03:21:09.96#ibcon#read 6, iclass 13, count 0 2006.173.03:21:09.96#ibcon#end of sib2, iclass 13, count 0 2006.173.03:21:09.96#ibcon#*mode == 0, iclass 13, count 0 2006.173.03:21:09.96#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.03:21:09.96#ibcon#[27=BW32\r\n] 2006.173.03:21:09.96#ibcon#*before write, iclass 13, count 0 2006.173.03:21:09.96#ibcon#enter sib2, iclass 13, count 0 2006.173.03:21:09.96#ibcon#flushed, iclass 13, count 0 2006.173.03:21:09.96#ibcon#about to write, iclass 13, count 0 2006.173.03:21:09.96#ibcon#wrote, iclass 13, count 0 2006.173.03:21:09.96#ibcon#about to read 3, iclass 13, count 0 2006.173.03:21:09.99#ibcon#read 3, iclass 13, count 0 2006.173.03:21:09.99#ibcon#about to read 4, iclass 13, count 0 2006.173.03:21:09.99#ibcon#read 4, iclass 13, count 0 2006.173.03:21:09.99#ibcon#about to read 5, iclass 13, count 0 2006.173.03:21:09.99#ibcon#read 5, iclass 13, count 0 2006.173.03:21:09.99#ibcon#about to read 6, iclass 13, count 0 2006.173.03:21:09.99#ibcon#read 6, iclass 13, count 0 2006.173.03:21:09.99#ibcon#end of sib2, iclass 13, count 0 2006.173.03:21:09.99#ibcon#*after write, iclass 13, count 0 2006.173.03:21:09.99#ibcon#*before return 0, iclass 13, count 0 2006.173.03:21:09.99#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.03:21:09.99#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.03:21:09.99#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.03:21:09.99#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.03:21:09.99$setupk4/ifdk4 2006.173.03:21:09.99$ifdk4/lo= 2006.173.03:21:09.99$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.03:21:09.99$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.03:21:09.99$ifdk4/patch= 2006.173.03:21:09.99$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.03:21:09.99$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.03:21:09.99$setupk4/!*+20s 2006.173.03:21:16.85#abcon#<5=/14 1.2 2.5 22.39 841006.3\r\n> 2006.173.03:21:16.87#abcon#{5=INTERFACE CLEAR} 2006.173.03:21:16.93#abcon#[5=S1D000X0/0*\r\n] 2006.173.03:21:24.50$setupk4/"tpicd 2006.173.03:21:24.50$setupk4/echo=off 2006.173.03:21:24.50$setupk4/xlog=off 2006.173.03:21:24.50:!2006.173.03:21:45 2006.173.03:21:43.13#trakl#Source acquired 2006.173.03:21:43.14#flagr#flagr/antenna,acquired 2006.173.03:21:45.02:preob 2006.173.03:21:46.14/onsource/TRACKING 2006.173.03:21:46.14:!2006.173.03:21:55 2006.173.03:21:55.02:"tape 2006.173.03:21:55.02:"st=record 2006.173.03:21:55.02:data_valid=on 2006.173.03:21:55.02:midob 2006.173.03:21:56.14/onsource/TRACKING 2006.173.03:21:56.14/wx/22.40,1006.3,84 2006.173.03:21:56.22/cable/+6.5113E-03 2006.173.03:21:57.31/va/01,07,usb,yes,45,48 2006.173.03:21:57.31/va/02,06,usb,yes,44,45 2006.173.03:21:57.31/va/03,05,usb,yes,56,58 2006.173.03:21:57.31/va/04,06,usb,yes,45,48 2006.173.03:21:57.31/va/05,04,usb,yes,36,37 2006.173.03:21:57.31/va/06,03,usb,yes,50,50 2006.173.03:21:57.31/va/07,04,usb,yes,41,42 2006.173.03:21:57.31/va/08,04,usb,yes,35,42 2006.173.03:21:57.54/valo/01,524.99,yes,locked 2006.173.03:21:57.54/valo/02,534.99,yes,locked 2006.173.03:21:57.54/valo/03,564.99,yes,locked 2006.173.03:21:57.54/valo/04,624.99,yes,locked 2006.173.03:21:57.54/valo/05,734.99,yes,locked 2006.173.03:21:57.54/valo/06,814.99,yes,locked 2006.173.03:21:57.54/valo/07,864.99,yes,locked 2006.173.03:21:57.54/valo/08,884.99,yes,locked 2006.173.03:21:58.63/vb/01,04,usb,yes,33,30 2006.173.03:21:58.63/vb/02,04,usb,yes,35,35 2006.173.03:21:58.63/vb/03,04,usb,yes,32,35 2006.173.03:21:58.63/vb/04,04,usb,yes,37,36 2006.173.03:21:58.63/vb/05,04,usb,yes,35,32 2006.173.03:21:58.63/vb/06,04,usb,yes,34,35 2006.173.03:21:58.63/vb/07,04,usb,yes,34,35 2006.173.03:21:58.63/vb/08,04,usb,yes,31,34 2006.173.03:21:58.86/vblo/01,629.99,yes,locked 2006.173.03:21:58.86/vblo/02,634.99,yes,locked 2006.173.03:21:58.86/vblo/03,649.99,yes,locked 2006.173.03:21:58.86/vblo/04,679.99,yes,locked 2006.173.03:21:58.86/vblo/05,709.99,yes,locked 2006.173.03:21:58.86/vblo/06,719.99,yes,locked 2006.173.03:21:58.86/vblo/07,734.99,yes,locked 2006.173.03:21:58.86/vblo/08,744.99,yes,locked 2006.173.03:21:59.00/vabw/8 2006.173.03:21:59.15/vbbw/8 2006.173.03:21:59.25/xfe/off,on,14.7 2006.173.03:21:59.61/ifatt/23,28,28,28 2006.173.03:22:00.07/fmout-gps/S +3.92E-07 2006.173.03:22:00.12:!2006.173.03:22:35 2006.173.03:22:35.02:data_valid=off 2006.173.03:22:35.02:"et 2006.173.03:22:35.02:!+3s 2006.173.03:22:38.05:"tape 2006.173.03:22:38.06:postob 2006.173.03:22:38.27/cable/+6.5102E-03 2006.173.03:22:38.28/wx/22.42,1006.3,84 2006.173.03:22:38.33/fmout-gps/S +3.93E-07 2006.173.03:22:38.34:scan_name=173-0326,jd0606,60 2006.173.03:22:38.34:source=0727-115,073019.11,-114112.6,2000.0,cw 2006.173.03:22:40.15#flagr#flagr/antenna,new-source 2006.173.03:22:40.15:checkk5 2006.173.03:22:40.49/chk_autoobs//k5ts1/ autoobs is running! 2006.173.03:22:40.83/chk_autoobs//k5ts2/ autoobs is running! 2006.173.03:22:41.17/chk_autoobs//k5ts3/ autoobs is running! 2006.173.03:22:41.51/chk_autoobs//k5ts4/ autoobs is running! 2006.173.03:22:41.84/chk_obsdata//k5ts1/T1730321??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.03:22:42.17/chk_obsdata//k5ts2/T1730321??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.03:22:42.50/chk_obsdata//k5ts3/T1730321??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.03:22:42.84/chk_obsdata//k5ts4/T1730321??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.03:22:43.49/k5log//k5ts1_log_newline 2006.173.03:22:44.14/k5log//k5ts2_log_newline 2006.173.03:22:44.80/k5log//k5ts3_log_newline 2006.173.03:22:45.45/k5log//k5ts4_log_newline 2006.173.03:22:45.47/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.03:22:45.47:setupk4=1 2006.173.03:22:45.47$setupk4/echo=on 2006.173.03:22:45.47$setupk4/pcalon 2006.173.03:22:45.47$pcalon/"no phase cal control is implemented here 2006.173.03:22:45.47$setupk4/"tpicd=stop 2006.173.03:22:45.47$setupk4/"rec=synch_on 2006.173.03:22:45.47$setupk4/"rec_mode=128 2006.173.03:22:45.47$setupk4/!* 2006.173.03:22:45.47$setupk4/recpk4 2006.173.03:22:45.48$recpk4/recpatch= 2006.173.03:22:45.48$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.03:22:45.48$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.03:22:45.48$setupk4/vck44 2006.173.03:22:45.48$vck44/valo=1,524.99 2006.173.03:22:45.48#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.03:22:45.48#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.03:22:45.48#ibcon#ireg 17 cls_cnt 0 2006.173.03:22:45.48#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.03:22:45.48#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.03:22:45.48#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.03:22:45.48#ibcon#enter wrdev, iclass 13, count 0 2006.173.03:22:45.48#ibcon#first serial, iclass 13, count 0 2006.173.03:22:45.48#ibcon#enter sib2, iclass 13, count 0 2006.173.03:22:45.48#ibcon#flushed, iclass 13, count 0 2006.173.03:22:45.48#ibcon#about to write, iclass 13, count 0 2006.173.03:22:45.48#ibcon#wrote, iclass 13, count 0 2006.173.03:22:45.48#ibcon#about to read 3, iclass 13, count 0 2006.173.03:22:45.50#ibcon#read 3, iclass 13, count 0 2006.173.03:22:45.50#ibcon#about to read 4, iclass 13, count 0 2006.173.03:22:45.50#ibcon#read 4, iclass 13, count 0 2006.173.03:22:45.50#ibcon#about to read 5, iclass 13, count 0 2006.173.03:22:45.50#ibcon#read 5, iclass 13, count 0 2006.173.03:22:45.50#ibcon#about to read 6, iclass 13, count 0 2006.173.03:22:45.50#ibcon#read 6, iclass 13, count 0 2006.173.03:22:45.50#ibcon#end of sib2, iclass 13, count 0 2006.173.03:22:45.50#ibcon#*mode == 0, iclass 13, count 0 2006.173.03:22:45.50#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.03:22:45.50#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.03:22:45.50#ibcon#*before write, iclass 13, count 0 2006.173.03:22:45.50#ibcon#enter sib2, iclass 13, count 0 2006.173.03:22:45.50#ibcon#flushed, iclass 13, count 0 2006.173.03:22:45.50#ibcon#about to write, iclass 13, count 0 2006.173.03:22:45.50#ibcon#wrote, iclass 13, count 0 2006.173.03:22:45.50#ibcon#about to read 3, iclass 13, count 0 2006.173.03:22:45.54#ibcon#read 3, iclass 13, count 0 2006.173.03:22:45.54#ibcon#about to read 4, iclass 13, count 0 2006.173.03:22:45.54#ibcon#read 4, iclass 13, count 0 2006.173.03:22:45.54#ibcon#about to read 5, iclass 13, count 0 2006.173.03:22:45.54#ibcon#read 5, iclass 13, count 0 2006.173.03:22:45.54#ibcon#about to read 6, iclass 13, count 0 2006.173.03:22:45.54#ibcon#read 6, iclass 13, count 0 2006.173.03:22:45.54#ibcon#end of sib2, iclass 13, count 0 2006.173.03:22:45.54#ibcon#*after write, iclass 13, count 0 2006.173.03:22:45.54#ibcon#*before return 0, iclass 13, count 0 2006.173.03:22:45.54#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.03:22:45.54#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.03:22:45.54#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.03:22:45.54#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.03:22:45.55$vck44/va=1,7 2006.173.03:22:45.55#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.03:22:45.55#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.03:22:45.55#ibcon#ireg 11 cls_cnt 2 2006.173.03:22:45.55#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.03:22:45.55#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.03:22:45.55#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.03:22:45.55#ibcon#enter wrdev, iclass 15, count 2 2006.173.03:22:45.55#ibcon#first serial, iclass 15, count 2 2006.173.03:22:45.55#ibcon#enter sib2, iclass 15, count 2 2006.173.03:22:45.55#ibcon#flushed, iclass 15, count 2 2006.173.03:22:45.55#ibcon#about to write, iclass 15, count 2 2006.173.03:22:45.55#ibcon#wrote, iclass 15, count 2 2006.173.03:22:45.55#ibcon#about to read 3, iclass 15, count 2 2006.173.03:22:45.56#ibcon#read 3, iclass 15, count 2 2006.173.03:22:45.56#ibcon#about to read 4, iclass 15, count 2 2006.173.03:22:45.56#ibcon#read 4, iclass 15, count 2 2006.173.03:22:45.56#ibcon#about to read 5, iclass 15, count 2 2006.173.03:22:45.56#ibcon#read 5, iclass 15, count 2 2006.173.03:22:45.56#ibcon#about to read 6, iclass 15, count 2 2006.173.03:22:45.56#ibcon#read 6, iclass 15, count 2 2006.173.03:22:45.56#ibcon#end of sib2, iclass 15, count 2 2006.173.03:22:45.56#ibcon#*mode == 0, iclass 15, count 2 2006.173.03:22:45.56#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.03:22:45.56#ibcon#[25=AT01-07\r\n] 2006.173.03:22:45.56#ibcon#*before write, iclass 15, count 2 2006.173.03:22:45.56#ibcon#enter sib2, iclass 15, count 2 2006.173.03:22:45.56#ibcon#flushed, iclass 15, count 2 2006.173.03:22:45.56#ibcon#about to write, iclass 15, count 2 2006.173.03:22:45.57#ibcon#wrote, iclass 15, count 2 2006.173.03:22:45.57#ibcon#about to read 3, iclass 15, count 2 2006.173.03:22:45.59#ibcon#read 3, iclass 15, count 2 2006.173.03:22:45.59#ibcon#about to read 4, iclass 15, count 2 2006.173.03:22:45.59#ibcon#read 4, iclass 15, count 2 2006.173.03:22:45.59#ibcon#about to read 5, iclass 15, count 2 2006.173.03:22:45.59#ibcon#read 5, iclass 15, count 2 2006.173.03:22:45.59#ibcon#about to read 6, iclass 15, count 2 2006.173.03:22:45.59#ibcon#read 6, iclass 15, count 2 2006.173.03:22:45.59#ibcon#end of sib2, iclass 15, count 2 2006.173.03:22:45.59#ibcon#*after write, iclass 15, count 2 2006.173.03:22:45.59#ibcon#*before return 0, iclass 15, count 2 2006.173.03:22:45.59#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.03:22:45.59#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.03:22:45.59#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.03:22:45.59#ibcon#ireg 7 cls_cnt 0 2006.173.03:22:45.59#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.03:22:45.71#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.03:22:45.71#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.03:22:45.71#ibcon#enter wrdev, iclass 15, count 0 2006.173.03:22:45.71#ibcon#first serial, iclass 15, count 0 2006.173.03:22:45.71#ibcon#enter sib2, iclass 15, count 0 2006.173.03:22:45.71#ibcon#flushed, iclass 15, count 0 2006.173.03:22:45.71#ibcon#about to write, iclass 15, count 0 2006.173.03:22:45.71#ibcon#wrote, iclass 15, count 0 2006.173.03:22:45.71#ibcon#about to read 3, iclass 15, count 0 2006.173.03:22:45.73#ibcon#read 3, iclass 15, count 0 2006.173.03:22:45.73#ibcon#about to read 4, iclass 15, count 0 2006.173.03:22:45.73#ibcon#read 4, iclass 15, count 0 2006.173.03:22:45.73#ibcon#about to read 5, iclass 15, count 0 2006.173.03:22:45.73#ibcon#read 5, iclass 15, count 0 2006.173.03:22:45.73#ibcon#about to read 6, iclass 15, count 0 2006.173.03:22:45.73#ibcon#read 6, iclass 15, count 0 2006.173.03:22:45.73#ibcon#end of sib2, iclass 15, count 0 2006.173.03:22:45.73#ibcon#*mode == 0, iclass 15, count 0 2006.173.03:22:45.73#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.03:22:45.73#ibcon#[25=USB\r\n] 2006.173.03:22:45.73#ibcon#*before write, iclass 15, count 0 2006.173.03:22:45.73#ibcon#enter sib2, iclass 15, count 0 2006.173.03:22:45.73#ibcon#flushed, iclass 15, count 0 2006.173.03:22:45.73#ibcon#about to write, iclass 15, count 0 2006.173.03:22:45.74#ibcon#wrote, iclass 15, count 0 2006.173.03:22:45.74#ibcon#about to read 3, iclass 15, count 0 2006.173.03:22:45.76#ibcon#read 3, iclass 15, count 0 2006.173.03:22:45.76#ibcon#about to read 4, iclass 15, count 0 2006.173.03:22:45.76#ibcon#read 4, iclass 15, count 0 2006.173.03:22:45.76#ibcon#about to read 5, iclass 15, count 0 2006.173.03:22:45.76#ibcon#read 5, iclass 15, count 0 2006.173.03:22:45.76#ibcon#about to read 6, iclass 15, count 0 2006.173.03:22:45.76#ibcon#read 6, iclass 15, count 0 2006.173.03:22:45.76#ibcon#end of sib2, iclass 15, count 0 2006.173.03:22:45.76#ibcon#*after write, iclass 15, count 0 2006.173.03:22:45.76#ibcon#*before return 0, iclass 15, count 0 2006.173.03:22:45.76#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.03:22:45.76#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.03:22:45.76#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.03:22:45.76#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.03:22:45.77$vck44/valo=2,534.99 2006.173.03:22:45.77#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.03:22:45.77#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.03:22:45.77#ibcon#ireg 17 cls_cnt 0 2006.173.03:22:45.77#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.03:22:45.77#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.03:22:45.77#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.03:22:45.77#ibcon#enter wrdev, iclass 17, count 0 2006.173.03:22:45.77#ibcon#first serial, iclass 17, count 0 2006.173.03:22:45.77#ibcon#enter sib2, iclass 17, count 0 2006.173.03:22:45.77#ibcon#flushed, iclass 17, count 0 2006.173.03:22:45.77#ibcon#about to write, iclass 17, count 0 2006.173.03:22:45.77#ibcon#wrote, iclass 17, count 0 2006.173.03:22:45.77#ibcon#about to read 3, iclass 17, count 0 2006.173.03:22:45.78#ibcon#read 3, iclass 17, count 0 2006.173.03:22:45.78#ibcon#about to read 4, iclass 17, count 0 2006.173.03:22:45.78#ibcon#read 4, iclass 17, count 0 2006.173.03:22:45.78#ibcon#about to read 5, iclass 17, count 0 2006.173.03:22:45.78#ibcon#read 5, iclass 17, count 0 2006.173.03:22:45.78#ibcon#about to read 6, iclass 17, count 0 2006.173.03:22:45.78#ibcon#read 6, iclass 17, count 0 2006.173.03:22:45.78#ibcon#end of sib2, iclass 17, count 0 2006.173.03:22:45.78#ibcon#*mode == 0, iclass 17, count 0 2006.173.03:22:45.78#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.03:22:45.78#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.03:22:45.78#ibcon#*before write, iclass 17, count 0 2006.173.03:22:45.78#ibcon#enter sib2, iclass 17, count 0 2006.173.03:22:45.78#ibcon#flushed, iclass 17, count 0 2006.173.03:22:45.78#ibcon#about to write, iclass 17, count 0 2006.173.03:22:45.79#ibcon#wrote, iclass 17, count 0 2006.173.03:22:45.79#ibcon#about to read 3, iclass 17, count 0 2006.173.03:22:45.82#ibcon#read 3, iclass 17, count 0 2006.173.03:22:45.82#ibcon#about to read 4, iclass 17, count 0 2006.173.03:22:45.82#ibcon#read 4, iclass 17, count 0 2006.173.03:22:45.82#ibcon#about to read 5, iclass 17, count 0 2006.173.03:22:45.82#ibcon#read 5, iclass 17, count 0 2006.173.03:22:45.82#ibcon#about to read 6, iclass 17, count 0 2006.173.03:22:45.82#ibcon#read 6, iclass 17, count 0 2006.173.03:22:45.82#ibcon#end of sib2, iclass 17, count 0 2006.173.03:22:45.82#ibcon#*after write, iclass 17, count 0 2006.173.03:22:45.82#ibcon#*before return 0, iclass 17, count 0 2006.173.03:22:45.82#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.03:22:45.82#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.03:22:45.82#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.03:22:45.82#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.03:22:45.83$vck44/va=2,6 2006.173.03:22:45.83#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.03:22:45.83#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.03:22:45.83#ibcon#ireg 11 cls_cnt 2 2006.173.03:22:45.83#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.03:22:45.87#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.03:22:45.87#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.03:22:45.87#ibcon#enter wrdev, iclass 19, count 2 2006.173.03:22:45.87#ibcon#first serial, iclass 19, count 2 2006.173.03:22:45.87#ibcon#enter sib2, iclass 19, count 2 2006.173.03:22:45.87#ibcon#flushed, iclass 19, count 2 2006.173.03:22:45.87#ibcon#about to write, iclass 19, count 2 2006.173.03:22:45.87#ibcon#wrote, iclass 19, count 2 2006.173.03:22:45.87#ibcon#about to read 3, iclass 19, count 2 2006.173.03:22:45.89#ibcon#read 3, iclass 19, count 2 2006.173.03:22:45.89#ibcon#about to read 4, iclass 19, count 2 2006.173.03:22:45.89#ibcon#read 4, iclass 19, count 2 2006.173.03:22:45.89#ibcon#about to read 5, iclass 19, count 2 2006.173.03:22:45.89#ibcon#read 5, iclass 19, count 2 2006.173.03:22:45.89#ibcon#about to read 6, iclass 19, count 2 2006.173.03:22:45.89#ibcon#read 6, iclass 19, count 2 2006.173.03:22:45.89#ibcon#end of sib2, iclass 19, count 2 2006.173.03:22:45.89#ibcon#*mode == 0, iclass 19, count 2 2006.173.03:22:45.89#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.03:22:45.89#ibcon#[25=AT02-06\r\n] 2006.173.03:22:45.89#ibcon#*before write, iclass 19, count 2 2006.173.03:22:45.89#ibcon#enter sib2, iclass 19, count 2 2006.173.03:22:45.89#ibcon#flushed, iclass 19, count 2 2006.173.03:22:45.89#ibcon#about to write, iclass 19, count 2 2006.173.03:22:45.90#ibcon#wrote, iclass 19, count 2 2006.173.03:22:45.90#ibcon#about to read 3, iclass 19, count 2 2006.173.03:22:45.92#ibcon#read 3, iclass 19, count 2 2006.173.03:22:45.92#ibcon#about to read 4, iclass 19, count 2 2006.173.03:22:45.92#ibcon#read 4, iclass 19, count 2 2006.173.03:22:45.92#ibcon#about to read 5, iclass 19, count 2 2006.173.03:22:45.92#ibcon#read 5, iclass 19, count 2 2006.173.03:22:45.92#ibcon#about to read 6, iclass 19, count 2 2006.173.03:22:45.92#ibcon#read 6, iclass 19, count 2 2006.173.03:22:45.92#ibcon#end of sib2, iclass 19, count 2 2006.173.03:22:45.92#ibcon#*after write, iclass 19, count 2 2006.173.03:22:45.92#ibcon#*before return 0, iclass 19, count 2 2006.173.03:22:45.92#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.03:22:45.92#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.03:22:45.92#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.03:22:45.92#ibcon#ireg 7 cls_cnt 0 2006.173.03:22:45.92#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.03:22:46.04#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.03:22:46.04#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.03:22:46.04#ibcon#enter wrdev, iclass 19, count 0 2006.173.03:22:46.04#ibcon#first serial, iclass 19, count 0 2006.173.03:22:46.04#ibcon#enter sib2, iclass 19, count 0 2006.173.03:22:46.04#ibcon#flushed, iclass 19, count 0 2006.173.03:22:46.04#ibcon#about to write, iclass 19, count 0 2006.173.03:22:46.04#ibcon#wrote, iclass 19, count 0 2006.173.03:22:46.04#ibcon#about to read 3, iclass 19, count 0 2006.173.03:22:46.06#ibcon#read 3, iclass 19, count 0 2006.173.03:22:46.06#ibcon#about to read 4, iclass 19, count 0 2006.173.03:22:46.06#ibcon#read 4, iclass 19, count 0 2006.173.03:22:46.06#ibcon#about to read 5, iclass 19, count 0 2006.173.03:22:46.06#ibcon#read 5, iclass 19, count 0 2006.173.03:22:46.06#ibcon#about to read 6, iclass 19, count 0 2006.173.03:22:46.06#ibcon#read 6, iclass 19, count 0 2006.173.03:22:46.06#ibcon#end of sib2, iclass 19, count 0 2006.173.03:22:46.06#ibcon#*mode == 0, iclass 19, count 0 2006.173.03:22:46.06#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.03:22:46.06#ibcon#[25=USB\r\n] 2006.173.03:22:46.06#ibcon#*before write, iclass 19, count 0 2006.173.03:22:46.06#ibcon#enter sib2, iclass 19, count 0 2006.173.03:22:46.06#ibcon#flushed, iclass 19, count 0 2006.173.03:22:46.06#ibcon#about to write, iclass 19, count 0 2006.173.03:22:46.07#ibcon#wrote, iclass 19, count 0 2006.173.03:22:46.07#ibcon#about to read 3, iclass 19, count 0 2006.173.03:22:46.09#ibcon#read 3, iclass 19, count 0 2006.173.03:22:46.09#ibcon#about to read 4, iclass 19, count 0 2006.173.03:22:46.09#ibcon#read 4, iclass 19, count 0 2006.173.03:22:46.09#ibcon#about to read 5, iclass 19, count 0 2006.173.03:22:46.09#ibcon#read 5, iclass 19, count 0 2006.173.03:22:46.09#ibcon#about to read 6, iclass 19, count 0 2006.173.03:22:46.09#ibcon#read 6, iclass 19, count 0 2006.173.03:22:46.09#ibcon#end of sib2, iclass 19, count 0 2006.173.03:22:46.09#ibcon#*after write, iclass 19, count 0 2006.173.03:22:46.09#ibcon#*before return 0, iclass 19, count 0 2006.173.03:22:46.09#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.03:22:46.09#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.03:22:46.09#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.03:22:46.09#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.03:22:46.10$vck44/valo=3,564.99 2006.173.03:22:46.10#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.03:22:46.10#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.03:22:46.10#ibcon#ireg 17 cls_cnt 0 2006.173.03:22:46.10#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.03:22:46.10#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.03:22:46.10#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.03:22:46.10#ibcon#enter wrdev, iclass 21, count 0 2006.173.03:22:46.10#ibcon#first serial, iclass 21, count 0 2006.173.03:22:46.10#ibcon#enter sib2, iclass 21, count 0 2006.173.03:22:46.10#ibcon#flushed, iclass 21, count 0 2006.173.03:22:46.10#ibcon#about to write, iclass 21, count 0 2006.173.03:22:46.10#ibcon#wrote, iclass 21, count 0 2006.173.03:22:46.10#ibcon#about to read 3, iclass 21, count 0 2006.173.03:22:46.11#ibcon#read 3, iclass 21, count 0 2006.173.03:22:46.11#ibcon#about to read 4, iclass 21, count 0 2006.173.03:22:46.11#ibcon#read 4, iclass 21, count 0 2006.173.03:22:46.11#ibcon#about to read 5, iclass 21, count 0 2006.173.03:22:46.11#ibcon#read 5, iclass 21, count 0 2006.173.03:22:46.11#ibcon#about to read 6, iclass 21, count 0 2006.173.03:22:46.11#ibcon#read 6, iclass 21, count 0 2006.173.03:22:46.11#ibcon#end of sib2, iclass 21, count 0 2006.173.03:22:46.11#ibcon#*mode == 0, iclass 21, count 0 2006.173.03:22:46.11#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.03:22:46.11#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.03:22:46.11#ibcon#*before write, iclass 21, count 0 2006.173.03:22:46.11#ibcon#enter sib2, iclass 21, count 0 2006.173.03:22:46.11#ibcon#flushed, iclass 21, count 0 2006.173.03:22:46.11#ibcon#about to write, iclass 21, count 0 2006.173.03:22:46.12#ibcon#wrote, iclass 21, count 0 2006.173.03:22:46.12#ibcon#about to read 3, iclass 21, count 0 2006.173.03:22:46.15#ibcon#read 3, iclass 21, count 0 2006.173.03:22:46.15#ibcon#about to read 4, iclass 21, count 0 2006.173.03:22:46.15#ibcon#read 4, iclass 21, count 0 2006.173.03:22:46.15#ibcon#about to read 5, iclass 21, count 0 2006.173.03:22:46.15#ibcon#read 5, iclass 21, count 0 2006.173.03:22:46.15#ibcon#about to read 6, iclass 21, count 0 2006.173.03:22:46.15#ibcon#read 6, iclass 21, count 0 2006.173.03:22:46.15#ibcon#end of sib2, iclass 21, count 0 2006.173.03:22:46.15#ibcon#*after write, iclass 21, count 0 2006.173.03:22:46.15#ibcon#*before return 0, iclass 21, count 0 2006.173.03:22:46.15#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.03:22:46.15#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.03:22:46.15#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.03:22:46.15#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.03:22:46.16$vck44/va=3,5 2006.173.03:22:46.16#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.03:22:46.16#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.03:22:46.16#ibcon#ireg 11 cls_cnt 2 2006.173.03:22:46.16#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.03:22:46.20#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.03:22:46.20#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.03:22:46.20#ibcon#enter wrdev, iclass 23, count 2 2006.173.03:22:46.20#ibcon#first serial, iclass 23, count 2 2006.173.03:22:46.20#ibcon#enter sib2, iclass 23, count 2 2006.173.03:22:46.20#ibcon#flushed, iclass 23, count 2 2006.173.03:22:46.20#ibcon#about to write, iclass 23, count 2 2006.173.03:22:46.20#ibcon#wrote, iclass 23, count 2 2006.173.03:22:46.20#ibcon#about to read 3, iclass 23, count 2 2006.173.03:22:46.22#ibcon#read 3, iclass 23, count 2 2006.173.03:22:46.22#ibcon#about to read 4, iclass 23, count 2 2006.173.03:22:46.22#ibcon#read 4, iclass 23, count 2 2006.173.03:22:46.22#ibcon#about to read 5, iclass 23, count 2 2006.173.03:22:46.22#ibcon#read 5, iclass 23, count 2 2006.173.03:22:46.22#ibcon#about to read 6, iclass 23, count 2 2006.173.03:22:46.22#ibcon#read 6, iclass 23, count 2 2006.173.03:22:46.22#ibcon#end of sib2, iclass 23, count 2 2006.173.03:22:46.22#ibcon#*mode == 0, iclass 23, count 2 2006.173.03:22:46.22#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.03:22:46.22#ibcon#[25=AT03-05\r\n] 2006.173.03:22:46.22#ibcon#*before write, iclass 23, count 2 2006.173.03:22:46.22#ibcon#enter sib2, iclass 23, count 2 2006.173.03:22:46.22#ibcon#flushed, iclass 23, count 2 2006.173.03:22:46.22#ibcon#about to write, iclass 23, count 2 2006.173.03:22:46.23#ibcon#wrote, iclass 23, count 2 2006.173.03:22:46.23#ibcon#about to read 3, iclass 23, count 2 2006.173.03:22:46.25#ibcon#read 3, iclass 23, count 2 2006.173.03:22:46.25#ibcon#about to read 4, iclass 23, count 2 2006.173.03:22:46.25#ibcon#read 4, iclass 23, count 2 2006.173.03:22:46.25#ibcon#about to read 5, iclass 23, count 2 2006.173.03:22:46.25#ibcon#read 5, iclass 23, count 2 2006.173.03:22:46.25#ibcon#about to read 6, iclass 23, count 2 2006.173.03:22:46.25#ibcon#read 6, iclass 23, count 2 2006.173.03:22:46.25#ibcon#end of sib2, iclass 23, count 2 2006.173.03:22:46.25#ibcon#*after write, iclass 23, count 2 2006.173.03:22:46.25#ibcon#*before return 0, iclass 23, count 2 2006.173.03:22:46.25#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.03:22:46.25#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.03:22:46.25#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.03:22:46.25#ibcon#ireg 7 cls_cnt 0 2006.173.03:22:46.25#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.03:22:46.37#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.03:22:46.37#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.03:22:46.37#ibcon#enter wrdev, iclass 23, count 0 2006.173.03:22:46.37#ibcon#first serial, iclass 23, count 0 2006.173.03:22:46.37#ibcon#enter sib2, iclass 23, count 0 2006.173.03:22:46.37#ibcon#flushed, iclass 23, count 0 2006.173.03:22:46.37#ibcon#about to write, iclass 23, count 0 2006.173.03:22:46.37#ibcon#wrote, iclass 23, count 0 2006.173.03:22:46.37#ibcon#about to read 3, iclass 23, count 0 2006.173.03:22:46.39#ibcon#read 3, iclass 23, count 0 2006.173.03:22:46.39#ibcon#about to read 4, iclass 23, count 0 2006.173.03:22:46.39#ibcon#read 4, iclass 23, count 0 2006.173.03:22:46.39#ibcon#about to read 5, iclass 23, count 0 2006.173.03:22:46.39#ibcon#read 5, iclass 23, count 0 2006.173.03:22:46.39#ibcon#about to read 6, iclass 23, count 0 2006.173.03:22:46.39#ibcon#read 6, iclass 23, count 0 2006.173.03:22:46.39#ibcon#end of sib2, iclass 23, count 0 2006.173.03:22:46.39#ibcon#*mode == 0, iclass 23, count 0 2006.173.03:22:46.39#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.03:22:46.39#ibcon#[25=USB\r\n] 2006.173.03:22:46.39#ibcon#*before write, iclass 23, count 0 2006.173.03:22:46.39#ibcon#enter sib2, iclass 23, count 0 2006.173.03:22:46.39#ibcon#flushed, iclass 23, count 0 2006.173.03:22:46.39#ibcon#about to write, iclass 23, count 0 2006.173.03:22:46.40#ibcon#wrote, iclass 23, count 0 2006.173.03:22:46.40#ibcon#about to read 3, iclass 23, count 0 2006.173.03:22:46.42#ibcon#read 3, iclass 23, count 0 2006.173.03:22:46.42#ibcon#about to read 4, iclass 23, count 0 2006.173.03:22:46.42#ibcon#read 4, iclass 23, count 0 2006.173.03:22:46.42#ibcon#about to read 5, iclass 23, count 0 2006.173.03:22:46.42#ibcon#read 5, iclass 23, count 0 2006.173.03:22:46.42#ibcon#about to read 6, iclass 23, count 0 2006.173.03:22:46.42#ibcon#read 6, iclass 23, count 0 2006.173.03:22:46.42#ibcon#end of sib2, iclass 23, count 0 2006.173.03:22:46.42#ibcon#*after write, iclass 23, count 0 2006.173.03:22:46.42#ibcon#*before return 0, iclass 23, count 0 2006.173.03:22:46.42#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.03:22:46.42#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.03:22:46.42#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.03:22:46.42#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.03:22:46.43$vck44/valo=4,624.99 2006.173.03:22:46.43#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.03:22:46.43#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.03:22:46.43#ibcon#ireg 17 cls_cnt 0 2006.173.03:22:46.43#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.03:22:46.43#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.03:22:46.43#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.03:22:46.43#ibcon#enter wrdev, iclass 25, count 0 2006.173.03:22:46.43#ibcon#first serial, iclass 25, count 0 2006.173.03:22:46.43#ibcon#enter sib2, iclass 25, count 0 2006.173.03:22:46.43#ibcon#flushed, iclass 25, count 0 2006.173.03:22:46.43#ibcon#about to write, iclass 25, count 0 2006.173.03:22:46.43#ibcon#wrote, iclass 25, count 0 2006.173.03:22:46.43#ibcon#about to read 3, iclass 25, count 0 2006.173.03:22:46.44#ibcon#read 3, iclass 25, count 0 2006.173.03:22:46.44#ibcon#about to read 4, iclass 25, count 0 2006.173.03:22:46.44#ibcon#read 4, iclass 25, count 0 2006.173.03:22:46.44#ibcon#about to read 5, iclass 25, count 0 2006.173.03:22:46.44#ibcon#read 5, iclass 25, count 0 2006.173.03:22:46.44#ibcon#about to read 6, iclass 25, count 0 2006.173.03:22:46.44#ibcon#read 6, iclass 25, count 0 2006.173.03:22:46.44#ibcon#end of sib2, iclass 25, count 0 2006.173.03:22:46.44#ibcon#*mode == 0, iclass 25, count 0 2006.173.03:22:46.44#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.03:22:46.44#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.03:22:46.44#ibcon#*before write, iclass 25, count 0 2006.173.03:22:46.44#ibcon#enter sib2, iclass 25, count 0 2006.173.03:22:46.44#ibcon#flushed, iclass 25, count 0 2006.173.03:22:46.44#ibcon#about to write, iclass 25, count 0 2006.173.03:22:46.45#ibcon#wrote, iclass 25, count 0 2006.173.03:22:46.45#ibcon#about to read 3, iclass 25, count 0 2006.173.03:22:46.48#ibcon#read 3, iclass 25, count 0 2006.173.03:22:46.48#ibcon#about to read 4, iclass 25, count 0 2006.173.03:22:46.48#ibcon#read 4, iclass 25, count 0 2006.173.03:22:46.48#ibcon#about to read 5, iclass 25, count 0 2006.173.03:22:46.48#ibcon#read 5, iclass 25, count 0 2006.173.03:22:46.48#ibcon#about to read 6, iclass 25, count 0 2006.173.03:22:46.48#ibcon#read 6, iclass 25, count 0 2006.173.03:22:46.48#ibcon#end of sib2, iclass 25, count 0 2006.173.03:22:46.48#ibcon#*after write, iclass 25, count 0 2006.173.03:22:46.48#ibcon#*before return 0, iclass 25, count 0 2006.173.03:22:46.48#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.03:22:46.48#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.03:22:46.48#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.03:22:46.48#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.03:22:46.49$vck44/va=4,6 2006.173.03:22:46.49#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.03:22:46.49#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.03:22:46.49#ibcon#ireg 11 cls_cnt 2 2006.173.03:22:46.49#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.03:22:46.53#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.03:22:46.53#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.03:22:46.53#ibcon#enter wrdev, iclass 27, count 2 2006.173.03:22:46.53#ibcon#first serial, iclass 27, count 2 2006.173.03:22:46.53#ibcon#enter sib2, iclass 27, count 2 2006.173.03:22:46.53#ibcon#flushed, iclass 27, count 2 2006.173.03:22:46.53#ibcon#about to write, iclass 27, count 2 2006.173.03:22:46.53#ibcon#wrote, iclass 27, count 2 2006.173.03:22:46.53#ibcon#about to read 3, iclass 27, count 2 2006.173.03:22:46.55#ibcon#read 3, iclass 27, count 2 2006.173.03:22:46.55#ibcon#about to read 4, iclass 27, count 2 2006.173.03:22:46.55#ibcon#read 4, iclass 27, count 2 2006.173.03:22:46.55#ibcon#about to read 5, iclass 27, count 2 2006.173.03:22:46.55#ibcon#read 5, iclass 27, count 2 2006.173.03:22:46.55#ibcon#about to read 6, iclass 27, count 2 2006.173.03:22:46.55#ibcon#read 6, iclass 27, count 2 2006.173.03:22:46.55#ibcon#end of sib2, iclass 27, count 2 2006.173.03:22:46.55#ibcon#*mode == 0, iclass 27, count 2 2006.173.03:22:46.55#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.03:22:46.55#ibcon#[25=AT04-06\r\n] 2006.173.03:22:46.55#ibcon#*before write, iclass 27, count 2 2006.173.03:22:46.55#ibcon#enter sib2, iclass 27, count 2 2006.173.03:22:46.55#ibcon#flushed, iclass 27, count 2 2006.173.03:22:46.55#ibcon#about to write, iclass 27, count 2 2006.173.03:22:46.56#ibcon#wrote, iclass 27, count 2 2006.173.03:22:46.56#ibcon#about to read 3, iclass 27, count 2 2006.173.03:22:46.58#ibcon#read 3, iclass 27, count 2 2006.173.03:22:46.58#ibcon#about to read 4, iclass 27, count 2 2006.173.03:22:46.58#ibcon#read 4, iclass 27, count 2 2006.173.03:22:46.58#ibcon#about to read 5, iclass 27, count 2 2006.173.03:22:46.58#ibcon#read 5, iclass 27, count 2 2006.173.03:22:46.58#ibcon#about to read 6, iclass 27, count 2 2006.173.03:22:46.58#ibcon#read 6, iclass 27, count 2 2006.173.03:22:46.58#ibcon#end of sib2, iclass 27, count 2 2006.173.03:22:46.58#ibcon#*after write, iclass 27, count 2 2006.173.03:22:46.58#ibcon#*before return 0, iclass 27, count 2 2006.173.03:22:46.58#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.03:22:46.58#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.03:22:46.58#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.03:22:46.58#ibcon#ireg 7 cls_cnt 0 2006.173.03:22:46.58#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.03:22:46.70#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.03:22:46.70#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.03:22:46.70#ibcon#enter wrdev, iclass 27, count 0 2006.173.03:22:46.70#ibcon#first serial, iclass 27, count 0 2006.173.03:22:46.70#ibcon#enter sib2, iclass 27, count 0 2006.173.03:22:46.70#ibcon#flushed, iclass 27, count 0 2006.173.03:22:46.70#ibcon#about to write, iclass 27, count 0 2006.173.03:22:46.70#ibcon#wrote, iclass 27, count 0 2006.173.03:22:46.70#ibcon#about to read 3, iclass 27, count 0 2006.173.03:22:46.72#ibcon#read 3, iclass 27, count 0 2006.173.03:22:46.72#ibcon#about to read 4, iclass 27, count 0 2006.173.03:22:46.72#ibcon#read 4, iclass 27, count 0 2006.173.03:22:46.72#ibcon#about to read 5, iclass 27, count 0 2006.173.03:22:46.72#ibcon#read 5, iclass 27, count 0 2006.173.03:22:46.72#ibcon#about to read 6, iclass 27, count 0 2006.173.03:22:46.72#ibcon#read 6, iclass 27, count 0 2006.173.03:22:46.72#ibcon#end of sib2, iclass 27, count 0 2006.173.03:22:46.72#ibcon#*mode == 0, iclass 27, count 0 2006.173.03:22:46.72#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.03:22:46.72#ibcon#[25=USB\r\n] 2006.173.03:22:46.72#ibcon#*before write, iclass 27, count 0 2006.173.03:22:46.72#ibcon#enter sib2, iclass 27, count 0 2006.173.03:22:46.72#ibcon#flushed, iclass 27, count 0 2006.173.03:22:46.72#ibcon#about to write, iclass 27, count 0 2006.173.03:22:46.73#ibcon#wrote, iclass 27, count 0 2006.173.03:22:46.73#ibcon#about to read 3, iclass 27, count 0 2006.173.03:22:46.75#ibcon#read 3, iclass 27, count 0 2006.173.03:22:46.75#ibcon#about to read 4, iclass 27, count 0 2006.173.03:22:46.75#ibcon#read 4, iclass 27, count 0 2006.173.03:22:46.75#ibcon#about to read 5, iclass 27, count 0 2006.173.03:22:46.75#ibcon#read 5, iclass 27, count 0 2006.173.03:22:46.75#ibcon#about to read 6, iclass 27, count 0 2006.173.03:22:46.75#ibcon#read 6, iclass 27, count 0 2006.173.03:22:46.75#ibcon#end of sib2, iclass 27, count 0 2006.173.03:22:46.75#ibcon#*after write, iclass 27, count 0 2006.173.03:22:46.75#ibcon#*before return 0, iclass 27, count 0 2006.173.03:22:46.75#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.03:22:46.75#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.03:22:46.75#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.03:22:46.75#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.03:22:46.76$vck44/valo=5,734.99 2006.173.03:22:46.76#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.03:22:46.76#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.03:22:46.76#ibcon#ireg 17 cls_cnt 0 2006.173.03:22:46.76#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.03:22:46.76#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.03:22:46.76#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.03:22:46.76#ibcon#enter wrdev, iclass 29, count 0 2006.173.03:22:46.76#ibcon#first serial, iclass 29, count 0 2006.173.03:22:46.76#ibcon#enter sib2, iclass 29, count 0 2006.173.03:22:46.76#ibcon#flushed, iclass 29, count 0 2006.173.03:22:46.76#ibcon#about to write, iclass 29, count 0 2006.173.03:22:46.76#ibcon#wrote, iclass 29, count 0 2006.173.03:22:46.76#ibcon#about to read 3, iclass 29, count 0 2006.173.03:22:46.77#ibcon#read 3, iclass 29, count 0 2006.173.03:22:46.77#ibcon#about to read 4, iclass 29, count 0 2006.173.03:22:46.77#ibcon#read 4, iclass 29, count 0 2006.173.03:22:46.77#ibcon#about to read 5, iclass 29, count 0 2006.173.03:22:46.77#ibcon#read 5, iclass 29, count 0 2006.173.03:22:46.77#ibcon#about to read 6, iclass 29, count 0 2006.173.03:22:46.77#ibcon#read 6, iclass 29, count 0 2006.173.03:22:46.77#ibcon#end of sib2, iclass 29, count 0 2006.173.03:22:46.77#ibcon#*mode == 0, iclass 29, count 0 2006.173.03:22:46.77#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.03:22:46.77#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.03:22:46.77#ibcon#*before write, iclass 29, count 0 2006.173.03:22:46.77#ibcon#enter sib2, iclass 29, count 0 2006.173.03:22:46.77#ibcon#flushed, iclass 29, count 0 2006.173.03:22:46.77#ibcon#about to write, iclass 29, count 0 2006.173.03:22:46.78#ibcon#wrote, iclass 29, count 0 2006.173.03:22:46.78#ibcon#about to read 3, iclass 29, count 0 2006.173.03:22:46.81#ibcon#read 3, iclass 29, count 0 2006.173.03:22:46.81#ibcon#about to read 4, iclass 29, count 0 2006.173.03:22:46.81#ibcon#read 4, iclass 29, count 0 2006.173.03:22:46.81#ibcon#about to read 5, iclass 29, count 0 2006.173.03:22:46.81#ibcon#read 5, iclass 29, count 0 2006.173.03:22:46.81#ibcon#about to read 6, iclass 29, count 0 2006.173.03:22:46.81#ibcon#read 6, iclass 29, count 0 2006.173.03:22:46.81#ibcon#end of sib2, iclass 29, count 0 2006.173.03:22:46.81#ibcon#*after write, iclass 29, count 0 2006.173.03:22:46.81#ibcon#*before return 0, iclass 29, count 0 2006.173.03:22:46.81#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.03:22:46.81#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.03:22:46.81#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.03:22:46.81#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.03:22:46.82$vck44/va=5,4 2006.173.03:22:46.82#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.03:22:46.82#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.03:22:46.82#ibcon#ireg 11 cls_cnt 2 2006.173.03:22:46.82#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.03:22:46.86#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.03:22:46.86#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.03:22:46.86#ibcon#enter wrdev, iclass 31, count 2 2006.173.03:22:46.86#ibcon#first serial, iclass 31, count 2 2006.173.03:22:46.86#ibcon#enter sib2, iclass 31, count 2 2006.173.03:22:46.86#ibcon#flushed, iclass 31, count 2 2006.173.03:22:46.86#ibcon#about to write, iclass 31, count 2 2006.173.03:22:46.86#ibcon#wrote, iclass 31, count 2 2006.173.03:22:46.86#ibcon#about to read 3, iclass 31, count 2 2006.173.03:22:46.88#ibcon#read 3, iclass 31, count 2 2006.173.03:22:46.88#ibcon#about to read 4, iclass 31, count 2 2006.173.03:22:46.88#ibcon#read 4, iclass 31, count 2 2006.173.03:22:46.88#ibcon#about to read 5, iclass 31, count 2 2006.173.03:22:46.88#ibcon#read 5, iclass 31, count 2 2006.173.03:22:46.88#ibcon#about to read 6, iclass 31, count 2 2006.173.03:22:46.88#ibcon#read 6, iclass 31, count 2 2006.173.03:22:46.88#ibcon#end of sib2, iclass 31, count 2 2006.173.03:22:46.88#ibcon#*mode == 0, iclass 31, count 2 2006.173.03:22:46.88#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.03:22:46.88#ibcon#[25=AT05-04\r\n] 2006.173.03:22:46.88#ibcon#*before write, iclass 31, count 2 2006.173.03:22:46.88#ibcon#enter sib2, iclass 31, count 2 2006.173.03:22:46.88#ibcon#flushed, iclass 31, count 2 2006.173.03:22:46.88#ibcon#about to write, iclass 31, count 2 2006.173.03:22:46.88#ibcon#wrote, iclass 31, count 2 2006.173.03:22:46.89#ibcon#about to read 3, iclass 31, count 2 2006.173.03:22:46.91#ibcon#read 3, iclass 31, count 2 2006.173.03:22:46.91#ibcon#about to read 4, iclass 31, count 2 2006.173.03:22:46.91#ibcon#read 4, iclass 31, count 2 2006.173.03:22:46.91#ibcon#about to read 5, iclass 31, count 2 2006.173.03:22:46.91#ibcon#read 5, iclass 31, count 2 2006.173.03:22:46.91#ibcon#about to read 6, iclass 31, count 2 2006.173.03:22:46.91#ibcon#read 6, iclass 31, count 2 2006.173.03:22:46.91#ibcon#end of sib2, iclass 31, count 2 2006.173.03:22:46.91#ibcon#*after write, iclass 31, count 2 2006.173.03:22:46.91#ibcon#*before return 0, iclass 31, count 2 2006.173.03:22:46.91#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.03:22:46.91#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.03:22:46.91#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.03:22:46.91#ibcon#ireg 7 cls_cnt 0 2006.173.03:22:46.91#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.03:22:47.03#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.03:22:47.03#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.03:22:47.03#ibcon#enter wrdev, iclass 31, count 0 2006.173.03:22:47.03#ibcon#first serial, iclass 31, count 0 2006.173.03:22:47.03#ibcon#enter sib2, iclass 31, count 0 2006.173.03:22:47.03#ibcon#flushed, iclass 31, count 0 2006.173.03:22:47.03#ibcon#about to write, iclass 31, count 0 2006.173.03:22:47.03#ibcon#wrote, iclass 31, count 0 2006.173.03:22:47.03#ibcon#about to read 3, iclass 31, count 0 2006.173.03:22:47.05#ibcon#read 3, iclass 31, count 0 2006.173.03:22:47.05#ibcon#about to read 4, iclass 31, count 0 2006.173.03:22:47.05#ibcon#read 4, iclass 31, count 0 2006.173.03:22:47.05#ibcon#about to read 5, iclass 31, count 0 2006.173.03:22:47.05#ibcon#read 5, iclass 31, count 0 2006.173.03:22:47.05#ibcon#about to read 6, iclass 31, count 0 2006.173.03:22:47.05#ibcon#read 6, iclass 31, count 0 2006.173.03:22:47.05#ibcon#end of sib2, iclass 31, count 0 2006.173.03:22:47.05#ibcon#*mode == 0, iclass 31, count 0 2006.173.03:22:47.05#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.03:22:47.05#ibcon#[25=USB\r\n] 2006.173.03:22:47.05#ibcon#*before write, iclass 31, count 0 2006.173.03:22:47.05#ibcon#enter sib2, iclass 31, count 0 2006.173.03:22:47.05#ibcon#flushed, iclass 31, count 0 2006.173.03:22:47.05#ibcon#about to write, iclass 31, count 0 2006.173.03:22:47.06#ibcon#wrote, iclass 31, count 0 2006.173.03:22:47.06#ibcon#about to read 3, iclass 31, count 0 2006.173.03:22:47.08#ibcon#read 3, iclass 31, count 0 2006.173.03:22:47.08#ibcon#about to read 4, iclass 31, count 0 2006.173.03:22:47.08#ibcon#read 4, iclass 31, count 0 2006.173.03:22:47.08#ibcon#about to read 5, iclass 31, count 0 2006.173.03:22:47.08#ibcon#read 5, iclass 31, count 0 2006.173.03:22:47.08#ibcon#about to read 6, iclass 31, count 0 2006.173.03:22:47.08#ibcon#read 6, iclass 31, count 0 2006.173.03:22:47.08#ibcon#end of sib2, iclass 31, count 0 2006.173.03:22:47.08#ibcon#*after write, iclass 31, count 0 2006.173.03:22:47.08#ibcon#*before return 0, iclass 31, count 0 2006.173.03:22:47.08#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.03:22:47.08#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.03:22:47.08#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.03:22:47.08#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.03:22:47.09$vck44/valo=6,814.99 2006.173.03:22:47.09#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.03:22:47.09#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.03:22:47.09#ibcon#ireg 17 cls_cnt 0 2006.173.03:22:47.09#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.03:22:47.09#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.03:22:47.09#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.03:22:47.09#ibcon#enter wrdev, iclass 33, count 0 2006.173.03:22:47.09#ibcon#first serial, iclass 33, count 0 2006.173.03:22:47.09#ibcon#enter sib2, iclass 33, count 0 2006.173.03:22:47.09#ibcon#flushed, iclass 33, count 0 2006.173.03:22:47.09#ibcon#about to write, iclass 33, count 0 2006.173.03:22:47.09#ibcon#wrote, iclass 33, count 0 2006.173.03:22:47.09#ibcon#about to read 3, iclass 33, count 0 2006.173.03:22:47.10#ibcon#read 3, iclass 33, count 0 2006.173.03:22:47.10#ibcon#about to read 4, iclass 33, count 0 2006.173.03:22:47.10#ibcon#read 4, iclass 33, count 0 2006.173.03:22:47.10#ibcon#about to read 5, iclass 33, count 0 2006.173.03:22:47.10#ibcon#read 5, iclass 33, count 0 2006.173.03:22:47.10#ibcon#about to read 6, iclass 33, count 0 2006.173.03:22:47.10#ibcon#read 6, iclass 33, count 0 2006.173.03:22:47.10#ibcon#end of sib2, iclass 33, count 0 2006.173.03:22:47.10#ibcon#*mode == 0, iclass 33, count 0 2006.173.03:22:47.10#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.03:22:47.10#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.03:22:47.10#ibcon#*before write, iclass 33, count 0 2006.173.03:22:47.10#ibcon#enter sib2, iclass 33, count 0 2006.173.03:22:47.10#ibcon#flushed, iclass 33, count 0 2006.173.03:22:47.10#ibcon#about to write, iclass 33, count 0 2006.173.03:22:47.11#ibcon#wrote, iclass 33, count 0 2006.173.03:22:47.11#ibcon#about to read 3, iclass 33, count 0 2006.173.03:22:47.15#ibcon#read 3, iclass 33, count 0 2006.173.03:22:47.15#ibcon#about to read 4, iclass 33, count 0 2006.173.03:22:47.15#ibcon#read 4, iclass 33, count 0 2006.173.03:22:47.15#ibcon#about to read 5, iclass 33, count 0 2006.173.03:22:47.15#ibcon#read 5, iclass 33, count 0 2006.173.03:22:47.15#ibcon#about to read 6, iclass 33, count 0 2006.173.03:22:47.15#ibcon#read 6, iclass 33, count 0 2006.173.03:22:47.15#ibcon#end of sib2, iclass 33, count 0 2006.173.03:22:47.15#ibcon#*after write, iclass 33, count 0 2006.173.03:22:47.15#ibcon#*before return 0, iclass 33, count 0 2006.173.03:22:47.15#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.03:22:47.15#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.03:22:47.15#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.03:22:47.15#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.03:22:47.15$vck44/va=6,3 2006.173.03:22:47.15#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.03:22:47.15#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.03:22:47.15#ibcon#ireg 11 cls_cnt 2 2006.173.03:22:47.15#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.03:22:47.19#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.03:22:47.19#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.03:22:47.19#ibcon#enter wrdev, iclass 35, count 2 2006.173.03:22:47.19#ibcon#first serial, iclass 35, count 2 2006.173.03:22:47.19#ibcon#enter sib2, iclass 35, count 2 2006.173.03:22:47.19#ibcon#flushed, iclass 35, count 2 2006.173.03:22:47.19#ibcon#about to write, iclass 35, count 2 2006.173.03:22:47.19#ibcon#wrote, iclass 35, count 2 2006.173.03:22:47.19#ibcon#about to read 3, iclass 35, count 2 2006.173.03:22:47.21#ibcon#read 3, iclass 35, count 2 2006.173.03:22:47.21#ibcon#about to read 4, iclass 35, count 2 2006.173.03:22:47.21#ibcon#read 4, iclass 35, count 2 2006.173.03:22:47.21#ibcon#about to read 5, iclass 35, count 2 2006.173.03:22:47.21#ibcon#read 5, iclass 35, count 2 2006.173.03:22:47.21#ibcon#about to read 6, iclass 35, count 2 2006.173.03:22:47.21#ibcon#read 6, iclass 35, count 2 2006.173.03:22:47.21#ibcon#end of sib2, iclass 35, count 2 2006.173.03:22:47.21#ibcon#*mode == 0, iclass 35, count 2 2006.173.03:22:47.21#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.03:22:47.21#ibcon#[25=AT06-03\r\n] 2006.173.03:22:47.21#ibcon#*before write, iclass 35, count 2 2006.173.03:22:47.21#ibcon#enter sib2, iclass 35, count 2 2006.173.03:22:47.21#ibcon#flushed, iclass 35, count 2 2006.173.03:22:47.21#ibcon#about to write, iclass 35, count 2 2006.173.03:22:47.21#ibcon#wrote, iclass 35, count 2 2006.173.03:22:47.22#ibcon#about to read 3, iclass 35, count 2 2006.173.03:22:47.24#ibcon#read 3, iclass 35, count 2 2006.173.03:22:47.24#ibcon#about to read 4, iclass 35, count 2 2006.173.03:22:47.24#ibcon#read 4, iclass 35, count 2 2006.173.03:22:47.24#ibcon#about to read 5, iclass 35, count 2 2006.173.03:22:47.24#ibcon#read 5, iclass 35, count 2 2006.173.03:22:47.24#ibcon#about to read 6, iclass 35, count 2 2006.173.03:22:47.24#ibcon#read 6, iclass 35, count 2 2006.173.03:22:47.24#ibcon#end of sib2, iclass 35, count 2 2006.173.03:22:47.24#ibcon#*after write, iclass 35, count 2 2006.173.03:22:47.24#ibcon#*before return 0, iclass 35, count 2 2006.173.03:22:47.24#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.03:22:47.24#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.03:22:47.24#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.03:22:47.24#ibcon#ireg 7 cls_cnt 0 2006.173.03:22:47.24#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.03:22:47.36#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.03:22:47.36#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.03:22:47.36#ibcon#enter wrdev, iclass 35, count 0 2006.173.03:22:47.36#ibcon#first serial, iclass 35, count 0 2006.173.03:22:47.36#ibcon#enter sib2, iclass 35, count 0 2006.173.03:22:47.36#ibcon#flushed, iclass 35, count 0 2006.173.03:22:47.36#ibcon#about to write, iclass 35, count 0 2006.173.03:22:47.36#ibcon#wrote, iclass 35, count 0 2006.173.03:22:47.36#ibcon#about to read 3, iclass 35, count 0 2006.173.03:22:47.38#ibcon#read 3, iclass 35, count 0 2006.173.03:22:47.38#ibcon#about to read 4, iclass 35, count 0 2006.173.03:22:47.38#ibcon#read 4, iclass 35, count 0 2006.173.03:22:47.38#ibcon#about to read 5, iclass 35, count 0 2006.173.03:22:47.38#ibcon#read 5, iclass 35, count 0 2006.173.03:22:47.38#ibcon#about to read 6, iclass 35, count 0 2006.173.03:22:47.38#ibcon#read 6, iclass 35, count 0 2006.173.03:22:47.38#ibcon#end of sib2, iclass 35, count 0 2006.173.03:22:47.38#ibcon#*mode == 0, iclass 35, count 0 2006.173.03:22:47.38#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.03:22:47.38#ibcon#[25=USB\r\n] 2006.173.03:22:47.38#ibcon#*before write, iclass 35, count 0 2006.173.03:22:47.38#ibcon#enter sib2, iclass 35, count 0 2006.173.03:22:47.38#ibcon#flushed, iclass 35, count 0 2006.173.03:22:47.38#ibcon#about to write, iclass 35, count 0 2006.173.03:22:47.38#ibcon#wrote, iclass 35, count 0 2006.173.03:22:47.39#ibcon#about to read 3, iclass 35, count 0 2006.173.03:22:47.41#ibcon#read 3, iclass 35, count 0 2006.173.03:22:47.41#ibcon#about to read 4, iclass 35, count 0 2006.173.03:22:47.41#ibcon#read 4, iclass 35, count 0 2006.173.03:22:47.41#ibcon#about to read 5, iclass 35, count 0 2006.173.03:22:47.41#ibcon#read 5, iclass 35, count 0 2006.173.03:22:47.41#ibcon#about to read 6, iclass 35, count 0 2006.173.03:22:47.41#ibcon#read 6, iclass 35, count 0 2006.173.03:22:47.41#ibcon#end of sib2, iclass 35, count 0 2006.173.03:22:47.41#ibcon#*after write, iclass 35, count 0 2006.173.03:22:47.41#ibcon#*before return 0, iclass 35, count 0 2006.173.03:22:47.41#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.03:22:47.41#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.03:22:47.41#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.03:22:47.41#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.03:22:47.42$vck44/valo=7,864.99 2006.173.03:22:47.42#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.03:22:47.42#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.03:22:47.42#ibcon#ireg 17 cls_cnt 0 2006.173.03:22:47.42#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.03:22:47.42#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.03:22:47.42#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.03:22:47.42#ibcon#enter wrdev, iclass 37, count 0 2006.173.03:22:47.42#ibcon#first serial, iclass 37, count 0 2006.173.03:22:47.42#ibcon#enter sib2, iclass 37, count 0 2006.173.03:22:47.42#ibcon#flushed, iclass 37, count 0 2006.173.03:22:47.42#ibcon#about to write, iclass 37, count 0 2006.173.03:22:47.42#ibcon#wrote, iclass 37, count 0 2006.173.03:22:47.42#ibcon#about to read 3, iclass 37, count 0 2006.173.03:22:47.43#ibcon#read 3, iclass 37, count 0 2006.173.03:22:47.43#ibcon#about to read 4, iclass 37, count 0 2006.173.03:22:47.43#ibcon#read 4, iclass 37, count 0 2006.173.03:22:47.43#ibcon#about to read 5, iclass 37, count 0 2006.173.03:22:47.43#ibcon#read 5, iclass 37, count 0 2006.173.03:22:47.43#ibcon#about to read 6, iclass 37, count 0 2006.173.03:22:47.43#ibcon#read 6, iclass 37, count 0 2006.173.03:22:47.43#ibcon#end of sib2, iclass 37, count 0 2006.173.03:22:47.43#ibcon#*mode == 0, iclass 37, count 0 2006.173.03:22:47.43#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.03:22:47.43#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.03:22:47.43#ibcon#*before write, iclass 37, count 0 2006.173.03:22:47.43#ibcon#enter sib2, iclass 37, count 0 2006.173.03:22:47.43#ibcon#flushed, iclass 37, count 0 2006.173.03:22:47.43#ibcon#about to write, iclass 37, count 0 2006.173.03:22:47.44#ibcon#wrote, iclass 37, count 0 2006.173.03:22:47.44#ibcon#about to read 3, iclass 37, count 0 2006.173.03:22:47.47#ibcon#read 3, iclass 37, count 0 2006.173.03:22:47.47#ibcon#about to read 4, iclass 37, count 0 2006.173.03:22:47.47#ibcon#read 4, iclass 37, count 0 2006.173.03:22:47.47#ibcon#about to read 5, iclass 37, count 0 2006.173.03:22:47.47#ibcon#read 5, iclass 37, count 0 2006.173.03:22:47.47#ibcon#about to read 6, iclass 37, count 0 2006.173.03:22:47.47#ibcon#read 6, iclass 37, count 0 2006.173.03:22:47.47#ibcon#end of sib2, iclass 37, count 0 2006.173.03:22:47.47#ibcon#*after write, iclass 37, count 0 2006.173.03:22:47.47#ibcon#*before return 0, iclass 37, count 0 2006.173.03:22:47.47#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.03:22:47.47#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.03:22:47.47#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.03:22:47.47#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.03:22:47.48$vck44/va=7,4 2006.173.03:22:47.48#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.03:22:47.48#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.03:22:47.48#ibcon#ireg 11 cls_cnt 2 2006.173.03:22:47.48#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.03:22:47.52#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.03:22:47.52#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.03:22:47.52#ibcon#enter wrdev, iclass 39, count 2 2006.173.03:22:47.52#ibcon#first serial, iclass 39, count 2 2006.173.03:22:47.52#ibcon#enter sib2, iclass 39, count 2 2006.173.03:22:47.52#ibcon#flushed, iclass 39, count 2 2006.173.03:22:47.52#ibcon#about to write, iclass 39, count 2 2006.173.03:22:47.52#ibcon#wrote, iclass 39, count 2 2006.173.03:22:47.52#ibcon#about to read 3, iclass 39, count 2 2006.173.03:22:47.54#ibcon#read 3, iclass 39, count 2 2006.173.03:22:47.54#ibcon#about to read 4, iclass 39, count 2 2006.173.03:22:47.54#ibcon#read 4, iclass 39, count 2 2006.173.03:22:47.54#ibcon#about to read 5, iclass 39, count 2 2006.173.03:22:47.54#ibcon#read 5, iclass 39, count 2 2006.173.03:22:47.54#ibcon#about to read 6, iclass 39, count 2 2006.173.03:22:47.54#ibcon#read 6, iclass 39, count 2 2006.173.03:22:47.54#ibcon#end of sib2, iclass 39, count 2 2006.173.03:22:47.54#ibcon#*mode == 0, iclass 39, count 2 2006.173.03:22:47.54#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.03:22:47.54#ibcon#[25=AT07-04\r\n] 2006.173.03:22:47.54#ibcon#*before write, iclass 39, count 2 2006.173.03:22:47.54#ibcon#enter sib2, iclass 39, count 2 2006.173.03:22:47.54#ibcon#flushed, iclass 39, count 2 2006.173.03:22:47.54#ibcon#about to write, iclass 39, count 2 2006.173.03:22:47.54#ibcon#wrote, iclass 39, count 2 2006.173.03:22:47.55#ibcon#about to read 3, iclass 39, count 2 2006.173.03:22:47.57#ibcon#read 3, iclass 39, count 2 2006.173.03:22:47.57#ibcon#about to read 4, iclass 39, count 2 2006.173.03:22:47.57#ibcon#read 4, iclass 39, count 2 2006.173.03:22:47.57#ibcon#about to read 5, iclass 39, count 2 2006.173.03:22:47.57#ibcon#read 5, iclass 39, count 2 2006.173.03:22:47.57#ibcon#about to read 6, iclass 39, count 2 2006.173.03:22:47.57#ibcon#read 6, iclass 39, count 2 2006.173.03:22:47.57#ibcon#end of sib2, iclass 39, count 2 2006.173.03:22:47.57#ibcon#*after write, iclass 39, count 2 2006.173.03:22:47.57#ibcon#*before return 0, iclass 39, count 2 2006.173.03:22:47.57#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.03:22:47.57#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.03:22:47.57#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.03:22:47.57#ibcon#ireg 7 cls_cnt 0 2006.173.03:22:47.57#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.03:22:47.69#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.03:22:47.69#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.03:22:47.69#ibcon#enter wrdev, iclass 39, count 0 2006.173.03:22:47.69#ibcon#first serial, iclass 39, count 0 2006.173.03:22:47.69#ibcon#enter sib2, iclass 39, count 0 2006.173.03:22:47.69#ibcon#flushed, iclass 39, count 0 2006.173.03:22:47.69#ibcon#about to write, iclass 39, count 0 2006.173.03:22:47.69#ibcon#wrote, iclass 39, count 0 2006.173.03:22:47.69#ibcon#about to read 3, iclass 39, count 0 2006.173.03:22:47.71#ibcon#read 3, iclass 39, count 0 2006.173.03:22:47.71#ibcon#about to read 4, iclass 39, count 0 2006.173.03:22:47.71#ibcon#read 4, iclass 39, count 0 2006.173.03:22:47.71#ibcon#about to read 5, iclass 39, count 0 2006.173.03:22:47.71#ibcon#read 5, iclass 39, count 0 2006.173.03:22:47.71#ibcon#about to read 6, iclass 39, count 0 2006.173.03:22:47.71#ibcon#read 6, iclass 39, count 0 2006.173.03:22:47.71#ibcon#end of sib2, iclass 39, count 0 2006.173.03:22:47.71#ibcon#*mode == 0, iclass 39, count 0 2006.173.03:22:47.71#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.03:22:47.71#ibcon#[25=USB\r\n] 2006.173.03:22:47.71#ibcon#*before write, iclass 39, count 0 2006.173.03:22:47.71#ibcon#enter sib2, iclass 39, count 0 2006.173.03:22:47.71#ibcon#flushed, iclass 39, count 0 2006.173.03:22:47.71#ibcon#about to write, iclass 39, count 0 2006.173.03:22:47.71#ibcon#wrote, iclass 39, count 0 2006.173.03:22:47.72#ibcon#about to read 3, iclass 39, count 0 2006.173.03:22:47.74#ibcon#read 3, iclass 39, count 0 2006.173.03:22:47.74#ibcon#about to read 4, iclass 39, count 0 2006.173.03:22:47.74#ibcon#read 4, iclass 39, count 0 2006.173.03:22:47.74#ibcon#about to read 5, iclass 39, count 0 2006.173.03:22:47.74#ibcon#read 5, iclass 39, count 0 2006.173.03:22:47.74#ibcon#about to read 6, iclass 39, count 0 2006.173.03:22:47.74#ibcon#read 6, iclass 39, count 0 2006.173.03:22:47.74#ibcon#end of sib2, iclass 39, count 0 2006.173.03:22:47.74#ibcon#*after write, iclass 39, count 0 2006.173.03:22:47.74#ibcon#*before return 0, iclass 39, count 0 2006.173.03:22:47.74#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.03:22:47.74#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.03:22:47.74#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.03:22:47.74#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.03:22:47.75$vck44/valo=8,884.99 2006.173.03:22:47.75#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.03:22:47.75#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.03:22:47.75#ibcon#ireg 17 cls_cnt 0 2006.173.03:22:47.75#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.03:22:47.75#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.03:22:47.75#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.03:22:47.75#ibcon#enter wrdev, iclass 3, count 0 2006.173.03:22:47.75#ibcon#first serial, iclass 3, count 0 2006.173.03:22:47.75#ibcon#enter sib2, iclass 3, count 0 2006.173.03:22:47.75#ibcon#flushed, iclass 3, count 0 2006.173.03:22:47.75#ibcon#about to write, iclass 3, count 0 2006.173.03:22:47.75#ibcon#wrote, iclass 3, count 0 2006.173.03:22:47.75#ibcon#about to read 3, iclass 3, count 0 2006.173.03:22:47.76#ibcon#read 3, iclass 3, count 0 2006.173.03:22:47.76#ibcon#about to read 4, iclass 3, count 0 2006.173.03:22:47.76#ibcon#read 4, iclass 3, count 0 2006.173.03:22:47.76#ibcon#about to read 5, iclass 3, count 0 2006.173.03:22:47.76#ibcon#read 5, iclass 3, count 0 2006.173.03:22:47.76#ibcon#about to read 6, iclass 3, count 0 2006.173.03:22:47.76#ibcon#read 6, iclass 3, count 0 2006.173.03:22:47.76#ibcon#end of sib2, iclass 3, count 0 2006.173.03:22:47.76#ibcon#*mode == 0, iclass 3, count 0 2006.173.03:22:47.76#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.03:22:47.76#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.03:22:47.76#ibcon#*before write, iclass 3, count 0 2006.173.03:22:47.76#ibcon#enter sib2, iclass 3, count 0 2006.173.03:22:47.76#ibcon#flushed, iclass 3, count 0 2006.173.03:22:47.76#ibcon#about to write, iclass 3, count 0 2006.173.03:22:47.76#ibcon#wrote, iclass 3, count 0 2006.173.03:22:47.77#ibcon#about to read 3, iclass 3, count 0 2006.173.03:22:47.80#ibcon#read 3, iclass 3, count 0 2006.173.03:22:47.80#ibcon#about to read 4, iclass 3, count 0 2006.173.03:22:47.80#ibcon#read 4, iclass 3, count 0 2006.173.03:22:47.80#ibcon#about to read 5, iclass 3, count 0 2006.173.03:22:47.80#ibcon#read 5, iclass 3, count 0 2006.173.03:22:47.80#ibcon#about to read 6, iclass 3, count 0 2006.173.03:22:47.80#ibcon#read 6, iclass 3, count 0 2006.173.03:22:47.80#ibcon#end of sib2, iclass 3, count 0 2006.173.03:22:47.80#ibcon#*after write, iclass 3, count 0 2006.173.03:22:47.80#ibcon#*before return 0, iclass 3, count 0 2006.173.03:22:47.80#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.03:22:47.80#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.03:22:47.80#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.03:22:47.80#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.03:22:47.81$vck44/va=8,4 2006.173.03:22:47.81#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.03:22:47.81#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.03:22:47.81#ibcon#ireg 11 cls_cnt 2 2006.173.03:22:47.81#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.03:22:47.85#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.03:22:47.85#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.03:22:47.85#ibcon#enter wrdev, iclass 5, count 2 2006.173.03:22:47.85#ibcon#first serial, iclass 5, count 2 2006.173.03:22:47.85#ibcon#enter sib2, iclass 5, count 2 2006.173.03:22:47.85#ibcon#flushed, iclass 5, count 2 2006.173.03:22:47.85#ibcon#about to write, iclass 5, count 2 2006.173.03:22:47.85#ibcon#wrote, iclass 5, count 2 2006.173.03:22:47.85#ibcon#about to read 3, iclass 5, count 2 2006.173.03:22:47.87#ibcon#read 3, iclass 5, count 2 2006.173.03:22:47.87#ibcon#about to read 4, iclass 5, count 2 2006.173.03:22:47.87#ibcon#read 4, iclass 5, count 2 2006.173.03:22:47.87#ibcon#about to read 5, iclass 5, count 2 2006.173.03:22:47.87#ibcon#read 5, iclass 5, count 2 2006.173.03:22:47.87#ibcon#about to read 6, iclass 5, count 2 2006.173.03:22:47.87#ibcon#read 6, iclass 5, count 2 2006.173.03:22:47.87#ibcon#end of sib2, iclass 5, count 2 2006.173.03:22:47.87#ibcon#*mode == 0, iclass 5, count 2 2006.173.03:22:47.87#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.03:22:47.87#ibcon#[25=AT08-04\r\n] 2006.173.03:22:47.87#ibcon#*before write, iclass 5, count 2 2006.173.03:22:47.87#ibcon#enter sib2, iclass 5, count 2 2006.173.03:22:47.87#ibcon#flushed, iclass 5, count 2 2006.173.03:22:47.87#ibcon#about to write, iclass 5, count 2 2006.173.03:22:47.87#ibcon#wrote, iclass 5, count 2 2006.173.03:22:47.88#ibcon#about to read 3, iclass 5, count 2 2006.173.03:22:47.90#ibcon#read 3, iclass 5, count 2 2006.173.03:22:47.90#ibcon#about to read 4, iclass 5, count 2 2006.173.03:22:47.90#ibcon#read 4, iclass 5, count 2 2006.173.03:22:47.90#ibcon#about to read 5, iclass 5, count 2 2006.173.03:22:47.90#ibcon#read 5, iclass 5, count 2 2006.173.03:22:47.90#ibcon#about to read 6, iclass 5, count 2 2006.173.03:22:47.90#ibcon#read 6, iclass 5, count 2 2006.173.03:22:47.90#ibcon#end of sib2, iclass 5, count 2 2006.173.03:22:47.90#ibcon#*after write, iclass 5, count 2 2006.173.03:22:47.90#ibcon#*before return 0, iclass 5, count 2 2006.173.03:22:47.90#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.03:22:47.90#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.03:22:47.90#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.03:22:47.90#ibcon#ireg 7 cls_cnt 0 2006.173.03:22:47.90#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.03:22:48.02#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.03:22:48.02#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.03:22:48.02#ibcon#enter wrdev, iclass 5, count 0 2006.173.03:22:48.02#ibcon#first serial, iclass 5, count 0 2006.173.03:22:48.02#ibcon#enter sib2, iclass 5, count 0 2006.173.03:22:48.02#ibcon#flushed, iclass 5, count 0 2006.173.03:22:48.02#ibcon#about to write, iclass 5, count 0 2006.173.03:22:48.02#ibcon#wrote, iclass 5, count 0 2006.173.03:22:48.02#ibcon#about to read 3, iclass 5, count 0 2006.173.03:22:48.04#ibcon#read 3, iclass 5, count 0 2006.173.03:22:48.04#ibcon#about to read 4, iclass 5, count 0 2006.173.03:22:48.04#ibcon#read 4, iclass 5, count 0 2006.173.03:22:48.04#ibcon#about to read 5, iclass 5, count 0 2006.173.03:22:48.04#ibcon#read 5, iclass 5, count 0 2006.173.03:22:48.04#ibcon#about to read 6, iclass 5, count 0 2006.173.03:22:48.04#ibcon#read 6, iclass 5, count 0 2006.173.03:22:48.04#ibcon#end of sib2, iclass 5, count 0 2006.173.03:22:48.04#ibcon#*mode == 0, iclass 5, count 0 2006.173.03:22:48.04#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.03:22:48.04#ibcon#[25=USB\r\n] 2006.173.03:22:48.04#ibcon#*before write, iclass 5, count 0 2006.173.03:22:48.04#ibcon#enter sib2, iclass 5, count 0 2006.173.03:22:48.04#ibcon#flushed, iclass 5, count 0 2006.173.03:22:48.04#ibcon#about to write, iclass 5, count 0 2006.173.03:22:48.04#ibcon#wrote, iclass 5, count 0 2006.173.03:22:48.05#ibcon#about to read 3, iclass 5, count 0 2006.173.03:22:48.07#ibcon#read 3, iclass 5, count 0 2006.173.03:22:48.07#ibcon#about to read 4, iclass 5, count 0 2006.173.03:22:48.07#ibcon#read 4, iclass 5, count 0 2006.173.03:22:48.07#ibcon#about to read 5, iclass 5, count 0 2006.173.03:22:48.07#ibcon#read 5, iclass 5, count 0 2006.173.03:22:48.07#ibcon#about to read 6, iclass 5, count 0 2006.173.03:22:48.07#ibcon#read 6, iclass 5, count 0 2006.173.03:22:48.07#ibcon#end of sib2, iclass 5, count 0 2006.173.03:22:48.07#ibcon#*after write, iclass 5, count 0 2006.173.03:22:48.07#ibcon#*before return 0, iclass 5, count 0 2006.173.03:22:48.07#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.03:22:48.07#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.03:22:48.07#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.03:22:48.07#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.03:22:48.08$vck44/vblo=1,629.99 2006.173.03:22:48.08#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.03:22:48.08#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.03:22:48.08#ibcon#ireg 17 cls_cnt 0 2006.173.03:22:48.08#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.03:22:48.08#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.03:22:48.08#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.03:22:48.08#ibcon#enter wrdev, iclass 7, count 0 2006.173.03:22:48.08#ibcon#first serial, iclass 7, count 0 2006.173.03:22:48.08#ibcon#enter sib2, iclass 7, count 0 2006.173.03:22:48.08#ibcon#flushed, iclass 7, count 0 2006.173.03:22:48.08#ibcon#about to write, iclass 7, count 0 2006.173.03:22:48.08#ibcon#wrote, iclass 7, count 0 2006.173.03:22:48.08#ibcon#about to read 3, iclass 7, count 0 2006.173.03:22:48.09#ibcon#read 3, iclass 7, count 0 2006.173.03:22:48.09#ibcon#about to read 4, iclass 7, count 0 2006.173.03:22:48.09#ibcon#read 4, iclass 7, count 0 2006.173.03:22:48.09#ibcon#about to read 5, iclass 7, count 0 2006.173.03:22:48.09#ibcon#read 5, iclass 7, count 0 2006.173.03:22:48.09#ibcon#about to read 6, iclass 7, count 0 2006.173.03:22:48.09#ibcon#read 6, iclass 7, count 0 2006.173.03:22:48.09#ibcon#end of sib2, iclass 7, count 0 2006.173.03:22:48.09#ibcon#*mode == 0, iclass 7, count 0 2006.173.03:22:48.09#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.03:22:48.09#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.03:22:48.09#ibcon#*before write, iclass 7, count 0 2006.173.03:22:48.09#ibcon#enter sib2, iclass 7, count 0 2006.173.03:22:48.09#ibcon#flushed, iclass 7, count 0 2006.173.03:22:48.09#ibcon#about to write, iclass 7, count 0 2006.173.03:22:48.10#ibcon#wrote, iclass 7, count 0 2006.173.03:22:48.10#ibcon#about to read 3, iclass 7, count 0 2006.173.03:22:48.13#ibcon#read 3, iclass 7, count 0 2006.173.03:22:48.13#ibcon#about to read 4, iclass 7, count 0 2006.173.03:22:48.13#ibcon#read 4, iclass 7, count 0 2006.173.03:22:48.13#ibcon#about to read 5, iclass 7, count 0 2006.173.03:22:48.13#ibcon#read 5, iclass 7, count 0 2006.173.03:22:48.13#ibcon#about to read 6, iclass 7, count 0 2006.173.03:22:48.13#ibcon#read 6, iclass 7, count 0 2006.173.03:22:48.13#ibcon#end of sib2, iclass 7, count 0 2006.173.03:22:48.13#ibcon#*after write, iclass 7, count 0 2006.173.03:22:48.13#ibcon#*before return 0, iclass 7, count 0 2006.173.03:22:48.13#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.03:22:48.13#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.03:22:48.13#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.03:22:48.13#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.03:22:48.14$vck44/vb=1,4 2006.173.03:22:48.14#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.03:22:48.14#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.03:22:48.14#ibcon#ireg 11 cls_cnt 2 2006.173.03:22:48.14#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.03:22:48.14#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.03:22:48.14#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.03:22:48.14#ibcon#enter wrdev, iclass 11, count 2 2006.173.03:22:48.14#ibcon#first serial, iclass 11, count 2 2006.173.03:22:48.14#ibcon#enter sib2, iclass 11, count 2 2006.173.03:22:48.14#ibcon#flushed, iclass 11, count 2 2006.173.03:22:48.14#ibcon#about to write, iclass 11, count 2 2006.173.03:22:48.14#ibcon#wrote, iclass 11, count 2 2006.173.03:22:48.14#ibcon#about to read 3, iclass 11, count 2 2006.173.03:22:48.15#ibcon#read 3, iclass 11, count 2 2006.173.03:22:48.15#ibcon#about to read 4, iclass 11, count 2 2006.173.03:22:48.15#ibcon#read 4, iclass 11, count 2 2006.173.03:22:48.15#ibcon#about to read 5, iclass 11, count 2 2006.173.03:22:48.15#ibcon#read 5, iclass 11, count 2 2006.173.03:22:48.15#ibcon#about to read 6, iclass 11, count 2 2006.173.03:22:48.15#ibcon#read 6, iclass 11, count 2 2006.173.03:22:48.15#ibcon#end of sib2, iclass 11, count 2 2006.173.03:22:48.15#ibcon#*mode == 0, iclass 11, count 2 2006.173.03:22:48.15#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.03:22:48.15#ibcon#[27=AT01-04\r\n] 2006.173.03:22:48.15#ibcon#*before write, iclass 11, count 2 2006.173.03:22:48.15#ibcon#enter sib2, iclass 11, count 2 2006.173.03:22:48.15#ibcon#flushed, iclass 11, count 2 2006.173.03:22:48.15#ibcon#about to write, iclass 11, count 2 2006.173.03:22:48.15#ibcon#wrote, iclass 11, count 2 2006.173.03:22:48.16#ibcon#about to read 3, iclass 11, count 2 2006.173.03:22:48.18#ibcon#read 3, iclass 11, count 2 2006.173.03:22:48.18#ibcon#about to read 4, iclass 11, count 2 2006.173.03:22:48.18#ibcon#read 4, iclass 11, count 2 2006.173.03:22:48.18#ibcon#about to read 5, iclass 11, count 2 2006.173.03:22:48.18#ibcon#read 5, iclass 11, count 2 2006.173.03:22:48.18#ibcon#about to read 6, iclass 11, count 2 2006.173.03:22:48.18#ibcon#read 6, iclass 11, count 2 2006.173.03:22:48.18#ibcon#end of sib2, iclass 11, count 2 2006.173.03:22:48.18#ibcon#*after write, iclass 11, count 2 2006.173.03:22:48.18#ibcon#*before return 0, iclass 11, count 2 2006.173.03:22:48.18#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.03:22:48.18#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.03:22:48.18#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.03:22:48.18#ibcon#ireg 7 cls_cnt 0 2006.173.03:22:48.18#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.03:22:48.30#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.03:22:48.30#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.03:22:48.30#ibcon#enter wrdev, iclass 11, count 0 2006.173.03:22:48.30#ibcon#first serial, iclass 11, count 0 2006.173.03:22:48.30#ibcon#enter sib2, iclass 11, count 0 2006.173.03:22:48.30#ibcon#flushed, iclass 11, count 0 2006.173.03:22:48.30#ibcon#about to write, iclass 11, count 0 2006.173.03:22:48.30#ibcon#wrote, iclass 11, count 0 2006.173.03:22:48.30#ibcon#about to read 3, iclass 11, count 0 2006.173.03:22:48.32#ibcon#read 3, iclass 11, count 0 2006.173.03:22:48.32#ibcon#about to read 4, iclass 11, count 0 2006.173.03:22:48.32#ibcon#read 4, iclass 11, count 0 2006.173.03:22:48.32#ibcon#about to read 5, iclass 11, count 0 2006.173.03:22:48.32#ibcon#read 5, iclass 11, count 0 2006.173.03:22:48.32#ibcon#about to read 6, iclass 11, count 0 2006.173.03:22:48.32#ibcon#read 6, iclass 11, count 0 2006.173.03:22:48.32#ibcon#end of sib2, iclass 11, count 0 2006.173.03:22:48.32#ibcon#*mode == 0, iclass 11, count 0 2006.173.03:22:48.32#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.03:22:48.32#ibcon#[27=USB\r\n] 2006.173.03:22:48.32#ibcon#*before write, iclass 11, count 0 2006.173.03:22:48.32#ibcon#enter sib2, iclass 11, count 0 2006.173.03:22:48.32#ibcon#flushed, iclass 11, count 0 2006.173.03:22:48.32#ibcon#about to write, iclass 11, count 0 2006.173.03:22:48.32#ibcon#wrote, iclass 11, count 0 2006.173.03:22:48.33#ibcon#about to read 3, iclass 11, count 0 2006.173.03:22:48.35#ibcon#read 3, iclass 11, count 0 2006.173.03:22:48.35#ibcon#about to read 4, iclass 11, count 0 2006.173.03:22:48.35#ibcon#read 4, iclass 11, count 0 2006.173.03:22:48.35#ibcon#about to read 5, iclass 11, count 0 2006.173.03:22:48.35#ibcon#read 5, iclass 11, count 0 2006.173.03:22:48.35#ibcon#about to read 6, iclass 11, count 0 2006.173.03:22:48.35#ibcon#read 6, iclass 11, count 0 2006.173.03:22:48.35#ibcon#end of sib2, iclass 11, count 0 2006.173.03:22:48.35#ibcon#*after write, iclass 11, count 0 2006.173.03:22:48.35#ibcon#*before return 0, iclass 11, count 0 2006.173.03:22:48.35#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.03:22:48.35#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.03:22:48.35#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.03:22:48.35#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.03:22:48.36$vck44/vblo=2,634.99 2006.173.03:22:48.36#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.03:22:48.36#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.03:22:48.36#ibcon#ireg 17 cls_cnt 0 2006.173.03:22:48.36#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.03:22:48.36#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.03:22:48.36#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.03:22:48.36#ibcon#enter wrdev, iclass 13, count 0 2006.173.03:22:48.36#ibcon#first serial, iclass 13, count 0 2006.173.03:22:48.36#ibcon#enter sib2, iclass 13, count 0 2006.173.03:22:48.36#ibcon#flushed, iclass 13, count 0 2006.173.03:22:48.36#ibcon#about to write, iclass 13, count 0 2006.173.03:22:48.36#ibcon#wrote, iclass 13, count 0 2006.173.03:22:48.36#ibcon#about to read 3, iclass 13, count 0 2006.173.03:22:48.37#ibcon#read 3, iclass 13, count 0 2006.173.03:22:48.37#ibcon#about to read 4, iclass 13, count 0 2006.173.03:22:48.37#ibcon#read 4, iclass 13, count 0 2006.173.03:22:48.37#ibcon#about to read 5, iclass 13, count 0 2006.173.03:22:48.37#ibcon#read 5, iclass 13, count 0 2006.173.03:22:48.37#ibcon#about to read 6, iclass 13, count 0 2006.173.03:22:48.37#ibcon#read 6, iclass 13, count 0 2006.173.03:22:48.37#ibcon#end of sib2, iclass 13, count 0 2006.173.03:22:48.37#ibcon#*mode == 0, iclass 13, count 0 2006.173.03:22:48.37#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.03:22:48.37#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.03:22:48.37#ibcon#*before write, iclass 13, count 0 2006.173.03:22:48.37#ibcon#enter sib2, iclass 13, count 0 2006.173.03:22:48.37#ibcon#flushed, iclass 13, count 0 2006.173.03:22:48.37#ibcon#about to write, iclass 13, count 0 2006.173.03:22:48.38#ibcon#wrote, iclass 13, count 0 2006.173.03:22:48.38#ibcon#about to read 3, iclass 13, count 0 2006.173.03:22:48.41#ibcon#read 3, iclass 13, count 0 2006.173.03:22:48.41#ibcon#about to read 4, iclass 13, count 0 2006.173.03:22:48.41#ibcon#read 4, iclass 13, count 0 2006.173.03:22:48.41#ibcon#about to read 5, iclass 13, count 0 2006.173.03:22:48.41#ibcon#read 5, iclass 13, count 0 2006.173.03:22:48.41#ibcon#about to read 6, iclass 13, count 0 2006.173.03:22:48.41#ibcon#read 6, iclass 13, count 0 2006.173.03:22:48.41#ibcon#end of sib2, iclass 13, count 0 2006.173.03:22:48.41#ibcon#*after write, iclass 13, count 0 2006.173.03:22:48.41#ibcon#*before return 0, iclass 13, count 0 2006.173.03:22:48.41#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.03:22:48.41#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.03:22:48.41#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.03:22:48.41#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.03:22:48.42$vck44/vb=2,4 2006.173.03:22:48.42#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.03:22:48.42#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.03:22:48.42#ibcon#ireg 11 cls_cnt 2 2006.173.03:22:48.42#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.03:22:48.46#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.03:22:48.46#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.03:22:48.46#ibcon#enter wrdev, iclass 15, count 2 2006.173.03:22:48.46#ibcon#first serial, iclass 15, count 2 2006.173.03:22:48.46#ibcon#enter sib2, iclass 15, count 2 2006.173.03:22:48.46#ibcon#flushed, iclass 15, count 2 2006.173.03:22:48.46#ibcon#about to write, iclass 15, count 2 2006.173.03:22:48.46#ibcon#wrote, iclass 15, count 2 2006.173.03:22:48.46#ibcon#about to read 3, iclass 15, count 2 2006.173.03:22:48.48#ibcon#read 3, iclass 15, count 2 2006.173.03:22:48.48#ibcon#about to read 4, iclass 15, count 2 2006.173.03:22:48.48#ibcon#read 4, iclass 15, count 2 2006.173.03:22:48.48#ibcon#about to read 5, iclass 15, count 2 2006.173.03:22:48.48#ibcon#read 5, iclass 15, count 2 2006.173.03:22:48.48#ibcon#about to read 6, iclass 15, count 2 2006.173.03:22:48.48#ibcon#read 6, iclass 15, count 2 2006.173.03:22:48.48#ibcon#end of sib2, iclass 15, count 2 2006.173.03:22:48.48#ibcon#*mode == 0, iclass 15, count 2 2006.173.03:22:48.48#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.03:22:48.48#ibcon#[27=AT02-04\r\n] 2006.173.03:22:48.48#ibcon#*before write, iclass 15, count 2 2006.173.03:22:48.48#ibcon#enter sib2, iclass 15, count 2 2006.173.03:22:48.48#ibcon#flushed, iclass 15, count 2 2006.173.03:22:48.48#ibcon#about to write, iclass 15, count 2 2006.173.03:22:48.48#ibcon#wrote, iclass 15, count 2 2006.173.03:22:48.49#ibcon#about to read 3, iclass 15, count 2 2006.173.03:22:48.51#ibcon#read 3, iclass 15, count 2 2006.173.03:22:48.51#ibcon#about to read 4, iclass 15, count 2 2006.173.03:22:48.51#ibcon#read 4, iclass 15, count 2 2006.173.03:22:48.51#ibcon#about to read 5, iclass 15, count 2 2006.173.03:22:48.51#ibcon#read 5, iclass 15, count 2 2006.173.03:22:48.51#ibcon#about to read 6, iclass 15, count 2 2006.173.03:22:48.51#ibcon#read 6, iclass 15, count 2 2006.173.03:22:48.51#ibcon#end of sib2, iclass 15, count 2 2006.173.03:22:48.51#ibcon#*after write, iclass 15, count 2 2006.173.03:22:48.51#ibcon#*before return 0, iclass 15, count 2 2006.173.03:22:48.51#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.03:22:48.51#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.03:22:48.51#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.03:22:48.51#ibcon#ireg 7 cls_cnt 0 2006.173.03:22:48.51#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.03:22:48.63#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.03:22:48.63#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.03:22:48.63#ibcon#enter wrdev, iclass 15, count 0 2006.173.03:22:48.63#ibcon#first serial, iclass 15, count 0 2006.173.03:22:48.63#ibcon#enter sib2, iclass 15, count 0 2006.173.03:22:48.63#ibcon#flushed, iclass 15, count 0 2006.173.03:22:48.63#ibcon#about to write, iclass 15, count 0 2006.173.03:22:48.63#ibcon#wrote, iclass 15, count 0 2006.173.03:22:48.63#ibcon#about to read 3, iclass 15, count 0 2006.173.03:22:48.65#ibcon#read 3, iclass 15, count 0 2006.173.03:22:48.65#ibcon#about to read 4, iclass 15, count 0 2006.173.03:22:48.65#ibcon#read 4, iclass 15, count 0 2006.173.03:22:48.65#ibcon#about to read 5, iclass 15, count 0 2006.173.03:22:48.65#ibcon#read 5, iclass 15, count 0 2006.173.03:22:48.65#ibcon#about to read 6, iclass 15, count 0 2006.173.03:22:48.65#ibcon#read 6, iclass 15, count 0 2006.173.03:22:48.65#ibcon#end of sib2, iclass 15, count 0 2006.173.03:22:48.65#ibcon#*mode == 0, iclass 15, count 0 2006.173.03:22:48.65#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.03:22:48.65#ibcon#[27=USB\r\n] 2006.173.03:22:48.65#ibcon#*before write, iclass 15, count 0 2006.173.03:22:48.65#ibcon#enter sib2, iclass 15, count 0 2006.173.03:22:48.65#ibcon#flushed, iclass 15, count 0 2006.173.03:22:48.65#ibcon#about to write, iclass 15, count 0 2006.173.03:22:48.65#ibcon#wrote, iclass 15, count 0 2006.173.03:22:48.66#ibcon#about to read 3, iclass 15, count 0 2006.173.03:22:48.68#ibcon#read 3, iclass 15, count 0 2006.173.03:22:48.68#ibcon#about to read 4, iclass 15, count 0 2006.173.03:22:48.68#ibcon#read 4, iclass 15, count 0 2006.173.03:22:48.68#ibcon#about to read 5, iclass 15, count 0 2006.173.03:22:48.68#ibcon#read 5, iclass 15, count 0 2006.173.03:22:48.68#ibcon#about to read 6, iclass 15, count 0 2006.173.03:22:48.68#ibcon#read 6, iclass 15, count 0 2006.173.03:22:48.68#ibcon#end of sib2, iclass 15, count 0 2006.173.03:22:48.68#ibcon#*after write, iclass 15, count 0 2006.173.03:22:48.68#ibcon#*before return 0, iclass 15, count 0 2006.173.03:22:48.68#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.03:22:48.68#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.03:22:48.68#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.03:22:48.68#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.03:22:48.69$vck44/vblo=3,649.99 2006.173.03:22:48.69#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.03:22:48.69#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.03:22:48.69#ibcon#ireg 17 cls_cnt 0 2006.173.03:22:48.69#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.03:22:48.69#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.03:22:48.69#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.03:22:48.69#ibcon#enter wrdev, iclass 17, count 0 2006.173.03:22:48.69#ibcon#first serial, iclass 17, count 0 2006.173.03:22:48.69#ibcon#enter sib2, iclass 17, count 0 2006.173.03:22:48.69#ibcon#flushed, iclass 17, count 0 2006.173.03:22:48.69#ibcon#about to write, iclass 17, count 0 2006.173.03:22:48.69#ibcon#wrote, iclass 17, count 0 2006.173.03:22:48.69#ibcon#about to read 3, iclass 17, count 0 2006.173.03:22:48.70#ibcon#read 3, iclass 17, count 0 2006.173.03:22:48.70#ibcon#about to read 4, iclass 17, count 0 2006.173.03:22:48.70#ibcon#read 4, iclass 17, count 0 2006.173.03:22:48.70#ibcon#about to read 5, iclass 17, count 0 2006.173.03:22:48.70#ibcon#read 5, iclass 17, count 0 2006.173.03:22:48.70#ibcon#about to read 6, iclass 17, count 0 2006.173.03:22:48.70#ibcon#read 6, iclass 17, count 0 2006.173.03:22:48.70#ibcon#end of sib2, iclass 17, count 0 2006.173.03:22:48.70#ibcon#*mode == 0, iclass 17, count 0 2006.173.03:22:48.70#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.03:22:48.70#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.03:22:48.70#ibcon#*before write, iclass 17, count 0 2006.173.03:22:48.70#ibcon#enter sib2, iclass 17, count 0 2006.173.03:22:48.70#ibcon#flushed, iclass 17, count 0 2006.173.03:22:48.70#ibcon#about to write, iclass 17, count 0 2006.173.03:22:48.71#ibcon#wrote, iclass 17, count 0 2006.173.03:22:48.71#ibcon#about to read 3, iclass 17, count 0 2006.173.03:22:48.74#ibcon#read 3, iclass 17, count 0 2006.173.03:22:48.74#ibcon#about to read 4, iclass 17, count 0 2006.173.03:22:48.74#ibcon#read 4, iclass 17, count 0 2006.173.03:22:48.74#ibcon#about to read 5, iclass 17, count 0 2006.173.03:22:48.74#ibcon#read 5, iclass 17, count 0 2006.173.03:22:48.74#ibcon#about to read 6, iclass 17, count 0 2006.173.03:22:48.74#ibcon#read 6, iclass 17, count 0 2006.173.03:22:48.74#ibcon#end of sib2, iclass 17, count 0 2006.173.03:22:48.74#ibcon#*after write, iclass 17, count 0 2006.173.03:22:48.74#ibcon#*before return 0, iclass 17, count 0 2006.173.03:22:48.74#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.03:22:48.74#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.03:22:48.74#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.03:22:48.74#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.03:22:48.75$vck44/vb=3,4 2006.173.03:22:48.75#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.03:22:48.75#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.03:22:48.75#ibcon#ireg 11 cls_cnt 2 2006.173.03:22:48.75#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.03:22:48.79#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.03:22:48.79#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.03:22:48.79#ibcon#enter wrdev, iclass 19, count 2 2006.173.03:22:48.79#ibcon#first serial, iclass 19, count 2 2006.173.03:22:48.79#ibcon#enter sib2, iclass 19, count 2 2006.173.03:22:48.79#ibcon#flushed, iclass 19, count 2 2006.173.03:22:48.79#ibcon#about to write, iclass 19, count 2 2006.173.03:22:48.79#ibcon#wrote, iclass 19, count 2 2006.173.03:22:48.79#ibcon#about to read 3, iclass 19, count 2 2006.173.03:22:48.81#ibcon#read 3, iclass 19, count 2 2006.173.03:22:48.81#ibcon#about to read 4, iclass 19, count 2 2006.173.03:22:48.81#ibcon#read 4, iclass 19, count 2 2006.173.03:22:48.81#ibcon#about to read 5, iclass 19, count 2 2006.173.03:22:48.81#ibcon#read 5, iclass 19, count 2 2006.173.03:22:48.81#ibcon#about to read 6, iclass 19, count 2 2006.173.03:22:48.81#ibcon#read 6, iclass 19, count 2 2006.173.03:22:48.81#ibcon#end of sib2, iclass 19, count 2 2006.173.03:22:48.81#ibcon#*mode == 0, iclass 19, count 2 2006.173.03:22:48.81#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.03:22:48.81#ibcon#[27=AT03-04\r\n] 2006.173.03:22:48.81#ibcon#*before write, iclass 19, count 2 2006.173.03:22:48.81#ibcon#enter sib2, iclass 19, count 2 2006.173.03:22:48.81#ibcon#flushed, iclass 19, count 2 2006.173.03:22:48.81#ibcon#about to write, iclass 19, count 2 2006.173.03:22:48.81#ibcon#wrote, iclass 19, count 2 2006.173.03:22:48.82#ibcon#about to read 3, iclass 19, count 2 2006.173.03:22:48.84#ibcon#read 3, iclass 19, count 2 2006.173.03:22:48.84#ibcon#about to read 4, iclass 19, count 2 2006.173.03:22:48.84#ibcon#read 4, iclass 19, count 2 2006.173.03:22:48.84#ibcon#about to read 5, iclass 19, count 2 2006.173.03:22:48.84#ibcon#read 5, iclass 19, count 2 2006.173.03:22:48.84#ibcon#about to read 6, iclass 19, count 2 2006.173.03:22:48.84#ibcon#read 6, iclass 19, count 2 2006.173.03:22:48.84#ibcon#end of sib2, iclass 19, count 2 2006.173.03:22:48.84#ibcon#*after write, iclass 19, count 2 2006.173.03:22:48.84#ibcon#*before return 0, iclass 19, count 2 2006.173.03:22:48.84#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.03:22:48.84#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.03:22:48.84#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.03:22:48.84#ibcon#ireg 7 cls_cnt 0 2006.173.03:22:48.84#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.03:22:48.96#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.03:22:48.96#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.03:22:48.96#ibcon#enter wrdev, iclass 19, count 0 2006.173.03:22:48.96#ibcon#first serial, iclass 19, count 0 2006.173.03:22:48.96#ibcon#enter sib2, iclass 19, count 0 2006.173.03:22:48.96#ibcon#flushed, iclass 19, count 0 2006.173.03:22:48.96#ibcon#about to write, iclass 19, count 0 2006.173.03:22:48.96#ibcon#wrote, iclass 19, count 0 2006.173.03:22:48.96#ibcon#about to read 3, iclass 19, count 0 2006.173.03:22:48.98#ibcon#read 3, iclass 19, count 0 2006.173.03:22:48.98#ibcon#about to read 4, iclass 19, count 0 2006.173.03:22:48.98#ibcon#read 4, iclass 19, count 0 2006.173.03:22:48.98#ibcon#about to read 5, iclass 19, count 0 2006.173.03:22:48.98#ibcon#read 5, iclass 19, count 0 2006.173.03:22:48.98#ibcon#about to read 6, iclass 19, count 0 2006.173.03:22:48.98#ibcon#read 6, iclass 19, count 0 2006.173.03:22:48.98#ibcon#end of sib2, iclass 19, count 0 2006.173.03:22:48.98#ibcon#*mode == 0, iclass 19, count 0 2006.173.03:22:48.98#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.03:22:48.98#ibcon#[27=USB\r\n] 2006.173.03:22:48.98#ibcon#*before write, iclass 19, count 0 2006.173.03:22:48.98#ibcon#enter sib2, iclass 19, count 0 2006.173.03:22:48.98#ibcon#flushed, iclass 19, count 0 2006.173.03:22:48.98#ibcon#about to write, iclass 19, count 0 2006.173.03:22:48.98#ibcon#wrote, iclass 19, count 0 2006.173.03:22:48.99#ibcon#about to read 3, iclass 19, count 0 2006.173.03:22:49.01#ibcon#read 3, iclass 19, count 0 2006.173.03:22:49.01#ibcon#about to read 4, iclass 19, count 0 2006.173.03:22:49.01#ibcon#read 4, iclass 19, count 0 2006.173.03:22:49.01#ibcon#about to read 5, iclass 19, count 0 2006.173.03:22:49.01#ibcon#read 5, iclass 19, count 0 2006.173.03:22:49.01#ibcon#about to read 6, iclass 19, count 0 2006.173.03:22:49.01#ibcon#read 6, iclass 19, count 0 2006.173.03:22:49.01#ibcon#end of sib2, iclass 19, count 0 2006.173.03:22:49.01#ibcon#*after write, iclass 19, count 0 2006.173.03:22:49.01#ibcon#*before return 0, iclass 19, count 0 2006.173.03:22:49.01#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.03:22:49.01#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.03:22:49.01#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.03:22:49.01#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.03:22:49.02$vck44/vblo=4,679.99 2006.173.03:22:49.02#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.03:22:49.02#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.03:22:49.02#ibcon#ireg 17 cls_cnt 0 2006.173.03:22:49.02#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.03:22:49.02#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.03:22:49.02#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.03:22:49.02#ibcon#enter wrdev, iclass 21, count 0 2006.173.03:22:49.02#ibcon#first serial, iclass 21, count 0 2006.173.03:22:49.02#ibcon#enter sib2, iclass 21, count 0 2006.173.03:22:49.02#ibcon#flushed, iclass 21, count 0 2006.173.03:22:49.02#ibcon#about to write, iclass 21, count 0 2006.173.03:22:49.02#ibcon#wrote, iclass 21, count 0 2006.173.03:22:49.02#ibcon#about to read 3, iclass 21, count 0 2006.173.03:22:49.03#ibcon#read 3, iclass 21, count 0 2006.173.03:22:49.03#ibcon#about to read 4, iclass 21, count 0 2006.173.03:22:49.03#ibcon#read 4, iclass 21, count 0 2006.173.03:22:49.03#ibcon#about to read 5, iclass 21, count 0 2006.173.03:22:49.03#ibcon#read 5, iclass 21, count 0 2006.173.03:22:49.03#ibcon#about to read 6, iclass 21, count 0 2006.173.03:22:49.03#ibcon#read 6, iclass 21, count 0 2006.173.03:22:49.03#ibcon#end of sib2, iclass 21, count 0 2006.173.03:22:49.03#ibcon#*mode == 0, iclass 21, count 0 2006.173.03:22:49.03#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.03:22:49.03#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.03:22:49.03#ibcon#*before write, iclass 21, count 0 2006.173.03:22:49.03#ibcon#enter sib2, iclass 21, count 0 2006.173.03:22:49.03#ibcon#flushed, iclass 21, count 0 2006.173.03:22:49.03#ibcon#about to write, iclass 21, count 0 2006.173.03:22:49.03#ibcon#wrote, iclass 21, count 0 2006.173.03:22:49.04#ibcon#about to read 3, iclass 21, count 0 2006.173.03:22:49.07#ibcon#read 3, iclass 21, count 0 2006.173.03:22:49.07#ibcon#about to read 4, iclass 21, count 0 2006.173.03:22:49.07#ibcon#read 4, iclass 21, count 0 2006.173.03:22:49.07#ibcon#about to read 5, iclass 21, count 0 2006.173.03:22:49.07#ibcon#read 5, iclass 21, count 0 2006.173.03:22:49.07#ibcon#about to read 6, iclass 21, count 0 2006.173.03:22:49.07#ibcon#read 6, iclass 21, count 0 2006.173.03:22:49.07#ibcon#end of sib2, iclass 21, count 0 2006.173.03:22:49.07#ibcon#*after write, iclass 21, count 0 2006.173.03:22:49.07#ibcon#*before return 0, iclass 21, count 0 2006.173.03:22:49.07#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.03:22:49.07#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.03:22:49.07#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.03:22:49.07#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.03:22:49.08$vck44/vb=4,4 2006.173.03:22:49.08#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.03:22:49.08#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.03:22:49.08#ibcon#ireg 11 cls_cnt 2 2006.173.03:22:49.08#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.03:22:49.12#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.03:22:49.12#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.03:22:49.12#ibcon#enter wrdev, iclass 23, count 2 2006.173.03:22:49.12#ibcon#first serial, iclass 23, count 2 2006.173.03:22:49.12#ibcon#enter sib2, iclass 23, count 2 2006.173.03:22:49.12#ibcon#flushed, iclass 23, count 2 2006.173.03:22:49.12#ibcon#about to write, iclass 23, count 2 2006.173.03:22:49.12#ibcon#wrote, iclass 23, count 2 2006.173.03:22:49.12#ibcon#about to read 3, iclass 23, count 2 2006.173.03:22:49.14#ibcon#read 3, iclass 23, count 2 2006.173.03:22:49.14#ibcon#about to read 4, iclass 23, count 2 2006.173.03:22:49.14#ibcon#read 4, iclass 23, count 2 2006.173.03:22:49.14#ibcon#about to read 5, iclass 23, count 2 2006.173.03:22:49.14#ibcon#read 5, iclass 23, count 2 2006.173.03:22:49.14#ibcon#about to read 6, iclass 23, count 2 2006.173.03:22:49.14#ibcon#read 6, iclass 23, count 2 2006.173.03:22:49.14#ibcon#end of sib2, iclass 23, count 2 2006.173.03:22:49.14#ibcon#*mode == 0, iclass 23, count 2 2006.173.03:22:49.14#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.03:22:49.14#ibcon#[27=AT04-04\r\n] 2006.173.03:22:49.14#ibcon#*before write, iclass 23, count 2 2006.173.03:22:49.14#ibcon#enter sib2, iclass 23, count 2 2006.173.03:22:49.14#ibcon#flushed, iclass 23, count 2 2006.173.03:22:49.14#ibcon#about to write, iclass 23, count 2 2006.173.03:22:49.14#ibcon#wrote, iclass 23, count 2 2006.173.03:22:49.15#ibcon#about to read 3, iclass 23, count 2 2006.173.03:22:49.17#ibcon#read 3, iclass 23, count 2 2006.173.03:22:49.17#ibcon#about to read 4, iclass 23, count 2 2006.173.03:22:49.17#ibcon#read 4, iclass 23, count 2 2006.173.03:22:49.17#ibcon#about to read 5, iclass 23, count 2 2006.173.03:22:49.17#ibcon#read 5, iclass 23, count 2 2006.173.03:22:49.17#ibcon#about to read 6, iclass 23, count 2 2006.173.03:22:49.17#ibcon#read 6, iclass 23, count 2 2006.173.03:22:49.17#ibcon#end of sib2, iclass 23, count 2 2006.173.03:22:49.17#ibcon#*after write, iclass 23, count 2 2006.173.03:22:49.17#ibcon#*before return 0, iclass 23, count 2 2006.173.03:22:49.17#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.03:22:49.17#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.03:22:49.17#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.03:22:49.17#ibcon#ireg 7 cls_cnt 0 2006.173.03:22:49.17#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.03:22:49.29#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.03:22:49.29#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.03:22:49.29#ibcon#enter wrdev, iclass 23, count 0 2006.173.03:22:49.29#ibcon#first serial, iclass 23, count 0 2006.173.03:22:49.29#ibcon#enter sib2, iclass 23, count 0 2006.173.03:22:49.29#ibcon#flushed, iclass 23, count 0 2006.173.03:22:49.29#ibcon#about to write, iclass 23, count 0 2006.173.03:22:49.29#ibcon#wrote, iclass 23, count 0 2006.173.03:22:49.29#ibcon#about to read 3, iclass 23, count 0 2006.173.03:22:49.31#ibcon#read 3, iclass 23, count 0 2006.173.03:22:49.31#ibcon#about to read 4, iclass 23, count 0 2006.173.03:22:49.31#ibcon#read 4, iclass 23, count 0 2006.173.03:22:49.31#ibcon#about to read 5, iclass 23, count 0 2006.173.03:22:49.31#ibcon#read 5, iclass 23, count 0 2006.173.03:22:49.31#ibcon#about to read 6, iclass 23, count 0 2006.173.03:22:49.31#ibcon#read 6, iclass 23, count 0 2006.173.03:22:49.31#ibcon#end of sib2, iclass 23, count 0 2006.173.03:22:49.31#ibcon#*mode == 0, iclass 23, count 0 2006.173.03:22:49.31#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.03:22:49.31#ibcon#[27=USB\r\n] 2006.173.03:22:49.31#ibcon#*before write, iclass 23, count 0 2006.173.03:22:49.31#ibcon#enter sib2, iclass 23, count 0 2006.173.03:22:49.31#ibcon#flushed, iclass 23, count 0 2006.173.03:22:49.31#ibcon#about to write, iclass 23, count 0 2006.173.03:22:49.31#ibcon#wrote, iclass 23, count 0 2006.173.03:22:49.32#ibcon#about to read 3, iclass 23, count 0 2006.173.03:22:49.34#ibcon#read 3, iclass 23, count 0 2006.173.03:22:49.34#ibcon#about to read 4, iclass 23, count 0 2006.173.03:22:49.34#ibcon#read 4, iclass 23, count 0 2006.173.03:22:49.34#ibcon#about to read 5, iclass 23, count 0 2006.173.03:22:49.34#ibcon#read 5, iclass 23, count 0 2006.173.03:22:49.34#ibcon#about to read 6, iclass 23, count 0 2006.173.03:22:49.34#ibcon#read 6, iclass 23, count 0 2006.173.03:22:49.34#ibcon#end of sib2, iclass 23, count 0 2006.173.03:22:49.34#ibcon#*after write, iclass 23, count 0 2006.173.03:22:49.34#ibcon#*before return 0, iclass 23, count 0 2006.173.03:22:49.34#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.03:22:49.34#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.03:22:49.34#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.03:22:49.34#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.03:22:49.35$vck44/vblo=5,709.99 2006.173.03:22:49.35#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.03:22:49.35#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.03:22:49.35#ibcon#ireg 17 cls_cnt 0 2006.173.03:22:49.35#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.03:22:49.35#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.03:22:49.35#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.03:22:49.35#ibcon#enter wrdev, iclass 25, count 0 2006.173.03:22:49.35#ibcon#first serial, iclass 25, count 0 2006.173.03:22:49.35#ibcon#enter sib2, iclass 25, count 0 2006.173.03:22:49.35#ibcon#flushed, iclass 25, count 0 2006.173.03:22:49.35#ibcon#about to write, iclass 25, count 0 2006.173.03:22:49.35#ibcon#wrote, iclass 25, count 0 2006.173.03:22:49.35#ibcon#about to read 3, iclass 25, count 0 2006.173.03:22:49.36#ibcon#read 3, iclass 25, count 0 2006.173.03:22:49.36#ibcon#about to read 4, iclass 25, count 0 2006.173.03:22:49.36#ibcon#read 4, iclass 25, count 0 2006.173.03:22:49.36#ibcon#about to read 5, iclass 25, count 0 2006.173.03:22:49.36#ibcon#read 5, iclass 25, count 0 2006.173.03:22:49.36#ibcon#about to read 6, iclass 25, count 0 2006.173.03:22:49.36#ibcon#read 6, iclass 25, count 0 2006.173.03:22:49.36#ibcon#end of sib2, iclass 25, count 0 2006.173.03:22:49.36#ibcon#*mode == 0, iclass 25, count 0 2006.173.03:22:49.36#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.03:22:49.36#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.03:22:49.36#ibcon#*before write, iclass 25, count 0 2006.173.03:22:49.36#ibcon#enter sib2, iclass 25, count 0 2006.173.03:22:49.36#ibcon#flushed, iclass 25, count 0 2006.173.03:22:49.36#ibcon#about to write, iclass 25, count 0 2006.173.03:22:49.36#ibcon#wrote, iclass 25, count 0 2006.173.03:22:49.37#ibcon#about to read 3, iclass 25, count 0 2006.173.03:22:49.40#ibcon#read 3, iclass 25, count 0 2006.173.03:22:49.40#ibcon#about to read 4, iclass 25, count 0 2006.173.03:22:49.40#ibcon#read 4, iclass 25, count 0 2006.173.03:22:49.40#ibcon#about to read 5, iclass 25, count 0 2006.173.03:22:49.40#ibcon#read 5, iclass 25, count 0 2006.173.03:22:49.40#ibcon#about to read 6, iclass 25, count 0 2006.173.03:22:49.40#ibcon#read 6, iclass 25, count 0 2006.173.03:22:49.40#ibcon#end of sib2, iclass 25, count 0 2006.173.03:22:49.40#ibcon#*after write, iclass 25, count 0 2006.173.03:22:49.40#ibcon#*before return 0, iclass 25, count 0 2006.173.03:22:49.40#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.03:22:49.40#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.03:22:49.40#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.03:22:49.40#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.03:22:49.41$vck44/vb=5,4 2006.173.03:22:49.41#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.03:22:49.41#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.03:22:49.41#ibcon#ireg 11 cls_cnt 2 2006.173.03:22:49.41#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.03:22:49.45#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.03:22:49.45#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.03:22:49.45#ibcon#enter wrdev, iclass 27, count 2 2006.173.03:22:49.45#ibcon#first serial, iclass 27, count 2 2006.173.03:22:49.45#ibcon#enter sib2, iclass 27, count 2 2006.173.03:22:49.45#ibcon#flushed, iclass 27, count 2 2006.173.03:22:49.45#ibcon#about to write, iclass 27, count 2 2006.173.03:22:49.45#ibcon#wrote, iclass 27, count 2 2006.173.03:22:49.45#ibcon#about to read 3, iclass 27, count 2 2006.173.03:22:49.47#ibcon#read 3, iclass 27, count 2 2006.173.03:22:49.47#ibcon#about to read 4, iclass 27, count 2 2006.173.03:22:49.47#ibcon#read 4, iclass 27, count 2 2006.173.03:22:49.47#ibcon#about to read 5, iclass 27, count 2 2006.173.03:22:49.47#ibcon#read 5, iclass 27, count 2 2006.173.03:22:49.47#ibcon#about to read 6, iclass 27, count 2 2006.173.03:22:49.47#ibcon#read 6, iclass 27, count 2 2006.173.03:22:49.47#ibcon#end of sib2, iclass 27, count 2 2006.173.03:22:49.47#ibcon#*mode == 0, iclass 27, count 2 2006.173.03:22:49.47#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.03:22:49.47#ibcon#[27=AT05-04\r\n] 2006.173.03:22:49.47#ibcon#*before write, iclass 27, count 2 2006.173.03:22:49.47#ibcon#enter sib2, iclass 27, count 2 2006.173.03:22:49.47#ibcon#flushed, iclass 27, count 2 2006.173.03:22:49.47#ibcon#about to write, iclass 27, count 2 2006.173.03:22:49.47#ibcon#wrote, iclass 27, count 2 2006.173.03:22:49.48#ibcon#about to read 3, iclass 27, count 2 2006.173.03:22:49.50#ibcon#read 3, iclass 27, count 2 2006.173.03:22:49.50#ibcon#about to read 4, iclass 27, count 2 2006.173.03:22:49.50#ibcon#read 4, iclass 27, count 2 2006.173.03:22:49.50#ibcon#about to read 5, iclass 27, count 2 2006.173.03:22:49.50#ibcon#read 5, iclass 27, count 2 2006.173.03:22:49.50#ibcon#about to read 6, iclass 27, count 2 2006.173.03:22:49.50#ibcon#read 6, iclass 27, count 2 2006.173.03:22:49.50#ibcon#end of sib2, iclass 27, count 2 2006.173.03:22:49.50#ibcon#*after write, iclass 27, count 2 2006.173.03:22:49.50#ibcon#*before return 0, iclass 27, count 2 2006.173.03:22:49.50#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.03:22:49.50#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.03:22:49.50#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.03:22:49.50#ibcon#ireg 7 cls_cnt 0 2006.173.03:22:49.50#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.03:22:49.62#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.03:22:49.62#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.03:22:49.62#ibcon#enter wrdev, iclass 27, count 0 2006.173.03:22:49.62#ibcon#first serial, iclass 27, count 0 2006.173.03:22:49.62#ibcon#enter sib2, iclass 27, count 0 2006.173.03:22:49.62#ibcon#flushed, iclass 27, count 0 2006.173.03:22:49.62#ibcon#about to write, iclass 27, count 0 2006.173.03:22:49.62#ibcon#wrote, iclass 27, count 0 2006.173.03:22:49.62#ibcon#about to read 3, iclass 27, count 0 2006.173.03:22:49.64#ibcon#read 3, iclass 27, count 0 2006.173.03:22:49.64#ibcon#about to read 4, iclass 27, count 0 2006.173.03:22:49.64#ibcon#read 4, iclass 27, count 0 2006.173.03:22:49.64#ibcon#about to read 5, iclass 27, count 0 2006.173.03:22:49.64#ibcon#read 5, iclass 27, count 0 2006.173.03:22:49.64#ibcon#about to read 6, iclass 27, count 0 2006.173.03:22:49.64#ibcon#read 6, iclass 27, count 0 2006.173.03:22:49.64#ibcon#end of sib2, iclass 27, count 0 2006.173.03:22:49.64#ibcon#*mode == 0, iclass 27, count 0 2006.173.03:22:49.64#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.03:22:49.64#ibcon#[27=USB\r\n] 2006.173.03:22:49.64#ibcon#*before write, iclass 27, count 0 2006.173.03:22:49.64#ibcon#enter sib2, iclass 27, count 0 2006.173.03:22:49.64#ibcon#flushed, iclass 27, count 0 2006.173.03:22:49.64#ibcon#about to write, iclass 27, count 0 2006.173.03:22:49.64#ibcon#wrote, iclass 27, count 0 2006.173.03:22:49.65#ibcon#about to read 3, iclass 27, count 0 2006.173.03:22:49.67#ibcon#read 3, iclass 27, count 0 2006.173.03:22:49.67#ibcon#about to read 4, iclass 27, count 0 2006.173.03:22:49.67#ibcon#read 4, iclass 27, count 0 2006.173.03:22:49.67#ibcon#about to read 5, iclass 27, count 0 2006.173.03:22:49.67#ibcon#read 5, iclass 27, count 0 2006.173.03:22:49.67#ibcon#about to read 6, iclass 27, count 0 2006.173.03:22:49.67#ibcon#read 6, iclass 27, count 0 2006.173.03:22:49.67#ibcon#end of sib2, iclass 27, count 0 2006.173.03:22:49.67#ibcon#*after write, iclass 27, count 0 2006.173.03:22:49.67#ibcon#*before return 0, iclass 27, count 0 2006.173.03:22:49.67#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.03:22:49.67#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.03:22:49.67#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.03:22:49.67#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.03:22:49.68$vck44/vblo=6,719.99 2006.173.03:22:49.68#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.03:22:49.68#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.03:22:49.68#ibcon#ireg 17 cls_cnt 0 2006.173.03:22:49.68#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.03:22:49.68#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.03:22:49.68#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.03:22:49.68#ibcon#enter wrdev, iclass 29, count 0 2006.173.03:22:49.68#ibcon#first serial, iclass 29, count 0 2006.173.03:22:49.68#ibcon#enter sib2, iclass 29, count 0 2006.173.03:22:49.68#ibcon#flushed, iclass 29, count 0 2006.173.03:22:49.68#ibcon#about to write, iclass 29, count 0 2006.173.03:22:49.68#ibcon#wrote, iclass 29, count 0 2006.173.03:22:49.68#ibcon#about to read 3, iclass 29, count 0 2006.173.03:22:49.69#ibcon#read 3, iclass 29, count 0 2006.173.03:22:49.69#ibcon#about to read 4, iclass 29, count 0 2006.173.03:22:49.69#ibcon#read 4, iclass 29, count 0 2006.173.03:22:49.69#ibcon#about to read 5, iclass 29, count 0 2006.173.03:22:49.69#ibcon#read 5, iclass 29, count 0 2006.173.03:22:49.69#ibcon#about to read 6, iclass 29, count 0 2006.173.03:22:49.69#ibcon#read 6, iclass 29, count 0 2006.173.03:22:49.69#ibcon#end of sib2, iclass 29, count 0 2006.173.03:22:49.69#ibcon#*mode == 0, iclass 29, count 0 2006.173.03:22:49.69#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.03:22:49.69#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.03:22:49.69#ibcon#*before write, iclass 29, count 0 2006.173.03:22:49.69#ibcon#enter sib2, iclass 29, count 0 2006.173.03:22:49.69#ibcon#flushed, iclass 29, count 0 2006.173.03:22:49.69#ibcon#about to write, iclass 29, count 0 2006.173.03:22:49.69#ibcon#wrote, iclass 29, count 0 2006.173.03:22:49.70#ibcon#about to read 3, iclass 29, count 0 2006.173.03:22:49.73#ibcon#read 3, iclass 29, count 0 2006.173.03:22:49.73#ibcon#about to read 4, iclass 29, count 0 2006.173.03:22:49.73#ibcon#read 4, iclass 29, count 0 2006.173.03:22:49.73#ibcon#about to read 5, iclass 29, count 0 2006.173.03:22:49.73#ibcon#read 5, iclass 29, count 0 2006.173.03:22:49.73#ibcon#about to read 6, iclass 29, count 0 2006.173.03:22:49.73#ibcon#read 6, iclass 29, count 0 2006.173.03:22:49.73#ibcon#end of sib2, iclass 29, count 0 2006.173.03:22:49.73#ibcon#*after write, iclass 29, count 0 2006.173.03:22:49.73#ibcon#*before return 0, iclass 29, count 0 2006.173.03:22:49.73#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.03:22:49.73#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.03:22:49.73#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.03:22:49.73#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.03:22:49.74$vck44/vb=6,4 2006.173.03:22:49.74#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.03:22:49.74#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.03:22:49.74#ibcon#ireg 11 cls_cnt 2 2006.173.03:22:49.74#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.03:22:49.78#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.03:22:49.78#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.03:22:49.78#ibcon#enter wrdev, iclass 31, count 2 2006.173.03:22:49.78#ibcon#first serial, iclass 31, count 2 2006.173.03:22:49.78#ibcon#enter sib2, iclass 31, count 2 2006.173.03:22:49.78#ibcon#flushed, iclass 31, count 2 2006.173.03:22:49.78#ibcon#about to write, iclass 31, count 2 2006.173.03:22:49.78#ibcon#wrote, iclass 31, count 2 2006.173.03:22:49.78#ibcon#about to read 3, iclass 31, count 2 2006.173.03:22:49.80#ibcon#read 3, iclass 31, count 2 2006.173.03:22:49.80#ibcon#about to read 4, iclass 31, count 2 2006.173.03:22:49.80#ibcon#read 4, iclass 31, count 2 2006.173.03:22:49.80#ibcon#about to read 5, iclass 31, count 2 2006.173.03:22:49.80#ibcon#read 5, iclass 31, count 2 2006.173.03:22:49.80#ibcon#about to read 6, iclass 31, count 2 2006.173.03:22:49.80#ibcon#read 6, iclass 31, count 2 2006.173.03:22:49.80#ibcon#end of sib2, iclass 31, count 2 2006.173.03:22:49.80#ibcon#*mode == 0, iclass 31, count 2 2006.173.03:22:49.80#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.03:22:49.80#ibcon#[27=AT06-04\r\n] 2006.173.03:22:49.80#ibcon#*before write, iclass 31, count 2 2006.173.03:22:49.80#ibcon#enter sib2, iclass 31, count 2 2006.173.03:22:49.80#ibcon#flushed, iclass 31, count 2 2006.173.03:22:49.80#ibcon#about to write, iclass 31, count 2 2006.173.03:22:49.80#ibcon#wrote, iclass 31, count 2 2006.173.03:22:49.81#ibcon#about to read 3, iclass 31, count 2 2006.173.03:22:49.83#ibcon#read 3, iclass 31, count 2 2006.173.03:22:49.83#ibcon#about to read 4, iclass 31, count 2 2006.173.03:22:49.83#ibcon#read 4, iclass 31, count 2 2006.173.03:22:49.83#ibcon#about to read 5, iclass 31, count 2 2006.173.03:22:49.83#ibcon#read 5, iclass 31, count 2 2006.173.03:22:49.83#ibcon#about to read 6, iclass 31, count 2 2006.173.03:22:49.83#ibcon#read 6, iclass 31, count 2 2006.173.03:22:49.83#ibcon#end of sib2, iclass 31, count 2 2006.173.03:22:49.83#ibcon#*after write, iclass 31, count 2 2006.173.03:22:49.83#ibcon#*before return 0, iclass 31, count 2 2006.173.03:22:49.83#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.03:22:49.83#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.03:22:49.83#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.03:22:49.83#ibcon#ireg 7 cls_cnt 0 2006.173.03:22:49.83#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.03:22:49.95#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.03:22:49.95#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.03:22:49.95#ibcon#enter wrdev, iclass 31, count 0 2006.173.03:22:49.95#ibcon#first serial, iclass 31, count 0 2006.173.03:22:49.95#ibcon#enter sib2, iclass 31, count 0 2006.173.03:22:49.95#ibcon#flushed, iclass 31, count 0 2006.173.03:22:49.95#ibcon#about to write, iclass 31, count 0 2006.173.03:22:49.95#ibcon#wrote, iclass 31, count 0 2006.173.03:22:49.95#ibcon#about to read 3, iclass 31, count 0 2006.173.03:22:49.97#ibcon#read 3, iclass 31, count 0 2006.173.03:22:49.97#ibcon#about to read 4, iclass 31, count 0 2006.173.03:22:49.97#ibcon#read 4, iclass 31, count 0 2006.173.03:22:49.97#ibcon#about to read 5, iclass 31, count 0 2006.173.03:22:49.97#ibcon#read 5, iclass 31, count 0 2006.173.03:22:49.97#ibcon#about to read 6, iclass 31, count 0 2006.173.03:22:49.97#ibcon#read 6, iclass 31, count 0 2006.173.03:22:49.97#ibcon#end of sib2, iclass 31, count 0 2006.173.03:22:49.97#ibcon#*mode == 0, iclass 31, count 0 2006.173.03:22:49.97#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.03:22:49.97#ibcon#[27=USB\r\n] 2006.173.03:22:49.97#ibcon#*before write, iclass 31, count 0 2006.173.03:22:49.97#ibcon#enter sib2, iclass 31, count 0 2006.173.03:22:49.97#ibcon#flushed, iclass 31, count 0 2006.173.03:22:49.97#ibcon#about to write, iclass 31, count 0 2006.173.03:22:49.97#ibcon#wrote, iclass 31, count 0 2006.173.03:22:49.98#ibcon#about to read 3, iclass 31, count 0 2006.173.03:22:50.00#ibcon#read 3, iclass 31, count 0 2006.173.03:22:50.00#ibcon#about to read 4, iclass 31, count 0 2006.173.03:22:50.00#ibcon#read 4, iclass 31, count 0 2006.173.03:22:50.00#ibcon#about to read 5, iclass 31, count 0 2006.173.03:22:50.00#ibcon#read 5, iclass 31, count 0 2006.173.03:22:50.00#ibcon#about to read 6, iclass 31, count 0 2006.173.03:22:50.00#ibcon#read 6, iclass 31, count 0 2006.173.03:22:50.00#ibcon#end of sib2, iclass 31, count 0 2006.173.03:22:50.00#ibcon#*after write, iclass 31, count 0 2006.173.03:22:50.00#ibcon#*before return 0, iclass 31, count 0 2006.173.03:22:50.00#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.03:22:50.00#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.03:22:50.00#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.03:22:50.00#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.03:22:50.01$vck44/vblo=7,734.99 2006.173.03:22:50.01#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.03:22:50.01#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.03:22:50.01#ibcon#ireg 17 cls_cnt 0 2006.173.03:22:50.01#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.03:22:50.01#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.03:22:50.01#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.03:22:50.01#ibcon#enter wrdev, iclass 33, count 0 2006.173.03:22:50.01#ibcon#first serial, iclass 33, count 0 2006.173.03:22:50.01#ibcon#enter sib2, iclass 33, count 0 2006.173.03:22:50.01#ibcon#flushed, iclass 33, count 0 2006.173.03:22:50.01#ibcon#about to write, iclass 33, count 0 2006.173.03:22:50.01#ibcon#wrote, iclass 33, count 0 2006.173.03:22:50.01#ibcon#about to read 3, iclass 33, count 0 2006.173.03:22:50.02#ibcon#read 3, iclass 33, count 0 2006.173.03:22:50.02#ibcon#about to read 4, iclass 33, count 0 2006.173.03:22:50.02#ibcon#read 4, iclass 33, count 0 2006.173.03:22:50.02#ibcon#about to read 5, iclass 33, count 0 2006.173.03:22:50.02#ibcon#read 5, iclass 33, count 0 2006.173.03:22:50.02#ibcon#about to read 6, iclass 33, count 0 2006.173.03:22:50.02#ibcon#read 6, iclass 33, count 0 2006.173.03:22:50.02#ibcon#end of sib2, iclass 33, count 0 2006.173.03:22:50.02#ibcon#*mode == 0, iclass 33, count 0 2006.173.03:22:50.02#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.03:22:50.02#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.03:22:50.02#ibcon#*before write, iclass 33, count 0 2006.173.03:22:50.02#ibcon#enter sib2, iclass 33, count 0 2006.173.03:22:50.02#ibcon#flushed, iclass 33, count 0 2006.173.03:22:50.02#ibcon#about to write, iclass 33, count 0 2006.173.03:22:50.02#ibcon#wrote, iclass 33, count 0 2006.173.03:22:50.03#ibcon#about to read 3, iclass 33, count 0 2006.173.03:22:50.06#ibcon#read 3, iclass 33, count 0 2006.173.03:22:50.06#ibcon#about to read 4, iclass 33, count 0 2006.173.03:22:50.06#ibcon#read 4, iclass 33, count 0 2006.173.03:22:50.06#ibcon#about to read 5, iclass 33, count 0 2006.173.03:22:50.06#ibcon#read 5, iclass 33, count 0 2006.173.03:22:50.06#ibcon#about to read 6, iclass 33, count 0 2006.173.03:22:50.06#ibcon#read 6, iclass 33, count 0 2006.173.03:22:50.06#ibcon#end of sib2, iclass 33, count 0 2006.173.03:22:50.06#ibcon#*after write, iclass 33, count 0 2006.173.03:22:50.06#ibcon#*before return 0, iclass 33, count 0 2006.173.03:22:50.06#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.03:22:50.06#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.03:22:50.06#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.03:22:50.06#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.03:22:50.07$vck44/vb=7,4 2006.173.03:22:50.07#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.03:22:50.07#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.03:22:50.07#ibcon#ireg 11 cls_cnt 2 2006.173.03:22:50.07#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.03:22:50.11#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.03:22:50.11#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.03:22:50.11#ibcon#enter wrdev, iclass 35, count 2 2006.173.03:22:50.11#ibcon#first serial, iclass 35, count 2 2006.173.03:22:50.11#ibcon#enter sib2, iclass 35, count 2 2006.173.03:22:50.11#ibcon#flushed, iclass 35, count 2 2006.173.03:22:50.11#ibcon#about to write, iclass 35, count 2 2006.173.03:22:50.11#ibcon#wrote, iclass 35, count 2 2006.173.03:22:50.11#ibcon#about to read 3, iclass 35, count 2 2006.173.03:22:50.13#ibcon#read 3, iclass 35, count 2 2006.173.03:22:50.13#ibcon#about to read 4, iclass 35, count 2 2006.173.03:22:50.13#ibcon#read 4, iclass 35, count 2 2006.173.03:22:50.13#ibcon#about to read 5, iclass 35, count 2 2006.173.03:22:50.13#ibcon#read 5, iclass 35, count 2 2006.173.03:22:50.13#ibcon#about to read 6, iclass 35, count 2 2006.173.03:22:50.13#ibcon#read 6, iclass 35, count 2 2006.173.03:22:50.13#ibcon#end of sib2, iclass 35, count 2 2006.173.03:22:50.13#ibcon#*mode == 0, iclass 35, count 2 2006.173.03:22:50.13#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.03:22:50.13#ibcon#[27=AT07-04\r\n] 2006.173.03:22:50.13#ibcon#*before write, iclass 35, count 2 2006.173.03:22:50.13#ibcon#enter sib2, iclass 35, count 2 2006.173.03:22:50.13#ibcon#flushed, iclass 35, count 2 2006.173.03:22:50.13#ibcon#about to write, iclass 35, count 2 2006.173.03:22:50.13#ibcon#wrote, iclass 35, count 2 2006.173.03:22:50.14#ibcon#about to read 3, iclass 35, count 2 2006.173.03:22:50.16#ibcon#read 3, iclass 35, count 2 2006.173.03:22:50.16#ibcon#about to read 4, iclass 35, count 2 2006.173.03:22:50.16#ibcon#read 4, iclass 35, count 2 2006.173.03:22:50.16#ibcon#about to read 5, iclass 35, count 2 2006.173.03:22:50.16#ibcon#read 5, iclass 35, count 2 2006.173.03:22:50.16#ibcon#about to read 6, iclass 35, count 2 2006.173.03:22:50.16#ibcon#read 6, iclass 35, count 2 2006.173.03:22:50.16#ibcon#end of sib2, iclass 35, count 2 2006.173.03:22:50.16#ibcon#*after write, iclass 35, count 2 2006.173.03:22:50.16#ibcon#*before return 0, iclass 35, count 2 2006.173.03:22:50.16#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.03:22:50.16#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.03:22:50.16#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.03:22:50.16#ibcon#ireg 7 cls_cnt 0 2006.173.03:22:50.16#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.03:22:50.28#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.03:22:50.28#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.03:22:50.28#ibcon#enter wrdev, iclass 35, count 0 2006.173.03:22:50.28#ibcon#first serial, iclass 35, count 0 2006.173.03:22:50.28#ibcon#enter sib2, iclass 35, count 0 2006.173.03:22:50.28#ibcon#flushed, iclass 35, count 0 2006.173.03:22:50.28#ibcon#about to write, iclass 35, count 0 2006.173.03:22:50.28#ibcon#wrote, iclass 35, count 0 2006.173.03:22:50.28#ibcon#about to read 3, iclass 35, count 0 2006.173.03:22:50.30#ibcon#read 3, iclass 35, count 0 2006.173.03:22:50.30#ibcon#about to read 4, iclass 35, count 0 2006.173.03:22:50.30#ibcon#read 4, iclass 35, count 0 2006.173.03:22:50.30#ibcon#about to read 5, iclass 35, count 0 2006.173.03:22:50.30#ibcon#read 5, iclass 35, count 0 2006.173.03:22:50.30#ibcon#about to read 6, iclass 35, count 0 2006.173.03:22:50.30#ibcon#read 6, iclass 35, count 0 2006.173.03:22:50.30#ibcon#end of sib2, iclass 35, count 0 2006.173.03:22:50.30#ibcon#*mode == 0, iclass 35, count 0 2006.173.03:22:50.30#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.03:22:50.30#ibcon#[27=USB\r\n] 2006.173.03:22:50.30#ibcon#*before write, iclass 35, count 0 2006.173.03:22:50.30#ibcon#enter sib2, iclass 35, count 0 2006.173.03:22:50.30#ibcon#flushed, iclass 35, count 0 2006.173.03:22:50.30#ibcon#about to write, iclass 35, count 0 2006.173.03:22:50.30#ibcon#wrote, iclass 35, count 0 2006.173.03:22:50.31#ibcon#about to read 3, iclass 35, count 0 2006.173.03:22:50.33#ibcon#read 3, iclass 35, count 0 2006.173.03:22:50.33#ibcon#about to read 4, iclass 35, count 0 2006.173.03:22:50.33#ibcon#read 4, iclass 35, count 0 2006.173.03:22:50.33#ibcon#about to read 5, iclass 35, count 0 2006.173.03:22:50.33#ibcon#read 5, iclass 35, count 0 2006.173.03:22:50.33#ibcon#about to read 6, iclass 35, count 0 2006.173.03:22:50.33#ibcon#read 6, iclass 35, count 0 2006.173.03:22:50.33#ibcon#end of sib2, iclass 35, count 0 2006.173.03:22:50.33#ibcon#*after write, iclass 35, count 0 2006.173.03:22:50.33#ibcon#*before return 0, iclass 35, count 0 2006.173.03:22:50.33#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.03:22:50.33#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.03:22:50.33#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.03:22:50.33#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.03:22:50.34$vck44/vblo=8,744.99 2006.173.03:22:50.34#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.03:22:50.34#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.03:22:50.34#ibcon#ireg 17 cls_cnt 0 2006.173.03:22:50.34#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.03:22:50.34#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.03:22:50.34#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.03:22:50.34#ibcon#enter wrdev, iclass 37, count 0 2006.173.03:22:50.34#ibcon#first serial, iclass 37, count 0 2006.173.03:22:50.34#ibcon#enter sib2, iclass 37, count 0 2006.173.03:22:50.34#ibcon#flushed, iclass 37, count 0 2006.173.03:22:50.34#ibcon#about to write, iclass 37, count 0 2006.173.03:22:50.34#ibcon#wrote, iclass 37, count 0 2006.173.03:22:50.34#ibcon#about to read 3, iclass 37, count 0 2006.173.03:22:50.35#ibcon#read 3, iclass 37, count 0 2006.173.03:22:50.35#ibcon#about to read 4, iclass 37, count 0 2006.173.03:22:50.35#ibcon#read 4, iclass 37, count 0 2006.173.03:22:50.35#ibcon#about to read 5, iclass 37, count 0 2006.173.03:22:50.35#ibcon#read 5, iclass 37, count 0 2006.173.03:22:50.35#ibcon#about to read 6, iclass 37, count 0 2006.173.03:22:50.35#ibcon#read 6, iclass 37, count 0 2006.173.03:22:50.35#ibcon#end of sib2, iclass 37, count 0 2006.173.03:22:50.35#ibcon#*mode == 0, iclass 37, count 0 2006.173.03:22:50.35#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.03:22:50.35#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.03:22:50.35#ibcon#*before write, iclass 37, count 0 2006.173.03:22:50.35#ibcon#enter sib2, iclass 37, count 0 2006.173.03:22:50.35#ibcon#flushed, iclass 37, count 0 2006.173.03:22:50.35#ibcon#about to write, iclass 37, count 0 2006.173.03:22:50.35#ibcon#wrote, iclass 37, count 0 2006.173.03:22:50.36#ibcon#about to read 3, iclass 37, count 0 2006.173.03:22:50.39#ibcon#read 3, iclass 37, count 0 2006.173.03:22:50.39#ibcon#about to read 4, iclass 37, count 0 2006.173.03:22:50.39#ibcon#read 4, iclass 37, count 0 2006.173.03:22:50.39#ibcon#about to read 5, iclass 37, count 0 2006.173.03:22:50.39#ibcon#read 5, iclass 37, count 0 2006.173.03:22:50.39#ibcon#about to read 6, iclass 37, count 0 2006.173.03:22:50.39#ibcon#read 6, iclass 37, count 0 2006.173.03:22:50.39#ibcon#end of sib2, iclass 37, count 0 2006.173.03:22:50.39#ibcon#*after write, iclass 37, count 0 2006.173.03:22:50.39#ibcon#*before return 0, iclass 37, count 0 2006.173.03:22:50.39#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.03:22:50.39#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.03:22:50.39#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.03:22:50.39#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.03:22:50.40$vck44/vb=8,4 2006.173.03:22:50.40#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.03:22:50.40#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.03:22:50.40#ibcon#ireg 11 cls_cnt 2 2006.173.03:22:50.40#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.03:22:50.44#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.03:22:50.44#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.03:22:50.44#ibcon#enter wrdev, iclass 39, count 2 2006.173.03:22:50.44#ibcon#first serial, iclass 39, count 2 2006.173.03:22:50.44#ibcon#enter sib2, iclass 39, count 2 2006.173.03:22:50.44#ibcon#flushed, iclass 39, count 2 2006.173.03:22:50.44#ibcon#about to write, iclass 39, count 2 2006.173.03:22:50.44#ibcon#wrote, iclass 39, count 2 2006.173.03:22:50.44#ibcon#about to read 3, iclass 39, count 2 2006.173.03:22:50.46#ibcon#read 3, iclass 39, count 2 2006.173.03:22:50.46#ibcon#about to read 4, iclass 39, count 2 2006.173.03:22:50.46#ibcon#read 4, iclass 39, count 2 2006.173.03:22:50.46#ibcon#about to read 5, iclass 39, count 2 2006.173.03:22:50.46#ibcon#read 5, iclass 39, count 2 2006.173.03:22:50.46#ibcon#about to read 6, iclass 39, count 2 2006.173.03:22:50.46#ibcon#read 6, iclass 39, count 2 2006.173.03:22:50.46#ibcon#end of sib2, iclass 39, count 2 2006.173.03:22:50.46#ibcon#*mode == 0, iclass 39, count 2 2006.173.03:22:50.46#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.03:22:50.46#ibcon#[27=AT08-04\r\n] 2006.173.03:22:50.46#ibcon#*before write, iclass 39, count 2 2006.173.03:22:50.46#ibcon#enter sib2, iclass 39, count 2 2006.173.03:22:50.46#ibcon#flushed, iclass 39, count 2 2006.173.03:22:50.46#ibcon#about to write, iclass 39, count 2 2006.173.03:22:50.46#ibcon#wrote, iclass 39, count 2 2006.173.03:22:50.46#ibcon#about to read 3, iclass 39, count 2 2006.173.03:22:50.49#ibcon#read 3, iclass 39, count 2 2006.173.03:22:50.49#ibcon#about to read 4, iclass 39, count 2 2006.173.03:22:50.49#ibcon#read 4, iclass 39, count 2 2006.173.03:22:50.49#ibcon#about to read 5, iclass 39, count 2 2006.173.03:22:50.49#ibcon#read 5, iclass 39, count 2 2006.173.03:22:50.49#ibcon#about to read 6, iclass 39, count 2 2006.173.03:22:50.49#ibcon#read 6, iclass 39, count 2 2006.173.03:22:50.49#ibcon#end of sib2, iclass 39, count 2 2006.173.03:22:50.49#ibcon#*after write, iclass 39, count 2 2006.173.03:22:50.49#ibcon#*before return 0, iclass 39, count 2 2006.173.03:22:50.49#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.03:22:50.49#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.03:22:50.49#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.03:22:50.49#ibcon#ireg 7 cls_cnt 0 2006.173.03:22:50.49#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.03:22:50.61#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.03:22:50.61#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.03:22:50.61#ibcon#enter wrdev, iclass 39, count 0 2006.173.03:22:50.61#ibcon#first serial, iclass 39, count 0 2006.173.03:22:50.61#ibcon#enter sib2, iclass 39, count 0 2006.173.03:22:50.61#ibcon#flushed, iclass 39, count 0 2006.173.03:22:50.61#ibcon#about to write, iclass 39, count 0 2006.173.03:22:50.61#ibcon#wrote, iclass 39, count 0 2006.173.03:22:50.61#ibcon#about to read 3, iclass 39, count 0 2006.173.03:22:50.63#ibcon#read 3, iclass 39, count 0 2006.173.03:22:50.63#ibcon#about to read 4, iclass 39, count 0 2006.173.03:22:50.63#ibcon#read 4, iclass 39, count 0 2006.173.03:22:50.63#ibcon#about to read 5, iclass 39, count 0 2006.173.03:22:50.63#ibcon#read 5, iclass 39, count 0 2006.173.03:22:50.63#ibcon#about to read 6, iclass 39, count 0 2006.173.03:22:50.63#ibcon#read 6, iclass 39, count 0 2006.173.03:22:50.63#ibcon#end of sib2, iclass 39, count 0 2006.173.03:22:50.63#ibcon#*mode == 0, iclass 39, count 0 2006.173.03:22:50.63#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.03:22:50.63#ibcon#[27=USB\r\n] 2006.173.03:22:50.63#ibcon#*before write, iclass 39, count 0 2006.173.03:22:50.63#ibcon#enter sib2, iclass 39, count 0 2006.173.03:22:50.63#ibcon#flushed, iclass 39, count 0 2006.173.03:22:50.63#ibcon#about to write, iclass 39, count 0 2006.173.03:22:50.63#ibcon#wrote, iclass 39, count 0 2006.173.03:22:50.63#ibcon#about to read 3, iclass 39, count 0 2006.173.03:22:50.66#ibcon#read 3, iclass 39, count 0 2006.173.03:22:50.66#ibcon#about to read 4, iclass 39, count 0 2006.173.03:22:50.66#ibcon#read 4, iclass 39, count 0 2006.173.03:22:50.66#ibcon#about to read 5, iclass 39, count 0 2006.173.03:22:50.66#ibcon#read 5, iclass 39, count 0 2006.173.03:22:50.66#ibcon#about to read 6, iclass 39, count 0 2006.173.03:22:50.66#ibcon#read 6, iclass 39, count 0 2006.173.03:22:50.66#ibcon#end of sib2, iclass 39, count 0 2006.173.03:22:50.66#ibcon#*after write, iclass 39, count 0 2006.173.03:22:50.66#ibcon#*before return 0, iclass 39, count 0 2006.173.03:22:50.66#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.03:22:50.66#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.03:22:50.66#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.03:22:50.66#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.03:22:50.67$vck44/vabw=wide 2006.173.03:22:50.67#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.03:22:50.67#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.03:22:50.67#ibcon#ireg 8 cls_cnt 0 2006.173.03:22:50.67#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.03:22:50.67#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.03:22:50.67#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.03:22:50.67#ibcon#enter wrdev, iclass 3, count 0 2006.173.03:22:50.67#ibcon#first serial, iclass 3, count 0 2006.173.03:22:50.67#ibcon#enter sib2, iclass 3, count 0 2006.173.03:22:50.67#ibcon#flushed, iclass 3, count 0 2006.173.03:22:50.67#ibcon#about to write, iclass 3, count 0 2006.173.03:22:50.67#ibcon#wrote, iclass 3, count 0 2006.173.03:22:50.67#ibcon#about to read 3, iclass 3, count 0 2006.173.03:22:50.68#ibcon#read 3, iclass 3, count 0 2006.173.03:22:50.68#ibcon#about to read 4, iclass 3, count 0 2006.173.03:22:50.68#ibcon#read 4, iclass 3, count 0 2006.173.03:22:50.68#ibcon#about to read 5, iclass 3, count 0 2006.173.03:22:50.68#ibcon#read 5, iclass 3, count 0 2006.173.03:22:50.68#ibcon#about to read 6, iclass 3, count 0 2006.173.03:22:50.68#ibcon#read 6, iclass 3, count 0 2006.173.03:22:50.68#ibcon#end of sib2, iclass 3, count 0 2006.173.03:22:50.68#ibcon#*mode == 0, iclass 3, count 0 2006.173.03:22:50.68#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.03:22:50.68#ibcon#[25=BW32\r\n] 2006.173.03:22:50.68#ibcon#*before write, iclass 3, count 0 2006.173.03:22:50.68#ibcon#enter sib2, iclass 3, count 0 2006.173.03:22:50.68#ibcon#flushed, iclass 3, count 0 2006.173.03:22:50.68#ibcon#about to write, iclass 3, count 0 2006.173.03:22:50.68#ibcon#wrote, iclass 3, count 0 2006.173.03:22:50.69#ibcon#about to read 3, iclass 3, count 0 2006.173.03:22:50.71#ibcon#read 3, iclass 3, count 0 2006.173.03:22:50.71#ibcon#about to read 4, iclass 3, count 0 2006.173.03:22:50.71#ibcon#read 4, iclass 3, count 0 2006.173.03:22:50.71#ibcon#about to read 5, iclass 3, count 0 2006.173.03:22:50.71#ibcon#read 5, iclass 3, count 0 2006.173.03:22:50.71#ibcon#about to read 6, iclass 3, count 0 2006.173.03:22:50.71#ibcon#read 6, iclass 3, count 0 2006.173.03:22:50.71#ibcon#end of sib2, iclass 3, count 0 2006.173.03:22:50.71#ibcon#*after write, iclass 3, count 0 2006.173.03:22:50.71#ibcon#*before return 0, iclass 3, count 0 2006.173.03:22:50.71#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.03:22:50.71#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.03:22:50.71#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.03:22:50.71#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.03:22:50.72$vck44/vbbw=wide 2006.173.03:22:50.72#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.03:22:50.72#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.03:22:50.72#ibcon#ireg 8 cls_cnt 0 2006.173.03:22:50.72#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.03:22:50.77#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.03:22:50.77#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.03:22:50.77#ibcon#enter wrdev, iclass 5, count 0 2006.173.03:22:50.77#ibcon#first serial, iclass 5, count 0 2006.173.03:22:50.77#ibcon#enter sib2, iclass 5, count 0 2006.173.03:22:50.77#ibcon#flushed, iclass 5, count 0 2006.173.03:22:50.77#ibcon#about to write, iclass 5, count 0 2006.173.03:22:50.77#ibcon#wrote, iclass 5, count 0 2006.173.03:22:50.77#ibcon#about to read 3, iclass 5, count 0 2006.173.03:22:50.79#ibcon#read 3, iclass 5, count 0 2006.173.03:22:50.79#ibcon#about to read 4, iclass 5, count 0 2006.173.03:22:50.79#ibcon#read 4, iclass 5, count 0 2006.173.03:22:50.79#ibcon#about to read 5, iclass 5, count 0 2006.173.03:22:50.79#ibcon#read 5, iclass 5, count 0 2006.173.03:22:50.79#ibcon#about to read 6, iclass 5, count 0 2006.173.03:22:50.79#ibcon#read 6, iclass 5, count 0 2006.173.03:22:50.79#ibcon#end of sib2, iclass 5, count 0 2006.173.03:22:50.79#ibcon#*mode == 0, iclass 5, count 0 2006.173.03:22:50.79#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.03:22:50.79#ibcon#[27=BW32\r\n] 2006.173.03:22:50.79#ibcon#*before write, iclass 5, count 0 2006.173.03:22:50.79#ibcon#enter sib2, iclass 5, count 0 2006.173.03:22:50.79#ibcon#flushed, iclass 5, count 0 2006.173.03:22:50.79#ibcon#about to write, iclass 5, count 0 2006.173.03:22:50.79#ibcon#wrote, iclass 5, count 0 2006.173.03:22:50.79#ibcon#about to read 3, iclass 5, count 0 2006.173.03:22:50.82#ibcon#read 3, iclass 5, count 0 2006.173.03:22:50.82#ibcon#about to read 4, iclass 5, count 0 2006.173.03:22:50.82#ibcon#read 4, iclass 5, count 0 2006.173.03:22:50.82#ibcon#about to read 5, iclass 5, count 0 2006.173.03:22:50.82#ibcon#read 5, iclass 5, count 0 2006.173.03:22:50.82#ibcon#about to read 6, iclass 5, count 0 2006.173.03:22:50.82#ibcon#read 6, iclass 5, count 0 2006.173.03:22:50.82#ibcon#end of sib2, iclass 5, count 0 2006.173.03:22:50.82#ibcon#*after write, iclass 5, count 0 2006.173.03:22:50.82#ibcon#*before return 0, iclass 5, count 0 2006.173.03:22:50.82#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.03:22:50.82#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.03:22:50.82#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.03:22:50.82#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.03:22:50.83$setupk4/ifdk4 2006.173.03:22:50.83$ifdk4/lo= 2006.173.03:22:50.83$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.03:22:50.83$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.03:22:50.83$ifdk4/patch= 2006.173.03:22:50.83$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.03:22:50.83$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.03:22:50.83$setupk4/!*+20s 2006.173.03:22:51.30#abcon#<5=/14 1.2 2.5 22.44 851006.3\r\n> 2006.173.03:22:51.32#abcon#{5=INTERFACE CLEAR} 2006.173.03:22:51.38#abcon#[5=S1D000X0/0*\r\n] 2006.173.03:23:01.47#abcon#<5=/14 1.2 2.5 22.44 851006.3\r\n> 2006.173.03:23:01.49#abcon#{5=INTERFACE CLEAR} 2006.173.03:23:01.55#abcon#[5=S1D000X0/0*\r\n] 2006.173.03:23:03.14#trakl#Source acquired 2006.173.03:23:05.15#flagr#flagr/antenna,acquired 2006.173.03:23:05.49$setupk4/"tpicd 2006.173.03:23:05.49$setupk4/echo=off 2006.173.03:23:05.49$setupk4/xlog=off 2006.173.03:23:05.50:!2006.173.03:25:51 2006.173.03:25:51.01:preob 2006.173.03:25:52.14/onsource/TRACKING 2006.173.03:25:52.14:!2006.173.03:26:01 2006.173.03:26:01.00:"tape 2006.173.03:26:01.00:"st=record 2006.173.03:26:01.00:data_valid=on 2006.173.03:26:01.00:midob 2006.173.03:26:01.14/onsource/TRACKING 2006.173.03:26:01.14/wx/22.53,1006.3,84 2006.173.03:26:01.24/cable/+6.5107E-03 2006.173.03:26:02.33/va/01,07,usb,yes,35,38 2006.173.03:26:02.33/va/02,06,usb,yes,35,36 2006.173.03:26:02.33/va/03,05,usb,yes,45,47 2006.173.03:26:02.33/va/04,06,usb,yes,36,38 2006.173.03:26:02.33/va/05,04,usb,yes,28,29 2006.173.03:26:02.33/va/06,03,usb,yes,40,39 2006.173.03:26:02.33/va/07,04,usb,yes,32,33 2006.173.03:26:02.33/va/08,04,usb,yes,27,33 2006.173.03:26:02.56/valo/01,524.99,yes,locked 2006.173.03:26:02.56/valo/02,534.99,yes,locked 2006.173.03:26:02.56/valo/03,564.99,yes,locked 2006.173.03:26:02.56/valo/04,624.99,yes,locked 2006.173.03:26:02.56/valo/05,734.99,yes,locked 2006.173.03:26:02.56/valo/06,814.99,yes,locked 2006.173.03:26:02.56/valo/07,864.99,yes,locked 2006.173.03:26:02.56/valo/08,884.99,yes,locked 2006.173.03:26:03.65/vb/01,04,usb,yes,29,27 2006.173.03:26:03.65/vb/02,04,usb,yes,31,31 2006.173.03:26:03.65/vb/03,04,usb,yes,28,31 2006.173.03:26:03.65/vb/04,04,usb,yes,32,31 2006.173.03:26:03.65/vb/05,04,usb,yes,25,28 2006.173.03:26:03.65/vb/06,04,usb,yes,29,26 2006.173.03:26:03.65/vb/07,04,usb,yes,29,29 2006.173.03:26:03.65/vb/08,04,usb,yes,27,30 2006.173.03:26:03.89/vblo/01,629.99,yes,locked 2006.173.03:26:03.89/vblo/02,634.99,yes,locked 2006.173.03:26:03.89/vblo/03,649.99,yes,locked 2006.173.03:26:03.89/vblo/04,679.99,yes,locked 2006.173.03:26:03.89/vblo/05,709.99,yes,locked 2006.173.03:26:03.89/vblo/06,719.99,yes,locked 2006.173.03:26:03.89/vblo/07,734.99,yes,locked 2006.173.03:26:03.89/vblo/08,744.99,yes,locked 2006.173.03:26:04.04/vabw/8 2006.173.03:26:04.19/vbbw/8 2006.173.03:26:04.28/xfe/off,on,15.0 2006.173.03:26:04.65/ifatt/23,28,28,28 2006.173.03:26:05.07/fmout-gps/S +3.94E-07 2006.173.03:26:05.12:!2006.173.03:27:01 2006.173.03:27:01.01:data_valid=off 2006.173.03:27:01.01:"et 2006.173.03:27:01.02:!+3s 2006.173.03:27:04.04:"tape 2006.173.03:27:04.04:postob 2006.173.03:27:04.28/cable/+6.5098E-03 2006.173.03:27:04.28/wx/22.56,1006.3,84 2006.173.03:27:04.34/fmout-gps/S +3.94E-07 2006.173.03:27:04.34:scan_name=173-0329,jd0606,50 2006.173.03:27:04.34:source=0552+398,055530.81,394849.2,2000.0,cw 2006.173.03:27:06.14#flagr#flagr/antenna,new-source 2006.173.03:27:06.14:checkk5 2006.173.03:27:06.49/chk_autoobs//k5ts1/ autoobs is running! 2006.173.03:27:06.84/chk_autoobs//k5ts2/ autoobs is running! 2006.173.03:27:07.18/chk_autoobs//k5ts3/ autoobs is running! 2006.173.03:27:07.53/chk_autoobs//k5ts4/ autoobs is running! 2006.173.03:27:07.86/chk_obsdata//k5ts1/T1730326??a.dat file size is correct (nominal:240MB, actual:236MB). 2006.173.03:27:08.19/chk_obsdata//k5ts2/T1730326??b.dat file size is correct (nominal:240MB, actual:236MB). 2006.173.03:27:08.52/chk_obsdata//k5ts3/T1730326??c.dat file size is correct (nominal:240MB, actual:236MB). 2006.173.03:27:08.86/chk_obsdata//k5ts4/T1730326??d.dat file size is correct (nominal:240MB, actual:236MB). 2006.173.03:27:09.52/k5log//k5ts1_log_newline 2006.173.03:27:10.17/k5log//k5ts2_log_newline 2006.173.03:27:10.82/k5log//k5ts3_log_newline 2006.173.03:27:11.48/k5log//k5ts4_log_newline 2006.173.03:27:11.51/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.03:27:11.51:setupk4=1 2006.173.03:27:11.51$setupk4/echo=on 2006.173.03:27:11.51$setupk4/pcalon 2006.173.03:27:11.51$pcalon/"no phase cal control is implemented here 2006.173.03:27:11.51$setupk4/"tpicd=stop 2006.173.03:27:11.51$setupk4/"rec=synch_on 2006.173.03:27:11.51$setupk4/"rec_mode=128 2006.173.03:27:11.51$setupk4/!* 2006.173.03:27:11.51$setupk4/recpk4 2006.173.03:27:11.51$recpk4/recpatch= 2006.173.03:27:11.51$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.03:27:11.51$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.03:27:11.51$setupk4/vck44 2006.173.03:27:11.51$vck44/valo=1,524.99 2006.173.03:27:11.51#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.03:27:11.51#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.03:27:11.51#ibcon#ireg 17 cls_cnt 0 2006.173.03:27:11.51#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.03:27:11.51#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.03:27:11.51#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.03:27:11.51#ibcon#enter wrdev, iclass 6, count 0 2006.173.03:27:11.51#ibcon#first serial, iclass 6, count 0 2006.173.03:27:11.51#ibcon#enter sib2, iclass 6, count 0 2006.173.03:27:11.51#ibcon#flushed, iclass 6, count 0 2006.173.03:27:11.51#ibcon#about to write, iclass 6, count 0 2006.173.03:27:11.51#ibcon#wrote, iclass 6, count 0 2006.173.03:27:11.51#ibcon#about to read 3, iclass 6, count 0 2006.173.03:27:11.52#ibcon#read 3, iclass 6, count 0 2006.173.03:27:11.52#ibcon#about to read 4, iclass 6, count 0 2006.173.03:27:11.52#ibcon#read 4, iclass 6, count 0 2006.173.03:27:11.52#ibcon#about to read 5, iclass 6, count 0 2006.173.03:27:11.52#ibcon#read 5, iclass 6, count 0 2006.173.03:27:11.52#ibcon#about to read 6, iclass 6, count 0 2006.173.03:27:11.52#ibcon#read 6, iclass 6, count 0 2006.173.03:27:11.52#ibcon#end of sib2, iclass 6, count 0 2006.173.03:27:11.52#ibcon#*mode == 0, iclass 6, count 0 2006.173.03:27:11.52#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.03:27:11.52#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.03:27:11.52#ibcon#*before write, iclass 6, count 0 2006.173.03:27:11.52#ibcon#enter sib2, iclass 6, count 0 2006.173.03:27:11.52#ibcon#flushed, iclass 6, count 0 2006.173.03:27:11.52#ibcon#about to write, iclass 6, count 0 2006.173.03:27:11.52#ibcon#wrote, iclass 6, count 0 2006.173.03:27:11.52#ibcon#about to read 3, iclass 6, count 0 2006.173.03:27:11.57#ibcon#read 3, iclass 6, count 0 2006.173.03:27:11.57#ibcon#about to read 4, iclass 6, count 0 2006.173.03:27:11.57#ibcon#read 4, iclass 6, count 0 2006.173.03:27:11.57#ibcon#about to read 5, iclass 6, count 0 2006.173.03:27:11.57#ibcon#read 5, iclass 6, count 0 2006.173.03:27:11.57#ibcon#about to read 6, iclass 6, count 0 2006.173.03:27:11.57#ibcon#read 6, iclass 6, count 0 2006.173.03:27:11.57#ibcon#end of sib2, iclass 6, count 0 2006.173.03:27:11.57#ibcon#*after write, iclass 6, count 0 2006.173.03:27:11.57#ibcon#*before return 0, iclass 6, count 0 2006.173.03:27:11.57#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.03:27:11.57#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.03:27:11.57#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.03:27:11.57#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.03:27:11.57$vck44/va=1,7 2006.173.03:27:11.57#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.03:27:11.57#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.03:27:11.57#ibcon#ireg 11 cls_cnt 2 2006.173.03:27:11.57#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.03:27:11.57#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.03:27:11.57#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.03:27:11.57#ibcon#enter wrdev, iclass 10, count 2 2006.173.03:27:11.57#ibcon#first serial, iclass 10, count 2 2006.173.03:27:11.57#ibcon#enter sib2, iclass 10, count 2 2006.173.03:27:11.57#ibcon#flushed, iclass 10, count 2 2006.173.03:27:11.57#ibcon#about to write, iclass 10, count 2 2006.173.03:27:11.57#ibcon#wrote, iclass 10, count 2 2006.173.03:27:11.57#ibcon#about to read 3, iclass 10, count 2 2006.173.03:27:11.59#ibcon#read 3, iclass 10, count 2 2006.173.03:27:11.59#ibcon#about to read 4, iclass 10, count 2 2006.173.03:27:11.59#ibcon#read 4, iclass 10, count 2 2006.173.03:27:11.59#ibcon#about to read 5, iclass 10, count 2 2006.173.03:27:11.59#ibcon#read 5, iclass 10, count 2 2006.173.03:27:11.59#ibcon#about to read 6, iclass 10, count 2 2006.173.03:27:11.59#ibcon#read 6, iclass 10, count 2 2006.173.03:27:11.59#ibcon#end of sib2, iclass 10, count 2 2006.173.03:27:11.59#ibcon#*mode == 0, iclass 10, count 2 2006.173.03:27:11.59#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.03:27:11.59#ibcon#[25=AT01-07\r\n] 2006.173.03:27:11.59#ibcon#*before write, iclass 10, count 2 2006.173.03:27:11.59#ibcon#enter sib2, iclass 10, count 2 2006.173.03:27:11.59#ibcon#flushed, iclass 10, count 2 2006.173.03:27:11.59#ibcon#about to write, iclass 10, count 2 2006.173.03:27:11.59#ibcon#wrote, iclass 10, count 2 2006.173.03:27:11.59#ibcon#about to read 3, iclass 10, count 2 2006.173.03:27:11.62#ibcon#read 3, iclass 10, count 2 2006.173.03:27:11.62#ibcon#about to read 4, iclass 10, count 2 2006.173.03:27:11.62#ibcon#read 4, iclass 10, count 2 2006.173.03:27:11.62#ibcon#about to read 5, iclass 10, count 2 2006.173.03:27:11.62#ibcon#read 5, iclass 10, count 2 2006.173.03:27:11.62#ibcon#about to read 6, iclass 10, count 2 2006.173.03:27:11.62#ibcon#read 6, iclass 10, count 2 2006.173.03:27:11.62#ibcon#end of sib2, iclass 10, count 2 2006.173.03:27:11.62#ibcon#*after write, iclass 10, count 2 2006.173.03:27:11.62#ibcon#*before return 0, iclass 10, count 2 2006.173.03:27:11.62#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.03:27:11.62#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.03:27:11.62#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.03:27:11.62#ibcon#ireg 7 cls_cnt 0 2006.173.03:27:11.62#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.03:27:11.74#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.03:27:11.74#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.03:27:11.74#ibcon#enter wrdev, iclass 10, count 0 2006.173.03:27:11.74#ibcon#first serial, iclass 10, count 0 2006.173.03:27:11.74#ibcon#enter sib2, iclass 10, count 0 2006.173.03:27:11.74#ibcon#flushed, iclass 10, count 0 2006.173.03:27:11.74#ibcon#about to write, iclass 10, count 0 2006.173.03:27:11.74#ibcon#wrote, iclass 10, count 0 2006.173.03:27:11.74#ibcon#about to read 3, iclass 10, count 0 2006.173.03:27:11.76#ibcon#read 3, iclass 10, count 0 2006.173.03:27:11.76#ibcon#about to read 4, iclass 10, count 0 2006.173.03:27:11.76#ibcon#read 4, iclass 10, count 0 2006.173.03:27:11.76#ibcon#about to read 5, iclass 10, count 0 2006.173.03:27:11.76#ibcon#read 5, iclass 10, count 0 2006.173.03:27:11.76#ibcon#about to read 6, iclass 10, count 0 2006.173.03:27:11.76#ibcon#read 6, iclass 10, count 0 2006.173.03:27:11.76#ibcon#end of sib2, iclass 10, count 0 2006.173.03:27:11.76#ibcon#*mode == 0, iclass 10, count 0 2006.173.03:27:11.76#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.03:27:11.76#ibcon#[25=USB\r\n] 2006.173.03:27:11.76#ibcon#*before write, iclass 10, count 0 2006.173.03:27:11.76#ibcon#enter sib2, iclass 10, count 0 2006.173.03:27:11.76#ibcon#flushed, iclass 10, count 0 2006.173.03:27:11.76#ibcon#about to write, iclass 10, count 0 2006.173.03:27:11.76#ibcon#wrote, iclass 10, count 0 2006.173.03:27:11.76#ibcon#about to read 3, iclass 10, count 0 2006.173.03:27:11.79#ibcon#read 3, iclass 10, count 0 2006.173.03:27:11.79#ibcon#about to read 4, iclass 10, count 0 2006.173.03:27:11.79#ibcon#read 4, iclass 10, count 0 2006.173.03:27:11.79#ibcon#about to read 5, iclass 10, count 0 2006.173.03:27:11.79#ibcon#read 5, iclass 10, count 0 2006.173.03:27:11.79#ibcon#about to read 6, iclass 10, count 0 2006.173.03:27:11.79#ibcon#read 6, iclass 10, count 0 2006.173.03:27:11.79#ibcon#end of sib2, iclass 10, count 0 2006.173.03:27:11.79#ibcon#*after write, iclass 10, count 0 2006.173.03:27:11.79#ibcon#*before return 0, iclass 10, count 0 2006.173.03:27:11.79#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.03:27:11.79#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.03:27:11.79#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.03:27:11.79#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.03:27:11.79$vck44/valo=2,534.99 2006.173.03:27:11.79#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.03:27:11.79#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.03:27:11.79#ibcon#ireg 17 cls_cnt 0 2006.173.03:27:11.79#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.03:27:11.79#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.03:27:11.79#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.03:27:11.79#ibcon#enter wrdev, iclass 12, count 0 2006.173.03:27:11.79#ibcon#first serial, iclass 12, count 0 2006.173.03:27:11.79#ibcon#enter sib2, iclass 12, count 0 2006.173.03:27:11.79#ibcon#flushed, iclass 12, count 0 2006.173.03:27:11.79#ibcon#about to write, iclass 12, count 0 2006.173.03:27:11.79#ibcon#wrote, iclass 12, count 0 2006.173.03:27:11.79#ibcon#about to read 3, iclass 12, count 0 2006.173.03:27:11.81#ibcon#read 3, iclass 12, count 0 2006.173.03:27:11.81#ibcon#about to read 4, iclass 12, count 0 2006.173.03:27:11.81#ibcon#read 4, iclass 12, count 0 2006.173.03:27:11.81#ibcon#about to read 5, iclass 12, count 0 2006.173.03:27:11.81#ibcon#read 5, iclass 12, count 0 2006.173.03:27:11.81#ibcon#about to read 6, iclass 12, count 0 2006.173.03:27:11.81#ibcon#read 6, iclass 12, count 0 2006.173.03:27:11.81#ibcon#end of sib2, iclass 12, count 0 2006.173.03:27:11.81#ibcon#*mode == 0, iclass 12, count 0 2006.173.03:27:11.81#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.03:27:11.81#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.03:27:11.81#ibcon#*before write, iclass 12, count 0 2006.173.03:27:11.81#ibcon#enter sib2, iclass 12, count 0 2006.173.03:27:11.81#ibcon#flushed, iclass 12, count 0 2006.173.03:27:11.81#ibcon#about to write, iclass 12, count 0 2006.173.03:27:11.81#ibcon#wrote, iclass 12, count 0 2006.173.03:27:11.81#ibcon#about to read 3, iclass 12, count 0 2006.173.03:27:11.85#ibcon#read 3, iclass 12, count 0 2006.173.03:27:11.85#ibcon#about to read 4, iclass 12, count 0 2006.173.03:27:11.85#ibcon#read 4, iclass 12, count 0 2006.173.03:27:11.85#ibcon#about to read 5, iclass 12, count 0 2006.173.03:27:11.85#ibcon#read 5, iclass 12, count 0 2006.173.03:27:11.85#ibcon#about to read 6, iclass 12, count 0 2006.173.03:27:11.85#ibcon#read 6, iclass 12, count 0 2006.173.03:27:11.85#ibcon#end of sib2, iclass 12, count 0 2006.173.03:27:11.85#ibcon#*after write, iclass 12, count 0 2006.173.03:27:11.85#ibcon#*before return 0, iclass 12, count 0 2006.173.03:27:11.85#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.03:27:11.85#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.03:27:11.85#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.03:27:11.85#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.03:27:11.85$vck44/va=2,6 2006.173.03:27:11.85#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.03:27:11.85#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.03:27:11.85#ibcon#ireg 11 cls_cnt 2 2006.173.03:27:11.85#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.03:27:11.91#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.03:27:11.91#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.03:27:11.91#ibcon#enter wrdev, iclass 14, count 2 2006.173.03:27:11.91#ibcon#first serial, iclass 14, count 2 2006.173.03:27:11.91#ibcon#enter sib2, iclass 14, count 2 2006.173.03:27:11.91#ibcon#flushed, iclass 14, count 2 2006.173.03:27:11.91#ibcon#about to write, iclass 14, count 2 2006.173.03:27:11.91#ibcon#wrote, iclass 14, count 2 2006.173.03:27:11.91#ibcon#about to read 3, iclass 14, count 2 2006.173.03:27:11.93#ibcon#read 3, iclass 14, count 2 2006.173.03:27:11.93#ibcon#about to read 4, iclass 14, count 2 2006.173.03:27:11.93#ibcon#read 4, iclass 14, count 2 2006.173.03:27:11.93#ibcon#about to read 5, iclass 14, count 2 2006.173.03:27:11.93#ibcon#read 5, iclass 14, count 2 2006.173.03:27:11.93#ibcon#about to read 6, iclass 14, count 2 2006.173.03:27:11.93#ibcon#read 6, iclass 14, count 2 2006.173.03:27:11.93#ibcon#end of sib2, iclass 14, count 2 2006.173.03:27:11.93#ibcon#*mode == 0, iclass 14, count 2 2006.173.03:27:11.93#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.03:27:11.93#ibcon#[25=AT02-06\r\n] 2006.173.03:27:11.93#ibcon#*before write, iclass 14, count 2 2006.173.03:27:11.93#ibcon#enter sib2, iclass 14, count 2 2006.173.03:27:11.93#ibcon#flushed, iclass 14, count 2 2006.173.03:27:11.93#ibcon#about to write, iclass 14, count 2 2006.173.03:27:11.93#ibcon#wrote, iclass 14, count 2 2006.173.03:27:11.93#ibcon#about to read 3, iclass 14, count 2 2006.173.03:27:11.96#ibcon#read 3, iclass 14, count 2 2006.173.03:27:11.96#ibcon#about to read 4, iclass 14, count 2 2006.173.03:27:11.96#ibcon#read 4, iclass 14, count 2 2006.173.03:27:11.96#ibcon#about to read 5, iclass 14, count 2 2006.173.03:27:11.96#ibcon#read 5, iclass 14, count 2 2006.173.03:27:11.96#ibcon#about to read 6, iclass 14, count 2 2006.173.03:27:11.96#ibcon#read 6, iclass 14, count 2 2006.173.03:27:11.96#ibcon#end of sib2, iclass 14, count 2 2006.173.03:27:11.96#ibcon#*after write, iclass 14, count 2 2006.173.03:27:11.96#ibcon#*before return 0, iclass 14, count 2 2006.173.03:27:11.96#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.03:27:11.96#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.03:27:11.96#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.03:27:11.96#ibcon#ireg 7 cls_cnt 0 2006.173.03:27:11.96#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.03:27:12.08#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.03:27:12.08#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.03:27:12.08#ibcon#enter wrdev, iclass 14, count 0 2006.173.03:27:12.08#ibcon#first serial, iclass 14, count 0 2006.173.03:27:12.08#ibcon#enter sib2, iclass 14, count 0 2006.173.03:27:12.08#ibcon#flushed, iclass 14, count 0 2006.173.03:27:12.08#ibcon#about to write, iclass 14, count 0 2006.173.03:27:12.08#ibcon#wrote, iclass 14, count 0 2006.173.03:27:12.08#ibcon#about to read 3, iclass 14, count 0 2006.173.03:27:12.10#ibcon#read 3, iclass 14, count 0 2006.173.03:27:12.10#ibcon#about to read 4, iclass 14, count 0 2006.173.03:27:12.10#ibcon#read 4, iclass 14, count 0 2006.173.03:27:12.10#ibcon#about to read 5, iclass 14, count 0 2006.173.03:27:12.10#ibcon#read 5, iclass 14, count 0 2006.173.03:27:12.10#ibcon#about to read 6, iclass 14, count 0 2006.173.03:27:12.10#ibcon#read 6, iclass 14, count 0 2006.173.03:27:12.10#ibcon#end of sib2, iclass 14, count 0 2006.173.03:27:12.10#ibcon#*mode == 0, iclass 14, count 0 2006.173.03:27:12.10#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.03:27:12.10#ibcon#[25=USB\r\n] 2006.173.03:27:12.10#ibcon#*before write, iclass 14, count 0 2006.173.03:27:12.10#ibcon#enter sib2, iclass 14, count 0 2006.173.03:27:12.10#ibcon#flushed, iclass 14, count 0 2006.173.03:27:12.10#ibcon#about to write, iclass 14, count 0 2006.173.03:27:12.10#ibcon#wrote, iclass 14, count 0 2006.173.03:27:12.10#ibcon#about to read 3, iclass 14, count 0 2006.173.03:27:12.13#ibcon#read 3, iclass 14, count 0 2006.173.03:27:12.13#ibcon#about to read 4, iclass 14, count 0 2006.173.03:27:12.13#ibcon#read 4, iclass 14, count 0 2006.173.03:27:12.13#ibcon#about to read 5, iclass 14, count 0 2006.173.03:27:12.13#ibcon#read 5, iclass 14, count 0 2006.173.03:27:12.13#ibcon#about to read 6, iclass 14, count 0 2006.173.03:27:12.13#ibcon#read 6, iclass 14, count 0 2006.173.03:27:12.13#ibcon#end of sib2, iclass 14, count 0 2006.173.03:27:12.13#ibcon#*after write, iclass 14, count 0 2006.173.03:27:12.13#ibcon#*before return 0, iclass 14, count 0 2006.173.03:27:12.13#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.03:27:12.13#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.03:27:12.13#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.03:27:12.13#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.03:27:12.13$vck44/valo=3,564.99 2006.173.03:27:12.13#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.03:27:12.13#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.03:27:12.13#ibcon#ireg 17 cls_cnt 0 2006.173.03:27:12.13#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.03:27:12.13#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.03:27:12.13#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.03:27:12.13#ibcon#enter wrdev, iclass 16, count 0 2006.173.03:27:12.13#ibcon#first serial, iclass 16, count 0 2006.173.03:27:12.13#ibcon#enter sib2, iclass 16, count 0 2006.173.03:27:12.13#ibcon#flushed, iclass 16, count 0 2006.173.03:27:12.13#ibcon#about to write, iclass 16, count 0 2006.173.03:27:12.13#ibcon#wrote, iclass 16, count 0 2006.173.03:27:12.13#ibcon#about to read 3, iclass 16, count 0 2006.173.03:27:12.15#ibcon#read 3, iclass 16, count 0 2006.173.03:27:12.15#ibcon#about to read 4, iclass 16, count 0 2006.173.03:27:12.15#ibcon#read 4, iclass 16, count 0 2006.173.03:27:12.15#ibcon#about to read 5, iclass 16, count 0 2006.173.03:27:12.15#ibcon#read 5, iclass 16, count 0 2006.173.03:27:12.15#ibcon#about to read 6, iclass 16, count 0 2006.173.03:27:12.15#ibcon#read 6, iclass 16, count 0 2006.173.03:27:12.15#ibcon#end of sib2, iclass 16, count 0 2006.173.03:27:12.15#ibcon#*mode == 0, iclass 16, count 0 2006.173.03:27:12.15#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.03:27:12.15#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.03:27:12.15#ibcon#*before write, iclass 16, count 0 2006.173.03:27:12.15#ibcon#enter sib2, iclass 16, count 0 2006.173.03:27:12.15#ibcon#flushed, iclass 16, count 0 2006.173.03:27:12.15#ibcon#about to write, iclass 16, count 0 2006.173.03:27:12.15#ibcon#wrote, iclass 16, count 0 2006.173.03:27:12.15#ibcon#about to read 3, iclass 16, count 0 2006.173.03:27:12.19#ibcon#read 3, iclass 16, count 0 2006.173.03:27:12.19#ibcon#about to read 4, iclass 16, count 0 2006.173.03:27:12.19#ibcon#read 4, iclass 16, count 0 2006.173.03:27:12.19#ibcon#about to read 5, iclass 16, count 0 2006.173.03:27:12.19#ibcon#read 5, iclass 16, count 0 2006.173.03:27:12.19#ibcon#about to read 6, iclass 16, count 0 2006.173.03:27:12.19#ibcon#read 6, iclass 16, count 0 2006.173.03:27:12.19#ibcon#end of sib2, iclass 16, count 0 2006.173.03:27:12.19#ibcon#*after write, iclass 16, count 0 2006.173.03:27:12.19#ibcon#*before return 0, iclass 16, count 0 2006.173.03:27:12.19#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.03:27:12.19#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.03:27:12.19#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.03:27:12.19#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.03:27:12.19$vck44/va=3,5 2006.173.03:27:12.19#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.03:27:12.19#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.03:27:12.19#ibcon#ireg 11 cls_cnt 2 2006.173.03:27:12.19#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.03:27:12.25#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.03:27:12.25#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.03:27:12.25#ibcon#enter wrdev, iclass 18, count 2 2006.173.03:27:12.25#ibcon#first serial, iclass 18, count 2 2006.173.03:27:12.25#ibcon#enter sib2, iclass 18, count 2 2006.173.03:27:12.25#ibcon#flushed, iclass 18, count 2 2006.173.03:27:12.25#ibcon#about to write, iclass 18, count 2 2006.173.03:27:12.25#ibcon#wrote, iclass 18, count 2 2006.173.03:27:12.25#ibcon#about to read 3, iclass 18, count 2 2006.173.03:27:12.27#ibcon#read 3, iclass 18, count 2 2006.173.03:27:12.27#ibcon#about to read 4, iclass 18, count 2 2006.173.03:27:12.27#ibcon#read 4, iclass 18, count 2 2006.173.03:27:12.27#ibcon#about to read 5, iclass 18, count 2 2006.173.03:27:12.27#ibcon#read 5, iclass 18, count 2 2006.173.03:27:12.27#ibcon#about to read 6, iclass 18, count 2 2006.173.03:27:12.27#ibcon#read 6, iclass 18, count 2 2006.173.03:27:12.27#ibcon#end of sib2, iclass 18, count 2 2006.173.03:27:12.27#ibcon#*mode == 0, iclass 18, count 2 2006.173.03:27:12.27#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.03:27:12.27#ibcon#[25=AT03-05\r\n] 2006.173.03:27:12.27#ibcon#*before write, iclass 18, count 2 2006.173.03:27:12.27#ibcon#enter sib2, iclass 18, count 2 2006.173.03:27:12.27#ibcon#flushed, iclass 18, count 2 2006.173.03:27:12.27#ibcon#about to write, iclass 18, count 2 2006.173.03:27:12.27#ibcon#wrote, iclass 18, count 2 2006.173.03:27:12.27#ibcon#about to read 3, iclass 18, count 2 2006.173.03:27:12.30#ibcon#read 3, iclass 18, count 2 2006.173.03:27:12.30#ibcon#about to read 4, iclass 18, count 2 2006.173.03:27:12.30#ibcon#read 4, iclass 18, count 2 2006.173.03:27:12.30#ibcon#about to read 5, iclass 18, count 2 2006.173.03:27:12.30#ibcon#read 5, iclass 18, count 2 2006.173.03:27:12.30#ibcon#about to read 6, iclass 18, count 2 2006.173.03:27:12.30#ibcon#read 6, iclass 18, count 2 2006.173.03:27:12.30#ibcon#end of sib2, iclass 18, count 2 2006.173.03:27:12.30#ibcon#*after write, iclass 18, count 2 2006.173.03:27:12.30#ibcon#*before return 0, iclass 18, count 2 2006.173.03:27:12.30#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.03:27:12.30#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.03:27:12.30#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.03:27:12.30#ibcon#ireg 7 cls_cnt 0 2006.173.03:27:12.30#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.03:27:12.42#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.03:27:12.42#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.03:27:12.42#ibcon#enter wrdev, iclass 18, count 0 2006.173.03:27:12.42#ibcon#first serial, iclass 18, count 0 2006.173.03:27:12.42#ibcon#enter sib2, iclass 18, count 0 2006.173.03:27:12.42#ibcon#flushed, iclass 18, count 0 2006.173.03:27:12.42#ibcon#about to write, iclass 18, count 0 2006.173.03:27:12.42#ibcon#wrote, iclass 18, count 0 2006.173.03:27:12.42#ibcon#about to read 3, iclass 18, count 0 2006.173.03:27:12.44#ibcon#read 3, iclass 18, count 0 2006.173.03:27:12.44#ibcon#about to read 4, iclass 18, count 0 2006.173.03:27:12.44#ibcon#read 4, iclass 18, count 0 2006.173.03:27:12.44#ibcon#about to read 5, iclass 18, count 0 2006.173.03:27:12.44#ibcon#read 5, iclass 18, count 0 2006.173.03:27:12.44#ibcon#about to read 6, iclass 18, count 0 2006.173.03:27:12.44#ibcon#read 6, iclass 18, count 0 2006.173.03:27:12.44#ibcon#end of sib2, iclass 18, count 0 2006.173.03:27:12.44#ibcon#*mode == 0, iclass 18, count 0 2006.173.03:27:12.44#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.03:27:12.44#ibcon#[25=USB\r\n] 2006.173.03:27:12.44#ibcon#*before write, iclass 18, count 0 2006.173.03:27:12.44#ibcon#enter sib2, iclass 18, count 0 2006.173.03:27:12.44#ibcon#flushed, iclass 18, count 0 2006.173.03:27:12.44#ibcon#about to write, iclass 18, count 0 2006.173.03:27:12.44#ibcon#wrote, iclass 18, count 0 2006.173.03:27:12.44#ibcon#about to read 3, iclass 18, count 0 2006.173.03:27:12.47#ibcon#read 3, iclass 18, count 0 2006.173.03:27:12.47#ibcon#about to read 4, iclass 18, count 0 2006.173.03:27:12.47#ibcon#read 4, iclass 18, count 0 2006.173.03:27:12.47#ibcon#about to read 5, iclass 18, count 0 2006.173.03:27:12.47#ibcon#read 5, iclass 18, count 0 2006.173.03:27:12.47#ibcon#about to read 6, iclass 18, count 0 2006.173.03:27:12.47#ibcon#read 6, iclass 18, count 0 2006.173.03:27:12.47#ibcon#end of sib2, iclass 18, count 0 2006.173.03:27:12.47#ibcon#*after write, iclass 18, count 0 2006.173.03:27:12.47#ibcon#*before return 0, iclass 18, count 0 2006.173.03:27:12.47#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.03:27:12.47#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.03:27:12.47#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.03:27:12.47#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.03:27:12.47$vck44/valo=4,624.99 2006.173.03:27:12.47#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.03:27:12.47#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.03:27:12.47#ibcon#ireg 17 cls_cnt 0 2006.173.03:27:12.47#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.03:27:12.47#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.03:27:12.47#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.03:27:12.47#ibcon#enter wrdev, iclass 20, count 0 2006.173.03:27:12.47#ibcon#first serial, iclass 20, count 0 2006.173.03:27:12.47#ibcon#enter sib2, iclass 20, count 0 2006.173.03:27:12.47#ibcon#flushed, iclass 20, count 0 2006.173.03:27:12.47#ibcon#about to write, iclass 20, count 0 2006.173.03:27:12.47#ibcon#wrote, iclass 20, count 0 2006.173.03:27:12.47#ibcon#about to read 3, iclass 20, count 0 2006.173.03:27:12.49#ibcon#read 3, iclass 20, count 0 2006.173.03:27:12.49#ibcon#about to read 4, iclass 20, count 0 2006.173.03:27:12.49#ibcon#read 4, iclass 20, count 0 2006.173.03:27:12.49#ibcon#about to read 5, iclass 20, count 0 2006.173.03:27:12.49#ibcon#read 5, iclass 20, count 0 2006.173.03:27:12.49#ibcon#about to read 6, iclass 20, count 0 2006.173.03:27:12.49#ibcon#read 6, iclass 20, count 0 2006.173.03:27:12.49#ibcon#end of sib2, iclass 20, count 0 2006.173.03:27:12.49#ibcon#*mode == 0, iclass 20, count 0 2006.173.03:27:12.49#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.03:27:12.49#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.03:27:12.49#ibcon#*before write, iclass 20, count 0 2006.173.03:27:12.49#ibcon#enter sib2, iclass 20, count 0 2006.173.03:27:12.49#ibcon#flushed, iclass 20, count 0 2006.173.03:27:12.49#ibcon#about to write, iclass 20, count 0 2006.173.03:27:12.49#ibcon#wrote, iclass 20, count 0 2006.173.03:27:12.49#ibcon#about to read 3, iclass 20, count 0 2006.173.03:27:12.53#ibcon#read 3, iclass 20, count 0 2006.173.03:27:12.53#ibcon#about to read 4, iclass 20, count 0 2006.173.03:27:12.53#ibcon#read 4, iclass 20, count 0 2006.173.03:27:12.53#ibcon#about to read 5, iclass 20, count 0 2006.173.03:27:12.53#ibcon#read 5, iclass 20, count 0 2006.173.03:27:12.53#ibcon#about to read 6, iclass 20, count 0 2006.173.03:27:12.53#ibcon#read 6, iclass 20, count 0 2006.173.03:27:12.53#ibcon#end of sib2, iclass 20, count 0 2006.173.03:27:12.53#ibcon#*after write, iclass 20, count 0 2006.173.03:27:12.53#ibcon#*before return 0, iclass 20, count 0 2006.173.03:27:12.53#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.03:27:12.53#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.03:27:12.53#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.03:27:12.53#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.03:27:12.53$vck44/va=4,6 2006.173.03:27:12.53#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.03:27:12.53#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.03:27:12.53#ibcon#ireg 11 cls_cnt 2 2006.173.03:27:12.53#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.03:27:12.59#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.03:27:12.59#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.03:27:12.59#ibcon#enter wrdev, iclass 22, count 2 2006.173.03:27:12.59#ibcon#first serial, iclass 22, count 2 2006.173.03:27:12.59#ibcon#enter sib2, iclass 22, count 2 2006.173.03:27:12.59#ibcon#flushed, iclass 22, count 2 2006.173.03:27:12.59#ibcon#about to write, iclass 22, count 2 2006.173.03:27:12.59#ibcon#wrote, iclass 22, count 2 2006.173.03:27:12.59#ibcon#about to read 3, iclass 22, count 2 2006.173.03:27:12.61#ibcon#read 3, iclass 22, count 2 2006.173.03:27:12.61#ibcon#about to read 4, iclass 22, count 2 2006.173.03:27:12.61#ibcon#read 4, iclass 22, count 2 2006.173.03:27:12.61#ibcon#about to read 5, iclass 22, count 2 2006.173.03:27:12.61#ibcon#read 5, iclass 22, count 2 2006.173.03:27:12.61#ibcon#about to read 6, iclass 22, count 2 2006.173.03:27:12.61#ibcon#read 6, iclass 22, count 2 2006.173.03:27:12.61#ibcon#end of sib2, iclass 22, count 2 2006.173.03:27:12.61#ibcon#*mode == 0, iclass 22, count 2 2006.173.03:27:12.61#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.03:27:12.61#ibcon#[25=AT04-06\r\n] 2006.173.03:27:12.61#ibcon#*before write, iclass 22, count 2 2006.173.03:27:12.61#ibcon#enter sib2, iclass 22, count 2 2006.173.03:27:12.61#ibcon#flushed, iclass 22, count 2 2006.173.03:27:12.61#ibcon#about to write, iclass 22, count 2 2006.173.03:27:12.61#ibcon#wrote, iclass 22, count 2 2006.173.03:27:12.61#ibcon#about to read 3, iclass 22, count 2 2006.173.03:27:12.64#ibcon#read 3, iclass 22, count 2 2006.173.03:27:12.64#ibcon#about to read 4, iclass 22, count 2 2006.173.03:27:12.64#ibcon#read 4, iclass 22, count 2 2006.173.03:27:12.64#ibcon#about to read 5, iclass 22, count 2 2006.173.03:27:12.64#ibcon#read 5, iclass 22, count 2 2006.173.03:27:12.64#ibcon#about to read 6, iclass 22, count 2 2006.173.03:27:12.64#ibcon#read 6, iclass 22, count 2 2006.173.03:27:12.64#ibcon#end of sib2, iclass 22, count 2 2006.173.03:27:12.64#ibcon#*after write, iclass 22, count 2 2006.173.03:27:12.64#ibcon#*before return 0, iclass 22, count 2 2006.173.03:27:12.64#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.03:27:12.64#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.03:27:12.64#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.03:27:12.64#ibcon#ireg 7 cls_cnt 0 2006.173.03:27:12.64#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.03:27:12.76#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.03:27:12.76#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.03:27:12.76#ibcon#enter wrdev, iclass 22, count 0 2006.173.03:27:12.76#ibcon#first serial, iclass 22, count 0 2006.173.03:27:12.76#ibcon#enter sib2, iclass 22, count 0 2006.173.03:27:12.76#ibcon#flushed, iclass 22, count 0 2006.173.03:27:12.76#ibcon#about to write, iclass 22, count 0 2006.173.03:27:12.76#ibcon#wrote, iclass 22, count 0 2006.173.03:27:12.76#ibcon#about to read 3, iclass 22, count 0 2006.173.03:27:12.78#ibcon#read 3, iclass 22, count 0 2006.173.03:27:12.78#ibcon#about to read 4, iclass 22, count 0 2006.173.03:27:12.78#ibcon#read 4, iclass 22, count 0 2006.173.03:27:12.78#ibcon#about to read 5, iclass 22, count 0 2006.173.03:27:12.78#ibcon#read 5, iclass 22, count 0 2006.173.03:27:12.78#ibcon#about to read 6, iclass 22, count 0 2006.173.03:27:12.78#ibcon#read 6, iclass 22, count 0 2006.173.03:27:12.78#ibcon#end of sib2, iclass 22, count 0 2006.173.03:27:12.78#ibcon#*mode == 0, iclass 22, count 0 2006.173.03:27:12.78#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.03:27:12.78#ibcon#[25=USB\r\n] 2006.173.03:27:12.78#ibcon#*before write, iclass 22, count 0 2006.173.03:27:12.78#ibcon#enter sib2, iclass 22, count 0 2006.173.03:27:12.78#ibcon#flushed, iclass 22, count 0 2006.173.03:27:12.78#ibcon#about to write, iclass 22, count 0 2006.173.03:27:12.78#ibcon#wrote, iclass 22, count 0 2006.173.03:27:12.78#ibcon#about to read 3, iclass 22, count 0 2006.173.03:27:12.81#ibcon#read 3, iclass 22, count 0 2006.173.03:27:12.81#ibcon#about to read 4, iclass 22, count 0 2006.173.03:27:12.81#ibcon#read 4, iclass 22, count 0 2006.173.03:27:12.81#ibcon#about to read 5, iclass 22, count 0 2006.173.03:27:12.81#ibcon#read 5, iclass 22, count 0 2006.173.03:27:12.81#ibcon#about to read 6, iclass 22, count 0 2006.173.03:27:12.81#ibcon#read 6, iclass 22, count 0 2006.173.03:27:12.81#ibcon#end of sib2, iclass 22, count 0 2006.173.03:27:12.81#ibcon#*after write, iclass 22, count 0 2006.173.03:27:12.81#ibcon#*before return 0, iclass 22, count 0 2006.173.03:27:12.81#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.03:27:12.81#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.03:27:12.81#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.03:27:12.81#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.03:27:12.81$vck44/valo=5,734.99 2006.173.03:27:12.81#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.03:27:12.81#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.03:27:12.81#ibcon#ireg 17 cls_cnt 0 2006.173.03:27:12.81#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.03:27:12.81#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.03:27:12.81#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.03:27:12.81#ibcon#enter wrdev, iclass 24, count 0 2006.173.03:27:12.81#ibcon#first serial, iclass 24, count 0 2006.173.03:27:12.81#ibcon#enter sib2, iclass 24, count 0 2006.173.03:27:12.81#ibcon#flushed, iclass 24, count 0 2006.173.03:27:12.81#ibcon#about to write, iclass 24, count 0 2006.173.03:27:12.81#ibcon#wrote, iclass 24, count 0 2006.173.03:27:12.81#ibcon#about to read 3, iclass 24, count 0 2006.173.03:27:12.83#ibcon#read 3, iclass 24, count 0 2006.173.03:27:12.83#ibcon#about to read 4, iclass 24, count 0 2006.173.03:27:12.83#ibcon#read 4, iclass 24, count 0 2006.173.03:27:12.83#ibcon#about to read 5, iclass 24, count 0 2006.173.03:27:12.83#ibcon#read 5, iclass 24, count 0 2006.173.03:27:12.83#ibcon#about to read 6, iclass 24, count 0 2006.173.03:27:12.83#ibcon#read 6, iclass 24, count 0 2006.173.03:27:12.83#ibcon#end of sib2, iclass 24, count 0 2006.173.03:27:12.83#ibcon#*mode == 0, iclass 24, count 0 2006.173.03:27:12.83#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.03:27:12.83#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.03:27:12.83#ibcon#*before write, iclass 24, count 0 2006.173.03:27:12.83#ibcon#enter sib2, iclass 24, count 0 2006.173.03:27:12.83#ibcon#flushed, iclass 24, count 0 2006.173.03:27:12.83#ibcon#about to write, iclass 24, count 0 2006.173.03:27:12.83#ibcon#wrote, iclass 24, count 0 2006.173.03:27:12.83#ibcon#about to read 3, iclass 24, count 0 2006.173.03:27:12.87#ibcon#read 3, iclass 24, count 0 2006.173.03:27:12.87#ibcon#about to read 4, iclass 24, count 0 2006.173.03:27:12.87#ibcon#read 4, iclass 24, count 0 2006.173.03:27:12.87#ibcon#about to read 5, iclass 24, count 0 2006.173.03:27:12.87#ibcon#read 5, iclass 24, count 0 2006.173.03:27:12.87#ibcon#about to read 6, iclass 24, count 0 2006.173.03:27:12.87#ibcon#read 6, iclass 24, count 0 2006.173.03:27:12.87#ibcon#end of sib2, iclass 24, count 0 2006.173.03:27:12.87#ibcon#*after write, iclass 24, count 0 2006.173.03:27:12.87#ibcon#*before return 0, iclass 24, count 0 2006.173.03:27:12.87#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.03:27:12.87#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.03:27:12.87#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.03:27:12.87#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.03:27:12.87$vck44/va=5,4 2006.173.03:27:12.87#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.03:27:12.87#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.03:27:12.87#ibcon#ireg 11 cls_cnt 2 2006.173.03:27:12.87#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.03:27:12.93#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.03:27:12.93#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.03:27:12.93#ibcon#enter wrdev, iclass 26, count 2 2006.173.03:27:12.93#ibcon#first serial, iclass 26, count 2 2006.173.03:27:12.93#ibcon#enter sib2, iclass 26, count 2 2006.173.03:27:12.93#ibcon#flushed, iclass 26, count 2 2006.173.03:27:12.93#ibcon#about to write, iclass 26, count 2 2006.173.03:27:12.93#ibcon#wrote, iclass 26, count 2 2006.173.03:27:12.93#ibcon#about to read 3, iclass 26, count 2 2006.173.03:27:12.95#ibcon#read 3, iclass 26, count 2 2006.173.03:27:12.95#ibcon#about to read 4, iclass 26, count 2 2006.173.03:27:12.95#ibcon#read 4, iclass 26, count 2 2006.173.03:27:12.95#ibcon#about to read 5, iclass 26, count 2 2006.173.03:27:12.95#ibcon#read 5, iclass 26, count 2 2006.173.03:27:12.95#ibcon#about to read 6, iclass 26, count 2 2006.173.03:27:12.95#ibcon#read 6, iclass 26, count 2 2006.173.03:27:12.95#ibcon#end of sib2, iclass 26, count 2 2006.173.03:27:12.95#ibcon#*mode == 0, iclass 26, count 2 2006.173.03:27:12.95#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.03:27:12.95#ibcon#[25=AT05-04\r\n] 2006.173.03:27:12.95#ibcon#*before write, iclass 26, count 2 2006.173.03:27:12.95#ibcon#enter sib2, iclass 26, count 2 2006.173.03:27:12.95#ibcon#flushed, iclass 26, count 2 2006.173.03:27:12.95#ibcon#about to write, iclass 26, count 2 2006.173.03:27:12.95#ibcon#wrote, iclass 26, count 2 2006.173.03:27:12.95#ibcon#about to read 3, iclass 26, count 2 2006.173.03:27:12.98#ibcon#read 3, iclass 26, count 2 2006.173.03:27:12.98#ibcon#about to read 4, iclass 26, count 2 2006.173.03:27:12.98#ibcon#read 4, iclass 26, count 2 2006.173.03:27:12.98#ibcon#about to read 5, iclass 26, count 2 2006.173.03:27:12.98#ibcon#read 5, iclass 26, count 2 2006.173.03:27:12.98#ibcon#about to read 6, iclass 26, count 2 2006.173.03:27:12.98#ibcon#read 6, iclass 26, count 2 2006.173.03:27:12.98#ibcon#end of sib2, iclass 26, count 2 2006.173.03:27:12.98#ibcon#*after write, iclass 26, count 2 2006.173.03:27:12.98#ibcon#*before return 0, iclass 26, count 2 2006.173.03:27:12.98#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.03:27:12.98#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.03:27:12.98#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.03:27:12.98#ibcon#ireg 7 cls_cnt 0 2006.173.03:27:12.98#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.03:27:13.10#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.03:27:13.10#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.03:27:13.10#ibcon#enter wrdev, iclass 26, count 0 2006.173.03:27:13.10#ibcon#first serial, iclass 26, count 0 2006.173.03:27:13.10#ibcon#enter sib2, iclass 26, count 0 2006.173.03:27:13.10#ibcon#flushed, iclass 26, count 0 2006.173.03:27:13.10#ibcon#about to write, iclass 26, count 0 2006.173.03:27:13.10#ibcon#wrote, iclass 26, count 0 2006.173.03:27:13.10#ibcon#about to read 3, iclass 26, count 0 2006.173.03:27:13.12#ibcon#read 3, iclass 26, count 0 2006.173.03:27:13.12#ibcon#about to read 4, iclass 26, count 0 2006.173.03:27:13.12#ibcon#read 4, iclass 26, count 0 2006.173.03:27:13.12#ibcon#about to read 5, iclass 26, count 0 2006.173.03:27:13.12#ibcon#read 5, iclass 26, count 0 2006.173.03:27:13.12#ibcon#about to read 6, iclass 26, count 0 2006.173.03:27:13.12#ibcon#read 6, iclass 26, count 0 2006.173.03:27:13.12#ibcon#end of sib2, iclass 26, count 0 2006.173.03:27:13.12#ibcon#*mode == 0, iclass 26, count 0 2006.173.03:27:13.12#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.03:27:13.12#ibcon#[25=USB\r\n] 2006.173.03:27:13.12#ibcon#*before write, iclass 26, count 0 2006.173.03:27:13.12#ibcon#enter sib2, iclass 26, count 0 2006.173.03:27:13.12#ibcon#flushed, iclass 26, count 0 2006.173.03:27:13.12#ibcon#about to write, iclass 26, count 0 2006.173.03:27:13.12#ibcon#wrote, iclass 26, count 0 2006.173.03:27:13.12#ibcon#about to read 3, iclass 26, count 0 2006.173.03:27:13.15#ibcon#read 3, iclass 26, count 0 2006.173.03:27:13.15#ibcon#about to read 4, iclass 26, count 0 2006.173.03:27:13.15#ibcon#read 4, iclass 26, count 0 2006.173.03:27:13.15#ibcon#about to read 5, iclass 26, count 0 2006.173.03:27:13.15#ibcon#read 5, iclass 26, count 0 2006.173.03:27:13.15#ibcon#about to read 6, iclass 26, count 0 2006.173.03:27:13.15#ibcon#read 6, iclass 26, count 0 2006.173.03:27:13.15#ibcon#end of sib2, iclass 26, count 0 2006.173.03:27:13.15#ibcon#*after write, iclass 26, count 0 2006.173.03:27:13.15#ibcon#*before return 0, iclass 26, count 0 2006.173.03:27:13.15#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.03:27:13.15#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.03:27:13.15#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.03:27:13.15#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.03:27:13.15$vck44/valo=6,814.99 2006.173.03:27:13.15#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.03:27:13.15#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.03:27:13.15#ibcon#ireg 17 cls_cnt 0 2006.173.03:27:13.15#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.03:27:13.15#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.03:27:13.15#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.03:27:13.15#ibcon#enter wrdev, iclass 28, count 0 2006.173.03:27:13.15#ibcon#first serial, iclass 28, count 0 2006.173.03:27:13.15#ibcon#enter sib2, iclass 28, count 0 2006.173.03:27:13.15#ibcon#flushed, iclass 28, count 0 2006.173.03:27:13.15#ibcon#about to write, iclass 28, count 0 2006.173.03:27:13.15#ibcon#wrote, iclass 28, count 0 2006.173.03:27:13.15#ibcon#about to read 3, iclass 28, count 0 2006.173.03:27:13.17#ibcon#read 3, iclass 28, count 0 2006.173.03:27:13.17#ibcon#about to read 4, iclass 28, count 0 2006.173.03:27:13.17#ibcon#read 4, iclass 28, count 0 2006.173.03:27:13.17#ibcon#about to read 5, iclass 28, count 0 2006.173.03:27:13.17#ibcon#read 5, iclass 28, count 0 2006.173.03:27:13.17#ibcon#about to read 6, iclass 28, count 0 2006.173.03:27:13.17#ibcon#read 6, iclass 28, count 0 2006.173.03:27:13.17#ibcon#end of sib2, iclass 28, count 0 2006.173.03:27:13.17#ibcon#*mode == 0, iclass 28, count 0 2006.173.03:27:13.17#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.03:27:13.17#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.03:27:13.17#ibcon#*before write, iclass 28, count 0 2006.173.03:27:13.17#ibcon#enter sib2, iclass 28, count 0 2006.173.03:27:13.17#ibcon#flushed, iclass 28, count 0 2006.173.03:27:13.17#ibcon#about to write, iclass 28, count 0 2006.173.03:27:13.17#ibcon#wrote, iclass 28, count 0 2006.173.03:27:13.17#ibcon#about to read 3, iclass 28, count 0 2006.173.03:27:13.21#ibcon#read 3, iclass 28, count 0 2006.173.03:27:13.21#ibcon#about to read 4, iclass 28, count 0 2006.173.03:27:13.21#ibcon#read 4, iclass 28, count 0 2006.173.03:27:13.21#ibcon#about to read 5, iclass 28, count 0 2006.173.03:27:13.21#ibcon#read 5, iclass 28, count 0 2006.173.03:27:13.21#ibcon#about to read 6, iclass 28, count 0 2006.173.03:27:13.21#ibcon#read 6, iclass 28, count 0 2006.173.03:27:13.21#ibcon#end of sib2, iclass 28, count 0 2006.173.03:27:13.21#ibcon#*after write, iclass 28, count 0 2006.173.03:27:13.21#ibcon#*before return 0, iclass 28, count 0 2006.173.03:27:13.21#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.03:27:13.21#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.03:27:13.21#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.03:27:13.21#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.03:27:13.21$vck44/va=6,3 2006.173.03:27:13.21#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.03:27:13.21#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.03:27:13.21#ibcon#ireg 11 cls_cnt 2 2006.173.03:27:13.21#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.03:27:13.27#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.03:27:13.27#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.03:27:13.27#ibcon#enter wrdev, iclass 30, count 2 2006.173.03:27:13.27#ibcon#first serial, iclass 30, count 2 2006.173.03:27:13.27#ibcon#enter sib2, iclass 30, count 2 2006.173.03:27:13.27#ibcon#flushed, iclass 30, count 2 2006.173.03:27:13.27#ibcon#about to write, iclass 30, count 2 2006.173.03:27:13.27#ibcon#wrote, iclass 30, count 2 2006.173.03:27:13.27#ibcon#about to read 3, iclass 30, count 2 2006.173.03:27:13.29#ibcon#read 3, iclass 30, count 2 2006.173.03:27:13.29#ibcon#about to read 4, iclass 30, count 2 2006.173.03:27:13.29#ibcon#read 4, iclass 30, count 2 2006.173.03:27:13.29#ibcon#about to read 5, iclass 30, count 2 2006.173.03:27:13.29#ibcon#read 5, iclass 30, count 2 2006.173.03:27:13.29#ibcon#about to read 6, iclass 30, count 2 2006.173.03:27:13.29#ibcon#read 6, iclass 30, count 2 2006.173.03:27:13.29#ibcon#end of sib2, iclass 30, count 2 2006.173.03:27:13.29#ibcon#*mode == 0, iclass 30, count 2 2006.173.03:27:13.29#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.03:27:13.29#ibcon#[25=AT06-03\r\n] 2006.173.03:27:13.29#ibcon#*before write, iclass 30, count 2 2006.173.03:27:13.29#ibcon#enter sib2, iclass 30, count 2 2006.173.03:27:13.29#ibcon#flushed, iclass 30, count 2 2006.173.03:27:13.29#ibcon#about to write, iclass 30, count 2 2006.173.03:27:13.29#ibcon#wrote, iclass 30, count 2 2006.173.03:27:13.29#ibcon#about to read 3, iclass 30, count 2 2006.173.03:27:13.32#ibcon#read 3, iclass 30, count 2 2006.173.03:27:13.32#ibcon#about to read 4, iclass 30, count 2 2006.173.03:27:13.32#ibcon#read 4, iclass 30, count 2 2006.173.03:27:13.32#ibcon#about to read 5, iclass 30, count 2 2006.173.03:27:13.32#ibcon#read 5, iclass 30, count 2 2006.173.03:27:13.32#ibcon#about to read 6, iclass 30, count 2 2006.173.03:27:13.32#ibcon#read 6, iclass 30, count 2 2006.173.03:27:13.32#ibcon#end of sib2, iclass 30, count 2 2006.173.03:27:13.32#ibcon#*after write, iclass 30, count 2 2006.173.03:27:13.32#ibcon#*before return 0, iclass 30, count 2 2006.173.03:27:13.32#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.03:27:13.32#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.03:27:13.32#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.03:27:13.32#ibcon#ireg 7 cls_cnt 0 2006.173.03:27:13.32#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.03:27:13.44#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.03:27:13.44#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.03:27:13.44#ibcon#enter wrdev, iclass 30, count 0 2006.173.03:27:13.44#ibcon#first serial, iclass 30, count 0 2006.173.03:27:13.44#ibcon#enter sib2, iclass 30, count 0 2006.173.03:27:13.44#ibcon#flushed, iclass 30, count 0 2006.173.03:27:13.44#ibcon#about to write, iclass 30, count 0 2006.173.03:27:13.44#ibcon#wrote, iclass 30, count 0 2006.173.03:27:13.44#ibcon#about to read 3, iclass 30, count 0 2006.173.03:27:13.46#ibcon#read 3, iclass 30, count 0 2006.173.03:27:13.46#ibcon#about to read 4, iclass 30, count 0 2006.173.03:27:13.46#ibcon#read 4, iclass 30, count 0 2006.173.03:27:13.46#ibcon#about to read 5, iclass 30, count 0 2006.173.03:27:13.46#ibcon#read 5, iclass 30, count 0 2006.173.03:27:13.46#ibcon#about to read 6, iclass 30, count 0 2006.173.03:27:13.46#ibcon#read 6, iclass 30, count 0 2006.173.03:27:13.46#ibcon#end of sib2, iclass 30, count 0 2006.173.03:27:13.46#ibcon#*mode == 0, iclass 30, count 0 2006.173.03:27:13.46#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.03:27:13.46#ibcon#[25=USB\r\n] 2006.173.03:27:13.46#ibcon#*before write, iclass 30, count 0 2006.173.03:27:13.46#ibcon#enter sib2, iclass 30, count 0 2006.173.03:27:13.46#ibcon#flushed, iclass 30, count 0 2006.173.03:27:13.46#ibcon#about to write, iclass 30, count 0 2006.173.03:27:13.46#ibcon#wrote, iclass 30, count 0 2006.173.03:27:13.46#ibcon#about to read 3, iclass 30, count 0 2006.173.03:27:13.49#ibcon#read 3, iclass 30, count 0 2006.173.03:27:13.49#ibcon#about to read 4, iclass 30, count 0 2006.173.03:27:13.49#ibcon#read 4, iclass 30, count 0 2006.173.03:27:13.49#ibcon#about to read 5, iclass 30, count 0 2006.173.03:27:13.49#ibcon#read 5, iclass 30, count 0 2006.173.03:27:13.49#ibcon#about to read 6, iclass 30, count 0 2006.173.03:27:13.49#ibcon#read 6, iclass 30, count 0 2006.173.03:27:13.49#ibcon#end of sib2, iclass 30, count 0 2006.173.03:27:13.49#ibcon#*after write, iclass 30, count 0 2006.173.03:27:13.49#ibcon#*before return 0, iclass 30, count 0 2006.173.03:27:13.49#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.03:27:13.49#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.03:27:13.49#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.03:27:13.49#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.03:27:13.49$vck44/valo=7,864.99 2006.173.03:27:13.49#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.03:27:13.49#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.03:27:13.49#ibcon#ireg 17 cls_cnt 0 2006.173.03:27:13.49#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.03:27:13.49#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.03:27:13.49#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.03:27:13.49#ibcon#enter wrdev, iclass 32, count 0 2006.173.03:27:13.49#ibcon#first serial, iclass 32, count 0 2006.173.03:27:13.49#ibcon#enter sib2, iclass 32, count 0 2006.173.03:27:13.49#ibcon#flushed, iclass 32, count 0 2006.173.03:27:13.49#ibcon#about to write, iclass 32, count 0 2006.173.03:27:13.49#ibcon#wrote, iclass 32, count 0 2006.173.03:27:13.49#ibcon#about to read 3, iclass 32, count 0 2006.173.03:27:13.51#ibcon#read 3, iclass 32, count 0 2006.173.03:27:13.51#ibcon#about to read 4, iclass 32, count 0 2006.173.03:27:13.51#ibcon#read 4, iclass 32, count 0 2006.173.03:27:13.51#ibcon#about to read 5, iclass 32, count 0 2006.173.03:27:13.51#ibcon#read 5, iclass 32, count 0 2006.173.03:27:13.51#ibcon#about to read 6, iclass 32, count 0 2006.173.03:27:13.51#ibcon#read 6, iclass 32, count 0 2006.173.03:27:13.51#ibcon#end of sib2, iclass 32, count 0 2006.173.03:27:13.51#ibcon#*mode == 0, iclass 32, count 0 2006.173.03:27:13.51#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.03:27:13.51#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.03:27:13.51#ibcon#*before write, iclass 32, count 0 2006.173.03:27:13.51#ibcon#enter sib2, iclass 32, count 0 2006.173.03:27:13.51#ibcon#flushed, iclass 32, count 0 2006.173.03:27:13.51#ibcon#about to write, iclass 32, count 0 2006.173.03:27:13.51#ibcon#wrote, iclass 32, count 0 2006.173.03:27:13.51#ibcon#about to read 3, iclass 32, count 0 2006.173.03:27:13.55#ibcon#read 3, iclass 32, count 0 2006.173.03:27:13.55#ibcon#about to read 4, iclass 32, count 0 2006.173.03:27:13.55#ibcon#read 4, iclass 32, count 0 2006.173.03:27:13.55#ibcon#about to read 5, iclass 32, count 0 2006.173.03:27:13.55#ibcon#read 5, iclass 32, count 0 2006.173.03:27:13.55#ibcon#about to read 6, iclass 32, count 0 2006.173.03:27:13.55#ibcon#read 6, iclass 32, count 0 2006.173.03:27:13.55#ibcon#end of sib2, iclass 32, count 0 2006.173.03:27:13.55#ibcon#*after write, iclass 32, count 0 2006.173.03:27:13.55#ibcon#*before return 0, iclass 32, count 0 2006.173.03:27:13.55#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.03:27:13.55#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.03:27:13.55#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.03:27:13.55#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.03:27:13.55$vck44/va=7,4 2006.173.03:27:13.55#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.03:27:13.55#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.03:27:13.55#ibcon#ireg 11 cls_cnt 2 2006.173.03:27:13.55#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.03:27:13.61#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.03:27:13.61#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.03:27:13.61#ibcon#enter wrdev, iclass 34, count 2 2006.173.03:27:13.61#ibcon#first serial, iclass 34, count 2 2006.173.03:27:13.61#ibcon#enter sib2, iclass 34, count 2 2006.173.03:27:13.61#ibcon#flushed, iclass 34, count 2 2006.173.03:27:13.61#ibcon#about to write, iclass 34, count 2 2006.173.03:27:13.61#ibcon#wrote, iclass 34, count 2 2006.173.03:27:13.61#ibcon#about to read 3, iclass 34, count 2 2006.173.03:27:13.63#ibcon#read 3, iclass 34, count 2 2006.173.03:27:13.63#ibcon#about to read 4, iclass 34, count 2 2006.173.03:27:13.63#ibcon#read 4, iclass 34, count 2 2006.173.03:27:13.63#ibcon#about to read 5, iclass 34, count 2 2006.173.03:27:13.63#ibcon#read 5, iclass 34, count 2 2006.173.03:27:13.63#ibcon#about to read 6, iclass 34, count 2 2006.173.03:27:13.63#ibcon#read 6, iclass 34, count 2 2006.173.03:27:13.63#ibcon#end of sib2, iclass 34, count 2 2006.173.03:27:13.63#ibcon#*mode == 0, iclass 34, count 2 2006.173.03:27:13.63#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.03:27:13.63#ibcon#[25=AT07-04\r\n] 2006.173.03:27:13.63#ibcon#*before write, iclass 34, count 2 2006.173.03:27:13.63#ibcon#enter sib2, iclass 34, count 2 2006.173.03:27:13.63#ibcon#flushed, iclass 34, count 2 2006.173.03:27:13.63#ibcon#about to write, iclass 34, count 2 2006.173.03:27:13.63#ibcon#wrote, iclass 34, count 2 2006.173.03:27:13.63#ibcon#about to read 3, iclass 34, count 2 2006.173.03:27:13.66#ibcon#read 3, iclass 34, count 2 2006.173.03:27:13.66#ibcon#about to read 4, iclass 34, count 2 2006.173.03:27:13.66#ibcon#read 4, iclass 34, count 2 2006.173.03:27:13.66#ibcon#about to read 5, iclass 34, count 2 2006.173.03:27:13.66#ibcon#read 5, iclass 34, count 2 2006.173.03:27:13.66#ibcon#about to read 6, iclass 34, count 2 2006.173.03:27:13.66#ibcon#read 6, iclass 34, count 2 2006.173.03:27:13.66#ibcon#end of sib2, iclass 34, count 2 2006.173.03:27:13.66#ibcon#*after write, iclass 34, count 2 2006.173.03:27:13.66#ibcon#*before return 0, iclass 34, count 2 2006.173.03:27:13.66#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.03:27:13.66#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.03:27:13.66#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.03:27:13.66#ibcon#ireg 7 cls_cnt 0 2006.173.03:27:13.66#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.03:27:13.78#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.03:27:13.78#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.03:27:13.78#ibcon#enter wrdev, iclass 34, count 0 2006.173.03:27:13.78#ibcon#first serial, iclass 34, count 0 2006.173.03:27:13.78#ibcon#enter sib2, iclass 34, count 0 2006.173.03:27:13.78#ibcon#flushed, iclass 34, count 0 2006.173.03:27:13.78#ibcon#about to write, iclass 34, count 0 2006.173.03:27:13.78#ibcon#wrote, iclass 34, count 0 2006.173.03:27:13.78#ibcon#about to read 3, iclass 34, count 0 2006.173.03:27:13.80#ibcon#read 3, iclass 34, count 0 2006.173.03:27:13.80#ibcon#about to read 4, iclass 34, count 0 2006.173.03:27:13.80#ibcon#read 4, iclass 34, count 0 2006.173.03:27:13.80#ibcon#about to read 5, iclass 34, count 0 2006.173.03:27:13.80#ibcon#read 5, iclass 34, count 0 2006.173.03:27:13.80#ibcon#about to read 6, iclass 34, count 0 2006.173.03:27:13.80#ibcon#read 6, iclass 34, count 0 2006.173.03:27:13.80#ibcon#end of sib2, iclass 34, count 0 2006.173.03:27:13.80#ibcon#*mode == 0, iclass 34, count 0 2006.173.03:27:13.80#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.03:27:13.80#ibcon#[25=USB\r\n] 2006.173.03:27:13.80#ibcon#*before write, iclass 34, count 0 2006.173.03:27:13.80#ibcon#enter sib2, iclass 34, count 0 2006.173.03:27:13.80#ibcon#flushed, iclass 34, count 0 2006.173.03:27:13.80#ibcon#about to write, iclass 34, count 0 2006.173.03:27:13.80#ibcon#wrote, iclass 34, count 0 2006.173.03:27:13.80#ibcon#about to read 3, iclass 34, count 0 2006.173.03:27:13.83#ibcon#read 3, iclass 34, count 0 2006.173.03:27:13.83#ibcon#about to read 4, iclass 34, count 0 2006.173.03:27:13.83#ibcon#read 4, iclass 34, count 0 2006.173.03:27:13.83#ibcon#about to read 5, iclass 34, count 0 2006.173.03:27:13.83#ibcon#read 5, iclass 34, count 0 2006.173.03:27:13.83#ibcon#about to read 6, iclass 34, count 0 2006.173.03:27:13.83#ibcon#read 6, iclass 34, count 0 2006.173.03:27:13.83#ibcon#end of sib2, iclass 34, count 0 2006.173.03:27:13.83#ibcon#*after write, iclass 34, count 0 2006.173.03:27:13.83#ibcon#*before return 0, iclass 34, count 0 2006.173.03:27:13.83#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.03:27:13.83#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.03:27:13.83#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.03:27:13.83#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.03:27:13.83$vck44/valo=8,884.99 2006.173.03:27:13.83#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.03:27:13.83#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.03:27:13.83#ibcon#ireg 17 cls_cnt 0 2006.173.03:27:13.83#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.03:27:13.83#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.03:27:13.83#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.03:27:13.83#ibcon#enter wrdev, iclass 36, count 0 2006.173.03:27:13.83#ibcon#first serial, iclass 36, count 0 2006.173.03:27:13.83#ibcon#enter sib2, iclass 36, count 0 2006.173.03:27:13.83#ibcon#flushed, iclass 36, count 0 2006.173.03:27:13.83#ibcon#about to write, iclass 36, count 0 2006.173.03:27:13.83#ibcon#wrote, iclass 36, count 0 2006.173.03:27:13.83#ibcon#about to read 3, iclass 36, count 0 2006.173.03:27:13.85#ibcon#read 3, iclass 36, count 0 2006.173.03:27:13.85#ibcon#about to read 4, iclass 36, count 0 2006.173.03:27:13.85#ibcon#read 4, iclass 36, count 0 2006.173.03:27:13.85#ibcon#about to read 5, iclass 36, count 0 2006.173.03:27:13.85#ibcon#read 5, iclass 36, count 0 2006.173.03:27:13.85#ibcon#about to read 6, iclass 36, count 0 2006.173.03:27:13.85#ibcon#read 6, iclass 36, count 0 2006.173.03:27:13.85#ibcon#end of sib2, iclass 36, count 0 2006.173.03:27:13.85#ibcon#*mode == 0, iclass 36, count 0 2006.173.03:27:13.85#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.03:27:13.85#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.03:27:13.85#ibcon#*before write, iclass 36, count 0 2006.173.03:27:13.85#ibcon#enter sib2, iclass 36, count 0 2006.173.03:27:13.85#ibcon#flushed, iclass 36, count 0 2006.173.03:27:13.85#ibcon#about to write, iclass 36, count 0 2006.173.03:27:13.85#ibcon#wrote, iclass 36, count 0 2006.173.03:27:13.85#ibcon#about to read 3, iclass 36, count 0 2006.173.03:27:13.89#ibcon#read 3, iclass 36, count 0 2006.173.03:27:13.89#ibcon#about to read 4, iclass 36, count 0 2006.173.03:27:13.89#ibcon#read 4, iclass 36, count 0 2006.173.03:27:13.89#ibcon#about to read 5, iclass 36, count 0 2006.173.03:27:13.89#ibcon#read 5, iclass 36, count 0 2006.173.03:27:13.89#ibcon#about to read 6, iclass 36, count 0 2006.173.03:27:13.89#ibcon#read 6, iclass 36, count 0 2006.173.03:27:13.89#ibcon#end of sib2, iclass 36, count 0 2006.173.03:27:13.89#ibcon#*after write, iclass 36, count 0 2006.173.03:27:13.89#ibcon#*before return 0, iclass 36, count 0 2006.173.03:27:13.89#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.03:27:13.89#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.03:27:13.89#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.03:27:13.89#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.03:27:13.89$vck44/va=8,4 2006.173.03:27:13.89#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.03:27:13.89#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.03:27:13.89#ibcon#ireg 11 cls_cnt 2 2006.173.03:27:13.89#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.03:27:13.95#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.03:27:13.95#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.03:27:13.95#ibcon#enter wrdev, iclass 38, count 2 2006.173.03:27:13.95#ibcon#first serial, iclass 38, count 2 2006.173.03:27:13.95#ibcon#enter sib2, iclass 38, count 2 2006.173.03:27:13.95#ibcon#flushed, iclass 38, count 2 2006.173.03:27:13.95#ibcon#about to write, iclass 38, count 2 2006.173.03:27:13.95#ibcon#wrote, iclass 38, count 2 2006.173.03:27:13.95#ibcon#about to read 3, iclass 38, count 2 2006.173.03:27:13.97#ibcon#read 3, iclass 38, count 2 2006.173.03:27:13.97#ibcon#about to read 4, iclass 38, count 2 2006.173.03:27:13.97#ibcon#read 4, iclass 38, count 2 2006.173.03:27:13.97#ibcon#about to read 5, iclass 38, count 2 2006.173.03:27:13.97#ibcon#read 5, iclass 38, count 2 2006.173.03:27:13.97#ibcon#about to read 6, iclass 38, count 2 2006.173.03:27:13.97#ibcon#read 6, iclass 38, count 2 2006.173.03:27:13.97#ibcon#end of sib2, iclass 38, count 2 2006.173.03:27:13.97#ibcon#*mode == 0, iclass 38, count 2 2006.173.03:27:13.97#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.03:27:13.97#ibcon#[25=AT08-04\r\n] 2006.173.03:27:13.97#ibcon#*before write, iclass 38, count 2 2006.173.03:27:13.97#ibcon#enter sib2, iclass 38, count 2 2006.173.03:27:13.97#ibcon#flushed, iclass 38, count 2 2006.173.03:27:13.97#ibcon#about to write, iclass 38, count 2 2006.173.03:27:13.97#ibcon#wrote, iclass 38, count 2 2006.173.03:27:13.97#ibcon#about to read 3, iclass 38, count 2 2006.173.03:27:14.00#ibcon#read 3, iclass 38, count 2 2006.173.03:27:14.00#ibcon#about to read 4, iclass 38, count 2 2006.173.03:27:14.00#ibcon#read 4, iclass 38, count 2 2006.173.03:27:14.00#ibcon#about to read 5, iclass 38, count 2 2006.173.03:27:14.00#ibcon#read 5, iclass 38, count 2 2006.173.03:27:14.00#ibcon#about to read 6, iclass 38, count 2 2006.173.03:27:14.00#ibcon#read 6, iclass 38, count 2 2006.173.03:27:14.00#ibcon#end of sib2, iclass 38, count 2 2006.173.03:27:14.00#ibcon#*after write, iclass 38, count 2 2006.173.03:27:14.00#ibcon#*before return 0, iclass 38, count 2 2006.173.03:27:14.00#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.03:27:14.00#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.03:27:14.00#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.03:27:14.00#ibcon#ireg 7 cls_cnt 0 2006.173.03:27:14.00#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.03:27:14.12#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.03:27:14.12#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.03:27:14.12#ibcon#enter wrdev, iclass 38, count 0 2006.173.03:27:14.12#ibcon#first serial, iclass 38, count 0 2006.173.03:27:14.12#ibcon#enter sib2, iclass 38, count 0 2006.173.03:27:14.12#ibcon#flushed, iclass 38, count 0 2006.173.03:27:14.12#ibcon#about to write, iclass 38, count 0 2006.173.03:27:14.12#ibcon#wrote, iclass 38, count 0 2006.173.03:27:14.12#ibcon#about to read 3, iclass 38, count 0 2006.173.03:27:14.14#ibcon#read 3, iclass 38, count 0 2006.173.03:27:14.14#ibcon#about to read 4, iclass 38, count 0 2006.173.03:27:14.14#ibcon#read 4, iclass 38, count 0 2006.173.03:27:14.14#ibcon#about to read 5, iclass 38, count 0 2006.173.03:27:14.14#ibcon#read 5, iclass 38, count 0 2006.173.03:27:14.14#ibcon#about to read 6, iclass 38, count 0 2006.173.03:27:14.14#ibcon#read 6, iclass 38, count 0 2006.173.03:27:14.14#ibcon#end of sib2, iclass 38, count 0 2006.173.03:27:14.14#ibcon#*mode == 0, iclass 38, count 0 2006.173.03:27:14.14#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.03:27:14.14#ibcon#[25=USB\r\n] 2006.173.03:27:14.14#ibcon#*before write, iclass 38, count 0 2006.173.03:27:14.14#ibcon#enter sib2, iclass 38, count 0 2006.173.03:27:14.14#ibcon#flushed, iclass 38, count 0 2006.173.03:27:14.14#ibcon#about to write, iclass 38, count 0 2006.173.03:27:14.14#ibcon#wrote, iclass 38, count 0 2006.173.03:27:14.14#ibcon#about to read 3, iclass 38, count 0 2006.173.03:27:14.17#ibcon#read 3, iclass 38, count 0 2006.173.03:27:14.17#ibcon#about to read 4, iclass 38, count 0 2006.173.03:27:14.17#ibcon#read 4, iclass 38, count 0 2006.173.03:27:14.17#ibcon#about to read 5, iclass 38, count 0 2006.173.03:27:14.17#ibcon#read 5, iclass 38, count 0 2006.173.03:27:14.17#ibcon#about to read 6, iclass 38, count 0 2006.173.03:27:14.17#ibcon#read 6, iclass 38, count 0 2006.173.03:27:14.17#ibcon#end of sib2, iclass 38, count 0 2006.173.03:27:14.17#ibcon#*after write, iclass 38, count 0 2006.173.03:27:14.17#ibcon#*before return 0, iclass 38, count 0 2006.173.03:27:14.17#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.03:27:14.17#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.03:27:14.17#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.03:27:14.17#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.03:27:14.17$vck44/vblo=1,629.99 2006.173.03:27:14.17#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.03:27:14.17#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.03:27:14.17#ibcon#ireg 17 cls_cnt 0 2006.173.03:27:14.17#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.03:27:14.17#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.03:27:14.17#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.03:27:14.17#ibcon#enter wrdev, iclass 40, count 0 2006.173.03:27:14.17#ibcon#first serial, iclass 40, count 0 2006.173.03:27:14.17#ibcon#enter sib2, iclass 40, count 0 2006.173.03:27:14.17#ibcon#flushed, iclass 40, count 0 2006.173.03:27:14.17#ibcon#about to write, iclass 40, count 0 2006.173.03:27:14.17#ibcon#wrote, iclass 40, count 0 2006.173.03:27:14.17#ibcon#about to read 3, iclass 40, count 0 2006.173.03:27:14.19#ibcon#read 3, iclass 40, count 0 2006.173.03:27:14.19#ibcon#about to read 4, iclass 40, count 0 2006.173.03:27:14.19#ibcon#read 4, iclass 40, count 0 2006.173.03:27:14.19#ibcon#about to read 5, iclass 40, count 0 2006.173.03:27:14.19#ibcon#read 5, iclass 40, count 0 2006.173.03:27:14.19#ibcon#about to read 6, iclass 40, count 0 2006.173.03:27:14.19#ibcon#read 6, iclass 40, count 0 2006.173.03:27:14.19#ibcon#end of sib2, iclass 40, count 0 2006.173.03:27:14.19#ibcon#*mode == 0, iclass 40, count 0 2006.173.03:27:14.19#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.03:27:14.19#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.03:27:14.19#ibcon#*before write, iclass 40, count 0 2006.173.03:27:14.19#ibcon#enter sib2, iclass 40, count 0 2006.173.03:27:14.19#ibcon#flushed, iclass 40, count 0 2006.173.03:27:14.19#ibcon#about to write, iclass 40, count 0 2006.173.03:27:14.19#ibcon#wrote, iclass 40, count 0 2006.173.03:27:14.19#ibcon#about to read 3, iclass 40, count 0 2006.173.03:27:14.23#ibcon#read 3, iclass 40, count 0 2006.173.03:27:14.23#ibcon#about to read 4, iclass 40, count 0 2006.173.03:27:14.23#ibcon#read 4, iclass 40, count 0 2006.173.03:27:14.23#ibcon#about to read 5, iclass 40, count 0 2006.173.03:27:14.23#ibcon#read 5, iclass 40, count 0 2006.173.03:27:14.23#ibcon#about to read 6, iclass 40, count 0 2006.173.03:27:14.23#ibcon#read 6, iclass 40, count 0 2006.173.03:27:14.23#ibcon#end of sib2, iclass 40, count 0 2006.173.03:27:14.23#ibcon#*after write, iclass 40, count 0 2006.173.03:27:14.23#ibcon#*before return 0, iclass 40, count 0 2006.173.03:27:14.23#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.03:27:14.23#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.03:27:14.23#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.03:27:14.23#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.03:27:14.23$vck44/vb=1,4 2006.173.03:27:14.23#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.03:27:14.23#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.03:27:14.23#ibcon#ireg 11 cls_cnt 2 2006.173.03:27:14.23#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.03:27:14.23#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.03:27:14.23#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.03:27:14.23#ibcon#enter wrdev, iclass 4, count 2 2006.173.03:27:14.23#ibcon#first serial, iclass 4, count 2 2006.173.03:27:14.23#ibcon#enter sib2, iclass 4, count 2 2006.173.03:27:14.23#ibcon#flushed, iclass 4, count 2 2006.173.03:27:14.23#ibcon#about to write, iclass 4, count 2 2006.173.03:27:14.23#ibcon#wrote, iclass 4, count 2 2006.173.03:27:14.23#ibcon#about to read 3, iclass 4, count 2 2006.173.03:27:14.25#ibcon#read 3, iclass 4, count 2 2006.173.03:27:14.25#ibcon#about to read 4, iclass 4, count 2 2006.173.03:27:14.25#ibcon#read 4, iclass 4, count 2 2006.173.03:27:14.25#ibcon#about to read 5, iclass 4, count 2 2006.173.03:27:14.25#ibcon#read 5, iclass 4, count 2 2006.173.03:27:14.25#ibcon#about to read 6, iclass 4, count 2 2006.173.03:27:14.25#ibcon#read 6, iclass 4, count 2 2006.173.03:27:14.25#ibcon#end of sib2, iclass 4, count 2 2006.173.03:27:14.25#ibcon#*mode == 0, iclass 4, count 2 2006.173.03:27:14.25#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.03:27:14.25#ibcon#[27=AT01-04\r\n] 2006.173.03:27:14.25#ibcon#*before write, iclass 4, count 2 2006.173.03:27:14.25#ibcon#enter sib2, iclass 4, count 2 2006.173.03:27:14.25#ibcon#flushed, iclass 4, count 2 2006.173.03:27:14.25#ibcon#about to write, iclass 4, count 2 2006.173.03:27:14.25#ibcon#wrote, iclass 4, count 2 2006.173.03:27:14.25#ibcon#about to read 3, iclass 4, count 2 2006.173.03:27:14.28#ibcon#read 3, iclass 4, count 2 2006.173.03:27:14.28#ibcon#about to read 4, iclass 4, count 2 2006.173.03:27:14.28#ibcon#read 4, iclass 4, count 2 2006.173.03:27:14.28#ibcon#about to read 5, iclass 4, count 2 2006.173.03:27:14.28#ibcon#read 5, iclass 4, count 2 2006.173.03:27:14.28#ibcon#about to read 6, iclass 4, count 2 2006.173.03:27:14.28#ibcon#read 6, iclass 4, count 2 2006.173.03:27:14.28#ibcon#end of sib2, iclass 4, count 2 2006.173.03:27:14.28#ibcon#*after write, iclass 4, count 2 2006.173.03:27:14.28#ibcon#*before return 0, iclass 4, count 2 2006.173.03:27:14.28#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.03:27:14.28#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.03:27:14.28#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.03:27:14.28#ibcon#ireg 7 cls_cnt 0 2006.173.03:27:14.28#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.03:27:14.40#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.03:27:14.40#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.03:27:14.40#ibcon#enter wrdev, iclass 4, count 0 2006.173.03:27:14.40#ibcon#first serial, iclass 4, count 0 2006.173.03:27:14.40#ibcon#enter sib2, iclass 4, count 0 2006.173.03:27:14.40#ibcon#flushed, iclass 4, count 0 2006.173.03:27:14.40#ibcon#about to write, iclass 4, count 0 2006.173.03:27:14.40#ibcon#wrote, iclass 4, count 0 2006.173.03:27:14.40#ibcon#about to read 3, iclass 4, count 0 2006.173.03:27:14.42#ibcon#read 3, iclass 4, count 0 2006.173.03:27:14.42#ibcon#about to read 4, iclass 4, count 0 2006.173.03:27:14.42#ibcon#read 4, iclass 4, count 0 2006.173.03:27:14.42#ibcon#about to read 5, iclass 4, count 0 2006.173.03:27:14.42#ibcon#read 5, iclass 4, count 0 2006.173.03:27:14.42#ibcon#about to read 6, iclass 4, count 0 2006.173.03:27:14.42#ibcon#read 6, iclass 4, count 0 2006.173.03:27:14.42#ibcon#end of sib2, iclass 4, count 0 2006.173.03:27:14.42#ibcon#*mode == 0, iclass 4, count 0 2006.173.03:27:14.42#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.03:27:14.42#ibcon#[27=USB\r\n] 2006.173.03:27:14.42#ibcon#*before write, iclass 4, count 0 2006.173.03:27:14.42#ibcon#enter sib2, iclass 4, count 0 2006.173.03:27:14.42#ibcon#flushed, iclass 4, count 0 2006.173.03:27:14.42#ibcon#about to write, iclass 4, count 0 2006.173.03:27:14.42#ibcon#wrote, iclass 4, count 0 2006.173.03:27:14.42#ibcon#about to read 3, iclass 4, count 0 2006.173.03:27:14.45#ibcon#read 3, iclass 4, count 0 2006.173.03:27:14.45#ibcon#about to read 4, iclass 4, count 0 2006.173.03:27:14.45#ibcon#read 4, iclass 4, count 0 2006.173.03:27:14.45#ibcon#about to read 5, iclass 4, count 0 2006.173.03:27:14.45#ibcon#read 5, iclass 4, count 0 2006.173.03:27:14.45#ibcon#about to read 6, iclass 4, count 0 2006.173.03:27:14.45#ibcon#read 6, iclass 4, count 0 2006.173.03:27:14.45#ibcon#end of sib2, iclass 4, count 0 2006.173.03:27:14.45#ibcon#*after write, iclass 4, count 0 2006.173.03:27:14.45#ibcon#*before return 0, iclass 4, count 0 2006.173.03:27:14.45#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.03:27:14.45#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.03:27:14.45#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.03:27:14.45#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.03:27:14.45$vck44/vblo=2,634.99 2006.173.03:27:14.45#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.03:27:14.45#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.03:27:14.45#ibcon#ireg 17 cls_cnt 0 2006.173.03:27:14.45#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.03:27:14.45#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.03:27:14.45#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.03:27:14.45#ibcon#enter wrdev, iclass 6, count 0 2006.173.03:27:14.45#ibcon#first serial, iclass 6, count 0 2006.173.03:27:14.45#ibcon#enter sib2, iclass 6, count 0 2006.173.03:27:14.45#ibcon#flushed, iclass 6, count 0 2006.173.03:27:14.45#ibcon#about to write, iclass 6, count 0 2006.173.03:27:14.45#ibcon#wrote, iclass 6, count 0 2006.173.03:27:14.45#ibcon#about to read 3, iclass 6, count 0 2006.173.03:27:14.47#ibcon#read 3, iclass 6, count 0 2006.173.03:27:14.47#ibcon#about to read 4, iclass 6, count 0 2006.173.03:27:14.47#ibcon#read 4, iclass 6, count 0 2006.173.03:27:14.47#ibcon#about to read 5, iclass 6, count 0 2006.173.03:27:14.47#ibcon#read 5, iclass 6, count 0 2006.173.03:27:14.47#ibcon#about to read 6, iclass 6, count 0 2006.173.03:27:14.47#ibcon#read 6, iclass 6, count 0 2006.173.03:27:14.47#ibcon#end of sib2, iclass 6, count 0 2006.173.03:27:14.47#ibcon#*mode == 0, iclass 6, count 0 2006.173.03:27:14.47#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.03:27:14.47#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.03:27:14.47#ibcon#*before write, iclass 6, count 0 2006.173.03:27:14.47#ibcon#enter sib2, iclass 6, count 0 2006.173.03:27:14.47#ibcon#flushed, iclass 6, count 0 2006.173.03:27:14.47#ibcon#about to write, iclass 6, count 0 2006.173.03:27:14.47#ibcon#wrote, iclass 6, count 0 2006.173.03:27:14.47#ibcon#about to read 3, iclass 6, count 0 2006.173.03:27:14.51#ibcon#read 3, iclass 6, count 0 2006.173.03:27:14.51#ibcon#about to read 4, iclass 6, count 0 2006.173.03:27:14.51#ibcon#read 4, iclass 6, count 0 2006.173.03:27:14.51#ibcon#about to read 5, iclass 6, count 0 2006.173.03:27:14.51#ibcon#read 5, iclass 6, count 0 2006.173.03:27:14.51#ibcon#about to read 6, iclass 6, count 0 2006.173.03:27:14.51#ibcon#read 6, iclass 6, count 0 2006.173.03:27:14.51#ibcon#end of sib2, iclass 6, count 0 2006.173.03:27:14.51#ibcon#*after write, iclass 6, count 0 2006.173.03:27:14.51#ibcon#*before return 0, iclass 6, count 0 2006.173.03:27:14.51#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.03:27:14.51#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.03:27:14.51#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.03:27:14.51#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.03:27:14.51$vck44/vb=2,4 2006.173.03:27:14.51#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.03:27:14.51#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.03:27:14.51#ibcon#ireg 11 cls_cnt 2 2006.173.03:27:14.51#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.03:27:14.57#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.03:27:14.57#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.03:27:14.57#ibcon#enter wrdev, iclass 10, count 2 2006.173.03:27:14.57#ibcon#first serial, iclass 10, count 2 2006.173.03:27:14.57#ibcon#enter sib2, iclass 10, count 2 2006.173.03:27:14.57#ibcon#flushed, iclass 10, count 2 2006.173.03:27:14.57#ibcon#about to write, iclass 10, count 2 2006.173.03:27:14.57#ibcon#wrote, iclass 10, count 2 2006.173.03:27:14.57#ibcon#about to read 3, iclass 10, count 2 2006.173.03:27:14.59#ibcon#read 3, iclass 10, count 2 2006.173.03:27:14.59#ibcon#about to read 4, iclass 10, count 2 2006.173.03:27:14.59#ibcon#read 4, iclass 10, count 2 2006.173.03:27:14.59#ibcon#about to read 5, iclass 10, count 2 2006.173.03:27:14.59#ibcon#read 5, iclass 10, count 2 2006.173.03:27:14.59#ibcon#about to read 6, iclass 10, count 2 2006.173.03:27:14.59#ibcon#read 6, iclass 10, count 2 2006.173.03:27:14.59#ibcon#end of sib2, iclass 10, count 2 2006.173.03:27:14.59#ibcon#*mode == 0, iclass 10, count 2 2006.173.03:27:14.59#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.03:27:14.59#ibcon#[27=AT02-04\r\n] 2006.173.03:27:14.59#ibcon#*before write, iclass 10, count 2 2006.173.03:27:14.59#ibcon#enter sib2, iclass 10, count 2 2006.173.03:27:14.59#ibcon#flushed, iclass 10, count 2 2006.173.03:27:14.59#ibcon#about to write, iclass 10, count 2 2006.173.03:27:14.59#ibcon#wrote, iclass 10, count 2 2006.173.03:27:14.59#ibcon#about to read 3, iclass 10, count 2 2006.173.03:27:14.62#ibcon#read 3, iclass 10, count 2 2006.173.03:27:14.62#ibcon#about to read 4, iclass 10, count 2 2006.173.03:27:14.62#ibcon#read 4, iclass 10, count 2 2006.173.03:27:14.62#ibcon#about to read 5, iclass 10, count 2 2006.173.03:27:14.62#ibcon#read 5, iclass 10, count 2 2006.173.03:27:14.62#ibcon#about to read 6, iclass 10, count 2 2006.173.03:27:14.62#ibcon#read 6, iclass 10, count 2 2006.173.03:27:14.62#ibcon#end of sib2, iclass 10, count 2 2006.173.03:27:14.62#ibcon#*after write, iclass 10, count 2 2006.173.03:27:14.62#ibcon#*before return 0, iclass 10, count 2 2006.173.03:27:14.62#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.03:27:14.62#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.03:27:14.62#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.03:27:14.62#ibcon#ireg 7 cls_cnt 0 2006.173.03:27:14.62#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.03:27:14.74#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.03:27:14.74#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.03:27:14.74#ibcon#enter wrdev, iclass 10, count 0 2006.173.03:27:14.74#ibcon#first serial, iclass 10, count 0 2006.173.03:27:14.74#ibcon#enter sib2, iclass 10, count 0 2006.173.03:27:14.74#ibcon#flushed, iclass 10, count 0 2006.173.03:27:14.74#ibcon#about to write, iclass 10, count 0 2006.173.03:27:14.74#ibcon#wrote, iclass 10, count 0 2006.173.03:27:14.74#ibcon#about to read 3, iclass 10, count 0 2006.173.03:27:14.76#ibcon#read 3, iclass 10, count 0 2006.173.03:27:14.76#ibcon#about to read 4, iclass 10, count 0 2006.173.03:27:14.76#ibcon#read 4, iclass 10, count 0 2006.173.03:27:14.76#ibcon#about to read 5, iclass 10, count 0 2006.173.03:27:14.76#ibcon#read 5, iclass 10, count 0 2006.173.03:27:14.76#ibcon#about to read 6, iclass 10, count 0 2006.173.03:27:14.76#ibcon#read 6, iclass 10, count 0 2006.173.03:27:14.76#ibcon#end of sib2, iclass 10, count 0 2006.173.03:27:14.76#ibcon#*mode == 0, iclass 10, count 0 2006.173.03:27:14.76#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.03:27:14.76#ibcon#[27=USB\r\n] 2006.173.03:27:14.76#ibcon#*before write, iclass 10, count 0 2006.173.03:27:14.76#ibcon#enter sib2, iclass 10, count 0 2006.173.03:27:14.76#ibcon#flushed, iclass 10, count 0 2006.173.03:27:14.76#ibcon#about to write, iclass 10, count 0 2006.173.03:27:14.76#ibcon#wrote, iclass 10, count 0 2006.173.03:27:14.76#ibcon#about to read 3, iclass 10, count 0 2006.173.03:27:14.79#ibcon#read 3, iclass 10, count 0 2006.173.03:27:14.79#ibcon#about to read 4, iclass 10, count 0 2006.173.03:27:14.79#ibcon#read 4, iclass 10, count 0 2006.173.03:27:14.79#ibcon#about to read 5, iclass 10, count 0 2006.173.03:27:14.79#ibcon#read 5, iclass 10, count 0 2006.173.03:27:14.79#ibcon#about to read 6, iclass 10, count 0 2006.173.03:27:14.79#ibcon#read 6, iclass 10, count 0 2006.173.03:27:14.79#ibcon#end of sib2, iclass 10, count 0 2006.173.03:27:14.79#ibcon#*after write, iclass 10, count 0 2006.173.03:27:14.79#ibcon#*before return 0, iclass 10, count 0 2006.173.03:27:14.79#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.03:27:14.79#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.03:27:14.79#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.03:27:14.79#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.03:27:14.79$vck44/vblo=3,649.99 2006.173.03:27:14.79#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.03:27:14.79#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.03:27:14.79#ibcon#ireg 17 cls_cnt 0 2006.173.03:27:14.79#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.03:27:14.79#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.03:27:14.79#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.03:27:14.79#ibcon#enter wrdev, iclass 12, count 0 2006.173.03:27:14.79#ibcon#first serial, iclass 12, count 0 2006.173.03:27:14.79#ibcon#enter sib2, iclass 12, count 0 2006.173.03:27:14.79#ibcon#flushed, iclass 12, count 0 2006.173.03:27:14.79#ibcon#about to write, iclass 12, count 0 2006.173.03:27:14.79#ibcon#wrote, iclass 12, count 0 2006.173.03:27:14.79#ibcon#about to read 3, iclass 12, count 0 2006.173.03:27:14.81#ibcon#read 3, iclass 12, count 0 2006.173.03:27:14.81#ibcon#about to read 4, iclass 12, count 0 2006.173.03:27:14.81#ibcon#read 4, iclass 12, count 0 2006.173.03:27:14.81#ibcon#about to read 5, iclass 12, count 0 2006.173.03:27:14.81#ibcon#read 5, iclass 12, count 0 2006.173.03:27:14.81#ibcon#about to read 6, iclass 12, count 0 2006.173.03:27:14.81#ibcon#read 6, iclass 12, count 0 2006.173.03:27:14.81#ibcon#end of sib2, iclass 12, count 0 2006.173.03:27:14.81#ibcon#*mode == 0, iclass 12, count 0 2006.173.03:27:14.81#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.03:27:14.81#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.03:27:14.81#ibcon#*before write, iclass 12, count 0 2006.173.03:27:14.81#ibcon#enter sib2, iclass 12, count 0 2006.173.03:27:14.81#ibcon#flushed, iclass 12, count 0 2006.173.03:27:14.81#ibcon#about to write, iclass 12, count 0 2006.173.03:27:14.81#ibcon#wrote, iclass 12, count 0 2006.173.03:27:14.81#ibcon#about to read 3, iclass 12, count 0 2006.173.03:27:14.85#ibcon#read 3, iclass 12, count 0 2006.173.03:27:14.85#ibcon#about to read 4, iclass 12, count 0 2006.173.03:27:14.85#ibcon#read 4, iclass 12, count 0 2006.173.03:27:14.85#ibcon#about to read 5, iclass 12, count 0 2006.173.03:27:14.85#ibcon#read 5, iclass 12, count 0 2006.173.03:27:14.85#ibcon#about to read 6, iclass 12, count 0 2006.173.03:27:14.85#ibcon#read 6, iclass 12, count 0 2006.173.03:27:14.85#ibcon#end of sib2, iclass 12, count 0 2006.173.03:27:14.85#ibcon#*after write, iclass 12, count 0 2006.173.03:27:14.85#ibcon#*before return 0, iclass 12, count 0 2006.173.03:27:14.85#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.03:27:14.85#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.03:27:14.85#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.03:27:14.85#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.03:27:14.85$vck44/vb=3,4 2006.173.03:27:14.85#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.03:27:14.85#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.03:27:14.85#ibcon#ireg 11 cls_cnt 2 2006.173.03:27:14.85#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.03:27:14.91#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.03:27:14.91#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.03:27:14.91#ibcon#enter wrdev, iclass 14, count 2 2006.173.03:27:14.91#ibcon#first serial, iclass 14, count 2 2006.173.03:27:14.91#ibcon#enter sib2, iclass 14, count 2 2006.173.03:27:14.91#ibcon#flushed, iclass 14, count 2 2006.173.03:27:14.91#ibcon#about to write, iclass 14, count 2 2006.173.03:27:14.91#ibcon#wrote, iclass 14, count 2 2006.173.03:27:14.91#ibcon#about to read 3, iclass 14, count 2 2006.173.03:27:14.93#ibcon#read 3, iclass 14, count 2 2006.173.03:27:14.93#ibcon#about to read 4, iclass 14, count 2 2006.173.03:27:14.93#ibcon#read 4, iclass 14, count 2 2006.173.03:27:14.93#ibcon#about to read 5, iclass 14, count 2 2006.173.03:27:14.93#ibcon#read 5, iclass 14, count 2 2006.173.03:27:14.93#ibcon#about to read 6, iclass 14, count 2 2006.173.03:27:14.93#ibcon#read 6, iclass 14, count 2 2006.173.03:27:14.93#ibcon#end of sib2, iclass 14, count 2 2006.173.03:27:14.93#ibcon#*mode == 0, iclass 14, count 2 2006.173.03:27:14.93#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.03:27:14.93#ibcon#[27=AT03-04\r\n] 2006.173.03:27:14.93#ibcon#*before write, iclass 14, count 2 2006.173.03:27:14.93#ibcon#enter sib2, iclass 14, count 2 2006.173.03:27:14.93#ibcon#flushed, iclass 14, count 2 2006.173.03:27:14.93#ibcon#about to write, iclass 14, count 2 2006.173.03:27:14.93#ibcon#wrote, iclass 14, count 2 2006.173.03:27:14.93#ibcon#about to read 3, iclass 14, count 2 2006.173.03:27:14.96#ibcon#read 3, iclass 14, count 2 2006.173.03:27:14.96#ibcon#about to read 4, iclass 14, count 2 2006.173.03:27:14.96#ibcon#read 4, iclass 14, count 2 2006.173.03:27:14.96#ibcon#about to read 5, iclass 14, count 2 2006.173.03:27:14.96#ibcon#read 5, iclass 14, count 2 2006.173.03:27:14.96#ibcon#about to read 6, iclass 14, count 2 2006.173.03:27:14.96#ibcon#read 6, iclass 14, count 2 2006.173.03:27:14.96#ibcon#end of sib2, iclass 14, count 2 2006.173.03:27:14.96#ibcon#*after write, iclass 14, count 2 2006.173.03:27:14.96#ibcon#*before return 0, iclass 14, count 2 2006.173.03:27:14.96#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.03:27:14.96#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.03:27:14.96#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.03:27:14.96#ibcon#ireg 7 cls_cnt 0 2006.173.03:27:14.96#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.03:27:15.08#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.03:27:15.08#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.03:27:15.08#ibcon#enter wrdev, iclass 14, count 0 2006.173.03:27:15.08#ibcon#first serial, iclass 14, count 0 2006.173.03:27:15.08#ibcon#enter sib2, iclass 14, count 0 2006.173.03:27:15.08#ibcon#flushed, iclass 14, count 0 2006.173.03:27:15.08#ibcon#about to write, iclass 14, count 0 2006.173.03:27:15.08#ibcon#wrote, iclass 14, count 0 2006.173.03:27:15.08#ibcon#about to read 3, iclass 14, count 0 2006.173.03:27:15.10#ibcon#read 3, iclass 14, count 0 2006.173.03:27:15.10#ibcon#about to read 4, iclass 14, count 0 2006.173.03:27:15.10#ibcon#read 4, iclass 14, count 0 2006.173.03:27:15.10#ibcon#about to read 5, iclass 14, count 0 2006.173.03:27:15.10#ibcon#read 5, iclass 14, count 0 2006.173.03:27:15.10#ibcon#about to read 6, iclass 14, count 0 2006.173.03:27:15.10#ibcon#read 6, iclass 14, count 0 2006.173.03:27:15.10#ibcon#end of sib2, iclass 14, count 0 2006.173.03:27:15.10#ibcon#*mode == 0, iclass 14, count 0 2006.173.03:27:15.10#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.03:27:15.10#ibcon#[27=USB\r\n] 2006.173.03:27:15.10#ibcon#*before write, iclass 14, count 0 2006.173.03:27:15.10#ibcon#enter sib2, iclass 14, count 0 2006.173.03:27:15.10#ibcon#flushed, iclass 14, count 0 2006.173.03:27:15.10#ibcon#about to write, iclass 14, count 0 2006.173.03:27:15.10#ibcon#wrote, iclass 14, count 0 2006.173.03:27:15.10#ibcon#about to read 3, iclass 14, count 0 2006.173.03:27:15.13#ibcon#read 3, iclass 14, count 0 2006.173.03:27:15.13#ibcon#about to read 4, iclass 14, count 0 2006.173.03:27:15.13#ibcon#read 4, iclass 14, count 0 2006.173.03:27:15.13#ibcon#about to read 5, iclass 14, count 0 2006.173.03:27:15.13#ibcon#read 5, iclass 14, count 0 2006.173.03:27:15.13#ibcon#about to read 6, iclass 14, count 0 2006.173.03:27:15.13#ibcon#read 6, iclass 14, count 0 2006.173.03:27:15.13#ibcon#end of sib2, iclass 14, count 0 2006.173.03:27:15.13#ibcon#*after write, iclass 14, count 0 2006.173.03:27:15.13#ibcon#*before return 0, iclass 14, count 0 2006.173.03:27:15.13#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.03:27:15.13#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.03:27:15.13#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.03:27:15.13#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.03:27:15.13$vck44/vblo=4,679.99 2006.173.03:27:15.13#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.03:27:15.13#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.03:27:15.13#ibcon#ireg 17 cls_cnt 0 2006.173.03:27:15.13#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.03:27:15.13#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.03:27:15.13#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.03:27:15.13#ibcon#enter wrdev, iclass 16, count 0 2006.173.03:27:15.13#ibcon#first serial, iclass 16, count 0 2006.173.03:27:15.13#ibcon#enter sib2, iclass 16, count 0 2006.173.03:27:15.13#ibcon#flushed, iclass 16, count 0 2006.173.03:27:15.13#ibcon#about to write, iclass 16, count 0 2006.173.03:27:15.13#ibcon#wrote, iclass 16, count 0 2006.173.03:27:15.13#ibcon#about to read 3, iclass 16, count 0 2006.173.03:27:15.15#ibcon#read 3, iclass 16, count 0 2006.173.03:27:15.15#ibcon#about to read 4, iclass 16, count 0 2006.173.03:27:15.15#ibcon#read 4, iclass 16, count 0 2006.173.03:27:15.15#ibcon#about to read 5, iclass 16, count 0 2006.173.03:27:15.15#ibcon#read 5, iclass 16, count 0 2006.173.03:27:15.15#ibcon#about to read 6, iclass 16, count 0 2006.173.03:27:15.15#ibcon#read 6, iclass 16, count 0 2006.173.03:27:15.15#ibcon#end of sib2, iclass 16, count 0 2006.173.03:27:15.15#ibcon#*mode == 0, iclass 16, count 0 2006.173.03:27:15.15#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.03:27:15.15#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.03:27:15.15#ibcon#*before write, iclass 16, count 0 2006.173.03:27:15.15#ibcon#enter sib2, iclass 16, count 0 2006.173.03:27:15.15#ibcon#flushed, iclass 16, count 0 2006.173.03:27:15.15#ibcon#about to write, iclass 16, count 0 2006.173.03:27:15.15#ibcon#wrote, iclass 16, count 0 2006.173.03:27:15.15#ibcon#about to read 3, iclass 16, count 0 2006.173.03:27:15.19#ibcon#read 3, iclass 16, count 0 2006.173.03:27:15.19#ibcon#about to read 4, iclass 16, count 0 2006.173.03:27:15.19#ibcon#read 4, iclass 16, count 0 2006.173.03:27:15.19#ibcon#about to read 5, iclass 16, count 0 2006.173.03:27:15.19#ibcon#read 5, iclass 16, count 0 2006.173.03:27:15.19#ibcon#about to read 6, iclass 16, count 0 2006.173.03:27:15.19#ibcon#read 6, iclass 16, count 0 2006.173.03:27:15.19#ibcon#end of sib2, iclass 16, count 0 2006.173.03:27:15.19#ibcon#*after write, iclass 16, count 0 2006.173.03:27:15.19#ibcon#*before return 0, iclass 16, count 0 2006.173.03:27:15.19#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.03:27:15.19#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.03:27:15.19#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.03:27:15.19#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.03:27:15.19$vck44/vb=4,4 2006.173.03:27:15.19#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.03:27:15.19#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.03:27:15.19#ibcon#ireg 11 cls_cnt 2 2006.173.03:27:15.19#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.03:27:15.25#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.03:27:15.25#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.03:27:15.25#ibcon#enter wrdev, iclass 18, count 2 2006.173.03:27:15.25#ibcon#first serial, iclass 18, count 2 2006.173.03:27:15.25#ibcon#enter sib2, iclass 18, count 2 2006.173.03:27:15.25#ibcon#flushed, iclass 18, count 2 2006.173.03:27:15.25#ibcon#about to write, iclass 18, count 2 2006.173.03:27:15.25#ibcon#wrote, iclass 18, count 2 2006.173.03:27:15.25#ibcon#about to read 3, iclass 18, count 2 2006.173.03:27:15.27#ibcon#read 3, iclass 18, count 2 2006.173.03:27:15.27#ibcon#about to read 4, iclass 18, count 2 2006.173.03:27:15.27#ibcon#read 4, iclass 18, count 2 2006.173.03:27:15.27#ibcon#about to read 5, iclass 18, count 2 2006.173.03:27:15.27#ibcon#read 5, iclass 18, count 2 2006.173.03:27:15.27#ibcon#about to read 6, iclass 18, count 2 2006.173.03:27:15.27#ibcon#read 6, iclass 18, count 2 2006.173.03:27:15.27#ibcon#end of sib2, iclass 18, count 2 2006.173.03:27:15.27#ibcon#*mode == 0, iclass 18, count 2 2006.173.03:27:15.27#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.03:27:15.27#ibcon#[27=AT04-04\r\n] 2006.173.03:27:15.27#ibcon#*before write, iclass 18, count 2 2006.173.03:27:15.27#ibcon#enter sib2, iclass 18, count 2 2006.173.03:27:15.27#ibcon#flushed, iclass 18, count 2 2006.173.03:27:15.27#ibcon#about to write, iclass 18, count 2 2006.173.03:27:15.27#ibcon#wrote, iclass 18, count 2 2006.173.03:27:15.27#ibcon#about to read 3, iclass 18, count 2 2006.173.03:27:15.30#ibcon#read 3, iclass 18, count 2 2006.173.03:27:15.30#ibcon#about to read 4, iclass 18, count 2 2006.173.03:27:15.30#ibcon#read 4, iclass 18, count 2 2006.173.03:27:15.30#ibcon#about to read 5, iclass 18, count 2 2006.173.03:27:15.30#ibcon#read 5, iclass 18, count 2 2006.173.03:27:15.30#ibcon#about to read 6, iclass 18, count 2 2006.173.03:27:15.30#ibcon#read 6, iclass 18, count 2 2006.173.03:27:15.30#ibcon#end of sib2, iclass 18, count 2 2006.173.03:27:15.30#ibcon#*after write, iclass 18, count 2 2006.173.03:27:15.30#ibcon#*before return 0, iclass 18, count 2 2006.173.03:27:15.30#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.03:27:15.30#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.03:27:15.30#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.03:27:15.30#ibcon#ireg 7 cls_cnt 0 2006.173.03:27:15.30#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.03:27:15.42#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.03:27:15.42#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.03:27:15.42#ibcon#enter wrdev, iclass 18, count 0 2006.173.03:27:15.42#ibcon#first serial, iclass 18, count 0 2006.173.03:27:15.42#ibcon#enter sib2, iclass 18, count 0 2006.173.03:27:15.42#ibcon#flushed, iclass 18, count 0 2006.173.03:27:15.42#ibcon#about to write, iclass 18, count 0 2006.173.03:27:15.42#ibcon#wrote, iclass 18, count 0 2006.173.03:27:15.42#ibcon#about to read 3, iclass 18, count 0 2006.173.03:27:15.44#ibcon#read 3, iclass 18, count 0 2006.173.03:27:15.44#ibcon#about to read 4, iclass 18, count 0 2006.173.03:27:15.44#ibcon#read 4, iclass 18, count 0 2006.173.03:27:15.44#ibcon#about to read 5, iclass 18, count 0 2006.173.03:27:15.44#ibcon#read 5, iclass 18, count 0 2006.173.03:27:15.44#ibcon#about to read 6, iclass 18, count 0 2006.173.03:27:15.44#ibcon#read 6, iclass 18, count 0 2006.173.03:27:15.44#ibcon#end of sib2, iclass 18, count 0 2006.173.03:27:15.44#ibcon#*mode == 0, iclass 18, count 0 2006.173.03:27:15.44#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.03:27:15.44#ibcon#[27=USB\r\n] 2006.173.03:27:15.44#ibcon#*before write, iclass 18, count 0 2006.173.03:27:15.44#ibcon#enter sib2, iclass 18, count 0 2006.173.03:27:15.44#ibcon#flushed, iclass 18, count 0 2006.173.03:27:15.44#ibcon#about to write, iclass 18, count 0 2006.173.03:27:15.44#ibcon#wrote, iclass 18, count 0 2006.173.03:27:15.44#ibcon#about to read 3, iclass 18, count 0 2006.173.03:27:15.47#ibcon#read 3, iclass 18, count 0 2006.173.03:27:15.47#ibcon#about to read 4, iclass 18, count 0 2006.173.03:27:15.47#ibcon#read 4, iclass 18, count 0 2006.173.03:27:15.47#ibcon#about to read 5, iclass 18, count 0 2006.173.03:27:15.47#ibcon#read 5, iclass 18, count 0 2006.173.03:27:15.47#ibcon#about to read 6, iclass 18, count 0 2006.173.03:27:15.47#ibcon#read 6, iclass 18, count 0 2006.173.03:27:15.47#ibcon#end of sib2, iclass 18, count 0 2006.173.03:27:15.47#ibcon#*after write, iclass 18, count 0 2006.173.03:27:15.47#ibcon#*before return 0, iclass 18, count 0 2006.173.03:27:15.47#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.03:27:15.47#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.03:27:15.47#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.03:27:15.47#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.03:27:15.47$vck44/vblo=5,709.99 2006.173.03:27:15.47#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.03:27:15.47#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.03:27:15.47#ibcon#ireg 17 cls_cnt 0 2006.173.03:27:15.47#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.03:27:15.47#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.03:27:15.47#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.03:27:15.47#ibcon#enter wrdev, iclass 20, count 0 2006.173.03:27:15.47#ibcon#first serial, iclass 20, count 0 2006.173.03:27:15.47#ibcon#enter sib2, iclass 20, count 0 2006.173.03:27:15.47#ibcon#flushed, iclass 20, count 0 2006.173.03:27:15.47#ibcon#about to write, iclass 20, count 0 2006.173.03:27:15.47#ibcon#wrote, iclass 20, count 0 2006.173.03:27:15.47#ibcon#about to read 3, iclass 20, count 0 2006.173.03:27:15.49#ibcon#read 3, iclass 20, count 0 2006.173.03:27:15.49#ibcon#about to read 4, iclass 20, count 0 2006.173.03:27:15.49#ibcon#read 4, iclass 20, count 0 2006.173.03:27:15.49#ibcon#about to read 5, iclass 20, count 0 2006.173.03:27:15.49#ibcon#read 5, iclass 20, count 0 2006.173.03:27:15.49#ibcon#about to read 6, iclass 20, count 0 2006.173.03:27:15.49#ibcon#read 6, iclass 20, count 0 2006.173.03:27:15.49#ibcon#end of sib2, iclass 20, count 0 2006.173.03:27:15.49#ibcon#*mode == 0, iclass 20, count 0 2006.173.03:27:15.49#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.03:27:15.49#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.03:27:15.49#ibcon#*before write, iclass 20, count 0 2006.173.03:27:15.49#ibcon#enter sib2, iclass 20, count 0 2006.173.03:27:15.49#ibcon#flushed, iclass 20, count 0 2006.173.03:27:15.49#ibcon#about to write, iclass 20, count 0 2006.173.03:27:15.49#ibcon#wrote, iclass 20, count 0 2006.173.03:27:15.49#ibcon#about to read 3, iclass 20, count 0 2006.173.03:27:15.53#ibcon#read 3, iclass 20, count 0 2006.173.03:27:15.53#ibcon#about to read 4, iclass 20, count 0 2006.173.03:27:15.53#ibcon#read 4, iclass 20, count 0 2006.173.03:27:15.53#ibcon#about to read 5, iclass 20, count 0 2006.173.03:27:15.53#ibcon#read 5, iclass 20, count 0 2006.173.03:27:15.53#ibcon#about to read 6, iclass 20, count 0 2006.173.03:27:15.53#ibcon#read 6, iclass 20, count 0 2006.173.03:27:15.53#ibcon#end of sib2, iclass 20, count 0 2006.173.03:27:15.53#ibcon#*after write, iclass 20, count 0 2006.173.03:27:15.53#ibcon#*before return 0, iclass 20, count 0 2006.173.03:27:15.53#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.03:27:15.53#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.03:27:15.53#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.03:27:15.53#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.03:27:15.53$vck44/vb=5,4 2006.173.03:27:15.53#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.03:27:15.53#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.03:27:15.53#ibcon#ireg 11 cls_cnt 2 2006.173.03:27:15.53#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.03:27:15.59#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.03:27:15.59#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.03:27:15.59#ibcon#enter wrdev, iclass 22, count 2 2006.173.03:27:15.59#ibcon#first serial, iclass 22, count 2 2006.173.03:27:15.59#ibcon#enter sib2, iclass 22, count 2 2006.173.03:27:15.59#ibcon#flushed, iclass 22, count 2 2006.173.03:27:15.59#ibcon#about to write, iclass 22, count 2 2006.173.03:27:15.59#ibcon#wrote, iclass 22, count 2 2006.173.03:27:15.59#ibcon#about to read 3, iclass 22, count 2 2006.173.03:27:15.61#ibcon#read 3, iclass 22, count 2 2006.173.03:27:15.61#ibcon#about to read 4, iclass 22, count 2 2006.173.03:27:15.61#ibcon#read 4, iclass 22, count 2 2006.173.03:27:15.61#ibcon#about to read 5, iclass 22, count 2 2006.173.03:27:15.61#ibcon#read 5, iclass 22, count 2 2006.173.03:27:15.61#ibcon#about to read 6, iclass 22, count 2 2006.173.03:27:15.61#ibcon#read 6, iclass 22, count 2 2006.173.03:27:15.61#ibcon#end of sib2, iclass 22, count 2 2006.173.03:27:15.61#ibcon#*mode == 0, iclass 22, count 2 2006.173.03:27:15.61#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.03:27:15.61#ibcon#[27=AT05-04\r\n] 2006.173.03:27:15.61#ibcon#*before write, iclass 22, count 2 2006.173.03:27:15.61#ibcon#enter sib2, iclass 22, count 2 2006.173.03:27:15.61#ibcon#flushed, iclass 22, count 2 2006.173.03:27:15.61#ibcon#about to write, iclass 22, count 2 2006.173.03:27:15.61#ibcon#wrote, iclass 22, count 2 2006.173.03:27:15.61#ibcon#about to read 3, iclass 22, count 2 2006.173.03:27:15.64#ibcon#read 3, iclass 22, count 2 2006.173.03:27:15.64#ibcon#about to read 4, iclass 22, count 2 2006.173.03:27:15.64#ibcon#read 4, iclass 22, count 2 2006.173.03:27:15.64#ibcon#about to read 5, iclass 22, count 2 2006.173.03:27:15.64#ibcon#read 5, iclass 22, count 2 2006.173.03:27:15.64#ibcon#about to read 6, iclass 22, count 2 2006.173.03:27:15.64#ibcon#read 6, iclass 22, count 2 2006.173.03:27:15.64#ibcon#end of sib2, iclass 22, count 2 2006.173.03:27:15.64#ibcon#*after write, iclass 22, count 2 2006.173.03:27:15.64#ibcon#*before return 0, iclass 22, count 2 2006.173.03:27:15.64#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.03:27:15.64#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.03:27:15.64#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.03:27:15.64#ibcon#ireg 7 cls_cnt 0 2006.173.03:27:15.64#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.03:27:15.76#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.03:27:15.76#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.03:27:15.76#ibcon#enter wrdev, iclass 22, count 0 2006.173.03:27:15.76#ibcon#first serial, iclass 22, count 0 2006.173.03:27:15.76#ibcon#enter sib2, iclass 22, count 0 2006.173.03:27:15.76#ibcon#flushed, iclass 22, count 0 2006.173.03:27:15.76#ibcon#about to write, iclass 22, count 0 2006.173.03:27:15.76#ibcon#wrote, iclass 22, count 0 2006.173.03:27:15.76#ibcon#about to read 3, iclass 22, count 0 2006.173.03:27:15.78#ibcon#read 3, iclass 22, count 0 2006.173.03:27:15.78#ibcon#about to read 4, iclass 22, count 0 2006.173.03:27:15.78#ibcon#read 4, iclass 22, count 0 2006.173.03:27:15.78#ibcon#about to read 5, iclass 22, count 0 2006.173.03:27:15.78#ibcon#read 5, iclass 22, count 0 2006.173.03:27:15.78#ibcon#about to read 6, iclass 22, count 0 2006.173.03:27:15.78#ibcon#read 6, iclass 22, count 0 2006.173.03:27:15.78#ibcon#end of sib2, iclass 22, count 0 2006.173.03:27:15.78#ibcon#*mode == 0, iclass 22, count 0 2006.173.03:27:15.78#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.03:27:15.78#ibcon#[27=USB\r\n] 2006.173.03:27:15.78#ibcon#*before write, iclass 22, count 0 2006.173.03:27:15.78#ibcon#enter sib2, iclass 22, count 0 2006.173.03:27:15.78#ibcon#flushed, iclass 22, count 0 2006.173.03:27:15.78#ibcon#about to write, iclass 22, count 0 2006.173.03:27:15.78#ibcon#wrote, iclass 22, count 0 2006.173.03:27:15.78#ibcon#about to read 3, iclass 22, count 0 2006.173.03:27:15.81#ibcon#read 3, iclass 22, count 0 2006.173.03:27:15.81#ibcon#about to read 4, iclass 22, count 0 2006.173.03:27:15.81#ibcon#read 4, iclass 22, count 0 2006.173.03:27:15.81#ibcon#about to read 5, iclass 22, count 0 2006.173.03:27:15.81#ibcon#read 5, iclass 22, count 0 2006.173.03:27:15.81#ibcon#about to read 6, iclass 22, count 0 2006.173.03:27:15.81#ibcon#read 6, iclass 22, count 0 2006.173.03:27:15.81#ibcon#end of sib2, iclass 22, count 0 2006.173.03:27:15.81#ibcon#*after write, iclass 22, count 0 2006.173.03:27:15.81#ibcon#*before return 0, iclass 22, count 0 2006.173.03:27:15.81#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.03:27:15.81#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.03:27:15.81#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.03:27:15.81#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.03:27:15.81$vck44/vblo=6,719.99 2006.173.03:27:15.81#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.03:27:15.81#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.03:27:15.81#ibcon#ireg 17 cls_cnt 0 2006.173.03:27:15.81#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.03:27:15.81#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.03:27:15.81#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.03:27:15.81#ibcon#enter wrdev, iclass 24, count 0 2006.173.03:27:15.81#ibcon#first serial, iclass 24, count 0 2006.173.03:27:15.81#ibcon#enter sib2, iclass 24, count 0 2006.173.03:27:15.81#ibcon#flushed, iclass 24, count 0 2006.173.03:27:15.81#ibcon#about to write, iclass 24, count 0 2006.173.03:27:15.81#ibcon#wrote, iclass 24, count 0 2006.173.03:27:15.81#ibcon#about to read 3, iclass 24, count 0 2006.173.03:27:15.83#ibcon#read 3, iclass 24, count 0 2006.173.03:27:15.83#ibcon#about to read 4, iclass 24, count 0 2006.173.03:27:15.83#ibcon#read 4, iclass 24, count 0 2006.173.03:27:15.83#ibcon#about to read 5, iclass 24, count 0 2006.173.03:27:15.83#ibcon#read 5, iclass 24, count 0 2006.173.03:27:15.83#ibcon#about to read 6, iclass 24, count 0 2006.173.03:27:15.83#ibcon#read 6, iclass 24, count 0 2006.173.03:27:15.83#ibcon#end of sib2, iclass 24, count 0 2006.173.03:27:15.83#ibcon#*mode == 0, iclass 24, count 0 2006.173.03:27:15.83#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.03:27:15.83#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.03:27:15.83#ibcon#*before write, iclass 24, count 0 2006.173.03:27:15.83#ibcon#enter sib2, iclass 24, count 0 2006.173.03:27:15.83#ibcon#flushed, iclass 24, count 0 2006.173.03:27:15.83#ibcon#about to write, iclass 24, count 0 2006.173.03:27:15.83#ibcon#wrote, iclass 24, count 0 2006.173.03:27:15.83#ibcon#about to read 3, iclass 24, count 0 2006.173.03:27:15.87#ibcon#read 3, iclass 24, count 0 2006.173.03:27:15.87#ibcon#about to read 4, iclass 24, count 0 2006.173.03:27:15.87#ibcon#read 4, iclass 24, count 0 2006.173.03:27:15.87#ibcon#about to read 5, iclass 24, count 0 2006.173.03:27:15.87#ibcon#read 5, iclass 24, count 0 2006.173.03:27:15.87#ibcon#about to read 6, iclass 24, count 0 2006.173.03:27:15.87#ibcon#read 6, iclass 24, count 0 2006.173.03:27:15.87#ibcon#end of sib2, iclass 24, count 0 2006.173.03:27:15.87#ibcon#*after write, iclass 24, count 0 2006.173.03:27:15.87#ibcon#*before return 0, iclass 24, count 0 2006.173.03:27:15.87#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.03:27:15.87#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.03:27:15.87#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.03:27:15.87#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.03:27:15.87$vck44/vb=6,4 2006.173.03:27:15.87#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.03:27:15.87#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.03:27:15.87#ibcon#ireg 11 cls_cnt 2 2006.173.03:27:15.87#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.03:27:15.89#abcon#<5=/14 1.2 2.5 22.57 841006.3\r\n> 2006.173.03:27:15.91#abcon#{5=INTERFACE CLEAR} 2006.173.03:27:15.93#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.03:27:15.93#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.03:27:15.93#ibcon#enter wrdev, iclass 27, count 2 2006.173.03:27:15.93#ibcon#first serial, iclass 27, count 2 2006.173.03:27:15.93#ibcon#enter sib2, iclass 27, count 2 2006.173.03:27:15.93#ibcon#flushed, iclass 27, count 2 2006.173.03:27:15.93#ibcon#about to write, iclass 27, count 2 2006.173.03:27:15.93#ibcon#wrote, iclass 27, count 2 2006.173.03:27:15.93#ibcon#about to read 3, iclass 27, count 2 2006.173.03:27:15.95#ibcon#read 3, iclass 27, count 2 2006.173.03:27:15.95#ibcon#about to read 4, iclass 27, count 2 2006.173.03:27:15.95#ibcon#read 4, iclass 27, count 2 2006.173.03:27:15.95#ibcon#about to read 5, iclass 27, count 2 2006.173.03:27:15.95#ibcon#read 5, iclass 27, count 2 2006.173.03:27:15.95#ibcon#about to read 6, iclass 27, count 2 2006.173.03:27:15.95#ibcon#read 6, iclass 27, count 2 2006.173.03:27:15.95#ibcon#end of sib2, iclass 27, count 2 2006.173.03:27:15.95#ibcon#*mode == 0, iclass 27, count 2 2006.173.03:27:15.95#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.03:27:15.95#ibcon#[27=AT06-04\r\n] 2006.173.03:27:15.95#ibcon#*before write, iclass 27, count 2 2006.173.03:27:15.95#ibcon#enter sib2, iclass 27, count 2 2006.173.03:27:15.95#ibcon#flushed, iclass 27, count 2 2006.173.03:27:15.95#ibcon#about to write, iclass 27, count 2 2006.173.03:27:15.95#ibcon#wrote, iclass 27, count 2 2006.173.03:27:15.95#ibcon#about to read 3, iclass 27, count 2 2006.173.03:27:15.97#abcon#[5=S1D000X0/0*\r\n] 2006.173.03:27:15.98#ibcon#read 3, iclass 27, count 2 2006.173.03:27:15.98#ibcon#about to read 4, iclass 27, count 2 2006.173.03:27:15.98#ibcon#read 4, iclass 27, count 2 2006.173.03:27:15.98#ibcon#about to read 5, iclass 27, count 2 2006.173.03:27:15.98#ibcon#read 5, iclass 27, count 2 2006.173.03:27:15.98#ibcon#about to read 6, iclass 27, count 2 2006.173.03:27:15.98#ibcon#read 6, iclass 27, count 2 2006.173.03:27:15.98#ibcon#end of sib2, iclass 27, count 2 2006.173.03:27:15.98#ibcon#*after write, iclass 27, count 2 2006.173.03:27:15.98#ibcon#*before return 0, iclass 27, count 2 2006.173.03:27:15.98#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.03:27:15.98#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.03:27:15.98#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.03:27:15.98#ibcon#ireg 7 cls_cnt 0 2006.173.03:27:15.98#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.03:27:16.10#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.03:27:16.10#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.03:27:16.10#ibcon#enter wrdev, iclass 27, count 0 2006.173.03:27:16.10#ibcon#first serial, iclass 27, count 0 2006.173.03:27:16.10#ibcon#enter sib2, iclass 27, count 0 2006.173.03:27:16.10#ibcon#flushed, iclass 27, count 0 2006.173.03:27:16.10#ibcon#about to write, iclass 27, count 0 2006.173.03:27:16.10#ibcon#wrote, iclass 27, count 0 2006.173.03:27:16.10#ibcon#about to read 3, iclass 27, count 0 2006.173.03:27:16.12#ibcon#read 3, iclass 27, count 0 2006.173.03:27:16.12#ibcon#about to read 4, iclass 27, count 0 2006.173.03:27:16.12#ibcon#read 4, iclass 27, count 0 2006.173.03:27:16.12#ibcon#about to read 5, iclass 27, count 0 2006.173.03:27:16.12#ibcon#read 5, iclass 27, count 0 2006.173.03:27:16.12#ibcon#about to read 6, iclass 27, count 0 2006.173.03:27:16.12#ibcon#read 6, iclass 27, count 0 2006.173.03:27:16.12#ibcon#end of sib2, iclass 27, count 0 2006.173.03:27:16.12#ibcon#*mode == 0, iclass 27, count 0 2006.173.03:27:16.12#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.03:27:16.12#ibcon#[27=USB\r\n] 2006.173.03:27:16.12#ibcon#*before write, iclass 27, count 0 2006.173.03:27:16.12#ibcon#enter sib2, iclass 27, count 0 2006.173.03:27:16.12#ibcon#flushed, iclass 27, count 0 2006.173.03:27:16.12#ibcon#about to write, iclass 27, count 0 2006.173.03:27:16.12#ibcon#wrote, iclass 27, count 0 2006.173.03:27:16.12#ibcon#about to read 3, iclass 27, count 0 2006.173.03:27:16.15#ibcon#read 3, iclass 27, count 0 2006.173.03:27:16.15#ibcon#about to read 4, iclass 27, count 0 2006.173.03:27:16.15#ibcon#read 4, iclass 27, count 0 2006.173.03:27:16.15#ibcon#about to read 5, iclass 27, count 0 2006.173.03:27:16.15#ibcon#read 5, iclass 27, count 0 2006.173.03:27:16.15#ibcon#about to read 6, iclass 27, count 0 2006.173.03:27:16.15#ibcon#read 6, iclass 27, count 0 2006.173.03:27:16.15#ibcon#end of sib2, iclass 27, count 0 2006.173.03:27:16.15#ibcon#*after write, iclass 27, count 0 2006.173.03:27:16.15#ibcon#*before return 0, iclass 27, count 0 2006.173.03:27:16.15#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.03:27:16.15#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.03:27:16.15#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.03:27:16.15#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.03:27:16.15$vck44/vblo=7,734.99 2006.173.03:27:16.15#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.03:27:16.15#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.03:27:16.15#ibcon#ireg 17 cls_cnt 0 2006.173.03:27:16.15#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.03:27:16.15#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.03:27:16.15#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.03:27:16.15#ibcon#enter wrdev, iclass 32, count 0 2006.173.03:27:16.15#ibcon#first serial, iclass 32, count 0 2006.173.03:27:16.15#ibcon#enter sib2, iclass 32, count 0 2006.173.03:27:16.15#ibcon#flushed, iclass 32, count 0 2006.173.03:27:16.15#ibcon#about to write, iclass 32, count 0 2006.173.03:27:16.15#ibcon#wrote, iclass 32, count 0 2006.173.03:27:16.15#ibcon#about to read 3, iclass 32, count 0 2006.173.03:27:16.17#ibcon#read 3, iclass 32, count 0 2006.173.03:27:16.17#ibcon#about to read 4, iclass 32, count 0 2006.173.03:27:16.17#ibcon#read 4, iclass 32, count 0 2006.173.03:27:16.17#ibcon#about to read 5, iclass 32, count 0 2006.173.03:27:16.17#ibcon#read 5, iclass 32, count 0 2006.173.03:27:16.17#ibcon#about to read 6, iclass 32, count 0 2006.173.03:27:16.17#ibcon#read 6, iclass 32, count 0 2006.173.03:27:16.17#ibcon#end of sib2, iclass 32, count 0 2006.173.03:27:16.17#ibcon#*mode == 0, iclass 32, count 0 2006.173.03:27:16.17#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.03:27:16.17#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.03:27:16.17#ibcon#*before write, iclass 32, count 0 2006.173.03:27:16.17#ibcon#enter sib2, iclass 32, count 0 2006.173.03:27:16.17#ibcon#flushed, iclass 32, count 0 2006.173.03:27:16.17#ibcon#about to write, iclass 32, count 0 2006.173.03:27:16.17#ibcon#wrote, iclass 32, count 0 2006.173.03:27:16.17#ibcon#about to read 3, iclass 32, count 0 2006.173.03:27:16.21#ibcon#read 3, iclass 32, count 0 2006.173.03:27:16.21#ibcon#about to read 4, iclass 32, count 0 2006.173.03:27:16.21#ibcon#read 4, iclass 32, count 0 2006.173.03:27:16.21#ibcon#about to read 5, iclass 32, count 0 2006.173.03:27:16.21#ibcon#read 5, iclass 32, count 0 2006.173.03:27:16.21#ibcon#about to read 6, iclass 32, count 0 2006.173.03:27:16.21#ibcon#read 6, iclass 32, count 0 2006.173.03:27:16.21#ibcon#end of sib2, iclass 32, count 0 2006.173.03:27:16.21#ibcon#*after write, iclass 32, count 0 2006.173.03:27:16.21#ibcon#*before return 0, iclass 32, count 0 2006.173.03:27:16.21#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.03:27:16.21#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.03:27:16.21#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.03:27:16.21#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.03:27:16.21$vck44/vb=7,4 2006.173.03:27:16.21#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.03:27:16.21#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.03:27:16.21#ibcon#ireg 11 cls_cnt 2 2006.173.03:27:16.21#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.03:27:16.27#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.03:27:16.27#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.03:27:16.27#ibcon#enter wrdev, iclass 34, count 2 2006.173.03:27:16.27#ibcon#first serial, iclass 34, count 2 2006.173.03:27:16.27#ibcon#enter sib2, iclass 34, count 2 2006.173.03:27:16.27#ibcon#flushed, iclass 34, count 2 2006.173.03:27:16.27#ibcon#about to write, iclass 34, count 2 2006.173.03:27:16.27#ibcon#wrote, iclass 34, count 2 2006.173.03:27:16.27#ibcon#about to read 3, iclass 34, count 2 2006.173.03:27:16.29#ibcon#read 3, iclass 34, count 2 2006.173.03:27:16.29#ibcon#about to read 4, iclass 34, count 2 2006.173.03:27:16.29#ibcon#read 4, iclass 34, count 2 2006.173.03:27:16.29#ibcon#about to read 5, iclass 34, count 2 2006.173.03:27:16.29#ibcon#read 5, iclass 34, count 2 2006.173.03:27:16.29#ibcon#about to read 6, iclass 34, count 2 2006.173.03:27:16.29#ibcon#read 6, iclass 34, count 2 2006.173.03:27:16.29#ibcon#end of sib2, iclass 34, count 2 2006.173.03:27:16.29#ibcon#*mode == 0, iclass 34, count 2 2006.173.03:27:16.29#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.03:27:16.29#ibcon#[27=AT07-04\r\n] 2006.173.03:27:16.29#ibcon#*before write, iclass 34, count 2 2006.173.03:27:16.29#ibcon#enter sib2, iclass 34, count 2 2006.173.03:27:16.29#ibcon#flushed, iclass 34, count 2 2006.173.03:27:16.29#ibcon#about to write, iclass 34, count 2 2006.173.03:27:16.29#ibcon#wrote, iclass 34, count 2 2006.173.03:27:16.29#ibcon#about to read 3, iclass 34, count 2 2006.173.03:27:16.32#ibcon#read 3, iclass 34, count 2 2006.173.03:27:16.32#ibcon#about to read 4, iclass 34, count 2 2006.173.03:27:16.32#ibcon#read 4, iclass 34, count 2 2006.173.03:27:16.32#ibcon#about to read 5, iclass 34, count 2 2006.173.03:27:16.32#ibcon#read 5, iclass 34, count 2 2006.173.03:27:16.32#ibcon#about to read 6, iclass 34, count 2 2006.173.03:27:16.32#ibcon#read 6, iclass 34, count 2 2006.173.03:27:16.32#ibcon#end of sib2, iclass 34, count 2 2006.173.03:27:16.32#ibcon#*after write, iclass 34, count 2 2006.173.03:27:16.32#ibcon#*before return 0, iclass 34, count 2 2006.173.03:27:16.32#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.03:27:16.32#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.03:27:16.32#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.03:27:16.32#ibcon#ireg 7 cls_cnt 0 2006.173.03:27:16.32#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.03:27:16.44#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.03:27:16.44#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.03:27:16.44#ibcon#enter wrdev, iclass 34, count 0 2006.173.03:27:16.44#ibcon#first serial, iclass 34, count 0 2006.173.03:27:16.44#ibcon#enter sib2, iclass 34, count 0 2006.173.03:27:16.44#ibcon#flushed, iclass 34, count 0 2006.173.03:27:16.44#ibcon#about to write, iclass 34, count 0 2006.173.03:27:16.44#ibcon#wrote, iclass 34, count 0 2006.173.03:27:16.44#ibcon#about to read 3, iclass 34, count 0 2006.173.03:27:16.46#ibcon#read 3, iclass 34, count 0 2006.173.03:27:16.46#ibcon#about to read 4, iclass 34, count 0 2006.173.03:27:16.46#ibcon#read 4, iclass 34, count 0 2006.173.03:27:16.46#ibcon#about to read 5, iclass 34, count 0 2006.173.03:27:16.46#ibcon#read 5, iclass 34, count 0 2006.173.03:27:16.46#ibcon#about to read 6, iclass 34, count 0 2006.173.03:27:16.46#ibcon#read 6, iclass 34, count 0 2006.173.03:27:16.46#ibcon#end of sib2, iclass 34, count 0 2006.173.03:27:16.46#ibcon#*mode == 0, iclass 34, count 0 2006.173.03:27:16.46#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.03:27:16.46#ibcon#[27=USB\r\n] 2006.173.03:27:16.46#ibcon#*before write, iclass 34, count 0 2006.173.03:27:16.46#ibcon#enter sib2, iclass 34, count 0 2006.173.03:27:16.46#ibcon#flushed, iclass 34, count 0 2006.173.03:27:16.46#ibcon#about to write, iclass 34, count 0 2006.173.03:27:16.46#ibcon#wrote, iclass 34, count 0 2006.173.03:27:16.46#ibcon#about to read 3, iclass 34, count 0 2006.173.03:27:16.49#ibcon#read 3, iclass 34, count 0 2006.173.03:27:16.49#ibcon#about to read 4, iclass 34, count 0 2006.173.03:27:16.49#ibcon#read 4, iclass 34, count 0 2006.173.03:27:16.49#ibcon#about to read 5, iclass 34, count 0 2006.173.03:27:16.49#ibcon#read 5, iclass 34, count 0 2006.173.03:27:16.49#ibcon#about to read 6, iclass 34, count 0 2006.173.03:27:16.49#ibcon#read 6, iclass 34, count 0 2006.173.03:27:16.49#ibcon#end of sib2, iclass 34, count 0 2006.173.03:27:16.49#ibcon#*after write, iclass 34, count 0 2006.173.03:27:16.49#ibcon#*before return 0, iclass 34, count 0 2006.173.03:27:16.49#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.03:27:16.49#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.03:27:16.49#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.03:27:16.49#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.03:27:16.49$vck44/vblo=8,744.99 2006.173.03:27:16.49#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.03:27:16.49#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.03:27:16.49#ibcon#ireg 17 cls_cnt 0 2006.173.03:27:16.49#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.03:27:16.49#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.03:27:16.49#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.03:27:16.49#ibcon#enter wrdev, iclass 36, count 0 2006.173.03:27:16.49#ibcon#first serial, iclass 36, count 0 2006.173.03:27:16.49#ibcon#enter sib2, iclass 36, count 0 2006.173.03:27:16.49#ibcon#flushed, iclass 36, count 0 2006.173.03:27:16.49#ibcon#about to write, iclass 36, count 0 2006.173.03:27:16.49#ibcon#wrote, iclass 36, count 0 2006.173.03:27:16.49#ibcon#about to read 3, iclass 36, count 0 2006.173.03:27:16.51#ibcon#read 3, iclass 36, count 0 2006.173.03:27:16.51#ibcon#about to read 4, iclass 36, count 0 2006.173.03:27:16.51#ibcon#read 4, iclass 36, count 0 2006.173.03:27:16.51#ibcon#about to read 5, iclass 36, count 0 2006.173.03:27:16.51#ibcon#read 5, iclass 36, count 0 2006.173.03:27:16.51#ibcon#about to read 6, iclass 36, count 0 2006.173.03:27:16.51#ibcon#read 6, iclass 36, count 0 2006.173.03:27:16.51#ibcon#end of sib2, iclass 36, count 0 2006.173.03:27:16.51#ibcon#*mode == 0, iclass 36, count 0 2006.173.03:27:16.51#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.03:27:16.51#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.03:27:16.51#ibcon#*before write, iclass 36, count 0 2006.173.03:27:16.51#ibcon#enter sib2, iclass 36, count 0 2006.173.03:27:16.51#ibcon#flushed, iclass 36, count 0 2006.173.03:27:16.51#ibcon#about to write, iclass 36, count 0 2006.173.03:27:16.51#ibcon#wrote, iclass 36, count 0 2006.173.03:27:16.51#ibcon#about to read 3, iclass 36, count 0 2006.173.03:27:16.55#ibcon#read 3, iclass 36, count 0 2006.173.03:27:16.55#ibcon#about to read 4, iclass 36, count 0 2006.173.03:27:16.55#ibcon#read 4, iclass 36, count 0 2006.173.03:27:16.55#ibcon#about to read 5, iclass 36, count 0 2006.173.03:27:16.55#ibcon#read 5, iclass 36, count 0 2006.173.03:27:16.55#ibcon#about to read 6, iclass 36, count 0 2006.173.03:27:16.55#ibcon#read 6, iclass 36, count 0 2006.173.03:27:16.55#ibcon#end of sib2, iclass 36, count 0 2006.173.03:27:16.55#ibcon#*after write, iclass 36, count 0 2006.173.03:27:16.55#ibcon#*before return 0, iclass 36, count 0 2006.173.03:27:16.55#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.03:27:16.55#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.03:27:16.55#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.03:27:16.55#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.03:27:16.55$vck44/vb=8,4 2006.173.03:27:16.55#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.03:27:16.55#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.03:27:16.55#ibcon#ireg 11 cls_cnt 2 2006.173.03:27:16.55#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.03:27:16.61#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.03:27:16.61#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.03:27:16.61#ibcon#enter wrdev, iclass 38, count 2 2006.173.03:27:16.61#ibcon#first serial, iclass 38, count 2 2006.173.03:27:16.61#ibcon#enter sib2, iclass 38, count 2 2006.173.03:27:16.61#ibcon#flushed, iclass 38, count 2 2006.173.03:27:16.61#ibcon#about to write, iclass 38, count 2 2006.173.03:27:16.61#ibcon#wrote, iclass 38, count 2 2006.173.03:27:16.61#ibcon#about to read 3, iclass 38, count 2 2006.173.03:27:16.63#ibcon#read 3, iclass 38, count 2 2006.173.03:27:16.63#ibcon#about to read 4, iclass 38, count 2 2006.173.03:27:16.63#ibcon#read 4, iclass 38, count 2 2006.173.03:27:16.63#ibcon#about to read 5, iclass 38, count 2 2006.173.03:27:16.63#ibcon#read 5, iclass 38, count 2 2006.173.03:27:16.63#ibcon#about to read 6, iclass 38, count 2 2006.173.03:27:16.63#ibcon#read 6, iclass 38, count 2 2006.173.03:27:16.63#ibcon#end of sib2, iclass 38, count 2 2006.173.03:27:16.63#ibcon#*mode == 0, iclass 38, count 2 2006.173.03:27:16.63#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.03:27:16.63#ibcon#[27=AT08-04\r\n] 2006.173.03:27:16.63#ibcon#*before write, iclass 38, count 2 2006.173.03:27:16.63#ibcon#enter sib2, iclass 38, count 2 2006.173.03:27:16.63#ibcon#flushed, iclass 38, count 2 2006.173.03:27:16.63#ibcon#about to write, iclass 38, count 2 2006.173.03:27:16.63#ibcon#wrote, iclass 38, count 2 2006.173.03:27:16.63#ibcon#about to read 3, iclass 38, count 2 2006.173.03:27:16.66#ibcon#read 3, iclass 38, count 2 2006.173.03:27:16.66#ibcon#about to read 4, iclass 38, count 2 2006.173.03:27:16.66#ibcon#read 4, iclass 38, count 2 2006.173.03:27:16.66#ibcon#about to read 5, iclass 38, count 2 2006.173.03:27:16.66#ibcon#read 5, iclass 38, count 2 2006.173.03:27:16.66#ibcon#about to read 6, iclass 38, count 2 2006.173.03:27:16.66#ibcon#read 6, iclass 38, count 2 2006.173.03:27:16.66#ibcon#end of sib2, iclass 38, count 2 2006.173.03:27:16.66#ibcon#*after write, iclass 38, count 2 2006.173.03:27:16.66#ibcon#*before return 0, iclass 38, count 2 2006.173.03:27:16.66#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.03:27:16.66#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.03:27:16.66#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.03:27:16.66#ibcon#ireg 7 cls_cnt 0 2006.173.03:27:16.66#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.03:27:16.78#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.03:27:16.78#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.03:27:16.78#ibcon#enter wrdev, iclass 38, count 0 2006.173.03:27:16.78#ibcon#first serial, iclass 38, count 0 2006.173.03:27:16.78#ibcon#enter sib2, iclass 38, count 0 2006.173.03:27:16.78#ibcon#flushed, iclass 38, count 0 2006.173.03:27:16.78#ibcon#about to write, iclass 38, count 0 2006.173.03:27:16.78#ibcon#wrote, iclass 38, count 0 2006.173.03:27:16.78#ibcon#about to read 3, iclass 38, count 0 2006.173.03:27:16.80#ibcon#read 3, iclass 38, count 0 2006.173.03:27:16.80#ibcon#about to read 4, iclass 38, count 0 2006.173.03:27:16.80#ibcon#read 4, iclass 38, count 0 2006.173.03:27:16.80#ibcon#about to read 5, iclass 38, count 0 2006.173.03:27:16.80#ibcon#read 5, iclass 38, count 0 2006.173.03:27:16.80#ibcon#about to read 6, iclass 38, count 0 2006.173.03:27:16.80#ibcon#read 6, iclass 38, count 0 2006.173.03:27:16.80#ibcon#end of sib2, iclass 38, count 0 2006.173.03:27:16.80#ibcon#*mode == 0, iclass 38, count 0 2006.173.03:27:16.80#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.03:27:16.80#ibcon#[27=USB\r\n] 2006.173.03:27:16.80#ibcon#*before write, iclass 38, count 0 2006.173.03:27:16.80#ibcon#enter sib2, iclass 38, count 0 2006.173.03:27:16.80#ibcon#flushed, iclass 38, count 0 2006.173.03:27:16.80#ibcon#about to write, iclass 38, count 0 2006.173.03:27:16.80#ibcon#wrote, iclass 38, count 0 2006.173.03:27:16.80#ibcon#about to read 3, iclass 38, count 0 2006.173.03:27:16.83#ibcon#read 3, iclass 38, count 0 2006.173.03:27:16.83#ibcon#about to read 4, iclass 38, count 0 2006.173.03:27:16.83#ibcon#read 4, iclass 38, count 0 2006.173.03:27:16.83#ibcon#about to read 5, iclass 38, count 0 2006.173.03:27:16.83#ibcon#read 5, iclass 38, count 0 2006.173.03:27:16.83#ibcon#about to read 6, iclass 38, count 0 2006.173.03:27:16.83#ibcon#read 6, iclass 38, count 0 2006.173.03:27:16.83#ibcon#end of sib2, iclass 38, count 0 2006.173.03:27:16.83#ibcon#*after write, iclass 38, count 0 2006.173.03:27:16.83#ibcon#*before return 0, iclass 38, count 0 2006.173.03:27:16.83#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.03:27:16.83#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.03:27:16.83#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.03:27:16.83#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.03:27:16.83$vck44/vabw=wide 2006.173.03:27:16.83#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.03:27:16.83#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.03:27:16.83#ibcon#ireg 8 cls_cnt 0 2006.173.03:27:16.83#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.03:27:16.83#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.03:27:16.83#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.03:27:16.83#ibcon#enter wrdev, iclass 40, count 0 2006.173.03:27:16.83#ibcon#first serial, iclass 40, count 0 2006.173.03:27:16.83#ibcon#enter sib2, iclass 40, count 0 2006.173.03:27:16.83#ibcon#flushed, iclass 40, count 0 2006.173.03:27:16.83#ibcon#about to write, iclass 40, count 0 2006.173.03:27:16.83#ibcon#wrote, iclass 40, count 0 2006.173.03:27:16.83#ibcon#about to read 3, iclass 40, count 0 2006.173.03:27:16.85#ibcon#read 3, iclass 40, count 0 2006.173.03:27:16.85#ibcon#about to read 4, iclass 40, count 0 2006.173.03:27:16.85#ibcon#read 4, iclass 40, count 0 2006.173.03:27:16.85#ibcon#about to read 5, iclass 40, count 0 2006.173.03:27:16.85#ibcon#read 5, iclass 40, count 0 2006.173.03:27:16.85#ibcon#about to read 6, iclass 40, count 0 2006.173.03:27:16.85#ibcon#read 6, iclass 40, count 0 2006.173.03:27:16.85#ibcon#end of sib2, iclass 40, count 0 2006.173.03:27:16.85#ibcon#*mode == 0, iclass 40, count 0 2006.173.03:27:16.85#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.03:27:16.85#ibcon#[25=BW32\r\n] 2006.173.03:27:16.85#ibcon#*before write, iclass 40, count 0 2006.173.03:27:16.85#ibcon#enter sib2, iclass 40, count 0 2006.173.03:27:16.85#ibcon#flushed, iclass 40, count 0 2006.173.03:27:16.85#ibcon#about to write, iclass 40, count 0 2006.173.03:27:16.85#ibcon#wrote, iclass 40, count 0 2006.173.03:27:16.85#ibcon#about to read 3, iclass 40, count 0 2006.173.03:27:16.88#ibcon#read 3, iclass 40, count 0 2006.173.03:27:16.88#ibcon#about to read 4, iclass 40, count 0 2006.173.03:27:16.88#ibcon#read 4, iclass 40, count 0 2006.173.03:27:16.88#ibcon#about to read 5, iclass 40, count 0 2006.173.03:27:16.88#ibcon#read 5, iclass 40, count 0 2006.173.03:27:16.88#ibcon#about to read 6, iclass 40, count 0 2006.173.03:27:16.88#ibcon#read 6, iclass 40, count 0 2006.173.03:27:16.88#ibcon#end of sib2, iclass 40, count 0 2006.173.03:27:16.88#ibcon#*after write, iclass 40, count 0 2006.173.03:27:16.88#ibcon#*before return 0, iclass 40, count 0 2006.173.03:27:16.88#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.03:27:16.88#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.03:27:16.88#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.03:27:16.88#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.03:27:16.88$vck44/vbbw=wide 2006.173.03:27:16.88#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.03:27:16.88#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.03:27:16.88#ibcon#ireg 8 cls_cnt 0 2006.173.03:27:16.88#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.03:27:16.95#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.03:27:16.95#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.03:27:16.95#ibcon#enter wrdev, iclass 4, count 0 2006.173.03:27:16.95#ibcon#first serial, iclass 4, count 0 2006.173.03:27:16.95#ibcon#enter sib2, iclass 4, count 0 2006.173.03:27:16.95#ibcon#flushed, iclass 4, count 0 2006.173.03:27:16.95#ibcon#about to write, iclass 4, count 0 2006.173.03:27:16.95#ibcon#wrote, iclass 4, count 0 2006.173.03:27:16.95#ibcon#about to read 3, iclass 4, count 0 2006.173.03:27:16.97#ibcon#read 3, iclass 4, count 0 2006.173.03:27:16.97#ibcon#about to read 4, iclass 4, count 0 2006.173.03:27:16.97#ibcon#read 4, iclass 4, count 0 2006.173.03:27:16.97#ibcon#about to read 5, iclass 4, count 0 2006.173.03:27:16.97#ibcon#read 5, iclass 4, count 0 2006.173.03:27:16.97#ibcon#about to read 6, iclass 4, count 0 2006.173.03:27:16.97#ibcon#read 6, iclass 4, count 0 2006.173.03:27:16.97#ibcon#end of sib2, iclass 4, count 0 2006.173.03:27:16.97#ibcon#*mode == 0, iclass 4, count 0 2006.173.03:27:16.97#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.03:27:16.97#ibcon#[27=BW32\r\n] 2006.173.03:27:16.97#ibcon#*before write, iclass 4, count 0 2006.173.03:27:16.97#ibcon#enter sib2, iclass 4, count 0 2006.173.03:27:16.97#ibcon#flushed, iclass 4, count 0 2006.173.03:27:16.97#ibcon#about to write, iclass 4, count 0 2006.173.03:27:16.97#ibcon#wrote, iclass 4, count 0 2006.173.03:27:16.97#ibcon#about to read 3, iclass 4, count 0 2006.173.03:27:17.00#ibcon#read 3, iclass 4, count 0 2006.173.03:27:17.00#ibcon#about to read 4, iclass 4, count 0 2006.173.03:27:17.00#ibcon#read 4, iclass 4, count 0 2006.173.03:27:17.00#ibcon#about to read 5, iclass 4, count 0 2006.173.03:27:17.00#ibcon#read 5, iclass 4, count 0 2006.173.03:27:17.00#ibcon#about to read 6, iclass 4, count 0 2006.173.03:27:17.00#ibcon#read 6, iclass 4, count 0 2006.173.03:27:17.00#ibcon#end of sib2, iclass 4, count 0 2006.173.03:27:17.00#ibcon#*after write, iclass 4, count 0 2006.173.03:27:17.00#ibcon#*before return 0, iclass 4, count 0 2006.173.03:27:17.00#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.03:27:17.00#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.03:27:17.00#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.03:27:17.00#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.03:27:17.00$setupk4/ifdk4 2006.173.03:27:17.00$ifdk4/lo= 2006.173.03:27:17.00$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.03:27:17.00$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.03:27:17.00$ifdk4/patch= 2006.173.03:27:17.01$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.03:27:17.01$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.03:27:17.01$setupk4/!*+20s 2006.173.03:27:26.06#abcon#<5=/14 1.2 2.6 22.57 841006.3\r\n> 2006.173.03:27:26.08#abcon#{5=INTERFACE CLEAR} 2006.173.03:27:26.14#abcon#[5=S1D000X0/0*\r\n] 2006.173.03:27:31.53$setupk4/"tpicd 2006.173.03:27:31.53$setupk4/echo=off 2006.173.03:27:31.53$setupk4/xlog=off 2006.173.03:27:31.53:!2006.173.03:29:20 2006.173.03:27:55.14#trakl#Source acquired 2006.173.03:27:55.14#flagr#flagr/antenna,acquired 2006.173.03:29:20.00:preob 2006.173.03:29:20.14/onsource/TRACKING 2006.173.03:29:20.14:!2006.173.03:29:30 2006.173.03:29:30.00:"tape 2006.173.03:29:30.00:"st=record 2006.173.03:29:30.00:data_valid=on 2006.173.03:29:30.00:midob 2006.173.03:29:31.14/onsource/TRACKING 2006.173.03:29:31.14/wx/22.60,1006.3,83 2006.173.03:29:31.29/cable/+6.5103E-03 2006.173.03:29:32.38/va/01,07,usb,yes,34,37 2006.173.03:29:32.38/va/02,06,usb,yes,34,35 2006.173.03:29:32.38/va/03,05,usb,yes,44,46 2006.173.03:29:32.38/va/04,06,usb,yes,35,37 2006.173.03:29:32.38/va/05,04,usb,yes,27,28 2006.173.03:29:32.38/va/06,03,usb,yes,39,38 2006.173.03:29:32.38/va/07,04,usb,yes,31,32 2006.173.03:29:32.38/va/08,04,usb,yes,26,32 2006.173.03:29:32.61/valo/01,524.99,yes,locked 2006.173.03:29:32.61/valo/02,534.99,yes,locked 2006.173.03:29:32.61/valo/03,564.99,yes,locked 2006.173.03:29:32.61/valo/04,624.99,yes,locked 2006.173.03:29:32.61/valo/05,734.99,yes,locked 2006.173.03:29:32.61/valo/06,814.99,yes,locked 2006.173.03:29:32.61/valo/07,864.99,yes,locked 2006.173.03:29:32.61/valo/08,884.99,yes,locked 2006.173.03:29:33.70/vb/01,04,usb,yes,29,27 2006.173.03:29:33.70/vb/02,04,usb,yes,31,31 2006.173.03:29:33.70/vb/03,04,usb,yes,28,31 2006.173.03:29:33.70/vb/04,04,usb,yes,32,31 2006.173.03:29:33.70/vb/05,04,usb,yes,25,28 2006.173.03:29:33.70/vb/06,04,usb,yes,29,26 2006.173.03:29:33.70/vb/07,04,usb,yes,29,29 2006.173.03:29:33.70/vb/08,04,usb,yes,27,30 2006.173.03:29:33.94/vblo/01,629.99,yes,locked 2006.173.03:29:33.94/vblo/02,634.99,yes,locked 2006.173.03:29:33.94/vblo/03,649.99,yes,locked 2006.173.03:29:33.94/vblo/04,679.99,yes,locked 2006.173.03:29:33.94/vblo/05,709.99,yes,locked 2006.173.03:29:33.94/vblo/06,719.99,yes,locked 2006.173.03:29:33.94/vblo/07,734.99,yes,locked 2006.173.03:29:33.94/vblo/08,744.99,yes,locked 2006.173.03:29:34.09/vabw/8 2006.173.03:29:34.24/vbbw/8 2006.173.03:29:34.33/xfe/off,on,14.5 2006.173.03:29:34.70/ifatt/23,28,28,28 2006.173.03:29:35.07/fmout-gps/S +3.95E-07 2006.173.03:29:35.12:!2006.173.03:30:20 2006.173.03:30:20.01:data_valid=off 2006.173.03:30:20.02:"et 2006.173.03:30:20.02:!+3s 2006.173.03:30:23.03:"tape 2006.173.03:30:23.03:postob 2006.173.03:30:23.17/cable/+6.5096E-03 2006.173.03:30:23.17/wx/22.61,1006.3,83 2006.173.03:30:23.23/fmout-gps/S +3.94E-07 2006.173.03:30:23.23:scan_name=173-0332,jd0606,260 2006.173.03:30:23.23:source=cta26,033930.94,-014635.8,2000.0,cw 2006.173.03:30:24.14#flagr#flagr/antenna,new-source 2006.173.03:30:24.14:checkk5 2006.173.03:30:24.48/chk_autoobs//k5ts1/ autoobs is running! 2006.173.03:30:24.82/chk_autoobs//k5ts2/ autoobs is running! 2006.173.03:30:25.16/chk_autoobs//k5ts3/ autoobs is running! 2006.173.03:30:25.51/chk_autoobs//k5ts4/ autoobs is running! 2006.173.03:30:25.83/chk_obsdata//k5ts1/T1730329??a.dat file size is correct (nominal:200MB, actual:200MB). 2006.173.03:30:26.17/chk_obsdata//k5ts2/T1730329??b.dat file size is correct (nominal:200MB, actual:200MB). 2006.173.03:30:26.50/chk_obsdata//k5ts3/T1730329??c.dat file size is correct (nominal:200MB, actual:200MB). 2006.173.03:30:26.83/chk_obsdata//k5ts4/T1730329??d.dat file size is correct (nominal:200MB, actual:200MB). 2006.173.03:30:27.49/k5log//k5ts1_log_newline 2006.173.03:30:28.14/k5log//k5ts2_log_newline 2006.173.03:30:28.78/k5log//k5ts3_log_newline 2006.173.03:30:29.44/k5log//k5ts4_log_newline 2006.173.03:30:29.47/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.03:30:29.47:setupk4=1 2006.173.03:30:29.47$setupk4/echo=on 2006.173.03:30:29.47$setupk4/pcalon 2006.173.03:30:29.47$pcalon/"no phase cal control is implemented here 2006.173.03:30:29.47$setupk4/"tpicd=stop 2006.173.03:30:29.47$setupk4/"rec=synch_on 2006.173.03:30:29.47$setupk4/"rec_mode=128 2006.173.03:30:29.47$setupk4/!* 2006.173.03:30:29.47$setupk4/recpk4 2006.173.03:30:29.47$recpk4/recpatch= 2006.173.03:30:29.47$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.03:30:29.47$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.03:30:29.47$setupk4/vck44 2006.173.03:30:29.47$vck44/valo=1,524.99 2006.173.03:30:29.47#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.03:30:29.47#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.03:30:29.47#ibcon#ireg 17 cls_cnt 0 2006.173.03:30:29.47#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.03:30:29.47#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.03:30:29.47#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.03:30:29.47#ibcon#enter wrdev, iclass 15, count 0 2006.173.03:30:29.47#ibcon#first serial, iclass 15, count 0 2006.173.03:30:29.47#ibcon#enter sib2, iclass 15, count 0 2006.173.03:30:29.47#ibcon#flushed, iclass 15, count 0 2006.173.03:30:29.47#ibcon#about to write, iclass 15, count 0 2006.173.03:30:29.47#ibcon#wrote, iclass 15, count 0 2006.173.03:30:29.47#ibcon#about to read 3, iclass 15, count 0 2006.173.03:30:29.48#ibcon#read 3, iclass 15, count 0 2006.173.03:30:29.48#ibcon#about to read 4, iclass 15, count 0 2006.173.03:30:29.48#ibcon#read 4, iclass 15, count 0 2006.173.03:30:29.48#ibcon#about to read 5, iclass 15, count 0 2006.173.03:30:29.48#ibcon#read 5, iclass 15, count 0 2006.173.03:30:29.48#ibcon#about to read 6, iclass 15, count 0 2006.173.03:30:29.48#ibcon#read 6, iclass 15, count 0 2006.173.03:30:29.48#ibcon#end of sib2, iclass 15, count 0 2006.173.03:30:29.48#ibcon#*mode == 0, iclass 15, count 0 2006.173.03:30:29.48#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.03:30:29.48#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.03:30:29.48#ibcon#*before write, iclass 15, count 0 2006.173.03:30:29.48#ibcon#enter sib2, iclass 15, count 0 2006.173.03:30:29.48#ibcon#flushed, iclass 15, count 0 2006.173.03:30:29.48#ibcon#about to write, iclass 15, count 0 2006.173.03:30:29.48#ibcon#wrote, iclass 15, count 0 2006.173.03:30:29.48#ibcon#about to read 3, iclass 15, count 0 2006.173.03:30:29.53#ibcon#read 3, iclass 15, count 0 2006.173.03:30:29.53#ibcon#about to read 4, iclass 15, count 0 2006.173.03:30:29.53#ibcon#read 4, iclass 15, count 0 2006.173.03:30:29.53#ibcon#about to read 5, iclass 15, count 0 2006.173.03:30:29.53#ibcon#read 5, iclass 15, count 0 2006.173.03:30:29.53#ibcon#about to read 6, iclass 15, count 0 2006.173.03:30:29.53#ibcon#read 6, iclass 15, count 0 2006.173.03:30:29.53#ibcon#end of sib2, iclass 15, count 0 2006.173.03:30:29.53#ibcon#*after write, iclass 15, count 0 2006.173.03:30:29.53#ibcon#*before return 0, iclass 15, count 0 2006.173.03:30:29.53#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.03:30:29.53#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.03:30:29.53#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.03:30:29.53#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.03:30:29.53$vck44/va=1,7 2006.173.03:30:29.53#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.03:30:29.53#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.03:30:29.53#ibcon#ireg 11 cls_cnt 2 2006.173.03:30:29.53#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.03:30:29.53#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.03:30:29.53#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.03:30:29.53#ibcon#enter wrdev, iclass 17, count 2 2006.173.03:30:29.53#ibcon#first serial, iclass 17, count 2 2006.173.03:30:29.53#ibcon#enter sib2, iclass 17, count 2 2006.173.03:30:29.53#ibcon#flushed, iclass 17, count 2 2006.173.03:30:29.53#ibcon#about to write, iclass 17, count 2 2006.173.03:30:29.53#ibcon#wrote, iclass 17, count 2 2006.173.03:30:29.53#ibcon#about to read 3, iclass 17, count 2 2006.173.03:30:29.55#ibcon#read 3, iclass 17, count 2 2006.173.03:30:29.55#ibcon#about to read 4, iclass 17, count 2 2006.173.03:30:29.55#ibcon#read 4, iclass 17, count 2 2006.173.03:30:29.55#ibcon#about to read 5, iclass 17, count 2 2006.173.03:30:29.55#ibcon#read 5, iclass 17, count 2 2006.173.03:30:29.55#ibcon#about to read 6, iclass 17, count 2 2006.173.03:30:29.55#ibcon#read 6, iclass 17, count 2 2006.173.03:30:29.55#ibcon#end of sib2, iclass 17, count 2 2006.173.03:30:29.55#ibcon#*mode == 0, iclass 17, count 2 2006.173.03:30:29.55#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.03:30:29.55#ibcon#[25=AT01-07\r\n] 2006.173.03:30:29.55#ibcon#*before write, iclass 17, count 2 2006.173.03:30:29.55#ibcon#enter sib2, iclass 17, count 2 2006.173.03:30:29.55#ibcon#flushed, iclass 17, count 2 2006.173.03:30:29.55#ibcon#about to write, iclass 17, count 2 2006.173.03:30:29.55#ibcon#wrote, iclass 17, count 2 2006.173.03:30:29.55#ibcon#about to read 3, iclass 17, count 2 2006.173.03:30:29.58#ibcon#read 3, iclass 17, count 2 2006.173.03:30:29.58#ibcon#about to read 4, iclass 17, count 2 2006.173.03:30:29.58#ibcon#read 4, iclass 17, count 2 2006.173.03:30:29.58#ibcon#about to read 5, iclass 17, count 2 2006.173.03:30:29.58#ibcon#read 5, iclass 17, count 2 2006.173.03:30:29.58#ibcon#about to read 6, iclass 17, count 2 2006.173.03:30:29.58#ibcon#read 6, iclass 17, count 2 2006.173.03:30:29.58#ibcon#end of sib2, iclass 17, count 2 2006.173.03:30:29.58#ibcon#*after write, iclass 17, count 2 2006.173.03:30:29.58#ibcon#*before return 0, iclass 17, count 2 2006.173.03:30:29.58#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.03:30:29.58#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.03:30:29.58#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.03:30:29.58#ibcon#ireg 7 cls_cnt 0 2006.173.03:30:29.58#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.03:30:29.70#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.03:30:29.70#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.03:30:29.70#ibcon#enter wrdev, iclass 17, count 0 2006.173.03:30:29.70#ibcon#first serial, iclass 17, count 0 2006.173.03:30:29.70#ibcon#enter sib2, iclass 17, count 0 2006.173.03:30:29.70#ibcon#flushed, iclass 17, count 0 2006.173.03:30:29.70#ibcon#about to write, iclass 17, count 0 2006.173.03:30:29.70#ibcon#wrote, iclass 17, count 0 2006.173.03:30:29.70#ibcon#about to read 3, iclass 17, count 0 2006.173.03:30:29.72#ibcon#read 3, iclass 17, count 0 2006.173.03:30:29.72#ibcon#about to read 4, iclass 17, count 0 2006.173.03:30:29.72#ibcon#read 4, iclass 17, count 0 2006.173.03:30:29.72#ibcon#about to read 5, iclass 17, count 0 2006.173.03:30:29.72#ibcon#read 5, iclass 17, count 0 2006.173.03:30:29.72#ibcon#about to read 6, iclass 17, count 0 2006.173.03:30:29.72#ibcon#read 6, iclass 17, count 0 2006.173.03:30:29.72#ibcon#end of sib2, iclass 17, count 0 2006.173.03:30:29.72#ibcon#*mode == 0, iclass 17, count 0 2006.173.03:30:29.72#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.03:30:29.72#ibcon#[25=USB\r\n] 2006.173.03:30:29.72#ibcon#*before write, iclass 17, count 0 2006.173.03:30:29.72#ibcon#enter sib2, iclass 17, count 0 2006.173.03:30:29.72#ibcon#flushed, iclass 17, count 0 2006.173.03:30:29.72#ibcon#about to write, iclass 17, count 0 2006.173.03:30:29.72#ibcon#wrote, iclass 17, count 0 2006.173.03:30:29.72#ibcon#about to read 3, iclass 17, count 0 2006.173.03:30:29.75#ibcon#read 3, iclass 17, count 0 2006.173.03:30:29.75#ibcon#about to read 4, iclass 17, count 0 2006.173.03:30:29.75#ibcon#read 4, iclass 17, count 0 2006.173.03:30:29.75#ibcon#about to read 5, iclass 17, count 0 2006.173.03:30:29.75#ibcon#read 5, iclass 17, count 0 2006.173.03:30:29.75#ibcon#about to read 6, iclass 17, count 0 2006.173.03:30:29.75#ibcon#read 6, iclass 17, count 0 2006.173.03:30:29.75#ibcon#end of sib2, iclass 17, count 0 2006.173.03:30:29.75#ibcon#*after write, iclass 17, count 0 2006.173.03:30:29.75#ibcon#*before return 0, iclass 17, count 0 2006.173.03:30:29.75#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.03:30:29.75#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.03:30:29.75#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.03:30:29.75#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.03:30:29.75$vck44/valo=2,534.99 2006.173.03:30:29.75#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.03:30:29.75#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.03:30:29.75#ibcon#ireg 17 cls_cnt 0 2006.173.03:30:29.75#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.03:30:29.75#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.03:30:29.75#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.03:30:29.75#ibcon#enter wrdev, iclass 19, count 0 2006.173.03:30:29.75#ibcon#first serial, iclass 19, count 0 2006.173.03:30:29.75#ibcon#enter sib2, iclass 19, count 0 2006.173.03:30:29.75#ibcon#flushed, iclass 19, count 0 2006.173.03:30:29.75#ibcon#about to write, iclass 19, count 0 2006.173.03:30:29.75#ibcon#wrote, iclass 19, count 0 2006.173.03:30:29.75#ibcon#about to read 3, iclass 19, count 0 2006.173.03:30:29.77#ibcon#read 3, iclass 19, count 0 2006.173.03:30:29.77#ibcon#about to read 4, iclass 19, count 0 2006.173.03:30:29.77#ibcon#read 4, iclass 19, count 0 2006.173.03:30:29.77#ibcon#about to read 5, iclass 19, count 0 2006.173.03:30:29.77#ibcon#read 5, iclass 19, count 0 2006.173.03:30:29.77#ibcon#about to read 6, iclass 19, count 0 2006.173.03:30:29.77#ibcon#read 6, iclass 19, count 0 2006.173.03:30:29.77#ibcon#end of sib2, iclass 19, count 0 2006.173.03:30:29.77#ibcon#*mode == 0, iclass 19, count 0 2006.173.03:30:29.77#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.03:30:29.77#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.03:30:29.77#ibcon#*before write, iclass 19, count 0 2006.173.03:30:29.77#ibcon#enter sib2, iclass 19, count 0 2006.173.03:30:29.77#ibcon#flushed, iclass 19, count 0 2006.173.03:30:29.77#ibcon#about to write, iclass 19, count 0 2006.173.03:30:29.77#ibcon#wrote, iclass 19, count 0 2006.173.03:30:29.77#ibcon#about to read 3, iclass 19, count 0 2006.173.03:30:29.81#ibcon#read 3, iclass 19, count 0 2006.173.03:30:29.81#ibcon#about to read 4, iclass 19, count 0 2006.173.03:30:29.81#ibcon#read 4, iclass 19, count 0 2006.173.03:30:29.81#ibcon#about to read 5, iclass 19, count 0 2006.173.03:30:29.81#ibcon#read 5, iclass 19, count 0 2006.173.03:30:29.81#ibcon#about to read 6, iclass 19, count 0 2006.173.03:30:29.81#ibcon#read 6, iclass 19, count 0 2006.173.03:30:29.81#ibcon#end of sib2, iclass 19, count 0 2006.173.03:30:29.81#ibcon#*after write, iclass 19, count 0 2006.173.03:30:29.81#ibcon#*before return 0, iclass 19, count 0 2006.173.03:30:29.81#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.03:30:29.81#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.03:30:29.81#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.03:30:29.81#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.03:30:29.81$vck44/va=2,6 2006.173.03:30:29.81#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.03:30:29.81#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.03:30:29.81#ibcon#ireg 11 cls_cnt 2 2006.173.03:30:29.81#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.03:30:29.87#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.03:30:29.87#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.03:30:29.87#ibcon#enter wrdev, iclass 21, count 2 2006.173.03:30:29.87#ibcon#first serial, iclass 21, count 2 2006.173.03:30:29.87#ibcon#enter sib2, iclass 21, count 2 2006.173.03:30:29.87#ibcon#flushed, iclass 21, count 2 2006.173.03:30:29.87#ibcon#about to write, iclass 21, count 2 2006.173.03:30:29.87#ibcon#wrote, iclass 21, count 2 2006.173.03:30:29.87#ibcon#about to read 3, iclass 21, count 2 2006.173.03:30:29.89#ibcon#read 3, iclass 21, count 2 2006.173.03:30:29.89#ibcon#about to read 4, iclass 21, count 2 2006.173.03:30:29.89#ibcon#read 4, iclass 21, count 2 2006.173.03:30:29.89#ibcon#about to read 5, iclass 21, count 2 2006.173.03:30:29.89#ibcon#read 5, iclass 21, count 2 2006.173.03:30:29.89#ibcon#about to read 6, iclass 21, count 2 2006.173.03:30:29.89#ibcon#read 6, iclass 21, count 2 2006.173.03:30:29.89#ibcon#end of sib2, iclass 21, count 2 2006.173.03:30:29.89#ibcon#*mode == 0, iclass 21, count 2 2006.173.03:30:29.89#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.03:30:29.89#ibcon#[25=AT02-06\r\n] 2006.173.03:30:29.89#ibcon#*before write, iclass 21, count 2 2006.173.03:30:29.89#ibcon#enter sib2, iclass 21, count 2 2006.173.03:30:29.89#ibcon#flushed, iclass 21, count 2 2006.173.03:30:29.89#ibcon#about to write, iclass 21, count 2 2006.173.03:30:29.89#ibcon#wrote, iclass 21, count 2 2006.173.03:30:29.89#ibcon#about to read 3, iclass 21, count 2 2006.173.03:30:29.92#ibcon#read 3, iclass 21, count 2 2006.173.03:30:29.92#ibcon#about to read 4, iclass 21, count 2 2006.173.03:30:29.92#ibcon#read 4, iclass 21, count 2 2006.173.03:30:29.92#ibcon#about to read 5, iclass 21, count 2 2006.173.03:30:29.92#ibcon#read 5, iclass 21, count 2 2006.173.03:30:29.92#ibcon#about to read 6, iclass 21, count 2 2006.173.03:30:29.92#ibcon#read 6, iclass 21, count 2 2006.173.03:30:29.92#ibcon#end of sib2, iclass 21, count 2 2006.173.03:30:29.92#ibcon#*after write, iclass 21, count 2 2006.173.03:30:29.92#ibcon#*before return 0, iclass 21, count 2 2006.173.03:30:29.92#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.03:30:29.92#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.03:30:29.92#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.03:30:29.92#ibcon#ireg 7 cls_cnt 0 2006.173.03:30:29.92#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.03:30:30.04#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.03:30:30.04#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.03:30:30.04#ibcon#enter wrdev, iclass 21, count 0 2006.173.03:30:30.04#ibcon#first serial, iclass 21, count 0 2006.173.03:30:30.04#ibcon#enter sib2, iclass 21, count 0 2006.173.03:30:30.04#ibcon#flushed, iclass 21, count 0 2006.173.03:30:30.04#ibcon#about to write, iclass 21, count 0 2006.173.03:30:30.04#ibcon#wrote, iclass 21, count 0 2006.173.03:30:30.04#ibcon#about to read 3, iclass 21, count 0 2006.173.03:30:30.06#ibcon#read 3, iclass 21, count 0 2006.173.03:30:30.06#ibcon#about to read 4, iclass 21, count 0 2006.173.03:30:30.06#ibcon#read 4, iclass 21, count 0 2006.173.03:30:30.06#ibcon#about to read 5, iclass 21, count 0 2006.173.03:30:30.06#ibcon#read 5, iclass 21, count 0 2006.173.03:30:30.06#ibcon#about to read 6, iclass 21, count 0 2006.173.03:30:30.06#ibcon#read 6, iclass 21, count 0 2006.173.03:30:30.06#ibcon#end of sib2, iclass 21, count 0 2006.173.03:30:30.06#ibcon#*mode == 0, iclass 21, count 0 2006.173.03:30:30.06#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.03:30:30.06#ibcon#[25=USB\r\n] 2006.173.03:30:30.06#ibcon#*before write, iclass 21, count 0 2006.173.03:30:30.06#ibcon#enter sib2, iclass 21, count 0 2006.173.03:30:30.06#ibcon#flushed, iclass 21, count 0 2006.173.03:30:30.06#ibcon#about to write, iclass 21, count 0 2006.173.03:30:30.06#ibcon#wrote, iclass 21, count 0 2006.173.03:30:30.06#ibcon#about to read 3, iclass 21, count 0 2006.173.03:30:30.09#ibcon#read 3, iclass 21, count 0 2006.173.03:30:30.09#ibcon#about to read 4, iclass 21, count 0 2006.173.03:30:30.09#ibcon#read 4, iclass 21, count 0 2006.173.03:30:30.09#ibcon#about to read 5, iclass 21, count 0 2006.173.03:30:30.09#ibcon#read 5, iclass 21, count 0 2006.173.03:30:30.09#ibcon#about to read 6, iclass 21, count 0 2006.173.03:30:30.09#ibcon#read 6, iclass 21, count 0 2006.173.03:30:30.09#ibcon#end of sib2, iclass 21, count 0 2006.173.03:30:30.09#ibcon#*after write, iclass 21, count 0 2006.173.03:30:30.09#ibcon#*before return 0, iclass 21, count 0 2006.173.03:30:30.09#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.03:30:30.09#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.03:30:30.09#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.03:30:30.09#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.03:30:30.09$vck44/valo=3,564.99 2006.173.03:30:30.09#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.03:30:30.09#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.03:30:30.09#ibcon#ireg 17 cls_cnt 0 2006.173.03:30:30.09#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.03:30:30.09#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.03:30:30.09#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.03:30:30.09#ibcon#enter wrdev, iclass 23, count 0 2006.173.03:30:30.09#ibcon#first serial, iclass 23, count 0 2006.173.03:30:30.09#ibcon#enter sib2, iclass 23, count 0 2006.173.03:30:30.09#ibcon#flushed, iclass 23, count 0 2006.173.03:30:30.09#ibcon#about to write, iclass 23, count 0 2006.173.03:30:30.09#ibcon#wrote, iclass 23, count 0 2006.173.03:30:30.09#ibcon#about to read 3, iclass 23, count 0 2006.173.03:30:30.11#ibcon#read 3, iclass 23, count 0 2006.173.03:30:30.11#ibcon#about to read 4, iclass 23, count 0 2006.173.03:30:30.11#ibcon#read 4, iclass 23, count 0 2006.173.03:30:30.11#ibcon#about to read 5, iclass 23, count 0 2006.173.03:30:30.11#ibcon#read 5, iclass 23, count 0 2006.173.03:30:30.11#ibcon#about to read 6, iclass 23, count 0 2006.173.03:30:30.11#ibcon#read 6, iclass 23, count 0 2006.173.03:30:30.11#ibcon#end of sib2, iclass 23, count 0 2006.173.03:30:30.11#ibcon#*mode == 0, iclass 23, count 0 2006.173.03:30:30.11#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.03:30:30.11#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.03:30:30.11#ibcon#*before write, iclass 23, count 0 2006.173.03:30:30.11#ibcon#enter sib2, iclass 23, count 0 2006.173.03:30:30.11#ibcon#flushed, iclass 23, count 0 2006.173.03:30:30.11#ibcon#about to write, iclass 23, count 0 2006.173.03:30:30.11#ibcon#wrote, iclass 23, count 0 2006.173.03:30:30.11#ibcon#about to read 3, iclass 23, count 0 2006.173.03:30:30.15#ibcon#read 3, iclass 23, count 0 2006.173.03:30:30.15#ibcon#about to read 4, iclass 23, count 0 2006.173.03:30:30.15#ibcon#read 4, iclass 23, count 0 2006.173.03:30:30.15#ibcon#about to read 5, iclass 23, count 0 2006.173.03:30:30.15#ibcon#read 5, iclass 23, count 0 2006.173.03:30:30.15#ibcon#about to read 6, iclass 23, count 0 2006.173.03:30:30.15#ibcon#read 6, iclass 23, count 0 2006.173.03:30:30.15#ibcon#end of sib2, iclass 23, count 0 2006.173.03:30:30.15#ibcon#*after write, iclass 23, count 0 2006.173.03:30:30.15#ibcon#*before return 0, iclass 23, count 0 2006.173.03:30:30.15#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.03:30:30.15#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.03:30:30.15#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.03:30:30.15#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.03:30:30.15$vck44/va=3,5 2006.173.03:30:30.15#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.03:30:30.15#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.03:30:30.15#ibcon#ireg 11 cls_cnt 2 2006.173.03:30:30.15#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.03:30:30.21#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.03:30:30.21#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.03:30:30.21#ibcon#enter wrdev, iclass 25, count 2 2006.173.03:30:30.21#ibcon#first serial, iclass 25, count 2 2006.173.03:30:30.21#ibcon#enter sib2, iclass 25, count 2 2006.173.03:30:30.21#ibcon#flushed, iclass 25, count 2 2006.173.03:30:30.21#ibcon#about to write, iclass 25, count 2 2006.173.03:30:30.21#ibcon#wrote, iclass 25, count 2 2006.173.03:30:30.21#ibcon#about to read 3, iclass 25, count 2 2006.173.03:30:30.23#ibcon#read 3, iclass 25, count 2 2006.173.03:30:30.23#ibcon#about to read 4, iclass 25, count 2 2006.173.03:30:30.23#ibcon#read 4, iclass 25, count 2 2006.173.03:30:30.23#ibcon#about to read 5, iclass 25, count 2 2006.173.03:30:30.23#ibcon#read 5, iclass 25, count 2 2006.173.03:30:30.23#ibcon#about to read 6, iclass 25, count 2 2006.173.03:30:30.23#ibcon#read 6, iclass 25, count 2 2006.173.03:30:30.23#ibcon#end of sib2, iclass 25, count 2 2006.173.03:30:30.23#ibcon#*mode == 0, iclass 25, count 2 2006.173.03:30:30.23#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.03:30:30.23#ibcon#[25=AT03-05\r\n] 2006.173.03:30:30.23#ibcon#*before write, iclass 25, count 2 2006.173.03:30:30.23#ibcon#enter sib2, iclass 25, count 2 2006.173.03:30:30.23#ibcon#flushed, iclass 25, count 2 2006.173.03:30:30.23#ibcon#about to write, iclass 25, count 2 2006.173.03:30:30.23#ibcon#wrote, iclass 25, count 2 2006.173.03:30:30.23#ibcon#about to read 3, iclass 25, count 2 2006.173.03:30:30.26#ibcon#read 3, iclass 25, count 2 2006.173.03:30:30.26#ibcon#about to read 4, iclass 25, count 2 2006.173.03:30:30.26#ibcon#read 4, iclass 25, count 2 2006.173.03:30:30.26#ibcon#about to read 5, iclass 25, count 2 2006.173.03:30:30.26#ibcon#read 5, iclass 25, count 2 2006.173.03:30:30.26#ibcon#about to read 6, iclass 25, count 2 2006.173.03:30:30.26#ibcon#read 6, iclass 25, count 2 2006.173.03:30:30.26#ibcon#end of sib2, iclass 25, count 2 2006.173.03:30:30.26#ibcon#*after write, iclass 25, count 2 2006.173.03:30:30.26#ibcon#*before return 0, iclass 25, count 2 2006.173.03:30:30.26#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.03:30:30.26#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.03:30:30.26#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.03:30:30.26#ibcon#ireg 7 cls_cnt 0 2006.173.03:30:30.26#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.03:30:30.38#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.03:30:30.38#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.03:30:30.38#ibcon#enter wrdev, iclass 25, count 0 2006.173.03:30:30.38#ibcon#first serial, iclass 25, count 0 2006.173.03:30:30.38#ibcon#enter sib2, iclass 25, count 0 2006.173.03:30:30.38#ibcon#flushed, iclass 25, count 0 2006.173.03:30:30.38#ibcon#about to write, iclass 25, count 0 2006.173.03:30:30.38#ibcon#wrote, iclass 25, count 0 2006.173.03:30:30.38#ibcon#about to read 3, iclass 25, count 0 2006.173.03:30:30.40#ibcon#read 3, iclass 25, count 0 2006.173.03:30:30.40#ibcon#about to read 4, iclass 25, count 0 2006.173.03:30:30.40#ibcon#read 4, iclass 25, count 0 2006.173.03:30:30.40#ibcon#about to read 5, iclass 25, count 0 2006.173.03:30:30.40#ibcon#read 5, iclass 25, count 0 2006.173.03:30:30.40#ibcon#about to read 6, iclass 25, count 0 2006.173.03:30:30.40#ibcon#read 6, iclass 25, count 0 2006.173.03:30:30.40#ibcon#end of sib2, iclass 25, count 0 2006.173.03:30:30.40#ibcon#*mode == 0, iclass 25, count 0 2006.173.03:30:30.40#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.03:30:30.40#ibcon#[25=USB\r\n] 2006.173.03:30:30.40#ibcon#*before write, iclass 25, count 0 2006.173.03:30:30.40#ibcon#enter sib2, iclass 25, count 0 2006.173.03:30:30.40#ibcon#flushed, iclass 25, count 0 2006.173.03:30:30.40#ibcon#about to write, iclass 25, count 0 2006.173.03:30:30.40#ibcon#wrote, iclass 25, count 0 2006.173.03:30:30.40#ibcon#about to read 3, iclass 25, count 0 2006.173.03:30:30.43#ibcon#read 3, iclass 25, count 0 2006.173.03:30:30.43#ibcon#about to read 4, iclass 25, count 0 2006.173.03:30:30.43#ibcon#read 4, iclass 25, count 0 2006.173.03:30:30.43#ibcon#about to read 5, iclass 25, count 0 2006.173.03:30:30.43#ibcon#read 5, iclass 25, count 0 2006.173.03:30:30.43#ibcon#about to read 6, iclass 25, count 0 2006.173.03:30:30.43#ibcon#read 6, iclass 25, count 0 2006.173.03:30:30.43#ibcon#end of sib2, iclass 25, count 0 2006.173.03:30:30.43#ibcon#*after write, iclass 25, count 0 2006.173.03:30:30.43#ibcon#*before return 0, iclass 25, count 0 2006.173.03:30:30.43#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.03:30:30.43#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.03:30:30.43#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.03:30:30.43#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.03:30:30.43$vck44/valo=4,624.99 2006.173.03:30:30.43#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.03:30:30.43#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.03:30:30.43#ibcon#ireg 17 cls_cnt 0 2006.173.03:30:30.43#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.03:30:30.43#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.03:30:30.43#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.03:30:30.43#ibcon#enter wrdev, iclass 27, count 0 2006.173.03:30:30.43#ibcon#first serial, iclass 27, count 0 2006.173.03:30:30.43#ibcon#enter sib2, iclass 27, count 0 2006.173.03:30:30.43#ibcon#flushed, iclass 27, count 0 2006.173.03:30:30.43#ibcon#about to write, iclass 27, count 0 2006.173.03:30:30.43#ibcon#wrote, iclass 27, count 0 2006.173.03:30:30.43#ibcon#about to read 3, iclass 27, count 0 2006.173.03:30:30.45#ibcon#read 3, iclass 27, count 0 2006.173.03:30:30.45#ibcon#about to read 4, iclass 27, count 0 2006.173.03:30:30.45#ibcon#read 4, iclass 27, count 0 2006.173.03:30:30.45#ibcon#about to read 5, iclass 27, count 0 2006.173.03:30:30.45#ibcon#read 5, iclass 27, count 0 2006.173.03:30:30.45#ibcon#about to read 6, iclass 27, count 0 2006.173.03:30:30.45#ibcon#read 6, iclass 27, count 0 2006.173.03:30:30.45#ibcon#end of sib2, iclass 27, count 0 2006.173.03:30:30.45#ibcon#*mode == 0, iclass 27, count 0 2006.173.03:30:30.45#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.03:30:30.45#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.03:30:30.45#ibcon#*before write, iclass 27, count 0 2006.173.03:30:30.45#ibcon#enter sib2, iclass 27, count 0 2006.173.03:30:30.45#ibcon#flushed, iclass 27, count 0 2006.173.03:30:30.45#ibcon#about to write, iclass 27, count 0 2006.173.03:30:30.45#ibcon#wrote, iclass 27, count 0 2006.173.03:30:30.45#ibcon#about to read 3, iclass 27, count 0 2006.173.03:30:30.49#ibcon#read 3, iclass 27, count 0 2006.173.03:30:30.49#ibcon#about to read 4, iclass 27, count 0 2006.173.03:30:30.49#ibcon#read 4, iclass 27, count 0 2006.173.03:30:30.49#ibcon#about to read 5, iclass 27, count 0 2006.173.03:30:30.49#ibcon#read 5, iclass 27, count 0 2006.173.03:30:30.49#ibcon#about to read 6, iclass 27, count 0 2006.173.03:30:30.49#ibcon#read 6, iclass 27, count 0 2006.173.03:30:30.49#ibcon#end of sib2, iclass 27, count 0 2006.173.03:30:30.49#ibcon#*after write, iclass 27, count 0 2006.173.03:30:30.49#ibcon#*before return 0, iclass 27, count 0 2006.173.03:30:30.49#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.03:30:30.49#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.03:30:30.49#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.03:30:30.49#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.03:30:30.49$vck44/va=4,6 2006.173.03:30:30.49#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.03:30:30.49#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.03:30:30.49#ibcon#ireg 11 cls_cnt 2 2006.173.03:30:30.49#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.03:30:30.55#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.03:30:30.55#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.03:30:30.55#ibcon#enter wrdev, iclass 29, count 2 2006.173.03:30:30.55#ibcon#first serial, iclass 29, count 2 2006.173.03:30:30.55#ibcon#enter sib2, iclass 29, count 2 2006.173.03:30:30.55#ibcon#flushed, iclass 29, count 2 2006.173.03:30:30.55#ibcon#about to write, iclass 29, count 2 2006.173.03:30:30.55#ibcon#wrote, iclass 29, count 2 2006.173.03:30:30.55#ibcon#about to read 3, iclass 29, count 2 2006.173.03:30:30.57#ibcon#read 3, iclass 29, count 2 2006.173.03:30:30.57#ibcon#about to read 4, iclass 29, count 2 2006.173.03:30:30.57#ibcon#read 4, iclass 29, count 2 2006.173.03:30:30.57#ibcon#about to read 5, iclass 29, count 2 2006.173.03:30:30.57#ibcon#read 5, iclass 29, count 2 2006.173.03:30:30.57#ibcon#about to read 6, iclass 29, count 2 2006.173.03:30:30.57#ibcon#read 6, iclass 29, count 2 2006.173.03:30:30.57#ibcon#end of sib2, iclass 29, count 2 2006.173.03:30:30.57#ibcon#*mode == 0, iclass 29, count 2 2006.173.03:30:30.57#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.03:30:30.57#ibcon#[25=AT04-06\r\n] 2006.173.03:30:30.57#ibcon#*before write, iclass 29, count 2 2006.173.03:30:30.57#ibcon#enter sib2, iclass 29, count 2 2006.173.03:30:30.57#ibcon#flushed, iclass 29, count 2 2006.173.03:30:30.57#ibcon#about to write, iclass 29, count 2 2006.173.03:30:30.57#ibcon#wrote, iclass 29, count 2 2006.173.03:30:30.57#ibcon#about to read 3, iclass 29, count 2 2006.173.03:30:30.60#ibcon#read 3, iclass 29, count 2 2006.173.03:30:30.60#ibcon#about to read 4, iclass 29, count 2 2006.173.03:30:30.60#ibcon#read 4, iclass 29, count 2 2006.173.03:30:30.60#ibcon#about to read 5, iclass 29, count 2 2006.173.03:30:30.60#ibcon#read 5, iclass 29, count 2 2006.173.03:30:30.60#ibcon#about to read 6, iclass 29, count 2 2006.173.03:30:30.60#ibcon#read 6, iclass 29, count 2 2006.173.03:30:30.60#ibcon#end of sib2, iclass 29, count 2 2006.173.03:30:30.60#ibcon#*after write, iclass 29, count 2 2006.173.03:30:30.60#ibcon#*before return 0, iclass 29, count 2 2006.173.03:30:30.60#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.03:30:30.60#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.03:30:30.60#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.03:30:30.60#ibcon#ireg 7 cls_cnt 0 2006.173.03:30:30.60#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.03:30:30.72#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.03:30:30.72#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.03:30:30.72#ibcon#enter wrdev, iclass 29, count 0 2006.173.03:30:30.72#ibcon#first serial, iclass 29, count 0 2006.173.03:30:30.72#ibcon#enter sib2, iclass 29, count 0 2006.173.03:30:30.72#ibcon#flushed, iclass 29, count 0 2006.173.03:30:30.72#ibcon#about to write, iclass 29, count 0 2006.173.03:30:30.72#ibcon#wrote, iclass 29, count 0 2006.173.03:30:30.72#ibcon#about to read 3, iclass 29, count 0 2006.173.03:30:30.74#ibcon#read 3, iclass 29, count 0 2006.173.03:30:30.74#ibcon#about to read 4, iclass 29, count 0 2006.173.03:30:30.74#ibcon#read 4, iclass 29, count 0 2006.173.03:30:30.74#ibcon#about to read 5, iclass 29, count 0 2006.173.03:30:30.74#ibcon#read 5, iclass 29, count 0 2006.173.03:30:30.74#ibcon#about to read 6, iclass 29, count 0 2006.173.03:30:30.74#ibcon#read 6, iclass 29, count 0 2006.173.03:30:30.74#ibcon#end of sib2, iclass 29, count 0 2006.173.03:30:30.74#ibcon#*mode == 0, iclass 29, count 0 2006.173.03:30:30.74#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.03:30:30.74#ibcon#[25=USB\r\n] 2006.173.03:30:30.74#ibcon#*before write, iclass 29, count 0 2006.173.03:30:30.74#ibcon#enter sib2, iclass 29, count 0 2006.173.03:30:30.74#ibcon#flushed, iclass 29, count 0 2006.173.03:30:30.74#ibcon#about to write, iclass 29, count 0 2006.173.03:30:30.74#ibcon#wrote, iclass 29, count 0 2006.173.03:30:30.74#ibcon#about to read 3, iclass 29, count 0 2006.173.03:30:30.77#ibcon#read 3, iclass 29, count 0 2006.173.03:30:30.77#ibcon#about to read 4, iclass 29, count 0 2006.173.03:30:30.77#ibcon#read 4, iclass 29, count 0 2006.173.03:30:30.77#ibcon#about to read 5, iclass 29, count 0 2006.173.03:30:30.77#ibcon#read 5, iclass 29, count 0 2006.173.03:30:30.77#ibcon#about to read 6, iclass 29, count 0 2006.173.03:30:30.77#ibcon#read 6, iclass 29, count 0 2006.173.03:30:30.77#ibcon#end of sib2, iclass 29, count 0 2006.173.03:30:30.77#ibcon#*after write, iclass 29, count 0 2006.173.03:30:30.77#ibcon#*before return 0, iclass 29, count 0 2006.173.03:30:30.77#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.03:30:30.77#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.03:30:30.77#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.03:30:30.77#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.03:30:30.77$vck44/valo=5,734.99 2006.173.03:30:30.77#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.03:30:30.77#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.03:30:30.77#ibcon#ireg 17 cls_cnt 0 2006.173.03:30:30.77#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.03:30:30.77#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.03:30:30.77#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.03:30:30.77#ibcon#enter wrdev, iclass 31, count 0 2006.173.03:30:30.77#ibcon#first serial, iclass 31, count 0 2006.173.03:30:30.77#ibcon#enter sib2, iclass 31, count 0 2006.173.03:30:30.77#ibcon#flushed, iclass 31, count 0 2006.173.03:30:30.77#ibcon#about to write, iclass 31, count 0 2006.173.03:30:30.77#ibcon#wrote, iclass 31, count 0 2006.173.03:30:30.77#ibcon#about to read 3, iclass 31, count 0 2006.173.03:30:30.79#ibcon#read 3, iclass 31, count 0 2006.173.03:30:30.79#ibcon#about to read 4, iclass 31, count 0 2006.173.03:30:30.79#ibcon#read 4, iclass 31, count 0 2006.173.03:30:30.79#ibcon#about to read 5, iclass 31, count 0 2006.173.03:30:30.79#ibcon#read 5, iclass 31, count 0 2006.173.03:30:30.79#ibcon#about to read 6, iclass 31, count 0 2006.173.03:30:30.79#ibcon#read 6, iclass 31, count 0 2006.173.03:30:30.79#ibcon#end of sib2, iclass 31, count 0 2006.173.03:30:30.79#ibcon#*mode == 0, iclass 31, count 0 2006.173.03:30:30.79#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.03:30:30.79#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.03:30:30.79#ibcon#*before write, iclass 31, count 0 2006.173.03:30:30.79#ibcon#enter sib2, iclass 31, count 0 2006.173.03:30:30.79#ibcon#flushed, iclass 31, count 0 2006.173.03:30:30.79#ibcon#about to write, iclass 31, count 0 2006.173.03:30:30.79#ibcon#wrote, iclass 31, count 0 2006.173.03:30:30.79#ibcon#about to read 3, iclass 31, count 0 2006.173.03:30:30.83#ibcon#read 3, iclass 31, count 0 2006.173.03:30:30.83#ibcon#about to read 4, iclass 31, count 0 2006.173.03:30:30.83#ibcon#read 4, iclass 31, count 0 2006.173.03:30:30.83#ibcon#about to read 5, iclass 31, count 0 2006.173.03:30:30.83#ibcon#read 5, iclass 31, count 0 2006.173.03:30:30.83#ibcon#about to read 6, iclass 31, count 0 2006.173.03:30:30.83#ibcon#read 6, iclass 31, count 0 2006.173.03:30:30.83#ibcon#end of sib2, iclass 31, count 0 2006.173.03:30:30.83#ibcon#*after write, iclass 31, count 0 2006.173.03:30:30.83#ibcon#*before return 0, iclass 31, count 0 2006.173.03:30:30.83#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.03:30:30.83#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.03:30:30.83#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.03:30:30.83#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.03:30:30.83$vck44/va=5,4 2006.173.03:30:30.83#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.173.03:30:30.83#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.173.03:30:30.83#ibcon#ireg 11 cls_cnt 2 2006.173.03:30:30.83#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.03:30:30.89#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.03:30:30.89#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.03:30:30.89#ibcon#enter wrdev, iclass 33, count 2 2006.173.03:30:30.89#ibcon#first serial, iclass 33, count 2 2006.173.03:30:30.89#ibcon#enter sib2, iclass 33, count 2 2006.173.03:30:30.89#ibcon#flushed, iclass 33, count 2 2006.173.03:30:30.89#ibcon#about to write, iclass 33, count 2 2006.173.03:30:30.89#ibcon#wrote, iclass 33, count 2 2006.173.03:30:30.89#ibcon#about to read 3, iclass 33, count 2 2006.173.03:30:30.91#ibcon#read 3, iclass 33, count 2 2006.173.03:30:30.91#ibcon#about to read 4, iclass 33, count 2 2006.173.03:30:30.91#ibcon#read 4, iclass 33, count 2 2006.173.03:30:30.91#ibcon#about to read 5, iclass 33, count 2 2006.173.03:30:30.91#ibcon#read 5, iclass 33, count 2 2006.173.03:30:30.91#ibcon#about to read 6, iclass 33, count 2 2006.173.03:30:30.91#ibcon#read 6, iclass 33, count 2 2006.173.03:30:30.91#ibcon#end of sib2, iclass 33, count 2 2006.173.03:30:30.91#ibcon#*mode == 0, iclass 33, count 2 2006.173.03:30:30.91#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.173.03:30:30.91#ibcon#[25=AT05-04\r\n] 2006.173.03:30:30.91#ibcon#*before write, iclass 33, count 2 2006.173.03:30:30.91#ibcon#enter sib2, iclass 33, count 2 2006.173.03:30:30.91#ibcon#flushed, iclass 33, count 2 2006.173.03:30:30.91#ibcon#about to write, iclass 33, count 2 2006.173.03:30:30.91#ibcon#wrote, iclass 33, count 2 2006.173.03:30:30.91#ibcon#about to read 3, iclass 33, count 2 2006.173.03:30:30.94#ibcon#read 3, iclass 33, count 2 2006.173.03:30:30.94#ibcon#about to read 4, iclass 33, count 2 2006.173.03:30:30.94#ibcon#read 4, iclass 33, count 2 2006.173.03:30:30.94#ibcon#about to read 5, iclass 33, count 2 2006.173.03:30:30.94#ibcon#read 5, iclass 33, count 2 2006.173.03:30:30.94#ibcon#about to read 6, iclass 33, count 2 2006.173.03:30:30.94#ibcon#read 6, iclass 33, count 2 2006.173.03:30:30.94#ibcon#end of sib2, iclass 33, count 2 2006.173.03:30:30.94#ibcon#*after write, iclass 33, count 2 2006.173.03:30:30.94#ibcon#*before return 0, iclass 33, count 2 2006.173.03:30:30.94#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.03:30:30.94#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.173.03:30:30.94#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.173.03:30:30.94#ibcon#ireg 7 cls_cnt 0 2006.173.03:30:30.94#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.03:30:31.06#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.03:30:31.06#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.03:30:31.06#ibcon#enter wrdev, iclass 33, count 0 2006.173.03:30:31.06#ibcon#first serial, iclass 33, count 0 2006.173.03:30:31.06#ibcon#enter sib2, iclass 33, count 0 2006.173.03:30:31.06#ibcon#flushed, iclass 33, count 0 2006.173.03:30:31.06#ibcon#about to write, iclass 33, count 0 2006.173.03:30:31.06#ibcon#wrote, iclass 33, count 0 2006.173.03:30:31.06#ibcon#about to read 3, iclass 33, count 0 2006.173.03:30:31.08#ibcon#read 3, iclass 33, count 0 2006.173.03:30:31.08#ibcon#about to read 4, iclass 33, count 0 2006.173.03:30:31.08#ibcon#read 4, iclass 33, count 0 2006.173.03:30:31.08#ibcon#about to read 5, iclass 33, count 0 2006.173.03:30:31.08#ibcon#read 5, iclass 33, count 0 2006.173.03:30:31.08#ibcon#about to read 6, iclass 33, count 0 2006.173.03:30:31.08#ibcon#read 6, iclass 33, count 0 2006.173.03:30:31.08#ibcon#end of sib2, iclass 33, count 0 2006.173.03:30:31.08#ibcon#*mode == 0, iclass 33, count 0 2006.173.03:30:31.08#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.03:30:31.08#ibcon#[25=USB\r\n] 2006.173.03:30:31.08#ibcon#*before write, iclass 33, count 0 2006.173.03:30:31.08#ibcon#enter sib2, iclass 33, count 0 2006.173.03:30:31.08#ibcon#flushed, iclass 33, count 0 2006.173.03:30:31.08#ibcon#about to write, iclass 33, count 0 2006.173.03:30:31.08#ibcon#wrote, iclass 33, count 0 2006.173.03:30:31.08#ibcon#about to read 3, iclass 33, count 0 2006.173.03:30:31.11#ibcon#read 3, iclass 33, count 0 2006.173.03:30:31.11#ibcon#about to read 4, iclass 33, count 0 2006.173.03:30:31.11#ibcon#read 4, iclass 33, count 0 2006.173.03:30:31.11#ibcon#about to read 5, iclass 33, count 0 2006.173.03:30:31.11#ibcon#read 5, iclass 33, count 0 2006.173.03:30:31.11#ibcon#about to read 6, iclass 33, count 0 2006.173.03:30:31.11#ibcon#read 6, iclass 33, count 0 2006.173.03:30:31.11#ibcon#end of sib2, iclass 33, count 0 2006.173.03:30:31.11#ibcon#*after write, iclass 33, count 0 2006.173.03:30:31.11#ibcon#*before return 0, iclass 33, count 0 2006.173.03:30:31.11#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.03:30:31.11#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.173.03:30:31.11#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.03:30:31.11#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.03:30:31.11$vck44/valo=6,814.99 2006.173.03:30:31.11#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.03:30:31.11#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.03:30:31.11#ibcon#ireg 17 cls_cnt 0 2006.173.03:30:31.11#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.03:30:31.11#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.03:30:31.11#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.03:30:31.11#ibcon#enter wrdev, iclass 35, count 0 2006.173.03:30:31.11#ibcon#first serial, iclass 35, count 0 2006.173.03:30:31.11#ibcon#enter sib2, iclass 35, count 0 2006.173.03:30:31.11#ibcon#flushed, iclass 35, count 0 2006.173.03:30:31.11#ibcon#about to write, iclass 35, count 0 2006.173.03:30:31.11#ibcon#wrote, iclass 35, count 0 2006.173.03:30:31.11#ibcon#about to read 3, iclass 35, count 0 2006.173.03:30:31.13#ibcon#read 3, iclass 35, count 0 2006.173.03:30:31.13#ibcon#about to read 4, iclass 35, count 0 2006.173.03:30:31.13#ibcon#read 4, iclass 35, count 0 2006.173.03:30:31.13#ibcon#about to read 5, iclass 35, count 0 2006.173.03:30:31.13#ibcon#read 5, iclass 35, count 0 2006.173.03:30:31.13#ibcon#about to read 6, iclass 35, count 0 2006.173.03:30:31.13#ibcon#read 6, iclass 35, count 0 2006.173.03:30:31.13#ibcon#end of sib2, iclass 35, count 0 2006.173.03:30:31.13#ibcon#*mode == 0, iclass 35, count 0 2006.173.03:30:31.13#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.03:30:31.13#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.03:30:31.13#ibcon#*before write, iclass 35, count 0 2006.173.03:30:31.13#ibcon#enter sib2, iclass 35, count 0 2006.173.03:30:31.13#ibcon#flushed, iclass 35, count 0 2006.173.03:30:31.13#ibcon#about to write, iclass 35, count 0 2006.173.03:30:31.13#ibcon#wrote, iclass 35, count 0 2006.173.03:30:31.13#ibcon#about to read 3, iclass 35, count 0 2006.173.03:30:31.17#ibcon#read 3, iclass 35, count 0 2006.173.03:30:31.17#ibcon#about to read 4, iclass 35, count 0 2006.173.03:30:31.17#ibcon#read 4, iclass 35, count 0 2006.173.03:30:31.17#ibcon#about to read 5, iclass 35, count 0 2006.173.03:30:31.17#ibcon#read 5, iclass 35, count 0 2006.173.03:30:31.17#ibcon#about to read 6, iclass 35, count 0 2006.173.03:30:31.17#ibcon#read 6, iclass 35, count 0 2006.173.03:30:31.17#ibcon#end of sib2, iclass 35, count 0 2006.173.03:30:31.17#ibcon#*after write, iclass 35, count 0 2006.173.03:30:31.17#ibcon#*before return 0, iclass 35, count 0 2006.173.03:30:31.17#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.03:30:31.17#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.03:30:31.17#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.03:30:31.17#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.03:30:31.17$vck44/va=6,3 2006.173.03:30:31.17#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.173.03:30:31.17#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.173.03:30:31.17#ibcon#ireg 11 cls_cnt 2 2006.173.03:30:31.17#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.03:30:31.23#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.03:30:31.23#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.03:30:31.23#ibcon#enter wrdev, iclass 37, count 2 2006.173.03:30:31.23#ibcon#first serial, iclass 37, count 2 2006.173.03:30:31.23#ibcon#enter sib2, iclass 37, count 2 2006.173.03:30:31.23#ibcon#flushed, iclass 37, count 2 2006.173.03:30:31.23#ibcon#about to write, iclass 37, count 2 2006.173.03:30:31.23#ibcon#wrote, iclass 37, count 2 2006.173.03:30:31.23#ibcon#about to read 3, iclass 37, count 2 2006.173.03:30:31.25#ibcon#read 3, iclass 37, count 2 2006.173.03:30:31.25#ibcon#about to read 4, iclass 37, count 2 2006.173.03:30:31.25#ibcon#read 4, iclass 37, count 2 2006.173.03:30:31.25#ibcon#about to read 5, iclass 37, count 2 2006.173.03:30:31.25#ibcon#read 5, iclass 37, count 2 2006.173.03:30:31.25#ibcon#about to read 6, iclass 37, count 2 2006.173.03:30:31.25#ibcon#read 6, iclass 37, count 2 2006.173.03:30:31.25#ibcon#end of sib2, iclass 37, count 2 2006.173.03:30:31.25#ibcon#*mode == 0, iclass 37, count 2 2006.173.03:30:31.25#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.173.03:30:31.25#ibcon#[25=AT06-03\r\n] 2006.173.03:30:31.25#ibcon#*before write, iclass 37, count 2 2006.173.03:30:31.25#ibcon#enter sib2, iclass 37, count 2 2006.173.03:30:31.25#ibcon#flushed, iclass 37, count 2 2006.173.03:30:31.25#ibcon#about to write, iclass 37, count 2 2006.173.03:30:31.25#ibcon#wrote, iclass 37, count 2 2006.173.03:30:31.25#ibcon#about to read 3, iclass 37, count 2 2006.173.03:30:31.28#ibcon#read 3, iclass 37, count 2 2006.173.03:30:31.28#ibcon#about to read 4, iclass 37, count 2 2006.173.03:30:31.28#ibcon#read 4, iclass 37, count 2 2006.173.03:30:31.28#ibcon#about to read 5, iclass 37, count 2 2006.173.03:30:31.28#ibcon#read 5, iclass 37, count 2 2006.173.03:30:31.28#ibcon#about to read 6, iclass 37, count 2 2006.173.03:30:31.28#ibcon#read 6, iclass 37, count 2 2006.173.03:30:31.28#ibcon#end of sib2, iclass 37, count 2 2006.173.03:30:31.28#ibcon#*after write, iclass 37, count 2 2006.173.03:30:31.28#ibcon#*before return 0, iclass 37, count 2 2006.173.03:30:31.28#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.03:30:31.28#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.173.03:30:31.28#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.173.03:30:31.28#ibcon#ireg 7 cls_cnt 0 2006.173.03:30:31.28#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.03:30:31.40#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.03:30:31.40#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.03:30:31.40#ibcon#enter wrdev, iclass 37, count 0 2006.173.03:30:31.40#ibcon#first serial, iclass 37, count 0 2006.173.03:30:31.40#ibcon#enter sib2, iclass 37, count 0 2006.173.03:30:31.40#ibcon#flushed, iclass 37, count 0 2006.173.03:30:31.40#ibcon#about to write, iclass 37, count 0 2006.173.03:30:31.40#ibcon#wrote, iclass 37, count 0 2006.173.03:30:31.40#ibcon#about to read 3, iclass 37, count 0 2006.173.03:30:31.42#ibcon#read 3, iclass 37, count 0 2006.173.03:30:31.42#ibcon#about to read 4, iclass 37, count 0 2006.173.03:30:31.42#ibcon#read 4, iclass 37, count 0 2006.173.03:30:31.42#ibcon#about to read 5, iclass 37, count 0 2006.173.03:30:31.42#ibcon#read 5, iclass 37, count 0 2006.173.03:30:31.42#ibcon#about to read 6, iclass 37, count 0 2006.173.03:30:31.42#ibcon#read 6, iclass 37, count 0 2006.173.03:30:31.42#ibcon#end of sib2, iclass 37, count 0 2006.173.03:30:31.42#ibcon#*mode == 0, iclass 37, count 0 2006.173.03:30:31.42#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.03:30:31.42#ibcon#[25=USB\r\n] 2006.173.03:30:31.42#ibcon#*before write, iclass 37, count 0 2006.173.03:30:31.42#ibcon#enter sib2, iclass 37, count 0 2006.173.03:30:31.42#ibcon#flushed, iclass 37, count 0 2006.173.03:30:31.42#ibcon#about to write, iclass 37, count 0 2006.173.03:30:31.42#ibcon#wrote, iclass 37, count 0 2006.173.03:30:31.42#ibcon#about to read 3, iclass 37, count 0 2006.173.03:30:31.45#ibcon#read 3, iclass 37, count 0 2006.173.03:30:31.45#ibcon#about to read 4, iclass 37, count 0 2006.173.03:30:31.45#ibcon#read 4, iclass 37, count 0 2006.173.03:30:31.45#ibcon#about to read 5, iclass 37, count 0 2006.173.03:30:31.45#ibcon#read 5, iclass 37, count 0 2006.173.03:30:31.45#ibcon#about to read 6, iclass 37, count 0 2006.173.03:30:31.45#ibcon#read 6, iclass 37, count 0 2006.173.03:30:31.45#ibcon#end of sib2, iclass 37, count 0 2006.173.03:30:31.45#ibcon#*after write, iclass 37, count 0 2006.173.03:30:31.45#ibcon#*before return 0, iclass 37, count 0 2006.173.03:30:31.45#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.03:30:31.45#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.173.03:30:31.45#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.03:30:31.45#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.03:30:31.45$vck44/valo=7,864.99 2006.173.03:30:31.45#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.03:30:31.45#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.03:30:31.45#ibcon#ireg 17 cls_cnt 0 2006.173.03:30:31.45#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.03:30:31.45#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.03:30:31.45#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.03:30:31.45#ibcon#enter wrdev, iclass 39, count 0 2006.173.03:30:31.45#ibcon#first serial, iclass 39, count 0 2006.173.03:30:31.45#ibcon#enter sib2, iclass 39, count 0 2006.173.03:30:31.45#ibcon#flushed, iclass 39, count 0 2006.173.03:30:31.45#ibcon#about to write, iclass 39, count 0 2006.173.03:30:31.45#ibcon#wrote, iclass 39, count 0 2006.173.03:30:31.45#ibcon#about to read 3, iclass 39, count 0 2006.173.03:30:31.47#ibcon#read 3, iclass 39, count 0 2006.173.03:30:31.47#ibcon#about to read 4, iclass 39, count 0 2006.173.03:30:31.47#ibcon#read 4, iclass 39, count 0 2006.173.03:30:31.47#ibcon#about to read 5, iclass 39, count 0 2006.173.03:30:31.47#ibcon#read 5, iclass 39, count 0 2006.173.03:30:31.47#ibcon#about to read 6, iclass 39, count 0 2006.173.03:30:31.47#ibcon#read 6, iclass 39, count 0 2006.173.03:30:31.47#ibcon#end of sib2, iclass 39, count 0 2006.173.03:30:31.47#ibcon#*mode == 0, iclass 39, count 0 2006.173.03:30:31.47#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.03:30:31.47#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.03:30:31.47#ibcon#*before write, iclass 39, count 0 2006.173.03:30:31.47#ibcon#enter sib2, iclass 39, count 0 2006.173.03:30:31.47#ibcon#flushed, iclass 39, count 0 2006.173.03:30:31.47#ibcon#about to write, iclass 39, count 0 2006.173.03:30:31.47#ibcon#wrote, iclass 39, count 0 2006.173.03:30:31.47#ibcon#about to read 3, iclass 39, count 0 2006.173.03:30:31.51#ibcon#read 3, iclass 39, count 0 2006.173.03:30:31.51#ibcon#about to read 4, iclass 39, count 0 2006.173.03:30:31.51#ibcon#read 4, iclass 39, count 0 2006.173.03:30:31.51#ibcon#about to read 5, iclass 39, count 0 2006.173.03:30:31.51#ibcon#read 5, iclass 39, count 0 2006.173.03:30:31.51#ibcon#about to read 6, iclass 39, count 0 2006.173.03:30:31.51#ibcon#read 6, iclass 39, count 0 2006.173.03:30:31.51#ibcon#end of sib2, iclass 39, count 0 2006.173.03:30:31.51#ibcon#*after write, iclass 39, count 0 2006.173.03:30:31.51#ibcon#*before return 0, iclass 39, count 0 2006.173.03:30:31.51#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.03:30:31.51#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.03:30:31.51#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.03:30:31.51#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.03:30:31.51$vck44/va=7,4 2006.173.03:30:31.51#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.03:30:31.51#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.03:30:31.51#ibcon#ireg 11 cls_cnt 2 2006.173.03:30:31.51#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.03:30:31.57#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.03:30:31.57#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.03:30:31.57#ibcon#enter wrdev, iclass 3, count 2 2006.173.03:30:31.57#ibcon#first serial, iclass 3, count 2 2006.173.03:30:31.57#ibcon#enter sib2, iclass 3, count 2 2006.173.03:30:31.57#ibcon#flushed, iclass 3, count 2 2006.173.03:30:31.57#ibcon#about to write, iclass 3, count 2 2006.173.03:30:31.57#ibcon#wrote, iclass 3, count 2 2006.173.03:30:31.57#ibcon#about to read 3, iclass 3, count 2 2006.173.03:30:31.59#ibcon#read 3, iclass 3, count 2 2006.173.03:30:31.59#ibcon#about to read 4, iclass 3, count 2 2006.173.03:30:31.59#ibcon#read 4, iclass 3, count 2 2006.173.03:30:31.59#ibcon#about to read 5, iclass 3, count 2 2006.173.03:30:31.59#ibcon#read 5, iclass 3, count 2 2006.173.03:30:31.59#ibcon#about to read 6, iclass 3, count 2 2006.173.03:30:31.59#ibcon#read 6, iclass 3, count 2 2006.173.03:30:31.59#ibcon#end of sib2, iclass 3, count 2 2006.173.03:30:31.59#ibcon#*mode == 0, iclass 3, count 2 2006.173.03:30:31.59#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.03:30:31.59#ibcon#[25=AT07-04\r\n] 2006.173.03:30:31.59#ibcon#*before write, iclass 3, count 2 2006.173.03:30:31.59#ibcon#enter sib2, iclass 3, count 2 2006.173.03:30:31.59#ibcon#flushed, iclass 3, count 2 2006.173.03:30:31.59#ibcon#about to write, iclass 3, count 2 2006.173.03:30:31.59#ibcon#wrote, iclass 3, count 2 2006.173.03:30:31.59#ibcon#about to read 3, iclass 3, count 2 2006.173.03:30:31.62#ibcon#read 3, iclass 3, count 2 2006.173.03:30:31.62#ibcon#about to read 4, iclass 3, count 2 2006.173.03:30:31.62#ibcon#read 4, iclass 3, count 2 2006.173.03:30:31.62#ibcon#about to read 5, iclass 3, count 2 2006.173.03:30:31.62#ibcon#read 5, iclass 3, count 2 2006.173.03:30:31.62#ibcon#about to read 6, iclass 3, count 2 2006.173.03:30:31.62#ibcon#read 6, iclass 3, count 2 2006.173.03:30:31.62#ibcon#end of sib2, iclass 3, count 2 2006.173.03:30:31.62#ibcon#*after write, iclass 3, count 2 2006.173.03:30:31.62#ibcon#*before return 0, iclass 3, count 2 2006.173.03:30:31.62#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.03:30:31.62#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.03:30:31.62#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.03:30:31.62#ibcon#ireg 7 cls_cnt 0 2006.173.03:30:31.62#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.03:30:31.74#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.03:30:31.74#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.03:30:31.74#ibcon#enter wrdev, iclass 3, count 0 2006.173.03:30:31.74#ibcon#first serial, iclass 3, count 0 2006.173.03:30:31.74#ibcon#enter sib2, iclass 3, count 0 2006.173.03:30:31.74#ibcon#flushed, iclass 3, count 0 2006.173.03:30:31.74#ibcon#about to write, iclass 3, count 0 2006.173.03:30:31.74#ibcon#wrote, iclass 3, count 0 2006.173.03:30:31.74#ibcon#about to read 3, iclass 3, count 0 2006.173.03:30:31.76#ibcon#read 3, iclass 3, count 0 2006.173.03:30:31.76#ibcon#about to read 4, iclass 3, count 0 2006.173.03:30:31.76#ibcon#read 4, iclass 3, count 0 2006.173.03:30:31.76#ibcon#about to read 5, iclass 3, count 0 2006.173.03:30:31.76#ibcon#read 5, iclass 3, count 0 2006.173.03:30:31.76#ibcon#about to read 6, iclass 3, count 0 2006.173.03:30:31.76#ibcon#read 6, iclass 3, count 0 2006.173.03:30:31.76#ibcon#end of sib2, iclass 3, count 0 2006.173.03:30:31.76#ibcon#*mode == 0, iclass 3, count 0 2006.173.03:30:31.76#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.03:30:31.76#ibcon#[25=USB\r\n] 2006.173.03:30:31.76#ibcon#*before write, iclass 3, count 0 2006.173.03:30:31.76#ibcon#enter sib2, iclass 3, count 0 2006.173.03:30:31.76#ibcon#flushed, iclass 3, count 0 2006.173.03:30:31.76#ibcon#about to write, iclass 3, count 0 2006.173.03:30:31.76#ibcon#wrote, iclass 3, count 0 2006.173.03:30:31.76#ibcon#about to read 3, iclass 3, count 0 2006.173.03:30:31.79#ibcon#read 3, iclass 3, count 0 2006.173.03:30:31.79#ibcon#about to read 4, iclass 3, count 0 2006.173.03:30:31.79#ibcon#read 4, iclass 3, count 0 2006.173.03:30:31.79#ibcon#about to read 5, iclass 3, count 0 2006.173.03:30:31.79#ibcon#read 5, iclass 3, count 0 2006.173.03:30:31.79#ibcon#about to read 6, iclass 3, count 0 2006.173.03:30:31.79#ibcon#read 6, iclass 3, count 0 2006.173.03:30:31.79#ibcon#end of sib2, iclass 3, count 0 2006.173.03:30:31.79#ibcon#*after write, iclass 3, count 0 2006.173.03:30:31.79#ibcon#*before return 0, iclass 3, count 0 2006.173.03:30:31.79#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.03:30:31.79#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.03:30:31.79#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.03:30:31.79#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.03:30:31.79$vck44/valo=8,884.99 2006.173.03:30:31.79#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.03:30:31.79#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.03:30:31.79#ibcon#ireg 17 cls_cnt 0 2006.173.03:30:31.79#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.03:30:31.79#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.03:30:31.79#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.03:30:31.79#ibcon#enter wrdev, iclass 5, count 0 2006.173.03:30:31.79#ibcon#first serial, iclass 5, count 0 2006.173.03:30:31.79#ibcon#enter sib2, iclass 5, count 0 2006.173.03:30:31.79#ibcon#flushed, iclass 5, count 0 2006.173.03:30:31.79#ibcon#about to write, iclass 5, count 0 2006.173.03:30:31.79#ibcon#wrote, iclass 5, count 0 2006.173.03:30:31.79#ibcon#about to read 3, iclass 5, count 0 2006.173.03:30:31.81#ibcon#read 3, iclass 5, count 0 2006.173.03:30:31.81#ibcon#about to read 4, iclass 5, count 0 2006.173.03:30:31.81#ibcon#read 4, iclass 5, count 0 2006.173.03:30:31.81#ibcon#about to read 5, iclass 5, count 0 2006.173.03:30:31.81#ibcon#read 5, iclass 5, count 0 2006.173.03:30:31.81#ibcon#about to read 6, iclass 5, count 0 2006.173.03:30:31.81#ibcon#read 6, iclass 5, count 0 2006.173.03:30:31.81#ibcon#end of sib2, iclass 5, count 0 2006.173.03:30:31.81#ibcon#*mode == 0, iclass 5, count 0 2006.173.03:30:31.81#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.03:30:31.81#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.03:30:31.81#ibcon#*before write, iclass 5, count 0 2006.173.03:30:31.81#ibcon#enter sib2, iclass 5, count 0 2006.173.03:30:31.81#ibcon#flushed, iclass 5, count 0 2006.173.03:30:31.81#ibcon#about to write, iclass 5, count 0 2006.173.03:30:31.81#ibcon#wrote, iclass 5, count 0 2006.173.03:30:31.81#ibcon#about to read 3, iclass 5, count 0 2006.173.03:30:31.85#ibcon#read 3, iclass 5, count 0 2006.173.03:30:31.85#ibcon#about to read 4, iclass 5, count 0 2006.173.03:30:31.85#ibcon#read 4, iclass 5, count 0 2006.173.03:30:31.85#ibcon#about to read 5, iclass 5, count 0 2006.173.03:30:31.85#ibcon#read 5, iclass 5, count 0 2006.173.03:30:31.85#ibcon#about to read 6, iclass 5, count 0 2006.173.03:30:31.85#ibcon#read 6, iclass 5, count 0 2006.173.03:30:31.85#ibcon#end of sib2, iclass 5, count 0 2006.173.03:30:31.85#ibcon#*after write, iclass 5, count 0 2006.173.03:30:31.85#ibcon#*before return 0, iclass 5, count 0 2006.173.03:30:31.85#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.03:30:31.85#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.03:30:31.85#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.03:30:31.85#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.03:30:31.85$vck44/va=8,4 2006.173.03:30:31.85#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.173.03:30:31.85#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.173.03:30:31.85#ibcon#ireg 11 cls_cnt 2 2006.173.03:30:31.85#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.03:30:31.91#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.03:30:31.91#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.03:30:31.91#ibcon#enter wrdev, iclass 7, count 2 2006.173.03:30:31.91#ibcon#first serial, iclass 7, count 2 2006.173.03:30:31.91#ibcon#enter sib2, iclass 7, count 2 2006.173.03:30:31.91#ibcon#flushed, iclass 7, count 2 2006.173.03:30:31.91#ibcon#about to write, iclass 7, count 2 2006.173.03:30:31.91#ibcon#wrote, iclass 7, count 2 2006.173.03:30:31.91#ibcon#about to read 3, iclass 7, count 2 2006.173.03:30:31.93#ibcon#read 3, iclass 7, count 2 2006.173.03:30:31.93#ibcon#about to read 4, iclass 7, count 2 2006.173.03:30:31.93#ibcon#read 4, iclass 7, count 2 2006.173.03:30:31.93#ibcon#about to read 5, iclass 7, count 2 2006.173.03:30:31.93#ibcon#read 5, iclass 7, count 2 2006.173.03:30:31.93#ibcon#about to read 6, iclass 7, count 2 2006.173.03:30:31.93#ibcon#read 6, iclass 7, count 2 2006.173.03:30:31.93#ibcon#end of sib2, iclass 7, count 2 2006.173.03:30:31.93#ibcon#*mode == 0, iclass 7, count 2 2006.173.03:30:31.93#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.173.03:30:31.93#ibcon#[25=AT08-04\r\n] 2006.173.03:30:31.93#ibcon#*before write, iclass 7, count 2 2006.173.03:30:31.93#ibcon#enter sib2, iclass 7, count 2 2006.173.03:30:31.93#ibcon#flushed, iclass 7, count 2 2006.173.03:30:31.93#ibcon#about to write, iclass 7, count 2 2006.173.03:30:31.93#ibcon#wrote, iclass 7, count 2 2006.173.03:30:31.93#ibcon#about to read 3, iclass 7, count 2 2006.173.03:30:31.96#ibcon#read 3, iclass 7, count 2 2006.173.03:30:31.96#ibcon#about to read 4, iclass 7, count 2 2006.173.03:30:31.96#ibcon#read 4, iclass 7, count 2 2006.173.03:30:31.96#ibcon#about to read 5, iclass 7, count 2 2006.173.03:30:31.96#ibcon#read 5, iclass 7, count 2 2006.173.03:30:31.96#ibcon#about to read 6, iclass 7, count 2 2006.173.03:30:31.96#ibcon#read 6, iclass 7, count 2 2006.173.03:30:31.96#ibcon#end of sib2, iclass 7, count 2 2006.173.03:30:31.96#ibcon#*after write, iclass 7, count 2 2006.173.03:30:31.96#ibcon#*before return 0, iclass 7, count 2 2006.173.03:30:31.96#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.03:30:31.96#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.173.03:30:31.96#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.173.03:30:31.96#ibcon#ireg 7 cls_cnt 0 2006.173.03:30:31.96#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.03:30:32.08#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.03:30:32.08#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.03:30:32.08#ibcon#enter wrdev, iclass 7, count 0 2006.173.03:30:32.08#ibcon#first serial, iclass 7, count 0 2006.173.03:30:32.08#ibcon#enter sib2, iclass 7, count 0 2006.173.03:30:32.08#ibcon#flushed, iclass 7, count 0 2006.173.03:30:32.08#ibcon#about to write, iclass 7, count 0 2006.173.03:30:32.08#ibcon#wrote, iclass 7, count 0 2006.173.03:30:32.08#ibcon#about to read 3, iclass 7, count 0 2006.173.03:30:32.10#ibcon#read 3, iclass 7, count 0 2006.173.03:30:32.10#ibcon#about to read 4, iclass 7, count 0 2006.173.03:30:32.10#ibcon#read 4, iclass 7, count 0 2006.173.03:30:32.10#ibcon#about to read 5, iclass 7, count 0 2006.173.03:30:32.10#ibcon#read 5, iclass 7, count 0 2006.173.03:30:32.10#ibcon#about to read 6, iclass 7, count 0 2006.173.03:30:32.10#ibcon#read 6, iclass 7, count 0 2006.173.03:30:32.10#ibcon#end of sib2, iclass 7, count 0 2006.173.03:30:32.10#ibcon#*mode == 0, iclass 7, count 0 2006.173.03:30:32.10#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.03:30:32.10#ibcon#[25=USB\r\n] 2006.173.03:30:32.10#ibcon#*before write, iclass 7, count 0 2006.173.03:30:32.10#ibcon#enter sib2, iclass 7, count 0 2006.173.03:30:32.10#ibcon#flushed, iclass 7, count 0 2006.173.03:30:32.10#ibcon#about to write, iclass 7, count 0 2006.173.03:30:32.10#ibcon#wrote, iclass 7, count 0 2006.173.03:30:32.10#ibcon#about to read 3, iclass 7, count 0 2006.173.03:30:32.13#ibcon#read 3, iclass 7, count 0 2006.173.03:30:32.13#ibcon#about to read 4, iclass 7, count 0 2006.173.03:30:32.13#ibcon#read 4, iclass 7, count 0 2006.173.03:30:32.13#ibcon#about to read 5, iclass 7, count 0 2006.173.03:30:32.13#ibcon#read 5, iclass 7, count 0 2006.173.03:30:32.13#ibcon#about to read 6, iclass 7, count 0 2006.173.03:30:32.13#ibcon#read 6, iclass 7, count 0 2006.173.03:30:32.13#ibcon#end of sib2, iclass 7, count 0 2006.173.03:30:32.13#ibcon#*after write, iclass 7, count 0 2006.173.03:30:32.13#ibcon#*before return 0, iclass 7, count 0 2006.173.03:30:32.13#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.03:30:32.13#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.173.03:30:32.13#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.03:30:32.13#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.03:30:32.13$vck44/vblo=1,629.99 2006.173.03:30:32.13#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.03:30:32.13#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.03:30:32.13#ibcon#ireg 17 cls_cnt 0 2006.173.03:30:32.13#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.03:30:32.13#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.03:30:32.13#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.03:30:32.13#ibcon#enter wrdev, iclass 11, count 0 2006.173.03:30:32.13#ibcon#first serial, iclass 11, count 0 2006.173.03:30:32.13#ibcon#enter sib2, iclass 11, count 0 2006.173.03:30:32.13#ibcon#flushed, iclass 11, count 0 2006.173.03:30:32.13#ibcon#about to write, iclass 11, count 0 2006.173.03:30:32.13#ibcon#wrote, iclass 11, count 0 2006.173.03:30:32.13#ibcon#about to read 3, iclass 11, count 0 2006.173.03:30:32.15#ibcon#read 3, iclass 11, count 0 2006.173.03:30:32.15#ibcon#about to read 4, iclass 11, count 0 2006.173.03:30:32.15#ibcon#read 4, iclass 11, count 0 2006.173.03:30:32.15#ibcon#about to read 5, iclass 11, count 0 2006.173.03:30:32.15#ibcon#read 5, iclass 11, count 0 2006.173.03:30:32.15#ibcon#about to read 6, iclass 11, count 0 2006.173.03:30:32.15#ibcon#read 6, iclass 11, count 0 2006.173.03:30:32.15#ibcon#end of sib2, iclass 11, count 0 2006.173.03:30:32.15#ibcon#*mode == 0, iclass 11, count 0 2006.173.03:30:32.15#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.03:30:32.15#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.03:30:32.15#ibcon#*before write, iclass 11, count 0 2006.173.03:30:32.15#ibcon#enter sib2, iclass 11, count 0 2006.173.03:30:32.15#ibcon#flushed, iclass 11, count 0 2006.173.03:30:32.15#ibcon#about to write, iclass 11, count 0 2006.173.03:30:32.15#ibcon#wrote, iclass 11, count 0 2006.173.03:30:32.15#ibcon#about to read 3, iclass 11, count 0 2006.173.03:30:32.19#ibcon#read 3, iclass 11, count 0 2006.173.03:30:32.19#ibcon#about to read 4, iclass 11, count 0 2006.173.03:30:32.19#ibcon#read 4, iclass 11, count 0 2006.173.03:30:32.19#ibcon#about to read 5, iclass 11, count 0 2006.173.03:30:32.19#ibcon#read 5, iclass 11, count 0 2006.173.03:30:32.19#ibcon#about to read 6, iclass 11, count 0 2006.173.03:30:32.19#ibcon#read 6, iclass 11, count 0 2006.173.03:30:32.19#ibcon#end of sib2, iclass 11, count 0 2006.173.03:30:32.19#ibcon#*after write, iclass 11, count 0 2006.173.03:30:32.19#ibcon#*before return 0, iclass 11, count 0 2006.173.03:30:32.19#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.03:30:32.19#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.03:30:32.19#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.03:30:32.19#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.03:30:32.19$vck44/vb=1,4 2006.173.03:30:32.19#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.173.03:30:32.19#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.173.03:30:32.19#ibcon#ireg 11 cls_cnt 2 2006.173.03:30:32.19#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.03:30:32.19#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.03:30:32.19#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.03:30:32.19#ibcon#enter wrdev, iclass 13, count 2 2006.173.03:30:32.19#ibcon#first serial, iclass 13, count 2 2006.173.03:30:32.19#ibcon#enter sib2, iclass 13, count 2 2006.173.03:30:32.19#ibcon#flushed, iclass 13, count 2 2006.173.03:30:32.19#ibcon#about to write, iclass 13, count 2 2006.173.03:30:32.19#ibcon#wrote, iclass 13, count 2 2006.173.03:30:32.19#ibcon#about to read 3, iclass 13, count 2 2006.173.03:30:32.21#ibcon#read 3, iclass 13, count 2 2006.173.03:30:32.21#ibcon#about to read 4, iclass 13, count 2 2006.173.03:30:32.21#ibcon#read 4, iclass 13, count 2 2006.173.03:30:32.21#ibcon#about to read 5, iclass 13, count 2 2006.173.03:30:32.21#ibcon#read 5, iclass 13, count 2 2006.173.03:30:32.21#ibcon#about to read 6, iclass 13, count 2 2006.173.03:30:32.21#ibcon#read 6, iclass 13, count 2 2006.173.03:30:32.21#ibcon#end of sib2, iclass 13, count 2 2006.173.03:30:32.21#ibcon#*mode == 0, iclass 13, count 2 2006.173.03:30:32.21#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.173.03:30:32.21#ibcon#[27=AT01-04\r\n] 2006.173.03:30:32.21#ibcon#*before write, iclass 13, count 2 2006.173.03:30:32.21#ibcon#enter sib2, iclass 13, count 2 2006.173.03:30:32.21#ibcon#flushed, iclass 13, count 2 2006.173.03:30:32.21#ibcon#about to write, iclass 13, count 2 2006.173.03:30:32.21#ibcon#wrote, iclass 13, count 2 2006.173.03:30:32.21#ibcon#about to read 3, iclass 13, count 2 2006.173.03:30:32.24#ibcon#read 3, iclass 13, count 2 2006.173.03:30:32.24#ibcon#about to read 4, iclass 13, count 2 2006.173.03:30:32.24#ibcon#read 4, iclass 13, count 2 2006.173.03:30:32.24#ibcon#about to read 5, iclass 13, count 2 2006.173.03:30:32.24#ibcon#read 5, iclass 13, count 2 2006.173.03:30:32.24#ibcon#about to read 6, iclass 13, count 2 2006.173.03:30:32.24#ibcon#read 6, iclass 13, count 2 2006.173.03:30:32.24#ibcon#end of sib2, iclass 13, count 2 2006.173.03:30:32.24#ibcon#*after write, iclass 13, count 2 2006.173.03:30:32.24#ibcon#*before return 0, iclass 13, count 2 2006.173.03:30:32.24#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.03:30:32.24#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.173.03:30:32.24#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.173.03:30:32.24#ibcon#ireg 7 cls_cnt 0 2006.173.03:30:32.24#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.03:30:32.36#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.03:30:32.36#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.03:30:32.36#ibcon#enter wrdev, iclass 13, count 0 2006.173.03:30:32.36#ibcon#first serial, iclass 13, count 0 2006.173.03:30:32.36#ibcon#enter sib2, iclass 13, count 0 2006.173.03:30:32.36#ibcon#flushed, iclass 13, count 0 2006.173.03:30:32.36#ibcon#about to write, iclass 13, count 0 2006.173.03:30:32.36#ibcon#wrote, iclass 13, count 0 2006.173.03:30:32.36#ibcon#about to read 3, iclass 13, count 0 2006.173.03:30:32.38#ibcon#read 3, iclass 13, count 0 2006.173.03:30:32.38#ibcon#about to read 4, iclass 13, count 0 2006.173.03:30:32.38#ibcon#read 4, iclass 13, count 0 2006.173.03:30:32.38#ibcon#about to read 5, iclass 13, count 0 2006.173.03:30:32.38#ibcon#read 5, iclass 13, count 0 2006.173.03:30:32.38#ibcon#about to read 6, iclass 13, count 0 2006.173.03:30:32.38#ibcon#read 6, iclass 13, count 0 2006.173.03:30:32.38#ibcon#end of sib2, iclass 13, count 0 2006.173.03:30:32.38#ibcon#*mode == 0, iclass 13, count 0 2006.173.03:30:32.38#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.03:30:32.38#ibcon#[27=USB\r\n] 2006.173.03:30:32.38#ibcon#*before write, iclass 13, count 0 2006.173.03:30:32.38#ibcon#enter sib2, iclass 13, count 0 2006.173.03:30:32.38#ibcon#flushed, iclass 13, count 0 2006.173.03:30:32.38#ibcon#about to write, iclass 13, count 0 2006.173.03:30:32.38#ibcon#wrote, iclass 13, count 0 2006.173.03:30:32.38#ibcon#about to read 3, iclass 13, count 0 2006.173.03:30:32.41#ibcon#read 3, iclass 13, count 0 2006.173.03:30:32.41#ibcon#about to read 4, iclass 13, count 0 2006.173.03:30:32.41#ibcon#read 4, iclass 13, count 0 2006.173.03:30:32.41#ibcon#about to read 5, iclass 13, count 0 2006.173.03:30:32.41#ibcon#read 5, iclass 13, count 0 2006.173.03:30:32.41#ibcon#about to read 6, iclass 13, count 0 2006.173.03:30:32.41#ibcon#read 6, iclass 13, count 0 2006.173.03:30:32.41#ibcon#end of sib2, iclass 13, count 0 2006.173.03:30:32.41#ibcon#*after write, iclass 13, count 0 2006.173.03:30:32.41#ibcon#*before return 0, iclass 13, count 0 2006.173.03:30:32.41#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.03:30:32.41#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.173.03:30:32.41#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.03:30:32.41#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.03:30:32.41$vck44/vblo=2,634.99 2006.173.03:30:32.41#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.03:30:32.41#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.03:30:32.41#ibcon#ireg 17 cls_cnt 0 2006.173.03:30:32.41#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.03:30:32.41#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.03:30:32.41#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.03:30:32.41#ibcon#enter wrdev, iclass 15, count 0 2006.173.03:30:32.41#ibcon#first serial, iclass 15, count 0 2006.173.03:30:32.41#ibcon#enter sib2, iclass 15, count 0 2006.173.03:30:32.41#ibcon#flushed, iclass 15, count 0 2006.173.03:30:32.41#ibcon#about to write, iclass 15, count 0 2006.173.03:30:32.41#ibcon#wrote, iclass 15, count 0 2006.173.03:30:32.41#ibcon#about to read 3, iclass 15, count 0 2006.173.03:30:32.43#ibcon#read 3, iclass 15, count 0 2006.173.03:30:32.43#ibcon#about to read 4, iclass 15, count 0 2006.173.03:30:32.43#ibcon#read 4, iclass 15, count 0 2006.173.03:30:32.43#ibcon#about to read 5, iclass 15, count 0 2006.173.03:30:32.43#ibcon#read 5, iclass 15, count 0 2006.173.03:30:32.43#ibcon#about to read 6, iclass 15, count 0 2006.173.03:30:32.43#ibcon#read 6, iclass 15, count 0 2006.173.03:30:32.43#ibcon#end of sib2, iclass 15, count 0 2006.173.03:30:32.43#ibcon#*mode == 0, iclass 15, count 0 2006.173.03:30:32.43#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.03:30:32.43#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.03:30:32.43#ibcon#*before write, iclass 15, count 0 2006.173.03:30:32.43#ibcon#enter sib2, iclass 15, count 0 2006.173.03:30:32.43#ibcon#flushed, iclass 15, count 0 2006.173.03:30:32.43#ibcon#about to write, iclass 15, count 0 2006.173.03:30:32.43#ibcon#wrote, iclass 15, count 0 2006.173.03:30:32.43#ibcon#about to read 3, iclass 15, count 0 2006.173.03:30:32.47#ibcon#read 3, iclass 15, count 0 2006.173.03:30:32.47#ibcon#about to read 4, iclass 15, count 0 2006.173.03:30:32.47#ibcon#read 4, iclass 15, count 0 2006.173.03:30:32.47#ibcon#about to read 5, iclass 15, count 0 2006.173.03:30:32.47#ibcon#read 5, iclass 15, count 0 2006.173.03:30:32.47#ibcon#about to read 6, iclass 15, count 0 2006.173.03:30:32.47#ibcon#read 6, iclass 15, count 0 2006.173.03:30:32.47#ibcon#end of sib2, iclass 15, count 0 2006.173.03:30:32.47#ibcon#*after write, iclass 15, count 0 2006.173.03:30:32.47#ibcon#*before return 0, iclass 15, count 0 2006.173.03:30:32.47#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.03:30:32.47#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.03:30:32.47#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.03:30:32.47#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.03:30:32.47$vck44/vb=2,4 2006.173.03:30:32.47#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.03:30:32.47#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.03:30:32.47#ibcon#ireg 11 cls_cnt 2 2006.173.03:30:32.47#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.03:30:32.53#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.03:30:32.53#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.03:30:32.53#ibcon#enter wrdev, iclass 17, count 2 2006.173.03:30:32.53#ibcon#first serial, iclass 17, count 2 2006.173.03:30:32.53#ibcon#enter sib2, iclass 17, count 2 2006.173.03:30:32.53#ibcon#flushed, iclass 17, count 2 2006.173.03:30:32.53#ibcon#about to write, iclass 17, count 2 2006.173.03:30:32.53#ibcon#wrote, iclass 17, count 2 2006.173.03:30:32.53#ibcon#about to read 3, iclass 17, count 2 2006.173.03:30:32.55#ibcon#read 3, iclass 17, count 2 2006.173.03:30:32.55#ibcon#about to read 4, iclass 17, count 2 2006.173.03:30:32.55#ibcon#read 4, iclass 17, count 2 2006.173.03:30:32.55#ibcon#about to read 5, iclass 17, count 2 2006.173.03:30:32.55#ibcon#read 5, iclass 17, count 2 2006.173.03:30:32.55#ibcon#about to read 6, iclass 17, count 2 2006.173.03:30:32.55#ibcon#read 6, iclass 17, count 2 2006.173.03:30:32.55#ibcon#end of sib2, iclass 17, count 2 2006.173.03:30:32.55#ibcon#*mode == 0, iclass 17, count 2 2006.173.03:30:32.55#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.03:30:32.55#ibcon#[27=AT02-04\r\n] 2006.173.03:30:32.55#ibcon#*before write, iclass 17, count 2 2006.173.03:30:32.55#ibcon#enter sib2, iclass 17, count 2 2006.173.03:30:32.55#ibcon#flushed, iclass 17, count 2 2006.173.03:30:32.55#ibcon#about to write, iclass 17, count 2 2006.173.03:30:32.55#ibcon#wrote, iclass 17, count 2 2006.173.03:30:32.55#ibcon#about to read 3, iclass 17, count 2 2006.173.03:30:32.58#ibcon#read 3, iclass 17, count 2 2006.173.03:30:32.58#ibcon#about to read 4, iclass 17, count 2 2006.173.03:30:32.58#ibcon#read 4, iclass 17, count 2 2006.173.03:30:32.58#ibcon#about to read 5, iclass 17, count 2 2006.173.03:30:32.58#ibcon#read 5, iclass 17, count 2 2006.173.03:30:32.58#ibcon#about to read 6, iclass 17, count 2 2006.173.03:30:32.58#ibcon#read 6, iclass 17, count 2 2006.173.03:30:32.58#ibcon#end of sib2, iclass 17, count 2 2006.173.03:30:32.58#ibcon#*after write, iclass 17, count 2 2006.173.03:30:32.58#ibcon#*before return 0, iclass 17, count 2 2006.173.03:30:32.58#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.03:30:32.58#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.03:30:32.58#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.03:30:32.58#ibcon#ireg 7 cls_cnt 0 2006.173.03:30:32.58#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.03:30:32.70#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.03:30:32.70#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.03:30:32.70#ibcon#enter wrdev, iclass 17, count 0 2006.173.03:30:32.70#ibcon#first serial, iclass 17, count 0 2006.173.03:30:32.70#ibcon#enter sib2, iclass 17, count 0 2006.173.03:30:32.70#ibcon#flushed, iclass 17, count 0 2006.173.03:30:32.70#ibcon#about to write, iclass 17, count 0 2006.173.03:30:32.70#ibcon#wrote, iclass 17, count 0 2006.173.03:30:32.70#ibcon#about to read 3, iclass 17, count 0 2006.173.03:30:32.72#ibcon#read 3, iclass 17, count 0 2006.173.03:30:32.72#ibcon#about to read 4, iclass 17, count 0 2006.173.03:30:32.72#ibcon#read 4, iclass 17, count 0 2006.173.03:30:32.72#ibcon#about to read 5, iclass 17, count 0 2006.173.03:30:32.72#ibcon#read 5, iclass 17, count 0 2006.173.03:30:32.72#ibcon#about to read 6, iclass 17, count 0 2006.173.03:30:32.72#ibcon#read 6, iclass 17, count 0 2006.173.03:30:32.72#ibcon#end of sib2, iclass 17, count 0 2006.173.03:30:32.72#ibcon#*mode == 0, iclass 17, count 0 2006.173.03:30:32.72#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.03:30:32.72#ibcon#[27=USB\r\n] 2006.173.03:30:32.72#ibcon#*before write, iclass 17, count 0 2006.173.03:30:32.72#ibcon#enter sib2, iclass 17, count 0 2006.173.03:30:32.72#ibcon#flushed, iclass 17, count 0 2006.173.03:30:32.72#ibcon#about to write, iclass 17, count 0 2006.173.03:30:32.72#ibcon#wrote, iclass 17, count 0 2006.173.03:30:32.72#ibcon#about to read 3, iclass 17, count 0 2006.173.03:30:32.75#ibcon#read 3, iclass 17, count 0 2006.173.03:30:32.75#ibcon#about to read 4, iclass 17, count 0 2006.173.03:30:32.75#ibcon#read 4, iclass 17, count 0 2006.173.03:30:32.75#ibcon#about to read 5, iclass 17, count 0 2006.173.03:30:32.75#ibcon#read 5, iclass 17, count 0 2006.173.03:30:32.75#ibcon#about to read 6, iclass 17, count 0 2006.173.03:30:32.75#ibcon#read 6, iclass 17, count 0 2006.173.03:30:32.75#ibcon#end of sib2, iclass 17, count 0 2006.173.03:30:32.75#ibcon#*after write, iclass 17, count 0 2006.173.03:30:32.75#ibcon#*before return 0, iclass 17, count 0 2006.173.03:30:32.75#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.03:30:32.75#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.03:30:32.75#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.03:30:32.75#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.03:30:32.75$vck44/vblo=3,649.99 2006.173.03:30:32.75#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.03:30:32.75#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.03:30:32.75#ibcon#ireg 17 cls_cnt 0 2006.173.03:30:32.75#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.03:30:32.75#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.03:30:32.75#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.03:30:32.75#ibcon#enter wrdev, iclass 19, count 0 2006.173.03:30:32.75#ibcon#first serial, iclass 19, count 0 2006.173.03:30:32.75#ibcon#enter sib2, iclass 19, count 0 2006.173.03:30:32.75#ibcon#flushed, iclass 19, count 0 2006.173.03:30:32.75#ibcon#about to write, iclass 19, count 0 2006.173.03:30:32.75#ibcon#wrote, iclass 19, count 0 2006.173.03:30:32.75#ibcon#about to read 3, iclass 19, count 0 2006.173.03:30:32.77#ibcon#read 3, iclass 19, count 0 2006.173.03:30:32.77#ibcon#about to read 4, iclass 19, count 0 2006.173.03:30:32.77#ibcon#read 4, iclass 19, count 0 2006.173.03:30:32.77#ibcon#about to read 5, iclass 19, count 0 2006.173.03:30:32.77#ibcon#read 5, iclass 19, count 0 2006.173.03:30:32.77#ibcon#about to read 6, iclass 19, count 0 2006.173.03:30:32.77#ibcon#read 6, iclass 19, count 0 2006.173.03:30:32.77#ibcon#end of sib2, iclass 19, count 0 2006.173.03:30:32.77#ibcon#*mode == 0, iclass 19, count 0 2006.173.03:30:32.77#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.03:30:32.77#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.03:30:32.77#ibcon#*before write, iclass 19, count 0 2006.173.03:30:32.77#ibcon#enter sib2, iclass 19, count 0 2006.173.03:30:32.77#ibcon#flushed, iclass 19, count 0 2006.173.03:30:32.77#ibcon#about to write, iclass 19, count 0 2006.173.03:30:32.77#ibcon#wrote, iclass 19, count 0 2006.173.03:30:32.77#ibcon#about to read 3, iclass 19, count 0 2006.173.03:30:32.81#ibcon#read 3, iclass 19, count 0 2006.173.03:30:32.81#ibcon#about to read 4, iclass 19, count 0 2006.173.03:30:32.81#ibcon#read 4, iclass 19, count 0 2006.173.03:30:32.81#ibcon#about to read 5, iclass 19, count 0 2006.173.03:30:32.81#ibcon#read 5, iclass 19, count 0 2006.173.03:30:32.81#ibcon#about to read 6, iclass 19, count 0 2006.173.03:30:32.81#ibcon#read 6, iclass 19, count 0 2006.173.03:30:32.81#ibcon#end of sib2, iclass 19, count 0 2006.173.03:30:32.81#ibcon#*after write, iclass 19, count 0 2006.173.03:30:32.81#ibcon#*before return 0, iclass 19, count 0 2006.173.03:30:32.81#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.03:30:32.81#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.03:30:32.81#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.03:30:32.81#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.03:30:32.81$vck44/vb=3,4 2006.173.03:30:32.81#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.03:30:32.81#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.03:30:32.81#ibcon#ireg 11 cls_cnt 2 2006.173.03:30:32.81#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.03:30:32.87#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.03:30:32.87#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.03:30:32.87#ibcon#enter wrdev, iclass 21, count 2 2006.173.03:30:32.87#ibcon#first serial, iclass 21, count 2 2006.173.03:30:32.87#ibcon#enter sib2, iclass 21, count 2 2006.173.03:30:32.87#ibcon#flushed, iclass 21, count 2 2006.173.03:30:32.87#ibcon#about to write, iclass 21, count 2 2006.173.03:30:32.87#ibcon#wrote, iclass 21, count 2 2006.173.03:30:32.87#ibcon#about to read 3, iclass 21, count 2 2006.173.03:30:32.89#ibcon#read 3, iclass 21, count 2 2006.173.03:30:32.89#ibcon#about to read 4, iclass 21, count 2 2006.173.03:30:32.89#ibcon#read 4, iclass 21, count 2 2006.173.03:30:32.89#ibcon#about to read 5, iclass 21, count 2 2006.173.03:30:32.89#ibcon#read 5, iclass 21, count 2 2006.173.03:30:32.89#ibcon#about to read 6, iclass 21, count 2 2006.173.03:30:32.89#ibcon#read 6, iclass 21, count 2 2006.173.03:30:32.89#ibcon#end of sib2, iclass 21, count 2 2006.173.03:30:32.89#ibcon#*mode == 0, iclass 21, count 2 2006.173.03:30:32.89#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.03:30:32.89#ibcon#[27=AT03-04\r\n] 2006.173.03:30:32.89#ibcon#*before write, iclass 21, count 2 2006.173.03:30:32.89#ibcon#enter sib2, iclass 21, count 2 2006.173.03:30:32.89#ibcon#flushed, iclass 21, count 2 2006.173.03:30:32.89#ibcon#about to write, iclass 21, count 2 2006.173.03:30:32.89#ibcon#wrote, iclass 21, count 2 2006.173.03:30:32.89#ibcon#about to read 3, iclass 21, count 2 2006.173.03:30:32.92#ibcon#read 3, iclass 21, count 2 2006.173.03:30:32.92#ibcon#about to read 4, iclass 21, count 2 2006.173.03:30:32.92#ibcon#read 4, iclass 21, count 2 2006.173.03:30:32.92#ibcon#about to read 5, iclass 21, count 2 2006.173.03:30:32.92#ibcon#read 5, iclass 21, count 2 2006.173.03:30:32.92#ibcon#about to read 6, iclass 21, count 2 2006.173.03:30:32.92#ibcon#read 6, iclass 21, count 2 2006.173.03:30:32.92#ibcon#end of sib2, iclass 21, count 2 2006.173.03:30:32.92#ibcon#*after write, iclass 21, count 2 2006.173.03:30:32.92#ibcon#*before return 0, iclass 21, count 2 2006.173.03:30:32.92#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.03:30:32.92#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.03:30:32.92#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.03:30:32.92#ibcon#ireg 7 cls_cnt 0 2006.173.03:30:32.92#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.03:30:33.04#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.03:30:33.04#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.03:30:33.04#ibcon#enter wrdev, iclass 21, count 0 2006.173.03:30:33.04#ibcon#first serial, iclass 21, count 0 2006.173.03:30:33.04#ibcon#enter sib2, iclass 21, count 0 2006.173.03:30:33.04#ibcon#flushed, iclass 21, count 0 2006.173.03:30:33.04#ibcon#about to write, iclass 21, count 0 2006.173.03:30:33.04#ibcon#wrote, iclass 21, count 0 2006.173.03:30:33.04#ibcon#about to read 3, iclass 21, count 0 2006.173.03:30:33.06#ibcon#read 3, iclass 21, count 0 2006.173.03:30:33.06#ibcon#about to read 4, iclass 21, count 0 2006.173.03:30:33.06#ibcon#read 4, iclass 21, count 0 2006.173.03:30:33.06#ibcon#about to read 5, iclass 21, count 0 2006.173.03:30:33.06#ibcon#read 5, iclass 21, count 0 2006.173.03:30:33.06#ibcon#about to read 6, iclass 21, count 0 2006.173.03:30:33.06#ibcon#read 6, iclass 21, count 0 2006.173.03:30:33.06#ibcon#end of sib2, iclass 21, count 0 2006.173.03:30:33.06#ibcon#*mode == 0, iclass 21, count 0 2006.173.03:30:33.06#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.03:30:33.06#ibcon#[27=USB\r\n] 2006.173.03:30:33.06#ibcon#*before write, iclass 21, count 0 2006.173.03:30:33.06#ibcon#enter sib2, iclass 21, count 0 2006.173.03:30:33.06#ibcon#flushed, iclass 21, count 0 2006.173.03:30:33.06#ibcon#about to write, iclass 21, count 0 2006.173.03:30:33.06#ibcon#wrote, iclass 21, count 0 2006.173.03:30:33.06#ibcon#about to read 3, iclass 21, count 0 2006.173.03:30:33.09#ibcon#read 3, iclass 21, count 0 2006.173.03:30:33.09#ibcon#about to read 4, iclass 21, count 0 2006.173.03:30:33.09#ibcon#read 4, iclass 21, count 0 2006.173.03:30:33.09#ibcon#about to read 5, iclass 21, count 0 2006.173.03:30:33.09#ibcon#read 5, iclass 21, count 0 2006.173.03:30:33.09#ibcon#about to read 6, iclass 21, count 0 2006.173.03:30:33.09#ibcon#read 6, iclass 21, count 0 2006.173.03:30:33.09#ibcon#end of sib2, iclass 21, count 0 2006.173.03:30:33.09#ibcon#*after write, iclass 21, count 0 2006.173.03:30:33.09#ibcon#*before return 0, iclass 21, count 0 2006.173.03:30:33.09#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.03:30:33.09#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.03:30:33.09#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.03:30:33.09#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.03:30:33.09$vck44/vblo=4,679.99 2006.173.03:30:33.09#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.03:30:33.09#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.03:30:33.09#ibcon#ireg 17 cls_cnt 0 2006.173.03:30:33.09#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.03:30:33.09#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.03:30:33.09#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.03:30:33.09#ibcon#enter wrdev, iclass 23, count 0 2006.173.03:30:33.09#ibcon#first serial, iclass 23, count 0 2006.173.03:30:33.09#ibcon#enter sib2, iclass 23, count 0 2006.173.03:30:33.09#ibcon#flushed, iclass 23, count 0 2006.173.03:30:33.09#ibcon#about to write, iclass 23, count 0 2006.173.03:30:33.09#ibcon#wrote, iclass 23, count 0 2006.173.03:30:33.09#ibcon#about to read 3, iclass 23, count 0 2006.173.03:30:33.11#ibcon#read 3, iclass 23, count 0 2006.173.03:30:33.11#ibcon#about to read 4, iclass 23, count 0 2006.173.03:30:33.11#ibcon#read 4, iclass 23, count 0 2006.173.03:30:33.11#ibcon#about to read 5, iclass 23, count 0 2006.173.03:30:33.11#ibcon#read 5, iclass 23, count 0 2006.173.03:30:33.11#ibcon#about to read 6, iclass 23, count 0 2006.173.03:30:33.11#ibcon#read 6, iclass 23, count 0 2006.173.03:30:33.11#ibcon#end of sib2, iclass 23, count 0 2006.173.03:30:33.11#ibcon#*mode == 0, iclass 23, count 0 2006.173.03:30:33.11#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.03:30:33.11#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.03:30:33.11#ibcon#*before write, iclass 23, count 0 2006.173.03:30:33.11#ibcon#enter sib2, iclass 23, count 0 2006.173.03:30:33.11#ibcon#flushed, iclass 23, count 0 2006.173.03:30:33.11#ibcon#about to write, iclass 23, count 0 2006.173.03:30:33.11#ibcon#wrote, iclass 23, count 0 2006.173.03:30:33.11#ibcon#about to read 3, iclass 23, count 0 2006.173.03:30:33.15#ibcon#read 3, iclass 23, count 0 2006.173.03:30:33.15#ibcon#about to read 4, iclass 23, count 0 2006.173.03:30:33.15#ibcon#read 4, iclass 23, count 0 2006.173.03:30:33.15#ibcon#about to read 5, iclass 23, count 0 2006.173.03:30:33.15#ibcon#read 5, iclass 23, count 0 2006.173.03:30:33.15#ibcon#about to read 6, iclass 23, count 0 2006.173.03:30:33.15#ibcon#read 6, iclass 23, count 0 2006.173.03:30:33.15#ibcon#end of sib2, iclass 23, count 0 2006.173.03:30:33.15#ibcon#*after write, iclass 23, count 0 2006.173.03:30:33.15#ibcon#*before return 0, iclass 23, count 0 2006.173.03:30:33.15#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.03:30:33.15#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.03:30:33.15#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.03:30:33.15#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.03:30:33.15$vck44/vb=4,4 2006.173.03:30:33.15#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.03:30:33.15#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.03:30:33.15#ibcon#ireg 11 cls_cnt 2 2006.173.03:30:33.15#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.03:30:33.21#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.03:30:33.21#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.03:30:33.21#ibcon#enter wrdev, iclass 25, count 2 2006.173.03:30:33.21#ibcon#first serial, iclass 25, count 2 2006.173.03:30:33.21#ibcon#enter sib2, iclass 25, count 2 2006.173.03:30:33.21#ibcon#flushed, iclass 25, count 2 2006.173.03:30:33.21#ibcon#about to write, iclass 25, count 2 2006.173.03:30:33.21#ibcon#wrote, iclass 25, count 2 2006.173.03:30:33.21#ibcon#about to read 3, iclass 25, count 2 2006.173.03:30:33.23#ibcon#read 3, iclass 25, count 2 2006.173.03:30:33.23#ibcon#about to read 4, iclass 25, count 2 2006.173.03:30:33.23#ibcon#read 4, iclass 25, count 2 2006.173.03:30:33.23#ibcon#about to read 5, iclass 25, count 2 2006.173.03:30:33.23#ibcon#read 5, iclass 25, count 2 2006.173.03:30:33.23#ibcon#about to read 6, iclass 25, count 2 2006.173.03:30:33.23#ibcon#read 6, iclass 25, count 2 2006.173.03:30:33.23#ibcon#end of sib2, iclass 25, count 2 2006.173.03:30:33.23#ibcon#*mode == 0, iclass 25, count 2 2006.173.03:30:33.23#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.03:30:33.23#ibcon#[27=AT04-04\r\n] 2006.173.03:30:33.23#ibcon#*before write, iclass 25, count 2 2006.173.03:30:33.23#ibcon#enter sib2, iclass 25, count 2 2006.173.03:30:33.23#ibcon#flushed, iclass 25, count 2 2006.173.03:30:33.23#ibcon#about to write, iclass 25, count 2 2006.173.03:30:33.23#ibcon#wrote, iclass 25, count 2 2006.173.03:30:33.23#ibcon#about to read 3, iclass 25, count 2 2006.173.03:30:33.26#ibcon#read 3, iclass 25, count 2 2006.173.03:30:33.26#ibcon#about to read 4, iclass 25, count 2 2006.173.03:30:33.26#ibcon#read 4, iclass 25, count 2 2006.173.03:30:33.26#ibcon#about to read 5, iclass 25, count 2 2006.173.03:30:33.26#ibcon#read 5, iclass 25, count 2 2006.173.03:30:33.26#ibcon#about to read 6, iclass 25, count 2 2006.173.03:30:33.26#ibcon#read 6, iclass 25, count 2 2006.173.03:30:33.26#ibcon#end of sib2, iclass 25, count 2 2006.173.03:30:33.26#ibcon#*after write, iclass 25, count 2 2006.173.03:30:33.26#ibcon#*before return 0, iclass 25, count 2 2006.173.03:30:33.26#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.03:30:33.26#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.03:30:33.26#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.03:30:33.26#ibcon#ireg 7 cls_cnt 0 2006.173.03:30:33.26#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.03:30:33.38#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.03:30:33.38#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.03:30:33.38#ibcon#enter wrdev, iclass 25, count 0 2006.173.03:30:33.38#ibcon#first serial, iclass 25, count 0 2006.173.03:30:33.38#ibcon#enter sib2, iclass 25, count 0 2006.173.03:30:33.38#ibcon#flushed, iclass 25, count 0 2006.173.03:30:33.38#ibcon#about to write, iclass 25, count 0 2006.173.03:30:33.38#ibcon#wrote, iclass 25, count 0 2006.173.03:30:33.38#ibcon#about to read 3, iclass 25, count 0 2006.173.03:30:33.40#ibcon#read 3, iclass 25, count 0 2006.173.03:30:33.40#ibcon#about to read 4, iclass 25, count 0 2006.173.03:30:33.40#ibcon#read 4, iclass 25, count 0 2006.173.03:30:33.40#ibcon#about to read 5, iclass 25, count 0 2006.173.03:30:33.40#ibcon#read 5, iclass 25, count 0 2006.173.03:30:33.40#ibcon#about to read 6, iclass 25, count 0 2006.173.03:30:33.40#ibcon#read 6, iclass 25, count 0 2006.173.03:30:33.40#ibcon#end of sib2, iclass 25, count 0 2006.173.03:30:33.40#ibcon#*mode == 0, iclass 25, count 0 2006.173.03:30:33.40#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.03:30:33.40#ibcon#[27=USB\r\n] 2006.173.03:30:33.40#ibcon#*before write, iclass 25, count 0 2006.173.03:30:33.40#ibcon#enter sib2, iclass 25, count 0 2006.173.03:30:33.40#ibcon#flushed, iclass 25, count 0 2006.173.03:30:33.40#ibcon#about to write, iclass 25, count 0 2006.173.03:30:33.40#ibcon#wrote, iclass 25, count 0 2006.173.03:30:33.40#ibcon#about to read 3, iclass 25, count 0 2006.173.03:30:33.43#ibcon#read 3, iclass 25, count 0 2006.173.03:30:33.43#ibcon#about to read 4, iclass 25, count 0 2006.173.03:30:33.43#ibcon#read 4, iclass 25, count 0 2006.173.03:30:33.43#ibcon#about to read 5, iclass 25, count 0 2006.173.03:30:33.43#ibcon#read 5, iclass 25, count 0 2006.173.03:30:33.43#ibcon#about to read 6, iclass 25, count 0 2006.173.03:30:33.43#ibcon#read 6, iclass 25, count 0 2006.173.03:30:33.43#ibcon#end of sib2, iclass 25, count 0 2006.173.03:30:33.43#ibcon#*after write, iclass 25, count 0 2006.173.03:30:33.43#ibcon#*before return 0, iclass 25, count 0 2006.173.03:30:33.43#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.03:30:33.43#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.03:30:33.43#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.03:30:33.43#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.03:30:33.43$vck44/vblo=5,709.99 2006.173.03:30:33.43#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.03:30:33.43#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.03:30:33.43#ibcon#ireg 17 cls_cnt 0 2006.173.03:30:33.43#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.03:30:33.43#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.03:30:33.43#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.03:30:33.43#ibcon#enter wrdev, iclass 27, count 0 2006.173.03:30:33.43#ibcon#first serial, iclass 27, count 0 2006.173.03:30:33.43#ibcon#enter sib2, iclass 27, count 0 2006.173.03:30:33.43#ibcon#flushed, iclass 27, count 0 2006.173.03:30:33.43#ibcon#about to write, iclass 27, count 0 2006.173.03:30:33.43#ibcon#wrote, iclass 27, count 0 2006.173.03:30:33.43#ibcon#about to read 3, iclass 27, count 0 2006.173.03:30:33.45#ibcon#read 3, iclass 27, count 0 2006.173.03:30:33.45#ibcon#about to read 4, iclass 27, count 0 2006.173.03:30:33.45#ibcon#read 4, iclass 27, count 0 2006.173.03:30:33.45#ibcon#about to read 5, iclass 27, count 0 2006.173.03:30:33.45#ibcon#read 5, iclass 27, count 0 2006.173.03:30:33.45#ibcon#about to read 6, iclass 27, count 0 2006.173.03:30:33.45#ibcon#read 6, iclass 27, count 0 2006.173.03:30:33.45#ibcon#end of sib2, iclass 27, count 0 2006.173.03:30:33.45#ibcon#*mode == 0, iclass 27, count 0 2006.173.03:30:33.45#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.03:30:33.45#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.03:30:33.45#ibcon#*before write, iclass 27, count 0 2006.173.03:30:33.45#ibcon#enter sib2, iclass 27, count 0 2006.173.03:30:33.45#ibcon#flushed, iclass 27, count 0 2006.173.03:30:33.45#ibcon#about to write, iclass 27, count 0 2006.173.03:30:33.45#ibcon#wrote, iclass 27, count 0 2006.173.03:30:33.45#ibcon#about to read 3, iclass 27, count 0 2006.173.03:30:33.49#ibcon#read 3, iclass 27, count 0 2006.173.03:30:33.49#ibcon#about to read 4, iclass 27, count 0 2006.173.03:30:33.49#ibcon#read 4, iclass 27, count 0 2006.173.03:30:33.49#ibcon#about to read 5, iclass 27, count 0 2006.173.03:30:33.49#ibcon#read 5, iclass 27, count 0 2006.173.03:30:33.49#ibcon#about to read 6, iclass 27, count 0 2006.173.03:30:33.49#ibcon#read 6, iclass 27, count 0 2006.173.03:30:33.49#ibcon#end of sib2, iclass 27, count 0 2006.173.03:30:33.49#ibcon#*after write, iclass 27, count 0 2006.173.03:30:33.49#ibcon#*before return 0, iclass 27, count 0 2006.173.03:30:33.49#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.03:30:33.49#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.03:30:33.49#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.03:30:33.49#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.03:30:33.49$vck44/vb=5,4 2006.173.03:30:33.49#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.03:30:33.49#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.03:30:33.49#ibcon#ireg 11 cls_cnt 2 2006.173.03:30:33.49#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.03:30:33.55#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.03:30:33.55#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.03:30:33.55#ibcon#enter wrdev, iclass 29, count 2 2006.173.03:30:33.55#ibcon#first serial, iclass 29, count 2 2006.173.03:30:33.55#ibcon#enter sib2, iclass 29, count 2 2006.173.03:30:33.55#ibcon#flushed, iclass 29, count 2 2006.173.03:30:33.55#ibcon#about to write, iclass 29, count 2 2006.173.03:30:33.55#ibcon#wrote, iclass 29, count 2 2006.173.03:30:33.55#ibcon#about to read 3, iclass 29, count 2 2006.173.03:30:33.57#ibcon#read 3, iclass 29, count 2 2006.173.03:30:33.57#ibcon#about to read 4, iclass 29, count 2 2006.173.03:30:33.57#ibcon#read 4, iclass 29, count 2 2006.173.03:30:33.57#ibcon#about to read 5, iclass 29, count 2 2006.173.03:30:33.57#ibcon#read 5, iclass 29, count 2 2006.173.03:30:33.57#ibcon#about to read 6, iclass 29, count 2 2006.173.03:30:33.57#ibcon#read 6, iclass 29, count 2 2006.173.03:30:33.57#ibcon#end of sib2, iclass 29, count 2 2006.173.03:30:33.57#ibcon#*mode == 0, iclass 29, count 2 2006.173.03:30:33.57#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.03:30:33.57#ibcon#[27=AT05-04\r\n] 2006.173.03:30:33.57#ibcon#*before write, iclass 29, count 2 2006.173.03:30:33.57#ibcon#enter sib2, iclass 29, count 2 2006.173.03:30:33.57#ibcon#flushed, iclass 29, count 2 2006.173.03:30:33.57#ibcon#about to write, iclass 29, count 2 2006.173.03:30:33.57#ibcon#wrote, iclass 29, count 2 2006.173.03:30:33.57#ibcon#about to read 3, iclass 29, count 2 2006.173.03:30:33.60#ibcon#read 3, iclass 29, count 2 2006.173.03:30:33.60#ibcon#about to read 4, iclass 29, count 2 2006.173.03:30:33.60#ibcon#read 4, iclass 29, count 2 2006.173.03:30:33.60#ibcon#about to read 5, iclass 29, count 2 2006.173.03:30:33.60#ibcon#read 5, iclass 29, count 2 2006.173.03:30:33.60#ibcon#about to read 6, iclass 29, count 2 2006.173.03:30:33.60#ibcon#read 6, iclass 29, count 2 2006.173.03:30:33.60#ibcon#end of sib2, iclass 29, count 2 2006.173.03:30:33.60#ibcon#*after write, iclass 29, count 2 2006.173.03:30:33.60#ibcon#*before return 0, iclass 29, count 2 2006.173.03:30:33.60#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.03:30:33.60#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.03:30:33.60#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.03:30:33.60#ibcon#ireg 7 cls_cnt 0 2006.173.03:30:33.60#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.03:30:33.72#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.03:30:33.72#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.03:30:33.72#ibcon#enter wrdev, iclass 29, count 0 2006.173.03:30:33.72#ibcon#first serial, iclass 29, count 0 2006.173.03:30:33.72#ibcon#enter sib2, iclass 29, count 0 2006.173.03:30:33.72#ibcon#flushed, iclass 29, count 0 2006.173.03:30:33.72#ibcon#about to write, iclass 29, count 0 2006.173.03:30:33.72#ibcon#wrote, iclass 29, count 0 2006.173.03:30:33.72#ibcon#about to read 3, iclass 29, count 0 2006.173.03:30:33.74#ibcon#read 3, iclass 29, count 0 2006.173.03:30:33.74#ibcon#about to read 4, iclass 29, count 0 2006.173.03:30:33.74#ibcon#read 4, iclass 29, count 0 2006.173.03:30:33.74#ibcon#about to read 5, iclass 29, count 0 2006.173.03:30:33.74#ibcon#read 5, iclass 29, count 0 2006.173.03:30:33.74#ibcon#about to read 6, iclass 29, count 0 2006.173.03:30:33.74#ibcon#read 6, iclass 29, count 0 2006.173.03:30:33.74#ibcon#end of sib2, iclass 29, count 0 2006.173.03:30:33.74#ibcon#*mode == 0, iclass 29, count 0 2006.173.03:30:33.74#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.03:30:33.74#ibcon#[27=USB\r\n] 2006.173.03:30:33.74#ibcon#*before write, iclass 29, count 0 2006.173.03:30:33.74#ibcon#enter sib2, iclass 29, count 0 2006.173.03:30:33.74#ibcon#flushed, iclass 29, count 0 2006.173.03:30:33.74#ibcon#about to write, iclass 29, count 0 2006.173.03:30:33.74#ibcon#wrote, iclass 29, count 0 2006.173.03:30:33.74#ibcon#about to read 3, iclass 29, count 0 2006.173.03:30:33.77#ibcon#read 3, iclass 29, count 0 2006.173.03:30:33.77#ibcon#about to read 4, iclass 29, count 0 2006.173.03:30:33.77#ibcon#read 4, iclass 29, count 0 2006.173.03:30:33.77#ibcon#about to read 5, iclass 29, count 0 2006.173.03:30:33.77#ibcon#read 5, iclass 29, count 0 2006.173.03:30:33.77#ibcon#about to read 6, iclass 29, count 0 2006.173.03:30:33.77#ibcon#read 6, iclass 29, count 0 2006.173.03:30:33.77#ibcon#end of sib2, iclass 29, count 0 2006.173.03:30:33.77#ibcon#*after write, iclass 29, count 0 2006.173.03:30:33.77#ibcon#*before return 0, iclass 29, count 0 2006.173.03:30:33.77#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.03:30:33.77#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.03:30:33.77#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.03:30:33.77#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.03:30:33.77$vck44/vblo=6,719.99 2006.173.03:30:33.77#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.03:30:33.77#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.03:30:33.77#ibcon#ireg 17 cls_cnt 0 2006.173.03:30:33.77#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.03:30:33.77#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.03:30:33.77#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.03:30:33.77#ibcon#enter wrdev, iclass 31, count 0 2006.173.03:30:33.77#ibcon#first serial, iclass 31, count 0 2006.173.03:30:33.77#ibcon#enter sib2, iclass 31, count 0 2006.173.03:30:33.77#ibcon#flushed, iclass 31, count 0 2006.173.03:30:33.77#ibcon#about to write, iclass 31, count 0 2006.173.03:30:33.77#ibcon#wrote, iclass 31, count 0 2006.173.03:30:33.77#ibcon#about to read 3, iclass 31, count 0 2006.173.03:30:33.79#ibcon#read 3, iclass 31, count 0 2006.173.03:30:33.79#ibcon#about to read 4, iclass 31, count 0 2006.173.03:30:33.79#ibcon#read 4, iclass 31, count 0 2006.173.03:30:33.79#ibcon#about to read 5, iclass 31, count 0 2006.173.03:30:33.79#ibcon#read 5, iclass 31, count 0 2006.173.03:30:33.79#ibcon#about to read 6, iclass 31, count 0 2006.173.03:30:33.79#ibcon#read 6, iclass 31, count 0 2006.173.03:30:33.79#ibcon#end of sib2, iclass 31, count 0 2006.173.03:30:33.79#ibcon#*mode == 0, iclass 31, count 0 2006.173.03:30:33.79#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.03:30:33.79#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.03:30:33.79#ibcon#*before write, iclass 31, count 0 2006.173.03:30:33.79#ibcon#enter sib2, iclass 31, count 0 2006.173.03:30:33.79#ibcon#flushed, iclass 31, count 0 2006.173.03:30:33.79#ibcon#about to write, iclass 31, count 0 2006.173.03:30:33.79#ibcon#wrote, iclass 31, count 0 2006.173.03:30:33.79#ibcon#about to read 3, iclass 31, count 0 2006.173.03:30:33.83#ibcon#read 3, iclass 31, count 0 2006.173.03:30:33.83#ibcon#about to read 4, iclass 31, count 0 2006.173.03:30:33.83#ibcon#read 4, iclass 31, count 0 2006.173.03:30:33.83#ibcon#about to read 5, iclass 31, count 0 2006.173.03:30:33.83#ibcon#read 5, iclass 31, count 0 2006.173.03:30:33.83#ibcon#about to read 6, iclass 31, count 0 2006.173.03:30:33.83#ibcon#read 6, iclass 31, count 0 2006.173.03:30:33.83#ibcon#end of sib2, iclass 31, count 0 2006.173.03:30:33.83#ibcon#*after write, iclass 31, count 0 2006.173.03:30:33.83#ibcon#*before return 0, iclass 31, count 0 2006.173.03:30:33.83#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.03:30:33.83#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.03:30:33.83#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.03:30:33.83#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.03:30:33.83$vck44/vb=6,4 2006.173.03:30:33.83#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.173.03:30:33.83#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.173.03:30:33.83#ibcon#ireg 11 cls_cnt 2 2006.173.03:30:33.83#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.03:30:33.89#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.03:30:33.89#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.03:30:33.89#ibcon#enter wrdev, iclass 33, count 2 2006.173.03:30:33.89#ibcon#first serial, iclass 33, count 2 2006.173.03:30:33.89#ibcon#enter sib2, iclass 33, count 2 2006.173.03:30:33.89#ibcon#flushed, iclass 33, count 2 2006.173.03:30:33.89#ibcon#about to write, iclass 33, count 2 2006.173.03:30:33.89#ibcon#wrote, iclass 33, count 2 2006.173.03:30:33.89#ibcon#about to read 3, iclass 33, count 2 2006.173.03:30:33.91#ibcon#read 3, iclass 33, count 2 2006.173.03:30:33.91#ibcon#about to read 4, iclass 33, count 2 2006.173.03:30:33.91#ibcon#read 4, iclass 33, count 2 2006.173.03:30:33.91#ibcon#about to read 5, iclass 33, count 2 2006.173.03:30:33.91#ibcon#read 5, iclass 33, count 2 2006.173.03:30:33.91#ibcon#about to read 6, iclass 33, count 2 2006.173.03:30:33.91#ibcon#read 6, iclass 33, count 2 2006.173.03:30:33.91#ibcon#end of sib2, iclass 33, count 2 2006.173.03:30:33.91#ibcon#*mode == 0, iclass 33, count 2 2006.173.03:30:33.91#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.173.03:30:33.91#ibcon#[27=AT06-04\r\n] 2006.173.03:30:33.91#ibcon#*before write, iclass 33, count 2 2006.173.03:30:33.91#ibcon#enter sib2, iclass 33, count 2 2006.173.03:30:33.91#ibcon#flushed, iclass 33, count 2 2006.173.03:30:33.91#ibcon#about to write, iclass 33, count 2 2006.173.03:30:33.91#ibcon#wrote, iclass 33, count 2 2006.173.03:30:33.91#ibcon#about to read 3, iclass 33, count 2 2006.173.03:30:33.94#ibcon#read 3, iclass 33, count 2 2006.173.03:30:33.94#ibcon#about to read 4, iclass 33, count 2 2006.173.03:30:33.94#ibcon#read 4, iclass 33, count 2 2006.173.03:30:33.94#ibcon#about to read 5, iclass 33, count 2 2006.173.03:30:33.94#ibcon#read 5, iclass 33, count 2 2006.173.03:30:33.94#ibcon#about to read 6, iclass 33, count 2 2006.173.03:30:33.94#ibcon#read 6, iclass 33, count 2 2006.173.03:30:33.94#ibcon#end of sib2, iclass 33, count 2 2006.173.03:30:33.94#ibcon#*after write, iclass 33, count 2 2006.173.03:30:33.94#ibcon#*before return 0, iclass 33, count 2 2006.173.03:30:33.94#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.03:30:33.94#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.173.03:30:33.94#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.173.03:30:33.94#ibcon#ireg 7 cls_cnt 0 2006.173.03:30:33.94#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.03:30:34.06#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.03:30:34.06#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.03:30:34.06#ibcon#enter wrdev, iclass 33, count 0 2006.173.03:30:34.06#ibcon#first serial, iclass 33, count 0 2006.173.03:30:34.06#ibcon#enter sib2, iclass 33, count 0 2006.173.03:30:34.06#ibcon#flushed, iclass 33, count 0 2006.173.03:30:34.06#ibcon#about to write, iclass 33, count 0 2006.173.03:30:34.06#ibcon#wrote, iclass 33, count 0 2006.173.03:30:34.06#ibcon#about to read 3, iclass 33, count 0 2006.173.03:30:34.08#ibcon#read 3, iclass 33, count 0 2006.173.03:30:34.08#ibcon#about to read 4, iclass 33, count 0 2006.173.03:30:34.08#ibcon#read 4, iclass 33, count 0 2006.173.03:30:34.08#ibcon#about to read 5, iclass 33, count 0 2006.173.03:30:34.08#ibcon#read 5, iclass 33, count 0 2006.173.03:30:34.08#ibcon#about to read 6, iclass 33, count 0 2006.173.03:30:34.08#ibcon#read 6, iclass 33, count 0 2006.173.03:30:34.08#ibcon#end of sib2, iclass 33, count 0 2006.173.03:30:34.08#ibcon#*mode == 0, iclass 33, count 0 2006.173.03:30:34.08#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.03:30:34.08#ibcon#[27=USB\r\n] 2006.173.03:30:34.08#ibcon#*before write, iclass 33, count 0 2006.173.03:30:34.08#ibcon#enter sib2, iclass 33, count 0 2006.173.03:30:34.08#ibcon#flushed, iclass 33, count 0 2006.173.03:30:34.08#ibcon#about to write, iclass 33, count 0 2006.173.03:30:34.08#ibcon#wrote, iclass 33, count 0 2006.173.03:30:34.08#ibcon#about to read 3, iclass 33, count 0 2006.173.03:30:34.11#ibcon#read 3, iclass 33, count 0 2006.173.03:30:34.11#ibcon#about to read 4, iclass 33, count 0 2006.173.03:30:34.11#ibcon#read 4, iclass 33, count 0 2006.173.03:30:34.11#ibcon#about to read 5, iclass 33, count 0 2006.173.03:30:34.11#ibcon#read 5, iclass 33, count 0 2006.173.03:30:34.11#ibcon#about to read 6, iclass 33, count 0 2006.173.03:30:34.11#ibcon#read 6, iclass 33, count 0 2006.173.03:30:34.11#ibcon#end of sib2, iclass 33, count 0 2006.173.03:30:34.11#ibcon#*after write, iclass 33, count 0 2006.173.03:30:34.11#ibcon#*before return 0, iclass 33, count 0 2006.173.03:30:34.11#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.03:30:34.11#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.173.03:30:34.11#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.03:30:34.11#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.03:30:34.11$vck44/vblo=7,734.99 2006.173.03:30:34.11#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.03:30:34.11#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.03:30:34.11#ibcon#ireg 17 cls_cnt 0 2006.173.03:30:34.11#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.03:30:34.11#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.03:30:34.11#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.03:30:34.11#ibcon#enter wrdev, iclass 35, count 0 2006.173.03:30:34.11#ibcon#first serial, iclass 35, count 0 2006.173.03:30:34.11#ibcon#enter sib2, iclass 35, count 0 2006.173.03:30:34.11#ibcon#flushed, iclass 35, count 0 2006.173.03:30:34.11#ibcon#about to write, iclass 35, count 0 2006.173.03:30:34.11#ibcon#wrote, iclass 35, count 0 2006.173.03:30:34.11#ibcon#about to read 3, iclass 35, count 0 2006.173.03:30:34.13#ibcon#read 3, iclass 35, count 0 2006.173.03:30:34.13#ibcon#about to read 4, iclass 35, count 0 2006.173.03:30:34.13#ibcon#read 4, iclass 35, count 0 2006.173.03:30:34.13#ibcon#about to read 5, iclass 35, count 0 2006.173.03:30:34.13#ibcon#read 5, iclass 35, count 0 2006.173.03:30:34.13#ibcon#about to read 6, iclass 35, count 0 2006.173.03:30:34.13#ibcon#read 6, iclass 35, count 0 2006.173.03:30:34.13#ibcon#end of sib2, iclass 35, count 0 2006.173.03:30:34.13#ibcon#*mode == 0, iclass 35, count 0 2006.173.03:30:34.13#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.03:30:34.13#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.03:30:34.13#ibcon#*before write, iclass 35, count 0 2006.173.03:30:34.13#ibcon#enter sib2, iclass 35, count 0 2006.173.03:30:34.13#ibcon#flushed, iclass 35, count 0 2006.173.03:30:34.13#ibcon#about to write, iclass 35, count 0 2006.173.03:30:34.13#ibcon#wrote, iclass 35, count 0 2006.173.03:30:34.13#ibcon#about to read 3, iclass 35, count 0 2006.173.03:30:34.17#ibcon#read 3, iclass 35, count 0 2006.173.03:30:34.17#ibcon#about to read 4, iclass 35, count 0 2006.173.03:30:34.17#ibcon#read 4, iclass 35, count 0 2006.173.03:30:34.17#ibcon#about to read 5, iclass 35, count 0 2006.173.03:30:34.17#ibcon#read 5, iclass 35, count 0 2006.173.03:30:34.17#ibcon#about to read 6, iclass 35, count 0 2006.173.03:30:34.17#ibcon#read 6, iclass 35, count 0 2006.173.03:30:34.17#ibcon#end of sib2, iclass 35, count 0 2006.173.03:30:34.17#ibcon#*after write, iclass 35, count 0 2006.173.03:30:34.17#ibcon#*before return 0, iclass 35, count 0 2006.173.03:30:34.17#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.03:30:34.17#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.03:30:34.17#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.03:30:34.17#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.03:30:34.17$vck44/vb=7,4 2006.173.03:30:34.17#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.173.03:30:34.17#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.173.03:30:34.17#ibcon#ireg 11 cls_cnt 2 2006.173.03:30:34.17#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.03:30:34.23#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.03:30:34.23#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.03:30:34.23#ibcon#enter wrdev, iclass 37, count 2 2006.173.03:30:34.23#ibcon#first serial, iclass 37, count 2 2006.173.03:30:34.23#ibcon#enter sib2, iclass 37, count 2 2006.173.03:30:34.23#ibcon#flushed, iclass 37, count 2 2006.173.03:30:34.23#ibcon#about to write, iclass 37, count 2 2006.173.03:30:34.23#ibcon#wrote, iclass 37, count 2 2006.173.03:30:34.23#ibcon#about to read 3, iclass 37, count 2 2006.173.03:30:34.25#ibcon#read 3, iclass 37, count 2 2006.173.03:30:34.25#ibcon#about to read 4, iclass 37, count 2 2006.173.03:30:34.25#ibcon#read 4, iclass 37, count 2 2006.173.03:30:34.25#ibcon#about to read 5, iclass 37, count 2 2006.173.03:30:34.25#ibcon#read 5, iclass 37, count 2 2006.173.03:30:34.25#ibcon#about to read 6, iclass 37, count 2 2006.173.03:30:34.25#ibcon#read 6, iclass 37, count 2 2006.173.03:30:34.25#ibcon#end of sib2, iclass 37, count 2 2006.173.03:30:34.25#ibcon#*mode == 0, iclass 37, count 2 2006.173.03:30:34.25#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.173.03:30:34.25#ibcon#[27=AT07-04\r\n] 2006.173.03:30:34.25#ibcon#*before write, iclass 37, count 2 2006.173.03:30:34.25#ibcon#enter sib2, iclass 37, count 2 2006.173.03:30:34.25#ibcon#flushed, iclass 37, count 2 2006.173.03:30:34.25#ibcon#about to write, iclass 37, count 2 2006.173.03:30:34.25#ibcon#wrote, iclass 37, count 2 2006.173.03:30:34.25#ibcon#about to read 3, iclass 37, count 2 2006.173.03:30:34.28#ibcon#read 3, iclass 37, count 2 2006.173.03:30:34.28#ibcon#about to read 4, iclass 37, count 2 2006.173.03:30:34.28#ibcon#read 4, iclass 37, count 2 2006.173.03:30:34.28#ibcon#about to read 5, iclass 37, count 2 2006.173.03:30:34.28#ibcon#read 5, iclass 37, count 2 2006.173.03:30:34.28#ibcon#about to read 6, iclass 37, count 2 2006.173.03:30:34.28#ibcon#read 6, iclass 37, count 2 2006.173.03:30:34.28#ibcon#end of sib2, iclass 37, count 2 2006.173.03:30:34.28#ibcon#*after write, iclass 37, count 2 2006.173.03:30:34.28#ibcon#*before return 0, iclass 37, count 2 2006.173.03:30:34.28#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.03:30:34.28#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.173.03:30:34.28#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.173.03:30:34.28#ibcon#ireg 7 cls_cnt 0 2006.173.03:30:34.28#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.03:30:34.40#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.03:30:34.40#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.03:30:34.40#ibcon#enter wrdev, iclass 37, count 0 2006.173.03:30:34.40#ibcon#first serial, iclass 37, count 0 2006.173.03:30:34.40#ibcon#enter sib2, iclass 37, count 0 2006.173.03:30:34.40#ibcon#flushed, iclass 37, count 0 2006.173.03:30:34.40#ibcon#about to write, iclass 37, count 0 2006.173.03:30:34.40#ibcon#wrote, iclass 37, count 0 2006.173.03:30:34.40#ibcon#about to read 3, iclass 37, count 0 2006.173.03:30:34.42#ibcon#read 3, iclass 37, count 0 2006.173.03:30:34.42#ibcon#about to read 4, iclass 37, count 0 2006.173.03:30:34.42#ibcon#read 4, iclass 37, count 0 2006.173.03:30:34.42#ibcon#about to read 5, iclass 37, count 0 2006.173.03:30:34.42#ibcon#read 5, iclass 37, count 0 2006.173.03:30:34.42#ibcon#about to read 6, iclass 37, count 0 2006.173.03:30:34.42#ibcon#read 6, iclass 37, count 0 2006.173.03:30:34.42#ibcon#end of sib2, iclass 37, count 0 2006.173.03:30:34.42#ibcon#*mode == 0, iclass 37, count 0 2006.173.03:30:34.42#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.03:30:34.42#ibcon#[27=USB\r\n] 2006.173.03:30:34.42#ibcon#*before write, iclass 37, count 0 2006.173.03:30:34.42#ibcon#enter sib2, iclass 37, count 0 2006.173.03:30:34.42#ibcon#flushed, iclass 37, count 0 2006.173.03:30:34.42#ibcon#about to write, iclass 37, count 0 2006.173.03:30:34.42#ibcon#wrote, iclass 37, count 0 2006.173.03:30:34.42#ibcon#about to read 3, iclass 37, count 0 2006.173.03:30:34.45#ibcon#read 3, iclass 37, count 0 2006.173.03:30:34.45#ibcon#about to read 4, iclass 37, count 0 2006.173.03:30:34.45#ibcon#read 4, iclass 37, count 0 2006.173.03:30:34.45#ibcon#about to read 5, iclass 37, count 0 2006.173.03:30:34.45#ibcon#read 5, iclass 37, count 0 2006.173.03:30:34.45#ibcon#about to read 6, iclass 37, count 0 2006.173.03:30:34.45#ibcon#read 6, iclass 37, count 0 2006.173.03:30:34.45#ibcon#end of sib2, iclass 37, count 0 2006.173.03:30:34.45#ibcon#*after write, iclass 37, count 0 2006.173.03:30:34.45#ibcon#*before return 0, iclass 37, count 0 2006.173.03:30:34.45#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.03:30:34.45#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.173.03:30:34.45#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.03:30:34.45#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.03:30:34.45$vck44/vblo=8,744.99 2006.173.03:30:34.45#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.03:30:34.45#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.03:30:34.45#ibcon#ireg 17 cls_cnt 0 2006.173.03:30:34.45#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.03:30:34.45#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.03:30:34.45#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.03:30:34.45#ibcon#enter wrdev, iclass 39, count 0 2006.173.03:30:34.45#ibcon#first serial, iclass 39, count 0 2006.173.03:30:34.45#ibcon#enter sib2, iclass 39, count 0 2006.173.03:30:34.45#ibcon#flushed, iclass 39, count 0 2006.173.03:30:34.45#ibcon#about to write, iclass 39, count 0 2006.173.03:30:34.45#ibcon#wrote, iclass 39, count 0 2006.173.03:30:34.45#ibcon#about to read 3, iclass 39, count 0 2006.173.03:30:34.47#ibcon#read 3, iclass 39, count 0 2006.173.03:30:34.47#ibcon#about to read 4, iclass 39, count 0 2006.173.03:30:34.47#ibcon#read 4, iclass 39, count 0 2006.173.03:30:34.47#ibcon#about to read 5, iclass 39, count 0 2006.173.03:30:34.47#ibcon#read 5, iclass 39, count 0 2006.173.03:30:34.47#ibcon#about to read 6, iclass 39, count 0 2006.173.03:30:34.47#ibcon#read 6, iclass 39, count 0 2006.173.03:30:34.47#ibcon#end of sib2, iclass 39, count 0 2006.173.03:30:34.47#ibcon#*mode == 0, iclass 39, count 0 2006.173.03:30:34.47#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.03:30:34.47#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.03:30:34.47#ibcon#*before write, iclass 39, count 0 2006.173.03:30:34.47#ibcon#enter sib2, iclass 39, count 0 2006.173.03:30:34.47#ibcon#flushed, iclass 39, count 0 2006.173.03:30:34.47#ibcon#about to write, iclass 39, count 0 2006.173.03:30:34.47#ibcon#wrote, iclass 39, count 0 2006.173.03:30:34.47#ibcon#about to read 3, iclass 39, count 0 2006.173.03:30:34.51#ibcon#read 3, iclass 39, count 0 2006.173.03:30:34.51#ibcon#about to read 4, iclass 39, count 0 2006.173.03:30:34.51#ibcon#read 4, iclass 39, count 0 2006.173.03:30:34.51#ibcon#about to read 5, iclass 39, count 0 2006.173.03:30:34.51#ibcon#read 5, iclass 39, count 0 2006.173.03:30:34.51#ibcon#about to read 6, iclass 39, count 0 2006.173.03:30:34.51#ibcon#read 6, iclass 39, count 0 2006.173.03:30:34.51#ibcon#end of sib2, iclass 39, count 0 2006.173.03:30:34.51#ibcon#*after write, iclass 39, count 0 2006.173.03:30:34.51#ibcon#*before return 0, iclass 39, count 0 2006.173.03:30:34.51#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.03:30:34.51#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.03:30:34.51#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.03:30:34.51#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.03:30:34.51$vck44/vb=8,4 2006.173.03:30:34.51#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.03:30:34.51#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.03:30:34.51#ibcon#ireg 11 cls_cnt 2 2006.173.03:30:34.51#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.03:30:34.57#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.03:30:34.57#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.03:30:34.57#ibcon#enter wrdev, iclass 3, count 2 2006.173.03:30:34.57#ibcon#first serial, iclass 3, count 2 2006.173.03:30:34.57#ibcon#enter sib2, iclass 3, count 2 2006.173.03:30:34.57#ibcon#flushed, iclass 3, count 2 2006.173.03:30:34.57#ibcon#about to write, iclass 3, count 2 2006.173.03:30:34.57#ibcon#wrote, iclass 3, count 2 2006.173.03:30:34.57#ibcon#about to read 3, iclass 3, count 2 2006.173.03:30:34.59#ibcon#read 3, iclass 3, count 2 2006.173.03:30:34.59#ibcon#about to read 4, iclass 3, count 2 2006.173.03:30:34.59#ibcon#read 4, iclass 3, count 2 2006.173.03:30:34.59#ibcon#about to read 5, iclass 3, count 2 2006.173.03:30:34.59#ibcon#read 5, iclass 3, count 2 2006.173.03:30:34.59#ibcon#about to read 6, iclass 3, count 2 2006.173.03:30:34.59#ibcon#read 6, iclass 3, count 2 2006.173.03:30:34.59#ibcon#end of sib2, iclass 3, count 2 2006.173.03:30:34.59#ibcon#*mode == 0, iclass 3, count 2 2006.173.03:30:34.59#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.03:30:34.59#ibcon#[27=AT08-04\r\n] 2006.173.03:30:34.59#ibcon#*before write, iclass 3, count 2 2006.173.03:30:34.59#ibcon#enter sib2, iclass 3, count 2 2006.173.03:30:34.59#ibcon#flushed, iclass 3, count 2 2006.173.03:30:34.59#ibcon#about to write, iclass 3, count 2 2006.173.03:30:34.59#ibcon#wrote, iclass 3, count 2 2006.173.03:30:34.59#ibcon#about to read 3, iclass 3, count 2 2006.173.03:30:34.62#ibcon#read 3, iclass 3, count 2 2006.173.03:30:34.62#ibcon#about to read 4, iclass 3, count 2 2006.173.03:30:34.62#ibcon#read 4, iclass 3, count 2 2006.173.03:30:34.62#ibcon#about to read 5, iclass 3, count 2 2006.173.03:30:34.62#ibcon#read 5, iclass 3, count 2 2006.173.03:30:34.62#ibcon#about to read 6, iclass 3, count 2 2006.173.03:30:34.62#ibcon#read 6, iclass 3, count 2 2006.173.03:30:34.62#ibcon#end of sib2, iclass 3, count 2 2006.173.03:30:34.62#ibcon#*after write, iclass 3, count 2 2006.173.03:30:34.62#ibcon#*before return 0, iclass 3, count 2 2006.173.03:30:34.62#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.03:30:34.62#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.03:30:34.62#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.03:30:34.62#ibcon#ireg 7 cls_cnt 0 2006.173.03:30:34.62#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.03:30:34.74#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.03:30:34.74#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.03:30:34.74#ibcon#enter wrdev, iclass 3, count 0 2006.173.03:30:34.74#ibcon#first serial, iclass 3, count 0 2006.173.03:30:34.74#ibcon#enter sib2, iclass 3, count 0 2006.173.03:30:34.74#ibcon#flushed, iclass 3, count 0 2006.173.03:30:34.74#ibcon#about to write, iclass 3, count 0 2006.173.03:30:34.74#ibcon#wrote, iclass 3, count 0 2006.173.03:30:34.74#ibcon#about to read 3, iclass 3, count 0 2006.173.03:30:34.76#ibcon#read 3, iclass 3, count 0 2006.173.03:30:34.76#ibcon#about to read 4, iclass 3, count 0 2006.173.03:30:34.76#ibcon#read 4, iclass 3, count 0 2006.173.03:30:34.76#ibcon#about to read 5, iclass 3, count 0 2006.173.03:30:34.76#ibcon#read 5, iclass 3, count 0 2006.173.03:30:34.76#ibcon#about to read 6, iclass 3, count 0 2006.173.03:30:34.76#ibcon#read 6, iclass 3, count 0 2006.173.03:30:34.76#ibcon#end of sib2, iclass 3, count 0 2006.173.03:30:34.76#ibcon#*mode == 0, iclass 3, count 0 2006.173.03:30:34.76#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.03:30:34.76#ibcon#[27=USB\r\n] 2006.173.03:30:34.76#ibcon#*before write, iclass 3, count 0 2006.173.03:30:34.76#ibcon#enter sib2, iclass 3, count 0 2006.173.03:30:34.76#ibcon#flushed, iclass 3, count 0 2006.173.03:30:34.76#ibcon#about to write, iclass 3, count 0 2006.173.03:30:34.76#ibcon#wrote, iclass 3, count 0 2006.173.03:30:34.76#ibcon#about to read 3, iclass 3, count 0 2006.173.03:30:34.79#ibcon#read 3, iclass 3, count 0 2006.173.03:30:34.79#ibcon#about to read 4, iclass 3, count 0 2006.173.03:30:34.79#ibcon#read 4, iclass 3, count 0 2006.173.03:30:34.79#ibcon#about to read 5, iclass 3, count 0 2006.173.03:30:34.79#ibcon#read 5, iclass 3, count 0 2006.173.03:30:34.79#ibcon#about to read 6, iclass 3, count 0 2006.173.03:30:34.79#ibcon#read 6, iclass 3, count 0 2006.173.03:30:34.79#ibcon#end of sib2, iclass 3, count 0 2006.173.03:30:34.79#ibcon#*after write, iclass 3, count 0 2006.173.03:30:34.79#ibcon#*before return 0, iclass 3, count 0 2006.173.03:30:34.79#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.03:30:34.79#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.03:30:34.79#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.03:30:34.79#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.03:30:34.79$vck44/vabw=wide 2006.173.03:30:34.79#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.03:30:34.79#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.03:30:34.79#ibcon#ireg 8 cls_cnt 0 2006.173.03:30:34.79#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.03:30:34.79#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.03:30:34.79#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.03:30:34.79#ibcon#enter wrdev, iclass 5, count 0 2006.173.03:30:34.79#ibcon#first serial, iclass 5, count 0 2006.173.03:30:34.79#ibcon#enter sib2, iclass 5, count 0 2006.173.03:30:34.79#ibcon#flushed, iclass 5, count 0 2006.173.03:30:34.79#ibcon#about to write, iclass 5, count 0 2006.173.03:30:34.79#ibcon#wrote, iclass 5, count 0 2006.173.03:30:34.79#ibcon#about to read 3, iclass 5, count 0 2006.173.03:30:34.81#ibcon#read 3, iclass 5, count 0 2006.173.03:30:34.81#ibcon#about to read 4, iclass 5, count 0 2006.173.03:30:34.81#ibcon#read 4, iclass 5, count 0 2006.173.03:30:34.81#ibcon#about to read 5, iclass 5, count 0 2006.173.03:30:34.81#ibcon#read 5, iclass 5, count 0 2006.173.03:30:34.81#ibcon#about to read 6, iclass 5, count 0 2006.173.03:30:34.81#ibcon#read 6, iclass 5, count 0 2006.173.03:30:34.81#ibcon#end of sib2, iclass 5, count 0 2006.173.03:30:34.81#ibcon#*mode == 0, iclass 5, count 0 2006.173.03:30:34.81#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.03:30:34.81#ibcon#[25=BW32\r\n] 2006.173.03:30:34.81#ibcon#*before write, iclass 5, count 0 2006.173.03:30:34.81#ibcon#enter sib2, iclass 5, count 0 2006.173.03:30:34.81#ibcon#flushed, iclass 5, count 0 2006.173.03:30:34.81#ibcon#about to write, iclass 5, count 0 2006.173.03:30:34.81#ibcon#wrote, iclass 5, count 0 2006.173.03:30:34.81#ibcon#about to read 3, iclass 5, count 0 2006.173.03:30:34.84#ibcon#read 3, iclass 5, count 0 2006.173.03:30:34.84#ibcon#about to read 4, iclass 5, count 0 2006.173.03:30:34.84#ibcon#read 4, iclass 5, count 0 2006.173.03:30:34.84#ibcon#about to read 5, iclass 5, count 0 2006.173.03:30:34.84#ibcon#read 5, iclass 5, count 0 2006.173.03:30:34.84#ibcon#about to read 6, iclass 5, count 0 2006.173.03:30:34.84#ibcon#read 6, iclass 5, count 0 2006.173.03:30:34.84#ibcon#end of sib2, iclass 5, count 0 2006.173.03:30:34.84#ibcon#*after write, iclass 5, count 0 2006.173.03:30:34.84#ibcon#*before return 0, iclass 5, count 0 2006.173.03:30:34.84#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.03:30:34.84#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.03:30:34.84#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.03:30:34.84#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.03:30:34.84$vck44/vbbw=wide 2006.173.03:30:34.84#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.03:30:34.84#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.03:30:34.84#ibcon#ireg 8 cls_cnt 0 2006.173.03:30:34.84#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.03:30:34.91#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.03:30:34.91#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.03:30:34.91#ibcon#enter wrdev, iclass 7, count 0 2006.173.03:30:34.91#ibcon#first serial, iclass 7, count 0 2006.173.03:30:34.91#ibcon#enter sib2, iclass 7, count 0 2006.173.03:30:34.91#ibcon#flushed, iclass 7, count 0 2006.173.03:30:34.91#ibcon#about to write, iclass 7, count 0 2006.173.03:30:34.91#ibcon#wrote, iclass 7, count 0 2006.173.03:30:34.91#ibcon#about to read 3, iclass 7, count 0 2006.173.03:30:34.93#ibcon#read 3, iclass 7, count 0 2006.173.03:30:34.93#ibcon#about to read 4, iclass 7, count 0 2006.173.03:30:34.93#ibcon#read 4, iclass 7, count 0 2006.173.03:30:34.93#ibcon#about to read 5, iclass 7, count 0 2006.173.03:30:34.93#ibcon#read 5, iclass 7, count 0 2006.173.03:30:34.93#ibcon#about to read 6, iclass 7, count 0 2006.173.03:30:34.93#ibcon#read 6, iclass 7, count 0 2006.173.03:30:34.93#ibcon#end of sib2, iclass 7, count 0 2006.173.03:30:34.93#ibcon#*mode == 0, iclass 7, count 0 2006.173.03:30:34.93#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.03:30:34.93#ibcon#[27=BW32\r\n] 2006.173.03:30:34.93#ibcon#*before write, iclass 7, count 0 2006.173.03:30:34.93#ibcon#enter sib2, iclass 7, count 0 2006.173.03:30:34.93#ibcon#flushed, iclass 7, count 0 2006.173.03:30:34.93#ibcon#about to write, iclass 7, count 0 2006.173.03:30:34.93#ibcon#wrote, iclass 7, count 0 2006.173.03:30:34.93#ibcon#about to read 3, iclass 7, count 0 2006.173.03:30:34.96#ibcon#read 3, iclass 7, count 0 2006.173.03:30:34.96#ibcon#about to read 4, iclass 7, count 0 2006.173.03:30:34.96#ibcon#read 4, iclass 7, count 0 2006.173.03:30:34.96#ibcon#about to read 5, iclass 7, count 0 2006.173.03:30:34.96#ibcon#read 5, iclass 7, count 0 2006.173.03:30:34.96#ibcon#about to read 6, iclass 7, count 0 2006.173.03:30:34.96#ibcon#read 6, iclass 7, count 0 2006.173.03:30:34.96#ibcon#end of sib2, iclass 7, count 0 2006.173.03:30:34.96#ibcon#*after write, iclass 7, count 0 2006.173.03:30:34.96#ibcon#*before return 0, iclass 7, count 0 2006.173.03:30:34.96#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.03:30:34.96#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.03:30:34.96#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.03:30:34.96#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.03:30:34.96$setupk4/ifdk4 2006.173.03:30:34.96$ifdk4/lo= 2006.173.03:30:34.96$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.03:30:34.96$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.03:30:34.96$ifdk4/patch= 2006.173.03:30:34.96$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.03:30:34.96$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.03:30:34.96$setupk4/!*+20s 2006.173.03:30:39.36#abcon#<5=/14 1.1 2.6 22.61 841006.3\r\n> 2006.173.03:30:39.38#abcon#{5=INTERFACE CLEAR} 2006.173.03:30:39.44#abcon#[5=S1D000X0/0*\r\n] 2006.173.03:30:49.48$setupk4/"tpicd 2006.173.03:30:49.48$setupk4/echo=off 2006.173.03:30:49.48$setupk4/xlog=off 2006.173.03:30:49.48:!2006.173.03:32:24 2006.173.03:30:49.53#abcon#<5=/14 1.1 2.6 22.62 841006.3\r\n> 2006.173.03:30:52.14#trakl#Source acquired 2006.173.03:30:52.14#flagr#flagr/antenna,acquired 2006.173.03:32:24.00:preob 2006.173.03:32:24.13/onsource/TRACKING 2006.173.03:32:24.13:!2006.173.03:32:34 2006.173.03:32:34.00:"tape 2006.173.03:32:34.00:"st=record 2006.173.03:32:34.00:data_valid=on 2006.173.03:32:34.00:midob 2006.173.03:32:34.13/onsource/TRACKING 2006.173.03:32:34.13/wx/22.65,1006.3,84 2006.173.03:32:34.21/cable/+6.5109E-03 2006.173.03:32:35.30/va/01,07,usb,yes,36,39 2006.173.03:32:35.30/va/02,06,usb,yes,36,37 2006.173.03:32:35.30/va/03,05,usb,yes,46,48 2006.173.03:32:35.30/va/04,06,usb,yes,37,39 2006.173.03:32:35.30/va/05,04,usb,yes,29,29 2006.173.03:32:35.30/va/06,03,usb,yes,40,40 2006.173.03:32:35.30/va/07,04,usb,yes,33,34 2006.173.03:32:35.30/va/08,04,usb,yes,28,34 2006.173.03:32:35.53/valo/01,524.99,yes,locked 2006.173.03:32:35.53/valo/02,534.99,yes,locked 2006.173.03:32:35.53/valo/03,564.99,yes,locked 2006.173.03:32:35.53/valo/04,624.99,yes,locked 2006.173.03:32:35.53/valo/05,734.99,yes,locked 2006.173.03:32:35.53/valo/06,814.99,yes,locked 2006.173.03:32:35.53/valo/07,864.99,yes,locked 2006.173.03:32:35.53/valo/08,884.99,yes,locked 2006.173.03:32:36.62/vb/01,04,usb,yes,30,27 2006.173.03:32:36.62/vb/02,04,usb,yes,32,32 2006.173.03:32:36.62/vb/03,04,usb,yes,29,32 2006.173.03:32:36.62/vb/04,04,usb,yes,33,32 2006.173.03:32:36.62/vb/05,04,usb,yes,26,28 2006.173.03:32:36.62/vb/06,04,usb,yes,30,26 2006.173.03:32:36.62/vb/07,04,usb,yes,30,30 2006.173.03:32:36.62/vb/08,04,usb,yes,27,31 2006.173.03:32:36.85/vblo/01,629.99,yes,locked 2006.173.03:32:36.85/vblo/02,634.99,yes,locked 2006.173.03:32:36.85/vblo/03,649.99,yes,locked 2006.173.03:32:36.85/vblo/04,679.99,yes,locked 2006.173.03:32:36.85/vblo/05,709.99,yes,locked 2006.173.03:32:36.85/vblo/06,719.99,yes,locked 2006.173.03:32:36.85/vblo/07,734.99,yes,locked 2006.173.03:32:36.85/vblo/08,744.99,yes,locked 2006.173.03:32:37.00/vabw/8 2006.173.03:32:37.15/vbbw/8 2006.173.03:32:37.35/xfe/off,on,15.0 2006.173.03:32:37.73/ifatt/23,28,28,28 2006.173.03:32:38.08/fmout-gps/S +3.96E-07 2006.173.03:32:38.12:!2006.173.03:36:54 2006.173.03:36:54.01:data_valid=off 2006.173.03:36:54.02:"et 2006.173.03:36:54.02:!+3s 2006.173.03:36:57.03:"tape 2006.173.03:36:57.04:postob 2006.173.03:36:57.20/cable/+6.5107E-03 2006.173.03:36:57.21/wx/22.68,1006.3,83 2006.173.03:36:57.26/fmout-gps/S +3.96E-07 2006.173.03:36:57.27:scan_name=173-0346,jd0606,450 2006.173.03:36:57.27:source=1308+326,131028.66,322043.8,2000.0,cw 2006.173.03:36:58.14#flagr#flagr/antenna,new-source 2006.173.03:36:58.14:checkk5 2006.173.03:36:58.49/chk_autoobs//k5ts1/ autoobs is running! 2006.173.03:36:58.84/chk_autoobs//k5ts2/ autoobs is running! 2006.173.03:36:59.18/chk_autoobs//k5ts3/ autoobs is running! 2006.173.03:36:59.52/chk_autoobs//k5ts4/ autoobs is running! 2006.173.03:36:59.85/chk_obsdata//k5ts1/T1730332??a.dat file size is correct (nominal:1040MB, actual:1036MB). 2006.173.03:37:00.19/chk_obsdata//k5ts2/T1730332??b.dat file size is correct (nominal:1040MB, actual:1036MB). 2006.173.03:37:00.52/chk_obsdata//k5ts3/T1730332??c.dat file size is correct (nominal:1040MB, actual:1036MB). 2006.173.03:37:00.85/chk_obsdata//k5ts4/T1730332??d.dat file size is correct (nominal:1040MB, actual:1036MB). 2006.173.03:37:01.51/k5log//k5ts1_log_newline 2006.173.03:37:02.16/k5log//k5ts2_log_newline 2006.173.03:37:02.81/k5log//k5ts3_log_newline 2006.173.03:37:03.46/k5log//k5ts4_log_newline 2006.173.03:37:03.49/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.03:37:03.49:setupk4=1 2006.173.03:37:03.49$setupk4/echo=on 2006.173.03:37:03.49$setupk4/pcalon 2006.173.03:37:03.49$pcalon/"no phase cal control is implemented here 2006.173.03:37:03.49$setupk4/"tpicd=stop 2006.173.03:37:03.49$setupk4/"rec=synch_on 2006.173.03:37:03.49$setupk4/"rec_mode=128 2006.173.03:37:03.49$setupk4/!* 2006.173.03:37:03.49$setupk4/recpk4 2006.173.03:37:03.49$recpk4/recpatch= 2006.173.03:37:03.49$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.03:37:03.49$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.03:37:03.49$setupk4/vck44 2006.173.03:37:03.49$vck44/valo=1,524.99 2006.173.03:37:03.49#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.03:37:03.49#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.03:37:03.49#ibcon#ireg 17 cls_cnt 0 2006.173.03:37:03.49#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.03:37:03.49#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.03:37:03.49#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.03:37:03.49#ibcon#enter wrdev, iclass 22, count 0 2006.173.03:37:03.49#ibcon#first serial, iclass 22, count 0 2006.173.03:37:03.49#ibcon#enter sib2, iclass 22, count 0 2006.173.03:37:03.49#ibcon#flushed, iclass 22, count 0 2006.173.03:37:03.49#ibcon#about to write, iclass 22, count 0 2006.173.03:37:03.49#ibcon#wrote, iclass 22, count 0 2006.173.03:37:03.49#ibcon#about to read 3, iclass 22, count 0 2006.173.03:37:03.51#ibcon#read 3, iclass 22, count 0 2006.173.03:37:03.51#ibcon#about to read 4, iclass 22, count 0 2006.173.03:37:03.51#ibcon#read 4, iclass 22, count 0 2006.173.03:37:03.51#ibcon#about to read 5, iclass 22, count 0 2006.173.03:37:03.51#ibcon#read 5, iclass 22, count 0 2006.173.03:37:03.51#ibcon#about to read 6, iclass 22, count 0 2006.173.03:37:03.51#ibcon#read 6, iclass 22, count 0 2006.173.03:37:03.51#ibcon#end of sib2, iclass 22, count 0 2006.173.03:37:03.51#ibcon#*mode == 0, iclass 22, count 0 2006.173.03:37:03.51#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.03:37:03.51#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.03:37:03.51#ibcon#*before write, iclass 22, count 0 2006.173.03:37:03.51#ibcon#enter sib2, iclass 22, count 0 2006.173.03:37:03.51#ibcon#flushed, iclass 22, count 0 2006.173.03:37:03.51#ibcon#about to write, iclass 22, count 0 2006.173.03:37:03.51#ibcon#wrote, iclass 22, count 0 2006.173.03:37:03.51#ibcon#about to read 3, iclass 22, count 0 2006.173.03:37:03.56#ibcon#read 3, iclass 22, count 0 2006.173.03:37:03.56#ibcon#about to read 4, iclass 22, count 0 2006.173.03:37:03.56#ibcon#read 4, iclass 22, count 0 2006.173.03:37:03.56#ibcon#about to read 5, iclass 22, count 0 2006.173.03:37:03.56#ibcon#read 5, iclass 22, count 0 2006.173.03:37:03.56#ibcon#about to read 6, iclass 22, count 0 2006.173.03:37:03.56#ibcon#read 6, iclass 22, count 0 2006.173.03:37:03.56#ibcon#end of sib2, iclass 22, count 0 2006.173.03:37:03.56#ibcon#*after write, iclass 22, count 0 2006.173.03:37:03.56#ibcon#*before return 0, iclass 22, count 0 2006.173.03:37:03.56#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.03:37:03.56#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.03:37:03.56#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.03:37:03.56#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.03:37:03.56$vck44/va=1,7 2006.173.03:37:03.56#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.03:37:03.56#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.03:37:03.56#ibcon#ireg 11 cls_cnt 2 2006.173.03:37:03.56#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.03:37:03.56#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.03:37:03.56#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.03:37:03.56#ibcon#enter wrdev, iclass 24, count 2 2006.173.03:37:03.56#ibcon#first serial, iclass 24, count 2 2006.173.03:37:03.56#ibcon#enter sib2, iclass 24, count 2 2006.173.03:37:03.56#ibcon#flushed, iclass 24, count 2 2006.173.03:37:03.56#ibcon#about to write, iclass 24, count 2 2006.173.03:37:03.56#ibcon#wrote, iclass 24, count 2 2006.173.03:37:03.56#ibcon#about to read 3, iclass 24, count 2 2006.173.03:37:03.58#ibcon#read 3, iclass 24, count 2 2006.173.03:37:03.58#ibcon#about to read 4, iclass 24, count 2 2006.173.03:37:03.58#ibcon#read 4, iclass 24, count 2 2006.173.03:37:03.58#ibcon#about to read 5, iclass 24, count 2 2006.173.03:37:03.58#ibcon#read 5, iclass 24, count 2 2006.173.03:37:03.58#ibcon#about to read 6, iclass 24, count 2 2006.173.03:37:03.58#ibcon#read 6, iclass 24, count 2 2006.173.03:37:03.58#ibcon#end of sib2, iclass 24, count 2 2006.173.03:37:03.58#ibcon#*mode == 0, iclass 24, count 2 2006.173.03:37:03.58#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.03:37:03.58#ibcon#[25=AT01-07\r\n] 2006.173.03:37:03.58#ibcon#*before write, iclass 24, count 2 2006.173.03:37:03.58#ibcon#enter sib2, iclass 24, count 2 2006.173.03:37:03.58#ibcon#flushed, iclass 24, count 2 2006.173.03:37:03.58#ibcon#about to write, iclass 24, count 2 2006.173.03:37:03.58#ibcon#wrote, iclass 24, count 2 2006.173.03:37:03.58#ibcon#about to read 3, iclass 24, count 2 2006.173.03:37:03.61#ibcon#read 3, iclass 24, count 2 2006.173.03:37:03.61#ibcon#about to read 4, iclass 24, count 2 2006.173.03:37:03.61#ibcon#read 4, iclass 24, count 2 2006.173.03:37:03.61#ibcon#about to read 5, iclass 24, count 2 2006.173.03:37:03.61#ibcon#read 5, iclass 24, count 2 2006.173.03:37:03.61#ibcon#about to read 6, iclass 24, count 2 2006.173.03:37:03.61#ibcon#read 6, iclass 24, count 2 2006.173.03:37:03.61#ibcon#end of sib2, iclass 24, count 2 2006.173.03:37:03.61#ibcon#*after write, iclass 24, count 2 2006.173.03:37:03.61#ibcon#*before return 0, iclass 24, count 2 2006.173.03:37:03.61#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.03:37:03.61#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.03:37:03.61#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.03:37:03.61#ibcon#ireg 7 cls_cnt 0 2006.173.03:37:03.61#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.03:37:03.73#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.03:37:03.73#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.03:37:03.73#ibcon#enter wrdev, iclass 24, count 0 2006.173.03:37:03.73#ibcon#first serial, iclass 24, count 0 2006.173.03:37:03.73#ibcon#enter sib2, iclass 24, count 0 2006.173.03:37:03.73#ibcon#flushed, iclass 24, count 0 2006.173.03:37:03.73#ibcon#about to write, iclass 24, count 0 2006.173.03:37:03.73#ibcon#wrote, iclass 24, count 0 2006.173.03:37:03.73#ibcon#about to read 3, iclass 24, count 0 2006.173.03:37:03.75#ibcon#read 3, iclass 24, count 0 2006.173.03:37:03.75#ibcon#about to read 4, iclass 24, count 0 2006.173.03:37:03.75#ibcon#read 4, iclass 24, count 0 2006.173.03:37:03.75#ibcon#about to read 5, iclass 24, count 0 2006.173.03:37:03.75#ibcon#read 5, iclass 24, count 0 2006.173.03:37:03.75#ibcon#about to read 6, iclass 24, count 0 2006.173.03:37:03.75#ibcon#read 6, iclass 24, count 0 2006.173.03:37:03.75#ibcon#end of sib2, iclass 24, count 0 2006.173.03:37:03.75#ibcon#*mode == 0, iclass 24, count 0 2006.173.03:37:03.75#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.03:37:03.75#ibcon#[25=USB\r\n] 2006.173.03:37:03.75#ibcon#*before write, iclass 24, count 0 2006.173.03:37:03.75#ibcon#enter sib2, iclass 24, count 0 2006.173.03:37:03.75#ibcon#flushed, iclass 24, count 0 2006.173.03:37:03.75#ibcon#about to write, iclass 24, count 0 2006.173.03:37:03.75#ibcon#wrote, iclass 24, count 0 2006.173.03:37:03.75#ibcon#about to read 3, iclass 24, count 0 2006.173.03:37:03.78#ibcon#read 3, iclass 24, count 0 2006.173.03:37:03.78#ibcon#about to read 4, iclass 24, count 0 2006.173.03:37:03.78#ibcon#read 4, iclass 24, count 0 2006.173.03:37:03.78#ibcon#about to read 5, iclass 24, count 0 2006.173.03:37:03.78#ibcon#read 5, iclass 24, count 0 2006.173.03:37:03.78#ibcon#about to read 6, iclass 24, count 0 2006.173.03:37:03.78#ibcon#read 6, iclass 24, count 0 2006.173.03:37:03.78#ibcon#end of sib2, iclass 24, count 0 2006.173.03:37:03.78#ibcon#*after write, iclass 24, count 0 2006.173.03:37:03.78#ibcon#*before return 0, iclass 24, count 0 2006.173.03:37:03.78#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.03:37:03.78#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.03:37:03.78#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.03:37:03.78#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.03:37:03.78$vck44/valo=2,534.99 2006.173.03:37:03.78#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.03:37:03.78#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.03:37:03.78#ibcon#ireg 17 cls_cnt 0 2006.173.03:37:03.78#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.03:37:03.78#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.03:37:03.78#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.03:37:03.78#ibcon#enter wrdev, iclass 26, count 0 2006.173.03:37:03.78#ibcon#first serial, iclass 26, count 0 2006.173.03:37:03.78#ibcon#enter sib2, iclass 26, count 0 2006.173.03:37:03.78#ibcon#flushed, iclass 26, count 0 2006.173.03:37:03.78#ibcon#about to write, iclass 26, count 0 2006.173.03:37:03.78#ibcon#wrote, iclass 26, count 0 2006.173.03:37:03.78#ibcon#about to read 3, iclass 26, count 0 2006.173.03:37:03.80#ibcon#read 3, iclass 26, count 0 2006.173.03:37:03.80#ibcon#about to read 4, iclass 26, count 0 2006.173.03:37:03.80#ibcon#read 4, iclass 26, count 0 2006.173.03:37:03.80#ibcon#about to read 5, iclass 26, count 0 2006.173.03:37:03.80#ibcon#read 5, iclass 26, count 0 2006.173.03:37:03.80#ibcon#about to read 6, iclass 26, count 0 2006.173.03:37:03.80#ibcon#read 6, iclass 26, count 0 2006.173.03:37:03.80#ibcon#end of sib2, iclass 26, count 0 2006.173.03:37:03.80#ibcon#*mode == 0, iclass 26, count 0 2006.173.03:37:03.80#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.03:37:03.80#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.03:37:03.80#ibcon#*before write, iclass 26, count 0 2006.173.03:37:03.80#ibcon#enter sib2, iclass 26, count 0 2006.173.03:37:03.80#ibcon#flushed, iclass 26, count 0 2006.173.03:37:03.80#ibcon#about to write, iclass 26, count 0 2006.173.03:37:03.80#ibcon#wrote, iclass 26, count 0 2006.173.03:37:03.80#ibcon#about to read 3, iclass 26, count 0 2006.173.03:37:03.84#ibcon#read 3, iclass 26, count 0 2006.173.03:37:03.84#ibcon#about to read 4, iclass 26, count 0 2006.173.03:37:03.84#ibcon#read 4, iclass 26, count 0 2006.173.03:37:03.84#ibcon#about to read 5, iclass 26, count 0 2006.173.03:37:03.84#ibcon#read 5, iclass 26, count 0 2006.173.03:37:03.84#ibcon#about to read 6, iclass 26, count 0 2006.173.03:37:03.84#ibcon#read 6, iclass 26, count 0 2006.173.03:37:03.84#ibcon#end of sib2, iclass 26, count 0 2006.173.03:37:03.84#ibcon#*after write, iclass 26, count 0 2006.173.03:37:03.84#ibcon#*before return 0, iclass 26, count 0 2006.173.03:37:03.84#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.03:37:03.84#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.03:37:03.84#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.03:37:03.84#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.03:37:03.84$vck44/va=2,6 2006.173.03:37:03.84#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.03:37:03.84#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.03:37:03.84#ibcon#ireg 11 cls_cnt 2 2006.173.03:37:03.84#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.03:37:03.90#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.03:37:03.90#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.03:37:03.90#ibcon#enter wrdev, iclass 28, count 2 2006.173.03:37:03.90#ibcon#first serial, iclass 28, count 2 2006.173.03:37:03.90#ibcon#enter sib2, iclass 28, count 2 2006.173.03:37:03.90#ibcon#flushed, iclass 28, count 2 2006.173.03:37:03.90#ibcon#about to write, iclass 28, count 2 2006.173.03:37:03.90#ibcon#wrote, iclass 28, count 2 2006.173.03:37:03.90#ibcon#about to read 3, iclass 28, count 2 2006.173.03:37:03.92#ibcon#read 3, iclass 28, count 2 2006.173.03:37:03.92#ibcon#about to read 4, iclass 28, count 2 2006.173.03:37:03.92#ibcon#read 4, iclass 28, count 2 2006.173.03:37:03.92#ibcon#about to read 5, iclass 28, count 2 2006.173.03:37:03.92#ibcon#read 5, iclass 28, count 2 2006.173.03:37:03.92#ibcon#about to read 6, iclass 28, count 2 2006.173.03:37:03.92#ibcon#read 6, iclass 28, count 2 2006.173.03:37:03.92#ibcon#end of sib2, iclass 28, count 2 2006.173.03:37:03.92#ibcon#*mode == 0, iclass 28, count 2 2006.173.03:37:03.92#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.03:37:03.92#ibcon#[25=AT02-06\r\n] 2006.173.03:37:03.92#ibcon#*before write, iclass 28, count 2 2006.173.03:37:03.92#ibcon#enter sib2, iclass 28, count 2 2006.173.03:37:03.92#ibcon#flushed, iclass 28, count 2 2006.173.03:37:03.92#ibcon#about to write, iclass 28, count 2 2006.173.03:37:03.92#ibcon#wrote, iclass 28, count 2 2006.173.03:37:03.92#ibcon#about to read 3, iclass 28, count 2 2006.173.03:37:03.95#ibcon#read 3, iclass 28, count 2 2006.173.03:37:03.95#ibcon#about to read 4, iclass 28, count 2 2006.173.03:37:03.95#ibcon#read 4, iclass 28, count 2 2006.173.03:37:03.95#ibcon#about to read 5, iclass 28, count 2 2006.173.03:37:03.95#ibcon#read 5, iclass 28, count 2 2006.173.03:37:03.95#ibcon#about to read 6, iclass 28, count 2 2006.173.03:37:03.95#ibcon#read 6, iclass 28, count 2 2006.173.03:37:03.95#ibcon#end of sib2, iclass 28, count 2 2006.173.03:37:03.95#ibcon#*after write, iclass 28, count 2 2006.173.03:37:03.95#ibcon#*before return 0, iclass 28, count 2 2006.173.03:37:03.95#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.03:37:03.95#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.03:37:03.95#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.03:37:03.95#ibcon#ireg 7 cls_cnt 0 2006.173.03:37:03.95#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.03:37:04.07#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.03:37:04.07#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.03:37:04.07#ibcon#enter wrdev, iclass 28, count 0 2006.173.03:37:04.07#ibcon#first serial, iclass 28, count 0 2006.173.03:37:04.07#ibcon#enter sib2, iclass 28, count 0 2006.173.03:37:04.07#ibcon#flushed, iclass 28, count 0 2006.173.03:37:04.07#ibcon#about to write, iclass 28, count 0 2006.173.03:37:04.07#ibcon#wrote, iclass 28, count 0 2006.173.03:37:04.07#ibcon#about to read 3, iclass 28, count 0 2006.173.03:37:04.09#ibcon#read 3, iclass 28, count 0 2006.173.03:37:04.09#ibcon#about to read 4, iclass 28, count 0 2006.173.03:37:04.09#ibcon#read 4, iclass 28, count 0 2006.173.03:37:04.09#ibcon#about to read 5, iclass 28, count 0 2006.173.03:37:04.09#ibcon#read 5, iclass 28, count 0 2006.173.03:37:04.09#ibcon#about to read 6, iclass 28, count 0 2006.173.03:37:04.09#ibcon#read 6, iclass 28, count 0 2006.173.03:37:04.09#ibcon#end of sib2, iclass 28, count 0 2006.173.03:37:04.09#ibcon#*mode == 0, iclass 28, count 0 2006.173.03:37:04.09#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.03:37:04.09#ibcon#[25=USB\r\n] 2006.173.03:37:04.09#ibcon#*before write, iclass 28, count 0 2006.173.03:37:04.09#ibcon#enter sib2, iclass 28, count 0 2006.173.03:37:04.09#ibcon#flushed, iclass 28, count 0 2006.173.03:37:04.09#ibcon#about to write, iclass 28, count 0 2006.173.03:37:04.09#ibcon#wrote, iclass 28, count 0 2006.173.03:37:04.09#ibcon#about to read 3, iclass 28, count 0 2006.173.03:37:04.12#ibcon#read 3, iclass 28, count 0 2006.173.03:37:04.12#ibcon#about to read 4, iclass 28, count 0 2006.173.03:37:04.12#ibcon#read 4, iclass 28, count 0 2006.173.03:37:04.12#ibcon#about to read 5, iclass 28, count 0 2006.173.03:37:04.12#ibcon#read 5, iclass 28, count 0 2006.173.03:37:04.12#ibcon#about to read 6, iclass 28, count 0 2006.173.03:37:04.12#ibcon#read 6, iclass 28, count 0 2006.173.03:37:04.12#ibcon#end of sib2, iclass 28, count 0 2006.173.03:37:04.12#ibcon#*after write, iclass 28, count 0 2006.173.03:37:04.12#ibcon#*before return 0, iclass 28, count 0 2006.173.03:37:04.12#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.03:37:04.12#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.03:37:04.12#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.03:37:04.12#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.03:37:04.12$vck44/valo=3,564.99 2006.173.03:37:04.12#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.03:37:04.12#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.03:37:04.12#ibcon#ireg 17 cls_cnt 0 2006.173.03:37:04.12#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.03:37:04.12#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.03:37:04.12#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.03:37:04.12#ibcon#enter wrdev, iclass 30, count 0 2006.173.03:37:04.12#ibcon#first serial, iclass 30, count 0 2006.173.03:37:04.12#ibcon#enter sib2, iclass 30, count 0 2006.173.03:37:04.12#ibcon#flushed, iclass 30, count 0 2006.173.03:37:04.12#ibcon#about to write, iclass 30, count 0 2006.173.03:37:04.12#ibcon#wrote, iclass 30, count 0 2006.173.03:37:04.12#ibcon#about to read 3, iclass 30, count 0 2006.173.03:37:04.14#ibcon#read 3, iclass 30, count 0 2006.173.03:37:04.14#ibcon#about to read 4, iclass 30, count 0 2006.173.03:37:04.14#ibcon#read 4, iclass 30, count 0 2006.173.03:37:04.14#ibcon#about to read 5, iclass 30, count 0 2006.173.03:37:04.14#ibcon#read 5, iclass 30, count 0 2006.173.03:37:04.14#ibcon#about to read 6, iclass 30, count 0 2006.173.03:37:04.14#ibcon#read 6, iclass 30, count 0 2006.173.03:37:04.14#ibcon#end of sib2, iclass 30, count 0 2006.173.03:37:04.14#ibcon#*mode == 0, iclass 30, count 0 2006.173.03:37:04.14#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.03:37:04.14#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.03:37:04.14#ibcon#*before write, iclass 30, count 0 2006.173.03:37:04.14#ibcon#enter sib2, iclass 30, count 0 2006.173.03:37:04.14#ibcon#flushed, iclass 30, count 0 2006.173.03:37:04.14#ibcon#about to write, iclass 30, count 0 2006.173.03:37:04.14#ibcon#wrote, iclass 30, count 0 2006.173.03:37:04.14#ibcon#about to read 3, iclass 30, count 0 2006.173.03:37:04.18#ibcon#read 3, iclass 30, count 0 2006.173.03:37:04.18#ibcon#about to read 4, iclass 30, count 0 2006.173.03:37:04.18#ibcon#read 4, iclass 30, count 0 2006.173.03:37:04.18#ibcon#about to read 5, iclass 30, count 0 2006.173.03:37:04.18#ibcon#read 5, iclass 30, count 0 2006.173.03:37:04.18#ibcon#about to read 6, iclass 30, count 0 2006.173.03:37:04.18#ibcon#read 6, iclass 30, count 0 2006.173.03:37:04.18#ibcon#end of sib2, iclass 30, count 0 2006.173.03:37:04.18#ibcon#*after write, iclass 30, count 0 2006.173.03:37:04.18#ibcon#*before return 0, iclass 30, count 0 2006.173.03:37:04.18#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.03:37:04.18#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.03:37:04.18#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.03:37:04.18#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.03:37:04.18$vck44/va=3,5 2006.173.03:37:04.18#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.173.03:37:04.18#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.173.03:37:04.18#ibcon#ireg 11 cls_cnt 2 2006.173.03:37:04.18#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.03:37:04.24#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.03:37:04.24#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.03:37:04.24#ibcon#enter wrdev, iclass 32, count 2 2006.173.03:37:04.24#ibcon#first serial, iclass 32, count 2 2006.173.03:37:04.24#ibcon#enter sib2, iclass 32, count 2 2006.173.03:37:04.24#ibcon#flushed, iclass 32, count 2 2006.173.03:37:04.24#ibcon#about to write, iclass 32, count 2 2006.173.03:37:04.24#ibcon#wrote, iclass 32, count 2 2006.173.03:37:04.24#ibcon#about to read 3, iclass 32, count 2 2006.173.03:37:04.26#ibcon#read 3, iclass 32, count 2 2006.173.03:37:04.26#ibcon#about to read 4, iclass 32, count 2 2006.173.03:37:04.26#ibcon#read 4, iclass 32, count 2 2006.173.03:37:04.26#ibcon#about to read 5, iclass 32, count 2 2006.173.03:37:04.26#ibcon#read 5, iclass 32, count 2 2006.173.03:37:04.26#ibcon#about to read 6, iclass 32, count 2 2006.173.03:37:04.26#ibcon#read 6, iclass 32, count 2 2006.173.03:37:04.26#ibcon#end of sib2, iclass 32, count 2 2006.173.03:37:04.26#ibcon#*mode == 0, iclass 32, count 2 2006.173.03:37:04.26#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.173.03:37:04.26#ibcon#[25=AT03-05\r\n] 2006.173.03:37:04.26#ibcon#*before write, iclass 32, count 2 2006.173.03:37:04.26#ibcon#enter sib2, iclass 32, count 2 2006.173.03:37:04.26#ibcon#flushed, iclass 32, count 2 2006.173.03:37:04.26#ibcon#about to write, iclass 32, count 2 2006.173.03:37:04.26#ibcon#wrote, iclass 32, count 2 2006.173.03:37:04.26#ibcon#about to read 3, iclass 32, count 2 2006.173.03:37:04.29#ibcon#read 3, iclass 32, count 2 2006.173.03:37:04.29#ibcon#about to read 4, iclass 32, count 2 2006.173.03:37:04.29#ibcon#read 4, iclass 32, count 2 2006.173.03:37:04.29#ibcon#about to read 5, iclass 32, count 2 2006.173.03:37:04.29#ibcon#read 5, iclass 32, count 2 2006.173.03:37:04.29#ibcon#about to read 6, iclass 32, count 2 2006.173.03:37:04.29#ibcon#read 6, iclass 32, count 2 2006.173.03:37:04.29#ibcon#end of sib2, iclass 32, count 2 2006.173.03:37:04.29#ibcon#*after write, iclass 32, count 2 2006.173.03:37:04.29#ibcon#*before return 0, iclass 32, count 2 2006.173.03:37:04.29#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.03:37:04.29#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.173.03:37:04.29#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.173.03:37:04.29#ibcon#ireg 7 cls_cnt 0 2006.173.03:37:04.29#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.03:37:04.41#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.03:37:04.41#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.03:37:04.41#ibcon#enter wrdev, iclass 32, count 0 2006.173.03:37:04.41#ibcon#first serial, iclass 32, count 0 2006.173.03:37:04.41#ibcon#enter sib2, iclass 32, count 0 2006.173.03:37:04.41#ibcon#flushed, iclass 32, count 0 2006.173.03:37:04.41#ibcon#about to write, iclass 32, count 0 2006.173.03:37:04.41#ibcon#wrote, iclass 32, count 0 2006.173.03:37:04.41#ibcon#about to read 3, iclass 32, count 0 2006.173.03:37:04.43#ibcon#read 3, iclass 32, count 0 2006.173.03:37:04.43#ibcon#about to read 4, iclass 32, count 0 2006.173.03:37:04.43#ibcon#read 4, iclass 32, count 0 2006.173.03:37:04.43#ibcon#about to read 5, iclass 32, count 0 2006.173.03:37:04.43#ibcon#read 5, iclass 32, count 0 2006.173.03:37:04.43#ibcon#about to read 6, iclass 32, count 0 2006.173.03:37:04.43#ibcon#read 6, iclass 32, count 0 2006.173.03:37:04.43#ibcon#end of sib2, iclass 32, count 0 2006.173.03:37:04.43#ibcon#*mode == 0, iclass 32, count 0 2006.173.03:37:04.43#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.03:37:04.43#ibcon#[25=USB\r\n] 2006.173.03:37:04.43#ibcon#*before write, iclass 32, count 0 2006.173.03:37:04.43#ibcon#enter sib2, iclass 32, count 0 2006.173.03:37:04.43#ibcon#flushed, iclass 32, count 0 2006.173.03:37:04.43#ibcon#about to write, iclass 32, count 0 2006.173.03:37:04.43#ibcon#wrote, iclass 32, count 0 2006.173.03:37:04.43#ibcon#about to read 3, iclass 32, count 0 2006.173.03:37:04.46#ibcon#read 3, iclass 32, count 0 2006.173.03:37:04.46#ibcon#about to read 4, iclass 32, count 0 2006.173.03:37:04.46#ibcon#read 4, iclass 32, count 0 2006.173.03:37:04.46#ibcon#about to read 5, iclass 32, count 0 2006.173.03:37:04.46#ibcon#read 5, iclass 32, count 0 2006.173.03:37:04.46#ibcon#about to read 6, iclass 32, count 0 2006.173.03:37:04.46#ibcon#read 6, iclass 32, count 0 2006.173.03:37:04.46#ibcon#end of sib2, iclass 32, count 0 2006.173.03:37:04.46#ibcon#*after write, iclass 32, count 0 2006.173.03:37:04.46#ibcon#*before return 0, iclass 32, count 0 2006.173.03:37:04.46#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.03:37:04.46#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.173.03:37:04.46#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.03:37:04.46#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.03:37:04.46$vck44/valo=4,624.99 2006.173.03:37:04.46#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.03:37:04.46#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.03:37:04.46#ibcon#ireg 17 cls_cnt 0 2006.173.03:37:04.46#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.03:37:04.46#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.03:37:04.46#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.03:37:04.46#ibcon#enter wrdev, iclass 34, count 0 2006.173.03:37:04.46#ibcon#first serial, iclass 34, count 0 2006.173.03:37:04.46#ibcon#enter sib2, iclass 34, count 0 2006.173.03:37:04.46#ibcon#flushed, iclass 34, count 0 2006.173.03:37:04.46#ibcon#about to write, iclass 34, count 0 2006.173.03:37:04.46#ibcon#wrote, iclass 34, count 0 2006.173.03:37:04.46#ibcon#about to read 3, iclass 34, count 0 2006.173.03:37:04.48#ibcon#read 3, iclass 34, count 0 2006.173.03:37:04.48#ibcon#about to read 4, iclass 34, count 0 2006.173.03:37:04.48#ibcon#read 4, iclass 34, count 0 2006.173.03:37:04.48#ibcon#about to read 5, iclass 34, count 0 2006.173.03:37:04.48#ibcon#read 5, iclass 34, count 0 2006.173.03:37:04.48#ibcon#about to read 6, iclass 34, count 0 2006.173.03:37:04.48#ibcon#read 6, iclass 34, count 0 2006.173.03:37:04.48#ibcon#end of sib2, iclass 34, count 0 2006.173.03:37:04.48#ibcon#*mode == 0, iclass 34, count 0 2006.173.03:37:04.48#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.03:37:04.48#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.03:37:04.48#ibcon#*before write, iclass 34, count 0 2006.173.03:37:04.48#ibcon#enter sib2, iclass 34, count 0 2006.173.03:37:04.48#ibcon#flushed, iclass 34, count 0 2006.173.03:37:04.48#ibcon#about to write, iclass 34, count 0 2006.173.03:37:04.48#ibcon#wrote, iclass 34, count 0 2006.173.03:37:04.48#ibcon#about to read 3, iclass 34, count 0 2006.173.03:37:04.52#ibcon#read 3, iclass 34, count 0 2006.173.03:37:04.52#ibcon#about to read 4, iclass 34, count 0 2006.173.03:37:04.52#ibcon#read 4, iclass 34, count 0 2006.173.03:37:04.52#ibcon#about to read 5, iclass 34, count 0 2006.173.03:37:04.52#ibcon#read 5, iclass 34, count 0 2006.173.03:37:04.52#ibcon#about to read 6, iclass 34, count 0 2006.173.03:37:04.52#ibcon#read 6, iclass 34, count 0 2006.173.03:37:04.52#ibcon#end of sib2, iclass 34, count 0 2006.173.03:37:04.52#ibcon#*after write, iclass 34, count 0 2006.173.03:37:04.52#ibcon#*before return 0, iclass 34, count 0 2006.173.03:37:04.52#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.03:37:04.52#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.03:37:04.52#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.03:37:04.52#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.03:37:04.52$vck44/va=4,6 2006.173.03:37:04.52#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.03:37:04.52#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.03:37:04.52#ibcon#ireg 11 cls_cnt 2 2006.173.03:37:04.52#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.03:37:04.58#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.03:37:04.58#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.03:37:04.58#ibcon#enter wrdev, iclass 36, count 2 2006.173.03:37:04.58#ibcon#first serial, iclass 36, count 2 2006.173.03:37:04.58#ibcon#enter sib2, iclass 36, count 2 2006.173.03:37:04.58#ibcon#flushed, iclass 36, count 2 2006.173.03:37:04.58#ibcon#about to write, iclass 36, count 2 2006.173.03:37:04.58#ibcon#wrote, iclass 36, count 2 2006.173.03:37:04.58#ibcon#about to read 3, iclass 36, count 2 2006.173.03:37:04.60#ibcon#read 3, iclass 36, count 2 2006.173.03:37:04.60#ibcon#about to read 4, iclass 36, count 2 2006.173.03:37:04.60#ibcon#read 4, iclass 36, count 2 2006.173.03:37:04.60#ibcon#about to read 5, iclass 36, count 2 2006.173.03:37:04.60#ibcon#read 5, iclass 36, count 2 2006.173.03:37:04.60#ibcon#about to read 6, iclass 36, count 2 2006.173.03:37:04.60#ibcon#read 6, iclass 36, count 2 2006.173.03:37:04.60#ibcon#end of sib2, iclass 36, count 2 2006.173.03:37:04.60#ibcon#*mode == 0, iclass 36, count 2 2006.173.03:37:04.60#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.03:37:04.60#ibcon#[25=AT04-06\r\n] 2006.173.03:37:04.60#ibcon#*before write, iclass 36, count 2 2006.173.03:37:04.60#ibcon#enter sib2, iclass 36, count 2 2006.173.03:37:04.60#ibcon#flushed, iclass 36, count 2 2006.173.03:37:04.60#ibcon#about to write, iclass 36, count 2 2006.173.03:37:04.60#ibcon#wrote, iclass 36, count 2 2006.173.03:37:04.60#ibcon#about to read 3, iclass 36, count 2 2006.173.03:37:04.63#ibcon#read 3, iclass 36, count 2 2006.173.03:37:04.63#ibcon#about to read 4, iclass 36, count 2 2006.173.03:37:04.63#ibcon#read 4, iclass 36, count 2 2006.173.03:37:04.63#ibcon#about to read 5, iclass 36, count 2 2006.173.03:37:04.63#ibcon#read 5, iclass 36, count 2 2006.173.03:37:04.63#ibcon#about to read 6, iclass 36, count 2 2006.173.03:37:04.63#ibcon#read 6, iclass 36, count 2 2006.173.03:37:04.63#ibcon#end of sib2, iclass 36, count 2 2006.173.03:37:04.63#ibcon#*after write, iclass 36, count 2 2006.173.03:37:04.63#ibcon#*before return 0, iclass 36, count 2 2006.173.03:37:04.63#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.03:37:04.63#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.03:37:04.63#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.03:37:04.63#ibcon#ireg 7 cls_cnt 0 2006.173.03:37:04.63#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.03:37:04.75#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.03:37:04.75#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.03:37:04.75#ibcon#enter wrdev, iclass 36, count 0 2006.173.03:37:04.75#ibcon#first serial, iclass 36, count 0 2006.173.03:37:04.75#ibcon#enter sib2, iclass 36, count 0 2006.173.03:37:04.75#ibcon#flushed, iclass 36, count 0 2006.173.03:37:04.75#ibcon#about to write, iclass 36, count 0 2006.173.03:37:04.75#ibcon#wrote, iclass 36, count 0 2006.173.03:37:04.75#ibcon#about to read 3, iclass 36, count 0 2006.173.03:37:04.77#ibcon#read 3, iclass 36, count 0 2006.173.03:37:04.77#ibcon#about to read 4, iclass 36, count 0 2006.173.03:37:04.77#ibcon#read 4, iclass 36, count 0 2006.173.03:37:04.77#ibcon#about to read 5, iclass 36, count 0 2006.173.03:37:04.77#ibcon#read 5, iclass 36, count 0 2006.173.03:37:04.77#ibcon#about to read 6, iclass 36, count 0 2006.173.03:37:04.77#ibcon#read 6, iclass 36, count 0 2006.173.03:37:04.77#ibcon#end of sib2, iclass 36, count 0 2006.173.03:37:04.77#ibcon#*mode == 0, iclass 36, count 0 2006.173.03:37:04.77#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.03:37:04.77#ibcon#[25=USB\r\n] 2006.173.03:37:04.77#ibcon#*before write, iclass 36, count 0 2006.173.03:37:04.77#ibcon#enter sib2, iclass 36, count 0 2006.173.03:37:04.77#ibcon#flushed, iclass 36, count 0 2006.173.03:37:04.77#ibcon#about to write, iclass 36, count 0 2006.173.03:37:04.77#ibcon#wrote, iclass 36, count 0 2006.173.03:37:04.77#ibcon#about to read 3, iclass 36, count 0 2006.173.03:37:04.80#ibcon#read 3, iclass 36, count 0 2006.173.03:37:04.80#ibcon#about to read 4, iclass 36, count 0 2006.173.03:37:04.80#ibcon#read 4, iclass 36, count 0 2006.173.03:37:04.80#ibcon#about to read 5, iclass 36, count 0 2006.173.03:37:04.80#ibcon#read 5, iclass 36, count 0 2006.173.03:37:04.80#ibcon#about to read 6, iclass 36, count 0 2006.173.03:37:04.80#ibcon#read 6, iclass 36, count 0 2006.173.03:37:04.80#ibcon#end of sib2, iclass 36, count 0 2006.173.03:37:04.80#ibcon#*after write, iclass 36, count 0 2006.173.03:37:04.80#ibcon#*before return 0, iclass 36, count 0 2006.173.03:37:04.80#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.03:37:04.80#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.03:37:04.80#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.03:37:04.80#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.03:37:04.80$vck44/valo=5,734.99 2006.173.03:37:04.80#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.03:37:04.80#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.03:37:04.80#ibcon#ireg 17 cls_cnt 0 2006.173.03:37:04.80#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.03:37:04.80#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.03:37:04.80#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.03:37:04.80#ibcon#enter wrdev, iclass 38, count 0 2006.173.03:37:04.80#ibcon#first serial, iclass 38, count 0 2006.173.03:37:04.80#ibcon#enter sib2, iclass 38, count 0 2006.173.03:37:04.80#ibcon#flushed, iclass 38, count 0 2006.173.03:37:04.80#ibcon#about to write, iclass 38, count 0 2006.173.03:37:04.80#ibcon#wrote, iclass 38, count 0 2006.173.03:37:04.80#ibcon#about to read 3, iclass 38, count 0 2006.173.03:37:04.82#ibcon#read 3, iclass 38, count 0 2006.173.03:37:04.82#ibcon#about to read 4, iclass 38, count 0 2006.173.03:37:04.82#ibcon#read 4, iclass 38, count 0 2006.173.03:37:04.82#ibcon#about to read 5, iclass 38, count 0 2006.173.03:37:04.82#ibcon#read 5, iclass 38, count 0 2006.173.03:37:04.82#ibcon#about to read 6, iclass 38, count 0 2006.173.03:37:04.82#ibcon#read 6, iclass 38, count 0 2006.173.03:37:04.82#ibcon#end of sib2, iclass 38, count 0 2006.173.03:37:04.82#ibcon#*mode == 0, iclass 38, count 0 2006.173.03:37:04.82#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.03:37:04.82#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.03:37:04.82#ibcon#*before write, iclass 38, count 0 2006.173.03:37:04.82#ibcon#enter sib2, iclass 38, count 0 2006.173.03:37:04.82#ibcon#flushed, iclass 38, count 0 2006.173.03:37:04.82#ibcon#about to write, iclass 38, count 0 2006.173.03:37:04.82#ibcon#wrote, iclass 38, count 0 2006.173.03:37:04.82#ibcon#about to read 3, iclass 38, count 0 2006.173.03:37:04.86#ibcon#read 3, iclass 38, count 0 2006.173.03:37:04.86#ibcon#about to read 4, iclass 38, count 0 2006.173.03:37:04.86#ibcon#read 4, iclass 38, count 0 2006.173.03:37:04.86#ibcon#about to read 5, iclass 38, count 0 2006.173.03:37:04.86#ibcon#read 5, iclass 38, count 0 2006.173.03:37:04.86#ibcon#about to read 6, iclass 38, count 0 2006.173.03:37:04.86#ibcon#read 6, iclass 38, count 0 2006.173.03:37:04.86#ibcon#end of sib2, iclass 38, count 0 2006.173.03:37:04.86#ibcon#*after write, iclass 38, count 0 2006.173.03:37:04.86#ibcon#*before return 0, iclass 38, count 0 2006.173.03:37:04.86#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.03:37:04.86#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.03:37:04.86#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.03:37:04.86#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.03:37:04.86$vck44/va=5,4 2006.173.03:37:04.86#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.03:37:04.86#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.03:37:04.86#ibcon#ireg 11 cls_cnt 2 2006.173.03:37:04.86#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.03:37:04.92#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.03:37:04.92#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.03:37:04.92#ibcon#enter wrdev, iclass 40, count 2 2006.173.03:37:04.92#ibcon#first serial, iclass 40, count 2 2006.173.03:37:04.92#ibcon#enter sib2, iclass 40, count 2 2006.173.03:37:04.92#ibcon#flushed, iclass 40, count 2 2006.173.03:37:04.92#ibcon#about to write, iclass 40, count 2 2006.173.03:37:04.92#ibcon#wrote, iclass 40, count 2 2006.173.03:37:04.92#ibcon#about to read 3, iclass 40, count 2 2006.173.03:37:04.94#ibcon#read 3, iclass 40, count 2 2006.173.03:37:04.94#ibcon#about to read 4, iclass 40, count 2 2006.173.03:37:04.94#ibcon#read 4, iclass 40, count 2 2006.173.03:37:04.94#ibcon#about to read 5, iclass 40, count 2 2006.173.03:37:04.94#ibcon#read 5, iclass 40, count 2 2006.173.03:37:04.94#ibcon#about to read 6, iclass 40, count 2 2006.173.03:37:04.94#ibcon#read 6, iclass 40, count 2 2006.173.03:37:04.94#ibcon#end of sib2, iclass 40, count 2 2006.173.03:37:04.94#ibcon#*mode == 0, iclass 40, count 2 2006.173.03:37:04.94#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.03:37:04.94#ibcon#[25=AT05-04\r\n] 2006.173.03:37:04.94#ibcon#*before write, iclass 40, count 2 2006.173.03:37:04.94#ibcon#enter sib2, iclass 40, count 2 2006.173.03:37:04.94#ibcon#flushed, iclass 40, count 2 2006.173.03:37:04.94#ibcon#about to write, iclass 40, count 2 2006.173.03:37:04.94#ibcon#wrote, iclass 40, count 2 2006.173.03:37:04.94#ibcon#about to read 3, iclass 40, count 2 2006.173.03:37:04.97#ibcon#read 3, iclass 40, count 2 2006.173.03:37:04.97#ibcon#about to read 4, iclass 40, count 2 2006.173.03:37:04.97#ibcon#read 4, iclass 40, count 2 2006.173.03:37:04.97#ibcon#about to read 5, iclass 40, count 2 2006.173.03:37:04.97#ibcon#read 5, iclass 40, count 2 2006.173.03:37:04.97#ibcon#about to read 6, iclass 40, count 2 2006.173.03:37:04.97#ibcon#read 6, iclass 40, count 2 2006.173.03:37:04.97#ibcon#end of sib2, iclass 40, count 2 2006.173.03:37:04.97#ibcon#*after write, iclass 40, count 2 2006.173.03:37:04.97#ibcon#*before return 0, iclass 40, count 2 2006.173.03:37:04.97#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.03:37:04.97#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.03:37:04.97#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.03:37:04.97#ibcon#ireg 7 cls_cnt 0 2006.173.03:37:04.97#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.03:37:05.09#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.03:37:05.09#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.03:37:05.09#ibcon#enter wrdev, iclass 40, count 0 2006.173.03:37:05.09#ibcon#first serial, iclass 40, count 0 2006.173.03:37:05.09#ibcon#enter sib2, iclass 40, count 0 2006.173.03:37:05.09#ibcon#flushed, iclass 40, count 0 2006.173.03:37:05.09#ibcon#about to write, iclass 40, count 0 2006.173.03:37:05.09#ibcon#wrote, iclass 40, count 0 2006.173.03:37:05.09#ibcon#about to read 3, iclass 40, count 0 2006.173.03:37:05.11#ibcon#read 3, iclass 40, count 0 2006.173.03:37:05.11#ibcon#about to read 4, iclass 40, count 0 2006.173.03:37:05.11#ibcon#read 4, iclass 40, count 0 2006.173.03:37:05.11#ibcon#about to read 5, iclass 40, count 0 2006.173.03:37:05.11#ibcon#read 5, iclass 40, count 0 2006.173.03:37:05.11#ibcon#about to read 6, iclass 40, count 0 2006.173.03:37:05.11#ibcon#read 6, iclass 40, count 0 2006.173.03:37:05.11#ibcon#end of sib2, iclass 40, count 0 2006.173.03:37:05.11#ibcon#*mode == 0, iclass 40, count 0 2006.173.03:37:05.11#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.03:37:05.11#ibcon#[25=USB\r\n] 2006.173.03:37:05.11#ibcon#*before write, iclass 40, count 0 2006.173.03:37:05.11#ibcon#enter sib2, iclass 40, count 0 2006.173.03:37:05.11#ibcon#flushed, iclass 40, count 0 2006.173.03:37:05.11#ibcon#about to write, iclass 40, count 0 2006.173.03:37:05.11#ibcon#wrote, iclass 40, count 0 2006.173.03:37:05.11#ibcon#about to read 3, iclass 40, count 0 2006.173.03:37:05.14#ibcon#read 3, iclass 40, count 0 2006.173.03:37:05.14#ibcon#about to read 4, iclass 40, count 0 2006.173.03:37:05.14#ibcon#read 4, iclass 40, count 0 2006.173.03:37:05.14#ibcon#about to read 5, iclass 40, count 0 2006.173.03:37:05.14#ibcon#read 5, iclass 40, count 0 2006.173.03:37:05.14#ibcon#about to read 6, iclass 40, count 0 2006.173.03:37:05.14#ibcon#read 6, iclass 40, count 0 2006.173.03:37:05.14#ibcon#end of sib2, iclass 40, count 0 2006.173.03:37:05.14#ibcon#*after write, iclass 40, count 0 2006.173.03:37:05.14#ibcon#*before return 0, iclass 40, count 0 2006.173.03:37:05.14#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.03:37:05.14#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.03:37:05.14#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.03:37:05.14#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.03:37:05.14$vck44/valo=6,814.99 2006.173.03:37:05.14#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.03:37:05.14#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.03:37:05.14#ibcon#ireg 17 cls_cnt 0 2006.173.03:37:05.14#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.03:37:05.14#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.03:37:05.14#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.03:37:05.14#ibcon#enter wrdev, iclass 4, count 0 2006.173.03:37:05.14#ibcon#first serial, iclass 4, count 0 2006.173.03:37:05.14#ibcon#enter sib2, iclass 4, count 0 2006.173.03:37:05.14#ibcon#flushed, iclass 4, count 0 2006.173.03:37:05.14#ibcon#about to write, iclass 4, count 0 2006.173.03:37:05.14#ibcon#wrote, iclass 4, count 0 2006.173.03:37:05.14#ibcon#about to read 3, iclass 4, count 0 2006.173.03:37:05.16#ibcon#read 3, iclass 4, count 0 2006.173.03:37:05.16#ibcon#about to read 4, iclass 4, count 0 2006.173.03:37:05.16#ibcon#read 4, iclass 4, count 0 2006.173.03:37:05.16#ibcon#about to read 5, iclass 4, count 0 2006.173.03:37:05.16#ibcon#read 5, iclass 4, count 0 2006.173.03:37:05.16#ibcon#about to read 6, iclass 4, count 0 2006.173.03:37:05.16#ibcon#read 6, iclass 4, count 0 2006.173.03:37:05.16#ibcon#end of sib2, iclass 4, count 0 2006.173.03:37:05.16#ibcon#*mode == 0, iclass 4, count 0 2006.173.03:37:05.16#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.03:37:05.16#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.03:37:05.16#ibcon#*before write, iclass 4, count 0 2006.173.03:37:05.16#ibcon#enter sib2, iclass 4, count 0 2006.173.03:37:05.16#ibcon#flushed, iclass 4, count 0 2006.173.03:37:05.16#ibcon#about to write, iclass 4, count 0 2006.173.03:37:05.16#ibcon#wrote, iclass 4, count 0 2006.173.03:37:05.16#ibcon#about to read 3, iclass 4, count 0 2006.173.03:37:05.20#ibcon#read 3, iclass 4, count 0 2006.173.03:37:05.20#ibcon#about to read 4, iclass 4, count 0 2006.173.03:37:05.20#ibcon#read 4, iclass 4, count 0 2006.173.03:37:05.20#ibcon#about to read 5, iclass 4, count 0 2006.173.03:37:05.20#ibcon#read 5, iclass 4, count 0 2006.173.03:37:05.20#ibcon#about to read 6, iclass 4, count 0 2006.173.03:37:05.20#ibcon#read 6, iclass 4, count 0 2006.173.03:37:05.20#ibcon#end of sib2, iclass 4, count 0 2006.173.03:37:05.20#ibcon#*after write, iclass 4, count 0 2006.173.03:37:05.20#ibcon#*before return 0, iclass 4, count 0 2006.173.03:37:05.20#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.03:37:05.20#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.03:37:05.20#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.03:37:05.20#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.03:37:05.20$vck44/va=6,3 2006.173.03:37:05.20#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.03:37:05.20#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.03:37:05.20#ibcon#ireg 11 cls_cnt 2 2006.173.03:37:05.20#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.03:37:05.26#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.03:37:05.26#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.03:37:05.26#ibcon#enter wrdev, iclass 6, count 2 2006.173.03:37:05.26#ibcon#first serial, iclass 6, count 2 2006.173.03:37:05.26#ibcon#enter sib2, iclass 6, count 2 2006.173.03:37:05.26#ibcon#flushed, iclass 6, count 2 2006.173.03:37:05.26#ibcon#about to write, iclass 6, count 2 2006.173.03:37:05.26#ibcon#wrote, iclass 6, count 2 2006.173.03:37:05.26#ibcon#about to read 3, iclass 6, count 2 2006.173.03:37:05.28#ibcon#read 3, iclass 6, count 2 2006.173.03:37:05.28#ibcon#about to read 4, iclass 6, count 2 2006.173.03:37:05.28#ibcon#read 4, iclass 6, count 2 2006.173.03:37:05.28#ibcon#about to read 5, iclass 6, count 2 2006.173.03:37:05.28#ibcon#read 5, iclass 6, count 2 2006.173.03:37:05.28#ibcon#about to read 6, iclass 6, count 2 2006.173.03:37:05.28#ibcon#read 6, iclass 6, count 2 2006.173.03:37:05.28#ibcon#end of sib2, iclass 6, count 2 2006.173.03:37:05.28#ibcon#*mode == 0, iclass 6, count 2 2006.173.03:37:05.28#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.03:37:05.28#ibcon#[25=AT06-03\r\n] 2006.173.03:37:05.28#ibcon#*before write, iclass 6, count 2 2006.173.03:37:05.28#ibcon#enter sib2, iclass 6, count 2 2006.173.03:37:05.28#ibcon#flushed, iclass 6, count 2 2006.173.03:37:05.28#ibcon#about to write, iclass 6, count 2 2006.173.03:37:05.28#ibcon#wrote, iclass 6, count 2 2006.173.03:37:05.28#ibcon#about to read 3, iclass 6, count 2 2006.173.03:37:05.31#ibcon#read 3, iclass 6, count 2 2006.173.03:37:05.31#ibcon#about to read 4, iclass 6, count 2 2006.173.03:37:05.31#ibcon#read 4, iclass 6, count 2 2006.173.03:37:05.31#ibcon#about to read 5, iclass 6, count 2 2006.173.03:37:05.31#ibcon#read 5, iclass 6, count 2 2006.173.03:37:05.31#ibcon#about to read 6, iclass 6, count 2 2006.173.03:37:05.31#ibcon#read 6, iclass 6, count 2 2006.173.03:37:05.31#ibcon#end of sib2, iclass 6, count 2 2006.173.03:37:05.31#ibcon#*after write, iclass 6, count 2 2006.173.03:37:05.31#ibcon#*before return 0, iclass 6, count 2 2006.173.03:37:05.31#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.03:37:05.31#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.03:37:05.31#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.03:37:05.31#ibcon#ireg 7 cls_cnt 0 2006.173.03:37:05.31#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.03:37:05.43#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.03:37:05.43#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.03:37:05.43#ibcon#enter wrdev, iclass 6, count 0 2006.173.03:37:05.43#ibcon#first serial, iclass 6, count 0 2006.173.03:37:05.43#ibcon#enter sib2, iclass 6, count 0 2006.173.03:37:05.43#ibcon#flushed, iclass 6, count 0 2006.173.03:37:05.43#ibcon#about to write, iclass 6, count 0 2006.173.03:37:05.43#ibcon#wrote, iclass 6, count 0 2006.173.03:37:05.43#ibcon#about to read 3, iclass 6, count 0 2006.173.03:37:05.45#ibcon#read 3, iclass 6, count 0 2006.173.03:37:05.45#ibcon#about to read 4, iclass 6, count 0 2006.173.03:37:05.45#ibcon#read 4, iclass 6, count 0 2006.173.03:37:05.45#ibcon#about to read 5, iclass 6, count 0 2006.173.03:37:05.45#ibcon#read 5, iclass 6, count 0 2006.173.03:37:05.45#ibcon#about to read 6, iclass 6, count 0 2006.173.03:37:05.45#ibcon#read 6, iclass 6, count 0 2006.173.03:37:05.45#ibcon#end of sib2, iclass 6, count 0 2006.173.03:37:05.45#ibcon#*mode == 0, iclass 6, count 0 2006.173.03:37:05.45#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.03:37:05.45#ibcon#[25=USB\r\n] 2006.173.03:37:05.45#ibcon#*before write, iclass 6, count 0 2006.173.03:37:05.45#ibcon#enter sib2, iclass 6, count 0 2006.173.03:37:05.45#ibcon#flushed, iclass 6, count 0 2006.173.03:37:05.45#ibcon#about to write, iclass 6, count 0 2006.173.03:37:05.45#ibcon#wrote, iclass 6, count 0 2006.173.03:37:05.45#ibcon#about to read 3, iclass 6, count 0 2006.173.03:37:05.48#ibcon#read 3, iclass 6, count 0 2006.173.03:37:05.48#ibcon#about to read 4, iclass 6, count 0 2006.173.03:37:05.48#ibcon#read 4, iclass 6, count 0 2006.173.03:37:05.48#ibcon#about to read 5, iclass 6, count 0 2006.173.03:37:05.48#ibcon#read 5, iclass 6, count 0 2006.173.03:37:05.48#ibcon#about to read 6, iclass 6, count 0 2006.173.03:37:05.48#ibcon#read 6, iclass 6, count 0 2006.173.03:37:05.48#ibcon#end of sib2, iclass 6, count 0 2006.173.03:37:05.48#ibcon#*after write, iclass 6, count 0 2006.173.03:37:05.48#ibcon#*before return 0, iclass 6, count 0 2006.173.03:37:05.48#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.03:37:05.48#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.03:37:05.48#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.03:37:05.48#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.03:37:05.48$vck44/valo=7,864.99 2006.173.03:37:05.48#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.03:37:05.48#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.03:37:05.48#ibcon#ireg 17 cls_cnt 0 2006.173.03:37:05.48#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.03:37:05.48#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.03:37:05.48#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.03:37:05.48#ibcon#enter wrdev, iclass 10, count 0 2006.173.03:37:05.48#ibcon#first serial, iclass 10, count 0 2006.173.03:37:05.48#ibcon#enter sib2, iclass 10, count 0 2006.173.03:37:05.48#ibcon#flushed, iclass 10, count 0 2006.173.03:37:05.48#ibcon#about to write, iclass 10, count 0 2006.173.03:37:05.48#ibcon#wrote, iclass 10, count 0 2006.173.03:37:05.48#ibcon#about to read 3, iclass 10, count 0 2006.173.03:37:05.50#ibcon#read 3, iclass 10, count 0 2006.173.03:37:05.50#ibcon#about to read 4, iclass 10, count 0 2006.173.03:37:05.50#ibcon#read 4, iclass 10, count 0 2006.173.03:37:05.50#ibcon#about to read 5, iclass 10, count 0 2006.173.03:37:05.50#ibcon#read 5, iclass 10, count 0 2006.173.03:37:05.50#ibcon#about to read 6, iclass 10, count 0 2006.173.03:37:05.50#ibcon#read 6, iclass 10, count 0 2006.173.03:37:05.50#ibcon#end of sib2, iclass 10, count 0 2006.173.03:37:05.50#ibcon#*mode == 0, iclass 10, count 0 2006.173.03:37:05.50#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.03:37:05.50#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.03:37:05.50#ibcon#*before write, iclass 10, count 0 2006.173.03:37:05.50#ibcon#enter sib2, iclass 10, count 0 2006.173.03:37:05.50#ibcon#flushed, iclass 10, count 0 2006.173.03:37:05.50#ibcon#about to write, iclass 10, count 0 2006.173.03:37:05.50#ibcon#wrote, iclass 10, count 0 2006.173.03:37:05.50#ibcon#about to read 3, iclass 10, count 0 2006.173.03:37:05.54#ibcon#read 3, iclass 10, count 0 2006.173.03:37:05.54#ibcon#about to read 4, iclass 10, count 0 2006.173.03:37:05.54#ibcon#read 4, iclass 10, count 0 2006.173.03:37:05.54#ibcon#about to read 5, iclass 10, count 0 2006.173.03:37:05.54#ibcon#read 5, iclass 10, count 0 2006.173.03:37:05.54#ibcon#about to read 6, iclass 10, count 0 2006.173.03:37:05.54#ibcon#read 6, iclass 10, count 0 2006.173.03:37:05.54#ibcon#end of sib2, iclass 10, count 0 2006.173.03:37:05.54#ibcon#*after write, iclass 10, count 0 2006.173.03:37:05.54#ibcon#*before return 0, iclass 10, count 0 2006.173.03:37:05.54#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.03:37:05.54#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.03:37:05.54#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.03:37:05.54#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.03:37:05.54$vck44/va=7,4 2006.173.03:37:05.54#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.03:37:05.54#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.03:37:05.54#ibcon#ireg 11 cls_cnt 2 2006.173.03:37:05.54#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.03:37:05.60#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.03:37:05.60#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.03:37:05.60#ibcon#enter wrdev, iclass 12, count 2 2006.173.03:37:05.60#ibcon#first serial, iclass 12, count 2 2006.173.03:37:05.60#ibcon#enter sib2, iclass 12, count 2 2006.173.03:37:05.60#ibcon#flushed, iclass 12, count 2 2006.173.03:37:05.60#ibcon#about to write, iclass 12, count 2 2006.173.03:37:05.60#ibcon#wrote, iclass 12, count 2 2006.173.03:37:05.60#ibcon#about to read 3, iclass 12, count 2 2006.173.03:37:05.62#ibcon#read 3, iclass 12, count 2 2006.173.03:37:05.62#ibcon#about to read 4, iclass 12, count 2 2006.173.03:37:05.62#ibcon#read 4, iclass 12, count 2 2006.173.03:37:05.62#ibcon#about to read 5, iclass 12, count 2 2006.173.03:37:05.62#ibcon#read 5, iclass 12, count 2 2006.173.03:37:05.62#ibcon#about to read 6, iclass 12, count 2 2006.173.03:37:05.62#ibcon#read 6, iclass 12, count 2 2006.173.03:37:05.62#ibcon#end of sib2, iclass 12, count 2 2006.173.03:37:05.62#ibcon#*mode == 0, iclass 12, count 2 2006.173.03:37:05.62#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.03:37:05.62#ibcon#[25=AT07-04\r\n] 2006.173.03:37:05.62#ibcon#*before write, iclass 12, count 2 2006.173.03:37:05.62#ibcon#enter sib2, iclass 12, count 2 2006.173.03:37:05.62#ibcon#flushed, iclass 12, count 2 2006.173.03:37:05.62#ibcon#about to write, iclass 12, count 2 2006.173.03:37:05.62#ibcon#wrote, iclass 12, count 2 2006.173.03:37:05.62#ibcon#about to read 3, iclass 12, count 2 2006.173.03:37:05.65#ibcon#read 3, iclass 12, count 2 2006.173.03:37:05.65#ibcon#about to read 4, iclass 12, count 2 2006.173.03:37:05.65#ibcon#read 4, iclass 12, count 2 2006.173.03:37:05.65#ibcon#about to read 5, iclass 12, count 2 2006.173.03:37:05.65#ibcon#read 5, iclass 12, count 2 2006.173.03:37:05.65#ibcon#about to read 6, iclass 12, count 2 2006.173.03:37:05.65#ibcon#read 6, iclass 12, count 2 2006.173.03:37:05.65#ibcon#end of sib2, iclass 12, count 2 2006.173.03:37:05.65#ibcon#*after write, iclass 12, count 2 2006.173.03:37:05.65#ibcon#*before return 0, iclass 12, count 2 2006.173.03:37:05.65#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.03:37:05.65#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.03:37:05.65#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.03:37:05.65#ibcon#ireg 7 cls_cnt 0 2006.173.03:37:05.65#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.03:37:05.77#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.03:37:05.77#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.03:37:05.77#ibcon#enter wrdev, iclass 12, count 0 2006.173.03:37:05.77#ibcon#first serial, iclass 12, count 0 2006.173.03:37:05.77#ibcon#enter sib2, iclass 12, count 0 2006.173.03:37:05.77#ibcon#flushed, iclass 12, count 0 2006.173.03:37:05.77#ibcon#about to write, iclass 12, count 0 2006.173.03:37:05.77#ibcon#wrote, iclass 12, count 0 2006.173.03:37:05.77#ibcon#about to read 3, iclass 12, count 0 2006.173.03:37:05.79#ibcon#read 3, iclass 12, count 0 2006.173.03:37:05.79#ibcon#about to read 4, iclass 12, count 0 2006.173.03:37:05.79#ibcon#read 4, iclass 12, count 0 2006.173.03:37:05.79#ibcon#about to read 5, iclass 12, count 0 2006.173.03:37:05.79#ibcon#read 5, iclass 12, count 0 2006.173.03:37:05.79#ibcon#about to read 6, iclass 12, count 0 2006.173.03:37:05.79#ibcon#read 6, iclass 12, count 0 2006.173.03:37:05.79#ibcon#end of sib2, iclass 12, count 0 2006.173.03:37:05.79#ibcon#*mode == 0, iclass 12, count 0 2006.173.03:37:05.79#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.03:37:05.79#ibcon#[25=USB\r\n] 2006.173.03:37:05.79#ibcon#*before write, iclass 12, count 0 2006.173.03:37:05.79#ibcon#enter sib2, iclass 12, count 0 2006.173.03:37:05.79#ibcon#flushed, iclass 12, count 0 2006.173.03:37:05.79#ibcon#about to write, iclass 12, count 0 2006.173.03:37:05.79#ibcon#wrote, iclass 12, count 0 2006.173.03:37:05.79#ibcon#about to read 3, iclass 12, count 0 2006.173.03:37:05.82#abcon#<5=/14 1.1 2.7 22.68 831006.3\r\n> 2006.173.03:37:05.82#ibcon#read 3, iclass 12, count 0 2006.173.03:37:05.82#ibcon#about to read 4, iclass 12, count 0 2006.173.03:37:05.82#ibcon#read 4, iclass 12, count 0 2006.173.03:37:05.82#ibcon#about to read 5, iclass 12, count 0 2006.173.03:37:05.82#ibcon#read 5, iclass 12, count 0 2006.173.03:37:05.82#ibcon#about to read 6, iclass 12, count 0 2006.173.03:37:05.82#ibcon#read 6, iclass 12, count 0 2006.173.03:37:05.82#ibcon#end of sib2, iclass 12, count 0 2006.173.03:37:05.82#ibcon#*after write, iclass 12, count 0 2006.173.03:37:05.82#ibcon#*before return 0, iclass 12, count 0 2006.173.03:37:05.82#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.03:37:05.82#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.03:37:05.82#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.03:37:05.82#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.03:37:05.82$vck44/valo=8,884.99 2006.173.03:37:05.82#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.03:37:05.82#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.03:37:05.82#ibcon#ireg 17 cls_cnt 0 2006.173.03:37:05.82#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.03:37:05.82#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.03:37:05.82#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.03:37:05.82#ibcon#enter wrdev, iclass 17, count 0 2006.173.03:37:05.82#ibcon#first serial, iclass 17, count 0 2006.173.03:37:05.82#ibcon#enter sib2, iclass 17, count 0 2006.173.03:37:05.82#ibcon#flushed, iclass 17, count 0 2006.173.03:37:05.82#ibcon#about to write, iclass 17, count 0 2006.173.03:37:05.82#ibcon#wrote, iclass 17, count 0 2006.173.03:37:05.82#ibcon#about to read 3, iclass 17, count 0 2006.173.03:37:05.84#ibcon#read 3, iclass 17, count 0 2006.173.03:37:05.84#ibcon#about to read 4, iclass 17, count 0 2006.173.03:37:05.84#ibcon#read 4, iclass 17, count 0 2006.173.03:37:05.84#ibcon#about to read 5, iclass 17, count 0 2006.173.03:37:05.84#ibcon#read 5, iclass 17, count 0 2006.173.03:37:05.84#ibcon#about to read 6, iclass 17, count 0 2006.173.03:37:05.84#ibcon#read 6, iclass 17, count 0 2006.173.03:37:05.84#ibcon#end of sib2, iclass 17, count 0 2006.173.03:37:05.84#ibcon#*mode == 0, iclass 17, count 0 2006.173.03:37:05.84#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.03:37:05.84#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.03:37:05.84#ibcon#*before write, iclass 17, count 0 2006.173.03:37:05.84#ibcon#enter sib2, iclass 17, count 0 2006.173.03:37:05.84#ibcon#flushed, iclass 17, count 0 2006.173.03:37:05.84#ibcon#about to write, iclass 17, count 0 2006.173.03:37:05.84#ibcon#wrote, iclass 17, count 0 2006.173.03:37:05.84#ibcon#about to read 3, iclass 17, count 0 2006.173.03:37:05.84#abcon#{5=INTERFACE CLEAR} 2006.173.03:37:05.88#ibcon#read 3, iclass 17, count 0 2006.173.03:37:05.88#ibcon#about to read 4, iclass 17, count 0 2006.173.03:37:05.88#ibcon#read 4, iclass 17, count 0 2006.173.03:37:05.88#ibcon#about to read 5, iclass 17, count 0 2006.173.03:37:05.88#ibcon#read 5, iclass 17, count 0 2006.173.03:37:05.88#ibcon#about to read 6, iclass 17, count 0 2006.173.03:37:05.88#ibcon#read 6, iclass 17, count 0 2006.173.03:37:05.88#ibcon#end of sib2, iclass 17, count 0 2006.173.03:37:05.88#ibcon#*after write, iclass 17, count 0 2006.173.03:37:05.88#ibcon#*before return 0, iclass 17, count 0 2006.173.03:37:05.88#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.03:37:05.88#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.03:37:05.88#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.03:37:05.88#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.03:37:05.88$vck44/va=8,4 2006.173.03:37:05.88#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.03:37:05.88#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.03:37:05.88#ibcon#ireg 11 cls_cnt 2 2006.173.03:37:05.88#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.03:37:05.90#abcon#[5=S1D000X0/0*\r\n] 2006.173.03:37:05.94#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.03:37:05.94#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.03:37:05.94#ibcon#enter wrdev, iclass 19, count 2 2006.173.03:37:05.94#ibcon#first serial, iclass 19, count 2 2006.173.03:37:05.94#ibcon#enter sib2, iclass 19, count 2 2006.173.03:37:05.94#ibcon#flushed, iclass 19, count 2 2006.173.03:37:05.94#ibcon#about to write, iclass 19, count 2 2006.173.03:37:05.94#ibcon#wrote, iclass 19, count 2 2006.173.03:37:05.94#ibcon#about to read 3, iclass 19, count 2 2006.173.03:37:05.96#ibcon#read 3, iclass 19, count 2 2006.173.03:37:05.96#ibcon#about to read 4, iclass 19, count 2 2006.173.03:37:05.96#ibcon#read 4, iclass 19, count 2 2006.173.03:37:05.96#ibcon#about to read 5, iclass 19, count 2 2006.173.03:37:05.96#ibcon#read 5, iclass 19, count 2 2006.173.03:37:05.96#ibcon#about to read 6, iclass 19, count 2 2006.173.03:37:05.96#ibcon#read 6, iclass 19, count 2 2006.173.03:37:05.96#ibcon#end of sib2, iclass 19, count 2 2006.173.03:37:05.96#ibcon#*mode == 0, iclass 19, count 2 2006.173.03:37:05.96#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.03:37:05.96#ibcon#[25=AT08-04\r\n] 2006.173.03:37:05.96#ibcon#*before write, iclass 19, count 2 2006.173.03:37:05.96#ibcon#enter sib2, iclass 19, count 2 2006.173.03:37:05.96#ibcon#flushed, iclass 19, count 2 2006.173.03:37:05.96#ibcon#about to write, iclass 19, count 2 2006.173.03:37:05.96#ibcon#wrote, iclass 19, count 2 2006.173.03:37:05.96#ibcon#about to read 3, iclass 19, count 2 2006.173.03:37:05.99#ibcon#read 3, iclass 19, count 2 2006.173.03:37:05.99#ibcon#about to read 4, iclass 19, count 2 2006.173.03:37:05.99#ibcon#read 4, iclass 19, count 2 2006.173.03:37:05.99#ibcon#about to read 5, iclass 19, count 2 2006.173.03:37:05.99#ibcon#read 5, iclass 19, count 2 2006.173.03:37:05.99#ibcon#about to read 6, iclass 19, count 2 2006.173.03:37:05.99#ibcon#read 6, iclass 19, count 2 2006.173.03:37:05.99#ibcon#end of sib2, iclass 19, count 2 2006.173.03:37:05.99#ibcon#*after write, iclass 19, count 2 2006.173.03:37:05.99#ibcon#*before return 0, iclass 19, count 2 2006.173.03:37:05.99#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.03:37:05.99#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.03:37:05.99#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.03:37:05.99#ibcon#ireg 7 cls_cnt 0 2006.173.03:37:05.99#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.03:37:06.11#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.03:37:06.11#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.03:37:06.11#ibcon#enter wrdev, iclass 19, count 0 2006.173.03:37:06.11#ibcon#first serial, iclass 19, count 0 2006.173.03:37:06.11#ibcon#enter sib2, iclass 19, count 0 2006.173.03:37:06.11#ibcon#flushed, iclass 19, count 0 2006.173.03:37:06.11#ibcon#about to write, iclass 19, count 0 2006.173.03:37:06.11#ibcon#wrote, iclass 19, count 0 2006.173.03:37:06.11#ibcon#about to read 3, iclass 19, count 0 2006.173.03:37:06.13#ibcon#read 3, iclass 19, count 0 2006.173.03:37:06.13#ibcon#about to read 4, iclass 19, count 0 2006.173.03:37:06.13#ibcon#read 4, iclass 19, count 0 2006.173.03:37:06.13#ibcon#about to read 5, iclass 19, count 0 2006.173.03:37:06.13#ibcon#read 5, iclass 19, count 0 2006.173.03:37:06.13#ibcon#about to read 6, iclass 19, count 0 2006.173.03:37:06.13#ibcon#read 6, iclass 19, count 0 2006.173.03:37:06.13#ibcon#end of sib2, iclass 19, count 0 2006.173.03:37:06.13#ibcon#*mode == 0, iclass 19, count 0 2006.173.03:37:06.13#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.03:37:06.13#ibcon#[25=USB\r\n] 2006.173.03:37:06.13#ibcon#*before write, iclass 19, count 0 2006.173.03:37:06.13#ibcon#enter sib2, iclass 19, count 0 2006.173.03:37:06.13#ibcon#flushed, iclass 19, count 0 2006.173.03:37:06.13#ibcon#about to write, iclass 19, count 0 2006.173.03:37:06.13#ibcon#wrote, iclass 19, count 0 2006.173.03:37:06.13#ibcon#about to read 3, iclass 19, count 0 2006.173.03:37:06.16#ibcon#read 3, iclass 19, count 0 2006.173.03:37:06.16#ibcon#about to read 4, iclass 19, count 0 2006.173.03:37:06.16#ibcon#read 4, iclass 19, count 0 2006.173.03:37:06.16#ibcon#about to read 5, iclass 19, count 0 2006.173.03:37:06.16#ibcon#read 5, iclass 19, count 0 2006.173.03:37:06.16#ibcon#about to read 6, iclass 19, count 0 2006.173.03:37:06.16#ibcon#read 6, iclass 19, count 0 2006.173.03:37:06.16#ibcon#end of sib2, iclass 19, count 0 2006.173.03:37:06.16#ibcon#*after write, iclass 19, count 0 2006.173.03:37:06.16#ibcon#*before return 0, iclass 19, count 0 2006.173.03:37:06.16#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.03:37:06.16#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.03:37:06.16#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.03:37:06.16#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.03:37:06.16$vck44/vblo=1,629.99 2006.173.03:37:06.16#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.03:37:06.16#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.03:37:06.16#ibcon#ireg 17 cls_cnt 0 2006.173.03:37:06.16#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.03:37:06.16#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.03:37:06.16#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.03:37:06.16#ibcon#enter wrdev, iclass 22, count 0 2006.173.03:37:06.16#ibcon#first serial, iclass 22, count 0 2006.173.03:37:06.16#ibcon#enter sib2, iclass 22, count 0 2006.173.03:37:06.16#ibcon#flushed, iclass 22, count 0 2006.173.03:37:06.16#ibcon#about to write, iclass 22, count 0 2006.173.03:37:06.16#ibcon#wrote, iclass 22, count 0 2006.173.03:37:06.16#ibcon#about to read 3, iclass 22, count 0 2006.173.03:37:06.18#ibcon#read 3, iclass 22, count 0 2006.173.03:37:06.18#ibcon#about to read 4, iclass 22, count 0 2006.173.03:37:06.18#ibcon#read 4, iclass 22, count 0 2006.173.03:37:06.18#ibcon#about to read 5, iclass 22, count 0 2006.173.03:37:06.18#ibcon#read 5, iclass 22, count 0 2006.173.03:37:06.18#ibcon#about to read 6, iclass 22, count 0 2006.173.03:37:06.18#ibcon#read 6, iclass 22, count 0 2006.173.03:37:06.18#ibcon#end of sib2, iclass 22, count 0 2006.173.03:37:06.18#ibcon#*mode == 0, iclass 22, count 0 2006.173.03:37:06.18#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.03:37:06.18#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.03:37:06.18#ibcon#*before write, iclass 22, count 0 2006.173.03:37:06.18#ibcon#enter sib2, iclass 22, count 0 2006.173.03:37:06.18#ibcon#flushed, iclass 22, count 0 2006.173.03:37:06.18#ibcon#about to write, iclass 22, count 0 2006.173.03:37:06.18#ibcon#wrote, iclass 22, count 0 2006.173.03:37:06.18#ibcon#about to read 3, iclass 22, count 0 2006.173.03:37:06.22#ibcon#read 3, iclass 22, count 0 2006.173.03:37:06.22#ibcon#about to read 4, iclass 22, count 0 2006.173.03:37:06.22#ibcon#read 4, iclass 22, count 0 2006.173.03:37:06.22#ibcon#about to read 5, iclass 22, count 0 2006.173.03:37:06.22#ibcon#read 5, iclass 22, count 0 2006.173.03:37:06.22#ibcon#about to read 6, iclass 22, count 0 2006.173.03:37:06.22#ibcon#read 6, iclass 22, count 0 2006.173.03:37:06.22#ibcon#end of sib2, iclass 22, count 0 2006.173.03:37:06.22#ibcon#*after write, iclass 22, count 0 2006.173.03:37:06.22#ibcon#*before return 0, iclass 22, count 0 2006.173.03:37:06.22#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.03:37:06.22#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.03:37:06.22#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.03:37:06.22#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.03:37:06.22$vck44/vb=1,4 2006.173.03:37:06.22#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.03:37:06.22#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.03:37:06.22#ibcon#ireg 11 cls_cnt 2 2006.173.03:37:06.22#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.03:37:06.22#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.03:37:06.22#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.03:37:06.22#ibcon#enter wrdev, iclass 24, count 2 2006.173.03:37:06.22#ibcon#first serial, iclass 24, count 2 2006.173.03:37:06.22#ibcon#enter sib2, iclass 24, count 2 2006.173.03:37:06.22#ibcon#flushed, iclass 24, count 2 2006.173.03:37:06.22#ibcon#about to write, iclass 24, count 2 2006.173.03:37:06.22#ibcon#wrote, iclass 24, count 2 2006.173.03:37:06.22#ibcon#about to read 3, iclass 24, count 2 2006.173.03:37:06.24#ibcon#read 3, iclass 24, count 2 2006.173.03:37:06.24#ibcon#about to read 4, iclass 24, count 2 2006.173.03:37:06.24#ibcon#read 4, iclass 24, count 2 2006.173.03:37:06.24#ibcon#about to read 5, iclass 24, count 2 2006.173.03:37:06.24#ibcon#read 5, iclass 24, count 2 2006.173.03:37:06.24#ibcon#about to read 6, iclass 24, count 2 2006.173.03:37:06.24#ibcon#read 6, iclass 24, count 2 2006.173.03:37:06.24#ibcon#end of sib2, iclass 24, count 2 2006.173.03:37:06.24#ibcon#*mode == 0, iclass 24, count 2 2006.173.03:37:06.24#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.03:37:06.24#ibcon#[27=AT01-04\r\n] 2006.173.03:37:06.24#ibcon#*before write, iclass 24, count 2 2006.173.03:37:06.24#ibcon#enter sib2, iclass 24, count 2 2006.173.03:37:06.24#ibcon#flushed, iclass 24, count 2 2006.173.03:37:06.24#ibcon#about to write, iclass 24, count 2 2006.173.03:37:06.24#ibcon#wrote, iclass 24, count 2 2006.173.03:37:06.24#ibcon#about to read 3, iclass 24, count 2 2006.173.03:37:06.27#ibcon#read 3, iclass 24, count 2 2006.173.03:37:06.27#ibcon#about to read 4, iclass 24, count 2 2006.173.03:37:06.27#ibcon#read 4, iclass 24, count 2 2006.173.03:37:06.27#ibcon#about to read 5, iclass 24, count 2 2006.173.03:37:06.27#ibcon#read 5, iclass 24, count 2 2006.173.03:37:06.27#ibcon#about to read 6, iclass 24, count 2 2006.173.03:37:06.27#ibcon#read 6, iclass 24, count 2 2006.173.03:37:06.27#ibcon#end of sib2, iclass 24, count 2 2006.173.03:37:06.27#ibcon#*after write, iclass 24, count 2 2006.173.03:37:06.27#ibcon#*before return 0, iclass 24, count 2 2006.173.03:37:06.27#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.03:37:06.27#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.03:37:06.27#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.03:37:06.27#ibcon#ireg 7 cls_cnt 0 2006.173.03:37:06.27#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.03:37:06.39#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.03:37:06.39#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.03:37:06.39#ibcon#enter wrdev, iclass 24, count 0 2006.173.03:37:06.39#ibcon#first serial, iclass 24, count 0 2006.173.03:37:06.39#ibcon#enter sib2, iclass 24, count 0 2006.173.03:37:06.39#ibcon#flushed, iclass 24, count 0 2006.173.03:37:06.39#ibcon#about to write, iclass 24, count 0 2006.173.03:37:06.39#ibcon#wrote, iclass 24, count 0 2006.173.03:37:06.39#ibcon#about to read 3, iclass 24, count 0 2006.173.03:37:06.41#ibcon#read 3, iclass 24, count 0 2006.173.03:37:06.41#ibcon#about to read 4, iclass 24, count 0 2006.173.03:37:06.41#ibcon#read 4, iclass 24, count 0 2006.173.03:37:06.41#ibcon#about to read 5, iclass 24, count 0 2006.173.03:37:06.41#ibcon#read 5, iclass 24, count 0 2006.173.03:37:06.41#ibcon#about to read 6, iclass 24, count 0 2006.173.03:37:06.41#ibcon#read 6, iclass 24, count 0 2006.173.03:37:06.41#ibcon#end of sib2, iclass 24, count 0 2006.173.03:37:06.41#ibcon#*mode == 0, iclass 24, count 0 2006.173.03:37:06.41#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.03:37:06.41#ibcon#[27=USB\r\n] 2006.173.03:37:06.41#ibcon#*before write, iclass 24, count 0 2006.173.03:37:06.41#ibcon#enter sib2, iclass 24, count 0 2006.173.03:37:06.41#ibcon#flushed, iclass 24, count 0 2006.173.03:37:06.41#ibcon#about to write, iclass 24, count 0 2006.173.03:37:06.41#ibcon#wrote, iclass 24, count 0 2006.173.03:37:06.41#ibcon#about to read 3, iclass 24, count 0 2006.173.03:37:06.44#ibcon#read 3, iclass 24, count 0 2006.173.03:37:06.44#ibcon#about to read 4, iclass 24, count 0 2006.173.03:37:06.44#ibcon#read 4, iclass 24, count 0 2006.173.03:37:06.44#ibcon#about to read 5, iclass 24, count 0 2006.173.03:37:06.44#ibcon#read 5, iclass 24, count 0 2006.173.03:37:06.44#ibcon#about to read 6, iclass 24, count 0 2006.173.03:37:06.44#ibcon#read 6, iclass 24, count 0 2006.173.03:37:06.44#ibcon#end of sib2, iclass 24, count 0 2006.173.03:37:06.44#ibcon#*after write, iclass 24, count 0 2006.173.03:37:06.44#ibcon#*before return 0, iclass 24, count 0 2006.173.03:37:06.44#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.03:37:06.44#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.03:37:06.44#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.03:37:06.44#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.03:37:06.44$vck44/vblo=2,634.99 2006.173.03:37:06.44#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.03:37:06.44#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.03:37:06.44#ibcon#ireg 17 cls_cnt 0 2006.173.03:37:06.44#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.03:37:06.44#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.03:37:06.44#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.03:37:06.44#ibcon#enter wrdev, iclass 26, count 0 2006.173.03:37:06.44#ibcon#first serial, iclass 26, count 0 2006.173.03:37:06.44#ibcon#enter sib2, iclass 26, count 0 2006.173.03:37:06.44#ibcon#flushed, iclass 26, count 0 2006.173.03:37:06.44#ibcon#about to write, iclass 26, count 0 2006.173.03:37:06.44#ibcon#wrote, iclass 26, count 0 2006.173.03:37:06.44#ibcon#about to read 3, iclass 26, count 0 2006.173.03:37:06.46#ibcon#read 3, iclass 26, count 0 2006.173.03:37:06.46#ibcon#about to read 4, iclass 26, count 0 2006.173.03:37:06.46#ibcon#read 4, iclass 26, count 0 2006.173.03:37:06.46#ibcon#about to read 5, iclass 26, count 0 2006.173.03:37:06.46#ibcon#read 5, iclass 26, count 0 2006.173.03:37:06.46#ibcon#about to read 6, iclass 26, count 0 2006.173.03:37:06.46#ibcon#read 6, iclass 26, count 0 2006.173.03:37:06.46#ibcon#end of sib2, iclass 26, count 0 2006.173.03:37:06.46#ibcon#*mode == 0, iclass 26, count 0 2006.173.03:37:06.46#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.03:37:06.46#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.03:37:06.46#ibcon#*before write, iclass 26, count 0 2006.173.03:37:06.46#ibcon#enter sib2, iclass 26, count 0 2006.173.03:37:06.46#ibcon#flushed, iclass 26, count 0 2006.173.03:37:06.46#ibcon#about to write, iclass 26, count 0 2006.173.03:37:06.46#ibcon#wrote, iclass 26, count 0 2006.173.03:37:06.46#ibcon#about to read 3, iclass 26, count 0 2006.173.03:37:06.50#ibcon#read 3, iclass 26, count 0 2006.173.03:37:06.50#ibcon#about to read 4, iclass 26, count 0 2006.173.03:37:06.50#ibcon#read 4, iclass 26, count 0 2006.173.03:37:06.50#ibcon#about to read 5, iclass 26, count 0 2006.173.03:37:06.50#ibcon#read 5, iclass 26, count 0 2006.173.03:37:06.50#ibcon#about to read 6, iclass 26, count 0 2006.173.03:37:06.50#ibcon#read 6, iclass 26, count 0 2006.173.03:37:06.50#ibcon#end of sib2, iclass 26, count 0 2006.173.03:37:06.50#ibcon#*after write, iclass 26, count 0 2006.173.03:37:06.50#ibcon#*before return 0, iclass 26, count 0 2006.173.03:37:06.50#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.03:37:06.50#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.03:37:06.50#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.03:37:06.50#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.03:37:06.50$vck44/vb=2,4 2006.173.03:37:06.50#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.03:37:06.50#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.03:37:06.50#ibcon#ireg 11 cls_cnt 2 2006.173.03:37:06.50#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.03:37:06.56#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.03:37:06.56#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.03:37:06.56#ibcon#enter wrdev, iclass 28, count 2 2006.173.03:37:06.56#ibcon#first serial, iclass 28, count 2 2006.173.03:37:06.56#ibcon#enter sib2, iclass 28, count 2 2006.173.03:37:06.56#ibcon#flushed, iclass 28, count 2 2006.173.03:37:06.56#ibcon#about to write, iclass 28, count 2 2006.173.03:37:06.56#ibcon#wrote, iclass 28, count 2 2006.173.03:37:06.56#ibcon#about to read 3, iclass 28, count 2 2006.173.03:37:06.58#ibcon#read 3, iclass 28, count 2 2006.173.03:37:06.58#ibcon#about to read 4, iclass 28, count 2 2006.173.03:37:06.58#ibcon#read 4, iclass 28, count 2 2006.173.03:37:06.58#ibcon#about to read 5, iclass 28, count 2 2006.173.03:37:06.58#ibcon#read 5, iclass 28, count 2 2006.173.03:37:06.58#ibcon#about to read 6, iclass 28, count 2 2006.173.03:37:06.58#ibcon#read 6, iclass 28, count 2 2006.173.03:37:06.58#ibcon#end of sib2, iclass 28, count 2 2006.173.03:37:06.58#ibcon#*mode == 0, iclass 28, count 2 2006.173.03:37:06.58#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.03:37:06.58#ibcon#[27=AT02-04\r\n] 2006.173.03:37:06.58#ibcon#*before write, iclass 28, count 2 2006.173.03:37:06.58#ibcon#enter sib2, iclass 28, count 2 2006.173.03:37:06.58#ibcon#flushed, iclass 28, count 2 2006.173.03:37:06.58#ibcon#about to write, iclass 28, count 2 2006.173.03:37:06.58#ibcon#wrote, iclass 28, count 2 2006.173.03:37:06.58#ibcon#about to read 3, iclass 28, count 2 2006.173.03:37:06.61#ibcon#read 3, iclass 28, count 2 2006.173.03:37:06.61#ibcon#about to read 4, iclass 28, count 2 2006.173.03:37:06.61#ibcon#read 4, iclass 28, count 2 2006.173.03:37:06.61#ibcon#about to read 5, iclass 28, count 2 2006.173.03:37:06.61#ibcon#read 5, iclass 28, count 2 2006.173.03:37:06.61#ibcon#about to read 6, iclass 28, count 2 2006.173.03:37:06.61#ibcon#read 6, iclass 28, count 2 2006.173.03:37:06.61#ibcon#end of sib2, iclass 28, count 2 2006.173.03:37:06.61#ibcon#*after write, iclass 28, count 2 2006.173.03:37:06.61#ibcon#*before return 0, iclass 28, count 2 2006.173.03:37:06.61#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.03:37:06.61#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.03:37:06.61#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.03:37:06.61#ibcon#ireg 7 cls_cnt 0 2006.173.03:37:06.61#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.03:37:06.73#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.03:37:06.73#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.03:37:06.73#ibcon#enter wrdev, iclass 28, count 0 2006.173.03:37:06.73#ibcon#first serial, iclass 28, count 0 2006.173.03:37:06.73#ibcon#enter sib2, iclass 28, count 0 2006.173.03:37:06.73#ibcon#flushed, iclass 28, count 0 2006.173.03:37:06.73#ibcon#about to write, iclass 28, count 0 2006.173.03:37:06.73#ibcon#wrote, iclass 28, count 0 2006.173.03:37:06.73#ibcon#about to read 3, iclass 28, count 0 2006.173.03:37:06.75#ibcon#read 3, iclass 28, count 0 2006.173.03:37:06.75#ibcon#about to read 4, iclass 28, count 0 2006.173.03:37:06.75#ibcon#read 4, iclass 28, count 0 2006.173.03:37:06.75#ibcon#about to read 5, iclass 28, count 0 2006.173.03:37:06.75#ibcon#read 5, iclass 28, count 0 2006.173.03:37:06.75#ibcon#about to read 6, iclass 28, count 0 2006.173.03:37:06.75#ibcon#read 6, iclass 28, count 0 2006.173.03:37:06.75#ibcon#end of sib2, iclass 28, count 0 2006.173.03:37:06.75#ibcon#*mode == 0, iclass 28, count 0 2006.173.03:37:06.75#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.03:37:06.75#ibcon#[27=USB\r\n] 2006.173.03:37:06.75#ibcon#*before write, iclass 28, count 0 2006.173.03:37:06.75#ibcon#enter sib2, iclass 28, count 0 2006.173.03:37:06.75#ibcon#flushed, iclass 28, count 0 2006.173.03:37:06.75#ibcon#about to write, iclass 28, count 0 2006.173.03:37:06.75#ibcon#wrote, iclass 28, count 0 2006.173.03:37:06.75#ibcon#about to read 3, iclass 28, count 0 2006.173.03:37:06.78#ibcon#read 3, iclass 28, count 0 2006.173.03:37:06.78#ibcon#about to read 4, iclass 28, count 0 2006.173.03:37:06.78#ibcon#read 4, iclass 28, count 0 2006.173.03:37:06.78#ibcon#about to read 5, iclass 28, count 0 2006.173.03:37:06.78#ibcon#read 5, iclass 28, count 0 2006.173.03:37:06.78#ibcon#about to read 6, iclass 28, count 0 2006.173.03:37:06.78#ibcon#read 6, iclass 28, count 0 2006.173.03:37:06.78#ibcon#end of sib2, iclass 28, count 0 2006.173.03:37:06.78#ibcon#*after write, iclass 28, count 0 2006.173.03:37:06.78#ibcon#*before return 0, iclass 28, count 0 2006.173.03:37:06.78#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.03:37:06.78#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.03:37:06.78#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.03:37:06.78#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.03:37:06.78$vck44/vblo=3,649.99 2006.173.03:37:06.78#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.03:37:06.78#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.03:37:06.78#ibcon#ireg 17 cls_cnt 0 2006.173.03:37:06.78#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.03:37:06.78#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.03:37:06.78#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.03:37:06.78#ibcon#enter wrdev, iclass 30, count 0 2006.173.03:37:06.78#ibcon#first serial, iclass 30, count 0 2006.173.03:37:06.78#ibcon#enter sib2, iclass 30, count 0 2006.173.03:37:06.78#ibcon#flushed, iclass 30, count 0 2006.173.03:37:06.78#ibcon#about to write, iclass 30, count 0 2006.173.03:37:06.78#ibcon#wrote, iclass 30, count 0 2006.173.03:37:06.78#ibcon#about to read 3, iclass 30, count 0 2006.173.03:37:06.80#ibcon#read 3, iclass 30, count 0 2006.173.03:37:06.80#ibcon#about to read 4, iclass 30, count 0 2006.173.03:37:06.80#ibcon#read 4, iclass 30, count 0 2006.173.03:37:06.80#ibcon#about to read 5, iclass 30, count 0 2006.173.03:37:06.80#ibcon#read 5, iclass 30, count 0 2006.173.03:37:06.80#ibcon#about to read 6, iclass 30, count 0 2006.173.03:37:06.80#ibcon#read 6, iclass 30, count 0 2006.173.03:37:06.80#ibcon#end of sib2, iclass 30, count 0 2006.173.03:37:06.80#ibcon#*mode == 0, iclass 30, count 0 2006.173.03:37:06.80#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.03:37:06.80#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.03:37:06.80#ibcon#*before write, iclass 30, count 0 2006.173.03:37:06.80#ibcon#enter sib2, iclass 30, count 0 2006.173.03:37:06.80#ibcon#flushed, iclass 30, count 0 2006.173.03:37:06.80#ibcon#about to write, iclass 30, count 0 2006.173.03:37:06.80#ibcon#wrote, iclass 30, count 0 2006.173.03:37:06.80#ibcon#about to read 3, iclass 30, count 0 2006.173.03:37:06.84#ibcon#read 3, iclass 30, count 0 2006.173.03:37:06.84#ibcon#about to read 4, iclass 30, count 0 2006.173.03:37:06.84#ibcon#read 4, iclass 30, count 0 2006.173.03:37:06.84#ibcon#about to read 5, iclass 30, count 0 2006.173.03:37:06.84#ibcon#read 5, iclass 30, count 0 2006.173.03:37:06.84#ibcon#about to read 6, iclass 30, count 0 2006.173.03:37:06.84#ibcon#read 6, iclass 30, count 0 2006.173.03:37:06.84#ibcon#end of sib2, iclass 30, count 0 2006.173.03:37:06.84#ibcon#*after write, iclass 30, count 0 2006.173.03:37:06.84#ibcon#*before return 0, iclass 30, count 0 2006.173.03:37:06.84#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.03:37:06.84#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.03:37:06.84#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.03:37:06.84#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.03:37:06.84$vck44/vb=3,4 2006.173.03:37:06.84#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.173.03:37:06.84#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.173.03:37:06.84#ibcon#ireg 11 cls_cnt 2 2006.173.03:37:06.84#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.03:37:06.90#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.03:37:06.90#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.03:37:06.90#ibcon#enter wrdev, iclass 32, count 2 2006.173.03:37:06.90#ibcon#first serial, iclass 32, count 2 2006.173.03:37:06.90#ibcon#enter sib2, iclass 32, count 2 2006.173.03:37:06.90#ibcon#flushed, iclass 32, count 2 2006.173.03:37:06.90#ibcon#about to write, iclass 32, count 2 2006.173.03:37:06.90#ibcon#wrote, iclass 32, count 2 2006.173.03:37:06.90#ibcon#about to read 3, iclass 32, count 2 2006.173.03:37:06.92#ibcon#read 3, iclass 32, count 2 2006.173.03:37:06.92#ibcon#about to read 4, iclass 32, count 2 2006.173.03:37:06.92#ibcon#read 4, iclass 32, count 2 2006.173.03:37:06.92#ibcon#about to read 5, iclass 32, count 2 2006.173.03:37:06.92#ibcon#read 5, iclass 32, count 2 2006.173.03:37:06.92#ibcon#about to read 6, iclass 32, count 2 2006.173.03:37:06.92#ibcon#read 6, iclass 32, count 2 2006.173.03:37:06.92#ibcon#end of sib2, iclass 32, count 2 2006.173.03:37:06.92#ibcon#*mode == 0, iclass 32, count 2 2006.173.03:37:06.92#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.173.03:37:06.92#ibcon#[27=AT03-04\r\n] 2006.173.03:37:06.92#ibcon#*before write, iclass 32, count 2 2006.173.03:37:06.92#ibcon#enter sib2, iclass 32, count 2 2006.173.03:37:06.92#ibcon#flushed, iclass 32, count 2 2006.173.03:37:06.92#ibcon#about to write, iclass 32, count 2 2006.173.03:37:06.92#ibcon#wrote, iclass 32, count 2 2006.173.03:37:06.92#ibcon#about to read 3, iclass 32, count 2 2006.173.03:37:06.95#ibcon#read 3, iclass 32, count 2 2006.173.03:37:06.95#ibcon#about to read 4, iclass 32, count 2 2006.173.03:37:06.95#ibcon#read 4, iclass 32, count 2 2006.173.03:37:06.95#ibcon#about to read 5, iclass 32, count 2 2006.173.03:37:06.95#ibcon#read 5, iclass 32, count 2 2006.173.03:37:06.95#ibcon#about to read 6, iclass 32, count 2 2006.173.03:37:06.95#ibcon#read 6, iclass 32, count 2 2006.173.03:37:06.95#ibcon#end of sib2, iclass 32, count 2 2006.173.03:37:06.95#ibcon#*after write, iclass 32, count 2 2006.173.03:37:06.95#ibcon#*before return 0, iclass 32, count 2 2006.173.03:37:06.95#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.03:37:06.95#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.173.03:37:06.95#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.173.03:37:06.95#ibcon#ireg 7 cls_cnt 0 2006.173.03:37:06.95#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.03:37:07.07#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.03:37:07.07#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.03:37:07.07#ibcon#enter wrdev, iclass 32, count 0 2006.173.03:37:07.07#ibcon#first serial, iclass 32, count 0 2006.173.03:37:07.07#ibcon#enter sib2, iclass 32, count 0 2006.173.03:37:07.07#ibcon#flushed, iclass 32, count 0 2006.173.03:37:07.07#ibcon#about to write, iclass 32, count 0 2006.173.03:37:07.07#ibcon#wrote, iclass 32, count 0 2006.173.03:37:07.07#ibcon#about to read 3, iclass 32, count 0 2006.173.03:37:07.09#ibcon#read 3, iclass 32, count 0 2006.173.03:37:07.09#ibcon#about to read 4, iclass 32, count 0 2006.173.03:37:07.09#ibcon#read 4, iclass 32, count 0 2006.173.03:37:07.09#ibcon#about to read 5, iclass 32, count 0 2006.173.03:37:07.09#ibcon#read 5, iclass 32, count 0 2006.173.03:37:07.09#ibcon#about to read 6, iclass 32, count 0 2006.173.03:37:07.09#ibcon#read 6, iclass 32, count 0 2006.173.03:37:07.09#ibcon#end of sib2, iclass 32, count 0 2006.173.03:37:07.09#ibcon#*mode == 0, iclass 32, count 0 2006.173.03:37:07.09#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.03:37:07.09#ibcon#[27=USB\r\n] 2006.173.03:37:07.09#ibcon#*before write, iclass 32, count 0 2006.173.03:37:07.09#ibcon#enter sib2, iclass 32, count 0 2006.173.03:37:07.09#ibcon#flushed, iclass 32, count 0 2006.173.03:37:07.09#ibcon#about to write, iclass 32, count 0 2006.173.03:37:07.09#ibcon#wrote, iclass 32, count 0 2006.173.03:37:07.09#ibcon#about to read 3, iclass 32, count 0 2006.173.03:37:07.12#ibcon#read 3, iclass 32, count 0 2006.173.03:37:07.12#ibcon#about to read 4, iclass 32, count 0 2006.173.03:37:07.12#ibcon#read 4, iclass 32, count 0 2006.173.03:37:07.12#ibcon#about to read 5, iclass 32, count 0 2006.173.03:37:07.12#ibcon#read 5, iclass 32, count 0 2006.173.03:37:07.12#ibcon#about to read 6, iclass 32, count 0 2006.173.03:37:07.12#ibcon#read 6, iclass 32, count 0 2006.173.03:37:07.12#ibcon#end of sib2, iclass 32, count 0 2006.173.03:37:07.12#ibcon#*after write, iclass 32, count 0 2006.173.03:37:07.12#ibcon#*before return 0, iclass 32, count 0 2006.173.03:37:07.12#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.03:37:07.12#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.173.03:37:07.12#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.03:37:07.12#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.03:37:07.12$vck44/vblo=4,679.99 2006.173.03:37:07.12#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.03:37:07.12#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.03:37:07.12#ibcon#ireg 17 cls_cnt 0 2006.173.03:37:07.12#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.03:37:07.12#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.03:37:07.12#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.03:37:07.12#ibcon#enter wrdev, iclass 34, count 0 2006.173.03:37:07.12#ibcon#first serial, iclass 34, count 0 2006.173.03:37:07.12#ibcon#enter sib2, iclass 34, count 0 2006.173.03:37:07.12#ibcon#flushed, iclass 34, count 0 2006.173.03:37:07.12#ibcon#about to write, iclass 34, count 0 2006.173.03:37:07.12#ibcon#wrote, iclass 34, count 0 2006.173.03:37:07.12#ibcon#about to read 3, iclass 34, count 0 2006.173.03:37:07.14#ibcon#read 3, iclass 34, count 0 2006.173.03:37:07.14#ibcon#about to read 4, iclass 34, count 0 2006.173.03:37:07.14#ibcon#read 4, iclass 34, count 0 2006.173.03:37:07.14#ibcon#about to read 5, iclass 34, count 0 2006.173.03:37:07.14#ibcon#read 5, iclass 34, count 0 2006.173.03:37:07.14#ibcon#about to read 6, iclass 34, count 0 2006.173.03:37:07.14#ibcon#read 6, iclass 34, count 0 2006.173.03:37:07.14#ibcon#end of sib2, iclass 34, count 0 2006.173.03:37:07.14#ibcon#*mode == 0, iclass 34, count 0 2006.173.03:37:07.14#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.03:37:07.14#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.03:37:07.14#ibcon#*before write, iclass 34, count 0 2006.173.03:37:07.14#ibcon#enter sib2, iclass 34, count 0 2006.173.03:37:07.14#ibcon#flushed, iclass 34, count 0 2006.173.03:37:07.14#ibcon#about to write, iclass 34, count 0 2006.173.03:37:07.14#ibcon#wrote, iclass 34, count 0 2006.173.03:37:07.14#ibcon#about to read 3, iclass 34, count 0 2006.173.03:37:07.18#ibcon#read 3, iclass 34, count 0 2006.173.03:37:07.18#ibcon#about to read 4, iclass 34, count 0 2006.173.03:37:07.18#ibcon#read 4, iclass 34, count 0 2006.173.03:37:07.18#ibcon#about to read 5, iclass 34, count 0 2006.173.03:37:07.18#ibcon#read 5, iclass 34, count 0 2006.173.03:37:07.18#ibcon#about to read 6, iclass 34, count 0 2006.173.03:37:07.18#ibcon#read 6, iclass 34, count 0 2006.173.03:37:07.18#ibcon#end of sib2, iclass 34, count 0 2006.173.03:37:07.18#ibcon#*after write, iclass 34, count 0 2006.173.03:37:07.18#ibcon#*before return 0, iclass 34, count 0 2006.173.03:37:07.18#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.03:37:07.18#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.03:37:07.18#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.03:37:07.18#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.03:37:07.18$vck44/vb=4,4 2006.173.03:37:07.18#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.03:37:07.18#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.03:37:07.18#ibcon#ireg 11 cls_cnt 2 2006.173.03:37:07.18#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.03:37:07.24#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.03:37:07.24#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.03:37:07.24#ibcon#enter wrdev, iclass 36, count 2 2006.173.03:37:07.24#ibcon#first serial, iclass 36, count 2 2006.173.03:37:07.24#ibcon#enter sib2, iclass 36, count 2 2006.173.03:37:07.24#ibcon#flushed, iclass 36, count 2 2006.173.03:37:07.24#ibcon#about to write, iclass 36, count 2 2006.173.03:37:07.24#ibcon#wrote, iclass 36, count 2 2006.173.03:37:07.24#ibcon#about to read 3, iclass 36, count 2 2006.173.03:37:07.26#ibcon#read 3, iclass 36, count 2 2006.173.03:37:07.26#ibcon#about to read 4, iclass 36, count 2 2006.173.03:37:07.26#ibcon#read 4, iclass 36, count 2 2006.173.03:37:07.26#ibcon#about to read 5, iclass 36, count 2 2006.173.03:37:07.26#ibcon#read 5, iclass 36, count 2 2006.173.03:37:07.26#ibcon#about to read 6, iclass 36, count 2 2006.173.03:37:07.26#ibcon#read 6, iclass 36, count 2 2006.173.03:37:07.26#ibcon#end of sib2, iclass 36, count 2 2006.173.03:37:07.26#ibcon#*mode == 0, iclass 36, count 2 2006.173.03:37:07.26#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.03:37:07.26#ibcon#[27=AT04-04\r\n] 2006.173.03:37:07.26#ibcon#*before write, iclass 36, count 2 2006.173.03:37:07.26#ibcon#enter sib2, iclass 36, count 2 2006.173.03:37:07.26#ibcon#flushed, iclass 36, count 2 2006.173.03:37:07.26#ibcon#about to write, iclass 36, count 2 2006.173.03:37:07.26#ibcon#wrote, iclass 36, count 2 2006.173.03:37:07.26#ibcon#about to read 3, iclass 36, count 2 2006.173.03:37:07.29#ibcon#read 3, iclass 36, count 2 2006.173.03:37:07.29#ibcon#about to read 4, iclass 36, count 2 2006.173.03:37:07.29#ibcon#read 4, iclass 36, count 2 2006.173.03:37:07.29#ibcon#about to read 5, iclass 36, count 2 2006.173.03:37:07.29#ibcon#read 5, iclass 36, count 2 2006.173.03:37:07.29#ibcon#about to read 6, iclass 36, count 2 2006.173.03:37:07.29#ibcon#read 6, iclass 36, count 2 2006.173.03:37:07.29#ibcon#end of sib2, iclass 36, count 2 2006.173.03:37:07.29#ibcon#*after write, iclass 36, count 2 2006.173.03:37:07.29#ibcon#*before return 0, iclass 36, count 2 2006.173.03:37:07.29#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.03:37:07.29#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.03:37:07.29#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.03:37:07.29#ibcon#ireg 7 cls_cnt 0 2006.173.03:37:07.29#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.03:37:07.41#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.03:37:07.41#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.03:37:07.41#ibcon#enter wrdev, iclass 36, count 0 2006.173.03:37:07.41#ibcon#first serial, iclass 36, count 0 2006.173.03:37:07.41#ibcon#enter sib2, iclass 36, count 0 2006.173.03:37:07.41#ibcon#flushed, iclass 36, count 0 2006.173.03:37:07.41#ibcon#about to write, iclass 36, count 0 2006.173.03:37:07.41#ibcon#wrote, iclass 36, count 0 2006.173.03:37:07.41#ibcon#about to read 3, iclass 36, count 0 2006.173.03:37:07.43#ibcon#read 3, iclass 36, count 0 2006.173.03:37:07.43#ibcon#about to read 4, iclass 36, count 0 2006.173.03:37:07.43#ibcon#read 4, iclass 36, count 0 2006.173.03:37:07.43#ibcon#about to read 5, iclass 36, count 0 2006.173.03:37:07.43#ibcon#read 5, iclass 36, count 0 2006.173.03:37:07.43#ibcon#about to read 6, iclass 36, count 0 2006.173.03:37:07.43#ibcon#read 6, iclass 36, count 0 2006.173.03:37:07.43#ibcon#end of sib2, iclass 36, count 0 2006.173.03:37:07.43#ibcon#*mode == 0, iclass 36, count 0 2006.173.03:37:07.43#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.03:37:07.43#ibcon#[27=USB\r\n] 2006.173.03:37:07.43#ibcon#*before write, iclass 36, count 0 2006.173.03:37:07.43#ibcon#enter sib2, iclass 36, count 0 2006.173.03:37:07.43#ibcon#flushed, iclass 36, count 0 2006.173.03:37:07.43#ibcon#about to write, iclass 36, count 0 2006.173.03:37:07.43#ibcon#wrote, iclass 36, count 0 2006.173.03:37:07.43#ibcon#about to read 3, iclass 36, count 0 2006.173.03:37:07.46#ibcon#read 3, iclass 36, count 0 2006.173.03:37:07.46#ibcon#about to read 4, iclass 36, count 0 2006.173.03:37:07.46#ibcon#read 4, iclass 36, count 0 2006.173.03:37:07.46#ibcon#about to read 5, iclass 36, count 0 2006.173.03:37:07.46#ibcon#read 5, iclass 36, count 0 2006.173.03:37:07.46#ibcon#about to read 6, iclass 36, count 0 2006.173.03:37:07.46#ibcon#read 6, iclass 36, count 0 2006.173.03:37:07.46#ibcon#end of sib2, iclass 36, count 0 2006.173.03:37:07.46#ibcon#*after write, iclass 36, count 0 2006.173.03:37:07.46#ibcon#*before return 0, iclass 36, count 0 2006.173.03:37:07.46#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.03:37:07.46#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.03:37:07.46#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.03:37:07.46#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.03:37:07.46$vck44/vblo=5,709.99 2006.173.03:37:07.46#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.03:37:07.46#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.03:37:07.46#ibcon#ireg 17 cls_cnt 0 2006.173.03:37:07.46#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.03:37:07.46#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.03:37:07.46#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.03:37:07.46#ibcon#enter wrdev, iclass 38, count 0 2006.173.03:37:07.46#ibcon#first serial, iclass 38, count 0 2006.173.03:37:07.46#ibcon#enter sib2, iclass 38, count 0 2006.173.03:37:07.46#ibcon#flushed, iclass 38, count 0 2006.173.03:37:07.46#ibcon#about to write, iclass 38, count 0 2006.173.03:37:07.46#ibcon#wrote, iclass 38, count 0 2006.173.03:37:07.46#ibcon#about to read 3, iclass 38, count 0 2006.173.03:37:07.48#ibcon#read 3, iclass 38, count 0 2006.173.03:37:07.48#ibcon#about to read 4, iclass 38, count 0 2006.173.03:37:07.48#ibcon#read 4, iclass 38, count 0 2006.173.03:37:07.48#ibcon#about to read 5, iclass 38, count 0 2006.173.03:37:07.48#ibcon#read 5, iclass 38, count 0 2006.173.03:37:07.48#ibcon#about to read 6, iclass 38, count 0 2006.173.03:37:07.48#ibcon#read 6, iclass 38, count 0 2006.173.03:37:07.48#ibcon#end of sib2, iclass 38, count 0 2006.173.03:37:07.48#ibcon#*mode == 0, iclass 38, count 0 2006.173.03:37:07.48#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.03:37:07.48#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.03:37:07.48#ibcon#*before write, iclass 38, count 0 2006.173.03:37:07.48#ibcon#enter sib2, iclass 38, count 0 2006.173.03:37:07.48#ibcon#flushed, iclass 38, count 0 2006.173.03:37:07.48#ibcon#about to write, iclass 38, count 0 2006.173.03:37:07.48#ibcon#wrote, iclass 38, count 0 2006.173.03:37:07.48#ibcon#about to read 3, iclass 38, count 0 2006.173.03:37:07.52#ibcon#read 3, iclass 38, count 0 2006.173.03:37:07.52#ibcon#about to read 4, iclass 38, count 0 2006.173.03:37:07.52#ibcon#read 4, iclass 38, count 0 2006.173.03:37:07.52#ibcon#about to read 5, iclass 38, count 0 2006.173.03:37:07.52#ibcon#read 5, iclass 38, count 0 2006.173.03:37:07.52#ibcon#about to read 6, iclass 38, count 0 2006.173.03:37:07.52#ibcon#read 6, iclass 38, count 0 2006.173.03:37:07.52#ibcon#end of sib2, iclass 38, count 0 2006.173.03:37:07.52#ibcon#*after write, iclass 38, count 0 2006.173.03:37:07.52#ibcon#*before return 0, iclass 38, count 0 2006.173.03:37:07.52#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.03:37:07.52#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.03:37:07.52#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.03:37:07.52#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.03:37:07.52$vck44/vb=5,4 2006.173.03:37:07.52#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.03:37:07.52#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.03:37:07.52#ibcon#ireg 11 cls_cnt 2 2006.173.03:37:07.52#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.03:37:07.58#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.03:37:07.58#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.03:37:07.58#ibcon#enter wrdev, iclass 40, count 2 2006.173.03:37:07.58#ibcon#first serial, iclass 40, count 2 2006.173.03:37:07.58#ibcon#enter sib2, iclass 40, count 2 2006.173.03:37:07.58#ibcon#flushed, iclass 40, count 2 2006.173.03:37:07.58#ibcon#about to write, iclass 40, count 2 2006.173.03:37:07.58#ibcon#wrote, iclass 40, count 2 2006.173.03:37:07.58#ibcon#about to read 3, iclass 40, count 2 2006.173.03:37:07.60#ibcon#read 3, iclass 40, count 2 2006.173.03:37:07.60#ibcon#about to read 4, iclass 40, count 2 2006.173.03:37:07.60#ibcon#read 4, iclass 40, count 2 2006.173.03:37:07.60#ibcon#about to read 5, iclass 40, count 2 2006.173.03:37:07.60#ibcon#read 5, iclass 40, count 2 2006.173.03:37:07.60#ibcon#about to read 6, iclass 40, count 2 2006.173.03:37:07.60#ibcon#read 6, iclass 40, count 2 2006.173.03:37:07.60#ibcon#end of sib2, iclass 40, count 2 2006.173.03:37:07.60#ibcon#*mode == 0, iclass 40, count 2 2006.173.03:37:07.60#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.03:37:07.60#ibcon#[27=AT05-04\r\n] 2006.173.03:37:07.60#ibcon#*before write, iclass 40, count 2 2006.173.03:37:07.60#ibcon#enter sib2, iclass 40, count 2 2006.173.03:37:07.60#ibcon#flushed, iclass 40, count 2 2006.173.03:37:07.60#ibcon#about to write, iclass 40, count 2 2006.173.03:37:07.60#ibcon#wrote, iclass 40, count 2 2006.173.03:37:07.60#ibcon#about to read 3, iclass 40, count 2 2006.173.03:37:07.63#ibcon#read 3, iclass 40, count 2 2006.173.03:37:07.63#ibcon#about to read 4, iclass 40, count 2 2006.173.03:37:07.63#ibcon#read 4, iclass 40, count 2 2006.173.03:37:07.63#ibcon#about to read 5, iclass 40, count 2 2006.173.03:37:07.63#ibcon#read 5, iclass 40, count 2 2006.173.03:37:07.63#ibcon#about to read 6, iclass 40, count 2 2006.173.03:37:07.63#ibcon#read 6, iclass 40, count 2 2006.173.03:37:07.63#ibcon#end of sib2, iclass 40, count 2 2006.173.03:37:07.63#ibcon#*after write, iclass 40, count 2 2006.173.03:37:07.63#ibcon#*before return 0, iclass 40, count 2 2006.173.03:37:07.63#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.03:37:07.63#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.03:37:07.63#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.03:37:07.63#ibcon#ireg 7 cls_cnt 0 2006.173.03:37:07.63#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.03:37:07.75#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.03:37:07.75#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.03:37:07.75#ibcon#enter wrdev, iclass 40, count 0 2006.173.03:37:07.75#ibcon#first serial, iclass 40, count 0 2006.173.03:37:07.75#ibcon#enter sib2, iclass 40, count 0 2006.173.03:37:07.75#ibcon#flushed, iclass 40, count 0 2006.173.03:37:07.75#ibcon#about to write, iclass 40, count 0 2006.173.03:37:07.75#ibcon#wrote, iclass 40, count 0 2006.173.03:37:07.75#ibcon#about to read 3, iclass 40, count 0 2006.173.03:37:07.77#ibcon#read 3, iclass 40, count 0 2006.173.03:37:07.77#ibcon#about to read 4, iclass 40, count 0 2006.173.03:37:07.77#ibcon#read 4, iclass 40, count 0 2006.173.03:37:07.77#ibcon#about to read 5, iclass 40, count 0 2006.173.03:37:07.77#ibcon#read 5, iclass 40, count 0 2006.173.03:37:07.77#ibcon#about to read 6, iclass 40, count 0 2006.173.03:37:07.77#ibcon#read 6, iclass 40, count 0 2006.173.03:37:07.77#ibcon#end of sib2, iclass 40, count 0 2006.173.03:37:07.77#ibcon#*mode == 0, iclass 40, count 0 2006.173.03:37:07.77#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.03:37:07.77#ibcon#[27=USB\r\n] 2006.173.03:37:07.77#ibcon#*before write, iclass 40, count 0 2006.173.03:37:07.77#ibcon#enter sib2, iclass 40, count 0 2006.173.03:37:07.77#ibcon#flushed, iclass 40, count 0 2006.173.03:37:07.77#ibcon#about to write, iclass 40, count 0 2006.173.03:37:07.77#ibcon#wrote, iclass 40, count 0 2006.173.03:37:07.77#ibcon#about to read 3, iclass 40, count 0 2006.173.03:37:07.80#ibcon#read 3, iclass 40, count 0 2006.173.03:37:07.80#ibcon#about to read 4, iclass 40, count 0 2006.173.03:37:07.80#ibcon#read 4, iclass 40, count 0 2006.173.03:37:07.80#ibcon#about to read 5, iclass 40, count 0 2006.173.03:37:07.80#ibcon#read 5, iclass 40, count 0 2006.173.03:37:07.80#ibcon#about to read 6, iclass 40, count 0 2006.173.03:37:07.80#ibcon#read 6, iclass 40, count 0 2006.173.03:37:07.80#ibcon#end of sib2, iclass 40, count 0 2006.173.03:37:07.80#ibcon#*after write, iclass 40, count 0 2006.173.03:37:07.80#ibcon#*before return 0, iclass 40, count 0 2006.173.03:37:07.80#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.03:37:07.80#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.03:37:07.80#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.03:37:07.80#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.03:37:07.80$vck44/vblo=6,719.99 2006.173.03:37:07.80#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.03:37:07.80#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.03:37:07.80#ibcon#ireg 17 cls_cnt 0 2006.173.03:37:07.80#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.03:37:07.80#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.03:37:07.80#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.03:37:07.80#ibcon#enter wrdev, iclass 4, count 0 2006.173.03:37:07.80#ibcon#first serial, iclass 4, count 0 2006.173.03:37:07.80#ibcon#enter sib2, iclass 4, count 0 2006.173.03:37:07.80#ibcon#flushed, iclass 4, count 0 2006.173.03:37:07.80#ibcon#about to write, iclass 4, count 0 2006.173.03:37:07.80#ibcon#wrote, iclass 4, count 0 2006.173.03:37:07.80#ibcon#about to read 3, iclass 4, count 0 2006.173.03:37:07.82#ibcon#read 3, iclass 4, count 0 2006.173.03:37:07.82#ibcon#about to read 4, iclass 4, count 0 2006.173.03:37:07.82#ibcon#read 4, iclass 4, count 0 2006.173.03:37:07.82#ibcon#about to read 5, iclass 4, count 0 2006.173.03:37:07.82#ibcon#read 5, iclass 4, count 0 2006.173.03:37:07.82#ibcon#about to read 6, iclass 4, count 0 2006.173.03:37:07.82#ibcon#read 6, iclass 4, count 0 2006.173.03:37:07.82#ibcon#end of sib2, iclass 4, count 0 2006.173.03:37:07.82#ibcon#*mode == 0, iclass 4, count 0 2006.173.03:37:07.82#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.03:37:07.82#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.03:37:07.82#ibcon#*before write, iclass 4, count 0 2006.173.03:37:07.82#ibcon#enter sib2, iclass 4, count 0 2006.173.03:37:07.82#ibcon#flushed, iclass 4, count 0 2006.173.03:37:07.82#ibcon#about to write, iclass 4, count 0 2006.173.03:37:07.82#ibcon#wrote, iclass 4, count 0 2006.173.03:37:07.82#ibcon#about to read 3, iclass 4, count 0 2006.173.03:37:07.86#ibcon#read 3, iclass 4, count 0 2006.173.03:37:07.86#ibcon#about to read 4, iclass 4, count 0 2006.173.03:37:07.86#ibcon#read 4, iclass 4, count 0 2006.173.03:37:07.86#ibcon#about to read 5, iclass 4, count 0 2006.173.03:37:07.86#ibcon#read 5, iclass 4, count 0 2006.173.03:37:07.86#ibcon#about to read 6, iclass 4, count 0 2006.173.03:37:07.86#ibcon#read 6, iclass 4, count 0 2006.173.03:37:07.86#ibcon#end of sib2, iclass 4, count 0 2006.173.03:37:07.86#ibcon#*after write, iclass 4, count 0 2006.173.03:37:07.86#ibcon#*before return 0, iclass 4, count 0 2006.173.03:37:07.86#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.03:37:07.86#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.03:37:07.86#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.03:37:07.86#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.03:37:07.86$vck44/vb=6,4 2006.173.03:37:07.86#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.03:37:07.86#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.03:37:07.86#ibcon#ireg 11 cls_cnt 2 2006.173.03:37:07.86#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.03:37:07.92#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.03:37:07.92#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.03:37:07.92#ibcon#enter wrdev, iclass 6, count 2 2006.173.03:37:07.92#ibcon#first serial, iclass 6, count 2 2006.173.03:37:07.92#ibcon#enter sib2, iclass 6, count 2 2006.173.03:37:07.92#ibcon#flushed, iclass 6, count 2 2006.173.03:37:07.92#ibcon#about to write, iclass 6, count 2 2006.173.03:37:07.92#ibcon#wrote, iclass 6, count 2 2006.173.03:37:07.92#ibcon#about to read 3, iclass 6, count 2 2006.173.03:37:07.94#ibcon#read 3, iclass 6, count 2 2006.173.03:37:07.94#ibcon#about to read 4, iclass 6, count 2 2006.173.03:37:07.94#ibcon#read 4, iclass 6, count 2 2006.173.03:37:07.94#ibcon#about to read 5, iclass 6, count 2 2006.173.03:37:07.94#ibcon#read 5, iclass 6, count 2 2006.173.03:37:07.94#ibcon#about to read 6, iclass 6, count 2 2006.173.03:37:07.94#ibcon#read 6, iclass 6, count 2 2006.173.03:37:07.94#ibcon#end of sib2, iclass 6, count 2 2006.173.03:37:07.94#ibcon#*mode == 0, iclass 6, count 2 2006.173.03:37:07.94#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.03:37:07.94#ibcon#[27=AT06-04\r\n] 2006.173.03:37:07.94#ibcon#*before write, iclass 6, count 2 2006.173.03:37:07.94#ibcon#enter sib2, iclass 6, count 2 2006.173.03:37:07.94#ibcon#flushed, iclass 6, count 2 2006.173.03:37:07.94#ibcon#about to write, iclass 6, count 2 2006.173.03:37:07.94#ibcon#wrote, iclass 6, count 2 2006.173.03:37:07.94#ibcon#about to read 3, iclass 6, count 2 2006.173.03:37:07.97#ibcon#read 3, iclass 6, count 2 2006.173.03:37:07.97#ibcon#about to read 4, iclass 6, count 2 2006.173.03:37:07.97#ibcon#read 4, iclass 6, count 2 2006.173.03:37:07.97#ibcon#about to read 5, iclass 6, count 2 2006.173.03:37:07.97#ibcon#read 5, iclass 6, count 2 2006.173.03:37:07.97#ibcon#about to read 6, iclass 6, count 2 2006.173.03:37:07.97#ibcon#read 6, iclass 6, count 2 2006.173.03:37:07.97#ibcon#end of sib2, iclass 6, count 2 2006.173.03:37:07.97#ibcon#*after write, iclass 6, count 2 2006.173.03:37:07.97#ibcon#*before return 0, iclass 6, count 2 2006.173.03:37:07.97#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.03:37:07.97#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.03:37:07.97#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.03:37:07.97#ibcon#ireg 7 cls_cnt 0 2006.173.03:37:07.97#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.03:37:08.09#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.03:37:08.09#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.03:37:08.09#ibcon#enter wrdev, iclass 6, count 0 2006.173.03:37:08.09#ibcon#first serial, iclass 6, count 0 2006.173.03:37:08.09#ibcon#enter sib2, iclass 6, count 0 2006.173.03:37:08.09#ibcon#flushed, iclass 6, count 0 2006.173.03:37:08.09#ibcon#about to write, iclass 6, count 0 2006.173.03:37:08.09#ibcon#wrote, iclass 6, count 0 2006.173.03:37:08.09#ibcon#about to read 3, iclass 6, count 0 2006.173.03:37:08.11#ibcon#read 3, iclass 6, count 0 2006.173.03:37:08.11#ibcon#about to read 4, iclass 6, count 0 2006.173.03:37:08.11#ibcon#read 4, iclass 6, count 0 2006.173.03:37:08.11#ibcon#about to read 5, iclass 6, count 0 2006.173.03:37:08.11#ibcon#read 5, iclass 6, count 0 2006.173.03:37:08.11#ibcon#about to read 6, iclass 6, count 0 2006.173.03:37:08.11#ibcon#read 6, iclass 6, count 0 2006.173.03:37:08.11#ibcon#end of sib2, iclass 6, count 0 2006.173.03:37:08.11#ibcon#*mode == 0, iclass 6, count 0 2006.173.03:37:08.11#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.03:37:08.11#ibcon#[27=USB\r\n] 2006.173.03:37:08.11#ibcon#*before write, iclass 6, count 0 2006.173.03:37:08.11#ibcon#enter sib2, iclass 6, count 0 2006.173.03:37:08.11#ibcon#flushed, iclass 6, count 0 2006.173.03:37:08.11#ibcon#about to write, iclass 6, count 0 2006.173.03:37:08.11#ibcon#wrote, iclass 6, count 0 2006.173.03:37:08.11#ibcon#about to read 3, iclass 6, count 0 2006.173.03:37:08.14#ibcon#read 3, iclass 6, count 0 2006.173.03:37:08.14#ibcon#about to read 4, iclass 6, count 0 2006.173.03:37:08.14#ibcon#read 4, iclass 6, count 0 2006.173.03:37:08.14#ibcon#about to read 5, iclass 6, count 0 2006.173.03:37:08.14#ibcon#read 5, iclass 6, count 0 2006.173.03:37:08.14#ibcon#about to read 6, iclass 6, count 0 2006.173.03:37:08.14#ibcon#read 6, iclass 6, count 0 2006.173.03:37:08.14#ibcon#end of sib2, iclass 6, count 0 2006.173.03:37:08.14#ibcon#*after write, iclass 6, count 0 2006.173.03:37:08.14#ibcon#*before return 0, iclass 6, count 0 2006.173.03:37:08.14#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.03:37:08.14#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.03:37:08.14#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.03:37:08.14#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.03:37:08.14$vck44/vblo=7,734.99 2006.173.03:37:08.14#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.03:37:08.14#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.03:37:08.14#ibcon#ireg 17 cls_cnt 0 2006.173.03:37:08.14#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.03:37:08.14#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.03:37:08.14#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.03:37:08.14#ibcon#enter wrdev, iclass 10, count 0 2006.173.03:37:08.14#ibcon#first serial, iclass 10, count 0 2006.173.03:37:08.14#ibcon#enter sib2, iclass 10, count 0 2006.173.03:37:08.14#ibcon#flushed, iclass 10, count 0 2006.173.03:37:08.14#ibcon#about to write, iclass 10, count 0 2006.173.03:37:08.14#ibcon#wrote, iclass 10, count 0 2006.173.03:37:08.14#ibcon#about to read 3, iclass 10, count 0 2006.173.03:37:08.16#ibcon#read 3, iclass 10, count 0 2006.173.03:37:08.16#ibcon#about to read 4, iclass 10, count 0 2006.173.03:37:08.16#ibcon#read 4, iclass 10, count 0 2006.173.03:37:08.16#ibcon#about to read 5, iclass 10, count 0 2006.173.03:37:08.16#ibcon#read 5, iclass 10, count 0 2006.173.03:37:08.16#ibcon#about to read 6, iclass 10, count 0 2006.173.03:37:08.16#ibcon#read 6, iclass 10, count 0 2006.173.03:37:08.16#ibcon#end of sib2, iclass 10, count 0 2006.173.03:37:08.16#ibcon#*mode == 0, iclass 10, count 0 2006.173.03:37:08.16#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.03:37:08.16#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.03:37:08.16#ibcon#*before write, iclass 10, count 0 2006.173.03:37:08.16#ibcon#enter sib2, iclass 10, count 0 2006.173.03:37:08.16#ibcon#flushed, iclass 10, count 0 2006.173.03:37:08.16#ibcon#about to write, iclass 10, count 0 2006.173.03:37:08.16#ibcon#wrote, iclass 10, count 0 2006.173.03:37:08.16#ibcon#about to read 3, iclass 10, count 0 2006.173.03:37:08.20#ibcon#read 3, iclass 10, count 0 2006.173.03:37:08.20#ibcon#about to read 4, iclass 10, count 0 2006.173.03:37:08.20#ibcon#read 4, iclass 10, count 0 2006.173.03:37:08.20#ibcon#about to read 5, iclass 10, count 0 2006.173.03:37:08.20#ibcon#read 5, iclass 10, count 0 2006.173.03:37:08.20#ibcon#about to read 6, iclass 10, count 0 2006.173.03:37:08.20#ibcon#read 6, iclass 10, count 0 2006.173.03:37:08.20#ibcon#end of sib2, iclass 10, count 0 2006.173.03:37:08.20#ibcon#*after write, iclass 10, count 0 2006.173.03:37:08.20#ibcon#*before return 0, iclass 10, count 0 2006.173.03:37:08.20#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.03:37:08.20#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.03:37:08.20#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.03:37:08.20#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.03:37:08.20$vck44/vb=7,4 2006.173.03:37:08.20#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.03:37:08.20#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.03:37:08.20#ibcon#ireg 11 cls_cnt 2 2006.173.03:37:08.20#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.03:37:08.26#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.03:37:08.26#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.03:37:08.26#ibcon#enter wrdev, iclass 12, count 2 2006.173.03:37:08.26#ibcon#first serial, iclass 12, count 2 2006.173.03:37:08.26#ibcon#enter sib2, iclass 12, count 2 2006.173.03:37:08.26#ibcon#flushed, iclass 12, count 2 2006.173.03:37:08.26#ibcon#about to write, iclass 12, count 2 2006.173.03:37:08.26#ibcon#wrote, iclass 12, count 2 2006.173.03:37:08.26#ibcon#about to read 3, iclass 12, count 2 2006.173.03:37:08.28#ibcon#read 3, iclass 12, count 2 2006.173.03:37:08.28#ibcon#about to read 4, iclass 12, count 2 2006.173.03:37:08.28#ibcon#read 4, iclass 12, count 2 2006.173.03:37:08.28#ibcon#about to read 5, iclass 12, count 2 2006.173.03:37:08.28#ibcon#read 5, iclass 12, count 2 2006.173.03:37:08.28#ibcon#about to read 6, iclass 12, count 2 2006.173.03:37:08.28#ibcon#read 6, iclass 12, count 2 2006.173.03:37:08.28#ibcon#end of sib2, iclass 12, count 2 2006.173.03:37:08.28#ibcon#*mode == 0, iclass 12, count 2 2006.173.03:37:08.28#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.03:37:08.28#ibcon#[27=AT07-04\r\n] 2006.173.03:37:08.28#ibcon#*before write, iclass 12, count 2 2006.173.03:37:08.28#ibcon#enter sib2, iclass 12, count 2 2006.173.03:37:08.28#ibcon#flushed, iclass 12, count 2 2006.173.03:37:08.28#ibcon#about to write, iclass 12, count 2 2006.173.03:37:08.28#ibcon#wrote, iclass 12, count 2 2006.173.03:37:08.28#ibcon#about to read 3, iclass 12, count 2 2006.173.03:37:08.31#ibcon#read 3, iclass 12, count 2 2006.173.03:37:08.31#ibcon#about to read 4, iclass 12, count 2 2006.173.03:37:08.31#ibcon#read 4, iclass 12, count 2 2006.173.03:37:08.31#ibcon#about to read 5, iclass 12, count 2 2006.173.03:37:08.31#ibcon#read 5, iclass 12, count 2 2006.173.03:37:08.31#ibcon#about to read 6, iclass 12, count 2 2006.173.03:37:08.31#ibcon#read 6, iclass 12, count 2 2006.173.03:37:08.31#ibcon#end of sib2, iclass 12, count 2 2006.173.03:37:08.31#ibcon#*after write, iclass 12, count 2 2006.173.03:37:08.31#ibcon#*before return 0, iclass 12, count 2 2006.173.03:37:08.31#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.03:37:08.31#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.03:37:08.31#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.03:37:08.31#ibcon#ireg 7 cls_cnt 0 2006.173.03:37:08.31#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.03:37:08.43#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.03:37:08.43#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.03:37:08.43#ibcon#enter wrdev, iclass 12, count 0 2006.173.03:37:08.43#ibcon#first serial, iclass 12, count 0 2006.173.03:37:08.43#ibcon#enter sib2, iclass 12, count 0 2006.173.03:37:08.43#ibcon#flushed, iclass 12, count 0 2006.173.03:37:08.43#ibcon#about to write, iclass 12, count 0 2006.173.03:37:08.43#ibcon#wrote, iclass 12, count 0 2006.173.03:37:08.43#ibcon#about to read 3, iclass 12, count 0 2006.173.03:37:08.45#ibcon#read 3, iclass 12, count 0 2006.173.03:37:08.45#ibcon#about to read 4, iclass 12, count 0 2006.173.03:37:08.45#ibcon#read 4, iclass 12, count 0 2006.173.03:37:08.45#ibcon#about to read 5, iclass 12, count 0 2006.173.03:37:08.45#ibcon#read 5, iclass 12, count 0 2006.173.03:37:08.45#ibcon#about to read 6, iclass 12, count 0 2006.173.03:37:08.45#ibcon#read 6, iclass 12, count 0 2006.173.03:37:08.45#ibcon#end of sib2, iclass 12, count 0 2006.173.03:37:08.45#ibcon#*mode == 0, iclass 12, count 0 2006.173.03:37:08.45#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.03:37:08.45#ibcon#[27=USB\r\n] 2006.173.03:37:08.45#ibcon#*before write, iclass 12, count 0 2006.173.03:37:08.45#ibcon#enter sib2, iclass 12, count 0 2006.173.03:37:08.45#ibcon#flushed, iclass 12, count 0 2006.173.03:37:08.45#ibcon#about to write, iclass 12, count 0 2006.173.03:37:08.45#ibcon#wrote, iclass 12, count 0 2006.173.03:37:08.45#ibcon#about to read 3, iclass 12, count 0 2006.173.03:37:08.48#ibcon#read 3, iclass 12, count 0 2006.173.03:37:08.48#ibcon#about to read 4, iclass 12, count 0 2006.173.03:37:08.48#ibcon#read 4, iclass 12, count 0 2006.173.03:37:08.48#ibcon#about to read 5, iclass 12, count 0 2006.173.03:37:08.48#ibcon#read 5, iclass 12, count 0 2006.173.03:37:08.48#ibcon#about to read 6, iclass 12, count 0 2006.173.03:37:08.48#ibcon#read 6, iclass 12, count 0 2006.173.03:37:08.48#ibcon#end of sib2, iclass 12, count 0 2006.173.03:37:08.48#ibcon#*after write, iclass 12, count 0 2006.173.03:37:08.48#ibcon#*before return 0, iclass 12, count 0 2006.173.03:37:08.48#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.03:37:08.48#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.03:37:08.48#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.03:37:08.48#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.03:37:08.48$vck44/vblo=8,744.99 2006.173.03:37:08.48#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.03:37:08.48#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.03:37:08.48#ibcon#ireg 17 cls_cnt 0 2006.173.03:37:08.48#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.03:37:08.48#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.03:37:08.48#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.03:37:08.48#ibcon#enter wrdev, iclass 14, count 0 2006.173.03:37:08.48#ibcon#first serial, iclass 14, count 0 2006.173.03:37:08.48#ibcon#enter sib2, iclass 14, count 0 2006.173.03:37:08.48#ibcon#flushed, iclass 14, count 0 2006.173.03:37:08.48#ibcon#about to write, iclass 14, count 0 2006.173.03:37:08.48#ibcon#wrote, iclass 14, count 0 2006.173.03:37:08.48#ibcon#about to read 3, iclass 14, count 0 2006.173.03:37:08.50#ibcon#read 3, iclass 14, count 0 2006.173.03:37:08.50#ibcon#about to read 4, iclass 14, count 0 2006.173.03:37:08.50#ibcon#read 4, iclass 14, count 0 2006.173.03:37:08.50#ibcon#about to read 5, iclass 14, count 0 2006.173.03:37:08.50#ibcon#read 5, iclass 14, count 0 2006.173.03:37:08.50#ibcon#about to read 6, iclass 14, count 0 2006.173.03:37:08.50#ibcon#read 6, iclass 14, count 0 2006.173.03:37:08.50#ibcon#end of sib2, iclass 14, count 0 2006.173.03:37:08.50#ibcon#*mode == 0, iclass 14, count 0 2006.173.03:37:08.50#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.03:37:08.50#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.03:37:08.50#ibcon#*before write, iclass 14, count 0 2006.173.03:37:08.50#ibcon#enter sib2, iclass 14, count 0 2006.173.03:37:08.50#ibcon#flushed, iclass 14, count 0 2006.173.03:37:08.50#ibcon#about to write, iclass 14, count 0 2006.173.03:37:08.50#ibcon#wrote, iclass 14, count 0 2006.173.03:37:08.50#ibcon#about to read 3, iclass 14, count 0 2006.173.03:37:08.54#ibcon#read 3, iclass 14, count 0 2006.173.03:37:08.54#ibcon#about to read 4, iclass 14, count 0 2006.173.03:37:08.54#ibcon#read 4, iclass 14, count 0 2006.173.03:37:08.54#ibcon#about to read 5, iclass 14, count 0 2006.173.03:37:08.54#ibcon#read 5, iclass 14, count 0 2006.173.03:37:08.54#ibcon#about to read 6, iclass 14, count 0 2006.173.03:37:08.54#ibcon#read 6, iclass 14, count 0 2006.173.03:37:08.54#ibcon#end of sib2, iclass 14, count 0 2006.173.03:37:08.54#ibcon#*after write, iclass 14, count 0 2006.173.03:37:08.54#ibcon#*before return 0, iclass 14, count 0 2006.173.03:37:08.54#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.03:37:08.54#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.03:37:08.54#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.03:37:08.54#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.03:37:08.54$vck44/vb=8,4 2006.173.03:37:08.54#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.03:37:08.54#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.03:37:08.54#ibcon#ireg 11 cls_cnt 2 2006.173.03:37:08.54#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.03:37:08.60#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.03:37:08.60#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.03:37:08.60#ibcon#enter wrdev, iclass 16, count 2 2006.173.03:37:08.60#ibcon#first serial, iclass 16, count 2 2006.173.03:37:08.60#ibcon#enter sib2, iclass 16, count 2 2006.173.03:37:08.60#ibcon#flushed, iclass 16, count 2 2006.173.03:37:08.60#ibcon#about to write, iclass 16, count 2 2006.173.03:37:08.60#ibcon#wrote, iclass 16, count 2 2006.173.03:37:08.60#ibcon#about to read 3, iclass 16, count 2 2006.173.03:37:08.62#ibcon#read 3, iclass 16, count 2 2006.173.03:37:08.62#ibcon#about to read 4, iclass 16, count 2 2006.173.03:37:08.62#ibcon#read 4, iclass 16, count 2 2006.173.03:37:08.62#ibcon#about to read 5, iclass 16, count 2 2006.173.03:37:08.62#ibcon#read 5, iclass 16, count 2 2006.173.03:37:08.62#ibcon#about to read 6, iclass 16, count 2 2006.173.03:37:08.62#ibcon#read 6, iclass 16, count 2 2006.173.03:37:08.62#ibcon#end of sib2, iclass 16, count 2 2006.173.03:37:08.62#ibcon#*mode == 0, iclass 16, count 2 2006.173.03:37:08.62#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.03:37:08.62#ibcon#[27=AT08-04\r\n] 2006.173.03:37:08.62#ibcon#*before write, iclass 16, count 2 2006.173.03:37:08.62#ibcon#enter sib2, iclass 16, count 2 2006.173.03:37:08.62#ibcon#flushed, iclass 16, count 2 2006.173.03:37:08.62#ibcon#about to write, iclass 16, count 2 2006.173.03:37:08.62#ibcon#wrote, iclass 16, count 2 2006.173.03:37:08.62#ibcon#about to read 3, iclass 16, count 2 2006.173.03:37:08.65#ibcon#read 3, iclass 16, count 2 2006.173.03:37:08.65#ibcon#about to read 4, iclass 16, count 2 2006.173.03:37:08.65#ibcon#read 4, iclass 16, count 2 2006.173.03:37:08.65#ibcon#about to read 5, iclass 16, count 2 2006.173.03:37:08.65#ibcon#read 5, iclass 16, count 2 2006.173.03:37:08.65#ibcon#about to read 6, iclass 16, count 2 2006.173.03:37:08.65#ibcon#read 6, iclass 16, count 2 2006.173.03:37:08.65#ibcon#end of sib2, iclass 16, count 2 2006.173.03:37:08.65#ibcon#*after write, iclass 16, count 2 2006.173.03:37:08.65#ibcon#*before return 0, iclass 16, count 2 2006.173.03:37:08.65#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.03:37:08.65#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.03:37:08.65#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.03:37:08.65#ibcon#ireg 7 cls_cnt 0 2006.173.03:37:08.65#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.03:37:08.77#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.03:37:08.77#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.03:37:08.77#ibcon#enter wrdev, iclass 16, count 0 2006.173.03:37:08.77#ibcon#first serial, iclass 16, count 0 2006.173.03:37:08.77#ibcon#enter sib2, iclass 16, count 0 2006.173.03:37:08.77#ibcon#flushed, iclass 16, count 0 2006.173.03:37:08.77#ibcon#about to write, iclass 16, count 0 2006.173.03:37:08.77#ibcon#wrote, iclass 16, count 0 2006.173.03:37:08.77#ibcon#about to read 3, iclass 16, count 0 2006.173.03:37:08.79#ibcon#read 3, iclass 16, count 0 2006.173.03:37:08.79#ibcon#about to read 4, iclass 16, count 0 2006.173.03:37:08.79#ibcon#read 4, iclass 16, count 0 2006.173.03:37:08.79#ibcon#about to read 5, iclass 16, count 0 2006.173.03:37:08.79#ibcon#read 5, iclass 16, count 0 2006.173.03:37:08.79#ibcon#about to read 6, iclass 16, count 0 2006.173.03:37:08.79#ibcon#read 6, iclass 16, count 0 2006.173.03:37:08.79#ibcon#end of sib2, iclass 16, count 0 2006.173.03:37:08.79#ibcon#*mode == 0, iclass 16, count 0 2006.173.03:37:08.79#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.03:37:08.79#ibcon#[27=USB\r\n] 2006.173.03:37:08.79#ibcon#*before write, iclass 16, count 0 2006.173.03:37:08.79#ibcon#enter sib2, iclass 16, count 0 2006.173.03:37:08.79#ibcon#flushed, iclass 16, count 0 2006.173.03:37:08.79#ibcon#about to write, iclass 16, count 0 2006.173.03:37:08.79#ibcon#wrote, iclass 16, count 0 2006.173.03:37:08.79#ibcon#about to read 3, iclass 16, count 0 2006.173.03:37:08.82#ibcon#read 3, iclass 16, count 0 2006.173.03:37:08.82#ibcon#about to read 4, iclass 16, count 0 2006.173.03:37:08.82#ibcon#read 4, iclass 16, count 0 2006.173.03:37:08.82#ibcon#about to read 5, iclass 16, count 0 2006.173.03:37:08.82#ibcon#read 5, iclass 16, count 0 2006.173.03:37:08.82#ibcon#about to read 6, iclass 16, count 0 2006.173.03:37:08.82#ibcon#read 6, iclass 16, count 0 2006.173.03:37:08.82#ibcon#end of sib2, iclass 16, count 0 2006.173.03:37:08.82#ibcon#*after write, iclass 16, count 0 2006.173.03:37:08.82#ibcon#*before return 0, iclass 16, count 0 2006.173.03:37:08.82#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.03:37:08.82#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.03:37:08.82#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.03:37:08.82#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.03:37:08.82$vck44/vabw=wide 2006.173.03:37:08.82#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.03:37:08.82#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.03:37:08.82#ibcon#ireg 8 cls_cnt 0 2006.173.03:37:08.82#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.03:37:08.82#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.03:37:08.82#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.03:37:08.82#ibcon#enter wrdev, iclass 18, count 0 2006.173.03:37:08.82#ibcon#first serial, iclass 18, count 0 2006.173.03:37:08.82#ibcon#enter sib2, iclass 18, count 0 2006.173.03:37:08.82#ibcon#flushed, iclass 18, count 0 2006.173.03:37:08.82#ibcon#about to write, iclass 18, count 0 2006.173.03:37:08.82#ibcon#wrote, iclass 18, count 0 2006.173.03:37:08.82#ibcon#about to read 3, iclass 18, count 0 2006.173.03:37:08.84#ibcon#read 3, iclass 18, count 0 2006.173.03:37:08.84#ibcon#about to read 4, iclass 18, count 0 2006.173.03:37:08.84#ibcon#read 4, iclass 18, count 0 2006.173.03:37:08.84#ibcon#about to read 5, iclass 18, count 0 2006.173.03:37:08.84#ibcon#read 5, iclass 18, count 0 2006.173.03:37:08.84#ibcon#about to read 6, iclass 18, count 0 2006.173.03:37:08.84#ibcon#read 6, iclass 18, count 0 2006.173.03:37:08.84#ibcon#end of sib2, iclass 18, count 0 2006.173.03:37:08.84#ibcon#*mode == 0, iclass 18, count 0 2006.173.03:37:08.84#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.03:37:08.84#ibcon#[25=BW32\r\n] 2006.173.03:37:08.84#ibcon#*before write, iclass 18, count 0 2006.173.03:37:08.84#ibcon#enter sib2, iclass 18, count 0 2006.173.03:37:08.84#ibcon#flushed, iclass 18, count 0 2006.173.03:37:08.84#ibcon#about to write, iclass 18, count 0 2006.173.03:37:08.84#ibcon#wrote, iclass 18, count 0 2006.173.03:37:08.84#ibcon#about to read 3, iclass 18, count 0 2006.173.03:37:08.87#ibcon#read 3, iclass 18, count 0 2006.173.03:37:08.87#ibcon#about to read 4, iclass 18, count 0 2006.173.03:37:08.87#ibcon#read 4, iclass 18, count 0 2006.173.03:37:08.87#ibcon#about to read 5, iclass 18, count 0 2006.173.03:37:08.87#ibcon#read 5, iclass 18, count 0 2006.173.03:37:08.87#ibcon#about to read 6, iclass 18, count 0 2006.173.03:37:08.87#ibcon#read 6, iclass 18, count 0 2006.173.03:37:08.87#ibcon#end of sib2, iclass 18, count 0 2006.173.03:37:08.87#ibcon#*after write, iclass 18, count 0 2006.173.03:37:08.87#ibcon#*before return 0, iclass 18, count 0 2006.173.03:37:08.87#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.03:37:08.87#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.03:37:08.87#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.03:37:08.87#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.03:37:08.87$vck44/vbbw=wide 2006.173.03:37:08.87#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.03:37:08.87#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.03:37:08.87#ibcon#ireg 8 cls_cnt 0 2006.173.03:37:08.87#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.03:37:08.94#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.03:37:08.94#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.03:37:08.94#ibcon#enter wrdev, iclass 20, count 0 2006.173.03:37:08.94#ibcon#first serial, iclass 20, count 0 2006.173.03:37:08.94#ibcon#enter sib2, iclass 20, count 0 2006.173.03:37:08.94#ibcon#flushed, iclass 20, count 0 2006.173.03:37:08.94#ibcon#about to write, iclass 20, count 0 2006.173.03:37:08.94#ibcon#wrote, iclass 20, count 0 2006.173.03:37:08.94#ibcon#about to read 3, iclass 20, count 0 2006.173.03:37:08.96#ibcon#read 3, iclass 20, count 0 2006.173.03:37:08.96#ibcon#about to read 4, iclass 20, count 0 2006.173.03:37:08.96#ibcon#read 4, iclass 20, count 0 2006.173.03:37:08.96#ibcon#about to read 5, iclass 20, count 0 2006.173.03:37:08.96#ibcon#read 5, iclass 20, count 0 2006.173.03:37:08.96#ibcon#about to read 6, iclass 20, count 0 2006.173.03:37:08.96#ibcon#read 6, iclass 20, count 0 2006.173.03:37:08.96#ibcon#end of sib2, iclass 20, count 0 2006.173.03:37:08.96#ibcon#*mode == 0, iclass 20, count 0 2006.173.03:37:08.96#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.03:37:08.96#ibcon#[27=BW32\r\n] 2006.173.03:37:08.96#ibcon#*before write, iclass 20, count 0 2006.173.03:37:08.96#ibcon#enter sib2, iclass 20, count 0 2006.173.03:37:08.96#ibcon#flushed, iclass 20, count 0 2006.173.03:37:08.96#ibcon#about to write, iclass 20, count 0 2006.173.03:37:08.96#ibcon#wrote, iclass 20, count 0 2006.173.03:37:08.96#ibcon#about to read 3, iclass 20, count 0 2006.173.03:37:08.99#ibcon#read 3, iclass 20, count 0 2006.173.03:37:08.99#ibcon#about to read 4, iclass 20, count 0 2006.173.03:37:08.99#ibcon#read 4, iclass 20, count 0 2006.173.03:37:08.99#ibcon#about to read 5, iclass 20, count 0 2006.173.03:37:08.99#ibcon#read 5, iclass 20, count 0 2006.173.03:37:08.99#ibcon#about to read 6, iclass 20, count 0 2006.173.03:37:08.99#ibcon#read 6, iclass 20, count 0 2006.173.03:37:08.99#ibcon#end of sib2, iclass 20, count 0 2006.173.03:37:08.99#ibcon#*after write, iclass 20, count 0 2006.173.03:37:08.99#ibcon#*before return 0, iclass 20, count 0 2006.173.03:37:08.99#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.03:37:08.99#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.03:37:08.99#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.03:37:08.99#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.03:37:08.99$setupk4/ifdk4 2006.173.03:37:08.99$ifdk4/lo= 2006.173.03:37:08.99$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.03:37:08.99$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.03:37:08.99$ifdk4/patch= 2006.173.03:37:08.99$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.03:37:08.99$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.03:37:08.99$setupk4/!*+20s 2006.173.03:37:15.99#abcon#<5=/14 1.1 2.7 22.68 831006.3\r\n> 2006.173.03:37:16.01#abcon#{5=INTERFACE CLEAR} 2006.173.03:37:16.07#abcon#[5=S1D000X0/0*\r\n] 2006.173.03:37:23.50$setupk4/"tpicd 2006.173.03:37:23.50$setupk4/echo=off 2006.173.03:37:23.50$setupk4/xlog=off 2006.173.03:37:23.50:!2006.173.03:46:41 2006.173.03:38:03.14#trakl#Source acquired 2006.173.03:38:05.14#flagr#flagr/antenna,acquired 2006.173.03:46:41.00:preob 2006.173.03:46:42.14/onsource/TRACKING 2006.173.03:46:42.14:!2006.173.03:46:51 2006.173.03:46:51.00:"tape 2006.173.03:46:51.00:"st=record 2006.173.03:46:51.00:data_valid=on 2006.173.03:46:51.00:midob 2006.173.03:46:51.14/onsource/TRACKING 2006.173.03:46:51.14/wx/22.83,1006.1,84 2006.173.03:46:51.28/cable/+6.5091E-03 2006.173.03:46:52.37/va/01,07,usb,yes,39,42 2006.173.03:46:52.37/va/02,06,usb,yes,39,40 2006.173.03:46:52.37/va/03,05,usb,yes,49,51 2006.173.03:46:52.37/va/04,06,usb,yes,40,42 2006.173.03:46:52.37/va/05,04,usb,yes,31,32 2006.173.03:46:52.37/va/06,03,usb,yes,43,43 2006.173.03:46:52.37/va/07,04,usb,yes,35,37 2006.173.03:46:52.37/va/08,04,usb,yes,30,36 2006.173.03:46:52.60/valo/01,524.99,yes,locked 2006.173.03:46:52.60/valo/02,534.99,yes,locked 2006.173.03:46:52.60/valo/03,564.99,yes,locked 2006.173.03:46:52.60/valo/04,624.99,yes,locked 2006.173.03:46:52.60/valo/05,734.99,yes,locked 2006.173.03:46:52.60/valo/06,814.99,yes,locked 2006.173.03:46:52.60/valo/07,864.99,yes,locked 2006.173.03:46:52.60/valo/08,884.99,yes,locked 2006.173.03:46:53.69/vb/01,04,usb,yes,30,28 2006.173.03:46:53.69/vb/02,04,usb,yes,32,32 2006.173.03:46:53.69/vb/03,04,usb,yes,29,32 2006.173.03:46:53.69/vb/04,04,usb,yes,34,33 2006.173.03:46:53.69/vb/05,04,usb,yes,26,29 2006.173.03:46:53.69/vb/06,04,usb,yes,31,27 2006.173.03:46:53.69/vb/07,04,usb,yes,31,31 2006.173.03:46:53.69/vb/08,04,usb,yes,28,32 2006.173.03:46:53.93/vblo/01,629.99,yes,locked 2006.173.03:46:53.93/vblo/02,634.99,yes,locked 2006.173.03:46:53.93/vblo/03,649.99,yes,locked 2006.173.03:46:53.93/vblo/04,679.99,yes,locked 2006.173.03:46:53.93/vblo/05,709.99,yes,locked 2006.173.03:46:53.93/vblo/06,719.99,yes,locked 2006.173.03:46:53.93/vblo/07,734.99,yes,locked 2006.173.03:46:53.93/vblo/08,744.99,yes,locked 2006.173.03:46:54.08/vabw/8 2006.173.03:46:54.23/vbbw/8 2006.173.03:46:54.32/xfe/off,on,15.5 2006.173.03:46:54.69/ifatt/23,28,28,28 2006.173.03:46:55.08/fmout-gps/S +3.98E-07 2006.173.03:46:55.12:!2006.173.03:54:21 2006.173.03:54:21.00:data_valid=off 2006.173.03:54:21.00:"et 2006.173.03:54:21.00:!+3s 2006.173.03:54:24.02:"tape 2006.173.03:54:24.02:postob 2006.173.03:54:24.22/cable/+6.5092E-03 2006.173.03:54:24.22/wx/22.96,1006.1,81 2006.173.03:54:25.08/fmout-gps/S +3.94E-07 2006.173.03:54:25.08:scan_name=173-0400,jd0606,240 2006.173.03:54:25.08:source=0059+581,010245.76,582411.1,2000.0,ccw 2006.173.03:54:25.14#flagr#flagr/antenna,new-source 2006.173.03:54:26.14:checkk5 2006.173.03:54:26.48/chk_autoobs//k5ts1/ autoobs is running! 2006.173.03:54:26.82/chk_autoobs//k5ts2/ autoobs is running! 2006.173.03:54:27.17/chk_autoobs//k5ts3/ autoobs is running! 2006.173.03:54:27.51/chk_autoobs//k5ts4/ autoobs is running! 2006.173.03:54:27.84/chk_obsdata//k5ts1/T1730346??a.dat file size is correct (nominal:1800MB, actual:1800MB). 2006.173.03:54:28.17/chk_obsdata//k5ts2/T1730346??b.dat file size is correct (nominal:1800MB, actual:1800MB). 2006.173.03:54:28.50/chk_obsdata//k5ts3/T1730346??c.dat file size is correct (nominal:1800MB, actual:1800MB). 2006.173.03:54:28.84/chk_obsdata//k5ts4/T1730346??d.dat file size is correct (nominal:1800MB, actual:1800MB). 2006.173.03:54:29.49/k5log//k5ts1_log_newline 2006.173.03:54:30.14/k5log//k5ts2_log_newline 2006.173.03:54:30.80/k5log//k5ts3_log_newline 2006.173.03:54:31.46/k5log//k5ts4_log_newline 2006.173.03:54:31.48/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.03:54:31.48:setupk4=1 2006.173.03:54:31.48$setupk4/echo=on 2006.173.03:54:31.48$setupk4/pcalon 2006.173.03:54:31.48$pcalon/"no phase cal control is implemented here 2006.173.03:54:31.48$setupk4/"tpicd=stop 2006.173.03:54:31.48$setupk4/"rec=synch_on 2006.173.03:54:31.48$setupk4/"rec_mode=128 2006.173.03:54:31.48$setupk4/!* 2006.173.03:54:31.48$setupk4/recpk4 2006.173.03:54:31.48$recpk4/recpatch= 2006.173.03:54:31.49$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.03:54:31.49$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.03:54:31.49$setupk4/vck44 2006.173.03:54:31.49$vck44/valo=1,524.99 2006.173.03:54:31.49#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.03:54:31.49#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.03:54:31.49#ibcon#ireg 17 cls_cnt 0 2006.173.03:54:31.49#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.03:54:31.49#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.03:54:31.49#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.03:54:31.49#ibcon#enter wrdev, iclass 37, count 0 2006.173.03:54:31.49#ibcon#first serial, iclass 37, count 0 2006.173.03:54:31.49#ibcon#enter sib2, iclass 37, count 0 2006.173.03:54:31.49#ibcon#flushed, iclass 37, count 0 2006.173.03:54:31.49#ibcon#about to write, iclass 37, count 0 2006.173.03:54:31.49#ibcon#wrote, iclass 37, count 0 2006.173.03:54:31.49#ibcon#about to read 3, iclass 37, count 0 2006.173.03:54:31.51#ibcon#read 3, iclass 37, count 0 2006.173.03:54:31.51#ibcon#about to read 4, iclass 37, count 0 2006.173.03:54:31.51#ibcon#read 4, iclass 37, count 0 2006.173.03:54:31.51#ibcon#about to read 5, iclass 37, count 0 2006.173.03:54:31.51#ibcon#read 5, iclass 37, count 0 2006.173.03:54:31.51#ibcon#about to read 6, iclass 37, count 0 2006.173.03:54:31.51#ibcon#read 6, iclass 37, count 0 2006.173.03:54:31.51#ibcon#end of sib2, iclass 37, count 0 2006.173.03:54:31.51#ibcon#*mode == 0, iclass 37, count 0 2006.173.03:54:31.51#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.03:54:31.51#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.03:54:31.51#ibcon#*before write, iclass 37, count 0 2006.173.03:54:31.51#ibcon#enter sib2, iclass 37, count 0 2006.173.03:54:31.51#ibcon#flushed, iclass 37, count 0 2006.173.03:54:31.51#ibcon#about to write, iclass 37, count 0 2006.173.03:54:31.51#ibcon#wrote, iclass 37, count 0 2006.173.03:54:31.51#ibcon#about to read 3, iclass 37, count 0 2006.173.03:54:31.56#ibcon#read 3, iclass 37, count 0 2006.173.03:54:31.56#ibcon#about to read 4, iclass 37, count 0 2006.173.03:54:31.56#ibcon#read 4, iclass 37, count 0 2006.173.03:54:31.56#ibcon#about to read 5, iclass 37, count 0 2006.173.03:54:31.56#ibcon#read 5, iclass 37, count 0 2006.173.03:54:31.56#ibcon#about to read 6, iclass 37, count 0 2006.173.03:54:31.56#ibcon#read 6, iclass 37, count 0 2006.173.03:54:31.56#ibcon#end of sib2, iclass 37, count 0 2006.173.03:54:31.56#ibcon#*after write, iclass 37, count 0 2006.173.03:54:31.56#ibcon#*before return 0, iclass 37, count 0 2006.173.03:54:31.56#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.03:54:31.56#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.03:54:31.56#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.03:54:31.56#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.03:54:31.56$vck44/va=1,7 2006.173.03:54:31.56#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.03:54:31.56#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.03:54:31.56#ibcon#ireg 11 cls_cnt 2 2006.173.03:54:31.56#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.03:54:31.56#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.03:54:31.56#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.03:54:31.56#ibcon#enter wrdev, iclass 39, count 2 2006.173.03:54:31.56#ibcon#first serial, iclass 39, count 2 2006.173.03:54:31.56#ibcon#enter sib2, iclass 39, count 2 2006.173.03:54:31.56#ibcon#flushed, iclass 39, count 2 2006.173.03:54:31.56#ibcon#about to write, iclass 39, count 2 2006.173.03:54:31.56#ibcon#wrote, iclass 39, count 2 2006.173.03:54:31.56#ibcon#about to read 3, iclass 39, count 2 2006.173.03:54:31.58#ibcon#read 3, iclass 39, count 2 2006.173.03:54:31.58#ibcon#about to read 4, iclass 39, count 2 2006.173.03:54:31.58#ibcon#read 4, iclass 39, count 2 2006.173.03:54:31.58#ibcon#about to read 5, iclass 39, count 2 2006.173.03:54:31.58#ibcon#read 5, iclass 39, count 2 2006.173.03:54:31.58#ibcon#about to read 6, iclass 39, count 2 2006.173.03:54:31.58#ibcon#read 6, iclass 39, count 2 2006.173.03:54:31.58#ibcon#end of sib2, iclass 39, count 2 2006.173.03:54:31.58#ibcon#*mode == 0, iclass 39, count 2 2006.173.03:54:31.58#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.03:54:31.58#ibcon#[25=AT01-07\r\n] 2006.173.03:54:31.58#ibcon#*before write, iclass 39, count 2 2006.173.03:54:31.58#ibcon#enter sib2, iclass 39, count 2 2006.173.03:54:31.58#ibcon#flushed, iclass 39, count 2 2006.173.03:54:31.58#ibcon#about to write, iclass 39, count 2 2006.173.03:54:31.58#ibcon#wrote, iclass 39, count 2 2006.173.03:54:31.58#ibcon#about to read 3, iclass 39, count 2 2006.173.03:54:31.61#ibcon#read 3, iclass 39, count 2 2006.173.03:54:31.61#ibcon#about to read 4, iclass 39, count 2 2006.173.03:54:31.61#ibcon#read 4, iclass 39, count 2 2006.173.03:54:31.61#ibcon#about to read 5, iclass 39, count 2 2006.173.03:54:31.61#ibcon#read 5, iclass 39, count 2 2006.173.03:54:31.61#ibcon#about to read 6, iclass 39, count 2 2006.173.03:54:31.61#ibcon#read 6, iclass 39, count 2 2006.173.03:54:31.61#ibcon#end of sib2, iclass 39, count 2 2006.173.03:54:31.61#ibcon#*after write, iclass 39, count 2 2006.173.03:54:31.61#ibcon#*before return 0, iclass 39, count 2 2006.173.03:54:31.61#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.03:54:31.61#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.03:54:31.61#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.03:54:31.61#ibcon#ireg 7 cls_cnt 0 2006.173.03:54:31.61#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.03:54:31.73#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.03:54:31.73#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.03:54:31.73#ibcon#enter wrdev, iclass 39, count 0 2006.173.03:54:31.73#ibcon#first serial, iclass 39, count 0 2006.173.03:54:31.73#ibcon#enter sib2, iclass 39, count 0 2006.173.03:54:31.73#ibcon#flushed, iclass 39, count 0 2006.173.03:54:31.73#ibcon#about to write, iclass 39, count 0 2006.173.03:54:31.73#ibcon#wrote, iclass 39, count 0 2006.173.03:54:31.73#ibcon#about to read 3, iclass 39, count 0 2006.173.03:54:31.75#ibcon#read 3, iclass 39, count 0 2006.173.03:54:31.75#ibcon#about to read 4, iclass 39, count 0 2006.173.03:54:31.75#ibcon#read 4, iclass 39, count 0 2006.173.03:54:31.75#ibcon#about to read 5, iclass 39, count 0 2006.173.03:54:31.75#ibcon#read 5, iclass 39, count 0 2006.173.03:54:31.75#ibcon#about to read 6, iclass 39, count 0 2006.173.03:54:31.75#ibcon#read 6, iclass 39, count 0 2006.173.03:54:31.75#ibcon#end of sib2, iclass 39, count 0 2006.173.03:54:31.75#ibcon#*mode == 0, iclass 39, count 0 2006.173.03:54:31.75#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.03:54:31.75#ibcon#[25=USB\r\n] 2006.173.03:54:31.75#ibcon#*before write, iclass 39, count 0 2006.173.03:54:31.75#ibcon#enter sib2, iclass 39, count 0 2006.173.03:54:31.75#ibcon#flushed, iclass 39, count 0 2006.173.03:54:31.75#ibcon#about to write, iclass 39, count 0 2006.173.03:54:31.75#ibcon#wrote, iclass 39, count 0 2006.173.03:54:31.75#ibcon#about to read 3, iclass 39, count 0 2006.173.03:54:31.78#ibcon#read 3, iclass 39, count 0 2006.173.03:54:31.78#ibcon#about to read 4, iclass 39, count 0 2006.173.03:54:31.78#ibcon#read 4, iclass 39, count 0 2006.173.03:54:31.78#ibcon#about to read 5, iclass 39, count 0 2006.173.03:54:31.78#ibcon#read 5, iclass 39, count 0 2006.173.03:54:31.78#ibcon#about to read 6, iclass 39, count 0 2006.173.03:54:31.78#ibcon#read 6, iclass 39, count 0 2006.173.03:54:31.78#ibcon#end of sib2, iclass 39, count 0 2006.173.03:54:31.78#ibcon#*after write, iclass 39, count 0 2006.173.03:54:31.78#ibcon#*before return 0, iclass 39, count 0 2006.173.03:54:31.78#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.03:54:31.78#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.03:54:31.78#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.03:54:31.78#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.03:54:31.78$vck44/valo=2,534.99 2006.173.03:54:31.78#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.03:54:31.78#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.03:54:31.78#ibcon#ireg 17 cls_cnt 0 2006.173.03:54:31.78#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.03:54:31.78#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.03:54:31.78#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.03:54:31.78#ibcon#enter wrdev, iclass 3, count 0 2006.173.03:54:31.78#ibcon#first serial, iclass 3, count 0 2006.173.03:54:31.78#ibcon#enter sib2, iclass 3, count 0 2006.173.03:54:31.78#ibcon#flushed, iclass 3, count 0 2006.173.03:54:31.78#ibcon#about to write, iclass 3, count 0 2006.173.03:54:31.78#ibcon#wrote, iclass 3, count 0 2006.173.03:54:31.78#ibcon#about to read 3, iclass 3, count 0 2006.173.03:54:31.80#ibcon#read 3, iclass 3, count 0 2006.173.03:54:31.80#ibcon#about to read 4, iclass 3, count 0 2006.173.03:54:31.80#ibcon#read 4, iclass 3, count 0 2006.173.03:54:31.80#ibcon#about to read 5, iclass 3, count 0 2006.173.03:54:31.80#ibcon#read 5, iclass 3, count 0 2006.173.03:54:31.80#ibcon#about to read 6, iclass 3, count 0 2006.173.03:54:31.80#ibcon#read 6, iclass 3, count 0 2006.173.03:54:31.80#ibcon#end of sib2, iclass 3, count 0 2006.173.03:54:31.80#ibcon#*mode == 0, iclass 3, count 0 2006.173.03:54:31.80#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.03:54:31.80#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.03:54:31.80#ibcon#*before write, iclass 3, count 0 2006.173.03:54:31.80#ibcon#enter sib2, iclass 3, count 0 2006.173.03:54:31.80#ibcon#flushed, iclass 3, count 0 2006.173.03:54:31.80#ibcon#about to write, iclass 3, count 0 2006.173.03:54:31.80#ibcon#wrote, iclass 3, count 0 2006.173.03:54:31.80#ibcon#about to read 3, iclass 3, count 0 2006.173.03:54:31.84#ibcon#read 3, iclass 3, count 0 2006.173.03:54:31.84#ibcon#about to read 4, iclass 3, count 0 2006.173.03:54:31.84#ibcon#read 4, iclass 3, count 0 2006.173.03:54:31.84#ibcon#about to read 5, iclass 3, count 0 2006.173.03:54:31.84#ibcon#read 5, iclass 3, count 0 2006.173.03:54:31.84#ibcon#about to read 6, iclass 3, count 0 2006.173.03:54:31.84#ibcon#read 6, iclass 3, count 0 2006.173.03:54:31.84#ibcon#end of sib2, iclass 3, count 0 2006.173.03:54:31.84#ibcon#*after write, iclass 3, count 0 2006.173.03:54:31.84#ibcon#*before return 0, iclass 3, count 0 2006.173.03:54:31.84#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.03:54:31.84#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.03:54:31.84#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.03:54:31.84#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.03:54:31.84$vck44/va=2,6 2006.173.03:54:31.84#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.03:54:31.84#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.03:54:31.84#ibcon#ireg 11 cls_cnt 2 2006.173.03:54:31.84#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.03:54:31.90#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.03:54:31.90#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.03:54:31.90#ibcon#enter wrdev, iclass 5, count 2 2006.173.03:54:31.90#ibcon#first serial, iclass 5, count 2 2006.173.03:54:31.90#ibcon#enter sib2, iclass 5, count 2 2006.173.03:54:31.90#ibcon#flushed, iclass 5, count 2 2006.173.03:54:31.90#ibcon#about to write, iclass 5, count 2 2006.173.03:54:31.90#ibcon#wrote, iclass 5, count 2 2006.173.03:54:31.90#ibcon#about to read 3, iclass 5, count 2 2006.173.03:54:31.92#ibcon#read 3, iclass 5, count 2 2006.173.03:54:31.92#ibcon#about to read 4, iclass 5, count 2 2006.173.03:54:31.92#ibcon#read 4, iclass 5, count 2 2006.173.03:54:31.92#ibcon#about to read 5, iclass 5, count 2 2006.173.03:54:31.92#ibcon#read 5, iclass 5, count 2 2006.173.03:54:31.92#ibcon#about to read 6, iclass 5, count 2 2006.173.03:54:31.92#ibcon#read 6, iclass 5, count 2 2006.173.03:54:31.92#ibcon#end of sib2, iclass 5, count 2 2006.173.03:54:31.92#ibcon#*mode == 0, iclass 5, count 2 2006.173.03:54:31.92#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.03:54:31.92#ibcon#[25=AT02-06\r\n] 2006.173.03:54:31.92#ibcon#*before write, iclass 5, count 2 2006.173.03:54:31.92#ibcon#enter sib2, iclass 5, count 2 2006.173.03:54:31.92#ibcon#flushed, iclass 5, count 2 2006.173.03:54:31.92#ibcon#about to write, iclass 5, count 2 2006.173.03:54:31.92#ibcon#wrote, iclass 5, count 2 2006.173.03:54:31.92#ibcon#about to read 3, iclass 5, count 2 2006.173.03:54:31.95#ibcon#read 3, iclass 5, count 2 2006.173.03:54:31.95#ibcon#about to read 4, iclass 5, count 2 2006.173.03:54:31.95#ibcon#read 4, iclass 5, count 2 2006.173.03:54:31.95#ibcon#about to read 5, iclass 5, count 2 2006.173.03:54:31.95#ibcon#read 5, iclass 5, count 2 2006.173.03:54:31.95#ibcon#about to read 6, iclass 5, count 2 2006.173.03:54:31.95#ibcon#read 6, iclass 5, count 2 2006.173.03:54:31.95#ibcon#end of sib2, iclass 5, count 2 2006.173.03:54:31.95#ibcon#*after write, iclass 5, count 2 2006.173.03:54:31.95#ibcon#*before return 0, iclass 5, count 2 2006.173.03:54:31.95#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.03:54:31.95#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.03:54:31.95#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.03:54:31.95#ibcon#ireg 7 cls_cnt 0 2006.173.03:54:31.95#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.03:54:32.07#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.03:54:32.07#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.03:54:32.07#ibcon#enter wrdev, iclass 5, count 0 2006.173.03:54:32.07#ibcon#first serial, iclass 5, count 0 2006.173.03:54:32.07#ibcon#enter sib2, iclass 5, count 0 2006.173.03:54:32.07#ibcon#flushed, iclass 5, count 0 2006.173.03:54:32.07#ibcon#about to write, iclass 5, count 0 2006.173.03:54:32.07#ibcon#wrote, iclass 5, count 0 2006.173.03:54:32.07#ibcon#about to read 3, iclass 5, count 0 2006.173.03:54:32.09#ibcon#read 3, iclass 5, count 0 2006.173.03:54:32.09#ibcon#about to read 4, iclass 5, count 0 2006.173.03:54:32.09#ibcon#read 4, iclass 5, count 0 2006.173.03:54:32.09#ibcon#about to read 5, iclass 5, count 0 2006.173.03:54:32.09#ibcon#read 5, iclass 5, count 0 2006.173.03:54:32.09#ibcon#about to read 6, iclass 5, count 0 2006.173.03:54:32.09#ibcon#read 6, iclass 5, count 0 2006.173.03:54:32.09#ibcon#end of sib2, iclass 5, count 0 2006.173.03:54:32.09#ibcon#*mode == 0, iclass 5, count 0 2006.173.03:54:32.09#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.03:54:32.09#ibcon#[25=USB\r\n] 2006.173.03:54:32.09#ibcon#*before write, iclass 5, count 0 2006.173.03:54:32.09#ibcon#enter sib2, iclass 5, count 0 2006.173.03:54:32.09#ibcon#flushed, iclass 5, count 0 2006.173.03:54:32.09#ibcon#about to write, iclass 5, count 0 2006.173.03:54:32.09#ibcon#wrote, iclass 5, count 0 2006.173.03:54:32.09#ibcon#about to read 3, iclass 5, count 0 2006.173.03:54:32.12#ibcon#read 3, iclass 5, count 0 2006.173.03:54:32.12#ibcon#about to read 4, iclass 5, count 0 2006.173.03:54:32.12#ibcon#read 4, iclass 5, count 0 2006.173.03:54:32.12#ibcon#about to read 5, iclass 5, count 0 2006.173.03:54:32.12#ibcon#read 5, iclass 5, count 0 2006.173.03:54:32.12#ibcon#about to read 6, iclass 5, count 0 2006.173.03:54:32.12#ibcon#read 6, iclass 5, count 0 2006.173.03:54:32.12#ibcon#end of sib2, iclass 5, count 0 2006.173.03:54:32.12#ibcon#*after write, iclass 5, count 0 2006.173.03:54:32.12#ibcon#*before return 0, iclass 5, count 0 2006.173.03:54:32.12#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.03:54:32.12#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.03:54:32.12#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.03:54:32.12#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.03:54:32.12$vck44/valo=3,564.99 2006.173.03:54:32.12#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.03:54:32.12#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.03:54:32.12#ibcon#ireg 17 cls_cnt 0 2006.173.03:54:32.12#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.03:54:32.12#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.03:54:32.12#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.03:54:32.12#ibcon#enter wrdev, iclass 7, count 0 2006.173.03:54:32.12#ibcon#first serial, iclass 7, count 0 2006.173.03:54:32.12#ibcon#enter sib2, iclass 7, count 0 2006.173.03:54:32.12#ibcon#flushed, iclass 7, count 0 2006.173.03:54:32.12#ibcon#about to write, iclass 7, count 0 2006.173.03:54:32.12#ibcon#wrote, iclass 7, count 0 2006.173.03:54:32.12#ibcon#about to read 3, iclass 7, count 0 2006.173.03:54:32.14#ibcon#read 3, iclass 7, count 0 2006.173.03:54:32.14#ibcon#about to read 4, iclass 7, count 0 2006.173.03:54:32.14#ibcon#read 4, iclass 7, count 0 2006.173.03:54:32.14#ibcon#about to read 5, iclass 7, count 0 2006.173.03:54:32.14#ibcon#read 5, iclass 7, count 0 2006.173.03:54:32.14#ibcon#about to read 6, iclass 7, count 0 2006.173.03:54:32.14#ibcon#read 6, iclass 7, count 0 2006.173.03:54:32.14#ibcon#end of sib2, iclass 7, count 0 2006.173.03:54:32.14#ibcon#*mode == 0, iclass 7, count 0 2006.173.03:54:32.14#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.03:54:32.14#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.03:54:32.14#ibcon#*before write, iclass 7, count 0 2006.173.03:54:32.14#ibcon#enter sib2, iclass 7, count 0 2006.173.03:54:32.14#ibcon#flushed, iclass 7, count 0 2006.173.03:54:32.14#ibcon#about to write, iclass 7, count 0 2006.173.03:54:32.14#ibcon#wrote, iclass 7, count 0 2006.173.03:54:32.14#ibcon#about to read 3, iclass 7, count 0 2006.173.03:54:32.18#ibcon#read 3, iclass 7, count 0 2006.173.03:54:32.18#ibcon#about to read 4, iclass 7, count 0 2006.173.03:54:32.18#ibcon#read 4, iclass 7, count 0 2006.173.03:54:32.18#ibcon#about to read 5, iclass 7, count 0 2006.173.03:54:32.18#ibcon#read 5, iclass 7, count 0 2006.173.03:54:32.18#ibcon#about to read 6, iclass 7, count 0 2006.173.03:54:32.18#ibcon#read 6, iclass 7, count 0 2006.173.03:54:32.18#ibcon#end of sib2, iclass 7, count 0 2006.173.03:54:32.18#ibcon#*after write, iclass 7, count 0 2006.173.03:54:32.18#ibcon#*before return 0, iclass 7, count 0 2006.173.03:54:32.18#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.03:54:32.18#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.03:54:32.18#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.03:54:32.18#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.03:54:32.18$vck44/va=3,5 2006.173.03:54:32.18#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.03:54:32.18#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.03:54:32.18#ibcon#ireg 11 cls_cnt 2 2006.173.03:54:32.18#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.03:54:32.24#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.03:54:32.24#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.03:54:32.24#ibcon#enter wrdev, iclass 11, count 2 2006.173.03:54:32.24#ibcon#first serial, iclass 11, count 2 2006.173.03:54:32.24#ibcon#enter sib2, iclass 11, count 2 2006.173.03:54:32.24#ibcon#flushed, iclass 11, count 2 2006.173.03:54:32.24#ibcon#about to write, iclass 11, count 2 2006.173.03:54:32.24#ibcon#wrote, iclass 11, count 2 2006.173.03:54:32.24#ibcon#about to read 3, iclass 11, count 2 2006.173.03:54:32.26#ibcon#read 3, iclass 11, count 2 2006.173.03:54:32.26#ibcon#about to read 4, iclass 11, count 2 2006.173.03:54:32.26#ibcon#read 4, iclass 11, count 2 2006.173.03:54:32.26#ibcon#about to read 5, iclass 11, count 2 2006.173.03:54:32.26#ibcon#read 5, iclass 11, count 2 2006.173.03:54:32.26#ibcon#about to read 6, iclass 11, count 2 2006.173.03:54:32.26#ibcon#read 6, iclass 11, count 2 2006.173.03:54:32.26#ibcon#end of sib2, iclass 11, count 2 2006.173.03:54:32.26#ibcon#*mode == 0, iclass 11, count 2 2006.173.03:54:32.26#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.03:54:32.26#ibcon#[25=AT03-05\r\n] 2006.173.03:54:32.26#ibcon#*before write, iclass 11, count 2 2006.173.03:54:32.26#ibcon#enter sib2, iclass 11, count 2 2006.173.03:54:32.26#ibcon#flushed, iclass 11, count 2 2006.173.03:54:32.26#ibcon#about to write, iclass 11, count 2 2006.173.03:54:32.26#ibcon#wrote, iclass 11, count 2 2006.173.03:54:32.26#ibcon#about to read 3, iclass 11, count 2 2006.173.03:54:32.29#ibcon#read 3, iclass 11, count 2 2006.173.03:54:32.29#ibcon#about to read 4, iclass 11, count 2 2006.173.03:54:32.29#ibcon#read 4, iclass 11, count 2 2006.173.03:54:32.29#ibcon#about to read 5, iclass 11, count 2 2006.173.03:54:32.29#ibcon#read 5, iclass 11, count 2 2006.173.03:54:32.29#ibcon#about to read 6, iclass 11, count 2 2006.173.03:54:32.29#ibcon#read 6, iclass 11, count 2 2006.173.03:54:32.29#ibcon#end of sib2, iclass 11, count 2 2006.173.03:54:32.29#ibcon#*after write, iclass 11, count 2 2006.173.03:54:32.29#ibcon#*before return 0, iclass 11, count 2 2006.173.03:54:32.29#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.03:54:32.29#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.03:54:32.29#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.03:54:32.29#ibcon#ireg 7 cls_cnt 0 2006.173.03:54:32.29#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.03:54:32.41#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.03:54:32.41#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.03:54:32.41#ibcon#enter wrdev, iclass 11, count 0 2006.173.03:54:32.41#ibcon#first serial, iclass 11, count 0 2006.173.03:54:32.41#ibcon#enter sib2, iclass 11, count 0 2006.173.03:54:32.41#ibcon#flushed, iclass 11, count 0 2006.173.03:54:32.41#ibcon#about to write, iclass 11, count 0 2006.173.03:54:32.41#ibcon#wrote, iclass 11, count 0 2006.173.03:54:32.41#ibcon#about to read 3, iclass 11, count 0 2006.173.03:54:32.43#ibcon#read 3, iclass 11, count 0 2006.173.03:54:32.43#ibcon#about to read 4, iclass 11, count 0 2006.173.03:54:32.43#ibcon#read 4, iclass 11, count 0 2006.173.03:54:32.43#ibcon#about to read 5, iclass 11, count 0 2006.173.03:54:32.43#ibcon#read 5, iclass 11, count 0 2006.173.03:54:32.43#ibcon#about to read 6, iclass 11, count 0 2006.173.03:54:32.43#ibcon#read 6, iclass 11, count 0 2006.173.03:54:32.43#ibcon#end of sib2, iclass 11, count 0 2006.173.03:54:32.43#ibcon#*mode == 0, iclass 11, count 0 2006.173.03:54:32.43#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.03:54:32.43#ibcon#[25=USB\r\n] 2006.173.03:54:32.43#ibcon#*before write, iclass 11, count 0 2006.173.03:54:32.43#ibcon#enter sib2, iclass 11, count 0 2006.173.03:54:32.43#ibcon#flushed, iclass 11, count 0 2006.173.03:54:32.43#ibcon#about to write, iclass 11, count 0 2006.173.03:54:32.43#ibcon#wrote, iclass 11, count 0 2006.173.03:54:32.43#ibcon#about to read 3, iclass 11, count 0 2006.173.03:54:32.46#ibcon#read 3, iclass 11, count 0 2006.173.03:54:32.46#ibcon#about to read 4, iclass 11, count 0 2006.173.03:54:32.46#ibcon#read 4, iclass 11, count 0 2006.173.03:54:32.46#ibcon#about to read 5, iclass 11, count 0 2006.173.03:54:32.46#ibcon#read 5, iclass 11, count 0 2006.173.03:54:32.46#ibcon#about to read 6, iclass 11, count 0 2006.173.03:54:32.46#ibcon#read 6, iclass 11, count 0 2006.173.03:54:32.46#ibcon#end of sib2, iclass 11, count 0 2006.173.03:54:32.46#ibcon#*after write, iclass 11, count 0 2006.173.03:54:32.46#ibcon#*before return 0, iclass 11, count 0 2006.173.03:54:32.46#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.03:54:32.46#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.03:54:32.46#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.03:54:32.46#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.03:54:32.46$vck44/valo=4,624.99 2006.173.03:54:32.46#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.03:54:32.46#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.03:54:32.46#ibcon#ireg 17 cls_cnt 0 2006.173.03:54:32.46#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.03:54:32.46#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.03:54:32.46#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.03:54:32.46#ibcon#enter wrdev, iclass 13, count 0 2006.173.03:54:32.46#ibcon#first serial, iclass 13, count 0 2006.173.03:54:32.46#ibcon#enter sib2, iclass 13, count 0 2006.173.03:54:32.46#ibcon#flushed, iclass 13, count 0 2006.173.03:54:32.46#ibcon#about to write, iclass 13, count 0 2006.173.03:54:32.46#ibcon#wrote, iclass 13, count 0 2006.173.03:54:32.46#ibcon#about to read 3, iclass 13, count 0 2006.173.03:54:32.48#ibcon#read 3, iclass 13, count 0 2006.173.03:54:32.48#ibcon#about to read 4, iclass 13, count 0 2006.173.03:54:32.48#ibcon#read 4, iclass 13, count 0 2006.173.03:54:32.48#ibcon#about to read 5, iclass 13, count 0 2006.173.03:54:32.48#ibcon#read 5, iclass 13, count 0 2006.173.03:54:32.48#ibcon#about to read 6, iclass 13, count 0 2006.173.03:54:32.48#ibcon#read 6, iclass 13, count 0 2006.173.03:54:32.48#ibcon#end of sib2, iclass 13, count 0 2006.173.03:54:32.48#ibcon#*mode == 0, iclass 13, count 0 2006.173.03:54:32.48#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.03:54:32.48#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.03:54:32.48#ibcon#*before write, iclass 13, count 0 2006.173.03:54:32.48#ibcon#enter sib2, iclass 13, count 0 2006.173.03:54:32.48#ibcon#flushed, iclass 13, count 0 2006.173.03:54:32.48#ibcon#about to write, iclass 13, count 0 2006.173.03:54:32.48#ibcon#wrote, iclass 13, count 0 2006.173.03:54:32.48#ibcon#about to read 3, iclass 13, count 0 2006.173.03:54:32.52#ibcon#read 3, iclass 13, count 0 2006.173.03:54:32.52#ibcon#about to read 4, iclass 13, count 0 2006.173.03:54:32.52#ibcon#read 4, iclass 13, count 0 2006.173.03:54:32.52#ibcon#about to read 5, iclass 13, count 0 2006.173.03:54:32.52#ibcon#read 5, iclass 13, count 0 2006.173.03:54:32.52#ibcon#about to read 6, iclass 13, count 0 2006.173.03:54:32.52#ibcon#read 6, iclass 13, count 0 2006.173.03:54:32.52#ibcon#end of sib2, iclass 13, count 0 2006.173.03:54:32.52#ibcon#*after write, iclass 13, count 0 2006.173.03:54:32.52#ibcon#*before return 0, iclass 13, count 0 2006.173.03:54:32.52#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.03:54:32.52#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.03:54:32.52#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.03:54:32.52#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.03:54:32.52$vck44/va=4,6 2006.173.03:54:32.52#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.03:54:32.52#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.03:54:32.52#ibcon#ireg 11 cls_cnt 2 2006.173.03:54:32.52#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.03:54:32.58#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.03:54:32.58#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.03:54:32.58#ibcon#enter wrdev, iclass 15, count 2 2006.173.03:54:32.58#ibcon#first serial, iclass 15, count 2 2006.173.03:54:32.58#ibcon#enter sib2, iclass 15, count 2 2006.173.03:54:32.58#ibcon#flushed, iclass 15, count 2 2006.173.03:54:32.58#ibcon#about to write, iclass 15, count 2 2006.173.03:54:32.58#ibcon#wrote, iclass 15, count 2 2006.173.03:54:32.58#ibcon#about to read 3, iclass 15, count 2 2006.173.03:54:32.60#ibcon#read 3, iclass 15, count 2 2006.173.03:54:32.60#ibcon#about to read 4, iclass 15, count 2 2006.173.03:54:32.60#ibcon#read 4, iclass 15, count 2 2006.173.03:54:32.60#ibcon#about to read 5, iclass 15, count 2 2006.173.03:54:32.60#ibcon#read 5, iclass 15, count 2 2006.173.03:54:32.60#ibcon#about to read 6, iclass 15, count 2 2006.173.03:54:32.60#ibcon#read 6, iclass 15, count 2 2006.173.03:54:32.60#ibcon#end of sib2, iclass 15, count 2 2006.173.03:54:32.60#ibcon#*mode == 0, iclass 15, count 2 2006.173.03:54:32.60#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.03:54:32.60#ibcon#[25=AT04-06\r\n] 2006.173.03:54:32.60#ibcon#*before write, iclass 15, count 2 2006.173.03:54:32.60#ibcon#enter sib2, iclass 15, count 2 2006.173.03:54:32.60#ibcon#flushed, iclass 15, count 2 2006.173.03:54:32.60#ibcon#about to write, iclass 15, count 2 2006.173.03:54:32.60#ibcon#wrote, iclass 15, count 2 2006.173.03:54:32.60#ibcon#about to read 3, iclass 15, count 2 2006.173.03:54:32.63#ibcon#read 3, iclass 15, count 2 2006.173.03:54:32.63#ibcon#about to read 4, iclass 15, count 2 2006.173.03:54:32.63#ibcon#read 4, iclass 15, count 2 2006.173.03:54:32.63#ibcon#about to read 5, iclass 15, count 2 2006.173.03:54:32.63#ibcon#read 5, iclass 15, count 2 2006.173.03:54:32.63#ibcon#about to read 6, iclass 15, count 2 2006.173.03:54:32.63#ibcon#read 6, iclass 15, count 2 2006.173.03:54:32.63#ibcon#end of sib2, iclass 15, count 2 2006.173.03:54:32.63#ibcon#*after write, iclass 15, count 2 2006.173.03:54:32.63#ibcon#*before return 0, iclass 15, count 2 2006.173.03:54:32.63#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.03:54:32.63#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.03:54:32.63#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.03:54:32.63#ibcon#ireg 7 cls_cnt 0 2006.173.03:54:32.63#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.03:54:32.75#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.03:54:32.75#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.03:54:32.75#ibcon#enter wrdev, iclass 15, count 0 2006.173.03:54:32.75#ibcon#first serial, iclass 15, count 0 2006.173.03:54:32.75#ibcon#enter sib2, iclass 15, count 0 2006.173.03:54:32.75#ibcon#flushed, iclass 15, count 0 2006.173.03:54:32.75#ibcon#about to write, iclass 15, count 0 2006.173.03:54:32.75#ibcon#wrote, iclass 15, count 0 2006.173.03:54:32.75#ibcon#about to read 3, iclass 15, count 0 2006.173.03:54:32.77#ibcon#read 3, iclass 15, count 0 2006.173.03:54:32.77#ibcon#about to read 4, iclass 15, count 0 2006.173.03:54:32.77#ibcon#read 4, iclass 15, count 0 2006.173.03:54:32.77#ibcon#about to read 5, iclass 15, count 0 2006.173.03:54:32.77#ibcon#read 5, iclass 15, count 0 2006.173.03:54:32.77#ibcon#about to read 6, iclass 15, count 0 2006.173.03:54:32.77#ibcon#read 6, iclass 15, count 0 2006.173.03:54:32.77#ibcon#end of sib2, iclass 15, count 0 2006.173.03:54:32.77#ibcon#*mode == 0, iclass 15, count 0 2006.173.03:54:32.77#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.03:54:32.77#ibcon#[25=USB\r\n] 2006.173.03:54:32.77#ibcon#*before write, iclass 15, count 0 2006.173.03:54:32.77#ibcon#enter sib2, iclass 15, count 0 2006.173.03:54:32.77#ibcon#flushed, iclass 15, count 0 2006.173.03:54:32.77#ibcon#about to write, iclass 15, count 0 2006.173.03:54:32.77#ibcon#wrote, iclass 15, count 0 2006.173.03:54:32.77#ibcon#about to read 3, iclass 15, count 0 2006.173.03:54:32.80#ibcon#read 3, iclass 15, count 0 2006.173.03:54:32.80#ibcon#about to read 4, iclass 15, count 0 2006.173.03:54:32.80#ibcon#read 4, iclass 15, count 0 2006.173.03:54:32.80#ibcon#about to read 5, iclass 15, count 0 2006.173.03:54:32.80#ibcon#read 5, iclass 15, count 0 2006.173.03:54:32.80#ibcon#about to read 6, iclass 15, count 0 2006.173.03:54:32.80#ibcon#read 6, iclass 15, count 0 2006.173.03:54:32.80#ibcon#end of sib2, iclass 15, count 0 2006.173.03:54:32.80#ibcon#*after write, iclass 15, count 0 2006.173.03:54:32.80#ibcon#*before return 0, iclass 15, count 0 2006.173.03:54:32.80#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.03:54:32.80#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.03:54:32.80#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.03:54:32.80#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.03:54:32.80$vck44/valo=5,734.99 2006.173.03:54:32.80#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.03:54:32.80#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.03:54:32.80#ibcon#ireg 17 cls_cnt 0 2006.173.03:54:32.80#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.03:54:32.80#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.03:54:32.80#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.03:54:32.80#ibcon#enter wrdev, iclass 17, count 0 2006.173.03:54:32.80#ibcon#first serial, iclass 17, count 0 2006.173.03:54:32.80#ibcon#enter sib2, iclass 17, count 0 2006.173.03:54:32.80#ibcon#flushed, iclass 17, count 0 2006.173.03:54:32.80#ibcon#about to write, iclass 17, count 0 2006.173.03:54:32.80#ibcon#wrote, iclass 17, count 0 2006.173.03:54:32.80#ibcon#about to read 3, iclass 17, count 0 2006.173.03:54:32.82#ibcon#read 3, iclass 17, count 0 2006.173.03:54:32.82#ibcon#about to read 4, iclass 17, count 0 2006.173.03:54:32.82#ibcon#read 4, iclass 17, count 0 2006.173.03:54:32.82#ibcon#about to read 5, iclass 17, count 0 2006.173.03:54:32.82#ibcon#read 5, iclass 17, count 0 2006.173.03:54:32.82#ibcon#about to read 6, iclass 17, count 0 2006.173.03:54:32.82#ibcon#read 6, iclass 17, count 0 2006.173.03:54:32.82#ibcon#end of sib2, iclass 17, count 0 2006.173.03:54:32.82#ibcon#*mode == 0, iclass 17, count 0 2006.173.03:54:32.82#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.03:54:32.82#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.03:54:32.82#ibcon#*before write, iclass 17, count 0 2006.173.03:54:32.82#ibcon#enter sib2, iclass 17, count 0 2006.173.03:54:32.82#ibcon#flushed, iclass 17, count 0 2006.173.03:54:32.82#ibcon#about to write, iclass 17, count 0 2006.173.03:54:32.82#ibcon#wrote, iclass 17, count 0 2006.173.03:54:32.82#ibcon#about to read 3, iclass 17, count 0 2006.173.03:54:32.86#ibcon#read 3, iclass 17, count 0 2006.173.03:54:32.86#ibcon#about to read 4, iclass 17, count 0 2006.173.03:54:32.86#ibcon#read 4, iclass 17, count 0 2006.173.03:54:32.86#ibcon#about to read 5, iclass 17, count 0 2006.173.03:54:32.86#ibcon#read 5, iclass 17, count 0 2006.173.03:54:32.86#ibcon#about to read 6, iclass 17, count 0 2006.173.03:54:32.86#ibcon#read 6, iclass 17, count 0 2006.173.03:54:32.86#ibcon#end of sib2, iclass 17, count 0 2006.173.03:54:32.86#ibcon#*after write, iclass 17, count 0 2006.173.03:54:32.86#ibcon#*before return 0, iclass 17, count 0 2006.173.03:54:32.86#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.03:54:32.86#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.03:54:32.86#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.03:54:32.86#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.03:54:32.86$vck44/va=5,4 2006.173.03:54:32.86#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.03:54:32.86#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.03:54:32.86#ibcon#ireg 11 cls_cnt 2 2006.173.03:54:32.86#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.03:54:32.92#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.03:54:32.92#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.03:54:32.92#ibcon#enter wrdev, iclass 19, count 2 2006.173.03:54:32.92#ibcon#first serial, iclass 19, count 2 2006.173.03:54:32.92#ibcon#enter sib2, iclass 19, count 2 2006.173.03:54:32.92#ibcon#flushed, iclass 19, count 2 2006.173.03:54:32.92#ibcon#about to write, iclass 19, count 2 2006.173.03:54:32.92#ibcon#wrote, iclass 19, count 2 2006.173.03:54:32.92#ibcon#about to read 3, iclass 19, count 2 2006.173.03:54:32.94#ibcon#read 3, iclass 19, count 2 2006.173.03:54:32.94#ibcon#about to read 4, iclass 19, count 2 2006.173.03:54:32.94#ibcon#read 4, iclass 19, count 2 2006.173.03:54:32.94#ibcon#about to read 5, iclass 19, count 2 2006.173.03:54:32.94#ibcon#read 5, iclass 19, count 2 2006.173.03:54:32.94#ibcon#about to read 6, iclass 19, count 2 2006.173.03:54:32.94#ibcon#read 6, iclass 19, count 2 2006.173.03:54:32.94#ibcon#end of sib2, iclass 19, count 2 2006.173.03:54:32.94#ibcon#*mode == 0, iclass 19, count 2 2006.173.03:54:32.94#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.03:54:32.94#ibcon#[25=AT05-04\r\n] 2006.173.03:54:32.94#ibcon#*before write, iclass 19, count 2 2006.173.03:54:32.94#ibcon#enter sib2, iclass 19, count 2 2006.173.03:54:32.94#ibcon#flushed, iclass 19, count 2 2006.173.03:54:32.94#ibcon#about to write, iclass 19, count 2 2006.173.03:54:32.94#ibcon#wrote, iclass 19, count 2 2006.173.03:54:32.94#ibcon#about to read 3, iclass 19, count 2 2006.173.03:54:32.97#ibcon#read 3, iclass 19, count 2 2006.173.03:54:32.97#ibcon#about to read 4, iclass 19, count 2 2006.173.03:54:32.97#ibcon#read 4, iclass 19, count 2 2006.173.03:54:32.97#ibcon#about to read 5, iclass 19, count 2 2006.173.03:54:32.97#ibcon#read 5, iclass 19, count 2 2006.173.03:54:32.97#ibcon#about to read 6, iclass 19, count 2 2006.173.03:54:32.97#ibcon#read 6, iclass 19, count 2 2006.173.03:54:32.97#ibcon#end of sib2, iclass 19, count 2 2006.173.03:54:32.97#ibcon#*after write, iclass 19, count 2 2006.173.03:54:32.97#ibcon#*before return 0, iclass 19, count 2 2006.173.03:54:32.97#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.03:54:32.97#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.03:54:32.97#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.03:54:32.97#ibcon#ireg 7 cls_cnt 0 2006.173.03:54:32.97#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.03:54:33.09#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.03:54:33.09#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.03:54:33.09#ibcon#enter wrdev, iclass 19, count 0 2006.173.03:54:33.09#ibcon#first serial, iclass 19, count 0 2006.173.03:54:33.09#ibcon#enter sib2, iclass 19, count 0 2006.173.03:54:33.09#ibcon#flushed, iclass 19, count 0 2006.173.03:54:33.09#ibcon#about to write, iclass 19, count 0 2006.173.03:54:33.09#ibcon#wrote, iclass 19, count 0 2006.173.03:54:33.09#ibcon#about to read 3, iclass 19, count 0 2006.173.03:54:33.11#ibcon#read 3, iclass 19, count 0 2006.173.03:54:33.11#ibcon#about to read 4, iclass 19, count 0 2006.173.03:54:33.11#ibcon#read 4, iclass 19, count 0 2006.173.03:54:33.11#ibcon#about to read 5, iclass 19, count 0 2006.173.03:54:33.11#ibcon#read 5, iclass 19, count 0 2006.173.03:54:33.11#ibcon#about to read 6, iclass 19, count 0 2006.173.03:54:33.11#ibcon#read 6, iclass 19, count 0 2006.173.03:54:33.11#ibcon#end of sib2, iclass 19, count 0 2006.173.03:54:33.11#ibcon#*mode == 0, iclass 19, count 0 2006.173.03:54:33.11#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.03:54:33.11#ibcon#[25=USB\r\n] 2006.173.03:54:33.11#ibcon#*before write, iclass 19, count 0 2006.173.03:54:33.11#ibcon#enter sib2, iclass 19, count 0 2006.173.03:54:33.11#ibcon#flushed, iclass 19, count 0 2006.173.03:54:33.11#ibcon#about to write, iclass 19, count 0 2006.173.03:54:33.11#ibcon#wrote, iclass 19, count 0 2006.173.03:54:33.11#ibcon#about to read 3, iclass 19, count 0 2006.173.03:54:33.14#ibcon#read 3, iclass 19, count 0 2006.173.03:54:33.14#ibcon#about to read 4, iclass 19, count 0 2006.173.03:54:33.14#ibcon#read 4, iclass 19, count 0 2006.173.03:54:33.14#ibcon#about to read 5, iclass 19, count 0 2006.173.03:54:33.14#ibcon#read 5, iclass 19, count 0 2006.173.03:54:33.14#ibcon#about to read 6, iclass 19, count 0 2006.173.03:54:33.14#ibcon#read 6, iclass 19, count 0 2006.173.03:54:33.14#ibcon#end of sib2, iclass 19, count 0 2006.173.03:54:33.14#ibcon#*after write, iclass 19, count 0 2006.173.03:54:33.14#ibcon#*before return 0, iclass 19, count 0 2006.173.03:54:33.14#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.03:54:33.14#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.03:54:33.14#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.03:54:33.14#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.03:54:33.14$vck44/valo=6,814.99 2006.173.03:54:33.14#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.03:54:33.14#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.03:54:33.14#ibcon#ireg 17 cls_cnt 0 2006.173.03:54:33.14#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.03:54:33.14#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.03:54:33.14#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.03:54:33.14#ibcon#enter wrdev, iclass 21, count 0 2006.173.03:54:33.14#ibcon#first serial, iclass 21, count 0 2006.173.03:54:33.14#ibcon#enter sib2, iclass 21, count 0 2006.173.03:54:33.14#ibcon#flushed, iclass 21, count 0 2006.173.03:54:33.14#ibcon#about to write, iclass 21, count 0 2006.173.03:54:33.14#ibcon#wrote, iclass 21, count 0 2006.173.03:54:33.14#ibcon#about to read 3, iclass 21, count 0 2006.173.03:54:33.16#ibcon#read 3, iclass 21, count 0 2006.173.03:54:33.16#ibcon#about to read 4, iclass 21, count 0 2006.173.03:54:33.16#ibcon#read 4, iclass 21, count 0 2006.173.03:54:33.16#ibcon#about to read 5, iclass 21, count 0 2006.173.03:54:33.16#ibcon#read 5, iclass 21, count 0 2006.173.03:54:33.16#ibcon#about to read 6, iclass 21, count 0 2006.173.03:54:33.16#ibcon#read 6, iclass 21, count 0 2006.173.03:54:33.16#ibcon#end of sib2, iclass 21, count 0 2006.173.03:54:33.16#ibcon#*mode == 0, iclass 21, count 0 2006.173.03:54:33.16#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.03:54:33.16#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.03:54:33.16#ibcon#*before write, iclass 21, count 0 2006.173.03:54:33.16#ibcon#enter sib2, iclass 21, count 0 2006.173.03:54:33.16#ibcon#flushed, iclass 21, count 0 2006.173.03:54:33.16#ibcon#about to write, iclass 21, count 0 2006.173.03:54:33.16#ibcon#wrote, iclass 21, count 0 2006.173.03:54:33.16#ibcon#about to read 3, iclass 21, count 0 2006.173.03:54:33.20#ibcon#read 3, iclass 21, count 0 2006.173.03:54:33.20#ibcon#about to read 4, iclass 21, count 0 2006.173.03:54:33.20#ibcon#read 4, iclass 21, count 0 2006.173.03:54:33.20#ibcon#about to read 5, iclass 21, count 0 2006.173.03:54:33.20#ibcon#read 5, iclass 21, count 0 2006.173.03:54:33.20#ibcon#about to read 6, iclass 21, count 0 2006.173.03:54:33.20#ibcon#read 6, iclass 21, count 0 2006.173.03:54:33.20#ibcon#end of sib2, iclass 21, count 0 2006.173.03:54:33.20#ibcon#*after write, iclass 21, count 0 2006.173.03:54:33.20#ibcon#*before return 0, iclass 21, count 0 2006.173.03:54:33.20#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.03:54:33.20#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.03:54:33.20#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.03:54:33.20#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.03:54:33.20$vck44/va=6,3 2006.173.03:54:33.20#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.03:54:33.20#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.03:54:33.20#ibcon#ireg 11 cls_cnt 2 2006.173.03:54:33.20#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.03:54:33.26#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.03:54:33.26#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.03:54:33.26#ibcon#enter wrdev, iclass 23, count 2 2006.173.03:54:33.26#ibcon#first serial, iclass 23, count 2 2006.173.03:54:33.26#ibcon#enter sib2, iclass 23, count 2 2006.173.03:54:33.26#ibcon#flushed, iclass 23, count 2 2006.173.03:54:33.26#ibcon#about to write, iclass 23, count 2 2006.173.03:54:33.26#ibcon#wrote, iclass 23, count 2 2006.173.03:54:33.26#ibcon#about to read 3, iclass 23, count 2 2006.173.03:54:33.28#ibcon#read 3, iclass 23, count 2 2006.173.03:54:33.28#ibcon#about to read 4, iclass 23, count 2 2006.173.03:54:33.28#ibcon#read 4, iclass 23, count 2 2006.173.03:54:33.28#ibcon#about to read 5, iclass 23, count 2 2006.173.03:54:33.28#ibcon#read 5, iclass 23, count 2 2006.173.03:54:33.28#ibcon#about to read 6, iclass 23, count 2 2006.173.03:54:33.28#ibcon#read 6, iclass 23, count 2 2006.173.03:54:33.28#ibcon#end of sib2, iclass 23, count 2 2006.173.03:54:33.28#ibcon#*mode == 0, iclass 23, count 2 2006.173.03:54:33.28#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.03:54:33.28#ibcon#[25=AT06-03\r\n] 2006.173.03:54:33.28#ibcon#*before write, iclass 23, count 2 2006.173.03:54:33.28#ibcon#enter sib2, iclass 23, count 2 2006.173.03:54:33.28#ibcon#flushed, iclass 23, count 2 2006.173.03:54:33.28#ibcon#about to write, iclass 23, count 2 2006.173.03:54:33.28#ibcon#wrote, iclass 23, count 2 2006.173.03:54:33.28#ibcon#about to read 3, iclass 23, count 2 2006.173.03:54:33.31#ibcon#read 3, iclass 23, count 2 2006.173.03:54:33.31#ibcon#about to read 4, iclass 23, count 2 2006.173.03:54:33.31#ibcon#read 4, iclass 23, count 2 2006.173.03:54:33.31#ibcon#about to read 5, iclass 23, count 2 2006.173.03:54:33.31#ibcon#read 5, iclass 23, count 2 2006.173.03:54:33.31#ibcon#about to read 6, iclass 23, count 2 2006.173.03:54:33.31#ibcon#read 6, iclass 23, count 2 2006.173.03:54:33.31#ibcon#end of sib2, iclass 23, count 2 2006.173.03:54:33.31#ibcon#*after write, iclass 23, count 2 2006.173.03:54:33.31#ibcon#*before return 0, iclass 23, count 2 2006.173.03:54:33.31#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.03:54:33.31#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.03:54:33.31#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.03:54:33.31#ibcon#ireg 7 cls_cnt 0 2006.173.03:54:33.31#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.03:54:33.43#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.03:54:33.43#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.03:54:33.43#ibcon#enter wrdev, iclass 23, count 0 2006.173.03:54:33.43#ibcon#first serial, iclass 23, count 0 2006.173.03:54:33.43#ibcon#enter sib2, iclass 23, count 0 2006.173.03:54:33.43#ibcon#flushed, iclass 23, count 0 2006.173.03:54:33.43#ibcon#about to write, iclass 23, count 0 2006.173.03:54:33.43#ibcon#wrote, iclass 23, count 0 2006.173.03:54:33.43#ibcon#about to read 3, iclass 23, count 0 2006.173.03:54:33.45#ibcon#read 3, iclass 23, count 0 2006.173.03:54:33.45#ibcon#about to read 4, iclass 23, count 0 2006.173.03:54:33.45#ibcon#read 4, iclass 23, count 0 2006.173.03:54:33.45#ibcon#about to read 5, iclass 23, count 0 2006.173.03:54:33.45#ibcon#read 5, iclass 23, count 0 2006.173.03:54:33.45#ibcon#about to read 6, iclass 23, count 0 2006.173.03:54:33.45#ibcon#read 6, iclass 23, count 0 2006.173.03:54:33.45#ibcon#end of sib2, iclass 23, count 0 2006.173.03:54:33.45#ibcon#*mode == 0, iclass 23, count 0 2006.173.03:54:33.45#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.03:54:33.45#ibcon#[25=USB\r\n] 2006.173.03:54:33.45#ibcon#*before write, iclass 23, count 0 2006.173.03:54:33.45#ibcon#enter sib2, iclass 23, count 0 2006.173.03:54:33.45#ibcon#flushed, iclass 23, count 0 2006.173.03:54:33.45#ibcon#about to write, iclass 23, count 0 2006.173.03:54:33.45#ibcon#wrote, iclass 23, count 0 2006.173.03:54:33.45#ibcon#about to read 3, iclass 23, count 0 2006.173.03:54:33.48#ibcon#read 3, iclass 23, count 0 2006.173.03:54:33.48#ibcon#about to read 4, iclass 23, count 0 2006.173.03:54:33.48#ibcon#read 4, iclass 23, count 0 2006.173.03:54:33.48#ibcon#about to read 5, iclass 23, count 0 2006.173.03:54:33.48#ibcon#read 5, iclass 23, count 0 2006.173.03:54:33.48#ibcon#about to read 6, iclass 23, count 0 2006.173.03:54:33.48#ibcon#read 6, iclass 23, count 0 2006.173.03:54:33.48#ibcon#end of sib2, iclass 23, count 0 2006.173.03:54:33.48#ibcon#*after write, iclass 23, count 0 2006.173.03:54:33.48#ibcon#*before return 0, iclass 23, count 0 2006.173.03:54:33.48#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.03:54:33.48#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.03:54:33.48#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.03:54:33.48#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.03:54:33.48$vck44/valo=7,864.99 2006.173.03:54:33.48#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.03:54:33.48#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.03:54:33.48#ibcon#ireg 17 cls_cnt 0 2006.173.03:54:33.48#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.03:54:33.48#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.03:54:33.48#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.03:54:33.48#ibcon#enter wrdev, iclass 25, count 0 2006.173.03:54:33.48#ibcon#first serial, iclass 25, count 0 2006.173.03:54:33.48#ibcon#enter sib2, iclass 25, count 0 2006.173.03:54:33.48#ibcon#flushed, iclass 25, count 0 2006.173.03:54:33.48#ibcon#about to write, iclass 25, count 0 2006.173.03:54:33.48#ibcon#wrote, iclass 25, count 0 2006.173.03:54:33.48#ibcon#about to read 3, iclass 25, count 0 2006.173.03:54:33.50#ibcon#read 3, iclass 25, count 0 2006.173.03:54:33.50#ibcon#about to read 4, iclass 25, count 0 2006.173.03:54:33.50#ibcon#read 4, iclass 25, count 0 2006.173.03:54:33.50#ibcon#about to read 5, iclass 25, count 0 2006.173.03:54:33.50#ibcon#read 5, iclass 25, count 0 2006.173.03:54:33.50#ibcon#about to read 6, iclass 25, count 0 2006.173.03:54:33.50#ibcon#read 6, iclass 25, count 0 2006.173.03:54:33.50#ibcon#end of sib2, iclass 25, count 0 2006.173.03:54:33.50#ibcon#*mode == 0, iclass 25, count 0 2006.173.03:54:33.50#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.03:54:33.50#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.03:54:33.50#ibcon#*before write, iclass 25, count 0 2006.173.03:54:33.50#ibcon#enter sib2, iclass 25, count 0 2006.173.03:54:33.50#ibcon#flushed, iclass 25, count 0 2006.173.03:54:33.50#ibcon#about to write, iclass 25, count 0 2006.173.03:54:33.50#ibcon#wrote, iclass 25, count 0 2006.173.03:54:33.50#ibcon#about to read 3, iclass 25, count 0 2006.173.03:54:33.54#ibcon#read 3, iclass 25, count 0 2006.173.03:54:33.54#ibcon#about to read 4, iclass 25, count 0 2006.173.03:54:33.54#ibcon#read 4, iclass 25, count 0 2006.173.03:54:33.54#ibcon#about to read 5, iclass 25, count 0 2006.173.03:54:33.54#ibcon#read 5, iclass 25, count 0 2006.173.03:54:33.54#ibcon#about to read 6, iclass 25, count 0 2006.173.03:54:33.54#ibcon#read 6, iclass 25, count 0 2006.173.03:54:33.54#ibcon#end of sib2, iclass 25, count 0 2006.173.03:54:33.54#ibcon#*after write, iclass 25, count 0 2006.173.03:54:33.54#ibcon#*before return 0, iclass 25, count 0 2006.173.03:54:33.54#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.03:54:33.54#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.03:54:33.54#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.03:54:33.54#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.03:54:33.54$vck44/va=7,4 2006.173.03:54:33.54#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.03:54:33.54#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.03:54:33.54#ibcon#ireg 11 cls_cnt 2 2006.173.03:54:33.54#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.03:54:33.60#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.03:54:33.60#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.03:54:33.60#ibcon#enter wrdev, iclass 27, count 2 2006.173.03:54:33.60#ibcon#first serial, iclass 27, count 2 2006.173.03:54:33.60#ibcon#enter sib2, iclass 27, count 2 2006.173.03:54:33.60#ibcon#flushed, iclass 27, count 2 2006.173.03:54:33.60#ibcon#about to write, iclass 27, count 2 2006.173.03:54:33.60#ibcon#wrote, iclass 27, count 2 2006.173.03:54:33.60#ibcon#about to read 3, iclass 27, count 2 2006.173.03:54:33.62#ibcon#read 3, iclass 27, count 2 2006.173.03:54:33.62#ibcon#about to read 4, iclass 27, count 2 2006.173.03:54:33.62#ibcon#read 4, iclass 27, count 2 2006.173.03:54:33.62#ibcon#about to read 5, iclass 27, count 2 2006.173.03:54:33.62#ibcon#read 5, iclass 27, count 2 2006.173.03:54:33.62#ibcon#about to read 6, iclass 27, count 2 2006.173.03:54:33.62#ibcon#read 6, iclass 27, count 2 2006.173.03:54:33.62#ibcon#end of sib2, iclass 27, count 2 2006.173.03:54:33.62#ibcon#*mode == 0, iclass 27, count 2 2006.173.03:54:33.62#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.03:54:33.62#ibcon#[25=AT07-04\r\n] 2006.173.03:54:33.62#ibcon#*before write, iclass 27, count 2 2006.173.03:54:33.62#ibcon#enter sib2, iclass 27, count 2 2006.173.03:54:33.62#ibcon#flushed, iclass 27, count 2 2006.173.03:54:33.62#ibcon#about to write, iclass 27, count 2 2006.173.03:54:33.62#ibcon#wrote, iclass 27, count 2 2006.173.03:54:33.62#ibcon#about to read 3, iclass 27, count 2 2006.173.03:54:33.62#abcon#<5=/14 1.4 2.6 22.97 811006.1\r\n> 2006.173.03:54:33.64#abcon#{5=INTERFACE CLEAR} 2006.173.03:54:33.65#ibcon#read 3, iclass 27, count 2 2006.173.03:54:33.65#ibcon#about to read 4, iclass 27, count 2 2006.173.03:54:33.65#ibcon#read 4, iclass 27, count 2 2006.173.03:54:33.65#ibcon#about to read 5, iclass 27, count 2 2006.173.03:54:33.65#ibcon#read 5, iclass 27, count 2 2006.173.03:54:33.65#ibcon#about to read 6, iclass 27, count 2 2006.173.03:54:33.65#ibcon#read 6, iclass 27, count 2 2006.173.03:54:33.65#ibcon#end of sib2, iclass 27, count 2 2006.173.03:54:33.65#ibcon#*after write, iclass 27, count 2 2006.173.03:54:33.65#ibcon#*before return 0, iclass 27, count 2 2006.173.03:54:33.65#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.03:54:33.65#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.03:54:33.65#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.03:54:33.65#ibcon#ireg 7 cls_cnt 0 2006.173.03:54:33.65#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.03:54:33.70#abcon#[5=S1D000X0/0*\r\n] 2006.173.03:54:33.77#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.03:54:33.77#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.03:54:33.77#ibcon#enter wrdev, iclass 27, count 0 2006.173.03:54:33.77#ibcon#first serial, iclass 27, count 0 2006.173.03:54:33.77#ibcon#enter sib2, iclass 27, count 0 2006.173.03:54:33.77#ibcon#flushed, iclass 27, count 0 2006.173.03:54:33.77#ibcon#about to write, iclass 27, count 0 2006.173.03:54:33.77#ibcon#wrote, iclass 27, count 0 2006.173.03:54:33.77#ibcon#about to read 3, iclass 27, count 0 2006.173.03:54:33.79#ibcon#read 3, iclass 27, count 0 2006.173.03:54:33.79#ibcon#about to read 4, iclass 27, count 0 2006.173.03:54:33.79#ibcon#read 4, iclass 27, count 0 2006.173.03:54:33.79#ibcon#about to read 5, iclass 27, count 0 2006.173.03:54:33.79#ibcon#read 5, iclass 27, count 0 2006.173.03:54:33.79#ibcon#about to read 6, iclass 27, count 0 2006.173.03:54:33.79#ibcon#read 6, iclass 27, count 0 2006.173.03:54:33.79#ibcon#end of sib2, iclass 27, count 0 2006.173.03:54:33.79#ibcon#*mode == 0, iclass 27, count 0 2006.173.03:54:33.79#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.03:54:33.79#ibcon#[25=USB\r\n] 2006.173.03:54:33.79#ibcon#*before write, iclass 27, count 0 2006.173.03:54:33.79#ibcon#enter sib2, iclass 27, count 0 2006.173.03:54:33.79#ibcon#flushed, iclass 27, count 0 2006.173.03:54:33.79#ibcon#about to write, iclass 27, count 0 2006.173.03:54:33.79#ibcon#wrote, iclass 27, count 0 2006.173.03:54:33.79#ibcon#about to read 3, iclass 27, count 0 2006.173.03:54:33.82#ibcon#read 3, iclass 27, count 0 2006.173.03:54:33.82#ibcon#about to read 4, iclass 27, count 0 2006.173.03:54:33.82#ibcon#read 4, iclass 27, count 0 2006.173.03:54:33.82#ibcon#about to read 5, iclass 27, count 0 2006.173.03:54:33.82#ibcon#read 5, iclass 27, count 0 2006.173.03:54:33.82#ibcon#about to read 6, iclass 27, count 0 2006.173.03:54:33.82#ibcon#read 6, iclass 27, count 0 2006.173.03:54:33.82#ibcon#end of sib2, iclass 27, count 0 2006.173.03:54:33.82#ibcon#*after write, iclass 27, count 0 2006.173.03:54:33.82#ibcon#*before return 0, iclass 27, count 0 2006.173.03:54:33.82#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.03:54:33.82#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.03:54:33.82#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.03:54:33.82#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.03:54:33.82$vck44/valo=8,884.99 2006.173.03:54:33.82#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.03:54:33.82#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.03:54:33.82#ibcon#ireg 17 cls_cnt 0 2006.173.03:54:33.82#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.03:54:33.82#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.03:54:33.82#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.03:54:33.82#ibcon#enter wrdev, iclass 33, count 0 2006.173.03:54:33.82#ibcon#first serial, iclass 33, count 0 2006.173.03:54:33.82#ibcon#enter sib2, iclass 33, count 0 2006.173.03:54:33.82#ibcon#flushed, iclass 33, count 0 2006.173.03:54:33.82#ibcon#about to write, iclass 33, count 0 2006.173.03:54:33.82#ibcon#wrote, iclass 33, count 0 2006.173.03:54:33.82#ibcon#about to read 3, iclass 33, count 0 2006.173.03:54:33.84#ibcon#read 3, iclass 33, count 0 2006.173.03:54:33.84#ibcon#about to read 4, iclass 33, count 0 2006.173.03:54:33.84#ibcon#read 4, iclass 33, count 0 2006.173.03:54:33.84#ibcon#about to read 5, iclass 33, count 0 2006.173.03:54:33.84#ibcon#read 5, iclass 33, count 0 2006.173.03:54:33.84#ibcon#about to read 6, iclass 33, count 0 2006.173.03:54:33.84#ibcon#read 6, iclass 33, count 0 2006.173.03:54:33.84#ibcon#end of sib2, iclass 33, count 0 2006.173.03:54:33.84#ibcon#*mode == 0, iclass 33, count 0 2006.173.03:54:33.84#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.03:54:33.84#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.03:54:33.84#ibcon#*before write, iclass 33, count 0 2006.173.03:54:33.84#ibcon#enter sib2, iclass 33, count 0 2006.173.03:54:33.84#ibcon#flushed, iclass 33, count 0 2006.173.03:54:33.84#ibcon#about to write, iclass 33, count 0 2006.173.03:54:33.84#ibcon#wrote, iclass 33, count 0 2006.173.03:54:33.84#ibcon#about to read 3, iclass 33, count 0 2006.173.03:54:33.88#ibcon#read 3, iclass 33, count 0 2006.173.03:54:33.88#ibcon#about to read 4, iclass 33, count 0 2006.173.03:54:33.88#ibcon#read 4, iclass 33, count 0 2006.173.03:54:33.88#ibcon#about to read 5, iclass 33, count 0 2006.173.03:54:33.88#ibcon#read 5, iclass 33, count 0 2006.173.03:54:33.88#ibcon#about to read 6, iclass 33, count 0 2006.173.03:54:33.88#ibcon#read 6, iclass 33, count 0 2006.173.03:54:33.88#ibcon#end of sib2, iclass 33, count 0 2006.173.03:54:33.88#ibcon#*after write, iclass 33, count 0 2006.173.03:54:33.88#ibcon#*before return 0, iclass 33, count 0 2006.173.03:54:33.88#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.03:54:33.88#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.03:54:33.88#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.03:54:33.88#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.03:54:33.88$vck44/va=8,4 2006.173.03:54:33.88#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.03:54:33.88#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.03:54:33.88#ibcon#ireg 11 cls_cnt 2 2006.173.03:54:33.88#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.03:54:33.94#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.03:54:33.94#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.03:54:33.94#ibcon#enter wrdev, iclass 35, count 2 2006.173.03:54:33.94#ibcon#first serial, iclass 35, count 2 2006.173.03:54:33.94#ibcon#enter sib2, iclass 35, count 2 2006.173.03:54:33.94#ibcon#flushed, iclass 35, count 2 2006.173.03:54:33.94#ibcon#about to write, iclass 35, count 2 2006.173.03:54:33.94#ibcon#wrote, iclass 35, count 2 2006.173.03:54:33.94#ibcon#about to read 3, iclass 35, count 2 2006.173.03:54:33.96#ibcon#read 3, iclass 35, count 2 2006.173.03:54:33.96#ibcon#about to read 4, iclass 35, count 2 2006.173.03:54:33.96#ibcon#read 4, iclass 35, count 2 2006.173.03:54:33.96#ibcon#about to read 5, iclass 35, count 2 2006.173.03:54:33.96#ibcon#read 5, iclass 35, count 2 2006.173.03:54:33.96#ibcon#about to read 6, iclass 35, count 2 2006.173.03:54:33.96#ibcon#read 6, iclass 35, count 2 2006.173.03:54:33.96#ibcon#end of sib2, iclass 35, count 2 2006.173.03:54:33.96#ibcon#*mode == 0, iclass 35, count 2 2006.173.03:54:33.96#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.03:54:33.96#ibcon#[25=AT08-04\r\n] 2006.173.03:54:33.96#ibcon#*before write, iclass 35, count 2 2006.173.03:54:33.96#ibcon#enter sib2, iclass 35, count 2 2006.173.03:54:33.96#ibcon#flushed, iclass 35, count 2 2006.173.03:54:33.96#ibcon#about to write, iclass 35, count 2 2006.173.03:54:33.96#ibcon#wrote, iclass 35, count 2 2006.173.03:54:33.96#ibcon#about to read 3, iclass 35, count 2 2006.173.03:54:33.99#ibcon#read 3, iclass 35, count 2 2006.173.03:54:33.99#ibcon#about to read 4, iclass 35, count 2 2006.173.03:54:33.99#ibcon#read 4, iclass 35, count 2 2006.173.03:54:33.99#ibcon#about to read 5, iclass 35, count 2 2006.173.03:54:33.99#ibcon#read 5, iclass 35, count 2 2006.173.03:54:33.99#ibcon#about to read 6, iclass 35, count 2 2006.173.03:54:33.99#ibcon#read 6, iclass 35, count 2 2006.173.03:54:33.99#ibcon#end of sib2, iclass 35, count 2 2006.173.03:54:33.99#ibcon#*after write, iclass 35, count 2 2006.173.03:54:33.99#ibcon#*before return 0, iclass 35, count 2 2006.173.03:54:33.99#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.03:54:33.99#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.03:54:33.99#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.03:54:33.99#ibcon#ireg 7 cls_cnt 0 2006.173.03:54:33.99#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.03:54:34.11#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.03:54:34.11#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.03:54:34.11#ibcon#enter wrdev, iclass 35, count 0 2006.173.03:54:34.11#ibcon#first serial, iclass 35, count 0 2006.173.03:54:34.11#ibcon#enter sib2, iclass 35, count 0 2006.173.03:54:34.11#ibcon#flushed, iclass 35, count 0 2006.173.03:54:34.11#ibcon#about to write, iclass 35, count 0 2006.173.03:54:34.11#ibcon#wrote, iclass 35, count 0 2006.173.03:54:34.11#ibcon#about to read 3, iclass 35, count 0 2006.173.03:54:34.13#ibcon#read 3, iclass 35, count 0 2006.173.03:54:34.13#ibcon#about to read 4, iclass 35, count 0 2006.173.03:54:34.13#ibcon#read 4, iclass 35, count 0 2006.173.03:54:34.13#ibcon#about to read 5, iclass 35, count 0 2006.173.03:54:34.13#ibcon#read 5, iclass 35, count 0 2006.173.03:54:34.13#ibcon#about to read 6, iclass 35, count 0 2006.173.03:54:34.13#ibcon#read 6, iclass 35, count 0 2006.173.03:54:34.13#ibcon#end of sib2, iclass 35, count 0 2006.173.03:54:34.13#ibcon#*mode == 0, iclass 35, count 0 2006.173.03:54:34.13#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.03:54:34.13#ibcon#[25=USB\r\n] 2006.173.03:54:34.13#ibcon#*before write, iclass 35, count 0 2006.173.03:54:34.13#ibcon#enter sib2, iclass 35, count 0 2006.173.03:54:34.13#ibcon#flushed, iclass 35, count 0 2006.173.03:54:34.13#ibcon#about to write, iclass 35, count 0 2006.173.03:54:34.13#ibcon#wrote, iclass 35, count 0 2006.173.03:54:34.13#ibcon#about to read 3, iclass 35, count 0 2006.173.03:54:34.16#ibcon#read 3, iclass 35, count 0 2006.173.03:54:34.16#ibcon#about to read 4, iclass 35, count 0 2006.173.03:54:34.16#ibcon#read 4, iclass 35, count 0 2006.173.03:54:34.16#ibcon#about to read 5, iclass 35, count 0 2006.173.03:54:34.16#ibcon#read 5, iclass 35, count 0 2006.173.03:54:34.16#ibcon#about to read 6, iclass 35, count 0 2006.173.03:54:34.16#ibcon#read 6, iclass 35, count 0 2006.173.03:54:34.16#ibcon#end of sib2, iclass 35, count 0 2006.173.03:54:34.16#ibcon#*after write, iclass 35, count 0 2006.173.03:54:34.16#ibcon#*before return 0, iclass 35, count 0 2006.173.03:54:34.16#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.03:54:34.16#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.03:54:34.16#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.03:54:34.16#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.03:54:34.16$vck44/vblo=1,629.99 2006.173.03:54:34.16#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.03:54:34.16#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.03:54:34.16#ibcon#ireg 17 cls_cnt 0 2006.173.03:54:34.16#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.03:54:34.16#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.03:54:34.16#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.03:54:34.16#ibcon#enter wrdev, iclass 37, count 0 2006.173.03:54:34.16#ibcon#first serial, iclass 37, count 0 2006.173.03:54:34.16#ibcon#enter sib2, iclass 37, count 0 2006.173.03:54:34.16#ibcon#flushed, iclass 37, count 0 2006.173.03:54:34.16#ibcon#about to write, iclass 37, count 0 2006.173.03:54:34.16#ibcon#wrote, iclass 37, count 0 2006.173.03:54:34.16#ibcon#about to read 3, iclass 37, count 0 2006.173.03:54:34.18#ibcon#read 3, iclass 37, count 0 2006.173.03:54:34.18#ibcon#about to read 4, iclass 37, count 0 2006.173.03:54:34.18#ibcon#read 4, iclass 37, count 0 2006.173.03:54:34.18#ibcon#about to read 5, iclass 37, count 0 2006.173.03:54:34.18#ibcon#read 5, iclass 37, count 0 2006.173.03:54:34.18#ibcon#about to read 6, iclass 37, count 0 2006.173.03:54:34.18#ibcon#read 6, iclass 37, count 0 2006.173.03:54:34.18#ibcon#end of sib2, iclass 37, count 0 2006.173.03:54:34.18#ibcon#*mode == 0, iclass 37, count 0 2006.173.03:54:34.18#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.03:54:34.18#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.03:54:34.18#ibcon#*before write, iclass 37, count 0 2006.173.03:54:34.18#ibcon#enter sib2, iclass 37, count 0 2006.173.03:54:34.18#ibcon#flushed, iclass 37, count 0 2006.173.03:54:34.18#ibcon#about to write, iclass 37, count 0 2006.173.03:54:34.18#ibcon#wrote, iclass 37, count 0 2006.173.03:54:34.18#ibcon#about to read 3, iclass 37, count 0 2006.173.03:54:34.22#ibcon#read 3, iclass 37, count 0 2006.173.03:54:34.22#ibcon#about to read 4, iclass 37, count 0 2006.173.03:54:34.22#ibcon#read 4, iclass 37, count 0 2006.173.03:54:34.22#ibcon#about to read 5, iclass 37, count 0 2006.173.03:54:34.22#ibcon#read 5, iclass 37, count 0 2006.173.03:54:34.22#ibcon#about to read 6, iclass 37, count 0 2006.173.03:54:34.22#ibcon#read 6, iclass 37, count 0 2006.173.03:54:34.22#ibcon#end of sib2, iclass 37, count 0 2006.173.03:54:34.22#ibcon#*after write, iclass 37, count 0 2006.173.03:54:34.22#ibcon#*before return 0, iclass 37, count 0 2006.173.03:54:34.22#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.03:54:34.22#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.03:54:34.22#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.03:54:34.22#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.03:54:34.22$vck44/vb=1,4 2006.173.03:54:34.22#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.03:54:34.22#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.03:54:34.22#ibcon#ireg 11 cls_cnt 2 2006.173.03:54:34.22#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.03:54:34.22#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.03:54:34.22#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.03:54:34.22#ibcon#enter wrdev, iclass 39, count 2 2006.173.03:54:34.22#ibcon#first serial, iclass 39, count 2 2006.173.03:54:34.22#ibcon#enter sib2, iclass 39, count 2 2006.173.03:54:34.22#ibcon#flushed, iclass 39, count 2 2006.173.03:54:34.22#ibcon#about to write, iclass 39, count 2 2006.173.03:54:34.22#ibcon#wrote, iclass 39, count 2 2006.173.03:54:34.22#ibcon#about to read 3, iclass 39, count 2 2006.173.03:54:34.24#ibcon#read 3, iclass 39, count 2 2006.173.03:54:34.24#ibcon#about to read 4, iclass 39, count 2 2006.173.03:54:34.24#ibcon#read 4, iclass 39, count 2 2006.173.03:54:34.24#ibcon#about to read 5, iclass 39, count 2 2006.173.03:54:34.24#ibcon#read 5, iclass 39, count 2 2006.173.03:54:34.24#ibcon#about to read 6, iclass 39, count 2 2006.173.03:54:34.24#ibcon#read 6, iclass 39, count 2 2006.173.03:54:34.24#ibcon#end of sib2, iclass 39, count 2 2006.173.03:54:34.24#ibcon#*mode == 0, iclass 39, count 2 2006.173.03:54:34.24#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.03:54:34.24#ibcon#[27=AT01-04\r\n] 2006.173.03:54:34.24#ibcon#*before write, iclass 39, count 2 2006.173.03:54:34.24#ibcon#enter sib2, iclass 39, count 2 2006.173.03:54:34.24#ibcon#flushed, iclass 39, count 2 2006.173.03:54:34.24#ibcon#about to write, iclass 39, count 2 2006.173.03:54:34.24#ibcon#wrote, iclass 39, count 2 2006.173.03:54:34.24#ibcon#about to read 3, iclass 39, count 2 2006.173.03:54:34.27#ibcon#read 3, iclass 39, count 2 2006.173.03:54:34.27#ibcon#about to read 4, iclass 39, count 2 2006.173.03:54:34.27#ibcon#read 4, iclass 39, count 2 2006.173.03:54:34.27#ibcon#about to read 5, iclass 39, count 2 2006.173.03:54:34.27#ibcon#read 5, iclass 39, count 2 2006.173.03:54:34.27#ibcon#about to read 6, iclass 39, count 2 2006.173.03:54:34.27#ibcon#read 6, iclass 39, count 2 2006.173.03:54:34.27#ibcon#end of sib2, iclass 39, count 2 2006.173.03:54:34.27#ibcon#*after write, iclass 39, count 2 2006.173.03:54:34.27#ibcon#*before return 0, iclass 39, count 2 2006.173.03:54:34.27#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.03:54:34.27#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.03:54:34.27#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.03:54:34.27#ibcon#ireg 7 cls_cnt 0 2006.173.03:54:34.27#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.03:54:34.39#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.03:54:34.39#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.03:54:34.39#ibcon#enter wrdev, iclass 39, count 0 2006.173.03:54:34.39#ibcon#first serial, iclass 39, count 0 2006.173.03:54:34.39#ibcon#enter sib2, iclass 39, count 0 2006.173.03:54:34.39#ibcon#flushed, iclass 39, count 0 2006.173.03:54:34.39#ibcon#about to write, iclass 39, count 0 2006.173.03:54:34.39#ibcon#wrote, iclass 39, count 0 2006.173.03:54:34.39#ibcon#about to read 3, iclass 39, count 0 2006.173.03:54:34.41#ibcon#read 3, iclass 39, count 0 2006.173.03:54:34.41#ibcon#about to read 4, iclass 39, count 0 2006.173.03:54:34.41#ibcon#read 4, iclass 39, count 0 2006.173.03:54:34.41#ibcon#about to read 5, iclass 39, count 0 2006.173.03:54:34.41#ibcon#read 5, iclass 39, count 0 2006.173.03:54:34.41#ibcon#about to read 6, iclass 39, count 0 2006.173.03:54:34.41#ibcon#read 6, iclass 39, count 0 2006.173.03:54:34.41#ibcon#end of sib2, iclass 39, count 0 2006.173.03:54:34.41#ibcon#*mode == 0, iclass 39, count 0 2006.173.03:54:34.41#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.03:54:34.41#ibcon#[27=USB\r\n] 2006.173.03:54:34.41#ibcon#*before write, iclass 39, count 0 2006.173.03:54:34.41#ibcon#enter sib2, iclass 39, count 0 2006.173.03:54:34.41#ibcon#flushed, iclass 39, count 0 2006.173.03:54:34.41#ibcon#about to write, iclass 39, count 0 2006.173.03:54:34.41#ibcon#wrote, iclass 39, count 0 2006.173.03:54:34.41#ibcon#about to read 3, iclass 39, count 0 2006.173.03:54:34.44#ibcon#read 3, iclass 39, count 0 2006.173.03:54:34.44#ibcon#about to read 4, iclass 39, count 0 2006.173.03:54:34.44#ibcon#read 4, iclass 39, count 0 2006.173.03:54:34.44#ibcon#about to read 5, iclass 39, count 0 2006.173.03:54:34.44#ibcon#read 5, iclass 39, count 0 2006.173.03:54:34.44#ibcon#about to read 6, iclass 39, count 0 2006.173.03:54:34.44#ibcon#read 6, iclass 39, count 0 2006.173.03:54:34.44#ibcon#end of sib2, iclass 39, count 0 2006.173.03:54:34.44#ibcon#*after write, iclass 39, count 0 2006.173.03:54:34.44#ibcon#*before return 0, iclass 39, count 0 2006.173.03:54:34.44#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.03:54:34.44#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.03:54:34.44#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.03:54:34.44#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.03:54:34.44$vck44/vblo=2,634.99 2006.173.03:54:34.44#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.03:54:34.44#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.03:54:34.44#ibcon#ireg 17 cls_cnt 0 2006.173.03:54:34.44#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.03:54:34.44#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.03:54:34.44#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.03:54:34.44#ibcon#enter wrdev, iclass 3, count 0 2006.173.03:54:34.44#ibcon#first serial, iclass 3, count 0 2006.173.03:54:34.44#ibcon#enter sib2, iclass 3, count 0 2006.173.03:54:34.44#ibcon#flushed, iclass 3, count 0 2006.173.03:54:34.44#ibcon#about to write, iclass 3, count 0 2006.173.03:54:34.44#ibcon#wrote, iclass 3, count 0 2006.173.03:54:34.44#ibcon#about to read 3, iclass 3, count 0 2006.173.03:54:34.46#ibcon#read 3, iclass 3, count 0 2006.173.03:54:34.46#ibcon#about to read 4, iclass 3, count 0 2006.173.03:54:34.46#ibcon#read 4, iclass 3, count 0 2006.173.03:54:34.46#ibcon#about to read 5, iclass 3, count 0 2006.173.03:54:34.46#ibcon#read 5, iclass 3, count 0 2006.173.03:54:34.46#ibcon#about to read 6, iclass 3, count 0 2006.173.03:54:34.46#ibcon#read 6, iclass 3, count 0 2006.173.03:54:34.46#ibcon#end of sib2, iclass 3, count 0 2006.173.03:54:34.46#ibcon#*mode == 0, iclass 3, count 0 2006.173.03:54:34.46#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.03:54:34.46#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.03:54:34.46#ibcon#*before write, iclass 3, count 0 2006.173.03:54:34.46#ibcon#enter sib2, iclass 3, count 0 2006.173.03:54:34.46#ibcon#flushed, iclass 3, count 0 2006.173.03:54:34.46#ibcon#about to write, iclass 3, count 0 2006.173.03:54:34.46#ibcon#wrote, iclass 3, count 0 2006.173.03:54:34.46#ibcon#about to read 3, iclass 3, count 0 2006.173.03:54:34.50#ibcon#read 3, iclass 3, count 0 2006.173.03:54:34.50#ibcon#about to read 4, iclass 3, count 0 2006.173.03:54:34.50#ibcon#read 4, iclass 3, count 0 2006.173.03:54:34.50#ibcon#about to read 5, iclass 3, count 0 2006.173.03:54:34.50#ibcon#read 5, iclass 3, count 0 2006.173.03:54:34.50#ibcon#about to read 6, iclass 3, count 0 2006.173.03:54:34.50#ibcon#read 6, iclass 3, count 0 2006.173.03:54:34.50#ibcon#end of sib2, iclass 3, count 0 2006.173.03:54:34.50#ibcon#*after write, iclass 3, count 0 2006.173.03:54:34.50#ibcon#*before return 0, iclass 3, count 0 2006.173.03:54:34.50#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.03:54:34.50#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.03:54:34.50#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.03:54:34.50#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.03:54:34.50$vck44/vb=2,4 2006.173.03:54:34.50#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.03:54:34.50#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.03:54:34.50#ibcon#ireg 11 cls_cnt 2 2006.173.03:54:34.50#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.03:54:34.56#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.03:54:34.56#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.03:54:34.56#ibcon#enter wrdev, iclass 5, count 2 2006.173.03:54:34.56#ibcon#first serial, iclass 5, count 2 2006.173.03:54:34.56#ibcon#enter sib2, iclass 5, count 2 2006.173.03:54:34.56#ibcon#flushed, iclass 5, count 2 2006.173.03:54:34.56#ibcon#about to write, iclass 5, count 2 2006.173.03:54:34.56#ibcon#wrote, iclass 5, count 2 2006.173.03:54:34.56#ibcon#about to read 3, iclass 5, count 2 2006.173.03:54:34.58#ibcon#read 3, iclass 5, count 2 2006.173.03:54:34.58#ibcon#about to read 4, iclass 5, count 2 2006.173.03:54:34.58#ibcon#read 4, iclass 5, count 2 2006.173.03:54:34.58#ibcon#about to read 5, iclass 5, count 2 2006.173.03:54:34.58#ibcon#read 5, iclass 5, count 2 2006.173.03:54:34.58#ibcon#about to read 6, iclass 5, count 2 2006.173.03:54:34.58#ibcon#read 6, iclass 5, count 2 2006.173.03:54:34.58#ibcon#end of sib2, iclass 5, count 2 2006.173.03:54:34.58#ibcon#*mode == 0, iclass 5, count 2 2006.173.03:54:34.58#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.03:54:34.58#ibcon#[27=AT02-04\r\n] 2006.173.03:54:34.58#ibcon#*before write, iclass 5, count 2 2006.173.03:54:34.58#ibcon#enter sib2, iclass 5, count 2 2006.173.03:54:34.58#ibcon#flushed, iclass 5, count 2 2006.173.03:54:34.58#ibcon#about to write, iclass 5, count 2 2006.173.03:54:34.58#ibcon#wrote, iclass 5, count 2 2006.173.03:54:34.58#ibcon#about to read 3, iclass 5, count 2 2006.173.03:54:34.61#ibcon#read 3, iclass 5, count 2 2006.173.03:54:34.61#ibcon#about to read 4, iclass 5, count 2 2006.173.03:54:34.61#ibcon#read 4, iclass 5, count 2 2006.173.03:54:34.61#ibcon#about to read 5, iclass 5, count 2 2006.173.03:54:34.61#ibcon#read 5, iclass 5, count 2 2006.173.03:54:34.61#ibcon#about to read 6, iclass 5, count 2 2006.173.03:54:34.61#ibcon#read 6, iclass 5, count 2 2006.173.03:54:34.61#ibcon#end of sib2, iclass 5, count 2 2006.173.03:54:34.61#ibcon#*after write, iclass 5, count 2 2006.173.03:54:34.61#ibcon#*before return 0, iclass 5, count 2 2006.173.03:54:34.61#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.03:54:34.61#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.03:54:34.61#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.03:54:34.61#ibcon#ireg 7 cls_cnt 0 2006.173.03:54:34.61#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.03:54:34.73#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.03:54:34.73#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.03:54:34.73#ibcon#enter wrdev, iclass 5, count 0 2006.173.03:54:34.73#ibcon#first serial, iclass 5, count 0 2006.173.03:54:34.73#ibcon#enter sib2, iclass 5, count 0 2006.173.03:54:34.73#ibcon#flushed, iclass 5, count 0 2006.173.03:54:34.73#ibcon#about to write, iclass 5, count 0 2006.173.03:54:34.73#ibcon#wrote, iclass 5, count 0 2006.173.03:54:34.73#ibcon#about to read 3, iclass 5, count 0 2006.173.03:54:34.75#ibcon#read 3, iclass 5, count 0 2006.173.03:54:34.75#ibcon#about to read 4, iclass 5, count 0 2006.173.03:54:34.75#ibcon#read 4, iclass 5, count 0 2006.173.03:54:34.75#ibcon#about to read 5, iclass 5, count 0 2006.173.03:54:34.75#ibcon#read 5, iclass 5, count 0 2006.173.03:54:34.75#ibcon#about to read 6, iclass 5, count 0 2006.173.03:54:34.75#ibcon#read 6, iclass 5, count 0 2006.173.03:54:34.75#ibcon#end of sib2, iclass 5, count 0 2006.173.03:54:34.75#ibcon#*mode == 0, iclass 5, count 0 2006.173.03:54:34.75#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.03:54:34.75#ibcon#[27=USB\r\n] 2006.173.03:54:34.75#ibcon#*before write, iclass 5, count 0 2006.173.03:54:34.75#ibcon#enter sib2, iclass 5, count 0 2006.173.03:54:34.75#ibcon#flushed, iclass 5, count 0 2006.173.03:54:34.75#ibcon#about to write, iclass 5, count 0 2006.173.03:54:34.75#ibcon#wrote, iclass 5, count 0 2006.173.03:54:34.75#ibcon#about to read 3, iclass 5, count 0 2006.173.03:54:34.78#ibcon#read 3, iclass 5, count 0 2006.173.03:54:34.78#ibcon#about to read 4, iclass 5, count 0 2006.173.03:54:34.78#ibcon#read 4, iclass 5, count 0 2006.173.03:54:34.78#ibcon#about to read 5, iclass 5, count 0 2006.173.03:54:34.78#ibcon#read 5, iclass 5, count 0 2006.173.03:54:34.78#ibcon#about to read 6, iclass 5, count 0 2006.173.03:54:34.78#ibcon#read 6, iclass 5, count 0 2006.173.03:54:34.78#ibcon#end of sib2, iclass 5, count 0 2006.173.03:54:34.78#ibcon#*after write, iclass 5, count 0 2006.173.03:54:34.78#ibcon#*before return 0, iclass 5, count 0 2006.173.03:54:34.78#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.03:54:34.78#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.03:54:34.78#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.03:54:34.78#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.03:54:34.78$vck44/vblo=3,649.99 2006.173.03:54:34.78#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.03:54:34.78#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.03:54:34.78#ibcon#ireg 17 cls_cnt 0 2006.173.03:54:34.78#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.03:54:34.78#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.03:54:34.78#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.03:54:34.78#ibcon#enter wrdev, iclass 7, count 0 2006.173.03:54:34.78#ibcon#first serial, iclass 7, count 0 2006.173.03:54:34.78#ibcon#enter sib2, iclass 7, count 0 2006.173.03:54:34.78#ibcon#flushed, iclass 7, count 0 2006.173.03:54:34.78#ibcon#about to write, iclass 7, count 0 2006.173.03:54:34.78#ibcon#wrote, iclass 7, count 0 2006.173.03:54:34.78#ibcon#about to read 3, iclass 7, count 0 2006.173.03:54:34.80#ibcon#read 3, iclass 7, count 0 2006.173.03:54:34.80#ibcon#about to read 4, iclass 7, count 0 2006.173.03:54:34.80#ibcon#read 4, iclass 7, count 0 2006.173.03:54:34.80#ibcon#about to read 5, iclass 7, count 0 2006.173.03:54:34.80#ibcon#read 5, iclass 7, count 0 2006.173.03:54:34.80#ibcon#about to read 6, iclass 7, count 0 2006.173.03:54:34.80#ibcon#read 6, iclass 7, count 0 2006.173.03:54:34.80#ibcon#end of sib2, iclass 7, count 0 2006.173.03:54:34.80#ibcon#*mode == 0, iclass 7, count 0 2006.173.03:54:34.80#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.03:54:34.80#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.03:54:34.80#ibcon#*before write, iclass 7, count 0 2006.173.03:54:34.80#ibcon#enter sib2, iclass 7, count 0 2006.173.03:54:34.80#ibcon#flushed, iclass 7, count 0 2006.173.03:54:34.80#ibcon#about to write, iclass 7, count 0 2006.173.03:54:34.80#ibcon#wrote, iclass 7, count 0 2006.173.03:54:34.80#ibcon#about to read 3, iclass 7, count 0 2006.173.03:54:34.84#ibcon#read 3, iclass 7, count 0 2006.173.03:54:34.84#ibcon#about to read 4, iclass 7, count 0 2006.173.03:54:34.84#ibcon#read 4, iclass 7, count 0 2006.173.03:54:34.84#ibcon#about to read 5, iclass 7, count 0 2006.173.03:54:34.84#ibcon#read 5, iclass 7, count 0 2006.173.03:54:34.84#ibcon#about to read 6, iclass 7, count 0 2006.173.03:54:34.84#ibcon#read 6, iclass 7, count 0 2006.173.03:54:34.84#ibcon#end of sib2, iclass 7, count 0 2006.173.03:54:34.84#ibcon#*after write, iclass 7, count 0 2006.173.03:54:34.84#ibcon#*before return 0, iclass 7, count 0 2006.173.03:54:34.84#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.03:54:34.84#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.03:54:34.84#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.03:54:34.84#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.03:54:34.84$vck44/vb=3,4 2006.173.03:54:34.84#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.03:54:34.84#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.03:54:34.84#ibcon#ireg 11 cls_cnt 2 2006.173.03:54:34.84#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.03:54:34.90#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.03:54:34.90#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.03:54:34.90#ibcon#enter wrdev, iclass 11, count 2 2006.173.03:54:34.90#ibcon#first serial, iclass 11, count 2 2006.173.03:54:34.90#ibcon#enter sib2, iclass 11, count 2 2006.173.03:54:34.90#ibcon#flushed, iclass 11, count 2 2006.173.03:54:34.90#ibcon#about to write, iclass 11, count 2 2006.173.03:54:34.90#ibcon#wrote, iclass 11, count 2 2006.173.03:54:34.90#ibcon#about to read 3, iclass 11, count 2 2006.173.03:54:34.92#ibcon#read 3, iclass 11, count 2 2006.173.03:54:34.92#ibcon#about to read 4, iclass 11, count 2 2006.173.03:54:34.92#ibcon#read 4, iclass 11, count 2 2006.173.03:54:34.92#ibcon#about to read 5, iclass 11, count 2 2006.173.03:54:34.92#ibcon#read 5, iclass 11, count 2 2006.173.03:54:34.92#ibcon#about to read 6, iclass 11, count 2 2006.173.03:54:34.92#ibcon#read 6, iclass 11, count 2 2006.173.03:54:34.92#ibcon#end of sib2, iclass 11, count 2 2006.173.03:54:34.92#ibcon#*mode == 0, iclass 11, count 2 2006.173.03:54:34.92#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.03:54:34.92#ibcon#[27=AT03-04\r\n] 2006.173.03:54:34.92#ibcon#*before write, iclass 11, count 2 2006.173.03:54:34.92#ibcon#enter sib2, iclass 11, count 2 2006.173.03:54:34.92#ibcon#flushed, iclass 11, count 2 2006.173.03:54:34.92#ibcon#about to write, iclass 11, count 2 2006.173.03:54:34.92#ibcon#wrote, iclass 11, count 2 2006.173.03:54:34.92#ibcon#about to read 3, iclass 11, count 2 2006.173.03:54:34.95#ibcon#read 3, iclass 11, count 2 2006.173.03:54:34.95#ibcon#about to read 4, iclass 11, count 2 2006.173.03:54:34.95#ibcon#read 4, iclass 11, count 2 2006.173.03:54:34.95#ibcon#about to read 5, iclass 11, count 2 2006.173.03:54:34.95#ibcon#read 5, iclass 11, count 2 2006.173.03:54:34.95#ibcon#about to read 6, iclass 11, count 2 2006.173.03:54:34.95#ibcon#read 6, iclass 11, count 2 2006.173.03:54:34.95#ibcon#end of sib2, iclass 11, count 2 2006.173.03:54:34.95#ibcon#*after write, iclass 11, count 2 2006.173.03:54:34.95#ibcon#*before return 0, iclass 11, count 2 2006.173.03:54:34.95#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.03:54:34.95#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.03:54:34.95#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.03:54:34.95#ibcon#ireg 7 cls_cnt 0 2006.173.03:54:34.95#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.03:54:35.07#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.03:54:35.07#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.03:54:35.07#ibcon#enter wrdev, iclass 11, count 0 2006.173.03:54:35.07#ibcon#first serial, iclass 11, count 0 2006.173.03:54:35.07#ibcon#enter sib2, iclass 11, count 0 2006.173.03:54:35.07#ibcon#flushed, iclass 11, count 0 2006.173.03:54:35.07#ibcon#about to write, iclass 11, count 0 2006.173.03:54:35.07#ibcon#wrote, iclass 11, count 0 2006.173.03:54:35.07#ibcon#about to read 3, iclass 11, count 0 2006.173.03:54:35.09#ibcon#read 3, iclass 11, count 0 2006.173.03:54:35.09#ibcon#about to read 4, iclass 11, count 0 2006.173.03:54:35.09#ibcon#read 4, iclass 11, count 0 2006.173.03:54:35.09#ibcon#about to read 5, iclass 11, count 0 2006.173.03:54:35.09#ibcon#read 5, iclass 11, count 0 2006.173.03:54:35.09#ibcon#about to read 6, iclass 11, count 0 2006.173.03:54:35.09#ibcon#read 6, iclass 11, count 0 2006.173.03:54:35.09#ibcon#end of sib2, iclass 11, count 0 2006.173.03:54:35.09#ibcon#*mode == 0, iclass 11, count 0 2006.173.03:54:35.09#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.03:54:35.09#ibcon#[27=USB\r\n] 2006.173.03:54:35.09#ibcon#*before write, iclass 11, count 0 2006.173.03:54:35.09#ibcon#enter sib2, iclass 11, count 0 2006.173.03:54:35.09#ibcon#flushed, iclass 11, count 0 2006.173.03:54:35.09#ibcon#about to write, iclass 11, count 0 2006.173.03:54:35.09#ibcon#wrote, iclass 11, count 0 2006.173.03:54:35.09#ibcon#about to read 3, iclass 11, count 0 2006.173.03:54:35.12#ibcon#read 3, iclass 11, count 0 2006.173.03:54:35.12#ibcon#about to read 4, iclass 11, count 0 2006.173.03:54:35.12#ibcon#read 4, iclass 11, count 0 2006.173.03:54:35.12#ibcon#about to read 5, iclass 11, count 0 2006.173.03:54:35.12#ibcon#read 5, iclass 11, count 0 2006.173.03:54:35.12#ibcon#about to read 6, iclass 11, count 0 2006.173.03:54:35.12#ibcon#read 6, iclass 11, count 0 2006.173.03:54:35.12#ibcon#end of sib2, iclass 11, count 0 2006.173.03:54:35.12#ibcon#*after write, iclass 11, count 0 2006.173.03:54:35.12#ibcon#*before return 0, iclass 11, count 0 2006.173.03:54:35.12#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.03:54:35.12#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.03:54:35.12#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.03:54:35.12#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.03:54:35.12$vck44/vblo=4,679.99 2006.173.03:54:35.12#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.03:54:35.12#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.03:54:35.12#ibcon#ireg 17 cls_cnt 0 2006.173.03:54:35.12#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.03:54:35.12#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.03:54:35.12#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.03:54:35.12#ibcon#enter wrdev, iclass 13, count 0 2006.173.03:54:35.12#ibcon#first serial, iclass 13, count 0 2006.173.03:54:35.12#ibcon#enter sib2, iclass 13, count 0 2006.173.03:54:35.12#ibcon#flushed, iclass 13, count 0 2006.173.03:54:35.12#ibcon#about to write, iclass 13, count 0 2006.173.03:54:35.12#ibcon#wrote, iclass 13, count 0 2006.173.03:54:35.12#ibcon#about to read 3, iclass 13, count 0 2006.173.03:54:35.14#ibcon#read 3, iclass 13, count 0 2006.173.03:54:35.14#ibcon#about to read 4, iclass 13, count 0 2006.173.03:54:35.14#ibcon#read 4, iclass 13, count 0 2006.173.03:54:35.14#ibcon#about to read 5, iclass 13, count 0 2006.173.03:54:35.14#ibcon#read 5, iclass 13, count 0 2006.173.03:54:35.14#ibcon#about to read 6, iclass 13, count 0 2006.173.03:54:35.14#ibcon#read 6, iclass 13, count 0 2006.173.03:54:35.14#ibcon#end of sib2, iclass 13, count 0 2006.173.03:54:35.14#ibcon#*mode == 0, iclass 13, count 0 2006.173.03:54:35.14#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.03:54:35.14#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.03:54:35.14#ibcon#*before write, iclass 13, count 0 2006.173.03:54:35.14#ibcon#enter sib2, iclass 13, count 0 2006.173.03:54:35.14#ibcon#flushed, iclass 13, count 0 2006.173.03:54:35.14#ibcon#about to write, iclass 13, count 0 2006.173.03:54:35.14#ibcon#wrote, iclass 13, count 0 2006.173.03:54:35.14#ibcon#about to read 3, iclass 13, count 0 2006.173.03:54:35.18#ibcon#read 3, iclass 13, count 0 2006.173.03:54:35.18#ibcon#about to read 4, iclass 13, count 0 2006.173.03:54:35.18#ibcon#read 4, iclass 13, count 0 2006.173.03:54:35.18#ibcon#about to read 5, iclass 13, count 0 2006.173.03:54:35.18#ibcon#read 5, iclass 13, count 0 2006.173.03:54:35.18#ibcon#about to read 6, iclass 13, count 0 2006.173.03:54:35.18#ibcon#read 6, iclass 13, count 0 2006.173.03:54:35.18#ibcon#end of sib2, iclass 13, count 0 2006.173.03:54:35.18#ibcon#*after write, iclass 13, count 0 2006.173.03:54:35.18#ibcon#*before return 0, iclass 13, count 0 2006.173.03:54:35.18#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.03:54:35.18#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.03:54:35.18#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.03:54:35.18#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.03:54:35.18$vck44/vb=4,4 2006.173.03:54:35.18#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.03:54:35.18#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.03:54:35.18#ibcon#ireg 11 cls_cnt 2 2006.173.03:54:35.18#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.03:54:35.24#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.03:54:35.24#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.03:54:35.24#ibcon#enter wrdev, iclass 15, count 2 2006.173.03:54:35.24#ibcon#first serial, iclass 15, count 2 2006.173.03:54:35.24#ibcon#enter sib2, iclass 15, count 2 2006.173.03:54:35.24#ibcon#flushed, iclass 15, count 2 2006.173.03:54:35.24#ibcon#about to write, iclass 15, count 2 2006.173.03:54:35.24#ibcon#wrote, iclass 15, count 2 2006.173.03:54:35.24#ibcon#about to read 3, iclass 15, count 2 2006.173.03:54:35.26#ibcon#read 3, iclass 15, count 2 2006.173.03:54:35.26#ibcon#about to read 4, iclass 15, count 2 2006.173.03:54:35.26#ibcon#read 4, iclass 15, count 2 2006.173.03:54:35.26#ibcon#about to read 5, iclass 15, count 2 2006.173.03:54:35.26#ibcon#read 5, iclass 15, count 2 2006.173.03:54:35.26#ibcon#about to read 6, iclass 15, count 2 2006.173.03:54:35.26#ibcon#read 6, iclass 15, count 2 2006.173.03:54:35.26#ibcon#end of sib2, iclass 15, count 2 2006.173.03:54:35.26#ibcon#*mode == 0, iclass 15, count 2 2006.173.03:54:35.26#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.03:54:35.26#ibcon#[27=AT04-04\r\n] 2006.173.03:54:35.26#ibcon#*before write, iclass 15, count 2 2006.173.03:54:35.26#ibcon#enter sib2, iclass 15, count 2 2006.173.03:54:35.26#ibcon#flushed, iclass 15, count 2 2006.173.03:54:35.26#ibcon#about to write, iclass 15, count 2 2006.173.03:54:35.26#ibcon#wrote, iclass 15, count 2 2006.173.03:54:35.26#ibcon#about to read 3, iclass 15, count 2 2006.173.03:54:35.29#ibcon#read 3, iclass 15, count 2 2006.173.03:54:35.29#ibcon#about to read 4, iclass 15, count 2 2006.173.03:54:35.29#ibcon#read 4, iclass 15, count 2 2006.173.03:54:35.29#ibcon#about to read 5, iclass 15, count 2 2006.173.03:54:35.29#ibcon#read 5, iclass 15, count 2 2006.173.03:54:35.29#ibcon#about to read 6, iclass 15, count 2 2006.173.03:54:35.29#ibcon#read 6, iclass 15, count 2 2006.173.03:54:35.29#ibcon#end of sib2, iclass 15, count 2 2006.173.03:54:35.29#ibcon#*after write, iclass 15, count 2 2006.173.03:54:35.29#ibcon#*before return 0, iclass 15, count 2 2006.173.03:54:35.29#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.03:54:35.29#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.03:54:35.29#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.03:54:35.29#ibcon#ireg 7 cls_cnt 0 2006.173.03:54:35.29#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.03:54:35.41#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.03:54:35.41#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.03:54:35.41#ibcon#enter wrdev, iclass 15, count 0 2006.173.03:54:35.41#ibcon#first serial, iclass 15, count 0 2006.173.03:54:35.41#ibcon#enter sib2, iclass 15, count 0 2006.173.03:54:35.41#ibcon#flushed, iclass 15, count 0 2006.173.03:54:35.41#ibcon#about to write, iclass 15, count 0 2006.173.03:54:35.41#ibcon#wrote, iclass 15, count 0 2006.173.03:54:35.41#ibcon#about to read 3, iclass 15, count 0 2006.173.03:54:35.43#ibcon#read 3, iclass 15, count 0 2006.173.03:54:35.43#ibcon#about to read 4, iclass 15, count 0 2006.173.03:54:35.43#ibcon#read 4, iclass 15, count 0 2006.173.03:54:35.43#ibcon#about to read 5, iclass 15, count 0 2006.173.03:54:35.43#ibcon#read 5, iclass 15, count 0 2006.173.03:54:35.43#ibcon#about to read 6, iclass 15, count 0 2006.173.03:54:35.43#ibcon#read 6, iclass 15, count 0 2006.173.03:54:35.43#ibcon#end of sib2, iclass 15, count 0 2006.173.03:54:35.43#ibcon#*mode == 0, iclass 15, count 0 2006.173.03:54:35.43#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.03:54:35.43#ibcon#[27=USB\r\n] 2006.173.03:54:35.43#ibcon#*before write, iclass 15, count 0 2006.173.03:54:35.43#ibcon#enter sib2, iclass 15, count 0 2006.173.03:54:35.43#ibcon#flushed, iclass 15, count 0 2006.173.03:54:35.43#ibcon#about to write, iclass 15, count 0 2006.173.03:54:35.43#ibcon#wrote, iclass 15, count 0 2006.173.03:54:35.43#ibcon#about to read 3, iclass 15, count 0 2006.173.03:54:35.46#ibcon#read 3, iclass 15, count 0 2006.173.03:54:35.46#ibcon#about to read 4, iclass 15, count 0 2006.173.03:54:35.46#ibcon#read 4, iclass 15, count 0 2006.173.03:54:35.46#ibcon#about to read 5, iclass 15, count 0 2006.173.03:54:35.46#ibcon#read 5, iclass 15, count 0 2006.173.03:54:35.46#ibcon#about to read 6, iclass 15, count 0 2006.173.03:54:35.46#ibcon#read 6, iclass 15, count 0 2006.173.03:54:35.46#ibcon#end of sib2, iclass 15, count 0 2006.173.03:54:35.46#ibcon#*after write, iclass 15, count 0 2006.173.03:54:35.46#ibcon#*before return 0, iclass 15, count 0 2006.173.03:54:35.46#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.03:54:35.46#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.03:54:35.46#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.03:54:35.46#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.03:54:35.46$vck44/vblo=5,709.99 2006.173.03:54:35.46#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.03:54:35.46#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.03:54:35.46#ibcon#ireg 17 cls_cnt 0 2006.173.03:54:35.46#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.03:54:35.46#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.03:54:35.46#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.03:54:35.46#ibcon#enter wrdev, iclass 17, count 0 2006.173.03:54:35.46#ibcon#first serial, iclass 17, count 0 2006.173.03:54:35.46#ibcon#enter sib2, iclass 17, count 0 2006.173.03:54:35.46#ibcon#flushed, iclass 17, count 0 2006.173.03:54:35.46#ibcon#about to write, iclass 17, count 0 2006.173.03:54:35.46#ibcon#wrote, iclass 17, count 0 2006.173.03:54:35.46#ibcon#about to read 3, iclass 17, count 0 2006.173.03:54:35.48#ibcon#read 3, iclass 17, count 0 2006.173.03:54:35.48#ibcon#about to read 4, iclass 17, count 0 2006.173.03:54:35.48#ibcon#read 4, iclass 17, count 0 2006.173.03:54:35.48#ibcon#about to read 5, iclass 17, count 0 2006.173.03:54:35.48#ibcon#read 5, iclass 17, count 0 2006.173.03:54:35.48#ibcon#about to read 6, iclass 17, count 0 2006.173.03:54:35.48#ibcon#read 6, iclass 17, count 0 2006.173.03:54:35.48#ibcon#end of sib2, iclass 17, count 0 2006.173.03:54:35.48#ibcon#*mode == 0, iclass 17, count 0 2006.173.03:54:35.48#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.03:54:35.48#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.03:54:35.48#ibcon#*before write, iclass 17, count 0 2006.173.03:54:35.48#ibcon#enter sib2, iclass 17, count 0 2006.173.03:54:35.48#ibcon#flushed, iclass 17, count 0 2006.173.03:54:35.48#ibcon#about to write, iclass 17, count 0 2006.173.03:54:35.48#ibcon#wrote, iclass 17, count 0 2006.173.03:54:35.48#ibcon#about to read 3, iclass 17, count 0 2006.173.03:54:35.52#ibcon#read 3, iclass 17, count 0 2006.173.03:54:35.52#ibcon#about to read 4, iclass 17, count 0 2006.173.03:54:35.52#ibcon#read 4, iclass 17, count 0 2006.173.03:54:35.52#ibcon#about to read 5, iclass 17, count 0 2006.173.03:54:35.52#ibcon#read 5, iclass 17, count 0 2006.173.03:54:35.52#ibcon#about to read 6, iclass 17, count 0 2006.173.03:54:35.52#ibcon#read 6, iclass 17, count 0 2006.173.03:54:35.52#ibcon#end of sib2, iclass 17, count 0 2006.173.03:54:35.52#ibcon#*after write, iclass 17, count 0 2006.173.03:54:35.52#ibcon#*before return 0, iclass 17, count 0 2006.173.03:54:35.52#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.03:54:35.52#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.03:54:35.52#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.03:54:35.52#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.03:54:35.52$vck44/vb=5,4 2006.173.03:54:35.52#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.03:54:35.52#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.03:54:35.52#ibcon#ireg 11 cls_cnt 2 2006.173.03:54:35.52#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.03:54:35.58#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.03:54:35.58#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.03:54:35.58#ibcon#enter wrdev, iclass 19, count 2 2006.173.03:54:35.58#ibcon#first serial, iclass 19, count 2 2006.173.03:54:35.58#ibcon#enter sib2, iclass 19, count 2 2006.173.03:54:35.58#ibcon#flushed, iclass 19, count 2 2006.173.03:54:35.58#ibcon#about to write, iclass 19, count 2 2006.173.03:54:35.58#ibcon#wrote, iclass 19, count 2 2006.173.03:54:35.58#ibcon#about to read 3, iclass 19, count 2 2006.173.03:54:35.60#ibcon#read 3, iclass 19, count 2 2006.173.03:54:35.60#ibcon#about to read 4, iclass 19, count 2 2006.173.03:54:35.60#ibcon#read 4, iclass 19, count 2 2006.173.03:54:35.60#ibcon#about to read 5, iclass 19, count 2 2006.173.03:54:35.60#ibcon#read 5, iclass 19, count 2 2006.173.03:54:35.60#ibcon#about to read 6, iclass 19, count 2 2006.173.03:54:35.60#ibcon#read 6, iclass 19, count 2 2006.173.03:54:35.60#ibcon#end of sib2, iclass 19, count 2 2006.173.03:54:35.60#ibcon#*mode == 0, iclass 19, count 2 2006.173.03:54:35.60#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.03:54:35.60#ibcon#[27=AT05-04\r\n] 2006.173.03:54:35.60#ibcon#*before write, iclass 19, count 2 2006.173.03:54:35.60#ibcon#enter sib2, iclass 19, count 2 2006.173.03:54:35.60#ibcon#flushed, iclass 19, count 2 2006.173.03:54:35.60#ibcon#about to write, iclass 19, count 2 2006.173.03:54:35.60#ibcon#wrote, iclass 19, count 2 2006.173.03:54:35.60#ibcon#about to read 3, iclass 19, count 2 2006.173.03:54:35.63#ibcon#read 3, iclass 19, count 2 2006.173.03:54:35.63#ibcon#about to read 4, iclass 19, count 2 2006.173.03:54:35.63#ibcon#read 4, iclass 19, count 2 2006.173.03:54:35.63#ibcon#about to read 5, iclass 19, count 2 2006.173.03:54:35.63#ibcon#read 5, iclass 19, count 2 2006.173.03:54:35.63#ibcon#about to read 6, iclass 19, count 2 2006.173.03:54:35.63#ibcon#read 6, iclass 19, count 2 2006.173.03:54:35.63#ibcon#end of sib2, iclass 19, count 2 2006.173.03:54:35.63#ibcon#*after write, iclass 19, count 2 2006.173.03:54:35.63#ibcon#*before return 0, iclass 19, count 2 2006.173.03:54:35.63#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.03:54:35.63#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.03:54:35.63#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.03:54:35.63#ibcon#ireg 7 cls_cnt 0 2006.173.03:54:35.63#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.03:54:35.75#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.03:54:35.75#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.03:54:35.75#ibcon#enter wrdev, iclass 19, count 0 2006.173.03:54:35.75#ibcon#first serial, iclass 19, count 0 2006.173.03:54:35.75#ibcon#enter sib2, iclass 19, count 0 2006.173.03:54:35.75#ibcon#flushed, iclass 19, count 0 2006.173.03:54:35.75#ibcon#about to write, iclass 19, count 0 2006.173.03:54:35.75#ibcon#wrote, iclass 19, count 0 2006.173.03:54:35.75#ibcon#about to read 3, iclass 19, count 0 2006.173.03:54:35.77#ibcon#read 3, iclass 19, count 0 2006.173.03:54:35.77#ibcon#about to read 4, iclass 19, count 0 2006.173.03:54:35.77#ibcon#read 4, iclass 19, count 0 2006.173.03:54:35.77#ibcon#about to read 5, iclass 19, count 0 2006.173.03:54:35.77#ibcon#read 5, iclass 19, count 0 2006.173.03:54:35.77#ibcon#about to read 6, iclass 19, count 0 2006.173.03:54:35.77#ibcon#read 6, iclass 19, count 0 2006.173.03:54:35.77#ibcon#end of sib2, iclass 19, count 0 2006.173.03:54:35.77#ibcon#*mode == 0, iclass 19, count 0 2006.173.03:54:35.77#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.03:54:35.77#ibcon#[27=USB\r\n] 2006.173.03:54:35.77#ibcon#*before write, iclass 19, count 0 2006.173.03:54:35.77#ibcon#enter sib2, iclass 19, count 0 2006.173.03:54:35.77#ibcon#flushed, iclass 19, count 0 2006.173.03:54:35.77#ibcon#about to write, iclass 19, count 0 2006.173.03:54:35.77#ibcon#wrote, iclass 19, count 0 2006.173.03:54:35.77#ibcon#about to read 3, iclass 19, count 0 2006.173.03:54:35.80#ibcon#read 3, iclass 19, count 0 2006.173.03:54:35.80#ibcon#about to read 4, iclass 19, count 0 2006.173.03:54:35.80#ibcon#read 4, iclass 19, count 0 2006.173.03:54:35.80#ibcon#about to read 5, iclass 19, count 0 2006.173.03:54:35.80#ibcon#read 5, iclass 19, count 0 2006.173.03:54:35.80#ibcon#about to read 6, iclass 19, count 0 2006.173.03:54:35.80#ibcon#read 6, iclass 19, count 0 2006.173.03:54:35.80#ibcon#end of sib2, iclass 19, count 0 2006.173.03:54:35.80#ibcon#*after write, iclass 19, count 0 2006.173.03:54:35.80#ibcon#*before return 0, iclass 19, count 0 2006.173.03:54:35.80#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.03:54:35.80#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.03:54:35.80#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.03:54:35.80#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.03:54:35.80$vck44/vblo=6,719.99 2006.173.03:54:35.80#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.03:54:35.80#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.03:54:35.80#ibcon#ireg 17 cls_cnt 0 2006.173.03:54:35.80#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.03:54:35.80#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.03:54:35.80#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.03:54:35.80#ibcon#enter wrdev, iclass 21, count 0 2006.173.03:54:35.80#ibcon#first serial, iclass 21, count 0 2006.173.03:54:35.80#ibcon#enter sib2, iclass 21, count 0 2006.173.03:54:35.80#ibcon#flushed, iclass 21, count 0 2006.173.03:54:35.80#ibcon#about to write, iclass 21, count 0 2006.173.03:54:35.80#ibcon#wrote, iclass 21, count 0 2006.173.03:54:35.80#ibcon#about to read 3, iclass 21, count 0 2006.173.03:54:35.82#ibcon#read 3, iclass 21, count 0 2006.173.03:54:35.82#ibcon#about to read 4, iclass 21, count 0 2006.173.03:54:35.82#ibcon#read 4, iclass 21, count 0 2006.173.03:54:35.82#ibcon#about to read 5, iclass 21, count 0 2006.173.03:54:35.82#ibcon#read 5, iclass 21, count 0 2006.173.03:54:35.82#ibcon#about to read 6, iclass 21, count 0 2006.173.03:54:35.82#ibcon#read 6, iclass 21, count 0 2006.173.03:54:35.82#ibcon#end of sib2, iclass 21, count 0 2006.173.03:54:35.82#ibcon#*mode == 0, iclass 21, count 0 2006.173.03:54:35.82#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.03:54:35.82#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.03:54:35.82#ibcon#*before write, iclass 21, count 0 2006.173.03:54:35.82#ibcon#enter sib2, iclass 21, count 0 2006.173.03:54:35.82#ibcon#flushed, iclass 21, count 0 2006.173.03:54:35.82#ibcon#about to write, iclass 21, count 0 2006.173.03:54:35.82#ibcon#wrote, iclass 21, count 0 2006.173.03:54:35.82#ibcon#about to read 3, iclass 21, count 0 2006.173.03:54:35.86#ibcon#read 3, iclass 21, count 0 2006.173.03:54:35.86#ibcon#about to read 4, iclass 21, count 0 2006.173.03:54:35.86#ibcon#read 4, iclass 21, count 0 2006.173.03:54:35.86#ibcon#about to read 5, iclass 21, count 0 2006.173.03:54:35.86#ibcon#read 5, iclass 21, count 0 2006.173.03:54:35.86#ibcon#about to read 6, iclass 21, count 0 2006.173.03:54:35.86#ibcon#read 6, iclass 21, count 0 2006.173.03:54:35.86#ibcon#end of sib2, iclass 21, count 0 2006.173.03:54:35.86#ibcon#*after write, iclass 21, count 0 2006.173.03:54:35.86#ibcon#*before return 0, iclass 21, count 0 2006.173.03:54:35.86#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.03:54:35.86#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.03:54:35.86#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.03:54:35.86#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.03:54:35.86$vck44/vb=6,4 2006.173.03:54:35.86#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.03:54:35.86#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.03:54:35.86#ibcon#ireg 11 cls_cnt 2 2006.173.03:54:35.86#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.03:54:35.92#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.03:54:35.92#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.03:54:35.92#ibcon#enter wrdev, iclass 23, count 2 2006.173.03:54:35.92#ibcon#first serial, iclass 23, count 2 2006.173.03:54:35.92#ibcon#enter sib2, iclass 23, count 2 2006.173.03:54:35.92#ibcon#flushed, iclass 23, count 2 2006.173.03:54:35.92#ibcon#about to write, iclass 23, count 2 2006.173.03:54:35.92#ibcon#wrote, iclass 23, count 2 2006.173.03:54:35.92#ibcon#about to read 3, iclass 23, count 2 2006.173.03:54:35.94#ibcon#read 3, iclass 23, count 2 2006.173.03:54:35.94#ibcon#about to read 4, iclass 23, count 2 2006.173.03:54:35.94#ibcon#read 4, iclass 23, count 2 2006.173.03:54:35.94#ibcon#about to read 5, iclass 23, count 2 2006.173.03:54:35.94#ibcon#read 5, iclass 23, count 2 2006.173.03:54:35.94#ibcon#about to read 6, iclass 23, count 2 2006.173.03:54:35.94#ibcon#read 6, iclass 23, count 2 2006.173.03:54:35.94#ibcon#end of sib2, iclass 23, count 2 2006.173.03:54:35.94#ibcon#*mode == 0, iclass 23, count 2 2006.173.03:54:35.94#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.03:54:35.94#ibcon#[27=AT06-04\r\n] 2006.173.03:54:35.94#ibcon#*before write, iclass 23, count 2 2006.173.03:54:35.94#ibcon#enter sib2, iclass 23, count 2 2006.173.03:54:35.94#ibcon#flushed, iclass 23, count 2 2006.173.03:54:35.94#ibcon#about to write, iclass 23, count 2 2006.173.03:54:35.94#ibcon#wrote, iclass 23, count 2 2006.173.03:54:35.94#ibcon#about to read 3, iclass 23, count 2 2006.173.03:54:35.97#ibcon#read 3, iclass 23, count 2 2006.173.03:54:35.97#ibcon#about to read 4, iclass 23, count 2 2006.173.03:54:35.97#ibcon#read 4, iclass 23, count 2 2006.173.03:54:35.97#ibcon#about to read 5, iclass 23, count 2 2006.173.03:54:35.97#ibcon#read 5, iclass 23, count 2 2006.173.03:54:35.97#ibcon#about to read 6, iclass 23, count 2 2006.173.03:54:35.97#ibcon#read 6, iclass 23, count 2 2006.173.03:54:35.97#ibcon#end of sib2, iclass 23, count 2 2006.173.03:54:35.97#ibcon#*after write, iclass 23, count 2 2006.173.03:54:35.97#ibcon#*before return 0, iclass 23, count 2 2006.173.03:54:35.97#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.03:54:35.97#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.03:54:35.97#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.03:54:35.97#ibcon#ireg 7 cls_cnt 0 2006.173.03:54:35.97#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.03:54:36.09#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.03:54:36.09#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.03:54:36.09#ibcon#enter wrdev, iclass 23, count 0 2006.173.03:54:36.09#ibcon#first serial, iclass 23, count 0 2006.173.03:54:36.09#ibcon#enter sib2, iclass 23, count 0 2006.173.03:54:36.09#ibcon#flushed, iclass 23, count 0 2006.173.03:54:36.09#ibcon#about to write, iclass 23, count 0 2006.173.03:54:36.09#ibcon#wrote, iclass 23, count 0 2006.173.03:54:36.09#ibcon#about to read 3, iclass 23, count 0 2006.173.03:54:36.11#ibcon#read 3, iclass 23, count 0 2006.173.03:54:36.11#ibcon#about to read 4, iclass 23, count 0 2006.173.03:54:36.11#ibcon#read 4, iclass 23, count 0 2006.173.03:54:36.11#ibcon#about to read 5, iclass 23, count 0 2006.173.03:54:36.11#ibcon#read 5, iclass 23, count 0 2006.173.03:54:36.11#ibcon#about to read 6, iclass 23, count 0 2006.173.03:54:36.11#ibcon#read 6, iclass 23, count 0 2006.173.03:54:36.11#ibcon#end of sib2, iclass 23, count 0 2006.173.03:54:36.11#ibcon#*mode == 0, iclass 23, count 0 2006.173.03:54:36.11#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.03:54:36.11#ibcon#[27=USB\r\n] 2006.173.03:54:36.11#ibcon#*before write, iclass 23, count 0 2006.173.03:54:36.11#ibcon#enter sib2, iclass 23, count 0 2006.173.03:54:36.11#ibcon#flushed, iclass 23, count 0 2006.173.03:54:36.11#ibcon#about to write, iclass 23, count 0 2006.173.03:54:36.11#ibcon#wrote, iclass 23, count 0 2006.173.03:54:36.11#ibcon#about to read 3, iclass 23, count 0 2006.173.03:54:36.14#ibcon#read 3, iclass 23, count 0 2006.173.03:54:36.14#ibcon#about to read 4, iclass 23, count 0 2006.173.03:54:36.14#ibcon#read 4, iclass 23, count 0 2006.173.03:54:36.14#ibcon#about to read 5, iclass 23, count 0 2006.173.03:54:36.14#ibcon#read 5, iclass 23, count 0 2006.173.03:54:36.14#ibcon#about to read 6, iclass 23, count 0 2006.173.03:54:36.14#ibcon#read 6, iclass 23, count 0 2006.173.03:54:36.14#ibcon#end of sib2, iclass 23, count 0 2006.173.03:54:36.14#ibcon#*after write, iclass 23, count 0 2006.173.03:54:36.14#ibcon#*before return 0, iclass 23, count 0 2006.173.03:54:36.14#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.03:54:36.14#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.03:54:36.14#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.03:54:36.14#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.03:54:36.14$vck44/vblo=7,734.99 2006.173.03:54:36.14#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.03:54:36.14#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.03:54:36.14#ibcon#ireg 17 cls_cnt 0 2006.173.03:54:36.14#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.03:54:36.14#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.03:54:36.14#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.03:54:36.14#ibcon#enter wrdev, iclass 25, count 0 2006.173.03:54:36.14#ibcon#first serial, iclass 25, count 0 2006.173.03:54:36.14#ibcon#enter sib2, iclass 25, count 0 2006.173.03:54:36.14#ibcon#flushed, iclass 25, count 0 2006.173.03:54:36.14#ibcon#about to write, iclass 25, count 0 2006.173.03:54:36.14#ibcon#wrote, iclass 25, count 0 2006.173.03:54:36.14#ibcon#about to read 3, iclass 25, count 0 2006.173.03:54:36.16#ibcon#read 3, iclass 25, count 0 2006.173.03:54:36.16#ibcon#about to read 4, iclass 25, count 0 2006.173.03:54:36.16#ibcon#read 4, iclass 25, count 0 2006.173.03:54:36.16#ibcon#about to read 5, iclass 25, count 0 2006.173.03:54:36.16#ibcon#read 5, iclass 25, count 0 2006.173.03:54:36.16#ibcon#about to read 6, iclass 25, count 0 2006.173.03:54:36.16#ibcon#read 6, iclass 25, count 0 2006.173.03:54:36.16#ibcon#end of sib2, iclass 25, count 0 2006.173.03:54:36.16#ibcon#*mode == 0, iclass 25, count 0 2006.173.03:54:36.16#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.03:54:36.16#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.03:54:36.16#ibcon#*before write, iclass 25, count 0 2006.173.03:54:36.16#ibcon#enter sib2, iclass 25, count 0 2006.173.03:54:36.16#ibcon#flushed, iclass 25, count 0 2006.173.03:54:36.16#ibcon#about to write, iclass 25, count 0 2006.173.03:54:36.16#ibcon#wrote, iclass 25, count 0 2006.173.03:54:36.16#ibcon#about to read 3, iclass 25, count 0 2006.173.03:54:36.20#ibcon#read 3, iclass 25, count 0 2006.173.03:54:36.20#ibcon#about to read 4, iclass 25, count 0 2006.173.03:54:36.20#ibcon#read 4, iclass 25, count 0 2006.173.03:54:36.20#ibcon#about to read 5, iclass 25, count 0 2006.173.03:54:36.20#ibcon#read 5, iclass 25, count 0 2006.173.03:54:36.20#ibcon#about to read 6, iclass 25, count 0 2006.173.03:54:36.20#ibcon#read 6, iclass 25, count 0 2006.173.03:54:36.20#ibcon#end of sib2, iclass 25, count 0 2006.173.03:54:36.20#ibcon#*after write, iclass 25, count 0 2006.173.03:54:36.20#ibcon#*before return 0, iclass 25, count 0 2006.173.03:54:36.20#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.03:54:36.20#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.03:54:36.20#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.03:54:36.20#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.03:54:36.20$vck44/vb=7,4 2006.173.03:54:36.20#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.03:54:36.20#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.03:54:36.20#ibcon#ireg 11 cls_cnt 2 2006.173.03:54:36.20#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.03:54:36.26#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.03:54:36.26#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.03:54:36.26#ibcon#enter wrdev, iclass 27, count 2 2006.173.03:54:36.26#ibcon#first serial, iclass 27, count 2 2006.173.03:54:36.26#ibcon#enter sib2, iclass 27, count 2 2006.173.03:54:36.26#ibcon#flushed, iclass 27, count 2 2006.173.03:54:36.26#ibcon#about to write, iclass 27, count 2 2006.173.03:54:36.26#ibcon#wrote, iclass 27, count 2 2006.173.03:54:36.26#ibcon#about to read 3, iclass 27, count 2 2006.173.03:54:36.28#ibcon#read 3, iclass 27, count 2 2006.173.03:54:36.28#ibcon#about to read 4, iclass 27, count 2 2006.173.03:54:36.28#ibcon#read 4, iclass 27, count 2 2006.173.03:54:36.28#ibcon#about to read 5, iclass 27, count 2 2006.173.03:54:36.28#ibcon#read 5, iclass 27, count 2 2006.173.03:54:36.28#ibcon#about to read 6, iclass 27, count 2 2006.173.03:54:36.28#ibcon#read 6, iclass 27, count 2 2006.173.03:54:36.28#ibcon#end of sib2, iclass 27, count 2 2006.173.03:54:36.28#ibcon#*mode == 0, iclass 27, count 2 2006.173.03:54:36.28#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.03:54:36.28#ibcon#[27=AT07-04\r\n] 2006.173.03:54:36.28#ibcon#*before write, iclass 27, count 2 2006.173.03:54:36.28#ibcon#enter sib2, iclass 27, count 2 2006.173.03:54:36.28#ibcon#flushed, iclass 27, count 2 2006.173.03:54:36.28#ibcon#about to write, iclass 27, count 2 2006.173.03:54:36.28#ibcon#wrote, iclass 27, count 2 2006.173.03:54:36.28#ibcon#about to read 3, iclass 27, count 2 2006.173.03:54:36.31#ibcon#read 3, iclass 27, count 2 2006.173.03:54:36.31#ibcon#about to read 4, iclass 27, count 2 2006.173.03:54:36.31#ibcon#read 4, iclass 27, count 2 2006.173.03:54:36.31#ibcon#about to read 5, iclass 27, count 2 2006.173.03:54:36.31#ibcon#read 5, iclass 27, count 2 2006.173.03:54:36.31#ibcon#about to read 6, iclass 27, count 2 2006.173.03:54:36.31#ibcon#read 6, iclass 27, count 2 2006.173.03:54:36.31#ibcon#end of sib2, iclass 27, count 2 2006.173.03:54:36.31#ibcon#*after write, iclass 27, count 2 2006.173.03:54:36.31#ibcon#*before return 0, iclass 27, count 2 2006.173.03:54:36.31#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.03:54:36.31#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.03:54:36.31#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.03:54:36.31#ibcon#ireg 7 cls_cnt 0 2006.173.03:54:36.31#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.03:54:36.43#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.03:54:36.43#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.03:54:36.43#ibcon#enter wrdev, iclass 27, count 0 2006.173.03:54:36.43#ibcon#first serial, iclass 27, count 0 2006.173.03:54:36.43#ibcon#enter sib2, iclass 27, count 0 2006.173.03:54:36.43#ibcon#flushed, iclass 27, count 0 2006.173.03:54:36.43#ibcon#about to write, iclass 27, count 0 2006.173.03:54:36.43#ibcon#wrote, iclass 27, count 0 2006.173.03:54:36.43#ibcon#about to read 3, iclass 27, count 0 2006.173.03:54:36.45#ibcon#read 3, iclass 27, count 0 2006.173.03:54:36.45#ibcon#about to read 4, iclass 27, count 0 2006.173.03:54:36.45#ibcon#read 4, iclass 27, count 0 2006.173.03:54:36.45#ibcon#about to read 5, iclass 27, count 0 2006.173.03:54:36.45#ibcon#read 5, iclass 27, count 0 2006.173.03:54:36.45#ibcon#about to read 6, iclass 27, count 0 2006.173.03:54:36.45#ibcon#read 6, iclass 27, count 0 2006.173.03:54:36.45#ibcon#end of sib2, iclass 27, count 0 2006.173.03:54:36.45#ibcon#*mode == 0, iclass 27, count 0 2006.173.03:54:36.45#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.03:54:36.45#ibcon#[27=USB\r\n] 2006.173.03:54:36.45#ibcon#*before write, iclass 27, count 0 2006.173.03:54:36.45#ibcon#enter sib2, iclass 27, count 0 2006.173.03:54:36.45#ibcon#flushed, iclass 27, count 0 2006.173.03:54:36.45#ibcon#about to write, iclass 27, count 0 2006.173.03:54:36.45#ibcon#wrote, iclass 27, count 0 2006.173.03:54:36.45#ibcon#about to read 3, iclass 27, count 0 2006.173.03:54:36.48#ibcon#read 3, iclass 27, count 0 2006.173.03:54:36.48#ibcon#about to read 4, iclass 27, count 0 2006.173.03:54:36.48#ibcon#read 4, iclass 27, count 0 2006.173.03:54:36.48#ibcon#about to read 5, iclass 27, count 0 2006.173.03:54:36.48#ibcon#read 5, iclass 27, count 0 2006.173.03:54:36.48#ibcon#about to read 6, iclass 27, count 0 2006.173.03:54:36.48#ibcon#read 6, iclass 27, count 0 2006.173.03:54:36.48#ibcon#end of sib2, iclass 27, count 0 2006.173.03:54:36.48#ibcon#*after write, iclass 27, count 0 2006.173.03:54:36.48#ibcon#*before return 0, iclass 27, count 0 2006.173.03:54:36.48#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.03:54:36.48#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.03:54:36.48#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.03:54:36.48#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.03:54:36.48$vck44/vblo=8,744.99 2006.173.03:54:36.48#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.03:54:36.48#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.03:54:36.48#ibcon#ireg 17 cls_cnt 0 2006.173.03:54:36.48#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.03:54:36.48#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.03:54:36.48#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.03:54:36.48#ibcon#enter wrdev, iclass 29, count 0 2006.173.03:54:36.48#ibcon#first serial, iclass 29, count 0 2006.173.03:54:36.48#ibcon#enter sib2, iclass 29, count 0 2006.173.03:54:36.48#ibcon#flushed, iclass 29, count 0 2006.173.03:54:36.48#ibcon#about to write, iclass 29, count 0 2006.173.03:54:36.48#ibcon#wrote, iclass 29, count 0 2006.173.03:54:36.48#ibcon#about to read 3, iclass 29, count 0 2006.173.03:54:36.50#ibcon#read 3, iclass 29, count 0 2006.173.03:54:36.50#ibcon#about to read 4, iclass 29, count 0 2006.173.03:54:36.50#ibcon#read 4, iclass 29, count 0 2006.173.03:54:36.50#ibcon#about to read 5, iclass 29, count 0 2006.173.03:54:36.50#ibcon#read 5, iclass 29, count 0 2006.173.03:54:36.50#ibcon#about to read 6, iclass 29, count 0 2006.173.03:54:36.50#ibcon#read 6, iclass 29, count 0 2006.173.03:54:36.50#ibcon#end of sib2, iclass 29, count 0 2006.173.03:54:36.50#ibcon#*mode == 0, iclass 29, count 0 2006.173.03:54:36.50#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.03:54:36.50#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.03:54:36.50#ibcon#*before write, iclass 29, count 0 2006.173.03:54:36.50#ibcon#enter sib2, iclass 29, count 0 2006.173.03:54:36.50#ibcon#flushed, iclass 29, count 0 2006.173.03:54:36.50#ibcon#about to write, iclass 29, count 0 2006.173.03:54:36.50#ibcon#wrote, iclass 29, count 0 2006.173.03:54:36.50#ibcon#about to read 3, iclass 29, count 0 2006.173.03:54:36.54#ibcon#read 3, iclass 29, count 0 2006.173.03:54:36.54#ibcon#about to read 4, iclass 29, count 0 2006.173.03:54:36.54#ibcon#read 4, iclass 29, count 0 2006.173.03:54:36.54#ibcon#about to read 5, iclass 29, count 0 2006.173.03:54:36.54#ibcon#read 5, iclass 29, count 0 2006.173.03:54:36.54#ibcon#about to read 6, iclass 29, count 0 2006.173.03:54:36.54#ibcon#read 6, iclass 29, count 0 2006.173.03:54:36.54#ibcon#end of sib2, iclass 29, count 0 2006.173.03:54:36.54#ibcon#*after write, iclass 29, count 0 2006.173.03:54:36.54#ibcon#*before return 0, iclass 29, count 0 2006.173.03:54:36.54#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.03:54:36.54#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.03:54:36.54#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.03:54:36.54#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.03:54:36.54$vck44/vb=8,4 2006.173.03:54:36.54#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.03:54:36.54#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.03:54:36.54#ibcon#ireg 11 cls_cnt 2 2006.173.03:54:36.54#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.03:54:36.60#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.03:54:36.60#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.03:54:36.60#ibcon#enter wrdev, iclass 31, count 2 2006.173.03:54:36.60#ibcon#first serial, iclass 31, count 2 2006.173.03:54:36.60#ibcon#enter sib2, iclass 31, count 2 2006.173.03:54:36.60#ibcon#flushed, iclass 31, count 2 2006.173.03:54:36.60#ibcon#about to write, iclass 31, count 2 2006.173.03:54:36.60#ibcon#wrote, iclass 31, count 2 2006.173.03:54:36.60#ibcon#about to read 3, iclass 31, count 2 2006.173.03:54:36.62#ibcon#read 3, iclass 31, count 2 2006.173.03:54:36.62#ibcon#about to read 4, iclass 31, count 2 2006.173.03:54:36.62#ibcon#read 4, iclass 31, count 2 2006.173.03:54:36.62#ibcon#about to read 5, iclass 31, count 2 2006.173.03:54:36.62#ibcon#read 5, iclass 31, count 2 2006.173.03:54:36.62#ibcon#about to read 6, iclass 31, count 2 2006.173.03:54:36.62#ibcon#read 6, iclass 31, count 2 2006.173.03:54:36.62#ibcon#end of sib2, iclass 31, count 2 2006.173.03:54:36.62#ibcon#*mode == 0, iclass 31, count 2 2006.173.03:54:36.62#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.03:54:36.62#ibcon#[27=AT08-04\r\n] 2006.173.03:54:36.62#ibcon#*before write, iclass 31, count 2 2006.173.03:54:36.62#ibcon#enter sib2, iclass 31, count 2 2006.173.03:54:36.62#ibcon#flushed, iclass 31, count 2 2006.173.03:54:36.62#ibcon#about to write, iclass 31, count 2 2006.173.03:54:36.62#ibcon#wrote, iclass 31, count 2 2006.173.03:54:36.62#ibcon#about to read 3, iclass 31, count 2 2006.173.03:54:36.65#ibcon#read 3, iclass 31, count 2 2006.173.03:54:36.65#ibcon#about to read 4, iclass 31, count 2 2006.173.03:54:36.65#ibcon#read 4, iclass 31, count 2 2006.173.03:54:36.65#ibcon#about to read 5, iclass 31, count 2 2006.173.03:54:36.65#ibcon#read 5, iclass 31, count 2 2006.173.03:54:36.65#ibcon#about to read 6, iclass 31, count 2 2006.173.03:54:36.65#ibcon#read 6, iclass 31, count 2 2006.173.03:54:36.65#ibcon#end of sib2, iclass 31, count 2 2006.173.03:54:36.65#ibcon#*after write, iclass 31, count 2 2006.173.03:54:36.65#ibcon#*before return 0, iclass 31, count 2 2006.173.03:54:36.65#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.03:54:36.65#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.03:54:36.65#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.03:54:36.65#ibcon#ireg 7 cls_cnt 0 2006.173.03:54:36.65#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.03:54:36.77#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.03:54:36.77#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.03:54:36.77#ibcon#enter wrdev, iclass 31, count 0 2006.173.03:54:36.77#ibcon#first serial, iclass 31, count 0 2006.173.03:54:36.77#ibcon#enter sib2, iclass 31, count 0 2006.173.03:54:36.77#ibcon#flushed, iclass 31, count 0 2006.173.03:54:36.77#ibcon#about to write, iclass 31, count 0 2006.173.03:54:36.77#ibcon#wrote, iclass 31, count 0 2006.173.03:54:36.77#ibcon#about to read 3, iclass 31, count 0 2006.173.03:54:36.79#ibcon#read 3, iclass 31, count 0 2006.173.03:54:36.79#ibcon#about to read 4, iclass 31, count 0 2006.173.03:54:36.79#ibcon#read 4, iclass 31, count 0 2006.173.03:54:36.79#ibcon#about to read 5, iclass 31, count 0 2006.173.03:54:36.79#ibcon#read 5, iclass 31, count 0 2006.173.03:54:36.79#ibcon#about to read 6, iclass 31, count 0 2006.173.03:54:36.79#ibcon#read 6, iclass 31, count 0 2006.173.03:54:36.79#ibcon#end of sib2, iclass 31, count 0 2006.173.03:54:36.79#ibcon#*mode == 0, iclass 31, count 0 2006.173.03:54:36.79#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.03:54:36.79#ibcon#[27=USB\r\n] 2006.173.03:54:36.79#ibcon#*before write, iclass 31, count 0 2006.173.03:54:36.79#ibcon#enter sib2, iclass 31, count 0 2006.173.03:54:36.79#ibcon#flushed, iclass 31, count 0 2006.173.03:54:36.79#ibcon#about to write, iclass 31, count 0 2006.173.03:54:36.79#ibcon#wrote, iclass 31, count 0 2006.173.03:54:36.79#ibcon#about to read 3, iclass 31, count 0 2006.173.03:54:36.82#ibcon#read 3, iclass 31, count 0 2006.173.03:54:36.82#ibcon#about to read 4, iclass 31, count 0 2006.173.03:54:36.82#ibcon#read 4, iclass 31, count 0 2006.173.03:54:36.82#ibcon#about to read 5, iclass 31, count 0 2006.173.03:54:36.82#ibcon#read 5, iclass 31, count 0 2006.173.03:54:36.82#ibcon#about to read 6, iclass 31, count 0 2006.173.03:54:36.82#ibcon#read 6, iclass 31, count 0 2006.173.03:54:36.82#ibcon#end of sib2, iclass 31, count 0 2006.173.03:54:36.82#ibcon#*after write, iclass 31, count 0 2006.173.03:54:36.82#ibcon#*before return 0, iclass 31, count 0 2006.173.03:54:36.82#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.03:54:36.82#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.03:54:36.82#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.03:54:36.82#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.03:54:36.82$vck44/vabw=wide 2006.173.03:54:36.82#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.03:54:36.82#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.03:54:36.82#ibcon#ireg 8 cls_cnt 0 2006.173.03:54:36.82#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.03:54:36.82#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.03:54:36.82#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.03:54:36.82#ibcon#enter wrdev, iclass 33, count 0 2006.173.03:54:36.82#ibcon#first serial, iclass 33, count 0 2006.173.03:54:36.82#ibcon#enter sib2, iclass 33, count 0 2006.173.03:54:36.82#ibcon#flushed, iclass 33, count 0 2006.173.03:54:36.82#ibcon#about to write, iclass 33, count 0 2006.173.03:54:36.82#ibcon#wrote, iclass 33, count 0 2006.173.03:54:36.82#ibcon#about to read 3, iclass 33, count 0 2006.173.03:54:36.84#ibcon#read 3, iclass 33, count 0 2006.173.03:54:36.84#ibcon#about to read 4, iclass 33, count 0 2006.173.03:54:36.84#ibcon#read 4, iclass 33, count 0 2006.173.03:54:36.84#ibcon#about to read 5, iclass 33, count 0 2006.173.03:54:36.84#ibcon#read 5, iclass 33, count 0 2006.173.03:54:36.84#ibcon#about to read 6, iclass 33, count 0 2006.173.03:54:36.84#ibcon#read 6, iclass 33, count 0 2006.173.03:54:36.84#ibcon#end of sib2, iclass 33, count 0 2006.173.03:54:36.84#ibcon#*mode == 0, iclass 33, count 0 2006.173.03:54:36.84#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.03:54:36.84#ibcon#[25=BW32\r\n] 2006.173.03:54:36.84#ibcon#*before write, iclass 33, count 0 2006.173.03:54:36.84#ibcon#enter sib2, iclass 33, count 0 2006.173.03:54:36.84#ibcon#flushed, iclass 33, count 0 2006.173.03:54:36.84#ibcon#about to write, iclass 33, count 0 2006.173.03:54:36.84#ibcon#wrote, iclass 33, count 0 2006.173.03:54:36.84#ibcon#about to read 3, iclass 33, count 0 2006.173.03:54:36.87#ibcon#read 3, iclass 33, count 0 2006.173.03:54:36.87#ibcon#about to read 4, iclass 33, count 0 2006.173.03:54:36.87#ibcon#read 4, iclass 33, count 0 2006.173.03:54:36.87#ibcon#about to read 5, iclass 33, count 0 2006.173.03:54:36.87#ibcon#read 5, iclass 33, count 0 2006.173.03:54:36.87#ibcon#about to read 6, iclass 33, count 0 2006.173.03:54:36.87#ibcon#read 6, iclass 33, count 0 2006.173.03:54:36.87#ibcon#end of sib2, iclass 33, count 0 2006.173.03:54:36.87#ibcon#*after write, iclass 33, count 0 2006.173.03:54:36.87#ibcon#*before return 0, iclass 33, count 0 2006.173.03:54:36.87#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.03:54:36.87#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.03:54:36.87#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.03:54:36.87#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.03:54:36.87$vck44/vbbw=wide 2006.173.03:54:36.87#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.03:54:36.87#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.03:54:36.87#ibcon#ireg 8 cls_cnt 0 2006.173.03:54:36.87#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.03:54:36.94#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.03:54:36.94#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.03:54:36.94#ibcon#enter wrdev, iclass 35, count 0 2006.173.03:54:36.94#ibcon#first serial, iclass 35, count 0 2006.173.03:54:36.94#ibcon#enter sib2, iclass 35, count 0 2006.173.03:54:36.94#ibcon#flushed, iclass 35, count 0 2006.173.03:54:36.94#ibcon#about to write, iclass 35, count 0 2006.173.03:54:36.94#ibcon#wrote, iclass 35, count 0 2006.173.03:54:36.94#ibcon#about to read 3, iclass 35, count 0 2006.173.03:54:36.96#ibcon#read 3, iclass 35, count 0 2006.173.03:54:36.96#ibcon#about to read 4, iclass 35, count 0 2006.173.03:54:36.96#ibcon#read 4, iclass 35, count 0 2006.173.03:54:36.96#ibcon#about to read 5, iclass 35, count 0 2006.173.03:54:36.96#ibcon#read 5, iclass 35, count 0 2006.173.03:54:36.96#ibcon#about to read 6, iclass 35, count 0 2006.173.03:54:36.96#ibcon#read 6, iclass 35, count 0 2006.173.03:54:36.96#ibcon#end of sib2, iclass 35, count 0 2006.173.03:54:36.96#ibcon#*mode == 0, iclass 35, count 0 2006.173.03:54:36.96#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.03:54:36.96#ibcon#[27=BW32\r\n] 2006.173.03:54:36.96#ibcon#*before write, iclass 35, count 0 2006.173.03:54:36.96#ibcon#enter sib2, iclass 35, count 0 2006.173.03:54:36.96#ibcon#flushed, iclass 35, count 0 2006.173.03:54:36.96#ibcon#about to write, iclass 35, count 0 2006.173.03:54:36.96#ibcon#wrote, iclass 35, count 0 2006.173.03:54:36.96#ibcon#about to read 3, iclass 35, count 0 2006.173.03:54:36.99#ibcon#read 3, iclass 35, count 0 2006.173.03:54:36.99#ibcon#about to read 4, iclass 35, count 0 2006.173.03:54:36.99#ibcon#read 4, iclass 35, count 0 2006.173.03:54:36.99#ibcon#about to read 5, iclass 35, count 0 2006.173.03:54:36.99#ibcon#read 5, iclass 35, count 0 2006.173.03:54:36.99#ibcon#about to read 6, iclass 35, count 0 2006.173.03:54:36.99#ibcon#read 6, iclass 35, count 0 2006.173.03:54:36.99#ibcon#end of sib2, iclass 35, count 0 2006.173.03:54:36.99#ibcon#*after write, iclass 35, count 0 2006.173.03:54:36.99#ibcon#*before return 0, iclass 35, count 0 2006.173.03:54:36.99#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.03:54:36.99#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.03:54:36.99#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.03:54:36.99#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.03:54:36.99$setupk4/ifdk4 2006.173.03:54:36.99$ifdk4/lo= 2006.173.03:54:36.99$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.03:54:36.99$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.03:54:36.99$ifdk4/patch= 2006.173.03:54:36.99$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.03:54:36.99$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.03:54:36.99$setupk4/!*+20s 2006.173.03:54:43.79#abcon#<5=/14 1.4 2.6 22.97 811006.2\r\n> 2006.173.03:54:43.81#abcon#{5=INTERFACE CLEAR} 2006.173.03:54:43.87#abcon#[5=S1D000X0/0*\r\n] 2006.173.03:54:51.49$setupk4/"tpicd 2006.173.03:54:51.49$setupk4/echo=off 2006.173.03:54:51.49$setupk4/xlog=off 2006.173.03:54:51.49:!2006.173.04:00:27 2006.173.03:55:07.14#trakl#Source acquired 2006.173.03:55:07.14#flagr#flagr/antenna,acquired 2006.173.04:00:27.02:preob 2006.173.04:00:28.14/onsource/TRACKING 2006.173.04:00:28.14:!2006.173.04:00:37 2006.173.04:00:37.02:"tape 2006.173.04:00:37.02:"st=record 2006.173.04:00:37.02:data_valid=on 2006.173.04:00:37.02:midob 2006.173.04:00:38.14/onsource/TRACKING 2006.173.04:00:38.14/wx/23.07,1006.1,77 2006.173.04:00:38.20/cable/+6.5107E-03 2006.173.04:00:39.29/va/01,07,usb,yes,36,39 2006.173.04:00:39.29/va/02,06,usb,yes,36,37 2006.173.04:00:39.29/va/03,05,usb,yes,46,48 2006.173.04:00:39.29/va/04,06,usb,yes,37,39 2006.173.04:00:39.29/va/05,04,usb,yes,29,29 2006.173.04:00:39.29/va/06,03,usb,yes,40,40 2006.173.04:00:39.29/va/07,04,usb,yes,33,34 2006.173.04:00:39.29/va/08,04,usb,yes,28,34 2006.173.04:00:39.52/valo/01,524.99,yes,locked 2006.173.04:00:39.52/valo/02,534.99,yes,locked 2006.173.04:00:39.52/valo/03,564.99,yes,locked 2006.173.04:00:39.52/valo/04,624.99,yes,locked 2006.173.04:00:39.52/valo/05,734.99,yes,locked 2006.173.04:00:39.52/valo/06,814.99,yes,locked 2006.173.04:00:39.52/valo/07,864.99,yes,locked 2006.173.04:00:39.52/valo/08,884.99,yes,locked 2006.173.04:00:40.61/vb/01,04,usb,yes,30,27 2006.173.04:00:40.61/vb/02,04,usb,yes,32,32 2006.173.04:00:40.61/vb/03,04,usb,yes,29,32 2006.173.04:00:40.61/vb/04,04,usb,yes,33,32 2006.173.04:00:40.61/vb/05,04,usb,yes,26,28 2006.173.04:00:40.61/vb/06,04,usb,yes,30,27 2006.173.04:00:40.61/vb/07,04,usb,yes,30,30 2006.173.04:00:40.61/vb/08,04,usb,yes,28,31 2006.173.04:00:40.84/vblo/01,629.99,yes,locked 2006.173.04:00:40.84/vblo/02,634.99,yes,locked 2006.173.04:00:40.84/vblo/03,649.99,yes,locked 2006.173.04:00:40.84/vblo/04,679.99,yes,locked 2006.173.04:00:40.84/vblo/05,709.99,yes,locked 2006.173.04:00:40.84/vblo/06,719.99,yes,locked 2006.173.04:00:40.84/vblo/07,734.99,yes,locked 2006.173.04:00:40.84/vblo/08,744.99,yes,locked 2006.173.04:00:40.99/vabw/8 2006.173.04:00:41.13/vbbw/8 2006.173.04:00:41.22/xfe/off,on,15.2 2006.173.04:00:41.61/ifatt/23,28,28,28 2006.173.04:00:42.08/fmout-gps/S +3.94E-07 2006.173.04:00:42.12:!2006.173.04:04:37 2006.173.04:04:37.01:data_valid=off 2006.173.04:04:37.02:"et 2006.173.04:04:37.02:!+3s 2006.173.04:04:40.05:"tape 2006.173.04:04:40.06:postob 2006.173.04:04:40.17/cable/+6.5091E-03 2006.173.04:04:40.18/wx/23.04,1006.1,79 2006.173.04:04:40.23/fmout-gps/S +3.95E-07 2006.173.04:04:40.24:scan_name=173-0408,jd0606,230 2006.173.04:04:40.24:source=0014+813,001708.47,813508.1,2000.0,neutral 2006.173.04:04:41.14#flagr#flagr/antenna,new-source 2006.173.04:04:41.15:checkk5 2006.173.04:04:41.49/chk_autoobs//k5ts1/ autoobs is running! 2006.173.04:04:41.83/chk_autoobs//k5ts2/ autoobs is running! 2006.173.04:04:42.18/chk_autoobs//k5ts3/ autoobs is running! 2006.173.04:04:42.51/chk_autoobs//k5ts4/ autoobs is running! 2006.173.04:04:42.85/chk_obsdata//k5ts1/T1730400??a.dat file size is correct (nominal:960MB, actual:956MB). 2006.173.04:04:43.18/chk_obsdata//k5ts2/T1730400??b.dat file size is correct (nominal:960MB, actual:956MB). 2006.173.04:04:43.52/chk_obsdata//k5ts3/T1730400??c.dat file size is correct (nominal:960MB, actual:956MB). 2006.173.04:04:43.85/chk_obsdata//k5ts4/T1730400??d.dat file size is correct (nominal:960MB, actual:956MB). 2006.173.04:04:44.50/k5log//k5ts1_log_newline 2006.173.04:04:45.15/k5log//k5ts2_log_newline 2006.173.04:04:45.81/k5log//k5ts3_log_newline 2006.173.04:04:46.46/k5log//k5ts4_log_newline 2006.173.04:04:46.48/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.04:04:46.48:setupk4=1 2006.173.04:04:46.48$setupk4/echo=on 2006.173.04:04:46.48$setupk4/pcalon 2006.173.04:04:46.48$pcalon/"no phase cal control is implemented here 2006.173.04:04:46.48$setupk4/"tpicd=stop 2006.173.04:04:46.48$setupk4/"rec=synch_on 2006.173.04:04:46.48$setupk4/"rec_mode=128 2006.173.04:04:46.48$setupk4/!* 2006.173.04:04:46.48$setupk4/recpk4 2006.173.04:04:46.48$recpk4/recpatch= 2006.173.04:04:46.49$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.04:04:46.49$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.04:04:46.49$setupk4/vck44 2006.173.04:04:46.49$vck44/valo=1,524.99 2006.173.04:04:46.49#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.04:04:46.49#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.04:04:46.49#ibcon#ireg 17 cls_cnt 0 2006.173.04:04:46.49#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.04:04:46.49#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.04:04:46.49#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.04:04:46.49#ibcon#enter wrdev, iclass 28, count 0 2006.173.04:04:46.49#ibcon#first serial, iclass 28, count 0 2006.173.04:04:46.49#ibcon#enter sib2, iclass 28, count 0 2006.173.04:04:46.49#ibcon#flushed, iclass 28, count 0 2006.173.04:04:46.49#ibcon#about to write, iclass 28, count 0 2006.173.04:04:46.49#ibcon#wrote, iclass 28, count 0 2006.173.04:04:46.49#ibcon#about to read 3, iclass 28, count 0 2006.173.04:04:46.50#ibcon#read 3, iclass 28, count 0 2006.173.04:04:46.50#ibcon#about to read 4, iclass 28, count 0 2006.173.04:04:46.50#ibcon#read 4, iclass 28, count 0 2006.173.04:04:46.50#ibcon#about to read 5, iclass 28, count 0 2006.173.04:04:46.50#ibcon#read 5, iclass 28, count 0 2006.173.04:04:46.50#ibcon#about to read 6, iclass 28, count 0 2006.173.04:04:46.50#ibcon#read 6, iclass 28, count 0 2006.173.04:04:46.50#ibcon#end of sib2, iclass 28, count 0 2006.173.04:04:46.50#ibcon#*mode == 0, iclass 28, count 0 2006.173.04:04:46.50#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.04:04:46.50#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.04:04:46.50#ibcon#*before write, iclass 28, count 0 2006.173.04:04:46.50#ibcon#enter sib2, iclass 28, count 0 2006.173.04:04:46.50#ibcon#flushed, iclass 28, count 0 2006.173.04:04:46.50#ibcon#about to write, iclass 28, count 0 2006.173.04:04:46.50#ibcon#wrote, iclass 28, count 0 2006.173.04:04:46.50#ibcon#about to read 3, iclass 28, count 0 2006.173.04:04:46.55#ibcon#read 3, iclass 28, count 0 2006.173.04:04:46.55#ibcon#about to read 4, iclass 28, count 0 2006.173.04:04:46.55#ibcon#read 4, iclass 28, count 0 2006.173.04:04:46.55#ibcon#about to read 5, iclass 28, count 0 2006.173.04:04:46.55#ibcon#read 5, iclass 28, count 0 2006.173.04:04:46.55#ibcon#about to read 6, iclass 28, count 0 2006.173.04:04:46.55#ibcon#read 6, iclass 28, count 0 2006.173.04:04:46.55#ibcon#end of sib2, iclass 28, count 0 2006.173.04:04:46.55#ibcon#*after write, iclass 28, count 0 2006.173.04:04:46.55#ibcon#*before return 0, iclass 28, count 0 2006.173.04:04:46.55#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.04:04:46.55#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.04:04:46.55#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.04:04:46.55#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.04:04:46.55$vck44/va=1,7 2006.173.04:04:46.55#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.04:04:46.55#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.04:04:46.55#ibcon#ireg 11 cls_cnt 2 2006.173.04:04:46.55#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.04:04:46.55#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.04:04:46.55#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.04:04:46.55#ibcon#enter wrdev, iclass 30, count 2 2006.173.04:04:46.55#ibcon#first serial, iclass 30, count 2 2006.173.04:04:46.55#ibcon#enter sib2, iclass 30, count 2 2006.173.04:04:46.55#ibcon#flushed, iclass 30, count 2 2006.173.04:04:46.55#ibcon#about to write, iclass 30, count 2 2006.173.04:04:46.55#ibcon#wrote, iclass 30, count 2 2006.173.04:04:46.55#ibcon#about to read 3, iclass 30, count 2 2006.173.04:04:46.57#ibcon#read 3, iclass 30, count 2 2006.173.04:04:46.57#ibcon#about to read 4, iclass 30, count 2 2006.173.04:04:46.57#ibcon#read 4, iclass 30, count 2 2006.173.04:04:46.57#ibcon#about to read 5, iclass 30, count 2 2006.173.04:04:46.57#ibcon#read 5, iclass 30, count 2 2006.173.04:04:46.57#ibcon#about to read 6, iclass 30, count 2 2006.173.04:04:46.57#ibcon#read 6, iclass 30, count 2 2006.173.04:04:46.57#ibcon#end of sib2, iclass 30, count 2 2006.173.04:04:46.57#ibcon#*mode == 0, iclass 30, count 2 2006.173.04:04:46.57#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.04:04:46.57#ibcon#[25=AT01-07\r\n] 2006.173.04:04:46.57#ibcon#*before write, iclass 30, count 2 2006.173.04:04:46.57#ibcon#enter sib2, iclass 30, count 2 2006.173.04:04:46.57#ibcon#flushed, iclass 30, count 2 2006.173.04:04:46.57#ibcon#about to write, iclass 30, count 2 2006.173.04:04:46.57#ibcon#wrote, iclass 30, count 2 2006.173.04:04:46.57#ibcon#about to read 3, iclass 30, count 2 2006.173.04:04:46.60#ibcon#read 3, iclass 30, count 2 2006.173.04:04:46.60#ibcon#about to read 4, iclass 30, count 2 2006.173.04:04:46.60#ibcon#read 4, iclass 30, count 2 2006.173.04:04:46.60#ibcon#about to read 5, iclass 30, count 2 2006.173.04:04:46.60#ibcon#read 5, iclass 30, count 2 2006.173.04:04:46.60#ibcon#about to read 6, iclass 30, count 2 2006.173.04:04:46.60#ibcon#read 6, iclass 30, count 2 2006.173.04:04:46.60#ibcon#end of sib2, iclass 30, count 2 2006.173.04:04:46.60#ibcon#*after write, iclass 30, count 2 2006.173.04:04:46.60#ibcon#*before return 0, iclass 30, count 2 2006.173.04:04:46.60#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.04:04:46.60#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.04:04:46.60#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.04:04:46.60#ibcon#ireg 7 cls_cnt 0 2006.173.04:04:46.60#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.04:04:46.72#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.04:04:46.72#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.04:04:46.72#ibcon#enter wrdev, iclass 30, count 0 2006.173.04:04:46.72#ibcon#first serial, iclass 30, count 0 2006.173.04:04:46.72#ibcon#enter sib2, iclass 30, count 0 2006.173.04:04:46.72#ibcon#flushed, iclass 30, count 0 2006.173.04:04:46.72#ibcon#about to write, iclass 30, count 0 2006.173.04:04:46.72#ibcon#wrote, iclass 30, count 0 2006.173.04:04:46.72#ibcon#about to read 3, iclass 30, count 0 2006.173.04:04:46.74#ibcon#read 3, iclass 30, count 0 2006.173.04:04:46.74#ibcon#about to read 4, iclass 30, count 0 2006.173.04:04:46.74#ibcon#read 4, iclass 30, count 0 2006.173.04:04:46.74#ibcon#about to read 5, iclass 30, count 0 2006.173.04:04:46.74#ibcon#read 5, iclass 30, count 0 2006.173.04:04:46.74#ibcon#about to read 6, iclass 30, count 0 2006.173.04:04:46.74#ibcon#read 6, iclass 30, count 0 2006.173.04:04:46.74#ibcon#end of sib2, iclass 30, count 0 2006.173.04:04:46.74#ibcon#*mode == 0, iclass 30, count 0 2006.173.04:04:46.74#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.04:04:46.74#ibcon#[25=USB\r\n] 2006.173.04:04:46.74#ibcon#*before write, iclass 30, count 0 2006.173.04:04:46.74#ibcon#enter sib2, iclass 30, count 0 2006.173.04:04:46.74#ibcon#flushed, iclass 30, count 0 2006.173.04:04:46.74#ibcon#about to write, iclass 30, count 0 2006.173.04:04:46.74#ibcon#wrote, iclass 30, count 0 2006.173.04:04:46.74#ibcon#about to read 3, iclass 30, count 0 2006.173.04:04:46.77#ibcon#read 3, iclass 30, count 0 2006.173.04:04:46.77#ibcon#about to read 4, iclass 30, count 0 2006.173.04:04:46.77#ibcon#read 4, iclass 30, count 0 2006.173.04:04:46.77#ibcon#about to read 5, iclass 30, count 0 2006.173.04:04:46.77#ibcon#read 5, iclass 30, count 0 2006.173.04:04:46.77#ibcon#about to read 6, iclass 30, count 0 2006.173.04:04:46.77#ibcon#read 6, iclass 30, count 0 2006.173.04:04:46.77#ibcon#end of sib2, iclass 30, count 0 2006.173.04:04:46.77#ibcon#*after write, iclass 30, count 0 2006.173.04:04:46.77#ibcon#*before return 0, iclass 30, count 0 2006.173.04:04:46.77#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.04:04:46.77#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.04:04:46.77#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.04:04:46.77#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.04:04:46.77$vck44/valo=2,534.99 2006.173.04:04:46.77#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.04:04:46.77#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.04:04:46.77#ibcon#ireg 17 cls_cnt 0 2006.173.04:04:46.77#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.04:04:46.77#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.04:04:46.77#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.04:04:46.77#ibcon#enter wrdev, iclass 32, count 0 2006.173.04:04:46.77#ibcon#first serial, iclass 32, count 0 2006.173.04:04:46.77#ibcon#enter sib2, iclass 32, count 0 2006.173.04:04:46.77#ibcon#flushed, iclass 32, count 0 2006.173.04:04:46.77#ibcon#about to write, iclass 32, count 0 2006.173.04:04:46.77#ibcon#wrote, iclass 32, count 0 2006.173.04:04:46.77#ibcon#about to read 3, iclass 32, count 0 2006.173.04:04:46.79#ibcon#read 3, iclass 32, count 0 2006.173.04:04:46.79#ibcon#about to read 4, iclass 32, count 0 2006.173.04:04:46.79#ibcon#read 4, iclass 32, count 0 2006.173.04:04:46.79#ibcon#about to read 5, iclass 32, count 0 2006.173.04:04:46.79#ibcon#read 5, iclass 32, count 0 2006.173.04:04:46.79#ibcon#about to read 6, iclass 32, count 0 2006.173.04:04:46.79#ibcon#read 6, iclass 32, count 0 2006.173.04:04:46.79#ibcon#end of sib2, iclass 32, count 0 2006.173.04:04:46.79#ibcon#*mode == 0, iclass 32, count 0 2006.173.04:04:46.79#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.04:04:46.79#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.04:04:46.79#ibcon#*before write, iclass 32, count 0 2006.173.04:04:46.79#ibcon#enter sib2, iclass 32, count 0 2006.173.04:04:46.79#ibcon#flushed, iclass 32, count 0 2006.173.04:04:46.79#ibcon#about to write, iclass 32, count 0 2006.173.04:04:46.79#ibcon#wrote, iclass 32, count 0 2006.173.04:04:46.79#ibcon#about to read 3, iclass 32, count 0 2006.173.04:04:46.83#ibcon#read 3, iclass 32, count 0 2006.173.04:04:46.83#ibcon#about to read 4, iclass 32, count 0 2006.173.04:04:46.83#ibcon#read 4, iclass 32, count 0 2006.173.04:04:46.83#ibcon#about to read 5, iclass 32, count 0 2006.173.04:04:46.83#ibcon#read 5, iclass 32, count 0 2006.173.04:04:46.83#ibcon#about to read 6, iclass 32, count 0 2006.173.04:04:46.83#ibcon#read 6, iclass 32, count 0 2006.173.04:04:46.83#ibcon#end of sib2, iclass 32, count 0 2006.173.04:04:46.83#ibcon#*after write, iclass 32, count 0 2006.173.04:04:46.83#ibcon#*before return 0, iclass 32, count 0 2006.173.04:04:46.83#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.04:04:46.83#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.04:04:46.83#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.04:04:46.83#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.04:04:46.83$vck44/va=2,6 2006.173.04:04:46.83#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.04:04:46.83#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.04:04:46.83#ibcon#ireg 11 cls_cnt 2 2006.173.04:04:46.83#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.04:04:46.89#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.04:04:46.89#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.04:04:46.89#ibcon#enter wrdev, iclass 34, count 2 2006.173.04:04:46.89#ibcon#first serial, iclass 34, count 2 2006.173.04:04:46.89#ibcon#enter sib2, iclass 34, count 2 2006.173.04:04:46.89#ibcon#flushed, iclass 34, count 2 2006.173.04:04:46.89#ibcon#about to write, iclass 34, count 2 2006.173.04:04:46.89#ibcon#wrote, iclass 34, count 2 2006.173.04:04:46.89#ibcon#about to read 3, iclass 34, count 2 2006.173.04:04:46.91#ibcon#read 3, iclass 34, count 2 2006.173.04:04:46.91#ibcon#about to read 4, iclass 34, count 2 2006.173.04:04:46.91#ibcon#read 4, iclass 34, count 2 2006.173.04:04:46.91#ibcon#about to read 5, iclass 34, count 2 2006.173.04:04:46.91#ibcon#read 5, iclass 34, count 2 2006.173.04:04:46.91#ibcon#about to read 6, iclass 34, count 2 2006.173.04:04:46.91#ibcon#read 6, iclass 34, count 2 2006.173.04:04:46.91#ibcon#end of sib2, iclass 34, count 2 2006.173.04:04:46.91#ibcon#*mode == 0, iclass 34, count 2 2006.173.04:04:46.91#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.04:04:46.91#ibcon#[25=AT02-06\r\n] 2006.173.04:04:46.91#ibcon#*before write, iclass 34, count 2 2006.173.04:04:46.91#ibcon#enter sib2, iclass 34, count 2 2006.173.04:04:46.91#ibcon#flushed, iclass 34, count 2 2006.173.04:04:46.91#ibcon#about to write, iclass 34, count 2 2006.173.04:04:46.91#ibcon#wrote, iclass 34, count 2 2006.173.04:04:46.91#ibcon#about to read 3, iclass 34, count 2 2006.173.04:04:46.94#ibcon#read 3, iclass 34, count 2 2006.173.04:04:46.94#ibcon#about to read 4, iclass 34, count 2 2006.173.04:04:46.94#ibcon#read 4, iclass 34, count 2 2006.173.04:04:46.94#ibcon#about to read 5, iclass 34, count 2 2006.173.04:04:46.94#ibcon#read 5, iclass 34, count 2 2006.173.04:04:46.94#ibcon#about to read 6, iclass 34, count 2 2006.173.04:04:46.94#ibcon#read 6, iclass 34, count 2 2006.173.04:04:46.94#ibcon#end of sib2, iclass 34, count 2 2006.173.04:04:46.94#ibcon#*after write, iclass 34, count 2 2006.173.04:04:46.94#ibcon#*before return 0, iclass 34, count 2 2006.173.04:04:46.94#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.04:04:46.94#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.04:04:46.94#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.04:04:46.94#ibcon#ireg 7 cls_cnt 0 2006.173.04:04:46.94#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.04:04:47.06#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.04:04:47.06#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.04:04:47.06#ibcon#enter wrdev, iclass 34, count 0 2006.173.04:04:47.06#ibcon#first serial, iclass 34, count 0 2006.173.04:04:47.06#ibcon#enter sib2, iclass 34, count 0 2006.173.04:04:47.06#ibcon#flushed, iclass 34, count 0 2006.173.04:04:47.06#ibcon#about to write, iclass 34, count 0 2006.173.04:04:47.06#ibcon#wrote, iclass 34, count 0 2006.173.04:04:47.06#ibcon#about to read 3, iclass 34, count 0 2006.173.04:04:47.08#ibcon#read 3, iclass 34, count 0 2006.173.04:04:47.08#ibcon#about to read 4, iclass 34, count 0 2006.173.04:04:47.08#ibcon#read 4, iclass 34, count 0 2006.173.04:04:47.08#ibcon#about to read 5, iclass 34, count 0 2006.173.04:04:47.08#ibcon#read 5, iclass 34, count 0 2006.173.04:04:47.08#ibcon#about to read 6, iclass 34, count 0 2006.173.04:04:47.08#ibcon#read 6, iclass 34, count 0 2006.173.04:04:47.08#ibcon#end of sib2, iclass 34, count 0 2006.173.04:04:47.08#ibcon#*mode == 0, iclass 34, count 0 2006.173.04:04:47.08#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.04:04:47.08#ibcon#[25=USB\r\n] 2006.173.04:04:47.08#ibcon#*before write, iclass 34, count 0 2006.173.04:04:47.08#ibcon#enter sib2, iclass 34, count 0 2006.173.04:04:47.08#ibcon#flushed, iclass 34, count 0 2006.173.04:04:47.08#ibcon#about to write, iclass 34, count 0 2006.173.04:04:47.08#ibcon#wrote, iclass 34, count 0 2006.173.04:04:47.08#ibcon#about to read 3, iclass 34, count 0 2006.173.04:04:47.11#ibcon#read 3, iclass 34, count 0 2006.173.04:04:47.11#ibcon#about to read 4, iclass 34, count 0 2006.173.04:04:47.11#ibcon#read 4, iclass 34, count 0 2006.173.04:04:47.11#ibcon#about to read 5, iclass 34, count 0 2006.173.04:04:47.11#ibcon#read 5, iclass 34, count 0 2006.173.04:04:47.11#ibcon#about to read 6, iclass 34, count 0 2006.173.04:04:47.11#ibcon#read 6, iclass 34, count 0 2006.173.04:04:47.11#ibcon#end of sib2, iclass 34, count 0 2006.173.04:04:47.11#ibcon#*after write, iclass 34, count 0 2006.173.04:04:47.11#ibcon#*before return 0, iclass 34, count 0 2006.173.04:04:47.11#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.04:04:47.11#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.04:04:47.11#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.04:04:47.11#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.04:04:47.11$vck44/valo=3,564.99 2006.173.04:04:47.11#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.04:04:47.11#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.04:04:47.11#ibcon#ireg 17 cls_cnt 0 2006.173.04:04:47.11#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.04:04:47.11#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.04:04:47.11#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.04:04:47.11#ibcon#enter wrdev, iclass 36, count 0 2006.173.04:04:47.11#ibcon#first serial, iclass 36, count 0 2006.173.04:04:47.11#ibcon#enter sib2, iclass 36, count 0 2006.173.04:04:47.11#ibcon#flushed, iclass 36, count 0 2006.173.04:04:47.11#ibcon#about to write, iclass 36, count 0 2006.173.04:04:47.11#ibcon#wrote, iclass 36, count 0 2006.173.04:04:47.11#ibcon#about to read 3, iclass 36, count 0 2006.173.04:04:47.13#ibcon#read 3, iclass 36, count 0 2006.173.04:04:47.13#ibcon#about to read 4, iclass 36, count 0 2006.173.04:04:47.13#ibcon#read 4, iclass 36, count 0 2006.173.04:04:47.13#ibcon#about to read 5, iclass 36, count 0 2006.173.04:04:47.13#ibcon#read 5, iclass 36, count 0 2006.173.04:04:47.13#ibcon#about to read 6, iclass 36, count 0 2006.173.04:04:47.13#ibcon#read 6, iclass 36, count 0 2006.173.04:04:47.13#ibcon#end of sib2, iclass 36, count 0 2006.173.04:04:47.13#ibcon#*mode == 0, iclass 36, count 0 2006.173.04:04:47.13#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.04:04:47.13#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.04:04:47.13#ibcon#*before write, iclass 36, count 0 2006.173.04:04:47.13#ibcon#enter sib2, iclass 36, count 0 2006.173.04:04:47.13#ibcon#flushed, iclass 36, count 0 2006.173.04:04:47.13#ibcon#about to write, iclass 36, count 0 2006.173.04:04:47.13#ibcon#wrote, iclass 36, count 0 2006.173.04:04:47.13#ibcon#about to read 3, iclass 36, count 0 2006.173.04:04:47.17#ibcon#read 3, iclass 36, count 0 2006.173.04:04:47.17#ibcon#about to read 4, iclass 36, count 0 2006.173.04:04:47.17#ibcon#read 4, iclass 36, count 0 2006.173.04:04:47.17#ibcon#about to read 5, iclass 36, count 0 2006.173.04:04:47.17#ibcon#read 5, iclass 36, count 0 2006.173.04:04:47.17#ibcon#about to read 6, iclass 36, count 0 2006.173.04:04:47.17#ibcon#read 6, iclass 36, count 0 2006.173.04:04:47.17#ibcon#end of sib2, iclass 36, count 0 2006.173.04:04:47.17#ibcon#*after write, iclass 36, count 0 2006.173.04:04:47.17#ibcon#*before return 0, iclass 36, count 0 2006.173.04:04:47.17#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.04:04:47.17#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.04:04:47.17#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.04:04:47.17#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.04:04:47.17$vck44/va=3,5 2006.173.04:04:47.17#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.04:04:47.17#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.04:04:47.17#ibcon#ireg 11 cls_cnt 2 2006.173.04:04:47.17#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.04:04:47.23#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.04:04:47.23#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.04:04:47.23#ibcon#enter wrdev, iclass 38, count 2 2006.173.04:04:47.23#ibcon#first serial, iclass 38, count 2 2006.173.04:04:47.23#ibcon#enter sib2, iclass 38, count 2 2006.173.04:04:47.23#ibcon#flushed, iclass 38, count 2 2006.173.04:04:47.23#ibcon#about to write, iclass 38, count 2 2006.173.04:04:47.23#ibcon#wrote, iclass 38, count 2 2006.173.04:04:47.23#ibcon#about to read 3, iclass 38, count 2 2006.173.04:04:47.25#ibcon#read 3, iclass 38, count 2 2006.173.04:04:47.25#ibcon#about to read 4, iclass 38, count 2 2006.173.04:04:47.25#ibcon#read 4, iclass 38, count 2 2006.173.04:04:47.25#ibcon#about to read 5, iclass 38, count 2 2006.173.04:04:47.25#ibcon#read 5, iclass 38, count 2 2006.173.04:04:47.25#ibcon#about to read 6, iclass 38, count 2 2006.173.04:04:47.25#ibcon#read 6, iclass 38, count 2 2006.173.04:04:47.25#ibcon#end of sib2, iclass 38, count 2 2006.173.04:04:47.25#ibcon#*mode == 0, iclass 38, count 2 2006.173.04:04:47.25#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.04:04:47.25#ibcon#[25=AT03-05\r\n] 2006.173.04:04:47.25#ibcon#*before write, iclass 38, count 2 2006.173.04:04:47.25#ibcon#enter sib2, iclass 38, count 2 2006.173.04:04:47.25#ibcon#flushed, iclass 38, count 2 2006.173.04:04:47.25#ibcon#about to write, iclass 38, count 2 2006.173.04:04:47.25#ibcon#wrote, iclass 38, count 2 2006.173.04:04:47.25#ibcon#about to read 3, iclass 38, count 2 2006.173.04:04:47.28#ibcon#read 3, iclass 38, count 2 2006.173.04:04:47.28#ibcon#about to read 4, iclass 38, count 2 2006.173.04:04:47.28#ibcon#read 4, iclass 38, count 2 2006.173.04:04:47.28#ibcon#about to read 5, iclass 38, count 2 2006.173.04:04:47.28#ibcon#read 5, iclass 38, count 2 2006.173.04:04:47.28#ibcon#about to read 6, iclass 38, count 2 2006.173.04:04:47.28#ibcon#read 6, iclass 38, count 2 2006.173.04:04:47.28#ibcon#end of sib2, iclass 38, count 2 2006.173.04:04:47.28#ibcon#*after write, iclass 38, count 2 2006.173.04:04:47.28#ibcon#*before return 0, iclass 38, count 2 2006.173.04:04:47.28#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.04:04:47.28#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.04:04:47.28#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.04:04:47.28#ibcon#ireg 7 cls_cnt 0 2006.173.04:04:47.28#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.04:04:47.40#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.04:04:47.40#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.04:04:47.40#ibcon#enter wrdev, iclass 38, count 0 2006.173.04:04:47.40#ibcon#first serial, iclass 38, count 0 2006.173.04:04:47.40#ibcon#enter sib2, iclass 38, count 0 2006.173.04:04:47.40#ibcon#flushed, iclass 38, count 0 2006.173.04:04:47.40#ibcon#about to write, iclass 38, count 0 2006.173.04:04:47.40#ibcon#wrote, iclass 38, count 0 2006.173.04:04:47.40#ibcon#about to read 3, iclass 38, count 0 2006.173.04:04:47.42#ibcon#read 3, iclass 38, count 0 2006.173.04:04:47.42#ibcon#about to read 4, iclass 38, count 0 2006.173.04:04:47.42#ibcon#read 4, iclass 38, count 0 2006.173.04:04:47.42#ibcon#about to read 5, iclass 38, count 0 2006.173.04:04:47.42#ibcon#read 5, iclass 38, count 0 2006.173.04:04:47.42#ibcon#about to read 6, iclass 38, count 0 2006.173.04:04:47.42#ibcon#read 6, iclass 38, count 0 2006.173.04:04:47.42#ibcon#end of sib2, iclass 38, count 0 2006.173.04:04:47.42#ibcon#*mode == 0, iclass 38, count 0 2006.173.04:04:47.42#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.04:04:47.42#ibcon#[25=USB\r\n] 2006.173.04:04:47.42#ibcon#*before write, iclass 38, count 0 2006.173.04:04:47.42#ibcon#enter sib2, iclass 38, count 0 2006.173.04:04:47.42#ibcon#flushed, iclass 38, count 0 2006.173.04:04:47.42#ibcon#about to write, iclass 38, count 0 2006.173.04:04:47.42#ibcon#wrote, iclass 38, count 0 2006.173.04:04:47.42#ibcon#about to read 3, iclass 38, count 0 2006.173.04:04:47.45#ibcon#read 3, iclass 38, count 0 2006.173.04:04:47.45#ibcon#about to read 4, iclass 38, count 0 2006.173.04:04:47.45#ibcon#read 4, iclass 38, count 0 2006.173.04:04:47.45#ibcon#about to read 5, iclass 38, count 0 2006.173.04:04:47.45#ibcon#read 5, iclass 38, count 0 2006.173.04:04:47.45#ibcon#about to read 6, iclass 38, count 0 2006.173.04:04:47.45#ibcon#read 6, iclass 38, count 0 2006.173.04:04:47.45#ibcon#end of sib2, iclass 38, count 0 2006.173.04:04:47.45#ibcon#*after write, iclass 38, count 0 2006.173.04:04:47.45#ibcon#*before return 0, iclass 38, count 0 2006.173.04:04:47.45#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.04:04:47.45#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.04:04:47.45#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.04:04:47.45#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.04:04:47.45$vck44/valo=4,624.99 2006.173.04:04:47.45#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.04:04:47.45#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.04:04:47.45#ibcon#ireg 17 cls_cnt 0 2006.173.04:04:47.45#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.04:04:47.45#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.04:04:47.45#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.04:04:47.45#ibcon#enter wrdev, iclass 40, count 0 2006.173.04:04:47.45#ibcon#first serial, iclass 40, count 0 2006.173.04:04:47.45#ibcon#enter sib2, iclass 40, count 0 2006.173.04:04:47.45#ibcon#flushed, iclass 40, count 0 2006.173.04:04:47.45#ibcon#about to write, iclass 40, count 0 2006.173.04:04:47.45#ibcon#wrote, iclass 40, count 0 2006.173.04:04:47.45#ibcon#about to read 3, iclass 40, count 0 2006.173.04:04:47.47#ibcon#read 3, iclass 40, count 0 2006.173.04:04:47.47#ibcon#about to read 4, iclass 40, count 0 2006.173.04:04:47.47#ibcon#read 4, iclass 40, count 0 2006.173.04:04:47.47#ibcon#about to read 5, iclass 40, count 0 2006.173.04:04:47.47#ibcon#read 5, iclass 40, count 0 2006.173.04:04:47.47#ibcon#about to read 6, iclass 40, count 0 2006.173.04:04:47.47#ibcon#read 6, iclass 40, count 0 2006.173.04:04:47.47#ibcon#end of sib2, iclass 40, count 0 2006.173.04:04:47.47#ibcon#*mode == 0, iclass 40, count 0 2006.173.04:04:47.47#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.04:04:47.47#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.04:04:47.47#ibcon#*before write, iclass 40, count 0 2006.173.04:04:47.47#ibcon#enter sib2, iclass 40, count 0 2006.173.04:04:47.47#ibcon#flushed, iclass 40, count 0 2006.173.04:04:47.47#ibcon#about to write, iclass 40, count 0 2006.173.04:04:47.47#ibcon#wrote, iclass 40, count 0 2006.173.04:04:47.47#ibcon#about to read 3, iclass 40, count 0 2006.173.04:04:47.51#ibcon#read 3, iclass 40, count 0 2006.173.04:04:47.51#ibcon#about to read 4, iclass 40, count 0 2006.173.04:04:47.51#ibcon#read 4, iclass 40, count 0 2006.173.04:04:47.51#ibcon#about to read 5, iclass 40, count 0 2006.173.04:04:47.51#ibcon#read 5, iclass 40, count 0 2006.173.04:04:47.51#ibcon#about to read 6, iclass 40, count 0 2006.173.04:04:47.51#ibcon#read 6, iclass 40, count 0 2006.173.04:04:47.51#ibcon#end of sib2, iclass 40, count 0 2006.173.04:04:47.51#ibcon#*after write, iclass 40, count 0 2006.173.04:04:47.51#ibcon#*before return 0, iclass 40, count 0 2006.173.04:04:47.51#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.04:04:47.51#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.04:04:47.51#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.04:04:47.51#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.04:04:47.51$vck44/va=4,6 2006.173.04:04:47.51#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.04:04:47.51#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.04:04:47.51#ibcon#ireg 11 cls_cnt 2 2006.173.04:04:47.51#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.04:04:47.57#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.04:04:47.57#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.04:04:47.57#ibcon#enter wrdev, iclass 4, count 2 2006.173.04:04:47.57#ibcon#first serial, iclass 4, count 2 2006.173.04:04:47.57#ibcon#enter sib2, iclass 4, count 2 2006.173.04:04:47.57#ibcon#flushed, iclass 4, count 2 2006.173.04:04:47.57#ibcon#about to write, iclass 4, count 2 2006.173.04:04:47.57#ibcon#wrote, iclass 4, count 2 2006.173.04:04:47.57#ibcon#about to read 3, iclass 4, count 2 2006.173.04:04:47.59#ibcon#read 3, iclass 4, count 2 2006.173.04:04:47.59#ibcon#about to read 4, iclass 4, count 2 2006.173.04:04:47.59#ibcon#read 4, iclass 4, count 2 2006.173.04:04:47.59#ibcon#about to read 5, iclass 4, count 2 2006.173.04:04:47.59#ibcon#read 5, iclass 4, count 2 2006.173.04:04:47.59#ibcon#about to read 6, iclass 4, count 2 2006.173.04:04:47.59#ibcon#read 6, iclass 4, count 2 2006.173.04:04:47.59#ibcon#end of sib2, iclass 4, count 2 2006.173.04:04:47.59#ibcon#*mode == 0, iclass 4, count 2 2006.173.04:04:47.59#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.04:04:47.59#ibcon#[25=AT04-06\r\n] 2006.173.04:04:47.59#ibcon#*before write, iclass 4, count 2 2006.173.04:04:47.59#ibcon#enter sib2, iclass 4, count 2 2006.173.04:04:47.59#ibcon#flushed, iclass 4, count 2 2006.173.04:04:47.59#ibcon#about to write, iclass 4, count 2 2006.173.04:04:47.59#ibcon#wrote, iclass 4, count 2 2006.173.04:04:47.59#ibcon#about to read 3, iclass 4, count 2 2006.173.04:04:47.62#ibcon#read 3, iclass 4, count 2 2006.173.04:04:47.62#ibcon#about to read 4, iclass 4, count 2 2006.173.04:04:47.62#ibcon#read 4, iclass 4, count 2 2006.173.04:04:47.62#ibcon#about to read 5, iclass 4, count 2 2006.173.04:04:47.62#ibcon#read 5, iclass 4, count 2 2006.173.04:04:47.62#ibcon#about to read 6, iclass 4, count 2 2006.173.04:04:47.62#ibcon#read 6, iclass 4, count 2 2006.173.04:04:47.62#ibcon#end of sib2, iclass 4, count 2 2006.173.04:04:47.62#ibcon#*after write, iclass 4, count 2 2006.173.04:04:47.62#ibcon#*before return 0, iclass 4, count 2 2006.173.04:04:47.62#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.04:04:47.62#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.04:04:47.62#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.04:04:47.62#ibcon#ireg 7 cls_cnt 0 2006.173.04:04:47.62#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.04:04:47.74#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.04:04:47.74#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.04:04:47.74#ibcon#enter wrdev, iclass 4, count 0 2006.173.04:04:47.74#ibcon#first serial, iclass 4, count 0 2006.173.04:04:47.74#ibcon#enter sib2, iclass 4, count 0 2006.173.04:04:47.74#ibcon#flushed, iclass 4, count 0 2006.173.04:04:47.74#ibcon#about to write, iclass 4, count 0 2006.173.04:04:47.74#ibcon#wrote, iclass 4, count 0 2006.173.04:04:47.74#ibcon#about to read 3, iclass 4, count 0 2006.173.04:04:47.76#ibcon#read 3, iclass 4, count 0 2006.173.04:04:47.76#ibcon#about to read 4, iclass 4, count 0 2006.173.04:04:47.76#ibcon#read 4, iclass 4, count 0 2006.173.04:04:47.76#ibcon#about to read 5, iclass 4, count 0 2006.173.04:04:47.76#ibcon#read 5, iclass 4, count 0 2006.173.04:04:47.76#ibcon#about to read 6, iclass 4, count 0 2006.173.04:04:47.76#ibcon#read 6, iclass 4, count 0 2006.173.04:04:47.76#ibcon#end of sib2, iclass 4, count 0 2006.173.04:04:47.76#ibcon#*mode == 0, iclass 4, count 0 2006.173.04:04:47.76#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.04:04:47.76#ibcon#[25=USB\r\n] 2006.173.04:04:47.76#ibcon#*before write, iclass 4, count 0 2006.173.04:04:47.76#ibcon#enter sib2, iclass 4, count 0 2006.173.04:04:47.76#ibcon#flushed, iclass 4, count 0 2006.173.04:04:47.76#ibcon#about to write, iclass 4, count 0 2006.173.04:04:47.76#ibcon#wrote, iclass 4, count 0 2006.173.04:04:47.76#ibcon#about to read 3, iclass 4, count 0 2006.173.04:04:47.79#ibcon#read 3, iclass 4, count 0 2006.173.04:04:47.79#ibcon#about to read 4, iclass 4, count 0 2006.173.04:04:47.79#ibcon#read 4, iclass 4, count 0 2006.173.04:04:47.79#ibcon#about to read 5, iclass 4, count 0 2006.173.04:04:47.79#ibcon#read 5, iclass 4, count 0 2006.173.04:04:47.79#ibcon#about to read 6, iclass 4, count 0 2006.173.04:04:47.79#ibcon#read 6, iclass 4, count 0 2006.173.04:04:47.79#ibcon#end of sib2, iclass 4, count 0 2006.173.04:04:47.79#ibcon#*after write, iclass 4, count 0 2006.173.04:04:47.79#ibcon#*before return 0, iclass 4, count 0 2006.173.04:04:47.79#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.04:04:47.79#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.04:04:47.79#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.04:04:47.79#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.04:04:47.79$vck44/valo=5,734.99 2006.173.04:04:47.79#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.04:04:47.79#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.04:04:47.79#ibcon#ireg 17 cls_cnt 0 2006.173.04:04:47.79#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.04:04:47.79#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.04:04:47.79#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.04:04:47.79#ibcon#enter wrdev, iclass 6, count 0 2006.173.04:04:47.79#ibcon#first serial, iclass 6, count 0 2006.173.04:04:47.79#ibcon#enter sib2, iclass 6, count 0 2006.173.04:04:47.79#ibcon#flushed, iclass 6, count 0 2006.173.04:04:47.79#ibcon#about to write, iclass 6, count 0 2006.173.04:04:47.79#ibcon#wrote, iclass 6, count 0 2006.173.04:04:47.79#ibcon#about to read 3, iclass 6, count 0 2006.173.04:04:47.81#ibcon#read 3, iclass 6, count 0 2006.173.04:04:47.81#ibcon#about to read 4, iclass 6, count 0 2006.173.04:04:47.81#ibcon#read 4, iclass 6, count 0 2006.173.04:04:47.81#ibcon#about to read 5, iclass 6, count 0 2006.173.04:04:47.81#ibcon#read 5, iclass 6, count 0 2006.173.04:04:47.81#ibcon#about to read 6, iclass 6, count 0 2006.173.04:04:47.81#ibcon#read 6, iclass 6, count 0 2006.173.04:04:47.81#ibcon#end of sib2, iclass 6, count 0 2006.173.04:04:47.81#ibcon#*mode == 0, iclass 6, count 0 2006.173.04:04:47.81#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.04:04:47.81#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.04:04:47.81#ibcon#*before write, iclass 6, count 0 2006.173.04:04:47.81#ibcon#enter sib2, iclass 6, count 0 2006.173.04:04:47.81#ibcon#flushed, iclass 6, count 0 2006.173.04:04:47.81#ibcon#about to write, iclass 6, count 0 2006.173.04:04:47.81#ibcon#wrote, iclass 6, count 0 2006.173.04:04:47.81#ibcon#about to read 3, iclass 6, count 0 2006.173.04:04:47.85#ibcon#read 3, iclass 6, count 0 2006.173.04:04:47.85#ibcon#about to read 4, iclass 6, count 0 2006.173.04:04:47.85#ibcon#read 4, iclass 6, count 0 2006.173.04:04:47.85#ibcon#about to read 5, iclass 6, count 0 2006.173.04:04:47.85#ibcon#read 5, iclass 6, count 0 2006.173.04:04:47.85#ibcon#about to read 6, iclass 6, count 0 2006.173.04:04:47.85#ibcon#read 6, iclass 6, count 0 2006.173.04:04:47.85#ibcon#end of sib2, iclass 6, count 0 2006.173.04:04:47.85#ibcon#*after write, iclass 6, count 0 2006.173.04:04:47.85#ibcon#*before return 0, iclass 6, count 0 2006.173.04:04:47.85#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.04:04:47.85#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.04:04:47.85#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.04:04:47.85#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.04:04:47.85$vck44/va=5,4 2006.173.04:04:47.85#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.04:04:47.85#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.04:04:47.85#ibcon#ireg 11 cls_cnt 2 2006.173.04:04:47.85#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.04:04:47.91#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.04:04:47.91#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.04:04:47.91#ibcon#enter wrdev, iclass 10, count 2 2006.173.04:04:47.91#ibcon#first serial, iclass 10, count 2 2006.173.04:04:47.91#ibcon#enter sib2, iclass 10, count 2 2006.173.04:04:47.91#ibcon#flushed, iclass 10, count 2 2006.173.04:04:47.91#ibcon#about to write, iclass 10, count 2 2006.173.04:04:47.91#ibcon#wrote, iclass 10, count 2 2006.173.04:04:47.91#ibcon#about to read 3, iclass 10, count 2 2006.173.04:04:47.93#ibcon#read 3, iclass 10, count 2 2006.173.04:04:47.93#ibcon#about to read 4, iclass 10, count 2 2006.173.04:04:47.93#ibcon#read 4, iclass 10, count 2 2006.173.04:04:47.93#ibcon#about to read 5, iclass 10, count 2 2006.173.04:04:47.93#ibcon#read 5, iclass 10, count 2 2006.173.04:04:47.93#ibcon#about to read 6, iclass 10, count 2 2006.173.04:04:47.93#ibcon#read 6, iclass 10, count 2 2006.173.04:04:47.93#ibcon#end of sib2, iclass 10, count 2 2006.173.04:04:47.93#ibcon#*mode == 0, iclass 10, count 2 2006.173.04:04:47.93#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.04:04:47.93#ibcon#[25=AT05-04\r\n] 2006.173.04:04:47.93#ibcon#*before write, iclass 10, count 2 2006.173.04:04:47.93#ibcon#enter sib2, iclass 10, count 2 2006.173.04:04:47.93#ibcon#flushed, iclass 10, count 2 2006.173.04:04:47.93#ibcon#about to write, iclass 10, count 2 2006.173.04:04:47.93#ibcon#wrote, iclass 10, count 2 2006.173.04:04:47.93#ibcon#about to read 3, iclass 10, count 2 2006.173.04:04:47.96#ibcon#read 3, iclass 10, count 2 2006.173.04:04:47.96#ibcon#about to read 4, iclass 10, count 2 2006.173.04:04:47.96#ibcon#read 4, iclass 10, count 2 2006.173.04:04:47.96#ibcon#about to read 5, iclass 10, count 2 2006.173.04:04:47.96#ibcon#read 5, iclass 10, count 2 2006.173.04:04:47.96#ibcon#about to read 6, iclass 10, count 2 2006.173.04:04:47.96#ibcon#read 6, iclass 10, count 2 2006.173.04:04:47.96#ibcon#end of sib2, iclass 10, count 2 2006.173.04:04:47.96#ibcon#*after write, iclass 10, count 2 2006.173.04:04:47.96#ibcon#*before return 0, iclass 10, count 2 2006.173.04:04:47.96#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.04:04:47.96#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.04:04:47.96#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.04:04:47.96#ibcon#ireg 7 cls_cnt 0 2006.173.04:04:47.96#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.04:04:48.08#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.04:04:48.08#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.04:04:48.08#ibcon#enter wrdev, iclass 10, count 0 2006.173.04:04:48.08#ibcon#first serial, iclass 10, count 0 2006.173.04:04:48.08#ibcon#enter sib2, iclass 10, count 0 2006.173.04:04:48.08#ibcon#flushed, iclass 10, count 0 2006.173.04:04:48.08#ibcon#about to write, iclass 10, count 0 2006.173.04:04:48.08#ibcon#wrote, iclass 10, count 0 2006.173.04:04:48.08#ibcon#about to read 3, iclass 10, count 0 2006.173.04:04:48.10#ibcon#read 3, iclass 10, count 0 2006.173.04:04:48.10#ibcon#about to read 4, iclass 10, count 0 2006.173.04:04:48.10#ibcon#read 4, iclass 10, count 0 2006.173.04:04:48.10#ibcon#about to read 5, iclass 10, count 0 2006.173.04:04:48.10#ibcon#read 5, iclass 10, count 0 2006.173.04:04:48.10#ibcon#about to read 6, iclass 10, count 0 2006.173.04:04:48.10#ibcon#read 6, iclass 10, count 0 2006.173.04:04:48.10#ibcon#end of sib2, iclass 10, count 0 2006.173.04:04:48.10#ibcon#*mode == 0, iclass 10, count 0 2006.173.04:04:48.10#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.04:04:48.10#ibcon#[25=USB\r\n] 2006.173.04:04:48.10#ibcon#*before write, iclass 10, count 0 2006.173.04:04:48.10#ibcon#enter sib2, iclass 10, count 0 2006.173.04:04:48.10#ibcon#flushed, iclass 10, count 0 2006.173.04:04:48.10#ibcon#about to write, iclass 10, count 0 2006.173.04:04:48.10#ibcon#wrote, iclass 10, count 0 2006.173.04:04:48.10#ibcon#about to read 3, iclass 10, count 0 2006.173.04:04:48.13#ibcon#read 3, iclass 10, count 0 2006.173.04:04:48.13#ibcon#about to read 4, iclass 10, count 0 2006.173.04:04:48.13#ibcon#read 4, iclass 10, count 0 2006.173.04:04:48.13#ibcon#about to read 5, iclass 10, count 0 2006.173.04:04:48.13#ibcon#read 5, iclass 10, count 0 2006.173.04:04:48.13#ibcon#about to read 6, iclass 10, count 0 2006.173.04:04:48.13#ibcon#read 6, iclass 10, count 0 2006.173.04:04:48.13#ibcon#end of sib2, iclass 10, count 0 2006.173.04:04:48.13#ibcon#*after write, iclass 10, count 0 2006.173.04:04:48.13#ibcon#*before return 0, iclass 10, count 0 2006.173.04:04:48.13#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.04:04:48.13#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.04:04:48.13#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.04:04:48.13#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.04:04:48.13$vck44/valo=6,814.99 2006.173.04:04:48.13#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.04:04:48.13#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.04:04:48.13#ibcon#ireg 17 cls_cnt 0 2006.173.04:04:48.13#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.04:04:48.13#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.04:04:48.13#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.04:04:48.13#ibcon#enter wrdev, iclass 12, count 0 2006.173.04:04:48.13#ibcon#first serial, iclass 12, count 0 2006.173.04:04:48.13#ibcon#enter sib2, iclass 12, count 0 2006.173.04:04:48.13#ibcon#flushed, iclass 12, count 0 2006.173.04:04:48.13#ibcon#about to write, iclass 12, count 0 2006.173.04:04:48.13#ibcon#wrote, iclass 12, count 0 2006.173.04:04:48.13#ibcon#about to read 3, iclass 12, count 0 2006.173.04:04:48.15#ibcon#read 3, iclass 12, count 0 2006.173.04:04:48.15#ibcon#about to read 4, iclass 12, count 0 2006.173.04:04:48.15#ibcon#read 4, iclass 12, count 0 2006.173.04:04:48.15#ibcon#about to read 5, iclass 12, count 0 2006.173.04:04:48.15#ibcon#read 5, iclass 12, count 0 2006.173.04:04:48.15#ibcon#about to read 6, iclass 12, count 0 2006.173.04:04:48.15#ibcon#read 6, iclass 12, count 0 2006.173.04:04:48.15#ibcon#end of sib2, iclass 12, count 0 2006.173.04:04:48.15#ibcon#*mode == 0, iclass 12, count 0 2006.173.04:04:48.15#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.04:04:48.15#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.04:04:48.15#ibcon#*before write, iclass 12, count 0 2006.173.04:04:48.15#ibcon#enter sib2, iclass 12, count 0 2006.173.04:04:48.15#ibcon#flushed, iclass 12, count 0 2006.173.04:04:48.15#ibcon#about to write, iclass 12, count 0 2006.173.04:04:48.15#ibcon#wrote, iclass 12, count 0 2006.173.04:04:48.15#ibcon#about to read 3, iclass 12, count 0 2006.173.04:04:48.19#ibcon#read 3, iclass 12, count 0 2006.173.04:04:48.19#ibcon#about to read 4, iclass 12, count 0 2006.173.04:04:48.19#ibcon#read 4, iclass 12, count 0 2006.173.04:04:48.19#ibcon#about to read 5, iclass 12, count 0 2006.173.04:04:48.19#ibcon#read 5, iclass 12, count 0 2006.173.04:04:48.19#ibcon#about to read 6, iclass 12, count 0 2006.173.04:04:48.19#ibcon#read 6, iclass 12, count 0 2006.173.04:04:48.19#ibcon#end of sib2, iclass 12, count 0 2006.173.04:04:48.19#ibcon#*after write, iclass 12, count 0 2006.173.04:04:48.19#ibcon#*before return 0, iclass 12, count 0 2006.173.04:04:48.19#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.04:04:48.19#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.04:04:48.19#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.04:04:48.19#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.04:04:48.19$vck44/va=6,3 2006.173.04:04:48.19#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.04:04:48.19#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.04:04:48.19#ibcon#ireg 11 cls_cnt 2 2006.173.04:04:48.19#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.04:04:48.25#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.04:04:48.25#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.04:04:48.25#ibcon#enter wrdev, iclass 14, count 2 2006.173.04:04:48.25#ibcon#first serial, iclass 14, count 2 2006.173.04:04:48.25#ibcon#enter sib2, iclass 14, count 2 2006.173.04:04:48.25#ibcon#flushed, iclass 14, count 2 2006.173.04:04:48.25#ibcon#about to write, iclass 14, count 2 2006.173.04:04:48.25#ibcon#wrote, iclass 14, count 2 2006.173.04:04:48.25#ibcon#about to read 3, iclass 14, count 2 2006.173.04:04:48.27#ibcon#read 3, iclass 14, count 2 2006.173.04:04:48.27#ibcon#about to read 4, iclass 14, count 2 2006.173.04:04:48.27#ibcon#read 4, iclass 14, count 2 2006.173.04:04:48.27#ibcon#about to read 5, iclass 14, count 2 2006.173.04:04:48.27#ibcon#read 5, iclass 14, count 2 2006.173.04:04:48.27#ibcon#about to read 6, iclass 14, count 2 2006.173.04:04:48.27#ibcon#read 6, iclass 14, count 2 2006.173.04:04:48.27#ibcon#end of sib2, iclass 14, count 2 2006.173.04:04:48.27#ibcon#*mode == 0, iclass 14, count 2 2006.173.04:04:48.27#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.04:04:48.27#ibcon#[25=AT06-03\r\n] 2006.173.04:04:48.27#ibcon#*before write, iclass 14, count 2 2006.173.04:04:48.27#ibcon#enter sib2, iclass 14, count 2 2006.173.04:04:48.27#ibcon#flushed, iclass 14, count 2 2006.173.04:04:48.27#ibcon#about to write, iclass 14, count 2 2006.173.04:04:48.27#ibcon#wrote, iclass 14, count 2 2006.173.04:04:48.27#ibcon#about to read 3, iclass 14, count 2 2006.173.04:04:48.30#ibcon#read 3, iclass 14, count 2 2006.173.04:04:48.30#ibcon#about to read 4, iclass 14, count 2 2006.173.04:04:48.30#ibcon#read 4, iclass 14, count 2 2006.173.04:04:48.30#ibcon#about to read 5, iclass 14, count 2 2006.173.04:04:48.30#ibcon#read 5, iclass 14, count 2 2006.173.04:04:48.30#ibcon#about to read 6, iclass 14, count 2 2006.173.04:04:48.30#ibcon#read 6, iclass 14, count 2 2006.173.04:04:48.30#ibcon#end of sib2, iclass 14, count 2 2006.173.04:04:48.30#ibcon#*after write, iclass 14, count 2 2006.173.04:04:48.30#ibcon#*before return 0, iclass 14, count 2 2006.173.04:04:48.30#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.04:04:48.30#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.04:04:48.30#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.04:04:48.30#ibcon#ireg 7 cls_cnt 0 2006.173.04:04:48.30#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.04:04:48.42#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.04:04:48.42#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.04:04:48.42#ibcon#enter wrdev, iclass 14, count 0 2006.173.04:04:48.42#ibcon#first serial, iclass 14, count 0 2006.173.04:04:48.42#ibcon#enter sib2, iclass 14, count 0 2006.173.04:04:48.42#ibcon#flushed, iclass 14, count 0 2006.173.04:04:48.42#ibcon#about to write, iclass 14, count 0 2006.173.04:04:48.42#ibcon#wrote, iclass 14, count 0 2006.173.04:04:48.42#ibcon#about to read 3, iclass 14, count 0 2006.173.04:04:48.44#ibcon#read 3, iclass 14, count 0 2006.173.04:04:48.44#ibcon#about to read 4, iclass 14, count 0 2006.173.04:04:48.44#ibcon#read 4, iclass 14, count 0 2006.173.04:04:48.44#ibcon#about to read 5, iclass 14, count 0 2006.173.04:04:48.44#ibcon#read 5, iclass 14, count 0 2006.173.04:04:48.44#ibcon#about to read 6, iclass 14, count 0 2006.173.04:04:48.44#ibcon#read 6, iclass 14, count 0 2006.173.04:04:48.44#ibcon#end of sib2, iclass 14, count 0 2006.173.04:04:48.44#ibcon#*mode == 0, iclass 14, count 0 2006.173.04:04:48.44#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.04:04:48.44#ibcon#[25=USB\r\n] 2006.173.04:04:48.44#ibcon#*before write, iclass 14, count 0 2006.173.04:04:48.44#ibcon#enter sib2, iclass 14, count 0 2006.173.04:04:48.44#ibcon#flushed, iclass 14, count 0 2006.173.04:04:48.44#ibcon#about to write, iclass 14, count 0 2006.173.04:04:48.44#ibcon#wrote, iclass 14, count 0 2006.173.04:04:48.44#ibcon#about to read 3, iclass 14, count 0 2006.173.04:04:48.47#ibcon#read 3, iclass 14, count 0 2006.173.04:04:48.47#ibcon#about to read 4, iclass 14, count 0 2006.173.04:04:48.47#ibcon#read 4, iclass 14, count 0 2006.173.04:04:48.47#ibcon#about to read 5, iclass 14, count 0 2006.173.04:04:48.47#ibcon#read 5, iclass 14, count 0 2006.173.04:04:48.47#ibcon#about to read 6, iclass 14, count 0 2006.173.04:04:48.47#ibcon#read 6, iclass 14, count 0 2006.173.04:04:48.47#ibcon#end of sib2, iclass 14, count 0 2006.173.04:04:48.47#ibcon#*after write, iclass 14, count 0 2006.173.04:04:48.47#ibcon#*before return 0, iclass 14, count 0 2006.173.04:04:48.47#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.04:04:48.47#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.04:04:48.47#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.04:04:48.47#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.04:04:48.47$vck44/valo=7,864.99 2006.173.04:04:48.47#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.04:04:48.47#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.04:04:48.47#ibcon#ireg 17 cls_cnt 0 2006.173.04:04:48.47#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.04:04:48.47#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.04:04:48.47#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.04:04:48.47#ibcon#enter wrdev, iclass 16, count 0 2006.173.04:04:48.47#ibcon#first serial, iclass 16, count 0 2006.173.04:04:48.47#ibcon#enter sib2, iclass 16, count 0 2006.173.04:04:48.47#ibcon#flushed, iclass 16, count 0 2006.173.04:04:48.47#ibcon#about to write, iclass 16, count 0 2006.173.04:04:48.47#ibcon#wrote, iclass 16, count 0 2006.173.04:04:48.47#ibcon#about to read 3, iclass 16, count 0 2006.173.04:04:48.49#ibcon#read 3, iclass 16, count 0 2006.173.04:04:48.49#ibcon#about to read 4, iclass 16, count 0 2006.173.04:04:48.49#ibcon#read 4, iclass 16, count 0 2006.173.04:04:48.49#ibcon#about to read 5, iclass 16, count 0 2006.173.04:04:48.49#ibcon#read 5, iclass 16, count 0 2006.173.04:04:48.49#ibcon#about to read 6, iclass 16, count 0 2006.173.04:04:48.49#ibcon#read 6, iclass 16, count 0 2006.173.04:04:48.49#ibcon#end of sib2, iclass 16, count 0 2006.173.04:04:48.49#ibcon#*mode == 0, iclass 16, count 0 2006.173.04:04:48.49#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.04:04:48.49#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.04:04:48.49#ibcon#*before write, iclass 16, count 0 2006.173.04:04:48.49#ibcon#enter sib2, iclass 16, count 0 2006.173.04:04:48.49#ibcon#flushed, iclass 16, count 0 2006.173.04:04:48.49#ibcon#about to write, iclass 16, count 0 2006.173.04:04:48.49#ibcon#wrote, iclass 16, count 0 2006.173.04:04:48.49#ibcon#about to read 3, iclass 16, count 0 2006.173.04:04:48.53#ibcon#read 3, iclass 16, count 0 2006.173.04:04:48.53#ibcon#about to read 4, iclass 16, count 0 2006.173.04:04:48.53#ibcon#read 4, iclass 16, count 0 2006.173.04:04:48.53#ibcon#about to read 5, iclass 16, count 0 2006.173.04:04:48.53#ibcon#read 5, iclass 16, count 0 2006.173.04:04:48.53#ibcon#about to read 6, iclass 16, count 0 2006.173.04:04:48.53#ibcon#read 6, iclass 16, count 0 2006.173.04:04:48.53#ibcon#end of sib2, iclass 16, count 0 2006.173.04:04:48.53#ibcon#*after write, iclass 16, count 0 2006.173.04:04:48.53#ibcon#*before return 0, iclass 16, count 0 2006.173.04:04:48.53#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.04:04:48.53#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.04:04:48.53#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.04:04:48.53#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.04:04:48.53$vck44/va=7,4 2006.173.04:04:48.53#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.04:04:48.53#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.04:04:48.53#ibcon#ireg 11 cls_cnt 2 2006.173.04:04:48.53#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.04:04:48.59#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.04:04:48.59#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.04:04:48.59#ibcon#enter wrdev, iclass 18, count 2 2006.173.04:04:48.59#ibcon#first serial, iclass 18, count 2 2006.173.04:04:48.59#ibcon#enter sib2, iclass 18, count 2 2006.173.04:04:48.59#ibcon#flushed, iclass 18, count 2 2006.173.04:04:48.59#ibcon#about to write, iclass 18, count 2 2006.173.04:04:48.59#ibcon#wrote, iclass 18, count 2 2006.173.04:04:48.59#ibcon#about to read 3, iclass 18, count 2 2006.173.04:04:48.61#ibcon#read 3, iclass 18, count 2 2006.173.04:04:48.61#ibcon#about to read 4, iclass 18, count 2 2006.173.04:04:48.61#ibcon#read 4, iclass 18, count 2 2006.173.04:04:48.61#ibcon#about to read 5, iclass 18, count 2 2006.173.04:04:48.61#ibcon#read 5, iclass 18, count 2 2006.173.04:04:48.61#ibcon#about to read 6, iclass 18, count 2 2006.173.04:04:48.61#ibcon#read 6, iclass 18, count 2 2006.173.04:04:48.61#ibcon#end of sib2, iclass 18, count 2 2006.173.04:04:48.61#ibcon#*mode == 0, iclass 18, count 2 2006.173.04:04:48.61#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.04:04:48.61#ibcon#[25=AT07-04\r\n] 2006.173.04:04:48.61#ibcon#*before write, iclass 18, count 2 2006.173.04:04:48.61#ibcon#enter sib2, iclass 18, count 2 2006.173.04:04:48.61#ibcon#flushed, iclass 18, count 2 2006.173.04:04:48.61#ibcon#about to write, iclass 18, count 2 2006.173.04:04:48.61#ibcon#wrote, iclass 18, count 2 2006.173.04:04:48.61#ibcon#about to read 3, iclass 18, count 2 2006.173.04:04:48.64#ibcon#read 3, iclass 18, count 2 2006.173.04:04:48.64#ibcon#about to read 4, iclass 18, count 2 2006.173.04:04:48.64#ibcon#read 4, iclass 18, count 2 2006.173.04:04:48.64#ibcon#about to read 5, iclass 18, count 2 2006.173.04:04:48.64#ibcon#read 5, iclass 18, count 2 2006.173.04:04:48.64#ibcon#about to read 6, iclass 18, count 2 2006.173.04:04:48.64#ibcon#read 6, iclass 18, count 2 2006.173.04:04:48.64#ibcon#end of sib2, iclass 18, count 2 2006.173.04:04:48.64#ibcon#*after write, iclass 18, count 2 2006.173.04:04:48.64#ibcon#*before return 0, iclass 18, count 2 2006.173.04:04:48.64#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.04:04:48.64#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.04:04:48.64#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.04:04:48.64#ibcon#ireg 7 cls_cnt 0 2006.173.04:04:48.64#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.04:04:48.76#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.04:04:48.76#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.04:04:48.76#ibcon#enter wrdev, iclass 18, count 0 2006.173.04:04:48.76#ibcon#first serial, iclass 18, count 0 2006.173.04:04:48.76#ibcon#enter sib2, iclass 18, count 0 2006.173.04:04:48.76#ibcon#flushed, iclass 18, count 0 2006.173.04:04:48.76#ibcon#about to write, iclass 18, count 0 2006.173.04:04:48.76#ibcon#wrote, iclass 18, count 0 2006.173.04:04:48.76#ibcon#about to read 3, iclass 18, count 0 2006.173.04:04:48.78#ibcon#read 3, iclass 18, count 0 2006.173.04:04:48.78#ibcon#about to read 4, iclass 18, count 0 2006.173.04:04:48.78#ibcon#read 4, iclass 18, count 0 2006.173.04:04:48.78#ibcon#about to read 5, iclass 18, count 0 2006.173.04:04:48.78#ibcon#read 5, iclass 18, count 0 2006.173.04:04:48.78#ibcon#about to read 6, iclass 18, count 0 2006.173.04:04:48.78#ibcon#read 6, iclass 18, count 0 2006.173.04:04:48.78#ibcon#end of sib2, iclass 18, count 0 2006.173.04:04:48.78#ibcon#*mode == 0, iclass 18, count 0 2006.173.04:04:48.78#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.04:04:48.78#ibcon#[25=USB\r\n] 2006.173.04:04:48.78#ibcon#*before write, iclass 18, count 0 2006.173.04:04:48.78#ibcon#enter sib2, iclass 18, count 0 2006.173.04:04:48.78#ibcon#flushed, iclass 18, count 0 2006.173.04:04:48.78#ibcon#about to write, iclass 18, count 0 2006.173.04:04:48.78#ibcon#wrote, iclass 18, count 0 2006.173.04:04:48.78#ibcon#about to read 3, iclass 18, count 0 2006.173.04:04:48.81#ibcon#read 3, iclass 18, count 0 2006.173.04:04:48.81#ibcon#about to read 4, iclass 18, count 0 2006.173.04:04:48.81#ibcon#read 4, iclass 18, count 0 2006.173.04:04:48.81#ibcon#about to read 5, iclass 18, count 0 2006.173.04:04:48.81#ibcon#read 5, iclass 18, count 0 2006.173.04:04:48.81#ibcon#about to read 6, iclass 18, count 0 2006.173.04:04:48.81#ibcon#read 6, iclass 18, count 0 2006.173.04:04:48.81#ibcon#end of sib2, iclass 18, count 0 2006.173.04:04:48.81#ibcon#*after write, iclass 18, count 0 2006.173.04:04:48.81#ibcon#*before return 0, iclass 18, count 0 2006.173.04:04:48.81#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.04:04:48.81#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.04:04:48.81#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.04:04:48.81#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.04:04:48.81$vck44/valo=8,884.99 2006.173.04:04:48.81#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.04:04:48.81#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.04:04:48.81#ibcon#ireg 17 cls_cnt 0 2006.173.04:04:48.81#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.04:04:48.81#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.04:04:48.81#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.04:04:48.81#ibcon#enter wrdev, iclass 20, count 0 2006.173.04:04:48.81#ibcon#first serial, iclass 20, count 0 2006.173.04:04:48.81#ibcon#enter sib2, iclass 20, count 0 2006.173.04:04:48.81#ibcon#flushed, iclass 20, count 0 2006.173.04:04:48.81#ibcon#about to write, iclass 20, count 0 2006.173.04:04:48.81#ibcon#wrote, iclass 20, count 0 2006.173.04:04:48.81#ibcon#about to read 3, iclass 20, count 0 2006.173.04:04:48.83#ibcon#read 3, iclass 20, count 0 2006.173.04:04:48.83#ibcon#about to read 4, iclass 20, count 0 2006.173.04:04:48.83#ibcon#read 4, iclass 20, count 0 2006.173.04:04:48.83#ibcon#about to read 5, iclass 20, count 0 2006.173.04:04:48.83#ibcon#read 5, iclass 20, count 0 2006.173.04:04:48.83#ibcon#about to read 6, iclass 20, count 0 2006.173.04:04:48.83#ibcon#read 6, iclass 20, count 0 2006.173.04:04:48.83#ibcon#end of sib2, iclass 20, count 0 2006.173.04:04:48.83#ibcon#*mode == 0, iclass 20, count 0 2006.173.04:04:48.83#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.04:04:48.83#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.04:04:48.83#ibcon#*before write, iclass 20, count 0 2006.173.04:04:48.83#ibcon#enter sib2, iclass 20, count 0 2006.173.04:04:48.83#ibcon#flushed, iclass 20, count 0 2006.173.04:04:48.83#ibcon#about to write, iclass 20, count 0 2006.173.04:04:48.83#ibcon#wrote, iclass 20, count 0 2006.173.04:04:48.83#ibcon#about to read 3, iclass 20, count 0 2006.173.04:04:48.87#ibcon#read 3, iclass 20, count 0 2006.173.04:04:48.87#ibcon#about to read 4, iclass 20, count 0 2006.173.04:04:48.87#ibcon#read 4, iclass 20, count 0 2006.173.04:04:48.87#ibcon#about to read 5, iclass 20, count 0 2006.173.04:04:48.87#ibcon#read 5, iclass 20, count 0 2006.173.04:04:48.87#ibcon#about to read 6, iclass 20, count 0 2006.173.04:04:48.87#ibcon#read 6, iclass 20, count 0 2006.173.04:04:48.87#ibcon#end of sib2, iclass 20, count 0 2006.173.04:04:48.87#ibcon#*after write, iclass 20, count 0 2006.173.04:04:48.87#ibcon#*before return 0, iclass 20, count 0 2006.173.04:04:48.87#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.04:04:48.87#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.04:04:48.87#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.04:04:48.87#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.04:04:48.87$vck44/va=8,4 2006.173.04:04:48.87#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.04:04:48.87#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.04:04:48.87#ibcon#ireg 11 cls_cnt 2 2006.173.04:04:48.87#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.04:04:48.93#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.04:04:48.93#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.04:04:48.93#ibcon#enter wrdev, iclass 22, count 2 2006.173.04:04:48.93#ibcon#first serial, iclass 22, count 2 2006.173.04:04:48.93#ibcon#enter sib2, iclass 22, count 2 2006.173.04:04:48.93#ibcon#flushed, iclass 22, count 2 2006.173.04:04:48.93#ibcon#about to write, iclass 22, count 2 2006.173.04:04:48.93#ibcon#wrote, iclass 22, count 2 2006.173.04:04:48.93#ibcon#about to read 3, iclass 22, count 2 2006.173.04:04:48.95#ibcon#read 3, iclass 22, count 2 2006.173.04:04:48.95#ibcon#about to read 4, iclass 22, count 2 2006.173.04:04:48.95#ibcon#read 4, iclass 22, count 2 2006.173.04:04:48.95#ibcon#about to read 5, iclass 22, count 2 2006.173.04:04:48.95#ibcon#read 5, iclass 22, count 2 2006.173.04:04:48.95#ibcon#about to read 6, iclass 22, count 2 2006.173.04:04:48.95#ibcon#read 6, iclass 22, count 2 2006.173.04:04:48.95#ibcon#end of sib2, iclass 22, count 2 2006.173.04:04:48.95#ibcon#*mode == 0, iclass 22, count 2 2006.173.04:04:48.95#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.04:04:48.95#ibcon#[25=AT08-04\r\n] 2006.173.04:04:48.95#ibcon#*before write, iclass 22, count 2 2006.173.04:04:48.95#ibcon#enter sib2, iclass 22, count 2 2006.173.04:04:48.95#ibcon#flushed, iclass 22, count 2 2006.173.04:04:48.95#ibcon#about to write, iclass 22, count 2 2006.173.04:04:48.95#ibcon#wrote, iclass 22, count 2 2006.173.04:04:48.95#ibcon#about to read 3, iclass 22, count 2 2006.173.04:04:48.98#ibcon#read 3, iclass 22, count 2 2006.173.04:04:48.98#ibcon#about to read 4, iclass 22, count 2 2006.173.04:04:48.98#ibcon#read 4, iclass 22, count 2 2006.173.04:04:48.98#ibcon#about to read 5, iclass 22, count 2 2006.173.04:04:48.98#ibcon#read 5, iclass 22, count 2 2006.173.04:04:48.98#ibcon#about to read 6, iclass 22, count 2 2006.173.04:04:48.98#ibcon#read 6, iclass 22, count 2 2006.173.04:04:48.98#ibcon#end of sib2, iclass 22, count 2 2006.173.04:04:48.98#ibcon#*after write, iclass 22, count 2 2006.173.04:04:48.98#ibcon#*before return 0, iclass 22, count 2 2006.173.04:04:48.98#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.04:04:48.98#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.04:04:48.98#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.04:04:48.98#ibcon#ireg 7 cls_cnt 0 2006.173.04:04:48.98#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.04:04:49.10#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.04:04:49.10#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.04:04:49.10#ibcon#enter wrdev, iclass 22, count 0 2006.173.04:04:49.10#ibcon#first serial, iclass 22, count 0 2006.173.04:04:49.10#ibcon#enter sib2, iclass 22, count 0 2006.173.04:04:49.10#ibcon#flushed, iclass 22, count 0 2006.173.04:04:49.10#ibcon#about to write, iclass 22, count 0 2006.173.04:04:49.10#ibcon#wrote, iclass 22, count 0 2006.173.04:04:49.10#ibcon#about to read 3, iclass 22, count 0 2006.173.04:04:49.12#ibcon#read 3, iclass 22, count 0 2006.173.04:04:49.12#ibcon#about to read 4, iclass 22, count 0 2006.173.04:04:49.12#ibcon#read 4, iclass 22, count 0 2006.173.04:04:49.12#ibcon#about to read 5, iclass 22, count 0 2006.173.04:04:49.12#ibcon#read 5, iclass 22, count 0 2006.173.04:04:49.12#ibcon#about to read 6, iclass 22, count 0 2006.173.04:04:49.12#ibcon#read 6, iclass 22, count 0 2006.173.04:04:49.12#ibcon#end of sib2, iclass 22, count 0 2006.173.04:04:49.12#ibcon#*mode == 0, iclass 22, count 0 2006.173.04:04:49.12#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.04:04:49.12#ibcon#[25=USB\r\n] 2006.173.04:04:49.12#ibcon#*before write, iclass 22, count 0 2006.173.04:04:49.12#ibcon#enter sib2, iclass 22, count 0 2006.173.04:04:49.12#ibcon#flushed, iclass 22, count 0 2006.173.04:04:49.12#ibcon#about to write, iclass 22, count 0 2006.173.04:04:49.12#ibcon#wrote, iclass 22, count 0 2006.173.04:04:49.12#ibcon#about to read 3, iclass 22, count 0 2006.173.04:04:49.15#ibcon#read 3, iclass 22, count 0 2006.173.04:04:49.15#ibcon#about to read 4, iclass 22, count 0 2006.173.04:04:49.15#ibcon#read 4, iclass 22, count 0 2006.173.04:04:49.15#ibcon#about to read 5, iclass 22, count 0 2006.173.04:04:49.15#ibcon#read 5, iclass 22, count 0 2006.173.04:04:49.15#ibcon#about to read 6, iclass 22, count 0 2006.173.04:04:49.15#ibcon#read 6, iclass 22, count 0 2006.173.04:04:49.15#ibcon#end of sib2, iclass 22, count 0 2006.173.04:04:49.15#ibcon#*after write, iclass 22, count 0 2006.173.04:04:49.15#ibcon#*before return 0, iclass 22, count 0 2006.173.04:04:49.15#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.04:04:49.15#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.04:04:49.15#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.04:04:49.15#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.04:04:49.15$vck44/vblo=1,629.99 2006.173.04:04:49.15#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.04:04:49.15#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.04:04:49.15#ibcon#ireg 17 cls_cnt 0 2006.173.04:04:49.15#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.04:04:49.15#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.04:04:49.15#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.04:04:49.15#ibcon#enter wrdev, iclass 24, count 0 2006.173.04:04:49.15#ibcon#first serial, iclass 24, count 0 2006.173.04:04:49.15#ibcon#enter sib2, iclass 24, count 0 2006.173.04:04:49.15#ibcon#flushed, iclass 24, count 0 2006.173.04:04:49.15#ibcon#about to write, iclass 24, count 0 2006.173.04:04:49.15#ibcon#wrote, iclass 24, count 0 2006.173.04:04:49.15#ibcon#about to read 3, iclass 24, count 0 2006.173.04:04:49.17#ibcon#read 3, iclass 24, count 0 2006.173.04:04:49.17#ibcon#about to read 4, iclass 24, count 0 2006.173.04:04:49.17#ibcon#read 4, iclass 24, count 0 2006.173.04:04:49.17#ibcon#about to read 5, iclass 24, count 0 2006.173.04:04:49.17#ibcon#read 5, iclass 24, count 0 2006.173.04:04:49.17#ibcon#about to read 6, iclass 24, count 0 2006.173.04:04:49.17#ibcon#read 6, iclass 24, count 0 2006.173.04:04:49.17#ibcon#end of sib2, iclass 24, count 0 2006.173.04:04:49.17#ibcon#*mode == 0, iclass 24, count 0 2006.173.04:04:49.17#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.04:04:49.17#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.04:04:49.17#ibcon#*before write, iclass 24, count 0 2006.173.04:04:49.17#ibcon#enter sib2, iclass 24, count 0 2006.173.04:04:49.17#ibcon#flushed, iclass 24, count 0 2006.173.04:04:49.17#ibcon#about to write, iclass 24, count 0 2006.173.04:04:49.17#ibcon#wrote, iclass 24, count 0 2006.173.04:04:49.17#ibcon#about to read 3, iclass 24, count 0 2006.173.04:04:49.21#ibcon#read 3, iclass 24, count 0 2006.173.04:04:49.21#ibcon#about to read 4, iclass 24, count 0 2006.173.04:04:49.21#ibcon#read 4, iclass 24, count 0 2006.173.04:04:49.21#ibcon#about to read 5, iclass 24, count 0 2006.173.04:04:49.21#ibcon#read 5, iclass 24, count 0 2006.173.04:04:49.21#ibcon#about to read 6, iclass 24, count 0 2006.173.04:04:49.21#ibcon#read 6, iclass 24, count 0 2006.173.04:04:49.21#ibcon#end of sib2, iclass 24, count 0 2006.173.04:04:49.21#ibcon#*after write, iclass 24, count 0 2006.173.04:04:49.21#ibcon#*before return 0, iclass 24, count 0 2006.173.04:04:49.21#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.04:04:49.21#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.04:04:49.21#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.04:04:49.21#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.04:04:49.21$vck44/vb=1,4 2006.173.04:04:49.21#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.04:04:49.21#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.04:04:49.21#ibcon#ireg 11 cls_cnt 2 2006.173.04:04:49.21#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.04:04:49.21#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.04:04:49.21#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.04:04:49.21#ibcon#enter wrdev, iclass 26, count 2 2006.173.04:04:49.21#ibcon#first serial, iclass 26, count 2 2006.173.04:04:49.21#ibcon#enter sib2, iclass 26, count 2 2006.173.04:04:49.21#ibcon#flushed, iclass 26, count 2 2006.173.04:04:49.21#ibcon#about to write, iclass 26, count 2 2006.173.04:04:49.21#ibcon#wrote, iclass 26, count 2 2006.173.04:04:49.21#ibcon#about to read 3, iclass 26, count 2 2006.173.04:04:49.23#ibcon#read 3, iclass 26, count 2 2006.173.04:04:49.23#ibcon#about to read 4, iclass 26, count 2 2006.173.04:04:49.23#ibcon#read 4, iclass 26, count 2 2006.173.04:04:49.23#ibcon#about to read 5, iclass 26, count 2 2006.173.04:04:49.23#ibcon#read 5, iclass 26, count 2 2006.173.04:04:49.23#ibcon#about to read 6, iclass 26, count 2 2006.173.04:04:49.23#ibcon#read 6, iclass 26, count 2 2006.173.04:04:49.23#ibcon#end of sib2, iclass 26, count 2 2006.173.04:04:49.23#ibcon#*mode == 0, iclass 26, count 2 2006.173.04:04:49.23#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.04:04:49.23#ibcon#[27=AT01-04\r\n] 2006.173.04:04:49.23#ibcon#*before write, iclass 26, count 2 2006.173.04:04:49.23#ibcon#enter sib2, iclass 26, count 2 2006.173.04:04:49.23#ibcon#flushed, iclass 26, count 2 2006.173.04:04:49.23#ibcon#about to write, iclass 26, count 2 2006.173.04:04:49.23#ibcon#wrote, iclass 26, count 2 2006.173.04:04:49.23#ibcon#about to read 3, iclass 26, count 2 2006.173.04:04:49.26#ibcon#read 3, iclass 26, count 2 2006.173.04:04:49.26#ibcon#about to read 4, iclass 26, count 2 2006.173.04:04:49.26#ibcon#read 4, iclass 26, count 2 2006.173.04:04:49.26#ibcon#about to read 5, iclass 26, count 2 2006.173.04:04:49.26#ibcon#read 5, iclass 26, count 2 2006.173.04:04:49.26#ibcon#about to read 6, iclass 26, count 2 2006.173.04:04:49.26#ibcon#read 6, iclass 26, count 2 2006.173.04:04:49.26#ibcon#end of sib2, iclass 26, count 2 2006.173.04:04:49.26#ibcon#*after write, iclass 26, count 2 2006.173.04:04:49.26#ibcon#*before return 0, iclass 26, count 2 2006.173.04:04:49.26#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.04:04:49.26#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.04:04:49.26#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.04:04:49.26#ibcon#ireg 7 cls_cnt 0 2006.173.04:04:49.26#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.04:04:49.38#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.04:04:49.38#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.04:04:49.38#ibcon#enter wrdev, iclass 26, count 0 2006.173.04:04:49.38#ibcon#first serial, iclass 26, count 0 2006.173.04:04:49.38#ibcon#enter sib2, iclass 26, count 0 2006.173.04:04:49.38#ibcon#flushed, iclass 26, count 0 2006.173.04:04:49.38#ibcon#about to write, iclass 26, count 0 2006.173.04:04:49.38#ibcon#wrote, iclass 26, count 0 2006.173.04:04:49.38#ibcon#about to read 3, iclass 26, count 0 2006.173.04:04:49.40#ibcon#read 3, iclass 26, count 0 2006.173.04:04:49.40#ibcon#about to read 4, iclass 26, count 0 2006.173.04:04:49.40#ibcon#read 4, iclass 26, count 0 2006.173.04:04:49.40#ibcon#about to read 5, iclass 26, count 0 2006.173.04:04:49.40#ibcon#read 5, iclass 26, count 0 2006.173.04:04:49.40#ibcon#about to read 6, iclass 26, count 0 2006.173.04:04:49.40#ibcon#read 6, iclass 26, count 0 2006.173.04:04:49.40#ibcon#end of sib2, iclass 26, count 0 2006.173.04:04:49.40#ibcon#*mode == 0, iclass 26, count 0 2006.173.04:04:49.40#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.04:04:49.40#ibcon#[27=USB\r\n] 2006.173.04:04:49.40#ibcon#*before write, iclass 26, count 0 2006.173.04:04:49.40#ibcon#enter sib2, iclass 26, count 0 2006.173.04:04:49.40#ibcon#flushed, iclass 26, count 0 2006.173.04:04:49.40#ibcon#about to write, iclass 26, count 0 2006.173.04:04:49.40#ibcon#wrote, iclass 26, count 0 2006.173.04:04:49.40#ibcon#about to read 3, iclass 26, count 0 2006.173.04:04:49.43#ibcon#read 3, iclass 26, count 0 2006.173.04:04:49.43#ibcon#about to read 4, iclass 26, count 0 2006.173.04:04:49.43#ibcon#read 4, iclass 26, count 0 2006.173.04:04:49.43#ibcon#about to read 5, iclass 26, count 0 2006.173.04:04:49.43#ibcon#read 5, iclass 26, count 0 2006.173.04:04:49.43#ibcon#about to read 6, iclass 26, count 0 2006.173.04:04:49.43#ibcon#read 6, iclass 26, count 0 2006.173.04:04:49.43#ibcon#end of sib2, iclass 26, count 0 2006.173.04:04:49.43#ibcon#*after write, iclass 26, count 0 2006.173.04:04:49.43#ibcon#*before return 0, iclass 26, count 0 2006.173.04:04:49.43#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.04:04:49.43#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.04:04:49.43#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.04:04:49.43#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.04:04:49.43$vck44/vblo=2,634.99 2006.173.04:04:49.43#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.04:04:49.43#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.04:04:49.43#ibcon#ireg 17 cls_cnt 0 2006.173.04:04:49.43#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.04:04:49.43#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.04:04:49.43#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.04:04:49.43#ibcon#enter wrdev, iclass 28, count 0 2006.173.04:04:49.43#ibcon#first serial, iclass 28, count 0 2006.173.04:04:49.43#ibcon#enter sib2, iclass 28, count 0 2006.173.04:04:49.43#ibcon#flushed, iclass 28, count 0 2006.173.04:04:49.43#ibcon#about to write, iclass 28, count 0 2006.173.04:04:49.43#ibcon#wrote, iclass 28, count 0 2006.173.04:04:49.43#ibcon#about to read 3, iclass 28, count 0 2006.173.04:04:49.45#ibcon#read 3, iclass 28, count 0 2006.173.04:04:49.45#ibcon#about to read 4, iclass 28, count 0 2006.173.04:04:49.45#ibcon#read 4, iclass 28, count 0 2006.173.04:04:49.45#ibcon#about to read 5, iclass 28, count 0 2006.173.04:04:49.45#ibcon#read 5, iclass 28, count 0 2006.173.04:04:49.45#ibcon#about to read 6, iclass 28, count 0 2006.173.04:04:49.45#ibcon#read 6, iclass 28, count 0 2006.173.04:04:49.45#ibcon#end of sib2, iclass 28, count 0 2006.173.04:04:49.45#ibcon#*mode == 0, iclass 28, count 0 2006.173.04:04:49.45#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.04:04:49.45#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.04:04:49.45#ibcon#*before write, iclass 28, count 0 2006.173.04:04:49.45#ibcon#enter sib2, iclass 28, count 0 2006.173.04:04:49.45#ibcon#flushed, iclass 28, count 0 2006.173.04:04:49.45#ibcon#about to write, iclass 28, count 0 2006.173.04:04:49.45#ibcon#wrote, iclass 28, count 0 2006.173.04:04:49.45#ibcon#about to read 3, iclass 28, count 0 2006.173.04:04:49.49#ibcon#read 3, iclass 28, count 0 2006.173.04:04:49.49#ibcon#about to read 4, iclass 28, count 0 2006.173.04:04:49.49#ibcon#read 4, iclass 28, count 0 2006.173.04:04:49.49#ibcon#about to read 5, iclass 28, count 0 2006.173.04:04:49.49#ibcon#read 5, iclass 28, count 0 2006.173.04:04:49.49#ibcon#about to read 6, iclass 28, count 0 2006.173.04:04:49.49#ibcon#read 6, iclass 28, count 0 2006.173.04:04:49.49#ibcon#end of sib2, iclass 28, count 0 2006.173.04:04:49.49#ibcon#*after write, iclass 28, count 0 2006.173.04:04:49.49#ibcon#*before return 0, iclass 28, count 0 2006.173.04:04:49.49#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.04:04:49.49#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.04:04:49.49#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.04:04:49.49#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.04:04:49.49$vck44/vb=2,4 2006.173.04:04:49.49#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.04:04:49.49#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.04:04:49.49#ibcon#ireg 11 cls_cnt 2 2006.173.04:04:49.49#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.04:04:49.55#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.04:04:49.55#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.04:04:49.55#ibcon#enter wrdev, iclass 30, count 2 2006.173.04:04:49.55#ibcon#first serial, iclass 30, count 2 2006.173.04:04:49.55#ibcon#enter sib2, iclass 30, count 2 2006.173.04:04:49.55#ibcon#flushed, iclass 30, count 2 2006.173.04:04:49.55#ibcon#about to write, iclass 30, count 2 2006.173.04:04:49.55#ibcon#wrote, iclass 30, count 2 2006.173.04:04:49.55#ibcon#about to read 3, iclass 30, count 2 2006.173.04:04:49.57#ibcon#read 3, iclass 30, count 2 2006.173.04:04:49.57#ibcon#about to read 4, iclass 30, count 2 2006.173.04:04:49.57#ibcon#read 4, iclass 30, count 2 2006.173.04:04:49.57#ibcon#about to read 5, iclass 30, count 2 2006.173.04:04:49.57#ibcon#read 5, iclass 30, count 2 2006.173.04:04:49.57#ibcon#about to read 6, iclass 30, count 2 2006.173.04:04:49.57#ibcon#read 6, iclass 30, count 2 2006.173.04:04:49.57#ibcon#end of sib2, iclass 30, count 2 2006.173.04:04:49.57#ibcon#*mode == 0, iclass 30, count 2 2006.173.04:04:49.57#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.04:04:49.57#ibcon#[27=AT02-04\r\n] 2006.173.04:04:49.57#ibcon#*before write, iclass 30, count 2 2006.173.04:04:49.57#ibcon#enter sib2, iclass 30, count 2 2006.173.04:04:49.57#ibcon#flushed, iclass 30, count 2 2006.173.04:04:49.57#ibcon#about to write, iclass 30, count 2 2006.173.04:04:49.57#ibcon#wrote, iclass 30, count 2 2006.173.04:04:49.57#ibcon#about to read 3, iclass 30, count 2 2006.173.04:04:49.60#ibcon#read 3, iclass 30, count 2 2006.173.04:04:49.60#ibcon#about to read 4, iclass 30, count 2 2006.173.04:04:49.60#ibcon#read 4, iclass 30, count 2 2006.173.04:04:49.60#ibcon#about to read 5, iclass 30, count 2 2006.173.04:04:49.60#ibcon#read 5, iclass 30, count 2 2006.173.04:04:49.60#ibcon#about to read 6, iclass 30, count 2 2006.173.04:04:49.60#ibcon#read 6, iclass 30, count 2 2006.173.04:04:49.60#ibcon#end of sib2, iclass 30, count 2 2006.173.04:04:49.60#ibcon#*after write, iclass 30, count 2 2006.173.04:04:49.60#ibcon#*before return 0, iclass 30, count 2 2006.173.04:04:49.60#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.04:04:49.60#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.04:04:49.60#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.04:04:49.60#ibcon#ireg 7 cls_cnt 0 2006.173.04:04:49.60#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.04:04:49.72#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.04:04:49.72#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.04:04:49.72#ibcon#enter wrdev, iclass 30, count 0 2006.173.04:04:49.72#ibcon#first serial, iclass 30, count 0 2006.173.04:04:49.72#ibcon#enter sib2, iclass 30, count 0 2006.173.04:04:49.72#ibcon#flushed, iclass 30, count 0 2006.173.04:04:49.72#ibcon#about to write, iclass 30, count 0 2006.173.04:04:49.72#ibcon#wrote, iclass 30, count 0 2006.173.04:04:49.72#ibcon#about to read 3, iclass 30, count 0 2006.173.04:04:49.74#ibcon#read 3, iclass 30, count 0 2006.173.04:04:49.74#ibcon#about to read 4, iclass 30, count 0 2006.173.04:04:49.74#ibcon#read 4, iclass 30, count 0 2006.173.04:04:49.74#ibcon#about to read 5, iclass 30, count 0 2006.173.04:04:49.74#ibcon#read 5, iclass 30, count 0 2006.173.04:04:49.74#ibcon#about to read 6, iclass 30, count 0 2006.173.04:04:49.74#ibcon#read 6, iclass 30, count 0 2006.173.04:04:49.74#ibcon#end of sib2, iclass 30, count 0 2006.173.04:04:49.74#ibcon#*mode == 0, iclass 30, count 0 2006.173.04:04:49.74#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.04:04:49.74#ibcon#[27=USB\r\n] 2006.173.04:04:49.74#ibcon#*before write, iclass 30, count 0 2006.173.04:04:49.74#ibcon#enter sib2, iclass 30, count 0 2006.173.04:04:49.74#ibcon#flushed, iclass 30, count 0 2006.173.04:04:49.74#ibcon#about to write, iclass 30, count 0 2006.173.04:04:49.74#ibcon#wrote, iclass 30, count 0 2006.173.04:04:49.74#ibcon#about to read 3, iclass 30, count 0 2006.173.04:04:49.77#ibcon#read 3, iclass 30, count 0 2006.173.04:04:49.77#ibcon#about to read 4, iclass 30, count 0 2006.173.04:04:49.77#ibcon#read 4, iclass 30, count 0 2006.173.04:04:49.77#ibcon#about to read 5, iclass 30, count 0 2006.173.04:04:49.77#ibcon#read 5, iclass 30, count 0 2006.173.04:04:49.77#ibcon#about to read 6, iclass 30, count 0 2006.173.04:04:49.77#ibcon#read 6, iclass 30, count 0 2006.173.04:04:49.77#ibcon#end of sib2, iclass 30, count 0 2006.173.04:04:49.77#ibcon#*after write, iclass 30, count 0 2006.173.04:04:49.77#ibcon#*before return 0, iclass 30, count 0 2006.173.04:04:49.77#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.04:04:49.77#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.04:04:49.77#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.04:04:49.77#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.04:04:49.77$vck44/vblo=3,649.99 2006.173.04:04:49.77#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.04:04:49.77#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.04:04:49.77#ibcon#ireg 17 cls_cnt 0 2006.173.04:04:49.77#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.04:04:49.77#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.04:04:49.77#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.04:04:49.77#ibcon#enter wrdev, iclass 32, count 0 2006.173.04:04:49.77#ibcon#first serial, iclass 32, count 0 2006.173.04:04:49.77#ibcon#enter sib2, iclass 32, count 0 2006.173.04:04:49.77#ibcon#flushed, iclass 32, count 0 2006.173.04:04:49.77#ibcon#about to write, iclass 32, count 0 2006.173.04:04:49.77#ibcon#wrote, iclass 32, count 0 2006.173.04:04:49.77#ibcon#about to read 3, iclass 32, count 0 2006.173.04:04:49.79#ibcon#read 3, iclass 32, count 0 2006.173.04:04:49.79#ibcon#about to read 4, iclass 32, count 0 2006.173.04:04:49.79#ibcon#read 4, iclass 32, count 0 2006.173.04:04:49.79#ibcon#about to read 5, iclass 32, count 0 2006.173.04:04:49.79#ibcon#read 5, iclass 32, count 0 2006.173.04:04:49.79#ibcon#about to read 6, iclass 32, count 0 2006.173.04:04:49.79#ibcon#read 6, iclass 32, count 0 2006.173.04:04:49.79#ibcon#end of sib2, iclass 32, count 0 2006.173.04:04:49.79#ibcon#*mode == 0, iclass 32, count 0 2006.173.04:04:49.79#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.04:04:49.79#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.04:04:49.79#ibcon#*before write, iclass 32, count 0 2006.173.04:04:49.79#ibcon#enter sib2, iclass 32, count 0 2006.173.04:04:49.79#ibcon#flushed, iclass 32, count 0 2006.173.04:04:49.79#ibcon#about to write, iclass 32, count 0 2006.173.04:04:49.79#ibcon#wrote, iclass 32, count 0 2006.173.04:04:49.79#ibcon#about to read 3, iclass 32, count 0 2006.173.04:04:49.83#ibcon#read 3, iclass 32, count 0 2006.173.04:04:49.83#ibcon#about to read 4, iclass 32, count 0 2006.173.04:04:49.83#ibcon#read 4, iclass 32, count 0 2006.173.04:04:49.83#ibcon#about to read 5, iclass 32, count 0 2006.173.04:04:49.83#ibcon#read 5, iclass 32, count 0 2006.173.04:04:49.83#ibcon#about to read 6, iclass 32, count 0 2006.173.04:04:49.83#ibcon#read 6, iclass 32, count 0 2006.173.04:04:49.83#ibcon#end of sib2, iclass 32, count 0 2006.173.04:04:49.83#ibcon#*after write, iclass 32, count 0 2006.173.04:04:49.83#ibcon#*before return 0, iclass 32, count 0 2006.173.04:04:49.83#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.04:04:49.83#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.04:04:49.83#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.04:04:49.83#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.04:04:49.83$vck44/vb=3,4 2006.173.04:04:49.83#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.04:04:49.83#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.04:04:49.83#ibcon#ireg 11 cls_cnt 2 2006.173.04:04:49.83#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.04:04:49.89#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.04:04:49.89#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.04:04:49.89#ibcon#enter wrdev, iclass 34, count 2 2006.173.04:04:49.89#ibcon#first serial, iclass 34, count 2 2006.173.04:04:49.89#ibcon#enter sib2, iclass 34, count 2 2006.173.04:04:49.89#ibcon#flushed, iclass 34, count 2 2006.173.04:04:49.89#ibcon#about to write, iclass 34, count 2 2006.173.04:04:49.89#ibcon#wrote, iclass 34, count 2 2006.173.04:04:49.89#ibcon#about to read 3, iclass 34, count 2 2006.173.04:04:49.91#ibcon#read 3, iclass 34, count 2 2006.173.04:04:49.91#ibcon#about to read 4, iclass 34, count 2 2006.173.04:04:49.91#ibcon#read 4, iclass 34, count 2 2006.173.04:04:49.91#ibcon#about to read 5, iclass 34, count 2 2006.173.04:04:49.91#ibcon#read 5, iclass 34, count 2 2006.173.04:04:49.91#ibcon#about to read 6, iclass 34, count 2 2006.173.04:04:49.91#ibcon#read 6, iclass 34, count 2 2006.173.04:04:49.91#ibcon#end of sib2, iclass 34, count 2 2006.173.04:04:49.91#ibcon#*mode == 0, iclass 34, count 2 2006.173.04:04:49.91#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.04:04:49.91#ibcon#[27=AT03-04\r\n] 2006.173.04:04:49.91#ibcon#*before write, iclass 34, count 2 2006.173.04:04:49.91#ibcon#enter sib2, iclass 34, count 2 2006.173.04:04:49.91#ibcon#flushed, iclass 34, count 2 2006.173.04:04:49.91#ibcon#about to write, iclass 34, count 2 2006.173.04:04:49.91#ibcon#wrote, iclass 34, count 2 2006.173.04:04:49.91#ibcon#about to read 3, iclass 34, count 2 2006.173.04:04:49.94#ibcon#read 3, iclass 34, count 2 2006.173.04:04:49.94#ibcon#about to read 4, iclass 34, count 2 2006.173.04:04:49.94#ibcon#read 4, iclass 34, count 2 2006.173.04:04:49.94#ibcon#about to read 5, iclass 34, count 2 2006.173.04:04:49.94#ibcon#read 5, iclass 34, count 2 2006.173.04:04:49.94#ibcon#about to read 6, iclass 34, count 2 2006.173.04:04:49.94#ibcon#read 6, iclass 34, count 2 2006.173.04:04:49.94#ibcon#end of sib2, iclass 34, count 2 2006.173.04:04:49.94#ibcon#*after write, iclass 34, count 2 2006.173.04:04:49.94#ibcon#*before return 0, iclass 34, count 2 2006.173.04:04:49.94#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.04:04:49.94#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.04:04:49.94#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.04:04:49.94#ibcon#ireg 7 cls_cnt 0 2006.173.04:04:49.94#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.04:04:50.06#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.04:04:50.06#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.04:04:50.06#ibcon#enter wrdev, iclass 34, count 0 2006.173.04:04:50.06#ibcon#first serial, iclass 34, count 0 2006.173.04:04:50.06#ibcon#enter sib2, iclass 34, count 0 2006.173.04:04:50.06#ibcon#flushed, iclass 34, count 0 2006.173.04:04:50.06#ibcon#about to write, iclass 34, count 0 2006.173.04:04:50.06#ibcon#wrote, iclass 34, count 0 2006.173.04:04:50.06#ibcon#about to read 3, iclass 34, count 0 2006.173.04:04:50.08#ibcon#read 3, iclass 34, count 0 2006.173.04:04:50.08#ibcon#about to read 4, iclass 34, count 0 2006.173.04:04:50.08#ibcon#read 4, iclass 34, count 0 2006.173.04:04:50.08#ibcon#about to read 5, iclass 34, count 0 2006.173.04:04:50.08#ibcon#read 5, iclass 34, count 0 2006.173.04:04:50.08#ibcon#about to read 6, iclass 34, count 0 2006.173.04:04:50.08#ibcon#read 6, iclass 34, count 0 2006.173.04:04:50.08#ibcon#end of sib2, iclass 34, count 0 2006.173.04:04:50.08#ibcon#*mode == 0, iclass 34, count 0 2006.173.04:04:50.08#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.04:04:50.08#ibcon#[27=USB\r\n] 2006.173.04:04:50.08#ibcon#*before write, iclass 34, count 0 2006.173.04:04:50.08#ibcon#enter sib2, iclass 34, count 0 2006.173.04:04:50.08#ibcon#flushed, iclass 34, count 0 2006.173.04:04:50.08#ibcon#about to write, iclass 34, count 0 2006.173.04:04:50.08#ibcon#wrote, iclass 34, count 0 2006.173.04:04:50.08#ibcon#about to read 3, iclass 34, count 0 2006.173.04:04:50.11#ibcon#read 3, iclass 34, count 0 2006.173.04:04:50.11#ibcon#about to read 4, iclass 34, count 0 2006.173.04:04:50.11#ibcon#read 4, iclass 34, count 0 2006.173.04:04:50.11#ibcon#about to read 5, iclass 34, count 0 2006.173.04:04:50.11#ibcon#read 5, iclass 34, count 0 2006.173.04:04:50.11#ibcon#about to read 6, iclass 34, count 0 2006.173.04:04:50.11#ibcon#read 6, iclass 34, count 0 2006.173.04:04:50.11#ibcon#end of sib2, iclass 34, count 0 2006.173.04:04:50.11#ibcon#*after write, iclass 34, count 0 2006.173.04:04:50.11#ibcon#*before return 0, iclass 34, count 0 2006.173.04:04:50.11#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.04:04:50.11#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.04:04:50.11#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.04:04:50.11#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.04:04:50.11$vck44/vblo=4,679.99 2006.173.04:04:50.11#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.04:04:50.11#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.04:04:50.11#ibcon#ireg 17 cls_cnt 0 2006.173.04:04:50.11#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.04:04:50.11#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.04:04:50.11#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.04:04:50.11#ibcon#enter wrdev, iclass 36, count 0 2006.173.04:04:50.11#ibcon#first serial, iclass 36, count 0 2006.173.04:04:50.11#ibcon#enter sib2, iclass 36, count 0 2006.173.04:04:50.11#ibcon#flushed, iclass 36, count 0 2006.173.04:04:50.11#ibcon#about to write, iclass 36, count 0 2006.173.04:04:50.11#ibcon#wrote, iclass 36, count 0 2006.173.04:04:50.11#ibcon#about to read 3, iclass 36, count 0 2006.173.04:04:50.13#ibcon#read 3, iclass 36, count 0 2006.173.04:04:50.13#ibcon#about to read 4, iclass 36, count 0 2006.173.04:04:50.13#ibcon#read 4, iclass 36, count 0 2006.173.04:04:50.13#ibcon#about to read 5, iclass 36, count 0 2006.173.04:04:50.13#ibcon#read 5, iclass 36, count 0 2006.173.04:04:50.13#ibcon#about to read 6, iclass 36, count 0 2006.173.04:04:50.13#ibcon#read 6, iclass 36, count 0 2006.173.04:04:50.13#ibcon#end of sib2, iclass 36, count 0 2006.173.04:04:50.13#ibcon#*mode == 0, iclass 36, count 0 2006.173.04:04:50.13#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.04:04:50.13#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.04:04:50.13#ibcon#*before write, iclass 36, count 0 2006.173.04:04:50.13#ibcon#enter sib2, iclass 36, count 0 2006.173.04:04:50.13#ibcon#flushed, iclass 36, count 0 2006.173.04:04:50.13#ibcon#about to write, iclass 36, count 0 2006.173.04:04:50.13#ibcon#wrote, iclass 36, count 0 2006.173.04:04:50.13#ibcon#about to read 3, iclass 36, count 0 2006.173.04:04:50.17#ibcon#read 3, iclass 36, count 0 2006.173.04:04:50.17#ibcon#about to read 4, iclass 36, count 0 2006.173.04:04:50.17#ibcon#read 4, iclass 36, count 0 2006.173.04:04:50.17#ibcon#about to read 5, iclass 36, count 0 2006.173.04:04:50.17#ibcon#read 5, iclass 36, count 0 2006.173.04:04:50.17#ibcon#about to read 6, iclass 36, count 0 2006.173.04:04:50.17#ibcon#read 6, iclass 36, count 0 2006.173.04:04:50.17#ibcon#end of sib2, iclass 36, count 0 2006.173.04:04:50.17#ibcon#*after write, iclass 36, count 0 2006.173.04:04:50.17#ibcon#*before return 0, iclass 36, count 0 2006.173.04:04:50.17#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.04:04:50.17#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.04:04:50.17#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.04:04:50.17#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.04:04:50.17$vck44/vb=4,4 2006.173.04:04:50.17#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.04:04:50.17#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.04:04:50.17#ibcon#ireg 11 cls_cnt 2 2006.173.04:04:50.17#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.04:04:50.23#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.04:04:50.23#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.04:04:50.23#ibcon#enter wrdev, iclass 38, count 2 2006.173.04:04:50.23#ibcon#first serial, iclass 38, count 2 2006.173.04:04:50.23#ibcon#enter sib2, iclass 38, count 2 2006.173.04:04:50.23#ibcon#flushed, iclass 38, count 2 2006.173.04:04:50.23#ibcon#about to write, iclass 38, count 2 2006.173.04:04:50.23#ibcon#wrote, iclass 38, count 2 2006.173.04:04:50.23#ibcon#about to read 3, iclass 38, count 2 2006.173.04:04:50.25#ibcon#read 3, iclass 38, count 2 2006.173.04:04:50.25#ibcon#about to read 4, iclass 38, count 2 2006.173.04:04:50.25#ibcon#read 4, iclass 38, count 2 2006.173.04:04:50.25#ibcon#about to read 5, iclass 38, count 2 2006.173.04:04:50.25#ibcon#read 5, iclass 38, count 2 2006.173.04:04:50.25#ibcon#about to read 6, iclass 38, count 2 2006.173.04:04:50.25#ibcon#read 6, iclass 38, count 2 2006.173.04:04:50.25#ibcon#end of sib2, iclass 38, count 2 2006.173.04:04:50.25#ibcon#*mode == 0, iclass 38, count 2 2006.173.04:04:50.25#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.04:04:50.25#ibcon#[27=AT04-04\r\n] 2006.173.04:04:50.25#ibcon#*before write, iclass 38, count 2 2006.173.04:04:50.25#ibcon#enter sib2, iclass 38, count 2 2006.173.04:04:50.25#ibcon#flushed, iclass 38, count 2 2006.173.04:04:50.25#ibcon#about to write, iclass 38, count 2 2006.173.04:04:50.25#ibcon#wrote, iclass 38, count 2 2006.173.04:04:50.25#ibcon#about to read 3, iclass 38, count 2 2006.173.04:04:50.28#ibcon#read 3, iclass 38, count 2 2006.173.04:04:50.28#ibcon#about to read 4, iclass 38, count 2 2006.173.04:04:50.28#ibcon#read 4, iclass 38, count 2 2006.173.04:04:50.28#ibcon#about to read 5, iclass 38, count 2 2006.173.04:04:50.28#ibcon#read 5, iclass 38, count 2 2006.173.04:04:50.28#ibcon#about to read 6, iclass 38, count 2 2006.173.04:04:50.28#ibcon#read 6, iclass 38, count 2 2006.173.04:04:50.28#ibcon#end of sib2, iclass 38, count 2 2006.173.04:04:50.28#ibcon#*after write, iclass 38, count 2 2006.173.04:04:50.28#ibcon#*before return 0, iclass 38, count 2 2006.173.04:04:50.28#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.04:04:50.28#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.04:04:50.28#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.04:04:50.28#ibcon#ireg 7 cls_cnt 0 2006.173.04:04:50.28#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.04:04:50.40#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.04:04:50.40#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.04:04:50.40#ibcon#enter wrdev, iclass 38, count 0 2006.173.04:04:50.40#ibcon#first serial, iclass 38, count 0 2006.173.04:04:50.40#ibcon#enter sib2, iclass 38, count 0 2006.173.04:04:50.40#ibcon#flushed, iclass 38, count 0 2006.173.04:04:50.40#ibcon#about to write, iclass 38, count 0 2006.173.04:04:50.40#ibcon#wrote, iclass 38, count 0 2006.173.04:04:50.40#ibcon#about to read 3, iclass 38, count 0 2006.173.04:04:50.42#ibcon#read 3, iclass 38, count 0 2006.173.04:04:50.42#ibcon#about to read 4, iclass 38, count 0 2006.173.04:04:50.42#ibcon#read 4, iclass 38, count 0 2006.173.04:04:50.42#ibcon#about to read 5, iclass 38, count 0 2006.173.04:04:50.42#ibcon#read 5, iclass 38, count 0 2006.173.04:04:50.42#ibcon#about to read 6, iclass 38, count 0 2006.173.04:04:50.42#ibcon#read 6, iclass 38, count 0 2006.173.04:04:50.42#ibcon#end of sib2, iclass 38, count 0 2006.173.04:04:50.42#ibcon#*mode == 0, iclass 38, count 0 2006.173.04:04:50.42#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.04:04:50.42#ibcon#[27=USB\r\n] 2006.173.04:04:50.42#ibcon#*before write, iclass 38, count 0 2006.173.04:04:50.42#ibcon#enter sib2, iclass 38, count 0 2006.173.04:04:50.42#ibcon#flushed, iclass 38, count 0 2006.173.04:04:50.42#ibcon#about to write, iclass 38, count 0 2006.173.04:04:50.42#ibcon#wrote, iclass 38, count 0 2006.173.04:04:50.42#ibcon#about to read 3, iclass 38, count 0 2006.173.04:04:50.45#ibcon#read 3, iclass 38, count 0 2006.173.04:04:50.45#ibcon#about to read 4, iclass 38, count 0 2006.173.04:04:50.45#ibcon#read 4, iclass 38, count 0 2006.173.04:04:50.45#ibcon#about to read 5, iclass 38, count 0 2006.173.04:04:50.45#ibcon#read 5, iclass 38, count 0 2006.173.04:04:50.45#ibcon#about to read 6, iclass 38, count 0 2006.173.04:04:50.45#ibcon#read 6, iclass 38, count 0 2006.173.04:04:50.45#ibcon#end of sib2, iclass 38, count 0 2006.173.04:04:50.45#ibcon#*after write, iclass 38, count 0 2006.173.04:04:50.45#ibcon#*before return 0, iclass 38, count 0 2006.173.04:04:50.45#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.04:04:50.45#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.04:04:50.45#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.04:04:50.45#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.04:04:50.45$vck44/vblo=5,709.99 2006.173.04:04:50.45#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.04:04:50.45#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.04:04:50.45#ibcon#ireg 17 cls_cnt 0 2006.173.04:04:50.45#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.04:04:50.45#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.04:04:50.45#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.04:04:50.45#ibcon#enter wrdev, iclass 40, count 0 2006.173.04:04:50.45#ibcon#first serial, iclass 40, count 0 2006.173.04:04:50.45#ibcon#enter sib2, iclass 40, count 0 2006.173.04:04:50.45#ibcon#flushed, iclass 40, count 0 2006.173.04:04:50.45#ibcon#about to write, iclass 40, count 0 2006.173.04:04:50.45#ibcon#wrote, iclass 40, count 0 2006.173.04:04:50.45#ibcon#about to read 3, iclass 40, count 0 2006.173.04:04:50.47#ibcon#read 3, iclass 40, count 0 2006.173.04:04:50.47#ibcon#about to read 4, iclass 40, count 0 2006.173.04:04:50.47#ibcon#read 4, iclass 40, count 0 2006.173.04:04:50.47#ibcon#about to read 5, iclass 40, count 0 2006.173.04:04:50.47#ibcon#read 5, iclass 40, count 0 2006.173.04:04:50.47#ibcon#about to read 6, iclass 40, count 0 2006.173.04:04:50.47#ibcon#read 6, iclass 40, count 0 2006.173.04:04:50.47#ibcon#end of sib2, iclass 40, count 0 2006.173.04:04:50.47#ibcon#*mode == 0, iclass 40, count 0 2006.173.04:04:50.47#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.04:04:50.47#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.04:04:50.47#ibcon#*before write, iclass 40, count 0 2006.173.04:04:50.47#ibcon#enter sib2, iclass 40, count 0 2006.173.04:04:50.47#ibcon#flushed, iclass 40, count 0 2006.173.04:04:50.47#ibcon#about to write, iclass 40, count 0 2006.173.04:04:50.47#ibcon#wrote, iclass 40, count 0 2006.173.04:04:50.47#ibcon#about to read 3, iclass 40, count 0 2006.173.04:04:50.51#ibcon#read 3, iclass 40, count 0 2006.173.04:04:50.51#ibcon#about to read 4, iclass 40, count 0 2006.173.04:04:50.51#ibcon#read 4, iclass 40, count 0 2006.173.04:04:50.51#ibcon#about to read 5, iclass 40, count 0 2006.173.04:04:50.51#ibcon#read 5, iclass 40, count 0 2006.173.04:04:50.51#ibcon#about to read 6, iclass 40, count 0 2006.173.04:04:50.51#ibcon#read 6, iclass 40, count 0 2006.173.04:04:50.51#ibcon#end of sib2, iclass 40, count 0 2006.173.04:04:50.51#ibcon#*after write, iclass 40, count 0 2006.173.04:04:50.51#ibcon#*before return 0, iclass 40, count 0 2006.173.04:04:50.51#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.04:04:50.51#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.04:04:50.51#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.04:04:50.51#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.04:04:50.51$vck44/vb=5,4 2006.173.04:04:50.51#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.04:04:50.51#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.04:04:50.51#ibcon#ireg 11 cls_cnt 2 2006.173.04:04:50.51#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.04:04:50.57#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.04:04:50.57#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.04:04:50.57#ibcon#enter wrdev, iclass 4, count 2 2006.173.04:04:50.57#ibcon#first serial, iclass 4, count 2 2006.173.04:04:50.57#ibcon#enter sib2, iclass 4, count 2 2006.173.04:04:50.57#ibcon#flushed, iclass 4, count 2 2006.173.04:04:50.57#ibcon#about to write, iclass 4, count 2 2006.173.04:04:50.57#ibcon#wrote, iclass 4, count 2 2006.173.04:04:50.57#ibcon#about to read 3, iclass 4, count 2 2006.173.04:04:50.59#ibcon#read 3, iclass 4, count 2 2006.173.04:04:50.59#ibcon#about to read 4, iclass 4, count 2 2006.173.04:04:50.59#ibcon#read 4, iclass 4, count 2 2006.173.04:04:50.59#ibcon#about to read 5, iclass 4, count 2 2006.173.04:04:50.59#ibcon#read 5, iclass 4, count 2 2006.173.04:04:50.59#ibcon#about to read 6, iclass 4, count 2 2006.173.04:04:50.59#ibcon#read 6, iclass 4, count 2 2006.173.04:04:50.59#ibcon#end of sib2, iclass 4, count 2 2006.173.04:04:50.59#ibcon#*mode == 0, iclass 4, count 2 2006.173.04:04:50.59#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.04:04:50.59#ibcon#[27=AT05-04\r\n] 2006.173.04:04:50.59#ibcon#*before write, iclass 4, count 2 2006.173.04:04:50.59#ibcon#enter sib2, iclass 4, count 2 2006.173.04:04:50.59#ibcon#flushed, iclass 4, count 2 2006.173.04:04:50.59#ibcon#about to write, iclass 4, count 2 2006.173.04:04:50.59#ibcon#wrote, iclass 4, count 2 2006.173.04:04:50.59#ibcon#about to read 3, iclass 4, count 2 2006.173.04:04:50.62#ibcon#read 3, iclass 4, count 2 2006.173.04:04:50.62#ibcon#about to read 4, iclass 4, count 2 2006.173.04:04:50.62#ibcon#read 4, iclass 4, count 2 2006.173.04:04:50.62#ibcon#about to read 5, iclass 4, count 2 2006.173.04:04:50.62#ibcon#read 5, iclass 4, count 2 2006.173.04:04:50.62#ibcon#about to read 6, iclass 4, count 2 2006.173.04:04:50.62#ibcon#read 6, iclass 4, count 2 2006.173.04:04:50.62#ibcon#end of sib2, iclass 4, count 2 2006.173.04:04:50.62#ibcon#*after write, iclass 4, count 2 2006.173.04:04:50.62#ibcon#*before return 0, iclass 4, count 2 2006.173.04:04:50.62#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.04:04:50.62#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.04:04:50.62#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.04:04:50.62#ibcon#ireg 7 cls_cnt 0 2006.173.04:04:50.62#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.04:04:50.74#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.04:04:50.74#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.04:04:50.74#ibcon#enter wrdev, iclass 4, count 0 2006.173.04:04:50.74#ibcon#first serial, iclass 4, count 0 2006.173.04:04:50.74#ibcon#enter sib2, iclass 4, count 0 2006.173.04:04:50.74#ibcon#flushed, iclass 4, count 0 2006.173.04:04:50.74#ibcon#about to write, iclass 4, count 0 2006.173.04:04:50.74#ibcon#wrote, iclass 4, count 0 2006.173.04:04:50.74#ibcon#about to read 3, iclass 4, count 0 2006.173.04:04:50.76#ibcon#read 3, iclass 4, count 0 2006.173.04:04:50.76#ibcon#about to read 4, iclass 4, count 0 2006.173.04:04:50.76#ibcon#read 4, iclass 4, count 0 2006.173.04:04:50.76#ibcon#about to read 5, iclass 4, count 0 2006.173.04:04:50.76#ibcon#read 5, iclass 4, count 0 2006.173.04:04:50.76#ibcon#about to read 6, iclass 4, count 0 2006.173.04:04:50.76#ibcon#read 6, iclass 4, count 0 2006.173.04:04:50.76#ibcon#end of sib2, iclass 4, count 0 2006.173.04:04:50.76#ibcon#*mode == 0, iclass 4, count 0 2006.173.04:04:50.76#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.04:04:50.76#ibcon#[27=USB\r\n] 2006.173.04:04:50.76#ibcon#*before write, iclass 4, count 0 2006.173.04:04:50.76#ibcon#enter sib2, iclass 4, count 0 2006.173.04:04:50.76#ibcon#flushed, iclass 4, count 0 2006.173.04:04:50.76#ibcon#about to write, iclass 4, count 0 2006.173.04:04:50.76#ibcon#wrote, iclass 4, count 0 2006.173.04:04:50.76#ibcon#about to read 3, iclass 4, count 0 2006.173.04:04:50.79#ibcon#read 3, iclass 4, count 0 2006.173.04:04:50.79#ibcon#about to read 4, iclass 4, count 0 2006.173.04:04:50.79#ibcon#read 4, iclass 4, count 0 2006.173.04:04:50.79#ibcon#about to read 5, iclass 4, count 0 2006.173.04:04:50.79#ibcon#read 5, iclass 4, count 0 2006.173.04:04:50.79#ibcon#about to read 6, iclass 4, count 0 2006.173.04:04:50.79#ibcon#read 6, iclass 4, count 0 2006.173.04:04:50.79#ibcon#end of sib2, iclass 4, count 0 2006.173.04:04:50.79#ibcon#*after write, iclass 4, count 0 2006.173.04:04:50.79#ibcon#*before return 0, iclass 4, count 0 2006.173.04:04:50.79#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.04:04:50.79#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.04:04:50.79#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.04:04:50.79#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.04:04:50.79$vck44/vblo=6,719.99 2006.173.04:04:50.79#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.04:04:50.79#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.04:04:50.79#ibcon#ireg 17 cls_cnt 0 2006.173.04:04:50.79#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.04:04:50.79#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.04:04:50.79#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.04:04:50.79#ibcon#enter wrdev, iclass 6, count 0 2006.173.04:04:50.79#ibcon#first serial, iclass 6, count 0 2006.173.04:04:50.79#ibcon#enter sib2, iclass 6, count 0 2006.173.04:04:50.79#ibcon#flushed, iclass 6, count 0 2006.173.04:04:50.79#ibcon#about to write, iclass 6, count 0 2006.173.04:04:50.79#ibcon#wrote, iclass 6, count 0 2006.173.04:04:50.79#ibcon#about to read 3, iclass 6, count 0 2006.173.04:04:50.81#ibcon#read 3, iclass 6, count 0 2006.173.04:04:50.81#ibcon#about to read 4, iclass 6, count 0 2006.173.04:04:50.81#ibcon#read 4, iclass 6, count 0 2006.173.04:04:50.81#ibcon#about to read 5, iclass 6, count 0 2006.173.04:04:50.81#ibcon#read 5, iclass 6, count 0 2006.173.04:04:50.81#ibcon#about to read 6, iclass 6, count 0 2006.173.04:04:50.81#ibcon#read 6, iclass 6, count 0 2006.173.04:04:50.81#ibcon#end of sib2, iclass 6, count 0 2006.173.04:04:50.81#ibcon#*mode == 0, iclass 6, count 0 2006.173.04:04:50.81#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.04:04:50.81#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.04:04:50.81#ibcon#*before write, iclass 6, count 0 2006.173.04:04:50.81#ibcon#enter sib2, iclass 6, count 0 2006.173.04:04:50.81#ibcon#flushed, iclass 6, count 0 2006.173.04:04:50.81#ibcon#about to write, iclass 6, count 0 2006.173.04:04:50.81#ibcon#wrote, iclass 6, count 0 2006.173.04:04:50.81#ibcon#about to read 3, iclass 6, count 0 2006.173.04:04:50.85#ibcon#read 3, iclass 6, count 0 2006.173.04:04:50.85#ibcon#about to read 4, iclass 6, count 0 2006.173.04:04:50.85#ibcon#read 4, iclass 6, count 0 2006.173.04:04:50.85#ibcon#about to read 5, iclass 6, count 0 2006.173.04:04:50.85#ibcon#read 5, iclass 6, count 0 2006.173.04:04:50.85#ibcon#about to read 6, iclass 6, count 0 2006.173.04:04:50.85#ibcon#read 6, iclass 6, count 0 2006.173.04:04:50.85#ibcon#end of sib2, iclass 6, count 0 2006.173.04:04:50.85#ibcon#*after write, iclass 6, count 0 2006.173.04:04:50.85#ibcon#*before return 0, iclass 6, count 0 2006.173.04:04:50.85#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.04:04:50.85#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.04:04:50.85#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.04:04:50.85#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.04:04:50.85$vck44/vb=6,4 2006.173.04:04:50.85#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.04:04:50.85#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.04:04:50.85#ibcon#ireg 11 cls_cnt 2 2006.173.04:04:50.85#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.04:04:50.91#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.04:04:50.91#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.04:04:50.91#ibcon#enter wrdev, iclass 10, count 2 2006.173.04:04:50.91#ibcon#first serial, iclass 10, count 2 2006.173.04:04:50.91#ibcon#enter sib2, iclass 10, count 2 2006.173.04:04:50.91#ibcon#flushed, iclass 10, count 2 2006.173.04:04:50.91#ibcon#about to write, iclass 10, count 2 2006.173.04:04:50.91#ibcon#wrote, iclass 10, count 2 2006.173.04:04:50.91#ibcon#about to read 3, iclass 10, count 2 2006.173.04:04:50.93#ibcon#read 3, iclass 10, count 2 2006.173.04:04:50.93#ibcon#about to read 4, iclass 10, count 2 2006.173.04:04:50.93#ibcon#read 4, iclass 10, count 2 2006.173.04:04:50.93#ibcon#about to read 5, iclass 10, count 2 2006.173.04:04:50.93#ibcon#read 5, iclass 10, count 2 2006.173.04:04:50.93#ibcon#about to read 6, iclass 10, count 2 2006.173.04:04:50.93#ibcon#read 6, iclass 10, count 2 2006.173.04:04:50.93#ibcon#end of sib2, iclass 10, count 2 2006.173.04:04:50.93#ibcon#*mode == 0, iclass 10, count 2 2006.173.04:04:50.93#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.04:04:50.93#ibcon#[27=AT06-04\r\n] 2006.173.04:04:50.93#ibcon#*before write, iclass 10, count 2 2006.173.04:04:50.93#ibcon#enter sib2, iclass 10, count 2 2006.173.04:04:50.93#ibcon#flushed, iclass 10, count 2 2006.173.04:04:50.93#ibcon#about to write, iclass 10, count 2 2006.173.04:04:50.93#ibcon#wrote, iclass 10, count 2 2006.173.04:04:50.93#ibcon#about to read 3, iclass 10, count 2 2006.173.04:04:50.96#ibcon#read 3, iclass 10, count 2 2006.173.04:04:50.96#ibcon#about to read 4, iclass 10, count 2 2006.173.04:04:50.96#ibcon#read 4, iclass 10, count 2 2006.173.04:04:50.96#ibcon#about to read 5, iclass 10, count 2 2006.173.04:04:50.96#ibcon#read 5, iclass 10, count 2 2006.173.04:04:50.96#ibcon#about to read 6, iclass 10, count 2 2006.173.04:04:50.96#ibcon#read 6, iclass 10, count 2 2006.173.04:04:50.96#ibcon#end of sib2, iclass 10, count 2 2006.173.04:04:50.96#ibcon#*after write, iclass 10, count 2 2006.173.04:04:50.96#ibcon#*before return 0, iclass 10, count 2 2006.173.04:04:50.96#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.04:04:50.96#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.04:04:50.96#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.04:04:50.96#ibcon#ireg 7 cls_cnt 0 2006.173.04:04:50.96#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.04:04:51.08#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.04:04:51.08#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.04:04:51.08#ibcon#enter wrdev, iclass 10, count 0 2006.173.04:04:51.08#ibcon#first serial, iclass 10, count 0 2006.173.04:04:51.08#ibcon#enter sib2, iclass 10, count 0 2006.173.04:04:51.08#ibcon#flushed, iclass 10, count 0 2006.173.04:04:51.08#ibcon#about to write, iclass 10, count 0 2006.173.04:04:51.08#ibcon#wrote, iclass 10, count 0 2006.173.04:04:51.08#ibcon#about to read 3, iclass 10, count 0 2006.173.04:04:51.10#ibcon#read 3, iclass 10, count 0 2006.173.04:04:51.10#ibcon#about to read 4, iclass 10, count 0 2006.173.04:04:51.10#ibcon#read 4, iclass 10, count 0 2006.173.04:04:51.10#ibcon#about to read 5, iclass 10, count 0 2006.173.04:04:51.10#ibcon#read 5, iclass 10, count 0 2006.173.04:04:51.10#ibcon#about to read 6, iclass 10, count 0 2006.173.04:04:51.10#ibcon#read 6, iclass 10, count 0 2006.173.04:04:51.10#ibcon#end of sib2, iclass 10, count 0 2006.173.04:04:51.10#ibcon#*mode == 0, iclass 10, count 0 2006.173.04:04:51.10#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.04:04:51.10#ibcon#[27=USB\r\n] 2006.173.04:04:51.10#ibcon#*before write, iclass 10, count 0 2006.173.04:04:51.10#ibcon#enter sib2, iclass 10, count 0 2006.173.04:04:51.10#ibcon#flushed, iclass 10, count 0 2006.173.04:04:51.10#ibcon#about to write, iclass 10, count 0 2006.173.04:04:51.10#ibcon#wrote, iclass 10, count 0 2006.173.04:04:51.10#ibcon#about to read 3, iclass 10, count 0 2006.173.04:04:51.13#ibcon#read 3, iclass 10, count 0 2006.173.04:04:51.13#ibcon#about to read 4, iclass 10, count 0 2006.173.04:04:51.13#ibcon#read 4, iclass 10, count 0 2006.173.04:04:51.13#ibcon#about to read 5, iclass 10, count 0 2006.173.04:04:51.13#ibcon#read 5, iclass 10, count 0 2006.173.04:04:51.13#ibcon#about to read 6, iclass 10, count 0 2006.173.04:04:51.13#ibcon#read 6, iclass 10, count 0 2006.173.04:04:51.13#ibcon#end of sib2, iclass 10, count 0 2006.173.04:04:51.13#ibcon#*after write, iclass 10, count 0 2006.173.04:04:51.13#ibcon#*before return 0, iclass 10, count 0 2006.173.04:04:51.13#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.04:04:51.13#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.04:04:51.13#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.04:04:51.13#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.04:04:51.13$vck44/vblo=7,734.99 2006.173.04:04:51.13#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.04:04:51.13#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.04:04:51.13#ibcon#ireg 17 cls_cnt 0 2006.173.04:04:51.13#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.04:04:51.13#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.04:04:51.13#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.04:04:51.13#ibcon#enter wrdev, iclass 12, count 0 2006.173.04:04:51.13#ibcon#first serial, iclass 12, count 0 2006.173.04:04:51.13#ibcon#enter sib2, iclass 12, count 0 2006.173.04:04:51.13#ibcon#flushed, iclass 12, count 0 2006.173.04:04:51.13#ibcon#about to write, iclass 12, count 0 2006.173.04:04:51.13#ibcon#wrote, iclass 12, count 0 2006.173.04:04:51.13#ibcon#about to read 3, iclass 12, count 0 2006.173.04:04:51.15#ibcon#read 3, iclass 12, count 0 2006.173.04:04:51.15#ibcon#about to read 4, iclass 12, count 0 2006.173.04:04:51.15#ibcon#read 4, iclass 12, count 0 2006.173.04:04:51.15#ibcon#about to read 5, iclass 12, count 0 2006.173.04:04:51.15#ibcon#read 5, iclass 12, count 0 2006.173.04:04:51.15#ibcon#about to read 6, iclass 12, count 0 2006.173.04:04:51.15#ibcon#read 6, iclass 12, count 0 2006.173.04:04:51.15#ibcon#end of sib2, iclass 12, count 0 2006.173.04:04:51.15#ibcon#*mode == 0, iclass 12, count 0 2006.173.04:04:51.15#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.04:04:51.15#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.04:04:51.15#ibcon#*before write, iclass 12, count 0 2006.173.04:04:51.15#ibcon#enter sib2, iclass 12, count 0 2006.173.04:04:51.15#ibcon#flushed, iclass 12, count 0 2006.173.04:04:51.15#ibcon#about to write, iclass 12, count 0 2006.173.04:04:51.15#ibcon#wrote, iclass 12, count 0 2006.173.04:04:51.15#ibcon#about to read 3, iclass 12, count 0 2006.173.04:04:51.19#ibcon#read 3, iclass 12, count 0 2006.173.04:04:51.19#ibcon#about to read 4, iclass 12, count 0 2006.173.04:04:51.19#ibcon#read 4, iclass 12, count 0 2006.173.04:04:51.19#ibcon#about to read 5, iclass 12, count 0 2006.173.04:04:51.19#ibcon#read 5, iclass 12, count 0 2006.173.04:04:51.19#ibcon#about to read 6, iclass 12, count 0 2006.173.04:04:51.19#ibcon#read 6, iclass 12, count 0 2006.173.04:04:51.19#ibcon#end of sib2, iclass 12, count 0 2006.173.04:04:51.19#ibcon#*after write, iclass 12, count 0 2006.173.04:04:51.19#ibcon#*before return 0, iclass 12, count 0 2006.173.04:04:51.19#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.04:04:51.19#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.04:04:51.19#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.04:04:51.19#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.04:04:51.19$vck44/vb=7,4 2006.173.04:04:51.19#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.04:04:51.19#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.04:04:51.19#ibcon#ireg 11 cls_cnt 2 2006.173.04:04:51.19#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.04:04:51.25#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.04:04:51.25#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.04:04:51.25#ibcon#enter wrdev, iclass 14, count 2 2006.173.04:04:51.25#ibcon#first serial, iclass 14, count 2 2006.173.04:04:51.25#ibcon#enter sib2, iclass 14, count 2 2006.173.04:04:51.25#ibcon#flushed, iclass 14, count 2 2006.173.04:04:51.25#ibcon#about to write, iclass 14, count 2 2006.173.04:04:51.25#ibcon#wrote, iclass 14, count 2 2006.173.04:04:51.25#ibcon#about to read 3, iclass 14, count 2 2006.173.04:04:51.27#ibcon#read 3, iclass 14, count 2 2006.173.04:04:51.27#ibcon#about to read 4, iclass 14, count 2 2006.173.04:04:51.27#ibcon#read 4, iclass 14, count 2 2006.173.04:04:51.27#ibcon#about to read 5, iclass 14, count 2 2006.173.04:04:51.27#ibcon#read 5, iclass 14, count 2 2006.173.04:04:51.27#ibcon#about to read 6, iclass 14, count 2 2006.173.04:04:51.27#ibcon#read 6, iclass 14, count 2 2006.173.04:04:51.27#ibcon#end of sib2, iclass 14, count 2 2006.173.04:04:51.27#ibcon#*mode == 0, iclass 14, count 2 2006.173.04:04:51.27#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.04:04:51.27#ibcon#[27=AT07-04\r\n] 2006.173.04:04:51.27#ibcon#*before write, iclass 14, count 2 2006.173.04:04:51.27#ibcon#enter sib2, iclass 14, count 2 2006.173.04:04:51.27#ibcon#flushed, iclass 14, count 2 2006.173.04:04:51.27#ibcon#about to write, iclass 14, count 2 2006.173.04:04:51.27#ibcon#wrote, iclass 14, count 2 2006.173.04:04:51.27#ibcon#about to read 3, iclass 14, count 2 2006.173.04:04:51.30#ibcon#read 3, iclass 14, count 2 2006.173.04:04:51.30#ibcon#about to read 4, iclass 14, count 2 2006.173.04:04:51.30#ibcon#read 4, iclass 14, count 2 2006.173.04:04:51.30#ibcon#about to read 5, iclass 14, count 2 2006.173.04:04:51.30#ibcon#read 5, iclass 14, count 2 2006.173.04:04:51.30#ibcon#about to read 6, iclass 14, count 2 2006.173.04:04:51.30#ibcon#read 6, iclass 14, count 2 2006.173.04:04:51.30#ibcon#end of sib2, iclass 14, count 2 2006.173.04:04:51.30#ibcon#*after write, iclass 14, count 2 2006.173.04:04:51.30#ibcon#*before return 0, iclass 14, count 2 2006.173.04:04:51.30#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.04:04:51.30#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.04:04:51.30#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.04:04:51.30#ibcon#ireg 7 cls_cnt 0 2006.173.04:04:51.30#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.04:04:51.42#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.04:04:51.42#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.04:04:51.42#ibcon#enter wrdev, iclass 14, count 0 2006.173.04:04:51.42#ibcon#first serial, iclass 14, count 0 2006.173.04:04:51.42#ibcon#enter sib2, iclass 14, count 0 2006.173.04:04:51.42#ibcon#flushed, iclass 14, count 0 2006.173.04:04:51.42#ibcon#about to write, iclass 14, count 0 2006.173.04:04:51.42#ibcon#wrote, iclass 14, count 0 2006.173.04:04:51.42#ibcon#about to read 3, iclass 14, count 0 2006.173.04:04:51.44#ibcon#read 3, iclass 14, count 0 2006.173.04:04:51.44#ibcon#about to read 4, iclass 14, count 0 2006.173.04:04:51.44#ibcon#read 4, iclass 14, count 0 2006.173.04:04:51.44#ibcon#about to read 5, iclass 14, count 0 2006.173.04:04:51.44#ibcon#read 5, iclass 14, count 0 2006.173.04:04:51.44#ibcon#about to read 6, iclass 14, count 0 2006.173.04:04:51.44#ibcon#read 6, iclass 14, count 0 2006.173.04:04:51.44#ibcon#end of sib2, iclass 14, count 0 2006.173.04:04:51.44#ibcon#*mode == 0, iclass 14, count 0 2006.173.04:04:51.44#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.04:04:51.44#ibcon#[27=USB\r\n] 2006.173.04:04:51.44#ibcon#*before write, iclass 14, count 0 2006.173.04:04:51.44#ibcon#enter sib2, iclass 14, count 0 2006.173.04:04:51.44#ibcon#flushed, iclass 14, count 0 2006.173.04:04:51.44#ibcon#about to write, iclass 14, count 0 2006.173.04:04:51.44#ibcon#wrote, iclass 14, count 0 2006.173.04:04:51.44#ibcon#about to read 3, iclass 14, count 0 2006.173.04:04:51.47#ibcon#read 3, iclass 14, count 0 2006.173.04:04:51.47#ibcon#about to read 4, iclass 14, count 0 2006.173.04:04:51.47#ibcon#read 4, iclass 14, count 0 2006.173.04:04:51.47#ibcon#about to read 5, iclass 14, count 0 2006.173.04:04:51.47#ibcon#read 5, iclass 14, count 0 2006.173.04:04:51.47#ibcon#about to read 6, iclass 14, count 0 2006.173.04:04:51.47#ibcon#read 6, iclass 14, count 0 2006.173.04:04:51.47#ibcon#end of sib2, iclass 14, count 0 2006.173.04:04:51.47#ibcon#*after write, iclass 14, count 0 2006.173.04:04:51.47#ibcon#*before return 0, iclass 14, count 0 2006.173.04:04:51.47#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.04:04:51.47#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.04:04:51.47#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.04:04:51.47#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.04:04:51.47$vck44/vblo=8,744.99 2006.173.04:04:51.47#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.04:04:51.47#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.04:04:51.47#ibcon#ireg 17 cls_cnt 0 2006.173.04:04:51.47#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.04:04:51.47#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.04:04:51.47#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.04:04:51.47#ibcon#enter wrdev, iclass 16, count 0 2006.173.04:04:51.47#ibcon#first serial, iclass 16, count 0 2006.173.04:04:51.47#ibcon#enter sib2, iclass 16, count 0 2006.173.04:04:51.47#ibcon#flushed, iclass 16, count 0 2006.173.04:04:51.47#ibcon#about to write, iclass 16, count 0 2006.173.04:04:51.47#ibcon#wrote, iclass 16, count 0 2006.173.04:04:51.47#ibcon#about to read 3, iclass 16, count 0 2006.173.04:04:51.49#ibcon#read 3, iclass 16, count 0 2006.173.04:04:51.49#ibcon#about to read 4, iclass 16, count 0 2006.173.04:04:51.49#ibcon#read 4, iclass 16, count 0 2006.173.04:04:51.49#ibcon#about to read 5, iclass 16, count 0 2006.173.04:04:51.49#ibcon#read 5, iclass 16, count 0 2006.173.04:04:51.49#ibcon#about to read 6, iclass 16, count 0 2006.173.04:04:51.49#ibcon#read 6, iclass 16, count 0 2006.173.04:04:51.49#ibcon#end of sib2, iclass 16, count 0 2006.173.04:04:51.49#ibcon#*mode == 0, iclass 16, count 0 2006.173.04:04:51.49#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.04:04:51.49#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.04:04:51.49#ibcon#*before write, iclass 16, count 0 2006.173.04:04:51.49#ibcon#enter sib2, iclass 16, count 0 2006.173.04:04:51.49#ibcon#flushed, iclass 16, count 0 2006.173.04:04:51.49#ibcon#about to write, iclass 16, count 0 2006.173.04:04:51.49#ibcon#wrote, iclass 16, count 0 2006.173.04:04:51.49#ibcon#about to read 3, iclass 16, count 0 2006.173.04:04:51.53#ibcon#read 3, iclass 16, count 0 2006.173.04:04:51.53#ibcon#about to read 4, iclass 16, count 0 2006.173.04:04:51.53#ibcon#read 4, iclass 16, count 0 2006.173.04:04:51.53#ibcon#about to read 5, iclass 16, count 0 2006.173.04:04:51.53#ibcon#read 5, iclass 16, count 0 2006.173.04:04:51.53#ibcon#about to read 6, iclass 16, count 0 2006.173.04:04:51.53#ibcon#read 6, iclass 16, count 0 2006.173.04:04:51.53#ibcon#end of sib2, iclass 16, count 0 2006.173.04:04:51.53#ibcon#*after write, iclass 16, count 0 2006.173.04:04:51.53#ibcon#*before return 0, iclass 16, count 0 2006.173.04:04:51.53#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.04:04:51.53#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.04:04:51.53#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.04:04:51.53#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.04:04:51.53$vck44/vb=8,4 2006.173.04:04:51.53#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.04:04:51.53#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.04:04:51.53#ibcon#ireg 11 cls_cnt 2 2006.173.04:04:51.53#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.04:04:51.59#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.04:04:51.59#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.04:04:51.59#ibcon#enter wrdev, iclass 18, count 2 2006.173.04:04:51.59#ibcon#first serial, iclass 18, count 2 2006.173.04:04:51.59#ibcon#enter sib2, iclass 18, count 2 2006.173.04:04:51.59#ibcon#flushed, iclass 18, count 2 2006.173.04:04:51.59#ibcon#about to write, iclass 18, count 2 2006.173.04:04:51.59#ibcon#wrote, iclass 18, count 2 2006.173.04:04:51.59#ibcon#about to read 3, iclass 18, count 2 2006.173.04:04:51.61#ibcon#read 3, iclass 18, count 2 2006.173.04:04:51.61#ibcon#about to read 4, iclass 18, count 2 2006.173.04:04:51.61#ibcon#read 4, iclass 18, count 2 2006.173.04:04:51.61#ibcon#about to read 5, iclass 18, count 2 2006.173.04:04:51.61#ibcon#read 5, iclass 18, count 2 2006.173.04:04:51.61#ibcon#about to read 6, iclass 18, count 2 2006.173.04:04:51.61#ibcon#read 6, iclass 18, count 2 2006.173.04:04:51.61#ibcon#end of sib2, iclass 18, count 2 2006.173.04:04:51.61#ibcon#*mode == 0, iclass 18, count 2 2006.173.04:04:51.61#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.04:04:51.61#ibcon#[27=AT08-04\r\n] 2006.173.04:04:51.61#ibcon#*before write, iclass 18, count 2 2006.173.04:04:51.61#ibcon#enter sib2, iclass 18, count 2 2006.173.04:04:51.61#ibcon#flushed, iclass 18, count 2 2006.173.04:04:51.61#ibcon#about to write, iclass 18, count 2 2006.173.04:04:51.61#ibcon#wrote, iclass 18, count 2 2006.173.04:04:51.61#ibcon#about to read 3, iclass 18, count 2 2006.173.04:04:51.64#ibcon#read 3, iclass 18, count 2 2006.173.04:04:51.64#ibcon#about to read 4, iclass 18, count 2 2006.173.04:04:51.64#ibcon#read 4, iclass 18, count 2 2006.173.04:04:51.64#ibcon#about to read 5, iclass 18, count 2 2006.173.04:04:51.64#ibcon#read 5, iclass 18, count 2 2006.173.04:04:51.64#ibcon#about to read 6, iclass 18, count 2 2006.173.04:04:51.64#ibcon#read 6, iclass 18, count 2 2006.173.04:04:51.64#ibcon#end of sib2, iclass 18, count 2 2006.173.04:04:51.64#ibcon#*after write, iclass 18, count 2 2006.173.04:04:51.64#ibcon#*before return 0, iclass 18, count 2 2006.173.04:04:51.64#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.04:04:51.64#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.04:04:51.64#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.04:04:51.64#ibcon#ireg 7 cls_cnt 0 2006.173.04:04:51.64#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.04:04:51.76#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.04:04:51.76#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.04:04:51.76#ibcon#enter wrdev, iclass 18, count 0 2006.173.04:04:51.76#ibcon#first serial, iclass 18, count 0 2006.173.04:04:51.76#ibcon#enter sib2, iclass 18, count 0 2006.173.04:04:51.76#ibcon#flushed, iclass 18, count 0 2006.173.04:04:51.76#ibcon#about to write, iclass 18, count 0 2006.173.04:04:51.76#ibcon#wrote, iclass 18, count 0 2006.173.04:04:51.76#ibcon#about to read 3, iclass 18, count 0 2006.173.04:04:51.78#ibcon#read 3, iclass 18, count 0 2006.173.04:04:51.78#ibcon#about to read 4, iclass 18, count 0 2006.173.04:04:51.78#ibcon#read 4, iclass 18, count 0 2006.173.04:04:51.78#ibcon#about to read 5, iclass 18, count 0 2006.173.04:04:51.78#ibcon#read 5, iclass 18, count 0 2006.173.04:04:51.78#ibcon#about to read 6, iclass 18, count 0 2006.173.04:04:51.78#ibcon#read 6, iclass 18, count 0 2006.173.04:04:51.78#ibcon#end of sib2, iclass 18, count 0 2006.173.04:04:51.78#ibcon#*mode == 0, iclass 18, count 0 2006.173.04:04:51.78#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.04:04:51.78#ibcon#[27=USB\r\n] 2006.173.04:04:51.78#ibcon#*before write, iclass 18, count 0 2006.173.04:04:51.78#ibcon#enter sib2, iclass 18, count 0 2006.173.04:04:51.78#ibcon#flushed, iclass 18, count 0 2006.173.04:04:51.78#ibcon#about to write, iclass 18, count 0 2006.173.04:04:51.78#ibcon#wrote, iclass 18, count 0 2006.173.04:04:51.78#ibcon#about to read 3, iclass 18, count 0 2006.173.04:04:51.81#ibcon#read 3, iclass 18, count 0 2006.173.04:04:51.81#ibcon#about to read 4, iclass 18, count 0 2006.173.04:04:51.81#ibcon#read 4, iclass 18, count 0 2006.173.04:04:51.81#ibcon#about to read 5, iclass 18, count 0 2006.173.04:04:51.81#ibcon#read 5, iclass 18, count 0 2006.173.04:04:51.81#ibcon#about to read 6, iclass 18, count 0 2006.173.04:04:51.81#ibcon#read 6, iclass 18, count 0 2006.173.04:04:51.81#ibcon#end of sib2, iclass 18, count 0 2006.173.04:04:51.81#ibcon#*after write, iclass 18, count 0 2006.173.04:04:51.81#ibcon#*before return 0, iclass 18, count 0 2006.173.04:04:51.81#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.04:04:51.81#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.04:04:51.81#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.04:04:51.81#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.04:04:51.81$vck44/vabw=wide 2006.173.04:04:51.81#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.04:04:51.81#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.04:04:51.81#ibcon#ireg 8 cls_cnt 0 2006.173.04:04:51.81#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.04:04:51.81#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.04:04:51.81#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.04:04:51.81#ibcon#enter wrdev, iclass 20, count 0 2006.173.04:04:51.81#ibcon#first serial, iclass 20, count 0 2006.173.04:04:51.81#ibcon#enter sib2, iclass 20, count 0 2006.173.04:04:51.81#ibcon#flushed, iclass 20, count 0 2006.173.04:04:51.81#ibcon#about to write, iclass 20, count 0 2006.173.04:04:51.81#ibcon#wrote, iclass 20, count 0 2006.173.04:04:51.81#ibcon#about to read 3, iclass 20, count 0 2006.173.04:04:51.83#ibcon#read 3, iclass 20, count 0 2006.173.04:04:51.83#ibcon#about to read 4, iclass 20, count 0 2006.173.04:04:51.83#ibcon#read 4, iclass 20, count 0 2006.173.04:04:51.83#ibcon#about to read 5, iclass 20, count 0 2006.173.04:04:51.83#ibcon#read 5, iclass 20, count 0 2006.173.04:04:51.83#ibcon#about to read 6, iclass 20, count 0 2006.173.04:04:51.83#ibcon#read 6, iclass 20, count 0 2006.173.04:04:51.83#ibcon#end of sib2, iclass 20, count 0 2006.173.04:04:51.83#ibcon#*mode == 0, iclass 20, count 0 2006.173.04:04:51.83#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.04:04:51.83#ibcon#[25=BW32\r\n] 2006.173.04:04:51.83#ibcon#*before write, iclass 20, count 0 2006.173.04:04:51.83#ibcon#enter sib2, iclass 20, count 0 2006.173.04:04:51.83#ibcon#flushed, iclass 20, count 0 2006.173.04:04:51.83#ibcon#about to write, iclass 20, count 0 2006.173.04:04:51.83#ibcon#wrote, iclass 20, count 0 2006.173.04:04:51.83#ibcon#about to read 3, iclass 20, count 0 2006.173.04:04:51.86#ibcon#read 3, iclass 20, count 0 2006.173.04:04:51.86#ibcon#about to read 4, iclass 20, count 0 2006.173.04:04:51.86#ibcon#read 4, iclass 20, count 0 2006.173.04:04:51.86#ibcon#about to read 5, iclass 20, count 0 2006.173.04:04:51.86#ibcon#read 5, iclass 20, count 0 2006.173.04:04:51.86#ibcon#about to read 6, iclass 20, count 0 2006.173.04:04:51.86#ibcon#read 6, iclass 20, count 0 2006.173.04:04:51.86#ibcon#end of sib2, iclass 20, count 0 2006.173.04:04:51.86#ibcon#*after write, iclass 20, count 0 2006.173.04:04:51.86#ibcon#*before return 0, iclass 20, count 0 2006.173.04:04:51.86#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.04:04:51.86#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.04:04:51.86#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.04:04:51.86#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.04:04:51.86$vck44/vbbw=wide 2006.173.04:04:51.86#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.04:04:51.86#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.04:04:51.86#ibcon#ireg 8 cls_cnt 0 2006.173.04:04:51.86#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.04:04:51.93#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.04:04:51.93#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.04:04:51.93#ibcon#enter wrdev, iclass 22, count 0 2006.173.04:04:51.93#ibcon#first serial, iclass 22, count 0 2006.173.04:04:51.93#ibcon#enter sib2, iclass 22, count 0 2006.173.04:04:51.93#ibcon#flushed, iclass 22, count 0 2006.173.04:04:51.93#ibcon#about to write, iclass 22, count 0 2006.173.04:04:51.93#ibcon#wrote, iclass 22, count 0 2006.173.04:04:51.93#ibcon#about to read 3, iclass 22, count 0 2006.173.04:04:51.95#ibcon#read 3, iclass 22, count 0 2006.173.04:04:51.95#ibcon#about to read 4, iclass 22, count 0 2006.173.04:04:51.95#ibcon#read 4, iclass 22, count 0 2006.173.04:04:51.95#ibcon#about to read 5, iclass 22, count 0 2006.173.04:04:51.95#ibcon#read 5, iclass 22, count 0 2006.173.04:04:51.95#ibcon#about to read 6, iclass 22, count 0 2006.173.04:04:51.95#ibcon#read 6, iclass 22, count 0 2006.173.04:04:51.95#ibcon#end of sib2, iclass 22, count 0 2006.173.04:04:51.95#ibcon#*mode == 0, iclass 22, count 0 2006.173.04:04:51.95#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.04:04:51.95#ibcon#[27=BW32\r\n] 2006.173.04:04:51.95#ibcon#*before write, iclass 22, count 0 2006.173.04:04:51.95#ibcon#enter sib2, iclass 22, count 0 2006.173.04:04:51.95#ibcon#flushed, iclass 22, count 0 2006.173.04:04:51.95#ibcon#about to write, iclass 22, count 0 2006.173.04:04:51.95#ibcon#wrote, iclass 22, count 0 2006.173.04:04:51.95#ibcon#about to read 3, iclass 22, count 0 2006.173.04:04:51.98#ibcon#read 3, iclass 22, count 0 2006.173.04:04:51.98#ibcon#about to read 4, iclass 22, count 0 2006.173.04:04:51.98#ibcon#read 4, iclass 22, count 0 2006.173.04:04:51.98#ibcon#about to read 5, iclass 22, count 0 2006.173.04:04:51.98#ibcon#read 5, iclass 22, count 0 2006.173.04:04:51.98#ibcon#about to read 6, iclass 22, count 0 2006.173.04:04:51.98#ibcon#read 6, iclass 22, count 0 2006.173.04:04:51.98#ibcon#end of sib2, iclass 22, count 0 2006.173.04:04:51.98#ibcon#*after write, iclass 22, count 0 2006.173.04:04:51.98#ibcon#*before return 0, iclass 22, count 0 2006.173.04:04:51.98#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.04:04:51.98#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.04:04:51.98#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.04:04:51.98#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.04:04:51.98$setupk4/ifdk4 2006.173.04:04:51.98$ifdk4/lo= 2006.173.04:04:51.98$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.04:04:51.98$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.04:04:51.99$ifdk4/patch= 2006.173.04:04:51.99$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.04:04:51.99$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.04:04:51.99$setupk4/!*+20s 2006.173.04:04:54.21#abcon#<5=/14 1.4 3.0 23.04 791006.1\r\n> 2006.173.04:04:54.23#abcon#{5=INTERFACE CLEAR} 2006.173.04:04:54.29#abcon#[5=S1D000X0/0*\r\n] 2006.173.04:04:59.14#trakl#Source acquired 2006.173.04:05:01.14#flagr#flagr/antenna,acquired 2006.173.04:05:04.38#abcon#<5=/14 1.4 3.0 23.04 791006.1\r\n> 2006.173.04:05:04.40#abcon#{5=INTERFACE CLEAR} 2006.173.04:05:04.46#abcon#[5=S1D000X0/0*\r\n] 2006.173.04:05:06.50$setupk4/"tpicd 2006.173.04:05:06.50$setupk4/echo=off 2006.173.04:05:06.50$setupk4/xlog=off 2006.173.04:05:06.50:!2006.173.04:08:03 2006.173.04:08:03.00:preob 2006.173.04:08:03.14/onsource/TRACKING 2006.173.04:08:03.14:!2006.173.04:08:13 2006.173.04:08:13.00:"tape 2006.173.04:08:13.00:"st=record 2006.173.04:08:13.00:data_valid=on 2006.173.04:08:13.00:midob 2006.173.04:08:13.14/onsource/TRACKING 2006.173.04:08:13.14/wx/23.02,1006.0,80 2006.173.04:08:13.24/cable/+6.5095E-03 2006.173.04:08:14.33/va/01,07,usb,yes,35,38 2006.173.04:08:14.33/va/02,06,usb,yes,35,36 2006.173.04:08:14.33/va/03,05,usb,yes,45,47 2006.173.04:08:14.33/va/04,06,usb,yes,36,38 2006.173.04:08:14.33/va/05,04,usb,yes,28,29 2006.173.04:08:14.33/va/06,03,usb,yes,39,39 2006.173.04:08:14.33/va/07,04,usb,yes,32,33 2006.173.04:08:14.33/va/08,04,usb,yes,27,33 2006.173.04:08:14.56/valo/01,524.99,yes,locked 2006.173.04:08:14.56/valo/02,534.99,yes,locked 2006.173.04:08:14.56/valo/03,564.99,yes,locked 2006.173.04:08:14.56/valo/04,624.99,yes,locked 2006.173.04:08:14.56/valo/05,734.99,yes,locked 2006.173.04:08:14.56/valo/06,814.99,yes,locked 2006.173.04:08:14.56/valo/07,864.99,yes,locked 2006.173.04:08:14.56/valo/08,884.99,yes,locked 2006.173.04:08:15.65/vb/01,04,usb,yes,29,27 2006.173.04:08:15.65/vb/02,04,usb,yes,32,32 2006.173.04:08:15.65/vb/03,04,usb,yes,29,32 2006.173.04:08:15.65/vb/04,04,usb,yes,33,32 2006.173.04:08:15.65/vb/05,04,usb,yes,26,28 2006.173.04:08:15.65/vb/06,04,usb,yes,30,26 2006.173.04:08:15.65/vb/07,04,usb,yes,30,30 2006.173.04:08:15.65/vb/08,04,usb,yes,27,31 2006.173.04:08:15.88/vblo/01,629.99,yes,locked 2006.173.04:08:15.88/vblo/02,634.99,yes,locked 2006.173.04:08:15.88/vblo/03,649.99,yes,locked 2006.173.04:08:15.88/vblo/04,679.99,yes,locked 2006.173.04:08:15.88/vblo/05,709.99,yes,locked 2006.173.04:08:15.88/vblo/06,719.99,yes,locked 2006.173.04:08:15.88/vblo/07,734.99,yes,locked 2006.173.04:08:15.88/vblo/08,744.99,yes,locked 2006.173.04:08:16.03/vabw/8 2006.173.04:08:16.18/vbbw/8 2006.173.04:08:16.27/xfe/off,on,15.5 2006.173.04:08:16.64/ifatt/23,28,28,28 2006.173.04:08:17.08/fmout-gps/S +3.97E-07 2006.173.04:08:17.13:!2006.173.04:12:03 2006.173.04:12:03.01:data_valid=off 2006.173.04:12:03.01:"et 2006.173.04:12:03.01:!+3s 2006.173.04:12:06.02:"tape 2006.173.04:12:06.02:postob 2006.173.04:12:06.21/cable/+6.5097E-03 2006.173.04:12:06.21/wx/23.04,1005.9,80 2006.173.04:12:07.08/fmout-gps/S +3.96E-07 2006.173.04:12:07.08:scan_name=173-0422,jd0606,110 2006.173.04:12:07.08:source=3c274,123049.42,122328.0,2000.0,cw 2006.173.04:12:08.14#flagr#flagr/antenna,new-source 2006.173.04:12:08.14:checkk5 2006.173.04:12:08.50/chk_autoobs//k5ts1/ autoobs is running! 2006.173.04:12:08.85/chk_autoobs//k5ts2/ autoobs is running! 2006.173.04:12:09.23/chk_autoobs//k5ts3/ autoobs is running! 2006.173.04:12:09.58/chk_autoobs//k5ts4/ autoobs is running! 2006.173.04:12:09.91/chk_obsdata//k5ts1/T1730408??a.dat file size is correct (nominal:920MB, actual:916MB). 2006.173.04:12:10.26/chk_obsdata//k5ts2/T1730408??b.dat file size is correct (nominal:920MB, actual:916MB). 2006.173.04:12:10.60/chk_obsdata//k5ts3/T1730408??c.dat file size is correct (nominal:920MB, actual:916MB). 2006.173.04:12:10.95/chk_obsdata//k5ts4/T1730408??d.dat file size is correct (nominal:920MB, actual:916MB). 2006.173.04:12:11.61/k5log//k5ts1_log_newline 2006.173.04:12:12.26/k5log//k5ts2_log_newline 2006.173.04:12:12.92/k5log//k5ts3_log_newline 2006.173.04:12:13.59/k5log//k5ts4_log_newline 2006.173.04:12:13.61/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.04:12:13.61:setupk4=1 2006.173.04:12:13.61$setupk4/echo=on 2006.173.04:12:13.61$setupk4/pcalon 2006.173.04:12:13.61$pcalon/"no phase cal control is implemented here 2006.173.04:12:13.61$setupk4/"tpicd=stop 2006.173.04:12:13.61$setupk4/"rec=synch_on 2006.173.04:12:13.61$setupk4/"rec_mode=128 2006.173.04:12:13.61$setupk4/!* 2006.173.04:12:13.61$setupk4/recpk4 2006.173.04:12:13.61$recpk4/recpatch= 2006.173.04:12:13.62$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.04:12:13.62$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.04:12:13.62$setupk4/vck44 2006.173.04:12:13.62$vck44/valo=1,524.99 2006.173.04:12:13.62#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.04:12:13.62#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.04:12:13.62#ibcon#ireg 17 cls_cnt 0 2006.173.04:12:13.62#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.04:12:13.62#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.04:12:13.62#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.04:12:13.62#ibcon#enter wrdev, iclass 14, count 0 2006.173.04:12:13.62#ibcon#first serial, iclass 14, count 0 2006.173.04:12:13.62#ibcon#enter sib2, iclass 14, count 0 2006.173.04:12:13.62#ibcon#flushed, iclass 14, count 0 2006.173.04:12:13.62#ibcon#about to write, iclass 14, count 0 2006.173.04:12:13.62#ibcon#wrote, iclass 14, count 0 2006.173.04:12:13.62#ibcon#about to read 3, iclass 14, count 0 2006.173.04:12:13.64#ibcon#read 3, iclass 14, count 0 2006.173.04:12:13.64#ibcon#about to read 4, iclass 14, count 0 2006.173.04:12:13.64#ibcon#read 4, iclass 14, count 0 2006.173.04:12:13.64#ibcon#about to read 5, iclass 14, count 0 2006.173.04:12:13.64#ibcon#read 5, iclass 14, count 0 2006.173.04:12:13.64#ibcon#about to read 6, iclass 14, count 0 2006.173.04:12:13.64#ibcon#read 6, iclass 14, count 0 2006.173.04:12:13.64#ibcon#end of sib2, iclass 14, count 0 2006.173.04:12:13.64#ibcon#*mode == 0, iclass 14, count 0 2006.173.04:12:13.64#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.04:12:13.64#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.04:12:13.64#ibcon#*before write, iclass 14, count 0 2006.173.04:12:13.64#ibcon#enter sib2, iclass 14, count 0 2006.173.04:12:13.64#ibcon#flushed, iclass 14, count 0 2006.173.04:12:13.64#ibcon#about to write, iclass 14, count 0 2006.173.04:12:13.64#ibcon#wrote, iclass 14, count 0 2006.173.04:12:13.64#ibcon#about to read 3, iclass 14, count 0 2006.173.04:12:13.69#ibcon#read 3, iclass 14, count 0 2006.173.04:12:13.69#ibcon#about to read 4, iclass 14, count 0 2006.173.04:12:13.69#ibcon#read 4, iclass 14, count 0 2006.173.04:12:13.69#ibcon#about to read 5, iclass 14, count 0 2006.173.04:12:13.69#ibcon#read 5, iclass 14, count 0 2006.173.04:12:13.69#ibcon#about to read 6, iclass 14, count 0 2006.173.04:12:13.69#ibcon#read 6, iclass 14, count 0 2006.173.04:12:13.69#ibcon#end of sib2, iclass 14, count 0 2006.173.04:12:13.69#ibcon#*after write, iclass 14, count 0 2006.173.04:12:13.69#ibcon#*before return 0, iclass 14, count 0 2006.173.04:12:13.69#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.04:12:13.69#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.04:12:13.69#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.04:12:13.69#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.04:12:13.69$vck44/va=1,7 2006.173.04:12:13.69#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.04:12:13.69#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.04:12:13.69#ibcon#ireg 11 cls_cnt 2 2006.173.04:12:13.69#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.04:12:13.69#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.04:12:13.69#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.04:12:13.69#ibcon#enter wrdev, iclass 16, count 2 2006.173.04:12:13.69#ibcon#first serial, iclass 16, count 2 2006.173.04:12:13.69#ibcon#enter sib2, iclass 16, count 2 2006.173.04:12:13.69#ibcon#flushed, iclass 16, count 2 2006.173.04:12:13.69#ibcon#about to write, iclass 16, count 2 2006.173.04:12:13.69#ibcon#wrote, iclass 16, count 2 2006.173.04:12:13.69#ibcon#about to read 3, iclass 16, count 2 2006.173.04:12:13.71#ibcon#read 3, iclass 16, count 2 2006.173.04:12:13.71#ibcon#about to read 4, iclass 16, count 2 2006.173.04:12:13.71#ibcon#read 4, iclass 16, count 2 2006.173.04:12:13.71#ibcon#about to read 5, iclass 16, count 2 2006.173.04:12:13.71#ibcon#read 5, iclass 16, count 2 2006.173.04:12:13.71#ibcon#about to read 6, iclass 16, count 2 2006.173.04:12:13.71#ibcon#read 6, iclass 16, count 2 2006.173.04:12:13.71#ibcon#end of sib2, iclass 16, count 2 2006.173.04:12:13.71#ibcon#*mode == 0, iclass 16, count 2 2006.173.04:12:13.71#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.04:12:13.71#ibcon#[25=AT01-07\r\n] 2006.173.04:12:13.71#ibcon#*before write, iclass 16, count 2 2006.173.04:12:13.71#ibcon#enter sib2, iclass 16, count 2 2006.173.04:12:13.71#ibcon#flushed, iclass 16, count 2 2006.173.04:12:13.71#ibcon#about to write, iclass 16, count 2 2006.173.04:12:13.71#ibcon#wrote, iclass 16, count 2 2006.173.04:12:13.71#ibcon#about to read 3, iclass 16, count 2 2006.173.04:12:13.74#ibcon#read 3, iclass 16, count 2 2006.173.04:12:13.74#ibcon#about to read 4, iclass 16, count 2 2006.173.04:12:13.74#ibcon#read 4, iclass 16, count 2 2006.173.04:12:13.74#ibcon#about to read 5, iclass 16, count 2 2006.173.04:12:13.74#ibcon#read 5, iclass 16, count 2 2006.173.04:12:13.74#ibcon#about to read 6, iclass 16, count 2 2006.173.04:12:13.74#ibcon#read 6, iclass 16, count 2 2006.173.04:12:13.74#ibcon#end of sib2, iclass 16, count 2 2006.173.04:12:13.74#ibcon#*after write, iclass 16, count 2 2006.173.04:12:13.74#ibcon#*before return 0, iclass 16, count 2 2006.173.04:12:13.74#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.04:12:13.74#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.04:12:13.74#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.04:12:13.74#ibcon#ireg 7 cls_cnt 0 2006.173.04:12:13.74#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.04:12:13.86#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.04:12:13.86#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.04:12:13.86#ibcon#enter wrdev, iclass 16, count 0 2006.173.04:12:13.86#ibcon#first serial, iclass 16, count 0 2006.173.04:12:13.86#ibcon#enter sib2, iclass 16, count 0 2006.173.04:12:13.86#ibcon#flushed, iclass 16, count 0 2006.173.04:12:13.86#ibcon#about to write, iclass 16, count 0 2006.173.04:12:13.86#ibcon#wrote, iclass 16, count 0 2006.173.04:12:13.86#ibcon#about to read 3, iclass 16, count 0 2006.173.04:12:13.88#ibcon#read 3, iclass 16, count 0 2006.173.04:12:13.88#ibcon#about to read 4, iclass 16, count 0 2006.173.04:12:13.88#ibcon#read 4, iclass 16, count 0 2006.173.04:12:13.88#ibcon#about to read 5, iclass 16, count 0 2006.173.04:12:13.88#ibcon#read 5, iclass 16, count 0 2006.173.04:12:13.88#ibcon#about to read 6, iclass 16, count 0 2006.173.04:12:13.88#ibcon#read 6, iclass 16, count 0 2006.173.04:12:13.88#ibcon#end of sib2, iclass 16, count 0 2006.173.04:12:13.88#ibcon#*mode == 0, iclass 16, count 0 2006.173.04:12:13.88#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.04:12:13.88#ibcon#[25=USB\r\n] 2006.173.04:12:13.88#ibcon#*before write, iclass 16, count 0 2006.173.04:12:13.88#ibcon#enter sib2, iclass 16, count 0 2006.173.04:12:13.88#ibcon#flushed, iclass 16, count 0 2006.173.04:12:13.88#ibcon#about to write, iclass 16, count 0 2006.173.04:12:13.88#ibcon#wrote, iclass 16, count 0 2006.173.04:12:13.88#ibcon#about to read 3, iclass 16, count 0 2006.173.04:12:13.91#ibcon#read 3, iclass 16, count 0 2006.173.04:12:13.91#ibcon#about to read 4, iclass 16, count 0 2006.173.04:12:13.91#ibcon#read 4, iclass 16, count 0 2006.173.04:12:13.91#ibcon#about to read 5, iclass 16, count 0 2006.173.04:12:13.91#ibcon#read 5, iclass 16, count 0 2006.173.04:12:13.91#ibcon#about to read 6, iclass 16, count 0 2006.173.04:12:13.91#ibcon#read 6, iclass 16, count 0 2006.173.04:12:13.91#ibcon#end of sib2, iclass 16, count 0 2006.173.04:12:13.91#ibcon#*after write, iclass 16, count 0 2006.173.04:12:13.91#ibcon#*before return 0, iclass 16, count 0 2006.173.04:12:13.91#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.04:12:13.91#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.04:12:13.91#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.04:12:13.91#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.04:12:13.91$vck44/valo=2,534.99 2006.173.04:12:13.91#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.04:12:13.91#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.04:12:13.91#ibcon#ireg 17 cls_cnt 0 2006.173.04:12:13.91#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.04:12:13.91#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.04:12:13.91#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.04:12:13.91#ibcon#enter wrdev, iclass 18, count 0 2006.173.04:12:13.91#ibcon#first serial, iclass 18, count 0 2006.173.04:12:13.91#ibcon#enter sib2, iclass 18, count 0 2006.173.04:12:13.91#ibcon#flushed, iclass 18, count 0 2006.173.04:12:13.91#ibcon#about to write, iclass 18, count 0 2006.173.04:12:13.91#ibcon#wrote, iclass 18, count 0 2006.173.04:12:13.91#ibcon#about to read 3, iclass 18, count 0 2006.173.04:12:13.93#ibcon#read 3, iclass 18, count 0 2006.173.04:12:13.93#ibcon#about to read 4, iclass 18, count 0 2006.173.04:12:13.93#ibcon#read 4, iclass 18, count 0 2006.173.04:12:13.93#ibcon#about to read 5, iclass 18, count 0 2006.173.04:12:13.93#ibcon#read 5, iclass 18, count 0 2006.173.04:12:13.93#ibcon#about to read 6, iclass 18, count 0 2006.173.04:12:13.93#ibcon#read 6, iclass 18, count 0 2006.173.04:12:13.93#ibcon#end of sib2, iclass 18, count 0 2006.173.04:12:13.93#ibcon#*mode == 0, iclass 18, count 0 2006.173.04:12:13.93#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.04:12:13.93#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.04:12:13.93#ibcon#*before write, iclass 18, count 0 2006.173.04:12:13.93#ibcon#enter sib2, iclass 18, count 0 2006.173.04:12:13.93#ibcon#flushed, iclass 18, count 0 2006.173.04:12:13.93#ibcon#about to write, iclass 18, count 0 2006.173.04:12:13.93#ibcon#wrote, iclass 18, count 0 2006.173.04:12:13.93#ibcon#about to read 3, iclass 18, count 0 2006.173.04:12:13.97#ibcon#read 3, iclass 18, count 0 2006.173.04:12:13.97#ibcon#about to read 4, iclass 18, count 0 2006.173.04:12:13.97#ibcon#read 4, iclass 18, count 0 2006.173.04:12:13.97#ibcon#about to read 5, iclass 18, count 0 2006.173.04:12:13.97#ibcon#read 5, iclass 18, count 0 2006.173.04:12:13.97#ibcon#about to read 6, iclass 18, count 0 2006.173.04:12:13.97#ibcon#read 6, iclass 18, count 0 2006.173.04:12:13.97#ibcon#end of sib2, iclass 18, count 0 2006.173.04:12:13.97#ibcon#*after write, iclass 18, count 0 2006.173.04:12:13.97#ibcon#*before return 0, iclass 18, count 0 2006.173.04:12:13.97#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.04:12:13.97#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.04:12:13.97#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.04:12:13.97#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.04:12:13.97$vck44/va=2,6 2006.173.04:12:13.97#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.04:12:13.97#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.04:12:13.97#ibcon#ireg 11 cls_cnt 2 2006.173.04:12:13.97#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.04:12:14.03#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.04:12:14.03#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.04:12:14.03#ibcon#enter wrdev, iclass 20, count 2 2006.173.04:12:14.03#ibcon#first serial, iclass 20, count 2 2006.173.04:12:14.03#ibcon#enter sib2, iclass 20, count 2 2006.173.04:12:14.03#ibcon#flushed, iclass 20, count 2 2006.173.04:12:14.03#ibcon#about to write, iclass 20, count 2 2006.173.04:12:14.03#ibcon#wrote, iclass 20, count 2 2006.173.04:12:14.03#ibcon#about to read 3, iclass 20, count 2 2006.173.04:12:14.05#ibcon#read 3, iclass 20, count 2 2006.173.04:12:14.05#ibcon#about to read 4, iclass 20, count 2 2006.173.04:12:14.05#ibcon#read 4, iclass 20, count 2 2006.173.04:12:14.05#ibcon#about to read 5, iclass 20, count 2 2006.173.04:12:14.05#ibcon#read 5, iclass 20, count 2 2006.173.04:12:14.05#ibcon#about to read 6, iclass 20, count 2 2006.173.04:12:14.05#ibcon#read 6, iclass 20, count 2 2006.173.04:12:14.05#ibcon#end of sib2, iclass 20, count 2 2006.173.04:12:14.05#ibcon#*mode == 0, iclass 20, count 2 2006.173.04:12:14.05#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.04:12:14.05#ibcon#[25=AT02-06\r\n] 2006.173.04:12:14.05#ibcon#*before write, iclass 20, count 2 2006.173.04:12:14.05#ibcon#enter sib2, iclass 20, count 2 2006.173.04:12:14.05#ibcon#flushed, iclass 20, count 2 2006.173.04:12:14.05#ibcon#about to write, iclass 20, count 2 2006.173.04:12:14.05#ibcon#wrote, iclass 20, count 2 2006.173.04:12:14.05#ibcon#about to read 3, iclass 20, count 2 2006.173.04:12:14.08#ibcon#read 3, iclass 20, count 2 2006.173.04:12:14.08#ibcon#about to read 4, iclass 20, count 2 2006.173.04:12:14.08#ibcon#read 4, iclass 20, count 2 2006.173.04:12:14.08#ibcon#about to read 5, iclass 20, count 2 2006.173.04:12:14.08#ibcon#read 5, iclass 20, count 2 2006.173.04:12:14.08#ibcon#about to read 6, iclass 20, count 2 2006.173.04:12:14.08#ibcon#read 6, iclass 20, count 2 2006.173.04:12:14.08#ibcon#end of sib2, iclass 20, count 2 2006.173.04:12:14.08#ibcon#*after write, iclass 20, count 2 2006.173.04:12:14.08#ibcon#*before return 0, iclass 20, count 2 2006.173.04:12:14.08#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.04:12:14.08#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.04:12:14.08#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.04:12:14.08#ibcon#ireg 7 cls_cnt 0 2006.173.04:12:14.08#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.04:12:14.20#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.04:12:14.20#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.04:12:14.20#ibcon#enter wrdev, iclass 20, count 0 2006.173.04:12:14.20#ibcon#first serial, iclass 20, count 0 2006.173.04:12:14.20#ibcon#enter sib2, iclass 20, count 0 2006.173.04:12:14.20#ibcon#flushed, iclass 20, count 0 2006.173.04:12:14.20#ibcon#about to write, iclass 20, count 0 2006.173.04:12:14.20#ibcon#wrote, iclass 20, count 0 2006.173.04:12:14.20#ibcon#about to read 3, iclass 20, count 0 2006.173.04:12:14.22#ibcon#read 3, iclass 20, count 0 2006.173.04:12:14.22#ibcon#about to read 4, iclass 20, count 0 2006.173.04:12:14.22#ibcon#read 4, iclass 20, count 0 2006.173.04:12:14.22#ibcon#about to read 5, iclass 20, count 0 2006.173.04:12:14.22#ibcon#read 5, iclass 20, count 0 2006.173.04:12:14.22#ibcon#about to read 6, iclass 20, count 0 2006.173.04:12:14.22#ibcon#read 6, iclass 20, count 0 2006.173.04:12:14.22#ibcon#end of sib2, iclass 20, count 0 2006.173.04:12:14.22#ibcon#*mode == 0, iclass 20, count 0 2006.173.04:12:14.22#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.04:12:14.22#ibcon#[25=USB\r\n] 2006.173.04:12:14.22#ibcon#*before write, iclass 20, count 0 2006.173.04:12:14.22#ibcon#enter sib2, iclass 20, count 0 2006.173.04:12:14.22#ibcon#flushed, iclass 20, count 0 2006.173.04:12:14.22#ibcon#about to write, iclass 20, count 0 2006.173.04:12:14.22#ibcon#wrote, iclass 20, count 0 2006.173.04:12:14.22#ibcon#about to read 3, iclass 20, count 0 2006.173.04:12:14.25#ibcon#read 3, iclass 20, count 0 2006.173.04:12:14.25#ibcon#about to read 4, iclass 20, count 0 2006.173.04:12:14.25#ibcon#read 4, iclass 20, count 0 2006.173.04:12:14.25#ibcon#about to read 5, iclass 20, count 0 2006.173.04:12:14.25#ibcon#read 5, iclass 20, count 0 2006.173.04:12:14.25#ibcon#about to read 6, iclass 20, count 0 2006.173.04:12:14.25#ibcon#read 6, iclass 20, count 0 2006.173.04:12:14.25#ibcon#end of sib2, iclass 20, count 0 2006.173.04:12:14.25#ibcon#*after write, iclass 20, count 0 2006.173.04:12:14.25#ibcon#*before return 0, iclass 20, count 0 2006.173.04:12:14.25#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.04:12:14.25#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.04:12:14.25#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.04:12:14.25#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.04:12:14.25$vck44/valo=3,564.99 2006.173.04:12:14.25#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.04:12:14.25#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.04:12:14.25#ibcon#ireg 17 cls_cnt 0 2006.173.04:12:14.25#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.04:12:14.25#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.04:12:14.25#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.04:12:14.25#ibcon#enter wrdev, iclass 22, count 0 2006.173.04:12:14.25#ibcon#first serial, iclass 22, count 0 2006.173.04:12:14.25#ibcon#enter sib2, iclass 22, count 0 2006.173.04:12:14.25#ibcon#flushed, iclass 22, count 0 2006.173.04:12:14.25#ibcon#about to write, iclass 22, count 0 2006.173.04:12:14.25#ibcon#wrote, iclass 22, count 0 2006.173.04:12:14.25#ibcon#about to read 3, iclass 22, count 0 2006.173.04:12:14.27#ibcon#read 3, iclass 22, count 0 2006.173.04:12:14.27#ibcon#about to read 4, iclass 22, count 0 2006.173.04:12:14.27#ibcon#read 4, iclass 22, count 0 2006.173.04:12:14.27#ibcon#about to read 5, iclass 22, count 0 2006.173.04:12:14.27#ibcon#read 5, iclass 22, count 0 2006.173.04:12:14.27#ibcon#about to read 6, iclass 22, count 0 2006.173.04:12:14.27#ibcon#read 6, iclass 22, count 0 2006.173.04:12:14.27#ibcon#end of sib2, iclass 22, count 0 2006.173.04:12:14.27#ibcon#*mode == 0, iclass 22, count 0 2006.173.04:12:14.27#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.04:12:14.27#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.04:12:14.27#ibcon#*before write, iclass 22, count 0 2006.173.04:12:14.27#ibcon#enter sib2, iclass 22, count 0 2006.173.04:12:14.27#ibcon#flushed, iclass 22, count 0 2006.173.04:12:14.27#ibcon#about to write, iclass 22, count 0 2006.173.04:12:14.27#ibcon#wrote, iclass 22, count 0 2006.173.04:12:14.27#ibcon#about to read 3, iclass 22, count 0 2006.173.04:12:14.31#ibcon#read 3, iclass 22, count 0 2006.173.04:12:14.31#ibcon#about to read 4, iclass 22, count 0 2006.173.04:12:14.31#ibcon#read 4, iclass 22, count 0 2006.173.04:12:14.31#ibcon#about to read 5, iclass 22, count 0 2006.173.04:12:14.31#ibcon#read 5, iclass 22, count 0 2006.173.04:12:14.31#ibcon#about to read 6, iclass 22, count 0 2006.173.04:12:14.31#ibcon#read 6, iclass 22, count 0 2006.173.04:12:14.31#ibcon#end of sib2, iclass 22, count 0 2006.173.04:12:14.31#ibcon#*after write, iclass 22, count 0 2006.173.04:12:14.31#ibcon#*before return 0, iclass 22, count 0 2006.173.04:12:14.31#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.04:12:14.31#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.04:12:14.31#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.04:12:14.31#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.04:12:14.31$vck44/va=3,5 2006.173.04:12:14.31#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.04:12:14.31#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.04:12:14.31#ibcon#ireg 11 cls_cnt 2 2006.173.04:12:14.31#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.04:12:14.37#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.04:12:14.37#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.04:12:14.37#ibcon#enter wrdev, iclass 24, count 2 2006.173.04:12:14.37#ibcon#first serial, iclass 24, count 2 2006.173.04:12:14.37#ibcon#enter sib2, iclass 24, count 2 2006.173.04:12:14.37#ibcon#flushed, iclass 24, count 2 2006.173.04:12:14.37#ibcon#about to write, iclass 24, count 2 2006.173.04:12:14.37#ibcon#wrote, iclass 24, count 2 2006.173.04:12:14.37#ibcon#about to read 3, iclass 24, count 2 2006.173.04:12:14.39#ibcon#read 3, iclass 24, count 2 2006.173.04:12:14.39#ibcon#about to read 4, iclass 24, count 2 2006.173.04:12:14.39#ibcon#read 4, iclass 24, count 2 2006.173.04:12:14.39#ibcon#about to read 5, iclass 24, count 2 2006.173.04:12:14.39#ibcon#read 5, iclass 24, count 2 2006.173.04:12:14.39#ibcon#about to read 6, iclass 24, count 2 2006.173.04:12:14.39#ibcon#read 6, iclass 24, count 2 2006.173.04:12:14.39#ibcon#end of sib2, iclass 24, count 2 2006.173.04:12:14.39#ibcon#*mode == 0, iclass 24, count 2 2006.173.04:12:14.39#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.04:12:14.39#ibcon#[25=AT03-05\r\n] 2006.173.04:12:14.39#ibcon#*before write, iclass 24, count 2 2006.173.04:12:14.39#ibcon#enter sib2, iclass 24, count 2 2006.173.04:12:14.39#ibcon#flushed, iclass 24, count 2 2006.173.04:12:14.39#ibcon#about to write, iclass 24, count 2 2006.173.04:12:14.39#ibcon#wrote, iclass 24, count 2 2006.173.04:12:14.39#ibcon#about to read 3, iclass 24, count 2 2006.173.04:12:14.42#ibcon#read 3, iclass 24, count 2 2006.173.04:12:14.42#ibcon#about to read 4, iclass 24, count 2 2006.173.04:12:14.42#ibcon#read 4, iclass 24, count 2 2006.173.04:12:14.42#ibcon#about to read 5, iclass 24, count 2 2006.173.04:12:14.42#ibcon#read 5, iclass 24, count 2 2006.173.04:12:14.42#ibcon#about to read 6, iclass 24, count 2 2006.173.04:12:14.42#ibcon#read 6, iclass 24, count 2 2006.173.04:12:14.42#ibcon#end of sib2, iclass 24, count 2 2006.173.04:12:14.42#ibcon#*after write, iclass 24, count 2 2006.173.04:12:14.42#ibcon#*before return 0, iclass 24, count 2 2006.173.04:12:14.42#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.04:12:14.42#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.04:12:14.42#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.04:12:14.42#ibcon#ireg 7 cls_cnt 0 2006.173.04:12:14.42#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.04:12:14.53#abcon#<5=/15 1.2 2.6 23.04 801005.9\r\n> 2006.173.04:12:14.54#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.04:12:14.54#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.04:12:14.54#ibcon#enter wrdev, iclass 24, count 0 2006.173.04:12:14.54#ibcon#first serial, iclass 24, count 0 2006.173.04:12:14.54#ibcon#enter sib2, iclass 24, count 0 2006.173.04:12:14.54#ibcon#flushed, iclass 24, count 0 2006.173.04:12:14.54#ibcon#about to write, iclass 24, count 0 2006.173.04:12:14.54#ibcon#wrote, iclass 24, count 0 2006.173.04:12:14.54#ibcon#about to read 3, iclass 24, count 0 2006.173.04:12:14.55#abcon#{5=INTERFACE CLEAR} 2006.173.04:12:14.56#ibcon#read 3, iclass 24, count 0 2006.173.04:12:14.56#ibcon#about to read 4, iclass 24, count 0 2006.173.04:12:14.56#ibcon#read 4, iclass 24, count 0 2006.173.04:12:14.56#ibcon#about to read 5, iclass 24, count 0 2006.173.04:12:14.56#ibcon#read 5, iclass 24, count 0 2006.173.04:12:14.56#ibcon#about to read 6, iclass 24, count 0 2006.173.04:12:14.56#ibcon#read 6, iclass 24, count 0 2006.173.04:12:14.56#ibcon#end of sib2, iclass 24, count 0 2006.173.04:12:14.56#ibcon#*mode == 0, iclass 24, count 0 2006.173.04:12:14.56#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.04:12:14.56#ibcon#[25=USB\r\n] 2006.173.04:12:14.56#ibcon#*before write, iclass 24, count 0 2006.173.04:12:14.56#ibcon#enter sib2, iclass 24, count 0 2006.173.04:12:14.56#ibcon#flushed, iclass 24, count 0 2006.173.04:12:14.56#ibcon#about to write, iclass 24, count 0 2006.173.04:12:14.56#ibcon#wrote, iclass 24, count 0 2006.173.04:12:14.56#ibcon#about to read 3, iclass 24, count 0 2006.173.04:12:14.59#ibcon#read 3, iclass 24, count 0 2006.173.04:12:14.59#ibcon#about to read 4, iclass 24, count 0 2006.173.04:12:14.59#ibcon#read 4, iclass 24, count 0 2006.173.04:12:14.59#ibcon#about to read 5, iclass 24, count 0 2006.173.04:12:14.59#ibcon#read 5, iclass 24, count 0 2006.173.04:12:14.59#ibcon#about to read 6, iclass 24, count 0 2006.173.04:12:14.59#ibcon#read 6, iclass 24, count 0 2006.173.04:12:14.59#ibcon#end of sib2, iclass 24, count 0 2006.173.04:12:14.59#ibcon#*after write, iclass 24, count 0 2006.173.04:12:14.59#ibcon#*before return 0, iclass 24, count 0 2006.173.04:12:14.59#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.04:12:14.59#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.04:12:14.59#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.04:12:14.59#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.04:12:14.59$vck44/valo=4,624.99 2006.173.04:12:14.59#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.04:12:14.59#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.04:12:14.59#ibcon#ireg 17 cls_cnt 0 2006.173.04:12:14.59#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.04:12:14.59#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.04:12:14.59#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.04:12:14.59#ibcon#enter wrdev, iclass 29, count 0 2006.173.04:12:14.59#ibcon#first serial, iclass 29, count 0 2006.173.04:12:14.59#ibcon#enter sib2, iclass 29, count 0 2006.173.04:12:14.59#ibcon#flushed, iclass 29, count 0 2006.173.04:12:14.59#ibcon#about to write, iclass 29, count 0 2006.173.04:12:14.59#ibcon#wrote, iclass 29, count 0 2006.173.04:12:14.59#ibcon#about to read 3, iclass 29, count 0 2006.173.04:12:14.61#ibcon#read 3, iclass 29, count 0 2006.173.04:12:14.61#ibcon#about to read 4, iclass 29, count 0 2006.173.04:12:14.61#ibcon#read 4, iclass 29, count 0 2006.173.04:12:14.61#ibcon#about to read 5, iclass 29, count 0 2006.173.04:12:14.61#ibcon#read 5, iclass 29, count 0 2006.173.04:12:14.61#ibcon#about to read 6, iclass 29, count 0 2006.173.04:12:14.61#ibcon#read 6, iclass 29, count 0 2006.173.04:12:14.61#ibcon#end of sib2, iclass 29, count 0 2006.173.04:12:14.61#ibcon#*mode == 0, iclass 29, count 0 2006.173.04:12:14.61#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.04:12:14.61#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.04:12:14.61#ibcon#*before write, iclass 29, count 0 2006.173.04:12:14.61#ibcon#enter sib2, iclass 29, count 0 2006.173.04:12:14.61#ibcon#flushed, iclass 29, count 0 2006.173.04:12:14.61#ibcon#about to write, iclass 29, count 0 2006.173.04:12:14.61#ibcon#wrote, iclass 29, count 0 2006.173.04:12:14.61#ibcon#about to read 3, iclass 29, count 0 2006.173.04:12:14.61#abcon#[5=S1D000X0/0*\r\n] 2006.173.04:12:14.65#ibcon#read 3, iclass 29, count 0 2006.173.04:12:14.65#ibcon#about to read 4, iclass 29, count 0 2006.173.04:12:14.65#ibcon#read 4, iclass 29, count 0 2006.173.04:12:14.65#ibcon#about to read 5, iclass 29, count 0 2006.173.04:12:14.65#ibcon#read 5, iclass 29, count 0 2006.173.04:12:14.65#ibcon#about to read 6, iclass 29, count 0 2006.173.04:12:14.65#ibcon#read 6, iclass 29, count 0 2006.173.04:12:14.65#ibcon#end of sib2, iclass 29, count 0 2006.173.04:12:14.65#ibcon#*after write, iclass 29, count 0 2006.173.04:12:14.65#ibcon#*before return 0, iclass 29, count 0 2006.173.04:12:14.65#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.04:12:14.65#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.04:12:14.65#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.04:12:14.65#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.04:12:14.65$vck44/va=4,6 2006.173.04:12:14.65#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.173.04:12:14.65#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.173.04:12:14.65#ibcon#ireg 11 cls_cnt 2 2006.173.04:12:14.65#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.04:12:14.71#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.04:12:14.71#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.04:12:14.71#ibcon#enter wrdev, iclass 32, count 2 2006.173.04:12:14.71#ibcon#first serial, iclass 32, count 2 2006.173.04:12:14.71#ibcon#enter sib2, iclass 32, count 2 2006.173.04:12:14.71#ibcon#flushed, iclass 32, count 2 2006.173.04:12:14.71#ibcon#about to write, iclass 32, count 2 2006.173.04:12:14.71#ibcon#wrote, iclass 32, count 2 2006.173.04:12:14.71#ibcon#about to read 3, iclass 32, count 2 2006.173.04:12:14.73#ibcon#read 3, iclass 32, count 2 2006.173.04:12:14.73#ibcon#about to read 4, iclass 32, count 2 2006.173.04:12:14.73#ibcon#read 4, iclass 32, count 2 2006.173.04:12:14.73#ibcon#about to read 5, iclass 32, count 2 2006.173.04:12:14.73#ibcon#read 5, iclass 32, count 2 2006.173.04:12:14.73#ibcon#about to read 6, iclass 32, count 2 2006.173.04:12:14.73#ibcon#read 6, iclass 32, count 2 2006.173.04:12:14.73#ibcon#end of sib2, iclass 32, count 2 2006.173.04:12:14.73#ibcon#*mode == 0, iclass 32, count 2 2006.173.04:12:14.73#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.173.04:12:14.73#ibcon#[25=AT04-06\r\n] 2006.173.04:12:14.73#ibcon#*before write, iclass 32, count 2 2006.173.04:12:14.73#ibcon#enter sib2, iclass 32, count 2 2006.173.04:12:14.73#ibcon#flushed, iclass 32, count 2 2006.173.04:12:14.73#ibcon#about to write, iclass 32, count 2 2006.173.04:12:14.73#ibcon#wrote, iclass 32, count 2 2006.173.04:12:14.73#ibcon#about to read 3, iclass 32, count 2 2006.173.04:12:14.76#ibcon#read 3, iclass 32, count 2 2006.173.04:12:14.76#ibcon#about to read 4, iclass 32, count 2 2006.173.04:12:14.76#ibcon#read 4, iclass 32, count 2 2006.173.04:12:14.76#ibcon#about to read 5, iclass 32, count 2 2006.173.04:12:14.76#ibcon#read 5, iclass 32, count 2 2006.173.04:12:14.76#ibcon#about to read 6, iclass 32, count 2 2006.173.04:12:14.76#ibcon#read 6, iclass 32, count 2 2006.173.04:12:14.76#ibcon#end of sib2, iclass 32, count 2 2006.173.04:12:14.76#ibcon#*after write, iclass 32, count 2 2006.173.04:12:14.76#ibcon#*before return 0, iclass 32, count 2 2006.173.04:12:14.76#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.04:12:14.76#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.173.04:12:14.76#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.173.04:12:14.76#ibcon#ireg 7 cls_cnt 0 2006.173.04:12:14.76#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.04:12:14.88#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.04:12:14.88#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.04:12:14.88#ibcon#enter wrdev, iclass 32, count 0 2006.173.04:12:14.88#ibcon#first serial, iclass 32, count 0 2006.173.04:12:14.88#ibcon#enter sib2, iclass 32, count 0 2006.173.04:12:14.88#ibcon#flushed, iclass 32, count 0 2006.173.04:12:14.88#ibcon#about to write, iclass 32, count 0 2006.173.04:12:14.88#ibcon#wrote, iclass 32, count 0 2006.173.04:12:14.88#ibcon#about to read 3, iclass 32, count 0 2006.173.04:12:14.90#ibcon#read 3, iclass 32, count 0 2006.173.04:12:14.90#ibcon#about to read 4, iclass 32, count 0 2006.173.04:12:14.90#ibcon#read 4, iclass 32, count 0 2006.173.04:12:14.90#ibcon#about to read 5, iclass 32, count 0 2006.173.04:12:14.90#ibcon#read 5, iclass 32, count 0 2006.173.04:12:14.90#ibcon#about to read 6, iclass 32, count 0 2006.173.04:12:14.90#ibcon#read 6, iclass 32, count 0 2006.173.04:12:14.90#ibcon#end of sib2, iclass 32, count 0 2006.173.04:12:14.90#ibcon#*mode == 0, iclass 32, count 0 2006.173.04:12:14.90#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.04:12:14.90#ibcon#[25=USB\r\n] 2006.173.04:12:14.90#ibcon#*before write, iclass 32, count 0 2006.173.04:12:14.90#ibcon#enter sib2, iclass 32, count 0 2006.173.04:12:14.90#ibcon#flushed, iclass 32, count 0 2006.173.04:12:14.90#ibcon#about to write, iclass 32, count 0 2006.173.04:12:14.90#ibcon#wrote, iclass 32, count 0 2006.173.04:12:14.90#ibcon#about to read 3, iclass 32, count 0 2006.173.04:12:14.93#ibcon#read 3, iclass 32, count 0 2006.173.04:12:14.93#ibcon#about to read 4, iclass 32, count 0 2006.173.04:12:14.93#ibcon#read 4, iclass 32, count 0 2006.173.04:12:14.93#ibcon#about to read 5, iclass 32, count 0 2006.173.04:12:14.93#ibcon#read 5, iclass 32, count 0 2006.173.04:12:14.93#ibcon#about to read 6, iclass 32, count 0 2006.173.04:12:14.93#ibcon#read 6, iclass 32, count 0 2006.173.04:12:14.93#ibcon#end of sib2, iclass 32, count 0 2006.173.04:12:14.93#ibcon#*after write, iclass 32, count 0 2006.173.04:12:14.93#ibcon#*before return 0, iclass 32, count 0 2006.173.04:12:14.93#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.04:12:14.93#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.173.04:12:14.93#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.04:12:14.93#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.04:12:14.93$vck44/valo=5,734.99 2006.173.04:12:14.93#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.04:12:14.93#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.04:12:14.93#ibcon#ireg 17 cls_cnt 0 2006.173.04:12:14.93#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.04:12:14.93#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.04:12:14.93#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.04:12:14.93#ibcon#enter wrdev, iclass 34, count 0 2006.173.04:12:14.93#ibcon#first serial, iclass 34, count 0 2006.173.04:12:14.93#ibcon#enter sib2, iclass 34, count 0 2006.173.04:12:14.93#ibcon#flushed, iclass 34, count 0 2006.173.04:12:14.93#ibcon#about to write, iclass 34, count 0 2006.173.04:12:14.93#ibcon#wrote, iclass 34, count 0 2006.173.04:12:14.93#ibcon#about to read 3, iclass 34, count 0 2006.173.04:12:14.95#ibcon#read 3, iclass 34, count 0 2006.173.04:12:14.95#ibcon#about to read 4, iclass 34, count 0 2006.173.04:12:14.95#ibcon#read 4, iclass 34, count 0 2006.173.04:12:14.95#ibcon#about to read 5, iclass 34, count 0 2006.173.04:12:14.95#ibcon#read 5, iclass 34, count 0 2006.173.04:12:14.95#ibcon#about to read 6, iclass 34, count 0 2006.173.04:12:14.95#ibcon#read 6, iclass 34, count 0 2006.173.04:12:14.95#ibcon#end of sib2, iclass 34, count 0 2006.173.04:12:14.95#ibcon#*mode == 0, iclass 34, count 0 2006.173.04:12:14.95#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.04:12:14.95#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.04:12:14.95#ibcon#*before write, iclass 34, count 0 2006.173.04:12:14.95#ibcon#enter sib2, iclass 34, count 0 2006.173.04:12:14.95#ibcon#flushed, iclass 34, count 0 2006.173.04:12:14.95#ibcon#about to write, iclass 34, count 0 2006.173.04:12:14.95#ibcon#wrote, iclass 34, count 0 2006.173.04:12:14.95#ibcon#about to read 3, iclass 34, count 0 2006.173.04:12:14.99#ibcon#read 3, iclass 34, count 0 2006.173.04:12:14.99#ibcon#about to read 4, iclass 34, count 0 2006.173.04:12:14.99#ibcon#read 4, iclass 34, count 0 2006.173.04:12:14.99#ibcon#about to read 5, iclass 34, count 0 2006.173.04:12:14.99#ibcon#read 5, iclass 34, count 0 2006.173.04:12:14.99#ibcon#about to read 6, iclass 34, count 0 2006.173.04:12:14.99#ibcon#read 6, iclass 34, count 0 2006.173.04:12:14.99#ibcon#end of sib2, iclass 34, count 0 2006.173.04:12:14.99#ibcon#*after write, iclass 34, count 0 2006.173.04:12:14.99#ibcon#*before return 0, iclass 34, count 0 2006.173.04:12:14.99#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.04:12:14.99#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.04:12:14.99#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.04:12:14.99#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.04:12:14.99$vck44/va=5,4 2006.173.04:12:14.99#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.04:12:14.99#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.04:12:14.99#ibcon#ireg 11 cls_cnt 2 2006.173.04:12:14.99#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.04:12:15.05#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.04:12:15.05#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.04:12:15.05#ibcon#enter wrdev, iclass 36, count 2 2006.173.04:12:15.05#ibcon#first serial, iclass 36, count 2 2006.173.04:12:15.05#ibcon#enter sib2, iclass 36, count 2 2006.173.04:12:15.05#ibcon#flushed, iclass 36, count 2 2006.173.04:12:15.05#ibcon#about to write, iclass 36, count 2 2006.173.04:12:15.05#ibcon#wrote, iclass 36, count 2 2006.173.04:12:15.05#ibcon#about to read 3, iclass 36, count 2 2006.173.04:12:15.07#ibcon#read 3, iclass 36, count 2 2006.173.04:12:15.07#ibcon#about to read 4, iclass 36, count 2 2006.173.04:12:15.07#ibcon#read 4, iclass 36, count 2 2006.173.04:12:15.07#ibcon#about to read 5, iclass 36, count 2 2006.173.04:12:15.07#ibcon#read 5, iclass 36, count 2 2006.173.04:12:15.07#ibcon#about to read 6, iclass 36, count 2 2006.173.04:12:15.07#ibcon#read 6, iclass 36, count 2 2006.173.04:12:15.07#ibcon#end of sib2, iclass 36, count 2 2006.173.04:12:15.07#ibcon#*mode == 0, iclass 36, count 2 2006.173.04:12:15.07#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.04:12:15.07#ibcon#[25=AT05-04\r\n] 2006.173.04:12:15.07#ibcon#*before write, iclass 36, count 2 2006.173.04:12:15.07#ibcon#enter sib2, iclass 36, count 2 2006.173.04:12:15.07#ibcon#flushed, iclass 36, count 2 2006.173.04:12:15.07#ibcon#about to write, iclass 36, count 2 2006.173.04:12:15.07#ibcon#wrote, iclass 36, count 2 2006.173.04:12:15.07#ibcon#about to read 3, iclass 36, count 2 2006.173.04:12:15.10#ibcon#read 3, iclass 36, count 2 2006.173.04:12:15.10#ibcon#about to read 4, iclass 36, count 2 2006.173.04:12:15.10#ibcon#read 4, iclass 36, count 2 2006.173.04:12:15.10#ibcon#about to read 5, iclass 36, count 2 2006.173.04:12:15.10#ibcon#read 5, iclass 36, count 2 2006.173.04:12:15.10#ibcon#about to read 6, iclass 36, count 2 2006.173.04:12:15.10#ibcon#read 6, iclass 36, count 2 2006.173.04:12:15.10#ibcon#end of sib2, iclass 36, count 2 2006.173.04:12:15.10#ibcon#*after write, iclass 36, count 2 2006.173.04:12:15.10#ibcon#*before return 0, iclass 36, count 2 2006.173.04:12:15.10#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.04:12:15.10#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.04:12:15.10#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.04:12:15.10#ibcon#ireg 7 cls_cnt 0 2006.173.04:12:15.10#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.04:12:15.22#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.04:12:15.22#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.04:12:15.22#ibcon#enter wrdev, iclass 36, count 0 2006.173.04:12:15.22#ibcon#first serial, iclass 36, count 0 2006.173.04:12:15.22#ibcon#enter sib2, iclass 36, count 0 2006.173.04:12:15.22#ibcon#flushed, iclass 36, count 0 2006.173.04:12:15.22#ibcon#about to write, iclass 36, count 0 2006.173.04:12:15.22#ibcon#wrote, iclass 36, count 0 2006.173.04:12:15.22#ibcon#about to read 3, iclass 36, count 0 2006.173.04:12:15.24#ibcon#read 3, iclass 36, count 0 2006.173.04:12:15.24#ibcon#about to read 4, iclass 36, count 0 2006.173.04:12:15.24#ibcon#read 4, iclass 36, count 0 2006.173.04:12:15.24#ibcon#about to read 5, iclass 36, count 0 2006.173.04:12:15.24#ibcon#read 5, iclass 36, count 0 2006.173.04:12:15.24#ibcon#about to read 6, iclass 36, count 0 2006.173.04:12:15.24#ibcon#read 6, iclass 36, count 0 2006.173.04:12:15.24#ibcon#end of sib2, iclass 36, count 0 2006.173.04:12:15.24#ibcon#*mode == 0, iclass 36, count 0 2006.173.04:12:15.24#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.04:12:15.24#ibcon#[25=USB\r\n] 2006.173.04:12:15.24#ibcon#*before write, iclass 36, count 0 2006.173.04:12:15.24#ibcon#enter sib2, iclass 36, count 0 2006.173.04:12:15.24#ibcon#flushed, iclass 36, count 0 2006.173.04:12:15.24#ibcon#about to write, iclass 36, count 0 2006.173.04:12:15.24#ibcon#wrote, iclass 36, count 0 2006.173.04:12:15.24#ibcon#about to read 3, iclass 36, count 0 2006.173.04:12:15.27#ibcon#read 3, iclass 36, count 0 2006.173.04:12:15.27#ibcon#about to read 4, iclass 36, count 0 2006.173.04:12:15.27#ibcon#read 4, iclass 36, count 0 2006.173.04:12:15.27#ibcon#about to read 5, iclass 36, count 0 2006.173.04:12:15.27#ibcon#read 5, iclass 36, count 0 2006.173.04:12:15.27#ibcon#about to read 6, iclass 36, count 0 2006.173.04:12:15.27#ibcon#read 6, iclass 36, count 0 2006.173.04:12:15.27#ibcon#end of sib2, iclass 36, count 0 2006.173.04:12:15.27#ibcon#*after write, iclass 36, count 0 2006.173.04:12:15.27#ibcon#*before return 0, iclass 36, count 0 2006.173.04:12:15.27#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.04:12:15.27#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.04:12:15.27#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.04:12:15.27#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.04:12:15.27$vck44/valo=6,814.99 2006.173.04:12:15.27#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.04:12:15.27#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.04:12:15.27#ibcon#ireg 17 cls_cnt 0 2006.173.04:12:15.27#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.04:12:15.27#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.04:12:15.27#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.04:12:15.27#ibcon#enter wrdev, iclass 38, count 0 2006.173.04:12:15.27#ibcon#first serial, iclass 38, count 0 2006.173.04:12:15.27#ibcon#enter sib2, iclass 38, count 0 2006.173.04:12:15.27#ibcon#flushed, iclass 38, count 0 2006.173.04:12:15.27#ibcon#about to write, iclass 38, count 0 2006.173.04:12:15.27#ibcon#wrote, iclass 38, count 0 2006.173.04:12:15.27#ibcon#about to read 3, iclass 38, count 0 2006.173.04:12:15.29#ibcon#read 3, iclass 38, count 0 2006.173.04:12:15.29#ibcon#about to read 4, iclass 38, count 0 2006.173.04:12:15.29#ibcon#read 4, iclass 38, count 0 2006.173.04:12:15.29#ibcon#about to read 5, iclass 38, count 0 2006.173.04:12:15.29#ibcon#read 5, iclass 38, count 0 2006.173.04:12:15.29#ibcon#about to read 6, iclass 38, count 0 2006.173.04:12:15.29#ibcon#read 6, iclass 38, count 0 2006.173.04:12:15.29#ibcon#end of sib2, iclass 38, count 0 2006.173.04:12:15.29#ibcon#*mode == 0, iclass 38, count 0 2006.173.04:12:15.29#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.04:12:15.29#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.04:12:15.29#ibcon#*before write, iclass 38, count 0 2006.173.04:12:15.29#ibcon#enter sib2, iclass 38, count 0 2006.173.04:12:15.29#ibcon#flushed, iclass 38, count 0 2006.173.04:12:15.29#ibcon#about to write, iclass 38, count 0 2006.173.04:12:15.29#ibcon#wrote, iclass 38, count 0 2006.173.04:12:15.29#ibcon#about to read 3, iclass 38, count 0 2006.173.04:12:15.33#ibcon#read 3, iclass 38, count 0 2006.173.04:12:15.33#ibcon#about to read 4, iclass 38, count 0 2006.173.04:12:15.33#ibcon#read 4, iclass 38, count 0 2006.173.04:12:15.33#ibcon#about to read 5, iclass 38, count 0 2006.173.04:12:15.33#ibcon#read 5, iclass 38, count 0 2006.173.04:12:15.33#ibcon#about to read 6, iclass 38, count 0 2006.173.04:12:15.33#ibcon#read 6, iclass 38, count 0 2006.173.04:12:15.33#ibcon#end of sib2, iclass 38, count 0 2006.173.04:12:15.33#ibcon#*after write, iclass 38, count 0 2006.173.04:12:15.33#ibcon#*before return 0, iclass 38, count 0 2006.173.04:12:15.33#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.04:12:15.33#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.04:12:15.33#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.04:12:15.33#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.04:12:15.33$vck44/va=6,3 2006.173.04:12:15.33#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.04:12:15.33#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.04:12:15.33#ibcon#ireg 11 cls_cnt 2 2006.173.04:12:15.33#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.04:12:15.39#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.04:12:15.39#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.04:12:15.39#ibcon#enter wrdev, iclass 40, count 2 2006.173.04:12:15.39#ibcon#first serial, iclass 40, count 2 2006.173.04:12:15.39#ibcon#enter sib2, iclass 40, count 2 2006.173.04:12:15.39#ibcon#flushed, iclass 40, count 2 2006.173.04:12:15.39#ibcon#about to write, iclass 40, count 2 2006.173.04:12:15.39#ibcon#wrote, iclass 40, count 2 2006.173.04:12:15.39#ibcon#about to read 3, iclass 40, count 2 2006.173.04:12:15.41#ibcon#read 3, iclass 40, count 2 2006.173.04:12:15.41#ibcon#about to read 4, iclass 40, count 2 2006.173.04:12:15.41#ibcon#read 4, iclass 40, count 2 2006.173.04:12:15.41#ibcon#about to read 5, iclass 40, count 2 2006.173.04:12:15.41#ibcon#read 5, iclass 40, count 2 2006.173.04:12:15.41#ibcon#about to read 6, iclass 40, count 2 2006.173.04:12:15.41#ibcon#read 6, iclass 40, count 2 2006.173.04:12:15.41#ibcon#end of sib2, iclass 40, count 2 2006.173.04:12:15.41#ibcon#*mode == 0, iclass 40, count 2 2006.173.04:12:15.41#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.04:12:15.41#ibcon#[25=AT06-03\r\n] 2006.173.04:12:15.41#ibcon#*before write, iclass 40, count 2 2006.173.04:12:15.41#ibcon#enter sib2, iclass 40, count 2 2006.173.04:12:15.41#ibcon#flushed, iclass 40, count 2 2006.173.04:12:15.41#ibcon#about to write, iclass 40, count 2 2006.173.04:12:15.41#ibcon#wrote, iclass 40, count 2 2006.173.04:12:15.41#ibcon#about to read 3, iclass 40, count 2 2006.173.04:12:15.44#ibcon#read 3, iclass 40, count 2 2006.173.04:12:15.44#ibcon#about to read 4, iclass 40, count 2 2006.173.04:12:15.44#ibcon#read 4, iclass 40, count 2 2006.173.04:12:15.44#ibcon#about to read 5, iclass 40, count 2 2006.173.04:12:15.44#ibcon#read 5, iclass 40, count 2 2006.173.04:12:15.44#ibcon#about to read 6, iclass 40, count 2 2006.173.04:12:15.44#ibcon#read 6, iclass 40, count 2 2006.173.04:12:15.44#ibcon#end of sib2, iclass 40, count 2 2006.173.04:12:15.44#ibcon#*after write, iclass 40, count 2 2006.173.04:12:15.44#ibcon#*before return 0, iclass 40, count 2 2006.173.04:12:15.44#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.04:12:15.44#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.04:12:15.44#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.04:12:15.44#ibcon#ireg 7 cls_cnt 0 2006.173.04:12:15.44#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.04:12:15.56#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.04:12:15.56#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.04:12:15.56#ibcon#enter wrdev, iclass 40, count 0 2006.173.04:12:15.56#ibcon#first serial, iclass 40, count 0 2006.173.04:12:15.56#ibcon#enter sib2, iclass 40, count 0 2006.173.04:12:15.56#ibcon#flushed, iclass 40, count 0 2006.173.04:12:15.56#ibcon#about to write, iclass 40, count 0 2006.173.04:12:15.56#ibcon#wrote, iclass 40, count 0 2006.173.04:12:15.56#ibcon#about to read 3, iclass 40, count 0 2006.173.04:12:15.58#ibcon#read 3, iclass 40, count 0 2006.173.04:12:15.58#ibcon#about to read 4, iclass 40, count 0 2006.173.04:12:15.58#ibcon#read 4, iclass 40, count 0 2006.173.04:12:15.58#ibcon#about to read 5, iclass 40, count 0 2006.173.04:12:15.58#ibcon#read 5, iclass 40, count 0 2006.173.04:12:15.58#ibcon#about to read 6, iclass 40, count 0 2006.173.04:12:15.58#ibcon#read 6, iclass 40, count 0 2006.173.04:12:15.58#ibcon#end of sib2, iclass 40, count 0 2006.173.04:12:15.58#ibcon#*mode == 0, iclass 40, count 0 2006.173.04:12:15.58#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.04:12:15.58#ibcon#[25=USB\r\n] 2006.173.04:12:15.58#ibcon#*before write, iclass 40, count 0 2006.173.04:12:15.58#ibcon#enter sib2, iclass 40, count 0 2006.173.04:12:15.58#ibcon#flushed, iclass 40, count 0 2006.173.04:12:15.58#ibcon#about to write, iclass 40, count 0 2006.173.04:12:15.58#ibcon#wrote, iclass 40, count 0 2006.173.04:12:15.58#ibcon#about to read 3, iclass 40, count 0 2006.173.04:12:15.61#ibcon#read 3, iclass 40, count 0 2006.173.04:12:15.61#ibcon#about to read 4, iclass 40, count 0 2006.173.04:12:15.61#ibcon#read 4, iclass 40, count 0 2006.173.04:12:15.61#ibcon#about to read 5, iclass 40, count 0 2006.173.04:12:15.61#ibcon#read 5, iclass 40, count 0 2006.173.04:12:15.61#ibcon#about to read 6, iclass 40, count 0 2006.173.04:12:15.61#ibcon#read 6, iclass 40, count 0 2006.173.04:12:15.61#ibcon#end of sib2, iclass 40, count 0 2006.173.04:12:15.61#ibcon#*after write, iclass 40, count 0 2006.173.04:12:15.61#ibcon#*before return 0, iclass 40, count 0 2006.173.04:12:15.61#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.04:12:15.61#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.04:12:15.61#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.04:12:15.61#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.04:12:15.61$vck44/valo=7,864.99 2006.173.04:12:15.61#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.04:12:15.61#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.04:12:15.61#ibcon#ireg 17 cls_cnt 0 2006.173.04:12:15.61#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.04:12:15.61#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.04:12:15.61#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.04:12:15.61#ibcon#enter wrdev, iclass 4, count 0 2006.173.04:12:15.61#ibcon#first serial, iclass 4, count 0 2006.173.04:12:15.61#ibcon#enter sib2, iclass 4, count 0 2006.173.04:12:15.61#ibcon#flushed, iclass 4, count 0 2006.173.04:12:15.61#ibcon#about to write, iclass 4, count 0 2006.173.04:12:15.61#ibcon#wrote, iclass 4, count 0 2006.173.04:12:15.61#ibcon#about to read 3, iclass 4, count 0 2006.173.04:12:15.63#ibcon#read 3, iclass 4, count 0 2006.173.04:12:15.63#ibcon#about to read 4, iclass 4, count 0 2006.173.04:12:15.63#ibcon#read 4, iclass 4, count 0 2006.173.04:12:15.63#ibcon#about to read 5, iclass 4, count 0 2006.173.04:12:15.63#ibcon#read 5, iclass 4, count 0 2006.173.04:12:15.63#ibcon#about to read 6, iclass 4, count 0 2006.173.04:12:15.63#ibcon#read 6, iclass 4, count 0 2006.173.04:12:15.63#ibcon#end of sib2, iclass 4, count 0 2006.173.04:12:15.63#ibcon#*mode == 0, iclass 4, count 0 2006.173.04:12:15.63#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.04:12:15.63#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.04:12:15.63#ibcon#*before write, iclass 4, count 0 2006.173.04:12:15.63#ibcon#enter sib2, iclass 4, count 0 2006.173.04:12:15.63#ibcon#flushed, iclass 4, count 0 2006.173.04:12:15.63#ibcon#about to write, iclass 4, count 0 2006.173.04:12:15.63#ibcon#wrote, iclass 4, count 0 2006.173.04:12:15.63#ibcon#about to read 3, iclass 4, count 0 2006.173.04:12:15.67#ibcon#read 3, iclass 4, count 0 2006.173.04:12:15.67#ibcon#about to read 4, iclass 4, count 0 2006.173.04:12:15.67#ibcon#read 4, iclass 4, count 0 2006.173.04:12:15.67#ibcon#about to read 5, iclass 4, count 0 2006.173.04:12:15.67#ibcon#read 5, iclass 4, count 0 2006.173.04:12:15.67#ibcon#about to read 6, iclass 4, count 0 2006.173.04:12:15.67#ibcon#read 6, iclass 4, count 0 2006.173.04:12:15.67#ibcon#end of sib2, iclass 4, count 0 2006.173.04:12:15.67#ibcon#*after write, iclass 4, count 0 2006.173.04:12:15.67#ibcon#*before return 0, iclass 4, count 0 2006.173.04:12:15.67#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.04:12:15.67#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.04:12:15.67#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.04:12:15.67#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.04:12:15.67$vck44/va=7,4 2006.173.04:12:15.67#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.04:12:15.67#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.04:12:15.67#ibcon#ireg 11 cls_cnt 2 2006.173.04:12:15.67#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.04:12:15.73#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.04:12:15.73#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.04:12:15.73#ibcon#enter wrdev, iclass 6, count 2 2006.173.04:12:15.73#ibcon#first serial, iclass 6, count 2 2006.173.04:12:15.73#ibcon#enter sib2, iclass 6, count 2 2006.173.04:12:15.73#ibcon#flushed, iclass 6, count 2 2006.173.04:12:15.73#ibcon#about to write, iclass 6, count 2 2006.173.04:12:15.73#ibcon#wrote, iclass 6, count 2 2006.173.04:12:15.73#ibcon#about to read 3, iclass 6, count 2 2006.173.04:12:15.75#ibcon#read 3, iclass 6, count 2 2006.173.04:12:15.75#ibcon#about to read 4, iclass 6, count 2 2006.173.04:12:15.75#ibcon#read 4, iclass 6, count 2 2006.173.04:12:15.75#ibcon#about to read 5, iclass 6, count 2 2006.173.04:12:15.75#ibcon#read 5, iclass 6, count 2 2006.173.04:12:15.75#ibcon#about to read 6, iclass 6, count 2 2006.173.04:12:15.75#ibcon#read 6, iclass 6, count 2 2006.173.04:12:15.75#ibcon#end of sib2, iclass 6, count 2 2006.173.04:12:15.75#ibcon#*mode == 0, iclass 6, count 2 2006.173.04:12:15.75#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.04:12:15.75#ibcon#[25=AT07-04\r\n] 2006.173.04:12:15.75#ibcon#*before write, iclass 6, count 2 2006.173.04:12:15.75#ibcon#enter sib2, iclass 6, count 2 2006.173.04:12:15.75#ibcon#flushed, iclass 6, count 2 2006.173.04:12:15.75#ibcon#about to write, iclass 6, count 2 2006.173.04:12:15.75#ibcon#wrote, iclass 6, count 2 2006.173.04:12:15.75#ibcon#about to read 3, iclass 6, count 2 2006.173.04:12:15.78#ibcon#read 3, iclass 6, count 2 2006.173.04:12:15.78#ibcon#about to read 4, iclass 6, count 2 2006.173.04:12:15.78#ibcon#read 4, iclass 6, count 2 2006.173.04:12:15.78#ibcon#about to read 5, iclass 6, count 2 2006.173.04:12:15.78#ibcon#read 5, iclass 6, count 2 2006.173.04:12:15.78#ibcon#about to read 6, iclass 6, count 2 2006.173.04:12:15.78#ibcon#read 6, iclass 6, count 2 2006.173.04:12:15.78#ibcon#end of sib2, iclass 6, count 2 2006.173.04:12:15.78#ibcon#*after write, iclass 6, count 2 2006.173.04:12:15.78#ibcon#*before return 0, iclass 6, count 2 2006.173.04:12:15.78#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.04:12:15.78#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.04:12:15.78#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.04:12:15.78#ibcon#ireg 7 cls_cnt 0 2006.173.04:12:15.78#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.04:12:15.90#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.04:12:15.90#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.04:12:15.90#ibcon#enter wrdev, iclass 6, count 0 2006.173.04:12:15.90#ibcon#first serial, iclass 6, count 0 2006.173.04:12:15.90#ibcon#enter sib2, iclass 6, count 0 2006.173.04:12:15.90#ibcon#flushed, iclass 6, count 0 2006.173.04:12:15.90#ibcon#about to write, iclass 6, count 0 2006.173.04:12:15.90#ibcon#wrote, iclass 6, count 0 2006.173.04:12:15.90#ibcon#about to read 3, iclass 6, count 0 2006.173.04:12:15.92#ibcon#read 3, iclass 6, count 0 2006.173.04:12:15.92#ibcon#about to read 4, iclass 6, count 0 2006.173.04:12:15.92#ibcon#read 4, iclass 6, count 0 2006.173.04:12:15.92#ibcon#about to read 5, iclass 6, count 0 2006.173.04:12:15.92#ibcon#read 5, iclass 6, count 0 2006.173.04:12:15.92#ibcon#about to read 6, iclass 6, count 0 2006.173.04:12:15.92#ibcon#read 6, iclass 6, count 0 2006.173.04:12:15.92#ibcon#end of sib2, iclass 6, count 0 2006.173.04:12:15.92#ibcon#*mode == 0, iclass 6, count 0 2006.173.04:12:15.92#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.04:12:15.92#ibcon#[25=USB\r\n] 2006.173.04:12:15.92#ibcon#*before write, iclass 6, count 0 2006.173.04:12:15.92#ibcon#enter sib2, iclass 6, count 0 2006.173.04:12:15.92#ibcon#flushed, iclass 6, count 0 2006.173.04:12:15.92#ibcon#about to write, iclass 6, count 0 2006.173.04:12:15.92#ibcon#wrote, iclass 6, count 0 2006.173.04:12:15.92#ibcon#about to read 3, iclass 6, count 0 2006.173.04:12:15.95#ibcon#read 3, iclass 6, count 0 2006.173.04:12:15.95#ibcon#about to read 4, iclass 6, count 0 2006.173.04:12:15.95#ibcon#read 4, iclass 6, count 0 2006.173.04:12:15.95#ibcon#about to read 5, iclass 6, count 0 2006.173.04:12:15.95#ibcon#read 5, iclass 6, count 0 2006.173.04:12:15.95#ibcon#about to read 6, iclass 6, count 0 2006.173.04:12:15.95#ibcon#read 6, iclass 6, count 0 2006.173.04:12:15.95#ibcon#end of sib2, iclass 6, count 0 2006.173.04:12:15.95#ibcon#*after write, iclass 6, count 0 2006.173.04:12:15.95#ibcon#*before return 0, iclass 6, count 0 2006.173.04:12:15.95#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.04:12:15.95#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.04:12:15.95#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.04:12:15.95#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.04:12:15.95$vck44/valo=8,884.99 2006.173.04:12:15.95#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.04:12:15.95#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.04:12:15.95#ibcon#ireg 17 cls_cnt 0 2006.173.04:12:15.95#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.04:12:15.95#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.04:12:15.95#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.04:12:15.95#ibcon#enter wrdev, iclass 10, count 0 2006.173.04:12:15.95#ibcon#first serial, iclass 10, count 0 2006.173.04:12:15.95#ibcon#enter sib2, iclass 10, count 0 2006.173.04:12:15.95#ibcon#flushed, iclass 10, count 0 2006.173.04:12:15.95#ibcon#about to write, iclass 10, count 0 2006.173.04:12:15.95#ibcon#wrote, iclass 10, count 0 2006.173.04:12:15.95#ibcon#about to read 3, iclass 10, count 0 2006.173.04:12:15.97#ibcon#read 3, iclass 10, count 0 2006.173.04:12:15.97#ibcon#about to read 4, iclass 10, count 0 2006.173.04:12:15.97#ibcon#read 4, iclass 10, count 0 2006.173.04:12:15.97#ibcon#about to read 5, iclass 10, count 0 2006.173.04:12:15.97#ibcon#read 5, iclass 10, count 0 2006.173.04:12:15.97#ibcon#about to read 6, iclass 10, count 0 2006.173.04:12:15.97#ibcon#read 6, iclass 10, count 0 2006.173.04:12:15.97#ibcon#end of sib2, iclass 10, count 0 2006.173.04:12:15.97#ibcon#*mode == 0, iclass 10, count 0 2006.173.04:12:15.97#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.04:12:15.97#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.04:12:15.97#ibcon#*before write, iclass 10, count 0 2006.173.04:12:15.97#ibcon#enter sib2, iclass 10, count 0 2006.173.04:12:15.97#ibcon#flushed, iclass 10, count 0 2006.173.04:12:15.97#ibcon#about to write, iclass 10, count 0 2006.173.04:12:15.97#ibcon#wrote, iclass 10, count 0 2006.173.04:12:15.97#ibcon#about to read 3, iclass 10, count 0 2006.173.04:12:16.01#ibcon#read 3, iclass 10, count 0 2006.173.04:12:16.01#ibcon#about to read 4, iclass 10, count 0 2006.173.04:12:16.01#ibcon#read 4, iclass 10, count 0 2006.173.04:12:16.01#ibcon#about to read 5, iclass 10, count 0 2006.173.04:12:16.01#ibcon#read 5, iclass 10, count 0 2006.173.04:12:16.01#ibcon#about to read 6, iclass 10, count 0 2006.173.04:12:16.01#ibcon#read 6, iclass 10, count 0 2006.173.04:12:16.01#ibcon#end of sib2, iclass 10, count 0 2006.173.04:12:16.01#ibcon#*after write, iclass 10, count 0 2006.173.04:12:16.01#ibcon#*before return 0, iclass 10, count 0 2006.173.04:12:16.01#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.04:12:16.01#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.04:12:16.01#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.04:12:16.01#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.04:12:16.01$vck44/va=8,4 2006.173.04:12:16.01#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.04:12:16.01#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.04:12:16.01#ibcon#ireg 11 cls_cnt 2 2006.173.04:12:16.01#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.04:12:16.07#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.04:12:16.07#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.04:12:16.07#ibcon#enter wrdev, iclass 12, count 2 2006.173.04:12:16.07#ibcon#first serial, iclass 12, count 2 2006.173.04:12:16.07#ibcon#enter sib2, iclass 12, count 2 2006.173.04:12:16.07#ibcon#flushed, iclass 12, count 2 2006.173.04:12:16.07#ibcon#about to write, iclass 12, count 2 2006.173.04:12:16.07#ibcon#wrote, iclass 12, count 2 2006.173.04:12:16.07#ibcon#about to read 3, iclass 12, count 2 2006.173.04:12:16.09#ibcon#read 3, iclass 12, count 2 2006.173.04:12:16.09#ibcon#about to read 4, iclass 12, count 2 2006.173.04:12:16.09#ibcon#read 4, iclass 12, count 2 2006.173.04:12:16.09#ibcon#about to read 5, iclass 12, count 2 2006.173.04:12:16.09#ibcon#read 5, iclass 12, count 2 2006.173.04:12:16.09#ibcon#about to read 6, iclass 12, count 2 2006.173.04:12:16.09#ibcon#read 6, iclass 12, count 2 2006.173.04:12:16.09#ibcon#end of sib2, iclass 12, count 2 2006.173.04:12:16.09#ibcon#*mode == 0, iclass 12, count 2 2006.173.04:12:16.09#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.04:12:16.09#ibcon#[25=AT08-04\r\n] 2006.173.04:12:16.09#ibcon#*before write, iclass 12, count 2 2006.173.04:12:16.09#ibcon#enter sib2, iclass 12, count 2 2006.173.04:12:16.09#ibcon#flushed, iclass 12, count 2 2006.173.04:12:16.09#ibcon#about to write, iclass 12, count 2 2006.173.04:12:16.09#ibcon#wrote, iclass 12, count 2 2006.173.04:12:16.09#ibcon#about to read 3, iclass 12, count 2 2006.173.04:12:16.12#ibcon#read 3, iclass 12, count 2 2006.173.04:12:16.12#ibcon#about to read 4, iclass 12, count 2 2006.173.04:12:16.12#ibcon#read 4, iclass 12, count 2 2006.173.04:12:16.12#ibcon#about to read 5, iclass 12, count 2 2006.173.04:12:16.12#ibcon#read 5, iclass 12, count 2 2006.173.04:12:16.12#ibcon#about to read 6, iclass 12, count 2 2006.173.04:12:16.12#ibcon#read 6, iclass 12, count 2 2006.173.04:12:16.12#ibcon#end of sib2, iclass 12, count 2 2006.173.04:12:16.12#ibcon#*after write, iclass 12, count 2 2006.173.04:12:16.12#ibcon#*before return 0, iclass 12, count 2 2006.173.04:12:16.12#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.04:12:16.12#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.04:12:16.12#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.04:12:16.12#ibcon#ireg 7 cls_cnt 0 2006.173.04:12:16.12#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.04:12:16.24#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.04:12:16.24#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.04:12:16.24#ibcon#enter wrdev, iclass 12, count 0 2006.173.04:12:16.24#ibcon#first serial, iclass 12, count 0 2006.173.04:12:16.24#ibcon#enter sib2, iclass 12, count 0 2006.173.04:12:16.24#ibcon#flushed, iclass 12, count 0 2006.173.04:12:16.24#ibcon#about to write, iclass 12, count 0 2006.173.04:12:16.24#ibcon#wrote, iclass 12, count 0 2006.173.04:12:16.24#ibcon#about to read 3, iclass 12, count 0 2006.173.04:12:16.26#ibcon#read 3, iclass 12, count 0 2006.173.04:12:16.26#ibcon#about to read 4, iclass 12, count 0 2006.173.04:12:16.26#ibcon#read 4, iclass 12, count 0 2006.173.04:12:16.26#ibcon#about to read 5, iclass 12, count 0 2006.173.04:12:16.26#ibcon#read 5, iclass 12, count 0 2006.173.04:12:16.26#ibcon#about to read 6, iclass 12, count 0 2006.173.04:12:16.26#ibcon#read 6, iclass 12, count 0 2006.173.04:12:16.26#ibcon#end of sib2, iclass 12, count 0 2006.173.04:12:16.26#ibcon#*mode == 0, iclass 12, count 0 2006.173.04:12:16.26#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.04:12:16.26#ibcon#[25=USB\r\n] 2006.173.04:12:16.26#ibcon#*before write, iclass 12, count 0 2006.173.04:12:16.26#ibcon#enter sib2, iclass 12, count 0 2006.173.04:12:16.26#ibcon#flushed, iclass 12, count 0 2006.173.04:12:16.26#ibcon#about to write, iclass 12, count 0 2006.173.04:12:16.26#ibcon#wrote, iclass 12, count 0 2006.173.04:12:16.26#ibcon#about to read 3, iclass 12, count 0 2006.173.04:12:16.29#ibcon#read 3, iclass 12, count 0 2006.173.04:12:16.29#ibcon#about to read 4, iclass 12, count 0 2006.173.04:12:16.29#ibcon#read 4, iclass 12, count 0 2006.173.04:12:16.29#ibcon#about to read 5, iclass 12, count 0 2006.173.04:12:16.29#ibcon#read 5, iclass 12, count 0 2006.173.04:12:16.29#ibcon#about to read 6, iclass 12, count 0 2006.173.04:12:16.29#ibcon#read 6, iclass 12, count 0 2006.173.04:12:16.29#ibcon#end of sib2, iclass 12, count 0 2006.173.04:12:16.29#ibcon#*after write, iclass 12, count 0 2006.173.04:12:16.29#ibcon#*before return 0, iclass 12, count 0 2006.173.04:12:16.29#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.04:12:16.29#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.04:12:16.29#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.04:12:16.29#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.04:12:16.29$vck44/vblo=1,629.99 2006.173.04:12:16.29#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.04:12:16.29#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.04:12:16.29#ibcon#ireg 17 cls_cnt 0 2006.173.04:12:16.29#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.04:12:16.29#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.04:12:16.29#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.04:12:16.29#ibcon#enter wrdev, iclass 14, count 0 2006.173.04:12:16.29#ibcon#first serial, iclass 14, count 0 2006.173.04:12:16.29#ibcon#enter sib2, iclass 14, count 0 2006.173.04:12:16.29#ibcon#flushed, iclass 14, count 0 2006.173.04:12:16.29#ibcon#about to write, iclass 14, count 0 2006.173.04:12:16.29#ibcon#wrote, iclass 14, count 0 2006.173.04:12:16.29#ibcon#about to read 3, iclass 14, count 0 2006.173.04:12:16.31#ibcon#read 3, iclass 14, count 0 2006.173.04:12:16.31#ibcon#about to read 4, iclass 14, count 0 2006.173.04:12:16.31#ibcon#read 4, iclass 14, count 0 2006.173.04:12:16.31#ibcon#about to read 5, iclass 14, count 0 2006.173.04:12:16.31#ibcon#read 5, iclass 14, count 0 2006.173.04:12:16.31#ibcon#about to read 6, iclass 14, count 0 2006.173.04:12:16.31#ibcon#read 6, iclass 14, count 0 2006.173.04:12:16.31#ibcon#end of sib2, iclass 14, count 0 2006.173.04:12:16.31#ibcon#*mode == 0, iclass 14, count 0 2006.173.04:12:16.31#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.04:12:16.31#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.04:12:16.31#ibcon#*before write, iclass 14, count 0 2006.173.04:12:16.31#ibcon#enter sib2, iclass 14, count 0 2006.173.04:12:16.31#ibcon#flushed, iclass 14, count 0 2006.173.04:12:16.31#ibcon#about to write, iclass 14, count 0 2006.173.04:12:16.31#ibcon#wrote, iclass 14, count 0 2006.173.04:12:16.31#ibcon#about to read 3, iclass 14, count 0 2006.173.04:12:16.35#ibcon#read 3, iclass 14, count 0 2006.173.04:12:16.35#ibcon#about to read 4, iclass 14, count 0 2006.173.04:12:16.35#ibcon#read 4, iclass 14, count 0 2006.173.04:12:16.35#ibcon#about to read 5, iclass 14, count 0 2006.173.04:12:16.35#ibcon#read 5, iclass 14, count 0 2006.173.04:12:16.35#ibcon#about to read 6, iclass 14, count 0 2006.173.04:12:16.35#ibcon#read 6, iclass 14, count 0 2006.173.04:12:16.35#ibcon#end of sib2, iclass 14, count 0 2006.173.04:12:16.35#ibcon#*after write, iclass 14, count 0 2006.173.04:12:16.35#ibcon#*before return 0, iclass 14, count 0 2006.173.04:12:16.35#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.04:12:16.35#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.04:12:16.35#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.04:12:16.35#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.04:12:16.35$vck44/vb=1,4 2006.173.04:12:16.35#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.04:12:16.35#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.04:12:16.35#ibcon#ireg 11 cls_cnt 2 2006.173.04:12:16.35#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.04:12:16.35#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.04:12:16.35#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.04:12:16.35#ibcon#enter wrdev, iclass 16, count 2 2006.173.04:12:16.35#ibcon#first serial, iclass 16, count 2 2006.173.04:12:16.35#ibcon#enter sib2, iclass 16, count 2 2006.173.04:12:16.35#ibcon#flushed, iclass 16, count 2 2006.173.04:12:16.35#ibcon#about to write, iclass 16, count 2 2006.173.04:12:16.35#ibcon#wrote, iclass 16, count 2 2006.173.04:12:16.35#ibcon#about to read 3, iclass 16, count 2 2006.173.04:12:16.37#ibcon#read 3, iclass 16, count 2 2006.173.04:12:16.37#ibcon#about to read 4, iclass 16, count 2 2006.173.04:12:16.37#ibcon#read 4, iclass 16, count 2 2006.173.04:12:16.37#ibcon#about to read 5, iclass 16, count 2 2006.173.04:12:16.37#ibcon#read 5, iclass 16, count 2 2006.173.04:12:16.37#ibcon#about to read 6, iclass 16, count 2 2006.173.04:12:16.37#ibcon#read 6, iclass 16, count 2 2006.173.04:12:16.37#ibcon#end of sib2, iclass 16, count 2 2006.173.04:12:16.37#ibcon#*mode == 0, iclass 16, count 2 2006.173.04:12:16.37#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.04:12:16.37#ibcon#[27=AT01-04\r\n] 2006.173.04:12:16.37#ibcon#*before write, iclass 16, count 2 2006.173.04:12:16.37#ibcon#enter sib2, iclass 16, count 2 2006.173.04:12:16.37#ibcon#flushed, iclass 16, count 2 2006.173.04:12:16.37#ibcon#about to write, iclass 16, count 2 2006.173.04:12:16.37#ibcon#wrote, iclass 16, count 2 2006.173.04:12:16.37#ibcon#about to read 3, iclass 16, count 2 2006.173.04:12:16.40#ibcon#read 3, iclass 16, count 2 2006.173.04:12:16.40#ibcon#about to read 4, iclass 16, count 2 2006.173.04:12:16.40#ibcon#read 4, iclass 16, count 2 2006.173.04:12:16.40#ibcon#about to read 5, iclass 16, count 2 2006.173.04:12:16.40#ibcon#read 5, iclass 16, count 2 2006.173.04:12:16.40#ibcon#about to read 6, iclass 16, count 2 2006.173.04:12:16.40#ibcon#read 6, iclass 16, count 2 2006.173.04:12:16.40#ibcon#end of sib2, iclass 16, count 2 2006.173.04:12:16.40#ibcon#*after write, iclass 16, count 2 2006.173.04:12:16.40#ibcon#*before return 0, iclass 16, count 2 2006.173.04:12:16.40#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.04:12:16.40#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.04:12:16.40#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.04:12:16.40#ibcon#ireg 7 cls_cnt 0 2006.173.04:12:16.40#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.04:12:16.52#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.04:12:16.52#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.04:12:16.52#ibcon#enter wrdev, iclass 16, count 0 2006.173.04:12:16.52#ibcon#first serial, iclass 16, count 0 2006.173.04:12:16.52#ibcon#enter sib2, iclass 16, count 0 2006.173.04:12:16.52#ibcon#flushed, iclass 16, count 0 2006.173.04:12:16.52#ibcon#about to write, iclass 16, count 0 2006.173.04:12:16.52#ibcon#wrote, iclass 16, count 0 2006.173.04:12:16.52#ibcon#about to read 3, iclass 16, count 0 2006.173.04:12:16.54#ibcon#read 3, iclass 16, count 0 2006.173.04:12:16.54#ibcon#about to read 4, iclass 16, count 0 2006.173.04:12:16.54#ibcon#read 4, iclass 16, count 0 2006.173.04:12:16.54#ibcon#about to read 5, iclass 16, count 0 2006.173.04:12:16.54#ibcon#read 5, iclass 16, count 0 2006.173.04:12:16.54#ibcon#about to read 6, iclass 16, count 0 2006.173.04:12:16.54#ibcon#read 6, iclass 16, count 0 2006.173.04:12:16.54#ibcon#end of sib2, iclass 16, count 0 2006.173.04:12:16.54#ibcon#*mode == 0, iclass 16, count 0 2006.173.04:12:16.54#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.04:12:16.54#ibcon#[27=USB\r\n] 2006.173.04:12:16.54#ibcon#*before write, iclass 16, count 0 2006.173.04:12:16.54#ibcon#enter sib2, iclass 16, count 0 2006.173.04:12:16.54#ibcon#flushed, iclass 16, count 0 2006.173.04:12:16.54#ibcon#about to write, iclass 16, count 0 2006.173.04:12:16.54#ibcon#wrote, iclass 16, count 0 2006.173.04:12:16.54#ibcon#about to read 3, iclass 16, count 0 2006.173.04:12:16.57#ibcon#read 3, iclass 16, count 0 2006.173.04:12:16.57#ibcon#about to read 4, iclass 16, count 0 2006.173.04:12:16.57#ibcon#read 4, iclass 16, count 0 2006.173.04:12:16.57#ibcon#about to read 5, iclass 16, count 0 2006.173.04:12:16.57#ibcon#read 5, iclass 16, count 0 2006.173.04:12:16.57#ibcon#about to read 6, iclass 16, count 0 2006.173.04:12:16.57#ibcon#read 6, iclass 16, count 0 2006.173.04:12:16.57#ibcon#end of sib2, iclass 16, count 0 2006.173.04:12:16.57#ibcon#*after write, iclass 16, count 0 2006.173.04:12:16.57#ibcon#*before return 0, iclass 16, count 0 2006.173.04:12:16.57#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.04:12:16.57#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.04:12:16.57#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.04:12:16.57#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.04:12:16.57$vck44/vblo=2,634.99 2006.173.04:12:16.57#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.04:12:16.57#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.04:12:16.57#ibcon#ireg 17 cls_cnt 0 2006.173.04:12:16.57#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.04:12:16.57#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.04:12:16.57#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.04:12:16.57#ibcon#enter wrdev, iclass 18, count 0 2006.173.04:12:16.57#ibcon#first serial, iclass 18, count 0 2006.173.04:12:16.57#ibcon#enter sib2, iclass 18, count 0 2006.173.04:12:16.57#ibcon#flushed, iclass 18, count 0 2006.173.04:12:16.57#ibcon#about to write, iclass 18, count 0 2006.173.04:12:16.57#ibcon#wrote, iclass 18, count 0 2006.173.04:12:16.57#ibcon#about to read 3, iclass 18, count 0 2006.173.04:12:16.59#ibcon#read 3, iclass 18, count 0 2006.173.04:12:16.59#ibcon#about to read 4, iclass 18, count 0 2006.173.04:12:16.59#ibcon#read 4, iclass 18, count 0 2006.173.04:12:16.59#ibcon#about to read 5, iclass 18, count 0 2006.173.04:12:16.59#ibcon#read 5, iclass 18, count 0 2006.173.04:12:16.59#ibcon#about to read 6, iclass 18, count 0 2006.173.04:12:16.59#ibcon#read 6, iclass 18, count 0 2006.173.04:12:16.59#ibcon#end of sib2, iclass 18, count 0 2006.173.04:12:16.59#ibcon#*mode == 0, iclass 18, count 0 2006.173.04:12:16.59#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.04:12:16.59#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.04:12:16.59#ibcon#*before write, iclass 18, count 0 2006.173.04:12:16.59#ibcon#enter sib2, iclass 18, count 0 2006.173.04:12:16.59#ibcon#flushed, iclass 18, count 0 2006.173.04:12:16.59#ibcon#about to write, iclass 18, count 0 2006.173.04:12:16.59#ibcon#wrote, iclass 18, count 0 2006.173.04:12:16.59#ibcon#about to read 3, iclass 18, count 0 2006.173.04:12:16.63#ibcon#read 3, iclass 18, count 0 2006.173.04:12:16.63#ibcon#about to read 4, iclass 18, count 0 2006.173.04:12:16.63#ibcon#read 4, iclass 18, count 0 2006.173.04:12:16.63#ibcon#about to read 5, iclass 18, count 0 2006.173.04:12:16.63#ibcon#read 5, iclass 18, count 0 2006.173.04:12:16.63#ibcon#about to read 6, iclass 18, count 0 2006.173.04:12:16.63#ibcon#read 6, iclass 18, count 0 2006.173.04:12:16.63#ibcon#end of sib2, iclass 18, count 0 2006.173.04:12:16.63#ibcon#*after write, iclass 18, count 0 2006.173.04:12:16.63#ibcon#*before return 0, iclass 18, count 0 2006.173.04:12:16.63#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.04:12:16.63#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.04:12:16.63#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.04:12:16.63#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.04:12:16.63$vck44/vb=2,4 2006.173.04:12:16.63#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.04:12:16.63#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.04:12:16.63#ibcon#ireg 11 cls_cnt 2 2006.173.04:12:16.63#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.04:12:16.69#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.04:12:16.69#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.04:12:16.69#ibcon#enter wrdev, iclass 20, count 2 2006.173.04:12:16.69#ibcon#first serial, iclass 20, count 2 2006.173.04:12:16.69#ibcon#enter sib2, iclass 20, count 2 2006.173.04:12:16.69#ibcon#flushed, iclass 20, count 2 2006.173.04:12:16.69#ibcon#about to write, iclass 20, count 2 2006.173.04:12:16.69#ibcon#wrote, iclass 20, count 2 2006.173.04:12:16.69#ibcon#about to read 3, iclass 20, count 2 2006.173.04:12:16.71#ibcon#read 3, iclass 20, count 2 2006.173.04:12:16.71#ibcon#about to read 4, iclass 20, count 2 2006.173.04:12:16.71#ibcon#read 4, iclass 20, count 2 2006.173.04:12:16.71#ibcon#about to read 5, iclass 20, count 2 2006.173.04:12:16.71#ibcon#read 5, iclass 20, count 2 2006.173.04:12:16.71#ibcon#about to read 6, iclass 20, count 2 2006.173.04:12:16.71#ibcon#read 6, iclass 20, count 2 2006.173.04:12:16.71#ibcon#end of sib2, iclass 20, count 2 2006.173.04:12:16.71#ibcon#*mode == 0, iclass 20, count 2 2006.173.04:12:16.71#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.04:12:16.71#ibcon#[27=AT02-04\r\n] 2006.173.04:12:16.71#ibcon#*before write, iclass 20, count 2 2006.173.04:12:16.71#ibcon#enter sib2, iclass 20, count 2 2006.173.04:12:16.71#ibcon#flushed, iclass 20, count 2 2006.173.04:12:16.71#ibcon#about to write, iclass 20, count 2 2006.173.04:12:16.71#ibcon#wrote, iclass 20, count 2 2006.173.04:12:16.71#ibcon#about to read 3, iclass 20, count 2 2006.173.04:12:16.74#ibcon#read 3, iclass 20, count 2 2006.173.04:12:16.74#ibcon#about to read 4, iclass 20, count 2 2006.173.04:12:16.74#ibcon#read 4, iclass 20, count 2 2006.173.04:12:16.74#ibcon#about to read 5, iclass 20, count 2 2006.173.04:12:16.74#ibcon#read 5, iclass 20, count 2 2006.173.04:12:16.74#ibcon#about to read 6, iclass 20, count 2 2006.173.04:12:16.74#ibcon#read 6, iclass 20, count 2 2006.173.04:12:16.74#ibcon#end of sib2, iclass 20, count 2 2006.173.04:12:16.74#ibcon#*after write, iclass 20, count 2 2006.173.04:12:16.74#ibcon#*before return 0, iclass 20, count 2 2006.173.04:12:16.74#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.04:12:16.74#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.04:12:16.74#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.04:12:16.74#ibcon#ireg 7 cls_cnt 0 2006.173.04:12:16.74#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.04:12:16.86#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.04:12:16.86#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.04:12:16.86#ibcon#enter wrdev, iclass 20, count 0 2006.173.04:12:16.86#ibcon#first serial, iclass 20, count 0 2006.173.04:12:16.86#ibcon#enter sib2, iclass 20, count 0 2006.173.04:12:16.86#ibcon#flushed, iclass 20, count 0 2006.173.04:12:16.86#ibcon#about to write, iclass 20, count 0 2006.173.04:12:16.86#ibcon#wrote, iclass 20, count 0 2006.173.04:12:16.86#ibcon#about to read 3, iclass 20, count 0 2006.173.04:12:16.88#ibcon#read 3, iclass 20, count 0 2006.173.04:12:16.88#ibcon#about to read 4, iclass 20, count 0 2006.173.04:12:16.88#ibcon#read 4, iclass 20, count 0 2006.173.04:12:16.88#ibcon#about to read 5, iclass 20, count 0 2006.173.04:12:16.88#ibcon#read 5, iclass 20, count 0 2006.173.04:12:16.88#ibcon#about to read 6, iclass 20, count 0 2006.173.04:12:16.88#ibcon#read 6, iclass 20, count 0 2006.173.04:12:16.88#ibcon#end of sib2, iclass 20, count 0 2006.173.04:12:16.88#ibcon#*mode == 0, iclass 20, count 0 2006.173.04:12:16.88#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.04:12:16.88#ibcon#[27=USB\r\n] 2006.173.04:12:16.88#ibcon#*before write, iclass 20, count 0 2006.173.04:12:16.88#ibcon#enter sib2, iclass 20, count 0 2006.173.04:12:16.88#ibcon#flushed, iclass 20, count 0 2006.173.04:12:16.88#ibcon#about to write, iclass 20, count 0 2006.173.04:12:16.88#ibcon#wrote, iclass 20, count 0 2006.173.04:12:16.88#ibcon#about to read 3, iclass 20, count 0 2006.173.04:12:16.91#ibcon#read 3, iclass 20, count 0 2006.173.04:12:16.91#ibcon#about to read 4, iclass 20, count 0 2006.173.04:12:16.91#ibcon#read 4, iclass 20, count 0 2006.173.04:12:16.91#ibcon#about to read 5, iclass 20, count 0 2006.173.04:12:16.91#ibcon#read 5, iclass 20, count 0 2006.173.04:12:16.91#ibcon#about to read 6, iclass 20, count 0 2006.173.04:12:16.91#ibcon#read 6, iclass 20, count 0 2006.173.04:12:16.91#ibcon#end of sib2, iclass 20, count 0 2006.173.04:12:16.91#ibcon#*after write, iclass 20, count 0 2006.173.04:12:16.91#ibcon#*before return 0, iclass 20, count 0 2006.173.04:12:16.91#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.04:12:16.91#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.04:12:16.91#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.04:12:16.91#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.04:12:16.91$vck44/vblo=3,649.99 2006.173.04:12:16.91#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.04:12:16.91#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.04:12:16.91#ibcon#ireg 17 cls_cnt 0 2006.173.04:12:16.91#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.04:12:16.91#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.04:12:16.91#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.04:12:16.91#ibcon#enter wrdev, iclass 22, count 0 2006.173.04:12:16.91#ibcon#first serial, iclass 22, count 0 2006.173.04:12:16.91#ibcon#enter sib2, iclass 22, count 0 2006.173.04:12:16.91#ibcon#flushed, iclass 22, count 0 2006.173.04:12:16.91#ibcon#about to write, iclass 22, count 0 2006.173.04:12:16.91#ibcon#wrote, iclass 22, count 0 2006.173.04:12:16.91#ibcon#about to read 3, iclass 22, count 0 2006.173.04:12:16.93#ibcon#read 3, iclass 22, count 0 2006.173.04:12:16.93#ibcon#about to read 4, iclass 22, count 0 2006.173.04:12:16.93#ibcon#read 4, iclass 22, count 0 2006.173.04:12:16.93#ibcon#about to read 5, iclass 22, count 0 2006.173.04:12:16.93#ibcon#read 5, iclass 22, count 0 2006.173.04:12:16.93#ibcon#about to read 6, iclass 22, count 0 2006.173.04:12:16.93#ibcon#read 6, iclass 22, count 0 2006.173.04:12:16.93#ibcon#end of sib2, iclass 22, count 0 2006.173.04:12:16.93#ibcon#*mode == 0, iclass 22, count 0 2006.173.04:12:16.93#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.04:12:16.93#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.04:12:16.93#ibcon#*before write, iclass 22, count 0 2006.173.04:12:16.93#ibcon#enter sib2, iclass 22, count 0 2006.173.04:12:16.93#ibcon#flushed, iclass 22, count 0 2006.173.04:12:16.93#ibcon#about to write, iclass 22, count 0 2006.173.04:12:16.93#ibcon#wrote, iclass 22, count 0 2006.173.04:12:16.93#ibcon#about to read 3, iclass 22, count 0 2006.173.04:12:16.97#ibcon#read 3, iclass 22, count 0 2006.173.04:12:16.97#ibcon#about to read 4, iclass 22, count 0 2006.173.04:12:16.97#ibcon#read 4, iclass 22, count 0 2006.173.04:12:16.97#ibcon#about to read 5, iclass 22, count 0 2006.173.04:12:16.97#ibcon#read 5, iclass 22, count 0 2006.173.04:12:16.97#ibcon#about to read 6, iclass 22, count 0 2006.173.04:12:16.97#ibcon#read 6, iclass 22, count 0 2006.173.04:12:16.97#ibcon#end of sib2, iclass 22, count 0 2006.173.04:12:16.97#ibcon#*after write, iclass 22, count 0 2006.173.04:12:16.97#ibcon#*before return 0, iclass 22, count 0 2006.173.04:12:16.97#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.04:12:16.97#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.04:12:16.97#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.04:12:16.97#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.04:12:16.97$vck44/vb=3,4 2006.173.04:12:16.97#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.04:12:16.97#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.04:12:16.97#ibcon#ireg 11 cls_cnt 2 2006.173.04:12:16.97#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.04:12:17.03#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.04:12:17.03#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.04:12:17.03#ibcon#enter wrdev, iclass 24, count 2 2006.173.04:12:17.03#ibcon#first serial, iclass 24, count 2 2006.173.04:12:17.03#ibcon#enter sib2, iclass 24, count 2 2006.173.04:12:17.03#ibcon#flushed, iclass 24, count 2 2006.173.04:12:17.03#ibcon#about to write, iclass 24, count 2 2006.173.04:12:17.03#ibcon#wrote, iclass 24, count 2 2006.173.04:12:17.03#ibcon#about to read 3, iclass 24, count 2 2006.173.04:12:17.05#ibcon#read 3, iclass 24, count 2 2006.173.04:12:17.05#ibcon#about to read 4, iclass 24, count 2 2006.173.04:12:17.05#ibcon#read 4, iclass 24, count 2 2006.173.04:12:17.05#ibcon#about to read 5, iclass 24, count 2 2006.173.04:12:17.05#ibcon#read 5, iclass 24, count 2 2006.173.04:12:17.05#ibcon#about to read 6, iclass 24, count 2 2006.173.04:12:17.05#ibcon#read 6, iclass 24, count 2 2006.173.04:12:17.05#ibcon#end of sib2, iclass 24, count 2 2006.173.04:12:17.05#ibcon#*mode == 0, iclass 24, count 2 2006.173.04:12:17.05#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.04:12:17.05#ibcon#[27=AT03-04\r\n] 2006.173.04:12:17.05#ibcon#*before write, iclass 24, count 2 2006.173.04:12:17.05#ibcon#enter sib2, iclass 24, count 2 2006.173.04:12:17.05#ibcon#flushed, iclass 24, count 2 2006.173.04:12:17.05#ibcon#about to write, iclass 24, count 2 2006.173.04:12:17.05#ibcon#wrote, iclass 24, count 2 2006.173.04:12:17.05#ibcon#about to read 3, iclass 24, count 2 2006.173.04:12:17.08#ibcon#read 3, iclass 24, count 2 2006.173.04:12:17.08#ibcon#about to read 4, iclass 24, count 2 2006.173.04:12:17.08#ibcon#read 4, iclass 24, count 2 2006.173.04:12:17.08#ibcon#about to read 5, iclass 24, count 2 2006.173.04:12:17.08#ibcon#read 5, iclass 24, count 2 2006.173.04:12:17.08#ibcon#about to read 6, iclass 24, count 2 2006.173.04:12:17.08#ibcon#read 6, iclass 24, count 2 2006.173.04:12:17.08#ibcon#end of sib2, iclass 24, count 2 2006.173.04:12:17.08#ibcon#*after write, iclass 24, count 2 2006.173.04:12:17.08#ibcon#*before return 0, iclass 24, count 2 2006.173.04:12:17.08#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.04:12:17.08#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.04:12:17.08#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.04:12:17.08#ibcon#ireg 7 cls_cnt 0 2006.173.04:12:17.08#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.04:12:17.20#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.04:12:17.20#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.04:12:17.20#ibcon#enter wrdev, iclass 24, count 0 2006.173.04:12:17.20#ibcon#first serial, iclass 24, count 0 2006.173.04:12:17.20#ibcon#enter sib2, iclass 24, count 0 2006.173.04:12:17.20#ibcon#flushed, iclass 24, count 0 2006.173.04:12:17.20#ibcon#about to write, iclass 24, count 0 2006.173.04:12:17.20#ibcon#wrote, iclass 24, count 0 2006.173.04:12:17.20#ibcon#about to read 3, iclass 24, count 0 2006.173.04:12:17.22#ibcon#read 3, iclass 24, count 0 2006.173.04:12:17.22#ibcon#about to read 4, iclass 24, count 0 2006.173.04:12:17.22#ibcon#read 4, iclass 24, count 0 2006.173.04:12:17.22#ibcon#about to read 5, iclass 24, count 0 2006.173.04:12:17.22#ibcon#read 5, iclass 24, count 0 2006.173.04:12:17.22#ibcon#about to read 6, iclass 24, count 0 2006.173.04:12:17.22#ibcon#read 6, iclass 24, count 0 2006.173.04:12:17.22#ibcon#end of sib2, iclass 24, count 0 2006.173.04:12:17.22#ibcon#*mode == 0, iclass 24, count 0 2006.173.04:12:17.22#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.04:12:17.22#ibcon#[27=USB\r\n] 2006.173.04:12:17.22#ibcon#*before write, iclass 24, count 0 2006.173.04:12:17.22#ibcon#enter sib2, iclass 24, count 0 2006.173.04:12:17.22#ibcon#flushed, iclass 24, count 0 2006.173.04:12:17.22#ibcon#about to write, iclass 24, count 0 2006.173.04:12:17.22#ibcon#wrote, iclass 24, count 0 2006.173.04:12:17.22#ibcon#about to read 3, iclass 24, count 0 2006.173.04:12:17.25#ibcon#read 3, iclass 24, count 0 2006.173.04:12:17.25#ibcon#about to read 4, iclass 24, count 0 2006.173.04:12:17.25#ibcon#read 4, iclass 24, count 0 2006.173.04:12:17.25#ibcon#about to read 5, iclass 24, count 0 2006.173.04:12:17.25#ibcon#read 5, iclass 24, count 0 2006.173.04:12:17.25#ibcon#about to read 6, iclass 24, count 0 2006.173.04:12:17.25#ibcon#read 6, iclass 24, count 0 2006.173.04:12:17.25#ibcon#end of sib2, iclass 24, count 0 2006.173.04:12:17.25#ibcon#*after write, iclass 24, count 0 2006.173.04:12:17.25#ibcon#*before return 0, iclass 24, count 0 2006.173.04:12:17.25#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.04:12:17.25#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.04:12:17.25#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.04:12:17.25#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.04:12:17.25$vck44/vblo=4,679.99 2006.173.04:12:17.25#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.04:12:17.25#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.04:12:17.25#ibcon#ireg 17 cls_cnt 0 2006.173.04:12:17.25#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.04:12:17.25#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.04:12:17.25#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.04:12:17.25#ibcon#enter wrdev, iclass 26, count 0 2006.173.04:12:17.25#ibcon#first serial, iclass 26, count 0 2006.173.04:12:17.25#ibcon#enter sib2, iclass 26, count 0 2006.173.04:12:17.25#ibcon#flushed, iclass 26, count 0 2006.173.04:12:17.25#ibcon#about to write, iclass 26, count 0 2006.173.04:12:17.25#ibcon#wrote, iclass 26, count 0 2006.173.04:12:17.25#ibcon#about to read 3, iclass 26, count 0 2006.173.04:12:17.27#ibcon#read 3, iclass 26, count 0 2006.173.04:12:17.27#ibcon#about to read 4, iclass 26, count 0 2006.173.04:12:17.27#ibcon#read 4, iclass 26, count 0 2006.173.04:12:17.27#ibcon#about to read 5, iclass 26, count 0 2006.173.04:12:17.27#ibcon#read 5, iclass 26, count 0 2006.173.04:12:17.27#ibcon#about to read 6, iclass 26, count 0 2006.173.04:12:17.27#ibcon#read 6, iclass 26, count 0 2006.173.04:12:17.27#ibcon#end of sib2, iclass 26, count 0 2006.173.04:12:17.27#ibcon#*mode == 0, iclass 26, count 0 2006.173.04:12:17.27#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.04:12:17.27#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.04:12:17.27#ibcon#*before write, iclass 26, count 0 2006.173.04:12:17.27#ibcon#enter sib2, iclass 26, count 0 2006.173.04:12:17.27#ibcon#flushed, iclass 26, count 0 2006.173.04:12:17.27#ibcon#about to write, iclass 26, count 0 2006.173.04:12:17.27#ibcon#wrote, iclass 26, count 0 2006.173.04:12:17.27#ibcon#about to read 3, iclass 26, count 0 2006.173.04:12:17.31#ibcon#read 3, iclass 26, count 0 2006.173.04:12:17.31#ibcon#about to read 4, iclass 26, count 0 2006.173.04:12:17.31#ibcon#read 4, iclass 26, count 0 2006.173.04:12:17.31#ibcon#about to read 5, iclass 26, count 0 2006.173.04:12:17.31#ibcon#read 5, iclass 26, count 0 2006.173.04:12:17.31#ibcon#about to read 6, iclass 26, count 0 2006.173.04:12:17.31#ibcon#read 6, iclass 26, count 0 2006.173.04:12:17.31#ibcon#end of sib2, iclass 26, count 0 2006.173.04:12:17.31#ibcon#*after write, iclass 26, count 0 2006.173.04:12:17.31#ibcon#*before return 0, iclass 26, count 0 2006.173.04:12:17.31#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.04:12:17.31#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.04:12:17.31#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.04:12:17.31#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.04:12:17.31$vck44/vb=4,4 2006.173.04:12:17.31#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.04:12:17.31#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.04:12:17.31#ibcon#ireg 11 cls_cnt 2 2006.173.04:12:17.31#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.04:12:17.37#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.04:12:17.37#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.04:12:17.37#ibcon#enter wrdev, iclass 28, count 2 2006.173.04:12:17.37#ibcon#first serial, iclass 28, count 2 2006.173.04:12:17.37#ibcon#enter sib2, iclass 28, count 2 2006.173.04:12:17.37#ibcon#flushed, iclass 28, count 2 2006.173.04:12:17.37#ibcon#about to write, iclass 28, count 2 2006.173.04:12:17.37#ibcon#wrote, iclass 28, count 2 2006.173.04:12:17.37#ibcon#about to read 3, iclass 28, count 2 2006.173.04:12:17.39#ibcon#read 3, iclass 28, count 2 2006.173.04:12:17.39#ibcon#about to read 4, iclass 28, count 2 2006.173.04:12:17.39#ibcon#read 4, iclass 28, count 2 2006.173.04:12:17.39#ibcon#about to read 5, iclass 28, count 2 2006.173.04:12:17.39#ibcon#read 5, iclass 28, count 2 2006.173.04:12:17.39#ibcon#about to read 6, iclass 28, count 2 2006.173.04:12:17.39#ibcon#read 6, iclass 28, count 2 2006.173.04:12:17.39#ibcon#end of sib2, iclass 28, count 2 2006.173.04:12:17.39#ibcon#*mode == 0, iclass 28, count 2 2006.173.04:12:17.39#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.04:12:17.39#ibcon#[27=AT04-04\r\n] 2006.173.04:12:17.39#ibcon#*before write, iclass 28, count 2 2006.173.04:12:17.39#ibcon#enter sib2, iclass 28, count 2 2006.173.04:12:17.39#ibcon#flushed, iclass 28, count 2 2006.173.04:12:17.39#ibcon#about to write, iclass 28, count 2 2006.173.04:12:17.39#ibcon#wrote, iclass 28, count 2 2006.173.04:12:17.39#ibcon#about to read 3, iclass 28, count 2 2006.173.04:12:17.42#ibcon#read 3, iclass 28, count 2 2006.173.04:12:17.42#ibcon#about to read 4, iclass 28, count 2 2006.173.04:12:17.42#ibcon#read 4, iclass 28, count 2 2006.173.04:12:17.42#ibcon#about to read 5, iclass 28, count 2 2006.173.04:12:17.42#ibcon#read 5, iclass 28, count 2 2006.173.04:12:17.42#ibcon#about to read 6, iclass 28, count 2 2006.173.04:12:17.42#ibcon#read 6, iclass 28, count 2 2006.173.04:12:17.42#ibcon#end of sib2, iclass 28, count 2 2006.173.04:12:17.42#ibcon#*after write, iclass 28, count 2 2006.173.04:12:17.42#ibcon#*before return 0, iclass 28, count 2 2006.173.04:12:17.42#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.04:12:17.42#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.04:12:17.42#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.04:12:17.42#ibcon#ireg 7 cls_cnt 0 2006.173.04:12:17.42#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.04:12:17.54#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.04:12:17.54#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.04:12:17.54#ibcon#enter wrdev, iclass 28, count 0 2006.173.04:12:17.54#ibcon#first serial, iclass 28, count 0 2006.173.04:12:17.54#ibcon#enter sib2, iclass 28, count 0 2006.173.04:12:17.54#ibcon#flushed, iclass 28, count 0 2006.173.04:12:17.54#ibcon#about to write, iclass 28, count 0 2006.173.04:12:17.54#ibcon#wrote, iclass 28, count 0 2006.173.04:12:17.54#ibcon#about to read 3, iclass 28, count 0 2006.173.04:12:17.56#ibcon#read 3, iclass 28, count 0 2006.173.04:12:17.56#ibcon#about to read 4, iclass 28, count 0 2006.173.04:12:17.56#ibcon#read 4, iclass 28, count 0 2006.173.04:12:17.56#ibcon#about to read 5, iclass 28, count 0 2006.173.04:12:17.56#ibcon#read 5, iclass 28, count 0 2006.173.04:12:17.56#ibcon#about to read 6, iclass 28, count 0 2006.173.04:12:17.56#ibcon#read 6, iclass 28, count 0 2006.173.04:12:17.56#ibcon#end of sib2, iclass 28, count 0 2006.173.04:12:17.56#ibcon#*mode == 0, iclass 28, count 0 2006.173.04:12:17.56#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.04:12:17.56#ibcon#[27=USB\r\n] 2006.173.04:12:17.56#ibcon#*before write, iclass 28, count 0 2006.173.04:12:17.56#ibcon#enter sib2, iclass 28, count 0 2006.173.04:12:17.56#ibcon#flushed, iclass 28, count 0 2006.173.04:12:17.56#ibcon#about to write, iclass 28, count 0 2006.173.04:12:17.56#ibcon#wrote, iclass 28, count 0 2006.173.04:12:17.56#ibcon#about to read 3, iclass 28, count 0 2006.173.04:12:17.59#ibcon#read 3, iclass 28, count 0 2006.173.04:12:17.59#ibcon#about to read 4, iclass 28, count 0 2006.173.04:12:17.59#ibcon#read 4, iclass 28, count 0 2006.173.04:12:17.59#ibcon#about to read 5, iclass 28, count 0 2006.173.04:12:17.59#ibcon#read 5, iclass 28, count 0 2006.173.04:12:17.59#ibcon#about to read 6, iclass 28, count 0 2006.173.04:12:17.59#ibcon#read 6, iclass 28, count 0 2006.173.04:12:17.59#ibcon#end of sib2, iclass 28, count 0 2006.173.04:12:17.59#ibcon#*after write, iclass 28, count 0 2006.173.04:12:17.59#ibcon#*before return 0, iclass 28, count 0 2006.173.04:12:17.59#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.04:12:17.59#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.04:12:17.59#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.04:12:17.59#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.04:12:17.59$vck44/vblo=5,709.99 2006.173.04:12:17.59#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.04:12:17.59#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.04:12:17.59#ibcon#ireg 17 cls_cnt 0 2006.173.04:12:17.59#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.04:12:17.59#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.04:12:17.59#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.04:12:17.59#ibcon#enter wrdev, iclass 30, count 0 2006.173.04:12:17.59#ibcon#first serial, iclass 30, count 0 2006.173.04:12:17.59#ibcon#enter sib2, iclass 30, count 0 2006.173.04:12:17.59#ibcon#flushed, iclass 30, count 0 2006.173.04:12:17.59#ibcon#about to write, iclass 30, count 0 2006.173.04:12:17.59#ibcon#wrote, iclass 30, count 0 2006.173.04:12:17.59#ibcon#about to read 3, iclass 30, count 0 2006.173.04:12:17.61#ibcon#read 3, iclass 30, count 0 2006.173.04:12:17.61#ibcon#about to read 4, iclass 30, count 0 2006.173.04:12:17.61#ibcon#read 4, iclass 30, count 0 2006.173.04:12:17.61#ibcon#about to read 5, iclass 30, count 0 2006.173.04:12:17.61#ibcon#read 5, iclass 30, count 0 2006.173.04:12:17.61#ibcon#about to read 6, iclass 30, count 0 2006.173.04:12:17.61#ibcon#read 6, iclass 30, count 0 2006.173.04:12:17.61#ibcon#end of sib2, iclass 30, count 0 2006.173.04:12:17.61#ibcon#*mode == 0, iclass 30, count 0 2006.173.04:12:17.61#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.04:12:17.61#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.04:12:17.61#ibcon#*before write, iclass 30, count 0 2006.173.04:12:17.61#ibcon#enter sib2, iclass 30, count 0 2006.173.04:12:17.61#ibcon#flushed, iclass 30, count 0 2006.173.04:12:17.61#ibcon#about to write, iclass 30, count 0 2006.173.04:12:17.61#ibcon#wrote, iclass 30, count 0 2006.173.04:12:17.61#ibcon#about to read 3, iclass 30, count 0 2006.173.04:12:17.65#ibcon#read 3, iclass 30, count 0 2006.173.04:12:17.65#ibcon#about to read 4, iclass 30, count 0 2006.173.04:12:17.65#ibcon#read 4, iclass 30, count 0 2006.173.04:12:17.65#ibcon#about to read 5, iclass 30, count 0 2006.173.04:12:17.65#ibcon#read 5, iclass 30, count 0 2006.173.04:12:17.65#ibcon#about to read 6, iclass 30, count 0 2006.173.04:12:17.65#ibcon#read 6, iclass 30, count 0 2006.173.04:12:17.65#ibcon#end of sib2, iclass 30, count 0 2006.173.04:12:17.65#ibcon#*after write, iclass 30, count 0 2006.173.04:12:17.65#ibcon#*before return 0, iclass 30, count 0 2006.173.04:12:17.65#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.04:12:17.65#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.04:12:17.65#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.04:12:17.65#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.04:12:17.65$vck44/vb=5,4 2006.173.04:12:17.65#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.173.04:12:17.65#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.173.04:12:17.65#ibcon#ireg 11 cls_cnt 2 2006.173.04:12:17.65#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.04:12:17.71#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.04:12:17.71#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.04:12:17.71#ibcon#enter wrdev, iclass 32, count 2 2006.173.04:12:17.71#ibcon#first serial, iclass 32, count 2 2006.173.04:12:17.71#ibcon#enter sib2, iclass 32, count 2 2006.173.04:12:17.71#ibcon#flushed, iclass 32, count 2 2006.173.04:12:17.71#ibcon#about to write, iclass 32, count 2 2006.173.04:12:17.71#ibcon#wrote, iclass 32, count 2 2006.173.04:12:17.71#ibcon#about to read 3, iclass 32, count 2 2006.173.04:12:17.73#ibcon#read 3, iclass 32, count 2 2006.173.04:12:17.73#ibcon#about to read 4, iclass 32, count 2 2006.173.04:12:17.73#ibcon#read 4, iclass 32, count 2 2006.173.04:12:17.73#ibcon#about to read 5, iclass 32, count 2 2006.173.04:12:17.73#ibcon#read 5, iclass 32, count 2 2006.173.04:12:17.73#ibcon#about to read 6, iclass 32, count 2 2006.173.04:12:17.73#ibcon#read 6, iclass 32, count 2 2006.173.04:12:17.73#ibcon#end of sib2, iclass 32, count 2 2006.173.04:12:17.73#ibcon#*mode == 0, iclass 32, count 2 2006.173.04:12:17.73#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.173.04:12:17.73#ibcon#[27=AT05-04\r\n] 2006.173.04:12:17.73#ibcon#*before write, iclass 32, count 2 2006.173.04:12:17.73#ibcon#enter sib2, iclass 32, count 2 2006.173.04:12:17.73#ibcon#flushed, iclass 32, count 2 2006.173.04:12:17.73#ibcon#about to write, iclass 32, count 2 2006.173.04:12:17.73#ibcon#wrote, iclass 32, count 2 2006.173.04:12:17.73#ibcon#about to read 3, iclass 32, count 2 2006.173.04:12:17.76#ibcon#read 3, iclass 32, count 2 2006.173.04:12:17.76#ibcon#about to read 4, iclass 32, count 2 2006.173.04:12:17.76#ibcon#read 4, iclass 32, count 2 2006.173.04:12:17.76#ibcon#about to read 5, iclass 32, count 2 2006.173.04:12:17.76#ibcon#read 5, iclass 32, count 2 2006.173.04:12:17.76#ibcon#about to read 6, iclass 32, count 2 2006.173.04:12:17.76#ibcon#read 6, iclass 32, count 2 2006.173.04:12:17.76#ibcon#end of sib2, iclass 32, count 2 2006.173.04:12:17.76#ibcon#*after write, iclass 32, count 2 2006.173.04:12:17.76#ibcon#*before return 0, iclass 32, count 2 2006.173.04:12:17.76#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.04:12:17.76#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.173.04:12:17.76#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.173.04:12:17.76#ibcon#ireg 7 cls_cnt 0 2006.173.04:12:17.76#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.04:12:17.88#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.04:12:17.88#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.04:12:17.88#ibcon#enter wrdev, iclass 32, count 0 2006.173.04:12:17.88#ibcon#first serial, iclass 32, count 0 2006.173.04:12:17.88#ibcon#enter sib2, iclass 32, count 0 2006.173.04:12:17.88#ibcon#flushed, iclass 32, count 0 2006.173.04:12:17.88#ibcon#about to write, iclass 32, count 0 2006.173.04:12:17.88#ibcon#wrote, iclass 32, count 0 2006.173.04:12:17.88#ibcon#about to read 3, iclass 32, count 0 2006.173.04:12:17.90#ibcon#read 3, iclass 32, count 0 2006.173.04:12:17.90#ibcon#about to read 4, iclass 32, count 0 2006.173.04:12:17.90#ibcon#read 4, iclass 32, count 0 2006.173.04:12:17.90#ibcon#about to read 5, iclass 32, count 0 2006.173.04:12:17.90#ibcon#read 5, iclass 32, count 0 2006.173.04:12:17.90#ibcon#about to read 6, iclass 32, count 0 2006.173.04:12:17.90#ibcon#read 6, iclass 32, count 0 2006.173.04:12:17.90#ibcon#end of sib2, iclass 32, count 0 2006.173.04:12:17.90#ibcon#*mode == 0, iclass 32, count 0 2006.173.04:12:17.90#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.04:12:17.90#ibcon#[27=USB\r\n] 2006.173.04:12:17.90#ibcon#*before write, iclass 32, count 0 2006.173.04:12:17.90#ibcon#enter sib2, iclass 32, count 0 2006.173.04:12:17.90#ibcon#flushed, iclass 32, count 0 2006.173.04:12:17.90#ibcon#about to write, iclass 32, count 0 2006.173.04:12:17.90#ibcon#wrote, iclass 32, count 0 2006.173.04:12:17.90#ibcon#about to read 3, iclass 32, count 0 2006.173.04:12:17.93#ibcon#read 3, iclass 32, count 0 2006.173.04:12:17.93#ibcon#about to read 4, iclass 32, count 0 2006.173.04:12:17.93#ibcon#read 4, iclass 32, count 0 2006.173.04:12:17.93#ibcon#about to read 5, iclass 32, count 0 2006.173.04:12:17.93#ibcon#read 5, iclass 32, count 0 2006.173.04:12:17.93#ibcon#about to read 6, iclass 32, count 0 2006.173.04:12:17.93#ibcon#read 6, iclass 32, count 0 2006.173.04:12:17.93#ibcon#end of sib2, iclass 32, count 0 2006.173.04:12:17.93#ibcon#*after write, iclass 32, count 0 2006.173.04:12:17.93#ibcon#*before return 0, iclass 32, count 0 2006.173.04:12:17.93#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.04:12:17.93#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.173.04:12:17.93#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.04:12:17.93#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.04:12:17.93$vck44/vblo=6,719.99 2006.173.04:12:17.93#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.04:12:17.93#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.04:12:17.93#ibcon#ireg 17 cls_cnt 0 2006.173.04:12:17.93#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.04:12:17.93#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.04:12:17.93#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.04:12:17.93#ibcon#enter wrdev, iclass 34, count 0 2006.173.04:12:17.93#ibcon#first serial, iclass 34, count 0 2006.173.04:12:17.93#ibcon#enter sib2, iclass 34, count 0 2006.173.04:12:17.93#ibcon#flushed, iclass 34, count 0 2006.173.04:12:17.93#ibcon#about to write, iclass 34, count 0 2006.173.04:12:17.93#ibcon#wrote, iclass 34, count 0 2006.173.04:12:17.93#ibcon#about to read 3, iclass 34, count 0 2006.173.04:12:17.95#ibcon#read 3, iclass 34, count 0 2006.173.04:12:17.95#ibcon#about to read 4, iclass 34, count 0 2006.173.04:12:17.95#ibcon#read 4, iclass 34, count 0 2006.173.04:12:17.95#ibcon#about to read 5, iclass 34, count 0 2006.173.04:12:17.95#ibcon#read 5, iclass 34, count 0 2006.173.04:12:17.95#ibcon#about to read 6, iclass 34, count 0 2006.173.04:12:17.95#ibcon#read 6, iclass 34, count 0 2006.173.04:12:17.95#ibcon#end of sib2, iclass 34, count 0 2006.173.04:12:17.95#ibcon#*mode == 0, iclass 34, count 0 2006.173.04:12:17.95#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.04:12:17.95#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.04:12:17.95#ibcon#*before write, iclass 34, count 0 2006.173.04:12:17.95#ibcon#enter sib2, iclass 34, count 0 2006.173.04:12:17.95#ibcon#flushed, iclass 34, count 0 2006.173.04:12:17.95#ibcon#about to write, iclass 34, count 0 2006.173.04:12:17.95#ibcon#wrote, iclass 34, count 0 2006.173.04:12:17.95#ibcon#about to read 3, iclass 34, count 0 2006.173.04:12:17.99#ibcon#read 3, iclass 34, count 0 2006.173.04:12:17.99#ibcon#about to read 4, iclass 34, count 0 2006.173.04:12:17.99#ibcon#read 4, iclass 34, count 0 2006.173.04:12:17.99#ibcon#about to read 5, iclass 34, count 0 2006.173.04:12:17.99#ibcon#read 5, iclass 34, count 0 2006.173.04:12:17.99#ibcon#about to read 6, iclass 34, count 0 2006.173.04:12:17.99#ibcon#read 6, iclass 34, count 0 2006.173.04:12:17.99#ibcon#end of sib2, iclass 34, count 0 2006.173.04:12:17.99#ibcon#*after write, iclass 34, count 0 2006.173.04:12:17.99#ibcon#*before return 0, iclass 34, count 0 2006.173.04:12:17.99#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.04:12:17.99#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.04:12:17.99#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.04:12:17.99#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.04:12:17.99$vck44/vb=6,4 2006.173.04:12:17.99#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.04:12:17.99#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.04:12:17.99#ibcon#ireg 11 cls_cnt 2 2006.173.04:12:17.99#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.04:12:18.05#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.04:12:18.05#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.04:12:18.05#ibcon#enter wrdev, iclass 36, count 2 2006.173.04:12:18.05#ibcon#first serial, iclass 36, count 2 2006.173.04:12:18.05#ibcon#enter sib2, iclass 36, count 2 2006.173.04:12:18.05#ibcon#flushed, iclass 36, count 2 2006.173.04:12:18.05#ibcon#about to write, iclass 36, count 2 2006.173.04:12:18.05#ibcon#wrote, iclass 36, count 2 2006.173.04:12:18.05#ibcon#about to read 3, iclass 36, count 2 2006.173.04:12:18.07#ibcon#read 3, iclass 36, count 2 2006.173.04:12:18.07#ibcon#about to read 4, iclass 36, count 2 2006.173.04:12:18.07#ibcon#read 4, iclass 36, count 2 2006.173.04:12:18.07#ibcon#about to read 5, iclass 36, count 2 2006.173.04:12:18.07#ibcon#read 5, iclass 36, count 2 2006.173.04:12:18.07#ibcon#about to read 6, iclass 36, count 2 2006.173.04:12:18.07#ibcon#read 6, iclass 36, count 2 2006.173.04:12:18.07#ibcon#end of sib2, iclass 36, count 2 2006.173.04:12:18.07#ibcon#*mode == 0, iclass 36, count 2 2006.173.04:12:18.07#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.04:12:18.07#ibcon#[27=AT06-04\r\n] 2006.173.04:12:18.07#ibcon#*before write, iclass 36, count 2 2006.173.04:12:18.07#ibcon#enter sib2, iclass 36, count 2 2006.173.04:12:18.07#ibcon#flushed, iclass 36, count 2 2006.173.04:12:18.07#ibcon#about to write, iclass 36, count 2 2006.173.04:12:18.07#ibcon#wrote, iclass 36, count 2 2006.173.04:12:18.07#ibcon#about to read 3, iclass 36, count 2 2006.173.04:12:18.10#ibcon#read 3, iclass 36, count 2 2006.173.04:12:18.10#ibcon#about to read 4, iclass 36, count 2 2006.173.04:12:18.10#ibcon#read 4, iclass 36, count 2 2006.173.04:12:18.10#ibcon#about to read 5, iclass 36, count 2 2006.173.04:12:18.10#ibcon#read 5, iclass 36, count 2 2006.173.04:12:18.10#ibcon#about to read 6, iclass 36, count 2 2006.173.04:12:18.10#ibcon#read 6, iclass 36, count 2 2006.173.04:12:18.10#ibcon#end of sib2, iclass 36, count 2 2006.173.04:12:18.10#ibcon#*after write, iclass 36, count 2 2006.173.04:12:18.10#ibcon#*before return 0, iclass 36, count 2 2006.173.04:12:18.10#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.04:12:18.10#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.04:12:18.10#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.04:12:18.10#ibcon#ireg 7 cls_cnt 0 2006.173.04:12:18.10#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.04:12:18.22#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.04:12:18.22#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.04:12:18.22#ibcon#enter wrdev, iclass 36, count 0 2006.173.04:12:18.22#ibcon#first serial, iclass 36, count 0 2006.173.04:12:18.22#ibcon#enter sib2, iclass 36, count 0 2006.173.04:12:18.22#ibcon#flushed, iclass 36, count 0 2006.173.04:12:18.22#ibcon#about to write, iclass 36, count 0 2006.173.04:12:18.22#ibcon#wrote, iclass 36, count 0 2006.173.04:12:18.22#ibcon#about to read 3, iclass 36, count 0 2006.173.04:12:18.24#ibcon#read 3, iclass 36, count 0 2006.173.04:12:18.24#ibcon#about to read 4, iclass 36, count 0 2006.173.04:12:18.24#ibcon#read 4, iclass 36, count 0 2006.173.04:12:18.24#ibcon#about to read 5, iclass 36, count 0 2006.173.04:12:18.24#ibcon#read 5, iclass 36, count 0 2006.173.04:12:18.24#ibcon#about to read 6, iclass 36, count 0 2006.173.04:12:18.24#ibcon#read 6, iclass 36, count 0 2006.173.04:12:18.24#ibcon#end of sib2, iclass 36, count 0 2006.173.04:12:18.24#ibcon#*mode == 0, iclass 36, count 0 2006.173.04:12:18.24#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.04:12:18.24#ibcon#[27=USB\r\n] 2006.173.04:12:18.24#ibcon#*before write, iclass 36, count 0 2006.173.04:12:18.24#ibcon#enter sib2, iclass 36, count 0 2006.173.04:12:18.24#ibcon#flushed, iclass 36, count 0 2006.173.04:12:18.24#ibcon#about to write, iclass 36, count 0 2006.173.04:12:18.24#ibcon#wrote, iclass 36, count 0 2006.173.04:12:18.24#ibcon#about to read 3, iclass 36, count 0 2006.173.04:12:18.27#ibcon#read 3, iclass 36, count 0 2006.173.04:12:18.27#ibcon#about to read 4, iclass 36, count 0 2006.173.04:12:18.27#ibcon#read 4, iclass 36, count 0 2006.173.04:12:18.27#ibcon#about to read 5, iclass 36, count 0 2006.173.04:12:18.27#ibcon#read 5, iclass 36, count 0 2006.173.04:12:18.27#ibcon#about to read 6, iclass 36, count 0 2006.173.04:12:18.27#ibcon#read 6, iclass 36, count 0 2006.173.04:12:18.27#ibcon#end of sib2, iclass 36, count 0 2006.173.04:12:18.27#ibcon#*after write, iclass 36, count 0 2006.173.04:12:18.27#ibcon#*before return 0, iclass 36, count 0 2006.173.04:12:18.27#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.04:12:18.27#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.04:12:18.27#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.04:12:18.27#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.04:12:18.27$vck44/vblo=7,734.99 2006.173.04:12:18.27#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.04:12:18.27#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.04:12:18.27#ibcon#ireg 17 cls_cnt 0 2006.173.04:12:18.27#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.04:12:18.27#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.04:12:18.27#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.04:12:18.27#ibcon#enter wrdev, iclass 38, count 0 2006.173.04:12:18.27#ibcon#first serial, iclass 38, count 0 2006.173.04:12:18.27#ibcon#enter sib2, iclass 38, count 0 2006.173.04:12:18.27#ibcon#flushed, iclass 38, count 0 2006.173.04:12:18.27#ibcon#about to write, iclass 38, count 0 2006.173.04:12:18.27#ibcon#wrote, iclass 38, count 0 2006.173.04:12:18.27#ibcon#about to read 3, iclass 38, count 0 2006.173.04:12:18.29#ibcon#read 3, iclass 38, count 0 2006.173.04:12:18.29#ibcon#about to read 4, iclass 38, count 0 2006.173.04:12:18.29#ibcon#read 4, iclass 38, count 0 2006.173.04:12:18.29#ibcon#about to read 5, iclass 38, count 0 2006.173.04:12:18.29#ibcon#read 5, iclass 38, count 0 2006.173.04:12:18.29#ibcon#about to read 6, iclass 38, count 0 2006.173.04:12:18.29#ibcon#read 6, iclass 38, count 0 2006.173.04:12:18.29#ibcon#end of sib2, iclass 38, count 0 2006.173.04:12:18.29#ibcon#*mode == 0, iclass 38, count 0 2006.173.04:12:18.29#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.04:12:18.29#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.04:12:18.29#ibcon#*before write, iclass 38, count 0 2006.173.04:12:18.29#ibcon#enter sib2, iclass 38, count 0 2006.173.04:12:18.29#ibcon#flushed, iclass 38, count 0 2006.173.04:12:18.29#ibcon#about to write, iclass 38, count 0 2006.173.04:12:18.29#ibcon#wrote, iclass 38, count 0 2006.173.04:12:18.29#ibcon#about to read 3, iclass 38, count 0 2006.173.04:12:18.33#ibcon#read 3, iclass 38, count 0 2006.173.04:12:18.33#ibcon#about to read 4, iclass 38, count 0 2006.173.04:12:18.33#ibcon#read 4, iclass 38, count 0 2006.173.04:12:18.33#ibcon#about to read 5, iclass 38, count 0 2006.173.04:12:18.33#ibcon#read 5, iclass 38, count 0 2006.173.04:12:18.33#ibcon#about to read 6, iclass 38, count 0 2006.173.04:12:18.33#ibcon#read 6, iclass 38, count 0 2006.173.04:12:18.33#ibcon#end of sib2, iclass 38, count 0 2006.173.04:12:18.33#ibcon#*after write, iclass 38, count 0 2006.173.04:12:18.33#ibcon#*before return 0, iclass 38, count 0 2006.173.04:12:18.33#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.04:12:18.33#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.04:12:18.33#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.04:12:18.33#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.04:12:18.33$vck44/vb=7,4 2006.173.04:12:18.33#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.04:12:18.33#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.04:12:18.33#ibcon#ireg 11 cls_cnt 2 2006.173.04:12:18.33#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.04:12:18.39#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.04:12:18.39#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.04:12:18.39#ibcon#enter wrdev, iclass 40, count 2 2006.173.04:12:18.39#ibcon#first serial, iclass 40, count 2 2006.173.04:12:18.39#ibcon#enter sib2, iclass 40, count 2 2006.173.04:12:18.39#ibcon#flushed, iclass 40, count 2 2006.173.04:12:18.39#ibcon#about to write, iclass 40, count 2 2006.173.04:12:18.39#ibcon#wrote, iclass 40, count 2 2006.173.04:12:18.39#ibcon#about to read 3, iclass 40, count 2 2006.173.04:12:18.41#ibcon#read 3, iclass 40, count 2 2006.173.04:12:18.41#ibcon#about to read 4, iclass 40, count 2 2006.173.04:12:18.41#ibcon#read 4, iclass 40, count 2 2006.173.04:12:18.41#ibcon#about to read 5, iclass 40, count 2 2006.173.04:12:18.41#ibcon#read 5, iclass 40, count 2 2006.173.04:12:18.41#ibcon#about to read 6, iclass 40, count 2 2006.173.04:12:18.41#ibcon#read 6, iclass 40, count 2 2006.173.04:12:18.41#ibcon#end of sib2, iclass 40, count 2 2006.173.04:12:18.41#ibcon#*mode == 0, iclass 40, count 2 2006.173.04:12:18.41#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.04:12:18.41#ibcon#[27=AT07-04\r\n] 2006.173.04:12:18.41#ibcon#*before write, iclass 40, count 2 2006.173.04:12:18.41#ibcon#enter sib2, iclass 40, count 2 2006.173.04:12:18.41#ibcon#flushed, iclass 40, count 2 2006.173.04:12:18.41#ibcon#about to write, iclass 40, count 2 2006.173.04:12:18.41#ibcon#wrote, iclass 40, count 2 2006.173.04:12:18.41#ibcon#about to read 3, iclass 40, count 2 2006.173.04:12:18.44#ibcon#read 3, iclass 40, count 2 2006.173.04:12:18.44#ibcon#about to read 4, iclass 40, count 2 2006.173.04:12:18.44#ibcon#read 4, iclass 40, count 2 2006.173.04:12:18.44#ibcon#about to read 5, iclass 40, count 2 2006.173.04:12:18.44#ibcon#read 5, iclass 40, count 2 2006.173.04:12:18.44#ibcon#about to read 6, iclass 40, count 2 2006.173.04:12:18.44#ibcon#read 6, iclass 40, count 2 2006.173.04:12:18.44#ibcon#end of sib2, iclass 40, count 2 2006.173.04:12:18.44#ibcon#*after write, iclass 40, count 2 2006.173.04:12:18.44#ibcon#*before return 0, iclass 40, count 2 2006.173.04:12:18.44#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.04:12:18.44#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.04:12:18.44#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.04:12:18.44#ibcon#ireg 7 cls_cnt 0 2006.173.04:12:18.44#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.04:12:18.56#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.04:12:18.56#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.04:12:18.56#ibcon#enter wrdev, iclass 40, count 0 2006.173.04:12:18.56#ibcon#first serial, iclass 40, count 0 2006.173.04:12:18.56#ibcon#enter sib2, iclass 40, count 0 2006.173.04:12:18.56#ibcon#flushed, iclass 40, count 0 2006.173.04:12:18.56#ibcon#about to write, iclass 40, count 0 2006.173.04:12:18.56#ibcon#wrote, iclass 40, count 0 2006.173.04:12:18.56#ibcon#about to read 3, iclass 40, count 0 2006.173.04:12:18.58#ibcon#read 3, iclass 40, count 0 2006.173.04:12:18.58#ibcon#about to read 4, iclass 40, count 0 2006.173.04:12:18.58#ibcon#read 4, iclass 40, count 0 2006.173.04:12:18.58#ibcon#about to read 5, iclass 40, count 0 2006.173.04:12:18.58#ibcon#read 5, iclass 40, count 0 2006.173.04:12:18.58#ibcon#about to read 6, iclass 40, count 0 2006.173.04:12:18.58#ibcon#read 6, iclass 40, count 0 2006.173.04:12:18.58#ibcon#end of sib2, iclass 40, count 0 2006.173.04:12:18.58#ibcon#*mode == 0, iclass 40, count 0 2006.173.04:12:18.58#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.04:12:18.58#ibcon#[27=USB\r\n] 2006.173.04:12:18.58#ibcon#*before write, iclass 40, count 0 2006.173.04:12:18.58#ibcon#enter sib2, iclass 40, count 0 2006.173.04:12:18.58#ibcon#flushed, iclass 40, count 0 2006.173.04:12:18.58#ibcon#about to write, iclass 40, count 0 2006.173.04:12:18.58#ibcon#wrote, iclass 40, count 0 2006.173.04:12:18.58#ibcon#about to read 3, iclass 40, count 0 2006.173.04:12:18.61#ibcon#read 3, iclass 40, count 0 2006.173.04:12:18.61#ibcon#about to read 4, iclass 40, count 0 2006.173.04:12:18.61#ibcon#read 4, iclass 40, count 0 2006.173.04:12:18.61#ibcon#about to read 5, iclass 40, count 0 2006.173.04:12:18.61#ibcon#read 5, iclass 40, count 0 2006.173.04:12:18.61#ibcon#about to read 6, iclass 40, count 0 2006.173.04:12:18.61#ibcon#read 6, iclass 40, count 0 2006.173.04:12:18.61#ibcon#end of sib2, iclass 40, count 0 2006.173.04:12:18.61#ibcon#*after write, iclass 40, count 0 2006.173.04:12:18.61#ibcon#*before return 0, iclass 40, count 0 2006.173.04:12:18.61#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.04:12:18.61#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.04:12:18.61#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.04:12:18.61#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.04:12:18.61$vck44/vblo=8,744.99 2006.173.04:12:18.61#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.04:12:18.61#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.04:12:18.61#ibcon#ireg 17 cls_cnt 0 2006.173.04:12:18.61#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.04:12:18.61#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.04:12:18.61#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.04:12:18.61#ibcon#enter wrdev, iclass 4, count 0 2006.173.04:12:18.61#ibcon#first serial, iclass 4, count 0 2006.173.04:12:18.61#ibcon#enter sib2, iclass 4, count 0 2006.173.04:12:18.61#ibcon#flushed, iclass 4, count 0 2006.173.04:12:18.61#ibcon#about to write, iclass 4, count 0 2006.173.04:12:18.61#ibcon#wrote, iclass 4, count 0 2006.173.04:12:18.61#ibcon#about to read 3, iclass 4, count 0 2006.173.04:12:18.63#ibcon#read 3, iclass 4, count 0 2006.173.04:12:18.63#ibcon#about to read 4, iclass 4, count 0 2006.173.04:12:18.63#ibcon#read 4, iclass 4, count 0 2006.173.04:12:18.63#ibcon#about to read 5, iclass 4, count 0 2006.173.04:12:18.63#ibcon#read 5, iclass 4, count 0 2006.173.04:12:18.63#ibcon#about to read 6, iclass 4, count 0 2006.173.04:12:18.63#ibcon#read 6, iclass 4, count 0 2006.173.04:12:18.63#ibcon#end of sib2, iclass 4, count 0 2006.173.04:12:18.63#ibcon#*mode == 0, iclass 4, count 0 2006.173.04:12:18.63#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.04:12:18.63#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.04:12:18.63#ibcon#*before write, iclass 4, count 0 2006.173.04:12:18.63#ibcon#enter sib2, iclass 4, count 0 2006.173.04:12:18.63#ibcon#flushed, iclass 4, count 0 2006.173.04:12:18.63#ibcon#about to write, iclass 4, count 0 2006.173.04:12:18.63#ibcon#wrote, iclass 4, count 0 2006.173.04:12:18.63#ibcon#about to read 3, iclass 4, count 0 2006.173.04:12:18.67#ibcon#read 3, iclass 4, count 0 2006.173.04:12:18.67#ibcon#about to read 4, iclass 4, count 0 2006.173.04:12:18.67#ibcon#read 4, iclass 4, count 0 2006.173.04:12:18.67#ibcon#about to read 5, iclass 4, count 0 2006.173.04:12:18.67#ibcon#read 5, iclass 4, count 0 2006.173.04:12:18.67#ibcon#about to read 6, iclass 4, count 0 2006.173.04:12:18.67#ibcon#read 6, iclass 4, count 0 2006.173.04:12:18.67#ibcon#end of sib2, iclass 4, count 0 2006.173.04:12:18.67#ibcon#*after write, iclass 4, count 0 2006.173.04:12:18.67#ibcon#*before return 0, iclass 4, count 0 2006.173.04:12:18.67#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.04:12:18.67#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.04:12:18.67#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.04:12:18.67#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.04:12:18.67$vck44/vb=8,4 2006.173.04:12:18.67#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.04:12:18.67#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.04:12:18.67#ibcon#ireg 11 cls_cnt 2 2006.173.04:12:18.67#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.04:12:18.73#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.04:12:18.73#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.04:12:18.73#ibcon#enter wrdev, iclass 6, count 2 2006.173.04:12:18.73#ibcon#first serial, iclass 6, count 2 2006.173.04:12:18.73#ibcon#enter sib2, iclass 6, count 2 2006.173.04:12:18.73#ibcon#flushed, iclass 6, count 2 2006.173.04:12:18.73#ibcon#about to write, iclass 6, count 2 2006.173.04:12:18.73#ibcon#wrote, iclass 6, count 2 2006.173.04:12:18.73#ibcon#about to read 3, iclass 6, count 2 2006.173.04:12:18.75#ibcon#read 3, iclass 6, count 2 2006.173.04:12:18.75#ibcon#about to read 4, iclass 6, count 2 2006.173.04:12:18.75#ibcon#read 4, iclass 6, count 2 2006.173.04:12:18.75#ibcon#about to read 5, iclass 6, count 2 2006.173.04:12:18.75#ibcon#read 5, iclass 6, count 2 2006.173.04:12:18.75#ibcon#about to read 6, iclass 6, count 2 2006.173.04:12:18.75#ibcon#read 6, iclass 6, count 2 2006.173.04:12:18.75#ibcon#end of sib2, iclass 6, count 2 2006.173.04:12:18.75#ibcon#*mode == 0, iclass 6, count 2 2006.173.04:12:18.75#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.04:12:18.75#ibcon#[27=AT08-04\r\n] 2006.173.04:12:18.75#ibcon#*before write, iclass 6, count 2 2006.173.04:12:18.75#ibcon#enter sib2, iclass 6, count 2 2006.173.04:12:18.75#ibcon#flushed, iclass 6, count 2 2006.173.04:12:18.75#ibcon#about to write, iclass 6, count 2 2006.173.04:12:18.75#ibcon#wrote, iclass 6, count 2 2006.173.04:12:18.75#ibcon#about to read 3, iclass 6, count 2 2006.173.04:12:18.78#ibcon#read 3, iclass 6, count 2 2006.173.04:12:18.78#ibcon#about to read 4, iclass 6, count 2 2006.173.04:12:18.78#ibcon#read 4, iclass 6, count 2 2006.173.04:12:18.78#ibcon#about to read 5, iclass 6, count 2 2006.173.04:12:18.78#ibcon#read 5, iclass 6, count 2 2006.173.04:12:18.78#ibcon#about to read 6, iclass 6, count 2 2006.173.04:12:18.78#ibcon#read 6, iclass 6, count 2 2006.173.04:12:18.78#ibcon#end of sib2, iclass 6, count 2 2006.173.04:12:18.78#ibcon#*after write, iclass 6, count 2 2006.173.04:12:18.78#ibcon#*before return 0, iclass 6, count 2 2006.173.04:12:18.78#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.04:12:18.78#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.04:12:18.78#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.04:12:18.78#ibcon#ireg 7 cls_cnt 0 2006.173.04:12:18.78#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.04:12:18.90#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.04:12:18.90#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.04:12:18.90#ibcon#enter wrdev, iclass 6, count 0 2006.173.04:12:18.90#ibcon#first serial, iclass 6, count 0 2006.173.04:12:18.90#ibcon#enter sib2, iclass 6, count 0 2006.173.04:12:18.90#ibcon#flushed, iclass 6, count 0 2006.173.04:12:18.90#ibcon#about to write, iclass 6, count 0 2006.173.04:12:18.90#ibcon#wrote, iclass 6, count 0 2006.173.04:12:18.90#ibcon#about to read 3, iclass 6, count 0 2006.173.04:12:18.92#ibcon#read 3, iclass 6, count 0 2006.173.04:12:18.92#ibcon#about to read 4, iclass 6, count 0 2006.173.04:12:18.92#ibcon#read 4, iclass 6, count 0 2006.173.04:12:18.92#ibcon#about to read 5, iclass 6, count 0 2006.173.04:12:18.92#ibcon#read 5, iclass 6, count 0 2006.173.04:12:18.92#ibcon#about to read 6, iclass 6, count 0 2006.173.04:12:18.92#ibcon#read 6, iclass 6, count 0 2006.173.04:12:18.92#ibcon#end of sib2, iclass 6, count 0 2006.173.04:12:18.92#ibcon#*mode == 0, iclass 6, count 0 2006.173.04:12:18.92#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.04:12:18.92#ibcon#[27=USB\r\n] 2006.173.04:12:18.92#ibcon#*before write, iclass 6, count 0 2006.173.04:12:18.92#ibcon#enter sib2, iclass 6, count 0 2006.173.04:12:18.92#ibcon#flushed, iclass 6, count 0 2006.173.04:12:18.92#ibcon#about to write, iclass 6, count 0 2006.173.04:12:18.92#ibcon#wrote, iclass 6, count 0 2006.173.04:12:18.92#ibcon#about to read 3, iclass 6, count 0 2006.173.04:12:18.95#ibcon#read 3, iclass 6, count 0 2006.173.04:12:18.95#ibcon#about to read 4, iclass 6, count 0 2006.173.04:12:18.95#ibcon#read 4, iclass 6, count 0 2006.173.04:12:18.95#ibcon#about to read 5, iclass 6, count 0 2006.173.04:12:18.95#ibcon#read 5, iclass 6, count 0 2006.173.04:12:18.95#ibcon#about to read 6, iclass 6, count 0 2006.173.04:12:18.95#ibcon#read 6, iclass 6, count 0 2006.173.04:12:18.95#ibcon#end of sib2, iclass 6, count 0 2006.173.04:12:18.95#ibcon#*after write, iclass 6, count 0 2006.173.04:12:18.95#ibcon#*before return 0, iclass 6, count 0 2006.173.04:12:18.95#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.04:12:18.95#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.04:12:18.95#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.04:12:18.95#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.04:12:18.95$vck44/vabw=wide 2006.173.04:12:18.95#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.04:12:18.95#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.04:12:18.95#ibcon#ireg 8 cls_cnt 0 2006.173.04:12:18.95#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.04:12:18.95#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.04:12:18.95#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.04:12:18.95#ibcon#enter wrdev, iclass 10, count 0 2006.173.04:12:18.95#ibcon#first serial, iclass 10, count 0 2006.173.04:12:18.95#ibcon#enter sib2, iclass 10, count 0 2006.173.04:12:18.95#ibcon#flushed, iclass 10, count 0 2006.173.04:12:18.95#ibcon#about to write, iclass 10, count 0 2006.173.04:12:18.95#ibcon#wrote, iclass 10, count 0 2006.173.04:12:18.95#ibcon#about to read 3, iclass 10, count 0 2006.173.04:12:18.97#ibcon#read 3, iclass 10, count 0 2006.173.04:12:18.97#ibcon#about to read 4, iclass 10, count 0 2006.173.04:12:18.97#ibcon#read 4, iclass 10, count 0 2006.173.04:12:18.97#ibcon#about to read 5, iclass 10, count 0 2006.173.04:12:18.97#ibcon#read 5, iclass 10, count 0 2006.173.04:12:18.97#ibcon#about to read 6, iclass 10, count 0 2006.173.04:12:18.97#ibcon#read 6, iclass 10, count 0 2006.173.04:12:18.97#ibcon#end of sib2, iclass 10, count 0 2006.173.04:12:18.97#ibcon#*mode == 0, iclass 10, count 0 2006.173.04:12:18.97#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.04:12:18.97#ibcon#[25=BW32\r\n] 2006.173.04:12:18.97#ibcon#*before write, iclass 10, count 0 2006.173.04:12:18.97#ibcon#enter sib2, iclass 10, count 0 2006.173.04:12:18.97#ibcon#flushed, iclass 10, count 0 2006.173.04:12:18.97#ibcon#about to write, iclass 10, count 0 2006.173.04:12:18.97#ibcon#wrote, iclass 10, count 0 2006.173.04:12:18.97#ibcon#about to read 3, iclass 10, count 0 2006.173.04:12:19.00#ibcon#read 3, iclass 10, count 0 2006.173.04:12:19.00#ibcon#about to read 4, iclass 10, count 0 2006.173.04:12:19.00#ibcon#read 4, iclass 10, count 0 2006.173.04:12:19.00#ibcon#about to read 5, iclass 10, count 0 2006.173.04:12:19.00#ibcon#read 5, iclass 10, count 0 2006.173.04:12:19.00#ibcon#about to read 6, iclass 10, count 0 2006.173.04:12:19.00#ibcon#read 6, iclass 10, count 0 2006.173.04:12:19.00#ibcon#end of sib2, iclass 10, count 0 2006.173.04:12:19.00#ibcon#*after write, iclass 10, count 0 2006.173.04:12:19.00#ibcon#*before return 0, iclass 10, count 0 2006.173.04:12:19.00#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.04:12:19.00#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.04:12:19.00#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.04:12:19.00#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.04:12:19.00$vck44/vbbw=wide 2006.173.04:12:19.00#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.04:12:19.00#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.04:12:19.00#ibcon#ireg 8 cls_cnt 0 2006.173.04:12:19.00#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.04:12:19.07#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.04:12:19.07#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.04:12:19.07#ibcon#enter wrdev, iclass 12, count 0 2006.173.04:12:19.07#ibcon#first serial, iclass 12, count 0 2006.173.04:12:19.07#ibcon#enter sib2, iclass 12, count 0 2006.173.04:12:19.07#ibcon#flushed, iclass 12, count 0 2006.173.04:12:19.07#ibcon#about to write, iclass 12, count 0 2006.173.04:12:19.07#ibcon#wrote, iclass 12, count 0 2006.173.04:12:19.07#ibcon#about to read 3, iclass 12, count 0 2006.173.04:12:19.09#ibcon#read 3, iclass 12, count 0 2006.173.04:12:19.09#ibcon#about to read 4, iclass 12, count 0 2006.173.04:12:19.09#ibcon#read 4, iclass 12, count 0 2006.173.04:12:19.09#ibcon#about to read 5, iclass 12, count 0 2006.173.04:12:19.09#ibcon#read 5, iclass 12, count 0 2006.173.04:12:19.09#ibcon#about to read 6, iclass 12, count 0 2006.173.04:12:19.09#ibcon#read 6, iclass 12, count 0 2006.173.04:12:19.09#ibcon#end of sib2, iclass 12, count 0 2006.173.04:12:19.09#ibcon#*mode == 0, iclass 12, count 0 2006.173.04:12:19.09#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.04:12:19.09#ibcon#[27=BW32\r\n] 2006.173.04:12:19.09#ibcon#*before write, iclass 12, count 0 2006.173.04:12:19.09#ibcon#enter sib2, iclass 12, count 0 2006.173.04:12:19.09#ibcon#flushed, iclass 12, count 0 2006.173.04:12:19.09#ibcon#about to write, iclass 12, count 0 2006.173.04:12:19.09#ibcon#wrote, iclass 12, count 0 2006.173.04:12:19.09#ibcon#about to read 3, iclass 12, count 0 2006.173.04:12:19.12#ibcon#read 3, iclass 12, count 0 2006.173.04:12:19.12#ibcon#about to read 4, iclass 12, count 0 2006.173.04:12:19.12#ibcon#read 4, iclass 12, count 0 2006.173.04:12:19.12#ibcon#about to read 5, iclass 12, count 0 2006.173.04:12:19.12#ibcon#read 5, iclass 12, count 0 2006.173.04:12:19.12#ibcon#about to read 6, iclass 12, count 0 2006.173.04:12:19.12#ibcon#read 6, iclass 12, count 0 2006.173.04:12:19.12#ibcon#end of sib2, iclass 12, count 0 2006.173.04:12:19.12#ibcon#*after write, iclass 12, count 0 2006.173.04:12:19.12#ibcon#*before return 0, iclass 12, count 0 2006.173.04:12:19.12#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.04:12:19.12#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.04:12:19.12#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.04:12:19.12#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.04:12:19.12$setupk4/ifdk4 2006.173.04:12:19.12$ifdk4/lo= 2006.173.04:12:19.12$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.04:12:19.12$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.04:12:19.12$ifdk4/patch= 2006.173.04:12:19.12$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.04:12:19.12$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.04:12:19.12$setupk4/!*+20s 2006.173.04:12:24.70#abcon#<5=/15 1.1 2.6 23.04 801005.9\r\n> 2006.173.04:12:24.72#abcon#{5=INTERFACE CLEAR} 2006.173.04:12:24.78#abcon#[5=S1D000X0/0*\r\n] 2006.173.04:12:33.62$setupk4/"tpicd 2006.173.04:12:33.62$setupk4/echo=off 2006.173.04:12:33.62$setupk4/xlog=off 2006.173.04:12:33.62:!2006.173.04:21:50 2006.173.04:12:48.14#trakl#Source acquired 2006.173.04:12:49.14#flagr#flagr/antenna,acquired 2006.173.04:21:50.00:preob 2006.173.04:21:50.14/onsource/TRACKING 2006.173.04:21:50.14:!2006.173.04:22:00 2006.173.04:22:00.00:"tape 2006.173.04:22:00.00:"st=record 2006.173.04:22:00.00:data_valid=on 2006.173.04:22:00.00:midob 2006.173.04:22:01.14/onsource/TRACKING 2006.173.04:22:01.14/wx/23.20,1005.9,78 2006.173.04:22:01.32/cable/+6.5072E-03 2006.173.04:22:02.41/va/01,07,usb,yes,40,43 2006.173.04:22:02.41/va/02,06,usb,yes,40,41 2006.173.04:22:02.41/va/03,05,usb,yes,50,52 2006.173.04:22:02.41/va/04,06,usb,yes,40,43 2006.173.04:22:02.41/va/05,04,usb,yes,32,33 2006.173.04:22:02.41/va/06,03,usb,yes,44,44 2006.173.04:22:02.41/va/07,04,usb,yes,36,37 2006.173.04:22:02.41/va/08,04,usb,yes,31,37 2006.173.04:22:02.64/valo/01,524.99,yes,locked 2006.173.04:22:02.64/valo/02,534.99,yes,locked 2006.173.04:22:02.64/valo/03,564.99,yes,locked 2006.173.04:22:02.64/valo/04,624.99,yes,locked 2006.173.04:22:02.64/valo/05,734.99,yes,locked 2006.173.04:22:02.64/valo/06,814.99,yes,locked 2006.173.04:22:02.64/valo/07,864.99,yes,locked 2006.173.04:22:02.64/valo/08,884.99,yes,locked 2006.173.04:22:03.73/vb/01,04,usb,yes,36,34 2006.173.04:22:03.73/vb/02,04,usb,yes,39,39 2006.173.04:22:03.73/vb/03,04,usb,yes,36,39 2006.173.04:22:03.73/vb/04,04,usb,yes,40,39 2006.173.04:22:03.73/vb/05,04,usb,yes,32,35 2006.173.04:22:03.73/vb/06,04,usb,yes,37,33 2006.173.04:22:03.73/vb/07,04,usb,yes,37,37 2006.173.04:22:03.73/vb/08,04,usb,yes,34,38 2006.173.04:22:03.97/vblo/01,629.99,yes,locked 2006.173.04:22:03.97/vblo/02,634.99,yes,locked 2006.173.04:22:03.97/vblo/03,649.99,yes,locked 2006.173.04:22:03.97/vblo/04,679.99,yes,locked 2006.173.04:22:03.97/vblo/05,709.99,yes,locked 2006.173.04:22:03.97/vblo/06,719.99,yes,locked 2006.173.04:22:03.97/vblo/07,734.99,yes,locked 2006.173.04:22:03.97/vblo/08,744.99,yes,locked 2006.173.04:22:04.12/vabw/8 2006.173.04:22:04.27/vbbw/8 2006.173.04:22:04.36/xfe/off,on,15.2 2006.173.04:22:04.74/ifatt/23,28,28,28 2006.173.04:22:05.07/fmout-gps/S +3.94E-07 2006.173.04:22:05.11:!2006.173.04:23:50 2006.173.04:23:50.00:data_valid=off 2006.173.04:23:50.00:"et 2006.173.04:23:50.00:!+3s 2006.173.04:23:53.01:"tape 2006.173.04:23:53.01:postob 2006.173.04:23:53.24/cable/+6.5071E-03 2006.173.04:23:53.24/wx/23.23,1006.0,79 2006.173.04:23:54.07/fmout-gps/S +3.93E-07 2006.173.04:23:54.07:scan_name=173-0430,jd0606,60 2006.173.04:23:54.07:source=0727-115,073019.11,-114112.6,2000.0,cw 2006.173.04:23:55.13#flagr#flagr/antenna,new-source 2006.173.04:23:55.13:checkk5 2006.173.04:23:55.49/chk_autoobs//k5ts1/ autoobs is running! 2006.173.04:23:55.84/chk_autoobs//k5ts2/ autoobs is running! 2006.173.04:23:56.20/chk_autoobs//k5ts3/ autoobs is running! 2006.173.04:23:56.54/chk_autoobs//k5ts4/ autoobs is running! 2006.173.04:23:56.88/chk_obsdata//k5ts1/T1730422??a.dat file size is correct (nominal:440MB, actual:436MB). 2006.173.04:23:57.23/chk_obsdata//k5ts2/T1730422??b.dat file size is correct (nominal:440MB, actual:436MB). 2006.173.04:23:57.57/chk_obsdata//k5ts3/T1730422??c.dat file size is correct (nominal:440MB, actual:436MB). 2006.173.04:23:57.91/chk_obsdata//k5ts4/T1730422??d.dat file size is correct (nominal:440MB, actual:436MB). 2006.173.04:23:58.58/k5log//k5ts1_log_newline 2006.173.04:23:59.24/k5log//k5ts2_log_newline 2006.173.04:23:59.89/k5log//k5ts3_log_newline 2006.173.04:24:00.55/k5log//k5ts4_log_newline 2006.173.04:24:00.57/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.04:24:00.57:setupk4=1 2006.173.04:24:00.58$setupk4/echo=on 2006.173.04:24:00.58$setupk4/pcalon 2006.173.04:24:00.58$pcalon/"no phase cal control is implemented here 2006.173.04:24:00.58$setupk4/"tpicd=stop 2006.173.04:24:00.58$setupk4/"rec=synch_on 2006.173.04:24:00.58$setupk4/"rec_mode=128 2006.173.04:24:00.58$setupk4/!* 2006.173.04:24:00.58$setupk4/recpk4 2006.173.04:24:00.58$recpk4/recpatch= 2006.173.04:24:00.58$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.04:24:00.58$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.04:24:00.58$setupk4/vck44 2006.173.04:24:00.58$vck44/valo=1,524.99 2006.173.04:24:00.58#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.04:24:00.58#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.04:24:00.58#ibcon#ireg 17 cls_cnt 0 2006.173.04:24:00.58#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.04:24:00.58#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.04:24:00.58#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.04:24:00.58#ibcon#enter wrdev, iclass 3, count 0 2006.173.04:24:00.58#ibcon#first serial, iclass 3, count 0 2006.173.04:24:00.58#ibcon#enter sib2, iclass 3, count 0 2006.173.04:24:00.58#ibcon#flushed, iclass 3, count 0 2006.173.04:24:00.58#ibcon#about to write, iclass 3, count 0 2006.173.04:24:00.58#ibcon#wrote, iclass 3, count 0 2006.173.04:24:00.58#ibcon#about to read 3, iclass 3, count 0 2006.173.04:24:00.60#ibcon#read 3, iclass 3, count 0 2006.173.04:24:00.60#ibcon#about to read 4, iclass 3, count 0 2006.173.04:24:00.60#ibcon#read 4, iclass 3, count 0 2006.173.04:24:00.60#ibcon#about to read 5, iclass 3, count 0 2006.173.04:24:00.60#ibcon#read 5, iclass 3, count 0 2006.173.04:24:00.60#ibcon#about to read 6, iclass 3, count 0 2006.173.04:24:00.60#ibcon#read 6, iclass 3, count 0 2006.173.04:24:00.60#ibcon#end of sib2, iclass 3, count 0 2006.173.04:24:00.60#ibcon#*mode == 0, iclass 3, count 0 2006.173.04:24:00.60#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.04:24:00.60#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.04:24:00.60#ibcon#*before write, iclass 3, count 0 2006.173.04:24:00.60#ibcon#enter sib2, iclass 3, count 0 2006.173.04:24:00.60#ibcon#flushed, iclass 3, count 0 2006.173.04:24:00.60#ibcon#about to write, iclass 3, count 0 2006.173.04:24:00.60#ibcon#wrote, iclass 3, count 0 2006.173.04:24:00.60#ibcon#about to read 3, iclass 3, count 0 2006.173.04:24:00.65#ibcon#read 3, iclass 3, count 0 2006.173.04:24:00.65#ibcon#about to read 4, iclass 3, count 0 2006.173.04:24:00.65#ibcon#read 4, iclass 3, count 0 2006.173.04:24:00.65#ibcon#about to read 5, iclass 3, count 0 2006.173.04:24:00.65#ibcon#read 5, iclass 3, count 0 2006.173.04:24:00.65#ibcon#about to read 6, iclass 3, count 0 2006.173.04:24:00.65#ibcon#read 6, iclass 3, count 0 2006.173.04:24:00.65#ibcon#end of sib2, iclass 3, count 0 2006.173.04:24:00.65#ibcon#*after write, iclass 3, count 0 2006.173.04:24:00.65#ibcon#*before return 0, iclass 3, count 0 2006.173.04:24:00.65#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.04:24:00.65#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.04:24:00.65#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.04:24:00.65#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.04:24:00.65$vck44/va=1,7 2006.173.04:24:00.65#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.04:24:00.65#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.04:24:00.65#ibcon#ireg 11 cls_cnt 2 2006.173.04:24:00.65#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.04:24:00.65#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.04:24:00.65#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.04:24:00.65#ibcon#enter wrdev, iclass 5, count 2 2006.173.04:24:00.65#ibcon#first serial, iclass 5, count 2 2006.173.04:24:00.65#ibcon#enter sib2, iclass 5, count 2 2006.173.04:24:00.65#ibcon#flushed, iclass 5, count 2 2006.173.04:24:00.65#ibcon#about to write, iclass 5, count 2 2006.173.04:24:00.65#ibcon#wrote, iclass 5, count 2 2006.173.04:24:00.65#ibcon#about to read 3, iclass 5, count 2 2006.173.04:24:00.67#ibcon#read 3, iclass 5, count 2 2006.173.04:24:00.67#ibcon#about to read 4, iclass 5, count 2 2006.173.04:24:00.67#ibcon#read 4, iclass 5, count 2 2006.173.04:24:00.67#ibcon#about to read 5, iclass 5, count 2 2006.173.04:24:00.67#ibcon#read 5, iclass 5, count 2 2006.173.04:24:00.67#ibcon#about to read 6, iclass 5, count 2 2006.173.04:24:00.67#ibcon#read 6, iclass 5, count 2 2006.173.04:24:00.67#ibcon#end of sib2, iclass 5, count 2 2006.173.04:24:00.67#ibcon#*mode == 0, iclass 5, count 2 2006.173.04:24:00.67#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.04:24:00.67#ibcon#[25=AT01-07\r\n] 2006.173.04:24:00.67#ibcon#*before write, iclass 5, count 2 2006.173.04:24:00.67#ibcon#enter sib2, iclass 5, count 2 2006.173.04:24:00.67#ibcon#flushed, iclass 5, count 2 2006.173.04:24:00.67#ibcon#about to write, iclass 5, count 2 2006.173.04:24:00.67#ibcon#wrote, iclass 5, count 2 2006.173.04:24:00.67#ibcon#about to read 3, iclass 5, count 2 2006.173.04:24:00.70#ibcon#read 3, iclass 5, count 2 2006.173.04:24:00.70#ibcon#about to read 4, iclass 5, count 2 2006.173.04:24:00.70#ibcon#read 4, iclass 5, count 2 2006.173.04:24:00.70#ibcon#about to read 5, iclass 5, count 2 2006.173.04:24:00.70#ibcon#read 5, iclass 5, count 2 2006.173.04:24:00.70#ibcon#about to read 6, iclass 5, count 2 2006.173.04:24:00.70#ibcon#read 6, iclass 5, count 2 2006.173.04:24:00.70#ibcon#end of sib2, iclass 5, count 2 2006.173.04:24:00.70#ibcon#*after write, iclass 5, count 2 2006.173.04:24:00.70#ibcon#*before return 0, iclass 5, count 2 2006.173.04:24:00.70#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.04:24:00.70#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.04:24:00.70#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.04:24:00.70#ibcon#ireg 7 cls_cnt 0 2006.173.04:24:00.70#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.04:24:00.82#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.04:24:00.82#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.04:24:00.82#ibcon#enter wrdev, iclass 5, count 0 2006.173.04:24:00.82#ibcon#first serial, iclass 5, count 0 2006.173.04:24:00.82#ibcon#enter sib2, iclass 5, count 0 2006.173.04:24:00.82#ibcon#flushed, iclass 5, count 0 2006.173.04:24:00.82#ibcon#about to write, iclass 5, count 0 2006.173.04:24:00.82#ibcon#wrote, iclass 5, count 0 2006.173.04:24:00.82#ibcon#about to read 3, iclass 5, count 0 2006.173.04:24:00.84#ibcon#read 3, iclass 5, count 0 2006.173.04:24:00.84#ibcon#about to read 4, iclass 5, count 0 2006.173.04:24:00.84#ibcon#read 4, iclass 5, count 0 2006.173.04:24:00.84#ibcon#about to read 5, iclass 5, count 0 2006.173.04:24:00.84#ibcon#read 5, iclass 5, count 0 2006.173.04:24:00.84#ibcon#about to read 6, iclass 5, count 0 2006.173.04:24:00.84#ibcon#read 6, iclass 5, count 0 2006.173.04:24:00.84#ibcon#end of sib2, iclass 5, count 0 2006.173.04:24:00.84#ibcon#*mode == 0, iclass 5, count 0 2006.173.04:24:00.84#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.04:24:00.84#ibcon#[25=USB\r\n] 2006.173.04:24:00.84#ibcon#*before write, iclass 5, count 0 2006.173.04:24:00.84#ibcon#enter sib2, iclass 5, count 0 2006.173.04:24:00.84#ibcon#flushed, iclass 5, count 0 2006.173.04:24:00.84#ibcon#about to write, iclass 5, count 0 2006.173.04:24:00.84#ibcon#wrote, iclass 5, count 0 2006.173.04:24:00.84#ibcon#about to read 3, iclass 5, count 0 2006.173.04:24:00.87#ibcon#read 3, iclass 5, count 0 2006.173.04:24:00.87#ibcon#about to read 4, iclass 5, count 0 2006.173.04:24:00.87#ibcon#read 4, iclass 5, count 0 2006.173.04:24:00.87#ibcon#about to read 5, iclass 5, count 0 2006.173.04:24:00.87#ibcon#read 5, iclass 5, count 0 2006.173.04:24:00.87#ibcon#about to read 6, iclass 5, count 0 2006.173.04:24:00.87#ibcon#read 6, iclass 5, count 0 2006.173.04:24:00.87#ibcon#end of sib2, iclass 5, count 0 2006.173.04:24:00.87#ibcon#*after write, iclass 5, count 0 2006.173.04:24:00.87#ibcon#*before return 0, iclass 5, count 0 2006.173.04:24:00.87#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.04:24:00.87#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.04:24:00.87#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.04:24:00.87#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.04:24:00.87$vck44/valo=2,534.99 2006.173.04:24:00.87#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.04:24:00.87#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.04:24:00.87#ibcon#ireg 17 cls_cnt 0 2006.173.04:24:00.87#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.04:24:00.87#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.04:24:00.87#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.04:24:00.87#ibcon#enter wrdev, iclass 7, count 0 2006.173.04:24:00.87#ibcon#first serial, iclass 7, count 0 2006.173.04:24:00.87#ibcon#enter sib2, iclass 7, count 0 2006.173.04:24:00.87#ibcon#flushed, iclass 7, count 0 2006.173.04:24:00.87#ibcon#about to write, iclass 7, count 0 2006.173.04:24:00.87#ibcon#wrote, iclass 7, count 0 2006.173.04:24:00.87#ibcon#about to read 3, iclass 7, count 0 2006.173.04:24:00.89#ibcon#read 3, iclass 7, count 0 2006.173.04:24:00.89#ibcon#about to read 4, iclass 7, count 0 2006.173.04:24:00.89#ibcon#read 4, iclass 7, count 0 2006.173.04:24:00.89#ibcon#about to read 5, iclass 7, count 0 2006.173.04:24:00.89#ibcon#read 5, iclass 7, count 0 2006.173.04:24:00.89#ibcon#about to read 6, iclass 7, count 0 2006.173.04:24:00.89#ibcon#read 6, iclass 7, count 0 2006.173.04:24:00.89#ibcon#end of sib2, iclass 7, count 0 2006.173.04:24:00.89#ibcon#*mode == 0, iclass 7, count 0 2006.173.04:24:00.89#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.04:24:00.89#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.04:24:00.89#ibcon#*before write, iclass 7, count 0 2006.173.04:24:00.89#ibcon#enter sib2, iclass 7, count 0 2006.173.04:24:00.89#ibcon#flushed, iclass 7, count 0 2006.173.04:24:00.89#ibcon#about to write, iclass 7, count 0 2006.173.04:24:00.89#ibcon#wrote, iclass 7, count 0 2006.173.04:24:00.89#ibcon#about to read 3, iclass 7, count 0 2006.173.04:24:00.93#ibcon#read 3, iclass 7, count 0 2006.173.04:24:00.93#ibcon#about to read 4, iclass 7, count 0 2006.173.04:24:00.93#ibcon#read 4, iclass 7, count 0 2006.173.04:24:00.93#ibcon#about to read 5, iclass 7, count 0 2006.173.04:24:00.93#ibcon#read 5, iclass 7, count 0 2006.173.04:24:00.93#ibcon#about to read 6, iclass 7, count 0 2006.173.04:24:00.93#ibcon#read 6, iclass 7, count 0 2006.173.04:24:00.93#ibcon#end of sib2, iclass 7, count 0 2006.173.04:24:00.93#ibcon#*after write, iclass 7, count 0 2006.173.04:24:00.93#ibcon#*before return 0, iclass 7, count 0 2006.173.04:24:00.93#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.04:24:00.93#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.04:24:00.93#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.04:24:00.93#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.04:24:00.93$vck44/va=2,6 2006.173.04:24:00.93#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.04:24:00.93#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.04:24:00.93#ibcon#ireg 11 cls_cnt 2 2006.173.04:24:00.93#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.04:24:00.99#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.04:24:00.99#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.04:24:00.99#ibcon#enter wrdev, iclass 11, count 2 2006.173.04:24:00.99#ibcon#first serial, iclass 11, count 2 2006.173.04:24:00.99#ibcon#enter sib2, iclass 11, count 2 2006.173.04:24:00.99#ibcon#flushed, iclass 11, count 2 2006.173.04:24:00.99#ibcon#about to write, iclass 11, count 2 2006.173.04:24:00.99#ibcon#wrote, iclass 11, count 2 2006.173.04:24:00.99#ibcon#about to read 3, iclass 11, count 2 2006.173.04:24:01.01#ibcon#read 3, iclass 11, count 2 2006.173.04:24:01.01#ibcon#about to read 4, iclass 11, count 2 2006.173.04:24:01.01#ibcon#read 4, iclass 11, count 2 2006.173.04:24:01.01#ibcon#about to read 5, iclass 11, count 2 2006.173.04:24:01.01#ibcon#read 5, iclass 11, count 2 2006.173.04:24:01.01#ibcon#about to read 6, iclass 11, count 2 2006.173.04:24:01.01#ibcon#read 6, iclass 11, count 2 2006.173.04:24:01.01#ibcon#end of sib2, iclass 11, count 2 2006.173.04:24:01.01#ibcon#*mode == 0, iclass 11, count 2 2006.173.04:24:01.01#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.04:24:01.01#ibcon#[25=AT02-06\r\n] 2006.173.04:24:01.01#ibcon#*before write, iclass 11, count 2 2006.173.04:24:01.01#ibcon#enter sib2, iclass 11, count 2 2006.173.04:24:01.01#ibcon#flushed, iclass 11, count 2 2006.173.04:24:01.01#ibcon#about to write, iclass 11, count 2 2006.173.04:24:01.01#ibcon#wrote, iclass 11, count 2 2006.173.04:24:01.01#ibcon#about to read 3, iclass 11, count 2 2006.173.04:24:01.04#ibcon#read 3, iclass 11, count 2 2006.173.04:24:01.04#ibcon#about to read 4, iclass 11, count 2 2006.173.04:24:01.04#ibcon#read 4, iclass 11, count 2 2006.173.04:24:01.04#ibcon#about to read 5, iclass 11, count 2 2006.173.04:24:01.04#ibcon#read 5, iclass 11, count 2 2006.173.04:24:01.04#ibcon#about to read 6, iclass 11, count 2 2006.173.04:24:01.04#ibcon#read 6, iclass 11, count 2 2006.173.04:24:01.04#ibcon#end of sib2, iclass 11, count 2 2006.173.04:24:01.04#ibcon#*after write, iclass 11, count 2 2006.173.04:24:01.04#ibcon#*before return 0, iclass 11, count 2 2006.173.04:24:01.04#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.04:24:01.04#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.04:24:01.04#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.04:24:01.04#ibcon#ireg 7 cls_cnt 0 2006.173.04:24:01.04#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.04:24:01.16#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.04:24:01.16#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.04:24:01.16#ibcon#enter wrdev, iclass 11, count 0 2006.173.04:24:01.16#ibcon#first serial, iclass 11, count 0 2006.173.04:24:01.16#ibcon#enter sib2, iclass 11, count 0 2006.173.04:24:01.16#ibcon#flushed, iclass 11, count 0 2006.173.04:24:01.16#ibcon#about to write, iclass 11, count 0 2006.173.04:24:01.16#ibcon#wrote, iclass 11, count 0 2006.173.04:24:01.16#ibcon#about to read 3, iclass 11, count 0 2006.173.04:24:01.18#ibcon#read 3, iclass 11, count 0 2006.173.04:24:01.18#ibcon#about to read 4, iclass 11, count 0 2006.173.04:24:01.18#ibcon#read 4, iclass 11, count 0 2006.173.04:24:01.18#ibcon#about to read 5, iclass 11, count 0 2006.173.04:24:01.18#ibcon#read 5, iclass 11, count 0 2006.173.04:24:01.18#ibcon#about to read 6, iclass 11, count 0 2006.173.04:24:01.18#ibcon#read 6, iclass 11, count 0 2006.173.04:24:01.18#ibcon#end of sib2, iclass 11, count 0 2006.173.04:24:01.18#ibcon#*mode == 0, iclass 11, count 0 2006.173.04:24:01.18#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.04:24:01.18#ibcon#[25=USB\r\n] 2006.173.04:24:01.18#ibcon#*before write, iclass 11, count 0 2006.173.04:24:01.18#ibcon#enter sib2, iclass 11, count 0 2006.173.04:24:01.18#ibcon#flushed, iclass 11, count 0 2006.173.04:24:01.18#ibcon#about to write, iclass 11, count 0 2006.173.04:24:01.18#ibcon#wrote, iclass 11, count 0 2006.173.04:24:01.18#ibcon#about to read 3, iclass 11, count 0 2006.173.04:24:01.21#ibcon#read 3, iclass 11, count 0 2006.173.04:24:01.21#ibcon#about to read 4, iclass 11, count 0 2006.173.04:24:01.21#ibcon#read 4, iclass 11, count 0 2006.173.04:24:01.21#ibcon#about to read 5, iclass 11, count 0 2006.173.04:24:01.21#ibcon#read 5, iclass 11, count 0 2006.173.04:24:01.21#ibcon#about to read 6, iclass 11, count 0 2006.173.04:24:01.21#ibcon#read 6, iclass 11, count 0 2006.173.04:24:01.21#ibcon#end of sib2, iclass 11, count 0 2006.173.04:24:01.21#ibcon#*after write, iclass 11, count 0 2006.173.04:24:01.21#ibcon#*before return 0, iclass 11, count 0 2006.173.04:24:01.21#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.04:24:01.21#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.04:24:01.21#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.04:24:01.21#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.04:24:01.21$vck44/valo=3,564.99 2006.173.04:24:01.21#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.04:24:01.21#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.04:24:01.21#ibcon#ireg 17 cls_cnt 0 2006.173.04:24:01.21#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.04:24:01.21#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.04:24:01.21#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.04:24:01.21#ibcon#enter wrdev, iclass 13, count 0 2006.173.04:24:01.21#ibcon#first serial, iclass 13, count 0 2006.173.04:24:01.21#ibcon#enter sib2, iclass 13, count 0 2006.173.04:24:01.21#ibcon#flushed, iclass 13, count 0 2006.173.04:24:01.21#ibcon#about to write, iclass 13, count 0 2006.173.04:24:01.21#ibcon#wrote, iclass 13, count 0 2006.173.04:24:01.21#ibcon#about to read 3, iclass 13, count 0 2006.173.04:24:01.23#ibcon#read 3, iclass 13, count 0 2006.173.04:24:01.23#ibcon#about to read 4, iclass 13, count 0 2006.173.04:24:01.23#ibcon#read 4, iclass 13, count 0 2006.173.04:24:01.23#ibcon#about to read 5, iclass 13, count 0 2006.173.04:24:01.23#ibcon#read 5, iclass 13, count 0 2006.173.04:24:01.23#ibcon#about to read 6, iclass 13, count 0 2006.173.04:24:01.23#ibcon#read 6, iclass 13, count 0 2006.173.04:24:01.23#ibcon#end of sib2, iclass 13, count 0 2006.173.04:24:01.23#ibcon#*mode == 0, iclass 13, count 0 2006.173.04:24:01.23#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.04:24:01.23#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.04:24:01.23#ibcon#*before write, iclass 13, count 0 2006.173.04:24:01.23#ibcon#enter sib2, iclass 13, count 0 2006.173.04:24:01.23#ibcon#flushed, iclass 13, count 0 2006.173.04:24:01.23#ibcon#about to write, iclass 13, count 0 2006.173.04:24:01.23#ibcon#wrote, iclass 13, count 0 2006.173.04:24:01.23#ibcon#about to read 3, iclass 13, count 0 2006.173.04:24:01.27#ibcon#read 3, iclass 13, count 0 2006.173.04:24:01.27#ibcon#about to read 4, iclass 13, count 0 2006.173.04:24:01.27#ibcon#read 4, iclass 13, count 0 2006.173.04:24:01.27#ibcon#about to read 5, iclass 13, count 0 2006.173.04:24:01.27#ibcon#read 5, iclass 13, count 0 2006.173.04:24:01.27#ibcon#about to read 6, iclass 13, count 0 2006.173.04:24:01.27#ibcon#read 6, iclass 13, count 0 2006.173.04:24:01.27#ibcon#end of sib2, iclass 13, count 0 2006.173.04:24:01.27#ibcon#*after write, iclass 13, count 0 2006.173.04:24:01.27#ibcon#*before return 0, iclass 13, count 0 2006.173.04:24:01.27#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.04:24:01.27#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.04:24:01.27#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.04:24:01.27#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.04:24:01.27$vck44/va=3,5 2006.173.04:24:01.27#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.04:24:01.27#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.04:24:01.27#ibcon#ireg 11 cls_cnt 2 2006.173.04:24:01.27#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.04:24:01.33#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.04:24:01.33#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.04:24:01.33#ibcon#enter wrdev, iclass 15, count 2 2006.173.04:24:01.33#ibcon#first serial, iclass 15, count 2 2006.173.04:24:01.33#ibcon#enter sib2, iclass 15, count 2 2006.173.04:24:01.33#ibcon#flushed, iclass 15, count 2 2006.173.04:24:01.33#ibcon#about to write, iclass 15, count 2 2006.173.04:24:01.33#ibcon#wrote, iclass 15, count 2 2006.173.04:24:01.33#ibcon#about to read 3, iclass 15, count 2 2006.173.04:24:01.35#ibcon#read 3, iclass 15, count 2 2006.173.04:24:01.35#ibcon#about to read 4, iclass 15, count 2 2006.173.04:24:01.35#ibcon#read 4, iclass 15, count 2 2006.173.04:24:01.35#ibcon#about to read 5, iclass 15, count 2 2006.173.04:24:01.35#ibcon#read 5, iclass 15, count 2 2006.173.04:24:01.35#ibcon#about to read 6, iclass 15, count 2 2006.173.04:24:01.35#ibcon#read 6, iclass 15, count 2 2006.173.04:24:01.35#ibcon#end of sib2, iclass 15, count 2 2006.173.04:24:01.35#ibcon#*mode == 0, iclass 15, count 2 2006.173.04:24:01.35#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.04:24:01.35#ibcon#[25=AT03-05\r\n] 2006.173.04:24:01.35#ibcon#*before write, iclass 15, count 2 2006.173.04:24:01.35#ibcon#enter sib2, iclass 15, count 2 2006.173.04:24:01.35#ibcon#flushed, iclass 15, count 2 2006.173.04:24:01.35#ibcon#about to write, iclass 15, count 2 2006.173.04:24:01.35#ibcon#wrote, iclass 15, count 2 2006.173.04:24:01.35#ibcon#about to read 3, iclass 15, count 2 2006.173.04:24:01.38#ibcon#read 3, iclass 15, count 2 2006.173.04:24:01.38#ibcon#about to read 4, iclass 15, count 2 2006.173.04:24:01.38#ibcon#read 4, iclass 15, count 2 2006.173.04:24:01.38#ibcon#about to read 5, iclass 15, count 2 2006.173.04:24:01.38#ibcon#read 5, iclass 15, count 2 2006.173.04:24:01.38#ibcon#about to read 6, iclass 15, count 2 2006.173.04:24:01.38#ibcon#read 6, iclass 15, count 2 2006.173.04:24:01.38#ibcon#end of sib2, iclass 15, count 2 2006.173.04:24:01.38#ibcon#*after write, iclass 15, count 2 2006.173.04:24:01.38#ibcon#*before return 0, iclass 15, count 2 2006.173.04:24:01.38#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.04:24:01.38#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.04:24:01.38#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.04:24:01.38#ibcon#ireg 7 cls_cnt 0 2006.173.04:24:01.38#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.04:24:01.50#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.04:24:01.50#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.04:24:01.50#ibcon#enter wrdev, iclass 15, count 0 2006.173.04:24:01.50#ibcon#first serial, iclass 15, count 0 2006.173.04:24:01.50#ibcon#enter sib2, iclass 15, count 0 2006.173.04:24:01.50#ibcon#flushed, iclass 15, count 0 2006.173.04:24:01.50#ibcon#about to write, iclass 15, count 0 2006.173.04:24:01.50#ibcon#wrote, iclass 15, count 0 2006.173.04:24:01.50#ibcon#about to read 3, iclass 15, count 0 2006.173.04:24:01.52#ibcon#read 3, iclass 15, count 0 2006.173.04:24:01.52#ibcon#about to read 4, iclass 15, count 0 2006.173.04:24:01.52#ibcon#read 4, iclass 15, count 0 2006.173.04:24:01.52#ibcon#about to read 5, iclass 15, count 0 2006.173.04:24:01.52#ibcon#read 5, iclass 15, count 0 2006.173.04:24:01.52#ibcon#about to read 6, iclass 15, count 0 2006.173.04:24:01.52#ibcon#read 6, iclass 15, count 0 2006.173.04:24:01.52#ibcon#end of sib2, iclass 15, count 0 2006.173.04:24:01.52#ibcon#*mode == 0, iclass 15, count 0 2006.173.04:24:01.52#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.04:24:01.52#ibcon#[25=USB\r\n] 2006.173.04:24:01.52#ibcon#*before write, iclass 15, count 0 2006.173.04:24:01.52#ibcon#enter sib2, iclass 15, count 0 2006.173.04:24:01.52#ibcon#flushed, iclass 15, count 0 2006.173.04:24:01.52#ibcon#about to write, iclass 15, count 0 2006.173.04:24:01.52#ibcon#wrote, iclass 15, count 0 2006.173.04:24:01.52#ibcon#about to read 3, iclass 15, count 0 2006.173.04:24:01.55#ibcon#read 3, iclass 15, count 0 2006.173.04:24:01.55#ibcon#about to read 4, iclass 15, count 0 2006.173.04:24:01.55#ibcon#read 4, iclass 15, count 0 2006.173.04:24:01.55#ibcon#about to read 5, iclass 15, count 0 2006.173.04:24:01.55#ibcon#read 5, iclass 15, count 0 2006.173.04:24:01.55#ibcon#about to read 6, iclass 15, count 0 2006.173.04:24:01.55#ibcon#read 6, iclass 15, count 0 2006.173.04:24:01.55#ibcon#end of sib2, iclass 15, count 0 2006.173.04:24:01.55#ibcon#*after write, iclass 15, count 0 2006.173.04:24:01.55#ibcon#*before return 0, iclass 15, count 0 2006.173.04:24:01.55#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.04:24:01.55#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.04:24:01.55#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.04:24:01.55#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.04:24:01.55$vck44/valo=4,624.99 2006.173.04:24:01.55#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.04:24:01.55#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.04:24:01.55#ibcon#ireg 17 cls_cnt 0 2006.173.04:24:01.55#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.04:24:01.55#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.04:24:01.55#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.04:24:01.55#ibcon#enter wrdev, iclass 17, count 0 2006.173.04:24:01.55#ibcon#first serial, iclass 17, count 0 2006.173.04:24:01.55#ibcon#enter sib2, iclass 17, count 0 2006.173.04:24:01.55#ibcon#flushed, iclass 17, count 0 2006.173.04:24:01.55#ibcon#about to write, iclass 17, count 0 2006.173.04:24:01.55#ibcon#wrote, iclass 17, count 0 2006.173.04:24:01.55#ibcon#about to read 3, iclass 17, count 0 2006.173.04:24:01.57#ibcon#read 3, iclass 17, count 0 2006.173.04:24:01.57#ibcon#about to read 4, iclass 17, count 0 2006.173.04:24:01.57#ibcon#read 4, iclass 17, count 0 2006.173.04:24:01.57#ibcon#about to read 5, iclass 17, count 0 2006.173.04:24:01.57#ibcon#read 5, iclass 17, count 0 2006.173.04:24:01.57#ibcon#about to read 6, iclass 17, count 0 2006.173.04:24:01.57#ibcon#read 6, iclass 17, count 0 2006.173.04:24:01.57#ibcon#end of sib2, iclass 17, count 0 2006.173.04:24:01.57#ibcon#*mode == 0, iclass 17, count 0 2006.173.04:24:01.57#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.04:24:01.57#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.04:24:01.57#ibcon#*before write, iclass 17, count 0 2006.173.04:24:01.57#ibcon#enter sib2, iclass 17, count 0 2006.173.04:24:01.57#ibcon#flushed, iclass 17, count 0 2006.173.04:24:01.57#ibcon#about to write, iclass 17, count 0 2006.173.04:24:01.57#ibcon#wrote, iclass 17, count 0 2006.173.04:24:01.57#ibcon#about to read 3, iclass 17, count 0 2006.173.04:24:01.61#ibcon#read 3, iclass 17, count 0 2006.173.04:24:01.61#ibcon#about to read 4, iclass 17, count 0 2006.173.04:24:01.61#ibcon#read 4, iclass 17, count 0 2006.173.04:24:01.61#ibcon#about to read 5, iclass 17, count 0 2006.173.04:24:01.61#ibcon#read 5, iclass 17, count 0 2006.173.04:24:01.61#ibcon#about to read 6, iclass 17, count 0 2006.173.04:24:01.61#ibcon#read 6, iclass 17, count 0 2006.173.04:24:01.61#ibcon#end of sib2, iclass 17, count 0 2006.173.04:24:01.61#ibcon#*after write, iclass 17, count 0 2006.173.04:24:01.61#ibcon#*before return 0, iclass 17, count 0 2006.173.04:24:01.61#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.04:24:01.61#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.04:24:01.61#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.04:24:01.61#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.04:24:01.61$vck44/va=4,6 2006.173.04:24:01.61#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.04:24:01.61#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.04:24:01.61#ibcon#ireg 11 cls_cnt 2 2006.173.04:24:01.61#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.04:24:01.67#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.04:24:01.67#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.04:24:01.67#ibcon#enter wrdev, iclass 19, count 2 2006.173.04:24:01.67#ibcon#first serial, iclass 19, count 2 2006.173.04:24:01.67#ibcon#enter sib2, iclass 19, count 2 2006.173.04:24:01.67#ibcon#flushed, iclass 19, count 2 2006.173.04:24:01.67#ibcon#about to write, iclass 19, count 2 2006.173.04:24:01.67#ibcon#wrote, iclass 19, count 2 2006.173.04:24:01.67#ibcon#about to read 3, iclass 19, count 2 2006.173.04:24:01.69#ibcon#read 3, iclass 19, count 2 2006.173.04:24:01.69#ibcon#about to read 4, iclass 19, count 2 2006.173.04:24:01.69#ibcon#read 4, iclass 19, count 2 2006.173.04:24:01.69#ibcon#about to read 5, iclass 19, count 2 2006.173.04:24:01.69#ibcon#read 5, iclass 19, count 2 2006.173.04:24:01.69#ibcon#about to read 6, iclass 19, count 2 2006.173.04:24:01.69#ibcon#read 6, iclass 19, count 2 2006.173.04:24:01.69#ibcon#end of sib2, iclass 19, count 2 2006.173.04:24:01.69#ibcon#*mode == 0, iclass 19, count 2 2006.173.04:24:01.69#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.04:24:01.69#ibcon#[25=AT04-06\r\n] 2006.173.04:24:01.69#ibcon#*before write, iclass 19, count 2 2006.173.04:24:01.69#ibcon#enter sib2, iclass 19, count 2 2006.173.04:24:01.69#ibcon#flushed, iclass 19, count 2 2006.173.04:24:01.69#ibcon#about to write, iclass 19, count 2 2006.173.04:24:01.69#ibcon#wrote, iclass 19, count 2 2006.173.04:24:01.69#ibcon#about to read 3, iclass 19, count 2 2006.173.04:24:01.72#ibcon#read 3, iclass 19, count 2 2006.173.04:24:01.72#ibcon#about to read 4, iclass 19, count 2 2006.173.04:24:01.72#ibcon#read 4, iclass 19, count 2 2006.173.04:24:01.72#ibcon#about to read 5, iclass 19, count 2 2006.173.04:24:01.72#ibcon#read 5, iclass 19, count 2 2006.173.04:24:01.72#ibcon#about to read 6, iclass 19, count 2 2006.173.04:24:01.72#ibcon#read 6, iclass 19, count 2 2006.173.04:24:01.72#ibcon#end of sib2, iclass 19, count 2 2006.173.04:24:01.72#ibcon#*after write, iclass 19, count 2 2006.173.04:24:01.72#ibcon#*before return 0, iclass 19, count 2 2006.173.04:24:01.72#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.04:24:01.72#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.04:24:01.72#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.04:24:01.72#ibcon#ireg 7 cls_cnt 0 2006.173.04:24:01.72#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.04:24:01.84#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.04:24:01.84#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.04:24:01.84#ibcon#enter wrdev, iclass 19, count 0 2006.173.04:24:01.84#ibcon#first serial, iclass 19, count 0 2006.173.04:24:01.84#ibcon#enter sib2, iclass 19, count 0 2006.173.04:24:01.84#ibcon#flushed, iclass 19, count 0 2006.173.04:24:01.84#ibcon#about to write, iclass 19, count 0 2006.173.04:24:01.84#ibcon#wrote, iclass 19, count 0 2006.173.04:24:01.84#ibcon#about to read 3, iclass 19, count 0 2006.173.04:24:01.86#ibcon#read 3, iclass 19, count 0 2006.173.04:24:01.86#ibcon#about to read 4, iclass 19, count 0 2006.173.04:24:01.86#ibcon#read 4, iclass 19, count 0 2006.173.04:24:01.86#ibcon#about to read 5, iclass 19, count 0 2006.173.04:24:01.86#ibcon#read 5, iclass 19, count 0 2006.173.04:24:01.86#ibcon#about to read 6, iclass 19, count 0 2006.173.04:24:01.86#ibcon#read 6, iclass 19, count 0 2006.173.04:24:01.86#ibcon#end of sib2, iclass 19, count 0 2006.173.04:24:01.86#ibcon#*mode == 0, iclass 19, count 0 2006.173.04:24:01.86#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.04:24:01.86#ibcon#[25=USB\r\n] 2006.173.04:24:01.86#ibcon#*before write, iclass 19, count 0 2006.173.04:24:01.86#ibcon#enter sib2, iclass 19, count 0 2006.173.04:24:01.86#ibcon#flushed, iclass 19, count 0 2006.173.04:24:01.86#ibcon#about to write, iclass 19, count 0 2006.173.04:24:01.86#ibcon#wrote, iclass 19, count 0 2006.173.04:24:01.86#ibcon#about to read 3, iclass 19, count 0 2006.173.04:24:01.89#ibcon#read 3, iclass 19, count 0 2006.173.04:24:01.89#ibcon#about to read 4, iclass 19, count 0 2006.173.04:24:01.89#ibcon#read 4, iclass 19, count 0 2006.173.04:24:01.89#ibcon#about to read 5, iclass 19, count 0 2006.173.04:24:01.89#ibcon#read 5, iclass 19, count 0 2006.173.04:24:01.89#ibcon#about to read 6, iclass 19, count 0 2006.173.04:24:01.89#ibcon#read 6, iclass 19, count 0 2006.173.04:24:01.89#ibcon#end of sib2, iclass 19, count 0 2006.173.04:24:01.89#ibcon#*after write, iclass 19, count 0 2006.173.04:24:01.89#ibcon#*before return 0, iclass 19, count 0 2006.173.04:24:01.89#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.04:24:01.89#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.04:24:01.89#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.04:24:01.89#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.04:24:01.89$vck44/valo=5,734.99 2006.173.04:24:01.89#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.04:24:01.89#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.04:24:01.89#ibcon#ireg 17 cls_cnt 0 2006.173.04:24:01.89#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.04:24:01.89#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.04:24:01.89#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.04:24:01.89#ibcon#enter wrdev, iclass 21, count 0 2006.173.04:24:01.89#ibcon#first serial, iclass 21, count 0 2006.173.04:24:01.89#ibcon#enter sib2, iclass 21, count 0 2006.173.04:24:01.89#ibcon#flushed, iclass 21, count 0 2006.173.04:24:01.89#ibcon#about to write, iclass 21, count 0 2006.173.04:24:01.89#ibcon#wrote, iclass 21, count 0 2006.173.04:24:01.89#ibcon#about to read 3, iclass 21, count 0 2006.173.04:24:01.91#ibcon#read 3, iclass 21, count 0 2006.173.04:24:01.91#ibcon#about to read 4, iclass 21, count 0 2006.173.04:24:01.91#ibcon#read 4, iclass 21, count 0 2006.173.04:24:01.91#ibcon#about to read 5, iclass 21, count 0 2006.173.04:24:01.91#ibcon#read 5, iclass 21, count 0 2006.173.04:24:01.91#ibcon#about to read 6, iclass 21, count 0 2006.173.04:24:01.91#ibcon#read 6, iclass 21, count 0 2006.173.04:24:01.91#ibcon#end of sib2, iclass 21, count 0 2006.173.04:24:01.91#ibcon#*mode == 0, iclass 21, count 0 2006.173.04:24:01.91#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.04:24:01.91#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.04:24:01.91#ibcon#*before write, iclass 21, count 0 2006.173.04:24:01.91#ibcon#enter sib2, iclass 21, count 0 2006.173.04:24:01.91#ibcon#flushed, iclass 21, count 0 2006.173.04:24:01.91#ibcon#about to write, iclass 21, count 0 2006.173.04:24:01.91#ibcon#wrote, iclass 21, count 0 2006.173.04:24:01.91#ibcon#about to read 3, iclass 21, count 0 2006.173.04:24:01.95#ibcon#read 3, iclass 21, count 0 2006.173.04:24:01.95#ibcon#about to read 4, iclass 21, count 0 2006.173.04:24:01.95#ibcon#read 4, iclass 21, count 0 2006.173.04:24:01.95#ibcon#about to read 5, iclass 21, count 0 2006.173.04:24:01.95#ibcon#read 5, iclass 21, count 0 2006.173.04:24:01.95#ibcon#about to read 6, iclass 21, count 0 2006.173.04:24:01.95#ibcon#read 6, iclass 21, count 0 2006.173.04:24:01.95#ibcon#end of sib2, iclass 21, count 0 2006.173.04:24:01.95#ibcon#*after write, iclass 21, count 0 2006.173.04:24:01.95#ibcon#*before return 0, iclass 21, count 0 2006.173.04:24:01.95#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.04:24:01.95#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.04:24:01.95#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.04:24:01.95#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.04:24:01.95$vck44/va=5,4 2006.173.04:24:01.95#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.04:24:01.95#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.04:24:01.95#ibcon#ireg 11 cls_cnt 2 2006.173.04:24:01.95#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.04:24:02.01#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.04:24:02.01#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.04:24:02.01#ibcon#enter wrdev, iclass 23, count 2 2006.173.04:24:02.01#ibcon#first serial, iclass 23, count 2 2006.173.04:24:02.01#ibcon#enter sib2, iclass 23, count 2 2006.173.04:24:02.01#ibcon#flushed, iclass 23, count 2 2006.173.04:24:02.01#ibcon#about to write, iclass 23, count 2 2006.173.04:24:02.01#ibcon#wrote, iclass 23, count 2 2006.173.04:24:02.01#ibcon#about to read 3, iclass 23, count 2 2006.173.04:24:02.03#ibcon#read 3, iclass 23, count 2 2006.173.04:24:02.03#ibcon#about to read 4, iclass 23, count 2 2006.173.04:24:02.03#ibcon#read 4, iclass 23, count 2 2006.173.04:24:02.03#ibcon#about to read 5, iclass 23, count 2 2006.173.04:24:02.03#ibcon#read 5, iclass 23, count 2 2006.173.04:24:02.03#ibcon#about to read 6, iclass 23, count 2 2006.173.04:24:02.03#ibcon#read 6, iclass 23, count 2 2006.173.04:24:02.03#ibcon#end of sib2, iclass 23, count 2 2006.173.04:24:02.03#ibcon#*mode == 0, iclass 23, count 2 2006.173.04:24:02.03#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.04:24:02.03#ibcon#[25=AT05-04\r\n] 2006.173.04:24:02.03#ibcon#*before write, iclass 23, count 2 2006.173.04:24:02.03#ibcon#enter sib2, iclass 23, count 2 2006.173.04:24:02.03#ibcon#flushed, iclass 23, count 2 2006.173.04:24:02.03#ibcon#about to write, iclass 23, count 2 2006.173.04:24:02.03#ibcon#wrote, iclass 23, count 2 2006.173.04:24:02.03#ibcon#about to read 3, iclass 23, count 2 2006.173.04:24:02.06#ibcon#read 3, iclass 23, count 2 2006.173.04:24:02.06#ibcon#about to read 4, iclass 23, count 2 2006.173.04:24:02.06#ibcon#read 4, iclass 23, count 2 2006.173.04:24:02.06#ibcon#about to read 5, iclass 23, count 2 2006.173.04:24:02.06#ibcon#read 5, iclass 23, count 2 2006.173.04:24:02.06#ibcon#about to read 6, iclass 23, count 2 2006.173.04:24:02.06#ibcon#read 6, iclass 23, count 2 2006.173.04:24:02.06#ibcon#end of sib2, iclass 23, count 2 2006.173.04:24:02.06#ibcon#*after write, iclass 23, count 2 2006.173.04:24:02.06#ibcon#*before return 0, iclass 23, count 2 2006.173.04:24:02.06#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.04:24:02.06#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.04:24:02.06#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.04:24:02.06#ibcon#ireg 7 cls_cnt 0 2006.173.04:24:02.06#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.04:24:02.18#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.04:24:02.18#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.04:24:02.18#ibcon#enter wrdev, iclass 23, count 0 2006.173.04:24:02.18#ibcon#first serial, iclass 23, count 0 2006.173.04:24:02.18#ibcon#enter sib2, iclass 23, count 0 2006.173.04:24:02.18#ibcon#flushed, iclass 23, count 0 2006.173.04:24:02.18#ibcon#about to write, iclass 23, count 0 2006.173.04:24:02.18#ibcon#wrote, iclass 23, count 0 2006.173.04:24:02.18#ibcon#about to read 3, iclass 23, count 0 2006.173.04:24:02.20#ibcon#read 3, iclass 23, count 0 2006.173.04:24:02.20#ibcon#about to read 4, iclass 23, count 0 2006.173.04:24:02.20#ibcon#read 4, iclass 23, count 0 2006.173.04:24:02.20#ibcon#about to read 5, iclass 23, count 0 2006.173.04:24:02.20#ibcon#read 5, iclass 23, count 0 2006.173.04:24:02.20#ibcon#about to read 6, iclass 23, count 0 2006.173.04:24:02.20#ibcon#read 6, iclass 23, count 0 2006.173.04:24:02.20#ibcon#end of sib2, iclass 23, count 0 2006.173.04:24:02.20#ibcon#*mode == 0, iclass 23, count 0 2006.173.04:24:02.20#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.04:24:02.20#ibcon#[25=USB\r\n] 2006.173.04:24:02.20#ibcon#*before write, iclass 23, count 0 2006.173.04:24:02.20#ibcon#enter sib2, iclass 23, count 0 2006.173.04:24:02.20#ibcon#flushed, iclass 23, count 0 2006.173.04:24:02.20#ibcon#about to write, iclass 23, count 0 2006.173.04:24:02.20#ibcon#wrote, iclass 23, count 0 2006.173.04:24:02.20#ibcon#about to read 3, iclass 23, count 0 2006.173.04:24:02.23#ibcon#read 3, iclass 23, count 0 2006.173.04:24:02.23#ibcon#about to read 4, iclass 23, count 0 2006.173.04:24:02.23#ibcon#read 4, iclass 23, count 0 2006.173.04:24:02.23#ibcon#about to read 5, iclass 23, count 0 2006.173.04:24:02.23#ibcon#read 5, iclass 23, count 0 2006.173.04:24:02.23#ibcon#about to read 6, iclass 23, count 0 2006.173.04:24:02.23#ibcon#read 6, iclass 23, count 0 2006.173.04:24:02.23#ibcon#end of sib2, iclass 23, count 0 2006.173.04:24:02.23#ibcon#*after write, iclass 23, count 0 2006.173.04:24:02.23#ibcon#*before return 0, iclass 23, count 0 2006.173.04:24:02.23#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.04:24:02.23#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.04:24:02.23#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.04:24:02.23#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.04:24:02.23$vck44/valo=6,814.99 2006.173.04:24:02.23#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.04:24:02.23#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.04:24:02.23#ibcon#ireg 17 cls_cnt 0 2006.173.04:24:02.23#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.04:24:02.23#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.04:24:02.23#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.04:24:02.23#ibcon#enter wrdev, iclass 25, count 0 2006.173.04:24:02.23#ibcon#first serial, iclass 25, count 0 2006.173.04:24:02.23#ibcon#enter sib2, iclass 25, count 0 2006.173.04:24:02.23#ibcon#flushed, iclass 25, count 0 2006.173.04:24:02.23#ibcon#about to write, iclass 25, count 0 2006.173.04:24:02.23#ibcon#wrote, iclass 25, count 0 2006.173.04:24:02.23#ibcon#about to read 3, iclass 25, count 0 2006.173.04:24:02.25#ibcon#read 3, iclass 25, count 0 2006.173.04:24:02.25#ibcon#about to read 4, iclass 25, count 0 2006.173.04:24:02.25#ibcon#read 4, iclass 25, count 0 2006.173.04:24:02.25#ibcon#about to read 5, iclass 25, count 0 2006.173.04:24:02.25#ibcon#read 5, iclass 25, count 0 2006.173.04:24:02.25#ibcon#about to read 6, iclass 25, count 0 2006.173.04:24:02.25#ibcon#read 6, iclass 25, count 0 2006.173.04:24:02.25#ibcon#end of sib2, iclass 25, count 0 2006.173.04:24:02.25#ibcon#*mode == 0, iclass 25, count 0 2006.173.04:24:02.25#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.04:24:02.25#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.04:24:02.25#ibcon#*before write, iclass 25, count 0 2006.173.04:24:02.25#ibcon#enter sib2, iclass 25, count 0 2006.173.04:24:02.25#ibcon#flushed, iclass 25, count 0 2006.173.04:24:02.25#ibcon#about to write, iclass 25, count 0 2006.173.04:24:02.25#ibcon#wrote, iclass 25, count 0 2006.173.04:24:02.25#ibcon#about to read 3, iclass 25, count 0 2006.173.04:24:02.29#ibcon#read 3, iclass 25, count 0 2006.173.04:24:02.29#ibcon#about to read 4, iclass 25, count 0 2006.173.04:24:02.29#ibcon#read 4, iclass 25, count 0 2006.173.04:24:02.29#ibcon#about to read 5, iclass 25, count 0 2006.173.04:24:02.29#ibcon#read 5, iclass 25, count 0 2006.173.04:24:02.29#ibcon#about to read 6, iclass 25, count 0 2006.173.04:24:02.29#ibcon#read 6, iclass 25, count 0 2006.173.04:24:02.29#ibcon#end of sib2, iclass 25, count 0 2006.173.04:24:02.29#ibcon#*after write, iclass 25, count 0 2006.173.04:24:02.29#ibcon#*before return 0, iclass 25, count 0 2006.173.04:24:02.29#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.04:24:02.29#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.04:24:02.29#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.04:24:02.29#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.04:24:02.29$vck44/va=6,3 2006.173.04:24:02.29#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.04:24:02.29#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.04:24:02.29#ibcon#ireg 11 cls_cnt 2 2006.173.04:24:02.29#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.04:24:02.35#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.04:24:02.35#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.04:24:02.35#ibcon#enter wrdev, iclass 27, count 2 2006.173.04:24:02.35#ibcon#first serial, iclass 27, count 2 2006.173.04:24:02.35#ibcon#enter sib2, iclass 27, count 2 2006.173.04:24:02.35#ibcon#flushed, iclass 27, count 2 2006.173.04:24:02.35#ibcon#about to write, iclass 27, count 2 2006.173.04:24:02.35#ibcon#wrote, iclass 27, count 2 2006.173.04:24:02.35#ibcon#about to read 3, iclass 27, count 2 2006.173.04:24:02.37#ibcon#read 3, iclass 27, count 2 2006.173.04:24:02.37#ibcon#about to read 4, iclass 27, count 2 2006.173.04:24:02.37#ibcon#read 4, iclass 27, count 2 2006.173.04:24:02.37#ibcon#about to read 5, iclass 27, count 2 2006.173.04:24:02.37#ibcon#read 5, iclass 27, count 2 2006.173.04:24:02.37#ibcon#about to read 6, iclass 27, count 2 2006.173.04:24:02.37#ibcon#read 6, iclass 27, count 2 2006.173.04:24:02.37#ibcon#end of sib2, iclass 27, count 2 2006.173.04:24:02.37#ibcon#*mode == 0, iclass 27, count 2 2006.173.04:24:02.37#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.04:24:02.37#ibcon#[25=AT06-03\r\n] 2006.173.04:24:02.37#ibcon#*before write, iclass 27, count 2 2006.173.04:24:02.37#ibcon#enter sib2, iclass 27, count 2 2006.173.04:24:02.37#ibcon#flushed, iclass 27, count 2 2006.173.04:24:02.37#ibcon#about to write, iclass 27, count 2 2006.173.04:24:02.37#ibcon#wrote, iclass 27, count 2 2006.173.04:24:02.37#ibcon#about to read 3, iclass 27, count 2 2006.173.04:24:02.40#ibcon#read 3, iclass 27, count 2 2006.173.04:24:02.40#ibcon#about to read 4, iclass 27, count 2 2006.173.04:24:02.40#ibcon#read 4, iclass 27, count 2 2006.173.04:24:02.40#ibcon#about to read 5, iclass 27, count 2 2006.173.04:24:02.40#ibcon#read 5, iclass 27, count 2 2006.173.04:24:02.40#ibcon#about to read 6, iclass 27, count 2 2006.173.04:24:02.40#ibcon#read 6, iclass 27, count 2 2006.173.04:24:02.40#ibcon#end of sib2, iclass 27, count 2 2006.173.04:24:02.40#ibcon#*after write, iclass 27, count 2 2006.173.04:24:02.40#ibcon#*before return 0, iclass 27, count 2 2006.173.04:24:02.40#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.04:24:02.40#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.04:24:02.40#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.04:24:02.40#ibcon#ireg 7 cls_cnt 0 2006.173.04:24:02.40#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.04:24:02.52#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.04:24:02.52#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.04:24:02.52#ibcon#enter wrdev, iclass 27, count 0 2006.173.04:24:02.52#ibcon#first serial, iclass 27, count 0 2006.173.04:24:02.52#ibcon#enter sib2, iclass 27, count 0 2006.173.04:24:02.52#ibcon#flushed, iclass 27, count 0 2006.173.04:24:02.52#ibcon#about to write, iclass 27, count 0 2006.173.04:24:02.52#ibcon#wrote, iclass 27, count 0 2006.173.04:24:02.52#ibcon#about to read 3, iclass 27, count 0 2006.173.04:24:02.54#ibcon#read 3, iclass 27, count 0 2006.173.04:24:02.54#ibcon#about to read 4, iclass 27, count 0 2006.173.04:24:02.54#ibcon#read 4, iclass 27, count 0 2006.173.04:24:02.54#ibcon#about to read 5, iclass 27, count 0 2006.173.04:24:02.54#ibcon#read 5, iclass 27, count 0 2006.173.04:24:02.54#ibcon#about to read 6, iclass 27, count 0 2006.173.04:24:02.54#ibcon#read 6, iclass 27, count 0 2006.173.04:24:02.54#ibcon#end of sib2, iclass 27, count 0 2006.173.04:24:02.54#ibcon#*mode == 0, iclass 27, count 0 2006.173.04:24:02.54#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.04:24:02.54#ibcon#[25=USB\r\n] 2006.173.04:24:02.54#ibcon#*before write, iclass 27, count 0 2006.173.04:24:02.54#ibcon#enter sib2, iclass 27, count 0 2006.173.04:24:02.54#ibcon#flushed, iclass 27, count 0 2006.173.04:24:02.54#ibcon#about to write, iclass 27, count 0 2006.173.04:24:02.54#ibcon#wrote, iclass 27, count 0 2006.173.04:24:02.54#ibcon#about to read 3, iclass 27, count 0 2006.173.04:24:02.57#ibcon#read 3, iclass 27, count 0 2006.173.04:24:02.57#ibcon#about to read 4, iclass 27, count 0 2006.173.04:24:02.57#ibcon#read 4, iclass 27, count 0 2006.173.04:24:02.57#ibcon#about to read 5, iclass 27, count 0 2006.173.04:24:02.57#ibcon#read 5, iclass 27, count 0 2006.173.04:24:02.57#ibcon#about to read 6, iclass 27, count 0 2006.173.04:24:02.57#ibcon#read 6, iclass 27, count 0 2006.173.04:24:02.57#ibcon#end of sib2, iclass 27, count 0 2006.173.04:24:02.57#ibcon#*after write, iclass 27, count 0 2006.173.04:24:02.57#ibcon#*before return 0, iclass 27, count 0 2006.173.04:24:02.57#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.04:24:02.57#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.04:24:02.57#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.04:24:02.57#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.04:24:02.57$vck44/valo=7,864.99 2006.173.04:24:02.57#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.04:24:02.57#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.04:24:02.57#ibcon#ireg 17 cls_cnt 0 2006.173.04:24:02.57#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.04:24:02.57#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.04:24:02.57#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.04:24:02.57#ibcon#enter wrdev, iclass 29, count 0 2006.173.04:24:02.57#ibcon#first serial, iclass 29, count 0 2006.173.04:24:02.57#ibcon#enter sib2, iclass 29, count 0 2006.173.04:24:02.57#ibcon#flushed, iclass 29, count 0 2006.173.04:24:02.57#ibcon#about to write, iclass 29, count 0 2006.173.04:24:02.57#ibcon#wrote, iclass 29, count 0 2006.173.04:24:02.57#ibcon#about to read 3, iclass 29, count 0 2006.173.04:24:02.59#ibcon#read 3, iclass 29, count 0 2006.173.04:24:02.59#ibcon#about to read 4, iclass 29, count 0 2006.173.04:24:02.59#ibcon#read 4, iclass 29, count 0 2006.173.04:24:02.59#ibcon#about to read 5, iclass 29, count 0 2006.173.04:24:02.59#ibcon#read 5, iclass 29, count 0 2006.173.04:24:02.59#ibcon#about to read 6, iclass 29, count 0 2006.173.04:24:02.59#ibcon#read 6, iclass 29, count 0 2006.173.04:24:02.59#ibcon#end of sib2, iclass 29, count 0 2006.173.04:24:02.59#ibcon#*mode == 0, iclass 29, count 0 2006.173.04:24:02.59#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.04:24:02.59#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.04:24:02.59#ibcon#*before write, iclass 29, count 0 2006.173.04:24:02.59#ibcon#enter sib2, iclass 29, count 0 2006.173.04:24:02.59#ibcon#flushed, iclass 29, count 0 2006.173.04:24:02.59#ibcon#about to write, iclass 29, count 0 2006.173.04:24:02.59#ibcon#wrote, iclass 29, count 0 2006.173.04:24:02.59#ibcon#about to read 3, iclass 29, count 0 2006.173.04:24:02.63#ibcon#read 3, iclass 29, count 0 2006.173.04:24:02.63#ibcon#about to read 4, iclass 29, count 0 2006.173.04:24:02.63#ibcon#read 4, iclass 29, count 0 2006.173.04:24:02.63#ibcon#about to read 5, iclass 29, count 0 2006.173.04:24:02.63#ibcon#read 5, iclass 29, count 0 2006.173.04:24:02.63#ibcon#about to read 6, iclass 29, count 0 2006.173.04:24:02.63#ibcon#read 6, iclass 29, count 0 2006.173.04:24:02.63#ibcon#end of sib2, iclass 29, count 0 2006.173.04:24:02.63#ibcon#*after write, iclass 29, count 0 2006.173.04:24:02.63#ibcon#*before return 0, iclass 29, count 0 2006.173.04:24:02.63#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.04:24:02.63#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.04:24:02.63#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.04:24:02.63#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.04:24:02.63$vck44/va=7,4 2006.173.04:24:02.63#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.04:24:02.63#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.04:24:02.63#ibcon#ireg 11 cls_cnt 2 2006.173.04:24:02.63#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.04:24:02.69#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.04:24:02.69#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.04:24:02.69#ibcon#enter wrdev, iclass 31, count 2 2006.173.04:24:02.69#ibcon#first serial, iclass 31, count 2 2006.173.04:24:02.69#ibcon#enter sib2, iclass 31, count 2 2006.173.04:24:02.69#ibcon#flushed, iclass 31, count 2 2006.173.04:24:02.69#ibcon#about to write, iclass 31, count 2 2006.173.04:24:02.69#ibcon#wrote, iclass 31, count 2 2006.173.04:24:02.69#ibcon#about to read 3, iclass 31, count 2 2006.173.04:24:02.71#ibcon#read 3, iclass 31, count 2 2006.173.04:24:02.71#ibcon#about to read 4, iclass 31, count 2 2006.173.04:24:02.71#ibcon#read 4, iclass 31, count 2 2006.173.04:24:02.71#ibcon#about to read 5, iclass 31, count 2 2006.173.04:24:02.71#ibcon#read 5, iclass 31, count 2 2006.173.04:24:02.71#ibcon#about to read 6, iclass 31, count 2 2006.173.04:24:02.71#ibcon#read 6, iclass 31, count 2 2006.173.04:24:02.71#ibcon#end of sib2, iclass 31, count 2 2006.173.04:24:02.71#ibcon#*mode == 0, iclass 31, count 2 2006.173.04:24:02.71#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.04:24:02.71#ibcon#[25=AT07-04\r\n] 2006.173.04:24:02.71#ibcon#*before write, iclass 31, count 2 2006.173.04:24:02.71#ibcon#enter sib2, iclass 31, count 2 2006.173.04:24:02.71#ibcon#flushed, iclass 31, count 2 2006.173.04:24:02.71#ibcon#about to write, iclass 31, count 2 2006.173.04:24:02.71#ibcon#wrote, iclass 31, count 2 2006.173.04:24:02.71#ibcon#about to read 3, iclass 31, count 2 2006.173.04:24:02.74#ibcon#read 3, iclass 31, count 2 2006.173.04:24:02.74#ibcon#about to read 4, iclass 31, count 2 2006.173.04:24:02.74#ibcon#read 4, iclass 31, count 2 2006.173.04:24:02.74#ibcon#about to read 5, iclass 31, count 2 2006.173.04:24:02.74#ibcon#read 5, iclass 31, count 2 2006.173.04:24:02.74#ibcon#about to read 6, iclass 31, count 2 2006.173.04:24:02.74#ibcon#read 6, iclass 31, count 2 2006.173.04:24:02.74#ibcon#end of sib2, iclass 31, count 2 2006.173.04:24:02.74#ibcon#*after write, iclass 31, count 2 2006.173.04:24:02.74#ibcon#*before return 0, iclass 31, count 2 2006.173.04:24:02.74#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.04:24:02.74#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.04:24:02.74#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.04:24:02.74#ibcon#ireg 7 cls_cnt 0 2006.173.04:24:02.74#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.04:24:02.86#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.04:24:02.86#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.04:24:02.86#ibcon#enter wrdev, iclass 31, count 0 2006.173.04:24:02.86#ibcon#first serial, iclass 31, count 0 2006.173.04:24:02.86#ibcon#enter sib2, iclass 31, count 0 2006.173.04:24:02.86#ibcon#flushed, iclass 31, count 0 2006.173.04:24:02.86#ibcon#about to write, iclass 31, count 0 2006.173.04:24:02.86#ibcon#wrote, iclass 31, count 0 2006.173.04:24:02.86#ibcon#about to read 3, iclass 31, count 0 2006.173.04:24:02.88#ibcon#read 3, iclass 31, count 0 2006.173.04:24:02.88#ibcon#about to read 4, iclass 31, count 0 2006.173.04:24:02.88#ibcon#read 4, iclass 31, count 0 2006.173.04:24:02.88#ibcon#about to read 5, iclass 31, count 0 2006.173.04:24:02.88#ibcon#read 5, iclass 31, count 0 2006.173.04:24:02.88#ibcon#about to read 6, iclass 31, count 0 2006.173.04:24:02.88#ibcon#read 6, iclass 31, count 0 2006.173.04:24:02.88#ibcon#end of sib2, iclass 31, count 0 2006.173.04:24:02.88#ibcon#*mode == 0, iclass 31, count 0 2006.173.04:24:02.88#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.04:24:02.88#ibcon#[25=USB\r\n] 2006.173.04:24:02.88#ibcon#*before write, iclass 31, count 0 2006.173.04:24:02.88#ibcon#enter sib2, iclass 31, count 0 2006.173.04:24:02.88#ibcon#flushed, iclass 31, count 0 2006.173.04:24:02.88#ibcon#about to write, iclass 31, count 0 2006.173.04:24:02.88#ibcon#wrote, iclass 31, count 0 2006.173.04:24:02.88#ibcon#about to read 3, iclass 31, count 0 2006.173.04:24:02.91#ibcon#read 3, iclass 31, count 0 2006.173.04:24:02.91#ibcon#about to read 4, iclass 31, count 0 2006.173.04:24:02.91#ibcon#read 4, iclass 31, count 0 2006.173.04:24:02.91#ibcon#about to read 5, iclass 31, count 0 2006.173.04:24:02.91#ibcon#read 5, iclass 31, count 0 2006.173.04:24:02.91#ibcon#about to read 6, iclass 31, count 0 2006.173.04:24:02.91#ibcon#read 6, iclass 31, count 0 2006.173.04:24:02.91#ibcon#end of sib2, iclass 31, count 0 2006.173.04:24:02.91#ibcon#*after write, iclass 31, count 0 2006.173.04:24:02.91#ibcon#*before return 0, iclass 31, count 0 2006.173.04:24:02.91#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.04:24:02.91#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.04:24:02.91#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.04:24:02.91#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.04:24:02.91$vck44/valo=8,884.99 2006.173.04:24:02.91#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.04:24:02.91#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.04:24:02.91#ibcon#ireg 17 cls_cnt 0 2006.173.04:24:02.91#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.04:24:02.91#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.04:24:02.91#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.04:24:02.91#ibcon#enter wrdev, iclass 33, count 0 2006.173.04:24:02.91#ibcon#first serial, iclass 33, count 0 2006.173.04:24:02.91#ibcon#enter sib2, iclass 33, count 0 2006.173.04:24:02.91#ibcon#flushed, iclass 33, count 0 2006.173.04:24:02.91#ibcon#about to write, iclass 33, count 0 2006.173.04:24:02.91#ibcon#wrote, iclass 33, count 0 2006.173.04:24:02.91#ibcon#about to read 3, iclass 33, count 0 2006.173.04:24:02.93#ibcon#read 3, iclass 33, count 0 2006.173.04:24:02.93#ibcon#about to read 4, iclass 33, count 0 2006.173.04:24:02.93#ibcon#read 4, iclass 33, count 0 2006.173.04:24:02.93#ibcon#about to read 5, iclass 33, count 0 2006.173.04:24:02.93#ibcon#read 5, iclass 33, count 0 2006.173.04:24:02.93#ibcon#about to read 6, iclass 33, count 0 2006.173.04:24:02.93#ibcon#read 6, iclass 33, count 0 2006.173.04:24:02.93#ibcon#end of sib2, iclass 33, count 0 2006.173.04:24:02.93#ibcon#*mode == 0, iclass 33, count 0 2006.173.04:24:02.93#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.04:24:02.93#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.04:24:02.93#ibcon#*before write, iclass 33, count 0 2006.173.04:24:02.93#ibcon#enter sib2, iclass 33, count 0 2006.173.04:24:02.93#ibcon#flushed, iclass 33, count 0 2006.173.04:24:02.93#ibcon#about to write, iclass 33, count 0 2006.173.04:24:02.93#ibcon#wrote, iclass 33, count 0 2006.173.04:24:02.93#ibcon#about to read 3, iclass 33, count 0 2006.173.04:24:02.97#ibcon#read 3, iclass 33, count 0 2006.173.04:24:02.97#ibcon#about to read 4, iclass 33, count 0 2006.173.04:24:02.97#ibcon#read 4, iclass 33, count 0 2006.173.04:24:02.97#ibcon#about to read 5, iclass 33, count 0 2006.173.04:24:02.97#ibcon#read 5, iclass 33, count 0 2006.173.04:24:02.97#ibcon#about to read 6, iclass 33, count 0 2006.173.04:24:02.97#ibcon#read 6, iclass 33, count 0 2006.173.04:24:02.97#ibcon#end of sib2, iclass 33, count 0 2006.173.04:24:02.97#ibcon#*after write, iclass 33, count 0 2006.173.04:24:02.97#ibcon#*before return 0, iclass 33, count 0 2006.173.04:24:02.97#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.04:24:02.97#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.04:24:02.97#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.04:24:02.97#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.04:24:02.97$vck44/va=8,4 2006.173.04:24:02.97#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.04:24:02.97#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.04:24:02.97#ibcon#ireg 11 cls_cnt 2 2006.173.04:24:02.97#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.04:24:03.03#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.04:24:03.03#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.04:24:03.03#ibcon#enter wrdev, iclass 35, count 2 2006.173.04:24:03.03#ibcon#first serial, iclass 35, count 2 2006.173.04:24:03.03#ibcon#enter sib2, iclass 35, count 2 2006.173.04:24:03.03#ibcon#flushed, iclass 35, count 2 2006.173.04:24:03.03#ibcon#about to write, iclass 35, count 2 2006.173.04:24:03.03#ibcon#wrote, iclass 35, count 2 2006.173.04:24:03.03#ibcon#about to read 3, iclass 35, count 2 2006.173.04:24:03.05#ibcon#read 3, iclass 35, count 2 2006.173.04:24:03.05#ibcon#about to read 4, iclass 35, count 2 2006.173.04:24:03.05#ibcon#read 4, iclass 35, count 2 2006.173.04:24:03.05#ibcon#about to read 5, iclass 35, count 2 2006.173.04:24:03.05#ibcon#read 5, iclass 35, count 2 2006.173.04:24:03.05#ibcon#about to read 6, iclass 35, count 2 2006.173.04:24:03.05#ibcon#read 6, iclass 35, count 2 2006.173.04:24:03.05#ibcon#end of sib2, iclass 35, count 2 2006.173.04:24:03.05#ibcon#*mode == 0, iclass 35, count 2 2006.173.04:24:03.05#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.04:24:03.05#ibcon#[25=AT08-04\r\n] 2006.173.04:24:03.05#ibcon#*before write, iclass 35, count 2 2006.173.04:24:03.05#ibcon#enter sib2, iclass 35, count 2 2006.173.04:24:03.05#ibcon#flushed, iclass 35, count 2 2006.173.04:24:03.05#ibcon#about to write, iclass 35, count 2 2006.173.04:24:03.05#ibcon#wrote, iclass 35, count 2 2006.173.04:24:03.05#ibcon#about to read 3, iclass 35, count 2 2006.173.04:24:03.08#ibcon#read 3, iclass 35, count 2 2006.173.04:24:03.08#ibcon#about to read 4, iclass 35, count 2 2006.173.04:24:03.08#ibcon#read 4, iclass 35, count 2 2006.173.04:24:03.08#ibcon#about to read 5, iclass 35, count 2 2006.173.04:24:03.08#ibcon#read 5, iclass 35, count 2 2006.173.04:24:03.08#ibcon#about to read 6, iclass 35, count 2 2006.173.04:24:03.08#ibcon#read 6, iclass 35, count 2 2006.173.04:24:03.08#ibcon#end of sib2, iclass 35, count 2 2006.173.04:24:03.08#ibcon#*after write, iclass 35, count 2 2006.173.04:24:03.08#ibcon#*before return 0, iclass 35, count 2 2006.173.04:24:03.08#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.04:24:03.08#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.04:24:03.08#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.04:24:03.08#ibcon#ireg 7 cls_cnt 0 2006.173.04:24:03.08#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.04:24:03.20#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.04:24:03.20#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.04:24:03.20#ibcon#enter wrdev, iclass 35, count 0 2006.173.04:24:03.20#ibcon#first serial, iclass 35, count 0 2006.173.04:24:03.20#ibcon#enter sib2, iclass 35, count 0 2006.173.04:24:03.20#ibcon#flushed, iclass 35, count 0 2006.173.04:24:03.20#ibcon#about to write, iclass 35, count 0 2006.173.04:24:03.20#ibcon#wrote, iclass 35, count 0 2006.173.04:24:03.20#ibcon#about to read 3, iclass 35, count 0 2006.173.04:24:03.22#ibcon#read 3, iclass 35, count 0 2006.173.04:24:03.22#ibcon#about to read 4, iclass 35, count 0 2006.173.04:24:03.22#ibcon#read 4, iclass 35, count 0 2006.173.04:24:03.22#ibcon#about to read 5, iclass 35, count 0 2006.173.04:24:03.22#ibcon#read 5, iclass 35, count 0 2006.173.04:24:03.22#ibcon#about to read 6, iclass 35, count 0 2006.173.04:24:03.22#ibcon#read 6, iclass 35, count 0 2006.173.04:24:03.22#ibcon#end of sib2, iclass 35, count 0 2006.173.04:24:03.22#ibcon#*mode == 0, iclass 35, count 0 2006.173.04:24:03.22#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.04:24:03.22#ibcon#[25=USB\r\n] 2006.173.04:24:03.22#ibcon#*before write, iclass 35, count 0 2006.173.04:24:03.22#ibcon#enter sib2, iclass 35, count 0 2006.173.04:24:03.22#ibcon#flushed, iclass 35, count 0 2006.173.04:24:03.22#ibcon#about to write, iclass 35, count 0 2006.173.04:24:03.22#ibcon#wrote, iclass 35, count 0 2006.173.04:24:03.22#ibcon#about to read 3, iclass 35, count 0 2006.173.04:24:03.25#ibcon#read 3, iclass 35, count 0 2006.173.04:24:03.25#ibcon#about to read 4, iclass 35, count 0 2006.173.04:24:03.25#ibcon#read 4, iclass 35, count 0 2006.173.04:24:03.25#ibcon#about to read 5, iclass 35, count 0 2006.173.04:24:03.25#ibcon#read 5, iclass 35, count 0 2006.173.04:24:03.25#ibcon#about to read 6, iclass 35, count 0 2006.173.04:24:03.25#ibcon#read 6, iclass 35, count 0 2006.173.04:24:03.25#ibcon#end of sib2, iclass 35, count 0 2006.173.04:24:03.25#ibcon#*after write, iclass 35, count 0 2006.173.04:24:03.25#ibcon#*before return 0, iclass 35, count 0 2006.173.04:24:03.25#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.04:24:03.25#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.04:24:03.25#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.04:24:03.25#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.04:24:03.25$vck44/vblo=1,629.99 2006.173.04:24:03.25#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.04:24:03.25#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.04:24:03.25#ibcon#ireg 17 cls_cnt 0 2006.173.04:24:03.25#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.04:24:03.25#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.04:24:03.25#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.04:24:03.25#ibcon#enter wrdev, iclass 37, count 0 2006.173.04:24:03.25#ibcon#first serial, iclass 37, count 0 2006.173.04:24:03.25#ibcon#enter sib2, iclass 37, count 0 2006.173.04:24:03.25#ibcon#flushed, iclass 37, count 0 2006.173.04:24:03.25#ibcon#about to write, iclass 37, count 0 2006.173.04:24:03.25#ibcon#wrote, iclass 37, count 0 2006.173.04:24:03.25#ibcon#about to read 3, iclass 37, count 0 2006.173.04:24:03.27#ibcon#read 3, iclass 37, count 0 2006.173.04:24:03.27#ibcon#about to read 4, iclass 37, count 0 2006.173.04:24:03.27#ibcon#read 4, iclass 37, count 0 2006.173.04:24:03.27#ibcon#about to read 5, iclass 37, count 0 2006.173.04:24:03.27#ibcon#read 5, iclass 37, count 0 2006.173.04:24:03.27#ibcon#about to read 6, iclass 37, count 0 2006.173.04:24:03.27#ibcon#read 6, iclass 37, count 0 2006.173.04:24:03.27#ibcon#end of sib2, iclass 37, count 0 2006.173.04:24:03.27#ibcon#*mode == 0, iclass 37, count 0 2006.173.04:24:03.27#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.04:24:03.27#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.04:24:03.27#ibcon#*before write, iclass 37, count 0 2006.173.04:24:03.27#ibcon#enter sib2, iclass 37, count 0 2006.173.04:24:03.27#ibcon#flushed, iclass 37, count 0 2006.173.04:24:03.27#ibcon#about to write, iclass 37, count 0 2006.173.04:24:03.27#ibcon#wrote, iclass 37, count 0 2006.173.04:24:03.27#ibcon#about to read 3, iclass 37, count 0 2006.173.04:24:03.31#ibcon#read 3, iclass 37, count 0 2006.173.04:24:03.31#ibcon#about to read 4, iclass 37, count 0 2006.173.04:24:03.31#ibcon#read 4, iclass 37, count 0 2006.173.04:24:03.31#ibcon#about to read 5, iclass 37, count 0 2006.173.04:24:03.31#ibcon#read 5, iclass 37, count 0 2006.173.04:24:03.31#ibcon#about to read 6, iclass 37, count 0 2006.173.04:24:03.31#ibcon#read 6, iclass 37, count 0 2006.173.04:24:03.31#ibcon#end of sib2, iclass 37, count 0 2006.173.04:24:03.31#ibcon#*after write, iclass 37, count 0 2006.173.04:24:03.31#ibcon#*before return 0, iclass 37, count 0 2006.173.04:24:03.31#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.04:24:03.31#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.04:24:03.31#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.04:24:03.31#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.04:24:03.31$vck44/vb=1,4 2006.173.04:24:03.31#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.04:24:03.31#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.04:24:03.31#ibcon#ireg 11 cls_cnt 2 2006.173.04:24:03.31#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.04:24:03.31#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.04:24:03.31#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.04:24:03.31#ibcon#enter wrdev, iclass 39, count 2 2006.173.04:24:03.31#ibcon#first serial, iclass 39, count 2 2006.173.04:24:03.31#ibcon#enter sib2, iclass 39, count 2 2006.173.04:24:03.31#ibcon#flushed, iclass 39, count 2 2006.173.04:24:03.31#ibcon#about to write, iclass 39, count 2 2006.173.04:24:03.31#ibcon#wrote, iclass 39, count 2 2006.173.04:24:03.31#ibcon#about to read 3, iclass 39, count 2 2006.173.04:24:03.33#ibcon#read 3, iclass 39, count 2 2006.173.04:24:03.33#ibcon#about to read 4, iclass 39, count 2 2006.173.04:24:03.33#ibcon#read 4, iclass 39, count 2 2006.173.04:24:03.33#ibcon#about to read 5, iclass 39, count 2 2006.173.04:24:03.33#ibcon#read 5, iclass 39, count 2 2006.173.04:24:03.33#ibcon#about to read 6, iclass 39, count 2 2006.173.04:24:03.33#ibcon#read 6, iclass 39, count 2 2006.173.04:24:03.33#ibcon#end of sib2, iclass 39, count 2 2006.173.04:24:03.33#ibcon#*mode == 0, iclass 39, count 2 2006.173.04:24:03.33#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.04:24:03.33#ibcon#[27=AT01-04\r\n] 2006.173.04:24:03.33#ibcon#*before write, iclass 39, count 2 2006.173.04:24:03.33#ibcon#enter sib2, iclass 39, count 2 2006.173.04:24:03.33#ibcon#flushed, iclass 39, count 2 2006.173.04:24:03.33#ibcon#about to write, iclass 39, count 2 2006.173.04:24:03.33#ibcon#wrote, iclass 39, count 2 2006.173.04:24:03.33#ibcon#about to read 3, iclass 39, count 2 2006.173.04:24:03.36#ibcon#read 3, iclass 39, count 2 2006.173.04:24:03.36#ibcon#about to read 4, iclass 39, count 2 2006.173.04:24:03.36#ibcon#read 4, iclass 39, count 2 2006.173.04:24:03.36#ibcon#about to read 5, iclass 39, count 2 2006.173.04:24:03.36#ibcon#read 5, iclass 39, count 2 2006.173.04:24:03.36#ibcon#about to read 6, iclass 39, count 2 2006.173.04:24:03.36#ibcon#read 6, iclass 39, count 2 2006.173.04:24:03.36#ibcon#end of sib2, iclass 39, count 2 2006.173.04:24:03.36#ibcon#*after write, iclass 39, count 2 2006.173.04:24:03.36#ibcon#*before return 0, iclass 39, count 2 2006.173.04:24:03.36#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.04:24:03.36#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.04:24:03.36#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.04:24:03.36#ibcon#ireg 7 cls_cnt 0 2006.173.04:24:03.36#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.04:24:03.48#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.04:24:03.48#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.04:24:03.48#ibcon#enter wrdev, iclass 39, count 0 2006.173.04:24:03.48#ibcon#first serial, iclass 39, count 0 2006.173.04:24:03.48#ibcon#enter sib2, iclass 39, count 0 2006.173.04:24:03.48#ibcon#flushed, iclass 39, count 0 2006.173.04:24:03.48#ibcon#about to write, iclass 39, count 0 2006.173.04:24:03.48#ibcon#wrote, iclass 39, count 0 2006.173.04:24:03.48#ibcon#about to read 3, iclass 39, count 0 2006.173.04:24:03.50#ibcon#read 3, iclass 39, count 0 2006.173.04:24:03.50#ibcon#about to read 4, iclass 39, count 0 2006.173.04:24:03.50#ibcon#read 4, iclass 39, count 0 2006.173.04:24:03.50#ibcon#about to read 5, iclass 39, count 0 2006.173.04:24:03.50#ibcon#read 5, iclass 39, count 0 2006.173.04:24:03.50#ibcon#about to read 6, iclass 39, count 0 2006.173.04:24:03.50#ibcon#read 6, iclass 39, count 0 2006.173.04:24:03.50#ibcon#end of sib2, iclass 39, count 0 2006.173.04:24:03.50#ibcon#*mode == 0, iclass 39, count 0 2006.173.04:24:03.50#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.04:24:03.50#ibcon#[27=USB\r\n] 2006.173.04:24:03.50#ibcon#*before write, iclass 39, count 0 2006.173.04:24:03.50#ibcon#enter sib2, iclass 39, count 0 2006.173.04:24:03.50#ibcon#flushed, iclass 39, count 0 2006.173.04:24:03.50#ibcon#about to write, iclass 39, count 0 2006.173.04:24:03.50#ibcon#wrote, iclass 39, count 0 2006.173.04:24:03.50#ibcon#about to read 3, iclass 39, count 0 2006.173.04:24:03.53#ibcon#read 3, iclass 39, count 0 2006.173.04:24:03.53#ibcon#about to read 4, iclass 39, count 0 2006.173.04:24:03.53#ibcon#read 4, iclass 39, count 0 2006.173.04:24:03.53#ibcon#about to read 5, iclass 39, count 0 2006.173.04:24:03.53#ibcon#read 5, iclass 39, count 0 2006.173.04:24:03.53#ibcon#about to read 6, iclass 39, count 0 2006.173.04:24:03.53#ibcon#read 6, iclass 39, count 0 2006.173.04:24:03.53#ibcon#end of sib2, iclass 39, count 0 2006.173.04:24:03.53#ibcon#*after write, iclass 39, count 0 2006.173.04:24:03.53#ibcon#*before return 0, iclass 39, count 0 2006.173.04:24:03.53#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.04:24:03.53#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.04:24:03.53#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.04:24:03.53#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.04:24:03.53$vck44/vblo=2,634.99 2006.173.04:24:03.53#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.04:24:03.53#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.04:24:03.53#ibcon#ireg 17 cls_cnt 0 2006.173.04:24:03.53#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.04:24:03.53#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.04:24:03.53#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.04:24:03.53#ibcon#enter wrdev, iclass 3, count 0 2006.173.04:24:03.53#ibcon#first serial, iclass 3, count 0 2006.173.04:24:03.53#ibcon#enter sib2, iclass 3, count 0 2006.173.04:24:03.53#ibcon#flushed, iclass 3, count 0 2006.173.04:24:03.53#ibcon#about to write, iclass 3, count 0 2006.173.04:24:03.53#ibcon#wrote, iclass 3, count 0 2006.173.04:24:03.53#ibcon#about to read 3, iclass 3, count 0 2006.173.04:24:03.55#ibcon#read 3, iclass 3, count 0 2006.173.04:24:03.55#ibcon#about to read 4, iclass 3, count 0 2006.173.04:24:03.55#ibcon#read 4, iclass 3, count 0 2006.173.04:24:03.55#ibcon#about to read 5, iclass 3, count 0 2006.173.04:24:03.55#ibcon#read 5, iclass 3, count 0 2006.173.04:24:03.55#ibcon#about to read 6, iclass 3, count 0 2006.173.04:24:03.55#ibcon#read 6, iclass 3, count 0 2006.173.04:24:03.55#ibcon#end of sib2, iclass 3, count 0 2006.173.04:24:03.55#ibcon#*mode == 0, iclass 3, count 0 2006.173.04:24:03.55#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.04:24:03.55#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.04:24:03.55#ibcon#*before write, iclass 3, count 0 2006.173.04:24:03.55#ibcon#enter sib2, iclass 3, count 0 2006.173.04:24:03.55#ibcon#flushed, iclass 3, count 0 2006.173.04:24:03.55#ibcon#about to write, iclass 3, count 0 2006.173.04:24:03.55#ibcon#wrote, iclass 3, count 0 2006.173.04:24:03.55#ibcon#about to read 3, iclass 3, count 0 2006.173.04:24:03.59#ibcon#read 3, iclass 3, count 0 2006.173.04:24:03.59#ibcon#about to read 4, iclass 3, count 0 2006.173.04:24:03.59#ibcon#read 4, iclass 3, count 0 2006.173.04:24:03.59#ibcon#about to read 5, iclass 3, count 0 2006.173.04:24:03.59#ibcon#read 5, iclass 3, count 0 2006.173.04:24:03.59#ibcon#about to read 6, iclass 3, count 0 2006.173.04:24:03.59#ibcon#read 6, iclass 3, count 0 2006.173.04:24:03.59#ibcon#end of sib2, iclass 3, count 0 2006.173.04:24:03.59#ibcon#*after write, iclass 3, count 0 2006.173.04:24:03.59#ibcon#*before return 0, iclass 3, count 0 2006.173.04:24:03.59#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.04:24:03.59#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.04:24:03.59#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.04:24:03.59#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.04:24:03.59$vck44/vb=2,4 2006.173.04:24:03.59#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.04:24:03.59#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.04:24:03.59#ibcon#ireg 11 cls_cnt 2 2006.173.04:24:03.59#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.04:24:03.65#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.04:24:03.65#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.04:24:03.65#ibcon#enter wrdev, iclass 5, count 2 2006.173.04:24:03.65#ibcon#first serial, iclass 5, count 2 2006.173.04:24:03.65#ibcon#enter sib2, iclass 5, count 2 2006.173.04:24:03.65#ibcon#flushed, iclass 5, count 2 2006.173.04:24:03.65#ibcon#about to write, iclass 5, count 2 2006.173.04:24:03.65#ibcon#wrote, iclass 5, count 2 2006.173.04:24:03.65#ibcon#about to read 3, iclass 5, count 2 2006.173.04:24:03.67#ibcon#read 3, iclass 5, count 2 2006.173.04:24:03.67#ibcon#about to read 4, iclass 5, count 2 2006.173.04:24:03.67#ibcon#read 4, iclass 5, count 2 2006.173.04:24:03.67#ibcon#about to read 5, iclass 5, count 2 2006.173.04:24:03.67#ibcon#read 5, iclass 5, count 2 2006.173.04:24:03.67#ibcon#about to read 6, iclass 5, count 2 2006.173.04:24:03.67#ibcon#read 6, iclass 5, count 2 2006.173.04:24:03.67#ibcon#end of sib2, iclass 5, count 2 2006.173.04:24:03.67#ibcon#*mode == 0, iclass 5, count 2 2006.173.04:24:03.67#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.04:24:03.67#ibcon#[27=AT02-04\r\n] 2006.173.04:24:03.67#ibcon#*before write, iclass 5, count 2 2006.173.04:24:03.67#ibcon#enter sib2, iclass 5, count 2 2006.173.04:24:03.67#ibcon#flushed, iclass 5, count 2 2006.173.04:24:03.67#ibcon#about to write, iclass 5, count 2 2006.173.04:24:03.67#ibcon#wrote, iclass 5, count 2 2006.173.04:24:03.67#ibcon#about to read 3, iclass 5, count 2 2006.173.04:24:03.70#ibcon#read 3, iclass 5, count 2 2006.173.04:24:03.70#ibcon#about to read 4, iclass 5, count 2 2006.173.04:24:03.70#ibcon#read 4, iclass 5, count 2 2006.173.04:24:03.70#ibcon#about to read 5, iclass 5, count 2 2006.173.04:24:03.70#ibcon#read 5, iclass 5, count 2 2006.173.04:24:03.70#ibcon#about to read 6, iclass 5, count 2 2006.173.04:24:03.70#ibcon#read 6, iclass 5, count 2 2006.173.04:24:03.70#ibcon#end of sib2, iclass 5, count 2 2006.173.04:24:03.70#ibcon#*after write, iclass 5, count 2 2006.173.04:24:03.70#ibcon#*before return 0, iclass 5, count 2 2006.173.04:24:03.70#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.04:24:03.70#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.04:24:03.70#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.04:24:03.70#ibcon#ireg 7 cls_cnt 0 2006.173.04:24:03.70#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.04:24:03.82#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.04:24:03.82#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.04:24:03.82#ibcon#enter wrdev, iclass 5, count 0 2006.173.04:24:03.82#ibcon#first serial, iclass 5, count 0 2006.173.04:24:03.82#ibcon#enter sib2, iclass 5, count 0 2006.173.04:24:03.82#ibcon#flushed, iclass 5, count 0 2006.173.04:24:03.82#ibcon#about to write, iclass 5, count 0 2006.173.04:24:03.82#ibcon#wrote, iclass 5, count 0 2006.173.04:24:03.82#ibcon#about to read 3, iclass 5, count 0 2006.173.04:24:03.84#ibcon#read 3, iclass 5, count 0 2006.173.04:24:03.84#ibcon#about to read 4, iclass 5, count 0 2006.173.04:24:03.84#ibcon#read 4, iclass 5, count 0 2006.173.04:24:03.84#ibcon#about to read 5, iclass 5, count 0 2006.173.04:24:03.84#ibcon#read 5, iclass 5, count 0 2006.173.04:24:03.84#ibcon#about to read 6, iclass 5, count 0 2006.173.04:24:03.84#ibcon#read 6, iclass 5, count 0 2006.173.04:24:03.84#ibcon#end of sib2, iclass 5, count 0 2006.173.04:24:03.84#ibcon#*mode == 0, iclass 5, count 0 2006.173.04:24:03.84#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.04:24:03.84#ibcon#[27=USB\r\n] 2006.173.04:24:03.84#ibcon#*before write, iclass 5, count 0 2006.173.04:24:03.84#ibcon#enter sib2, iclass 5, count 0 2006.173.04:24:03.84#ibcon#flushed, iclass 5, count 0 2006.173.04:24:03.84#ibcon#about to write, iclass 5, count 0 2006.173.04:24:03.84#ibcon#wrote, iclass 5, count 0 2006.173.04:24:03.84#ibcon#about to read 3, iclass 5, count 0 2006.173.04:24:03.87#ibcon#read 3, iclass 5, count 0 2006.173.04:24:03.87#ibcon#about to read 4, iclass 5, count 0 2006.173.04:24:03.87#ibcon#read 4, iclass 5, count 0 2006.173.04:24:03.87#ibcon#about to read 5, iclass 5, count 0 2006.173.04:24:03.87#ibcon#read 5, iclass 5, count 0 2006.173.04:24:03.87#ibcon#about to read 6, iclass 5, count 0 2006.173.04:24:03.87#ibcon#read 6, iclass 5, count 0 2006.173.04:24:03.87#ibcon#end of sib2, iclass 5, count 0 2006.173.04:24:03.87#ibcon#*after write, iclass 5, count 0 2006.173.04:24:03.87#ibcon#*before return 0, iclass 5, count 0 2006.173.04:24:03.87#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.04:24:03.87#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.04:24:03.87#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.04:24:03.87#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.04:24:03.87$vck44/vblo=3,649.99 2006.173.04:24:03.87#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.04:24:03.87#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.04:24:03.87#ibcon#ireg 17 cls_cnt 0 2006.173.04:24:03.87#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.04:24:03.87#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.04:24:03.87#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.04:24:03.87#ibcon#enter wrdev, iclass 7, count 0 2006.173.04:24:03.87#ibcon#first serial, iclass 7, count 0 2006.173.04:24:03.87#ibcon#enter sib2, iclass 7, count 0 2006.173.04:24:03.87#ibcon#flushed, iclass 7, count 0 2006.173.04:24:03.87#ibcon#about to write, iclass 7, count 0 2006.173.04:24:03.87#ibcon#wrote, iclass 7, count 0 2006.173.04:24:03.87#ibcon#about to read 3, iclass 7, count 0 2006.173.04:24:03.89#ibcon#read 3, iclass 7, count 0 2006.173.04:24:03.89#ibcon#about to read 4, iclass 7, count 0 2006.173.04:24:03.89#ibcon#read 4, iclass 7, count 0 2006.173.04:24:03.89#ibcon#about to read 5, iclass 7, count 0 2006.173.04:24:03.89#ibcon#read 5, iclass 7, count 0 2006.173.04:24:03.89#ibcon#about to read 6, iclass 7, count 0 2006.173.04:24:03.89#ibcon#read 6, iclass 7, count 0 2006.173.04:24:03.89#ibcon#end of sib2, iclass 7, count 0 2006.173.04:24:03.89#ibcon#*mode == 0, iclass 7, count 0 2006.173.04:24:03.89#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.04:24:03.89#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.04:24:03.89#ibcon#*before write, iclass 7, count 0 2006.173.04:24:03.89#ibcon#enter sib2, iclass 7, count 0 2006.173.04:24:03.89#ibcon#flushed, iclass 7, count 0 2006.173.04:24:03.89#ibcon#about to write, iclass 7, count 0 2006.173.04:24:03.89#ibcon#wrote, iclass 7, count 0 2006.173.04:24:03.89#ibcon#about to read 3, iclass 7, count 0 2006.173.04:24:03.93#ibcon#read 3, iclass 7, count 0 2006.173.04:24:03.93#ibcon#about to read 4, iclass 7, count 0 2006.173.04:24:03.93#ibcon#read 4, iclass 7, count 0 2006.173.04:24:03.93#ibcon#about to read 5, iclass 7, count 0 2006.173.04:24:03.93#ibcon#read 5, iclass 7, count 0 2006.173.04:24:03.93#ibcon#about to read 6, iclass 7, count 0 2006.173.04:24:03.93#ibcon#read 6, iclass 7, count 0 2006.173.04:24:03.93#ibcon#end of sib2, iclass 7, count 0 2006.173.04:24:03.93#ibcon#*after write, iclass 7, count 0 2006.173.04:24:03.93#ibcon#*before return 0, iclass 7, count 0 2006.173.04:24:03.93#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.04:24:03.93#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.04:24:03.93#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.04:24:03.93#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.04:24:03.93$vck44/vb=3,4 2006.173.04:24:03.93#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.04:24:03.93#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.04:24:03.93#ibcon#ireg 11 cls_cnt 2 2006.173.04:24:03.93#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.04:24:03.99#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.04:24:03.99#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.04:24:03.99#ibcon#enter wrdev, iclass 11, count 2 2006.173.04:24:03.99#ibcon#first serial, iclass 11, count 2 2006.173.04:24:03.99#ibcon#enter sib2, iclass 11, count 2 2006.173.04:24:03.99#ibcon#flushed, iclass 11, count 2 2006.173.04:24:03.99#ibcon#about to write, iclass 11, count 2 2006.173.04:24:03.99#ibcon#wrote, iclass 11, count 2 2006.173.04:24:03.99#ibcon#about to read 3, iclass 11, count 2 2006.173.04:24:04.01#ibcon#read 3, iclass 11, count 2 2006.173.04:24:04.01#ibcon#about to read 4, iclass 11, count 2 2006.173.04:24:04.01#ibcon#read 4, iclass 11, count 2 2006.173.04:24:04.01#ibcon#about to read 5, iclass 11, count 2 2006.173.04:24:04.01#ibcon#read 5, iclass 11, count 2 2006.173.04:24:04.01#ibcon#about to read 6, iclass 11, count 2 2006.173.04:24:04.01#ibcon#read 6, iclass 11, count 2 2006.173.04:24:04.01#ibcon#end of sib2, iclass 11, count 2 2006.173.04:24:04.01#ibcon#*mode == 0, iclass 11, count 2 2006.173.04:24:04.01#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.04:24:04.01#ibcon#[27=AT03-04\r\n] 2006.173.04:24:04.01#ibcon#*before write, iclass 11, count 2 2006.173.04:24:04.01#ibcon#enter sib2, iclass 11, count 2 2006.173.04:24:04.01#ibcon#flushed, iclass 11, count 2 2006.173.04:24:04.01#ibcon#about to write, iclass 11, count 2 2006.173.04:24:04.01#ibcon#wrote, iclass 11, count 2 2006.173.04:24:04.01#ibcon#about to read 3, iclass 11, count 2 2006.173.04:24:04.04#ibcon#read 3, iclass 11, count 2 2006.173.04:24:04.04#ibcon#about to read 4, iclass 11, count 2 2006.173.04:24:04.04#ibcon#read 4, iclass 11, count 2 2006.173.04:24:04.04#ibcon#about to read 5, iclass 11, count 2 2006.173.04:24:04.04#ibcon#read 5, iclass 11, count 2 2006.173.04:24:04.04#ibcon#about to read 6, iclass 11, count 2 2006.173.04:24:04.04#ibcon#read 6, iclass 11, count 2 2006.173.04:24:04.04#ibcon#end of sib2, iclass 11, count 2 2006.173.04:24:04.04#ibcon#*after write, iclass 11, count 2 2006.173.04:24:04.04#ibcon#*before return 0, iclass 11, count 2 2006.173.04:24:04.04#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.04:24:04.04#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.04:24:04.04#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.04:24:04.04#ibcon#ireg 7 cls_cnt 0 2006.173.04:24:04.04#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.04:24:04.16#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.04:24:04.16#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.04:24:04.16#ibcon#enter wrdev, iclass 11, count 0 2006.173.04:24:04.16#ibcon#first serial, iclass 11, count 0 2006.173.04:24:04.16#ibcon#enter sib2, iclass 11, count 0 2006.173.04:24:04.16#ibcon#flushed, iclass 11, count 0 2006.173.04:24:04.16#ibcon#about to write, iclass 11, count 0 2006.173.04:24:04.16#ibcon#wrote, iclass 11, count 0 2006.173.04:24:04.16#ibcon#about to read 3, iclass 11, count 0 2006.173.04:24:04.18#ibcon#read 3, iclass 11, count 0 2006.173.04:24:04.18#ibcon#about to read 4, iclass 11, count 0 2006.173.04:24:04.18#ibcon#read 4, iclass 11, count 0 2006.173.04:24:04.18#ibcon#about to read 5, iclass 11, count 0 2006.173.04:24:04.18#ibcon#read 5, iclass 11, count 0 2006.173.04:24:04.18#ibcon#about to read 6, iclass 11, count 0 2006.173.04:24:04.18#ibcon#read 6, iclass 11, count 0 2006.173.04:24:04.18#ibcon#end of sib2, iclass 11, count 0 2006.173.04:24:04.18#ibcon#*mode == 0, iclass 11, count 0 2006.173.04:24:04.18#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.04:24:04.18#ibcon#[27=USB\r\n] 2006.173.04:24:04.18#ibcon#*before write, iclass 11, count 0 2006.173.04:24:04.18#ibcon#enter sib2, iclass 11, count 0 2006.173.04:24:04.18#ibcon#flushed, iclass 11, count 0 2006.173.04:24:04.18#ibcon#about to write, iclass 11, count 0 2006.173.04:24:04.18#ibcon#wrote, iclass 11, count 0 2006.173.04:24:04.18#ibcon#about to read 3, iclass 11, count 0 2006.173.04:24:04.21#ibcon#read 3, iclass 11, count 0 2006.173.04:24:04.21#ibcon#about to read 4, iclass 11, count 0 2006.173.04:24:04.21#ibcon#read 4, iclass 11, count 0 2006.173.04:24:04.21#ibcon#about to read 5, iclass 11, count 0 2006.173.04:24:04.21#ibcon#read 5, iclass 11, count 0 2006.173.04:24:04.21#ibcon#about to read 6, iclass 11, count 0 2006.173.04:24:04.21#ibcon#read 6, iclass 11, count 0 2006.173.04:24:04.21#ibcon#end of sib2, iclass 11, count 0 2006.173.04:24:04.21#ibcon#*after write, iclass 11, count 0 2006.173.04:24:04.21#ibcon#*before return 0, iclass 11, count 0 2006.173.04:24:04.21#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.04:24:04.21#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.04:24:04.21#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.04:24:04.21#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.04:24:04.21$vck44/vblo=4,679.99 2006.173.04:24:04.21#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.04:24:04.21#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.04:24:04.21#ibcon#ireg 17 cls_cnt 0 2006.173.04:24:04.21#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.04:24:04.21#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.04:24:04.21#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.04:24:04.21#ibcon#enter wrdev, iclass 13, count 0 2006.173.04:24:04.21#ibcon#first serial, iclass 13, count 0 2006.173.04:24:04.21#ibcon#enter sib2, iclass 13, count 0 2006.173.04:24:04.21#ibcon#flushed, iclass 13, count 0 2006.173.04:24:04.21#ibcon#about to write, iclass 13, count 0 2006.173.04:24:04.21#ibcon#wrote, iclass 13, count 0 2006.173.04:24:04.21#ibcon#about to read 3, iclass 13, count 0 2006.173.04:24:04.23#ibcon#read 3, iclass 13, count 0 2006.173.04:24:04.23#ibcon#about to read 4, iclass 13, count 0 2006.173.04:24:04.23#ibcon#read 4, iclass 13, count 0 2006.173.04:24:04.23#ibcon#about to read 5, iclass 13, count 0 2006.173.04:24:04.23#ibcon#read 5, iclass 13, count 0 2006.173.04:24:04.23#ibcon#about to read 6, iclass 13, count 0 2006.173.04:24:04.23#ibcon#read 6, iclass 13, count 0 2006.173.04:24:04.23#ibcon#end of sib2, iclass 13, count 0 2006.173.04:24:04.23#ibcon#*mode == 0, iclass 13, count 0 2006.173.04:24:04.23#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.04:24:04.23#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.04:24:04.23#ibcon#*before write, iclass 13, count 0 2006.173.04:24:04.23#ibcon#enter sib2, iclass 13, count 0 2006.173.04:24:04.23#ibcon#flushed, iclass 13, count 0 2006.173.04:24:04.23#ibcon#about to write, iclass 13, count 0 2006.173.04:24:04.23#ibcon#wrote, iclass 13, count 0 2006.173.04:24:04.23#ibcon#about to read 3, iclass 13, count 0 2006.173.04:24:04.27#ibcon#read 3, iclass 13, count 0 2006.173.04:24:04.27#ibcon#about to read 4, iclass 13, count 0 2006.173.04:24:04.27#ibcon#read 4, iclass 13, count 0 2006.173.04:24:04.27#ibcon#about to read 5, iclass 13, count 0 2006.173.04:24:04.27#ibcon#read 5, iclass 13, count 0 2006.173.04:24:04.27#ibcon#about to read 6, iclass 13, count 0 2006.173.04:24:04.27#ibcon#read 6, iclass 13, count 0 2006.173.04:24:04.27#ibcon#end of sib2, iclass 13, count 0 2006.173.04:24:04.27#ibcon#*after write, iclass 13, count 0 2006.173.04:24:04.27#ibcon#*before return 0, iclass 13, count 0 2006.173.04:24:04.27#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.04:24:04.27#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.04:24:04.27#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.04:24:04.27#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.04:24:04.27$vck44/vb=4,4 2006.173.04:24:04.27#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.04:24:04.27#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.04:24:04.27#ibcon#ireg 11 cls_cnt 2 2006.173.04:24:04.27#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.04:24:04.33#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.04:24:04.33#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.04:24:04.33#ibcon#enter wrdev, iclass 15, count 2 2006.173.04:24:04.33#ibcon#first serial, iclass 15, count 2 2006.173.04:24:04.33#ibcon#enter sib2, iclass 15, count 2 2006.173.04:24:04.33#ibcon#flushed, iclass 15, count 2 2006.173.04:24:04.33#ibcon#about to write, iclass 15, count 2 2006.173.04:24:04.33#ibcon#wrote, iclass 15, count 2 2006.173.04:24:04.33#ibcon#about to read 3, iclass 15, count 2 2006.173.04:24:04.35#ibcon#read 3, iclass 15, count 2 2006.173.04:24:04.35#ibcon#about to read 4, iclass 15, count 2 2006.173.04:24:04.35#ibcon#read 4, iclass 15, count 2 2006.173.04:24:04.35#ibcon#about to read 5, iclass 15, count 2 2006.173.04:24:04.35#ibcon#read 5, iclass 15, count 2 2006.173.04:24:04.35#ibcon#about to read 6, iclass 15, count 2 2006.173.04:24:04.35#ibcon#read 6, iclass 15, count 2 2006.173.04:24:04.35#ibcon#end of sib2, iclass 15, count 2 2006.173.04:24:04.35#ibcon#*mode == 0, iclass 15, count 2 2006.173.04:24:04.35#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.04:24:04.35#ibcon#[27=AT04-04\r\n] 2006.173.04:24:04.35#ibcon#*before write, iclass 15, count 2 2006.173.04:24:04.35#ibcon#enter sib2, iclass 15, count 2 2006.173.04:24:04.35#ibcon#flushed, iclass 15, count 2 2006.173.04:24:04.35#ibcon#about to write, iclass 15, count 2 2006.173.04:24:04.35#ibcon#wrote, iclass 15, count 2 2006.173.04:24:04.35#ibcon#about to read 3, iclass 15, count 2 2006.173.04:24:04.38#ibcon#read 3, iclass 15, count 2 2006.173.04:24:04.38#ibcon#about to read 4, iclass 15, count 2 2006.173.04:24:04.38#ibcon#read 4, iclass 15, count 2 2006.173.04:24:04.38#ibcon#about to read 5, iclass 15, count 2 2006.173.04:24:04.38#ibcon#read 5, iclass 15, count 2 2006.173.04:24:04.38#ibcon#about to read 6, iclass 15, count 2 2006.173.04:24:04.38#ibcon#read 6, iclass 15, count 2 2006.173.04:24:04.38#ibcon#end of sib2, iclass 15, count 2 2006.173.04:24:04.38#ibcon#*after write, iclass 15, count 2 2006.173.04:24:04.38#ibcon#*before return 0, iclass 15, count 2 2006.173.04:24:04.38#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.04:24:04.38#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.04:24:04.38#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.04:24:04.38#ibcon#ireg 7 cls_cnt 0 2006.173.04:24:04.38#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.04:24:04.50#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.04:24:04.50#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.04:24:04.50#ibcon#enter wrdev, iclass 15, count 0 2006.173.04:24:04.50#ibcon#first serial, iclass 15, count 0 2006.173.04:24:04.50#ibcon#enter sib2, iclass 15, count 0 2006.173.04:24:04.50#ibcon#flushed, iclass 15, count 0 2006.173.04:24:04.50#ibcon#about to write, iclass 15, count 0 2006.173.04:24:04.50#ibcon#wrote, iclass 15, count 0 2006.173.04:24:04.50#ibcon#about to read 3, iclass 15, count 0 2006.173.04:24:04.52#ibcon#read 3, iclass 15, count 0 2006.173.04:24:04.52#ibcon#about to read 4, iclass 15, count 0 2006.173.04:24:04.52#ibcon#read 4, iclass 15, count 0 2006.173.04:24:04.52#ibcon#about to read 5, iclass 15, count 0 2006.173.04:24:04.52#ibcon#read 5, iclass 15, count 0 2006.173.04:24:04.52#ibcon#about to read 6, iclass 15, count 0 2006.173.04:24:04.52#ibcon#read 6, iclass 15, count 0 2006.173.04:24:04.52#ibcon#end of sib2, iclass 15, count 0 2006.173.04:24:04.52#ibcon#*mode == 0, iclass 15, count 0 2006.173.04:24:04.52#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.04:24:04.52#ibcon#[27=USB\r\n] 2006.173.04:24:04.52#ibcon#*before write, iclass 15, count 0 2006.173.04:24:04.52#ibcon#enter sib2, iclass 15, count 0 2006.173.04:24:04.52#ibcon#flushed, iclass 15, count 0 2006.173.04:24:04.52#ibcon#about to write, iclass 15, count 0 2006.173.04:24:04.52#ibcon#wrote, iclass 15, count 0 2006.173.04:24:04.52#ibcon#about to read 3, iclass 15, count 0 2006.173.04:24:04.55#ibcon#read 3, iclass 15, count 0 2006.173.04:24:04.55#ibcon#about to read 4, iclass 15, count 0 2006.173.04:24:04.55#ibcon#read 4, iclass 15, count 0 2006.173.04:24:04.55#ibcon#about to read 5, iclass 15, count 0 2006.173.04:24:04.55#ibcon#read 5, iclass 15, count 0 2006.173.04:24:04.55#ibcon#about to read 6, iclass 15, count 0 2006.173.04:24:04.55#ibcon#read 6, iclass 15, count 0 2006.173.04:24:04.55#ibcon#end of sib2, iclass 15, count 0 2006.173.04:24:04.55#ibcon#*after write, iclass 15, count 0 2006.173.04:24:04.55#ibcon#*before return 0, iclass 15, count 0 2006.173.04:24:04.55#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.04:24:04.55#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.04:24:04.55#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.04:24:04.55#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.04:24:04.55$vck44/vblo=5,709.99 2006.173.04:24:04.55#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.04:24:04.55#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.04:24:04.55#ibcon#ireg 17 cls_cnt 0 2006.173.04:24:04.55#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.04:24:04.55#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.04:24:04.55#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.04:24:04.55#ibcon#enter wrdev, iclass 17, count 0 2006.173.04:24:04.55#ibcon#first serial, iclass 17, count 0 2006.173.04:24:04.55#ibcon#enter sib2, iclass 17, count 0 2006.173.04:24:04.55#ibcon#flushed, iclass 17, count 0 2006.173.04:24:04.55#ibcon#about to write, iclass 17, count 0 2006.173.04:24:04.55#ibcon#wrote, iclass 17, count 0 2006.173.04:24:04.55#ibcon#about to read 3, iclass 17, count 0 2006.173.04:24:04.57#ibcon#read 3, iclass 17, count 0 2006.173.04:24:04.57#ibcon#about to read 4, iclass 17, count 0 2006.173.04:24:04.57#ibcon#read 4, iclass 17, count 0 2006.173.04:24:04.57#ibcon#about to read 5, iclass 17, count 0 2006.173.04:24:04.57#ibcon#read 5, iclass 17, count 0 2006.173.04:24:04.57#ibcon#about to read 6, iclass 17, count 0 2006.173.04:24:04.57#ibcon#read 6, iclass 17, count 0 2006.173.04:24:04.57#ibcon#end of sib2, iclass 17, count 0 2006.173.04:24:04.57#ibcon#*mode == 0, iclass 17, count 0 2006.173.04:24:04.57#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.04:24:04.57#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.04:24:04.57#ibcon#*before write, iclass 17, count 0 2006.173.04:24:04.57#ibcon#enter sib2, iclass 17, count 0 2006.173.04:24:04.57#ibcon#flushed, iclass 17, count 0 2006.173.04:24:04.57#ibcon#about to write, iclass 17, count 0 2006.173.04:24:04.57#ibcon#wrote, iclass 17, count 0 2006.173.04:24:04.57#ibcon#about to read 3, iclass 17, count 0 2006.173.04:24:04.61#ibcon#read 3, iclass 17, count 0 2006.173.04:24:04.61#ibcon#about to read 4, iclass 17, count 0 2006.173.04:24:04.61#ibcon#read 4, iclass 17, count 0 2006.173.04:24:04.61#ibcon#about to read 5, iclass 17, count 0 2006.173.04:24:04.61#ibcon#read 5, iclass 17, count 0 2006.173.04:24:04.61#ibcon#about to read 6, iclass 17, count 0 2006.173.04:24:04.61#ibcon#read 6, iclass 17, count 0 2006.173.04:24:04.61#ibcon#end of sib2, iclass 17, count 0 2006.173.04:24:04.61#ibcon#*after write, iclass 17, count 0 2006.173.04:24:04.61#ibcon#*before return 0, iclass 17, count 0 2006.173.04:24:04.61#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.04:24:04.61#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.04:24:04.61#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.04:24:04.61#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.04:24:04.61$vck44/vb=5,4 2006.173.04:24:04.61#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.04:24:04.61#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.04:24:04.61#ibcon#ireg 11 cls_cnt 2 2006.173.04:24:04.61#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.04:24:04.67#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.04:24:04.67#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.04:24:04.67#ibcon#enter wrdev, iclass 19, count 2 2006.173.04:24:04.67#ibcon#first serial, iclass 19, count 2 2006.173.04:24:04.67#ibcon#enter sib2, iclass 19, count 2 2006.173.04:24:04.67#ibcon#flushed, iclass 19, count 2 2006.173.04:24:04.67#ibcon#about to write, iclass 19, count 2 2006.173.04:24:04.67#ibcon#wrote, iclass 19, count 2 2006.173.04:24:04.67#ibcon#about to read 3, iclass 19, count 2 2006.173.04:24:04.69#ibcon#read 3, iclass 19, count 2 2006.173.04:24:04.69#ibcon#about to read 4, iclass 19, count 2 2006.173.04:24:04.69#ibcon#read 4, iclass 19, count 2 2006.173.04:24:04.69#ibcon#about to read 5, iclass 19, count 2 2006.173.04:24:04.69#ibcon#read 5, iclass 19, count 2 2006.173.04:24:04.69#ibcon#about to read 6, iclass 19, count 2 2006.173.04:24:04.69#ibcon#read 6, iclass 19, count 2 2006.173.04:24:04.69#ibcon#end of sib2, iclass 19, count 2 2006.173.04:24:04.69#ibcon#*mode == 0, iclass 19, count 2 2006.173.04:24:04.69#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.04:24:04.69#ibcon#[27=AT05-04\r\n] 2006.173.04:24:04.69#ibcon#*before write, iclass 19, count 2 2006.173.04:24:04.69#ibcon#enter sib2, iclass 19, count 2 2006.173.04:24:04.69#ibcon#flushed, iclass 19, count 2 2006.173.04:24:04.69#ibcon#about to write, iclass 19, count 2 2006.173.04:24:04.69#ibcon#wrote, iclass 19, count 2 2006.173.04:24:04.69#ibcon#about to read 3, iclass 19, count 2 2006.173.04:24:04.72#ibcon#read 3, iclass 19, count 2 2006.173.04:24:04.72#ibcon#about to read 4, iclass 19, count 2 2006.173.04:24:04.72#ibcon#read 4, iclass 19, count 2 2006.173.04:24:04.72#ibcon#about to read 5, iclass 19, count 2 2006.173.04:24:04.72#ibcon#read 5, iclass 19, count 2 2006.173.04:24:04.72#ibcon#about to read 6, iclass 19, count 2 2006.173.04:24:04.72#ibcon#read 6, iclass 19, count 2 2006.173.04:24:04.72#ibcon#end of sib2, iclass 19, count 2 2006.173.04:24:04.72#ibcon#*after write, iclass 19, count 2 2006.173.04:24:04.72#ibcon#*before return 0, iclass 19, count 2 2006.173.04:24:04.72#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.04:24:04.72#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.04:24:04.72#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.04:24:04.72#ibcon#ireg 7 cls_cnt 0 2006.173.04:24:04.72#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.04:24:04.84#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.04:24:04.84#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.04:24:04.84#ibcon#enter wrdev, iclass 19, count 0 2006.173.04:24:04.84#ibcon#first serial, iclass 19, count 0 2006.173.04:24:04.84#ibcon#enter sib2, iclass 19, count 0 2006.173.04:24:04.84#ibcon#flushed, iclass 19, count 0 2006.173.04:24:04.84#ibcon#about to write, iclass 19, count 0 2006.173.04:24:04.84#ibcon#wrote, iclass 19, count 0 2006.173.04:24:04.84#ibcon#about to read 3, iclass 19, count 0 2006.173.04:24:04.86#ibcon#read 3, iclass 19, count 0 2006.173.04:24:04.86#ibcon#about to read 4, iclass 19, count 0 2006.173.04:24:04.86#ibcon#read 4, iclass 19, count 0 2006.173.04:24:04.86#ibcon#about to read 5, iclass 19, count 0 2006.173.04:24:04.86#ibcon#read 5, iclass 19, count 0 2006.173.04:24:04.86#ibcon#about to read 6, iclass 19, count 0 2006.173.04:24:04.86#ibcon#read 6, iclass 19, count 0 2006.173.04:24:04.86#ibcon#end of sib2, iclass 19, count 0 2006.173.04:24:04.86#ibcon#*mode == 0, iclass 19, count 0 2006.173.04:24:04.86#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.04:24:04.86#ibcon#[27=USB\r\n] 2006.173.04:24:04.86#ibcon#*before write, iclass 19, count 0 2006.173.04:24:04.86#ibcon#enter sib2, iclass 19, count 0 2006.173.04:24:04.86#ibcon#flushed, iclass 19, count 0 2006.173.04:24:04.86#ibcon#about to write, iclass 19, count 0 2006.173.04:24:04.86#ibcon#wrote, iclass 19, count 0 2006.173.04:24:04.86#ibcon#about to read 3, iclass 19, count 0 2006.173.04:24:04.89#ibcon#read 3, iclass 19, count 0 2006.173.04:24:04.89#ibcon#about to read 4, iclass 19, count 0 2006.173.04:24:04.89#ibcon#read 4, iclass 19, count 0 2006.173.04:24:04.89#ibcon#about to read 5, iclass 19, count 0 2006.173.04:24:04.89#ibcon#read 5, iclass 19, count 0 2006.173.04:24:04.89#ibcon#about to read 6, iclass 19, count 0 2006.173.04:24:04.89#ibcon#read 6, iclass 19, count 0 2006.173.04:24:04.89#ibcon#end of sib2, iclass 19, count 0 2006.173.04:24:04.89#ibcon#*after write, iclass 19, count 0 2006.173.04:24:04.89#ibcon#*before return 0, iclass 19, count 0 2006.173.04:24:04.89#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.04:24:04.89#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.04:24:04.89#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.04:24:04.89#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.04:24:04.89$vck44/vblo=6,719.99 2006.173.04:24:04.89#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.04:24:04.89#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.04:24:04.89#ibcon#ireg 17 cls_cnt 0 2006.173.04:24:04.89#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.04:24:04.89#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.04:24:04.89#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.04:24:04.89#ibcon#enter wrdev, iclass 21, count 0 2006.173.04:24:04.89#ibcon#first serial, iclass 21, count 0 2006.173.04:24:04.89#ibcon#enter sib2, iclass 21, count 0 2006.173.04:24:04.89#ibcon#flushed, iclass 21, count 0 2006.173.04:24:04.89#ibcon#about to write, iclass 21, count 0 2006.173.04:24:04.89#ibcon#wrote, iclass 21, count 0 2006.173.04:24:04.89#ibcon#about to read 3, iclass 21, count 0 2006.173.04:24:04.91#ibcon#read 3, iclass 21, count 0 2006.173.04:24:04.91#ibcon#about to read 4, iclass 21, count 0 2006.173.04:24:04.91#ibcon#read 4, iclass 21, count 0 2006.173.04:24:04.91#ibcon#about to read 5, iclass 21, count 0 2006.173.04:24:04.91#ibcon#read 5, iclass 21, count 0 2006.173.04:24:04.91#ibcon#about to read 6, iclass 21, count 0 2006.173.04:24:04.91#ibcon#read 6, iclass 21, count 0 2006.173.04:24:04.91#ibcon#end of sib2, iclass 21, count 0 2006.173.04:24:04.91#ibcon#*mode == 0, iclass 21, count 0 2006.173.04:24:04.91#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.04:24:04.91#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.04:24:04.91#ibcon#*before write, iclass 21, count 0 2006.173.04:24:04.91#ibcon#enter sib2, iclass 21, count 0 2006.173.04:24:04.91#ibcon#flushed, iclass 21, count 0 2006.173.04:24:04.91#ibcon#about to write, iclass 21, count 0 2006.173.04:24:04.91#ibcon#wrote, iclass 21, count 0 2006.173.04:24:04.91#ibcon#about to read 3, iclass 21, count 0 2006.173.04:24:04.95#ibcon#read 3, iclass 21, count 0 2006.173.04:24:04.95#ibcon#about to read 4, iclass 21, count 0 2006.173.04:24:04.95#ibcon#read 4, iclass 21, count 0 2006.173.04:24:04.95#ibcon#about to read 5, iclass 21, count 0 2006.173.04:24:04.95#ibcon#read 5, iclass 21, count 0 2006.173.04:24:04.95#ibcon#about to read 6, iclass 21, count 0 2006.173.04:24:04.95#ibcon#read 6, iclass 21, count 0 2006.173.04:24:04.95#ibcon#end of sib2, iclass 21, count 0 2006.173.04:24:04.95#ibcon#*after write, iclass 21, count 0 2006.173.04:24:04.95#ibcon#*before return 0, iclass 21, count 0 2006.173.04:24:04.95#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.04:24:04.95#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.04:24:04.95#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.04:24:04.95#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.04:24:04.95$vck44/vb=6,4 2006.173.04:24:04.95#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.04:24:04.95#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.04:24:04.95#ibcon#ireg 11 cls_cnt 2 2006.173.04:24:04.95#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.04:24:05.01#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.04:24:05.01#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.04:24:05.01#ibcon#enter wrdev, iclass 23, count 2 2006.173.04:24:05.01#ibcon#first serial, iclass 23, count 2 2006.173.04:24:05.01#ibcon#enter sib2, iclass 23, count 2 2006.173.04:24:05.01#ibcon#flushed, iclass 23, count 2 2006.173.04:24:05.01#ibcon#about to write, iclass 23, count 2 2006.173.04:24:05.01#ibcon#wrote, iclass 23, count 2 2006.173.04:24:05.01#ibcon#about to read 3, iclass 23, count 2 2006.173.04:24:05.03#ibcon#read 3, iclass 23, count 2 2006.173.04:24:05.03#ibcon#about to read 4, iclass 23, count 2 2006.173.04:24:05.03#ibcon#read 4, iclass 23, count 2 2006.173.04:24:05.03#ibcon#about to read 5, iclass 23, count 2 2006.173.04:24:05.03#ibcon#read 5, iclass 23, count 2 2006.173.04:24:05.03#ibcon#about to read 6, iclass 23, count 2 2006.173.04:24:05.03#ibcon#read 6, iclass 23, count 2 2006.173.04:24:05.03#ibcon#end of sib2, iclass 23, count 2 2006.173.04:24:05.03#ibcon#*mode == 0, iclass 23, count 2 2006.173.04:24:05.03#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.04:24:05.03#ibcon#[27=AT06-04\r\n] 2006.173.04:24:05.03#ibcon#*before write, iclass 23, count 2 2006.173.04:24:05.03#ibcon#enter sib2, iclass 23, count 2 2006.173.04:24:05.03#ibcon#flushed, iclass 23, count 2 2006.173.04:24:05.03#ibcon#about to write, iclass 23, count 2 2006.173.04:24:05.03#ibcon#wrote, iclass 23, count 2 2006.173.04:24:05.03#ibcon#about to read 3, iclass 23, count 2 2006.173.04:24:05.06#ibcon#read 3, iclass 23, count 2 2006.173.04:24:05.06#ibcon#about to read 4, iclass 23, count 2 2006.173.04:24:05.06#ibcon#read 4, iclass 23, count 2 2006.173.04:24:05.06#ibcon#about to read 5, iclass 23, count 2 2006.173.04:24:05.06#ibcon#read 5, iclass 23, count 2 2006.173.04:24:05.06#ibcon#about to read 6, iclass 23, count 2 2006.173.04:24:05.06#ibcon#read 6, iclass 23, count 2 2006.173.04:24:05.06#ibcon#end of sib2, iclass 23, count 2 2006.173.04:24:05.06#ibcon#*after write, iclass 23, count 2 2006.173.04:24:05.06#ibcon#*before return 0, iclass 23, count 2 2006.173.04:24:05.06#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.04:24:05.06#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.04:24:05.06#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.04:24:05.06#ibcon#ireg 7 cls_cnt 0 2006.173.04:24:05.06#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.04:24:05.18#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.04:24:05.18#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.04:24:05.18#ibcon#enter wrdev, iclass 23, count 0 2006.173.04:24:05.18#ibcon#first serial, iclass 23, count 0 2006.173.04:24:05.18#ibcon#enter sib2, iclass 23, count 0 2006.173.04:24:05.18#ibcon#flushed, iclass 23, count 0 2006.173.04:24:05.18#ibcon#about to write, iclass 23, count 0 2006.173.04:24:05.18#ibcon#wrote, iclass 23, count 0 2006.173.04:24:05.18#ibcon#about to read 3, iclass 23, count 0 2006.173.04:24:05.20#ibcon#read 3, iclass 23, count 0 2006.173.04:24:05.20#ibcon#about to read 4, iclass 23, count 0 2006.173.04:24:05.20#ibcon#read 4, iclass 23, count 0 2006.173.04:24:05.20#ibcon#about to read 5, iclass 23, count 0 2006.173.04:24:05.20#ibcon#read 5, iclass 23, count 0 2006.173.04:24:05.20#ibcon#about to read 6, iclass 23, count 0 2006.173.04:24:05.20#ibcon#read 6, iclass 23, count 0 2006.173.04:24:05.20#ibcon#end of sib2, iclass 23, count 0 2006.173.04:24:05.20#ibcon#*mode == 0, iclass 23, count 0 2006.173.04:24:05.20#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.04:24:05.20#ibcon#[27=USB\r\n] 2006.173.04:24:05.20#ibcon#*before write, iclass 23, count 0 2006.173.04:24:05.20#ibcon#enter sib2, iclass 23, count 0 2006.173.04:24:05.20#ibcon#flushed, iclass 23, count 0 2006.173.04:24:05.20#ibcon#about to write, iclass 23, count 0 2006.173.04:24:05.20#ibcon#wrote, iclass 23, count 0 2006.173.04:24:05.20#ibcon#about to read 3, iclass 23, count 0 2006.173.04:24:05.23#ibcon#read 3, iclass 23, count 0 2006.173.04:24:05.23#ibcon#about to read 4, iclass 23, count 0 2006.173.04:24:05.23#ibcon#read 4, iclass 23, count 0 2006.173.04:24:05.23#ibcon#about to read 5, iclass 23, count 0 2006.173.04:24:05.23#ibcon#read 5, iclass 23, count 0 2006.173.04:24:05.23#ibcon#about to read 6, iclass 23, count 0 2006.173.04:24:05.23#ibcon#read 6, iclass 23, count 0 2006.173.04:24:05.23#ibcon#end of sib2, iclass 23, count 0 2006.173.04:24:05.23#ibcon#*after write, iclass 23, count 0 2006.173.04:24:05.23#ibcon#*before return 0, iclass 23, count 0 2006.173.04:24:05.23#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.04:24:05.23#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.04:24:05.23#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.04:24:05.23#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.04:24:05.23$vck44/vblo=7,734.99 2006.173.04:24:05.23#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.04:24:05.23#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.04:24:05.23#ibcon#ireg 17 cls_cnt 0 2006.173.04:24:05.23#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.04:24:05.23#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.04:24:05.23#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.04:24:05.23#ibcon#enter wrdev, iclass 25, count 0 2006.173.04:24:05.23#ibcon#first serial, iclass 25, count 0 2006.173.04:24:05.23#ibcon#enter sib2, iclass 25, count 0 2006.173.04:24:05.23#ibcon#flushed, iclass 25, count 0 2006.173.04:24:05.23#ibcon#about to write, iclass 25, count 0 2006.173.04:24:05.23#ibcon#wrote, iclass 25, count 0 2006.173.04:24:05.23#ibcon#about to read 3, iclass 25, count 0 2006.173.04:24:05.25#ibcon#read 3, iclass 25, count 0 2006.173.04:24:05.25#ibcon#about to read 4, iclass 25, count 0 2006.173.04:24:05.25#ibcon#read 4, iclass 25, count 0 2006.173.04:24:05.25#ibcon#about to read 5, iclass 25, count 0 2006.173.04:24:05.25#ibcon#read 5, iclass 25, count 0 2006.173.04:24:05.25#ibcon#about to read 6, iclass 25, count 0 2006.173.04:24:05.25#ibcon#read 6, iclass 25, count 0 2006.173.04:24:05.25#ibcon#end of sib2, iclass 25, count 0 2006.173.04:24:05.25#ibcon#*mode == 0, iclass 25, count 0 2006.173.04:24:05.25#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.04:24:05.25#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.04:24:05.25#ibcon#*before write, iclass 25, count 0 2006.173.04:24:05.25#ibcon#enter sib2, iclass 25, count 0 2006.173.04:24:05.25#ibcon#flushed, iclass 25, count 0 2006.173.04:24:05.25#ibcon#about to write, iclass 25, count 0 2006.173.04:24:05.25#ibcon#wrote, iclass 25, count 0 2006.173.04:24:05.25#ibcon#about to read 3, iclass 25, count 0 2006.173.04:24:05.29#ibcon#read 3, iclass 25, count 0 2006.173.04:24:05.29#ibcon#about to read 4, iclass 25, count 0 2006.173.04:24:05.29#ibcon#read 4, iclass 25, count 0 2006.173.04:24:05.29#ibcon#about to read 5, iclass 25, count 0 2006.173.04:24:05.29#ibcon#read 5, iclass 25, count 0 2006.173.04:24:05.29#ibcon#about to read 6, iclass 25, count 0 2006.173.04:24:05.29#ibcon#read 6, iclass 25, count 0 2006.173.04:24:05.29#ibcon#end of sib2, iclass 25, count 0 2006.173.04:24:05.29#ibcon#*after write, iclass 25, count 0 2006.173.04:24:05.29#ibcon#*before return 0, iclass 25, count 0 2006.173.04:24:05.29#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.04:24:05.29#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.04:24:05.29#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.04:24:05.29#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.04:24:05.29$vck44/vb=7,4 2006.173.04:24:05.29#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.04:24:05.29#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.04:24:05.29#ibcon#ireg 11 cls_cnt 2 2006.173.04:24:05.29#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.04:24:05.35#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.04:24:05.35#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.04:24:05.35#ibcon#enter wrdev, iclass 27, count 2 2006.173.04:24:05.35#ibcon#first serial, iclass 27, count 2 2006.173.04:24:05.35#ibcon#enter sib2, iclass 27, count 2 2006.173.04:24:05.35#ibcon#flushed, iclass 27, count 2 2006.173.04:24:05.35#ibcon#about to write, iclass 27, count 2 2006.173.04:24:05.35#ibcon#wrote, iclass 27, count 2 2006.173.04:24:05.35#ibcon#about to read 3, iclass 27, count 2 2006.173.04:24:05.37#ibcon#read 3, iclass 27, count 2 2006.173.04:24:05.37#ibcon#about to read 4, iclass 27, count 2 2006.173.04:24:05.37#ibcon#read 4, iclass 27, count 2 2006.173.04:24:05.37#ibcon#about to read 5, iclass 27, count 2 2006.173.04:24:05.37#ibcon#read 5, iclass 27, count 2 2006.173.04:24:05.37#ibcon#about to read 6, iclass 27, count 2 2006.173.04:24:05.37#ibcon#read 6, iclass 27, count 2 2006.173.04:24:05.37#ibcon#end of sib2, iclass 27, count 2 2006.173.04:24:05.37#ibcon#*mode == 0, iclass 27, count 2 2006.173.04:24:05.37#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.04:24:05.37#ibcon#[27=AT07-04\r\n] 2006.173.04:24:05.37#ibcon#*before write, iclass 27, count 2 2006.173.04:24:05.37#ibcon#enter sib2, iclass 27, count 2 2006.173.04:24:05.37#ibcon#flushed, iclass 27, count 2 2006.173.04:24:05.37#ibcon#about to write, iclass 27, count 2 2006.173.04:24:05.37#ibcon#wrote, iclass 27, count 2 2006.173.04:24:05.37#ibcon#about to read 3, iclass 27, count 2 2006.173.04:24:05.40#ibcon#read 3, iclass 27, count 2 2006.173.04:24:05.40#ibcon#about to read 4, iclass 27, count 2 2006.173.04:24:05.40#ibcon#read 4, iclass 27, count 2 2006.173.04:24:05.40#ibcon#about to read 5, iclass 27, count 2 2006.173.04:24:05.40#ibcon#read 5, iclass 27, count 2 2006.173.04:24:05.40#ibcon#about to read 6, iclass 27, count 2 2006.173.04:24:05.40#ibcon#read 6, iclass 27, count 2 2006.173.04:24:05.40#ibcon#end of sib2, iclass 27, count 2 2006.173.04:24:05.40#ibcon#*after write, iclass 27, count 2 2006.173.04:24:05.40#ibcon#*before return 0, iclass 27, count 2 2006.173.04:24:05.40#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.04:24:05.40#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.04:24:05.40#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.04:24:05.40#ibcon#ireg 7 cls_cnt 0 2006.173.04:24:05.40#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.04:24:05.52#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.04:24:05.52#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.04:24:05.52#ibcon#enter wrdev, iclass 27, count 0 2006.173.04:24:05.52#ibcon#first serial, iclass 27, count 0 2006.173.04:24:05.52#ibcon#enter sib2, iclass 27, count 0 2006.173.04:24:05.52#ibcon#flushed, iclass 27, count 0 2006.173.04:24:05.52#ibcon#about to write, iclass 27, count 0 2006.173.04:24:05.52#ibcon#wrote, iclass 27, count 0 2006.173.04:24:05.52#ibcon#about to read 3, iclass 27, count 0 2006.173.04:24:05.54#ibcon#read 3, iclass 27, count 0 2006.173.04:24:05.54#ibcon#about to read 4, iclass 27, count 0 2006.173.04:24:05.54#ibcon#read 4, iclass 27, count 0 2006.173.04:24:05.54#ibcon#about to read 5, iclass 27, count 0 2006.173.04:24:05.54#ibcon#read 5, iclass 27, count 0 2006.173.04:24:05.54#ibcon#about to read 6, iclass 27, count 0 2006.173.04:24:05.54#ibcon#read 6, iclass 27, count 0 2006.173.04:24:05.54#ibcon#end of sib2, iclass 27, count 0 2006.173.04:24:05.54#ibcon#*mode == 0, iclass 27, count 0 2006.173.04:24:05.54#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.04:24:05.54#ibcon#[27=USB\r\n] 2006.173.04:24:05.54#ibcon#*before write, iclass 27, count 0 2006.173.04:24:05.54#ibcon#enter sib2, iclass 27, count 0 2006.173.04:24:05.54#ibcon#flushed, iclass 27, count 0 2006.173.04:24:05.54#ibcon#about to write, iclass 27, count 0 2006.173.04:24:05.54#ibcon#wrote, iclass 27, count 0 2006.173.04:24:05.54#ibcon#about to read 3, iclass 27, count 0 2006.173.04:24:05.57#ibcon#read 3, iclass 27, count 0 2006.173.04:24:05.57#ibcon#about to read 4, iclass 27, count 0 2006.173.04:24:05.57#ibcon#read 4, iclass 27, count 0 2006.173.04:24:05.57#ibcon#about to read 5, iclass 27, count 0 2006.173.04:24:05.57#ibcon#read 5, iclass 27, count 0 2006.173.04:24:05.57#ibcon#about to read 6, iclass 27, count 0 2006.173.04:24:05.57#ibcon#read 6, iclass 27, count 0 2006.173.04:24:05.57#ibcon#end of sib2, iclass 27, count 0 2006.173.04:24:05.57#ibcon#*after write, iclass 27, count 0 2006.173.04:24:05.57#ibcon#*before return 0, iclass 27, count 0 2006.173.04:24:05.57#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.04:24:05.57#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.04:24:05.57#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.04:24:05.57#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.04:24:05.57$vck44/vblo=8,744.99 2006.173.04:24:05.57#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.04:24:05.57#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.04:24:05.57#ibcon#ireg 17 cls_cnt 0 2006.173.04:24:05.57#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.04:24:05.57#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.04:24:05.57#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.04:24:05.57#ibcon#enter wrdev, iclass 29, count 0 2006.173.04:24:05.57#ibcon#first serial, iclass 29, count 0 2006.173.04:24:05.57#ibcon#enter sib2, iclass 29, count 0 2006.173.04:24:05.57#ibcon#flushed, iclass 29, count 0 2006.173.04:24:05.57#ibcon#about to write, iclass 29, count 0 2006.173.04:24:05.57#ibcon#wrote, iclass 29, count 0 2006.173.04:24:05.57#ibcon#about to read 3, iclass 29, count 0 2006.173.04:24:05.59#ibcon#read 3, iclass 29, count 0 2006.173.04:24:05.59#ibcon#about to read 4, iclass 29, count 0 2006.173.04:24:05.59#ibcon#read 4, iclass 29, count 0 2006.173.04:24:05.59#ibcon#about to read 5, iclass 29, count 0 2006.173.04:24:05.59#ibcon#read 5, iclass 29, count 0 2006.173.04:24:05.59#ibcon#about to read 6, iclass 29, count 0 2006.173.04:24:05.59#ibcon#read 6, iclass 29, count 0 2006.173.04:24:05.59#ibcon#end of sib2, iclass 29, count 0 2006.173.04:24:05.59#ibcon#*mode == 0, iclass 29, count 0 2006.173.04:24:05.59#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.04:24:05.59#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.04:24:05.59#ibcon#*before write, iclass 29, count 0 2006.173.04:24:05.59#ibcon#enter sib2, iclass 29, count 0 2006.173.04:24:05.59#ibcon#flushed, iclass 29, count 0 2006.173.04:24:05.59#ibcon#about to write, iclass 29, count 0 2006.173.04:24:05.59#ibcon#wrote, iclass 29, count 0 2006.173.04:24:05.59#ibcon#about to read 3, iclass 29, count 0 2006.173.04:24:05.63#ibcon#read 3, iclass 29, count 0 2006.173.04:24:05.63#ibcon#about to read 4, iclass 29, count 0 2006.173.04:24:05.63#ibcon#read 4, iclass 29, count 0 2006.173.04:24:05.63#ibcon#about to read 5, iclass 29, count 0 2006.173.04:24:05.63#ibcon#read 5, iclass 29, count 0 2006.173.04:24:05.63#ibcon#about to read 6, iclass 29, count 0 2006.173.04:24:05.63#ibcon#read 6, iclass 29, count 0 2006.173.04:24:05.63#ibcon#end of sib2, iclass 29, count 0 2006.173.04:24:05.63#ibcon#*after write, iclass 29, count 0 2006.173.04:24:05.63#ibcon#*before return 0, iclass 29, count 0 2006.173.04:24:05.63#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.04:24:05.63#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.04:24:05.63#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.04:24:05.63#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.04:24:05.63$vck44/vb=8,4 2006.173.04:24:05.63#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.04:24:05.63#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.04:24:05.63#ibcon#ireg 11 cls_cnt 2 2006.173.04:24:05.63#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.04:24:05.69#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.04:24:05.69#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.04:24:05.69#ibcon#enter wrdev, iclass 31, count 2 2006.173.04:24:05.69#ibcon#first serial, iclass 31, count 2 2006.173.04:24:05.69#ibcon#enter sib2, iclass 31, count 2 2006.173.04:24:05.69#ibcon#flushed, iclass 31, count 2 2006.173.04:24:05.69#ibcon#about to write, iclass 31, count 2 2006.173.04:24:05.69#ibcon#wrote, iclass 31, count 2 2006.173.04:24:05.69#ibcon#about to read 3, iclass 31, count 2 2006.173.04:24:05.71#ibcon#read 3, iclass 31, count 2 2006.173.04:24:05.71#ibcon#about to read 4, iclass 31, count 2 2006.173.04:24:05.71#ibcon#read 4, iclass 31, count 2 2006.173.04:24:05.71#ibcon#about to read 5, iclass 31, count 2 2006.173.04:24:05.71#ibcon#read 5, iclass 31, count 2 2006.173.04:24:05.71#ibcon#about to read 6, iclass 31, count 2 2006.173.04:24:05.71#ibcon#read 6, iclass 31, count 2 2006.173.04:24:05.71#ibcon#end of sib2, iclass 31, count 2 2006.173.04:24:05.71#ibcon#*mode == 0, iclass 31, count 2 2006.173.04:24:05.71#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.04:24:05.71#ibcon#[27=AT08-04\r\n] 2006.173.04:24:05.71#ibcon#*before write, iclass 31, count 2 2006.173.04:24:05.71#ibcon#enter sib2, iclass 31, count 2 2006.173.04:24:05.71#ibcon#flushed, iclass 31, count 2 2006.173.04:24:05.71#ibcon#about to write, iclass 31, count 2 2006.173.04:24:05.71#ibcon#wrote, iclass 31, count 2 2006.173.04:24:05.71#ibcon#about to read 3, iclass 31, count 2 2006.173.04:24:05.74#ibcon#read 3, iclass 31, count 2 2006.173.04:24:05.74#ibcon#about to read 4, iclass 31, count 2 2006.173.04:24:05.74#ibcon#read 4, iclass 31, count 2 2006.173.04:24:05.74#ibcon#about to read 5, iclass 31, count 2 2006.173.04:24:05.74#ibcon#read 5, iclass 31, count 2 2006.173.04:24:05.74#ibcon#about to read 6, iclass 31, count 2 2006.173.04:24:05.74#ibcon#read 6, iclass 31, count 2 2006.173.04:24:05.74#ibcon#end of sib2, iclass 31, count 2 2006.173.04:24:05.74#ibcon#*after write, iclass 31, count 2 2006.173.04:24:05.74#ibcon#*before return 0, iclass 31, count 2 2006.173.04:24:05.74#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.04:24:05.74#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.04:24:05.74#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.04:24:05.74#ibcon#ireg 7 cls_cnt 0 2006.173.04:24:05.74#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.04:24:05.86#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.04:24:05.86#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.04:24:05.86#ibcon#enter wrdev, iclass 31, count 0 2006.173.04:24:05.86#ibcon#first serial, iclass 31, count 0 2006.173.04:24:05.86#ibcon#enter sib2, iclass 31, count 0 2006.173.04:24:05.86#ibcon#flushed, iclass 31, count 0 2006.173.04:24:05.86#ibcon#about to write, iclass 31, count 0 2006.173.04:24:05.86#ibcon#wrote, iclass 31, count 0 2006.173.04:24:05.86#ibcon#about to read 3, iclass 31, count 0 2006.173.04:24:05.88#ibcon#read 3, iclass 31, count 0 2006.173.04:24:05.88#ibcon#about to read 4, iclass 31, count 0 2006.173.04:24:05.88#ibcon#read 4, iclass 31, count 0 2006.173.04:24:05.88#ibcon#about to read 5, iclass 31, count 0 2006.173.04:24:05.88#ibcon#read 5, iclass 31, count 0 2006.173.04:24:05.88#ibcon#about to read 6, iclass 31, count 0 2006.173.04:24:05.88#ibcon#read 6, iclass 31, count 0 2006.173.04:24:05.88#ibcon#end of sib2, iclass 31, count 0 2006.173.04:24:05.88#ibcon#*mode == 0, iclass 31, count 0 2006.173.04:24:05.88#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.04:24:05.88#ibcon#[27=USB\r\n] 2006.173.04:24:05.88#ibcon#*before write, iclass 31, count 0 2006.173.04:24:05.88#ibcon#enter sib2, iclass 31, count 0 2006.173.04:24:05.88#ibcon#flushed, iclass 31, count 0 2006.173.04:24:05.88#ibcon#about to write, iclass 31, count 0 2006.173.04:24:05.88#ibcon#wrote, iclass 31, count 0 2006.173.04:24:05.88#ibcon#about to read 3, iclass 31, count 0 2006.173.04:24:05.91#ibcon#read 3, iclass 31, count 0 2006.173.04:24:05.91#ibcon#about to read 4, iclass 31, count 0 2006.173.04:24:05.91#ibcon#read 4, iclass 31, count 0 2006.173.04:24:05.91#ibcon#about to read 5, iclass 31, count 0 2006.173.04:24:05.91#ibcon#read 5, iclass 31, count 0 2006.173.04:24:05.91#ibcon#about to read 6, iclass 31, count 0 2006.173.04:24:05.91#ibcon#read 6, iclass 31, count 0 2006.173.04:24:05.91#ibcon#end of sib2, iclass 31, count 0 2006.173.04:24:05.91#ibcon#*after write, iclass 31, count 0 2006.173.04:24:05.91#ibcon#*before return 0, iclass 31, count 0 2006.173.04:24:05.91#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.04:24:05.91#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.04:24:05.91#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.04:24:05.91#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.04:24:05.91$vck44/vabw=wide 2006.173.04:24:05.91#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.04:24:05.91#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.04:24:05.91#ibcon#ireg 8 cls_cnt 0 2006.173.04:24:05.91#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.04:24:05.91#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.04:24:05.91#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.04:24:05.91#ibcon#enter wrdev, iclass 33, count 0 2006.173.04:24:05.91#ibcon#first serial, iclass 33, count 0 2006.173.04:24:05.91#ibcon#enter sib2, iclass 33, count 0 2006.173.04:24:05.91#ibcon#flushed, iclass 33, count 0 2006.173.04:24:05.91#ibcon#about to write, iclass 33, count 0 2006.173.04:24:05.91#ibcon#wrote, iclass 33, count 0 2006.173.04:24:05.91#ibcon#about to read 3, iclass 33, count 0 2006.173.04:24:05.93#ibcon#read 3, iclass 33, count 0 2006.173.04:24:05.93#ibcon#about to read 4, iclass 33, count 0 2006.173.04:24:05.93#ibcon#read 4, iclass 33, count 0 2006.173.04:24:05.93#ibcon#about to read 5, iclass 33, count 0 2006.173.04:24:05.93#ibcon#read 5, iclass 33, count 0 2006.173.04:24:05.93#ibcon#about to read 6, iclass 33, count 0 2006.173.04:24:05.93#ibcon#read 6, iclass 33, count 0 2006.173.04:24:05.93#ibcon#end of sib2, iclass 33, count 0 2006.173.04:24:05.93#ibcon#*mode == 0, iclass 33, count 0 2006.173.04:24:05.93#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.04:24:05.93#ibcon#[25=BW32\r\n] 2006.173.04:24:05.93#ibcon#*before write, iclass 33, count 0 2006.173.04:24:05.93#ibcon#enter sib2, iclass 33, count 0 2006.173.04:24:05.93#ibcon#flushed, iclass 33, count 0 2006.173.04:24:05.93#ibcon#about to write, iclass 33, count 0 2006.173.04:24:05.93#ibcon#wrote, iclass 33, count 0 2006.173.04:24:05.93#ibcon#about to read 3, iclass 33, count 0 2006.173.04:24:05.96#ibcon#read 3, iclass 33, count 0 2006.173.04:24:05.96#ibcon#about to read 4, iclass 33, count 0 2006.173.04:24:05.96#ibcon#read 4, iclass 33, count 0 2006.173.04:24:05.96#ibcon#about to read 5, iclass 33, count 0 2006.173.04:24:05.96#ibcon#read 5, iclass 33, count 0 2006.173.04:24:05.96#ibcon#about to read 6, iclass 33, count 0 2006.173.04:24:05.96#ibcon#read 6, iclass 33, count 0 2006.173.04:24:05.96#ibcon#end of sib2, iclass 33, count 0 2006.173.04:24:05.96#ibcon#*after write, iclass 33, count 0 2006.173.04:24:05.96#ibcon#*before return 0, iclass 33, count 0 2006.173.04:24:05.96#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.04:24:05.96#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.04:24:05.96#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.04:24:05.96#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.04:24:05.96$vck44/vbbw=wide 2006.173.04:24:05.96#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.04:24:05.96#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.04:24:05.96#ibcon#ireg 8 cls_cnt 0 2006.173.04:24:05.96#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.04:24:06.03#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.04:24:06.03#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.04:24:06.03#ibcon#enter wrdev, iclass 35, count 0 2006.173.04:24:06.03#ibcon#first serial, iclass 35, count 0 2006.173.04:24:06.03#ibcon#enter sib2, iclass 35, count 0 2006.173.04:24:06.03#ibcon#flushed, iclass 35, count 0 2006.173.04:24:06.03#ibcon#about to write, iclass 35, count 0 2006.173.04:24:06.03#ibcon#wrote, iclass 35, count 0 2006.173.04:24:06.03#ibcon#about to read 3, iclass 35, count 0 2006.173.04:24:06.05#ibcon#read 3, iclass 35, count 0 2006.173.04:24:06.05#ibcon#about to read 4, iclass 35, count 0 2006.173.04:24:06.05#ibcon#read 4, iclass 35, count 0 2006.173.04:24:06.05#ibcon#about to read 5, iclass 35, count 0 2006.173.04:24:06.05#ibcon#read 5, iclass 35, count 0 2006.173.04:24:06.05#ibcon#about to read 6, iclass 35, count 0 2006.173.04:24:06.05#ibcon#read 6, iclass 35, count 0 2006.173.04:24:06.05#ibcon#end of sib2, iclass 35, count 0 2006.173.04:24:06.05#ibcon#*mode == 0, iclass 35, count 0 2006.173.04:24:06.05#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.04:24:06.05#ibcon#[27=BW32\r\n] 2006.173.04:24:06.05#ibcon#*before write, iclass 35, count 0 2006.173.04:24:06.05#ibcon#enter sib2, iclass 35, count 0 2006.173.04:24:06.05#ibcon#flushed, iclass 35, count 0 2006.173.04:24:06.05#ibcon#about to write, iclass 35, count 0 2006.173.04:24:06.05#ibcon#wrote, iclass 35, count 0 2006.173.04:24:06.05#ibcon#about to read 3, iclass 35, count 0 2006.173.04:24:06.08#ibcon#read 3, iclass 35, count 0 2006.173.04:24:06.08#ibcon#about to read 4, iclass 35, count 0 2006.173.04:24:06.08#ibcon#read 4, iclass 35, count 0 2006.173.04:24:06.08#ibcon#about to read 5, iclass 35, count 0 2006.173.04:24:06.08#ibcon#read 5, iclass 35, count 0 2006.173.04:24:06.08#ibcon#about to read 6, iclass 35, count 0 2006.173.04:24:06.08#ibcon#read 6, iclass 35, count 0 2006.173.04:24:06.08#ibcon#end of sib2, iclass 35, count 0 2006.173.04:24:06.08#ibcon#*after write, iclass 35, count 0 2006.173.04:24:06.08#ibcon#*before return 0, iclass 35, count 0 2006.173.04:24:06.08#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.04:24:06.08#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.04:24:06.08#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.04:24:06.08#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.04:24:06.08$setupk4/ifdk4 2006.173.04:24:06.08$ifdk4/lo= 2006.173.04:24:06.08$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.04:24:06.08$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.04:24:06.08$ifdk4/patch= 2006.173.04:24:06.08$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.04:24:06.08$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.04:24:06.08$setupk4/!*+20s 2006.173.04:24:06.83#abcon#<5=/15 1.1 2.1 23.23 791005.9\r\n> 2006.173.04:24:06.85#abcon#{5=INTERFACE CLEAR} 2006.173.04:24:06.91#abcon#[5=S1D000X0/0*\r\n] 2006.173.04:24:17.00#abcon#<5=/15 1.1 2.1 23.24 791005.9\r\n> 2006.173.04:24:17.02#abcon#{5=INTERFACE CLEAR} 2006.173.04:24:17.08#abcon#[5=S1D000X0/0*\r\n] 2006.173.04:24:20.59$setupk4/"tpicd 2006.173.04:24:20.59$setupk4/echo=off 2006.173.04:24:20.59$setupk4/xlog=off 2006.173.04:24:20.59:!2006.173.04:30:15 2006.173.04:24:34.14#trakl#Source acquired 2006.173.04:24:36.14#flagr#flagr/antenna,acquired 2006.173.04:30:15.00:preob 2006.173.04:30:16.14/onsource/TRACKING 2006.173.04:30:16.14:!2006.173.04:30:25 2006.173.04:30:25.00:"tape 2006.173.04:30:25.00:"st=record 2006.173.04:30:25.00:data_valid=on 2006.173.04:30:25.00:midob 2006.173.04:30:25.14/onsource/TRACKING 2006.173.04:30:25.14/wx/23.28,1005.9,80 2006.173.04:30:25.29/cable/+6.5084E-03 2006.173.04:30:26.38/va/01,07,usb,yes,35,38 2006.173.04:30:26.38/va/02,06,usb,yes,35,36 2006.173.04:30:26.38/va/03,05,usb,yes,44,46 2006.173.04:30:26.38/va/04,06,usb,yes,36,37 2006.173.04:30:26.38/va/05,04,usb,yes,28,28 2006.173.04:30:26.38/va/06,03,usb,yes,39,39 2006.173.04:30:26.38/va/07,04,usb,yes,32,33 2006.173.04:30:26.38/va/08,04,usb,yes,27,32 2006.173.04:30:26.61/valo/01,524.99,yes,locked 2006.173.04:30:26.61/valo/02,534.99,yes,locked 2006.173.04:30:26.61/valo/03,564.99,yes,locked 2006.173.04:30:26.61/valo/04,624.99,yes,locked 2006.173.04:30:26.61/valo/05,734.99,yes,locked 2006.173.04:30:26.61/valo/06,814.99,yes,locked 2006.173.04:30:26.61/valo/07,864.99,yes,locked 2006.173.04:30:26.61/valo/08,884.99,yes,locked 2006.173.04:30:27.70/vb/01,04,usb,yes,29,27 2006.173.04:30:27.70/vb/02,04,usb,yes,31,31 2006.173.04:30:27.70/vb/03,04,usb,yes,28,31 2006.173.04:30:27.70/vb/04,04,usb,yes,32,31 2006.173.04:30:27.70/vb/05,04,usb,yes,25,28 2006.173.04:30:27.70/vb/06,04,usb,yes,30,26 2006.173.04:30:27.70/vb/07,04,usb,yes,29,29 2006.173.04:30:27.70/vb/08,04,usb,yes,27,30 2006.173.04:30:27.94/vblo/01,629.99,yes,locked 2006.173.04:30:27.94/vblo/02,634.99,yes,locked 2006.173.04:30:27.94/vblo/03,649.99,yes,locked 2006.173.04:30:27.94/vblo/04,679.99,yes,locked 2006.173.04:30:27.94/vblo/05,709.99,yes,locked 2006.173.04:30:27.94/vblo/06,719.99,yes,locked 2006.173.04:30:27.94/vblo/07,734.99,yes,locked 2006.173.04:30:27.94/vblo/08,744.99,yes,locked 2006.173.04:30:28.09/vabw/8 2006.173.04:30:28.24/vbbw/8 2006.173.04:30:28.33/xfe/off,on,14.7 2006.173.04:30:28.73/ifatt/23,28,28,28 2006.173.04:30:29.08/fmout-gps/S +3.94E-07 2006.173.04:30:29.12:!2006.173.04:31:25 2006.173.04:31:25.00:data_valid=off 2006.173.04:31:25.00:"et 2006.173.04:31:25.00:!+3s 2006.173.04:31:28.01:"tape 2006.173.04:31:28.01:postob 2006.173.04:31:28.12/cable/+6.5088E-03 2006.173.04:31:28.12/wx/23.30,1005.9,80 2006.173.04:31:29.08/fmout-gps/S +3.95E-07 2006.173.04:31:29.08:scan_name=173-0433,jd0606,50 2006.173.04:31:29.08:source=0552+398,055530.81,394849.2,2000.0,cw 2006.173.04:31:29.13#flagr#flagr/antenna,new-source 2006.173.04:31:30.13:checkk5 2006.173.04:31:30.48/chk_autoobs//k5ts1/ autoobs is running! 2006.173.04:31:30.83/chk_autoobs//k5ts2/ autoobs is running! 2006.173.04:31:31.19/chk_autoobs//k5ts3/ autoobs is running! 2006.173.04:31:31.53/chk_autoobs//k5ts4/ autoobs is running! 2006.173.04:31:31.86/chk_obsdata//k5ts1/T1730430??a.dat file size is correct (nominal:240MB, actual:236MB). 2006.173.04:31:32.21/chk_obsdata//k5ts2/T1730430??b.dat file size is correct (nominal:240MB, actual:236MB). 2006.173.04:31:32.55/chk_obsdata//k5ts3/T1730430??c.dat file size is correct (nominal:240MB, actual:236MB). 2006.173.04:31:32.90/chk_obsdata//k5ts4/T1730430??d.dat file size is correct (nominal:240MB, actual:236MB). 2006.173.04:31:33.57/k5log//k5ts1_log_newline 2006.173.04:31:34.23/k5log//k5ts2_log_newline 2006.173.04:31:34.88/k5log//k5ts3_log_newline 2006.173.04:31:35.53/k5log//k5ts4_log_newline 2006.173.04:31:35.55/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.04:31:35.55:setupk4=1 2006.173.04:31:35.55$setupk4/echo=on 2006.173.04:31:35.55$setupk4/pcalon 2006.173.04:31:35.56$pcalon/"no phase cal control is implemented here 2006.173.04:31:35.56$setupk4/"tpicd=stop 2006.173.04:31:35.56$setupk4/"rec=synch_on 2006.173.04:31:35.56$setupk4/"rec_mode=128 2006.173.04:31:35.56$setupk4/!* 2006.173.04:31:35.56$setupk4/recpk4 2006.173.04:31:35.56$recpk4/recpatch= 2006.173.04:31:35.56$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.04:31:35.56$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.04:31:35.56$setupk4/vck44 2006.173.04:31:35.56$vck44/valo=1,524.99 2006.173.04:31:35.56#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.04:31:35.56#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.04:31:35.56#ibcon#ireg 17 cls_cnt 0 2006.173.04:31:35.56#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.04:31:35.56#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.04:31:35.56#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.04:31:35.56#ibcon#enter wrdev, iclass 40, count 0 2006.173.04:31:35.56#ibcon#first serial, iclass 40, count 0 2006.173.04:31:35.56#ibcon#enter sib2, iclass 40, count 0 2006.173.04:31:35.56#ibcon#flushed, iclass 40, count 0 2006.173.04:31:35.56#ibcon#about to write, iclass 40, count 0 2006.173.04:31:35.56#ibcon#wrote, iclass 40, count 0 2006.173.04:31:35.56#ibcon#about to read 3, iclass 40, count 0 2006.173.04:31:35.58#ibcon#read 3, iclass 40, count 0 2006.173.04:31:35.58#ibcon#about to read 4, iclass 40, count 0 2006.173.04:31:35.58#ibcon#read 4, iclass 40, count 0 2006.173.04:31:35.58#ibcon#about to read 5, iclass 40, count 0 2006.173.04:31:35.58#ibcon#read 5, iclass 40, count 0 2006.173.04:31:35.58#ibcon#about to read 6, iclass 40, count 0 2006.173.04:31:35.58#ibcon#read 6, iclass 40, count 0 2006.173.04:31:35.58#ibcon#end of sib2, iclass 40, count 0 2006.173.04:31:35.58#ibcon#*mode == 0, iclass 40, count 0 2006.173.04:31:35.58#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.04:31:35.58#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.04:31:35.58#ibcon#*before write, iclass 40, count 0 2006.173.04:31:35.58#ibcon#enter sib2, iclass 40, count 0 2006.173.04:31:35.58#ibcon#flushed, iclass 40, count 0 2006.173.04:31:35.58#ibcon#about to write, iclass 40, count 0 2006.173.04:31:35.58#ibcon#wrote, iclass 40, count 0 2006.173.04:31:35.58#ibcon#about to read 3, iclass 40, count 0 2006.173.04:31:35.63#ibcon#read 3, iclass 40, count 0 2006.173.04:31:35.63#ibcon#about to read 4, iclass 40, count 0 2006.173.04:31:35.63#ibcon#read 4, iclass 40, count 0 2006.173.04:31:35.63#ibcon#about to read 5, iclass 40, count 0 2006.173.04:31:35.63#ibcon#read 5, iclass 40, count 0 2006.173.04:31:35.63#ibcon#about to read 6, iclass 40, count 0 2006.173.04:31:35.63#ibcon#read 6, iclass 40, count 0 2006.173.04:31:35.63#ibcon#end of sib2, iclass 40, count 0 2006.173.04:31:35.63#ibcon#*after write, iclass 40, count 0 2006.173.04:31:35.63#ibcon#*before return 0, iclass 40, count 0 2006.173.04:31:35.63#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.04:31:35.63#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.04:31:35.63#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.04:31:35.63#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.04:31:35.63$vck44/va=1,7 2006.173.04:31:35.63#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.04:31:35.63#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.04:31:35.63#ibcon#ireg 11 cls_cnt 2 2006.173.04:31:35.63#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.04:31:35.63#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.04:31:35.63#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.04:31:35.63#ibcon#enter wrdev, iclass 4, count 2 2006.173.04:31:35.63#ibcon#first serial, iclass 4, count 2 2006.173.04:31:35.63#ibcon#enter sib2, iclass 4, count 2 2006.173.04:31:35.63#ibcon#flushed, iclass 4, count 2 2006.173.04:31:35.63#ibcon#about to write, iclass 4, count 2 2006.173.04:31:35.63#ibcon#wrote, iclass 4, count 2 2006.173.04:31:35.63#ibcon#about to read 3, iclass 4, count 2 2006.173.04:31:35.65#ibcon#read 3, iclass 4, count 2 2006.173.04:31:35.65#ibcon#about to read 4, iclass 4, count 2 2006.173.04:31:35.65#ibcon#read 4, iclass 4, count 2 2006.173.04:31:35.65#ibcon#about to read 5, iclass 4, count 2 2006.173.04:31:35.65#ibcon#read 5, iclass 4, count 2 2006.173.04:31:35.65#ibcon#about to read 6, iclass 4, count 2 2006.173.04:31:35.65#ibcon#read 6, iclass 4, count 2 2006.173.04:31:35.65#ibcon#end of sib2, iclass 4, count 2 2006.173.04:31:35.65#ibcon#*mode == 0, iclass 4, count 2 2006.173.04:31:35.65#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.04:31:35.65#ibcon#[25=AT01-07\r\n] 2006.173.04:31:35.65#ibcon#*before write, iclass 4, count 2 2006.173.04:31:35.65#ibcon#enter sib2, iclass 4, count 2 2006.173.04:31:35.65#ibcon#flushed, iclass 4, count 2 2006.173.04:31:35.65#ibcon#about to write, iclass 4, count 2 2006.173.04:31:35.65#ibcon#wrote, iclass 4, count 2 2006.173.04:31:35.65#ibcon#about to read 3, iclass 4, count 2 2006.173.04:31:35.68#ibcon#read 3, iclass 4, count 2 2006.173.04:31:35.68#ibcon#about to read 4, iclass 4, count 2 2006.173.04:31:35.68#ibcon#read 4, iclass 4, count 2 2006.173.04:31:35.68#ibcon#about to read 5, iclass 4, count 2 2006.173.04:31:35.68#ibcon#read 5, iclass 4, count 2 2006.173.04:31:35.68#ibcon#about to read 6, iclass 4, count 2 2006.173.04:31:35.68#ibcon#read 6, iclass 4, count 2 2006.173.04:31:35.68#ibcon#end of sib2, iclass 4, count 2 2006.173.04:31:35.68#ibcon#*after write, iclass 4, count 2 2006.173.04:31:35.68#ibcon#*before return 0, iclass 4, count 2 2006.173.04:31:35.68#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.04:31:35.68#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.04:31:35.68#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.04:31:35.68#ibcon#ireg 7 cls_cnt 0 2006.173.04:31:35.68#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.04:31:35.80#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.04:31:35.80#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.04:31:35.80#ibcon#enter wrdev, iclass 4, count 0 2006.173.04:31:35.80#ibcon#first serial, iclass 4, count 0 2006.173.04:31:35.80#ibcon#enter sib2, iclass 4, count 0 2006.173.04:31:35.80#ibcon#flushed, iclass 4, count 0 2006.173.04:31:35.80#ibcon#about to write, iclass 4, count 0 2006.173.04:31:35.80#ibcon#wrote, iclass 4, count 0 2006.173.04:31:35.80#ibcon#about to read 3, iclass 4, count 0 2006.173.04:31:35.82#ibcon#read 3, iclass 4, count 0 2006.173.04:31:35.82#ibcon#about to read 4, iclass 4, count 0 2006.173.04:31:35.82#ibcon#read 4, iclass 4, count 0 2006.173.04:31:35.82#ibcon#about to read 5, iclass 4, count 0 2006.173.04:31:35.82#ibcon#read 5, iclass 4, count 0 2006.173.04:31:35.82#ibcon#about to read 6, iclass 4, count 0 2006.173.04:31:35.82#ibcon#read 6, iclass 4, count 0 2006.173.04:31:35.82#ibcon#end of sib2, iclass 4, count 0 2006.173.04:31:35.82#ibcon#*mode == 0, iclass 4, count 0 2006.173.04:31:35.82#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.04:31:35.82#ibcon#[25=USB\r\n] 2006.173.04:31:35.82#ibcon#*before write, iclass 4, count 0 2006.173.04:31:35.82#ibcon#enter sib2, iclass 4, count 0 2006.173.04:31:35.82#ibcon#flushed, iclass 4, count 0 2006.173.04:31:35.82#ibcon#about to write, iclass 4, count 0 2006.173.04:31:35.82#ibcon#wrote, iclass 4, count 0 2006.173.04:31:35.82#ibcon#about to read 3, iclass 4, count 0 2006.173.04:31:35.85#ibcon#read 3, iclass 4, count 0 2006.173.04:31:35.85#ibcon#about to read 4, iclass 4, count 0 2006.173.04:31:35.85#ibcon#read 4, iclass 4, count 0 2006.173.04:31:35.85#ibcon#about to read 5, iclass 4, count 0 2006.173.04:31:35.85#ibcon#read 5, iclass 4, count 0 2006.173.04:31:35.85#ibcon#about to read 6, iclass 4, count 0 2006.173.04:31:35.85#ibcon#read 6, iclass 4, count 0 2006.173.04:31:35.85#ibcon#end of sib2, iclass 4, count 0 2006.173.04:31:35.85#ibcon#*after write, iclass 4, count 0 2006.173.04:31:35.85#ibcon#*before return 0, iclass 4, count 0 2006.173.04:31:35.85#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.04:31:35.85#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.04:31:35.85#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.04:31:35.85#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.04:31:35.85$vck44/valo=2,534.99 2006.173.04:31:35.85#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.04:31:35.85#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.04:31:35.85#ibcon#ireg 17 cls_cnt 0 2006.173.04:31:35.85#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.04:31:35.85#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.04:31:35.85#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.04:31:35.85#ibcon#enter wrdev, iclass 6, count 0 2006.173.04:31:35.85#ibcon#first serial, iclass 6, count 0 2006.173.04:31:35.85#ibcon#enter sib2, iclass 6, count 0 2006.173.04:31:35.85#ibcon#flushed, iclass 6, count 0 2006.173.04:31:35.85#ibcon#about to write, iclass 6, count 0 2006.173.04:31:35.85#ibcon#wrote, iclass 6, count 0 2006.173.04:31:35.85#ibcon#about to read 3, iclass 6, count 0 2006.173.04:31:35.87#ibcon#read 3, iclass 6, count 0 2006.173.04:31:35.87#ibcon#about to read 4, iclass 6, count 0 2006.173.04:31:35.87#ibcon#read 4, iclass 6, count 0 2006.173.04:31:35.87#ibcon#about to read 5, iclass 6, count 0 2006.173.04:31:35.87#ibcon#read 5, iclass 6, count 0 2006.173.04:31:35.87#ibcon#about to read 6, iclass 6, count 0 2006.173.04:31:35.87#ibcon#read 6, iclass 6, count 0 2006.173.04:31:35.87#ibcon#end of sib2, iclass 6, count 0 2006.173.04:31:35.87#ibcon#*mode == 0, iclass 6, count 0 2006.173.04:31:35.87#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.04:31:35.87#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.04:31:35.87#ibcon#*before write, iclass 6, count 0 2006.173.04:31:35.87#ibcon#enter sib2, iclass 6, count 0 2006.173.04:31:35.87#ibcon#flushed, iclass 6, count 0 2006.173.04:31:35.87#ibcon#about to write, iclass 6, count 0 2006.173.04:31:35.87#ibcon#wrote, iclass 6, count 0 2006.173.04:31:35.87#ibcon#about to read 3, iclass 6, count 0 2006.173.04:31:35.91#ibcon#read 3, iclass 6, count 0 2006.173.04:31:35.91#ibcon#about to read 4, iclass 6, count 0 2006.173.04:31:35.91#ibcon#read 4, iclass 6, count 0 2006.173.04:31:35.91#ibcon#about to read 5, iclass 6, count 0 2006.173.04:31:35.91#ibcon#read 5, iclass 6, count 0 2006.173.04:31:35.91#ibcon#about to read 6, iclass 6, count 0 2006.173.04:31:35.91#ibcon#read 6, iclass 6, count 0 2006.173.04:31:35.91#ibcon#end of sib2, iclass 6, count 0 2006.173.04:31:35.91#ibcon#*after write, iclass 6, count 0 2006.173.04:31:35.91#ibcon#*before return 0, iclass 6, count 0 2006.173.04:31:35.91#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.04:31:35.91#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.04:31:35.91#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.04:31:35.91#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.04:31:35.91$vck44/va=2,6 2006.173.04:31:35.91#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.04:31:35.91#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.04:31:35.91#ibcon#ireg 11 cls_cnt 2 2006.173.04:31:35.91#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.04:31:35.97#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.04:31:35.97#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.04:31:35.97#ibcon#enter wrdev, iclass 10, count 2 2006.173.04:31:35.97#ibcon#first serial, iclass 10, count 2 2006.173.04:31:35.97#ibcon#enter sib2, iclass 10, count 2 2006.173.04:31:35.97#ibcon#flushed, iclass 10, count 2 2006.173.04:31:35.97#ibcon#about to write, iclass 10, count 2 2006.173.04:31:35.97#ibcon#wrote, iclass 10, count 2 2006.173.04:31:35.97#ibcon#about to read 3, iclass 10, count 2 2006.173.04:31:35.99#ibcon#read 3, iclass 10, count 2 2006.173.04:31:35.99#ibcon#about to read 4, iclass 10, count 2 2006.173.04:31:35.99#ibcon#read 4, iclass 10, count 2 2006.173.04:31:35.99#ibcon#about to read 5, iclass 10, count 2 2006.173.04:31:35.99#ibcon#read 5, iclass 10, count 2 2006.173.04:31:35.99#ibcon#about to read 6, iclass 10, count 2 2006.173.04:31:35.99#ibcon#read 6, iclass 10, count 2 2006.173.04:31:35.99#ibcon#end of sib2, iclass 10, count 2 2006.173.04:31:35.99#ibcon#*mode == 0, iclass 10, count 2 2006.173.04:31:35.99#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.04:31:35.99#ibcon#[25=AT02-06\r\n] 2006.173.04:31:35.99#ibcon#*before write, iclass 10, count 2 2006.173.04:31:35.99#ibcon#enter sib2, iclass 10, count 2 2006.173.04:31:35.99#ibcon#flushed, iclass 10, count 2 2006.173.04:31:35.99#ibcon#about to write, iclass 10, count 2 2006.173.04:31:35.99#ibcon#wrote, iclass 10, count 2 2006.173.04:31:35.99#ibcon#about to read 3, iclass 10, count 2 2006.173.04:31:36.02#ibcon#read 3, iclass 10, count 2 2006.173.04:31:36.02#ibcon#about to read 4, iclass 10, count 2 2006.173.04:31:36.02#ibcon#read 4, iclass 10, count 2 2006.173.04:31:36.02#ibcon#about to read 5, iclass 10, count 2 2006.173.04:31:36.02#ibcon#read 5, iclass 10, count 2 2006.173.04:31:36.02#ibcon#about to read 6, iclass 10, count 2 2006.173.04:31:36.02#ibcon#read 6, iclass 10, count 2 2006.173.04:31:36.02#ibcon#end of sib2, iclass 10, count 2 2006.173.04:31:36.02#ibcon#*after write, iclass 10, count 2 2006.173.04:31:36.02#ibcon#*before return 0, iclass 10, count 2 2006.173.04:31:36.02#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.04:31:36.02#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.04:31:36.02#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.04:31:36.02#ibcon#ireg 7 cls_cnt 0 2006.173.04:31:36.02#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.04:31:36.14#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.04:31:36.14#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.04:31:36.14#ibcon#enter wrdev, iclass 10, count 0 2006.173.04:31:36.14#ibcon#first serial, iclass 10, count 0 2006.173.04:31:36.14#ibcon#enter sib2, iclass 10, count 0 2006.173.04:31:36.14#ibcon#flushed, iclass 10, count 0 2006.173.04:31:36.14#ibcon#about to write, iclass 10, count 0 2006.173.04:31:36.14#ibcon#wrote, iclass 10, count 0 2006.173.04:31:36.14#ibcon#about to read 3, iclass 10, count 0 2006.173.04:31:36.16#ibcon#read 3, iclass 10, count 0 2006.173.04:31:36.16#ibcon#about to read 4, iclass 10, count 0 2006.173.04:31:36.16#ibcon#read 4, iclass 10, count 0 2006.173.04:31:36.16#ibcon#about to read 5, iclass 10, count 0 2006.173.04:31:36.16#ibcon#read 5, iclass 10, count 0 2006.173.04:31:36.16#ibcon#about to read 6, iclass 10, count 0 2006.173.04:31:36.16#ibcon#read 6, iclass 10, count 0 2006.173.04:31:36.16#ibcon#end of sib2, iclass 10, count 0 2006.173.04:31:36.16#ibcon#*mode == 0, iclass 10, count 0 2006.173.04:31:36.16#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.04:31:36.16#ibcon#[25=USB\r\n] 2006.173.04:31:36.16#ibcon#*before write, iclass 10, count 0 2006.173.04:31:36.16#ibcon#enter sib2, iclass 10, count 0 2006.173.04:31:36.16#ibcon#flushed, iclass 10, count 0 2006.173.04:31:36.16#ibcon#about to write, iclass 10, count 0 2006.173.04:31:36.16#ibcon#wrote, iclass 10, count 0 2006.173.04:31:36.16#ibcon#about to read 3, iclass 10, count 0 2006.173.04:31:36.19#ibcon#read 3, iclass 10, count 0 2006.173.04:31:36.19#ibcon#about to read 4, iclass 10, count 0 2006.173.04:31:36.19#ibcon#read 4, iclass 10, count 0 2006.173.04:31:36.19#ibcon#about to read 5, iclass 10, count 0 2006.173.04:31:36.19#ibcon#read 5, iclass 10, count 0 2006.173.04:31:36.19#ibcon#about to read 6, iclass 10, count 0 2006.173.04:31:36.19#ibcon#read 6, iclass 10, count 0 2006.173.04:31:36.19#ibcon#end of sib2, iclass 10, count 0 2006.173.04:31:36.19#ibcon#*after write, iclass 10, count 0 2006.173.04:31:36.19#ibcon#*before return 0, iclass 10, count 0 2006.173.04:31:36.19#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.04:31:36.19#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.04:31:36.19#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.04:31:36.19#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.04:31:36.19$vck44/valo=3,564.99 2006.173.04:31:36.19#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.04:31:36.19#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.04:31:36.19#ibcon#ireg 17 cls_cnt 0 2006.173.04:31:36.19#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.04:31:36.19#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.04:31:36.19#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.04:31:36.19#ibcon#enter wrdev, iclass 12, count 0 2006.173.04:31:36.19#ibcon#first serial, iclass 12, count 0 2006.173.04:31:36.19#ibcon#enter sib2, iclass 12, count 0 2006.173.04:31:36.19#ibcon#flushed, iclass 12, count 0 2006.173.04:31:36.19#ibcon#about to write, iclass 12, count 0 2006.173.04:31:36.19#ibcon#wrote, iclass 12, count 0 2006.173.04:31:36.19#ibcon#about to read 3, iclass 12, count 0 2006.173.04:31:36.21#ibcon#read 3, iclass 12, count 0 2006.173.04:31:36.21#ibcon#about to read 4, iclass 12, count 0 2006.173.04:31:36.21#ibcon#read 4, iclass 12, count 0 2006.173.04:31:36.21#ibcon#about to read 5, iclass 12, count 0 2006.173.04:31:36.21#ibcon#read 5, iclass 12, count 0 2006.173.04:31:36.21#ibcon#about to read 6, iclass 12, count 0 2006.173.04:31:36.21#ibcon#read 6, iclass 12, count 0 2006.173.04:31:36.21#ibcon#end of sib2, iclass 12, count 0 2006.173.04:31:36.21#ibcon#*mode == 0, iclass 12, count 0 2006.173.04:31:36.21#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.04:31:36.21#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.04:31:36.21#ibcon#*before write, iclass 12, count 0 2006.173.04:31:36.21#ibcon#enter sib2, iclass 12, count 0 2006.173.04:31:36.21#ibcon#flushed, iclass 12, count 0 2006.173.04:31:36.21#ibcon#about to write, iclass 12, count 0 2006.173.04:31:36.21#ibcon#wrote, iclass 12, count 0 2006.173.04:31:36.21#ibcon#about to read 3, iclass 12, count 0 2006.173.04:31:36.25#ibcon#read 3, iclass 12, count 0 2006.173.04:31:36.25#ibcon#about to read 4, iclass 12, count 0 2006.173.04:31:36.25#ibcon#read 4, iclass 12, count 0 2006.173.04:31:36.25#ibcon#about to read 5, iclass 12, count 0 2006.173.04:31:36.25#ibcon#read 5, iclass 12, count 0 2006.173.04:31:36.25#ibcon#about to read 6, iclass 12, count 0 2006.173.04:31:36.25#ibcon#read 6, iclass 12, count 0 2006.173.04:31:36.25#ibcon#end of sib2, iclass 12, count 0 2006.173.04:31:36.25#ibcon#*after write, iclass 12, count 0 2006.173.04:31:36.25#ibcon#*before return 0, iclass 12, count 0 2006.173.04:31:36.25#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.04:31:36.25#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.04:31:36.25#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.04:31:36.25#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.04:31:36.25$vck44/va=3,5 2006.173.04:31:36.25#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.04:31:36.25#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.04:31:36.25#ibcon#ireg 11 cls_cnt 2 2006.173.04:31:36.25#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.04:31:36.31#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.04:31:36.31#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.04:31:36.31#ibcon#enter wrdev, iclass 14, count 2 2006.173.04:31:36.31#ibcon#first serial, iclass 14, count 2 2006.173.04:31:36.31#ibcon#enter sib2, iclass 14, count 2 2006.173.04:31:36.31#ibcon#flushed, iclass 14, count 2 2006.173.04:31:36.31#ibcon#about to write, iclass 14, count 2 2006.173.04:31:36.31#ibcon#wrote, iclass 14, count 2 2006.173.04:31:36.31#ibcon#about to read 3, iclass 14, count 2 2006.173.04:31:36.33#ibcon#read 3, iclass 14, count 2 2006.173.04:31:36.33#ibcon#about to read 4, iclass 14, count 2 2006.173.04:31:36.33#ibcon#read 4, iclass 14, count 2 2006.173.04:31:36.33#ibcon#about to read 5, iclass 14, count 2 2006.173.04:31:36.33#ibcon#read 5, iclass 14, count 2 2006.173.04:31:36.33#ibcon#about to read 6, iclass 14, count 2 2006.173.04:31:36.33#ibcon#read 6, iclass 14, count 2 2006.173.04:31:36.33#ibcon#end of sib2, iclass 14, count 2 2006.173.04:31:36.33#ibcon#*mode == 0, iclass 14, count 2 2006.173.04:31:36.33#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.04:31:36.33#ibcon#[25=AT03-05\r\n] 2006.173.04:31:36.33#ibcon#*before write, iclass 14, count 2 2006.173.04:31:36.33#ibcon#enter sib2, iclass 14, count 2 2006.173.04:31:36.33#ibcon#flushed, iclass 14, count 2 2006.173.04:31:36.33#ibcon#about to write, iclass 14, count 2 2006.173.04:31:36.33#ibcon#wrote, iclass 14, count 2 2006.173.04:31:36.33#ibcon#about to read 3, iclass 14, count 2 2006.173.04:31:36.36#ibcon#read 3, iclass 14, count 2 2006.173.04:31:36.36#ibcon#about to read 4, iclass 14, count 2 2006.173.04:31:36.36#ibcon#read 4, iclass 14, count 2 2006.173.04:31:36.36#ibcon#about to read 5, iclass 14, count 2 2006.173.04:31:36.36#ibcon#read 5, iclass 14, count 2 2006.173.04:31:36.36#ibcon#about to read 6, iclass 14, count 2 2006.173.04:31:36.36#ibcon#read 6, iclass 14, count 2 2006.173.04:31:36.36#ibcon#end of sib2, iclass 14, count 2 2006.173.04:31:36.36#ibcon#*after write, iclass 14, count 2 2006.173.04:31:36.36#ibcon#*before return 0, iclass 14, count 2 2006.173.04:31:36.36#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.04:31:36.36#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.04:31:36.36#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.04:31:36.36#ibcon#ireg 7 cls_cnt 0 2006.173.04:31:36.36#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.04:31:36.48#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.04:31:36.48#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.04:31:36.48#ibcon#enter wrdev, iclass 14, count 0 2006.173.04:31:36.48#ibcon#first serial, iclass 14, count 0 2006.173.04:31:36.48#ibcon#enter sib2, iclass 14, count 0 2006.173.04:31:36.48#ibcon#flushed, iclass 14, count 0 2006.173.04:31:36.48#ibcon#about to write, iclass 14, count 0 2006.173.04:31:36.48#ibcon#wrote, iclass 14, count 0 2006.173.04:31:36.48#ibcon#about to read 3, iclass 14, count 0 2006.173.04:31:36.50#ibcon#read 3, iclass 14, count 0 2006.173.04:31:36.50#ibcon#about to read 4, iclass 14, count 0 2006.173.04:31:36.50#ibcon#read 4, iclass 14, count 0 2006.173.04:31:36.50#ibcon#about to read 5, iclass 14, count 0 2006.173.04:31:36.50#ibcon#read 5, iclass 14, count 0 2006.173.04:31:36.50#ibcon#about to read 6, iclass 14, count 0 2006.173.04:31:36.50#ibcon#read 6, iclass 14, count 0 2006.173.04:31:36.50#ibcon#end of sib2, iclass 14, count 0 2006.173.04:31:36.50#ibcon#*mode == 0, iclass 14, count 0 2006.173.04:31:36.50#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.04:31:36.50#ibcon#[25=USB\r\n] 2006.173.04:31:36.50#ibcon#*before write, iclass 14, count 0 2006.173.04:31:36.50#ibcon#enter sib2, iclass 14, count 0 2006.173.04:31:36.50#ibcon#flushed, iclass 14, count 0 2006.173.04:31:36.50#ibcon#about to write, iclass 14, count 0 2006.173.04:31:36.50#ibcon#wrote, iclass 14, count 0 2006.173.04:31:36.50#ibcon#about to read 3, iclass 14, count 0 2006.173.04:31:36.53#ibcon#read 3, iclass 14, count 0 2006.173.04:31:36.53#ibcon#about to read 4, iclass 14, count 0 2006.173.04:31:36.53#ibcon#read 4, iclass 14, count 0 2006.173.04:31:36.53#ibcon#about to read 5, iclass 14, count 0 2006.173.04:31:36.53#ibcon#read 5, iclass 14, count 0 2006.173.04:31:36.53#ibcon#about to read 6, iclass 14, count 0 2006.173.04:31:36.53#ibcon#read 6, iclass 14, count 0 2006.173.04:31:36.53#ibcon#end of sib2, iclass 14, count 0 2006.173.04:31:36.53#ibcon#*after write, iclass 14, count 0 2006.173.04:31:36.53#ibcon#*before return 0, iclass 14, count 0 2006.173.04:31:36.53#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.04:31:36.53#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.04:31:36.53#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.04:31:36.53#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.04:31:36.53$vck44/valo=4,624.99 2006.173.04:31:36.53#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.04:31:36.53#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.04:31:36.53#ibcon#ireg 17 cls_cnt 0 2006.173.04:31:36.53#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.04:31:36.53#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.04:31:36.53#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.04:31:36.53#ibcon#enter wrdev, iclass 16, count 0 2006.173.04:31:36.53#ibcon#first serial, iclass 16, count 0 2006.173.04:31:36.53#ibcon#enter sib2, iclass 16, count 0 2006.173.04:31:36.53#ibcon#flushed, iclass 16, count 0 2006.173.04:31:36.53#ibcon#about to write, iclass 16, count 0 2006.173.04:31:36.53#ibcon#wrote, iclass 16, count 0 2006.173.04:31:36.53#ibcon#about to read 3, iclass 16, count 0 2006.173.04:31:36.55#ibcon#read 3, iclass 16, count 0 2006.173.04:31:36.55#ibcon#about to read 4, iclass 16, count 0 2006.173.04:31:36.55#ibcon#read 4, iclass 16, count 0 2006.173.04:31:36.55#ibcon#about to read 5, iclass 16, count 0 2006.173.04:31:36.55#ibcon#read 5, iclass 16, count 0 2006.173.04:31:36.55#ibcon#about to read 6, iclass 16, count 0 2006.173.04:31:36.55#ibcon#read 6, iclass 16, count 0 2006.173.04:31:36.55#ibcon#end of sib2, iclass 16, count 0 2006.173.04:31:36.55#ibcon#*mode == 0, iclass 16, count 0 2006.173.04:31:36.55#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.04:31:36.55#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.04:31:36.55#ibcon#*before write, iclass 16, count 0 2006.173.04:31:36.55#ibcon#enter sib2, iclass 16, count 0 2006.173.04:31:36.55#ibcon#flushed, iclass 16, count 0 2006.173.04:31:36.55#ibcon#about to write, iclass 16, count 0 2006.173.04:31:36.55#ibcon#wrote, iclass 16, count 0 2006.173.04:31:36.55#ibcon#about to read 3, iclass 16, count 0 2006.173.04:31:36.59#ibcon#read 3, iclass 16, count 0 2006.173.04:31:36.59#ibcon#about to read 4, iclass 16, count 0 2006.173.04:31:36.59#ibcon#read 4, iclass 16, count 0 2006.173.04:31:36.59#ibcon#about to read 5, iclass 16, count 0 2006.173.04:31:36.59#ibcon#read 5, iclass 16, count 0 2006.173.04:31:36.59#ibcon#about to read 6, iclass 16, count 0 2006.173.04:31:36.59#ibcon#read 6, iclass 16, count 0 2006.173.04:31:36.59#ibcon#end of sib2, iclass 16, count 0 2006.173.04:31:36.59#ibcon#*after write, iclass 16, count 0 2006.173.04:31:36.59#ibcon#*before return 0, iclass 16, count 0 2006.173.04:31:36.59#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.04:31:36.59#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.04:31:36.59#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.04:31:36.59#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.04:31:36.59$vck44/va=4,6 2006.173.04:31:36.59#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.04:31:36.59#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.04:31:36.59#ibcon#ireg 11 cls_cnt 2 2006.173.04:31:36.59#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.04:31:36.65#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.04:31:36.65#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.04:31:36.65#ibcon#enter wrdev, iclass 18, count 2 2006.173.04:31:36.65#ibcon#first serial, iclass 18, count 2 2006.173.04:31:36.65#ibcon#enter sib2, iclass 18, count 2 2006.173.04:31:36.65#ibcon#flushed, iclass 18, count 2 2006.173.04:31:36.65#ibcon#about to write, iclass 18, count 2 2006.173.04:31:36.65#ibcon#wrote, iclass 18, count 2 2006.173.04:31:36.65#ibcon#about to read 3, iclass 18, count 2 2006.173.04:31:36.67#ibcon#read 3, iclass 18, count 2 2006.173.04:31:36.67#ibcon#about to read 4, iclass 18, count 2 2006.173.04:31:36.67#ibcon#read 4, iclass 18, count 2 2006.173.04:31:36.67#ibcon#about to read 5, iclass 18, count 2 2006.173.04:31:36.67#ibcon#read 5, iclass 18, count 2 2006.173.04:31:36.67#ibcon#about to read 6, iclass 18, count 2 2006.173.04:31:36.67#ibcon#read 6, iclass 18, count 2 2006.173.04:31:36.67#ibcon#end of sib2, iclass 18, count 2 2006.173.04:31:36.67#ibcon#*mode == 0, iclass 18, count 2 2006.173.04:31:36.67#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.04:31:36.67#ibcon#[25=AT04-06\r\n] 2006.173.04:31:36.67#ibcon#*before write, iclass 18, count 2 2006.173.04:31:36.67#ibcon#enter sib2, iclass 18, count 2 2006.173.04:31:36.67#ibcon#flushed, iclass 18, count 2 2006.173.04:31:36.67#ibcon#about to write, iclass 18, count 2 2006.173.04:31:36.67#ibcon#wrote, iclass 18, count 2 2006.173.04:31:36.67#ibcon#about to read 3, iclass 18, count 2 2006.173.04:31:36.70#ibcon#read 3, iclass 18, count 2 2006.173.04:31:36.70#ibcon#about to read 4, iclass 18, count 2 2006.173.04:31:36.70#ibcon#read 4, iclass 18, count 2 2006.173.04:31:36.70#ibcon#about to read 5, iclass 18, count 2 2006.173.04:31:36.70#ibcon#read 5, iclass 18, count 2 2006.173.04:31:36.70#ibcon#about to read 6, iclass 18, count 2 2006.173.04:31:36.70#ibcon#read 6, iclass 18, count 2 2006.173.04:31:36.70#ibcon#end of sib2, iclass 18, count 2 2006.173.04:31:36.70#ibcon#*after write, iclass 18, count 2 2006.173.04:31:36.70#ibcon#*before return 0, iclass 18, count 2 2006.173.04:31:36.70#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.04:31:36.70#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.04:31:36.70#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.04:31:36.70#ibcon#ireg 7 cls_cnt 0 2006.173.04:31:36.70#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.04:31:36.82#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.04:31:36.82#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.04:31:36.82#ibcon#enter wrdev, iclass 18, count 0 2006.173.04:31:36.82#ibcon#first serial, iclass 18, count 0 2006.173.04:31:36.82#ibcon#enter sib2, iclass 18, count 0 2006.173.04:31:36.82#ibcon#flushed, iclass 18, count 0 2006.173.04:31:36.82#ibcon#about to write, iclass 18, count 0 2006.173.04:31:36.82#ibcon#wrote, iclass 18, count 0 2006.173.04:31:36.82#ibcon#about to read 3, iclass 18, count 0 2006.173.04:31:36.84#ibcon#read 3, iclass 18, count 0 2006.173.04:31:36.84#ibcon#about to read 4, iclass 18, count 0 2006.173.04:31:36.84#ibcon#read 4, iclass 18, count 0 2006.173.04:31:36.84#ibcon#about to read 5, iclass 18, count 0 2006.173.04:31:36.84#ibcon#read 5, iclass 18, count 0 2006.173.04:31:36.84#ibcon#about to read 6, iclass 18, count 0 2006.173.04:31:36.84#ibcon#read 6, iclass 18, count 0 2006.173.04:31:36.84#ibcon#end of sib2, iclass 18, count 0 2006.173.04:31:36.84#ibcon#*mode == 0, iclass 18, count 0 2006.173.04:31:36.84#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.04:31:36.84#ibcon#[25=USB\r\n] 2006.173.04:31:36.84#ibcon#*before write, iclass 18, count 0 2006.173.04:31:36.84#ibcon#enter sib2, iclass 18, count 0 2006.173.04:31:36.84#ibcon#flushed, iclass 18, count 0 2006.173.04:31:36.84#ibcon#about to write, iclass 18, count 0 2006.173.04:31:36.84#ibcon#wrote, iclass 18, count 0 2006.173.04:31:36.84#ibcon#about to read 3, iclass 18, count 0 2006.173.04:31:36.87#ibcon#read 3, iclass 18, count 0 2006.173.04:31:36.87#ibcon#about to read 4, iclass 18, count 0 2006.173.04:31:36.87#ibcon#read 4, iclass 18, count 0 2006.173.04:31:36.87#ibcon#about to read 5, iclass 18, count 0 2006.173.04:31:36.87#ibcon#read 5, iclass 18, count 0 2006.173.04:31:36.87#ibcon#about to read 6, iclass 18, count 0 2006.173.04:31:36.87#ibcon#read 6, iclass 18, count 0 2006.173.04:31:36.87#ibcon#end of sib2, iclass 18, count 0 2006.173.04:31:36.87#ibcon#*after write, iclass 18, count 0 2006.173.04:31:36.87#ibcon#*before return 0, iclass 18, count 0 2006.173.04:31:36.87#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.04:31:36.87#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.04:31:36.87#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.04:31:36.87#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.04:31:36.87$vck44/valo=5,734.99 2006.173.04:31:36.87#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.04:31:36.87#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.04:31:36.87#ibcon#ireg 17 cls_cnt 0 2006.173.04:31:36.87#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.04:31:36.87#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.04:31:36.87#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.04:31:36.87#ibcon#enter wrdev, iclass 20, count 0 2006.173.04:31:36.87#ibcon#first serial, iclass 20, count 0 2006.173.04:31:36.87#ibcon#enter sib2, iclass 20, count 0 2006.173.04:31:36.87#ibcon#flushed, iclass 20, count 0 2006.173.04:31:36.87#ibcon#about to write, iclass 20, count 0 2006.173.04:31:36.87#ibcon#wrote, iclass 20, count 0 2006.173.04:31:36.87#ibcon#about to read 3, iclass 20, count 0 2006.173.04:31:36.89#ibcon#read 3, iclass 20, count 0 2006.173.04:31:36.89#ibcon#about to read 4, iclass 20, count 0 2006.173.04:31:36.89#ibcon#read 4, iclass 20, count 0 2006.173.04:31:36.89#ibcon#about to read 5, iclass 20, count 0 2006.173.04:31:36.89#ibcon#read 5, iclass 20, count 0 2006.173.04:31:36.89#ibcon#about to read 6, iclass 20, count 0 2006.173.04:31:36.89#ibcon#read 6, iclass 20, count 0 2006.173.04:31:36.89#ibcon#end of sib2, iclass 20, count 0 2006.173.04:31:36.89#ibcon#*mode == 0, iclass 20, count 0 2006.173.04:31:36.89#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.04:31:36.89#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.04:31:36.89#ibcon#*before write, iclass 20, count 0 2006.173.04:31:36.89#ibcon#enter sib2, iclass 20, count 0 2006.173.04:31:36.89#ibcon#flushed, iclass 20, count 0 2006.173.04:31:36.89#ibcon#about to write, iclass 20, count 0 2006.173.04:31:36.89#ibcon#wrote, iclass 20, count 0 2006.173.04:31:36.89#ibcon#about to read 3, iclass 20, count 0 2006.173.04:31:36.93#ibcon#read 3, iclass 20, count 0 2006.173.04:31:36.93#ibcon#about to read 4, iclass 20, count 0 2006.173.04:31:36.93#ibcon#read 4, iclass 20, count 0 2006.173.04:31:36.93#ibcon#about to read 5, iclass 20, count 0 2006.173.04:31:36.93#ibcon#read 5, iclass 20, count 0 2006.173.04:31:36.93#ibcon#about to read 6, iclass 20, count 0 2006.173.04:31:36.93#ibcon#read 6, iclass 20, count 0 2006.173.04:31:36.93#ibcon#end of sib2, iclass 20, count 0 2006.173.04:31:36.93#ibcon#*after write, iclass 20, count 0 2006.173.04:31:36.93#ibcon#*before return 0, iclass 20, count 0 2006.173.04:31:36.93#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.04:31:36.93#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.04:31:36.93#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.04:31:36.93#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.04:31:36.93$vck44/va=5,4 2006.173.04:31:36.93#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.04:31:36.93#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.04:31:36.93#ibcon#ireg 11 cls_cnt 2 2006.173.04:31:36.93#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.04:31:36.99#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.04:31:36.99#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.04:31:36.99#ibcon#enter wrdev, iclass 22, count 2 2006.173.04:31:36.99#ibcon#first serial, iclass 22, count 2 2006.173.04:31:36.99#ibcon#enter sib2, iclass 22, count 2 2006.173.04:31:36.99#ibcon#flushed, iclass 22, count 2 2006.173.04:31:36.99#ibcon#about to write, iclass 22, count 2 2006.173.04:31:36.99#ibcon#wrote, iclass 22, count 2 2006.173.04:31:36.99#ibcon#about to read 3, iclass 22, count 2 2006.173.04:31:37.01#ibcon#read 3, iclass 22, count 2 2006.173.04:31:37.01#ibcon#about to read 4, iclass 22, count 2 2006.173.04:31:37.01#ibcon#read 4, iclass 22, count 2 2006.173.04:31:37.01#ibcon#about to read 5, iclass 22, count 2 2006.173.04:31:37.01#ibcon#read 5, iclass 22, count 2 2006.173.04:31:37.01#ibcon#about to read 6, iclass 22, count 2 2006.173.04:31:37.01#ibcon#read 6, iclass 22, count 2 2006.173.04:31:37.01#ibcon#end of sib2, iclass 22, count 2 2006.173.04:31:37.01#ibcon#*mode == 0, iclass 22, count 2 2006.173.04:31:37.01#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.04:31:37.01#ibcon#[25=AT05-04\r\n] 2006.173.04:31:37.01#ibcon#*before write, iclass 22, count 2 2006.173.04:31:37.01#ibcon#enter sib2, iclass 22, count 2 2006.173.04:31:37.01#ibcon#flushed, iclass 22, count 2 2006.173.04:31:37.01#ibcon#about to write, iclass 22, count 2 2006.173.04:31:37.01#ibcon#wrote, iclass 22, count 2 2006.173.04:31:37.01#ibcon#about to read 3, iclass 22, count 2 2006.173.04:31:37.04#ibcon#read 3, iclass 22, count 2 2006.173.04:31:37.04#ibcon#about to read 4, iclass 22, count 2 2006.173.04:31:37.04#ibcon#read 4, iclass 22, count 2 2006.173.04:31:37.04#ibcon#about to read 5, iclass 22, count 2 2006.173.04:31:37.04#ibcon#read 5, iclass 22, count 2 2006.173.04:31:37.04#ibcon#about to read 6, iclass 22, count 2 2006.173.04:31:37.04#ibcon#read 6, iclass 22, count 2 2006.173.04:31:37.04#ibcon#end of sib2, iclass 22, count 2 2006.173.04:31:37.04#ibcon#*after write, iclass 22, count 2 2006.173.04:31:37.04#ibcon#*before return 0, iclass 22, count 2 2006.173.04:31:37.04#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.04:31:37.04#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.04:31:37.04#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.04:31:37.04#ibcon#ireg 7 cls_cnt 0 2006.173.04:31:37.04#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.04:31:37.16#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.04:31:37.16#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.04:31:37.16#ibcon#enter wrdev, iclass 22, count 0 2006.173.04:31:37.16#ibcon#first serial, iclass 22, count 0 2006.173.04:31:37.16#ibcon#enter sib2, iclass 22, count 0 2006.173.04:31:37.16#ibcon#flushed, iclass 22, count 0 2006.173.04:31:37.16#ibcon#about to write, iclass 22, count 0 2006.173.04:31:37.16#ibcon#wrote, iclass 22, count 0 2006.173.04:31:37.16#ibcon#about to read 3, iclass 22, count 0 2006.173.04:31:37.18#ibcon#read 3, iclass 22, count 0 2006.173.04:31:37.18#ibcon#about to read 4, iclass 22, count 0 2006.173.04:31:37.18#ibcon#read 4, iclass 22, count 0 2006.173.04:31:37.18#ibcon#about to read 5, iclass 22, count 0 2006.173.04:31:37.18#ibcon#read 5, iclass 22, count 0 2006.173.04:31:37.18#ibcon#about to read 6, iclass 22, count 0 2006.173.04:31:37.18#ibcon#read 6, iclass 22, count 0 2006.173.04:31:37.18#ibcon#end of sib2, iclass 22, count 0 2006.173.04:31:37.18#ibcon#*mode == 0, iclass 22, count 0 2006.173.04:31:37.18#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.04:31:37.18#ibcon#[25=USB\r\n] 2006.173.04:31:37.18#ibcon#*before write, iclass 22, count 0 2006.173.04:31:37.18#ibcon#enter sib2, iclass 22, count 0 2006.173.04:31:37.18#ibcon#flushed, iclass 22, count 0 2006.173.04:31:37.18#ibcon#about to write, iclass 22, count 0 2006.173.04:31:37.18#ibcon#wrote, iclass 22, count 0 2006.173.04:31:37.18#ibcon#about to read 3, iclass 22, count 0 2006.173.04:31:37.21#ibcon#read 3, iclass 22, count 0 2006.173.04:31:37.21#ibcon#about to read 4, iclass 22, count 0 2006.173.04:31:37.21#ibcon#read 4, iclass 22, count 0 2006.173.04:31:37.21#ibcon#about to read 5, iclass 22, count 0 2006.173.04:31:37.21#ibcon#read 5, iclass 22, count 0 2006.173.04:31:37.21#ibcon#about to read 6, iclass 22, count 0 2006.173.04:31:37.21#ibcon#read 6, iclass 22, count 0 2006.173.04:31:37.21#ibcon#end of sib2, iclass 22, count 0 2006.173.04:31:37.21#ibcon#*after write, iclass 22, count 0 2006.173.04:31:37.21#ibcon#*before return 0, iclass 22, count 0 2006.173.04:31:37.21#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.04:31:37.21#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.04:31:37.21#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.04:31:37.21#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.04:31:37.21$vck44/valo=6,814.99 2006.173.04:31:37.21#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.04:31:37.21#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.04:31:37.21#ibcon#ireg 17 cls_cnt 0 2006.173.04:31:37.21#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.04:31:37.21#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.04:31:37.21#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.04:31:37.21#ibcon#enter wrdev, iclass 24, count 0 2006.173.04:31:37.21#ibcon#first serial, iclass 24, count 0 2006.173.04:31:37.21#ibcon#enter sib2, iclass 24, count 0 2006.173.04:31:37.21#ibcon#flushed, iclass 24, count 0 2006.173.04:31:37.21#ibcon#about to write, iclass 24, count 0 2006.173.04:31:37.21#ibcon#wrote, iclass 24, count 0 2006.173.04:31:37.21#ibcon#about to read 3, iclass 24, count 0 2006.173.04:31:37.23#ibcon#read 3, iclass 24, count 0 2006.173.04:31:37.23#ibcon#about to read 4, iclass 24, count 0 2006.173.04:31:37.23#ibcon#read 4, iclass 24, count 0 2006.173.04:31:37.23#ibcon#about to read 5, iclass 24, count 0 2006.173.04:31:37.23#ibcon#read 5, iclass 24, count 0 2006.173.04:31:37.23#ibcon#about to read 6, iclass 24, count 0 2006.173.04:31:37.23#ibcon#read 6, iclass 24, count 0 2006.173.04:31:37.23#ibcon#end of sib2, iclass 24, count 0 2006.173.04:31:37.23#ibcon#*mode == 0, iclass 24, count 0 2006.173.04:31:37.23#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.04:31:37.23#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.04:31:37.23#ibcon#*before write, iclass 24, count 0 2006.173.04:31:37.23#ibcon#enter sib2, iclass 24, count 0 2006.173.04:31:37.23#ibcon#flushed, iclass 24, count 0 2006.173.04:31:37.23#ibcon#about to write, iclass 24, count 0 2006.173.04:31:37.23#ibcon#wrote, iclass 24, count 0 2006.173.04:31:37.23#ibcon#about to read 3, iclass 24, count 0 2006.173.04:31:37.27#ibcon#read 3, iclass 24, count 0 2006.173.04:31:37.27#ibcon#about to read 4, iclass 24, count 0 2006.173.04:31:37.27#ibcon#read 4, iclass 24, count 0 2006.173.04:31:37.27#ibcon#about to read 5, iclass 24, count 0 2006.173.04:31:37.27#ibcon#read 5, iclass 24, count 0 2006.173.04:31:37.27#ibcon#about to read 6, iclass 24, count 0 2006.173.04:31:37.27#ibcon#read 6, iclass 24, count 0 2006.173.04:31:37.27#ibcon#end of sib2, iclass 24, count 0 2006.173.04:31:37.27#ibcon#*after write, iclass 24, count 0 2006.173.04:31:37.27#ibcon#*before return 0, iclass 24, count 0 2006.173.04:31:37.27#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.04:31:37.27#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.04:31:37.27#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.04:31:37.27#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.04:31:37.27$vck44/va=6,3 2006.173.04:31:37.27#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.04:31:37.27#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.04:31:37.27#ibcon#ireg 11 cls_cnt 2 2006.173.04:31:37.27#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.04:31:37.33#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.04:31:37.33#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.04:31:37.33#ibcon#enter wrdev, iclass 26, count 2 2006.173.04:31:37.33#ibcon#first serial, iclass 26, count 2 2006.173.04:31:37.33#ibcon#enter sib2, iclass 26, count 2 2006.173.04:31:37.33#ibcon#flushed, iclass 26, count 2 2006.173.04:31:37.33#ibcon#about to write, iclass 26, count 2 2006.173.04:31:37.33#ibcon#wrote, iclass 26, count 2 2006.173.04:31:37.33#ibcon#about to read 3, iclass 26, count 2 2006.173.04:31:37.35#ibcon#read 3, iclass 26, count 2 2006.173.04:31:37.35#ibcon#about to read 4, iclass 26, count 2 2006.173.04:31:37.35#ibcon#read 4, iclass 26, count 2 2006.173.04:31:37.35#ibcon#about to read 5, iclass 26, count 2 2006.173.04:31:37.35#ibcon#read 5, iclass 26, count 2 2006.173.04:31:37.35#ibcon#about to read 6, iclass 26, count 2 2006.173.04:31:37.35#ibcon#read 6, iclass 26, count 2 2006.173.04:31:37.35#ibcon#end of sib2, iclass 26, count 2 2006.173.04:31:37.35#ibcon#*mode == 0, iclass 26, count 2 2006.173.04:31:37.35#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.04:31:37.35#ibcon#[25=AT06-03\r\n] 2006.173.04:31:37.35#ibcon#*before write, iclass 26, count 2 2006.173.04:31:37.35#ibcon#enter sib2, iclass 26, count 2 2006.173.04:31:37.35#ibcon#flushed, iclass 26, count 2 2006.173.04:31:37.35#ibcon#about to write, iclass 26, count 2 2006.173.04:31:37.35#ibcon#wrote, iclass 26, count 2 2006.173.04:31:37.35#ibcon#about to read 3, iclass 26, count 2 2006.173.04:31:37.38#ibcon#read 3, iclass 26, count 2 2006.173.04:31:37.38#ibcon#about to read 4, iclass 26, count 2 2006.173.04:31:37.38#ibcon#read 4, iclass 26, count 2 2006.173.04:31:37.38#ibcon#about to read 5, iclass 26, count 2 2006.173.04:31:37.38#ibcon#read 5, iclass 26, count 2 2006.173.04:31:37.38#ibcon#about to read 6, iclass 26, count 2 2006.173.04:31:37.38#ibcon#read 6, iclass 26, count 2 2006.173.04:31:37.38#ibcon#end of sib2, iclass 26, count 2 2006.173.04:31:37.38#ibcon#*after write, iclass 26, count 2 2006.173.04:31:37.38#ibcon#*before return 0, iclass 26, count 2 2006.173.04:31:37.38#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.04:31:37.38#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.04:31:37.38#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.04:31:37.38#ibcon#ireg 7 cls_cnt 0 2006.173.04:31:37.38#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.04:31:37.50#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.04:31:37.50#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.04:31:37.50#ibcon#enter wrdev, iclass 26, count 0 2006.173.04:31:37.50#ibcon#first serial, iclass 26, count 0 2006.173.04:31:37.50#ibcon#enter sib2, iclass 26, count 0 2006.173.04:31:37.50#ibcon#flushed, iclass 26, count 0 2006.173.04:31:37.50#ibcon#about to write, iclass 26, count 0 2006.173.04:31:37.50#ibcon#wrote, iclass 26, count 0 2006.173.04:31:37.50#ibcon#about to read 3, iclass 26, count 0 2006.173.04:31:37.52#ibcon#read 3, iclass 26, count 0 2006.173.04:31:37.52#ibcon#about to read 4, iclass 26, count 0 2006.173.04:31:37.52#ibcon#read 4, iclass 26, count 0 2006.173.04:31:37.52#ibcon#about to read 5, iclass 26, count 0 2006.173.04:31:37.52#ibcon#read 5, iclass 26, count 0 2006.173.04:31:37.52#ibcon#about to read 6, iclass 26, count 0 2006.173.04:31:37.52#ibcon#read 6, iclass 26, count 0 2006.173.04:31:37.52#ibcon#end of sib2, iclass 26, count 0 2006.173.04:31:37.52#ibcon#*mode == 0, iclass 26, count 0 2006.173.04:31:37.52#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.04:31:37.52#ibcon#[25=USB\r\n] 2006.173.04:31:37.52#ibcon#*before write, iclass 26, count 0 2006.173.04:31:37.52#ibcon#enter sib2, iclass 26, count 0 2006.173.04:31:37.52#ibcon#flushed, iclass 26, count 0 2006.173.04:31:37.52#ibcon#about to write, iclass 26, count 0 2006.173.04:31:37.52#ibcon#wrote, iclass 26, count 0 2006.173.04:31:37.52#ibcon#about to read 3, iclass 26, count 0 2006.173.04:31:37.55#ibcon#read 3, iclass 26, count 0 2006.173.04:31:37.55#ibcon#about to read 4, iclass 26, count 0 2006.173.04:31:37.55#ibcon#read 4, iclass 26, count 0 2006.173.04:31:37.55#ibcon#about to read 5, iclass 26, count 0 2006.173.04:31:37.55#ibcon#read 5, iclass 26, count 0 2006.173.04:31:37.55#ibcon#about to read 6, iclass 26, count 0 2006.173.04:31:37.55#ibcon#read 6, iclass 26, count 0 2006.173.04:31:37.55#ibcon#end of sib2, iclass 26, count 0 2006.173.04:31:37.55#ibcon#*after write, iclass 26, count 0 2006.173.04:31:37.55#ibcon#*before return 0, iclass 26, count 0 2006.173.04:31:37.55#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.04:31:37.55#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.04:31:37.55#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.04:31:37.55#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.04:31:37.55$vck44/valo=7,864.99 2006.173.04:31:37.55#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.04:31:37.55#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.04:31:37.55#ibcon#ireg 17 cls_cnt 0 2006.173.04:31:37.55#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.04:31:37.55#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.04:31:37.55#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.04:31:37.55#ibcon#enter wrdev, iclass 28, count 0 2006.173.04:31:37.55#ibcon#first serial, iclass 28, count 0 2006.173.04:31:37.55#ibcon#enter sib2, iclass 28, count 0 2006.173.04:31:37.55#ibcon#flushed, iclass 28, count 0 2006.173.04:31:37.55#ibcon#about to write, iclass 28, count 0 2006.173.04:31:37.55#ibcon#wrote, iclass 28, count 0 2006.173.04:31:37.55#ibcon#about to read 3, iclass 28, count 0 2006.173.04:31:37.57#ibcon#read 3, iclass 28, count 0 2006.173.04:31:37.57#ibcon#about to read 4, iclass 28, count 0 2006.173.04:31:37.57#ibcon#read 4, iclass 28, count 0 2006.173.04:31:37.57#ibcon#about to read 5, iclass 28, count 0 2006.173.04:31:37.57#ibcon#read 5, iclass 28, count 0 2006.173.04:31:37.57#ibcon#about to read 6, iclass 28, count 0 2006.173.04:31:37.57#ibcon#read 6, iclass 28, count 0 2006.173.04:31:37.57#ibcon#end of sib2, iclass 28, count 0 2006.173.04:31:37.57#ibcon#*mode == 0, iclass 28, count 0 2006.173.04:31:37.57#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.04:31:37.57#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.04:31:37.57#ibcon#*before write, iclass 28, count 0 2006.173.04:31:37.57#ibcon#enter sib2, iclass 28, count 0 2006.173.04:31:37.57#ibcon#flushed, iclass 28, count 0 2006.173.04:31:37.57#ibcon#about to write, iclass 28, count 0 2006.173.04:31:37.57#ibcon#wrote, iclass 28, count 0 2006.173.04:31:37.57#ibcon#about to read 3, iclass 28, count 0 2006.173.04:31:37.61#ibcon#read 3, iclass 28, count 0 2006.173.04:31:37.61#ibcon#about to read 4, iclass 28, count 0 2006.173.04:31:37.61#ibcon#read 4, iclass 28, count 0 2006.173.04:31:37.61#ibcon#about to read 5, iclass 28, count 0 2006.173.04:31:37.61#ibcon#read 5, iclass 28, count 0 2006.173.04:31:37.61#ibcon#about to read 6, iclass 28, count 0 2006.173.04:31:37.61#ibcon#read 6, iclass 28, count 0 2006.173.04:31:37.61#ibcon#end of sib2, iclass 28, count 0 2006.173.04:31:37.61#ibcon#*after write, iclass 28, count 0 2006.173.04:31:37.61#ibcon#*before return 0, iclass 28, count 0 2006.173.04:31:37.61#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.04:31:37.61#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.04:31:37.61#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.04:31:37.61#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.04:31:37.61$vck44/va=7,4 2006.173.04:31:37.61#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.04:31:37.61#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.04:31:37.61#ibcon#ireg 11 cls_cnt 2 2006.173.04:31:37.61#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.04:31:37.67#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.04:31:37.67#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.04:31:37.67#ibcon#enter wrdev, iclass 30, count 2 2006.173.04:31:37.67#ibcon#first serial, iclass 30, count 2 2006.173.04:31:37.67#ibcon#enter sib2, iclass 30, count 2 2006.173.04:31:37.67#ibcon#flushed, iclass 30, count 2 2006.173.04:31:37.67#ibcon#about to write, iclass 30, count 2 2006.173.04:31:37.67#ibcon#wrote, iclass 30, count 2 2006.173.04:31:37.67#ibcon#about to read 3, iclass 30, count 2 2006.173.04:31:37.69#ibcon#read 3, iclass 30, count 2 2006.173.04:31:37.69#ibcon#about to read 4, iclass 30, count 2 2006.173.04:31:37.69#ibcon#read 4, iclass 30, count 2 2006.173.04:31:37.69#ibcon#about to read 5, iclass 30, count 2 2006.173.04:31:37.69#ibcon#read 5, iclass 30, count 2 2006.173.04:31:37.69#ibcon#about to read 6, iclass 30, count 2 2006.173.04:31:37.69#ibcon#read 6, iclass 30, count 2 2006.173.04:31:37.69#ibcon#end of sib2, iclass 30, count 2 2006.173.04:31:37.69#ibcon#*mode == 0, iclass 30, count 2 2006.173.04:31:37.69#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.04:31:37.69#ibcon#[25=AT07-04\r\n] 2006.173.04:31:37.69#ibcon#*before write, iclass 30, count 2 2006.173.04:31:37.69#ibcon#enter sib2, iclass 30, count 2 2006.173.04:31:37.69#ibcon#flushed, iclass 30, count 2 2006.173.04:31:37.69#ibcon#about to write, iclass 30, count 2 2006.173.04:31:37.69#ibcon#wrote, iclass 30, count 2 2006.173.04:31:37.69#ibcon#about to read 3, iclass 30, count 2 2006.173.04:31:37.72#ibcon#read 3, iclass 30, count 2 2006.173.04:31:37.72#ibcon#about to read 4, iclass 30, count 2 2006.173.04:31:37.72#ibcon#read 4, iclass 30, count 2 2006.173.04:31:37.72#ibcon#about to read 5, iclass 30, count 2 2006.173.04:31:37.72#ibcon#read 5, iclass 30, count 2 2006.173.04:31:37.72#ibcon#about to read 6, iclass 30, count 2 2006.173.04:31:37.72#ibcon#read 6, iclass 30, count 2 2006.173.04:31:37.72#ibcon#end of sib2, iclass 30, count 2 2006.173.04:31:37.72#ibcon#*after write, iclass 30, count 2 2006.173.04:31:37.72#ibcon#*before return 0, iclass 30, count 2 2006.173.04:31:37.72#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.04:31:37.72#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.04:31:37.72#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.04:31:37.72#ibcon#ireg 7 cls_cnt 0 2006.173.04:31:37.72#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.04:31:37.84#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.04:31:37.84#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.04:31:37.84#ibcon#enter wrdev, iclass 30, count 0 2006.173.04:31:37.84#ibcon#first serial, iclass 30, count 0 2006.173.04:31:37.84#ibcon#enter sib2, iclass 30, count 0 2006.173.04:31:37.84#ibcon#flushed, iclass 30, count 0 2006.173.04:31:37.84#ibcon#about to write, iclass 30, count 0 2006.173.04:31:37.84#ibcon#wrote, iclass 30, count 0 2006.173.04:31:37.84#ibcon#about to read 3, iclass 30, count 0 2006.173.04:31:37.86#ibcon#read 3, iclass 30, count 0 2006.173.04:31:37.86#ibcon#about to read 4, iclass 30, count 0 2006.173.04:31:37.86#ibcon#read 4, iclass 30, count 0 2006.173.04:31:37.86#ibcon#about to read 5, iclass 30, count 0 2006.173.04:31:37.86#ibcon#read 5, iclass 30, count 0 2006.173.04:31:37.86#ibcon#about to read 6, iclass 30, count 0 2006.173.04:31:37.86#ibcon#read 6, iclass 30, count 0 2006.173.04:31:37.86#ibcon#end of sib2, iclass 30, count 0 2006.173.04:31:37.86#ibcon#*mode == 0, iclass 30, count 0 2006.173.04:31:37.86#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.04:31:37.86#ibcon#[25=USB\r\n] 2006.173.04:31:37.86#ibcon#*before write, iclass 30, count 0 2006.173.04:31:37.86#ibcon#enter sib2, iclass 30, count 0 2006.173.04:31:37.86#ibcon#flushed, iclass 30, count 0 2006.173.04:31:37.86#ibcon#about to write, iclass 30, count 0 2006.173.04:31:37.86#ibcon#wrote, iclass 30, count 0 2006.173.04:31:37.86#ibcon#about to read 3, iclass 30, count 0 2006.173.04:31:37.89#ibcon#read 3, iclass 30, count 0 2006.173.04:31:37.89#ibcon#about to read 4, iclass 30, count 0 2006.173.04:31:37.89#ibcon#read 4, iclass 30, count 0 2006.173.04:31:37.89#ibcon#about to read 5, iclass 30, count 0 2006.173.04:31:37.89#ibcon#read 5, iclass 30, count 0 2006.173.04:31:37.89#ibcon#about to read 6, iclass 30, count 0 2006.173.04:31:37.89#ibcon#read 6, iclass 30, count 0 2006.173.04:31:37.89#ibcon#end of sib2, iclass 30, count 0 2006.173.04:31:37.89#ibcon#*after write, iclass 30, count 0 2006.173.04:31:37.89#ibcon#*before return 0, iclass 30, count 0 2006.173.04:31:37.89#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.04:31:37.89#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.04:31:37.89#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.04:31:37.89#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.04:31:37.89$vck44/valo=8,884.99 2006.173.04:31:37.89#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.04:31:37.89#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.04:31:37.89#ibcon#ireg 17 cls_cnt 0 2006.173.04:31:37.89#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.04:31:37.89#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.04:31:37.89#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.04:31:37.89#ibcon#enter wrdev, iclass 32, count 0 2006.173.04:31:37.89#ibcon#first serial, iclass 32, count 0 2006.173.04:31:37.89#ibcon#enter sib2, iclass 32, count 0 2006.173.04:31:37.89#ibcon#flushed, iclass 32, count 0 2006.173.04:31:37.89#ibcon#about to write, iclass 32, count 0 2006.173.04:31:37.89#ibcon#wrote, iclass 32, count 0 2006.173.04:31:37.89#ibcon#about to read 3, iclass 32, count 0 2006.173.04:31:37.91#ibcon#read 3, iclass 32, count 0 2006.173.04:31:37.91#ibcon#about to read 4, iclass 32, count 0 2006.173.04:31:37.91#ibcon#read 4, iclass 32, count 0 2006.173.04:31:37.91#ibcon#about to read 5, iclass 32, count 0 2006.173.04:31:37.91#ibcon#read 5, iclass 32, count 0 2006.173.04:31:37.91#ibcon#about to read 6, iclass 32, count 0 2006.173.04:31:37.91#ibcon#read 6, iclass 32, count 0 2006.173.04:31:37.91#ibcon#end of sib2, iclass 32, count 0 2006.173.04:31:37.91#ibcon#*mode == 0, iclass 32, count 0 2006.173.04:31:37.91#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.04:31:37.91#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.04:31:37.91#ibcon#*before write, iclass 32, count 0 2006.173.04:31:37.91#ibcon#enter sib2, iclass 32, count 0 2006.173.04:31:37.91#ibcon#flushed, iclass 32, count 0 2006.173.04:31:37.91#ibcon#about to write, iclass 32, count 0 2006.173.04:31:37.91#ibcon#wrote, iclass 32, count 0 2006.173.04:31:37.91#ibcon#about to read 3, iclass 32, count 0 2006.173.04:31:37.95#ibcon#read 3, iclass 32, count 0 2006.173.04:31:37.95#ibcon#about to read 4, iclass 32, count 0 2006.173.04:31:37.95#ibcon#read 4, iclass 32, count 0 2006.173.04:31:37.95#ibcon#about to read 5, iclass 32, count 0 2006.173.04:31:37.95#ibcon#read 5, iclass 32, count 0 2006.173.04:31:37.95#ibcon#about to read 6, iclass 32, count 0 2006.173.04:31:37.95#ibcon#read 6, iclass 32, count 0 2006.173.04:31:37.95#ibcon#end of sib2, iclass 32, count 0 2006.173.04:31:37.95#ibcon#*after write, iclass 32, count 0 2006.173.04:31:37.95#ibcon#*before return 0, iclass 32, count 0 2006.173.04:31:37.95#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.04:31:37.95#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.04:31:37.95#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.04:31:37.95#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.04:31:37.95$vck44/va=8,4 2006.173.04:31:37.95#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.04:31:37.95#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.04:31:37.95#ibcon#ireg 11 cls_cnt 2 2006.173.04:31:37.95#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.04:31:38.01#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.04:31:38.01#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.04:31:38.01#ibcon#enter wrdev, iclass 34, count 2 2006.173.04:31:38.01#ibcon#first serial, iclass 34, count 2 2006.173.04:31:38.01#ibcon#enter sib2, iclass 34, count 2 2006.173.04:31:38.01#ibcon#flushed, iclass 34, count 2 2006.173.04:31:38.01#ibcon#about to write, iclass 34, count 2 2006.173.04:31:38.01#ibcon#wrote, iclass 34, count 2 2006.173.04:31:38.01#ibcon#about to read 3, iclass 34, count 2 2006.173.04:31:38.03#ibcon#read 3, iclass 34, count 2 2006.173.04:31:38.03#ibcon#about to read 4, iclass 34, count 2 2006.173.04:31:38.03#ibcon#read 4, iclass 34, count 2 2006.173.04:31:38.03#ibcon#about to read 5, iclass 34, count 2 2006.173.04:31:38.03#ibcon#read 5, iclass 34, count 2 2006.173.04:31:38.03#ibcon#about to read 6, iclass 34, count 2 2006.173.04:31:38.03#ibcon#read 6, iclass 34, count 2 2006.173.04:31:38.03#ibcon#end of sib2, iclass 34, count 2 2006.173.04:31:38.03#ibcon#*mode == 0, iclass 34, count 2 2006.173.04:31:38.03#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.04:31:38.03#ibcon#[25=AT08-04\r\n] 2006.173.04:31:38.03#ibcon#*before write, iclass 34, count 2 2006.173.04:31:38.03#ibcon#enter sib2, iclass 34, count 2 2006.173.04:31:38.03#ibcon#flushed, iclass 34, count 2 2006.173.04:31:38.03#ibcon#about to write, iclass 34, count 2 2006.173.04:31:38.03#ibcon#wrote, iclass 34, count 2 2006.173.04:31:38.03#ibcon#about to read 3, iclass 34, count 2 2006.173.04:31:38.06#ibcon#read 3, iclass 34, count 2 2006.173.04:31:38.06#ibcon#about to read 4, iclass 34, count 2 2006.173.04:31:38.06#ibcon#read 4, iclass 34, count 2 2006.173.04:31:38.06#ibcon#about to read 5, iclass 34, count 2 2006.173.04:31:38.06#ibcon#read 5, iclass 34, count 2 2006.173.04:31:38.06#ibcon#about to read 6, iclass 34, count 2 2006.173.04:31:38.06#ibcon#read 6, iclass 34, count 2 2006.173.04:31:38.06#ibcon#end of sib2, iclass 34, count 2 2006.173.04:31:38.06#ibcon#*after write, iclass 34, count 2 2006.173.04:31:38.06#ibcon#*before return 0, iclass 34, count 2 2006.173.04:31:38.06#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.04:31:38.06#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.04:31:38.06#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.04:31:38.06#ibcon#ireg 7 cls_cnt 0 2006.173.04:31:38.06#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.04:31:38.18#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.04:31:38.18#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.04:31:38.18#ibcon#enter wrdev, iclass 34, count 0 2006.173.04:31:38.18#ibcon#first serial, iclass 34, count 0 2006.173.04:31:38.18#ibcon#enter sib2, iclass 34, count 0 2006.173.04:31:38.18#ibcon#flushed, iclass 34, count 0 2006.173.04:31:38.18#ibcon#about to write, iclass 34, count 0 2006.173.04:31:38.18#ibcon#wrote, iclass 34, count 0 2006.173.04:31:38.18#ibcon#about to read 3, iclass 34, count 0 2006.173.04:31:38.20#ibcon#read 3, iclass 34, count 0 2006.173.04:31:38.20#ibcon#about to read 4, iclass 34, count 0 2006.173.04:31:38.20#ibcon#read 4, iclass 34, count 0 2006.173.04:31:38.20#ibcon#about to read 5, iclass 34, count 0 2006.173.04:31:38.20#ibcon#read 5, iclass 34, count 0 2006.173.04:31:38.20#ibcon#about to read 6, iclass 34, count 0 2006.173.04:31:38.20#ibcon#read 6, iclass 34, count 0 2006.173.04:31:38.20#ibcon#end of sib2, iclass 34, count 0 2006.173.04:31:38.20#ibcon#*mode == 0, iclass 34, count 0 2006.173.04:31:38.20#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.04:31:38.20#ibcon#[25=USB\r\n] 2006.173.04:31:38.20#ibcon#*before write, iclass 34, count 0 2006.173.04:31:38.20#ibcon#enter sib2, iclass 34, count 0 2006.173.04:31:38.20#ibcon#flushed, iclass 34, count 0 2006.173.04:31:38.20#ibcon#about to write, iclass 34, count 0 2006.173.04:31:38.20#ibcon#wrote, iclass 34, count 0 2006.173.04:31:38.20#ibcon#about to read 3, iclass 34, count 0 2006.173.04:31:38.23#ibcon#read 3, iclass 34, count 0 2006.173.04:31:38.23#ibcon#about to read 4, iclass 34, count 0 2006.173.04:31:38.23#ibcon#read 4, iclass 34, count 0 2006.173.04:31:38.23#ibcon#about to read 5, iclass 34, count 0 2006.173.04:31:38.23#ibcon#read 5, iclass 34, count 0 2006.173.04:31:38.23#ibcon#about to read 6, iclass 34, count 0 2006.173.04:31:38.23#ibcon#read 6, iclass 34, count 0 2006.173.04:31:38.23#ibcon#end of sib2, iclass 34, count 0 2006.173.04:31:38.23#ibcon#*after write, iclass 34, count 0 2006.173.04:31:38.23#ibcon#*before return 0, iclass 34, count 0 2006.173.04:31:38.23#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.04:31:38.23#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.04:31:38.23#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.04:31:38.23#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.04:31:38.23$vck44/vblo=1,629.99 2006.173.04:31:38.23#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.04:31:38.23#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.04:31:38.23#ibcon#ireg 17 cls_cnt 0 2006.173.04:31:38.23#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.04:31:38.23#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.04:31:38.23#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.04:31:38.23#ibcon#enter wrdev, iclass 36, count 0 2006.173.04:31:38.23#ibcon#first serial, iclass 36, count 0 2006.173.04:31:38.23#ibcon#enter sib2, iclass 36, count 0 2006.173.04:31:38.23#ibcon#flushed, iclass 36, count 0 2006.173.04:31:38.23#ibcon#about to write, iclass 36, count 0 2006.173.04:31:38.23#ibcon#wrote, iclass 36, count 0 2006.173.04:31:38.23#ibcon#about to read 3, iclass 36, count 0 2006.173.04:31:38.25#ibcon#read 3, iclass 36, count 0 2006.173.04:31:38.25#ibcon#about to read 4, iclass 36, count 0 2006.173.04:31:38.25#ibcon#read 4, iclass 36, count 0 2006.173.04:31:38.25#ibcon#about to read 5, iclass 36, count 0 2006.173.04:31:38.25#ibcon#read 5, iclass 36, count 0 2006.173.04:31:38.25#ibcon#about to read 6, iclass 36, count 0 2006.173.04:31:38.25#ibcon#read 6, iclass 36, count 0 2006.173.04:31:38.25#ibcon#end of sib2, iclass 36, count 0 2006.173.04:31:38.25#ibcon#*mode == 0, iclass 36, count 0 2006.173.04:31:38.25#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.04:31:38.25#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.04:31:38.25#ibcon#*before write, iclass 36, count 0 2006.173.04:31:38.25#ibcon#enter sib2, iclass 36, count 0 2006.173.04:31:38.25#ibcon#flushed, iclass 36, count 0 2006.173.04:31:38.25#ibcon#about to write, iclass 36, count 0 2006.173.04:31:38.25#ibcon#wrote, iclass 36, count 0 2006.173.04:31:38.25#ibcon#about to read 3, iclass 36, count 0 2006.173.04:31:38.29#ibcon#read 3, iclass 36, count 0 2006.173.04:31:38.29#ibcon#about to read 4, iclass 36, count 0 2006.173.04:31:38.29#ibcon#read 4, iclass 36, count 0 2006.173.04:31:38.29#ibcon#about to read 5, iclass 36, count 0 2006.173.04:31:38.29#ibcon#read 5, iclass 36, count 0 2006.173.04:31:38.29#ibcon#about to read 6, iclass 36, count 0 2006.173.04:31:38.29#ibcon#read 6, iclass 36, count 0 2006.173.04:31:38.29#ibcon#end of sib2, iclass 36, count 0 2006.173.04:31:38.29#ibcon#*after write, iclass 36, count 0 2006.173.04:31:38.29#ibcon#*before return 0, iclass 36, count 0 2006.173.04:31:38.29#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.04:31:38.29#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.04:31:38.29#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.04:31:38.29#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.04:31:38.29$vck44/vb=1,4 2006.173.04:31:38.29#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.04:31:38.29#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.04:31:38.29#ibcon#ireg 11 cls_cnt 2 2006.173.04:31:38.29#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.04:31:38.29#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.04:31:38.29#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.04:31:38.29#ibcon#enter wrdev, iclass 38, count 2 2006.173.04:31:38.29#ibcon#first serial, iclass 38, count 2 2006.173.04:31:38.29#ibcon#enter sib2, iclass 38, count 2 2006.173.04:31:38.29#ibcon#flushed, iclass 38, count 2 2006.173.04:31:38.29#ibcon#about to write, iclass 38, count 2 2006.173.04:31:38.29#ibcon#wrote, iclass 38, count 2 2006.173.04:31:38.29#ibcon#about to read 3, iclass 38, count 2 2006.173.04:31:38.31#ibcon#read 3, iclass 38, count 2 2006.173.04:31:38.31#ibcon#about to read 4, iclass 38, count 2 2006.173.04:31:38.31#ibcon#read 4, iclass 38, count 2 2006.173.04:31:38.31#ibcon#about to read 5, iclass 38, count 2 2006.173.04:31:38.31#ibcon#read 5, iclass 38, count 2 2006.173.04:31:38.31#ibcon#about to read 6, iclass 38, count 2 2006.173.04:31:38.31#ibcon#read 6, iclass 38, count 2 2006.173.04:31:38.31#ibcon#end of sib2, iclass 38, count 2 2006.173.04:31:38.31#ibcon#*mode == 0, iclass 38, count 2 2006.173.04:31:38.31#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.04:31:38.31#ibcon#[27=AT01-04\r\n] 2006.173.04:31:38.31#ibcon#*before write, iclass 38, count 2 2006.173.04:31:38.31#ibcon#enter sib2, iclass 38, count 2 2006.173.04:31:38.31#ibcon#flushed, iclass 38, count 2 2006.173.04:31:38.31#ibcon#about to write, iclass 38, count 2 2006.173.04:31:38.31#ibcon#wrote, iclass 38, count 2 2006.173.04:31:38.31#ibcon#about to read 3, iclass 38, count 2 2006.173.04:31:38.34#ibcon#read 3, iclass 38, count 2 2006.173.04:31:38.34#ibcon#about to read 4, iclass 38, count 2 2006.173.04:31:38.34#ibcon#read 4, iclass 38, count 2 2006.173.04:31:38.34#ibcon#about to read 5, iclass 38, count 2 2006.173.04:31:38.34#ibcon#read 5, iclass 38, count 2 2006.173.04:31:38.34#ibcon#about to read 6, iclass 38, count 2 2006.173.04:31:38.34#ibcon#read 6, iclass 38, count 2 2006.173.04:31:38.34#ibcon#end of sib2, iclass 38, count 2 2006.173.04:31:38.34#ibcon#*after write, iclass 38, count 2 2006.173.04:31:38.34#ibcon#*before return 0, iclass 38, count 2 2006.173.04:31:38.34#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.04:31:38.34#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.04:31:38.34#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.04:31:38.34#ibcon#ireg 7 cls_cnt 0 2006.173.04:31:38.34#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.04:31:38.46#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.04:31:38.46#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.04:31:38.46#ibcon#enter wrdev, iclass 38, count 0 2006.173.04:31:38.46#ibcon#first serial, iclass 38, count 0 2006.173.04:31:38.46#ibcon#enter sib2, iclass 38, count 0 2006.173.04:31:38.46#ibcon#flushed, iclass 38, count 0 2006.173.04:31:38.46#ibcon#about to write, iclass 38, count 0 2006.173.04:31:38.46#ibcon#wrote, iclass 38, count 0 2006.173.04:31:38.46#ibcon#about to read 3, iclass 38, count 0 2006.173.04:31:38.48#ibcon#read 3, iclass 38, count 0 2006.173.04:31:38.48#ibcon#about to read 4, iclass 38, count 0 2006.173.04:31:38.48#ibcon#read 4, iclass 38, count 0 2006.173.04:31:38.48#ibcon#about to read 5, iclass 38, count 0 2006.173.04:31:38.48#ibcon#read 5, iclass 38, count 0 2006.173.04:31:38.48#ibcon#about to read 6, iclass 38, count 0 2006.173.04:31:38.48#ibcon#read 6, iclass 38, count 0 2006.173.04:31:38.48#ibcon#end of sib2, iclass 38, count 0 2006.173.04:31:38.48#ibcon#*mode == 0, iclass 38, count 0 2006.173.04:31:38.48#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.04:31:38.48#ibcon#[27=USB\r\n] 2006.173.04:31:38.48#ibcon#*before write, iclass 38, count 0 2006.173.04:31:38.48#ibcon#enter sib2, iclass 38, count 0 2006.173.04:31:38.48#ibcon#flushed, iclass 38, count 0 2006.173.04:31:38.48#ibcon#about to write, iclass 38, count 0 2006.173.04:31:38.48#ibcon#wrote, iclass 38, count 0 2006.173.04:31:38.48#ibcon#about to read 3, iclass 38, count 0 2006.173.04:31:38.51#ibcon#read 3, iclass 38, count 0 2006.173.04:31:38.51#ibcon#about to read 4, iclass 38, count 0 2006.173.04:31:38.51#ibcon#read 4, iclass 38, count 0 2006.173.04:31:38.51#ibcon#about to read 5, iclass 38, count 0 2006.173.04:31:38.51#ibcon#read 5, iclass 38, count 0 2006.173.04:31:38.51#ibcon#about to read 6, iclass 38, count 0 2006.173.04:31:38.51#ibcon#read 6, iclass 38, count 0 2006.173.04:31:38.51#ibcon#end of sib2, iclass 38, count 0 2006.173.04:31:38.51#ibcon#*after write, iclass 38, count 0 2006.173.04:31:38.51#ibcon#*before return 0, iclass 38, count 0 2006.173.04:31:38.51#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.04:31:38.51#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.04:31:38.51#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.04:31:38.51#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.04:31:38.51$vck44/vblo=2,634.99 2006.173.04:31:38.51#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.04:31:38.51#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.04:31:38.51#ibcon#ireg 17 cls_cnt 0 2006.173.04:31:38.51#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.04:31:38.51#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.04:31:38.51#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.04:31:38.51#ibcon#enter wrdev, iclass 40, count 0 2006.173.04:31:38.51#ibcon#first serial, iclass 40, count 0 2006.173.04:31:38.51#ibcon#enter sib2, iclass 40, count 0 2006.173.04:31:38.51#ibcon#flushed, iclass 40, count 0 2006.173.04:31:38.51#ibcon#about to write, iclass 40, count 0 2006.173.04:31:38.51#ibcon#wrote, iclass 40, count 0 2006.173.04:31:38.51#ibcon#about to read 3, iclass 40, count 0 2006.173.04:31:38.53#ibcon#read 3, iclass 40, count 0 2006.173.04:31:38.53#ibcon#about to read 4, iclass 40, count 0 2006.173.04:31:38.53#ibcon#read 4, iclass 40, count 0 2006.173.04:31:38.53#ibcon#about to read 5, iclass 40, count 0 2006.173.04:31:38.53#ibcon#read 5, iclass 40, count 0 2006.173.04:31:38.53#ibcon#about to read 6, iclass 40, count 0 2006.173.04:31:38.53#ibcon#read 6, iclass 40, count 0 2006.173.04:31:38.53#ibcon#end of sib2, iclass 40, count 0 2006.173.04:31:38.53#ibcon#*mode == 0, iclass 40, count 0 2006.173.04:31:38.53#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.04:31:38.53#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.04:31:38.53#ibcon#*before write, iclass 40, count 0 2006.173.04:31:38.53#ibcon#enter sib2, iclass 40, count 0 2006.173.04:31:38.53#ibcon#flushed, iclass 40, count 0 2006.173.04:31:38.53#ibcon#about to write, iclass 40, count 0 2006.173.04:31:38.53#ibcon#wrote, iclass 40, count 0 2006.173.04:31:38.53#ibcon#about to read 3, iclass 40, count 0 2006.173.04:31:38.57#ibcon#read 3, iclass 40, count 0 2006.173.04:31:38.57#ibcon#about to read 4, iclass 40, count 0 2006.173.04:31:38.57#ibcon#read 4, iclass 40, count 0 2006.173.04:31:38.57#ibcon#about to read 5, iclass 40, count 0 2006.173.04:31:38.57#ibcon#read 5, iclass 40, count 0 2006.173.04:31:38.57#ibcon#about to read 6, iclass 40, count 0 2006.173.04:31:38.57#ibcon#read 6, iclass 40, count 0 2006.173.04:31:38.57#ibcon#end of sib2, iclass 40, count 0 2006.173.04:31:38.57#ibcon#*after write, iclass 40, count 0 2006.173.04:31:38.57#ibcon#*before return 0, iclass 40, count 0 2006.173.04:31:38.57#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.04:31:38.57#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.04:31:38.57#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.04:31:38.57#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.04:31:38.57$vck44/vb=2,4 2006.173.04:31:38.57#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.04:31:38.57#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.04:31:38.57#ibcon#ireg 11 cls_cnt 2 2006.173.04:31:38.57#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.04:31:38.63#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.04:31:38.63#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.04:31:38.63#ibcon#enter wrdev, iclass 4, count 2 2006.173.04:31:38.63#ibcon#first serial, iclass 4, count 2 2006.173.04:31:38.63#ibcon#enter sib2, iclass 4, count 2 2006.173.04:31:38.63#ibcon#flushed, iclass 4, count 2 2006.173.04:31:38.63#ibcon#about to write, iclass 4, count 2 2006.173.04:31:38.63#ibcon#wrote, iclass 4, count 2 2006.173.04:31:38.63#ibcon#about to read 3, iclass 4, count 2 2006.173.04:31:38.65#ibcon#read 3, iclass 4, count 2 2006.173.04:31:38.65#ibcon#about to read 4, iclass 4, count 2 2006.173.04:31:38.65#ibcon#read 4, iclass 4, count 2 2006.173.04:31:38.65#ibcon#about to read 5, iclass 4, count 2 2006.173.04:31:38.65#ibcon#read 5, iclass 4, count 2 2006.173.04:31:38.65#ibcon#about to read 6, iclass 4, count 2 2006.173.04:31:38.65#ibcon#read 6, iclass 4, count 2 2006.173.04:31:38.65#ibcon#end of sib2, iclass 4, count 2 2006.173.04:31:38.65#ibcon#*mode == 0, iclass 4, count 2 2006.173.04:31:38.65#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.04:31:38.65#ibcon#[27=AT02-04\r\n] 2006.173.04:31:38.65#ibcon#*before write, iclass 4, count 2 2006.173.04:31:38.65#ibcon#enter sib2, iclass 4, count 2 2006.173.04:31:38.65#ibcon#flushed, iclass 4, count 2 2006.173.04:31:38.65#ibcon#about to write, iclass 4, count 2 2006.173.04:31:38.65#ibcon#wrote, iclass 4, count 2 2006.173.04:31:38.65#ibcon#about to read 3, iclass 4, count 2 2006.173.04:31:38.68#ibcon#read 3, iclass 4, count 2 2006.173.04:31:38.68#ibcon#about to read 4, iclass 4, count 2 2006.173.04:31:38.68#ibcon#read 4, iclass 4, count 2 2006.173.04:31:38.68#ibcon#about to read 5, iclass 4, count 2 2006.173.04:31:38.68#ibcon#read 5, iclass 4, count 2 2006.173.04:31:38.68#ibcon#about to read 6, iclass 4, count 2 2006.173.04:31:38.68#ibcon#read 6, iclass 4, count 2 2006.173.04:31:38.68#ibcon#end of sib2, iclass 4, count 2 2006.173.04:31:38.68#ibcon#*after write, iclass 4, count 2 2006.173.04:31:38.68#ibcon#*before return 0, iclass 4, count 2 2006.173.04:31:38.68#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.04:31:38.68#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.04:31:38.68#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.04:31:38.68#ibcon#ireg 7 cls_cnt 0 2006.173.04:31:38.68#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.04:31:38.80#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.04:31:38.80#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.04:31:38.80#ibcon#enter wrdev, iclass 4, count 0 2006.173.04:31:38.80#ibcon#first serial, iclass 4, count 0 2006.173.04:31:38.80#ibcon#enter sib2, iclass 4, count 0 2006.173.04:31:38.80#ibcon#flushed, iclass 4, count 0 2006.173.04:31:38.80#ibcon#about to write, iclass 4, count 0 2006.173.04:31:38.80#ibcon#wrote, iclass 4, count 0 2006.173.04:31:38.80#ibcon#about to read 3, iclass 4, count 0 2006.173.04:31:38.82#ibcon#read 3, iclass 4, count 0 2006.173.04:31:38.82#ibcon#about to read 4, iclass 4, count 0 2006.173.04:31:38.82#ibcon#read 4, iclass 4, count 0 2006.173.04:31:38.82#ibcon#about to read 5, iclass 4, count 0 2006.173.04:31:38.82#ibcon#read 5, iclass 4, count 0 2006.173.04:31:38.82#ibcon#about to read 6, iclass 4, count 0 2006.173.04:31:38.82#ibcon#read 6, iclass 4, count 0 2006.173.04:31:38.82#ibcon#end of sib2, iclass 4, count 0 2006.173.04:31:38.82#ibcon#*mode == 0, iclass 4, count 0 2006.173.04:31:38.82#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.04:31:38.82#ibcon#[27=USB\r\n] 2006.173.04:31:38.82#ibcon#*before write, iclass 4, count 0 2006.173.04:31:38.82#ibcon#enter sib2, iclass 4, count 0 2006.173.04:31:38.82#ibcon#flushed, iclass 4, count 0 2006.173.04:31:38.82#ibcon#about to write, iclass 4, count 0 2006.173.04:31:38.82#ibcon#wrote, iclass 4, count 0 2006.173.04:31:38.82#ibcon#about to read 3, iclass 4, count 0 2006.173.04:31:38.85#ibcon#read 3, iclass 4, count 0 2006.173.04:31:38.85#ibcon#about to read 4, iclass 4, count 0 2006.173.04:31:38.85#ibcon#read 4, iclass 4, count 0 2006.173.04:31:38.85#ibcon#about to read 5, iclass 4, count 0 2006.173.04:31:38.85#ibcon#read 5, iclass 4, count 0 2006.173.04:31:38.85#ibcon#about to read 6, iclass 4, count 0 2006.173.04:31:38.85#ibcon#read 6, iclass 4, count 0 2006.173.04:31:38.85#ibcon#end of sib2, iclass 4, count 0 2006.173.04:31:38.85#ibcon#*after write, iclass 4, count 0 2006.173.04:31:38.85#ibcon#*before return 0, iclass 4, count 0 2006.173.04:31:38.85#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.04:31:38.85#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.04:31:38.85#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.04:31:38.85#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.04:31:38.85$vck44/vblo=3,649.99 2006.173.04:31:38.85#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.04:31:38.85#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.04:31:38.85#ibcon#ireg 17 cls_cnt 0 2006.173.04:31:38.85#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.04:31:38.85#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.04:31:38.85#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.04:31:38.85#ibcon#enter wrdev, iclass 6, count 0 2006.173.04:31:38.85#ibcon#first serial, iclass 6, count 0 2006.173.04:31:38.85#ibcon#enter sib2, iclass 6, count 0 2006.173.04:31:38.85#ibcon#flushed, iclass 6, count 0 2006.173.04:31:38.85#ibcon#about to write, iclass 6, count 0 2006.173.04:31:38.85#ibcon#wrote, iclass 6, count 0 2006.173.04:31:38.85#ibcon#about to read 3, iclass 6, count 0 2006.173.04:31:38.87#ibcon#read 3, iclass 6, count 0 2006.173.04:31:38.87#ibcon#about to read 4, iclass 6, count 0 2006.173.04:31:38.87#ibcon#read 4, iclass 6, count 0 2006.173.04:31:38.87#ibcon#about to read 5, iclass 6, count 0 2006.173.04:31:38.87#ibcon#read 5, iclass 6, count 0 2006.173.04:31:38.87#ibcon#about to read 6, iclass 6, count 0 2006.173.04:31:38.87#ibcon#read 6, iclass 6, count 0 2006.173.04:31:38.87#ibcon#end of sib2, iclass 6, count 0 2006.173.04:31:38.87#ibcon#*mode == 0, iclass 6, count 0 2006.173.04:31:38.87#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.04:31:38.87#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.04:31:38.87#ibcon#*before write, iclass 6, count 0 2006.173.04:31:38.87#ibcon#enter sib2, iclass 6, count 0 2006.173.04:31:38.87#ibcon#flushed, iclass 6, count 0 2006.173.04:31:38.87#ibcon#about to write, iclass 6, count 0 2006.173.04:31:38.87#ibcon#wrote, iclass 6, count 0 2006.173.04:31:38.87#ibcon#about to read 3, iclass 6, count 0 2006.173.04:31:38.91#ibcon#read 3, iclass 6, count 0 2006.173.04:31:38.91#ibcon#about to read 4, iclass 6, count 0 2006.173.04:31:38.91#ibcon#read 4, iclass 6, count 0 2006.173.04:31:38.91#ibcon#about to read 5, iclass 6, count 0 2006.173.04:31:38.91#ibcon#read 5, iclass 6, count 0 2006.173.04:31:38.91#ibcon#about to read 6, iclass 6, count 0 2006.173.04:31:38.91#ibcon#read 6, iclass 6, count 0 2006.173.04:31:38.91#ibcon#end of sib2, iclass 6, count 0 2006.173.04:31:38.91#ibcon#*after write, iclass 6, count 0 2006.173.04:31:38.91#ibcon#*before return 0, iclass 6, count 0 2006.173.04:31:38.91#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.04:31:38.91#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.04:31:38.91#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.04:31:38.91#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.04:31:38.91$vck44/vb=3,4 2006.173.04:31:38.91#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.04:31:38.91#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.04:31:38.91#ibcon#ireg 11 cls_cnt 2 2006.173.04:31:38.91#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.04:31:38.97#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.04:31:38.97#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.04:31:38.97#ibcon#enter wrdev, iclass 10, count 2 2006.173.04:31:38.97#ibcon#first serial, iclass 10, count 2 2006.173.04:31:38.97#ibcon#enter sib2, iclass 10, count 2 2006.173.04:31:38.97#ibcon#flushed, iclass 10, count 2 2006.173.04:31:38.97#ibcon#about to write, iclass 10, count 2 2006.173.04:31:38.97#ibcon#wrote, iclass 10, count 2 2006.173.04:31:38.97#ibcon#about to read 3, iclass 10, count 2 2006.173.04:31:38.99#ibcon#read 3, iclass 10, count 2 2006.173.04:31:38.99#ibcon#about to read 4, iclass 10, count 2 2006.173.04:31:38.99#ibcon#read 4, iclass 10, count 2 2006.173.04:31:38.99#ibcon#about to read 5, iclass 10, count 2 2006.173.04:31:38.99#ibcon#read 5, iclass 10, count 2 2006.173.04:31:38.99#ibcon#about to read 6, iclass 10, count 2 2006.173.04:31:38.99#ibcon#read 6, iclass 10, count 2 2006.173.04:31:38.99#ibcon#end of sib2, iclass 10, count 2 2006.173.04:31:38.99#ibcon#*mode == 0, iclass 10, count 2 2006.173.04:31:38.99#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.04:31:38.99#ibcon#[27=AT03-04\r\n] 2006.173.04:31:38.99#ibcon#*before write, iclass 10, count 2 2006.173.04:31:38.99#ibcon#enter sib2, iclass 10, count 2 2006.173.04:31:38.99#ibcon#flushed, iclass 10, count 2 2006.173.04:31:38.99#ibcon#about to write, iclass 10, count 2 2006.173.04:31:38.99#ibcon#wrote, iclass 10, count 2 2006.173.04:31:38.99#ibcon#about to read 3, iclass 10, count 2 2006.173.04:31:39.02#ibcon#read 3, iclass 10, count 2 2006.173.04:31:39.02#ibcon#about to read 4, iclass 10, count 2 2006.173.04:31:39.02#ibcon#read 4, iclass 10, count 2 2006.173.04:31:39.02#ibcon#about to read 5, iclass 10, count 2 2006.173.04:31:39.02#ibcon#read 5, iclass 10, count 2 2006.173.04:31:39.02#ibcon#about to read 6, iclass 10, count 2 2006.173.04:31:39.02#ibcon#read 6, iclass 10, count 2 2006.173.04:31:39.02#ibcon#end of sib2, iclass 10, count 2 2006.173.04:31:39.02#ibcon#*after write, iclass 10, count 2 2006.173.04:31:39.02#ibcon#*before return 0, iclass 10, count 2 2006.173.04:31:39.02#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.04:31:39.02#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.04:31:39.02#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.04:31:39.02#ibcon#ireg 7 cls_cnt 0 2006.173.04:31:39.02#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.04:31:39.14#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.04:31:39.14#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.04:31:39.14#ibcon#enter wrdev, iclass 10, count 0 2006.173.04:31:39.14#ibcon#first serial, iclass 10, count 0 2006.173.04:31:39.14#ibcon#enter sib2, iclass 10, count 0 2006.173.04:31:39.14#ibcon#flushed, iclass 10, count 0 2006.173.04:31:39.14#ibcon#about to write, iclass 10, count 0 2006.173.04:31:39.14#ibcon#wrote, iclass 10, count 0 2006.173.04:31:39.14#ibcon#about to read 3, iclass 10, count 0 2006.173.04:31:39.16#ibcon#read 3, iclass 10, count 0 2006.173.04:31:39.16#ibcon#about to read 4, iclass 10, count 0 2006.173.04:31:39.16#ibcon#read 4, iclass 10, count 0 2006.173.04:31:39.16#ibcon#about to read 5, iclass 10, count 0 2006.173.04:31:39.16#ibcon#read 5, iclass 10, count 0 2006.173.04:31:39.16#ibcon#about to read 6, iclass 10, count 0 2006.173.04:31:39.16#ibcon#read 6, iclass 10, count 0 2006.173.04:31:39.16#ibcon#end of sib2, iclass 10, count 0 2006.173.04:31:39.16#ibcon#*mode == 0, iclass 10, count 0 2006.173.04:31:39.16#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.04:31:39.16#ibcon#[27=USB\r\n] 2006.173.04:31:39.16#ibcon#*before write, iclass 10, count 0 2006.173.04:31:39.16#ibcon#enter sib2, iclass 10, count 0 2006.173.04:31:39.16#ibcon#flushed, iclass 10, count 0 2006.173.04:31:39.16#ibcon#about to write, iclass 10, count 0 2006.173.04:31:39.16#ibcon#wrote, iclass 10, count 0 2006.173.04:31:39.16#ibcon#about to read 3, iclass 10, count 0 2006.173.04:31:39.19#ibcon#read 3, iclass 10, count 0 2006.173.04:31:39.19#ibcon#about to read 4, iclass 10, count 0 2006.173.04:31:39.19#ibcon#read 4, iclass 10, count 0 2006.173.04:31:39.19#ibcon#about to read 5, iclass 10, count 0 2006.173.04:31:39.19#ibcon#read 5, iclass 10, count 0 2006.173.04:31:39.19#ibcon#about to read 6, iclass 10, count 0 2006.173.04:31:39.19#ibcon#read 6, iclass 10, count 0 2006.173.04:31:39.19#ibcon#end of sib2, iclass 10, count 0 2006.173.04:31:39.19#ibcon#*after write, iclass 10, count 0 2006.173.04:31:39.19#ibcon#*before return 0, iclass 10, count 0 2006.173.04:31:39.19#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.04:31:39.19#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.04:31:39.19#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.04:31:39.19#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.04:31:39.19$vck44/vblo=4,679.99 2006.173.04:31:39.19#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.04:31:39.19#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.04:31:39.19#ibcon#ireg 17 cls_cnt 0 2006.173.04:31:39.19#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.04:31:39.19#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.04:31:39.19#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.04:31:39.19#ibcon#enter wrdev, iclass 12, count 0 2006.173.04:31:39.19#ibcon#first serial, iclass 12, count 0 2006.173.04:31:39.19#ibcon#enter sib2, iclass 12, count 0 2006.173.04:31:39.19#ibcon#flushed, iclass 12, count 0 2006.173.04:31:39.19#ibcon#about to write, iclass 12, count 0 2006.173.04:31:39.19#ibcon#wrote, iclass 12, count 0 2006.173.04:31:39.19#ibcon#about to read 3, iclass 12, count 0 2006.173.04:31:39.21#ibcon#read 3, iclass 12, count 0 2006.173.04:31:39.21#ibcon#about to read 4, iclass 12, count 0 2006.173.04:31:39.21#ibcon#read 4, iclass 12, count 0 2006.173.04:31:39.21#ibcon#about to read 5, iclass 12, count 0 2006.173.04:31:39.21#ibcon#read 5, iclass 12, count 0 2006.173.04:31:39.21#ibcon#about to read 6, iclass 12, count 0 2006.173.04:31:39.21#ibcon#read 6, iclass 12, count 0 2006.173.04:31:39.21#ibcon#end of sib2, iclass 12, count 0 2006.173.04:31:39.21#ibcon#*mode == 0, iclass 12, count 0 2006.173.04:31:39.21#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.04:31:39.21#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.04:31:39.21#ibcon#*before write, iclass 12, count 0 2006.173.04:31:39.21#ibcon#enter sib2, iclass 12, count 0 2006.173.04:31:39.21#ibcon#flushed, iclass 12, count 0 2006.173.04:31:39.21#ibcon#about to write, iclass 12, count 0 2006.173.04:31:39.21#ibcon#wrote, iclass 12, count 0 2006.173.04:31:39.21#ibcon#about to read 3, iclass 12, count 0 2006.173.04:31:39.25#ibcon#read 3, iclass 12, count 0 2006.173.04:31:39.25#ibcon#about to read 4, iclass 12, count 0 2006.173.04:31:39.25#ibcon#read 4, iclass 12, count 0 2006.173.04:31:39.25#ibcon#about to read 5, iclass 12, count 0 2006.173.04:31:39.25#ibcon#read 5, iclass 12, count 0 2006.173.04:31:39.25#ibcon#about to read 6, iclass 12, count 0 2006.173.04:31:39.25#ibcon#read 6, iclass 12, count 0 2006.173.04:31:39.25#ibcon#end of sib2, iclass 12, count 0 2006.173.04:31:39.25#ibcon#*after write, iclass 12, count 0 2006.173.04:31:39.25#ibcon#*before return 0, iclass 12, count 0 2006.173.04:31:39.25#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.04:31:39.25#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.04:31:39.25#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.04:31:39.25#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.04:31:39.25$vck44/vb=4,4 2006.173.04:31:39.25#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.04:31:39.25#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.04:31:39.25#ibcon#ireg 11 cls_cnt 2 2006.173.04:31:39.25#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.04:31:39.31#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.04:31:39.31#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.04:31:39.31#ibcon#enter wrdev, iclass 14, count 2 2006.173.04:31:39.31#ibcon#first serial, iclass 14, count 2 2006.173.04:31:39.31#ibcon#enter sib2, iclass 14, count 2 2006.173.04:31:39.31#ibcon#flushed, iclass 14, count 2 2006.173.04:31:39.31#ibcon#about to write, iclass 14, count 2 2006.173.04:31:39.31#ibcon#wrote, iclass 14, count 2 2006.173.04:31:39.31#ibcon#about to read 3, iclass 14, count 2 2006.173.04:31:39.33#ibcon#read 3, iclass 14, count 2 2006.173.04:31:39.33#ibcon#about to read 4, iclass 14, count 2 2006.173.04:31:39.33#ibcon#read 4, iclass 14, count 2 2006.173.04:31:39.33#ibcon#about to read 5, iclass 14, count 2 2006.173.04:31:39.33#ibcon#read 5, iclass 14, count 2 2006.173.04:31:39.33#ibcon#about to read 6, iclass 14, count 2 2006.173.04:31:39.33#ibcon#read 6, iclass 14, count 2 2006.173.04:31:39.33#ibcon#end of sib2, iclass 14, count 2 2006.173.04:31:39.33#ibcon#*mode == 0, iclass 14, count 2 2006.173.04:31:39.33#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.04:31:39.33#ibcon#[27=AT04-04\r\n] 2006.173.04:31:39.33#ibcon#*before write, iclass 14, count 2 2006.173.04:31:39.33#ibcon#enter sib2, iclass 14, count 2 2006.173.04:31:39.33#ibcon#flushed, iclass 14, count 2 2006.173.04:31:39.33#ibcon#about to write, iclass 14, count 2 2006.173.04:31:39.33#ibcon#wrote, iclass 14, count 2 2006.173.04:31:39.33#ibcon#about to read 3, iclass 14, count 2 2006.173.04:31:39.36#ibcon#read 3, iclass 14, count 2 2006.173.04:31:39.36#ibcon#about to read 4, iclass 14, count 2 2006.173.04:31:39.36#ibcon#read 4, iclass 14, count 2 2006.173.04:31:39.36#ibcon#about to read 5, iclass 14, count 2 2006.173.04:31:39.36#ibcon#read 5, iclass 14, count 2 2006.173.04:31:39.36#ibcon#about to read 6, iclass 14, count 2 2006.173.04:31:39.36#ibcon#read 6, iclass 14, count 2 2006.173.04:31:39.36#ibcon#end of sib2, iclass 14, count 2 2006.173.04:31:39.36#ibcon#*after write, iclass 14, count 2 2006.173.04:31:39.36#ibcon#*before return 0, iclass 14, count 2 2006.173.04:31:39.36#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.04:31:39.36#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.04:31:39.36#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.04:31:39.36#ibcon#ireg 7 cls_cnt 0 2006.173.04:31:39.36#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.04:31:39.48#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.04:31:39.48#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.04:31:39.48#ibcon#enter wrdev, iclass 14, count 0 2006.173.04:31:39.48#ibcon#first serial, iclass 14, count 0 2006.173.04:31:39.48#ibcon#enter sib2, iclass 14, count 0 2006.173.04:31:39.48#ibcon#flushed, iclass 14, count 0 2006.173.04:31:39.48#ibcon#about to write, iclass 14, count 0 2006.173.04:31:39.48#ibcon#wrote, iclass 14, count 0 2006.173.04:31:39.48#ibcon#about to read 3, iclass 14, count 0 2006.173.04:31:39.50#ibcon#read 3, iclass 14, count 0 2006.173.04:31:39.50#ibcon#about to read 4, iclass 14, count 0 2006.173.04:31:39.50#ibcon#read 4, iclass 14, count 0 2006.173.04:31:39.50#ibcon#about to read 5, iclass 14, count 0 2006.173.04:31:39.50#ibcon#read 5, iclass 14, count 0 2006.173.04:31:39.50#ibcon#about to read 6, iclass 14, count 0 2006.173.04:31:39.50#ibcon#read 6, iclass 14, count 0 2006.173.04:31:39.50#ibcon#end of sib2, iclass 14, count 0 2006.173.04:31:39.50#ibcon#*mode == 0, iclass 14, count 0 2006.173.04:31:39.50#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.04:31:39.50#ibcon#[27=USB\r\n] 2006.173.04:31:39.50#ibcon#*before write, iclass 14, count 0 2006.173.04:31:39.50#ibcon#enter sib2, iclass 14, count 0 2006.173.04:31:39.50#ibcon#flushed, iclass 14, count 0 2006.173.04:31:39.50#ibcon#about to write, iclass 14, count 0 2006.173.04:31:39.50#ibcon#wrote, iclass 14, count 0 2006.173.04:31:39.50#ibcon#about to read 3, iclass 14, count 0 2006.173.04:31:39.53#ibcon#read 3, iclass 14, count 0 2006.173.04:31:39.53#ibcon#about to read 4, iclass 14, count 0 2006.173.04:31:39.53#ibcon#read 4, iclass 14, count 0 2006.173.04:31:39.53#ibcon#about to read 5, iclass 14, count 0 2006.173.04:31:39.53#ibcon#read 5, iclass 14, count 0 2006.173.04:31:39.53#ibcon#about to read 6, iclass 14, count 0 2006.173.04:31:39.53#ibcon#read 6, iclass 14, count 0 2006.173.04:31:39.53#ibcon#end of sib2, iclass 14, count 0 2006.173.04:31:39.53#ibcon#*after write, iclass 14, count 0 2006.173.04:31:39.53#ibcon#*before return 0, iclass 14, count 0 2006.173.04:31:39.53#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.04:31:39.53#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.04:31:39.53#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.04:31:39.53#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.04:31:39.53$vck44/vblo=5,709.99 2006.173.04:31:39.53#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.04:31:39.53#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.04:31:39.53#ibcon#ireg 17 cls_cnt 0 2006.173.04:31:39.53#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.04:31:39.53#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.04:31:39.53#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.04:31:39.53#ibcon#enter wrdev, iclass 16, count 0 2006.173.04:31:39.53#ibcon#first serial, iclass 16, count 0 2006.173.04:31:39.53#ibcon#enter sib2, iclass 16, count 0 2006.173.04:31:39.53#ibcon#flushed, iclass 16, count 0 2006.173.04:31:39.53#ibcon#about to write, iclass 16, count 0 2006.173.04:31:39.53#ibcon#wrote, iclass 16, count 0 2006.173.04:31:39.53#ibcon#about to read 3, iclass 16, count 0 2006.173.04:31:39.55#ibcon#read 3, iclass 16, count 0 2006.173.04:31:39.55#ibcon#about to read 4, iclass 16, count 0 2006.173.04:31:39.55#ibcon#read 4, iclass 16, count 0 2006.173.04:31:39.55#ibcon#about to read 5, iclass 16, count 0 2006.173.04:31:39.55#ibcon#read 5, iclass 16, count 0 2006.173.04:31:39.55#ibcon#about to read 6, iclass 16, count 0 2006.173.04:31:39.55#ibcon#read 6, iclass 16, count 0 2006.173.04:31:39.55#ibcon#end of sib2, iclass 16, count 0 2006.173.04:31:39.55#ibcon#*mode == 0, iclass 16, count 0 2006.173.04:31:39.55#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.04:31:39.55#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.04:31:39.55#ibcon#*before write, iclass 16, count 0 2006.173.04:31:39.55#ibcon#enter sib2, iclass 16, count 0 2006.173.04:31:39.55#ibcon#flushed, iclass 16, count 0 2006.173.04:31:39.55#ibcon#about to write, iclass 16, count 0 2006.173.04:31:39.55#ibcon#wrote, iclass 16, count 0 2006.173.04:31:39.55#ibcon#about to read 3, iclass 16, count 0 2006.173.04:31:39.59#ibcon#read 3, iclass 16, count 0 2006.173.04:31:39.59#ibcon#about to read 4, iclass 16, count 0 2006.173.04:31:39.59#ibcon#read 4, iclass 16, count 0 2006.173.04:31:39.59#ibcon#about to read 5, iclass 16, count 0 2006.173.04:31:39.59#ibcon#read 5, iclass 16, count 0 2006.173.04:31:39.59#ibcon#about to read 6, iclass 16, count 0 2006.173.04:31:39.59#ibcon#read 6, iclass 16, count 0 2006.173.04:31:39.59#ibcon#end of sib2, iclass 16, count 0 2006.173.04:31:39.59#ibcon#*after write, iclass 16, count 0 2006.173.04:31:39.59#ibcon#*before return 0, iclass 16, count 0 2006.173.04:31:39.59#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.04:31:39.59#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.04:31:39.59#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.04:31:39.59#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.04:31:39.59$vck44/vb=5,4 2006.173.04:31:39.59#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.04:31:39.59#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.04:31:39.59#ibcon#ireg 11 cls_cnt 2 2006.173.04:31:39.59#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.04:31:39.65#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.04:31:39.65#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.04:31:39.65#ibcon#enter wrdev, iclass 18, count 2 2006.173.04:31:39.65#ibcon#first serial, iclass 18, count 2 2006.173.04:31:39.65#ibcon#enter sib2, iclass 18, count 2 2006.173.04:31:39.65#ibcon#flushed, iclass 18, count 2 2006.173.04:31:39.65#ibcon#about to write, iclass 18, count 2 2006.173.04:31:39.65#ibcon#wrote, iclass 18, count 2 2006.173.04:31:39.65#ibcon#about to read 3, iclass 18, count 2 2006.173.04:31:39.67#ibcon#read 3, iclass 18, count 2 2006.173.04:31:39.67#ibcon#about to read 4, iclass 18, count 2 2006.173.04:31:39.67#ibcon#read 4, iclass 18, count 2 2006.173.04:31:39.67#ibcon#about to read 5, iclass 18, count 2 2006.173.04:31:39.67#ibcon#read 5, iclass 18, count 2 2006.173.04:31:39.67#ibcon#about to read 6, iclass 18, count 2 2006.173.04:31:39.67#ibcon#read 6, iclass 18, count 2 2006.173.04:31:39.67#ibcon#end of sib2, iclass 18, count 2 2006.173.04:31:39.67#ibcon#*mode == 0, iclass 18, count 2 2006.173.04:31:39.67#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.04:31:39.67#ibcon#[27=AT05-04\r\n] 2006.173.04:31:39.67#ibcon#*before write, iclass 18, count 2 2006.173.04:31:39.67#ibcon#enter sib2, iclass 18, count 2 2006.173.04:31:39.67#ibcon#flushed, iclass 18, count 2 2006.173.04:31:39.67#ibcon#about to write, iclass 18, count 2 2006.173.04:31:39.67#ibcon#wrote, iclass 18, count 2 2006.173.04:31:39.67#ibcon#about to read 3, iclass 18, count 2 2006.173.04:31:39.70#ibcon#read 3, iclass 18, count 2 2006.173.04:31:39.70#ibcon#about to read 4, iclass 18, count 2 2006.173.04:31:39.70#ibcon#read 4, iclass 18, count 2 2006.173.04:31:39.70#ibcon#about to read 5, iclass 18, count 2 2006.173.04:31:39.70#ibcon#read 5, iclass 18, count 2 2006.173.04:31:39.70#ibcon#about to read 6, iclass 18, count 2 2006.173.04:31:39.70#ibcon#read 6, iclass 18, count 2 2006.173.04:31:39.70#ibcon#end of sib2, iclass 18, count 2 2006.173.04:31:39.70#ibcon#*after write, iclass 18, count 2 2006.173.04:31:39.70#ibcon#*before return 0, iclass 18, count 2 2006.173.04:31:39.70#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.04:31:39.70#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.04:31:39.70#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.04:31:39.70#ibcon#ireg 7 cls_cnt 0 2006.173.04:31:39.70#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.04:31:39.82#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.04:31:39.82#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.04:31:39.82#ibcon#enter wrdev, iclass 18, count 0 2006.173.04:31:39.82#ibcon#first serial, iclass 18, count 0 2006.173.04:31:39.82#ibcon#enter sib2, iclass 18, count 0 2006.173.04:31:39.82#ibcon#flushed, iclass 18, count 0 2006.173.04:31:39.82#ibcon#about to write, iclass 18, count 0 2006.173.04:31:39.82#ibcon#wrote, iclass 18, count 0 2006.173.04:31:39.82#ibcon#about to read 3, iclass 18, count 0 2006.173.04:31:39.84#ibcon#read 3, iclass 18, count 0 2006.173.04:31:39.84#ibcon#about to read 4, iclass 18, count 0 2006.173.04:31:39.84#ibcon#read 4, iclass 18, count 0 2006.173.04:31:39.84#ibcon#about to read 5, iclass 18, count 0 2006.173.04:31:39.84#ibcon#read 5, iclass 18, count 0 2006.173.04:31:39.84#ibcon#about to read 6, iclass 18, count 0 2006.173.04:31:39.84#ibcon#read 6, iclass 18, count 0 2006.173.04:31:39.84#ibcon#end of sib2, iclass 18, count 0 2006.173.04:31:39.84#ibcon#*mode == 0, iclass 18, count 0 2006.173.04:31:39.84#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.04:31:39.84#ibcon#[27=USB\r\n] 2006.173.04:31:39.84#ibcon#*before write, iclass 18, count 0 2006.173.04:31:39.84#ibcon#enter sib2, iclass 18, count 0 2006.173.04:31:39.84#ibcon#flushed, iclass 18, count 0 2006.173.04:31:39.84#ibcon#about to write, iclass 18, count 0 2006.173.04:31:39.84#ibcon#wrote, iclass 18, count 0 2006.173.04:31:39.84#ibcon#about to read 3, iclass 18, count 0 2006.173.04:31:39.87#ibcon#read 3, iclass 18, count 0 2006.173.04:31:39.87#ibcon#about to read 4, iclass 18, count 0 2006.173.04:31:39.87#ibcon#read 4, iclass 18, count 0 2006.173.04:31:39.87#ibcon#about to read 5, iclass 18, count 0 2006.173.04:31:39.87#ibcon#read 5, iclass 18, count 0 2006.173.04:31:39.87#ibcon#about to read 6, iclass 18, count 0 2006.173.04:31:39.87#ibcon#read 6, iclass 18, count 0 2006.173.04:31:39.87#ibcon#end of sib2, iclass 18, count 0 2006.173.04:31:39.87#ibcon#*after write, iclass 18, count 0 2006.173.04:31:39.87#ibcon#*before return 0, iclass 18, count 0 2006.173.04:31:39.87#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.04:31:39.87#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.04:31:39.87#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.04:31:39.87#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.04:31:39.87$vck44/vblo=6,719.99 2006.173.04:31:39.87#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.04:31:39.87#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.04:31:39.87#ibcon#ireg 17 cls_cnt 0 2006.173.04:31:39.87#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.04:31:39.87#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.04:31:39.87#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.04:31:39.87#ibcon#enter wrdev, iclass 20, count 0 2006.173.04:31:39.87#ibcon#first serial, iclass 20, count 0 2006.173.04:31:39.87#ibcon#enter sib2, iclass 20, count 0 2006.173.04:31:39.87#ibcon#flushed, iclass 20, count 0 2006.173.04:31:39.87#ibcon#about to write, iclass 20, count 0 2006.173.04:31:39.87#ibcon#wrote, iclass 20, count 0 2006.173.04:31:39.87#ibcon#about to read 3, iclass 20, count 0 2006.173.04:31:39.89#ibcon#read 3, iclass 20, count 0 2006.173.04:31:39.89#ibcon#about to read 4, iclass 20, count 0 2006.173.04:31:39.89#ibcon#read 4, iclass 20, count 0 2006.173.04:31:39.89#ibcon#about to read 5, iclass 20, count 0 2006.173.04:31:39.89#ibcon#read 5, iclass 20, count 0 2006.173.04:31:39.89#ibcon#about to read 6, iclass 20, count 0 2006.173.04:31:39.89#ibcon#read 6, iclass 20, count 0 2006.173.04:31:39.89#ibcon#end of sib2, iclass 20, count 0 2006.173.04:31:39.89#ibcon#*mode == 0, iclass 20, count 0 2006.173.04:31:39.89#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.04:31:39.89#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.04:31:39.89#ibcon#*before write, iclass 20, count 0 2006.173.04:31:39.89#ibcon#enter sib2, iclass 20, count 0 2006.173.04:31:39.89#ibcon#flushed, iclass 20, count 0 2006.173.04:31:39.89#ibcon#about to write, iclass 20, count 0 2006.173.04:31:39.89#ibcon#wrote, iclass 20, count 0 2006.173.04:31:39.89#ibcon#about to read 3, iclass 20, count 0 2006.173.04:31:39.93#ibcon#read 3, iclass 20, count 0 2006.173.04:31:39.93#ibcon#about to read 4, iclass 20, count 0 2006.173.04:31:39.93#ibcon#read 4, iclass 20, count 0 2006.173.04:31:39.93#ibcon#about to read 5, iclass 20, count 0 2006.173.04:31:39.93#ibcon#read 5, iclass 20, count 0 2006.173.04:31:39.93#ibcon#about to read 6, iclass 20, count 0 2006.173.04:31:39.93#ibcon#read 6, iclass 20, count 0 2006.173.04:31:39.93#ibcon#end of sib2, iclass 20, count 0 2006.173.04:31:39.93#ibcon#*after write, iclass 20, count 0 2006.173.04:31:39.93#ibcon#*before return 0, iclass 20, count 0 2006.173.04:31:39.93#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.04:31:39.93#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.04:31:39.93#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.04:31:39.93#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.04:31:39.93$vck44/vb=6,4 2006.173.04:31:39.93#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.04:31:39.93#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.04:31:39.93#ibcon#ireg 11 cls_cnt 2 2006.173.04:31:39.93#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.04:31:39.99#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.04:31:39.99#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.04:31:39.99#ibcon#enter wrdev, iclass 22, count 2 2006.173.04:31:39.99#ibcon#first serial, iclass 22, count 2 2006.173.04:31:39.99#ibcon#enter sib2, iclass 22, count 2 2006.173.04:31:39.99#ibcon#flushed, iclass 22, count 2 2006.173.04:31:39.99#ibcon#about to write, iclass 22, count 2 2006.173.04:31:39.99#ibcon#wrote, iclass 22, count 2 2006.173.04:31:39.99#ibcon#about to read 3, iclass 22, count 2 2006.173.04:31:40.01#ibcon#read 3, iclass 22, count 2 2006.173.04:31:40.01#ibcon#about to read 4, iclass 22, count 2 2006.173.04:31:40.01#ibcon#read 4, iclass 22, count 2 2006.173.04:31:40.01#ibcon#about to read 5, iclass 22, count 2 2006.173.04:31:40.01#ibcon#read 5, iclass 22, count 2 2006.173.04:31:40.01#ibcon#about to read 6, iclass 22, count 2 2006.173.04:31:40.01#ibcon#read 6, iclass 22, count 2 2006.173.04:31:40.01#ibcon#end of sib2, iclass 22, count 2 2006.173.04:31:40.01#ibcon#*mode == 0, iclass 22, count 2 2006.173.04:31:40.01#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.04:31:40.01#ibcon#[27=AT06-04\r\n] 2006.173.04:31:40.01#ibcon#*before write, iclass 22, count 2 2006.173.04:31:40.01#ibcon#enter sib2, iclass 22, count 2 2006.173.04:31:40.01#ibcon#flushed, iclass 22, count 2 2006.173.04:31:40.01#ibcon#about to write, iclass 22, count 2 2006.173.04:31:40.01#ibcon#wrote, iclass 22, count 2 2006.173.04:31:40.01#ibcon#about to read 3, iclass 22, count 2 2006.173.04:31:40.04#ibcon#read 3, iclass 22, count 2 2006.173.04:31:40.04#ibcon#about to read 4, iclass 22, count 2 2006.173.04:31:40.04#ibcon#read 4, iclass 22, count 2 2006.173.04:31:40.04#ibcon#about to read 5, iclass 22, count 2 2006.173.04:31:40.04#ibcon#read 5, iclass 22, count 2 2006.173.04:31:40.04#ibcon#about to read 6, iclass 22, count 2 2006.173.04:31:40.04#ibcon#read 6, iclass 22, count 2 2006.173.04:31:40.04#ibcon#end of sib2, iclass 22, count 2 2006.173.04:31:40.04#ibcon#*after write, iclass 22, count 2 2006.173.04:31:40.04#ibcon#*before return 0, iclass 22, count 2 2006.173.04:31:40.04#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.04:31:40.04#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.04:31:40.04#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.04:31:40.04#ibcon#ireg 7 cls_cnt 0 2006.173.04:31:40.04#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.04:31:40.16#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.04:31:40.16#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.04:31:40.16#ibcon#enter wrdev, iclass 22, count 0 2006.173.04:31:40.16#ibcon#first serial, iclass 22, count 0 2006.173.04:31:40.16#ibcon#enter sib2, iclass 22, count 0 2006.173.04:31:40.16#ibcon#flushed, iclass 22, count 0 2006.173.04:31:40.16#ibcon#about to write, iclass 22, count 0 2006.173.04:31:40.16#ibcon#wrote, iclass 22, count 0 2006.173.04:31:40.16#ibcon#about to read 3, iclass 22, count 0 2006.173.04:31:40.18#ibcon#read 3, iclass 22, count 0 2006.173.04:31:40.18#ibcon#about to read 4, iclass 22, count 0 2006.173.04:31:40.18#ibcon#read 4, iclass 22, count 0 2006.173.04:31:40.18#ibcon#about to read 5, iclass 22, count 0 2006.173.04:31:40.18#ibcon#read 5, iclass 22, count 0 2006.173.04:31:40.18#ibcon#about to read 6, iclass 22, count 0 2006.173.04:31:40.18#ibcon#read 6, iclass 22, count 0 2006.173.04:31:40.18#ibcon#end of sib2, iclass 22, count 0 2006.173.04:31:40.18#ibcon#*mode == 0, iclass 22, count 0 2006.173.04:31:40.18#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.04:31:40.18#ibcon#[27=USB\r\n] 2006.173.04:31:40.18#ibcon#*before write, iclass 22, count 0 2006.173.04:31:40.18#ibcon#enter sib2, iclass 22, count 0 2006.173.04:31:40.18#ibcon#flushed, iclass 22, count 0 2006.173.04:31:40.18#ibcon#about to write, iclass 22, count 0 2006.173.04:31:40.18#ibcon#wrote, iclass 22, count 0 2006.173.04:31:40.18#ibcon#about to read 3, iclass 22, count 0 2006.173.04:31:40.21#ibcon#read 3, iclass 22, count 0 2006.173.04:31:40.21#ibcon#about to read 4, iclass 22, count 0 2006.173.04:31:40.21#ibcon#read 4, iclass 22, count 0 2006.173.04:31:40.21#ibcon#about to read 5, iclass 22, count 0 2006.173.04:31:40.21#ibcon#read 5, iclass 22, count 0 2006.173.04:31:40.21#ibcon#about to read 6, iclass 22, count 0 2006.173.04:31:40.21#ibcon#read 6, iclass 22, count 0 2006.173.04:31:40.21#ibcon#end of sib2, iclass 22, count 0 2006.173.04:31:40.21#ibcon#*after write, iclass 22, count 0 2006.173.04:31:40.21#ibcon#*before return 0, iclass 22, count 0 2006.173.04:31:40.21#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.04:31:40.21#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.04:31:40.21#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.04:31:40.21#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.04:31:40.21$vck44/vblo=7,734.99 2006.173.04:31:40.21#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.04:31:40.21#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.04:31:40.21#ibcon#ireg 17 cls_cnt 0 2006.173.04:31:40.21#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.04:31:40.21#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.04:31:40.21#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.04:31:40.21#ibcon#enter wrdev, iclass 24, count 0 2006.173.04:31:40.21#ibcon#first serial, iclass 24, count 0 2006.173.04:31:40.21#ibcon#enter sib2, iclass 24, count 0 2006.173.04:31:40.21#ibcon#flushed, iclass 24, count 0 2006.173.04:31:40.21#ibcon#about to write, iclass 24, count 0 2006.173.04:31:40.21#ibcon#wrote, iclass 24, count 0 2006.173.04:31:40.21#ibcon#about to read 3, iclass 24, count 0 2006.173.04:31:40.23#ibcon#read 3, iclass 24, count 0 2006.173.04:31:40.23#ibcon#about to read 4, iclass 24, count 0 2006.173.04:31:40.23#ibcon#read 4, iclass 24, count 0 2006.173.04:31:40.23#ibcon#about to read 5, iclass 24, count 0 2006.173.04:31:40.23#ibcon#read 5, iclass 24, count 0 2006.173.04:31:40.23#ibcon#about to read 6, iclass 24, count 0 2006.173.04:31:40.23#ibcon#read 6, iclass 24, count 0 2006.173.04:31:40.23#ibcon#end of sib2, iclass 24, count 0 2006.173.04:31:40.23#ibcon#*mode == 0, iclass 24, count 0 2006.173.04:31:40.23#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.04:31:40.23#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.04:31:40.23#ibcon#*before write, iclass 24, count 0 2006.173.04:31:40.23#ibcon#enter sib2, iclass 24, count 0 2006.173.04:31:40.23#ibcon#flushed, iclass 24, count 0 2006.173.04:31:40.23#ibcon#about to write, iclass 24, count 0 2006.173.04:31:40.23#ibcon#wrote, iclass 24, count 0 2006.173.04:31:40.23#ibcon#about to read 3, iclass 24, count 0 2006.173.04:31:40.27#ibcon#read 3, iclass 24, count 0 2006.173.04:31:40.27#ibcon#about to read 4, iclass 24, count 0 2006.173.04:31:40.27#ibcon#read 4, iclass 24, count 0 2006.173.04:31:40.27#ibcon#about to read 5, iclass 24, count 0 2006.173.04:31:40.27#ibcon#read 5, iclass 24, count 0 2006.173.04:31:40.27#ibcon#about to read 6, iclass 24, count 0 2006.173.04:31:40.27#ibcon#read 6, iclass 24, count 0 2006.173.04:31:40.27#ibcon#end of sib2, iclass 24, count 0 2006.173.04:31:40.27#ibcon#*after write, iclass 24, count 0 2006.173.04:31:40.27#ibcon#*before return 0, iclass 24, count 0 2006.173.04:31:40.27#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.04:31:40.27#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.04:31:40.27#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.04:31:40.27#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.04:31:40.27$vck44/vb=7,4 2006.173.04:31:40.27#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.04:31:40.27#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.04:31:40.27#ibcon#ireg 11 cls_cnt 2 2006.173.04:31:40.27#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.04:31:40.33#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.04:31:40.33#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.04:31:40.33#ibcon#enter wrdev, iclass 26, count 2 2006.173.04:31:40.33#ibcon#first serial, iclass 26, count 2 2006.173.04:31:40.33#ibcon#enter sib2, iclass 26, count 2 2006.173.04:31:40.33#ibcon#flushed, iclass 26, count 2 2006.173.04:31:40.33#ibcon#about to write, iclass 26, count 2 2006.173.04:31:40.33#ibcon#wrote, iclass 26, count 2 2006.173.04:31:40.33#ibcon#about to read 3, iclass 26, count 2 2006.173.04:31:40.35#ibcon#read 3, iclass 26, count 2 2006.173.04:31:40.35#ibcon#about to read 4, iclass 26, count 2 2006.173.04:31:40.35#ibcon#read 4, iclass 26, count 2 2006.173.04:31:40.35#ibcon#about to read 5, iclass 26, count 2 2006.173.04:31:40.35#ibcon#read 5, iclass 26, count 2 2006.173.04:31:40.35#ibcon#about to read 6, iclass 26, count 2 2006.173.04:31:40.35#ibcon#read 6, iclass 26, count 2 2006.173.04:31:40.35#ibcon#end of sib2, iclass 26, count 2 2006.173.04:31:40.35#ibcon#*mode == 0, iclass 26, count 2 2006.173.04:31:40.35#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.04:31:40.35#ibcon#[27=AT07-04\r\n] 2006.173.04:31:40.35#ibcon#*before write, iclass 26, count 2 2006.173.04:31:40.35#ibcon#enter sib2, iclass 26, count 2 2006.173.04:31:40.35#ibcon#flushed, iclass 26, count 2 2006.173.04:31:40.35#ibcon#about to write, iclass 26, count 2 2006.173.04:31:40.35#ibcon#wrote, iclass 26, count 2 2006.173.04:31:40.35#ibcon#about to read 3, iclass 26, count 2 2006.173.04:31:40.38#ibcon#read 3, iclass 26, count 2 2006.173.04:31:40.38#ibcon#about to read 4, iclass 26, count 2 2006.173.04:31:40.38#ibcon#read 4, iclass 26, count 2 2006.173.04:31:40.38#ibcon#about to read 5, iclass 26, count 2 2006.173.04:31:40.38#ibcon#read 5, iclass 26, count 2 2006.173.04:31:40.38#ibcon#about to read 6, iclass 26, count 2 2006.173.04:31:40.38#ibcon#read 6, iclass 26, count 2 2006.173.04:31:40.38#ibcon#end of sib2, iclass 26, count 2 2006.173.04:31:40.38#ibcon#*after write, iclass 26, count 2 2006.173.04:31:40.38#ibcon#*before return 0, iclass 26, count 2 2006.173.04:31:40.38#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.04:31:40.38#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.04:31:40.38#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.04:31:40.38#ibcon#ireg 7 cls_cnt 0 2006.173.04:31:40.38#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.04:31:40.50#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.04:31:40.50#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.04:31:40.50#ibcon#enter wrdev, iclass 26, count 0 2006.173.04:31:40.50#ibcon#first serial, iclass 26, count 0 2006.173.04:31:40.50#ibcon#enter sib2, iclass 26, count 0 2006.173.04:31:40.50#ibcon#flushed, iclass 26, count 0 2006.173.04:31:40.50#ibcon#about to write, iclass 26, count 0 2006.173.04:31:40.50#ibcon#wrote, iclass 26, count 0 2006.173.04:31:40.50#ibcon#about to read 3, iclass 26, count 0 2006.173.04:31:40.52#ibcon#read 3, iclass 26, count 0 2006.173.04:31:40.52#ibcon#about to read 4, iclass 26, count 0 2006.173.04:31:40.52#ibcon#read 4, iclass 26, count 0 2006.173.04:31:40.52#ibcon#about to read 5, iclass 26, count 0 2006.173.04:31:40.52#ibcon#read 5, iclass 26, count 0 2006.173.04:31:40.52#ibcon#about to read 6, iclass 26, count 0 2006.173.04:31:40.52#ibcon#read 6, iclass 26, count 0 2006.173.04:31:40.52#ibcon#end of sib2, iclass 26, count 0 2006.173.04:31:40.52#ibcon#*mode == 0, iclass 26, count 0 2006.173.04:31:40.52#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.04:31:40.52#ibcon#[27=USB\r\n] 2006.173.04:31:40.52#ibcon#*before write, iclass 26, count 0 2006.173.04:31:40.52#ibcon#enter sib2, iclass 26, count 0 2006.173.04:31:40.52#ibcon#flushed, iclass 26, count 0 2006.173.04:31:40.52#ibcon#about to write, iclass 26, count 0 2006.173.04:31:40.52#ibcon#wrote, iclass 26, count 0 2006.173.04:31:40.52#ibcon#about to read 3, iclass 26, count 0 2006.173.04:31:40.55#ibcon#read 3, iclass 26, count 0 2006.173.04:31:40.55#ibcon#about to read 4, iclass 26, count 0 2006.173.04:31:40.55#ibcon#read 4, iclass 26, count 0 2006.173.04:31:40.55#ibcon#about to read 5, iclass 26, count 0 2006.173.04:31:40.55#ibcon#read 5, iclass 26, count 0 2006.173.04:31:40.55#ibcon#about to read 6, iclass 26, count 0 2006.173.04:31:40.55#ibcon#read 6, iclass 26, count 0 2006.173.04:31:40.55#ibcon#end of sib2, iclass 26, count 0 2006.173.04:31:40.55#ibcon#*after write, iclass 26, count 0 2006.173.04:31:40.55#ibcon#*before return 0, iclass 26, count 0 2006.173.04:31:40.55#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.04:31:40.55#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.04:31:40.55#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.04:31:40.55#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.04:31:40.55$vck44/vblo=8,744.99 2006.173.04:31:40.55#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.04:31:40.55#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.04:31:40.55#ibcon#ireg 17 cls_cnt 0 2006.173.04:31:40.55#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.04:31:40.55#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.04:31:40.55#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.04:31:40.55#ibcon#enter wrdev, iclass 28, count 0 2006.173.04:31:40.55#ibcon#first serial, iclass 28, count 0 2006.173.04:31:40.55#ibcon#enter sib2, iclass 28, count 0 2006.173.04:31:40.55#ibcon#flushed, iclass 28, count 0 2006.173.04:31:40.55#ibcon#about to write, iclass 28, count 0 2006.173.04:31:40.55#ibcon#wrote, iclass 28, count 0 2006.173.04:31:40.55#ibcon#about to read 3, iclass 28, count 0 2006.173.04:31:40.57#ibcon#read 3, iclass 28, count 0 2006.173.04:31:40.57#ibcon#about to read 4, iclass 28, count 0 2006.173.04:31:40.57#ibcon#read 4, iclass 28, count 0 2006.173.04:31:40.57#ibcon#about to read 5, iclass 28, count 0 2006.173.04:31:40.57#ibcon#read 5, iclass 28, count 0 2006.173.04:31:40.57#ibcon#about to read 6, iclass 28, count 0 2006.173.04:31:40.57#ibcon#read 6, iclass 28, count 0 2006.173.04:31:40.57#ibcon#end of sib2, iclass 28, count 0 2006.173.04:31:40.57#ibcon#*mode == 0, iclass 28, count 0 2006.173.04:31:40.57#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.04:31:40.57#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.04:31:40.57#ibcon#*before write, iclass 28, count 0 2006.173.04:31:40.57#ibcon#enter sib2, iclass 28, count 0 2006.173.04:31:40.57#ibcon#flushed, iclass 28, count 0 2006.173.04:31:40.57#ibcon#about to write, iclass 28, count 0 2006.173.04:31:40.57#ibcon#wrote, iclass 28, count 0 2006.173.04:31:40.57#ibcon#about to read 3, iclass 28, count 0 2006.173.04:31:40.61#ibcon#read 3, iclass 28, count 0 2006.173.04:31:40.61#ibcon#about to read 4, iclass 28, count 0 2006.173.04:31:40.61#ibcon#read 4, iclass 28, count 0 2006.173.04:31:40.61#ibcon#about to read 5, iclass 28, count 0 2006.173.04:31:40.61#ibcon#read 5, iclass 28, count 0 2006.173.04:31:40.61#ibcon#about to read 6, iclass 28, count 0 2006.173.04:31:40.61#ibcon#read 6, iclass 28, count 0 2006.173.04:31:40.61#ibcon#end of sib2, iclass 28, count 0 2006.173.04:31:40.61#ibcon#*after write, iclass 28, count 0 2006.173.04:31:40.61#ibcon#*before return 0, iclass 28, count 0 2006.173.04:31:40.61#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.04:31:40.61#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.04:31:40.61#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.04:31:40.61#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.04:31:40.61$vck44/vb=8,4 2006.173.04:31:40.61#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.04:31:40.61#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.04:31:40.61#ibcon#ireg 11 cls_cnt 2 2006.173.04:31:40.61#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.04:31:40.67#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.04:31:40.67#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.04:31:40.67#ibcon#enter wrdev, iclass 30, count 2 2006.173.04:31:40.67#ibcon#first serial, iclass 30, count 2 2006.173.04:31:40.67#ibcon#enter sib2, iclass 30, count 2 2006.173.04:31:40.67#ibcon#flushed, iclass 30, count 2 2006.173.04:31:40.67#ibcon#about to write, iclass 30, count 2 2006.173.04:31:40.67#ibcon#wrote, iclass 30, count 2 2006.173.04:31:40.67#ibcon#about to read 3, iclass 30, count 2 2006.173.04:31:40.69#ibcon#read 3, iclass 30, count 2 2006.173.04:31:40.69#ibcon#about to read 4, iclass 30, count 2 2006.173.04:31:40.69#ibcon#read 4, iclass 30, count 2 2006.173.04:31:40.69#ibcon#about to read 5, iclass 30, count 2 2006.173.04:31:40.69#ibcon#read 5, iclass 30, count 2 2006.173.04:31:40.69#ibcon#about to read 6, iclass 30, count 2 2006.173.04:31:40.69#ibcon#read 6, iclass 30, count 2 2006.173.04:31:40.69#ibcon#end of sib2, iclass 30, count 2 2006.173.04:31:40.69#ibcon#*mode == 0, iclass 30, count 2 2006.173.04:31:40.69#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.04:31:40.69#ibcon#[27=AT08-04\r\n] 2006.173.04:31:40.69#ibcon#*before write, iclass 30, count 2 2006.173.04:31:40.69#ibcon#enter sib2, iclass 30, count 2 2006.173.04:31:40.69#ibcon#flushed, iclass 30, count 2 2006.173.04:31:40.69#ibcon#about to write, iclass 30, count 2 2006.173.04:31:40.69#ibcon#wrote, iclass 30, count 2 2006.173.04:31:40.69#ibcon#about to read 3, iclass 30, count 2 2006.173.04:31:40.72#ibcon#read 3, iclass 30, count 2 2006.173.04:31:40.72#ibcon#about to read 4, iclass 30, count 2 2006.173.04:31:40.72#ibcon#read 4, iclass 30, count 2 2006.173.04:31:40.72#ibcon#about to read 5, iclass 30, count 2 2006.173.04:31:40.72#ibcon#read 5, iclass 30, count 2 2006.173.04:31:40.72#ibcon#about to read 6, iclass 30, count 2 2006.173.04:31:40.72#ibcon#read 6, iclass 30, count 2 2006.173.04:31:40.72#ibcon#end of sib2, iclass 30, count 2 2006.173.04:31:40.72#ibcon#*after write, iclass 30, count 2 2006.173.04:31:40.72#ibcon#*before return 0, iclass 30, count 2 2006.173.04:31:40.72#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.04:31:40.72#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.04:31:40.72#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.04:31:40.72#ibcon#ireg 7 cls_cnt 0 2006.173.04:31:40.72#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.04:31:40.84#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.04:31:40.84#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.04:31:40.84#ibcon#enter wrdev, iclass 30, count 0 2006.173.04:31:40.84#ibcon#first serial, iclass 30, count 0 2006.173.04:31:40.84#ibcon#enter sib2, iclass 30, count 0 2006.173.04:31:40.84#ibcon#flushed, iclass 30, count 0 2006.173.04:31:40.84#ibcon#about to write, iclass 30, count 0 2006.173.04:31:40.84#ibcon#wrote, iclass 30, count 0 2006.173.04:31:40.84#ibcon#about to read 3, iclass 30, count 0 2006.173.04:31:40.86#ibcon#read 3, iclass 30, count 0 2006.173.04:31:40.86#ibcon#about to read 4, iclass 30, count 0 2006.173.04:31:40.86#ibcon#read 4, iclass 30, count 0 2006.173.04:31:40.86#ibcon#about to read 5, iclass 30, count 0 2006.173.04:31:40.86#ibcon#read 5, iclass 30, count 0 2006.173.04:31:40.86#ibcon#about to read 6, iclass 30, count 0 2006.173.04:31:40.86#ibcon#read 6, iclass 30, count 0 2006.173.04:31:40.86#ibcon#end of sib2, iclass 30, count 0 2006.173.04:31:40.86#ibcon#*mode == 0, iclass 30, count 0 2006.173.04:31:40.86#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.04:31:40.86#ibcon#[27=USB\r\n] 2006.173.04:31:40.86#ibcon#*before write, iclass 30, count 0 2006.173.04:31:40.86#ibcon#enter sib2, iclass 30, count 0 2006.173.04:31:40.86#ibcon#flushed, iclass 30, count 0 2006.173.04:31:40.86#ibcon#about to write, iclass 30, count 0 2006.173.04:31:40.86#ibcon#wrote, iclass 30, count 0 2006.173.04:31:40.86#ibcon#about to read 3, iclass 30, count 0 2006.173.04:31:40.89#ibcon#read 3, iclass 30, count 0 2006.173.04:31:40.89#ibcon#about to read 4, iclass 30, count 0 2006.173.04:31:40.89#ibcon#read 4, iclass 30, count 0 2006.173.04:31:40.89#ibcon#about to read 5, iclass 30, count 0 2006.173.04:31:40.89#ibcon#read 5, iclass 30, count 0 2006.173.04:31:40.89#ibcon#about to read 6, iclass 30, count 0 2006.173.04:31:40.89#ibcon#read 6, iclass 30, count 0 2006.173.04:31:40.89#ibcon#end of sib2, iclass 30, count 0 2006.173.04:31:40.89#ibcon#*after write, iclass 30, count 0 2006.173.04:31:40.89#ibcon#*before return 0, iclass 30, count 0 2006.173.04:31:40.89#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.04:31:40.89#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.04:31:40.89#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.04:31:40.89#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.04:31:40.89$vck44/vabw=wide 2006.173.04:31:40.89#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.04:31:40.89#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.04:31:40.89#ibcon#ireg 8 cls_cnt 0 2006.173.04:31:40.89#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.04:31:40.89#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.04:31:40.89#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.04:31:40.89#ibcon#enter wrdev, iclass 32, count 0 2006.173.04:31:40.89#ibcon#first serial, iclass 32, count 0 2006.173.04:31:40.89#ibcon#enter sib2, iclass 32, count 0 2006.173.04:31:40.89#ibcon#flushed, iclass 32, count 0 2006.173.04:31:40.89#ibcon#about to write, iclass 32, count 0 2006.173.04:31:40.89#ibcon#wrote, iclass 32, count 0 2006.173.04:31:40.89#ibcon#about to read 3, iclass 32, count 0 2006.173.04:31:40.91#ibcon#read 3, iclass 32, count 0 2006.173.04:31:40.91#ibcon#about to read 4, iclass 32, count 0 2006.173.04:31:40.91#ibcon#read 4, iclass 32, count 0 2006.173.04:31:40.91#ibcon#about to read 5, iclass 32, count 0 2006.173.04:31:40.91#ibcon#read 5, iclass 32, count 0 2006.173.04:31:40.91#ibcon#about to read 6, iclass 32, count 0 2006.173.04:31:40.91#ibcon#read 6, iclass 32, count 0 2006.173.04:31:40.91#ibcon#end of sib2, iclass 32, count 0 2006.173.04:31:40.91#ibcon#*mode == 0, iclass 32, count 0 2006.173.04:31:40.91#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.04:31:40.91#ibcon#[25=BW32\r\n] 2006.173.04:31:40.91#ibcon#*before write, iclass 32, count 0 2006.173.04:31:40.91#ibcon#enter sib2, iclass 32, count 0 2006.173.04:31:40.91#ibcon#flushed, iclass 32, count 0 2006.173.04:31:40.91#ibcon#about to write, iclass 32, count 0 2006.173.04:31:40.91#ibcon#wrote, iclass 32, count 0 2006.173.04:31:40.91#ibcon#about to read 3, iclass 32, count 0 2006.173.04:31:40.94#ibcon#read 3, iclass 32, count 0 2006.173.04:31:40.94#ibcon#about to read 4, iclass 32, count 0 2006.173.04:31:40.94#ibcon#read 4, iclass 32, count 0 2006.173.04:31:40.94#ibcon#about to read 5, iclass 32, count 0 2006.173.04:31:40.94#ibcon#read 5, iclass 32, count 0 2006.173.04:31:40.94#ibcon#about to read 6, iclass 32, count 0 2006.173.04:31:40.94#ibcon#read 6, iclass 32, count 0 2006.173.04:31:40.94#ibcon#end of sib2, iclass 32, count 0 2006.173.04:31:40.94#ibcon#*after write, iclass 32, count 0 2006.173.04:31:40.94#ibcon#*before return 0, iclass 32, count 0 2006.173.04:31:40.94#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.04:31:40.94#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.04:31:40.94#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.04:31:40.94#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.04:31:40.94$vck44/vbbw=wide 2006.173.04:31:40.94#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.04:31:40.94#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.04:31:40.94#ibcon#ireg 8 cls_cnt 0 2006.173.04:31:40.94#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.04:31:41.01#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.04:31:41.01#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.04:31:41.01#ibcon#enter wrdev, iclass 34, count 0 2006.173.04:31:41.01#ibcon#first serial, iclass 34, count 0 2006.173.04:31:41.01#ibcon#enter sib2, iclass 34, count 0 2006.173.04:31:41.01#ibcon#flushed, iclass 34, count 0 2006.173.04:31:41.01#ibcon#about to write, iclass 34, count 0 2006.173.04:31:41.01#ibcon#wrote, iclass 34, count 0 2006.173.04:31:41.01#ibcon#about to read 3, iclass 34, count 0 2006.173.04:31:41.03#ibcon#read 3, iclass 34, count 0 2006.173.04:31:41.03#ibcon#about to read 4, iclass 34, count 0 2006.173.04:31:41.03#ibcon#read 4, iclass 34, count 0 2006.173.04:31:41.03#ibcon#about to read 5, iclass 34, count 0 2006.173.04:31:41.03#ibcon#read 5, iclass 34, count 0 2006.173.04:31:41.03#ibcon#about to read 6, iclass 34, count 0 2006.173.04:31:41.03#ibcon#read 6, iclass 34, count 0 2006.173.04:31:41.03#ibcon#end of sib2, iclass 34, count 0 2006.173.04:31:41.03#ibcon#*mode == 0, iclass 34, count 0 2006.173.04:31:41.03#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.04:31:41.03#ibcon#[27=BW32\r\n] 2006.173.04:31:41.03#ibcon#*before write, iclass 34, count 0 2006.173.04:31:41.03#ibcon#enter sib2, iclass 34, count 0 2006.173.04:31:41.03#ibcon#flushed, iclass 34, count 0 2006.173.04:31:41.03#ibcon#about to write, iclass 34, count 0 2006.173.04:31:41.03#ibcon#wrote, iclass 34, count 0 2006.173.04:31:41.03#ibcon#about to read 3, iclass 34, count 0 2006.173.04:31:41.06#ibcon#read 3, iclass 34, count 0 2006.173.04:31:41.06#ibcon#about to read 4, iclass 34, count 0 2006.173.04:31:41.06#ibcon#read 4, iclass 34, count 0 2006.173.04:31:41.06#ibcon#about to read 5, iclass 34, count 0 2006.173.04:31:41.06#ibcon#read 5, iclass 34, count 0 2006.173.04:31:41.06#ibcon#about to read 6, iclass 34, count 0 2006.173.04:31:41.06#ibcon#read 6, iclass 34, count 0 2006.173.04:31:41.06#ibcon#end of sib2, iclass 34, count 0 2006.173.04:31:41.06#ibcon#*after write, iclass 34, count 0 2006.173.04:31:41.06#ibcon#*before return 0, iclass 34, count 0 2006.173.04:31:41.06#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.04:31:41.06#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.04:31:41.06#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.04:31:41.06#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.04:31:41.06$setupk4/ifdk4 2006.173.04:31:41.06$ifdk4/lo= 2006.173.04:31:41.06$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.04:31:41.06$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.04:31:41.06$ifdk4/patch= 2006.173.04:31:41.06$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.04:31:41.06$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.04:31:41.06$setupk4/!*+20s 2006.173.04:31:44.63#abcon#<5=/15 1.0 2.0 23.31 801005.9\r\n> 2006.173.04:31:44.65#abcon#{5=INTERFACE CLEAR} 2006.173.04:31:44.71#abcon#[5=S1D000X0/0*\r\n] 2006.173.04:31:54.80#abcon#<5=/15 1.0 2.0 23.31 801005.9\r\n> 2006.173.04:31:54.82#abcon#{5=INTERFACE CLEAR} 2006.173.04:31:54.88#abcon#[5=S1D000X0/0*\r\n] 2006.173.04:31:55.57$setupk4/"tpicd 2006.173.04:31:55.57$setupk4/echo=off 2006.173.04:31:55.57$setupk4/xlog=off 2006.173.04:31:55.57:!2006.173.04:33:28 2006.173.04:32:11.13#trakl#Source acquired 2006.173.04:32:11.13#flagr#flagr/antenna,acquired 2006.173.04:33:28.00:preob 2006.173.04:33:28.14/onsource/TRACKING 2006.173.04:33:28.14:!2006.173.04:33:38 2006.173.04:33:38.00:"tape 2006.173.04:33:38.00:"st=record 2006.173.04:33:38.00:data_valid=on 2006.173.04:33:38.00:midob 2006.173.04:33:38.14/onsource/TRACKING 2006.173.04:33:38.14/wx/23.34,1005.9,79 2006.173.04:33:38.32/cable/+6.5096E-03 2006.173.04:33:39.41/va/01,07,usb,yes,34,37 2006.173.04:33:39.41/va/02,06,usb,yes,34,35 2006.173.04:33:39.41/va/03,05,usb,yes,43,45 2006.173.04:33:39.41/va/04,06,usb,yes,35,37 2006.173.04:33:39.41/va/05,04,usb,yes,27,28 2006.173.04:33:39.41/va/06,03,usb,yes,38,38 2006.173.04:33:39.41/va/07,04,usb,yes,31,32 2006.173.04:33:39.41/va/08,04,usb,yes,26,32 2006.173.04:33:39.64/valo/01,524.99,yes,locked 2006.173.04:33:39.64/valo/02,534.99,yes,locked 2006.173.04:33:39.64/valo/03,564.99,yes,locked 2006.173.04:33:39.64/valo/04,624.99,yes,locked 2006.173.04:33:39.64/valo/05,734.99,yes,locked 2006.173.04:33:39.64/valo/06,814.99,yes,locked 2006.173.04:33:39.64/valo/07,864.99,yes,locked 2006.173.04:33:39.64/valo/08,884.99,yes,locked 2006.173.04:33:40.73/vb/01,04,usb,yes,29,27 2006.173.04:33:40.73/vb/02,04,usb,yes,31,31 2006.173.04:33:40.73/vb/03,04,usb,yes,28,31 2006.173.04:33:40.73/vb/04,04,usb,yes,32,31 2006.173.04:33:40.73/vb/05,04,usb,yes,25,27 2006.173.04:33:40.73/vb/06,04,usb,yes,29,26 2006.173.04:33:40.73/vb/07,04,usb,yes,29,29 2006.173.04:33:40.73/vb/08,04,usb,yes,27,30 2006.173.04:33:40.96/vblo/01,629.99,yes,locked 2006.173.04:33:40.96/vblo/02,634.99,yes,locked 2006.173.04:33:40.96/vblo/03,649.99,yes,locked 2006.173.04:33:40.96/vblo/04,679.99,yes,locked 2006.173.04:33:40.96/vblo/05,709.99,yes,locked 2006.173.04:33:40.96/vblo/06,719.99,yes,locked 2006.173.04:33:40.96/vblo/07,734.99,yes,locked 2006.173.04:33:40.96/vblo/08,744.99,yes,locked 2006.173.04:33:41.11/vabw/8 2006.173.04:33:41.26/vbbw/8 2006.173.04:33:41.35/xfe/off,on,15.0 2006.173.04:33:41.72/ifatt/23,28,28,28 2006.173.04:33:42.08/fmout-gps/S +3.95E-07 2006.173.04:33:42.11:!2006.173.04:34:28 2006.173.04:34:28.01:data_valid=off 2006.173.04:34:28.01:"et 2006.173.04:34:28.01:!+3s 2006.173.04:34:31.02:"tape 2006.173.04:34:31.02:postob 2006.173.04:34:31.20/cable/+6.5085E-03 2006.173.04:34:31.20/wx/23.35,1005.9,80 2006.173.04:34:32.08/fmout-gps/S +3.94E-07 2006.173.04:34:32.08:scan_name=173-0436,jd0606,330 2006.173.04:34:32.08:source=cta26,033930.94,-014635.8,2000.0,cw 2006.173.04:34:33.14#flagr#flagr/antenna,new-source 2006.173.04:34:33.14:checkk5 2006.173.04:34:33.50/chk_autoobs//k5ts1/ autoobs is running! 2006.173.04:34:33.91/chk_autoobs//k5ts2/ autoobs is running! 2006.173.04:34:34.31/chk_autoobs//k5ts3/ autoobs is running! 2006.173.04:34:34.70/chk_autoobs//k5ts4/ autoobs is running! 2006.173.04:34:35.07/chk_obsdata//k5ts1/T1730433??a.dat file size is correct (nominal:200MB, actual:196MB). 2006.173.04:34:35.45/chk_obsdata//k5ts2/T1730433??b.dat file size is correct (nominal:200MB, actual:196MB). 2006.173.04:34:35.85/chk_obsdata//k5ts3/T1730433??c.dat file size is correct (nominal:200MB, actual:196MB). 2006.173.04:34:36.26/chk_obsdata//k5ts4/T1730433??d.dat file size is correct (nominal:200MB, actual:196MB). 2006.173.04:34:36.98/k5log//k5ts1_log_newline 2006.173.04:34:37.69/k5log//k5ts2_log_newline 2006.173.04:34:38.40/k5log//k5ts3_log_newline 2006.173.04:34:39.10/k5log//k5ts4_log_newline 2006.173.04:34:39.13/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.04:34:39.13:setupk4=1 2006.173.04:34:39.13$setupk4/echo=on 2006.173.04:34:39.13$setupk4/pcalon 2006.173.04:34:39.13$pcalon/"no phase cal control is implemented here 2006.173.04:34:39.13$setupk4/"tpicd=stop 2006.173.04:34:39.13$setupk4/"rec=synch_on 2006.173.04:34:39.13$setupk4/"rec_mode=128 2006.173.04:34:39.13$setupk4/!* 2006.173.04:34:39.13$setupk4/recpk4 2006.173.04:34:39.13$recpk4/recpatch= 2006.173.04:34:39.13$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.04:34:39.13$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.04:34:39.13$setupk4/vck44 2006.173.04:34:39.13$vck44/valo=1,524.99 2006.173.04:34:39.13#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.04:34:39.13#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.04:34:39.13#ibcon#ireg 17 cls_cnt 0 2006.173.04:34:39.13#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.04:34:39.13#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.04:34:39.13#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.04:34:39.13#ibcon#enter wrdev, iclass 39, count 0 2006.173.04:34:39.13#ibcon#first serial, iclass 39, count 0 2006.173.04:34:39.13#ibcon#enter sib2, iclass 39, count 0 2006.173.04:34:39.13#ibcon#flushed, iclass 39, count 0 2006.173.04:34:39.13#ibcon#about to write, iclass 39, count 0 2006.173.04:34:39.13#ibcon#wrote, iclass 39, count 0 2006.173.04:34:39.13#ibcon#about to read 3, iclass 39, count 0 2006.173.04:34:39.15#ibcon#read 3, iclass 39, count 0 2006.173.04:34:39.15#ibcon#about to read 4, iclass 39, count 0 2006.173.04:34:39.15#ibcon#read 4, iclass 39, count 0 2006.173.04:34:39.15#ibcon#about to read 5, iclass 39, count 0 2006.173.04:34:39.15#ibcon#read 5, iclass 39, count 0 2006.173.04:34:39.15#ibcon#about to read 6, iclass 39, count 0 2006.173.04:34:39.15#ibcon#read 6, iclass 39, count 0 2006.173.04:34:39.15#ibcon#end of sib2, iclass 39, count 0 2006.173.04:34:39.15#ibcon#*mode == 0, iclass 39, count 0 2006.173.04:34:39.15#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.04:34:39.15#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.04:34:39.15#ibcon#*before write, iclass 39, count 0 2006.173.04:34:39.15#ibcon#enter sib2, iclass 39, count 0 2006.173.04:34:39.15#ibcon#flushed, iclass 39, count 0 2006.173.04:34:39.15#ibcon#about to write, iclass 39, count 0 2006.173.04:34:39.15#ibcon#wrote, iclass 39, count 0 2006.173.04:34:39.15#ibcon#about to read 3, iclass 39, count 0 2006.173.04:34:39.20#ibcon#read 3, iclass 39, count 0 2006.173.04:34:39.20#ibcon#about to read 4, iclass 39, count 0 2006.173.04:34:39.20#ibcon#read 4, iclass 39, count 0 2006.173.04:34:39.20#ibcon#about to read 5, iclass 39, count 0 2006.173.04:34:39.20#ibcon#read 5, iclass 39, count 0 2006.173.04:34:39.20#ibcon#about to read 6, iclass 39, count 0 2006.173.04:34:39.20#ibcon#read 6, iclass 39, count 0 2006.173.04:34:39.20#ibcon#end of sib2, iclass 39, count 0 2006.173.04:34:39.20#ibcon#*after write, iclass 39, count 0 2006.173.04:34:39.20#ibcon#*before return 0, iclass 39, count 0 2006.173.04:34:39.20#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.04:34:39.20#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.04:34:39.20#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.04:34:39.20#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.04:34:39.20$vck44/va=1,7 2006.173.04:34:39.20#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.04:34:39.20#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.04:34:39.20#ibcon#ireg 11 cls_cnt 2 2006.173.04:34:39.20#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.04:34:39.20#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.04:34:39.20#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.04:34:39.20#ibcon#enter wrdev, iclass 3, count 2 2006.173.04:34:39.20#ibcon#first serial, iclass 3, count 2 2006.173.04:34:39.20#ibcon#enter sib2, iclass 3, count 2 2006.173.04:34:39.20#ibcon#flushed, iclass 3, count 2 2006.173.04:34:39.20#ibcon#about to write, iclass 3, count 2 2006.173.04:34:39.20#ibcon#wrote, iclass 3, count 2 2006.173.04:34:39.20#ibcon#about to read 3, iclass 3, count 2 2006.173.04:34:39.22#ibcon#read 3, iclass 3, count 2 2006.173.04:34:39.22#ibcon#about to read 4, iclass 3, count 2 2006.173.04:34:39.22#ibcon#read 4, iclass 3, count 2 2006.173.04:34:39.22#ibcon#about to read 5, iclass 3, count 2 2006.173.04:34:39.22#ibcon#read 5, iclass 3, count 2 2006.173.04:34:39.22#ibcon#about to read 6, iclass 3, count 2 2006.173.04:34:39.22#ibcon#read 6, iclass 3, count 2 2006.173.04:34:39.22#ibcon#end of sib2, iclass 3, count 2 2006.173.04:34:39.22#ibcon#*mode == 0, iclass 3, count 2 2006.173.04:34:39.22#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.04:34:39.22#ibcon#[25=AT01-07\r\n] 2006.173.04:34:39.22#ibcon#*before write, iclass 3, count 2 2006.173.04:34:39.22#ibcon#enter sib2, iclass 3, count 2 2006.173.04:34:39.22#ibcon#flushed, iclass 3, count 2 2006.173.04:34:39.22#ibcon#about to write, iclass 3, count 2 2006.173.04:34:39.22#ibcon#wrote, iclass 3, count 2 2006.173.04:34:39.22#ibcon#about to read 3, iclass 3, count 2 2006.173.04:34:39.25#ibcon#read 3, iclass 3, count 2 2006.173.04:34:39.25#ibcon#about to read 4, iclass 3, count 2 2006.173.04:34:39.25#ibcon#read 4, iclass 3, count 2 2006.173.04:34:39.25#ibcon#about to read 5, iclass 3, count 2 2006.173.04:34:39.25#ibcon#read 5, iclass 3, count 2 2006.173.04:34:39.25#ibcon#about to read 6, iclass 3, count 2 2006.173.04:34:39.25#ibcon#read 6, iclass 3, count 2 2006.173.04:34:39.25#ibcon#end of sib2, iclass 3, count 2 2006.173.04:34:39.25#ibcon#*after write, iclass 3, count 2 2006.173.04:34:39.25#ibcon#*before return 0, iclass 3, count 2 2006.173.04:34:39.25#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.04:34:39.25#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.04:34:39.25#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.04:34:39.25#ibcon#ireg 7 cls_cnt 0 2006.173.04:34:39.25#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.04:34:39.37#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.04:34:39.37#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.04:34:39.37#ibcon#enter wrdev, iclass 3, count 0 2006.173.04:34:39.37#ibcon#first serial, iclass 3, count 0 2006.173.04:34:39.37#ibcon#enter sib2, iclass 3, count 0 2006.173.04:34:39.37#ibcon#flushed, iclass 3, count 0 2006.173.04:34:39.37#ibcon#about to write, iclass 3, count 0 2006.173.04:34:39.37#ibcon#wrote, iclass 3, count 0 2006.173.04:34:39.37#ibcon#about to read 3, iclass 3, count 0 2006.173.04:34:39.39#ibcon#read 3, iclass 3, count 0 2006.173.04:34:39.39#ibcon#about to read 4, iclass 3, count 0 2006.173.04:34:39.39#ibcon#read 4, iclass 3, count 0 2006.173.04:34:39.39#ibcon#about to read 5, iclass 3, count 0 2006.173.04:34:39.39#ibcon#read 5, iclass 3, count 0 2006.173.04:34:39.39#ibcon#about to read 6, iclass 3, count 0 2006.173.04:34:39.39#ibcon#read 6, iclass 3, count 0 2006.173.04:34:39.39#ibcon#end of sib2, iclass 3, count 0 2006.173.04:34:39.39#ibcon#*mode == 0, iclass 3, count 0 2006.173.04:34:39.39#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.04:34:39.39#ibcon#[25=USB\r\n] 2006.173.04:34:39.39#ibcon#*before write, iclass 3, count 0 2006.173.04:34:39.39#ibcon#enter sib2, iclass 3, count 0 2006.173.04:34:39.39#ibcon#flushed, iclass 3, count 0 2006.173.04:34:39.39#ibcon#about to write, iclass 3, count 0 2006.173.04:34:39.39#ibcon#wrote, iclass 3, count 0 2006.173.04:34:39.39#ibcon#about to read 3, iclass 3, count 0 2006.173.04:34:39.42#ibcon#read 3, iclass 3, count 0 2006.173.04:34:39.42#ibcon#about to read 4, iclass 3, count 0 2006.173.04:34:39.42#ibcon#read 4, iclass 3, count 0 2006.173.04:34:39.42#ibcon#about to read 5, iclass 3, count 0 2006.173.04:34:39.42#ibcon#read 5, iclass 3, count 0 2006.173.04:34:39.42#ibcon#about to read 6, iclass 3, count 0 2006.173.04:34:39.42#ibcon#read 6, iclass 3, count 0 2006.173.04:34:39.42#ibcon#end of sib2, iclass 3, count 0 2006.173.04:34:39.42#ibcon#*after write, iclass 3, count 0 2006.173.04:34:39.42#ibcon#*before return 0, iclass 3, count 0 2006.173.04:34:39.42#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.04:34:39.42#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.04:34:39.42#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.04:34:39.42#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.04:34:39.42$vck44/valo=2,534.99 2006.173.04:34:39.42#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.04:34:39.42#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.04:34:39.42#ibcon#ireg 17 cls_cnt 0 2006.173.04:34:39.42#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.04:34:39.42#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.04:34:39.42#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.04:34:39.42#ibcon#enter wrdev, iclass 5, count 0 2006.173.04:34:39.42#ibcon#first serial, iclass 5, count 0 2006.173.04:34:39.42#ibcon#enter sib2, iclass 5, count 0 2006.173.04:34:39.42#ibcon#flushed, iclass 5, count 0 2006.173.04:34:39.42#ibcon#about to write, iclass 5, count 0 2006.173.04:34:39.42#ibcon#wrote, iclass 5, count 0 2006.173.04:34:39.42#ibcon#about to read 3, iclass 5, count 0 2006.173.04:34:39.44#ibcon#read 3, iclass 5, count 0 2006.173.04:34:39.44#ibcon#about to read 4, iclass 5, count 0 2006.173.04:34:39.44#ibcon#read 4, iclass 5, count 0 2006.173.04:34:39.44#ibcon#about to read 5, iclass 5, count 0 2006.173.04:34:39.44#ibcon#read 5, iclass 5, count 0 2006.173.04:34:39.44#ibcon#about to read 6, iclass 5, count 0 2006.173.04:34:39.44#ibcon#read 6, iclass 5, count 0 2006.173.04:34:39.44#ibcon#end of sib2, iclass 5, count 0 2006.173.04:34:39.44#ibcon#*mode == 0, iclass 5, count 0 2006.173.04:34:39.44#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.04:34:39.44#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.04:34:39.44#ibcon#*before write, iclass 5, count 0 2006.173.04:34:39.44#ibcon#enter sib2, iclass 5, count 0 2006.173.04:34:39.44#ibcon#flushed, iclass 5, count 0 2006.173.04:34:39.44#ibcon#about to write, iclass 5, count 0 2006.173.04:34:39.44#ibcon#wrote, iclass 5, count 0 2006.173.04:34:39.44#ibcon#about to read 3, iclass 5, count 0 2006.173.04:34:39.48#ibcon#read 3, iclass 5, count 0 2006.173.04:34:39.48#ibcon#about to read 4, iclass 5, count 0 2006.173.04:34:39.48#ibcon#read 4, iclass 5, count 0 2006.173.04:34:39.48#ibcon#about to read 5, iclass 5, count 0 2006.173.04:34:39.48#ibcon#read 5, iclass 5, count 0 2006.173.04:34:39.48#ibcon#about to read 6, iclass 5, count 0 2006.173.04:34:39.48#ibcon#read 6, iclass 5, count 0 2006.173.04:34:39.48#ibcon#end of sib2, iclass 5, count 0 2006.173.04:34:39.48#ibcon#*after write, iclass 5, count 0 2006.173.04:34:39.48#ibcon#*before return 0, iclass 5, count 0 2006.173.04:34:39.48#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.04:34:39.48#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.04:34:39.48#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.04:34:39.48#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.04:34:39.48$vck44/va=2,6 2006.173.04:34:39.48#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.173.04:34:39.48#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.173.04:34:39.48#ibcon#ireg 11 cls_cnt 2 2006.173.04:34:39.48#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.04:34:39.54#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.04:34:39.54#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.04:34:39.54#ibcon#enter wrdev, iclass 7, count 2 2006.173.04:34:39.54#ibcon#first serial, iclass 7, count 2 2006.173.04:34:39.54#ibcon#enter sib2, iclass 7, count 2 2006.173.04:34:39.54#ibcon#flushed, iclass 7, count 2 2006.173.04:34:39.54#ibcon#about to write, iclass 7, count 2 2006.173.04:34:39.54#ibcon#wrote, iclass 7, count 2 2006.173.04:34:39.54#ibcon#about to read 3, iclass 7, count 2 2006.173.04:34:39.56#ibcon#read 3, iclass 7, count 2 2006.173.04:34:39.56#ibcon#about to read 4, iclass 7, count 2 2006.173.04:34:39.56#ibcon#read 4, iclass 7, count 2 2006.173.04:34:39.56#ibcon#about to read 5, iclass 7, count 2 2006.173.04:34:39.56#ibcon#read 5, iclass 7, count 2 2006.173.04:34:39.56#ibcon#about to read 6, iclass 7, count 2 2006.173.04:34:39.56#ibcon#read 6, iclass 7, count 2 2006.173.04:34:39.56#ibcon#end of sib2, iclass 7, count 2 2006.173.04:34:39.56#ibcon#*mode == 0, iclass 7, count 2 2006.173.04:34:39.56#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.173.04:34:39.56#ibcon#[25=AT02-06\r\n] 2006.173.04:34:39.56#ibcon#*before write, iclass 7, count 2 2006.173.04:34:39.56#ibcon#enter sib2, iclass 7, count 2 2006.173.04:34:39.56#ibcon#flushed, iclass 7, count 2 2006.173.04:34:39.56#ibcon#about to write, iclass 7, count 2 2006.173.04:34:39.56#ibcon#wrote, iclass 7, count 2 2006.173.04:34:39.56#ibcon#about to read 3, iclass 7, count 2 2006.173.04:34:39.59#ibcon#read 3, iclass 7, count 2 2006.173.04:34:39.59#ibcon#about to read 4, iclass 7, count 2 2006.173.04:34:39.59#ibcon#read 4, iclass 7, count 2 2006.173.04:34:39.59#ibcon#about to read 5, iclass 7, count 2 2006.173.04:34:39.59#ibcon#read 5, iclass 7, count 2 2006.173.04:34:39.59#ibcon#about to read 6, iclass 7, count 2 2006.173.04:34:39.59#ibcon#read 6, iclass 7, count 2 2006.173.04:34:39.59#ibcon#end of sib2, iclass 7, count 2 2006.173.04:34:39.59#ibcon#*after write, iclass 7, count 2 2006.173.04:34:39.59#ibcon#*before return 0, iclass 7, count 2 2006.173.04:34:39.59#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.04:34:39.59#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.173.04:34:39.59#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.173.04:34:39.59#ibcon#ireg 7 cls_cnt 0 2006.173.04:34:39.59#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.04:34:39.71#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.04:34:39.71#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.04:34:39.71#ibcon#enter wrdev, iclass 7, count 0 2006.173.04:34:39.71#ibcon#first serial, iclass 7, count 0 2006.173.04:34:39.71#ibcon#enter sib2, iclass 7, count 0 2006.173.04:34:39.71#ibcon#flushed, iclass 7, count 0 2006.173.04:34:39.71#ibcon#about to write, iclass 7, count 0 2006.173.04:34:39.71#ibcon#wrote, iclass 7, count 0 2006.173.04:34:39.71#ibcon#about to read 3, iclass 7, count 0 2006.173.04:34:39.73#ibcon#read 3, iclass 7, count 0 2006.173.04:34:39.73#ibcon#about to read 4, iclass 7, count 0 2006.173.04:34:39.73#ibcon#read 4, iclass 7, count 0 2006.173.04:34:39.73#ibcon#about to read 5, iclass 7, count 0 2006.173.04:34:39.73#ibcon#read 5, iclass 7, count 0 2006.173.04:34:39.73#ibcon#about to read 6, iclass 7, count 0 2006.173.04:34:39.73#ibcon#read 6, iclass 7, count 0 2006.173.04:34:39.73#ibcon#end of sib2, iclass 7, count 0 2006.173.04:34:39.73#ibcon#*mode == 0, iclass 7, count 0 2006.173.04:34:39.73#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.04:34:39.73#ibcon#[25=USB\r\n] 2006.173.04:34:39.73#ibcon#*before write, iclass 7, count 0 2006.173.04:34:39.73#ibcon#enter sib2, iclass 7, count 0 2006.173.04:34:39.73#ibcon#flushed, iclass 7, count 0 2006.173.04:34:39.73#ibcon#about to write, iclass 7, count 0 2006.173.04:34:39.73#ibcon#wrote, iclass 7, count 0 2006.173.04:34:39.73#ibcon#about to read 3, iclass 7, count 0 2006.173.04:34:39.76#ibcon#read 3, iclass 7, count 0 2006.173.04:34:39.76#ibcon#about to read 4, iclass 7, count 0 2006.173.04:34:39.76#ibcon#read 4, iclass 7, count 0 2006.173.04:34:39.76#ibcon#about to read 5, iclass 7, count 0 2006.173.04:34:39.76#ibcon#read 5, iclass 7, count 0 2006.173.04:34:39.76#ibcon#about to read 6, iclass 7, count 0 2006.173.04:34:39.76#ibcon#read 6, iclass 7, count 0 2006.173.04:34:39.76#ibcon#end of sib2, iclass 7, count 0 2006.173.04:34:39.76#ibcon#*after write, iclass 7, count 0 2006.173.04:34:39.76#ibcon#*before return 0, iclass 7, count 0 2006.173.04:34:39.76#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.04:34:39.76#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.173.04:34:39.76#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.04:34:39.76#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.04:34:39.76$vck44/valo=3,564.99 2006.173.04:34:39.76#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.04:34:39.76#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.04:34:39.76#ibcon#ireg 17 cls_cnt 0 2006.173.04:34:39.76#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.04:34:39.76#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.04:34:39.76#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.04:34:39.76#ibcon#enter wrdev, iclass 11, count 0 2006.173.04:34:39.76#ibcon#first serial, iclass 11, count 0 2006.173.04:34:39.76#ibcon#enter sib2, iclass 11, count 0 2006.173.04:34:39.76#ibcon#flushed, iclass 11, count 0 2006.173.04:34:39.76#ibcon#about to write, iclass 11, count 0 2006.173.04:34:39.76#ibcon#wrote, iclass 11, count 0 2006.173.04:34:39.76#ibcon#about to read 3, iclass 11, count 0 2006.173.04:34:39.78#ibcon#read 3, iclass 11, count 0 2006.173.04:34:39.78#ibcon#about to read 4, iclass 11, count 0 2006.173.04:34:39.78#ibcon#read 4, iclass 11, count 0 2006.173.04:34:39.78#ibcon#about to read 5, iclass 11, count 0 2006.173.04:34:39.78#ibcon#read 5, iclass 11, count 0 2006.173.04:34:39.78#ibcon#about to read 6, iclass 11, count 0 2006.173.04:34:39.78#ibcon#read 6, iclass 11, count 0 2006.173.04:34:39.78#ibcon#end of sib2, iclass 11, count 0 2006.173.04:34:39.78#ibcon#*mode == 0, iclass 11, count 0 2006.173.04:34:39.78#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.04:34:39.78#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.04:34:39.78#ibcon#*before write, iclass 11, count 0 2006.173.04:34:39.78#ibcon#enter sib2, iclass 11, count 0 2006.173.04:34:39.78#ibcon#flushed, iclass 11, count 0 2006.173.04:34:39.78#ibcon#about to write, iclass 11, count 0 2006.173.04:34:39.78#ibcon#wrote, iclass 11, count 0 2006.173.04:34:39.78#ibcon#about to read 3, iclass 11, count 0 2006.173.04:34:39.82#ibcon#read 3, iclass 11, count 0 2006.173.04:34:39.82#ibcon#about to read 4, iclass 11, count 0 2006.173.04:34:39.82#ibcon#read 4, iclass 11, count 0 2006.173.04:34:39.82#ibcon#about to read 5, iclass 11, count 0 2006.173.04:34:39.82#ibcon#read 5, iclass 11, count 0 2006.173.04:34:39.82#ibcon#about to read 6, iclass 11, count 0 2006.173.04:34:39.82#ibcon#read 6, iclass 11, count 0 2006.173.04:34:39.82#ibcon#end of sib2, iclass 11, count 0 2006.173.04:34:39.82#ibcon#*after write, iclass 11, count 0 2006.173.04:34:39.82#ibcon#*before return 0, iclass 11, count 0 2006.173.04:34:39.82#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.04:34:39.82#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.04:34:39.82#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.04:34:39.82#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.04:34:39.82$vck44/va=3,5 2006.173.04:34:39.82#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.173.04:34:39.82#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.173.04:34:39.82#ibcon#ireg 11 cls_cnt 2 2006.173.04:34:39.82#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.04:34:39.88#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.04:34:39.88#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.04:34:39.88#ibcon#enter wrdev, iclass 13, count 2 2006.173.04:34:39.88#ibcon#first serial, iclass 13, count 2 2006.173.04:34:39.88#ibcon#enter sib2, iclass 13, count 2 2006.173.04:34:39.88#ibcon#flushed, iclass 13, count 2 2006.173.04:34:39.88#ibcon#about to write, iclass 13, count 2 2006.173.04:34:39.88#ibcon#wrote, iclass 13, count 2 2006.173.04:34:39.88#ibcon#about to read 3, iclass 13, count 2 2006.173.04:34:39.90#ibcon#read 3, iclass 13, count 2 2006.173.04:34:39.90#ibcon#about to read 4, iclass 13, count 2 2006.173.04:34:39.90#ibcon#read 4, iclass 13, count 2 2006.173.04:34:39.90#ibcon#about to read 5, iclass 13, count 2 2006.173.04:34:39.90#ibcon#read 5, iclass 13, count 2 2006.173.04:34:39.90#ibcon#about to read 6, iclass 13, count 2 2006.173.04:34:39.90#ibcon#read 6, iclass 13, count 2 2006.173.04:34:39.90#ibcon#end of sib2, iclass 13, count 2 2006.173.04:34:39.90#ibcon#*mode == 0, iclass 13, count 2 2006.173.04:34:39.90#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.173.04:34:39.90#ibcon#[25=AT03-05\r\n] 2006.173.04:34:39.90#ibcon#*before write, iclass 13, count 2 2006.173.04:34:39.90#ibcon#enter sib2, iclass 13, count 2 2006.173.04:34:39.90#ibcon#flushed, iclass 13, count 2 2006.173.04:34:39.90#ibcon#about to write, iclass 13, count 2 2006.173.04:34:39.90#ibcon#wrote, iclass 13, count 2 2006.173.04:34:39.90#ibcon#about to read 3, iclass 13, count 2 2006.173.04:34:39.93#ibcon#read 3, iclass 13, count 2 2006.173.04:34:39.93#ibcon#about to read 4, iclass 13, count 2 2006.173.04:34:39.93#ibcon#read 4, iclass 13, count 2 2006.173.04:34:39.93#ibcon#about to read 5, iclass 13, count 2 2006.173.04:34:39.93#ibcon#read 5, iclass 13, count 2 2006.173.04:34:39.93#ibcon#about to read 6, iclass 13, count 2 2006.173.04:34:39.93#ibcon#read 6, iclass 13, count 2 2006.173.04:34:39.93#ibcon#end of sib2, iclass 13, count 2 2006.173.04:34:39.93#ibcon#*after write, iclass 13, count 2 2006.173.04:34:39.93#ibcon#*before return 0, iclass 13, count 2 2006.173.04:34:39.93#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.04:34:39.93#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.173.04:34:39.93#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.173.04:34:39.93#ibcon#ireg 7 cls_cnt 0 2006.173.04:34:39.93#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.04:34:40.05#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.04:34:40.05#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.04:34:40.05#ibcon#enter wrdev, iclass 13, count 0 2006.173.04:34:40.05#ibcon#first serial, iclass 13, count 0 2006.173.04:34:40.05#ibcon#enter sib2, iclass 13, count 0 2006.173.04:34:40.05#ibcon#flushed, iclass 13, count 0 2006.173.04:34:40.05#ibcon#about to write, iclass 13, count 0 2006.173.04:34:40.05#ibcon#wrote, iclass 13, count 0 2006.173.04:34:40.05#ibcon#about to read 3, iclass 13, count 0 2006.173.04:34:40.07#ibcon#read 3, iclass 13, count 0 2006.173.04:34:40.07#ibcon#about to read 4, iclass 13, count 0 2006.173.04:34:40.07#ibcon#read 4, iclass 13, count 0 2006.173.04:34:40.07#ibcon#about to read 5, iclass 13, count 0 2006.173.04:34:40.07#ibcon#read 5, iclass 13, count 0 2006.173.04:34:40.07#ibcon#about to read 6, iclass 13, count 0 2006.173.04:34:40.07#ibcon#read 6, iclass 13, count 0 2006.173.04:34:40.07#ibcon#end of sib2, iclass 13, count 0 2006.173.04:34:40.07#ibcon#*mode == 0, iclass 13, count 0 2006.173.04:34:40.07#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.04:34:40.07#ibcon#[25=USB\r\n] 2006.173.04:34:40.07#ibcon#*before write, iclass 13, count 0 2006.173.04:34:40.07#ibcon#enter sib2, iclass 13, count 0 2006.173.04:34:40.07#ibcon#flushed, iclass 13, count 0 2006.173.04:34:40.07#ibcon#about to write, iclass 13, count 0 2006.173.04:34:40.07#ibcon#wrote, iclass 13, count 0 2006.173.04:34:40.07#ibcon#about to read 3, iclass 13, count 0 2006.173.04:34:40.10#ibcon#read 3, iclass 13, count 0 2006.173.04:34:40.10#ibcon#about to read 4, iclass 13, count 0 2006.173.04:34:40.10#ibcon#read 4, iclass 13, count 0 2006.173.04:34:40.10#ibcon#about to read 5, iclass 13, count 0 2006.173.04:34:40.10#ibcon#read 5, iclass 13, count 0 2006.173.04:34:40.10#ibcon#about to read 6, iclass 13, count 0 2006.173.04:34:40.10#ibcon#read 6, iclass 13, count 0 2006.173.04:34:40.10#ibcon#end of sib2, iclass 13, count 0 2006.173.04:34:40.10#ibcon#*after write, iclass 13, count 0 2006.173.04:34:40.10#ibcon#*before return 0, iclass 13, count 0 2006.173.04:34:40.10#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.04:34:40.10#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.173.04:34:40.10#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.04:34:40.10#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.04:34:40.10$vck44/valo=4,624.99 2006.173.04:34:40.10#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.04:34:40.10#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.04:34:40.10#ibcon#ireg 17 cls_cnt 0 2006.173.04:34:40.10#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.04:34:40.10#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.04:34:40.10#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.04:34:40.10#ibcon#enter wrdev, iclass 15, count 0 2006.173.04:34:40.10#ibcon#first serial, iclass 15, count 0 2006.173.04:34:40.10#ibcon#enter sib2, iclass 15, count 0 2006.173.04:34:40.10#ibcon#flushed, iclass 15, count 0 2006.173.04:34:40.10#ibcon#about to write, iclass 15, count 0 2006.173.04:34:40.10#ibcon#wrote, iclass 15, count 0 2006.173.04:34:40.10#ibcon#about to read 3, iclass 15, count 0 2006.173.04:34:40.12#ibcon#read 3, iclass 15, count 0 2006.173.04:34:40.12#ibcon#about to read 4, iclass 15, count 0 2006.173.04:34:40.12#ibcon#read 4, iclass 15, count 0 2006.173.04:34:40.12#ibcon#about to read 5, iclass 15, count 0 2006.173.04:34:40.12#ibcon#read 5, iclass 15, count 0 2006.173.04:34:40.12#ibcon#about to read 6, iclass 15, count 0 2006.173.04:34:40.12#ibcon#read 6, iclass 15, count 0 2006.173.04:34:40.12#ibcon#end of sib2, iclass 15, count 0 2006.173.04:34:40.12#ibcon#*mode == 0, iclass 15, count 0 2006.173.04:34:40.12#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.04:34:40.12#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.04:34:40.12#ibcon#*before write, iclass 15, count 0 2006.173.04:34:40.12#ibcon#enter sib2, iclass 15, count 0 2006.173.04:34:40.12#ibcon#flushed, iclass 15, count 0 2006.173.04:34:40.12#ibcon#about to write, iclass 15, count 0 2006.173.04:34:40.12#ibcon#wrote, iclass 15, count 0 2006.173.04:34:40.12#ibcon#about to read 3, iclass 15, count 0 2006.173.04:34:40.16#ibcon#read 3, iclass 15, count 0 2006.173.04:34:40.16#ibcon#about to read 4, iclass 15, count 0 2006.173.04:34:40.16#ibcon#read 4, iclass 15, count 0 2006.173.04:34:40.16#ibcon#about to read 5, iclass 15, count 0 2006.173.04:34:40.16#ibcon#read 5, iclass 15, count 0 2006.173.04:34:40.16#ibcon#about to read 6, iclass 15, count 0 2006.173.04:34:40.16#ibcon#read 6, iclass 15, count 0 2006.173.04:34:40.16#ibcon#end of sib2, iclass 15, count 0 2006.173.04:34:40.16#ibcon#*after write, iclass 15, count 0 2006.173.04:34:40.16#ibcon#*before return 0, iclass 15, count 0 2006.173.04:34:40.16#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.04:34:40.16#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.04:34:40.16#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.04:34:40.16#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.04:34:40.16$vck44/va=4,6 2006.173.04:34:40.16#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.04:34:40.16#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.04:34:40.16#ibcon#ireg 11 cls_cnt 2 2006.173.04:34:40.16#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.04:34:40.22#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.04:34:40.22#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.04:34:40.22#ibcon#enter wrdev, iclass 17, count 2 2006.173.04:34:40.22#ibcon#first serial, iclass 17, count 2 2006.173.04:34:40.22#ibcon#enter sib2, iclass 17, count 2 2006.173.04:34:40.22#ibcon#flushed, iclass 17, count 2 2006.173.04:34:40.22#ibcon#about to write, iclass 17, count 2 2006.173.04:34:40.22#ibcon#wrote, iclass 17, count 2 2006.173.04:34:40.22#ibcon#about to read 3, iclass 17, count 2 2006.173.04:34:40.24#ibcon#read 3, iclass 17, count 2 2006.173.04:34:40.24#ibcon#about to read 4, iclass 17, count 2 2006.173.04:34:40.24#ibcon#read 4, iclass 17, count 2 2006.173.04:34:40.24#ibcon#about to read 5, iclass 17, count 2 2006.173.04:34:40.24#ibcon#read 5, iclass 17, count 2 2006.173.04:34:40.24#ibcon#about to read 6, iclass 17, count 2 2006.173.04:34:40.24#ibcon#read 6, iclass 17, count 2 2006.173.04:34:40.24#ibcon#end of sib2, iclass 17, count 2 2006.173.04:34:40.24#ibcon#*mode == 0, iclass 17, count 2 2006.173.04:34:40.24#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.04:34:40.24#ibcon#[25=AT04-06\r\n] 2006.173.04:34:40.24#ibcon#*before write, iclass 17, count 2 2006.173.04:34:40.24#ibcon#enter sib2, iclass 17, count 2 2006.173.04:34:40.24#ibcon#flushed, iclass 17, count 2 2006.173.04:34:40.24#ibcon#about to write, iclass 17, count 2 2006.173.04:34:40.24#ibcon#wrote, iclass 17, count 2 2006.173.04:34:40.24#ibcon#about to read 3, iclass 17, count 2 2006.173.04:34:40.27#ibcon#read 3, iclass 17, count 2 2006.173.04:34:40.27#ibcon#about to read 4, iclass 17, count 2 2006.173.04:34:40.27#ibcon#read 4, iclass 17, count 2 2006.173.04:34:40.27#ibcon#about to read 5, iclass 17, count 2 2006.173.04:34:40.27#ibcon#read 5, iclass 17, count 2 2006.173.04:34:40.27#ibcon#about to read 6, iclass 17, count 2 2006.173.04:34:40.27#ibcon#read 6, iclass 17, count 2 2006.173.04:34:40.27#ibcon#end of sib2, iclass 17, count 2 2006.173.04:34:40.27#ibcon#*after write, iclass 17, count 2 2006.173.04:34:40.27#ibcon#*before return 0, iclass 17, count 2 2006.173.04:34:40.27#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.04:34:40.27#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.04:34:40.27#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.04:34:40.27#ibcon#ireg 7 cls_cnt 0 2006.173.04:34:40.27#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.04:34:40.39#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.04:34:40.39#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.04:34:40.39#ibcon#enter wrdev, iclass 17, count 0 2006.173.04:34:40.39#ibcon#first serial, iclass 17, count 0 2006.173.04:34:40.39#ibcon#enter sib2, iclass 17, count 0 2006.173.04:34:40.39#ibcon#flushed, iclass 17, count 0 2006.173.04:34:40.39#ibcon#about to write, iclass 17, count 0 2006.173.04:34:40.39#ibcon#wrote, iclass 17, count 0 2006.173.04:34:40.39#ibcon#about to read 3, iclass 17, count 0 2006.173.04:34:40.41#ibcon#read 3, iclass 17, count 0 2006.173.04:34:40.41#ibcon#about to read 4, iclass 17, count 0 2006.173.04:34:40.41#ibcon#read 4, iclass 17, count 0 2006.173.04:34:40.41#ibcon#about to read 5, iclass 17, count 0 2006.173.04:34:40.41#ibcon#read 5, iclass 17, count 0 2006.173.04:34:40.41#ibcon#about to read 6, iclass 17, count 0 2006.173.04:34:40.41#ibcon#read 6, iclass 17, count 0 2006.173.04:34:40.41#ibcon#end of sib2, iclass 17, count 0 2006.173.04:34:40.41#ibcon#*mode == 0, iclass 17, count 0 2006.173.04:34:40.41#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.04:34:40.41#ibcon#[25=USB\r\n] 2006.173.04:34:40.41#ibcon#*before write, iclass 17, count 0 2006.173.04:34:40.41#ibcon#enter sib2, iclass 17, count 0 2006.173.04:34:40.41#ibcon#flushed, iclass 17, count 0 2006.173.04:34:40.41#ibcon#about to write, iclass 17, count 0 2006.173.04:34:40.41#ibcon#wrote, iclass 17, count 0 2006.173.04:34:40.41#ibcon#about to read 3, iclass 17, count 0 2006.173.04:34:40.44#ibcon#read 3, iclass 17, count 0 2006.173.04:34:40.44#ibcon#about to read 4, iclass 17, count 0 2006.173.04:34:40.44#ibcon#read 4, iclass 17, count 0 2006.173.04:34:40.44#ibcon#about to read 5, iclass 17, count 0 2006.173.04:34:40.44#ibcon#read 5, iclass 17, count 0 2006.173.04:34:40.44#ibcon#about to read 6, iclass 17, count 0 2006.173.04:34:40.44#ibcon#read 6, iclass 17, count 0 2006.173.04:34:40.44#ibcon#end of sib2, iclass 17, count 0 2006.173.04:34:40.44#ibcon#*after write, iclass 17, count 0 2006.173.04:34:40.44#ibcon#*before return 0, iclass 17, count 0 2006.173.04:34:40.44#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.04:34:40.44#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.04:34:40.44#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.04:34:40.44#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.04:34:40.44$vck44/valo=5,734.99 2006.173.04:34:40.44#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.04:34:40.44#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.04:34:40.44#ibcon#ireg 17 cls_cnt 0 2006.173.04:34:40.44#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.04:34:40.44#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.04:34:40.44#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.04:34:40.44#ibcon#enter wrdev, iclass 19, count 0 2006.173.04:34:40.44#ibcon#first serial, iclass 19, count 0 2006.173.04:34:40.44#ibcon#enter sib2, iclass 19, count 0 2006.173.04:34:40.44#ibcon#flushed, iclass 19, count 0 2006.173.04:34:40.44#ibcon#about to write, iclass 19, count 0 2006.173.04:34:40.44#ibcon#wrote, iclass 19, count 0 2006.173.04:34:40.44#ibcon#about to read 3, iclass 19, count 0 2006.173.04:34:40.46#ibcon#read 3, iclass 19, count 0 2006.173.04:34:40.46#ibcon#about to read 4, iclass 19, count 0 2006.173.04:34:40.46#ibcon#read 4, iclass 19, count 0 2006.173.04:34:40.46#ibcon#about to read 5, iclass 19, count 0 2006.173.04:34:40.46#ibcon#read 5, iclass 19, count 0 2006.173.04:34:40.46#ibcon#about to read 6, iclass 19, count 0 2006.173.04:34:40.46#ibcon#read 6, iclass 19, count 0 2006.173.04:34:40.46#ibcon#end of sib2, iclass 19, count 0 2006.173.04:34:40.46#ibcon#*mode == 0, iclass 19, count 0 2006.173.04:34:40.46#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.04:34:40.46#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.04:34:40.46#ibcon#*before write, iclass 19, count 0 2006.173.04:34:40.46#ibcon#enter sib2, iclass 19, count 0 2006.173.04:34:40.46#ibcon#flushed, iclass 19, count 0 2006.173.04:34:40.46#ibcon#about to write, iclass 19, count 0 2006.173.04:34:40.46#ibcon#wrote, iclass 19, count 0 2006.173.04:34:40.46#ibcon#about to read 3, iclass 19, count 0 2006.173.04:34:40.50#ibcon#read 3, iclass 19, count 0 2006.173.04:34:40.50#ibcon#about to read 4, iclass 19, count 0 2006.173.04:34:40.50#ibcon#read 4, iclass 19, count 0 2006.173.04:34:40.50#ibcon#about to read 5, iclass 19, count 0 2006.173.04:34:40.50#ibcon#read 5, iclass 19, count 0 2006.173.04:34:40.50#ibcon#about to read 6, iclass 19, count 0 2006.173.04:34:40.50#ibcon#read 6, iclass 19, count 0 2006.173.04:34:40.50#ibcon#end of sib2, iclass 19, count 0 2006.173.04:34:40.50#ibcon#*after write, iclass 19, count 0 2006.173.04:34:40.50#ibcon#*before return 0, iclass 19, count 0 2006.173.04:34:40.50#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.04:34:40.50#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.04:34:40.50#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.04:34:40.50#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.04:34:40.50$vck44/va=5,4 2006.173.04:34:40.50#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.04:34:40.50#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.04:34:40.50#ibcon#ireg 11 cls_cnt 2 2006.173.04:34:40.50#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.04:34:40.56#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.04:34:40.56#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.04:34:40.56#ibcon#enter wrdev, iclass 21, count 2 2006.173.04:34:40.56#ibcon#first serial, iclass 21, count 2 2006.173.04:34:40.56#ibcon#enter sib2, iclass 21, count 2 2006.173.04:34:40.56#ibcon#flushed, iclass 21, count 2 2006.173.04:34:40.56#ibcon#about to write, iclass 21, count 2 2006.173.04:34:40.56#ibcon#wrote, iclass 21, count 2 2006.173.04:34:40.56#ibcon#about to read 3, iclass 21, count 2 2006.173.04:34:40.58#ibcon#read 3, iclass 21, count 2 2006.173.04:34:40.58#ibcon#about to read 4, iclass 21, count 2 2006.173.04:34:40.58#ibcon#read 4, iclass 21, count 2 2006.173.04:34:40.58#ibcon#about to read 5, iclass 21, count 2 2006.173.04:34:40.58#ibcon#read 5, iclass 21, count 2 2006.173.04:34:40.58#ibcon#about to read 6, iclass 21, count 2 2006.173.04:34:40.58#ibcon#read 6, iclass 21, count 2 2006.173.04:34:40.58#ibcon#end of sib2, iclass 21, count 2 2006.173.04:34:40.58#ibcon#*mode == 0, iclass 21, count 2 2006.173.04:34:40.58#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.04:34:40.58#ibcon#[25=AT05-04\r\n] 2006.173.04:34:40.58#ibcon#*before write, iclass 21, count 2 2006.173.04:34:40.58#ibcon#enter sib2, iclass 21, count 2 2006.173.04:34:40.58#ibcon#flushed, iclass 21, count 2 2006.173.04:34:40.58#ibcon#about to write, iclass 21, count 2 2006.173.04:34:40.58#ibcon#wrote, iclass 21, count 2 2006.173.04:34:40.58#ibcon#about to read 3, iclass 21, count 2 2006.173.04:34:40.61#ibcon#read 3, iclass 21, count 2 2006.173.04:34:40.61#ibcon#about to read 4, iclass 21, count 2 2006.173.04:34:40.61#ibcon#read 4, iclass 21, count 2 2006.173.04:34:40.61#ibcon#about to read 5, iclass 21, count 2 2006.173.04:34:40.61#ibcon#read 5, iclass 21, count 2 2006.173.04:34:40.61#ibcon#about to read 6, iclass 21, count 2 2006.173.04:34:40.61#ibcon#read 6, iclass 21, count 2 2006.173.04:34:40.61#ibcon#end of sib2, iclass 21, count 2 2006.173.04:34:40.61#ibcon#*after write, iclass 21, count 2 2006.173.04:34:40.61#ibcon#*before return 0, iclass 21, count 2 2006.173.04:34:40.61#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.04:34:40.61#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.04:34:40.61#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.04:34:40.61#ibcon#ireg 7 cls_cnt 0 2006.173.04:34:40.61#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.04:34:40.73#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.04:34:40.73#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.04:34:40.73#ibcon#enter wrdev, iclass 21, count 0 2006.173.04:34:40.73#ibcon#first serial, iclass 21, count 0 2006.173.04:34:40.73#ibcon#enter sib2, iclass 21, count 0 2006.173.04:34:40.73#ibcon#flushed, iclass 21, count 0 2006.173.04:34:40.73#ibcon#about to write, iclass 21, count 0 2006.173.04:34:40.73#ibcon#wrote, iclass 21, count 0 2006.173.04:34:40.73#ibcon#about to read 3, iclass 21, count 0 2006.173.04:34:40.75#ibcon#read 3, iclass 21, count 0 2006.173.04:34:40.75#ibcon#about to read 4, iclass 21, count 0 2006.173.04:34:40.75#ibcon#read 4, iclass 21, count 0 2006.173.04:34:40.75#ibcon#about to read 5, iclass 21, count 0 2006.173.04:34:40.75#ibcon#read 5, iclass 21, count 0 2006.173.04:34:40.75#ibcon#about to read 6, iclass 21, count 0 2006.173.04:34:40.75#ibcon#read 6, iclass 21, count 0 2006.173.04:34:40.75#ibcon#end of sib2, iclass 21, count 0 2006.173.04:34:40.75#ibcon#*mode == 0, iclass 21, count 0 2006.173.04:34:40.75#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.04:34:40.75#ibcon#[25=USB\r\n] 2006.173.04:34:40.75#ibcon#*before write, iclass 21, count 0 2006.173.04:34:40.75#ibcon#enter sib2, iclass 21, count 0 2006.173.04:34:40.75#ibcon#flushed, iclass 21, count 0 2006.173.04:34:40.75#ibcon#about to write, iclass 21, count 0 2006.173.04:34:40.75#ibcon#wrote, iclass 21, count 0 2006.173.04:34:40.75#ibcon#about to read 3, iclass 21, count 0 2006.173.04:34:40.78#ibcon#read 3, iclass 21, count 0 2006.173.04:34:40.78#ibcon#about to read 4, iclass 21, count 0 2006.173.04:34:40.78#ibcon#read 4, iclass 21, count 0 2006.173.04:34:40.78#ibcon#about to read 5, iclass 21, count 0 2006.173.04:34:40.78#ibcon#read 5, iclass 21, count 0 2006.173.04:34:40.78#ibcon#about to read 6, iclass 21, count 0 2006.173.04:34:40.78#ibcon#read 6, iclass 21, count 0 2006.173.04:34:40.78#ibcon#end of sib2, iclass 21, count 0 2006.173.04:34:40.78#ibcon#*after write, iclass 21, count 0 2006.173.04:34:40.78#ibcon#*before return 0, iclass 21, count 0 2006.173.04:34:40.78#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.04:34:40.78#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.04:34:40.78#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.04:34:40.78#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.04:34:40.78$vck44/valo=6,814.99 2006.173.04:34:40.78#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.04:34:40.78#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.04:34:40.78#ibcon#ireg 17 cls_cnt 0 2006.173.04:34:40.78#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.04:34:40.78#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.04:34:40.78#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.04:34:40.78#ibcon#enter wrdev, iclass 23, count 0 2006.173.04:34:40.78#ibcon#first serial, iclass 23, count 0 2006.173.04:34:40.78#ibcon#enter sib2, iclass 23, count 0 2006.173.04:34:40.78#ibcon#flushed, iclass 23, count 0 2006.173.04:34:40.78#ibcon#about to write, iclass 23, count 0 2006.173.04:34:40.78#ibcon#wrote, iclass 23, count 0 2006.173.04:34:40.78#ibcon#about to read 3, iclass 23, count 0 2006.173.04:34:40.80#ibcon#read 3, iclass 23, count 0 2006.173.04:34:40.80#ibcon#about to read 4, iclass 23, count 0 2006.173.04:34:40.80#ibcon#read 4, iclass 23, count 0 2006.173.04:34:40.80#ibcon#about to read 5, iclass 23, count 0 2006.173.04:34:40.80#ibcon#read 5, iclass 23, count 0 2006.173.04:34:40.80#ibcon#about to read 6, iclass 23, count 0 2006.173.04:34:40.80#ibcon#read 6, iclass 23, count 0 2006.173.04:34:40.80#ibcon#end of sib2, iclass 23, count 0 2006.173.04:34:40.80#ibcon#*mode == 0, iclass 23, count 0 2006.173.04:34:40.80#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.04:34:40.80#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.04:34:40.80#ibcon#*before write, iclass 23, count 0 2006.173.04:34:40.80#ibcon#enter sib2, iclass 23, count 0 2006.173.04:34:40.80#ibcon#flushed, iclass 23, count 0 2006.173.04:34:40.80#ibcon#about to write, iclass 23, count 0 2006.173.04:34:40.80#ibcon#wrote, iclass 23, count 0 2006.173.04:34:40.80#ibcon#about to read 3, iclass 23, count 0 2006.173.04:34:40.84#ibcon#read 3, iclass 23, count 0 2006.173.04:34:40.84#ibcon#about to read 4, iclass 23, count 0 2006.173.04:34:40.84#ibcon#read 4, iclass 23, count 0 2006.173.04:34:40.84#ibcon#about to read 5, iclass 23, count 0 2006.173.04:34:40.84#ibcon#read 5, iclass 23, count 0 2006.173.04:34:40.84#ibcon#about to read 6, iclass 23, count 0 2006.173.04:34:40.84#ibcon#read 6, iclass 23, count 0 2006.173.04:34:40.84#ibcon#end of sib2, iclass 23, count 0 2006.173.04:34:40.84#ibcon#*after write, iclass 23, count 0 2006.173.04:34:40.84#ibcon#*before return 0, iclass 23, count 0 2006.173.04:34:40.84#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.04:34:40.84#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.04:34:40.84#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.04:34:40.84#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.04:34:40.84$vck44/va=6,3 2006.173.04:34:40.84#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.04:34:40.84#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.04:34:40.84#ibcon#ireg 11 cls_cnt 2 2006.173.04:34:40.84#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.04:34:40.90#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.04:34:40.90#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.04:34:40.90#ibcon#enter wrdev, iclass 25, count 2 2006.173.04:34:40.90#ibcon#first serial, iclass 25, count 2 2006.173.04:34:40.90#ibcon#enter sib2, iclass 25, count 2 2006.173.04:34:40.90#ibcon#flushed, iclass 25, count 2 2006.173.04:34:40.90#ibcon#about to write, iclass 25, count 2 2006.173.04:34:40.90#ibcon#wrote, iclass 25, count 2 2006.173.04:34:40.90#ibcon#about to read 3, iclass 25, count 2 2006.173.04:34:40.92#ibcon#read 3, iclass 25, count 2 2006.173.04:34:40.92#ibcon#about to read 4, iclass 25, count 2 2006.173.04:34:40.92#ibcon#read 4, iclass 25, count 2 2006.173.04:34:40.92#ibcon#about to read 5, iclass 25, count 2 2006.173.04:34:40.92#ibcon#read 5, iclass 25, count 2 2006.173.04:34:40.92#ibcon#about to read 6, iclass 25, count 2 2006.173.04:34:40.92#ibcon#read 6, iclass 25, count 2 2006.173.04:34:40.92#ibcon#end of sib2, iclass 25, count 2 2006.173.04:34:40.92#ibcon#*mode == 0, iclass 25, count 2 2006.173.04:34:40.92#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.04:34:40.92#ibcon#[25=AT06-03\r\n] 2006.173.04:34:40.92#ibcon#*before write, iclass 25, count 2 2006.173.04:34:40.92#ibcon#enter sib2, iclass 25, count 2 2006.173.04:34:40.92#ibcon#flushed, iclass 25, count 2 2006.173.04:34:40.92#ibcon#about to write, iclass 25, count 2 2006.173.04:34:40.92#ibcon#wrote, iclass 25, count 2 2006.173.04:34:40.92#ibcon#about to read 3, iclass 25, count 2 2006.173.04:34:40.95#ibcon#read 3, iclass 25, count 2 2006.173.04:34:40.95#ibcon#about to read 4, iclass 25, count 2 2006.173.04:34:40.95#ibcon#read 4, iclass 25, count 2 2006.173.04:34:40.95#ibcon#about to read 5, iclass 25, count 2 2006.173.04:34:40.95#ibcon#read 5, iclass 25, count 2 2006.173.04:34:40.95#ibcon#about to read 6, iclass 25, count 2 2006.173.04:34:40.95#ibcon#read 6, iclass 25, count 2 2006.173.04:34:40.95#ibcon#end of sib2, iclass 25, count 2 2006.173.04:34:40.95#ibcon#*after write, iclass 25, count 2 2006.173.04:34:40.95#ibcon#*before return 0, iclass 25, count 2 2006.173.04:34:40.95#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.04:34:40.95#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.04:34:40.95#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.04:34:40.95#ibcon#ireg 7 cls_cnt 0 2006.173.04:34:40.95#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.04:34:41.07#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.04:34:41.07#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.04:34:41.07#ibcon#enter wrdev, iclass 25, count 0 2006.173.04:34:41.07#ibcon#first serial, iclass 25, count 0 2006.173.04:34:41.07#ibcon#enter sib2, iclass 25, count 0 2006.173.04:34:41.07#ibcon#flushed, iclass 25, count 0 2006.173.04:34:41.07#ibcon#about to write, iclass 25, count 0 2006.173.04:34:41.07#ibcon#wrote, iclass 25, count 0 2006.173.04:34:41.07#ibcon#about to read 3, iclass 25, count 0 2006.173.04:34:41.09#ibcon#read 3, iclass 25, count 0 2006.173.04:34:41.09#ibcon#about to read 4, iclass 25, count 0 2006.173.04:34:41.09#ibcon#read 4, iclass 25, count 0 2006.173.04:34:41.09#ibcon#about to read 5, iclass 25, count 0 2006.173.04:34:41.09#ibcon#read 5, iclass 25, count 0 2006.173.04:34:41.09#ibcon#about to read 6, iclass 25, count 0 2006.173.04:34:41.09#ibcon#read 6, iclass 25, count 0 2006.173.04:34:41.09#ibcon#end of sib2, iclass 25, count 0 2006.173.04:34:41.09#ibcon#*mode == 0, iclass 25, count 0 2006.173.04:34:41.09#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.04:34:41.09#ibcon#[25=USB\r\n] 2006.173.04:34:41.09#ibcon#*before write, iclass 25, count 0 2006.173.04:34:41.09#ibcon#enter sib2, iclass 25, count 0 2006.173.04:34:41.09#ibcon#flushed, iclass 25, count 0 2006.173.04:34:41.09#ibcon#about to write, iclass 25, count 0 2006.173.04:34:41.09#ibcon#wrote, iclass 25, count 0 2006.173.04:34:41.09#ibcon#about to read 3, iclass 25, count 0 2006.173.04:34:41.12#ibcon#read 3, iclass 25, count 0 2006.173.04:34:41.12#ibcon#about to read 4, iclass 25, count 0 2006.173.04:34:41.12#ibcon#read 4, iclass 25, count 0 2006.173.04:34:41.12#ibcon#about to read 5, iclass 25, count 0 2006.173.04:34:41.12#ibcon#read 5, iclass 25, count 0 2006.173.04:34:41.12#ibcon#about to read 6, iclass 25, count 0 2006.173.04:34:41.12#ibcon#read 6, iclass 25, count 0 2006.173.04:34:41.12#ibcon#end of sib2, iclass 25, count 0 2006.173.04:34:41.12#ibcon#*after write, iclass 25, count 0 2006.173.04:34:41.12#ibcon#*before return 0, iclass 25, count 0 2006.173.04:34:41.12#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.04:34:41.12#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.04:34:41.12#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.04:34:41.12#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.04:34:41.12$vck44/valo=7,864.99 2006.173.04:34:41.12#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.04:34:41.12#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.04:34:41.12#ibcon#ireg 17 cls_cnt 0 2006.173.04:34:41.12#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.04:34:41.12#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.04:34:41.12#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.04:34:41.12#ibcon#enter wrdev, iclass 27, count 0 2006.173.04:34:41.12#ibcon#first serial, iclass 27, count 0 2006.173.04:34:41.12#ibcon#enter sib2, iclass 27, count 0 2006.173.04:34:41.12#ibcon#flushed, iclass 27, count 0 2006.173.04:34:41.12#ibcon#about to write, iclass 27, count 0 2006.173.04:34:41.12#ibcon#wrote, iclass 27, count 0 2006.173.04:34:41.12#ibcon#about to read 3, iclass 27, count 0 2006.173.04:34:41.14#ibcon#read 3, iclass 27, count 0 2006.173.04:34:41.14#ibcon#about to read 4, iclass 27, count 0 2006.173.04:34:41.14#ibcon#read 4, iclass 27, count 0 2006.173.04:34:41.14#ibcon#about to read 5, iclass 27, count 0 2006.173.04:34:41.14#ibcon#read 5, iclass 27, count 0 2006.173.04:34:41.14#ibcon#about to read 6, iclass 27, count 0 2006.173.04:34:41.14#ibcon#read 6, iclass 27, count 0 2006.173.04:34:41.14#ibcon#end of sib2, iclass 27, count 0 2006.173.04:34:41.14#ibcon#*mode == 0, iclass 27, count 0 2006.173.04:34:41.14#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.04:34:41.14#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.04:34:41.14#ibcon#*before write, iclass 27, count 0 2006.173.04:34:41.14#ibcon#enter sib2, iclass 27, count 0 2006.173.04:34:41.14#ibcon#flushed, iclass 27, count 0 2006.173.04:34:41.14#ibcon#about to write, iclass 27, count 0 2006.173.04:34:41.14#ibcon#wrote, iclass 27, count 0 2006.173.04:34:41.14#ibcon#about to read 3, iclass 27, count 0 2006.173.04:34:41.18#ibcon#read 3, iclass 27, count 0 2006.173.04:34:41.18#ibcon#about to read 4, iclass 27, count 0 2006.173.04:34:41.18#ibcon#read 4, iclass 27, count 0 2006.173.04:34:41.18#ibcon#about to read 5, iclass 27, count 0 2006.173.04:34:41.18#ibcon#read 5, iclass 27, count 0 2006.173.04:34:41.18#ibcon#about to read 6, iclass 27, count 0 2006.173.04:34:41.18#ibcon#read 6, iclass 27, count 0 2006.173.04:34:41.18#ibcon#end of sib2, iclass 27, count 0 2006.173.04:34:41.18#ibcon#*after write, iclass 27, count 0 2006.173.04:34:41.18#ibcon#*before return 0, iclass 27, count 0 2006.173.04:34:41.18#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.04:34:41.18#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.04:34:41.18#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.04:34:41.18#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.04:34:41.18$vck44/va=7,4 2006.173.04:34:41.18#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.04:34:41.18#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.04:34:41.18#ibcon#ireg 11 cls_cnt 2 2006.173.04:34:41.18#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.04:34:41.24#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.04:34:41.24#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.04:34:41.24#ibcon#enter wrdev, iclass 29, count 2 2006.173.04:34:41.24#ibcon#first serial, iclass 29, count 2 2006.173.04:34:41.24#ibcon#enter sib2, iclass 29, count 2 2006.173.04:34:41.24#ibcon#flushed, iclass 29, count 2 2006.173.04:34:41.24#ibcon#about to write, iclass 29, count 2 2006.173.04:34:41.24#ibcon#wrote, iclass 29, count 2 2006.173.04:34:41.24#ibcon#about to read 3, iclass 29, count 2 2006.173.04:34:41.26#ibcon#read 3, iclass 29, count 2 2006.173.04:34:41.26#ibcon#about to read 4, iclass 29, count 2 2006.173.04:34:41.26#ibcon#read 4, iclass 29, count 2 2006.173.04:34:41.26#ibcon#about to read 5, iclass 29, count 2 2006.173.04:34:41.26#ibcon#read 5, iclass 29, count 2 2006.173.04:34:41.26#ibcon#about to read 6, iclass 29, count 2 2006.173.04:34:41.26#ibcon#read 6, iclass 29, count 2 2006.173.04:34:41.26#ibcon#end of sib2, iclass 29, count 2 2006.173.04:34:41.26#ibcon#*mode == 0, iclass 29, count 2 2006.173.04:34:41.26#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.04:34:41.26#ibcon#[25=AT07-04\r\n] 2006.173.04:34:41.26#ibcon#*before write, iclass 29, count 2 2006.173.04:34:41.26#ibcon#enter sib2, iclass 29, count 2 2006.173.04:34:41.26#ibcon#flushed, iclass 29, count 2 2006.173.04:34:41.26#ibcon#about to write, iclass 29, count 2 2006.173.04:34:41.26#ibcon#wrote, iclass 29, count 2 2006.173.04:34:41.26#ibcon#about to read 3, iclass 29, count 2 2006.173.04:34:41.29#ibcon#read 3, iclass 29, count 2 2006.173.04:34:41.29#ibcon#about to read 4, iclass 29, count 2 2006.173.04:34:41.29#ibcon#read 4, iclass 29, count 2 2006.173.04:34:41.29#ibcon#about to read 5, iclass 29, count 2 2006.173.04:34:41.29#ibcon#read 5, iclass 29, count 2 2006.173.04:34:41.29#ibcon#about to read 6, iclass 29, count 2 2006.173.04:34:41.29#ibcon#read 6, iclass 29, count 2 2006.173.04:34:41.29#ibcon#end of sib2, iclass 29, count 2 2006.173.04:34:41.29#ibcon#*after write, iclass 29, count 2 2006.173.04:34:41.29#ibcon#*before return 0, iclass 29, count 2 2006.173.04:34:41.29#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.04:34:41.29#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.04:34:41.29#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.04:34:41.29#ibcon#ireg 7 cls_cnt 0 2006.173.04:34:41.29#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.04:34:41.41#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.04:34:41.41#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.04:34:41.41#ibcon#enter wrdev, iclass 29, count 0 2006.173.04:34:41.41#ibcon#first serial, iclass 29, count 0 2006.173.04:34:41.41#ibcon#enter sib2, iclass 29, count 0 2006.173.04:34:41.41#ibcon#flushed, iclass 29, count 0 2006.173.04:34:41.41#ibcon#about to write, iclass 29, count 0 2006.173.04:34:41.41#ibcon#wrote, iclass 29, count 0 2006.173.04:34:41.41#ibcon#about to read 3, iclass 29, count 0 2006.173.04:34:41.43#ibcon#read 3, iclass 29, count 0 2006.173.04:34:41.43#ibcon#about to read 4, iclass 29, count 0 2006.173.04:34:41.43#ibcon#read 4, iclass 29, count 0 2006.173.04:34:41.43#ibcon#about to read 5, iclass 29, count 0 2006.173.04:34:41.43#ibcon#read 5, iclass 29, count 0 2006.173.04:34:41.43#ibcon#about to read 6, iclass 29, count 0 2006.173.04:34:41.43#ibcon#read 6, iclass 29, count 0 2006.173.04:34:41.43#ibcon#end of sib2, iclass 29, count 0 2006.173.04:34:41.43#ibcon#*mode == 0, iclass 29, count 0 2006.173.04:34:41.43#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.04:34:41.43#ibcon#[25=USB\r\n] 2006.173.04:34:41.43#ibcon#*before write, iclass 29, count 0 2006.173.04:34:41.43#ibcon#enter sib2, iclass 29, count 0 2006.173.04:34:41.43#ibcon#flushed, iclass 29, count 0 2006.173.04:34:41.43#ibcon#about to write, iclass 29, count 0 2006.173.04:34:41.43#ibcon#wrote, iclass 29, count 0 2006.173.04:34:41.43#ibcon#about to read 3, iclass 29, count 0 2006.173.04:34:41.46#ibcon#read 3, iclass 29, count 0 2006.173.04:34:41.46#ibcon#about to read 4, iclass 29, count 0 2006.173.04:34:41.46#ibcon#read 4, iclass 29, count 0 2006.173.04:34:41.46#ibcon#about to read 5, iclass 29, count 0 2006.173.04:34:41.46#ibcon#read 5, iclass 29, count 0 2006.173.04:34:41.46#ibcon#about to read 6, iclass 29, count 0 2006.173.04:34:41.46#ibcon#read 6, iclass 29, count 0 2006.173.04:34:41.46#ibcon#end of sib2, iclass 29, count 0 2006.173.04:34:41.46#ibcon#*after write, iclass 29, count 0 2006.173.04:34:41.46#ibcon#*before return 0, iclass 29, count 0 2006.173.04:34:41.46#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.04:34:41.46#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.04:34:41.46#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.04:34:41.46#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.04:34:41.46$vck44/valo=8,884.99 2006.173.04:34:41.46#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.04:34:41.46#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.04:34:41.46#ibcon#ireg 17 cls_cnt 0 2006.173.04:34:41.46#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.04:34:41.46#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.04:34:41.46#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.04:34:41.46#ibcon#enter wrdev, iclass 31, count 0 2006.173.04:34:41.46#ibcon#first serial, iclass 31, count 0 2006.173.04:34:41.46#ibcon#enter sib2, iclass 31, count 0 2006.173.04:34:41.46#ibcon#flushed, iclass 31, count 0 2006.173.04:34:41.46#ibcon#about to write, iclass 31, count 0 2006.173.04:34:41.46#ibcon#wrote, iclass 31, count 0 2006.173.04:34:41.46#ibcon#about to read 3, iclass 31, count 0 2006.173.04:34:41.48#ibcon#read 3, iclass 31, count 0 2006.173.04:34:41.48#ibcon#about to read 4, iclass 31, count 0 2006.173.04:34:41.48#ibcon#read 4, iclass 31, count 0 2006.173.04:34:41.48#ibcon#about to read 5, iclass 31, count 0 2006.173.04:34:41.48#ibcon#read 5, iclass 31, count 0 2006.173.04:34:41.48#ibcon#about to read 6, iclass 31, count 0 2006.173.04:34:41.48#ibcon#read 6, iclass 31, count 0 2006.173.04:34:41.48#ibcon#end of sib2, iclass 31, count 0 2006.173.04:34:41.48#ibcon#*mode == 0, iclass 31, count 0 2006.173.04:34:41.48#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.04:34:41.48#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.04:34:41.48#ibcon#*before write, iclass 31, count 0 2006.173.04:34:41.48#ibcon#enter sib2, iclass 31, count 0 2006.173.04:34:41.48#ibcon#flushed, iclass 31, count 0 2006.173.04:34:41.48#ibcon#about to write, iclass 31, count 0 2006.173.04:34:41.48#ibcon#wrote, iclass 31, count 0 2006.173.04:34:41.48#ibcon#about to read 3, iclass 31, count 0 2006.173.04:34:41.52#ibcon#read 3, iclass 31, count 0 2006.173.04:34:41.52#ibcon#about to read 4, iclass 31, count 0 2006.173.04:34:41.52#ibcon#read 4, iclass 31, count 0 2006.173.04:34:41.52#ibcon#about to read 5, iclass 31, count 0 2006.173.04:34:41.52#ibcon#read 5, iclass 31, count 0 2006.173.04:34:41.52#ibcon#about to read 6, iclass 31, count 0 2006.173.04:34:41.52#ibcon#read 6, iclass 31, count 0 2006.173.04:34:41.52#ibcon#end of sib2, iclass 31, count 0 2006.173.04:34:41.52#ibcon#*after write, iclass 31, count 0 2006.173.04:34:41.52#ibcon#*before return 0, iclass 31, count 0 2006.173.04:34:41.52#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.04:34:41.52#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.04:34:41.52#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.04:34:41.52#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.04:34:41.52$vck44/va=8,4 2006.173.04:34:41.52#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.173.04:34:41.52#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.173.04:34:41.52#ibcon#ireg 11 cls_cnt 2 2006.173.04:34:41.52#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.04:34:41.58#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.04:34:41.58#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.04:34:41.58#ibcon#enter wrdev, iclass 33, count 2 2006.173.04:34:41.58#ibcon#first serial, iclass 33, count 2 2006.173.04:34:41.58#ibcon#enter sib2, iclass 33, count 2 2006.173.04:34:41.58#ibcon#flushed, iclass 33, count 2 2006.173.04:34:41.58#ibcon#about to write, iclass 33, count 2 2006.173.04:34:41.58#ibcon#wrote, iclass 33, count 2 2006.173.04:34:41.58#ibcon#about to read 3, iclass 33, count 2 2006.173.04:34:41.60#ibcon#read 3, iclass 33, count 2 2006.173.04:34:41.60#ibcon#about to read 4, iclass 33, count 2 2006.173.04:34:41.60#ibcon#read 4, iclass 33, count 2 2006.173.04:34:41.60#ibcon#about to read 5, iclass 33, count 2 2006.173.04:34:41.60#ibcon#read 5, iclass 33, count 2 2006.173.04:34:41.60#ibcon#about to read 6, iclass 33, count 2 2006.173.04:34:41.60#ibcon#read 6, iclass 33, count 2 2006.173.04:34:41.60#ibcon#end of sib2, iclass 33, count 2 2006.173.04:34:41.60#ibcon#*mode == 0, iclass 33, count 2 2006.173.04:34:41.60#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.173.04:34:41.60#ibcon#[25=AT08-04\r\n] 2006.173.04:34:41.60#ibcon#*before write, iclass 33, count 2 2006.173.04:34:41.60#ibcon#enter sib2, iclass 33, count 2 2006.173.04:34:41.60#ibcon#flushed, iclass 33, count 2 2006.173.04:34:41.60#ibcon#about to write, iclass 33, count 2 2006.173.04:34:41.60#ibcon#wrote, iclass 33, count 2 2006.173.04:34:41.60#ibcon#about to read 3, iclass 33, count 2 2006.173.04:34:41.63#ibcon#read 3, iclass 33, count 2 2006.173.04:34:41.63#ibcon#about to read 4, iclass 33, count 2 2006.173.04:34:41.63#ibcon#read 4, iclass 33, count 2 2006.173.04:34:41.63#ibcon#about to read 5, iclass 33, count 2 2006.173.04:34:41.63#ibcon#read 5, iclass 33, count 2 2006.173.04:34:41.63#ibcon#about to read 6, iclass 33, count 2 2006.173.04:34:41.63#ibcon#read 6, iclass 33, count 2 2006.173.04:34:41.63#ibcon#end of sib2, iclass 33, count 2 2006.173.04:34:41.63#ibcon#*after write, iclass 33, count 2 2006.173.04:34:41.63#ibcon#*before return 0, iclass 33, count 2 2006.173.04:34:41.63#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.04:34:41.63#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.173.04:34:41.63#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.173.04:34:41.63#ibcon#ireg 7 cls_cnt 0 2006.173.04:34:41.63#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.04:34:41.75#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.04:34:41.75#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.04:34:41.75#ibcon#enter wrdev, iclass 33, count 0 2006.173.04:34:41.75#ibcon#first serial, iclass 33, count 0 2006.173.04:34:41.75#ibcon#enter sib2, iclass 33, count 0 2006.173.04:34:41.75#ibcon#flushed, iclass 33, count 0 2006.173.04:34:41.75#ibcon#about to write, iclass 33, count 0 2006.173.04:34:41.75#ibcon#wrote, iclass 33, count 0 2006.173.04:34:41.75#ibcon#about to read 3, iclass 33, count 0 2006.173.04:34:41.77#ibcon#read 3, iclass 33, count 0 2006.173.04:34:41.77#ibcon#about to read 4, iclass 33, count 0 2006.173.04:34:41.77#ibcon#read 4, iclass 33, count 0 2006.173.04:34:41.77#ibcon#about to read 5, iclass 33, count 0 2006.173.04:34:41.77#ibcon#read 5, iclass 33, count 0 2006.173.04:34:41.77#ibcon#about to read 6, iclass 33, count 0 2006.173.04:34:41.77#ibcon#read 6, iclass 33, count 0 2006.173.04:34:41.77#ibcon#end of sib2, iclass 33, count 0 2006.173.04:34:41.77#ibcon#*mode == 0, iclass 33, count 0 2006.173.04:34:41.77#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.04:34:41.77#ibcon#[25=USB\r\n] 2006.173.04:34:41.77#ibcon#*before write, iclass 33, count 0 2006.173.04:34:41.77#ibcon#enter sib2, iclass 33, count 0 2006.173.04:34:41.77#ibcon#flushed, iclass 33, count 0 2006.173.04:34:41.77#ibcon#about to write, iclass 33, count 0 2006.173.04:34:41.77#ibcon#wrote, iclass 33, count 0 2006.173.04:34:41.77#ibcon#about to read 3, iclass 33, count 0 2006.173.04:34:41.80#ibcon#read 3, iclass 33, count 0 2006.173.04:34:41.80#ibcon#about to read 4, iclass 33, count 0 2006.173.04:34:41.80#ibcon#read 4, iclass 33, count 0 2006.173.04:34:41.80#ibcon#about to read 5, iclass 33, count 0 2006.173.04:34:41.80#ibcon#read 5, iclass 33, count 0 2006.173.04:34:41.80#ibcon#about to read 6, iclass 33, count 0 2006.173.04:34:41.80#ibcon#read 6, iclass 33, count 0 2006.173.04:34:41.80#ibcon#end of sib2, iclass 33, count 0 2006.173.04:34:41.80#ibcon#*after write, iclass 33, count 0 2006.173.04:34:41.80#ibcon#*before return 0, iclass 33, count 0 2006.173.04:34:41.80#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.04:34:41.80#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.173.04:34:41.80#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.04:34:41.80#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.04:34:41.80$vck44/vblo=1,629.99 2006.173.04:34:41.80#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.04:34:41.80#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.04:34:41.80#ibcon#ireg 17 cls_cnt 0 2006.173.04:34:41.80#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.04:34:41.80#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.04:34:41.80#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.04:34:41.80#ibcon#enter wrdev, iclass 35, count 0 2006.173.04:34:41.80#ibcon#first serial, iclass 35, count 0 2006.173.04:34:41.80#ibcon#enter sib2, iclass 35, count 0 2006.173.04:34:41.80#ibcon#flushed, iclass 35, count 0 2006.173.04:34:41.80#ibcon#about to write, iclass 35, count 0 2006.173.04:34:41.80#ibcon#wrote, iclass 35, count 0 2006.173.04:34:41.80#ibcon#about to read 3, iclass 35, count 0 2006.173.04:34:41.82#ibcon#read 3, iclass 35, count 0 2006.173.04:34:41.82#ibcon#about to read 4, iclass 35, count 0 2006.173.04:34:41.82#ibcon#read 4, iclass 35, count 0 2006.173.04:34:41.82#ibcon#about to read 5, iclass 35, count 0 2006.173.04:34:41.82#ibcon#read 5, iclass 35, count 0 2006.173.04:34:41.82#ibcon#about to read 6, iclass 35, count 0 2006.173.04:34:41.82#ibcon#read 6, iclass 35, count 0 2006.173.04:34:41.82#ibcon#end of sib2, iclass 35, count 0 2006.173.04:34:41.82#ibcon#*mode == 0, iclass 35, count 0 2006.173.04:34:41.82#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.04:34:41.82#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.04:34:41.82#ibcon#*before write, iclass 35, count 0 2006.173.04:34:41.82#ibcon#enter sib2, iclass 35, count 0 2006.173.04:34:41.82#ibcon#flushed, iclass 35, count 0 2006.173.04:34:41.82#ibcon#about to write, iclass 35, count 0 2006.173.04:34:41.82#ibcon#wrote, iclass 35, count 0 2006.173.04:34:41.82#ibcon#about to read 3, iclass 35, count 0 2006.173.04:34:41.86#ibcon#read 3, iclass 35, count 0 2006.173.04:34:41.86#ibcon#about to read 4, iclass 35, count 0 2006.173.04:34:41.86#ibcon#read 4, iclass 35, count 0 2006.173.04:34:41.86#ibcon#about to read 5, iclass 35, count 0 2006.173.04:34:41.86#ibcon#read 5, iclass 35, count 0 2006.173.04:34:41.86#ibcon#about to read 6, iclass 35, count 0 2006.173.04:34:41.86#ibcon#read 6, iclass 35, count 0 2006.173.04:34:41.86#ibcon#end of sib2, iclass 35, count 0 2006.173.04:34:41.86#ibcon#*after write, iclass 35, count 0 2006.173.04:34:41.86#ibcon#*before return 0, iclass 35, count 0 2006.173.04:34:41.86#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.04:34:41.86#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.04:34:41.86#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.04:34:41.86#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.04:34:41.86$vck44/vb=1,4 2006.173.04:34:41.86#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.173.04:34:41.86#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.173.04:34:41.86#ibcon#ireg 11 cls_cnt 2 2006.173.04:34:41.86#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.04:34:41.86#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.04:34:41.86#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.04:34:41.86#ibcon#enter wrdev, iclass 37, count 2 2006.173.04:34:41.86#ibcon#first serial, iclass 37, count 2 2006.173.04:34:41.86#ibcon#enter sib2, iclass 37, count 2 2006.173.04:34:41.86#ibcon#flushed, iclass 37, count 2 2006.173.04:34:41.86#ibcon#about to write, iclass 37, count 2 2006.173.04:34:41.86#ibcon#wrote, iclass 37, count 2 2006.173.04:34:41.86#ibcon#about to read 3, iclass 37, count 2 2006.173.04:34:41.88#ibcon#read 3, iclass 37, count 2 2006.173.04:34:41.88#ibcon#about to read 4, iclass 37, count 2 2006.173.04:34:41.88#ibcon#read 4, iclass 37, count 2 2006.173.04:34:41.88#ibcon#about to read 5, iclass 37, count 2 2006.173.04:34:41.88#ibcon#read 5, iclass 37, count 2 2006.173.04:34:41.88#ibcon#about to read 6, iclass 37, count 2 2006.173.04:34:41.88#ibcon#read 6, iclass 37, count 2 2006.173.04:34:41.88#ibcon#end of sib2, iclass 37, count 2 2006.173.04:34:41.88#ibcon#*mode == 0, iclass 37, count 2 2006.173.04:34:41.88#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.173.04:34:41.88#ibcon#[27=AT01-04\r\n] 2006.173.04:34:41.88#ibcon#*before write, iclass 37, count 2 2006.173.04:34:41.88#ibcon#enter sib2, iclass 37, count 2 2006.173.04:34:41.88#ibcon#flushed, iclass 37, count 2 2006.173.04:34:41.88#ibcon#about to write, iclass 37, count 2 2006.173.04:34:41.88#ibcon#wrote, iclass 37, count 2 2006.173.04:34:41.88#ibcon#about to read 3, iclass 37, count 2 2006.173.04:34:41.91#ibcon#read 3, iclass 37, count 2 2006.173.04:34:41.91#ibcon#about to read 4, iclass 37, count 2 2006.173.04:34:41.91#ibcon#read 4, iclass 37, count 2 2006.173.04:34:41.91#ibcon#about to read 5, iclass 37, count 2 2006.173.04:34:41.91#ibcon#read 5, iclass 37, count 2 2006.173.04:34:41.91#ibcon#about to read 6, iclass 37, count 2 2006.173.04:34:41.91#ibcon#read 6, iclass 37, count 2 2006.173.04:34:41.91#ibcon#end of sib2, iclass 37, count 2 2006.173.04:34:41.91#ibcon#*after write, iclass 37, count 2 2006.173.04:34:41.91#ibcon#*before return 0, iclass 37, count 2 2006.173.04:34:41.91#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.04:34:41.91#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.173.04:34:41.91#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.173.04:34:41.91#ibcon#ireg 7 cls_cnt 0 2006.173.04:34:41.91#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.04:34:42.03#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.04:34:42.03#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.04:34:42.03#ibcon#enter wrdev, iclass 37, count 0 2006.173.04:34:42.03#ibcon#first serial, iclass 37, count 0 2006.173.04:34:42.03#ibcon#enter sib2, iclass 37, count 0 2006.173.04:34:42.03#ibcon#flushed, iclass 37, count 0 2006.173.04:34:42.03#ibcon#about to write, iclass 37, count 0 2006.173.04:34:42.03#ibcon#wrote, iclass 37, count 0 2006.173.04:34:42.03#ibcon#about to read 3, iclass 37, count 0 2006.173.04:34:42.05#ibcon#read 3, iclass 37, count 0 2006.173.04:34:42.05#ibcon#about to read 4, iclass 37, count 0 2006.173.04:34:42.05#ibcon#read 4, iclass 37, count 0 2006.173.04:34:42.05#ibcon#about to read 5, iclass 37, count 0 2006.173.04:34:42.05#ibcon#read 5, iclass 37, count 0 2006.173.04:34:42.05#ibcon#about to read 6, iclass 37, count 0 2006.173.04:34:42.05#ibcon#read 6, iclass 37, count 0 2006.173.04:34:42.05#ibcon#end of sib2, iclass 37, count 0 2006.173.04:34:42.05#ibcon#*mode == 0, iclass 37, count 0 2006.173.04:34:42.05#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.04:34:42.05#ibcon#[27=USB\r\n] 2006.173.04:34:42.05#ibcon#*before write, iclass 37, count 0 2006.173.04:34:42.05#ibcon#enter sib2, iclass 37, count 0 2006.173.04:34:42.05#ibcon#flushed, iclass 37, count 0 2006.173.04:34:42.05#ibcon#about to write, iclass 37, count 0 2006.173.04:34:42.05#ibcon#wrote, iclass 37, count 0 2006.173.04:34:42.05#ibcon#about to read 3, iclass 37, count 0 2006.173.04:34:42.08#ibcon#read 3, iclass 37, count 0 2006.173.04:34:42.08#ibcon#about to read 4, iclass 37, count 0 2006.173.04:34:42.08#ibcon#read 4, iclass 37, count 0 2006.173.04:34:42.08#ibcon#about to read 5, iclass 37, count 0 2006.173.04:34:42.08#ibcon#read 5, iclass 37, count 0 2006.173.04:34:42.08#ibcon#about to read 6, iclass 37, count 0 2006.173.04:34:42.08#ibcon#read 6, iclass 37, count 0 2006.173.04:34:42.08#ibcon#end of sib2, iclass 37, count 0 2006.173.04:34:42.08#ibcon#*after write, iclass 37, count 0 2006.173.04:34:42.08#ibcon#*before return 0, iclass 37, count 0 2006.173.04:34:42.08#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.04:34:42.08#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.173.04:34:42.08#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.04:34:42.08#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.04:34:42.08$vck44/vblo=2,634.99 2006.173.04:34:42.08#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.04:34:42.08#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.04:34:42.08#ibcon#ireg 17 cls_cnt 0 2006.173.04:34:42.08#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.04:34:42.08#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.04:34:42.08#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.04:34:42.08#ibcon#enter wrdev, iclass 39, count 0 2006.173.04:34:42.08#ibcon#first serial, iclass 39, count 0 2006.173.04:34:42.08#ibcon#enter sib2, iclass 39, count 0 2006.173.04:34:42.08#ibcon#flushed, iclass 39, count 0 2006.173.04:34:42.08#ibcon#about to write, iclass 39, count 0 2006.173.04:34:42.08#ibcon#wrote, iclass 39, count 0 2006.173.04:34:42.08#ibcon#about to read 3, iclass 39, count 0 2006.173.04:34:42.10#ibcon#read 3, iclass 39, count 0 2006.173.04:34:42.10#ibcon#about to read 4, iclass 39, count 0 2006.173.04:34:42.10#ibcon#read 4, iclass 39, count 0 2006.173.04:34:42.10#ibcon#about to read 5, iclass 39, count 0 2006.173.04:34:42.10#ibcon#read 5, iclass 39, count 0 2006.173.04:34:42.10#ibcon#about to read 6, iclass 39, count 0 2006.173.04:34:42.10#ibcon#read 6, iclass 39, count 0 2006.173.04:34:42.10#ibcon#end of sib2, iclass 39, count 0 2006.173.04:34:42.10#ibcon#*mode == 0, iclass 39, count 0 2006.173.04:34:42.10#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.04:34:42.10#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.04:34:42.10#ibcon#*before write, iclass 39, count 0 2006.173.04:34:42.10#ibcon#enter sib2, iclass 39, count 0 2006.173.04:34:42.10#ibcon#flushed, iclass 39, count 0 2006.173.04:34:42.10#ibcon#about to write, iclass 39, count 0 2006.173.04:34:42.10#ibcon#wrote, iclass 39, count 0 2006.173.04:34:42.10#ibcon#about to read 3, iclass 39, count 0 2006.173.04:34:42.14#ibcon#read 3, iclass 39, count 0 2006.173.04:34:42.14#ibcon#about to read 4, iclass 39, count 0 2006.173.04:34:42.14#ibcon#read 4, iclass 39, count 0 2006.173.04:34:42.14#ibcon#about to read 5, iclass 39, count 0 2006.173.04:34:42.14#ibcon#read 5, iclass 39, count 0 2006.173.04:34:42.14#ibcon#about to read 6, iclass 39, count 0 2006.173.04:34:42.14#ibcon#read 6, iclass 39, count 0 2006.173.04:34:42.14#ibcon#end of sib2, iclass 39, count 0 2006.173.04:34:42.14#ibcon#*after write, iclass 39, count 0 2006.173.04:34:42.14#ibcon#*before return 0, iclass 39, count 0 2006.173.04:34:42.14#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.04:34:42.14#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.04:34:42.14#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.04:34:42.14#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.04:34:42.14$vck44/vb=2,4 2006.173.04:34:42.14#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.04:34:42.14#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.04:34:42.14#ibcon#ireg 11 cls_cnt 2 2006.173.04:34:42.14#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.04:34:42.20#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.04:34:42.20#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.04:34:42.20#ibcon#enter wrdev, iclass 3, count 2 2006.173.04:34:42.20#ibcon#first serial, iclass 3, count 2 2006.173.04:34:42.20#ibcon#enter sib2, iclass 3, count 2 2006.173.04:34:42.20#ibcon#flushed, iclass 3, count 2 2006.173.04:34:42.20#ibcon#about to write, iclass 3, count 2 2006.173.04:34:42.20#ibcon#wrote, iclass 3, count 2 2006.173.04:34:42.20#ibcon#about to read 3, iclass 3, count 2 2006.173.04:34:42.22#ibcon#read 3, iclass 3, count 2 2006.173.04:34:42.22#ibcon#about to read 4, iclass 3, count 2 2006.173.04:34:42.22#ibcon#read 4, iclass 3, count 2 2006.173.04:34:42.22#ibcon#about to read 5, iclass 3, count 2 2006.173.04:34:42.22#ibcon#read 5, iclass 3, count 2 2006.173.04:34:42.22#ibcon#about to read 6, iclass 3, count 2 2006.173.04:34:42.22#ibcon#read 6, iclass 3, count 2 2006.173.04:34:42.22#ibcon#end of sib2, iclass 3, count 2 2006.173.04:34:42.22#ibcon#*mode == 0, iclass 3, count 2 2006.173.04:34:42.22#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.04:34:42.22#ibcon#[27=AT02-04\r\n] 2006.173.04:34:42.22#ibcon#*before write, iclass 3, count 2 2006.173.04:34:42.22#ibcon#enter sib2, iclass 3, count 2 2006.173.04:34:42.22#ibcon#flushed, iclass 3, count 2 2006.173.04:34:42.22#ibcon#about to write, iclass 3, count 2 2006.173.04:34:42.22#ibcon#wrote, iclass 3, count 2 2006.173.04:34:42.22#ibcon#about to read 3, iclass 3, count 2 2006.173.04:34:42.25#ibcon#read 3, iclass 3, count 2 2006.173.04:34:42.25#ibcon#about to read 4, iclass 3, count 2 2006.173.04:34:42.25#ibcon#read 4, iclass 3, count 2 2006.173.04:34:42.25#ibcon#about to read 5, iclass 3, count 2 2006.173.04:34:42.25#ibcon#read 5, iclass 3, count 2 2006.173.04:34:42.25#ibcon#about to read 6, iclass 3, count 2 2006.173.04:34:42.25#ibcon#read 6, iclass 3, count 2 2006.173.04:34:42.25#ibcon#end of sib2, iclass 3, count 2 2006.173.04:34:42.25#ibcon#*after write, iclass 3, count 2 2006.173.04:34:42.25#ibcon#*before return 0, iclass 3, count 2 2006.173.04:34:42.25#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.04:34:42.25#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.04:34:42.25#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.04:34:42.25#ibcon#ireg 7 cls_cnt 0 2006.173.04:34:42.25#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.04:34:42.37#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.04:34:42.37#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.04:34:42.37#ibcon#enter wrdev, iclass 3, count 0 2006.173.04:34:42.37#ibcon#first serial, iclass 3, count 0 2006.173.04:34:42.37#ibcon#enter sib2, iclass 3, count 0 2006.173.04:34:42.37#ibcon#flushed, iclass 3, count 0 2006.173.04:34:42.37#ibcon#about to write, iclass 3, count 0 2006.173.04:34:42.37#ibcon#wrote, iclass 3, count 0 2006.173.04:34:42.37#ibcon#about to read 3, iclass 3, count 0 2006.173.04:34:42.39#ibcon#read 3, iclass 3, count 0 2006.173.04:34:42.39#ibcon#about to read 4, iclass 3, count 0 2006.173.04:34:42.39#ibcon#read 4, iclass 3, count 0 2006.173.04:34:42.39#ibcon#about to read 5, iclass 3, count 0 2006.173.04:34:42.39#ibcon#read 5, iclass 3, count 0 2006.173.04:34:42.39#ibcon#about to read 6, iclass 3, count 0 2006.173.04:34:42.39#ibcon#read 6, iclass 3, count 0 2006.173.04:34:42.39#ibcon#end of sib2, iclass 3, count 0 2006.173.04:34:42.39#ibcon#*mode == 0, iclass 3, count 0 2006.173.04:34:42.39#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.04:34:42.39#ibcon#[27=USB\r\n] 2006.173.04:34:42.39#ibcon#*before write, iclass 3, count 0 2006.173.04:34:42.39#ibcon#enter sib2, iclass 3, count 0 2006.173.04:34:42.39#ibcon#flushed, iclass 3, count 0 2006.173.04:34:42.39#ibcon#about to write, iclass 3, count 0 2006.173.04:34:42.39#ibcon#wrote, iclass 3, count 0 2006.173.04:34:42.39#ibcon#about to read 3, iclass 3, count 0 2006.173.04:34:42.42#ibcon#read 3, iclass 3, count 0 2006.173.04:34:42.42#ibcon#about to read 4, iclass 3, count 0 2006.173.04:34:42.42#ibcon#read 4, iclass 3, count 0 2006.173.04:34:42.42#ibcon#about to read 5, iclass 3, count 0 2006.173.04:34:42.42#ibcon#read 5, iclass 3, count 0 2006.173.04:34:42.42#ibcon#about to read 6, iclass 3, count 0 2006.173.04:34:42.42#ibcon#read 6, iclass 3, count 0 2006.173.04:34:42.42#ibcon#end of sib2, iclass 3, count 0 2006.173.04:34:42.42#ibcon#*after write, iclass 3, count 0 2006.173.04:34:42.42#ibcon#*before return 0, iclass 3, count 0 2006.173.04:34:42.42#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.04:34:42.42#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.04:34:42.42#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.04:34:42.42#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.04:34:42.42$vck44/vblo=3,649.99 2006.173.04:34:42.42#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.04:34:42.42#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.04:34:42.42#ibcon#ireg 17 cls_cnt 0 2006.173.04:34:42.42#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.04:34:42.42#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.04:34:42.42#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.04:34:42.42#ibcon#enter wrdev, iclass 5, count 0 2006.173.04:34:42.42#ibcon#first serial, iclass 5, count 0 2006.173.04:34:42.42#ibcon#enter sib2, iclass 5, count 0 2006.173.04:34:42.42#ibcon#flushed, iclass 5, count 0 2006.173.04:34:42.42#ibcon#about to write, iclass 5, count 0 2006.173.04:34:42.42#ibcon#wrote, iclass 5, count 0 2006.173.04:34:42.42#ibcon#about to read 3, iclass 5, count 0 2006.173.04:34:42.44#ibcon#read 3, iclass 5, count 0 2006.173.04:34:42.44#ibcon#about to read 4, iclass 5, count 0 2006.173.04:34:42.44#ibcon#read 4, iclass 5, count 0 2006.173.04:34:42.44#ibcon#about to read 5, iclass 5, count 0 2006.173.04:34:42.44#ibcon#read 5, iclass 5, count 0 2006.173.04:34:42.44#ibcon#about to read 6, iclass 5, count 0 2006.173.04:34:42.44#ibcon#read 6, iclass 5, count 0 2006.173.04:34:42.44#ibcon#end of sib2, iclass 5, count 0 2006.173.04:34:42.44#ibcon#*mode == 0, iclass 5, count 0 2006.173.04:34:42.44#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.04:34:42.44#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.04:34:42.44#ibcon#*before write, iclass 5, count 0 2006.173.04:34:42.44#ibcon#enter sib2, iclass 5, count 0 2006.173.04:34:42.44#ibcon#flushed, iclass 5, count 0 2006.173.04:34:42.44#ibcon#about to write, iclass 5, count 0 2006.173.04:34:42.44#ibcon#wrote, iclass 5, count 0 2006.173.04:34:42.44#ibcon#about to read 3, iclass 5, count 0 2006.173.04:34:42.48#ibcon#read 3, iclass 5, count 0 2006.173.04:34:42.48#ibcon#about to read 4, iclass 5, count 0 2006.173.04:34:42.48#ibcon#read 4, iclass 5, count 0 2006.173.04:34:42.48#ibcon#about to read 5, iclass 5, count 0 2006.173.04:34:42.48#ibcon#read 5, iclass 5, count 0 2006.173.04:34:42.48#ibcon#about to read 6, iclass 5, count 0 2006.173.04:34:42.48#ibcon#read 6, iclass 5, count 0 2006.173.04:34:42.48#ibcon#end of sib2, iclass 5, count 0 2006.173.04:34:42.48#ibcon#*after write, iclass 5, count 0 2006.173.04:34:42.48#ibcon#*before return 0, iclass 5, count 0 2006.173.04:34:42.48#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.04:34:42.48#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.04:34:42.48#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.04:34:42.48#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.04:34:42.48$vck44/vb=3,4 2006.173.04:34:42.48#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.173.04:34:42.48#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.173.04:34:42.48#ibcon#ireg 11 cls_cnt 2 2006.173.04:34:42.48#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.04:34:42.54#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.04:34:42.54#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.04:34:42.54#ibcon#enter wrdev, iclass 7, count 2 2006.173.04:34:42.54#ibcon#first serial, iclass 7, count 2 2006.173.04:34:42.54#ibcon#enter sib2, iclass 7, count 2 2006.173.04:34:42.54#ibcon#flushed, iclass 7, count 2 2006.173.04:34:42.54#ibcon#about to write, iclass 7, count 2 2006.173.04:34:42.54#ibcon#wrote, iclass 7, count 2 2006.173.04:34:42.54#ibcon#about to read 3, iclass 7, count 2 2006.173.04:34:42.56#ibcon#read 3, iclass 7, count 2 2006.173.04:34:42.56#ibcon#about to read 4, iclass 7, count 2 2006.173.04:34:42.56#ibcon#read 4, iclass 7, count 2 2006.173.04:34:42.56#ibcon#about to read 5, iclass 7, count 2 2006.173.04:34:42.56#ibcon#read 5, iclass 7, count 2 2006.173.04:34:42.56#ibcon#about to read 6, iclass 7, count 2 2006.173.04:34:42.56#ibcon#read 6, iclass 7, count 2 2006.173.04:34:42.56#ibcon#end of sib2, iclass 7, count 2 2006.173.04:34:42.56#ibcon#*mode == 0, iclass 7, count 2 2006.173.04:34:42.56#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.173.04:34:42.56#ibcon#[27=AT03-04\r\n] 2006.173.04:34:42.56#ibcon#*before write, iclass 7, count 2 2006.173.04:34:42.56#ibcon#enter sib2, iclass 7, count 2 2006.173.04:34:42.56#ibcon#flushed, iclass 7, count 2 2006.173.04:34:42.56#ibcon#about to write, iclass 7, count 2 2006.173.04:34:42.56#ibcon#wrote, iclass 7, count 2 2006.173.04:34:42.56#ibcon#about to read 3, iclass 7, count 2 2006.173.04:34:42.59#ibcon#read 3, iclass 7, count 2 2006.173.04:34:42.59#ibcon#about to read 4, iclass 7, count 2 2006.173.04:34:42.59#ibcon#read 4, iclass 7, count 2 2006.173.04:34:42.59#ibcon#about to read 5, iclass 7, count 2 2006.173.04:34:42.59#ibcon#read 5, iclass 7, count 2 2006.173.04:34:42.59#ibcon#about to read 6, iclass 7, count 2 2006.173.04:34:42.59#ibcon#read 6, iclass 7, count 2 2006.173.04:34:42.59#ibcon#end of sib2, iclass 7, count 2 2006.173.04:34:42.59#ibcon#*after write, iclass 7, count 2 2006.173.04:34:42.59#ibcon#*before return 0, iclass 7, count 2 2006.173.04:34:42.59#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.04:34:42.59#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.173.04:34:42.59#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.173.04:34:42.59#ibcon#ireg 7 cls_cnt 0 2006.173.04:34:42.59#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.04:34:42.71#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.04:34:42.71#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.04:34:42.71#ibcon#enter wrdev, iclass 7, count 0 2006.173.04:34:42.71#ibcon#first serial, iclass 7, count 0 2006.173.04:34:42.71#ibcon#enter sib2, iclass 7, count 0 2006.173.04:34:42.71#ibcon#flushed, iclass 7, count 0 2006.173.04:34:42.71#ibcon#about to write, iclass 7, count 0 2006.173.04:34:42.71#ibcon#wrote, iclass 7, count 0 2006.173.04:34:42.71#ibcon#about to read 3, iclass 7, count 0 2006.173.04:34:42.73#ibcon#read 3, iclass 7, count 0 2006.173.04:34:42.73#ibcon#about to read 4, iclass 7, count 0 2006.173.04:34:42.73#ibcon#read 4, iclass 7, count 0 2006.173.04:34:42.73#ibcon#about to read 5, iclass 7, count 0 2006.173.04:34:42.73#ibcon#read 5, iclass 7, count 0 2006.173.04:34:42.73#ibcon#about to read 6, iclass 7, count 0 2006.173.04:34:42.73#ibcon#read 6, iclass 7, count 0 2006.173.04:34:42.73#ibcon#end of sib2, iclass 7, count 0 2006.173.04:34:42.73#ibcon#*mode == 0, iclass 7, count 0 2006.173.04:34:42.73#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.04:34:42.73#ibcon#[27=USB\r\n] 2006.173.04:34:42.73#ibcon#*before write, iclass 7, count 0 2006.173.04:34:42.73#ibcon#enter sib2, iclass 7, count 0 2006.173.04:34:42.73#ibcon#flushed, iclass 7, count 0 2006.173.04:34:42.73#ibcon#about to write, iclass 7, count 0 2006.173.04:34:42.73#ibcon#wrote, iclass 7, count 0 2006.173.04:34:42.73#ibcon#about to read 3, iclass 7, count 0 2006.173.04:34:42.76#ibcon#read 3, iclass 7, count 0 2006.173.04:34:42.76#ibcon#about to read 4, iclass 7, count 0 2006.173.04:34:42.76#ibcon#read 4, iclass 7, count 0 2006.173.04:34:42.76#ibcon#about to read 5, iclass 7, count 0 2006.173.04:34:42.76#ibcon#read 5, iclass 7, count 0 2006.173.04:34:42.76#ibcon#about to read 6, iclass 7, count 0 2006.173.04:34:42.76#ibcon#read 6, iclass 7, count 0 2006.173.04:34:42.76#ibcon#end of sib2, iclass 7, count 0 2006.173.04:34:42.76#ibcon#*after write, iclass 7, count 0 2006.173.04:34:42.76#ibcon#*before return 0, iclass 7, count 0 2006.173.04:34:42.76#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.04:34:42.76#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.173.04:34:42.76#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.04:34:42.76#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.04:34:42.76$vck44/vblo=4,679.99 2006.173.04:34:42.76#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.04:34:42.76#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.04:34:42.76#ibcon#ireg 17 cls_cnt 0 2006.173.04:34:42.76#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.04:34:42.76#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.04:34:42.76#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.04:34:42.76#ibcon#enter wrdev, iclass 11, count 0 2006.173.04:34:42.76#ibcon#first serial, iclass 11, count 0 2006.173.04:34:42.76#ibcon#enter sib2, iclass 11, count 0 2006.173.04:34:42.76#ibcon#flushed, iclass 11, count 0 2006.173.04:34:42.76#ibcon#about to write, iclass 11, count 0 2006.173.04:34:42.76#ibcon#wrote, iclass 11, count 0 2006.173.04:34:42.76#ibcon#about to read 3, iclass 11, count 0 2006.173.04:34:42.78#ibcon#read 3, iclass 11, count 0 2006.173.04:34:42.78#ibcon#about to read 4, iclass 11, count 0 2006.173.04:34:42.78#ibcon#read 4, iclass 11, count 0 2006.173.04:34:42.78#ibcon#about to read 5, iclass 11, count 0 2006.173.04:34:42.78#ibcon#read 5, iclass 11, count 0 2006.173.04:34:42.78#ibcon#about to read 6, iclass 11, count 0 2006.173.04:34:42.78#ibcon#read 6, iclass 11, count 0 2006.173.04:34:42.78#ibcon#end of sib2, iclass 11, count 0 2006.173.04:34:42.78#ibcon#*mode == 0, iclass 11, count 0 2006.173.04:34:42.78#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.04:34:42.78#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.04:34:42.78#ibcon#*before write, iclass 11, count 0 2006.173.04:34:42.78#ibcon#enter sib2, iclass 11, count 0 2006.173.04:34:42.78#ibcon#flushed, iclass 11, count 0 2006.173.04:34:42.78#ibcon#about to write, iclass 11, count 0 2006.173.04:34:42.78#ibcon#wrote, iclass 11, count 0 2006.173.04:34:42.78#ibcon#about to read 3, iclass 11, count 0 2006.173.04:34:42.82#ibcon#read 3, iclass 11, count 0 2006.173.04:34:42.82#ibcon#about to read 4, iclass 11, count 0 2006.173.04:34:42.82#ibcon#read 4, iclass 11, count 0 2006.173.04:34:42.82#ibcon#about to read 5, iclass 11, count 0 2006.173.04:34:42.82#ibcon#read 5, iclass 11, count 0 2006.173.04:34:42.82#ibcon#about to read 6, iclass 11, count 0 2006.173.04:34:42.82#ibcon#read 6, iclass 11, count 0 2006.173.04:34:42.82#ibcon#end of sib2, iclass 11, count 0 2006.173.04:34:42.82#ibcon#*after write, iclass 11, count 0 2006.173.04:34:42.82#ibcon#*before return 0, iclass 11, count 0 2006.173.04:34:42.82#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.04:34:42.82#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.04:34:42.82#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.04:34:42.82#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.04:34:42.82$vck44/vb=4,4 2006.173.04:34:42.82#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.173.04:34:42.82#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.173.04:34:42.82#ibcon#ireg 11 cls_cnt 2 2006.173.04:34:42.82#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.04:34:42.88#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.04:34:42.88#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.04:34:42.88#ibcon#enter wrdev, iclass 13, count 2 2006.173.04:34:42.88#ibcon#first serial, iclass 13, count 2 2006.173.04:34:42.88#ibcon#enter sib2, iclass 13, count 2 2006.173.04:34:42.88#ibcon#flushed, iclass 13, count 2 2006.173.04:34:42.88#ibcon#about to write, iclass 13, count 2 2006.173.04:34:42.88#ibcon#wrote, iclass 13, count 2 2006.173.04:34:42.88#ibcon#about to read 3, iclass 13, count 2 2006.173.04:34:42.90#ibcon#read 3, iclass 13, count 2 2006.173.04:34:42.90#ibcon#about to read 4, iclass 13, count 2 2006.173.04:34:42.90#ibcon#read 4, iclass 13, count 2 2006.173.04:34:42.90#ibcon#about to read 5, iclass 13, count 2 2006.173.04:34:42.90#ibcon#read 5, iclass 13, count 2 2006.173.04:34:42.90#ibcon#about to read 6, iclass 13, count 2 2006.173.04:34:42.90#ibcon#read 6, iclass 13, count 2 2006.173.04:34:42.90#ibcon#end of sib2, iclass 13, count 2 2006.173.04:34:42.90#ibcon#*mode == 0, iclass 13, count 2 2006.173.04:34:42.90#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.173.04:34:42.90#ibcon#[27=AT04-04\r\n] 2006.173.04:34:42.90#ibcon#*before write, iclass 13, count 2 2006.173.04:34:42.90#ibcon#enter sib2, iclass 13, count 2 2006.173.04:34:42.90#ibcon#flushed, iclass 13, count 2 2006.173.04:34:42.90#ibcon#about to write, iclass 13, count 2 2006.173.04:34:42.90#ibcon#wrote, iclass 13, count 2 2006.173.04:34:42.90#ibcon#about to read 3, iclass 13, count 2 2006.173.04:34:42.93#ibcon#read 3, iclass 13, count 2 2006.173.04:34:42.93#ibcon#about to read 4, iclass 13, count 2 2006.173.04:34:42.93#ibcon#read 4, iclass 13, count 2 2006.173.04:34:42.93#ibcon#about to read 5, iclass 13, count 2 2006.173.04:34:42.93#ibcon#read 5, iclass 13, count 2 2006.173.04:34:42.93#ibcon#about to read 6, iclass 13, count 2 2006.173.04:34:42.93#ibcon#read 6, iclass 13, count 2 2006.173.04:34:42.93#ibcon#end of sib2, iclass 13, count 2 2006.173.04:34:42.93#ibcon#*after write, iclass 13, count 2 2006.173.04:34:42.93#ibcon#*before return 0, iclass 13, count 2 2006.173.04:34:42.93#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.04:34:42.93#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.173.04:34:42.93#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.173.04:34:42.93#ibcon#ireg 7 cls_cnt 0 2006.173.04:34:42.93#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.04:34:43.05#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.04:34:43.05#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.04:34:43.05#ibcon#enter wrdev, iclass 13, count 0 2006.173.04:34:43.05#ibcon#first serial, iclass 13, count 0 2006.173.04:34:43.05#ibcon#enter sib2, iclass 13, count 0 2006.173.04:34:43.05#ibcon#flushed, iclass 13, count 0 2006.173.04:34:43.05#ibcon#about to write, iclass 13, count 0 2006.173.04:34:43.05#ibcon#wrote, iclass 13, count 0 2006.173.04:34:43.05#ibcon#about to read 3, iclass 13, count 0 2006.173.04:34:43.07#ibcon#read 3, iclass 13, count 0 2006.173.04:34:43.07#ibcon#about to read 4, iclass 13, count 0 2006.173.04:34:43.07#ibcon#read 4, iclass 13, count 0 2006.173.04:34:43.07#ibcon#about to read 5, iclass 13, count 0 2006.173.04:34:43.07#ibcon#read 5, iclass 13, count 0 2006.173.04:34:43.07#ibcon#about to read 6, iclass 13, count 0 2006.173.04:34:43.07#ibcon#read 6, iclass 13, count 0 2006.173.04:34:43.07#ibcon#end of sib2, iclass 13, count 0 2006.173.04:34:43.07#ibcon#*mode == 0, iclass 13, count 0 2006.173.04:34:43.07#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.04:34:43.07#ibcon#[27=USB\r\n] 2006.173.04:34:43.07#ibcon#*before write, iclass 13, count 0 2006.173.04:34:43.07#ibcon#enter sib2, iclass 13, count 0 2006.173.04:34:43.07#ibcon#flushed, iclass 13, count 0 2006.173.04:34:43.07#ibcon#about to write, iclass 13, count 0 2006.173.04:34:43.07#ibcon#wrote, iclass 13, count 0 2006.173.04:34:43.07#ibcon#about to read 3, iclass 13, count 0 2006.173.04:34:43.10#ibcon#read 3, iclass 13, count 0 2006.173.04:34:43.10#ibcon#about to read 4, iclass 13, count 0 2006.173.04:34:43.10#ibcon#read 4, iclass 13, count 0 2006.173.04:34:43.10#ibcon#about to read 5, iclass 13, count 0 2006.173.04:34:43.10#ibcon#read 5, iclass 13, count 0 2006.173.04:34:43.10#ibcon#about to read 6, iclass 13, count 0 2006.173.04:34:43.10#ibcon#read 6, iclass 13, count 0 2006.173.04:34:43.10#ibcon#end of sib2, iclass 13, count 0 2006.173.04:34:43.10#ibcon#*after write, iclass 13, count 0 2006.173.04:34:43.10#ibcon#*before return 0, iclass 13, count 0 2006.173.04:34:43.10#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.04:34:43.10#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.173.04:34:43.10#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.04:34:43.10#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.04:34:43.10$vck44/vblo=5,709.99 2006.173.04:34:43.10#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.04:34:43.10#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.04:34:43.10#ibcon#ireg 17 cls_cnt 0 2006.173.04:34:43.10#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.04:34:43.10#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.04:34:43.10#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.04:34:43.10#ibcon#enter wrdev, iclass 15, count 0 2006.173.04:34:43.10#ibcon#first serial, iclass 15, count 0 2006.173.04:34:43.10#ibcon#enter sib2, iclass 15, count 0 2006.173.04:34:43.10#ibcon#flushed, iclass 15, count 0 2006.173.04:34:43.10#ibcon#about to write, iclass 15, count 0 2006.173.04:34:43.10#ibcon#wrote, iclass 15, count 0 2006.173.04:34:43.10#ibcon#about to read 3, iclass 15, count 0 2006.173.04:34:43.12#ibcon#read 3, iclass 15, count 0 2006.173.04:34:43.12#ibcon#about to read 4, iclass 15, count 0 2006.173.04:34:43.12#ibcon#read 4, iclass 15, count 0 2006.173.04:34:43.12#ibcon#about to read 5, iclass 15, count 0 2006.173.04:34:43.12#ibcon#read 5, iclass 15, count 0 2006.173.04:34:43.12#ibcon#about to read 6, iclass 15, count 0 2006.173.04:34:43.12#ibcon#read 6, iclass 15, count 0 2006.173.04:34:43.12#ibcon#end of sib2, iclass 15, count 0 2006.173.04:34:43.12#ibcon#*mode == 0, iclass 15, count 0 2006.173.04:34:43.12#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.04:34:43.12#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.04:34:43.12#ibcon#*before write, iclass 15, count 0 2006.173.04:34:43.12#ibcon#enter sib2, iclass 15, count 0 2006.173.04:34:43.12#ibcon#flushed, iclass 15, count 0 2006.173.04:34:43.12#ibcon#about to write, iclass 15, count 0 2006.173.04:34:43.12#ibcon#wrote, iclass 15, count 0 2006.173.04:34:43.12#ibcon#about to read 3, iclass 15, count 0 2006.173.04:34:43.16#ibcon#read 3, iclass 15, count 0 2006.173.04:34:43.16#ibcon#about to read 4, iclass 15, count 0 2006.173.04:34:43.16#ibcon#read 4, iclass 15, count 0 2006.173.04:34:43.16#ibcon#about to read 5, iclass 15, count 0 2006.173.04:34:43.16#ibcon#read 5, iclass 15, count 0 2006.173.04:34:43.16#ibcon#about to read 6, iclass 15, count 0 2006.173.04:34:43.16#ibcon#read 6, iclass 15, count 0 2006.173.04:34:43.16#ibcon#end of sib2, iclass 15, count 0 2006.173.04:34:43.16#ibcon#*after write, iclass 15, count 0 2006.173.04:34:43.16#ibcon#*before return 0, iclass 15, count 0 2006.173.04:34:43.16#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.04:34:43.16#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.04:34:43.16#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.04:34:43.16#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.04:34:43.16$vck44/vb=5,4 2006.173.04:34:43.16#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.04:34:43.16#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.04:34:43.16#ibcon#ireg 11 cls_cnt 2 2006.173.04:34:43.16#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.04:34:43.22#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.04:34:43.22#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.04:34:43.22#ibcon#enter wrdev, iclass 17, count 2 2006.173.04:34:43.22#ibcon#first serial, iclass 17, count 2 2006.173.04:34:43.22#ibcon#enter sib2, iclass 17, count 2 2006.173.04:34:43.22#ibcon#flushed, iclass 17, count 2 2006.173.04:34:43.22#ibcon#about to write, iclass 17, count 2 2006.173.04:34:43.22#ibcon#wrote, iclass 17, count 2 2006.173.04:34:43.22#ibcon#about to read 3, iclass 17, count 2 2006.173.04:34:43.24#ibcon#read 3, iclass 17, count 2 2006.173.04:34:43.24#ibcon#about to read 4, iclass 17, count 2 2006.173.04:34:43.24#ibcon#read 4, iclass 17, count 2 2006.173.04:34:43.24#ibcon#about to read 5, iclass 17, count 2 2006.173.04:34:43.24#ibcon#read 5, iclass 17, count 2 2006.173.04:34:43.24#ibcon#about to read 6, iclass 17, count 2 2006.173.04:34:43.24#ibcon#read 6, iclass 17, count 2 2006.173.04:34:43.24#ibcon#end of sib2, iclass 17, count 2 2006.173.04:34:43.24#ibcon#*mode == 0, iclass 17, count 2 2006.173.04:34:43.24#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.04:34:43.24#ibcon#[27=AT05-04\r\n] 2006.173.04:34:43.24#ibcon#*before write, iclass 17, count 2 2006.173.04:34:43.24#ibcon#enter sib2, iclass 17, count 2 2006.173.04:34:43.24#ibcon#flushed, iclass 17, count 2 2006.173.04:34:43.24#ibcon#about to write, iclass 17, count 2 2006.173.04:34:43.24#ibcon#wrote, iclass 17, count 2 2006.173.04:34:43.24#ibcon#about to read 3, iclass 17, count 2 2006.173.04:34:43.27#ibcon#read 3, iclass 17, count 2 2006.173.04:34:43.27#ibcon#about to read 4, iclass 17, count 2 2006.173.04:34:43.27#ibcon#read 4, iclass 17, count 2 2006.173.04:34:43.27#ibcon#about to read 5, iclass 17, count 2 2006.173.04:34:43.27#ibcon#read 5, iclass 17, count 2 2006.173.04:34:43.27#ibcon#about to read 6, iclass 17, count 2 2006.173.04:34:43.27#ibcon#read 6, iclass 17, count 2 2006.173.04:34:43.27#ibcon#end of sib2, iclass 17, count 2 2006.173.04:34:43.27#ibcon#*after write, iclass 17, count 2 2006.173.04:34:43.27#ibcon#*before return 0, iclass 17, count 2 2006.173.04:34:43.27#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.04:34:43.27#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.04:34:43.27#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.04:34:43.27#ibcon#ireg 7 cls_cnt 0 2006.173.04:34:43.27#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.04:34:43.39#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.04:34:43.39#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.04:34:43.39#ibcon#enter wrdev, iclass 17, count 0 2006.173.04:34:43.39#ibcon#first serial, iclass 17, count 0 2006.173.04:34:43.39#ibcon#enter sib2, iclass 17, count 0 2006.173.04:34:43.39#ibcon#flushed, iclass 17, count 0 2006.173.04:34:43.39#ibcon#about to write, iclass 17, count 0 2006.173.04:34:43.39#ibcon#wrote, iclass 17, count 0 2006.173.04:34:43.39#ibcon#about to read 3, iclass 17, count 0 2006.173.04:34:43.41#ibcon#read 3, iclass 17, count 0 2006.173.04:34:43.41#ibcon#about to read 4, iclass 17, count 0 2006.173.04:34:43.41#ibcon#read 4, iclass 17, count 0 2006.173.04:34:43.41#ibcon#about to read 5, iclass 17, count 0 2006.173.04:34:43.41#ibcon#read 5, iclass 17, count 0 2006.173.04:34:43.41#ibcon#about to read 6, iclass 17, count 0 2006.173.04:34:43.41#ibcon#read 6, iclass 17, count 0 2006.173.04:34:43.41#ibcon#end of sib2, iclass 17, count 0 2006.173.04:34:43.41#ibcon#*mode == 0, iclass 17, count 0 2006.173.04:34:43.41#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.04:34:43.41#ibcon#[27=USB\r\n] 2006.173.04:34:43.41#ibcon#*before write, iclass 17, count 0 2006.173.04:34:43.41#ibcon#enter sib2, iclass 17, count 0 2006.173.04:34:43.41#ibcon#flushed, iclass 17, count 0 2006.173.04:34:43.41#ibcon#about to write, iclass 17, count 0 2006.173.04:34:43.41#ibcon#wrote, iclass 17, count 0 2006.173.04:34:43.41#ibcon#about to read 3, iclass 17, count 0 2006.173.04:34:43.44#ibcon#read 3, iclass 17, count 0 2006.173.04:34:43.44#ibcon#about to read 4, iclass 17, count 0 2006.173.04:34:43.44#ibcon#read 4, iclass 17, count 0 2006.173.04:34:43.44#ibcon#about to read 5, iclass 17, count 0 2006.173.04:34:43.44#ibcon#read 5, iclass 17, count 0 2006.173.04:34:43.44#ibcon#about to read 6, iclass 17, count 0 2006.173.04:34:43.44#ibcon#read 6, iclass 17, count 0 2006.173.04:34:43.44#ibcon#end of sib2, iclass 17, count 0 2006.173.04:34:43.44#ibcon#*after write, iclass 17, count 0 2006.173.04:34:43.44#ibcon#*before return 0, iclass 17, count 0 2006.173.04:34:43.44#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.04:34:43.44#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.04:34:43.44#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.04:34:43.44#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.04:34:43.44$vck44/vblo=6,719.99 2006.173.04:34:43.44#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.04:34:43.44#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.04:34:43.44#ibcon#ireg 17 cls_cnt 0 2006.173.04:34:43.44#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.04:34:43.44#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.04:34:43.44#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.04:34:43.44#ibcon#enter wrdev, iclass 19, count 0 2006.173.04:34:43.44#ibcon#first serial, iclass 19, count 0 2006.173.04:34:43.44#ibcon#enter sib2, iclass 19, count 0 2006.173.04:34:43.44#ibcon#flushed, iclass 19, count 0 2006.173.04:34:43.44#ibcon#about to write, iclass 19, count 0 2006.173.04:34:43.44#ibcon#wrote, iclass 19, count 0 2006.173.04:34:43.44#ibcon#about to read 3, iclass 19, count 0 2006.173.04:34:43.46#ibcon#read 3, iclass 19, count 0 2006.173.04:34:43.46#ibcon#about to read 4, iclass 19, count 0 2006.173.04:34:43.46#ibcon#read 4, iclass 19, count 0 2006.173.04:34:43.46#ibcon#about to read 5, iclass 19, count 0 2006.173.04:34:43.46#ibcon#read 5, iclass 19, count 0 2006.173.04:34:43.46#ibcon#about to read 6, iclass 19, count 0 2006.173.04:34:43.46#ibcon#read 6, iclass 19, count 0 2006.173.04:34:43.46#ibcon#end of sib2, iclass 19, count 0 2006.173.04:34:43.46#ibcon#*mode == 0, iclass 19, count 0 2006.173.04:34:43.46#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.04:34:43.46#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.04:34:43.46#ibcon#*before write, iclass 19, count 0 2006.173.04:34:43.46#ibcon#enter sib2, iclass 19, count 0 2006.173.04:34:43.46#ibcon#flushed, iclass 19, count 0 2006.173.04:34:43.46#ibcon#about to write, iclass 19, count 0 2006.173.04:34:43.46#ibcon#wrote, iclass 19, count 0 2006.173.04:34:43.46#ibcon#about to read 3, iclass 19, count 0 2006.173.04:34:43.50#ibcon#read 3, iclass 19, count 0 2006.173.04:34:43.50#ibcon#about to read 4, iclass 19, count 0 2006.173.04:34:43.50#ibcon#read 4, iclass 19, count 0 2006.173.04:34:43.50#ibcon#about to read 5, iclass 19, count 0 2006.173.04:34:43.50#ibcon#read 5, iclass 19, count 0 2006.173.04:34:43.50#ibcon#about to read 6, iclass 19, count 0 2006.173.04:34:43.50#ibcon#read 6, iclass 19, count 0 2006.173.04:34:43.50#ibcon#end of sib2, iclass 19, count 0 2006.173.04:34:43.50#ibcon#*after write, iclass 19, count 0 2006.173.04:34:43.50#ibcon#*before return 0, iclass 19, count 0 2006.173.04:34:43.50#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.04:34:43.50#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.04:34:43.50#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.04:34:43.50#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.04:34:43.50$vck44/vb=6,4 2006.173.04:34:43.50#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.04:34:43.50#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.04:34:43.50#ibcon#ireg 11 cls_cnt 2 2006.173.04:34:43.50#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.04:34:43.56#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.04:34:43.56#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.04:34:43.56#ibcon#enter wrdev, iclass 21, count 2 2006.173.04:34:43.56#ibcon#first serial, iclass 21, count 2 2006.173.04:34:43.56#ibcon#enter sib2, iclass 21, count 2 2006.173.04:34:43.56#ibcon#flushed, iclass 21, count 2 2006.173.04:34:43.56#ibcon#about to write, iclass 21, count 2 2006.173.04:34:43.56#ibcon#wrote, iclass 21, count 2 2006.173.04:34:43.56#ibcon#about to read 3, iclass 21, count 2 2006.173.04:34:43.58#ibcon#read 3, iclass 21, count 2 2006.173.04:34:43.58#ibcon#about to read 4, iclass 21, count 2 2006.173.04:34:43.58#ibcon#read 4, iclass 21, count 2 2006.173.04:34:43.58#ibcon#about to read 5, iclass 21, count 2 2006.173.04:34:43.58#ibcon#read 5, iclass 21, count 2 2006.173.04:34:43.58#ibcon#about to read 6, iclass 21, count 2 2006.173.04:34:43.58#ibcon#read 6, iclass 21, count 2 2006.173.04:34:43.58#ibcon#end of sib2, iclass 21, count 2 2006.173.04:34:43.58#ibcon#*mode == 0, iclass 21, count 2 2006.173.04:34:43.58#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.04:34:43.58#ibcon#[27=AT06-04\r\n] 2006.173.04:34:43.58#ibcon#*before write, iclass 21, count 2 2006.173.04:34:43.58#ibcon#enter sib2, iclass 21, count 2 2006.173.04:34:43.58#ibcon#flushed, iclass 21, count 2 2006.173.04:34:43.58#ibcon#about to write, iclass 21, count 2 2006.173.04:34:43.58#ibcon#wrote, iclass 21, count 2 2006.173.04:34:43.58#ibcon#about to read 3, iclass 21, count 2 2006.173.04:34:43.61#ibcon#read 3, iclass 21, count 2 2006.173.04:34:43.61#ibcon#about to read 4, iclass 21, count 2 2006.173.04:34:43.61#ibcon#read 4, iclass 21, count 2 2006.173.04:34:43.61#ibcon#about to read 5, iclass 21, count 2 2006.173.04:34:43.61#ibcon#read 5, iclass 21, count 2 2006.173.04:34:43.61#ibcon#about to read 6, iclass 21, count 2 2006.173.04:34:43.61#ibcon#read 6, iclass 21, count 2 2006.173.04:34:43.61#ibcon#end of sib2, iclass 21, count 2 2006.173.04:34:43.61#ibcon#*after write, iclass 21, count 2 2006.173.04:34:43.61#ibcon#*before return 0, iclass 21, count 2 2006.173.04:34:43.61#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.04:34:43.61#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.04:34:43.61#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.04:34:43.61#ibcon#ireg 7 cls_cnt 0 2006.173.04:34:43.61#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.04:34:43.73#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.04:34:43.73#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.04:34:43.73#ibcon#enter wrdev, iclass 21, count 0 2006.173.04:34:43.73#ibcon#first serial, iclass 21, count 0 2006.173.04:34:43.73#ibcon#enter sib2, iclass 21, count 0 2006.173.04:34:43.73#ibcon#flushed, iclass 21, count 0 2006.173.04:34:43.73#ibcon#about to write, iclass 21, count 0 2006.173.04:34:43.73#ibcon#wrote, iclass 21, count 0 2006.173.04:34:43.73#ibcon#about to read 3, iclass 21, count 0 2006.173.04:34:43.75#ibcon#read 3, iclass 21, count 0 2006.173.04:34:43.75#ibcon#about to read 4, iclass 21, count 0 2006.173.04:34:43.75#ibcon#read 4, iclass 21, count 0 2006.173.04:34:43.75#ibcon#about to read 5, iclass 21, count 0 2006.173.04:34:43.75#ibcon#read 5, iclass 21, count 0 2006.173.04:34:43.75#ibcon#about to read 6, iclass 21, count 0 2006.173.04:34:43.75#ibcon#read 6, iclass 21, count 0 2006.173.04:34:43.75#ibcon#end of sib2, iclass 21, count 0 2006.173.04:34:43.75#ibcon#*mode == 0, iclass 21, count 0 2006.173.04:34:43.75#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.04:34:43.75#ibcon#[27=USB\r\n] 2006.173.04:34:43.75#ibcon#*before write, iclass 21, count 0 2006.173.04:34:43.75#ibcon#enter sib2, iclass 21, count 0 2006.173.04:34:43.75#ibcon#flushed, iclass 21, count 0 2006.173.04:34:43.75#ibcon#about to write, iclass 21, count 0 2006.173.04:34:43.75#ibcon#wrote, iclass 21, count 0 2006.173.04:34:43.75#ibcon#about to read 3, iclass 21, count 0 2006.173.04:34:43.78#ibcon#read 3, iclass 21, count 0 2006.173.04:34:43.78#ibcon#about to read 4, iclass 21, count 0 2006.173.04:34:43.78#ibcon#read 4, iclass 21, count 0 2006.173.04:34:43.78#ibcon#about to read 5, iclass 21, count 0 2006.173.04:34:43.78#ibcon#read 5, iclass 21, count 0 2006.173.04:34:43.78#ibcon#about to read 6, iclass 21, count 0 2006.173.04:34:43.78#ibcon#read 6, iclass 21, count 0 2006.173.04:34:43.78#ibcon#end of sib2, iclass 21, count 0 2006.173.04:34:43.78#ibcon#*after write, iclass 21, count 0 2006.173.04:34:43.78#ibcon#*before return 0, iclass 21, count 0 2006.173.04:34:43.78#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.04:34:43.78#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.04:34:43.78#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.04:34:43.78#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.04:34:43.78$vck44/vblo=7,734.99 2006.173.04:34:43.78#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.04:34:43.78#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.04:34:43.78#ibcon#ireg 17 cls_cnt 0 2006.173.04:34:43.78#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.04:34:43.78#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.04:34:43.78#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.04:34:43.78#ibcon#enter wrdev, iclass 23, count 0 2006.173.04:34:43.78#ibcon#first serial, iclass 23, count 0 2006.173.04:34:43.78#ibcon#enter sib2, iclass 23, count 0 2006.173.04:34:43.78#ibcon#flushed, iclass 23, count 0 2006.173.04:34:43.78#ibcon#about to write, iclass 23, count 0 2006.173.04:34:43.78#ibcon#wrote, iclass 23, count 0 2006.173.04:34:43.78#ibcon#about to read 3, iclass 23, count 0 2006.173.04:34:43.80#ibcon#read 3, iclass 23, count 0 2006.173.04:34:43.80#ibcon#about to read 4, iclass 23, count 0 2006.173.04:34:43.80#ibcon#read 4, iclass 23, count 0 2006.173.04:34:43.80#ibcon#about to read 5, iclass 23, count 0 2006.173.04:34:43.80#ibcon#read 5, iclass 23, count 0 2006.173.04:34:43.80#ibcon#about to read 6, iclass 23, count 0 2006.173.04:34:43.80#ibcon#read 6, iclass 23, count 0 2006.173.04:34:43.80#ibcon#end of sib2, iclass 23, count 0 2006.173.04:34:43.80#ibcon#*mode == 0, iclass 23, count 0 2006.173.04:34:43.80#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.04:34:43.80#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.04:34:43.80#ibcon#*before write, iclass 23, count 0 2006.173.04:34:43.80#ibcon#enter sib2, iclass 23, count 0 2006.173.04:34:43.80#ibcon#flushed, iclass 23, count 0 2006.173.04:34:43.80#ibcon#about to write, iclass 23, count 0 2006.173.04:34:43.80#ibcon#wrote, iclass 23, count 0 2006.173.04:34:43.80#ibcon#about to read 3, iclass 23, count 0 2006.173.04:34:43.84#ibcon#read 3, iclass 23, count 0 2006.173.04:34:43.84#ibcon#about to read 4, iclass 23, count 0 2006.173.04:34:43.84#ibcon#read 4, iclass 23, count 0 2006.173.04:34:43.84#ibcon#about to read 5, iclass 23, count 0 2006.173.04:34:43.84#ibcon#read 5, iclass 23, count 0 2006.173.04:34:43.84#ibcon#about to read 6, iclass 23, count 0 2006.173.04:34:43.84#ibcon#read 6, iclass 23, count 0 2006.173.04:34:43.84#ibcon#end of sib2, iclass 23, count 0 2006.173.04:34:43.84#ibcon#*after write, iclass 23, count 0 2006.173.04:34:43.84#ibcon#*before return 0, iclass 23, count 0 2006.173.04:34:43.84#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.04:34:43.84#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.04:34:43.84#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.04:34:43.84#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.04:34:43.84$vck44/vb=7,4 2006.173.04:34:43.84#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.04:34:43.84#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.04:34:43.84#ibcon#ireg 11 cls_cnt 2 2006.173.04:34:43.84#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.04:34:43.90#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.04:34:43.90#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.04:34:43.90#ibcon#enter wrdev, iclass 25, count 2 2006.173.04:34:43.90#ibcon#first serial, iclass 25, count 2 2006.173.04:34:43.90#ibcon#enter sib2, iclass 25, count 2 2006.173.04:34:43.90#ibcon#flushed, iclass 25, count 2 2006.173.04:34:43.90#ibcon#about to write, iclass 25, count 2 2006.173.04:34:43.90#ibcon#wrote, iclass 25, count 2 2006.173.04:34:43.90#ibcon#about to read 3, iclass 25, count 2 2006.173.04:34:43.92#ibcon#read 3, iclass 25, count 2 2006.173.04:34:43.92#ibcon#about to read 4, iclass 25, count 2 2006.173.04:34:43.92#ibcon#read 4, iclass 25, count 2 2006.173.04:34:43.92#ibcon#about to read 5, iclass 25, count 2 2006.173.04:34:43.92#ibcon#read 5, iclass 25, count 2 2006.173.04:34:43.92#ibcon#about to read 6, iclass 25, count 2 2006.173.04:34:43.92#ibcon#read 6, iclass 25, count 2 2006.173.04:34:43.92#ibcon#end of sib2, iclass 25, count 2 2006.173.04:34:43.92#ibcon#*mode == 0, iclass 25, count 2 2006.173.04:34:43.92#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.04:34:43.92#ibcon#[27=AT07-04\r\n] 2006.173.04:34:43.92#ibcon#*before write, iclass 25, count 2 2006.173.04:34:43.92#ibcon#enter sib2, iclass 25, count 2 2006.173.04:34:43.92#ibcon#flushed, iclass 25, count 2 2006.173.04:34:43.92#ibcon#about to write, iclass 25, count 2 2006.173.04:34:43.92#ibcon#wrote, iclass 25, count 2 2006.173.04:34:43.92#ibcon#about to read 3, iclass 25, count 2 2006.173.04:34:43.95#ibcon#read 3, iclass 25, count 2 2006.173.04:34:43.95#ibcon#about to read 4, iclass 25, count 2 2006.173.04:34:43.95#ibcon#read 4, iclass 25, count 2 2006.173.04:34:43.95#ibcon#about to read 5, iclass 25, count 2 2006.173.04:34:43.95#ibcon#read 5, iclass 25, count 2 2006.173.04:34:43.95#ibcon#about to read 6, iclass 25, count 2 2006.173.04:34:43.95#ibcon#read 6, iclass 25, count 2 2006.173.04:34:43.95#ibcon#end of sib2, iclass 25, count 2 2006.173.04:34:43.95#ibcon#*after write, iclass 25, count 2 2006.173.04:34:43.95#ibcon#*before return 0, iclass 25, count 2 2006.173.04:34:43.95#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.04:34:43.95#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.04:34:43.95#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.04:34:43.95#ibcon#ireg 7 cls_cnt 0 2006.173.04:34:43.95#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.04:34:44.07#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.04:34:44.07#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.04:34:44.07#ibcon#enter wrdev, iclass 25, count 0 2006.173.04:34:44.07#ibcon#first serial, iclass 25, count 0 2006.173.04:34:44.07#ibcon#enter sib2, iclass 25, count 0 2006.173.04:34:44.07#ibcon#flushed, iclass 25, count 0 2006.173.04:34:44.07#ibcon#about to write, iclass 25, count 0 2006.173.04:34:44.07#ibcon#wrote, iclass 25, count 0 2006.173.04:34:44.07#ibcon#about to read 3, iclass 25, count 0 2006.173.04:34:44.09#ibcon#read 3, iclass 25, count 0 2006.173.04:34:44.09#ibcon#about to read 4, iclass 25, count 0 2006.173.04:34:44.09#ibcon#read 4, iclass 25, count 0 2006.173.04:34:44.09#ibcon#about to read 5, iclass 25, count 0 2006.173.04:34:44.09#ibcon#read 5, iclass 25, count 0 2006.173.04:34:44.09#ibcon#about to read 6, iclass 25, count 0 2006.173.04:34:44.09#ibcon#read 6, iclass 25, count 0 2006.173.04:34:44.09#ibcon#end of sib2, iclass 25, count 0 2006.173.04:34:44.09#ibcon#*mode == 0, iclass 25, count 0 2006.173.04:34:44.09#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.04:34:44.09#ibcon#[27=USB\r\n] 2006.173.04:34:44.09#ibcon#*before write, iclass 25, count 0 2006.173.04:34:44.09#ibcon#enter sib2, iclass 25, count 0 2006.173.04:34:44.09#ibcon#flushed, iclass 25, count 0 2006.173.04:34:44.09#ibcon#about to write, iclass 25, count 0 2006.173.04:34:44.09#ibcon#wrote, iclass 25, count 0 2006.173.04:34:44.09#ibcon#about to read 3, iclass 25, count 0 2006.173.04:34:44.12#ibcon#read 3, iclass 25, count 0 2006.173.04:34:44.12#ibcon#about to read 4, iclass 25, count 0 2006.173.04:34:44.12#ibcon#read 4, iclass 25, count 0 2006.173.04:34:44.12#ibcon#about to read 5, iclass 25, count 0 2006.173.04:34:44.12#ibcon#read 5, iclass 25, count 0 2006.173.04:34:44.12#ibcon#about to read 6, iclass 25, count 0 2006.173.04:34:44.12#ibcon#read 6, iclass 25, count 0 2006.173.04:34:44.12#ibcon#end of sib2, iclass 25, count 0 2006.173.04:34:44.12#ibcon#*after write, iclass 25, count 0 2006.173.04:34:44.12#ibcon#*before return 0, iclass 25, count 0 2006.173.04:34:44.12#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.04:34:44.12#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.04:34:44.12#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.04:34:44.12#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.04:34:44.12$vck44/vblo=8,744.99 2006.173.04:34:44.12#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.04:34:44.12#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.04:34:44.12#ibcon#ireg 17 cls_cnt 0 2006.173.04:34:44.12#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.04:34:44.12#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.04:34:44.12#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.04:34:44.12#ibcon#enter wrdev, iclass 27, count 0 2006.173.04:34:44.12#ibcon#first serial, iclass 27, count 0 2006.173.04:34:44.12#ibcon#enter sib2, iclass 27, count 0 2006.173.04:34:44.12#ibcon#flushed, iclass 27, count 0 2006.173.04:34:44.12#ibcon#about to write, iclass 27, count 0 2006.173.04:34:44.12#ibcon#wrote, iclass 27, count 0 2006.173.04:34:44.12#ibcon#about to read 3, iclass 27, count 0 2006.173.04:34:44.14#ibcon#read 3, iclass 27, count 0 2006.173.04:34:44.14#ibcon#about to read 4, iclass 27, count 0 2006.173.04:34:44.14#ibcon#read 4, iclass 27, count 0 2006.173.04:34:44.14#ibcon#about to read 5, iclass 27, count 0 2006.173.04:34:44.14#ibcon#read 5, iclass 27, count 0 2006.173.04:34:44.14#ibcon#about to read 6, iclass 27, count 0 2006.173.04:34:44.14#ibcon#read 6, iclass 27, count 0 2006.173.04:34:44.14#ibcon#end of sib2, iclass 27, count 0 2006.173.04:34:44.14#ibcon#*mode == 0, iclass 27, count 0 2006.173.04:34:44.14#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.04:34:44.14#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.04:34:44.14#ibcon#*before write, iclass 27, count 0 2006.173.04:34:44.14#ibcon#enter sib2, iclass 27, count 0 2006.173.04:34:44.14#ibcon#flushed, iclass 27, count 0 2006.173.04:34:44.14#ibcon#about to write, iclass 27, count 0 2006.173.04:34:44.14#ibcon#wrote, iclass 27, count 0 2006.173.04:34:44.14#ibcon#about to read 3, iclass 27, count 0 2006.173.04:34:44.18#ibcon#read 3, iclass 27, count 0 2006.173.04:34:44.18#ibcon#about to read 4, iclass 27, count 0 2006.173.04:34:44.18#ibcon#read 4, iclass 27, count 0 2006.173.04:34:44.18#ibcon#about to read 5, iclass 27, count 0 2006.173.04:34:44.18#ibcon#read 5, iclass 27, count 0 2006.173.04:34:44.18#ibcon#about to read 6, iclass 27, count 0 2006.173.04:34:44.18#ibcon#read 6, iclass 27, count 0 2006.173.04:34:44.18#ibcon#end of sib2, iclass 27, count 0 2006.173.04:34:44.18#ibcon#*after write, iclass 27, count 0 2006.173.04:34:44.18#ibcon#*before return 0, iclass 27, count 0 2006.173.04:34:44.18#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.04:34:44.18#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.04:34:44.18#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.04:34:44.18#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.04:34:44.18$vck44/vb=8,4 2006.173.04:34:44.18#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.04:34:44.18#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.04:34:44.18#ibcon#ireg 11 cls_cnt 2 2006.173.04:34:44.18#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.04:34:44.24#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.04:34:44.24#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.04:34:44.24#ibcon#enter wrdev, iclass 29, count 2 2006.173.04:34:44.24#ibcon#first serial, iclass 29, count 2 2006.173.04:34:44.24#ibcon#enter sib2, iclass 29, count 2 2006.173.04:34:44.24#ibcon#flushed, iclass 29, count 2 2006.173.04:34:44.24#ibcon#about to write, iclass 29, count 2 2006.173.04:34:44.24#ibcon#wrote, iclass 29, count 2 2006.173.04:34:44.24#ibcon#about to read 3, iclass 29, count 2 2006.173.04:34:44.26#ibcon#read 3, iclass 29, count 2 2006.173.04:34:44.26#ibcon#about to read 4, iclass 29, count 2 2006.173.04:34:44.26#ibcon#read 4, iclass 29, count 2 2006.173.04:34:44.26#ibcon#about to read 5, iclass 29, count 2 2006.173.04:34:44.26#ibcon#read 5, iclass 29, count 2 2006.173.04:34:44.26#ibcon#about to read 6, iclass 29, count 2 2006.173.04:34:44.26#ibcon#read 6, iclass 29, count 2 2006.173.04:34:44.26#ibcon#end of sib2, iclass 29, count 2 2006.173.04:34:44.26#ibcon#*mode == 0, iclass 29, count 2 2006.173.04:34:44.26#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.04:34:44.26#ibcon#[27=AT08-04\r\n] 2006.173.04:34:44.26#ibcon#*before write, iclass 29, count 2 2006.173.04:34:44.26#ibcon#enter sib2, iclass 29, count 2 2006.173.04:34:44.26#ibcon#flushed, iclass 29, count 2 2006.173.04:34:44.26#ibcon#about to write, iclass 29, count 2 2006.173.04:34:44.26#ibcon#wrote, iclass 29, count 2 2006.173.04:34:44.26#ibcon#about to read 3, iclass 29, count 2 2006.173.04:34:44.29#ibcon#read 3, iclass 29, count 2 2006.173.04:34:44.29#ibcon#about to read 4, iclass 29, count 2 2006.173.04:34:44.29#ibcon#read 4, iclass 29, count 2 2006.173.04:34:44.29#ibcon#about to read 5, iclass 29, count 2 2006.173.04:34:44.29#ibcon#read 5, iclass 29, count 2 2006.173.04:34:44.29#ibcon#about to read 6, iclass 29, count 2 2006.173.04:34:44.29#ibcon#read 6, iclass 29, count 2 2006.173.04:34:44.29#ibcon#end of sib2, iclass 29, count 2 2006.173.04:34:44.29#ibcon#*after write, iclass 29, count 2 2006.173.04:34:44.29#ibcon#*before return 0, iclass 29, count 2 2006.173.04:34:44.29#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.04:34:44.29#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.04:34:44.29#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.04:34:44.29#ibcon#ireg 7 cls_cnt 0 2006.173.04:34:44.29#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.04:34:44.41#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.04:34:44.41#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.04:34:44.41#ibcon#enter wrdev, iclass 29, count 0 2006.173.04:34:44.41#ibcon#first serial, iclass 29, count 0 2006.173.04:34:44.41#ibcon#enter sib2, iclass 29, count 0 2006.173.04:34:44.41#ibcon#flushed, iclass 29, count 0 2006.173.04:34:44.41#ibcon#about to write, iclass 29, count 0 2006.173.04:34:44.41#ibcon#wrote, iclass 29, count 0 2006.173.04:34:44.41#ibcon#about to read 3, iclass 29, count 0 2006.173.04:34:44.43#ibcon#read 3, iclass 29, count 0 2006.173.04:34:44.43#ibcon#about to read 4, iclass 29, count 0 2006.173.04:34:44.43#ibcon#read 4, iclass 29, count 0 2006.173.04:34:44.43#ibcon#about to read 5, iclass 29, count 0 2006.173.04:34:44.43#ibcon#read 5, iclass 29, count 0 2006.173.04:34:44.43#ibcon#about to read 6, iclass 29, count 0 2006.173.04:34:44.43#ibcon#read 6, iclass 29, count 0 2006.173.04:34:44.43#ibcon#end of sib2, iclass 29, count 0 2006.173.04:34:44.43#ibcon#*mode == 0, iclass 29, count 0 2006.173.04:34:44.43#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.04:34:44.43#ibcon#[27=USB\r\n] 2006.173.04:34:44.43#ibcon#*before write, iclass 29, count 0 2006.173.04:34:44.43#ibcon#enter sib2, iclass 29, count 0 2006.173.04:34:44.43#ibcon#flushed, iclass 29, count 0 2006.173.04:34:44.43#ibcon#about to write, iclass 29, count 0 2006.173.04:34:44.43#ibcon#wrote, iclass 29, count 0 2006.173.04:34:44.43#ibcon#about to read 3, iclass 29, count 0 2006.173.04:34:44.46#ibcon#read 3, iclass 29, count 0 2006.173.04:34:44.46#ibcon#about to read 4, iclass 29, count 0 2006.173.04:34:44.46#ibcon#read 4, iclass 29, count 0 2006.173.04:34:44.46#ibcon#about to read 5, iclass 29, count 0 2006.173.04:34:44.46#ibcon#read 5, iclass 29, count 0 2006.173.04:34:44.46#ibcon#about to read 6, iclass 29, count 0 2006.173.04:34:44.46#ibcon#read 6, iclass 29, count 0 2006.173.04:34:44.46#ibcon#end of sib2, iclass 29, count 0 2006.173.04:34:44.46#ibcon#*after write, iclass 29, count 0 2006.173.04:34:44.46#ibcon#*before return 0, iclass 29, count 0 2006.173.04:34:44.46#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.04:34:44.46#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.04:34:44.46#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.04:34:44.46#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.04:34:44.46$vck44/vabw=wide 2006.173.04:34:44.46#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.04:34:44.46#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.04:34:44.46#ibcon#ireg 8 cls_cnt 0 2006.173.04:34:44.46#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.04:34:44.46#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.04:34:44.46#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.04:34:44.46#ibcon#enter wrdev, iclass 31, count 0 2006.173.04:34:44.46#ibcon#first serial, iclass 31, count 0 2006.173.04:34:44.46#ibcon#enter sib2, iclass 31, count 0 2006.173.04:34:44.46#ibcon#flushed, iclass 31, count 0 2006.173.04:34:44.46#ibcon#about to write, iclass 31, count 0 2006.173.04:34:44.46#ibcon#wrote, iclass 31, count 0 2006.173.04:34:44.46#ibcon#about to read 3, iclass 31, count 0 2006.173.04:34:44.48#ibcon#read 3, iclass 31, count 0 2006.173.04:34:44.48#ibcon#about to read 4, iclass 31, count 0 2006.173.04:34:44.48#ibcon#read 4, iclass 31, count 0 2006.173.04:34:44.48#ibcon#about to read 5, iclass 31, count 0 2006.173.04:34:44.48#ibcon#read 5, iclass 31, count 0 2006.173.04:34:44.48#ibcon#about to read 6, iclass 31, count 0 2006.173.04:34:44.48#ibcon#read 6, iclass 31, count 0 2006.173.04:34:44.48#ibcon#end of sib2, iclass 31, count 0 2006.173.04:34:44.48#ibcon#*mode == 0, iclass 31, count 0 2006.173.04:34:44.48#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.04:34:44.48#ibcon#[25=BW32\r\n] 2006.173.04:34:44.48#ibcon#*before write, iclass 31, count 0 2006.173.04:34:44.48#ibcon#enter sib2, iclass 31, count 0 2006.173.04:34:44.48#ibcon#flushed, iclass 31, count 0 2006.173.04:34:44.48#ibcon#about to write, iclass 31, count 0 2006.173.04:34:44.48#ibcon#wrote, iclass 31, count 0 2006.173.04:34:44.48#ibcon#about to read 3, iclass 31, count 0 2006.173.04:34:44.51#ibcon#read 3, iclass 31, count 0 2006.173.04:34:44.51#ibcon#about to read 4, iclass 31, count 0 2006.173.04:34:44.51#ibcon#read 4, iclass 31, count 0 2006.173.04:34:44.51#ibcon#about to read 5, iclass 31, count 0 2006.173.04:34:44.51#ibcon#read 5, iclass 31, count 0 2006.173.04:34:44.51#ibcon#about to read 6, iclass 31, count 0 2006.173.04:34:44.51#ibcon#read 6, iclass 31, count 0 2006.173.04:34:44.51#ibcon#end of sib2, iclass 31, count 0 2006.173.04:34:44.51#ibcon#*after write, iclass 31, count 0 2006.173.04:34:44.51#ibcon#*before return 0, iclass 31, count 0 2006.173.04:34:44.51#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.04:34:44.51#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.04:34:44.51#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.04:34:44.51#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.04:34:44.51$vck44/vbbw=wide 2006.173.04:34:44.51#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.04:34:44.51#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.04:34:44.51#ibcon#ireg 8 cls_cnt 0 2006.173.04:34:44.51#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.04:34:44.58#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.04:34:44.58#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.04:34:44.58#ibcon#enter wrdev, iclass 33, count 0 2006.173.04:34:44.58#ibcon#first serial, iclass 33, count 0 2006.173.04:34:44.58#ibcon#enter sib2, iclass 33, count 0 2006.173.04:34:44.58#ibcon#flushed, iclass 33, count 0 2006.173.04:34:44.58#ibcon#about to write, iclass 33, count 0 2006.173.04:34:44.58#ibcon#wrote, iclass 33, count 0 2006.173.04:34:44.58#ibcon#about to read 3, iclass 33, count 0 2006.173.04:34:44.60#ibcon#read 3, iclass 33, count 0 2006.173.04:34:44.60#ibcon#about to read 4, iclass 33, count 0 2006.173.04:34:44.60#ibcon#read 4, iclass 33, count 0 2006.173.04:34:44.60#ibcon#about to read 5, iclass 33, count 0 2006.173.04:34:44.60#ibcon#read 5, iclass 33, count 0 2006.173.04:34:44.60#ibcon#about to read 6, iclass 33, count 0 2006.173.04:34:44.60#ibcon#read 6, iclass 33, count 0 2006.173.04:34:44.60#ibcon#end of sib2, iclass 33, count 0 2006.173.04:34:44.60#ibcon#*mode == 0, iclass 33, count 0 2006.173.04:34:44.60#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.04:34:44.60#ibcon#[27=BW32\r\n] 2006.173.04:34:44.60#ibcon#*before write, iclass 33, count 0 2006.173.04:34:44.60#ibcon#enter sib2, iclass 33, count 0 2006.173.04:34:44.60#ibcon#flushed, iclass 33, count 0 2006.173.04:34:44.60#ibcon#about to write, iclass 33, count 0 2006.173.04:34:44.60#ibcon#wrote, iclass 33, count 0 2006.173.04:34:44.60#ibcon#about to read 3, iclass 33, count 0 2006.173.04:34:44.63#ibcon#read 3, iclass 33, count 0 2006.173.04:34:44.63#ibcon#about to read 4, iclass 33, count 0 2006.173.04:34:44.63#ibcon#read 4, iclass 33, count 0 2006.173.04:34:44.63#ibcon#about to read 5, iclass 33, count 0 2006.173.04:34:44.63#ibcon#read 5, iclass 33, count 0 2006.173.04:34:44.63#ibcon#about to read 6, iclass 33, count 0 2006.173.04:34:44.63#ibcon#read 6, iclass 33, count 0 2006.173.04:34:44.63#ibcon#end of sib2, iclass 33, count 0 2006.173.04:34:44.63#ibcon#*after write, iclass 33, count 0 2006.173.04:34:44.63#ibcon#*before return 0, iclass 33, count 0 2006.173.04:34:44.63#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.04:34:44.63#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.04:34:44.63#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.04:34:44.63#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.04:34:44.63$setupk4/ifdk4 2006.173.04:34:44.63$ifdk4/lo= 2006.173.04:34:44.63$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.04:34:44.63$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.04:34:44.63$ifdk4/patch= 2006.173.04:34:44.63$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.04:34:44.63$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.04:34:44.63$setupk4/!*+20s 2006.173.04:34:47.69#abcon#<5=/15 1.0 2.4 23.36 801005.9\r\n> 2006.173.04:34:47.71#abcon#{5=INTERFACE CLEAR} 2006.173.04:34:47.77#abcon#[5=S1D000X0/0*\r\n] 2006.173.04:34:58.00#abcon#<5=/15 1.0 2.4 23.37 781005.9\r\n> 2006.173.04:34:58.02#abcon#{5=INTERFACE CLEAR} 2006.173.04:34:58.08#abcon#[5=S1D000X0/0*\r\n] 2006.173.04:34:59.14$setupk4/"tpicd 2006.173.04:34:59.14$setupk4/echo=off 2006.173.04:34:59.14$setupk4/xlog=off 2006.173.04:34:59.14:!2006.173.04:36:24 2006.173.04:35:01.14#trakl#Source acquired 2006.173.04:35:02.14#flagr#flagr/antenna,acquired 2006.173.04:36:24.00:preob 2006.173.04:36:24.14/onsource/TRACKING 2006.173.04:36:24.14:!2006.173.04:36:34 2006.173.04:36:34.00:"tape 2006.173.04:36:34.00:"st=record 2006.173.04:36:34.00:data_valid=on 2006.173.04:36:34.00:midob 2006.173.04:36:35.14/onsource/TRACKING 2006.173.04:36:35.14/wx/23.38,1005.8,79 2006.173.04:36:35.29/cable/+6.5086E-03 2006.173.04:36:36.38/va/01,07,usb,yes,37,40 2006.173.04:36:36.38/va/02,06,usb,yes,37,38 2006.173.04:36:36.38/va/03,05,usb,yes,47,49 2006.173.04:36:36.38/va/04,06,usb,yes,37,40 2006.173.04:36:36.38/va/05,04,usb,yes,29,30 2006.173.04:36:36.38/va/06,03,usb,yes,41,41 2006.173.04:36:36.38/va/07,04,usb,yes,33,35 2006.173.04:36:36.38/va/08,04,usb,yes,28,34 2006.173.04:36:36.61/valo/01,524.99,yes,locked 2006.173.04:36:36.61/valo/02,534.99,yes,locked 2006.173.04:36:36.61/valo/03,564.99,yes,locked 2006.173.04:36:36.61/valo/04,624.99,yes,locked 2006.173.04:36:36.61/valo/05,734.99,yes,locked 2006.173.04:36:36.61/valo/06,814.99,yes,locked 2006.173.04:36:36.61/valo/07,864.99,yes,locked 2006.173.04:36:36.61/valo/08,884.99,yes,locked 2006.173.04:36:37.70/vb/01,04,usb,yes,31,28 2006.173.04:36:37.70/vb/02,04,usb,yes,33,33 2006.173.04:36:37.70/vb/03,04,usb,yes,30,33 2006.173.04:36:37.70/vb/04,04,usb,yes,34,33 2006.173.04:36:37.70/vb/05,04,usb,yes,27,29 2006.173.04:36:37.70/vb/06,04,usb,yes,31,27 2006.173.04:36:37.70/vb/07,04,usb,yes,31,31 2006.173.04:36:37.70/vb/08,04,usb,yes,28,32 2006.173.04:36:37.94/vblo/01,629.99,yes,locked 2006.173.04:36:37.94/vblo/02,634.99,yes,locked 2006.173.04:36:37.94/vblo/03,649.99,yes,locked 2006.173.04:36:37.94/vblo/04,679.99,yes,locked 2006.173.04:36:37.94/vblo/05,709.99,yes,locked 2006.173.04:36:37.94/vblo/06,719.99,yes,locked 2006.173.04:36:37.94/vblo/07,734.99,yes,locked 2006.173.04:36:37.94/vblo/08,744.99,yes,locked 2006.173.04:36:38.09/vabw/8 2006.173.04:36:38.24/vbbw/8 2006.173.04:36:38.33/xfe/off,on,14.5 2006.173.04:36:38.72/ifatt/23,28,28,28 2006.173.04:36:39.08/fmout-gps/S +3.94E-07 2006.173.04:36:39.12:!2006.173.04:42:04 2006.173.04:42:04.00:data_valid=off 2006.173.04:42:04.01:"et 2006.173.04:42:04.01:!+3s 2006.173.04:42:07.03:"tape 2006.173.04:42:07.03:postob 2006.173.04:42:07.16/cable/+6.5075E-03 2006.173.04:42:07.17/wx/23.43,1005.8,76 2006.173.04:42:07.22/fmout-gps/S +3.93E-07 2006.173.04:42:07.22:scan_name=173-0455,jd0606,690 2006.173.04:42:07.23:source=0133+476,013658.59,475129.1,2000.0,cw 2006.173.04:42:08.14#flagr#flagr/antenna,new-source 2006.173.04:42:08.15:checkk5 2006.173.04:42:08.55/chk_autoobs//k5ts1/ autoobs is running! 2006.173.04:42:08.94/chk_autoobs//k5ts2/ autoobs is running! 2006.173.04:42:09.35/chk_autoobs//k5ts3/ autoobs is running! 2006.173.04:42:09.73/chk_autoobs//k5ts4/ autoobs is running! 2006.173.04:42:10.12/chk_obsdata//k5ts1/T1730436??a.dat file size is correct (nominal:1320MB, actual:1316MB). 2006.173.04:42:10.50/chk_obsdata//k5ts2/T1730436??b.dat file size is correct (nominal:1320MB, actual:1316MB). 2006.173.04:42:10.91/chk_obsdata//k5ts3/T1730436??c.dat file size is correct (nominal:1320MB, actual:1316MB). 2006.173.04:42:11.32/chk_obsdata//k5ts4/T1730436??d.dat file size is correct (nominal:1320MB, actual:1316MB). 2006.173.04:42:12.04/k5log//k5ts1_log_newline 2006.173.04:42:12.74/k5log//k5ts2_log_newline 2006.173.04:42:13.45/k5log//k5ts3_log_newline 2006.173.04:42:14.16/k5log//k5ts4_log_newline 2006.173.04:42:14.18/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.04:42:14.18:setupk4=1 2006.173.04:42:14.18$setupk4/echo=on 2006.173.04:42:14.18$setupk4/pcalon 2006.173.04:42:14.18$pcalon/"no phase cal control is implemented here 2006.173.04:42:14.18$setupk4/"tpicd=stop 2006.173.04:42:14.18$setupk4/"rec=synch_on 2006.173.04:42:14.18$setupk4/"rec_mode=128 2006.173.04:42:14.18$setupk4/!* 2006.173.04:42:14.18$setupk4/recpk4 2006.173.04:42:14.18$recpk4/recpatch= 2006.173.04:42:14.19$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.04:42:14.19$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.04:42:14.19$setupk4/vck44 2006.173.04:42:14.19$vck44/valo=1,524.99 2006.173.04:42:14.19#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.04:42:14.19#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.04:42:14.19#ibcon#ireg 17 cls_cnt 0 2006.173.04:42:14.19#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.04:42:14.19#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.04:42:14.19#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.04:42:14.19#ibcon#enter wrdev, iclass 34, count 0 2006.173.04:42:14.19#ibcon#first serial, iclass 34, count 0 2006.173.04:42:14.19#ibcon#enter sib2, iclass 34, count 0 2006.173.04:42:14.19#ibcon#flushed, iclass 34, count 0 2006.173.04:42:14.19#ibcon#about to write, iclass 34, count 0 2006.173.04:42:14.19#ibcon#wrote, iclass 34, count 0 2006.173.04:42:14.19#ibcon#about to read 3, iclass 34, count 0 2006.173.04:42:14.20#ibcon#read 3, iclass 34, count 0 2006.173.04:42:14.20#ibcon#about to read 4, iclass 34, count 0 2006.173.04:42:14.20#ibcon#read 4, iclass 34, count 0 2006.173.04:42:14.20#ibcon#about to read 5, iclass 34, count 0 2006.173.04:42:14.20#ibcon#read 5, iclass 34, count 0 2006.173.04:42:14.20#ibcon#about to read 6, iclass 34, count 0 2006.173.04:42:14.20#ibcon#read 6, iclass 34, count 0 2006.173.04:42:14.20#ibcon#end of sib2, iclass 34, count 0 2006.173.04:42:14.20#ibcon#*mode == 0, iclass 34, count 0 2006.173.04:42:14.20#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.04:42:14.20#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.04:42:14.20#ibcon#*before write, iclass 34, count 0 2006.173.04:42:14.20#ibcon#enter sib2, iclass 34, count 0 2006.173.04:42:14.20#ibcon#flushed, iclass 34, count 0 2006.173.04:42:14.20#ibcon#about to write, iclass 34, count 0 2006.173.04:42:14.20#ibcon#wrote, iclass 34, count 0 2006.173.04:42:14.20#ibcon#about to read 3, iclass 34, count 0 2006.173.04:42:14.25#ibcon#read 3, iclass 34, count 0 2006.173.04:42:14.25#ibcon#about to read 4, iclass 34, count 0 2006.173.04:42:14.25#ibcon#read 4, iclass 34, count 0 2006.173.04:42:14.25#ibcon#about to read 5, iclass 34, count 0 2006.173.04:42:14.25#ibcon#read 5, iclass 34, count 0 2006.173.04:42:14.25#ibcon#about to read 6, iclass 34, count 0 2006.173.04:42:14.25#ibcon#read 6, iclass 34, count 0 2006.173.04:42:14.25#ibcon#end of sib2, iclass 34, count 0 2006.173.04:42:14.25#ibcon#*after write, iclass 34, count 0 2006.173.04:42:14.25#ibcon#*before return 0, iclass 34, count 0 2006.173.04:42:14.25#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.04:42:14.25#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.04:42:14.25#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.04:42:14.25#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.04:42:14.25$vck44/va=1,7 2006.173.04:42:14.25#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.04:42:14.25#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.04:42:14.25#ibcon#ireg 11 cls_cnt 2 2006.173.04:42:14.25#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.04:42:14.25#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.04:42:14.25#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.04:42:14.25#ibcon#enter wrdev, iclass 36, count 2 2006.173.04:42:14.25#ibcon#first serial, iclass 36, count 2 2006.173.04:42:14.25#ibcon#enter sib2, iclass 36, count 2 2006.173.04:42:14.25#ibcon#flushed, iclass 36, count 2 2006.173.04:42:14.25#ibcon#about to write, iclass 36, count 2 2006.173.04:42:14.25#ibcon#wrote, iclass 36, count 2 2006.173.04:42:14.25#ibcon#about to read 3, iclass 36, count 2 2006.173.04:42:14.27#ibcon#read 3, iclass 36, count 2 2006.173.04:42:14.27#ibcon#about to read 4, iclass 36, count 2 2006.173.04:42:14.27#ibcon#read 4, iclass 36, count 2 2006.173.04:42:14.27#ibcon#about to read 5, iclass 36, count 2 2006.173.04:42:14.27#ibcon#read 5, iclass 36, count 2 2006.173.04:42:14.27#ibcon#about to read 6, iclass 36, count 2 2006.173.04:42:14.27#ibcon#read 6, iclass 36, count 2 2006.173.04:42:14.27#ibcon#end of sib2, iclass 36, count 2 2006.173.04:42:14.27#ibcon#*mode == 0, iclass 36, count 2 2006.173.04:42:14.27#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.04:42:14.27#ibcon#[25=AT01-07\r\n] 2006.173.04:42:14.27#ibcon#*before write, iclass 36, count 2 2006.173.04:42:14.27#ibcon#enter sib2, iclass 36, count 2 2006.173.04:42:14.27#ibcon#flushed, iclass 36, count 2 2006.173.04:42:14.27#ibcon#about to write, iclass 36, count 2 2006.173.04:42:14.27#ibcon#wrote, iclass 36, count 2 2006.173.04:42:14.27#ibcon#about to read 3, iclass 36, count 2 2006.173.04:42:14.30#ibcon#read 3, iclass 36, count 2 2006.173.04:42:14.30#ibcon#about to read 4, iclass 36, count 2 2006.173.04:42:14.30#ibcon#read 4, iclass 36, count 2 2006.173.04:42:14.30#ibcon#about to read 5, iclass 36, count 2 2006.173.04:42:14.30#ibcon#read 5, iclass 36, count 2 2006.173.04:42:14.30#ibcon#about to read 6, iclass 36, count 2 2006.173.04:42:14.30#ibcon#read 6, iclass 36, count 2 2006.173.04:42:14.30#ibcon#end of sib2, iclass 36, count 2 2006.173.04:42:14.30#ibcon#*after write, iclass 36, count 2 2006.173.04:42:14.30#ibcon#*before return 0, iclass 36, count 2 2006.173.04:42:14.30#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.04:42:14.30#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.04:42:14.30#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.04:42:14.30#ibcon#ireg 7 cls_cnt 0 2006.173.04:42:14.30#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.04:42:14.42#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.04:42:14.42#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.04:42:14.42#ibcon#enter wrdev, iclass 36, count 0 2006.173.04:42:14.42#ibcon#first serial, iclass 36, count 0 2006.173.04:42:14.42#ibcon#enter sib2, iclass 36, count 0 2006.173.04:42:14.42#ibcon#flushed, iclass 36, count 0 2006.173.04:42:14.42#ibcon#about to write, iclass 36, count 0 2006.173.04:42:14.42#ibcon#wrote, iclass 36, count 0 2006.173.04:42:14.42#ibcon#about to read 3, iclass 36, count 0 2006.173.04:42:14.44#ibcon#read 3, iclass 36, count 0 2006.173.04:42:14.44#ibcon#about to read 4, iclass 36, count 0 2006.173.04:42:14.44#ibcon#read 4, iclass 36, count 0 2006.173.04:42:14.44#ibcon#about to read 5, iclass 36, count 0 2006.173.04:42:14.44#ibcon#read 5, iclass 36, count 0 2006.173.04:42:14.44#ibcon#about to read 6, iclass 36, count 0 2006.173.04:42:14.44#ibcon#read 6, iclass 36, count 0 2006.173.04:42:14.44#ibcon#end of sib2, iclass 36, count 0 2006.173.04:42:14.44#ibcon#*mode == 0, iclass 36, count 0 2006.173.04:42:14.44#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.04:42:14.44#ibcon#[25=USB\r\n] 2006.173.04:42:14.44#ibcon#*before write, iclass 36, count 0 2006.173.04:42:14.44#ibcon#enter sib2, iclass 36, count 0 2006.173.04:42:14.44#ibcon#flushed, iclass 36, count 0 2006.173.04:42:14.44#ibcon#about to write, iclass 36, count 0 2006.173.04:42:14.44#ibcon#wrote, iclass 36, count 0 2006.173.04:42:14.44#ibcon#about to read 3, iclass 36, count 0 2006.173.04:42:14.47#ibcon#read 3, iclass 36, count 0 2006.173.04:42:14.47#ibcon#about to read 4, iclass 36, count 0 2006.173.04:42:14.47#ibcon#read 4, iclass 36, count 0 2006.173.04:42:14.47#ibcon#about to read 5, iclass 36, count 0 2006.173.04:42:14.47#ibcon#read 5, iclass 36, count 0 2006.173.04:42:14.47#ibcon#about to read 6, iclass 36, count 0 2006.173.04:42:14.47#ibcon#read 6, iclass 36, count 0 2006.173.04:42:14.47#ibcon#end of sib2, iclass 36, count 0 2006.173.04:42:14.47#ibcon#*after write, iclass 36, count 0 2006.173.04:42:14.47#ibcon#*before return 0, iclass 36, count 0 2006.173.04:42:14.47#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.04:42:14.47#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.04:42:14.47#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.04:42:14.47#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.04:42:14.47$vck44/valo=2,534.99 2006.173.04:42:14.47#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.04:42:14.47#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.04:42:14.47#ibcon#ireg 17 cls_cnt 0 2006.173.04:42:14.47#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.04:42:14.47#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.04:42:14.47#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.04:42:14.47#ibcon#enter wrdev, iclass 38, count 0 2006.173.04:42:14.47#ibcon#first serial, iclass 38, count 0 2006.173.04:42:14.47#ibcon#enter sib2, iclass 38, count 0 2006.173.04:42:14.47#ibcon#flushed, iclass 38, count 0 2006.173.04:42:14.47#ibcon#about to write, iclass 38, count 0 2006.173.04:42:14.47#ibcon#wrote, iclass 38, count 0 2006.173.04:42:14.47#ibcon#about to read 3, iclass 38, count 0 2006.173.04:42:14.49#ibcon#read 3, iclass 38, count 0 2006.173.04:42:14.49#ibcon#about to read 4, iclass 38, count 0 2006.173.04:42:14.49#ibcon#read 4, iclass 38, count 0 2006.173.04:42:14.49#ibcon#about to read 5, iclass 38, count 0 2006.173.04:42:14.49#ibcon#read 5, iclass 38, count 0 2006.173.04:42:14.49#ibcon#about to read 6, iclass 38, count 0 2006.173.04:42:14.49#ibcon#read 6, iclass 38, count 0 2006.173.04:42:14.49#ibcon#end of sib2, iclass 38, count 0 2006.173.04:42:14.49#ibcon#*mode == 0, iclass 38, count 0 2006.173.04:42:14.49#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.04:42:14.49#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.04:42:14.49#ibcon#*before write, iclass 38, count 0 2006.173.04:42:14.49#ibcon#enter sib2, iclass 38, count 0 2006.173.04:42:14.49#ibcon#flushed, iclass 38, count 0 2006.173.04:42:14.49#ibcon#about to write, iclass 38, count 0 2006.173.04:42:14.49#ibcon#wrote, iclass 38, count 0 2006.173.04:42:14.49#ibcon#about to read 3, iclass 38, count 0 2006.173.04:42:14.53#ibcon#read 3, iclass 38, count 0 2006.173.04:42:14.53#ibcon#about to read 4, iclass 38, count 0 2006.173.04:42:14.53#ibcon#read 4, iclass 38, count 0 2006.173.04:42:14.53#ibcon#about to read 5, iclass 38, count 0 2006.173.04:42:14.53#ibcon#read 5, iclass 38, count 0 2006.173.04:42:14.53#ibcon#about to read 6, iclass 38, count 0 2006.173.04:42:14.53#ibcon#read 6, iclass 38, count 0 2006.173.04:42:14.53#ibcon#end of sib2, iclass 38, count 0 2006.173.04:42:14.53#ibcon#*after write, iclass 38, count 0 2006.173.04:42:14.53#ibcon#*before return 0, iclass 38, count 0 2006.173.04:42:14.53#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.04:42:14.53#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.04:42:14.53#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.04:42:14.53#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.04:42:14.53$vck44/va=2,6 2006.173.04:42:14.53#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.04:42:14.53#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.04:42:14.53#ibcon#ireg 11 cls_cnt 2 2006.173.04:42:14.53#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.04:42:14.59#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.04:42:14.59#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.04:42:14.59#ibcon#enter wrdev, iclass 40, count 2 2006.173.04:42:14.59#ibcon#first serial, iclass 40, count 2 2006.173.04:42:14.59#ibcon#enter sib2, iclass 40, count 2 2006.173.04:42:14.59#ibcon#flushed, iclass 40, count 2 2006.173.04:42:14.59#ibcon#about to write, iclass 40, count 2 2006.173.04:42:14.59#ibcon#wrote, iclass 40, count 2 2006.173.04:42:14.59#ibcon#about to read 3, iclass 40, count 2 2006.173.04:42:14.61#ibcon#read 3, iclass 40, count 2 2006.173.04:42:14.61#ibcon#about to read 4, iclass 40, count 2 2006.173.04:42:14.61#ibcon#read 4, iclass 40, count 2 2006.173.04:42:14.61#ibcon#about to read 5, iclass 40, count 2 2006.173.04:42:14.61#ibcon#read 5, iclass 40, count 2 2006.173.04:42:14.61#ibcon#about to read 6, iclass 40, count 2 2006.173.04:42:14.61#ibcon#read 6, iclass 40, count 2 2006.173.04:42:14.61#ibcon#end of sib2, iclass 40, count 2 2006.173.04:42:14.61#ibcon#*mode == 0, iclass 40, count 2 2006.173.04:42:14.61#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.04:42:14.61#ibcon#[25=AT02-06\r\n] 2006.173.04:42:14.61#ibcon#*before write, iclass 40, count 2 2006.173.04:42:14.61#ibcon#enter sib2, iclass 40, count 2 2006.173.04:42:14.61#ibcon#flushed, iclass 40, count 2 2006.173.04:42:14.61#ibcon#about to write, iclass 40, count 2 2006.173.04:42:14.61#ibcon#wrote, iclass 40, count 2 2006.173.04:42:14.61#ibcon#about to read 3, iclass 40, count 2 2006.173.04:42:14.64#ibcon#read 3, iclass 40, count 2 2006.173.04:42:14.64#ibcon#about to read 4, iclass 40, count 2 2006.173.04:42:14.64#ibcon#read 4, iclass 40, count 2 2006.173.04:42:14.64#ibcon#about to read 5, iclass 40, count 2 2006.173.04:42:14.64#ibcon#read 5, iclass 40, count 2 2006.173.04:42:14.64#ibcon#about to read 6, iclass 40, count 2 2006.173.04:42:14.64#ibcon#read 6, iclass 40, count 2 2006.173.04:42:14.64#ibcon#end of sib2, iclass 40, count 2 2006.173.04:42:14.64#ibcon#*after write, iclass 40, count 2 2006.173.04:42:14.64#ibcon#*before return 0, iclass 40, count 2 2006.173.04:42:14.64#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.04:42:14.64#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.04:42:14.64#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.04:42:14.64#ibcon#ireg 7 cls_cnt 0 2006.173.04:42:14.64#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.04:42:14.76#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.04:42:14.76#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.04:42:14.76#ibcon#enter wrdev, iclass 40, count 0 2006.173.04:42:14.76#ibcon#first serial, iclass 40, count 0 2006.173.04:42:14.76#ibcon#enter sib2, iclass 40, count 0 2006.173.04:42:14.76#ibcon#flushed, iclass 40, count 0 2006.173.04:42:14.76#ibcon#about to write, iclass 40, count 0 2006.173.04:42:14.76#ibcon#wrote, iclass 40, count 0 2006.173.04:42:14.76#ibcon#about to read 3, iclass 40, count 0 2006.173.04:42:14.78#ibcon#read 3, iclass 40, count 0 2006.173.04:42:14.78#ibcon#about to read 4, iclass 40, count 0 2006.173.04:42:14.78#ibcon#read 4, iclass 40, count 0 2006.173.04:42:14.78#ibcon#about to read 5, iclass 40, count 0 2006.173.04:42:14.78#ibcon#read 5, iclass 40, count 0 2006.173.04:42:14.78#ibcon#about to read 6, iclass 40, count 0 2006.173.04:42:14.78#ibcon#read 6, iclass 40, count 0 2006.173.04:42:14.78#ibcon#end of sib2, iclass 40, count 0 2006.173.04:42:14.78#ibcon#*mode == 0, iclass 40, count 0 2006.173.04:42:14.78#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.04:42:14.78#ibcon#[25=USB\r\n] 2006.173.04:42:14.78#ibcon#*before write, iclass 40, count 0 2006.173.04:42:14.78#ibcon#enter sib2, iclass 40, count 0 2006.173.04:42:14.78#ibcon#flushed, iclass 40, count 0 2006.173.04:42:14.78#ibcon#about to write, iclass 40, count 0 2006.173.04:42:14.78#ibcon#wrote, iclass 40, count 0 2006.173.04:42:14.78#ibcon#about to read 3, iclass 40, count 0 2006.173.04:42:14.81#ibcon#read 3, iclass 40, count 0 2006.173.04:42:14.81#ibcon#about to read 4, iclass 40, count 0 2006.173.04:42:14.81#ibcon#read 4, iclass 40, count 0 2006.173.04:42:14.81#ibcon#about to read 5, iclass 40, count 0 2006.173.04:42:14.81#ibcon#read 5, iclass 40, count 0 2006.173.04:42:14.81#ibcon#about to read 6, iclass 40, count 0 2006.173.04:42:14.81#ibcon#read 6, iclass 40, count 0 2006.173.04:42:14.81#ibcon#end of sib2, iclass 40, count 0 2006.173.04:42:14.81#ibcon#*after write, iclass 40, count 0 2006.173.04:42:14.81#ibcon#*before return 0, iclass 40, count 0 2006.173.04:42:14.81#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.04:42:14.81#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.04:42:14.81#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.04:42:14.81#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.04:42:14.81$vck44/valo=3,564.99 2006.173.04:42:14.81#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.04:42:14.81#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.04:42:14.81#ibcon#ireg 17 cls_cnt 0 2006.173.04:42:14.81#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.04:42:14.81#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.04:42:14.81#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.04:42:14.81#ibcon#enter wrdev, iclass 4, count 0 2006.173.04:42:14.81#ibcon#first serial, iclass 4, count 0 2006.173.04:42:14.81#ibcon#enter sib2, iclass 4, count 0 2006.173.04:42:14.81#ibcon#flushed, iclass 4, count 0 2006.173.04:42:14.81#ibcon#about to write, iclass 4, count 0 2006.173.04:42:14.81#ibcon#wrote, iclass 4, count 0 2006.173.04:42:14.81#ibcon#about to read 3, iclass 4, count 0 2006.173.04:42:14.83#ibcon#read 3, iclass 4, count 0 2006.173.04:42:14.83#ibcon#about to read 4, iclass 4, count 0 2006.173.04:42:14.83#ibcon#read 4, iclass 4, count 0 2006.173.04:42:14.83#ibcon#about to read 5, iclass 4, count 0 2006.173.04:42:14.83#ibcon#read 5, iclass 4, count 0 2006.173.04:42:14.83#ibcon#about to read 6, iclass 4, count 0 2006.173.04:42:14.83#ibcon#read 6, iclass 4, count 0 2006.173.04:42:14.83#ibcon#end of sib2, iclass 4, count 0 2006.173.04:42:14.83#ibcon#*mode == 0, iclass 4, count 0 2006.173.04:42:14.83#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.04:42:14.83#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.04:42:14.83#ibcon#*before write, iclass 4, count 0 2006.173.04:42:14.83#ibcon#enter sib2, iclass 4, count 0 2006.173.04:42:14.83#ibcon#flushed, iclass 4, count 0 2006.173.04:42:14.83#ibcon#about to write, iclass 4, count 0 2006.173.04:42:14.83#ibcon#wrote, iclass 4, count 0 2006.173.04:42:14.83#ibcon#about to read 3, iclass 4, count 0 2006.173.04:42:14.87#ibcon#read 3, iclass 4, count 0 2006.173.04:42:14.87#ibcon#about to read 4, iclass 4, count 0 2006.173.04:42:14.87#ibcon#read 4, iclass 4, count 0 2006.173.04:42:14.87#ibcon#about to read 5, iclass 4, count 0 2006.173.04:42:14.87#ibcon#read 5, iclass 4, count 0 2006.173.04:42:14.87#ibcon#about to read 6, iclass 4, count 0 2006.173.04:42:14.87#ibcon#read 6, iclass 4, count 0 2006.173.04:42:14.87#ibcon#end of sib2, iclass 4, count 0 2006.173.04:42:14.87#ibcon#*after write, iclass 4, count 0 2006.173.04:42:14.87#ibcon#*before return 0, iclass 4, count 0 2006.173.04:42:14.87#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.04:42:14.87#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.04:42:14.87#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.04:42:14.87#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.04:42:14.87$vck44/va=3,5 2006.173.04:42:14.87#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.04:42:14.87#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.04:42:14.87#ibcon#ireg 11 cls_cnt 2 2006.173.04:42:14.87#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.04:42:14.93#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.04:42:14.93#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.04:42:14.93#ibcon#enter wrdev, iclass 6, count 2 2006.173.04:42:14.93#ibcon#first serial, iclass 6, count 2 2006.173.04:42:14.93#ibcon#enter sib2, iclass 6, count 2 2006.173.04:42:14.93#ibcon#flushed, iclass 6, count 2 2006.173.04:42:14.93#ibcon#about to write, iclass 6, count 2 2006.173.04:42:14.93#ibcon#wrote, iclass 6, count 2 2006.173.04:42:14.93#ibcon#about to read 3, iclass 6, count 2 2006.173.04:42:14.95#ibcon#read 3, iclass 6, count 2 2006.173.04:42:14.95#ibcon#about to read 4, iclass 6, count 2 2006.173.04:42:14.95#ibcon#read 4, iclass 6, count 2 2006.173.04:42:14.95#ibcon#about to read 5, iclass 6, count 2 2006.173.04:42:14.95#ibcon#read 5, iclass 6, count 2 2006.173.04:42:14.95#ibcon#about to read 6, iclass 6, count 2 2006.173.04:42:14.95#ibcon#read 6, iclass 6, count 2 2006.173.04:42:14.95#ibcon#end of sib2, iclass 6, count 2 2006.173.04:42:14.95#ibcon#*mode == 0, iclass 6, count 2 2006.173.04:42:14.95#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.04:42:14.95#ibcon#[25=AT03-05\r\n] 2006.173.04:42:14.95#ibcon#*before write, iclass 6, count 2 2006.173.04:42:14.95#ibcon#enter sib2, iclass 6, count 2 2006.173.04:42:14.95#ibcon#flushed, iclass 6, count 2 2006.173.04:42:14.95#ibcon#about to write, iclass 6, count 2 2006.173.04:42:14.95#ibcon#wrote, iclass 6, count 2 2006.173.04:42:14.95#ibcon#about to read 3, iclass 6, count 2 2006.173.04:42:14.98#ibcon#read 3, iclass 6, count 2 2006.173.04:42:14.98#ibcon#about to read 4, iclass 6, count 2 2006.173.04:42:14.98#ibcon#read 4, iclass 6, count 2 2006.173.04:42:14.98#ibcon#about to read 5, iclass 6, count 2 2006.173.04:42:14.98#ibcon#read 5, iclass 6, count 2 2006.173.04:42:14.98#ibcon#about to read 6, iclass 6, count 2 2006.173.04:42:14.98#ibcon#read 6, iclass 6, count 2 2006.173.04:42:14.98#ibcon#end of sib2, iclass 6, count 2 2006.173.04:42:14.98#ibcon#*after write, iclass 6, count 2 2006.173.04:42:14.98#ibcon#*before return 0, iclass 6, count 2 2006.173.04:42:14.98#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.04:42:14.98#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.04:42:14.98#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.04:42:14.98#ibcon#ireg 7 cls_cnt 0 2006.173.04:42:14.98#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.04:42:15.10#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.04:42:15.10#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.04:42:15.10#ibcon#enter wrdev, iclass 6, count 0 2006.173.04:42:15.10#ibcon#first serial, iclass 6, count 0 2006.173.04:42:15.10#ibcon#enter sib2, iclass 6, count 0 2006.173.04:42:15.10#ibcon#flushed, iclass 6, count 0 2006.173.04:42:15.10#ibcon#about to write, iclass 6, count 0 2006.173.04:42:15.10#ibcon#wrote, iclass 6, count 0 2006.173.04:42:15.10#ibcon#about to read 3, iclass 6, count 0 2006.173.04:42:15.12#ibcon#read 3, iclass 6, count 0 2006.173.04:42:15.12#ibcon#about to read 4, iclass 6, count 0 2006.173.04:42:15.12#ibcon#read 4, iclass 6, count 0 2006.173.04:42:15.12#ibcon#about to read 5, iclass 6, count 0 2006.173.04:42:15.12#ibcon#read 5, iclass 6, count 0 2006.173.04:42:15.12#ibcon#about to read 6, iclass 6, count 0 2006.173.04:42:15.12#ibcon#read 6, iclass 6, count 0 2006.173.04:42:15.12#ibcon#end of sib2, iclass 6, count 0 2006.173.04:42:15.12#ibcon#*mode == 0, iclass 6, count 0 2006.173.04:42:15.12#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.04:42:15.12#ibcon#[25=USB\r\n] 2006.173.04:42:15.12#ibcon#*before write, iclass 6, count 0 2006.173.04:42:15.12#ibcon#enter sib2, iclass 6, count 0 2006.173.04:42:15.12#ibcon#flushed, iclass 6, count 0 2006.173.04:42:15.12#ibcon#about to write, iclass 6, count 0 2006.173.04:42:15.12#ibcon#wrote, iclass 6, count 0 2006.173.04:42:15.12#ibcon#about to read 3, iclass 6, count 0 2006.173.04:42:15.15#ibcon#read 3, iclass 6, count 0 2006.173.04:42:15.15#ibcon#about to read 4, iclass 6, count 0 2006.173.04:42:15.15#ibcon#read 4, iclass 6, count 0 2006.173.04:42:15.15#ibcon#about to read 5, iclass 6, count 0 2006.173.04:42:15.15#ibcon#read 5, iclass 6, count 0 2006.173.04:42:15.15#ibcon#about to read 6, iclass 6, count 0 2006.173.04:42:15.15#ibcon#read 6, iclass 6, count 0 2006.173.04:42:15.15#ibcon#end of sib2, iclass 6, count 0 2006.173.04:42:15.15#ibcon#*after write, iclass 6, count 0 2006.173.04:42:15.15#ibcon#*before return 0, iclass 6, count 0 2006.173.04:42:15.15#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.04:42:15.15#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.04:42:15.15#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.04:42:15.15#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.04:42:15.15$vck44/valo=4,624.99 2006.173.04:42:15.15#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.04:42:15.15#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.04:42:15.15#ibcon#ireg 17 cls_cnt 0 2006.173.04:42:15.15#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.04:42:15.15#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.04:42:15.15#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.04:42:15.15#ibcon#enter wrdev, iclass 10, count 0 2006.173.04:42:15.15#ibcon#first serial, iclass 10, count 0 2006.173.04:42:15.15#ibcon#enter sib2, iclass 10, count 0 2006.173.04:42:15.15#ibcon#flushed, iclass 10, count 0 2006.173.04:42:15.15#ibcon#about to write, iclass 10, count 0 2006.173.04:42:15.15#ibcon#wrote, iclass 10, count 0 2006.173.04:42:15.15#ibcon#about to read 3, iclass 10, count 0 2006.173.04:42:15.17#ibcon#read 3, iclass 10, count 0 2006.173.04:42:15.17#ibcon#about to read 4, iclass 10, count 0 2006.173.04:42:15.17#ibcon#read 4, iclass 10, count 0 2006.173.04:42:15.17#ibcon#about to read 5, iclass 10, count 0 2006.173.04:42:15.17#ibcon#read 5, iclass 10, count 0 2006.173.04:42:15.17#ibcon#about to read 6, iclass 10, count 0 2006.173.04:42:15.17#ibcon#read 6, iclass 10, count 0 2006.173.04:42:15.17#ibcon#end of sib2, iclass 10, count 0 2006.173.04:42:15.17#ibcon#*mode == 0, iclass 10, count 0 2006.173.04:42:15.17#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.04:42:15.17#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.04:42:15.17#ibcon#*before write, iclass 10, count 0 2006.173.04:42:15.17#ibcon#enter sib2, iclass 10, count 0 2006.173.04:42:15.17#ibcon#flushed, iclass 10, count 0 2006.173.04:42:15.17#ibcon#about to write, iclass 10, count 0 2006.173.04:42:15.17#ibcon#wrote, iclass 10, count 0 2006.173.04:42:15.17#ibcon#about to read 3, iclass 10, count 0 2006.173.04:42:15.21#ibcon#read 3, iclass 10, count 0 2006.173.04:42:15.21#ibcon#about to read 4, iclass 10, count 0 2006.173.04:42:15.21#ibcon#read 4, iclass 10, count 0 2006.173.04:42:15.21#ibcon#about to read 5, iclass 10, count 0 2006.173.04:42:15.21#ibcon#read 5, iclass 10, count 0 2006.173.04:42:15.21#ibcon#about to read 6, iclass 10, count 0 2006.173.04:42:15.21#ibcon#read 6, iclass 10, count 0 2006.173.04:42:15.21#ibcon#end of sib2, iclass 10, count 0 2006.173.04:42:15.21#ibcon#*after write, iclass 10, count 0 2006.173.04:42:15.21#ibcon#*before return 0, iclass 10, count 0 2006.173.04:42:15.21#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.04:42:15.21#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.04:42:15.21#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.04:42:15.21#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.04:42:15.21$vck44/va=4,6 2006.173.04:42:15.21#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.04:42:15.21#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.04:42:15.21#ibcon#ireg 11 cls_cnt 2 2006.173.04:42:15.21#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.04:42:15.27#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.04:42:15.27#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.04:42:15.27#ibcon#enter wrdev, iclass 12, count 2 2006.173.04:42:15.27#ibcon#first serial, iclass 12, count 2 2006.173.04:42:15.27#ibcon#enter sib2, iclass 12, count 2 2006.173.04:42:15.27#ibcon#flushed, iclass 12, count 2 2006.173.04:42:15.27#ibcon#about to write, iclass 12, count 2 2006.173.04:42:15.27#ibcon#wrote, iclass 12, count 2 2006.173.04:42:15.27#ibcon#about to read 3, iclass 12, count 2 2006.173.04:42:15.29#ibcon#read 3, iclass 12, count 2 2006.173.04:42:15.29#ibcon#about to read 4, iclass 12, count 2 2006.173.04:42:15.29#ibcon#read 4, iclass 12, count 2 2006.173.04:42:15.29#ibcon#about to read 5, iclass 12, count 2 2006.173.04:42:15.29#ibcon#read 5, iclass 12, count 2 2006.173.04:42:15.29#ibcon#about to read 6, iclass 12, count 2 2006.173.04:42:15.29#ibcon#read 6, iclass 12, count 2 2006.173.04:42:15.29#ibcon#end of sib2, iclass 12, count 2 2006.173.04:42:15.29#ibcon#*mode == 0, iclass 12, count 2 2006.173.04:42:15.29#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.04:42:15.29#ibcon#[25=AT04-06\r\n] 2006.173.04:42:15.29#ibcon#*before write, iclass 12, count 2 2006.173.04:42:15.29#ibcon#enter sib2, iclass 12, count 2 2006.173.04:42:15.29#ibcon#flushed, iclass 12, count 2 2006.173.04:42:15.29#ibcon#about to write, iclass 12, count 2 2006.173.04:42:15.29#ibcon#wrote, iclass 12, count 2 2006.173.04:42:15.29#ibcon#about to read 3, iclass 12, count 2 2006.173.04:42:15.30#abcon#<5=/16 1.0 2.4 23.43 761005.8\r\n> 2006.173.04:42:15.32#abcon#{5=INTERFACE CLEAR} 2006.173.04:42:15.32#ibcon#read 3, iclass 12, count 2 2006.173.04:42:15.32#ibcon#about to read 4, iclass 12, count 2 2006.173.04:42:15.32#ibcon#read 4, iclass 12, count 2 2006.173.04:42:15.32#ibcon#about to read 5, iclass 12, count 2 2006.173.04:42:15.32#ibcon#read 5, iclass 12, count 2 2006.173.04:42:15.32#ibcon#about to read 6, iclass 12, count 2 2006.173.04:42:15.32#ibcon#read 6, iclass 12, count 2 2006.173.04:42:15.32#ibcon#end of sib2, iclass 12, count 2 2006.173.04:42:15.32#ibcon#*after write, iclass 12, count 2 2006.173.04:42:15.32#ibcon#*before return 0, iclass 12, count 2 2006.173.04:42:15.32#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.04:42:15.32#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.04:42:15.32#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.04:42:15.32#ibcon#ireg 7 cls_cnt 0 2006.173.04:42:15.32#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.04:42:15.38#abcon#[5=S1D000X0/0*\r\n] 2006.173.04:42:15.44#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.04:42:15.44#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.04:42:15.44#ibcon#enter wrdev, iclass 12, count 0 2006.173.04:42:15.44#ibcon#first serial, iclass 12, count 0 2006.173.04:42:15.44#ibcon#enter sib2, iclass 12, count 0 2006.173.04:42:15.44#ibcon#flushed, iclass 12, count 0 2006.173.04:42:15.44#ibcon#about to write, iclass 12, count 0 2006.173.04:42:15.44#ibcon#wrote, iclass 12, count 0 2006.173.04:42:15.44#ibcon#about to read 3, iclass 12, count 0 2006.173.04:42:15.46#ibcon#read 3, iclass 12, count 0 2006.173.04:42:15.46#ibcon#about to read 4, iclass 12, count 0 2006.173.04:42:15.46#ibcon#read 4, iclass 12, count 0 2006.173.04:42:15.46#ibcon#about to read 5, iclass 12, count 0 2006.173.04:42:15.46#ibcon#read 5, iclass 12, count 0 2006.173.04:42:15.46#ibcon#about to read 6, iclass 12, count 0 2006.173.04:42:15.46#ibcon#read 6, iclass 12, count 0 2006.173.04:42:15.46#ibcon#end of sib2, iclass 12, count 0 2006.173.04:42:15.46#ibcon#*mode == 0, iclass 12, count 0 2006.173.04:42:15.46#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.04:42:15.46#ibcon#[25=USB\r\n] 2006.173.04:42:15.46#ibcon#*before write, iclass 12, count 0 2006.173.04:42:15.46#ibcon#enter sib2, iclass 12, count 0 2006.173.04:42:15.46#ibcon#flushed, iclass 12, count 0 2006.173.04:42:15.46#ibcon#about to write, iclass 12, count 0 2006.173.04:42:15.46#ibcon#wrote, iclass 12, count 0 2006.173.04:42:15.46#ibcon#about to read 3, iclass 12, count 0 2006.173.04:42:15.49#ibcon#read 3, iclass 12, count 0 2006.173.04:42:15.49#ibcon#about to read 4, iclass 12, count 0 2006.173.04:42:15.49#ibcon#read 4, iclass 12, count 0 2006.173.04:42:15.49#ibcon#about to read 5, iclass 12, count 0 2006.173.04:42:15.49#ibcon#read 5, iclass 12, count 0 2006.173.04:42:15.49#ibcon#about to read 6, iclass 12, count 0 2006.173.04:42:15.49#ibcon#read 6, iclass 12, count 0 2006.173.04:42:15.49#ibcon#end of sib2, iclass 12, count 0 2006.173.04:42:15.49#ibcon#*after write, iclass 12, count 0 2006.173.04:42:15.49#ibcon#*before return 0, iclass 12, count 0 2006.173.04:42:15.49#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.04:42:15.49#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.04:42:15.49#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.04:42:15.49#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.04:42:15.49$vck44/valo=5,734.99 2006.173.04:42:15.49#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.04:42:15.49#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.04:42:15.49#ibcon#ireg 17 cls_cnt 0 2006.173.04:42:15.49#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.04:42:15.49#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.04:42:15.49#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.04:42:15.49#ibcon#enter wrdev, iclass 18, count 0 2006.173.04:42:15.49#ibcon#first serial, iclass 18, count 0 2006.173.04:42:15.49#ibcon#enter sib2, iclass 18, count 0 2006.173.04:42:15.49#ibcon#flushed, iclass 18, count 0 2006.173.04:42:15.49#ibcon#about to write, iclass 18, count 0 2006.173.04:42:15.49#ibcon#wrote, iclass 18, count 0 2006.173.04:42:15.49#ibcon#about to read 3, iclass 18, count 0 2006.173.04:42:15.51#ibcon#read 3, iclass 18, count 0 2006.173.04:42:15.51#ibcon#about to read 4, iclass 18, count 0 2006.173.04:42:15.51#ibcon#read 4, iclass 18, count 0 2006.173.04:42:15.51#ibcon#about to read 5, iclass 18, count 0 2006.173.04:42:15.51#ibcon#read 5, iclass 18, count 0 2006.173.04:42:15.51#ibcon#about to read 6, iclass 18, count 0 2006.173.04:42:15.51#ibcon#read 6, iclass 18, count 0 2006.173.04:42:15.51#ibcon#end of sib2, iclass 18, count 0 2006.173.04:42:15.51#ibcon#*mode == 0, iclass 18, count 0 2006.173.04:42:15.51#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.04:42:15.51#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.04:42:15.51#ibcon#*before write, iclass 18, count 0 2006.173.04:42:15.51#ibcon#enter sib2, iclass 18, count 0 2006.173.04:42:15.51#ibcon#flushed, iclass 18, count 0 2006.173.04:42:15.51#ibcon#about to write, iclass 18, count 0 2006.173.04:42:15.51#ibcon#wrote, iclass 18, count 0 2006.173.04:42:15.51#ibcon#about to read 3, iclass 18, count 0 2006.173.04:42:15.55#ibcon#read 3, iclass 18, count 0 2006.173.04:42:15.55#ibcon#about to read 4, iclass 18, count 0 2006.173.04:42:15.55#ibcon#read 4, iclass 18, count 0 2006.173.04:42:15.55#ibcon#about to read 5, iclass 18, count 0 2006.173.04:42:15.55#ibcon#read 5, iclass 18, count 0 2006.173.04:42:15.55#ibcon#about to read 6, iclass 18, count 0 2006.173.04:42:15.55#ibcon#read 6, iclass 18, count 0 2006.173.04:42:15.55#ibcon#end of sib2, iclass 18, count 0 2006.173.04:42:15.55#ibcon#*after write, iclass 18, count 0 2006.173.04:42:15.55#ibcon#*before return 0, iclass 18, count 0 2006.173.04:42:15.55#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.04:42:15.55#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.04:42:15.55#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.04:42:15.55#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.04:42:15.55$vck44/va=5,4 2006.173.04:42:15.55#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.04:42:15.55#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.04:42:15.55#ibcon#ireg 11 cls_cnt 2 2006.173.04:42:15.55#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.04:42:15.61#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.04:42:15.61#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.04:42:15.61#ibcon#enter wrdev, iclass 20, count 2 2006.173.04:42:15.61#ibcon#first serial, iclass 20, count 2 2006.173.04:42:15.61#ibcon#enter sib2, iclass 20, count 2 2006.173.04:42:15.61#ibcon#flushed, iclass 20, count 2 2006.173.04:42:15.61#ibcon#about to write, iclass 20, count 2 2006.173.04:42:15.61#ibcon#wrote, iclass 20, count 2 2006.173.04:42:15.61#ibcon#about to read 3, iclass 20, count 2 2006.173.04:42:15.63#ibcon#read 3, iclass 20, count 2 2006.173.04:42:15.63#ibcon#about to read 4, iclass 20, count 2 2006.173.04:42:15.63#ibcon#read 4, iclass 20, count 2 2006.173.04:42:15.63#ibcon#about to read 5, iclass 20, count 2 2006.173.04:42:15.63#ibcon#read 5, iclass 20, count 2 2006.173.04:42:15.63#ibcon#about to read 6, iclass 20, count 2 2006.173.04:42:15.63#ibcon#read 6, iclass 20, count 2 2006.173.04:42:15.63#ibcon#end of sib2, iclass 20, count 2 2006.173.04:42:15.63#ibcon#*mode == 0, iclass 20, count 2 2006.173.04:42:15.63#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.04:42:15.63#ibcon#[25=AT05-04\r\n] 2006.173.04:42:15.63#ibcon#*before write, iclass 20, count 2 2006.173.04:42:15.63#ibcon#enter sib2, iclass 20, count 2 2006.173.04:42:15.63#ibcon#flushed, iclass 20, count 2 2006.173.04:42:15.63#ibcon#about to write, iclass 20, count 2 2006.173.04:42:15.63#ibcon#wrote, iclass 20, count 2 2006.173.04:42:15.63#ibcon#about to read 3, iclass 20, count 2 2006.173.04:42:15.66#ibcon#read 3, iclass 20, count 2 2006.173.04:42:15.66#ibcon#about to read 4, iclass 20, count 2 2006.173.04:42:15.66#ibcon#read 4, iclass 20, count 2 2006.173.04:42:15.66#ibcon#about to read 5, iclass 20, count 2 2006.173.04:42:15.66#ibcon#read 5, iclass 20, count 2 2006.173.04:42:15.66#ibcon#about to read 6, iclass 20, count 2 2006.173.04:42:15.66#ibcon#read 6, iclass 20, count 2 2006.173.04:42:15.66#ibcon#end of sib2, iclass 20, count 2 2006.173.04:42:15.66#ibcon#*after write, iclass 20, count 2 2006.173.04:42:15.66#ibcon#*before return 0, iclass 20, count 2 2006.173.04:42:15.66#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.04:42:15.66#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.04:42:15.66#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.04:42:15.66#ibcon#ireg 7 cls_cnt 0 2006.173.04:42:15.66#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.04:42:15.78#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.04:42:15.78#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.04:42:15.78#ibcon#enter wrdev, iclass 20, count 0 2006.173.04:42:15.78#ibcon#first serial, iclass 20, count 0 2006.173.04:42:15.78#ibcon#enter sib2, iclass 20, count 0 2006.173.04:42:15.78#ibcon#flushed, iclass 20, count 0 2006.173.04:42:15.78#ibcon#about to write, iclass 20, count 0 2006.173.04:42:15.78#ibcon#wrote, iclass 20, count 0 2006.173.04:42:15.78#ibcon#about to read 3, iclass 20, count 0 2006.173.04:42:15.80#ibcon#read 3, iclass 20, count 0 2006.173.04:42:15.80#ibcon#about to read 4, iclass 20, count 0 2006.173.04:42:15.80#ibcon#read 4, iclass 20, count 0 2006.173.04:42:15.80#ibcon#about to read 5, iclass 20, count 0 2006.173.04:42:15.80#ibcon#read 5, iclass 20, count 0 2006.173.04:42:15.80#ibcon#about to read 6, iclass 20, count 0 2006.173.04:42:15.80#ibcon#read 6, iclass 20, count 0 2006.173.04:42:15.80#ibcon#end of sib2, iclass 20, count 0 2006.173.04:42:15.80#ibcon#*mode == 0, iclass 20, count 0 2006.173.04:42:15.80#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.04:42:15.80#ibcon#[25=USB\r\n] 2006.173.04:42:15.80#ibcon#*before write, iclass 20, count 0 2006.173.04:42:15.80#ibcon#enter sib2, iclass 20, count 0 2006.173.04:42:15.80#ibcon#flushed, iclass 20, count 0 2006.173.04:42:15.80#ibcon#about to write, iclass 20, count 0 2006.173.04:42:15.80#ibcon#wrote, iclass 20, count 0 2006.173.04:42:15.80#ibcon#about to read 3, iclass 20, count 0 2006.173.04:42:15.83#ibcon#read 3, iclass 20, count 0 2006.173.04:42:15.83#ibcon#about to read 4, iclass 20, count 0 2006.173.04:42:15.83#ibcon#read 4, iclass 20, count 0 2006.173.04:42:15.83#ibcon#about to read 5, iclass 20, count 0 2006.173.04:42:15.83#ibcon#read 5, iclass 20, count 0 2006.173.04:42:15.83#ibcon#about to read 6, iclass 20, count 0 2006.173.04:42:15.83#ibcon#read 6, iclass 20, count 0 2006.173.04:42:15.83#ibcon#end of sib2, iclass 20, count 0 2006.173.04:42:15.83#ibcon#*after write, iclass 20, count 0 2006.173.04:42:15.83#ibcon#*before return 0, iclass 20, count 0 2006.173.04:42:15.83#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.04:42:15.83#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.04:42:15.83#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.04:42:15.83#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.04:42:15.83$vck44/valo=6,814.99 2006.173.04:42:15.83#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.04:42:15.83#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.04:42:15.83#ibcon#ireg 17 cls_cnt 0 2006.173.04:42:15.83#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.04:42:15.83#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.04:42:15.83#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.04:42:15.83#ibcon#enter wrdev, iclass 22, count 0 2006.173.04:42:15.83#ibcon#first serial, iclass 22, count 0 2006.173.04:42:15.83#ibcon#enter sib2, iclass 22, count 0 2006.173.04:42:15.83#ibcon#flushed, iclass 22, count 0 2006.173.04:42:15.83#ibcon#about to write, iclass 22, count 0 2006.173.04:42:15.83#ibcon#wrote, iclass 22, count 0 2006.173.04:42:15.83#ibcon#about to read 3, iclass 22, count 0 2006.173.04:42:15.85#ibcon#read 3, iclass 22, count 0 2006.173.04:42:15.85#ibcon#about to read 4, iclass 22, count 0 2006.173.04:42:15.85#ibcon#read 4, iclass 22, count 0 2006.173.04:42:15.85#ibcon#about to read 5, iclass 22, count 0 2006.173.04:42:15.85#ibcon#read 5, iclass 22, count 0 2006.173.04:42:15.85#ibcon#about to read 6, iclass 22, count 0 2006.173.04:42:15.85#ibcon#read 6, iclass 22, count 0 2006.173.04:42:15.85#ibcon#end of sib2, iclass 22, count 0 2006.173.04:42:15.85#ibcon#*mode == 0, iclass 22, count 0 2006.173.04:42:15.85#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.04:42:15.85#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.04:42:15.85#ibcon#*before write, iclass 22, count 0 2006.173.04:42:15.85#ibcon#enter sib2, iclass 22, count 0 2006.173.04:42:15.85#ibcon#flushed, iclass 22, count 0 2006.173.04:42:15.85#ibcon#about to write, iclass 22, count 0 2006.173.04:42:15.85#ibcon#wrote, iclass 22, count 0 2006.173.04:42:15.85#ibcon#about to read 3, iclass 22, count 0 2006.173.04:42:15.89#ibcon#read 3, iclass 22, count 0 2006.173.04:42:15.89#ibcon#about to read 4, iclass 22, count 0 2006.173.04:42:15.89#ibcon#read 4, iclass 22, count 0 2006.173.04:42:15.89#ibcon#about to read 5, iclass 22, count 0 2006.173.04:42:15.89#ibcon#read 5, iclass 22, count 0 2006.173.04:42:15.89#ibcon#about to read 6, iclass 22, count 0 2006.173.04:42:15.89#ibcon#read 6, iclass 22, count 0 2006.173.04:42:15.89#ibcon#end of sib2, iclass 22, count 0 2006.173.04:42:15.89#ibcon#*after write, iclass 22, count 0 2006.173.04:42:15.89#ibcon#*before return 0, iclass 22, count 0 2006.173.04:42:15.89#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.04:42:15.89#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.04:42:15.89#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.04:42:15.89#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.04:42:15.89$vck44/va=6,3 2006.173.04:42:15.89#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.04:42:15.89#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.04:42:15.89#ibcon#ireg 11 cls_cnt 2 2006.173.04:42:15.89#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.04:42:15.95#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.04:42:15.95#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.04:42:15.95#ibcon#enter wrdev, iclass 24, count 2 2006.173.04:42:15.95#ibcon#first serial, iclass 24, count 2 2006.173.04:42:15.95#ibcon#enter sib2, iclass 24, count 2 2006.173.04:42:15.95#ibcon#flushed, iclass 24, count 2 2006.173.04:42:15.95#ibcon#about to write, iclass 24, count 2 2006.173.04:42:15.95#ibcon#wrote, iclass 24, count 2 2006.173.04:42:15.95#ibcon#about to read 3, iclass 24, count 2 2006.173.04:42:15.97#ibcon#read 3, iclass 24, count 2 2006.173.04:42:15.97#ibcon#about to read 4, iclass 24, count 2 2006.173.04:42:15.97#ibcon#read 4, iclass 24, count 2 2006.173.04:42:15.97#ibcon#about to read 5, iclass 24, count 2 2006.173.04:42:15.97#ibcon#read 5, iclass 24, count 2 2006.173.04:42:15.97#ibcon#about to read 6, iclass 24, count 2 2006.173.04:42:15.97#ibcon#read 6, iclass 24, count 2 2006.173.04:42:15.97#ibcon#end of sib2, iclass 24, count 2 2006.173.04:42:15.97#ibcon#*mode == 0, iclass 24, count 2 2006.173.04:42:15.97#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.04:42:15.97#ibcon#[25=AT06-03\r\n] 2006.173.04:42:15.97#ibcon#*before write, iclass 24, count 2 2006.173.04:42:15.97#ibcon#enter sib2, iclass 24, count 2 2006.173.04:42:15.97#ibcon#flushed, iclass 24, count 2 2006.173.04:42:15.97#ibcon#about to write, iclass 24, count 2 2006.173.04:42:15.97#ibcon#wrote, iclass 24, count 2 2006.173.04:42:15.97#ibcon#about to read 3, iclass 24, count 2 2006.173.04:42:16.00#ibcon#read 3, iclass 24, count 2 2006.173.04:42:16.00#ibcon#about to read 4, iclass 24, count 2 2006.173.04:42:16.00#ibcon#read 4, iclass 24, count 2 2006.173.04:42:16.00#ibcon#about to read 5, iclass 24, count 2 2006.173.04:42:16.00#ibcon#read 5, iclass 24, count 2 2006.173.04:42:16.00#ibcon#about to read 6, iclass 24, count 2 2006.173.04:42:16.00#ibcon#read 6, iclass 24, count 2 2006.173.04:42:16.00#ibcon#end of sib2, iclass 24, count 2 2006.173.04:42:16.00#ibcon#*after write, iclass 24, count 2 2006.173.04:42:16.00#ibcon#*before return 0, iclass 24, count 2 2006.173.04:42:16.00#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.04:42:16.00#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.04:42:16.00#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.04:42:16.00#ibcon#ireg 7 cls_cnt 0 2006.173.04:42:16.00#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.04:42:16.12#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.04:42:16.12#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.04:42:16.12#ibcon#enter wrdev, iclass 24, count 0 2006.173.04:42:16.12#ibcon#first serial, iclass 24, count 0 2006.173.04:42:16.12#ibcon#enter sib2, iclass 24, count 0 2006.173.04:42:16.12#ibcon#flushed, iclass 24, count 0 2006.173.04:42:16.12#ibcon#about to write, iclass 24, count 0 2006.173.04:42:16.12#ibcon#wrote, iclass 24, count 0 2006.173.04:42:16.12#ibcon#about to read 3, iclass 24, count 0 2006.173.04:42:16.14#ibcon#read 3, iclass 24, count 0 2006.173.04:42:16.14#ibcon#about to read 4, iclass 24, count 0 2006.173.04:42:16.14#ibcon#read 4, iclass 24, count 0 2006.173.04:42:16.14#ibcon#about to read 5, iclass 24, count 0 2006.173.04:42:16.14#ibcon#read 5, iclass 24, count 0 2006.173.04:42:16.14#ibcon#about to read 6, iclass 24, count 0 2006.173.04:42:16.14#ibcon#read 6, iclass 24, count 0 2006.173.04:42:16.14#ibcon#end of sib2, iclass 24, count 0 2006.173.04:42:16.14#ibcon#*mode == 0, iclass 24, count 0 2006.173.04:42:16.14#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.04:42:16.14#ibcon#[25=USB\r\n] 2006.173.04:42:16.14#ibcon#*before write, iclass 24, count 0 2006.173.04:42:16.14#ibcon#enter sib2, iclass 24, count 0 2006.173.04:42:16.14#ibcon#flushed, iclass 24, count 0 2006.173.04:42:16.14#ibcon#about to write, iclass 24, count 0 2006.173.04:42:16.14#ibcon#wrote, iclass 24, count 0 2006.173.04:42:16.14#ibcon#about to read 3, iclass 24, count 0 2006.173.04:42:16.17#ibcon#read 3, iclass 24, count 0 2006.173.04:42:16.17#ibcon#about to read 4, iclass 24, count 0 2006.173.04:42:16.17#ibcon#read 4, iclass 24, count 0 2006.173.04:42:16.17#ibcon#about to read 5, iclass 24, count 0 2006.173.04:42:16.17#ibcon#read 5, iclass 24, count 0 2006.173.04:42:16.17#ibcon#about to read 6, iclass 24, count 0 2006.173.04:42:16.17#ibcon#read 6, iclass 24, count 0 2006.173.04:42:16.17#ibcon#end of sib2, iclass 24, count 0 2006.173.04:42:16.17#ibcon#*after write, iclass 24, count 0 2006.173.04:42:16.17#ibcon#*before return 0, iclass 24, count 0 2006.173.04:42:16.17#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.04:42:16.17#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.04:42:16.17#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.04:42:16.17#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.04:42:16.17$vck44/valo=7,864.99 2006.173.04:42:16.17#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.04:42:16.17#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.04:42:16.17#ibcon#ireg 17 cls_cnt 0 2006.173.04:42:16.17#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.04:42:16.17#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.04:42:16.17#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.04:42:16.17#ibcon#enter wrdev, iclass 26, count 0 2006.173.04:42:16.17#ibcon#first serial, iclass 26, count 0 2006.173.04:42:16.17#ibcon#enter sib2, iclass 26, count 0 2006.173.04:42:16.17#ibcon#flushed, iclass 26, count 0 2006.173.04:42:16.17#ibcon#about to write, iclass 26, count 0 2006.173.04:42:16.18#ibcon#wrote, iclass 26, count 0 2006.173.04:42:16.18#ibcon#about to read 3, iclass 26, count 0 2006.173.04:42:16.19#ibcon#read 3, iclass 26, count 0 2006.173.04:42:16.19#ibcon#about to read 4, iclass 26, count 0 2006.173.04:42:16.19#ibcon#read 4, iclass 26, count 0 2006.173.04:42:16.19#ibcon#about to read 5, iclass 26, count 0 2006.173.04:42:16.19#ibcon#read 5, iclass 26, count 0 2006.173.04:42:16.19#ibcon#about to read 6, iclass 26, count 0 2006.173.04:42:16.19#ibcon#read 6, iclass 26, count 0 2006.173.04:42:16.19#ibcon#end of sib2, iclass 26, count 0 2006.173.04:42:16.19#ibcon#*mode == 0, iclass 26, count 0 2006.173.04:42:16.19#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.04:42:16.19#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.04:42:16.19#ibcon#*before write, iclass 26, count 0 2006.173.04:42:16.19#ibcon#enter sib2, iclass 26, count 0 2006.173.04:42:16.19#ibcon#flushed, iclass 26, count 0 2006.173.04:42:16.19#ibcon#about to write, iclass 26, count 0 2006.173.04:42:16.19#ibcon#wrote, iclass 26, count 0 2006.173.04:42:16.19#ibcon#about to read 3, iclass 26, count 0 2006.173.04:42:16.23#ibcon#read 3, iclass 26, count 0 2006.173.04:42:16.23#ibcon#about to read 4, iclass 26, count 0 2006.173.04:42:16.23#ibcon#read 4, iclass 26, count 0 2006.173.04:42:16.23#ibcon#about to read 5, iclass 26, count 0 2006.173.04:42:16.23#ibcon#read 5, iclass 26, count 0 2006.173.04:42:16.23#ibcon#about to read 6, iclass 26, count 0 2006.173.04:42:16.23#ibcon#read 6, iclass 26, count 0 2006.173.04:42:16.23#ibcon#end of sib2, iclass 26, count 0 2006.173.04:42:16.23#ibcon#*after write, iclass 26, count 0 2006.173.04:42:16.23#ibcon#*before return 0, iclass 26, count 0 2006.173.04:42:16.23#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.04:42:16.23#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.04:42:16.23#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.04:42:16.23#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.04:42:16.23$vck44/va=7,4 2006.173.04:42:16.23#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.04:42:16.23#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.04:42:16.23#ibcon#ireg 11 cls_cnt 2 2006.173.04:42:16.23#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.04:42:16.29#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.04:42:16.29#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.04:42:16.29#ibcon#enter wrdev, iclass 28, count 2 2006.173.04:42:16.29#ibcon#first serial, iclass 28, count 2 2006.173.04:42:16.29#ibcon#enter sib2, iclass 28, count 2 2006.173.04:42:16.29#ibcon#flushed, iclass 28, count 2 2006.173.04:42:16.29#ibcon#about to write, iclass 28, count 2 2006.173.04:42:16.29#ibcon#wrote, iclass 28, count 2 2006.173.04:42:16.29#ibcon#about to read 3, iclass 28, count 2 2006.173.04:42:16.31#ibcon#read 3, iclass 28, count 2 2006.173.04:42:16.31#ibcon#about to read 4, iclass 28, count 2 2006.173.04:42:16.31#ibcon#read 4, iclass 28, count 2 2006.173.04:42:16.31#ibcon#about to read 5, iclass 28, count 2 2006.173.04:42:16.31#ibcon#read 5, iclass 28, count 2 2006.173.04:42:16.31#ibcon#about to read 6, iclass 28, count 2 2006.173.04:42:16.31#ibcon#read 6, iclass 28, count 2 2006.173.04:42:16.31#ibcon#end of sib2, iclass 28, count 2 2006.173.04:42:16.31#ibcon#*mode == 0, iclass 28, count 2 2006.173.04:42:16.31#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.04:42:16.31#ibcon#[25=AT07-04\r\n] 2006.173.04:42:16.31#ibcon#*before write, iclass 28, count 2 2006.173.04:42:16.31#ibcon#enter sib2, iclass 28, count 2 2006.173.04:42:16.31#ibcon#flushed, iclass 28, count 2 2006.173.04:42:16.31#ibcon#about to write, iclass 28, count 2 2006.173.04:42:16.31#ibcon#wrote, iclass 28, count 2 2006.173.04:42:16.31#ibcon#about to read 3, iclass 28, count 2 2006.173.04:42:16.34#ibcon#read 3, iclass 28, count 2 2006.173.04:42:16.34#ibcon#about to read 4, iclass 28, count 2 2006.173.04:42:16.34#ibcon#read 4, iclass 28, count 2 2006.173.04:42:16.34#ibcon#about to read 5, iclass 28, count 2 2006.173.04:42:16.34#ibcon#read 5, iclass 28, count 2 2006.173.04:42:16.34#ibcon#about to read 6, iclass 28, count 2 2006.173.04:42:16.34#ibcon#read 6, iclass 28, count 2 2006.173.04:42:16.34#ibcon#end of sib2, iclass 28, count 2 2006.173.04:42:16.34#ibcon#*after write, iclass 28, count 2 2006.173.04:42:16.34#ibcon#*before return 0, iclass 28, count 2 2006.173.04:42:16.34#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.04:42:16.34#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.04:42:16.34#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.04:42:16.34#ibcon#ireg 7 cls_cnt 0 2006.173.04:42:16.34#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.04:42:16.46#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.04:42:16.46#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.04:42:16.46#ibcon#enter wrdev, iclass 28, count 0 2006.173.04:42:16.46#ibcon#first serial, iclass 28, count 0 2006.173.04:42:16.46#ibcon#enter sib2, iclass 28, count 0 2006.173.04:42:16.46#ibcon#flushed, iclass 28, count 0 2006.173.04:42:16.46#ibcon#about to write, iclass 28, count 0 2006.173.04:42:16.46#ibcon#wrote, iclass 28, count 0 2006.173.04:42:16.46#ibcon#about to read 3, iclass 28, count 0 2006.173.04:42:16.48#ibcon#read 3, iclass 28, count 0 2006.173.04:42:16.48#ibcon#about to read 4, iclass 28, count 0 2006.173.04:42:16.48#ibcon#read 4, iclass 28, count 0 2006.173.04:42:16.48#ibcon#about to read 5, iclass 28, count 0 2006.173.04:42:16.48#ibcon#read 5, iclass 28, count 0 2006.173.04:42:16.48#ibcon#about to read 6, iclass 28, count 0 2006.173.04:42:16.48#ibcon#read 6, iclass 28, count 0 2006.173.04:42:16.48#ibcon#end of sib2, iclass 28, count 0 2006.173.04:42:16.48#ibcon#*mode == 0, iclass 28, count 0 2006.173.04:42:16.48#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.04:42:16.48#ibcon#[25=USB\r\n] 2006.173.04:42:16.48#ibcon#*before write, iclass 28, count 0 2006.173.04:42:16.48#ibcon#enter sib2, iclass 28, count 0 2006.173.04:42:16.48#ibcon#flushed, iclass 28, count 0 2006.173.04:42:16.48#ibcon#about to write, iclass 28, count 0 2006.173.04:42:16.48#ibcon#wrote, iclass 28, count 0 2006.173.04:42:16.48#ibcon#about to read 3, iclass 28, count 0 2006.173.04:42:16.51#ibcon#read 3, iclass 28, count 0 2006.173.04:42:16.51#ibcon#about to read 4, iclass 28, count 0 2006.173.04:42:16.51#ibcon#read 4, iclass 28, count 0 2006.173.04:42:16.51#ibcon#about to read 5, iclass 28, count 0 2006.173.04:42:16.51#ibcon#read 5, iclass 28, count 0 2006.173.04:42:16.51#ibcon#about to read 6, iclass 28, count 0 2006.173.04:42:16.51#ibcon#read 6, iclass 28, count 0 2006.173.04:42:16.51#ibcon#end of sib2, iclass 28, count 0 2006.173.04:42:16.51#ibcon#*after write, iclass 28, count 0 2006.173.04:42:16.51#ibcon#*before return 0, iclass 28, count 0 2006.173.04:42:16.51#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.04:42:16.51#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.04:42:16.51#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.04:42:16.51#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.04:42:16.51$vck44/valo=8,884.99 2006.173.04:42:16.51#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.04:42:16.51#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.04:42:16.51#ibcon#ireg 17 cls_cnt 0 2006.173.04:42:16.51#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.04:42:16.51#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.04:42:16.51#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.04:42:16.51#ibcon#enter wrdev, iclass 30, count 0 2006.173.04:42:16.51#ibcon#first serial, iclass 30, count 0 2006.173.04:42:16.51#ibcon#enter sib2, iclass 30, count 0 2006.173.04:42:16.51#ibcon#flushed, iclass 30, count 0 2006.173.04:42:16.51#ibcon#about to write, iclass 30, count 0 2006.173.04:42:16.51#ibcon#wrote, iclass 30, count 0 2006.173.04:42:16.51#ibcon#about to read 3, iclass 30, count 0 2006.173.04:42:16.53#ibcon#read 3, iclass 30, count 0 2006.173.04:42:16.53#ibcon#about to read 4, iclass 30, count 0 2006.173.04:42:16.53#ibcon#read 4, iclass 30, count 0 2006.173.04:42:16.53#ibcon#about to read 5, iclass 30, count 0 2006.173.04:42:16.53#ibcon#read 5, iclass 30, count 0 2006.173.04:42:16.53#ibcon#about to read 6, iclass 30, count 0 2006.173.04:42:16.53#ibcon#read 6, iclass 30, count 0 2006.173.04:42:16.53#ibcon#end of sib2, iclass 30, count 0 2006.173.04:42:16.53#ibcon#*mode == 0, iclass 30, count 0 2006.173.04:42:16.53#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.04:42:16.53#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.04:42:16.53#ibcon#*before write, iclass 30, count 0 2006.173.04:42:16.53#ibcon#enter sib2, iclass 30, count 0 2006.173.04:42:16.53#ibcon#flushed, iclass 30, count 0 2006.173.04:42:16.53#ibcon#about to write, iclass 30, count 0 2006.173.04:42:16.53#ibcon#wrote, iclass 30, count 0 2006.173.04:42:16.53#ibcon#about to read 3, iclass 30, count 0 2006.173.04:42:16.57#ibcon#read 3, iclass 30, count 0 2006.173.04:42:16.57#ibcon#about to read 4, iclass 30, count 0 2006.173.04:42:16.57#ibcon#read 4, iclass 30, count 0 2006.173.04:42:16.57#ibcon#about to read 5, iclass 30, count 0 2006.173.04:42:16.57#ibcon#read 5, iclass 30, count 0 2006.173.04:42:16.57#ibcon#about to read 6, iclass 30, count 0 2006.173.04:42:16.57#ibcon#read 6, iclass 30, count 0 2006.173.04:42:16.57#ibcon#end of sib2, iclass 30, count 0 2006.173.04:42:16.57#ibcon#*after write, iclass 30, count 0 2006.173.04:42:16.57#ibcon#*before return 0, iclass 30, count 0 2006.173.04:42:16.57#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.04:42:16.57#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.04:42:16.57#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.04:42:16.57#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.04:42:16.57$vck44/va=8,4 2006.173.04:42:16.57#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.173.04:42:16.57#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.173.04:42:16.57#ibcon#ireg 11 cls_cnt 2 2006.173.04:42:16.57#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.04:42:16.63#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.04:42:16.63#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.04:42:16.63#ibcon#enter wrdev, iclass 32, count 2 2006.173.04:42:16.63#ibcon#first serial, iclass 32, count 2 2006.173.04:42:16.63#ibcon#enter sib2, iclass 32, count 2 2006.173.04:42:16.63#ibcon#flushed, iclass 32, count 2 2006.173.04:42:16.63#ibcon#about to write, iclass 32, count 2 2006.173.04:42:16.63#ibcon#wrote, iclass 32, count 2 2006.173.04:42:16.63#ibcon#about to read 3, iclass 32, count 2 2006.173.04:42:16.65#ibcon#read 3, iclass 32, count 2 2006.173.04:42:16.65#ibcon#about to read 4, iclass 32, count 2 2006.173.04:42:16.65#ibcon#read 4, iclass 32, count 2 2006.173.04:42:16.65#ibcon#about to read 5, iclass 32, count 2 2006.173.04:42:16.65#ibcon#read 5, iclass 32, count 2 2006.173.04:42:16.65#ibcon#about to read 6, iclass 32, count 2 2006.173.04:42:16.65#ibcon#read 6, iclass 32, count 2 2006.173.04:42:16.65#ibcon#end of sib2, iclass 32, count 2 2006.173.04:42:16.65#ibcon#*mode == 0, iclass 32, count 2 2006.173.04:42:16.65#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.173.04:42:16.65#ibcon#[25=AT08-04\r\n] 2006.173.04:42:16.65#ibcon#*before write, iclass 32, count 2 2006.173.04:42:16.65#ibcon#enter sib2, iclass 32, count 2 2006.173.04:42:16.65#ibcon#flushed, iclass 32, count 2 2006.173.04:42:16.65#ibcon#about to write, iclass 32, count 2 2006.173.04:42:16.65#ibcon#wrote, iclass 32, count 2 2006.173.04:42:16.65#ibcon#about to read 3, iclass 32, count 2 2006.173.04:42:16.68#ibcon#read 3, iclass 32, count 2 2006.173.04:42:16.68#ibcon#about to read 4, iclass 32, count 2 2006.173.04:42:16.68#ibcon#read 4, iclass 32, count 2 2006.173.04:42:16.68#ibcon#about to read 5, iclass 32, count 2 2006.173.04:42:16.68#ibcon#read 5, iclass 32, count 2 2006.173.04:42:16.68#ibcon#about to read 6, iclass 32, count 2 2006.173.04:42:16.68#ibcon#read 6, iclass 32, count 2 2006.173.04:42:16.68#ibcon#end of sib2, iclass 32, count 2 2006.173.04:42:16.68#ibcon#*after write, iclass 32, count 2 2006.173.04:42:16.68#ibcon#*before return 0, iclass 32, count 2 2006.173.04:42:16.68#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.04:42:16.68#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.173.04:42:16.68#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.173.04:42:16.68#ibcon#ireg 7 cls_cnt 0 2006.173.04:42:16.68#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.04:42:16.80#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.04:42:16.80#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.04:42:16.80#ibcon#enter wrdev, iclass 32, count 0 2006.173.04:42:16.80#ibcon#first serial, iclass 32, count 0 2006.173.04:42:16.80#ibcon#enter sib2, iclass 32, count 0 2006.173.04:42:16.80#ibcon#flushed, iclass 32, count 0 2006.173.04:42:16.80#ibcon#about to write, iclass 32, count 0 2006.173.04:42:16.80#ibcon#wrote, iclass 32, count 0 2006.173.04:42:16.80#ibcon#about to read 3, iclass 32, count 0 2006.173.04:42:16.82#ibcon#read 3, iclass 32, count 0 2006.173.04:42:16.82#ibcon#about to read 4, iclass 32, count 0 2006.173.04:42:16.82#ibcon#read 4, iclass 32, count 0 2006.173.04:42:16.82#ibcon#about to read 5, iclass 32, count 0 2006.173.04:42:16.82#ibcon#read 5, iclass 32, count 0 2006.173.04:42:16.82#ibcon#about to read 6, iclass 32, count 0 2006.173.04:42:16.82#ibcon#read 6, iclass 32, count 0 2006.173.04:42:16.82#ibcon#end of sib2, iclass 32, count 0 2006.173.04:42:16.82#ibcon#*mode == 0, iclass 32, count 0 2006.173.04:42:16.82#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.04:42:16.82#ibcon#[25=USB\r\n] 2006.173.04:42:16.82#ibcon#*before write, iclass 32, count 0 2006.173.04:42:16.82#ibcon#enter sib2, iclass 32, count 0 2006.173.04:42:16.82#ibcon#flushed, iclass 32, count 0 2006.173.04:42:16.82#ibcon#about to write, iclass 32, count 0 2006.173.04:42:16.82#ibcon#wrote, iclass 32, count 0 2006.173.04:42:16.82#ibcon#about to read 3, iclass 32, count 0 2006.173.04:42:16.85#ibcon#read 3, iclass 32, count 0 2006.173.04:42:16.85#ibcon#about to read 4, iclass 32, count 0 2006.173.04:42:16.85#ibcon#read 4, iclass 32, count 0 2006.173.04:42:16.85#ibcon#about to read 5, iclass 32, count 0 2006.173.04:42:16.85#ibcon#read 5, iclass 32, count 0 2006.173.04:42:16.85#ibcon#about to read 6, iclass 32, count 0 2006.173.04:42:16.85#ibcon#read 6, iclass 32, count 0 2006.173.04:42:16.85#ibcon#end of sib2, iclass 32, count 0 2006.173.04:42:16.85#ibcon#*after write, iclass 32, count 0 2006.173.04:42:16.85#ibcon#*before return 0, iclass 32, count 0 2006.173.04:42:16.85#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.04:42:16.85#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.173.04:42:16.85#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.04:42:16.85#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.04:42:16.85$vck44/vblo=1,629.99 2006.173.04:42:16.85#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.04:42:16.85#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.04:42:16.85#ibcon#ireg 17 cls_cnt 0 2006.173.04:42:16.85#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.04:42:16.85#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.04:42:16.85#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.04:42:16.85#ibcon#enter wrdev, iclass 34, count 0 2006.173.04:42:16.85#ibcon#first serial, iclass 34, count 0 2006.173.04:42:16.85#ibcon#enter sib2, iclass 34, count 0 2006.173.04:42:16.85#ibcon#flushed, iclass 34, count 0 2006.173.04:42:16.85#ibcon#about to write, iclass 34, count 0 2006.173.04:42:16.85#ibcon#wrote, iclass 34, count 0 2006.173.04:42:16.85#ibcon#about to read 3, iclass 34, count 0 2006.173.04:42:16.87#ibcon#read 3, iclass 34, count 0 2006.173.04:42:16.87#ibcon#about to read 4, iclass 34, count 0 2006.173.04:42:16.87#ibcon#read 4, iclass 34, count 0 2006.173.04:42:16.87#ibcon#about to read 5, iclass 34, count 0 2006.173.04:42:16.87#ibcon#read 5, iclass 34, count 0 2006.173.04:42:16.87#ibcon#about to read 6, iclass 34, count 0 2006.173.04:42:16.87#ibcon#read 6, iclass 34, count 0 2006.173.04:42:16.87#ibcon#end of sib2, iclass 34, count 0 2006.173.04:42:16.87#ibcon#*mode == 0, iclass 34, count 0 2006.173.04:42:16.87#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.04:42:16.87#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.04:42:16.87#ibcon#*before write, iclass 34, count 0 2006.173.04:42:16.87#ibcon#enter sib2, iclass 34, count 0 2006.173.04:42:16.87#ibcon#flushed, iclass 34, count 0 2006.173.04:42:16.87#ibcon#about to write, iclass 34, count 0 2006.173.04:42:16.87#ibcon#wrote, iclass 34, count 0 2006.173.04:42:16.87#ibcon#about to read 3, iclass 34, count 0 2006.173.04:42:16.91#ibcon#read 3, iclass 34, count 0 2006.173.04:42:16.91#ibcon#about to read 4, iclass 34, count 0 2006.173.04:42:16.91#ibcon#read 4, iclass 34, count 0 2006.173.04:42:16.91#ibcon#about to read 5, iclass 34, count 0 2006.173.04:42:16.91#ibcon#read 5, iclass 34, count 0 2006.173.04:42:16.91#ibcon#about to read 6, iclass 34, count 0 2006.173.04:42:16.91#ibcon#read 6, iclass 34, count 0 2006.173.04:42:16.91#ibcon#end of sib2, iclass 34, count 0 2006.173.04:42:16.91#ibcon#*after write, iclass 34, count 0 2006.173.04:42:16.91#ibcon#*before return 0, iclass 34, count 0 2006.173.04:42:16.91#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.04:42:16.91#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.04:42:16.91#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.04:42:16.91#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.04:42:16.91$vck44/vb=1,4 2006.173.04:42:16.91#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.04:42:16.91#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.04:42:16.91#ibcon#ireg 11 cls_cnt 2 2006.173.04:42:16.91#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.04:42:16.91#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.04:42:16.91#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.04:42:16.91#ibcon#enter wrdev, iclass 36, count 2 2006.173.04:42:16.91#ibcon#first serial, iclass 36, count 2 2006.173.04:42:16.91#ibcon#enter sib2, iclass 36, count 2 2006.173.04:42:16.91#ibcon#flushed, iclass 36, count 2 2006.173.04:42:16.91#ibcon#about to write, iclass 36, count 2 2006.173.04:42:16.91#ibcon#wrote, iclass 36, count 2 2006.173.04:42:16.91#ibcon#about to read 3, iclass 36, count 2 2006.173.04:42:16.93#ibcon#read 3, iclass 36, count 2 2006.173.04:42:16.93#ibcon#about to read 4, iclass 36, count 2 2006.173.04:42:16.93#ibcon#read 4, iclass 36, count 2 2006.173.04:42:16.93#ibcon#about to read 5, iclass 36, count 2 2006.173.04:42:16.93#ibcon#read 5, iclass 36, count 2 2006.173.04:42:16.93#ibcon#about to read 6, iclass 36, count 2 2006.173.04:42:16.93#ibcon#read 6, iclass 36, count 2 2006.173.04:42:16.93#ibcon#end of sib2, iclass 36, count 2 2006.173.04:42:16.93#ibcon#*mode == 0, iclass 36, count 2 2006.173.04:42:16.93#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.04:42:16.93#ibcon#[27=AT01-04\r\n] 2006.173.04:42:16.93#ibcon#*before write, iclass 36, count 2 2006.173.04:42:16.93#ibcon#enter sib2, iclass 36, count 2 2006.173.04:42:16.93#ibcon#flushed, iclass 36, count 2 2006.173.04:42:16.93#ibcon#about to write, iclass 36, count 2 2006.173.04:42:16.93#ibcon#wrote, iclass 36, count 2 2006.173.04:42:16.93#ibcon#about to read 3, iclass 36, count 2 2006.173.04:42:16.96#ibcon#read 3, iclass 36, count 2 2006.173.04:42:16.96#ibcon#about to read 4, iclass 36, count 2 2006.173.04:42:16.96#ibcon#read 4, iclass 36, count 2 2006.173.04:42:16.96#ibcon#about to read 5, iclass 36, count 2 2006.173.04:42:16.96#ibcon#read 5, iclass 36, count 2 2006.173.04:42:16.96#ibcon#about to read 6, iclass 36, count 2 2006.173.04:42:16.96#ibcon#read 6, iclass 36, count 2 2006.173.04:42:16.96#ibcon#end of sib2, iclass 36, count 2 2006.173.04:42:16.96#ibcon#*after write, iclass 36, count 2 2006.173.04:42:16.96#ibcon#*before return 0, iclass 36, count 2 2006.173.04:42:16.96#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.04:42:16.96#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.04:42:16.96#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.04:42:16.96#ibcon#ireg 7 cls_cnt 0 2006.173.04:42:16.96#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.04:42:17.08#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.04:42:17.08#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.04:42:17.08#ibcon#enter wrdev, iclass 36, count 0 2006.173.04:42:17.08#ibcon#first serial, iclass 36, count 0 2006.173.04:42:17.08#ibcon#enter sib2, iclass 36, count 0 2006.173.04:42:17.08#ibcon#flushed, iclass 36, count 0 2006.173.04:42:17.08#ibcon#about to write, iclass 36, count 0 2006.173.04:42:17.08#ibcon#wrote, iclass 36, count 0 2006.173.04:42:17.08#ibcon#about to read 3, iclass 36, count 0 2006.173.04:42:17.10#ibcon#read 3, iclass 36, count 0 2006.173.04:42:17.10#ibcon#about to read 4, iclass 36, count 0 2006.173.04:42:17.10#ibcon#read 4, iclass 36, count 0 2006.173.04:42:17.10#ibcon#about to read 5, iclass 36, count 0 2006.173.04:42:17.10#ibcon#read 5, iclass 36, count 0 2006.173.04:42:17.10#ibcon#about to read 6, iclass 36, count 0 2006.173.04:42:17.10#ibcon#read 6, iclass 36, count 0 2006.173.04:42:17.10#ibcon#end of sib2, iclass 36, count 0 2006.173.04:42:17.10#ibcon#*mode == 0, iclass 36, count 0 2006.173.04:42:17.10#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.04:42:17.10#ibcon#[27=USB\r\n] 2006.173.04:42:17.10#ibcon#*before write, iclass 36, count 0 2006.173.04:42:17.10#ibcon#enter sib2, iclass 36, count 0 2006.173.04:42:17.10#ibcon#flushed, iclass 36, count 0 2006.173.04:42:17.10#ibcon#about to write, iclass 36, count 0 2006.173.04:42:17.10#ibcon#wrote, iclass 36, count 0 2006.173.04:42:17.10#ibcon#about to read 3, iclass 36, count 0 2006.173.04:42:17.13#ibcon#read 3, iclass 36, count 0 2006.173.04:42:17.13#ibcon#about to read 4, iclass 36, count 0 2006.173.04:42:17.13#ibcon#read 4, iclass 36, count 0 2006.173.04:42:17.13#ibcon#about to read 5, iclass 36, count 0 2006.173.04:42:17.13#ibcon#read 5, iclass 36, count 0 2006.173.04:42:17.13#ibcon#about to read 6, iclass 36, count 0 2006.173.04:42:17.13#ibcon#read 6, iclass 36, count 0 2006.173.04:42:17.13#ibcon#end of sib2, iclass 36, count 0 2006.173.04:42:17.13#ibcon#*after write, iclass 36, count 0 2006.173.04:42:17.13#ibcon#*before return 0, iclass 36, count 0 2006.173.04:42:17.13#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.04:42:17.13#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.04:42:17.13#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.04:42:17.13#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.04:42:17.13$vck44/vblo=2,634.99 2006.173.04:42:17.13#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.04:42:17.13#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.04:42:17.13#ibcon#ireg 17 cls_cnt 0 2006.173.04:42:17.13#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.04:42:17.13#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.04:42:17.13#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.04:42:17.13#ibcon#enter wrdev, iclass 38, count 0 2006.173.04:42:17.13#ibcon#first serial, iclass 38, count 0 2006.173.04:42:17.13#ibcon#enter sib2, iclass 38, count 0 2006.173.04:42:17.13#ibcon#flushed, iclass 38, count 0 2006.173.04:42:17.13#ibcon#about to write, iclass 38, count 0 2006.173.04:42:17.13#ibcon#wrote, iclass 38, count 0 2006.173.04:42:17.14#ibcon#about to read 3, iclass 38, count 0 2006.173.04:42:17.15#ibcon#read 3, iclass 38, count 0 2006.173.04:42:17.15#ibcon#about to read 4, iclass 38, count 0 2006.173.04:42:17.15#ibcon#read 4, iclass 38, count 0 2006.173.04:42:17.15#ibcon#about to read 5, iclass 38, count 0 2006.173.04:42:17.15#ibcon#read 5, iclass 38, count 0 2006.173.04:42:17.15#ibcon#about to read 6, iclass 38, count 0 2006.173.04:42:17.15#ibcon#read 6, iclass 38, count 0 2006.173.04:42:17.15#ibcon#end of sib2, iclass 38, count 0 2006.173.04:42:17.15#ibcon#*mode == 0, iclass 38, count 0 2006.173.04:42:17.15#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.04:42:17.15#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.04:42:17.15#ibcon#*before write, iclass 38, count 0 2006.173.04:42:17.15#ibcon#enter sib2, iclass 38, count 0 2006.173.04:42:17.15#ibcon#flushed, iclass 38, count 0 2006.173.04:42:17.15#ibcon#about to write, iclass 38, count 0 2006.173.04:42:17.15#ibcon#wrote, iclass 38, count 0 2006.173.04:42:17.15#ibcon#about to read 3, iclass 38, count 0 2006.173.04:42:17.19#ibcon#read 3, iclass 38, count 0 2006.173.04:42:17.19#ibcon#about to read 4, iclass 38, count 0 2006.173.04:42:17.19#ibcon#read 4, iclass 38, count 0 2006.173.04:42:17.19#ibcon#about to read 5, iclass 38, count 0 2006.173.04:42:17.19#ibcon#read 5, iclass 38, count 0 2006.173.04:42:17.19#ibcon#about to read 6, iclass 38, count 0 2006.173.04:42:17.19#ibcon#read 6, iclass 38, count 0 2006.173.04:42:17.19#ibcon#end of sib2, iclass 38, count 0 2006.173.04:42:17.19#ibcon#*after write, iclass 38, count 0 2006.173.04:42:17.19#ibcon#*before return 0, iclass 38, count 0 2006.173.04:42:17.19#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.04:42:17.19#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.04:42:17.19#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.04:42:17.19#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.04:42:17.19$vck44/vb=2,4 2006.173.04:42:17.19#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.04:42:17.19#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.04:42:17.19#ibcon#ireg 11 cls_cnt 2 2006.173.04:42:17.19#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.04:42:17.25#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.04:42:17.25#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.04:42:17.25#ibcon#enter wrdev, iclass 40, count 2 2006.173.04:42:17.25#ibcon#first serial, iclass 40, count 2 2006.173.04:42:17.25#ibcon#enter sib2, iclass 40, count 2 2006.173.04:42:17.25#ibcon#flushed, iclass 40, count 2 2006.173.04:42:17.25#ibcon#about to write, iclass 40, count 2 2006.173.04:42:17.25#ibcon#wrote, iclass 40, count 2 2006.173.04:42:17.25#ibcon#about to read 3, iclass 40, count 2 2006.173.04:42:17.27#ibcon#read 3, iclass 40, count 2 2006.173.04:42:17.27#ibcon#about to read 4, iclass 40, count 2 2006.173.04:42:17.27#ibcon#read 4, iclass 40, count 2 2006.173.04:42:17.27#ibcon#about to read 5, iclass 40, count 2 2006.173.04:42:17.27#ibcon#read 5, iclass 40, count 2 2006.173.04:42:17.27#ibcon#about to read 6, iclass 40, count 2 2006.173.04:42:17.27#ibcon#read 6, iclass 40, count 2 2006.173.04:42:17.27#ibcon#end of sib2, iclass 40, count 2 2006.173.04:42:17.27#ibcon#*mode == 0, iclass 40, count 2 2006.173.04:42:17.27#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.04:42:17.27#ibcon#[27=AT02-04\r\n] 2006.173.04:42:17.27#ibcon#*before write, iclass 40, count 2 2006.173.04:42:17.27#ibcon#enter sib2, iclass 40, count 2 2006.173.04:42:17.27#ibcon#flushed, iclass 40, count 2 2006.173.04:42:17.27#ibcon#about to write, iclass 40, count 2 2006.173.04:42:17.27#ibcon#wrote, iclass 40, count 2 2006.173.04:42:17.27#ibcon#about to read 3, iclass 40, count 2 2006.173.04:42:17.30#ibcon#read 3, iclass 40, count 2 2006.173.04:42:17.30#ibcon#about to read 4, iclass 40, count 2 2006.173.04:42:17.30#ibcon#read 4, iclass 40, count 2 2006.173.04:42:17.30#ibcon#about to read 5, iclass 40, count 2 2006.173.04:42:17.30#ibcon#read 5, iclass 40, count 2 2006.173.04:42:17.30#ibcon#about to read 6, iclass 40, count 2 2006.173.04:42:17.30#ibcon#read 6, iclass 40, count 2 2006.173.04:42:17.30#ibcon#end of sib2, iclass 40, count 2 2006.173.04:42:17.30#ibcon#*after write, iclass 40, count 2 2006.173.04:42:17.30#ibcon#*before return 0, iclass 40, count 2 2006.173.04:42:17.30#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.04:42:17.30#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.04:42:17.30#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.04:42:17.30#ibcon#ireg 7 cls_cnt 0 2006.173.04:42:17.30#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.04:42:17.42#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.04:42:17.42#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.04:42:17.42#ibcon#enter wrdev, iclass 40, count 0 2006.173.04:42:17.42#ibcon#first serial, iclass 40, count 0 2006.173.04:42:17.42#ibcon#enter sib2, iclass 40, count 0 2006.173.04:42:17.42#ibcon#flushed, iclass 40, count 0 2006.173.04:42:17.42#ibcon#about to write, iclass 40, count 0 2006.173.04:42:17.42#ibcon#wrote, iclass 40, count 0 2006.173.04:42:17.42#ibcon#about to read 3, iclass 40, count 0 2006.173.04:42:17.44#ibcon#read 3, iclass 40, count 0 2006.173.04:42:17.44#ibcon#about to read 4, iclass 40, count 0 2006.173.04:42:17.44#ibcon#read 4, iclass 40, count 0 2006.173.04:42:17.44#ibcon#about to read 5, iclass 40, count 0 2006.173.04:42:17.44#ibcon#read 5, iclass 40, count 0 2006.173.04:42:17.44#ibcon#about to read 6, iclass 40, count 0 2006.173.04:42:17.44#ibcon#read 6, iclass 40, count 0 2006.173.04:42:17.44#ibcon#end of sib2, iclass 40, count 0 2006.173.04:42:17.44#ibcon#*mode == 0, iclass 40, count 0 2006.173.04:42:17.44#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.04:42:17.44#ibcon#[27=USB\r\n] 2006.173.04:42:17.44#ibcon#*before write, iclass 40, count 0 2006.173.04:42:17.44#ibcon#enter sib2, iclass 40, count 0 2006.173.04:42:17.44#ibcon#flushed, iclass 40, count 0 2006.173.04:42:17.44#ibcon#about to write, iclass 40, count 0 2006.173.04:42:17.44#ibcon#wrote, iclass 40, count 0 2006.173.04:42:17.44#ibcon#about to read 3, iclass 40, count 0 2006.173.04:42:17.47#ibcon#read 3, iclass 40, count 0 2006.173.04:42:17.47#ibcon#about to read 4, iclass 40, count 0 2006.173.04:42:17.47#ibcon#read 4, iclass 40, count 0 2006.173.04:42:17.47#ibcon#about to read 5, iclass 40, count 0 2006.173.04:42:17.47#ibcon#read 5, iclass 40, count 0 2006.173.04:42:17.47#ibcon#about to read 6, iclass 40, count 0 2006.173.04:42:17.47#ibcon#read 6, iclass 40, count 0 2006.173.04:42:17.47#ibcon#end of sib2, iclass 40, count 0 2006.173.04:42:17.47#ibcon#*after write, iclass 40, count 0 2006.173.04:42:17.47#ibcon#*before return 0, iclass 40, count 0 2006.173.04:42:17.47#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.04:42:17.47#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.04:42:17.47#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.04:42:17.47#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.04:42:17.47$vck44/vblo=3,649.99 2006.173.04:42:17.47#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.04:42:17.47#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.04:42:17.47#ibcon#ireg 17 cls_cnt 0 2006.173.04:42:17.47#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.04:42:17.47#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.04:42:17.47#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.04:42:17.47#ibcon#enter wrdev, iclass 4, count 0 2006.173.04:42:17.47#ibcon#first serial, iclass 4, count 0 2006.173.04:42:17.47#ibcon#enter sib2, iclass 4, count 0 2006.173.04:42:17.47#ibcon#flushed, iclass 4, count 0 2006.173.04:42:17.47#ibcon#about to write, iclass 4, count 0 2006.173.04:42:17.47#ibcon#wrote, iclass 4, count 0 2006.173.04:42:17.47#ibcon#about to read 3, iclass 4, count 0 2006.173.04:42:17.49#ibcon#read 3, iclass 4, count 0 2006.173.04:42:17.49#ibcon#about to read 4, iclass 4, count 0 2006.173.04:42:17.49#ibcon#read 4, iclass 4, count 0 2006.173.04:42:17.49#ibcon#about to read 5, iclass 4, count 0 2006.173.04:42:17.49#ibcon#read 5, iclass 4, count 0 2006.173.04:42:17.49#ibcon#about to read 6, iclass 4, count 0 2006.173.04:42:17.49#ibcon#read 6, iclass 4, count 0 2006.173.04:42:17.49#ibcon#end of sib2, iclass 4, count 0 2006.173.04:42:17.49#ibcon#*mode == 0, iclass 4, count 0 2006.173.04:42:17.49#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.04:42:17.49#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.04:42:17.49#ibcon#*before write, iclass 4, count 0 2006.173.04:42:17.49#ibcon#enter sib2, iclass 4, count 0 2006.173.04:42:17.49#ibcon#flushed, iclass 4, count 0 2006.173.04:42:17.49#ibcon#about to write, iclass 4, count 0 2006.173.04:42:17.49#ibcon#wrote, iclass 4, count 0 2006.173.04:42:17.49#ibcon#about to read 3, iclass 4, count 0 2006.173.04:42:17.53#ibcon#read 3, iclass 4, count 0 2006.173.04:42:17.53#ibcon#about to read 4, iclass 4, count 0 2006.173.04:42:17.53#ibcon#read 4, iclass 4, count 0 2006.173.04:42:17.53#ibcon#about to read 5, iclass 4, count 0 2006.173.04:42:17.53#ibcon#read 5, iclass 4, count 0 2006.173.04:42:17.53#ibcon#about to read 6, iclass 4, count 0 2006.173.04:42:17.53#ibcon#read 6, iclass 4, count 0 2006.173.04:42:17.53#ibcon#end of sib2, iclass 4, count 0 2006.173.04:42:17.53#ibcon#*after write, iclass 4, count 0 2006.173.04:42:17.53#ibcon#*before return 0, iclass 4, count 0 2006.173.04:42:17.53#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.04:42:17.53#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.04:42:17.53#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.04:42:17.53#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.04:42:17.53$vck44/vb=3,4 2006.173.04:42:17.53#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.04:42:17.53#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.04:42:17.53#ibcon#ireg 11 cls_cnt 2 2006.173.04:42:17.53#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.04:42:17.59#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.04:42:17.59#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.04:42:17.59#ibcon#enter wrdev, iclass 6, count 2 2006.173.04:42:17.59#ibcon#first serial, iclass 6, count 2 2006.173.04:42:17.59#ibcon#enter sib2, iclass 6, count 2 2006.173.04:42:17.59#ibcon#flushed, iclass 6, count 2 2006.173.04:42:17.59#ibcon#about to write, iclass 6, count 2 2006.173.04:42:17.59#ibcon#wrote, iclass 6, count 2 2006.173.04:42:17.59#ibcon#about to read 3, iclass 6, count 2 2006.173.04:42:17.61#ibcon#read 3, iclass 6, count 2 2006.173.04:42:17.61#ibcon#about to read 4, iclass 6, count 2 2006.173.04:42:17.61#ibcon#read 4, iclass 6, count 2 2006.173.04:42:17.61#ibcon#about to read 5, iclass 6, count 2 2006.173.04:42:17.61#ibcon#read 5, iclass 6, count 2 2006.173.04:42:17.61#ibcon#about to read 6, iclass 6, count 2 2006.173.04:42:17.61#ibcon#read 6, iclass 6, count 2 2006.173.04:42:17.61#ibcon#end of sib2, iclass 6, count 2 2006.173.04:42:17.61#ibcon#*mode == 0, iclass 6, count 2 2006.173.04:42:17.61#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.04:42:17.61#ibcon#[27=AT03-04\r\n] 2006.173.04:42:17.61#ibcon#*before write, iclass 6, count 2 2006.173.04:42:17.61#ibcon#enter sib2, iclass 6, count 2 2006.173.04:42:17.61#ibcon#flushed, iclass 6, count 2 2006.173.04:42:17.61#ibcon#about to write, iclass 6, count 2 2006.173.04:42:17.61#ibcon#wrote, iclass 6, count 2 2006.173.04:42:17.61#ibcon#about to read 3, iclass 6, count 2 2006.173.04:42:17.64#ibcon#read 3, iclass 6, count 2 2006.173.04:42:17.64#ibcon#about to read 4, iclass 6, count 2 2006.173.04:42:17.64#ibcon#read 4, iclass 6, count 2 2006.173.04:42:17.64#ibcon#about to read 5, iclass 6, count 2 2006.173.04:42:17.64#ibcon#read 5, iclass 6, count 2 2006.173.04:42:17.64#ibcon#about to read 6, iclass 6, count 2 2006.173.04:42:17.64#ibcon#read 6, iclass 6, count 2 2006.173.04:42:17.64#ibcon#end of sib2, iclass 6, count 2 2006.173.04:42:17.64#ibcon#*after write, iclass 6, count 2 2006.173.04:42:17.64#ibcon#*before return 0, iclass 6, count 2 2006.173.04:42:17.64#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.04:42:17.64#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.04:42:17.64#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.04:42:17.64#ibcon#ireg 7 cls_cnt 0 2006.173.04:42:17.64#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.04:42:17.76#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.04:42:17.76#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.04:42:17.76#ibcon#enter wrdev, iclass 6, count 0 2006.173.04:42:17.76#ibcon#first serial, iclass 6, count 0 2006.173.04:42:17.76#ibcon#enter sib2, iclass 6, count 0 2006.173.04:42:17.76#ibcon#flushed, iclass 6, count 0 2006.173.04:42:17.76#ibcon#about to write, iclass 6, count 0 2006.173.04:42:17.76#ibcon#wrote, iclass 6, count 0 2006.173.04:42:17.76#ibcon#about to read 3, iclass 6, count 0 2006.173.04:42:17.78#ibcon#read 3, iclass 6, count 0 2006.173.04:42:17.78#ibcon#about to read 4, iclass 6, count 0 2006.173.04:42:17.78#ibcon#read 4, iclass 6, count 0 2006.173.04:42:17.78#ibcon#about to read 5, iclass 6, count 0 2006.173.04:42:17.78#ibcon#read 5, iclass 6, count 0 2006.173.04:42:17.78#ibcon#about to read 6, iclass 6, count 0 2006.173.04:42:17.78#ibcon#read 6, iclass 6, count 0 2006.173.04:42:17.78#ibcon#end of sib2, iclass 6, count 0 2006.173.04:42:17.78#ibcon#*mode == 0, iclass 6, count 0 2006.173.04:42:17.78#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.04:42:17.78#ibcon#[27=USB\r\n] 2006.173.04:42:17.78#ibcon#*before write, iclass 6, count 0 2006.173.04:42:17.78#ibcon#enter sib2, iclass 6, count 0 2006.173.04:42:17.78#ibcon#flushed, iclass 6, count 0 2006.173.04:42:17.78#ibcon#about to write, iclass 6, count 0 2006.173.04:42:17.78#ibcon#wrote, iclass 6, count 0 2006.173.04:42:17.78#ibcon#about to read 3, iclass 6, count 0 2006.173.04:42:17.81#ibcon#read 3, iclass 6, count 0 2006.173.04:42:17.81#ibcon#about to read 4, iclass 6, count 0 2006.173.04:42:17.81#ibcon#read 4, iclass 6, count 0 2006.173.04:42:17.81#ibcon#about to read 5, iclass 6, count 0 2006.173.04:42:17.81#ibcon#read 5, iclass 6, count 0 2006.173.04:42:17.81#ibcon#about to read 6, iclass 6, count 0 2006.173.04:42:17.81#ibcon#read 6, iclass 6, count 0 2006.173.04:42:17.81#ibcon#end of sib2, iclass 6, count 0 2006.173.04:42:17.81#ibcon#*after write, iclass 6, count 0 2006.173.04:42:17.81#ibcon#*before return 0, iclass 6, count 0 2006.173.04:42:17.81#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.04:42:17.81#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.04:42:17.81#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.04:42:17.81#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.04:42:17.81$vck44/vblo=4,679.99 2006.173.04:42:17.81#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.04:42:17.81#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.04:42:17.81#ibcon#ireg 17 cls_cnt 0 2006.173.04:42:17.81#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.04:42:17.81#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.04:42:17.81#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.04:42:17.81#ibcon#enter wrdev, iclass 10, count 0 2006.173.04:42:17.81#ibcon#first serial, iclass 10, count 0 2006.173.04:42:17.81#ibcon#enter sib2, iclass 10, count 0 2006.173.04:42:17.81#ibcon#flushed, iclass 10, count 0 2006.173.04:42:17.81#ibcon#about to write, iclass 10, count 0 2006.173.04:42:17.81#ibcon#wrote, iclass 10, count 0 2006.173.04:42:17.81#ibcon#about to read 3, iclass 10, count 0 2006.173.04:42:17.83#ibcon#read 3, iclass 10, count 0 2006.173.04:42:17.83#ibcon#about to read 4, iclass 10, count 0 2006.173.04:42:17.83#ibcon#read 4, iclass 10, count 0 2006.173.04:42:17.83#ibcon#about to read 5, iclass 10, count 0 2006.173.04:42:17.83#ibcon#read 5, iclass 10, count 0 2006.173.04:42:17.83#ibcon#about to read 6, iclass 10, count 0 2006.173.04:42:17.83#ibcon#read 6, iclass 10, count 0 2006.173.04:42:17.83#ibcon#end of sib2, iclass 10, count 0 2006.173.04:42:17.83#ibcon#*mode == 0, iclass 10, count 0 2006.173.04:42:17.83#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.04:42:17.83#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.04:42:17.83#ibcon#*before write, iclass 10, count 0 2006.173.04:42:17.83#ibcon#enter sib2, iclass 10, count 0 2006.173.04:42:17.83#ibcon#flushed, iclass 10, count 0 2006.173.04:42:17.83#ibcon#about to write, iclass 10, count 0 2006.173.04:42:17.83#ibcon#wrote, iclass 10, count 0 2006.173.04:42:17.83#ibcon#about to read 3, iclass 10, count 0 2006.173.04:42:17.87#ibcon#read 3, iclass 10, count 0 2006.173.04:42:17.87#ibcon#about to read 4, iclass 10, count 0 2006.173.04:42:17.87#ibcon#read 4, iclass 10, count 0 2006.173.04:42:17.87#ibcon#about to read 5, iclass 10, count 0 2006.173.04:42:17.87#ibcon#read 5, iclass 10, count 0 2006.173.04:42:17.87#ibcon#about to read 6, iclass 10, count 0 2006.173.04:42:17.87#ibcon#read 6, iclass 10, count 0 2006.173.04:42:17.87#ibcon#end of sib2, iclass 10, count 0 2006.173.04:42:17.87#ibcon#*after write, iclass 10, count 0 2006.173.04:42:17.87#ibcon#*before return 0, iclass 10, count 0 2006.173.04:42:17.87#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.04:42:17.87#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.04:42:17.87#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.04:42:17.87#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.04:42:17.87$vck44/vb=4,4 2006.173.04:42:17.87#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.04:42:17.87#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.04:42:17.87#ibcon#ireg 11 cls_cnt 2 2006.173.04:42:17.87#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.04:42:17.93#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.04:42:17.93#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.04:42:17.93#ibcon#enter wrdev, iclass 12, count 2 2006.173.04:42:17.93#ibcon#first serial, iclass 12, count 2 2006.173.04:42:17.93#ibcon#enter sib2, iclass 12, count 2 2006.173.04:42:17.93#ibcon#flushed, iclass 12, count 2 2006.173.04:42:17.93#ibcon#about to write, iclass 12, count 2 2006.173.04:42:17.93#ibcon#wrote, iclass 12, count 2 2006.173.04:42:17.93#ibcon#about to read 3, iclass 12, count 2 2006.173.04:42:17.95#ibcon#read 3, iclass 12, count 2 2006.173.04:42:17.95#ibcon#about to read 4, iclass 12, count 2 2006.173.04:42:17.95#ibcon#read 4, iclass 12, count 2 2006.173.04:42:17.95#ibcon#about to read 5, iclass 12, count 2 2006.173.04:42:17.95#ibcon#read 5, iclass 12, count 2 2006.173.04:42:17.95#ibcon#about to read 6, iclass 12, count 2 2006.173.04:42:17.95#ibcon#read 6, iclass 12, count 2 2006.173.04:42:17.95#ibcon#end of sib2, iclass 12, count 2 2006.173.04:42:17.95#ibcon#*mode == 0, iclass 12, count 2 2006.173.04:42:17.95#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.04:42:17.95#ibcon#[27=AT04-04\r\n] 2006.173.04:42:17.95#ibcon#*before write, iclass 12, count 2 2006.173.04:42:17.95#ibcon#enter sib2, iclass 12, count 2 2006.173.04:42:17.95#ibcon#flushed, iclass 12, count 2 2006.173.04:42:17.95#ibcon#about to write, iclass 12, count 2 2006.173.04:42:17.95#ibcon#wrote, iclass 12, count 2 2006.173.04:42:17.95#ibcon#about to read 3, iclass 12, count 2 2006.173.04:42:17.98#ibcon#read 3, iclass 12, count 2 2006.173.04:42:17.98#ibcon#about to read 4, iclass 12, count 2 2006.173.04:42:17.98#ibcon#read 4, iclass 12, count 2 2006.173.04:42:17.98#ibcon#about to read 5, iclass 12, count 2 2006.173.04:42:17.98#ibcon#read 5, iclass 12, count 2 2006.173.04:42:17.98#ibcon#about to read 6, iclass 12, count 2 2006.173.04:42:17.98#ibcon#read 6, iclass 12, count 2 2006.173.04:42:17.98#ibcon#end of sib2, iclass 12, count 2 2006.173.04:42:17.98#ibcon#*after write, iclass 12, count 2 2006.173.04:42:17.98#ibcon#*before return 0, iclass 12, count 2 2006.173.04:42:17.98#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.04:42:17.98#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.04:42:17.98#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.04:42:17.98#ibcon#ireg 7 cls_cnt 0 2006.173.04:42:17.98#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.04:42:18.10#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.04:42:18.10#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.04:42:18.10#ibcon#enter wrdev, iclass 12, count 0 2006.173.04:42:18.10#ibcon#first serial, iclass 12, count 0 2006.173.04:42:18.10#ibcon#enter sib2, iclass 12, count 0 2006.173.04:42:18.10#ibcon#flushed, iclass 12, count 0 2006.173.04:42:18.10#ibcon#about to write, iclass 12, count 0 2006.173.04:42:18.10#ibcon#wrote, iclass 12, count 0 2006.173.04:42:18.10#ibcon#about to read 3, iclass 12, count 0 2006.173.04:42:18.12#ibcon#read 3, iclass 12, count 0 2006.173.04:42:18.12#ibcon#about to read 4, iclass 12, count 0 2006.173.04:42:18.12#ibcon#read 4, iclass 12, count 0 2006.173.04:42:18.12#ibcon#about to read 5, iclass 12, count 0 2006.173.04:42:18.12#ibcon#read 5, iclass 12, count 0 2006.173.04:42:18.12#ibcon#about to read 6, iclass 12, count 0 2006.173.04:42:18.12#ibcon#read 6, iclass 12, count 0 2006.173.04:42:18.12#ibcon#end of sib2, iclass 12, count 0 2006.173.04:42:18.12#ibcon#*mode == 0, iclass 12, count 0 2006.173.04:42:18.12#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.04:42:18.12#ibcon#[27=USB\r\n] 2006.173.04:42:18.12#ibcon#*before write, iclass 12, count 0 2006.173.04:42:18.12#ibcon#enter sib2, iclass 12, count 0 2006.173.04:42:18.12#ibcon#flushed, iclass 12, count 0 2006.173.04:42:18.12#ibcon#about to write, iclass 12, count 0 2006.173.04:42:18.12#ibcon#wrote, iclass 12, count 0 2006.173.04:42:18.12#ibcon#about to read 3, iclass 12, count 0 2006.173.04:42:18.15#ibcon#read 3, iclass 12, count 0 2006.173.04:42:18.15#ibcon#about to read 4, iclass 12, count 0 2006.173.04:42:18.15#ibcon#read 4, iclass 12, count 0 2006.173.04:42:18.15#ibcon#about to read 5, iclass 12, count 0 2006.173.04:42:18.15#ibcon#read 5, iclass 12, count 0 2006.173.04:42:18.15#ibcon#about to read 6, iclass 12, count 0 2006.173.04:42:18.15#ibcon#read 6, iclass 12, count 0 2006.173.04:42:18.15#ibcon#end of sib2, iclass 12, count 0 2006.173.04:42:18.15#ibcon#*after write, iclass 12, count 0 2006.173.04:42:18.15#ibcon#*before return 0, iclass 12, count 0 2006.173.04:42:18.15#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.04:42:18.15#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.04:42:18.15#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.04:42:18.15#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.04:42:18.15$vck44/vblo=5,709.99 2006.173.04:42:18.15#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.04:42:18.15#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.04:42:18.15#ibcon#ireg 17 cls_cnt 0 2006.173.04:42:18.15#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.04:42:18.15#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.04:42:18.15#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.04:42:18.15#ibcon#enter wrdev, iclass 14, count 0 2006.173.04:42:18.15#ibcon#first serial, iclass 14, count 0 2006.173.04:42:18.15#ibcon#enter sib2, iclass 14, count 0 2006.173.04:42:18.15#ibcon#flushed, iclass 14, count 0 2006.173.04:42:18.15#ibcon#about to write, iclass 14, count 0 2006.173.04:42:18.15#ibcon#wrote, iclass 14, count 0 2006.173.04:42:18.15#ibcon#about to read 3, iclass 14, count 0 2006.173.04:42:18.17#ibcon#read 3, iclass 14, count 0 2006.173.04:42:18.17#ibcon#about to read 4, iclass 14, count 0 2006.173.04:42:18.17#ibcon#read 4, iclass 14, count 0 2006.173.04:42:18.17#ibcon#about to read 5, iclass 14, count 0 2006.173.04:42:18.17#ibcon#read 5, iclass 14, count 0 2006.173.04:42:18.17#ibcon#about to read 6, iclass 14, count 0 2006.173.04:42:18.17#ibcon#read 6, iclass 14, count 0 2006.173.04:42:18.17#ibcon#end of sib2, iclass 14, count 0 2006.173.04:42:18.17#ibcon#*mode == 0, iclass 14, count 0 2006.173.04:42:18.17#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.04:42:18.17#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.04:42:18.17#ibcon#*before write, iclass 14, count 0 2006.173.04:42:18.17#ibcon#enter sib2, iclass 14, count 0 2006.173.04:42:18.17#ibcon#flushed, iclass 14, count 0 2006.173.04:42:18.17#ibcon#about to write, iclass 14, count 0 2006.173.04:42:18.17#ibcon#wrote, iclass 14, count 0 2006.173.04:42:18.17#ibcon#about to read 3, iclass 14, count 0 2006.173.04:42:18.21#ibcon#read 3, iclass 14, count 0 2006.173.04:42:18.21#ibcon#about to read 4, iclass 14, count 0 2006.173.04:42:18.21#ibcon#read 4, iclass 14, count 0 2006.173.04:42:18.21#ibcon#about to read 5, iclass 14, count 0 2006.173.04:42:18.21#ibcon#read 5, iclass 14, count 0 2006.173.04:42:18.21#ibcon#about to read 6, iclass 14, count 0 2006.173.04:42:18.21#ibcon#read 6, iclass 14, count 0 2006.173.04:42:18.21#ibcon#end of sib2, iclass 14, count 0 2006.173.04:42:18.21#ibcon#*after write, iclass 14, count 0 2006.173.04:42:18.21#ibcon#*before return 0, iclass 14, count 0 2006.173.04:42:18.21#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.04:42:18.21#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.04:42:18.21#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.04:42:18.21#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.04:42:18.21$vck44/vb=5,4 2006.173.04:42:18.21#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.04:42:18.21#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.04:42:18.21#ibcon#ireg 11 cls_cnt 2 2006.173.04:42:18.21#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.04:42:18.27#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.04:42:18.27#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.04:42:18.27#ibcon#enter wrdev, iclass 16, count 2 2006.173.04:42:18.27#ibcon#first serial, iclass 16, count 2 2006.173.04:42:18.27#ibcon#enter sib2, iclass 16, count 2 2006.173.04:42:18.27#ibcon#flushed, iclass 16, count 2 2006.173.04:42:18.27#ibcon#about to write, iclass 16, count 2 2006.173.04:42:18.27#ibcon#wrote, iclass 16, count 2 2006.173.04:42:18.27#ibcon#about to read 3, iclass 16, count 2 2006.173.04:42:18.29#ibcon#read 3, iclass 16, count 2 2006.173.04:42:18.29#ibcon#about to read 4, iclass 16, count 2 2006.173.04:42:18.29#ibcon#read 4, iclass 16, count 2 2006.173.04:42:18.29#ibcon#about to read 5, iclass 16, count 2 2006.173.04:42:18.29#ibcon#read 5, iclass 16, count 2 2006.173.04:42:18.29#ibcon#about to read 6, iclass 16, count 2 2006.173.04:42:18.29#ibcon#read 6, iclass 16, count 2 2006.173.04:42:18.29#ibcon#end of sib2, iclass 16, count 2 2006.173.04:42:18.29#ibcon#*mode == 0, iclass 16, count 2 2006.173.04:42:18.29#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.04:42:18.29#ibcon#[27=AT05-04\r\n] 2006.173.04:42:18.29#ibcon#*before write, iclass 16, count 2 2006.173.04:42:18.29#ibcon#enter sib2, iclass 16, count 2 2006.173.04:42:18.29#ibcon#flushed, iclass 16, count 2 2006.173.04:42:18.29#ibcon#about to write, iclass 16, count 2 2006.173.04:42:18.29#ibcon#wrote, iclass 16, count 2 2006.173.04:42:18.29#ibcon#about to read 3, iclass 16, count 2 2006.173.04:42:18.32#ibcon#read 3, iclass 16, count 2 2006.173.04:42:18.32#ibcon#about to read 4, iclass 16, count 2 2006.173.04:42:18.32#ibcon#read 4, iclass 16, count 2 2006.173.04:42:18.32#ibcon#about to read 5, iclass 16, count 2 2006.173.04:42:18.32#ibcon#read 5, iclass 16, count 2 2006.173.04:42:18.32#ibcon#about to read 6, iclass 16, count 2 2006.173.04:42:18.32#ibcon#read 6, iclass 16, count 2 2006.173.04:42:18.32#ibcon#end of sib2, iclass 16, count 2 2006.173.04:42:18.32#ibcon#*after write, iclass 16, count 2 2006.173.04:42:18.32#ibcon#*before return 0, iclass 16, count 2 2006.173.04:42:18.32#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.04:42:18.32#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.04:42:18.32#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.04:42:18.32#ibcon#ireg 7 cls_cnt 0 2006.173.04:42:18.32#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.04:42:18.44#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.04:42:18.44#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.04:42:18.44#ibcon#enter wrdev, iclass 16, count 0 2006.173.04:42:18.44#ibcon#first serial, iclass 16, count 0 2006.173.04:42:18.44#ibcon#enter sib2, iclass 16, count 0 2006.173.04:42:18.44#ibcon#flushed, iclass 16, count 0 2006.173.04:42:18.44#ibcon#about to write, iclass 16, count 0 2006.173.04:42:18.44#ibcon#wrote, iclass 16, count 0 2006.173.04:42:18.44#ibcon#about to read 3, iclass 16, count 0 2006.173.04:42:18.46#ibcon#read 3, iclass 16, count 0 2006.173.04:42:18.46#ibcon#about to read 4, iclass 16, count 0 2006.173.04:42:18.46#ibcon#read 4, iclass 16, count 0 2006.173.04:42:18.46#ibcon#about to read 5, iclass 16, count 0 2006.173.04:42:18.46#ibcon#read 5, iclass 16, count 0 2006.173.04:42:18.46#ibcon#about to read 6, iclass 16, count 0 2006.173.04:42:18.46#ibcon#read 6, iclass 16, count 0 2006.173.04:42:18.46#ibcon#end of sib2, iclass 16, count 0 2006.173.04:42:18.46#ibcon#*mode == 0, iclass 16, count 0 2006.173.04:42:18.46#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.04:42:18.46#ibcon#[27=USB\r\n] 2006.173.04:42:18.46#ibcon#*before write, iclass 16, count 0 2006.173.04:42:18.46#ibcon#enter sib2, iclass 16, count 0 2006.173.04:42:18.46#ibcon#flushed, iclass 16, count 0 2006.173.04:42:18.46#ibcon#about to write, iclass 16, count 0 2006.173.04:42:18.46#ibcon#wrote, iclass 16, count 0 2006.173.04:42:18.46#ibcon#about to read 3, iclass 16, count 0 2006.173.04:42:18.49#ibcon#read 3, iclass 16, count 0 2006.173.04:42:18.49#ibcon#about to read 4, iclass 16, count 0 2006.173.04:42:18.49#ibcon#read 4, iclass 16, count 0 2006.173.04:42:18.49#ibcon#about to read 5, iclass 16, count 0 2006.173.04:42:18.49#ibcon#read 5, iclass 16, count 0 2006.173.04:42:18.49#ibcon#about to read 6, iclass 16, count 0 2006.173.04:42:18.49#ibcon#read 6, iclass 16, count 0 2006.173.04:42:18.49#ibcon#end of sib2, iclass 16, count 0 2006.173.04:42:18.49#ibcon#*after write, iclass 16, count 0 2006.173.04:42:18.49#ibcon#*before return 0, iclass 16, count 0 2006.173.04:42:18.49#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.04:42:18.49#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.04:42:18.49#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.04:42:18.49#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.04:42:18.49$vck44/vblo=6,719.99 2006.173.04:42:18.49#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.04:42:18.49#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.04:42:18.49#ibcon#ireg 17 cls_cnt 0 2006.173.04:42:18.49#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.04:42:18.49#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.04:42:18.49#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.04:42:18.49#ibcon#enter wrdev, iclass 18, count 0 2006.173.04:42:18.49#ibcon#first serial, iclass 18, count 0 2006.173.04:42:18.49#ibcon#enter sib2, iclass 18, count 0 2006.173.04:42:18.49#ibcon#flushed, iclass 18, count 0 2006.173.04:42:18.50#ibcon#about to write, iclass 18, count 0 2006.173.04:42:18.50#ibcon#wrote, iclass 18, count 0 2006.173.04:42:18.50#ibcon#about to read 3, iclass 18, count 0 2006.173.04:42:18.51#ibcon#read 3, iclass 18, count 0 2006.173.04:42:18.51#ibcon#about to read 4, iclass 18, count 0 2006.173.04:42:18.51#ibcon#read 4, iclass 18, count 0 2006.173.04:42:18.51#ibcon#about to read 5, iclass 18, count 0 2006.173.04:42:18.51#ibcon#read 5, iclass 18, count 0 2006.173.04:42:18.51#ibcon#about to read 6, iclass 18, count 0 2006.173.04:42:18.51#ibcon#read 6, iclass 18, count 0 2006.173.04:42:18.51#ibcon#end of sib2, iclass 18, count 0 2006.173.04:42:18.51#ibcon#*mode == 0, iclass 18, count 0 2006.173.04:42:18.51#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.04:42:18.51#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.04:42:18.51#ibcon#*before write, iclass 18, count 0 2006.173.04:42:18.51#ibcon#enter sib2, iclass 18, count 0 2006.173.04:42:18.51#ibcon#flushed, iclass 18, count 0 2006.173.04:42:18.51#ibcon#about to write, iclass 18, count 0 2006.173.04:42:18.51#ibcon#wrote, iclass 18, count 0 2006.173.04:42:18.51#ibcon#about to read 3, iclass 18, count 0 2006.173.04:42:18.55#ibcon#read 3, iclass 18, count 0 2006.173.04:42:18.55#ibcon#about to read 4, iclass 18, count 0 2006.173.04:42:18.55#ibcon#read 4, iclass 18, count 0 2006.173.04:42:18.55#ibcon#about to read 5, iclass 18, count 0 2006.173.04:42:18.55#ibcon#read 5, iclass 18, count 0 2006.173.04:42:18.55#ibcon#about to read 6, iclass 18, count 0 2006.173.04:42:18.55#ibcon#read 6, iclass 18, count 0 2006.173.04:42:18.55#ibcon#end of sib2, iclass 18, count 0 2006.173.04:42:18.55#ibcon#*after write, iclass 18, count 0 2006.173.04:42:18.55#ibcon#*before return 0, iclass 18, count 0 2006.173.04:42:18.55#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.04:42:18.55#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.04:42:18.55#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.04:42:18.55#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.04:42:18.55$vck44/vb=6,4 2006.173.04:42:18.55#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.04:42:18.55#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.04:42:18.55#ibcon#ireg 11 cls_cnt 2 2006.173.04:42:18.55#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.04:42:18.61#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.04:42:18.61#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.04:42:18.61#ibcon#enter wrdev, iclass 20, count 2 2006.173.04:42:18.61#ibcon#first serial, iclass 20, count 2 2006.173.04:42:18.61#ibcon#enter sib2, iclass 20, count 2 2006.173.04:42:18.61#ibcon#flushed, iclass 20, count 2 2006.173.04:42:18.61#ibcon#about to write, iclass 20, count 2 2006.173.04:42:18.61#ibcon#wrote, iclass 20, count 2 2006.173.04:42:18.61#ibcon#about to read 3, iclass 20, count 2 2006.173.04:42:18.63#ibcon#read 3, iclass 20, count 2 2006.173.04:42:18.63#ibcon#about to read 4, iclass 20, count 2 2006.173.04:42:18.63#ibcon#read 4, iclass 20, count 2 2006.173.04:42:18.63#ibcon#about to read 5, iclass 20, count 2 2006.173.04:42:18.63#ibcon#read 5, iclass 20, count 2 2006.173.04:42:18.63#ibcon#about to read 6, iclass 20, count 2 2006.173.04:42:18.63#ibcon#read 6, iclass 20, count 2 2006.173.04:42:18.63#ibcon#end of sib2, iclass 20, count 2 2006.173.04:42:18.63#ibcon#*mode == 0, iclass 20, count 2 2006.173.04:42:18.63#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.04:42:18.63#ibcon#[27=AT06-04\r\n] 2006.173.04:42:18.63#ibcon#*before write, iclass 20, count 2 2006.173.04:42:18.63#ibcon#enter sib2, iclass 20, count 2 2006.173.04:42:18.63#ibcon#flushed, iclass 20, count 2 2006.173.04:42:18.63#ibcon#about to write, iclass 20, count 2 2006.173.04:42:18.63#ibcon#wrote, iclass 20, count 2 2006.173.04:42:18.63#ibcon#about to read 3, iclass 20, count 2 2006.173.04:42:18.66#ibcon#read 3, iclass 20, count 2 2006.173.04:42:18.66#ibcon#about to read 4, iclass 20, count 2 2006.173.04:42:18.66#ibcon#read 4, iclass 20, count 2 2006.173.04:42:18.66#ibcon#about to read 5, iclass 20, count 2 2006.173.04:42:18.66#ibcon#read 5, iclass 20, count 2 2006.173.04:42:18.66#ibcon#about to read 6, iclass 20, count 2 2006.173.04:42:18.66#ibcon#read 6, iclass 20, count 2 2006.173.04:42:18.66#ibcon#end of sib2, iclass 20, count 2 2006.173.04:42:18.66#ibcon#*after write, iclass 20, count 2 2006.173.04:42:18.66#ibcon#*before return 0, iclass 20, count 2 2006.173.04:42:18.66#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.04:42:18.66#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.04:42:18.66#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.04:42:18.66#ibcon#ireg 7 cls_cnt 0 2006.173.04:42:18.66#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.04:42:18.78#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.04:42:18.78#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.04:42:18.78#ibcon#enter wrdev, iclass 20, count 0 2006.173.04:42:18.78#ibcon#first serial, iclass 20, count 0 2006.173.04:42:18.78#ibcon#enter sib2, iclass 20, count 0 2006.173.04:42:18.78#ibcon#flushed, iclass 20, count 0 2006.173.04:42:18.78#ibcon#about to write, iclass 20, count 0 2006.173.04:42:18.78#ibcon#wrote, iclass 20, count 0 2006.173.04:42:18.78#ibcon#about to read 3, iclass 20, count 0 2006.173.04:42:18.80#ibcon#read 3, iclass 20, count 0 2006.173.04:42:18.80#ibcon#about to read 4, iclass 20, count 0 2006.173.04:42:18.80#ibcon#read 4, iclass 20, count 0 2006.173.04:42:18.80#ibcon#about to read 5, iclass 20, count 0 2006.173.04:42:18.80#ibcon#read 5, iclass 20, count 0 2006.173.04:42:18.80#ibcon#about to read 6, iclass 20, count 0 2006.173.04:42:18.80#ibcon#read 6, iclass 20, count 0 2006.173.04:42:18.80#ibcon#end of sib2, iclass 20, count 0 2006.173.04:42:18.80#ibcon#*mode == 0, iclass 20, count 0 2006.173.04:42:18.80#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.04:42:18.80#ibcon#[27=USB\r\n] 2006.173.04:42:18.80#ibcon#*before write, iclass 20, count 0 2006.173.04:42:18.80#ibcon#enter sib2, iclass 20, count 0 2006.173.04:42:18.80#ibcon#flushed, iclass 20, count 0 2006.173.04:42:18.80#ibcon#about to write, iclass 20, count 0 2006.173.04:42:18.80#ibcon#wrote, iclass 20, count 0 2006.173.04:42:18.80#ibcon#about to read 3, iclass 20, count 0 2006.173.04:42:18.83#ibcon#read 3, iclass 20, count 0 2006.173.04:42:18.83#ibcon#about to read 4, iclass 20, count 0 2006.173.04:42:18.83#ibcon#read 4, iclass 20, count 0 2006.173.04:42:18.83#ibcon#about to read 5, iclass 20, count 0 2006.173.04:42:18.83#ibcon#read 5, iclass 20, count 0 2006.173.04:42:18.83#ibcon#about to read 6, iclass 20, count 0 2006.173.04:42:18.83#ibcon#read 6, iclass 20, count 0 2006.173.04:42:18.83#ibcon#end of sib2, iclass 20, count 0 2006.173.04:42:18.83#ibcon#*after write, iclass 20, count 0 2006.173.04:42:18.83#ibcon#*before return 0, iclass 20, count 0 2006.173.04:42:18.83#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.04:42:18.83#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.04:42:18.83#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.04:42:18.83#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.04:42:18.83$vck44/vblo=7,734.99 2006.173.04:42:18.83#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.04:42:18.83#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.04:42:18.83#ibcon#ireg 17 cls_cnt 0 2006.173.04:42:18.83#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.04:42:18.83#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.04:42:18.83#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.04:42:18.83#ibcon#enter wrdev, iclass 22, count 0 2006.173.04:42:18.83#ibcon#first serial, iclass 22, count 0 2006.173.04:42:18.83#ibcon#enter sib2, iclass 22, count 0 2006.173.04:42:18.83#ibcon#flushed, iclass 22, count 0 2006.173.04:42:18.83#ibcon#about to write, iclass 22, count 0 2006.173.04:42:18.83#ibcon#wrote, iclass 22, count 0 2006.173.04:42:18.83#ibcon#about to read 3, iclass 22, count 0 2006.173.04:42:18.85#ibcon#read 3, iclass 22, count 0 2006.173.04:42:18.85#ibcon#about to read 4, iclass 22, count 0 2006.173.04:42:18.85#ibcon#read 4, iclass 22, count 0 2006.173.04:42:18.85#ibcon#about to read 5, iclass 22, count 0 2006.173.04:42:18.85#ibcon#read 5, iclass 22, count 0 2006.173.04:42:18.85#ibcon#about to read 6, iclass 22, count 0 2006.173.04:42:18.85#ibcon#read 6, iclass 22, count 0 2006.173.04:42:18.85#ibcon#end of sib2, iclass 22, count 0 2006.173.04:42:18.85#ibcon#*mode == 0, iclass 22, count 0 2006.173.04:42:18.85#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.04:42:18.85#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.04:42:18.85#ibcon#*before write, iclass 22, count 0 2006.173.04:42:18.85#ibcon#enter sib2, iclass 22, count 0 2006.173.04:42:18.85#ibcon#flushed, iclass 22, count 0 2006.173.04:42:18.85#ibcon#about to write, iclass 22, count 0 2006.173.04:42:18.85#ibcon#wrote, iclass 22, count 0 2006.173.04:42:18.85#ibcon#about to read 3, iclass 22, count 0 2006.173.04:42:18.89#ibcon#read 3, iclass 22, count 0 2006.173.04:42:18.89#ibcon#about to read 4, iclass 22, count 0 2006.173.04:42:18.89#ibcon#read 4, iclass 22, count 0 2006.173.04:42:18.89#ibcon#about to read 5, iclass 22, count 0 2006.173.04:42:18.89#ibcon#read 5, iclass 22, count 0 2006.173.04:42:18.89#ibcon#about to read 6, iclass 22, count 0 2006.173.04:42:18.89#ibcon#read 6, iclass 22, count 0 2006.173.04:42:18.89#ibcon#end of sib2, iclass 22, count 0 2006.173.04:42:18.89#ibcon#*after write, iclass 22, count 0 2006.173.04:42:18.89#ibcon#*before return 0, iclass 22, count 0 2006.173.04:42:18.89#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.04:42:18.89#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.04:42:18.89#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.04:42:18.89#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.04:42:18.89$vck44/vb=7,4 2006.173.04:42:18.89#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.04:42:18.89#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.04:42:18.89#ibcon#ireg 11 cls_cnt 2 2006.173.04:42:18.89#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.04:42:18.95#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.04:42:18.95#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.04:42:18.95#ibcon#enter wrdev, iclass 24, count 2 2006.173.04:42:18.95#ibcon#first serial, iclass 24, count 2 2006.173.04:42:18.95#ibcon#enter sib2, iclass 24, count 2 2006.173.04:42:18.95#ibcon#flushed, iclass 24, count 2 2006.173.04:42:18.95#ibcon#about to write, iclass 24, count 2 2006.173.04:42:18.95#ibcon#wrote, iclass 24, count 2 2006.173.04:42:18.95#ibcon#about to read 3, iclass 24, count 2 2006.173.04:42:18.97#ibcon#read 3, iclass 24, count 2 2006.173.04:42:18.97#ibcon#about to read 4, iclass 24, count 2 2006.173.04:42:18.97#ibcon#read 4, iclass 24, count 2 2006.173.04:42:18.97#ibcon#about to read 5, iclass 24, count 2 2006.173.04:42:18.97#ibcon#read 5, iclass 24, count 2 2006.173.04:42:18.97#ibcon#about to read 6, iclass 24, count 2 2006.173.04:42:18.97#ibcon#read 6, iclass 24, count 2 2006.173.04:42:18.97#ibcon#end of sib2, iclass 24, count 2 2006.173.04:42:18.97#ibcon#*mode == 0, iclass 24, count 2 2006.173.04:42:18.97#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.04:42:18.97#ibcon#[27=AT07-04\r\n] 2006.173.04:42:18.97#ibcon#*before write, iclass 24, count 2 2006.173.04:42:18.97#ibcon#enter sib2, iclass 24, count 2 2006.173.04:42:18.97#ibcon#flushed, iclass 24, count 2 2006.173.04:42:18.97#ibcon#about to write, iclass 24, count 2 2006.173.04:42:18.97#ibcon#wrote, iclass 24, count 2 2006.173.04:42:18.97#ibcon#about to read 3, iclass 24, count 2 2006.173.04:42:19.00#ibcon#read 3, iclass 24, count 2 2006.173.04:42:19.00#ibcon#about to read 4, iclass 24, count 2 2006.173.04:42:19.00#ibcon#read 4, iclass 24, count 2 2006.173.04:42:19.00#ibcon#about to read 5, iclass 24, count 2 2006.173.04:42:19.00#ibcon#read 5, iclass 24, count 2 2006.173.04:42:19.00#ibcon#about to read 6, iclass 24, count 2 2006.173.04:42:19.00#ibcon#read 6, iclass 24, count 2 2006.173.04:42:19.00#ibcon#end of sib2, iclass 24, count 2 2006.173.04:42:19.00#ibcon#*after write, iclass 24, count 2 2006.173.04:42:19.00#ibcon#*before return 0, iclass 24, count 2 2006.173.04:42:19.00#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.04:42:19.00#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.04:42:19.00#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.04:42:19.00#ibcon#ireg 7 cls_cnt 0 2006.173.04:42:19.00#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.04:42:19.12#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.04:42:19.12#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.04:42:19.12#ibcon#enter wrdev, iclass 24, count 0 2006.173.04:42:19.12#ibcon#first serial, iclass 24, count 0 2006.173.04:42:19.12#ibcon#enter sib2, iclass 24, count 0 2006.173.04:42:19.12#ibcon#flushed, iclass 24, count 0 2006.173.04:42:19.12#ibcon#about to write, iclass 24, count 0 2006.173.04:42:19.12#ibcon#wrote, iclass 24, count 0 2006.173.04:42:19.12#ibcon#about to read 3, iclass 24, count 0 2006.173.04:42:19.14#ibcon#read 3, iclass 24, count 0 2006.173.04:42:19.14#ibcon#about to read 4, iclass 24, count 0 2006.173.04:42:19.14#ibcon#read 4, iclass 24, count 0 2006.173.04:42:19.14#ibcon#about to read 5, iclass 24, count 0 2006.173.04:42:19.14#ibcon#read 5, iclass 24, count 0 2006.173.04:42:19.14#ibcon#about to read 6, iclass 24, count 0 2006.173.04:42:19.14#ibcon#read 6, iclass 24, count 0 2006.173.04:42:19.14#ibcon#end of sib2, iclass 24, count 0 2006.173.04:42:19.14#ibcon#*mode == 0, iclass 24, count 0 2006.173.04:42:19.14#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.04:42:19.14#ibcon#[27=USB\r\n] 2006.173.04:42:19.14#ibcon#*before write, iclass 24, count 0 2006.173.04:42:19.14#ibcon#enter sib2, iclass 24, count 0 2006.173.04:42:19.14#ibcon#flushed, iclass 24, count 0 2006.173.04:42:19.14#ibcon#about to write, iclass 24, count 0 2006.173.04:42:19.14#ibcon#wrote, iclass 24, count 0 2006.173.04:42:19.14#ibcon#about to read 3, iclass 24, count 0 2006.173.04:42:19.17#ibcon#read 3, iclass 24, count 0 2006.173.04:42:19.17#ibcon#about to read 4, iclass 24, count 0 2006.173.04:42:19.17#ibcon#read 4, iclass 24, count 0 2006.173.04:42:19.17#ibcon#about to read 5, iclass 24, count 0 2006.173.04:42:19.17#ibcon#read 5, iclass 24, count 0 2006.173.04:42:19.17#ibcon#about to read 6, iclass 24, count 0 2006.173.04:42:19.17#ibcon#read 6, iclass 24, count 0 2006.173.04:42:19.17#ibcon#end of sib2, iclass 24, count 0 2006.173.04:42:19.17#ibcon#*after write, iclass 24, count 0 2006.173.04:42:19.17#ibcon#*before return 0, iclass 24, count 0 2006.173.04:42:19.17#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.04:42:19.17#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.04:42:19.17#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.04:42:19.17#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.04:42:19.17$vck44/vblo=8,744.99 2006.173.04:42:19.17#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.04:42:19.17#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.04:42:19.17#ibcon#ireg 17 cls_cnt 0 2006.173.04:42:19.17#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.04:42:19.17#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.04:42:19.17#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.04:42:19.17#ibcon#enter wrdev, iclass 26, count 0 2006.173.04:42:19.17#ibcon#first serial, iclass 26, count 0 2006.173.04:42:19.17#ibcon#enter sib2, iclass 26, count 0 2006.173.04:42:19.17#ibcon#flushed, iclass 26, count 0 2006.173.04:42:19.17#ibcon#about to write, iclass 26, count 0 2006.173.04:42:19.17#ibcon#wrote, iclass 26, count 0 2006.173.04:42:19.17#ibcon#about to read 3, iclass 26, count 0 2006.173.04:42:19.19#ibcon#read 3, iclass 26, count 0 2006.173.04:42:19.19#ibcon#about to read 4, iclass 26, count 0 2006.173.04:42:19.19#ibcon#read 4, iclass 26, count 0 2006.173.04:42:19.19#ibcon#about to read 5, iclass 26, count 0 2006.173.04:42:19.19#ibcon#read 5, iclass 26, count 0 2006.173.04:42:19.19#ibcon#about to read 6, iclass 26, count 0 2006.173.04:42:19.19#ibcon#read 6, iclass 26, count 0 2006.173.04:42:19.19#ibcon#end of sib2, iclass 26, count 0 2006.173.04:42:19.19#ibcon#*mode == 0, iclass 26, count 0 2006.173.04:42:19.19#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.04:42:19.19#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.04:42:19.19#ibcon#*before write, iclass 26, count 0 2006.173.04:42:19.19#ibcon#enter sib2, iclass 26, count 0 2006.173.04:42:19.19#ibcon#flushed, iclass 26, count 0 2006.173.04:42:19.19#ibcon#about to write, iclass 26, count 0 2006.173.04:42:19.19#ibcon#wrote, iclass 26, count 0 2006.173.04:42:19.19#ibcon#about to read 3, iclass 26, count 0 2006.173.04:42:19.23#ibcon#read 3, iclass 26, count 0 2006.173.04:42:19.23#ibcon#about to read 4, iclass 26, count 0 2006.173.04:42:19.23#ibcon#read 4, iclass 26, count 0 2006.173.04:42:19.23#ibcon#about to read 5, iclass 26, count 0 2006.173.04:42:19.23#ibcon#read 5, iclass 26, count 0 2006.173.04:42:19.23#ibcon#about to read 6, iclass 26, count 0 2006.173.04:42:19.23#ibcon#read 6, iclass 26, count 0 2006.173.04:42:19.23#ibcon#end of sib2, iclass 26, count 0 2006.173.04:42:19.23#ibcon#*after write, iclass 26, count 0 2006.173.04:42:19.23#ibcon#*before return 0, iclass 26, count 0 2006.173.04:42:19.23#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.04:42:19.23#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.04:42:19.23#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.04:42:19.23#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.04:42:19.23$vck44/vb=8,4 2006.173.04:42:19.23#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.04:42:19.23#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.04:42:19.23#ibcon#ireg 11 cls_cnt 2 2006.173.04:42:19.23#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.04:42:19.29#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.04:42:19.29#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.04:42:19.29#ibcon#enter wrdev, iclass 28, count 2 2006.173.04:42:19.29#ibcon#first serial, iclass 28, count 2 2006.173.04:42:19.29#ibcon#enter sib2, iclass 28, count 2 2006.173.04:42:19.29#ibcon#flushed, iclass 28, count 2 2006.173.04:42:19.29#ibcon#about to write, iclass 28, count 2 2006.173.04:42:19.29#ibcon#wrote, iclass 28, count 2 2006.173.04:42:19.29#ibcon#about to read 3, iclass 28, count 2 2006.173.04:42:19.31#ibcon#read 3, iclass 28, count 2 2006.173.04:42:19.31#ibcon#about to read 4, iclass 28, count 2 2006.173.04:42:19.31#ibcon#read 4, iclass 28, count 2 2006.173.04:42:19.31#ibcon#about to read 5, iclass 28, count 2 2006.173.04:42:19.31#ibcon#read 5, iclass 28, count 2 2006.173.04:42:19.31#ibcon#about to read 6, iclass 28, count 2 2006.173.04:42:19.31#ibcon#read 6, iclass 28, count 2 2006.173.04:42:19.31#ibcon#end of sib2, iclass 28, count 2 2006.173.04:42:19.31#ibcon#*mode == 0, iclass 28, count 2 2006.173.04:42:19.31#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.04:42:19.31#ibcon#[27=AT08-04\r\n] 2006.173.04:42:19.31#ibcon#*before write, iclass 28, count 2 2006.173.04:42:19.31#ibcon#enter sib2, iclass 28, count 2 2006.173.04:42:19.31#ibcon#flushed, iclass 28, count 2 2006.173.04:42:19.31#ibcon#about to write, iclass 28, count 2 2006.173.04:42:19.31#ibcon#wrote, iclass 28, count 2 2006.173.04:42:19.31#ibcon#about to read 3, iclass 28, count 2 2006.173.04:42:19.34#ibcon#read 3, iclass 28, count 2 2006.173.04:42:19.34#ibcon#about to read 4, iclass 28, count 2 2006.173.04:42:19.34#ibcon#read 4, iclass 28, count 2 2006.173.04:42:19.34#ibcon#about to read 5, iclass 28, count 2 2006.173.04:42:19.34#ibcon#read 5, iclass 28, count 2 2006.173.04:42:19.34#ibcon#about to read 6, iclass 28, count 2 2006.173.04:42:19.34#ibcon#read 6, iclass 28, count 2 2006.173.04:42:19.34#ibcon#end of sib2, iclass 28, count 2 2006.173.04:42:19.34#ibcon#*after write, iclass 28, count 2 2006.173.04:42:19.34#ibcon#*before return 0, iclass 28, count 2 2006.173.04:42:19.34#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.04:42:19.34#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.04:42:19.34#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.04:42:19.34#ibcon#ireg 7 cls_cnt 0 2006.173.04:42:19.34#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.04:42:19.46#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.04:42:19.46#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.04:42:19.46#ibcon#enter wrdev, iclass 28, count 0 2006.173.04:42:19.46#ibcon#first serial, iclass 28, count 0 2006.173.04:42:19.46#ibcon#enter sib2, iclass 28, count 0 2006.173.04:42:19.46#ibcon#flushed, iclass 28, count 0 2006.173.04:42:19.46#ibcon#about to write, iclass 28, count 0 2006.173.04:42:19.46#ibcon#wrote, iclass 28, count 0 2006.173.04:42:19.46#ibcon#about to read 3, iclass 28, count 0 2006.173.04:42:19.48#ibcon#read 3, iclass 28, count 0 2006.173.04:42:19.48#ibcon#about to read 4, iclass 28, count 0 2006.173.04:42:19.48#ibcon#read 4, iclass 28, count 0 2006.173.04:42:19.48#ibcon#about to read 5, iclass 28, count 0 2006.173.04:42:19.48#ibcon#read 5, iclass 28, count 0 2006.173.04:42:19.48#ibcon#about to read 6, iclass 28, count 0 2006.173.04:42:19.48#ibcon#read 6, iclass 28, count 0 2006.173.04:42:19.48#ibcon#end of sib2, iclass 28, count 0 2006.173.04:42:19.48#ibcon#*mode == 0, iclass 28, count 0 2006.173.04:42:19.48#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.04:42:19.48#ibcon#[27=USB\r\n] 2006.173.04:42:19.48#ibcon#*before write, iclass 28, count 0 2006.173.04:42:19.48#ibcon#enter sib2, iclass 28, count 0 2006.173.04:42:19.48#ibcon#flushed, iclass 28, count 0 2006.173.04:42:19.48#ibcon#about to write, iclass 28, count 0 2006.173.04:42:19.48#ibcon#wrote, iclass 28, count 0 2006.173.04:42:19.48#ibcon#about to read 3, iclass 28, count 0 2006.173.04:42:19.51#ibcon#read 3, iclass 28, count 0 2006.173.04:42:19.51#ibcon#about to read 4, iclass 28, count 0 2006.173.04:42:19.51#ibcon#read 4, iclass 28, count 0 2006.173.04:42:19.51#ibcon#about to read 5, iclass 28, count 0 2006.173.04:42:19.51#ibcon#read 5, iclass 28, count 0 2006.173.04:42:19.51#ibcon#about to read 6, iclass 28, count 0 2006.173.04:42:19.51#ibcon#read 6, iclass 28, count 0 2006.173.04:42:19.51#ibcon#end of sib2, iclass 28, count 0 2006.173.04:42:19.51#ibcon#*after write, iclass 28, count 0 2006.173.04:42:19.51#ibcon#*before return 0, iclass 28, count 0 2006.173.04:42:19.51#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.04:42:19.51#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.04:42:19.51#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.04:42:19.51#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.04:42:19.51$vck44/vabw=wide 2006.173.04:42:19.51#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.04:42:19.51#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.04:42:19.51#ibcon#ireg 8 cls_cnt 0 2006.173.04:42:19.51#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.04:42:19.51#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.04:42:19.51#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.04:42:19.51#ibcon#enter wrdev, iclass 30, count 0 2006.173.04:42:19.51#ibcon#first serial, iclass 30, count 0 2006.173.04:42:19.51#ibcon#enter sib2, iclass 30, count 0 2006.173.04:42:19.51#ibcon#flushed, iclass 30, count 0 2006.173.04:42:19.51#ibcon#about to write, iclass 30, count 0 2006.173.04:42:19.52#ibcon#wrote, iclass 30, count 0 2006.173.04:42:19.52#ibcon#about to read 3, iclass 30, count 0 2006.173.04:42:19.53#ibcon#read 3, iclass 30, count 0 2006.173.04:42:19.53#ibcon#about to read 4, iclass 30, count 0 2006.173.04:42:19.53#ibcon#read 4, iclass 30, count 0 2006.173.04:42:19.53#ibcon#about to read 5, iclass 30, count 0 2006.173.04:42:19.53#ibcon#read 5, iclass 30, count 0 2006.173.04:42:19.53#ibcon#about to read 6, iclass 30, count 0 2006.173.04:42:19.53#ibcon#read 6, iclass 30, count 0 2006.173.04:42:19.53#ibcon#end of sib2, iclass 30, count 0 2006.173.04:42:19.53#ibcon#*mode == 0, iclass 30, count 0 2006.173.04:42:19.53#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.04:42:19.53#ibcon#[25=BW32\r\n] 2006.173.04:42:19.53#ibcon#*before write, iclass 30, count 0 2006.173.04:42:19.53#ibcon#enter sib2, iclass 30, count 0 2006.173.04:42:19.53#ibcon#flushed, iclass 30, count 0 2006.173.04:42:19.53#ibcon#about to write, iclass 30, count 0 2006.173.04:42:19.53#ibcon#wrote, iclass 30, count 0 2006.173.04:42:19.53#ibcon#about to read 3, iclass 30, count 0 2006.173.04:42:19.56#ibcon#read 3, iclass 30, count 0 2006.173.04:42:19.56#ibcon#about to read 4, iclass 30, count 0 2006.173.04:42:19.56#ibcon#read 4, iclass 30, count 0 2006.173.04:42:19.56#ibcon#about to read 5, iclass 30, count 0 2006.173.04:42:19.56#ibcon#read 5, iclass 30, count 0 2006.173.04:42:19.56#ibcon#about to read 6, iclass 30, count 0 2006.173.04:42:19.56#ibcon#read 6, iclass 30, count 0 2006.173.04:42:19.56#ibcon#end of sib2, iclass 30, count 0 2006.173.04:42:19.56#ibcon#*after write, iclass 30, count 0 2006.173.04:42:19.56#ibcon#*before return 0, iclass 30, count 0 2006.173.04:42:19.56#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.04:42:19.56#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.04:42:19.56#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.04:42:19.56#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.04:42:19.56$vck44/vbbw=wide 2006.173.04:42:19.56#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.04:42:19.56#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.04:42:19.56#ibcon#ireg 8 cls_cnt 0 2006.173.04:42:19.56#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.04:42:19.63#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.04:42:19.63#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.04:42:19.63#ibcon#enter wrdev, iclass 32, count 0 2006.173.04:42:19.63#ibcon#first serial, iclass 32, count 0 2006.173.04:42:19.63#ibcon#enter sib2, iclass 32, count 0 2006.173.04:42:19.63#ibcon#flushed, iclass 32, count 0 2006.173.04:42:19.63#ibcon#about to write, iclass 32, count 0 2006.173.04:42:19.63#ibcon#wrote, iclass 32, count 0 2006.173.04:42:19.63#ibcon#about to read 3, iclass 32, count 0 2006.173.04:42:19.65#ibcon#read 3, iclass 32, count 0 2006.173.04:42:19.65#ibcon#about to read 4, iclass 32, count 0 2006.173.04:42:19.65#ibcon#read 4, iclass 32, count 0 2006.173.04:42:19.65#ibcon#about to read 5, iclass 32, count 0 2006.173.04:42:19.65#ibcon#read 5, iclass 32, count 0 2006.173.04:42:19.65#ibcon#about to read 6, iclass 32, count 0 2006.173.04:42:19.65#ibcon#read 6, iclass 32, count 0 2006.173.04:42:19.65#ibcon#end of sib2, iclass 32, count 0 2006.173.04:42:19.65#ibcon#*mode == 0, iclass 32, count 0 2006.173.04:42:19.65#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.04:42:19.65#ibcon#[27=BW32\r\n] 2006.173.04:42:19.65#ibcon#*before write, iclass 32, count 0 2006.173.04:42:19.65#ibcon#enter sib2, iclass 32, count 0 2006.173.04:42:19.65#ibcon#flushed, iclass 32, count 0 2006.173.04:42:19.65#ibcon#about to write, iclass 32, count 0 2006.173.04:42:19.65#ibcon#wrote, iclass 32, count 0 2006.173.04:42:19.65#ibcon#about to read 3, iclass 32, count 0 2006.173.04:42:19.68#ibcon#read 3, iclass 32, count 0 2006.173.04:42:19.68#ibcon#about to read 4, iclass 32, count 0 2006.173.04:42:19.68#ibcon#read 4, iclass 32, count 0 2006.173.04:42:19.68#ibcon#about to read 5, iclass 32, count 0 2006.173.04:42:19.68#ibcon#read 5, iclass 32, count 0 2006.173.04:42:19.68#ibcon#about to read 6, iclass 32, count 0 2006.173.04:42:19.68#ibcon#read 6, iclass 32, count 0 2006.173.04:42:19.68#ibcon#end of sib2, iclass 32, count 0 2006.173.04:42:19.68#ibcon#*after write, iclass 32, count 0 2006.173.04:42:19.68#ibcon#*before return 0, iclass 32, count 0 2006.173.04:42:19.68#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.04:42:19.68#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.04:42:19.68#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.04:42:19.68#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.04:42:19.68$setupk4/ifdk4 2006.173.04:42:19.68$ifdk4/lo= 2006.173.04:42:19.68$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.04:42:19.69$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.04:42:19.69$ifdk4/patch= 2006.173.04:42:19.69$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.04:42:19.69$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.04:42:19.69$setupk4/!*+20s 2006.173.04:42:25.47#abcon#<5=/16 1.0 2.4 23.43 761005.8\r\n> 2006.173.04:42:25.49#abcon#{5=INTERFACE CLEAR} 2006.173.04:42:25.55#abcon#[5=S1D000X0/0*\r\n] 2006.173.04:42:34.20$setupk4/"tpicd 2006.173.04:42:34.20$setupk4/echo=off 2006.173.04:42:34.20$setupk4/xlog=off 2006.173.04:42:34.20:!2006.173.04:55:42 2006.173.04:42:36.14#trakl#Source acquired 2006.173.04:42:37.14#flagr#flagr/antenna,acquired 2006.173.04:55:42.00:preob 2006.173.04:55:42.14/onsource/TRACKING 2006.173.04:55:42.14:!2006.173.04:55:52 2006.173.04:55:52.00:"tape 2006.173.04:55:52.00:"st=record 2006.173.04:55:52.00:data_valid=on 2006.173.04:55:52.00:midob 2006.173.04:55:52.14/onsource/TRACKING 2006.173.04:55:52.14/wx/23.50,1005.5,76 2006.173.04:55:52.36/cable/+6.5069E-03 2006.173.04:55:53.45/va/01,07,usb,yes,37,40 2006.173.04:55:53.45/va/02,06,usb,yes,37,38 2006.173.04:55:53.45/va/03,05,usb,yes,47,49 2006.173.04:55:53.45/va/04,06,usb,yes,38,40 2006.173.04:55:53.45/va/05,04,usb,yes,29,30 2006.173.04:55:53.45/va/06,03,usb,yes,41,41 2006.173.04:55:53.45/va/07,04,usb,yes,33,35 2006.173.04:55:53.45/va/08,04,usb,yes,28,34 2006.173.04:55:53.68/valo/01,524.99,yes,locked 2006.173.04:55:53.68/valo/02,534.99,yes,locked 2006.173.04:55:53.68/valo/03,564.99,yes,locked 2006.173.04:55:53.68/valo/04,624.99,yes,locked 2006.173.04:55:53.68/valo/05,734.99,yes,locked 2006.173.04:55:53.68/valo/06,814.99,yes,locked 2006.173.04:55:53.68/valo/07,864.99,yes,locked 2006.173.04:55:53.68/valo/08,884.99,yes,locked 2006.173.04:55:54.77/vb/01,04,usb,yes,30,28 2006.173.04:55:54.77/vb/02,04,usb,yes,33,33 2006.173.04:55:54.77/vb/03,04,usb,yes,30,33 2006.173.04:55:54.77/vb/04,04,usb,yes,34,33 2006.173.04:55:54.77/vb/05,04,usb,yes,27,29 2006.173.04:55:54.77/vb/06,04,usb,yes,31,27 2006.173.04:55:54.77/vb/07,04,usb,yes,31,31 2006.173.04:55:54.77/vb/08,04,usb,yes,28,32 2006.173.04:55:55.01/vblo/01,629.99,yes,locked 2006.173.04:55:55.01/vblo/02,634.99,yes,locked 2006.173.04:55:55.01/vblo/03,649.99,yes,locked 2006.173.04:55:55.01/vblo/04,679.99,yes,locked 2006.173.04:55:55.01/vblo/05,709.99,yes,locked 2006.173.04:55:55.01/vblo/06,719.99,yes,locked 2006.173.04:55:55.01/vblo/07,734.99,yes,locked 2006.173.04:55:55.01/vblo/08,744.99,yes,locked 2006.173.04:55:55.16/vabw/8 2006.173.04:55:55.31/vbbw/8 2006.173.04:55:55.40/xfe/off,on,15.5 2006.173.04:55:55.78/ifatt/23,28,28,28 2006.173.04:55:56.07/fmout-gps/S +3.93E-07 2006.173.04:55:56.11:!2006.173.05:07:22 2006.173.05:07:22.00:data_valid=off 2006.173.05:07:22.00:"et 2006.173.05:07:22.01:!+3s 2006.173.05:07:25.02:"tape 2006.173.05:07:25.02:postob 2006.173.05:07:25.13/cable/+6.5080E-03 2006.173.05:07:25.13/wx/23.49,1005.5,79 2006.173.05:07:26.08/fmout-gps/S +3.97E-07 2006.173.05:07:26.08:scan_name=173-0511,jd0606,100 2006.173.05:07:26.09:source=3c274,123049.42,122328.0,2000.0,cw 2006.173.05:07:26.14#flagr#flagr/antenna,new-source 2006.173.05:07:27.14:checkk5 2006.173.05:07:27.54/chk_autoobs//k5ts1/ autoobs is running! 2006.173.05:07:27.95/chk_autoobs//k5ts2/ autoobs is running! 2006.173.05:07:28.36/chk_autoobs//k5ts3/ autoobs is running! 2006.173.05:07:28.75/chk_autoobs//k5ts4/ autoobs is running! 2006.173.05:07:29.45/chk_obsdata//k5ts1/T1730455??a.dat file size is correct (nominal:2760MB, actual:2756MB). 2006.173.05:07:30.15/chk_obsdata//k5ts2/T1730455??b.dat file size is correct (nominal:2760MB, actual:2756MB). 2006.173.05:07:30.85/chk_obsdata//k5ts3/T1730455??c.dat file size is correct (nominal:2760MB, actual:2756MB). 2006.173.05:07:31.55/chk_obsdata//k5ts4/T1730455??d.dat file size is correct (nominal:2760MB, actual:2756MB). 2006.173.05:07:32.27/k5log//k5ts1_log_newline 2006.173.05:07:32.97/k5log//k5ts2_log_newline 2006.173.05:07:33.68/k5log//k5ts3_log_newline 2006.173.05:07:34.38/k5log//k5ts4_log_newline 2006.173.05:07:34.40/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.05:07:34.40:setupk4=1 2006.173.05:07:34.40$setupk4/echo=on 2006.173.05:07:34.40$setupk4/pcalon 2006.173.05:07:34.40$pcalon/"no phase cal control is implemented here 2006.173.05:07:34.40$setupk4/"tpicd=stop 2006.173.05:07:34.40$setupk4/"rec=synch_on 2006.173.05:07:34.40$setupk4/"rec_mode=128 2006.173.05:07:34.40$setupk4/!* 2006.173.05:07:34.40$setupk4/recpk4 2006.173.05:07:34.40$recpk4/recpatch= 2006.173.05:07:34.41$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.05:07:34.41$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.05:07:34.41$setupk4/vck44 2006.173.05:07:34.41$vck44/valo=1,524.99 2006.173.05:07:34.41#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.05:07:34.41#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.05:07:34.41#ibcon#ireg 17 cls_cnt 0 2006.173.05:07:34.41#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.05:07:34.41#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.05:07:34.41#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.05:07:34.41#ibcon#enter wrdev, iclass 21, count 0 2006.173.05:07:34.41#ibcon#first serial, iclass 21, count 0 2006.173.05:07:34.41#ibcon#enter sib2, iclass 21, count 0 2006.173.05:07:34.41#ibcon#flushed, iclass 21, count 0 2006.173.05:07:34.41#ibcon#about to write, iclass 21, count 0 2006.173.05:07:34.41#ibcon#wrote, iclass 21, count 0 2006.173.05:07:34.41#ibcon#about to read 3, iclass 21, count 0 2006.173.05:07:34.43#ibcon#read 3, iclass 21, count 0 2006.173.05:07:34.43#ibcon#about to read 4, iclass 21, count 0 2006.173.05:07:34.43#ibcon#read 4, iclass 21, count 0 2006.173.05:07:34.43#ibcon#about to read 5, iclass 21, count 0 2006.173.05:07:34.43#ibcon#read 5, iclass 21, count 0 2006.173.05:07:34.43#ibcon#about to read 6, iclass 21, count 0 2006.173.05:07:34.43#ibcon#read 6, iclass 21, count 0 2006.173.05:07:34.43#ibcon#end of sib2, iclass 21, count 0 2006.173.05:07:34.43#ibcon#*mode == 0, iclass 21, count 0 2006.173.05:07:34.43#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.05:07:34.43#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.05:07:34.43#ibcon#*before write, iclass 21, count 0 2006.173.05:07:34.43#ibcon#enter sib2, iclass 21, count 0 2006.173.05:07:34.43#ibcon#flushed, iclass 21, count 0 2006.173.05:07:34.43#ibcon#about to write, iclass 21, count 0 2006.173.05:07:34.43#ibcon#wrote, iclass 21, count 0 2006.173.05:07:34.43#ibcon#about to read 3, iclass 21, count 0 2006.173.05:07:34.48#ibcon#read 3, iclass 21, count 0 2006.173.05:07:34.48#ibcon#about to read 4, iclass 21, count 0 2006.173.05:07:34.48#ibcon#read 4, iclass 21, count 0 2006.173.05:07:34.48#ibcon#about to read 5, iclass 21, count 0 2006.173.05:07:34.48#ibcon#read 5, iclass 21, count 0 2006.173.05:07:34.48#ibcon#about to read 6, iclass 21, count 0 2006.173.05:07:34.48#ibcon#read 6, iclass 21, count 0 2006.173.05:07:34.48#ibcon#end of sib2, iclass 21, count 0 2006.173.05:07:34.48#ibcon#*after write, iclass 21, count 0 2006.173.05:07:34.48#ibcon#*before return 0, iclass 21, count 0 2006.173.05:07:34.48#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.05:07:34.48#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.05:07:34.48#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.05:07:34.48#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.05:07:34.48$vck44/va=1,7 2006.173.05:07:34.48#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.05:07:34.48#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.05:07:34.48#ibcon#ireg 11 cls_cnt 2 2006.173.05:07:34.48#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.05:07:34.48#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.05:07:34.48#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.05:07:34.48#ibcon#enter wrdev, iclass 23, count 2 2006.173.05:07:34.48#ibcon#first serial, iclass 23, count 2 2006.173.05:07:34.48#ibcon#enter sib2, iclass 23, count 2 2006.173.05:07:34.48#ibcon#flushed, iclass 23, count 2 2006.173.05:07:34.48#ibcon#about to write, iclass 23, count 2 2006.173.05:07:34.48#ibcon#wrote, iclass 23, count 2 2006.173.05:07:34.48#ibcon#about to read 3, iclass 23, count 2 2006.173.05:07:34.50#ibcon#read 3, iclass 23, count 2 2006.173.05:07:34.50#ibcon#about to read 4, iclass 23, count 2 2006.173.05:07:34.50#ibcon#read 4, iclass 23, count 2 2006.173.05:07:34.50#ibcon#about to read 5, iclass 23, count 2 2006.173.05:07:34.50#ibcon#read 5, iclass 23, count 2 2006.173.05:07:34.50#ibcon#about to read 6, iclass 23, count 2 2006.173.05:07:34.50#ibcon#read 6, iclass 23, count 2 2006.173.05:07:34.50#ibcon#end of sib2, iclass 23, count 2 2006.173.05:07:34.50#ibcon#*mode == 0, iclass 23, count 2 2006.173.05:07:34.50#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.05:07:34.50#ibcon#[25=AT01-07\r\n] 2006.173.05:07:34.50#ibcon#*before write, iclass 23, count 2 2006.173.05:07:34.50#ibcon#enter sib2, iclass 23, count 2 2006.173.05:07:34.50#ibcon#flushed, iclass 23, count 2 2006.173.05:07:34.50#ibcon#about to write, iclass 23, count 2 2006.173.05:07:34.50#ibcon#wrote, iclass 23, count 2 2006.173.05:07:34.50#ibcon#about to read 3, iclass 23, count 2 2006.173.05:07:34.53#ibcon#read 3, iclass 23, count 2 2006.173.05:07:34.53#ibcon#about to read 4, iclass 23, count 2 2006.173.05:07:34.53#ibcon#read 4, iclass 23, count 2 2006.173.05:07:34.53#ibcon#about to read 5, iclass 23, count 2 2006.173.05:07:34.53#ibcon#read 5, iclass 23, count 2 2006.173.05:07:34.53#ibcon#about to read 6, iclass 23, count 2 2006.173.05:07:34.53#ibcon#read 6, iclass 23, count 2 2006.173.05:07:34.53#ibcon#end of sib2, iclass 23, count 2 2006.173.05:07:34.53#ibcon#*after write, iclass 23, count 2 2006.173.05:07:34.53#ibcon#*before return 0, iclass 23, count 2 2006.173.05:07:34.53#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.05:07:34.53#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.05:07:34.53#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.05:07:34.53#ibcon#ireg 7 cls_cnt 0 2006.173.05:07:34.53#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.05:07:34.65#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.05:07:34.65#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.05:07:34.65#ibcon#enter wrdev, iclass 23, count 0 2006.173.05:07:34.65#ibcon#first serial, iclass 23, count 0 2006.173.05:07:34.65#ibcon#enter sib2, iclass 23, count 0 2006.173.05:07:34.65#ibcon#flushed, iclass 23, count 0 2006.173.05:07:34.65#ibcon#about to write, iclass 23, count 0 2006.173.05:07:34.65#ibcon#wrote, iclass 23, count 0 2006.173.05:07:34.65#ibcon#about to read 3, iclass 23, count 0 2006.173.05:07:34.67#ibcon#read 3, iclass 23, count 0 2006.173.05:07:34.67#ibcon#about to read 4, iclass 23, count 0 2006.173.05:07:34.67#ibcon#read 4, iclass 23, count 0 2006.173.05:07:34.67#ibcon#about to read 5, iclass 23, count 0 2006.173.05:07:34.67#ibcon#read 5, iclass 23, count 0 2006.173.05:07:34.67#ibcon#about to read 6, iclass 23, count 0 2006.173.05:07:34.67#ibcon#read 6, iclass 23, count 0 2006.173.05:07:34.67#ibcon#end of sib2, iclass 23, count 0 2006.173.05:07:34.67#ibcon#*mode == 0, iclass 23, count 0 2006.173.05:07:34.67#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.05:07:34.67#ibcon#[25=USB\r\n] 2006.173.05:07:34.67#ibcon#*before write, iclass 23, count 0 2006.173.05:07:34.67#ibcon#enter sib2, iclass 23, count 0 2006.173.05:07:34.67#ibcon#flushed, iclass 23, count 0 2006.173.05:07:34.67#ibcon#about to write, iclass 23, count 0 2006.173.05:07:34.67#ibcon#wrote, iclass 23, count 0 2006.173.05:07:34.67#ibcon#about to read 3, iclass 23, count 0 2006.173.05:07:34.70#ibcon#read 3, iclass 23, count 0 2006.173.05:07:34.70#ibcon#about to read 4, iclass 23, count 0 2006.173.05:07:34.70#ibcon#read 4, iclass 23, count 0 2006.173.05:07:34.70#ibcon#about to read 5, iclass 23, count 0 2006.173.05:07:34.70#ibcon#read 5, iclass 23, count 0 2006.173.05:07:34.70#ibcon#about to read 6, iclass 23, count 0 2006.173.05:07:34.70#ibcon#read 6, iclass 23, count 0 2006.173.05:07:34.70#ibcon#end of sib2, iclass 23, count 0 2006.173.05:07:34.70#ibcon#*after write, iclass 23, count 0 2006.173.05:07:34.70#ibcon#*before return 0, iclass 23, count 0 2006.173.05:07:34.70#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.05:07:34.70#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.05:07:34.70#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.05:07:34.70#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.05:07:34.70$vck44/valo=2,534.99 2006.173.05:07:34.70#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.05:07:34.70#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.05:07:34.70#ibcon#ireg 17 cls_cnt 0 2006.173.05:07:34.70#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.05:07:34.70#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.05:07:34.70#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.05:07:34.70#ibcon#enter wrdev, iclass 25, count 0 2006.173.05:07:34.70#ibcon#first serial, iclass 25, count 0 2006.173.05:07:34.70#ibcon#enter sib2, iclass 25, count 0 2006.173.05:07:34.70#ibcon#flushed, iclass 25, count 0 2006.173.05:07:34.70#ibcon#about to write, iclass 25, count 0 2006.173.05:07:34.70#ibcon#wrote, iclass 25, count 0 2006.173.05:07:34.70#ibcon#about to read 3, iclass 25, count 0 2006.173.05:07:34.72#ibcon#read 3, iclass 25, count 0 2006.173.05:07:34.72#ibcon#about to read 4, iclass 25, count 0 2006.173.05:07:34.72#ibcon#read 4, iclass 25, count 0 2006.173.05:07:34.72#ibcon#about to read 5, iclass 25, count 0 2006.173.05:07:34.72#ibcon#read 5, iclass 25, count 0 2006.173.05:07:34.72#ibcon#about to read 6, iclass 25, count 0 2006.173.05:07:34.72#ibcon#read 6, iclass 25, count 0 2006.173.05:07:34.72#ibcon#end of sib2, iclass 25, count 0 2006.173.05:07:34.72#ibcon#*mode == 0, iclass 25, count 0 2006.173.05:07:34.72#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.05:07:34.72#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.05:07:34.72#ibcon#*before write, iclass 25, count 0 2006.173.05:07:34.72#ibcon#enter sib2, iclass 25, count 0 2006.173.05:07:34.72#ibcon#flushed, iclass 25, count 0 2006.173.05:07:34.72#ibcon#about to write, iclass 25, count 0 2006.173.05:07:34.72#ibcon#wrote, iclass 25, count 0 2006.173.05:07:34.72#ibcon#about to read 3, iclass 25, count 0 2006.173.05:07:34.76#ibcon#read 3, iclass 25, count 0 2006.173.05:07:34.76#ibcon#about to read 4, iclass 25, count 0 2006.173.05:07:34.76#ibcon#read 4, iclass 25, count 0 2006.173.05:07:34.76#ibcon#about to read 5, iclass 25, count 0 2006.173.05:07:34.76#ibcon#read 5, iclass 25, count 0 2006.173.05:07:34.76#ibcon#about to read 6, iclass 25, count 0 2006.173.05:07:34.76#ibcon#read 6, iclass 25, count 0 2006.173.05:07:34.76#ibcon#end of sib2, iclass 25, count 0 2006.173.05:07:34.76#ibcon#*after write, iclass 25, count 0 2006.173.05:07:34.76#ibcon#*before return 0, iclass 25, count 0 2006.173.05:07:34.76#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.05:07:34.76#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.05:07:34.76#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.05:07:34.76#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.05:07:34.76$vck44/va=2,6 2006.173.05:07:34.76#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.05:07:34.76#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.05:07:34.76#ibcon#ireg 11 cls_cnt 2 2006.173.05:07:34.76#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.05:07:34.82#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.05:07:34.82#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.05:07:34.82#ibcon#enter wrdev, iclass 27, count 2 2006.173.05:07:34.82#ibcon#first serial, iclass 27, count 2 2006.173.05:07:34.82#ibcon#enter sib2, iclass 27, count 2 2006.173.05:07:34.82#ibcon#flushed, iclass 27, count 2 2006.173.05:07:34.82#ibcon#about to write, iclass 27, count 2 2006.173.05:07:34.82#ibcon#wrote, iclass 27, count 2 2006.173.05:07:34.82#ibcon#about to read 3, iclass 27, count 2 2006.173.05:07:34.84#ibcon#read 3, iclass 27, count 2 2006.173.05:07:34.84#ibcon#about to read 4, iclass 27, count 2 2006.173.05:07:34.84#ibcon#read 4, iclass 27, count 2 2006.173.05:07:34.84#ibcon#about to read 5, iclass 27, count 2 2006.173.05:07:34.84#ibcon#read 5, iclass 27, count 2 2006.173.05:07:34.84#ibcon#about to read 6, iclass 27, count 2 2006.173.05:07:34.84#ibcon#read 6, iclass 27, count 2 2006.173.05:07:34.84#ibcon#end of sib2, iclass 27, count 2 2006.173.05:07:34.84#ibcon#*mode == 0, iclass 27, count 2 2006.173.05:07:34.84#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.05:07:34.84#ibcon#[25=AT02-06\r\n] 2006.173.05:07:34.84#ibcon#*before write, iclass 27, count 2 2006.173.05:07:34.84#ibcon#enter sib2, iclass 27, count 2 2006.173.05:07:34.84#ibcon#flushed, iclass 27, count 2 2006.173.05:07:34.84#ibcon#about to write, iclass 27, count 2 2006.173.05:07:34.84#ibcon#wrote, iclass 27, count 2 2006.173.05:07:34.84#ibcon#about to read 3, iclass 27, count 2 2006.173.05:07:34.87#ibcon#read 3, iclass 27, count 2 2006.173.05:07:34.87#ibcon#about to read 4, iclass 27, count 2 2006.173.05:07:34.87#ibcon#read 4, iclass 27, count 2 2006.173.05:07:34.87#ibcon#about to read 5, iclass 27, count 2 2006.173.05:07:34.87#ibcon#read 5, iclass 27, count 2 2006.173.05:07:34.87#ibcon#about to read 6, iclass 27, count 2 2006.173.05:07:34.87#ibcon#read 6, iclass 27, count 2 2006.173.05:07:34.87#ibcon#end of sib2, iclass 27, count 2 2006.173.05:07:34.87#ibcon#*after write, iclass 27, count 2 2006.173.05:07:34.87#ibcon#*before return 0, iclass 27, count 2 2006.173.05:07:34.87#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.05:07:34.87#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.05:07:34.87#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.05:07:34.87#ibcon#ireg 7 cls_cnt 0 2006.173.05:07:34.87#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.05:07:34.99#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.05:07:34.99#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.05:07:34.99#ibcon#enter wrdev, iclass 27, count 0 2006.173.05:07:34.99#ibcon#first serial, iclass 27, count 0 2006.173.05:07:34.99#ibcon#enter sib2, iclass 27, count 0 2006.173.05:07:34.99#ibcon#flushed, iclass 27, count 0 2006.173.05:07:34.99#ibcon#about to write, iclass 27, count 0 2006.173.05:07:34.99#ibcon#wrote, iclass 27, count 0 2006.173.05:07:34.99#ibcon#about to read 3, iclass 27, count 0 2006.173.05:07:35.01#ibcon#read 3, iclass 27, count 0 2006.173.05:07:35.01#ibcon#about to read 4, iclass 27, count 0 2006.173.05:07:35.01#ibcon#read 4, iclass 27, count 0 2006.173.05:07:35.01#ibcon#about to read 5, iclass 27, count 0 2006.173.05:07:35.01#ibcon#read 5, iclass 27, count 0 2006.173.05:07:35.01#ibcon#about to read 6, iclass 27, count 0 2006.173.05:07:35.01#ibcon#read 6, iclass 27, count 0 2006.173.05:07:35.01#ibcon#end of sib2, iclass 27, count 0 2006.173.05:07:35.01#ibcon#*mode == 0, iclass 27, count 0 2006.173.05:07:35.01#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.05:07:35.01#ibcon#[25=USB\r\n] 2006.173.05:07:35.01#ibcon#*before write, iclass 27, count 0 2006.173.05:07:35.01#ibcon#enter sib2, iclass 27, count 0 2006.173.05:07:35.01#ibcon#flushed, iclass 27, count 0 2006.173.05:07:35.01#ibcon#about to write, iclass 27, count 0 2006.173.05:07:35.01#ibcon#wrote, iclass 27, count 0 2006.173.05:07:35.01#ibcon#about to read 3, iclass 27, count 0 2006.173.05:07:35.04#ibcon#read 3, iclass 27, count 0 2006.173.05:07:35.04#ibcon#about to read 4, iclass 27, count 0 2006.173.05:07:35.04#ibcon#read 4, iclass 27, count 0 2006.173.05:07:35.04#ibcon#about to read 5, iclass 27, count 0 2006.173.05:07:35.04#ibcon#read 5, iclass 27, count 0 2006.173.05:07:35.04#ibcon#about to read 6, iclass 27, count 0 2006.173.05:07:35.04#ibcon#read 6, iclass 27, count 0 2006.173.05:07:35.04#ibcon#end of sib2, iclass 27, count 0 2006.173.05:07:35.04#ibcon#*after write, iclass 27, count 0 2006.173.05:07:35.04#ibcon#*before return 0, iclass 27, count 0 2006.173.05:07:35.04#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.05:07:35.04#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.05:07:35.04#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.05:07:35.04#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.05:07:35.04$vck44/valo=3,564.99 2006.173.05:07:35.04#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.05:07:35.04#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.05:07:35.04#ibcon#ireg 17 cls_cnt 0 2006.173.05:07:35.04#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.05:07:35.04#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.05:07:35.04#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.05:07:35.04#ibcon#enter wrdev, iclass 29, count 0 2006.173.05:07:35.04#ibcon#first serial, iclass 29, count 0 2006.173.05:07:35.04#ibcon#enter sib2, iclass 29, count 0 2006.173.05:07:35.04#ibcon#flushed, iclass 29, count 0 2006.173.05:07:35.04#ibcon#about to write, iclass 29, count 0 2006.173.05:07:35.04#ibcon#wrote, iclass 29, count 0 2006.173.05:07:35.04#ibcon#about to read 3, iclass 29, count 0 2006.173.05:07:35.06#ibcon#read 3, iclass 29, count 0 2006.173.05:07:35.06#ibcon#about to read 4, iclass 29, count 0 2006.173.05:07:35.06#ibcon#read 4, iclass 29, count 0 2006.173.05:07:35.06#ibcon#about to read 5, iclass 29, count 0 2006.173.05:07:35.06#ibcon#read 5, iclass 29, count 0 2006.173.05:07:35.06#ibcon#about to read 6, iclass 29, count 0 2006.173.05:07:35.06#ibcon#read 6, iclass 29, count 0 2006.173.05:07:35.06#ibcon#end of sib2, iclass 29, count 0 2006.173.05:07:35.06#ibcon#*mode == 0, iclass 29, count 0 2006.173.05:07:35.06#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.05:07:35.06#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.05:07:35.06#ibcon#*before write, iclass 29, count 0 2006.173.05:07:35.06#ibcon#enter sib2, iclass 29, count 0 2006.173.05:07:35.06#ibcon#flushed, iclass 29, count 0 2006.173.05:07:35.06#ibcon#about to write, iclass 29, count 0 2006.173.05:07:35.06#ibcon#wrote, iclass 29, count 0 2006.173.05:07:35.06#ibcon#about to read 3, iclass 29, count 0 2006.173.05:07:35.10#ibcon#read 3, iclass 29, count 0 2006.173.05:07:35.10#ibcon#about to read 4, iclass 29, count 0 2006.173.05:07:35.10#ibcon#read 4, iclass 29, count 0 2006.173.05:07:35.10#ibcon#about to read 5, iclass 29, count 0 2006.173.05:07:35.10#ibcon#read 5, iclass 29, count 0 2006.173.05:07:35.10#ibcon#about to read 6, iclass 29, count 0 2006.173.05:07:35.10#ibcon#read 6, iclass 29, count 0 2006.173.05:07:35.10#ibcon#end of sib2, iclass 29, count 0 2006.173.05:07:35.10#ibcon#*after write, iclass 29, count 0 2006.173.05:07:35.10#ibcon#*before return 0, iclass 29, count 0 2006.173.05:07:35.10#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.05:07:35.10#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.05:07:35.10#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.05:07:35.10#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.05:07:35.10$vck44/va=3,5 2006.173.05:07:35.10#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.05:07:35.10#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.05:07:35.10#ibcon#ireg 11 cls_cnt 2 2006.173.05:07:35.10#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.05:07:35.16#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.05:07:35.16#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.05:07:35.16#ibcon#enter wrdev, iclass 31, count 2 2006.173.05:07:35.16#ibcon#first serial, iclass 31, count 2 2006.173.05:07:35.16#ibcon#enter sib2, iclass 31, count 2 2006.173.05:07:35.16#ibcon#flushed, iclass 31, count 2 2006.173.05:07:35.16#ibcon#about to write, iclass 31, count 2 2006.173.05:07:35.16#ibcon#wrote, iclass 31, count 2 2006.173.05:07:35.16#ibcon#about to read 3, iclass 31, count 2 2006.173.05:07:35.18#ibcon#read 3, iclass 31, count 2 2006.173.05:07:35.18#ibcon#about to read 4, iclass 31, count 2 2006.173.05:07:35.18#ibcon#read 4, iclass 31, count 2 2006.173.05:07:35.18#ibcon#about to read 5, iclass 31, count 2 2006.173.05:07:35.18#ibcon#read 5, iclass 31, count 2 2006.173.05:07:35.18#ibcon#about to read 6, iclass 31, count 2 2006.173.05:07:35.18#ibcon#read 6, iclass 31, count 2 2006.173.05:07:35.18#ibcon#end of sib2, iclass 31, count 2 2006.173.05:07:35.18#ibcon#*mode == 0, iclass 31, count 2 2006.173.05:07:35.18#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.05:07:35.18#ibcon#[25=AT03-05\r\n] 2006.173.05:07:35.18#ibcon#*before write, iclass 31, count 2 2006.173.05:07:35.18#ibcon#enter sib2, iclass 31, count 2 2006.173.05:07:35.18#ibcon#flushed, iclass 31, count 2 2006.173.05:07:35.18#ibcon#about to write, iclass 31, count 2 2006.173.05:07:35.18#ibcon#wrote, iclass 31, count 2 2006.173.05:07:35.18#ibcon#about to read 3, iclass 31, count 2 2006.173.05:07:35.21#ibcon#read 3, iclass 31, count 2 2006.173.05:07:35.21#ibcon#about to read 4, iclass 31, count 2 2006.173.05:07:35.21#ibcon#read 4, iclass 31, count 2 2006.173.05:07:35.21#ibcon#about to read 5, iclass 31, count 2 2006.173.05:07:35.21#ibcon#read 5, iclass 31, count 2 2006.173.05:07:35.21#ibcon#about to read 6, iclass 31, count 2 2006.173.05:07:35.21#ibcon#read 6, iclass 31, count 2 2006.173.05:07:35.21#ibcon#end of sib2, iclass 31, count 2 2006.173.05:07:35.21#ibcon#*after write, iclass 31, count 2 2006.173.05:07:35.21#ibcon#*before return 0, iclass 31, count 2 2006.173.05:07:35.21#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.05:07:35.21#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.05:07:35.21#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.05:07:35.21#ibcon#ireg 7 cls_cnt 0 2006.173.05:07:35.21#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.05:07:35.33#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.05:07:35.33#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.05:07:35.33#ibcon#enter wrdev, iclass 31, count 0 2006.173.05:07:35.33#ibcon#first serial, iclass 31, count 0 2006.173.05:07:35.33#ibcon#enter sib2, iclass 31, count 0 2006.173.05:07:35.33#ibcon#flushed, iclass 31, count 0 2006.173.05:07:35.33#ibcon#about to write, iclass 31, count 0 2006.173.05:07:35.33#ibcon#wrote, iclass 31, count 0 2006.173.05:07:35.33#ibcon#about to read 3, iclass 31, count 0 2006.173.05:07:35.35#ibcon#read 3, iclass 31, count 0 2006.173.05:07:35.35#ibcon#about to read 4, iclass 31, count 0 2006.173.05:07:35.35#ibcon#read 4, iclass 31, count 0 2006.173.05:07:35.35#ibcon#about to read 5, iclass 31, count 0 2006.173.05:07:35.35#ibcon#read 5, iclass 31, count 0 2006.173.05:07:35.35#ibcon#about to read 6, iclass 31, count 0 2006.173.05:07:35.35#ibcon#read 6, iclass 31, count 0 2006.173.05:07:35.35#ibcon#end of sib2, iclass 31, count 0 2006.173.05:07:35.35#ibcon#*mode == 0, iclass 31, count 0 2006.173.05:07:35.35#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.05:07:35.35#ibcon#[25=USB\r\n] 2006.173.05:07:35.35#ibcon#*before write, iclass 31, count 0 2006.173.05:07:35.35#ibcon#enter sib2, iclass 31, count 0 2006.173.05:07:35.35#ibcon#flushed, iclass 31, count 0 2006.173.05:07:35.35#ibcon#about to write, iclass 31, count 0 2006.173.05:07:35.35#ibcon#wrote, iclass 31, count 0 2006.173.05:07:35.35#ibcon#about to read 3, iclass 31, count 0 2006.173.05:07:35.38#ibcon#read 3, iclass 31, count 0 2006.173.05:07:35.38#ibcon#about to read 4, iclass 31, count 0 2006.173.05:07:35.38#ibcon#read 4, iclass 31, count 0 2006.173.05:07:35.38#ibcon#about to read 5, iclass 31, count 0 2006.173.05:07:35.38#ibcon#read 5, iclass 31, count 0 2006.173.05:07:35.38#ibcon#about to read 6, iclass 31, count 0 2006.173.05:07:35.38#ibcon#read 6, iclass 31, count 0 2006.173.05:07:35.38#ibcon#end of sib2, iclass 31, count 0 2006.173.05:07:35.38#ibcon#*after write, iclass 31, count 0 2006.173.05:07:35.38#ibcon#*before return 0, iclass 31, count 0 2006.173.05:07:35.38#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.05:07:35.38#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.05:07:35.38#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.05:07:35.38#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.05:07:35.38$vck44/valo=4,624.99 2006.173.05:07:35.38#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.05:07:35.38#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.05:07:35.38#ibcon#ireg 17 cls_cnt 0 2006.173.05:07:35.38#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.05:07:35.38#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.05:07:35.38#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.05:07:35.38#ibcon#enter wrdev, iclass 33, count 0 2006.173.05:07:35.38#ibcon#first serial, iclass 33, count 0 2006.173.05:07:35.38#ibcon#enter sib2, iclass 33, count 0 2006.173.05:07:35.38#ibcon#flushed, iclass 33, count 0 2006.173.05:07:35.38#ibcon#about to write, iclass 33, count 0 2006.173.05:07:35.38#ibcon#wrote, iclass 33, count 0 2006.173.05:07:35.38#ibcon#about to read 3, iclass 33, count 0 2006.173.05:07:35.40#ibcon#read 3, iclass 33, count 0 2006.173.05:07:35.40#ibcon#about to read 4, iclass 33, count 0 2006.173.05:07:35.40#ibcon#read 4, iclass 33, count 0 2006.173.05:07:35.40#ibcon#about to read 5, iclass 33, count 0 2006.173.05:07:35.40#ibcon#read 5, iclass 33, count 0 2006.173.05:07:35.40#ibcon#about to read 6, iclass 33, count 0 2006.173.05:07:35.40#ibcon#read 6, iclass 33, count 0 2006.173.05:07:35.40#ibcon#end of sib2, iclass 33, count 0 2006.173.05:07:35.40#ibcon#*mode == 0, iclass 33, count 0 2006.173.05:07:35.40#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.05:07:35.40#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.05:07:35.40#ibcon#*before write, iclass 33, count 0 2006.173.05:07:35.40#ibcon#enter sib2, iclass 33, count 0 2006.173.05:07:35.40#ibcon#flushed, iclass 33, count 0 2006.173.05:07:35.40#ibcon#about to write, iclass 33, count 0 2006.173.05:07:35.40#ibcon#wrote, iclass 33, count 0 2006.173.05:07:35.40#ibcon#about to read 3, iclass 33, count 0 2006.173.05:07:35.44#ibcon#read 3, iclass 33, count 0 2006.173.05:07:35.44#ibcon#about to read 4, iclass 33, count 0 2006.173.05:07:35.44#ibcon#read 4, iclass 33, count 0 2006.173.05:07:35.44#ibcon#about to read 5, iclass 33, count 0 2006.173.05:07:35.44#ibcon#read 5, iclass 33, count 0 2006.173.05:07:35.44#ibcon#about to read 6, iclass 33, count 0 2006.173.05:07:35.44#ibcon#read 6, iclass 33, count 0 2006.173.05:07:35.44#ibcon#end of sib2, iclass 33, count 0 2006.173.05:07:35.44#ibcon#*after write, iclass 33, count 0 2006.173.05:07:35.44#ibcon#*before return 0, iclass 33, count 0 2006.173.05:07:35.44#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.05:07:35.44#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.05:07:35.44#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.05:07:35.44#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.05:07:35.44$vck44/va=4,6 2006.173.05:07:35.44#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.05:07:35.44#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.05:07:35.44#ibcon#ireg 11 cls_cnt 2 2006.173.05:07:35.44#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.05:07:35.50#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.05:07:35.50#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.05:07:35.50#ibcon#enter wrdev, iclass 35, count 2 2006.173.05:07:35.50#ibcon#first serial, iclass 35, count 2 2006.173.05:07:35.50#ibcon#enter sib2, iclass 35, count 2 2006.173.05:07:35.50#ibcon#flushed, iclass 35, count 2 2006.173.05:07:35.50#ibcon#about to write, iclass 35, count 2 2006.173.05:07:35.50#ibcon#wrote, iclass 35, count 2 2006.173.05:07:35.50#ibcon#about to read 3, iclass 35, count 2 2006.173.05:07:35.52#ibcon#read 3, iclass 35, count 2 2006.173.05:07:35.52#ibcon#about to read 4, iclass 35, count 2 2006.173.05:07:35.52#ibcon#read 4, iclass 35, count 2 2006.173.05:07:35.52#ibcon#about to read 5, iclass 35, count 2 2006.173.05:07:35.52#ibcon#read 5, iclass 35, count 2 2006.173.05:07:35.52#ibcon#about to read 6, iclass 35, count 2 2006.173.05:07:35.52#ibcon#read 6, iclass 35, count 2 2006.173.05:07:35.52#ibcon#end of sib2, iclass 35, count 2 2006.173.05:07:35.52#ibcon#*mode == 0, iclass 35, count 2 2006.173.05:07:35.52#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.05:07:35.52#ibcon#[25=AT04-06\r\n] 2006.173.05:07:35.52#ibcon#*before write, iclass 35, count 2 2006.173.05:07:35.52#ibcon#enter sib2, iclass 35, count 2 2006.173.05:07:35.52#ibcon#flushed, iclass 35, count 2 2006.173.05:07:35.52#ibcon#about to write, iclass 35, count 2 2006.173.05:07:35.52#ibcon#wrote, iclass 35, count 2 2006.173.05:07:35.52#ibcon#about to read 3, iclass 35, count 2 2006.173.05:07:35.55#ibcon#read 3, iclass 35, count 2 2006.173.05:07:35.55#ibcon#about to read 4, iclass 35, count 2 2006.173.05:07:35.55#ibcon#read 4, iclass 35, count 2 2006.173.05:07:35.55#ibcon#about to read 5, iclass 35, count 2 2006.173.05:07:35.55#ibcon#read 5, iclass 35, count 2 2006.173.05:07:35.55#ibcon#about to read 6, iclass 35, count 2 2006.173.05:07:35.55#ibcon#read 6, iclass 35, count 2 2006.173.05:07:35.55#ibcon#end of sib2, iclass 35, count 2 2006.173.05:07:35.55#ibcon#*after write, iclass 35, count 2 2006.173.05:07:35.55#ibcon#*before return 0, iclass 35, count 2 2006.173.05:07:35.55#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.05:07:35.55#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.05:07:35.55#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.05:07:35.55#ibcon#ireg 7 cls_cnt 0 2006.173.05:07:35.55#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.05:07:35.67#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.05:07:35.67#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.05:07:35.67#ibcon#enter wrdev, iclass 35, count 0 2006.173.05:07:35.67#ibcon#first serial, iclass 35, count 0 2006.173.05:07:35.67#ibcon#enter sib2, iclass 35, count 0 2006.173.05:07:35.67#ibcon#flushed, iclass 35, count 0 2006.173.05:07:35.67#ibcon#about to write, iclass 35, count 0 2006.173.05:07:35.67#ibcon#wrote, iclass 35, count 0 2006.173.05:07:35.67#ibcon#about to read 3, iclass 35, count 0 2006.173.05:07:35.69#ibcon#read 3, iclass 35, count 0 2006.173.05:07:35.69#ibcon#about to read 4, iclass 35, count 0 2006.173.05:07:35.69#ibcon#read 4, iclass 35, count 0 2006.173.05:07:35.69#ibcon#about to read 5, iclass 35, count 0 2006.173.05:07:35.69#ibcon#read 5, iclass 35, count 0 2006.173.05:07:35.69#ibcon#about to read 6, iclass 35, count 0 2006.173.05:07:35.69#ibcon#read 6, iclass 35, count 0 2006.173.05:07:35.69#ibcon#end of sib2, iclass 35, count 0 2006.173.05:07:35.69#ibcon#*mode == 0, iclass 35, count 0 2006.173.05:07:35.69#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.05:07:35.69#ibcon#[25=USB\r\n] 2006.173.05:07:35.69#ibcon#*before write, iclass 35, count 0 2006.173.05:07:35.69#ibcon#enter sib2, iclass 35, count 0 2006.173.05:07:35.69#ibcon#flushed, iclass 35, count 0 2006.173.05:07:35.69#ibcon#about to write, iclass 35, count 0 2006.173.05:07:35.69#ibcon#wrote, iclass 35, count 0 2006.173.05:07:35.69#ibcon#about to read 3, iclass 35, count 0 2006.173.05:07:35.72#ibcon#read 3, iclass 35, count 0 2006.173.05:07:35.72#ibcon#about to read 4, iclass 35, count 0 2006.173.05:07:35.72#ibcon#read 4, iclass 35, count 0 2006.173.05:07:35.72#ibcon#about to read 5, iclass 35, count 0 2006.173.05:07:35.72#ibcon#read 5, iclass 35, count 0 2006.173.05:07:35.72#ibcon#about to read 6, iclass 35, count 0 2006.173.05:07:35.72#ibcon#read 6, iclass 35, count 0 2006.173.05:07:35.72#ibcon#end of sib2, iclass 35, count 0 2006.173.05:07:35.72#ibcon#*after write, iclass 35, count 0 2006.173.05:07:35.72#ibcon#*before return 0, iclass 35, count 0 2006.173.05:07:35.72#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.05:07:35.72#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.05:07:35.72#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.05:07:35.72#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.05:07:35.72$vck44/valo=5,734.99 2006.173.05:07:35.72#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.05:07:35.72#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.05:07:35.72#ibcon#ireg 17 cls_cnt 0 2006.173.05:07:35.72#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.05:07:35.72#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.05:07:35.72#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.05:07:35.72#ibcon#enter wrdev, iclass 37, count 0 2006.173.05:07:35.72#ibcon#first serial, iclass 37, count 0 2006.173.05:07:35.72#ibcon#enter sib2, iclass 37, count 0 2006.173.05:07:35.72#ibcon#flushed, iclass 37, count 0 2006.173.05:07:35.72#ibcon#about to write, iclass 37, count 0 2006.173.05:07:35.72#ibcon#wrote, iclass 37, count 0 2006.173.05:07:35.72#ibcon#about to read 3, iclass 37, count 0 2006.173.05:07:35.74#ibcon#read 3, iclass 37, count 0 2006.173.05:07:35.74#ibcon#about to read 4, iclass 37, count 0 2006.173.05:07:35.74#ibcon#read 4, iclass 37, count 0 2006.173.05:07:35.74#ibcon#about to read 5, iclass 37, count 0 2006.173.05:07:35.74#ibcon#read 5, iclass 37, count 0 2006.173.05:07:35.74#ibcon#about to read 6, iclass 37, count 0 2006.173.05:07:35.74#ibcon#read 6, iclass 37, count 0 2006.173.05:07:35.74#ibcon#end of sib2, iclass 37, count 0 2006.173.05:07:35.74#ibcon#*mode == 0, iclass 37, count 0 2006.173.05:07:35.74#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.05:07:35.74#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.05:07:35.74#ibcon#*before write, iclass 37, count 0 2006.173.05:07:35.74#ibcon#enter sib2, iclass 37, count 0 2006.173.05:07:35.74#ibcon#flushed, iclass 37, count 0 2006.173.05:07:35.74#ibcon#about to write, iclass 37, count 0 2006.173.05:07:35.74#ibcon#wrote, iclass 37, count 0 2006.173.05:07:35.74#ibcon#about to read 3, iclass 37, count 0 2006.173.05:07:35.78#ibcon#read 3, iclass 37, count 0 2006.173.05:07:35.78#ibcon#about to read 4, iclass 37, count 0 2006.173.05:07:35.78#ibcon#read 4, iclass 37, count 0 2006.173.05:07:35.78#ibcon#about to read 5, iclass 37, count 0 2006.173.05:07:35.78#ibcon#read 5, iclass 37, count 0 2006.173.05:07:35.78#ibcon#about to read 6, iclass 37, count 0 2006.173.05:07:35.78#ibcon#read 6, iclass 37, count 0 2006.173.05:07:35.78#ibcon#end of sib2, iclass 37, count 0 2006.173.05:07:35.78#ibcon#*after write, iclass 37, count 0 2006.173.05:07:35.78#ibcon#*before return 0, iclass 37, count 0 2006.173.05:07:35.78#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.05:07:35.78#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.05:07:35.78#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.05:07:35.78#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.05:07:35.78$vck44/va=5,4 2006.173.05:07:35.78#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.05:07:35.78#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.05:07:35.78#ibcon#ireg 11 cls_cnt 2 2006.173.05:07:35.78#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.05:07:35.84#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.05:07:35.84#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.05:07:35.84#ibcon#enter wrdev, iclass 39, count 2 2006.173.05:07:35.84#ibcon#first serial, iclass 39, count 2 2006.173.05:07:35.84#ibcon#enter sib2, iclass 39, count 2 2006.173.05:07:35.84#ibcon#flushed, iclass 39, count 2 2006.173.05:07:35.84#ibcon#about to write, iclass 39, count 2 2006.173.05:07:35.84#ibcon#wrote, iclass 39, count 2 2006.173.05:07:35.84#ibcon#about to read 3, iclass 39, count 2 2006.173.05:07:35.86#ibcon#read 3, iclass 39, count 2 2006.173.05:07:35.86#ibcon#about to read 4, iclass 39, count 2 2006.173.05:07:35.86#ibcon#read 4, iclass 39, count 2 2006.173.05:07:35.86#ibcon#about to read 5, iclass 39, count 2 2006.173.05:07:35.86#ibcon#read 5, iclass 39, count 2 2006.173.05:07:35.86#ibcon#about to read 6, iclass 39, count 2 2006.173.05:07:35.86#ibcon#read 6, iclass 39, count 2 2006.173.05:07:35.86#ibcon#end of sib2, iclass 39, count 2 2006.173.05:07:35.86#ibcon#*mode == 0, iclass 39, count 2 2006.173.05:07:35.86#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.05:07:35.86#ibcon#[25=AT05-04\r\n] 2006.173.05:07:35.86#ibcon#*before write, iclass 39, count 2 2006.173.05:07:35.86#ibcon#enter sib2, iclass 39, count 2 2006.173.05:07:35.86#ibcon#flushed, iclass 39, count 2 2006.173.05:07:35.86#ibcon#about to write, iclass 39, count 2 2006.173.05:07:35.86#ibcon#wrote, iclass 39, count 2 2006.173.05:07:35.86#ibcon#about to read 3, iclass 39, count 2 2006.173.05:07:35.89#ibcon#read 3, iclass 39, count 2 2006.173.05:07:35.89#ibcon#about to read 4, iclass 39, count 2 2006.173.05:07:35.89#ibcon#read 4, iclass 39, count 2 2006.173.05:07:35.89#ibcon#about to read 5, iclass 39, count 2 2006.173.05:07:35.89#ibcon#read 5, iclass 39, count 2 2006.173.05:07:35.89#ibcon#about to read 6, iclass 39, count 2 2006.173.05:07:35.89#ibcon#read 6, iclass 39, count 2 2006.173.05:07:35.89#ibcon#end of sib2, iclass 39, count 2 2006.173.05:07:35.89#ibcon#*after write, iclass 39, count 2 2006.173.05:07:35.89#ibcon#*before return 0, iclass 39, count 2 2006.173.05:07:35.89#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.05:07:35.89#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.05:07:35.89#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.05:07:35.89#ibcon#ireg 7 cls_cnt 0 2006.173.05:07:35.89#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.05:07:36.01#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.05:07:36.01#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.05:07:36.01#ibcon#enter wrdev, iclass 39, count 0 2006.173.05:07:36.01#ibcon#first serial, iclass 39, count 0 2006.173.05:07:36.01#ibcon#enter sib2, iclass 39, count 0 2006.173.05:07:36.01#ibcon#flushed, iclass 39, count 0 2006.173.05:07:36.01#ibcon#about to write, iclass 39, count 0 2006.173.05:07:36.01#ibcon#wrote, iclass 39, count 0 2006.173.05:07:36.01#ibcon#about to read 3, iclass 39, count 0 2006.173.05:07:36.03#ibcon#read 3, iclass 39, count 0 2006.173.05:07:36.03#ibcon#about to read 4, iclass 39, count 0 2006.173.05:07:36.03#ibcon#read 4, iclass 39, count 0 2006.173.05:07:36.03#ibcon#about to read 5, iclass 39, count 0 2006.173.05:07:36.03#ibcon#read 5, iclass 39, count 0 2006.173.05:07:36.03#ibcon#about to read 6, iclass 39, count 0 2006.173.05:07:36.03#ibcon#read 6, iclass 39, count 0 2006.173.05:07:36.03#ibcon#end of sib2, iclass 39, count 0 2006.173.05:07:36.03#ibcon#*mode == 0, iclass 39, count 0 2006.173.05:07:36.03#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.05:07:36.03#ibcon#[25=USB\r\n] 2006.173.05:07:36.03#ibcon#*before write, iclass 39, count 0 2006.173.05:07:36.03#ibcon#enter sib2, iclass 39, count 0 2006.173.05:07:36.03#ibcon#flushed, iclass 39, count 0 2006.173.05:07:36.03#ibcon#about to write, iclass 39, count 0 2006.173.05:07:36.03#ibcon#wrote, iclass 39, count 0 2006.173.05:07:36.03#ibcon#about to read 3, iclass 39, count 0 2006.173.05:07:36.06#ibcon#read 3, iclass 39, count 0 2006.173.05:07:36.06#ibcon#about to read 4, iclass 39, count 0 2006.173.05:07:36.06#ibcon#read 4, iclass 39, count 0 2006.173.05:07:36.06#ibcon#about to read 5, iclass 39, count 0 2006.173.05:07:36.06#ibcon#read 5, iclass 39, count 0 2006.173.05:07:36.06#ibcon#about to read 6, iclass 39, count 0 2006.173.05:07:36.06#ibcon#read 6, iclass 39, count 0 2006.173.05:07:36.06#ibcon#end of sib2, iclass 39, count 0 2006.173.05:07:36.06#ibcon#*after write, iclass 39, count 0 2006.173.05:07:36.06#ibcon#*before return 0, iclass 39, count 0 2006.173.05:07:36.06#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.05:07:36.06#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.05:07:36.06#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.05:07:36.06#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.05:07:36.06$vck44/valo=6,814.99 2006.173.05:07:36.06#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.05:07:36.06#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.05:07:36.06#ibcon#ireg 17 cls_cnt 0 2006.173.05:07:36.06#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.05:07:36.06#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.05:07:36.06#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.05:07:36.06#ibcon#enter wrdev, iclass 3, count 0 2006.173.05:07:36.06#ibcon#first serial, iclass 3, count 0 2006.173.05:07:36.06#ibcon#enter sib2, iclass 3, count 0 2006.173.05:07:36.06#ibcon#flushed, iclass 3, count 0 2006.173.05:07:36.06#ibcon#about to write, iclass 3, count 0 2006.173.05:07:36.06#ibcon#wrote, iclass 3, count 0 2006.173.05:07:36.06#ibcon#about to read 3, iclass 3, count 0 2006.173.05:07:36.08#ibcon#read 3, iclass 3, count 0 2006.173.05:07:36.08#ibcon#about to read 4, iclass 3, count 0 2006.173.05:07:36.08#ibcon#read 4, iclass 3, count 0 2006.173.05:07:36.08#ibcon#about to read 5, iclass 3, count 0 2006.173.05:07:36.08#ibcon#read 5, iclass 3, count 0 2006.173.05:07:36.08#ibcon#about to read 6, iclass 3, count 0 2006.173.05:07:36.08#ibcon#read 6, iclass 3, count 0 2006.173.05:07:36.08#ibcon#end of sib2, iclass 3, count 0 2006.173.05:07:36.08#ibcon#*mode == 0, iclass 3, count 0 2006.173.05:07:36.08#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.05:07:36.08#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.05:07:36.08#ibcon#*before write, iclass 3, count 0 2006.173.05:07:36.08#ibcon#enter sib2, iclass 3, count 0 2006.173.05:07:36.08#ibcon#flushed, iclass 3, count 0 2006.173.05:07:36.08#ibcon#about to write, iclass 3, count 0 2006.173.05:07:36.08#ibcon#wrote, iclass 3, count 0 2006.173.05:07:36.08#ibcon#about to read 3, iclass 3, count 0 2006.173.05:07:36.12#ibcon#read 3, iclass 3, count 0 2006.173.05:07:36.12#ibcon#about to read 4, iclass 3, count 0 2006.173.05:07:36.12#ibcon#read 4, iclass 3, count 0 2006.173.05:07:36.12#ibcon#about to read 5, iclass 3, count 0 2006.173.05:07:36.12#ibcon#read 5, iclass 3, count 0 2006.173.05:07:36.12#ibcon#about to read 6, iclass 3, count 0 2006.173.05:07:36.12#ibcon#read 6, iclass 3, count 0 2006.173.05:07:36.12#ibcon#end of sib2, iclass 3, count 0 2006.173.05:07:36.12#ibcon#*after write, iclass 3, count 0 2006.173.05:07:36.12#ibcon#*before return 0, iclass 3, count 0 2006.173.05:07:36.12#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.05:07:36.12#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.05:07:36.12#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.05:07:36.12#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.05:07:36.12$vck44/va=6,3 2006.173.05:07:36.12#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.05:07:36.12#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.05:07:36.12#ibcon#ireg 11 cls_cnt 2 2006.173.05:07:36.12#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.05:07:36.18#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.05:07:36.18#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.05:07:36.18#ibcon#enter wrdev, iclass 5, count 2 2006.173.05:07:36.18#ibcon#first serial, iclass 5, count 2 2006.173.05:07:36.18#ibcon#enter sib2, iclass 5, count 2 2006.173.05:07:36.18#ibcon#flushed, iclass 5, count 2 2006.173.05:07:36.18#ibcon#about to write, iclass 5, count 2 2006.173.05:07:36.18#ibcon#wrote, iclass 5, count 2 2006.173.05:07:36.18#ibcon#about to read 3, iclass 5, count 2 2006.173.05:07:36.20#ibcon#read 3, iclass 5, count 2 2006.173.05:07:36.20#ibcon#about to read 4, iclass 5, count 2 2006.173.05:07:36.20#ibcon#read 4, iclass 5, count 2 2006.173.05:07:36.20#ibcon#about to read 5, iclass 5, count 2 2006.173.05:07:36.20#ibcon#read 5, iclass 5, count 2 2006.173.05:07:36.20#ibcon#about to read 6, iclass 5, count 2 2006.173.05:07:36.20#ibcon#read 6, iclass 5, count 2 2006.173.05:07:36.20#ibcon#end of sib2, iclass 5, count 2 2006.173.05:07:36.20#ibcon#*mode == 0, iclass 5, count 2 2006.173.05:07:36.20#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.05:07:36.20#ibcon#[25=AT06-03\r\n] 2006.173.05:07:36.20#ibcon#*before write, iclass 5, count 2 2006.173.05:07:36.20#ibcon#enter sib2, iclass 5, count 2 2006.173.05:07:36.20#ibcon#flushed, iclass 5, count 2 2006.173.05:07:36.20#ibcon#about to write, iclass 5, count 2 2006.173.05:07:36.20#ibcon#wrote, iclass 5, count 2 2006.173.05:07:36.20#ibcon#about to read 3, iclass 5, count 2 2006.173.05:07:36.23#ibcon#read 3, iclass 5, count 2 2006.173.05:07:36.23#ibcon#about to read 4, iclass 5, count 2 2006.173.05:07:36.23#ibcon#read 4, iclass 5, count 2 2006.173.05:07:36.23#ibcon#about to read 5, iclass 5, count 2 2006.173.05:07:36.23#ibcon#read 5, iclass 5, count 2 2006.173.05:07:36.23#ibcon#about to read 6, iclass 5, count 2 2006.173.05:07:36.23#ibcon#read 6, iclass 5, count 2 2006.173.05:07:36.23#ibcon#end of sib2, iclass 5, count 2 2006.173.05:07:36.23#ibcon#*after write, iclass 5, count 2 2006.173.05:07:36.23#ibcon#*before return 0, iclass 5, count 2 2006.173.05:07:36.23#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.05:07:36.23#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.05:07:36.23#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.05:07:36.23#ibcon#ireg 7 cls_cnt 0 2006.173.05:07:36.23#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.05:07:36.35#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.05:07:36.35#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.05:07:36.35#ibcon#enter wrdev, iclass 5, count 0 2006.173.05:07:36.35#ibcon#first serial, iclass 5, count 0 2006.173.05:07:36.35#ibcon#enter sib2, iclass 5, count 0 2006.173.05:07:36.35#ibcon#flushed, iclass 5, count 0 2006.173.05:07:36.35#ibcon#about to write, iclass 5, count 0 2006.173.05:07:36.35#ibcon#wrote, iclass 5, count 0 2006.173.05:07:36.35#ibcon#about to read 3, iclass 5, count 0 2006.173.05:07:36.37#ibcon#read 3, iclass 5, count 0 2006.173.05:07:36.37#ibcon#about to read 4, iclass 5, count 0 2006.173.05:07:36.37#ibcon#read 4, iclass 5, count 0 2006.173.05:07:36.37#ibcon#about to read 5, iclass 5, count 0 2006.173.05:07:36.37#ibcon#read 5, iclass 5, count 0 2006.173.05:07:36.37#ibcon#about to read 6, iclass 5, count 0 2006.173.05:07:36.37#ibcon#read 6, iclass 5, count 0 2006.173.05:07:36.37#ibcon#end of sib2, iclass 5, count 0 2006.173.05:07:36.37#ibcon#*mode == 0, iclass 5, count 0 2006.173.05:07:36.37#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.05:07:36.37#ibcon#[25=USB\r\n] 2006.173.05:07:36.37#ibcon#*before write, iclass 5, count 0 2006.173.05:07:36.37#ibcon#enter sib2, iclass 5, count 0 2006.173.05:07:36.37#ibcon#flushed, iclass 5, count 0 2006.173.05:07:36.37#ibcon#about to write, iclass 5, count 0 2006.173.05:07:36.37#ibcon#wrote, iclass 5, count 0 2006.173.05:07:36.37#ibcon#about to read 3, iclass 5, count 0 2006.173.05:07:36.40#ibcon#read 3, iclass 5, count 0 2006.173.05:07:36.40#ibcon#about to read 4, iclass 5, count 0 2006.173.05:07:36.40#ibcon#read 4, iclass 5, count 0 2006.173.05:07:36.40#ibcon#about to read 5, iclass 5, count 0 2006.173.05:07:36.40#ibcon#read 5, iclass 5, count 0 2006.173.05:07:36.40#ibcon#about to read 6, iclass 5, count 0 2006.173.05:07:36.40#ibcon#read 6, iclass 5, count 0 2006.173.05:07:36.40#ibcon#end of sib2, iclass 5, count 0 2006.173.05:07:36.40#ibcon#*after write, iclass 5, count 0 2006.173.05:07:36.40#ibcon#*before return 0, iclass 5, count 0 2006.173.05:07:36.40#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.05:07:36.40#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.05:07:36.40#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.05:07:36.40#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.05:07:36.40$vck44/valo=7,864.99 2006.173.05:07:36.40#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.05:07:36.40#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.05:07:36.40#ibcon#ireg 17 cls_cnt 0 2006.173.05:07:36.40#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.05:07:36.40#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.05:07:36.40#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.05:07:36.40#ibcon#enter wrdev, iclass 7, count 0 2006.173.05:07:36.40#ibcon#first serial, iclass 7, count 0 2006.173.05:07:36.40#ibcon#enter sib2, iclass 7, count 0 2006.173.05:07:36.40#ibcon#flushed, iclass 7, count 0 2006.173.05:07:36.40#ibcon#about to write, iclass 7, count 0 2006.173.05:07:36.40#ibcon#wrote, iclass 7, count 0 2006.173.05:07:36.40#ibcon#about to read 3, iclass 7, count 0 2006.173.05:07:36.42#ibcon#read 3, iclass 7, count 0 2006.173.05:07:36.42#ibcon#about to read 4, iclass 7, count 0 2006.173.05:07:36.42#ibcon#read 4, iclass 7, count 0 2006.173.05:07:36.42#ibcon#about to read 5, iclass 7, count 0 2006.173.05:07:36.42#ibcon#read 5, iclass 7, count 0 2006.173.05:07:36.42#ibcon#about to read 6, iclass 7, count 0 2006.173.05:07:36.42#ibcon#read 6, iclass 7, count 0 2006.173.05:07:36.42#ibcon#end of sib2, iclass 7, count 0 2006.173.05:07:36.42#ibcon#*mode == 0, iclass 7, count 0 2006.173.05:07:36.42#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.05:07:36.42#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.05:07:36.42#ibcon#*before write, iclass 7, count 0 2006.173.05:07:36.42#ibcon#enter sib2, iclass 7, count 0 2006.173.05:07:36.42#ibcon#flushed, iclass 7, count 0 2006.173.05:07:36.42#ibcon#about to write, iclass 7, count 0 2006.173.05:07:36.42#ibcon#wrote, iclass 7, count 0 2006.173.05:07:36.42#ibcon#about to read 3, iclass 7, count 0 2006.173.05:07:36.46#ibcon#read 3, iclass 7, count 0 2006.173.05:07:36.46#ibcon#about to read 4, iclass 7, count 0 2006.173.05:07:36.46#ibcon#read 4, iclass 7, count 0 2006.173.05:07:36.46#ibcon#about to read 5, iclass 7, count 0 2006.173.05:07:36.46#ibcon#read 5, iclass 7, count 0 2006.173.05:07:36.46#ibcon#about to read 6, iclass 7, count 0 2006.173.05:07:36.46#ibcon#read 6, iclass 7, count 0 2006.173.05:07:36.46#ibcon#end of sib2, iclass 7, count 0 2006.173.05:07:36.46#ibcon#*after write, iclass 7, count 0 2006.173.05:07:36.46#ibcon#*before return 0, iclass 7, count 0 2006.173.05:07:36.46#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.05:07:36.46#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.05:07:36.46#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.05:07:36.46#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.05:07:36.46$vck44/va=7,4 2006.173.05:07:36.46#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.05:07:36.46#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.05:07:36.46#ibcon#ireg 11 cls_cnt 2 2006.173.05:07:36.46#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.05:07:36.52#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.05:07:36.52#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.05:07:36.52#ibcon#enter wrdev, iclass 11, count 2 2006.173.05:07:36.52#ibcon#first serial, iclass 11, count 2 2006.173.05:07:36.52#ibcon#enter sib2, iclass 11, count 2 2006.173.05:07:36.52#ibcon#flushed, iclass 11, count 2 2006.173.05:07:36.52#ibcon#about to write, iclass 11, count 2 2006.173.05:07:36.52#ibcon#wrote, iclass 11, count 2 2006.173.05:07:36.52#ibcon#about to read 3, iclass 11, count 2 2006.173.05:07:36.54#ibcon#read 3, iclass 11, count 2 2006.173.05:07:36.54#ibcon#about to read 4, iclass 11, count 2 2006.173.05:07:36.54#ibcon#read 4, iclass 11, count 2 2006.173.05:07:36.54#ibcon#about to read 5, iclass 11, count 2 2006.173.05:07:36.54#ibcon#read 5, iclass 11, count 2 2006.173.05:07:36.54#ibcon#about to read 6, iclass 11, count 2 2006.173.05:07:36.54#ibcon#read 6, iclass 11, count 2 2006.173.05:07:36.54#ibcon#end of sib2, iclass 11, count 2 2006.173.05:07:36.54#ibcon#*mode == 0, iclass 11, count 2 2006.173.05:07:36.54#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.05:07:36.54#ibcon#[25=AT07-04\r\n] 2006.173.05:07:36.54#ibcon#*before write, iclass 11, count 2 2006.173.05:07:36.54#ibcon#enter sib2, iclass 11, count 2 2006.173.05:07:36.54#ibcon#flushed, iclass 11, count 2 2006.173.05:07:36.54#ibcon#about to write, iclass 11, count 2 2006.173.05:07:36.54#ibcon#wrote, iclass 11, count 2 2006.173.05:07:36.54#ibcon#about to read 3, iclass 11, count 2 2006.173.05:07:36.57#ibcon#read 3, iclass 11, count 2 2006.173.05:07:36.57#ibcon#about to read 4, iclass 11, count 2 2006.173.05:07:36.57#ibcon#read 4, iclass 11, count 2 2006.173.05:07:36.57#ibcon#about to read 5, iclass 11, count 2 2006.173.05:07:36.57#ibcon#read 5, iclass 11, count 2 2006.173.05:07:36.57#ibcon#about to read 6, iclass 11, count 2 2006.173.05:07:36.57#ibcon#read 6, iclass 11, count 2 2006.173.05:07:36.57#ibcon#end of sib2, iclass 11, count 2 2006.173.05:07:36.57#ibcon#*after write, iclass 11, count 2 2006.173.05:07:36.57#ibcon#*before return 0, iclass 11, count 2 2006.173.05:07:36.57#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.05:07:36.57#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.05:07:36.57#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.05:07:36.57#ibcon#ireg 7 cls_cnt 0 2006.173.05:07:36.57#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.05:07:36.69#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.05:07:36.69#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.05:07:36.69#ibcon#enter wrdev, iclass 11, count 0 2006.173.05:07:36.69#ibcon#first serial, iclass 11, count 0 2006.173.05:07:36.69#ibcon#enter sib2, iclass 11, count 0 2006.173.05:07:36.69#ibcon#flushed, iclass 11, count 0 2006.173.05:07:36.69#ibcon#about to write, iclass 11, count 0 2006.173.05:07:36.69#ibcon#wrote, iclass 11, count 0 2006.173.05:07:36.69#ibcon#about to read 3, iclass 11, count 0 2006.173.05:07:36.71#ibcon#read 3, iclass 11, count 0 2006.173.05:07:36.71#ibcon#about to read 4, iclass 11, count 0 2006.173.05:07:36.71#ibcon#read 4, iclass 11, count 0 2006.173.05:07:36.71#ibcon#about to read 5, iclass 11, count 0 2006.173.05:07:36.71#ibcon#read 5, iclass 11, count 0 2006.173.05:07:36.71#ibcon#about to read 6, iclass 11, count 0 2006.173.05:07:36.71#ibcon#read 6, iclass 11, count 0 2006.173.05:07:36.71#ibcon#end of sib2, iclass 11, count 0 2006.173.05:07:36.71#ibcon#*mode == 0, iclass 11, count 0 2006.173.05:07:36.71#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.05:07:36.71#ibcon#[25=USB\r\n] 2006.173.05:07:36.71#ibcon#*before write, iclass 11, count 0 2006.173.05:07:36.71#ibcon#enter sib2, iclass 11, count 0 2006.173.05:07:36.71#ibcon#flushed, iclass 11, count 0 2006.173.05:07:36.71#ibcon#about to write, iclass 11, count 0 2006.173.05:07:36.71#ibcon#wrote, iclass 11, count 0 2006.173.05:07:36.71#ibcon#about to read 3, iclass 11, count 0 2006.173.05:07:36.74#ibcon#read 3, iclass 11, count 0 2006.173.05:07:36.74#ibcon#about to read 4, iclass 11, count 0 2006.173.05:07:36.74#ibcon#read 4, iclass 11, count 0 2006.173.05:07:36.74#ibcon#about to read 5, iclass 11, count 0 2006.173.05:07:36.74#ibcon#read 5, iclass 11, count 0 2006.173.05:07:36.74#ibcon#about to read 6, iclass 11, count 0 2006.173.05:07:36.74#ibcon#read 6, iclass 11, count 0 2006.173.05:07:36.74#ibcon#end of sib2, iclass 11, count 0 2006.173.05:07:36.74#ibcon#*after write, iclass 11, count 0 2006.173.05:07:36.74#ibcon#*before return 0, iclass 11, count 0 2006.173.05:07:36.74#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.05:07:36.74#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.05:07:36.74#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.05:07:36.74#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.05:07:36.74$vck44/valo=8,884.99 2006.173.05:07:36.74#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.05:07:36.74#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.05:07:36.74#ibcon#ireg 17 cls_cnt 0 2006.173.05:07:36.74#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.05:07:36.74#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.05:07:36.74#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.05:07:36.74#ibcon#enter wrdev, iclass 13, count 0 2006.173.05:07:36.74#ibcon#first serial, iclass 13, count 0 2006.173.05:07:36.74#ibcon#enter sib2, iclass 13, count 0 2006.173.05:07:36.74#ibcon#flushed, iclass 13, count 0 2006.173.05:07:36.74#ibcon#about to write, iclass 13, count 0 2006.173.05:07:36.74#ibcon#wrote, iclass 13, count 0 2006.173.05:07:36.74#ibcon#about to read 3, iclass 13, count 0 2006.173.05:07:36.76#ibcon#read 3, iclass 13, count 0 2006.173.05:07:36.76#ibcon#about to read 4, iclass 13, count 0 2006.173.05:07:36.76#ibcon#read 4, iclass 13, count 0 2006.173.05:07:36.76#ibcon#about to read 5, iclass 13, count 0 2006.173.05:07:36.76#ibcon#read 5, iclass 13, count 0 2006.173.05:07:36.76#ibcon#about to read 6, iclass 13, count 0 2006.173.05:07:36.76#ibcon#read 6, iclass 13, count 0 2006.173.05:07:36.76#ibcon#end of sib2, iclass 13, count 0 2006.173.05:07:36.76#ibcon#*mode == 0, iclass 13, count 0 2006.173.05:07:36.76#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.05:07:36.76#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.05:07:36.76#ibcon#*before write, iclass 13, count 0 2006.173.05:07:36.76#ibcon#enter sib2, iclass 13, count 0 2006.173.05:07:36.76#ibcon#flushed, iclass 13, count 0 2006.173.05:07:36.76#ibcon#about to write, iclass 13, count 0 2006.173.05:07:36.76#ibcon#wrote, iclass 13, count 0 2006.173.05:07:36.76#ibcon#about to read 3, iclass 13, count 0 2006.173.05:07:36.80#ibcon#read 3, iclass 13, count 0 2006.173.05:07:36.80#ibcon#about to read 4, iclass 13, count 0 2006.173.05:07:36.80#ibcon#read 4, iclass 13, count 0 2006.173.05:07:36.80#ibcon#about to read 5, iclass 13, count 0 2006.173.05:07:36.80#ibcon#read 5, iclass 13, count 0 2006.173.05:07:36.80#ibcon#about to read 6, iclass 13, count 0 2006.173.05:07:36.80#ibcon#read 6, iclass 13, count 0 2006.173.05:07:36.80#ibcon#end of sib2, iclass 13, count 0 2006.173.05:07:36.80#ibcon#*after write, iclass 13, count 0 2006.173.05:07:36.80#ibcon#*before return 0, iclass 13, count 0 2006.173.05:07:36.80#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.05:07:36.80#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.05:07:36.80#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.05:07:36.80#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.05:07:36.80$vck44/va=8,4 2006.173.05:07:36.80#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.05:07:36.80#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.05:07:36.80#ibcon#ireg 11 cls_cnt 2 2006.173.05:07:36.80#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.05:07:36.86#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.05:07:36.86#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.05:07:36.86#ibcon#enter wrdev, iclass 15, count 2 2006.173.05:07:36.86#ibcon#first serial, iclass 15, count 2 2006.173.05:07:36.86#ibcon#enter sib2, iclass 15, count 2 2006.173.05:07:36.86#ibcon#flushed, iclass 15, count 2 2006.173.05:07:36.86#ibcon#about to write, iclass 15, count 2 2006.173.05:07:36.86#ibcon#wrote, iclass 15, count 2 2006.173.05:07:36.86#ibcon#about to read 3, iclass 15, count 2 2006.173.05:07:36.88#ibcon#read 3, iclass 15, count 2 2006.173.05:07:36.88#ibcon#about to read 4, iclass 15, count 2 2006.173.05:07:36.88#ibcon#read 4, iclass 15, count 2 2006.173.05:07:36.88#ibcon#about to read 5, iclass 15, count 2 2006.173.05:07:36.88#ibcon#read 5, iclass 15, count 2 2006.173.05:07:36.88#ibcon#about to read 6, iclass 15, count 2 2006.173.05:07:36.88#ibcon#read 6, iclass 15, count 2 2006.173.05:07:36.88#ibcon#end of sib2, iclass 15, count 2 2006.173.05:07:36.88#ibcon#*mode == 0, iclass 15, count 2 2006.173.05:07:36.88#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.05:07:36.88#ibcon#[25=AT08-04\r\n] 2006.173.05:07:36.88#ibcon#*before write, iclass 15, count 2 2006.173.05:07:36.88#ibcon#enter sib2, iclass 15, count 2 2006.173.05:07:36.88#ibcon#flushed, iclass 15, count 2 2006.173.05:07:36.88#ibcon#about to write, iclass 15, count 2 2006.173.05:07:36.88#ibcon#wrote, iclass 15, count 2 2006.173.05:07:36.88#ibcon#about to read 3, iclass 15, count 2 2006.173.05:07:36.91#ibcon#read 3, iclass 15, count 2 2006.173.05:07:36.91#ibcon#about to read 4, iclass 15, count 2 2006.173.05:07:36.91#ibcon#read 4, iclass 15, count 2 2006.173.05:07:36.91#ibcon#about to read 5, iclass 15, count 2 2006.173.05:07:36.91#ibcon#read 5, iclass 15, count 2 2006.173.05:07:36.91#ibcon#about to read 6, iclass 15, count 2 2006.173.05:07:36.91#ibcon#read 6, iclass 15, count 2 2006.173.05:07:36.91#ibcon#end of sib2, iclass 15, count 2 2006.173.05:07:36.91#ibcon#*after write, iclass 15, count 2 2006.173.05:07:36.91#ibcon#*before return 0, iclass 15, count 2 2006.173.05:07:36.91#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.05:07:36.91#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.05:07:36.91#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.05:07:36.91#ibcon#ireg 7 cls_cnt 0 2006.173.05:07:36.91#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.05:07:37.03#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.05:07:37.03#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.05:07:37.03#ibcon#enter wrdev, iclass 15, count 0 2006.173.05:07:37.03#ibcon#first serial, iclass 15, count 0 2006.173.05:07:37.03#ibcon#enter sib2, iclass 15, count 0 2006.173.05:07:37.03#ibcon#flushed, iclass 15, count 0 2006.173.05:07:37.03#ibcon#about to write, iclass 15, count 0 2006.173.05:07:37.03#ibcon#wrote, iclass 15, count 0 2006.173.05:07:37.03#ibcon#about to read 3, iclass 15, count 0 2006.173.05:07:37.05#ibcon#read 3, iclass 15, count 0 2006.173.05:07:37.05#ibcon#about to read 4, iclass 15, count 0 2006.173.05:07:37.05#ibcon#read 4, iclass 15, count 0 2006.173.05:07:37.05#ibcon#about to read 5, iclass 15, count 0 2006.173.05:07:37.05#ibcon#read 5, iclass 15, count 0 2006.173.05:07:37.05#ibcon#about to read 6, iclass 15, count 0 2006.173.05:07:37.05#ibcon#read 6, iclass 15, count 0 2006.173.05:07:37.05#ibcon#end of sib2, iclass 15, count 0 2006.173.05:07:37.05#ibcon#*mode == 0, iclass 15, count 0 2006.173.05:07:37.05#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.05:07:37.05#ibcon#[25=USB\r\n] 2006.173.05:07:37.05#ibcon#*before write, iclass 15, count 0 2006.173.05:07:37.05#ibcon#enter sib2, iclass 15, count 0 2006.173.05:07:37.05#ibcon#flushed, iclass 15, count 0 2006.173.05:07:37.05#ibcon#about to write, iclass 15, count 0 2006.173.05:07:37.05#ibcon#wrote, iclass 15, count 0 2006.173.05:07:37.05#ibcon#about to read 3, iclass 15, count 0 2006.173.05:07:37.08#ibcon#read 3, iclass 15, count 0 2006.173.05:07:37.08#ibcon#about to read 4, iclass 15, count 0 2006.173.05:07:37.08#ibcon#read 4, iclass 15, count 0 2006.173.05:07:37.08#ibcon#about to read 5, iclass 15, count 0 2006.173.05:07:37.08#ibcon#read 5, iclass 15, count 0 2006.173.05:07:37.08#ibcon#about to read 6, iclass 15, count 0 2006.173.05:07:37.08#ibcon#read 6, iclass 15, count 0 2006.173.05:07:37.08#ibcon#end of sib2, iclass 15, count 0 2006.173.05:07:37.08#ibcon#*after write, iclass 15, count 0 2006.173.05:07:37.08#ibcon#*before return 0, iclass 15, count 0 2006.173.05:07:37.08#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.05:07:37.08#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.05:07:37.08#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.05:07:37.08#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.05:07:37.08$vck44/vblo=1,629.99 2006.173.05:07:37.08#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.05:07:37.08#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.05:07:37.08#ibcon#ireg 17 cls_cnt 0 2006.173.05:07:37.08#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.05:07:37.08#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.05:07:37.08#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.05:07:37.08#ibcon#enter wrdev, iclass 17, count 0 2006.173.05:07:37.08#ibcon#first serial, iclass 17, count 0 2006.173.05:07:37.08#ibcon#enter sib2, iclass 17, count 0 2006.173.05:07:37.08#ibcon#flushed, iclass 17, count 0 2006.173.05:07:37.08#ibcon#about to write, iclass 17, count 0 2006.173.05:07:37.08#ibcon#wrote, iclass 17, count 0 2006.173.05:07:37.08#ibcon#about to read 3, iclass 17, count 0 2006.173.05:07:37.10#ibcon#read 3, iclass 17, count 0 2006.173.05:07:37.10#ibcon#about to read 4, iclass 17, count 0 2006.173.05:07:37.10#ibcon#read 4, iclass 17, count 0 2006.173.05:07:37.10#ibcon#about to read 5, iclass 17, count 0 2006.173.05:07:37.10#ibcon#read 5, iclass 17, count 0 2006.173.05:07:37.10#ibcon#about to read 6, iclass 17, count 0 2006.173.05:07:37.10#ibcon#read 6, iclass 17, count 0 2006.173.05:07:37.10#ibcon#end of sib2, iclass 17, count 0 2006.173.05:07:37.10#ibcon#*mode == 0, iclass 17, count 0 2006.173.05:07:37.10#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.05:07:37.10#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.05:07:37.10#ibcon#*before write, iclass 17, count 0 2006.173.05:07:37.10#ibcon#enter sib2, iclass 17, count 0 2006.173.05:07:37.10#ibcon#flushed, iclass 17, count 0 2006.173.05:07:37.10#ibcon#about to write, iclass 17, count 0 2006.173.05:07:37.10#ibcon#wrote, iclass 17, count 0 2006.173.05:07:37.10#ibcon#about to read 3, iclass 17, count 0 2006.173.05:07:37.14#ibcon#read 3, iclass 17, count 0 2006.173.05:07:37.14#ibcon#about to read 4, iclass 17, count 0 2006.173.05:07:37.14#ibcon#read 4, iclass 17, count 0 2006.173.05:07:37.14#ibcon#about to read 5, iclass 17, count 0 2006.173.05:07:37.14#ibcon#read 5, iclass 17, count 0 2006.173.05:07:37.14#ibcon#about to read 6, iclass 17, count 0 2006.173.05:07:37.14#ibcon#read 6, iclass 17, count 0 2006.173.05:07:37.14#ibcon#end of sib2, iclass 17, count 0 2006.173.05:07:37.14#ibcon#*after write, iclass 17, count 0 2006.173.05:07:37.14#ibcon#*before return 0, iclass 17, count 0 2006.173.05:07:37.14#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.05:07:37.14#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.05:07:37.14#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.05:07:37.14#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.05:07:37.14$vck44/vb=1,4 2006.173.05:07:37.14#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.05:07:37.14#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.05:07:37.14#ibcon#ireg 11 cls_cnt 2 2006.173.05:07:37.14#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.05:07:37.14#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.05:07:37.14#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.05:07:37.14#ibcon#enter wrdev, iclass 19, count 2 2006.173.05:07:37.14#ibcon#first serial, iclass 19, count 2 2006.173.05:07:37.14#ibcon#enter sib2, iclass 19, count 2 2006.173.05:07:37.14#ibcon#flushed, iclass 19, count 2 2006.173.05:07:37.14#ibcon#about to write, iclass 19, count 2 2006.173.05:07:37.14#ibcon#wrote, iclass 19, count 2 2006.173.05:07:37.14#ibcon#about to read 3, iclass 19, count 2 2006.173.05:07:37.16#ibcon#read 3, iclass 19, count 2 2006.173.05:07:37.16#ibcon#about to read 4, iclass 19, count 2 2006.173.05:07:37.16#ibcon#read 4, iclass 19, count 2 2006.173.05:07:37.16#ibcon#about to read 5, iclass 19, count 2 2006.173.05:07:37.16#ibcon#read 5, iclass 19, count 2 2006.173.05:07:37.16#ibcon#about to read 6, iclass 19, count 2 2006.173.05:07:37.16#ibcon#read 6, iclass 19, count 2 2006.173.05:07:37.16#ibcon#end of sib2, iclass 19, count 2 2006.173.05:07:37.16#ibcon#*mode == 0, iclass 19, count 2 2006.173.05:07:37.16#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.05:07:37.16#ibcon#[27=AT01-04\r\n] 2006.173.05:07:37.16#ibcon#*before write, iclass 19, count 2 2006.173.05:07:37.16#ibcon#enter sib2, iclass 19, count 2 2006.173.05:07:37.16#ibcon#flushed, iclass 19, count 2 2006.173.05:07:37.16#ibcon#about to write, iclass 19, count 2 2006.173.05:07:37.16#ibcon#wrote, iclass 19, count 2 2006.173.05:07:37.16#ibcon#about to read 3, iclass 19, count 2 2006.173.05:07:37.19#ibcon#read 3, iclass 19, count 2 2006.173.05:07:37.19#ibcon#about to read 4, iclass 19, count 2 2006.173.05:07:37.19#ibcon#read 4, iclass 19, count 2 2006.173.05:07:37.19#ibcon#about to read 5, iclass 19, count 2 2006.173.05:07:37.19#ibcon#read 5, iclass 19, count 2 2006.173.05:07:37.19#ibcon#about to read 6, iclass 19, count 2 2006.173.05:07:37.19#ibcon#read 6, iclass 19, count 2 2006.173.05:07:37.19#ibcon#end of sib2, iclass 19, count 2 2006.173.05:07:37.19#ibcon#*after write, iclass 19, count 2 2006.173.05:07:37.19#ibcon#*before return 0, iclass 19, count 2 2006.173.05:07:37.19#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.05:07:37.19#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.05:07:37.19#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.05:07:37.19#ibcon#ireg 7 cls_cnt 0 2006.173.05:07:37.19#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.05:07:37.31#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.05:07:37.31#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.05:07:37.31#ibcon#enter wrdev, iclass 19, count 0 2006.173.05:07:37.31#ibcon#first serial, iclass 19, count 0 2006.173.05:07:37.31#ibcon#enter sib2, iclass 19, count 0 2006.173.05:07:37.31#ibcon#flushed, iclass 19, count 0 2006.173.05:07:37.31#ibcon#about to write, iclass 19, count 0 2006.173.05:07:37.31#ibcon#wrote, iclass 19, count 0 2006.173.05:07:37.31#ibcon#about to read 3, iclass 19, count 0 2006.173.05:07:37.33#ibcon#read 3, iclass 19, count 0 2006.173.05:07:37.33#ibcon#about to read 4, iclass 19, count 0 2006.173.05:07:37.33#ibcon#read 4, iclass 19, count 0 2006.173.05:07:37.33#ibcon#about to read 5, iclass 19, count 0 2006.173.05:07:37.33#ibcon#read 5, iclass 19, count 0 2006.173.05:07:37.33#ibcon#about to read 6, iclass 19, count 0 2006.173.05:07:37.33#ibcon#read 6, iclass 19, count 0 2006.173.05:07:37.33#ibcon#end of sib2, iclass 19, count 0 2006.173.05:07:37.33#ibcon#*mode == 0, iclass 19, count 0 2006.173.05:07:37.33#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.05:07:37.33#ibcon#[27=USB\r\n] 2006.173.05:07:37.33#ibcon#*before write, iclass 19, count 0 2006.173.05:07:37.33#ibcon#enter sib2, iclass 19, count 0 2006.173.05:07:37.33#ibcon#flushed, iclass 19, count 0 2006.173.05:07:37.33#ibcon#about to write, iclass 19, count 0 2006.173.05:07:37.33#ibcon#wrote, iclass 19, count 0 2006.173.05:07:37.33#ibcon#about to read 3, iclass 19, count 0 2006.173.05:07:37.36#ibcon#read 3, iclass 19, count 0 2006.173.05:07:37.36#ibcon#about to read 4, iclass 19, count 0 2006.173.05:07:37.36#ibcon#read 4, iclass 19, count 0 2006.173.05:07:37.36#ibcon#about to read 5, iclass 19, count 0 2006.173.05:07:37.36#ibcon#read 5, iclass 19, count 0 2006.173.05:07:37.36#ibcon#about to read 6, iclass 19, count 0 2006.173.05:07:37.36#ibcon#read 6, iclass 19, count 0 2006.173.05:07:37.36#ibcon#end of sib2, iclass 19, count 0 2006.173.05:07:37.36#ibcon#*after write, iclass 19, count 0 2006.173.05:07:37.36#ibcon#*before return 0, iclass 19, count 0 2006.173.05:07:37.36#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.05:07:37.36#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.05:07:37.36#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.05:07:37.36#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.05:07:37.36$vck44/vblo=2,634.99 2006.173.05:07:37.36#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.05:07:37.36#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.05:07:37.36#ibcon#ireg 17 cls_cnt 0 2006.173.05:07:37.36#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.05:07:37.36#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.05:07:37.36#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.05:07:37.36#ibcon#enter wrdev, iclass 21, count 0 2006.173.05:07:37.36#ibcon#first serial, iclass 21, count 0 2006.173.05:07:37.36#ibcon#enter sib2, iclass 21, count 0 2006.173.05:07:37.36#ibcon#flushed, iclass 21, count 0 2006.173.05:07:37.36#ibcon#about to write, iclass 21, count 0 2006.173.05:07:37.36#ibcon#wrote, iclass 21, count 0 2006.173.05:07:37.36#ibcon#about to read 3, iclass 21, count 0 2006.173.05:07:37.38#ibcon#read 3, iclass 21, count 0 2006.173.05:07:37.38#ibcon#about to read 4, iclass 21, count 0 2006.173.05:07:37.38#ibcon#read 4, iclass 21, count 0 2006.173.05:07:37.38#ibcon#about to read 5, iclass 21, count 0 2006.173.05:07:37.38#ibcon#read 5, iclass 21, count 0 2006.173.05:07:37.38#ibcon#about to read 6, iclass 21, count 0 2006.173.05:07:37.38#ibcon#read 6, iclass 21, count 0 2006.173.05:07:37.38#ibcon#end of sib2, iclass 21, count 0 2006.173.05:07:37.38#ibcon#*mode == 0, iclass 21, count 0 2006.173.05:07:37.38#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.05:07:37.38#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.05:07:37.38#ibcon#*before write, iclass 21, count 0 2006.173.05:07:37.38#ibcon#enter sib2, iclass 21, count 0 2006.173.05:07:37.38#ibcon#flushed, iclass 21, count 0 2006.173.05:07:37.38#ibcon#about to write, iclass 21, count 0 2006.173.05:07:37.38#ibcon#wrote, iclass 21, count 0 2006.173.05:07:37.38#ibcon#about to read 3, iclass 21, count 0 2006.173.05:07:37.42#ibcon#read 3, iclass 21, count 0 2006.173.05:07:37.42#ibcon#about to read 4, iclass 21, count 0 2006.173.05:07:37.42#ibcon#read 4, iclass 21, count 0 2006.173.05:07:37.42#ibcon#about to read 5, iclass 21, count 0 2006.173.05:07:37.42#ibcon#read 5, iclass 21, count 0 2006.173.05:07:37.42#ibcon#about to read 6, iclass 21, count 0 2006.173.05:07:37.42#ibcon#read 6, iclass 21, count 0 2006.173.05:07:37.42#ibcon#end of sib2, iclass 21, count 0 2006.173.05:07:37.42#ibcon#*after write, iclass 21, count 0 2006.173.05:07:37.42#ibcon#*before return 0, iclass 21, count 0 2006.173.05:07:37.42#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.05:07:37.42#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.05:07:37.42#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.05:07:37.42#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.05:07:37.42$vck44/vb=2,4 2006.173.05:07:37.42#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.05:07:37.42#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.05:07:37.42#ibcon#ireg 11 cls_cnt 2 2006.173.05:07:37.42#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.05:07:37.48#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.05:07:37.48#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.05:07:37.48#ibcon#enter wrdev, iclass 23, count 2 2006.173.05:07:37.48#ibcon#first serial, iclass 23, count 2 2006.173.05:07:37.48#ibcon#enter sib2, iclass 23, count 2 2006.173.05:07:37.48#ibcon#flushed, iclass 23, count 2 2006.173.05:07:37.48#ibcon#about to write, iclass 23, count 2 2006.173.05:07:37.48#ibcon#wrote, iclass 23, count 2 2006.173.05:07:37.48#ibcon#about to read 3, iclass 23, count 2 2006.173.05:07:37.50#ibcon#read 3, iclass 23, count 2 2006.173.05:07:37.50#ibcon#about to read 4, iclass 23, count 2 2006.173.05:07:37.50#ibcon#read 4, iclass 23, count 2 2006.173.05:07:37.50#ibcon#about to read 5, iclass 23, count 2 2006.173.05:07:37.50#ibcon#read 5, iclass 23, count 2 2006.173.05:07:37.50#ibcon#about to read 6, iclass 23, count 2 2006.173.05:07:37.50#ibcon#read 6, iclass 23, count 2 2006.173.05:07:37.50#ibcon#end of sib2, iclass 23, count 2 2006.173.05:07:37.50#ibcon#*mode == 0, iclass 23, count 2 2006.173.05:07:37.50#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.05:07:37.50#ibcon#[27=AT02-04\r\n] 2006.173.05:07:37.50#ibcon#*before write, iclass 23, count 2 2006.173.05:07:37.50#ibcon#enter sib2, iclass 23, count 2 2006.173.05:07:37.50#ibcon#flushed, iclass 23, count 2 2006.173.05:07:37.50#ibcon#about to write, iclass 23, count 2 2006.173.05:07:37.50#ibcon#wrote, iclass 23, count 2 2006.173.05:07:37.50#ibcon#about to read 3, iclass 23, count 2 2006.173.05:07:37.53#ibcon#read 3, iclass 23, count 2 2006.173.05:07:37.53#ibcon#about to read 4, iclass 23, count 2 2006.173.05:07:37.53#ibcon#read 4, iclass 23, count 2 2006.173.05:07:37.53#ibcon#about to read 5, iclass 23, count 2 2006.173.05:07:37.53#ibcon#read 5, iclass 23, count 2 2006.173.05:07:37.53#ibcon#about to read 6, iclass 23, count 2 2006.173.05:07:37.53#ibcon#read 6, iclass 23, count 2 2006.173.05:07:37.53#ibcon#end of sib2, iclass 23, count 2 2006.173.05:07:37.53#ibcon#*after write, iclass 23, count 2 2006.173.05:07:37.53#ibcon#*before return 0, iclass 23, count 2 2006.173.05:07:37.53#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.05:07:37.53#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.05:07:37.53#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.05:07:37.53#ibcon#ireg 7 cls_cnt 0 2006.173.05:07:37.53#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.05:07:37.65#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.05:07:37.65#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.05:07:37.65#ibcon#enter wrdev, iclass 23, count 0 2006.173.05:07:37.65#ibcon#first serial, iclass 23, count 0 2006.173.05:07:37.65#ibcon#enter sib2, iclass 23, count 0 2006.173.05:07:37.65#ibcon#flushed, iclass 23, count 0 2006.173.05:07:37.65#ibcon#about to write, iclass 23, count 0 2006.173.05:07:37.65#ibcon#wrote, iclass 23, count 0 2006.173.05:07:37.65#ibcon#about to read 3, iclass 23, count 0 2006.173.05:07:37.67#ibcon#read 3, iclass 23, count 0 2006.173.05:07:37.67#ibcon#about to read 4, iclass 23, count 0 2006.173.05:07:37.67#ibcon#read 4, iclass 23, count 0 2006.173.05:07:37.67#ibcon#about to read 5, iclass 23, count 0 2006.173.05:07:37.67#ibcon#read 5, iclass 23, count 0 2006.173.05:07:37.67#ibcon#about to read 6, iclass 23, count 0 2006.173.05:07:37.67#ibcon#read 6, iclass 23, count 0 2006.173.05:07:37.67#ibcon#end of sib2, iclass 23, count 0 2006.173.05:07:37.67#ibcon#*mode == 0, iclass 23, count 0 2006.173.05:07:37.67#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.05:07:37.67#ibcon#[27=USB\r\n] 2006.173.05:07:37.67#ibcon#*before write, iclass 23, count 0 2006.173.05:07:37.67#ibcon#enter sib2, iclass 23, count 0 2006.173.05:07:37.67#ibcon#flushed, iclass 23, count 0 2006.173.05:07:37.67#ibcon#about to write, iclass 23, count 0 2006.173.05:07:37.67#ibcon#wrote, iclass 23, count 0 2006.173.05:07:37.67#ibcon#about to read 3, iclass 23, count 0 2006.173.05:07:37.70#ibcon#read 3, iclass 23, count 0 2006.173.05:07:37.70#ibcon#about to read 4, iclass 23, count 0 2006.173.05:07:37.70#ibcon#read 4, iclass 23, count 0 2006.173.05:07:37.70#ibcon#about to read 5, iclass 23, count 0 2006.173.05:07:37.70#ibcon#read 5, iclass 23, count 0 2006.173.05:07:37.70#ibcon#about to read 6, iclass 23, count 0 2006.173.05:07:37.70#ibcon#read 6, iclass 23, count 0 2006.173.05:07:37.70#ibcon#end of sib2, iclass 23, count 0 2006.173.05:07:37.70#ibcon#*after write, iclass 23, count 0 2006.173.05:07:37.70#ibcon#*before return 0, iclass 23, count 0 2006.173.05:07:37.70#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.05:07:37.70#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.05:07:37.70#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.05:07:37.70#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.05:07:37.70$vck44/vblo=3,649.99 2006.173.05:07:37.70#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.05:07:37.70#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.05:07:37.70#ibcon#ireg 17 cls_cnt 0 2006.173.05:07:37.70#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.05:07:37.70#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.05:07:37.70#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.05:07:37.70#ibcon#enter wrdev, iclass 25, count 0 2006.173.05:07:37.70#ibcon#first serial, iclass 25, count 0 2006.173.05:07:37.70#ibcon#enter sib2, iclass 25, count 0 2006.173.05:07:37.70#ibcon#flushed, iclass 25, count 0 2006.173.05:07:37.70#ibcon#about to write, iclass 25, count 0 2006.173.05:07:37.70#ibcon#wrote, iclass 25, count 0 2006.173.05:07:37.70#ibcon#about to read 3, iclass 25, count 0 2006.173.05:07:37.72#ibcon#read 3, iclass 25, count 0 2006.173.05:07:37.72#ibcon#about to read 4, iclass 25, count 0 2006.173.05:07:37.72#ibcon#read 4, iclass 25, count 0 2006.173.05:07:37.72#ibcon#about to read 5, iclass 25, count 0 2006.173.05:07:37.72#ibcon#read 5, iclass 25, count 0 2006.173.05:07:37.72#ibcon#about to read 6, iclass 25, count 0 2006.173.05:07:37.72#ibcon#read 6, iclass 25, count 0 2006.173.05:07:37.72#ibcon#end of sib2, iclass 25, count 0 2006.173.05:07:37.72#ibcon#*mode == 0, iclass 25, count 0 2006.173.05:07:37.72#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.05:07:37.72#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.05:07:37.72#ibcon#*before write, iclass 25, count 0 2006.173.05:07:37.72#ibcon#enter sib2, iclass 25, count 0 2006.173.05:07:37.72#ibcon#flushed, iclass 25, count 0 2006.173.05:07:37.72#ibcon#about to write, iclass 25, count 0 2006.173.05:07:37.72#ibcon#wrote, iclass 25, count 0 2006.173.05:07:37.72#ibcon#about to read 3, iclass 25, count 0 2006.173.05:07:37.76#ibcon#read 3, iclass 25, count 0 2006.173.05:07:37.76#ibcon#about to read 4, iclass 25, count 0 2006.173.05:07:37.76#ibcon#read 4, iclass 25, count 0 2006.173.05:07:37.76#ibcon#about to read 5, iclass 25, count 0 2006.173.05:07:37.76#ibcon#read 5, iclass 25, count 0 2006.173.05:07:37.76#ibcon#about to read 6, iclass 25, count 0 2006.173.05:07:37.76#ibcon#read 6, iclass 25, count 0 2006.173.05:07:37.76#ibcon#end of sib2, iclass 25, count 0 2006.173.05:07:37.76#ibcon#*after write, iclass 25, count 0 2006.173.05:07:37.76#ibcon#*before return 0, iclass 25, count 0 2006.173.05:07:37.76#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.05:07:37.76#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.05:07:37.76#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.05:07:37.76#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.05:07:37.76$vck44/vb=3,4 2006.173.05:07:37.76#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.05:07:37.76#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.05:07:37.76#ibcon#ireg 11 cls_cnt 2 2006.173.05:07:37.76#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.05:07:37.82#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.05:07:37.82#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.05:07:37.82#ibcon#enter wrdev, iclass 27, count 2 2006.173.05:07:37.82#ibcon#first serial, iclass 27, count 2 2006.173.05:07:37.82#ibcon#enter sib2, iclass 27, count 2 2006.173.05:07:37.82#ibcon#flushed, iclass 27, count 2 2006.173.05:07:37.82#ibcon#about to write, iclass 27, count 2 2006.173.05:07:37.82#ibcon#wrote, iclass 27, count 2 2006.173.05:07:37.82#ibcon#about to read 3, iclass 27, count 2 2006.173.05:07:37.84#ibcon#read 3, iclass 27, count 2 2006.173.05:07:37.84#ibcon#about to read 4, iclass 27, count 2 2006.173.05:07:37.84#ibcon#read 4, iclass 27, count 2 2006.173.05:07:37.84#ibcon#about to read 5, iclass 27, count 2 2006.173.05:07:37.84#ibcon#read 5, iclass 27, count 2 2006.173.05:07:37.84#ibcon#about to read 6, iclass 27, count 2 2006.173.05:07:37.84#ibcon#read 6, iclass 27, count 2 2006.173.05:07:37.84#ibcon#end of sib2, iclass 27, count 2 2006.173.05:07:37.84#ibcon#*mode == 0, iclass 27, count 2 2006.173.05:07:37.84#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.05:07:37.84#ibcon#[27=AT03-04\r\n] 2006.173.05:07:37.84#ibcon#*before write, iclass 27, count 2 2006.173.05:07:37.84#ibcon#enter sib2, iclass 27, count 2 2006.173.05:07:37.84#ibcon#flushed, iclass 27, count 2 2006.173.05:07:37.84#ibcon#about to write, iclass 27, count 2 2006.173.05:07:37.84#ibcon#wrote, iclass 27, count 2 2006.173.05:07:37.84#ibcon#about to read 3, iclass 27, count 2 2006.173.05:07:37.87#ibcon#read 3, iclass 27, count 2 2006.173.05:07:37.87#ibcon#about to read 4, iclass 27, count 2 2006.173.05:07:37.87#ibcon#read 4, iclass 27, count 2 2006.173.05:07:37.87#ibcon#about to read 5, iclass 27, count 2 2006.173.05:07:37.87#ibcon#read 5, iclass 27, count 2 2006.173.05:07:37.87#ibcon#about to read 6, iclass 27, count 2 2006.173.05:07:37.87#ibcon#read 6, iclass 27, count 2 2006.173.05:07:37.87#ibcon#end of sib2, iclass 27, count 2 2006.173.05:07:37.87#ibcon#*after write, iclass 27, count 2 2006.173.05:07:37.87#ibcon#*before return 0, iclass 27, count 2 2006.173.05:07:37.87#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.05:07:37.87#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.05:07:37.87#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.05:07:37.87#ibcon#ireg 7 cls_cnt 0 2006.173.05:07:37.87#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.05:07:37.99#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.05:07:37.99#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.05:07:37.99#ibcon#enter wrdev, iclass 27, count 0 2006.173.05:07:37.99#ibcon#first serial, iclass 27, count 0 2006.173.05:07:37.99#ibcon#enter sib2, iclass 27, count 0 2006.173.05:07:37.99#ibcon#flushed, iclass 27, count 0 2006.173.05:07:37.99#ibcon#about to write, iclass 27, count 0 2006.173.05:07:37.99#ibcon#wrote, iclass 27, count 0 2006.173.05:07:37.99#ibcon#about to read 3, iclass 27, count 0 2006.173.05:07:38.01#ibcon#read 3, iclass 27, count 0 2006.173.05:07:38.01#ibcon#about to read 4, iclass 27, count 0 2006.173.05:07:38.01#ibcon#read 4, iclass 27, count 0 2006.173.05:07:38.01#ibcon#about to read 5, iclass 27, count 0 2006.173.05:07:38.01#ibcon#read 5, iclass 27, count 0 2006.173.05:07:38.01#ibcon#about to read 6, iclass 27, count 0 2006.173.05:07:38.01#ibcon#read 6, iclass 27, count 0 2006.173.05:07:38.01#ibcon#end of sib2, iclass 27, count 0 2006.173.05:07:38.01#ibcon#*mode == 0, iclass 27, count 0 2006.173.05:07:38.01#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.05:07:38.01#ibcon#[27=USB\r\n] 2006.173.05:07:38.01#ibcon#*before write, iclass 27, count 0 2006.173.05:07:38.01#ibcon#enter sib2, iclass 27, count 0 2006.173.05:07:38.01#ibcon#flushed, iclass 27, count 0 2006.173.05:07:38.01#ibcon#about to write, iclass 27, count 0 2006.173.05:07:38.01#ibcon#wrote, iclass 27, count 0 2006.173.05:07:38.01#ibcon#about to read 3, iclass 27, count 0 2006.173.05:07:38.04#ibcon#read 3, iclass 27, count 0 2006.173.05:07:38.04#ibcon#about to read 4, iclass 27, count 0 2006.173.05:07:38.04#ibcon#read 4, iclass 27, count 0 2006.173.05:07:38.04#ibcon#about to read 5, iclass 27, count 0 2006.173.05:07:38.04#ibcon#read 5, iclass 27, count 0 2006.173.05:07:38.04#ibcon#about to read 6, iclass 27, count 0 2006.173.05:07:38.04#ibcon#read 6, iclass 27, count 0 2006.173.05:07:38.04#ibcon#end of sib2, iclass 27, count 0 2006.173.05:07:38.04#ibcon#*after write, iclass 27, count 0 2006.173.05:07:38.04#ibcon#*before return 0, iclass 27, count 0 2006.173.05:07:38.04#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.05:07:38.04#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.05:07:38.04#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.05:07:38.04#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.05:07:38.04$vck44/vblo=4,679.99 2006.173.05:07:38.04#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.05:07:38.04#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.05:07:38.04#ibcon#ireg 17 cls_cnt 0 2006.173.05:07:38.04#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.05:07:38.04#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.05:07:38.04#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.05:07:38.04#ibcon#enter wrdev, iclass 29, count 0 2006.173.05:07:38.04#ibcon#first serial, iclass 29, count 0 2006.173.05:07:38.04#ibcon#enter sib2, iclass 29, count 0 2006.173.05:07:38.04#ibcon#flushed, iclass 29, count 0 2006.173.05:07:38.04#ibcon#about to write, iclass 29, count 0 2006.173.05:07:38.04#ibcon#wrote, iclass 29, count 0 2006.173.05:07:38.04#ibcon#about to read 3, iclass 29, count 0 2006.173.05:07:38.06#ibcon#read 3, iclass 29, count 0 2006.173.05:07:38.06#ibcon#about to read 4, iclass 29, count 0 2006.173.05:07:38.06#ibcon#read 4, iclass 29, count 0 2006.173.05:07:38.06#ibcon#about to read 5, iclass 29, count 0 2006.173.05:07:38.06#ibcon#read 5, iclass 29, count 0 2006.173.05:07:38.06#ibcon#about to read 6, iclass 29, count 0 2006.173.05:07:38.06#ibcon#read 6, iclass 29, count 0 2006.173.05:07:38.06#ibcon#end of sib2, iclass 29, count 0 2006.173.05:07:38.06#ibcon#*mode == 0, iclass 29, count 0 2006.173.05:07:38.06#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.05:07:38.06#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.05:07:38.06#ibcon#*before write, iclass 29, count 0 2006.173.05:07:38.06#ibcon#enter sib2, iclass 29, count 0 2006.173.05:07:38.06#ibcon#flushed, iclass 29, count 0 2006.173.05:07:38.06#ibcon#about to write, iclass 29, count 0 2006.173.05:07:38.06#ibcon#wrote, iclass 29, count 0 2006.173.05:07:38.06#ibcon#about to read 3, iclass 29, count 0 2006.173.05:07:38.10#ibcon#read 3, iclass 29, count 0 2006.173.05:07:38.10#ibcon#about to read 4, iclass 29, count 0 2006.173.05:07:38.10#ibcon#read 4, iclass 29, count 0 2006.173.05:07:38.10#ibcon#about to read 5, iclass 29, count 0 2006.173.05:07:38.10#ibcon#read 5, iclass 29, count 0 2006.173.05:07:38.10#ibcon#about to read 6, iclass 29, count 0 2006.173.05:07:38.10#ibcon#read 6, iclass 29, count 0 2006.173.05:07:38.10#ibcon#end of sib2, iclass 29, count 0 2006.173.05:07:38.10#ibcon#*after write, iclass 29, count 0 2006.173.05:07:38.10#ibcon#*before return 0, iclass 29, count 0 2006.173.05:07:38.10#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.05:07:38.10#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.05:07:38.10#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.05:07:38.10#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.05:07:38.10$vck44/vb=4,4 2006.173.05:07:38.10#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.05:07:38.10#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.05:07:38.10#ibcon#ireg 11 cls_cnt 2 2006.173.05:07:38.10#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.05:07:38.16#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.05:07:38.16#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.05:07:38.16#ibcon#enter wrdev, iclass 31, count 2 2006.173.05:07:38.16#ibcon#first serial, iclass 31, count 2 2006.173.05:07:38.16#ibcon#enter sib2, iclass 31, count 2 2006.173.05:07:38.16#ibcon#flushed, iclass 31, count 2 2006.173.05:07:38.16#ibcon#about to write, iclass 31, count 2 2006.173.05:07:38.16#ibcon#wrote, iclass 31, count 2 2006.173.05:07:38.16#ibcon#about to read 3, iclass 31, count 2 2006.173.05:07:38.18#ibcon#read 3, iclass 31, count 2 2006.173.05:07:38.18#ibcon#about to read 4, iclass 31, count 2 2006.173.05:07:38.18#ibcon#read 4, iclass 31, count 2 2006.173.05:07:38.18#ibcon#about to read 5, iclass 31, count 2 2006.173.05:07:38.18#ibcon#read 5, iclass 31, count 2 2006.173.05:07:38.18#ibcon#about to read 6, iclass 31, count 2 2006.173.05:07:38.18#ibcon#read 6, iclass 31, count 2 2006.173.05:07:38.18#ibcon#end of sib2, iclass 31, count 2 2006.173.05:07:38.18#ibcon#*mode == 0, iclass 31, count 2 2006.173.05:07:38.18#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.05:07:38.18#ibcon#[27=AT04-04\r\n] 2006.173.05:07:38.18#ibcon#*before write, iclass 31, count 2 2006.173.05:07:38.18#ibcon#enter sib2, iclass 31, count 2 2006.173.05:07:38.18#ibcon#flushed, iclass 31, count 2 2006.173.05:07:38.18#ibcon#about to write, iclass 31, count 2 2006.173.05:07:38.18#ibcon#wrote, iclass 31, count 2 2006.173.05:07:38.18#ibcon#about to read 3, iclass 31, count 2 2006.173.05:07:38.21#ibcon#read 3, iclass 31, count 2 2006.173.05:07:38.21#ibcon#about to read 4, iclass 31, count 2 2006.173.05:07:38.21#ibcon#read 4, iclass 31, count 2 2006.173.05:07:38.21#ibcon#about to read 5, iclass 31, count 2 2006.173.05:07:38.21#ibcon#read 5, iclass 31, count 2 2006.173.05:07:38.21#ibcon#about to read 6, iclass 31, count 2 2006.173.05:07:38.21#ibcon#read 6, iclass 31, count 2 2006.173.05:07:38.21#ibcon#end of sib2, iclass 31, count 2 2006.173.05:07:38.21#ibcon#*after write, iclass 31, count 2 2006.173.05:07:38.21#ibcon#*before return 0, iclass 31, count 2 2006.173.05:07:38.21#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.05:07:38.21#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.05:07:38.21#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.05:07:38.21#ibcon#ireg 7 cls_cnt 0 2006.173.05:07:38.21#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.05:07:38.33#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.05:07:38.33#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.05:07:38.33#ibcon#enter wrdev, iclass 31, count 0 2006.173.05:07:38.33#ibcon#first serial, iclass 31, count 0 2006.173.05:07:38.33#ibcon#enter sib2, iclass 31, count 0 2006.173.05:07:38.33#ibcon#flushed, iclass 31, count 0 2006.173.05:07:38.33#ibcon#about to write, iclass 31, count 0 2006.173.05:07:38.33#ibcon#wrote, iclass 31, count 0 2006.173.05:07:38.33#ibcon#about to read 3, iclass 31, count 0 2006.173.05:07:38.35#ibcon#read 3, iclass 31, count 0 2006.173.05:07:38.35#ibcon#about to read 4, iclass 31, count 0 2006.173.05:07:38.35#ibcon#read 4, iclass 31, count 0 2006.173.05:07:38.35#ibcon#about to read 5, iclass 31, count 0 2006.173.05:07:38.35#ibcon#read 5, iclass 31, count 0 2006.173.05:07:38.35#ibcon#about to read 6, iclass 31, count 0 2006.173.05:07:38.35#ibcon#read 6, iclass 31, count 0 2006.173.05:07:38.35#ibcon#end of sib2, iclass 31, count 0 2006.173.05:07:38.35#ibcon#*mode == 0, iclass 31, count 0 2006.173.05:07:38.35#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.05:07:38.35#ibcon#[27=USB\r\n] 2006.173.05:07:38.35#ibcon#*before write, iclass 31, count 0 2006.173.05:07:38.35#ibcon#enter sib2, iclass 31, count 0 2006.173.05:07:38.35#ibcon#flushed, iclass 31, count 0 2006.173.05:07:38.35#ibcon#about to write, iclass 31, count 0 2006.173.05:07:38.35#ibcon#wrote, iclass 31, count 0 2006.173.05:07:38.35#ibcon#about to read 3, iclass 31, count 0 2006.173.05:07:38.38#ibcon#read 3, iclass 31, count 0 2006.173.05:07:38.38#ibcon#about to read 4, iclass 31, count 0 2006.173.05:07:38.38#ibcon#read 4, iclass 31, count 0 2006.173.05:07:38.38#ibcon#about to read 5, iclass 31, count 0 2006.173.05:07:38.38#ibcon#read 5, iclass 31, count 0 2006.173.05:07:38.38#ibcon#about to read 6, iclass 31, count 0 2006.173.05:07:38.38#ibcon#read 6, iclass 31, count 0 2006.173.05:07:38.38#ibcon#end of sib2, iclass 31, count 0 2006.173.05:07:38.38#ibcon#*after write, iclass 31, count 0 2006.173.05:07:38.38#ibcon#*before return 0, iclass 31, count 0 2006.173.05:07:38.38#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.05:07:38.38#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.05:07:38.38#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.05:07:38.38#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.05:07:38.38$vck44/vblo=5,709.99 2006.173.05:07:38.38#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.05:07:38.38#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.05:07:38.38#ibcon#ireg 17 cls_cnt 0 2006.173.05:07:38.38#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.05:07:38.38#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.05:07:38.38#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.05:07:38.38#ibcon#enter wrdev, iclass 33, count 0 2006.173.05:07:38.38#ibcon#first serial, iclass 33, count 0 2006.173.05:07:38.38#ibcon#enter sib2, iclass 33, count 0 2006.173.05:07:38.38#ibcon#flushed, iclass 33, count 0 2006.173.05:07:38.38#ibcon#about to write, iclass 33, count 0 2006.173.05:07:38.38#ibcon#wrote, iclass 33, count 0 2006.173.05:07:38.38#ibcon#about to read 3, iclass 33, count 0 2006.173.05:07:38.40#ibcon#read 3, iclass 33, count 0 2006.173.05:07:38.40#ibcon#about to read 4, iclass 33, count 0 2006.173.05:07:38.40#ibcon#read 4, iclass 33, count 0 2006.173.05:07:38.40#ibcon#about to read 5, iclass 33, count 0 2006.173.05:07:38.40#ibcon#read 5, iclass 33, count 0 2006.173.05:07:38.40#ibcon#about to read 6, iclass 33, count 0 2006.173.05:07:38.40#ibcon#read 6, iclass 33, count 0 2006.173.05:07:38.40#ibcon#end of sib2, iclass 33, count 0 2006.173.05:07:38.40#ibcon#*mode == 0, iclass 33, count 0 2006.173.05:07:38.40#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.05:07:38.40#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.05:07:38.40#ibcon#*before write, iclass 33, count 0 2006.173.05:07:38.40#ibcon#enter sib2, iclass 33, count 0 2006.173.05:07:38.40#ibcon#flushed, iclass 33, count 0 2006.173.05:07:38.40#ibcon#about to write, iclass 33, count 0 2006.173.05:07:38.40#ibcon#wrote, iclass 33, count 0 2006.173.05:07:38.40#ibcon#about to read 3, iclass 33, count 0 2006.173.05:07:38.44#ibcon#read 3, iclass 33, count 0 2006.173.05:07:38.44#ibcon#about to read 4, iclass 33, count 0 2006.173.05:07:38.44#ibcon#read 4, iclass 33, count 0 2006.173.05:07:38.44#ibcon#about to read 5, iclass 33, count 0 2006.173.05:07:38.44#ibcon#read 5, iclass 33, count 0 2006.173.05:07:38.44#ibcon#about to read 6, iclass 33, count 0 2006.173.05:07:38.44#ibcon#read 6, iclass 33, count 0 2006.173.05:07:38.44#ibcon#end of sib2, iclass 33, count 0 2006.173.05:07:38.44#ibcon#*after write, iclass 33, count 0 2006.173.05:07:38.44#ibcon#*before return 0, iclass 33, count 0 2006.173.05:07:38.44#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.05:07:38.44#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.05:07:38.44#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.05:07:38.44#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.05:07:38.44$vck44/vb=5,4 2006.173.05:07:38.44#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.05:07:38.44#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.05:07:38.44#ibcon#ireg 11 cls_cnt 2 2006.173.05:07:38.44#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.05:07:38.50#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.05:07:38.50#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.05:07:38.50#ibcon#enter wrdev, iclass 35, count 2 2006.173.05:07:38.50#ibcon#first serial, iclass 35, count 2 2006.173.05:07:38.50#ibcon#enter sib2, iclass 35, count 2 2006.173.05:07:38.50#ibcon#flushed, iclass 35, count 2 2006.173.05:07:38.50#ibcon#about to write, iclass 35, count 2 2006.173.05:07:38.50#ibcon#wrote, iclass 35, count 2 2006.173.05:07:38.50#ibcon#about to read 3, iclass 35, count 2 2006.173.05:07:38.52#ibcon#read 3, iclass 35, count 2 2006.173.05:07:38.52#ibcon#about to read 4, iclass 35, count 2 2006.173.05:07:38.52#ibcon#read 4, iclass 35, count 2 2006.173.05:07:38.52#ibcon#about to read 5, iclass 35, count 2 2006.173.05:07:38.52#ibcon#read 5, iclass 35, count 2 2006.173.05:07:38.52#ibcon#about to read 6, iclass 35, count 2 2006.173.05:07:38.52#ibcon#read 6, iclass 35, count 2 2006.173.05:07:38.52#ibcon#end of sib2, iclass 35, count 2 2006.173.05:07:38.52#ibcon#*mode == 0, iclass 35, count 2 2006.173.05:07:38.52#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.05:07:38.52#ibcon#[27=AT05-04\r\n] 2006.173.05:07:38.52#ibcon#*before write, iclass 35, count 2 2006.173.05:07:38.52#ibcon#enter sib2, iclass 35, count 2 2006.173.05:07:38.52#ibcon#flushed, iclass 35, count 2 2006.173.05:07:38.52#ibcon#about to write, iclass 35, count 2 2006.173.05:07:38.52#ibcon#wrote, iclass 35, count 2 2006.173.05:07:38.52#ibcon#about to read 3, iclass 35, count 2 2006.173.05:07:38.55#ibcon#read 3, iclass 35, count 2 2006.173.05:07:38.55#ibcon#about to read 4, iclass 35, count 2 2006.173.05:07:38.55#ibcon#read 4, iclass 35, count 2 2006.173.05:07:38.55#ibcon#about to read 5, iclass 35, count 2 2006.173.05:07:38.55#ibcon#read 5, iclass 35, count 2 2006.173.05:07:38.55#ibcon#about to read 6, iclass 35, count 2 2006.173.05:07:38.55#ibcon#read 6, iclass 35, count 2 2006.173.05:07:38.55#ibcon#end of sib2, iclass 35, count 2 2006.173.05:07:38.55#ibcon#*after write, iclass 35, count 2 2006.173.05:07:38.55#ibcon#*before return 0, iclass 35, count 2 2006.173.05:07:38.55#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.05:07:38.55#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.05:07:38.55#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.05:07:38.55#ibcon#ireg 7 cls_cnt 0 2006.173.05:07:38.55#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.05:07:38.67#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.05:07:38.67#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.05:07:38.67#ibcon#enter wrdev, iclass 35, count 0 2006.173.05:07:38.67#ibcon#first serial, iclass 35, count 0 2006.173.05:07:38.67#ibcon#enter sib2, iclass 35, count 0 2006.173.05:07:38.67#ibcon#flushed, iclass 35, count 0 2006.173.05:07:38.67#ibcon#about to write, iclass 35, count 0 2006.173.05:07:38.67#ibcon#wrote, iclass 35, count 0 2006.173.05:07:38.67#ibcon#about to read 3, iclass 35, count 0 2006.173.05:07:38.69#ibcon#read 3, iclass 35, count 0 2006.173.05:07:38.69#ibcon#about to read 4, iclass 35, count 0 2006.173.05:07:38.69#ibcon#read 4, iclass 35, count 0 2006.173.05:07:38.69#ibcon#about to read 5, iclass 35, count 0 2006.173.05:07:38.69#ibcon#read 5, iclass 35, count 0 2006.173.05:07:38.69#ibcon#about to read 6, iclass 35, count 0 2006.173.05:07:38.69#ibcon#read 6, iclass 35, count 0 2006.173.05:07:38.69#ibcon#end of sib2, iclass 35, count 0 2006.173.05:07:38.69#ibcon#*mode == 0, iclass 35, count 0 2006.173.05:07:38.69#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.05:07:38.69#ibcon#[27=USB\r\n] 2006.173.05:07:38.69#ibcon#*before write, iclass 35, count 0 2006.173.05:07:38.69#ibcon#enter sib2, iclass 35, count 0 2006.173.05:07:38.69#ibcon#flushed, iclass 35, count 0 2006.173.05:07:38.69#ibcon#about to write, iclass 35, count 0 2006.173.05:07:38.69#ibcon#wrote, iclass 35, count 0 2006.173.05:07:38.69#ibcon#about to read 3, iclass 35, count 0 2006.173.05:07:38.72#ibcon#read 3, iclass 35, count 0 2006.173.05:07:38.72#ibcon#about to read 4, iclass 35, count 0 2006.173.05:07:38.72#ibcon#read 4, iclass 35, count 0 2006.173.05:07:38.72#ibcon#about to read 5, iclass 35, count 0 2006.173.05:07:38.72#ibcon#read 5, iclass 35, count 0 2006.173.05:07:38.72#ibcon#about to read 6, iclass 35, count 0 2006.173.05:07:38.72#ibcon#read 6, iclass 35, count 0 2006.173.05:07:38.72#ibcon#end of sib2, iclass 35, count 0 2006.173.05:07:38.72#ibcon#*after write, iclass 35, count 0 2006.173.05:07:38.72#ibcon#*before return 0, iclass 35, count 0 2006.173.05:07:38.72#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.05:07:38.72#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.05:07:38.72#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.05:07:38.72#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.05:07:38.72$vck44/vblo=6,719.99 2006.173.05:07:38.72#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.05:07:38.72#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.05:07:38.72#ibcon#ireg 17 cls_cnt 0 2006.173.05:07:38.72#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.05:07:38.72#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.05:07:38.72#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.05:07:38.72#ibcon#enter wrdev, iclass 37, count 0 2006.173.05:07:38.72#ibcon#first serial, iclass 37, count 0 2006.173.05:07:38.72#ibcon#enter sib2, iclass 37, count 0 2006.173.05:07:38.72#ibcon#flushed, iclass 37, count 0 2006.173.05:07:38.72#ibcon#about to write, iclass 37, count 0 2006.173.05:07:38.72#ibcon#wrote, iclass 37, count 0 2006.173.05:07:38.72#ibcon#about to read 3, iclass 37, count 0 2006.173.05:07:38.74#ibcon#read 3, iclass 37, count 0 2006.173.05:07:38.74#ibcon#about to read 4, iclass 37, count 0 2006.173.05:07:38.74#ibcon#read 4, iclass 37, count 0 2006.173.05:07:38.74#ibcon#about to read 5, iclass 37, count 0 2006.173.05:07:38.74#ibcon#read 5, iclass 37, count 0 2006.173.05:07:38.74#ibcon#about to read 6, iclass 37, count 0 2006.173.05:07:38.74#ibcon#read 6, iclass 37, count 0 2006.173.05:07:38.74#ibcon#end of sib2, iclass 37, count 0 2006.173.05:07:38.74#ibcon#*mode == 0, iclass 37, count 0 2006.173.05:07:38.74#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.05:07:38.74#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.05:07:38.74#ibcon#*before write, iclass 37, count 0 2006.173.05:07:38.74#ibcon#enter sib2, iclass 37, count 0 2006.173.05:07:38.74#ibcon#flushed, iclass 37, count 0 2006.173.05:07:38.74#ibcon#about to write, iclass 37, count 0 2006.173.05:07:38.74#ibcon#wrote, iclass 37, count 0 2006.173.05:07:38.74#ibcon#about to read 3, iclass 37, count 0 2006.173.05:07:38.78#ibcon#read 3, iclass 37, count 0 2006.173.05:07:38.78#ibcon#about to read 4, iclass 37, count 0 2006.173.05:07:38.78#ibcon#read 4, iclass 37, count 0 2006.173.05:07:38.78#ibcon#about to read 5, iclass 37, count 0 2006.173.05:07:38.78#ibcon#read 5, iclass 37, count 0 2006.173.05:07:38.78#ibcon#about to read 6, iclass 37, count 0 2006.173.05:07:38.78#ibcon#read 6, iclass 37, count 0 2006.173.05:07:38.78#ibcon#end of sib2, iclass 37, count 0 2006.173.05:07:38.78#ibcon#*after write, iclass 37, count 0 2006.173.05:07:38.78#ibcon#*before return 0, iclass 37, count 0 2006.173.05:07:38.78#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.05:07:38.78#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.05:07:38.78#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.05:07:38.78#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.05:07:38.78$vck44/vb=6,4 2006.173.05:07:38.78#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.05:07:38.78#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.05:07:38.78#ibcon#ireg 11 cls_cnt 2 2006.173.05:07:38.78#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.05:07:38.84#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.05:07:38.84#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.05:07:38.84#ibcon#enter wrdev, iclass 39, count 2 2006.173.05:07:38.84#ibcon#first serial, iclass 39, count 2 2006.173.05:07:38.84#ibcon#enter sib2, iclass 39, count 2 2006.173.05:07:38.84#ibcon#flushed, iclass 39, count 2 2006.173.05:07:38.84#ibcon#about to write, iclass 39, count 2 2006.173.05:07:38.84#ibcon#wrote, iclass 39, count 2 2006.173.05:07:38.84#ibcon#about to read 3, iclass 39, count 2 2006.173.05:07:38.86#ibcon#read 3, iclass 39, count 2 2006.173.05:07:38.86#ibcon#about to read 4, iclass 39, count 2 2006.173.05:07:38.86#ibcon#read 4, iclass 39, count 2 2006.173.05:07:38.86#ibcon#about to read 5, iclass 39, count 2 2006.173.05:07:38.86#ibcon#read 5, iclass 39, count 2 2006.173.05:07:38.86#ibcon#about to read 6, iclass 39, count 2 2006.173.05:07:38.86#ibcon#read 6, iclass 39, count 2 2006.173.05:07:38.86#ibcon#end of sib2, iclass 39, count 2 2006.173.05:07:38.86#ibcon#*mode == 0, iclass 39, count 2 2006.173.05:07:38.86#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.05:07:38.86#ibcon#[27=AT06-04\r\n] 2006.173.05:07:38.86#ibcon#*before write, iclass 39, count 2 2006.173.05:07:38.86#ibcon#enter sib2, iclass 39, count 2 2006.173.05:07:38.86#ibcon#flushed, iclass 39, count 2 2006.173.05:07:38.86#ibcon#about to write, iclass 39, count 2 2006.173.05:07:38.86#ibcon#wrote, iclass 39, count 2 2006.173.05:07:38.86#ibcon#about to read 3, iclass 39, count 2 2006.173.05:07:38.89#ibcon#read 3, iclass 39, count 2 2006.173.05:07:38.89#ibcon#about to read 4, iclass 39, count 2 2006.173.05:07:38.89#ibcon#read 4, iclass 39, count 2 2006.173.05:07:38.89#ibcon#about to read 5, iclass 39, count 2 2006.173.05:07:38.89#ibcon#read 5, iclass 39, count 2 2006.173.05:07:38.89#ibcon#about to read 6, iclass 39, count 2 2006.173.05:07:38.89#ibcon#read 6, iclass 39, count 2 2006.173.05:07:38.89#ibcon#end of sib2, iclass 39, count 2 2006.173.05:07:38.89#ibcon#*after write, iclass 39, count 2 2006.173.05:07:38.89#ibcon#*before return 0, iclass 39, count 2 2006.173.05:07:38.89#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.05:07:38.89#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.05:07:38.89#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.05:07:38.89#ibcon#ireg 7 cls_cnt 0 2006.173.05:07:38.89#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.05:07:39.01#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.05:07:39.01#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.05:07:39.01#ibcon#enter wrdev, iclass 39, count 0 2006.173.05:07:39.01#ibcon#first serial, iclass 39, count 0 2006.173.05:07:39.01#ibcon#enter sib2, iclass 39, count 0 2006.173.05:07:39.01#ibcon#flushed, iclass 39, count 0 2006.173.05:07:39.01#ibcon#about to write, iclass 39, count 0 2006.173.05:07:39.01#ibcon#wrote, iclass 39, count 0 2006.173.05:07:39.01#ibcon#about to read 3, iclass 39, count 0 2006.173.05:07:39.03#ibcon#read 3, iclass 39, count 0 2006.173.05:07:39.03#ibcon#about to read 4, iclass 39, count 0 2006.173.05:07:39.03#ibcon#read 4, iclass 39, count 0 2006.173.05:07:39.03#ibcon#about to read 5, iclass 39, count 0 2006.173.05:07:39.03#ibcon#read 5, iclass 39, count 0 2006.173.05:07:39.03#ibcon#about to read 6, iclass 39, count 0 2006.173.05:07:39.03#ibcon#read 6, iclass 39, count 0 2006.173.05:07:39.03#ibcon#end of sib2, iclass 39, count 0 2006.173.05:07:39.03#ibcon#*mode == 0, iclass 39, count 0 2006.173.05:07:39.03#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.05:07:39.03#ibcon#[27=USB\r\n] 2006.173.05:07:39.03#ibcon#*before write, iclass 39, count 0 2006.173.05:07:39.03#ibcon#enter sib2, iclass 39, count 0 2006.173.05:07:39.03#ibcon#flushed, iclass 39, count 0 2006.173.05:07:39.03#ibcon#about to write, iclass 39, count 0 2006.173.05:07:39.03#ibcon#wrote, iclass 39, count 0 2006.173.05:07:39.03#ibcon#about to read 3, iclass 39, count 0 2006.173.05:07:39.06#ibcon#read 3, iclass 39, count 0 2006.173.05:07:39.06#ibcon#about to read 4, iclass 39, count 0 2006.173.05:07:39.06#ibcon#read 4, iclass 39, count 0 2006.173.05:07:39.06#ibcon#about to read 5, iclass 39, count 0 2006.173.05:07:39.06#ibcon#read 5, iclass 39, count 0 2006.173.05:07:39.06#ibcon#about to read 6, iclass 39, count 0 2006.173.05:07:39.06#ibcon#read 6, iclass 39, count 0 2006.173.05:07:39.06#ibcon#end of sib2, iclass 39, count 0 2006.173.05:07:39.06#ibcon#*after write, iclass 39, count 0 2006.173.05:07:39.06#ibcon#*before return 0, iclass 39, count 0 2006.173.05:07:39.06#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.05:07:39.06#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.05:07:39.06#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.05:07:39.06#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.05:07:39.06$vck44/vblo=7,734.99 2006.173.05:07:39.06#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.05:07:39.06#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.05:07:39.06#ibcon#ireg 17 cls_cnt 0 2006.173.05:07:39.06#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.05:07:39.06#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.05:07:39.06#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.05:07:39.06#ibcon#enter wrdev, iclass 3, count 0 2006.173.05:07:39.06#ibcon#first serial, iclass 3, count 0 2006.173.05:07:39.06#ibcon#enter sib2, iclass 3, count 0 2006.173.05:07:39.06#ibcon#flushed, iclass 3, count 0 2006.173.05:07:39.06#ibcon#about to write, iclass 3, count 0 2006.173.05:07:39.06#ibcon#wrote, iclass 3, count 0 2006.173.05:07:39.06#ibcon#about to read 3, iclass 3, count 0 2006.173.05:07:39.08#ibcon#read 3, iclass 3, count 0 2006.173.05:07:39.08#ibcon#about to read 4, iclass 3, count 0 2006.173.05:07:39.08#ibcon#read 4, iclass 3, count 0 2006.173.05:07:39.08#ibcon#about to read 5, iclass 3, count 0 2006.173.05:07:39.08#ibcon#read 5, iclass 3, count 0 2006.173.05:07:39.08#ibcon#about to read 6, iclass 3, count 0 2006.173.05:07:39.08#ibcon#read 6, iclass 3, count 0 2006.173.05:07:39.08#ibcon#end of sib2, iclass 3, count 0 2006.173.05:07:39.08#ibcon#*mode == 0, iclass 3, count 0 2006.173.05:07:39.08#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.05:07:39.08#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.05:07:39.08#ibcon#*before write, iclass 3, count 0 2006.173.05:07:39.08#ibcon#enter sib2, iclass 3, count 0 2006.173.05:07:39.08#ibcon#flushed, iclass 3, count 0 2006.173.05:07:39.08#ibcon#about to write, iclass 3, count 0 2006.173.05:07:39.08#ibcon#wrote, iclass 3, count 0 2006.173.05:07:39.08#ibcon#about to read 3, iclass 3, count 0 2006.173.05:07:39.12#ibcon#read 3, iclass 3, count 0 2006.173.05:07:39.12#ibcon#about to read 4, iclass 3, count 0 2006.173.05:07:39.12#ibcon#read 4, iclass 3, count 0 2006.173.05:07:39.12#ibcon#about to read 5, iclass 3, count 0 2006.173.05:07:39.12#ibcon#read 5, iclass 3, count 0 2006.173.05:07:39.12#ibcon#about to read 6, iclass 3, count 0 2006.173.05:07:39.12#ibcon#read 6, iclass 3, count 0 2006.173.05:07:39.12#ibcon#end of sib2, iclass 3, count 0 2006.173.05:07:39.12#ibcon#*after write, iclass 3, count 0 2006.173.05:07:39.12#ibcon#*before return 0, iclass 3, count 0 2006.173.05:07:39.12#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.05:07:39.12#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.05:07:39.12#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.05:07:39.12#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.05:07:39.12$vck44/vb=7,4 2006.173.05:07:39.12#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.05:07:39.12#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.05:07:39.12#ibcon#ireg 11 cls_cnt 2 2006.173.05:07:39.12#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.05:07:39.18#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.05:07:39.18#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.05:07:39.18#ibcon#enter wrdev, iclass 5, count 2 2006.173.05:07:39.18#ibcon#first serial, iclass 5, count 2 2006.173.05:07:39.18#ibcon#enter sib2, iclass 5, count 2 2006.173.05:07:39.18#ibcon#flushed, iclass 5, count 2 2006.173.05:07:39.18#ibcon#about to write, iclass 5, count 2 2006.173.05:07:39.18#ibcon#wrote, iclass 5, count 2 2006.173.05:07:39.18#ibcon#about to read 3, iclass 5, count 2 2006.173.05:07:39.20#ibcon#read 3, iclass 5, count 2 2006.173.05:07:39.20#ibcon#about to read 4, iclass 5, count 2 2006.173.05:07:39.20#ibcon#read 4, iclass 5, count 2 2006.173.05:07:39.20#ibcon#about to read 5, iclass 5, count 2 2006.173.05:07:39.20#ibcon#read 5, iclass 5, count 2 2006.173.05:07:39.20#ibcon#about to read 6, iclass 5, count 2 2006.173.05:07:39.20#ibcon#read 6, iclass 5, count 2 2006.173.05:07:39.20#ibcon#end of sib2, iclass 5, count 2 2006.173.05:07:39.20#ibcon#*mode == 0, iclass 5, count 2 2006.173.05:07:39.20#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.05:07:39.20#ibcon#[27=AT07-04\r\n] 2006.173.05:07:39.20#ibcon#*before write, iclass 5, count 2 2006.173.05:07:39.20#ibcon#enter sib2, iclass 5, count 2 2006.173.05:07:39.20#ibcon#flushed, iclass 5, count 2 2006.173.05:07:39.20#ibcon#about to write, iclass 5, count 2 2006.173.05:07:39.20#ibcon#wrote, iclass 5, count 2 2006.173.05:07:39.20#ibcon#about to read 3, iclass 5, count 2 2006.173.05:07:39.23#ibcon#read 3, iclass 5, count 2 2006.173.05:07:39.23#ibcon#about to read 4, iclass 5, count 2 2006.173.05:07:39.23#ibcon#read 4, iclass 5, count 2 2006.173.05:07:39.23#ibcon#about to read 5, iclass 5, count 2 2006.173.05:07:39.23#ibcon#read 5, iclass 5, count 2 2006.173.05:07:39.23#ibcon#about to read 6, iclass 5, count 2 2006.173.05:07:39.23#ibcon#read 6, iclass 5, count 2 2006.173.05:07:39.23#ibcon#end of sib2, iclass 5, count 2 2006.173.05:07:39.23#ibcon#*after write, iclass 5, count 2 2006.173.05:07:39.23#ibcon#*before return 0, iclass 5, count 2 2006.173.05:07:39.23#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.05:07:39.23#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.05:07:39.23#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.05:07:39.23#ibcon#ireg 7 cls_cnt 0 2006.173.05:07:39.23#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.05:07:39.35#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.05:07:39.35#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.05:07:39.35#ibcon#enter wrdev, iclass 5, count 0 2006.173.05:07:39.35#ibcon#first serial, iclass 5, count 0 2006.173.05:07:39.35#ibcon#enter sib2, iclass 5, count 0 2006.173.05:07:39.35#ibcon#flushed, iclass 5, count 0 2006.173.05:07:39.35#ibcon#about to write, iclass 5, count 0 2006.173.05:07:39.35#ibcon#wrote, iclass 5, count 0 2006.173.05:07:39.35#ibcon#about to read 3, iclass 5, count 0 2006.173.05:07:39.37#ibcon#read 3, iclass 5, count 0 2006.173.05:07:39.37#ibcon#about to read 4, iclass 5, count 0 2006.173.05:07:39.37#ibcon#read 4, iclass 5, count 0 2006.173.05:07:39.37#ibcon#about to read 5, iclass 5, count 0 2006.173.05:07:39.37#ibcon#read 5, iclass 5, count 0 2006.173.05:07:39.37#ibcon#about to read 6, iclass 5, count 0 2006.173.05:07:39.37#ibcon#read 6, iclass 5, count 0 2006.173.05:07:39.37#ibcon#end of sib2, iclass 5, count 0 2006.173.05:07:39.37#ibcon#*mode == 0, iclass 5, count 0 2006.173.05:07:39.37#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.05:07:39.37#ibcon#[27=USB\r\n] 2006.173.05:07:39.37#ibcon#*before write, iclass 5, count 0 2006.173.05:07:39.37#ibcon#enter sib2, iclass 5, count 0 2006.173.05:07:39.37#ibcon#flushed, iclass 5, count 0 2006.173.05:07:39.37#ibcon#about to write, iclass 5, count 0 2006.173.05:07:39.37#ibcon#wrote, iclass 5, count 0 2006.173.05:07:39.37#ibcon#about to read 3, iclass 5, count 0 2006.173.05:07:39.40#ibcon#read 3, iclass 5, count 0 2006.173.05:07:39.40#ibcon#about to read 4, iclass 5, count 0 2006.173.05:07:39.40#ibcon#read 4, iclass 5, count 0 2006.173.05:07:39.40#ibcon#about to read 5, iclass 5, count 0 2006.173.05:07:39.40#ibcon#read 5, iclass 5, count 0 2006.173.05:07:39.40#ibcon#about to read 6, iclass 5, count 0 2006.173.05:07:39.40#ibcon#read 6, iclass 5, count 0 2006.173.05:07:39.40#ibcon#end of sib2, iclass 5, count 0 2006.173.05:07:39.40#ibcon#*after write, iclass 5, count 0 2006.173.05:07:39.40#ibcon#*before return 0, iclass 5, count 0 2006.173.05:07:39.40#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.05:07:39.40#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.05:07:39.40#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.05:07:39.40#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.05:07:39.40$vck44/vblo=8,744.99 2006.173.05:07:39.40#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.05:07:39.40#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.05:07:39.40#ibcon#ireg 17 cls_cnt 0 2006.173.05:07:39.40#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.05:07:39.40#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.05:07:39.40#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.05:07:39.40#ibcon#enter wrdev, iclass 7, count 0 2006.173.05:07:39.40#ibcon#first serial, iclass 7, count 0 2006.173.05:07:39.40#ibcon#enter sib2, iclass 7, count 0 2006.173.05:07:39.40#ibcon#flushed, iclass 7, count 0 2006.173.05:07:39.40#ibcon#about to write, iclass 7, count 0 2006.173.05:07:39.40#ibcon#wrote, iclass 7, count 0 2006.173.05:07:39.40#ibcon#about to read 3, iclass 7, count 0 2006.173.05:07:39.42#ibcon#read 3, iclass 7, count 0 2006.173.05:07:39.42#ibcon#about to read 4, iclass 7, count 0 2006.173.05:07:39.42#ibcon#read 4, iclass 7, count 0 2006.173.05:07:39.42#ibcon#about to read 5, iclass 7, count 0 2006.173.05:07:39.42#ibcon#read 5, iclass 7, count 0 2006.173.05:07:39.42#ibcon#about to read 6, iclass 7, count 0 2006.173.05:07:39.42#ibcon#read 6, iclass 7, count 0 2006.173.05:07:39.42#ibcon#end of sib2, iclass 7, count 0 2006.173.05:07:39.42#ibcon#*mode == 0, iclass 7, count 0 2006.173.05:07:39.42#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.05:07:39.42#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.05:07:39.42#ibcon#*before write, iclass 7, count 0 2006.173.05:07:39.42#ibcon#enter sib2, iclass 7, count 0 2006.173.05:07:39.42#ibcon#flushed, iclass 7, count 0 2006.173.05:07:39.42#ibcon#about to write, iclass 7, count 0 2006.173.05:07:39.42#ibcon#wrote, iclass 7, count 0 2006.173.05:07:39.42#ibcon#about to read 3, iclass 7, count 0 2006.173.05:07:39.46#ibcon#read 3, iclass 7, count 0 2006.173.05:07:39.46#ibcon#about to read 4, iclass 7, count 0 2006.173.05:07:39.46#ibcon#read 4, iclass 7, count 0 2006.173.05:07:39.46#ibcon#about to read 5, iclass 7, count 0 2006.173.05:07:39.46#ibcon#read 5, iclass 7, count 0 2006.173.05:07:39.46#ibcon#about to read 6, iclass 7, count 0 2006.173.05:07:39.46#ibcon#read 6, iclass 7, count 0 2006.173.05:07:39.46#ibcon#end of sib2, iclass 7, count 0 2006.173.05:07:39.46#ibcon#*after write, iclass 7, count 0 2006.173.05:07:39.46#ibcon#*before return 0, iclass 7, count 0 2006.173.05:07:39.46#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.05:07:39.46#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.05:07:39.46#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.05:07:39.46#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.05:07:39.46$vck44/vb=8,4 2006.173.05:07:39.46#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.05:07:39.46#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.05:07:39.46#ibcon#ireg 11 cls_cnt 2 2006.173.05:07:39.46#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.05:07:39.52#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.05:07:39.52#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.05:07:39.52#ibcon#enter wrdev, iclass 11, count 2 2006.173.05:07:39.52#ibcon#first serial, iclass 11, count 2 2006.173.05:07:39.52#ibcon#enter sib2, iclass 11, count 2 2006.173.05:07:39.52#ibcon#flushed, iclass 11, count 2 2006.173.05:07:39.52#ibcon#about to write, iclass 11, count 2 2006.173.05:07:39.52#ibcon#wrote, iclass 11, count 2 2006.173.05:07:39.52#ibcon#about to read 3, iclass 11, count 2 2006.173.05:07:39.54#ibcon#read 3, iclass 11, count 2 2006.173.05:07:39.54#ibcon#about to read 4, iclass 11, count 2 2006.173.05:07:39.54#ibcon#read 4, iclass 11, count 2 2006.173.05:07:39.54#ibcon#about to read 5, iclass 11, count 2 2006.173.05:07:39.54#ibcon#read 5, iclass 11, count 2 2006.173.05:07:39.54#ibcon#about to read 6, iclass 11, count 2 2006.173.05:07:39.54#ibcon#read 6, iclass 11, count 2 2006.173.05:07:39.54#ibcon#end of sib2, iclass 11, count 2 2006.173.05:07:39.54#ibcon#*mode == 0, iclass 11, count 2 2006.173.05:07:39.54#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.05:07:39.54#ibcon#[27=AT08-04\r\n] 2006.173.05:07:39.54#ibcon#*before write, iclass 11, count 2 2006.173.05:07:39.54#ibcon#enter sib2, iclass 11, count 2 2006.173.05:07:39.54#ibcon#flushed, iclass 11, count 2 2006.173.05:07:39.54#ibcon#about to write, iclass 11, count 2 2006.173.05:07:39.54#ibcon#wrote, iclass 11, count 2 2006.173.05:07:39.54#ibcon#about to read 3, iclass 11, count 2 2006.173.05:07:39.57#ibcon#read 3, iclass 11, count 2 2006.173.05:07:39.57#ibcon#about to read 4, iclass 11, count 2 2006.173.05:07:39.57#ibcon#read 4, iclass 11, count 2 2006.173.05:07:39.57#ibcon#about to read 5, iclass 11, count 2 2006.173.05:07:39.57#ibcon#read 5, iclass 11, count 2 2006.173.05:07:39.57#ibcon#about to read 6, iclass 11, count 2 2006.173.05:07:39.57#ibcon#read 6, iclass 11, count 2 2006.173.05:07:39.57#ibcon#end of sib2, iclass 11, count 2 2006.173.05:07:39.57#ibcon#*after write, iclass 11, count 2 2006.173.05:07:39.57#ibcon#*before return 0, iclass 11, count 2 2006.173.05:07:39.57#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.05:07:39.57#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.05:07:39.57#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.05:07:39.57#ibcon#ireg 7 cls_cnt 0 2006.173.05:07:39.57#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.05:07:39.69#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.05:07:39.69#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.05:07:39.69#ibcon#enter wrdev, iclass 11, count 0 2006.173.05:07:39.69#ibcon#first serial, iclass 11, count 0 2006.173.05:07:39.69#ibcon#enter sib2, iclass 11, count 0 2006.173.05:07:39.69#ibcon#flushed, iclass 11, count 0 2006.173.05:07:39.69#ibcon#about to write, iclass 11, count 0 2006.173.05:07:39.69#ibcon#wrote, iclass 11, count 0 2006.173.05:07:39.69#ibcon#about to read 3, iclass 11, count 0 2006.173.05:07:39.71#ibcon#read 3, iclass 11, count 0 2006.173.05:07:39.71#ibcon#about to read 4, iclass 11, count 0 2006.173.05:07:39.71#ibcon#read 4, iclass 11, count 0 2006.173.05:07:39.71#ibcon#about to read 5, iclass 11, count 0 2006.173.05:07:39.71#ibcon#read 5, iclass 11, count 0 2006.173.05:07:39.71#ibcon#about to read 6, iclass 11, count 0 2006.173.05:07:39.71#ibcon#read 6, iclass 11, count 0 2006.173.05:07:39.71#ibcon#end of sib2, iclass 11, count 0 2006.173.05:07:39.71#ibcon#*mode == 0, iclass 11, count 0 2006.173.05:07:39.71#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.05:07:39.71#ibcon#[27=USB\r\n] 2006.173.05:07:39.71#ibcon#*before write, iclass 11, count 0 2006.173.05:07:39.71#ibcon#enter sib2, iclass 11, count 0 2006.173.05:07:39.71#ibcon#flushed, iclass 11, count 0 2006.173.05:07:39.71#ibcon#about to write, iclass 11, count 0 2006.173.05:07:39.71#ibcon#wrote, iclass 11, count 0 2006.173.05:07:39.71#ibcon#about to read 3, iclass 11, count 0 2006.173.05:07:39.74#ibcon#read 3, iclass 11, count 0 2006.173.05:07:39.74#ibcon#about to read 4, iclass 11, count 0 2006.173.05:07:39.74#ibcon#read 4, iclass 11, count 0 2006.173.05:07:39.74#ibcon#about to read 5, iclass 11, count 0 2006.173.05:07:39.74#ibcon#read 5, iclass 11, count 0 2006.173.05:07:39.74#ibcon#about to read 6, iclass 11, count 0 2006.173.05:07:39.74#ibcon#read 6, iclass 11, count 0 2006.173.05:07:39.74#ibcon#end of sib2, iclass 11, count 0 2006.173.05:07:39.74#ibcon#*after write, iclass 11, count 0 2006.173.05:07:39.74#ibcon#*before return 0, iclass 11, count 0 2006.173.05:07:39.74#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.05:07:39.74#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.05:07:39.74#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.05:07:39.74#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.05:07:39.74$vck44/vabw=wide 2006.173.05:07:39.74#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.05:07:39.74#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.05:07:39.74#ibcon#ireg 8 cls_cnt 0 2006.173.05:07:39.74#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.05:07:39.74#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.05:07:39.74#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.05:07:39.74#ibcon#enter wrdev, iclass 13, count 0 2006.173.05:07:39.74#ibcon#first serial, iclass 13, count 0 2006.173.05:07:39.74#ibcon#enter sib2, iclass 13, count 0 2006.173.05:07:39.74#ibcon#flushed, iclass 13, count 0 2006.173.05:07:39.74#ibcon#about to write, iclass 13, count 0 2006.173.05:07:39.74#ibcon#wrote, iclass 13, count 0 2006.173.05:07:39.74#ibcon#about to read 3, iclass 13, count 0 2006.173.05:07:39.76#ibcon#read 3, iclass 13, count 0 2006.173.05:07:39.76#ibcon#about to read 4, iclass 13, count 0 2006.173.05:07:39.76#ibcon#read 4, iclass 13, count 0 2006.173.05:07:39.76#ibcon#about to read 5, iclass 13, count 0 2006.173.05:07:39.76#ibcon#read 5, iclass 13, count 0 2006.173.05:07:39.76#ibcon#about to read 6, iclass 13, count 0 2006.173.05:07:39.76#ibcon#read 6, iclass 13, count 0 2006.173.05:07:39.76#ibcon#end of sib2, iclass 13, count 0 2006.173.05:07:39.76#ibcon#*mode == 0, iclass 13, count 0 2006.173.05:07:39.76#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.05:07:39.76#ibcon#[25=BW32\r\n] 2006.173.05:07:39.76#ibcon#*before write, iclass 13, count 0 2006.173.05:07:39.76#ibcon#enter sib2, iclass 13, count 0 2006.173.05:07:39.76#ibcon#flushed, iclass 13, count 0 2006.173.05:07:39.76#ibcon#about to write, iclass 13, count 0 2006.173.05:07:39.76#ibcon#wrote, iclass 13, count 0 2006.173.05:07:39.76#ibcon#about to read 3, iclass 13, count 0 2006.173.05:07:39.79#ibcon#read 3, iclass 13, count 0 2006.173.05:07:39.79#ibcon#about to read 4, iclass 13, count 0 2006.173.05:07:39.79#ibcon#read 4, iclass 13, count 0 2006.173.05:07:39.79#ibcon#about to read 5, iclass 13, count 0 2006.173.05:07:39.79#ibcon#read 5, iclass 13, count 0 2006.173.05:07:39.79#ibcon#about to read 6, iclass 13, count 0 2006.173.05:07:39.79#ibcon#read 6, iclass 13, count 0 2006.173.05:07:39.79#ibcon#end of sib2, iclass 13, count 0 2006.173.05:07:39.79#ibcon#*after write, iclass 13, count 0 2006.173.05:07:39.79#ibcon#*before return 0, iclass 13, count 0 2006.173.05:07:39.79#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.05:07:39.79#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.05:07:39.79#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.05:07:39.79#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.05:07:39.79$vck44/vbbw=wide 2006.173.05:07:39.79#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.05:07:39.79#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.05:07:39.79#ibcon#ireg 8 cls_cnt 0 2006.173.05:07:39.79#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.05:07:39.86#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.05:07:39.86#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.05:07:39.86#ibcon#enter wrdev, iclass 15, count 0 2006.173.05:07:39.86#ibcon#first serial, iclass 15, count 0 2006.173.05:07:39.86#ibcon#enter sib2, iclass 15, count 0 2006.173.05:07:39.86#ibcon#flushed, iclass 15, count 0 2006.173.05:07:39.86#ibcon#about to write, iclass 15, count 0 2006.173.05:07:39.86#ibcon#wrote, iclass 15, count 0 2006.173.05:07:39.86#ibcon#about to read 3, iclass 15, count 0 2006.173.05:07:39.88#ibcon#read 3, iclass 15, count 0 2006.173.05:07:39.88#ibcon#about to read 4, iclass 15, count 0 2006.173.05:07:39.88#ibcon#read 4, iclass 15, count 0 2006.173.05:07:39.88#ibcon#about to read 5, iclass 15, count 0 2006.173.05:07:39.88#ibcon#read 5, iclass 15, count 0 2006.173.05:07:39.88#ibcon#about to read 6, iclass 15, count 0 2006.173.05:07:39.88#ibcon#read 6, iclass 15, count 0 2006.173.05:07:39.88#ibcon#end of sib2, iclass 15, count 0 2006.173.05:07:39.88#ibcon#*mode == 0, iclass 15, count 0 2006.173.05:07:39.88#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.05:07:39.88#ibcon#[27=BW32\r\n] 2006.173.05:07:39.88#ibcon#*before write, iclass 15, count 0 2006.173.05:07:39.88#ibcon#enter sib2, iclass 15, count 0 2006.173.05:07:39.88#ibcon#flushed, iclass 15, count 0 2006.173.05:07:39.88#ibcon#about to write, iclass 15, count 0 2006.173.05:07:39.88#ibcon#wrote, iclass 15, count 0 2006.173.05:07:39.88#ibcon#about to read 3, iclass 15, count 0 2006.173.05:07:39.91#ibcon#read 3, iclass 15, count 0 2006.173.05:07:39.91#ibcon#about to read 4, iclass 15, count 0 2006.173.05:07:39.91#ibcon#read 4, iclass 15, count 0 2006.173.05:07:39.91#ibcon#about to read 5, iclass 15, count 0 2006.173.05:07:39.91#ibcon#read 5, iclass 15, count 0 2006.173.05:07:39.91#ibcon#about to read 6, iclass 15, count 0 2006.173.05:07:39.91#ibcon#read 6, iclass 15, count 0 2006.173.05:07:39.91#ibcon#end of sib2, iclass 15, count 0 2006.173.05:07:39.91#ibcon#*after write, iclass 15, count 0 2006.173.05:07:39.91#ibcon#*before return 0, iclass 15, count 0 2006.173.05:07:39.91#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.05:07:39.91#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.05:07:39.91#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.05:07:39.91#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.05:07:39.91$setupk4/ifdk4 2006.173.05:07:39.91$ifdk4/lo= 2006.173.05:07:39.91$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.05:07:39.91$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.05:07:39.91$ifdk4/patch= 2006.173.05:07:39.91$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.05:07:39.91$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.05:07:39.91$setupk4/!*+20s 2006.173.05:07:41.24#abcon#<5=/16 1.1 2.0 23.49 791005.5\r\n> 2006.173.05:07:41.26#abcon#{5=INTERFACE CLEAR} 2006.173.05:07:41.32#abcon#[5=S1D000X0/0*\r\n] 2006.173.05:07:51.41#abcon#<5=/16 1.1 2.0 23.49 791005.5\r\n> 2006.173.05:07:51.43#abcon#{5=INTERFACE CLEAR} 2006.173.05:07:51.49#abcon#[5=S1D000X0/0*\r\n] 2006.173.05:07:54.41$setupk4/"tpicd 2006.173.05:07:54.41$setupk4/echo=off 2006.173.05:07:54.41$setupk4/xlog=off 2006.173.05:07:54.41:!2006.173.05:10:54 2006.173.05:08:44.14#trakl#Source acquired 2006.173.05:08:44.14#flagr#flagr/antenna,acquired 2006.173.05:10:54.00:preob 2006.173.05:10:54.14/onsource/TRACKING 2006.173.05:10:54.14:!2006.173.05:11:04 2006.173.05:11:04.00:"tape 2006.173.05:11:04.00:"st=record 2006.173.05:11:04.00:data_valid=on 2006.173.05:11:04.00:midob 2006.173.05:11:05.14/onsource/TRACKING 2006.173.05:11:05.14/wx/23.51,1005.6,79 2006.173.05:11:05.32/cable/+6.5083E-03 2006.173.05:11:06.41/va/01,07,usb,yes,39,42 2006.173.05:11:06.41/va/02,06,usb,yes,38,39 2006.173.05:11:06.41/va/03,05,usb,yes,49,51 2006.173.05:11:06.41/va/04,06,usb,yes,39,41 2006.173.05:11:06.41/va/05,04,usb,yes,31,31 2006.173.05:11:06.41/va/06,03,usb,yes,43,43 2006.173.05:11:06.41/va/07,04,usb,yes,35,36 2006.173.05:11:06.41/va/08,04,usb,yes,30,36 2006.173.05:11:06.64/valo/01,524.99,yes,locked 2006.173.05:11:06.64/valo/02,534.99,yes,locked 2006.173.05:11:06.64/valo/03,564.99,yes,locked 2006.173.05:11:06.64/valo/04,624.99,yes,locked 2006.173.05:11:06.64/valo/05,734.99,yes,locked 2006.173.05:11:06.64/valo/06,814.99,yes,locked 2006.173.05:11:06.64/valo/07,864.99,yes,locked 2006.173.05:11:06.64/valo/08,884.99,yes,locked 2006.173.05:11:07.73/vb/01,04,usb,yes,37,34 2006.173.05:11:07.73/vb/02,04,usb,yes,39,39 2006.173.05:11:07.73/vb/03,04,usb,yes,36,40 2006.173.05:11:07.73/vb/04,04,usb,yes,41,40 2006.173.05:11:07.73/vb/05,04,usb,yes,32,35 2006.173.05:11:07.73/vb/06,04,usb,yes,37,33 2006.173.05:11:07.73/vb/07,04,usb,yes,37,37 2006.173.05:11:07.73/vb/08,04,usb,yes,34,38 2006.173.05:11:07.96/vblo/01,629.99,yes,locked 2006.173.05:11:07.96/vblo/02,634.99,yes,locked 2006.173.05:11:07.96/vblo/03,649.99,yes,locked 2006.173.05:11:07.96/vblo/04,679.99,yes,locked 2006.173.05:11:07.96/vblo/05,709.99,yes,locked 2006.173.05:11:07.96/vblo/06,719.99,yes,locked 2006.173.05:11:07.96/vblo/07,734.99,yes,locked 2006.173.05:11:07.96/vblo/08,744.99,yes,locked 2006.173.05:11:08.11/vabw/8 2006.173.05:11:08.26/vbbw/8 2006.173.05:11:08.35/xfe/off,on,14.7 2006.173.05:11:08.73/ifatt/23,28,28,28 2006.173.05:11:09.08/fmout-gps/S +3.97E-07 2006.173.05:11:09.12:!2006.173.05:12:44 2006.173.05:12:44.00:data_valid=off 2006.173.05:12:44.00:"et 2006.173.05:12:44.00:!+3s 2006.173.05:12:47.02:"tape 2006.173.05:12:47.02:postob 2006.173.05:12:47.09/cable/+6.5050E-03 2006.173.05:12:47.09/wx/23.50,1005.6,78 2006.173.05:12:48.08/fmout-gps/S +3.96E-07 2006.173.05:12:48.08:scan_name=173-0517,jd0606,220 2006.173.05:12:48.08:source=1044+719,104827.62,714335.9,2000.0,cw 2006.173.05:12:49.13#flagr#flagr/antenna,new-source 2006.173.05:12:49.13:checkk5 2006.173.05:12:49.52/chk_autoobs//k5ts1/ autoobs is running! 2006.173.05:12:49.93/chk_autoobs//k5ts2/ autoobs is running! 2006.173.05:12:50.33/chk_autoobs//k5ts3/ autoobs is running! 2006.173.05:12:50.74/chk_autoobs//k5ts4/ autoobs is running! 2006.173.05:12:51.13/chk_obsdata//k5ts1/T1730511??a.dat file size is correct (nominal:400MB, actual:396MB). 2006.173.05:12:51.53/chk_obsdata//k5ts2/T1730511??b.dat file size is correct (nominal:400MB, actual:396MB). 2006.173.05:12:51.94/chk_obsdata//k5ts3/T1730511??c.dat file size is correct (nominal:400MB, actual:396MB). 2006.173.05:12:52.33/chk_obsdata//k5ts4/T1730511??d.dat file size is correct (nominal:400MB, actual:396MB). 2006.173.05:12:53.06/k5log//k5ts1_log_newline 2006.173.05:12:53.76/k5log//k5ts2_log_newline 2006.173.05:12:54.49/k5log//k5ts3_log_newline 2006.173.05:12:55.19/k5log//k5ts4_log_newline 2006.173.05:12:55.22/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.05:12:55.22:setupk4=1 2006.173.05:12:55.22$setupk4/echo=on 2006.173.05:12:55.22$setupk4/pcalon 2006.173.05:12:55.22$pcalon/"no phase cal control is implemented here 2006.173.05:12:55.22$setupk4/"tpicd=stop 2006.173.05:12:55.22$setupk4/"rec=synch_on 2006.173.05:12:55.22$setupk4/"rec_mode=128 2006.173.05:12:55.22$setupk4/!* 2006.173.05:12:55.22$setupk4/recpk4 2006.173.05:12:55.22$recpk4/recpatch= 2006.173.05:12:55.22$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.05:12:55.22$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.05:12:55.22$setupk4/vck44 2006.173.05:12:55.22$vck44/valo=1,524.99 2006.173.05:12:55.22#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.05:12:55.22#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.05:12:55.22#ibcon#ireg 17 cls_cnt 0 2006.173.05:12:55.22#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.05:12:55.22#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.05:12:55.22#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.05:12:55.22#ibcon#enter wrdev, iclass 36, count 0 2006.173.05:12:55.22#ibcon#first serial, iclass 36, count 0 2006.173.05:12:55.22#ibcon#enter sib2, iclass 36, count 0 2006.173.05:12:55.22#ibcon#flushed, iclass 36, count 0 2006.173.05:12:55.22#ibcon#about to write, iclass 36, count 0 2006.173.05:12:55.23#ibcon#wrote, iclass 36, count 0 2006.173.05:12:55.23#ibcon#about to read 3, iclass 36, count 0 2006.173.05:12:55.24#ibcon#read 3, iclass 36, count 0 2006.173.05:12:55.24#ibcon#about to read 4, iclass 36, count 0 2006.173.05:12:55.24#ibcon#read 4, iclass 36, count 0 2006.173.05:12:55.24#ibcon#about to read 5, iclass 36, count 0 2006.173.05:12:55.24#ibcon#read 5, iclass 36, count 0 2006.173.05:12:55.24#ibcon#about to read 6, iclass 36, count 0 2006.173.05:12:55.24#ibcon#read 6, iclass 36, count 0 2006.173.05:12:55.24#ibcon#end of sib2, iclass 36, count 0 2006.173.05:12:55.24#ibcon#*mode == 0, iclass 36, count 0 2006.173.05:12:55.24#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.05:12:55.24#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.05:12:55.24#ibcon#*before write, iclass 36, count 0 2006.173.05:12:55.24#ibcon#enter sib2, iclass 36, count 0 2006.173.05:12:55.24#ibcon#flushed, iclass 36, count 0 2006.173.05:12:55.24#ibcon#about to write, iclass 36, count 0 2006.173.05:12:55.24#ibcon#wrote, iclass 36, count 0 2006.173.05:12:55.24#ibcon#about to read 3, iclass 36, count 0 2006.173.05:12:55.29#ibcon#read 3, iclass 36, count 0 2006.173.05:12:55.29#ibcon#about to read 4, iclass 36, count 0 2006.173.05:12:55.29#ibcon#read 4, iclass 36, count 0 2006.173.05:12:55.29#ibcon#about to read 5, iclass 36, count 0 2006.173.05:12:55.29#ibcon#read 5, iclass 36, count 0 2006.173.05:12:55.29#ibcon#about to read 6, iclass 36, count 0 2006.173.05:12:55.29#ibcon#read 6, iclass 36, count 0 2006.173.05:12:55.29#ibcon#end of sib2, iclass 36, count 0 2006.173.05:12:55.29#ibcon#*after write, iclass 36, count 0 2006.173.05:12:55.29#ibcon#*before return 0, iclass 36, count 0 2006.173.05:12:55.29#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.05:12:55.29#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.05:12:55.29#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.05:12:55.29#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.05:12:55.29$vck44/va=1,7 2006.173.05:12:55.29#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.05:12:55.29#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.05:12:55.29#ibcon#ireg 11 cls_cnt 2 2006.173.05:12:55.29#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.05:12:55.29#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.05:12:55.29#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.05:12:55.29#ibcon#enter wrdev, iclass 38, count 2 2006.173.05:12:55.29#ibcon#first serial, iclass 38, count 2 2006.173.05:12:55.29#ibcon#enter sib2, iclass 38, count 2 2006.173.05:12:55.29#ibcon#flushed, iclass 38, count 2 2006.173.05:12:55.29#ibcon#about to write, iclass 38, count 2 2006.173.05:12:55.29#ibcon#wrote, iclass 38, count 2 2006.173.05:12:55.29#ibcon#about to read 3, iclass 38, count 2 2006.173.05:12:55.31#ibcon#read 3, iclass 38, count 2 2006.173.05:12:55.31#ibcon#about to read 4, iclass 38, count 2 2006.173.05:12:55.31#ibcon#read 4, iclass 38, count 2 2006.173.05:12:55.31#ibcon#about to read 5, iclass 38, count 2 2006.173.05:12:55.31#ibcon#read 5, iclass 38, count 2 2006.173.05:12:55.31#ibcon#about to read 6, iclass 38, count 2 2006.173.05:12:55.31#ibcon#read 6, iclass 38, count 2 2006.173.05:12:55.31#ibcon#end of sib2, iclass 38, count 2 2006.173.05:12:55.31#ibcon#*mode == 0, iclass 38, count 2 2006.173.05:12:55.31#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.05:12:55.31#ibcon#[25=AT01-07\r\n] 2006.173.05:12:55.31#ibcon#*before write, iclass 38, count 2 2006.173.05:12:55.31#ibcon#enter sib2, iclass 38, count 2 2006.173.05:12:55.31#ibcon#flushed, iclass 38, count 2 2006.173.05:12:55.31#ibcon#about to write, iclass 38, count 2 2006.173.05:12:55.31#ibcon#wrote, iclass 38, count 2 2006.173.05:12:55.31#ibcon#about to read 3, iclass 38, count 2 2006.173.05:12:55.34#ibcon#read 3, iclass 38, count 2 2006.173.05:12:55.34#ibcon#about to read 4, iclass 38, count 2 2006.173.05:12:55.34#ibcon#read 4, iclass 38, count 2 2006.173.05:12:55.34#ibcon#about to read 5, iclass 38, count 2 2006.173.05:12:55.34#ibcon#read 5, iclass 38, count 2 2006.173.05:12:55.34#ibcon#about to read 6, iclass 38, count 2 2006.173.05:12:55.34#ibcon#read 6, iclass 38, count 2 2006.173.05:12:55.34#ibcon#end of sib2, iclass 38, count 2 2006.173.05:12:55.34#ibcon#*after write, iclass 38, count 2 2006.173.05:12:55.34#ibcon#*before return 0, iclass 38, count 2 2006.173.05:12:55.34#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.05:12:55.34#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.05:12:55.34#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.05:12:55.34#ibcon#ireg 7 cls_cnt 0 2006.173.05:12:55.34#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.05:12:55.46#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.05:12:55.46#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.05:12:55.46#ibcon#enter wrdev, iclass 38, count 0 2006.173.05:12:55.46#ibcon#first serial, iclass 38, count 0 2006.173.05:12:55.46#ibcon#enter sib2, iclass 38, count 0 2006.173.05:12:55.46#ibcon#flushed, iclass 38, count 0 2006.173.05:12:55.46#ibcon#about to write, iclass 38, count 0 2006.173.05:12:55.46#ibcon#wrote, iclass 38, count 0 2006.173.05:12:55.46#ibcon#about to read 3, iclass 38, count 0 2006.173.05:12:55.48#ibcon#read 3, iclass 38, count 0 2006.173.05:12:55.48#ibcon#about to read 4, iclass 38, count 0 2006.173.05:12:55.48#ibcon#read 4, iclass 38, count 0 2006.173.05:12:55.48#ibcon#about to read 5, iclass 38, count 0 2006.173.05:12:55.48#ibcon#read 5, iclass 38, count 0 2006.173.05:12:55.48#ibcon#about to read 6, iclass 38, count 0 2006.173.05:12:55.48#ibcon#read 6, iclass 38, count 0 2006.173.05:12:55.48#ibcon#end of sib2, iclass 38, count 0 2006.173.05:12:55.48#ibcon#*mode == 0, iclass 38, count 0 2006.173.05:12:55.48#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.05:12:55.48#ibcon#[25=USB\r\n] 2006.173.05:12:55.48#ibcon#*before write, iclass 38, count 0 2006.173.05:12:55.48#ibcon#enter sib2, iclass 38, count 0 2006.173.05:12:55.48#ibcon#flushed, iclass 38, count 0 2006.173.05:12:55.48#ibcon#about to write, iclass 38, count 0 2006.173.05:12:55.48#ibcon#wrote, iclass 38, count 0 2006.173.05:12:55.48#ibcon#about to read 3, iclass 38, count 0 2006.173.05:12:55.51#ibcon#read 3, iclass 38, count 0 2006.173.05:12:55.51#ibcon#about to read 4, iclass 38, count 0 2006.173.05:12:55.51#ibcon#read 4, iclass 38, count 0 2006.173.05:12:55.51#ibcon#about to read 5, iclass 38, count 0 2006.173.05:12:55.51#ibcon#read 5, iclass 38, count 0 2006.173.05:12:55.51#ibcon#about to read 6, iclass 38, count 0 2006.173.05:12:55.51#ibcon#read 6, iclass 38, count 0 2006.173.05:12:55.51#ibcon#end of sib2, iclass 38, count 0 2006.173.05:12:55.51#ibcon#*after write, iclass 38, count 0 2006.173.05:12:55.51#ibcon#*before return 0, iclass 38, count 0 2006.173.05:12:55.51#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.05:12:55.51#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.05:12:55.51#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.05:12:55.51#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.05:12:55.51$vck44/valo=2,534.99 2006.173.05:12:55.51#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.05:12:55.51#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.05:12:55.51#ibcon#ireg 17 cls_cnt 0 2006.173.05:12:55.51#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.05:12:55.51#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.05:12:55.51#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.05:12:55.51#ibcon#enter wrdev, iclass 40, count 0 2006.173.05:12:55.51#ibcon#first serial, iclass 40, count 0 2006.173.05:12:55.51#ibcon#enter sib2, iclass 40, count 0 2006.173.05:12:55.51#ibcon#flushed, iclass 40, count 0 2006.173.05:12:55.51#ibcon#about to write, iclass 40, count 0 2006.173.05:12:55.51#ibcon#wrote, iclass 40, count 0 2006.173.05:12:55.51#ibcon#about to read 3, iclass 40, count 0 2006.173.05:12:55.53#ibcon#read 3, iclass 40, count 0 2006.173.05:12:55.53#ibcon#about to read 4, iclass 40, count 0 2006.173.05:12:55.53#ibcon#read 4, iclass 40, count 0 2006.173.05:12:55.53#ibcon#about to read 5, iclass 40, count 0 2006.173.05:12:55.53#ibcon#read 5, iclass 40, count 0 2006.173.05:12:55.53#ibcon#about to read 6, iclass 40, count 0 2006.173.05:12:55.53#ibcon#read 6, iclass 40, count 0 2006.173.05:12:55.53#ibcon#end of sib2, iclass 40, count 0 2006.173.05:12:55.53#ibcon#*mode == 0, iclass 40, count 0 2006.173.05:12:55.53#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.05:12:55.53#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.05:12:55.53#ibcon#*before write, iclass 40, count 0 2006.173.05:12:55.53#ibcon#enter sib2, iclass 40, count 0 2006.173.05:12:55.53#ibcon#flushed, iclass 40, count 0 2006.173.05:12:55.53#ibcon#about to write, iclass 40, count 0 2006.173.05:12:55.53#ibcon#wrote, iclass 40, count 0 2006.173.05:12:55.53#ibcon#about to read 3, iclass 40, count 0 2006.173.05:12:55.57#ibcon#read 3, iclass 40, count 0 2006.173.05:12:55.57#ibcon#about to read 4, iclass 40, count 0 2006.173.05:12:55.57#ibcon#read 4, iclass 40, count 0 2006.173.05:12:55.57#ibcon#about to read 5, iclass 40, count 0 2006.173.05:12:55.57#ibcon#read 5, iclass 40, count 0 2006.173.05:12:55.57#ibcon#about to read 6, iclass 40, count 0 2006.173.05:12:55.57#ibcon#read 6, iclass 40, count 0 2006.173.05:12:55.57#ibcon#end of sib2, iclass 40, count 0 2006.173.05:12:55.57#ibcon#*after write, iclass 40, count 0 2006.173.05:12:55.57#ibcon#*before return 0, iclass 40, count 0 2006.173.05:12:55.57#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.05:12:55.57#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.05:12:55.57#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.05:12:55.57#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.05:12:55.57$vck44/va=2,6 2006.173.05:12:55.57#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.05:12:55.57#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.05:12:55.57#ibcon#ireg 11 cls_cnt 2 2006.173.05:12:55.57#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.05:12:55.63#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.05:12:55.63#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.05:12:55.63#ibcon#enter wrdev, iclass 4, count 2 2006.173.05:12:55.63#ibcon#first serial, iclass 4, count 2 2006.173.05:12:55.63#ibcon#enter sib2, iclass 4, count 2 2006.173.05:12:55.63#ibcon#flushed, iclass 4, count 2 2006.173.05:12:55.63#ibcon#about to write, iclass 4, count 2 2006.173.05:12:55.63#ibcon#wrote, iclass 4, count 2 2006.173.05:12:55.63#ibcon#about to read 3, iclass 4, count 2 2006.173.05:12:55.65#ibcon#read 3, iclass 4, count 2 2006.173.05:12:55.65#ibcon#about to read 4, iclass 4, count 2 2006.173.05:12:55.65#ibcon#read 4, iclass 4, count 2 2006.173.05:12:55.65#ibcon#about to read 5, iclass 4, count 2 2006.173.05:12:55.65#ibcon#read 5, iclass 4, count 2 2006.173.05:12:55.65#ibcon#about to read 6, iclass 4, count 2 2006.173.05:12:55.65#ibcon#read 6, iclass 4, count 2 2006.173.05:12:55.65#ibcon#end of sib2, iclass 4, count 2 2006.173.05:12:55.65#ibcon#*mode == 0, iclass 4, count 2 2006.173.05:12:55.65#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.05:12:55.65#ibcon#[25=AT02-06\r\n] 2006.173.05:12:55.65#ibcon#*before write, iclass 4, count 2 2006.173.05:12:55.65#ibcon#enter sib2, iclass 4, count 2 2006.173.05:12:55.65#ibcon#flushed, iclass 4, count 2 2006.173.05:12:55.65#ibcon#about to write, iclass 4, count 2 2006.173.05:12:55.65#ibcon#wrote, iclass 4, count 2 2006.173.05:12:55.65#ibcon#about to read 3, iclass 4, count 2 2006.173.05:12:55.68#ibcon#read 3, iclass 4, count 2 2006.173.05:12:55.68#ibcon#about to read 4, iclass 4, count 2 2006.173.05:12:55.68#ibcon#read 4, iclass 4, count 2 2006.173.05:12:55.68#ibcon#about to read 5, iclass 4, count 2 2006.173.05:12:55.68#ibcon#read 5, iclass 4, count 2 2006.173.05:12:55.68#ibcon#about to read 6, iclass 4, count 2 2006.173.05:12:55.68#ibcon#read 6, iclass 4, count 2 2006.173.05:12:55.68#ibcon#end of sib2, iclass 4, count 2 2006.173.05:12:55.68#ibcon#*after write, iclass 4, count 2 2006.173.05:12:55.68#ibcon#*before return 0, iclass 4, count 2 2006.173.05:12:55.68#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.05:12:55.68#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.05:12:55.68#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.05:12:55.68#ibcon#ireg 7 cls_cnt 0 2006.173.05:12:55.68#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.05:12:55.80#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.05:12:55.80#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.05:12:55.80#ibcon#enter wrdev, iclass 4, count 0 2006.173.05:12:55.80#ibcon#first serial, iclass 4, count 0 2006.173.05:12:55.80#ibcon#enter sib2, iclass 4, count 0 2006.173.05:12:55.80#ibcon#flushed, iclass 4, count 0 2006.173.05:12:55.80#ibcon#about to write, iclass 4, count 0 2006.173.05:12:55.80#ibcon#wrote, iclass 4, count 0 2006.173.05:12:55.80#ibcon#about to read 3, iclass 4, count 0 2006.173.05:12:55.82#ibcon#read 3, iclass 4, count 0 2006.173.05:12:55.82#ibcon#about to read 4, iclass 4, count 0 2006.173.05:12:55.82#ibcon#read 4, iclass 4, count 0 2006.173.05:12:55.82#ibcon#about to read 5, iclass 4, count 0 2006.173.05:12:55.82#ibcon#read 5, iclass 4, count 0 2006.173.05:12:55.82#ibcon#about to read 6, iclass 4, count 0 2006.173.05:12:55.82#ibcon#read 6, iclass 4, count 0 2006.173.05:12:55.82#ibcon#end of sib2, iclass 4, count 0 2006.173.05:12:55.82#ibcon#*mode == 0, iclass 4, count 0 2006.173.05:12:55.82#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.05:12:55.82#ibcon#[25=USB\r\n] 2006.173.05:12:55.82#ibcon#*before write, iclass 4, count 0 2006.173.05:12:55.82#ibcon#enter sib2, iclass 4, count 0 2006.173.05:12:55.82#ibcon#flushed, iclass 4, count 0 2006.173.05:12:55.82#ibcon#about to write, iclass 4, count 0 2006.173.05:12:55.82#ibcon#wrote, iclass 4, count 0 2006.173.05:12:55.82#ibcon#about to read 3, iclass 4, count 0 2006.173.05:12:55.85#ibcon#read 3, iclass 4, count 0 2006.173.05:12:55.85#ibcon#about to read 4, iclass 4, count 0 2006.173.05:12:55.85#ibcon#read 4, iclass 4, count 0 2006.173.05:12:55.85#ibcon#about to read 5, iclass 4, count 0 2006.173.05:12:55.85#ibcon#read 5, iclass 4, count 0 2006.173.05:12:55.85#ibcon#about to read 6, iclass 4, count 0 2006.173.05:12:55.85#ibcon#read 6, iclass 4, count 0 2006.173.05:12:55.85#ibcon#end of sib2, iclass 4, count 0 2006.173.05:12:55.85#ibcon#*after write, iclass 4, count 0 2006.173.05:12:55.85#ibcon#*before return 0, iclass 4, count 0 2006.173.05:12:55.85#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.05:12:55.85#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.05:12:55.85#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.05:12:55.85#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.05:12:55.85$vck44/valo=3,564.99 2006.173.05:12:55.85#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.05:12:55.85#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.05:12:55.85#ibcon#ireg 17 cls_cnt 0 2006.173.05:12:55.85#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.05:12:55.85#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.05:12:55.85#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.05:12:55.85#ibcon#enter wrdev, iclass 6, count 0 2006.173.05:12:55.85#ibcon#first serial, iclass 6, count 0 2006.173.05:12:55.85#ibcon#enter sib2, iclass 6, count 0 2006.173.05:12:55.85#ibcon#flushed, iclass 6, count 0 2006.173.05:12:55.85#ibcon#about to write, iclass 6, count 0 2006.173.05:12:55.85#ibcon#wrote, iclass 6, count 0 2006.173.05:12:55.85#ibcon#about to read 3, iclass 6, count 0 2006.173.05:12:55.87#ibcon#read 3, iclass 6, count 0 2006.173.05:12:55.87#ibcon#about to read 4, iclass 6, count 0 2006.173.05:12:55.87#ibcon#read 4, iclass 6, count 0 2006.173.05:12:55.87#ibcon#about to read 5, iclass 6, count 0 2006.173.05:12:55.87#ibcon#read 5, iclass 6, count 0 2006.173.05:12:55.87#ibcon#about to read 6, iclass 6, count 0 2006.173.05:12:55.87#ibcon#read 6, iclass 6, count 0 2006.173.05:12:55.87#ibcon#end of sib2, iclass 6, count 0 2006.173.05:12:55.87#ibcon#*mode == 0, iclass 6, count 0 2006.173.05:12:55.87#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.05:12:55.87#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.05:12:55.87#ibcon#*before write, iclass 6, count 0 2006.173.05:12:55.87#ibcon#enter sib2, iclass 6, count 0 2006.173.05:12:55.87#ibcon#flushed, iclass 6, count 0 2006.173.05:12:55.87#ibcon#about to write, iclass 6, count 0 2006.173.05:12:55.87#ibcon#wrote, iclass 6, count 0 2006.173.05:12:55.87#ibcon#about to read 3, iclass 6, count 0 2006.173.05:12:55.91#ibcon#read 3, iclass 6, count 0 2006.173.05:12:55.91#ibcon#about to read 4, iclass 6, count 0 2006.173.05:12:55.91#ibcon#read 4, iclass 6, count 0 2006.173.05:12:55.91#ibcon#about to read 5, iclass 6, count 0 2006.173.05:12:55.91#ibcon#read 5, iclass 6, count 0 2006.173.05:12:55.91#ibcon#about to read 6, iclass 6, count 0 2006.173.05:12:55.91#ibcon#read 6, iclass 6, count 0 2006.173.05:12:55.91#ibcon#end of sib2, iclass 6, count 0 2006.173.05:12:55.91#ibcon#*after write, iclass 6, count 0 2006.173.05:12:55.91#ibcon#*before return 0, iclass 6, count 0 2006.173.05:12:55.91#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.05:12:55.91#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.05:12:55.91#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.05:12:55.91#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.05:12:55.91$vck44/va=3,5 2006.173.05:12:55.91#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.05:12:55.91#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.05:12:55.91#ibcon#ireg 11 cls_cnt 2 2006.173.05:12:55.91#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.05:12:55.97#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.05:12:55.97#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.05:12:55.97#ibcon#enter wrdev, iclass 10, count 2 2006.173.05:12:55.97#ibcon#first serial, iclass 10, count 2 2006.173.05:12:55.97#ibcon#enter sib2, iclass 10, count 2 2006.173.05:12:55.97#ibcon#flushed, iclass 10, count 2 2006.173.05:12:55.97#ibcon#about to write, iclass 10, count 2 2006.173.05:12:55.97#ibcon#wrote, iclass 10, count 2 2006.173.05:12:55.97#ibcon#about to read 3, iclass 10, count 2 2006.173.05:12:55.99#ibcon#read 3, iclass 10, count 2 2006.173.05:12:55.99#ibcon#about to read 4, iclass 10, count 2 2006.173.05:12:55.99#ibcon#read 4, iclass 10, count 2 2006.173.05:12:55.99#ibcon#about to read 5, iclass 10, count 2 2006.173.05:12:55.99#ibcon#read 5, iclass 10, count 2 2006.173.05:12:55.99#ibcon#about to read 6, iclass 10, count 2 2006.173.05:12:55.99#ibcon#read 6, iclass 10, count 2 2006.173.05:12:55.99#ibcon#end of sib2, iclass 10, count 2 2006.173.05:12:55.99#ibcon#*mode == 0, iclass 10, count 2 2006.173.05:12:55.99#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.05:12:55.99#ibcon#[25=AT03-05\r\n] 2006.173.05:12:55.99#ibcon#*before write, iclass 10, count 2 2006.173.05:12:55.99#ibcon#enter sib2, iclass 10, count 2 2006.173.05:12:55.99#ibcon#flushed, iclass 10, count 2 2006.173.05:12:55.99#ibcon#about to write, iclass 10, count 2 2006.173.05:12:55.99#ibcon#wrote, iclass 10, count 2 2006.173.05:12:55.99#ibcon#about to read 3, iclass 10, count 2 2006.173.05:12:56.02#ibcon#read 3, iclass 10, count 2 2006.173.05:12:56.02#ibcon#about to read 4, iclass 10, count 2 2006.173.05:12:56.02#ibcon#read 4, iclass 10, count 2 2006.173.05:12:56.02#ibcon#about to read 5, iclass 10, count 2 2006.173.05:12:56.02#ibcon#read 5, iclass 10, count 2 2006.173.05:12:56.02#ibcon#about to read 6, iclass 10, count 2 2006.173.05:12:56.02#ibcon#read 6, iclass 10, count 2 2006.173.05:12:56.02#ibcon#end of sib2, iclass 10, count 2 2006.173.05:12:56.02#ibcon#*after write, iclass 10, count 2 2006.173.05:12:56.02#ibcon#*before return 0, iclass 10, count 2 2006.173.05:12:56.02#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.05:12:56.02#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.05:12:56.02#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.05:12:56.02#ibcon#ireg 7 cls_cnt 0 2006.173.05:12:56.02#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.05:12:56.14#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.05:12:56.14#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.05:12:56.14#ibcon#enter wrdev, iclass 10, count 0 2006.173.05:12:56.14#ibcon#first serial, iclass 10, count 0 2006.173.05:12:56.14#ibcon#enter sib2, iclass 10, count 0 2006.173.05:12:56.14#ibcon#flushed, iclass 10, count 0 2006.173.05:12:56.14#ibcon#about to write, iclass 10, count 0 2006.173.05:12:56.14#ibcon#wrote, iclass 10, count 0 2006.173.05:12:56.14#ibcon#about to read 3, iclass 10, count 0 2006.173.05:12:56.16#ibcon#read 3, iclass 10, count 0 2006.173.05:12:56.16#ibcon#about to read 4, iclass 10, count 0 2006.173.05:12:56.16#ibcon#read 4, iclass 10, count 0 2006.173.05:12:56.16#ibcon#about to read 5, iclass 10, count 0 2006.173.05:12:56.16#ibcon#read 5, iclass 10, count 0 2006.173.05:12:56.16#ibcon#about to read 6, iclass 10, count 0 2006.173.05:12:56.16#ibcon#read 6, iclass 10, count 0 2006.173.05:12:56.16#ibcon#end of sib2, iclass 10, count 0 2006.173.05:12:56.16#ibcon#*mode == 0, iclass 10, count 0 2006.173.05:12:56.16#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.05:12:56.16#ibcon#[25=USB\r\n] 2006.173.05:12:56.16#ibcon#*before write, iclass 10, count 0 2006.173.05:12:56.16#ibcon#enter sib2, iclass 10, count 0 2006.173.05:12:56.16#ibcon#flushed, iclass 10, count 0 2006.173.05:12:56.16#ibcon#about to write, iclass 10, count 0 2006.173.05:12:56.16#ibcon#wrote, iclass 10, count 0 2006.173.05:12:56.16#ibcon#about to read 3, iclass 10, count 0 2006.173.05:12:56.19#ibcon#read 3, iclass 10, count 0 2006.173.05:12:56.19#ibcon#about to read 4, iclass 10, count 0 2006.173.05:12:56.19#ibcon#read 4, iclass 10, count 0 2006.173.05:12:56.19#ibcon#about to read 5, iclass 10, count 0 2006.173.05:12:56.19#ibcon#read 5, iclass 10, count 0 2006.173.05:12:56.19#ibcon#about to read 6, iclass 10, count 0 2006.173.05:12:56.19#ibcon#read 6, iclass 10, count 0 2006.173.05:12:56.19#ibcon#end of sib2, iclass 10, count 0 2006.173.05:12:56.19#ibcon#*after write, iclass 10, count 0 2006.173.05:12:56.19#ibcon#*before return 0, iclass 10, count 0 2006.173.05:12:56.19#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.05:12:56.19#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.05:12:56.19#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.05:12:56.19#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.05:12:56.19$vck44/valo=4,624.99 2006.173.05:12:56.19#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.05:12:56.19#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.05:12:56.19#ibcon#ireg 17 cls_cnt 0 2006.173.05:12:56.19#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.05:12:56.19#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.05:12:56.19#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.05:12:56.19#ibcon#enter wrdev, iclass 12, count 0 2006.173.05:12:56.19#ibcon#first serial, iclass 12, count 0 2006.173.05:12:56.19#ibcon#enter sib2, iclass 12, count 0 2006.173.05:12:56.19#ibcon#flushed, iclass 12, count 0 2006.173.05:12:56.19#ibcon#about to write, iclass 12, count 0 2006.173.05:12:56.19#ibcon#wrote, iclass 12, count 0 2006.173.05:12:56.19#ibcon#about to read 3, iclass 12, count 0 2006.173.05:12:56.21#ibcon#read 3, iclass 12, count 0 2006.173.05:12:56.21#ibcon#about to read 4, iclass 12, count 0 2006.173.05:12:56.21#ibcon#read 4, iclass 12, count 0 2006.173.05:12:56.21#ibcon#about to read 5, iclass 12, count 0 2006.173.05:12:56.21#ibcon#read 5, iclass 12, count 0 2006.173.05:12:56.21#ibcon#about to read 6, iclass 12, count 0 2006.173.05:12:56.21#ibcon#read 6, iclass 12, count 0 2006.173.05:12:56.21#ibcon#end of sib2, iclass 12, count 0 2006.173.05:12:56.21#ibcon#*mode == 0, iclass 12, count 0 2006.173.05:12:56.21#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.05:12:56.21#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.05:12:56.21#ibcon#*before write, iclass 12, count 0 2006.173.05:12:56.21#ibcon#enter sib2, iclass 12, count 0 2006.173.05:12:56.21#ibcon#flushed, iclass 12, count 0 2006.173.05:12:56.21#ibcon#about to write, iclass 12, count 0 2006.173.05:12:56.21#ibcon#wrote, iclass 12, count 0 2006.173.05:12:56.21#ibcon#about to read 3, iclass 12, count 0 2006.173.05:12:56.25#ibcon#read 3, iclass 12, count 0 2006.173.05:12:56.25#ibcon#about to read 4, iclass 12, count 0 2006.173.05:12:56.25#ibcon#read 4, iclass 12, count 0 2006.173.05:12:56.25#ibcon#about to read 5, iclass 12, count 0 2006.173.05:12:56.25#ibcon#read 5, iclass 12, count 0 2006.173.05:12:56.25#ibcon#about to read 6, iclass 12, count 0 2006.173.05:12:56.25#ibcon#read 6, iclass 12, count 0 2006.173.05:12:56.25#ibcon#end of sib2, iclass 12, count 0 2006.173.05:12:56.25#ibcon#*after write, iclass 12, count 0 2006.173.05:12:56.25#ibcon#*before return 0, iclass 12, count 0 2006.173.05:12:56.25#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.05:12:56.25#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.05:12:56.25#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.05:12:56.25#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.05:12:56.25$vck44/va=4,6 2006.173.05:12:56.25#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.05:12:56.25#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.05:12:56.25#ibcon#ireg 11 cls_cnt 2 2006.173.05:12:56.25#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.05:12:56.31#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.05:12:56.31#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.05:12:56.31#ibcon#enter wrdev, iclass 14, count 2 2006.173.05:12:56.31#ibcon#first serial, iclass 14, count 2 2006.173.05:12:56.31#ibcon#enter sib2, iclass 14, count 2 2006.173.05:12:56.31#ibcon#flushed, iclass 14, count 2 2006.173.05:12:56.31#ibcon#about to write, iclass 14, count 2 2006.173.05:12:56.31#ibcon#wrote, iclass 14, count 2 2006.173.05:12:56.31#ibcon#about to read 3, iclass 14, count 2 2006.173.05:12:56.33#ibcon#read 3, iclass 14, count 2 2006.173.05:12:56.33#ibcon#about to read 4, iclass 14, count 2 2006.173.05:12:56.33#ibcon#read 4, iclass 14, count 2 2006.173.05:12:56.33#ibcon#about to read 5, iclass 14, count 2 2006.173.05:12:56.33#ibcon#read 5, iclass 14, count 2 2006.173.05:12:56.33#ibcon#about to read 6, iclass 14, count 2 2006.173.05:12:56.33#ibcon#read 6, iclass 14, count 2 2006.173.05:12:56.33#ibcon#end of sib2, iclass 14, count 2 2006.173.05:12:56.33#ibcon#*mode == 0, iclass 14, count 2 2006.173.05:12:56.33#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.05:12:56.33#ibcon#[25=AT04-06\r\n] 2006.173.05:12:56.33#ibcon#*before write, iclass 14, count 2 2006.173.05:12:56.33#ibcon#enter sib2, iclass 14, count 2 2006.173.05:12:56.33#ibcon#flushed, iclass 14, count 2 2006.173.05:12:56.33#ibcon#about to write, iclass 14, count 2 2006.173.05:12:56.33#ibcon#wrote, iclass 14, count 2 2006.173.05:12:56.33#ibcon#about to read 3, iclass 14, count 2 2006.173.05:12:56.36#ibcon#read 3, iclass 14, count 2 2006.173.05:12:56.36#ibcon#about to read 4, iclass 14, count 2 2006.173.05:12:56.36#ibcon#read 4, iclass 14, count 2 2006.173.05:12:56.36#ibcon#about to read 5, iclass 14, count 2 2006.173.05:12:56.36#ibcon#read 5, iclass 14, count 2 2006.173.05:12:56.36#ibcon#about to read 6, iclass 14, count 2 2006.173.05:12:56.36#ibcon#read 6, iclass 14, count 2 2006.173.05:12:56.36#ibcon#end of sib2, iclass 14, count 2 2006.173.05:12:56.36#ibcon#*after write, iclass 14, count 2 2006.173.05:12:56.36#ibcon#*before return 0, iclass 14, count 2 2006.173.05:12:56.36#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.05:12:56.36#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.05:12:56.36#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.05:12:56.36#ibcon#ireg 7 cls_cnt 0 2006.173.05:12:56.36#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.05:12:56.48#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.05:12:56.48#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.05:12:56.48#ibcon#enter wrdev, iclass 14, count 0 2006.173.05:12:56.48#ibcon#first serial, iclass 14, count 0 2006.173.05:12:56.48#ibcon#enter sib2, iclass 14, count 0 2006.173.05:12:56.48#ibcon#flushed, iclass 14, count 0 2006.173.05:12:56.48#ibcon#about to write, iclass 14, count 0 2006.173.05:12:56.48#ibcon#wrote, iclass 14, count 0 2006.173.05:12:56.48#ibcon#about to read 3, iclass 14, count 0 2006.173.05:12:56.50#ibcon#read 3, iclass 14, count 0 2006.173.05:12:56.50#ibcon#about to read 4, iclass 14, count 0 2006.173.05:12:56.50#ibcon#read 4, iclass 14, count 0 2006.173.05:12:56.50#ibcon#about to read 5, iclass 14, count 0 2006.173.05:12:56.50#ibcon#read 5, iclass 14, count 0 2006.173.05:12:56.50#ibcon#about to read 6, iclass 14, count 0 2006.173.05:12:56.50#ibcon#read 6, iclass 14, count 0 2006.173.05:12:56.50#ibcon#end of sib2, iclass 14, count 0 2006.173.05:12:56.50#ibcon#*mode == 0, iclass 14, count 0 2006.173.05:12:56.50#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.05:12:56.50#ibcon#[25=USB\r\n] 2006.173.05:12:56.50#ibcon#*before write, iclass 14, count 0 2006.173.05:12:56.50#ibcon#enter sib2, iclass 14, count 0 2006.173.05:12:56.50#ibcon#flushed, iclass 14, count 0 2006.173.05:12:56.50#ibcon#about to write, iclass 14, count 0 2006.173.05:12:56.50#ibcon#wrote, iclass 14, count 0 2006.173.05:12:56.50#ibcon#about to read 3, iclass 14, count 0 2006.173.05:12:56.52#abcon#<5=/15 1.1 1.9 23.50 781005.6\r\n> 2006.173.05:12:56.53#ibcon#read 3, iclass 14, count 0 2006.173.05:12:56.53#ibcon#about to read 4, iclass 14, count 0 2006.173.05:12:56.53#ibcon#read 4, iclass 14, count 0 2006.173.05:12:56.53#ibcon#about to read 5, iclass 14, count 0 2006.173.05:12:56.53#ibcon#read 5, iclass 14, count 0 2006.173.05:12:56.53#ibcon#about to read 6, iclass 14, count 0 2006.173.05:12:56.53#ibcon#read 6, iclass 14, count 0 2006.173.05:12:56.53#ibcon#end of sib2, iclass 14, count 0 2006.173.05:12:56.53#ibcon#*after write, iclass 14, count 0 2006.173.05:12:56.53#ibcon#*before return 0, iclass 14, count 0 2006.173.05:12:56.53#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.05:12:56.53#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.05:12:56.53#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.05:12:56.53#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.05:12:56.53$vck44/valo=5,734.99 2006.173.05:12:56.53#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.05:12:56.53#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.05:12:56.53#ibcon#ireg 17 cls_cnt 0 2006.173.05:12:56.53#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.05:12:56.53#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.05:12:56.53#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.05:12:56.53#ibcon#enter wrdev, iclass 19, count 0 2006.173.05:12:56.53#ibcon#first serial, iclass 19, count 0 2006.173.05:12:56.53#ibcon#enter sib2, iclass 19, count 0 2006.173.05:12:56.53#ibcon#flushed, iclass 19, count 0 2006.173.05:12:56.53#ibcon#about to write, iclass 19, count 0 2006.173.05:12:56.53#ibcon#wrote, iclass 19, count 0 2006.173.05:12:56.53#ibcon#about to read 3, iclass 19, count 0 2006.173.05:12:56.54#abcon#{5=INTERFACE CLEAR} 2006.173.05:12:56.55#ibcon#read 3, iclass 19, count 0 2006.173.05:12:56.55#ibcon#about to read 4, iclass 19, count 0 2006.173.05:12:56.55#ibcon#read 4, iclass 19, count 0 2006.173.05:12:56.55#ibcon#about to read 5, iclass 19, count 0 2006.173.05:12:56.55#ibcon#read 5, iclass 19, count 0 2006.173.05:12:56.55#ibcon#about to read 6, iclass 19, count 0 2006.173.05:12:56.55#ibcon#read 6, iclass 19, count 0 2006.173.05:12:56.55#ibcon#end of sib2, iclass 19, count 0 2006.173.05:12:56.55#ibcon#*mode == 0, iclass 19, count 0 2006.173.05:12:56.55#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.05:12:56.55#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.05:12:56.55#ibcon#*before write, iclass 19, count 0 2006.173.05:12:56.55#ibcon#enter sib2, iclass 19, count 0 2006.173.05:12:56.55#ibcon#flushed, iclass 19, count 0 2006.173.05:12:56.55#ibcon#about to write, iclass 19, count 0 2006.173.05:12:56.55#ibcon#wrote, iclass 19, count 0 2006.173.05:12:56.55#ibcon#about to read 3, iclass 19, count 0 2006.173.05:12:56.59#ibcon#read 3, iclass 19, count 0 2006.173.05:12:56.59#ibcon#about to read 4, iclass 19, count 0 2006.173.05:12:56.59#ibcon#read 4, iclass 19, count 0 2006.173.05:12:56.59#ibcon#about to read 5, iclass 19, count 0 2006.173.05:12:56.59#ibcon#read 5, iclass 19, count 0 2006.173.05:12:56.59#ibcon#about to read 6, iclass 19, count 0 2006.173.05:12:56.59#ibcon#read 6, iclass 19, count 0 2006.173.05:12:56.59#ibcon#end of sib2, iclass 19, count 0 2006.173.05:12:56.59#ibcon#*after write, iclass 19, count 0 2006.173.05:12:56.59#ibcon#*before return 0, iclass 19, count 0 2006.173.05:12:56.59#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.05:12:56.59#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.05:12:56.59#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.05:12:56.59#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.05:12:56.59$vck44/va=5,4 2006.173.05:12:56.59#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.05:12:56.59#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.05:12:56.59#ibcon#ireg 11 cls_cnt 2 2006.173.05:12:56.59#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.05:12:56.60#abcon#[5=S1D000X0/0*\r\n] 2006.173.05:12:56.65#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.05:12:56.65#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.05:12:56.65#ibcon#enter wrdev, iclass 22, count 2 2006.173.05:12:56.65#ibcon#first serial, iclass 22, count 2 2006.173.05:12:56.65#ibcon#enter sib2, iclass 22, count 2 2006.173.05:12:56.65#ibcon#flushed, iclass 22, count 2 2006.173.05:12:56.65#ibcon#about to write, iclass 22, count 2 2006.173.05:12:56.65#ibcon#wrote, iclass 22, count 2 2006.173.05:12:56.65#ibcon#about to read 3, iclass 22, count 2 2006.173.05:12:56.67#ibcon#read 3, iclass 22, count 2 2006.173.05:12:56.67#ibcon#about to read 4, iclass 22, count 2 2006.173.05:12:56.67#ibcon#read 4, iclass 22, count 2 2006.173.05:12:56.67#ibcon#about to read 5, iclass 22, count 2 2006.173.05:12:56.67#ibcon#read 5, iclass 22, count 2 2006.173.05:12:56.67#ibcon#about to read 6, iclass 22, count 2 2006.173.05:12:56.67#ibcon#read 6, iclass 22, count 2 2006.173.05:12:56.67#ibcon#end of sib2, iclass 22, count 2 2006.173.05:12:56.67#ibcon#*mode == 0, iclass 22, count 2 2006.173.05:12:56.67#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.05:12:56.67#ibcon#[25=AT05-04\r\n] 2006.173.05:12:56.67#ibcon#*before write, iclass 22, count 2 2006.173.05:12:56.67#ibcon#enter sib2, iclass 22, count 2 2006.173.05:12:56.67#ibcon#flushed, iclass 22, count 2 2006.173.05:12:56.67#ibcon#about to write, iclass 22, count 2 2006.173.05:12:56.67#ibcon#wrote, iclass 22, count 2 2006.173.05:12:56.67#ibcon#about to read 3, iclass 22, count 2 2006.173.05:12:56.70#ibcon#read 3, iclass 22, count 2 2006.173.05:12:56.70#ibcon#about to read 4, iclass 22, count 2 2006.173.05:12:56.70#ibcon#read 4, iclass 22, count 2 2006.173.05:12:56.70#ibcon#about to read 5, iclass 22, count 2 2006.173.05:12:56.70#ibcon#read 5, iclass 22, count 2 2006.173.05:12:56.70#ibcon#about to read 6, iclass 22, count 2 2006.173.05:12:56.70#ibcon#read 6, iclass 22, count 2 2006.173.05:12:56.70#ibcon#end of sib2, iclass 22, count 2 2006.173.05:12:56.70#ibcon#*after write, iclass 22, count 2 2006.173.05:12:56.70#ibcon#*before return 0, iclass 22, count 2 2006.173.05:12:56.70#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.05:12:56.70#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.05:12:56.70#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.05:12:56.70#ibcon#ireg 7 cls_cnt 0 2006.173.05:12:56.70#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.05:12:56.82#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.05:12:56.82#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.05:12:56.82#ibcon#enter wrdev, iclass 22, count 0 2006.173.05:12:56.82#ibcon#first serial, iclass 22, count 0 2006.173.05:12:56.82#ibcon#enter sib2, iclass 22, count 0 2006.173.05:12:56.82#ibcon#flushed, iclass 22, count 0 2006.173.05:12:56.82#ibcon#about to write, iclass 22, count 0 2006.173.05:12:56.82#ibcon#wrote, iclass 22, count 0 2006.173.05:12:56.82#ibcon#about to read 3, iclass 22, count 0 2006.173.05:12:56.84#ibcon#read 3, iclass 22, count 0 2006.173.05:12:56.84#ibcon#about to read 4, iclass 22, count 0 2006.173.05:12:56.84#ibcon#read 4, iclass 22, count 0 2006.173.05:12:56.84#ibcon#about to read 5, iclass 22, count 0 2006.173.05:12:56.84#ibcon#read 5, iclass 22, count 0 2006.173.05:12:56.84#ibcon#about to read 6, iclass 22, count 0 2006.173.05:12:56.84#ibcon#read 6, iclass 22, count 0 2006.173.05:12:56.84#ibcon#end of sib2, iclass 22, count 0 2006.173.05:12:56.84#ibcon#*mode == 0, iclass 22, count 0 2006.173.05:12:56.84#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.05:12:56.84#ibcon#[25=USB\r\n] 2006.173.05:12:56.84#ibcon#*before write, iclass 22, count 0 2006.173.05:12:56.84#ibcon#enter sib2, iclass 22, count 0 2006.173.05:12:56.84#ibcon#flushed, iclass 22, count 0 2006.173.05:12:56.84#ibcon#about to write, iclass 22, count 0 2006.173.05:12:56.84#ibcon#wrote, iclass 22, count 0 2006.173.05:12:56.84#ibcon#about to read 3, iclass 22, count 0 2006.173.05:12:56.87#ibcon#read 3, iclass 22, count 0 2006.173.05:12:56.87#ibcon#about to read 4, iclass 22, count 0 2006.173.05:12:56.87#ibcon#read 4, iclass 22, count 0 2006.173.05:12:56.87#ibcon#about to read 5, iclass 22, count 0 2006.173.05:12:56.87#ibcon#read 5, iclass 22, count 0 2006.173.05:12:56.87#ibcon#about to read 6, iclass 22, count 0 2006.173.05:12:56.87#ibcon#read 6, iclass 22, count 0 2006.173.05:12:56.87#ibcon#end of sib2, iclass 22, count 0 2006.173.05:12:56.87#ibcon#*after write, iclass 22, count 0 2006.173.05:12:56.87#ibcon#*before return 0, iclass 22, count 0 2006.173.05:12:56.87#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.05:12:56.87#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.05:12:56.87#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.05:12:56.87#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.05:12:56.87$vck44/valo=6,814.99 2006.173.05:12:56.87#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.05:12:56.87#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.05:12:56.87#ibcon#ireg 17 cls_cnt 0 2006.173.05:12:56.87#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.05:12:56.87#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.05:12:56.87#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.05:12:56.87#ibcon#enter wrdev, iclass 24, count 0 2006.173.05:12:56.87#ibcon#first serial, iclass 24, count 0 2006.173.05:12:56.87#ibcon#enter sib2, iclass 24, count 0 2006.173.05:12:56.87#ibcon#flushed, iclass 24, count 0 2006.173.05:12:56.87#ibcon#about to write, iclass 24, count 0 2006.173.05:12:56.87#ibcon#wrote, iclass 24, count 0 2006.173.05:12:56.87#ibcon#about to read 3, iclass 24, count 0 2006.173.05:12:56.89#ibcon#read 3, iclass 24, count 0 2006.173.05:12:56.89#ibcon#about to read 4, iclass 24, count 0 2006.173.05:12:56.89#ibcon#read 4, iclass 24, count 0 2006.173.05:12:56.89#ibcon#about to read 5, iclass 24, count 0 2006.173.05:12:56.89#ibcon#read 5, iclass 24, count 0 2006.173.05:12:56.89#ibcon#about to read 6, iclass 24, count 0 2006.173.05:12:56.89#ibcon#read 6, iclass 24, count 0 2006.173.05:12:56.89#ibcon#end of sib2, iclass 24, count 0 2006.173.05:12:56.89#ibcon#*mode == 0, iclass 24, count 0 2006.173.05:12:56.89#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.05:12:56.89#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.05:12:56.89#ibcon#*before write, iclass 24, count 0 2006.173.05:12:56.89#ibcon#enter sib2, iclass 24, count 0 2006.173.05:12:56.89#ibcon#flushed, iclass 24, count 0 2006.173.05:12:56.89#ibcon#about to write, iclass 24, count 0 2006.173.05:12:56.89#ibcon#wrote, iclass 24, count 0 2006.173.05:12:56.89#ibcon#about to read 3, iclass 24, count 0 2006.173.05:12:56.93#ibcon#read 3, iclass 24, count 0 2006.173.05:12:56.93#ibcon#about to read 4, iclass 24, count 0 2006.173.05:12:56.93#ibcon#read 4, iclass 24, count 0 2006.173.05:12:56.93#ibcon#about to read 5, iclass 24, count 0 2006.173.05:12:56.93#ibcon#read 5, iclass 24, count 0 2006.173.05:12:56.93#ibcon#about to read 6, iclass 24, count 0 2006.173.05:12:56.93#ibcon#read 6, iclass 24, count 0 2006.173.05:12:56.93#ibcon#end of sib2, iclass 24, count 0 2006.173.05:12:56.93#ibcon#*after write, iclass 24, count 0 2006.173.05:12:56.93#ibcon#*before return 0, iclass 24, count 0 2006.173.05:12:56.93#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.05:12:56.93#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.05:12:56.93#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.05:12:56.93#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.05:12:56.93$vck44/va=6,3 2006.173.05:12:56.93#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.05:12:56.93#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.05:12:56.93#ibcon#ireg 11 cls_cnt 2 2006.173.05:12:56.93#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.05:12:56.99#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.05:12:56.99#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.05:12:56.99#ibcon#enter wrdev, iclass 26, count 2 2006.173.05:12:56.99#ibcon#first serial, iclass 26, count 2 2006.173.05:12:56.99#ibcon#enter sib2, iclass 26, count 2 2006.173.05:12:56.99#ibcon#flushed, iclass 26, count 2 2006.173.05:12:56.99#ibcon#about to write, iclass 26, count 2 2006.173.05:12:56.99#ibcon#wrote, iclass 26, count 2 2006.173.05:12:56.99#ibcon#about to read 3, iclass 26, count 2 2006.173.05:12:57.01#ibcon#read 3, iclass 26, count 2 2006.173.05:12:57.01#ibcon#about to read 4, iclass 26, count 2 2006.173.05:12:57.01#ibcon#read 4, iclass 26, count 2 2006.173.05:12:57.01#ibcon#about to read 5, iclass 26, count 2 2006.173.05:12:57.01#ibcon#read 5, iclass 26, count 2 2006.173.05:12:57.01#ibcon#about to read 6, iclass 26, count 2 2006.173.05:12:57.01#ibcon#read 6, iclass 26, count 2 2006.173.05:12:57.01#ibcon#end of sib2, iclass 26, count 2 2006.173.05:12:57.01#ibcon#*mode == 0, iclass 26, count 2 2006.173.05:12:57.01#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.05:12:57.01#ibcon#[25=AT06-03\r\n] 2006.173.05:12:57.01#ibcon#*before write, iclass 26, count 2 2006.173.05:12:57.01#ibcon#enter sib2, iclass 26, count 2 2006.173.05:12:57.01#ibcon#flushed, iclass 26, count 2 2006.173.05:12:57.01#ibcon#about to write, iclass 26, count 2 2006.173.05:12:57.01#ibcon#wrote, iclass 26, count 2 2006.173.05:12:57.01#ibcon#about to read 3, iclass 26, count 2 2006.173.05:12:57.04#ibcon#read 3, iclass 26, count 2 2006.173.05:12:57.04#ibcon#about to read 4, iclass 26, count 2 2006.173.05:12:57.04#ibcon#read 4, iclass 26, count 2 2006.173.05:12:57.04#ibcon#about to read 5, iclass 26, count 2 2006.173.05:12:57.04#ibcon#read 5, iclass 26, count 2 2006.173.05:12:57.04#ibcon#about to read 6, iclass 26, count 2 2006.173.05:12:57.04#ibcon#read 6, iclass 26, count 2 2006.173.05:12:57.04#ibcon#end of sib2, iclass 26, count 2 2006.173.05:12:57.04#ibcon#*after write, iclass 26, count 2 2006.173.05:12:57.04#ibcon#*before return 0, iclass 26, count 2 2006.173.05:12:57.04#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.05:12:57.04#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.05:12:57.04#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.05:12:57.04#ibcon#ireg 7 cls_cnt 0 2006.173.05:12:57.04#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.05:12:57.16#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.05:12:57.16#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.05:12:57.16#ibcon#enter wrdev, iclass 26, count 0 2006.173.05:12:57.16#ibcon#first serial, iclass 26, count 0 2006.173.05:12:57.16#ibcon#enter sib2, iclass 26, count 0 2006.173.05:12:57.16#ibcon#flushed, iclass 26, count 0 2006.173.05:12:57.16#ibcon#about to write, iclass 26, count 0 2006.173.05:12:57.16#ibcon#wrote, iclass 26, count 0 2006.173.05:12:57.16#ibcon#about to read 3, iclass 26, count 0 2006.173.05:12:57.18#ibcon#read 3, iclass 26, count 0 2006.173.05:12:57.18#ibcon#about to read 4, iclass 26, count 0 2006.173.05:12:57.18#ibcon#read 4, iclass 26, count 0 2006.173.05:12:57.18#ibcon#about to read 5, iclass 26, count 0 2006.173.05:12:57.18#ibcon#read 5, iclass 26, count 0 2006.173.05:12:57.18#ibcon#about to read 6, iclass 26, count 0 2006.173.05:12:57.18#ibcon#read 6, iclass 26, count 0 2006.173.05:12:57.18#ibcon#end of sib2, iclass 26, count 0 2006.173.05:12:57.18#ibcon#*mode == 0, iclass 26, count 0 2006.173.05:12:57.18#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.05:12:57.18#ibcon#[25=USB\r\n] 2006.173.05:12:57.18#ibcon#*before write, iclass 26, count 0 2006.173.05:12:57.18#ibcon#enter sib2, iclass 26, count 0 2006.173.05:12:57.18#ibcon#flushed, iclass 26, count 0 2006.173.05:12:57.18#ibcon#about to write, iclass 26, count 0 2006.173.05:12:57.18#ibcon#wrote, iclass 26, count 0 2006.173.05:12:57.18#ibcon#about to read 3, iclass 26, count 0 2006.173.05:12:57.21#ibcon#read 3, iclass 26, count 0 2006.173.05:12:57.21#ibcon#about to read 4, iclass 26, count 0 2006.173.05:12:57.21#ibcon#read 4, iclass 26, count 0 2006.173.05:12:57.21#ibcon#about to read 5, iclass 26, count 0 2006.173.05:12:57.21#ibcon#read 5, iclass 26, count 0 2006.173.05:12:57.21#ibcon#about to read 6, iclass 26, count 0 2006.173.05:12:57.21#ibcon#read 6, iclass 26, count 0 2006.173.05:12:57.21#ibcon#end of sib2, iclass 26, count 0 2006.173.05:12:57.21#ibcon#*after write, iclass 26, count 0 2006.173.05:12:57.21#ibcon#*before return 0, iclass 26, count 0 2006.173.05:12:57.21#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.05:12:57.21#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.05:12:57.21#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.05:12:57.21#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.05:12:57.21$vck44/valo=7,864.99 2006.173.05:12:57.21#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.05:12:57.21#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.05:12:57.21#ibcon#ireg 17 cls_cnt 0 2006.173.05:12:57.21#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.05:12:57.21#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.05:12:57.21#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.05:12:57.21#ibcon#enter wrdev, iclass 28, count 0 2006.173.05:12:57.21#ibcon#first serial, iclass 28, count 0 2006.173.05:12:57.21#ibcon#enter sib2, iclass 28, count 0 2006.173.05:12:57.21#ibcon#flushed, iclass 28, count 0 2006.173.05:12:57.21#ibcon#about to write, iclass 28, count 0 2006.173.05:12:57.21#ibcon#wrote, iclass 28, count 0 2006.173.05:12:57.21#ibcon#about to read 3, iclass 28, count 0 2006.173.05:12:57.23#ibcon#read 3, iclass 28, count 0 2006.173.05:12:57.23#ibcon#about to read 4, iclass 28, count 0 2006.173.05:12:57.23#ibcon#read 4, iclass 28, count 0 2006.173.05:12:57.23#ibcon#about to read 5, iclass 28, count 0 2006.173.05:12:57.23#ibcon#read 5, iclass 28, count 0 2006.173.05:12:57.23#ibcon#about to read 6, iclass 28, count 0 2006.173.05:12:57.23#ibcon#read 6, iclass 28, count 0 2006.173.05:12:57.23#ibcon#end of sib2, iclass 28, count 0 2006.173.05:12:57.23#ibcon#*mode == 0, iclass 28, count 0 2006.173.05:12:57.23#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.05:12:57.23#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.05:12:57.23#ibcon#*before write, iclass 28, count 0 2006.173.05:12:57.23#ibcon#enter sib2, iclass 28, count 0 2006.173.05:12:57.23#ibcon#flushed, iclass 28, count 0 2006.173.05:12:57.23#ibcon#about to write, iclass 28, count 0 2006.173.05:12:57.23#ibcon#wrote, iclass 28, count 0 2006.173.05:12:57.23#ibcon#about to read 3, iclass 28, count 0 2006.173.05:12:57.27#ibcon#read 3, iclass 28, count 0 2006.173.05:12:57.27#ibcon#about to read 4, iclass 28, count 0 2006.173.05:12:57.27#ibcon#read 4, iclass 28, count 0 2006.173.05:12:57.27#ibcon#about to read 5, iclass 28, count 0 2006.173.05:12:57.27#ibcon#read 5, iclass 28, count 0 2006.173.05:12:57.27#ibcon#about to read 6, iclass 28, count 0 2006.173.05:12:57.27#ibcon#read 6, iclass 28, count 0 2006.173.05:12:57.27#ibcon#end of sib2, iclass 28, count 0 2006.173.05:12:57.27#ibcon#*after write, iclass 28, count 0 2006.173.05:12:57.27#ibcon#*before return 0, iclass 28, count 0 2006.173.05:12:57.27#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.05:12:57.27#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.05:12:57.27#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.05:12:57.27#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.05:12:57.27$vck44/va=7,4 2006.173.05:12:57.27#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.05:12:57.27#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.05:12:57.27#ibcon#ireg 11 cls_cnt 2 2006.173.05:12:57.27#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.05:12:57.33#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.05:12:57.33#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.05:12:57.33#ibcon#enter wrdev, iclass 30, count 2 2006.173.05:12:57.33#ibcon#first serial, iclass 30, count 2 2006.173.05:12:57.33#ibcon#enter sib2, iclass 30, count 2 2006.173.05:12:57.33#ibcon#flushed, iclass 30, count 2 2006.173.05:12:57.33#ibcon#about to write, iclass 30, count 2 2006.173.05:12:57.33#ibcon#wrote, iclass 30, count 2 2006.173.05:12:57.33#ibcon#about to read 3, iclass 30, count 2 2006.173.05:12:57.35#ibcon#read 3, iclass 30, count 2 2006.173.05:12:57.35#ibcon#about to read 4, iclass 30, count 2 2006.173.05:12:57.35#ibcon#read 4, iclass 30, count 2 2006.173.05:12:57.35#ibcon#about to read 5, iclass 30, count 2 2006.173.05:12:57.35#ibcon#read 5, iclass 30, count 2 2006.173.05:12:57.35#ibcon#about to read 6, iclass 30, count 2 2006.173.05:12:57.35#ibcon#read 6, iclass 30, count 2 2006.173.05:12:57.35#ibcon#end of sib2, iclass 30, count 2 2006.173.05:12:57.35#ibcon#*mode == 0, iclass 30, count 2 2006.173.05:12:57.35#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.05:12:57.35#ibcon#[25=AT07-04\r\n] 2006.173.05:12:57.35#ibcon#*before write, iclass 30, count 2 2006.173.05:12:57.35#ibcon#enter sib2, iclass 30, count 2 2006.173.05:12:57.35#ibcon#flushed, iclass 30, count 2 2006.173.05:12:57.35#ibcon#about to write, iclass 30, count 2 2006.173.05:12:57.35#ibcon#wrote, iclass 30, count 2 2006.173.05:12:57.35#ibcon#about to read 3, iclass 30, count 2 2006.173.05:12:57.38#ibcon#read 3, iclass 30, count 2 2006.173.05:12:57.38#ibcon#about to read 4, iclass 30, count 2 2006.173.05:12:57.38#ibcon#read 4, iclass 30, count 2 2006.173.05:12:57.38#ibcon#about to read 5, iclass 30, count 2 2006.173.05:12:57.38#ibcon#read 5, iclass 30, count 2 2006.173.05:12:57.38#ibcon#about to read 6, iclass 30, count 2 2006.173.05:12:57.38#ibcon#read 6, iclass 30, count 2 2006.173.05:12:57.38#ibcon#end of sib2, iclass 30, count 2 2006.173.05:12:57.38#ibcon#*after write, iclass 30, count 2 2006.173.05:12:57.38#ibcon#*before return 0, iclass 30, count 2 2006.173.05:12:57.38#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.05:12:57.38#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.05:12:57.38#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.05:12:57.38#ibcon#ireg 7 cls_cnt 0 2006.173.05:12:57.38#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.05:12:57.50#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.05:12:57.50#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.05:12:57.50#ibcon#enter wrdev, iclass 30, count 0 2006.173.05:12:57.50#ibcon#first serial, iclass 30, count 0 2006.173.05:12:57.50#ibcon#enter sib2, iclass 30, count 0 2006.173.05:12:57.50#ibcon#flushed, iclass 30, count 0 2006.173.05:12:57.50#ibcon#about to write, iclass 30, count 0 2006.173.05:12:57.50#ibcon#wrote, iclass 30, count 0 2006.173.05:12:57.50#ibcon#about to read 3, iclass 30, count 0 2006.173.05:12:57.52#ibcon#read 3, iclass 30, count 0 2006.173.05:12:57.52#ibcon#about to read 4, iclass 30, count 0 2006.173.05:12:57.52#ibcon#read 4, iclass 30, count 0 2006.173.05:12:57.52#ibcon#about to read 5, iclass 30, count 0 2006.173.05:12:57.52#ibcon#read 5, iclass 30, count 0 2006.173.05:12:57.52#ibcon#about to read 6, iclass 30, count 0 2006.173.05:12:57.52#ibcon#read 6, iclass 30, count 0 2006.173.05:12:57.52#ibcon#end of sib2, iclass 30, count 0 2006.173.05:12:57.52#ibcon#*mode == 0, iclass 30, count 0 2006.173.05:12:57.52#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.05:12:57.52#ibcon#[25=USB\r\n] 2006.173.05:12:57.52#ibcon#*before write, iclass 30, count 0 2006.173.05:12:57.52#ibcon#enter sib2, iclass 30, count 0 2006.173.05:12:57.52#ibcon#flushed, iclass 30, count 0 2006.173.05:12:57.52#ibcon#about to write, iclass 30, count 0 2006.173.05:12:57.52#ibcon#wrote, iclass 30, count 0 2006.173.05:12:57.52#ibcon#about to read 3, iclass 30, count 0 2006.173.05:12:57.55#ibcon#read 3, iclass 30, count 0 2006.173.05:12:57.55#ibcon#about to read 4, iclass 30, count 0 2006.173.05:12:57.55#ibcon#read 4, iclass 30, count 0 2006.173.05:12:57.55#ibcon#about to read 5, iclass 30, count 0 2006.173.05:12:57.55#ibcon#read 5, iclass 30, count 0 2006.173.05:12:57.55#ibcon#about to read 6, iclass 30, count 0 2006.173.05:12:57.55#ibcon#read 6, iclass 30, count 0 2006.173.05:12:57.55#ibcon#end of sib2, iclass 30, count 0 2006.173.05:12:57.55#ibcon#*after write, iclass 30, count 0 2006.173.05:12:57.55#ibcon#*before return 0, iclass 30, count 0 2006.173.05:12:57.55#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.05:12:57.55#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.05:12:57.55#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.05:12:57.55#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.05:12:57.55$vck44/valo=8,884.99 2006.173.05:12:57.55#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.05:12:57.55#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.05:12:57.55#ibcon#ireg 17 cls_cnt 0 2006.173.05:12:57.55#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.05:12:57.55#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.05:12:57.55#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.05:12:57.55#ibcon#enter wrdev, iclass 32, count 0 2006.173.05:12:57.55#ibcon#first serial, iclass 32, count 0 2006.173.05:12:57.55#ibcon#enter sib2, iclass 32, count 0 2006.173.05:12:57.55#ibcon#flushed, iclass 32, count 0 2006.173.05:12:57.55#ibcon#about to write, iclass 32, count 0 2006.173.05:12:57.55#ibcon#wrote, iclass 32, count 0 2006.173.05:12:57.55#ibcon#about to read 3, iclass 32, count 0 2006.173.05:12:57.57#ibcon#read 3, iclass 32, count 0 2006.173.05:12:57.57#ibcon#about to read 4, iclass 32, count 0 2006.173.05:12:57.57#ibcon#read 4, iclass 32, count 0 2006.173.05:12:57.57#ibcon#about to read 5, iclass 32, count 0 2006.173.05:12:57.57#ibcon#read 5, iclass 32, count 0 2006.173.05:12:57.57#ibcon#about to read 6, iclass 32, count 0 2006.173.05:12:57.57#ibcon#read 6, iclass 32, count 0 2006.173.05:12:57.57#ibcon#end of sib2, iclass 32, count 0 2006.173.05:12:57.57#ibcon#*mode == 0, iclass 32, count 0 2006.173.05:12:57.57#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.05:12:57.57#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.05:12:57.57#ibcon#*before write, iclass 32, count 0 2006.173.05:12:57.57#ibcon#enter sib2, iclass 32, count 0 2006.173.05:12:57.57#ibcon#flushed, iclass 32, count 0 2006.173.05:12:57.57#ibcon#about to write, iclass 32, count 0 2006.173.05:12:57.57#ibcon#wrote, iclass 32, count 0 2006.173.05:12:57.57#ibcon#about to read 3, iclass 32, count 0 2006.173.05:12:57.61#ibcon#read 3, iclass 32, count 0 2006.173.05:12:57.61#ibcon#about to read 4, iclass 32, count 0 2006.173.05:12:57.61#ibcon#read 4, iclass 32, count 0 2006.173.05:12:57.61#ibcon#about to read 5, iclass 32, count 0 2006.173.05:12:57.61#ibcon#read 5, iclass 32, count 0 2006.173.05:12:57.61#ibcon#about to read 6, iclass 32, count 0 2006.173.05:12:57.61#ibcon#read 6, iclass 32, count 0 2006.173.05:12:57.61#ibcon#end of sib2, iclass 32, count 0 2006.173.05:12:57.61#ibcon#*after write, iclass 32, count 0 2006.173.05:12:57.61#ibcon#*before return 0, iclass 32, count 0 2006.173.05:12:57.61#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.05:12:57.61#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.05:12:57.61#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.05:12:57.61#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.05:12:57.61$vck44/va=8,4 2006.173.05:12:57.61#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.05:12:57.61#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.05:12:57.61#ibcon#ireg 11 cls_cnt 2 2006.173.05:12:57.61#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.05:12:57.67#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.05:12:57.67#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.05:12:57.67#ibcon#enter wrdev, iclass 34, count 2 2006.173.05:12:57.67#ibcon#first serial, iclass 34, count 2 2006.173.05:12:57.67#ibcon#enter sib2, iclass 34, count 2 2006.173.05:12:57.67#ibcon#flushed, iclass 34, count 2 2006.173.05:12:57.67#ibcon#about to write, iclass 34, count 2 2006.173.05:12:57.67#ibcon#wrote, iclass 34, count 2 2006.173.05:12:57.67#ibcon#about to read 3, iclass 34, count 2 2006.173.05:12:57.69#ibcon#read 3, iclass 34, count 2 2006.173.05:12:57.69#ibcon#about to read 4, iclass 34, count 2 2006.173.05:12:57.69#ibcon#read 4, iclass 34, count 2 2006.173.05:12:57.69#ibcon#about to read 5, iclass 34, count 2 2006.173.05:12:57.69#ibcon#read 5, iclass 34, count 2 2006.173.05:12:57.69#ibcon#about to read 6, iclass 34, count 2 2006.173.05:12:57.69#ibcon#read 6, iclass 34, count 2 2006.173.05:12:57.69#ibcon#end of sib2, iclass 34, count 2 2006.173.05:12:57.69#ibcon#*mode == 0, iclass 34, count 2 2006.173.05:12:57.69#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.05:12:57.69#ibcon#[25=AT08-04\r\n] 2006.173.05:12:57.69#ibcon#*before write, iclass 34, count 2 2006.173.05:12:57.69#ibcon#enter sib2, iclass 34, count 2 2006.173.05:12:57.69#ibcon#flushed, iclass 34, count 2 2006.173.05:12:57.69#ibcon#about to write, iclass 34, count 2 2006.173.05:12:57.69#ibcon#wrote, iclass 34, count 2 2006.173.05:12:57.69#ibcon#about to read 3, iclass 34, count 2 2006.173.05:12:57.72#ibcon#read 3, iclass 34, count 2 2006.173.05:12:57.72#ibcon#about to read 4, iclass 34, count 2 2006.173.05:12:57.72#ibcon#read 4, iclass 34, count 2 2006.173.05:12:57.72#ibcon#about to read 5, iclass 34, count 2 2006.173.05:12:57.72#ibcon#read 5, iclass 34, count 2 2006.173.05:12:57.72#ibcon#about to read 6, iclass 34, count 2 2006.173.05:12:57.72#ibcon#read 6, iclass 34, count 2 2006.173.05:12:57.72#ibcon#end of sib2, iclass 34, count 2 2006.173.05:12:57.72#ibcon#*after write, iclass 34, count 2 2006.173.05:12:57.72#ibcon#*before return 0, iclass 34, count 2 2006.173.05:12:57.72#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.05:12:57.72#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.05:12:57.72#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.05:12:57.72#ibcon#ireg 7 cls_cnt 0 2006.173.05:12:57.72#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.05:12:57.84#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.05:12:57.84#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.05:12:57.84#ibcon#enter wrdev, iclass 34, count 0 2006.173.05:12:57.84#ibcon#first serial, iclass 34, count 0 2006.173.05:12:57.84#ibcon#enter sib2, iclass 34, count 0 2006.173.05:12:57.84#ibcon#flushed, iclass 34, count 0 2006.173.05:12:57.84#ibcon#about to write, iclass 34, count 0 2006.173.05:12:57.84#ibcon#wrote, iclass 34, count 0 2006.173.05:12:57.84#ibcon#about to read 3, iclass 34, count 0 2006.173.05:12:57.86#ibcon#read 3, iclass 34, count 0 2006.173.05:12:57.86#ibcon#about to read 4, iclass 34, count 0 2006.173.05:12:57.86#ibcon#read 4, iclass 34, count 0 2006.173.05:12:57.86#ibcon#about to read 5, iclass 34, count 0 2006.173.05:12:57.86#ibcon#read 5, iclass 34, count 0 2006.173.05:12:57.86#ibcon#about to read 6, iclass 34, count 0 2006.173.05:12:57.86#ibcon#read 6, iclass 34, count 0 2006.173.05:12:57.86#ibcon#end of sib2, iclass 34, count 0 2006.173.05:12:57.86#ibcon#*mode == 0, iclass 34, count 0 2006.173.05:12:57.86#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.05:12:57.86#ibcon#[25=USB\r\n] 2006.173.05:12:57.86#ibcon#*before write, iclass 34, count 0 2006.173.05:12:57.86#ibcon#enter sib2, iclass 34, count 0 2006.173.05:12:57.86#ibcon#flushed, iclass 34, count 0 2006.173.05:12:57.86#ibcon#about to write, iclass 34, count 0 2006.173.05:12:57.86#ibcon#wrote, iclass 34, count 0 2006.173.05:12:57.86#ibcon#about to read 3, iclass 34, count 0 2006.173.05:12:57.89#ibcon#read 3, iclass 34, count 0 2006.173.05:12:57.89#ibcon#about to read 4, iclass 34, count 0 2006.173.05:12:57.89#ibcon#read 4, iclass 34, count 0 2006.173.05:12:57.89#ibcon#about to read 5, iclass 34, count 0 2006.173.05:12:57.89#ibcon#read 5, iclass 34, count 0 2006.173.05:12:57.89#ibcon#about to read 6, iclass 34, count 0 2006.173.05:12:57.89#ibcon#read 6, iclass 34, count 0 2006.173.05:12:57.89#ibcon#end of sib2, iclass 34, count 0 2006.173.05:12:57.89#ibcon#*after write, iclass 34, count 0 2006.173.05:12:57.89#ibcon#*before return 0, iclass 34, count 0 2006.173.05:12:57.89#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.05:12:57.89#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.05:12:57.89#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.05:12:57.89#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.05:12:57.89$vck44/vblo=1,629.99 2006.173.05:12:57.89#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.05:12:57.89#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.05:12:57.89#ibcon#ireg 17 cls_cnt 0 2006.173.05:12:57.89#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.05:12:57.89#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.05:12:57.89#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.05:12:57.89#ibcon#enter wrdev, iclass 36, count 0 2006.173.05:12:57.89#ibcon#first serial, iclass 36, count 0 2006.173.05:12:57.89#ibcon#enter sib2, iclass 36, count 0 2006.173.05:12:57.89#ibcon#flushed, iclass 36, count 0 2006.173.05:12:57.89#ibcon#about to write, iclass 36, count 0 2006.173.05:12:57.89#ibcon#wrote, iclass 36, count 0 2006.173.05:12:57.89#ibcon#about to read 3, iclass 36, count 0 2006.173.05:12:57.91#ibcon#read 3, iclass 36, count 0 2006.173.05:12:57.91#ibcon#about to read 4, iclass 36, count 0 2006.173.05:12:57.91#ibcon#read 4, iclass 36, count 0 2006.173.05:12:57.91#ibcon#about to read 5, iclass 36, count 0 2006.173.05:12:57.91#ibcon#read 5, iclass 36, count 0 2006.173.05:12:57.91#ibcon#about to read 6, iclass 36, count 0 2006.173.05:12:57.91#ibcon#read 6, iclass 36, count 0 2006.173.05:12:57.91#ibcon#end of sib2, iclass 36, count 0 2006.173.05:12:57.91#ibcon#*mode == 0, iclass 36, count 0 2006.173.05:12:57.91#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.05:12:57.91#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.05:12:57.91#ibcon#*before write, iclass 36, count 0 2006.173.05:12:57.91#ibcon#enter sib2, iclass 36, count 0 2006.173.05:12:57.91#ibcon#flushed, iclass 36, count 0 2006.173.05:12:57.91#ibcon#about to write, iclass 36, count 0 2006.173.05:12:57.91#ibcon#wrote, iclass 36, count 0 2006.173.05:12:57.91#ibcon#about to read 3, iclass 36, count 0 2006.173.05:12:57.95#ibcon#read 3, iclass 36, count 0 2006.173.05:12:57.95#ibcon#about to read 4, iclass 36, count 0 2006.173.05:12:57.95#ibcon#read 4, iclass 36, count 0 2006.173.05:12:57.95#ibcon#about to read 5, iclass 36, count 0 2006.173.05:12:57.95#ibcon#read 5, iclass 36, count 0 2006.173.05:12:57.95#ibcon#about to read 6, iclass 36, count 0 2006.173.05:12:57.95#ibcon#read 6, iclass 36, count 0 2006.173.05:12:57.95#ibcon#end of sib2, iclass 36, count 0 2006.173.05:12:57.95#ibcon#*after write, iclass 36, count 0 2006.173.05:12:57.95#ibcon#*before return 0, iclass 36, count 0 2006.173.05:12:57.95#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.05:12:57.95#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.05:12:57.95#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.05:12:57.95#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.05:12:57.95$vck44/vb=1,4 2006.173.05:12:57.95#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.05:12:57.95#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.05:12:57.95#ibcon#ireg 11 cls_cnt 2 2006.173.05:12:57.95#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.05:12:57.95#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.05:12:57.95#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.05:12:57.95#ibcon#enter wrdev, iclass 38, count 2 2006.173.05:12:57.95#ibcon#first serial, iclass 38, count 2 2006.173.05:12:57.95#ibcon#enter sib2, iclass 38, count 2 2006.173.05:12:57.95#ibcon#flushed, iclass 38, count 2 2006.173.05:12:57.95#ibcon#about to write, iclass 38, count 2 2006.173.05:12:57.95#ibcon#wrote, iclass 38, count 2 2006.173.05:12:57.95#ibcon#about to read 3, iclass 38, count 2 2006.173.05:12:57.97#ibcon#read 3, iclass 38, count 2 2006.173.05:12:57.97#ibcon#about to read 4, iclass 38, count 2 2006.173.05:12:57.97#ibcon#read 4, iclass 38, count 2 2006.173.05:12:57.97#ibcon#about to read 5, iclass 38, count 2 2006.173.05:12:57.97#ibcon#read 5, iclass 38, count 2 2006.173.05:12:57.97#ibcon#about to read 6, iclass 38, count 2 2006.173.05:12:57.97#ibcon#read 6, iclass 38, count 2 2006.173.05:12:57.97#ibcon#end of sib2, iclass 38, count 2 2006.173.05:12:57.97#ibcon#*mode == 0, iclass 38, count 2 2006.173.05:12:57.97#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.05:12:57.97#ibcon#[27=AT01-04\r\n] 2006.173.05:12:57.97#ibcon#*before write, iclass 38, count 2 2006.173.05:12:57.97#ibcon#enter sib2, iclass 38, count 2 2006.173.05:12:57.97#ibcon#flushed, iclass 38, count 2 2006.173.05:12:57.97#ibcon#about to write, iclass 38, count 2 2006.173.05:12:57.97#ibcon#wrote, iclass 38, count 2 2006.173.05:12:57.97#ibcon#about to read 3, iclass 38, count 2 2006.173.05:12:58.00#ibcon#read 3, iclass 38, count 2 2006.173.05:12:58.00#ibcon#about to read 4, iclass 38, count 2 2006.173.05:12:58.00#ibcon#read 4, iclass 38, count 2 2006.173.05:12:58.00#ibcon#about to read 5, iclass 38, count 2 2006.173.05:12:58.00#ibcon#read 5, iclass 38, count 2 2006.173.05:12:58.00#ibcon#about to read 6, iclass 38, count 2 2006.173.05:12:58.00#ibcon#read 6, iclass 38, count 2 2006.173.05:12:58.00#ibcon#end of sib2, iclass 38, count 2 2006.173.05:12:58.00#ibcon#*after write, iclass 38, count 2 2006.173.05:12:58.00#ibcon#*before return 0, iclass 38, count 2 2006.173.05:12:58.00#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.05:12:58.00#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.05:12:58.00#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.05:12:58.00#ibcon#ireg 7 cls_cnt 0 2006.173.05:12:58.00#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.05:12:58.12#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.05:12:58.12#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.05:12:58.12#ibcon#enter wrdev, iclass 38, count 0 2006.173.05:12:58.12#ibcon#first serial, iclass 38, count 0 2006.173.05:12:58.12#ibcon#enter sib2, iclass 38, count 0 2006.173.05:12:58.12#ibcon#flushed, iclass 38, count 0 2006.173.05:12:58.12#ibcon#about to write, iclass 38, count 0 2006.173.05:12:58.12#ibcon#wrote, iclass 38, count 0 2006.173.05:12:58.12#ibcon#about to read 3, iclass 38, count 0 2006.173.05:12:58.14#ibcon#read 3, iclass 38, count 0 2006.173.05:12:58.14#ibcon#about to read 4, iclass 38, count 0 2006.173.05:12:58.14#ibcon#read 4, iclass 38, count 0 2006.173.05:12:58.14#ibcon#about to read 5, iclass 38, count 0 2006.173.05:12:58.14#ibcon#read 5, iclass 38, count 0 2006.173.05:12:58.14#ibcon#about to read 6, iclass 38, count 0 2006.173.05:12:58.14#ibcon#read 6, iclass 38, count 0 2006.173.05:12:58.14#ibcon#end of sib2, iclass 38, count 0 2006.173.05:12:58.14#ibcon#*mode == 0, iclass 38, count 0 2006.173.05:12:58.14#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.05:12:58.14#ibcon#[27=USB\r\n] 2006.173.05:12:58.14#ibcon#*before write, iclass 38, count 0 2006.173.05:12:58.14#ibcon#enter sib2, iclass 38, count 0 2006.173.05:12:58.14#ibcon#flushed, iclass 38, count 0 2006.173.05:12:58.14#ibcon#about to write, iclass 38, count 0 2006.173.05:12:58.14#ibcon#wrote, iclass 38, count 0 2006.173.05:12:58.14#ibcon#about to read 3, iclass 38, count 0 2006.173.05:12:58.17#ibcon#read 3, iclass 38, count 0 2006.173.05:12:58.17#ibcon#about to read 4, iclass 38, count 0 2006.173.05:12:58.17#ibcon#read 4, iclass 38, count 0 2006.173.05:12:58.17#ibcon#about to read 5, iclass 38, count 0 2006.173.05:12:58.17#ibcon#read 5, iclass 38, count 0 2006.173.05:12:58.17#ibcon#about to read 6, iclass 38, count 0 2006.173.05:12:58.17#ibcon#read 6, iclass 38, count 0 2006.173.05:12:58.17#ibcon#end of sib2, iclass 38, count 0 2006.173.05:12:58.17#ibcon#*after write, iclass 38, count 0 2006.173.05:12:58.17#ibcon#*before return 0, iclass 38, count 0 2006.173.05:12:58.17#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.05:12:58.17#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.05:12:58.17#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.05:12:58.17#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.05:12:58.17$vck44/vblo=2,634.99 2006.173.05:12:58.17#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.05:12:58.17#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.05:12:58.17#ibcon#ireg 17 cls_cnt 0 2006.173.05:12:58.17#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.05:12:58.17#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.05:12:58.17#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.05:12:58.17#ibcon#enter wrdev, iclass 40, count 0 2006.173.05:12:58.17#ibcon#first serial, iclass 40, count 0 2006.173.05:12:58.17#ibcon#enter sib2, iclass 40, count 0 2006.173.05:12:58.17#ibcon#flushed, iclass 40, count 0 2006.173.05:12:58.17#ibcon#about to write, iclass 40, count 0 2006.173.05:12:58.17#ibcon#wrote, iclass 40, count 0 2006.173.05:12:58.17#ibcon#about to read 3, iclass 40, count 0 2006.173.05:12:58.19#ibcon#read 3, iclass 40, count 0 2006.173.05:12:58.19#ibcon#about to read 4, iclass 40, count 0 2006.173.05:12:58.19#ibcon#read 4, iclass 40, count 0 2006.173.05:12:58.19#ibcon#about to read 5, iclass 40, count 0 2006.173.05:12:58.19#ibcon#read 5, iclass 40, count 0 2006.173.05:12:58.19#ibcon#about to read 6, iclass 40, count 0 2006.173.05:12:58.19#ibcon#read 6, iclass 40, count 0 2006.173.05:12:58.19#ibcon#end of sib2, iclass 40, count 0 2006.173.05:12:58.19#ibcon#*mode == 0, iclass 40, count 0 2006.173.05:12:58.19#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.05:12:58.19#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.05:12:58.19#ibcon#*before write, iclass 40, count 0 2006.173.05:12:58.19#ibcon#enter sib2, iclass 40, count 0 2006.173.05:12:58.19#ibcon#flushed, iclass 40, count 0 2006.173.05:12:58.19#ibcon#about to write, iclass 40, count 0 2006.173.05:12:58.19#ibcon#wrote, iclass 40, count 0 2006.173.05:12:58.19#ibcon#about to read 3, iclass 40, count 0 2006.173.05:12:58.23#ibcon#read 3, iclass 40, count 0 2006.173.05:12:58.23#ibcon#about to read 4, iclass 40, count 0 2006.173.05:12:58.23#ibcon#read 4, iclass 40, count 0 2006.173.05:12:58.23#ibcon#about to read 5, iclass 40, count 0 2006.173.05:12:58.23#ibcon#read 5, iclass 40, count 0 2006.173.05:12:58.23#ibcon#about to read 6, iclass 40, count 0 2006.173.05:12:58.23#ibcon#read 6, iclass 40, count 0 2006.173.05:12:58.23#ibcon#end of sib2, iclass 40, count 0 2006.173.05:12:58.23#ibcon#*after write, iclass 40, count 0 2006.173.05:12:58.23#ibcon#*before return 0, iclass 40, count 0 2006.173.05:12:58.23#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.05:12:58.23#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.05:12:58.23#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.05:12:58.23#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.05:12:58.23$vck44/vb=2,4 2006.173.05:12:58.23#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.05:12:58.23#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.05:12:58.23#ibcon#ireg 11 cls_cnt 2 2006.173.05:12:58.23#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.05:12:58.29#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.05:12:58.29#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.05:12:58.29#ibcon#enter wrdev, iclass 4, count 2 2006.173.05:12:58.29#ibcon#first serial, iclass 4, count 2 2006.173.05:12:58.29#ibcon#enter sib2, iclass 4, count 2 2006.173.05:12:58.29#ibcon#flushed, iclass 4, count 2 2006.173.05:12:58.29#ibcon#about to write, iclass 4, count 2 2006.173.05:12:58.29#ibcon#wrote, iclass 4, count 2 2006.173.05:12:58.29#ibcon#about to read 3, iclass 4, count 2 2006.173.05:12:58.31#ibcon#read 3, iclass 4, count 2 2006.173.05:12:58.31#ibcon#about to read 4, iclass 4, count 2 2006.173.05:12:58.31#ibcon#read 4, iclass 4, count 2 2006.173.05:12:58.31#ibcon#about to read 5, iclass 4, count 2 2006.173.05:12:58.31#ibcon#read 5, iclass 4, count 2 2006.173.05:12:58.31#ibcon#about to read 6, iclass 4, count 2 2006.173.05:12:58.31#ibcon#read 6, iclass 4, count 2 2006.173.05:12:58.31#ibcon#end of sib2, iclass 4, count 2 2006.173.05:12:58.31#ibcon#*mode == 0, iclass 4, count 2 2006.173.05:12:58.31#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.05:12:58.31#ibcon#[27=AT02-04\r\n] 2006.173.05:12:58.31#ibcon#*before write, iclass 4, count 2 2006.173.05:12:58.31#ibcon#enter sib2, iclass 4, count 2 2006.173.05:12:58.31#ibcon#flushed, iclass 4, count 2 2006.173.05:12:58.31#ibcon#about to write, iclass 4, count 2 2006.173.05:12:58.31#ibcon#wrote, iclass 4, count 2 2006.173.05:12:58.31#ibcon#about to read 3, iclass 4, count 2 2006.173.05:12:58.34#ibcon#read 3, iclass 4, count 2 2006.173.05:12:58.34#ibcon#about to read 4, iclass 4, count 2 2006.173.05:12:58.34#ibcon#read 4, iclass 4, count 2 2006.173.05:12:58.34#ibcon#about to read 5, iclass 4, count 2 2006.173.05:12:58.34#ibcon#read 5, iclass 4, count 2 2006.173.05:12:58.34#ibcon#about to read 6, iclass 4, count 2 2006.173.05:12:58.34#ibcon#read 6, iclass 4, count 2 2006.173.05:12:58.34#ibcon#end of sib2, iclass 4, count 2 2006.173.05:12:58.34#ibcon#*after write, iclass 4, count 2 2006.173.05:12:58.34#ibcon#*before return 0, iclass 4, count 2 2006.173.05:12:58.34#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.05:12:58.34#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.05:12:58.34#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.05:12:58.34#ibcon#ireg 7 cls_cnt 0 2006.173.05:12:58.34#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.05:12:58.46#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.05:12:58.46#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.05:12:58.46#ibcon#enter wrdev, iclass 4, count 0 2006.173.05:12:58.46#ibcon#first serial, iclass 4, count 0 2006.173.05:12:58.46#ibcon#enter sib2, iclass 4, count 0 2006.173.05:12:58.46#ibcon#flushed, iclass 4, count 0 2006.173.05:12:58.46#ibcon#about to write, iclass 4, count 0 2006.173.05:12:58.46#ibcon#wrote, iclass 4, count 0 2006.173.05:12:58.46#ibcon#about to read 3, iclass 4, count 0 2006.173.05:12:58.48#ibcon#read 3, iclass 4, count 0 2006.173.05:12:58.48#ibcon#about to read 4, iclass 4, count 0 2006.173.05:12:58.48#ibcon#read 4, iclass 4, count 0 2006.173.05:12:58.48#ibcon#about to read 5, iclass 4, count 0 2006.173.05:12:58.48#ibcon#read 5, iclass 4, count 0 2006.173.05:12:58.48#ibcon#about to read 6, iclass 4, count 0 2006.173.05:12:58.48#ibcon#read 6, iclass 4, count 0 2006.173.05:12:58.48#ibcon#end of sib2, iclass 4, count 0 2006.173.05:12:58.48#ibcon#*mode == 0, iclass 4, count 0 2006.173.05:12:58.48#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.05:12:58.48#ibcon#[27=USB\r\n] 2006.173.05:12:58.48#ibcon#*before write, iclass 4, count 0 2006.173.05:12:58.48#ibcon#enter sib2, iclass 4, count 0 2006.173.05:12:58.48#ibcon#flushed, iclass 4, count 0 2006.173.05:12:58.48#ibcon#about to write, iclass 4, count 0 2006.173.05:12:58.48#ibcon#wrote, iclass 4, count 0 2006.173.05:12:58.48#ibcon#about to read 3, iclass 4, count 0 2006.173.05:12:58.51#ibcon#read 3, iclass 4, count 0 2006.173.05:12:58.51#ibcon#about to read 4, iclass 4, count 0 2006.173.05:12:58.51#ibcon#read 4, iclass 4, count 0 2006.173.05:12:58.51#ibcon#about to read 5, iclass 4, count 0 2006.173.05:12:58.51#ibcon#read 5, iclass 4, count 0 2006.173.05:12:58.51#ibcon#about to read 6, iclass 4, count 0 2006.173.05:12:58.51#ibcon#read 6, iclass 4, count 0 2006.173.05:12:58.51#ibcon#end of sib2, iclass 4, count 0 2006.173.05:12:58.51#ibcon#*after write, iclass 4, count 0 2006.173.05:12:58.51#ibcon#*before return 0, iclass 4, count 0 2006.173.05:12:58.51#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.05:12:58.51#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.05:12:58.51#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.05:12:58.51#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.05:12:58.51$vck44/vblo=3,649.99 2006.173.05:12:58.51#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.05:12:58.51#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.05:12:58.51#ibcon#ireg 17 cls_cnt 0 2006.173.05:12:58.51#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.05:12:58.51#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.05:12:58.51#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.05:12:58.51#ibcon#enter wrdev, iclass 6, count 0 2006.173.05:12:58.51#ibcon#first serial, iclass 6, count 0 2006.173.05:12:58.51#ibcon#enter sib2, iclass 6, count 0 2006.173.05:12:58.51#ibcon#flushed, iclass 6, count 0 2006.173.05:12:58.51#ibcon#about to write, iclass 6, count 0 2006.173.05:12:58.51#ibcon#wrote, iclass 6, count 0 2006.173.05:12:58.51#ibcon#about to read 3, iclass 6, count 0 2006.173.05:12:58.53#ibcon#read 3, iclass 6, count 0 2006.173.05:12:58.53#ibcon#about to read 4, iclass 6, count 0 2006.173.05:12:58.53#ibcon#read 4, iclass 6, count 0 2006.173.05:12:58.53#ibcon#about to read 5, iclass 6, count 0 2006.173.05:12:58.53#ibcon#read 5, iclass 6, count 0 2006.173.05:12:58.53#ibcon#about to read 6, iclass 6, count 0 2006.173.05:12:58.53#ibcon#read 6, iclass 6, count 0 2006.173.05:12:58.53#ibcon#end of sib2, iclass 6, count 0 2006.173.05:12:58.53#ibcon#*mode == 0, iclass 6, count 0 2006.173.05:12:58.53#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.05:12:58.53#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.05:12:58.53#ibcon#*before write, iclass 6, count 0 2006.173.05:12:58.53#ibcon#enter sib2, iclass 6, count 0 2006.173.05:12:58.53#ibcon#flushed, iclass 6, count 0 2006.173.05:12:58.53#ibcon#about to write, iclass 6, count 0 2006.173.05:12:58.53#ibcon#wrote, iclass 6, count 0 2006.173.05:12:58.53#ibcon#about to read 3, iclass 6, count 0 2006.173.05:12:58.57#ibcon#read 3, iclass 6, count 0 2006.173.05:12:58.57#ibcon#about to read 4, iclass 6, count 0 2006.173.05:12:58.57#ibcon#read 4, iclass 6, count 0 2006.173.05:12:58.57#ibcon#about to read 5, iclass 6, count 0 2006.173.05:12:58.57#ibcon#read 5, iclass 6, count 0 2006.173.05:12:58.57#ibcon#about to read 6, iclass 6, count 0 2006.173.05:12:58.57#ibcon#read 6, iclass 6, count 0 2006.173.05:12:58.57#ibcon#end of sib2, iclass 6, count 0 2006.173.05:12:58.57#ibcon#*after write, iclass 6, count 0 2006.173.05:12:58.57#ibcon#*before return 0, iclass 6, count 0 2006.173.05:12:58.57#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.05:12:58.57#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.05:12:58.57#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.05:12:58.57#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.05:12:58.57$vck44/vb=3,4 2006.173.05:12:58.57#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.05:12:58.57#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.05:12:58.57#ibcon#ireg 11 cls_cnt 2 2006.173.05:12:58.57#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.05:12:58.63#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.05:12:58.63#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.05:12:58.63#ibcon#enter wrdev, iclass 10, count 2 2006.173.05:12:58.63#ibcon#first serial, iclass 10, count 2 2006.173.05:12:58.63#ibcon#enter sib2, iclass 10, count 2 2006.173.05:12:58.63#ibcon#flushed, iclass 10, count 2 2006.173.05:12:58.63#ibcon#about to write, iclass 10, count 2 2006.173.05:12:58.63#ibcon#wrote, iclass 10, count 2 2006.173.05:12:58.63#ibcon#about to read 3, iclass 10, count 2 2006.173.05:12:58.65#ibcon#read 3, iclass 10, count 2 2006.173.05:12:58.65#ibcon#about to read 4, iclass 10, count 2 2006.173.05:12:58.65#ibcon#read 4, iclass 10, count 2 2006.173.05:12:58.65#ibcon#about to read 5, iclass 10, count 2 2006.173.05:12:58.65#ibcon#read 5, iclass 10, count 2 2006.173.05:12:58.65#ibcon#about to read 6, iclass 10, count 2 2006.173.05:12:58.65#ibcon#read 6, iclass 10, count 2 2006.173.05:12:58.65#ibcon#end of sib2, iclass 10, count 2 2006.173.05:12:58.65#ibcon#*mode == 0, iclass 10, count 2 2006.173.05:12:58.65#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.05:12:58.65#ibcon#[27=AT03-04\r\n] 2006.173.05:12:58.65#ibcon#*before write, iclass 10, count 2 2006.173.05:12:58.65#ibcon#enter sib2, iclass 10, count 2 2006.173.05:12:58.65#ibcon#flushed, iclass 10, count 2 2006.173.05:12:58.65#ibcon#about to write, iclass 10, count 2 2006.173.05:12:58.65#ibcon#wrote, iclass 10, count 2 2006.173.05:12:58.65#ibcon#about to read 3, iclass 10, count 2 2006.173.05:12:58.68#ibcon#read 3, iclass 10, count 2 2006.173.05:12:58.68#ibcon#about to read 4, iclass 10, count 2 2006.173.05:12:58.68#ibcon#read 4, iclass 10, count 2 2006.173.05:12:58.68#ibcon#about to read 5, iclass 10, count 2 2006.173.05:12:58.68#ibcon#read 5, iclass 10, count 2 2006.173.05:12:58.68#ibcon#about to read 6, iclass 10, count 2 2006.173.05:12:58.68#ibcon#read 6, iclass 10, count 2 2006.173.05:12:58.68#ibcon#end of sib2, iclass 10, count 2 2006.173.05:12:58.68#ibcon#*after write, iclass 10, count 2 2006.173.05:12:58.68#ibcon#*before return 0, iclass 10, count 2 2006.173.05:12:58.68#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.05:12:58.68#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.05:12:58.68#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.05:12:58.68#ibcon#ireg 7 cls_cnt 0 2006.173.05:12:58.68#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.05:12:58.80#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.05:12:58.80#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.05:12:58.80#ibcon#enter wrdev, iclass 10, count 0 2006.173.05:12:58.80#ibcon#first serial, iclass 10, count 0 2006.173.05:12:58.80#ibcon#enter sib2, iclass 10, count 0 2006.173.05:12:58.80#ibcon#flushed, iclass 10, count 0 2006.173.05:12:58.80#ibcon#about to write, iclass 10, count 0 2006.173.05:12:58.80#ibcon#wrote, iclass 10, count 0 2006.173.05:12:58.80#ibcon#about to read 3, iclass 10, count 0 2006.173.05:12:58.82#ibcon#read 3, iclass 10, count 0 2006.173.05:12:58.82#ibcon#about to read 4, iclass 10, count 0 2006.173.05:12:58.82#ibcon#read 4, iclass 10, count 0 2006.173.05:12:58.82#ibcon#about to read 5, iclass 10, count 0 2006.173.05:12:58.82#ibcon#read 5, iclass 10, count 0 2006.173.05:12:58.82#ibcon#about to read 6, iclass 10, count 0 2006.173.05:12:58.82#ibcon#read 6, iclass 10, count 0 2006.173.05:12:58.82#ibcon#end of sib2, iclass 10, count 0 2006.173.05:12:58.82#ibcon#*mode == 0, iclass 10, count 0 2006.173.05:12:58.82#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.05:12:58.82#ibcon#[27=USB\r\n] 2006.173.05:12:58.82#ibcon#*before write, iclass 10, count 0 2006.173.05:12:58.82#ibcon#enter sib2, iclass 10, count 0 2006.173.05:12:58.82#ibcon#flushed, iclass 10, count 0 2006.173.05:12:58.82#ibcon#about to write, iclass 10, count 0 2006.173.05:12:58.82#ibcon#wrote, iclass 10, count 0 2006.173.05:12:58.82#ibcon#about to read 3, iclass 10, count 0 2006.173.05:12:58.85#ibcon#read 3, iclass 10, count 0 2006.173.05:12:58.85#ibcon#about to read 4, iclass 10, count 0 2006.173.05:12:58.85#ibcon#read 4, iclass 10, count 0 2006.173.05:12:58.85#ibcon#about to read 5, iclass 10, count 0 2006.173.05:12:58.85#ibcon#read 5, iclass 10, count 0 2006.173.05:12:58.85#ibcon#about to read 6, iclass 10, count 0 2006.173.05:12:58.85#ibcon#read 6, iclass 10, count 0 2006.173.05:12:58.85#ibcon#end of sib2, iclass 10, count 0 2006.173.05:12:58.85#ibcon#*after write, iclass 10, count 0 2006.173.05:12:58.85#ibcon#*before return 0, iclass 10, count 0 2006.173.05:12:58.85#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.05:12:58.85#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.05:12:58.85#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.05:12:58.85#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.05:12:58.85$vck44/vblo=4,679.99 2006.173.05:12:58.85#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.05:12:58.85#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.05:12:58.85#ibcon#ireg 17 cls_cnt 0 2006.173.05:12:58.85#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.05:12:58.85#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.05:12:58.85#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.05:12:58.85#ibcon#enter wrdev, iclass 12, count 0 2006.173.05:12:58.85#ibcon#first serial, iclass 12, count 0 2006.173.05:12:58.85#ibcon#enter sib2, iclass 12, count 0 2006.173.05:12:58.85#ibcon#flushed, iclass 12, count 0 2006.173.05:12:58.85#ibcon#about to write, iclass 12, count 0 2006.173.05:12:58.85#ibcon#wrote, iclass 12, count 0 2006.173.05:12:58.85#ibcon#about to read 3, iclass 12, count 0 2006.173.05:12:58.87#ibcon#read 3, iclass 12, count 0 2006.173.05:12:58.87#ibcon#about to read 4, iclass 12, count 0 2006.173.05:12:58.87#ibcon#read 4, iclass 12, count 0 2006.173.05:12:58.87#ibcon#about to read 5, iclass 12, count 0 2006.173.05:12:58.87#ibcon#read 5, iclass 12, count 0 2006.173.05:12:58.87#ibcon#about to read 6, iclass 12, count 0 2006.173.05:12:58.87#ibcon#read 6, iclass 12, count 0 2006.173.05:12:58.87#ibcon#end of sib2, iclass 12, count 0 2006.173.05:12:58.87#ibcon#*mode == 0, iclass 12, count 0 2006.173.05:12:58.87#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.05:12:58.87#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.05:12:58.87#ibcon#*before write, iclass 12, count 0 2006.173.05:12:58.87#ibcon#enter sib2, iclass 12, count 0 2006.173.05:12:58.87#ibcon#flushed, iclass 12, count 0 2006.173.05:12:58.87#ibcon#about to write, iclass 12, count 0 2006.173.05:12:58.87#ibcon#wrote, iclass 12, count 0 2006.173.05:12:58.87#ibcon#about to read 3, iclass 12, count 0 2006.173.05:12:58.91#ibcon#read 3, iclass 12, count 0 2006.173.05:12:58.91#ibcon#about to read 4, iclass 12, count 0 2006.173.05:12:58.91#ibcon#read 4, iclass 12, count 0 2006.173.05:12:58.91#ibcon#about to read 5, iclass 12, count 0 2006.173.05:12:58.91#ibcon#read 5, iclass 12, count 0 2006.173.05:12:58.91#ibcon#about to read 6, iclass 12, count 0 2006.173.05:12:58.91#ibcon#read 6, iclass 12, count 0 2006.173.05:12:58.91#ibcon#end of sib2, iclass 12, count 0 2006.173.05:12:58.91#ibcon#*after write, iclass 12, count 0 2006.173.05:12:58.91#ibcon#*before return 0, iclass 12, count 0 2006.173.05:12:58.91#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.05:12:58.91#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.05:12:58.91#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.05:12:58.91#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.05:12:58.91$vck44/vb=4,4 2006.173.05:12:58.91#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.05:12:58.91#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.05:12:58.91#ibcon#ireg 11 cls_cnt 2 2006.173.05:12:58.91#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.05:12:58.97#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.05:12:58.97#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.05:12:58.97#ibcon#enter wrdev, iclass 14, count 2 2006.173.05:12:58.97#ibcon#first serial, iclass 14, count 2 2006.173.05:12:58.97#ibcon#enter sib2, iclass 14, count 2 2006.173.05:12:58.97#ibcon#flushed, iclass 14, count 2 2006.173.05:12:58.97#ibcon#about to write, iclass 14, count 2 2006.173.05:12:58.97#ibcon#wrote, iclass 14, count 2 2006.173.05:12:58.97#ibcon#about to read 3, iclass 14, count 2 2006.173.05:12:58.99#ibcon#read 3, iclass 14, count 2 2006.173.05:12:58.99#ibcon#about to read 4, iclass 14, count 2 2006.173.05:12:58.99#ibcon#read 4, iclass 14, count 2 2006.173.05:12:58.99#ibcon#about to read 5, iclass 14, count 2 2006.173.05:12:58.99#ibcon#read 5, iclass 14, count 2 2006.173.05:12:58.99#ibcon#about to read 6, iclass 14, count 2 2006.173.05:12:58.99#ibcon#read 6, iclass 14, count 2 2006.173.05:12:58.99#ibcon#end of sib2, iclass 14, count 2 2006.173.05:12:58.99#ibcon#*mode == 0, iclass 14, count 2 2006.173.05:12:58.99#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.05:12:58.99#ibcon#[27=AT04-04\r\n] 2006.173.05:12:58.99#ibcon#*before write, iclass 14, count 2 2006.173.05:12:58.99#ibcon#enter sib2, iclass 14, count 2 2006.173.05:12:58.99#ibcon#flushed, iclass 14, count 2 2006.173.05:12:58.99#ibcon#about to write, iclass 14, count 2 2006.173.05:12:58.99#ibcon#wrote, iclass 14, count 2 2006.173.05:12:58.99#ibcon#about to read 3, iclass 14, count 2 2006.173.05:12:59.02#ibcon#read 3, iclass 14, count 2 2006.173.05:12:59.02#ibcon#about to read 4, iclass 14, count 2 2006.173.05:12:59.02#ibcon#read 4, iclass 14, count 2 2006.173.05:12:59.02#ibcon#about to read 5, iclass 14, count 2 2006.173.05:12:59.02#ibcon#read 5, iclass 14, count 2 2006.173.05:12:59.02#ibcon#about to read 6, iclass 14, count 2 2006.173.05:12:59.02#ibcon#read 6, iclass 14, count 2 2006.173.05:12:59.02#ibcon#end of sib2, iclass 14, count 2 2006.173.05:12:59.02#ibcon#*after write, iclass 14, count 2 2006.173.05:12:59.02#ibcon#*before return 0, iclass 14, count 2 2006.173.05:12:59.02#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.05:12:59.02#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.05:12:59.02#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.05:12:59.02#ibcon#ireg 7 cls_cnt 0 2006.173.05:12:59.02#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.05:12:59.14#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.05:12:59.14#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.05:12:59.14#ibcon#enter wrdev, iclass 14, count 0 2006.173.05:12:59.14#ibcon#first serial, iclass 14, count 0 2006.173.05:12:59.14#ibcon#enter sib2, iclass 14, count 0 2006.173.05:12:59.14#ibcon#flushed, iclass 14, count 0 2006.173.05:12:59.14#ibcon#about to write, iclass 14, count 0 2006.173.05:12:59.14#ibcon#wrote, iclass 14, count 0 2006.173.05:12:59.14#ibcon#about to read 3, iclass 14, count 0 2006.173.05:12:59.16#ibcon#read 3, iclass 14, count 0 2006.173.05:12:59.16#ibcon#about to read 4, iclass 14, count 0 2006.173.05:12:59.16#ibcon#read 4, iclass 14, count 0 2006.173.05:12:59.16#ibcon#about to read 5, iclass 14, count 0 2006.173.05:12:59.16#ibcon#read 5, iclass 14, count 0 2006.173.05:12:59.16#ibcon#about to read 6, iclass 14, count 0 2006.173.05:12:59.16#ibcon#read 6, iclass 14, count 0 2006.173.05:12:59.16#ibcon#end of sib2, iclass 14, count 0 2006.173.05:12:59.16#ibcon#*mode == 0, iclass 14, count 0 2006.173.05:12:59.16#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.05:12:59.16#ibcon#[27=USB\r\n] 2006.173.05:12:59.16#ibcon#*before write, iclass 14, count 0 2006.173.05:12:59.16#ibcon#enter sib2, iclass 14, count 0 2006.173.05:12:59.16#ibcon#flushed, iclass 14, count 0 2006.173.05:12:59.16#ibcon#about to write, iclass 14, count 0 2006.173.05:12:59.16#ibcon#wrote, iclass 14, count 0 2006.173.05:12:59.16#ibcon#about to read 3, iclass 14, count 0 2006.173.05:12:59.19#ibcon#read 3, iclass 14, count 0 2006.173.05:12:59.19#ibcon#about to read 4, iclass 14, count 0 2006.173.05:12:59.19#ibcon#read 4, iclass 14, count 0 2006.173.05:12:59.19#ibcon#about to read 5, iclass 14, count 0 2006.173.05:12:59.19#ibcon#read 5, iclass 14, count 0 2006.173.05:12:59.19#ibcon#about to read 6, iclass 14, count 0 2006.173.05:12:59.19#ibcon#read 6, iclass 14, count 0 2006.173.05:12:59.19#ibcon#end of sib2, iclass 14, count 0 2006.173.05:12:59.19#ibcon#*after write, iclass 14, count 0 2006.173.05:12:59.19#ibcon#*before return 0, iclass 14, count 0 2006.173.05:12:59.19#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.05:12:59.19#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.05:12:59.19#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.05:12:59.19#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.05:12:59.19$vck44/vblo=5,709.99 2006.173.05:12:59.19#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.05:12:59.19#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.05:12:59.19#ibcon#ireg 17 cls_cnt 0 2006.173.05:12:59.19#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.05:12:59.19#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.05:12:59.19#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.05:12:59.19#ibcon#enter wrdev, iclass 16, count 0 2006.173.05:12:59.19#ibcon#first serial, iclass 16, count 0 2006.173.05:12:59.19#ibcon#enter sib2, iclass 16, count 0 2006.173.05:12:59.19#ibcon#flushed, iclass 16, count 0 2006.173.05:12:59.19#ibcon#about to write, iclass 16, count 0 2006.173.05:12:59.19#ibcon#wrote, iclass 16, count 0 2006.173.05:12:59.19#ibcon#about to read 3, iclass 16, count 0 2006.173.05:12:59.21#ibcon#read 3, iclass 16, count 0 2006.173.05:12:59.21#ibcon#about to read 4, iclass 16, count 0 2006.173.05:12:59.21#ibcon#read 4, iclass 16, count 0 2006.173.05:12:59.21#ibcon#about to read 5, iclass 16, count 0 2006.173.05:12:59.21#ibcon#read 5, iclass 16, count 0 2006.173.05:12:59.21#ibcon#about to read 6, iclass 16, count 0 2006.173.05:12:59.21#ibcon#read 6, iclass 16, count 0 2006.173.05:12:59.21#ibcon#end of sib2, iclass 16, count 0 2006.173.05:12:59.21#ibcon#*mode == 0, iclass 16, count 0 2006.173.05:12:59.21#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.05:12:59.21#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.05:12:59.21#ibcon#*before write, iclass 16, count 0 2006.173.05:12:59.21#ibcon#enter sib2, iclass 16, count 0 2006.173.05:12:59.21#ibcon#flushed, iclass 16, count 0 2006.173.05:12:59.21#ibcon#about to write, iclass 16, count 0 2006.173.05:12:59.21#ibcon#wrote, iclass 16, count 0 2006.173.05:12:59.21#ibcon#about to read 3, iclass 16, count 0 2006.173.05:12:59.25#ibcon#read 3, iclass 16, count 0 2006.173.05:12:59.25#ibcon#about to read 4, iclass 16, count 0 2006.173.05:12:59.25#ibcon#read 4, iclass 16, count 0 2006.173.05:12:59.25#ibcon#about to read 5, iclass 16, count 0 2006.173.05:12:59.25#ibcon#read 5, iclass 16, count 0 2006.173.05:12:59.25#ibcon#about to read 6, iclass 16, count 0 2006.173.05:12:59.25#ibcon#read 6, iclass 16, count 0 2006.173.05:12:59.25#ibcon#end of sib2, iclass 16, count 0 2006.173.05:12:59.25#ibcon#*after write, iclass 16, count 0 2006.173.05:12:59.25#ibcon#*before return 0, iclass 16, count 0 2006.173.05:12:59.25#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.05:12:59.25#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.05:12:59.25#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.05:12:59.25#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.05:12:59.25$vck44/vb=5,4 2006.173.05:12:59.25#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.05:12:59.25#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.05:12:59.25#ibcon#ireg 11 cls_cnt 2 2006.173.05:12:59.25#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.05:12:59.31#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.05:12:59.31#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.05:12:59.31#ibcon#enter wrdev, iclass 18, count 2 2006.173.05:12:59.31#ibcon#first serial, iclass 18, count 2 2006.173.05:12:59.31#ibcon#enter sib2, iclass 18, count 2 2006.173.05:12:59.31#ibcon#flushed, iclass 18, count 2 2006.173.05:12:59.31#ibcon#about to write, iclass 18, count 2 2006.173.05:12:59.31#ibcon#wrote, iclass 18, count 2 2006.173.05:12:59.31#ibcon#about to read 3, iclass 18, count 2 2006.173.05:12:59.33#ibcon#read 3, iclass 18, count 2 2006.173.05:12:59.33#ibcon#about to read 4, iclass 18, count 2 2006.173.05:12:59.33#ibcon#read 4, iclass 18, count 2 2006.173.05:12:59.33#ibcon#about to read 5, iclass 18, count 2 2006.173.05:12:59.33#ibcon#read 5, iclass 18, count 2 2006.173.05:12:59.33#ibcon#about to read 6, iclass 18, count 2 2006.173.05:12:59.33#ibcon#read 6, iclass 18, count 2 2006.173.05:12:59.33#ibcon#end of sib2, iclass 18, count 2 2006.173.05:12:59.33#ibcon#*mode == 0, iclass 18, count 2 2006.173.05:12:59.33#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.05:12:59.33#ibcon#[27=AT05-04\r\n] 2006.173.05:12:59.33#ibcon#*before write, iclass 18, count 2 2006.173.05:12:59.33#ibcon#enter sib2, iclass 18, count 2 2006.173.05:12:59.33#ibcon#flushed, iclass 18, count 2 2006.173.05:12:59.33#ibcon#about to write, iclass 18, count 2 2006.173.05:12:59.33#ibcon#wrote, iclass 18, count 2 2006.173.05:12:59.33#ibcon#about to read 3, iclass 18, count 2 2006.173.05:12:59.36#ibcon#read 3, iclass 18, count 2 2006.173.05:12:59.36#ibcon#about to read 4, iclass 18, count 2 2006.173.05:12:59.36#ibcon#read 4, iclass 18, count 2 2006.173.05:12:59.36#ibcon#about to read 5, iclass 18, count 2 2006.173.05:12:59.36#ibcon#read 5, iclass 18, count 2 2006.173.05:12:59.36#ibcon#about to read 6, iclass 18, count 2 2006.173.05:12:59.36#ibcon#read 6, iclass 18, count 2 2006.173.05:12:59.36#ibcon#end of sib2, iclass 18, count 2 2006.173.05:12:59.36#ibcon#*after write, iclass 18, count 2 2006.173.05:12:59.36#ibcon#*before return 0, iclass 18, count 2 2006.173.05:12:59.36#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.05:12:59.36#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.05:12:59.36#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.05:12:59.36#ibcon#ireg 7 cls_cnt 0 2006.173.05:12:59.36#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.05:12:59.48#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.05:12:59.48#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.05:12:59.48#ibcon#enter wrdev, iclass 18, count 0 2006.173.05:12:59.48#ibcon#first serial, iclass 18, count 0 2006.173.05:12:59.48#ibcon#enter sib2, iclass 18, count 0 2006.173.05:12:59.48#ibcon#flushed, iclass 18, count 0 2006.173.05:12:59.48#ibcon#about to write, iclass 18, count 0 2006.173.05:12:59.48#ibcon#wrote, iclass 18, count 0 2006.173.05:12:59.48#ibcon#about to read 3, iclass 18, count 0 2006.173.05:12:59.50#ibcon#read 3, iclass 18, count 0 2006.173.05:12:59.50#ibcon#about to read 4, iclass 18, count 0 2006.173.05:12:59.50#ibcon#read 4, iclass 18, count 0 2006.173.05:12:59.50#ibcon#about to read 5, iclass 18, count 0 2006.173.05:12:59.50#ibcon#read 5, iclass 18, count 0 2006.173.05:12:59.50#ibcon#about to read 6, iclass 18, count 0 2006.173.05:12:59.50#ibcon#read 6, iclass 18, count 0 2006.173.05:12:59.50#ibcon#end of sib2, iclass 18, count 0 2006.173.05:12:59.50#ibcon#*mode == 0, iclass 18, count 0 2006.173.05:12:59.50#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.05:12:59.50#ibcon#[27=USB\r\n] 2006.173.05:12:59.50#ibcon#*before write, iclass 18, count 0 2006.173.05:12:59.50#ibcon#enter sib2, iclass 18, count 0 2006.173.05:12:59.50#ibcon#flushed, iclass 18, count 0 2006.173.05:12:59.50#ibcon#about to write, iclass 18, count 0 2006.173.05:12:59.50#ibcon#wrote, iclass 18, count 0 2006.173.05:12:59.50#ibcon#about to read 3, iclass 18, count 0 2006.173.05:12:59.53#ibcon#read 3, iclass 18, count 0 2006.173.05:12:59.53#ibcon#about to read 4, iclass 18, count 0 2006.173.05:12:59.53#ibcon#read 4, iclass 18, count 0 2006.173.05:12:59.53#ibcon#about to read 5, iclass 18, count 0 2006.173.05:12:59.53#ibcon#read 5, iclass 18, count 0 2006.173.05:12:59.53#ibcon#about to read 6, iclass 18, count 0 2006.173.05:12:59.53#ibcon#read 6, iclass 18, count 0 2006.173.05:12:59.53#ibcon#end of sib2, iclass 18, count 0 2006.173.05:12:59.53#ibcon#*after write, iclass 18, count 0 2006.173.05:12:59.53#ibcon#*before return 0, iclass 18, count 0 2006.173.05:12:59.53#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.05:12:59.53#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.05:12:59.53#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.05:12:59.53#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.05:12:59.53$vck44/vblo=6,719.99 2006.173.05:12:59.53#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.05:12:59.53#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.05:12:59.53#ibcon#ireg 17 cls_cnt 0 2006.173.05:12:59.53#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.05:12:59.53#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.05:12:59.53#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.05:12:59.53#ibcon#enter wrdev, iclass 20, count 0 2006.173.05:12:59.53#ibcon#first serial, iclass 20, count 0 2006.173.05:12:59.53#ibcon#enter sib2, iclass 20, count 0 2006.173.05:12:59.53#ibcon#flushed, iclass 20, count 0 2006.173.05:12:59.53#ibcon#about to write, iclass 20, count 0 2006.173.05:12:59.53#ibcon#wrote, iclass 20, count 0 2006.173.05:12:59.53#ibcon#about to read 3, iclass 20, count 0 2006.173.05:12:59.55#ibcon#read 3, iclass 20, count 0 2006.173.05:12:59.55#ibcon#about to read 4, iclass 20, count 0 2006.173.05:12:59.55#ibcon#read 4, iclass 20, count 0 2006.173.05:12:59.55#ibcon#about to read 5, iclass 20, count 0 2006.173.05:12:59.55#ibcon#read 5, iclass 20, count 0 2006.173.05:12:59.55#ibcon#about to read 6, iclass 20, count 0 2006.173.05:12:59.55#ibcon#read 6, iclass 20, count 0 2006.173.05:12:59.55#ibcon#end of sib2, iclass 20, count 0 2006.173.05:12:59.55#ibcon#*mode == 0, iclass 20, count 0 2006.173.05:12:59.55#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.05:12:59.55#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.05:12:59.55#ibcon#*before write, iclass 20, count 0 2006.173.05:12:59.55#ibcon#enter sib2, iclass 20, count 0 2006.173.05:12:59.55#ibcon#flushed, iclass 20, count 0 2006.173.05:12:59.55#ibcon#about to write, iclass 20, count 0 2006.173.05:12:59.55#ibcon#wrote, iclass 20, count 0 2006.173.05:12:59.55#ibcon#about to read 3, iclass 20, count 0 2006.173.05:12:59.59#ibcon#read 3, iclass 20, count 0 2006.173.05:12:59.59#ibcon#about to read 4, iclass 20, count 0 2006.173.05:12:59.59#ibcon#read 4, iclass 20, count 0 2006.173.05:12:59.59#ibcon#about to read 5, iclass 20, count 0 2006.173.05:12:59.59#ibcon#read 5, iclass 20, count 0 2006.173.05:12:59.59#ibcon#about to read 6, iclass 20, count 0 2006.173.05:12:59.59#ibcon#read 6, iclass 20, count 0 2006.173.05:12:59.59#ibcon#end of sib2, iclass 20, count 0 2006.173.05:12:59.59#ibcon#*after write, iclass 20, count 0 2006.173.05:12:59.59#ibcon#*before return 0, iclass 20, count 0 2006.173.05:12:59.59#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.05:12:59.59#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.05:12:59.59#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.05:12:59.59#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.05:12:59.59$vck44/vb=6,4 2006.173.05:12:59.59#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.05:12:59.59#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.05:12:59.59#ibcon#ireg 11 cls_cnt 2 2006.173.05:12:59.59#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.05:12:59.65#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.05:12:59.65#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.05:12:59.65#ibcon#enter wrdev, iclass 22, count 2 2006.173.05:12:59.65#ibcon#first serial, iclass 22, count 2 2006.173.05:12:59.65#ibcon#enter sib2, iclass 22, count 2 2006.173.05:12:59.65#ibcon#flushed, iclass 22, count 2 2006.173.05:12:59.65#ibcon#about to write, iclass 22, count 2 2006.173.05:12:59.65#ibcon#wrote, iclass 22, count 2 2006.173.05:12:59.65#ibcon#about to read 3, iclass 22, count 2 2006.173.05:12:59.67#ibcon#read 3, iclass 22, count 2 2006.173.05:12:59.67#ibcon#about to read 4, iclass 22, count 2 2006.173.05:12:59.67#ibcon#read 4, iclass 22, count 2 2006.173.05:12:59.67#ibcon#about to read 5, iclass 22, count 2 2006.173.05:12:59.67#ibcon#read 5, iclass 22, count 2 2006.173.05:12:59.67#ibcon#about to read 6, iclass 22, count 2 2006.173.05:12:59.67#ibcon#read 6, iclass 22, count 2 2006.173.05:12:59.67#ibcon#end of sib2, iclass 22, count 2 2006.173.05:12:59.67#ibcon#*mode == 0, iclass 22, count 2 2006.173.05:12:59.67#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.05:12:59.67#ibcon#[27=AT06-04\r\n] 2006.173.05:12:59.67#ibcon#*before write, iclass 22, count 2 2006.173.05:12:59.67#ibcon#enter sib2, iclass 22, count 2 2006.173.05:12:59.67#ibcon#flushed, iclass 22, count 2 2006.173.05:12:59.67#ibcon#about to write, iclass 22, count 2 2006.173.05:12:59.67#ibcon#wrote, iclass 22, count 2 2006.173.05:12:59.67#ibcon#about to read 3, iclass 22, count 2 2006.173.05:12:59.70#ibcon#read 3, iclass 22, count 2 2006.173.05:12:59.70#ibcon#about to read 4, iclass 22, count 2 2006.173.05:12:59.70#ibcon#read 4, iclass 22, count 2 2006.173.05:12:59.70#ibcon#about to read 5, iclass 22, count 2 2006.173.05:12:59.70#ibcon#read 5, iclass 22, count 2 2006.173.05:12:59.70#ibcon#about to read 6, iclass 22, count 2 2006.173.05:12:59.70#ibcon#read 6, iclass 22, count 2 2006.173.05:12:59.70#ibcon#end of sib2, iclass 22, count 2 2006.173.05:12:59.70#ibcon#*after write, iclass 22, count 2 2006.173.05:12:59.70#ibcon#*before return 0, iclass 22, count 2 2006.173.05:12:59.70#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.05:12:59.70#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.05:12:59.70#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.05:12:59.70#ibcon#ireg 7 cls_cnt 0 2006.173.05:12:59.70#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.05:12:59.82#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.05:12:59.82#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.05:12:59.82#ibcon#enter wrdev, iclass 22, count 0 2006.173.05:12:59.82#ibcon#first serial, iclass 22, count 0 2006.173.05:12:59.82#ibcon#enter sib2, iclass 22, count 0 2006.173.05:12:59.82#ibcon#flushed, iclass 22, count 0 2006.173.05:12:59.82#ibcon#about to write, iclass 22, count 0 2006.173.05:12:59.82#ibcon#wrote, iclass 22, count 0 2006.173.05:12:59.82#ibcon#about to read 3, iclass 22, count 0 2006.173.05:12:59.84#ibcon#read 3, iclass 22, count 0 2006.173.05:12:59.84#ibcon#about to read 4, iclass 22, count 0 2006.173.05:12:59.84#ibcon#read 4, iclass 22, count 0 2006.173.05:12:59.84#ibcon#about to read 5, iclass 22, count 0 2006.173.05:12:59.84#ibcon#read 5, iclass 22, count 0 2006.173.05:12:59.84#ibcon#about to read 6, iclass 22, count 0 2006.173.05:12:59.84#ibcon#read 6, iclass 22, count 0 2006.173.05:12:59.84#ibcon#end of sib2, iclass 22, count 0 2006.173.05:12:59.84#ibcon#*mode == 0, iclass 22, count 0 2006.173.05:12:59.84#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.05:12:59.84#ibcon#[27=USB\r\n] 2006.173.05:12:59.84#ibcon#*before write, iclass 22, count 0 2006.173.05:12:59.84#ibcon#enter sib2, iclass 22, count 0 2006.173.05:12:59.84#ibcon#flushed, iclass 22, count 0 2006.173.05:12:59.84#ibcon#about to write, iclass 22, count 0 2006.173.05:12:59.84#ibcon#wrote, iclass 22, count 0 2006.173.05:12:59.84#ibcon#about to read 3, iclass 22, count 0 2006.173.05:12:59.87#ibcon#read 3, iclass 22, count 0 2006.173.05:12:59.87#ibcon#about to read 4, iclass 22, count 0 2006.173.05:12:59.87#ibcon#read 4, iclass 22, count 0 2006.173.05:12:59.87#ibcon#about to read 5, iclass 22, count 0 2006.173.05:12:59.87#ibcon#read 5, iclass 22, count 0 2006.173.05:12:59.87#ibcon#about to read 6, iclass 22, count 0 2006.173.05:12:59.87#ibcon#read 6, iclass 22, count 0 2006.173.05:12:59.87#ibcon#end of sib2, iclass 22, count 0 2006.173.05:12:59.87#ibcon#*after write, iclass 22, count 0 2006.173.05:12:59.87#ibcon#*before return 0, iclass 22, count 0 2006.173.05:12:59.87#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.05:12:59.87#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.05:12:59.87#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.05:12:59.87#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.05:12:59.87$vck44/vblo=7,734.99 2006.173.05:12:59.87#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.05:12:59.87#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.05:12:59.87#ibcon#ireg 17 cls_cnt 0 2006.173.05:12:59.87#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.05:12:59.87#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.05:12:59.87#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.05:12:59.87#ibcon#enter wrdev, iclass 24, count 0 2006.173.05:12:59.87#ibcon#first serial, iclass 24, count 0 2006.173.05:12:59.87#ibcon#enter sib2, iclass 24, count 0 2006.173.05:12:59.87#ibcon#flushed, iclass 24, count 0 2006.173.05:12:59.87#ibcon#about to write, iclass 24, count 0 2006.173.05:12:59.87#ibcon#wrote, iclass 24, count 0 2006.173.05:12:59.87#ibcon#about to read 3, iclass 24, count 0 2006.173.05:12:59.89#ibcon#read 3, iclass 24, count 0 2006.173.05:12:59.89#ibcon#about to read 4, iclass 24, count 0 2006.173.05:12:59.89#ibcon#read 4, iclass 24, count 0 2006.173.05:12:59.89#ibcon#about to read 5, iclass 24, count 0 2006.173.05:12:59.89#ibcon#read 5, iclass 24, count 0 2006.173.05:12:59.89#ibcon#about to read 6, iclass 24, count 0 2006.173.05:12:59.89#ibcon#read 6, iclass 24, count 0 2006.173.05:12:59.89#ibcon#end of sib2, iclass 24, count 0 2006.173.05:12:59.89#ibcon#*mode == 0, iclass 24, count 0 2006.173.05:12:59.89#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.05:12:59.89#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.05:12:59.89#ibcon#*before write, iclass 24, count 0 2006.173.05:12:59.89#ibcon#enter sib2, iclass 24, count 0 2006.173.05:12:59.89#ibcon#flushed, iclass 24, count 0 2006.173.05:12:59.89#ibcon#about to write, iclass 24, count 0 2006.173.05:12:59.89#ibcon#wrote, iclass 24, count 0 2006.173.05:12:59.89#ibcon#about to read 3, iclass 24, count 0 2006.173.05:12:59.93#ibcon#read 3, iclass 24, count 0 2006.173.05:12:59.93#ibcon#about to read 4, iclass 24, count 0 2006.173.05:12:59.93#ibcon#read 4, iclass 24, count 0 2006.173.05:12:59.93#ibcon#about to read 5, iclass 24, count 0 2006.173.05:12:59.93#ibcon#read 5, iclass 24, count 0 2006.173.05:12:59.93#ibcon#about to read 6, iclass 24, count 0 2006.173.05:12:59.93#ibcon#read 6, iclass 24, count 0 2006.173.05:12:59.93#ibcon#end of sib2, iclass 24, count 0 2006.173.05:12:59.93#ibcon#*after write, iclass 24, count 0 2006.173.05:12:59.93#ibcon#*before return 0, iclass 24, count 0 2006.173.05:12:59.93#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.05:12:59.93#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.05:12:59.93#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.05:12:59.93#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.05:12:59.93$vck44/vb=7,4 2006.173.05:12:59.93#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.05:12:59.93#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.05:12:59.93#ibcon#ireg 11 cls_cnt 2 2006.173.05:12:59.93#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.05:12:59.99#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.05:12:59.99#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.05:12:59.99#ibcon#enter wrdev, iclass 26, count 2 2006.173.05:12:59.99#ibcon#first serial, iclass 26, count 2 2006.173.05:12:59.99#ibcon#enter sib2, iclass 26, count 2 2006.173.05:12:59.99#ibcon#flushed, iclass 26, count 2 2006.173.05:12:59.99#ibcon#about to write, iclass 26, count 2 2006.173.05:12:59.99#ibcon#wrote, iclass 26, count 2 2006.173.05:12:59.99#ibcon#about to read 3, iclass 26, count 2 2006.173.05:13:00.01#ibcon#read 3, iclass 26, count 2 2006.173.05:13:00.01#ibcon#about to read 4, iclass 26, count 2 2006.173.05:13:00.01#ibcon#read 4, iclass 26, count 2 2006.173.05:13:00.01#ibcon#about to read 5, iclass 26, count 2 2006.173.05:13:00.01#ibcon#read 5, iclass 26, count 2 2006.173.05:13:00.01#ibcon#about to read 6, iclass 26, count 2 2006.173.05:13:00.01#ibcon#read 6, iclass 26, count 2 2006.173.05:13:00.01#ibcon#end of sib2, iclass 26, count 2 2006.173.05:13:00.01#ibcon#*mode == 0, iclass 26, count 2 2006.173.05:13:00.01#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.05:13:00.01#ibcon#[27=AT07-04\r\n] 2006.173.05:13:00.01#ibcon#*before write, iclass 26, count 2 2006.173.05:13:00.01#ibcon#enter sib2, iclass 26, count 2 2006.173.05:13:00.01#ibcon#flushed, iclass 26, count 2 2006.173.05:13:00.01#ibcon#about to write, iclass 26, count 2 2006.173.05:13:00.01#ibcon#wrote, iclass 26, count 2 2006.173.05:13:00.01#ibcon#about to read 3, iclass 26, count 2 2006.173.05:13:00.04#ibcon#read 3, iclass 26, count 2 2006.173.05:13:00.04#ibcon#about to read 4, iclass 26, count 2 2006.173.05:13:00.04#ibcon#read 4, iclass 26, count 2 2006.173.05:13:00.04#ibcon#about to read 5, iclass 26, count 2 2006.173.05:13:00.04#ibcon#read 5, iclass 26, count 2 2006.173.05:13:00.04#ibcon#about to read 6, iclass 26, count 2 2006.173.05:13:00.04#ibcon#read 6, iclass 26, count 2 2006.173.05:13:00.04#ibcon#end of sib2, iclass 26, count 2 2006.173.05:13:00.04#ibcon#*after write, iclass 26, count 2 2006.173.05:13:00.04#ibcon#*before return 0, iclass 26, count 2 2006.173.05:13:00.04#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.05:13:00.04#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.05:13:00.04#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.05:13:00.04#ibcon#ireg 7 cls_cnt 0 2006.173.05:13:00.04#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.05:13:00.16#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.05:13:00.16#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.05:13:00.16#ibcon#enter wrdev, iclass 26, count 0 2006.173.05:13:00.16#ibcon#first serial, iclass 26, count 0 2006.173.05:13:00.16#ibcon#enter sib2, iclass 26, count 0 2006.173.05:13:00.16#ibcon#flushed, iclass 26, count 0 2006.173.05:13:00.16#ibcon#about to write, iclass 26, count 0 2006.173.05:13:00.16#ibcon#wrote, iclass 26, count 0 2006.173.05:13:00.16#ibcon#about to read 3, iclass 26, count 0 2006.173.05:13:00.18#ibcon#read 3, iclass 26, count 0 2006.173.05:13:00.18#ibcon#about to read 4, iclass 26, count 0 2006.173.05:13:00.18#ibcon#read 4, iclass 26, count 0 2006.173.05:13:00.18#ibcon#about to read 5, iclass 26, count 0 2006.173.05:13:00.18#ibcon#read 5, iclass 26, count 0 2006.173.05:13:00.18#ibcon#about to read 6, iclass 26, count 0 2006.173.05:13:00.18#ibcon#read 6, iclass 26, count 0 2006.173.05:13:00.18#ibcon#end of sib2, iclass 26, count 0 2006.173.05:13:00.18#ibcon#*mode == 0, iclass 26, count 0 2006.173.05:13:00.18#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.05:13:00.18#ibcon#[27=USB\r\n] 2006.173.05:13:00.18#ibcon#*before write, iclass 26, count 0 2006.173.05:13:00.18#ibcon#enter sib2, iclass 26, count 0 2006.173.05:13:00.18#ibcon#flushed, iclass 26, count 0 2006.173.05:13:00.18#ibcon#about to write, iclass 26, count 0 2006.173.05:13:00.18#ibcon#wrote, iclass 26, count 0 2006.173.05:13:00.18#ibcon#about to read 3, iclass 26, count 0 2006.173.05:13:00.21#ibcon#read 3, iclass 26, count 0 2006.173.05:13:00.21#ibcon#about to read 4, iclass 26, count 0 2006.173.05:13:00.21#ibcon#read 4, iclass 26, count 0 2006.173.05:13:00.21#ibcon#about to read 5, iclass 26, count 0 2006.173.05:13:00.21#ibcon#read 5, iclass 26, count 0 2006.173.05:13:00.21#ibcon#about to read 6, iclass 26, count 0 2006.173.05:13:00.21#ibcon#read 6, iclass 26, count 0 2006.173.05:13:00.21#ibcon#end of sib2, iclass 26, count 0 2006.173.05:13:00.21#ibcon#*after write, iclass 26, count 0 2006.173.05:13:00.21#ibcon#*before return 0, iclass 26, count 0 2006.173.05:13:00.21#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.05:13:00.21#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.05:13:00.21#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.05:13:00.21#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.05:13:00.21$vck44/vblo=8,744.99 2006.173.05:13:00.21#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.05:13:00.21#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.05:13:00.21#ibcon#ireg 17 cls_cnt 0 2006.173.05:13:00.21#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.05:13:00.21#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.05:13:00.21#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.05:13:00.21#ibcon#enter wrdev, iclass 28, count 0 2006.173.05:13:00.21#ibcon#first serial, iclass 28, count 0 2006.173.05:13:00.21#ibcon#enter sib2, iclass 28, count 0 2006.173.05:13:00.21#ibcon#flushed, iclass 28, count 0 2006.173.05:13:00.21#ibcon#about to write, iclass 28, count 0 2006.173.05:13:00.21#ibcon#wrote, iclass 28, count 0 2006.173.05:13:00.21#ibcon#about to read 3, iclass 28, count 0 2006.173.05:13:00.23#ibcon#read 3, iclass 28, count 0 2006.173.05:13:00.23#ibcon#about to read 4, iclass 28, count 0 2006.173.05:13:00.23#ibcon#read 4, iclass 28, count 0 2006.173.05:13:00.23#ibcon#about to read 5, iclass 28, count 0 2006.173.05:13:00.23#ibcon#read 5, iclass 28, count 0 2006.173.05:13:00.23#ibcon#about to read 6, iclass 28, count 0 2006.173.05:13:00.23#ibcon#read 6, iclass 28, count 0 2006.173.05:13:00.23#ibcon#end of sib2, iclass 28, count 0 2006.173.05:13:00.23#ibcon#*mode == 0, iclass 28, count 0 2006.173.05:13:00.23#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.05:13:00.23#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.05:13:00.23#ibcon#*before write, iclass 28, count 0 2006.173.05:13:00.23#ibcon#enter sib2, iclass 28, count 0 2006.173.05:13:00.23#ibcon#flushed, iclass 28, count 0 2006.173.05:13:00.23#ibcon#about to write, iclass 28, count 0 2006.173.05:13:00.23#ibcon#wrote, iclass 28, count 0 2006.173.05:13:00.23#ibcon#about to read 3, iclass 28, count 0 2006.173.05:13:00.27#ibcon#read 3, iclass 28, count 0 2006.173.05:13:00.27#ibcon#about to read 4, iclass 28, count 0 2006.173.05:13:00.27#ibcon#read 4, iclass 28, count 0 2006.173.05:13:00.27#ibcon#about to read 5, iclass 28, count 0 2006.173.05:13:00.27#ibcon#read 5, iclass 28, count 0 2006.173.05:13:00.27#ibcon#about to read 6, iclass 28, count 0 2006.173.05:13:00.27#ibcon#read 6, iclass 28, count 0 2006.173.05:13:00.27#ibcon#end of sib2, iclass 28, count 0 2006.173.05:13:00.27#ibcon#*after write, iclass 28, count 0 2006.173.05:13:00.27#ibcon#*before return 0, iclass 28, count 0 2006.173.05:13:00.27#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.05:13:00.27#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.05:13:00.27#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.05:13:00.27#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.05:13:00.27$vck44/vb=8,4 2006.173.05:13:00.27#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.05:13:00.27#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.05:13:00.27#ibcon#ireg 11 cls_cnt 2 2006.173.05:13:00.27#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.05:13:00.33#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.05:13:00.33#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.05:13:00.33#ibcon#enter wrdev, iclass 30, count 2 2006.173.05:13:00.33#ibcon#first serial, iclass 30, count 2 2006.173.05:13:00.33#ibcon#enter sib2, iclass 30, count 2 2006.173.05:13:00.33#ibcon#flushed, iclass 30, count 2 2006.173.05:13:00.33#ibcon#about to write, iclass 30, count 2 2006.173.05:13:00.33#ibcon#wrote, iclass 30, count 2 2006.173.05:13:00.33#ibcon#about to read 3, iclass 30, count 2 2006.173.05:13:00.35#ibcon#read 3, iclass 30, count 2 2006.173.05:13:00.35#ibcon#about to read 4, iclass 30, count 2 2006.173.05:13:00.35#ibcon#read 4, iclass 30, count 2 2006.173.05:13:00.35#ibcon#about to read 5, iclass 30, count 2 2006.173.05:13:00.35#ibcon#read 5, iclass 30, count 2 2006.173.05:13:00.35#ibcon#about to read 6, iclass 30, count 2 2006.173.05:13:00.35#ibcon#read 6, iclass 30, count 2 2006.173.05:13:00.35#ibcon#end of sib2, iclass 30, count 2 2006.173.05:13:00.35#ibcon#*mode == 0, iclass 30, count 2 2006.173.05:13:00.35#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.05:13:00.35#ibcon#[27=AT08-04\r\n] 2006.173.05:13:00.35#ibcon#*before write, iclass 30, count 2 2006.173.05:13:00.35#ibcon#enter sib2, iclass 30, count 2 2006.173.05:13:00.35#ibcon#flushed, iclass 30, count 2 2006.173.05:13:00.35#ibcon#about to write, iclass 30, count 2 2006.173.05:13:00.35#ibcon#wrote, iclass 30, count 2 2006.173.05:13:00.35#ibcon#about to read 3, iclass 30, count 2 2006.173.05:13:00.38#ibcon#read 3, iclass 30, count 2 2006.173.05:13:00.38#ibcon#about to read 4, iclass 30, count 2 2006.173.05:13:00.38#ibcon#read 4, iclass 30, count 2 2006.173.05:13:00.38#ibcon#about to read 5, iclass 30, count 2 2006.173.05:13:00.38#ibcon#read 5, iclass 30, count 2 2006.173.05:13:00.38#ibcon#about to read 6, iclass 30, count 2 2006.173.05:13:00.38#ibcon#read 6, iclass 30, count 2 2006.173.05:13:00.38#ibcon#end of sib2, iclass 30, count 2 2006.173.05:13:00.38#ibcon#*after write, iclass 30, count 2 2006.173.05:13:00.38#ibcon#*before return 0, iclass 30, count 2 2006.173.05:13:00.38#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.05:13:00.38#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.05:13:00.38#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.05:13:00.38#ibcon#ireg 7 cls_cnt 0 2006.173.05:13:00.38#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.05:13:00.50#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.05:13:00.50#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.05:13:00.50#ibcon#enter wrdev, iclass 30, count 0 2006.173.05:13:00.50#ibcon#first serial, iclass 30, count 0 2006.173.05:13:00.50#ibcon#enter sib2, iclass 30, count 0 2006.173.05:13:00.50#ibcon#flushed, iclass 30, count 0 2006.173.05:13:00.50#ibcon#about to write, iclass 30, count 0 2006.173.05:13:00.50#ibcon#wrote, iclass 30, count 0 2006.173.05:13:00.50#ibcon#about to read 3, iclass 30, count 0 2006.173.05:13:00.52#ibcon#read 3, iclass 30, count 0 2006.173.05:13:00.52#ibcon#about to read 4, iclass 30, count 0 2006.173.05:13:00.52#ibcon#read 4, iclass 30, count 0 2006.173.05:13:00.52#ibcon#about to read 5, iclass 30, count 0 2006.173.05:13:00.52#ibcon#read 5, iclass 30, count 0 2006.173.05:13:00.52#ibcon#about to read 6, iclass 30, count 0 2006.173.05:13:00.52#ibcon#read 6, iclass 30, count 0 2006.173.05:13:00.52#ibcon#end of sib2, iclass 30, count 0 2006.173.05:13:00.52#ibcon#*mode == 0, iclass 30, count 0 2006.173.05:13:00.52#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.05:13:00.52#ibcon#[27=USB\r\n] 2006.173.05:13:00.52#ibcon#*before write, iclass 30, count 0 2006.173.05:13:00.52#ibcon#enter sib2, iclass 30, count 0 2006.173.05:13:00.52#ibcon#flushed, iclass 30, count 0 2006.173.05:13:00.52#ibcon#about to write, iclass 30, count 0 2006.173.05:13:00.52#ibcon#wrote, iclass 30, count 0 2006.173.05:13:00.52#ibcon#about to read 3, iclass 30, count 0 2006.173.05:13:00.55#ibcon#read 3, iclass 30, count 0 2006.173.05:13:00.55#ibcon#about to read 4, iclass 30, count 0 2006.173.05:13:00.55#ibcon#read 4, iclass 30, count 0 2006.173.05:13:00.55#ibcon#about to read 5, iclass 30, count 0 2006.173.05:13:00.55#ibcon#read 5, iclass 30, count 0 2006.173.05:13:00.55#ibcon#about to read 6, iclass 30, count 0 2006.173.05:13:00.55#ibcon#read 6, iclass 30, count 0 2006.173.05:13:00.55#ibcon#end of sib2, iclass 30, count 0 2006.173.05:13:00.55#ibcon#*after write, iclass 30, count 0 2006.173.05:13:00.55#ibcon#*before return 0, iclass 30, count 0 2006.173.05:13:00.55#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.05:13:00.55#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.05:13:00.55#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.05:13:00.55#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.05:13:00.55$vck44/vabw=wide 2006.173.05:13:00.55#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.05:13:00.55#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.05:13:00.55#ibcon#ireg 8 cls_cnt 0 2006.173.05:13:00.55#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.05:13:00.55#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.05:13:00.55#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.05:13:00.55#ibcon#enter wrdev, iclass 32, count 0 2006.173.05:13:00.55#ibcon#first serial, iclass 32, count 0 2006.173.05:13:00.55#ibcon#enter sib2, iclass 32, count 0 2006.173.05:13:00.55#ibcon#flushed, iclass 32, count 0 2006.173.05:13:00.55#ibcon#about to write, iclass 32, count 0 2006.173.05:13:00.55#ibcon#wrote, iclass 32, count 0 2006.173.05:13:00.55#ibcon#about to read 3, iclass 32, count 0 2006.173.05:13:00.57#ibcon#read 3, iclass 32, count 0 2006.173.05:13:00.57#ibcon#about to read 4, iclass 32, count 0 2006.173.05:13:00.57#ibcon#read 4, iclass 32, count 0 2006.173.05:13:00.57#ibcon#about to read 5, iclass 32, count 0 2006.173.05:13:00.57#ibcon#read 5, iclass 32, count 0 2006.173.05:13:00.57#ibcon#about to read 6, iclass 32, count 0 2006.173.05:13:00.57#ibcon#read 6, iclass 32, count 0 2006.173.05:13:00.57#ibcon#end of sib2, iclass 32, count 0 2006.173.05:13:00.57#ibcon#*mode == 0, iclass 32, count 0 2006.173.05:13:00.57#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.05:13:00.57#ibcon#[25=BW32\r\n] 2006.173.05:13:00.57#ibcon#*before write, iclass 32, count 0 2006.173.05:13:00.57#ibcon#enter sib2, iclass 32, count 0 2006.173.05:13:00.57#ibcon#flushed, iclass 32, count 0 2006.173.05:13:00.57#ibcon#about to write, iclass 32, count 0 2006.173.05:13:00.57#ibcon#wrote, iclass 32, count 0 2006.173.05:13:00.57#ibcon#about to read 3, iclass 32, count 0 2006.173.05:13:00.60#ibcon#read 3, iclass 32, count 0 2006.173.05:13:00.60#ibcon#about to read 4, iclass 32, count 0 2006.173.05:13:00.60#ibcon#read 4, iclass 32, count 0 2006.173.05:13:00.60#ibcon#about to read 5, iclass 32, count 0 2006.173.05:13:00.60#ibcon#read 5, iclass 32, count 0 2006.173.05:13:00.60#ibcon#about to read 6, iclass 32, count 0 2006.173.05:13:00.60#ibcon#read 6, iclass 32, count 0 2006.173.05:13:00.60#ibcon#end of sib2, iclass 32, count 0 2006.173.05:13:00.60#ibcon#*after write, iclass 32, count 0 2006.173.05:13:00.60#ibcon#*before return 0, iclass 32, count 0 2006.173.05:13:00.60#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.05:13:00.60#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.05:13:00.60#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.05:13:00.60#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.05:13:00.60$vck44/vbbw=wide 2006.173.05:13:00.60#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.05:13:00.60#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.05:13:00.60#ibcon#ireg 8 cls_cnt 0 2006.173.05:13:00.60#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.05:13:00.67#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.05:13:00.67#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.05:13:00.67#ibcon#enter wrdev, iclass 34, count 0 2006.173.05:13:00.67#ibcon#first serial, iclass 34, count 0 2006.173.05:13:00.67#ibcon#enter sib2, iclass 34, count 0 2006.173.05:13:00.67#ibcon#flushed, iclass 34, count 0 2006.173.05:13:00.67#ibcon#about to write, iclass 34, count 0 2006.173.05:13:00.67#ibcon#wrote, iclass 34, count 0 2006.173.05:13:00.67#ibcon#about to read 3, iclass 34, count 0 2006.173.05:13:00.69#ibcon#read 3, iclass 34, count 0 2006.173.05:13:00.69#ibcon#about to read 4, iclass 34, count 0 2006.173.05:13:00.69#ibcon#read 4, iclass 34, count 0 2006.173.05:13:00.69#ibcon#about to read 5, iclass 34, count 0 2006.173.05:13:00.69#ibcon#read 5, iclass 34, count 0 2006.173.05:13:00.69#ibcon#about to read 6, iclass 34, count 0 2006.173.05:13:00.69#ibcon#read 6, iclass 34, count 0 2006.173.05:13:00.69#ibcon#end of sib2, iclass 34, count 0 2006.173.05:13:00.69#ibcon#*mode == 0, iclass 34, count 0 2006.173.05:13:00.69#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.05:13:00.69#ibcon#[27=BW32\r\n] 2006.173.05:13:00.69#ibcon#*before write, iclass 34, count 0 2006.173.05:13:00.69#ibcon#enter sib2, iclass 34, count 0 2006.173.05:13:00.69#ibcon#flushed, iclass 34, count 0 2006.173.05:13:00.69#ibcon#about to write, iclass 34, count 0 2006.173.05:13:00.69#ibcon#wrote, iclass 34, count 0 2006.173.05:13:00.69#ibcon#about to read 3, iclass 34, count 0 2006.173.05:13:00.72#ibcon#read 3, iclass 34, count 0 2006.173.05:13:00.72#ibcon#about to read 4, iclass 34, count 0 2006.173.05:13:00.72#ibcon#read 4, iclass 34, count 0 2006.173.05:13:00.72#ibcon#about to read 5, iclass 34, count 0 2006.173.05:13:00.72#ibcon#read 5, iclass 34, count 0 2006.173.05:13:00.72#ibcon#about to read 6, iclass 34, count 0 2006.173.05:13:00.72#ibcon#read 6, iclass 34, count 0 2006.173.05:13:00.72#ibcon#end of sib2, iclass 34, count 0 2006.173.05:13:00.72#ibcon#*after write, iclass 34, count 0 2006.173.05:13:00.72#ibcon#*before return 0, iclass 34, count 0 2006.173.05:13:00.72#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.05:13:00.72#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.05:13:00.72#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.05:13:00.72#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.05:13:00.72$setupk4/ifdk4 2006.173.05:13:00.72$ifdk4/lo= 2006.173.05:13:00.72$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.05:13:00.72$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.05:13:00.72$ifdk4/patch= 2006.173.05:13:00.72$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.05:13:00.72$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.05:13:00.72$setupk4/!*+20s 2006.173.05:13:06.69#abcon#<5=/15 1.1 1.9 23.50 781005.6\r\n> 2006.173.05:13:06.71#abcon#{5=INTERFACE CLEAR} 2006.173.05:13:06.77#abcon#[5=S1D000X0/0*\r\n] 2006.173.05:13:15.23$setupk4/"tpicd 2006.173.05:13:15.23$setupk4/echo=off 2006.173.05:13:15.23$setupk4/xlog=off 2006.173.05:13:15.23:!2006.173.05:17:22 2006.173.05:13:24.13#trakl#Source acquired 2006.173.05:13:26.13#flagr#flagr/antenna,acquired 2006.173.05:17:22.02:preob 2006.173.05:17:23.14/onsource/TRACKING 2006.173.05:17:23.14:!2006.173.05:17:32 2006.173.05:17:32.01:"tape 2006.173.05:17:32.02:"st=record 2006.173.05:17:32.02:data_valid=on 2006.173.05:17:32.02:midob 2006.173.05:17:33.15/onsource/TRACKING 2006.173.05:17:33.15/wx/23.47,1005.7,78 2006.173.05:17:33.33/cable/+6.5058E-03 2006.173.05:17:34.42/va/01,07,usb,yes,34,37 2006.173.05:17:34.42/va/02,06,usb,yes,34,35 2006.173.05:17:34.42/va/03,05,usb,yes,43,45 2006.173.05:17:34.42/va/04,06,usb,yes,35,37 2006.173.05:17:34.42/va/05,04,usb,yes,27,28 2006.173.05:17:34.42/va/06,03,usb,yes,38,38 2006.173.05:17:34.42/va/07,04,usb,yes,31,32 2006.173.05:17:34.42/va/08,04,usb,yes,26,32 2006.173.05:17:34.65/valo/01,524.99,yes,locked 2006.173.05:17:34.65/valo/02,534.99,yes,locked 2006.173.05:17:34.65/valo/03,564.99,yes,locked 2006.173.05:17:34.65/valo/04,624.99,yes,locked 2006.173.05:17:34.65/valo/05,734.99,yes,locked 2006.173.05:17:34.65/valo/06,814.99,yes,locked 2006.173.05:17:34.65/valo/07,864.99,yes,locked 2006.173.05:17:34.65/valo/08,884.99,yes,locked 2006.173.05:17:35.74/vb/01,04,usb,yes,29,27 2006.173.05:17:35.74/vb/02,04,usb,yes,31,31 2006.173.05:17:35.74/vb/03,04,usb,yes,28,31 2006.173.05:17:35.74/vb/04,04,usb,yes,32,31 2006.173.05:17:35.74/vb/05,04,usb,yes,25,27 2006.173.05:17:35.74/vb/06,04,usb,yes,29,26 2006.173.05:17:35.74/vb/07,04,usb,yes,29,29 2006.173.05:17:35.74/vb/08,04,usb,yes,27,30 2006.173.05:17:35.98/vblo/01,629.99,yes,locked 2006.173.05:17:35.98/vblo/02,634.99,yes,locked 2006.173.05:17:35.98/vblo/03,649.99,yes,locked 2006.173.05:17:35.98/vblo/04,679.99,yes,locked 2006.173.05:17:35.98/vblo/05,709.99,yes,locked 2006.173.05:17:35.98/vblo/06,719.99,yes,locked 2006.173.05:17:35.98/vblo/07,734.99,yes,locked 2006.173.05:17:35.98/vblo/08,744.99,yes,locked 2006.173.05:17:36.12/vabw/8 2006.173.05:17:36.27/vbbw/8 2006.173.05:17:36.37/xfe/off,on,15.5 2006.173.05:17:36.75/ifatt/23,28,28,28 2006.173.05:17:37.07/fmout-gps/S +3.98E-07 2006.173.05:17:37.12:!2006.173.05:21:12 2006.173.05:21:12.01:data_valid=off 2006.173.05:21:12.02:"et 2006.173.05:21:12.02:!+3s 2006.173.05:21:15.04:"tape 2006.173.05:21:15.04:postob 2006.173.05:21:15.12/cable/+6.5056E-03 2006.173.05:21:15.12/wx/23.50,1005.6,80 2006.173.05:21:15.18/fmout-gps/S +3.98E-07 2006.173.05:21:15.18:scan_name=173-0524,jd0606,260 2006.173.05:21:15.19:source=0059+581,010245.76,582411.1,2000.0,ccw 2006.173.05:21:16.13#flagr#flagr/antenna,new-source 2006.173.05:21:16.14:checkk5 2006.173.05:21:16.51/chk_autoobs//k5ts1/ autoobs is running! 2006.173.05:21:16.91/chk_autoobs//k5ts2/ autoobs is running! 2006.173.05:21:17.34/chk_autoobs//k5ts3/ autoobs is running! 2006.173.05:21:17.74/chk_autoobs//k5ts4/ autoobs is running! 2006.173.05:21:18.11/chk_obsdata//k5ts1/T1730517??a.dat file size is correct (nominal:880MB, actual:876MB). 2006.173.05:21:18.50/chk_obsdata//k5ts2/T1730517??b.dat file size is correct (nominal:880MB, actual:876MB). 2006.173.05:21:18.88/chk_obsdata//k5ts3/T1730517??c.dat file size is correct (nominal:880MB, actual:876MB). 2006.173.05:21:19.29/chk_obsdata//k5ts4/T1730517??d.dat file size is correct (nominal:880MB, actual:876MB). 2006.173.05:21:20.01/k5log//k5ts1_log_newline 2006.173.05:21:20.73/k5log//k5ts2_log_newline 2006.173.05:21:21.44/k5log//k5ts3_log_newline 2006.173.05:21:22.14/k5log//k5ts4_log_newline 2006.173.05:21:22.17/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.05:21:22.17:setupk4=1 2006.173.05:21:22.17$setupk4/echo=on 2006.173.05:21:22.17$setupk4/pcalon 2006.173.05:21:22.17$pcalon/"no phase cal control is implemented here 2006.173.05:21:22.17$setupk4/"tpicd=stop 2006.173.05:21:22.17$setupk4/"rec=synch_on 2006.173.05:21:22.17$setupk4/"rec_mode=128 2006.173.05:21:22.17$setupk4/!* 2006.173.05:21:22.17$setupk4/recpk4 2006.173.05:21:22.17$recpk4/recpatch= 2006.173.05:21:22.17$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.05:21:22.17$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.05:21:22.17$setupk4/vck44 2006.173.05:21:22.17$vck44/valo=1,524.99 2006.173.05:21:22.17#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.05:21:22.17#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.05:21:22.17#ibcon#ireg 17 cls_cnt 0 2006.173.05:21:22.17#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.05:21:22.17#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.05:21:22.17#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.05:21:22.17#ibcon#enter wrdev, iclass 19, count 0 2006.173.05:21:22.17#ibcon#first serial, iclass 19, count 0 2006.173.05:21:22.17#ibcon#enter sib2, iclass 19, count 0 2006.173.05:21:22.17#ibcon#flushed, iclass 19, count 0 2006.173.05:21:22.17#ibcon#about to write, iclass 19, count 0 2006.173.05:21:22.17#ibcon#wrote, iclass 19, count 0 2006.173.05:21:22.17#ibcon#about to read 3, iclass 19, count 0 2006.173.05:21:22.18#ibcon#read 3, iclass 19, count 0 2006.173.05:21:22.18#ibcon#about to read 4, iclass 19, count 0 2006.173.05:21:22.18#ibcon#read 4, iclass 19, count 0 2006.173.05:21:22.18#ibcon#about to read 5, iclass 19, count 0 2006.173.05:21:22.18#ibcon#read 5, iclass 19, count 0 2006.173.05:21:22.18#ibcon#about to read 6, iclass 19, count 0 2006.173.05:21:22.18#ibcon#read 6, iclass 19, count 0 2006.173.05:21:22.18#ibcon#end of sib2, iclass 19, count 0 2006.173.05:21:22.18#ibcon#*mode == 0, iclass 19, count 0 2006.173.05:21:22.18#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.05:21:22.18#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.05:21:22.18#ibcon#*before write, iclass 19, count 0 2006.173.05:21:22.18#ibcon#enter sib2, iclass 19, count 0 2006.173.05:21:22.18#ibcon#flushed, iclass 19, count 0 2006.173.05:21:22.18#ibcon#about to write, iclass 19, count 0 2006.173.05:21:22.18#ibcon#wrote, iclass 19, count 0 2006.173.05:21:22.18#ibcon#about to read 3, iclass 19, count 0 2006.173.05:21:22.23#ibcon#read 3, iclass 19, count 0 2006.173.05:21:22.23#ibcon#about to read 4, iclass 19, count 0 2006.173.05:21:22.23#ibcon#read 4, iclass 19, count 0 2006.173.05:21:22.23#ibcon#about to read 5, iclass 19, count 0 2006.173.05:21:22.23#ibcon#read 5, iclass 19, count 0 2006.173.05:21:22.23#ibcon#about to read 6, iclass 19, count 0 2006.173.05:21:22.23#ibcon#read 6, iclass 19, count 0 2006.173.05:21:22.23#ibcon#end of sib2, iclass 19, count 0 2006.173.05:21:22.23#ibcon#*after write, iclass 19, count 0 2006.173.05:21:22.23#ibcon#*before return 0, iclass 19, count 0 2006.173.05:21:22.23#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.05:21:22.23#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.05:21:22.23#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.05:21:22.23#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.05:21:22.23$vck44/va=1,7 2006.173.05:21:22.23#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.05:21:22.23#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.05:21:22.23#ibcon#ireg 11 cls_cnt 2 2006.173.05:21:22.23#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.05:21:22.23#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.05:21:22.23#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.05:21:22.23#ibcon#enter wrdev, iclass 21, count 2 2006.173.05:21:22.23#ibcon#first serial, iclass 21, count 2 2006.173.05:21:22.23#ibcon#enter sib2, iclass 21, count 2 2006.173.05:21:22.23#ibcon#flushed, iclass 21, count 2 2006.173.05:21:22.23#ibcon#about to write, iclass 21, count 2 2006.173.05:21:22.23#ibcon#wrote, iclass 21, count 2 2006.173.05:21:22.23#ibcon#about to read 3, iclass 21, count 2 2006.173.05:21:22.25#ibcon#read 3, iclass 21, count 2 2006.173.05:21:22.25#ibcon#about to read 4, iclass 21, count 2 2006.173.05:21:22.25#ibcon#read 4, iclass 21, count 2 2006.173.05:21:22.25#ibcon#about to read 5, iclass 21, count 2 2006.173.05:21:22.25#ibcon#read 5, iclass 21, count 2 2006.173.05:21:22.25#ibcon#about to read 6, iclass 21, count 2 2006.173.05:21:22.25#ibcon#read 6, iclass 21, count 2 2006.173.05:21:22.25#ibcon#end of sib2, iclass 21, count 2 2006.173.05:21:22.25#ibcon#*mode == 0, iclass 21, count 2 2006.173.05:21:22.25#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.05:21:22.25#ibcon#[25=AT01-07\r\n] 2006.173.05:21:22.25#ibcon#*before write, iclass 21, count 2 2006.173.05:21:22.25#ibcon#enter sib2, iclass 21, count 2 2006.173.05:21:22.25#ibcon#flushed, iclass 21, count 2 2006.173.05:21:22.25#ibcon#about to write, iclass 21, count 2 2006.173.05:21:22.25#ibcon#wrote, iclass 21, count 2 2006.173.05:21:22.25#ibcon#about to read 3, iclass 21, count 2 2006.173.05:21:22.28#ibcon#read 3, iclass 21, count 2 2006.173.05:21:22.28#ibcon#about to read 4, iclass 21, count 2 2006.173.05:21:22.28#ibcon#read 4, iclass 21, count 2 2006.173.05:21:22.28#ibcon#about to read 5, iclass 21, count 2 2006.173.05:21:22.28#ibcon#read 5, iclass 21, count 2 2006.173.05:21:22.28#ibcon#about to read 6, iclass 21, count 2 2006.173.05:21:22.28#ibcon#read 6, iclass 21, count 2 2006.173.05:21:22.28#ibcon#end of sib2, iclass 21, count 2 2006.173.05:21:22.28#ibcon#*after write, iclass 21, count 2 2006.173.05:21:22.28#ibcon#*before return 0, iclass 21, count 2 2006.173.05:21:22.28#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.05:21:22.28#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.05:21:22.28#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.05:21:22.28#ibcon#ireg 7 cls_cnt 0 2006.173.05:21:22.28#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.05:21:22.40#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.05:21:22.40#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.05:21:22.40#ibcon#enter wrdev, iclass 21, count 0 2006.173.05:21:22.40#ibcon#first serial, iclass 21, count 0 2006.173.05:21:22.40#ibcon#enter sib2, iclass 21, count 0 2006.173.05:21:22.40#ibcon#flushed, iclass 21, count 0 2006.173.05:21:22.40#ibcon#about to write, iclass 21, count 0 2006.173.05:21:22.40#ibcon#wrote, iclass 21, count 0 2006.173.05:21:22.40#ibcon#about to read 3, iclass 21, count 0 2006.173.05:21:22.42#ibcon#read 3, iclass 21, count 0 2006.173.05:21:22.42#ibcon#about to read 4, iclass 21, count 0 2006.173.05:21:22.42#ibcon#read 4, iclass 21, count 0 2006.173.05:21:22.42#ibcon#about to read 5, iclass 21, count 0 2006.173.05:21:22.42#ibcon#read 5, iclass 21, count 0 2006.173.05:21:22.42#ibcon#about to read 6, iclass 21, count 0 2006.173.05:21:22.42#ibcon#read 6, iclass 21, count 0 2006.173.05:21:22.42#ibcon#end of sib2, iclass 21, count 0 2006.173.05:21:22.42#ibcon#*mode == 0, iclass 21, count 0 2006.173.05:21:22.42#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.05:21:22.42#ibcon#[25=USB\r\n] 2006.173.05:21:22.42#ibcon#*before write, iclass 21, count 0 2006.173.05:21:22.42#ibcon#enter sib2, iclass 21, count 0 2006.173.05:21:22.42#ibcon#flushed, iclass 21, count 0 2006.173.05:21:22.42#ibcon#about to write, iclass 21, count 0 2006.173.05:21:22.42#ibcon#wrote, iclass 21, count 0 2006.173.05:21:22.42#ibcon#about to read 3, iclass 21, count 0 2006.173.05:21:22.45#ibcon#read 3, iclass 21, count 0 2006.173.05:21:22.45#ibcon#about to read 4, iclass 21, count 0 2006.173.05:21:22.45#ibcon#read 4, iclass 21, count 0 2006.173.05:21:22.45#ibcon#about to read 5, iclass 21, count 0 2006.173.05:21:22.45#ibcon#read 5, iclass 21, count 0 2006.173.05:21:22.45#ibcon#about to read 6, iclass 21, count 0 2006.173.05:21:22.45#ibcon#read 6, iclass 21, count 0 2006.173.05:21:22.45#ibcon#end of sib2, iclass 21, count 0 2006.173.05:21:22.45#ibcon#*after write, iclass 21, count 0 2006.173.05:21:22.45#ibcon#*before return 0, iclass 21, count 0 2006.173.05:21:22.45#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.05:21:22.45#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.05:21:22.45#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.05:21:22.45#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.05:21:22.45$vck44/valo=2,534.99 2006.173.05:21:22.45#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.05:21:22.45#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.05:21:22.45#ibcon#ireg 17 cls_cnt 0 2006.173.05:21:22.45#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.05:21:22.45#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.05:21:22.45#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.05:21:22.45#ibcon#enter wrdev, iclass 23, count 0 2006.173.05:21:22.45#ibcon#first serial, iclass 23, count 0 2006.173.05:21:22.45#ibcon#enter sib2, iclass 23, count 0 2006.173.05:21:22.45#ibcon#flushed, iclass 23, count 0 2006.173.05:21:22.45#ibcon#about to write, iclass 23, count 0 2006.173.05:21:22.45#ibcon#wrote, iclass 23, count 0 2006.173.05:21:22.45#ibcon#about to read 3, iclass 23, count 0 2006.173.05:21:22.47#ibcon#read 3, iclass 23, count 0 2006.173.05:21:22.47#ibcon#about to read 4, iclass 23, count 0 2006.173.05:21:22.47#ibcon#read 4, iclass 23, count 0 2006.173.05:21:22.47#ibcon#about to read 5, iclass 23, count 0 2006.173.05:21:22.47#ibcon#read 5, iclass 23, count 0 2006.173.05:21:22.47#ibcon#about to read 6, iclass 23, count 0 2006.173.05:21:22.47#ibcon#read 6, iclass 23, count 0 2006.173.05:21:22.47#ibcon#end of sib2, iclass 23, count 0 2006.173.05:21:22.47#ibcon#*mode == 0, iclass 23, count 0 2006.173.05:21:22.47#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.05:21:22.47#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.05:21:22.47#ibcon#*before write, iclass 23, count 0 2006.173.05:21:22.47#ibcon#enter sib2, iclass 23, count 0 2006.173.05:21:22.47#ibcon#flushed, iclass 23, count 0 2006.173.05:21:22.47#ibcon#about to write, iclass 23, count 0 2006.173.05:21:22.47#ibcon#wrote, iclass 23, count 0 2006.173.05:21:22.47#ibcon#about to read 3, iclass 23, count 0 2006.173.05:21:22.51#ibcon#read 3, iclass 23, count 0 2006.173.05:21:22.51#ibcon#about to read 4, iclass 23, count 0 2006.173.05:21:22.51#ibcon#read 4, iclass 23, count 0 2006.173.05:21:22.51#ibcon#about to read 5, iclass 23, count 0 2006.173.05:21:22.51#ibcon#read 5, iclass 23, count 0 2006.173.05:21:22.51#ibcon#about to read 6, iclass 23, count 0 2006.173.05:21:22.51#ibcon#read 6, iclass 23, count 0 2006.173.05:21:22.51#ibcon#end of sib2, iclass 23, count 0 2006.173.05:21:22.51#ibcon#*after write, iclass 23, count 0 2006.173.05:21:22.51#ibcon#*before return 0, iclass 23, count 0 2006.173.05:21:22.51#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.05:21:22.51#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.05:21:22.51#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.05:21:22.51#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.05:21:22.51$vck44/va=2,6 2006.173.05:21:22.51#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.05:21:22.51#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.05:21:22.51#ibcon#ireg 11 cls_cnt 2 2006.173.05:21:22.51#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.05:21:22.57#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.05:21:22.57#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.05:21:22.57#ibcon#enter wrdev, iclass 25, count 2 2006.173.05:21:22.57#ibcon#first serial, iclass 25, count 2 2006.173.05:21:22.57#ibcon#enter sib2, iclass 25, count 2 2006.173.05:21:22.57#ibcon#flushed, iclass 25, count 2 2006.173.05:21:22.57#ibcon#about to write, iclass 25, count 2 2006.173.05:21:22.57#ibcon#wrote, iclass 25, count 2 2006.173.05:21:22.57#ibcon#about to read 3, iclass 25, count 2 2006.173.05:21:22.59#ibcon#read 3, iclass 25, count 2 2006.173.05:21:22.59#ibcon#about to read 4, iclass 25, count 2 2006.173.05:21:22.59#ibcon#read 4, iclass 25, count 2 2006.173.05:21:22.59#ibcon#about to read 5, iclass 25, count 2 2006.173.05:21:22.59#ibcon#read 5, iclass 25, count 2 2006.173.05:21:22.59#ibcon#about to read 6, iclass 25, count 2 2006.173.05:21:22.59#ibcon#read 6, iclass 25, count 2 2006.173.05:21:22.59#ibcon#end of sib2, iclass 25, count 2 2006.173.05:21:22.59#ibcon#*mode == 0, iclass 25, count 2 2006.173.05:21:22.59#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.05:21:22.59#ibcon#[25=AT02-06\r\n] 2006.173.05:21:22.59#ibcon#*before write, iclass 25, count 2 2006.173.05:21:22.59#ibcon#enter sib2, iclass 25, count 2 2006.173.05:21:22.59#ibcon#flushed, iclass 25, count 2 2006.173.05:21:22.59#ibcon#about to write, iclass 25, count 2 2006.173.05:21:22.59#ibcon#wrote, iclass 25, count 2 2006.173.05:21:22.59#ibcon#about to read 3, iclass 25, count 2 2006.173.05:21:22.62#ibcon#read 3, iclass 25, count 2 2006.173.05:21:22.62#ibcon#about to read 4, iclass 25, count 2 2006.173.05:21:22.62#ibcon#read 4, iclass 25, count 2 2006.173.05:21:22.62#ibcon#about to read 5, iclass 25, count 2 2006.173.05:21:22.62#ibcon#read 5, iclass 25, count 2 2006.173.05:21:22.62#ibcon#about to read 6, iclass 25, count 2 2006.173.05:21:22.62#ibcon#read 6, iclass 25, count 2 2006.173.05:21:22.62#ibcon#end of sib2, iclass 25, count 2 2006.173.05:21:22.62#ibcon#*after write, iclass 25, count 2 2006.173.05:21:22.62#ibcon#*before return 0, iclass 25, count 2 2006.173.05:21:22.62#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.05:21:22.62#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.05:21:22.62#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.05:21:22.62#ibcon#ireg 7 cls_cnt 0 2006.173.05:21:22.62#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.05:21:22.74#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.05:21:22.74#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.05:21:22.74#ibcon#enter wrdev, iclass 25, count 0 2006.173.05:21:22.74#ibcon#first serial, iclass 25, count 0 2006.173.05:21:22.74#ibcon#enter sib2, iclass 25, count 0 2006.173.05:21:22.74#ibcon#flushed, iclass 25, count 0 2006.173.05:21:22.74#ibcon#about to write, iclass 25, count 0 2006.173.05:21:22.74#ibcon#wrote, iclass 25, count 0 2006.173.05:21:22.74#ibcon#about to read 3, iclass 25, count 0 2006.173.05:21:22.76#ibcon#read 3, iclass 25, count 0 2006.173.05:21:22.76#ibcon#about to read 4, iclass 25, count 0 2006.173.05:21:22.76#ibcon#read 4, iclass 25, count 0 2006.173.05:21:22.76#ibcon#about to read 5, iclass 25, count 0 2006.173.05:21:22.76#ibcon#read 5, iclass 25, count 0 2006.173.05:21:22.76#ibcon#about to read 6, iclass 25, count 0 2006.173.05:21:22.76#ibcon#read 6, iclass 25, count 0 2006.173.05:21:22.76#ibcon#end of sib2, iclass 25, count 0 2006.173.05:21:22.76#ibcon#*mode == 0, iclass 25, count 0 2006.173.05:21:22.76#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.05:21:22.76#ibcon#[25=USB\r\n] 2006.173.05:21:22.76#ibcon#*before write, iclass 25, count 0 2006.173.05:21:22.76#ibcon#enter sib2, iclass 25, count 0 2006.173.05:21:22.76#ibcon#flushed, iclass 25, count 0 2006.173.05:21:22.76#ibcon#about to write, iclass 25, count 0 2006.173.05:21:22.76#ibcon#wrote, iclass 25, count 0 2006.173.05:21:22.76#ibcon#about to read 3, iclass 25, count 0 2006.173.05:21:22.79#ibcon#read 3, iclass 25, count 0 2006.173.05:21:22.79#ibcon#about to read 4, iclass 25, count 0 2006.173.05:21:22.79#ibcon#read 4, iclass 25, count 0 2006.173.05:21:22.79#ibcon#about to read 5, iclass 25, count 0 2006.173.05:21:22.79#ibcon#read 5, iclass 25, count 0 2006.173.05:21:22.79#ibcon#about to read 6, iclass 25, count 0 2006.173.05:21:22.79#ibcon#read 6, iclass 25, count 0 2006.173.05:21:22.79#ibcon#end of sib2, iclass 25, count 0 2006.173.05:21:22.79#ibcon#*after write, iclass 25, count 0 2006.173.05:21:22.79#ibcon#*before return 0, iclass 25, count 0 2006.173.05:21:22.79#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.05:21:22.79#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.05:21:22.79#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.05:21:22.79#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.05:21:22.79$vck44/valo=3,564.99 2006.173.05:21:22.79#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.05:21:22.79#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.05:21:22.79#ibcon#ireg 17 cls_cnt 0 2006.173.05:21:22.79#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.05:21:22.79#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.05:21:22.79#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.05:21:22.79#ibcon#enter wrdev, iclass 27, count 0 2006.173.05:21:22.79#ibcon#first serial, iclass 27, count 0 2006.173.05:21:22.79#ibcon#enter sib2, iclass 27, count 0 2006.173.05:21:22.79#ibcon#flushed, iclass 27, count 0 2006.173.05:21:22.79#ibcon#about to write, iclass 27, count 0 2006.173.05:21:22.79#ibcon#wrote, iclass 27, count 0 2006.173.05:21:22.79#ibcon#about to read 3, iclass 27, count 0 2006.173.05:21:22.81#ibcon#read 3, iclass 27, count 0 2006.173.05:21:22.81#ibcon#about to read 4, iclass 27, count 0 2006.173.05:21:22.81#ibcon#read 4, iclass 27, count 0 2006.173.05:21:22.81#ibcon#about to read 5, iclass 27, count 0 2006.173.05:21:22.81#ibcon#read 5, iclass 27, count 0 2006.173.05:21:22.81#ibcon#about to read 6, iclass 27, count 0 2006.173.05:21:22.81#ibcon#read 6, iclass 27, count 0 2006.173.05:21:22.81#ibcon#end of sib2, iclass 27, count 0 2006.173.05:21:22.81#ibcon#*mode == 0, iclass 27, count 0 2006.173.05:21:22.81#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.05:21:22.81#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.05:21:22.81#ibcon#*before write, iclass 27, count 0 2006.173.05:21:22.81#ibcon#enter sib2, iclass 27, count 0 2006.173.05:21:22.81#ibcon#flushed, iclass 27, count 0 2006.173.05:21:22.81#ibcon#about to write, iclass 27, count 0 2006.173.05:21:22.81#ibcon#wrote, iclass 27, count 0 2006.173.05:21:22.81#ibcon#about to read 3, iclass 27, count 0 2006.173.05:21:22.85#ibcon#read 3, iclass 27, count 0 2006.173.05:21:22.85#ibcon#about to read 4, iclass 27, count 0 2006.173.05:21:22.85#ibcon#read 4, iclass 27, count 0 2006.173.05:21:22.85#ibcon#about to read 5, iclass 27, count 0 2006.173.05:21:22.85#ibcon#read 5, iclass 27, count 0 2006.173.05:21:22.85#ibcon#about to read 6, iclass 27, count 0 2006.173.05:21:22.85#ibcon#read 6, iclass 27, count 0 2006.173.05:21:22.85#ibcon#end of sib2, iclass 27, count 0 2006.173.05:21:22.85#ibcon#*after write, iclass 27, count 0 2006.173.05:21:22.85#ibcon#*before return 0, iclass 27, count 0 2006.173.05:21:22.85#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.05:21:22.85#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.05:21:22.85#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.05:21:22.85#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.05:21:22.85$vck44/va=3,5 2006.173.05:21:22.85#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.05:21:22.85#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.05:21:22.85#ibcon#ireg 11 cls_cnt 2 2006.173.05:21:22.85#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.05:21:22.91#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.05:21:22.91#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.05:21:22.91#ibcon#enter wrdev, iclass 29, count 2 2006.173.05:21:22.91#ibcon#first serial, iclass 29, count 2 2006.173.05:21:22.91#ibcon#enter sib2, iclass 29, count 2 2006.173.05:21:22.91#ibcon#flushed, iclass 29, count 2 2006.173.05:21:22.91#ibcon#about to write, iclass 29, count 2 2006.173.05:21:22.91#ibcon#wrote, iclass 29, count 2 2006.173.05:21:22.91#ibcon#about to read 3, iclass 29, count 2 2006.173.05:21:22.93#ibcon#read 3, iclass 29, count 2 2006.173.05:21:22.93#ibcon#about to read 4, iclass 29, count 2 2006.173.05:21:22.93#ibcon#read 4, iclass 29, count 2 2006.173.05:21:22.93#ibcon#about to read 5, iclass 29, count 2 2006.173.05:21:22.93#ibcon#read 5, iclass 29, count 2 2006.173.05:21:22.93#ibcon#about to read 6, iclass 29, count 2 2006.173.05:21:22.93#ibcon#read 6, iclass 29, count 2 2006.173.05:21:22.93#ibcon#end of sib2, iclass 29, count 2 2006.173.05:21:22.93#ibcon#*mode == 0, iclass 29, count 2 2006.173.05:21:22.93#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.05:21:22.93#ibcon#[25=AT03-05\r\n] 2006.173.05:21:22.93#ibcon#*before write, iclass 29, count 2 2006.173.05:21:22.93#ibcon#enter sib2, iclass 29, count 2 2006.173.05:21:22.93#ibcon#flushed, iclass 29, count 2 2006.173.05:21:22.93#ibcon#about to write, iclass 29, count 2 2006.173.05:21:22.93#ibcon#wrote, iclass 29, count 2 2006.173.05:21:22.93#ibcon#about to read 3, iclass 29, count 2 2006.173.05:21:22.96#ibcon#read 3, iclass 29, count 2 2006.173.05:21:22.96#ibcon#about to read 4, iclass 29, count 2 2006.173.05:21:22.96#ibcon#read 4, iclass 29, count 2 2006.173.05:21:22.96#ibcon#about to read 5, iclass 29, count 2 2006.173.05:21:22.96#ibcon#read 5, iclass 29, count 2 2006.173.05:21:22.96#ibcon#about to read 6, iclass 29, count 2 2006.173.05:21:22.96#ibcon#read 6, iclass 29, count 2 2006.173.05:21:22.96#ibcon#end of sib2, iclass 29, count 2 2006.173.05:21:22.96#ibcon#*after write, iclass 29, count 2 2006.173.05:21:22.96#ibcon#*before return 0, iclass 29, count 2 2006.173.05:21:22.96#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.05:21:22.96#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.05:21:22.96#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.05:21:22.96#ibcon#ireg 7 cls_cnt 0 2006.173.05:21:22.96#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.05:21:23.08#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.05:21:23.08#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.05:21:23.08#ibcon#enter wrdev, iclass 29, count 0 2006.173.05:21:23.08#ibcon#first serial, iclass 29, count 0 2006.173.05:21:23.08#ibcon#enter sib2, iclass 29, count 0 2006.173.05:21:23.08#ibcon#flushed, iclass 29, count 0 2006.173.05:21:23.08#ibcon#about to write, iclass 29, count 0 2006.173.05:21:23.08#ibcon#wrote, iclass 29, count 0 2006.173.05:21:23.08#ibcon#about to read 3, iclass 29, count 0 2006.173.05:21:23.10#ibcon#read 3, iclass 29, count 0 2006.173.05:21:23.10#ibcon#about to read 4, iclass 29, count 0 2006.173.05:21:23.10#ibcon#read 4, iclass 29, count 0 2006.173.05:21:23.10#ibcon#about to read 5, iclass 29, count 0 2006.173.05:21:23.10#ibcon#read 5, iclass 29, count 0 2006.173.05:21:23.10#ibcon#about to read 6, iclass 29, count 0 2006.173.05:21:23.10#ibcon#read 6, iclass 29, count 0 2006.173.05:21:23.10#ibcon#end of sib2, iclass 29, count 0 2006.173.05:21:23.10#ibcon#*mode == 0, iclass 29, count 0 2006.173.05:21:23.10#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.05:21:23.10#ibcon#[25=USB\r\n] 2006.173.05:21:23.10#ibcon#*before write, iclass 29, count 0 2006.173.05:21:23.10#ibcon#enter sib2, iclass 29, count 0 2006.173.05:21:23.10#ibcon#flushed, iclass 29, count 0 2006.173.05:21:23.10#ibcon#about to write, iclass 29, count 0 2006.173.05:21:23.10#ibcon#wrote, iclass 29, count 0 2006.173.05:21:23.10#ibcon#about to read 3, iclass 29, count 0 2006.173.05:21:23.13#ibcon#read 3, iclass 29, count 0 2006.173.05:21:23.13#ibcon#about to read 4, iclass 29, count 0 2006.173.05:21:23.13#ibcon#read 4, iclass 29, count 0 2006.173.05:21:23.13#ibcon#about to read 5, iclass 29, count 0 2006.173.05:21:23.13#ibcon#read 5, iclass 29, count 0 2006.173.05:21:23.13#ibcon#about to read 6, iclass 29, count 0 2006.173.05:21:23.13#ibcon#read 6, iclass 29, count 0 2006.173.05:21:23.13#ibcon#end of sib2, iclass 29, count 0 2006.173.05:21:23.13#ibcon#*after write, iclass 29, count 0 2006.173.05:21:23.13#ibcon#*before return 0, iclass 29, count 0 2006.173.05:21:23.13#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.05:21:23.13#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.05:21:23.13#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.05:21:23.13#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.05:21:23.13$vck44/valo=4,624.99 2006.173.05:21:23.13#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.05:21:23.13#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.05:21:23.13#ibcon#ireg 17 cls_cnt 0 2006.173.05:21:23.13#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.05:21:23.13#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.05:21:23.13#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.05:21:23.13#ibcon#enter wrdev, iclass 31, count 0 2006.173.05:21:23.13#ibcon#first serial, iclass 31, count 0 2006.173.05:21:23.13#ibcon#enter sib2, iclass 31, count 0 2006.173.05:21:23.13#ibcon#flushed, iclass 31, count 0 2006.173.05:21:23.13#ibcon#about to write, iclass 31, count 0 2006.173.05:21:23.13#ibcon#wrote, iclass 31, count 0 2006.173.05:21:23.13#ibcon#about to read 3, iclass 31, count 0 2006.173.05:21:23.15#ibcon#read 3, iclass 31, count 0 2006.173.05:21:23.15#ibcon#about to read 4, iclass 31, count 0 2006.173.05:21:23.15#ibcon#read 4, iclass 31, count 0 2006.173.05:21:23.15#ibcon#about to read 5, iclass 31, count 0 2006.173.05:21:23.15#ibcon#read 5, iclass 31, count 0 2006.173.05:21:23.15#ibcon#about to read 6, iclass 31, count 0 2006.173.05:21:23.15#ibcon#read 6, iclass 31, count 0 2006.173.05:21:23.15#ibcon#end of sib2, iclass 31, count 0 2006.173.05:21:23.15#ibcon#*mode == 0, iclass 31, count 0 2006.173.05:21:23.15#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.05:21:23.15#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.05:21:23.15#ibcon#*before write, iclass 31, count 0 2006.173.05:21:23.15#ibcon#enter sib2, iclass 31, count 0 2006.173.05:21:23.15#ibcon#flushed, iclass 31, count 0 2006.173.05:21:23.15#ibcon#about to write, iclass 31, count 0 2006.173.05:21:23.15#ibcon#wrote, iclass 31, count 0 2006.173.05:21:23.15#ibcon#about to read 3, iclass 31, count 0 2006.173.05:21:23.19#ibcon#read 3, iclass 31, count 0 2006.173.05:21:23.19#ibcon#about to read 4, iclass 31, count 0 2006.173.05:21:23.19#ibcon#read 4, iclass 31, count 0 2006.173.05:21:23.19#ibcon#about to read 5, iclass 31, count 0 2006.173.05:21:23.19#ibcon#read 5, iclass 31, count 0 2006.173.05:21:23.19#ibcon#about to read 6, iclass 31, count 0 2006.173.05:21:23.19#ibcon#read 6, iclass 31, count 0 2006.173.05:21:23.19#ibcon#end of sib2, iclass 31, count 0 2006.173.05:21:23.19#ibcon#*after write, iclass 31, count 0 2006.173.05:21:23.19#ibcon#*before return 0, iclass 31, count 0 2006.173.05:21:23.19#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.05:21:23.19#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.05:21:23.19#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.05:21:23.19#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.05:21:23.19$vck44/va=4,6 2006.173.05:21:23.19#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.173.05:21:23.19#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.173.05:21:23.19#ibcon#ireg 11 cls_cnt 2 2006.173.05:21:23.19#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.05:21:23.25#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.05:21:23.25#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.05:21:23.25#ibcon#enter wrdev, iclass 33, count 2 2006.173.05:21:23.25#ibcon#first serial, iclass 33, count 2 2006.173.05:21:23.25#ibcon#enter sib2, iclass 33, count 2 2006.173.05:21:23.25#ibcon#flushed, iclass 33, count 2 2006.173.05:21:23.25#ibcon#about to write, iclass 33, count 2 2006.173.05:21:23.25#ibcon#wrote, iclass 33, count 2 2006.173.05:21:23.25#ibcon#about to read 3, iclass 33, count 2 2006.173.05:21:23.27#ibcon#read 3, iclass 33, count 2 2006.173.05:21:23.27#ibcon#about to read 4, iclass 33, count 2 2006.173.05:21:23.27#ibcon#read 4, iclass 33, count 2 2006.173.05:21:23.27#ibcon#about to read 5, iclass 33, count 2 2006.173.05:21:23.27#ibcon#read 5, iclass 33, count 2 2006.173.05:21:23.27#ibcon#about to read 6, iclass 33, count 2 2006.173.05:21:23.27#ibcon#read 6, iclass 33, count 2 2006.173.05:21:23.27#ibcon#end of sib2, iclass 33, count 2 2006.173.05:21:23.27#ibcon#*mode == 0, iclass 33, count 2 2006.173.05:21:23.27#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.173.05:21:23.27#ibcon#[25=AT04-06\r\n] 2006.173.05:21:23.27#ibcon#*before write, iclass 33, count 2 2006.173.05:21:23.27#ibcon#enter sib2, iclass 33, count 2 2006.173.05:21:23.27#ibcon#flushed, iclass 33, count 2 2006.173.05:21:23.27#ibcon#about to write, iclass 33, count 2 2006.173.05:21:23.27#ibcon#wrote, iclass 33, count 2 2006.173.05:21:23.27#ibcon#about to read 3, iclass 33, count 2 2006.173.05:21:23.30#ibcon#read 3, iclass 33, count 2 2006.173.05:21:23.30#ibcon#about to read 4, iclass 33, count 2 2006.173.05:21:23.30#ibcon#read 4, iclass 33, count 2 2006.173.05:21:23.30#ibcon#about to read 5, iclass 33, count 2 2006.173.05:21:23.30#ibcon#read 5, iclass 33, count 2 2006.173.05:21:23.30#ibcon#about to read 6, iclass 33, count 2 2006.173.05:21:23.30#ibcon#read 6, iclass 33, count 2 2006.173.05:21:23.30#ibcon#end of sib2, iclass 33, count 2 2006.173.05:21:23.30#ibcon#*after write, iclass 33, count 2 2006.173.05:21:23.30#ibcon#*before return 0, iclass 33, count 2 2006.173.05:21:23.30#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.05:21:23.30#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.173.05:21:23.30#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.173.05:21:23.30#ibcon#ireg 7 cls_cnt 0 2006.173.05:21:23.30#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.05:21:23.42#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.05:21:23.42#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.05:21:23.42#ibcon#enter wrdev, iclass 33, count 0 2006.173.05:21:23.42#ibcon#first serial, iclass 33, count 0 2006.173.05:21:23.42#ibcon#enter sib2, iclass 33, count 0 2006.173.05:21:23.42#ibcon#flushed, iclass 33, count 0 2006.173.05:21:23.42#ibcon#about to write, iclass 33, count 0 2006.173.05:21:23.42#ibcon#wrote, iclass 33, count 0 2006.173.05:21:23.42#ibcon#about to read 3, iclass 33, count 0 2006.173.05:21:23.44#ibcon#read 3, iclass 33, count 0 2006.173.05:21:23.44#ibcon#about to read 4, iclass 33, count 0 2006.173.05:21:23.44#ibcon#read 4, iclass 33, count 0 2006.173.05:21:23.44#ibcon#about to read 5, iclass 33, count 0 2006.173.05:21:23.44#ibcon#read 5, iclass 33, count 0 2006.173.05:21:23.44#ibcon#about to read 6, iclass 33, count 0 2006.173.05:21:23.44#ibcon#read 6, iclass 33, count 0 2006.173.05:21:23.44#ibcon#end of sib2, iclass 33, count 0 2006.173.05:21:23.44#ibcon#*mode == 0, iclass 33, count 0 2006.173.05:21:23.44#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.05:21:23.44#ibcon#[25=USB\r\n] 2006.173.05:21:23.44#ibcon#*before write, iclass 33, count 0 2006.173.05:21:23.44#ibcon#enter sib2, iclass 33, count 0 2006.173.05:21:23.44#ibcon#flushed, iclass 33, count 0 2006.173.05:21:23.44#ibcon#about to write, iclass 33, count 0 2006.173.05:21:23.44#ibcon#wrote, iclass 33, count 0 2006.173.05:21:23.44#ibcon#about to read 3, iclass 33, count 0 2006.173.05:21:23.47#ibcon#read 3, iclass 33, count 0 2006.173.05:21:23.47#ibcon#about to read 4, iclass 33, count 0 2006.173.05:21:23.47#ibcon#read 4, iclass 33, count 0 2006.173.05:21:23.47#ibcon#about to read 5, iclass 33, count 0 2006.173.05:21:23.47#ibcon#read 5, iclass 33, count 0 2006.173.05:21:23.47#ibcon#about to read 6, iclass 33, count 0 2006.173.05:21:23.47#ibcon#read 6, iclass 33, count 0 2006.173.05:21:23.47#ibcon#end of sib2, iclass 33, count 0 2006.173.05:21:23.47#ibcon#*after write, iclass 33, count 0 2006.173.05:21:23.47#ibcon#*before return 0, iclass 33, count 0 2006.173.05:21:23.47#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.05:21:23.47#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.173.05:21:23.47#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.05:21:23.47#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.05:21:23.47$vck44/valo=5,734.99 2006.173.05:21:23.47#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.05:21:23.47#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.05:21:23.47#ibcon#ireg 17 cls_cnt 0 2006.173.05:21:23.47#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.05:21:23.47#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.05:21:23.47#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.05:21:23.47#ibcon#enter wrdev, iclass 35, count 0 2006.173.05:21:23.47#ibcon#first serial, iclass 35, count 0 2006.173.05:21:23.47#ibcon#enter sib2, iclass 35, count 0 2006.173.05:21:23.47#ibcon#flushed, iclass 35, count 0 2006.173.05:21:23.47#ibcon#about to write, iclass 35, count 0 2006.173.05:21:23.47#ibcon#wrote, iclass 35, count 0 2006.173.05:21:23.47#ibcon#about to read 3, iclass 35, count 0 2006.173.05:21:23.49#ibcon#read 3, iclass 35, count 0 2006.173.05:21:23.49#ibcon#about to read 4, iclass 35, count 0 2006.173.05:21:23.49#ibcon#read 4, iclass 35, count 0 2006.173.05:21:23.49#ibcon#about to read 5, iclass 35, count 0 2006.173.05:21:23.49#ibcon#read 5, iclass 35, count 0 2006.173.05:21:23.49#ibcon#about to read 6, iclass 35, count 0 2006.173.05:21:23.49#ibcon#read 6, iclass 35, count 0 2006.173.05:21:23.49#ibcon#end of sib2, iclass 35, count 0 2006.173.05:21:23.49#ibcon#*mode == 0, iclass 35, count 0 2006.173.05:21:23.49#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.05:21:23.49#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.05:21:23.49#ibcon#*before write, iclass 35, count 0 2006.173.05:21:23.49#ibcon#enter sib2, iclass 35, count 0 2006.173.05:21:23.49#ibcon#flushed, iclass 35, count 0 2006.173.05:21:23.49#ibcon#about to write, iclass 35, count 0 2006.173.05:21:23.49#ibcon#wrote, iclass 35, count 0 2006.173.05:21:23.49#ibcon#about to read 3, iclass 35, count 0 2006.173.05:21:23.53#ibcon#read 3, iclass 35, count 0 2006.173.05:21:23.53#ibcon#about to read 4, iclass 35, count 0 2006.173.05:21:23.53#ibcon#read 4, iclass 35, count 0 2006.173.05:21:23.53#ibcon#about to read 5, iclass 35, count 0 2006.173.05:21:23.53#ibcon#read 5, iclass 35, count 0 2006.173.05:21:23.53#ibcon#about to read 6, iclass 35, count 0 2006.173.05:21:23.53#ibcon#read 6, iclass 35, count 0 2006.173.05:21:23.53#ibcon#end of sib2, iclass 35, count 0 2006.173.05:21:23.53#ibcon#*after write, iclass 35, count 0 2006.173.05:21:23.53#ibcon#*before return 0, iclass 35, count 0 2006.173.05:21:23.53#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.05:21:23.53#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.05:21:23.53#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.05:21:23.53#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.05:21:23.53$vck44/va=5,4 2006.173.05:21:23.53#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.173.05:21:23.53#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.173.05:21:23.53#ibcon#ireg 11 cls_cnt 2 2006.173.05:21:23.53#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.05:21:23.59#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.05:21:23.59#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.05:21:23.59#ibcon#enter wrdev, iclass 37, count 2 2006.173.05:21:23.59#ibcon#first serial, iclass 37, count 2 2006.173.05:21:23.59#ibcon#enter sib2, iclass 37, count 2 2006.173.05:21:23.59#ibcon#flushed, iclass 37, count 2 2006.173.05:21:23.59#ibcon#about to write, iclass 37, count 2 2006.173.05:21:23.59#ibcon#wrote, iclass 37, count 2 2006.173.05:21:23.59#ibcon#about to read 3, iclass 37, count 2 2006.173.05:21:23.61#ibcon#read 3, iclass 37, count 2 2006.173.05:21:23.61#ibcon#about to read 4, iclass 37, count 2 2006.173.05:21:23.61#ibcon#read 4, iclass 37, count 2 2006.173.05:21:23.61#ibcon#about to read 5, iclass 37, count 2 2006.173.05:21:23.61#ibcon#read 5, iclass 37, count 2 2006.173.05:21:23.61#ibcon#about to read 6, iclass 37, count 2 2006.173.05:21:23.61#ibcon#read 6, iclass 37, count 2 2006.173.05:21:23.61#ibcon#end of sib2, iclass 37, count 2 2006.173.05:21:23.61#ibcon#*mode == 0, iclass 37, count 2 2006.173.05:21:23.61#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.173.05:21:23.61#ibcon#[25=AT05-04\r\n] 2006.173.05:21:23.61#ibcon#*before write, iclass 37, count 2 2006.173.05:21:23.61#ibcon#enter sib2, iclass 37, count 2 2006.173.05:21:23.61#ibcon#flushed, iclass 37, count 2 2006.173.05:21:23.61#ibcon#about to write, iclass 37, count 2 2006.173.05:21:23.61#ibcon#wrote, iclass 37, count 2 2006.173.05:21:23.61#ibcon#about to read 3, iclass 37, count 2 2006.173.05:21:23.64#ibcon#read 3, iclass 37, count 2 2006.173.05:21:23.64#ibcon#about to read 4, iclass 37, count 2 2006.173.05:21:23.64#ibcon#read 4, iclass 37, count 2 2006.173.05:21:23.64#ibcon#about to read 5, iclass 37, count 2 2006.173.05:21:23.64#ibcon#read 5, iclass 37, count 2 2006.173.05:21:23.64#ibcon#about to read 6, iclass 37, count 2 2006.173.05:21:23.64#ibcon#read 6, iclass 37, count 2 2006.173.05:21:23.64#ibcon#end of sib2, iclass 37, count 2 2006.173.05:21:23.64#ibcon#*after write, iclass 37, count 2 2006.173.05:21:23.64#ibcon#*before return 0, iclass 37, count 2 2006.173.05:21:23.64#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.05:21:23.64#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.173.05:21:23.64#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.173.05:21:23.64#ibcon#ireg 7 cls_cnt 0 2006.173.05:21:23.64#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.05:21:23.76#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.05:21:23.76#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.05:21:23.76#ibcon#enter wrdev, iclass 37, count 0 2006.173.05:21:23.76#ibcon#first serial, iclass 37, count 0 2006.173.05:21:23.76#ibcon#enter sib2, iclass 37, count 0 2006.173.05:21:23.76#ibcon#flushed, iclass 37, count 0 2006.173.05:21:23.76#ibcon#about to write, iclass 37, count 0 2006.173.05:21:23.76#ibcon#wrote, iclass 37, count 0 2006.173.05:21:23.76#ibcon#about to read 3, iclass 37, count 0 2006.173.05:21:23.78#ibcon#read 3, iclass 37, count 0 2006.173.05:21:23.78#ibcon#about to read 4, iclass 37, count 0 2006.173.05:21:23.78#ibcon#read 4, iclass 37, count 0 2006.173.05:21:23.78#ibcon#about to read 5, iclass 37, count 0 2006.173.05:21:23.78#ibcon#read 5, iclass 37, count 0 2006.173.05:21:23.78#ibcon#about to read 6, iclass 37, count 0 2006.173.05:21:23.78#ibcon#read 6, iclass 37, count 0 2006.173.05:21:23.78#ibcon#end of sib2, iclass 37, count 0 2006.173.05:21:23.78#ibcon#*mode == 0, iclass 37, count 0 2006.173.05:21:23.78#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.05:21:23.78#ibcon#[25=USB\r\n] 2006.173.05:21:23.78#ibcon#*before write, iclass 37, count 0 2006.173.05:21:23.78#ibcon#enter sib2, iclass 37, count 0 2006.173.05:21:23.78#ibcon#flushed, iclass 37, count 0 2006.173.05:21:23.78#ibcon#about to write, iclass 37, count 0 2006.173.05:21:23.78#ibcon#wrote, iclass 37, count 0 2006.173.05:21:23.78#ibcon#about to read 3, iclass 37, count 0 2006.173.05:21:23.81#ibcon#read 3, iclass 37, count 0 2006.173.05:21:23.81#ibcon#about to read 4, iclass 37, count 0 2006.173.05:21:23.81#ibcon#read 4, iclass 37, count 0 2006.173.05:21:23.81#ibcon#about to read 5, iclass 37, count 0 2006.173.05:21:23.81#ibcon#read 5, iclass 37, count 0 2006.173.05:21:23.81#ibcon#about to read 6, iclass 37, count 0 2006.173.05:21:23.81#ibcon#read 6, iclass 37, count 0 2006.173.05:21:23.81#ibcon#end of sib2, iclass 37, count 0 2006.173.05:21:23.81#ibcon#*after write, iclass 37, count 0 2006.173.05:21:23.81#ibcon#*before return 0, iclass 37, count 0 2006.173.05:21:23.81#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.05:21:23.81#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.173.05:21:23.81#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.05:21:23.81#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.05:21:23.81$vck44/valo=6,814.99 2006.173.05:21:23.81#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.05:21:23.81#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.05:21:23.81#ibcon#ireg 17 cls_cnt 0 2006.173.05:21:23.81#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.05:21:23.81#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.05:21:23.81#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.05:21:23.81#ibcon#enter wrdev, iclass 39, count 0 2006.173.05:21:23.81#ibcon#first serial, iclass 39, count 0 2006.173.05:21:23.81#ibcon#enter sib2, iclass 39, count 0 2006.173.05:21:23.81#ibcon#flushed, iclass 39, count 0 2006.173.05:21:23.81#ibcon#about to write, iclass 39, count 0 2006.173.05:21:23.81#ibcon#wrote, iclass 39, count 0 2006.173.05:21:23.81#ibcon#about to read 3, iclass 39, count 0 2006.173.05:21:23.83#ibcon#read 3, iclass 39, count 0 2006.173.05:21:23.83#ibcon#about to read 4, iclass 39, count 0 2006.173.05:21:23.83#ibcon#read 4, iclass 39, count 0 2006.173.05:21:23.83#ibcon#about to read 5, iclass 39, count 0 2006.173.05:21:23.83#ibcon#read 5, iclass 39, count 0 2006.173.05:21:23.83#ibcon#about to read 6, iclass 39, count 0 2006.173.05:21:23.83#ibcon#read 6, iclass 39, count 0 2006.173.05:21:23.83#ibcon#end of sib2, iclass 39, count 0 2006.173.05:21:23.83#ibcon#*mode == 0, iclass 39, count 0 2006.173.05:21:23.83#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.05:21:23.83#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.05:21:23.83#ibcon#*before write, iclass 39, count 0 2006.173.05:21:23.83#ibcon#enter sib2, iclass 39, count 0 2006.173.05:21:23.83#ibcon#flushed, iclass 39, count 0 2006.173.05:21:23.83#ibcon#about to write, iclass 39, count 0 2006.173.05:21:23.83#ibcon#wrote, iclass 39, count 0 2006.173.05:21:23.83#ibcon#about to read 3, iclass 39, count 0 2006.173.05:21:23.87#ibcon#read 3, iclass 39, count 0 2006.173.05:21:23.87#ibcon#about to read 4, iclass 39, count 0 2006.173.05:21:23.87#ibcon#read 4, iclass 39, count 0 2006.173.05:21:23.87#ibcon#about to read 5, iclass 39, count 0 2006.173.05:21:23.87#ibcon#read 5, iclass 39, count 0 2006.173.05:21:23.87#ibcon#about to read 6, iclass 39, count 0 2006.173.05:21:23.87#ibcon#read 6, iclass 39, count 0 2006.173.05:21:23.87#ibcon#end of sib2, iclass 39, count 0 2006.173.05:21:23.87#ibcon#*after write, iclass 39, count 0 2006.173.05:21:23.87#ibcon#*before return 0, iclass 39, count 0 2006.173.05:21:23.87#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.05:21:23.87#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.05:21:23.87#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.05:21:23.87#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.05:21:23.87$vck44/va=6,3 2006.173.05:21:23.87#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.05:21:23.87#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.05:21:23.87#ibcon#ireg 11 cls_cnt 2 2006.173.05:21:23.87#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.05:21:23.93#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.05:21:23.93#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.05:21:23.93#ibcon#enter wrdev, iclass 3, count 2 2006.173.05:21:23.93#ibcon#first serial, iclass 3, count 2 2006.173.05:21:23.93#ibcon#enter sib2, iclass 3, count 2 2006.173.05:21:23.93#ibcon#flushed, iclass 3, count 2 2006.173.05:21:23.93#ibcon#about to write, iclass 3, count 2 2006.173.05:21:23.93#ibcon#wrote, iclass 3, count 2 2006.173.05:21:23.93#ibcon#about to read 3, iclass 3, count 2 2006.173.05:21:23.95#ibcon#read 3, iclass 3, count 2 2006.173.05:21:23.95#ibcon#about to read 4, iclass 3, count 2 2006.173.05:21:23.95#ibcon#read 4, iclass 3, count 2 2006.173.05:21:23.95#ibcon#about to read 5, iclass 3, count 2 2006.173.05:21:23.95#ibcon#read 5, iclass 3, count 2 2006.173.05:21:23.95#ibcon#about to read 6, iclass 3, count 2 2006.173.05:21:23.95#ibcon#read 6, iclass 3, count 2 2006.173.05:21:23.95#ibcon#end of sib2, iclass 3, count 2 2006.173.05:21:23.95#ibcon#*mode == 0, iclass 3, count 2 2006.173.05:21:23.95#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.05:21:23.95#ibcon#[25=AT06-03\r\n] 2006.173.05:21:23.95#ibcon#*before write, iclass 3, count 2 2006.173.05:21:23.95#ibcon#enter sib2, iclass 3, count 2 2006.173.05:21:23.95#ibcon#flushed, iclass 3, count 2 2006.173.05:21:23.95#ibcon#about to write, iclass 3, count 2 2006.173.05:21:23.95#ibcon#wrote, iclass 3, count 2 2006.173.05:21:23.95#ibcon#about to read 3, iclass 3, count 2 2006.173.05:21:23.98#ibcon#read 3, iclass 3, count 2 2006.173.05:21:23.98#ibcon#about to read 4, iclass 3, count 2 2006.173.05:21:23.98#ibcon#read 4, iclass 3, count 2 2006.173.05:21:23.98#ibcon#about to read 5, iclass 3, count 2 2006.173.05:21:23.98#ibcon#read 5, iclass 3, count 2 2006.173.05:21:23.98#ibcon#about to read 6, iclass 3, count 2 2006.173.05:21:23.98#ibcon#read 6, iclass 3, count 2 2006.173.05:21:23.98#ibcon#end of sib2, iclass 3, count 2 2006.173.05:21:23.98#ibcon#*after write, iclass 3, count 2 2006.173.05:21:23.98#ibcon#*before return 0, iclass 3, count 2 2006.173.05:21:23.98#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.05:21:23.98#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.05:21:23.98#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.05:21:23.98#ibcon#ireg 7 cls_cnt 0 2006.173.05:21:23.98#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.05:21:24.10#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.05:21:24.10#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.05:21:24.10#ibcon#enter wrdev, iclass 3, count 0 2006.173.05:21:24.10#ibcon#first serial, iclass 3, count 0 2006.173.05:21:24.10#ibcon#enter sib2, iclass 3, count 0 2006.173.05:21:24.10#ibcon#flushed, iclass 3, count 0 2006.173.05:21:24.10#ibcon#about to write, iclass 3, count 0 2006.173.05:21:24.10#ibcon#wrote, iclass 3, count 0 2006.173.05:21:24.10#ibcon#about to read 3, iclass 3, count 0 2006.173.05:21:24.12#ibcon#read 3, iclass 3, count 0 2006.173.05:21:24.12#ibcon#about to read 4, iclass 3, count 0 2006.173.05:21:24.12#ibcon#read 4, iclass 3, count 0 2006.173.05:21:24.12#ibcon#about to read 5, iclass 3, count 0 2006.173.05:21:24.12#ibcon#read 5, iclass 3, count 0 2006.173.05:21:24.12#ibcon#about to read 6, iclass 3, count 0 2006.173.05:21:24.12#ibcon#read 6, iclass 3, count 0 2006.173.05:21:24.12#ibcon#end of sib2, iclass 3, count 0 2006.173.05:21:24.12#ibcon#*mode == 0, iclass 3, count 0 2006.173.05:21:24.12#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.05:21:24.12#ibcon#[25=USB\r\n] 2006.173.05:21:24.12#ibcon#*before write, iclass 3, count 0 2006.173.05:21:24.12#ibcon#enter sib2, iclass 3, count 0 2006.173.05:21:24.12#ibcon#flushed, iclass 3, count 0 2006.173.05:21:24.12#ibcon#about to write, iclass 3, count 0 2006.173.05:21:24.12#ibcon#wrote, iclass 3, count 0 2006.173.05:21:24.12#ibcon#about to read 3, iclass 3, count 0 2006.173.05:21:24.15#ibcon#read 3, iclass 3, count 0 2006.173.05:21:24.15#ibcon#about to read 4, iclass 3, count 0 2006.173.05:21:24.15#ibcon#read 4, iclass 3, count 0 2006.173.05:21:24.15#ibcon#about to read 5, iclass 3, count 0 2006.173.05:21:24.15#ibcon#read 5, iclass 3, count 0 2006.173.05:21:24.15#ibcon#about to read 6, iclass 3, count 0 2006.173.05:21:24.15#ibcon#read 6, iclass 3, count 0 2006.173.05:21:24.15#ibcon#end of sib2, iclass 3, count 0 2006.173.05:21:24.15#ibcon#*after write, iclass 3, count 0 2006.173.05:21:24.15#ibcon#*before return 0, iclass 3, count 0 2006.173.05:21:24.15#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.05:21:24.15#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.05:21:24.15#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.05:21:24.15#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.05:21:24.15$vck44/valo=7,864.99 2006.173.05:21:24.15#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.05:21:24.15#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.05:21:24.15#ibcon#ireg 17 cls_cnt 0 2006.173.05:21:24.15#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.05:21:24.15#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.05:21:24.15#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.05:21:24.15#ibcon#enter wrdev, iclass 5, count 0 2006.173.05:21:24.15#ibcon#first serial, iclass 5, count 0 2006.173.05:21:24.15#ibcon#enter sib2, iclass 5, count 0 2006.173.05:21:24.15#ibcon#flushed, iclass 5, count 0 2006.173.05:21:24.15#ibcon#about to write, iclass 5, count 0 2006.173.05:21:24.15#ibcon#wrote, iclass 5, count 0 2006.173.05:21:24.15#ibcon#about to read 3, iclass 5, count 0 2006.173.05:21:24.17#ibcon#read 3, iclass 5, count 0 2006.173.05:21:24.17#ibcon#about to read 4, iclass 5, count 0 2006.173.05:21:24.17#ibcon#read 4, iclass 5, count 0 2006.173.05:21:24.17#ibcon#about to read 5, iclass 5, count 0 2006.173.05:21:24.17#ibcon#read 5, iclass 5, count 0 2006.173.05:21:24.17#ibcon#about to read 6, iclass 5, count 0 2006.173.05:21:24.17#ibcon#read 6, iclass 5, count 0 2006.173.05:21:24.17#ibcon#end of sib2, iclass 5, count 0 2006.173.05:21:24.17#ibcon#*mode == 0, iclass 5, count 0 2006.173.05:21:24.17#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.05:21:24.17#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.05:21:24.17#ibcon#*before write, iclass 5, count 0 2006.173.05:21:24.17#ibcon#enter sib2, iclass 5, count 0 2006.173.05:21:24.17#ibcon#flushed, iclass 5, count 0 2006.173.05:21:24.17#ibcon#about to write, iclass 5, count 0 2006.173.05:21:24.17#ibcon#wrote, iclass 5, count 0 2006.173.05:21:24.17#ibcon#about to read 3, iclass 5, count 0 2006.173.05:21:24.21#ibcon#read 3, iclass 5, count 0 2006.173.05:21:24.21#ibcon#about to read 4, iclass 5, count 0 2006.173.05:21:24.21#ibcon#read 4, iclass 5, count 0 2006.173.05:21:24.21#ibcon#about to read 5, iclass 5, count 0 2006.173.05:21:24.21#ibcon#read 5, iclass 5, count 0 2006.173.05:21:24.21#ibcon#about to read 6, iclass 5, count 0 2006.173.05:21:24.21#ibcon#read 6, iclass 5, count 0 2006.173.05:21:24.21#ibcon#end of sib2, iclass 5, count 0 2006.173.05:21:24.21#ibcon#*after write, iclass 5, count 0 2006.173.05:21:24.21#ibcon#*before return 0, iclass 5, count 0 2006.173.05:21:24.21#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.05:21:24.21#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.05:21:24.21#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.05:21:24.21#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.05:21:24.21$vck44/va=7,4 2006.173.05:21:24.21#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.173.05:21:24.21#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.173.05:21:24.21#ibcon#ireg 11 cls_cnt 2 2006.173.05:21:24.21#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.05:21:24.27#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.05:21:24.27#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.05:21:24.27#ibcon#enter wrdev, iclass 7, count 2 2006.173.05:21:24.27#ibcon#first serial, iclass 7, count 2 2006.173.05:21:24.27#ibcon#enter sib2, iclass 7, count 2 2006.173.05:21:24.27#ibcon#flushed, iclass 7, count 2 2006.173.05:21:24.27#ibcon#about to write, iclass 7, count 2 2006.173.05:21:24.27#ibcon#wrote, iclass 7, count 2 2006.173.05:21:24.27#ibcon#about to read 3, iclass 7, count 2 2006.173.05:21:24.29#ibcon#read 3, iclass 7, count 2 2006.173.05:21:24.29#ibcon#about to read 4, iclass 7, count 2 2006.173.05:21:24.29#ibcon#read 4, iclass 7, count 2 2006.173.05:21:24.29#ibcon#about to read 5, iclass 7, count 2 2006.173.05:21:24.29#ibcon#read 5, iclass 7, count 2 2006.173.05:21:24.29#ibcon#about to read 6, iclass 7, count 2 2006.173.05:21:24.29#ibcon#read 6, iclass 7, count 2 2006.173.05:21:24.29#ibcon#end of sib2, iclass 7, count 2 2006.173.05:21:24.29#ibcon#*mode == 0, iclass 7, count 2 2006.173.05:21:24.29#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.173.05:21:24.29#ibcon#[25=AT07-04\r\n] 2006.173.05:21:24.29#ibcon#*before write, iclass 7, count 2 2006.173.05:21:24.29#ibcon#enter sib2, iclass 7, count 2 2006.173.05:21:24.29#ibcon#flushed, iclass 7, count 2 2006.173.05:21:24.29#ibcon#about to write, iclass 7, count 2 2006.173.05:21:24.29#ibcon#wrote, iclass 7, count 2 2006.173.05:21:24.29#ibcon#about to read 3, iclass 7, count 2 2006.173.05:21:24.32#ibcon#read 3, iclass 7, count 2 2006.173.05:21:24.32#ibcon#about to read 4, iclass 7, count 2 2006.173.05:21:24.32#ibcon#read 4, iclass 7, count 2 2006.173.05:21:24.32#ibcon#about to read 5, iclass 7, count 2 2006.173.05:21:24.32#ibcon#read 5, iclass 7, count 2 2006.173.05:21:24.32#ibcon#about to read 6, iclass 7, count 2 2006.173.05:21:24.32#ibcon#read 6, iclass 7, count 2 2006.173.05:21:24.32#ibcon#end of sib2, iclass 7, count 2 2006.173.05:21:24.32#ibcon#*after write, iclass 7, count 2 2006.173.05:21:24.32#ibcon#*before return 0, iclass 7, count 2 2006.173.05:21:24.32#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.05:21:24.41#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.173.05:21:24.41#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.173.05:21:24.41#ibcon#ireg 7 cls_cnt 0 2006.173.05:21:24.41#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.05:21:24.52#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.05:21:24.52#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.05:21:24.52#ibcon#enter wrdev, iclass 7, count 0 2006.173.05:21:24.52#ibcon#first serial, iclass 7, count 0 2006.173.05:21:24.52#ibcon#enter sib2, iclass 7, count 0 2006.173.05:21:24.52#ibcon#flushed, iclass 7, count 0 2006.173.05:21:24.52#ibcon#about to write, iclass 7, count 0 2006.173.05:21:24.52#ibcon#wrote, iclass 7, count 0 2006.173.05:21:24.52#ibcon#about to read 3, iclass 7, count 0 2006.173.05:21:24.54#ibcon#read 3, iclass 7, count 0 2006.173.05:21:24.54#ibcon#about to read 4, iclass 7, count 0 2006.173.05:21:24.54#ibcon#read 4, iclass 7, count 0 2006.173.05:21:24.54#ibcon#about to read 5, iclass 7, count 0 2006.173.05:21:24.54#ibcon#read 5, iclass 7, count 0 2006.173.05:21:24.54#ibcon#about to read 6, iclass 7, count 0 2006.173.05:21:24.54#ibcon#read 6, iclass 7, count 0 2006.173.05:21:24.54#ibcon#end of sib2, iclass 7, count 0 2006.173.05:21:24.54#ibcon#*mode == 0, iclass 7, count 0 2006.173.05:21:24.54#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.05:21:24.54#ibcon#[25=USB\r\n] 2006.173.05:21:24.54#ibcon#*before write, iclass 7, count 0 2006.173.05:21:24.54#ibcon#enter sib2, iclass 7, count 0 2006.173.05:21:24.54#ibcon#flushed, iclass 7, count 0 2006.173.05:21:24.54#ibcon#about to write, iclass 7, count 0 2006.173.05:21:24.54#ibcon#wrote, iclass 7, count 0 2006.173.05:21:24.54#ibcon#about to read 3, iclass 7, count 0 2006.173.05:21:24.57#ibcon#read 3, iclass 7, count 0 2006.173.05:21:24.57#ibcon#about to read 4, iclass 7, count 0 2006.173.05:21:24.57#ibcon#read 4, iclass 7, count 0 2006.173.05:21:24.57#ibcon#about to read 5, iclass 7, count 0 2006.173.05:21:24.57#ibcon#read 5, iclass 7, count 0 2006.173.05:21:24.57#ibcon#about to read 6, iclass 7, count 0 2006.173.05:21:24.57#ibcon#read 6, iclass 7, count 0 2006.173.05:21:24.57#ibcon#end of sib2, iclass 7, count 0 2006.173.05:21:24.57#ibcon#*after write, iclass 7, count 0 2006.173.05:21:24.57#ibcon#*before return 0, iclass 7, count 0 2006.173.05:21:24.57#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.05:21:24.57#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.173.05:21:24.57#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.05:21:24.57#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.05:21:24.57$vck44/valo=8,884.99 2006.173.05:21:24.57#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.05:21:24.57#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.05:21:24.57#ibcon#ireg 17 cls_cnt 0 2006.173.05:21:24.57#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.05:21:24.57#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.05:21:24.57#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.05:21:24.57#ibcon#enter wrdev, iclass 11, count 0 2006.173.05:21:24.57#ibcon#first serial, iclass 11, count 0 2006.173.05:21:24.57#ibcon#enter sib2, iclass 11, count 0 2006.173.05:21:24.57#ibcon#flushed, iclass 11, count 0 2006.173.05:21:24.57#ibcon#about to write, iclass 11, count 0 2006.173.05:21:24.57#ibcon#wrote, iclass 11, count 0 2006.173.05:21:24.57#ibcon#about to read 3, iclass 11, count 0 2006.173.05:21:24.59#ibcon#read 3, iclass 11, count 0 2006.173.05:21:24.59#ibcon#about to read 4, iclass 11, count 0 2006.173.05:21:24.59#ibcon#read 4, iclass 11, count 0 2006.173.05:21:24.59#ibcon#about to read 5, iclass 11, count 0 2006.173.05:21:24.59#ibcon#read 5, iclass 11, count 0 2006.173.05:21:24.59#ibcon#about to read 6, iclass 11, count 0 2006.173.05:21:24.59#ibcon#read 6, iclass 11, count 0 2006.173.05:21:24.59#ibcon#end of sib2, iclass 11, count 0 2006.173.05:21:24.59#ibcon#*mode == 0, iclass 11, count 0 2006.173.05:21:24.59#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.05:21:24.59#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.05:21:24.59#ibcon#*before write, iclass 11, count 0 2006.173.05:21:24.59#ibcon#enter sib2, iclass 11, count 0 2006.173.05:21:24.59#ibcon#flushed, iclass 11, count 0 2006.173.05:21:24.59#ibcon#about to write, iclass 11, count 0 2006.173.05:21:24.59#ibcon#wrote, iclass 11, count 0 2006.173.05:21:24.59#ibcon#about to read 3, iclass 11, count 0 2006.173.05:21:24.63#ibcon#read 3, iclass 11, count 0 2006.173.05:21:24.63#ibcon#about to read 4, iclass 11, count 0 2006.173.05:21:24.63#ibcon#read 4, iclass 11, count 0 2006.173.05:21:24.63#ibcon#about to read 5, iclass 11, count 0 2006.173.05:21:24.63#ibcon#read 5, iclass 11, count 0 2006.173.05:21:24.63#ibcon#about to read 6, iclass 11, count 0 2006.173.05:21:24.63#ibcon#read 6, iclass 11, count 0 2006.173.05:21:24.63#ibcon#end of sib2, iclass 11, count 0 2006.173.05:21:24.63#ibcon#*after write, iclass 11, count 0 2006.173.05:21:24.63#ibcon#*before return 0, iclass 11, count 0 2006.173.05:21:24.63#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.05:21:24.63#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.05:21:24.63#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.05:21:24.63#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.05:21:24.63$vck44/va=8,4 2006.173.05:21:24.63#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.173.05:21:24.63#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.173.05:21:24.63#ibcon#ireg 11 cls_cnt 2 2006.173.05:21:24.63#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.05:21:24.69#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.05:21:24.69#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.05:21:24.69#ibcon#enter wrdev, iclass 13, count 2 2006.173.05:21:24.69#ibcon#first serial, iclass 13, count 2 2006.173.05:21:24.69#ibcon#enter sib2, iclass 13, count 2 2006.173.05:21:24.69#ibcon#flushed, iclass 13, count 2 2006.173.05:21:24.69#ibcon#about to write, iclass 13, count 2 2006.173.05:21:24.69#ibcon#wrote, iclass 13, count 2 2006.173.05:21:24.69#ibcon#about to read 3, iclass 13, count 2 2006.173.05:21:24.71#ibcon#read 3, iclass 13, count 2 2006.173.05:21:24.71#ibcon#about to read 4, iclass 13, count 2 2006.173.05:21:24.71#ibcon#read 4, iclass 13, count 2 2006.173.05:21:24.71#ibcon#about to read 5, iclass 13, count 2 2006.173.05:21:24.71#ibcon#read 5, iclass 13, count 2 2006.173.05:21:24.71#ibcon#about to read 6, iclass 13, count 2 2006.173.05:21:24.71#ibcon#read 6, iclass 13, count 2 2006.173.05:21:24.71#ibcon#end of sib2, iclass 13, count 2 2006.173.05:21:24.71#ibcon#*mode == 0, iclass 13, count 2 2006.173.05:21:24.71#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.173.05:21:24.71#ibcon#[25=AT08-04\r\n] 2006.173.05:21:24.71#ibcon#*before write, iclass 13, count 2 2006.173.05:21:24.71#ibcon#enter sib2, iclass 13, count 2 2006.173.05:21:24.71#ibcon#flushed, iclass 13, count 2 2006.173.05:21:24.71#ibcon#about to write, iclass 13, count 2 2006.173.05:21:24.71#ibcon#wrote, iclass 13, count 2 2006.173.05:21:24.71#ibcon#about to read 3, iclass 13, count 2 2006.173.05:21:24.74#ibcon#read 3, iclass 13, count 2 2006.173.05:21:24.74#ibcon#about to read 4, iclass 13, count 2 2006.173.05:21:24.74#ibcon#read 4, iclass 13, count 2 2006.173.05:21:24.74#ibcon#about to read 5, iclass 13, count 2 2006.173.05:21:24.74#ibcon#read 5, iclass 13, count 2 2006.173.05:21:24.74#ibcon#about to read 6, iclass 13, count 2 2006.173.05:21:24.74#ibcon#read 6, iclass 13, count 2 2006.173.05:21:24.74#ibcon#end of sib2, iclass 13, count 2 2006.173.05:21:24.74#ibcon#*after write, iclass 13, count 2 2006.173.05:21:24.74#ibcon#*before return 0, iclass 13, count 2 2006.173.05:21:24.74#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.05:21:24.74#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.173.05:21:24.74#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.173.05:21:24.74#ibcon#ireg 7 cls_cnt 0 2006.173.05:21:24.74#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.05:21:24.86#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.05:21:24.86#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.05:21:24.86#ibcon#enter wrdev, iclass 13, count 0 2006.173.05:21:24.86#ibcon#first serial, iclass 13, count 0 2006.173.05:21:24.86#ibcon#enter sib2, iclass 13, count 0 2006.173.05:21:24.86#ibcon#flushed, iclass 13, count 0 2006.173.05:21:24.86#ibcon#about to write, iclass 13, count 0 2006.173.05:21:24.86#ibcon#wrote, iclass 13, count 0 2006.173.05:21:24.86#ibcon#about to read 3, iclass 13, count 0 2006.173.05:21:24.88#ibcon#read 3, iclass 13, count 0 2006.173.05:21:24.88#ibcon#about to read 4, iclass 13, count 0 2006.173.05:21:24.88#ibcon#read 4, iclass 13, count 0 2006.173.05:21:24.88#ibcon#about to read 5, iclass 13, count 0 2006.173.05:21:24.88#ibcon#read 5, iclass 13, count 0 2006.173.05:21:24.88#ibcon#about to read 6, iclass 13, count 0 2006.173.05:21:24.88#ibcon#read 6, iclass 13, count 0 2006.173.05:21:24.88#ibcon#end of sib2, iclass 13, count 0 2006.173.05:21:24.88#ibcon#*mode == 0, iclass 13, count 0 2006.173.05:21:24.88#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.05:21:24.88#ibcon#[25=USB\r\n] 2006.173.05:21:24.88#ibcon#*before write, iclass 13, count 0 2006.173.05:21:24.88#ibcon#enter sib2, iclass 13, count 0 2006.173.05:21:24.88#ibcon#flushed, iclass 13, count 0 2006.173.05:21:24.88#ibcon#about to write, iclass 13, count 0 2006.173.05:21:24.88#ibcon#wrote, iclass 13, count 0 2006.173.05:21:24.88#ibcon#about to read 3, iclass 13, count 0 2006.173.05:21:24.91#ibcon#read 3, iclass 13, count 0 2006.173.05:21:24.91#ibcon#about to read 4, iclass 13, count 0 2006.173.05:21:24.91#ibcon#read 4, iclass 13, count 0 2006.173.05:21:24.91#ibcon#about to read 5, iclass 13, count 0 2006.173.05:21:24.91#ibcon#read 5, iclass 13, count 0 2006.173.05:21:24.91#ibcon#about to read 6, iclass 13, count 0 2006.173.05:21:24.91#ibcon#read 6, iclass 13, count 0 2006.173.05:21:24.91#ibcon#end of sib2, iclass 13, count 0 2006.173.05:21:24.91#ibcon#*after write, iclass 13, count 0 2006.173.05:21:24.91#ibcon#*before return 0, iclass 13, count 0 2006.173.05:21:24.91#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.05:21:24.91#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.173.05:21:24.91#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.05:21:24.91#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.05:21:24.91$vck44/vblo=1,629.99 2006.173.05:21:24.91#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.05:21:24.91#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.05:21:24.91#ibcon#ireg 17 cls_cnt 0 2006.173.05:21:24.91#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.05:21:24.91#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.05:21:24.91#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.05:21:24.91#ibcon#enter wrdev, iclass 15, count 0 2006.173.05:21:24.91#ibcon#first serial, iclass 15, count 0 2006.173.05:21:24.91#ibcon#enter sib2, iclass 15, count 0 2006.173.05:21:24.91#ibcon#flushed, iclass 15, count 0 2006.173.05:21:24.91#ibcon#about to write, iclass 15, count 0 2006.173.05:21:24.91#ibcon#wrote, iclass 15, count 0 2006.173.05:21:24.91#ibcon#about to read 3, iclass 15, count 0 2006.173.05:21:24.93#ibcon#read 3, iclass 15, count 0 2006.173.05:21:24.93#ibcon#about to read 4, iclass 15, count 0 2006.173.05:21:24.93#ibcon#read 4, iclass 15, count 0 2006.173.05:21:24.93#ibcon#about to read 5, iclass 15, count 0 2006.173.05:21:24.93#ibcon#read 5, iclass 15, count 0 2006.173.05:21:24.93#ibcon#about to read 6, iclass 15, count 0 2006.173.05:21:24.93#ibcon#read 6, iclass 15, count 0 2006.173.05:21:24.93#ibcon#end of sib2, iclass 15, count 0 2006.173.05:21:24.93#ibcon#*mode == 0, iclass 15, count 0 2006.173.05:21:24.93#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.05:21:24.93#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.05:21:24.93#ibcon#*before write, iclass 15, count 0 2006.173.05:21:24.93#ibcon#enter sib2, iclass 15, count 0 2006.173.05:21:24.93#ibcon#flushed, iclass 15, count 0 2006.173.05:21:24.93#ibcon#about to write, iclass 15, count 0 2006.173.05:21:24.93#ibcon#wrote, iclass 15, count 0 2006.173.05:21:24.93#ibcon#about to read 3, iclass 15, count 0 2006.173.05:21:24.97#ibcon#read 3, iclass 15, count 0 2006.173.05:21:24.97#ibcon#about to read 4, iclass 15, count 0 2006.173.05:21:24.97#ibcon#read 4, iclass 15, count 0 2006.173.05:21:24.97#ibcon#about to read 5, iclass 15, count 0 2006.173.05:21:24.97#ibcon#read 5, iclass 15, count 0 2006.173.05:21:24.97#ibcon#about to read 6, iclass 15, count 0 2006.173.05:21:24.97#ibcon#read 6, iclass 15, count 0 2006.173.05:21:24.97#ibcon#end of sib2, iclass 15, count 0 2006.173.05:21:24.97#ibcon#*after write, iclass 15, count 0 2006.173.05:21:24.97#ibcon#*before return 0, iclass 15, count 0 2006.173.05:21:24.97#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.05:21:24.97#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.05:21:24.97#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.05:21:24.97#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.05:21:24.97$vck44/vb=1,4 2006.173.05:21:24.97#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.05:21:24.97#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.05:21:24.97#ibcon#ireg 11 cls_cnt 2 2006.173.05:21:24.97#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.05:21:24.97#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.05:21:24.97#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.05:21:24.97#ibcon#enter wrdev, iclass 17, count 2 2006.173.05:21:24.97#ibcon#first serial, iclass 17, count 2 2006.173.05:21:24.97#ibcon#enter sib2, iclass 17, count 2 2006.173.05:21:24.97#ibcon#flushed, iclass 17, count 2 2006.173.05:21:24.97#ibcon#about to write, iclass 17, count 2 2006.173.05:21:24.97#ibcon#wrote, iclass 17, count 2 2006.173.05:21:24.97#ibcon#about to read 3, iclass 17, count 2 2006.173.05:21:24.99#ibcon#read 3, iclass 17, count 2 2006.173.05:21:24.99#ibcon#about to read 4, iclass 17, count 2 2006.173.05:21:24.99#ibcon#read 4, iclass 17, count 2 2006.173.05:21:24.99#ibcon#about to read 5, iclass 17, count 2 2006.173.05:21:24.99#ibcon#read 5, iclass 17, count 2 2006.173.05:21:24.99#ibcon#about to read 6, iclass 17, count 2 2006.173.05:21:24.99#ibcon#read 6, iclass 17, count 2 2006.173.05:21:24.99#ibcon#end of sib2, iclass 17, count 2 2006.173.05:21:24.99#ibcon#*mode == 0, iclass 17, count 2 2006.173.05:21:24.99#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.05:21:24.99#ibcon#[27=AT01-04\r\n] 2006.173.05:21:24.99#ibcon#*before write, iclass 17, count 2 2006.173.05:21:24.99#ibcon#enter sib2, iclass 17, count 2 2006.173.05:21:24.99#ibcon#flushed, iclass 17, count 2 2006.173.05:21:24.99#ibcon#about to write, iclass 17, count 2 2006.173.05:21:24.99#ibcon#wrote, iclass 17, count 2 2006.173.05:21:24.99#ibcon#about to read 3, iclass 17, count 2 2006.173.05:21:25.02#ibcon#read 3, iclass 17, count 2 2006.173.05:21:25.02#ibcon#about to read 4, iclass 17, count 2 2006.173.05:21:25.02#ibcon#read 4, iclass 17, count 2 2006.173.05:21:25.02#ibcon#about to read 5, iclass 17, count 2 2006.173.05:21:25.02#ibcon#read 5, iclass 17, count 2 2006.173.05:21:25.02#ibcon#about to read 6, iclass 17, count 2 2006.173.05:21:25.02#ibcon#read 6, iclass 17, count 2 2006.173.05:21:25.02#ibcon#end of sib2, iclass 17, count 2 2006.173.05:21:25.02#ibcon#*after write, iclass 17, count 2 2006.173.05:21:25.02#ibcon#*before return 0, iclass 17, count 2 2006.173.05:21:25.02#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.05:21:25.02#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.05:21:25.02#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.05:21:25.02#ibcon#ireg 7 cls_cnt 0 2006.173.05:21:25.02#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.05:21:25.14#abcon#<5=/14 0.9 2.2 23.51 801005.6\r\n> 2006.173.05:21:25.14#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.05:21:25.14#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.05:21:25.14#ibcon#enter wrdev, iclass 17, count 0 2006.173.05:21:25.14#ibcon#first serial, iclass 17, count 0 2006.173.05:21:25.14#ibcon#enter sib2, iclass 17, count 0 2006.173.05:21:25.14#ibcon#flushed, iclass 17, count 0 2006.173.05:21:25.14#ibcon#about to write, iclass 17, count 0 2006.173.05:21:25.14#ibcon#wrote, iclass 17, count 0 2006.173.05:21:25.14#ibcon#about to read 3, iclass 17, count 0 2006.173.05:21:25.16#ibcon#read 3, iclass 17, count 0 2006.173.05:21:25.16#ibcon#about to read 4, iclass 17, count 0 2006.173.05:21:25.16#ibcon#read 4, iclass 17, count 0 2006.173.05:21:25.16#ibcon#about to read 5, iclass 17, count 0 2006.173.05:21:25.16#ibcon#read 5, iclass 17, count 0 2006.173.05:21:25.16#ibcon#about to read 6, iclass 17, count 0 2006.173.05:21:25.16#ibcon#read 6, iclass 17, count 0 2006.173.05:21:25.16#ibcon#end of sib2, iclass 17, count 0 2006.173.05:21:25.16#ibcon#*mode == 0, iclass 17, count 0 2006.173.05:21:25.16#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.05:21:25.16#ibcon#[27=USB\r\n] 2006.173.05:21:25.16#ibcon#*before write, iclass 17, count 0 2006.173.05:21:25.16#ibcon#enter sib2, iclass 17, count 0 2006.173.05:21:25.16#ibcon#flushed, iclass 17, count 0 2006.173.05:21:25.16#ibcon#about to write, iclass 17, count 0 2006.173.05:21:25.16#ibcon#wrote, iclass 17, count 0 2006.173.05:21:25.16#ibcon#about to read 3, iclass 17, count 0 2006.173.05:21:25.16#abcon#{5=INTERFACE CLEAR} 2006.173.05:21:25.19#ibcon#read 3, iclass 17, count 0 2006.173.05:21:25.19#ibcon#about to read 4, iclass 17, count 0 2006.173.05:21:25.19#ibcon#read 4, iclass 17, count 0 2006.173.05:21:25.19#ibcon#about to read 5, iclass 17, count 0 2006.173.05:21:25.19#ibcon#read 5, iclass 17, count 0 2006.173.05:21:25.19#ibcon#about to read 6, iclass 17, count 0 2006.173.05:21:25.19#ibcon#read 6, iclass 17, count 0 2006.173.05:21:25.19#ibcon#end of sib2, iclass 17, count 0 2006.173.05:21:25.19#ibcon#*after write, iclass 17, count 0 2006.173.05:21:25.19#ibcon#*before return 0, iclass 17, count 0 2006.173.05:21:25.19#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.05:21:25.19#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.05:21:25.19#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.05:21:25.19#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.05:21:25.19$vck44/vblo=2,634.99 2006.173.05:21:25.19#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.05:21:25.19#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.05:21:25.19#ibcon#ireg 17 cls_cnt 0 2006.173.05:21:25.19#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.05:21:25.19#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.05:21:25.19#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.05:21:25.19#ibcon#enter wrdev, iclass 22, count 0 2006.173.05:21:25.19#ibcon#first serial, iclass 22, count 0 2006.173.05:21:25.19#ibcon#enter sib2, iclass 22, count 0 2006.173.05:21:25.19#ibcon#flushed, iclass 22, count 0 2006.173.05:21:25.19#ibcon#about to write, iclass 22, count 0 2006.173.05:21:25.19#ibcon#wrote, iclass 22, count 0 2006.173.05:21:25.19#ibcon#about to read 3, iclass 22, count 0 2006.173.05:21:25.21#ibcon#read 3, iclass 22, count 0 2006.173.05:21:25.21#ibcon#about to read 4, iclass 22, count 0 2006.173.05:21:25.21#ibcon#read 4, iclass 22, count 0 2006.173.05:21:25.21#ibcon#about to read 5, iclass 22, count 0 2006.173.05:21:25.21#ibcon#read 5, iclass 22, count 0 2006.173.05:21:25.21#ibcon#about to read 6, iclass 22, count 0 2006.173.05:21:25.21#ibcon#read 6, iclass 22, count 0 2006.173.05:21:25.21#ibcon#end of sib2, iclass 22, count 0 2006.173.05:21:25.21#ibcon#*mode == 0, iclass 22, count 0 2006.173.05:21:25.21#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.05:21:25.21#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.05:21:25.21#ibcon#*before write, iclass 22, count 0 2006.173.05:21:25.21#ibcon#enter sib2, iclass 22, count 0 2006.173.05:21:25.21#ibcon#flushed, iclass 22, count 0 2006.173.05:21:25.21#ibcon#about to write, iclass 22, count 0 2006.173.05:21:25.21#ibcon#wrote, iclass 22, count 0 2006.173.05:21:25.21#ibcon#about to read 3, iclass 22, count 0 2006.173.05:21:25.22#abcon#[5=S1D000X0/0*\r\n] 2006.173.05:21:25.25#ibcon#read 3, iclass 22, count 0 2006.173.05:21:25.25#ibcon#about to read 4, iclass 22, count 0 2006.173.05:21:25.25#ibcon#read 4, iclass 22, count 0 2006.173.05:21:25.25#ibcon#about to read 5, iclass 22, count 0 2006.173.05:21:25.25#ibcon#read 5, iclass 22, count 0 2006.173.05:21:25.25#ibcon#about to read 6, iclass 22, count 0 2006.173.05:21:25.25#ibcon#read 6, iclass 22, count 0 2006.173.05:21:25.25#ibcon#end of sib2, iclass 22, count 0 2006.173.05:21:25.25#ibcon#*after write, iclass 22, count 0 2006.173.05:21:25.25#ibcon#*before return 0, iclass 22, count 0 2006.173.05:21:25.25#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.05:21:25.25#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.05:21:25.25#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.05:21:25.25#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.05:21:25.25$vck44/vb=2,4 2006.173.05:21:25.25#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.05:21:25.25#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.05:21:25.25#ibcon#ireg 11 cls_cnt 2 2006.173.05:21:25.25#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.05:21:25.31#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.05:21:25.31#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.05:21:25.31#ibcon#enter wrdev, iclass 25, count 2 2006.173.05:21:25.31#ibcon#first serial, iclass 25, count 2 2006.173.05:21:25.31#ibcon#enter sib2, iclass 25, count 2 2006.173.05:21:25.31#ibcon#flushed, iclass 25, count 2 2006.173.05:21:25.31#ibcon#about to write, iclass 25, count 2 2006.173.05:21:25.31#ibcon#wrote, iclass 25, count 2 2006.173.05:21:25.31#ibcon#about to read 3, iclass 25, count 2 2006.173.05:21:25.33#ibcon#read 3, iclass 25, count 2 2006.173.05:21:25.33#ibcon#about to read 4, iclass 25, count 2 2006.173.05:21:25.33#ibcon#read 4, iclass 25, count 2 2006.173.05:21:25.33#ibcon#about to read 5, iclass 25, count 2 2006.173.05:21:25.33#ibcon#read 5, iclass 25, count 2 2006.173.05:21:25.33#ibcon#about to read 6, iclass 25, count 2 2006.173.05:21:25.33#ibcon#read 6, iclass 25, count 2 2006.173.05:21:25.33#ibcon#end of sib2, iclass 25, count 2 2006.173.05:21:25.33#ibcon#*mode == 0, iclass 25, count 2 2006.173.05:21:25.33#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.05:21:25.33#ibcon#[27=AT02-04\r\n] 2006.173.05:21:25.33#ibcon#*before write, iclass 25, count 2 2006.173.05:21:25.33#ibcon#enter sib2, iclass 25, count 2 2006.173.05:21:25.33#ibcon#flushed, iclass 25, count 2 2006.173.05:21:25.33#ibcon#about to write, iclass 25, count 2 2006.173.05:21:25.33#ibcon#wrote, iclass 25, count 2 2006.173.05:21:25.33#ibcon#about to read 3, iclass 25, count 2 2006.173.05:21:25.36#ibcon#read 3, iclass 25, count 2 2006.173.05:21:25.36#ibcon#about to read 4, iclass 25, count 2 2006.173.05:21:25.36#ibcon#read 4, iclass 25, count 2 2006.173.05:21:25.36#ibcon#about to read 5, iclass 25, count 2 2006.173.05:21:25.36#ibcon#read 5, iclass 25, count 2 2006.173.05:21:25.36#ibcon#about to read 6, iclass 25, count 2 2006.173.05:21:25.38#ibcon#read 6, iclass 25, count 2 2006.173.05:21:25.38#ibcon#end of sib2, iclass 25, count 2 2006.173.05:21:25.38#ibcon#*after write, iclass 25, count 2 2006.173.05:21:25.38#ibcon#*before return 0, iclass 25, count 2 2006.173.05:21:25.38#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.05:21:25.38#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.05:21:25.38#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.05:21:25.38#ibcon#ireg 7 cls_cnt 0 2006.173.05:21:25.38#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.05:21:25.49#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.05:21:25.49#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.05:21:25.49#ibcon#enter wrdev, iclass 25, count 0 2006.173.05:21:25.49#ibcon#first serial, iclass 25, count 0 2006.173.05:21:25.49#ibcon#enter sib2, iclass 25, count 0 2006.173.05:21:25.49#ibcon#flushed, iclass 25, count 0 2006.173.05:21:25.49#ibcon#about to write, iclass 25, count 0 2006.173.05:21:25.49#ibcon#wrote, iclass 25, count 0 2006.173.05:21:25.49#ibcon#about to read 3, iclass 25, count 0 2006.173.05:21:25.51#ibcon#read 3, iclass 25, count 0 2006.173.05:21:25.51#ibcon#about to read 4, iclass 25, count 0 2006.173.05:21:25.51#ibcon#read 4, iclass 25, count 0 2006.173.05:21:25.51#ibcon#about to read 5, iclass 25, count 0 2006.173.05:21:25.51#ibcon#read 5, iclass 25, count 0 2006.173.05:21:25.51#ibcon#about to read 6, iclass 25, count 0 2006.173.05:21:25.51#ibcon#read 6, iclass 25, count 0 2006.173.05:21:25.51#ibcon#end of sib2, iclass 25, count 0 2006.173.05:21:25.51#ibcon#*mode == 0, iclass 25, count 0 2006.173.05:21:25.51#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.05:21:25.51#ibcon#[27=USB\r\n] 2006.173.05:21:25.51#ibcon#*before write, iclass 25, count 0 2006.173.05:21:25.51#ibcon#enter sib2, iclass 25, count 0 2006.173.05:21:25.51#ibcon#flushed, iclass 25, count 0 2006.173.05:21:25.51#ibcon#about to write, iclass 25, count 0 2006.173.05:21:25.51#ibcon#wrote, iclass 25, count 0 2006.173.05:21:25.51#ibcon#about to read 3, iclass 25, count 0 2006.173.05:21:25.54#ibcon#read 3, iclass 25, count 0 2006.173.05:21:25.54#ibcon#about to read 4, iclass 25, count 0 2006.173.05:21:25.54#ibcon#read 4, iclass 25, count 0 2006.173.05:21:25.54#ibcon#about to read 5, iclass 25, count 0 2006.173.05:21:25.54#ibcon#read 5, iclass 25, count 0 2006.173.05:21:25.54#ibcon#about to read 6, iclass 25, count 0 2006.173.05:21:25.54#ibcon#read 6, iclass 25, count 0 2006.173.05:21:25.54#ibcon#end of sib2, iclass 25, count 0 2006.173.05:21:25.54#ibcon#*after write, iclass 25, count 0 2006.173.05:21:25.54#ibcon#*before return 0, iclass 25, count 0 2006.173.05:21:25.54#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.05:21:25.54#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.05:21:25.54#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.05:21:25.54#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.05:21:25.54$vck44/vblo=3,649.99 2006.173.05:21:25.54#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.05:21:25.54#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.05:21:25.54#ibcon#ireg 17 cls_cnt 0 2006.173.05:21:25.54#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.05:21:25.54#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.05:21:25.54#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.05:21:25.54#ibcon#enter wrdev, iclass 27, count 0 2006.173.05:21:25.54#ibcon#first serial, iclass 27, count 0 2006.173.05:21:25.54#ibcon#enter sib2, iclass 27, count 0 2006.173.05:21:25.54#ibcon#flushed, iclass 27, count 0 2006.173.05:21:25.54#ibcon#about to write, iclass 27, count 0 2006.173.05:21:25.54#ibcon#wrote, iclass 27, count 0 2006.173.05:21:25.54#ibcon#about to read 3, iclass 27, count 0 2006.173.05:21:25.56#ibcon#read 3, iclass 27, count 0 2006.173.05:21:25.56#ibcon#about to read 4, iclass 27, count 0 2006.173.05:21:25.56#ibcon#read 4, iclass 27, count 0 2006.173.05:21:25.56#ibcon#about to read 5, iclass 27, count 0 2006.173.05:21:25.56#ibcon#read 5, iclass 27, count 0 2006.173.05:21:25.56#ibcon#about to read 6, iclass 27, count 0 2006.173.05:21:25.56#ibcon#read 6, iclass 27, count 0 2006.173.05:21:25.56#ibcon#end of sib2, iclass 27, count 0 2006.173.05:21:25.56#ibcon#*mode == 0, iclass 27, count 0 2006.173.05:21:25.56#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.05:21:25.56#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.05:21:25.56#ibcon#*before write, iclass 27, count 0 2006.173.05:21:25.56#ibcon#enter sib2, iclass 27, count 0 2006.173.05:21:25.56#ibcon#flushed, iclass 27, count 0 2006.173.05:21:25.56#ibcon#about to write, iclass 27, count 0 2006.173.05:21:25.56#ibcon#wrote, iclass 27, count 0 2006.173.05:21:25.56#ibcon#about to read 3, iclass 27, count 0 2006.173.05:21:25.60#ibcon#read 3, iclass 27, count 0 2006.173.05:21:25.60#ibcon#about to read 4, iclass 27, count 0 2006.173.05:21:25.60#ibcon#read 4, iclass 27, count 0 2006.173.05:21:25.60#ibcon#about to read 5, iclass 27, count 0 2006.173.05:21:25.60#ibcon#read 5, iclass 27, count 0 2006.173.05:21:25.60#ibcon#about to read 6, iclass 27, count 0 2006.173.05:21:25.60#ibcon#read 6, iclass 27, count 0 2006.173.05:21:25.60#ibcon#end of sib2, iclass 27, count 0 2006.173.05:21:25.60#ibcon#*after write, iclass 27, count 0 2006.173.05:21:25.60#ibcon#*before return 0, iclass 27, count 0 2006.173.05:21:25.60#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.05:21:25.60#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.05:21:25.60#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.05:21:25.60#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.05:21:25.60$vck44/vb=3,4 2006.173.05:21:25.60#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.05:21:25.60#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.05:21:25.60#ibcon#ireg 11 cls_cnt 2 2006.173.05:21:25.60#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.05:21:25.66#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.05:21:25.66#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.05:21:25.66#ibcon#enter wrdev, iclass 29, count 2 2006.173.05:21:25.66#ibcon#first serial, iclass 29, count 2 2006.173.05:21:25.66#ibcon#enter sib2, iclass 29, count 2 2006.173.05:21:25.66#ibcon#flushed, iclass 29, count 2 2006.173.05:21:25.66#ibcon#about to write, iclass 29, count 2 2006.173.05:21:25.66#ibcon#wrote, iclass 29, count 2 2006.173.05:21:25.66#ibcon#about to read 3, iclass 29, count 2 2006.173.05:21:25.68#ibcon#read 3, iclass 29, count 2 2006.173.05:21:25.68#ibcon#about to read 4, iclass 29, count 2 2006.173.05:21:25.68#ibcon#read 4, iclass 29, count 2 2006.173.05:21:25.68#ibcon#about to read 5, iclass 29, count 2 2006.173.05:21:25.68#ibcon#read 5, iclass 29, count 2 2006.173.05:21:25.68#ibcon#about to read 6, iclass 29, count 2 2006.173.05:21:25.68#ibcon#read 6, iclass 29, count 2 2006.173.05:21:25.68#ibcon#end of sib2, iclass 29, count 2 2006.173.05:21:25.68#ibcon#*mode == 0, iclass 29, count 2 2006.173.05:21:25.68#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.05:21:25.68#ibcon#[27=AT03-04\r\n] 2006.173.05:21:25.68#ibcon#*before write, iclass 29, count 2 2006.173.05:21:25.68#ibcon#enter sib2, iclass 29, count 2 2006.173.05:21:25.68#ibcon#flushed, iclass 29, count 2 2006.173.05:21:25.68#ibcon#about to write, iclass 29, count 2 2006.173.05:21:25.68#ibcon#wrote, iclass 29, count 2 2006.173.05:21:25.68#ibcon#about to read 3, iclass 29, count 2 2006.173.05:21:25.71#ibcon#read 3, iclass 29, count 2 2006.173.05:21:25.71#ibcon#about to read 4, iclass 29, count 2 2006.173.05:21:25.71#ibcon#read 4, iclass 29, count 2 2006.173.05:21:25.71#ibcon#about to read 5, iclass 29, count 2 2006.173.05:21:25.71#ibcon#read 5, iclass 29, count 2 2006.173.05:21:25.71#ibcon#about to read 6, iclass 29, count 2 2006.173.05:21:25.71#ibcon#read 6, iclass 29, count 2 2006.173.05:21:25.71#ibcon#end of sib2, iclass 29, count 2 2006.173.05:21:25.71#ibcon#*after write, iclass 29, count 2 2006.173.05:21:25.71#ibcon#*before return 0, iclass 29, count 2 2006.173.05:21:25.71#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.05:21:25.71#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.05:21:25.71#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.05:21:25.71#ibcon#ireg 7 cls_cnt 0 2006.173.05:21:25.71#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.05:21:25.83#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.05:21:25.83#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.05:21:25.83#ibcon#enter wrdev, iclass 29, count 0 2006.173.05:21:25.83#ibcon#first serial, iclass 29, count 0 2006.173.05:21:25.83#ibcon#enter sib2, iclass 29, count 0 2006.173.05:21:25.83#ibcon#flushed, iclass 29, count 0 2006.173.05:21:25.83#ibcon#about to write, iclass 29, count 0 2006.173.05:21:25.83#ibcon#wrote, iclass 29, count 0 2006.173.05:21:25.83#ibcon#about to read 3, iclass 29, count 0 2006.173.05:21:25.85#ibcon#read 3, iclass 29, count 0 2006.173.05:21:25.85#ibcon#about to read 4, iclass 29, count 0 2006.173.05:21:25.85#ibcon#read 4, iclass 29, count 0 2006.173.05:21:25.85#ibcon#about to read 5, iclass 29, count 0 2006.173.05:21:25.85#ibcon#read 5, iclass 29, count 0 2006.173.05:21:25.85#ibcon#about to read 6, iclass 29, count 0 2006.173.05:21:25.85#ibcon#read 6, iclass 29, count 0 2006.173.05:21:25.85#ibcon#end of sib2, iclass 29, count 0 2006.173.05:21:25.85#ibcon#*mode == 0, iclass 29, count 0 2006.173.05:21:25.85#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.05:21:25.85#ibcon#[27=USB\r\n] 2006.173.05:21:25.85#ibcon#*before write, iclass 29, count 0 2006.173.05:21:25.85#ibcon#enter sib2, iclass 29, count 0 2006.173.05:21:25.85#ibcon#flushed, iclass 29, count 0 2006.173.05:21:25.85#ibcon#about to write, iclass 29, count 0 2006.173.05:21:25.85#ibcon#wrote, iclass 29, count 0 2006.173.05:21:25.85#ibcon#about to read 3, iclass 29, count 0 2006.173.05:21:25.88#ibcon#read 3, iclass 29, count 0 2006.173.05:21:25.88#ibcon#about to read 4, iclass 29, count 0 2006.173.05:21:25.88#ibcon#read 4, iclass 29, count 0 2006.173.05:21:25.88#ibcon#about to read 5, iclass 29, count 0 2006.173.05:21:25.88#ibcon#read 5, iclass 29, count 0 2006.173.05:21:25.88#ibcon#about to read 6, iclass 29, count 0 2006.173.05:21:25.88#ibcon#read 6, iclass 29, count 0 2006.173.05:21:25.88#ibcon#end of sib2, iclass 29, count 0 2006.173.05:21:25.88#ibcon#*after write, iclass 29, count 0 2006.173.05:21:25.88#ibcon#*before return 0, iclass 29, count 0 2006.173.05:21:25.88#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.05:21:25.88#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.05:21:25.88#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.05:21:25.88#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.05:21:25.88$vck44/vblo=4,679.99 2006.173.05:21:25.88#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.05:21:25.88#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.05:21:25.88#ibcon#ireg 17 cls_cnt 0 2006.173.05:21:25.88#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.05:21:25.88#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.05:21:25.88#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.05:21:25.88#ibcon#enter wrdev, iclass 31, count 0 2006.173.05:21:25.88#ibcon#first serial, iclass 31, count 0 2006.173.05:21:25.88#ibcon#enter sib2, iclass 31, count 0 2006.173.05:21:25.88#ibcon#flushed, iclass 31, count 0 2006.173.05:21:25.88#ibcon#about to write, iclass 31, count 0 2006.173.05:21:25.88#ibcon#wrote, iclass 31, count 0 2006.173.05:21:25.88#ibcon#about to read 3, iclass 31, count 0 2006.173.05:21:25.90#ibcon#read 3, iclass 31, count 0 2006.173.05:21:25.90#ibcon#about to read 4, iclass 31, count 0 2006.173.05:21:25.90#ibcon#read 4, iclass 31, count 0 2006.173.05:21:25.90#ibcon#about to read 5, iclass 31, count 0 2006.173.05:21:25.90#ibcon#read 5, iclass 31, count 0 2006.173.05:21:25.90#ibcon#about to read 6, iclass 31, count 0 2006.173.05:21:25.90#ibcon#read 6, iclass 31, count 0 2006.173.05:21:25.90#ibcon#end of sib2, iclass 31, count 0 2006.173.05:21:25.90#ibcon#*mode == 0, iclass 31, count 0 2006.173.05:21:25.90#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.05:21:25.90#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.05:21:25.90#ibcon#*before write, iclass 31, count 0 2006.173.05:21:25.90#ibcon#enter sib2, iclass 31, count 0 2006.173.05:21:25.90#ibcon#flushed, iclass 31, count 0 2006.173.05:21:25.90#ibcon#about to write, iclass 31, count 0 2006.173.05:21:25.90#ibcon#wrote, iclass 31, count 0 2006.173.05:21:25.90#ibcon#about to read 3, iclass 31, count 0 2006.173.05:21:25.94#ibcon#read 3, iclass 31, count 0 2006.173.05:21:25.94#ibcon#about to read 4, iclass 31, count 0 2006.173.05:21:25.94#ibcon#read 4, iclass 31, count 0 2006.173.05:21:25.94#ibcon#about to read 5, iclass 31, count 0 2006.173.05:21:25.94#ibcon#read 5, iclass 31, count 0 2006.173.05:21:25.94#ibcon#about to read 6, iclass 31, count 0 2006.173.05:21:25.94#ibcon#read 6, iclass 31, count 0 2006.173.05:21:25.94#ibcon#end of sib2, iclass 31, count 0 2006.173.05:21:25.94#ibcon#*after write, iclass 31, count 0 2006.173.05:21:25.94#ibcon#*before return 0, iclass 31, count 0 2006.173.05:21:25.94#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.05:21:25.94#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.05:21:25.94#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.05:21:25.94#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.05:21:25.94$vck44/vb=4,4 2006.173.05:21:25.94#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.173.05:21:25.94#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.173.05:21:25.94#ibcon#ireg 11 cls_cnt 2 2006.173.05:21:25.94#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.05:21:26.00#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.05:21:26.00#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.05:21:26.00#ibcon#enter wrdev, iclass 33, count 2 2006.173.05:21:26.00#ibcon#first serial, iclass 33, count 2 2006.173.05:21:26.00#ibcon#enter sib2, iclass 33, count 2 2006.173.05:21:26.00#ibcon#flushed, iclass 33, count 2 2006.173.05:21:26.00#ibcon#about to write, iclass 33, count 2 2006.173.05:21:26.00#ibcon#wrote, iclass 33, count 2 2006.173.05:21:26.00#ibcon#about to read 3, iclass 33, count 2 2006.173.05:21:26.02#ibcon#read 3, iclass 33, count 2 2006.173.05:21:26.02#ibcon#about to read 4, iclass 33, count 2 2006.173.05:21:26.02#ibcon#read 4, iclass 33, count 2 2006.173.05:21:26.02#ibcon#about to read 5, iclass 33, count 2 2006.173.05:21:26.02#ibcon#read 5, iclass 33, count 2 2006.173.05:21:26.02#ibcon#about to read 6, iclass 33, count 2 2006.173.05:21:26.02#ibcon#read 6, iclass 33, count 2 2006.173.05:21:26.02#ibcon#end of sib2, iclass 33, count 2 2006.173.05:21:26.02#ibcon#*mode == 0, iclass 33, count 2 2006.173.05:21:26.02#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.173.05:21:26.02#ibcon#[27=AT04-04\r\n] 2006.173.05:21:26.02#ibcon#*before write, iclass 33, count 2 2006.173.05:21:26.02#ibcon#enter sib2, iclass 33, count 2 2006.173.05:21:26.02#ibcon#flushed, iclass 33, count 2 2006.173.05:21:26.02#ibcon#about to write, iclass 33, count 2 2006.173.05:21:26.02#ibcon#wrote, iclass 33, count 2 2006.173.05:21:26.02#ibcon#about to read 3, iclass 33, count 2 2006.173.05:21:26.05#ibcon#read 3, iclass 33, count 2 2006.173.05:21:26.05#ibcon#about to read 4, iclass 33, count 2 2006.173.05:21:26.05#ibcon#read 4, iclass 33, count 2 2006.173.05:21:26.05#ibcon#about to read 5, iclass 33, count 2 2006.173.05:21:26.05#ibcon#read 5, iclass 33, count 2 2006.173.05:21:26.05#ibcon#about to read 6, iclass 33, count 2 2006.173.05:21:26.05#ibcon#read 6, iclass 33, count 2 2006.173.05:21:26.05#ibcon#end of sib2, iclass 33, count 2 2006.173.05:21:26.05#ibcon#*after write, iclass 33, count 2 2006.173.05:21:26.05#ibcon#*before return 0, iclass 33, count 2 2006.173.05:21:26.05#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.05:21:26.05#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.173.05:21:26.05#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.173.05:21:26.05#ibcon#ireg 7 cls_cnt 0 2006.173.05:21:26.05#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.05:21:26.17#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.05:21:26.17#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.05:21:26.17#ibcon#enter wrdev, iclass 33, count 0 2006.173.05:21:26.17#ibcon#first serial, iclass 33, count 0 2006.173.05:21:26.17#ibcon#enter sib2, iclass 33, count 0 2006.173.05:21:26.17#ibcon#flushed, iclass 33, count 0 2006.173.05:21:26.17#ibcon#about to write, iclass 33, count 0 2006.173.05:21:26.17#ibcon#wrote, iclass 33, count 0 2006.173.05:21:26.17#ibcon#about to read 3, iclass 33, count 0 2006.173.05:21:26.19#ibcon#read 3, iclass 33, count 0 2006.173.05:21:26.19#ibcon#about to read 4, iclass 33, count 0 2006.173.05:21:26.19#ibcon#read 4, iclass 33, count 0 2006.173.05:21:26.19#ibcon#about to read 5, iclass 33, count 0 2006.173.05:21:26.19#ibcon#read 5, iclass 33, count 0 2006.173.05:21:26.19#ibcon#about to read 6, iclass 33, count 0 2006.173.05:21:26.19#ibcon#read 6, iclass 33, count 0 2006.173.05:21:26.19#ibcon#end of sib2, iclass 33, count 0 2006.173.05:21:26.19#ibcon#*mode == 0, iclass 33, count 0 2006.173.05:21:26.19#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.05:21:26.19#ibcon#[27=USB\r\n] 2006.173.05:21:26.19#ibcon#*before write, iclass 33, count 0 2006.173.05:21:26.19#ibcon#enter sib2, iclass 33, count 0 2006.173.05:21:26.19#ibcon#flushed, iclass 33, count 0 2006.173.05:21:26.19#ibcon#about to write, iclass 33, count 0 2006.173.05:21:26.19#ibcon#wrote, iclass 33, count 0 2006.173.05:21:26.19#ibcon#about to read 3, iclass 33, count 0 2006.173.05:21:26.22#ibcon#read 3, iclass 33, count 0 2006.173.05:21:26.22#ibcon#about to read 4, iclass 33, count 0 2006.173.05:21:26.22#ibcon#read 4, iclass 33, count 0 2006.173.05:21:26.22#ibcon#about to read 5, iclass 33, count 0 2006.173.05:21:26.22#ibcon#read 5, iclass 33, count 0 2006.173.05:21:26.22#ibcon#about to read 6, iclass 33, count 0 2006.173.05:21:26.22#ibcon#read 6, iclass 33, count 0 2006.173.05:21:26.22#ibcon#end of sib2, iclass 33, count 0 2006.173.05:21:26.22#ibcon#*after write, iclass 33, count 0 2006.173.05:21:26.22#ibcon#*before return 0, iclass 33, count 0 2006.173.05:21:26.22#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.05:21:26.22#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.173.05:21:26.22#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.05:21:26.22#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.05:21:26.22$vck44/vblo=5,709.99 2006.173.05:21:26.22#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.05:21:26.22#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.05:21:26.22#ibcon#ireg 17 cls_cnt 0 2006.173.05:21:26.22#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.05:21:26.22#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.05:21:26.22#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.05:21:26.22#ibcon#enter wrdev, iclass 35, count 0 2006.173.05:21:26.22#ibcon#first serial, iclass 35, count 0 2006.173.05:21:26.22#ibcon#enter sib2, iclass 35, count 0 2006.173.05:21:26.22#ibcon#flushed, iclass 35, count 0 2006.173.05:21:26.22#ibcon#about to write, iclass 35, count 0 2006.173.05:21:26.22#ibcon#wrote, iclass 35, count 0 2006.173.05:21:26.22#ibcon#about to read 3, iclass 35, count 0 2006.173.05:21:26.24#ibcon#read 3, iclass 35, count 0 2006.173.05:21:26.24#ibcon#about to read 4, iclass 35, count 0 2006.173.05:21:26.24#ibcon#read 4, iclass 35, count 0 2006.173.05:21:26.24#ibcon#about to read 5, iclass 35, count 0 2006.173.05:21:26.24#ibcon#read 5, iclass 35, count 0 2006.173.05:21:26.24#ibcon#about to read 6, iclass 35, count 0 2006.173.05:21:26.24#ibcon#read 6, iclass 35, count 0 2006.173.05:21:26.24#ibcon#end of sib2, iclass 35, count 0 2006.173.05:21:26.24#ibcon#*mode == 0, iclass 35, count 0 2006.173.05:21:26.24#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.05:21:26.24#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.05:21:26.24#ibcon#*before write, iclass 35, count 0 2006.173.05:21:26.24#ibcon#enter sib2, iclass 35, count 0 2006.173.05:21:26.24#ibcon#flushed, iclass 35, count 0 2006.173.05:21:26.24#ibcon#about to write, iclass 35, count 0 2006.173.05:21:26.24#ibcon#wrote, iclass 35, count 0 2006.173.05:21:26.24#ibcon#about to read 3, iclass 35, count 0 2006.173.05:21:26.28#ibcon#read 3, iclass 35, count 0 2006.173.05:21:26.28#ibcon#about to read 4, iclass 35, count 0 2006.173.05:21:26.28#ibcon#read 4, iclass 35, count 0 2006.173.05:21:26.28#ibcon#about to read 5, iclass 35, count 0 2006.173.05:21:26.28#ibcon#read 5, iclass 35, count 0 2006.173.05:21:26.28#ibcon#about to read 6, iclass 35, count 0 2006.173.05:21:26.28#ibcon#read 6, iclass 35, count 0 2006.173.05:21:26.28#ibcon#end of sib2, iclass 35, count 0 2006.173.05:21:26.28#ibcon#*after write, iclass 35, count 0 2006.173.05:21:26.28#ibcon#*before return 0, iclass 35, count 0 2006.173.05:21:26.28#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.05:21:26.28#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.05:21:26.28#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.05:21:26.28#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.05:21:26.28$vck44/vb=5,4 2006.173.05:21:26.28#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.173.05:21:26.28#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.173.05:21:26.28#ibcon#ireg 11 cls_cnt 2 2006.173.05:21:26.28#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.05:21:26.34#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.05:21:26.34#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.05:21:26.34#ibcon#enter wrdev, iclass 37, count 2 2006.173.05:21:26.34#ibcon#first serial, iclass 37, count 2 2006.173.05:21:26.34#ibcon#enter sib2, iclass 37, count 2 2006.173.05:21:26.34#ibcon#flushed, iclass 37, count 2 2006.173.05:21:26.34#ibcon#about to write, iclass 37, count 2 2006.173.05:21:26.34#ibcon#wrote, iclass 37, count 2 2006.173.05:21:26.34#ibcon#about to read 3, iclass 37, count 2 2006.173.05:21:26.36#ibcon#read 3, iclass 37, count 2 2006.173.05:21:26.36#ibcon#about to read 4, iclass 37, count 2 2006.173.05:21:26.36#ibcon#read 4, iclass 37, count 2 2006.173.05:21:26.36#ibcon#about to read 5, iclass 37, count 2 2006.173.05:21:26.36#ibcon#read 5, iclass 37, count 2 2006.173.05:21:26.36#ibcon#about to read 6, iclass 37, count 2 2006.173.05:21:26.36#ibcon#read 6, iclass 37, count 2 2006.173.05:21:26.36#ibcon#end of sib2, iclass 37, count 2 2006.173.05:21:26.36#ibcon#*mode == 0, iclass 37, count 2 2006.173.05:21:26.36#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.173.05:21:26.36#ibcon#[27=AT05-04\r\n] 2006.173.05:21:26.36#ibcon#*before write, iclass 37, count 2 2006.173.05:21:26.36#ibcon#enter sib2, iclass 37, count 2 2006.173.05:21:26.36#ibcon#flushed, iclass 37, count 2 2006.173.05:21:26.36#ibcon#about to write, iclass 37, count 2 2006.173.05:21:26.36#ibcon#wrote, iclass 37, count 2 2006.173.05:21:26.36#ibcon#about to read 3, iclass 37, count 2 2006.173.05:21:26.39#ibcon#read 3, iclass 37, count 2 2006.173.05:21:26.39#ibcon#about to read 4, iclass 37, count 2 2006.173.05:21:26.39#ibcon#read 4, iclass 37, count 2 2006.173.05:21:26.39#ibcon#about to read 5, iclass 37, count 2 2006.173.05:21:26.39#ibcon#read 5, iclass 37, count 2 2006.173.05:21:26.39#ibcon#about to read 6, iclass 37, count 2 2006.173.05:21:26.39#ibcon#read 6, iclass 37, count 2 2006.173.05:21:26.39#ibcon#end of sib2, iclass 37, count 2 2006.173.05:21:26.39#ibcon#*after write, iclass 37, count 2 2006.173.05:21:26.39#ibcon#*before return 0, iclass 37, count 2 2006.173.05:21:26.39#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.05:21:26.39#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.173.05:21:26.39#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.173.05:21:26.39#ibcon#ireg 7 cls_cnt 0 2006.173.05:21:26.39#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.05:21:26.51#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.05:21:26.51#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.05:21:26.51#ibcon#enter wrdev, iclass 37, count 0 2006.173.05:21:26.51#ibcon#first serial, iclass 37, count 0 2006.173.05:21:26.51#ibcon#enter sib2, iclass 37, count 0 2006.173.05:21:26.51#ibcon#flushed, iclass 37, count 0 2006.173.05:21:26.51#ibcon#about to write, iclass 37, count 0 2006.173.05:21:26.51#ibcon#wrote, iclass 37, count 0 2006.173.05:21:26.51#ibcon#about to read 3, iclass 37, count 0 2006.173.05:21:26.53#ibcon#read 3, iclass 37, count 0 2006.173.05:21:26.53#ibcon#about to read 4, iclass 37, count 0 2006.173.05:21:26.53#ibcon#read 4, iclass 37, count 0 2006.173.05:21:26.53#ibcon#about to read 5, iclass 37, count 0 2006.173.05:21:26.53#ibcon#read 5, iclass 37, count 0 2006.173.05:21:26.53#ibcon#about to read 6, iclass 37, count 0 2006.173.05:21:26.53#ibcon#read 6, iclass 37, count 0 2006.173.05:21:26.53#ibcon#end of sib2, iclass 37, count 0 2006.173.05:21:26.53#ibcon#*mode == 0, iclass 37, count 0 2006.173.05:21:26.53#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.05:21:26.53#ibcon#[27=USB\r\n] 2006.173.05:21:26.53#ibcon#*before write, iclass 37, count 0 2006.173.05:21:26.53#ibcon#enter sib2, iclass 37, count 0 2006.173.05:21:26.53#ibcon#flushed, iclass 37, count 0 2006.173.05:21:26.53#ibcon#about to write, iclass 37, count 0 2006.173.05:21:26.53#ibcon#wrote, iclass 37, count 0 2006.173.05:21:26.53#ibcon#about to read 3, iclass 37, count 0 2006.173.05:21:26.56#ibcon#read 3, iclass 37, count 0 2006.173.05:21:26.56#ibcon#about to read 4, iclass 37, count 0 2006.173.05:21:26.56#ibcon#read 4, iclass 37, count 0 2006.173.05:21:26.56#ibcon#about to read 5, iclass 37, count 0 2006.173.05:21:26.56#ibcon#read 5, iclass 37, count 0 2006.173.05:21:26.56#ibcon#about to read 6, iclass 37, count 0 2006.173.05:21:26.56#ibcon#read 6, iclass 37, count 0 2006.173.05:21:26.56#ibcon#end of sib2, iclass 37, count 0 2006.173.05:21:26.56#ibcon#*after write, iclass 37, count 0 2006.173.05:21:26.56#ibcon#*before return 0, iclass 37, count 0 2006.173.05:21:26.56#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.05:21:26.56#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.173.05:21:26.56#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.05:21:26.56#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.05:21:26.56$vck44/vblo=6,719.99 2006.173.05:21:26.56#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.05:21:26.56#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.05:21:26.56#ibcon#ireg 17 cls_cnt 0 2006.173.05:21:26.56#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.05:21:26.56#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.05:21:26.56#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.05:21:26.56#ibcon#enter wrdev, iclass 39, count 0 2006.173.05:21:26.56#ibcon#first serial, iclass 39, count 0 2006.173.05:21:26.56#ibcon#enter sib2, iclass 39, count 0 2006.173.05:21:26.56#ibcon#flushed, iclass 39, count 0 2006.173.05:21:26.56#ibcon#about to write, iclass 39, count 0 2006.173.05:21:26.56#ibcon#wrote, iclass 39, count 0 2006.173.05:21:26.56#ibcon#about to read 3, iclass 39, count 0 2006.173.05:21:26.58#ibcon#read 3, iclass 39, count 0 2006.173.05:21:26.58#ibcon#about to read 4, iclass 39, count 0 2006.173.05:21:26.58#ibcon#read 4, iclass 39, count 0 2006.173.05:21:26.58#ibcon#about to read 5, iclass 39, count 0 2006.173.05:21:26.58#ibcon#read 5, iclass 39, count 0 2006.173.05:21:26.58#ibcon#about to read 6, iclass 39, count 0 2006.173.05:21:26.58#ibcon#read 6, iclass 39, count 0 2006.173.05:21:26.58#ibcon#end of sib2, iclass 39, count 0 2006.173.05:21:26.58#ibcon#*mode == 0, iclass 39, count 0 2006.173.05:21:26.58#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.05:21:26.58#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.05:21:26.58#ibcon#*before write, iclass 39, count 0 2006.173.05:21:26.58#ibcon#enter sib2, iclass 39, count 0 2006.173.05:21:26.58#ibcon#flushed, iclass 39, count 0 2006.173.05:21:26.58#ibcon#about to write, iclass 39, count 0 2006.173.05:21:26.58#ibcon#wrote, iclass 39, count 0 2006.173.05:21:26.58#ibcon#about to read 3, iclass 39, count 0 2006.173.05:21:26.62#ibcon#read 3, iclass 39, count 0 2006.173.05:21:26.62#ibcon#about to read 4, iclass 39, count 0 2006.173.05:21:26.62#ibcon#read 4, iclass 39, count 0 2006.173.05:21:26.62#ibcon#about to read 5, iclass 39, count 0 2006.173.05:21:26.62#ibcon#read 5, iclass 39, count 0 2006.173.05:21:26.62#ibcon#about to read 6, iclass 39, count 0 2006.173.05:21:26.62#ibcon#read 6, iclass 39, count 0 2006.173.05:21:26.62#ibcon#end of sib2, iclass 39, count 0 2006.173.05:21:26.62#ibcon#*after write, iclass 39, count 0 2006.173.05:21:26.62#ibcon#*before return 0, iclass 39, count 0 2006.173.05:21:26.62#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.05:21:26.62#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.05:21:26.62#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.05:21:26.62#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.05:21:26.62$vck44/vb=6,4 2006.173.05:21:26.62#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.05:21:26.62#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.05:21:26.62#ibcon#ireg 11 cls_cnt 2 2006.173.05:21:26.62#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.05:21:26.68#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.05:21:26.68#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.05:21:26.68#ibcon#enter wrdev, iclass 3, count 2 2006.173.05:21:26.68#ibcon#first serial, iclass 3, count 2 2006.173.05:21:26.68#ibcon#enter sib2, iclass 3, count 2 2006.173.05:21:26.68#ibcon#flushed, iclass 3, count 2 2006.173.05:21:26.68#ibcon#about to write, iclass 3, count 2 2006.173.05:21:26.68#ibcon#wrote, iclass 3, count 2 2006.173.05:21:26.68#ibcon#about to read 3, iclass 3, count 2 2006.173.05:21:26.70#ibcon#read 3, iclass 3, count 2 2006.173.05:21:26.70#ibcon#about to read 4, iclass 3, count 2 2006.173.05:21:26.70#ibcon#read 4, iclass 3, count 2 2006.173.05:21:26.70#ibcon#about to read 5, iclass 3, count 2 2006.173.05:21:26.70#ibcon#read 5, iclass 3, count 2 2006.173.05:21:26.70#ibcon#about to read 6, iclass 3, count 2 2006.173.05:21:26.70#ibcon#read 6, iclass 3, count 2 2006.173.05:21:26.70#ibcon#end of sib2, iclass 3, count 2 2006.173.05:21:26.70#ibcon#*mode == 0, iclass 3, count 2 2006.173.05:21:26.70#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.05:21:26.70#ibcon#[27=AT06-04\r\n] 2006.173.05:21:26.70#ibcon#*before write, iclass 3, count 2 2006.173.05:21:26.70#ibcon#enter sib2, iclass 3, count 2 2006.173.05:21:26.70#ibcon#flushed, iclass 3, count 2 2006.173.05:21:26.70#ibcon#about to write, iclass 3, count 2 2006.173.05:21:26.70#ibcon#wrote, iclass 3, count 2 2006.173.05:21:26.70#ibcon#about to read 3, iclass 3, count 2 2006.173.05:21:26.73#ibcon#read 3, iclass 3, count 2 2006.173.05:21:26.73#ibcon#about to read 4, iclass 3, count 2 2006.173.05:21:26.73#ibcon#read 4, iclass 3, count 2 2006.173.05:21:26.73#ibcon#about to read 5, iclass 3, count 2 2006.173.05:21:26.73#ibcon#read 5, iclass 3, count 2 2006.173.05:21:26.73#ibcon#about to read 6, iclass 3, count 2 2006.173.05:21:26.73#ibcon#read 6, iclass 3, count 2 2006.173.05:21:26.73#ibcon#end of sib2, iclass 3, count 2 2006.173.05:21:26.73#ibcon#*after write, iclass 3, count 2 2006.173.05:21:26.73#ibcon#*before return 0, iclass 3, count 2 2006.173.05:21:26.73#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.05:21:26.73#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.05:21:26.73#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.05:21:26.73#ibcon#ireg 7 cls_cnt 0 2006.173.05:21:26.73#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.05:21:26.85#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.05:21:26.85#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.05:21:26.85#ibcon#enter wrdev, iclass 3, count 0 2006.173.05:21:26.85#ibcon#first serial, iclass 3, count 0 2006.173.05:21:26.85#ibcon#enter sib2, iclass 3, count 0 2006.173.05:21:26.85#ibcon#flushed, iclass 3, count 0 2006.173.05:21:26.85#ibcon#about to write, iclass 3, count 0 2006.173.05:21:26.85#ibcon#wrote, iclass 3, count 0 2006.173.05:21:26.85#ibcon#about to read 3, iclass 3, count 0 2006.173.05:21:26.87#ibcon#read 3, iclass 3, count 0 2006.173.05:21:26.87#ibcon#about to read 4, iclass 3, count 0 2006.173.05:21:26.87#ibcon#read 4, iclass 3, count 0 2006.173.05:21:26.87#ibcon#about to read 5, iclass 3, count 0 2006.173.05:21:26.87#ibcon#read 5, iclass 3, count 0 2006.173.05:21:26.87#ibcon#about to read 6, iclass 3, count 0 2006.173.05:21:26.87#ibcon#read 6, iclass 3, count 0 2006.173.05:21:26.87#ibcon#end of sib2, iclass 3, count 0 2006.173.05:21:26.87#ibcon#*mode == 0, iclass 3, count 0 2006.173.05:21:26.87#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.05:21:26.87#ibcon#[27=USB\r\n] 2006.173.05:21:26.87#ibcon#*before write, iclass 3, count 0 2006.173.05:21:26.87#ibcon#enter sib2, iclass 3, count 0 2006.173.05:21:26.87#ibcon#flushed, iclass 3, count 0 2006.173.05:21:26.87#ibcon#about to write, iclass 3, count 0 2006.173.05:21:26.87#ibcon#wrote, iclass 3, count 0 2006.173.05:21:26.87#ibcon#about to read 3, iclass 3, count 0 2006.173.05:21:26.90#ibcon#read 3, iclass 3, count 0 2006.173.05:21:26.90#ibcon#about to read 4, iclass 3, count 0 2006.173.05:21:26.90#ibcon#read 4, iclass 3, count 0 2006.173.05:21:26.90#ibcon#about to read 5, iclass 3, count 0 2006.173.05:21:26.90#ibcon#read 5, iclass 3, count 0 2006.173.05:21:26.90#ibcon#about to read 6, iclass 3, count 0 2006.173.05:21:26.90#ibcon#read 6, iclass 3, count 0 2006.173.05:21:26.90#ibcon#end of sib2, iclass 3, count 0 2006.173.05:21:26.90#ibcon#*after write, iclass 3, count 0 2006.173.05:21:26.90#ibcon#*before return 0, iclass 3, count 0 2006.173.05:21:26.90#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.05:21:26.90#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.05:21:26.90#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.05:21:26.90#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.05:21:26.90$vck44/vblo=7,734.99 2006.173.05:21:26.90#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.05:21:26.90#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.05:21:26.90#ibcon#ireg 17 cls_cnt 0 2006.173.05:21:26.90#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.05:21:26.90#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.05:21:26.90#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.05:21:26.90#ibcon#enter wrdev, iclass 5, count 0 2006.173.05:21:26.90#ibcon#first serial, iclass 5, count 0 2006.173.05:21:26.90#ibcon#enter sib2, iclass 5, count 0 2006.173.05:21:26.90#ibcon#flushed, iclass 5, count 0 2006.173.05:21:26.90#ibcon#about to write, iclass 5, count 0 2006.173.05:21:26.90#ibcon#wrote, iclass 5, count 0 2006.173.05:21:26.90#ibcon#about to read 3, iclass 5, count 0 2006.173.05:21:26.92#ibcon#read 3, iclass 5, count 0 2006.173.05:21:26.92#ibcon#about to read 4, iclass 5, count 0 2006.173.05:21:26.92#ibcon#read 4, iclass 5, count 0 2006.173.05:21:26.92#ibcon#about to read 5, iclass 5, count 0 2006.173.05:21:26.92#ibcon#read 5, iclass 5, count 0 2006.173.05:21:26.92#ibcon#about to read 6, iclass 5, count 0 2006.173.05:21:26.92#ibcon#read 6, iclass 5, count 0 2006.173.05:21:26.92#ibcon#end of sib2, iclass 5, count 0 2006.173.05:21:26.92#ibcon#*mode == 0, iclass 5, count 0 2006.173.05:21:26.92#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.05:21:26.92#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.05:21:26.92#ibcon#*before write, iclass 5, count 0 2006.173.05:21:26.92#ibcon#enter sib2, iclass 5, count 0 2006.173.05:21:26.92#ibcon#flushed, iclass 5, count 0 2006.173.05:21:26.92#ibcon#about to write, iclass 5, count 0 2006.173.05:21:26.92#ibcon#wrote, iclass 5, count 0 2006.173.05:21:26.92#ibcon#about to read 3, iclass 5, count 0 2006.173.05:21:26.96#ibcon#read 3, iclass 5, count 0 2006.173.05:21:26.96#ibcon#about to read 4, iclass 5, count 0 2006.173.05:21:26.96#ibcon#read 4, iclass 5, count 0 2006.173.05:21:26.96#ibcon#about to read 5, iclass 5, count 0 2006.173.05:21:26.96#ibcon#read 5, iclass 5, count 0 2006.173.05:21:26.96#ibcon#about to read 6, iclass 5, count 0 2006.173.05:21:26.96#ibcon#read 6, iclass 5, count 0 2006.173.05:21:26.96#ibcon#end of sib2, iclass 5, count 0 2006.173.05:21:26.96#ibcon#*after write, iclass 5, count 0 2006.173.05:21:26.96#ibcon#*before return 0, iclass 5, count 0 2006.173.05:21:26.96#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.05:21:26.96#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.05:21:26.96#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.05:21:26.96#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.05:21:26.96$vck44/vb=7,4 2006.173.05:21:26.96#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.173.05:21:26.96#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.173.05:21:26.96#ibcon#ireg 11 cls_cnt 2 2006.173.05:21:26.96#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.05:21:27.02#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.05:21:27.02#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.05:21:27.02#ibcon#enter wrdev, iclass 7, count 2 2006.173.05:21:27.02#ibcon#first serial, iclass 7, count 2 2006.173.05:21:27.02#ibcon#enter sib2, iclass 7, count 2 2006.173.05:21:27.02#ibcon#flushed, iclass 7, count 2 2006.173.05:21:27.02#ibcon#about to write, iclass 7, count 2 2006.173.05:21:27.02#ibcon#wrote, iclass 7, count 2 2006.173.05:21:27.02#ibcon#about to read 3, iclass 7, count 2 2006.173.05:21:27.04#ibcon#read 3, iclass 7, count 2 2006.173.05:21:27.04#ibcon#about to read 4, iclass 7, count 2 2006.173.05:21:27.04#ibcon#read 4, iclass 7, count 2 2006.173.05:21:27.04#ibcon#about to read 5, iclass 7, count 2 2006.173.05:21:27.04#ibcon#read 5, iclass 7, count 2 2006.173.05:21:27.04#ibcon#about to read 6, iclass 7, count 2 2006.173.05:21:27.04#ibcon#read 6, iclass 7, count 2 2006.173.05:21:27.04#ibcon#end of sib2, iclass 7, count 2 2006.173.05:21:27.04#ibcon#*mode == 0, iclass 7, count 2 2006.173.05:21:27.04#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.173.05:21:27.04#ibcon#[27=AT07-04\r\n] 2006.173.05:21:27.04#ibcon#*before write, iclass 7, count 2 2006.173.05:21:27.04#ibcon#enter sib2, iclass 7, count 2 2006.173.05:21:27.04#ibcon#flushed, iclass 7, count 2 2006.173.05:21:27.04#ibcon#about to write, iclass 7, count 2 2006.173.05:21:27.04#ibcon#wrote, iclass 7, count 2 2006.173.05:21:27.04#ibcon#about to read 3, iclass 7, count 2 2006.173.05:21:27.07#ibcon#read 3, iclass 7, count 2 2006.173.05:21:27.07#ibcon#about to read 4, iclass 7, count 2 2006.173.05:21:27.07#ibcon#read 4, iclass 7, count 2 2006.173.05:21:27.07#ibcon#about to read 5, iclass 7, count 2 2006.173.05:21:27.07#ibcon#read 5, iclass 7, count 2 2006.173.05:21:27.07#ibcon#about to read 6, iclass 7, count 2 2006.173.05:21:27.07#ibcon#read 6, iclass 7, count 2 2006.173.05:21:27.07#ibcon#end of sib2, iclass 7, count 2 2006.173.05:21:27.07#ibcon#*after write, iclass 7, count 2 2006.173.05:21:27.07#ibcon#*before return 0, iclass 7, count 2 2006.173.05:21:27.07#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.05:21:27.07#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.173.05:21:27.07#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.173.05:21:27.07#ibcon#ireg 7 cls_cnt 0 2006.173.05:21:27.07#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.05:21:27.19#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.05:21:27.19#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.05:21:27.19#ibcon#enter wrdev, iclass 7, count 0 2006.173.05:21:27.19#ibcon#first serial, iclass 7, count 0 2006.173.05:21:27.19#ibcon#enter sib2, iclass 7, count 0 2006.173.05:21:27.19#ibcon#flushed, iclass 7, count 0 2006.173.05:21:27.19#ibcon#about to write, iclass 7, count 0 2006.173.05:21:27.19#ibcon#wrote, iclass 7, count 0 2006.173.05:21:27.19#ibcon#about to read 3, iclass 7, count 0 2006.173.05:21:27.21#ibcon#read 3, iclass 7, count 0 2006.173.05:21:27.21#ibcon#about to read 4, iclass 7, count 0 2006.173.05:21:27.21#ibcon#read 4, iclass 7, count 0 2006.173.05:21:27.21#ibcon#about to read 5, iclass 7, count 0 2006.173.05:21:27.21#ibcon#read 5, iclass 7, count 0 2006.173.05:21:27.21#ibcon#about to read 6, iclass 7, count 0 2006.173.05:21:27.21#ibcon#read 6, iclass 7, count 0 2006.173.05:21:27.21#ibcon#end of sib2, iclass 7, count 0 2006.173.05:21:27.21#ibcon#*mode == 0, iclass 7, count 0 2006.173.05:21:27.21#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.05:21:27.21#ibcon#[27=USB\r\n] 2006.173.05:21:27.21#ibcon#*before write, iclass 7, count 0 2006.173.05:21:27.21#ibcon#enter sib2, iclass 7, count 0 2006.173.05:21:27.21#ibcon#flushed, iclass 7, count 0 2006.173.05:21:27.21#ibcon#about to write, iclass 7, count 0 2006.173.05:21:27.21#ibcon#wrote, iclass 7, count 0 2006.173.05:21:27.21#ibcon#about to read 3, iclass 7, count 0 2006.173.05:21:27.24#ibcon#read 3, iclass 7, count 0 2006.173.05:21:27.24#ibcon#about to read 4, iclass 7, count 0 2006.173.05:21:27.24#ibcon#read 4, iclass 7, count 0 2006.173.05:21:27.24#ibcon#about to read 5, iclass 7, count 0 2006.173.05:21:27.24#ibcon#read 5, iclass 7, count 0 2006.173.05:21:27.24#ibcon#about to read 6, iclass 7, count 0 2006.173.05:21:27.24#ibcon#read 6, iclass 7, count 0 2006.173.05:21:27.24#ibcon#end of sib2, iclass 7, count 0 2006.173.05:21:27.24#ibcon#*after write, iclass 7, count 0 2006.173.05:21:27.24#ibcon#*before return 0, iclass 7, count 0 2006.173.05:21:27.24#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.05:21:27.24#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.173.05:21:27.24#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.05:21:27.24#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.05:21:27.24$vck44/vblo=8,744.99 2006.173.05:21:27.24#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.05:21:27.24#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.05:21:27.24#ibcon#ireg 17 cls_cnt 0 2006.173.05:21:27.24#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.05:21:27.24#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.05:21:27.24#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.05:21:27.24#ibcon#enter wrdev, iclass 11, count 0 2006.173.05:21:27.24#ibcon#first serial, iclass 11, count 0 2006.173.05:21:27.24#ibcon#enter sib2, iclass 11, count 0 2006.173.05:21:27.24#ibcon#flushed, iclass 11, count 0 2006.173.05:21:27.24#ibcon#about to write, iclass 11, count 0 2006.173.05:21:27.24#ibcon#wrote, iclass 11, count 0 2006.173.05:21:27.24#ibcon#about to read 3, iclass 11, count 0 2006.173.05:21:27.26#ibcon#read 3, iclass 11, count 0 2006.173.05:21:27.26#ibcon#about to read 4, iclass 11, count 0 2006.173.05:21:27.26#ibcon#read 4, iclass 11, count 0 2006.173.05:21:27.26#ibcon#about to read 5, iclass 11, count 0 2006.173.05:21:27.26#ibcon#read 5, iclass 11, count 0 2006.173.05:21:27.26#ibcon#about to read 6, iclass 11, count 0 2006.173.05:21:27.26#ibcon#read 6, iclass 11, count 0 2006.173.05:21:27.26#ibcon#end of sib2, iclass 11, count 0 2006.173.05:21:27.26#ibcon#*mode == 0, iclass 11, count 0 2006.173.05:21:27.26#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.05:21:27.26#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.05:21:27.26#ibcon#*before write, iclass 11, count 0 2006.173.05:21:27.26#ibcon#enter sib2, iclass 11, count 0 2006.173.05:21:27.26#ibcon#flushed, iclass 11, count 0 2006.173.05:21:27.26#ibcon#about to write, iclass 11, count 0 2006.173.05:21:27.26#ibcon#wrote, iclass 11, count 0 2006.173.05:21:27.26#ibcon#about to read 3, iclass 11, count 0 2006.173.05:21:27.30#ibcon#read 3, iclass 11, count 0 2006.173.05:21:27.30#ibcon#about to read 4, iclass 11, count 0 2006.173.05:21:27.30#ibcon#read 4, iclass 11, count 0 2006.173.05:21:27.30#ibcon#about to read 5, iclass 11, count 0 2006.173.05:21:27.30#ibcon#read 5, iclass 11, count 0 2006.173.05:21:27.30#ibcon#about to read 6, iclass 11, count 0 2006.173.05:21:27.30#ibcon#read 6, iclass 11, count 0 2006.173.05:21:27.30#ibcon#end of sib2, iclass 11, count 0 2006.173.05:21:27.30#ibcon#*after write, iclass 11, count 0 2006.173.05:21:27.30#ibcon#*before return 0, iclass 11, count 0 2006.173.05:21:27.30#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.05:21:27.30#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.05:21:27.30#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.05:21:27.30#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.05:21:27.30$vck44/vb=8,4 2006.173.05:21:27.30#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.173.05:21:27.30#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.173.05:21:27.30#ibcon#ireg 11 cls_cnt 2 2006.173.05:21:27.30#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.05:21:27.36#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.05:21:27.36#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.05:21:27.36#ibcon#enter wrdev, iclass 13, count 2 2006.173.05:21:27.36#ibcon#first serial, iclass 13, count 2 2006.173.05:21:27.36#ibcon#enter sib2, iclass 13, count 2 2006.173.05:21:27.36#ibcon#flushed, iclass 13, count 2 2006.173.05:21:27.36#ibcon#about to write, iclass 13, count 2 2006.173.05:21:27.36#ibcon#wrote, iclass 13, count 2 2006.173.05:21:27.36#ibcon#about to read 3, iclass 13, count 2 2006.173.05:21:27.38#ibcon#read 3, iclass 13, count 2 2006.173.05:21:27.38#ibcon#about to read 4, iclass 13, count 2 2006.173.05:21:27.38#ibcon#read 4, iclass 13, count 2 2006.173.05:21:27.38#ibcon#about to read 5, iclass 13, count 2 2006.173.05:21:27.38#ibcon#read 5, iclass 13, count 2 2006.173.05:21:27.38#ibcon#about to read 6, iclass 13, count 2 2006.173.05:21:27.38#ibcon#read 6, iclass 13, count 2 2006.173.05:21:27.38#ibcon#end of sib2, iclass 13, count 2 2006.173.05:21:27.38#ibcon#*mode == 0, iclass 13, count 2 2006.173.05:21:27.38#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.173.05:21:27.38#ibcon#[27=AT08-04\r\n] 2006.173.05:21:27.38#ibcon#*before write, iclass 13, count 2 2006.173.05:21:27.38#ibcon#enter sib2, iclass 13, count 2 2006.173.05:21:27.38#ibcon#flushed, iclass 13, count 2 2006.173.05:21:27.38#ibcon#about to write, iclass 13, count 2 2006.173.05:21:27.38#ibcon#wrote, iclass 13, count 2 2006.173.05:21:27.38#ibcon#about to read 3, iclass 13, count 2 2006.173.05:21:27.41#ibcon#read 3, iclass 13, count 2 2006.173.05:21:27.41#ibcon#about to read 4, iclass 13, count 2 2006.173.05:21:27.41#ibcon#read 4, iclass 13, count 2 2006.173.05:21:27.41#ibcon#about to read 5, iclass 13, count 2 2006.173.05:21:27.41#ibcon#read 5, iclass 13, count 2 2006.173.05:21:27.41#ibcon#about to read 6, iclass 13, count 2 2006.173.05:21:27.41#ibcon#read 6, iclass 13, count 2 2006.173.05:21:27.41#ibcon#end of sib2, iclass 13, count 2 2006.173.05:21:27.41#ibcon#*after write, iclass 13, count 2 2006.173.05:21:27.41#ibcon#*before return 0, iclass 13, count 2 2006.173.05:21:27.41#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.05:21:27.41#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.173.05:21:27.41#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.173.05:21:27.41#ibcon#ireg 7 cls_cnt 0 2006.173.05:21:27.41#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.05:21:27.53#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.05:21:27.53#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.05:21:27.53#ibcon#enter wrdev, iclass 13, count 0 2006.173.05:21:27.53#ibcon#first serial, iclass 13, count 0 2006.173.05:21:27.53#ibcon#enter sib2, iclass 13, count 0 2006.173.05:21:27.53#ibcon#flushed, iclass 13, count 0 2006.173.05:21:27.53#ibcon#about to write, iclass 13, count 0 2006.173.05:21:27.53#ibcon#wrote, iclass 13, count 0 2006.173.05:21:27.53#ibcon#about to read 3, iclass 13, count 0 2006.173.05:21:27.55#ibcon#read 3, iclass 13, count 0 2006.173.05:21:27.55#ibcon#about to read 4, iclass 13, count 0 2006.173.05:21:27.55#ibcon#read 4, iclass 13, count 0 2006.173.05:21:27.55#ibcon#about to read 5, iclass 13, count 0 2006.173.05:21:27.55#ibcon#read 5, iclass 13, count 0 2006.173.05:21:27.55#ibcon#about to read 6, iclass 13, count 0 2006.173.05:21:27.55#ibcon#read 6, iclass 13, count 0 2006.173.05:21:27.55#ibcon#end of sib2, iclass 13, count 0 2006.173.05:21:27.55#ibcon#*mode == 0, iclass 13, count 0 2006.173.05:21:27.55#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.05:21:27.55#ibcon#[27=USB\r\n] 2006.173.05:21:27.55#ibcon#*before write, iclass 13, count 0 2006.173.05:21:27.55#ibcon#enter sib2, iclass 13, count 0 2006.173.05:21:27.55#ibcon#flushed, iclass 13, count 0 2006.173.05:21:27.55#ibcon#about to write, iclass 13, count 0 2006.173.05:21:27.55#ibcon#wrote, iclass 13, count 0 2006.173.05:21:27.55#ibcon#about to read 3, iclass 13, count 0 2006.173.05:21:27.58#ibcon#read 3, iclass 13, count 0 2006.173.05:21:27.58#ibcon#about to read 4, iclass 13, count 0 2006.173.05:21:27.58#ibcon#read 4, iclass 13, count 0 2006.173.05:21:27.58#ibcon#about to read 5, iclass 13, count 0 2006.173.05:21:27.58#ibcon#read 5, iclass 13, count 0 2006.173.05:21:27.58#ibcon#about to read 6, iclass 13, count 0 2006.173.05:21:27.58#ibcon#read 6, iclass 13, count 0 2006.173.05:21:27.58#ibcon#end of sib2, iclass 13, count 0 2006.173.05:21:27.58#ibcon#*after write, iclass 13, count 0 2006.173.05:21:27.58#ibcon#*before return 0, iclass 13, count 0 2006.173.05:21:27.58#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.05:21:27.58#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.173.05:21:27.58#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.05:21:27.58#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.05:21:27.58$vck44/vabw=wide 2006.173.05:21:27.58#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.05:21:27.58#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.05:21:27.58#ibcon#ireg 8 cls_cnt 0 2006.173.05:21:27.58#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.05:21:27.58#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.05:21:27.58#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.05:21:27.58#ibcon#enter wrdev, iclass 15, count 0 2006.173.05:21:27.58#ibcon#first serial, iclass 15, count 0 2006.173.05:21:27.58#ibcon#enter sib2, iclass 15, count 0 2006.173.05:21:27.58#ibcon#flushed, iclass 15, count 0 2006.173.05:21:27.58#ibcon#about to write, iclass 15, count 0 2006.173.05:21:27.58#ibcon#wrote, iclass 15, count 0 2006.173.05:21:27.58#ibcon#about to read 3, iclass 15, count 0 2006.173.05:21:27.60#ibcon#read 3, iclass 15, count 0 2006.173.05:21:27.60#ibcon#about to read 4, iclass 15, count 0 2006.173.05:21:27.60#ibcon#read 4, iclass 15, count 0 2006.173.05:21:27.60#ibcon#about to read 5, iclass 15, count 0 2006.173.05:21:27.60#ibcon#read 5, iclass 15, count 0 2006.173.05:21:27.60#ibcon#about to read 6, iclass 15, count 0 2006.173.05:21:27.60#ibcon#read 6, iclass 15, count 0 2006.173.05:21:27.60#ibcon#end of sib2, iclass 15, count 0 2006.173.05:21:27.60#ibcon#*mode == 0, iclass 15, count 0 2006.173.05:21:27.60#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.05:21:27.60#ibcon#[25=BW32\r\n] 2006.173.05:21:27.60#ibcon#*before write, iclass 15, count 0 2006.173.05:21:27.60#ibcon#enter sib2, iclass 15, count 0 2006.173.05:21:27.60#ibcon#flushed, iclass 15, count 0 2006.173.05:21:27.60#ibcon#about to write, iclass 15, count 0 2006.173.05:21:27.60#ibcon#wrote, iclass 15, count 0 2006.173.05:21:27.60#ibcon#about to read 3, iclass 15, count 0 2006.173.05:21:27.63#ibcon#read 3, iclass 15, count 0 2006.173.05:21:27.63#ibcon#about to read 4, iclass 15, count 0 2006.173.05:21:27.63#ibcon#read 4, iclass 15, count 0 2006.173.05:21:27.63#ibcon#about to read 5, iclass 15, count 0 2006.173.05:21:27.63#ibcon#read 5, iclass 15, count 0 2006.173.05:21:27.63#ibcon#about to read 6, iclass 15, count 0 2006.173.05:21:27.63#ibcon#read 6, iclass 15, count 0 2006.173.05:21:27.63#ibcon#end of sib2, iclass 15, count 0 2006.173.05:21:27.63#ibcon#*after write, iclass 15, count 0 2006.173.05:21:27.63#ibcon#*before return 0, iclass 15, count 0 2006.173.05:21:27.63#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.05:21:27.63#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.05:21:27.63#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.05:21:27.63#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.05:21:27.63$vck44/vbbw=wide 2006.173.05:21:27.63#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.05:21:27.63#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.05:21:27.63#ibcon#ireg 8 cls_cnt 0 2006.173.05:21:27.63#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.05:21:27.70#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.05:21:27.70#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.05:21:27.70#ibcon#enter wrdev, iclass 17, count 0 2006.173.05:21:27.70#ibcon#first serial, iclass 17, count 0 2006.173.05:21:27.70#ibcon#enter sib2, iclass 17, count 0 2006.173.05:21:27.70#ibcon#flushed, iclass 17, count 0 2006.173.05:21:27.70#ibcon#about to write, iclass 17, count 0 2006.173.05:21:27.70#ibcon#wrote, iclass 17, count 0 2006.173.05:21:27.70#ibcon#about to read 3, iclass 17, count 0 2006.173.05:21:27.72#ibcon#read 3, iclass 17, count 0 2006.173.05:21:27.72#ibcon#about to read 4, iclass 17, count 0 2006.173.05:21:27.72#ibcon#read 4, iclass 17, count 0 2006.173.05:21:27.72#ibcon#about to read 5, iclass 17, count 0 2006.173.05:21:27.72#ibcon#read 5, iclass 17, count 0 2006.173.05:21:27.72#ibcon#about to read 6, iclass 17, count 0 2006.173.05:21:27.72#ibcon#read 6, iclass 17, count 0 2006.173.05:21:27.72#ibcon#end of sib2, iclass 17, count 0 2006.173.05:21:27.72#ibcon#*mode == 0, iclass 17, count 0 2006.173.05:21:27.72#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.05:21:27.72#ibcon#[27=BW32\r\n] 2006.173.05:21:27.72#ibcon#*before write, iclass 17, count 0 2006.173.05:21:27.72#ibcon#enter sib2, iclass 17, count 0 2006.173.05:21:27.72#ibcon#flushed, iclass 17, count 0 2006.173.05:21:27.72#ibcon#about to write, iclass 17, count 0 2006.173.05:21:27.72#ibcon#wrote, iclass 17, count 0 2006.173.05:21:27.72#ibcon#about to read 3, iclass 17, count 0 2006.173.05:21:27.75#ibcon#read 3, iclass 17, count 0 2006.173.05:21:27.75#ibcon#about to read 4, iclass 17, count 0 2006.173.05:21:27.75#ibcon#read 4, iclass 17, count 0 2006.173.05:21:27.75#ibcon#about to read 5, iclass 17, count 0 2006.173.05:21:27.75#ibcon#read 5, iclass 17, count 0 2006.173.05:21:27.75#ibcon#about to read 6, iclass 17, count 0 2006.173.05:21:27.75#ibcon#read 6, iclass 17, count 0 2006.173.05:21:27.75#ibcon#end of sib2, iclass 17, count 0 2006.173.05:21:27.75#ibcon#*after write, iclass 17, count 0 2006.173.05:21:27.75#ibcon#*before return 0, iclass 17, count 0 2006.173.05:21:27.75#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.05:21:27.75#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.05:21:27.75#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.05:21:27.75#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.05:21:27.75$setupk4/ifdk4 2006.173.05:21:27.75$ifdk4/lo= 2006.173.05:21:27.75$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.05:21:27.76$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.05:21:27.76$ifdk4/patch= 2006.173.05:21:27.76$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.05:21:27.76$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.05:21:27.76$setupk4/!*+20s 2006.173.05:21:35.31#abcon#<5=/14 0.9 2.3 23.51 801005.6\r\n> 2006.173.05:21:35.33#abcon#{5=INTERFACE CLEAR} 2006.173.05:21:35.39#abcon#[5=S1D000X0/0*\r\n] 2006.173.05:21:40.13#trakl#Source acquired 2006.173.05:21:42.13#flagr#flagr/antenna,acquired 2006.173.05:21:42.19$setupk4/"tpicd 2006.173.05:21:42.19$setupk4/echo=off 2006.173.05:21:42.19$setupk4/xlog=off 2006.173.05:21:42.19:!2006.173.05:24:18 2006.173.05:24:18.00:preob 2006.173.05:24:19.14/onsource/TRACKING 2006.173.05:24:19.14:!2006.173.05:24:28 2006.173.05:24:28.00:"tape 2006.173.05:24:28.00:"st=record 2006.173.05:24:28.00:data_valid=on 2006.173.05:24:28.00:midob 2006.173.05:24:28.14/onsource/TRACKING 2006.173.05:24:28.14/wx/23.53,1005.6,79 2006.173.05:24:28.20/cable/+6.5068E-03 2006.173.05:24:29.29/va/01,07,usb,yes,37,40 2006.173.05:24:29.29/va/02,06,usb,yes,37,38 2006.173.05:24:29.29/va/03,05,usb,yes,47,49 2006.173.05:24:29.29/va/04,06,usb,yes,38,40 2006.173.05:24:29.29/va/05,04,usb,yes,30,30 2006.173.05:24:29.29/va/06,03,usb,yes,42,42 2006.173.05:24:29.29/va/07,04,usb,yes,34,35 2006.173.05:24:29.29/va/08,04,usb,yes,29,35 2006.173.05:24:29.52/valo/01,524.99,yes,locked 2006.173.05:24:29.52/valo/02,534.99,yes,locked 2006.173.05:24:29.52/valo/03,564.99,yes,locked 2006.173.05:24:29.52/valo/04,624.99,yes,locked 2006.173.05:24:29.52/valo/05,734.99,yes,locked 2006.173.05:24:29.52/valo/06,814.99,yes,locked 2006.173.05:24:29.52/valo/07,864.99,yes,locked 2006.173.05:24:29.52/valo/08,884.99,yes,locked 2006.173.05:24:30.61/vb/01,04,usb,yes,30,28 2006.173.05:24:30.61/vb/02,04,usb,yes,33,33 2006.173.05:24:30.61/vb/03,04,usb,yes,30,33 2006.173.05:24:30.61/vb/04,04,usb,yes,34,33 2006.173.05:24:30.61/vb/05,04,usb,yes,27,29 2006.173.05:24:30.61/vb/06,04,usb,yes,31,27 2006.173.05:24:30.61/vb/07,04,usb,yes,31,31 2006.173.05:24:30.61/vb/08,04,usb,yes,29,32 2006.173.05:24:30.84/vblo/01,629.99,yes,locked 2006.173.05:24:30.84/vblo/02,634.99,yes,locked 2006.173.05:24:30.84/vblo/03,649.99,yes,locked 2006.173.05:24:30.84/vblo/04,679.99,yes,locked 2006.173.05:24:30.84/vblo/05,709.99,yes,locked 2006.173.05:24:30.84/vblo/06,719.99,yes,locked 2006.173.05:24:30.84/vblo/07,734.99,yes,locked 2006.173.05:24:30.84/vblo/08,744.99,yes,locked 2006.173.05:24:30.99/vabw/8 2006.173.05:24:31.14/vbbw/8 2006.173.05:24:31.23/xfe/off,on,14.7 2006.173.05:24:31.61/ifatt/23,28,28,28 2006.173.05:24:32.07/fmout-gps/S +3.98E-07 2006.173.05:24:32.12:!2006.173.05:28:48 2006.173.05:28:48.01:data_valid=off 2006.173.05:28:48.01:"et 2006.173.05:28:48.01:!+3s 2006.173.05:28:51.02:"tape 2006.173.05:28:51.02:postob 2006.173.05:28:51.15/cable/+6.5057E-03 2006.173.05:28:51.15/wx/23.51,1005.4,78 2006.173.05:28:51.21/fmout-gps/S +3.98E-07 2006.173.05:28:51.21:scan_name=173-0533,jd0606,480 2006.173.05:28:51.21:source=1418+546,141946.60,542314.8,2000.0,cw 2006.173.05:28:52.14:checkk5 2006.173.05:28:52.14#flagr#flagr/antenna,new-source 2006.173.05:28:52.56/chk_autoobs//k5ts1/ autoobs is running! 2006.173.05:28:52.97/chk_autoobs//k5ts2/ autoobs is running! 2006.173.05:28:53.37/chk_autoobs//k5ts3/ autoobs is running! 2006.173.05:28:53.77/chk_autoobs//k5ts4/ autoobs is running! 2006.173.05:28:54.15/chk_obsdata//k5ts1/T1730524??a.dat file size is correct (nominal:1040MB, actual:1036MB). 2006.173.05:28:54.56/chk_obsdata//k5ts2/T1730524??b.dat file size is correct (nominal:1040MB, actual:1036MB). 2006.173.05:28:54.95/chk_obsdata//k5ts3/T1730524??c.dat file size is correct (nominal:1040MB, actual:1036MB). 2006.173.05:28:55.35/chk_obsdata//k5ts4/T1730524??d.dat file size is correct (nominal:1040MB, actual:1036MB). 2006.173.05:28:56.07/k5log//k5ts1_log_newline 2006.173.05:28:56.78/k5log//k5ts2_log_newline 2006.173.05:28:57.50/k5log//k5ts3_log_newline 2006.173.05:28:58.21/k5log//k5ts4_log_newline 2006.173.05:28:58.24/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.05:28:58.24:setupk4=1 2006.173.05:28:58.24$setupk4/echo=on 2006.173.05:28:58.24$setupk4/pcalon 2006.173.05:28:58.24$pcalon/"no phase cal control is implemented here 2006.173.05:28:58.24$setupk4/"tpicd=stop 2006.173.05:28:58.24$setupk4/"rec=synch_on 2006.173.05:28:58.24$setupk4/"rec_mode=128 2006.173.05:28:58.24$setupk4/!* 2006.173.05:28:58.24$setupk4/recpk4 2006.173.05:28:58.24$recpk4/recpatch= 2006.173.05:28:58.24$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.05:28:58.24$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.05:28:58.24$setupk4/vck44 2006.173.05:28:58.24$vck44/valo=1,524.99 2006.173.05:28:58.24#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.05:28:58.24#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.05:28:58.24#ibcon#ireg 17 cls_cnt 0 2006.173.05:28:58.24#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.05:28:58.24#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.05:28:58.24#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.05:28:58.24#ibcon#enter wrdev, iclass 18, count 0 2006.173.05:28:58.24#ibcon#first serial, iclass 18, count 0 2006.173.05:28:58.24#ibcon#enter sib2, iclass 18, count 0 2006.173.05:28:58.24#ibcon#flushed, iclass 18, count 0 2006.173.05:28:58.24#ibcon#about to write, iclass 18, count 0 2006.173.05:28:58.24#ibcon#wrote, iclass 18, count 0 2006.173.05:28:58.24#ibcon#about to read 3, iclass 18, count 0 2006.173.05:28:58.26#ibcon#read 3, iclass 18, count 0 2006.173.05:28:58.26#ibcon#about to read 4, iclass 18, count 0 2006.173.05:28:58.26#ibcon#read 4, iclass 18, count 0 2006.173.05:28:58.26#ibcon#about to read 5, iclass 18, count 0 2006.173.05:28:58.26#ibcon#read 5, iclass 18, count 0 2006.173.05:28:58.26#ibcon#about to read 6, iclass 18, count 0 2006.173.05:28:58.26#ibcon#read 6, iclass 18, count 0 2006.173.05:28:58.26#ibcon#end of sib2, iclass 18, count 0 2006.173.05:28:58.26#ibcon#*mode == 0, iclass 18, count 0 2006.173.05:28:58.26#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.05:28:58.26#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.05:28:58.26#ibcon#*before write, iclass 18, count 0 2006.173.05:28:58.26#ibcon#enter sib2, iclass 18, count 0 2006.173.05:28:58.26#ibcon#flushed, iclass 18, count 0 2006.173.05:28:58.26#ibcon#about to write, iclass 18, count 0 2006.173.05:28:58.26#ibcon#wrote, iclass 18, count 0 2006.173.05:28:58.26#ibcon#about to read 3, iclass 18, count 0 2006.173.05:28:58.31#ibcon#read 3, iclass 18, count 0 2006.173.05:28:58.31#ibcon#about to read 4, iclass 18, count 0 2006.173.05:28:58.31#ibcon#read 4, iclass 18, count 0 2006.173.05:28:58.31#ibcon#about to read 5, iclass 18, count 0 2006.173.05:28:58.31#ibcon#read 5, iclass 18, count 0 2006.173.05:28:58.31#ibcon#about to read 6, iclass 18, count 0 2006.173.05:28:58.31#ibcon#read 6, iclass 18, count 0 2006.173.05:28:58.31#ibcon#end of sib2, iclass 18, count 0 2006.173.05:28:58.31#ibcon#*after write, iclass 18, count 0 2006.173.05:28:58.31#ibcon#*before return 0, iclass 18, count 0 2006.173.05:28:58.31#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.05:28:58.31#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.05:28:58.31#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.05:28:58.31#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.05:28:58.31$vck44/va=1,7 2006.173.05:28:58.31#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.05:28:58.31#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.05:28:58.31#ibcon#ireg 11 cls_cnt 2 2006.173.05:28:58.31#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.05:28:58.31#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.05:28:58.31#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.05:28:58.31#ibcon#enter wrdev, iclass 20, count 2 2006.173.05:28:58.31#ibcon#first serial, iclass 20, count 2 2006.173.05:28:58.31#ibcon#enter sib2, iclass 20, count 2 2006.173.05:28:58.31#ibcon#flushed, iclass 20, count 2 2006.173.05:28:58.31#ibcon#about to write, iclass 20, count 2 2006.173.05:28:58.31#ibcon#wrote, iclass 20, count 2 2006.173.05:28:58.31#ibcon#about to read 3, iclass 20, count 2 2006.173.05:28:58.33#ibcon#read 3, iclass 20, count 2 2006.173.05:28:58.33#ibcon#about to read 4, iclass 20, count 2 2006.173.05:28:58.33#ibcon#read 4, iclass 20, count 2 2006.173.05:28:58.33#ibcon#about to read 5, iclass 20, count 2 2006.173.05:28:58.33#ibcon#read 5, iclass 20, count 2 2006.173.05:28:58.33#ibcon#about to read 6, iclass 20, count 2 2006.173.05:28:58.33#ibcon#read 6, iclass 20, count 2 2006.173.05:28:58.33#ibcon#end of sib2, iclass 20, count 2 2006.173.05:28:58.33#ibcon#*mode == 0, iclass 20, count 2 2006.173.05:28:58.33#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.05:28:58.33#ibcon#[25=AT01-07\r\n] 2006.173.05:28:58.33#ibcon#*before write, iclass 20, count 2 2006.173.05:28:58.33#ibcon#enter sib2, iclass 20, count 2 2006.173.05:28:58.33#ibcon#flushed, iclass 20, count 2 2006.173.05:28:58.33#ibcon#about to write, iclass 20, count 2 2006.173.05:28:58.33#ibcon#wrote, iclass 20, count 2 2006.173.05:28:58.33#ibcon#about to read 3, iclass 20, count 2 2006.173.05:28:58.36#ibcon#read 3, iclass 20, count 2 2006.173.05:28:58.36#ibcon#about to read 4, iclass 20, count 2 2006.173.05:28:58.36#ibcon#read 4, iclass 20, count 2 2006.173.05:28:58.36#ibcon#about to read 5, iclass 20, count 2 2006.173.05:28:58.36#ibcon#read 5, iclass 20, count 2 2006.173.05:28:58.36#ibcon#about to read 6, iclass 20, count 2 2006.173.05:28:58.36#ibcon#read 6, iclass 20, count 2 2006.173.05:28:58.36#ibcon#end of sib2, iclass 20, count 2 2006.173.05:28:58.36#ibcon#*after write, iclass 20, count 2 2006.173.05:28:58.36#ibcon#*before return 0, iclass 20, count 2 2006.173.05:28:58.36#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.05:28:58.36#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.05:28:58.36#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.05:28:58.36#ibcon#ireg 7 cls_cnt 0 2006.173.05:28:58.36#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.05:28:58.48#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.05:28:58.48#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.05:28:58.48#ibcon#enter wrdev, iclass 20, count 0 2006.173.05:28:58.48#ibcon#first serial, iclass 20, count 0 2006.173.05:28:58.48#ibcon#enter sib2, iclass 20, count 0 2006.173.05:28:58.48#ibcon#flushed, iclass 20, count 0 2006.173.05:28:58.48#ibcon#about to write, iclass 20, count 0 2006.173.05:28:58.48#ibcon#wrote, iclass 20, count 0 2006.173.05:28:58.48#ibcon#about to read 3, iclass 20, count 0 2006.173.05:28:58.50#ibcon#read 3, iclass 20, count 0 2006.173.05:28:58.50#ibcon#about to read 4, iclass 20, count 0 2006.173.05:28:58.50#ibcon#read 4, iclass 20, count 0 2006.173.05:28:58.50#ibcon#about to read 5, iclass 20, count 0 2006.173.05:28:58.50#ibcon#read 5, iclass 20, count 0 2006.173.05:28:58.50#ibcon#about to read 6, iclass 20, count 0 2006.173.05:28:58.50#ibcon#read 6, iclass 20, count 0 2006.173.05:28:58.50#ibcon#end of sib2, iclass 20, count 0 2006.173.05:28:58.50#ibcon#*mode == 0, iclass 20, count 0 2006.173.05:28:58.50#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.05:28:58.50#ibcon#[25=USB\r\n] 2006.173.05:28:58.50#ibcon#*before write, iclass 20, count 0 2006.173.05:28:58.50#ibcon#enter sib2, iclass 20, count 0 2006.173.05:28:58.50#ibcon#flushed, iclass 20, count 0 2006.173.05:28:58.50#ibcon#about to write, iclass 20, count 0 2006.173.05:28:58.50#ibcon#wrote, iclass 20, count 0 2006.173.05:28:58.50#ibcon#about to read 3, iclass 20, count 0 2006.173.05:28:58.53#ibcon#read 3, iclass 20, count 0 2006.173.05:28:58.53#ibcon#about to read 4, iclass 20, count 0 2006.173.05:28:58.53#ibcon#read 4, iclass 20, count 0 2006.173.05:28:58.53#ibcon#about to read 5, iclass 20, count 0 2006.173.05:28:58.53#ibcon#read 5, iclass 20, count 0 2006.173.05:28:58.53#ibcon#about to read 6, iclass 20, count 0 2006.173.05:28:58.53#ibcon#read 6, iclass 20, count 0 2006.173.05:28:58.53#ibcon#end of sib2, iclass 20, count 0 2006.173.05:28:58.53#ibcon#*after write, iclass 20, count 0 2006.173.05:28:58.53#ibcon#*before return 0, iclass 20, count 0 2006.173.05:28:58.53#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.05:28:58.53#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.05:28:58.53#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.05:28:58.53#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.05:28:58.53$vck44/valo=2,534.99 2006.173.05:28:58.53#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.05:28:58.53#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.05:28:58.53#ibcon#ireg 17 cls_cnt 0 2006.173.05:28:58.53#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.05:28:58.53#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.05:28:58.53#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.05:28:58.53#ibcon#enter wrdev, iclass 22, count 0 2006.173.05:28:58.53#ibcon#first serial, iclass 22, count 0 2006.173.05:28:58.53#ibcon#enter sib2, iclass 22, count 0 2006.173.05:28:58.53#ibcon#flushed, iclass 22, count 0 2006.173.05:28:58.53#ibcon#about to write, iclass 22, count 0 2006.173.05:28:58.53#ibcon#wrote, iclass 22, count 0 2006.173.05:28:58.53#ibcon#about to read 3, iclass 22, count 0 2006.173.05:28:58.55#ibcon#read 3, iclass 22, count 0 2006.173.05:28:58.55#ibcon#about to read 4, iclass 22, count 0 2006.173.05:28:58.55#ibcon#read 4, iclass 22, count 0 2006.173.05:28:58.55#ibcon#about to read 5, iclass 22, count 0 2006.173.05:28:58.55#ibcon#read 5, iclass 22, count 0 2006.173.05:28:58.55#ibcon#about to read 6, iclass 22, count 0 2006.173.05:28:58.55#ibcon#read 6, iclass 22, count 0 2006.173.05:28:58.55#ibcon#end of sib2, iclass 22, count 0 2006.173.05:28:58.55#ibcon#*mode == 0, iclass 22, count 0 2006.173.05:28:58.55#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.05:28:58.55#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.05:28:58.55#ibcon#*before write, iclass 22, count 0 2006.173.05:28:58.55#ibcon#enter sib2, iclass 22, count 0 2006.173.05:28:58.55#ibcon#flushed, iclass 22, count 0 2006.173.05:28:58.55#ibcon#about to write, iclass 22, count 0 2006.173.05:28:58.55#ibcon#wrote, iclass 22, count 0 2006.173.05:28:58.55#ibcon#about to read 3, iclass 22, count 0 2006.173.05:28:58.59#ibcon#read 3, iclass 22, count 0 2006.173.05:28:58.59#ibcon#about to read 4, iclass 22, count 0 2006.173.05:28:58.59#ibcon#read 4, iclass 22, count 0 2006.173.05:28:58.59#ibcon#about to read 5, iclass 22, count 0 2006.173.05:28:58.59#ibcon#read 5, iclass 22, count 0 2006.173.05:28:58.59#ibcon#about to read 6, iclass 22, count 0 2006.173.05:28:58.59#ibcon#read 6, iclass 22, count 0 2006.173.05:28:58.59#ibcon#end of sib2, iclass 22, count 0 2006.173.05:28:58.59#ibcon#*after write, iclass 22, count 0 2006.173.05:28:58.59#ibcon#*before return 0, iclass 22, count 0 2006.173.05:28:58.59#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.05:28:58.59#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.05:28:58.59#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.05:28:58.59#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.05:28:58.59$vck44/va=2,6 2006.173.05:28:58.59#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.05:28:58.59#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.05:28:58.59#ibcon#ireg 11 cls_cnt 2 2006.173.05:28:58.59#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.05:28:58.65#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.05:28:58.65#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.05:28:58.65#ibcon#enter wrdev, iclass 24, count 2 2006.173.05:28:58.65#ibcon#first serial, iclass 24, count 2 2006.173.05:28:58.65#ibcon#enter sib2, iclass 24, count 2 2006.173.05:28:58.65#ibcon#flushed, iclass 24, count 2 2006.173.05:28:58.65#ibcon#about to write, iclass 24, count 2 2006.173.05:28:58.65#ibcon#wrote, iclass 24, count 2 2006.173.05:28:58.65#ibcon#about to read 3, iclass 24, count 2 2006.173.05:28:58.67#ibcon#read 3, iclass 24, count 2 2006.173.05:28:58.67#ibcon#about to read 4, iclass 24, count 2 2006.173.05:28:58.67#ibcon#read 4, iclass 24, count 2 2006.173.05:28:58.67#ibcon#about to read 5, iclass 24, count 2 2006.173.05:28:58.67#ibcon#read 5, iclass 24, count 2 2006.173.05:28:58.67#ibcon#about to read 6, iclass 24, count 2 2006.173.05:28:58.67#ibcon#read 6, iclass 24, count 2 2006.173.05:28:58.67#ibcon#end of sib2, iclass 24, count 2 2006.173.05:28:58.67#ibcon#*mode == 0, iclass 24, count 2 2006.173.05:28:58.67#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.05:28:58.67#ibcon#[25=AT02-06\r\n] 2006.173.05:28:58.67#ibcon#*before write, iclass 24, count 2 2006.173.05:28:58.67#ibcon#enter sib2, iclass 24, count 2 2006.173.05:28:58.67#ibcon#flushed, iclass 24, count 2 2006.173.05:28:58.67#ibcon#about to write, iclass 24, count 2 2006.173.05:28:58.67#ibcon#wrote, iclass 24, count 2 2006.173.05:28:58.67#ibcon#about to read 3, iclass 24, count 2 2006.173.05:28:58.70#ibcon#read 3, iclass 24, count 2 2006.173.05:28:58.70#ibcon#about to read 4, iclass 24, count 2 2006.173.05:28:58.70#ibcon#read 4, iclass 24, count 2 2006.173.05:28:58.70#ibcon#about to read 5, iclass 24, count 2 2006.173.05:28:58.70#ibcon#read 5, iclass 24, count 2 2006.173.05:28:58.70#ibcon#about to read 6, iclass 24, count 2 2006.173.05:28:58.70#ibcon#read 6, iclass 24, count 2 2006.173.05:28:58.70#ibcon#end of sib2, iclass 24, count 2 2006.173.05:28:58.70#ibcon#*after write, iclass 24, count 2 2006.173.05:28:58.70#ibcon#*before return 0, iclass 24, count 2 2006.173.05:28:58.70#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.05:28:58.70#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.05:28:58.70#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.05:28:58.70#ibcon#ireg 7 cls_cnt 0 2006.173.05:28:58.70#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.05:28:58.82#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.05:28:58.82#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.05:28:58.82#ibcon#enter wrdev, iclass 24, count 0 2006.173.05:28:58.82#ibcon#first serial, iclass 24, count 0 2006.173.05:28:58.82#ibcon#enter sib2, iclass 24, count 0 2006.173.05:28:58.82#ibcon#flushed, iclass 24, count 0 2006.173.05:28:58.82#ibcon#about to write, iclass 24, count 0 2006.173.05:28:58.82#ibcon#wrote, iclass 24, count 0 2006.173.05:28:58.82#ibcon#about to read 3, iclass 24, count 0 2006.173.05:28:58.84#ibcon#read 3, iclass 24, count 0 2006.173.05:28:58.84#ibcon#about to read 4, iclass 24, count 0 2006.173.05:28:58.84#ibcon#read 4, iclass 24, count 0 2006.173.05:28:58.84#ibcon#about to read 5, iclass 24, count 0 2006.173.05:28:58.84#ibcon#read 5, iclass 24, count 0 2006.173.05:28:58.84#ibcon#about to read 6, iclass 24, count 0 2006.173.05:28:58.84#ibcon#read 6, iclass 24, count 0 2006.173.05:28:58.84#ibcon#end of sib2, iclass 24, count 0 2006.173.05:28:58.84#ibcon#*mode == 0, iclass 24, count 0 2006.173.05:28:58.84#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.05:28:58.84#ibcon#[25=USB\r\n] 2006.173.05:28:58.84#ibcon#*before write, iclass 24, count 0 2006.173.05:28:58.84#ibcon#enter sib2, iclass 24, count 0 2006.173.05:28:58.84#ibcon#flushed, iclass 24, count 0 2006.173.05:28:58.84#ibcon#about to write, iclass 24, count 0 2006.173.05:28:58.84#ibcon#wrote, iclass 24, count 0 2006.173.05:28:58.84#ibcon#about to read 3, iclass 24, count 0 2006.173.05:28:58.87#ibcon#read 3, iclass 24, count 0 2006.173.05:28:58.87#ibcon#about to read 4, iclass 24, count 0 2006.173.05:28:58.87#ibcon#read 4, iclass 24, count 0 2006.173.05:28:58.87#ibcon#about to read 5, iclass 24, count 0 2006.173.05:28:58.87#ibcon#read 5, iclass 24, count 0 2006.173.05:28:58.87#ibcon#about to read 6, iclass 24, count 0 2006.173.05:28:58.87#ibcon#read 6, iclass 24, count 0 2006.173.05:28:58.87#ibcon#end of sib2, iclass 24, count 0 2006.173.05:28:58.87#ibcon#*after write, iclass 24, count 0 2006.173.05:28:58.87#ibcon#*before return 0, iclass 24, count 0 2006.173.05:28:58.87#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.05:28:58.87#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.05:28:58.87#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.05:28:58.87#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.05:28:58.87$vck44/valo=3,564.99 2006.173.05:28:58.87#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.05:28:58.87#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.05:28:58.87#ibcon#ireg 17 cls_cnt 0 2006.173.05:28:58.87#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.05:28:58.87#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.05:28:58.87#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.05:28:58.87#ibcon#enter wrdev, iclass 26, count 0 2006.173.05:28:58.87#ibcon#first serial, iclass 26, count 0 2006.173.05:28:58.87#ibcon#enter sib2, iclass 26, count 0 2006.173.05:28:58.87#ibcon#flushed, iclass 26, count 0 2006.173.05:28:58.87#ibcon#about to write, iclass 26, count 0 2006.173.05:28:58.87#ibcon#wrote, iclass 26, count 0 2006.173.05:28:58.87#ibcon#about to read 3, iclass 26, count 0 2006.173.05:28:58.89#ibcon#read 3, iclass 26, count 0 2006.173.05:28:58.89#ibcon#about to read 4, iclass 26, count 0 2006.173.05:28:58.89#ibcon#read 4, iclass 26, count 0 2006.173.05:28:58.89#ibcon#about to read 5, iclass 26, count 0 2006.173.05:28:58.89#ibcon#read 5, iclass 26, count 0 2006.173.05:28:58.89#ibcon#about to read 6, iclass 26, count 0 2006.173.05:28:58.89#ibcon#read 6, iclass 26, count 0 2006.173.05:28:58.89#ibcon#end of sib2, iclass 26, count 0 2006.173.05:28:58.89#ibcon#*mode == 0, iclass 26, count 0 2006.173.05:28:58.89#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.05:28:58.89#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.05:28:58.89#ibcon#*before write, iclass 26, count 0 2006.173.05:28:58.89#ibcon#enter sib2, iclass 26, count 0 2006.173.05:28:58.89#ibcon#flushed, iclass 26, count 0 2006.173.05:28:58.89#ibcon#about to write, iclass 26, count 0 2006.173.05:28:58.89#ibcon#wrote, iclass 26, count 0 2006.173.05:28:58.89#ibcon#about to read 3, iclass 26, count 0 2006.173.05:28:58.93#ibcon#read 3, iclass 26, count 0 2006.173.05:28:58.93#ibcon#about to read 4, iclass 26, count 0 2006.173.05:28:58.93#ibcon#read 4, iclass 26, count 0 2006.173.05:28:58.93#ibcon#about to read 5, iclass 26, count 0 2006.173.05:28:58.93#ibcon#read 5, iclass 26, count 0 2006.173.05:28:58.93#ibcon#about to read 6, iclass 26, count 0 2006.173.05:28:58.93#ibcon#read 6, iclass 26, count 0 2006.173.05:28:58.93#ibcon#end of sib2, iclass 26, count 0 2006.173.05:28:58.93#ibcon#*after write, iclass 26, count 0 2006.173.05:28:58.93#ibcon#*before return 0, iclass 26, count 0 2006.173.05:28:58.93#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.05:28:58.93#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.05:28:58.93#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.05:28:58.93#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.05:28:58.93$vck44/va=3,5 2006.173.05:28:58.93#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.05:28:58.93#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.05:28:58.93#ibcon#ireg 11 cls_cnt 2 2006.173.05:28:58.93#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.05:28:58.99#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.05:28:58.99#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.05:28:58.99#ibcon#enter wrdev, iclass 28, count 2 2006.173.05:28:58.99#ibcon#first serial, iclass 28, count 2 2006.173.05:28:58.99#ibcon#enter sib2, iclass 28, count 2 2006.173.05:28:58.99#ibcon#flushed, iclass 28, count 2 2006.173.05:28:58.99#ibcon#about to write, iclass 28, count 2 2006.173.05:28:58.99#ibcon#wrote, iclass 28, count 2 2006.173.05:28:58.99#ibcon#about to read 3, iclass 28, count 2 2006.173.05:28:59.01#ibcon#read 3, iclass 28, count 2 2006.173.05:28:59.01#ibcon#about to read 4, iclass 28, count 2 2006.173.05:28:59.01#ibcon#read 4, iclass 28, count 2 2006.173.05:28:59.01#ibcon#about to read 5, iclass 28, count 2 2006.173.05:28:59.01#ibcon#read 5, iclass 28, count 2 2006.173.05:28:59.01#ibcon#about to read 6, iclass 28, count 2 2006.173.05:28:59.01#ibcon#read 6, iclass 28, count 2 2006.173.05:28:59.01#ibcon#end of sib2, iclass 28, count 2 2006.173.05:28:59.01#ibcon#*mode == 0, iclass 28, count 2 2006.173.05:28:59.01#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.05:28:59.01#ibcon#[25=AT03-05\r\n] 2006.173.05:28:59.01#ibcon#*before write, iclass 28, count 2 2006.173.05:28:59.01#ibcon#enter sib2, iclass 28, count 2 2006.173.05:28:59.01#ibcon#flushed, iclass 28, count 2 2006.173.05:28:59.01#ibcon#about to write, iclass 28, count 2 2006.173.05:28:59.01#ibcon#wrote, iclass 28, count 2 2006.173.05:28:59.01#ibcon#about to read 3, iclass 28, count 2 2006.173.05:28:59.04#ibcon#read 3, iclass 28, count 2 2006.173.05:28:59.04#ibcon#about to read 4, iclass 28, count 2 2006.173.05:28:59.04#ibcon#read 4, iclass 28, count 2 2006.173.05:28:59.04#ibcon#about to read 5, iclass 28, count 2 2006.173.05:28:59.04#ibcon#read 5, iclass 28, count 2 2006.173.05:28:59.04#ibcon#about to read 6, iclass 28, count 2 2006.173.05:28:59.04#ibcon#read 6, iclass 28, count 2 2006.173.05:28:59.04#ibcon#end of sib2, iclass 28, count 2 2006.173.05:28:59.04#ibcon#*after write, iclass 28, count 2 2006.173.05:28:59.04#ibcon#*before return 0, iclass 28, count 2 2006.173.05:28:59.04#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.05:28:59.04#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.05:28:59.04#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.05:28:59.04#ibcon#ireg 7 cls_cnt 0 2006.173.05:28:59.04#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.05:28:59.16#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.05:28:59.16#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.05:28:59.16#ibcon#enter wrdev, iclass 28, count 0 2006.173.05:28:59.16#ibcon#first serial, iclass 28, count 0 2006.173.05:28:59.16#ibcon#enter sib2, iclass 28, count 0 2006.173.05:28:59.16#ibcon#flushed, iclass 28, count 0 2006.173.05:28:59.16#ibcon#about to write, iclass 28, count 0 2006.173.05:28:59.16#ibcon#wrote, iclass 28, count 0 2006.173.05:28:59.16#ibcon#about to read 3, iclass 28, count 0 2006.173.05:28:59.18#ibcon#read 3, iclass 28, count 0 2006.173.05:28:59.18#ibcon#about to read 4, iclass 28, count 0 2006.173.05:28:59.18#ibcon#read 4, iclass 28, count 0 2006.173.05:28:59.18#ibcon#about to read 5, iclass 28, count 0 2006.173.05:28:59.18#ibcon#read 5, iclass 28, count 0 2006.173.05:28:59.18#ibcon#about to read 6, iclass 28, count 0 2006.173.05:28:59.18#ibcon#read 6, iclass 28, count 0 2006.173.05:28:59.18#ibcon#end of sib2, iclass 28, count 0 2006.173.05:28:59.18#ibcon#*mode == 0, iclass 28, count 0 2006.173.05:28:59.18#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.05:28:59.18#ibcon#[25=USB\r\n] 2006.173.05:28:59.18#ibcon#*before write, iclass 28, count 0 2006.173.05:28:59.18#ibcon#enter sib2, iclass 28, count 0 2006.173.05:28:59.18#ibcon#flushed, iclass 28, count 0 2006.173.05:28:59.18#ibcon#about to write, iclass 28, count 0 2006.173.05:28:59.18#ibcon#wrote, iclass 28, count 0 2006.173.05:28:59.18#ibcon#about to read 3, iclass 28, count 0 2006.173.05:28:59.21#ibcon#read 3, iclass 28, count 0 2006.173.05:28:59.21#ibcon#about to read 4, iclass 28, count 0 2006.173.05:28:59.21#ibcon#read 4, iclass 28, count 0 2006.173.05:28:59.21#ibcon#about to read 5, iclass 28, count 0 2006.173.05:28:59.21#ibcon#read 5, iclass 28, count 0 2006.173.05:28:59.21#ibcon#about to read 6, iclass 28, count 0 2006.173.05:28:59.21#ibcon#read 6, iclass 28, count 0 2006.173.05:28:59.21#ibcon#end of sib2, iclass 28, count 0 2006.173.05:28:59.21#ibcon#*after write, iclass 28, count 0 2006.173.05:28:59.21#ibcon#*before return 0, iclass 28, count 0 2006.173.05:28:59.21#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.05:28:59.21#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.05:28:59.21#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.05:28:59.21#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.05:28:59.21$vck44/valo=4,624.99 2006.173.05:28:59.21#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.05:28:59.21#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.05:28:59.21#ibcon#ireg 17 cls_cnt 0 2006.173.05:28:59.21#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.05:28:59.21#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.05:28:59.21#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.05:28:59.21#ibcon#enter wrdev, iclass 30, count 0 2006.173.05:28:59.21#ibcon#first serial, iclass 30, count 0 2006.173.05:28:59.21#ibcon#enter sib2, iclass 30, count 0 2006.173.05:28:59.21#ibcon#flushed, iclass 30, count 0 2006.173.05:28:59.21#ibcon#about to write, iclass 30, count 0 2006.173.05:28:59.21#ibcon#wrote, iclass 30, count 0 2006.173.05:28:59.21#ibcon#about to read 3, iclass 30, count 0 2006.173.05:28:59.23#ibcon#read 3, iclass 30, count 0 2006.173.05:28:59.23#ibcon#about to read 4, iclass 30, count 0 2006.173.05:28:59.23#ibcon#read 4, iclass 30, count 0 2006.173.05:28:59.23#ibcon#about to read 5, iclass 30, count 0 2006.173.05:28:59.23#ibcon#read 5, iclass 30, count 0 2006.173.05:28:59.23#ibcon#about to read 6, iclass 30, count 0 2006.173.05:28:59.23#ibcon#read 6, iclass 30, count 0 2006.173.05:28:59.23#ibcon#end of sib2, iclass 30, count 0 2006.173.05:28:59.23#ibcon#*mode == 0, iclass 30, count 0 2006.173.05:28:59.23#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.05:28:59.23#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.05:28:59.23#ibcon#*before write, iclass 30, count 0 2006.173.05:28:59.23#ibcon#enter sib2, iclass 30, count 0 2006.173.05:28:59.23#ibcon#flushed, iclass 30, count 0 2006.173.05:28:59.23#ibcon#about to write, iclass 30, count 0 2006.173.05:28:59.23#ibcon#wrote, iclass 30, count 0 2006.173.05:28:59.23#ibcon#about to read 3, iclass 30, count 0 2006.173.05:28:59.27#ibcon#read 3, iclass 30, count 0 2006.173.05:28:59.27#ibcon#about to read 4, iclass 30, count 0 2006.173.05:28:59.27#ibcon#read 4, iclass 30, count 0 2006.173.05:28:59.27#ibcon#about to read 5, iclass 30, count 0 2006.173.05:28:59.27#ibcon#read 5, iclass 30, count 0 2006.173.05:28:59.27#ibcon#about to read 6, iclass 30, count 0 2006.173.05:28:59.27#ibcon#read 6, iclass 30, count 0 2006.173.05:28:59.27#ibcon#end of sib2, iclass 30, count 0 2006.173.05:28:59.27#ibcon#*after write, iclass 30, count 0 2006.173.05:28:59.27#ibcon#*before return 0, iclass 30, count 0 2006.173.05:28:59.27#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.05:28:59.27#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.05:28:59.27#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.05:28:59.27#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.05:28:59.27$vck44/va=4,6 2006.173.05:28:59.27#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.173.05:28:59.27#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.173.05:28:59.27#ibcon#ireg 11 cls_cnt 2 2006.173.05:28:59.27#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.05:28:59.33#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.05:28:59.33#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.05:28:59.33#ibcon#enter wrdev, iclass 32, count 2 2006.173.05:28:59.33#ibcon#first serial, iclass 32, count 2 2006.173.05:28:59.33#ibcon#enter sib2, iclass 32, count 2 2006.173.05:28:59.33#ibcon#flushed, iclass 32, count 2 2006.173.05:28:59.33#ibcon#about to write, iclass 32, count 2 2006.173.05:28:59.33#ibcon#wrote, iclass 32, count 2 2006.173.05:28:59.33#ibcon#about to read 3, iclass 32, count 2 2006.173.05:28:59.35#ibcon#read 3, iclass 32, count 2 2006.173.05:28:59.35#ibcon#about to read 4, iclass 32, count 2 2006.173.05:28:59.35#ibcon#read 4, iclass 32, count 2 2006.173.05:28:59.35#ibcon#about to read 5, iclass 32, count 2 2006.173.05:28:59.35#ibcon#read 5, iclass 32, count 2 2006.173.05:28:59.35#ibcon#about to read 6, iclass 32, count 2 2006.173.05:28:59.35#ibcon#read 6, iclass 32, count 2 2006.173.05:28:59.35#ibcon#end of sib2, iclass 32, count 2 2006.173.05:28:59.35#ibcon#*mode == 0, iclass 32, count 2 2006.173.05:28:59.35#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.173.05:28:59.35#ibcon#[25=AT04-06\r\n] 2006.173.05:28:59.35#ibcon#*before write, iclass 32, count 2 2006.173.05:28:59.35#ibcon#enter sib2, iclass 32, count 2 2006.173.05:28:59.35#ibcon#flushed, iclass 32, count 2 2006.173.05:28:59.35#ibcon#about to write, iclass 32, count 2 2006.173.05:28:59.35#ibcon#wrote, iclass 32, count 2 2006.173.05:28:59.35#ibcon#about to read 3, iclass 32, count 2 2006.173.05:28:59.38#ibcon#read 3, iclass 32, count 2 2006.173.05:28:59.38#ibcon#about to read 4, iclass 32, count 2 2006.173.05:28:59.38#ibcon#read 4, iclass 32, count 2 2006.173.05:28:59.38#ibcon#about to read 5, iclass 32, count 2 2006.173.05:28:59.38#ibcon#read 5, iclass 32, count 2 2006.173.05:28:59.38#ibcon#about to read 6, iclass 32, count 2 2006.173.05:28:59.38#ibcon#read 6, iclass 32, count 2 2006.173.05:28:59.38#ibcon#end of sib2, iclass 32, count 2 2006.173.05:28:59.38#ibcon#*after write, iclass 32, count 2 2006.173.05:28:59.38#ibcon#*before return 0, iclass 32, count 2 2006.173.05:28:59.38#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.05:28:59.38#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.173.05:28:59.38#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.173.05:28:59.38#ibcon#ireg 7 cls_cnt 0 2006.173.05:28:59.38#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.05:28:59.50#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.05:28:59.50#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.05:28:59.50#ibcon#enter wrdev, iclass 32, count 0 2006.173.05:28:59.50#ibcon#first serial, iclass 32, count 0 2006.173.05:28:59.50#ibcon#enter sib2, iclass 32, count 0 2006.173.05:28:59.50#ibcon#flushed, iclass 32, count 0 2006.173.05:28:59.50#ibcon#about to write, iclass 32, count 0 2006.173.05:28:59.50#ibcon#wrote, iclass 32, count 0 2006.173.05:28:59.50#ibcon#about to read 3, iclass 32, count 0 2006.173.05:28:59.52#ibcon#read 3, iclass 32, count 0 2006.173.05:28:59.52#ibcon#about to read 4, iclass 32, count 0 2006.173.05:28:59.52#ibcon#read 4, iclass 32, count 0 2006.173.05:28:59.52#ibcon#about to read 5, iclass 32, count 0 2006.173.05:28:59.52#ibcon#read 5, iclass 32, count 0 2006.173.05:28:59.52#ibcon#about to read 6, iclass 32, count 0 2006.173.05:28:59.52#ibcon#read 6, iclass 32, count 0 2006.173.05:28:59.52#ibcon#end of sib2, iclass 32, count 0 2006.173.05:28:59.52#ibcon#*mode == 0, iclass 32, count 0 2006.173.05:28:59.52#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.05:28:59.52#ibcon#[25=USB\r\n] 2006.173.05:28:59.52#ibcon#*before write, iclass 32, count 0 2006.173.05:28:59.52#ibcon#enter sib2, iclass 32, count 0 2006.173.05:28:59.52#ibcon#flushed, iclass 32, count 0 2006.173.05:28:59.52#ibcon#about to write, iclass 32, count 0 2006.173.05:28:59.52#ibcon#wrote, iclass 32, count 0 2006.173.05:28:59.52#ibcon#about to read 3, iclass 32, count 0 2006.173.05:28:59.55#ibcon#read 3, iclass 32, count 0 2006.173.05:28:59.55#ibcon#about to read 4, iclass 32, count 0 2006.173.05:28:59.55#ibcon#read 4, iclass 32, count 0 2006.173.05:28:59.55#ibcon#about to read 5, iclass 32, count 0 2006.173.05:28:59.55#ibcon#read 5, iclass 32, count 0 2006.173.05:28:59.55#ibcon#about to read 6, iclass 32, count 0 2006.173.05:28:59.55#ibcon#read 6, iclass 32, count 0 2006.173.05:28:59.55#ibcon#end of sib2, iclass 32, count 0 2006.173.05:28:59.55#ibcon#*after write, iclass 32, count 0 2006.173.05:28:59.55#ibcon#*before return 0, iclass 32, count 0 2006.173.05:28:59.55#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.05:28:59.55#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.173.05:28:59.55#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.05:28:59.55#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.05:28:59.55$vck44/valo=5,734.99 2006.173.05:28:59.55#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.05:28:59.55#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.05:28:59.55#ibcon#ireg 17 cls_cnt 0 2006.173.05:28:59.55#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.05:28:59.55#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.05:28:59.55#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.05:28:59.55#ibcon#enter wrdev, iclass 34, count 0 2006.173.05:28:59.55#ibcon#first serial, iclass 34, count 0 2006.173.05:28:59.55#ibcon#enter sib2, iclass 34, count 0 2006.173.05:28:59.55#ibcon#flushed, iclass 34, count 0 2006.173.05:28:59.55#ibcon#about to write, iclass 34, count 0 2006.173.05:28:59.55#ibcon#wrote, iclass 34, count 0 2006.173.05:28:59.55#ibcon#about to read 3, iclass 34, count 0 2006.173.05:28:59.57#ibcon#read 3, iclass 34, count 0 2006.173.05:28:59.57#ibcon#about to read 4, iclass 34, count 0 2006.173.05:28:59.57#ibcon#read 4, iclass 34, count 0 2006.173.05:28:59.57#ibcon#about to read 5, iclass 34, count 0 2006.173.05:28:59.57#ibcon#read 5, iclass 34, count 0 2006.173.05:28:59.57#ibcon#about to read 6, iclass 34, count 0 2006.173.05:28:59.57#ibcon#read 6, iclass 34, count 0 2006.173.05:28:59.57#ibcon#end of sib2, iclass 34, count 0 2006.173.05:28:59.57#ibcon#*mode == 0, iclass 34, count 0 2006.173.05:28:59.57#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.05:28:59.57#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.05:28:59.57#ibcon#*before write, iclass 34, count 0 2006.173.05:28:59.57#ibcon#enter sib2, iclass 34, count 0 2006.173.05:28:59.57#ibcon#flushed, iclass 34, count 0 2006.173.05:28:59.57#ibcon#about to write, iclass 34, count 0 2006.173.05:28:59.57#ibcon#wrote, iclass 34, count 0 2006.173.05:28:59.57#ibcon#about to read 3, iclass 34, count 0 2006.173.05:28:59.61#ibcon#read 3, iclass 34, count 0 2006.173.05:28:59.61#ibcon#about to read 4, iclass 34, count 0 2006.173.05:28:59.61#ibcon#read 4, iclass 34, count 0 2006.173.05:28:59.61#ibcon#about to read 5, iclass 34, count 0 2006.173.05:28:59.61#ibcon#read 5, iclass 34, count 0 2006.173.05:28:59.61#ibcon#about to read 6, iclass 34, count 0 2006.173.05:28:59.61#ibcon#read 6, iclass 34, count 0 2006.173.05:28:59.61#ibcon#end of sib2, iclass 34, count 0 2006.173.05:28:59.61#ibcon#*after write, iclass 34, count 0 2006.173.05:28:59.61#ibcon#*before return 0, iclass 34, count 0 2006.173.05:28:59.61#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.05:28:59.61#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.05:28:59.61#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.05:28:59.61#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.05:28:59.61$vck44/va=5,4 2006.173.05:28:59.61#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.05:28:59.61#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.05:28:59.61#ibcon#ireg 11 cls_cnt 2 2006.173.05:28:59.61#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.05:28:59.67#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.05:28:59.67#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.05:28:59.67#ibcon#enter wrdev, iclass 36, count 2 2006.173.05:28:59.67#ibcon#first serial, iclass 36, count 2 2006.173.05:28:59.67#ibcon#enter sib2, iclass 36, count 2 2006.173.05:28:59.67#ibcon#flushed, iclass 36, count 2 2006.173.05:28:59.67#ibcon#about to write, iclass 36, count 2 2006.173.05:28:59.67#ibcon#wrote, iclass 36, count 2 2006.173.05:28:59.67#ibcon#about to read 3, iclass 36, count 2 2006.173.05:28:59.69#ibcon#read 3, iclass 36, count 2 2006.173.05:28:59.69#ibcon#about to read 4, iclass 36, count 2 2006.173.05:28:59.69#ibcon#read 4, iclass 36, count 2 2006.173.05:28:59.69#ibcon#about to read 5, iclass 36, count 2 2006.173.05:28:59.69#ibcon#read 5, iclass 36, count 2 2006.173.05:28:59.69#ibcon#about to read 6, iclass 36, count 2 2006.173.05:28:59.69#ibcon#read 6, iclass 36, count 2 2006.173.05:28:59.69#ibcon#end of sib2, iclass 36, count 2 2006.173.05:28:59.69#ibcon#*mode == 0, iclass 36, count 2 2006.173.05:28:59.69#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.05:28:59.69#ibcon#[25=AT05-04\r\n] 2006.173.05:28:59.69#ibcon#*before write, iclass 36, count 2 2006.173.05:28:59.69#ibcon#enter sib2, iclass 36, count 2 2006.173.05:28:59.69#ibcon#flushed, iclass 36, count 2 2006.173.05:28:59.69#ibcon#about to write, iclass 36, count 2 2006.173.05:28:59.69#ibcon#wrote, iclass 36, count 2 2006.173.05:28:59.69#ibcon#about to read 3, iclass 36, count 2 2006.173.05:28:59.72#ibcon#read 3, iclass 36, count 2 2006.173.05:28:59.72#ibcon#about to read 4, iclass 36, count 2 2006.173.05:28:59.72#ibcon#read 4, iclass 36, count 2 2006.173.05:28:59.72#ibcon#about to read 5, iclass 36, count 2 2006.173.05:28:59.72#ibcon#read 5, iclass 36, count 2 2006.173.05:28:59.72#ibcon#about to read 6, iclass 36, count 2 2006.173.05:28:59.72#ibcon#read 6, iclass 36, count 2 2006.173.05:28:59.72#ibcon#end of sib2, iclass 36, count 2 2006.173.05:28:59.72#ibcon#*after write, iclass 36, count 2 2006.173.05:28:59.72#ibcon#*before return 0, iclass 36, count 2 2006.173.05:28:59.72#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.05:28:59.72#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.05:28:59.72#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.05:28:59.72#ibcon#ireg 7 cls_cnt 0 2006.173.05:28:59.72#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.05:28:59.84#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.05:28:59.84#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.05:28:59.84#ibcon#enter wrdev, iclass 36, count 0 2006.173.05:28:59.84#ibcon#first serial, iclass 36, count 0 2006.173.05:28:59.84#ibcon#enter sib2, iclass 36, count 0 2006.173.05:28:59.84#ibcon#flushed, iclass 36, count 0 2006.173.05:28:59.84#ibcon#about to write, iclass 36, count 0 2006.173.05:28:59.84#ibcon#wrote, iclass 36, count 0 2006.173.05:28:59.84#ibcon#about to read 3, iclass 36, count 0 2006.173.05:28:59.86#ibcon#read 3, iclass 36, count 0 2006.173.05:28:59.86#ibcon#about to read 4, iclass 36, count 0 2006.173.05:28:59.86#ibcon#read 4, iclass 36, count 0 2006.173.05:28:59.86#ibcon#about to read 5, iclass 36, count 0 2006.173.05:28:59.86#ibcon#read 5, iclass 36, count 0 2006.173.05:28:59.86#ibcon#about to read 6, iclass 36, count 0 2006.173.05:28:59.86#ibcon#read 6, iclass 36, count 0 2006.173.05:28:59.86#ibcon#end of sib2, iclass 36, count 0 2006.173.05:28:59.86#ibcon#*mode == 0, iclass 36, count 0 2006.173.05:28:59.86#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.05:28:59.86#ibcon#[25=USB\r\n] 2006.173.05:28:59.86#ibcon#*before write, iclass 36, count 0 2006.173.05:28:59.86#ibcon#enter sib2, iclass 36, count 0 2006.173.05:28:59.86#ibcon#flushed, iclass 36, count 0 2006.173.05:28:59.86#ibcon#about to write, iclass 36, count 0 2006.173.05:28:59.86#ibcon#wrote, iclass 36, count 0 2006.173.05:28:59.86#ibcon#about to read 3, iclass 36, count 0 2006.173.05:28:59.89#ibcon#read 3, iclass 36, count 0 2006.173.05:28:59.89#ibcon#about to read 4, iclass 36, count 0 2006.173.05:28:59.89#ibcon#read 4, iclass 36, count 0 2006.173.05:28:59.89#ibcon#about to read 5, iclass 36, count 0 2006.173.05:28:59.89#ibcon#read 5, iclass 36, count 0 2006.173.05:28:59.89#ibcon#about to read 6, iclass 36, count 0 2006.173.05:28:59.89#ibcon#read 6, iclass 36, count 0 2006.173.05:28:59.89#ibcon#end of sib2, iclass 36, count 0 2006.173.05:28:59.89#ibcon#*after write, iclass 36, count 0 2006.173.05:28:59.89#ibcon#*before return 0, iclass 36, count 0 2006.173.05:28:59.89#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.05:28:59.89#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.05:28:59.89#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.05:28:59.89#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.05:28:59.89$vck44/valo=6,814.99 2006.173.05:28:59.89#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.05:28:59.89#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.05:28:59.89#ibcon#ireg 17 cls_cnt 0 2006.173.05:28:59.89#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.05:28:59.89#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.05:28:59.89#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.05:28:59.89#ibcon#enter wrdev, iclass 38, count 0 2006.173.05:28:59.89#ibcon#first serial, iclass 38, count 0 2006.173.05:28:59.89#ibcon#enter sib2, iclass 38, count 0 2006.173.05:28:59.89#ibcon#flushed, iclass 38, count 0 2006.173.05:28:59.89#ibcon#about to write, iclass 38, count 0 2006.173.05:28:59.89#ibcon#wrote, iclass 38, count 0 2006.173.05:28:59.89#ibcon#about to read 3, iclass 38, count 0 2006.173.05:28:59.91#ibcon#read 3, iclass 38, count 0 2006.173.05:28:59.91#ibcon#about to read 4, iclass 38, count 0 2006.173.05:28:59.91#ibcon#read 4, iclass 38, count 0 2006.173.05:28:59.91#ibcon#about to read 5, iclass 38, count 0 2006.173.05:28:59.91#ibcon#read 5, iclass 38, count 0 2006.173.05:28:59.91#ibcon#about to read 6, iclass 38, count 0 2006.173.05:28:59.91#ibcon#read 6, iclass 38, count 0 2006.173.05:28:59.91#ibcon#end of sib2, iclass 38, count 0 2006.173.05:28:59.91#ibcon#*mode == 0, iclass 38, count 0 2006.173.05:28:59.91#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.05:28:59.91#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.05:28:59.91#ibcon#*before write, iclass 38, count 0 2006.173.05:28:59.91#ibcon#enter sib2, iclass 38, count 0 2006.173.05:28:59.91#ibcon#flushed, iclass 38, count 0 2006.173.05:28:59.91#ibcon#about to write, iclass 38, count 0 2006.173.05:28:59.91#ibcon#wrote, iclass 38, count 0 2006.173.05:28:59.91#ibcon#about to read 3, iclass 38, count 0 2006.173.05:28:59.95#ibcon#read 3, iclass 38, count 0 2006.173.05:28:59.95#ibcon#about to read 4, iclass 38, count 0 2006.173.05:28:59.95#ibcon#read 4, iclass 38, count 0 2006.173.05:28:59.95#ibcon#about to read 5, iclass 38, count 0 2006.173.05:28:59.95#ibcon#read 5, iclass 38, count 0 2006.173.05:28:59.95#ibcon#about to read 6, iclass 38, count 0 2006.173.05:28:59.95#ibcon#read 6, iclass 38, count 0 2006.173.05:28:59.95#ibcon#end of sib2, iclass 38, count 0 2006.173.05:28:59.95#ibcon#*after write, iclass 38, count 0 2006.173.05:28:59.95#ibcon#*before return 0, iclass 38, count 0 2006.173.05:28:59.95#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.05:28:59.95#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.05:28:59.95#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.05:28:59.95#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.05:28:59.95$vck44/va=6,3 2006.173.05:28:59.95#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.05:28:59.95#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.05:28:59.95#ibcon#ireg 11 cls_cnt 2 2006.173.05:28:59.95#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.05:29:00.01#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.05:29:00.01#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.05:29:00.01#ibcon#enter wrdev, iclass 40, count 2 2006.173.05:29:00.01#ibcon#first serial, iclass 40, count 2 2006.173.05:29:00.01#ibcon#enter sib2, iclass 40, count 2 2006.173.05:29:00.01#ibcon#flushed, iclass 40, count 2 2006.173.05:29:00.01#ibcon#about to write, iclass 40, count 2 2006.173.05:29:00.01#ibcon#wrote, iclass 40, count 2 2006.173.05:29:00.01#ibcon#about to read 3, iclass 40, count 2 2006.173.05:29:00.03#ibcon#read 3, iclass 40, count 2 2006.173.05:29:00.03#ibcon#about to read 4, iclass 40, count 2 2006.173.05:29:00.03#ibcon#read 4, iclass 40, count 2 2006.173.05:29:00.03#ibcon#about to read 5, iclass 40, count 2 2006.173.05:29:00.03#ibcon#read 5, iclass 40, count 2 2006.173.05:29:00.03#ibcon#about to read 6, iclass 40, count 2 2006.173.05:29:00.03#ibcon#read 6, iclass 40, count 2 2006.173.05:29:00.03#ibcon#end of sib2, iclass 40, count 2 2006.173.05:29:00.03#ibcon#*mode == 0, iclass 40, count 2 2006.173.05:29:00.03#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.05:29:00.03#ibcon#[25=AT06-03\r\n] 2006.173.05:29:00.03#ibcon#*before write, iclass 40, count 2 2006.173.05:29:00.03#ibcon#enter sib2, iclass 40, count 2 2006.173.05:29:00.03#ibcon#flushed, iclass 40, count 2 2006.173.05:29:00.03#ibcon#about to write, iclass 40, count 2 2006.173.05:29:00.03#ibcon#wrote, iclass 40, count 2 2006.173.05:29:00.03#ibcon#about to read 3, iclass 40, count 2 2006.173.05:29:00.06#ibcon#read 3, iclass 40, count 2 2006.173.05:29:00.06#ibcon#about to read 4, iclass 40, count 2 2006.173.05:29:00.06#ibcon#read 4, iclass 40, count 2 2006.173.05:29:00.06#ibcon#about to read 5, iclass 40, count 2 2006.173.05:29:00.06#ibcon#read 5, iclass 40, count 2 2006.173.05:29:00.06#ibcon#about to read 6, iclass 40, count 2 2006.173.05:29:00.06#ibcon#read 6, iclass 40, count 2 2006.173.05:29:00.06#ibcon#end of sib2, iclass 40, count 2 2006.173.05:29:00.06#ibcon#*after write, iclass 40, count 2 2006.173.05:29:00.06#ibcon#*before return 0, iclass 40, count 2 2006.173.05:29:00.06#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.05:29:00.06#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.05:29:00.06#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.05:29:00.06#ibcon#ireg 7 cls_cnt 0 2006.173.05:29:00.06#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.05:29:00.18#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.05:29:00.18#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.05:29:00.18#ibcon#enter wrdev, iclass 40, count 0 2006.173.05:29:00.18#ibcon#first serial, iclass 40, count 0 2006.173.05:29:00.18#ibcon#enter sib2, iclass 40, count 0 2006.173.05:29:00.18#ibcon#flushed, iclass 40, count 0 2006.173.05:29:00.18#ibcon#about to write, iclass 40, count 0 2006.173.05:29:00.18#ibcon#wrote, iclass 40, count 0 2006.173.05:29:00.18#ibcon#about to read 3, iclass 40, count 0 2006.173.05:29:00.20#ibcon#read 3, iclass 40, count 0 2006.173.05:29:00.20#ibcon#about to read 4, iclass 40, count 0 2006.173.05:29:00.20#ibcon#read 4, iclass 40, count 0 2006.173.05:29:00.20#ibcon#about to read 5, iclass 40, count 0 2006.173.05:29:00.20#ibcon#read 5, iclass 40, count 0 2006.173.05:29:00.20#ibcon#about to read 6, iclass 40, count 0 2006.173.05:29:00.20#ibcon#read 6, iclass 40, count 0 2006.173.05:29:00.20#ibcon#end of sib2, iclass 40, count 0 2006.173.05:29:00.20#ibcon#*mode == 0, iclass 40, count 0 2006.173.05:29:00.20#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.05:29:00.20#ibcon#[25=USB\r\n] 2006.173.05:29:00.20#ibcon#*before write, iclass 40, count 0 2006.173.05:29:00.20#ibcon#enter sib2, iclass 40, count 0 2006.173.05:29:00.20#ibcon#flushed, iclass 40, count 0 2006.173.05:29:00.20#ibcon#about to write, iclass 40, count 0 2006.173.05:29:00.20#ibcon#wrote, iclass 40, count 0 2006.173.05:29:00.20#ibcon#about to read 3, iclass 40, count 0 2006.173.05:29:00.23#ibcon#read 3, iclass 40, count 0 2006.173.05:29:00.23#ibcon#about to read 4, iclass 40, count 0 2006.173.05:29:00.23#ibcon#read 4, iclass 40, count 0 2006.173.05:29:00.23#ibcon#about to read 5, iclass 40, count 0 2006.173.05:29:00.23#ibcon#read 5, iclass 40, count 0 2006.173.05:29:00.23#ibcon#about to read 6, iclass 40, count 0 2006.173.05:29:00.23#ibcon#read 6, iclass 40, count 0 2006.173.05:29:00.23#ibcon#end of sib2, iclass 40, count 0 2006.173.05:29:00.23#ibcon#*after write, iclass 40, count 0 2006.173.05:29:00.23#ibcon#*before return 0, iclass 40, count 0 2006.173.05:29:00.23#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.05:29:00.23#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.05:29:00.23#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.05:29:00.23#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.05:29:00.23$vck44/valo=7,864.99 2006.173.05:29:00.23#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.05:29:00.23#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.05:29:00.23#ibcon#ireg 17 cls_cnt 0 2006.173.05:29:00.23#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.05:29:00.23#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.05:29:00.23#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.05:29:00.23#ibcon#enter wrdev, iclass 4, count 0 2006.173.05:29:00.23#ibcon#first serial, iclass 4, count 0 2006.173.05:29:00.23#ibcon#enter sib2, iclass 4, count 0 2006.173.05:29:00.23#ibcon#flushed, iclass 4, count 0 2006.173.05:29:00.23#ibcon#about to write, iclass 4, count 0 2006.173.05:29:00.23#ibcon#wrote, iclass 4, count 0 2006.173.05:29:00.23#ibcon#about to read 3, iclass 4, count 0 2006.173.05:29:00.25#ibcon#read 3, iclass 4, count 0 2006.173.05:29:00.25#ibcon#about to read 4, iclass 4, count 0 2006.173.05:29:00.25#ibcon#read 4, iclass 4, count 0 2006.173.05:29:00.25#ibcon#about to read 5, iclass 4, count 0 2006.173.05:29:00.25#ibcon#read 5, iclass 4, count 0 2006.173.05:29:00.25#ibcon#about to read 6, iclass 4, count 0 2006.173.05:29:00.25#ibcon#read 6, iclass 4, count 0 2006.173.05:29:00.25#ibcon#end of sib2, iclass 4, count 0 2006.173.05:29:00.25#ibcon#*mode == 0, iclass 4, count 0 2006.173.05:29:00.25#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.05:29:00.25#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.05:29:00.25#ibcon#*before write, iclass 4, count 0 2006.173.05:29:00.25#ibcon#enter sib2, iclass 4, count 0 2006.173.05:29:00.25#ibcon#flushed, iclass 4, count 0 2006.173.05:29:00.25#ibcon#about to write, iclass 4, count 0 2006.173.05:29:00.25#ibcon#wrote, iclass 4, count 0 2006.173.05:29:00.25#ibcon#about to read 3, iclass 4, count 0 2006.173.05:29:00.29#ibcon#read 3, iclass 4, count 0 2006.173.05:29:00.29#ibcon#about to read 4, iclass 4, count 0 2006.173.05:29:00.29#ibcon#read 4, iclass 4, count 0 2006.173.05:29:00.29#ibcon#about to read 5, iclass 4, count 0 2006.173.05:29:00.29#ibcon#read 5, iclass 4, count 0 2006.173.05:29:00.29#ibcon#about to read 6, iclass 4, count 0 2006.173.05:29:00.29#ibcon#read 6, iclass 4, count 0 2006.173.05:29:00.29#ibcon#end of sib2, iclass 4, count 0 2006.173.05:29:00.29#ibcon#*after write, iclass 4, count 0 2006.173.05:29:00.29#ibcon#*before return 0, iclass 4, count 0 2006.173.05:29:00.29#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.05:29:00.29#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.05:29:00.29#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.05:29:00.29#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.05:29:00.29$vck44/va=7,4 2006.173.05:29:00.29#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.05:29:00.29#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.05:29:00.29#ibcon#ireg 11 cls_cnt 2 2006.173.05:29:00.29#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.05:29:00.35#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.05:29:00.35#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.05:29:00.35#ibcon#enter wrdev, iclass 6, count 2 2006.173.05:29:00.35#ibcon#first serial, iclass 6, count 2 2006.173.05:29:00.35#ibcon#enter sib2, iclass 6, count 2 2006.173.05:29:00.35#ibcon#flushed, iclass 6, count 2 2006.173.05:29:00.35#ibcon#about to write, iclass 6, count 2 2006.173.05:29:00.35#ibcon#wrote, iclass 6, count 2 2006.173.05:29:00.35#ibcon#about to read 3, iclass 6, count 2 2006.173.05:29:00.37#ibcon#read 3, iclass 6, count 2 2006.173.05:29:00.37#ibcon#about to read 4, iclass 6, count 2 2006.173.05:29:00.37#ibcon#read 4, iclass 6, count 2 2006.173.05:29:00.37#ibcon#about to read 5, iclass 6, count 2 2006.173.05:29:00.37#ibcon#read 5, iclass 6, count 2 2006.173.05:29:00.37#ibcon#about to read 6, iclass 6, count 2 2006.173.05:29:00.37#ibcon#read 6, iclass 6, count 2 2006.173.05:29:00.37#ibcon#end of sib2, iclass 6, count 2 2006.173.05:29:00.37#ibcon#*mode == 0, iclass 6, count 2 2006.173.05:29:00.37#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.05:29:00.37#ibcon#[25=AT07-04\r\n] 2006.173.05:29:00.37#ibcon#*before write, iclass 6, count 2 2006.173.05:29:00.37#ibcon#enter sib2, iclass 6, count 2 2006.173.05:29:00.37#ibcon#flushed, iclass 6, count 2 2006.173.05:29:00.37#ibcon#about to write, iclass 6, count 2 2006.173.05:29:00.37#ibcon#wrote, iclass 6, count 2 2006.173.05:29:00.37#ibcon#about to read 3, iclass 6, count 2 2006.173.05:29:00.40#ibcon#read 3, iclass 6, count 2 2006.173.05:29:00.40#ibcon#about to read 4, iclass 6, count 2 2006.173.05:29:00.40#ibcon#read 4, iclass 6, count 2 2006.173.05:29:00.40#ibcon#about to read 5, iclass 6, count 2 2006.173.05:29:00.40#ibcon#read 5, iclass 6, count 2 2006.173.05:29:00.40#ibcon#about to read 6, iclass 6, count 2 2006.173.05:29:00.40#ibcon#read 6, iclass 6, count 2 2006.173.05:29:00.40#ibcon#end of sib2, iclass 6, count 2 2006.173.05:29:00.40#ibcon#*after write, iclass 6, count 2 2006.173.05:29:00.40#ibcon#*before return 0, iclass 6, count 2 2006.173.05:29:00.40#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.05:29:00.40#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.05:29:00.40#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.05:29:00.40#ibcon#ireg 7 cls_cnt 0 2006.173.05:29:00.40#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.05:29:00.52#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.05:29:00.52#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.05:29:00.52#ibcon#enter wrdev, iclass 6, count 0 2006.173.05:29:00.52#ibcon#first serial, iclass 6, count 0 2006.173.05:29:00.52#ibcon#enter sib2, iclass 6, count 0 2006.173.05:29:00.52#ibcon#flushed, iclass 6, count 0 2006.173.05:29:00.52#ibcon#about to write, iclass 6, count 0 2006.173.05:29:00.52#ibcon#wrote, iclass 6, count 0 2006.173.05:29:00.52#ibcon#about to read 3, iclass 6, count 0 2006.173.05:29:00.54#ibcon#read 3, iclass 6, count 0 2006.173.05:29:00.54#ibcon#about to read 4, iclass 6, count 0 2006.173.05:29:00.54#ibcon#read 4, iclass 6, count 0 2006.173.05:29:00.54#ibcon#about to read 5, iclass 6, count 0 2006.173.05:29:00.54#ibcon#read 5, iclass 6, count 0 2006.173.05:29:00.54#ibcon#about to read 6, iclass 6, count 0 2006.173.05:29:00.54#ibcon#read 6, iclass 6, count 0 2006.173.05:29:00.54#ibcon#end of sib2, iclass 6, count 0 2006.173.05:29:00.54#ibcon#*mode == 0, iclass 6, count 0 2006.173.05:29:00.54#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.05:29:00.54#ibcon#[25=USB\r\n] 2006.173.05:29:00.54#ibcon#*before write, iclass 6, count 0 2006.173.05:29:00.54#ibcon#enter sib2, iclass 6, count 0 2006.173.05:29:00.54#ibcon#flushed, iclass 6, count 0 2006.173.05:29:00.54#ibcon#about to write, iclass 6, count 0 2006.173.05:29:00.54#ibcon#wrote, iclass 6, count 0 2006.173.05:29:00.54#ibcon#about to read 3, iclass 6, count 0 2006.173.05:29:00.57#ibcon#read 3, iclass 6, count 0 2006.173.05:29:00.57#ibcon#about to read 4, iclass 6, count 0 2006.173.05:29:00.57#ibcon#read 4, iclass 6, count 0 2006.173.05:29:00.57#ibcon#about to read 5, iclass 6, count 0 2006.173.05:29:00.57#ibcon#read 5, iclass 6, count 0 2006.173.05:29:00.57#ibcon#about to read 6, iclass 6, count 0 2006.173.05:29:00.57#ibcon#read 6, iclass 6, count 0 2006.173.05:29:00.57#ibcon#end of sib2, iclass 6, count 0 2006.173.05:29:00.57#ibcon#*after write, iclass 6, count 0 2006.173.05:29:00.57#ibcon#*before return 0, iclass 6, count 0 2006.173.05:29:00.57#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.05:29:00.57#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.05:29:00.57#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.05:29:00.57#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.05:29:00.57$vck44/valo=8,884.99 2006.173.05:29:00.57#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.05:29:00.57#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.05:29:00.57#ibcon#ireg 17 cls_cnt 0 2006.173.05:29:00.57#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.05:29:00.57#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.05:29:00.57#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.05:29:00.57#ibcon#enter wrdev, iclass 10, count 0 2006.173.05:29:00.57#ibcon#first serial, iclass 10, count 0 2006.173.05:29:00.57#ibcon#enter sib2, iclass 10, count 0 2006.173.05:29:00.57#ibcon#flushed, iclass 10, count 0 2006.173.05:29:00.57#ibcon#about to write, iclass 10, count 0 2006.173.05:29:00.57#ibcon#wrote, iclass 10, count 0 2006.173.05:29:00.57#ibcon#about to read 3, iclass 10, count 0 2006.173.05:29:00.59#ibcon#read 3, iclass 10, count 0 2006.173.05:29:00.59#ibcon#about to read 4, iclass 10, count 0 2006.173.05:29:00.59#ibcon#read 4, iclass 10, count 0 2006.173.05:29:00.59#ibcon#about to read 5, iclass 10, count 0 2006.173.05:29:00.59#ibcon#read 5, iclass 10, count 0 2006.173.05:29:00.59#ibcon#about to read 6, iclass 10, count 0 2006.173.05:29:00.59#ibcon#read 6, iclass 10, count 0 2006.173.05:29:00.59#ibcon#end of sib2, iclass 10, count 0 2006.173.05:29:00.59#ibcon#*mode == 0, iclass 10, count 0 2006.173.05:29:00.59#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.05:29:00.59#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.05:29:00.59#ibcon#*before write, iclass 10, count 0 2006.173.05:29:00.59#ibcon#enter sib2, iclass 10, count 0 2006.173.05:29:00.59#ibcon#flushed, iclass 10, count 0 2006.173.05:29:00.59#ibcon#about to write, iclass 10, count 0 2006.173.05:29:00.59#ibcon#wrote, iclass 10, count 0 2006.173.05:29:00.59#ibcon#about to read 3, iclass 10, count 0 2006.173.05:29:00.63#ibcon#read 3, iclass 10, count 0 2006.173.05:29:00.63#ibcon#about to read 4, iclass 10, count 0 2006.173.05:29:00.63#ibcon#read 4, iclass 10, count 0 2006.173.05:29:00.63#ibcon#about to read 5, iclass 10, count 0 2006.173.05:29:00.63#ibcon#read 5, iclass 10, count 0 2006.173.05:29:00.63#ibcon#about to read 6, iclass 10, count 0 2006.173.05:29:00.63#ibcon#read 6, iclass 10, count 0 2006.173.05:29:00.63#ibcon#end of sib2, iclass 10, count 0 2006.173.05:29:00.63#ibcon#*after write, iclass 10, count 0 2006.173.05:29:00.63#ibcon#*before return 0, iclass 10, count 0 2006.173.05:29:00.63#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.05:29:00.63#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.05:29:00.63#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.05:29:00.63#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.05:29:00.63$vck44/va=8,4 2006.173.05:29:00.63#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.05:29:00.63#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.05:29:00.63#ibcon#ireg 11 cls_cnt 2 2006.173.05:29:00.63#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.05:29:00.69#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.05:29:00.69#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.05:29:00.69#ibcon#enter wrdev, iclass 12, count 2 2006.173.05:29:00.69#ibcon#first serial, iclass 12, count 2 2006.173.05:29:00.69#ibcon#enter sib2, iclass 12, count 2 2006.173.05:29:00.69#ibcon#flushed, iclass 12, count 2 2006.173.05:29:00.69#ibcon#about to write, iclass 12, count 2 2006.173.05:29:00.69#ibcon#wrote, iclass 12, count 2 2006.173.05:29:00.69#ibcon#about to read 3, iclass 12, count 2 2006.173.05:29:00.71#ibcon#read 3, iclass 12, count 2 2006.173.05:29:00.71#ibcon#about to read 4, iclass 12, count 2 2006.173.05:29:00.71#ibcon#read 4, iclass 12, count 2 2006.173.05:29:00.71#ibcon#about to read 5, iclass 12, count 2 2006.173.05:29:00.71#ibcon#read 5, iclass 12, count 2 2006.173.05:29:00.71#ibcon#about to read 6, iclass 12, count 2 2006.173.05:29:00.71#ibcon#read 6, iclass 12, count 2 2006.173.05:29:00.71#ibcon#end of sib2, iclass 12, count 2 2006.173.05:29:00.71#ibcon#*mode == 0, iclass 12, count 2 2006.173.05:29:00.71#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.05:29:00.71#ibcon#[25=AT08-04\r\n] 2006.173.05:29:00.71#ibcon#*before write, iclass 12, count 2 2006.173.05:29:00.71#ibcon#enter sib2, iclass 12, count 2 2006.173.05:29:00.71#ibcon#flushed, iclass 12, count 2 2006.173.05:29:00.71#ibcon#about to write, iclass 12, count 2 2006.173.05:29:00.71#ibcon#wrote, iclass 12, count 2 2006.173.05:29:00.71#ibcon#about to read 3, iclass 12, count 2 2006.173.05:29:00.74#ibcon#read 3, iclass 12, count 2 2006.173.05:29:00.74#ibcon#about to read 4, iclass 12, count 2 2006.173.05:29:00.74#ibcon#read 4, iclass 12, count 2 2006.173.05:29:00.74#ibcon#about to read 5, iclass 12, count 2 2006.173.05:29:00.74#ibcon#read 5, iclass 12, count 2 2006.173.05:29:00.74#ibcon#about to read 6, iclass 12, count 2 2006.173.05:29:00.74#ibcon#read 6, iclass 12, count 2 2006.173.05:29:00.74#ibcon#end of sib2, iclass 12, count 2 2006.173.05:29:00.74#ibcon#*after write, iclass 12, count 2 2006.173.05:29:00.74#ibcon#*before return 0, iclass 12, count 2 2006.173.05:29:00.74#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.05:29:00.74#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.05:29:00.74#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.05:29:00.74#ibcon#ireg 7 cls_cnt 0 2006.173.05:29:00.74#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.05:29:00.86#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.05:29:00.86#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.05:29:00.86#ibcon#enter wrdev, iclass 12, count 0 2006.173.05:29:00.86#ibcon#first serial, iclass 12, count 0 2006.173.05:29:00.86#ibcon#enter sib2, iclass 12, count 0 2006.173.05:29:00.86#ibcon#flushed, iclass 12, count 0 2006.173.05:29:00.86#ibcon#about to write, iclass 12, count 0 2006.173.05:29:00.86#ibcon#wrote, iclass 12, count 0 2006.173.05:29:00.86#ibcon#about to read 3, iclass 12, count 0 2006.173.05:29:00.88#ibcon#read 3, iclass 12, count 0 2006.173.05:29:00.88#ibcon#about to read 4, iclass 12, count 0 2006.173.05:29:00.88#ibcon#read 4, iclass 12, count 0 2006.173.05:29:00.88#ibcon#about to read 5, iclass 12, count 0 2006.173.05:29:00.88#ibcon#read 5, iclass 12, count 0 2006.173.05:29:00.88#ibcon#about to read 6, iclass 12, count 0 2006.173.05:29:00.88#ibcon#read 6, iclass 12, count 0 2006.173.05:29:00.88#ibcon#end of sib2, iclass 12, count 0 2006.173.05:29:00.88#ibcon#*mode == 0, iclass 12, count 0 2006.173.05:29:00.88#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.05:29:00.88#ibcon#[25=USB\r\n] 2006.173.05:29:00.88#ibcon#*before write, iclass 12, count 0 2006.173.05:29:00.88#ibcon#enter sib2, iclass 12, count 0 2006.173.05:29:00.88#ibcon#flushed, iclass 12, count 0 2006.173.05:29:00.88#ibcon#about to write, iclass 12, count 0 2006.173.05:29:00.88#ibcon#wrote, iclass 12, count 0 2006.173.05:29:00.88#ibcon#about to read 3, iclass 12, count 0 2006.173.05:29:00.91#ibcon#read 3, iclass 12, count 0 2006.173.05:29:00.91#ibcon#about to read 4, iclass 12, count 0 2006.173.05:29:00.91#ibcon#read 4, iclass 12, count 0 2006.173.05:29:00.91#ibcon#about to read 5, iclass 12, count 0 2006.173.05:29:00.91#ibcon#read 5, iclass 12, count 0 2006.173.05:29:00.91#ibcon#about to read 6, iclass 12, count 0 2006.173.05:29:00.91#ibcon#read 6, iclass 12, count 0 2006.173.05:29:00.91#ibcon#end of sib2, iclass 12, count 0 2006.173.05:29:00.91#ibcon#*after write, iclass 12, count 0 2006.173.05:29:00.91#ibcon#*before return 0, iclass 12, count 0 2006.173.05:29:00.91#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.05:29:00.91#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.05:29:00.91#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.05:29:00.91#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.05:29:00.91$vck44/vblo=1,629.99 2006.173.05:29:00.91#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.05:29:00.91#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.05:29:00.91#ibcon#ireg 17 cls_cnt 0 2006.173.05:29:00.91#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.05:29:00.91#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.05:29:00.91#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.05:29:00.91#ibcon#enter wrdev, iclass 14, count 0 2006.173.05:29:00.91#ibcon#first serial, iclass 14, count 0 2006.173.05:29:00.91#ibcon#enter sib2, iclass 14, count 0 2006.173.05:29:00.91#ibcon#flushed, iclass 14, count 0 2006.173.05:29:00.91#ibcon#about to write, iclass 14, count 0 2006.173.05:29:00.91#ibcon#wrote, iclass 14, count 0 2006.173.05:29:00.91#ibcon#about to read 3, iclass 14, count 0 2006.173.05:29:00.93#ibcon#read 3, iclass 14, count 0 2006.173.05:29:00.93#ibcon#about to read 4, iclass 14, count 0 2006.173.05:29:00.93#ibcon#read 4, iclass 14, count 0 2006.173.05:29:00.93#ibcon#about to read 5, iclass 14, count 0 2006.173.05:29:00.93#ibcon#read 5, iclass 14, count 0 2006.173.05:29:00.93#ibcon#about to read 6, iclass 14, count 0 2006.173.05:29:00.93#ibcon#read 6, iclass 14, count 0 2006.173.05:29:00.93#ibcon#end of sib2, iclass 14, count 0 2006.173.05:29:00.93#ibcon#*mode == 0, iclass 14, count 0 2006.173.05:29:00.93#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.05:29:00.93#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.05:29:00.93#ibcon#*before write, iclass 14, count 0 2006.173.05:29:00.93#ibcon#enter sib2, iclass 14, count 0 2006.173.05:29:00.93#ibcon#flushed, iclass 14, count 0 2006.173.05:29:00.93#ibcon#about to write, iclass 14, count 0 2006.173.05:29:00.93#ibcon#wrote, iclass 14, count 0 2006.173.05:29:00.93#ibcon#about to read 3, iclass 14, count 0 2006.173.05:29:00.97#ibcon#read 3, iclass 14, count 0 2006.173.05:29:00.97#ibcon#about to read 4, iclass 14, count 0 2006.173.05:29:00.97#ibcon#read 4, iclass 14, count 0 2006.173.05:29:00.97#ibcon#about to read 5, iclass 14, count 0 2006.173.05:29:00.97#ibcon#read 5, iclass 14, count 0 2006.173.05:29:00.97#ibcon#about to read 6, iclass 14, count 0 2006.173.05:29:00.97#ibcon#read 6, iclass 14, count 0 2006.173.05:29:00.97#ibcon#end of sib2, iclass 14, count 0 2006.173.05:29:00.97#ibcon#*after write, iclass 14, count 0 2006.173.05:29:00.97#ibcon#*before return 0, iclass 14, count 0 2006.173.05:29:00.97#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.05:29:00.97#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.05:29:00.97#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.05:29:00.97#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.05:29:00.97$vck44/vb=1,4 2006.173.05:29:00.97#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.05:29:00.97#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.05:29:00.97#ibcon#ireg 11 cls_cnt 2 2006.173.05:29:00.97#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.05:29:00.97#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.05:29:00.97#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.05:29:00.97#ibcon#enter wrdev, iclass 16, count 2 2006.173.05:29:00.97#ibcon#first serial, iclass 16, count 2 2006.173.05:29:00.97#ibcon#enter sib2, iclass 16, count 2 2006.173.05:29:00.97#ibcon#flushed, iclass 16, count 2 2006.173.05:29:00.97#ibcon#about to write, iclass 16, count 2 2006.173.05:29:00.97#ibcon#wrote, iclass 16, count 2 2006.173.05:29:00.97#ibcon#about to read 3, iclass 16, count 2 2006.173.05:29:00.99#ibcon#read 3, iclass 16, count 2 2006.173.05:29:00.99#ibcon#about to read 4, iclass 16, count 2 2006.173.05:29:00.99#ibcon#read 4, iclass 16, count 2 2006.173.05:29:00.99#ibcon#about to read 5, iclass 16, count 2 2006.173.05:29:00.99#ibcon#read 5, iclass 16, count 2 2006.173.05:29:00.99#ibcon#about to read 6, iclass 16, count 2 2006.173.05:29:00.99#ibcon#read 6, iclass 16, count 2 2006.173.05:29:00.99#ibcon#end of sib2, iclass 16, count 2 2006.173.05:29:00.99#ibcon#*mode == 0, iclass 16, count 2 2006.173.05:29:00.99#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.05:29:00.99#ibcon#[27=AT01-04\r\n] 2006.173.05:29:00.99#ibcon#*before write, iclass 16, count 2 2006.173.05:29:00.99#ibcon#enter sib2, iclass 16, count 2 2006.173.05:29:00.99#ibcon#flushed, iclass 16, count 2 2006.173.05:29:00.99#ibcon#about to write, iclass 16, count 2 2006.173.05:29:00.99#ibcon#wrote, iclass 16, count 2 2006.173.05:29:00.99#ibcon#about to read 3, iclass 16, count 2 2006.173.05:29:01.02#ibcon#read 3, iclass 16, count 2 2006.173.05:29:01.02#ibcon#about to read 4, iclass 16, count 2 2006.173.05:29:01.02#ibcon#read 4, iclass 16, count 2 2006.173.05:29:01.02#ibcon#about to read 5, iclass 16, count 2 2006.173.05:29:01.02#ibcon#read 5, iclass 16, count 2 2006.173.05:29:01.02#ibcon#about to read 6, iclass 16, count 2 2006.173.05:29:01.02#ibcon#read 6, iclass 16, count 2 2006.173.05:29:01.02#ibcon#end of sib2, iclass 16, count 2 2006.173.05:29:01.02#ibcon#*after write, iclass 16, count 2 2006.173.05:29:01.02#ibcon#*before return 0, iclass 16, count 2 2006.173.05:29:01.02#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.05:29:01.02#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.05:29:01.02#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.05:29:01.02#ibcon#ireg 7 cls_cnt 0 2006.173.05:29:01.02#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.05:29:01.14#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.05:29:01.14#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.05:29:01.14#ibcon#enter wrdev, iclass 16, count 0 2006.173.05:29:01.14#ibcon#first serial, iclass 16, count 0 2006.173.05:29:01.14#ibcon#enter sib2, iclass 16, count 0 2006.173.05:29:01.14#ibcon#flushed, iclass 16, count 0 2006.173.05:29:01.14#ibcon#about to write, iclass 16, count 0 2006.173.05:29:01.14#ibcon#wrote, iclass 16, count 0 2006.173.05:29:01.14#ibcon#about to read 3, iclass 16, count 0 2006.173.05:29:01.16#ibcon#read 3, iclass 16, count 0 2006.173.05:29:01.16#ibcon#about to read 4, iclass 16, count 0 2006.173.05:29:01.16#ibcon#read 4, iclass 16, count 0 2006.173.05:29:01.16#ibcon#about to read 5, iclass 16, count 0 2006.173.05:29:01.16#ibcon#read 5, iclass 16, count 0 2006.173.05:29:01.16#ibcon#about to read 6, iclass 16, count 0 2006.173.05:29:01.16#ibcon#read 6, iclass 16, count 0 2006.173.05:29:01.16#ibcon#end of sib2, iclass 16, count 0 2006.173.05:29:01.16#ibcon#*mode == 0, iclass 16, count 0 2006.173.05:29:01.16#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.05:29:01.16#ibcon#[27=USB\r\n] 2006.173.05:29:01.16#ibcon#*before write, iclass 16, count 0 2006.173.05:29:01.16#ibcon#enter sib2, iclass 16, count 0 2006.173.05:29:01.16#ibcon#flushed, iclass 16, count 0 2006.173.05:29:01.16#ibcon#about to write, iclass 16, count 0 2006.173.05:29:01.16#ibcon#wrote, iclass 16, count 0 2006.173.05:29:01.16#ibcon#about to read 3, iclass 16, count 0 2006.173.05:29:01.19#ibcon#read 3, iclass 16, count 0 2006.173.05:29:01.19#ibcon#about to read 4, iclass 16, count 0 2006.173.05:29:01.19#ibcon#read 4, iclass 16, count 0 2006.173.05:29:01.19#ibcon#about to read 5, iclass 16, count 0 2006.173.05:29:01.19#ibcon#read 5, iclass 16, count 0 2006.173.05:29:01.19#ibcon#about to read 6, iclass 16, count 0 2006.173.05:29:01.19#ibcon#read 6, iclass 16, count 0 2006.173.05:29:01.19#ibcon#end of sib2, iclass 16, count 0 2006.173.05:29:01.19#ibcon#*after write, iclass 16, count 0 2006.173.05:29:01.19#ibcon#*before return 0, iclass 16, count 0 2006.173.05:29:01.19#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.05:29:01.19#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.05:29:01.19#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.05:29:01.19#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.05:29:01.19$vck44/vblo=2,634.99 2006.173.05:29:01.19#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.05:29:01.19#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.05:29:01.19#ibcon#ireg 17 cls_cnt 0 2006.173.05:29:01.19#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.05:29:01.19#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.05:29:01.19#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.05:29:01.19#ibcon#enter wrdev, iclass 18, count 0 2006.173.05:29:01.19#ibcon#first serial, iclass 18, count 0 2006.173.05:29:01.19#ibcon#enter sib2, iclass 18, count 0 2006.173.05:29:01.19#ibcon#flushed, iclass 18, count 0 2006.173.05:29:01.19#ibcon#about to write, iclass 18, count 0 2006.173.05:29:01.19#ibcon#wrote, iclass 18, count 0 2006.173.05:29:01.19#ibcon#about to read 3, iclass 18, count 0 2006.173.05:29:01.21#ibcon#read 3, iclass 18, count 0 2006.173.05:29:01.21#ibcon#about to read 4, iclass 18, count 0 2006.173.05:29:01.21#ibcon#read 4, iclass 18, count 0 2006.173.05:29:01.21#ibcon#about to read 5, iclass 18, count 0 2006.173.05:29:01.21#ibcon#read 5, iclass 18, count 0 2006.173.05:29:01.21#ibcon#about to read 6, iclass 18, count 0 2006.173.05:29:01.21#ibcon#read 6, iclass 18, count 0 2006.173.05:29:01.21#ibcon#end of sib2, iclass 18, count 0 2006.173.05:29:01.21#ibcon#*mode == 0, iclass 18, count 0 2006.173.05:29:01.21#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.05:29:01.21#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.05:29:01.21#ibcon#*before write, iclass 18, count 0 2006.173.05:29:01.21#ibcon#enter sib2, iclass 18, count 0 2006.173.05:29:01.21#ibcon#flushed, iclass 18, count 0 2006.173.05:29:01.21#ibcon#about to write, iclass 18, count 0 2006.173.05:29:01.21#ibcon#wrote, iclass 18, count 0 2006.173.05:29:01.21#ibcon#about to read 3, iclass 18, count 0 2006.173.05:29:01.25#ibcon#read 3, iclass 18, count 0 2006.173.05:29:01.25#ibcon#about to read 4, iclass 18, count 0 2006.173.05:29:01.25#ibcon#read 4, iclass 18, count 0 2006.173.05:29:01.25#ibcon#about to read 5, iclass 18, count 0 2006.173.05:29:01.25#ibcon#read 5, iclass 18, count 0 2006.173.05:29:01.25#ibcon#about to read 6, iclass 18, count 0 2006.173.05:29:01.25#ibcon#read 6, iclass 18, count 0 2006.173.05:29:01.25#ibcon#end of sib2, iclass 18, count 0 2006.173.05:29:01.25#ibcon#*after write, iclass 18, count 0 2006.173.05:29:01.25#ibcon#*before return 0, iclass 18, count 0 2006.173.05:29:01.25#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.05:29:01.25#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.05:29:01.25#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.05:29:01.25#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.05:29:01.25$vck44/vb=2,4 2006.173.05:29:01.25#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.05:29:01.25#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.05:29:01.25#ibcon#ireg 11 cls_cnt 2 2006.173.05:29:01.25#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.05:29:01.31#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.05:29:01.31#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.05:29:01.31#ibcon#enter wrdev, iclass 20, count 2 2006.173.05:29:01.31#ibcon#first serial, iclass 20, count 2 2006.173.05:29:01.31#ibcon#enter sib2, iclass 20, count 2 2006.173.05:29:01.31#ibcon#flushed, iclass 20, count 2 2006.173.05:29:01.31#ibcon#about to write, iclass 20, count 2 2006.173.05:29:01.31#ibcon#wrote, iclass 20, count 2 2006.173.05:29:01.31#ibcon#about to read 3, iclass 20, count 2 2006.173.05:29:01.33#ibcon#read 3, iclass 20, count 2 2006.173.05:29:01.33#ibcon#about to read 4, iclass 20, count 2 2006.173.05:29:01.33#ibcon#read 4, iclass 20, count 2 2006.173.05:29:01.33#ibcon#about to read 5, iclass 20, count 2 2006.173.05:29:01.33#ibcon#read 5, iclass 20, count 2 2006.173.05:29:01.33#ibcon#about to read 6, iclass 20, count 2 2006.173.05:29:01.33#ibcon#read 6, iclass 20, count 2 2006.173.05:29:01.33#ibcon#end of sib2, iclass 20, count 2 2006.173.05:29:01.33#ibcon#*mode == 0, iclass 20, count 2 2006.173.05:29:01.33#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.05:29:01.33#ibcon#[27=AT02-04\r\n] 2006.173.05:29:01.33#ibcon#*before write, iclass 20, count 2 2006.173.05:29:01.33#ibcon#enter sib2, iclass 20, count 2 2006.173.05:29:01.33#ibcon#flushed, iclass 20, count 2 2006.173.05:29:01.33#ibcon#about to write, iclass 20, count 2 2006.173.05:29:01.33#ibcon#wrote, iclass 20, count 2 2006.173.05:29:01.33#ibcon#about to read 3, iclass 20, count 2 2006.173.05:29:01.36#ibcon#read 3, iclass 20, count 2 2006.173.05:29:01.36#ibcon#about to read 4, iclass 20, count 2 2006.173.05:29:01.36#ibcon#read 4, iclass 20, count 2 2006.173.05:29:01.36#ibcon#about to read 5, iclass 20, count 2 2006.173.05:29:01.36#ibcon#read 5, iclass 20, count 2 2006.173.05:29:01.36#ibcon#about to read 6, iclass 20, count 2 2006.173.05:29:01.36#ibcon#read 6, iclass 20, count 2 2006.173.05:29:01.36#ibcon#end of sib2, iclass 20, count 2 2006.173.05:29:01.36#ibcon#*after write, iclass 20, count 2 2006.173.05:29:01.36#ibcon#*before return 0, iclass 20, count 2 2006.173.05:29:01.36#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.05:29:01.36#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.05:29:01.36#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.05:29:01.36#ibcon#ireg 7 cls_cnt 0 2006.173.05:29:01.36#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.05:29:01.48#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.05:29:01.48#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.05:29:01.48#ibcon#enter wrdev, iclass 20, count 0 2006.173.05:29:01.48#ibcon#first serial, iclass 20, count 0 2006.173.05:29:01.48#ibcon#enter sib2, iclass 20, count 0 2006.173.05:29:01.48#ibcon#flushed, iclass 20, count 0 2006.173.05:29:01.48#ibcon#about to write, iclass 20, count 0 2006.173.05:29:01.48#ibcon#wrote, iclass 20, count 0 2006.173.05:29:01.48#ibcon#about to read 3, iclass 20, count 0 2006.173.05:29:01.50#ibcon#read 3, iclass 20, count 0 2006.173.05:29:01.50#ibcon#about to read 4, iclass 20, count 0 2006.173.05:29:01.50#ibcon#read 4, iclass 20, count 0 2006.173.05:29:01.50#ibcon#about to read 5, iclass 20, count 0 2006.173.05:29:01.50#ibcon#read 5, iclass 20, count 0 2006.173.05:29:01.50#ibcon#about to read 6, iclass 20, count 0 2006.173.05:29:01.50#ibcon#read 6, iclass 20, count 0 2006.173.05:29:01.50#ibcon#end of sib2, iclass 20, count 0 2006.173.05:29:01.50#ibcon#*mode == 0, iclass 20, count 0 2006.173.05:29:01.50#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.05:29:01.50#ibcon#[27=USB\r\n] 2006.173.05:29:01.50#ibcon#*before write, iclass 20, count 0 2006.173.05:29:01.50#ibcon#enter sib2, iclass 20, count 0 2006.173.05:29:01.50#ibcon#flushed, iclass 20, count 0 2006.173.05:29:01.50#ibcon#about to write, iclass 20, count 0 2006.173.05:29:01.50#ibcon#wrote, iclass 20, count 0 2006.173.05:29:01.50#ibcon#about to read 3, iclass 20, count 0 2006.173.05:29:01.53#ibcon#read 3, iclass 20, count 0 2006.173.05:29:01.53#ibcon#about to read 4, iclass 20, count 0 2006.173.05:29:01.53#ibcon#read 4, iclass 20, count 0 2006.173.05:29:01.53#ibcon#about to read 5, iclass 20, count 0 2006.173.05:29:01.53#ibcon#read 5, iclass 20, count 0 2006.173.05:29:01.53#ibcon#about to read 6, iclass 20, count 0 2006.173.05:29:01.53#ibcon#read 6, iclass 20, count 0 2006.173.05:29:01.53#ibcon#end of sib2, iclass 20, count 0 2006.173.05:29:01.53#ibcon#*after write, iclass 20, count 0 2006.173.05:29:01.53#ibcon#*before return 0, iclass 20, count 0 2006.173.05:29:01.53#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.05:29:01.53#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.05:29:01.53#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.05:29:01.53#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.05:29:01.53$vck44/vblo=3,649.99 2006.173.05:29:01.53#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.05:29:01.53#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.05:29:01.53#ibcon#ireg 17 cls_cnt 0 2006.173.05:29:01.53#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.05:29:01.53#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.05:29:01.53#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.05:29:01.53#ibcon#enter wrdev, iclass 22, count 0 2006.173.05:29:01.53#ibcon#first serial, iclass 22, count 0 2006.173.05:29:01.53#ibcon#enter sib2, iclass 22, count 0 2006.173.05:29:01.53#ibcon#flushed, iclass 22, count 0 2006.173.05:29:01.53#ibcon#about to write, iclass 22, count 0 2006.173.05:29:01.53#ibcon#wrote, iclass 22, count 0 2006.173.05:29:01.53#ibcon#about to read 3, iclass 22, count 0 2006.173.05:29:01.55#ibcon#read 3, iclass 22, count 0 2006.173.05:29:01.55#ibcon#about to read 4, iclass 22, count 0 2006.173.05:29:01.55#ibcon#read 4, iclass 22, count 0 2006.173.05:29:01.55#ibcon#about to read 5, iclass 22, count 0 2006.173.05:29:01.55#ibcon#read 5, iclass 22, count 0 2006.173.05:29:01.55#ibcon#about to read 6, iclass 22, count 0 2006.173.05:29:01.55#ibcon#read 6, iclass 22, count 0 2006.173.05:29:01.55#ibcon#end of sib2, iclass 22, count 0 2006.173.05:29:01.55#ibcon#*mode == 0, iclass 22, count 0 2006.173.05:29:01.55#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.05:29:01.55#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.05:29:01.55#ibcon#*before write, iclass 22, count 0 2006.173.05:29:01.55#ibcon#enter sib2, iclass 22, count 0 2006.173.05:29:01.55#ibcon#flushed, iclass 22, count 0 2006.173.05:29:01.55#ibcon#about to write, iclass 22, count 0 2006.173.05:29:01.55#ibcon#wrote, iclass 22, count 0 2006.173.05:29:01.55#ibcon#about to read 3, iclass 22, count 0 2006.173.05:29:01.59#ibcon#read 3, iclass 22, count 0 2006.173.05:29:01.59#ibcon#about to read 4, iclass 22, count 0 2006.173.05:29:01.59#ibcon#read 4, iclass 22, count 0 2006.173.05:29:01.59#ibcon#about to read 5, iclass 22, count 0 2006.173.05:29:01.59#ibcon#read 5, iclass 22, count 0 2006.173.05:29:01.73#ibcon#about to read 6, iclass 22, count 0 2006.173.05:29:01.73#ibcon#read 6, iclass 22, count 0 2006.173.05:29:01.73#ibcon#end of sib2, iclass 22, count 0 2006.173.05:29:01.73#ibcon#*after write, iclass 22, count 0 2006.173.05:29:01.73#ibcon#*before return 0, iclass 22, count 0 2006.173.05:29:01.73#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.05:29:01.73#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.05:29:01.73#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.05:29:01.73#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.05:29:01.73$vck44/vb=3,4 2006.173.05:29:01.73#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.05:29:01.73#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.05:29:01.73#ibcon#ireg 11 cls_cnt 2 2006.173.05:29:01.73#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.05:29:01.73#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.05:29:01.73#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.05:29:01.73#ibcon#enter wrdev, iclass 24, count 2 2006.173.05:29:01.73#ibcon#first serial, iclass 24, count 2 2006.173.05:29:01.74#ibcon#enter sib2, iclass 24, count 2 2006.173.05:29:01.74#ibcon#flushed, iclass 24, count 2 2006.173.05:29:01.74#ibcon#about to write, iclass 24, count 2 2006.173.05:29:01.74#ibcon#wrote, iclass 24, count 2 2006.173.05:29:01.74#ibcon#about to read 3, iclass 24, count 2 2006.173.05:29:01.75#ibcon#read 3, iclass 24, count 2 2006.173.05:29:01.75#ibcon#about to read 4, iclass 24, count 2 2006.173.05:29:01.75#ibcon#read 4, iclass 24, count 2 2006.173.05:29:01.75#ibcon#about to read 5, iclass 24, count 2 2006.173.05:29:01.75#ibcon#read 5, iclass 24, count 2 2006.173.05:29:01.75#ibcon#about to read 6, iclass 24, count 2 2006.173.05:29:01.75#ibcon#read 6, iclass 24, count 2 2006.173.05:29:01.75#ibcon#end of sib2, iclass 24, count 2 2006.173.05:29:01.75#ibcon#*mode == 0, iclass 24, count 2 2006.173.05:29:01.75#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.05:29:01.75#ibcon#[27=AT03-04\r\n] 2006.173.05:29:01.75#ibcon#*before write, iclass 24, count 2 2006.173.05:29:01.75#ibcon#enter sib2, iclass 24, count 2 2006.173.05:29:01.75#ibcon#flushed, iclass 24, count 2 2006.173.05:29:01.75#ibcon#about to write, iclass 24, count 2 2006.173.05:29:01.75#ibcon#wrote, iclass 24, count 2 2006.173.05:29:01.75#ibcon#about to read 3, iclass 24, count 2 2006.173.05:29:01.78#ibcon#read 3, iclass 24, count 2 2006.173.05:29:01.78#ibcon#about to read 4, iclass 24, count 2 2006.173.05:29:01.78#ibcon#read 4, iclass 24, count 2 2006.173.05:29:01.78#ibcon#about to read 5, iclass 24, count 2 2006.173.05:29:01.78#ibcon#read 5, iclass 24, count 2 2006.173.05:29:01.78#ibcon#about to read 6, iclass 24, count 2 2006.173.05:29:01.78#ibcon#read 6, iclass 24, count 2 2006.173.05:29:01.78#ibcon#end of sib2, iclass 24, count 2 2006.173.05:29:01.78#ibcon#*after write, iclass 24, count 2 2006.173.05:29:01.78#ibcon#*before return 0, iclass 24, count 2 2006.173.05:29:01.78#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.05:29:01.78#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.05:29:01.78#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.05:29:01.78#ibcon#ireg 7 cls_cnt 0 2006.173.05:29:01.78#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.05:29:01.90#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.05:29:01.90#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.05:29:01.90#ibcon#enter wrdev, iclass 24, count 0 2006.173.05:29:01.90#ibcon#first serial, iclass 24, count 0 2006.173.05:29:01.90#ibcon#enter sib2, iclass 24, count 0 2006.173.05:29:01.90#ibcon#flushed, iclass 24, count 0 2006.173.05:29:01.90#ibcon#about to write, iclass 24, count 0 2006.173.05:29:01.90#ibcon#wrote, iclass 24, count 0 2006.173.05:29:01.90#ibcon#about to read 3, iclass 24, count 0 2006.173.05:29:01.92#ibcon#read 3, iclass 24, count 0 2006.173.05:29:01.92#ibcon#about to read 4, iclass 24, count 0 2006.173.05:29:01.92#ibcon#read 4, iclass 24, count 0 2006.173.05:29:01.92#ibcon#about to read 5, iclass 24, count 0 2006.173.05:29:01.92#ibcon#read 5, iclass 24, count 0 2006.173.05:29:01.92#ibcon#about to read 6, iclass 24, count 0 2006.173.05:29:01.92#ibcon#read 6, iclass 24, count 0 2006.173.05:29:01.92#ibcon#end of sib2, iclass 24, count 0 2006.173.05:29:01.92#ibcon#*mode == 0, iclass 24, count 0 2006.173.05:29:01.92#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.05:29:01.92#ibcon#[27=USB\r\n] 2006.173.05:29:01.92#ibcon#*before write, iclass 24, count 0 2006.173.05:29:01.92#ibcon#enter sib2, iclass 24, count 0 2006.173.05:29:01.92#ibcon#flushed, iclass 24, count 0 2006.173.05:29:01.92#ibcon#about to write, iclass 24, count 0 2006.173.05:29:01.92#ibcon#wrote, iclass 24, count 0 2006.173.05:29:01.92#ibcon#about to read 3, iclass 24, count 0 2006.173.05:29:01.95#ibcon#read 3, iclass 24, count 0 2006.173.05:29:01.95#ibcon#about to read 4, iclass 24, count 0 2006.173.05:29:01.95#ibcon#read 4, iclass 24, count 0 2006.173.05:29:01.95#ibcon#about to read 5, iclass 24, count 0 2006.173.05:29:01.95#ibcon#read 5, iclass 24, count 0 2006.173.05:29:01.95#ibcon#about to read 6, iclass 24, count 0 2006.173.05:29:01.95#ibcon#read 6, iclass 24, count 0 2006.173.05:29:01.95#ibcon#end of sib2, iclass 24, count 0 2006.173.05:29:01.95#ibcon#*after write, iclass 24, count 0 2006.173.05:29:01.95#ibcon#*before return 0, iclass 24, count 0 2006.173.05:29:01.95#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.05:29:01.95#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.05:29:01.95#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.05:29:01.95#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.05:29:01.95$vck44/vblo=4,679.99 2006.173.05:29:01.95#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.05:29:01.95#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.05:29:01.95#ibcon#ireg 17 cls_cnt 0 2006.173.05:29:01.95#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.05:29:01.95#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.05:29:01.95#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.05:29:01.95#ibcon#enter wrdev, iclass 26, count 0 2006.173.05:29:01.95#ibcon#first serial, iclass 26, count 0 2006.173.05:29:01.95#ibcon#enter sib2, iclass 26, count 0 2006.173.05:29:01.95#ibcon#flushed, iclass 26, count 0 2006.173.05:29:01.95#ibcon#about to write, iclass 26, count 0 2006.173.05:29:01.95#ibcon#wrote, iclass 26, count 0 2006.173.05:29:01.95#ibcon#about to read 3, iclass 26, count 0 2006.173.05:29:01.97#ibcon#read 3, iclass 26, count 0 2006.173.05:29:01.97#ibcon#about to read 4, iclass 26, count 0 2006.173.05:29:01.97#ibcon#read 4, iclass 26, count 0 2006.173.05:29:01.97#ibcon#about to read 5, iclass 26, count 0 2006.173.05:29:01.97#ibcon#read 5, iclass 26, count 0 2006.173.05:29:01.97#ibcon#about to read 6, iclass 26, count 0 2006.173.05:29:01.97#ibcon#read 6, iclass 26, count 0 2006.173.05:29:01.97#ibcon#end of sib2, iclass 26, count 0 2006.173.05:29:01.97#ibcon#*mode == 0, iclass 26, count 0 2006.173.05:29:01.97#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.05:29:01.97#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.05:29:01.97#ibcon#*before write, iclass 26, count 0 2006.173.05:29:01.97#ibcon#enter sib2, iclass 26, count 0 2006.173.05:29:01.97#ibcon#flushed, iclass 26, count 0 2006.173.05:29:01.97#ibcon#about to write, iclass 26, count 0 2006.173.05:29:01.97#ibcon#wrote, iclass 26, count 0 2006.173.05:29:01.97#ibcon#about to read 3, iclass 26, count 0 2006.173.05:29:02.01#ibcon#read 3, iclass 26, count 0 2006.173.05:29:02.01#ibcon#about to read 4, iclass 26, count 0 2006.173.05:29:02.01#ibcon#read 4, iclass 26, count 0 2006.173.05:29:02.01#ibcon#about to read 5, iclass 26, count 0 2006.173.05:29:02.01#ibcon#read 5, iclass 26, count 0 2006.173.05:29:02.01#ibcon#about to read 6, iclass 26, count 0 2006.173.05:29:02.01#ibcon#read 6, iclass 26, count 0 2006.173.05:29:02.01#ibcon#end of sib2, iclass 26, count 0 2006.173.05:29:02.01#ibcon#*after write, iclass 26, count 0 2006.173.05:29:02.01#ibcon#*before return 0, iclass 26, count 0 2006.173.05:29:02.01#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.05:29:02.01#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.05:29:02.01#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.05:29:02.01#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.05:29:02.01$vck44/vb=4,4 2006.173.05:29:02.01#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.05:29:02.01#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.05:29:02.01#ibcon#ireg 11 cls_cnt 2 2006.173.05:29:02.01#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.05:29:02.07#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.05:29:02.07#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.05:29:02.07#ibcon#enter wrdev, iclass 28, count 2 2006.173.05:29:02.07#ibcon#first serial, iclass 28, count 2 2006.173.05:29:02.07#ibcon#enter sib2, iclass 28, count 2 2006.173.05:29:02.07#ibcon#flushed, iclass 28, count 2 2006.173.05:29:02.07#ibcon#about to write, iclass 28, count 2 2006.173.05:29:02.07#ibcon#wrote, iclass 28, count 2 2006.173.05:29:02.07#ibcon#about to read 3, iclass 28, count 2 2006.173.05:29:02.09#ibcon#read 3, iclass 28, count 2 2006.173.05:29:02.09#ibcon#about to read 4, iclass 28, count 2 2006.173.05:29:02.09#ibcon#read 4, iclass 28, count 2 2006.173.05:29:02.09#ibcon#about to read 5, iclass 28, count 2 2006.173.05:29:02.09#ibcon#read 5, iclass 28, count 2 2006.173.05:29:02.09#ibcon#about to read 6, iclass 28, count 2 2006.173.05:29:02.09#ibcon#read 6, iclass 28, count 2 2006.173.05:29:02.09#ibcon#end of sib2, iclass 28, count 2 2006.173.05:29:02.09#ibcon#*mode == 0, iclass 28, count 2 2006.173.05:29:02.09#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.05:29:02.09#ibcon#[27=AT04-04\r\n] 2006.173.05:29:02.09#ibcon#*before write, iclass 28, count 2 2006.173.05:29:02.09#ibcon#enter sib2, iclass 28, count 2 2006.173.05:29:02.09#ibcon#flushed, iclass 28, count 2 2006.173.05:29:02.09#ibcon#about to write, iclass 28, count 2 2006.173.05:29:02.09#ibcon#wrote, iclass 28, count 2 2006.173.05:29:02.09#ibcon#about to read 3, iclass 28, count 2 2006.173.05:29:02.12#ibcon#read 3, iclass 28, count 2 2006.173.05:29:02.12#ibcon#about to read 4, iclass 28, count 2 2006.173.05:29:02.12#ibcon#read 4, iclass 28, count 2 2006.173.05:29:02.12#ibcon#about to read 5, iclass 28, count 2 2006.173.05:29:02.12#ibcon#read 5, iclass 28, count 2 2006.173.05:29:02.12#ibcon#about to read 6, iclass 28, count 2 2006.173.05:29:02.12#ibcon#read 6, iclass 28, count 2 2006.173.05:29:02.12#ibcon#end of sib2, iclass 28, count 2 2006.173.05:29:02.12#ibcon#*after write, iclass 28, count 2 2006.173.05:29:02.12#ibcon#*before return 0, iclass 28, count 2 2006.173.05:29:02.12#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.05:29:02.12#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.05:29:02.12#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.05:29:02.12#ibcon#ireg 7 cls_cnt 0 2006.173.05:29:02.12#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.05:29:02.24#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.05:29:02.24#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.05:29:02.24#ibcon#enter wrdev, iclass 28, count 0 2006.173.05:29:02.24#ibcon#first serial, iclass 28, count 0 2006.173.05:29:02.24#ibcon#enter sib2, iclass 28, count 0 2006.173.05:29:02.24#ibcon#flushed, iclass 28, count 0 2006.173.05:29:02.24#ibcon#about to write, iclass 28, count 0 2006.173.05:29:02.24#ibcon#wrote, iclass 28, count 0 2006.173.05:29:02.24#ibcon#about to read 3, iclass 28, count 0 2006.173.05:29:02.26#ibcon#read 3, iclass 28, count 0 2006.173.05:29:02.26#ibcon#about to read 4, iclass 28, count 0 2006.173.05:29:02.26#ibcon#read 4, iclass 28, count 0 2006.173.05:29:02.26#ibcon#about to read 5, iclass 28, count 0 2006.173.05:29:02.26#ibcon#read 5, iclass 28, count 0 2006.173.05:29:02.26#ibcon#about to read 6, iclass 28, count 0 2006.173.05:29:02.26#ibcon#read 6, iclass 28, count 0 2006.173.05:29:02.26#ibcon#end of sib2, iclass 28, count 0 2006.173.05:29:02.26#ibcon#*mode == 0, iclass 28, count 0 2006.173.05:29:02.26#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.05:29:02.26#ibcon#[27=USB\r\n] 2006.173.05:29:02.26#ibcon#*before write, iclass 28, count 0 2006.173.05:29:02.26#ibcon#enter sib2, iclass 28, count 0 2006.173.05:29:02.26#ibcon#flushed, iclass 28, count 0 2006.173.05:29:02.26#ibcon#about to write, iclass 28, count 0 2006.173.05:29:02.26#ibcon#wrote, iclass 28, count 0 2006.173.05:29:02.26#ibcon#about to read 3, iclass 28, count 0 2006.173.05:29:02.29#ibcon#read 3, iclass 28, count 0 2006.173.05:29:02.29#ibcon#about to read 4, iclass 28, count 0 2006.173.05:29:02.29#ibcon#read 4, iclass 28, count 0 2006.173.05:29:02.29#ibcon#about to read 5, iclass 28, count 0 2006.173.05:29:02.29#ibcon#read 5, iclass 28, count 0 2006.173.05:29:02.29#ibcon#about to read 6, iclass 28, count 0 2006.173.05:29:02.29#ibcon#read 6, iclass 28, count 0 2006.173.05:29:02.29#ibcon#end of sib2, iclass 28, count 0 2006.173.05:29:02.29#ibcon#*after write, iclass 28, count 0 2006.173.05:29:02.29#ibcon#*before return 0, iclass 28, count 0 2006.173.05:29:02.29#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.05:29:02.29#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.05:29:02.29#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.05:29:02.29#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.05:29:02.29$vck44/vblo=5,709.99 2006.173.05:29:02.29#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.05:29:02.29#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.05:29:02.29#ibcon#ireg 17 cls_cnt 0 2006.173.05:29:02.29#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.05:29:02.29#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.05:29:02.29#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.05:29:02.29#ibcon#enter wrdev, iclass 30, count 0 2006.173.05:29:02.29#ibcon#first serial, iclass 30, count 0 2006.173.05:29:02.29#ibcon#enter sib2, iclass 30, count 0 2006.173.05:29:02.29#ibcon#flushed, iclass 30, count 0 2006.173.05:29:02.29#ibcon#about to write, iclass 30, count 0 2006.173.05:29:02.29#ibcon#wrote, iclass 30, count 0 2006.173.05:29:02.29#ibcon#about to read 3, iclass 30, count 0 2006.173.05:29:02.31#ibcon#read 3, iclass 30, count 0 2006.173.05:29:02.31#ibcon#about to read 4, iclass 30, count 0 2006.173.05:29:02.31#ibcon#read 4, iclass 30, count 0 2006.173.05:29:02.31#ibcon#about to read 5, iclass 30, count 0 2006.173.05:29:02.31#ibcon#read 5, iclass 30, count 0 2006.173.05:29:02.31#ibcon#about to read 6, iclass 30, count 0 2006.173.05:29:02.31#ibcon#read 6, iclass 30, count 0 2006.173.05:29:02.31#ibcon#end of sib2, iclass 30, count 0 2006.173.05:29:02.31#ibcon#*mode == 0, iclass 30, count 0 2006.173.05:29:02.31#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.05:29:02.31#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.05:29:02.31#ibcon#*before write, iclass 30, count 0 2006.173.05:29:02.31#ibcon#enter sib2, iclass 30, count 0 2006.173.05:29:02.31#ibcon#flushed, iclass 30, count 0 2006.173.05:29:02.31#ibcon#about to write, iclass 30, count 0 2006.173.05:29:02.31#ibcon#wrote, iclass 30, count 0 2006.173.05:29:02.31#ibcon#about to read 3, iclass 30, count 0 2006.173.05:29:02.35#ibcon#read 3, iclass 30, count 0 2006.173.05:29:02.35#ibcon#about to read 4, iclass 30, count 0 2006.173.05:29:02.35#ibcon#read 4, iclass 30, count 0 2006.173.05:29:02.35#ibcon#about to read 5, iclass 30, count 0 2006.173.05:29:02.35#ibcon#read 5, iclass 30, count 0 2006.173.05:29:02.35#ibcon#about to read 6, iclass 30, count 0 2006.173.05:29:02.35#ibcon#read 6, iclass 30, count 0 2006.173.05:29:02.35#ibcon#end of sib2, iclass 30, count 0 2006.173.05:29:02.35#ibcon#*after write, iclass 30, count 0 2006.173.05:29:02.35#ibcon#*before return 0, iclass 30, count 0 2006.173.05:29:02.35#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.05:29:02.35#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.05:29:02.35#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.05:29:02.35#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.05:29:02.35$vck44/vb=5,4 2006.173.05:29:02.35#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.173.05:29:02.35#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.173.05:29:02.35#ibcon#ireg 11 cls_cnt 2 2006.173.05:29:02.35#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.05:29:02.41#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.05:29:02.41#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.05:29:02.41#ibcon#enter wrdev, iclass 32, count 2 2006.173.05:29:02.41#ibcon#first serial, iclass 32, count 2 2006.173.05:29:02.41#ibcon#enter sib2, iclass 32, count 2 2006.173.05:29:02.41#ibcon#flushed, iclass 32, count 2 2006.173.05:29:02.41#ibcon#about to write, iclass 32, count 2 2006.173.05:29:02.41#ibcon#wrote, iclass 32, count 2 2006.173.05:29:02.41#ibcon#about to read 3, iclass 32, count 2 2006.173.05:29:02.43#ibcon#read 3, iclass 32, count 2 2006.173.05:29:02.43#ibcon#about to read 4, iclass 32, count 2 2006.173.05:29:02.43#ibcon#read 4, iclass 32, count 2 2006.173.05:29:02.43#ibcon#about to read 5, iclass 32, count 2 2006.173.05:29:02.43#ibcon#read 5, iclass 32, count 2 2006.173.05:29:02.43#ibcon#about to read 6, iclass 32, count 2 2006.173.05:29:02.43#ibcon#read 6, iclass 32, count 2 2006.173.05:29:02.43#ibcon#end of sib2, iclass 32, count 2 2006.173.05:29:02.43#ibcon#*mode == 0, iclass 32, count 2 2006.173.05:29:02.43#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.173.05:29:02.43#ibcon#[27=AT05-04\r\n] 2006.173.05:29:02.43#ibcon#*before write, iclass 32, count 2 2006.173.05:29:02.43#ibcon#enter sib2, iclass 32, count 2 2006.173.05:29:02.43#ibcon#flushed, iclass 32, count 2 2006.173.05:29:02.43#ibcon#about to write, iclass 32, count 2 2006.173.05:29:02.43#ibcon#wrote, iclass 32, count 2 2006.173.05:29:02.43#ibcon#about to read 3, iclass 32, count 2 2006.173.05:29:02.46#ibcon#read 3, iclass 32, count 2 2006.173.05:29:02.46#ibcon#about to read 4, iclass 32, count 2 2006.173.05:29:02.46#ibcon#read 4, iclass 32, count 2 2006.173.05:29:02.46#ibcon#about to read 5, iclass 32, count 2 2006.173.05:29:02.46#ibcon#read 5, iclass 32, count 2 2006.173.05:29:02.46#ibcon#about to read 6, iclass 32, count 2 2006.173.05:29:02.46#ibcon#read 6, iclass 32, count 2 2006.173.05:29:02.46#ibcon#end of sib2, iclass 32, count 2 2006.173.05:29:02.46#ibcon#*after write, iclass 32, count 2 2006.173.05:29:02.46#ibcon#*before return 0, iclass 32, count 2 2006.173.05:29:02.46#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.05:29:02.46#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.173.05:29:02.46#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.173.05:29:02.46#ibcon#ireg 7 cls_cnt 0 2006.173.05:29:02.46#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.05:29:02.58#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.05:29:02.58#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.05:29:02.58#ibcon#enter wrdev, iclass 32, count 0 2006.173.05:29:02.58#ibcon#first serial, iclass 32, count 0 2006.173.05:29:02.58#ibcon#enter sib2, iclass 32, count 0 2006.173.05:29:02.58#ibcon#flushed, iclass 32, count 0 2006.173.05:29:02.58#ibcon#about to write, iclass 32, count 0 2006.173.05:29:02.58#ibcon#wrote, iclass 32, count 0 2006.173.05:29:02.58#ibcon#about to read 3, iclass 32, count 0 2006.173.05:29:02.60#ibcon#read 3, iclass 32, count 0 2006.173.05:29:02.60#ibcon#about to read 4, iclass 32, count 0 2006.173.05:29:02.60#ibcon#read 4, iclass 32, count 0 2006.173.05:29:02.60#ibcon#about to read 5, iclass 32, count 0 2006.173.05:29:02.60#ibcon#read 5, iclass 32, count 0 2006.173.05:29:02.60#ibcon#about to read 6, iclass 32, count 0 2006.173.05:29:02.60#ibcon#read 6, iclass 32, count 0 2006.173.05:29:02.60#ibcon#end of sib2, iclass 32, count 0 2006.173.05:29:02.60#ibcon#*mode == 0, iclass 32, count 0 2006.173.05:29:02.60#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.05:29:02.66#ibcon#[27=USB\r\n] 2006.173.05:29:02.66#ibcon#*before write, iclass 32, count 0 2006.173.05:29:02.66#ibcon#enter sib2, iclass 32, count 0 2006.173.05:29:02.66#ibcon#flushed, iclass 32, count 0 2006.173.05:29:02.66#ibcon#about to write, iclass 32, count 0 2006.173.05:29:02.66#ibcon#wrote, iclass 32, count 0 2006.173.05:29:02.66#ibcon#about to read 3, iclass 32, count 0 2006.173.05:29:02.69#ibcon#read 3, iclass 32, count 0 2006.173.05:29:02.69#ibcon#about to read 4, iclass 32, count 0 2006.173.05:29:02.69#ibcon#read 4, iclass 32, count 0 2006.173.05:29:02.69#ibcon#about to read 5, iclass 32, count 0 2006.173.05:29:02.69#ibcon#read 5, iclass 32, count 0 2006.173.05:29:02.69#ibcon#about to read 6, iclass 32, count 0 2006.173.05:29:02.69#ibcon#read 6, iclass 32, count 0 2006.173.05:29:02.69#ibcon#end of sib2, iclass 32, count 0 2006.173.05:29:02.69#ibcon#*after write, iclass 32, count 0 2006.173.05:29:02.69#ibcon#*before return 0, iclass 32, count 0 2006.173.05:29:02.69#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.05:29:02.69#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.173.05:29:02.69#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.05:29:02.69#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.05:29:02.69$vck44/vblo=6,719.99 2006.173.05:29:02.69#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.05:29:02.69#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.05:29:02.69#ibcon#ireg 17 cls_cnt 0 2006.173.05:29:02.69#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.05:29:02.69#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.05:29:02.69#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.05:29:02.69#ibcon#enter wrdev, iclass 34, count 0 2006.173.05:29:02.69#ibcon#first serial, iclass 34, count 0 2006.173.05:29:02.69#ibcon#enter sib2, iclass 34, count 0 2006.173.05:29:02.69#ibcon#flushed, iclass 34, count 0 2006.173.05:29:02.69#ibcon#about to write, iclass 34, count 0 2006.173.05:29:02.69#ibcon#wrote, iclass 34, count 0 2006.173.05:29:02.69#ibcon#about to read 3, iclass 34, count 0 2006.173.05:29:02.71#ibcon#read 3, iclass 34, count 0 2006.173.05:29:02.71#ibcon#about to read 4, iclass 34, count 0 2006.173.05:29:02.71#ibcon#read 4, iclass 34, count 0 2006.173.05:29:02.71#ibcon#about to read 5, iclass 34, count 0 2006.173.05:29:02.71#ibcon#read 5, iclass 34, count 0 2006.173.05:29:02.71#ibcon#about to read 6, iclass 34, count 0 2006.173.05:29:02.71#ibcon#read 6, iclass 34, count 0 2006.173.05:29:02.71#ibcon#end of sib2, iclass 34, count 0 2006.173.05:29:02.71#ibcon#*mode == 0, iclass 34, count 0 2006.173.05:29:02.71#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.05:29:02.71#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.05:29:02.71#ibcon#*before write, iclass 34, count 0 2006.173.05:29:02.71#ibcon#enter sib2, iclass 34, count 0 2006.173.05:29:02.71#ibcon#flushed, iclass 34, count 0 2006.173.05:29:02.71#ibcon#about to write, iclass 34, count 0 2006.173.05:29:02.71#ibcon#wrote, iclass 34, count 0 2006.173.05:29:02.71#ibcon#about to read 3, iclass 34, count 0 2006.173.05:29:02.75#ibcon#read 3, iclass 34, count 0 2006.173.05:29:02.75#ibcon#about to read 4, iclass 34, count 0 2006.173.05:29:02.75#ibcon#read 4, iclass 34, count 0 2006.173.05:29:02.75#ibcon#about to read 5, iclass 34, count 0 2006.173.05:29:02.75#ibcon#read 5, iclass 34, count 0 2006.173.05:29:02.75#ibcon#about to read 6, iclass 34, count 0 2006.173.05:29:02.75#ibcon#read 6, iclass 34, count 0 2006.173.05:29:02.75#ibcon#end of sib2, iclass 34, count 0 2006.173.05:29:02.75#ibcon#*after write, iclass 34, count 0 2006.173.05:29:02.75#ibcon#*before return 0, iclass 34, count 0 2006.173.05:29:02.75#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.05:29:02.75#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.05:29:02.75#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.05:29:02.75#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.05:29:02.75$vck44/vb=6,4 2006.173.05:29:02.75#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.05:29:02.75#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.05:29:02.75#ibcon#ireg 11 cls_cnt 2 2006.173.05:29:02.75#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.05:29:02.81#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.05:29:02.81#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.05:29:02.81#ibcon#enter wrdev, iclass 36, count 2 2006.173.05:29:02.81#ibcon#first serial, iclass 36, count 2 2006.173.05:29:02.81#ibcon#enter sib2, iclass 36, count 2 2006.173.05:29:02.81#ibcon#flushed, iclass 36, count 2 2006.173.05:29:02.81#ibcon#about to write, iclass 36, count 2 2006.173.05:29:02.81#ibcon#wrote, iclass 36, count 2 2006.173.05:29:02.81#ibcon#about to read 3, iclass 36, count 2 2006.173.05:29:02.83#ibcon#read 3, iclass 36, count 2 2006.173.05:29:02.83#ibcon#about to read 4, iclass 36, count 2 2006.173.05:29:02.83#ibcon#read 4, iclass 36, count 2 2006.173.05:29:02.83#ibcon#about to read 5, iclass 36, count 2 2006.173.05:29:02.83#ibcon#read 5, iclass 36, count 2 2006.173.05:29:02.83#ibcon#about to read 6, iclass 36, count 2 2006.173.05:29:02.83#ibcon#read 6, iclass 36, count 2 2006.173.05:29:02.83#ibcon#end of sib2, iclass 36, count 2 2006.173.05:29:02.83#ibcon#*mode == 0, iclass 36, count 2 2006.173.05:29:02.83#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.05:29:02.83#ibcon#[27=AT06-04\r\n] 2006.173.05:29:02.83#ibcon#*before write, iclass 36, count 2 2006.173.05:29:02.83#ibcon#enter sib2, iclass 36, count 2 2006.173.05:29:02.83#ibcon#flushed, iclass 36, count 2 2006.173.05:29:02.83#ibcon#about to write, iclass 36, count 2 2006.173.05:29:02.83#ibcon#wrote, iclass 36, count 2 2006.173.05:29:02.83#ibcon#about to read 3, iclass 36, count 2 2006.173.05:29:02.86#ibcon#read 3, iclass 36, count 2 2006.173.05:29:02.86#ibcon#about to read 4, iclass 36, count 2 2006.173.05:29:02.86#ibcon#read 4, iclass 36, count 2 2006.173.05:29:02.86#ibcon#about to read 5, iclass 36, count 2 2006.173.05:29:02.86#ibcon#read 5, iclass 36, count 2 2006.173.05:29:02.86#ibcon#about to read 6, iclass 36, count 2 2006.173.05:29:02.86#ibcon#read 6, iclass 36, count 2 2006.173.05:29:02.86#ibcon#end of sib2, iclass 36, count 2 2006.173.05:29:02.86#ibcon#*after write, iclass 36, count 2 2006.173.05:29:02.86#ibcon#*before return 0, iclass 36, count 2 2006.173.05:29:02.86#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.05:29:02.86#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.05:29:02.86#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.05:29:02.86#ibcon#ireg 7 cls_cnt 0 2006.173.05:29:02.86#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.05:29:02.93#abcon#<5=/15 0.7 1.5 23.51 781005.4\r\n> 2006.173.05:29:02.95#abcon#{5=INTERFACE CLEAR} 2006.173.05:29:02.98#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.05:29:02.98#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.05:29:02.98#ibcon#enter wrdev, iclass 36, count 0 2006.173.05:29:02.98#ibcon#first serial, iclass 36, count 0 2006.173.05:29:02.98#ibcon#enter sib2, iclass 36, count 0 2006.173.05:29:02.98#ibcon#flushed, iclass 36, count 0 2006.173.05:29:02.98#ibcon#about to write, iclass 36, count 0 2006.173.05:29:02.98#ibcon#wrote, iclass 36, count 0 2006.173.05:29:02.98#ibcon#about to read 3, iclass 36, count 0 2006.173.05:29:03.00#ibcon#read 3, iclass 36, count 0 2006.173.05:29:03.00#ibcon#about to read 4, iclass 36, count 0 2006.173.05:29:03.00#ibcon#read 4, iclass 36, count 0 2006.173.05:29:03.00#ibcon#about to read 5, iclass 36, count 0 2006.173.05:29:03.00#ibcon#read 5, iclass 36, count 0 2006.173.05:29:03.00#ibcon#about to read 6, iclass 36, count 0 2006.173.05:29:03.00#ibcon#read 6, iclass 36, count 0 2006.173.05:29:03.00#ibcon#end of sib2, iclass 36, count 0 2006.173.05:29:03.00#ibcon#*mode == 0, iclass 36, count 0 2006.173.05:29:03.00#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.05:29:03.00#ibcon#[27=USB\r\n] 2006.173.05:29:03.00#ibcon#*before write, iclass 36, count 0 2006.173.05:29:03.00#ibcon#enter sib2, iclass 36, count 0 2006.173.05:29:03.00#ibcon#flushed, iclass 36, count 0 2006.173.05:29:03.00#ibcon#about to write, iclass 36, count 0 2006.173.05:29:03.00#ibcon#wrote, iclass 36, count 0 2006.173.05:29:03.00#ibcon#about to read 3, iclass 36, count 0 2006.173.05:29:03.01#abcon#[5=S1D000X0/0*\r\n] 2006.173.05:29:03.03#ibcon#read 3, iclass 36, count 0 2006.173.05:29:03.03#ibcon#about to read 4, iclass 36, count 0 2006.173.05:29:03.03#ibcon#read 4, iclass 36, count 0 2006.173.05:29:03.03#ibcon#about to read 5, iclass 36, count 0 2006.173.05:29:03.03#ibcon#read 5, iclass 36, count 0 2006.173.05:29:03.03#ibcon#about to read 6, iclass 36, count 0 2006.173.05:29:03.03#ibcon#read 6, iclass 36, count 0 2006.173.05:29:03.03#ibcon#end of sib2, iclass 36, count 0 2006.173.05:29:03.03#ibcon#*after write, iclass 36, count 0 2006.173.05:29:03.03#ibcon#*before return 0, iclass 36, count 0 2006.173.05:29:03.03#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.05:29:03.03#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.05:29:03.03#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.05:29:03.03#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.05:29:03.03$vck44/vblo=7,734.99 2006.173.05:29:03.03#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.05:29:03.03#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.05:29:03.03#ibcon#ireg 17 cls_cnt 0 2006.173.05:29:03.03#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.05:29:03.03#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.05:29:03.03#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.05:29:03.03#ibcon#enter wrdev, iclass 4, count 0 2006.173.05:29:03.03#ibcon#first serial, iclass 4, count 0 2006.173.05:29:03.03#ibcon#enter sib2, iclass 4, count 0 2006.173.05:29:03.03#ibcon#flushed, iclass 4, count 0 2006.173.05:29:03.03#ibcon#about to write, iclass 4, count 0 2006.173.05:29:03.03#ibcon#wrote, iclass 4, count 0 2006.173.05:29:03.03#ibcon#about to read 3, iclass 4, count 0 2006.173.05:29:03.05#ibcon#read 3, iclass 4, count 0 2006.173.05:29:03.05#ibcon#about to read 4, iclass 4, count 0 2006.173.05:29:03.05#ibcon#read 4, iclass 4, count 0 2006.173.05:29:03.05#ibcon#about to read 5, iclass 4, count 0 2006.173.05:29:03.05#ibcon#read 5, iclass 4, count 0 2006.173.05:29:03.05#ibcon#about to read 6, iclass 4, count 0 2006.173.05:29:03.05#ibcon#read 6, iclass 4, count 0 2006.173.05:29:03.05#ibcon#end of sib2, iclass 4, count 0 2006.173.05:29:03.05#ibcon#*mode == 0, iclass 4, count 0 2006.173.05:29:03.05#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.05:29:03.05#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.05:29:03.05#ibcon#*before write, iclass 4, count 0 2006.173.05:29:03.05#ibcon#enter sib2, iclass 4, count 0 2006.173.05:29:03.05#ibcon#flushed, iclass 4, count 0 2006.173.05:29:03.05#ibcon#about to write, iclass 4, count 0 2006.173.05:29:03.05#ibcon#wrote, iclass 4, count 0 2006.173.05:29:03.05#ibcon#about to read 3, iclass 4, count 0 2006.173.05:29:03.09#ibcon#read 3, iclass 4, count 0 2006.173.05:29:03.09#ibcon#about to read 4, iclass 4, count 0 2006.173.05:29:03.09#ibcon#read 4, iclass 4, count 0 2006.173.05:29:03.09#ibcon#about to read 5, iclass 4, count 0 2006.173.05:29:03.09#ibcon#read 5, iclass 4, count 0 2006.173.05:29:03.09#ibcon#about to read 6, iclass 4, count 0 2006.173.05:29:03.09#ibcon#read 6, iclass 4, count 0 2006.173.05:29:03.09#ibcon#end of sib2, iclass 4, count 0 2006.173.05:29:03.09#ibcon#*after write, iclass 4, count 0 2006.173.05:29:03.09#ibcon#*before return 0, iclass 4, count 0 2006.173.05:29:03.09#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.05:29:03.09#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.05:29:03.09#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.05:29:03.09#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.05:29:03.09$vck44/vb=7,4 2006.173.05:29:03.09#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.05:29:03.09#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.05:29:03.09#ibcon#ireg 11 cls_cnt 2 2006.173.05:29:03.09#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.05:29:03.15#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.05:29:03.15#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.05:29:03.15#ibcon#enter wrdev, iclass 6, count 2 2006.173.05:29:03.15#ibcon#first serial, iclass 6, count 2 2006.173.05:29:03.15#ibcon#enter sib2, iclass 6, count 2 2006.173.05:29:03.15#ibcon#flushed, iclass 6, count 2 2006.173.05:29:03.15#ibcon#about to write, iclass 6, count 2 2006.173.05:29:03.15#ibcon#wrote, iclass 6, count 2 2006.173.05:29:03.15#ibcon#about to read 3, iclass 6, count 2 2006.173.05:29:03.17#ibcon#read 3, iclass 6, count 2 2006.173.05:29:03.17#ibcon#about to read 4, iclass 6, count 2 2006.173.05:29:03.17#ibcon#read 4, iclass 6, count 2 2006.173.05:29:03.17#ibcon#about to read 5, iclass 6, count 2 2006.173.05:29:03.17#ibcon#read 5, iclass 6, count 2 2006.173.05:29:03.17#ibcon#about to read 6, iclass 6, count 2 2006.173.05:29:03.17#ibcon#read 6, iclass 6, count 2 2006.173.05:29:03.17#ibcon#end of sib2, iclass 6, count 2 2006.173.05:29:03.17#ibcon#*mode == 0, iclass 6, count 2 2006.173.05:29:03.17#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.05:29:03.17#ibcon#[27=AT07-04\r\n] 2006.173.05:29:03.17#ibcon#*before write, iclass 6, count 2 2006.173.05:29:03.17#ibcon#enter sib2, iclass 6, count 2 2006.173.05:29:03.17#ibcon#flushed, iclass 6, count 2 2006.173.05:29:03.17#ibcon#about to write, iclass 6, count 2 2006.173.05:29:03.17#ibcon#wrote, iclass 6, count 2 2006.173.05:29:03.17#ibcon#about to read 3, iclass 6, count 2 2006.173.05:29:03.20#ibcon#read 3, iclass 6, count 2 2006.173.05:29:03.20#ibcon#about to read 4, iclass 6, count 2 2006.173.05:29:03.20#ibcon#read 4, iclass 6, count 2 2006.173.05:29:03.20#ibcon#about to read 5, iclass 6, count 2 2006.173.05:29:03.20#ibcon#read 5, iclass 6, count 2 2006.173.05:29:03.20#ibcon#about to read 6, iclass 6, count 2 2006.173.05:29:03.20#ibcon#read 6, iclass 6, count 2 2006.173.05:29:03.20#ibcon#end of sib2, iclass 6, count 2 2006.173.05:29:03.20#ibcon#*after write, iclass 6, count 2 2006.173.05:29:03.20#ibcon#*before return 0, iclass 6, count 2 2006.173.05:29:03.20#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.05:29:03.20#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.05:29:03.20#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.05:29:03.20#ibcon#ireg 7 cls_cnt 0 2006.173.05:29:03.20#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.05:29:03.32#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.05:29:03.32#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.05:29:03.32#ibcon#enter wrdev, iclass 6, count 0 2006.173.05:29:03.32#ibcon#first serial, iclass 6, count 0 2006.173.05:29:03.32#ibcon#enter sib2, iclass 6, count 0 2006.173.05:29:03.32#ibcon#flushed, iclass 6, count 0 2006.173.05:29:03.32#ibcon#about to write, iclass 6, count 0 2006.173.05:29:03.32#ibcon#wrote, iclass 6, count 0 2006.173.05:29:03.32#ibcon#about to read 3, iclass 6, count 0 2006.173.05:29:03.34#ibcon#read 3, iclass 6, count 0 2006.173.05:29:03.34#ibcon#about to read 4, iclass 6, count 0 2006.173.05:29:03.34#ibcon#read 4, iclass 6, count 0 2006.173.05:29:03.34#ibcon#about to read 5, iclass 6, count 0 2006.173.05:29:03.34#ibcon#read 5, iclass 6, count 0 2006.173.05:29:03.34#ibcon#about to read 6, iclass 6, count 0 2006.173.05:29:03.34#ibcon#read 6, iclass 6, count 0 2006.173.05:29:03.34#ibcon#end of sib2, iclass 6, count 0 2006.173.05:29:03.34#ibcon#*mode == 0, iclass 6, count 0 2006.173.05:29:03.34#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.05:29:03.34#ibcon#[27=USB\r\n] 2006.173.05:29:03.34#ibcon#*before write, iclass 6, count 0 2006.173.05:29:03.34#ibcon#enter sib2, iclass 6, count 0 2006.173.05:29:03.34#ibcon#flushed, iclass 6, count 0 2006.173.05:29:03.34#ibcon#about to write, iclass 6, count 0 2006.173.05:29:03.34#ibcon#wrote, iclass 6, count 0 2006.173.05:29:03.34#ibcon#about to read 3, iclass 6, count 0 2006.173.05:29:03.37#ibcon#read 3, iclass 6, count 0 2006.173.05:29:03.37#ibcon#about to read 4, iclass 6, count 0 2006.173.05:29:03.37#ibcon#read 4, iclass 6, count 0 2006.173.05:29:03.37#ibcon#about to read 5, iclass 6, count 0 2006.173.05:29:03.37#ibcon#read 5, iclass 6, count 0 2006.173.05:29:03.37#ibcon#about to read 6, iclass 6, count 0 2006.173.05:29:03.37#ibcon#read 6, iclass 6, count 0 2006.173.05:29:03.37#ibcon#end of sib2, iclass 6, count 0 2006.173.05:29:03.37#ibcon#*after write, iclass 6, count 0 2006.173.05:29:03.37#ibcon#*before return 0, iclass 6, count 0 2006.173.05:29:03.37#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.05:29:03.37#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.05:29:03.37#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.05:29:03.37#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.05:29:03.37$vck44/vblo=8,744.99 2006.173.05:29:03.37#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.05:29:03.37#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.05:29:03.37#ibcon#ireg 17 cls_cnt 0 2006.173.05:29:03.37#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.05:29:03.37#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.05:29:03.37#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.05:29:03.37#ibcon#enter wrdev, iclass 10, count 0 2006.173.05:29:03.37#ibcon#first serial, iclass 10, count 0 2006.173.05:29:03.37#ibcon#enter sib2, iclass 10, count 0 2006.173.05:29:03.37#ibcon#flushed, iclass 10, count 0 2006.173.05:29:03.37#ibcon#about to write, iclass 10, count 0 2006.173.05:29:03.37#ibcon#wrote, iclass 10, count 0 2006.173.05:29:03.37#ibcon#about to read 3, iclass 10, count 0 2006.173.05:29:03.39#ibcon#read 3, iclass 10, count 0 2006.173.05:29:03.39#ibcon#about to read 4, iclass 10, count 0 2006.173.05:29:03.39#ibcon#read 4, iclass 10, count 0 2006.173.05:29:03.39#ibcon#about to read 5, iclass 10, count 0 2006.173.05:29:03.39#ibcon#read 5, iclass 10, count 0 2006.173.05:29:03.39#ibcon#about to read 6, iclass 10, count 0 2006.173.05:29:03.39#ibcon#read 6, iclass 10, count 0 2006.173.05:29:03.39#ibcon#end of sib2, iclass 10, count 0 2006.173.05:29:03.39#ibcon#*mode == 0, iclass 10, count 0 2006.173.05:29:03.39#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.05:29:03.39#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.05:29:03.39#ibcon#*before write, iclass 10, count 0 2006.173.05:29:03.39#ibcon#enter sib2, iclass 10, count 0 2006.173.05:29:03.39#ibcon#flushed, iclass 10, count 0 2006.173.05:29:03.39#ibcon#about to write, iclass 10, count 0 2006.173.05:29:03.39#ibcon#wrote, iclass 10, count 0 2006.173.05:29:03.39#ibcon#about to read 3, iclass 10, count 0 2006.173.05:29:03.43#ibcon#read 3, iclass 10, count 0 2006.173.05:29:03.43#ibcon#about to read 4, iclass 10, count 0 2006.173.05:29:03.43#ibcon#read 4, iclass 10, count 0 2006.173.05:29:03.43#ibcon#about to read 5, iclass 10, count 0 2006.173.05:29:03.43#ibcon#read 5, iclass 10, count 0 2006.173.05:29:03.43#ibcon#about to read 6, iclass 10, count 0 2006.173.05:29:03.43#ibcon#read 6, iclass 10, count 0 2006.173.05:29:03.43#ibcon#end of sib2, iclass 10, count 0 2006.173.05:29:03.43#ibcon#*after write, iclass 10, count 0 2006.173.05:29:03.43#ibcon#*before return 0, iclass 10, count 0 2006.173.05:29:03.43#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.05:29:03.43#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.05:29:03.43#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.05:29:03.43#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.05:29:03.43$vck44/vb=8,4 2006.173.05:29:03.43#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.05:29:03.43#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.05:29:03.43#ibcon#ireg 11 cls_cnt 2 2006.173.05:29:03.43#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.05:29:03.49#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.05:29:03.49#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.05:29:03.49#ibcon#enter wrdev, iclass 12, count 2 2006.173.05:29:03.49#ibcon#first serial, iclass 12, count 2 2006.173.05:29:03.49#ibcon#enter sib2, iclass 12, count 2 2006.173.05:29:03.49#ibcon#flushed, iclass 12, count 2 2006.173.05:29:03.49#ibcon#about to write, iclass 12, count 2 2006.173.05:29:03.49#ibcon#wrote, iclass 12, count 2 2006.173.05:29:03.49#ibcon#about to read 3, iclass 12, count 2 2006.173.05:29:03.51#ibcon#read 3, iclass 12, count 2 2006.173.05:29:03.51#ibcon#about to read 4, iclass 12, count 2 2006.173.05:29:03.51#ibcon#read 4, iclass 12, count 2 2006.173.05:29:03.51#ibcon#about to read 5, iclass 12, count 2 2006.173.05:29:03.51#ibcon#read 5, iclass 12, count 2 2006.173.05:29:03.51#ibcon#about to read 6, iclass 12, count 2 2006.173.05:29:03.51#ibcon#read 6, iclass 12, count 2 2006.173.05:29:03.51#ibcon#end of sib2, iclass 12, count 2 2006.173.05:29:03.51#ibcon#*mode == 0, iclass 12, count 2 2006.173.05:29:03.51#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.05:29:03.51#ibcon#[27=AT08-04\r\n] 2006.173.05:29:03.51#ibcon#*before write, iclass 12, count 2 2006.173.05:29:03.51#ibcon#enter sib2, iclass 12, count 2 2006.173.05:29:03.51#ibcon#flushed, iclass 12, count 2 2006.173.05:29:03.51#ibcon#about to write, iclass 12, count 2 2006.173.05:29:03.51#ibcon#wrote, iclass 12, count 2 2006.173.05:29:03.51#ibcon#about to read 3, iclass 12, count 2 2006.173.05:29:03.54#ibcon#read 3, iclass 12, count 2 2006.173.05:29:03.54#ibcon#about to read 4, iclass 12, count 2 2006.173.05:29:03.54#ibcon#read 4, iclass 12, count 2 2006.173.05:29:03.54#ibcon#about to read 5, iclass 12, count 2 2006.173.05:29:03.54#ibcon#read 5, iclass 12, count 2 2006.173.05:29:03.54#ibcon#about to read 6, iclass 12, count 2 2006.173.05:29:03.54#ibcon#read 6, iclass 12, count 2 2006.173.05:29:03.54#ibcon#end of sib2, iclass 12, count 2 2006.173.05:29:03.54#ibcon#*after write, iclass 12, count 2 2006.173.05:29:03.54#ibcon#*before return 0, iclass 12, count 2 2006.173.05:29:03.54#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.05:29:03.54#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.05:29:03.54#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.05:29:03.54#ibcon#ireg 7 cls_cnt 0 2006.173.05:29:03.54#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.05:29:03.66#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.05:29:03.66#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.05:29:03.66#ibcon#enter wrdev, iclass 12, count 0 2006.173.05:29:03.66#ibcon#first serial, iclass 12, count 0 2006.173.05:29:03.66#ibcon#enter sib2, iclass 12, count 0 2006.173.05:29:03.66#ibcon#flushed, iclass 12, count 0 2006.173.05:29:03.66#ibcon#about to write, iclass 12, count 0 2006.173.05:29:03.66#ibcon#wrote, iclass 12, count 0 2006.173.05:29:03.66#ibcon#about to read 3, iclass 12, count 0 2006.173.05:29:03.68#ibcon#read 3, iclass 12, count 0 2006.173.05:29:03.68#ibcon#about to read 4, iclass 12, count 0 2006.173.05:29:03.68#ibcon#read 4, iclass 12, count 0 2006.173.05:29:03.68#ibcon#about to read 5, iclass 12, count 0 2006.173.05:29:03.68#ibcon#read 5, iclass 12, count 0 2006.173.05:29:03.68#ibcon#about to read 6, iclass 12, count 0 2006.173.05:29:03.68#ibcon#read 6, iclass 12, count 0 2006.173.05:29:03.68#ibcon#end of sib2, iclass 12, count 0 2006.173.05:29:03.68#ibcon#*mode == 0, iclass 12, count 0 2006.173.05:29:03.68#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.05:29:03.68#ibcon#[27=USB\r\n] 2006.173.05:29:03.68#ibcon#*before write, iclass 12, count 0 2006.173.05:29:03.68#ibcon#enter sib2, iclass 12, count 0 2006.173.05:29:03.68#ibcon#flushed, iclass 12, count 0 2006.173.05:29:03.68#ibcon#about to write, iclass 12, count 0 2006.173.05:29:03.68#ibcon#wrote, iclass 12, count 0 2006.173.05:29:03.68#ibcon#about to read 3, iclass 12, count 0 2006.173.05:29:03.71#ibcon#read 3, iclass 12, count 0 2006.173.05:29:03.71#ibcon#about to read 4, iclass 12, count 0 2006.173.05:29:03.71#ibcon#read 4, iclass 12, count 0 2006.173.05:29:03.71#ibcon#about to read 5, iclass 12, count 0 2006.173.05:29:03.71#ibcon#read 5, iclass 12, count 0 2006.173.05:29:03.71#ibcon#about to read 6, iclass 12, count 0 2006.173.05:29:03.71#ibcon#read 6, iclass 12, count 0 2006.173.05:29:03.71#ibcon#end of sib2, iclass 12, count 0 2006.173.05:29:03.71#ibcon#*after write, iclass 12, count 0 2006.173.05:29:03.71#ibcon#*before return 0, iclass 12, count 0 2006.173.05:29:03.71#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.05:29:03.71#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.05:29:03.71#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.05:29:03.71#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.05:29:03.71$vck44/vabw=wide 2006.173.05:29:03.71#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.05:29:03.71#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.05:29:03.71#ibcon#ireg 8 cls_cnt 0 2006.173.05:29:03.71#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.05:29:03.71#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.05:29:03.71#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.05:29:03.71#ibcon#enter wrdev, iclass 14, count 0 2006.173.05:29:03.71#ibcon#first serial, iclass 14, count 0 2006.173.05:29:03.71#ibcon#enter sib2, iclass 14, count 0 2006.173.05:29:03.71#ibcon#flushed, iclass 14, count 0 2006.173.05:29:03.71#ibcon#about to write, iclass 14, count 0 2006.173.05:29:03.71#ibcon#wrote, iclass 14, count 0 2006.173.05:29:03.71#ibcon#about to read 3, iclass 14, count 0 2006.173.05:29:03.73#ibcon#read 3, iclass 14, count 0 2006.173.05:29:03.73#ibcon#about to read 4, iclass 14, count 0 2006.173.05:29:03.73#ibcon#read 4, iclass 14, count 0 2006.173.05:29:03.73#ibcon#about to read 5, iclass 14, count 0 2006.173.05:29:03.73#ibcon#read 5, iclass 14, count 0 2006.173.05:29:03.73#ibcon#about to read 6, iclass 14, count 0 2006.173.05:29:03.73#ibcon#read 6, iclass 14, count 0 2006.173.05:29:03.73#ibcon#end of sib2, iclass 14, count 0 2006.173.05:29:03.73#ibcon#*mode == 0, iclass 14, count 0 2006.173.05:29:03.73#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.05:29:03.73#ibcon#[25=BW32\r\n] 2006.173.05:29:03.73#ibcon#*before write, iclass 14, count 0 2006.173.05:29:03.73#ibcon#enter sib2, iclass 14, count 0 2006.173.05:29:03.73#ibcon#flushed, iclass 14, count 0 2006.173.05:29:03.73#ibcon#about to write, iclass 14, count 0 2006.173.05:29:03.73#ibcon#wrote, iclass 14, count 0 2006.173.05:29:03.73#ibcon#about to read 3, iclass 14, count 0 2006.173.05:29:03.76#ibcon#read 3, iclass 14, count 0 2006.173.05:29:03.76#ibcon#about to read 4, iclass 14, count 0 2006.173.05:29:03.76#ibcon#read 4, iclass 14, count 0 2006.173.05:29:03.76#ibcon#about to read 5, iclass 14, count 0 2006.173.05:29:03.76#ibcon#read 5, iclass 14, count 0 2006.173.05:29:03.76#ibcon#about to read 6, iclass 14, count 0 2006.173.05:29:03.76#ibcon#read 6, iclass 14, count 0 2006.173.05:29:03.76#ibcon#end of sib2, iclass 14, count 0 2006.173.05:29:03.76#ibcon#*after write, iclass 14, count 0 2006.173.05:29:03.76#ibcon#*before return 0, iclass 14, count 0 2006.173.05:29:03.76#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.05:29:03.76#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.05:29:03.76#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.05:29:03.76#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.05:29:03.76$vck44/vbbw=wide 2006.173.05:29:03.76#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.05:29:03.76#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.05:29:03.76#ibcon#ireg 8 cls_cnt 0 2006.173.05:29:03.76#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.05:29:03.83#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.05:29:03.83#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.05:29:03.83#ibcon#enter wrdev, iclass 16, count 0 2006.173.05:29:03.83#ibcon#first serial, iclass 16, count 0 2006.173.05:29:03.83#ibcon#enter sib2, iclass 16, count 0 2006.173.05:29:03.83#ibcon#flushed, iclass 16, count 0 2006.173.05:29:03.83#ibcon#about to write, iclass 16, count 0 2006.173.05:29:03.83#ibcon#wrote, iclass 16, count 0 2006.173.05:29:03.83#ibcon#about to read 3, iclass 16, count 0 2006.173.05:29:03.85#ibcon#read 3, iclass 16, count 0 2006.173.05:29:03.85#ibcon#about to read 4, iclass 16, count 0 2006.173.05:29:03.85#ibcon#read 4, iclass 16, count 0 2006.173.05:29:03.85#ibcon#about to read 5, iclass 16, count 0 2006.173.05:29:03.85#ibcon#read 5, iclass 16, count 0 2006.173.05:29:03.85#ibcon#about to read 6, iclass 16, count 0 2006.173.05:29:03.85#ibcon#read 6, iclass 16, count 0 2006.173.05:29:03.85#ibcon#end of sib2, iclass 16, count 0 2006.173.05:29:03.85#ibcon#*mode == 0, iclass 16, count 0 2006.173.05:29:03.85#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.05:29:03.85#ibcon#[27=BW32\r\n] 2006.173.05:29:03.85#ibcon#*before write, iclass 16, count 0 2006.173.05:29:03.85#ibcon#enter sib2, iclass 16, count 0 2006.173.05:29:03.85#ibcon#flushed, iclass 16, count 0 2006.173.05:29:03.85#ibcon#about to write, iclass 16, count 0 2006.173.05:29:03.85#ibcon#wrote, iclass 16, count 0 2006.173.05:29:03.85#ibcon#about to read 3, iclass 16, count 0 2006.173.05:29:03.88#ibcon#read 3, iclass 16, count 0 2006.173.05:29:03.88#ibcon#about to read 4, iclass 16, count 0 2006.173.05:29:03.88#ibcon#read 4, iclass 16, count 0 2006.173.05:29:03.88#ibcon#about to read 5, iclass 16, count 0 2006.173.05:29:03.88#ibcon#read 5, iclass 16, count 0 2006.173.05:29:03.88#ibcon#about to read 6, iclass 16, count 0 2006.173.05:29:03.88#ibcon#read 6, iclass 16, count 0 2006.173.05:29:03.88#ibcon#end of sib2, iclass 16, count 0 2006.173.05:29:03.88#ibcon#*after write, iclass 16, count 0 2006.173.05:29:03.88#ibcon#*before return 0, iclass 16, count 0 2006.173.05:29:03.88#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.05:29:03.88#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.05:29:03.88#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.05:29:03.88#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.05:29:03.88$setupk4/ifdk4 2006.173.05:29:03.88$ifdk4/lo= 2006.173.05:29:03.88$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.05:29:03.88$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.05:29:03.88$ifdk4/patch= 2006.173.05:29:03.88$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.05:29:03.88$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.05:29:03.88$setupk4/!*+20s 2006.173.05:29:13.10#abcon#<5=/15 0.7 1.5 23.51 771005.4\r\n> 2006.173.05:29:13.12#abcon#{5=INTERFACE CLEAR} 2006.173.05:29:13.18#abcon#[5=S1D000X0/0*\r\n] 2006.173.05:29:18.25$setupk4/"tpicd 2006.173.05:29:18.25$setupk4/echo=off 2006.173.05:29:18.25$setupk4/xlog=off 2006.173.05:29:18.25:!2006.173.05:33:34 2006.173.05:29:24.14#trakl#Source acquired 2006.173.05:29:26.14#flagr#flagr/antenna,acquired 2006.173.05:33:34.00:preob 2006.173.05:33:34.14/onsource/TRACKING 2006.173.05:33:34.14:!2006.173.05:33:44 2006.173.05:33:44.00:"tape 2006.173.05:33:44.00:"st=record 2006.173.05:33:44.00:data_valid=on 2006.173.05:33:44.00:midob 2006.173.05:33:44.14/onsource/TRACKING 2006.173.05:33:44.14/wx/23.49,1005.3,78 2006.173.05:33:44.28/cable/+6.5056E-03 2006.173.05:33:45.37/va/01,07,usb,yes,35,38 2006.173.05:33:45.37/va/02,06,usb,yes,35,36 2006.173.05:33:45.37/va/03,05,usb,yes,44,46 2006.173.05:33:45.37/va/04,06,usb,yes,35,37 2006.173.05:33:45.37/va/05,04,usb,yes,28,28 2006.173.05:33:45.37/va/06,03,usb,yes,39,39 2006.173.05:33:45.37/va/07,04,usb,yes,32,33 2006.173.05:33:45.37/va/08,04,usb,yes,27,32 2006.173.05:33:45.60/valo/01,524.99,yes,locked 2006.173.05:33:45.60/valo/02,534.99,yes,locked 2006.173.05:33:45.60/valo/03,564.99,yes,locked 2006.173.05:33:45.60/valo/04,624.99,yes,locked 2006.173.05:33:45.60/valo/05,734.99,yes,locked 2006.173.05:33:45.60/valo/06,814.99,yes,locked 2006.173.05:33:45.60/valo/07,864.99,yes,locked 2006.173.05:33:45.60/valo/08,884.99,yes,locked 2006.173.05:33:46.69/vb/01,04,usb,yes,29,27 2006.173.05:33:46.69/vb/02,04,usb,yes,31,31 2006.173.05:33:46.69/vb/03,04,usb,yes,28,31 2006.173.05:33:46.69/vb/04,04,usb,yes,32,31 2006.173.05:33:46.69/vb/05,04,usb,yes,25,27 2006.173.05:33:46.69/vb/06,04,usb,yes,29,26 2006.173.05:33:46.69/vb/07,04,usb,yes,29,29 2006.173.05:33:46.69/vb/08,04,usb,yes,27,30 2006.173.05:33:46.93/vblo/01,629.99,yes,locked 2006.173.05:33:46.93/vblo/02,634.99,yes,locked 2006.173.05:33:46.93/vblo/03,649.99,yes,locked 2006.173.05:33:46.93/vblo/04,679.99,yes,locked 2006.173.05:33:46.93/vblo/05,709.99,yes,locked 2006.173.05:33:46.93/vblo/06,719.99,yes,locked 2006.173.05:33:46.93/vblo/07,734.99,yes,locked 2006.173.05:33:46.93/vblo/08,744.99,yes,locked 2006.173.05:33:47.08/vabw/8 2006.173.05:33:47.23/vbbw/8 2006.173.05:33:47.32/xfe/off,on,14.5 2006.173.05:33:47.69/ifatt/23,28,28,28 2006.173.05:33:48.08/fmout-gps/S +3.97E-07 2006.173.05:33:48.12:!2006.173.05:41:44 2006.173.05:41:44.00:data_valid=off 2006.173.05:41:44.00:"et 2006.173.05:41:44.00:!+3s 2006.173.05:41:47.01:"tape 2006.173.05:41:47.01:postob 2006.173.05:41:47.21/cable/+6.5049E-03 2006.173.05:41:47.21/wx/23.51,1005.3,78 2006.173.05:41:48.07/fmout-gps/S +4.00E-07 2006.173.05:41:48.07:scan_name=173-0547,jd0606,50 2006.173.05:41:48.07:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.173.05:41:48.14#flagr#flagr/antenna,new-source 2006.173.05:41:49.14:checkk5 2006.173.05:41:49.54/chk_autoobs//k5ts1/ autoobs is running! 2006.173.05:41:49.94/chk_autoobs//k5ts2/ autoobs is running! 2006.173.05:41:50.34/chk_autoobs//k5ts3/ autoobs is running! 2006.173.05:41:50.73/chk_autoobs//k5ts4/ autoobs is running! 2006.173.05:41:51.13/chk_obsdata//k5ts1/T1730533??a.dat file size is correct (nominal:1920MB, actual:1916MB). 2006.173.05:41:51.53/chk_obsdata//k5ts2/T1730533??b.dat file size is correct (nominal:1920MB, actual:1916MB). 2006.173.05:41:51.92/chk_obsdata//k5ts3/T1730533??c.dat file size is correct (nominal:1920MB, actual:1916MB). 2006.173.05:41:52.32/chk_obsdata//k5ts4/T1730533??d.dat file size is correct (nominal:1920MB, actual:1916MB). 2006.173.05:41:53.03/k5log//k5ts1_log_newline 2006.173.05:41:53.75/k5log//k5ts2_log_newline 2006.173.05:41:54.46/k5log//k5ts3_log_newline 2006.173.05:41:55.16/k5log//k5ts4_log_newline 2006.173.05:41:55.19/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.05:41:55.19:setupk4=1 2006.173.05:41:55.19$setupk4/echo=on 2006.173.05:41:55.19$setupk4/pcalon 2006.173.05:41:55.19$pcalon/"no phase cal control is implemented here 2006.173.05:41:55.19$setupk4/"tpicd=stop 2006.173.05:41:55.19$setupk4/"rec=synch_on 2006.173.05:41:55.19$setupk4/"rec_mode=128 2006.173.05:41:55.19$setupk4/!* 2006.173.05:41:55.19$setupk4/recpk4 2006.173.05:41:55.19$recpk4/recpatch= 2006.173.05:41:55.19$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.05:41:55.19$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.05:41:55.19$setupk4/vck44 2006.173.05:41:55.19$vck44/valo=1,524.99 2006.173.05:41:55.19#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.05:41:55.19#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.05:41:55.19#ibcon#ireg 17 cls_cnt 0 2006.173.05:41:55.19#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.05:41:55.19#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.05:41:55.19#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.05:41:55.19#ibcon#enter wrdev, iclass 33, count 0 2006.173.05:41:55.19#ibcon#first serial, iclass 33, count 0 2006.173.05:41:55.19#ibcon#enter sib2, iclass 33, count 0 2006.173.05:41:55.19#ibcon#flushed, iclass 33, count 0 2006.173.05:41:55.19#ibcon#about to write, iclass 33, count 0 2006.173.05:41:55.19#ibcon#wrote, iclass 33, count 0 2006.173.05:41:55.19#ibcon#about to read 3, iclass 33, count 0 2006.173.05:41:55.21#ibcon#read 3, iclass 33, count 0 2006.173.05:41:55.21#ibcon#about to read 4, iclass 33, count 0 2006.173.05:41:55.21#ibcon#read 4, iclass 33, count 0 2006.173.05:41:55.21#ibcon#about to read 5, iclass 33, count 0 2006.173.05:41:55.21#ibcon#read 5, iclass 33, count 0 2006.173.05:41:55.21#ibcon#about to read 6, iclass 33, count 0 2006.173.05:41:55.21#ibcon#read 6, iclass 33, count 0 2006.173.05:41:55.21#ibcon#end of sib2, iclass 33, count 0 2006.173.05:41:55.21#ibcon#*mode == 0, iclass 33, count 0 2006.173.05:41:55.21#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.05:41:55.21#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.05:41:55.21#ibcon#*before write, iclass 33, count 0 2006.173.05:41:55.21#ibcon#enter sib2, iclass 33, count 0 2006.173.05:41:55.21#ibcon#flushed, iclass 33, count 0 2006.173.05:41:55.21#ibcon#about to write, iclass 33, count 0 2006.173.05:41:55.21#ibcon#wrote, iclass 33, count 0 2006.173.05:41:55.21#ibcon#about to read 3, iclass 33, count 0 2006.173.05:41:55.26#ibcon#read 3, iclass 33, count 0 2006.173.05:41:55.26#ibcon#about to read 4, iclass 33, count 0 2006.173.05:41:55.26#ibcon#read 4, iclass 33, count 0 2006.173.05:41:55.26#ibcon#about to read 5, iclass 33, count 0 2006.173.05:41:55.26#ibcon#read 5, iclass 33, count 0 2006.173.05:41:55.26#ibcon#about to read 6, iclass 33, count 0 2006.173.05:41:55.26#ibcon#read 6, iclass 33, count 0 2006.173.05:41:55.26#ibcon#end of sib2, iclass 33, count 0 2006.173.05:41:55.26#ibcon#*after write, iclass 33, count 0 2006.173.05:41:55.26#ibcon#*before return 0, iclass 33, count 0 2006.173.05:41:55.26#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.05:41:55.26#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.05:41:55.26#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.05:41:55.26#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.05:41:55.26$vck44/va=1,7 2006.173.05:41:55.26#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.05:41:55.26#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.05:41:55.26#ibcon#ireg 11 cls_cnt 2 2006.173.05:41:55.26#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.05:41:55.26#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.05:41:55.26#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.05:41:55.26#ibcon#enter wrdev, iclass 35, count 2 2006.173.05:41:55.26#ibcon#first serial, iclass 35, count 2 2006.173.05:41:55.26#ibcon#enter sib2, iclass 35, count 2 2006.173.05:41:55.26#ibcon#flushed, iclass 35, count 2 2006.173.05:41:55.26#ibcon#about to write, iclass 35, count 2 2006.173.05:41:55.26#ibcon#wrote, iclass 35, count 2 2006.173.05:41:55.26#ibcon#about to read 3, iclass 35, count 2 2006.173.05:41:55.28#ibcon#read 3, iclass 35, count 2 2006.173.05:41:55.28#ibcon#about to read 4, iclass 35, count 2 2006.173.05:41:55.28#ibcon#read 4, iclass 35, count 2 2006.173.05:41:55.28#ibcon#about to read 5, iclass 35, count 2 2006.173.05:41:55.28#ibcon#read 5, iclass 35, count 2 2006.173.05:41:55.28#ibcon#about to read 6, iclass 35, count 2 2006.173.05:41:55.28#ibcon#read 6, iclass 35, count 2 2006.173.05:41:55.28#ibcon#end of sib2, iclass 35, count 2 2006.173.05:41:55.28#ibcon#*mode == 0, iclass 35, count 2 2006.173.05:41:55.28#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.05:41:55.28#ibcon#[25=AT01-07\r\n] 2006.173.05:41:55.28#ibcon#*before write, iclass 35, count 2 2006.173.05:41:55.28#ibcon#enter sib2, iclass 35, count 2 2006.173.05:41:55.28#ibcon#flushed, iclass 35, count 2 2006.173.05:41:55.28#ibcon#about to write, iclass 35, count 2 2006.173.05:41:55.28#ibcon#wrote, iclass 35, count 2 2006.173.05:41:55.28#ibcon#about to read 3, iclass 35, count 2 2006.173.05:41:55.31#ibcon#read 3, iclass 35, count 2 2006.173.05:41:55.31#ibcon#about to read 4, iclass 35, count 2 2006.173.05:41:55.31#ibcon#read 4, iclass 35, count 2 2006.173.05:41:55.31#ibcon#about to read 5, iclass 35, count 2 2006.173.05:41:55.31#ibcon#read 5, iclass 35, count 2 2006.173.05:41:55.31#ibcon#about to read 6, iclass 35, count 2 2006.173.05:41:55.31#ibcon#read 6, iclass 35, count 2 2006.173.05:41:55.31#ibcon#end of sib2, iclass 35, count 2 2006.173.05:41:55.31#ibcon#*after write, iclass 35, count 2 2006.173.05:41:55.31#ibcon#*before return 0, iclass 35, count 2 2006.173.05:41:55.31#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.05:41:55.31#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.05:41:55.31#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.05:41:55.31#ibcon#ireg 7 cls_cnt 0 2006.173.05:41:55.31#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.05:41:55.43#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.05:41:55.43#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.05:41:55.43#ibcon#enter wrdev, iclass 35, count 0 2006.173.05:41:55.43#ibcon#first serial, iclass 35, count 0 2006.173.05:41:55.43#ibcon#enter sib2, iclass 35, count 0 2006.173.05:41:55.43#ibcon#flushed, iclass 35, count 0 2006.173.05:41:55.43#ibcon#about to write, iclass 35, count 0 2006.173.05:41:55.43#ibcon#wrote, iclass 35, count 0 2006.173.05:41:55.43#ibcon#about to read 3, iclass 35, count 0 2006.173.05:41:55.45#ibcon#read 3, iclass 35, count 0 2006.173.05:41:55.45#ibcon#about to read 4, iclass 35, count 0 2006.173.05:41:55.45#ibcon#read 4, iclass 35, count 0 2006.173.05:41:55.45#ibcon#about to read 5, iclass 35, count 0 2006.173.05:41:55.45#ibcon#read 5, iclass 35, count 0 2006.173.05:41:55.45#ibcon#about to read 6, iclass 35, count 0 2006.173.05:41:55.45#ibcon#read 6, iclass 35, count 0 2006.173.05:41:55.45#ibcon#end of sib2, iclass 35, count 0 2006.173.05:41:55.45#ibcon#*mode == 0, iclass 35, count 0 2006.173.05:41:55.45#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.05:41:55.45#ibcon#[25=USB\r\n] 2006.173.05:41:55.45#ibcon#*before write, iclass 35, count 0 2006.173.05:41:55.45#ibcon#enter sib2, iclass 35, count 0 2006.173.05:41:55.45#ibcon#flushed, iclass 35, count 0 2006.173.05:41:55.45#ibcon#about to write, iclass 35, count 0 2006.173.05:41:55.45#ibcon#wrote, iclass 35, count 0 2006.173.05:41:55.45#ibcon#about to read 3, iclass 35, count 0 2006.173.05:41:55.48#ibcon#read 3, iclass 35, count 0 2006.173.05:41:55.48#ibcon#about to read 4, iclass 35, count 0 2006.173.05:41:55.48#ibcon#read 4, iclass 35, count 0 2006.173.05:41:55.48#ibcon#about to read 5, iclass 35, count 0 2006.173.05:41:55.48#ibcon#read 5, iclass 35, count 0 2006.173.05:41:55.48#ibcon#about to read 6, iclass 35, count 0 2006.173.05:41:55.48#ibcon#read 6, iclass 35, count 0 2006.173.05:41:55.48#ibcon#end of sib2, iclass 35, count 0 2006.173.05:41:55.48#ibcon#*after write, iclass 35, count 0 2006.173.05:41:55.48#ibcon#*before return 0, iclass 35, count 0 2006.173.05:41:55.48#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.05:41:55.48#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.05:41:55.48#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.05:41:55.48#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.05:41:55.48$vck44/valo=2,534.99 2006.173.05:41:55.48#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.05:41:55.48#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.05:41:55.48#ibcon#ireg 17 cls_cnt 0 2006.173.05:41:55.48#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.05:41:55.48#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.05:41:55.48#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.05:41:55.48#ibcon#enter wrdev, iclass 37, count 0 2006.173.05:41:55.48#ibcon#first serial, iclass 37, count 0 2006.173.05:41:55.48#ibcon#enter sib2, iclass 37, count 0 2006.173.05:41:55.48#ibcon#flushed, iclass 37, count 0 2006.173.05:41:55.48#ibcon#about to write, iclass 37, count 0 2006.173.05:41:55.48#ibcon#wrote, iclass 37, count 0 2006.173.05:41:55.48#ibcon#about to read 3, iclass 37, count 0 2006.173.05:41:55.50#ibcon#read 3, iclass 37, count 0 2006.173.05:41:55.50#ibcon#about to read 4, iclass 37, count 0 2006.173.05:41:55.50#ibcon#read 4, iclass 37, count 0 2006.173.05:41:55.50#ibcon#about to read 5, iclass 37, count 0 2006.173.05:41:55.50#ibcon#read 5, iclass 37, count 0 2006.173.05:41:55.50#ibcon#about to read 6, iclass 37, count 0 2006.173.05:41:55.50#ibcon#read 6, iclass 37, count 0 2006.173.05:41:55.50#ibcon#end of sib2, iclass 37, count 0 2006.173.05:41:55.50#ibcon#*mode == 0, iclass 37, count 0 2006.173.05:41:55.50#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.05:41:55.50#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.05:41:55.50#ibcon#*before write, iclass 37, count 0 2006.173.05:41:55.50#ibcon#enter sib2, iclass 37, count 0 2006.173.05:41:55.50#ibcon#flushed, iclass 37, count 0 2006.173.05:41:55.50#ibcon#about to write, iclass 37, count 0 2006.173.05:41:55.50#ibcon#wrote, iclass 37, count 0 2006.173.05:41:55.50#ibcon#about to read 3, iclass 37, count 0 2006.173.05:41:55.54#ibcon#read 3, iclass 37, count 0 2006.173.05:41:55.54#ibcon#about to read 4, iclass 37, count 0 2006.173.05:41:55.54#ibcon#read 4, iclass 37, count 0 2006.173.05:41:55.54#ibcon#about to read 5, iclass 37, count 0 2006.173.05:41:55.54#ibcon#read 5, iclass 37, count 0 2006.173.05:41:55.54#ibcon#about to read 6, iclass 37, count 0 2006.173.05:41:55.54#ibcon#read 6, iclass 37, count 0 2006.173.05:41:55.54#ibcon#end of sib2, iclass 37, count 0 2006.173.05:41:55.54#ibcon#*after write, iclass 37, count 0 2006.173.05:41:55.54#ibcon#*before return 0, iclass 37, count 0 2006.173.05:41:55.54#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.05:41:55.54#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.05:41:55.54#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.05:41:55.54#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.05:41:55.54$vck44/va=2,6 2006.173.05:41:55.54#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.05:41:55.54#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.05:41:55.54#ibcon#ireg 11 cls_cnt 2 2006.173.05:41:55.54#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.05:41:55.60#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.05:41:55.60#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.05:41:55.60#ibcon#enter wrdev, iclass 39, count 2 2006.173.05:41:55.60#ibcon#first serial, iclass 39, count 2 2006.173.05:41:55.60#ibcon#enter sib2, iclass 39, count 2 2006.173.05:41:55.60#ibcon#flushed, iclass 39, count 2 2006.173.05:41:55.60#ibcon#about to write, iclass 39, count 2 2006.173.05:41:55.60#ibcon#wrote, iclass 39, count 2 2006.173.05:41:55.60#ibcon#about to read 3, iclass 39, count 2 2006.173.05:41:55.62#ibcon#read 3, iclass 39, count 2 2006.173.05:41:55.62#ibcon#about to read 4, iclass 39, count 2 2006.173.05:41:55.62#ibcon#read 4, iclass 39, count 2 2006.173.05:41:55.62#ibcon#about to read 5, iclass 39, count 2 2006.173.05:41:55.62#ibcon#read 5, iclass 39, count 2 2006.173.05:41:55.62#ibcon#about to read 6, iclass 39, count 2 2006.173.05:41:55.62#ibcon#read 6, iclass 39, count 2 2006.173.05:41:55.62#ibcon#end of sib2, iclass 39, count 2 2006.173.05:41:55.62#ibcon#*mode == 0, iclass 39, count 2 2006.173.05:41:55.62#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.05:41:55.62#ibcon#[25=AT02-06\r\n] 2006.173.05:41:55.62#ibcon#*before write, iclass 39, count 2 2006.173.05:41:55.62#ibcon#enter sib2, iclass 39, count 2 2006.173.05:41:55.62#ibcon#flushed, iclass 39, count 2 2006.173.05:41:55.62#ibcon#about to write, iclass 39, count 2 2006.173.05:41:55.62#ibcon#wrote, iclass 39, count 2 2006.173.05:41:55.62#ibcon#about to read 3, iclass 39, count 2 2006.173.05:41:55.65#ibcon#read 3, iclass 39, count 2 2006.173.05:41:55.65#ibcon#about to read 4, iclass 39, count 2 2006.173.05:41:55.65#ibcon#read 4, iclass 39, count 2 2006.173.05:41:55.65#ibcon#about to read 5, iclass 39, count 2 2006.173.05:41:55.65#ibcon#read 5, iclass 39, count 2 2006.173.05:41:55.65#ibcon#about to read 6, iclass 39, count 2 2006.173.05:41:55.65#ibcon#read 6, iclass 39, count 2 2006.173.05:41:55.65#ibcon#end of sib2, iclass 39, count 2 2006.173.05:41:55.65#ibcon#*after write, iclass 39, count 2 2006.173.05:41:55.65#ibcon#*before return 0, iclass 39, count 2 2006.173.05:41:55.65#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.05:41:55.65#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.05:41:55.65#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.05:41:55.65#ibcon#ireg 7 cls_cnt 0 2006.173.05:41:55.65#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.05:41:55.77#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.05:41:55.77#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.05:41:55.77#ibcon#enter wrdev, iclass 39, count 0 2006.173.05:41:55.77#ibcon#first serial, iclass 39, count 0 2006.173.05:41:55.77#ibcon#enter sib2, iclass 39, count 0 2006.173.05:41:55.77#ibcon#flushed, iclass 39, count 0 2006.173.05:41:55.77#ibcon#about to write, iclass 39, count 0 2006.173.05:41:55.77#ibcon#wrote, iclass 39, count 0 2006.173.05:41:55.77#ibcon#about to read 3, iclass 39, count 0 2006.173.05:41:55.79#ibcon#read 3, iclass 39, count 0 2006.173.05:41:55.79#ibcon#about to read 4, iclass 39, count 0 2006.173.05:41:55.79#ibcon#read 4, iclass 39, count 0 2006.173.05:41:55.79#ibcon#about to read 5, iclass 39, count 0 2006.173.05:41:55.79#ibcon#read 5, iclass 39, count 0 2006.173.05:41:55.79#ibcon#about to read 6, iclass 39, count 0 2006.173.05:41:55.79#ibcon#read 6, iclass 39, count 0 2006.173.05:41:55.79#ibcon#end of sib2, iclass 39, count 0 2006.173.05:41:55.79#ibcon#*mode == 0, iclass 39, count 0 2006.173.05:41:55.79#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.05:41:55.79#ibcon#[25=USB\r\n] 2006.173.05:41:55.79#ibcon#*before write, iclass 39, count 0 2006.173.05:41:55.79#ibcon#enter sib2, iclass 39, count 0 2006.173.05:41:55.79#ibcon#flushed, iclass 39, count 0 2006.173.05:41:55.79#ibcon#about to write, iclass 39, count 0 2006.173.05:41:55.79#ibcon#wrote, iclass 39, count 0 2006.173.05:41:55.79#ibcon#about to read 3, iclass 39, count 0 2006.173.05:41:55.82#ibcon#read 3, iclass 39, count 0 2006.173.05:41:55.82#ibcon#about to read 4, iclass 39, count 0 2006.173.05:41:55.82#ibcon#read 4, iclass 39, count 0 2006.173.05:41:55.82#ibcon#about to read 5, iclass 39, count 0 2006.173.05:41:55.82#ibcon#read 5, iclass 39, count 0 2006.173.05:41:55.82#ibcon#about to read 6, iclass 39, count 0 2006.173.05:41:55.82#ibcon#read 6, iclass 39, count 0 2006.173.05:41:55.82#ibcon#end of sib2, iclass 39, count 0 2006.173.05:41:55.82#ibcon#*after write, iclass 39, count 0 2006.173.05:41:55.82#ibcon#*before return 0, iclass 39, count 0 2006.173.05:41:55.82#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.05:41:55.82#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.05:41:55.82#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.05:41:55.82#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.05:41:55.82$vck44/valo=3,564.99 2006.173.05:41:55.82#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.05:41:55.82#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.05:41:55.82#ibcon#ireg 17 cls_cnt 0 2006.173.05:41:55.82#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.05:41:55.82#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.05:41:55.82#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.05:41:55.82#ibcon#enter wrdev, iclass 3, count 0 2006.173.05:41:55.82#ibcon#first serial, iclass 3, count 0 2006.173.05:41:55.82#ibcon#enter sib2, iclass 3, count 0 2006.173.05:41:55.82#ibcon#flushed, iclass 3, count 0 2006.173.05:41:55.82#ibcon#about to write, iclass 3, count 0 2006.173.05:41:55.82#ibcon#wrote, iclass 3, count 0 2006.173.05:41:55.82#ibcon#about to read 3, iclass 3, count 0 2006.173.05:41:55.84#ibcon#read 3, iclass 3, count 0 2006.173.05:41:55.84#ibcon#about to read 4, iclass 3, count 0 2006.173.05:41:55.84#ibcon#read 4, iclass 3, count 0 2006.173.05:41:55.84#ibcon#about to read 5, iclass 3, count 0 2006.173.05:41:55.84#ibcon#read 5, iclass 3, count 0 2006.173.05:41:55.84#ibcon#about to read 6, iclass 3, count 0 2006.173.05:41:55.84#ibcon#read 6, iclass 3, count 0 2006.173.05:41:55.84#ibcon#end of sib2, iclass 3, count 0 2006.173.05:41:55.84#ibcon#*mode == 0, iclass 3, count 0 2006.173.05:41:55.84#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.05:41:55.84#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.05:41:55.84#ibcon#*before write, iclass 3, count 0 2006.173.05:41:55.84#ibcon#enter sib2, iclass 3, count 0 2006.173.05:41:55.84#ibcon#flushed, iclass 3, count 0 2006.173.05:41:55.84#ibcon#about to write, iclass 3, count 0 2006.173.05:41:55.84#ibcon#wrote, iclass 3, count 0 2006.173.05:41:55.84#ibcon#about to read 3, iclass 3, count 0 2006.173.05:41:55.88#ibcon#read 3, iclass 3, count 0 2006.173.05:41:55.88#ibcon#about to read 4, iclass 3, count 0 2006.173.05:41:55.88#ibcon#read 4, iclass 3, count 0 2006.173.05:41:55.88#ibcon#about to read 5, iclass 3, count 0 2006.173.05:41:55.88#ibcon#read 5, iclass 3, count 0 2006.173.05:41:55.88#ibcon#about to read 6, iclass 3, count 0 2006.173.05:41:55.88#ibcon#read 6, iclass 3, count 0 2006.173.05:41:55.88#ibcon#end of sib2, iclass 3, count 0 2006.173.05:41:55.88#ibcon#*after write, iclass 3, count 0 2006.173.05:41:55.88#ibcon#*before return 0, iclass 3, count 0 2006.173.05:41:55.88#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.05:41:55.88#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.05:41:55.88#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.05:41:55.88#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.05:41:55.88$vck44/va=3,5 2006.173.05:41:55.88#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.05:41:55.88#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.05:41:55.88#ibcon#ireg 11 cls_cnt 2 2006.173.05:41:55.88#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.05:41:55.94#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.05:41:55.94#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.05:41:55.94#ibcon#enter wrdev, iclass 5, count 2 2006.173.05:41:55.94#ibcon#first serial, iclass 5, count 2 2006.173.05:41:55.94#ibcon#enter sib2, iclass 5, count 2 2006.173.05:41:55.94#ibcon#flushed, iclass 5, count 2 2006.173.05:41:55.94#ibcon#about to write, iclass 5, count 2 2006.173.05:41:55.94#ibcon#wrote, iclass 5, count 2 2006.173.05:41:55.94#ibcon#about to read 3, iclass 5, count 2 2006.173.05:41:55.96#ibcon#read 3, iclass 5, count 2 2006.173.05:41:55.96#ibcon#about to read 4, iclass 5, count 2 2006.173.05:41:55.96#ibcon#read 4, iclass 5, count 2 2006.173.05:41:55.96#ibcon#about to read 5, iclass 5, count 2 2006.173.05:41:55.96#ibcon#read 5, iclass 5, count 2 2006.173.05:41:55.96#ibcon#about to read 6, iclass 5, count 2 2006.173.05:41:55.96#ibcon#read 6, iclass 5, count 2 2006.173.05:41:55.96#ibcon#end of sib2, iclass 5, count 2 2006.173.05:41:55.96#ibcon#*mode == 0, iclass 5, count 2 2006.173.05:41:55.96#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.05:41:55.96#ibcon#[25=AT03-05\r\n] 2006.173.05:41:55.96#ibcon#*before write, iclass 5, count 2 2006.173.05:41:55.96#ibcon#enter sib2, iclass 5, count 2 2006.173.05:41:55.96#ibcon#flushed, iclass 5, count 2 2006.173.05:41:55.96#ibcon#about to write, iclass 5, count 2 2006.173.05:41:55.96#ibcon#wrote, iclass 5, count 2 2006.173.05:41:55.96#ibcon#about to read 3, iclass 5, count 2 2006.173.05:41:55.99#ibcon#read 3, iclass 5, count 2 2006.173.05:41:55.99#ibcon#about to read 4, iclass 5, count 2 2006.173.05:41:55.99#ibcon#read 4, iclass 5, count 2 2006.173.05:41:55.99#ibcon#about to read 5, iclass 5, count 2 2006.173.05:41:55.99#ibcon#read 5, iclass 5, count 2 2006.173.05:41:55.99#ibcon#about to read 6, iclass 5, count 2 2006.173.05:41:55.99#ibcon#read 6, iclass 5, count 2 2006.173.05:41:55.99#ibcon#end of sib2, iclass 5, count 2 2006.173.05:41:55.99#ibcon#*after write, iclass 5, count 2 2006.173.05:41:55.99#ibcon#*before return 0, iclass 5, count 2 2006.173.05:41:55.99#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.05:41:55.99#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.05:41:55.99#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.05:41:55.99#ibcon#ireg 7 cls_cnt 0 2006.173.05:41:55.99#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.05:41:56.08#abcon#<5=/15 0.5 1.2 23.51 781005.3\r\n> 2006.173.05:41:56.10#abcon#{5=INTERFACE CLEAR} 2006.173.05:41:56.11#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.05:41:56.11#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.05:41:56.11#ibcon#enter wrdev, iclass 5, count 0 2006.173.05:41:56.11#ibcon#first serial, iclass 5, count 0 2006.173.05:41:56.11#ibcon#enter sib2, iclass 5, count 0 2006.173.05:41:56.11#ibcon#flushed, iclass 5, count 0 2006.173.05:41:56.11#ibcon#about to write, iclass 5, count 0 2006.173.05:41:56.11#ibcon#wrote, iclass 5, count 0 2006.173.05:41:56.11#ibcon#about to read 3, iclass 5, count 0 2006.173.05:41:56.13#ibcon#read 3, iclass 5, count 0 2006.173.05:41:56.13#ibcon#about to read 4, iclass 5, count 0 2006.173.05:41:56.13#ibcon#read 4, iclass 5, count 0 2006.173.05:41:56.13#ibcon#about to read 5, iclass 5, count 0 2006.173.05:41:56.13#ibcon#read 5, iclass 5, count 0 2006.173.05:41:56.13#ibcon#about to read 6, iclass 5, count 0 2006.173.05:41:56.13#ibcon#read 6, iclass 5, count 0 2006.173.05:41:56.13#ibcon#end of sib2, iclass 5, count 0 2006.173.05:41:56.13#ibcon#*mode == 0, iclass 5, count 0 2006.173.05:41:56.13#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.05:41:56.13#ibcon#[25=USB\r\n] 2006.173.05:41:56.13#ibcon#*before write, iclass 5, count 0 2006.173.05:41:56.13#ibcon#enter sib2, iclass 5, count 0 2006.173.05:41:56.13#ibcon#flushed, iclass 5, count 0 2006.173.05:41:56.13#ibcon#about to write, iclass 5, count 0 2006.173.05:41:56.13#ibcon#wrote, iclass 5, count 0 2006.173.05:41:56.13#ibcon#about to read 3, iclass 5, count 0 2006.173.05:41:56.16#abcon#[5=S1D000X0/0*\r\n] 2006.173.05:41:56.16#ibcon#read 3, iclass 5, count 0 2006.173.05:41:56.16#ibcon#about to read 4, iclass 5, count 0 2006.173.05:41:56.16#ibcon#read 4, iclass 5, count 0 2006.173.05:41:56.16#ibcon#about to read 5, iclass 5, count 0 2006.173.05:41:56.16#ibcon#read 5, iclass 5, count 0 2006.173.05:41:56.16#ibcon#about to read 6, iclass 5, count 0 2006.173.05:41:56.16#ibcon#read 6, iclass 5, count 0 2006.173.05:41:56.16#ibcon#end of sib2, iclass 5, count 0 2006.173.05:41:56.16#ibcon#*after write, iclass 5, count 0 2006.173.05:41:56.16#ibcon#*before return 0, iclass 5, count 0 2006.173.05:41:56.16#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.05:41:56.16#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.05:41:56.16#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.05:41:56.16#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.05:41:56.16$vck44/valo=4,624.99 2006.173.05:41:56.16#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.05:41:56.16#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.05:41:56.16#ibcon#ireg 17 cls_cnt 0 2006.173.05:41:56.16#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.05:41:56.16#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.05:41:56.16#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.05:41:56.16#ibcon#enter wrdev, iclass 13, count 0 2006.173.05:41:56.16#ibcon#first serial, iclass 13, count 0 2006.173.05:41:56.16#ibcon#enter sib2, iclass 13, count 0 2006.173.05:41:56.16#ibcon#flushed, iclass 13, count 0 2006.173.05:41:56.16#ibcon#about to write, iclass 13, count 0 2006.173.05:41:56.16#ibcon#wrote, iclass 13, count 0 2006.173.05:41:56.16#ibcon#about to read 3, iclass 13, count 0 2006.173.05:41:56.18#ibcon#read 3, iclass 13, count 0 2006.173.05:41:56.18#ibcon#about to read 4, iclass 13, count 0 2006.173.05:41:56.18#ibcon#read 4, iclass 13, count 0 2006.173.05:41:56.18#ibcon#about to read 5, iclass 13, count 0 2006.173.05:41:56.18#ibcon#read 5, iclass 13, count 0 2006.173.05:41:56.18#ibcon#about to read 6, iclass 13, count 0 2006.173.05:41:56.18#ibcon#read 6, iclass 13, count 0 2006.173.05:41:56.18#ibcon#end of sib2, iclass 13, count 0 2006.173.05:41:56.18#ibcon#*mode == 0, iclass 13, count 0 2006.173.05:41:56.18#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.05:41:56.18#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.05:41:56.18#ibcon#*before write, iclass 13, count 0 2006.173.05:41:56.18#ibcon#enter sib2, iclass 13, count 0 2006.173.05:41:56.18#ibcon#flushed, iclass 13, count 0 2006.173.05:41:56.18#ibcon#about to write, iclass 13, count 0 2006.173.05:41:56.18#ibcon#wrote, iclass 13, count 0 2006.173.05:41:56.18#ibcon#about to read 3, iclass 13, count 0 2006.173.05:41:56.22#ibcon#read 3, iclass 13, count 0 2006.173.05:41:56.22#ibcon#about to read 4, iclass 13, count 0 2006.173.05:41:56.22#ibcon#read 4, iclass 13, count 0 2006.173.05:41:56.22#ibcon#about to read 5, iclass 13, count 0 2006.173.05:41:56.22#ibcon#read 5, iclass 13, count 0 2006.173.05:41:56.22#ibcon#about to read 6, iclass 13, count 0 2006.173.05:41:56.22#ibcon#read 6, iclass 13, count 0 2006.173.05:41:56.22#ibcon#end of sib2, iclass 13, count 0 2006.173.05:41:56.22#ibcon#*after write, iclass 13, count 0 2006.173.05:41:56.22#ibcon#*before return 0, iclass 13, count 0 2006.173.05:41:56.22#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.05:41:56.22#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.05:41:56.22#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.05:41:56.22#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.05:41:56.22$vck44/va=4,6 2006.173.05:41:56.22#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.05:41:56.22#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.05:41:56.22#ibcon#ireg 11 cls_cnt 2 2006.173.05:41:56.22#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.05:41:56.28#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.05:41:56.28#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.05:41:56.28#ibcon#enter wrdev, iclass 15, count 2 2006.173.05:41:56.28#ibcon#first serial, iclass 15, count 2 2006.173.05:41:56.28#ibcon#enter sib2, iclass 15, count 2 2006.173.05:41:56.28#ibcon#flushed, iclass 15, count 2 2006.173.05:41:56.28#ibcon#about to write, iclass 15, count 2 2006.173.05:41:56.28#ibcon#wrote, iclass 15, count 2 2006.173.05:41:56.28#ibcon#about to read 3, iclass 15, count 2 2006.173.05:41:56.30#ibcon#read 3, iclass 15, count 2 2006.173.05:41:56.30#ibcon#about to read 4, iclass 15, count 2 2006.173.05:41:56.30#ibcon#read 4, iclass 15, count 2 2006.173.05:41:56.30#ibcon#about to read 5, iclass 15, count 2 2006.173.05:41:56.30#ibcon#read 5, iclass 15, count 2 2006.173.05:41:56.30#ibcon#about to read 6, iclass 15, count 2 2006.173.05:41:56.30#ibcon#read 6, iclass 15, count 2 2006.173.05:41:56.30#ibcon#end of sib2, iclass 15, count 2 2006.173.05:41:56.30#ibcon#*mode == 0, iclass 15, count 2 2006.173.05:41:56.30#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.05:41:56.30#ibcon#[25=AT04-06\r\n] 2006.173.05:41:56.30#ibcon#*before write, iclass 15, count 2 2006.173.05:41:56.30#ibcon#enter sib2, iclass 15, count 2 2006.173.05:41:56.30#ibcon#flushed, iclass 15, count 2 2006.173.05:41:56.30#ibcon#about to write, iclass 15, count 2 2006.173.05:41:56.30#ibcon#wrote, iclass 15, count 2 2006.173.05:41:56.30#ibcon#about to read 3, iclass 15, count 2 2006.173.05:41:56.33#ibcon#read 3, iclass 15, count 2 2006.173.05:41:56.33#ibcon#about to read 4, iclass 15, count 2 2006.173.05:41:56.33#ibcon#read 4, iclass 15, count 2 2006.173.05:41:56.33#ibcon#about to read 5, iclass 15, count 2 2006.173.05:41:56.33#ibcon#read 5, iclass 15, count 2 2006.173.05:41:56.33#ibcon#about to read 6, iclass 15, count 2 2006.173.05:41:56.33#ibcon#read 6, iclass 15, count 2 2006.173.05:41:56.33#ibcon#end of sib2, iclass 15, count 2 2006.173.05:41:56.33#ibcon#*after write, iclass 15, count 2 2006.173.05:41:56.33#ibcon#*before return 0, iclass 15, count 2 2006.173.05:41:56.33#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.05:41:56.33#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.05:41:56.33#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.05:41:56.33#ibcon#ireg 7 cls_cnt 0 2006.173.05:41:56.33#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.05:41:56.45#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.05:41:56.45#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.05:41:56.45#ibcon#enter wrdev, iclass 15, count 0 2006.173.05:41:56.45#ibcon#first serial, iclass 15, count 0 2006.173.05:41:56.45#ibcon#enter sib2, iclass 15, count 0 2006.173.05:41:56.45#ibcon#flushed, iclass 15, count 0 2006.173.05:41:56.45#ibcon#about to write, iclass 15, count 0 2006.173.05:41:56.45#ibcon#wrote, iclass 15, count 0 2006.173.05:41:56.45#ibcon#about to read 3, iclass 15, count 0 2006.173.05:41:56.47#ibcon#read 3, iclass 15, count 0 2006.173.05:41:56.47#ibcon#about to read 4, iclass 15, count 0 2006.173.05:41:56.47#ibcon#read 4, iclass 15, count 0 2006.173.05:41:56.47#ibcon#about to read 5, iclass 15, count 0 2006.173.05:41:56.47#ibcon#read 5, iclass 15, count 0 2006.173.05:41:56.47#ibcon#about to read 6, iclass 15, count 0 2006.173.05:41:56.47#ibcon#read 6, iclass 15, count 0 2006.173.05:41:56.47#ibcon#end of sib2, iclass 15, count 0 2006.173.05:41:56.47#ibcon#*mode == 0, iclass 15, count 0 2006.173.05:41:56.47#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.05:41:56.47#ibcon#[25=USB\r\n] 2006.173.05:41:56.47#ibcon#*before write, iclass 15, count 0 2006.173.05:41:56.47#ibcon#enter sib2, iclass 15, count 0 2006.173.05:41:56.47#ibcon#flushed, iclass 15, count 0 2006.173.05:41:56.47#ibcon#about to write, iclass 15, count 0 2006.173.05:41:56.47#ibcon#wrote, iclass 15, count 0 2006.173.05:41:56.47#ibcon#about to read 3, iclass 15, count 0 2006.173.05:41:56.50#ibcon#read 3, iclass 15, count 0 2006.173.05:41:56.50#ibcon#about to read 4, iclass 15, count 0 2006.173.05:41:56.50#ibcon#read 4, iclass 15, count 0 2006.173.05:41:56.50#ibcon#about to read 5, iclass 15, count 0 2006.173.05:41:56.50#ibcon#read 5, iclass 15, count 0 2006.173.05:41:56.50#ibcon#about to read 6, iclass 15, count 0 2006.173.05:41:56.50#ibcon#read 6, iclass 15, count 0 2006.173.05:41:56.50#ibcon#end of sib2, iclass 15, count 0 2006.173.05:41:56.50#ibcon#*after write, iclass 15, count 0 2006.173.05:41:56.50#ibcon#*before return 0, iclass 15, count 0 2006.173.05:41:56.50#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.05:41:56.50#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.05:41:56.50#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.05:41:56.50#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.05:41:56.50$vck44/valo=5,734.99 2006.173.05:41:56.50#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.05:41:56.50#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.05:41:56.50#ibcon#ireg 17 cls_cnt 0 2006.173.05:41:56.50#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.05:41:56.50#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.05:41:56.50#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.05:41:56.50#ibcon#enter wrdev, iclass 17, count 0 2006.173.05:41:56.50#ibcon#first serial, iclass 17, count 0 2006.173.05:41:56.50#ibcon#enter sib2, iclass 17, count 0 2006.173.05:41:56.50#ibcon#flushed, iclass 17, count 0 2006.173.05:41:56.50#ibcon#about to write, iclass 17, count 0 2006.173.05:41:56.50#ibcon#wrote, iclass 17, count 0 2006.173.05:41:56.50#ibcon#about to read 3, iclass 17, count 0 2006.173.05:41:56.52#ibcon#read 3, iclass 17, count 0 2006.173.05:41:56.52#ibcon#about to read 4, iclass 17, count 0 2006.173.05:41:56.52#ibcon#read 4, iclass 17, count 0 2006.173.05:41:56.52#ibcon#about to read 5, iclass 17, count 0 2006.173.05:41:56.52#ibcon#read 5, iclass 17, count 0 2006.173.05:41:56.52#ibcon#about to read 6, iclass 17, count 0 2006.173.05:41:56.52#ibcon#read 6, iclass 17, count 0 2006.173.05:41:56.52#ibcon#end of sib2, iclass 17, count 0 2006.173.05:41:56.52#ibcon#*mode == 0, iclass 17, count 0 2006.173.05:41:56.52#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.05:41:56.52#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.05:41:56.52#ibcon#*before write, iclass 17, count 0 2006.173.05:41:56.52#ibcon#enter sib2, iclass 17, count 0 2006.173.05:41:56.52#ibcon#flushed, iclass 17, count 0 2006.173.05:41:56.52#ibcon#about to write, iclass 17, count 0 2006.173.05:41:56.52#ibcon#wrote, iclass 17, count 0 2006.173.05:41:56.52#ibcon#about to read 3, iclass 17, count 0 2006.173.05:41:56.56#ibcon#read 3, iclass 17, count 0 2006.173.05:41:56.56#ibcon#about to read 4, iclass 17, count 0 2006.173.05:41:56.56#ibcon#read 4, iclass 17, count 0 2006.173.05:41:56.56#ibcon#about to read 5, iclass 17, count 0 2006.173.05:41:56.56#ibcon#read 5, iclass 17, count 0 2006.173.05:41:56.56#ibcon#about to read 6, iclass 17, count 0 2006.173.05:41:56.56#ibcon#read 6, iclass 17, count 0 2006.173.05:41:56.56#ibcon#end of sib2, iclass 17, count 0 2006.173.05:41:56.56#ibcon#*after write, iclass 17, count 0 2006.173.05:41:56.56#ibcon#*before return 0, iclass 17, count 0 2006.173.05:41:56.56#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.05:41:56.56#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.05:41:56.56#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.05:41:56.56#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.05:41:56.56$vck44/va=5,4 2006.173.05:41:56.56#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.05:41:56.56#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.05:41:56.56#ibcon#ireg 11 cls_cnt 2 2006.173.05:41:56.56#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.05:41:56.62#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.05:41:56.62#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.05:41:56.62#ibcon#enter wrdev, iclass 19, count 2 2006.173.05:41:56.62#ibcon#first serial, iclass 19, count 2 2006.173.05:41:56.62#ibcon#enter sib2, iclass 19, count 2 2006.173.05:41:56.62#ibcon#flushed, iclass 19, count 2 2006.173.05:41:56.62#ibcon#about to write, iclass 19, count 2 2006.173.05:41:56.62#ibcon#wrote, iclass 19, count 2 2006.173.05:41:56.62#ibcon#about to read 3, iclass 19, count 2 2006.173.05:41:56.64#ibcon#read 3, iclass 19, count 2 2006.173.05:41:56.64#ibcon#about to read 4, iclass 19, count 2 2006.173.05:41:56.64#ibcon#read 4, iclass 19, count 2 2006.173.05:41:56.64#ibcon#about to read 5, iclass 19, count 2 2006.173.05:41:56.64#ibcon#read 5, iclass 19, count 2 2006.173.05:41:56.64#ibcon#about to read 6, iclass 19, count 2 2006.173.05:41:56.64#ibcon#read 6, iclass 19, count 2 2006.173.05:41:56.64#ibcon#end of sib2, iclass 19, count 2 2006.173.05:41:56.64#ibcon#*mode == 0, iclass 19, count 2 2006.173.05:41:56.64#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.05:41:56.64#ibcon#[25=AT05-04\r\n] 2006.173.05:41:56.64#ibcon#*before write, iclass 19, count 2 2006.173.05:41:56.64#ibcon#enter sib2, iclass 19, count 2 2006.173.05:41:56.64#ibcon#flushed, iclass 19, count 2 2006.173.05:41:56.64#ibcon#about to write, iclass 19, count 2 2006.173.05:41:56.64#ibcon#wrote, iclass 19, count 2 2006.173.05:41:56.64#ibcon#about to read 3, iclass 19, count 2 2006.173.05:41:56.67#ibcon#read 3, iclass 19, count 2 2006.173.05:41:56.67#ibcon#about to read 4, iclass 19, count 2 2006.173.05:41:56.67#ibcon#read 4, iclass 19, count 2 2006.173.05:41:56.67#ibcon#about to read 5, iclass 19, count 2 2006.173.05:41:56.67#ibcon#read 5, iclass 19, count 2 2006.173.05:41:56.67#ibcon#about to read 6, iclass 19, count 2 2006.173.05:41:56.67#ibcon#read 6, iclass 19, count 2 2006.173.05:41:56.67#ibcon#end of sib2, iclass 19, count 2 2006.173.05:41:56.67#ibcon#*after write, iclass 19, count 2 2006.173.05:41:56.67#ibcon#*before return 0, iclass 19, count 2 2006.173.05:41:56.67#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.05:41:56.67#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.05:41:56.67#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.05:41:56.67#ibcon#ireg 7 cls_cnt 0 2006.173.05:41:56.67#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.05:41:56.79#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.05:41:56.79#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.05:41:56.79#ibcon#enter wrdev, iclass 19, count 0 2006.173.05:41:56.79#ibcon#first serial, iclass 19, count 0 2006.173.05:41:56.79#ibcon#enter sib2, iclass 19, count 0 2006.173.05:41:56.79#ibcon#flushed, iclass 19, count 0 2006.173.05:41:56.79#ibcon#about to write, iclass 19, count 0 2006.173.05:41:56.79#ibcon#wrote, iclass 19, count 0 2006.173.05:41:56.79#ibcon#about to read 3, iclass 19, count 0 2006.173.05:41:56.81#ibcon#read 3, iclass 19, count 0 2006.173.05:41:56.81#ibcon#about to read 4, iclass 19, count 0 2006.173.05:41:56.81#ibcon#read 4, iclass 19, count 0 2006.173.05:41:56.81#ibcon#about to read 5, iclass 19, count 0 2006.173.05:41:56.81#ibcon#read 5, iclass 19, count 0 2006.173.05:41:56.81#ibcon#about to read 6, iclass 19, count 0 2006.173.05:41:56.81#ibcon#read 6, iclass 19, count 0 2006.173.05:41:56.81#ibcon#end of sib2, iclass 19, count 0 2006.173.05:41:56.81#ibcon#*mode == 0, iclass 19, count 0 2006.173.05:41:56.81#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.05:41:56.81#ibcon#[25=USB\r\n] 2006.173.05:41:56.81#ibcon#*before write, iclass 19, count 0 2006.173.05:41:56.81#ibcon#enter sib2, iclass 19, count 0 2006.173.05:41:56.81#ibcon#flushed, iclass 19, count 0 2006.173.05:41:56.81#ibcon#about to write, iclass 19, count 0 2006.173.05:41:56.81#ibcon#wrote, iclass 19, count 0 2006.173.05:41:56.81#ibcon#about to read 3, iclass 19, count 0 2006.173.05:41:56.84#ibcon#read 3, iclass 19, count 0 2006.173.05:41:56.84#ibcon#about to read 4, iclass 19, count 0 2006.173.05:41:56.84#ibcon#read 4, iclass 19, count 0 2006.173.05:41:56.84#ibcon#about to read 5, iclass 19, count 0 2006.173.05:41:56.84#ibcon#read 5, iclass 19, count 0 2006.173.05:41:56.84#ibcon#about to read 6, iclass 19, count 0 2006.173.05:41:56.84#ibcon#read 6, iclass 19, count 0 2006.173.05:41:56.84#ibcon#end of sib2, iclass 19, count 0 2006.173.05:41:56.84#ibcon#*after write, iclass 19, count 0 2006.173.05:41:56.84#ibcon#*before return 0, iclass 19, count 0 2006.173.05:41:56.84#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.05:41:56.84#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.05:41:56.84#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.05:41:56.84#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.05:41:56.84$vck44/valo=6,814.99 2006.173.05:41:56.84#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.05:41:56.84#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.05:41:56.84#ibcon#ireg 17 cls_cnt 0 2006.173.05:41:56.84#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.05:41:56.84#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.05:41:56.84#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.05:41:56.84#ibcon#enter wrdev, iclass 21, count 0 2006.173.05:41:56.84#ibcon#first serial, iclass 21, count 0 2006.173.05:41:56.84#ibcon#enter sib2, iclass 21, count 0 2006.173.05:41:56.84#ibcon#flushed, iclass 21, count 0 2006.173.05:41:56.84#ibcon#about to write, iclass 21, count 0 2006.173.05:41:56.84#ibcon#wrote, iclass 21, count 0 2006.173.05:41:56.84#ibcon#about to read 3, iclass 21, count 0 2006.173.05:41:56.86#ibcon#read 3, iclass 21, count 0 2006.173.05:41:56.86#ibcon#about to read 4, iclass 21, count 0 2006.173.05:41:56.86#ibcon#read 4, iclass 21, count 0 2006.173.05:41:56.86#ibcon#about to read 5, iclass 21, count 0 2006.173.05:41:56.86#ibcon#read 5, iclass 21, count 0 2006.173.05:41:56.86#ibcon#about to read 6, iclass 21, count 0 2006.173.05:41:56.86#ibcon#read 6, iclass 21, count 0 2006.173.05:41:56.86#ibcon#end of sib2, iclass 21, count 0 2006.173.05:41:56.86#ibcon#*mode == 0, iclass 21, count 0 2006.173.05:41:56.86#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.05:41:56.86#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.05:41:56.86#ibcon#*before write, iclass 21, count 0 2006.173.05:41:56.86#ibcon#enter sib2, iclass 21, count 0 2006.173.05:41:56.86#ibcon#flushed, iclass 21, count 0 2006.173.05:41:56.86#ibcon#about to write, iclass 21, count 0 2006.173.05:41:56.86#ibcon#wrote, iclass 21, count 0 2006.173.05:41:56.86#ibcon#about to read 3, iclass 21, count 0 2006.173.05:41:56.90#ibcon#read 3, iclass 21, count 0 2006.173.05:41:56.90#ibcon#about to read 4, iclass 21, count 0 2006.173.05:41:56.90#ibcon#read 4, iclass 21, count 0 2006.173.05:41:56.90#ibcon#about to read 5, iclass 21, count 0 2006.173.05:41:56.90#ibcon#read 5, iclass 21, count 0 2006.173.05:41:56.90#ibcon#about to read 6, iclass 21, count 0 2006.173.05:41:56.90#ibcon#read 6, iclass 21, count 0 2006.173.05:41:56.90#ibcon#end of sib2, iclass 21, count 0 2006.173.05:41:56.90#ibcon#*after write, iclass 21, count 0 2006.173.05:41:56.90#ibcon#*before return 0, iclass 21, count 0 2006.173.05:41:56.90#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.05:41:56.90#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.05:41:56.90#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.05:41:56.90#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.05:41:56.90$vck44/va=6,3 2006.173.05:41:56.90#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.05:41:56.90#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.05:41:56.90#ibcon#ireg 11 cls_cnt 2 2006.173.05:41:56.90#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.05:41:56.96#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.05:41:56.96#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.05:41:56.96#ibcon#enter wrdev, iclass 23, count 2 2006.173.05:41:56.96#ibcon#first serial, iclass 23, count 2 2006.173.05:41:56.96#ibcon#enter sib2, iclass 23, count 2 2006.173.05:41:56.96#ibcon#flushed, iclass 23, count 2 2006.173.05:41:56.96#ibcon#about to write, iclass 23, count 2 2006.173.05:41:56.96#ibcon#wrote, iclass 23, count 2 2006.173.05:41:56.96#ibcon#about to read 3, iclass 23, count 2 2006.173.05:41:56.98#ibcon#read 3, iclass 23, count 2 2006.173.05:41:56.98#ibcon#about to read 4, iclass 23, count 2 2006.173.05:41:56.98#ibcon#read 4, iclass 23, count 2 2006.173.05:41:56.98#ibcon#about to read 5, iclass 23, count 2 2006.173.05:41:56.98#ibcon#read 5, iclass 23, count 2 2006.173.05:41:56.98#ibcon#about to read 6, iclass 23, count 2 2006.173.05:41:56.98#ibcon#read 6, iclass 23, count 2 2006.173.05:41:56.98#ibcon#end of sib2, iclass 23, count 2 2006.173.05:41:56.98#ibcon#*mode == 0, iclass 23, count 2 2006.173.05:41:56.98#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.05:41:56.98#ibcon#[25=AT06-03\r\n] 2006.173.05:41:56.98#ibcon#*before write, iclass 23, count 2 2006.173.05:41:56.98#ibcon#enter sib2, iclass 23, count 2 2006.173.05:41:56.98#ibcon#flushed, iclass 23, count 2 2006.173.05:41:56.98#ibcon#about to write, iclass 23, count 2 2006.173.05:41:56.98#ibcon#wrote, iclass 23, count 2 2006.173.05:41:56.98#ibcon#about to read 3, iclass 23, count 2 2006.173.05:41:57.01#ibcon#read 3, iclass 23, count 2 2006.173.05:41:57.01#ibcon#about to read 4, iclass 23, count 2 2006.173.05:41:57.01#ibcon#read 4, iclass 23, count 2 2006.173.05:41:57.01#ibcon#about to read 5, iclass 23, count 2 2006.173.05:41:57.01#ibcon#read 5, iclass 23, count 2 2006.173.05:41:57.01#ibcon#about to read 6, iclass 23, count 2 2006.173.05:41:57.01#ibcon#read 6, iclass 23, count 2 2006.173.05:41:57.01#ibcon#end of sib2, iclass 23, count 2 2006.173.05:41:57.01#ibcon#*after write, iclass 23, count 2 2006.173.05:41:57.01#ibcon#*before return 0, iclass 23, count 2 2006.173.05:41:57.01#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.05:41:57.01#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.05:41:57.01#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.05:41:57.01#ibcon#ireg 7 cls_cnt 0 2006.173.05:41:57.01#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.05:41:57.13#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.05:41:57.13#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.05:41:57.13#ibcon#enter wrdev, iclass 23, count 0 2006.173.05:41:57.13#ibcon#first serial, iclass 23, count 0 2006.173.05:41:57.13#ibcon#enter sib2, iclass 23, count 0 2006.173.05:41:57.13#ibcon#flushed, iclass 23, count 0 2006.173.05:41:57.13#ibcon#about to write, iclass 23, count 0 2006.173.05:41:57.13#ibcon#wrote, iclass 23, count 0 2006.173.05:41:57.13#ibcon#about to read 3, iclass 23, count 0 2006.173.05:41:57.15#ibcon#read 3, iclass 23, count 0 2006.173.05:41:57.15#ibcon#about to read 4, iclass 23, count 0 2006.173.05:41:57.15#ibcon#read 4, iclass 23, count 0 2006.173.05:41:57.15#ibcon#about to read 5, iclass 23, count 0 2006.173.05:41:57.15#ibcon#read 5, iclass 23, count 0 2006.173.05:41:57.15#ibcon#about to read 6, iclass 23, count 0 2006.173.05:41:57.15#ibcon#read 6, iclass 23, count 0 2006.173.05:41:57.15#ibcon#end of sib2, iclass 23, count 0 2006.173.05:41:57.15#ibcon#*mode == 0, iclass 23, count 0 2006.173.05:41:57.15#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.05:41:57.15#ibcon#[25=USB\r\n] 2006.173.05:41:57.15#ibcon#*before write, iclass 23, count 0 2006.173.05:41:57.15#ibcon#enter sib2, iclass 23, count 0 2006.173.05:41:57.15#ibcon#flushed, iclass 23, count 0 2006.173.05:41:57.15#ibcon#about to write, iclass 23, count 0 2006.173.05:41:57.15#ibcon#wrote, iclass 23, count 0 2006.173.05:41:57.15#ibcon#about to read 3, iclass 23, count 0 2006.173.05:41:57.18#ibcon#read 3, iclass 23, count 0 2006.173.05:41:57.18#ibcon#about to read 4, iclass 23, count 0 2006.173.05:41:57.18#ibcon#read 4, iclass 23, count 0 2006.173.05:41:57.18#ibcon#about to read 5, iclass 23, count 0 2006.173.05:41:57.18#ibcon#read 5, iclass 23, count 0 2006.173.05:41:57.18#ibcon#about to read 6, iclass 23, count 0 2006.173.05:41:57.18#ibcon#read 6, iclass 23, count 0 2006.173.05:41:57.18#ibcon#end of sib2, iclass 23, count 0 2006.173.05:41:57.18#ibcon#*after write, iclass 23, count 0 2006.173.05:41:57.18#ibcon#*before return 0, iclass 23, count 0 2006.173.05:41:57.18#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.05:41:57.18#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.05:41:57.18#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.05:41:57.18#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.05:41:57.18$vck44/valo=7,864.99 2006.173.05:41:57.18#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.05:41:57.18#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.05:41:57.18#ibcon#ireg 17 cls_cnt 0 2006.173.05:41:57.18#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.05:41:57.18#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.05:41:57.18#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.05:41:57.18#ibcon#enter wrdev, iclass 25, count 0 2006.173.05:41:57.18#ibcon#first serial, iclass 25, count 0 2006.173.05:41:57.18#ibcon#enter sib2, iclass 25, count 0 2006.173.05:41:57.18#ibcon#flushed, iclass 25, count 0 2006.173.05:41:57.18#ibcon#about to write, iclass 25, count 0 2006.173.05:41:57.18#ibcon#wrote, iclass 25, count 0 2006.173.05:41:57.18#ibcon#about to read 3, iclass 25, count 0 2006.173.05:41:57.20#ibcon#read 3, iclass 25, count 0 2006.173.05:41:57.20#ibcon#about to read 4, iclass 25, count 0 2006.173.05:41:57.20#ibcon#read 4, iclass 25, count 0 2006.173.05:41:57.20#ibcon#about to read 5, iclass 25, count 0 2006.173.05:41:57.20#ibcon#read 5, iclass 25, count 0 2006.173.05:41:57.20#ibcon#about to read 6, iclass 25, count 0 2006.173.05:41:57.20#ibcon#read 6, iclass 25, count 0 2006.173.05:41:57.20#ibcon#end of sib2, iclass 25, count 0 2006.173.05:41:57.20#ibcon#*mode == 0, iclass 25, count 0 2006.173.05:41:57.20#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.05:41:57.20#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.05:41:57.20#ibcon#*before write, iclass 25, count 0 2006.173.05:41:57.20#ibcon#enter sib2, iclass 25, count 0 2006.173.05:41:57.20#ibcon#flushed, iclass 25, count 0 2006.173.05:41:57.20#ibcon#about to write, iclass 25, count 0 2006.173.05:41:57.20#ibcon#wrote, iclass 25, count 0 2006.173.05:41:57.20#ibcon#about to read 3, iclass 25, count 0 2006.173.05:41:57.24#ibcon#read 3, iclass 25, count 0 2006.173.05:41:57.24#ibcon#about to read 4, iclass 25, count 0 2006.173.05:41:57.24#ibcon#read 4, iclass 25, count 0 2006.173.05:41:57.24#ibcon#about to read 5, iclass 25, count 0 2006.173.05:41:57.24#ibcon#read 5, iclass 25, count 0 2006.173.05:41:57.24#ibcon#about to read 6, iclass 25, count 0 2006.173.05:41:57.24#ibcon#read 6, iclass 25, count 0 2006.173.05:41:57.24#ibcon#end of sib2, iclass 25, count 0 2006.173.05:41:57.24#ibcon#*after write, iclass 25, count 0 2006.173.05:41:57.24#ibcon#*before return 0, iclass 25, count 0 2006.173.05:41:57.24#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.05:41:57.24#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.05:41:57.24#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.05:41:57.24#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.05:41:57.24$vck44/va=7,4 2006.173.05:41:57.24#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.05:41:57.24#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.05:41:57.24#ibcon#ireg 11 cls_cnt 2 2006.173.05:41:57.24#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.05:41:57.30#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.05:41:57.30#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.05:41:57.30#ibcon#enter wrdev, iclass 27, count 2 2006.173.05:41:57.30#ibcon#first serial, iclass 27, count 2 2006.173.05:41:57.30#ibcon#enter sib2, iclass 27, count 2 2006.173.05:41:57.30#ibcon#flushed, iclass 27, count 2 2006.173.05:41:57.30#ibcon#about to write, iclass 27, count 2 2006.173.05:41:57.30#ibcon#wrote, iclass 27, count 2 2006.173.05:41:57.30#ibcon#about to read 3, iclass 27, count 2 2006.173.05:41:57.32#ibcon#read 3, iclass 27, count 2 2006.173.05:41:57.32#ibcon#about to read 4, iclass 27, count 2 2006.173.05:41:57.32#ibcon#read 4, iclass 27, count 2 2006.173.05:41:57.32#ibcon#about to read 5, iclass 27, count 2 2006.173.05:41:57.32#ibcon#read 5, iclass 27, count 2 2006.173.05:41:57.32#ibcon#about to read 6, iclass 27, count 2 2006.173.05:41:57.32#ibcon#read 6, iclass 27, count 2 2006.173.05:41:57.32#ibcon#end of sib2, iclass 27, count 2 2006.173.05:41:57.32#ibcon#*mode == 0, iclass 27, count 2 2006.173.05:41:57.32#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.05:41:57.32#ibcon#[25=AT07-04\r\n] 2006.173.05:41:57.32#ibcon#*before write, iclass 27, count 2 2006.173.05:41:57.32#ibcon#enter sib2, iclass 27, count 2 2006.173.05:41:57.32#ibcon#flushed, iclass 27, count 2 2006.173.05:41:57.32#ibcon#about to write, iclass 27, count 2 2006.173.05:41:57.32#ibcon#wrote, iclass 27, count 2 2006.173.05:41:57.32#ibcon#about to read 3, iclass 27, count 2 2006.173.05:41:57.35#ibcon#read 3, iclass 27, count 2 2006.173.05:41:57.35#ibcon#about to read 4, iclass 27, count 2 2006.173.05:41:57.35#ibcon#read 4, iclass 27, count 2 2006.173.05:41:57.35#ibcon#about to read 5, iclass 27, count 2 2006.173.05:41:57.35#ibcon#read 5, iclass 27, count 2 2006.173.05:41:57.35#ibcon#about to read 6, iclass 27, count 2 2006.173.05:41:57.35#ibcon#read 6, iclass 27, count 2 2006.173.05:41:57.35#ibcon#end of sib2, iclass 27, count 2 2006.173.05:41:57.35#ibcon#*after write, iclass 27, count 2 2006.173.05:41:57.35#ibcon#*before return 0, iclass 27, count 2 2006.173.05:41:57.35#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.05:41:57.35#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.05:41:57.35#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.05:41:57.35#ibcon#ireg 7 cls_cnt 0 2006.173.05:41:57.35#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.05:41:57.47#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.05:41:57.47#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.05:41:57.47#ibcon#enter wrdev, iclass 27, count 0 2006.173.05:41:57.47#ibcon#first serial, iclass 27, count 0 2006.173.05:41:57.47#ibcon#enter sib2, iclass 27, count 0 2006.173.05:41:57.47#ibcon#flushed, iclass 27, count 0 2006.173.05:41:57.47#ibcon#about to write, iclass 27, count 0 2006.173.05:41:57.47#ibcon#wrote, iclass 27, count 0 2006.173.05:41:57.47#ibcon#about to read 3, iclass 27, count 0 2006.173.05:41:57.49#ibcon#read 3, iclass 27, count 0 2006.173.05:41:57.49#ibcon#about to read 4, iclass 27, count 0 2006.173.05:41:57.49#ibcon#read 4, iclass 27, count 0 2006.173.05:41:57.49#ibcon#about to read 5, iclass 27, count 0 2006.173.05:41:57.49#ibcon#read 5, iclass 27, count 0 2006.173.05:41:57.49#ibcon#about to read 6, iclass 27, count 0 2006.173.05:41:57.49#ibcon#read 6, iclass 27, count 0 2006.173.05:41:57.49#ibcon#end of sib2, iclass 27, count 0 2006.173.05:41:57.49#ibcon#*mode == 0, iclass 27, count 0 2006.173.05:41:57.49#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.05:41:57.49#ibcon#[25=USB\r\n] 2006.173.05:41:57.49#ibcon#*before write, iclass 27, count 0 2006.173.05:41:57.49#ibcon#enter sib2, iclass 27, count 0 2006.173.05:41:57.49#ibcon#flushed, iclass 27, count 0 2006.173.05:41:57.49#ibcon#about to write, iclass 27, count 0 2006.173.05:41:57.49#ibcon#wrote, iclass 27, count 0 2006.173.05:41:57.49#ibcon#about to read 3, iclass 27, count 0 2006.173.05:41:57.52#ibcon#read 3, iclass 27, count 0 2006.173.05:41:57.52#ibcon#about to read 4, iclass 27, count 0 2006.173.05:41:57.52#ibcon#read 4, iclass 27, count 0 2006.173.05:41:57.52#ibcon#about to read 5, iclass 27, count 0 2006.173.05:41:57.52#ibcon#read 5, iclass 27, count 0 2006.173.05:41:57.52#ibcon#about to read 6, iclass 27, count 0 2006.173.05:41:57.52#ibcon#read 6, iclass 27, count 0 2006.173.05:41:57.52#ibcon#end of sib2, iclass 27, count 0 2006.173.05:41:57.52#ibcon#*after write, iclass 27, count 0 2006.173.05:41:57.52#ibcon#*before return 0, iclass 27, count 0 2006.173.05:41:57.52#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.05:41:57.52#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.05:41:57.52#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.05:41:57.52#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.05:41:57.52$vck44/valo=8,884.99 2006.173.05:41:57.52#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.05:41:57.52#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.05:41:57.52#ibcon#ireg 17 cls_cnt 0 2006.173.05:41:57.52#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.05:41:57.52#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.05:41:57.52#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.05:41:57.52#ibcon#enter wrdev, iclass 29, count 0 2006.173.05:41:57.52#ibcon#first serial, iclass 29, count 0 2006.173.05:41:57.52#ibcon#enter sib2, iclass 29, count 0 2006.173.05:41:57.52#ibcon#flushed, iclass 29, count 0 2006.173.05:41:57.52#ibcon#about to write, iclass 29, count 0 2006.173.05:41:57.52#ibcon#wrote, iclass 29, count 0 2006.173.05:41:57.52#ibcon#about to read 3, iclass 29, count 0 2006.173.05:41:57.54#ibcon#read 3, iclass 29, count 0 2006.173.05:41:57.54#ibcon#about to read 4, iclass 29, count 0 2006.173.05:41:57.54#ibcon#read 4, iclass 29, count 0 2006.173.05:41:57.54#ibcon#about to read 5, iclass 29, count 0 2006.173.05:41:57.54#ibcon#read 5, iclass 29, count 0 2006.173.05:41:57.54#ibcon#about to read 6, iclass 29, count 0 2006.173.05:41:57.54#ibcon#read 6, iclass 29, count 0 2006.173.05:41:57.54#ibcon#end of sib2, iclass 29, count 0 2006.173.05:41:57.54#ibcon#*mode == 0, iclass 29, count 0 2006.173.05:41:57.54#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.05:41:57.54#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.05:41:57.54#ibcon#*before write, iclass 29, count 0 2006.173.05:41:57.54#ibcon#enter sib2, iclass 29, count 0 2006.173.05:41:57.54#ibcon#flushed, iclass 29, count 0 2006.173.05:41:57.54#ibcon#about to write, iclass 29, count 0 2006.173.05:41:57.54#ibcon#wrote, iclass 29, count 0 2006.173.05:41:57.54#ibcon#about to read 3, iclass 29, count 0 2006.173.05:41:57.58#ibcon#read 3, iclass 29, count 0 2006.173.05:41:57.58#ibcon#about to read 4, iclass 29, count 0 2006.173.05:41:57.58#ibcon#read 4, iclass 29, count 0 2006.173.05:41:57.58#ibcon#about to read 5, iclass 29, count 0 2006.173.05:41:57.58#ibcon#read 5, iclass 29, count 0 2006.173.05:41:57.58#ibcon#about to read 6, iclass 29, count 0 2006.173.05:41:57.58#ibcon#read 6, iclass 29, count 0 2006.173.05:41:57.58#ibcon#end of sib2, iclass 29, count 0 2006.173.05:41:57.58#ibcon#*after write, iclass 29, count 0 2006.173.05:41:57.58#ibcon#*before return 0, iclass 29, count 0 2006.173.05:41:57.58#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.05:41:57.58#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.05:41:57.58#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.05:41:57.58#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.05:41:57.58$vck44/va=8,4 2006.173.05:41:57.58#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.05:41:57.58#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.05:41:57.58#ibcon#ireg 11 cls_cnt 2 2006.173.05:41:57.58#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.05:41:57.64#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.05:41:57.64#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.05:41:57.64#ibcon#enter wrdev, iclass 31, count 2 2006.173.05:41:57.64#ibcon#first serial, iclass 31, count 2 2006.173.05:41:57.64#ibcon#enter sib2, iclass 31, count 2 2006.173.05:41:57.64#ibcon#flushed, iclass 31, count 2 2006.173.05:41:57.64#ibcon#about to write, iclass 31, count 2 2006.173.05:41:57.64#ibcon#wrote, iclass 31, count 2 2006.173.05:41:57.64#ibcon#about to read 3, iclass 31, count 2 2006.173.05:41:57.66#ibcon#read 3, iclass 31, count 2 2006.173.05:41:57.66#ibcon#about to read 4, iclass 31, count 2 2006.173.05:41:57.66#ibcon#read 4, iclass 31, count 2 2006.173.05:41:57.66#ibcon#about to read 5, iclass 31, count 2 2006.173.05:41:57.66#ibcon#read 5, iclass 31, count 2 2006.173.05:41:57.66#ibcon#about to read 6, iclass 31, count 2 2006.173.05:41:57.66#ibcon#read 6, iclass 31, count 2 2006.173.05:41:57.66#ibcon#end of sib2, iclass 31, count 2 2006.173.05:41:57.66#ibcon#*mode == 0, iclass 31, count 2 2006.173.05:41:57.66#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.05:41:57.66#ibcon#[25=AT08-04\r\n] 2006.173.05:41:57.66#ibcon#*before write, iclass 31, count 2 2006.173.05:41:57.66#ibcon#enter sib2, iclass 31, count 2 2006.173.05:41:57.66#ibcon#flushed, iclass 31, count 2 2006.173.05:41:57.66#ibcon#about to write, iclass 31, count 2 2006.173.05:41:57.66#ibcon#wrote, iclass 31, count 2 2006.173.05:41:57.66#ibcon#about to read 3, iclass 31, count 2 2006.173.05:41:57.69#ibcon#read 3, iclass 31, count 2 2006.173.05:41:57.69#ibcon#about to read 4, iclass 31, count 2 2006.173.05:41:57.69#ibcon#read 4, iclass 31, count 2 2006.173.05:41:57.69#ibcon#about to read 5, iclass 31, count 2 2006.173.05:41:57.69#ibcon#read 5, iclass 31, count 2 2006.173.05:41:57.69#ibcon#about to read 6, iclass 31, count 2 2006.173.05:41:57.69#ibcon#read 6, iclass 31, count 2 2006.173.05:41:57.69#ibcon#end of sib2, iclass 31, count 2 2006.173.05:41:57.69#ibcon#*after write, iclass 31, count 2 2006.173.05:41:57.69#ibcon#*before return 0, iclass 31, count 2 2006.173.05:41:57.69#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.05:41:57.69#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.05:41:57.69#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.05:41:57.69#ibcon#ireg 7 cls_cnt 0 2006.173.05:41:57.69#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.05:41:57.81#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.05:41:57.81#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.05:41:57.81#ibcon#enter wrdev, iclass 31, count 0 2006.173.05:41:57.81#ibcon#first serial, iclass 31, count 0 2006.173.05:41:57.81#ibcon#enter sib2, iclass 31, count 0 2006.173.05:41:57.81#ibcon#flushed, iclass 31, count 0 2006.173.05:41:57.81#ibcon#about to write, iclass 31, count 0 2006.173.05:41:57.81#ibcon#wrote, iclass 31, count 0 2006.173.05:41:57.81#ibcon#about to read 3, iclass 31, count 0 2006.173.05:41:57.83#ibcon#read 3, iclass 31, count 0 2006.173.05:41:57.83#ibcon#about to read 4, iclass 31, count 0 2006.173.05:41:57.83#ibcon#read 4, iclass 31, count 0 2006.173.05:41:57.83#ibcon#about to read 5, iclass 31, count 0 2006.173.05:41:57.83#ibcon#read 5, iclass 31, count 0 2006.173.05:41:57.83#ibcon#about to read 6, iclass 31, count 0 2006.173.05:41:57.83#ibcon#read 6, iclass 31, count 0 2006.173.05:41:57.83#ibcon#end of sib2, iclass 31, count 0 2006.173.05:41:57.83#ibcon#*mode == 0, iclass 31, count 0 2006.173.05:41:57.83#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.05:41:57.83#ibcon#[25=USB\r\n] 2006.173.05:41:57.83#ibcon#*before write, iclass 31, count 0 2006.173.05:41:57.83#ibcon#enter sib2, iclass 31, count 0 2006.173.05:41:57.83#ibcon#flushed, iclass 31, count 0 2006.173.05:41:57.83#ibcon#about to write, iclass 31, count 0 2006.173.05:41:57.83#ibcon#wrote, iclass 31, count 0 2006.173.05:41:57.83#ibcon#about to read 3, iclass 31, count 0 2006.173.05:41:57.86#ibcon#read 3, iclass 31, count 0 2006.173.05:41:57.86#ibcon#about to read 4, iclass 31, count 0 2006.173.05:41:57.86#ibcon#read 4, iclass 31, count 0 2006.173.05:41:57.86#ibcon#about to read 5, iclass 31, count 0 2006.173.05:41:57.86#ibcon#read 5, iclass 31, count 0 2006.173.05:41:57.86#ibcon#about to read 6, iclass 31, count 0 2006.173.05:41:57.86#ibcon#read 6, iclass 31, count 0 2006.173.05:41:57.86#ibcon#end of sib2, iclass 31, count 0 2006.173.05:41:57.86#ibcon#*after write, iclass 31, count 0 2006.173.05:41:57.86#ibcon#*before return 0, iclass 31, count 0 2006.173.05:41:57.86#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.05:41:57.86#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.05:41:57.86#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.05:41:57.86#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.05:41:57.86$vck44/vblo=1,629.99 2006.173.05:41:57.86#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.05:41:57.86#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.05:41:57.86#ibcon#ireg 17 cls_cnt 0 2006.173.05:41:57.86#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.05:41:57.86#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.05:41:57.86#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.05:41:57.86#ibcon#enter wrdev, iclass 33, count 0 2006.173.05:41:57.86#ibcon#first serial, iclass 33, count 0 2006.173.05:41:57.86#ibcon#enter sib2, iclass 33, count 0 2006.173.05:41:57.86#ibcon#flushed, iclass 33, count 0 2006.173.05:41:57.86#ibcon#about to write, iclass 33, count 0 2006.173.05:41:57.86#ibcon#wrote, iclass 33, count 0 2006.173.05:41:57.86#ibcon#about to read 3, iclass 33, count 0 2006.173.05:41:57.88#ibcon#read 3, iclass 33, count 0 2006.173.05:41:57.88#ibcon#about to read 4, iclass 33, count 0 2006.173.05:41:57.88#ibcon#read 4, iclass 33, count 0 2006.173.05:41:57.88#ibcon#about to read 5, iclass 33, count 0 2006.173.05:41:57.88#ibcon#read 5, iclass 33, count 0 2006.173.05:41:57.88#ibcon#about to read 6, iclass 33, count 0 2006.173.05:41:57.88#ibcon#read 6, iclass 33, count 0 2006.173.05:41:57.88#ibcon#end of sib2, iclass 33, count 0 2006.173.05:41:57.88#ibcon#*mode == 0, iclass 33, count 0 2006.173.05:41:57.88#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.05:41:57.88#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.05:41:57.88#ibcon#*before write, iclass 33, count 0 2006.173.05:41:57.88#ibcon#enter sib2, iclass 33, count 0 2006.173.05:41:57.88#ibcon#flushed, iclass 33, count 0 2006.173.05:41:57.88#ibcon#about to write, iclass 33, count 0 2006.173.05:41:57.88#ibcon#wrote, iclass 33, count 0 2006.173.05:41:57.88#ibcon#about to read 3, iclass 33, count 0 2006.173.05:41:57.92#ibcon#read 3, iclass 33, count 0 2006.173.05:41:57.92#ibcon#about to read 4, iclass 33, count 0 2006.173.05:41:57.92#ibcon#read 4, iclass 33, count 0 2006.173.05:41:57.92#ibcon#about to read 5, iclass 33, count 0 2006.173.05:41:57.92#ibcon#read 5, iclass 33, count 0 2006.173.05:41:57.92#ibcon#about to read 6, iclass 33, count 0 2006.173.05:41:57.92#ibcon#read 6, iclass 33, count 0 2006.173.05:41:57.92#ibcon#end of sib2, iclass 33, count 0 2006.173.05:41:57.92#ibcon#*after write, iclass 33, count 0 2006.173.05:41:57.92#ibcon#*before return 0, iclass 33, count 0 2006.173.05:41:57.92#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.05:41:57.92#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.05:41:57.92#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.05:41:57.92#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.05:41:57.92$vck44/vb=1,4 2006.173.05:41:57.92#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.05:41:57.92#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.05:41:57.92#ibcon#ireg 11 cls_cnt 2 2006.173.05:41:57.92#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.05:41:57.92#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.05:41:57.92#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.05:41:57.92#ibcon#enter wrdev, iclass 35, count 2 2006.173.05:41:57.92#ibcon#first serial, iclass 35, count 2 2006.173.05:41:57.92#ibcon#enter sib2, iclass 35, count 2 2006.173.05:41:57.92#ibcon#flushed, iclass 35, count 2 2006.173.05:41:57.92#ibcon#about to write, iclass 35, count 2 2006.173.05:41:57.92#ibcon#wrote, iclass 35, count 2 2006.173.05:41:57.92#ibcon#about to read 3, iclass 35, count 2 2006.173.05:41:57.94#ibcon#read 3, iclass 35, count 2 2006.173.05:41:57.94#ibcon#about to read 4, iclass 35, count 2 2006.173.05:41:57.94#ibcon#read 4, iclass 35, count 2 2006.173.05:41:57.94#ibcon#about to read 5, iclass 35, count 2 2006.173.05:41:57.94#ibcon#read 5, iclass 35, count 2 2006.173.05:41:57.94#ibcon#about to read 6, iclass 35, count 2 2006.173.05:41:57.94#ibcon#read 6, iclass 35, count 2 2006.173.05:41:57.94#ibcon#end of sib2, iclass 35, count 2 2006.173.05:41:57.94#ibcon#*mode == 0, iclass 35, count 2 2006.173.05:41:57.94#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.05:41:57.94#ibcon#[27=AT01-04\r\n] 2006.173.05:41:57.94#ibcon#*before write, iclass 35, count 2 2006.173.05:41:57.94#ibcon#enter sib2, iclass 35, count 2 2006.173.05:41:57.94#ibcon#flushed, iclass 35, count 2 2006.173.05:41:57.94#ibcon#about to write, iclass 35, count 2 2006.173.05:41:57.94#ibcon#wrote, iclass 35, count 2 2006.173.05:41:57.94#ibcon#about to read 3, iclass 35, count 2 2006.173.05:41:57.97#ibcon#read 3, iclass 35, count 2 2006.173.05:41:57.97#ibcon#about to read 4, iclass 35, count 2 2006.173.05:41:57.97#ibcon#read 4, iclass 35, count 2 2006.173.05:41:57.97#ibcon#about to read 5, iclass 35, count 2 2006.173.05:41:57.97#ibcon#read 5, iclass 35, count 2 2006.173.05:41:57.97#ibcon#about to read 6, iclass 35, count 2 2006.173.05:41:57.97#ibcon#read 6, iclass 35, count 2 2006.173.05:41:57.97#ibcon#end of sib2, iclass 35, count 2 2006.173.05:41:57.97#ibcon#*after write, iclass 35, count 2 2006.173.05:41:57.97#ibcon#*before return 0, iclass 35, count 2 2006.173.05:41:57.97#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.05:41:57.97#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.05:41:57.97#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.05:41:57.97#ibcon#ireg 7 cls_cnt 0 2006.173.05:41:57.97#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.05:41:58.09#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.05:41:58.09#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.05:41:58.09#ibcon#enter wrdev, iclass 35, count 0 2006.173.05:41:58.09#ibcon#first serial, iclass 35, count 0 2006.173.05:41:58.09#ibcon#enter sib2, iclass 35, count 0 2006.173.05:41:58.09#ibcon#flushed, iclass 35, count 0 2006.173.05:41:58.09#ibcon#about to write, iclass 35, count 0 2006.173.05:41:58.09#ibcon#wrote, iclass 35, count 0 2006.173.05:41:58.09#ibcon#about to read 3, iclass 35, count 0 2006.173.05:41:58.11#ibcon#read 3, iclass 35, count 0 2006.173.05:41:58.11#ibcon#about to read 4, iclass 35, count 0 2006.173.05:41:58.11#ibcon#read 4, iclass 35, count 0 2006.173.05:41:58.11#ibcon#about to read 5, iclass 35, count 0 2006.173.05:41:58.11#ibcon#read 5, iclass 35, count 0 2006.173.05:41:58.11#ibcon#about to read 6, iclass 35, count 0 2006.173.05:41:58.11#ibcon#read 6, iclass 35, count 0 2006.173.05:41:58.11#ibcon#end of sib2, iclass 35, count 0 2006.173.05:41:58.11#ibcon#*mode == 0, iclass 35, count 0 2006.173.05:41:58.11#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.05:41:58.11#ibcon#[27=USB\r\n] 2006.173.05:41:58.11#ibcon#*before write, iclass 35, count 0 2006.173.05:41:58.11#ibcon#enter sib2, iclass 35, count 0 2006.173.05:41:58.11#ibcon#flushed, iclass 35, count 0 2006.173.05:41:58.11#ibcon#about to write, iclass 35, count 0 2006.173.05:41:58.11#ibcon#wrote, iclass 35, count 0 2006.173.05:41:58.11#ibcon#about to read 3, iclass 35, count 0 2006.173.05:41:58.14#ibcon#read 3, iclass 35, count 0 2006.173.05:41:58.14#ibcon#about to read 4, iclass 35, count 0 2006.173.05:41:58.14#ibcon#read 4, iclass 35, count 0 2006.173.05:41:58.14#ibcon#about to read 5, iclass 35, count 0 2006.173.05:41:58.14#ibcon#read 5, iclass 35, count 0 2006.173.05:41:58.14#ibcon#about to read 6, iclass 35, count 0 2006.173.05:41:58.14#ibcon#read 6, iclass 35, count 0 2006.173.05:41:58.14#ibcon#end of sib2, iclass 35, count 0 2006.173.05:41:58.14#ibcon#*after write, iclass 35, count 0 2006.173.05:41:58.14#ibcon#*before return 0, iclass 35, count 0 2006.173.05:41:58.14#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.05:41:58.14#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.05:41:58.14#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.05:41:58.14#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.05:41:58.14$vck44/vblo=2,634.99 2006.173.05:41:58.14#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.05:41:58.14#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.05:41:58.14#ibcon#ireg 17 cls_cnt 0 2006.173.05:41:58.14#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.05:41:58.14#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.05:41:58.14#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.05:41:58.14#ibcon#enter wrdev, iclass 37, count 0 2006.173.05:41:58.14#ibcon#first serial, iclass 37, count 0 2006.173.05:41:58.14#ibcon#enter sib2, iclass 37, count 0 2006.173.05:41:58.14#ibcon#flushed, iclass 37, count 0 2006.173.05:41:58.14#ibcon#about to write, iclass 37, count 0 2006.173.05:41:58.14#ibcon#wrote, iclass 37, count 0 2006.173.05:41:58.14#ibcon#about to read 3, iclass 37, count 0 2006.173.05:41:58.16#ibcon#read 3, iclass 37, count 0 2006.173.05:41:58.16#ibcon#about to read 4, iclass 37, count 0 2006.173.05:41:58.16#ibcon#read 4, iclass 37, count 0 2006.173.05:41:58.16#ibcon#about to read 5, iclass 37, count 0 2006.173.05:41:58.16#ibcon#read 5, iclass 37, count 0 2006.173.05:41:58.16#ibcon#about to read 6, iclass 37, count 0 2006.173.05:41:58.16#ibcon#read 6, iclass 37, count 0 2006.173.05:41:58.16#ibcon#end of sib2, iclass 37, count 0 2006.173.05:41:58.16#ibcon#*mode == 0, iclass 37, count 0 2006.173.05:41:58.16#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.05:41:58.16#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.05:41:58.16#ibcon#*before write, iclass 37, count 0 2006.173.05:41:58.16#ibcon#enter sib2, iclass 37, count 0 2006.173.05:41:58.16#ibcon#flushed, iclass 37, count 0 2006.173.05:41:58.16#ibcon#about to write, iclass 37, count 0 2006.173.05:41:58.16#ibcon#wrote, iclass 37, count 0 2006.173.05:41:58.16#ibcon#about to read 3, iclass 37, count 0 2006.173.05:41:58.20#ibcon#read 3, iclass 37, count 0 2006.173.05:41:58.20#ibcon#about to read 4, iclass 37, count 0 2006.173.05:41:58.20#ibcon#read 4, iclass 37, count 0 2006.173.05:41:58.20#ibcon#about to read 5, iclass 37, count 0 2006.173.05:41:58.20#ibcon#read 5, iclass 37, count 0 2006.173.05:41:58.20#ibcon#about to read 6, iclass 37, count 0 2006.173.05:41:58.20#ibcon#read 6, iclass 37, count 0 2006.173.05:41:58.20#ibcon#end of sib2, iclass 37, count 0 2006.173.05:41:58.20#ibcon#*after write, iclass 37, count 0 2006.173.05:41:58.20#ibcon#*before return 0, iclass 37, count 0 2006.173.05:41:58.20#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.05:41:58.20#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.05:41:58.20#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.05:41:58.20#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.05:41:58.20$vck44/vb=2,4 2006.173.05:41:58.20#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.05:41:58.20#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.05:41:58.20#ibcon#ireg 11 cls_cnt 2 2006.173.05:41:58.20#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.05:41:58.26#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.05:41:58.26#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.05:41:58.26#ibcon#enter wrdev, iclass 39, count 2 2006.173.05:41:58.26#ibcon#first serial, iclass 39, count 2 2006.173.05:41:58.26#ibcon#enter sib2, iclass 39, count 2 2006.173.05:41:58.26#ibcon#flushed, iclass 39, count 2 2006.173.05:41:58.26#ibcon#about to write, iclass 39, count 2 2006.173.05:41:58.26#ibcon#wrote, iclass 39, count 2 2006.173.05:41:58.26#ibcon#about to read 3, iclass 39, count 2 2006.173.05:41:58.28#ibcon#read 3, iclass 39, count 2 2006.173.05:41:58.28#ibcon#about to read 4, iclass 39, count 2 2006.173.05:41:58.28#ibcon#read 4, iclass 39, count 2 2006.173.05:41:58.28#ibcon#about to read 5, iclass 39, count 2 2006.173.05:41:58.28#ibcon#read 5, iclass 39, count 2 2006.173.05:41:58.28#ibcon#about to read 6, iclass 39, count 2 2006.173.05:41:58.28#ibcon#read 6, iclass 39, count 2 2006.173.05:41:58.28#ibcon#end of sib2, iclass 39, count 2 2006.173.05:41:58.28#ibcon#*mode == 0, iclass 39, count 2 2006.173.05:41:58.28#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.05:41:58.28#ibcon#[27=AT02-04\r\n] 2006.173.05:41:58.28#ibcon#*before write, iclass 39, count 2 2006.173.05:41:58.28#ibcon#enter sib2, iclass 39, count 2 2006.173.05:41:58.28#ibcon#flushed, iclass 39, count 2 2006.173.05:41:58.28#ibcon#about to write, iclass 39, count 2 2006.173.05:41:58.28#ibcon#wrote, iclass 39, count 2 2006.173.05:41:58.28#ibcon#about to read 3, iclass 39, count 2 2006.173.05:41:58.31#ibcon#read 3, iclass 39, count 2 2006.173.05:41:58.31#ibcon#about to read 4, iclass 39, count 2 2006.173.05:41:58.31#ibcon#read 4, iclass 39, count 2 2006.173.05:41:58.31#ibcon#about to read 5, iclass 39, count 2 2006.173.05:41:58.31#ibcon#read 5, iclass 39, count 2 2006.173.05:41:58.31#ibcon#about to read 6, iclass 39, count 2 2006.173.05:41:58.31#ibcon#read 6, iclass 39, count 2 2006.173.05:41:58.31#ibcon#end of sib2, iclass 39, count 2 2006.173.05:41:58.31#ibcon#*after write, iclass 39, count 2 2006.173.05:41:58.31#ibcon#*before return 0, iclass 39, count 2 2006.173.05:41:58.31#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.05:41:58.31#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.05:41:58.31#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.05:41:58.31#ibcon#ireg 7 cls_cnt 0 2006.173.05:41:58.31#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.05:41:58.43#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.05:41:58.43#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.05:41:58.43#ibcon#enter wrdev, iclass 39, count 0 2006.173.05:41:58.43#ibcon#first serial, iclass 39, count 0 2006.173.05:41:58.43#ibcon#enter sib2, iclass 39, count 0 2006.173.05:41:58.43#ibcon#flushed, iclass 39, count 0 2006.173.05:41:58.43#ibcon#about to write, iclass 39, count 0 2006.173.05:41:58.43#ibcon#wrote, iclass 39, count 0 2006.173.05:41:58.43#ibcon#about to read 3, iclass 39, count 0 2006.173.05:41:58.45#ibcon#read 3, iclass 39, count 0 2006.173.05:41:58.45#ibcon#about to read 4, iclass 39, count 0 2006.173.05:41:58.45#ibcon#read 4, iclass 39, count 0 2006.173.05:41:58.45#ibcon#about to read 5, iclass 39, count 0 2006.173.05:41:58.45#ibcon#read 5, iclass 39, count 0 2006.173.05:41:58.45#ibcon#about to read 6, iclass 39, count 0 2006.173.05:41:58.45#ibcon#read 6, iclass 39, count 0 2006.173.05:41:58.45#ibcon#end of sib2, iclass 39, count 0 2006.173.05:41:58.45#ibcon#*mode == 0, iclass 39, count 0 2006.173.05:41:58.45#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.05:41:58.45#ibcon#[27=USB\r\n] 2006.173.05:41:58.45#ibcon#*before write, iclass 39, count 0 2006.173.05:41:58.45#ibcon#enter sib2, iclass 39, count 0 2006.173.05:41:58.45#ibcon#flushed, iclass 39, count 0 2006.173.05:41:58.45#ibcon#about to write, iclass 39, count 0 2006.173.05:41:58.45#ibcon#wrote, iclass 39, count 0 2006.173.05:41:58.45#ibcon#about to read 3, iclass 39, count 0 2006.173.05:41:58.48#ibcon#read 3, iclass 39, count 0 2006.173.05:41:58.48#ibcon#about to read 4, iclass 39, count 0 2006.173.05:41:58.48#ibcon#read 4, iclass 39, count 0 2006.173.05:41:58.48#ibcon#about to read 5, iclass 39, count 0 2006.173.05:41:58.48#ibcon#read 5, iclass 39, count 0 2006.173.05:41:58.48#ibcon#about to read 6, iclass 39, count 0 2006.173.05:41:58.48#ibcon#read 6, iclass 39, count 0 2006.173.05:41:58.48#ibcon#end of sib2, iclass 39, count 0 2006.173.05:41:58.48#ibcon#*after write, iclass 39, count 0 2006.173.05:41:58.48#ibcon#*before return 0, iclass 39, count 0 2006.173.05:41:58.48#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.05:41:58.48#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.05:41:58.48#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.05:41:58.48#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.05:41:58.48$vck44/vblo=3,649.99 2006.173.05:41:58.48#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.05:41:58.48#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.05:41:58.48#ibcon#ireg 17 cls_cnt 0 2006.173.05:41:58.48#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.05:41:58.48#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.05:41:58.48#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.05:41:58.48#ibcon#enter wrdev, iclass 3, count 0 2006.173.05:41:58.48#ibcon#first serial, iclass 3, count 0 2006.173.05:41:58.48#ibcon#enter sib2, iclass 3, count 0 2006.173.05:41:58.48#ibcon#flushed, iclass 3, count 0 2006.173.05:41:58.48#ibcon#about to write, iclass 3, count 0 2006.173.05:41:58.48#ibcon#wrote, iclass 3, count 0 2006.173.05:41:58.48#ibcon#about to read 3, iclass 3, count 0 2006.173.05:41:58.50#ibcon#read 3, iclass 3, count 0 2006.173.05:41:58.50#ibcon#about to read 4, iclass 3, count 0 2006.173.05:41:58.50#ibcon#read 4, iclass 3, count 0 2006.173.05:41:58.50#ibcon#about to read 5, iclass 3, count 0 2006.173.05:41:58.50#ibcon#read 5, iclass 3, count 0 2006.173.05:41:58.50#ibcon#about to read 6, iclass 3, count 0 2006.173.05:41:58.50#ibcon#read 6, iclass 3, count 0 2006.173.05:41:58.50#ibcon#end of sib2, iclass 3, count 0 2006.173.05:41:58.50#ibcon#*mode == 0, iclass 3, count 0 2006.173.05:41:58.50#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.05:41:58.50#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.05:41:58.50#ibcon#*before write, iclass 3, count 0 2006.173.05:41:58.50#ibcon#enter sib2, iclass 3, count 0 2006.173.05:41:58.50#ibcon#flushed, iclass 3, count 0 2006.173.05:41:58.50#ibcon#about to write, iclass 3, count 0 2006.173.05:41:58.50#ibcon#wrote, iclass 3, count 0 2006.173.05:41:58.50#ibcon#about to read 3, iclass 3, count 0 2006.173.05:41:58.54#ibcon#read 3, iclass 3, count 0 2006.173.05:41:58.54#ibcon#about to read 4, iclass 3, count 0 2006.173.05:41:58.54#ibcon#read 4, iclass 3, count 0 2006.173.05:41:58.54#ibcon#about to read 5, iclass 3, count 0 2006.173.05:41:58.54#ibcon#read 5, iclass 3, count 0 2006.173.05:41:58.54#ibcon#about to read 6, iclass 3, count 0 2006.173.05:41:58.54#ibcon#read 6, iclass 3, count 0 2006.173.05:41:58.54#ibcon#end of sib2, iclass 3, count 0 2006.173.05:41:58.54#ibcon#*after write, iclass 3, count 0 2006.173.05:41:58.54#ibcon#*before return 0, iclass 3, count 0 2006.173.05:41:58.54#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.05:41:58.54#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.05:41:58.54#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.05:41:58.54#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.05:41:58.54$vck44/vb=3,4 2006.173.05:41:58.54#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.05:41:58.54#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.05:41:58.54#ibcon#ireg 11 cls_cnt 2 2006.173.05:41:58.54#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.05:41:58.60#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.05:41:58.60#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.05:41:58.60#ibcon#enter wrdev, iclass 5, count 2 2006.173.05:41:58.60#ibcon#first serial, iclass 5, count 2 2006.173.05:41:58.60#ibcon#enter sib2, iclass 5, count 2 2006.173.05:41:58.60#ibcon#flushed, iclass 5, count 2 2006.173.05:41:58.60#ibcon#about to write, iclass 5, count 2 2006.173.05:41:58.60#ibcon#wrote, iclass 5, count 2 2006.173.05:41:58.60#ibcon#about to read 3, iclass 5, count 2 2006.173.05:41:58.62#ibcon#read 3, iclass 5, count 2 2006.173.05:41:58.62#ibcon#about to read 4, iclass 5, count 2 2006.173.05:41:58.62#ibcon#read 4, iclass 5, count 2 2006.173.05:41:58.62#ibcon#about to read 5, iclass 5, count 2 2006.173.05:41:58.62#ibcon#read 5, iclass 5, count 2 2006.173.05:41:58.62#ibcon#about to read 6, iclass 5, count 2 2006.173.05:41:58.62#ibcon#read 6, iclass 5, count 2 2006.173.05:41:58.62#ibcon#end of sib2, iclass 5, count 2 2006.173.05:41:58.62#ibcon#*mode == 0, iclass 5, count 2 2006.173.05:41:58.62#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.05:41:58.62#ibcon#[27=AT03-04\r\n] 2006.173.05:41:58.62#ibcon#*before write, iclass 5, count 2 2006.173.05:41:58.62#ibcon#enter sib2, iclass 5, count 2 2006.173.05:41:58.62#ibcon#flushed, iclass 5, count 2 2006.173.05:41:58.62#ibcon#about to write, iclass 5, count 2 2006.173.05:41:58.62#ibcon#wrote, iclass 5, count 2 2006.173.05:41:58.62#ibcon#about to read 3, iclass 5, count 2 2006.173.05:41:58.65#ibcon#read 3, iclass 5, count 2 2006.173.05:41:58.65#ibcon#about to read 4, iclass 5, count 2 2006.173.05:41:58.65#ibcon#read 4, iclass 5, count 2 2006.173.05:41:58.65#ibcon#about to read 5, iclass 5, count 2 2006.173.05:41:58.65#ibcon#read 5, iclass 5, count 2 2006.173.05:41:58.65#ibcon#about to read 6, iclass 5, count 2 2006.173.05:41:58.65#ibcon#read 6, iclass 5, count 2 2006.173.05:41:58.65#ibcon#end of sib2, iclass 5, count 2 2006.173.05:41:58.65#ibcon#*after write, iclass 5, count 2 2006.173.05:41:58.65#ibcon#*before return 0, iclass 5, count 2 2006.173.05:41:58.65#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.05:41:58.65#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.05:41:58.65#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.05:41:58.65#ibcon#ireg 7 cls_cnt 0 2006.173.05:41:58.65#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.05:41:58.77#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.05:41:58.77#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.05:41:58.77#ibcon#enter wrdev, iclass 5, count 0 2006.173.05:41:58.77#ibcon#first serial, iclass 5, count 0 2006.173.05:41:58.77#ibcon#enter sib2, iclass 5, count 0 2006.173.05:41:58.77#ibcon#flushed, iclass 5, count 0 2006.173.05:41:58.77#ibcon#about to write, iclass 5, count 0 2006.173.05:41:58.77#ibcon#wrote, iclass 5, count 0 2006.173.05:41:58.77#ibcon#about to read 3, iclass 5, count 0 2006.173.05:41:58.79#ibcon#read 3, iclass 5, count 0 2006.173.05:41:58.79#ibcon#about to read 4, iclass 5, count 0 2006.173.05:41:58.79#ibcon#read 4, iclass 5, count 0 2006.173.05:41:58.79#ibcon#about to read 5, iclass 5, count 0 2006.173.05:41:58.79#ibcon#read 5, iclass 5, count 0 2006.173.05:41:58.79#ibcon#about to read 6, iclass 5, count 0 2006.173.05:41:58.79#ibcon#read 6, iclass 5, count 0 2006.173.05:41:58.79#ibcon#end of sib2, iclass 5, count 0 2006.173.05:41:58.79#ibcon#*mode == 0, iclass 5, count 0 2006.173.05:41:58.79#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.05:41:58.79#ibcon#[27=USB\r\n] 2006.173.05:41:58.79#ibcon#*before write, iclass 5, count 0 2006.173.05:41:58.79#ibcon#enter sib2, iclass 5, count 0 2006.173.05:41:58.79#ibcon#flushed, iclass 5, count 0 2006.173.05:41:58.79#ibcon#about to write, iclass 5, count 0 2006.173.05:41:58.79#ibcon#wrote, iclass 5, count 0 2006.173.05:41:58.79#ibcon#about to read 3, iclass 5, count 0 2006.173.05:41:58.82#ibcon#read 3, iclass 5, count 0 2006.173.05:41:58.82#ibcon#about to read 4, iclass 5, count 0 2006.173.05:41:58.82#ibcon#read 4, iclass 5, count 0 2006.173.05:41:58.82#ibcon#about to read 5, iclass 5, count 0 2006.173.05:41:58.82#ibcon#read 5, iclass 5, count 0 2006.173.05:41:58.82#ibcon#about to read 6, iclass 5, count 0 2006.173.05:41:58.82#ibcon#read 6, iclass 5, count 0 2006.173.05:41:58.82#ibcon#end of sib2, iclass 5, count 0 2006.173.05:41:58.82#ibcon#*after write, iclass 5, count 0 2006.173.05:41:58.82#ibcon#*before return 0, iclass 5, count 0 2006.173.05:41:58.82#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.05:41:58.82#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.05:41:58.82#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.05:41:58.82#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.05:41:58.82$vck44/vblo=4,679.99 2006.173.05:41:58.82#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.05:41:58.82#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.05:41:58.82#ibcon#ireg 17 cls_cnt 0 2006.173.05:41:58.82#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.05:41:58.82#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.05:41:58.82#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.05:41:58.82#ibcon#enter wrdev, iclass 7, count 0 2006.173.05:41:58.82#ibcon#first serial, iclass 7, count 0 2006.173.05:41:58.82#ibcon#enter sib2, iclass 7, count 0 2006.173.05:41:58.82#ibcon#flushed, iclass 7, count 0 2006.173.05:41:58.82#ibcon#about to write, iclass 7, count 0 2006.173.05:41:58.82#ibcon#wrote, iclass 7, count 0 2006.173.05:41:58.82#ibcon#about to read 3, iclass 7, count 0 2006.173.05:41:58.84#ibcon#read 3, iclass 7, count 0 2006.173.05:41:58.84#ibcon#about to read 4, iclass 7, count 0 2006.173.05:41:58.84#ibcon#read 4, iclass 7, count 0 2006.173.05:41:58.84#ibcon#about to read 5, iclass 7, count 0 2006.173.05:41:58.84#ibcon#read 5, iclass 7, count 0 2006.173.05:41:58.84#ibcon#about to read 6, iclass 7, count 0 2006.173.05:41:58.84#ibcon#read 6, iclass 7, count 0 2006.173.05:41:58.84#ibcon#end of sib2, iclass 7, count 0 2006.173.05:41:58.84#ibcon#*mode == 0, iclass 7, count 0 2006.173.05:41:58.84#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.05:41:58.84#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.05:41:58.84#ibcon#*before write, iclass 7, count 0 2006.173.05:41:58.84#ibcon#enter sib2, iclass 7, count 0 2006.173.05:41:58.84#ibcon#flushed, iclass 7, count 0 2006.173.05:41:58.84#ibcon#about to write, iclass 7, count 0 2006.173.05:41:58.84#ibcon#wrote, iclass 7, count 0 2006.173.05:41:58.84#ibcon#about to read 3, iclass 7, count 0 2006.173.05:41:58.88#ibcon#read 3, iclass 7, count 0 2006.173.05:41:58.88#ibcon#about to read 4, iclass 7, count 0 2006.173.05:41:58.88#ibcon#read 4, iclass 7, count 0 2006.173.05:41:58.88#ibcon#about to read 5, iclass 7, count 0 2006.173.05:41:58.88#ibcon#read 5, iclass 7, count 0 2006.173.05:41:58.88#ibcon#about to read 6, iclass 7, count 0 2006.173.05:41:58.88#ibcon#read 6, iclass 7, count 0 2006.173.05:41:58.88#ibcon#end of sib2, iclass 7, count 0 2006.173.05:41:58.88#ibcon#*after write, iclass 7, count 0 2006.173.05:41:58.88#ibcon#*before return 0, iclass 7, count 0 2006.173.05:41:58.88#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.05:41:58.88#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.05:41:58.88#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.05:41:58.88#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.05:41:58.88$vck44/vb=4,4 2006.173.05:41:58.88#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.05:41:58.88#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.05:41:58.88#ibcon#ireg 11 cls_cnt 2 2006.173.05:41:58.88#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.05:41:58.94#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.05:41:58.94#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.05:41:58.94#ibcon#enter wrdev, iclass 11, count 2 2006.173.05:41:58.94#ibcon#first serial, iclass 11, count 2 2006.173.05:41:58.94#ibcon#enter sib2, iclass 11, count 2 2006.173.05:41:58.94#ibcon#flushed, iclass 11, count 2 2006.173.05:41:58.94#ibcon#about to write, iclass 11, count 2 2006.173.05:41:58.94#ibcon#wrote, iclass 11, count 2 2006.173.05:41:58.94#ibcon#about to read 3, iclass 11, count 2 2006.173.05:41:58.96#ibcon#read 3, iclass 11, count 2 2006.173.05:41:58.96#ibcon#about to read 4, iclass 11, count 2 2006.173.05:41:58.96#ibcon#read 4, iclass 11, count 2 2006.173.05:41:58.96#ibcon#about to read 5, iclass 11, count 2 2006.173.05:41:58.96#ibcon#read 5, iclass 11, count 2 2006.173.05:41:58.96#ibcon#about to read 6, iclass 11, count 2 2006.173.05:41:58.96#ibcon#read 6, iclass 11, count 2 2006.173.05:41:58.96#ibcon#end of sib2, iclass 11, count 2 2006.173.05:41:58.96#ibcon#*mode == 0, iclass 11, count 2 2006.173.05:41:58.96#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.05:41:58.96#ibcon#[27=AT04-04\r\n] 2006.173.05:41:58.96#ibcon#*before write, iclass 11, count 2 2006.173.05:41:58.96#ibcon#enter sib2, iclass 11, count 2 2006.173.05:41:58.96#ibcon#flushed, iclass 11, count 2 2006.173.05:41:58.96#ibcon#about to write, iclass 11, count 2 2006.173.05:41:58.96#ibcon#wrote, iclass 11, count 2 2006.173.05:41:58.96#ibcon#about to read 3, iclass 11, count 2 2006.173.05:41:58.99#ibcon#read 3, iclass 11, count 2 2006.173.05:41:58.99#ibcon#about to read 4, iclass 11, count 2 2006.173.05:41:58.99#ibcon#read 4, iclass 11, count 2 2006.173.05:41:58.99#ibcon#about to read 5, iclass 11, count 2 2006.173.05:41:58.99#ibcon#read 5, iclass 11, count 2 2006.173.05:41:58.99#ibcon#about to read 6, iclass 11, count 2 2006.173.05:41:58.99#ibcon#read 6, iclass 11, count 2 2006.173.05:41:58.99#ibcon#end of sib2, iclass 11, count 2 2006.173.05:41:58.99#ibcon#*after write, iclass 11, count 2 2006.173.05:41:58.99#ibcon#*before return 0, iclass 11, count 2 2006.173.05:41:58.99#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.05:41:58.99#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.05:41:58.99#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.05:41:58.99#ibcon#ireg 7 cls_cnt 0 2006.173.05:41:58.99#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.05:41:59.11#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.05:41:59.11#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.05:41:59.11#ibcon#enter wrdev, iclass 11, count 0 2006.173.05:41:59.11#ibcon#first serial, iclass 11, count 0 2006.173.05:41:59.11#ibcon#enter sib2, iclass 11, count 0 2006.173.05:41:59.11#ibcon#flushed, iclass 11, count 0 2006.173.05:41:59.11#ibcon#about to write, iclass 11, count 0 2006.173.05:41:59.11#ibcon#wrote, iclass 11, count 0 2006.173.05:41:59.11#ibcon#about to read 3, iclass 11, count 0 2006.173.05:41:59.13#ibcon#read 3, iclass 11, count 0 2006.173.05:41:59.13#ibcon#about to read 4, iclass 11, count 0 2006.173.05:41:59.13#ibcon#read 4, iclass 11, count 0 2006.173.05:41:59.13#ibcon#about to read 5, iclass 11, count 0 2006.173.05:41:59.13#ibcon#read 5, iclass 11, count 0 2006.173.05:41:59.13#ibcon#about to read 6, iclass 11, count 0 2006.173.05:41:59.13#ibcon#read 6, iclass 11, count 0 2006.173.05:41:59.13#ibcon#end of sib2, iclass 11, count 0 2006.173.05:41:59.13#ibcon#*mode == 0, iclass 11, count 0 2006.173.05:41:59.13#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.05:41:59.13#ibcon#[27=USB\r\n] 2006.173.05:41:59.13#ibcon#*before write, iclass 11, count 0 2006.173.05:41:59.13#ibcon#enter sib2, iclass 11, count 0 2006.173.05:41:59.13#ibcon#flushed, iclass 11, count 0 2006.173.05:41:59.13#ibcon#about to write, iclass 11, count 0 2006.173.05:41:59.13#ibcon#wrote, iclass 11, count 0 2006.173.05:41:59.13#ibcon#about to read 3, iclass 11, count 0 2006.173.05:41:59.16#ibcon#read 3, iclass 11, count 0 2006.173.05:41:59.16#ibcon#about to read 4, iclass 11, count 0 2006.173.05:41:59.16#ibcon#read 4, iclass 11, count 0 2006.173.05:41:59.16#ibcon#about to read 5, iclass 11, count 0 2006.173.05:41:59.16#ibcon#read 5, iclass 11, count 0 2006.173.05:41:59.16#ibcon#about to read 6, iclass 11, count 0 2006.173.05:41:59.16#ibcon#read 6, iclass 11, count 0 2006.173.05:41:59.16#ibcon#end of sib2, iclass 11, count 0 2006.173.05:41:59.16#ibcon#*after write, iclass 11, count 0 2006.173.05:41:59.16#ibcon#*before return 0, iclass 11, count 0 2006.173.05:41:59.16#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.05:41:59.16#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.05:41:59.16#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.05:41:59.16#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.05:41:59.16$vck44/vblo=5,709.99 2006.173.05:41:59.16#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.05:41:59.16#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.05:41:59.16#ibcon#ireg 17 cls_cnt 0 2006.173.05:41:59.16#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.05:41:59.16#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.05:41:59.16#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.05:41:59.16#ibcon#enter wrdev, iclass 13, count 0 2006.173.05:41:59.16#ibcon#first serial, iclass 13, count 0 2006.173.05:41:59.16#ibcon#enter sib2, iclass 13, count 0 2006.173.05:41:59.16#ibcon#flushed, iclass 13, count 0 2006.173.05:41:59.16#ibcon#about to write, iclass 13, count 0 2006.173.05:41:59.16#ibcon#wrote, iclass 13, count 0 2006.173.05:41:59.16#ibcon#about to read 3, iclass 13, count 0 2006.173.05:41:59.18#ibcon#read 3, iclass 13, count 0 2006.173.05:41:59.18#ibcon#about to read 4, iclass 13, count 0 2006.173.05:41:59.18#ibcon#read 4, iclass 13, count 0 2006.173.05:41:59.18#ibcon#about to read 5, iclass 13, count 0 2006.173.05:41:59.18#ibcon#read 5, iclass 13, count 0 2006.173.05:41:59.18#ibcon#about to read 6, iclass 13, count 0 2006.173.05:41:59.18#ibcon#read 6, iclass 13, count 0 2006.173.05:41:59.18#ibcon#end of sib2, iclass 13, count 0 2006.173.05:41:59.18#ibcon#*mode == 0, iclass 13, count 0 2006.173.05:41:59.18#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.05:41:59.18#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.05:41:59.18#ibcon#*before write, iclass 13, count 0 2006.173.05:41:59.18#ibcon#enter sib2, iclass 13, count 0 2006.173.05:41:59.18#ibcon#flushed, iclass 13, count 0 2006.173.05:41:59.18#ibcon#about to write, iclass 13, count 0 2006.173.05:41:59.18#ibcon#wrote, iclass 13, count 0 2006.173.05:41:59.18#ibcon#about to read 3, iclass 13, count 0 2006.173.05:41:59.22#ibcon#read 3, iclass 13, count 0 2006.173.05:41:59.22#ibcon#about to read 4, iclass 13, count 0 2006.173.05:41:59.22#ibcon#read 4, iclass 13, count 0 2006.173.05:41:59.22#ibcon#about to read 5, iclass 13, count 0 2006.173.05:41:59.22#ibcon#read 5, iclass 13, count 0 2006.173.05:41:59.22#ibcon#about to read 6, iclass 13, count 0 2006.173.05:41:59.22#ibcon#read 6, iclass 13, count 0 2006.173.05:41:59.22#ibcon#end of sib2, iclass 13, count 0 2006.173.05:41:59.22#ibcon#*after write, iclass 13, count 0 2006.173.05:41:59.22#ibcon#*before return 0, iclass 13, count 0 2006.173.05:41:59.22#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.05:41:59.22#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.05:41:59.22#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.05:41:59.22#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.05:41:59.22$vck44/vb=5,4 2006.173.05:41:59.22#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.05:41:59.22#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.05:41:59.22#ibcon#ireg 11 cls_cnt 2 2006.173.05:41:59.22#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.05:41:59.28#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.05:41:59.28#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.05:41:59.28#ibcon#enter wrdev, iclass 15, count 2 2006.173.05:41:59.28#ibcon#first serial, iclass 15, count 2 2006.173.05:41:59.28#ibcon#enter sib2, iclass 15, count 2 2006.173.05:41:59.28#ibcon#flushed, iclass 15, count 2 2006.173.05:41:59.28#ibcon#about to write, iclass 15, count 2 2006.173.05:41:59.28#ibcon#wrote, iclass 15, count 2 2006.173.05:41:59.28#ibcon#about to read 3, iclass 15, count 2 2006.173.05:41:59.30#ibcon#read 3, iclass 15, count 2 2006.173.05:41:59.30#ibcon#about to read 4, iclass 15, count 2 2006.173.05:41:59.30#ibcon#read 4, iclass 15, count 2 2006.173.05:41:59.30#ibcon#about to read 5, iclass 15, count 2 2006.173.05:41:59.30#ibcon#read 5, iclass 15, count 2 2006.173.05:41:59.30#ibcon#about to read 6, iclass 15, count 2 2006.173.05:41:59.30#ibcon#read 6, iclass 15, count 2 2006.173.05:41:59.30#ibcon#end of sib2, iclass 15, count 2 2006.173.05:41:59.30#ibcon#*mode == 0, iclass 15, count 2 2006.173.05:41:59.30#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.05:41:59.30#ibcon#[27=AT05-04\r\n] 2006.173.05:41:59.30#ibcon#*before write, iclass 15, count 2 2006.173.05:41:59.30#ibcon#enter sib2, iclass 15, count 2 2006.173.05:41:59.30#ibcon#flushed, iclass 15, count 2 2006.173.05:41:59.30#ibcon#about to write, iclass 15, count 2 2006.173.05:41:59.30#ibcon#wrote, iclass 15, count 2 2006.173.05:41:59.30#ibcon#about to read 3, iclass 15, count 2 2006.173.05:41:59.33#ibcon#read 3, iclass 15, count 2 2006.173.05:41:59.33#ibcon#about to read 4, iclass 15, count 2 2006.173.05:41:59.33#ibcon#read 4, iclass 15, count 2 2006.173.05:41:59.33#ibcon#about to read 5, iclass 15, count 2 2006.173.05:41:59.33#ibcon#read 5, iclass 15, count 2 2006.173.05:41:59.33#ibcon#about to read 6, iclass 15, count 2 2006.173.05:41:59.33#ibcon#read 6, iclass 15, count 2 2006.173.05:41:59.33#ibcon#end of sib2, iclass 15, count 2 2006.173.05:41:59.33#ibcon#*after write, iclass 15, count 2 2006.173.05:41:59.33#ibcon#*before return 0, iclass 15, count 2 2006.173.05:41:59.33#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.05:41:59.33#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.05:41:59.33#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.05:41:59.33#ibcon#ireg 7 cls_cnt 0 2006.173.05:41:59.33#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.05:41:59.45#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.05:41:59.45#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.05:41:59.45#ibcon#enter wrdev, iclass 15, count 0 2006.173.05:41:59.45#ibcon#first serial, iclass 15, count 0 2006.173.05:41:59.45#ibcon#enter sib2, iclass 15, count 0 2006.173.05:41:59.45#ibcon#flushed, iclass 15, count 0 2006.173.05:41:59.45#ibcon#about to write, iclass 15, count 0 2006.173.05:41:59.45#ibcon#wrote, iclass 15, count 0 2006.173.05:41:59.45#ibcon#about to read 3, iclass 15, count 0 2006.173.05:41:59.47#ibcon#read 3, iclass 15, count 0 2006.173.05:41:59.47#ibcon#about to read 4, iclass 15, count 0 2006.173.05:41:59.47#ibcon#read 4, iclass 15, count 0 2006.173.05:41:59.47#ibcon#about to read 5, iclass 15, count 0 2006.173.05:41:59.47#ibcon#read 5, iclass 15, count 0 2006.173.05:41:59.47#ibcon#about to read 6, iclass 15, count 0 2006.173.05:41:59.47#ibcon#read 6, iclass 15, count 0 2006.173.05:41:59.47#ibcon#end of sib2, iclass 15, count 0 2006.173.05:41:59.47#ibcon#*mode == 0, iclass 15, count 0 2006.173.05:41:59.47#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.05:41:59.47#ibcon#[27=USB\r\n] 2006.173.05:41:59.47#ibcon#*before write, iclass 15, count 0 2006.173.05:41:59.47#ibcon#enter sib2, iclass 15, count 0 2006.173.05:41:59.47#ibcon#flushed, iclass 15, count 0 2006.173.05:41:59.47#ibcon#about to write, iclass 15, count 0 2006.173.05:41:59.47#ibcon#wrote, iclass 15, count 0 2006.173.05:41:59.47#ibcon#about to read 3, iclass 15, count 0 2006.173.05:41:59.50#ibcon#read 3, iclass 15, count 0 2006.173.05:41:59.50#ibcon#about to read 4, iclass 15, count 0 2006.173.05:41:59.50#ibcon#read 4, iclass 15, count 0 2006.173.05:41:59.50#ibcon#about to read 5, iclass 15, count 0 2006.173.05:41:59.50#ibcon#read 5, iclass 15, count 0 2006.173.05:41:59.50#ibcon#about to read 6, iclass 15, count 0 2006.173.05:41:59.50#ibcon#read 6, iclass 15, count 0 2006.173.05:41:59.50#ibcon#end of sib2, iclass 15, count 0 2006.173.05:41:59.50#ibcon#*after write, iclass 15, count 0 2006.173.05:41:59.50#ibcon#*before return 0, iclass 15, count 0 2006.173.05:41:59.50#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.05:41:59.50#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.05:41:59.50#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.05:41:59.50#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.05:41:59.50$vck44/vblo=6,719.99 2006.173.05:41:59.50#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.05:41:59.50#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.05:41:59.50#ibcon#ireg 17 cls_cnt 0 2006.173.05:41:59.50#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.05:41:59.50#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.05:41:59.50#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.05:41:59.50#ibcon#enter wrdev, iclass 17, count 0 2006.173.05:41:59.50#ibcon#first serial, iclass 17, count 0 2006.173.05:41:59.50#ibcon#enter sib2, iclass 17, count 0 2006.173.05:41:59.50#ibcon#flushed, iclass 17, count 0 2006.173.05:41:59.50#ibcon#about to write, iclass 17, count 0 2006.173.05:41:59.50#ibcon#wrote, iclass 17, count 0 2006.173.05:41:59.50#ibcon#about to read 3, iclass 17, count 0 2006.173.05:41:59.52#ibcon#read 3, iclass 17, count 0 2006.173.05:41:59.52#ibcon#about to read 4, iclass 17, count 0 2006.173.05:41:59.52#ibcon#read 4, iclass 17, count 0 2006.173.05:41:59.52#ibcon#about to read 5, iclass 17, count 0 2006.173.05:41:59.52#ibcon#read 5, iclass 17, count 0 2006.173.05:41:59.52#ibcon#about to read 6, iclass 17, count 0 2006.173.05:41:59.52#ibcon#read 6, iclass 17, count 0 2006.173.05:41:59.52#ibcon#end of sib2, iclass 17, count 0 2006.173.05:41:59.52#ibcon#*mode == 0, iclass 17, count 0 2006.173.05:41:59.52#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.05:41:59.52#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.05:41:59.52#ibcon#*before write, iclass 17, count 0 2006.173.05:41:59.52#ibcon#enter sib2, iclass 17, count 0 2006.173.05:41:59.52#ibcon#flushed, iclass 17, count 0 2006.173.05:41:59.52#ibcon#about to write, iclass 17, count 0 2006.173.05:41:59.52#ibcon#wrote, iclass 17, count 0 2006.173.05:41:59.52#ibcon#about to read 3, iclass 17, count 0 2006.173.05:41:59.56#ibcon#read 3, iclass 17, count 0 2006.173.05:41:59.56#ibcon#about to read 4, iclass 17, count 0 2006.173.05:41:59.56#ibcon#read 4, iclass 17, count 0 2006.173.05:41:59.56#ibcon#about to read 5, iclass 17, count 0 2006.173.05:41:59.56#ibcon#read 5, iclass 17, count 0 2006.173.05:41:59.56#ibcon#about to read 6, iclass 17, count 0 2006.173.05:41:59.56#ibcon#read 6, iclass 17, count 0 2006.173.05:41:59.56#ibcon#end of sib2, iclass 17, count 0 2006.173.05:41:59.56#ibcon#*after write, iclass 17, count 0 2006.173.05:41:59.56#ibcon#*before return 0, iclass 17, count 0 2006.173.05:41:59.56#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.05:41:59.56#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.05:41:59.56#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.05:41:59.56#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.05:41:59.56$vck44/vb=6,4 2006.173.05:41:59.56#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.05:41:59.56#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.05:41:59.56#ibcon#ireg 11 cls_cnt 2 2006.173.05:41:59.56#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.05:41:59.62#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.05:41:59.62#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.05:41:59.62#ibcon#enter wrdev, iclass 19, count 2 2006.173.05:41:59.62#ibcon#first serial, iclass 19, count 2 2006.173.05:41:59.62#ibcon#enter sib2, iclass 19, count 2 2006.173.05:41:59.62#ibcon#flushed, iclass 19, count 2 2006.173.05:41:59.62#ibcon#about to write, iclass 19, count 2 2006.173.05:41:59.62#ibcon#wrote, iclass 19, count 2 2006.173.05:41:59.62#ibcon#about to read 3, iclass 19, count 2 2006.173.05:41:59.64#ibcon#read 3, iclass 19, count 2 2006.173.05:41:59.64#ibcon#about to read 4, iclass 19, count 2 2006.173.05:41:59.64#ibcon#read 4, iclass 19, count 2 2006.173.05:41:59.64#ibcon#about to read 5, iclass 19, count 2 2006.173.05:41:59.64#ibcon#read 5, iclass 19, count 2 2006.173.05:41:59.64#ibcon#about to read 6, iclass 19, count 2 2006.173.05:41:59.64#ibcon#read 6, iclass 19, count 2 2006.173.05:41:59.64#ibcon#end of sib2, iclass 19, count 2 2006.173.05:41:59.64#ibcon#*mode == 0, iclass 19, count 2 2006.173.05:41:59.64#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.05:41:59.64#ibcon#[27=AT06-04\r\n] 2006.173.05:41:59.64#ibcon#*before write, iclass 19, count 2 2006.173.05:41:59.64#ibcon#enter sib2, iclass 19, count 2 2006.173.05:41:59.64#ibcon#flushed, iclass 19, count 2 2006.173.05:41:59.64#ibcon#about to write, iclass 19, count 2 2006.173.05:41:59.64#ibcon#wrote, iclass 19, count 2 2006.173.05:41:59.64#ibcon#about to read 3, iclass 19, count 2 2006.173.05:41:59.67#ibcon#read 3, iclass 19, count 2 2006.173.05:41:59.67#ibcon#about to read 4, iclass 19, count 2 2006.173.05:41:59.67#ibcon#read 4, iclass 19, count 2 2006.173.05:41:59.67#ibcon#about to read 5, iclass 19, count 2 2006.173.05:41:59.67#ibcon#read 5, iclass 19, count 2 2006.173.05:41:59.67#ibcon#about to read 6, iclass 19, count 2 2006.173.05:41:59.67#ibcon#read 6, iclass 19, count 2 2006.173.05:41:59.67#ibcon#end of sib2, iclass 19, count 2 2006.173.05:41:59.67#ibcon#*after write, iclass 19, count 2 2006.173.05:41:59.67#ibcon#*before return 0, iclass 19, count 2 2006.173.05:41:59.67#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.05:41:59.67#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.05:41:59.67#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.05:41:59.67#ibcon#ireg 7 cls_cnt 0 2006.173.05:41:59.67#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.05:41:59.79#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.05:41:59.79#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.05:41:59.79#ibcon#enter wrdev, iclass 19, count 0 2006.173.05:41:59.79#ibcon#first serial, iclass 19, count 0 2006.173.05:41:59.79#ibcon#enter sib2, iclass 19, count 0 2006.173.05:41:59.79#ibcon#flushed, iclass 19, count 0 2006.173.05:41:59.79#ibcon#about to write, iclass 19, count 0 2006.173.05:41:59.79#ibcon#wrote, iclass 19, count 0 2006.173.05:41:59.79#ibcon#about to read 3, iclass 19, count 0 2006.173.05:41:59.81#ibcon#read 3, iclass 19, count 0 2006.173.05:41:59.81#ibcon#about to read 4, iclass 19, count 0 2006.173.05:41:59.81#ibcon#read 4, iclass 19, count 0 2006.173.05:41:59.81#ibcon#about to read 5, iclass 19, count 0 2006.173.05:41:59.81#ibcon#read 5, iclass 19, count 0 2006.173.05:41:59.81#ibcon#about to read 6, iclass 19, count 0 2006.173.05:41:59.81#ibcon#read 6, iclass 19, count 0 2006.173.05:41:59.81#ibcon#end of sib2, iclass 19, count 0 2006.173.05:41:59.81#ibcon#*mode == 0, iclass 19, count 0 2006.173.05:41:59.81#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.05:41:59.81#ibcon#[27=USB\r\n] 2006.173.05:41:59.81#ibcon#*before write, iclass 19, count 0 2006.173.05:41:59.81#ibcon#enter sib2, iclass 19, count 0 2006.173.05:41:59.81#ibcon#flushed, iclass 19, count 0 2006.173.05:41:59.81#ibcon#about to write, iclass 19, count 0 2006.173.05:41:59.81#ibcon#wrote, iclass 19, count 0 2006.173.05:41:59.81#ibcon#about to read 3, iclass 19, count 0 2006.173.05:41:59.84#ibcon#read 3, iclass 19, count 0 2006.173.05:41:59.84#ibcon#about to read 4, iclass 19, count 0 2006.173.05:41:59.84#ibcon#read 4, iclass 19, count 0 2006.173.05:41:59.84#ibcon#about to read 5, iclass 19, count 0 2006.173.05:41:59.84#ibcon#read 5, iclass 19, count 0 2006.173.05:41:59.84#ibcon#about to read 6, iclass 19, count 0 2006.173.05:41:59.84#ibcon#read 6, iclass 19, count 0 2006.173.05:41:59.84#ibcon#end of sib2, iclass 19, count 0 2006.173.05:41:59.84#ibcon#*after write, iclass 19, count 0 2006.173.05:41:59.84#ibcon#*before return 0, iclass 19, count 0 2006.173.05:41:59.84#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.05:41:59.84#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.05:41:59.84#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.05:41:59.84#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.05:41:59.84$vck44/vblo=7,734.99 2006.173.05:41:59.84#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.05:41:59.84#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.05:41:59.84#ibcon#ireg 17 cls_cnt 0 2006.173.05:41:59.84#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.05:41:59.84#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.05:41:59.84#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.05:41:59.84#ibcon#enter wrdev, iclass 21, count 0 2006.173.05:41:59.84#ibcon#first serial, iclass 21, count 0 2006.173.05:41:59.84#ibcon#enter sib2, iclass 21, count 0 2006.173.05:41:59.84#ibcon#flushed, iclass 21, count 0 2006.173.05:41:59.84#ibcon#about to write, iclass 21, count 0 2006.173.05:41:59.84#ibcon#wrote, iclass 21, count 0 2006.173.05:41:59.84#ibcon#about to read 3, iclass 21, count 0 2006.173.05:41:59.86#ibcon#read 3, iclass 21, count 0 2006.173.05:41:59.86#ibcon#about to read 4, iclass 21, count 0 2006.173.05:41:59.86#ibcon#read 4, iclass 21, count 0 2006.173.05:41:59.86#ibcon#about to read 5, iclass 21, count 0 2006.173.05:41:59.86#ibcon#read 5, iclass 21, count 0 2006.173.05:41:59.86#ibcon#about to read 6, iclass 21, count 0 2006.173.05:41:59.86#ibcon#read 6, iclass 21, count 0 2006.173.05:41:59.86#ibcon#end of sib2, iclass 21, count 0 2006.173.05:41:59.86#ibcon#*mode == 0, iclass 21, count 0 2006.173.05:41:59.86#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.05:41:59.86#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.05:41:59.86#ibcon#*before write, iclass 21, count 0 2006.173.05:41:59.86#ibcon#enter sib2, iclass 21, count 0 2006.173.05:41:59.86#ibcon#flushed, iclass 21, count 0 2006.173.05:41:59.86#ibcon#about to write, iclass 21, count 0 2006.173.05:41:59.86#ibcon#wrote, iclass 21, count 0 2006.173.05:41:59.86#ibcon#about to read 3, iclass 21, count 0 2006.173.05:41:59.90#ibcon#read 3, iclass 21, count 0 2006.173.05:41:59.90#ibcon#about to read 4, iclass 21, count 0 2006.173.05:41:59.90#ibcon#read 4, iclass 21, count 0 2006.173.05:41:59.90#ibcon#about to read 5, iclass 21, count 0 2006.173.05:41:59.90#ibcon#read 5, iclass 21, count 0 2006.173.05:41:59.90#ibcon#about to read 6, iclass 21, count 0 2006.173.05:41:59.90#ibcon#read 6, iclass 21, count 0 2006.173.05:41:59.90#ibcon#end of sib2, iclass 21, count 0 2006.173.05:41:59.90#ibcon#*after write, iclass 21, count 0 2006.173.05:41:59.90#ibcon#*before return 0, iclass 21, count 0 2006.173.05:41:59.90#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.05:41:59.90#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.05:41:59.90#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.05:41:59.90#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.05:41:59.90$vck44/vb=7,4 2006.173.05:41:59.90#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.05:41:59.90#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.05:41:59.90#ibcon#ireg 11 cls_cnt 2 2006.173.05:41:59.90#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.05:41:59.96#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.05:41:59.96#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.05:41:59.96#ibcon#enter wrdev, iclass 23, count 2 2006.173.05:41:59.96#ibcon#first serial, iclass 23, count 2 2006.173.05:41:59.96#ibcon#enter sib2, iclass 23, count 2 2006.173.05:41:59.96#ibcon#flushed, iclass 23, count 2 2006.173.05:41:59.96#ibcon#about to write, iclass 23, count 2 2006.173.05:41:59.96#ibcon#wrote, iclass 23, count 2 2006.173.05:41:59.96#ibcon#about to read 3, iclass 23, count 2 2006.173.05:41:59.98#ibcon#read 3, iclass 23, count 2 2006.173.05:41:59.98#ibcon#about to read 4, iclass 23, count 2 2006.173.05:41:59.98#ibcon#read 4, iclass 23, count 2 2006.173.05:41:59.98#ibcon#about to read 5, iclass 23, count 2 2006.173.05:41:59.98#ibcon#read 5, iclass 23, count 2 2006.173.05:41:59.98#ibcon#about to read 6, iclass 23, count 2 2006.173.05:41:59.98#ibcon#read 6, iclass 23, count 2 2006.173.05:41:59.98#ibcon#end of sib2, iclass 23, count 2 2006.173.05:41:59.98#ibcon#*mode == 0, iclass 23, count 2 2006.173.05:41:59.98#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.05:41:59.98#ibcon#[27=AT07-04\r\n] 2006.173.05:41:59.98#ibcon#*before write, iclass 23, count 2 2006.173.05:41:59.98#ibcon#enter sib2, iclass 23, count 2 2006.173.05:41:59.98#ibcon#flushed, iclass 23, count 2 2006.173.05:41:59.98#ibcon#about to write, iclass 23, count 2 2006.173.05:41:59.98#ibcon#wrote, iclass 23, count 2 2006.173.05:41:59.98#ibcon#about to read 3, iclass 23, count 2 2006.173.05:42:00.01#ibcon#read 3, iclass 23, count 2 2006.173.05:42:00.01#ibcon#about to read 4, iclass 23, count 2 2006.173.05:42:00.01#ibcon#read 4, iclass 23, count 2 2006.173.05:42:00.01#ibcon#about to read 5, iclass 23, count 2 2006.173.05:42:00.01#ibcon#read 5, iclass 23, count 2 2006.173.05:42:00.01#ibcon#about to read 6, iclass 23, count 2 2006.173.05:42:00.01#ibcon#read 6, iclass 23, count 2 2006.173.05:42:00.01#ibcon#end of sib2, iclass 23, count 2 2006.173.05:42:00.01#ibcon#*after write, iclass 23, count 2 2006.173.05:42:00.01#ibcon#*before return 0, iclass 23, count 2 2006.173.05:42:00.01#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.05:42:00.01#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.05:42:00.01#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.05:42:00.01#ibcon#ireg 7 cls_cnt 0 2006.173.05:42:00.01#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.05:42:00.13#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.05:42:00.13#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.05:42:00.13#ibcon#enter wrdev, iclass 23, count 0 2006.173.05:42:00.13#ibcon#first serial, iclass 23, count 0 2006.173.05:42:00.13#ibcon#enter sib2, iclass 23, count 0 2006.173.05:42:00.13#ibcon#flushed, iclass 23, count 0 2006.173.05:42:00.13#ibcon#about to write, iclass 23, count 0 2006.173.05:42:00.13#ibcon#wrote, iclass 23, count 0 2006.173.05:42:00.13#ibcon#about to read 3, iclass 23, count 0 2006.173.05:42:00.15#ibcon#read 3, iclass 23, count 0 2006.173.05:42:00.15#ibcon#about to read 4, iclass 23, count 0 2006.173.05:42:00.15#ibcon#read 4, iclass 23, count 0 2006.173.05:42:00.15#ibcon#about to read 5, iclass 23, count 0 2006.173.05:42:00.15#ibcon#read 5, iclass 23, count 0 2006.173.05:42:00.15#ibcon#about to read 6, iclass 23, count 0 2006.173.05:42:00.15#ibcon#read 6, iclass 23, count 0 2006.173.05:42:00.15#ibcon#end of sib2, iclass 23, count 0 2006.173.05:42:00.15#ibcon#*mode == 0, iclass 23, count 0 2006.173.05:42:00.15#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.05:42:00.15#ibcon#[27=USB\r\n] 2006.173.05:42:00.15#ibcon#*before write, iclass 23, count 0 2006.173.05:42:00.15#ibcon#enter sib2, iclass 23, count 0 2006.173.05:42:00.15#ibcon#flushed, iclass 23, count 0 2006.173.05:42:00.15#ibcon#about to write, iclass 23, count 0 2006.173.05:42:00.15#ibcon#wrote, iclass 23, count 0 2006.173.05:42:00.15#ibcon#about to read 3, iclass 23, count 0 2006.173.05:42:00.18#ibcon#read 3, iclass 23, count 0 2006.173.05:42:00.18#ibcon#about to read 4, iclass 23, count 0 2006.173.05:42:00.18#ibcon#read 4, iclass 23, count 0 2006.173.05:42:00.18#ibcon#about to read 5, iclass 23, count 0 2006.173.05:42:00.18#ibcon#read 5, iclass 23, count 0 2006.173.05:42:00.18#ibcon#about to read 6, iclass 23, count 0 2006.173.05:42:00.18#ibcon#read 6, iclass 23, count 0 2006.173.05:42:00.18#ibcon#end of sib2, iclass 23, count 0 2006.173.05:42:00.18#ibcon#*after write, iclass 23, count 0 2006.173.05:42:00.18#ibcon#*before return 0, iclass 23, count 0 2006.173.05:42:00.18#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.05:42:00.18#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.05:42:00.18#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.05:42:00.18#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.05:42:00.18$vck44/vblo=8,744.99 2006.173.05:42:00.18#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.05:42:00.18#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.05:42:00.18#ibcon#ireg 17 cls_cnt 0 2006.173.05:42:00.18#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.05:42:00.18#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.05:42:00.18#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.05:42:00.18#ibcon#enter wrdev, iclass 25, count 0 2006.173.05:42:00.18#ibcon#first serial, iclass 25, count 0 2006.173.05:42:00.18#ibcon#enter sib2, iclass 25, count 0 2006.173.05:42:00.18#ibcon#flushed, iclass 25, count 0 2006.173.05:42:00.18#ibcon#about to write, iclass 25, count 0 2006.173.05:42:00.18#ibcon#wrote, iclass 25, count 0 2006.173.05:42:00.18#ibcon#about to read 3, iclass 25, count 0 2006.173.05:42:00.20#ibcon#read 3, iclass 25, count 0 2006.173.05:42:00.20#ibcon#about to read 4, iclass 25, count 0 2006.173.05:42:00.20#ibcon#read 4, iclass 25, count 0 2006.173.05:42:00.20#ibcon#about to read 5, iclass 25, count 0 2006.173.05:42:00.20#ibcon#read 5, iclass 25, count 0 2006.173.05:42:00.20#ibcon#about to read 6, iclass 25, count 0 2006.173.05:42:00.20#ibcon#read 6, iclass 25, count 0 2006.173.05:42:00.20#ibcon#end of sib2, iclass 25, count 0 2006.173.05:42:00.20#ibcon#*mode == 0, iclass 25, count 0 2006.173.05:42:00.20#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.05:42:00.20#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.05:42:00.20#ibcon#*before write, iclass 25, count 0 2006.173.05:42:00.20#ibcon#enter sib2, iclass 25, count 0 2006.173.05:42:00.20#ibcon#flushed, iclass 25, count 0 2006.173.05:42:00.20#ibcon#about to write, iclass 25, count 0 2006.173.05:42:00.20#ibcon#wrote, iclass 25, count 0 2006.173.05:42:00.20#ibcon#about to read 3, iclass 25, count 0 2006.173.05:42:00.24#ibcon#read 3, iclass 25, count 0 2006.173.05:42:00.24#ibcon#about to read 4, iclass 25, count 0 2006.173.05:42:00.24#ibcon#read 4, iclass 25, count 0 2006.173.05:42:00.24#ibcon#about to read 5, iclass 25, count 0 2006.173.05:42:00.24#ibcon#read 5, iclass 25, count 0 2006.173.05:42:00.24#ibcon#about to read 6, iclass 25, count 0 2006.173.05:42:00.24#ibcon#read 6, iclass 25, count 0 2006.173.05:42:00.24#ibcon#end of sib2, iclass 25, count 0 2006.173.05:42:00.24#ibcon#*after write, iclass 25, count 0 2006.173.05:42:00.24#ibcon#*before return 0, iclass 25, count 0 2006.173.05:42:00.24#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.05:42:00.24#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.05:42:00.24#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.05:42:00.24#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.05:42:00.24$vck44/vb=8,4 2006.173.05:42:00.24#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.05:42:00.24#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.05:42:00.24#ibcon#ireg 11 cls_cnt 2 2006.173.05:42:00.24#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.05:42:00.30#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.05:42:00.30#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.05:42:00.30#ibcon#enter wrdev, iclass 27, count 2 2006.173.05:42:00.30#ibcon#first serial, iclass 27, count 2 2006.173.05:42:00.30#ibcon#enter sib2, iclass 27, count 2 2006.173.05:42:00.30#ibcon#flushed, iclass 27, count 2 2006.173.05:42:00.30#ibcon#about to write, iclass 27, count 2 2006.173.05:42:00.30#ibcon#wrote, iclass 27, count 2 2006.173.05:42:00.30#ibcon#about to read 3, iclass 27, count 2 2006.173.05:42:00.32#ibcon#read 3, iclass 27, count 2 2006.173.05:42:00.32#ibcon#about to read 4, iclass 27, count 2 2006.173.05:42:00.32#ibcon#read 4, iclass 27, count 2 2006.173.05:42:00.32#ibcon#about to read 5, iclass 27, count 2 2006.173.05:42:00.32#ibcon#read 5, iclass 27, count 2 2006.173.05:42:00.32#ibcon#about to read 6, iclass 27, count 2 2006.173.05:42:00.32#ibcon#read 6, iclass 27, count 2 2006.173.05:42:00.32#ibcon#end of sib2, iclass 27, count 2 2006.173.05:42:00.32#ibcon#*mode == 0, iclass 27, count 2 2006.173.05:42:00.32#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.05:42:00.32#ibcon#[27=AT08-04\r\n] 2006.173.05:42:00.32#ibcon#*before write, iclass 27, count 2 2006.173.05:42:00.32#ibcon#enter sib2, iclass 27, count 2 2006.173.05:42:00.32#ibcon#flushed, iclass 27, count 2 2006.173.05:42:00.32#ibcon#about to write, iclass 27, count 2 2006.173.05:42:00.32#ibcon#wrote, iclass 27, count 2 2006.173.05:42:00.32#ibcon#about to read 3, iclass 27, count 2 2006.173.05:42:00.35#ibcon#read 3, iclass 27, count 2 2006.173.05:42:00.35#ibcon#about to read 4, iclass 27, count 2 2006.173.05:42:00.35#ibcon#read 4, iclass 27, count 2 2006.173.05:42:00.35#ibcon#about to read 5, iclass 27, count 2 2006.173.05:42:00.35#ibcon#read 5, iclass 27, count 2 2006.173.05:42:00.35#ibcon#about to read 6, iclass 27, count 2 2006.173.05:42:00.35#ibcon#read 6, iclass 27, count 2 2006.173.05:42:00.35#ibcon#end of sib2, iclass 27, count 2 2006.173.05:42:00.35#ibcon#*after write, iclass 27, count 2 2006.173.05:42:00.35#ibcon#*before return 0, iclass 27, count 2 2006.173.05:42:00.35#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.05:42:00.35#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.05:42:00.35#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.05:42:00.35#ibcon#ireg 7 cls_cnt 0 2006.173.05:42:00.35#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.05:42:00.47#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.05:42:00.47#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.05:42:00.47#ibcon#enter wrdev, iclass 27, count 0 2006.173.05:42:00.47#ibcon#first serial, iclass 27, count 0 2006.173.05:42:00.47#ibcon#enter sib2, iclass 27, count 0 2006.173.05:42:00.47#ibcon#flushed, iclass 27, count 0 2006.173.05:42:00.47#ibcon#about to write, iclass 27, count 0 2006.173.05:42:00.47#ibcon#wrote, iclass 27, count 0 2006.173.05:42:00.47#ibcon#about to read 3, iclass 27, count 0 2006.173.05:42:00.49#ibcon#read 3, iclass 27, count 0 2006.173.05:42:00.49#ibcon#about to read 4, iclass 27, count 0 2006.173.05:42:00.49#ibcon#read 4, iclass 27, count 0 2006.173.05:42:00.49#ibcon#about to read 5, iclass 27, count 0 2006.173.05:42:00.49#ibcon#read 5, iclass 27, count 0 2006.173.05:42:00.49#ibcon#about to read 6, iclass 27, count 0 2006.173.05:42:00.49#ibcon#read 6, iclass 27, count 0 2006.173.05:42:00.49#ibcon#end of sib2, iclass 27, count 0 2006.173.05:42:00.49#ibcon#*mode == 0, iclass 27, count 0 2006.173.05:42:00.49#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.05:42:00.49#ibcon#[27=USB\r\n] 2006.173.05:42:00.49#ibcon#*before write, iclass 27, count 0 2006.173.05:42:00.49#ibcon#enter sib2, iclass 27, count 0 2006.173.05:42:00.49#ibcon#flushed, iclass 27, count 0 2006.173.05:42:00.49#ibcon#about to write, iclass 27, count 0 2006.173.05:42:00.49#ibcon#wrote, iclass 27, count 0 2006.173.05:42:00.49#ibcon#about to read 3, iclass 27, count 0 2006.173.05:42:00.52#ibcon#read 3, iclass 27, count 0 2006.173.05:42:00.52#ibcon#about to read 4, iclass 27, count 0 2006.173.05:42:00.52#ibcon#read 4, iclass 27, count 0 2006.173.05:42:00.52#ibcon#about to read 5, iclass 27, count 0 2006.173.05:42:00.52#ibcon#read 5, iclass 27, count 0 2006.173.05:42:00.52#ibcon#about to read 6, iclass 27, count 0 2006.173.05:42:00.52#ibcon#read 6, iclass 27, count 0 2006.173.05:42:00.52#ibcon#end of sib2, iclass 27, count 0 2006.173.05:42:00.52#ibcon#*after write, iclass 27, count 0 2006.173.05:42:00.52#ibcon#*before return 0, iclass 27, count 0 2006.173.05:42:00.52#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.05:42:00.52#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.05:42:00.52#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.05:42:00.52#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.05:42:00.52$vck44/vabw=wide 2006.173.05:42:00.52#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.05:42:00.52#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.05:42:00.52#ibcon#ireg 8 cls_cnt 0 2006.173.05:42:00.52#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.05:42:00.52#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.05:42:00.52#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.05:42:00.52#ibcon#enter wrdev, iclass 29, count 0 2006.173.05:42:00.52#ibcon#first serial, iclass 29, count 0 2006.173.05:42:00.52#ibcon#enter sib2, iclass 29, count 0 2006.173.05:42:00.52#ibcon#flushed, iclass 29, count 0 2006.173.05:42:00.52#ibcon#about to write, iclass 29, count 0 2006.173.05:42:00.52#ibcon#wrote, iclass 29, count 0 2006.173.05:42:00.52#ibcon#about to read 3, iclass 29, count 0 2006.173.05:42:00.54#ibcon#read 3, iclass 29, count 0 2006.173.05:42:00.54#ibcon#about to read 4, iclass 29, count 0 2006.173.05:42:00.54#ibcon#read 4, iclass 29, count 0 2006.173.05:42:00.54#ibcon#about to read 5, iclass 29, count 0 2006.173.05:42:00.54#ibcon#read 5, iclass 29, count 0 2006.173.05:42:00.54#ibcon#about to read 6, iclass 29, count 0 2006.173.05:42:00.54#ibcon#read 6, iclass 29, count 0 2006.173.05:42:00.54#ibcon#end of sib2, iclass 29, count 0 2006.173.05:42:00.54#ibcon#*mode == 0, iclass 29, count 0 2006.173.05:42:00.54#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.05:42:00.54#ibcon#[25=BW32\r\n] 2006.173.05:42:00.54#ibcon#*before write, iclass 29, count 0 2006.173.05:42:00.54#ibcon#enter sib2, iclass 29, count 0 2006.173.05:42:00.54#ibcon#flushed, iclass 29, count 0 2006.173.05:42:00.54#ibcon#about to write, iclass 29, count 0 2006.173.05:42:00.54#ibcon#wrote, iclass 29, count 0 2006.173.05:42:00.54#ibcon#about to read 3, iclass 29, count 0 2006.173.05:42:00.57#ibcon#read 3, iclass 29, count 0 2006.173.05:42:00.57#ibcon#about to read 4, iclass 29, count 0 2006.173.05:42:00.57#ibcon#read 4, iclass 29, count 0 2006.173.05:42:00.57#ibcon#about to read 5, iclass 29, count 0 2006.173.05:42:00.57#ibcon#read 5, iclass 29, count 0 2006.173.05:42:00.57#ibcon#about to read 6, iclass 29, count 0 2006.173.05:42:00.57#ibcon#read 6, iclass 29, count 0 2006.173.05:42:00.57#ibcon#end of sib2, iclass 29, count 0 2006.173.05:42:00.57#ibcon#*after write, iclass 29, count 0 2006.173.05:42:00.57#ibcon#*before return 0, iclass 29, count 0 2006.173.05:42:00.57#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.05:42:00.57#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.05:42:00.57#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.05:42:00.57#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.05:42:00.57$vck44/vbbw=wide 2006.173.05:42:00.57#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.05:42:00.57#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.05:42:00.57#ibcon#ireg 8 cls_cnt 0 2006.173.05:42:00.57#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.05:42:00.64#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.05:42:00.64#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.05:42:00.64#ibcon#enter wrdev, iclass 31, count 0 2006.173.05:42:00.64#ibcon#first serial, iclass 31, count 0 2006.173.05:42:00.64#ibcon#enter sib2, iclass 31, count 0 2006.173.05:42:00.64#ibcon#flushed, iclass 31, count 0 2006.173.05:42:00.64#ibcon#about to write, iclass 31, count 0 2006.173.05:42:00.64#ibcon#wrote, iclass 31, count 0 2006.173.05:42:00.64#ibcon#about to read 3, iclass 31, count 0 2006.173.05:42:00.66#ibcon#read 3, iclass 31, count 0 2006.173.05:42:00.66#ibcon#about to read 4, iclass 31, count 0 2006.173.05:42:00.66#ibcon#read 4, iclass 31, count 0 2006.173.05:42:00.66#ibcon#about to read 5, iclass 31, count 0 2006.173.05:42:00.66#ibcon#read 5, iclass 31, count 0 2006.173.05:42:00.66#ibcon#about to read 6, iclass 31, count 0 2006.173.05:42:00.66#ibcon#read 6, iclass 31, count 0 2006.173.05:42:00.66#ibcon#end of sib2, iclass 31, count 0 2006.173.05:42:00.66#ibcon#*mode == 0, iclass 31, count 0 2006.173.05:42:00.66#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.05:42:00.66#ibcon#[27=BW32\r\n] 2006.173.05:42:00.66#ibcon#*before write, iclass 31, count 0 2006.173.05:42:00.66#ibcon#enter sib2, iclass 31, count 0 2006.173.05:42:00.66#ibcon#flushed, iclass 31, count 0 2006.173.05:42:00.66#ibcon#about to write, iclass 31, count 0 2006.173.05:42:00.66#ibcon#wrote, iclass 31, count 0 2006.173.05:42:00.66#ibcon#about to read 3, iclass 31, count 0 2006.173.05:42:00.69#ibcon#read 3, iclass 31, count 0 2006.173.05:42:00.69#ibcon#about to read 4, iclass 31, count 0 2006.173.05:42:00.69#ibcon#read 4, iclass 31, count 0 2006.173.05:42:00.69#ibcon#about to read 5, iclass 31, count 0 2006.173.05:42:00.69#ibcon#read 5, iclass 31, count 0 2006.173.05:42:00.69#ibcon#about to read 6, iclass 31, count 0 2006.173.05:42:00.69#ibcon#read 6, iclass 31, count 0 2006.173.05:42:00.69#ibcon#end of sib2, iclass 31, count 0 2006.173.05:42:00.69#ibcon#*after write, iclass 31, count 0 2006.173.05:42:00.69#ibcon#*before return 0, iclass 31, count 0 2006.173.05:42:00.69#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.05:42:00.69#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.05:42:00.69#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.05:42:00.69#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.05:42:00.69$setupk4/ifdk4 2006.173.05:42:00.69$ifdk4/lo= 2006.173.05:42:00.69$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.05:42:00.69$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.05:42:00.69$ifdk4/patch= 2006.173.05:42:00.69$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.05:42:00.69$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.05:42:00.69$setupk4/!*+20s 2006.173.05:42:06.25#abcon#<5=/15 0.5 1.2 23.52 781005.3\r\n> 2006.173.05:42:06.27#abcon#{5=INTERFACE CLEAR} 2006.173.05:42:06.33#abcon#[5=S1D000X0/0*\r\n] 2006.173.05:42:15.20$setupk4/"tpicd 2006.173.05:42:15.20$setupk4/echo=off 2006.173.05:42:15.20$setupk4/xlog=off 2006.173.05:42:15.20:!2006.173.05:47:24 2006.173.05:42:34.14#trakl#Source acquired 2006.173.05:42:36.14#flagr#flagr/antenna,acquired 2006.173.05:47:24.00:preob 2006.173.05:47:25.13/onsource/TRACKING 2006.173.05:47:25.13:!2006.173.05:47:34 2006.173.05:47:34.00:"tape 2006.173.05:47:34.00:"st=record 2006.173.05:47:34.00:data_valid=on 2006.173.05:47:34.00:midob 2006.173.05:47:34.13/onsource/TRACKING 2006.173.05:47:34.13/wx/23.58,1005.3,77 2006.173.05:47:34.34/cable/+6.5083E-03 2006.173.05:47:35.43/va/01,07,usb,yes,34,37 2006.173.05:47:35.43/va/02,06,usb,yes,34,35 2006.173.05:47:35.43/va/03,05,usb,yes,44,45 2006.173.05:47:35.43/va/04,06,usb,yes,35,37 2006.173.05:47:35.43/va/05,04,usb,yes,27,28 2006.173.05:47:35.43/va/06,03,usb,yes,38,38 2006.173.05:47:35.43/va/07,04,usb,yes,31,32 2006.173.05:47:35.43/va/08,04,usb,yes,26,32 2006.173.05:47:35.66/valo/01,524.99,yes,locked 2006.173.05:47:35.66/valo/02,534.99,yes,locked 2006.173.05:47:35.66/valo/03,564.99,yes,locked 2006.173.05:47:35.66/valo/04,624.99,yes,locked 2006.173.05:47:35.66/valo/05,734.99,yes,locked 2006.173.05:47:35.66/valo/06,814.99,yes,locked 2006.173.05:47:35.66/valo/07,864.99,yes,locked 2006.173.05:47:35.66/valo/08,884.99,yes,locked 2006.173.05:47:36.75/vb/01,04,usb,yes,29,27 2006.173.05:47:36.75/vb/02,04,usb,yes,31,31 2006.173.05:47:36.75/vb/03,04,usb,yes,28,31 2006.173.05:47:36.75/vb/04,04,usb,yes,33,32 2006.173.05:47:36.75/vb/05,04,usb,yes,25,28 2006.173.05:47:36.75/vb/06,04,usb,yes,30,26 2006.173.05:47:36.75/vb/07,04,usb,yes,29,29 2006.173.05:47:36.75/vb/08,04,usb,yes,27,30 2006.173.05:47:36.98/vblo/01,629.99,yes,locked 2006.173.05:47:36.98/vblo/02,634.99,yes,locked 2006.173.05:47:36.98/vblo/03,649.99,yes,locked 2006.173.05:47:36.98/vblo/04,679.99,yes,locked 2006.173.05:47:36.98/vblo/05,709.99,yes,locked 2006.173.05:47:36.98/vblo/06,719.99,yes,locked 2006.173.05:47:36.98/vblo/07,734.99,yes,locked 2006.173.05:47:36.98/vblo/08,744.99,yes,locked 2006.173.05:47:37.13/vabw/8 2006.173.05:47:37.28/vbbw/8 2006.173.05:47:37.48/xfe/off,on,14.7 2006.173.05:47:37.85/ifatt/23,28,28,28 2006.173.05:47:38.07/fmout-gps/S +4.01E-07 2006.173.05:47:38.11:!2006.173.05:48:24 2006.173.05:48:24.00:data_valid=off 2006.173.05:48:24.00:"et 2006.173.05:48:24.00:!+3s 2006.173.05:48:27.01:"tape 2006.173.05:48:27.01:postob 2006.173.05:48:27.21/cable/+6.5077E-03 2006.173.05:48:27.21/wx/23.59,1005.3,78 2006.173.05:48:28.07/fmout-gps/S +4.01E-07 2006.173.05:48:28.07:scan_name=173-0550,jd0606,60 2006.173.05:48:28.07:source=0727-115,073019.11,-114112.6,2000.0,ccw 2006.173.05:48:29.13#flagr#flagr/antenna,new-source 2006.173.05:48:29.14:checkk5 2006.173.05:48:29.55/chk_autoobs//k5ts1/ autoobs is running! 2006.173.05:48:29.95/chk_autoobs//k5ts2/ autoobs is running! 2006.173.05:48:30.35/chk_autoobs//k5ts3/ autoobs is running! 2006.173.05:48:30.75/chk_autoobs//k5ts4/ autoobs is running! 2006.173.05:48:31.14/chk_obsdata//k5ts1/T1730547??a.dat file size is correct (nominal:200MB, actual:196MB). 2006.173.05:48:31.53/chk_obsdata//k5ts2/T1730547??b.dat file size is correct (nominal:200MB, actual:196MB). 2006.173.05:48:31.93/chk_obsdata//k5ts3/T1730547??c.dat file size is correct (nominal:200MB, actual:196MB). 2006.173.05:48:32.35/chk_obsdata//k5ts4/T1730547??d.dat file size is correct (nominal:200MB, actual:196MB). 2006.173.05:48:33.08/k5log//k5ts1_log_newline 2006.173.05:48:33.79/k5log//k5ts2_log_newline 2006.173.05:48:34.50/k5log//k5ts3_log_newline 2006.173.05:48:35.21/k5log//k5ts4_log_newline 2006.173.05:48:35.23/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.05:48:35.23:setupk4=1 2006.173.05:48:35.23$setupk4/echo=on 2006.173.05:48:35.23$setupk4/pcalon 2006.173.05:48:35.23$pcalon/"no phase cal control is implemented here 2006.173.05:48:35.23$setupk4/"tpicd=stop 2006.173.05:48:35.23$setupk4/"rec=synch_on 2006.173.05:48:35.23$setupk4/"rec_mode=128 2006.173.05:48:35.23$setupk4/!* 2006.173.05:48:35.23$setupk4/recpk4 2006.173.05:48:35.23$recpk4/recpatch= 2006.173.05:48:35.24$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.05:48:35.24$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.05:48:35.24$setupk4/vck44 2006.173.05:48:35.24$vck44/valo=1,524.99 2006.173.05:48:35.24#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.05:48:35.24#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.05:48:35.24#ibcon#ireg 17 cls_cnt 0 2006.173.05:48:35.24#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.05:48:35.24#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.05:48:35.24#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.05:48:35.24#ibcon#enter wrdev, iclass 39, count 0 2006.173.05:48:35.24#ibcon#first serial, iclass 39, count 0 2006.173.05:48:35.24#ibcon#enter sib2, iclass 39, count 0 2006.173.05:48:35.24#ibcon#flushed, iclass 39, count 0 2006.173.05:48:35.24#ibcon#about to write, iclass 39, count 0 2006.173.05:48:35.24#ibcon#wrote, iclass 39, count 0 2006.173.05:48:35.24#ibcon#about to read 3, iclass 39, count 0 2006.173.05:48:35.26#ibcon#read 3, iclass 39, count 0 2006.173.05:48:35.26#ibcon#about to read 4, iclass 39, count 0 2006.173.05:48:35.26#ibcon#read 4, iclass 39, count 0 2006.173.05:48:35.26#ibcon#about to read 5, iclass 39, count 0 2006.173.05:48:35.26#ibcon#read 5, iclass 39, count 0 2006.173.05:48:35.26#ibcon#about to read 6, iclass 39, count 0 2006.173.05:48:35.26#ibcon#read 6, iclass 39, count 0 2006.173.05:48:35.26#ibcon#end of sib2, iclass 39, count 0 2006.173.05:48:35.26#ibcon#*mode == 0, iclass 39, count 0 2006.173.05:48:35.26#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.05:48:35.26#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.05:48:35.26#ibcon#*before write, iclass 39, count 0 2006.173.05:48:35.26#ibcon#enter sib2, iclass 39, count 0 2006.173.05:48:35.26#ibcon#flushed, iclass 39, count 0 2006.173.05:48:35.26#ibcon#about to write, iclass 39, count 0 2006.173.05:48:35.26#ibcon#wrote, iclass 39, count 0 2006.173.05:48:35.26#ibcon#about to read 3, iclass 39, count 0 2006.173.05:48:35.31#ibcon#read 3, iclass 39, count 0 2006.173.05:48:35.31#ibcon#about to read 4, iclass 39, count 0 2006.173.05:48:35.31#ibcon#read 4, iclass 39, count 0 2006.173.05:48:35.31#ibcon#about to read 5, iclass 39, count 0 2006.173.05:48:35.31#ibcon#read 5, iclass 39, count 0 2006.173.05:48:35.31#ibcon#about to read 6, iclass 39, count 0 2006.173.05:48:35.31#ibcon#read 6, iclass 39, count 0 2006.173.05:48:35.31#ibcon#end of sib2, iclass 39, count 0 2006.173.05:48:35.31#ibcon#*after write, iclass 39, count 0 2006.173.05:48:35.31#ibcon#*before return 0, iclass 39, count 0 2006.173.05:48:35.31#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.05:48:35.31#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.05:48:35.31#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.05:48:35.31#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.05:48:35.31$vck44/va=1,7 2006.173.05:48:35.31#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.05:48:35.31#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.05:48:35.31#ibcon#ireg 11 cls_cnt 2 2006.173.05:48:35.31#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.05:48:35.31#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.05:48:35.31#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.05:48:35.31#ibcon#enter wrdev, iclass 3, count 2 2006.173.05:48:35.31#ibcon#first serial, iclass 3, count 2 2006.173.05:48:35.31#ibcon#enter sib2, iclass 3, count 2 2006.173.05:48:35.31#ibcon#flushed, iclass 3, count 2 2006.173.05:48:35.31#ibcon#about to write, iclass 3, count 2 2006.173.05:48:35.31#ibcon#wrote, iclass 3, count 2 2006.173.05:48:35.31#ibcon#about to read 3, iclass 3, count 2 2006.173.05:48:35.33#ibcon#read 3, iclass 3, count 2 2006.173.05:48:35.33#ibcon#about to read 4, iclass 3, count 2 2006.173.05:48:35.33#ibcon#read 4, iclass 3, count 2 2006.173.05:48:35.33#ibcon#about to read 5, iclass 3, count 2 2006.173.05:48:35.33#ibcon#read 5, iclass 3, count 2 2006.173.05:48:35.33#ibcon#about to read 6, iclass 3, count 2 2006.173.05:48:35.33#ibcon#read 6, iclass 3, count 2 2006.173.05:48:35.33#ibcon#end of sib2, iclass 3, count 2 2006.173.05:48:35.33#ibcon#*mode == 0, iclass 3, count 2 2006.173.05:48:35.33#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.05:48:35.33#ibcon#[25=AT01-07\r\n] 2006.173.05:48:35.33#ibcon#*before write, iclass 3, count 2 2006.173.05:48:35.33#ibcon#enter sib2, iclass 3, count 2 2006.173.05:48:35.33#ibcon#flushed, iclass 3, count 2 2006.173.05:48:35.33#ibcon#about to write, iclass 3, count 2 2006.173.05:48:35.33#ibcon#wrote, iclass 3, count 2 2006.173.05:48:35.33#ibcon#about to read 3, iclass 3, count 2 2006.173.05:48:35.36#ibcon#read 3, iclass 3, count 2 2006.173.05:48:35.36#ibcon#about to read 4, iclass 3, count 2 2006.173.05:48:35.36#ibcon#read 4, iclass 3, count 2 2006.173.05:48:35.36#ibcon#about to read 5, iclass 3, count 2 2006.173.05:48:35.36#ibcon#read 5, iclass 3, count 2 2006.173.05:48:35.36#ibcon#about to read 6, iclass 3, count 2 2006.173.05:48:35.36#ibcon#read 6, iclass 3, count 2 2006.173.05:48:35.36#ibcon#end of sib2, iclass 3, count 2 2006.173.05:48:35.36#ibcon#*after write, iclass 3, count 2 2006.173.05:48:35.36#ibcon#*before return 0, iclass 3, count 2 2006.173.05:48:35.36#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.05:48:35.36#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.05:48:35.36#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.05:48:35.36#ibcon#ireg 7 cls_cnt 0 2006.173.05:48:35.36#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.05:48:35.48#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.05:48:35.48#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.05:48:35.48#ibcon#enter wrdev, iclass 3, count 0 2006.173.05:48:35.48#ibcon#first serial, iclass 3, count 0 2006.173.05:48:35.48#ibcon#enter sib2, iclass 3, count 0 2006.173.05:48:35.48#ibcon#flushed, iclass 3, count 0 2006.173.05:48:35.48#ibcon#about to write, iclass 3, count 0 2006.173.05:48:35.48#ibcon#wrote, iclass 3, count 0 2006.173.05:48:35.48#ibcon#about to read 3, iclass 3, count 0 2006.173.05:48:35.50#ibcon#read 3, iclass 3, count 0 2006.173.05:48:35.50#ibcon#about to read 4, iclass 3, count 0 2006.173.05:48:35.50#ibcon#read 4, iclass 3, count 0 2006.173.05:48:35.50#ibcon#about to read 5, iclass 3, count 0 2006.173.05:48:35.50#ibcon#read 5, iclass 3, count 0 2006.173.05:48:35.50#ibcon#about to read 6, iclass 3, count 0 2006.173.05:48:35.50#ibcon#read 6, iclass 3, count 0 2006.173.05:48:35.50#ibcon#end of sib2, iclass 3, count 0 2006.173.05:48:35.50#ibcon#*mode == 0, iclass 3, count 0 2006.173.05:48:35.50#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.05:48:35.50#ibcon#[25=USB\r\n] 2006.173.05:48:35.50#ibcon#*before write, iclass 3, count 0 2006.173.05:48:35.50#ibcon#enter sib2, iclass 3, count 0 2006.173.05:48:35.50#ibcon#flushed, iclass 3, count 0 2006.173.05:48:35.50#ibcon#about to write, iclass 3, count 0 2006.173.05:48:35.50#ibcon#wrote, iclass 3, count 0 2006.173.05:48:35.50#ibcon#about to read 3, iclass 3, count 0 2006.173.05:48:35.53#ibcon#read 3, iclass 3, count 0 2006.173.05:48:35.53#ibcon#about to read 4, iclass 3, count 0 2006.173.05:48:35.53#ibcon#read 4, iclass 3, count 0 2006.173.05:48:35.53#ibcon#about to read 5, iclass 3, count 0 2006.173.05:48:35.53#ibcon#read 5, iclass 3, count 0 2006.173.05:48:35.53#ibcon#about to read 6, iclass 3, count 0 2006.173.05:48:35.53#ibcon#read 6, iclass 3, count 0 2006.173.05:48:35.53#ibcon#end of sib2, iclass 3, count 0 2006.173.05:48:35.53#ibcon#*after write, iclass 3, count 0 2006.173.05:48:35.53#ibcon#*before return 0, iclass 3, count 0 2006.173.05:48:35.53#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.05:48:35.53#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.05:48:35.53#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.05:48:35.53#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.05:48:35.53$vck44/valo=2,534.99 2006.173.05:48:35.53#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.05:48:35.53#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.05:48:35.53#ibcon#ireg 17 cls_cnt 0 2006.173.05:48:35.53#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.05:48:35.53#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.05:48:35.53#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.05:48:35.53#ibcon#enter wrdev, iclass 5, count 0 2006.173.05:48:35.53#ibcon#first serial, iclass 5, count 0 2006.173.05:48:35.53#ibcon#enter sib2, iclass 5, count 0 2006.173.05:48:35.53#ibcon#flushed, iclass 5, count 0 2006.173.05:48:35.53#ibcon#about to write, iclass 5, count 0 2006.173.05:48:35.53#ibcon#wrote, iclass 5, count 0 2006.173.05:48:35.53#ibcon#about to read 3, iclass 5, count 0 2006.173.05:48:35.55#ibcon#read 3, iclass 5, count 0 2006.173.05:48:35.55#ibcon#about to read 4, iclass 5, count 0 2006.173.05:48:35.55#ibcon#read 4, iclass 5, count 0 2006.173.05:48:35.55#ibcon#about to read 5, iclass 5, count 0 2006.173.05:48:35.55#ibcon#read 5, iclass 5, count 0 2006.173.05:48:35.55#ibcon#about to read 6, iclass 5, count 0 2006.173.05:48:35.55#ibcon#read 6, iclass 5, count 0 2006.173.05:48:35.55#ibcon#end of sib2, iclass 5, count 0 2006.173.05:48:35.55#ibcon#*mode == 0, iclass 5, count 0 2006.173.05:48:35.55#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.05:48:35.55#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.05:48:35.55#ibcon#*before write, iclass 5, count 0 2006.173.05:48:35.55#ibcon#enter sib2, iclass 5, count 0 2006.173.05:48:35.55#ibcon#flushed, iclass 5, count 0 2006.173.05:48:35.55#ibcon#about to write, iclass 5, count 0 2006.173.05:48:35.55#ibcon#wrote, iclass 5, count 0 2006.173.05:48:35.55#ibcon#about to read 3, iclass 5, count 0 2006.173.05:48:35.59#ibcon#read 3, iclass 5, count 0 2006.173.05:48:35.59#ibcon#about to read 4, iclass 5, count 0 2006.173.05:48:35.59#ibcon#read 4, iclass 5, count 0 2006.173.05:48:35.59#ibcon#about to read 5, iclass 5, count 0 2006.173.05:48:35.59#ibcon#read 5, iclass 5, count 0 2006.173.05:48:35.59#ibcon#about to read 6, iclass 5, count 0 2006.173.05:48:35.59#ibcon#read 6, iclass 5, count 0 2006.173.05:48:35.59#ibcon#end of sib2, iclass 5, count 0 2006.173.05:48:35.59#ibcon#*after write, iclass 5, count 0 2006.173.05:48:35.59#ibcon#*before return 0, iclass 5, count 0 2006.173.05:48:35.59#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.05:48:35.59#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.05:48:35.59#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.05:48:35.59#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.05:48:35.59$vck44/va=2,6 2006.173.05:48:35.59#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.05:48:35.59#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.05:48:35.59#ibcon#ireg 11 cls_cnt 2 2006.173.05:48:35.59#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.05:48:35.63#abcon#<5=/15 0.6 1.3 23.59 781005.3\r\n> 2006.173.05:48:35.65#abcon#{5=INTERFACE CLEAR} 2006.173.05:48:35.65#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.05:48:35.65#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.05:48:35.65#ibcon#enter wrdev, iclass 10, count 2 2006.173.05:48:35.65#ibcon#first serial, iclass 10, count 2 2006.173.05:48:35.65#ibcon#enter sib2, iclass 10, count 2 2006.173.05:48:35.65#ibcon#flushed, iclass 10, count 2 2006.173.05:48:35.65#ibcon#about to write, iclass 10, count 2 2006.173.05:48:35.65#ibcon#wrote, iclass 10, count 2 2006.173.05:48:35.65#ibcon#about to read 3, iclass 10, count 2 2006.173.05:48:35.67#ibcon#read 3, iclass 10, count 2 2006.173.05:48:35.67#ibcon#about to read 4, iclass 10, count 2 2006.173.05:48:35.67#ibcon#read 4, iclass 10, count 2 2006.173.05:48:35.67#ibcon#about to read 5, iclass 10, count 2 2006.173.05:48:35.67#ibcon#read 5, iclass 10, count 2 2006.173.05:48:35.67#ibcon#about to read 6, iclass 10, count 2 2006.173.05:48:35.67#ibcon#read 6, iclass 10, count 2 2006.173.05:48:35.67#ibcon#end of sib2, iclass 10, count 2 2006.173.05:48:35.67#ibcon#*mode == 0, iclass 10, count 2 2006.173.05:48:35.67#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.05:48:35.67#ibcon#[25=AT02-06\r\n] 2006.173.05:48:35.67#ibcon#*before write, iclass 10, count 2 2006.173.05:48:35.67#ibcon#enter sib2, iclass 10, count 2 2006.173.05:48:35.67#ibcon#flushed, iclass 10, count 2 2006.173.05:48:35.67#ibcon#about to write, iclass 10, count 2 2006.173.05:48:35.67#ibcon#wrote, iclass 10, count 2 2006.173.05:48:35.67#ibcon#about to read 3, iclass 10, count 2 2006.173.05:48:35.70#ibcon#read 3, iclass 10, count 2 2006.173.05:48:35.70#ibcon#about to read 4, iclass 10, count 2 2006.173.05:48:35.70#ibcon#read 4, iclass 10, count 2 2006.173.05:48:35.70#ibcon#about to read 5, iclass 10, count 2 2006.173.05:48:35.70#ibcon#read 5, iclass 10, count 2 2006.173.05:48:35.70#ibcon#about to read 6, iclass 10, count 2 2006.173.05:48:35.70#ibcon#read 6, iclass 10, count 2 2006.173.05:48:35.70#ibcon#end of sib2, iclass 10, count 2 2006.173.05:48:35.70#ibcon#*after write, iclass 10, count 2 2006.173.05:48:35.70#ibcon#*before return 0, iclass 10, count 2 2006.173.05:48:35.70#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.05:48:35.70#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.05:48:35.70#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.05:48:35.70#ibcon#ireg 7 cls_cnt 0 2006.173.05:48:35.70#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.05:48:35.71#abcon#[5=S1D000X0/0*\r\n] 2006.173.05:48:35.82#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.05:48:35.82#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.05:48:35.82#ibcon#enter wrdev, iclass 10, count 0 2006.173.05:48:35.82#ibcon#first serial, iclass 10, count 0 2006.173.05:48:35.82#ibcon#enter sib2, iclass 10, count 0 2006.173.05:48:35.82#ibcon#flushed, iclass 10, count 0 2006.173.05:48:35.82#ibcon#about to write, iclass 10, count 0 2006.173.05:48:35.82#ibcon#wrote, iclass 10, count 0 2006.173.05:48:35.82#ibcon#about to read 3, iclass 10, count 0 2006.173.05:48:35.84#ibcon#read 3, iclass 10, count 0 2006.173.05:48:35.84#ibcon#about to read 4, iclass 10, count 0 2006.173.05:48:35.84#ibcon#read 4, iclass 10, count 0 2006.173.05:48:35.84#ibcon#about to read 5, iclass 10, count 0 2006.173.05:48:35.84#ibcon#read 5, iclass 10, count 0 2006.173.05:48:35.84#ibcon#about to read 6, iclass 10, count 0 2006.173.05:48:35.84#ibcon#read 6, iclass 10, count 0 2006.173.05:48:35.84#ibcon#end of sib2, iclass 10, count 0 2006.173.05:48:35.84#ibcon#*mode == 0, iclass 10, count 0 2006.173.05:48:35.84#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.05:48:35.84#ibcon#[25=USB\r\n] 2006.173.05:48:35.84#ibcon#*before write, iclass 10, count 0 2006.173.05:48:35.84#ibcon#enter sib2, iclass 10, count 0 2006.173.05:48:35.84#ibcon#flushed, iclass 10, count 0 2006.173.05:48:35.84#ibcon#about to write, iclass 10, count 0 2006.173.05:48:35.84#ibcon#wrote, iclass 10, count 0 2006.173.05:48:35.84#ibcon#about to read 3, iclass 10, count 0 2006.173.05:48:35.87#ibcon#read 3, iclass 10, count 0 2006.173.05:48:35.87#ibcon#about to read 4, iclass 10, count 0 2006.173.05:48:35.87#ibcon#read 4, iclass 10, count 0 2006.173.05:48:35.87#ibcon#about to read 5, iclass 10, count 0 2006.173.05:48:35.87#ibcon#read 5, iclass 10, count 0 2006.173.05:48:35.87#ibcon#about to read 6, iclass 10, count 0 2006.173.05:48:35.87#ibcon#read 6, iclass 10, count 0 2006.173.05:48:35.87#ibcon#end of sib2, iclass 10, count 0 2006.173.05:48:35.87#ibcon#*after write, iclass 10, count 0 2006.173.05:48:35.87#ibcon#*before return 0, iclass 10, count 0 2006.173.05:48:35.87#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.05:48:35.87#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.05:48:35.87#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.05:48:35.87#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.05:48:35.87$vck44/valo=3,564.99 2006.173.05:48:35.87#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.05:48:35.87#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.05:48:35.87#ibcon#ireg 17 cls_cnt 0 2006.173.05:48:35.87#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.05:48:35.87#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.05:48:35.87#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.05:48:35.87#ibcon#enter wrdev, iclass 15, count 0 2006.173.05:48:35.87#ibcon#first serial, iclass 15, count 0 2006.173.05:48:35.87#ibcon#enter sib2, iclass 15, count 0 2006.173.05:48:35.87#ibcon#flushed, iclass 15, count 0 2006.173.05:48:35.87#ibcon#about to write, iclass 15, count 0 2006.173.05:48:35.87#ibcon#wrote, iclass 15, count 0 2006.173.05:48:35.87#ibcon#about to read 3, iclass 15, count 0 2006.173.05:48:35.89#ibcon#read 3, iclass 15, count 0 2006.173.05:48:35.89#ibcon#about to read 4, iclass 15, count 0 2006.173.05:48:35.89#ibcon#read 4, iclass 15, count 0 2006.173.05:48:35.89#ibcon#about to read 5, iclass 15, count 0 2006.173.05:48:35.89#ibcon#read 5, iclass 15, count 0 2006.173.05:48:35.89#ibcon#about to read 6, iclass 15, count 0 2006.173.05:48:35.89#ibcon#read 6, iclass 15, count 0 2006.173.05:48:35.89#ibcon#end of sib2, iclass 15, count 0 2006.173.05:48:35.89#ibcon#*mode == 0, iclass 15, count 0 2006.173.05:48:35.89#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.05:48:35.89#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.05:48:35.89#ibcon#*before write, iclass 15, count 0 2006.173.05:48:35.89#ibcon#enter sib2, iclass 15, count 0 2006.173.05:48:35.89#ibcon#flushed, iclass 15, count 0 2006.173.05:48:35.89#ibcon#about to write, iclass 15, count 0 2006.173.05:48:35.89#ibcon#wrote, iclass 15, count 0 2006.173.05:48:35.89#ibcon#about to read 3, iclass 15, count 0 2006.173.05:48:35.93#ibcon#read 3, iclass 15, count 0 2006.173.05:48:35.93#ibcon#about to read 4, iclass 15, count 0 2006.173.05:48:35.93#ibcon#read 4, iclass 15, count 0 2006.173.05:48:35.93#ibcon#about to read 5, iclass 15, count 0 2006.173.05:48:35.93#ibcon#read 5, iclass 15, count 0 2006.173.05:48:35.93#ibcon#about to read 6, iclass 15, count 0 2006.173.05:48:35.93#ibcon#read 6, iclass 15, count 0 2006.173.05:48:35.93#ibcon#end of sib2, iclass 15, count 0 2006.173.05:48:35.93#ibcon#*after write, iclass 15, count 0 2006.173.05:48:35.93#ibcon#*before return 0, iclass 15, count 0 2006.173.05:48:35.93#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.05:48:35.93#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.05:48:35.93#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.05:48:35.93#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.05:48:35.93$vck44/va=3,5 2006.173.05:48:35.93#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.05:48:35.93#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.05:48:35.93#ibcon#ireg 11 cls_cnt 2 2006.173.05:48:35.93#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.05:48:35.99#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.05:48:35.99#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.05:48:35.99#ibcon#enter wrdev, iclass 17, count 2 2006.173.05:48:35.99#ibcon#first serial, iclass 17, count 2 2006.173.05:48:35.99#ibcon#enter sib2, iclass 17, count 2 2006.173.05:48:35.99#ibcon#flushed, iclass 17, count 2 2006.173.05:48:35.99#ibcon#about to write, iclass 17, count 2 2006.173.05:48:35.99#ibcon#wrote, iclass 17, count 2 2006.173.05:48:35.99#ibcon#about to read 3, iclass 17, count 2 2006.173.05:48:36.01#ibcon#read 3, iclass 17, count 2 2006.173.05:48:36.01#ibcon#about to read 4, iclass 17, count 2 2006.173.05:48:36.01#ibcon#read 4, iclass 17, count 2 2006.173.05:48:36.01#ibcon#about to read 5, iclass 17, count 2 2006.173.05:48:36.01#ibcon#read 5, iclass 17, count 2 2006.173.05:48:36.01#ibcon#about to read 6, iclass 17, count 2 2006.173.05:48:36.01#ibcon#read 6, iclass 17, count 2 2006.173.05:48:36.01#ibcon#end of sib2, iclass 17, count 2 2006.173.05:48:36.01#ibcon#*mode == 0, iclass 17, count 2 2006.173.05:48:36.01#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.05:48:36.01#ibcon#[25=AT03-05\r\n] 2006.173.05:48:36.01#ibcon#*before write, iclass 17, count 2 2006.173.05:48:36.01#ibcon#enter sib2, iclass 17, count 2 2006.173.05:48:36.01#ibcon#flushed, iclass 17, count 2 2006.173.05:48:36.01#ibcon#about to write, iclass 17, count 2 2006.173.05:48:36.01#ibcon#wrote, iclass 17, count 2 2006.173.05:48:36.01#ibcon#about to read 3, iclass 17, count 2 2006.173.05:48:36.04#ibcon#read 3, iclass 17, count 2 2006.173.05:48:36.04#ibcon#about to read 4, iclass 17, count 2 2006.173.05:48:36.04#ibcon#read 4, iclass 17, count 2 2006.173.05:48:36.04#ibcon#about to read 5, iclass 17, count 2 2006.173.05:48:36.04#ibcon#read 5, iclass 17, count 2 2006.173.05:48:36.04#ibcon#about to read 6, iclass 17, count 2 2006.173.05:48:36.04#ibcon#read 6, iclass 17, count 2 2006.173.05:48:36.04#ibcon#end of sib2, iclass 17, count 2 2006.173.05:48:36.04#ibcon#*after write, iclass 17, count 2 2006.173.05:48:36.04#ibcon#*before return 0, iclass 17, count 2 2006.173.05:48:36.04#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.05:48:36.04#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.05:48:36.04#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.05:48:36.04#ibcon#ireg 7 cls_cnt 0 2006.173.05:48:36.04#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.05:48:36.16#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.05:48:36.16#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.05:48:36.16#ibcon#enter wrdev, iclass 17, count 0 2006.173.05:48:36.16#ibcon#first serial, iclass 17, count 0 2006.173.05:48:36.16#ibcon#enter sib2, iclass 17, count 0 2006.173.05:48:36.16#ibcon#flushed, iclass 17, count 0 2006.173.05:48:36.16#ibcon#about to write, iclass 17, count 0 2006.173.05:48:36.16#ibcon#wrote, iclass 17, count 0 2006.173.05:48:36.16#ibcon#about to read 3, iclass 17, count 0 2006.173.05:48:36.18#ibcon#read 3, iclass 17, count 0 2006.173.05:48:36.18#ibcon#about to read 4, iclass 17, count 0 2006.173.05:48:36.18#ibcon#read 4, iclass 17, count 0 2006.173.05:48:36.18#ibcon#about to read 5, iclass 17, count 0 2006.173.05:48:36.18#ibcon#read 5, iclass 17, count 0 2006.173.05:48:36.18#ibcon#about to read 6, iclass 17, count 0 2006.173.05:48:36.18#ibcon#read 6, iclass 17, count 0 2006.173.05:48:36.18#ibcon#end of sib2, iclass 17, count 0 2006.173.05:48:36.18#ibcon#*mode == 0, iclass 17, count 0 2006.173.05:48:36.18#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.05:48:36.18#ibcon#[25=USB\r\n] 2006.173.05:48:36.18#ibcon#*before write, iclass 17, count 0 2006.173.05:48:36.18#ibcon#enter sib2, iclass 17, count 0 2006.173.05:48:36.18#ibcon#flushed, iclass 17, count 0 2006.173.05:48:36.18#ibcon#about to write, iclass 17, count 0 2006.173.05:48:36.18#ibcon#wrote, iclass 17, count 0 2006.173.05:48:36.18#ibcon#about to read 3, iclass 17, count 0 2006.173.05:48:36.21#ibcon#read 3, iclass 17, count 0 2006.173.05:48:36.21#ibcon#about to read 4, iclass 17, count 0 2006.173.05:48:36.21#ibcon#read 4, iclass 17, count 0 2006.173.05:48:36.21#ibcon#about to read 5, iclass 17, count 0 2006.173.05:48:36.21#ibcon#read 5, iclass 17, count 0 2006.173.05:48:36.21#ibcon#about to read 6, iclass 17, count 0 2006.173.05:48:36.21#ibcon#read 6, iclass 17, count 0 2006.173.05:48:36.21#ibcon#end of sib2, iclass 17, count 0 2006.173.05:48:36.21#ibcon#*after write, iclass 17, count 0 2006.173.05:48:36.21#ibcon#*before return 0, iclass 17, count 0 2006.173.05:48:36.21#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.05:48:36.21#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.05:48:36.21#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.05:48:36.21#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.05:48:36.21$vck44/valo=4,624.99 2006.173.05:48:36.21#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.05:48:36.21#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.05:48:36.21#ibcon#ireg 17 cls_cnt 0 2006.173.05:48:36.21#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.05:48:36.21#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.05:48:36.21#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.05:48:36.21#ibcon#enter wrdev, iclass 19, count 0 2006.173.05:48:36.21#ibcon#first serial, iclass 19, count 0 2006.173.05:48:36.21#ibcon#enter sib2, iclass 19, count 0 2006.173.05:48:36.21#ibcon#flushed, iclass 19, count 0 2006.173.05:48:36.21#ibcon#about to write, iclass 19, count 0 2006.173.05:48:36.21#ibcon#wrote, iclass 19, count 0 2006.173.05:48:36.21#ibcon#about to read 3, iclass 19, count 0 2006.173.05:48:36.23#ibcon#read 3, iclass 19, count 0 2006.173.05:48:36.23#ibcon#about to read 4, iclass 19, count 0 2006.173.05:48:36.23#ibcon#read 4, iclass 19, count 0 2006.173.05:48:36.23#ibcon#about to read 5, iclass 19, count 0 2006.173.05:48:36.23#ibcon#read 5, iclass 19, count 0 2006.173.05:48:36.23#ibcon#about to read 6, iclass 19, count 0 2006.173.05:48:36.23#ibcon#read 6, iclass 19, count 0 2006.173.05:48:36.23#ibcon#end of sib2, iclass 19, count 0 2006.173.05:48:36.23#ibcon#*mode == 0, iclass 19, count 0 2006.173.05:48:36.23#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.05:48:36.23#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.05:48:36.23#ibcon#*before write, iclass 19, count 0 2006.173.05:48:36.23#ibcon#enter sib2, iclass 19, count 0 2006.173.05:48:36.23#ibcon#flushed, iclass 19, count 0 2006.173.05:48:36.23#ibcon#about to write, iclass 19, count 0 2006.173.05:48:36.23#ibcon#wrote, iclass 19, count 0 2006.173.05:48:36.23#ibcon#about to read 3, iclass 19, count 0 2006.173.05:48:36.27#ibcon#read 3, iclass 19, count 0 2006.173.05:48:36.27#ibcon#about to read 4, iclass 19, count 0 2006.173.05:48:36.27#ibcon#read 4, iclass 19, count 0 2006.173.05:48:36.27#ibcon#about to read 5, iclass 19, count 0 2006.173.05:48:36.27#ibcon#read 5, iclass 19, count 0 2006.173.05:48:36.27#ibcon#about to read 6, iclass 19, count 0 2006.173.05:48:36.27#ibcon#read 6, iclass 19, count 0 2006.173.05:48:36.27#ibcon#end of sib2, iclass 19, count 0 2006.173.05:48:36.27#ibcon#*after write, iclass 19, count 0 2006.173.05:48:36.27#ibcon#*before return 0, iclass 19, count 0 2006.173.05:48:36.27#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.05:48:36.27#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.05:48:36.27#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.05:48:36.27#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.05:48:36.27$vck44/va=4,6 2006.173.05:48:36.27#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.05:48:36.27#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.05:48:36.27#ibcon#ireg 11 cls_cnt 2 2006.173.05:48:36.27#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.05:48:36.33#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.05:48:36.33#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.05:48:36.33#ibcon#enter wrdev, iclass 21, count 2 2006.173.05:48:36.33#ibcon#first serial, iclass 21, count 2 2006.173.05:48:36.33#ibcon#enter sib2, iclass 21, count 2 2006.173.05:48:36.33#ibcon#flushed, iclass 21, count 2 2006.173.05:48:36.33#ibcon#about to write, iclass 21, count 2 2006.173.05:48:36.33#ibcon#wrote, iclass 21, count 2 2006.173.05:48:36.33#ibcon#about to read 3, iclass 21, count 2 2006.173.05:48:36.35#ibcon#read 3, iclass 21, count 2 2006.173.05:48:36.35#ibcon#about to read 4, iclass 21, count 2 2006.173.05:48:36.35#ibcon#read 4, iclass 21, count 2 2006.173.05:48:36.35#ibcon#about to read 5, iclass 21, count 2 2006.173.05:48:36.35#ibcon#read 5, iclass 21, count 2 2006.173.05:48:36.35#ibcon#about to read 6, iclass 21, count 2 2006.173.05:48:36.35#ibcon#read 6, iclass 21, count 2 2006.173.05:48:36.35#ibcon#end of sib2, iclass 21, count 2 2006.173.05:48:36.35#ibcon#*mode == 0, iclass 21, count 2 2006.173.05:48:36.35#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.05:48:36.35#ibcon#[25=AT04-06\r\n] 2006.173.05:48:36.35#ibcon#*before write, iclass 21, count 2 2006.173.05:48:36.35#ibcon#enter sib2, iclass 21, count 2 2006.173.05:48:36.35#ibcon#flushed, iclass 21, count 2 2006.173.05:48:36.35#ibcon#about to write, iclass 21, count 2 2006.173.05:48:36.35#ibcon#wrote, iclass 21, count 2 2006.173.05:48:36.35#ibcon#about to read 3, iclass 21, count 2 2006.173.05:48:36.38#ibcon#read 3, iclass 21, count 2 2006.173.05:48:36.38#ibcon#about to read 4, iclass 21, count 2 2006.173.05:48:36.38#ibcon#read 4, iclass 21, count 2 2006.173.05:48:36.38#ibcon#about to read 5, iclass 21, count 2 2006.173.05:48:36.38#ibcon#read 5, iclass 21, count 2 2006.173.05:48:36.38#ibcon#about to read 6, iclass 21, count 2 2006.173.05:48:36.38#ibcon#read 6, iclass 21, count 2 2006.173.05:48:36.38#ibcon#end of sib2, iclass 21, count 2 2006.173.05:48:36.38#ibcon#*after write, iclass 21, count 2 2006.173.05:48:36.38#ibcon#*before return 0, iclass 21, count 2 2006.173.05:48:36.38#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.05:48:36.38#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.05:48:36.38#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.05:48:36.38#ibcon#ireg 7 cls_cnt 0 2006.173.05:48:36.38#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.05:48:36.50#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.05:48:36.50#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.05:48:36.50#ibcon#enter wrdev, iclass 21, count 0 2006.173.05:48:36.50#ibcon#first serial, iclass 21, count 0 2006.173.05:48:36.50#ibcon#enter sib2, iclass 21, count 0 2006.173.05:48:36.50#ibcon#flushed, iclass 21, count 0 2006.173.05:48:36.50#ibcon#about to write, iclass 21, count 0 2006.173.05:48:36.50#ibcon#wrote, iclass 21, count 0 2006.173.05:48:36.50#ibcon#about to read 3, iclass 21, count 0 2006.173.05:48:36.52#ibcon#read 3, iclass 21, count 0 2006.173.05:48:36.52#ibcon#about to read 4, iclass 21, count 0 2006.173.05:48:36.52#ibcon#read 4, iclass 21, count 0 2006.173.05:48:36.52#ibcon#about to read 5, iclass 21, count 0 2006.173.05:48:36.52#ibcon#read 5, iclass 21, count 0 2006.173.05:48:36.52#ibcon#about to read 6, iclass 21, count 0 2006.173.05:48:36.52#ibcon#read 6, iclass 21, count 0 2006.173.05:48:36.52#ibcon#end of sib2, iclass 21, count 0 2006.173.05:48:36.52#ibcon#*mode == 0, iclass 21, count 0 2006.173.05:48:36.52#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.05:48:36.52#ibcon#[25=USB\r\n] 2006.173.05:48:36.52#ibcon#*before write, iclass 21, count 0 2006.173.05:48:36.52#ibcon#enter sib2, iclass 21, count 0 2006.173.05:48:36.52#ibcon#flushed, iclass 21, count 0 2006.173.05:48:36.52#ibcon#about to write, iclass 21, count 0 2006.173.05:48:36.52#ibcon#wrote, iclass 21, count 0 2006.173.05:48:36.52#ibcon#about to read 3, iclass 21, count 0 2006.173.05:48:36.55#ibcon#read 3, iclass 21, count 0 2006.173.05:48:36.55#ibcon#about to read 4, iclass 21, count 0 2006.173.05:48:36.55#ibcon#read 4, iclass 21, count 0 2006.173.05:48:36.55#ibcon#about to read 5, iclass 21, count 0 2006.173.05:48:36.55#ibcon#read 5, iclass 21, count 0 2006.173.05:48:36.55#ibcon#about to read 6, iclass 21, count 0 2006.173.05:48:36.55#ibcon#read 6, iclass 21, count 0 2006.173.05:48:36.55#ibcon#end of sib2, iclass 21, count 0 2006.173.05:48:36.55#ibcon#*after write, iclass 21, count 0 2006.173.05:48:36.55#ibcon#*before return 0, iclass 21, count 0 2006.173.05:48:36.55#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.05:48:36.55#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.05:48:36.55#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.05:48:36.55#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.05:48:36.55$vck44/valo=5,734.99 2006.173.05:48:36.55#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.05:48:36.55#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.05:48:36.55#ibcon#ireg 17 cls_cnt 0 2006.173.05:48:36.55#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.05:48:36.55#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.05:48:36.55#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.05:48:36.55#ibcon#enter wrdev, iclass 23, count 0 2006.173.05:48:36.55#ibcon#first serial, iclass 23, count 0 2006.173.05:48:36.55#ibcon#enter sib2, iclass 23, count 0 2006.173.05:48:36.55#ibcon#flushed, iclass 23, count 0 2006.173.05:48:36.55#ibcon#about to write, iclass 23, count 0 2006.173.05:48:36.55#ibcon#wrote, iclass 23, count 0 2006.173.05:48:36.55#ibcon#about to read 3, iclass 23, count 0 2006.173.05:48:36.57#ibcon#read 3, iclass 23, count 0 2006.173.05:48:36.57#ibcon#about to read 4, iclass 23, count 0 2006.173.05:48:36.57#ibcon#read 4, iclass 23, count 0 2006.173.05:48:36.57#ibcon#about to read 5, iclass 23, count 0 2006.173.05:48:36.57#ibcon#read 5, iclass 23, count 0 2006.173.05:48:36.57#ibcon#about to read 6, iclass 23, count 0 2006.173.05:48:36.57#ibcon#read 6, iclass 23, count 0 2006.173.05:48:36.57#ibcon#end of sib2, iclass 23, count 0 2006.173.05:48:36.57#ibcon#*mode == 0, iclass 23, count 0 2006.173.05:48:36.57#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.05:48:36.57#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.05:48:36.57#ibcon#*before write, iclass 23, count 0 2006.173.05:48:36.57#ibcon#enter sib2, iclass 23, count 0 2006.173.05:48:36.57#ibcon#flushed, iclass 23, count 0 2006.173.05:48:36.57#ibcon#about to write, iclass 23, count 0 2006.173.05:48:36.57#ibcon#wrote, iclass 23, count 0 2006.173.05:48:36.57#ibcon#about to read 3, iclass 23, count 0 2006.173.05:48:36.61#ibcon#read 3, iclass 23, count 0 2006.173.05:48:36.61#ibcon#about to read 4, iclass 23, count 0 2006.173.05:48:36.61#ibcon#read 4, iclass 23, count 0 2006.173.05:48:36.61#ibcon#about to read 5, iclass 23, count 0 2006.173.05:48:36.61#ibcon#read 5, iclass 23, count 0 2006.173.05:48:36.61#ibcon#about to read 6, iclass 23, count 0 2006.173.05:48:36.61#ibcon#read 6, iclass 23, count 0 2006.173.05:48:36.61#ibcon#end of sib2, iclass 23, count 0 2006.173.05:48:36.61#ibcon#*after write, iclass 23, count 0 2006.173.05:48:36.61#ibcon#*before return 0, iclass 23, count 0 2006.173.05:48:36.61#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.05:48:36.61#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.05:48:36.61#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.05:48:36.61#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.05:48:36.61$vck44/va=5,4 2006.173.05:48:36.61#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.05:48:36.61#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.05:48:36.61#ibcon#ireg 11 cls_cnt 2 2006.173.05:48:36.61#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.05:48:36.67#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.05:48:36.67#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.05:48:36.67#ibcon#enter wrdev, iclass 25, count 2 2006.173.05:48:36.67#ibcon#first serial, iclass 25, count 2 2006.173.05:48:36.67#ibcon#enter sib2, iclass 25, count 2 2006.173.05:48:36.67#ibcon#flushed, iclass 25, count 2 2006.173.05:48:36.67#ibcon#about to write, iclass 25, count 2 2006.173.05:48:36.67#ibcon#wrote, iclass 25, count 2 2006.173.05:48:36.67#ibcon#about to read 3, iclass 25, count 2 2006.173.05:48:36.69#ibcon#read 3, iclass 25, count 2 2006.173.05:48:36.69#ibcon#about to read 4, iclass 25, count 2 2006.173.05:48:36.69#ibcon#read 4, iclass 25, count 2 2006.173.05:48:36.69#ibcon#about to read 5, iclass 25, count 2 2006.173.05:48:36.69#ibcon#read 5, iclass 25, count 2 2006.173.05:48:36.69#ibcon#about to read 6, iclass 25, count 2 2006.173.05:48:36.69#ibcon#read 6, iclass 25, count 2 2006.173.05:48:36.69#ibcon#end of sib2, iclass 25, count 2 2006.173.05:48:36.69#ibcon#*mode == 0, iclass 25, count 2 2006.173.05:48:36.69#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.05:48:36.69#ibcon#[25=AT05-04\r\n] 2006.173.05:48:36.69#ibcon#*before write, iclass 25, count 2 2006.173.05:48:36.69#ibcon#enter sib2, iclass 25, count 2 2006.173.05:48:36.69#ibcon#flushed, iclass 25, count 2 2006.173.05:48:36.69#ibcon#about to write, iclass 25, count 2 2006.173.05:48:36.69#ibcon#wrote, iclass 25, count 2 2006.173.05:48:36.69#ibcon#about to read 3, iclass 25, count 2 2006.173.05:48:36.72#ibcon#read 3, iclass 25, count 2 2006.173.05:48:36.72#ibcon#about to read 4, iclass 25, count 2 2006.173.05:48:36.72#ibcon#read 4, iclass 25, count 2 2006.173.05:48:36.72#ibcon#about to read 5, iclass 25, count 2 2006.173.05:48:36.72#ibcon#read 5, iclass 25, count 2 2006.173.05:48:36.72#ibcon#about to read 6, iclass 25, count 2 2006.173.05:48:36.72#ibcon#read 6, iclass 25, count 2 2006.173.05:48:36.72#ibcon#end of sib2, iclass 25, count 2 2006.173.05:48:36.72#ibcon#*after write, iclass 25, count 2 2006.173.05:48:36.72#ibcon#*before return 0, iclass 25, count 2 2006.173.05:48:36.72#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.05:48:36.72#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.05:48:36.72#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.05:48:36.72#ibcon#ireg 7 cls_cnt 0 2006.173.05:48:36.72#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.05:48:36.84#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.05:48:36.84#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.05:48:36.84#ibcon#enter wrdev, iclass 25, count 0 2006.173.05:48:36.84#ibcon#first serial, iclass 25, count 0 2006.173.05:48:36.84#ibcon#enter sib2, iclass 25, count 0 2006.173.05:48:36.84#ibcon#flushed, iclass 25, count 0 2006.173.05:48:36.84#ibcon#about to write, iclass 25, count 0 2006.173.05:48:36.84#ibcon#wrote, iclass 25, count 0 2006.173.05:48:36.84#ibcon#about to read 3, iclass 25, count 0 2006.173.05:48:36.86#ibcon#read 3, iclass 25, count 0 2006.173.05:48:36.86#ibcon#about to read 4, iclass 25, count 0 2006.173.05:48:36.86#ibcon#read 4, iclass 25, count 0 2006.173.05:48:36.86#ibcon#about to read 5, iclass 25, count 0 2006.173.05:48:36.86#ibcon#read 5, iclass 25, count 0 2006.173.05:48:36.86#ibcon#about to read 6, iclass 25, count 0 2006.173.05:48:36.86#ibcon#read 6, iclass 25, count 0 2006.173.05:48:36.86#ibcon#end of sib2, iclass 25, count 0 2006.173.05:48:36.86#ibcon#*mode == 0, iclass 25, count 0 2006.173.05:48:36.86#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.05:48:36.86#ibcon#[25=USB\r\n] 2006.173.05:48:36.86#ibcon#*before write, iclass 25, count 0 2006.173.05:48:36.86#ibcon#enter sib2, iclass 25, count 0 2006.173.05:48:36.86#ibcon#flushed, iclass 25, count 0 2006.173.05:48:36.86#ibcon#about to write, iclass 25, count 0 2006.173.05:48:36.86#ibcon#wrote, iclass 25, count 0 2006.173.05:48:36.86#ibcon#about to read 3, iclass 25, count 0 2006.173.05:48:36.89#ibcon#read 3, iclass 25, count 0 2006.173.05:48:36.89#ibcon#about to read 4, iclass 25, count 0 2006.173.05:48:36.89#ibcon#read 4, iclass 25, count 0 2006.173.05:48:36.89#ibcon#about to read 5, iclass 25, count 0 2006.173.05:48:36.89#ibcon#read 5, iclass 25, count 0 2006.173.05:48:36.89#ibcon#about to read 6, iclass 25, count 0 2006.173.05:48:36.89#ibcon#read 6, iclass 25, count 0 2006.173.05:48:36.89#ibcon#end of sib2, iclass 25, count 0 2006.173.05:48:36.89#ibcon#*after write, iclass 25, count 0 2006.173.05:48:36.89#ibcon#*before return 0, iclass 25, count 0 2006.173.05:48:36.89#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.05:48:36.89#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.05:48:36.89#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.05:48:36.89#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.05:48:36.89$vck44/valo=6,814.99 2006.173.05:48:36.89#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.05:48:36.89#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.05:48:36.89#ibcon#ireg 17 cls_cnt 0 2006.173.05:48:36.89#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.05:48:36.89#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.05:48:36.89#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.05:48:36.89#ibcon#enter wrdev, iclass 27, count 0 2006.173.05:48:36.89#ibcon#first serial, iclass 27, count 0 2006.173.05:48:36.89#ibcon#enter sib2, iclass 27, count 0 2006.173.05:48:36.89#ibcon#flushed, iclass 27, count 0 2006.173.05:48:36.89#ibcon#about to write, iclass 27, count 0 2006.173.05:48:36.89#ibcon#wrote, iclass 27, count 0 2006.173.05:48:36.89#ibcon#about to read 3, iclass 27, count 0 2006.173.05:48:36.91#ibcon#read 3, iclass 27, count 0 2006.173.05:48:36.91#ibcon#about to read 4, iclass 27, count 0 2006.173.05:48:36.91#ibcon#read 4, iclass 27, count 0 2006.173.05:48:36.91#ibcon#about to read 5, iclass 27, count 0 2006.173.05:48:36.91#ibcon#read 5, iclass 27, count 0 2006.173.05:48:36.91#ibcon#about to read 6, iclass 27, count 0 2006.173.05:48:36.91#ibcon#read 6, iclass 27, count 0 2006.173.05:48:36.91#ibcon#end of sib2, iclass 27, count 0 2006.173.05:48:36.91#ibcon#*mode == 0, iclass 27, count 0 2006.173.05:48:36.91#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.05:48:36.91#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.05:48:36.91#ibcon#*before write, iclass 27, count 0 2006.173.05:48:36.91#ibcon#enter sib2, iclass 27, count 0 2006.173.05:48:36.91#ibcon#flushed, iclass 27, count 0 2006.173.05:48:36.91#ibcon#about to write, iclass 27, count 0 2006.173.05:48:36.91#ibcon#wrote, iclass 27, count 0 2006.173.05:48:36.91#ibcon#about to read 3, iclass 27, count 0 2006.173.05:48:36.95#ibcon#read 3, iclass 27, count 0 2006.173.05:48:36.95#ibcon#about to read 4, iclass 27, count 0 2006.173.05:48:36.95#ibcon#read 4, iclass 27, count 0 2006.173.05:48:36.95#ibcon#about to read 5, iclass 27, count 0 2006.173.05:48:36.95#ibcon#read 5, iclass 27, count 0 2006.173.05:48:36.95#ibcon#about to read 6, iclass 27, count 0 2006.173.05:48:36.95#ibcon#read 6, iclass 27, count 0 2006.173.05:48:36.95#ibcon#end of sib2, iclass 27, count 0 2006.173.05:48:36.95#ibcon#*after write, iclass 27, count 0 2006.173.05:48:36.95#ibcon#*before return 0, iclass 27, count 0 2006.173.05:48:36.95#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.05:48:36.95#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.05:48:36.95#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.05:48:36.95#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.05:48:36.95$vck44/va=6,3 2006.173.05:48:36.95#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.05:48:36.95#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.05:48:36.95#ibcon#ireg 11 cls_cnt 2 2006.173.05:48:36.95#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.05:48:37.01#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.05:48:37.01#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.05:48:37.01#ibcon#enter wrdev, iclass 29, count 2 2006.173.05:48:37.01#ibcon#first serial, iclass 29, count 2 2006.173.05:48:37.01#ibcon#enter sib2, iclass 29, count 2 2006.173.05:48:37.01#ibcon#flushed, iclass 29, count 2 2006.173.05:48:37.01#ibcon#about to write, iclass 29, count 2 2006.173.05:48:37.01#ibcon#wrote, iclass 29, count 2 2006.173.05:48:37.01#ibcon#about to read 3, iclass 29, count 2 2006.173.05:48:37.03#ibcon#read 3, iclass 29, count 2 2006.173.05:48:37.03#ibcon#about to read 4, iclass 29, count 2 2006.173.05:48:37.03#ibcon#read 4, iclass 29, count 2 2006.173.05:48:37.03#ibcon#about to read 5, iclass 29, count 2 2006.173.05:48:37.03#ibcon#read 5, iclass 29, count 2 2006.173.05:48:37.03#ibcon#about to read 6, iclass 29, count 2 2006.173.05:48:37.03#ibcon#read 6, iclass 29, count 2 2006.173.05:48:37.03#ibcon#end of sib2, iclass 29, count 2 2006.173.05:48:37.03#ibcon#*mode == 0, iclass 29, count 2 2006.173.05:48:37.03#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.05:48:37.03#ibcon#[25=AT06-03\r\n] 2006.173.05:48:37.03#ibcon#*before write, iclass 29, count 2 2006.173.05:48:37.03#ibcon#enter sib2, iclass 29, count 2 2006.173.05:48:37.03#ibcon#flushed, iclass 29, count 2 2006.173.05:48:37.03#ibcon#about to write, iclass 29, count 2 2006.173.05:48:37.03#ibcon#wrote, iclass 29, count 2 2006.173.05:48:37.03#ibcon#about to read 3, iclass 29, count 2 2006.173.05:48:37.06#ibcon#read 3, iclass 29, count 2 2006.173.05:48:37.06#ibcon#about to read 4, iclass 29, count 2 2006.173.05:48:37.06#ibcon#read 4, iclass 29, count 2 2006.173.05:48:37.06#ibcon#about to read 5, iclass 29, count 2 2006.173.05:48:37.06#ibcon#read 5, iclass 29, count 2 2006.173.05:48:37.06#ibcon#about to read 6, iclass 29, count 2 2006.173.05:48:37.06#ibcon#read 6, iclass 29, count 2 2006.173.05:48:37.06#ibcon#end of sib2, iclass 29, count 2 2006.173.05:48:37.06#ibcon#*after write, iclass 29, count 2 2006.173.05:48:37.06#ibcon#*before return 0, iclass 29, count 2 2006.173.05:48:37.06#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.05:48:37.06#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.05:48:37.06#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.05:48:37.06#ibcon#ireg 7 cls_cnt 0 2006.173.05:48:37.06#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.05:48:37.18#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.05:48:37.18#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.05:48:37.18#ibcon#enter wrdev, iclass 29, count 0 2006.173.05:48:37.18#ibcon#first serial, iclass 29, count 0 2006.173.05:48:37.18#ibcon#enter sib2, iclass 29, count 0 2006.173.05:48:37.18#ibcon#flushed, iclass 29, count 0 2006.173.05:48:37.18#ibcon#about to write, iclass 29, count 0 2006.173.05:48:37.18#ibcon#wrote, iclass 29, count 0 2006.173.05:48:37.18#ibcon#about to read 3, iclass 29, count 0 2006.173.05:48:37.20#ibcon#read 3, iclass 29, count 0 2006.173.05:48:37.20#ibcon#about to read 4, iclass 29, count 0 2006.173.05:48:37.20#ibcon#read 4, iclass 29, count 0 2006.173.05:48:37.20#ibcon#about to read 5, iclass 29, count 0 2006.173.05:48:37.20#ibcon#read 5, iclass 29, count 0 2006.173.05:48:37.20#ibcon#about to read 6, iclass 29, count 0 2006.173.05:48:37.20#ibcon#read 6, iclass 29, count 0 2006.173.05:48:37.20#ibcon#end of sib2, iclass 29, count 0 2006.173.05:48:37.20#ibcon#*mode == 0, iclass 29, count 0 2006.173.05:48:37.20#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.05:48:37.20#ibcon#[25=USB\r\n] 2006.173.05:48:37.20#ibcon#*before write, iclass 29, count 0 2006.173.05:48:37.20#ibcon#enter sib2, iclass 29, count 0 2006.173.05:48:37.20#ibcon#flushed, iclass 29, count 0 2006.173.05:48:37.20#ibcon#about to write, iclass 29, count 0 2006.173.05:48:37.20#ibcon#wrote, iclass 29, count 0 2006.173.05:48:37.20#ibcon#about to read 3, iclass 29, count 0 2006.173.05:48:37.23#ibcon#read 3, iclass 29, count 0 2006.173.05:48:37.23#ibcon#about to read 4, iclass 29, count 0 2006.173.05:48:37.23#ibcon#read 4, iclass 29, count 0 2006.173.05:48:37.23#ibcon#about to read 5, iclass 29, count 0 2006.173.05:48:37.23#ibcon#read 5, iclass 29, count 0 2006.173.05:48:37.23#ibcon#about to read 6, iclass 29, count 0 2006.173.05:48:37.23#ibcon#read 6, iclass 29, count 0 2006.173.05:48:37.23#ibcon#end of sib2, iclass 29, count 0 2006.173.05:48:37.23#ibcon#*after write, iclass 29, count 0 2006.173.05:48:37.23#ibcon#*before return 0, iclass 29, count 0 2006.173.05:48:37.23#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.05:48:37.23#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.05:48:37.23#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.05:48:37.23#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.05:48:37.23$vck44/valo=7,864.99 2006.173.05:48:37.23#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.05:48:37.23#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.05:48:37.23#ibcon#ireg 17 cls_cnt 0 2006.173.05:48:37.23#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.05:48:37.23#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.05:48:37.23#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.05:48:37.23#ibcon#enter wrdev, iclass 31, count 0 2006.173.05:48:37.23#ibcon#first serial, iclass 31, count 0 2006.173.05:48:37.23#ibcon#enter sib2, iclass 31, count 0 2006.173.05:48:37.23#ibcon#flushed, iclass 31, count 0 2006.173.05:48:37.23#ibcon#about to write, iclass 31, count 0 2006.173.05:48:37.23#ibcon#wrote, iclass 31, count 0 2006.173.05:48:37.23#ibcon#about to read 3, iclass 31, count 0 2006.173.05:48:37.25#ibcon#read 3, iclass 31, count 0 2006.173.05:48:37.25#ibcon#about to read 4, iclass 31, count 0 2006.173.05:48:37.25#ibcon#read 4, iclass 31, count 0 2006.173.05:48:37.25#ibcon#about to read 5, iclass 31, count 0 2006.173.05:48:37.25#ibcon#read 5, iclass 31, count 0 2006.173.05:48:37.25#ibcon#about to read 6, iclass 31, count 0 2006.173.05:48:37.25#ibcon#read 6, iclass 31, count 0 2006.173.05:48:37.25#ibcon#end of sib2, iclass 31, count 0 2006.173.05:48:37.25#ibcon#*mode == 0, iclass 31, count 0 2006.173.05:48:37.25#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.05:48:37.25#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.05:48:37.25#ibcon#*before write, iclass 31, count 0 2006.173.05:48:37.25#ibcon#enter sib2, iclass 31, count 0 2006.173.05:48:37.25#ibcon#flushed, iclass 31, count 0 2006.173.05:48:37.25#ibcon#about to write, iclass 31, count 0 2006.173.05:48:37.25#ibcon#wrote, iclass 31, count 0 2006.173.05:48:37.25#ibcon#about to read 3, iclass 31, count 0 2006.173.05:48:37.29#ibcon#read 3, iclass 31, count 0 2006.173.05:48:37.29#ibcon#about to read 4, iclass 31, count 0 2006.173.05:48:37.29#ibcon#read 4, iclass 31, count 0 2006.173.05:48:37.29#ibcon#about to read 5, iclass 31, count 0 2006.173.05:48:37.29#ibcon#read 5, iclass 31, count 0 2006.173.05:48:37.29#ibcon#about to read 6, iclass 31, count 0 2006.173.05:48:37.29#ibcon#read 6, iclass 31, count 0 2006.173.05:48:37.29#ibcon#end of sib2, iclass 31, count 0 2006.173.05:48:37.29#ibcon#*after write, iclass 31, count 0 2006.173.05:48:37.29#ibcon#*before return 0, iclass 31, count 0 2006.173.05:48:37.29#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.05:48:37.29#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.05:48:37.29#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.05:48:37.29#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.05:48:37.29$vck44/va=7,4 2006.173.05:48:37.29#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.173.05:48:37.29#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.173.05:48:37.29#ibcon#ireg 11 cls_cnt 2 2006.173.05:48:37.29#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.05:48:37.35#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.05:48:37.35#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.05:48:37.35#ibcon#enter wrdev, iclass 33, count 2 2006.173.05:48:37.35#ibcon#first serial, iclass 33, count 2 2006.173.05:48:37.35#ibcon#enter sib2, iclass 33, count 2 2006.173.05:48:37.35#ibcon#flushed, iclass 33, count 2 2006.173.05:48:37.35#ibcon#about to write, iclass 33, count 2 2006.173.05:48:37.35#ibcon#wrote, iclass 33, count 2 2006.173.05:48:37.35#ibcon#about to read 3, iclass 33, count 2 2006.173.05:48:37.37#ibcon#read 3, iclass 33, count 2 2006.173.05:48:37.37#ibcon#about to read 4, iclass 33, count 2 2006.173.05:48:37.37#ibcon#read 4, iclass 33, count 2 2006.173.05:48:37.37#ibcon#about to read 5, iclass 33, count 2 2006.173.05:48:37.37#ibcon#read 5, iclass 33, count 2 2006.173.05:48:37.37#ibcon#about to read 6, iclass 33, count 2 2006.173.05:48:37.37#ibcon#read 6, iclass 33, count 2 2006.173.05:48:37.37#ibcon#end of sib2, iclass 33, count 2 2006.173.05:48:37.37#ibcon#*mode == 0, iclass 33, count 2 2006.173.05:48:37.37#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.173.05:48:37.37#ibcon#[25=AT07-04\r\n] 2006.173.05:48:37.37#ibcon#*before write, iclass 33, count 2 2006.173.05:48:37.37#ibcon#enter sib2, iclass 33, count 2 2006.173.05:48:37.37#ibcon#flushed, iclass 33, count 2 2006.173.05:48:37.37#ibcon#about to write, iclass 33, count 2 2006.173.05:48:37.37#ibcon#wrote, iclass 33, count 2 2006.173.05:48:37.37#ibcon#about to read 3, iclass 33, count 2 2006.173.05:48:37.40#ibcon#read 3, iclass 33, count 2 2006.173.05:48:37.40#ibcon#about to read 4, iclass 33, count 2 2006.173.05:48:37.40#ibcon#read 4, iclass 33, count 2 2006.173.05:48:37.40#ibcon#about to read 5, iclass 33, count 2 2006.173.05:48:37.40#ibcon#read 5, iclass 33, count 2 2006.173.05:48:37.40#ibcon#about to read 6, iclass 33, count 2 2006.173.05:48:37.40#ibcon#read 6, iclass 33, count 2 2006.173.05:48:37.40#ibcon#end of sib2, iclass 33, count 2 2006.173.05:48:37.40#ibcon#*after write, iclass 33, count 2 2006.173.05:48:37.40#ibcon#*before return 0, iclass 33, count 2 2006.173.05:48:37.40#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.05:48:37.40#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.173.05:48:37.40#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.173.05:48:37.40#ibcon#ireg 7 cls_cnt 0 2006.173.05:48:37.40#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.05:48:37.52#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.05:48:37.52#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.05:48:37.52#ibcon#enter wrdev, iclass 33, count 0 2006.173.05:48:37.52#ibcon#first serial, iclass 33, count 0 2006.173.05:48:37.52#ibcon#enter sib2, iclass 33, count 0 2006.173.05:48:37.52#ibcon#flushed, iclass 33, count 0 2006.173.05:48:37.52#ibcon#about to write, iclass 33, count 0 2006.173.05:48:37.52#ibcon#wrote, iclass 33, count 0 2006.173.05:48:37.52#ibcon#about to read 3, iclass 33, count 0 2006.173.05:48:37.54#ibcon#read 3, iclass 33, count 0 2006.173.05:48:37.54#ibcon#about to read 4, iclass 33, count 0 2006.173.05:48:37.54#ibcon#read 4, iclass 33, count 0 2006.173.05:48:37.54#ibcon#about to read 5, iclass 33, count 0 2006.173.05:48:37.54#ibcon#read 5, iclass 33, count 0 2006.173.05:48:37.54#ibcon#about to read 6, iclass 33, count 0 2006.173.05:48:37.54#ibcon#read 6, iclass 33, count 0 2006.173.05:48:37.54#ibcon#end of sib2, iclass 33, count 0 2006.173.05:48:37.54#ibcon#*mode == 0, iclass 33, count 0 2006.173.05:48:37.54#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.05:48:37.54#ibcon#[25=USB\r\n] 2006.173.05:48:37.54#ibcon#*before write, iclass 33, count 0 2006.173.05:48:37.54#ibcon#enter sib2, iclass 33, count 0 2006.173.05:48:37.54#ibcon#flushed, iclass 33, count 0 2006.173.05:48:37.54#ibcon#about to write, iclass 33, count 0 2006.173.05:48:37.54#ibcon#wrote, iclass 33, count 0 2006.173.05:48:37.54#ibcon#about to read 3, iclass 33, count 0 2006.173.05:48:37.57#ibcon#read 3, iclass 33, count 0 2006.173.05:48:37.57#ibcon#about to read 4, iclass 33, count 0 2006.173.05:48:37.57#ibcon#read 4, iclass 33, count 0 2006.173.05:48:37.57#ibcon#about to read 5, iclass 33, count 0 2006.173.05:48:37.57#ibcon#read 5, iclass 33, count 0 2006.173.05:48:37.57#ibcon#about to read 6, iclass 33, count 0 2006.173.05:48:37.57#ibcon#read 6, iclass 33, count 0 2006.173.05:48:37.57#ibcon#end of sib2, iclass 33, count 0 2006.173.05:48:37.57#ibcon#*after write, iclass 33, count 0 2006.173.05:48:37.57#ibcon#*before return 0, iclass 33, count 0 2006.173.05:48:37.57#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.05:48:37.57#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.173.05:48:37.57#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.05:48:37.57#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.05:48:37.57$vck44/valo=8,884.99 2006.173.05:48:37.57#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.05:48:37.57#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.05:48:37.57#ibcon#ireg 17 cls_cnt 0 2006.173.05:48:37.57#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.05:48:37.57#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.05:48:37.57#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.05:48:37.57#ibcon#enter wrdev, iclass 35, count 0 2006.173.05:48:37.57#ibcon#first serial, iclass 35, count 0 2006.173.05:48:37.57#ibcon#enter sib2, iclass 35, count 0 2006.173.05:48:37.57#ibcon#flushed, iclass 35, count 0 2006.173.05:48:37.57#ibcon#about to write, iclass 35, count 0 2006.173.05:48:37.57#ibcon#wrote, iclass 35, count 0 2006.173.05:48:37.57#ibcon#about to read 3, iclass 35, count 0 2006.173.05:48:37.59#ibcon#read 3, iclass 35, count 0 2006.173.05:48:37.59#ibcon#about to read 4, iclass 35, count 0 2006.173.05:48:37.59#ibcon#read 4, iclass 35, count 0 2006.173.05:48:37.59#ibcon#about to read 5, iclass 35, count 0 2006.173.05:48:37.59#ibcon#read 5, iclass 35, count 0 2006.173.05:48:37.59#ibcon#about to read 6, iclass 35, count 0 2006.173.05:48:37.59#ibcon#read 6, iclass 35, count 0 2006.173.05:48:37.59#ibcon#end of sib2, iclass 35, count 0 2006.173.05:48:37.59#ibcon#*mode == 0, iclass 35, count 0 2006.173.05:48:37.59#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.05:48:37.59#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.05:48:37.59#ibcon#*before write, iclass 35, count 0 2006.173.05:48:37.59#ibcon#enter sib2, iclass 35, count 0 2006.173.05:48:37.59#ibcon#flushed, iclass 35, count 0 2006.173.05:48:37.59#ibcon#about to write, iclass 35, count 0 2006.173.05:48:37.59#ibcon#wrote, iclass 35, count 0 2006.173.05:48:37.59#ibcon#about to read 3, iclass 35, count 0 2006.173.05:48:37.63#ibcon#read 3, iclass 35, count 0 2006.173.05:48:37.63#ibcon#about to read 4, iclass 35, count 0 2006.173.05:48:37.63#ibcon#read 4, iclass 35, count 0 2006.173.05:48:37.63#ibcon#about to read 5, iclass 35, count 0 2006.173.05:48:37.63#ibcon#read 5, iclass 35, count 0 2006.173.05:48:37.63#ibcon#about to read 6, iclass 35, count 0 2006.173.05:48:37.63#ibcon#read 6, iclass 35, count 0 2006.173.05:48:37.63#ibcon#end of sib2, iclass 35, count 0 2006.173.05:48:37.63#ibcon#*after write, iclass 35, count 0 2006.173.05:48:37.63#ibcon#*before return 0, iclass 35, count 0 2006.173.05:48:37.63#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.05:48:37.63#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.05:48:37.63#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.05:48:37.63#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.05:48:37.63$vck44/va=8,4 2006.173.05:48:37.63#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.173.05:48:37.63#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.173.05:48:37.63#ibcon#ireg 11 cls_cnt 2 2006.173.05:48:37.63#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.05:48:37.69#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.05:48:37.69#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.05:48:37.69#ibcon#enter wrdev, iclass 37, count 2 2006.173.05:48:37.69#ibcon#first serial, iclass 37, count 2 2006.173.05:48:37.69#ibcon#enter sib2, iclass 37, count 2 2006.173.05:48:37.69#ibcon#flushed, iclass 37, count 2 2006.173.05:48:37.69#ibcon#about to write, iclass 37, count 2 2006.173.05:48:37.69#ibcon#wrote, iclass 37, count 2 2006.173.05:48:37.69#ibcon#about to read 3, iclass 37, count 2 2006.173.05:48:37.71#ibcon#read 3, iclass 37, count 2 2006.173.05:48:37.71#ibcon#about to read 4, iclass 37, count 2 2006.173.05:48:37.71#ibcon#read 4, iclass 37, count 2 2006.173.05:48:37.71#ibcon#about to read 5, iclass 37, count 2 2006.173.05:48:37.71#ibcon#read 5, iclass 37, count 2 2006.173.05:48:37.71#ibcon#about to read 6, iclass 37, count 2 2006.173.05:48:37.71#ibcon#read 6, iclass 37, count 2 2006.173.05:48:37.71#ibcon#end of sib2, iclass 37, count 2 2006.173.05:48:37.71#ibcon#*mode == 0, iclass 37, count 2 2006.173.05:48:37.71#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.173.05:48:37.71#ibcon#[25=AT08-04\r\n] 2006.173.05:48:37.71#ibcon#*before write, iclass 37, count 2 2006.173.05:48:37.71#ibcon#enter sib2, iclass 37, count 2 2006.173.05:48:37.71#ibcon#flushed, iclass 37, count 2 2006.173.05:48:37.71#ibcon#about to write, iclass 37, count 2 2006.173.05:48:37.71#ibcon#wrote, iclass 37, count 2 2006.173.05:48:37.71#ibcon#about to read 3, iclass 37, count 2 2006.173.05:48:37.74#ibcon#read 3, iclass 37, count 2 2006.173.05:48:37.74#ibcon#about to read 4, iclass 37, count 2 2006.173.05:48:37.74#ibcon#read 4, iclass 37, count 2 2006.173.05:48:37.74#ibcon#about to read 5, iclass 37, count 2 2006.173.05:48:37.74#ibcon#read 5, iclass 37, count 2 2006.173.05:48:37.74#ibcon#about to read 6, iclass 37, count 2 2006.173.05:48:37.74#ibcon#read 6, iclass 37, count 2 2006.173.05:48:37.74#ibcon#end of sib2, iclass 37, count 2 2006.173.05:48:37.74#ibcon#*after write, iclass 37, count 2 2006.173.05:48:37.74#ibcon#*before return 0, iclass 37, count 2 2006.173.05:48:37.74#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.05:48:37.74#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.173.05:48:37.74#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.173.05:48:37.74#ibcon#ireg 7 cls_cnt 0 2006.173.05:48:37.74#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.05:48:37.86#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.05:48:37.86#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.05:48:37.86#ibcon#enter wrdev, iclass 37, count 0 2006.173.05:48:37.86#ibcon#first serial, iclass 37, count 0 2006.173.05:48:37.86#ibcon#enter sib2, iclass 37, count 0 2006.173.05:48:37.86#ibcon#flushed, iclass 37, count 0 2006.173.05:48:37.86#ibcon#about to write, iclass 37, count 0 2006.173.05:48:37.86#ibcon#wrote, iclass 37, count 0 2006.173.05:48:37.86#ibcon#about to read 3, iclass 37, count 0 2006.173.05:48:37.88#ibcon#read 3, iclass 37, count 0 2006.173.05:48:37.88#ibcon#about to read 4, iclass 37, count 0 2006.173.05:48:37.88#ibcon#read 4, iclass 37, count 0 2006.173.05:48:37.88#ibcon#about to read 5, iclass 37, count 0 2006.173.05:48:37.88#ibcon#read 5, iclass 37, count 0 2006.173.05:48:37.88#ibcon#about to read 6, iclass 37, count 0 2006.173.05:48:37.88#ibcon#read 6, iclass 37, count 0 2006.173.05:48:37.88#ibcon#end of sib2, iclass 37, count 0 2006.173.05:48:37.88#ibcon#*mode == 0, iclass 37, count 0 2006.173.05:48:37.88#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.05:48:37.88#ibcon#[25=USB\r\n] 2006.173.05:48:37.88#ibcon#*before write, iclass 37, count 0 2006.173.05:48:37.88#ibcon#enter sib2, iclass 37, count 0 2006.173.05:48:37.88#ibcon#flushed, iclass 37, count 0 2006.173.05:48:37.88#ibcon#about to write, iclass 37, count 0 2006.173.05:48:37.88#ibcon#wrote, iclass 37, count 0 2006.173.05:48:37.88#ibcon#about to read 3, iclass 37, count 0 2006.173.05:48:37.91#ibcon#read 3, iclass 37, count 0 2006.173.05:48:37.91#ibcon#about to read 4, iclass 37, count 0 2006.173.05:48:37.91#ibcon#read 4, iclass 37, count 0 2006.173.05:48:37.91#ibcon#about to read 5, iclass 37, count 0 2006.173.05:48:37.91#ibcon#read 5, iclass 37, count 0 2006.173.05:48:37.91#ibcon#about to read 6, iclass 37, count 0 2006.173.05:48:37.91#ibcon#read 6, iclass 37, count 0 2006.173.05:48:37.91#ibcon#end of sib2, iclass 37, count 0 2006.173.05:48:37.91#ibcon#*after write, iclass 37, count 0 2006.173.05:48:37.91#ibcon#*before return 0, iclass 37, count 0 2006.173.05:48:37.91#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.05:48:37.91#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.173.05:48:37.91#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.05:48:37.91#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.05:48:37.91$vck44/vblo=1,629.99 2006.173.05:48:37.91#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.05:48:37.91#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.05:48:37.91#ibcon#ireg 17 cls_cnt 0 2006.173.05:48:37.91#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.05:48:37.91#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.05:48:37.91#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.05:48:37.91#ibcon#enter wrdev, iclass 39, count 0 2006.173.05:48:37.91#ibcon#first serial, iclass 39, count 0 2006.173.05:48:37.91#ibcon#enter sib2, iclass 39, count 0 2006.173.05:48:37.91#ibcon#flushed, iclass 39, count 0 2006.173.05:48:37.91#ibcon#about to write, iclass 39, count 0 2006.173.05:48:37.91#ibcon#wrote, iclass 39, count 0 2006.173.05:48:37.91#ibcon#about to read 3, iclass 39, count 0 2006.173.05:48:37.93#ibcon#read 3, iclass 39, count 0 2006.173.05:48:37.93#ibcon#about to read 4, iclass 39, count 0 2006.173.05:48:37.93#ibcon#read 4, iclass 39, count 0 2006.173.05:48:37.93#ibcon#about to read 5, iclass 39, count 0 2006.173.05:48:37.93#ibcon#read 5, iclass 39, count 0 2006.173.05:48:37.93#ibcon#about to read 6, iclass 39, count 0 2006.173.05:48:37.93#ibcon#read 6, iclass 39, count 0 2006.173.05:48:37.93#ibcon#end of sib2, iclass 39, count 0 2006.173.05:48:37.93#ibcon#*mode == 0, iclass 39, count 0 2006.173.05:48:37.93#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.05:48:37.93#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.05:48:37.93#ibcon#*before write, iclass 39, count 0 2006.173.05:48:37.93#ibcon#enter sib2, iclass 39, count 0 2006.173.05:48:37.93#ibcon#flushed, iclass 39, count 0 2006.173.05:48:37.93#ibcon#about to write, iclass 39, count 0 2006.173.05:48:37.93#ibcon#wrote, iclass 39, count 0 2006.173.05:48:37.93#ibcon#about to read 3, iclass 39, count 0 2006.173.05:48:37.97#ibcon#read 3, iclass 39, count 0 2006.173.05:48:37.97#ibcon#about to read 4, iclass 39, count 0 2006.173.05:48:37.97#ibcon#read 4, iclass 39, count 0 2006.173.05:48:37.97#ibcon#about to read 5, iclass 39, count 0 2006.173.05:48:37.97#ibcon#read 5, iclass 39, count 0 2006.173.05:48:37.97#ibcon#about to read 6, iclass 39, count 0 2006.173.05:48:37.97#ibcon#read 6, iclass 39, count 0 2006.173.05:48:37.97#ibcon#end of sib2, iclass 39, count 0 2006.173.05:48:37.97#ibcon#*after write, iclass 39, count 0 2006.173.05:48:37.97#ibcon#*before return 0, iclass 39, count 0 2006.173.05:48:37.97#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.05:48:37.97#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.05:48:37.97#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.05:48:37.97#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.05:48:37.97$vck44/vb=1,4 2006.173.05:48:37.97#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.05:48:37.97#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.05:48:37.97#ibcon#ireg 11 cls_cnt 2 2006.173.05:48:37.97#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.05:48:37.97#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.05:48:37.97#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.05:48:37.97#ibcon#enter wrdev, iclass 3, count 2 2006.173.05:48:37.97#ibcon#first serial, iclass 3, count 2 2006.173.05:48:37.97#ibcon#enter sib2, iclass 3, count 2 2006.173.05:48:37.97#ibcon#flushed, iclass 3, count 2 2006.173.05:48:37.97#ibcon#about to write, iclass 3, count 2 2006.173.05:48:37.97#ibcon#wrote, iclass 3, count 2 2006.173.05:48:37.97#ibcon#about to read 3, iclass 3, count 2 2006.173.05:48:37.99#ibcon#read 3, iclass 3, count 2 2006.173.05:48:37.99#ibcon#about to read 4, iclass 3, count 2 2006.173.05:48:37.99#ibcon#read 4, iclass 3, count 2 2006.173.05:48:37.99#ibcon#about to read 5, iclass 3, count 2 2006.173.05:48:37.99#ibcon#read 5, iclass 3, count 2 2006.173.05:48:37.99#ibcon#about to read 6, iclass 3, count 2 2006.173.05:48:37.99#ibcon#read 6, iclass 3, count 2 2006.173.05:48:37.99#ibcon#end of sib2, iclass 3, count 2 2006.173.05:48:37.99#ibcon#*mode == 0, iclass 3, count 2 2006.173.05:48:37.99#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.05:48:37.99#ibcon#[27=AT01-04\r\n] 2006.173.05:48:37.99#ibcon#*before write, iclass 3, count 2 2006.173.05:48:37.99#ibcon#enter sib2, iclass 3, count 2 2006.173.05:48:37.99#ibcon#flushed, iclass 3, count 2 2006.173.05:48:37.99#ibcon#about to write, iclass 3, count 2 2006.173.05:48:37.99#ibcon#wrote, iclass 3, count 2 2006.173.05:48:37.99#ibcon#about to read 3, iclass 3, count 2 2006.173.05:48:38.02#ibcon#read 3, iclass 3, count 2 2006.173.05:48:38.02#ibcon#about to read 4, iclass 3, count 2 2006.173.05:48:38.02#ibcon#read 4, iclass 3, count 2 2006.173.05:48:38.02#ibcon#about to read 5, iclass 3, count 2 2006.173.05:48:38.02#ibcon#read 5, iclass 3, count 2 2006.173.05:48:38.02#ibcon#about to read 6, iclass 3, count 2 2006.173.05:48:38.02#ibcon#read 6, iclass 3, count 2 2006.173.05:48:38.02#ibcon#end of sib2, iclass 3, count 2 2006.173.05:48:38.02#ibcon#*after write, iclass 3, count 2 2006.173.05:48:38.02#ibcon#*before return 0, iclass 3, count 2 2006.173.05:48:38.02#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.05:48:38.02#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.05:48:38.02#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.05:48:38.02#ibcon#ireg 7 cls_cnt 0 2006.173.05:48:38.02#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.05:48:38.14#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.05:48:38.14#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.05:48:38.14#ibcon#enter wrdev, iclass 3, count 0 2006.173.05:48:38.14#ibcon#first serial, iclass 3, count 0 2006.173.05:48:38.14#ibcon#enter sib2, iclass 3, count 0 2006.173.05:48:38.14#ibcon#flushed, iclass 3, count 0 2006.173.05:48:38.14#ibcon#about to write, iclass 3, count 0 2006.173.05:48:38.14#ibcon#wrote, iclass 3, count 0 2006.173.05:48:38.14#ibcon#about to read 3, iclass 3, count 0 2006.173.05:48:38.16#ibcon#read 3, iclass 3, count 0 2006.173.05:48:38.16#ibcon#about to read 4, iclass 3, count 0 2006.173.05:48:38.16#ibcon#read 4, iclass 3, count 0 2006.173.05:48:38.16#ibcon#about to read 5, iclass 3, count 0 2006.173.05:48:38.16#ibcon#read 5, iclass 3, count 0 2006.173.05:48:38.16#ibcon#about to read 6, iclass 3, count 0 2006.173.05:48:38.16#ibcon#read 6, iclass 3, count 0 2006.173.05:48:38.16#ibcon#end of sib2, iclass 3, count 0 2006.173.05:48:38.16#ibcon#*mode == 0, iclass 3, count 0 2006.173.05:48:38.16#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.05:48:38.16#ibcon#[27=USB\r\n] 2006.173.05:48:38.16#ibcon#*before write, iclass 3, count 0 2006.173.05:48:38.16#ibcon#enter sib2, iclass 3, count 0 2006.173.05:48:38.16#ibcon#flushed, iclass 3, count 0 2006.173.05:48:38.16#ibcon#about to write, iclass 3, count 0 2006.173.05:48:38.16#ibcon#wrote, iclass 3, count 0 2006.173.05:48:38.16#ibcon#about to read 3, iclass 3, count 0 2006.173.05:48:38.19#ibcon#read 3, iclass 3, count 0 2006.173.05:48:38.19#ibcon#about to read 4, iclass 3, count 0 2006.173.05:48:38.19#ibcon#read 4, iclass 3, count 0 2006.173.05:48:38.19#ibcon#about to read 5, iclass 3, count 0 2006.173.05:48:38.19#ibcon#read 5, iclass 3, count 0 2006.173.05:48:38.19#ibcon#about to read 6, iclass 3, count 0 2006.173.05:48:38.19#ibcon#read 6, iclass 3, count 0 2006.173.05:48:38.19#ibcon#end of sib2, iclass 3, count 0 2006.173.05:48:38.19#ibcon#*after write, iclass 3, count 0 2006.173.05:48:38.19#ibcon#*before return 0, iclass 3, count 0 2006.173.05:48:38.19#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.05:48:38.19#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.05:48:38.19#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.05:48:38.19#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.05:48:38.19$vck44/vblo=2,634.99 2006.173.05:48:38.19#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.05:48:38.19#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.05:48:38.19#ibcon#ireg 17 cls_cnt 0 2006.173.05:48:38.19#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.05:48:38.19#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.05:48:38.19#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.05:48:38.19#ibcon#enter wrdev, iclass 5, count 0 2006.173.05:48:38.19#ibcon#first serial, iclass 5, count 0 2006.173.05:48:38.19#ibcon#enter sib2, iclass 5, count 0 2006.173.05:48:38.19#ibcon#flushed, iclass 5, count 0 2006.173.05:48:38.19#ibcon#about to write, iclass 5, count 0 2006.173.05:48:38.19#ibcon#wrote, iclass 5, count 0 2006.173.05:48:38.19#ibcon#about to read 3, iclass 5, count 0 2006.173.05:48:38.21#ibcon#read 3, iclass 5, count 0 2006.173.05:48:38.21#ibcon#about to read 4, iclass 5, count 0 2006.173.05:48:38.21#ibcon#read 4, iclass 5, count 0 2006.173.05:48:38.21#ibcon#about to read 5, iclass 5, count 0 2006.173.05:48:38.21#ibcon#read 5, iclass 5, count 0 2006.173.05:48:38.21#ibcon#about to read 6, iclass 5, count 0 2006.173.05:48:38.21#ibcon#read 6, iclass 5, count 0 2006.173.05:48:38.21#ibcon#end of sib2, iclass 5, count 0 2006.173.05:48:38.21#ibcon#*mode == 0, iclass 5, count 0 2006.173.05:48:38.21#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.05:48:38.21#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.05:48:38.21#ibcon#*before write, iclass 5, count 0 2006.173.05:48:38.21#ibcon#enter sib2, iclass 5, count 0 2006.173.05:48:38.21#ibcon#flushed, iclass 5, count 0 2006.173.05:48:38.21#ibcon#about to write, iclass 5, count 0 2006.173.05:48:38.21#ibcon#wrote, iclass 5, count 0 2006.173.05:48:38.21#ibcon#about to read 3, iclass 5, count 0 2006.173.05:48:38.25#ibcon#read 3, iclass 5, count 0 2006.173.05:48:38.25#ibcon#about to read 4, iclass 5, count 0 2006.173.05:48:38.25#ibcon#read 4, iclass 5, count 0 2006.173.05:48:38.25#ibcon#about to read 5, iclass 5, count 0 2006.173.05:48:38.25#ibcon#read 5, iclass 5, count 0 2006.173.05:48:38.25#ibcon#about to read 6, iclass 5, count 0 2006.173.05:48:38.25#ibcon#read 6, iclass 5, count 0 2006.173.05:48:38.25#ibcon#end of sib2, iclass 5, count 0 2006.173.05:48:38.25#ibcon#*after write, iclass 5, count 0 2006.173.05:48:38.25#ibcon#*before return 0, iclass 5, count 0 2006.173.05:48:38.25#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.05:48:38.25#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.05:48:38.25#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.05:48:38.25#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.05:48:38.25$vck44/vb=2,4 2006.173.05:48:38.25#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.173.05:48:38.25#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.173.05:48:38.25#ibcon#ireg 11 cls_cnt 2 2006.173.05:48:38.25#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.05:48:38.31#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.05:48:38.31#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.05:48:38.31#ibcon#enter wrdev, iclass 7, count 2 2006.173.05:48:38.31#ibcon#first serial, iclass 7, count 2 2006.173.05:48:38.31#ibcon#enter sib2, iclass 7, count 2 2006.173.05:48:38.31#ibcon#flushed, iclass 7, count 2 2006.173.05:48:38.31#ibcon#about to write, iclass 7, count 2 2006.173.05:48:38.31#ibcon#wrote, iclass 7, count 2 2006.173.05:48:38.31#ibcon#about to read 3, iclass 7, count 2 2006.173.05:48:38.33#ibcon#read 3, iclass 7, count 2 2006.173.05:48:38.33#ibcon#about to read 4, iclass 7, count 2 2006.173.05:48:38.33#ibcon#read 4, iclass 7, count 2 2006.173.05:48:38.33#ibcon#about to read 5, iclass 7, count 2 2006.173.05:48:38.33#ibcon#read 5, iclass 7, count 2 2006.173.05:48:38.33#ibcon#about to read 6, iclass 7, count 2 2006.173.05:48:38.33#ibcon#read 6, iclass 7, count 2 2006.173.05:48:38.33#ibcon#end of sib2, iclass 7, count 2 2006.173.05:48:38.33#ibcon#*mode == 0, iclass 7, count 2 2006.173.05:48:38.33#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.173.05:48:38.33#ibcon#[27=AT02-04\r\n] 2006.173.05:48:38.33#ibcon#*before write, iclass 7, count 2 2006.173.05:48:38.33#ibcon#enter sib2, iclass 7, count 2 2006.173.05:48:38.33#ibcon#flushed, iclass 7, count 2 2006.173.05:48:38.33#ibcon#about to write, iclass 7, count 2 2006.173.05:48:38.33#ibcon#wrote, iclass 7, count 2 2006.173.05:48:38.33#ibcon#about to read 3, iclass 7, count 2 2006.173.05:48:38.36#ibcon#read 3, iclass 7, count 2 2006.173.05:48:38.36#ibcon#about to read 4, iclass 7, count 2 2006.173.05:48:38.36#ibcon#read 4, iclass 7, count 2 2006.173.05:48:38.36#ibcon#about to read 5, iclass 7, count 2 2006.173.05:48:38.36#ibcon#read 5, iclass 7, count 2 2006.173.05:48:38.36#ibcon#about to read 6, iclass 7, count 2 2006.173.05:48:38.36#ibcon#read 6, iclass 7, count 2 2006.173.05:48:38.36#ibcon#end of sib2, iclass 7, count 2 2006.173.05:48:38.36#ibcon#*after write, iclass 7, count 2 2006.173.05:48:38.36#ibcon#*before return 0, iclass 7, count 2 2006.173.05:48:38.36#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.05:48:38.36#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.173.05:48:38.36#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.173.05:48:38.36#ibcon#ireg 7 cls_cnt 0 2006.173.05:48:38.36#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.05:48:38.48#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.05:48:38.48#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.05:48:38.48#ibcon#enter wrdev, iclass 7, count 0 2006.173.05:48:38.48#ibcon#first serial, iclass 7, count 0 2006.173.05:48:38.48#ibcon#enter sib2, iclass 7, count 0 2006.173.05:48:38.48#ibcon#flushed, iclass 7, count 0 2006.173.05:48:38.48#ibcon#about to write, iclass 7, count 0 2006.173.05:48:38.48#ibcon#wrote, iclass 7, count 0 2006.173.05:48:38.48#ibcon#about to read 3, iclass 7, count 0 2006.173.05:48:38.50#ibcon#read 3, iclass 7, count 0 2006.173.05:48:38.50#ibcon#about to read 4, iclass 7, count 0 2006.173.05:48:38.50#ibcon#read 4, iclass 7, count 0 2006.173.05:48:38.50#ibcon#about to read 5, iclass 7, count 0 2006.173.05:48:38.50#ibcon#read 5, iclass 7, count 0 2006.173.05:48:38.50#ibcon#about to read 6, iclass 7, count 0 2006.173.05:48:38.50#ibcon#read 6, iclass 7, count 0 2006.173.05:48:38.50#ibcon#end of sib2, iclass 7, count 0 2006.173.05:48:38.50#ibcon#*mode == 0, iclass 7, count 0 2006.173.05:48:38.50#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.05:48:38.50#ibcon#[27=USB\r\n] 2006.173.05:48:38.50#ibcon#*before write, iclass 7, count 0 2006.173.05:48:38.50#ibcon#enter sib2, iclass 7, count 0 2006.173.05:48:38.50#ibcon#flushed, iclass 7, count 0 2006.173.05:48:38.50#ibcon#about to write, iclass 7, count 0 2006.173.05:48:38.50#ibcon#wrote, iclass 7, count 0 2006.173.05:48:38.50#ibcon#about to read 3, iclass 7, count 0 2006.173.05:48:38.53#ibcon#read 3, iclass 7, count 0 2006.173.05:48:38.53#ibcon#about to read 4, iclass 7, count 0 2006.173.05:48:38.53#ibcon#read 4, iclass 7, count 0 2006.173.05:48:38.53#ibcon#about to read 5, iclass 7, count 0 2006.173.05:48:38.53#ibcon#read 5, iclass 7, count 0 2006.173.05:48:38.53#ibcon#about to read 6, iclass 7, count 0 2006.173.05:48:38.53#ibcon#read 6, iclass 7, count 0 2006.173.05:48:38.53#ibcon#end of sib2, iclass 7, count 0 2006.173.05:48:38.53#ibcon#*after write, iclass 7, count 0 2006.173.05:48:38.53#ibcon#*before return 0, iclass 7, count 0 2006.173.05:48:38.53#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.05:48:38.53#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.173.05:48:38.53#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.05:48:38.53#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.05:48:38.53$vck44/vblo=3,649.99 2006.173.05:48:38.53#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.05:48:38.53#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.05:48:38.53#ibcon#ireg 17 cls_cnt 0 2006.173.05:48:38.53#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.05:48:38.53#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.05:48:38.53#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.05:48:38.53#ibcon#enter wrdev, iclass 11, count 0 2006.173.05:48:38.53#ibcon#first serial, iclass 11, count 0 2006.173.05:48:38.53#ibcon#enter sib2, iclass 11, count 0 2006.173.05:48:38.53#ibcon#flushed, iclass 11, count 0 2006.173.05:48:38.53#ibcon#about to write, iclass 11, count 0 2006.173.05:48:38.53#ibcon#wrote, iclass 11, count 0 2006.173.05:48:38.53#ibcon#about to read 3, iclass 11, count 0 2006.173.05:48:38.55#ibcon#read 3, iclass 11, count 0 2006.173.05:48:38.55#ibcon#about to read 4, iclass 11, count 0 2006.173.05:48:38.55#ibcon#read 4, iclass 11, count 0 2006.173.05:48:38.55#ibcon#about to read 5, iclass 11, count 0 2006.173.05:48:38.55#ibcon#read 5, iclass 11, count 0 2006.173.05:48:38.55#ibcon#about to read 6, iclass 11, count 0 2006.173.05:48:38.55#ibcon#read 6, iclass 11, count 0 2006.173.05:48:38.55#ibcon#end of sib2, iclass 11, count 0 2006.173.05:48:38.55#ibcon#*mode == 0, iclass 11, count 0 2006.173.05:48:38.55#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.05:48:38.55#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.05:48:38.55#ibcon#*before write, iclass 11, count 0 2006.173.05:48:38.55#ibcon#enter sib2, iclass 11, count 0 2006.173.05:48:38.55#ibcon#flushed, iclass 11, count 0 2006.173.05:48:38.55#ibcon#about to write, iclass 11, count 0 2006.173.05:48:38.55#ibcon#wrote, iclass 11, count 0 2006.173.05:48:38.55#ibcon#about to read 3, iclass 11, count 0 2006.173.05:48:38.59#ibcon#read 3, iclass 11, count 0 2006.173.05:48:38.59#ibcon#about to read 4, iclass 11, count 0 2006.173.05:48:38.59#ibcon#read 4, iclass 11, count 0 2006.173.05:48:38.59#ibcon#about to read 5, iclass 11, count 0 2006.173.05:48:38.59#ibcon#read 5, iclass 11, count 0 2006.173.05:48:38.59#ibcon#about to read 6, iclass 11, count 0 2006.173.05:48:38.59#ibcon#read 6, iclass 11, count 0 2006.173.05:48:38.59#ibcon#end of sib2, iclass 11, count 0 2006.173.05:48:38.59#ibcon#*after write, iclass 11, count 0 2006.173.05:48:38.59#ibcon#*before return 0, iclass 11, count 0 2006.173.05:48:38.59#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.05:48:38.59#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.05:48:38.59#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.05:48:38.59#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.05:48:38.59$vck44/vb=3,4 2006.173.05:48:38.59#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.173.05:48:38.59#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.173.05:48:38.59#ibcon#ireg 11 cls_cnt 2 2006.173.05:48:38.59#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.05:48:38.65#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.05:48:38.65#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.05:48:38.65#ibcon#enter wrdev, iclass 13, count 2 2006.173.05:48:38.65#ibcon#first serial, iclass 13, count 2 2006.173.05:48:38.65#ibcon#enter sib2, iclass 13, count 2 2006.173.05:48:38.65#ibcon#flushed, iclass 13, count 2 2006.173.05:48:38.65#ibcon#about to write, iclass 13, count 2 2006.173.05:48:38.65#ibcon#wrote, iclass 13, count 2 2006.173.05:48:38.65#ibcon#about to read 3, iclass 13, count 2 2006.173.05:48:38.67#ibcon#read 3, iclass 13, count 2 2006.173.05:48:38.67#ibcon#about to read 4, iclass 13, count 2 2006.173.05:48:38.67#ibcon#read 4, iclass 13, count 2 2006.173.05:48:38.67#ibcon#about to read 5, iclass 13, count 2 2006.173.05:48:38.67#ibcon#read 5, iclass 13, count 2 2006.173.05:48:38.67#ibcon#about to read 6, iclass 13, count 2 2006.173.05:48:38.67#ibcon#read 6, iclass 13, count 2 2006.173.05:48:38.67#ibcon#end of sib2, iclass 13, count 2 2006.173.05:48:38.67#ibcon#*mode == 0, iclass 13, count 2 2006.173.05:48:38.67#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.173.05:48:38.67#ibcon#[27=AT03-04\r\n] 2006.173.05:48:38.67#ibcon#*before write, iclass 13, count 2 2006.173.05:48:38.67#ibcon#enter sib2, iclass 13, count 2 2006.173.05:48:38.67#ibcon#flushed, iclass 13, count 2 2006.173.05:48:38.67#ibcon#about to write, iclass 13, count 2 2006.173.05:48:38.67#ibcon#wrote, iclass 13, count 2 2006.173.05:48:38.67#ibcon#about to read 3, iclass 13, count 2 2006.173.05:48:38.70#ibcon#read 3, iclass 13, count 2 2006.173.05:48:38.70#ibcon#about to read 4, iclass 13, count 2 2006.173.05:48:38.70#ibcon#read 4, iclass 13, count 2 2006.173.05:48:38.70#ibcon#about to read 5, iclass 13, count 2 2006.173.05:48:38.70#ibcon#read 5, iclass 13, count 2 2006.173.05:48:38.70#ibcon#about to read 6, iclass 13, count 2 2006.173.05:48:38.70#ibcon#read 6, iclass 13, count 2 2006.173.05:48:38.70#ibcon#end of sib2, iclass 13, count 2 2006.173.05:48:38.70#ibcon#*after write, iclass 13, count 2 2006.173.05:48:38.70#ibcon#*before return 0, iclass 13, count 2 2006.173.05:48:38.70#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.05:48:38.70#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.173.05:48:38.70#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.173.05:48:38.70#ibcon#ireg 7 cls_cnt 0 2006.173.05:48:38.70#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.05:48:38.82#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.05:48:38.82#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.05:48:38.82#ibcon#enter wrdev, iclass 13, count 0 2006.173.05:48:38.82#ibcon#first serial, iclass 13, count 0 2006.173.05:48:38.82#ibcon#enter sib2, iclass 13, count 0 2006.173.05:48:38.82#ibcon#flushed, iclass 13, count 0 2006.173.05:48:38.82#ibcon#about to write, iclass 13, count 0 2006.173.05:48:38.82#ibcon#wrote, iclass 13, count 0 2006.173.05:48:38.82#ibcon#about to read 3, iclass 13, count 0 2006.173.05:48:38.84#ibcon#read 3, iclass 13, count 0 2006.173.05:48:38.84#ibcon#about to read 4, iclass 13, count 0 2006.173.05:48:38.84#ibcon#read 4, iclass 13, count 0 2006.173.05:48:38.84#ibcon#about to read 5, iclass 13, count 0 2006.173.05:48:38.84#ibcon#read 5, iclass 13, count 0 2006.173.05:48:38.84#ibcon#about to read 6, iclass 13, count 0 2006.173.05:48:38.84#ibcon#read 6, iclass 13, count 0 2006.173.05:48:38.84#ibcon#end of sib2, iclass 13, count 0 2006.173.05:48:38.84#ibcon#*mode == 0, iclass 13, count 0 2006.173.05:48:38.84#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.05:48:38.84#ibcon#[27=USB\r\n] 2006.173.05:48:38.84#ibcon#*before write, iclass 13, count 0 2006.173.05:48:38.84#ibcon#enter sib2, iclass 13, count 0 2006.173.05:48:38.84#ibcon#flushed, iclass 13, count 0 2006.173.05:48:38.84#ibcon#about to write, iclass 13, count 0 2006.173.05:48:38.84#ibcon#wrote, iclass 13, count 0 2006.173.05:48:38.84#ibcon#about to read 3, iclass 13, count 0 2006.173.05:48:38.87#ibcon#read 3, iclass 13, count 0 2006.173.05:48:38.87#ibcon#about to read 4, iclass 13, count 0 2006.173.05:48:38.87#ibcon#read 4, iclass 13, count 0 2006.173.05:48:38.87#ibcon#about to read 5, iclass 13, count 0 2006.173.05:48:38.87#ibcon#read 5, iclass 13, count 0 2006.173.05:48:38.87#ibcon#about to read 6, iclass 13, count 0 2006.173.05:48:38.87#ibcon#read 6, iclass 13, count 0 2006.173.05:48:38.87#ibcon#end of sib2, iclass 13, count 0 2006.173.05:48:38.87#ibcon#*after write, iclass 13, count 0 2006.173.05:48:38.87#ibcon#*before return 0, iclass 13, count 0 2006.173.05:48:38.87#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.05:48:38.87#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.173.05:48:38.87#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.05:48:38.87#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.05:48:38.87$vck44/vblo=4,679.99 2006.173.05:48:38.87#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.05:48:38.87#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.05:48:38.87#ibcon#ireg 17 cls_cnt 0 2006.173.05:48:38.87#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.05:48:38.87#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.05:48:38.87#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.05:48:38.87#ibcon#enter wrdev, iclass 15, count 0 2006.173.05:48:38.87#ibcon#first serial, iclass 15, count 0 2006.173.05:48:38.87#ibcon#enter sib2, iclass 15, count 0 2006.173.05:48:38.87#ibcon#flushed, iclass 15, count 0 2006.173.05:48:38.87#ibcon#about to write, iclass 15, count 0 2006.173.05:48:38.87#ibcon#wrote, iclass 15, count 0 2006.173.05:48:38.87#ibcon#about to read 3, iclass 15, count 0 2006.173.05:48:38.89#ibcon#read 3, iclass 15, count 0 2006.173.05:48:38.89#ibcon#about to read 4, iclass 15, count 0 2006.173.05:48:38.89#ibcon#read 4, iclass 15, count 0 2006.173.05:48:38.89#ibcon#about to read 5, iclass 15, count 0 2006.173.05:48:38.89#ibcon#read 5, iclass 15, count 0 2006.173.05:48:38.89#ibcon#about to read 6, iclass 15, count 0 2006.173.05:48:38.89#ibcon#read 6, iclass 15, count 0 2006.173.05:48:38.89#ibcon#end of sib2, iclass 15, count 0 2006.173.05:48:38.89#ibcon#*mode == 0, iclass 15, count 0 2006.173.05:48:38.89#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.05:48:38.89#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.05:48:38.89#ibcon#*before write, iclass 15, count 0 2006.173.05:48:38.89#ibcon#enter sib2, iclass 15, count 0 2006.173.05:48:38.89#ibcon#flushed, iclass 15, count 0 2006.173.05:48:38.89#ibcon#about to write, iclass 15, count 0 2006.173.05:48:38.89#ibcon#wrote, iclass 15, count 0 2006.173.05:48:38.89#ibcon#about to read 3, iclass 15, count 0 2006.173.05:48:38.93#ibcon#read 3, iclass 15, count 0 2006.173.05:48:38.93#ibcon#about to read 4, iclass 15, count 0 2006.173.05:48:38.93#ibcon#read 4, iclass 15, count 0 2006.173.05:48:38.93#ibcon#about to read 5, iclass 15, count 0 2006.173.05:48:38.93#ibcon#read 5, iclass 15, count 0 2006.173.05:48:38.93#ibcon#about to read 6, iclass 15, count 0 2006.173.05:48:38.93#ibcon#read 6, iclass 15, count 0 2006.173.05:48:38.93#ibcon#end of sib2, iclass 15, count 0 2006.173.05:48:38.93#ibcon#*after write, iclass 15, count 0 2006.173.05:48:38.93#ibcon#*before return 0, iclass 15, count 0 2006.173.05:48:38.93#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.05:48:38.93#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.05:48:38.93#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.05:48:38.93#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.05:48:38.93$vck44/vb=4,4 2006.173.05:48:38.93#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.05:48:38.93#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.05:48:38.93#ibcon#ireg 11 cls_cnt 2 2006.173.05:48:38.93#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.05:48:38.99#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.05:48:38.99#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.05:48:38.99#ibcon#enter wrdev, iclass 17, count 2 2006.173.05:48:38.99#ibcon#first serial, iclass 17, count 2 2006.173.05:48:38.99#ibcon#enter sib2, iclass 17, count 2 2006.173.05:48:38.99#ibcon#flushed, iclass 17, count 2 2006.173.05:48:38.99#ibcon#about to write, iclass 17, count 2 2006.173.05:48:38.99#ibcon#wrote, iclass 17, count 2 2006.173.05:48:38.99#ibcon#about to read 3, iclass 17, count 2 2006.173.05:48:39.01#ibcon#read 3, iclass 17, count 2 2006.173.05:48:39.01#ibcon#about to read 4, iclass 17, count 2 2006.173.05:48:39.01#ibcon#read 4, iclass 17, count 2 2006.173.05:48:39.01#ibcon#about to read 5, iclass 17, count 2 2006.173.05:48:39.01#ibcon#read 5, iclass 17, count 2 2006.173.05:48:39.01#ibcon#about to read 6, iclass 17, count 2 2006.173.05:48:39.01#ibcon#read 6, iclass 17, count 2 2006.173.05:48:39.01#ibcon#end of sib2, iclass 17, count 2 2006.173.05:48:39.01#ibcon#*mode == 0, iclass 17, count 2 2006.173.05:48:39.01#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.05:48:39.01#ibcon#[27=AT04-04\r\n] 2006.173.05:48:39.01#ibcon#*before write, iclass 17, count 2 2006.173.05:48:39.01#ibcon#enter sib2, iclass 17, count 2 2006.173.05:48:39.01#ibcon#flushed, iclass 17, count 2 2006.173.05:48:39.01#ibcon#about to write, iclass 17, count 2 2006.173.05:48:39.01#ibcon#wrote, iclass 17, count 2 2006.173.05:48:39.01#ibcon#about to read 3, iclass 17, count 2 2006.173.05:48:39.04#ibcon#read 3, iclass 17, count 2 2006.173.05:48:39.04#ibcon#about to read 4, iclass 17, count 2 2006.173.05:48:39.04#ibcon#read 4, iclass 17, count 2 2006.173.05:48:39.04#ibcon#about to read 5, iclass 17, count 2 2006.173.05:48:39.04#ibcon#read 5, iclass 17, count 2 2006.173.05:48:39.04#ibcon#about to read 6, iclass 17, count 2 2006.173.05:48:39.04#ibcon#read 6, iclass 17, count 2 2006.173.05:48:39.04#ibcon#end of sib2, iclass 17, count 2 2006.173.05:48:39.04#ibcon#*after write, iclass 17, count 2 2006.173.05:48:39.04#ibcon#*before return 0, iclass 17, count 2 2006.173.05:48:39.04#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.05:48:39.04#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.05:48:39.04#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.05:48:39.04#ibcon#ireg 7 cls_cnt 0 2006.173.05:48:39.04#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.05:48:39.16#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.05:48:39.16#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.05:48:39.16#ibcon#enter wrdev, iclass 17, count 0 2006.173.05:48:39.16#ibcon#first serial, iclass 17, count 0 2006.173.05:48:39.16#ibcon#enter sib2, iclass 17, count 0 2006.173.05:48:39.16#ibcon#flushed, iclass 17, count 0 2006.173.05:48:39.16#ibcon#about to write, iclass 17, count 0 2006.173.05:48:39.16#ibcon#wrote, iclass 17, count 0 2006.173.05:48:39.16#ibcon#about to read 3, iclass 17, count 0 2006.173.05:48:39.18#ibcon#read 3, iclass 17, count 0 2006.173.05:48:39.18#ibcon#about to read 4, iclass 17, count 0 2006.173.05:48:39.18#ibcon#read 4, iclass 17, count 0 2006.173.05:48:39.18#ibcon#about to read 5, iclass 17, count 0 2006.173.05:48:39.18#ibcon#read 5, iclass 17, count 0 2006.173.05:48:39.18#ibcon#about to read 6, iclass 17, count 0 2006.173.05:48:39.18#ibcon#read 6, iclass 17, count 0 2006.173.05:48:39.18#ibcon#end of sib2, iclass 17, count 0 2006.173.05:48:39.18#ibcon#*mode == 0, iclass 17, count 0 2006.173.05:48:39.18#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.05:48:39.18#ibcon#[27=USB\r\n] 2006.173.05:48:39.18#ibcon#*before write, iclass 17, count 0 2006.173.05:48:39.18#ibcon#enter sib2, iclass 17, count 0 2006.173.05:48:39.18#ibcon#flushed, iclass 17, count 0 2006.173.05:48:39.18#ibcon#about to write, iclass 17, count 0 2006.173.05:48:39.18#ibcon#wrote, iclass 17, count 0 2006.173.05:48:39.18#ibcon#about to read 3, iclass 17, count 0 2006.173.05:48:39.21#ibcon#read 3, iclass 17, count 0 2006.173.05:48:39.21#ibcon#about to read 4, iclass 17, count 0 2006.173.05:48:39.21#ibcon#read 4, iclass 17, count 0 2006.173.05:48:39.21#ibcon#about to read 5, iclass 17, count 0 2006.173.05:48:39.21#ibcon#read 5, iclass 17, count 0 2006.173.05:48:39.21#ibcon#about to read 6, iclass 17, count 0 2006.173.05:48:39.21#ibcon#read 6, iclass 17, count 0 2006.173.05:48:39.21#ibcon#end of sib2, iclass 17, count 0 2006.173.05:48:39.21#ibcon#*after write, iclass 17, count 0 2006.173.05:48:39.21#ibcon#*before return 0, iclass 17, count 0 2006.173.05:48:39.21#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.05:48:39.21#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.05:48:39.21#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.05:48:39.21#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.05:48:39.21$vck44/vblo=5,709.99 2006.173.05:48:39.21#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.05:48:39.21#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.05:48:39.21#ibcon#ireg 17 cls_cnt 0 2006.173.05:48:39.21#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.05:48:39.21#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.05:48:39.21#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.05:48:39.21#ibcon#enter wrdev, iclass 19, count 0 2006.173.05:48:39.21#ibcon#first serial, iclass 19, count 0 2006.173.05:48:39.21#ibcon#enter sib2, iclass 19, count 0 2006.173.05:48:39.21#ibcon#flushed, iclass 19, count 0 2006.173.05:48:39.21#ibcon#about to write, iclass 19, count 0 2006.173.05:48:39.21#ibcon#wrote, iclass 19, count 0 2006.173.05:48:39.21#ibcon#about to read 3, iclass 19, count 0 2006.173.05:48:39.23#ibcon#read 3, iclass 19, count 0 2006.173.05:48:39.23#ibcon#about to read 4, iclass 19, count 0 2006.173.05:48:39.23#ibcon#read 4, iclass 19, count 0 2006.173.05:48:39.23#ibcon#about to read 5, iclass 19, count 0 2006.173.05:48:39.23#ibcon#read 5, iclass 19, count 0 2006.173.05:48:39.23#ibcon#about to read 6, iclass 19, count 0 2006.173.05:48:39.23#ibcon#read 6, iclass 19, count 0 2006.173.05:48:39.23#ibcon#end of sib2, iclass 19, count 0 2006.173.05:48:39.23#ibcon#*mode == 0, iclass 19, count 0 2006.173.05:48:39.23#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.05:48:39.23#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.05:48:39.23#ibcon#*before write, iclass 19, count 0 2006.173.05:48:39.23#ibcon#enter sib2, iclass 19, count 0 2006.173.05:48:39.23#ibcon#flushed, iclass 19, count 0 2006.173.05:48:39.23#ibcon#about to write, iclass 19, count 0 2006.173.05:48:39.23#ibcon#wrote, iclass 19, count 0 2006.173.05:48:39.23#ibcon#about to read 3, iclass 19, count 0 2006.173.05:48:39.27#ibcon#read 3, iclass 19, count 0 2006.173.05:48:39.27#ibcon#about to read 4, iclass 19, count 0 2006.173.05:48:39.27#ibcon#read 4, iclass 19, count 0 2006.173.05:48:39.27#ibcon#about to read 5, iclass 19, count 0 2006.173.05:48:39.27#ibcon#read 5, iclass 19, count 0 2006.173.05:48:39.27#ibcon#about to read 6, iclass 19, count 0 2006.173.05:48:39.27#ibcon#read 6, iclass 19, count 0 2006.173.05:48:39.27#ibcon#end of sib2, iclass 19, count 0 2006.173.05:48:39.27#ibcon#*after write, iclass 19, count 0 2006.173.05:48:39.27#ibcon#*before return 0, iclass 19, count 0 2006.173.05:48:39.27#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.05:48:39.27#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.05:48:39.27#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.05:48:39.27#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.05:48:39.27$vck44/vb=5,4 2006.173.05:48:39.27#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.05:48:39.27#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.05:48:39.27#ibcon#ireg 11 cls_cnt 2 2006.173.05:48:39.27#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.05:48:39.33#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.05:48:39.33#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.05:48:39.33#ibcon#enter wrdev, iclass 21, count 2 2006.173.05:48:39.33#ibcon#first serial, iclass 21, count 2 2006.173.05:48:39.33#ibcon#enter sib2, iclass 21, count 2 2006.173.05:48:39.33#ibcon#flushed, iclass 21, count 2 2006.173.05:48:39.33#ibcon#about to write, iclass 21, count 2 2006.173.05:48:39.33#ibcon#wrote, iclass 21, count 2 2006.173.05:48:39.33#ibcon#about to read 3, iclass 21, count 2 2006.173.05:48:39.35#ibcon#read 3, iclass 21, count 2 2006.173.05:48:39.35#ibcon#about to read 4, iclass 21, count 2 2006.173.05:48:39.35#ibcon#read 4, iclass 21, count 2 2006.173.05:48:39.35#ibcon#about to read 5, iclass 21, count 2 2006.173.05:48:39.35#ibcon#read 5, iclass 21, count 2 2006.173.05:48:39.35#ibcon#about to read 6, iclass 21, count 2 2006.173.05:48:39.35#ibcon#read 6, iclass 21, count 2 2006.173.05:48:39.35#ibcon#end of sib2, iclass 21, count 2 2006.173.05:48:39.35#ibcon#*mode == 0, iclass 21, count 2 2006.173.05:48:39.35#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.05:48:39.35#ibcon#[27=AT05-04\r\n] 2006.173.05:48:39.35#ibcon#*before write, iclass 21, count 2 2006.173.05:48:39.35#ibcon#enter sib2, iclass 21, count 2 2006.173.05:48:39.35#ibcon#flushed, iclass 21, count 2 2006.173.05:48:39.35#ibcon#about to write, iclass 21, count 2 2006.173.05:48:39.35#ibcon#wrote, iclass 21, count 2 2006.173.05:48:39.35#ibcon#about to read 3, iclass 21, count 2 2006.173.05:48:39.38#ibcon#read 3, iclass 21, count 2 2006.173.05:48:39.38#ibcon#about to read 4, iclass 21, count 2 2006.173.05:48:39.38#ibcon#read 4, iclass 21, count 2 2006.173.05:48:39.38#ibcon#about to read 5, iclass 21, count 2 2006.173.05:48:39.38#ibcon#read 5, iclass 21, count 2 2006.173.05:48:39.38#ibcon#about to read 6, iclass 21, count 2 2006.173.05:48:39.38#ibcon#read 6, iclass 21, count 2 2006.173.05:48:39.38#ibcon#end of sib2, iclass 21, count 2 2006.173.05:48:39.38#ibcon#*after write, iclass 21, count 2 2006.173.05:48:39.38#ibcon#*before return 0, iclass 21, count 2 2006.173.05:48:39.38#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.05:48:39.38#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.05:48:39.38#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.05:48:39.38#ibcon#ireg 7 cls_cnt 0 2006.173.05:48:39.38#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.05:48:39.50#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.05:48:39.50#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.05:48:39.50#ibcon#enter wrdev, iclass 21, count 0 2006.173.05:48:39.50#ibcon#first serial, iclass 21, count 0 2006.173.05:48:39.50#ibcon#enter sib2, iclass 21, count 0 2006.173.05:48:39.50#ibcon#flushed, iclass 21, count 0 2006.173.05:48:39.50#ibcon#about to write, iclass 21, count 0 2006.173.05:48:39.50#ibcon#wrote, iclass 21, count 0 2006.173.05:48:39.50#ibcon#about to read 3, iclass 21, count 0 2006.173.05:48:39.52#ibcon#read 3, iclass 21, count 0 2006.173.05:48:39.52#ibcon#about to read 4, iclass 21, count 0 2006.173.05:48:39.52#ibcon#read 4, iclass 21, count 0 2006.173.05:48:39.52#ibcon#about to read 5, iclass 21, count 0 2006.173.05:48:39.52#ibcon#read 5, iclass 21, count 0 2006.173.05:48:39.52#ibcon#about to read 6, iclass 21, count 0 2006.173.05:48:39.52#ibcon#read 6, iclass 21, count 0 2006.173.05:48:39.52#ibcon#end of sib2, iclass 21, count 0 2006.173.05:48:39.52#ibcon#*mode == 0, iclass 21, count 0 2006.173.05:48:39.52#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.05:48:39.52#ibcon#[27=USB\r\n] 2006.173.05:48:39.52#ibcon#*before write, iclass 21, count 0 2006.173.05:48:39.52#ibcon#enter sib2, iclass 21, count 0 2006.173.05:48:39.52#ibcon#flushed, iclass 21, count 0 2006.173.05:48:39.52#ibcon#about to write, iclass 21, count 0 2006.173.05:48:39.52#ibcon#wrote, iclass 21, count 0 2006.173.05:48:39.52#ibcon#about to read 3, iclass 21, count 0 2006.173.05:48:39.55#ibcon#read 3, iclass 21, count 0 2006.173.05:48:39.55#ibcon#about to read 4, iclass 21, count 0 2006.173.05:48:39.55#ibcon#read 4, iclass 21, count 0 2006.173.05:48:39.55#ibcon#about to read 5, iclass 21, count 0 2006.173.05:48:39.55#ibcon#read 5, iclass 21, count 0 2006.173.05:48:39.55#ibcon#about to read 6, iclass 21, count 0 2006.173.05:48:39.55#ibcon#read 6, iclass 21, count 0 2006.173.05:48:39.55#ibcon#end of sib2, iclass 21, count 0 2006.173.05:48:39.55#ibcon#*after write, iclass 21, count 0 2006.173.05:48:39.55#ibcon#*before return 0, iclass 21, count 0 2006.173.05:48:39.55#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.05:48:39.55#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.05:48:39.55#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.05:48:39.55#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.05:48:39.55$vck44/vblo=6,719.99 2006.173.05:48:39.55#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.05:48:39.55#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.05:48:39.55#ibcon#ireg 17 cls_cnt 0 2006.173.05:48:39.55#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.05:48:39.55#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.05:48:39.55#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.05:48:39.55#ibcon#enter wrdev, iclass 23, count 0 2006.173.05:48:39.55#ibcon#first serial, iclass 23, count 0 2006.173.05:48:39.55#ibcon#enter sib2, iclass 23, count 0 2006.173.05:48:39.55#ibcon#flushed, iclass 23, count 0 2006.173.05:48:39.55#ibcon#about to write, iclass 23, count 0 2006.173.05:48:39.55#ibcon#wrote, iclass 23, count 0 2006.173.05:48:39.55#ibcon#about to read 3, iclass 23, count 0 2006.173.05:48:39.57#ibcon#read 3, iclass 23, count 0 2006.173.05:48:39.57#ibcon#about to read 4, iclass 23, count 0 2006.173.05:48:39.57#ibcon#read 4, iclass 23, count 0 2006.173.05:48:39.57#ibcon#about to read 5, iclass 23, count 0 2006.173.05:48:39.57#ibcon#read 5, iclass 23, count 0 2006.173.05:48:39.57#ibcon#about to read 6, iclass 23, count 0 2006.173.05:48:39.57#ibcon#read 6, iclass 23, count 0 2006.173.05:48:39.57#ibcon#end of sib2, iclass 23, count 0 2006.173.05:48:39.57#ibcon#*mode == 0, iclass 23, count 0 2006.173.05:48:39.57#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.05:48:39.57#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.05:48:39.57#ibcon#*before write, iclass 23, count 0 2006.173.05:48:39.57#ibcon#enter sib2, iclass 23, count 0 2006.173.05:48:39.57#ibcon#flushed, iclass 23, count 0 2006.173.05:48:39.57#ibcon#about to write, iclass 23, count 0 2006.173.05:48:39.57#ibcon#wrote, iclass 23, count 0 2006.173.05:48:39.57#ibcon#about to read 3, iclass 23, count 0 2006.173.05:48:39.61#ibcon#read 3, iclass 23, count 0 2006.173.05:48:39.61#ibcon#about to read 4, iclass 23, count 0 2006.173.05:48:39.61#ibcon#read 4, iclass 23, count 0 2006.173.05:48:39.61#ibcon#about to read 5, iclass 23, count 0 2006.173.05:48:39.61#ibcon#read 5, iclass 23, count 0 2006.173.05:48:39.61#ibcon#about to read 6, iclass 23, count 0 2006.173.05:48:39.61#ibcon#read 6, iclass 23, count 0 2006.173.05:48:39.61#ibcon#end of sib2, iclass 23, count 0 2006.173.05:48:39.61#ibcon#*after write, iclass 23, count 0 2006.173.05:48:39.61#ibcon#*before return 0, iclass 23, count 0 2006.173.05:48:39.61#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.05:48:39.61#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.05:48:39.61#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.05:48:39.61#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.05:48:39.61$vck44/vb=6,4 2006.173.05:48:39.61#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.05:48:39.61#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.05:48:39.61#ibcon#ireg 11 cls_cnt 2 2006.173.05:48:39.61#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.05:48:39.67#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.05:48:39.67#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.05:48:39.67#ibcon#enter wrdev, iclass 25, count 2 2006.173.05:48:39.67#ibcon#first serial, iclass 25, count 2 2006.173.05:48:39.67#ibcon#enter sib2, iclass 25, count 2 2006.173.05:48:39.67#ibcon#flushed, iclass 25, count 2 2006.173.05:48:39.67#ibcon#about to write, iclass 25, count 2 2006.173.05:48:39.67#ibcon#wrote, iclass 25, count 2 2006.173.05:48:39.67#ibcon#about to read 3, iclass 25, count 2 2006.173.05:48:39.69#ibcon#read 3, iclass 25, count 2 2006.173.05:48:39.69#ibcon#about to read 4, iclass 25, count 2 2006.173.05:48:39.69#ibcon#read 4, iclass 25, count 2 2006.173.05:48:39.69#ibcon#about to read 5, iclass 25, count 2 2006.173.05:48:39.69#ibcon#read 5, iclass 25, count 2 2006.173.05:48:39.69#ibcon#about to read 6, iclass 25, count 2 2006.173.05:48:39.69#ibcon#read 6, iclass 25, count 2 2006.173.05:48:39.69#ibcon#end of sib2, iclass 25, count 2 2006.173.05:48:39.69#ibcon#*mode == 0, iclass 25, count 2 2006.173.05:48:39.69#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.05:48:39.69#ibcon#[27=AT06-04\r\n] 2006.173.05:48:39.69#ibcon#*before write, iclass 25, count 2 2006.173.05:48:39.69#ibcon#enter sib2, iclass 25, count 2 2006.173.05:48:39.69#ibcon#flushed, iclass 25, count 2 2006.173.05:48:39.69#ibcon#about to write, iclass 25, count 2 2006.173.05:48:39.69#ibcon#wrote, iclass 25, count 2 2006.173.05:48:39.69#ibcon#about to read 3, iclass 25, count 2 2006.173.05:48:39.72#ibcon#read 3, iclass 25, count 2 2006.173.05:48:39.72#ibcon#about to read 4, iclass 25, count 2 2006.173.05:48:39.72#ibcon#read 4, iclass 25, count 2 2006.173.05:48:39.72#ibcon#about to read 5, iclass 25, count 2 2006.173.05:48:39.72#ibcon#read 5, iclass 25, count 2 2006.173.05:48:39.72#ibcon#about to read 6, iclass 25, count 2 2006.173.05:48:39.72#ibcon#read 6, iclass 25, count 2 2006.173.05:48:39.72#ibcon#end of sib2, iclass 25, count 2 2006.173.05:48:39.72#ibcon#*after write, iclass 25, count 2 2006.173.05:48:39.72#ibcon#*before return 0, iclass 25, count 2 2006.173.05:48:39.72#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.05:48:39.72#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.05:48:39.72#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.05:48:39.72#ibcon#ireg 7 cls_cnt 0 2006.173.05:48:39.72#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.05:48:39.84#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.05:48:39.84#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.05:48:39.84#ibcon#enter wrdev, iclass 25, count 0 2006.173.05:48:39.84#ibcon#first serial, iclass 25, count 0 2006.173.05:48:39.84#ibcon#enter sib2, iclass 25, count 0 2006.173.05:48:39.84#ibcon#flushed, iclass 25, count 0 2006.173.05:48:39.84#ibcon#about to write, iclass 25, count 0 2006.173.05:48:39.84#ibcon#wrote, iclass 25, count 0 2006.173.05:48:39.84#ibcon#about to read 3, iclass 25, count 0 2006.173.05:48:39.86#ibcon#read 3, iclass 25, count 0 2006.173.05:48:39.86#ibcon#about to read 4, iclass 25, count 0 2006.173.05:48:39.86#ibcon#read 4, iclass 25, count 0 2006.173.05:48:39.86#ibcon#about to read 5, iclass 25, count 0 2006.173.05:48:39.86#ibcon#read 5, iclass 25, count 0 2006.173.05:48:39.86#ibcon#about to read 6, iclass 25, count 0 2006.173.05:48:39.86#ibcon#read 6, iclass 25, count 0 2006.173.05:48:39.86#ibcon#end of sib2, iclass 25, count 0 2006.173.05:48:39.86#ibcon#*mode == 0, iclass 25, count 0 2006.173.05:48:39.86#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.05:48:39.86#ibcon#[27=USB\r\n] 2006.173.05:48:39.86#ibcon#*before write, iclass 25, count 0 2006.173.05:48:39.86#ibcon#enter sib2, iclass 25, count 0 2006.173.05:48:39.86#ibcon#flushed, iclass 25, count 0 2006.173.05:48:39.86#ibcon#about to write, iclass 25, count 0 2006.173.05:48:39.86#ibcon#wrote, iclass 25, count 0 2006.173.05:48:39.86#ibcon#about to read 3, iclass 25, count 0 2006.173.05:48:39.89#ibcon#read 3, iclass 25, count 0 2006.173.05:48:39.89#ibcon#about to read 4, iclass 25, count 0 2006.173.05:48:39.89#ibcon#read 4, iclass 25, count 0 2006.173.05:48:39.89#ibcon#about to read 5, iclass 25, count 0 2006.173.05:48:39.89#ibcon#read 5, iclass 25, count 0 2006.173.05:48:39.89#ibcon#about to read 6, iclass 25, count 0 2006.173.05:48:39.89#ibcon#read 6, iclass 25, count 0 2006.173.05:48:39.89#ibcon#end of sib2, iclass 25, count 0 2006.173.05:48:39.89#ibcon#*after write, iclass 25, count 0 2006.173.05:48:39.89#ibcon#*before return 0, iclass 25, count 0 2006.173.05:48:39.89#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.05:48:39.89#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.05:48:39.89#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.05:48:39.89#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.05:48:39.89$vck44/vblo=7,734.99 2006.173.05:48:39.89#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.05:48:39.89#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.05:48:39.89#ibcon#ireg 17 cls_cnt 0 2006.173.05:48:39.89#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.05:48:39.89#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.05:48:39.89#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.05:48:39.89#ibcon#enter wrdev, iclass 27, count 0 2006.173.05:48:39.89#ibcon#first serial, iclass 27, count 0 2006.173.05:48:39.89#ibcon#enter sib2, iclass 27, count 0 2006.173.05:48:39.89#ibcon#flushed, iclass 27, count 0 2006.173.05:48:39.89#ibcon#about to write, iclass 27, count 0 2006.173.05:48:39.89#ibcon#wrote, iclass 27, count 0 2006.173.05:48:39.89#ibcon#about to read 3, iclass 27, count 0 2006.173.05:48:39.91#ibcon#read 3, iclass 27, count 0 2006.173.05:48:39.91#ibcon#about to read 4, iclass 27, count 0 2006.173.05:48:39.91#ibcon#read 4, iclass 27, count 0 2006.173.05:48:39.91#ibcon#about to read 5, iclass 27, count 0 2006.173.05:48:39.91#ibcon#read 5, iclass 27, count 0 2006.173.05:48:39.91#ibcon#about to read 6, iclass 27, count 0 2006.173.05:48:39.91#ibcon#read 6, iclass 27, count 0 2006.173.05:48:39.91#ibcon#end of sib2, iclass 27, count 0 2006.173.05:48:39.91#ibcon#*mode == 0, iclass 27, count 0 2006.173.05:48:39.91#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.05:48:39.91#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.05:48:39.91#ibcon#*before write, iclass 27, count 0 2006.173.05:48:39.91#ibcon#enter sib2, iclass 27, count 0 2006.173.05:48:39.91#ibcon#flushed, iclass 27, count 0 2006.173.05:48:39.91#ibcon#about to write, iclass 27, count 0 2006.173.05:48:39.91#ibcon#wrote, iclass 27, count 0 2006.173.05:48:39.91#ibcon#about to read 3, iclass 27, count 0 2006.173.05:48:39.95#ibcon#read 3, iclass 27, count 0 2006.173.05:48:39.95#ibcon#about to read 4, iclass 27, count 0 2006.173.05:48:39.95#ibcon#read 4, iclass 27, count 0 2006.173.05:48:39.95#ibcon#about to read 5, iclass 27, count 0 2006.173.05:48:39.95#ibcon#read 5, iclass 27, count 0 2006.173.05:48:39.95#ibcon#about to read 6, iclass 27, count 0 2006.173.05:48:39.95#ibcon#read 6, iclass 27, count 0 2006.173.05:48:39.95#ibcon#end of sib2, iclass 27, count 0 2006.173.05:48:39.95#ibcon#*after write, iclass 27, count 0 2006.173.05:48:39.95#ibcon#*before return 0, iclass 27, count 0 2006.173.05:48:39.95#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.05:48:39.95#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.05:48:39.95#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.05:48:39.95#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.05:48:39.95$vck44/vb=7,4 2006.173.05:48:39.95#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.05:48:39.95#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.05:48:39.95#ibcon#ireg 11 cls_cnt 2 2006.173.05:48:39.95#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.05:48:40.01#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.05:48:40.01#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.05:48:40.01#ibcon#enter wrdev, iclass 29, count 2 2006.173.05:48:40.01#ibcon#first serial, iclass 29, count 2 2006.173.05:48:40.01#ibcon#enter sib2, iclass 29, count 2 2006.173.05:48:40.01#ibcon#flushed, iclass 29, count 2 2006.173.05:48:40.01#ibcon#about to write, iclass 29, count 2 2006.173.05:48:40.01#ibcon#wrote, iclass 29, count 2 2006.173.05:48:40.01#ibcon#about to read 3, iclass 29, count 2 2006.173.05:48:40.03#ibcon#read 3, iclass 29, count 2 2006.173.05:48:40.03#ibcon#about to read 4, iclass 29, count 2 2006.173.05:48:40.03#ibcon#read 4, iclass 29, count 2 2006.173.05:48:40.03#ibcon#about to read 5, iclass 29, count 2 2006.173.05:48:40.03#ibcon#read 5, iclass 29, count 2 2006.173.05:48:40.03#ibcon#about to read 6, iclass 29, count 2 2006.173.05:48:40.03#ibcon#read 6, iclass 29, count 2 2006.173.05:48:40.03#ibcon#end of sib2, iclass 29, count 2 2006.173.05:48:40.03#ibcon#*mode == 0, iclass 29, count 2 2006.173.05:48:40.03#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.05:48:40.03#ibcon#[27=AT07-04\r\n] 2006.173.05:48:40.03#ibcon#*before write, iclass 29, count 2 2006.173.05:48:40.03#ibcon#enter sib2, iclass 29, count 2 2006.173.05:48:40.03#ibcon#flushed, iclass 29, count 2 2006.173.05:48:40.03#ibcon#about to write, iclass 29, count 2 2006.173.05:48:40.03#ibcon#wrote, iclass 29, count 2 2006.173.05:48:40.03#ibcon#about to read 3, iclass 29, count 2 2006.173.05:48:40.06#ibcon#read 3, iclass 29, count 2 2006.173.05:48:40.06#ibcon#about to read 4, iclass 29, count 2 2006.173.05:48:40.06#ibcon#read 4, iclass 29, count 2 2006.173.05:48:40.06#ibcon#about to read 5, iclass 29, count 2 2006.173.05:48:40.06#ibcon#read 5, iclass 29, count 2 2006.173.05:48:40.06#ibcon#about to read 6, iclass 29, count 2 2006.173.05:48:40.06#ibcon#read 6, iclass 29, count 2 2006.173.05:48:40.06#ibcon#end of sib2, iclass 29, count 2 2006.173.05:48:40.06#ibcon#*after write, iclass 29, count 2 2006.173.05:48:40.06#ibcon#*before return 0, iclass 29, count 2 2006.173.05:48:40.06#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.05:48:40.06#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.05:48:40.06#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.05:48:40.06#ibcon#ireg 7 cls_cnt 0 2006.173.05:48:40.06#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.05:48:40.18#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.05:48:40.18#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.05:48:40.18#ibcon#enter wrdev, iclass 29, count 0 2006.173.05:48:40.18#ibcon#first serial, iclass 29, count 0 2006.173.05:48:40.18#ibcon#enter sib2, iclass 29, count 0 2006.173.05:48:40.18#ibcon#flushed, iclass 29, count 0 2006.173.05:48:40.18#ibcon#about to write, iclass 29, count 0 2006.173.05:48:40.18#ibcon#wrote, iclass 29, count 0 2006.173.05:48:40.18#ibcon#about to read 3, iclass 29, count 0 2006.173.05:48:40.20#ibcon#read 3, iclass 29, count 0 2006.173.05:48:40.20#ibcon#about to read 4, iclass 29, count 0 2006.173.05:48:40.20#ibcon#read 4, iclass 29, count 0 2006.173.05:48:40.20#ibcon#about to read 5, iclass 29, count 0 2006.173.05:48:40.20#ibcon#read 5, iclass 29, count 0 2006.173.05:48:40.20#ibcon#about to read 6, iclass 29, count 0 2006.173.05:48:40.20#ibcon#read 6, iclass 29, count 0 2006.173.05:48:40.20#ibcon#end of sib2, iclass 29, count 0 2006.173.05:48:40.20#ibcon#*mode == 0, iclass 29, count 0 2006.173.05:48:40.20#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.05:48:40.20#ibcon#[27=USB\r\n] 2006.173.05:48:40.20#ibcon#*before write, iclass 29, count 0 2006.173.05:48:40.20#ibcon#enter sib2, iclass 29, count 0 2006.173.05:48:40.20#ibcon#flushed, iclass 29, count 0 2006.173.05:48:40.20#ibcon#about to write, iclass 29, count 0 2006.173.05:48:40.20#ibcon#wrote, iclass 29, count 0 2006.173.05:48:40.20#ibcon#about to read 3, iclass 29, count 0 2006.173.05:48:40.23#ibcon#read 3, iclass 29, count 0 2006.173.05:48:40.23#ibcon#about to read 4, iclass 29, count 0 2006.173.05:48:40.23#ibcon#read 4, iclass 29, count 0 2006.173.05:48:40.23#ibcon#about to read 5, iclass 29, count 0 2006.173.05:48:40.23#ibcon#read 5, iclass 29, count 0 2006.173.05:48:40.23#ibcon#about to read 6, iclass 29, count 0 2006.173.05:48:40.23#ibcon#read 6, iclass 29, count 0 2006.173.05:48:40.23#ibcon#end of sib2, iclass 29, count 0 2006.173.05:48:40.23#ibcon#*after write, iclass 29, count 0 2006.173.05:48:40.23#ibcon#*before return 0, iclass 29, count 0 2006.173.05:48:40.23#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.05:48:40.23#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.05:48:40.23#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.05:48:40.23#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.05:48:40.23$vck44/vblo=8,744.99 2006.173.05:48:40.23#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.05:48:40.23#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.05:48:40.23#ibcon#ireg 17 cls_cnt 0 2006.173.05:48:40.23#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.05:48:40.23#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.05:48:40.23#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.05:48:40.23#ibcon#enter wrdev, iclass 31, count 0 2006.173.05:48:40.23#ibcon#first serial, iclass 31, count 0 2006.173.05:48:40.23#ibcon#enter sib2, iclass 31, count 0 2006.173.05:48:40.23#ibcon#flushed, iclass 31, count 0 2006.173.05:48:40.23#ibcon#about to write, iclass 31, count 0 2006.173.05:48:40.23#ibcon#wrote, iclass 31, count 0 2006.173.05:48:40.23#ibcon#about to read 3, iclass 31, count 0 2006.173.05:48:40.25#ibcon#read 3, iclass 31, count 0 2006.173.05:48:40.25#ibcon#about to read 4, iclass 31, count 0 2006.173.05:48:40.25#ibcon#read 4, iclass 31, count 0 2006.173.05:48:40.25#ibcon#about to read 5, iclass 31, count 0 2006.173.05:48:40.25#ibcon#read 5, iclass 31, count 0 2006.173.05:48:40.25#ibcon#about to read 6, iclass 31, count 0 2006.173.05:48:40.25#ibcon#read 6, iclass 31, count 0 2006.173.05:48:40.25#ibcon#end of sib2, iclass 31, count 0 2006.173.05:48:40.25#ibcon#*mode == 0, iclass 31, count 0 2006.173.05:48:40.25#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.05:48:40.25#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.05:48:40.25#ibcon#*before write, iclass 31, count 0 2006.173.05:48:40.25#ibcon#enter sib2, iclass 31, count 0 2006.173.05:48:40.25#ibcon#flushed, iclass 31, count 0 2006.173.05:48:40.25#ibcon#about to write, iclass 31, count 0 2006.173.05:48:40.25#ibcon#wrote, iclass 31, count 0 2006.173.05:48:40.25#ibcon#about to read 3, iclass 31, count 0 2006.173.05:48:40.29#ibcon#read 3, iclass 31, count 0 2006.173.05:48:40.29#ibcon#about to read 4, iclass 31, count 0 2006.173.05:48:40.29#ibcon#read 4, iclass 31, count 0 2006.173.05:48:40.29#ibcon#about to read 5, iclass 31, count 0 2006.173.05:48:40.29#ibcon#read 5, iclass 31, count 0 2006.173.05:48:40.29#ibcon#about to read 6, iclass 31, count 0 2006.173.05:48:40.29#ibcon#read 6, iclass 31, count 0 2006.173.05:48:40.29#ibcon#end of sib2, iclass 31, count 0 2006.173.05:48:40.29#ibcon#*after write, iclass 31, count 0 2006.173.05:48:40.29#ibcon#*before return 0, iclass 31, count 0 2006.173.05:48:40.29#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.05:48:40.29#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.05:48:40.29#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.05:48:40.29#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.05:48:40.29$vck44/vb=8,4 2006.173.05:48:40.29#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.173.05:48:40.29#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.173.05:48:40.29#ibcon#ireg 11 cls_cnt 2 2006.173.05:48:40.29#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.05:48:40.35#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.05:48:40.35#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.05:48:40.35#ibcon#enter wrdev, iclass 33, count 2 2006.173.05:48:40.35#ibcon#first serial, iclass 33, count 2 2006.173.05:48:40.35#ibcon#enter sib2, iclass 33, count 2 2006.173.05:48:40.35#ibcon#flushed, iclass 33, count 2 2006.173.05:48:40.35#ibcon#about to write, iclass 33, count 2 2006.173.05:48:40.35#ibcon#wrote, iclass 33, count 2 2006.173.05:48:40.35#ibcon#about to read 3, iclass 33, count 2 2006.173.05:48:40.37#ibcon#read 3, iclass 33, count 2 2006.173.05:48:40.37#ibcon#about to read 4, iclass 33, count 2 2006.173.05:48:40.37#ibcon#read 4, iclass 33, count 2 2006.173.05:48:40.37#ibcon#about to read 5, iclass 33, count 2 2006.173.05:48:40.37#ibcon#read 5, iclass 33, count 2 2006.173.05:48:40.37#ibcon#about to read 6, iclass 33, count 2 2006.173.05:48:40.37#ibcon#read 6, iclass 33, count 2 2006.173.05:48:40.37#ibcon#end of sib2, iclass 33, count 2 2006.173.05:48:40.37#ibcon#*mode == 0, iclass 33, count 2 2006.173.05:48:40.37#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.173.05:48:40.37#ibcon#[27=AT08-04\r\n] 2006.173.05:48:40.37#ibcon#*before write, iclass 33, count 2 2006.173.05:48:40.37#ibcon#enter sib2, iclass 33, count 2 2006.173.05:48:40.37#ibcon#flushed, iclass 33, count 2 2006.173.05:48:40.37#ibcon#about to write, iclass 33, count 2 2006.173.05:48:40.37#ibcon#wrote, iclass 33, count 2 2006.173.05:48:40.37#ibcon#about to read 3, iclass 33, count 2 2006.173.05:48:40.40#ibcon#read 3, iclass 33, count 2 2006.173.05:48:40.40#ibcon#about to read 4, iclass 33, count 2 2006.173.05:48:40.40#ibcon#read 4, iclass 33, count 2 2006.173.05:48:40.40#ibcon#about to read 5, iclass 33, count 2 2006.173.05:48:40.40#ibcon#read 5, iclass 33, count 2 2006.173.05:48:40.40#ibcon#about to read 6, iclass 33, count 2 2006.173.05:48:40.40#ibcon#read 6, iclass 33, count 2 2006.173.05:48:40.40#ibcon#end of sib2, iclass 33, count 2 2006.173.05:48:40.40#ibcon#*after write, iclass 33, count 2 2006.173.05:48:40.40#ibcon#*before return 0, iclass 33, count 2 2006.173.05:48:40.40#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.05:48:40.40#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.173.05:48:40.40#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.173.05:48:40.40#ibcon#ireg 7 cls_cnt 0 2006.173.05:48:40.40#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.05:48:40.52#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.05:48:40.52#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.05:48:40.52#ibcon#enter wrdev, iclass 33, count 0 2006.173.05:48:40.52#ibcon#first serial, iclass 33, count 0 2006.173.05:48:40.52#ibcon#enter sib2, iclass 33, count 0 2006.173.05:48:40.52#ibcon#flushed, iclass 33, count 0 2006.173.05:48:40.52#ibcon#about to write, iclass 33, count 0 2006.173.05:48:40.52#ibcon#wrote, iclass 33, count 0 2006.173.05:48:40.52#ibcon#about to read 3, iclass 33, count 0 2006.173.05:48:40.54#ibcon#read 3, iclass 33, count 0 2006.173.05:48:40.54#ibcon#about to read 4, iclass 33, count 0 2006.173.05:48:40.54#ibcon#read 4, iclass 33, count 0 2006.173.05:48:40.54#ibcon#about to read 5, iclass 33, count 0 2006.173.05:48:40.54#ibcon#read 5, iclass 33, count 0 2006.173.05:48:40.54#ibcon#about to read 6, iclass 33, count 0 2006.173.05:48:40.54#ibcon#read 6, iclass 33, count 0 2006.173.05:48:40.54#ibcon#end of sib2, iclass 33, count 0 2006.173.05:48:40.54#ibcon#*mode == 0, iclass 33, count 0 2006.173.05:48:40.54#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.05:48:40.54#ibcon#[27=USB\r\n] 2006.173.05:48:40.54#ibcon#*before write, iclass 33, count 0 2006.173.05:48:40.54#ibcon#enter sib2, iclass 33, count 0 2006.173.05:48:40.54#ibcon#flushed, iclass 33, count 0 2006.173.05:48:40.54#ibcon#about to write, iclass 33, count 0 2006.173.05:48:40.54#ibcon#wrote, iclass 33, count 0 2006.173.05:48:40.54#ibcon#about to read 3, iclass 33, count 0 2006.173.05:48:40.57#ibcon#read 3, iclass 33, count 0 2006.173.05:48:40.57#ibcon#about to read 4, iclass 33, count 0 2006.173.05:48:40.57#ibcon#read 4, iclass 33, count 0 2006.173.05:48:40.57#ibcon#about to read 5, iclass 33, count 0 2006.173.05:48:40.57#ibcon#read 5, iclass 33, count 0 2006.173.05:48:40.57#ibcon#about to read 6, iclass 33, count 0 2006.173.05:48:40.57#ibcon#read 6, iclass 33, count 0 2006.173.05:48:40.57#ibcon#end of sib2, iclass 33, count 0 2006.173.05:48:40.57#ibcon#*after write, iclass 33, count 0 2006.173.05:48:40.57#ibcon#*before return 0, iclass 33, count 0 2006.173.05:48:40.57#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.05:48:40.57#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.173.05:48:40.57#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.05:48:40.57#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.05:48:40.57$vck44/vabw=wide 2006.173.05:48:40.57#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.05:48:40.57#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.05:48:40.57#ibcon#ireg 8 cls_cnt 0 2006.173.05:48:40.57#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.05:48:40.57#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.05:48:40.57#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.05:48:40.57#ibcon#enter wrdev, iclass 35, count 0 2006.173.05:48:40.57#ibcon#first serial, iclass 35, count 0 2006.173.05:48:40.57#ibcon#enter sib2, iclass 35, count 0 2006.173.05:48:40.57#ibcon#flushed, iclass 35, count 0 2006.173.05:48:40.57#ibcon#about to write, iclass 35, count 0 2006.173.05:48:40.57#ibcon#wrote, iclass 35, count 0 2006.173.05:48:40.57#ibcon#about to read 3, iclass 35, count 0 2006.173.05:48:40.59#ibcon#read 3, iclass 35, count 0 2006.173.05:48:40.59#ibcon#about to read 4, iclass 35, count 0 2006.173.05:48:40.59#ibcon#read 4, iclass 35, count 0 2006.173.05:48:40.59#ibcon#about to read 5, iclass 35, count 0 2006.173.05:48:40.59#ibcon#read 5, iclass 35, count 0 2006.173.05:48:40.59#ibcon#about to read 6, iclass 35, count 0 2006.173.05:48:40.59#ibcon#read 6, iclass 35, count 0 2006.173.05:48:40.59#ibcon#end of sib2, iclass 35, count 0 2006.173.05:48:40.59#ibcon#*mode == 0, iclass 35, count 0 2006.173.05:48:40.59#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.05:48:40.59#ibcon#[25=BW32\r\n] 2006.173.05:48:40.59#ibcon#*before write, iclass 35, count 0 2006.173.05:48:40.59#ibcon#enter sib2, iclass 35, count 0 2006.173.05:48:40.59#ibcon#flushed, iclass 35, count 0 2006.173.05:48:40.59#ibcon#about to write, iclass 35, count 0 2006.173.05:48:40.59#ibcon#wrote, iclass 35, count 0 2006.173.05:48:40.59#ibcon#about to read 3, iclass 35, count 0 2006.173.05:48:40.62#ibcon#read 3, iclass 35, count 0 2006.173.05:48:40.62#ibcon#about to read 4, iclass 35, count 0 2006.173.05:48:40.62#ibcon#read 4, iclass 35, count 0 2006.173.05:48:40.62#ibcon#about to read 5, iclass 35, count 0 2006.173.05:48:40.62#ibcon#read 5, iclass 35, count 0 2006.173.05:48:40.62#ibcon#about to read 6, iclass 35, count 0 2006.173.05:48:40.62#ibcon#read 6, iclass 35, count 0 2006.173.05:48:40.62#ibcon#end of sib2, iclass 35, count 0 2006.173.05:48:40.62#ibcon#*after write, iclass 35, count 0 2006.173.05:48:40.62#ibcon#*before return 0, iclass 35, count 0 2006.173.05:48:40.62#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.05:48:40.62#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.05:48:40.62#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.05:48:40.62#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.05:48:40.62$vck44/vbbw=wide 2006.173.05:48:40.62#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.05:48:40.62#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.05:48:40.62#ibcon#ireg 8 cls_cnt 0 2006.173.05:48:40.62#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.05:48:40.69#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.05:48:40.69#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.05:48:40.69#ibcon#enter wrdev, iclass 37, count 0 2006.173.05:48:40.69#ibcon#first serial, iclass 37, count 0 2006.173.05:48:40.69#ibcon#enter sib2, iclass 37, count 0 2006.173.05:48:40.69#ibcon#flushed, iclass 37, count 0 2006.173.05:48:40.69#ibcon#about to write, iclass 37, count 0 2006.173.05:48:40.69#ibcon#wrote, iclass 37, count 0 2006.173.05:48:40.69#ibcon#about to read 3, iclass 37, count 0 2006.173.05:48:40.71#ibcon#read 3, iclass 37, count 0 2006.173.05:48:40.71#ibcon#about to read 4, iclass 37, count 0 2006.173.05:48:40.71#ibcon#read 4, iclass 37, count 0 2006.173.05:48:40.71#ibcon#about to read 5, iclass 37, count 0 2006.173.05:48:40.71#ibcon#read 5, iclass 37, count 0 2006.173.05:48:40.71#ibcon#about to read 6, iclass 37, count 0 2006.173.05:48:40.71#ibcon#read 6, iclass 37, count 0 2006.173.05:48:40.71#ibcon#end of sib2, iclass 37, count 0 2006.173.05:48:40.71#ibcon#*mode == 0, iclass 37, count 0 2006.173.05:48:40.71#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.05:48:40.71#ibcon#[27=BW32\r\n] 2006.173.05:48:40.71#ibcon#*before write, iclass 37, count 0 2006.173.05:48:40.71#ibcon#enter sib2, iclass 37, count 0 2006.173.05:48:40.71#ibcon#flushed, iclass 37, count 0 2006.173.05:48:40.71#ibcon#about to write, iclass 37, count 0 2006.173.05:48:40.71#ibcon#wrote, iclass 37, count 0 2006.173.05:48:40.71#ibcon#about to read 3, iclass 37, count 0 2006.173.05:48:40.74#ibcon#read 3, iclass 37, count 0 2006.173.05:48:40.74#ibcon#about to read 4, iclass 37, count 0 2006.173.05:48:40.74#ibcon#read 4, iclass 37, count 0 2006.173.05:48:40.74#ibcon#about to read 5, iclass 37, count 0 2006.173.05:48:40.74#ibcon#read 5, iclass 37, count 0 2006.173.05:48:40.74#ibcon#about to read 6, iclass 37, count 0 2006.173.05:48:40.74#ibcon#read 6, iclass 37, count 0 2006.173.05:48:40.74#ibcon#end of sib2, iclass 37, count 0 2006.173.05:48:40.74#ibcon#*after write, iclass 37, count 0 2006.173.05:48:40.74#ibcon#*before return 0, iclass 37, count 0 2006.173.05:48:40.74#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.05:48:40.74#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.05:48:40.74#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.05:48:40.74#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.05:48:40.74$setupk4/ifdk4 2006.173.05:48:40.74$ifdk4/lo= 2006.173.05:48:40.74$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.05:48:40.74$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.05:48:40.74$ifdk4/patch= 2006.173.05:48:40.74$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.05:48:40.74$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.05:48:40.74$setupk4/!*+20s 2006.173.05:48:45.80#abcon#<5=/15 0.6 1.3 23.60 781005.3\r\n> 2006.173.05:48:45.82#abcon#{5=INTERFACE CLEAR} 2006.173.05:48:45.88#abcon#[5=S1D000X0/0*\r\n] 2006.173.05:48:55.24$setupk4/"tpicd 2006.173.05:48:55.24$setupk4/echo=off 2006.173.05:48:55.24$setupk4/xlog=off 2006.173.05:48:55.24:!2006.173.05:50:26 2006.173.05:49:05.14#trakl#Source acquired 2006.173.05:49:07.14#flagr#flagr/antenna,acquired 2006.173.05:50:26.00:preob 2006.173.05:50:26.14/onsource/TRACKING 2006.173.05:50:26.14:!2006.173.05:50:36 2006.173.05:50:36.00:"tape 2006.173.05:50:36.00:"st=record 2006.173.05:50:36.00:data_valid=on 2006.173.05:50:36.00:midob 2006.173.05:50:37.14/onsource/TRACKING 2006.173.05:50:37.14/wx/23.61,1005.3,76 2006.173.05:50:37.29/cable/+6.5069E-03 2006.173.05:50:38.38/va/01,07,usb,yes,35,38 2006.173.05:50:38.38/va/02,06,usb,yes,35,36 2006.173.05:50:38.38/va/03,05,usb,yes,45,47 2006.173.05:50:38.38/va/04,06,usb,yes,36,38 2006.173.05:50:38.38/va/05,04,usb,yes,28,29 2006.173.05:50:38.38/va/06,03,usb,yes,39,39 2006.173.05:50:38.38/va/07,04,usb,yes,32,33 2006.173.05:50:38.38/va/08,04,usb,yes,27,33 2006.173.05:50:38.61/valo/01,524.99,yes,locked 2006.173.05:50:38.61/valo/02,534.99,yes,locked 2006.173.05:50:38.61/valo/03,564.99,yes,locked 2006.173.05:50:38.61/valo/04,624.99,yes,locked 2006.173.05:50:38.61/valo/05,734.99,yes,locked 2006.173.05:50:38.61/valo/06,814.99,yes,locked 2006.173.05:50:38.61/valo/07,864.99,yes,locked 2006.173.05:50:38.61/valo/08,884.99,yes,locked 2006.173.05:50:39.70/vb/01,04,usb,yes,30,27 2006.173.05:50:39.70/vb/02,04,usb,yes,32,32 2006.173.05:50:39.70/vb/03,04,usb,yes,29,32 2006.173.05:50:39.70/vb/04,04,usb,yes,33,32 2006.173.05:50:39.70/vb/05,04,usb,yes,26,28 2006.173.05:50:39.70/vb/06,04,usb,yes,30,26 2006.173.05:50:39.70/vb/07,04,usb,yes,30,30 2006.173.05:50:39.70/vb/08,04,usb,yes,27,31 2006.173.05:50:39.93/vblo/01,629.99,yes,locked 2006.173.05:50:39.93/vblo/02,634.99,yes,locked 2006.173.05:50:39.93/vblo/03,649.99,yes,locked 2006.173.05:50:39.93/vblo/04,679.99,yes,locked 2006.173.05:50:39.93/vblo/05,709.99,yes,locked 2006.173.05:50:39.93/vblo/06,719.99,yes,locked 2006.173.05:50:39.93/vblo/07,734.99,yes,locked 2006.173.05:50:39.93/vblo/08,744.99,yes,locked 2006.173.05:50:40.08/vabw/8 2006.173.05:50:40.23/vbbw/8 2006.173.05:50:40.32/xfe/off,on,15.0 2006.173.05:50:40.70/ifatt/23,28,28,28 2006.173.05:50:41.07/fmout-gps/S +4.02E-07 2006.173.05:50:41.11:!2006.173.05:51:36 2006.173.05:51:36.00:data_valid=off 2006.173.05:51:36.00:"et 2006.173.05:51:36.00:!+3s 2006.173.05:51:39.01:"tape 2006.173.05:51:39.01:postob 2006.173.05:51:39.20/cable/+6.5038E-03 2006.173.05:51:39.20/wx/23.64,1005.3,77 2006.173.05:51:40.08/fmout-gps/S +4.02E-07 2006.173.05:51:40.08:scan_name=173-0553,jd0606,90 2006.173.05:51:40.08:source=3c274,123049.42,122328.0,2000.0,ccw 2006.173.05:51:40.14#flagr#flagr/antenna,new-source 2006.173.05:51:41.14:checkk5 2006.173.05:51:41.48/chk_autoobs//k5ts1/ autoobs is running! 2006.173.05:51:41.88/chk_autoobs//k5ts2/ autoobs is running! 2006.173.05:51:42.30/chk_autoobs//k5ts3/ autoobs is running! 2006.173.05:51:42.69/chk_autoobs//k5ts4/ autoobs is running! 2006.173.05:51:43.08/chk_obsdata//k5ts1/T1730550??a.dat file size is correct (nominal:240MB, actual:240MB). 2006.173.05:51:43.49/chk_obsdata//k5ts2/T1730550??b.dat file size is correct (nominal:240MB, actual:240MB). 2006.173.05:51:43.89/chk_obsdata//k5ts3/T1730550??c.dat file size is correct (nominal:240MB, actual:240MB). 2006.173.05:51:44.30/chk_obsdata//k5ts4/T1730550??d.dat file size is correct (nominal:240MB, actual:240MB). 2006.173.05:51:45.02/k5log//k5ts1_log_newline 2006.173.05:51:45.73/k5log//k5ts2_log_newline 2006.173.05:51:46.43/k5log//k5ts3_log_newline 2006.173.05:51:47.14/k5log//k5ts4_log_newline 2006.173.05:51:47.16/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.05:51:47.16:setupk4=1 2006.173.05:51:47.16$setupk4/echo=on 2006.173.05:51:47.16$setupk4/pcalon 2006.173.05:51:47.16$pcalon/"no phase cal control is implemented here 2006.173.05:51:47.16$setupk4/"tpicd=stop 2006.173.05:51:47.16$setupk4/"rec=synch_on 2006.173.05:51:47.16$setupk4/"rec_mode=128 2006.173.05:51:47.16$setupk4/!* 2006.173.05:51:47.16$setupk4/recpk4 2006.173.05:51:47.16$recpk4/recpatch= 2006.173.05:51:47.17$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.05:51:47.17$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.05:51:47.17$setupk4/vck44 2006.173.05:51:47.17$vck44/valo=1,524.99 2006.173.05:51:47.17#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.05:51:47.17#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.05:51:47.17#ibcon#ireg 17 cls_cnt 0 2006.173.05:51:47.17#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.05:51:47.17#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.05:51:47.17#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.05:51:47.17#ibcon#enter wrdev, iclass 4, count 0 2006.173.05:51:47.17#ibcon#first serial, iclass 4, count 0 2006.173.05:51:47.17#ibcon#enter sib2, iclass 4, count 0 2006.173.05:51:47.17#ibcon#flushed, iclass 4, count 0 2006.173.05:51:47.17#ibcon#about to write, iclass 4, count 0 2006.173.05:51:47.17#ibcon#wrote, iclass 4, count 0 2006.173.05:51:47.17#ibcon#about to read 3, iclass 4, count 0 2006.173.05:51:47.19#ibcon#read 3, iclass 4, count 0 2006.173.05:51:47.19#ibcon#about to read 4, iclass 4, count 0 2006.173.05:51:47.19#ibcon#read 4, iclass 4, count 0 2006.173.05:51:47.19#ibcon#about to read 5, iclass 4, count 0 2006.173.05:51:47.19#ibcon#read 5, iclass 4, count 0 2006.173.05:51:47.19#ibcon#about to read 6, iclass 4, count 0 2006.173.05:51:47.19#ibcon#read 6, iclass 4, count 0 2006.173.05:51:47.19#ibcon#end of sib2, iclass 4, count 0 2006.173.05:51:47.19#ibcon#*mode == 0, iclass 4, count 0 2006.173.05:51:47.19#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.05:51:47.19#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.05:51:47.19#ibcon#*before write, iclass 4, count 0 2006.173.05:51:47.19#ibcon#enter sib2, iclass 4, count 0 2006.173.05:51:47.19#ibcon#flushed, iclass 4, count 0 2006.173.05:51:47.19#ibcon#about to write, iclass 4, count 0 2006.173.05:51:47.19#ibcon#wrote, iclass 4, count 0 2006.173.05:51:47.19#ibcon#about to read 3, iclass 4, count 0 2006.173.05:51:47.24#ibcon#read 3, iclass 4, count 0 2006.173.05:51:47.24#ibcon#about to read 4, iclass 4, count 0 2006.173.05:51:47.24#ibcon#read 4, iclass 4, count 0 2006.173.05:51:47.24#ibcon#about to read 5, iclass 4, count 0 2006.173.05:51:47.24#ibcon#read 5, iclass 4, count 0 2006.173.05:51:47.24#ibcon#about to read 6, iclass 4, count 0 2006.173.05:51:47.24#ibcon#read 6, iclass 4, count 0 2006.173.05:51:47.24#ibcon#end of sib2, iclass 4, count 0 2006.173.05:51:47.24#ibcon#*after write, iclass 4, count 0 2006.173.05:51:47.24#ibcon#*before return 0, iclass 4, count 0 2006.173.05:51:47.24#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.05:51:47.24#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.05:51:47.24#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.05:51:47.24#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.05:51:47.24$vck44/va=1,7 2006.173.05:51:47.24#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.05:51:47.24#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.05:51:47.24#ibcon#ireg 11 cls_cnt 2 2006.173.05:51:47.24#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.05:51:47.24#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.05:51:47.24#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.05:51:47.24#ibcon#enter wrdev, iclass 6, count 2 2006.173.05:51:47.24#ibcon#first serial, iclass 6, count 2 2006.173.05:51:47.24#ibcon#enter sib2, iclass 6, count 2 2006.173.05:51:47.24#ibcon#flushed, iclass 6, count 2 2006.173.05:51:47.24#ibcon#about to write, iclass 6, count 2 2006.173.05:51:47.24#ibcon#wrote, iclass 6, count 2 2006.173.05:51:47.24#ibcon#about to read 3, iclass 6, count 2 2006.173.05:51:47.26#ibcon#read 3, iclass 6, count 2 2006.173.05:51:47.26#ibcon#about to read 4, iclass 6, count 2 2006.173.05:51:47.26#ibcon#read 4, iclass 6, count 2 2006.173.05:51:47.26#ibcon#about to read 5, iclass 6, count 2 2006.173.05:51:47.26#ibcon#read 5, iclass 6, count 2 2006.173.05:51:47.26#ibcon#about to read 6, iclass 6, count 2 2006.173.05:51:47.26#ibcon#read 6, iclass 6, count 2 2006.173.05:51:47.26#ibcon#end of sib2, iclass 6, count 2 2006.173.05:51:47.26#ibcon#*mode == 0, iclass 6, count 2 2006.173.05:51:47.26#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.05:51:47.26#ibcon#[25=AT01-07\r\n] 2006.173.05:51:47.26#ibcon#*before write, iclass 6, count 2 2006.173.05:51:47.26#ibcon#enter sib2, iclass 6, count 2 2006.173.05:51:47.26#ibcon#flushed, iclass 6, count 2 2006.173.05:51:47.26#ibcon#about to write, iclass 6, count 2 2006.173.05:51:47.26#ibcon#wrote, iclass 6, count 2 2006.173.05:51:47.26#ibcon#about to read 3, iclass 6, count 2 2006.173.05:51:47.29#ibcon#read 3, iclass 6, count 2 2006.173.05:51:47.29#ibcon#about to read 4, iclass 6, count 2 2006.173.05:51:47.29#ibcon#read 4, iclass 6, count 2 2006.173.05:51:47.29#ibcon#about to read 5, iclass 6, count 2 2006.173.05:51:47.29#ibcon#read 5, iclass 6, count 2 2006.173.05:51:47.29#ibcon#about to read 6, iclass 6, count 2 2006.173.05:51:47.29#ibcon#read 6, iclass 6, count 2 2006.173.05:51:47.29#ibcon#end of sib2, iclass 6, count 2 2006.173.05:51:47.29#ibcon#*after write, iclass 6, count 2 2006.173.05:51:47.29#ibcon#*before return 0, iclass 6, count 2 2006.173.05:51:47.29#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.05:51:47.29#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.05:51:47.29#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.05:51:47.29#ibcon#ireg 7 cls_cnt 0 2006.173.05:51:47.29#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.05:51:47.41#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.05:51:47.41#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.05:51:47.41#ibcon#enter wrdev, iclass 6, count 0 2006.173.05:51:47.41#ibcon#first serial, iclass 6, count 0 2006.173.05:51:47.41#ibcon#enter sib2, iclass 6, count 0 2006.173.05:51:47.41#ibcon#flushed, iclass 6, count 0 2006.173.05:51:47.41#ibcon#about to write, iclass 6, count 0 2006.173.05:51:47.41#ibcon#wrote, iclass 6, count 0 2006.173.05:51:47.41#ibcon#about to read 3, iclass 6, count 0 2006.173.05:51:47.43#ibcon#read 3, iclass 6, count 0 2006.173.05:51:47.43#ibcon#about to read 4, iclass 6, count 0 2006.173.05:51:47.43#ibcon#read 4, iclass 6, count 0 2006.173.05:51:47.43#ibcon#about to read 5, iclass 6, count 0 2006.173.05:51:47.43#ibcon#read 5, iclass 6, count 0 2006.173.05:51:47.43#ibcon#about to read 6, iclass 6, count 0 2006.173.05:51:47.43#ibcon#read 6, iclass 6, count 0 2006.173.05:51:47.43#ibcon#end of sib2, iclass 6, count 0 2006.173.05:51:47.43#ibcon#*mode == 0, iclass 6, count 0 2006.173.05:51:47.43#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.05:51:47.43#ibcon#[25=USB\r\n] 2006.173.05:51:47.43#ibcon#*before write, iclass 6, count 0 2006.173.05:51:47.43#ibcon#enter sib2, iclass 6, count 0 2006.173.05:51:47.43#ibcon#flushed, iclass 6, count 0 2006.173.05:51:47.43#ibcon#about to write, iclass 6, count 0 2006.173.05:51:47.43#ibcon#wrote, iclass 6, count 0 2006.173.05:51:47.43#ibcon#about to read 3, iclass 6, count 0 2006.173.05:51:47.46#ibcon#read 3, iclass 6, count 0 2006.173.05:51:47.46#ibcon#about to read 4, iclass 6, count 0 2006.173.05:51:47.46#ibcon#read 4, iclass 6, count 0 2006.173.05:51:47.46#ibcon#about to read 5, iclass 6, count 0 2006.173.05:51:47.46#ibcon#read 5, iclass 6, count 0 2006.173.05:51:47.46#ibcon#about to read 6, iclass 6, count 0 2006.173.05:51:47.46#ibcon#read 6, iclass 6, count 0 2006.173.05:51:47.46#ibcon#end of sib2, iclass 6, count 0 2006.173.05:51:47.46#ibcon#*after write, iclass 6, count 0 2006.173.05:51:47.46#ibcon#*before return 0, iclass 6, count 0 2006.173.05:51:47.46#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.05:51:47.46#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.05:51:47.46#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.05:51:47.46#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.05:51:47.46$vck44/valo=2,534.99 2006.173.05:51:47.46#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.05:51:47.46#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.05:51:47.46#ibcon#ireg 17 cls_cnt 0 2006.173.05:51:47.46#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.05:51:47.46#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.05:51:47.46#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.05:51:47.46#ibcon#enter wrdev, iclass 10, count 0 2006.173.05:51:47.46#ibcon#first serial, iclass 10, count 0 2006.173.05:51:47.46#ibcon#enter sib2, iclass 10, count 0 2006.173.05:51:47.46#ibcon#flushed, iclass 10, count 0 2006.173.05:51:47.46#ibcon#about to write, iclass 10, count 0 2006.173.05:51:47.46#ibcon#wrote, iclass 10, count 0 2006.173.05:51:47.46#ibcon#about to read 3, iclass 10, count 0 2006.173.05:51:47.48#ibcon#read 3, iclass 10, count 0 2006.173.05:51:47.48#ibcon#about to read 4, iclass 10, count 0 2006.173.05:51:47.48#ibcon#read 4, iclass 10, count 0 2006.173.05:51:47.48#ibcon#about to read 5, iclass 10, count 0 2006.173.05:51:47.48#ibcon#read 5, iclass 10, count 0 2006.173.05:51:47.48#ibcon#about to read 6, iclass 10, count 0 2006.173.05:51:47.48#ibcon#read 6, iclass 10, count 0 2006.173.05:51:47.48#ibcon#end of sib2, iclass 10, count 0 2006.173.05:51:47.48#ibcon#*mode == 0, iclass 10, count 0 2006.173.05:51:47.48#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.05:51:47.48#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.05:51:47.48#ibcon#*before write, iclass 10, count 0 2006.173.05:51:47.48#ibcon#enter sib2, iclass 10, count 0 2006.173.05:51:47.48#ibcon#flushed, iclass 10, count 0 2006.173.05:51:47.48#ibcon#about to write, iclass 10, count 0 2006.173.05:51:47.48#ibcon#wrote, iclass 10, count 0 2006.173.05:51:47.48#ibcon#about to read 3, iclass 10, count 0 2006.173.05:51:47.52#ibcon#read 3, iclass 10, count 0 2006.173.05:51:47.52#ibcon#about to read 4, iclass 10, count 0 2006.173.05:51:47.52#ibcon#read 4, iclass 10, count 0 2006.173.05:51:47.52#ibcon#about to read 5, iclass 10, count 0 2006.173.05:51:47.52#ibcon#read 5, iclass 10, count 0 2006.173.05:51:47.52#ibcon#about to read 6, iclass 10, count 0 2006.173.05:51:47.52#ibcon#read 6, iclass 10, count 0 2006.173.05:51:47.52#ibcon#end of sib2, iclass 10, count 0 2006.173.05:51:47.52#ibcon#*after write, iclass 10, count 0 2006.173.05:51:47.52#ibcon#*before return 0, iclass 10, count 0 2006.173.05:51:47.52#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.05:51:47.52#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.05:51:47.52#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.05:51:47.52#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.05:51:47.52$vck44/va=2,6 2006.173.05:51:47.52#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.05:51:47.52#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.05:51:47.52#ibcon#ireg 11 cls_cnt 2 2006.173.05:51:47.52#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.05:51:47.58#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.05:51:47.58#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.05:51:47.58#ibcon#enter wrdev, iclass 12, count 2 2006.173.05:51:47.58#ibcon#first serial, iclass 12, count 2 2006.173.05:51:47.58#ibcon#enter sib2, iclass 12, count 2 2006.173.05:51:47.58#ibcon#flushed, iclass 12, count 2 2006.173.05:51:47.58#ibcon#about to write, iclass 12, count 2 2006.173.05:51:47.58#ibcon#wrote, iclass 12, count 2 2006.173.05:51:47.58#ibcon#about to read 3, iclass 12, count 2 2006.173.05:51:47.60#ibcon#read 3, iclass 12, count 2 2006.173.05:51:47.60#ibcon#about to read 4, iclass 12, count 2 2006.173.05:51:47.60#ibcon#read 4, iclass 12, count 2 2006.173.05:51:47.60#ibcon#about to read 5, iclass 12, count 2 2006.173.05:51:47.60#ibcon#read 5, iclass 12, count 2 2006.173.05:51:47.60#ibcon#about to read 6, iclass 12, count 2 2006.173.05:51:47.60#ibcon#read 6, iclass 12, count 2 2006.173.05:51:47.60#ibcon#end of sib2, iclass 12, count 2 2006.173.05:51:47.60#ibcon#*mode == 0, iclass 12, count 2 2006.173.05:51:47.60#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.05:51:47.60#ibcon#[25=AT02-06\r\n] 2006.173.05:51:47.60#ibcon#*before write, iclass 12, count 2 2006.173.05:51:47.60#ibcon#enter sib2, iclass 12, count 2 2006.173.05:51:47.60#ibcon#flushed, iclass 12, count 2 2006.173.05:51:47.60#ibcon#about to write, iclass 12, count 2 2006.173.05:51:47.60#ibcon#wrote, iclass 12, count 2 2006.173.05:51:47.60#ibcon#about to read 3, iclass 12, count 2 2006.173.05:51:47.63#ibcon#read 3, iclass 12, count 2 2006.173.05:51:47.63#ibcon#about to read 4, iclass 12, count 2 2006.173.05:51:47.63#ibcon#read 4, iclass 12, count 2 2006.173.05:51:47.63#ibcon#about to read 5, iclass 12, count 2 2006.173.05:51:47.63#ibcon#read 5, iclass 12, count 2 2006.173.05:51:47.63#ibcon#about to read 6, iclass 12, count 2 2006.173.05:51:47.63#ibcon#read 6, iclass 12, count 2 2006.173.05:51:47.63#ibcon#end of sib2, iclass 12, count 2 2006.173.05:51:47.63#ibcon#*after write, iclass 12, count 2 2006.173.05:51:47.63#ibcon#*before return 0, iclass 12, count 2 2006.173.05:51:47.63#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.05:51:47.63#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.05:51:47.63#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.05:51:47.63#ibcon#ireg 7 cls_cnt 0 2006.173.05:51:47.63#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.05:51:47.75#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.05:51:47.75#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.05:51:47.75#ibcon#enter wrdev, iclass 12, count 0 2006.173.05:51:47.75#ibcon#first serial, iclass 12, count 0 2006.173.05:51:47.75#ibcon#enter sib2, iclass 12, count 0 2006.173.05:51:47.75#ibcon#flushed, iclass 12, count 0 2006.173.05:51:47.75#ibcon#about to write, iclass 12, count 0 2006.173.05:51:47.75#ibcon#wrote, iclass 12, count 0 2006.173.05:51:47.75#ibcon#about to read 3, iclass 12, count 0 2006.173.05:51:47.77#ibcon#read 3, iclass 12, count 0 2006.173.05:51:47.77#ibcon#about to read 4, iclass 12, count 0 2006.173.05:51:47.77#ibcon#read 4, iclass 12, count 0 2006.173.05:51:47.77#ibcon#about to read 5, iclass 12, count 0 2006.173.05:51:47.77#ibcon#read 5, iclass 12, count 0 2006.173.05:51:47.77#ibcon#about to read 6, iclass 12, count 0 2006.173.05:51:47.77#ibcon#read 6, iclass 12, count 0 2006.173.05:51:47.77#ibcon#end of sib2, iclass 12, count 0 2006.173.05:51:47.77#ibcon#*mode == 0, iclass 12, count 0 2006.173.05:51:47.77#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.05:51:47.77#ibcon#[25=USB\r\n] 2006.173.05:51:47.77#ibcon#*before write, iclass 12, count 0 2006.173.05:51:47.77#ibcon#enter sib2, iclass 12, count 0 2006.173.05:51:47.77#ibcon#flushed, iclass 12, count 0 2006.173.05:51:47.77#ibcon#about to write, iclass 12, count 0 2006.173.05:51:47.77#ibcon#wrote, iclass 12, count 0 2006.173.05:51:47.77#ibcon#about to read 3, iclass 12, count 0 2006.173.05:51:47.80#ibcon#read 3, iclass 12, count 0 2006.173.05:51:47.80#ibcon#about to read 4, iclass 12, count 0 2006.173.05:51:47.80#ibcon#read 4, iclass 12, count 0 2006.173.05:51:47.80#ibcon#about to read 5, iclass 12, count 0 2006.173.05:51:47.80#ibcon#read 5, iclass 12, count 0 2006.173.05:51:47.80#ibcon#about to read 6, iclass 12, count 0 2006.173.05:51:47.80#ibcon#read 6, iclass 12, count 0 2006.173.05:51:47.80#ibcon#end of sib2, iclass 12, count 0 2006.173.05:51:47.80#ibcon#*after write, iclass 12, count 0 2006.173.05:51:47.80#ibcon#*before return 0, iclass 12, count 0 2006.173.05:51:47.80#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.05:51:47.80#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.05:51:47.80#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.05:51:47.80#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.05:51:47.80$vck44/valo=3,564.99 2006.173.05:51:47.80#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.05:51:47.80#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.05:51:47.80#ibcon#ireg 17 cls_cnt 0 2006.173.05:51:47.80#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.05:51:47.80#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.05:51:47.80#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.05:51:47.80#ibcon#enter wrdev, iclass 14, count 0 2006.173.05:51:47.80#ibcon#first serial, iclass 14, count 0 2006.173.05:51:47.80#ibcon#enter sib2, iclass 14, count 0 2006.173.05:51:47.80#ibcon#flushed, iclass 14, count 0 2006.173.05:51:47.80#ibcon#about to write, iclass 14, count 0 2006.173.05:51:47.80#ibcon#wrote, iclass 14, count 0 2006.173.05:51:47.80#ibcon#about to read 3, iclass 14, count 0 2006.173.05:51:47.82#ibcon#read 3, iclass 14, count 0 2006.173.05:51:47.82#ibcon#about to read 4, iclass 14, count 0 2006.173.05:51:47.82#ibcon#read 4, iclass 14, count 0 2006.173.05:51:47.82#ibcon#about to read 5, iclass 14, count 0 2006.173.05:51:47.82#ibcon#read 5, iclass 14, count 0 2006.173.05:51:47.82#ibcon#about to read 6, iclass 14, count 0 2006.173.05:51:47.82#ibcon#read 6, iclass 14, count 0 2006.173.05:51:47.82#ibcon#end of sib2, iclass 14, count 0 2006.173.05:51:47.82#ibcon#*mode == 0, iclass 14, count 0 2006.173.05:51:47.82#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.05:51:47.82#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.05:51:47.82#ibcon#*before write, iclass 14, count 0 2006.173.05:51:47.82#ibcon#enter sib2, iclass 14, count 0 2006.173.05:51:47.82#ibcon#flushed, iclass 14, count 0 2006.173.05:51:47.82#ibcon#about to write, iclass 14, count 0 2006.173.05:51:47.82#ibcon#wrote, iclass 14, count 0 2006.173.05:51:47.82#ibcon#about to read 3, iclass 14, count 0 2006.173.05:51:47.86#ibcon#read 3, iclass 14, count 0 2006.173.05:51:47.86#ibcon#about to read 4, iclass 14, count 0 2006.173.05:51:47.86#ibcon#read 4, iclass 14, count 0 2006.173.05:51:47.86#ibcon#about to read 5, iclass 14, count 0 2006.173.05:51:47.86#ibcon#read 5, iclass 14, count 0 2006.173.05:51:47.86#ibcon#about to read 6, iclass 14, count 0 2006.173.05:51:47.86#ibcon#read 6, iclass 14, count 0 2006.173.05:51:47.86#ibcon#end of sib2, iclass 14, count 0 2006.173.05:51:47.86#ibcon#*after write, iclass 14, count 0 2006.173.05:51:47.86#ibcon#*before return 0, iclass 14, count 0 2006.173.05:51:47.86#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.05:51:47.86#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.05:51:47.86#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.05:51:47.86#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.05:51:47.86$vck44/va=3,5 2006.173.05:51:47.86#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.05:51:47.86#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.05:51:47.86#ibcon#ireg 11 cls_cnt 2 2006.173.05:51:47.86#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.05:51:47.92#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.05:51:47.92#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.05:51:47.92#ibcon#enter wrdev, iclass 16, count 2 2006.173.05:51:47.92#ibcon#first serial, iclass 16, count 2 2006.173.05:51:47.92#ibcon#enter sib2, iclass 16, count 2 2006.173.05:51:47.92#ibcon#flushed, iclass 16, count 2 2006.173.05:51:47.92#ibcon#about to write, iclass 16, count 2 2006.173.05:51:47.92#ibcon#wrote, iclass 16, count 2 2006.173.05:51:47.92#ibcon#about to read 3, iclass 16, count 2 2006.173.05:51:47.94#ibcon#read 3, iclass 16, count 2 2006.173.05:51:47.94#ibcon#about to read 4, iclass 16, count 2 2006.173.05:51:47.94#ibcon#read 4, iclass 16, count 2 2006.173.05:51:47.94#ibcon#about to read 5, iclass 16, count 2 2006.173.05:51:47.94#ibcon#read 5, iclass 16, count 2 2006.173.05:51:47.94#ibcon#about to read 6, iclass 16, count 2 2006.173.05:51:47.94#ibcon#read 6, iclass 16, count 2 2006.173.05:51:47.94#ibcon#end of sib2, iclass 16, count 2 2006.173.05:51:47.94#ibcon#*mode == 0, iclass 16, count 2 2006.173.05:51:47.94#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.05:51:47.94#ibcon#[25=AT03-05\r\n] 2006.173.05:51:47.94#ibcon#*before write, iclass 16, count 2 2006.173.05:51:47.94#ibcon#enter sib2, iclass 16, count 2 2006.173.05:51:47.94#ibcon#flushed, iclass 16, count 2 2006.173.05:51:47.94#ibcon#about to write, iclass 16, count 2 2006.173.05:51:47.94#ibcon#wrote, iclass 16, count 2 2006.173.05:51:47.94#ibcon#about to read 3, iclass 16, count 2 2006.173.05:51:47.97#ibcon#read 3, iclass 16, count 2 2006.173.05:51:47.97#ibcon#about to read 4, iclass 16, count 2 2006.173.05:51:47.97#ibcon#read 4, iclass 16, count 2 2006.173.05:51:47.97#ibcon#about to read 5, iclass 16, count 2 2006.173.05:51:47.97#ibcon#read 5, iclass 16, count 2 2006.173.05:51:47.97#ibcon#about to read 6, iclass 16, count 2 2006.173.05:51:47.97#ibcon#read 6, iclass 16, count 2 2006.173.05:51:47.97#ibcon#end of sib2, iclass 16, count 2 2006.173.05:51:47.97#ibcon#*after write, iclass 16, count 2 2006.173.05:51:47.97#ibcon#*before return 0, iclass 16, count 2 2006.173.05:51:47.97#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.05:51:47.97#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.05:51:47.97#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.05:51:47.97#ibcon#ireg 7 cls_cnt 0 2006.173.05:51:47.97#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.05:51:48.09#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.05:51:48.09#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.05:51:48.09#ibcon#enter wrdev, iclass 16, count 0 2006.173.05:51:48.09#ibcon#first serial, iclass 16, count 0 2006.173.05:51:48.09#ibcon#enter sib2, iclass 16, count 0 2006.173.05:51:48.09#ibcon#flushed, iclass 16, count 0 2006.173.05:51:48.09#ibcon#about to write, iclass 16, count 0 2006.173.05:51:48.09#ibcon#wrote, iclass 16, count 0 2006.173.05:51:48.09#ibcon#about to read 3, iclass 16, count 0 2006.173.05:51:48.11#ibcon#read 3, iclass 16, count 0 2006.173.05:51:48.11#ibcon#about to read 4, iclass 16, count 0 2006.173.05:51:48.11#ibcon#read 4, iclass 16, count 0 2006.173.05:51:48.11#ibcon#about to read 5, iclass 16, count 0 2006.173.05:51:48.11#ibcon#read 5, iclass 16, count 0 2006.173.05:51:48.11#ibcon#about to read 6, iclass 16, count 0 2006.173.05:51:48.11#ibcon#read 6, iclass 16, count 0 2006.173.05:51:48.11#ibcon#end of sib2, iclass 16, count 0 2006.173.05:51:48.11#ibcon#*mode == 0, iclass 16, count 0 2006.173.05:51:48.11#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.05:51:48.11#ibcon#[25=USB\r\n] 2006.173.05:51:48.11#ibcon#*before write, iclass 16, count 0 2006.173.05:51:48.11#ibcon#enter sib2, iclass 16, count 0 2006.173.05:51:48.11#ibcon#flushed, iclass 16, count 0 2006.173.05:51:48.11#ibcon#about to write, iclass 16, count 0 2006.173.05:51:48.11#ibcon#wrote, iclass 16, count 0 2006.173.05:51:48.11#ibcon#about to read 3, iclass 16, count 0 2006.173.05:51:48.14#ibcon#read 3, iclass 16, count 0 2006.173.05:51:48.14#ibcon#about to read 4, iclass 16, count 0 2006.173.05:51:48.14#ibcon#read 4, iclass 16, count 0 2006.173.05:51:48.14#ibcon#about to read 5, iclass 16, count 0 2006.173.05:51:48.14#ibcon#read 5, iclass 16, count 0 2006.173.05:51:48.14#ibcon#about to read 6, iclass 16, count 0 2006.173.05:51:48.14#ibcon#read 6, iclass 16, count 0 2006.173.05:51:48.14#ibcon#end of sib2, iclass 16, count 0 2006.173.05:51:48.14#ibcon#*after write, iclass 16, count 0 2006.173.05:51:48.14#ibcon#*before return 0, iclass 16, count 0 2006.173.05:51:48.14#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.05:51:48.14#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.05:51:48.14#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.05:51:48.14#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.05:51:48.14$vck44/valo=4,624.99 2006.173.05:51:48.14#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.05:51:48.14#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.05:51:48.14#ibcon#ireg 17 cls_cnt 0 2006.173.05:51:48.14#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.05:51:48.14#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.05:51:48.14#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.05:51:48.14#ibcon#enter wrdev, iclass 18, count 0 2006.173.05:51:48.14#ibcon#first serial, iclass 18, count 0 2006.173.05:51:48.14#ibcon#enter sib2, iclass 18, count 0 2006.173.05:51:48.14#ibcon#flushed, iclass 18, count 0 2006.173.05:51:48.14#ibcon#about to write, iclass 18, count 0 2006.173.05:51:48.14#ibcon#wrote, iclass 18, count 0 2006.173.05:51:48.14#ibcon#about to read 3, iclass 18, count 0 2006.173.05:51:48.16#ibcon#read 3, iclass 18, count 0 2006.173.05:51:48.16#ibcon#about to read 4, iclass 18, count 0 2006.173.05:51:48.16#ibcon#read 4, iclass 18, count 0 2006.173.05:51:48.16#ibcon#about to read 5, iclass 18, count 0 2006.173.05:51:48.16#ibcon#read 5, iclass 18, count 0 2006.173.05:51:48.16#ibcon#about to read 6, iclass 18, count 0 2006.173.05:51:48.16#ibcon#read 6, iclass 18, count 0 2006.173.05:51:48.16#ibcon#end of sib2, iclass 18, count 0 2006.173.05:51:48.16#ibcon#*mode == 0, iclass 18, count 0 2006.173.05:51:48.16#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.05:51:48.16#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.05:51:48.16#ibcon#*before write, iclass 18, count 0 2006.173.05:51:48.16#ibcon#enter sib2, iclass 18, count 0 2006.173.05:51:48.16#ibcon#flushed, iclass 18, count 0 2006.173.05:51:48.16#ibcon#about to write, iclass 18, count 0 2006.173.05:51:48.16#ibcon#wrote, iclass 18, count 0 2006.173.05:51:48.16#ibcon#about to read 3, iclass 18, count 0 2006.173.05:51:48.20#ibcon#read 3, iclass 18, count 0 2006.173.05:51:48.20#ibcon#about to read 4, iclass 18, count 0 2006.173.05:51:48.20#ibcon#read 4, iclass 18, count 0 2006.173.05:51:48.20#ibcon#about to read 5, iclass 18, count 0 2006.173.05:51:48.20#ibcon#read 5, iclass 18, count 0 2006.173.05:51:48.20#ibcon#about to read 6, iclass 18, count 0 2006.173.05:51:48.20#ibcon#read 6, iclass 18, count 0 2006.173.05:51:48.20#ibcon#end of sib2, iclass 18, count 0 2006.173.05:51:48.20#ibcon#*after write, iclass 18, count 0 2006.173.05:51:48.20#ibcon#*before return 0, iclass 18, count 0 2006.173.05:51:48.20#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.05:51:48.20#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.05:51:48.20#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.05:51:48.20#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.05:51:48.20$vck44/va=4,6 2006.173.05:51:48.20#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.05:51:48.20#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.05:51:48.20#ibcon#ireg 11 cls_cnt 2 2006.173.05:51:48.20#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.05:51:48.26#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.05:51:48.26#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.05:51:48.26#ibcon#enter wrdev, iclass 20, count 2 2006.173.05:51:48.26#ibcon#first serial, iclass 20, count 2 2006.173.05:51:48.26#ibcon#enter sib2, iclass 20, count 2 2006.173.05:51:48.26#ibcon#flushed, iclass 20, count 2 2006.173.05:51:48.26#ibcon#about to write, iclass 20, count 2 2006.173.05:51:48.26#ibcon#wrote, iclass 20, count 2 2006.173.05:51:48.26#ibcon#about to read 3, iclass 20, count 2 2006.173.05:51:48.28#ibcon#read 3, iclass 20, count 2 2006.173.05:51:48.28#ibcon#about to read 4, iclass 20, count 2 2006.173.05:51:48.28#ibcon#read 4, iclass 20, count 2 2006.173.05:51:48.28#ibcon#about to read 5, iclass 20, count 2 2006.173.05:51:48.28#ibcon#read 5, iclass 20, count 2 2006.173.05:51:48.28#ibcon#about to read 6, iclass 20, count 2 2006.173.05:51:48.28#ibcon#read 6, iclass 20, count 2 2006.173.05:51:48.28#ibcon#end of sib2, iclass 20, count 2 2006.173.05:51:48.28#ibcon#*mode == 0, iclass 20, count 2 2006.173.05:51:48.28#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.05:51:48.28#ibcon#[25=AT04-06\r\n] 2006.173.05:51:48.28#ibcon#*before write, iclass 20, count 2 2006.173.05:51:48.28#ibcon#enter sib2, iclass 20, count 2 2006.173.05:51:48.28#ibcon#flushed, iclass 20, count 2 2006.173.05:51:48.28#ibcon#about to write, iclass 20, count 2 2006.173.05:51:48.28#ibcon#wrote, iclass 20, count 2 2006.173.05:51:48.28#ibcon#about to read 3, iclass 20, count 2 2006.173.05:51:48.31#ibcon#read 3, iclass 20, count 2 2006.173.05:51:48.31#ibcon#about to read 4, iclass 20, count 2 2006.173.05:51:48.31#ibcon#read 4, iclass 20, count 2 2006.173.05:51:48.31#ibcon#about to read 5, iclass 20, count 2 2006.173.05:51:48.31#ibcon#read 5, iclass 20, count 2 2006.173.05:51:48.31#ibcon#about to read 6, iclass 20, count 2 2006.173.05:51:48.31#ibcon#read 6, iclass 20, count 2 2006.173.05:51:48.31#ibcon#end of sib2, iclass 20, count 2 2006.173.05:51:48.31#ibcon#*after write, iclass 20, count 2 2006.173.05:51:48.31#ibcon#*before return 0, iclass 20, count 2 2006.173.05:51:48.31#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.05:51:48.31#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.05:51:48.31#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.05:51:48.31#ibcon#ireg 7 cls_cnt 0 2006.173.05:51:48.31#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.05:51:48.43#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.05:51:48.43#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.05:51:48.43#ibcon#enter wrdev, iclass 20, count 0 2006.173.05:51:48.43#ibcon#first serial, iclass 20, count 0 2006.173.05:51:48.43#ibcon#enter sib2, iclass 20, count 0 2006.173.05:51:48.43#ibcon#flushed, iclass 20, count 0 2006.173.05:51:48.43#ibcon#about to write, iclass 20, count 0 2006.173.05:51:48.43#ibcon#wrote, iclass 20, count 0 2006.173.05:51:48.43#ibcon#about to read 3, iclass 20, count 0 2006.173.05:51:48.45#ibcon#read 3, iclass 20, count 0 2006.173.05:51:48.45#ibcon#about to read 4, iclass 20, count 0 2006.173.05:51:48.45#ibcon#read 4, iclass 20, count 0 2006.173.05:51:48.45#ibcon#about to read 5, iclass 20, count 0 2006.173.05:51:48.45#ibcon#read 5, iclass 20, count 0 2006.173.05:51:48.45#ibcon#about to read 6, iclass 20, count 0 2006.173.05:51:48.45#ibcon#read 6, iclass 20, count 0 2006.173.05:51:48.45#ibcon#end of sib2, iclass 20, count 0 2006.173.05:51:48.45#ibcon#*mode == 0, iclass 20, count 0 2006.173.05:51:48.45#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.05:51:48.45#ibcon#[25=USB\r\n] 2006.173.05:51:48.45#ibcon#*before write, iclass 20, count 0 2006.173.05:51:48.45#ibcon#enter sib2, iclass 20, count 0 2006.173.05:51:48.45#ibcon#flushed, iclass 20, count 0 2006.173.05:51:48.45#ibcon#about to write, iclass 20, count 0 2006.173.05:51:48.45#ibcon#wrote, iclass 20, count 0 2006.173.05:51:48.45#ibcon#about to read 3, iclass 20, count 0 2006.173.05:51:48.48#ibcon#read 3, iclass 20, count 0 2006.173.05:51:48.48#ibcon#about to read 4, iclass 20, count 0 2006.173.05:51:48.48#ibcon#read 4, iclass 20, count 0 2006.173.05:51:48.48#ibcon#about to read 5, iclass 20, count 0 2006.173.05:51:48.48#ibcon#read 5, iclass 20, count 0 2006.173.05:51:48.48#ibcon#about to read 6, iclass 20, count 0 2006.173.05:51:48.48#ibcon#read 6, iclass 20, count 0 2006.173.05:51:48.48#ibcon#end of sib2, iclass 20, count 0 2006.173.05:51:48.48#ibcon#*after write, iclass 20, count 0 2006.173.05:51:48.48#ibcon#*before return 0, iclass 20, count 0 2006.173.05:51:48.48#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.05:51:48.48#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.05:51:48.48#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.05:51:48.48#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.05:51:48.48$vck44/valo=5,734.99 2006.173.05:51:48.48#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.05:51:48.48#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.05:51:48.48#ibcon#ireg 17 cls_cnt 0 2006.173.05:51:48.48#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.05:51:48.48#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.05:51:48.48#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.05:51:48.48#ibcon#enter wrdev, iclass 22, count 0 2006.173.05:51:48.48#ibcon#first serial, iclass 22, count 0 2006.173.05:51:48.48#ibcon#enter sib2, iclass 22, count 0 2006.173.05:51:48.48#ibcon#flushed, iclass 22, count 0 2006.173.05:51:48.48#ibcon#about to write, iclass 22, count 0 2006.173.05:51:48.48#ibcon#wrote, iclass 22, count 0 2006.173.05:51:48.48#ibcon#about to read 3, iclass 22, count 0 2006.173.05:51:48.50#ibcon#read 3, iclass 22, count 0 2006.173.05:51:48.50#ibcon#about to read 4, iclass 22, count 0 2006.173.05:51:48.50#ibcon#read 4, iclass 22, count 0 2006.173.05:51:48.50#ibcon#about to read 5, iclass 22, count 0 2006.173.05:51:48.50#ibcon#read 5, iclass 22, count 0 2006.173.05:51:48.50#ibcon#about to read 6, iclass 22, count 0 2006.173.05:51:48.50#ibcon#read 6, iclass 22, count 0 2006.173.05:51:48.50#ibcon#end of sib2, iclass 22, count 0 2006.173.05:51:48.50#ibcon#*mode == 0, iclass 22, count 0 2006.173.05:51:48.50#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.05:51:48.50#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.05:51:48.50#ibcon#*before write, iclass 22, count 0 2006.173.05:51:48.50#ibcon#enter sib2, iclass 22, count 0 2006.173.05:51:48.50#ibcon#flushed, iclass 22, count 0 2006.173.05:51:48.50#ibcon#about to write, iclass 22, count 0 2006.173.05:51:48.50#ibcon#wrote, iclass 22, count 0 2006.173.05:51:48.50#ibcon#about to read 3, iclass 22, count 0 2006.173.05:51:48.54#ibcon#read 3, iclass 22, count 0 2006.173.05:51:48.54#ibcon#about to read 4, iclass 22, count 0 2006.173.05:51:48.54#ibcon#read 4, iclass 22, count 0 2006.173.05:51:48.54#ibcon#about to read 5, iclass 22, count 0 2006.173.05:51:48.54#ibcon#read 5, iclass 22, count 0 2006.173.05:51:48.54#ibcon#about to read 6, iclass 22, count 0 2006.173.05:51:48.54#ibcon#read 6, iclass 22, count 0 2006.173.05:51:48.54#ibcon#end of sib2, iclass 22, count 0 2006.173.05:51:48.54#ibcon#*after write, iclass 22, count 0 2006.173.05:51:48.54#ibcon#*before return 0, iclass 22, count 0 2006.173.05:51:48.54#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.05:51:48.54#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.05:51:48.54#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.05:51:48.54#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.05:51:48.54$vck44/va=5,4 2006.173.05:51:48.54#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.05:51:48.54#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.05:51:48.54#ibcon#ireg 11 cls_cnt 2 2006.173.05:51:48.54#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.05:51:48.60#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.05:51:48.60#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.05:51:48.60#ibcon#enter wrdev, iclass 24, count 2 2006.173.05:51:48.60#ibcon#first serial, iclass 24, count 2 2006.173.05:51:48.60#ibcon#enter sib2, iclass 24, count 2 2006.173.05:51:48.60#ibcon#flushed, iclass 24, count 2 2006.173.05:51:48.60#ibcon#about to write, iclass 24, count 2 2006.173.05:51:48.60#ibcon#wrote, iclass 24, count 2 2006.173.05:51:48.60#ibcon#about to read 3, iclass 24, count 2 2006.173.05:51:48.62#ibcon#read 3, iclass 24, count 2 2006.173.05:51:48.62#ibcon#about to read 4, iclass 24, count 2 2006.173.05:51:48.62#ibcon#read 4, iclass 24, count 2 2006.173.05:51:48.62#ibcon#about to read 5, iclass 24, count 2 2006.173.05:51:48.62#ibcon#read 5, iclass 24, count 2 2006.173.05:51:48.62#ibcon#about to read 6, iclass 24, count 2 2006.173.05:51:48.62#ibcon#read 6, iclass 24, count 2 2006.173.05:51:48.62#ibcon#end of sib2, iclass 24, count 2 2006.173.05:51:48.62#ibcon#*mode == 0, iclass 24, count 2 2006.173.05:51:48.62#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.05:51:48.62#ibcon#[25=AT05-04\r\n] 2006.173.05:51:48.62#ibcon#*before write, iclass 24, count 2 2006.173.05:51:48.62#ibcon#enter sib2, iclass 24, count 2 2006.173.05:51:48.62#ibcon#flushed, iclass 24, count 2 2006.173.05:51:48.62#ibcon#about to write, iclass 24, count 2 2006.173.05:51:48.62#ibcon#wrote, iclass 24, count 2 2006.173.05:51:48.62#ibcon#about to read 3, iclass 24, count 2 2006.173.05:51:48.65#ibcon#read 3, iclass 24, count 2 2006.173.05:51:48.65#ibcon#about to read 4, iclass 24, count 2 2006.173.05:51:48.65#ibcon#read 4, iclass 24, count 2 2006.173.05:51:48.65#ibcon#about to read 5, iclass 24, count 2 2006.173.05:51:48.65#ibcon#read 5, iclass 24, count 2 2006.173.05:51:48.65#ibcon#about to read 6, iclass 24, count 2 2006.173.05:51:48.65#ibcon#read 6, iclass 24, count 2 2006.173.05:51:48.65#ibcon#end of sib2, iclass 24, count 2 2006.173.05:51:48.65#ibcon#*after write, iclass 24, count 2 2006.173.05:51:48.65#ibcon#*before return 0, iclass 24, count 2 2006.173.05:51:48.65#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.05:51:48.65#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.05:51:48.65#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.05:51:48.65#ibcon#ireg 7 cls_cnt 0 2006.173.05:51:48.65#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.05:51:48.77#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.05:51:48.77#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.05:51:48.77#ibcon#enter wrdev, iclass 24, count 0 2006.173.05:51:48.77#ibcon#first serial, iclass 24, count 0 2006.173.05:51:48.77#ibcon#enter sib2, iclass 24, count 0 2006.173.05:51:48.77#ibcon#flushed, iclass 24, count 0 2006.173.05:51:48.77#ibcon#about to write, iclass 24, count 0 2006.173.05:51:48.77#ibcon#wrote, iclass 24, count 0 2006.173.05:51:48.77#ibcon#about to read 3, iclass 24, count 0 2006.173.05:51:48.79#ibcon#read 3, iclass 24, count 0 2006.173.05:51:48.79#ibcon#about to read 4, iclass 24, count 0 2006.173.05:51:48.79#ibcon#read 4, iclass 24, count 0 2006.173.05:51:48.79#ibcon#about to read 5, iclass 24, count 0 2006.173.05:51:48.79#ibcon#read 5, iclass 24, count 0 2006.173.05:51:48.79#ibcon#about to read 6, iclass 24, count 0 2006.173.05:51:48.79#ibcon#read 6, iclass 24, count 0 2006.173.05:51:48.79#ibcon#end of sib2, iclass 24, count 0 2006.173.05:51:48.79#ibcon#*mode == 0, iclass 24, count 0 2006.173.05:51:48.79#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.05:51:48.79#ibcon#[25=USB\r\n] 2006.173.05:51:48.79#ibcon#*before write, iclass 24, count 0 2006.173.05:51:48.79#ibcon#enter sib2, iclass 24, count 0 2006.173.05:51:48.79#ibcon#flushed, iclass 24, count 0 2006.173.05:51:48.79#ibcon#about to write, iclass 24, count 0 2006.173.05:51:48.79#ibcon#wrote, iclass 24, count 0 2006.173.05:51:48.79#ibcon#about to read 3, iclass 24, count 0 2006.173.05:51:48.82#ibcon#read 3, iclass 24, count 0 2006.173.05:51:48.82#ibcon#about to read 4, iclass 24, count 0 2006.173.05:51:48.82#ibcon#read 4, iclass 24, count 0 2006.173.05:51:48.82#ibcon#about to read 5, iclass 24, count 0 2006.173.05:51:48.82#ibcon#read 5, iclass 24, count 0 2006.173.05:51:48.82#ibcon#about to read 6, iclass 24, count 0 2006.173.05:51:48.82#ibcon#read 6, iclass 24, count 0 2006.173.05:51:48.82#ibcon#end of sib2, iclass 24, count 0 2006.173.05:51:48.82#ibcon#*after write, iclass 24, count 0 2006.173.05:51:48.82#ibcon#*before return 0, iclass 24, count 0 2006.173.05:51:48.82#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.05:51:48.82#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.05:51:48.82#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.05:51:48.82#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.05:51:48.82$vck44/valo=6,814.99 2006.173.05:51:48.82#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.05:51:48.82#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.05:51:48.82#ibcon#ireg 17 cls_cnt 0 2006.173.05:51:48.82#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.05:51:48.82#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.05:51:48.82#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.05:51:48.82#ibcon#enter wrdev, iclass 26, count 0 2006.173.05:51:48.82#ibcon#first serial, iclass 26, count 0 2006.173.05:51:48.82#ibcon#enter sib2, iclass 26, count 0 2006.173.05:51:48.82#ibcon#flushed, iclass 26, count 0 2006.173.05:51:48.82#ibcon#about to write, iclass 26, count 0 2006.173.05:51:48.82#ibcon#wrote, iclass 26, count 0 2006.173.05:51:48.82#ibcon#about to read 3, iclass 26, count 0 2006.173.05:51:48.84#ibcon#read 3, iclass 26, count 0 2006.173.05:51:48.84#ibcon#about to read 4, iclass 26, count 0 2006.173.05:51:48.84#ibcon#read 4, iclass 26, count 0 2006.173.05:51:48.84#ibcon#about to read 5, iclass 26, count 0 2006.173.05:51:48.84#ibcon#read 5, iclass 26, count 0 2006.173.05:51:48.84#ibcon#about to read 6, iclass 26, count 0 2006.173.05:51:48.84#ibcon#read 6, iclass 26, count 0 2006.173.05:51:48.84#ibcon#end of sib2, iclass 26, count 0 2006.173.05:51:48.84#ibcon#*mode == 0, iclass 26, count 0 2006.173.05:51:48.84#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.05:51:48.84#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.05:51:48.84#ibcon#*before write, iclass 26, count 0 2006.173.05:51:48.84#ibcon#enter sib2, iclass 26, count 0 2006.173.05:51:48.84#ibcon#flushed, iclass 26, count 0 2006.173.05:51:48.84#ibcon#about to write, iclass 26, count 0 2006.173.05:51:48.84#ibcon#wrote, iclass 26, count 0 2006.173.05:51:48.84#ibcon#about to read 3, iclass 26, count 0 2006.173.05:51:48.88#ibcon#read 3, iclass 26, count 0 2006.173.05:51:48.88#ibcon#about to read 4, iclass 26, count 0 2006.173.05:51:48.88#ibcon#read 4, iclass 26, count 0 2006.173.05:51:48.88#ibcon#about to read 5, iclass 26, count 0 2006.173.05:51:48.88#ibcon#read 5, iclass 26, count 0 2006.173.05:51:48.88#ibcon#about to read 6, iclass 26, count 0 2006.173.05:51:48.88#ibcon#read 6, iclass 26, count 0 2006.173.05:51:48.88#ibcon#end of sib2, iclass 26, count 0 2006.173.05:51:48.88#ibcon#*after write, iclass 26, count 0 2006.173.05:51:48.88#ibcon#*before return 0, iclass 26, count 0 2006.173.05:51:48.88#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.05:51:48.88#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.05:51:48.88#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.05:51:48.88#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.05:51:48.88$vck44/va=6,3 2006.173.05:51:48.88#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.05:51:48.88#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.05:51:48.88#ibcon#ireg 11 cls_cnt 2 2006.173.05:51:48.88#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.05:51:48.94#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.05:51:48.94#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.05:51:48.94#ibcon#enter wrdev, iclass 28, count 2 2006.173.05:51:48.94#ibcon#first serial, iclass 28, count 2 2006.173.05:51:48.94#ibcon#enter sib2, iclass 28, count 2 2006.173.05:51:48.94#ibcon#flushed, iclass 28, count 2 2006.173.05:51:48.94#ibcon#about to write, iclass 28, count 2 2006.173.05:51:48.94#ibcon#wrote, iclass 28, count 2 2006.173.05:51:48.94#ibcon#about to read 3, iclass 28, count 2 2006.173.05:51:48.96#ibcon#read 3, iclass 28, count 2 2006.173.05:51:48.96#ibcon#about to read 4, iclass 28, count 2 2006.173.05:51:48.96#ibcon#read 4, iclass 28, count 2 2006.173.05:51:48.96#ibcon#about to read 5, iclass 28, count 2 2006.173.05:51:48.96#ibcon#read 5, iclass 28, count 2 2006.173.05:51:48.96#ibcon#about to read 6, iclass 28, count 2 2006.173.05:51:48.96#ibcon#read 6, iclass 28, count 2 2006.173.05:51:48.96#ibcon#end of sib2, iclass 28, count 2 2006.173.05:51:48.96#ibcon#*mode == 0, iclass 28, count 2 2006.173.05:51:48.96#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.05:51:48.96#ibcon#[25=AT06-03\r\n] 2006.173.05:51:48.96#ibcon#*before write, iclass 28, count 2 2006.173.05:51:48.96#ibcon#enter sib2, iclass 28, count 2 2006.173.05:51:48.96#ibcon#flushed, iclass 28, count 2 2006.173.05:51:48.96#ibcon#about to write, iclass 28, count 2 2006.173.05:51:48.96#ibcon#wrote, iclass 28, count 2 2006.173.05:51:48.96#ibcon#about to read 3, iclass 28, count 2 2006.173.05:51:48.99#ibcon#read 3, iclass 28, count 2 2006.173.05:51:48.99#ibcon#about to read 4, iclass 28, count 2 2006.173.05:51:48.99#ibcon#read 4, iclass 28, count 2 2006.173.05:51:48.99#ibcon#about to read 5, iclass 28, count 2 2006.173.05:51:48.99#ibcon#read 5, iclass 28, count 2 2006.173.05:51:48.99#ibcon#about to read 6, iclass 28, count 2 2006.173.05:51:48.99#ibcon#read 6, iclass 28, count 2 2006.173.05:51:48.99#ibcon#end of sib2, iclass 28, count 2 2006.173.05:51:48.99#ibcon#*after write, iclass 28, count 2 2006.173.05:51:48.99#ibcon#*before return 0, iclass 28, count 2 2006.173.05:51:48.99#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.05:51:48.99#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.05:51:48.99#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.05:51:48.99#ibcon#ireg 7 cls_cnt 0 2006.173.05:51:48.99#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.05:51:49.02#abcon#<5=/15 0.5 1.3 23.64 771005.3\r\n> 2006.173.05:51:49.04#abcon#{5=INTERFACE CLEAR} 2006.173.05:51:49.10#abcon#[5=S1D000X0/0*\r\n] 2006.173.05:51:49.11#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.05:51:49.11#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.05:51:49.11#ibcon#enter wrdev, iclass 28, count 0 2006.173.05:51:49.11#ibcon#first serial, iclass 28, count 0 2006.173.05:51:49.11#ibcon#enter sib2, iclass 28, count 0 2006.173.05:51:49.11#ibcon#flushed, iclass 28, count 0 2006.173.05:51:49.11#ibcon#about to write, iclass 28, count 0 2006.173.05:51:49.11#ibcon#wrote, iclass 28, count 0 2006.173.05:51:49.11#ibcon#about to read 3, iclass 28, count 0 2006.173.05:51:49.13#ibcon#read 3, iclass 28, count 0 2006.173.05:51:49.13#ibcon#about to read 4, iclass 28, count 0 2006.173.05:51:49.13#ibcon#read 4, iclass 28, count 0 2006.173.05:51:49.13#ibcon#about to read 5, iclass 28, count 0 2006.173.05:51:49.13#ibcon#read 5, iclass 28, count 0 2006.173.05:51:49.13#ibcon#about to read 6, iclass 28, count 0 2006.173.05:51:49.13#ibcon#read 6, iclass 28, count 0 2006.173.05:51:49.13#ibcon#end of sib2, iclass 28, count 0 2006.173.05:51:49.13#ibcon#*mode == 0, iclass 28, count 0 2006.173.05:51:49.13#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.05:51:49.13#ibcon#[25=USB\r\n] 2006.173.05:51:49.13#ibcon#*before write, iclass 28, count 0 2006.173.05:51:49.13#ibcon#enter sib2, iclass 28, count 0 2006.173.05:51:49.13#ibcon#flushed, iclass 28, count 0 2006.173.05:51:49.13#ibcon#about to write, iclass 28, count 0 2006.173.05:51:49.13#ibcon#wrote, iclass 28, count 0 2006.173.05:51:49.13#ibcon#about to read 3, iclass 28, count 0 2006.173.05:51:49.16#ibcon#read 3, iclass 28, count 0 2006.173.05:51:49.16#ibcon#about to read 4, iclass 28, count 0 2006.173.05:51:49.16#ibcon#read 4, iclass 28, count 0 2006.173.05:51:49.16#ibcon#about to read 5, iclass 28, count 0 2006.173.05:51:49.16#ibcon#read 5, iclass 28, count 0 2006.173.05:51:49.16#ibcon#about to read 6, iclass 28, count 0 2006.173.05:51:49.16#ibcon#read 6, iclass 28, count 0 2006.173.05:51:49.16#ibcon#end of sib2, iclass 28, count 0 2006.173.05:51:49.16#ibcon#*after write, iclass 28, count 0 2006.173.05:51:49.16#ibcon#*before return 0, iclass 28, count 0 2006.173.05:51:49.16#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.05:51:49.16#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.05:51:49.16#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.05:51:49.16#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.05:51:49.16$vck44/valo=7,864.99 2006.173.05:51:49.16#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.05:51:49.16#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.05:51:49.16#ibcon#ireg 17 cls_cnt 0 2006.173.05:51:49.16#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.05:51:49.16#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.05:51:49.16#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.05:51:49.16#ibcon#enter wrdev, iclass 34, count 0 2006.173.05:51:49.16#ibcon#first serial, iclass 34, count 0 2006.173.05:51:49.16#ibcon#enter sib2, iclass 34, count 0 2006.173.05:51:49.16#ibcon#flushed, iclass 34, count 0 2006.173.05:51:49.16#ibcon#about to write, iclass 34, count 0 2006.173.05:51:49.16#ibcon#wrote, iclass 34, count 0 2006.173.05:51:49.16#ibcon#about to read 3, iclass 34, count 0 2006.173.05:51:49.18#ibcon#read 3, iclass 34, count 0 2006.173.05:51:49.18#ibcon#about to read 4, iclass 34, count 0 2006.173.05:51:49.18#ibcon#read 4, iclass 34, count 0 2006.173.05:51:49.18#ibcon#about to read 5, iclass 34, count 0 2006.173.05:51:49.18#ibcon#read 5, iclass 34, count 0 2006.173.05:51:49.18#ibcon#about to read 6, iclass 34, count 0 2006.173.05:51:49.18#ibcon#read 6, iclass 34, count 0 2006.173.05:51:49.18#ibcon#end of sib2, iclass 34, count 0 2006.173.05:51:49.18#ibcon#*mode == 0, iclass 34, count 0 2006.173.05:51:49.18#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.05:51:49.18#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.05:51:49.18#ibcon#*before write, iclass 34, count 0 2006.173.05:51:49.18#ibcon#enter sib2, iclass 34, count 0 2006.173.05:51:49.18#ibcon#flushed, iclass 34, count 0 2006.173.05:51:49.18#ibcon#about to write, iclass 34, count 0 2006.173.05:51:49.18#ibcon#wrote, iclass 34, count 0 2006.173.05:51:49.18#ibcon#about to read 3, iclass 34, count 0 2006.173.05:51:49.22#ibcon#read 3, iclass 34, count 0 2006.173.05:51:49.22#ibcon#about to read 4, iclass 34, count 0 2006.173.05:51:49.22#ibcon#read 4, iclass 34, count 0 2006.173.05:51:49.22#ibcon#about to read 5, iclass 34, count 0 2006.173.05:51:49.22#ibcon#read 5, iclass 34, count 0 2006.173.05:51:49.22#ibcon#about to read 6, iclass 34, count 0 2006.173.05:51:49.22#ibcon#read 6, iclass 34, count 0 2006.173.05:51:49.22#ibcon#end of sib2, iclass 34, count 0 2006.173.05:51:49.22#ibcon#*after write, iclass 34, count 0 2006.173.05:51:49.22#ibcon#*before return 0, iclass 34, count 0 2006.173.05:51:49.22#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.05:51:49.22#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.05:51:49.22#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.05:51:49.22#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.05:51:49.22$vck44/va=7,4 2006.173.05:51:49.22#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.05:51:49.22#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.05:51:49.22#ibcon#ireg 11 cls_cnt 2 2006.173.05:51:49.22#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.05:51:49.28#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.05:51:49.28#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.05:51:49.28#ibcon#enter wrdev, iclass 36, count 2 2006.173.05:51:49.28#ibcon#first serial, iclass 36, count 2 2006.173.05:51:49.28#ibcon#enter sib2, iclass 36, count 2 2006.173.05:51:49.28#ibcon#flushed, iclass 36, count 2 2006.173.05:51:49.28#ibcon#about to write, iclass 36, count 2 2006.173.05:51:49.28#ibcon#wrote, iclass 36, count 2 2006.173.05:51:49.28#ibcon#about to read 3, iclass 36, count 2 2006.173.05:51:49.30#ibcon#read 3, iclass 36, count 2 2006.173.05:51:49.30#ibcon#about to read 4, iclass 36, count 2 2006.173.05:51:49.30#ibcon#read 4, iclass 36, count 2 2006.173.05:51:49.30#ibcon#about to read 5, iclass 36, count 2 2006.173.05:51:49.30#ibcon#read 5, iclass 36, count 2 2006.173.05:51:49.30#ibcon#about to read 6, iclass 36, count 2 2006.173.05:51:49.30#ibcon#read 6, iclass 36, count 2 2006.173.05:51:49.30#ibcon#end of sib2, iclass 36, count 2 2006.173.05:51:49.30#ibcon#*mode == 0, iclass 36, count 2 2006.173.05:51:49.30#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.05:51:49.30#ibcon#[25=AT07-04\r\n] 2006.173.05:51:49.30#ibcon#*before write, iclass 36, count 2 2006.173.05:51:49.30#ibcon#enter sib2, iclass 36, count 2 2006.173.05:51:49.30#ibcon#flushed, iclass 36, count 2 2006.173.05:51:49.30#ibcon#about to write, iclass 36, count 2 2006.173.05:51:49.30#ibcon#wrote, iclass 36, count 2 2006.173.05:51:49.30#ibcon#about to read 3, iclass 36, count 2 2006.173.05:51:49.33#ibcon#read 3, iclass 36, count 2 2006.173.05:51:49.33#ibcon#about to read 4, iclass 36, count 2 2006.173.05:51:49.33#ibcon#read 4, iclass 36, count 2 2006.173.05:51:49.33#ibcon#about to read 5, iclass 36, count 2 2006.173.05:51:49.33#ibcon#read 5, iclass 36, count 2 2006.173.05:51:49.33#ibcon#about to read 6, iclass 36, count 2 2006.173.05:51:49.33#ibcon#read 6, iclass 36, count 2 2006.173.05:51:49.33#ibcon#end of sib2, iclass 36, count 2 2006.173.05:51:49.33#ibcon#*after write, iclass 36, count 2 2006.173.05:51:49.33#ibcon#*before return 0, iclass 36, count 2 2006.173.05:51:49.33#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.05:51:49.33#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.05:51:49.33#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.05:51:49.33#ibcon#ireg 7 cls_cnt 0 2006.173.05:51:49.33#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.05:51:49.45#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.05:51:49.45#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.05:51:49.45#ibcon#enter wrdev, iclass 36, count 0 2006.173.05:51:49.45#ibcon#first serial, iclass 36, count 0 2006.173.05:51:49.45#ibcon#enter sib2, iclass 36, count 0 2006.173.05:51:49.45#ibcon#flushed, iclass 36, count 0 2006.173.05:51:49.45#ibcon#about to write, iclass 36, count 0 2006.173.05:51:49.45#ibcon#wrote, iclass 36, count 0 2006.173.05:51:49.45#ibcon#about to read 3, iclass 36, count 0 2006.173.05:51:49.47#ibcon#read 3, iclass 36, count 0 2006.173.05:51:49.47#ibcon#about to read 4, iclass 36, count 0 2006.173.05:51:49.47#ibcon#read 4, iclass 36, count 0 2006.173.05:51:49.47#ibcon#about to read 5, iclass 36, count 0 2006.173.05:51:49.47#ibcon#read 5, iclass 36, count 0 2006.173.05:51:49.47#ibcon#about to read 6, iclass 36, count 0 2006.173.05:51:49.47#ibcon#read 6, iclass 36, count 0 2006.173.05:51:49.47#ibcon#end of sib2, iclass 36, count 0 2006.173.05:51:49.47#ibcon#*mode == 0, iclass 36, count 0 2006.173.05:51:49.47#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.05:51:49.47#ibcon#[25=USB\r\n] 2006.173.05:51:49.47#ibcon#*before write, iclass 36, count 0 2006.173.05:51:49.47#ibcon#enter sib2, iclass 36, count 0 2006.173.05:51:49.47#ibcon#flushed, iclass 36, count 0 2006.173.05:51:49.47#ibcon#about to write, iclass 36, count 0 2006.173.05:51:49.47#ibcon#wrote, iclass 36, count 0 2006.173.05:51:49.47#ibcon#about to read 3, iclass 36, count 0 2006.173.05:51:49.50#ibcon#read 3, iclass 36, count 0 2006.173.05:51:49.50#ibcon#about to read 4, iclass 36, count 0 2006.173.05:51:49.50#ibcon#read 4, iclass 36, count 0 2006.173.05:51:49.50#ibcon#about to read 5, iclass 36, count 0 2006.173.05:51:49.50#ibcon#read 5, iclass 36, count 0 2006.173.05:51:49.50#ibcon#about to read 6, iclass 36, count 0 2006.173.05:51:49.50#ibcon#read 6, iclass 36, count 0 2006.173.05:51:49.50#ibcon#end of sib2, iclass 36, count 0 2006.173.05:51:49.50#ibcon#*after write, iclass 36, count 0 2006.173.05:51:49.50#ibcon#*before return 0, iclass 36, count 0 2006.173.05:51:49.50#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.05:51:49.50#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.05:51:49.50#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.05:51:49.50#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.05:51:49.50$vck44/valo=8,884.99 2006.173.05:51:49.50#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.05:51:49.50#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.05:51:49.50#ibcon#ireg 17 cls_cnt 0 2006.173.05:51:49.50#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.05:51:49.50#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.05:51:49.50#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.05:51:49.50#ibcon#enter wrdev, iclass 38, count 0 2006.173.05:51:49.50#ibcon#first serial, iclass 38, count 0 2006.173.05:51:49.50#ibcon#enter sib2, iclass 38, count 0 2006.173.05:51:49.50#ibcon#flushed, iclass 38, count 0 2006.173.05:51:49.50#ibcon#about to write, iclass 38, count 0 2006.173.05:51:49.50#ibcon#wrote, iclass 38, count 0 2006.173.05:51:49.50#ibcon#about to read 3, iclass 38, count 0 2006.173.05:51:49.52#ibcon#read 3, iclass 38, count 0 2006.173.05:51:49.52#ibcon#about to read 4, iclass 38, count 0 2006.173.05:51:49.52#ibcon#read 4, iclass 38, count 0 2006.173.05:51:49.52#ibcon#about to read 5, iclass 38, count 0 2006.173.05:51:49.52#ibcon#read 5, iclass 38, count 0 2006.173.05:51:49.52#ibcon#about to read 6, iclass 38, count 0 2006.173.05:51:49.52#ibcon#read 6, iclass 38, count 0 2006.173.05:51:49.52#ibcon#end of sib2, iclass 38, count 0 2006.173.05:51:49.52#ibcon#*mode == 0, iclass 38, count 0 2006.173.05:51:49.52#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.05:51:49.52#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.05:51:49.52#ibcon#*before write, iclass 38, count 0 2006.173.05:51:49.52#ibcon#enter sib2, iclass 38, count 0 2006.173.05:51:49.52#ibcon#flushed, iclass 38, count 0 2006.173.05:51:49.52#ibcon#about to write, iclass 38, count 0 2006.173.05:51:49.52#ibcon#wrote, iclass 38, count 0 2006.173.05:51:49.52#ibcon#about to read 3, iclass 38, count 0 2006.173.05:51:49.56#ibcon#read 3, iclass 38, count 0 2006.173.05:51:49.56#ibcon#about to read 4, iclass 38, count 0 2006.173.05:51:49.56#ibcon#read 4, iclass 38, count 0 2006.173.05:51:49.56#ibcon#about to read 5, iclass 38, count 0 2006.173.05:51:49.56#ibcon#read 5, iclass 38, count 0 2006.173.05:51:49.56#ibcon#about to read 6, iclass 38, count 0 2006.173.05:51:49.56#ibcon#read 6, iclass 38, count 0 2006.173.05:51:49.56#ibcon#end of sib2, iclass 38, count 0 2006.173.05:51:49.56#ibcon#*after write, iclass 38, count 0 2006.173.05:51:49.56#ibcon#*before return 0, iclass 38, count 0 2006.173.05:51:49.56#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.05:51:49.56#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.05:51:49.56#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.05:51:49.56#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.05:51:49.56$vck44/va=8,4 2006.173.05:51:49.56#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.05:51:49.56#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.05:51:49.56#ibcon#ireg 11 cls_cnt 2 2006.173.05:51:49.56#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.05:51:49.62#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.05:51:49.62#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.05:51:49.62#ibcon#enter wrdev, iclass 40, count 2 2006.173.05:51:49.62#ibcon#first serial, iclass 40, count 2 2006.173.05:51:49.62#ibcon#enter sib2, iclass 40, count 2 2006.173.05:51:49.62#ibcon#flushed, iclass 40, count 2 2006.173.05:51:49.62#ibcon#about to write, iclass 40, count 2 2006.173.05:51:49.62#ibcon#wrote, iclass 40, count 2 2006.173.05:51:49.62#ibcon#about to read 3, iclass 40, count 2 2006.173.05:51:49.64#ibcon#read 3, iclass 40, count 2 2006.173.05:51:49.64#ibcon#about to read 4, iclass 40, count 2 2006.173.05:51:49.64#ibcon#read 4, iclass 40, count 2 2006.173.05:51:49.64#ibcon#about to read 5, iclass 40, count 2 2006.173.05:51:49.64#ibcon#read 5, iclass 40, count 2 2006.173.05:51:49.64#ibcon#about to read 6, iclass 40, count 2 2006.173.05:51:49.64#ibcon#read 6, iclass 40, count 2 2006.173.05:51:49.64#ibcon#end of sib2, iclass 40, count 2 2006.173.05:51:49.64#ibcon#*mode == 0, iclass 40, count 2 2006.173.05:51:49.64#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.05:51:49.64#ibcon#[25=AT08-04\r\n] 2006.173.05:51:49.64#ibcon#*before write, iclass 40, count 2 2006.173.05:51:49.64#ibcon#enter sib2, iclass 40, count 2 2006.173.05:51:49.64#ibcon#flushed, iclass 40, count 2 2006.173.05:51:49.64#ibcon#about to write, iclass 40, count 2 2006.173.05:51:49.64#ibcon#wrote, iclass 40, count 2 2006.173.05:51:49.64#ibcon#about to read 3, iclass 40, count 2 2006.173.05:51:49.67#ibcon#read 3, iclass 40, count 2 2006.173.05:51:49.67#ibcon#about to read 4, iclass 40, count 2 2006.173.05:51:49.67#ibcon#read 4, iclass 40, count 2 2006.173.05:51:49.67#ibcon#about to read 5, iclass 40, count 2 2006.173.05:51:49.67#ibcon#read 5, iclass 40, count 2 2006.173.05:51:49.67#ibcon#about to read 6, iclass 40, count 2 2006.173.05:51:49.67#ibcon#read 6, iclass 40, count 2 2006.173.05:51:49.67#ibcon#end of sib2, iclass 40, count 2 2006.173.05:51:49.67#ibcon#*after write, iclass 40, count 2 2006.173.05:51:49.67#ibcon#*before return 0, iclass 40, count 2 2006.173.05:51:49.67#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.05:51:49.67#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.05:51:49.67#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.05:51:49.67#ibcon#ireg 7 cls_cnt 0 2006.173.05:51:49.67#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.05:51:49.79#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.05:51:49.79#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.05:51:49.79#ibcon#enter wrdev, iclass 40, count 0 2006.173.05:51:49.79#ibcon#first serial, iclass 40, count 0 2006.173.05:51:49.79#ibcon#enter sib2, iclass 40, count 0 2006.173.05:51:49.79#ibcon#flushed, iclass 40, count 0 2006.173.05:51:49.79#ibcon#about to write, iclass 40, count 0 2006.173.05:51:49.79#ibcon#wrote, iclass 40, count 0 2006.173.05:51:49.79#ibcon#about to read 3, iclass 40, count 0 2006.173.05:51:49.81#ibcon#read 3, iclass 40, count 0 2006.173.05:51:49.81#ibcon#about to read 4, iclass 40, count 0 2006.173.05:51:49.81#ibcon#read 4, iclass 40, count 0 2006.173.05:51:49.81#ibcon#about to read 5, iclass 40, count 0 2006.173.05:51:49.81#ibcon#read 5, iclass 40, count 0 2006.173.05:51:49.81#ibcon#about to read 6, iclass 40, count 0 2006.173.05:51:49.81#ibcon#read 6, iclass 40, count 0 2006.173.05:51:49.81#ibcon#end of sib2, iclass 40, count 0 2006.173.05:51:49.81#ibcon#*mode == 0, iclass 40, count 0 2006.173.05:51:49.81#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.05:51:49.81#ibcon#[25=USB\r\n] 2006.173.05:51:49.81#ibcon#*before write, iclass 40, count 0 2006.173.05:51:49.81#ibcon#enter sib2, iclass 40, count 0 2006.173.05:51:49.81#ibcon#flushed, iclass 40, count 0 2006.173.05:51:49.81#ibcon#about to write, iclass 40, count 0 2006.173.05:51:49.81#ibcon#wrote, iclass 40, count 0 2006.173.05:51:49.81#ibcon#about to read 3, iclass 40, count 0 2006.173.05:51:49.84#ibcon#read 3, iclass 40, count 0 2006.173.05:51:49.84#ibcon#about to read 4, iclass 40, count 0 2006.173.05:51:49.84#ibcon#read 4, iclass 40, count 0 2006.173.05:51:49.84#ibcon#about to read 5, iclass 40, count 0 2006.173.05:51:49.84#ibcon#read 5, iclass 40, count 0 2006.173.05:51:49.84#ibcon#about to read 6, iclass 40, count 0 2006.173.05:51:49.84#ibcon#read 6, iclass 40, count 0 2006.173.05:51:49.84#ibcon#end of sib2, iclass 40, count 0 2006.173.05:51:49.84#ibcon#*after write, iclass 40, count 0 2006.173.05:51:49.84#ibcon#*before return 0, iclass 40, count 0 2006.173.05:51:49.84#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.05:51:49.84#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.05:51:49.84#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.05:51:49.84#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.05:51:49.84$vck44/vblo=1,629.99 2006.173.05:51:49.84#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.05:51:49.84#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.05:51:49.84#ibcon#ireg 17 cls_cnt 0 2006.173.05:51:49.84#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.05:51:49.84#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.05:51:49.84#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.05:51:49.84#ibcon#enter wrdev, iclass 4, count 0 2006.173.05:51:49.84#ibcon#first serial, iclass 4, count 0 2006.173.05:51:49.84#ibcon#enter sib2, iclass 4, count 0 2006.173.05:51:49.84#ibcon#flushed, iclass 4, count 0 2006.173.05:51:49.84#ibcon#about to write, iclass 4, count 0 2006.173.05:51:49.84#ibcon#wrote, iclass 4, count 0 2006.173.05:51:49.84#ibcon#about to read 3, iclass 4, count 0 2006.173.05:51:49.86#ibcon#read 3, iclass 4, count 0 2006.173.05:51:49.86#ibcon#about to read 4, iclass 4, count 0 2006.173.05:51:49.86#ibcon#read 4, iclass 4, count 0 2006.173.05:51:49.86#ibcon#about to read 5, iclass 4, count 0 2006.173.05:51:49.86#ibcon#read 5, iclass 4, count 0 2006.173.05:51:49.86#ibcon#about to read 6, iclass 4, count 0 2006.173.05:51:49.86#ibcon#read 6, iclass 4, count 0 2006.173.05:51:49.86#ibcon#end of sib2, iclass 4, count 0 2006.173.05:51:49.86#ibcon#*mode == 0, iclass 4, count 0 2006.173.05:51:49.86#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.05:51:49.86#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.05:51:49.86#ibcon#*before write, iclass 4, count 0 2006.173.05:51:49.86#ibcon#enter sib2, iclass 4, count 0 2006.173.05:51:49.86#ibcon#flushed, iclass 4, count 0 2006.173.05:51:49.86#ibcon#about to write, iclass 4, count 0 2006.173.05:51:49.86#ibcon#wrote, iclass 4, count 0 2006.173.05:51:49.86#ibcon#about to read 3, iclass 4, count 0 2006.173.05:51:49.90#ibcon#read 3, iclass 4, count 0 2006.173.05:51:49.90#ibcon#about to read 4, iclass 4, count 0 2006.173.05:51:49.90#ibcon#read 4, iclass 4, count 0 2006.173.05:51:49.90#ibcon#about to read 5, iclass 4, count 0 2006.173.05:51:49.90#ibcon#read 5, iclass 4, count 0 2006.173.05:51:49.90#ibcon#about to read 6, iclass 4, count 0 2006.173.05:51:49.90#ibcon#read 6, iclass 4, count 0 2006.173.05:51:49.90#ibcon#end of sib2, iclass 4, count 0 2006.173.05:51:49.90#ibcon#*after write, iclass 4, count 0 2006.173.05:51:49.90#ibcon#*before return 0, iclass 4, count 0 2006.173.05:51:49.90#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.05:51:49.90#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.05:51:49.90#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.05:51:49.90#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.05:51:49.90$vck44/vb=1,4 2006.173.05:51:49.90#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.05:51:49.90#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.05:51:49.90#ibcon#ireg 11 cls_cnt 2 2006.173.05:51:49.90#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.05:51:49.90#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.05:51:49.90#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.05:51:49.90#ibcon#enter wrdev, iclass 6, count 2 2006.173.05:51:49.90#ibcon#first serial, iclass 6, count 2 2006.173.05:51:49.90#ibcon#enter sib2, iclass 6, count 2 2006.173.05:51:49.90#ibcon#flushed, iclass 6, count 2 2006.173.05:51:49.90#ibcon#about to write, iclass 6, count 2 2006.173.05:51:49.90#ibcon#wrote, iclass 6, count 2 2006.173.05:51:49.90#ibcon#about to read 3, iclass 6, count 2 2006.173.05:51:49.92#ibcon#read 3, iclass 6, count 2 2006.173.05:51:49.92#ibcon#about to read 4, iclass 6, count 2 2006.173.05:51:49.92#ibcon#read 4, iclass 6, count 2 2006.173.05:51:49.92#ibcon#about to read 5, iclass 6, count 2 2006.173.05:51:49.92#ibcon#read 5, iclass 6, count 2 2006.173.05:51:49.92#ibcon#about to read 6, iclass 6, count 2 2006.173.05:51:49.92#ibcon#read 6, iclass 6, count 2 2006.173.05:51:49.92#ibcon#end of sib2, iclass 6, count 2 2006.173.05:51:49.92#ibcon#*mode == 0, iclass 6, count 2 2006.173.05:51:49.92#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.05:51:49.92#ibcon#[27=AT01-04\r\n] 2006.173.05:51:49.92#ibcon#*before write, iclass 6, count 2 2006.173.05:51:49.92#ibcon#enter sib2, iclass 6, count 2 2006.173.05:51:49.92#ibcon#flushed, iclass 6, count 2 2006.173.05:51:49.92#ibcon#about to write, iclass 6, count 2 2006.173.05:51:49.92#ibcon#wrote, iclass 6, count 2 2006.173.05:51:49.92#ibcon#about to read 3, iclass 6, count 2 2006.173.05:51:49.95#ibcon#read 3, iclass 6, count 2 2006.173.05:51:49.95#ibcon#about to read 4, iclass 6, count 2 2006.173.05:51:49.95#ibcon#read 4, iclass 6, count 2 2006.173.05:51:49.95#ibcon#about to read 5, iclass 6, count 2 2006.173.05:51:49.95#ibcon#read 5, iclass 6, count 2 2006.173.05:51:49.95#ibcon#about to read 6, iclass 6, count 2 2006.173.05:51:49.95#ibcon#read 6, iclass 6, count 2 2006.173.05:51:49.95#ibcon#end of sib2, iclass 6, count 2 2006.173.05:51:49.95#ibcon#*after write, iclass 6, count 2 2006.173.05:51:49.95#ibcon#*before return 0, iclass 6, count 2 2006.173.05:51:49.95#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.05:51:49.95#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.05:51:49.95#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.05:51:49.95#ibcon#ireg 7 cls_cnt 0 2006.173.05:51:49.95#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.05:51:50.07#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.05:51:50.07#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.05:51:50.07#ibcon#enter wrdev, iclass 6, count 0 2006.173.05:51:50.07#ibcon#first serial, iclass 6, count 0 2006.173.05:51:50.07#ibcon#enter sib2, iclass 6, count 0 2006.173.05:51:50.07#ibcon#flushed, iclass 6, count 0 2006.173.05:51:50.07#ibcon#about to write, iclass 6, count 0 2006.173.05:51:50.07#ibcon#wrote, iclass 6, count 0 2006.173.05:51:50.07#ibcon#about to read 3, iclass 6, count 0 2006.173.05:51:50.09#ibcon#read 3, iclass 6, count 0 2006.173.05:51:50.09#ibcon#about to read 4, iclass 6, count 0 2006.173.05:51:50.09#ibcon#read 4, iclass 6, count 0 2006.173.05:51:50.09#ibcon#about to read 5, iclass 6, count 0 2006.173.05:51:50.09#ibcon#read 5, iclass 6, count 0 2006.173.05:51:50.09#ibcon#about to read 6, iclass 6, count 0 2006.173.05:51:50.09#ibcon#read 6, iclass 6, count 0 2006.173.05:51:50.09#ibcon#end of sib2, iclass 6, count 0 2006.173.05:51:50.09#ibcon#*mode == 0, iclass 6, count 0 2006.173.05:51:50.09#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.05:51:50.09#ibcon#[27=USB\r\n] 2006.173.05:51:50.09#ibcon#*before write, iclass 6, count 0 2006.173.05:51:50.09#ibcon#enter sib2, iclass 6, count 0 2006.173.05:51:50.09#ibcon#flushed, iclass 6, count 0 2006.173.05:51:50.09#ibcon#about to write, iclass 6, count 0 2006.173.05:51:50.09#ibcon#wrote, iclass 6, count 0 2006.173.05:51:50.09#ibcon#about to read 3, iclass 6, count 0 2006.173.05:51:50.12#ibcon#read 3, iclass 6, count 0 2006.173.05:51:50.12#ibcon#about to read 4, iclass 6, count 0 2006.173.05:51:50.12#ibcon#read 4, iclass 6, count 0 2006.173.05:51:50.12#ibcon#about to read 5, iclass 6, count 0 2006.173.05:51:50.12#ibcon#read 5, iclass 6, count 0 2006.173.05:51:50.12#ibcon#about to read 6, iclass 6, count 0 2006.173.05:51:50.12#ibcon#read 6, iclass 6, count 0 2006.173.05:51:50.12#ibcon#end of sib2, iclass 6, count 0 2006.173.05:51:50.12#ibcon#*after write, iclass 6, count 0 2006.173.05:51:50.12#ibcon#*before return 0, iclass 6, count 0 2006.173.05:51:50.12#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.05:51:50.12#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.05:51:50.12#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.05:51:50.12#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.05:51:50.12$vck44/vblo=2,634.99 2006.173.05:51:50.12#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.05:51:50.12#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.05:51:50.12#ibcon#ireg 17 cls_cnt 0 2006.173.05:51:50.12#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.05:51:50.12#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.05:51:50.12#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.05:51:50.12#ibcon#enter wrdev, iclass 10, count 0 2006.173.05:51:50.12#ibcon#first serial, iclass 10, count 0 2006.173.05:51:50.12#ibcon#enter sib2, iclass 10, count 0 2006.173.05:51:50.12#ibcon#flushed, iclass 10, count 0 2006.173.05:51:50.12#ibcon#about to write, iclass 10, count 0 2006.173.05:51:50.12#ibcon#wrote, iclass 10, count 0 2006.173.05:51:50.12#ibcon#about to read 3, iclass 10, count 0 2006.173.05:51:50.14#ibcon#read 3, iclass 10, count 0 2006.173.05:51:50.14#ibcon#about to read 4, iclass 10, count 0 2006.173.05:51:50.14#ibcon#read 4, iclass 10, count 0 2006.173.05:51:50.14#ibcon#about to read 5, iclass 10, count 0 2006.173.05:51:50.14#ibcon#read 5, iclass 10, count 0 2006.173.05:51:50.14#ibcon#about to read 6, iclass 10, count 0 2006.173.05:51:50.14#ibcon#read 6, iclass 10, count 0 2006.173.05:51:50.14#ibcon#end of sib2, iclass 10, count 0 2006.173.05:51:50.14#ibcon#*mode == 0, iclass 10, count 0 2006.173.05:51:50.14#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.05:51:50.14#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.05:51:50.14#ibcon#*before write, iclass 10, count 0 2006.173.05:51:50.14#ibcon#enter sib2, iclass 10, count 0 2006.173.05:51:50.14#ibcon#flushed, iclass 10, count 0 2006.173.05:51:50.14#ibcon#about to write, iclass 10, count 0 2006.173.05:51:50.14#ibcon#wrote, iclass 10, count 0 2006.173.05:51:50.14#ibcon#about to read 3, iclass 10, count 0 2006.173.05:51:50.18#ibcon#read 3, iclass 10, count 0 2006.173.05:51:50.18#ibcon#about to read 4, iclass 10, count 0 2006.173.05:51:50.18#ibcon#read 4, iclass 10, count 0 2006.173.05:51:50.18#ibcon#about to read 5, iclass 10, count 0 2006.173.05:51:50.18#ibcon#read 5, iclass 10, count 0 2006.173.05:51:50.18#ibcon#about to read 6, iclass 10, count 0 2006.173.05:51:50.18#ibcon#read 6, iclass 10, count 0 2006.173.05:51:50.18#ibcon#end of sib2, iclass 10, count 0 2006.173.05:51:50.18#ibcon#*after write, iclass 10, count 0 2006.173.05:51:50.18#ibcon#*before return 0, iclass 10, count 0 2006.173.05:51:50.18#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.05:51:50.18#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.05:51:50.18#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.05:51:50.18#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.05:51:50.18$vck44/vb=2,4 2006.173.05:51:50.18#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.05:51:50.18#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.05:51:50.18#ibcon#ireg 11 cls_cnt 2 2006.173.05:51:50.18#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.05:51:50.24#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.05:51:50.24#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.05:51:50.24#ibcon#enter wrdev, iclass 12, count 2 2006.173.05:51:50.24#ibcon#first serial, iclass 12, count 2 2006.173.05:51:50.24#ibcon#enter sib2, iclass 12, count 2 2006.173.05:51:50.24#ibcon#flushed, iclass 12, count 2 2006.173.05:51:50.24#ibcon#about to write, iclass 12, count 2 2006.173.05:51:50.24#ibcon#wrote, iclass 12, count 2 2006.173.05:51:50.24#ibcon#about to read 3, iclass 12, count 2 2006.173.05:51:50.26#ibcon#read 3, iclass 12, count 2 2006.173.05:51:50.26#ibcon#about to read 4, iclass 12, count 2 2006.173.05:51:50.26#ibcon#read 4, iclass 12, count 2 2006.173.05:51:50.26#ibcon#about to read 5, iclass 12, count 2 2006.173.05:51:50.26#ibcon#read 5, iclass 12, count 2 2006.173.05:51:50.26#ibcon#about to read 6, iclass 12, count 2 2006.173.05:51:50.26#ibcon#read 6, iclass 12, count 2 2006.173.05:51:50.26#ibcon#end of sib2, iclass 12, count 2 2006.173.05:51:50.26#ibcon#*mode == 0, iclass 12, count 2 2006.173.05:51:50.26#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.05:51:50.26#ibcon#[27=AT02-04\r\n] 2006.173.05:51:50.26#ibcon#*before write, iclass 12, count 2 2006.173.05:51:50.26#ibcon#enter sib2, iclass 12, count 2 2006.173.05:51:50.26#ibcon#flushed, iclass 12, count 2 2006.173.05:51:50.26#ibcon#about to write, iclass 12, count 2 2006.173.05:51:50.26#ibcon#wrote, iclass 12, count 2 2006.173.05:51:50.26#ibcon#about to read 3, iclass 12, count 2 2006.173.05:51:50.29#ibcon#read 3, iclass 12, count 2 2006.173.05:51:50.29#ibcon#about to read 4, iclass 12, count 2 2006.173.05:51:50.29#ibcon#read 4, iclass 12, count 2 2006.173.05:51:50.29#ibcon#about to read 5, iclass 12, count 2 2006.173.05:51:50.29#ibcon#read 5, iclass 12, count 2 2006.173.05:51:50.29#ibcon#about to read 6, iclass 12, count 2 2006.173.05:51:50.29#ibcon#read 6, iclass 12, count 2 2006.173.05:51:50.29#ibcon#end of sib2, iclass 12, count 2 2006.173.05:51:50.29#ibcon#*after write, iclass 12, count 2 2006.173.05:51:50.29#ibcon#*before return 0, iclass 12, count 2 2006.173.05:51:50.29#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.05:51:50.29#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.05:51:50.29#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.05:51:50.29#ibcon#ireg 7 cls_cnt 0 2006.173.05:51:50.29#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.05:51:50.41#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.05:51:50.41#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.05:51:50.41#ibcon#enter wrdev, iclass 12, count 0 2006.173.05:51:50.41#ibcon#first serial, iclass 12, count 0 2006.173.05:51:50.41#ibcon#enter sib2, iclass 12, count 0 2006.173.05:51:50.41#ibcon#flushed, iclass 12, count 0 2006.173.05:51:50.41#ibcon#about to write, iclass 12, count 0 2006.173.05:51:50.41#ibcon#wrote, iclass 12, count 0 2006.173.05:51:50.41#ibcon#about to read 3, iclass 12, count 0 2006.173.05:51:50.43#ibcon#read 3, iclass 12, count 0 2006.173.05:51:50.43#ibcon#about to read 4, iclass 12, count 0 2006.173.05:51:50.43#ibcon#read 4, iclass 12, count 0 2006.173.05:51:50.43#ibcon#about to read 5, iclass 12, count 0 2006.173.05:51:50.43#ibcon#read 5, iclass 12, count 0 2006.173.05:51:50.43#ibcon#about to read 6, iclass 12, count 0 2006.173.05:51:50.43#ibcon#read 6, iclass 12, count 0 2006.173.05:51:50.43#ibcon#end of sib2, iclass 12, count 0 2006.173.05:51:50.43#ibcon#*mode == 0, iclass 12, count 0 2006.173.05:51:50.43#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.05:51:50.43#ibcon#[27=USB\r\n] 2006.173.05:51:50.43#ibcon#*before write, iclass 12, count 0 2006.173.05:51:50.43#ibcon#enter sib2, iclass 12, count 0 2006.173.05:51:50.43#ibcon#flushed, iclass 12, count 0 2006.173.05:51:50.43#ibcon#about to write, iclass 12, count 0 2006.173.05:51:50.43#ibcon#wrote, iclass 12, count 0 2006.173.05:51:50.43#ibcon#about to read 3, iclass 12, count 0 2006.173.05:51:50.46#ibcon#read 3, iclass 12, count 0 2006.173.05:51:50.46#ibcon#about to read 4, iclass 12, count 0 2006.173.05:51:50.46#ibcon#read 4, iclass 12, count 0 2006.173.05:51:50.46#ibcon#about to read 5, iclass 12, count 0 2006.173.05:51:50.46#ibcon#read 5, iclass 12, count 0 2006.173.05:51:50.46#ibcon#about to read 6, iclass 12, count 0 2006.173.05:51:50.46#ibcon#read 6, iclass 12, count 0 2006.173.05:51:50.46#ibcon#end of sib2, iclass 12, count 0 2006.173.05:51:50.46#ibcon#*after write, iclass 12, count 0 2006.173.05:51:50.46#ibcon#*before return 0, iclass 12, count 0 2006.173.05:51:50.46#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.05:51:50.46#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.05:51:50.46#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.05:51:50.46#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.05:51:50.46$vck44/vblo=3,649.99 2006.173.05:51:50.46#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.05:51:50.46#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.05:51:50.46#ibcon#ireg 17 cls_cnt 0 2006.173.05:51:50.46#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.05:51:50.46#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.05:51:50.46#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.05:51:50.46#ibcon#enter wrdev, iclass 14, count 0 2006.173.05:51:50.46#ibcon#first serial, iclass 14, count 0 2006.173.05:51:50.46#ibcon#enter sib2, iclass 14, count 0 2006.173.05:51:50.46#ibcon#flushed, iclass 14, count 0 2006.173.05:51:50.46#ibcon#about to write, iclass 14, count 0 2006.173.05:51:50.46#ibcon#wrote, iclass 14, count 0 2006.173.05:51:50.46#ibcon#about to read 3, iclass 14, count 0 2006.173.05:51:50.48#ibcon#read 3, iclass 14, count 0 2006.173.05:51:50.48#ibcon#about to read 4, iclass 14, count 0 2006.173.05:51:50.48#ibcon#read 4, iclass 14, count 0 2006.173.05:51:50.48#ibcon#about to read 5, iclass 14, count 0 2006.173.05:51:50.48#ibcon#read 5, iclass 14, count 0 2006.173.05:51:50.48#ibcon#about to read 6, iclass 14, count 0 2006.173.05:51:50.48#ibcon#read 6, iclass 14, count 0 2006.173.05:51:50.48#ibcon#end of sib2, iclass 14, count 0 2006.173.05:51:50.48#ibcon#*mode == 0, iclass 14, count 0 2006.173.05:51:50.48#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.05:51:50.48#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.05:51:50.48#ibcon#*before write, iclass 14, count 0 2006.173.05:51:50.48#ibcon#enter sib2, iclass 14, count 0 2006.173.05:51:50.48#ibcon#flushed, iclass 14, count 0 2006.173.05:51:50.48#ibcon#about to write, iclass 14, count 0 2006.173.05:51:50.48#ibcon#wrote, iclass 14, count 0 2006.173.05:51:50.48#ibcon#about to read 3, iclass 14, count 0 2006.173.05:51:50.52#ibcon#read 3, iclass 14, count 0 2006.173.05:51:50.52#ibcon#about to read 4, iclass 14, count 0 2006.173.05:51:50.52#ibcon#read 4, iclass 14, count 0 2006.173.05:51:50.52#ibcon#about to read 5, iclass 14, count 0 2006.173.05:51:50.52#ibcon#read 5, iclass 14, count 0 2006.173.05:51:50.52#ibcon#about to read 6, iclass 14, count 0 2006.173.05:51:50.52#ibcon#read 6, iclass 14, count 0 2006.173.05:51:50.52#ibcon#end of sib2, iclass 14, count 0 2006.173.05:51:50.52#ibcon#*after write, iclass 14, count 0 2006.173.05:51:50.52#ibcon#*before return 0, iclass 14, count 0 2006.173.05:51:50.52#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.05:51:50.52#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.05:51:50.52#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.05:51:50.52#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.05:51:50.52$vck44/vb=3,4 2006.173.05:51:50.52#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.05:51:50.52#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.05:51:50.52#ibcon#ireg 11 cls_cnt 2 2006.173.05:51:50.52#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.05:51:50.58#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.05:51:50.58#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.05:51:50.58#ibcon#enter wrdev, iclass 16, count 2 2006.173.05:51:50.58#ibcon#first serial, iclass 16, count 2 2006.173.05:51:50.58#ibcon#enter sib2, iclass 16, count 2 2006.173.05:51:50.58#ibcon#flushed, iclass 16, count 2 2006.173.05:51:50.58#ibcon#about to write, iclass 16, count 2 2006.173.05:51:50.58#ibcon#wrote, iclass 16, count 2 2006.173.05:51:50.58#ibcon#about to read 3, iclass 16, count 2 2006.173.05:51:50.60#ibcon#read 3, iclass 16, count 2 2006.173.05:51:50.60#ibcon#about to read 4, iclass 16, count 2 2006.173.05:51:50.60#ibcon#read 4, iclass 16, count 2 2006.173.05:51:50.60#ibcon#about to read 5, iclass 16, count 2 2006.173.05:51:50.60#ibcon#read 5, iclass 16, count 2 2006.173.05:51:50.60#ibcon#about to read 6, iclass 16, count 2 2006.173.05:51:50.60#ibcon#read 6, iclass 16, count 2 2006.173.05:51:50.60#ibcon#end of sib2, iclass 16, count 2 2006.173.05:51:50.60#ibcon#*mode == 0, iclass 16, count 2 2006.173.05:51:50.60#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.05:51:50.60#ibcon#[27=AT03-04\r\n] 2006.173.05:51:50.60#ibcon#*before write, iclass 16, count 2 2006.173.05:51:50.60#ibcon#enter sib2, iclass 16, count 2 2006.173.05:51:50.60#ibcon#flushed, iclass 16, count 2 2006.173.05:51:50.60#ibcon#about to write, iclass 16, count 2 2006.173.05:51:50.60#ibcon#wrote, iclass 16, count 2 2006.173.05:51:50.60#ibcon#about to read 3, iclass 16, count 2 2006.173.05:51:50.63#ibcon#read 3, iclass 16, count 2 2006.173.05:51:50.63#ibcon#about to read 4, iclass 16, count 2 2006.173.05:51:50.63#ibcon#read 4, iclass 16, count 2 2006.173.05:51:50.63#ibcon#about to read 5, iclass 16, count 2 2006.173.05:51:50.63#ibcon#read 5, iclass 16, count 2 2006.173.05:51:50.63#ibcon#about to read 6, iclass 16, count 2 2006.173.05:51:50.63#ibcon#read 6, iclass 16, count 2 2006.173.05:51:50.63#ibcon#end of sib2, iclass 16, count 2 2006.173.05:51:50.63#ibcon#*after write, iclass 16, count 2 2006.173.05:51:50.63#ibcon#*before return 0, iclass 16, count 2 2006.173.05:51:50.63#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.05:51:50.63#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.05:51:50.63#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.05:51:50.63#ibcon#ireg 7 cls_cnt 0 2006.173.05:51:50.63#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.05:51:50.75#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.05:51:50.75#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.05:51:50.75#ibcon#enter wrdev, iclass 16, count 0 2006.173.05:51:50.75#ibcon#first serial, iclass 16, count 0 2006.173.05:51:50.75#ibcon#enter sib2, iclass 16, count 0 2006.173.05:51:50.75#ibcon#flushed, iclass 16, count 0 2006.173.05:51:50.75#ibcon#about to write, iclass 16, count 0 2006.173.05:51:50.75#ibcon#wrote, iclass 16, count 0 2006.173.05:51:50.75#ibcon#about to read 3, iclass 16, count 0 2006.173.05:51:50.77#ibcon#read 3, iclass 16, count 0 2006.173.05:51:50.77#ibcon#about to read 4, iclass 16, count 0 2006.173.05:51:50.77#ibcon#read 4, iclass 16, count 0 2006.173.05:51:50.77#ibcon#about to read 5, iclass 16, count 0 2006.173.05:51:50.77#ibcon#read 5, iclass 16, count 0 2006.173.05:51:50.77#ibcon#about to read 6, iclass 16, count 0 2006.173.05:51:50.77#ibcon#read 6, iclass 16, count 0 2006.173.05:51:50.77#ibcon#end of sib2, iclass 16, count 0 2006.173.05:51:50.77#ibcon#*mode == 0, iclass 16, count 0 2006.173.05:51:50.77#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.05:51:50.77#ibcon#[27=USB\r\n] 2006.173.05:51:50.77#ibcon#*before write, iclass 16, count 0 2006.173.05:51:50.77#ibcon#enter sib2, iclass 16, count 0 2006.173.05:51:50.77#ibcon#flushed, iclass 16, count 0 2006.173.05:51:50.77#ibcon#about to write, iclass 16, count 0 2006.173.05:51:50.77#ibcon#wrote, iclass 16, count 0 2006.173.05:51:50.77#ibcon#about to read 3, iclass 16, count 0 2006.173.05:51:50.80#ibcon#read 3, iclass 16, count 0 2006.173.05:51:50.80#ibcon#about to read 4, iclass 16, count 0 2006.173.05:51:50.80#ibcon#read 4, iclass 16, count 0 2006.173.05:51:50.80#ibcon#about to read 5, iclass 16, count 0 2006.173.05:51:50.80#ibcon#read 5, iclass 16, count 0 2006.173.05:51:50.80#ibcon#about to read 6, iclass 16, count 0 2006.173.05:51:50.80#ibcon#read 6, iclass 16, count 0 2006.173.05:51:50.80#ibcon#end of sib2, iclass 16, count 0 2006.173.05:51:50.80#ibcon#*after write, iclass 16, count 0 2006.173.05:51:50.80#ibcon#*before return 0, iclass 16, count 0 2006.173.05:51:50.80#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.05:51:50.80#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.05:51:50.80#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.05:51:50.80#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.05:51:50.80$vck44/vblo=4,679.99 2006.173.05:51:50.80#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.05:51:50.80#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.05:51:50.80#ibcon#ireg 17 cls_cnt 0 2006.173.05:51:50.80#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.05:51:50.80#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.05:51:50.80#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.05:51:50.80#ibcon#enter wrdev, iclass 18, count 0 2006.173.05:51:50.80#ibcon#first serial, iclass 18, count 0 2006.173.05:51:50.80#ibcon#enter sib2, iclass 18, count 0 2006.173.05:51:50.80#ibcon#flushed, iclass 18, count 0 2006.173.05:51:50.80#ibcon#about to write, iclass 18, count 0 2006.173.05:51:50.80#ibcon#wrote, iclass 18, count 0 2006.173.05:51:50.80#ibcon#about to read 3, iclass 18, count 0 2006.173.05:51:50.82#ibcon#read 3, iclass 18, count 0 2006.173.05:51:50.82#ibcon#about to read 4, iclass 18, count 0 2006.173.05:51:50.82#ibcon#read 4, iclass 18, count 0 2006.173.05:51:50.82#ibcon#about to read 5, iclass 18, count 0 2006.173.05:51:50.82#ibcon#read 5, iclass 18, count 0 2006.173.05:51:50.82#ibcon#about to read 6, iclass 18, count 0 2006.173.05:51:50.82#ibcon#read 6, iclass 18, count 0 2006.173.05:51:50.82#ibcon#end of sib2, iclass 18, count 0 2006.173.05:51:50.82#ibcon#*mode == 0, iclass 18, count 0 2006.173.05:51:50.82#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.05:51:50.82#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.05:51:50.82#ibcon#*before write, iclass 18, count 0 2006.173.05:51:50.82#ibcon#enter sib2, iclass 18, count 0 2006.173.05:51:50.82#ibcon#flushed, iclass 18, count 0 2006.173.05:51:50.82#ibcon#about to write, iclass 18, count 0 2006.173.05:51:50.82#ibcon#wrote, iclass 18, count 0 2006.173.05:51:50.82#ibcon#about to read 3, iclass 18, count 0 2006.173.05:51:50.86#ibcon#read 3, iclass 18, count 0 2006.173.05:51:50.86#ibcon#about to read 4, iclass 18, count 0 2006.173.05:51:50.86#ibcon#read 4, iclass 18, count 0 2006.173.05:51:50.86#ibcon#about to read 5, iclass 18, count 0 2006.173.05:51:50.86#ibcon#read 5, iclass 18, count 0 2006.173.05:51:50.86#ibcon#about to read 6, iclass 18, count 0 2006.173.05:51:50.86#ibcon#read 6, iclass 18, count 0 2006.173.05:51:50.86#ibcon#end of sib2, iclass 18, count 0 2006.173.05:51:50.86#ibcon#*after write, iclass 18, count 0 2006.173.05:51:50.86#ibcon#*before return 0, iclass 18, count 0 2006.173.05:51:50.86#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.05:51:50.86#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.05:51:50.86#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.05:51:50.86#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.05:51:50.86$vck44/vb=4,4 2006.173.05:51:50.86#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.05:51:50.86#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.05:51:50.86#ibcon#ireg 11 cls_cnt 2 2006.173.05:51:50.86#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.05:51:50.92#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.05:51:50.92#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.05:51:50.92#ibcon#enter wrdev, iclass 20, count 2 2006.173.05:51:50.92#ibcon#first serial, iclass 20, count 2 2006.173.05:51:50.92#ibcon#enter sib2, iclass 20, count 2 2006.173.05:51:50.92#ibcon#flushed, iclass 20, count 2 2006.173.05:51:50.92#ibcon#about to write, iclass 20, count 2 2006.173.05:51:50.92#ibcon#wrote, iclass 20, count 2 2006.173.05:51:50.92#ibcon#about to read 3, iclass 20, count 2 2006.173.05:51:50.94#ibcon#read 3, iclass 20, count 2 2006.173.05:51:50.94#ibcon#about to read 4, iclass 20, count 2 2006.173.05:51:50.94#ibcon#read 4, iclass 20, count 2 2006.173.05:51:50.94#ibcon#about to read 5, iclass 20, count 2 2006.173.05:51:50.94#ibcon#read 5, iclass 20, count 2 2006.173.05:51:50.94#ibcon#about to read 6, iclass 20, count 2 2006.173.05:51:50.94#ibcon#read 6, iclass 20, count 2 2006.173.05:51:50.94#ibcon#end of sib2, iclass 20, count 2 2006.173.05:51:50.94#ibcon#*mode == 0, iclass 20, count 2 2006.173.05:51:50.94#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.05:51:50.94#ibcon#[27=AT04-04\r\n] 2006.173.05:51:50.94#ibcon#*before write, iclass 20, count 2 2006.173.05:51:50.94#ibcon#enter sib2, iclass 20, count 2 2006.173.05:51:50.94#ibcon#flushed, iclass 20, count 2 2006.173.05:51:50.94#ibcon#about to write, iclass 20, count 2 2006.173.05:51:50.94#ibcon#wrote, iclass 20, count 2 2006.173.05:51:50.94#ibcon#about to read 3, iclass 20, count 2 2006.173.05:51:50.97#ibcon#read 3, iclass 20, count 2 2006.173.05:51:50.97#ibcon#about to read 4, iclass 20, count 2 2006.173.05:51:50.97#ibcon#read 4, iclass 20, count 2 2006.173.05:51:50.97#ibcon#about to read 5, iclass 20, count 2 2006.173.05:51:50.97#ibcon#read 5, iclass 20, count 2 2006.173.05:51:50.97#ibcon#about to read 6, iclass 20, count 2 2006.173.05:51:50.97#ibcon#read 6, iclass 20, count 2 2006.173.05:51:50.97#ibcon#end of sib2, iclass 20, count 2 2006.173.05:51:50.97#ibcon#*after write, iclass 20, count 2 2006.173.05:51:50.97#ibcon#*before return 0, iclass 20, count 2 2006.173.05:51:50.97#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.05:51:50.97#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.05:51:50.97#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.05:51:50.97#ibcon#ireg 7 cls_cnt 0 2006.173.05:51:50.97#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.05:51:51.09#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.05:51:51.09#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.05:51:51.09#ibcon#enter wrdev, iclass 20, count 0 2006.173.05:51:51.09#ibcon#first serial, iclass 20, count 0 2006.173.05:51:51.09#ibcon#enter sib2, iclass 20, count 0 2006.173.05:51:51.09#ibcon#flushed, iclass 20, count 0 2006.173.05:51:51.09#ibcon#about to write, iclass 20, count 0 2006.173.05:51:51.09#ibcon#wrote, iclass 20, count 0 2006.173.05:51:51.09#ibcon#about to read 3, iclass 20, count 0 2006.173.05:51:51.11#ibcon#read 3, iclass 20, count 0 2006.173.05:51:51.11#ibcon#about to read 4, iclass 20, count 0 2006.173.05:51:51.11#ibcon#read 4, iclass 20, count 0 2006.173.05:51:51.11#ibcon#about to read 5, iclass 20, count 0 2006.173.05:51:51.11#ibcon#read 5, iclass 20, count 0 2006.173.05:51:51.11#ibcon#about to read 6, iclass 20, count 0 2006.173.05:51:51.11#ibcon#read 6, iclass 20, count 0 2006.173.05:51:51.11#ibcon#end of sib2, iclass 20, count 0 2006.173.05:51:51.11#ibcon#*mode == 0, iclass 20, count 0 2006.173.05:51:51.11#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.05:51:51.11#ibcon#[27=USB\r\n] 2006.173.05:51:51.11#ibcon#*before write, iclass 20, count 0 2006.173.05:51:51.11#ibcon#enter sib2, iclass 20, count 0 2006.173.05:51:51.11#ibcon#flushed, iclass 20, count 0 2006.173.05:51:51.11#ibcon#about to write, iclass 20, count 0 2006.173.05:51:51.11#ibcon#wrote, iclass 20, count 0 2006.173.05:51:51.11#ibcon#about to read 3, iclass 20, count 0 2006.173.05:51:51.14#ibcon#read 3, iclass 20, count 0 2006.173.05:51:51.14#ibcon#about to read 4, iclass 20, count 0 2006.173.05:51:51.14#ibcon#read 4, iclass 20, count 0 2006.173.05:51:51.14#ibcon#about to read 5, iclass 20, count 0 2006.173.05:51:51.14#ibcon#read 5, iclass 20, count 0 2006.173.05:51:51.14#ibcon#about to read 6, iclass 20, count 0 2006.173.05:51:51.14#ibcon#read 6, iclass 20, count 0 2006.173.05:51:51.14#ibcon#end of sib2, iclass 20, count 0 2006.173.05:51:51.14#ibcon#*after write, iclass 20, count 0 2006.173.05:51:51.14#ibcon#*before return 0, iclass 20, count 0 2006.173.05:51:51.14#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.05:51:51.14#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.05:51:51.14#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.05:51:51.14#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.05:51:51.14$vck44/vblo=5,709.99 2006.173.05:51:51.14#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.05:51:51.14#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.05:51:51.14#ibcon#ireg 17 cls_cnt 0 2006.173.05:51:51.14#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.05:51:51.14#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.05:51:51.14#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.05:51:51.14#ibcon#enter wrdev, iclass 22, count 0 2006.173.05:51:51.14#ibcon#first serial, iclass 22, count 0 2006.173.05:51:51.14#ibcon#enter sib2, iclass 22, count 0 2006.173.05:51:51.14#ibcon#flushed, iclass 22, count 0 2006.173.05:51:51.14#ibcon#about to write, iclass 22, count 0 2006.173.05:51:51.14#ibcon#wrote, iclass 22, count 0 2006.173.05:51:51.14#ibcon#about to read 3, iclass 22, count 0 2006.173.05:51:51.16#ibcon#read 3, iclass 22, count 0 2006.173.05:51:51.16#ibcon#about to read 4, iclass 22, count 0 2006.173.05:51:51.16#ibcon#read 4, iclass 22, count 0 2006.173.05:51:51.16#ibcon#about to read 5, iclass 22, count 0 2006.173.05:51:51.16#ibcon#read 5, iclass 22, count 0 2006.173.05:51:51.16#ibcon#about to read 6, iclass 22, count 0 2006.173.05:51:51.16#ibcon#read 6, iclass 22, count 0 2006.173.05:51:51.16#ibcon#end of sib2, iclass 22, count 0 2006.173.05:51:51.16#ibcon#*mode == 0, iclass 22, count 0 2006.173.05:51:51.16#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.05:51:51.16#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.05:51:51.16#ibcon#*before write, iclass 22, count 0 2006.173.05:51:51.16#ibcon#enter sib2, iclass 22, count 0 2006.173.05:51:51.16#ibcon#flushed, iclass 22, count 0 2006.173.05:51:51.16#ibcon#about to write, iclass 22, count 0 2006.173.05:51:51.16#ibcon#wrote, iclass 22, count 0 2006.173.05:51:51.16#ibcon#about to read 3, iclass 22, count 0 2006.173.05:51:51.20#ibcon#read 3, iclass 22, count 0 2006.173.05:51:51.20#ibcon#about to read 4, iclass 22, count 0 2006.173.05:51:51.20#ibcon#read 4, iclass 22, count 0 2006.173.05:51:51.20#ibcon#about to read 5, iclass 22, count 0 2006.173.05:51:51.20#ibcon#read 5, iclass 22, count 0 2006.173.05:51:51.20#ibcon#about to read 6, iclass 22, count 0 2006.173.05:51:51.20#ibcon#read 6, iclass 22, count 0 2006.173.05:51:51.20#ibcon#end of sib2, iclass 22, count 0 2006.173.05:51:51.20#ibcon#*after write, iclass 22, count 0 2006.173.05:51:51.20#ibcon#*before return 0, iclass 22, count 0 2006.173.05:51:51.20#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.05:51:51.20#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.05:51:51.20#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.05:51:51.20#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.05:51:51.20$vck44/vb=5,4 2006.173.05:51:51.20#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.05:51:51.20#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.05:51:51.20#ibcon#ireg 11 cls_cnt 2 2006.173.05:51:51.20#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.05:51:51.26#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.05:51:51.26#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.05:51:51.26#ibcon#enter wrdev, iclass 24, count 2 2006.173.05:51:51.26#ibcon#first serial, iclass 24, count 2 2006.173.05:51:51.26#ibcon#enter sib2, iclass 24, count 2 2006.173.05:51:51.26#ibcon#flushed, iclass 24, count 2 2006.173.05:51:51.26#ibcon#about to write, iclass 24, count 2 2006.173.05:51:51.26#ibcon#wrote, iclass 24, count 2 2006.173.05:51:51.26#ibcon#about to read 3, iclass 24, count 2 2006.173.05:51:51.28#ibcon#read 3, iclass 24, count 2 2006.173.05:51:51.28#ibcon#about to read 4, iclass 24, count 2 2006.173.05:51:51.28#ibcon#read 4, iclass 24, count 2 2006.173.05:51:51.28#ibcon#about to read 5, iclass 24, count 2 2006.173.05:51:51.28#ibcon#read 5, iclass 24, count 2 2006.173.05:51:51.28#ibcon#about to read 6, iclass 24, count 2 2006.173.05:51:51.28#ibcon#read 6, iclass 24, count 2 2006.173.05:51:51.28#ibcon#end of sib2, iclass 24, count 2 2006.173.05:51:51.28#ibcon#*mode == 0, iclass 24, count 2 2006.173.05:51:51.28#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.05:51:51.28#ibcon#[27=AT05-04\r\n] 2006.173.05:51:51.28#ibcon#*before write, iclass 24, count 2 2006.173.05:51:51.28#ibcon#enter sib2, iclass 24, count 2 2006.173.05:51:51.28#ibcon#flushed, iclass 24, count 2 2006.173.05:51:51.28#ibcon#about to write, iclass 24, count 2 2006.173.05:51:51.28#ibcon#wrote, iclass 24, count 2 2006.173.05:51:51.28#ibcon#about to read 3, iclass 24, count 2 2006.173.05:51:51.31#ibcon#read 3, iclass 24, count 2 2006.173.05:51:51.31#ibcon#about to read 4, iclass 24, count 2 2006.173.05:51:51.31#ibcon#read 4, iclass 24, count 2 2006.173.05:51:51.31#ibcon#about to read 5, iclass 24, count 2 2006.173.05:51:51.31#ibcon#read 5, iclass 24, count 2 2006.173.05:51:51.31#ibcon#about to read 6, iclass 24, count 2 2006.173.05:51:51.31#ibcon#read 6, iclass 24, count 2 2006.173.05:51:51.31#ibcon#end of sib2, iclass 24, count 2 2006.173.05:51:51.31#ibcon#*after write, iclass 24, count 2 2006.173.05:51:51.31#ibcon#*before return 0, iclass 24, count 2 2006.173.05:51:51.31#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.05:51:51.31#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.05:51:51.31#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.05:51:51.31#ibcon#ireg 7 cls_cnt 0 2006.173.05:51:51.31#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.05:51:51.43#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.05:51:51.43#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.05:51:51.43#ibcon#enter wrdev, iclass 24, count 0 2006.173.05:51:51.43#ibcon#first serial, iclass 24, count 0 2006.173.05:51:51.43#ibcon#enter sib2, iclass 24, count 0 2006.173.05:51:51.43#ibcon#flushed, iclass 24, count 0 2006.173.05:51:51.43#ibcon#about to write, iclass 24, count 0 2006.173.05:51:51.43#ibcon#wrote, iclass 24, count 0 2006.173.05:51:51.43#ibcon#about to read 3, iclass 24, count 0 2006.173.05:51:51.45#ibcon#read 3, iclass 24, count 0 2006.173.05:51:51.45#ibcon#about to read 4, iclass 24, count 0 2006.173.05:51:51.45#ibcon#read 4, iclass 24, count 0 2006.173.05:51:51.45#ibcon#about to read 5, iclass 24, count 0 2006.173.05:51:51.45#ibcon#read 5, iclass 24, count 0 2006.173.05:51:51.45#ibcon#about to read 6, iclass 24, count 0 2006.173.05:51:51.45#ibcon#read 6, iclass 24, count 0 2006.173.05:51:51.45#ibcon#end of sib2, iclass 24, count 0 2006.173.05:51:51.45#ibcon#*mode == 0, iclass 24, count 0 2006.173.05:51:51.45#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.05:51:51.45#ibcon#[27=USB\r\n] 2006.173.05:51:51.45#ibcon#*before write, iclass 24, count 0 2006.173.05:51:51.45#ibcon#enter sib2, iclass 24, count 0 2006.173.05:51:51.45#ibcon#flushed, iclass 24, count 0 2006.173.05:51:51.45#ibcon#about to write, iclass 24, count 0 2006.173.05:51:51.45#ibcon#wrote, iclass 24, count 0 2006.173.05:51:51.45#ibcon#about to read 3, iclass 24, count 0 2006.173.05:51:51.48#ibcon#read 3, iclass 24, count 0 2006.173.05:51:51.48#ibcon#about to read 4, iclass 24, count 0 2006.173.05:51:51.48#ibcon#read 4, iclass 24, count 0 2006.173.05:51:51.48#ibcon#about to read 5, iclass 24, count 0 2006.173.05:51:51.48#ibcon#read 5, iclass 24, count 0 2006.173.05:51:51.48#ibcon#about to read 6, iclass 24, count 0 2006.173.05:51:51.48#ibcon#read 6, iclass 24, count 0 2006.173.05:51:51.48#ibcon#end of sib2, iclass 24, count 0 2006.173.05:51:51.48#ibcon#*after write, iclass 24, count 0 2006.173.05:51:51.48#ibcon#*before return 0, iclass 24, count 0 2006.173.05:51:51.48#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.05:51:51.48#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.05:51:51.48#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.05:51:51.48#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.05:51:51.48$vck44/vblo=6,719.99 2006.173.05:51:51.48#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.05:51:51.48#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.05:51:51.48#ibcon#ireg 17 cls_cnt 0 2006.173.05:51:51.48#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.05:51:51.48#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.05:51:51.48#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.05:51:51.48#ibcon#enter wrdev, iclass 26, count 0 2006.173.05:51:51.48#ibcon#first serial, iclass 26, count 0 2006.173.05:51:51.48#ibcon#enter sib2, iclass 26, count 0 2006.173.05:51:51.48#ibcon#flushed, iclass 26, count 0 2006.173.05:51:51.48#ibcon#about to write, iclass 26, count 0 2006.173.05:51:51.48#ibcon#wrote, iclass 26, count 0 2006.173.05:51:51.48#ibcon#about to read 3, iclass 26, count 0 2006.173.05:51:51.50#ibcon#read 3, iclass 26, count 0 2006.173.05:51:51.50#ibcon#about to read 4, iclass 26, count 0 2006.173.05:51:51.50#ibcon#read 4, iclass 26, count 0 2006.173.05:51:51.50#ibcon#about to read 5, iclass 26, count 0 2006.173.05:51:51.50#ibcon#read 5, iclass 26, count 0 2006.173.05:51:51.50#ibcon#about to read 6, iclass 26, count 0 2006.173.05:51:51.50#ibcon#read 6, iclass 26, count 0 2006.173.05:51:51.50#ibcon#end of sib2, iclass 26, count 0 2006.173.05:51:51.50#ibcon#*mode == 0, iclass 26, count 0 2006.173.05:51:51.50#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.05:51:51.50#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.05:51:51.50#ibcon#*before write, iclass 26, count 0 2006.173.05:51:51.50#ibcon#enter sib2, iclass 26, count 0 2006.173.05:51:51.50#ibcon#flushed, iclass 26, count 0 2006.173.05:51:51.50#ibcon#about to write, iclass 26, count 0 2006.173.05:51:51.50#ibcon#wrote, iclass 26, count 0 2006.173.05:51:51.50#ibcon#about to read 3, iclass 26, count 0 2006.173.05:51:51.54#ibcon#read 3, iclass 26, count 0 2006.173.05:51:51.54#ibcon#about to read 4, iclass 26, count 0 2006.173.05:51:51.54#ibcon#read 4, iclass 26, count 0 2006.173.05:51:51.54#ibcon#about to read 5, iclass 26, count 0 2006.173.05:51:51.54#ibcon#read 5, iclass 26, count 0 2006.173.05:51:51.54#ibcon#about to read 6, iclass 26, count 0 2006.173.05:51:51.54#ibcon#read 6, iclass 26, count 0 2006.173.05:51:51.54#ibcon#end of sib2, iclass 26, count 0 2006.173.05:51:51.54#ibcon#*after write, iclass 26, count 0 2006.173.05:51:51.54#ibcon#*before return 0, iclass 26, count 0 2006.173.05:51:51.54#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.05:51:51.54#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.05:51:51.54#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.05:51:51.54#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.05:51:51.54$vck44/vb=6,4 2006.173.05:51:51.54#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.05:51:51.54#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.05:51:51.54#ibcon#ireg 11 cls_cnt 2 2006.173.05:51:51.54#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.05:51:51.60#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.05:51:51.60#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.05:51:51.60#ibcon#enter wrdev, iclass 28, count 2 2006.173.05:51:51.60#ibcon#first serial, iclass 28, count 2 2006.173.05:51:51.60#ibcon#enter sib2, iclass 28, count 2 2006.173.05:51:51.60#ibcon#flushed, iclass 28, count 2 2006.173.05:51:51.60#ibcon#about to write, iclass 28, count 2 2006.173.05:51:51.60#ibcon#wrote, iclass 28, count 2 2006.173.05:51:51.60#ibcon#about to read 3, iclass 28, count 2 2006.173.05:51:51.62#ibcon#read 3, iclass 28, count 2 2006.173.05:51:51.62#ibcon#about to read 4, iclass 28, count 2 2006.173.05:51:51.62#ibcon#read 4, iclass 28, count 2 2006.173.05:51:51.62#ibcon#about to read 5, iclass 28, count 2 2006.173.05:51:51.62#ibcon#read 5, iclass 28, count 2 2006.173.05:51:51.62#ibcon#about to read 6, iclass 28, count 2 2006.173.05:51:51.62#ibcon#read 6, iclass 28, count 2 2006.173.05:51:51.62#ibcon#end of sib2, iclass 28, count 2 2006.173.05:51:51.62#ibcon#*mode == 0, iclass 28, count 2 2006.173.05:51:51.62#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.05:51:51.62#ibcon#[27=AT06-04\r\n] 2006.173.05:51:51.62#ibcon#*before write, iclass 28, count 2 2006.173.05:51:51.62#ibcon#enter sib2, iclass 28, count 2 2006.173.05:51:51.62#ibcon#flushed, iclass 28, count 2 2006.173.05:51:51.62#ibcon#about to write, iclass 28, count 2 2006.173.05:51:51.62#ibcon#wrote, iclass 28, count 2 2006.173.05:51:51.62#ibcon#about to read 3, iclass 28, count 2 2006.173.05:51:51.65#ibcon#read 3, iclass 28, count 2 2006.173.05:51:51.65#ibcon#about to read 4, iclass 28, count 2 2006.173.05:51:51.65#ibcon#read 4, iclass 28, count 2 2006.173.05:51:51.65#ibcon#about to read 5, iclass 28, count 2 2006.173.05:51:51.65#ibcon#read 5, iclass 28, count 2 2006.173.05:51:51.65#ibcon#about to read 6, iclass 28, count 2 2006.173.05:51:51.65#ibcon#read 6, iclass 28, count 2 2006.173.05:51:51.65#ibcon#end of sib2, iclass 28, count 2 2006.173.05:51:51.65#ibcon#*after write, iclass 28, count 2 2006.173.05:51:51.65#ibcon#*before return 0, iclass 28, count 2 2006.173.05:51:51.65#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.05:51:51.65#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.05:51:51.65#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.05:51:51.65#ibcon#ireg 7 cls_cnt 0 2006.173.05:51:51.65#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.05:51:51.77#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.05:51:51.77#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.05:51:51.77#ibcon#enter wrdev, iclass 28, count 0 2006.173.05:51:51.77#ibcon#first serial, iclass 28, count 0 2006.173.05:51:51.77#ibcon#enter sib2, iclass 28, count 0 2006.173.05:51:51.77#ibcon#flushed, iclass 28, count 0 2006.173.05:51:51.77#ibcon#about to write, iclass 28, count 0 2006.173.05:51:51.77#ibcon#wrote, iclass 28, count 0 2006.173.05:51:51.77#ibcon#about to read 3, iclass 28, count 0 2006.173.05:51:51.79#ibcon#read 3, iclass 28, count 0 2006.173.05:51:51.79#ibcon#about to read 4, iclass 28, count 0 2006.173.05:51:51.79#ibcon#read 4, iclass 28, count 0 2006.173.05:51:51.79#ibcon#about to read 5, iclass 28, count 0 2006.173.05:51:51.79#ibcon#read 5, iclass 28, count 0 2006.173.05:51:51.79#ibcon#about to read 6, iclass 28, count 0 2006.173.05:51:51.79#ibcon#read 6, iclass 28, count 0 2006.173.05:51:51.79#ibcon#end of sib2, iclass 28, count 0 2006.173.05:51:51.79#ibcon#*mode == 0, iclass 28, count 0 2006.173.05:51:51.79#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.05:51:51.79#ibcon#[27=USB\r\n] 2006.173.05:51:51.79#ibcon#*before write, iclass 28, count 0 2006.173.05:51:51.79#ibcon#enter sib2, iclass 28, count 0 2006.173.05:51:51.79#ibcon#flushed, iclass 28, count 0 2006.173.05:51:51.79#ibcon#about to write, iclass 28, count 0 2006.173.05:51:51.79#ibcon#wrote, iclass 28, count 0 2006.173.05:51:51.79#ibcon#about to read 3, iclass 28, count 0 2006.173.05:51:51.82#ibcon#read 3, iclass 28, count 0 2006.173.05:51:51.82#ibcon#about to read 4, iclass 28, count 0 2006.173.05:51:51.82#ibcon#read 4, iclass 28, count 0 2006.173.05:51:51.82#ibcon#about to read 5, iclass 28, count 0 2006.173.05:51:51.82#ibcon#read 5, iclass 28, count 0 2006.173.05:51:51.82#ibcon#about to read 6, iclass 28, count 0 2006.173.05:51:51.82#ibcon#read 6, iclass 28, count 0 2006.173.05:51:51.82#ibcon#end of sib2, iclass 28, count 0 2006.173.05:51:51.82#ibcon#*after write, iclass 28, count 0 2006.173.05:51:51.82#ibcon#*before return 0, iclass 28, count 0 2006.173.05:51:51.82#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.05:51:51.82#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.05:51:51.82#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.05:51:51.82#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.05:51:51.82$vck44/vblo=7,734.99 2006.173.05:51:51.82#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.05:51:51.82#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.05:51:51.82#ibcon#ireg 17 cls_cnt 0 2006.173.05:51:51.82#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.05:51:51.82#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.05:51:51.82#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.05:51:51.82#ibcon#enter wrdev, iclass 30, count 0 2006.173.05:51:51.82#ibcon#first serial, iclass 30, count 0 2006.173.05:51:51.82#ibcon#enter sib2, iclass 30, count 0 2006.173.05:51:51.82#ibcon#flushed, iclass 30, count 0 2006.173.05:51:51.82#ibcon#about to write, iclass 30, count 0 2006.173.05:51:51.82#ibcon#wrote, iclass 30, count 0 2006.173.05:51:51.82#ibcon#about to read 3, iclass 30, count 0 2006.173.05:51:51.84#ibcon#read 3, iclass 30, count 0 2006.173.05:51:51.84#ibcon#about to read 4, iclass 30, count 0 2006.173.05:51:51.84#ibcon#read 4, iclass 30, count 0 2006.173.05:51:51.84#ibcon#about to read 5, iclass 30, count 0 2006.173.05:51:51.84#ibcon#read 5, iclass 30, count 0 2006.173.05:51:51.84#ibcon#about to read 6, iclass 30, count 0 2006.173.05:51:51.84#ibcon#read 6, iclass 30, count 0 2006.173.05:51:51.84#ibcon#end of sib2, iclass 30, count 0 2006.173.05:51:51.84#ibcon#*mode == 0, iclass 30, count 0 2006.173.05:51:51.84#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.05:51:51.84#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.05:51:51.84#ibcon#*before write, iclass 30, count 0 2006.173.05:51:51.84#ibcon#enter sib2, iclass 30, count 0 2006.173.05:51:51.84#ibcon#flushed, iclass 30, count 0 2006.173.05:51:51.84#ibcon#about to write, iclass 30, count 0 2006.173.05:51:51.84#ibcon#wrote, iclass 30, count 0 2006.173.05:51:51.84#ibcon#about to read 3, iclass 30, count 0 2006.173.05:51:51.88#ibcon#read 3, iclass 30, count 0 2006.173.05:51:51.88#ibcon#about to read 4, iclass 30, count 0 2006.173.05:51:51.88#ibcon#read 4, iclass 30, count 0 2006.173.05:51:51.88#ibcon#about to read 5, iclass 30, count 0 2006.173.05:51:51.88#ibcon#read 5, iclass 30, count 0 2006.173.05:51:51.88#ibcon#about to read 6, iclass 30, count 0 2006.173.05:51:51.88#ibcon#read 6, iclass 30, count 0 2006.173.05:51:51.88#ibcon#end of sib2, iclass 30, count 0 2006.173.05:51:51.88#ibcon#*after write, iclass 30, count 0 2006.173.05:51:51.88#ibcon#*before return 0, iclass 30, count 0 2006.173.05:51:51.88#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.05:51:51.88#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.05:51:51.88#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.05:51:51.88#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.05:51:51.88$vck44/vb=7,4 2006.173.05:51:51.88#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.173.05:51:51.88#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.173.05:51:51.88#ibcon#ireg 11 cls_cnt 2 2006.173.05:51:51.88#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.05:51:51.94#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.05:51:51.94#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.05:51:51.94#ibcon#enter wrdev, iclass 32, count 2 2006.173.05:51:51.94#ibcon#first serial, iclass 32, count 2 2006.173.05:51:51.94#ibcon#enter sib2, iclass 32, count 2 2006.173.05:51:51.94#ibcon#flushed, iclass 32, count 2 2006.173.05:51:51.94#ibcon#about to write, iclass 32, count 2 2006.173.05:51:51.94#ibcon#wrote, iclass 32, count 2 2006.173.05:51:51.94#ibcon#about to read 3, iclass 32, count 2 2006.173.05:51:51.96#ibcon#read 3, iclass 32, count 2 2006.173.05:51:51.96#ibcon#about to read 4, iclass 32, count 2 2006.173.05:51:51.96#ibcon#read 4, iclass 32, count 2 2006.173.05:51:51.96#ibcon#about to read 5, iclass 32, count 2 2006.173.05:51:51.96#ibcon#read 5, iclass 32, count 2 2006.173.05:51:51.96#ibcon#about to read 6, iclass 32, count 2 2006.173.05:51:51.96#ibcon#read 6, iclass 32, count 2 2006.173.05:51:51.96#ibcon#end of sib2, iclass 32, count 2 2006.173.05:51:51.96#ibcon#*mode == 0, iclass 32, count 2 2006.173.05:51:51.96#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.173.05:51:51.96#ibcon#[27=AT07-04\r\n] 2006.173.05:51:51.96#ibcon#*before write, iclass 32, count 2 2006.173.05:51:51.96#ibcon#enter sib2, iclass 32, count 2 2006.173.05:51:51.96#ibcon#flushed, iclass 32, count 2 2006.173.05:51:51.96#ibcon#about to write, iclass 32, count 2 2006.173.05:51:51.96#ibcon#wrote, iclass 32, count 2 2006.173.05:51:51.96#ibcon#about to read 3, iclass 32, count 2 2006.173.05:51:51.99#ibcon#read 3, iclass 32, count 2 2006.173.05:51:51.99#ibcon#about to read 4, iclass 32, count 2 2006.173.05:51:51.99#ibcon#read 4, iclass 32, count 2 2006.173.05:51:51.99#ibcon#about to read 5, iclass 32, count 2 2006.173.05:51:51.99#ibcon#read 5, iclass 32, count 2 2006.173.05:51:51.99#ibcon#about to read 6, iclass 32, count 2 2006.173.05:51:51.99#ibcon#read 6, iclass 32, count 2 2006.173.05:51:51.99#ibcon#end of sib2, iclass 32, count 2 2006.173.05:51:51.99#ibcon#*after write, iclass 32, count 2 2006.173.05:51:51.99#ibcon#*before return 0, iclass 32, count 2 2006.173.05:51:51.99#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.05:51:51.99#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.173.05:51:51.99#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.173.05:51:51.99#ibcon#ireg 7 cls_cnt 0 2006.173.05:51:51.99#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.05:51:52.11#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.05:51:52.11#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.05:51:52.11#ibcon#enter wrdev, iclass 32, count 0 2006.173.05:51:52.11#ibcon#first serial, iclass 32, count 0 2006.173.05:51:52.11#ibcon#enter sib2, iclass 32, count 0 2006.173.05:51:52.11#ibcon#flushed, iclass 32, count 0 2006.173.05:51:52.11#ibcon#about to write, iclass 32, count 0 2006.173.05:51:52.11#ibcon#wrote, iclass 32, count 0 2006.173.05:51:52.11#ibcon#about to read 3, iclass 32, count 0 2006.173.05:51:52.13#ibcon#read 3, iclass 32, count 0 2006.173.05:51:52.13#ibcon#about to read 4, iclass 32, count 0 2006.173.05:51:52.13#ibcon#read 4, iclass 32, count 0 2006.173.05:51:52.13#ibcon#about to read 5, iclass 32, count 0 2006.173.05:51:52.13#ibcon#read 5, iclass 32, count 0 2006.173.05:51:52.13#ibcon#about to read 6, iclass 32, count 0 2006.173.05:51:52.13#ibcon#read 6, iclass 32, count 0 2006.173.05:51:52.13#ibcon#end of sib2, iclass 32, count 0 2006.173.05:51:52.13#ibcon#*mode == 0, iclass 32, count 0 2006.173.05:51:52.13#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.05:51:52.13#ibcon#[27=USB\r\n] 2006.173.05:51:52.13#ibcon#*before write, iclass 32, count 0 2006.173.05:51:52.13#ibcon#enter sib2, iclass 32, count 0 2006.173.05:51:52.13#ibcon#flushed, iclass 32, count 0 2006.173.05:51:52.13#ibcon#about to write, iclass 32, count 0 2006.173.05:51:52.13#ibcon#wrote, iclass 32, count 0 2006.173.05:51:52.13#ibcon#about to read 3, iclass 32, count 0 2006.173.05:51:52.16#ibcon#read 3, iclass 32, count 0 2006.173.05:51:52.16#ibcon#about to read 4, iclass 32, count 0 2006.173.05:51:52.16#ibcon#read 4, iclass 32, count 0 2006.173.05:51:52.16#ibcon#about to read 5, iclass 32, count 0 2006.173.05:51:52.16#ibcon#read 5, iclass 32, count 0 2006.173.05:51:52.16#ibcon#about to read 6, iclass 32, count 0 2006.173.05:51:52.16#ibcon#read 6, iclass 32, count 0 2006.173.05:51:52.16#ibcon#end of sib2, iclass 32, count 0 2006.173.05:51:52.16#ibcon#*after write, iclass 32, count 0 2006.173.05:51:52.16#ibcon#*before return 0, iclass 32, count 0 2006.173.05:51:52.16#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.05:51:52.16#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.173.05:51:52.16#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.05:51:52.16#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.05:51:52.16$vck44/vblo=8,744.99 2006.173.05:51:52.16#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.05:51:52.16#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.05:51:52.16#ibcon#ireg 17 cls_cnt 0 2006.173.05:51:52.16#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.05:51:52.16#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.05:51:52.16#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.05:51:52.16#ibcon#enter wrdev, iclass 34, count 0 2006.173.05:51:52.16#ibcon#first serial, iclass 34, count 0 2006.173.05:51:52.16#ibcon#enter sib2, iclass 34, count 0 2006.173.05:51:52.16#ibcon#flushed, iclass 34, count 0 2006.173.05:51:52.16#ibcon#about to write, iclass 34, count 0 2006.173.05:51:52.16#ibcon#wrote, iclass 34, count 0 2006.173.05:51:52.16#ibcon#about to read 3, iclass 34, count 0 2006.173.05:51:52.18#ibcon#read 3, iclass 34, count 0 2006.173.05:51:52.18#ibcon#about to read 4, iclass 34, count 0 2006.173.05:51:52.18#ibcon#read 4, iclass 34, count 0 2006.173.05:51:52.18#ibcon#about to read 5, iclass 34, count 0 2006.173.05:51:52.18#ibcon#read 5, iclass 34, count 0 2006.173.05:51:52.18#ibcon#about to read 6, iclass 34, count 0 2006.173.05:51:52.18#ibcon#read 6, iclass 34, count 0 2006.173.05:51:52.18#ibcon#end of sib2, iclass 34, count 0 2006.173.05:51:52.18#ibcon#*mode == 0, iclass 34, count 0 2006.173.05:51:52.18#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.05:51:52.18#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.05:51:52.18#ibcon#*before write, iclass 34, count 0 2006.173.05:51:52.18#ibcon#enter sib2, iclass 34, count 0 2006.173.05:51:52.18#ibcon#flushed, iclass 34, count 0 2006.173.05:51:52.18#ibcon#about to write, iclass 34, count 0 2006.173.05:51:52.18#ibcon#wrote, iclass 34, count 0 2006.173.05:51:52.18#ibcon#about to read 3, iclass 34, count 0 2006.173.05:51:52.22#ibcon#read 3, iclass 34, count 0 2006.173.05:51:52.22#ibcon#about to read 4, iclass 34, count 0 2006.173.05:51:52.22#ibcon#read 4, iclass 34, count 0 2006.173.05:51:52.22#ibcon#about to read 5, iclass 34, count 0 2006.173.05:51:52.22#ibcon#read 5, iclass 34, count 0 2006.173.05:51:52.22#ibcon#about to read 6, iclass 34, count 0 2006.173.05:51:52.22#ibcon#read 6, iclass 34, count 0 2006.173.05:51:52.22#ibcon#end of sib2, iclass 34, count 0 2006.173.05:51:52.22#ibcon#*after write, iclass 34, count 0 2006.173.05:51:52.22#ibcon#*before return 0, iclass 34, count 0 2006.173.05:51:52.22#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.05:51:52.22#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.05:51:52.22#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.05:51:52.22#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.05:51:52.22$vck44/vb=8,4 2006.173.05:51:52.22#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.05:51:52.22#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.05:51:52.22#ibcon#ireg 11 cls_cnt 2 2006.173.05:51:52.22#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.05:51:52.28#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.05:51:52.28#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.05:51:52.28#ibcon#enter wrdev, iclass 36, count 2 2006.173.05:51:52.28#ibcon#first serial, iclass 36, count 2 2006.173.05:51:52.28#ibcon#enter sib2, iclass 36, count 2 2006.173.05:51:52.28#ibcon#flushed, iclass 36, count 2 2006.173.05:51:52.28#ibcon#about to write, iclass 36, count 2 2006.173.05:51:52.28#ibcon#wrote, iclass 36, count 2 2006.173.05:51:52.28#ibcon#about to read 3, iclass 36, count 2 2006.173.05:51:52.30#ibcon#read 3, iclass 36, count 2 2006.173.05:51:52.30#ibcon#about to read 4, iclass 36, count 2 2006.173.05:51:52.30#ibcon#read 4, iclass 36, count 2 2006.173.05:51:52.30#ibcon#about to read 5, iclass 36, count 2 2006.173.05:51:52.30#ibcon#read 5, iclass 36, count 2 2006.173.05:51:52.30#ibcon#about to read 6, iclass 36, count 2 2006.173.05:51:52.30#ibcon#read 6, iclass 36, count 2 2006.173.05:51:52.30#ibcon#end of sib2, iclass 36, count 2 2006.173.05:51:52.30#ibcon#*mode == 0, iclass 36, count 2 2006.173.05:51:52.30#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.05:51:52.30#ibcon#[27=AT08-04\r\n] 2006.173.05:51:52.30#ibcon#*before write, iclass 36, count 2 2006.173.05:51:52.30#ibcon#enter sib2, iclass 36, count 2 2006.173.05:51:52.30#ibcon#flushed, iclass 36, count 2 2006.173.05:51:52.30#ibcon#about to write, iclass 36, count 2 2006.173.05:51:52.30#ibcon#wrote, iclass 36, count 2 2006.173.05:51:52.30#ibcon#about to read 3, iclass 36, count 2 2006.173.05:51:52.33#ibcon#read 3, iclass 36, count 2 2006.173.05:51:52.33#ibcon#about to read 4, iclass 36, count 2 2006.173.05:51:52.33#ibcon#read 4, iclass 36, count 2 2006.173.05:51:52.33#ibcon#about to read 5, iclass 36, count 2 2006.173.05:51:52.33#ibcon#read 5, iclass 36, count 2 2006.173.05:51:52.33#ibcon#about to read 6, iclass 36, count 2 2006.173.05:51:52.33#ibcon#read 6, iclass 36, count 2 2006.173.05:51:52.33#ibcon#end of sib2, iclass 36, count 2 2006.173.05:51:52.33#ibcon#*after write, iclass 36, count 2 2006.173.05:51:52.33#ibcon#*before return 0, iclass 36, count 2 2006.173.05:51:52.33#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.05:51:52.33#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.05:51:52.33#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.05:51:52.33#ibcon#ireg 7 cls_cnt 0 2006.173.05:51:52.33#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.05:51:52.45#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.05:51:52.45#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.05:51:52.45#ibcon#enter wrdev, iclass 36, count 0 2006.173.05:51:52.45#ibcon#first serial, iclass 36, count 0 2006.173.05:51:52.45#ibcon#enter sib2, iclass 36, count 0 2006.173.05:51:52.45#ibcon#flushed, iclass 36, count 0 2006.173.05:51:52.45#ibcon#about to write, iclass 36, count 0 2006.173.05:51:52.45#ibcon#wrote, iclass 36, count 0 2006.173.05:51:52.45#ibcon#about to read 3, iclass 36, count 0 2006.173.05:51:52.47#ibcon#read 3, iclass 36, count 0 2006.173.05:51:52.47#ibcon#about to read 4, iclass 36, count 0 2006.173.05:51:52.47#ibcon#read 4, iclass 36, count 0 2006.173.05:51:52.47#ibcon#about to read 5, iclass 36, count 0 2006.173.05:51:52.47#ibcon#read 5, iclass 36, count 0 2006.173.05:51:52.47#ibcon#about to read 6, iclass 36, count 0 2006.173.05:51:52.47#ibcon#read 6, iclass 36, count 0 2006.173.05:51:52.47#ibcon#end of sib2, iclass 36, count 0 2006.173.05:51:52.47#ibcon#*mode == 0, iclass 36, count 0 2006.173.05:51:52.47#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.05:51:52.47#ibcon#[27=USB\r\n] 2006.173.05:51:52.47#ibcon#*before write, iclass 36, count 0 2006.173.05:51:52.47#ibcon#enter sib2, iclass 36, count 0 2006.173.05:51:52.47#ibcon#flushed, iclass 36, count 0 2006.173.05:51:52.47#ibcon#about to write, iclass 36, count 0 2006.173.05:51:52.47#ibcon#wrote, iclass 36, count 0 2006.173.05:51:52.47#ibcon#about to read 3, iclass 36, count 0 2006.173.05:51:52.50#ibcon#read 3, iclass 36, count 0 2006.173.05:51:52.50#ibcon#about to read 4, iclass 36, count 0 2006.173.05:51:52.50#ibcon#read 4, iclass 36, count 0 2006.173.05:51:52.50#ibcon#about to read 5, iclass 36, count 0 2006.173.05:51:52.50#ibcon#read 5, iclass 36, count 0 2006.173.05:51:52.50#ibcon#about to read 6, iclass 36, count 0 2006.173.05:51:52.50#ibcon#read 6, iclass 36, count 0 2006.173.05:51:52.50#ibcon#end of sib2, iclass 36, count 0 2006.173.05:51:52.50#ibcon#*after write, iclass 36, count 0 2006.173.05:51:52.50#ibcon#*before return 0, iclass 36, count 0 2006.173.05:51:52.50#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.05:51:52.50#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.05:51:52.50#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.05:51:52.50#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.05:51:52.50$vck44/vabw=wide 2006.173.05:51:52.50#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.05:51:52.50#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.05:51:52.50#ibcon#ireg 8 cls_cnt 0 2006.173.05:51:52.50#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.05:51:52.50#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.05:51:52.50#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.05:51:52.50#ibcon#enter wrdev, iclass 38, count 0 2006.173.05:51:52.50#ibcon#first serial, iclass 38, count 0 2006.173.05:51:52.50#ibcon#enter sib2, iclass 38, count 0 2006.173.05:51:52.50#ibcon#flushed, iclass 38, count 0 2006.173.05:51:52.50#ibcon#about to write, iclass 38, count 0 2006.173.05:51:52.50#ibcon#wrote, iclass 38, count 0 2006.173.05:51:52.50#ibcon#about to read 3, iclass 38, count 0 2006.173.05:51:52.52#ibcon#read 3, iclass 38, count 0 2006.173.05:51:52.52#ibcon#about to read 4, iclass 38, count 0 2006.173.05:51:52.52#ibcon#read 4, iclass 38, count 0 2006.173.05:51:52.52#ibcon#about to read 5, iclass 38, count 0 2006.173.05:51:52.52#ibcon#read 5, iclass 38, count 0 2006.173.05:51:52.52#ibcon#about to read 6, iclass 38, count 0 2006.173.05:51:52.52#ibcon#read 6, iclass 38, count 0 2006.173.05:51:52.52#ibcon#end of sib2, iclass 38, count 0 2006.173.05:51:52.52#ibcon#*mode == 0, iclass 38, count 0 2006.173.05:51:52.52#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.05:51:52.52#ibcon#[25=BW32\r\n] 2006.173.05:51:52.52#ibcon#*before write, iclass 38, count 0 2006.173.05:51:52.52#ibcon#enter sib2, iclass 38, count 0 2006.173.05:51:52.52#ibcon#flushed, iclass 38, count 0 2006.173.05:51:52.52#ibcon#about to write, iclass 38, count 0 2006.173.05:51:52.52#ibcon#wrote, iclass 38, count 0 2006.173.05:51:52.52#ibcon#about to read 3, iclass 38, count 0 2006.173.05:51:52.55#ibcon#read 3, iclass 38, count 0 2006.173.05:51:52.55#ibcon#about to read 4, iclass 38, count 0 2006.173.05:51:52.55#ibcon#read 4, iclass 38, count 0 2006.173.05:51:52.55#ibcon#about to read 5, iclass 38, count 0 2006.173.05:51:52.55#ibcon#read 5, iclass 38, count 0 2006.173.05:51:52.55#ibcon#about to read 6, iclass 38, count 0 2006.173.05:51:52.55#ibcon#read 6, iclass 38, count 0 2006.173.05:51:52.55#ibcon#end of sib2, iclass 38, count 0 2006.173.05:51:52.55#ibcon#*after write, iclass 38, count 0 2006.173.05:51:52.55#ibcon#*before return 0, iclass 38, count 0 2006.173.05:51:52.55#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.05:51:52.55#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.05:51:52.55#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.05:51:52.55#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.05:51:52.55$vck44/vbbw=wide 2006.173.05:51:52.55#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.05:51:52.55#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.05:51:52.55#ibcon#ireg 8 cls_cnt 0 2006.173.05:51:52.55#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.05:51:52.62#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.05:51:52.62#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.05:51:52.62#ibcon#enter wrdev, iclass 40, count 0 2006.173.05:51:52.62#ibcon#first serial, iclass 40, count 0 2006.173.05:51:52.62#ibcon#enter sib2, iclass 40, count 0 2006.173.05:51:52.62#ibcon#flushed, iclass 40, count 0 2006.173.05:51:52.62#ibcon#about to write, iclass 40, count 0 2006.173.05:51:52.62#ibcon#wrote, iclass 40, count 0 2006.173.05:51:52.62#ibcon#about to read 3, iclass 40, count 0 2006.173.05:51:52.64#ibcon#read 3, iclass 40, count 0 2006.173.05:51:52.64#ibcon#about to read 4, iclass 40, count 0 2006.173.05:51:52.64#ibcon#read 4, iclass 40, count 0 2006.173.05:51:52.64#ibcon#about to read 5, iclass 40, count 0 2006.173.05:51:52.64#ibcon#read 5, iclass 40, count 0 2006.173.05:51:52.64#ibcon#about to read 6, iclass 40, count 0 2006.173.05:51:52.64#ibcon#read 6, iclass 40, count 0 2006.173.05:51:52.64#ibcon#end of sib2, iclass 40, count 0 2006.173.05:51:52.64#ibcon#*mode == 0, iclass 40, count 0 2006.173.05:51:52.64#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.05:51:52.64#ibcon#[27=BW32\r\n] 2006.173.05:51:52.64#ibcon#*before write, iclass 40, count 0 2006.173.05:51:52.64#ibcon#enter sib2, iclass 40, count 0 2006.173.05:51:52.64#ibcon#flushed, iclass 40, count 0 2006.173.05:51:52.64#ibcon#about to write, iclass 40, count 0 2006.173.05:51:52.64#ibcon#wrote, iclass 40, count 0 2006.173.05:51:52.64#ibcon#about to read 3, iclass 40, count 0 2006.173.05:51:52.67#ibcon#read 3, iclass 40, count 0 2006.173.05:51:52.67#ibcon#about to read 4, iclass 40, count 0 2006.173.05:51:52.67#ibcon#read 4, iclass 40, count 0 2006.173.05:51:52.67#ibcon#about to read 5, iclass 40, count 0 2006.173.05:51:52.67#ibcon#read 5, iclass 40, count 0 2006.173.05:51:52.67#ibcon#about to read 6, iclass 40, count 0 2006.173.05:51:52.67#ibcon#read 6, iclass 40, count 0 2006.173.05:51:52.67#ibcon#end of sib2, iclass 40, count 0 2006.173.05:51:52.67#ibcon#*after write, iclass 40, count 0 2006.173.05:51:52.67#ibcon#*before return 0, iclass 40, count 0 2006.173.05:51:52.67#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.05:51:52.67#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.05:51:52.67#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.05:51:52.67#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.05:51:52.67$setupk4/ifdk4 2006.173.05:51:52.67$ifdk4/lo= 2006.173.05:51:52.67$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.05:51:52.67$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.05:51:52.67$ifdk4/patch= 2006.173.05:51:52.67$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.05:51:52.67$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.05:51:52.67$setupk4/!*+20s 2006.173.05:51:59.19#abcon#<5=/15 0.6 1.3 23.65 771005.3\r\n> 2006.173.05:51:59.21#abcon#{5=INTERFACE CLEAR} 2006.173.05:51:59.27#abcon#[5=S1D000X0/0*\r\n] 2006.173.05:52:07.17$setupk4/"tpicd 2006.173.05:52:07.17$setupk4/echo=off 2006.173.05:52:07.17$setupk4/xlog=off 2006.173.05:52:07.17:!2006.173.05:53:36 2006.173.05:52:24.14#trakl#Source acquired 2006.173.05:52:25.14#flagr#flagr/antenna,acquired 2006.173.05:53:36.00:preob 2006.173.05:53:36.14/onsource/TRACKING 2006.173.05:53:36.14:!2006.173.05:53:46 2006.173.05:53:46.00:"tape 2006.173.05:53:46.00:"st=record 2006.173.05:53:46.00:data_valid=on 2006.173.05:53:46.00:midob 2006.173.05:53:46.14/onsource/TRACKING 2006.173.05:53:46.14/wx/23.65,1005.4,76 2006.173.05:53:46.25/cable/+6.5028E-03 2006.173.05:53:47.34/va/01,07,usb,yes,38,41 2006.173.05:53:47.34/va/02,06,usb,yes,38,39 2006.173.05:53:47.34/va/03,05,usb,yes,48,50 2006.173.05:53:47.34/va/04,06,usb,yes,39,41 2006.173.05:53:47.34/va/05,04,usb,yes,30,31 2006.173.05:53:47.34/va/06,03,usb,yes,42,42 2006.173.05:53:47.34/va/07,04,usb,yes,34,36 2006.173.05:53:47.34/va/08,04,usb,yes,29,35 2006.173.05:53:47.57/valo/01,524.99,yes,locked 2006.173.05:53:47.57/valo/02,534.99,yes,locked 2006.173.05:53:47.57/valo/03,564.99,yes,locked 2006.173.05:53:47.57/valo/04,624.99,yes,locked 2006.173.05:53:47.57/valo/05,734.99,yes,locked 2006.173.05:53:47.57/valo/06,814.99,yes,locked 2006.173.05:53:47.57/valo/07,864.99,yes,locked 2006.173.05:53:47.57/valo/08,884.99,yes,locked 2006.173.05:53:48.66/vb/01,04,usb,yes,36,33 2006.173.05:53:48.66/vb/02,04,usb,yes,38,38 2006.173.05:53:48.66/vb/03,04,usb,yes,35,38 2006.173.05:53:48.66/vb/04,04,usb,yes,39,38 2006.173.05:53:48.66/vb/05,04,usb,yes,31,34 2006.173.05:53:48.66/vb/06,04,usb,yes,36,32 2006.173.05:53:48.66/vb/07,04,usb,yes,35,35 2006.173.05:53:48.66/vb/08,04,usb,yes,32,36 2006.173.05:53:48.89/vblo/01,629.99,yes,locked 2006.173.05:53:48.89/vblo/02,634.99,yes,locked 2006.173.05:53:48.89/vblo/03,649.99,yes,locked 2006.173.05:53:48.89/vblo/04,679.99,yes,locked 2006.173.05:53:48.89/vblo/05,709.99,yes,locked 2006.173.05:53:48.89/vblo/06,719.99,yes,locked 2006.173.05:53:48.89/vblo/07,734.99,yes,locked 2006.173.05:53:48.89/vblo/08,744.99,yes,locked 2006.173.05:53:49.04/vabw/8 2006.173.05:53:49.19/vbbw/8 2006.173.05:53:49.28/xfe/off,on,15.0 2006.173.05:53:49.65/ifatt/23,28,28,28 2006.173.05:53:50.08/fmout-gps/S +4.02E-07 2006.173.05:53:50.12:!2006.173.05:55:16 2006.173.05:55:16.00:data_valid=off 2006.173.05:55:16.00:"et 2006.173.05:55:16.00:!+3s 2006.173.05:55:19.02:"tape 2006.173.05:55:19.02:postob 2006.173.05:55:19.13/cable/+6.5041E-03 2006.173.05:55:19.13/wx/23.66,1005.3,76 2006.173.05:55:20.08/fmout-gps/S +4.03E-07 2006.173.05:55:20.08:scan_name=173-0559,jd0606,40 2006.173.05:55:20.08:source=1334-127,133739.78,-125724.7,2000.0,ccw 2006.173.05:55:20.13#flagr#flagr/antenna,new-source 2006.173.05:55:21.13:checkk5 2006.173.05:55:21.53/chk_autoobs//k5ts1/ autoobs is running! 2006.173.05:55:21.93/chk_autoobs//k5ts2/ autoobs is running! 2006.173.05:55:22.33/chk_autoobs//k5ts3/ autoobs is running! 2006.173.05:55:22.71/chk_autoobs//k5ts4/ autoobs is running! 2006.173.05:55:23.10/chk_obsdata//k5ts1/T1730553??a.dat file size is correct (nominal:360MB, actual:356MB). 2006.173.05:55:23.51/chk_obsdata//k5ts2/T1730553??b.dat file size is correct (nominal:360MB, actual:356MB). 2006.173.05:55:23.93/chk_obsdata//k5ts3/T1730553??c.dat file size is correct (nominal:360MB, actual:356MB). 2006.173.05:55:24.33/chk_obsdata//k5ts4/T1730553??d.dat file size is correct (nominal:360MB, actual:356MB). 2006.173.05:55:25.06/k5log//k5ts1_log_newline 2006.173.05:55:25.77/k5log//k5ts2_log_newline 2006.173.05:55:26.47/k5log//k5ts3_log_newline 2006.173.05:55:27.18/k5log//k5ts4_log_newline 2006.173.05:55:27.20/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.05:55:27.20:setupk4=1 2006.173.05:55:27.21$setupk4/echo=on 2006.173.05:55:27.21$setupk4/pcalon 2006.173.05:55:27.21$pcalon/"no phase cal control is implemented here 2006.173.05:55:27.21$setupk4/"tpicd=stop 2006.173.05:55:27.21$setupk4/"rec=synch_on 2006.173.05:55:27.21$setupk4/"rec_mode=128 2006.173.05:55:27.21$setupk4/!* 2006.173.05:55:27.21$setupk4/recpk4 2006.173.05:55:27.21$recpk4/recpatch= 2006.173.05:55:27.21$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.05:55:27.21$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.05:55:27.21$setupk4/vck44 2006.173.05:55:27.21$vck44/valo=1,524.99 2006.173.05:55:27.21#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.05:55:27.21#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.05:55:27.21#ibcon#ireg 17 cls_cnt 0 2006.173.05:55:27.21#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.05:55:27.21#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.05:55:27.21#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.05:55:27.21#ibcon#enter wrdev, iclass 21, count 0 2006.173.05:55:27.21#ibcon#first serial, iclass 21, count 0 2006.173.05:55:27.21#ibcon#enter sib2, iclass 21, count 0 2006.173.05:55:27.21#ibcon#flushed, iclass 21, count 0 2006.173.05:55:27.21#ibcon#about to write, iclass 21, count 0 2006.173.05:55:27.21#ibcon#wrote, iclass 21, count 0 2006.173.05:55:27.21#ibcon#about to read 3, iclass 21, count 0 2006.173.05:55:27.23#ibcon#read 3, iclass 21, count 0 2006.173.05:55:27.23#ibcon#about to read 4, iclass 21, count 0 2006.173.05:55:27.24#ibcon#read 4, iclass 21, count 0 2006.173.05:55:27.24#ibcon#about to read 5, iclass 21, count 0 2006.173.05:55:27.24#ibcon#read 5, iclass 21, count 0 2006.173.05:55:27.24#ibcon#about to read 6, iclass 21, count 0 2006.173.05:55:27.24#ibcon#read 6, iclass 21, count 0 2006.173.05:55:27.24#ibcon#end of sib2, iclass 21, count 0 2006.173.05:55:27.24#ibcon#*mode == 0, iclass 21, count 0 2006.173.05:55:27.24#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.05:55:27.24#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.05:55:27.24#ibcon#*before write, iclass 21, count 0 2006.173.05:55:27.24#ibcon#enter sib2, iclass 21, count 0 2006.173.05:55:27.24#ibcon#flushed, iclass 21, count 0 2006.173.05:55:27.24#ibcon#about to write, iclass 21, count 0 2006.173.05:55:27.24#ibcon#wrote, iclass 21, count 0 2006.173.05:55:27.24#ibcon#about to read 3, iclass 21, count 0 2006.173.05:55:27.28#ibcon#read 3, iclass 21, count 0 2006.173.05:55:27.28#ibcon#about to read 4, iclass 21, count 0 2006.173.05:55:27.28#ibcon#read 4, iclass 21, count 0 2006.173.05:55:27.28#ibcon#about to read 5, iclass 21, count 0 2006.173.05:55:27.29#ibcon#read 5, iclass 21, count 0 2006.173.05:55:27.29#ibcon#about to read 6, iclass 21, count 0 2006.173.05:55:27.29#ibcon#read 6, iclass 21, count 0 2006.173.05:55:27.29#ibcon#end of sib2, iclass 21, count 0 2006.173.05:55:27.29#ibcon#*after write, iclass 21, count 0 2006.173.05:55:27.29#ibcon#*before return 0, iclass 21, count 0 2006.173.05:55:27.29#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.05:55:27.29#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.05:55:27.29#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.05:55:27.29#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.05:55:27.29$vck44/va=1,7 2006.173.05:55:27.29#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.05:55:27.29#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.05:55:27.29#ibcon#ireg 11 cls_cnt 2 2006.173.05:55:27.29#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.05:55:27.29#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.05:55:27.29#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.05:55:27.29#ibcon#enter wrdev, iclass 23, count 2 2006.173.05:55:27.29#ibcon#first serial, iclass 23, count 2 2006.173.05:55:27.29#ibcon#enter sib2, iclass 23, count 2 2006.173.05:55:27.29#ibcon#flushed, iclass 23, count 2 2006.173.05:55:27.29#ibcon#about to write, iclass 23, count 2 2006.173.05:55:27.29#ibcon#wrote, iclass 23, count 2 2006.173.05:55:27.29#ibcon#about to read 3, iclass 23, count 2 2006.173.05:55:27.30#ibcon#read 3, iclass 23, count 2 2006.173.05:55:27.31#ibcon#about to read 4, iclass 23, count 2 2006.173.05:55:27.31#ibcon#read 4, iclass 23, count 2 2006.173.05:55:27.31#ibcon#about to read 5, iclass 23, count 2 2006.173.05:55:27.31#ibcon#read 5, iclass 23, count 2 2006.173.05:55:27.31#ibcon#about to read 6, iclass 23, count 2 2006.173.05:55:27.31#ibcon#read 6, iclass 23, count 2 2006.173.05:55:27.31#ibcon#end of sib2, iclass 23, count 2 2006.173.05:55:27.31#ibcon#*mode == 0, iclass 23, count 2 2006.173.05:55:27.31#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.05:55:27.31#ibcon#[25=AT01-07\r\n] 2006.173.05:55:27.31#ibcon#*before write, iclass 23, count 2 2006.173.05:55:27.31#ibcon#enter sib2, iclass 23, count 2 2006.173.05:55:27.31#ibcon#flushed, iclass 23, count 2 2006.173.05:55:27.31#ibcon#about to write, iclass 23, count 2 2006.173.05:55:27.31#ibcon#wrote, iclass 23, count 2 2006.173.05:55:27.31#ibcon#about to read 3, iclass 23, count 2 2006.173.05:55:27.33#ibcon#read 3, iclass 23, count 2 2006.173.05:55:27.33#ibcon#about to read 4, iclass 23, count 2 2006.173.05:55:27.33#ibcon#read 4, iclass 23, count 2 2006.173.05:55:27.33#ibcon#about to read 5, iclass 23, count 2 2006.173.05:55:27.34#ibcon#read 5, iclass 23, count 2 2006.173.05:55:27.34#ibcon#about to read 6, iclass 23, count 2 2006.173.05:55:27.34#ibcon#read 6, iclass 23, count 2 2006.173.05:55:27.34#ibcon#end of sib2, iclass 23, count 2 2006.173.05:55:27.34#ibcon#*after write, iclass 23, count 2 2006.173.05:55:27.34#ibcon#*before return 0, iclass 23, count 2 2006.173.05:55:27.34#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.05:55:27.34#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.05:55:27.34#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.05:55:27.34#ibcon#ireg 7 cls_cnt 0 2006.173.05:55:27.34#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.05:55:27.45#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.05:55:27.45#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.05:55:27.45#ibcon#enter wrdev, iclass 23, count 0 2006.173.05:55:27.45#ibcon#first serial, iclass 23, count 0 2006.173.05:55:27.46#ibcon#enter sib2, iclass 23, count 0 2006.173.05:55:27.46#ibcon#flushed, iclass 23, count 0 2006.173.05:55:27.46#ibcon#about to write, iclass 23, count 0 2006.173.05:55:27.46#ibcon#wrote, iclass 23, count 0 2006.173.05:55:27.46#ibcon#about to read 3, iclass 23, count 0 2006.173.05:55:27.47#ibcon#read 3, iclass 23, count 0 2006.173.05:55:27.47#ibcon#about to read 4, iclass 23, count 0 2006.173.05:55:27.48#ibcon#read 4, iclass 23, count 0 2006.173.05:55:27.48#ibcon#about to read 5, iclass 23, count 0 2006.173.05:55:27.48#ibcon#read 5, iclass 23, count 0 2006.173.05:55:27.48#ibcon#about to read 6, iclass 23, count 0 2006.173.05:55:27.48#ibcon#read 6, iclass 23, count 0 2006.173.05:55:27.48#ibcon#end of sib2, iclass 23, count 0 2006.173.05:55:27.48#ibcon#*mode == 0, iclass 23, count 0 2006.173.05:55:27.48#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.05:55:27.48#ibcon#[25=USB\r\n] 2006.173.05:55:27.48#ibcon#*before write, iclass 23, count 0 2006.173.05:55:27.48#ibcon#enter sib2, iclass 23, count 0 2006.173.05:55:27.48#ibcon#flushed, iclass 23, count 0 2006.173.05:55:27.48#ibcon#about to write, iclass 23, count 0 2006.173.05:55:27.48#ibcon#wrote, iclass 23, count 0 2006.173.05:55:27.48#ibcon#about to read 3, iclass 23, count 0 2006.173.05:55:27.50#ibcon#read 3, iclass 23, count 0 2006.173.05:55:27.50#ibcon#about to read 4, iclass 23, count 0 2006.173.05:55:27.51#ibcon#read 4, iclass 23, count 0 2006.173.05:55:27.51#ibcon#about to read 5, iclass 23, count 0 2006.173.05:55:27.51#ibcon#read 5, iclass 23, count 0 2006.173.05:55:27.51#ibcon#about to read 6, iclass 23, count 0 2006.173.05:55:27.51#ibcon#read 6, iclass 23, count 0 2006.173.05:55:27.51#ibcon#end of sib2, iclass 23, count 0 2006.173.05:55:27.51#ibcon#*after write, iclass 23, count 0 2006.173.05:55:27.51#ibcon#*before return 0, iclass 23, count 0 2006.173.05:55:27.51#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.05:55:27.51#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.05:55:27.51#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.05:55:27.51#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.05:55:27.51$vck44/valo=2,534.99 2006.173.05:55:27.51#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.05:55:27.51#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.05:55:27.51#ibcon#ireg 17 cls_cnt 0 2006.173.05:55:27.51#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.05:55:27.51#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.05:55:27.51#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.05:55:27.51#ibcon#enter wrdev, iclass 25, count 0 2006.173.05:55:27.51#ibcon#first serial, iclass 25, count 0 2006.173.05:55:27.51#ibcon#enter sib2, iclass 25, count 0 2006.173.05:55:27.51#ibcon#flushed, iclass 25, count 0 2006.173.05:55:27.51#ibcon#about to write, iclass 25, count 0 2006.173.05:55:27.51#ibcon#wrote, iclass 25, count 0 2006.173.05:55:27.51#ibcon#about to read 3, iclass 25, count 0 2006.173.05:55:27.53#ibcon#read 3, iclass 25, count 0 2006.173.05:55:27.53#ibcon#about to read 4, iclass 25, count 0 2006.173.05:55:27.53#ibcon#read 4, iclass 25, count 0 2006.173.05:55:27.53#ibcon#about to read 5, iclass 25, count 0 2006.173.05:55:27.53#ibcon#read 5, iclass 25, count 0 2006.173.05:55:27.53#ibcon#about to read 6, iclass 25, count 0 2006.173.05:55:27.53#ibcon#read 6, iclass 25, count 0 2006.173.05:55:27.53#ibcon#end of sib2, iclass 25, count 0 2006.173.05:55:27.53#ibcon#*mode == 0, iclass 25, count 0 2006.173.05:55:27.53#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.05:55:27.53#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.05:55:27.53#ibcon#*before write, iclass 25, count 0 2006.173.05:55:27.53#ibcon#enter sib2, iclass 25, count 0 2006.173.05:55:27.53#ibcon#flushed, iclass 25, count 0 2006.173.05:55:27.53#ibcon#about to write, iclass 25, count 0 2006.173.05:55:27.53#ibcon#wrote, iclass 25, count 0 2006.173.05:55:27.53#ibcon#about to read 3, iclass 25, count 0 2006.173.05:55:27.56#ibcon#read 3, iclass 25, count 0 2006.173.05:55:27.56#ibcon#about to read 4, iclass 25, count 0 2006.173.05:55:27.57#ibcon#read 4, iclass 25, count 0 2006.173.05:55:27.57#ibcon#about to read 5, iclass 25, count 0 2006.173.05:55:27.57#ibcon#read 5, iclass 25, count 0 2006.173.05:55:27.57#ibcon#about to read 6, iclass 25, count 0 2006.173.05:55:27.57#ibcon#read 6, iclass 25, count 0 2006.173.05:55:27.57#ibcon#end of sib2, iclass 25, count 0 2006.173.05:55:27.57#ibcon#*after write, iclass 25, count 0 2006.173.05:55:27.57#ibcon#*before return 0, iclass 25, count 0 2006.173.05:55:27.57#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.05:55:27.57#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.05:55:27.57#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.05:55:27.57#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.05:55:27.57$vck44/va=2,6 2006.173.05:55:27.57#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.05:55:27.57#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.05:55:27.57#ibcon#ireg 11 cls_cnt 2 2006.173.05:55:27.57#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.05:55:27.62#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.05:55:27.62#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.05:55:27.62#ibcon#enter wrdev, iclass 27, count 2 2006.173.05:55:27.62#ibcon#first serial, iclass 27, count 2 2006.173.05:55:27.63#ibcon#enter sib2, iclass 27, count 2 2006.173.05:55:27.63#ibcon#flushed, iclass 27, count 2 2006.173.05:55:27.63#ibcon#about to write, iclass 27, count 2 2006.173.05:55:27.63#ibcon#wrote, iclass 27, count 2 2006.173.05:55:27.63#ibcon#about to read 3, iclass 27, count 2 2006.173.05:55:27.64#ibcon#read 3, iclass 27, count 2 2006.173.05:55:27.64#ibcon#about to read 4, iclass 27, count 2 2006.173.05:55:27.64#ibcon#read 4, iclass 27, count 2 2006.173.05:55:27.65#ibcon#about to read 5, iclass 27, count 2 2006.173.05:55:27.65#ibcon#read 5, iclass 27, count 2 2006.173.05:55:27.65#ibcon#about to read 6, iclass 27, count 2 2006.173.05:55:27.65#ibcon#read 6, iclass 27, count 2 2006.173.05:55:27.65#ibcon#end of sib2, iclass 27, count 2 2006.173.05:55:27.65#ibcon#*mode == 0, iclass 27, count 2 2006.173.05:55:27.65#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.05:55:27.65#ibcon#[25=AT02-06\r\n] 2006.173.05:55:27.65#ibcon#*before write, iclass 27, count 2 2006.173.05:55:27.65#ibcon#enter sib2, iclass 27, count 2 2006.173.05:55:27.65#ibcon#flushed, iclass 27, count 2 2006.173.05:55:27.65#ibcon#about to write, iclass 27, count 2 2006.173.05:55:27.65#ibcon#wrote, iclass 27, count 2 2006.173.05:55:27.65#ibcon#about to read 3, iclass 27, count 2 2006.173.05:55:27.67#ibcon#read 3, iclass 27, count 2 2006.173.05:55:27.67#ibcon#about to read 4, iclass 27, count 2 2006.173.05:55:27.67#ibcon#read 4, iclass 27, count 2 2006.173.05:55:27.68#ibcon#about to read 5, iclass 27, count 2 2006.173.05:55:27.68#ibcon#read 5, iclass 27, count 2 2006.173.05:55:27.68#ibcon#about to read 6, iclass 27, count 2 2006.173.05:55:27.68#ibcon#read 6, iclass 27, count 2 2006.173.05:55:27.68#ibcon#end of sib2, iclass 27, count 2 2006.173.05:55:27.68#ibcon#*after write, iclass 27, count 2 2006.173.05:55:27.68#ibcon#*before return 0, iclass 27, count 2 2006.173.05:55:27.68#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.05:55:27.68#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.05:55:27.68#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.05:55:27.68#ibcon#ireg 7 cls_cnt 0 2006.173.05:55:27.68#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.05:55:27.79#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.05:55:27.79#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.05:55:27.79#ibcon#enter wrdev, iclass 27, count 0 2006.173.05:55:27.79#ibcon#first serial, iclass 27, count 0 2006.173.05:55:27.80#ibcon#enter sib2, iclass 27, count 0 2006.173.05:55:27.80#ibcon#flushed, iclass 27, count 0 2006.173.05:55:27.80#ibcon#about to write, iclass 27, count 0 2006.173.05:55:27.80#ibcon#wrote, iclass 27, count 0 2006.173.05:55:27.80#ibcon#about to read 3, iclass 27, count 0 2006.173.05:55:27.81#ibcon#read 3, iclass 27, count 0 2006.173.05:55:27.81#ibcon#about to read 4, iclass 27, count 0 2006.173.05:55:27.82#ibcon#read 4, iclass 27, count 0 2006.173.05:55:27.82#ibcon#about to read 5, iclass 27, count 0 2006.173.05:55:27.82#ibcon#read 5, iclass 27, count 0 2006.173.05:55:27.82#ibcon#about to read 6, iclass 27, count 0 2006.173.05:55:27.82#ibcon#read 6, iclass 27, count 0 2006.173.05:55:27.82#ibcon#end of sib2, iclass 27, count 0 2006.173.05:55:27.82#ibcon#*mode == 0, iclass 27, count 0 2006.173.05:55:27.82#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.05:55:27.82#ibcon#[25=USB\r\n] 2006.173.05:55:27.82#ibcon#*before write, iclass 27, count 0 2006.173.05:55:27.82#ibcon#enter sib2, iclass 27, count 0 2006.173.05:55:27.82#ibcon#flushed, iclass 27, count 0 2006.173.05:55:27.82#ibcon#about to write, iclass 27, count 0 2006.173.05:55:27.82#ibcon#wrote, iclass 27, count 0 2006.173.05:55:27.82#ibcon#about to read 3, iclass 27, count 0 2006.173.05:55:27.84#ibcon#read 3, iclass 27, count 0 2006.173.05:55:27.84#ibcon#about to read 4, iclass 27, count 0 2006.173.05:55:27.84#ibcon#read 4, iclass 27, count 0 2006.173.05:55:27.84#ibcon#about to read 5, iclass 27, count 0 2006.173.05:55:27.85#ibcon#read 5, iclass 27, count 0 2006.173.05:55:27.85#ibcon#about to read 6, iclass 27, count 0 2006.173.05:55:27.85#ibcon#read 6, iclass 27, count 0 2006.173.05:55:27.85#ibcon#end of sib2, iclass 27, count 0 2006.173.05:55:27.85#ibcon#*after write, iclass 27, count 0 2006.173.05:55:27.85#ibcon#*before return 0, iclass 27, count 0 2006.173.05:55:27.85#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.05:55:27.85#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.05:55:27.85#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.05:55:27.85#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.05:55:27.85$vck44/valo=3,564.99 2006.173.05:55:27.85#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.05:55:27.85#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.05:55:27.85#ibcon#ireg 17 cls_cnt 0 2006.173.05:55:27.85#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.05:55:27.85#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.05:55:27.85#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.05:55:27.85#ibcon#enter wrdev, iclass 29, count 0 2006.173.05:55:27.85#ibcon#first serial, iclass 29, count 0 2006.173.05:55:27.85#ibcon#enter sib2, iclass 29, count 0 2006.173.05:55:27.85#ibcon#flushed, iclass 29, count 0 2006.173.05:55:27.85#ibcon#about to write, iclass 29, count 0 2006.173.05:55:27.85#ibcon#wrote, iclass 29, count 0 2006.173.05:55:27.85#ibcon#about to read 3, iclass 29, count 0 2006.173.05:55:27.86#ibcon#read 3, iclass 29, count 0 2006.173.05:55:27.86#ibcon#about to read 4, iclass 29, count 0 2006.173.05:55:27.87#ibcon#read 4, iclass 29, count 0 2006.173.05:55:27.87#ibcon#about to read 5, iclass 29, count 0 2006.173.05:55:27.87#ibcon#read 5, iclass 29, count 0 2006.173.05:55:27.87#ibcon#about to read 6, iclass 29, count 0 2006.173.05:55:27.87#ibcon#read 6, iclass 29, count 0 2006.173.05:55:27.87#ibcon#end of sib2, iclass 29, count 0 2006.173.05:55:27.87#ibcon#*mode == 0, iclass 29, count 0 2006.173.05:55:27.87#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.05:55:27.87#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.05:55:27.87#ibcon#*before write, iclass 29, count 0 2006.173.05:55:27.87#ibcon#enter sib2, iclass 29, count 0 2006.173.05:55:27.87#ibcon#flushed, iclass 29, count 0 2006.173.05:55:27.87#ibcon#about to write, iclass 29, count 0 2006.173.05:55:27.87#ibcon#wrote, iclass 29, count 0 2006.173.05:55:27.87#ibcon#about to read 3, iclass 29, count 0 2006.173.05:55:27.90#ibcon#read 3, iclass 29, count 0 2006.173.05:55:27.90#ibcon#about to read 4, iclass 29, count 0 2006.173.05:55:27.90#ibcon#read 4, iclass 29, count 0 2006.173.05:55:27.91#ibcon#about to read 5, iclass 29, count 0 2006.173.05:55:27.91#ibcon#read 5, iclass 29, count 0 2006.173.05:55:27.91#ibcon#about to read 6, iclass 29, count 0 2006.173.05:55:27.91#ibcon#read 6, iclass 29, count 0 2006.173.05:55:27.91#ibcon#end of sib2, iclass 29, count 0 2006.173.05:55:27.91#ibcon#*after write, iclass 29, count 0 2006.173.05:55:27.91#ibcon#*before return 0, iclass 29, count 0 2006.173.05:55:27.91#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.05:55:27.91#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.05:55:27.91#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.05:55:27.91#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.05:55:27.91$vck44/va=3,5 2006.173.05:55:27.91#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.05:55:27.91#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.05:55:27.91#ibcon#ireg 11 cls_cnt 2 2006.173.05:55:27.91#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.05:55:27.96#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.05:55:27.96#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.05:55:27.96#ibcon#enter wrdev, iclass 31, count 2 2006.173.05:55:27.96#ibcon#first serial, iclass 31, count 2 2006.173.05:55:27.96#ibcon#enter sib2, iclass 31, count 2 2006.173.05:55:27.97#ibcon#flushed, iclass 31, count 2 2006.173.05:55:27.97#ibcon#about to write, iclass 31, count 2 2006.173.05:55:27.97#ibcon#wrote, iclass 31, count 2 2006.173.05:55:27.97#ibcon#about to read 3, iclass 31, count 2 2006.173.05:55:27.98#ibcon#read 3, iclass 31, count 2 2006.173.05:55:27.98#ibcon#about to read 4, iclass 31, count 2 2006.173.05:55:27.98#ibcon#read 4, iclass 31, count 2 2006.173.05:55:27.98#ibcon#about to read 5, iclass 31, count 2 2006.173.05:55:27.98#ibcon#read 5, iclass 31, count 2 2006.173.05:55:27.99#ibcon#about to read 6, iclass 31, count 2 2006.173.05:55:27.99#ibcon#read 6, iclass 31, count 2 2006.173.05:55:27.99#ibcon#end of sib2, iclass 31, count 2 2006.173.05:55:27.99#ibcon#*mode == 0, iclass 31, count 2 2006.173.05:55:27.99#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.05:55:27.99#ibcon#[25=AT03-05\r\n] 2006.173.05:55:27.99#ibcon#*before write, iclass 31, count 2 2006.173.05:55:27.99#ibcon#enter sib2, iclass 31, count 2 2006.173.05:55:27.99#ibcon#flushed, iclass 31, count 2 2006.173.05:55:27.99#ibcon#about to write, iclass 31, count 2 2006.173.05:55:27.99#ibcon#wrote, iclass 31, count 2 2006.173.05:55:27.99#ibcon#about to read 3, iclass 31, count 2 2006.173.05:55:28.01#ibcon#read 3, iclass 31, count 2 2006.173.05:55:28.01#ibcon#about to read 4, iclass 31, count 2 2006.173.05:55:28.01#ibcon#read 4, iclass 31, count 2 2006.173.05:55:28.01#ibcon#about to read 5, iclass 31, count 2 2006.173.05:55:28.02#ibcon#read 5, iclass 31, count 2 2006.173.05:55:28.02#ibcon#about to read 6, iclass 31, count 2 2006.173.05:55:28.02#ibcon#read 6, iclass 31, count 2 2006.173.05:55:28.02#ibcon#end of sib2, iclass 31, count 2 2006.173.05:55:28.02#ibcon#*after write, iclass 31, count 2 2006.173.05:55:28.02#ibcon#*before return 0, iclass 31, count 2 2006.173.05:55:28.02#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.05:55:28.02#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.05:55:28.02#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.05:55:28.02#ibcon#ireg 7 cls_cnt 0 2006.173.05:55:28.02#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.05:55:28.13#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.05:55:28.13#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.05:55:28.13#ibcon#enter wrdev, iclass 31, count 0 2006.173.05:55:28.13#ibcon#first serial, iclass 31, count 0 2006.173.05:55:28.14#ibcon#enter sib2, iclass 31, count 0 2006.173.05:55:28.14#ibcon#flushed, iclass 31, count 0 2006.173.05:55:28.14#ibcon#about to write, iclass 31, count 0 2006.173.05:55:28.14#ibcon#wrote, iclass 31, count 0 2006.173.05:55:28.14#ibcon#about to read 3, iclass 31, count 0 2006.173.05:55:28.15#ibcon#read 3, iclass 31, count 0 2006.173.05:55:28.15#ibcon#about to read 4, iclass 31, count 0 2006.173.05:55:28.16#ibcon#read 4, iclass 31, count 0 2006.173.05:55:28.16#ibcon#about to read 5, iclass 31, count 0 2006.173.05:55:28.16#ibcon#read 5, iclass 31, count 0 2006.173.05:55:28.16#ibcon#about to read 6, iclass 31, count 0 2006.173.05:55:28.16#ibcon#read 6, iclass 31, count 0 2006.173.05:55:28.16#ibcon#end of sib2, iclass 31, count 0 2006.173.05:55:28.16#ibcon#*mode == 0, iclass 31, count 0 2006.173.05:55:28.16#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.05:55:28.16#ibcon#[25=USB\r\n] 2006.173.05:55:28.16#ibcon#*before write, iclass 31, count 0 2006.173.05:55:28.16#ibcon#enter sib2, iclass 31, count 0 2006.173.05:55:28.16#ibcon#flushed, iclass 31, count 0 2006.173.05:55:28.16#ibcon#about to write, iclass 31, count 0 2006.173.05:55:28.16#ibcon#wrote, iclass 31, count 0 2006.173.05:55:28.16#ibcon#about to read 3, iclass 31, count 0 2006.173.05:55:28.18#ibcon#read 3, iclass 31, count 0 2006.173.05:55:28.18#ibcon#about to read 4, iclass 31, count 0 2006.173.05:55:28.18#ibcon#read 4, iclass 31, count 0 2006.173.05:55:28.19#ibcon#about to read 5, iclass 31, count 0 2006.173.05:55:28.19#ibcon#read 5, iclass 31, count 0 2006.173.05:55:28.19#ibcon#about to read 6, iclass 31, count 0 2006.173.05:55:28.19#ibcon#read 6, iclass 31, count 0 2006.173.05:55:28.19#ibcon#end of sib2, iclass 31, count 0 2006.173.05:55:28.19#ibcon#*after write, iclass 31, count 0 2006.173.05:55:28.19#ibcon#*before return 0, iclass 31, count 0 2006.173.05:55:28.19#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.05:55:28.19#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.05:55:28.19#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.05:55:28.19#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.05:55:28.19$vck44/valo=4,624.99 2006.173.05:55:28.19#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.05:55:28.19#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.05:55:28.19#ibcon#ireg 17 cls_cnt 0 2006.173.05:55:28.19#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.05:55:28.19#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.05:55:28.19#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.05:55:28.19#ibcon#enter wrdev, iclass 33, count 0 2006.173.05:55:28.19#ibcon#first serial, iclass 33, count 0 2006.173.05:55:28.19#ibcon#enter sib2, iclass 33, count 0 2006.173.05:55:28.19#ibcon#flushed, iclass 33, count 0 2006.173.05:55:28.19#ibcon#about to write, iclass 33, count 0 2006.173.05:55:28.19#ibcon#wrote, iclass 33, count 0 2006.173.05:55:28.19#ibcon#about to read 3, iclass 33, count 0 2006.173.05:55:28.20#ibcon#read 3, iclass 33, count 0 2006.173.05:55:28.20#ibcon#about to read 4, iclass 33, count 0 2006.173.05:55:28.20#ibcon#read 4, iclass 33, count 0 2006.173.05:55:28.20#ibcon#about to read 5, iclass 33, count 0 2006.173.05:55:28.20#ibcon#read 5, iclass 33, count 0 2006.173.05:55:28.21#ibcon#about to read 6, iclass 33, count 0 2006.173.05:55:28.21#ibcon#read 6, iclass 33, count 0 2006.173.05:55:28.21#ibcon#end of sib2, iclass 33, count 0 2006.173.05:55:28.21#ibcon#*mode == 0, iclass 33, count 0 2006.173.05:55:28.21#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.05:55:28.21#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.05:55:28.21#ibcon#*before write, iclass 33, count 0 2006.173.05:55:28.21#ibcon#enter sib2, iclass 33, count 0 2006.173.05:55:28.21#ibcon#flushed, iclass 33, count 0 2006.173.05:55:28.21#ibcon#about to write, iclass 33, count 0 2006.173.05:55:28.21#ibcon#wrote, iclass 33, count 0 2006.173.05:55:28.21#ibcon#about to read 3, iclass 33, count 0 2006.173.05:55:28.24#ibcon#read 3, iclass 33, count 0 2006.173.05:55:28.25#ibcon#about to read 4, iclass 33, count 0 2006.173.05:55:28.25#ibcon#read 4, iclass 33, count 0 2006.173.05:55:28.25#ibcon#about to read 5, iclass 33, count 0 2006.173.05:55:28.25#ibcon#read 5, iclass 33, count 0 2006.173.05:55:28.25#ibcon#about to read 6, iclass 33, count 0 2006.173.05:55:28.25#ibcon#read 6, iclass 33, count 0 2006.173.05:55:28.25#ibcon#end of sib2, iclass 33, count 0 2006.173.05:55:28.25#ibcon#*after write, iclass 33, count 0 2006.173.05:55:28.25#ibcon#*before return 0, iclass 33, count 0 2006.173.05:55:28.25#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.05:55:28.25#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.05:55:28.25#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.05:55:28.25#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.05:55:28.25$vck44/va=4,6 2006.173.05:55:28.25#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.05:55:28.25#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.05:55:28.25#ibcon#ireg 11 cls_cnt 2 2006.173.05:55:28.25#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.05:55:28.30#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.05:55:28.30#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.05:55:28.30#ibcon#enter wrdev, iclass 35, count 2 2006.173.05:55:28.30#ibcon#first serial, iclass 35, count 2 2006.173.05:55:28.31#ibcon#enter sib2, iclass 35, count 2 2006.173.05:55:28.31#ibcon#flushed, iclass 35, count 2 2006.173.05:55:28.31#ibcon#about to write, iclass 35, count 2 2006.173.05:55:28.31#ibcon#wrote, iclass 35, count 2 2006.173.05:55:28.31#ibcon#about to read 3, iclass 35, count 2 2006.173.05:55:28.32#ibcon#read 3, iclass 35, count 2 2006.173.05:55:28.33#ibcon#about to read 4, iclass 35, count 2 2006.173.05:55:28.33#ibcon#read 4, iclass 35, count 2 2006.173.05:55:28.33#ibcon#about to read 5, iclass 35, count 2 2006.173.05:55:28.33#ibcon#read 5, iclass 35, count 2 2006.173.05:55:28.33#ibcon#about to read 6, iclass 35, count 2 2006.173.05:55:28.33#ibcon#read 6, iclass 35, count 2 2006.173.05:55:28.33#ibcon#end of sib2, iclass 35, count 2 2006.173.05:55:28.33#ibcon#*mode == 0, iclass 35, count 2 2006.173.05:55:28.33#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.05:55:28.33#ibcon#[25=AT04-06\r\n] 2006.173.05:55:28.33#ibcon#*before write, iclass 35, count 2 2006.173.05:55:28.33#ibcon#enter sib2, iclass 35, count 2 2006.173.05:55:28.33#ibcon#flushed, iclass 35, count 2 2006.173.05:55:28.33#ibcon#about to write, iclass 35, count 2 2006.173.05:55:28.33#ibcon#wrote, iclass 35, count 2 2006.173.05:55:28.33#ibcon#about to read 3, iclass 35, count 2 2006.173.05:55:28.35#ibcon#read 3, iclass 35, count 2 2006.173.05:55:28.35#ibcon#about to read 4, iclass 35, count 2 2006.173.05:55:28.36#ibcon#read 4, iclass 35, count 2 2006.173.05:55:28.36#ibcon#about to read 5, iclass 35, count 2 2006.173.05:55:28.36#ibcon#read 5, iclass 35, count 2 2006.173.05:55:28.36#ibcon#about to read 6, iclass 35, count 2 2006.173.05:55:28.36#ibcon#read 6, iclass 35, count 2 2006.173.05:55:28.36#ibcon#end of sib2, iclass 35, count 2 2006.173.05:55:28.36#ibcon#*after write, iclass 35, count 2 2006.173.05:55:28.36#ibcon#*before return 0, iclass 35, count 2 2006.173.05:55:28.36#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.05:55:28.36#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.05:55:28.36#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.05:55:28.36#ibcon#ireg 7 cls_cnt 0 2006.173.05:55:28.36#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.05:55:28.47#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.05:55:28.47#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.05:55:28.47#ibcon#enter wrdev, iclass 35, count 0 2006.173.05:55:28.48#ibcon#first serial, iclass 35, count 0 2006.173.05:55:28.48#ibcon#enter sib2, iclass 35, count 0 2006.173.05:55:28.48#ibcon#flushed, iclass 35, count 0 2006.173.05:55:28.48#ibcon#about to write, iclass 35, count 0 2006.173.05:55:28.48#ibcon#wrote, iclass 35, count 0 2006.173.05:55:28.48#ibcon#about to read 3, iclass 35, count 0 2006.173.05:55:28.49#ibcon#read 3, iclass 35, count 0 2006.173.05:55:28.50#ibcon#about to read 4, iclass 35, count 0 2006.173.05:55:28.50#ibcon#read 4, iclass 35, count 0 2006.173.05:55:28.50#ibcon#about to read 5, iclass 35, count 0 2006.173.05:55:28.50#ibcon#read 5, iclass 35, count 0 2006.173.05:55:28.50#ibcon#about to read 6, iclass 35, count 0 2006.173.05:55:28.50#ibcon#read 6, iclass 35, count 0 2006.173.05:55:28.50#ibcon#end of sib2, iclass 35, count 0 2006.173.05:55:28.50#ibcon#*mode == 0, iclass 35, count 0 2006.173.05:55:28.50#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.05:55:28.50#ibcon#[25=USB\r\n] 2006.173.05:55:28.50#ibcon#*before write, iclass 35, count 0 2006.173.05:55:28.50#ibcon#enter sib2, iclass 35, count 0 2006.173.05:55:28.50#ibcon#flushed, iclass 35, count 0 2006.173.05:55:28.50#ibcon#about to write, iclass 35, count 0 2006.173.05:55:28.50#ibcon#wrote, iclass 35, count 0 2006.173.05:55:28.50#ibcon#about to read 3, iclass 35, count 0 2006.173.05:55:28.52#ibcon#read 3, iclass 35, count 0 2006.173.05:55:28.52#ibcon#about to read 4, iclass 35, count 0 2006.173.05:55:28.53#ibcon#read 4, iclass 35, count 0 2006.173.05:55:28.53#ibcon#about to read 5, iclass 35, count 0 2006.173.05:55:28.53#ibcon#read 5, iclass 35, count 0 2006.173.05:55:28.53#ibcon#about to read 6, iclass 35, count 0 2006.173.05:55:28.53#ibcon#read 6, iclass 35, count 0 2006.173.05:55:28.53#ibcon#end of sib2, iclass 35, count 0 2006.173.05:55:28.53#ibcon#*after write, iclass 35, count 0 2006.173.05:55:28.53#ibcon#*before return 0, iclass 35, count 0 2006.173.05:55:28.53#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.05:55:28.53#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.05:55:28.53#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.05:55:28.53#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.05:55:28.53$vck44/valo=5,734.99 2006.173.05:55:28.53#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.05:55:28.53#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.05:55:28.53#ibcon#ireg 17 cls_cnt 0 2006.173.05:55:28.53#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.05:55:28.53#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.05:55:28.53#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.05:55:28.53#ibcon#enter wrdev, iclass 37, count 0 2006.173.05:55:28.53#ibcon#first serial, iclass 37, count 0 2006.173.05:55:28.53#ibcon#enter sib2, iclass 37, count 0 2006.173.05:55:28.53#ibcon#flushed, iclass 37, count 0 2006.173.05:55:28.53#ibcon#about to write, iclass 37, count 0 2006.173.05:55:28.53#ibcon#wrote, iclass 37, count 0 2006.173.05:55:28.53#ibcon#about to read 3, iclass 37, count 0 2006.173.05:55:28.54#ibcon#read 3, iclass 37, count 0 2006.173.05:55:28.54#ibcon#about to read 4, iclass 37, count 0 2006.173.05:55:28.55#ibcon#read 4, iclass 37, count 0 2006.173.05:55:28.55#ibcon#about to read 5, iclass 37, count 0 2006.173.05:55:28.55#ibcon#read 5, iclass 37, count 0 2006.173.05:55:28.55#ibcon#about to read 6, iclass 37, count 0 2006.173.05:55:28.55#ibcon#read 6, iclass 37, count 0 2006.173.05:55:28.55#ibcon#end of sib2, iclass 37, count 0 2006.173.05:55:28.55#ibcon#*mode == 0, iclass 37, count 0 2006.173.05:55:28.55#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.05:55:28.55#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.05:55:28.55#ibcon#*before write, iclass 37, count 0 2006.173.05:55:28.55#ibcon#enter sib2, iclass 37, count 0 2006.173.05:55:28.55#ibcon#flushed, iclass 37, count 0 2006.173.05:55:28.55#ibcon#about to write, iclass 37, count 0 2006.173.05:55:28.55#ibcon#wrote, iclass 37, count 0 2006.173.05:55:28.55#ibcon#about to read 3, iclass 37, count 0 2006.173.05:55:28.58#ibcon#read 3, iclass 37, count 0 2006.173.05:55:28.58#ibcon#about to read 4, iclass 37, count 0 2006.173.05:55:28.59#ibcon#read 4, iclass 37, count 0 2006.173.05:55:28.59#ibcon#about to read 5, iclass 37, count 0 2006.173.05:55:28.59#ibcon#read 5, iclass 37, count 0 2006.173.05:55:28.59#ibcon#about to read 6, iclass 37, count 0 2006.173.05:55:28.59#ibcon#read 6, iclass 37, count 0 2006.173.05:55:28.59#ibcon#end of sib2, iclass 37, count 0 2006.173.05:55:28.59#ibcon#*after write, iclass 37, count 0 2006.173.05:55:28.59#ibcon#*before return 0, iclass 37, count 0 2006.173.05:55:28.59#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.05:55:28.59#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.05:55:28.59#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.05:55:28.59#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.05:55:28.59$vck44/va=5,4 2006.173.05:55:28.59#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.05:55:28.59#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.05:55:28.59#ibcon#ireg 11 cls_cnt 2 2006.173.05:55:28.59#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.05:55:28.64#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.05:55:28.64#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.05:55:28.64#ibcon#enter wrdev, iclass 39, count 2 2006.173.05:55:28.64#ibcon#first serial, iclass 39, count 2 2006.173.05:55:28.65#ibcon#enter sib2, iclass 39, count 2 2006.173.05:55:28.65#ibcon#flushed, iclass 39, count 2 2006.173.05:55:28.65#ibcon#about to write, iclass 39, count 2 2006.173.05:55:28.65#ibcon#wrote, iclass 39, count 2 2006.173.05:55:28.65#ibcon#about to read 3, iclass 39, count 2 2006.173.05:55:28.67#ibcon#read 3, iclass 39, count 2 2006.173.05:55:28.67#ibcon#about to read 4, iclass 39, count 2 2006.173.05:55:28.67#ibcon#read 4, iclass 39, count 2 2006.173.05:55:28.67#ibcon#about to read 5, iclass 39, count 2 2006.173.05:55:28.67#ibcon#read 5, iclass 39, count 2 2006.173.05:55:28.67#ibcon#about to read 6, iclass 39, count 2 2006.173.05:55:28.67#ibcon#read 6, iclass 39, count 2 2006.173.05:55:28.67#ibcon#end of sib2, iclass 39, count 2 2006.173.05:55:28.67#ibcon#*mode == 0, iclass 39, count 2 2006.173.05:55:28.67#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.05:55:28.67#ibcon#[25=AT05-04\r\n] 2006.173.05:55:28.67#ibcon#*before write, iclass 39, count 2 2006.173.05:55:28.67#ibcon#enter sib2, iclass 39, count 2 2006.173.05:55:28.67#ibcon#flushed, iclass 39, count 2 2006.173.05:55:28.67#ibcon#about to write, iclass 39, count 2 2006.173.05:55:28.67#ibcon#wrote, iclass 39, count 2 2006.173.05:55:28.67#ibcon#about to read 3, iclass 39, count 2 2006.173.05:55:28.69#ibcon#read 3, iclass 39, count 2 2006.173.05:55:28.69#ibcon#about to read 4, iclass 39, count 2 2006.173.05:55:28.69#ibcon#read 4, iclass 39, count 2 2006.173.05:55:28.70#ibcon#about to read 5, iclass 39, count 2 2006.173.05:55:28.70#ibcon#read 5, iclass 39, count 2 2006.173.05:55:28.70#ibcon#about to read 6, iclass 39, count 2 2006.173.05:55:28.70#ibcon#read 6, iclass 39, count 2 2006.173.05:55:28.70#ibcon#end of sib2, iclass 39, count 2 2006.173.05:55:28.70#ibcon#*after write, iclass 39, count 2 2006.173.05:55:28.70#ibcon#*before return 0, iclass 39, count 2 2006.173.05:55:28.70#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.05:55:28.70#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.05:55:28.70#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.05:55:28.70#ibcon#ireg 7 cls_cnt 0 2006.173.05:55:28.70#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.05:55:28.81#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.05:55:28.81#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.05:55:28.81#ibcon#enter wrdev, iclass 39, count 0 2006.173.05:55:28.81#ibcon#first serial, iclass 39, count 0 2006.173.05:55:28.82#ibcon#enter sib2, iclass 39, count 0 2006.173.05:55:28.82#ibcon#flushed, iclass 39, count 0 2006.173.05:55:28.82#ibcon#about to write, iclass 39, count 0 2006.173.05:55:28.82#ibcon#wrote, iclass 39, count 0 2006.173.05:55:28.82#ibcon#about to read 3, iclass 39, count 0 2006.173.05:55:28.83#ibcon#read 3, iclass 39, count 0 2006.173.05:55:28.83#ibcon#about to read 4, iclass 39, count 0 2006.173.05:55:28.84#ibcon#read 4, iclass 39, count 0 2006.173.05:55:28.84#ibcon#about to read 5, iclass 39, count 0 2006.173.05:55:28.84#ibcon#read 5, iclass 39, count 0 2006.173.05:55:28.84#ibcon#about to read 6, iclass 39, count 0 2006.173.05:55:28.84#ibcon#read 6, iclass 39, count 0 2006.173.05:55:28.84#ibcon#end of sib2, iclass 39, count 0 2006.173.05:55:28.84#ibcon#*mode == 0, iclass 39, count 0 2006.173.05:55:28.84#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.05:55:28.84#ibcon#[25=USB\r\n] 2006.173.05:55:28.84#ibcon#*before write, iclass 39, count 0 2006.173.05:55:28.84#ibcon#enter sib2, iclass 39, count 0 2006.173.05:55:28.84#ibcon#flushed, iclass 39, count 0 2006.173.05:55:28.84#ibcon#about to write, iclass 39, count 0 2006.173.05:55:28.84#ibcon#wrote, iclass 39, count 0 2006.173.05:55:28.84#ibcon#about to read 3, iclass 39, count 0 2006.173.05:55:28.86#ibcon#read 3, iclass 39, count 0 2006.173.05:55:28.86#ibcon#about to read 4, iclass 39, count 0 2006.173.05:55:28.86#ibcon#read 4, iclass 39, count 0 2006.173.05:55:28.87#ibcon#about to read 5, iclass 39, count 0 2006.173.05:55:28.87#ibcon#read 5, iclass 39, count 0 2006.173.05:55:28.87#ibcon#about to read 6, iclass 39, count 0 2006.173.05:55:28.87#ibcon#read 6, iclass 39, count 0 2006.173.05:55:28.87#ibcon#end of sib2, iclass 39, count 0 2006.173.05:55:28.87#ibcon#*after write, iclass 39, count 0 2006.173.05:55:28.87#ibcon#*before return 0, iclass 39, count 0 2006.173.05:55:28.87#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.05:55:28.87#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.05:55:28.87#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.05:55:28.87#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.05:55:28.87$vck44/valo=6,814.99 2006.173.05:55:28.87#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.05:55:28.87#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.05:55:28.87#ibcon#ireg 17 cls_cnt 0 2006.173.05:55:28.87#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.05:55:28.87#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.05:55:28.87#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.05:55:28.87#ibcon#enter wrdev, iclass 3, count 0 2006.173.05:55:28.87#ibcon#first serial, iclass 3, count 0 2006.173.05:55:28.87#ibcon#enter sib2, iclass 3, count 0 2006.173.05:55:28.87#ibcon#flushed, iclass 3, count 0 2006.173.05:55:28.87#ibcon#about to write, iclass 3, count 0 2006.173.05:55:28.87#ibcon#wrote, iclass 3, count 0 2006.173.05:55:28.87#ibcon#about to read 3, iclass 3, count 0 2006.173.05:55:28.88#ibcon#read 3, iclass 3, count 0 2006.173.05:55:28.88#ibcon#about to read 4, iclass 3, count 0 2006.173.05:55:28.89#ibcon#read 4, iclass 3, count 0 2006.173.05:55:28.89#ibcon#about to read 5, iclass 3, count 0 2006.173.05:55:28.89#ibcon#read 5, iclass 3, count 0 2006.173.05:55:28.89#ibcon#about to read 6, iclass 3, count 0 2006.173.05:55:28.89#ibcon#read 6, iclass 3, count 0 2006.173.05:55:28.89#ibcon#end of sib2, iclass 3, count 0 2006.173.05:55:28.89#ibcon#*mode == 0, iclass 3, count 0 2006.173.05:55:28.89#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.05:55:28.89#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.05:55:28.89#ibcon#*before write, iclass 3, count 0 2006.173.05:55:28.89#ibcon#enter sib2, iclass 3, count 0 2006.173.05:55:28.89#ibcon#flushed, iclass 3, count 0 2006.173.05:55:28.89#ibcon#about to write, iclass 3, count 0 2006.173.05:55:28.89#ibcon#wrote, iclass 3, count 0 2006.173.05:55:28.89#ibcon#about to read 3, iclass 3, count 0 2006.173.05:55:28.92#ibcon#read 3, iclass 3, count 0 2006.173.05:55:28.93#ibcon#about to read 4, iclass 3, count 0 2006.173.05:55:28.93#ibcon#read 4, iclass 3, count 0 2006.173.05:55:28.93#ibcon#about to read 5, iclass 3, count 0 2006.173.05:55:28.93#ibcon#read 5, iclass 3, count 0 2006.173.05:55:28.93#ibcon#about to read 6, iclass 3, count 0 2006.173.05:55:28.93#ibcon#read 6, iclass 3, count 0 2006.173.05:55:28.93#ibcon#end of sib2, iclass 3, count 0 2006.173.05:55:28.93#ibcon#*after write, iclass 3, count 0 2006.173.05:55:28.93#ibcon#*before return 0, iclass 3, count 0 2006.173.05:55:28.93#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.05:55:28.93#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.05:55:28.93#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.05:55:28.93#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.05:55:28.93$vck44/va=6,3 2006.173.05:55:28.93#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.05:55:28.93#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.05:55:28.93#ibcon#ireg 11 cls_cnt 2 2006.173.05:55:28.93#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.05:55:28.98#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.05:55:28.98#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.05:55:28.98#ibcon#enter wrdev, iclass 5, count 2 2006.173.05:55:28.98#ibcon#first serial, iclass 5, count 2 2006.173.05:55:28.99#ibcon#enter sib2, iclass 5, count 2 2006.173.05:55:28.99#ibcon#flushed, iclass 5, count 2 2006.173.05:55:28.99#ibcon#about to write, iclass 5, count 2 2006.173.05:55:28.99#ibcon#wrote, iclass 5, count 2 2006.173.05:55:28.99#ibcon#about to read 3, iclass 5, count 2 2006.173.05:55:29.00#ibcon#read 3, iclass 5, count 2 2006.173.05:55:29.00#ibcon#about to read 4, iclass 5, count 2 2006.173.05:55:29.01#ibcon#read 4, iclass 5, count 2 2006.173.05:55:29.01#ibcon#about to read 5, iclass 5, count 2 2006.173.05:55:29.01#ibcon#read 5, iclass 5, count 2 2006.173.05:55:29.01#ibcon#about to read 6, iclass 5, count 2 2006.173.05:55:29.01#ibcon#read 6, iclass 5, count 2 2006.173.05:55:29.01#ibcon#end of sib2, iclass 5, count 2 2006.173.05:55:29.01#ibcon#*mode == 0, iclass 5, count 2 2006.173.05:55:29.01#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.05:55:29.01#ibcon#[25=AT06-03\r\n] 2006.173.05:55:29.01#ibcon#*before write, iclass 5, count 2 2006.173.05:55:29.01#ibcon#enter sib2, iclass 5, count 2 2006.173.05:55:29.01#ibcon#flushed, iclass 5, count 2 2006.173.05:55:29.01#ibcon#about to write, iclass 5, count 2 2006.173.05:55:29.01#ibcon#wrote, iclass 5, count 2 2006.173.05:55:29.01#ibcon#about to read 3, iclass 5, count 2 2006.173.05:55:29.03#ibcon#read 3, iclass 5, count 2 2006.173.05:55:29.03#ibcon#about to read 4, iclass 5, count 2 2006.173.05:55:29.03#ibcon#read 4, iclass 5, count 2 2006.173.05:55:29.04#ibcon#about to read 5, iclass 5, count 2 2006.173.05:55:29.04#ibcon#read 5, iclass 5, count 2 2006.173.05:55:29.04#ibcon#about to read 6, iclass 5, count 2 2006.173.05:55:29.04#ibcon#read 6, iclass 5, count 2 2006.173.05:55:29.04#ibcon#end of sib2, iclass 5, count 2 2006.173.05:55:29.04#ibcon#*after write, iclass 5, count 2 2006.173.05:55:29.04#ibcon#*before return 0, iclass 5, count 2 2006.173.05:55:29.04#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.05:55:29.04#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.05:55:29.04#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.05:55:29.04#ibcon#ireg 7 cls_cnt 0 2006.173.05:55:29.04#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.05:55:29.15#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.05:55:29.15#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.05:55:29.15#ibcon#enter wrdev, iclass 5, count 0 2006.173.05:55:29.15#ibcon#first serial, iclass 5, count 0 2006.173.05:55:29.16#ibcon#enter sib2, iclass 5, count 0 2006.173.05:55:29.16#ibcon#flushed, iclass 5, count 0 2006.173.05:55:29.16#ibcon#about to write, iclass 5, count 0 2006.173.05:55:29.16#ibcon#wrote, iclass 5, count 0 2006.173.05:55:29.16#ibcon#about to read 3, iclass 5, count 0 2006.173.05:55:29.17#ibcon#read 3, iclass 5, count 0 2006.173.05:55:29.17#ibcon#about to read 4, iclass 5, count 0 2006.173.05:55:29.17#ibcon#read 4, iclass 5, count 0 2006.173.05:55:29.17#ibcon#about to read 5, iclass 5, count 0 2006.173.05:55:29.17#ibcon#read 5, iclass 5, count 0 2006.173.05:55:29.17#ibcon#about to read 6, iclass 5, count 0 2006.173.05:55:29.18#ibcon#read 6, iclass 5, count 0 2006.173.05:55:29.18#ibcon#end of sib2, iclass 5, count 0 2006.173.05:55:29.18#ibcon#*mode == 0, iclass 5, count 0 2006.173.05:55:29.18#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.05:55:29.18#ibcon#[25=USB\r\n] 2006.173.05:55:29.18#ibcon#*before write, iclass 5, count 0 2006.173.05:55:29.18#ibcon#enter sib2, iclass 5, count 0 2006.173.05:55:29.18#ibcon#flushed, iclass 5, count 0 2006.173.05:55:29.18#ibcon#about to write, iclass 5, count 0 2006.173.05:55:29.18#ibcon#wrote, iclass 5, count 0 2006.173.05:55:29.18#ibcon#about to read 3, iclass 5, count 0 2006.173.05:55:29.20#ibcon#read 3, iclass 5, count 0 2006.173.05:55:29.20#ibcon#about to read 4, iclass 5, count 0 2006.173.05:55:29.20#ibcon#read 4, iclass 5, count 0 2006.173.05:55:29.20#ibcon#about to read 5, iclass 5, count 0 2006.173.05:55:29.20#ibcon#read 5, iclass 5, count 0 2006.173.05:55:29.21#ibcon#about to read 6, iclass 5, count 0 2006.173.05:55:29.21#ibcon#read 6, iclass 5, count 0 2006.173.05:55:29.21#ibcon#end of sib2, iclass 5, count 0 2006.173.05:55:29.21#ibcon#*after write, iclass 5, count 0 2006.173.05:55:29.21#ibcon#*before return 0, iclass 5, count 0 2006.173.05:55:29.21#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.05:55:29.21#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.05:55:29.21#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.05:55:29.21#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.05:55:29.21$vck44/valo=7,864.99 2006.173.05:55:29.21#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.05:55:29.21#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.05:55:29.21#ibcon#ireg 17 cls_cnt 0 2006.173.05:55:29.21#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.05:55:29.21#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.05:55:29.21#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.05:55:29.21#ibcon#enter wrdev, iclass 7, count 0 2006.173.05:55:29.21#ibcon#first serial, iclass 7, count 0 2006.173.05:55:29.21#ibcon#enter sib2, iclass 7, count 0 2006.173.05:55:29.21#ibcon#flushed, iclass 7, count 0 2006.173.05:55:29.21#ibcon#about to write, iclass 7, count 0 2006.173.05:55:29.21#ibcon#wrote, iclass 7, count 0 2006.173.05:55:29.21#ibcon#about to read 3, iclass 7, count 0 2006.173.05:55:29.22#ibcon#read 3, iclass 7, count 0 2006.173.05:55:29.22#ibcon#about to read 4, iclass 7, count 0 2006.173.05:55:29.23#ibcon#read 4, iclass 7, count 0 2006.173.05:55:29.23#ibcon#about to read 5, iclass 7, count 0 2006.173.05:55:29.23#ibcon#read 5, iclass 7, count 0 2006.173.05:55:29.23#ibcon#about to read 6, iclass 7, count 0 2006.173.05:55:29.23#ibcon#read 6, iclass 7, count 0 2006.173.05:55:29.23#ibcon#end of sib2, iclass 7, count 0 2006.173.05:55:29.23#ibcon#*mode == 0, iclass 7, count 0 2006.173.05:55:29.23#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.05:55:29.23#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.05:55:29.23#ibcon#*before write, iclass 7, count 0 2006.173.05:55:29.23#ibcon#enter sib2, iclass 7, count 0 2006.173.05:55:29.23#ibcon#flushed, iclass 7, count 0 2006.173.05:55:29.23#ibcon#about to write, iclass 7, count 0 2006.173.05:55:29.23#ibcon#wrote, iclass 7, count 0 2006.173.05:55:29.23#ibcon#about to read 3, iclass 7, count 0 2006.173.05:55:29.27#ibcon#read 3, iclass 7, count 0 2006.173.05:55:29.27#ibcon#about to read 4, iclass 7, count 0 2006.173.05:55:29.27#ibcon#read 4, iclass 7, count 0 2006.173.05:55:29.27#ibcon#about to read 5, iclass 7, count 0 2006.173.05:55:29.27#ibcon#read 5, iclass 7, count 0 2006.173.05:55:29.27#ibcon#about to read 6, iclass 7, count 0 2006.173.05:55:29.27#ibcon#read 6, iclass 7, count 0 2006.173.05:55:29.27#ibcon#end of sib2, iclass 7, count 0 2006.173.05:55:29.27#ibcon#*after write, iclass 7, count 0 2006.173.05:55:29.27#ibcon#*before return 0, iclass 7, count 0 2006.173.05:55:29.27#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.05:55:29.27#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.05:55:29.27#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.05:55:29.27#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.05:55:29.27$vck44/va=7,4 2006.173.05:55:29.27#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.05:55:29.27#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.05:55:29.27#ibcon#ireg 11 cls_cnt 2 2006.173.05:55:29.27#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.05:55:29.32#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.05:55:29.32#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.05:55:29.32#ibcon#enter wrdev, iclass 11, count 2 2006.173.05:55:29.32#ibcon#first serial, iclass 11, count 2 2006.173.05:55:29.33#ibcon#enter sib2, iclass 11, count 2 2006.173.05:55:29.33#ibcon#flushed, iclass 11, count 2 2006.173.05:55:29.33#ibcon#about to write, iclass 11, count 2 2006.173.05:55:29.33#ibcon#wrote, iclass 11, count 2 2006.173.05:55:29.33#ibcon#about to read 3, iclass 11, count 2 2006.173.05:55:29.34#ibcon#read 3, iclass 11, count 2 2006.173.05:55:29.34#ibcon#about to read 4, iclass 11, count 2 2006.173.05:55:29.34#ibcon#read 4, iclass 11, count 2 2006.173.05:55:29.34#ibcon#about to read 5, iclass 11, count 2 2006.173.05:55:29.34#ibcon#read 5, iclass 11, count 2 2006.173.05:55:29.34#ibcon#about to read 6, iclass 11, count 2 2006.173.05:55:29.35#ibcon#read 6, iclass 11, count 2 2006.173.05:55:29.35#ibcon#end of sib2, iclass 11, count 2 2006.173.05:55:29.35#ibcon#*mode == 0, iclass 11, count 2 2006.173.05:55:29.35#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.05:55:29.35#ibcon#[25=AT07-04\r\n] 2006.173.05:55:29.35#ibcon#*before write, iclass 11, count 2 2006.173.05:55:29.35#ibcon#enter sib2, iclass 11, count 2 2006.173.05:55:29.35#ibcon#flushed, iclass 11, count 2 2006.173.05:55:29.35#ibcon#about to write, iclass 11, count 2 2006.173.05:55:29.35#ibcon#wrote, iclass 11, count 2 2006.173.05:55:29.35#ibcon#about to read 3, iclass 11, count 2 2006.173.05:55:29.37#ibcon#read 3, iclass 11, count 2 2006.173.05:55:29.37#ibcon#about to read 4, iclass 11, count 2 2006.173.05:55:29.37#ibcon#read 4, iclass 11, count 2 2006.173.05:55:29.37#ibcon#about to read 5, iclass 11, count 2 2006.173.05:55:29.37#ibcon#read 5, iclass 11, count 2 2006.173.05:55:29.37#ibcon#about to read 6, iclass 11, count 2 2006.173.05:55:29.38#ibcon#read 6, iclass 11, count 2 2006.173.05:55:29.38#ibcon#end of sib2, iclass 11, count 2 2006.173.05:55:29.38#ibcon#*after write, iclass 11, count 2 2006.173.05:55:29.38#ibcon#*before return 0, iclass 11, count 2 2006.173.05:55:29.38#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.05:55:29.38#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.05:55:29.38#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.05:55:29.38#ibcon#ireg 7 cls_cnt 0 2006.173.05:55:29.38#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.05:55:29.50#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.05:55:29.50#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.05:55:29.50#ibcon#enter wrdev, iclass 11, count 0 2006.173.05:55:29.50#ibcon#first serial, iclass 11, count 0 2006.173.05:55:29.50#ibcon#enter sib2, iclass 11, count 0 2006.173.05:55:29.50#ibcon#flushed, iclass 11, count 0 2006.173.05:55:29.50#ibcon#about to write, iclass 11, count 0 2006.173.05:55:29.50#ibcon#wrote, iclass 11, count 0 2006.173.05:55:29.50#ibcon#about to read 3, iclass 11, count 0 2006.173.05:55:29.51#ibcon#read 3, iclass 11, count 0 2006.173.05:55:29.51#ibcon#about to read 4, iclass 11, count 0 2006.173.05:55:29.51#ibcon#read 4, iclass 11, count 0 2006.173.05:55:29.51#ibcon#about to read 5, iclass 11, count 0 2006.173.05:55:29.51#ibcon#read 5, iclass 11, count 0 2006.173.05:55:29.52#ibcon#about to read 6, iclass 11, count 0 2006.173.05:55:29.52#ibcon#read 6, iclass 11, count 0 2006.173.05:55:29.52#ibcon#end of sib2, iclass 11, count 0 2006.173.05:55:29.52#ibcon#*mode == 0, iclass 11, count 0 2006.173.05:55:29.52#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.05:55:29.52#ibcon#[25=USB\r\n] 2006.173.05:55:29.52#ibcon#*before write, iclass 11, count 0 2006.173.05:55:29.52#ibcon#enter sib2, iclass 11, count 0 2006.173.05:55:29.52#ibcon#flushed, iclass 11, count 0 2006.173.05:55:29.52#ibcon#about to write, iclass 11, count 0 2006.173.05:55:29.52#ibcon#wrote, iclass 11, count 0 2006.173.05:55:29.52#ibcon#about to read 3, iclass 11, count 0 2006.173.05:55:29.54#ibcon#read 3, iclass 11, count 0 2006.173.05:55:29.55#ibcon#about to read 4, iclass 11, count 0 2006.173.05:55:29.55#ibcon#read 4, iclass 11, count 0 2006.173.05:55:29.55#ibcon#about to read 5, iclass 11, count 0 2006.173.05:55:29.55#ibcon#read 5, iclass 11, count 0 2006.173.05:55:29.55#ibcon#about to read 6, iclass 11, count 0 2006.173.05:55:29.55#ibcon#read 6, iclass 11, count 0 2006.173.05:55:29.55#ibcon#end of sib2, iclass 11, count 0 2006.173.05:55:29.55#ibcon#*after write, iclass 11, count 0 2006.173.05:55:29.55#ibcon#*before return 0, iclass 11, count 0 2006.173.05:55:29.55#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.05:55:29.55#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.05:55:29.55#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.05:55:29.55#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.05:55:29.55$vck44/valo=8,884.99 2006.173.05:55:29.55#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.05:55:29.55#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.05:55:29.55#ibcon#ireg 17 cls_cnt 0 2006.173.05:55:29.55#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.05:55:29.55#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.05:55:29.55#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.05:55:29.55#ibcon#enter wrdev, iclass 13, count 0 2006.173.05:55:29.55#ibcon#first serial, iclass 13, count 0 2006.173.05:55:29.55#ibcon#enter sib2, iclass 13, count 0 2006.173.05:55:29.55#ibcon#flushed, iclass 13, count 0 2006.173.05:55:29.55#ibcon#about to write, iclass 13, count 0 2006.173.05:55:29.55#ibcon#wrote, iclass 13, count 0 2006.173.05:55:29.55#ibcon#about to read 3, iclass 13, count 0 2006.173.05:55:29.56#ibcon#read 3, iclass 13, count 0 2006.173.05:55:29.57#ibcon#about to read 4, iclass 13, count 0 2006.173.05:55:29.57#ibcon#read 4, iclass 13, count 0 2006.173.05:55:29.57#ibcon#about to read 5, iclass 13, count 0 2006.173.05:55:29.57#ibcon#read 5, iclass 13, count 0 2006.173.05:55:29.57#ibcon#about to read 6, iclass 13, count 0 2006.173.05:55:29.57#ibcon#read 6, iclass 13, count 0 2006.173.05:55:29.57#ibcon#end of sib2, iclass 13, count 0 2006.173.05:55:29.57#ibcon#*mode == 0, iclass 13, count 0 2006.173.05:55:29.57#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.05:55:29.57#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.05:55:29.57#ibcon#*before write, iclass 13, count 0 2006.173.05:55:29.57#ibcon#enter sib2, iclass 13, count 0 2006.173.05:55:29.57#ibcon#flushed, iclass 13, count 0 2006.173.05:55:29.57#ibcon#about to write, iclass 13, count 0 2006.173.05:55:29.57#ibcon#wrote, iclass 13, count 0 2006.173.05:55:29.57#ibcon#about to read 3, iclass 13, count 0 2006.173.05:55:29.60#ibcon#read 3, iclass 13, count 0 2006.173.05:55:29.60#ibcon#about to read 4, iclass 13, count 0 2006.173.05:55:29.61#ibcon#read 4, iclass 13, count 0 2006.173.05:55:29.61#ibcon#about to read 5, iclass 13, count 0 2006.173.05:55:29.61#ibcon#read 5, iclass 13, count 0 2006.173.05:55:29.61#ibcon#about to read 6, iclass 13, count 0 2006.173.05:55:29.61#ibcon#read 6, iclass 13, count 0 2006.173.05:55:29.61#ibcon#end of sib2, iclass 13, count 0 2006.173.05:55:29.61#ibcon#*after write, iclass 13, count 0 2006.173.05:55:29.61#ibcon#*before return 0, iclass 13, count 0 2006.173.05:55:29.61#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.05:55:29.61#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.05:55:29.61#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.05:55:29.61#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.05:55:29.61$vck44/va=8,4 2006.173.05:55:29.61#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.05:55:29.61#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.05:55:29.61#ibcon#ireg 11 cls_cnt 2 2006.173.05:55:29.61#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.05:55:29.66#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.05:55:29.66#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.05:55:29.66#ibcon#enter wrdev, iclass 15, count 2 2006.173.05:55:29.66#ibcon#first serial, iclass 15, count 2 2006.173.05:55:29.67#ibcon#enter sib2, iclass 15, count 2 2006.173.05:55:29.67#ibcon#flushed, iclass 15, count 2 2006.173.05:55:29.67#ibcon#about to write, iclass 15, count 2 2006.173.05:55:29.67#ibcon#wrote, iclass 15, count 2 2006.173.05:55:29.67#ibcon#about to read 3, iclass 15, count 2 2006.173.05:55:29.68#ibcon#read 3, iclass 15, count 2 2006.173.05:55:29.68#ibcon#about to read 4, iclass 15, count 2 2006.173.05:55:29.69#ibcon#read 4, iclass 15, count 2 2006.173.05:55:29.69#ibcon#about to read 5, iclass 15, count 2 2006.173.05:55:29.69#ibcon#read 5, iclass 15, count 2 2006.173.05:55:29.69#ibcon#about to read 6, iclass 15, count 2 2006.173.05:55:29.69#ibcon#read 6, iclass 15, count 2 2006.173.05:55:29.69#ibcon#end of sib2, iclass 15, count 2 2006.173.05:55:29.69#ibcon#*mode == 0, iclass 15, count 2 2006.173.05:55:29.69#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.05:55:29.69#ibcon#[25=AT08-04\r\n] 2006.173.05:55:29.69#ibcon#*before write, iclass 15, count 2 2006.173.05:55:29.69#ibcon#enter sib2, iclass 15, count 2 2006.173.05:55:29.69#ibcon#flushed, iclass 15, count 2 2006.173.05:55:29.69#ibcon#about to write, iclass 15, count 2 2006.173.05:55:29.69#ibcon#wrote, iclass 15, count 2 2006.173.05:55:29.69#ibcon#about to read 3, iclass 15, count 2 2006.173.05:55:29.71#ibcon#read 3, iclass 15, count 2 2006.173.05:55:29.71#ibcon#about to read 4, iclass 15, count 2 2006.173.05:55:29.71#ibcon#read 4, iclass 15, count 2 2006.173.05:55:29.72#ibcon#about to read 5, iclass 15, count 2 2006.173.05:55:29.72#ibcon#read 5, iclass 15, count 2 2006.173.05:55:29.72#ibcon#about to read 6, iclass 15, count 2 2006.173.05:55:29.72#ibcon#read 6, iclass 15, count 2 2006.173.05:55:29.72#ibcon#end of sib2, iclass 15, count 2 2006.173.05:55:29.72#ibcon#*after write, iclass 15, count 2 2006.173.05:55:29.72#ibcon#*before return 0, iclass 15, count 2 2006.173.05:55:29.72#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.05:55:29.72#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.05:55:29.72#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.05:55:29.72#ibcon#ireg 7 cls_cnt 0 2006.173.05:55:29.72#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.05:55:29.83#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.05:55:29.83#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.05:55:29.83#ibcon#enter wrdev, iclass 15, count 0 2006.173.05:55:29.83#ibcon#first serial, iclass 15, count 0 2006.173.05:55:29.84#ibcon#enter sib2, iclass 15, count 0 2006.173.05:55:29.84#ibcon#flushed, iclass 15, count 0 2006.173.05:55:29.84#ibcon#about to write, iclass 15, count 0 2006.173.05:55:29.84#ibcon#wrote, iclass 15, count 0 2006.173.05:55:29.84#ibcon#about to read 3, iclass 15, count 0 2006.173.05:55:29.85#ibcon#read 3, iclass 15, count 0 2006.173.05:55:29.85#ibcon#about to read 4, iclass 15, count 0 2006.173.05:55:29.85#ibcon#read 4, iclass 15, count 0 2006.173.05:55:29.85#ibcon#about to read 5, iclass 15, count 0 2006.173.05:55:29.86#ibcon#read 5, iclass 15, count 0 2006.173.05:55:29.86#ibcon#about to read 6, iclass 15, count 0 2006.173.05:55:29.86#ibcon#read 6, iclass 15, count 0 2006.173.05:55:29.86#ibcon#end of sib2, iclass 15, count 0 2006.173.05:55:29.86#ibcon#*mode == 0, iclass 15, count 0 2006.173.05:55:29.86#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.05:55:29.86#ibcon#[25=USB\r\n] 2006.173.05:55:29.86#ibcon#*before write, iclass 15, count 0 2006.173.05:55:29.86#ibcon#enter sib2, iclass 15, count 0 2006.173.05:55:29.86#ibcon#flushed, iclass 15, count 0 2006.173.05:55:29.86#ibcon#about to write, iclass 15, count 0 2006.173.05:55:29.86#ibcon#wrote, iclass 15, count 0 2006.173.05:55:29.86#ibcon#about to read 3, iclass 15, count 0 2006.173.05:55:29.88#ibcon#read 3, iclass 15, count 0 2006.173.05:55:29.88#ibcon#about to read 4, iclass 15, count 0 2006.173.05:55:29.88#ibcon#read 4, iclass 15, count 0 2006.173.05:55:29.89#ibcon#about to read 5, iclass 15, count 0 2006.173.05:55:29.89#ibcon#read 5, iclass 15, count 0 2006.173.05:55:29.89#ibcon#about to read 6, iclass 15, count 0 2006.173.05:55:29.89#ibcon#read 6, iclass 15, count 0 2006.173.05:55:29.89#ibcon#end of sib2, iclass 15, count 0 2006.173.05:55:29.89#ibcon#*after write, iclass 15, count 0 2006.173.05:55:29.89#ibcon#*before return 0, iclass 15, count 0 2006.173.05:55:29.89#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.05:55:29.89#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.05:55:29.89#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.05:55:29.89#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.05:55:29.89$vck44/vblo=1,629.99 2006.173.05:55:29.89#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.05:55:29.89#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.05:55:29.89#ibcon#ireg 17 cls_cnt 0 2006.173.05:55:29.89#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.05:55:29.89#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.05:55:29.89#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.05:55:29.89#ibcon#enter wrdev, iclass 17, count 0 2006.173.05:55:29.89#ibcon#first serial, iclass 17, count 0 2006.173.05:55:29.89#ibcon#enter sib2, iclass 17, count 0 2006.173.05:55:29.89#ibcon#flushed, iclass 17, count 0 2006.173.05:55:29.89#ibcon#about to write, iclass 17, count 0 2006.173.05:55:29.89#ibcon#wrote, iclass 17, count 0 2006.173.05:55:29.89#ibcon#about to read 3, iclass 17, count 0 2006.173.05:55:29.90#ibcon#read 3, iclass 17, count 0 2006.173.05:55:29.90#ibcon#about to read 4, iclass 17, count 0 2006.173.05:55:29.91#ibcon#read 4, iclass 17, count 0 2006.173.05:55:29.91#ibcon#about to read 5, iclass 17, count 0 2006.173.05:55:29.91#ibcon#read 5, iclass 17, count 0 2006.173.05:55:29.91#ibcon#about to read 6, iclass 17, count 0 2006.173.05:55:29.91#ibcon#read 6, iclass 17, count 0 2006.173.05:55:29.91#ibcon#end of sib2, iclass 17, count 0 2006.173.05:55:29.91#ibcon#*mode == 0, iclass 17, count 0 2006.173.05:55:29.91#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.05:55:29.91#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.05:55:29.91#ibcon#*before write, iclass 17, count 0 2006.173.05:55:29.91#ibcon#enter sib2, iclass 17, count 0 2006.173.05:55:29.91#ibcon#flushed, iclass 17, count 0 2006.173.05:55:29.91#ibcon#about to write, iclass 17, count 0 2006.173.05:55:29.91#ibcon#wrote, iclass 17, count 0 2006.173.05:55:29.91#ibcon#about to read 3, iclass 17, count 0 2006.173.05:55:29.94#ibcon#read 3, iclass 17, count 0 2006.173.05:55:29.94#ibcon#about to read 4, iclass 17, count 0 2006.173.05:55:29.95#ibcon#read 4, iclass 17, count 0 2006.173.05:55:29.95#ibcon#about to read 5, iclass 17, count 0 2006.173.05:55:29.95#ibcon#read 5, iclass 17, count 0 2006.173.05:55:29.95#ibcon#about to read 6, iclass 17, count 0 2006.173.05:55:29.95#ibcon#read 6, iclass 17, count 0 2006.173.05:55:29.95#ibcon#end of sib2, iclass 17, count 0 2006.173.05:55:29.95#ibcon#*after write, iclass 17, count 0 2006.173.05:55:29.95#ibcon#*before return 0, iclass 17, count 0 2006.173.05:55:29.95#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.05:55:29.95#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.05:55:29.95#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.05:55:29.95#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.05:55:29.95$vck44/vb=1,4 2006.173.05:55:29.95#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.05:55:29.95#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.05:55:29.95#ibcon#ireg 11 cls_cnt 2 2006.173.05:55:29.95#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.05:55:29.95#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.05:55:29.95#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.05:55:29.95#ibcon#enter wrdev, iclass 19, count 2 2006.173.05:55:29.95#ibcon#first serial, iclass 19, count 2 2006.173.05:55:29.95#ibcon#enter sib2, iclass 19, count 2 2006.173.05:55:29.95#ibcon#flushed, iclass 19, count 2 2006.173.05:55:29.95#ibcon#about to write, iclass 19, count 2 2006.173.05:55:29.95#ibcon#wrote, iclass 19, count 2 2006.173.05:55:29.95#ibcon#about to read 3, iclass 19, count 2 2006.173.05:55:29.96#ibcon#read 3, iclass 19, count 2 2006.173.05:55:29.96#ibcon#about to read 4, iclass 19, count 2 2006.173.05:55:29.96#ibcon#read 4, iclass 19, count 2 2006.173.05:55:29.96#ibcon#about to read 5, iclass 19, count 2 2006.173.05:55:29.96#ibcon#read 5, iclass 19, count 2 2006.173.05:55:29.97#ibcon#about to read 6, iclass 19, count 2 2006.173.05:55:29.97#ibcon#read 6, iclass 19, count 2 2006.173.05:55:29.97#ibcon#end of sib2, iclass 19, count 2 2006.173.05:55:29.97#ibcon#*mode == 0, iclass 19, count 2 2006.173.05:55:29.97#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.05:55:29.97#ibcon#[27=AT01-04\r\n] 2006.173.05:55:29.97#ibcon#*before write, iclass 19, count 2 2006.173.05:55:29.97#ibcon#enter sib2, iclass 19, count 2 2006.173.05:55:29.97#ibcon#flushed, iclass 19, count 2 2006.173.05:55:29.97#ibcon#about to write, iclass 19, count 2 2006.173.05:55:29.97#ibcon#wrote, iclass 19, count 2 2006.173.05:55:29.97#ibcon#about to read 3, iclass 19, count 2 2006.173.05:55:29.99#ibcon#read 3, iclass 19, count 2 2006.173.05:55:29.99#ibcon#about to read 4, iclass 19, count 2 2006.173.05:55:29.99#ibcon#read 4, iclass 19, count 2 2006.173.05:55:29.99#ibcon#about to read 5, iclass 19, count 2 2006.173.05:55:29.99#ibcon#read 5, iclass 19, count 2 2006.173.05:55:29.99#ibcon#about to read 6, iclass 19, count 2 2006.173.05:55:30.00#ibcon#read 6, iclass 19, count 2 2006.173.05:55:30.00#ibcon#end of sib2, iclass 19, count 2 2006.173.05:55:30.00#ibcon#*after write, iclass 19, count 2 2006.173.05:55:30.00#ibcon#*before return 0, iclass 19, count 2 2006.173.05:55:30.00#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.05:55:30.00#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.05:55:30.00#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.05:55:30.00#ibcon#ireg 7 cls_cnt 0 2006.173.05:55:30.00#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.05:55:30.11#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.05:55:30.11#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.05:55:30.11#ibcon#enter wrdev, iclass 19, count 0 2006.173.05:55:30.11#ibcon#first serial, iclass 19, count 0 2006.173.05:55:30.12#ibcon#enter sib2, iclass 19, count 0 2006.173.05:55:30.12#ibcon#flushed, iclass 19, count 0 2006.173.05:55:30.12#ibcon#about to write, iclass 19, count 0 2006.173.05:55:30.12#ibcon#wrote, iclass 19, count 0 2006.173.05:55:30.12#ibcon#about to read 3, iclass 19, count 0 2006.173.05:55:30.13#ibcon#read 3, iclass 19, count 0 2006.173.05:55:30.13#ibcon#about to read 4, iclass 19, count 0 2006.173.05:55:30.13#ibcon#read 4, iclass 19, count 0 2006.173.05:55:30.13#ibcon#about to read 5, iclass 19, count 0 2006.173.05:55:30.14#ibcon#read 5, iclass 19, count 0 2006.173.05:55:30.14#ibcon#about to read 6, iclass 19, count 0 2006.173.05:55:30.14#ibcon#read 6, iclass 19, count 0 2006.173.05:55:30.14#ibcon#end of sib2, iclass 19, count 0 2006.173.05:55:30.14#ibcon#*mode == 0, iclass 19, count 0 2006.173.05:55:30.14#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.05:55:30.14#ibcon#[27=USB\r\n] 2006.173.05:55:30.14#ibcon#*before write, iclass 19, count 0 2006.173.05:55:30.14#ibcon#enter sib2, iclass 19, count 0 2006.173.05:55:30.14#ibcon#flushed, iclass 19, count 0 2006.173.05:55:30.14#ibcon#about to write, iclass 19, count 0 2006.173.05:55:30.14#ibcon#wrote, iclass 19, count 0 2006.173.05:55:30.14#ibcon#about to read 3, iclass 19, count 0 2006.173.05:55:30.16#ibcon#read 3, iclass 19, count 0 2006.173.05:55:30.16#ibcon#about to read 4, iclass 19, count 0 2006.173.05:55:30.16#ibcon#read 4, iclass 19, count 0 2006.173.05:55:30.16#ibcon#about to read 5, iclass 19, count 0 2006.173.05:55:30.16#ibcon#read 5, iclass 19, count 0 2006.173.05:55:30.17#ibcon#about to read 6, iclass 19, count 0 2006.173.05:55:30.17#ibcon#read 6, iclass 19, count 0 2006.173.05:55:30.17#ibcon#end of sib2, iclass 19, count 0 2006.173.05:55:30.17#ibcon#*after write, iclass 19, count 0 2006.173.05:55:30.17#ibcon#*before return 0, iclass 19, count 0 2006.173.05:55:30.17#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.05:55:30.17#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.05:55:30.17#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.05:55:30.17#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.05:55:30.17$vck44/vblo=2,634.99 2006.173.05:55:30.17#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.05:55:30.17#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.05:55:30.17#ibcon#ireg 17 cls_cnt 0 2006.173.05:55:30.17#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.05:55:30.17#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.05:55:30.17#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.05:55:30.17#ibcon#enter wrdev, iclass 21, count 0 2006.173.05:55:30.17#ibcon#first serial, iclass 21, count 0 2006.173.05:55:30.17#ibcon#enter sib2, iclass 21, count 0 2006.173.05:55:30.17#ibcon#flushed, iclass 21, count 0 2006.173.05:55:30.17#ibcon#about to write, iclass 21, count 0 2006.173.05:55:30.17#ibcon#wrote, iclass 21, count 0 2006.173.05:55:30.17#ibcon#about to read 3, iclass 21, count 0 2006.173.05:55:30.18#ibcon#read 3, iclass 21, count 0 2006.173.05:55:30.18#ibcon#about to read 4, iclass 21, count 0 2006.173.05:55:30.18#ibcon#read 4, iclass 21, count 0 2006.173.05:55:30.18#ibcon#about to read 5, iclass 21, count 0 2006.173.05:55:30.19#ibcon#read 5, iclass 21, count 0 2006.173.05:55:30.19#ibcon#about to read 6, iclass 21, count 0 2006.173.05:55:30.19#ibcon#read 6, iclass 21, count 0 2006.173.05:55:30.19#ibcon#end of sib2, iclass 21, count 0 2006.173.05:55:30.19#ibcon#*mode == 0, iclass 21, count 0 2006.173.05:55:30.19#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.05:55:30.19#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.05:55:30.19#ibcon#*before write, iclass 21, count 0 2006.173.05:55:30.19#ibcon#enter sib2, iclass 21, count 0 2006.173.05:55:30.19#ibcon#flushed, iclass 21, count 0 2006.173.05:55:30.19#ibcon#about to write, iclass 21, count 0 2006.173.05:55:30.19#ibcon#wrote, iclass 21, count 0 2006.173.05:55:30.19#ibcon#about to read 3, iclass 21, count 0 2006.173.05:55:30.22#ibcon#read 3, iclass 21, count 0 2006.173.05:55:30.22#ibcon#about to read 4, iclass 21, count 0 2006.173.05:55:30.22#ibcon#read 4, iclass 21, count 0 2006.173.05:55:30.22#ibcon#about to read 5, iclass 21, count 0 2006.173.05:55:30.22#ibcon#read 5, iclass 21, count 0 2006.173.05:55:30.23#ibcon#about to read 6, iclass 21, count 0 2006.173.05:55:30.23#ibcon#read 6, iclass 21, count 0 2006.173.05:55:30.23#ibcon#end of sib2, iclass 21, count 0 2006.173.05:55:30.23#ibcon#*after write, iclass 21, count 0 2006.173.05:55:30.23#ibcon#*before return 0, iclass 21, count 0 2006.173.05:55:30.23#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.05:55:30.23#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.05:55:30.23#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.05:55:30.23#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.05:55:30.23$vck44/vb=2,4 2006.173.05:55:30.23#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.05:55:30.23#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.05:55:30.23#ibcon#ireg 11 cls_cnt 2 2006.173.05:55:30.23#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.05:55:30.28#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.05:55:30.28#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.05:55:30.28#ibcon#enter wrdev, iclass 23, count 2 2006.173.05:55:30.28#ibcon#first serial, iclass 23, count 2 2006.173.05:55:30.29#ibcon#enter sib2, iclass 23, count 2 2006.173.05:55:30.29#ibcon#flushed, iclass 23, count 2 2006.173.05:55:30.29#ibcon#about to write, iclass 23, count 2 2006.173.05:55:30.29#ibcon#wrote, iclass 23, count 2 2006.173.05:55:30.29#ibcon#about to read 3, iclass 23, count 2 2006.173.05:55:30.30#ibcon#read 3, iclass 23, count 2 2006.173.05:55:30.30#ibcon#about to read 4, iclass 23, count 2 2006.173.05:55:30.30#ibcon#read 4, iclass 23, count 2 2006.173.05:55:30.30#ibcon#about to read 5, iclass 23, count 2 2006.173.05:55:30.31#ibcon#read 5, iclass 23, count 2 2006.173.05:55:30.31#ibcon#about to read 6, iclass 23, count 2 2006.173.05:55:30.31#ibcon#read 6, iclass 23, count 2 2006.173.05:55:30.31#ibcon#end of sib2, iclass 23, count 2 2006.173.05:55:30.31#ibcon#*mode == 0, iclass 23, count 2 2006.173.05:55:30.31#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.05:55:30.31#ibcon#[27=AT02-04\r\n] 2006.173.05:55:30.31#ibcon#*before write, iclass 23, count 2 2006.173.05:55:30.31#ibcon#enter sib2, iclass 23, count 2 2006.173.05:55:30.31#ibcon#flushed, iclass 23, count 2 2006.173.05:55:30.31#ibcon#about to write, iclass 23, count 2 2006.173.05:55:30.31#ibcon#wrote, iclass 23, count 2 2006.173.05:55:30.31#ibcon#about to read 3, iclass 23, count 2 2006.173.05:55:30.33#ibcon#read 3, iclass 23, count 2 2006.173.05:55:30.33#ibcon#about to read 4, iclass 23, count 2 2006.173.05:55:30.33#ibcon#read 4, iclass 23, count 2 2006.173.05:55:30.34#ibcon#about to read 5, iclass 23, count 2 2006.173.05:55:30.34#ibcon#read 5, iclass 23, count 2 2006.173.05:55:30.34#ibcon#about to read 6, iclass 23, count 2 2006.173.05:55:30.34#ibcon#read 6, iclass 23, count 2 2006.173.05:55:30.34#ibcon#end of sib2, iclass 23, count 2 2006.173.05:55:30.34#ibcon#*after write, iclass 23, count 2 2006.173.05:55:30.34#ibcon#*before return 0, iclass 23, count 2 2006.173.05:55:30.34#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.05:55:30.34#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.05:55:30.34#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.05:55:30.34#ibcon#ireg 7 cls_cnt 0 2006.173.05:55:30.34#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.05:55:30.45#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.05:55:30.45#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.05:55:30.45#ibcon#enter wrdev, iclass 23, count 0 2006.173.05:55:30.45#ibcon#first serial, iclass 23, count 0 2006.173.05:55:30.46#ibcon#enter sib2, iclass 23, count 0 2006.173.05:55:30.46#ibcon#flushed, iclass 23, count 0 2006.173.05:55:30.46#ibcon#about to write, iclass 23, count 0 2006.173.05:55:30.46#ibcon#wrote, iclass 23, count 0 2006.173.05:55:30.46#ibcon#about to read 3, iclass 23, count 0 2006.173.05:55:30.47#ibcon#read 3, iclass 23, count 0 2006.173.05:55:30.47#ibcon#about to read 4, iclass 23, count 0 2006.173.05:55:30.48#ibcon#read 4, iclass 23, count 0 2006.173.05:55:30.48#ibcon#about to read 5, iclass 23, count 0 2006.173.05:55:30.48#ibcon#read 5, iclass 23, count 0 2006.173.05:55:30.48#ibcon#about to read 6, iclass 23, count 0 2006.173.05:55:30.48#ibcon#read 6, iclass 23, count 0 2006.173.05:55:30.48#ibcon#end of sib2, iclass 23, count 0 2006.173.05:55:30.48#ibcon#*mode == 0, iclass 23, count 0 2006.173.05:55:30.48#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.05:55:30.48#ibcon#[27=USB\r\n] 2006.173.05:55:30.48#ibcon#*before write, iclass 23, count 0 2006.173.05:55:30.48#ibcon#enter sib2, iclass 23, count 0 2006.173.05:55:30.48#ibcon#flushed, iclass 23, count 0 2006.173.05:55:30.48#ibcon#about to write, iclass 23, count 0 2006.173.05:55:30.48#ibcon#wrote, iclass 23, count 0 2006.173.05:55:30.48#ibcon#about to read 3, iclass 23, count 0 2006.173.05:55:30.50#ibcon#read 3, iclass 23, count 0 2006.173.05:55:30.50#ibcon#about to read 4, iclass 23, count 0 2006.173.05:55:30.50#ibcon#read 4, iclass 23, count 0 2006.173.05:55:30.51#ibcon#about to read 5, iclass 23, count 0 2006.173.05:55:30.51#ibcon#read 5, iclass 23, count 0 2006.173.05:55:30.51#ibcon#about to read 6, iclass 23, count 0 2006.173.05:55:30.51#ibcon#read 6, iclass 23, count 0 2006.173.05:55:30.51#ibcon#end of sib2, iclass 23, count 0 2006.173.05:55:30.51#ibcon#*after write, iclass 23, count 0 2006.173.05:55:30.51#ibcon#*before return 0, iclass 23, count 0 2006.173.05:55:30.51#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.05:55:30.51#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.05:55:30.51#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.05:55:30.51#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.05:55:30.51$vck44/vblo=3,649.99 2006.173.05:55:30.51#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.05:55:30.51#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.05:55:30.51#ibcon#ireg 17 cls_cnt 0 2006.173.05:55:30.51#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.05:55:30.51#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.05:55:30.51#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.05:55:30.51#ibcon#enter wrdev, iclass 25, count 0 2006.173.05:55:30.51#ibcon#first serial, iclass 25, count 0 2006.173.05:55:30.51#ibcon#enter sib2, iclass 25, count 0 2006.173.05:55:30.51#ibcon#flushed, iclass 25, count 0 2006.173.05:55:30.51#ibcon#about to write, iclass 25, count 0 2006.173.05:55:30.51#ibcon#wrote, iclass 25, count 0 2006.173.05:55:30.51#ibcon#about to read 3, iclass 25, count 0 2006.173.05:55:30.52#ibcon#read 3, iclass 25, count 0 2006.173.05:55:30.52#ibcon#about to read 4, iclass 25, count 0 2006.173.05:55:30.52#ibcon#read 4, iclass 25, count 0 2006.173.05:55:30.52#ibcon#about to read 5, iclass 25, count 0 2006.173.05:55:30.52#ibcon#read 5, iclass 25, count 0 2006.173.05:55:30.52#ibcon#about to read 6, iclass 25, count 0 2006.173.05:55:30.53#ibcon#read 6, iclass 25, count 0 2006.173.05:55:30.53#ibcon#end of sib2, iclass 25, count 0 2006.173.05:55:30.53#ibcon#*mode == 0, iclass 25, count 0 2006.173.05:55:30.53#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.05:55:30.53#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.05:55:30.53#ibcon#*before write, iclass 25, count 0 2006.173.05:55:30.53#ibcon#enter sib2, iclass 25, count 0 2006.173.05:55:30.53#ibcon#flushed, iclass 25, count 0 2006.173.05:55:30.53#ibcon#about to write, iclass 25, count 0 2006.173.05:55:30.53#ibcon#wrote, iclass 25, count 0 2006.173.05:55:30.53#ibcon#about to read 3, iclass 25, count 0 2006.173.05:55:30.56#ibcon#read 3, iclass 25, count 0 2006.173.05:55:30.56#ibcon#about to read 4, iclass 25, count 0 2006.173.05:55:30.57#ibcon#read 4, iclass 25, count 0 2006.173.05:55:30.57#ibcon#about to read 5, iclass 25, count 0 2006.173.05:55:30.57#ibcon#read 5, iclass 25, count 0 2006.173.05:55:30.57#ibcon#about to read 6, iclass 25, count 0 2006.173.05:55:30.57#ibcon#read 6, iclass 25, count 0 2006.173.05:55:30.57#ibcon#end of sib2, iclass 25, count 0 2006.173.05:55:30.57#ibcon#*after write, iclass 25, count 0 2006.173.05:55:30.57#ibcon#*before return 0, iclass 25, count 0 2006.173.05:55:30.57#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.05:55:30.57#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.05:55:30.57#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.05:55:30.57#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.05:55:30.57$vck44/vb=3,4 2006.173.05:55:30.57#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.05:55:30.57#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.05:55:30.57#ibcon#ireg 11 cls_cnt 2 2006.173.05:55:30.57#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.05:55:30.62#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.05:55:30.62#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.05:55:30.63#ibcon#enter wrdev, iclass 27, count 2 2006.173.05:55:30.63#ibcon#first serial, iclass 27, count 2 2006.173.05:55:30.63#ibcon#enter sib2, iclass 27, count 2 2006.173.05:55:30.63#ibcon#flushed, iclass 27, count 2 2006.173.05:55:30.63#ibcon#about to write, iclass 27, count 2 2006.173.05:55:30.63#ibcon#wrote, iclass 27, count 2 2006.173.05:55:30.63#ibcon#about to read 3, iclass 27, count 2 2006.173.05:55:30.64#ibcon#read 3, iclass 27, count 2 2006.173.05:55:30.65#ibcon#about to read 4, iclass 27, count 2 2006.173.05:55:30.65#ibcon#read 4, iclass 27, count 2 2006.173.05:55:30.65#ibcon#about to read 5, iclass 27, count 2 2006.173.05:55:30.65#ibcon#read 5, iclass 27, count 2 2006.173.05:55:30.65#ibcon#about to read 6, iclass 27, count 2 2006.173.05:55:30.65#ibcon#read 6, iclass 27, count 2 2006.173.05:55:30.65#ibcon#end of sib2, iclass 27, count 2 2006.173.05:55:30.65#ibcon#*mode == 0, iclass 27, count 2 2006.173.05:55:30.65#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.05:55:30.65#ibcon#[27=AT03-04\r\n] 2006.173.05:55:30.65#ibcon#*before write, iclass 27, count 2 2006.173.05:55:30.65#ibcon#enter sib2, iclass 27, count 2 2006.173.05:55:30.65#ibcon#flushed, iclass 27, count 2 2006.173.05:55:30.65#ibcon#about to write, iclass 27, count 2 2006.173.05:55:30.65#ibcon#wrote, iclass 27, count 2 2006.173.05:55:30.65#ibcon#about to read 3, iclass 27, count 2 2006.173.05:55:30.67#ibcon#read 3, iclass 27, count 2 2006.173.05:55:30.67#ibcon#about to read 4, iclass 27, count 2 2006.173.05:55:30.68#ibcon#read 4, iclass 27, count 2 2006.173.05:55:30.68#ibcon#about to read 5, iclass 27, count 2 2006.173.05:55:30.68#ibcon#read 5, iclass 27, count 2 2006.173.05:55:30.68#ibcon#about to read 6, iclass 27, count 2 2006.173.05:55:30.68#ibcon#read 6, iclass 27, count 2 2006.173.05:55:30.68#ibcon#end of sib2, iclass 27, count 2 2006.173.05:55:30.68#ibcon#*after write, iclass 27, count 2 2006.173.05:55:30.68#ibcon#*before return 0, iclass 27, count 2 2006.173.05:55:30.68#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.05:55:30.68#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.05:55:30.68#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.05:55:30.68#ibcon#ireg 7 cls_cnt 0 2006.173.05:55:30.68#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.05:55:30.79#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.05:55:30.79#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.05:55:30.80#ibcon#enter wrdev, iclass 27, count 0 2006.173.05:55:30.80#ibcon#first serial, iclass 27, count 0 2006.173.05:55:30.80#ibcon#enter sib2, iclass 27, count 0 2006.173.05:55:30.80#ibcon#flushed, iclass 27, count 0 2006.173.05:55:30.80#ibcon#about to write, iclass 27, count 0 2006.173.05:55:30.80#ibcon#wrote, iclass 27, count 0 2006.173.05:55:30.80#ibcon#about to read 3, iclass 27, count 0 2006.173.05:55:30.81#ibcon#read 3, iclass 27, count 0 2006.173.05:55:30.81#ibcon#about to read 4, iclass 27, count 0 2006.173.05:55:30.82#ibcon#read 4, iclass 27, count 0 2006.173.05:55:30.82#ibcon#about to read 5, iclass 27, count 0 2006.173.05:55:30.82#ibcon#read 5, iclass 27, count 0 2006.173.05:55:30.82#ibcon#about to read 6, iclass 27, count 0 2006.173.05:55:30.82#ibcon#read 6, iclass 27, count 0 2006.173.05:55:30.82#ibcon#end of sib2, iclass 27, count 0 2006.173.05:55:30.82#ibcon#*mode == 0, iclass 27, count 0 2006.173.05:55:30.82#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.05:55:30.82#ibcon#[27=USB\r\n] 2006.173.05:55:30.82#ibcon#*before write, iclass 27, count 0 2006.173.05:55:30.82#ibcon#enter sib2, iclass 27, count 0 2006.173.05:55:30.82#ibcon#flushed, iclass 27, count 0 2006.173.05:55:30.82#ibcon#about to write, iclass 27, count 0 2006.173.05:55:30.82#ibcon#wrote, iclass 27, count 0 2006.173.05:55:30.82#ibcon#about to read 3, iclass 27, count 0 2006.173.05:55:30.84#ibcon#read 3, iclass 27, count 0 2006.173.05:55:30.84#ibcon#about to read 4, iclass 27, count 0 2006.173.05:55:30.84#ibcon#read 4, iclass 27, count 0 2006.173.05:55:30.85#ibcon#about to read 5, iclass 27, count 0 2006.173.05:55:30.85#ibcon#read 5, iclass 27, count 0 2006.173.05:55:30.85#ibcon#about to read 6, iclass 27, count 0 2006.173.05:55:30.85#ibcon#read 6, iclass 27, count 0 2006.173.05:55:30.85#ibcon#end of sib2, iclass 27, count 0 2006.173.05:55:30.85#ibcon#*after write, iclass 27, count 0 2006.173.05:55:30.85#ibcon#*before return 0, iclass 27, count 0 2006.173.05:55:30.85#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.05:55:30.85#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.05:55:30.85#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.05:55:30.85#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.05:55:30.85$vck44/vblo=4,679.99 2006.173.05:55:30.85#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.05:55:30.85#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.05:55:30.85#ibcon#ireg 17 cls_cnt 0 2006.173.05:55:30.85#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.05:55:30.85#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.05:55:30.85#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.05:55:30.85#ibcon#enter wrdev, iclass 29, count 0 2006.173.05:55:30.85#ibcon#first serial, iclass 29, count 0 2006.173.05:55:30.85#ibcon#enter sib2, iclass 29, count 0 2006.173.05:55:30.85#ibcon#flushed, iclass 29, count 0 2006.173.05:55:30.85#ibcon#about to write, iclass 29, count 0 2006.173.05:55:30.85#ibcon#wrote, iclass 29, count 0 2006.173.05:55:30.85#ibcon#about to read 3, iclass 29, count 0 2006.173.05:55:30.86#ibcon#read 3, iclass 29, count 0 2006.173.05:55:30.86#ibcon#about to read 4, iclass 29, count 0 2006.173.05:55:30.86#ibcon#read 4, iclass 29, count 0 2006.173.05:55:30.87#ibcon#about to read 5, iclass 29, count 0 2006.173.05:55:30.87#ibcon#read 5, iclass 29, count 0 2006.173.05:55:30.87#ibcon#about to read 6, iclass 29, count 0 2006.173.05:55:30.87#ibcon#read 6, iclass 29, count 0 2006.173.05:55:30.87#ibcon#end of sib2, iclass 29, count 0 2006.173.05:55:30.87#ibcon#*mode == 0, iclass 29, count 0 2006.173.05:55:30.87#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.05:55:30.87#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.05:55:30.87#ibcon#*before write, iclass 29, count 0 2006.173.05:55:30.87#ibcon#enter sib2, iclass 29, count 0 2006.173.05:55:30.87#ibcon#flushed, iclass 29, count 0 2006.173.05:55:30.87#ibcon#about to write, iclass 29, count 0 2006.173.05:55:30.87#ibcon#wrote, iclass 29, count 0 2006.173.05:55:30.87#ibcon#about to read 3, iclass 29, count 0 2006.173.05:55:30.90#ibcon#read 3, iclass 29, count 0 2006.173.05:55:30.90#ibcon#about to read 4, iclass 29, count 0 2006.173.05:55:30.90#ibcon#read 4, iclass 29, count 0 2006.173.05:55:30.90#ibcon#about to read 5, iclass 29, count 0 2006.173.05:55:30.91#ibcon#read 5, iclass 29, count 0 2006.173.05:55:30.91#ibcon#about to read 6, iclass 29, count 0 2006.173.05:55:30.91#ibcon#read 6, iclass 29, count 0 2006.173.05:55:30.91#ibcon#end of sib2, iclass 29, count 0 2006.173.05:55:30.91#ibcon#*after write, iclass 29, count 0 2006.173.05:55:30.91#ibcon#*before return 0, iclass 29, count 0 2006.173.05:55:30.91#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.05:55:30.91#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.05:55:30.91#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.05:55:30.91#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.05:55:30.91$vck44/vb=4,4 2006.173.05:55:30.91#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.05:55:30.91#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.05:55:30.91#ibcon#ireg 11 cls_cnt 2 2006.173.05:55:30.91#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.05:55:30.96#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.05:55:30.96#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.05:55:30.96#ibcon#enter wrdev, iclass 31, count 2 2006.173.05:55:30.96#ibcon#first serial, iclass 31, count 2 2006.173.05:55:30.96#ibcon#enter sib2, iclass 31, count 2 2006.173.05:55:30.97#ibcon#flushed, iclass 31, count 2 2006.173.05:55:30.97#ibcon#about to write, iclass 31, count 2 2006.173.05:55:30.97#ibcon#wrote, iclass 31, count 2 2006.173.05:55:30.97#ibcon#about to read 3, iclass 31, count 2 2006.173.05:55:30.98#ibcon#read 3, iclass 31, count 2 2006.173.05:55:30.98#ibcon#about to read 4, iclass 31, count 2 2006.173.05:55:30.98#ibcon#read 4, iclass 31, count 2 2006.173.05:55:30.98#ibcon#about to read 5, iclass 31, count 2 2006.173.05:55:30.99#ibcon#read 5, iclass 31, count 2 2006.173.05:55:30.99#ibcon#about to read 6, iclass 31, count 2 2006.173.05:55:30.99#ibcon#read 6, iclass 31, count 2 2006.173.05:55:30.99#ibcon#end of sib2, iclass 31, count 2 2006.173.05:55:30.99#ibcon#*mode == 0, iclass 31, count 2 2006.173.05:55:30.99#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.05:55:30.99#ibcon#[27=AT04-04\r\n] 2006.173.05:55:30.99#ibcon#*before write, iclass 31, count 2 2006.173.05:55:30.99#ibcon#enter sib2, iclass 31, count 2 2006.173.05:55:30.99#ibcon#flushed, iclass 31, count 2 2006.173.05:55:30.99#ibcon#about to write, iclass 31, count 2 2006.173.05:55:30.99#ibcon#wrote, iclass 31, count 2 2006.173.05:55:30.99#ibcon#about to read 3, iclass 31, count 2 2006.173.05:55:31.01#ibcon#read 3, iclass 31, count 2 2006.173.05:55:31.01#ibcon#about to read 4, iclass 31, count 2 2006.173.05:55:31.02#ibcon#read 4, iclass 31, count 2 2006.173.05:55:31.02#ibcon#about to read 5, iclass 31, count 2 2006.173.05:55:31.02#ibcon#read 5, iclass 31, count 2 2006.173.05:55:31.02#ibcon#about to read 6, iclass 31, count 2 2006.173.05:55:31.02#ibcon#read 6, iclass 31, count 2 2006.173.05:55:31.02#ibcon#end of sib2, iclass 31, count 2 2006.173.05:55:31.02#ibcon#*after write, iclass 31, count 2 2006.173.05:55:31.02#ibcon#*before return 0, iclass 31, count 2 2006.173.05:55:31.02#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.05:55:31.02#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.05:55:31.02#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.05:55:31.02#ibcon#ireg 7 cls_cnt 0 2006.173.05:55:31.02#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.05:55:31.13#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.05:55:31.13#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.05:55:31.13#ibcon#enter wrdev, iclass 31, count 0 2006.173.05:55:31.13#ibcon#first serial, iclass 31, count 0 2006.173.05:55:31.14#ibcon#enter sib2, iclass 31, count 0 2006.173.05:55:31.14#ibcon#flushed, iclass 31, count 0 2006.173.05:55:31.14#ibcon#about to write, iclass 31, count 0 2006.173.05:55:31.14#ibcon#wrote, iclass 31, count 0 2006.173.05:55:31.14#ibcon#about to read 3, iclass 31, count 0 2006.173.05:55:31.15#ibcon#read 3, iclass 31, count 0 2006.173.05:55:31.15#ibcon#about to read 4, iclass 31, count 0 2006.173.05:55:31.15#ibcon#read 4, iclass 31, count 0 2006.173.05:55:31.15#ibcon#about to read 5, iclass 31, count 0 2006.173.05:55:31.15#ibcon#read 5, iclass 31, count 0 2006.173.05:55:31.16#ibcon#about to read 6, iclass 31, count 0 2006.173.05:55:31.16#ibcon#read 6, iclass 31, count 0 2006.173.05:55:31.16#ibcon#end of sib2, iclass 31, count 0 2006.173.05:55:31.16#ibcon#*mode == 0, iclass 31, count 0 2006.173.05:55:31.16#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.05:55:31.16#ibcon#[27=USB\r\n] 2006.173.05:55:31.16#ibcon#*before write, iclass 31, count 0 2006.173.05:55:31.16#ibcon#enter sib2, iclass 31, count 0 2006.173.05:55:31.16#ibcon#flushed, iclass 31, count 0 2006.173.05:55:31.16#ibcon#about to write, iclass 31, count 0 2006.173.05:55:31.16#ibcon#wrote, iclass 31, count 0 2006.173.05:55:31.16#ibcon#about to read 3, iclass 31, count 0 2006.173.05:55:31.18#ibcon#read 3, iclass 31, count 0 2006.173.05:55:31.18#ibcon#about to read 4, iclass 31, count 0 2006.173.05:55:31.18#ibcon#read 4, iclass 31, count 0 2006.173.05:55:31.18#ibcon#about to read 5, iclass 31, count 0 2006.173.05:55:31.18#ibcon#read 5, iclass 31, count 0 2006.173.05:55:31.19#ibcon#about to read 6, iclass 31, count 0 2006.173.05:55:31.19#ibcon#read 6, iclass 31, count 0 2006.173.05:55:31.19#ibcon#end of sib2, iclass 31, count 0 2006.173.05:55:31.19#ibcon#*after write, iclass 31, count 0 2006.173.05:55:31.19#ibcon#*before return 0, iclass 31, count 0 2006.173.05:55:31.19#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.05:55:31.19#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.05:55:31.19#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.05:55:31.19#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.05:55:31.19$vck44/vblo=5,709.99 2006.173.05:55:31.19#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.05:55:31.19#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.05:55:31.19#ibcon#ireg 17 cls_cnt 0 2006.173.05:55:31.19#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.05:55:31.19#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.05:55:31.19#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.05:55:31.19#ibcon#enter wrdev, iclass 33, count 0 2006.173.05:55:31.19#ibcon#first serial, iclass 33, count 0 2006.173.05:55:31.19#ibcon#enter sib2, iclass 33, count 0 2006.173.05:55:31.19#ibcon#flushed, iclass 33, count 0 2006.173.05:55:31.19#ibcon#about to write, iclass 33, count 0 2006.173.05:55:31.19#ibcon#wrote, iclass 33, count 0 2006.173.05:55:31.19#ibcon#about to read 3, iclass 33, count 0 2006.173.05:55:31.20#ibcon#read 3, iclass 33, count 0 2006.173.05:55:31.20#ibcon#about to read 4, iclass 33, count 0 2006.173.05:55:31.20#ibcon#read 4, iclass 33, count 0 2006.173.05:55:31.20#ibcon#about to read 5, iclass 33, count 0 2006.173.05:55:31.20#ibcon#read 5, iclass 33, count 0 2006.173.05:55:31.20#ibcon#about to read 6, iclass 33, count 0 2006.173.05:55:31.21#ibcon#read 6, iclass 33, count 0 2006.173.05:55:31.21#ibcon#end of sib2, iclass 33, count 0 2006.173.05:55:31.21#ibcon#*mode == 0, iclass 33, count 0 2006.173.05:55:31.21#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.05:55:31.21#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.05:55:31.21#ibcon#*before write, iclass 33, count 0 2006.173.05:55:31.21#ibcon#enter sib2, iclass 33, count 0 2006.173.05:55:31.21#ibcon#flushed, iclass 33, count 0 2006.173.05:55:31.21#ibcon#about to write, iclass 33, count 0 2006.173.05:55:31.21#ibcon#wrote, iclass 33, count 0 2006.173.05:55:31.21#ibcon#about to read 3, iclass 33, count 0 2006.173.05:55:31.24#ibcon#read 3, iclass 33, count 0 2006.173.05:55:31.24#ibcon#about to read 4, iclass 33, count 0 2006.173.05:55:31.24#ibcon#read 4, iclass 33, count 0 2006.173.05:55:31.24#ibcon#about to read 5, iclass 33, count 0 2006.173.05:55:31.24#ibcon#read 5, iclass 33, count 0 2006.173.05:55:31.25#ibcon#about to read 6, iclass 33, count 0 2006.173.05:55:31.25#ibcon#read 6, iclass 33, count 0 2006.173.05:55:31.25#ibcon#end of sib2, iclass 33, count 0 2006.173.05:55:31.25#ibcon#*after write, iclass 33, count 0 2006.173.05:55:31.25#ibcon#*before return 0, iclass 33, count 0 2006.173.05:55:31.25#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.05:55:31.25#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.05:55:31.25#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.05:55:31.25#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.05:55:31.25$vck44/vb=5,4 2006.173.05:55:31.25#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.05:55:31.25#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.05:55:31.25#ibcon#ireg 11 cls_cnt 2 2006.173.05:55:31.25#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.05:55:31.30#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.05:55:31.30#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.05:55:31.30#ibcon#enter wrdev, iclass 35, count 2 2006.173.05:55:31.30#ibcon#first serial, iclass 35, count 2 2006.173.05:55:31.30#ibcon#enter sib2, iclass 35, count 2 2006.173.05:55:31.31#ibcon#flushed, iclass 35, count 2 2006.173.05:55:31.31#ibcon#about to write, iclass 35, count 2 2006.173.05:55:31.31#ibcon#wrote, iclass 35, count 2 2006.173.05:55:31.31#ibcon#about to read 3, iclass 35, count 2 2006.173.05:55:31.32#ibcon#read 3, iclass 35, count 2 2006.173.05:55:31.32#ibcon#about to read 4, iclass 35, count 2 2006.173.05:55:31.32#ibcon#read 4, iclass 35, count 2 2006.173.05:55:31.32#ibcon#about to read 5, iclass 35, count 2 2006.173.05:55:31.32#ibcon#read 5, iclass 35, count 2 2006.173.05:55:31.32#ibcon#about to read 6, iclass 35, count 2 2006.173.05:55:31.32#ibcon#read 6, iclass 35, count 2 2006.173.05:55:31.33#ibcon#end of sib2, iclass 35, count 2 2006.173.05:55:31.33#ibcon#*mode == 0, iclass 35, count 2 2006.173.05:55:31.33#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.05:55:31.33#ibcon#[27=AT05-04\r\n] 2006.173.05:55:31.33#ibcon#*before write, iclass 35, count 2 2006.173.05:55:31.33#ibcon#enter sib2, iclass 35, count 2 2006.173.05:55:31.33#ibcon#flushed, iclass 35, count 2 2006.173.05:55:31.33#ibcon#about to write, iclass 35, count 2 2006.173.05:55:31.33#ibcon#wrote, iclass 35, count 2 2006.173.05:55:31.33#ibcon#about to read 3, iclass 35, count 2 2006.173.05:55:31.35#ibcon#read 3, iclass 35, count 2 2006.173.05:55:31.35#ibcon#about to read 4, iclass 35, count 2 2006.173.05:55:31.35#ibcon#read 4, iclass 35, count 2 2006.173.05:55:31.35#ibcon#about to read 5, iclass 35, count 2 2006.173.05:55:31.35#ibcon#read 5, iclass 35, count 2 2006.173.05:55:31.36#ibcon#about to read 6, iclass 35, count 2 2006.173.05:55:31.36#ibcon#read 6, iclass 35, count 2 2006.173.05:55:31.36#ibcon#end of sib2, iclass 35, count 2 2006.173.05:55:31.36#ibcon#*after write, iclass 35, count 2 2006.173.05:55:31.36#ibcon#*before return 0, iclass 35, count 2 2006.173.05:55:31.36#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.05:55:31.36#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.05:55:31.36#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.05:55:31.36#ibcon#ireg 7 cls_cnt 0 2006.173.05:55:31.36#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.05:55:31.47#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.05:55:31.47#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.05:55:31.47#ibcon#enter wrdev, iclass 35, count 0 2006.173.05:55:31.47#ibcon#first serial, iclass 35, count 0 2006.173.05:55:31.47#ibcon#enter sib2, iclass 35, count 0 2006.173.05:55:31.48#ibcon#flushed, iclass 35, count 0 2006.173.05:55:31.48#ibcon#about to write, iclass 35, count 0 2006.173.05:55:31.48#ibcon#wrote, iclass 35, count 0 2006.173.05:55:31.48#ibcon#about to read 3, iclass 35, count 0 2006.173.05:55:31.49#ibcon#read 3, iclass 35, count 0 2006.173.05:55:31.49#ibcon#about to read 4, iclass 35, count 0 2006.173.05:55:31.49#ibcon#read 4, iclass 35, count 0 2006.173.05:55:31.49#ibcon#about to read 5, iclass 35, count 0 2006.173.05:55:31.49#ibcon#read 5, iclass 35, count 0 2006.173.05:55:31.49#ibcon#about to read 6, iclass 35, count 0 2006.173.05:55:31.50#ibcon#read 6, iclass 35, count 0 2006.173.05:55:31.50#ibcon#end of sib2, iclass 35, count 0 2006.173.05:55:31.50#ibcon#*mode == 0, iclass 35, count 0 2006.173.05:55:31.50#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.05:55:31.50#ibcon#[27=USB\r\n] 2006.173.05:55:31.50#ibcon#*before write, iclass 35, count 0 2006.173.05:55:31.50#ibcon#enter sib2, iclass 35, count 0 2006.173.05:55:31.50#ibcon#flushed, iclass 35, count 0 2006.173.05:55:31.50#ibcon#about to write, iclass 35, count 0 2006.173.05:55:31.50#ibcon#wrote, iclass 35, count 0 2006.173.05:55:31.50#ibcon#about to read 3, iclass 35, count 0 2006.173.05:55:31.52#ibcon#read 3, iclass 35, count 0 2006.173.05:55:31.52#ibcon#about to read 4, iclass 35, count 0 2006.173.05:55:31.52#ibcon#read 4, iclass 35, count 0 2006.173.05:55:31.52#ibcon#about to read 5, iclass 35, count 0 2006.173.05:55:31.53#ibcon#read 5, iclass 35, count 0 2006.173.05:55:31.53#ibcon#about to read 6, iclass 35, count 0 2006.173.05:55:31.53#ibcon#read 6, iclass 35, count 0 2006.173.05:55:31.53#ibcon#end of sib2, iclass 35, count 0 2006.173.05:55:31.53#ibcon#*after write, iclass 35, count 0 2006.173.05:55:31.53#ibcon#*before return 0, iclass 35, count 0 2006.173.05:55:31.53#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.05:55:31.53#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.05:55:31.53#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.05:55:31.53#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.05:55:31.53$vck44/vblo=6,719.99 2006.173.05:55:31.53#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.05:55:31.53#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.05:55:31.53#ibcon#ireg 17 cls_cnt 0 2006.173.05:55:31.53#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.05:55:31.53#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.05:55:31.53#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.05:55:31.53#ibcon#enter wrdev, iclass 37, count 0 2006.173.05:55:31.53#ibcon#first serial, iclass 37, count 0 2006.173.05:55:31.53#ibcon#enter sib2, iclass 37, count 0 2006.173.05:55:31.53#ibcon#flushed, iclass 37, count 0 2006.173.05:55:31.53#ibcon#about to write, iclass 37, count 0 2006.173.05:55:31.53#ibcon#wrote, iclass 37, count 0 2006.173.05:55:31.53#ibcon#about to read 3, iclass 37, count 0 2006.173.05:55:31.54#ibcon#read 3, iclass 37, count 0 2006.173.05:55:31.54#ibcon#about to read 4, iclass 37, count 0 2006.173.05:55:31.54#ibcon#read 4, iclass 37, count 0 2006.173.05:55:31.55#ibcon#about to read 5, iclass 37, count 0 2006.173.05:55:31.55#ibcon#read 5, iclass 37, count 0 2006.173.05:55:31.55#ibcon#about to read 6, iclass 37, count 0 2006.173.05:55:31.55#ibcon#read 6, iclass 37, count 0 2006.173.05:55:31.55#ibcon#end of sib2, iclass 37, count 0 2006.173.05:55:31.55#ibcon#*mode == 0, iclass 37, count 0 2006.173.05:55:31.55#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.05:55:31.55#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.05:55:31.55#ibcon#*before write, iclass 37, count 0 2006.173.05:55:31.55#ibcon#enter sib2, iclass 37, count 0 2006.173.05:55:31.55#ibcon#flushed, iclass 37, count 0 2006.173.05:55:31.55#ibcon#about to write, iclass 37, count 0 2006.173.05:55:31.55#ibcon#wrote, iclass 37, count 0 2006.173.05:55:31.55#ibcon#about to read 3, iclass 37, count 0 2006.173.05:55:31.58#ibcon#read 3, iclass 37, count 0 2006.173.05:55:31.58#ibcon#about to read 4, iclass 37, count 0 2006.173.05:55:31.58#ibcon#read 4, iclass 37, count 0 2006.173.05:55:31.58#ibcon#about to read 5, iclass 37, count 0 2006.173.05:55:31.58#ibcon#read 5, iclass 37, count 0 2006.173.05:55:31.58#ibcon#about to read 6, iclass 37, count 0 2006.173.05:55:31.59#ibcon#read 6, iclass 37, count 0 2006.173.05:55:31.59#ibcon#end of sib2, iclass 37, count 0 2006.173.05:55:31.59#ibcon#*after write, iclass 37, count 0 2006.173.05:55:31.59#ibcon#*before return 0, iclass 37, count 0 2006.173.05:55:31.59#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.05:55:31.59#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.05:55:31.59#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.05:55:31.59#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.05:55:31.59$vck44/vb=6,4 2006.173.05:55:31.59#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.05:55:31.59#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.05:55:31.59#ibcon#ireg 11 cls_cnt 2 2006.173.05:55:31.59#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.05:55:31.64#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.05:55:31.64#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.05:55:31.64#ibcon#enter wrdev, iclass 39, count 2 2006.173.05:55:31.64#ibcon#first serial, iclass 39, count 2 2006.173.05:55:31.64#ibcon#enter sib2, iclass 39, count 2 2006.173.05:55:31.65#ibcon#flushed, iclass 39, count 2 2006.173.05:55:31.65#ibcon#about to write, iclass 39, count 2 2006.173.05:55:31.65#ibcon#wrote, iclass 39, count 2 2006.173.05:55:31.65#ibcon#about to read 3, iclass 39, count 2 2006.173.05:55:31.66#ibcon#read 3, iclass 39, count 2 2006.173.05:55:31.66#ibcon#about to read 4, iclass 39, count 2 2006.173.05:55:31.67#ibcon#read 4, iclass 39, count 2 2006.173.05:55:31.67#ibcon#about to read 5, iclass 39, count 2 2006.173.05:55:31.67#ibcon#read 5, iclass 39, count 2 2006.173.05:55:31.67#ibcon#about to read 6, iclass 39, count 2 2006.173.05:55:31.67#ibcon#read 6, iclass 39, count 2 2006.173.05:55:31.67#ibcon#end of sib2, iclass 39, count 2 2006.173.05:55:31.67#ibcon#*mode == 0, iclass 39, count 2 2006.173.05:55:31.67#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.05:55:31.67#ibcon#[27=AT06-04\r\n] 2006.173.05:55:31.67#ibcon#*before write, iclass 39, count 2 2006.173.05:55:31.67#ibcon#enter sib2, iclass 39, count 2 2006.173.05:55:31.67#ibcon#flushed, iclass 39, count 2 2006.173.05:55:31.67#ibcon#about to write, iclass 39, count 2 2006.173.05:55:31.67#ibcon#wrote, iclass 39, count 2 2006.173.05:55:31.67#ibcon#about to read 3, iclass 39, count 2 2006.173.05:55:31.69#ibcon#read 3, iclass 39, count 2 2006.173.05:55:31.69#ibcon#about to read 4, iclass 39, count 2 2006.173.05:55:31.69#ibcon#read 4, iclass 39, count 2 2006.173.05:55:31.69#ibcon#about to read 5, iclass 39, count 2 2006.173.05:55:31.69#ibcon#read 5, iclass 39, count 2 2006.173.05:55:31.69#ibcon#about to read 6, iclass 39, count 2 2006.173.05:55:31.70#ibcon#read 6, iclass 39, count 2 2006.173.05:55:31.70#ibcon#end of sib2, iclass 39, count 2 2006.173.05:55:31.70#ibcon#*after write, iclass 39, count 2 2006.173.05:55:31.70#ibcon#*before return 0, iclass 39, count 2 2006.173.05:55:31.70#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.05:55:31.70#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.05:55:31.70#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.05:55:31.70#ibcon#ireg 7 cls_cnt 0 2006.173.05:55:31.70#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.05:55:31.81#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.05:55:31.81#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.05:55:31.81#ibcon#enter wrdev, iclass 39, count 0 2006.173.05:55:31.81#ibcon#first serial, iclass 39, count 0 2006.173.05:55:31.82#ibcon#enter sib2, iclass 39, count 0 2006.173.05:55:31.82#ibcon#flushed, iclass 39, count 0 2006.173.05:55:31.82#ibcon#about to write, iclass 39, count 0 2006.173.05:55:31.82#ibcon#wrote, iclass 39, count 0 2006.173.05:55:31.82#ibcon#about to read 3, iclass 39, count 0 2006.173.05:55:31.83#ibcon#read 3, iclass 39, count 0 2006.173.05:55:31.83#ibcon#about to read 4, iclass 39, count 0 2006.173.05:55:31.83#ibcon#read 4, iclass 39, count 0 2006.173.05:55:31.84#ibcon#about to read 5, iclass 39, count 0 2006.173.05:55:31.84#ibcon#read 5, iclass 39, count 0 2006.173.05:55:31.84#ibcon#about to read 6, iclass 39, count 0 2006.173.05:55:31.84#ibcon#read 6, iclass 39, count 0 2006.173.05:55:31.84#ibcon#end of sib2, iclass 39, count 0 2006.173.05:55:31.84#ibcon#*mode == 0, iclass 39, count 0 2006.173.05:55:31.84#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.05:55:31.84#ibcon#[27=USB\r\n] 2006.173.05:55:31.84#ibcon#*before write, iclass 39, count 0 2006.173.05:55:31.84#ibcon#enter sib2, iclass 39, count 0 2006.173.05:55:31.84#ibcon#flushed, iclass 39, count 0 2006.173.05:55:31.84#ibcon#about to write, iclass 39, count 0 2006.173.05:55:31.84#ibcon#wrote, iclass 39, count 0 2006.173.05:55:31.84#ibcon#about to read 3, iclass 39, count 0 2006.173.05:55:31.86#ibcon#read 3, iclass 39, count 0 2006.173.05:55:31.86#ibcon#about to read 4, iclass 39, count 0 2006.173.05:55:31.86#ibcon#read 4, iclass 39, count 0 2006.173.05:55:31.87#ibcon#about to read 5, iclass 39, count 0 2006.173.05:55:31.87#ibcon#read 5, iclass 39, count 0 2006.173.05:55:31.87#ibcon#about to read 6, iclass 39, count 0 2006.173.05:55:31.87#ibcon#read 6, iclass 39, count 0 2006.173.05:55:31.87#ibcon#end of sib2, iclass 39, count 0 2006.173.05:55:31.87#ibcon#*after write, iclass 39, count 0 2006.173.05:55:31.87#ibcon#*before return 0, iclass 39, count 0 2006.173.05:55:31.87#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.05:55:31.87#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.05:55:31.87#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.05:55:31.87#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.05:55:31.87$vck44/vblo=7,734.99 2006.173.05:55:31.87#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.05:55:31.87#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.05:55:31.87#ibcon#ireg 17 cls_cnt 0 2006.173.05:55:31.87#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.05:55:31.87#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.05:55:31.87#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.05:55:31.87#ibcon#enter wrdev, iclass 3, count 0 2006.173.05:55:31.87#ibcon#first serial, iclass 3, count 0 2006.173.05:55:31.87#ibcon#enter sib2, iclass 3, count 0 2006.173.05:55:31.87#ibcon#flushed, iclass 3, count 0 2006.173.05:55:31.87#ibcon#about to write, iclass 3, count 0 2006.173.05:55:31.87#ibcon#wrote, iclass 3, count 0 2006.173.05:55:31.87#ibcon#about to read 3, iclass 3, count 0 2006.173.05:55:31.88#ibcon#read 3, iclass 3, count 0 2006.173.05:55:31.88#ibcon#about to read 4, iclass 3, count 0 2006.173.05:55:31.89#ibcon#read 4, iclass 3, count 0 2006.173.05:55:31.89#ibcon#about to read 5, iclass 3, count 0 2006.173.05:55:31.89#ibcon#read 5, iclass 3, count 0 2006.173.05:55:31.89#ibcon#about to read 6, iclass 3, count 0 2006.173.05:55:31.89#ibcon#read 6, iclass 3, count 0 2006.173.05:55:31.89#ibcon#end of sib2, iclass 3, count 0 2006.173.05:55:31.89#ibcon#*mode == 0, iclass 3, count 0 2006.173.05:55:31.89#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.05:55:31.89#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.05:55:31.89#ibcon#*before write, iclass 3, count 0 2006.173.05:55:31.89#ibcon#enter sib2, iclass 3, count 0 2006.173.05:55:31.89#ibcon#flushed, iclass 3, count 0 2006.173.05:55:31.89#ibcon#about to write, iclass 3, count 0 2006.173.05:55:31.89#ibcon#wrote, iclass 3, count 0 2006.173.05:55:31.89#ibcon#about to read 3, iclass 3, count 0 2006.173.05:55:31.92#ibcon#read 3, iclass 3, count 0 2006.173.05:55:31.92#ibcon#about to read 4, iclass 3, count 0 2006.173.05:55:31.92#ibcon#read 4, iclass 3, count 0 2006.173.05:55:31.93#ibcon#about to read 5, iclass 3, count 0 2006.173.05:55:31.93#ibcon#read 5, iclass 3, count 0 2006.173.05:55:31.93#ibcon#about to read 6, iclass 3, count 0 2006.173.05:55:31.93#ibcon#read 6, iclass 3, count 0 2006.173.05:55:31.93#ibcon#end of sib2, iclass 3, count 0 2006.173.05:55:31.93#ibcon#*after write, iclass 3, count 0 2006.173.05:55:31.93#ibcon#*before return 0, iclass 3, count 0 2006.173.05:55:31.93#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.05:55:31.93#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.05:55:31.93#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.05:55:31.93#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.05:55:31.93$vck44/vb=7,4 2006.173.05:55:31.93#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.05:55:31.93#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.05:55:31.93#ibcon#ireg 11 cls_cnt 2 2006.173.05:55:31.93#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.05:55:31.98#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.05:55:31.98#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.05:55:31.98#ibcon#enter wrdev, iclass 5, count 2 2006.173.05:55:31.98#ibcon#first serial, iclass 5, count 2 2006.173.05:55:31.98#ibcon#enter sib2, iclass 5, count 2 2006.173.05:55:31.99#ibcon#flushed, iclass 5, count 2 2006.173.05:55:31.99#ibcon#about to write, iclass 5, count 2 2006.173.05:55:31.99#ibcon#wrote, iclass 5, count 2 2006.173.05:55:31.99#ibcon#about to read 3, iclass 5, count 2 2006.173.05:55:32.00#ibcon#read 3, iclass 5, count 2 2006.173.05:55:32.00#ibcon#about to read 4, iclass 5, count 2 2006.173.05:55:32.00#ibcon#read 4, iclass 5, count 2 2006.173.05:55:32.00#ibcon#about to read 5, iclass 5, count 2 2006.173.05:55:32.00#ibcon#read 5, iclass 5, count 2 2006.173.05:55:32.01#ibcon#about to read 6, iclass 5, count 2 2006.173.05:55:32.01#ibcon#read 6, iclass 5, count 2 2006.173.05:55:32.01#ibcon#end of sib2, iclass 5, count 2 2006.173.05:55:32.01#ibcon#*mode == 0, iclass 5, count 2 2006.173.05:55:32.01#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.05:55:32.01#ibcon#[27=AT07-04\r\n] 2006.173.05:55:32.01#ibcon#*before write, iclass 5, count 2 2006.173.05:55:32.01#ibcon#enter sib2, iclass 5, count 2 2006.173.05:55:32.01#ibcon#flushed, iclass 5, count 2 2006.173.05:55:32.01#ibcon#about to write, iclass 5, count 2 2006.173.05:55:32.01#ibcon#wrote, iclass 5, count 2 2006.173.05:55:32.01#ibcon#about to read 3, iclass 5, count 2 2006.173.05:55:32.03#ibcon#read 3, iclass 5, count 2 2006.173.05:55:32.03#ibcon#about to read 4, iclass 5, count 2 2006.173.05:55:32.03#ibcon#read 4, iclass 5, count 2 2006.173.05:55:32.03#ibcon#about to read 5, iclass 5, count 2 2006.173.05:55:32.04#ibcon#read 5, iclass 5, count 2 2006.173.05:55:32.04#ibcon#about to read 6, iclass 5, count 2 2006.173.05:55:32.04#ibcon#read 6, iclass 5, count 2 2006.173.05:55:32.04#ibcon#end of sib2, iclass 5, count 2 2006.173.05:55:32.04#ibcon#*after write, iclass 5, count 2 2006.173.05:55:32.04#ibcon#*before return 0, iclass 5, count 2 2006.173.05:55:32.04#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.05:55:32.04#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.05:55:32.04#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.05:55:32.04#ibcon#ireg 7 cls_cnt 0 2006.173.05:55:32.04#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.05:55:32.15#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.05:55:32.15#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.05:55:32.15#ibcon#enter wrdev, iclass 5, count 0 2006.173.05:55:32.15#ibcon#first serial, iclass 5, count 0 2006.173.05:55:32.15#ibcon#enter sib2, iclass 5, count 0 2006.173.05:55:32.16#ibcon#flushed, iclass 5, count 0 2006.173.05:55:32.16#ibcon#about to write, iclass 5, count 0 2006.173.05:55:32.16#ibcon#wrote, iclass 5, count 0 2006.173.05:55:32.16#ibcon#about to read 3, iclass 5, count 0 2006.173.05:55:32.17#ibcon#read 3, iclass 5, count 0 2006.173.05:55:32.17#ibcon#about to read 4, iclass 5, count 0 2006.173.05:55:32.17#ibcon#read 4, iclass 5, count 0 2006.173.05:55:32.17#ibcon#about to read 5, iclass 5, count 0 2006.173.05:55:32.17#ibcon#read 5, iclass 5, count 0 2006.173.05:55:32.17#ibcon#about to read 6, iclass 5, count 0 2006.173.05:55:32.18#ibcon#read 6, iclass 5, count 0 2006.173.05:55:32.18#ibcon#end of sib2, iclass 5, count 0 2006.173.05:55:32.18#ibcon#*mode == 0, iclass 5, count 0 2006.173.05:55:32.18#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.05:55:32.18#ibcon#[27=USB\r\n] 2006.173.05:55:32.18#ibcon#*before write, iclass 5, count 0 2006.173.05:55:32.18#ibcon#enter sib2, iclass 5, count 0 2006.173.05:55:32.18#ibcon#flushed, iclass 5, count 0 2006.173.05:55:32.18#ibcon#about to write, iclass 5, count 0 2006.173.05:55:32.18#ibcon#wrote, iclass 5, count 0 2006.173.05:55:32.18#ibcon#about to read 3, iclass 5, count 0 2006.173.05:55:32.20#ibcon#read 3, iclass 5, count 0 2006.173.05:55:32.20#ibcon#about to read 4, iclass 5, count 0 2006.173.05:55:32.21#ibcon#read 4, iclass 5, count 0 2006.173.05:55:32.21#ibcon#about to read 5, iclass 5, count 0 2006.173.05:55:32.21#ibcon#read 5, iclass 5, count 0 2006.173.05:55:32.21#ibcon#about to read 6, iclass 5, count 0 2006.173.05:55:32.21#ibcon#read 6, iclass 5, count 0 2006.173.05:55:32.21#ibcon#end of sib2, iclass 5, count 0 2006.173.05:55:32.21#ibcon#*after write, iclass 5, count 0 2006.173.05:55:32.21#ibcon#*before return 0, iclass 5, count 0 2006.173.05:55:32.21#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.05:55:32.21#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.05:55:32.21#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.05:55:32.21#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.05:55:32.21$vck44/vblo=8,744.99 2006.173.05:55:32.21#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.05:55:32.21#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.05:55:32.21#ibcon#ireg 17 cls_cnt 0 2006.173.05:55:32.21#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.05:55:32.21#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.05:55:32.21#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.05:55:32.21#ibcon#enter wrdev, iclass 7, count 0 2006.173.05:55:32.21#ibcon#first serial, iclass 7, count 0 2006.173.05:55:32.21#ibcon#enter sib2, iclass 7, count 0 2006.173.05:55:32.21#ibcon#flushed, iclass 7, count 0 2006.173.05:55:32.21#ibcon#about to write, iclass 7, count 0 2006.173.05:55:32.21#ibcon#wrote, iclass 7, count 0 2006.173.05:55:32.21#ibcon#about to read 3, iclass 7, count 0 2006.173.05:55:32.22#ibcon#read 3, iclass 7, count 0 2006.173.05:55:32.22#ibcon#about to read 4, iclass 7, count 0 2006.173.05:55:32.22#ibcon#read 4, iclass 7, count 0 2006.173.05:55:32.22#ibcon#about to read 5, iclass 7, count 0 2006.173.05:55:32.22#ibcon#read 5, iclass 7, count 0 2006.173.05:55:32.23#ibcon#about to read 6, iclass 7, count 0 2006.173.05:55:32.23#ibcon#read 6, iclass 7, count 0 2006.173.05:55:32.23#ibcon#end of sib2, iclass 7, count 0 2006.173.05:55:32.23#ibcon#*mode == 0, iclass 7, count 0 2006.173.05:55:32.23#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.05:55:32.23#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.05:55:32.23#ibcon#*before write, iclass 7, count 0 2006.173.05:55:32.23#ibcon#enter sib2, iclass 7, count 0 2006.173.05:55:32.23#ibcon#flushed, iclass 7, count 0 2006.173.05:55:32.23#ibcon#about to write, iclass 7, count 0 2006.173.05:55:32.23#ibcon#wrote, iclass 7, count 0 2006.173.05:55:32.23#ibcon#about to read 3, iclass 7, count 0 2006.173.05:55:32.26#ibcon#read 3, iclass 7, count 0 2006.173.05:55:32.26#ibcon#about to read 4, iclass 7, count 0 2006.173.05:55:32.26#ibcon#read 4, iclass 7, count 0 2006.173.05:55:32.26#ibcon#about to read 5, iclass 7, count 0 2006.173.05:55:32.27#ibcon#read 5, iclass 7, count 0 2006.173.05:55:32.27#ibcon#about to read 6, iclass 7, count 0 2006.173.05:55:32.27#ibcon#read 6, iclass 7, count 0 2006.173.05:55:32.27#ibcon#end of sib2, iclass 7, count 0 2006.173.05:55:32.27#ibcon#*after write, iclass 7, count 0 2006.173.05:55:32.27#ibcon#*before return 0, iclass 7, count 0 2006.173.05:55:32.27#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.05:55:32.27#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.05:55:32.27#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.05:55:32.27#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.05:55:32.27$vck44/vb=8,4 2006.173.05:55:32.27#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.05:55:32.27#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.05:55:32.27#ibcon#ireg 11 cls_cnt 2 2006.173.05:55:32.27#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.05:55:32.32#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.05:55:32.32#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.05:55:32.32#ibcon#enter wrdev, iclass 11, count 2 2006.173.05:55:32.32#ibcon#first serial, iclass 11, count 2 2006.173.05:55:32.32#ibcon#enter sib2, iclass 11, count 2 2006.173.05:55:32.33#ibcon#flushed, iclass 11, count 2 2006.173.05:55:32.33#ibcon#about to write, iclass 11, count 2 2006.173.05:55:32.33#ibcon#wrote, iclass 11, count 2 2006.173.05:55:32.33#ibcon#about to read 3, iclass 11, count 2 2006.173.05:55:32.34#ibcon#read 3, iclass 11, count 2 2006.173.05:55:32.34#ibcon#about to read 4, iclass 11, count 2 2006.173.05:55:32.34#ibcon#read 4, iclass 11, count 2 2006.173.05:55:32.34#ibcon#about to read 5, iclass 11, count 2 2006.173.05:55:32.34#ibcon#read 5, iclass 11, count 2 2006.173.05:55:32.34#ibcon#about to read 6, iclass 11, count 2 2006.173.05:55:32.34#ibcon#read 6, iclass 11, count 2 2006.173.05:55:32.35#ibcon#end of sib2, iclass 11, count 2 2006.173.05:55:32.35#ibcon#*mode == 0, iclass 11, count 2 2006.173.05:55:32.35#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.05:55:32.35#ibcon#[27=AT08-04\r\n] 2006.173.05:55:32.35#ibcon#*before write, iclass 11, count 2 2006.173.05:55:32.35#ibcon#enter sib2, iclass 11, count 2 2006.173.05:55:32.35#ibcon#flushed, iclass 11, count 2 2006.173.05:55:32.35#ibcon#about to write, iclass 11, count 2 2006.173.05:55:32.35#ibcon#wrote, iclass 11, count 2 2006.173.05:55:32.35#ibcon#about to read 3, iclass 11, count 2 2006.173.05:55:32.37#ibcon#read 3, iclass 11, count 2 2006.173.05:55:32.37#ibcon#about to read 4, iclass 11, count 2 2006.173.05:55:32.37#ibcon#read 4, iclass 11, count 2 2006.173.05:55:32.37#ibcon#about to read 5, iclass 11, count 2 2006.173.05:55:32.37#ibcon#read 5, iclass 11, count 2 2006.173.05:55:32.37#ibcon#about to read 6, iclass 11, count 2 2006.173.05:55:32.37#ibcon#read 6, iclass 11, count 2 2006.173.05:55:32.38#ibcon#end of sib2, iclass 11, count 2 2006.173.05:55:32.38#ibcon#*after write, iclass 11, count 2 2006.173.05:55:32.38#ibcon#*before return 0, iclass 11, count 2 2006.173.05:55:32.38#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.05:55:32.38#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.05:55:32.38#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.05:55:32.38#ibcon#ireg 7 cls_cnt 0 2006.173.05:55:32.38#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.05:55:32.49#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.05:55:32.49#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.05:55:32.49#ibcon#enter wrdev, iclass 11, count 0 2006.173.05:55:32.49#ibcon#first serial, iclass 11, count 0 2006.173.05:55:32.49#ibcon#enter sib2, iclass 11, count 0 2006.173.05:55:32.50#ibcon#flushed, iclass 11, count 0 2006.173.05:55:32.50#ibcon#about to write, iclass 11, count 0 2006.173.05:55:32.50#ibcon#wrote, iclass 11, count 0 2006.173.05:55:32.50#ibcon#about to read 3, iclass 11, count 0 2006.173.05:55:32.51#ibcon#read 3, iclass 11, count 0 2006.173.05:55:32.51#ibcon#about to read 4, iclass 11, count 0 2006.173.05:55:32.51#ibcon#read 4, iclass 11, count 0 2006.173.05:55:32.52#ibcon#about to read 5, iclass 11, count 0 2006.173.05:55:32.52#ibcon#read 5, iclass 11, count 0 2006.173.05:55:32.52#ibcon#about to read 6, iclass 11, count 0 2006.173.05:55:32.52#ibcon#read 6, iclass 11, count 0 2006.173.05:55:32.52#ibcon#end of sib2, iclass 11, count 0 2006.173.05:55:32.52#ibcon#*mode == 0, iclass 11, count 0 2006.173.05:55:32.52#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.05:55:32.52#ibcon#[27=USB\r\n] 2006.173.05:55:32.52#ibcon#*before write, iclass 11, count 0 2006.173.05:55:32.52#ibcon#enter sib2, iclass 11, count 0 2006.173.05:55:32.52#ibcon#flushed, iclass 11, count 0 2006.173.05:55:32.52#ibcon#about to write, iclass 11, count 0 2006.173.05:55:32.52#ibcon#wrote, iclass 11, count 0 2006.173.05:55:32.52#ibcon#about to read 3, iclass 11, count 0 2006.173.05:55:32.54#ibcon#read 3, iclass 11, count 0 2006.173.05:55:32.54#ibcon#about to read 4, iclass 11, count 0 2006.173.05:55:32.54#ibcon#read 4, iclass 11, count 0 2006.173.05:55:32.55#ibcon#about to read 5, iclass 11, count 0 2006.173.05:55:32.55#ibcon#read 5, iclass 11, count 0 2006.173.05:55:32.55#ibcon#about to read 6, iclass 11, count 0 2006.173.05:55:32.55#ibcon#read 6, iclass 11, count 0 2006.173.05:55:32.55#ibcon#end of sib2, iclass 11, count 0 2006.173.05:55:32.55#ibcon#*after write, iclass 11, count 0 2006.173.05:55:32.55#ibcon#*before return 0, iclass 11, count 0 2006.173.05:55:32.55#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.05:55:32.55#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.05:55:32.55#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.05:55:32.55#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.05:55:32.55$vck44/vabw=wide 2006.173.05:55:32.55#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.05:55:32.55#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.05:55:32.55#ibcon#ireg 8 cls_cnt 0 2006.173.05:55:32.55#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.05:55:32.55#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.05:55:32.55#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.05:55:32.55#ibcon#enter wrdev, iclass 13, count 0 2006.173.05:55:32.55#ibcon#first serial, iclass 13, count 0 2006.173.05:55:32.55#ibcon#enter sib2, iclass 13, count 0 2006.173.05:55:32.55#ibcon#flushed, iclass 13, count 0 2006.173.05:55:32.55#ibcon#about to write, iclass 13, count 0 2006.173.05:55:32.55#ibcon#wrote, iclass 13, count 0 2006.173.05:55:32.55#ibcon#about to read 3, iclass 13, count 0 2006.173.05:55:32.56#ibcon#read 3, iclass 13, count 0 2006.173.05:55:32.56#ibcon#about to read 4, iclass 13, count 0 2006.173.05:55:32.56#ibcon#read 4, iclass 13, count 0 2006.173.05:55:32.56#ibcon#about to read 5, iclass 13, count 0 2006.173.05:55:32.56#ibcon#read 5, iclass 13, count 0 2006.173.05:55:32.56#ibcon#about to read 6, iclass 13, count 0 2006.173.05:55:32.57#ibcon#read 6, iclass 13, count 0 2006.173.05:55:32.57#ibcon#end of sib2, iclass 13, count 0 2006.173.05:55:32.57#ibcon#*mode == 0, iclass 13, count 0 2006.173.05:55:32.57#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.05:55:32.57#ibcon#[25=BW32\r\n] 2006.173.05:55:32.57#ibcon#*before write, iclass 13, count 0 2006.173.05:55:32.57#ibcon#enter sib2, iclass 13, count 0 2006.173.05:55:32.57#ibcon#flushed, iclass 13, count 0 2006.173.05:55:32.57#ibcon#about to write, iclass 13, count 0 2006.173.05:55:32.57#ibcon#wrote, iclass 13, count 0 2006.173.05:55:32.57#ibcon#about to read 3, iclass 13, count 0 2006.173.05:55:32.59#ibcon#read 3, iclass 13, count 0 2006.173.05:55:32.59#ibcon#about to read 4, iclass 13, count 0 2006.173.05:55:32.59#ibcon#read 4, iclass 13, count 0 2006.173.05:55:32.59#ibcon#about to read 5, iclass 13, count 0 2006.173.05:55:32.59#ibcon#read 5, iclass 13, count 0 2006.173.05:55:32.59#ibcon#about to read 6, iclass 13, count 0 2006.173.05:55:32.59#ibcon#read 6, iclass 13, count 0 2006.173.05:55:32.60#ibcon#end of sib2, iclass 13, count 0 2006.173.05:55:32.60#ibcon#*after write, iclass 13, count 0 2006.173.05:55:32.60#ibcon#*before return 0, iclass 13, count 0 2006.173.05:55:32.60#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.05:55:32.60#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.05:55:32.60#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.05:55:32.60#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.05:55:32.60$vck44/vbbw=wide 2006.173.05:55:32.60#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.05:55:32.60#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.05:55:32.60#ibcon#ireg 8 cls_cnt 0 2006.173.05:55:32.60#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.05:55:32.66#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.05:55:32.66#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.05:55:32.66#ibcon#enter wrdev, iclass 15, count 0 2006.173.05:55:32.66#ibcon#first serial, iclass 15, count 0 2006.173.05:55:32.66#ibcon#enter sib2, iclass 15, count 0 2006.173.05:55:32.67#ibcon#flushed, iclass 15, count 0 2006.173.05:55:32.67#ibcon#about to write, iclass 15, count 0 2006.173.05:55:32.67#ibcon#wrote, iclass 15, count 0 2006.173.05:55:32.67#ibcon#about to read 3, iclass 15, count 0 2006.173.05:55:32.68#ibcon#read 3, iclass 15, count 0 2006.173.05:55:32.68#ibcon#about to read 4, iclass 15, count 0 2006.173.05:55:32.68#ibcon#read 4, iclass 15, count 0 2006.173.05:55:32.69#ibcon#about to read 5, iclass 15, count 0 2006.173.05:55:32.69#ibcon#read 5, iclass 15, count 0 2006.173.05:55:32.69#ibcon#about to read 6, iclass 15, count 0 2006.173.05:55:32.69#ibcon#read 6, iclass 15, count 0 2006.173.05:55:32.69#ibcon#end of sib2, iclass 15, count 0 2006.173.05:55:32.69#ibcon#*mode == 0, iclass 15, count 0 2006.173.05:55:32.69#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.05:55:32.69#ibcon#[27=BW32\r\n] 2006.173.05:55:32.69#ibcon#*before write, iclass 15, count 0 2006.173.05:55:32.69#ibcon#enter sib2, iclass 15, count 0 2006.173.05:55:32.69#ibcon#flushed, iclass 15, count 0 2006.173.05:55:32.69#ibcon#about to write, iclass 15, count 0 2006.173.05:55:32.69#ibcon#wrote, iclass 15, count 0 2006.173.05:55:32.69#ibcon#about to read 3, iclass 15, count 0 2006.173.05:55:32.71#ibcon#read 3, iclass 15, count 0 2006.173.05:55:32.71#ibcon#about to read 4, iclass 15, count 0 2006.173.05:55:32.71#ibcon#read 4, iclass 15, count 0 2006.173.05:55:32.72#ibcon#about to read 5, iclass 15, count 0 2006.173.05:55:32.72#ibcon#read 5, iclass 15, count 0 2006.173.05:55:32.72#ibcon#about to read 6, iclass 15, count 0 2006.173.05:55:32.72#ibcon#read 6, iclass 15, count 0 2006.173.05:55:32.72#ibcon#end of sib2, iclass 15, count 0 2006.173.05:55:32.72#ibcon#*after write, iclass 15, count 0 2006.173.05:55:32.72#ibcon#*before return 0, iclass 15, count 0 2006.173.05:55:32.72#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.05:55:32.72#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.05:55:32.72#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.05:55:32.72#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.05:55:32.72$setupk4/ifdk4 2006.173.05:55:32.72$ifdk4/lo= 2006.173.05:55:32.72$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.05:55:32.72$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.05:55:32.72$ifdk4/patch= 2006.173.05:55:32.72$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.05:55:32.72$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.05:55:32.72$setupk4/!*+20s 2006.173.05:55:32.75#abcon#<5=/16 0.5 0.9 23.67 761005.3\r\n> 2006.173.05:55:32.77#abcon#{5=INTERFACE CLEAR} 2006.173.05:55:32.83#abcon#[5=S1D000X0/0*\r\n] 2006.173.05:55:42.92#abcon#<5=/16 0.5 0.9 23.67 761005.3\r\n> 2006.173.05:55:42.94#abcon#{5=INTERFACE CLEAR} 2006.173.05:55:43.00#abcon#[5=S1D000X0/0*\r\n] 2006.173.05:55:43.13#trakl#Source acquired 2006.173.05:55:44.13#flagr#flagr/antenna,acquired 2006.173.05:55:47.23$setupk4/"tpicd 2006.173.05:55:47.24$setupk4/echo=off 2006.173.05:55:47.24$setupk4/xlog=off 2006.173.05:55:47.24:!2006.173.05:59:22 2006.173.05:59:22.01:preob 2006.173.05:59:23.14/onsource/TRACKING 2006.173.05:59:23.14:!2006.173.05:59:32 2006.173.05:59:32.00:"tape 2006.173.05:59:32.00:"st=record 2006.173.05:59:32.00:data_valid=on 2006.173.05:59:32.00:midob 2006.173.05:59:32.14/onsource/TRACKING 2006.173.05:59:32.15/wx/23.69,1005.2,74 2006.173.05:59:32.33/cable/+6.5033E-03 2006.173.05:59:33.42/va/01,07,usb,yes,40,43 2006.173.05:59:33.42/va/02,06,usb,yes,39,40 2006.173.05:59:33.42/va/03,05,usb,yes,50,52 2006.173.05:59:33.42/va/04,06,usb,yes,40,43 2006.173.05:59:33.42/va/05,04,usb,yes,32,32 2006.173.05:59:33.42/va/06,03,usb,yes,44,44 2006.173.05:59:33.42/va/07,04,usb,yes,36,37 2006.173.05:59:33.42/va/08,04,usb,yes,31,37 2006.173.05:59:33.65/valo/01,524.99,yes,locked 2006.173.05:59:33.65/valo/02,534.99,yes,locked 2006.173.05:59:33.65/valo/03,564.99,yes,locked 2006.173.05:59:33.65/valo/04,624.99,yes,locked 2006.173.05:59:33.65/valo/05,734.99,yes,locked 2006.173.05:59:33.65/valo/06,814.99,yes,locked 2006.173.05:59:33.65/valo/07,864.99,yes,locked 2006.173.05:59:33.65/valo/08,884.99,yes,locked 2006.173.05:59:34.74/vb/01,04,usb,yes,31,28 2006.173.05:59:34.74/vb/02,04,usb,yes,33,33 2006.173.05:59:34.74/vb/03,04,usb,yes,30,33 2006.173.05:59:34.74/vb/04,04,usb,yes,34,33 2006.173.05:59:34.74/vb/05,04,usb,yes,27,29 2006.173.05:59:34.74/vb/06,04,usb,yes,32,28 2006.173.05:59:34.74/vb/07,04,usb,yes,31,31 2006.173.05:59:34.74/vb/08,04,usb,yes,29,32 2006.173.05:59:34.97/vblo/01,629.99,yes,locked 2006.173.05:59:34.97/vblo/02,634.99,yes,locked 2006.173.05:59:34.97/vblo/03,649.99,yes,locked 2006.173.05:59:34.97/vblo/04,679.99,yes,locked 2006.173.05:59:34.97/vblo/05,709.99,yes,locked 2006.173.05:59:34.97/vblo/06,719.99,yes,locked 2006.173.05:59:34.97/vblo/07,734.99,yes,locked 2006.173.05:59:34.97/vblo/08,744.99,yes,locked 2006.173.05:59:35.12/vabw/8 2006.173.05:59:35.27/vbbw/8 2006.173.05:59:35.36/xfe/off,on,14.2 2006.173.05:59:35.75/ifatt/23,28,28,28 2006.173.05:59:36.07/fmout-gps/S +4.04E-07 2006.173.05:59:36.12:!2006.173.06:00:12 2006.173.06:00:12.01:data_valid=off 2006.173.06:00:12.02:"et 2006.173.06:00:12.02:!+3s 2006.173.06:00:15.04:"tape 2006.173.06:00:15.04:postob 2006.173.06:00:15.20/cable/+6.5050E-03 2006.173.06:00:15.20/wx/23.69,1005.2,75 2006.173.06:00:15.26/fmout-gps/S +4.05E-07 2006.173.06:00:15.26:scan_name=173-0605,jd0606,380 2006.173.06:00:15.27:source=1308+326,131028.66,322043.8,2000.0,ccw 2006.173.06:00:16.14#flagr#flagr/antenna,new-source 2006.173.06:00:16.15:checkk5 2006.173.06:00:16.52/chk_autoobs//k5ts1/ autoobs is running! 2006.173.06:00:16.92/chk_autoobs//k5ts2/ autoobs is running! 2006.173.06:00:17.34/chk_autoobs//k5ts3/ autoobs is running! 2006.173.06:00:17.74/chk_autoobs//k5ts4/ autoobs is running! 2006.173.06:00:18.13/chk_obsdata//k5ts1/T1730559??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.173.06:00:18.54/chk_obsdata//k5ts2/T1730559??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.173.06:00:18.92/chk_obsdata//k5ts3/T1730559??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.173.06:00:19.32/chk_obsdata//k5ts4/T1730559??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.173.06:00:20.03/k5log//k5ts1_log_newline 2006.173.06:00:20.73/k5log//k5ts2_log_newline 2006.173.06:00:21.45/k5log//k5ts3_log_newline 2006.173.06:00:22.16/k5log//k5ts4_log_newline 2006.173.06:00:22.18/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.06:00:22.18:setupk4=1 2006.173.06:00:22.18$setupk4/echo=on 2006.173.06:00:22.18$setupk4/pcalon 2006.173.06:00:22.18$pcalon/"no phase cal control is implemented here 2006.173.06:00:22.18$setupk4/"tpicd=stop 2006.173.06:00:22.18$setupk4/"rec=synch_on 2006.173.06:00:22.18$setupk4/"rec_mode=128 2006.173.06:00:22.18$setupk4/!* 2006.173.06:00:22.18$setupk4/recpk4 2006.173.06:00:22.18$recpk4/recpatch= 2006.173.06:00:22.19$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.06:00:22.19$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.06:00:22.19$setupk4/vck44 2006.173.06:00:22.19$vck44/valo=1,524.99 2006.173.06:00:22.19#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.06:00:22.19#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.06:00:22.19#ibcon#ireg 17 cls_cnt 0 2006.173.06:00:22.19#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.06:00:22.19#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.06:00:22.19#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.06:00:22.19#ibcon#enter wrdev, iclass 28, count 0 2006.173.06:00:22.19#ibcon#first serial, iclass 28, count 0 2006.173.06:00:22.19#ibcon#enter sib2, iclass 28, count 0 2006.173.06:00:22.19#ibcon#flushed, iclass 28, count 0 2006.173.06:00:22.19#ibcon#about to write, iclass 28, count 0 2006.173.06:00:22.19#ibcon#wrote, iclass 28, count 0 2006.173.06:00:22.20#ibcon#about to read 3, iclass 28, count 0 2006.173.06:00:22.21#ibcon#read 3, iclass 28, count 0 2006.173.06:00:22.21#ibcon#about to read 4, iclass 28, count 0 2006.173.06:00:22.21#ibcon#read 4, iclass 28, count 0 2006.173.06:00:22.21#ibcon#about to read 5, iclass 28, count 0 2006.173.06:00:22.21#ibcon#read 5, iclass 28, count 0 2006.173.06:00:22.21#ibcon#about to read 6, iclass 28, count 0 2006.173.06:00:22.21#ibcon#read 6, iclass 28, count 0 2006.173.06:00:22.21#ibcon#end of sib2, iclass 28, count 0 2006.173.06:00:22.21#ibcon#*mode == 0, iclass 28, count 0 2006.173.06:00:22.21#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.06:00:22.22#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.06:00:22.22#ibcon#*before write, iclass 28, count 0 2006.173.06:00:22.22#ibcon#enter sib2, iclass 28, count 0 2006.173.06:00:22.22#ibcon#flushed, iclass 28, count 0 2006.173.06:00:22.22#ibcon#about to write, iclass 28, count 0 2006.173.06:00:22.22#ibcon#wrote, iclass 28, count 0 2006.173.06:00:22.22#ibcon#about to read 3, iclass 28, count 0 2006.173.06:00:22.26#ibcon#read 3, iclass 28, count 0 2006.173.06:00:22.26#ibcon#about to read 4, iclass 28, count 0 2006.173.06:00:22.26#ibcon#read 4, iclass 28, count 0 2006.173.06:00:22.26#ibcon#about to read 5, iclass 28, count 0 2006.173.06:00:22.26#ibcon#read 5, iclass 28, count 0 2006.173.06:00:22.26#ibcon#about to read 6, iclass 28, count 0 2006.173.06:00:22.26#ibcon#read 6, iclass 28, count 0 2006.173.06:00:22.26#ibcon#end of sib2, iclass 28, count 0 2006.173.06:00:22.26#ibcon#*after write, iclass 28, count 0 2006.173.06:00:22.26#ibcon#*before return 0, iclass 28, count 0 2006.173.06:00:22.26#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.06:00:22.26#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.06:00:22.26#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.06:00:22.26#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.06:00:22.26$vck44/va=1,7 2006.173.06:00:22.26#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.06:00:22.26#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.06:00:22.26#ibcon#ireg 11 cls_cnt 2 2006.173.06:00:22.26#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.06:00:22.26#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.06:00:22.26#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.06:00:22.26#ibcon#enter wrdev, iclass 30, count 2 2006.173.06:00:22.26#ibcon#first serial, iclass 30, count 2 2006.173.06:00:22.26#ibcon#enter sib2, iclass 30, count 2 2006.173.06:00:22.26#ibcon#flushed, iclass 30, count 2 2006.173.06:00:22.26#ibcon#about to write, iclass 30, count 2 2006.173.06:00:22.26#ibcon#wrote, iclass 30, count 2 2006.173.06:00:22.26#ibcon#about to read 3, iclass 30, count 2 2006.173.06:00:22.28#ibcon#read 3, iclass 30, count 2 2006.173.06:00:22.28#ibcon#about to read 4, iclass 30, count 2 2006.173.06:00:22.28#ibcon#read 4, iclass 30, count 2 2006.173.06:00:22.28#ibcon#about to read 5, iclass 30, count 2 2006.173.06:00:22.28#ibcon#read 5, iclass 30, count 2 2006.173.06:00:22.28#ibcon#about to read 6, iclass 30, count 2 2006.173.06:00:22.28#ibcon#read 6, iclass 30, count 2 2006.173.06:00:22.28#ibcon#end of sib2, iclass 30, count 2 2006.173.06:00:22.28#ibcon#*mode == 0, iclass 30, count 2 2006.173.06:00:22.28#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.06:00:22.28#ibcon#[25=AT01-07\r\n] 2006.173.06:00:22.28#ibcon#*before write, iclass 30, count 2 2006.173.06:00:22.28#ibcon#enter sib2, iclass 30, count 2 2006.173.06:00:22.28#ibcon#flushed, iclass 30, count 2 2006.173.06:00:22.28#ibcon#about to write, iclass 30, count 2 2006.173.06:00:22.28#ibcon#wrote, iclass 30, count 2 2006.173.06:00:22.28#ibcon#about to read 3, iclass 30, count 2 2006.173.06:00:22.31#ibcon#read 3, iclass 30, count 2 2006.173.06:00:22.31#ibcon#about to read 4, iclass 30, count 2 2006.173.06:00:22.31#ibcon#read 4, iclass 30, count 2 2006.173.06:00:22.31#ibcon#about to read 5, iclass 30, count 2 2006.173.06:00:22.31#ibcon#read 5, iclass 30, count 2 2006.173.06:00:22.31#ibcon#about to read 6, iclass 30, count 2 2006.173.06:00:22.31#ibcon#read 6, iclass 30, count 2 2006.173.06:00:22.31#ibcon#end of sib2, iclass 30, count 2 2006.173.06:00:22.31#ibcon#*after write, iclass 30, count 2 2006.173.06:00:22.31#ibcon#*before return 0, iclass 30, count 2 2006.173.06:00:22.31#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.06:00:22.31#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.06:00:22.31#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.06:00:22.31#ibcon#ireg 7 cls_cnt 0 2006.173.06:00:22.31#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.06:00:22.43#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.06:00:22.43#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.06:00:22.43#ibcon#enter wrdev, iclass 30, count 0 2006.173.06:00:22.43#ibcon#first serial, iclass 30, count 0 2006.173.06:00:22.43#ibcon#enter sib2, iclass 30, count 0 2006.173.06:00:22.43#ibcon#flushed, iclass 30, count 0 2006.173.06:00:22.43#ibcon#about to write, iclass 30, count 0 2006.173.06:00:22.43#ibcon#wrote, iclass 30, count 0 2006.173.06:00:22.43#ibcon#about to read 3, iclass 30, count 0 2006.173.06:00:22.45#ibcon#read 3, iclass 30, count 0 2006.173.06:00:22.45#ibcon#about to read 4, iclass 30, count 0 2006.173.06:00:22.45#ibcon#read 4, iclass 30, count 0 2006.173.06:00:22.45#ibcon#about to read 5, iclass 30, count 0 2006.173.06:00:22.45#ibcon#read 5, iclass 30, count 0 2006.173.06:00:22.45#ibcon#about to read 6, iclass 30, count 0 2006.173.06:00:22.45#ibcon#read 6, iclass 30, count 0 2006.173.06:00:22.45#ibcon#end of sib2, iclass 30, count 0 2006.173.06:00:22.45#ibcon#*mode == 0, iclass 30, count 0 2006.173.06:00:22.45#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.06:00:22.45#ibcon#[25=USB\r\n] 2006.173.06:00:22.45#ibcon#*before write, iclass 30, count 0 2006.173.06:00:22.45#ibcon#enter sib2, iclass 30, count 0 2006.173.06:00:22.45#ibcon#flushed, iclass 30, count 0 2006.173.06:00:22.45#ibcon#about to write, iclass 30, count 0 2006.173.06:00:22.45#ibcon#wrote, iclass 30, count 0 2006.173.06:00:22.45#ibcon#about to read 3, iclass 30, count 0 2006.173.06:00:22.48#ibcon#read 3, iclass 30, count 0 2006.173.06:00:22.48#ibcon#about to read 4, iclass 30, count 0 2006.173.06:00:22.48#ibcon#read 4, iclass 30, count 0 2006.173.06:00:22.48#ibcon#about to read 5, iclass 30, count 0 2006.173.06:00:22.48#ibcon#read 5, iclass 30, count 0 2006.173.06:00:22.48#ibcon#about to read 6, iclass 30, count 0 2006.173.06:00:22.48#ibcon#read 6, iclass 30, count 0 2006.173.06:00:22.48#ibcon#end of sib2, iclass 30, count 0 2006.173.06:00:22.48#ibcon#*after write, iclass 30, count 0 2006.173.06:00:22.48#ibcon#*before return 0, iclass 30, count 0 2006.173.06:00:22.48#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.06:00:22.48#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.06:00:22.48#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.06:00:22.48#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.06:00:22.48$vck44/valo=2,534.99 2006.173.06:00:22.48#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.06:00:22.48#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.06:00:22.48#ibcon#ireg 17 cls_cnt 0 2006.173.06:00:22.48#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.06:00:22.48#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.06:00:22.48#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.06:00:22.48#ibcon#enter wrdev, iclass 32, count 0 2006.173.06:00:22.48#ibcon#first serial, iclass 32, count 0 2006.173.06:00:22.48#ibcon#enter sib2, iclass 32, count 0 2006.173.06:00:22.48#ibcon#flushed, iclass 32, count 0 2006.173.06:00:22.48#ibcon#about to write, iclass 32, count 0 2006.173.06:00:22.48#ibcon#wrote, iclass 32, count 0 2006.173.06:00:22.48#ibcon#about to read 3, iclass 32, count 0 2006.173.06:00:22.50#ibcon#read 3, iclass 32, count 0 2006.173.06:00:22.50#ibcon#about to read 4, iclass 32, count 0 2006.173.06:00:22.50#ibcon#read 4, iclass 32, count 0 2006.173.06:00:22.50#ibcon#about to read 5, iclass 32, count 0 2006.173.06:00:22.50#ibcon#read 5, iclass 32, count 0 2006.173.06:00:22.50#ibcon#about to read 6, iclass 32, count 0 2006.173.06:00:22.50#ibcon#read 6, iclass 32, count 0 2006.173.06:00:22.50#ibcon#end of sib2, iclass 32, count 0 2006.173.06:00:22.50#ibcon#*mode == 0, iclass 32, count 0 2006.173.06:00:22.50#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.06:00:22.50#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.06:00:22.50#ibcon#*before write, iclass 32, count 0 2006.173.06:00:22.50#ibcon#enter sib2, iclass 32, count 0 2006.173.06:00:22.50#ibcon#flushed, iclass 32, count 0 2006.173.06:00:22.50#ibcon#about to write, iclass 32, count 0 2006.173.06:00:22.50#ibcon#wrote, iclass 32, count 0 2006.173.06:00:22.50#ibcon#about to read 3, iclass 32, count 0 2006.173.06:00:22.54#ibcon#read 3, iclass 32, count 0 2006.173.06:00:22.54#ibcon#about to read 4, iclass 32, count 0 2006.173.06:00:22.54#ibcon#read 4, iclass 32, count 0 2006.173.06:00:22.54#ibcon#about to read 5, iclass 32, count 0 2006.173.06:00:22.54#ibcon#read 5, iclass 32, count 0 2006.173.06:00:22.54#ibcon#about to read 6, iclass 32, count 0 2006.173.06:00:22.54#ibcon#read 6, iclass 32, count 0 2006.173.06:00:22.54#ibcon#end of sib2, iclass 32, count 0 2006.173.06:00:22.54#ibcon#*after write, iclass 32, count 0 2006.173.06:00:22.54#ibcon#*before return 0, iclass 32, count 0 2006.173.06:00:22.54#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.06:00:22.54#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.06:00:22.54#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.06:00:22.54#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.06:00:22.54$vck44/va=2,6 2006.173.06:00:22.54#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.06:00:22.54#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.06:00:22.54#ibcon#ireg 11 cls_cnt 2 2006.173.06:00:22.54#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.06:00:22.60#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.06:00:22.60#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.06:00:22.60#ibcon#enter wrdev, iclass 34, count 2 2006.173.06:00:22.60#ibcon#first serial, iclass 34, count 2 2006.173.06:00:22.60#ibcon#enter sib2, iclass 34, count 2 2006.173.06:00:22.60#ibcon#flushed, iclass 34, count 2 2006.173.06:00:22.60#ibcon#about to write, iclass 34, count 2 2006.173.06:00:22.60#ibcon#wrote, iclass 34, count 2 2006.173.06:00:22.60#ibcon#about to read 3, iclass 34, count 2 2006.173.06:00:22.62#ibcon#read 3, iclass 34, count 2 2006.173.06:00:22.62#ibcon#about to read 4, iclass 34, count 2 2006.173.06:00:22.62#ibcon#read 4, iclass 34, count 2 2006.173.06:00:22.62#ibcon#about to read 5, iclass 34, count 2 2006.173.06:00:22.62#ibcon#read 5, iclass 34, count 2 2006.173.06:00:22.62#ibcon#about to read 6, iclass 34, count 2 2006.173.06:00:22.62#ibcon#read 6, iclass 34, count 2 2006.173.06:00:22.62#ibcon#end of sib2, iclass 34, count 2 2006.173.06:00:22.62#ibcon#*mode == 0, iclass 34, count 2 2006.173.06:00:22.62#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.06:00:22.62#ibcon#[25=AT02-06\r\n] 2006.173.06:00:22.62#ibcon#*before write, iclass 34, count 2 2006.173.06:00:22.62#ibcon#enter sib2, iclass 34, count 2 2006.173.06:00:22.62#ibcon#flushed, iclass 34, count 2 2006.173.06:00:22.62#ibcon#about to write, iclass 34, count 2 2006.173.06:00:22.62#ibcon#wrote, iclass 34, count 2 2006.173.06:00:22.62#ibcon#about to read 3, iclass 34, count 2 2006.173.06:00:22.65#ibcon#read 3, iclass 34, count 2 2006.173.06:00:22.65#ibcon#about to read 4, iclass 34, count 2 2006.173.06:00:22.65#ibcon#read 4, iclass 34, count 2 2006.173.06:00:22.65#ibcon#about to read 5, iclass 34, count 2 2006.173.06:00:22.65#ibcon#read 5, iclass 34, count 2 2006.173.06:00:22.65#ibcon#about to read 6, iclass 34, count 2 2006.173.06:00:22.65#ibcon#read 6, iclass 34, count 2 2006.173.06:00:22.65#ibcon#end of sib2, iclass 34, count 2 2006.173.06:00:22.65#ibcon#*after write, iclass 34, count 2 2006.173.06:00:22.65#ibcon#*before return 0, iclass 34, count 2 2006.173.06:00:22.65#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.06:00:22.65#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.06:00:22.65#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.06:00:22.65#ibcon#ireg 7 cls_cnt 0 2006.173.06:00:22.65#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.06:00:22.77#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.06:00:22.77#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.06:00:22.77#ibcon#enter wrdev, iclass 34, count 0 2006.173.06:00:22.77#ibcon#first serial, iclass 34, count 0 2006.173.06:00:22.77#ibcon#enter sib2, iclass 34, count 0 2006.173.06:00:22.77#ibcon#flushed, iclass 34, count 0 2006.173.06:00:22.77#ibcon#about to write, iclass 34, count 0 2006.173.06:00:22.77#ibcon#wrote, iclass 34, count 0 2006.173.06:00:22.77#ibcon#about to read 3, iclass 34, count 0 2006.173.06:00:22.79#ibcon#read 3, iclass 34, count 0 2006.173.06:00:22.79#ibcon#about to read 4, iclass 34, count 0 2006.173.06:00:22.79#ibcon#read 4, iclass 34, count 0 2006.173.06:00:22.79#ibcon#about to read 5, iclass 34, count 0 2006.173.06:00:22.79#ibcon#read 5, iclass 34, count 0 2006.173.06:00:22.79#ibcon#about to read 6, iclass 34, count 0 2006.173.06:00:22.79#ibcon#read 6, iclass 34, count 0 2006.173.06:00:22.79#ibcon#end of sib2, iclass 34, count 0 2006.173.06:00:22.79#ibcon#*mode == 0, iclass 34, count 0 2006.173.06:00:22.79#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.06:00:22.79#ibcon#[25=USB\r\n] 2006.173.06:00:22.79#ibcon#*before write, iclass 34, count 0 2006.173.06:00:22.79#ibcon#enter sib2, iclass 34, count 0 2006.173.06:00:22.79#ibcon#flushed, iclass 34, count 0 2006.173.06:00:22.79#ibcon#about to write, iclass 34, count 0 2006.173.06:00:22.79#ibcon#wrote, iclass 34, count 0 2006.173.06:00:22.79#ibcon#about to read 3, iclass 34, count 0 2006.173.06:00:22.82#ibcon#read 3, iclass 34, count 0 2006.173.06:00:22.82#ibcon#about to read 4, iclass 34, count 0 2006.173.06:00:22.82#ibcon#read 4, iclass 34, count 0 2006.173.06:00:22.82#ibcon#about to read 5, iclass 34, count 0 2006.173.06:00:22.82#ibcon#read 5, iclass 34, count 0 2006.173.06:00:22.82#ibcon#about to read 6, iclass 34, count 0 2006.173.06:00:22.82#ibcon#read 6, iclass 34, count 0 2006.173.06:00:22.82#ibcon#end of sib2, iclass 34, count 0 2006.173.06:00:22.82#ibcon#*after write, iclass 34, count 0 2006.173.06:00:22.82#ibcon#*before return 0, iclass 34, count 0 2006.173.06:00:22.82#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.06:00:22.82#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.06:00:22.82#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.06:00:22.82#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.06:00:22.82$vck44/valo=3,564.99 2006.173.06:00:22.82#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.06:00:22.82#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.06:00:22.82#ibcon#ireg 17 cls_cnt 0 2006.173.06:00:22.82#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.06:00:22.82#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.06:00:22.82#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.06:00:22.82#ibcon#enter wrdev, iclass 36, count 0 2006.173.06:00:22.82#ibcon#first serial, iclass 36, count 0 2006.173.06:00:22.82#ibcon#enter sib2, iclass 36, count 0 2006.173.06:00:22.82#ibcon#flushed, iclass 36, count 0 2006.173.06:00:22.82#ibcon#about to write, iclass 36, count 0 2006.173.06:00:22.82#ibcon#wrote, iclass 36, count 0 2006.173.06:00:22.82#ibcon#about to read 3, iclass 36, count 0 2006.173.06:00:22.84#ibcon#read 3, iclass 36, count 0 2006.173.06:00:22.84#ibcon#about to read 4, iclass 36, count 0 2006.173.06:00:22.84#ibcon#read 4, iclass 36, count 0 2006.173.06:00:22.84#ibcon#about to read 5, iclass 36, count 0 2006.173.06:00:22.84#ibcon#read 5, iclass 36, count 0 2006.173.06:00:22.84#ibcon#about to read 6, iclass 36, count 0 2006.173.06:00:22.84#ibcon#read 6, iclass 36, count 0 2006.173.06:00:22.84#ibcon#end of sib2, iclass 36, count 0 2006.173.06:00:22.84#ibcon#*mode == 0, iclass 36, count 0 2006.173.06:00:22.84#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.06:00:22.84#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.06:00:22.84#ibcon#*before write, iclass 36, count 0 2006.173.06:00:22.84#ibcon#enter sib2, iclass 36, count 0 2006.173.06:00:22.84#ibcon#flushed, iclass 36, count 0 2006.173.06:00:22.84#ibcon#about to write, iclass 36, count 0 2006.173.06:00:22.84#ibcon#wrote, iclass 36, count 0 2006.173.06:00:22.84#ibcon#about to read 3, iclass 36, count 0 2006.173.06:00:22.88#ibcon#read 3, iclass 36, count 0 2006.173.06:00:22.88#ibcon#about to read 4, iclass 36, count 0 2006.173.06:00:22.88#ibcon#read 4, iclass 36, count 0 2006.173.06:00:22.88#ibcon#about to read 5, iclass 36, count 0 2006.173.06:00:22.88#ibcon#read 5, iclass 36, count 0 2006.173.06:00:22.88#ibcon#about to read 6, iclass 36, count 0 2006.173.06:00:22.88#ibcon#read 6, iclass 36, count 0 2006.173.06:00:22.88#ibcon#end of sib2, iclass 36, count 0 2006.173.06:00:22.88#ibcon#*after write, iclass 36, count 0 2006.173.06:00:22.88#ibcon#*before return 0, iclass 36, count 0 2006.173.06:00:22.88#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.06:00:22.88#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.06:00:22.88#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.06:00:22.88#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.06:00:22.88$vck44/va=3,5 2006.173.06:00:22.88#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.06:00:22.88#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.06:00:22.88#ibcon#ireg 11 cls_cnt 2 2006.173.06:00:22.88#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.06:00:22.94#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.06:00:22.94#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.06:00:22.94#ibcon#enter wrdev, iclass 38, count 2 2006.173.06:00:22.94#ibcon#first serial, iclass 38, count 2 2006.173.06:00:22.94#ibcon#enter sib2, iclass 38, count 2 2006.173.06:00:22.94#ibcon#flushed, iclass 38, count 2 2006.173.06:00:22.94#ibcon#about to write, iclass 38, count 2 2006.173.06:00:22.94#ibcon#wrote, iclass 38, count 2 2006.173.06:00:22.94#ibcon#about to read 3, iclass 38, count 2 2006.173.06:00:22.96#ibcon#read 3, iclass 38, count 2 2006.173.06:00:22.96#ibcon#about to read 4, iclass 38, count 2 2006.173.06:00:22.96#ibcon#read 4, iclass 38, count 2 2006.173.06:00:22.96#ibcon#about to read 5, iclass 38, count 2 2006.173.06:00:22.96#ibcon#read 5, iclass 38, count 2 2006.173.06:00:22.96#ibcon#about to read 6, iclass 38, count 2 2006.173.06:00:22.96#ibcon#read 6, iclass 38, count 2 2006.173.06:00:22.96#ibcon#end of sib2, iclass 38, count 2 2006.173.06:00:22.96#ibcon#*mode == 0, iclass 38, count 2 2006.173.06:00:22.96#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.06:00:22.96#ibcon#[25=AT03-05\r\n] 2006.173.06:00:22.96#ibcon#*before write, iclass 38, count 2 2006.173.06:00:22.96#ibcon#enter sib2, iclass 38, count 2 2006.173.06:00:22.96#ibcon#flushed, iclass 38, count 2 2006.173.06:00:22.96#ibcon#about to write, iclass 38, count 2 2006.173.06:00:22.96#ibcon#wrote, iclass 38, count 2 2006.173.06:00:22.96#ibcon#about to read 3, iclass 38, count 2 2006.173.06:00:22.99#ibcon#read 3, iclass 38, count 2 2006.173.06:00:22.99#ibcon#about to read 4, iclass 38, count 2 2006.173.06:00:22.99#ibcon#read 4, iclass 38, count 2 2006.173.06:00:22.99#ibcon#about to read 5, iclass 38, count 2 2006.173.06:00:22.99#ibcon#read 5, iclass 38, count 2 2006.173.06:00:22.99#ibcon#about to read 6, iclass 38, count 2 2006.173.06:00:22.99#ibcon#read 6, iclass 38, count 2 2006.173.06:00:22.99#ibcon#end of sib2, iclass 38, count 2 2006.173.06:00:22.99#ibcon#*after write, iclass 38, count 2 2006.173.06:00:22.99#ibcon#*before return 0, iclass 38, count 2 2006.173.06:00:22.99#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.06:00:22.99#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.06:00:22.99#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.06:00:22.99#ibcon#ireg 7 cls_cnt 0 2006.173.06:00:22.99#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.06:00:23.11#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.06:00:23.11#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.06:00:23.11#ibcon#enter wrdev, iclass 38, count 0 2006.173.06:00:23.11#ibcon#first serial, iclass 38, count 0 2006.173.06:00:23.11#ibcon#enter sib2, iclass 38, count 0 2006.173.06:00:23.11#ibcon#flushed, iclass 38, count 0 2006.173.06:00:23.11#ibcon#about to write, iclass 38, count 0 2006.173.06:00:23.11#ibcon#wrote, iclass 38, count 0 2006.173.06:00:23.11#ibcon#about to read 3, iclass 38, count 0 2006.173.06:00:23.13#ibcon#read 3, iclass 38, count 0 2006.173.06:00:23.13#ibcon#about to read 4, iclass 38, count 0 2006.173.06:00:23.13#ibcon#read 4, iclass 38, count 0 2006.173.06:00:23.13#ibcon#about to read 5, iclass 38, count 0 2006.173.06:00:23.13#ibcon#read 5, iclass 38, count 0 2006.173.06:00:23.13#ibcon#about to read 6, iclass 38, count 0 2006.173.06:00:23.13#ibcon#read 6, iclass 38, count 0 2006.173.06:00:23.13#ibcon#end of sib2, iclass 38, count 0 2006.173.06:00:23.13#ibcon#*mode == 0, iclass 38, count 0 2006.173.06:00:23.13#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.06:00:23.13#ibcon#[25=USB\r\n] 2006.173.06:00:23.13#ibcon#*before write, iclass 38, count 0 2006.173.06:00:23.13#ibcon#enter sib2, iclass 38, count 0 2006.173.06:00:23.13#ibcon#flushed, iclass 38, count 0 2006.173.06:00:23.13#ibcon#about to write, iclass 38, count 0 2006.173.06:00:23.13#ibcon#wrote, iclass 38, count 0 2006.173.06:00:23.13#ibcon#about to read 3, iclass 38, count 0 2006.173.06:00:23.16#ibcon#read 3, iclass 38, count 0 2006.173.06:00:23.16#ibcon#about to read 4, iclass 38, count 0 2006.173.06:00:23.16#ibcon#read 4, iclass 38, count 0 2006.173.06:00:23.16#ibcon#about to read 5, iclass 38, count 0 2006.173.06:00:23.16#ibcon#read 5, iclass 38, count 0 2006.173.06:00:23.16#ibcon#about to read 6, iclass 38, count 0 2006.173.06:00:23.16#ibcon#read 6, iclass 38, count 0 2006.173.06:00:23.16#ibcon#end of sib2, iclass 38, count 0 2006.173.06:00:23.16#ibcon#*after write, iclass 38, count 0 2006.173.06:00:23.16#ibcon#*before return 0, iclass 38, count 0 2006.173.06:00:23.16#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.06:00:23.16#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.06:00:23.16#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.06:00:23.16#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.06:00:23.16$vck44/valo=4,624.99 2006.173.06:00:23.16#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.06:00:23.16#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.06:00:23.16#ibcon#ireg 17 cls_cnt 0 2006.173.06:00:23.16#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.06:00:23.16#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.06:00:23.16#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.06:00:23.16#ibcon#enter wrdev, iclass 40, count 0 2006.173.06:00:23.16#ibcon#first serial, iclass 40, count 0 2006.173.06:00:23.16#ibcon#enter sib2, iclass 40, count 0 2006.173.06:00:23.16#ibcon#flushed, iclass 40, count 0 2006.173.06:00:23.16#ibcon#about to write, iclass 40, count 0 2006.173.06:00:23.16#ibcon#wrote, iclass 40, count 0 2006.173.06:00:23.16#ibcon#about to read 3, iclass 40, count 0 2006.173.06:00:23.18#ibcon#read 3, iclass 40, count 0 2006.173.06:00:23.18#ibcon#about to read 4, iclass 40, count 0 2006.173.06:00:23.18#ibcon#read 4, iclass 40, count 0 2006.173.06:00:23.18#ibcon#about to read 5, iclass 40, count 0 2006.173.06:00:23.18#ibcon#read 5, iclass 40, count 0 2006.173.06:00:23.18#ibcon#about to read 6, iclass 40, count 0 2006.173.06:00:23.18#ibcon#read 6, iclass 40, count 0 2006.173.06:00:23.18#ibcon#end of sib2, iclass 40, count 0 2006.173.06:00:23.18#ibcon#*mode == 0, iclass 40, count 0 2006.173.06:00:23.18#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.06:00:23.18#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.06:00:23.18#ibcon#*before write, iclass 40, count 0 2006.173.06:00:23.18#ibcon#enter sib2, iclass 40, count 0 2006.173.06:00:23.18#ibcon#flushed, iclass 40, count 0 2006.173.06:00:23.18#ibcon#about to write, iclass 40, count 0 2006.173.06:00:23.18#ibcon#wrote, iclass 40, count 0 2006.173.06:00:23.18#ibcon#about to read 3, iclass 40, count 0 2006.173.06:00:23.22#ibcon#read 3, iclass 40, count 0 2006.173.06:00:23.22#ibcon#about to read 4, iclass 40, count 0 2006.173.06:00:23.22#ibcon#read 4, iclass 40, count 0 2006.173.06:00:23.22#ibcon#about to read 5, iclass 40, count 0 2006.173.06:00:23.22#ibcon#read 5, iclass 40, count 0 2006.173.06:00:23.22#ibcon#about to read 6, iclass 40, count 0 2006.173.06:00:23.22#ibcon#read 6, iclass 40, count 0 2006.173.06:00:23.22#ibcon#end of sib2, iclass 40, count 0 2006.173.06:00:23.22#ibcon#*after write, iclass 40, count 0 2006.173.06:00:23.22#ibcon#*before return 0, iclass 40, count 0 2006.173.06:00:23.22#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.06:00:23.22#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.06:00:23.22#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.06:00:23.22#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.06:00:23.22$vck44/va=4,6 2006.173.06:00:23.22#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.06:00:23.22#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.06:00:23.22#ibcon#ireg 11 cls_cnt 2 2006.173.06:00:23.22#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.06:00:23.28#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.06:00:23.28#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.06:00:23.28#ibcon#enter wrdev, iclass 4, count 2 2006.173.06:00:23.28#ibcon#first serial, iclass 4, count 2 2006.173.06:00:23.28#ibcon#enter sib2, iclass 4, count 2 2006.173.06:00:23.28#ibcon#flushed, iclass 4, count 2 2006.173.06:00:23.28#ibcon#about to write, iclass 4, count 2 2006.173.06:00:23.28#ibcon#wrote, iclass 4, count 2 2006.173.06:00:23.28#ibcon#about to read 3, iclass 4, count 2 2006.173.06:00:23.30#ibcon#read 3, iclass 4, count 2 2006.173.06:00:23.30#ibcon#about to read 4, iclass 4, count 2 2006.173.06:00:23.30#ibcon#read 4, iclass 4, count 2 2006.173.06:00:23.30#ibcon#about to read 5, iclass 4, count 2 2006.173.06:00:23.30#ibcon#read 5, iclass 4, count 2 2006.173.06:00:23.30#ibcon#about to read 6, iclass 4, count 2 2006.173.06:00:23.30#ibcon#read 6, iclass 4, count 2 2006.173.06:00:23.30#ibcon#end of sib2, iclass 4, count 2 2006.173.06:00:23.30#ibcon#*mode == 0, iclass 4, count 2 2006.173.06:00:23.30#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.06:00:23.30#ibcon#[25=AT04-06\r\n] 2006.173.06:00:23.30#ibcon#*before write, iclass 4, count 2 2006.173.06:00:23.30#ibcon#enter sib2, iclass 4, count 2 2006.173.06:00:23.30#ibcon#flushed, iclass 4, count 2 2006.173.06:00:23.30#ibcon#about to write, iclass 4, count 2 2006.173.06:00:23.30#ibcon#wrote, iclass 4, count 2 2006.173.06:00:23.30#ibcon#about to read 3, iclass 4, count 2 2006.173.06:00:23.33#ibcon#read 3, iclass 4, count 2 2006.173.06:00:23.33#ibcon#about to read 4, iclass 4, count 2 2006.173.06:00:23.33#ibcon#read 4, iclass 4, count 2 2006.173.06:00:23.33#ibcon#about to read 5, iclass 4, count 2 2006.173.06:00:23.33#ibcon#read 5, iclass 4, count 2 2006.173.06:00:23.33#ibcon#about to read 6, iclass 4, count 2 2006.173.06:00:23.33#ibcon#read 6, iclass 4, count 2 2006.173.06:00:23.33#ibcon#end of sib2, iclass 4, count 2 2006.173.06:00:23.33#ibcon#*after write, iclass 4, count 2 2006.173.06:00:23.33#ibcon#*before return 0, iclass 4, count 2 2006.173.06:00:23.33#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.06:00:23.33#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.06:00:23.33#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.06:00:23.33#ibcon#ireg 7 cls_cnt 0 2006.173.06:00:23.33#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.06:00:23.45#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.06:00:23.45#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.06:00:23.45#ibcon#enter wrdev, iclass 4, count 0 2006.173.06:00:23.45#ibcon#first serial, iclass 4, count 0 2006.173.06:00:23.45#ibcon#enter sib2, iclass 4, count 0 2006.173.06:00:23.45#ibcon#flushed, iclass 4, count 0 2006.173.06:00:23.45#ibcon#about to write, iclass 4, count 0 2006.173.06:00:23.45#ibcon#wrote, iclass 4, count 0 2006.173.06:00:23.45#ibcon#about to read 3, iclass 4, count 0 2006.173.06:00:23.47#ibcon#read 3, iclass 4, count 0 2006.173.06:00:23.47#ibcon#about to read 4, iclass 4, count 0 2006.173.06:00:23.47#ibcon#read 4, iclass 4, count 0 2006.173.06:00:23.47#ibcon#about to read 5, iclass 4, count 0 2006.173.06:00:23.47#ibcon#read 5, iclass 4, count 0 2006.173.06:00:23.47#ibcon#about to read 6, iclass 4, count 0 2006.173.06:00:23.47#ibcon#read 6, iclass 4, count 0 2006.173.06:00:23.47#ibcon#end of sib2, iclass 4, count 0 2006.173.06:00:23.47#ibcon#*mode == 0, iclass 4, count 0 2006.173.06:00:23.47#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.06:00:23.47#ibcon#[25=USB\r\n] 2006.173.06:00:23.47#ibcon#*before write, iclass 4, count 0 2006.173.06:00:23.47#ibcon#enter sib2, iclass 4, count 0 2006.173.06:00:23.47#ibcon#flushed, iclass 4, count 0 2006.173.06:00:23.47#ibcon#about to write, iclass 4, count 0 2006.173.06:00:23.47#ibcon#wrote, iclass 4, count 0 2006.173.06:00:23.47#ibcon#about to read 3, iclass 4, count 0 2006.173.06:00:23.50#ibcon#read 3, iclass 4, count 0 2006.173.06:00:23.50#ibcon#about to read 4, iclass 4, count 0 2006.173.06:00:23.50#ibcon#read 4, iclass 4, count 0 2006.173.06:00:23.50#ibcon#about to read 5, iclass 4, count 0 2006.173.06:00:23.50#ibcon#read 5, iclass 4, count 0 2006.173.06:00:23.50#ibcon#about to read 6, iclass 4, count 0 2006.173.06:00:23.50#ibcon#read 6, iclass 4, count 0 2006.173.06:00:23.50#ibcon#end of sib2, iclass 4, count 0 2006.173.06:00:23.50#ibcon#*after write, iclass 4, count 0 2006.173.06:00:23.50#ibcon#*before return 0, iclass 4, count 0 2006.173.06:00:23.50#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.06:00:23.50#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.06:00:23.50#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.06:00:23.50#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.06:00:23.50$vck44/valo=5,734.99 2006.173.06:00:23.50#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.06:00:23.50#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.06:00:23.50#ibcon#ireg 17 cls_cnt 0 2006.173.06:00:23.50#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.06:00:23.50#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.06:00:23.50#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.06:00:23.50#ibcon#enter wrdev, iclass 6, count 0 2006.173.06:00:23.50#ibcon#first serial, iclass 6, count 0 2006.173.06:00:23.50#ibcon#enter sib2, iclass 6, count 0 2006.173.06:00:23.50#ibcon#flushed, iclass 6, count 0 2006.173.06:00:23.50#ibcon#about to write, iclass 6, count 0 2006.173.06:00:23.50#ibcon#wrote, iclass 6, count 0 2006.173.06:00:23.50#ibcon#about to read 3, iclass 6, count 0 2006.173.06:00:23.52#ibcon#read 3, iclass 6, count 0 2006.173.06:00:23.52#ibcon#about to read 4, iclass 6, count 0 2006.173.06:00:23.52#ibcon#read 4, iclass 6, count 0 2006.173.06:00:23.52#ibcon#about to read 5, iclass 6, count 0 2006.173.06:00:23.52#ibcon#read 5, iclass 6, count 0 2006.173.06:00:23.52#ibcon#about to read 6, iclass 6, count 0 2006.173.06:00:23.52#ibcon#read 6, iclass 6, count 0 2006.173.06:00:23.52#ibcon#end of sib2, iclass 6, count 0 2006.173.06:00:23.52#ibcon#*mode == 0, iclass 6, count 0 2006.173.06:00:23.52#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.06:00:23.52#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.06:00:23.52#ibcon#*before write, iclass 6, count 0 2006.173.06:00:23.52#ibcon#enter sib2, iclass 6, count 0 2006.173.06:00:23.52#ibcon#flushed, iclass 6, count 0 2006.173.06:00:23.52#ibcon#about to write, iclass 6, count 0 2006.173.06:00:23.52#ibcon#wrote, iclass 6, count 0 2006.173.06:00:23.52#ibcon#about to read 3, iclass 6, count 0 2006.173.06:00:23.56#ibcon#read 3, iclass 6, count 0 2006.173.06:00:23.56#ibcon#about to read 4, iclass 6, count 0 2006.173.06:00:23.56#ibcon#read 4, iclass 6, count 0 2006.173.06:00:23.56#ibcon#about to read 5, iclass 6, count 0 2006.173.06:00:23.56#ibcon#read 5, iclass 6, count 0 2006.173.06:00:23.56#ibcon#about to read 6, iclass 6, count 0 2006.173.06:00:23.56#ibcon#read 6, iclass 6, count 0 2006.173.06:00:23.56#ibcon#end of sib2, iclass 6, count 0 2006.173.06:00:23.56#ibcon#*after write, iclass 6, count 0 2006.173.06:00:23.56#ibcon#*before return 0, iclass 6, count 0 2006.173.06:00:23.56#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.06:00:23.56#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.06:00:23.56#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.06:00:23.56#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.06:00:23.56$vck44/va=5,4 2006.173.06:00:23.56#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.06:00:23.56#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.06:00:23.56#ibcon#ireg 11 cls_cnt 2 2006.173.06:00:23.56#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.06:00:23.62#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.06:00:23.62#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.06:00:23.62#ibcon#enter wrdev, iclass 10, count 2 2006.173.06:00:23.62#ibcon#first serial, iclass 10, count 2 2006.173.06:00:23.62#ibcon#enter sib2, iclass 10, count 2 2006.173.06:00:23.62#ibcon#flushed, iclass 10, count 2 2006.173.06:00:23.62#ibcon#about to write, iclass 10, count 2 2006.173.06:00:23.62#ibcon#wrote, iclass 10, count 2 2006.173.06:00:23.62#ibcon#about to read 3, iclass 10, count 2 2006.173.06:00:23.64#ibcon#read 3, iclass 10, count 2 2006.173.06:00:23.64#ibcon#about to read 4, iclass 10, count 2 2006.173.06:00:23.64#ibcon#read 4, iclass 10, count 2 2006.173.06:00:23.64#ibcon#about to read 5, iclass 10, count 2 2006.173.06:00:23.64#ibcon#read 5, iclass 10, count 2 2006.173.06:00:23.64#ibcon#about to read 6, iclass 10, count 2 2006.173.06:00:23.64#ibcon#read 6, iclass 10, count 2 2006.173.06:00:23.64#ibcon#end of sib2, iclass 10, count 2 2006.173.06:00:23.64#ibcon#*mode == 0, iclass 10, count 2 2006.173.06:00:23.64#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.06:00:23.64#ibcon#[25=AT05-04\r\n] 2006.173.06:00:23.64#ibcon#*before write, iclass 10, count 2 2006.173.06:00:23.64#ibcon#enter sib2, iclass 10, count 2 2006.173.06:00:23.64#ibcon#flushed, iclass 10, count 2 2006.173.06:00:23.64#ibcon#about to write, iclass 10, count 2 2006.173.06:00:23.64#ibcon#wrote, iclass 10, count 2 2006.173.06:00:23.64#ibcon#about to read 3, iclass 10, count 2 2006.173.06:00:23.67#ibcon#read 3, iclass 10, count 2 2006.173.06:00:23.67#ibcon#about to read 4, iclass 10, count 2 2006.173.06:00:23.67#ibcon#read 4, iclass 10, count 2 2006.173.06:00:23.67#ibcon#about to read 5, iclass 10, count 2 2006.173.06:00:23.67#ibcon#read 5, iclass 10, count 2 2006.173.06:00:23.67#ibcon#about to read 6, iclass 10, count 2 2006.173.06:00:23.67#ibcon#read 6, iclass 10, count 2 2006.173.06:00:23.67#ibcon#end of sib2, iclass 10, count 2 2006.173.06:00:23.67#ibcon#*after write, iclass 10, count 2 2006.173.06:00:23.67#ibcon#*before return 0, iclass 10, count 2 2006.173.06:00:23.67#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.06:00:23.67#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.06:00:23.67#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.06:00:23.67#ibcon#ireg 7 cls_cnt 0 2006.173.06:00:23.67#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.06:00:23.79#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.06:00:23.79#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.06:00:23.79#ibcon#enter wrdev, iclass 10, count 0 2006.173.06:00:23.79#ibcon#first serial, iclass 10, count 0 2006.173.06:00:23.79#ibcon#enter sib2, iclass 10, count 0 2006.173.06:00:23.79#ibcon#flushed, iclass 10, count 0 2006.173.06:00:23.79#ibcon#about to write, iclass 10, count 0 2006.173.06:00:23.79#ibcon#wrote, iclass 10, count 0 2006.173.06:00:23.79#ibcon#about to read 3, iclass 10, count 0 2006.173.06:00:23.81#ibcon#read 3, iclass 10, count 0 2006.173.06:00:23.81#ibcon#about to read 4, iclass 10, count 0 2006.173.06:00:23.81#ibcon#read 4, iclass 10, count 0 2006.173.06:00:23.81#ibcon#about to read 5, iclass 10, count 0 2006.173.06:00:23.81#ibcon#read 5, iclass 10, count 0 2006.173.06:00:23.81#ibcon#about to read 6, iclass 10, count 0 2006.173.06:00:23.81#ibcon#read 6, iclass 10, count 0 2006.173.06:00:23.81#ibcon#end of sib2, iclass 10, count 0 2006.173.06:00:23.81#ibcon#*mode == 0, iclass 10, count 0 2006.173.06:00:23.81#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.06:00:23.81#ibcon#[25=USB\r\n] 2006.173.06:00:23.81#ibcon#*before write, iclass 10, count 0 2006.173.06:00:23.81#ibcon#enter sib2, iclass 10, count 0 2006.173.06:00:23.81#ibcon#flushed, iclass 10, count 0 2006.173.06:00:23.81#ibcon#about to write, iclass 10, count 0 2006.173.06:00:23.81#ibcon#wrote, iclass 10, count 0 2006.173.06:00:23.81#ibcon#about to read 3, iclass 10, count 0 2006.173.06:00:23.84#ibcon#read 3, iclass 10, count 0 2006.173.06:00:23.84#ibcon#about to read 4, iclass 10, count 0 2006.173.06:00:23.84#ibcon#read 4, iclass 10, count 0 2006.173.06:00:23.84#ibcon#about to read 5, iclass 10, count 0 2006.173.06:00:23.84#ibcon#read 5, iclass 10, count 0 2006.173.06:00:23.84#ibcon#about to read 6, iclass 10, count 0 2006.173.06:00:23.84#ibcon#read 6, iclass 10, count 0 2006.173.06:00:23.84#ibcon#end of sib2, iclass 10, count 0 2006.173.06:00:23.84#ibcon#*after write, iclass 10, count 0 2006.173.06:00:23.84#ibcon#*before return 0, iclass 10, count 0 2006.173.06:00:23.84#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.06:00:23.84#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.06:00:23.84#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.06:00:23.84#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.06:00:23.84$vck44/valo=6,814.99 2006.173.06:00:23.84#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.06:00:23.84#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.06:00:23.84#ibcon#ireg 17 cls_cnt 0 2006.173.06:00:23.84#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.06:00:23.84#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.06:00:23.84#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.06:00:23.84#ibcon#enter wrdev, iclass 12, count 0 2006.173.06:00:23.84#ibcon#first serial, iclass 12, count 0 2006.173.06:00:23.84#ibcon#enter sib2, iclass 12, count 0 2006.173.06:00:23.84#ibcon#flushed, iclass 12, count 0 2006.173.06:00:23.84#ibcon#about to write, iclass 12, count 0 2006.173.06:00:23.84#ibcon#wrote, iclass 12, count 0 2006.173.06:00:23.84#ibcon#about to read 3, iclass 12, count 0 2006.173.06:00:23.86#ibcon#read 3, iclass 12, count 0 2006.173.06:00:23.86#ibcon#about to read 4, iclass 12, count 0 2006.173.06:00:23.86#ibcon#read 4, iclass 12, count 0 2006.173.06:00:23.86#ibcon#about to read 5, iclass 12, count 0 2006.173.06:00:23.86#ibcon#read 5, iclass 12, count 0 2006.173.06:00:23.86#ibcon#about to read 6, iclass 12, count 0 2006.173.06:00:23.86#ibcon#read 6, iclass 12, count 0 2006.173.06:00:23.86#ibcon#end of sib2, iclass 12, count 0 2006.173.06:00:23.86#ibcon#*mode == 0, iclass 12, count 0 2006.173.06:00:23.86#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.06:00:23.86#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.06:00:23.86#ibcon#*before write, iclass 12, count 0 2006.173.06:00:23.86#ibcon#enter sib2, iclass 12, count 0 2006.173.06:00:23.86#ibcon#flushed, iclass 12, count 0 2006.173.06:00:23.86#ibcon#about to write, iclass 12, count 0 2006.173.06:00:23.86#ibcon#wrote, iclass 12, count 0 2006.173.06:00:23.86#ibcon#about to read 3, iclass 12, count 0 2006.173.06:00:23.90#ibcon#read 3, iclass 12, count 0 2006.173.06:00:23.90#ibcon#about to read 4, iclass 12, count 0 2006.173.06:00:23.90#ibcon#read 4, iclass 12, count 0 2006.173.06:00:23.90#ibcon#about to read 5, iclass 12, count 0 2006.173.06:00:23.90#ibcon#read 5, iclass 12, count 0 2006.173.06:00:23.90#ibcon#about to read 6, iclass 12, count 0 2006.173.06:00:23.90#ibcon#read 6, iclass 12, count 0 2006.173.06:00:23.90#ibcon#end of sib2, iclass 12, count 0 2006.173.06:00:23.90#ibcon#*after write, iclass 12, count 0 2006.173.06:00:23.90#ibcon#*before return 0, iclass 12, count 0 2006.173.06:00:23.90#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.06:00:23.90#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.06:00:23.90#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.06:00:23.90#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.06:00:23.90$vck44/va=6,3 2006.173.06:00:23.90#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.06:00:23.90#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.06:00:23.90#ibcon#ireg 11 cls_cnt 2 2006.173.06:00:23.90#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.06:00:23.96#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.06:00:23.96#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.06:00:23.96#ibcon#enter wrdev, iclass 14, count 2 2006.173.06:00:23.96#ibcon#first serial, iclass 14, count 2 2006.173.06:00:23.96#ibcon#enter sib2, iclass 14, count 2 2006.173.06:00:23.96#ibcon#flushed, iclass 14, count 2 2006.173.06:00:23.96#ibcon#about to write, iclass 14, count 2 2006.173.06:00:23.96#ibcon#wrote, iclass 14, count 2 2006.173.06:00:23.96#ibcon#about to read 3, iclass 14, count 2 2006.173.06:00:23.98#ibcon#read 3, iclass 14, count 2 2006.173.06:00:23.98#ibcon#about to read 4, iclass 14, count 2 2006.173.06:00:23.98#ibcon#read 4, iclass 14, count 2 2006.173.06:00:23.98#ibcon#about to read 5, iclass 14, count 2 2006.173.06:00:23.98#ibcon#read 5, iclass 14, count 2 2006.173.06:00:23.98#ibcon#about to read 6, iclass 14, count 2 2006.173.06:00:23.98#ibcon#read 6, iclass 14, count 2 2006.173.06:00:23.98#ibcon#end of sib2, iclass 14, count 2 2006.173.06:00:23.98#ibcon#*mode == 0, iclass 14, count 2 2006.173.06:00:23.98#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.06:00:23.98#ibcon#[25=AT06-03\r\n] 2006.173.06:00:23.98#ibcon#*before write, iclass 14, count 2 2006.173.06:00:23.98#ibcon#enter sib2, iclass 14, count 2 2006.173.06:00:23.98#ibcon#flushed, iclass 14, count 2 2006.173.06:00:23.98#ibcon#about to write, iclass 14, count 2 2006.173.06:00:23.98#ibcon#wrote, iclass 14, count 2 2006.173.06:00:23.98#ibcon#about to read 3, iclass 14, count 2 2006.173.06:00:24.01#ibcon#read 3, iclass 14, count 2 2006.173.06:00:24.01#ibcon#about to read 4, iclass 14, count 2 2006.173.06:00:24.01#ibcon#read 4, iclass 14, count 2 2006.173.06:00:24.01#ibcon#about to read 5, iclass 14, count 2 2006.173.06:00:24.01#ibcon#read 5, iclass 14, count 2 2006.173.06:00:24.01#ibcon#about to read 6, iclass 14, count 2 2006.173.06:00:24.01#ibcon#read 6, iclass 14, count 2 2006.173.06:00:24.01#ibcon#end of sib2, iclass 14, count 2 2006.173.06:00:24.01#ibcon#*after write, iclass 14, count 2 2006.173.06:00:24.01#ibcon#*before return 0, iclass 14, count 2 2006.173.06:00:24.01#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.06:00:24.01#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.06:00:24.01#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.06:00:24.01#ibcon#ireg 7 cls_cnt 0 2006.173.06:00:24.01#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.06:00:24.13#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.06:00:24.13#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.06:00:24.13#ibcon#enter wrdev, iclass 14, count 0 2006.173.06:00:24.13#ibcon#first serial, iclass 14, count 0 2006.173.06:00:24.13#ibcon#enter sib2, iclass 14, count 0 2006.173.06:00:24.13#ibcon#flushed, iclass 14, count 0 2006.173.06:00:24.13#ibcon#about to write, iclass 14, count 0 2006.173.06:00:24.13#ibcon#wrote, iclass 14, count 0 2006.173.06:00:24.13#ibcon#about to read 3, iclass 14, count 0 2006.173.06:00:24.15#ibcon#read 3, iclass 14, count 0 2006.173.06:00:24.15#ibcon#about to read 4, iclass 14, count 0 2006.173.06:00:24.15#ibcon#read 4, iclass 14, count 0 2006.173.06:00:24.15#ibcon#about to read 5, iclass 14, count 0 2006.173.06:00:24.15#ibcon#read 5, iclass 14, count 0 2006.173.06:00:24.15#ibcon#about to read 6, iclass 14, count 0 2006.173.06:00:24.15#ibcon#read 6, iclass 14, count 0 2006.173.06:00:24.15#ibcon#end of sib2, iclass 14, count 0 2006.173.06:00:24.15#ibcon#*mode == 0, iclass 14, count 0 2006.173.06:00:24.15#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.06:00:24.15#ibcon#[25=USB\r\n] 2006.173.06:00:24.15#ibcon#*before write, iclass 14, count 0 2006.173.06:00:24.15#ibcon#enter sib2, iclass 14, count 0 2006.173.06:00:24.15#ibcon#flushed, iclass 14, count 0 2006.173.06:00:24.15#ibcon#about to write, iclass 14, count 0 2006.173.06:00:24.15#ibcon#wrote, iclass 14, count 0 2006.173.06:00:24.15#ibcon#about to read 3, iclass 14, count 0 2006.173.06:00:24.18#ibcon#read 3, iclass 14, count 0 2006.173.06:00:24.18#ibcon#about to read 4, iclass 14, count 0 2006.173.06:00:24.18#ibcon#read 4, iclass 14, count 0 2006.173.06:00:24.18#ibcon#about to read 5, iclass 14, count 0 2006.173.06:00:24.18#ibcon#read 5, iclass 14, count 0 2006.173.06:00:24.18#ibcon#about to read 6, iclass 14, count 0 2006.173.06:00:24.18#ibcon#read 6, iclass 14, count 0 2006.173.06:00:24.18#ibcon#end of sib2, iclass 14, count 0 2006.173.06:00:24.18#ibcon#*after write, iclass 14, count 0 2006.173.06:00:24.18#ibcon#*before return 0, iclass 14, count 0 2006.173.06:00:24.18#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.06:00:24.18#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.06:00:24.18#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.06:00:24.18#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.06:00:24.18$vck44/valo=7,864.99 2006.173.06:00:24.18#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.06:00:24.18#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.06:00:24.18#ibcon#ireg 17 cls_cnt 0 2006.173.06:00:24.18#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.06:00:24.18#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.06:00:24.18#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.06:00:24.18#ibcon#enter wrdev, iclass 16, count 0 2006.173.06:00:24.18#ibcon#first serial, iclass 16, count 0 2006.173.06:00:24.18#ibcon#enter sib2, iclass 16, count 0 2006.173.06:00:24.18#ibcon#flushed, iclass 16, count 0 2006.173.06:00:24.18#ibcon#about to write, iclass 16, count 0 2006.173.06:00:24.18#ibcon#wrote, iclass 16, count 0 2006.173.06:00:24.18#ibcon#about to read 3, iclass 16, count 0 2006.173.06:00:24.20#ibcon#read 3, iclass 16, count 0 2006.173.06:00:24.20#ibcon#about to read 4, iclass 16, count 0 2006.173.06:00:24.20#ibcon#read 4, iclass 16, count 0 2006.173.06:00:24.20#ibcon#about to read 5, iclass 16, count 0 2006.173.06:00:24.20#ibcon#read 5, iclass 16, count 0 2006.173.06:00:24.20#ibcon#about to read 6, iclass 16, count 0 2006.173.06:00:24.20#ibcon#read 6, iclass 16, count 0 2006.173.06:00:24.20#ibcon#end of sib2, iclass 16, count 0 2006.173.06:00:24.20#ibcon#*mode == 0, iclass 16, count 0 2006.173.06:00:24.20#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.06:00:24.20#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.06:00:24.20#ibcon#*before write, iclass 16, count 0 2006.173.06:00:24.20#ibcon#enter sib2, iclass 16, count 0 2006.173.06:00:24.20#ibcon#flushed, iclass 16, count 0 2006.173.06:00:24.20#ibcon#about to write, iclass 16, count 0 2006.173.06:00:24.20#ibcon#wrote, iclass 16, count 0 2006.173.06:00:24.20#ibcon#about to read 3, iclass 16, count 0 2006.173.06:00:24.24#ibcon#read 3, iclass 16, count 0 2006.173.06:00:24.24#ibcon#about to read 4, iclass 16, count 0 2006.173.06:00:24.24#ibcon#read 4, iclass 16, count 0 2006.173.06:00:24.24#ibcon#about to read 5, iclass 16, count 0 2006.173.06:00:24.24#ibcon#read 5, iclass 16, count 0 2006.173.06:00:24.24#ibcon#about to read 6, iclass 16, count 0 2006.173.06:00:24.24#ibcon#read 6, iclass 16, count 0 2006.173.06:00:24.24#ibcon#end of sib2, iclass 16, count 0 2006.173.06:00:24.24#ibcon#*after write, iclass 16, count 0 2006.173.06:00:24.24#ibcon#*before return 0, iclass 16, count 0 2006.173.06:00:24.24#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.06:00:24.24#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.06:00:24.24#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.06:00:24.24#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.06:00:24.24$vck44/va=7,4 2006.173.06:00:24.24#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.06:00:24.24#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.06:00:24.24#ibcon#ireg 11 cls_cnt 2 2006.173.06:00:24.24#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.06:00:24.30#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.06:00:24.30#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.06:00:24.30#ibcon#enter wrdev, iclass 18, count 2 2006.173.06:00:24.30#ibcon#first serial, iclass 18, count 2 2006.173.06:00:24.30#ibcon#enter sib2, iclass 18, count 2 2006.173.06:00:24.30#ibcon#flushed, iclass 18, count 2 2006.173.06:00:24.30#ibcon#about to write, iclass 18, count 2 2006.173.06:00:24.30#ibcon#wrote, iclass 18, count 2 2006.173.06:00:24.30#ibcon#about to read 3, iclass 18, count 2 2006.173.06:00:24.32#ibcon#read 3, iclass 18, count 2 2006.173.06:00:24.32#ibcon#about to read 4, iclass 18, count 2 2006.173.06:00:24.32#ibcon#read 4, iclass 18, count 2 2006.173.06:00:24.32#ibcon#about to read 5, iclass 18, count 2 2006.173.06:00:24.32#ibcon#read 5, iclass 18, count 2 2006.173.06:00:24.32#ibcon#about to read 6, iclass 18, count 2 2006.173.06:00:24.32#ibcon#read 6, iclass 18, count 2 2006.173.06:00:24.32#ibcon#end of sib2, iclass 18, count 2 2006.173.06:00:24.32#ibcon#*mode == 0, iclass 18, count 2 2006.173.06:00:24.32#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.06:00:24.32#ibcon#[25=AT07-04\r\n] 2006.173.06:00:24.32#ibcon#*before write, iclass 18, count 2 2006.173.06:00:24.32#ibcon#enter sib2, iclass 18, count 2 2006.173.06:00:24.32#ibcon#flushed, iclass 18, count 2 2006.173.06:00:24.32#ibcon#about to write, iclass 18, count 2 2006.173.06:00:24.32#ibcon#wrote, iclass 18, count 2 2006.173.06:00:24.32#ibcon#about to read 3, iclass 18, count 2 2006.173.06:00:24.35#ibcon#read 3, iclass 18, count 2 2006.173.06:00:24.35#ibcon#about to read 4, iclass 18, count 2 2006.173.06:00:24.35#ibcon#read 4, iclass 18, count 2 2006.173.06:00:24.35#ibcon#about to read 5, iclass 18, count 2 2006.173.06:00:24.35#ibcon#read 5, iclass 18, count 2 2006.173.06:00:24.35#ibcon#about to read 6, iclass 18, count 2 2006.173.06:00:24.35#ibcon#read 6, iclass 18, count 2 2006.173.06:00:24.35#ibcon#end of sib2, iclass 18, count 2 2006.173.06:00:24.35#ibcon#*after write, iclass 18, count 2 2006.173.06:00:24.35#ibcon#*before return 0, iclass 18, count 2 2006.173.06:00:24.35#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.06:00:24.35#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.06:00:24.35#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.06:00:24.35#ibcon#ireg 7 cls_cnt 0 2006.173.06:00:24.35#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.06:00:24.47#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.06:00:24.47#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.06:00:24.47#ibcon#enter wrdev, iclass 18, count 0 2006.173.06:00:24.47#ibcon#first serial, iclass 18, count 0 2006.173.06:00:24.47#ibcon#enter sib2, iclass 18, count 0 2006.173.06:00:24.47#ibcon#flushed, iclass 18, count 0 2006.173.06:00:24.47#ibcon#about to write, iclass 18, count 0 2006.173.06:00:24.47#ibcon#wrote, iclass 18, count 0 2006.173.06:00:24.47#ibcon#about to read 3, iclass 18, count 0 2006.173.06:00:24.49#ibcon#read 3, iclass 18, count 0 2006.173.06:00:24.49#ibcon#about to read 4, iclass 18, count 0 2006.173.06:00:24.49#ibcon#read 4, iclass 18, count 0 2006.173.06:00:24.49#ibcon#about to read 5, iclass 18, count 0 2006.173.06:00:24.49#ibcon#read 5, iclass 18, count 0 2006.173.06:00:24.49#ibcon#about to read 6, iclass 18, count 0 2006.173.06:00:24.49#ibcon#read 6, iclass 18, count 0 2006.173.06:00:24.49#ibcon#end of sib2, iclass 18, count 0 2006.173.06:00:24.49#ibcon#*mode == 0, iclass 18, count 0 2006.173.06:00:24.49#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.06:00:24.49#ibcon#[25=USB\r\n] 2006.173.06:00:24.49#ibcon#*before write, iclass 18, count 0 2006.173.06:00:24.49#ibcon#enter sib2, iclass 18, count 0 2006.173.06:00:24.49#ibcon#flushed, iclass 18, count 0 2006.173.06:00:24.49#ibcon#about to write, iclass 18, count 0 2006.173.06:00:24.49#ibcon#wrote, iclass 18, count 0 2006.173.06:00:24.49#ibcon#about to read 3, iclass 18, count 0 2006.173.06:00:24.52#ibcon#read 3, iclass 18, count 0 2006.173.06:00:24.52#ibcon#about to read 4, iclass 18, count 0 2006.173.06:00:24.52#ibcon#read 4, iclass 18, count 0 2006.173.06:00:24.52#ibcon#about to read 5, iclass 18, count 0 2006.173.06:00:24.52#ibcon#read 5, iclass 18, count 0 2006.173.06:00:24.52#ibcon#about to read 6, iclass 18, count 0 2006.173.06:00:24.52#ibcon#read 6, iclass 18, count 0 2006.173.06:00:24.52#ibcon#end of sib2, iclass 18, count 0 2006.173.06:00:24.52#ibcon#*after write, iclass 18, count 0 2006.173.06:00:24.52#ibcon#*before return 0, iclass 18, count 0 2006.173.06:00:24.52#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.06:00:24.52#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.06:00:24.52#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.06:00:24.52#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.06:00:24.52$vck44/valo=8,884.99 2006.173.06:00:24.52#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.06:00:24.52#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.06:00:24.52#ibcon#ireg 17 cls_cnt 0 2006.173.06:00:24.52#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.06:00:24.52#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.06:00:24.52#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.06:00:24.52#ibcon#enter wrdev, iclass 20, count 0 2006.173.06:00:24.52#ibcon#first serial, iclass 20, count 0 2006.173.06:00:24.52#ibcon#enter sib2, iclass 20, count 0 2006.173.06:00:24.52#ibcon#flushed, iclass 20, count 0 2006.173.06:00:24.52#ibcon#about to write, iclass 20, count 0 2006.173.06:00:24.52#ibcon#wrote, iclass 20, count 0 2006.173.06:00:24.52#ibcon#about to read 3, iclass 20, count 0 2006.173.06:00:24.54#ibcon#read 3, iclass 20, count 0 2006.173.06:00:24.54#ibcon#about to read 4, iclass 20, count 0 2006.173.06:00:24.54#ibcon#read 4, iclass 20, count 0 2006.173.06:00:24.54#ibcon#about to read 5, iclass 20, count 0 2006.173.06:00:24.54#ibcon#read 5, iclass 20, count 0 2006.173.06:00:24.54#ibcon#about to read 6, iclass 20, count 0 2006.173.06:00:24.54#ibcon#read 6, iclass 20, count 0 2006.173.06:00:24.54#ibcon#end of sib2, iclass 20, count 0 2006.173.06:00:24.54#ibcon#*mode == 0, iclass 20, count 0 2006.173.06:00:24.54#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.06:00:24.54#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.06:00:24.54#ibcon#*before write, iclass 20, count 0 2006.173.06:00:24.54#ibcon#enter sib2, iclass 20, count 0 2006.173.06:00:24.54#ibcon#flushed, iclass 20, count 0 2006.173.06:00:24.54#ibcon#about to write, iclass 20, count 0 2006.173.06:00:24.54#ibcon#wrote, iclass 20, count 0 2006.173.06:00:24.54#ibcon#about to read 3, iclass 20, count 0 2006.173.06:00:24.58#ibcon#read 3, iclass 20, count 0 2006.173.06:00:24.58#ibcon#about to read 4, iclass 20, count 0 2006.173.06:00:24.58#ibcon#read 4, iclass 20, count 0 2006.173.06:00:24.58#ibcon#about to read 5, iclass 20, count 0 2006.173.06:00:24.58#ibcon#read 5, iclass 20, count 0 2006.173.06:00:24.58#ibcon#about to read 6, iclass 20, count 0 2006.173.06:00:24.58#ibcon#read 6, iclass 20, count 0 2006.173.06:00:24.58#ibcon#end of sib2, iclass 20, count 0 2006.173.06:00:24.58#ibcon#*after write, iclass 20, count 0 2006.173.06:00:24.58#ibcon#*before return 0, iclass 20, count 0 2006.173.06:00:24.58#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.06:00:24.58#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.06:00:24.58#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.06:00:24.58#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.06:00:24.58$vck44/va=8,4 2006.173.06:00:24.58#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.06:00:24.58#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.06:00:24.58#ibcon#ireg 11 cls_cnt 2 2006.173.06:00:24.58#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.06:00:24.64#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.06:00:24.64#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.06:00:24.64#ibcon#enter wrdev, iclass 22, count 2 2006.173.06:00:24.64#ibcon#first serial, iclass 22, count 2 2006.173.06:00:24.64#ibcon#enter sib2, iclass 22, count 2 2006.173.06:00:24.64#ibcon#flushed, iclass 22, count 2 2006.173.06:00:24.64#ibcon#about to write, iclass 22, count 2 2006.173.06:00:24.64#ibcon#wrote, iclass 22, count 2 2006.173.06:00:24.64#ibcon#about to read 3, iclass 22, count 2 2006.173.06:00:24.66#ibcon#read 3, iclass 22, count 2 2006.173.06:00:24.66#ibcon#about to read 4, iclass 22, count 2 2006.173.06:00:24.66#ibcon#read 4, iclass 22, count 2 2006.173.06:00:24.66#ibcon#about to read 5, iclass 22, count 2 2006.173.06:00:24.66#ibcon#read 5, iclass 22, count 2 2006.173.06:00:24.66#ibcon#about to read 6, iclass 22, count 2 2006.173.06:00:24.66#ibcon#read 6, iclass 22, count 2 2006.173.06:00:24.66#ibcon#end of sib2, iclass 22, count 2 2006.173.06:00:24.66#ibcon#*mode == 0, iclass 22, count 2 2006.173.06:00:24.66#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.06:00:24.66#ibcon#[25=AT08-04\r\n] 2006.173.06:00:24.66#ibcon#*before write, iclass 22, count 2 2006.173.06:00:24.66#ibcon#enter sib2, iclass 22, count 2 2006.173.06:00:24.66#ibcon#flushed, iclass 22, count 2 2006.173.06:00:24.66#ibcon#about to write, iclass 22, count 2 2006.173.06:00:24.66#ibcon#wrote, iclass 22, count 2 2006.173.06:00:24.66#ibcon#about to read 3, iclass 22, count 2 2006.173.06:00:24.69#ibcon#read 3, iclass 22, count 2 2006.173.06:00:24.69#ibcon#about to read 4, iclass 22, count 2 2006.173.06:00:24.69#ibcon#read 4, iclass 22, count 2 2006.173.06:00:24.69#ibcon#about to read 5, iclass 22, count 2 2006.173.06:00:24.69#ibcon#read 5, iclass 22, count 2 2006.173.06:00:24.69#ibcon#about to read 6, iclass 22, count 2 2006.173.06:00:24.69#ibcon#read 6, iclass 22, count 2 2006.173.06:00:24.69#ibcon#end of sib2, iclass 22, count 2 2006.173.06:00:24.69#ibcon#*after write, iclass 22, count 2 2006.173.06:00:24.69#ibcon#*before return 0, iclass 22, count 2 2006.173.06:00:24.69#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.06:00:24.69#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.06:00:24.69#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.06:00:24.69#ibcon#ireg 7 cls_cnt 0 2006.173.06:00:24.69#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.06:00:24.81#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.06:00:24.81#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.06:00:24.81#ibcon#enter wrdev, iclass 22, count 0 2006.173.06:00:24.81#ibcon#first serial, iclass 22, count 0 2006.173.06:00:24.81#ibcon#enter sib2, iclass 22, count 0 2006.173.06:00:24.81#ibcon#flushed, iclass 22, count 0 2006.173.06:00:24.81#ibcon#about to write, iclass 22, count 0 2006.173.06:00:24.81#ibcon#wrote, iclass 22, count 0 2006.173.06:00:24.81#ibcon#about to read 3, iclass 22, count 0 2006.173.06:00:24.83#ibcon#read 3, iclass 22, count 0 2006.173.06:00:24.83#ibcon#about to read 4, iclass 22, count 0 2006.173.06:00:24.83#ibcon#read 4, iclass 22, count 0 2006.173.06:00:24.83#ibcon#about to read 5, iclass 22, count 0 2006.173.06:00:24.83#ibcon#read 5, iclass 22, count 0 2006.173.06:00:24.83#ibcon#about to read 6, iclass 22, count 0 2006.173.06:00:24.83#ibcon#read 6, iclass 22, count 0 2006.173.06:00:24.83#ibcon#end of sib2, iclass 22, count 0 2006.173.06:00:24.83#ibcon#*mode == 0, iclass 22, count 0 2006.173.06:00:24.83#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.06:00:24.83#ibcon#[25=USB\r\n] 2006.173.06:00:24.83#ibcon#*before write, iclass 22, count 0 2006.173.06:00:24.83#ibcon#enter sib2, iclass 22, count 0 2006.173.06:00:24.83#ibcon#flushed, iclass 22, count 0 2006.173.06:00:24.83#ibcon#about to write, iclass 22, count 0 2006.173.06:00:24.83#ibcon#wrote, iclass 22, count 0 2006.173.06:00:24.83#ibcon#about to read 3, iclass 22, count 0 2006.173.06:00:24.86#ibcon#read 3, iclass 22, count 0 2006.173.06:00:24.86#ibcon#about to read 4, iclass 22, count 0 2006.173.06:00:24.86#ibcon#read 4, iclass 22, count 0 2006.173.06:00:24.86#ibcon#about to read 5, iclass 22, count 0 2006.173.06:00:24.86#ibcon#read 5, iclass 22, count 0 2006.173.06:00:24.86#ibcon#about to read 6, iclass 22, count 0 2006.173.06:00:24.86#ibcon#read 6, iclass 22, count 0 2006.173.06:00:24.86#ibcon#end of sib2, iclass 22, count 0 2006.173.06:00:24.86#ibcon#*after write, iclass 22, count 0 2006.173.06:00:24.86#ibcon#*before return 0, iclass 22, count 0 2006.173.06:00:24.86#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.06:00:24.86#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.06:00:24.86#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.06:00:24.86#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.06:00:24.86$vck44/vblo=1,629.99 2006.173.06:00:24.86#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.06:00:24.86#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.06:00:24.86#ibcon#ireg 17 cls_cnt 0 2006.173.06:00:24.86#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.06:00:24.86#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.06:00:24.86#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.06:00:24.86#ibcon#enter wrdev, iclass 24, count 0 2006.173.06:00:24.86#ibcon#first serial, iclass 24, count 0 2006.173.06:00:24.86#ibcon#enter sib2, iclass 24, count 0 2006.173.06:00:24.86#ibcon#flushed, iclass 24, count 0 2006.173.06:00:24.86#ibcon#about to write, iclass 24, count 0 2006.173.06:00:24.86#ibcon#wrote, iclass 24, count 0 2006.173.06:00:24.86#ibcon#about to read 3, iclass 24, count 0 2006.173.06:00:24.88#ibcon#read 3, iclass 24, count 0 2006.173.06:00:24.88#ibcon#about to read 4, iclass 24, count 0 2006.173.06:00:24.88#ibcon#read 4, iclass 24, count 0 2006.173.06:00:24.88#ibcon#about to read 5, iclass 24, count 0 2006.173.06:00:24.88#ibcon#read 5, iclass 24, count 0 2006.173.06:00:24.88#ibcon#about to read 6, iclass 24, count 0 2006.173.06:00:24.88#ibcon#read 6, iclass 24, count 0 2006.173.06:00:24.88#ibcon#end of sib2, iclass 24, count 0 2006.173.06:00:24.88#ibcon#*mode == 0, iclass 24, count 0 2006.173.06:00:24.88#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.06:00:24.88#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.06:00:24.88#ibcon#*before write, iclass 24, count 0 2006.173.06:00:24.88#ibcon#enter sib2, iclass 24, count 0 2006.173.06:00:24.88#ibcon#flushed, iclass 24, count 0 2006.173.06:00:24.88#ibcon#about to write, iclass 24, count 0 2006.173.06:00:24.88#ibcon#wrote, iclass 24, count 0 2006.173.06:00:24.88#ibcon#about to read 3, iclass 24, count 0 2006.173.06:00:24.92#ibcon#read 3, iclass 24, count 0 2006.173.06:00:24.92#ibcon#about to read 4, iclass 24, count 0 2006.173.06:00:24.92#ibcon#read 4, iclass 24, count 0 2006.173.06:00:24.92#ibcon#about to read 5, iclass 24, count 0 2006.173.06:00:24.92#ibcon#read 5, iclass 24, count 0 2006.173.06:00:24.92#ibcon#about to read 6, iclass 24, count 0 2006.173.06:00:24.92#ibcon#read 6, iclass 24, count 0 2006.173.06:00:24.92#ibcon#end of sib2, iclass 24, count 0 2006.173.06:00:24.92#ibcon#*after write, iclass 24, count 0 2006.173.06:00:24.92#ibcon#*before return 0, iclass 24, count 0 2006.173.06:00:24.92#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.06:00:24.92#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.06:00:24.92#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.06:00:24.92#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.06:00:24.92$vck44/vb=1,4 2006.173.06:00:24.92#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.06:00:24.92#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.06:00:24.92#ibcon#ireg 11 cls_cnt 2 2006.173.06:00:24.92#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.06:00:24.92#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.06:00:24.92#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.06:00:24.92#ibcon#enter wrdev, iclass 26, count 2 2006.173.06:00:24.92#ibcon#first serial, iclass 26, count 2 2006.173.06:00:24.92#ibcon#enter sib2, iclass 26, count 2 2006.173.06:00:24.92#ibcon#flushed, iclass 26, count 2 2006.173.06:00:24.92#ibcon#about to write, iclass 26, count 2 2006.173.06:00:24.92#ibcon#wrote, iclass 26, count 2 2006.173.06:00:24.92#ibcon#about to read 3, iclass 26, count 2 2006.173.06:00:24.94#ibcon#read 3, iclass 26, count 2 2006.173.06:00:24.94#ibcon#about to read 4, iclass 26, count 2 2006.173.06:00:24.94#ibcon#read 4, iclass 26, count 2 2006.173.06:00:24.94#ibcon#about to read 5, iclass 26, count 2 2006.173.06:00:24.94#ibcon#read 5, iclass 26, count 2 2006.173.06:00:24.94#ibcon#about to read 6, iclass 26, count 2 2006.173.06:00:24.94#ibcon#read 6, iclass 26, count 2 2006.173.06:00:24.94#ibcon#end of sib2, iclass 26, count 2 2006.173.06:00:24.94#ibcon#*mode == 0, iclass 26, count 2 2006.173.06:00:24.94#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.06:00:24.94#ibcon#[27=AT01-04\r\n] 2006.173.06:00:24.94#ibcon#*before write, iclass 26, count 2 2006.173.06:00:24.94#ibcon#enter sib2, iclass 26, count 2 2006.173.06:00:24.94#ibcon#flushed, iclass 26, count 2 2006.173.06:00:24.94#ibcon#about to write, iclass 26, count 2 2006.173.06:00:24.94#ibcon#wrote, iclass 26, count 2 2006.173.06:00:24.94#ibcon#about to read 3, iclass 26, count 2 2006.173.06:00:24.97#ibcon#read 3, iclass 26, count 2 2006.173.06:00:24.97#ibcon#about to read 4, iclass 26, count 2 2006.173.06:00:24.97#ibcon#read 4, iclass 26, count 2 2006.173.06:00:24.97#ibcon#about to read 5, iclass 26, count 2 2006.173.06:00:24.97#ibcon#read 5, iclass 26, count 2 2006.173.06:00:24.97#ibcon#about to read 6, iclass 26, count 2 2006.173.06:00:24.97#ibcon#read 6, iclass 26, count 2 2006.173.06:00:24.97#ibcon#end of sib2, iclass 26, count 2 2006.173.06:00:24.97#ibcon#*after write, iclass 26, count 2 2006.173.06:00:24.97#ibcon#*before return 0, iclass 26, count 2 2006.173.06:00:24.97#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.06:00:24.97#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.06:00:24.97#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.06:00:24.97#ibcon#ireg 7 cls_cnt 0 2006.173.06:00:24.97#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.06:00:25.09#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.06:00:25.09#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.06:00:25.09#ibcon#enter wrdev, iclass 26, count 0 2006.173.06:00:25.09#ibcon#first serial, iclass 26, count 0 2006.173.06:00:25.09#ibcon#enter sib2, iclass 26, count 0 2006.173.06:00:25.09#ibcon#flushed, iclass 26, count 0 2006.173.06:00:25.09#ibcon#about to write, iclass 26, count 0 2006.173.06:00:25.09#ibcon#wrote, iclass 26, count 0 2006.173.06:00:25.09#ibcon#about to read 3, iclass 26, count 0 2006.173.06:00:25.11#ibcon#read 3, iclass 26, count 0 2006.173.06:00:25.11#ibcon#about to read 4, iclass 26, count 0 2006.173.06:00:25.11#ibcon#read 4, iclass 26, count 0 2006.173.06:00:25.11#ibcon#about to read 5, iclass 26, count 0 2006.173.06:00:25.11#ibcon#read 5, iclass 26, count 0 2006.173.06:00:25.11#ibcon#about to read 6, iclass 26, count 0 2006.173.06:00:25.11#ibcon#read 6, iclass 26, count 0 2006.173.06:00:25.11#ibcon#end of sib2, iclass 26, count 0 2006.173.06:00:25.11#ibcon#*mode == 0, iclass 26, count 0 2006.173.06:00:25.11#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.06:00:25.11#ibcon#[27=USB\r\n] 2006.173.06:00:25.11#ibcon#*before write, iclass 26, count 0 2006.173.06:00:25.11#ibcon#enter sib2, iclass 26, count 0 2006.173.06:00:25.11#ibcon#flushed, iclass 26, count 0 2006.173.06:00:25.11#ibcon#about to write, iclass 26, count 0 2006.173.06:00:25.11#ibcon#wrote, iclass 26, count 0 2006.173.06:00:25.11#ibcon#about to read 3, iclass 26, count 0 2006.173.06:00:25.14#ibcon#read 3, iclass 26, count 0 2006.173.06:00:25.14#ibcon#about to read 4, iclass 26, count 0 2006.173.06:00:25.14#ibcon#read 4, iclass 26, count 0 2006.173.06:00:25.14#ibcon#about to read 5, iclass 26, count 0 2006.173.06:00:25.14#ibcon#read 5, iclass 26, count 0 2006.173.06:00:25.14#ibcon#about to read 6, iclass 26, count 0 2006.173.06:00:25.14#ibcon#read 6, iclass 26, count 0 2006.173.06:00:25.14#ibcon#end of sib2, iclass 26, count 0 2006.173.06:00:25.14#ibcon#*after write, iclass 26, count 0 2006.173.06:00:25.14#ibcon#*before return 0, iclass 26, count 0 2006.173.06:00:25.14#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.06:00:25.14#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.06:00:25.14#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.06:00:25.14#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.06:00:25.14$vck44/vblo=2,634.99 2006.173.06:00:25.14#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.06:00:25.14#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.06:00:25.14#ibcon#ireg 17 cls_cnt 0 2006.173.06:00:25.15#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.06:00:25.15#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.06:00:25.15#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.06:00:25.15#ibcon#enter wrdev, iclass 28, count 0 2006.173.06:00:25.15#ibcon#first serial, iclass 28, count 0 2006.173.06:00:25.15#ibcon#enter sib2, iclass 28, count 0 2006.173.06:00:25.15#ibcon#flushed, iclass 28, count 0 2006.173.06:00:25.15#ibcon#about to write, iclass 28, count 0 2006.173.06:00:25.15#ibcon#wrote, iclass 28, count 0 2006.173.06:00:25.15#ibcon#about to read 3, iclass 28, count 0 2006.173.06:00:25.16#ibcon#read 3, iclass 28, count 0 2006.173.06:00:25.16#ibcon#about to read 4, iclass 28, count 0 2006.173.06:00:25.16#ibcon#read 4, iclass 28, count 0 2006.173.06:00:25.16#ibcon#about to read 5, iclass 28, count 0 2006.173.06:00:25.16#ibcon#read 5, iclass 28, count 0 2006.173.06:00:25.16#ibcon#about to read 6, iclass 28, count 0 2006.173.06:00:25.16#ibcon#read 6, iclass 28, count 0 2006.173.06:00:25.16#ibcon#end of sib2, iclass 28, count 0 2006.173.06:00:25.16#ibcon#*mode == 0, iclass 28, count 0 2006.173.06:00:25.16#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.06:00:25.16#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.06:00:25.16#ibcon#*before write, iclass 28, count 0 2006.173.06:00:25.16#ibcon#enter sib2, iclass 28, count 0 2006.173.06:00:25.16#ibcon#flushed, iclass 28, count 0 2006.173.06:00:25.16#ibcon#about to write, iclass 28, count 0 2006.173.06:00:25.16#ibcon#wrote, iclass 28, count 0 2006.173.06:00:25.16#ibcon#about to read 3, iclass 28, count 0 2006.173.06:00:25.20#ibcon#read 3, iclass 28, count 0 2006.173.06:00:25.20#ibcon#about to read 4, iclass 28, count 0 2006.173.06:00:25.20#ibcon#read 4, iclass 28, count 0 2006.173.06:00:25.20#ibcon#about to read 5, iclass 28, count 0 2006.173.06:00:25.20#ibcon#read 5, iclass 28, count 0 2006.173.06:00:25.20#ibcon#about to read 6, iclass 28, count 0 2006.173.06:00:25.20#ibcon#read 6, iclass 28, count 0 2006.173.06:00:25.20#ibcon#end of sib2, iclass 28, count 0 2006.173.06:00:25.20#ibcon#*after write, iclass 28, count 0 2006.173.06:00:25.20#ibcon#*before return 0, iclass 28, count 0 2006.173.06:00:25.20#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.06:00:25.20#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.06:00:25.20#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.06:00:25.20#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.06:00:25.20$vck44/vb=2,4 2006.173.06:00:25.20#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.06:00:25.20#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.06:00:25.20#ibcon#ireg 11 cls_cnt 2 2006.173.06:00:25.20#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.06:00:25.26#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.06:00:25.26#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.06:00:25.26#ibcon#enter wrdev, iclass 30, count 2 2006.173.06:00:25.26#ibcon#first serial, iclass 30, count 2 2006.173.06:00:25.26#ibcon#enter sib2, iclass 30, count 2 2006.173.06:00:25.26#ibcon#flushed, iclass 30, count 2 2006.173.06:00:25.26#ibcon#about to write, iclass 30, count 2 2006.173.06:00:25.26#ibcon#wrote, iclass 30, count 2 2006.173.06:00:25.26#ibcon#about to read 3, iclass 30, count 2 2006.173.06:00:25.28#ibcon#read 3, iclass 30, count 2 2006.173.06:00:25.28#ibcon#about to read 4, iclass 30, count 2 2006.173.06:00:25.28#ibcon#read 4, iclass 30, count 2 2006.173.06:00:25.28#ibcon#about to read 5, iclass 30, count 2 2006.173.06:00:25.28#ibcon#read 5, iclass 30, count 2 2006.173.06:00:25.28#ibcon#about to read 6, iclass 30, count 2 2006.173.06:00:25.28#ibcon#read 6, iclass 30, count 2 2006.173.06:00:25.28#ibcon#end of sib2, iclass 30, count 2 2006.173.06:00:25.28#ibcon#*mode == 0, iclass 30, count 2 2006.173.06:00:25.28#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.06:00:25.28#ibcon#[27=AT02-04\r\n] 2006.173.06:00:25.28#ibcon#*before write, iclass 30, count 2 2006.173.06:00:25.28#ibcon#enter sib2, iclass 30, count 2 2006.173.06:00:25.28#ibcon#flushed, iclass 30, count 2 2006.173.06:00:25.28#ibcon#about to write, iclass 30, count 2 2006.173.06:00:25.28#ibcon#wrote, iclass 30, count 2 2006.173.06:00:25.28#ibcon#about to read 3, iclass 30, count 2 2006.173.06:00:25.31#ibcon#read 3, iclass 30, count 2 2006.173.06:00:25.31#ibcon#about to read 4, iclass 30, count 2 2006.173.06:00:25.31#ibcon#read 4, iclass 30, count 2 2006.173.06:00:25.31#ibcon#about to read 5, iclass 30, count 2 2006.173.06:00:25.31#ibcon#read 5, iclass 30, count 2 2006.173.06:00:25.31#ibcon#about to read 6, iclass 30, count 2 2006.173.06:00:25.31#ibcon#read 6, iclass 30, count 2 2006.173.06:00:25.31#ibcon#end of sib2, iclass 30, count 2 2006.173.06:00:25.31#ibcon#*after write, iclass 30, count 2 2006.173.06:00:25.31#ibcon#*before return 0, iclass 30, count 2 2006.173.06:00:25.31#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.06:00:25.31#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.06:00:25.31#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.06:00:25.31#ibcon#ireg 7 cls_cnt 0 2006.173.06:00:25.31#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.06:00:25.43#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.06:00:25.43#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.06:00:25.43#ibcon#enter wrdev, iclass 30, count 0 2006.173.06:00:25.43#ibcon#first serial, iclass 30, count 0 2006.173.06:00:25.43#ibcon#enter sib2, iclass 30, count 0 2006.173.06:00:25.43#ibcon#flushed, iclass 30, count 0 2006.173.06:00:25.43#ibcon#about to write, iclass 30, count 0 2006.173.06:00:25.43#ibcon#wrote, iclass 30, count 0 2006.173.06:00:25.43#ibcon#about to read 3, iclass 30, count 0 2006.173.06:00:25.45#ibcon#read 3, iclass 30, count 0 2006.173.06:00:25.45#ibcon#about to read 4, iclass 30, count 0 2006.173.06:00:25.45#ibcon#read 4, iclass 30, count 0 2006.173.06:00:25.45#ibcon#about to read 5, iclass 30, count 0 2006.173.06:00:25.45#ibcon#read 5, iclass 30, count 0 2006.173.06:00:25.45#ibcon#about to read 6, iclass 30, count 0 2006.173.06:00:25.45#ibcon#read 6, iclass 30, count 0 2006.173.06:00:25.45#ibcon#end of sib2, iclass 30, count 0 2006.173.06:00:25.45#ibcon#*mode == 0, iclass 30, count 0 2006.173.06:00:25.45#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.06:00:25.45#ibcon#[27=USB\r\n] 2006.173.06:00:25.45#ibcon#*before write, iclass 30, count 0 2006.173.06:00:25.45#ibcon#enter sib2, iclass 30, count 0 2006.173.06:00:25.45#ibcon#flushed, iclass 30, count 0 2006.173.06:00:25.45#ibcon#about to write, iclass 30, count 0 2006.173.06:00:25.45#ibcon#wrote, iclass 30, count 0 2006.173.06:00:25.45#ibcon#about to read 3, iclass 30, count 0 2006.173.06:00:25.48#ibcon#read 3, iclass 30, count 0 2006.173.06:00:25.48#ibcon#about to read 4, iclass 30, count 0 2006.173.06:00:25.48#ibcon#read 4, iclass 30, count 0 2006.173.06:00:25.48#ibcon#about to read 5, iclass 30, count 0 2006.173.06:00:25.48#ibcon#read 5, iclass 30, count 0 2006.173.06:00:25.48#ibcon#about to read 6, iclass 30, count 0 2006.173.06:00:25.48#ibcon#read 6, iclass 30, count 0 2006.173.06:00:25.48#ibcon#end of sib2, iclass 30, count 0 2006.173.06:00:25.48#ibcon#*after write, iclass 30, count 0 2006.173.06:00:25.48#ibcon#*before return 0, iclass 30, count 0 2006.173.06:00:25.48#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.06:00:25.48#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.06:00:25.48#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.06:00:25.48#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.06:00:25.48$vck44/vblo=3,649.99 2006.173.06:00:25.48#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.06:00:25.48#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.06:00:25.48#ibcon#ireg 17 cls_cnt 0 2006.173.06:00:25.48#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.06:00:25.48#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.06:00:25.48#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.06:00:25.48#ibcon#enter wrdev, iclass 32, count 0 2006.173.06:00:25.48#ibcon#first serial, iclass 32, count 0 2006.173.06:00:25.48#ibcon#enter sib2, iclass 32, count 0 2006.173.06:00:25.48#ibcon#flushed, iclass 32, count 0 2006.173.06:00:25.48#ibcon#about to write, iclass 32, count 0 2006.173.06:00:25.48#ibcon#wrote, iclass 32, count 0 2006.173.06:00:25.48#ibcon#about to read 3, iclass 32, count 0 2006.173.06:00:25.50#ibcon#read 3, iclass 32, count 0 2006.173.06:00:25.50#ibcon#about to read 4, iclass 32, count 0 2006.173.06:00:25.50#ibcon#read 4, iclass 32, count 0 2006.173.06:00:25.50#ibcon#about to read 5, iclass 32, count 0 2006.173.06:00:25.50#ibcon#read 5, iclass 32, count 0 2006.173.06:00:25.50#ibcon#about to read 6, iclass 32, count 0 2006.173.06:00:25.50#ibcon#read 6, iclass 32, count 0 2006.173.06:00:25.50#ibcon#end of sib2, iclass 32, count 0 2006.173.06:00:25.50#ibcon#*mode == 0, iclass 32, count 0 2006.173.06:00:25.50#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.06:00:25.50#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.06:00:25.50#ibcon#*before write, iclass 32, count 0 2006.173.06:00:25.50#ibcon#enter sib2, iclass 32, count 0 2006.173.06:00:25.50#ibcon#flushed, iclass 32, count 0 2006.173.06:00:25.50#ibcon#about to write, iclass 32, count 0 2006.173.06:00:25.50#ibcon#wrote, iclass 32, count 0 2006.173.06:00:25.50#ibcon#about to read 3, iclass 32, count 0 2006.173.06:00:25.54#ibcon#read 3, iclass 32, count 0 2006.173.06:00:25.54#ibcon#about to read 4, iclass 32, count 0 2006.173.06:00:25.54#ibcon#read 4, iclass 32, count 0 2006.173.06:00:25.54#ibcon#about to read 5, iclass 32, count 0 2006.173.06:00:25.54#ibcon#read 5, iclass 32, count 0 2006.173.06:00:25.54#ibcon#about to read 6, iclass 32, count 0 2006.173.06:00:25.54#ibcon#read 6, iclass 32, count 0 2006.173.06:00:25.54#ibcon#end of sib2, iclass 32, count 0 2006.173.06:00:25.54#ibcon#*after write, iclass 32, count 0 2006.173.06:00:25.54#ibcon#*before return 0, iclass 32, count 0 2006.173.06:00:25.54#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.06:00:25.54#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.06:00:25.54#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.06:00:25.54#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.06:00:25.54$vck44/vb=3,4 2006.173.06:00:25.54#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.06:00:25.54#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.06:00:25.54#ibcon#ireg 11 cls_cnt 2 2006.173.06:00:25.54#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.06:00:25.60#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.06:00:25.60#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.06:00:25.60#ibcon#enter wrdev, iclass 34, count 2 2006.173.06:00:25.60#ibcon#first serial, iclass 34, count 2 2006.173.06:00:25.60#ibcon#enter sib2, iclass 34, count 2 2006.173.06:00:25.60#ibcon#flushed, iclass 34, count 2 2006.173.06:00:25.60#ibcon#about to write, iclass 34, count 2 2006.173.06:00:25.60#ibcon#wrote, iclass 34, count 2 2006.173.06:00:25.60#ibcon#about to read 3, iclass 34, count 2 2006.173.06:00:25.62#ibcon#read 3, iclass 34, count 2 2006.173.06:00:25.62#ibcon#about to read 4, iclass 34, count 2 2006.173.06:00:25.62#ibcon#read 4, iclass 34, count 2 2006.173.06:00:25.62#ibcon#about to read 5, iclass 34, count 2 2006.173.06:00:25.62#ibcon#read 5, iclass 34, count 2 2006.173.06:00:25.62#ibcon#about to read 6, iclass 34, count 2 2006.173.06:00:25.62#ibcon#read 6, iclass 34, count 2 2006.173.06:00:25.62#ibcon#end of sib2, iclass 34, count 2 2006.173.06:00:25.62#ibcon#*mode == 0, iclass 34, count 2 2006.173.06:00:25.62#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.06:00:25.62#ibcon#[27=AT03-04\r\n] 2006.173.06:00:25.62#ibcon#*before write, iclass 34, count 2 2006.173.06:00:25.62#ibcon#enter sib2, iclass 34, count 2 2006.173.06:00:25.62#ibcon#flushed, iclass 34, count 2 2006.173.06:00:25.62#ibcon#about to write, iclass 34, count 2 2006.173.06:00:25.62#ibcon#wrote, iclass 34, count 2 2006.173.06:00:25.62#ibcon#about to read 3, iclass 34, count 2 2006.173.06:00:25.65#ibcon#read 3, iclass 34, count 2 2006.173.06:00:25.65#ibcon#about to read 4, iclass 34, count 2 2006.173.06:00:25.65#ibcon#read 4, iclass 34, count 2 2006.173.06:00:25.65#ibcon#about to read 5, iclass 34, count 2 2006.173.06:00:25.65#ibcon#read 5, iclass 34, count 2 2006.173.06:00:25.65#ibcon#about to read 6, iclass 34, count 2 2006.173.06:00:25.65#ibcon#read 6, iclass 34, count 2 2006.173.06:00:25.65#ibcon#end of sib2, iclass 34, count 2 2006.173.06:00:25.65#ibcon#*after write, iclass 34, count 2 2006.173.06:00:25.65#ibcon#*before return 0, iclass 34, count 2 2006.173.06:00:25.65#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.06:00:25.65#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.06:00:25.65#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.06:00:25.65#ibcon#ireg 7 cls_cnt 0 2006.173.06:00:25.65#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.06:00:25.77#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.06:00:25.77#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.06:00:25.77#ibcon#enter wrdev, iclass 34, count 0 2006.173.06:00:25.77#ibcon#first serial, iclass 34, count 0 2006.173.06:00:25.77#ibcon#enter sib2, iclass 34, count 0 2006.173.06:00:25.77#ibcon#flushed, iclass 34, count 0 2006.173.06:00:25.77#ibcon#about to write, iclass 34, count 0 2006.173.06:00:25.77#ibcon#wrote, iclass 34, count 0 2006.173.06:00:25.77#ibcon#about to read 3, iclass 34, count 0 2006.173.06:00:25.79#ibcon#read 3, iclass 34, count 0 2006.173.06:00:25.79#ibcon#about to read 4, iclass 34, count 0 2006.173.06:00:25.79#ibcon#read 4, iclass 34, count 0 2006.173.06:00:25.79#ibcon#about to read 5, iclass 34, count 0 2006.173.06:00:25.79#ibcon#read 5, iclass 34, count 0 2006.173.06:00:25.79#ibcon#about to read 6, iclass 34, count 0 2006.173.06:00:25.79#ibcon#read 6, iclass 34, count 0 2006.173.06:00:25.79#ibcon#end of sib2, iclass 34, count 0 2006.173.06:00:25.79#ibcon#*mode == 0, iclass 34, count 0 2006.173.06:00:25.79#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.06:00:25.79#ibcon#[27=USB\r\n] 2006.173.06:00:25.79#ibcon#*before write, iclass 34, count 0 2006.173.06:00:25.79#ibcon#enter sib2, iclass 34, count 0 2006.173.06:00:25.79#ibcon#flushed, iclass 34, count 0 2006.173.06:00:25.79#ibcon#about to write, iclass 34, count 0 2006.173.06:00:25.79#ibcon#wrote, iclass 34, count 0 2006.173.06:00:25.79#ibcon#about to read 3, iclass 34, count 0 2006.173.06:00:25.82#ibcon#read 3, iclass 34, count 0 2006.173.06:00:25.82#ibcon#about to read 4, iclass 34, count 0 2006.173.06:00:25.82#ibcon#read 4, iclass 34, count 0 2006.173.06:00:25.82#ibcon#about to read 5, iclass 34, count 0 2006.173.06:00:25.82#ibcon#read 5, iclass 34, count 0 2006.173.06:00:25.82#ibcon#about to read 6, iclass 34, count 0 2006.173.06:00:25.82#ibcon#read 6, iclass 34, count 0 2006.173.06:00:25.82#ibcon#end of sib2, iclass 34, count 0 2006.173.06:00:25.82#ibcon#*after write, iclass 34, count 0 2006.173.06:00:25.82#ibcon#*before return 0, iclass 34, count 0 2006.173.06:00:25.82#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.06:00:25.82#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.06:00:25.82#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.06:00:25.82#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.06:00:25.82$vck44/vblo=4,679.99 2006.173.06:00:25.82#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.06:00:25.82#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.06:00:25.82#ibcon#ireg 17 cls_cnt 0 2006.173.06:00:25.82#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.06:00:25.82#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.06:00:25.82#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.06:00:25.82#ibcon#enter wrdev, iclass 36, count 0 2006.173.06:00:25.82#ibcon#first serial, iclass 36, count 0 2006.173.06:00:25.82#ibcon#enter sib2, iclass 36, count 0 2006.173.06:00:25.82#ibcon#flushed, iclass 36, count 0 2006.173.06:00:25.82#ibcon#about to write, iclass 36, count 0 2006.173.06:00:25.82#ibcon#wrote, iclass 36, count 0 2006.173.06:00:25.82#ibcon#about to read 3, iclass 36, count 0 2006.173.06:00:25.84#ibcon#read 3, iclass 36, count 0 2006.173.06:00:25.84#ibcon#about to read 4, iclass 36, count 0 2006.173.06:00:25.84#ibcon#read 4, iclass 36, count 0 2006.173.06:00:25.84#ibcon#about to read 5, iclass 36, count 0 2006.173.06:00:25.84#ibcon#read 5, iclass 36, count 0 2006.173.06:00:25.84#ibcon#about to read 6, iclass 36, count 0 2006.173.06:00:25.84#ibcon#read 6, iclass 36, count 0 2006.173.06:00:25.84#ibcon#end of sib2, iclass 36, count 0 2006.173.06:00:25.84#ibcon#*mode == 0, iclass 36, count 0 2006.173.06:00:25.84#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.06:00:25.84#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.06:00:25.84#ibcon#*before write, iclass 36, count 0 2006.173.06:00:25.84#ibcon#enter sib2, iclass 36, count 0 2006.173.06:00:25.84#ibcon#flushed, iclass 36, count 0 2006.173.06:00:25.84#ibcon#about to write, iclass 36, count 0 2006.173.06:00:25.84#ibcon#wrote, iclass 36, count 0 2006.173.06:00:25.84#ibcon#about to read 3, iclass 36, count 0 2006.173.06:00:25.88#ibcon#read 3, iclass 36, count 0 2006.173.06:00:25.88#ibcon#about to read 4, iclass 36, count 0 2006.173.06:00:25.88#ibcon#read 4, iclass 36, count 0 2006.173.06:00:25.88#ibcon#about to read 5, iclass 36, count 0 2006.173.06:00:25.88#ibcon#read 5, iclass 36, count 0 2006.173.06:00:25.88#ibcon#about to read 6, iclass 36, count 0 2006.173.06:00:25.88#ibcon#read 6, iclass 36, count 0 2006.173.06:00:25.88#ibcon#end of sib2, iclass 36, count 0 2006.173.06:00:25.88#ibcon#*after write, iclass 36, count 0 2006.173.06:00:25.88#ibcon#*before return 0, iclass 36, count 0 2006.173.06:00:25.88#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.06:00:25.88#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.06:00:25.88#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.06:00:25.88#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.06:00:25.88$vck44/vb=4,4 2006.173.06:00:25.88#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.06:00:25.88#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.06:00:25.88#ibcon#ireg 11 cls_cnt 2 2006.173.06:00:25.88#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.06:00:25.94#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.06:00:25.94#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.06:00:25.94#ibcon#enter wrdev, iclass 38, count 2 2006.173.06:00:25.94#ibcon#first serial, iclass 38, count 2 2006.173.06:00:25.94#ibcon#enter sib2, iclass 38, count 2 2006.173.06:00:25.94#ibcon#flushed, iclass 38, count 2 2006.173.06:00:25.94#ibcon#about to write, iclass 38, count 2 2006.173.06:00:25.94#ibcon#wrote, iclass 38, count 2 2006.173.06:00:25.94#ibcon#about to read 3, iclass 38, count 2 2006.173.06:00:25.96#ibcon#read 3, iclass 38, count 2 2006.173.06:00:25.96#ibcon#about to read 4, iclass 38, count 2 2006.173.06:00:25.96#ibcon#read 4, iclass 38, count 2 2006.173.06:00:25.96#ibcon#about to read 5, iclass 38, count 2 2006.173.06:00:25.96#ibcon#read 5, iclass 38, count 2 2006.173.06:00:25.96#ibcon#about to read 6, iclass 38, count 2 2006.173.06:00:25.96#ibcon#read 6, iclass 38, count 2 2006.173.06:00:25.96#ibcon#end of sib2, iclass 38, count 2 2006.173.06:00:25.96#ibcon#*mode == 0, iclass 38, count 2 2006.173.06:00:25.96#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.06:00:25.96#ibcon#[27=AT04-04\r\n] 2006.173.06:00:25.96#ibcon#*before write, iclass 38, count 2 2006.173.06:00:25.96#ibcon#enter sib2, iclass 38, count 2 2006.173.06:00:25.96#ibcon#flushed, iclass 38, count 2 2006.173.06:00:25.96#ibcon#about to write, iclass 38, count 2 2006.173.06:00:25.96#ibcon#wrote, iclass 38, count 2 2006.173.06:00:25.96#ibcon#about to read 3, iclass 38, count 2 2006.173.06:00:25.99#ibcon#read 3, iclass 38, count 2 2006.173.06:00:25.99#ibcon#about to read 4, iclass 38, count 2 2006.173.06:00:25.99#ibcon#read 4, iclass 38, count 2 2006.173.06:00:25.99#ibcon#about to read 5, iclass 38, count 2 2006.173.06:00:25.99#ibcon#read 5, iclass 38, count 2 2006.173.06:00:25.99#ibcon#about to read 6, iclass 38, count 2 2006.173.06:00:25.99#ibcon#read 6, iclass 38, count 2 2006.173.06:00:25.99#ibcon#end of sib2, iclass 38, count 2 2006.173.06:00:25.99#ibcon#*after write, iclass 38, count 2 2006.173.06:00:25.99#ibcon#*before return 0, iclass 38, count 2 2006.173.06:00:25.99#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.06:00:25.99#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.06:00:25.99#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.06:00:25.99#ibcon#ireg 7 cls_cnt 0 2006.173.06:00:25.99#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.06:00:26.11#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.06:00:26.11#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.06:00:26.11#ibcon#enter wrdev, iclass 38, count 0 2006.173.06:00:26.11#ibcon#first serial, iclass 38, count 0 2006.173.06:00:26.11#ibcon#enter sib2, iclass 38, count 0 2006.173.06:00:26.11#ibcon#flushed, iclass 38, count 0 2006.173.06:00:26.11#ibcon#about to write, iclass 38, count 0 2006.173.06:00:26.11#ibcon#wrote, iclass 38, count 0 2006.173.06:00:26.11#ibcon#about to read 3, iclass 38, count 0 2006.173.06:00:26.13#ibcon#read 3, iclass 38, count 0 2006.173.06:00:26.13#ibcon#about to read 4, iclass 38, count 0 2006.173.06:00:26.13#ibcon#read 4, iclass 38, count 0 2006.173.06:00:26.13#ibcon#about to read 5, iclass 38, count 0 2006.173.06:00:26.13#ibcon#read 5, iclass 38, count 0 2006.173.06:00:26.13#ibcon#about to read 6, iclass 38, count 0 2006.173.06:00:26.13#ibcon#read 6, iclass 38, count 0 2006.173.06:00:26.13#ibcon#end of sib2, iclass 38, count 0 2006.173.06:00:26.13#ibcon#*mode == 0, iclass 38, count 0 2006.173.06:00:26.13#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.06:00:26.13#ibcon#[27=USB\r\n] 2006.173.06:00:26.13#ibcon#*before write, iclass 38, count 0 2006.173.06:00:26.13#ibcon#enter sib2, iclass 38, count 0 2006.173.06:00:26.13#ibcon#flushed, iclass 38, count 0 2006.173.06:00:26.13#ibcon#about to write, iclass 38, count 0 2006.173.06:00:26.13#ibcon#wrote, iclass 38, count 0 2006.173.06:00:26.13#ibcon#about to read 3, iclass 38, count 0 2006.173.06:00:26.16#ibcon#read 3, iclass 38, count 0 2006.173.06:00:26.16#ibcon#about to read 4, iclass 38, count 0 2006.173.06:00:26.16#ibcon#read 4, iclass 38, count 0 2006.173.06:00:26.16#ibcon#about to read 5, iclass 38, count 0 2006.173.06:00:26.16#ibcon#read 5, iclass 38, count 0 2006.173.06:00:26.16#ibcon#about to read 6, iclass 38, count 0 2006.173.06:00:26.16#ibcon#read 6, iclass 38, count 0 2006.173.06:00:26.16#ibcon#end of sib2, iclass 38, count 0 2006.173.06:00:26.16#ibcon#*after write, iclass 38, count 0 2006.173.06:00:26.16#ibcon#*before return 0, iclass 38, count 0 2006.173.06:00:26.16#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.06:00:26.16#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.06:00:26.16#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.06:00:26.16#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.06:00:26.16$vck44/vblo=5,709.99 2006.173.06:00:26.16#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.06:00:26.16#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.06:00:26.16#ibcon#ireg 17 cls_cnt 0 2006.173.06:00:26.16#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.06:00:26.16#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.06:00:26.16#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.06:00:26.16#ibcon#enter wrdev, iclass 40, count 0 2006.173.06:00:26.16#ibcon#first serial, iclass 40, count 0 2006.173.06:00:26.16#ibcon#enter sib2, iclass 40, count 0 2006.173.06:00:26.16#ibcon#flushed, iclass 40, count 0 2006.173.06:00:26.16#ibcon#about to write, iclass 40, count 0 2006.173.06:00:26.16#ibcon#wrote, iclass 40, count 0 2006.173.06:00:26.16#ibcon#about to read 3, iclass 40, count 0 2006.173.06:00:26.18#ibcon#read 3, iclass 40, count 0 2006.173.06:00:26.18#ibcon#about to read 4, iclass 40, count 0 2006.173.06:00:26.18#ibcon#read 4, iclass 40, count 0 2006.173.06:00:26.18#ibcon#about to read 5, iclass 40, count 0 2006.173.06:00:26.18#ibcon#read 5, iclass 40, count 0 2006.173.06:00:26.18#ibcon#about to read 6, iclass 40, count 0 2006.173.06:00:26.18#ibcon#read 6, iclass 40, count 0 2006.173.06:00:26.18#ibcon#end of sib2, iclass 40, count 0 2006.173.06:00:26.18#ibcon#*mode == 0, iclass 40, count 0 2006.173.06:00:26.18#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.06:00:26.18#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.06:00:26.18#ibcon#*before write, iclass 40, count 0 2006.173.06:00:26.18#ibcon#enter sib2, iclass 40, count 0 2006.173.06:00:26.18#ibcon#flushed, iclass 40, count 0 2006.173.06:00:26.18#ibcon#about to write, iclass 40, count 0 2006.173.06:00:26.18#ibcon#wrote, iclass 40, count 0 2006.173.06:00:26.18#ibcon#about to read 3, iclass 40, count 0 2006.173.06:00:26.22#ibcon#read 3, iclass 40, count 0 2006.173.06:00:26.22#ibcon#about to read 4, iclass 40, count 0 2006.173.06:00:26.22#ibcon#read 4, iclass 40, count 0 2006.173.06:00:26.22#ibcon#about to read 5, iclass 40, count 0 2006.173.06:00:26.22#ibcon#read 5, iclass 40, count 0 2006.173.06:00:26.22#ibcon#about to read 6, iclass 40, count 0 2006.173.06:00:26.22#ibcon#read 6, iclass 40, count 0 2006.173.06:00:26.22#ibcon#end of sib2, iclass 40, count 0 2006.173.06:00:26.22#ibcon#*after write, iclass 40, count 0 2006.173.06:00:26.22#ibcon#*before return 0, iclass 40, count 0 2006.173.06:00:26.22#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.06:00:26.22#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.06:00:26.22#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.06:00:26.22#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.06:00:26.22$vck44/vb=5,4 2006.173.06:00:26.22#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.06:00:26.22#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.06:00:26.22#ibcon#ireg 11 cls_cnt 2 2006.173.06:00:26.22#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.06:00:26.28#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.06:00:26.28#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.06:00:26.28#ibcon#enter wrdev, iclass 4, count 2 2006.173.06:00:26.28#ibcon#first serial, iclass 4, count 2 2006.173.06:00:26.28#ibcon#enter sib2, iclass 4, count 2 2006.173.06:00:26.28#ibcon#flushed, iclass 4, count 2 2006.173.06:00:26.28#ibcon#about to write, iclass 4, count 2 2006.173.06:00:26.28#ibcon#wrote, iclass 4, count 2 2006.173.06:00:26.28#ibcon#about to read 3, iclass 4, count 2 2006.173.06:00:26.30#ibcon#read 3, iclass 4, count 2 2006.173.06:00:26.30#ibcon#about to read 4, iclass 4, count 2 2006.173.06:00:26.30#ibcon#read 4, iclass 4, count 2 2006.173.06:00:26.30#ibcon#about to read 5, iclass 4, count 2 2006.173.06:00:26.30#ibcon#read 5, iclass 4, count 2 2006.173.06:00:26.30#ibcon#about to read 6, iclass 4, count 2 2006.173.06:00:26.30#ibcon#read 6, iclass 4, count 2 2006.173.06:00:26.30#ibcon#end of sib2, iclass 4, count 2 2006.173.06:00:26.30#ibcon#*mode == 0, iclass 4, count 2 2006.173.06:00:26.30#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.06:00:26.30#ibcon#[27=AT05-04\r\n] 2006.173.06:00:26.30#ibcon#*before write, iclass 4, count 2 2006.173.06:00:26.30#ibcon#enter sib2, iclass 4, count 2 2006.173.06:00:26.30#ibcon#flushed, iclass 4, count 2 2006.173.06:00:26.30#ibcon#about to write, iclass 4, count 2 2006.173.06:00:26.30#ibcon#wrote, iclass 4, count 2 2006.173.06:00:26.30#ibcon#about to read 3, iclass 4, count 2 2006.173.06:00:26.33#ibcon#read 3, iclass 4, count 2 2006.173.06:00:26.33#ibcon#about to read 4, iclass 4, count 2 2006.173.06:00:26.33#ibcon#read 4, iclass 4, count 2 2006.173.06:00:26.33#ibcon#about to read 5, iclass 4, count 2 2006.173.06:00:26.33#ibcon#read 5, iclass 4, count 2 2006.173.06:00:26.33#ibcon#about to read 6, iclass 4, count 2 2006.173.06:00:26.33#ibcon#read 6, iclass 4, count 2 2006.173.06:00:26.33#ibcon#end of sib2, iclass 4, count 2 2006.173.06:00:26.33#ibcon#*after write, iclass 4, count 2 2006.173.06:00:26.33#ibcon#*before return 0, iclass 4, count 2 2006.173.06:00:26.33#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.06:00:26.33#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.06:00:26.33#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.06:00:26.33#ibcon#ireg 7 cls_cnt 0 2006.173.06:00:26.33#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.06:00:26.45#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.06:00:26.45#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.06:00:26.45#ibcon#enter wrdev, iclass 4, count 0 2006.173.06:00:26.45#ibcon#first serial, iclass 4, count 0 2006.173.06:00:26.45#ibcon#enter sib2, iclass 4, count 0 2006.173.06:00:26.45#ibcon#flushed, iclass 4, count 0 2006.173.06:00:26.45#ibcon#about to write, iclass 4, count 0 2006.173.06:00:26.45#ibcon#wrote, iclass 4, count 0 2006.173.06:00:26.45#ibcon#about to read 3, iclass 4, count 0 2006.173.06:00:26.47#ibcon#read 3, iclass 4, count 0 2006.173.06:00:26.47#ibcon#about to read 4, iclass 4, count 0 2006.173.06:00:26.47#ibcon#read 4, iclass 4, count 0 2006.173.06:00:26.47#ibcon#about to read 5, iclass 4, count 0 2006.173.06:00:26.47#ibcon#read 5, iclass 4, count 0 2006.173.06:00:26.47#ibcon#about to read 6, iclass 4, count 0 2006.173.06:00:26.47#ibcon#read 6, iclass 4, count 0 2006.173.06:00:26.47#ibcon#end of sib2, iclass 4, count 0 2006.173.06:00:26.47#ibcon#*mode == 0, iclass 4, count 0 2006.173.06:00:26.47#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.06:00:26.47#ibcon#[27=USB\r\n] 2006.173.06:00:26.47#ibcon#*before write, iclass 4, count 0 2006.173.06:00:26.47#ibcon#enter sib2, iclass 4, count 0 2006.173.06:00:26.47#ibcon#flushed, iclass 4, count 0 2006.173.06:00:26.47#ibcon#about to write, iclass 4, count 0 2006.173.06:00:26.47#ibcon#wrote, iclass 4, count 0 2006.173.06:00:26.47#ibcon#about to read 3, iclass 4, count 0 2006.173.06:00:26.50#ibcon#read 3, iclass 4, count 0 2006.173.06:00:26.50#ibcon#about to read 4, iclass 4, count 0 2006.173.06:00:26.50#ibcon#read 4, iclass 4, count 0 2006.173.06:00:26.50#ibcon#about to read 5, iclass 4, count 0 2006.173.06:00:26.50#ibcon#read 5, iclass 4, count 0 2006.173.06:00:26.50#ibcon#about to read 6, iclass 4, count 0 2006.173.06:00:26.50#ibcon#read 6, iclass 4, count 0 2006.173.06:00:26.50#ibcon#end of sib2, iclass 4, count 0 2006.173.06:00:26.50#ibcon#*after write, iclass 4, count 0 2006.173.06:00:26.50#ibcon#*before return 0, iclass 4, count 0 2006.173.06:00:26.50#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.06:00:26.50#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.06:00:26.50#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.06:00:26.50#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.06:00:26.50$vck44/vblo=6,719.99 2006.173.06:00:26.50#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.06:00:26.50#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.06:00:26.50#ibcon#ireg 17 cls_cnt 0 2006.173.06:00:26.50#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.06:00:26.50#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.06:00:26.50#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.06:00:26.50#ibcon#enter wrdev, iclass 6, count 0 2006.173.06:00:26.50#ibcon#first serial, iclass 6, count 0 2006.173.06:00:26.50#ibcon#enter sib2, iclass 6, count 0 2006.173.06:00:26.50#ibcon#flushed, iclass 6, count 0 2006.173.06:00:26.50#ibcon#about to write, iclass 6, count 0 2006.173.06:00:26.50#ibcon#wrote, iclass 6, count 0 2006.173.06:00:26.50#ibcon#about to read 3, iclass 6, count 0 2006.173.06:00:26.52#ibcon#read 3, iclass 6, count 0 2006.173.06:00:26.52#ibcon#about to read 4, iclass 6, count 0 2006.173.06:00:26.52#ibcon#read 4, iclass 6, count 0 2006.173.06:00:26.52#ibcon#about to read 5, iclass 6, count 0 2006.173.06:00:26.52#ibcon#read 5, iclass 6, count 0 2006.173.06:00:26.52#ibcon#about to read 6, iclass 6, count 0 2006.173.06:00:26.52#ibcon#read 6, iclass 6, count 0 2006.173.06:00:26.52#ibcon#end of sib2, iclass 6, count 0 2006.173.06:00:26.52#ibcon#*mode == 0, iclass 6, count 0 2006.173.06:00:26.52#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.06:00:26.52#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.06:00:26.52#ibcon#*before write, iclass 6, count 0 2006.173.06:00:26.52#ibcon#enter sib2, iclass 6, count 0 2006.173.06:00:26.52#ibcon#flushed, iclass 6, count 0 2006.173.06:00:26.52#ibcon#about to write, iclass 6, count 0 2006.173.06:00:26.52#ibcon#wrote, iclass 6, count 0 2006.173.06:00:26.52#ibcon#about to read 3, iclass 6, count 0 2006.173.06:00:26.56#ibcon#read 3, iclass 6, count 0 2006.173.06:00:26.56#ibcon#about to read 4, iclass 6, count 0 2006.173.06:00:26.56#ibcon#read 4, iclass 6, count 0 2006.173.06:00:26.56#ibcon#about to read 5, iclass 6, count 0 2006.173.06:00:26.56#ibcon#read 5, iclass 6, count 0 2006.173.06:00:26.56#ibcon#about to read 6, iclass 6, count 0 2006.173.06:00:26.56#ibcon#read 6, iclass 6, count 0 2006.173.06:00:26.56#ibcon#end of sib2, iclass 6, count 0 2006.173.06:00:26.56#ibcon#*after write, iclass 6, count 0 2006.173.06:00:26.56#ibcon#*before return 0, iclass 6, count 0 2006.173.06:00:26.56#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.06:00:26.56#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.06:00:26.56#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.06:00:26.56#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.06:00:26.56$vck44/vb=6,4 2006.173.06:00:26.56#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.06:00:26.56#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.06:00:26.56#ibcon#ireg 11 cls_cnt 2 2006.173.06:00:26.56#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.06:00:26.62#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.06:00:26.62#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.06:00:26.62#ibcon#enter wrdev, iclass 10, count 2 2006.173.06:00:26.62#ibcon#first serial, iclass 10, count 2 2006.173.06:00:26.62#ibcon#enter sib2, iclass 10, count 2 2006.173.06:00:26.62#ibcon#flushed, iclass 10, count 2 2006.173.06:00:26.62#ibcon#about to write, iclass 10, count 2 2006.173.06:00:26.62#ibcon#wrote, iclass 10, count 2 2006.173.06:00:26.62#ibcon#about to read 3, iclass 10, count 2 2006.173.06:00:26.64#ibcon#read 3, iclass 10, count 2 2006.173.06:00:26.64#ibcon#about to read 4, iclass 10, count 2 2006.173.06:00:26.64#ibcon#read 4, iclass 10, count 2 2006.173.06:00:26.64#ibcon#about to read 5, iclass 10, count 2 2006.173.06:00:26.64#ibcon#read 5, iclass 10, count 2 2006.173.06:00:26.64#ibcon#about to read 6, iclass 10, count 2 2006.173.06:00:26.64#ibcon#read 6, iclass 10, count 2 2006.173.06:00:26.64#ibcon#end of sib2, iclass 10, count 2 2006.173.06:00:26.64#ibcon#*mode == 0, iclass 10, count 2 2006.173.06:00:26.64#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.06:00:26.64#ibcon#[27=AT06-04\r\n] 2006.173.06:00:26.64#ibcon#*before write, iclass 10, count 2 2006.173.06:00:26.64#ibcon#enter sib2, iclass 10, count 2 2006.173.06:00:26.64#ibcon#flushed, iclass 10, count 2 2006.173.06:00:26.64#ibcon#about to write, iclass 10, count 2 2006.173.06:00:26.64#ibcon#wrote, iclass 10, count 2 2006.173.06:00:26.64#ibcon#about to read 3, iclass 10, count 2 2006.173.06:00:26.67#ibcon#read 3, iclass 10, count 2 2006.173.06:00:26.67#ibcon#about to read 4, iclass 10, count 2 2006.173.06:00:26.67#ibcon#read 4, iclass 10, count 2 2006.173.06:00:26.67#ibcon#about to read 5, iclass 10, count 2 2006.173.06:00:26.67#ibcon#read 5, iclass 10, count 2 2006.173.06:00:26.67#ibcon#about to read 6, iclass 10, count 2 2006.173.06:00:26.67#ibcon#read 6, iclass 10, count 2 2006.173.06:00:26.67#ibcon#end of sib2, iclass 10, count 2 2006.173.06:00:26.67#ibcon#*after write, iclass 10, count 2 2006.173.06:00:26.67#ibcon#*before return 0, iclass 10, count 2 2006.173.06:00:26.67#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.06:00:26.67#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.06:00:26.67#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.06:00:26.67#ibcon#ireg 7 cls_cnt 0 2006.173.06:00:26.67#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.06:00:26.79#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.06:00:26.79#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.06:00:26.79#ibcon#enter wrdev, iclass 10, count 0 2006.173.06:00:26.79#ibcon#first serial, iclass 10, count 0 2006.173.06:00:26.79#ibcon#enter sib2, iclass 10, count 0 2006.173.06:00:26.79#ibcon#flushed, iclass 10, count 0 2006.173.06:00:26.79#ibcon#about to write, iclass 10, count 0 2006.173.06:00:26.79#ibcon#wrote, iclass 10, count 0 2006.173.06:00:26.79#ibcon#about to read 3, iclass 10, count 0 2006.173.06:00:26.81#ibcon#read 3, iclass 10, count 0 2006.173.06:00:26.81#ibcon#about to read 4, iclass 10, count 0 2006.173.06:00:26.81#ibcon#read 4, iclass 10, count 0 2006.173.06:00:26.81#ibcon#about to read 5, iclass 10, count 0 2006.173.06:00:26.81#ibcon#read 5, iclass 10, count 0 2006.173.06:00:26.81#ibcon#about to read 6, iclass 10, count 0 2006.173.06:00:26.81#ibcon#read 6, iclass 10, count 0 2006.173.06:00:26.81#ibcon#end of sib2, iclass 10, count 0 2006.173.06:00:26.81#ibcon#*mode == 0, iclass 10, count 0 2006.173.06:00:26.81#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.06:00:26.81#ibcon#[27=USB\r\n] 2006.173.06:00:26.81#ibcon#*before write, iclass 10, count 0 2006.173.06:00:26.81#ibcon#enter sib2, iclass 10, count 0 2006.173.06:00:26.81#ibcon#flushed, iclass 10, count 0 2006.173.06:00:26.81#ibcon#about to write, iclass 10, count 0 2006.173.06:00:26.81#ibcon#wrote, iclass 10, count 0 2006.173.06:00:26.81#ibcon#about to read 3, iclass 10, count 0 2006.173.06:00:26.84#ibcon#read 3, iclass 10, count 0 2006.173.06:00:26.84#ibcon#about to read 4, iclass 10, count 0 2006.173.06:00:26.84#ibcon#read 4, iclass 10, count 0 2006.173.06:00:26.84#ibcon#about to read 5, iclass 10, count 0 2006.173.06:00:26.84#ibcon#read 5, iclass 10, count 0 2006.173.06:00:26.84#ibcon#about to read 6, iclass 10, count 0 2006.173.06:00:26.84#ibcon#read 6, iclass 10, count 0 2006.173.06:00:26.84#ibcon#end of sib2, iclass 10, count 0 2006.173.06:00:26.84#ibcon#*after write, iclass 10, count 0 2006.173.06:00:26.84#ibcon#*before return 0, iclass 10, count 0 2006.173.06:00:26.84#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.06:00:26.84#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.06:00:26.84#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.06:00:26.84#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.06:00:26.84$vck44/vblo=7,734.99 2006.173.06:00:26.84#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.06:00:26.84#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.06:00:26.84#ibcon#ireg 17 cls_cnt 0 2006.173.06:00:26.84#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.06:00:26.84#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.06:00:26.84#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.06:00:26.84#ibcon#enter wrdev, iclass 12, count 0 2006.173.06:00:26.84#ibcon#first serial, iclass 12, count 0 2006.173.06:00:26.84#ibcon#enter sib2, iclass 12, count 0 2006.173.06:00:26.84#ibcon#flushed, iclass 12, count 0 2006.173.06:00:26.84#ibcon#about to write, iclass 12, count 0 2006.173.06:00:26.84#ibcon#wrote, iclass 12, count 0 2006.173.06:00:26.84#ibcon#about to read 3, iclass 12, count 0 2006.173.06:00:26.86#ibcon#read 3, iclass 12, count 0 2006.173.06:00:26.86#ibcon#about to read 4, iclass 12, count 0 2006.173.06:00:26.86#ibcon#read 4, iclass 12, count 0 2006.173.06:00:26.86#ibcon#about to read 5, iclass 12, count 0 2006.173.06:00:26.86#ibcon#read 5, iclass 12, count 0 2006.173.06:00:26.86#ibcon#about to read 6, iclass 12, count 0 2006.173.06:00:26.86#ibcon#read 6, iclass 12, count 0 2006.173.06:00:26.86#ibcon#end of sib2, iclass 12, count 0 2006.173.06:00:26.86#ibcon#*mode == 0, iclass 12, count 0 2006.173.06:00:26.86#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.06:00:26.86#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.06:00:26.86#ibcon#*before write, iclass 12, count 0 2006.173.06:00:26.86#ibcon#enter sib2, iclass 12, count 0 2006.173.06:00:26.86#ibcon#flushed, iclass 12, count 0 2006.173.06:00:26.86#ibcon#about to write, iclass 12, count 0 2006.173.06:00:26.86#ibcon#wrote, iclass 12, count 0 2006.173.06:00:26.86#ibcon#about to read 3, iclass 12, count 0 2006.173.06:00:26.90#ibcon#read 3, iclass 12, count 0 2006.173.06:00:26.90#ibcon#about to read 4, iclass 12, count 0 2006.173.06:00:26.90#ibcon#read 4, iclass 12, count 0 2006.173.06:00:26.90#ibcon#about to read 5, iclass 12, count 0 2006.173.06:00:26.90#ibcon#read 5, iclass 12, count 0 2006.173.06:00:26.90#ibcon#about to read 6, iclass 12, count 0 2006.173.06:00:26.90#ibcon#read 6, iclass 12, count 0 2006.173.06:00:26.90#ibcon#end of sib2, iclass 12, count 0 2006.173.06:00:26.90#ibcon#*after write, iclass 12, count 0 2006.173.06:00:26.90#ibcon#*before return 0, iclass 12, count 0 2006.173.06:00:26.90#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.06:00:26.90#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.06:00:26.90#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.06:00:26.90#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.06:00:26.90$vck44/vb=7,4 2006.173.06:00:26.90#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.06:00:26.90#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.06:00:26.90#ibcon#ireg 11 cls_cnt 2 2006.173.06:00:26.90#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.06:00:26.96#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.06:00:26.96#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.06:00:26.96#ibcon#enter wrdev, iclass 14, count 2 2006.173.06:00:26.96#ibcon#first serial, iclass 14, count 2 2006.173.06:00:26.96#ibcon#enter sib2, iclass 14, count 2 2006.173.06:00:26.96#ibcon#flushed, iclass 14, count 2 2006.173.06:00:26.96#ibcon#about to write, iclass 14, count 2 2006.173.06:00:26.96#ibcon#wrote, iclass 14, count 2 2006.173.06:00:26.96#ibcon#about to read 3, iclass 14, count 2 2006.173.06:00:26.98#ibcon#read 3, iclass 14, count 2 2006.173.06:00:26.98#ibcon#about to read 4, iclass 14, count 2 2006.173.06:00:26.98#ibcon#read 4, iclass 14, count 2 2006.173.06:00:26.98#ibcon#about to read 5, iclass 14, count 2 2006.173.06:00:26.98#ibcon#read 5, iclass 14, count 2 2006.173.06:00:26.98#ibcon#about to read 6, iclass 14, count 2 2006.173.06:00:26.98#ibcon#read 6, iclass 14, count 2 2006.173.06:00:26.98#ibcon#end of sib2, iclass 14, count 2 2006.173.06:00:26.98#ibcon#*mode == 0, iclass 14, count 2 2006.173.06:00:26.98#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.06:00:26.98#ibcon#[27=AT07-04\r\n] 2006.173.06:00:26.98#ibcon#*before write, iclass 14, count 2 2006.173.06:00:26.98#ibcon#enter sib2, iclass 14, count 2 2006.173.06:00:26.98#ibcon#flushed, iclass 14, count 2 2006.173.06:00:26.98#ibcon#about to write, iclass 14, count 2 2006.173.06:00:26.98#ibcon#wrote, iclass 14, count 2 2006.173.06:00:26.98#ibcon#about to read 3, iclass 14, count 2 2006.173.06:00:27.01#ibcon#read 3, iclass 14, count 2 2006.173.06:00:27.01#ibcon#about to read 4, iclass 14, count 2 2006.173.06:00:27.01#ibcon#read 4, iclass 14, count 2 2006.173.06:00:27.01#ibcon#about to read 5, iclass 14, count 2 2006.173.06:00:27.01#ibcon#read 5, iclass 14, count 2 2006.173.06:00:27.01#ibcon#about to read 6, iclass 14, count 2 2006.173.06:00:27.01#ibcon#read 6, iclass 14, count 2 2006.173.06:00:27.01#ibcon#end of sib2, iclass 14, count 2 2006.173.06:00:27.01#ibcon#*after write, iclass 14, count 2 2006.173.06:00:27.01#ibcon#*before return 0, iclass 14, count 2 2006.173.06:00:27.01#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.06:00:27.01#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.06:00:27.01#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.06:00:27.01#ibcon#ireg 7 cls_cnt 0 2006.173.06:00:27.01#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.06:00:27.13#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.06:00:27.13#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.06:00:27.13#ibcon#enter wrdev, iclass 14, count 0 2006.173.06:00:27.13#ibcon#first serial, iclass 14, count 0 2006.173.06:00:27.13#ibcon#enter sib2, iclass 14, count 0 2006.173.06:00:27.13#ibcon#flushed, iclass 14, count 0 2006.173.06:00:27.13#ibcon#about to write, iclass 14, count 0 2006.173.06:00:27.13#ibcon#wrote, iclass 14, count 0 2006.173.06:00:27.13#ibcon#about to read 3, iclass 14, count 0 2006.173.06:00:27.15#ibcon#read 3, iclass 14, count 0 2006.173.06:00:27.15#ibcon#about to read 4, iclass 14, count 0 2006.173.06:00:27.15#ibcon#read 4, iclass 14, count 0 2006.173.06:00:27.15#ibcon#about to read 5, iclass 14, count 0 2006.173.06:00:27.15#ibcon#read 5, iclass 14, count 0 2006.173.06:00:27.15#ibcon#about to read 6, iclass 14, count 0 2006.173.06:00:27.15#ibcon#read 6, iclass 14, count 0 2006.173.06:00:27.15#ibcon#end of sib2, iclass 14, count 0 2006.173.06:00:27.15#ibcon#*mode == 0, iclass 14, count 0 2006.173.06:00:27.15#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.06:00:27.15#ibcon#[27=USB\r\n] 2006.173.06:00:27.15#ibcon#*before write, iclass 14, count 0 2006.173.06:00:27.15#ibcon#enter sib2, iclass 14, count 0 2006.173.06:00:27.15#ibcon#flushed, iclass 14, count 0 2006.173.06:00:27.15#ibcon#about to write, iclass 14, count 0 2006.173.06:00:27.15#ibcon#wrote, iclass 14, count 0 2006.173.06:00:27.15#ibcon#about to read 3, iclass 14, count 0 2006.173.06:00:27.18#ibcon#read 3, iclass 14, count 0 2006.173.06:00:27.18#ibcon#about to read 4, iclass 14, count 0 2006.173.06:00:27.18#ibcon#read 4, iclass 14, count 0 2006.173.06:00:27.18#ibcon#about to read 5, iclass 14, count 0 2006.173.06:00:27.18#ibcon#read 5, iclass 14, count 0 2006.173.06:00:27.18#ibcon#about to read 6, iclass 14, count 0 2006.173.06:00:27.18#ibcon#read 6, iclass 14, count 0 2006.173.06:00:27.18#ibcon#end of sib2, iclass 14, count 0 2006.173.06:00:27.18#ibcon#*after write, iclass 14, count 0 2006.173.06:00:27.18#ibcon#*before return 0, iclass 14, count 0 2006.173.06:00:27.18#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.06:00:27.18#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.06:00:27.18#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.06:00:27.18#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.06:00:27.18$vck44/vblo=8,744.99 2006.173.06:00:27.18#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.06:00:27.18#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.06:00:27.18#ibcon#ireg 17 cls_cnt 0 2006.173.06:00:27.18#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.06:00:27.18#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.06:00:27.18#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.06:00:27.18#ibcon#enter wrdev, iclass 16, count 0 2006.173.06:00:27.18#ibcon#first serial, iclass 16, count 0 2006.173.06:00:27.18#ibcon#enter sib2, iclass 16, count 0 2006.173.06:00:27.18#ibcon#flushed, iclass 16, count 0 2006.173.06:00:27.18#ibcon#about to write, iclass 16, count 0 2006.173.06:00:27.18#ibcon#wrote, iclass 16, count 0 2006.173.06:00:27.18#ibcon#about to read 3, iclass 16, count 0 2006.173.06:00:27.20#ibcon#read 3, iclass 16, count 0 2006.173.06:00:27.20#ibcon#about to read 4, iclass 16, count 0 2006.173.06:00:27.20#ibcon#read 4, iclass 16, count 0 2006.173.06:00:27.20#ibcon#about to read 5, iclass 16, count 0 2006.173.06:00:27.20#ibcon#read 5, iclass 16, count 0 2006.173.06:00:27.20#ibcon#about to read 6, iclass 16, count 0 2006.173.06:00:27.20#ibcon#read 6, iclass 16, count 0 2006.173.06:00:27.20#ibcon#end of sib2, iclass 16, count 0 2006.173.06:00:27.20#ibcon#*mode == 0, iclass 16, count 0 2006.173.06:00:27.20#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.06:00:27.20#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.06:00:27.20#ibcon#*before write, iclass 16, count 0 2006.173.06:00:27.20#ibcon#enter sib2, iclass 16, count 0 2006.173.06:00:27.20#ibcon#flushed, iclass 16, count 0 2006.173.06:00:27.20#ibcon#about to write, iclass 16, count 0 2006.173.06:00:27.20#ibcon#wrote, iclass 16, count 0 2006.173.06:00:27.20#ibcon#about to read 3, iclass 16, count 0 2006.173.06:00:27.24#ibcon#read 3, iclass 16, count 0 2006.173.06:00:27.24#ibcon#about to read 4, iclass 16, count 0 2006.173.06:00:27.24#ibcon#read 4, iclass 16, count 0 2006.173.06:00:27.24#ibcon#about to read 5, iclass 16, count 0 2006.173.06:00:27.24#ibcon#read 5, iclass 16, count 0 2006.173.06:00:27.24#ibcon#about to read 6, iclass 16, count 0 2006.173.06:00:27.24#ibcon#read 6, iclass 16, count 0 2006.173.06:00:27.24#ibcon#end of sib2, iclass 16, count 0 2006.173.06:00:27.24#ibcon#*after write, iclass 16, count 0 2006.173.06:00:27.24#ibcon#*before return 0, iclass 16, count 0 2006.173.06:00:27.24#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.06:00:27.24#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.06:00:27.24#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.06:00:27.24#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.06:00:27.24$vck44/vb=8,4 2006.173.06:00:27.24#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.06:00:27.24#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.06:00:27.24#ibcon#ireg 11 cls_cnt 2 2006.173.06:00:27.24#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.06:00:27.30#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.06:00:27.30#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.06:00:27.30#ibcon#enter wrdev, iclass 18, count 2 2006.173.06:00:27.30#ibcon#first serial, iclass 18, count 2 2006.173.06:00:27.30#ibcon#enter sib2, iclass 18, count 2 2006.173.06:00:27.30#ibcon#flushed, iclass 18, count 2 2006.173.06:00:27.30#ibcon#about to write, iclass 18, count 2 2006.173.06:00:27.30#ibcon#wrote, iclass 18, count 2 2006.173.06:00:27.30#ibcon#about to read 3, iclass 18, count 2 2006.173.06:00:27.32#ibcon#read 3, iclass 18, count 2 2006.173.06:00:27.32#ibcon#about to read 4, iclass 18, count 2 2006.173.06:00:27.32#ibcon#read 4, iclass 18, count 2 2006.173.06:00:27.32#ibcon#about to read 5, iclass 18, count 2 2006.173.06:00:27.32#ibcon#read 5, iclass 18, count 2 2006.173.06:00:27.32#ibcon#about to read 6, iclass 18, count 2 2006.173.06:00:27.32#ibcon#read 6, iclass 18, count 2 2006.173.06:00:27.32#ibcon#end of sib2, iclass 18, count 2 2006.173.06:00:27.32#ibcon#*mode == 0, iclass 18, count 2 2006.173.06:00:27.32#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.06:00:27.32#ibcon#[27=AT08-04\r\n] 2006.173.06:00:27.32#ibcon#*before write, iclass 18, count 2 2006.173.06:00:27.32#ibcon#enter sib2, iclass 18, count 2 2006.173.06:00:27.32#ibcon#flushed, iclass 18, count 2 2006.173.06:00:27.32#ibcon#about to write, iclass 18, count 2 2006.173.06:00:27.32#ibcon#wrote, iclass 18, count 2 2006.173.06:00:27.32#ibcon#about to read 3, iclass 18, count 2 2006.173.06:00:27.35#ibcon#read 3, iclass 18, count 2 2006.173.06:00:27.35#ibcon#about to read 4, iclass 18, count 2 2006.173.06:00:27.35#ibcon#read 4, iclass 18, count 2 2006.173.06:00:27.35#ibcon#about to read 5, iclass 18, count 2 2006.173.06:00:27.35#ibcon#read 5, iclass 18, count 2 2006.173.06:00:27.35#ibcon#about to read 6, iclass 18, count 2 2006.173.06:00:27.35#ibcon#read 6, iclass 18, count 2 2006.173.06:00:27.35#ibcon#end of sib2, iclass 18, count 2 2006.173.06:00:27.35#ibcon#*after write, iclass 18, count 2 2006.173.06:00:27.35#ibcon#*before return 0, iclass 18, count 2 2006.173.06:00:27.35#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.06:00:27.35#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.06:00:27.35#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.06:00:27.35#ibcon#ireg 7 cls_cnt 0 2006.173.06:00:27.35#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.06:00:27.47#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.06:00:27.47#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.06:00:27.47#ibcon#enter wrdev, iclass 18, count 0 2006.173.06:00:27.47#ibcon#first serial, iclass 18, count 0 2006.173.06:00:27.47#ibcon#enter sib2, iclass 18, count 0 2006.173.06:00:27.47#ibcon#flushed, iclass 18, count 0 2006.173.06:00:27.47#ibcon#about to write, iclass 18, count 0 2006.173.06:00:27.47#ibcon#wrote, iclass 18, count 0 2006.173.06:00:27.47#ibcon#about to read 3, iclass 18, count 0 2006.173.06:00:27.49#ibcon#read 3, iclass 18, count 0 2006.173.06:00:27.49#ibcon#about to read 4, iclass 18, count 0 2006.173.06:00:27.49#ibcon#read 4, iclass 18, count 0 2006.173.06:00:27.49#ibcon#about to read 5, iclass 18, count 0 2006.173.06:00:27.49#ibcon#read 5, iclass 18, count 0 2006.173.06:00:27.49#ibcon#about to read 6, iclass 18, count 0 2006.173.06:00:27.49#ibcon#read 6, iclass 18, count 0 2006.173.06:00:27.49#ibcon#end of sib2, iclass 18, count 0 2006.173.06:00:27.49#ibcon#*mode == 0, iclass 18, count 0 2006.173.06:00:27.49#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.06:00:27.49#ibcon#[27=USB\r\n] 2006.173.06:00:27.49#ibcon#*before write, iclass 18, count 0 2006.173.06:00:27.49#ibcon#enter sib2, iclass 18, count 0 2006.173.06:00:27.49#ibcon#flushed, iclass 18, count 0 2006.173.06:00:27.49#ibcon#about to write, iclass 18, count 0 2006.173.06:00:27.49#ibcon#wrote, iclass 18, count 0 2006.173.06:00:27.49#ibcon#about to read 3, iclass 18, count 0 2006.173.06:00:27.52#ibcon#read 3, iclass 18, count 0 2006.173.06:00:27.52#ibcon#about to read 4, iclass 18, count 0 2006.173.06:00:27.52#ibcon#read 4, iclass 18, count 0 2006.173.06:00:27.52#ibcon#about to read 5, iclass 18, count 0 2006.173.06:00:27.52#ibcon#read 5, iclass 18, count 0 2006.173.06:00:27.52#ibcon#about to read 6, iclass 18, count 0 2006.173.06:00:27.52#ibcon#read 6, iclass 18, count 0 2006.173.06:00:27.52#ibcon#end of sib2, iclass 18, count 0 2006.173.06:00:27.52#ibcon#*after write, iclass 18, count 0 2006.173.06:00:27.52#ibcon#*before return 0, iclass 18, count 0 2006.173.06:00:27.52#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.06:00:27.52#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.06:00:27.52#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.06:00:27.52#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.06:00:27.52$vck44/vabw=wide 2006.173.06:00:27.52#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.06:00:27.52#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.06:00:27.52#ibcon#ireg 8 cls_cnt 0 2006.173.06:00:27.52#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.06:00:27.52#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.06:00:27.52#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.06:00:27.52#ibcon#enter wrdev, iclass 20, count 0 2006.173.06:00:27.52#ibcon#first serial, iclass 20, count 0 2006.173.06:00:27.52#ibcon#enter sib2, iclass 20, count 0 2006.173.06:00:27.52#ibcon#flushed, iclass 20, count 0 2006.173.06:00:27.52#ibcon#about to write, iclass 20, count 0 2006.173.06:00:27.52#ibcon#wrote, iclass 20, count 0 2006.173.06:00:27.52#ibcon#about to read 3, iclass 20, count 0 2006.173.06:00:27.54#ibcon#read 3, iclass 20, count 0 2006.173.06:00:27.54#ibcon#about to read 4, iclass 20, count 0 2006.173.06:00:27.54#ibcon#read 4, iclass 20, count 0 2006.173.06:00:27.54#ibcon#about to read 5, iclass 20, count 0 2006.173.06:00:27.54#ibcon#read 5, iclass 20, count 0 2006.173.06:00:27.54#ibcon#about to read 6, iclass 20, count 0 2006.173.06:00:27.54#ibcon#read 6, iclass 20, count 0 2006.173.06:00:27.54#ibcon#end of sib2, iclass 20, count 0 2006.173.06:00:27.54#ibcon#*mode == 0, iclass 20, count 0 2006.173.06:00:27.54#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.06:00:27.54#ibcon#[25=BW32\r\n] 2006.173.06:00:27.54#ibcon#*before write, iclass 20, count 0 2006.173.06:00:27.54#ibcon#enter sib2, iclass 20, count 0 2006.173.06:00:27.54#ibcon#flushed, iclass 20, count 0 2006.173.06:00:27.54#ibcon#about to write, iclass 20, count 0 2006.173.06:00:27.54#ibcon#wrote, iclass 20, count 0 2006.173.06:00:27.54#ibcon#about to read 3, iclass 20, count 0 2006.173.06:00:27.57#ibcon#read 3, iclass 20, count 0 2006.173.06:00:27.57#ibcon#about to read 4, iclass 20, count 0 2006.173.06:00:27.57#ibcon#read 4, iclass 20, count 0 2006.173.06:00:27.57#ibcon#about to read 5, iclass 20, count 0 2006.173.06:00:27.57#ibcon#read 5, iclass 20, count 0 2006.173.06:00:27.57#ibcon#about to read 6, iclass 20, count 0 2006.173.06:00:27.57#ibcon#read 6, iclass 20, count 0 2006.173.06:00:27.57#ibcon#end of sib2, iclass 20, count 0 2006.173.06:00:27.57#ibcon#*after write, iclass 20, count 0 2006.173.06:00:27.57#ibcon#*before return 0, iclass 20, count 0 2006.173.06:00:27.57#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.06:00:27.57#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.06:00:27.57#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.06:00:27.57#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.06:00:27.57$vck44/vbbw=wide 2006.173.06:00:27.57#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.06:00:27.57#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.06:00:27.57#ibcon#ireg 8 cls_cnt 0 2006.173.06:00:27.57#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.06:00:27.64#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.06:00:27.64#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.06:00:27.64#ibcon#enter wrdev, iclass 22, count 0 2006.173.06:00:27.64#ibcon#first serial, iclass 22, count 0 2006.173.06:00:27.64#ibcon#enter sib2, iclass 22, count 0 2006.173.06:00:27.64#ibcon#flushed, iclass 22, count 0 2006.173.06:00:27.64#ibcon#about to write, iclass 22, count 0 2006.173.06:00:27.64#ibcon#wrote, iclass 22, count 0 2006.173.06:00:27.64#ibcon#about to read 3, iclass 22, count 0 2006.173.06:00:27.66#ibcon#read 3, iclass 22, count 0 2006.173.06:00:27.66#ibcon#about to read 4, iclass 22, count 0 2006.173.06:00:27.66#ibcon#read 4, iclass 22, count 0 2006.173.06:00:27.66#ibcon#about to read 5, iclass 22, count 0 2006.173.06:00:27.66#ibcon#read 5, iclass 22, count 0 2006.173.06:00:27.66#ibcon#about to read 6, iclass 22, count 0 2006.173.06:00:27.66#ibcon#read 6, iclass 22, count 0 2006.173.06:00:27.66#ibcon#end of sib2, iclass 22, count 0 2006.173.06:00:27.66#ibcon#*mode == 0, iclass 22, count 0 2006.173.06:00:27.66#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.06:00:27.66#ibcon#[27=BW32\r\n] 2006.173.06:00:27.66#ibcon#*before write, iclass 22, count 0 2006.173.06:00:27.66#ibcon#enter sib2, iclass 22, count 0 2006.173.06:00:27.66#ibcon#flushed, iclass 22, count 0 2006.173.06:00:27.66#ibcon#about to write, iclass 22, count 0 2006.173.06:00:27.66#ibcon#wrote, iclass 22, count 0 2006.173.06:00:27.66#ibcon#about to read 3, iclass 22, count 0 2006.173.06:00:27.68#abcon#<5=/16 0.3 0.8 23.69 741005.2\r\n> 2006.173.06:00:27.69#ibcon#read 3, iclass 22, count 0 2006.173.06:00:27.69#ibcon#about to read 4, iclass 22, count 0 2006.173.06:00:27.69#ibcon#read 4, iclass 22, count 0 2006.173.06:00:27.69#ibcon#about to read 5, iclass 22, count 0 2006.173.06:00:27.69#ibcon#read 5, iclass 22, count 0 2006.173.06:00:27.69#ibcon#about to read 6, iclass 22, count 0 2006.173.06:00:27.69#ibcon#read 6, iclass 22, count 0 2006.173.06:00:27.69#ibcon#end of sib2, iclass 22, count 0 2006.173.06:00:27.69#ibcon#*after write, iclass 22, count 0 2006.173.06:00:27.69#ibcon#*before return 0, iclass 22, count 0 2006.173.06:00:27.69#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.06:00:27.69#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.06:00:27.69#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.06:00:27.69#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.06:00:27.69$setupk4/ifdk4 2006.173.06:00:27.69$ifdk4/lo= 2006.173.06:00:27.69$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.06:00:27.69$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.06:00:27.69$ifdk4/patch= 2006.173.06:00:27.70$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.06:00:27.70$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.06:00:27.70$setupk4/!*+20s 2006.173.06:00:27.70#abcon#{5=INTERFACE CLEAR} 2006.173.06:00:27.76#abcon#[5=S1D000X0/0*\r\n] 2006.173.06:00:38.00#abcon#<5=/16 0.3 0.8 23.70 731005.2\r\n> 2006.173.06:00:38.02#abcon#{5=INTERFACE CLEAR} 2006.173.06:00:38.08#abcon#[5=S1D000X0/0*\r\n] 2006.173.06:00:38.14#trakl#Source acquired 2006.173.06:00:38.14#flagr#flagr/antenna,acquired 2006.173.06:00:42.20$setupk4/"tpicd 2006.173.06:00:42.20$setupk4/echo=off 2006.173.06:00:42.20$setupk4/xlog=off 2006.173.06:00:42.20:!2006.173.06:05:28 2006.173.06:05:28.00:preob 2006.173.06:05:28.14/onsource/TRACKING 2006.173.06:05:28.14:!2006.173.06:05:38 2006.173.06:05:38.00:"tape 2006.173.06:05:38.00:"st=record 2006.173.06:05:38.00:data_valid=on 2006.173.06:05:38.00:midob 2006.173.06:05:38.14/onsource/TRACKING 2006.173.06:05:38.14/wx/23.72,1005.1,75 2006.173.06:05:38.24/cable/+6.5046E-03 2006.173.06:05:39.33/va/01,07,usb,yes,35,37 2006.173.06:05:39.33/va/02,06,usb,yes,34,35 2006.173.06:05:39.33/va/03,05,usb,yes,44,46 2006.173.06:05:39.33/va/04,06,usb,yes,35,37 2006.173.06:05:39.33/va/05,04,usb,yes,27,28 2006.173.06:05:39.33/va/06,03,usb,yes,39,38 2006.173.06:05:39.33/va/07,04,usb,yes,31,32 2006.173.06:05:39.33/va/08,04,usb,yes,26,32 2006.173.06:05:39.56/valo/01,524.99,yes,locked 2006.173.06:05:39.56/valo/02,534.99,yes,locked 2006.173.06:05:39.56/valo/03,564.99,yes,locked 2006.173.06:05:39.56/valo/04,624.99,yes,locked 2006.173.06:05:39.56/valo/05,734.99,yes,locked 2006.173.06:05:39.56/valo/06,814.99,yes,locked 2006.173.06:05:39.56/valo/07,864.99,yes,locked 2006.173.06:05:39.56/valo/08,884.99,yes,locked 2006.173.06:05:40.65/vb/01,04,usb,yes,29,27 2006.173.06:05:40.65/vb/02,04,usb,yes,31,31 2006.173.06:05:40.65/vb/03,04,usb,yes,28,31 2006.173.06:05:40.65/vb/04,04,usb,yes,33,32 2006.173.06:05:40.65/vb/05,04,usb,yes,25,28 2006.173.06:05:40.65/vb/06,04,usb,yes,30,26 2006.173.06:05:40.65/vb/07,04,usb,yes,29,29 2006.173.06:05:40.65/vb/08,04,usb,yes,27,30 2006.173.06:05:40.88/vblo/01,629.99,yes,locked 2006.173.06:05:40.88/vblo/02,634.99,yes,locked 2006.173.06:05:40.88/vblo/03,649.99,yes,locked 2006.173.06:05:40.88/vblo/04,679.99,yes,locked 2006.173.06:05:40.88/vblo/05,709.99,yes,locked 2006.173.06:05:40.88/vblo/06,719.99,yes,locked 2006.173.06:05:40.88/vblo/07,734.99,yes,locked 2006.173.06:05:40.88/vblo/08,744.99,yes,locked 2006.173.06:05:41.03/vabw/8 2006.173.06:05:41.18/vbbw/8 2006.173.06:05:41.27/xfe/off,on,15.5 2006.173.06:05:41.67/ifatt/23,28,28,28 2006.173.06:05:42.07/fmout-gps/S +4.06E-07 2006.173.06:05:42.11:!2006.173.06:11:58 2006.173.06:11:58.00:data_valid=off 2006.173.06:11:58.00:"et 2006.173.06:11:58.00:!+3s 2006.173.06:12:01.01:"tape 2006.173.06:12:01.01:postob 2006.173.06:12:01.08/cable/+6.5030E-03 2006.173.06:12:01.08/wx/23.85,1005.2,77 2006.173.06:12:02.07/fmout-gps/S +4.01E-07 2006.173.06:12:02.07:scan_name=173-0612,jd0606,40 2006.173.06:12:02.07:source=3c345,164258.81,394837.0,2000.0,ccw 2006.173.06:12:03.13:checkk5 2006.173.06:12:03.13#flagr#flagr/antenna,new-source 2006.173.06:12:03.53/chk_autoobs//k5ts1/ autoobs is running! 2006.173.06:12:03.94/chk_autoobs//k5ts2/ autoobs is running! 2006.173.06:12:04.34/chk_autoobs//k5ts3/ autoobs is running! 2006.173.06:12:04.75/chk_autoobs//k5ts4/ autoobs is running! 2006.173.06:12:05.13/chk_obsdata//k5ts1/T1730605??a.dat file size is correct (nominal:1520MB, actual:1520MB). 2006.173.06:12:05.54/chk_obsdata//k5ts2/T1730605??b.dat file size is correct (nominal:1520MB, actual:1520MB). 2006.173.06:12:05.93/chk_obsdata//k5ts3/T1730605??c.dat file size is correct (nominal:1520MB, actual:1520MB). 2006.173.06:12:06.33/chk_obsdata//k5ts4/T1730605??d.dat file size is correct (nominal:1520MB, actual:1520MB). 2006.173.06:12:07.04/k5log//k5ts1_log_newline 2006.173.06:12:07.74/k5log//k5ts2_log_newline 2006.173.06:12:08.44/k5log//k5ts3_log_newline 2006.173.06:12:09.14/k5log//k5ts4_log_newline 2006.173.06:12:09.17/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.06:12:09.17:setupk4=1 2006.173.06:12:09.17$setupk4/echo=on 2006.173.06:12:09.17$setupk4/pcalon 2006.173.06:12:09.17$pcalon/"no phase cal control is implemented here 2006.173.06:12:09.17$setupk4/"tpicd=stop 2006.173.06:12:09.17$setupk4/"rec=synch_on 2006.173.06:12:09.17$setupk4/"rec_mode=128 2006.173.06:12:09.17$setupk4/!* 2006.173.06:12:09.17$setupk4/recpk4 2006.173.06:12:09.17$recpk4/recpatch= 2006.173.06:12:09.17$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.06:12:09.17$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.06:12:09.18$setupk4/vck44 2006.173.06:12:09.18$vck44/valo=1,524.99 2006.173.06:12:09.18#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.06:12:09.18#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.06:12:09.18#ibcon#ireg 17 cls_cnt 0 2006.173.06:12:09.18#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.06:12:09.18#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.06:12:09.18#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.06:12:09.18#ibcon#enter wrdev, iclass 15, count 0 2006.173.06:12:09.18#ibcon#first serial, iclass 15, count 0 2006.173.06:12:09.18#ibcon#enter sib2, iclass 15, count 0 2006.173.06:12:09.18#ibcon#flushed, iclass 15, count 0 2006.173.06:12:09.18#ibcon#about to write, iclass 15, count 0 2006.173.06:12:09.18#ibcon#wrote, iclass 15, count 0 2006.173.06:12:09.18#ibcon#about to read 3, iclass 15, count 0 2006.173.06:12:09.19#ibcon#read 3, iclass 15, count 0 2006.173.06:12:09.19#ibcon#about to read 4, iclass 15, count 0 2006.173.06:12:09.19#ibcon#read 4, iclass 15, count 0 2006.173.06:12:09.19#ibcon#about to read 5, iclass 15, count 0 2006.173.06:12:09.19#ibcon#read 5, iclass 15, count 0 2006.173.06:12:09.19#ibcon#about to read 6, iclass 15, count 0 2006.173.06:12:09.19#ibcon#read 6, iclass 15, count 0 2006.173.06:12:09.19#ibcon#end of sib2, iclass 15, count 0 2006.173.06:12:09.19#ibcon#*mode == 0, iclass 15, count 0 2006.173.06:12:09.19#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.06:12:09.19#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.06:12:09.19#ibcon#*before write, iclass 15, count 0 2006.173.06:12:09.19#ibcon#enter sib2, iclass 15, count 0 2006.173.06:12:09.19#ibcon#flushed, iclass 15, count 0 2006.173.06:12:09.19#ibcon#about to write, iclass 15, count 0 2006.173.06:12:09.19#ibcon#wrote, iclass 15, count 0 2006.173.06:12:09.19#ibcon#about to read 3, iclass 15, count 0 2006.173.06:12:09.24#ibcon#read 3, iclass 15, count 0 2006.173.06:12:09.24#ibcon#about to read 4, iclass 15, count 0 2006.173.06:12:09.24#ibcon#read 4, iclass 15, count 0 2006.173.06:12:09.24#ibcon#about to read 5, iclass 15, count 0 2006.173.06:12:09.24#ibcon#read 5, iclass 15, count 0 2006.173.06:12:09.24#ibcon#about to read 6, iclass 15, count 0 2006.173.06:12:09.24#ibcon#read 6, iclass 15, count 0 2006.173.06:12:09.24#ibcon#end of sib2, iclass 15, count 0 2006.173.06:12:09.24#ibcon#*after write, iclass 15, count 0 2006.173.06:12:09.24#ibcon#*before return 0, iclass 15, count 0 2006.173.06:12:09.24#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.06:12:09.24#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.06:12:09.24#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.06:12:09.24#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.06:12:09.24$vck44/va=1,7 2006.173.06:12:09.24#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.06:12:09.24#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.06:12:09.24#ibcon#ireg 11 cls_cnt 2 2006.173.06:12:09.24#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.06:12:09.24#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.06:12:09.24#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.06:12:09.24#ibcon#enter wrdev, iclass 17, count 2 2006.173.06:12:09.24#ibcon#first serial, iclass 17, count 2 2006.173.06:12:09.24#ibcon#enter sib2, iclass 17, count 2 2006.173.06:12:09.24#ibcon#flushed, iclass 17, count 2 2006.173.06:12:09.24#ibcon#about to write, iclass 17, count 2 2006.173.06:12:09.24#ibcon#wrote, iclass 17, count 2 2006.173.06:12:09.24#ibcon#about to read 3, iclass 17, count 2 2006.173.06:12:09.26#ibcon#read 3, iclass 17, count 2 2006.173.06:12:09.26#ibcon#about to read 4, iclass 17, count 2 2006.173.06:12:09.26#ibcon#read 4, iclass 17, count 2 2006.173.06:12:09.26#ibcon#about to read 5, iclass 17, count 2 2006.173.06:12:09.26#ibcon#read 5, iclass 17, count 2 2006.173.06:12:09.26#ibcon#about to read 6, iclass 17, count 2 2006.173.06:12:09.26#ibcon#read 6, iclass 17, count 2 2006.173.06:12:09.26#ibcon#end of sib2, iclass 17, count 2 2006.173.06:12:09.26#ibcon#*mode == 0, iclass 17, count 2 2006.173.06:12:09.26#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.06:12:09.26#ibcon#[25=AT01-07\r\n] 2006.173.06:12:09.26#ibcon#*before write, iclass 17, count 2 2006.173.06:12:09.26#ibcon#enter sib2, iclass 17, count 2 2006.173.06:12:09.26#ibcon#flushed, iclass 17, count 2 2006.173.06:12:09.26#ibcon#about to write, iclass 17, count 2 2006.173.06:12:09.26#ibcon#wrote, iclass 17, count 2 2006.173.06:12:09.26#ibcon#about to read 3, iclass 17, count 2 2006.173.06:12:09.29#ibcon#read 3, iclass 17, count 2 2006.173.06:12:09.29#ibcon#about to read 4, iclass 17, count 2 2006.173.06:12:09.29#ibcon#read 4, iclass 17, count 2 2006.173.06:12:09.29#ibcon#about to read 5, iclass 17, count 2 2006.173.06:12:09.29#ibcon#read 5, iclass 17, count 2 2006.173.06:12:09.29#ibcon#about to read 6, iclass 17, count 2 2006.173.06:12:09.29#ibcon#read 6, iclass 17, count 2 2006.173.06:12:09.29#ibcon#end of sib2, iclass 17, count 2 2006.173.06:12:09.29#ibcon#*after write, iclass 17, count 2 2006.173.06:12:09.29#ibcon#*before return 0, iclass 17, count 2 2006.173.06:12:09.29#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.06:12:09.29#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.06:12:09.29#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.06:12:09.29#ibcon#ireg 7 cls_cnt 0 2006.173.06:12:09.29#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.06:12:09.41#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.06:12:09.41#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.06:12:09.41#ibcon#enter wrdev, iclass 17, count 0 2006.173.06:12:09.41#ibcon#first serial, iclass 17, count 0 2006.173.06:12:09.41#ibcon#enter sib2, iclass 17, count 0 2006.173.06:12:09.41#ibcon#flushed, iclass 17, count 0 2006.173.06:12:09.41#ibcon#about to write, iclass 17, count 0 2006.173.06:12:09.41#ibcon#wrote, iclass 17, count 0 2006.173.06:12:09.41#ibcon#about to read 3, iclass 17, count 0 2006.173.06:12:09.43#ibcon#read 3, iclass 17, count 0 2006.173.06:12:09.43#ibcon#about to read 4, iclass 17, count 0 2006.173.06:12:09.43#ibcon#read 4, iclass 17, count 0 2006.173.06:12:09.43#ibcon#about to read 5, iclass 17, count 0 2006.173.06:12:09.43#ibcon#read 5, iclass 17, count 0 2006.173.06:12:09.43#ibcon#about to read 6, iclass 17, count 0 2006.173.06:12:09.43#ibcon#read 6, iclass 17, count 0 2006.173.06:12:09.43#ibcon#end of sib2, iclass 17, count 0 2006.173.06:12:09.43#ibcon#*mode == 0, iclass 17, count 0 2006.173.06:12:09.43#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.06:12:09.43#ibcon#[25=USB\r\n] 2006.173.06:12:09.43#ibcon#*before write, iclass 17, count 0 2006.173.06:12:09.43#ibcon#enter sib2, iclass 17, count 0 2006.173.06:12:09.43#ibcon#flushed, iclass 17, count 0 2006.173.06:12:09.43#ibcon#about to write, iclass 17, count 0 2006.173.06:12:09.43#ibcon#wrote, iclass 17, count 0 2006.173.06:12:09.43#ibcon#about to read 3, iclass 17, count 0 2006.173.06:12:09.46#ibcon#read 3, iclass 17, count 0 2006.173.06:12:09.46#ibcon#about to read 4, iclass 17, count 0 2006.173.06:12:09.46#ibcon#read 4, iclass 17, count 0 2006.173.06:12:09.46#ibcon#about to read 5, iclass 17, count 0 2006.173.06:12:09.46#ibcon#read 5, iclass 17, count 0 2006.173.06:12:09.46#ibcon#about to read 6, iclass 17, count 0 2006.173.06:12:09.46#ibcon#read 6, iclass 17, count 0 2006.173.06:12:09.46#ibcon#end of sib2, iclass 17, count 0 2006.173.06:12:09.46#ibcon#*after write, iclass 17, count 0 2006.173.06:12:09.46#ibcon#*before return 0, iclass 17, count 0 2006.173.06:12:09.46#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.06:12:09.46#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.06:12:09.46#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.06:12:09.46#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.06:12:09.46$vck44/valo=2,534.99 2006.173.06:12:09.46#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.06:12:09.46#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.06:12:09.46#ibcon#ireg 17 cls_cnt 0 2006.173.06:12:09.46#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.06:12:09.46#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.06:12:09.46#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.06:12:09.46#ibcon#enter wrdev, iclass 19, count 0 2006.173.06:12:09.46#ibcon#first serial, iclass 19, count 0 2006.173.06:12:09.46#ibcon#enter sib2, iclass 19, count 0 2006.173.06:12:09.46#ibcon#flushed, iclass 19, count 0 2006.173.06:12:09.46#ibcon#about to write, iclass 19, count 0 2006.173.06:12:09.46#ibcon#wrote, iclass 19, count 0 2006.173.06:12:09.46#ibcon#about to read 3, iclass 19, count 0 2006.173.06:12:09.48#ibcon#read 3, iclass 19, count 0 2006.173.06:12:09.48#ibcon#about to read 4, iclass 19, count 0 2006.173.06:12:09.48#ibcon#read 4, iclass 19, count 0 2006.173.06:12:09.48#ibcon#about to read 5, iclass 19, count 0 2006.173.06:12:09.48#ibcon#read 5, iclass 19, count 0 2006.173.06:12:09.48#ibcon#about to read 6, iclass 19, count 0 2006.173.06:12:09.48#ibcon#read 6, iclass 19, count 0 2006.173.06:12:09.48#ibcon#end of sib2, iclass 19, count 0 2006.173.06:12:09.48#ibcon#*mode == 0, iclass 19, count 0 2006.173.06:12:09.48#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.06:12:09.48#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.06:12:09.48#ibcon#*before write, iclass 19, count 0 2006.173.06:12:09.48#ibcon#enter sib2, iclass 19, count 0 2006.173.06:12:09.48#ibcon#flushed, iclass 19, count 0 2006.173.06:12:09.48#ibcon#about to write, iclass 19, count 0 2006.173.06:12:09.48#ibcon#wrote, iclass 19, count 0 2006.173.06:12:09.48#ibcon#about to read 3, iclass 19, count 0 2006.173.06:12:09.52#ibcon#read 3, iclass 19, count 0 2006.173.06:12:09.52#ibcon#about to read 4, iclass 19, count 0 2006.173.06:12:09.52#ibcon#read 4, iclass 19, count 0 2006.173.06:12:09.52#ibcon#about to read 5, iclass 19, count 0 2006.173.06:12:09.52#ibcon#read 5, iclass 19, count 0 2006.173.06:12:09.52#ibcon#about to read 6, iclass 19, count 0 2006.173.06:12:09.52#ibcon#read 6, iclass 19, count 0 2006.173.06:12:09.52#ibcon#end of sib2, iclass 19, count 0 2006.173.06:12:09.52#ibcon#*after write, iclass 19, count 0 2006.173.06:12:09.52#ibcon#*before return 0, iclass 19, count 0 2006.173.06:12:09.52#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.06:12:09.52#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.06:12:09.52#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.06:12:09.52#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.06:12:09.52$vck44/va=2,6 2006.173.06:12:09.52#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.06:12:09.52#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.06:12:09.52#ibcon#ireg 11 cls_cnt 2 2006.173.06:12:09.52#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.06:12:09.58#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.06:12:09.58#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.06:12:09.58#ibcon#enter wrdev, iclass 21, count 2 2006.173.06:12:09.58#ibcon#first serial, iclass 21, count 2 2006.173.06:12:09.58#ibcon#enter sib2, iclass 21, count 2 2006.173.06:12:09.58#ibcon#flushed, iclass 21, count 2 2006.173.06:12:09.58#ibcon#about to write, iclass 21, count 2 2006.173.06:12:09.58#ibcon#wrote, iclass 21, count 2 2006.173.06:12:09.58#ibcon#about to read 3, iclass 21, count 2 2006.173.06:12:09.60#ibcon#read 3, iclass 21, count 2 2006.173.06:12:09.60#ibcon#about to read 4, iclass 21, count 2 2006.173.06:12:09.60#ibcon#read 4, iclass 21, count 2 2006.173.06:12:09.60#ibcon#about to read 5, iclass 21, count 2 2006.173.06:12:09.60#ibcon#read 5, iclass 21, count 2 2006.173.06:12:09.60#ibcon#about to read 6, iclass 21, count 2 2006.173.06:12:09.60#ibcon#read 6, iclass 21, count 2 2006.173.06:12:09.60#ibcon#end of sib2, iclass 21, count 2 2006.173.06:12:09.60#ibcon#*mode == 0, iclass 21, count 2 2006.173.06:12:09.60#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.06:12:09.60#ibcon#[25=AT02-06\r\n] 2006.173.06:12:09.60#ibcon#*before write, iclass 21, count 2 2006.173.06:12:09.60#ibcon#enter sib2, iclass 21, count 2 2006.173.06:12:09.60#ibcon#flushed, iclass 21, count 2 2006.173.06:12:09.60#ibcon#about to write, iclass 21, count 2 2006.173.06:12:09.60#ibcon#wrote, iclass 21, count 2 2006.173.06:12:09.60#ibcon#about to read 3, iclass 21, count 2 2006.173.06:12:09.63#ibcon#read 3, iclass 21, count 2 2006.173.06:12:09.63#ibcon#about to read 4, iclass 21, count 2 2006.173.06:12:09.63#ibcon#read 4, iclass 21, count 2 2006.173.06:12:09.63#ibcon#about to read 5, iclass 21, count 2 2006.173.06:12:09.63#ibcon#read 5, iclass 21, count 2 2006.173.06:12:09.63#ibcon#about to read 6, iclass 21, count 2 2006.173.06:12:09.63#ibcon#read 6, iclass 21, count 2 2006.173.06:12:09.63#ibcon#end of sib2, iclass 21, count 2 2006.173.06:12:09.63#ibcon#*after write, iclass 21, count 2 2006.173.06:12:09.63#ibcon#*before return 0, iclass 21, count 2 2006.173.06:12:09.63#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.06:12:09.63#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.06:12:09.63#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.06:12:09.63#ibcon#ireg 7 cls_cnt 0 2006.173.06:12:09.63#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.06:12:09.69#abcon#<5=/01 0.6 0.9 23.86 761005.2\r\n> 2006.173.06:12:09.71#abcon#{5=INTERFACE CLEAR} 2006.173.06:12:09.75#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.06:12:09.75#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.06:12:09.75#ibcon#enter wrdev, iclass 21, count 0 2006.173.06:12:09.75#ibcon#first serial, iclass 21, count 0 2006.173.06:12:09.75#ibcon#enter sib2, iclass 21, count 0 2006.173.06:12:09.75#ibcon#flushed, iclass 21, count 0 2006.173.06:12:09.75#ibcon#about to write, iclass 21, count 0 2006.173.06:12:09.75#ibcon#wrote, iclass 21, count 0 2006.173.06:12:09.75#ibcon#about to read 3, iclass 21, count 0 2006.173.06:12:09.77#ibcon#read 3, iclass 21, count 0 2006.173.06:12:09.77#ibcon#about to read 4, iclass 21, count 0 2006.173.06:12:09.77#ibcon#read 4, iclass 21, count 0 2006.173.06:12:09.77#ibcon#about to read 5, iclass 21, count 0 2006.173.06:12:09.77#ibcon#read 5, iclass 21, count 0 2006.173.06:12:09.77#ibcon#about to read 6, iclass 21, count 0 2006.173.06:12:09.77#ibcon#read 6, iclass 21, count 0 2006.173.06:12:09.77#ibcon#end of sib2, iclass 21, count 0 2006.173.06:12:09.77#ibcon#*mode == 0, iclass 21, count 0 2006.173.06:12:09.77#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.06:12:09.77#ibcon#[25=USB\r\n] 2006.173.06:12:09.77#ibcon#*before write, iclass 21, count 0 2006.173.06:12:09.77#ibcon#enter sib2, iclass 21, count 0 2006.173.06:12:09.77#ibcon#flushed, iclass 21, count 0 2006.173.06:12:09.77#ibcon#about to write, iclass 21, count 0 2006.173.06:12:09.77#ibcon#wrote, iclass 21, count 0 2006.173.06:12:09.77#ibcon#about to read 3, iclass 21, count 0 2006.173.06:12:09.77#abcon#[5=S1D000X0/0*\r\n] 2006.173.06:12:09.80#ibcon#read 3, iclass 21, count 0 2006.173.06:12:09.80#ibcon#about to read 4, iclass 21, count 0 2006.173.06:12:09.80#ibcon#read 4, iclass 21, count 0 2006.173.06:12:09.80#ibcon#about to read 5, iclass 21, count 0 2006.173.06:12:09.80#ibcon#read 5, iclass 21, count 0 2006.173.06:12:09.80#ibcon#about to read 6, iclass 21, count 0 2006.173.06:12:09.80#ibcon#read 6, iclass 21, count 0 2006.173.06:12:09.80#ibcon#end of sib2, iclass 21, count 0 2006.173.06:12:09.80#ibcon#*after write, iclass 21, count 0 2006.173.06:12:09.80#ibcon#*before return 0, iclass 21, count 0 2006.173.06:12:09.80#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.06:12:09.80#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.06:12:09.80#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.06:12:09.80#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.06:12:09.80$vck44/valo=3,564.99 2006.173.06:12:09.80#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.06:12:09.80#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.06:12:09.80#ibcon#ireg 17 cls_cnt 0 2006.173.06:12:09.80#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.06:12:09.80#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.06:12:09.80#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.06:12:09.80#ibcon#enter wrdev, iclass 27, count 0 2006.173.06:12:09.80#ibcon#first serial, iclass 27, count 0 2006.173.06:12:09.80#ibcon#enter sib2, iclass 27, count 0 2006.173.06:12:09.80#ibcon#flushed, iclass 27, count 0 2006.173.06:12:09.80#ibcon#about to write, iclass 27, count 0 2006.173.06:12:09.80#ibcon#wrote, iclass 27, count 0 2006.173.06:12:09.80#ibcon#about to read 3, iclass 27, count 0 2006.173.06:12:09.82#ibcon#read 3, iclass 27, count 0 2006.173.06:12:09.82#ibcon#about to read 4, iclass 27, count 0 2006.173.06:12:09.82#ibcon#read 4, iclass 27, count 0 2006.173.06:12:09.82#ibcon#about to read 5, iclass 27, count 0 2006.173.06:12:09.82#ibcon#read 5, iclass 27, count 0 2006.173.06:12:09.82#ibcon#about to read 6, iclass 27, count 0 2006.173.06:12:09.82#ibcon#read 6, iclass 27, count 0 2006.173.06:12:09.82#ibcon#end of sib2, iclass 27, count 0 2006.173.06:12:09.82#ibcon#*mode == 0, iclass 27, count 0 2006.173.06:12:09.82#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.06:12:09.82#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.06:12:09.82#ibcon#*before write, iclass 27, count 0 2006.173.06:12:09.82#ibcon#enter sib2, iclass 27, count 0 2006.173.06:12:09.82#ibcon#flushed, iclass 27, count 0 2006.173.06:12:09.82#ibcon#about to write, iclass 27, count 0 2006.173.06:12:09.82#ibcon#wrote, iclass 27, count 0 2006.173.06:12:09.82#ibcon#about to read 3, iclass 27, count 0 2006.173.06:12:09.86#ibcon#read 3, iclass 27, count 0 2006.173.06:12:09.86#ibcon#about to read 4, iclass 27, count 0 2006.173.06:12:09.86#ibcon#read 4, iclass 27, count 0 2006.173.06:12:09.86#ibcon#about to read 5, iclass 27, count 0 2006.173.06:12:09.86#ibcon#read 5, iclass 27, count 0 2006.173.06:12:09.86#ibcon#about to read 6, iclass 27, count 0 2006.173.06:12:09.86#ibcon#read 6, iclass 27, count 0 2006.173.06:12:09.86#ibcon#end of sib2, iclass 27, count 0 2006.173.06:12:09.86#ibcon#*after write, iclass 27, count 0 2006.173.06:12:09.86#ibcon#*before return 0, iclass 27, count 0 2006.173.06:12:09.86#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.06:12:09.86#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.06:12:09.86#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.06:12:09.86#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.06:12:09.86$vck44/va=3,5 2006.173.06:12:09.86#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.06:12:09.86#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.06:12:09.86#ibcon#ireg 11 cls_cnt 2 2006.173.06:12:09.86#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.06:12:09.92#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.06:12:09.92#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.06:12:09.92#ibcon#enter wrdev, iclass 29, count 2 2006.173.06:12:09.92#ibcon#first serial, iclass 29, count 2 2006.173.06:12:09.92#ibcon#enter sib2, iclass 29, count 2 2006.173.06:12:09.92#ibcon#flushed, iclass 29, count 2 2006.173.06:12:09.92#ibcon#about to write, iclass 29, count 2 2006.173.06:12:09.92#ibcon#wrote, iclass 29, count 2 2006.173.06:12:09.92#ibcon#about to read 3, iclass 29, count 2 2006.173.06:12:09.94#ibcon#read 3, iclass 29, count 2 2006.173.06:12:09.94#ibcon#about to read 4, iclass 29, count 2 2006.173.06:12:09.94#ibcon#read 4, iclass 29, count 2 2006.173.06:12:09.94#ibcon#about to read 5, iclass 29, count 2 2006.173.06:12:09.94#ibcon#read 5, iclass 29, count 2 2006.173.06:12:09.94#ibcon#about to read 6, iclass 29, count 2 2006.173.06:12:09.94#ibcon#read 6, iclass 29, count 2 2006.173.06:12:09.94#ibcon#end of sib2, iclass 29, count 2 2006.173.06:12:09.94#ibcon#*mode == 0, iclass 29, count 2 2006.173.06:12:09.94#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.06:12:09.94#ibcon#[25=AT03-05\r\n] 2006.173.06:12:09.94#ibcon#*before write, iclass 29, count 2 2006.173.06:12:09.94#ibcon#enter sib2, iclass 29, count 2 2006.173.06:12:09.94#ibcon#flushed, iclass 29, count 2 2006.173.06:12:09.94#ibcon#about to write, iclass 29, count 2 2006.173.06:12:09.94#ibcon#wrote, iclass 29, count 2 2006.173.06:12:09.94#ibcon#about to read 3, iclass 29, count 2 2006.173.06:12:09.97#ibcon#read 3, iclass 29, count 2 2006.173.06:12:09.97#ibcon#about to read 4, iclass 29, count 2 2006.173.06:12:09.97#ibcon#read 4, iclass 29, count 2 2006.173.06:12:09.97#ibcon#about to read 5, iclass 29, count 2 2006.173.06:12:09.97#ibcon#read 5, iclass 29, count 2 2006.173.06:12:09.97#ibcon#about to read 6, iclass 29, count 2 2006.173.06:12:09.97#ibcon#read 6, iclass 29, count 2 2006.173.06:12:09.97#ibcon#end of sib2, iclass 29, count 2 2006.173.06:12:09.97#ibcon#*after write, iclass 29, count 2 2006.173.06:12:09.97#ibcon#*before return 0, iclass 29, count 2 2006.173.06:12:09.97#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.06:12:09.97#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.06:12:09.97#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.06:12:09.97#ibcon#ireg 7 cls_cnt 0 2006.173.06:12:09.97#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.06:12:10.09#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.06:12:10.09#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.06:12:10.09#ibcon#enter wrdev, iclass 29, count 0 2006.173.06:12:10.09#ibcon#first serial, iclass 29, count 0 2006.173.06:12:10.09#ibcon#enter sib2, iclass 29, count 0 2006.173.06:12:10.09#ibcon#flushed, iclass 29, count 0 2006.173.06:12:10.09#ibcon#about to write, iclass 29, count 0 2006.173.06:12:10.09#ibcon#wrote, iclass 29, count 0 2006.173.06:12:10.09#ibcon#about to read 3, iclass 29, count 0 2006.173.06:12:10.11#ibcon#read 3, iclass 29, count 0 2006.173.06:12:10.11#ibcon#about to read 4, iclass 29, count 0 2006.173.06:12:10.11#ibcon#read 4, iclass 29, count 0 2006.173.06:12:10.11#ibcon#about to read 5, iclass 29, count 0 2006.173.06:12:10.11#ibcon#read 5, iclass 29, count 0 2006.173.06:12:10.11#ibcon#about to read 6, iclass 29, count 0 2006.173.06:12:10.11#ibcon#read 6, iclass 29, count 0 2006.173.06:12:10.11#ibcon#end of sib2, iclass 29, count 0 2006.173.06:12:10.11#ibcon#*mode == 0, iclass 29, count 0 2006.173.06:12:10.11#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.06:12:10.11#ibcon#[25=USB\r\n] 2006.173.06:12:10.11#ibcon#*before write, iclass 29, count 0 2006.173.06:12:10.11#ibcon#enter sib2, iclass 29, count 0 2006.173.06:12:10.11#ibcon#flushed, iclass 29, count 0 2006.173.06:12:10.11#ibcon#about to write, iclass 29, count 0 2006.173.06:12:10.11#ibcon#wrote, iclass 29, count 0 2006.173.06:12:10.11#ibcon#about to read 3, iclass 29, count 0 2006.173.06:12:10.14#ibcon#read 3, iclass 29, count 0 2006.173.06:12:10.14#ibcon#about to read 4, iclass 29, count 0 2006.173.06:12:10.14#ibcon#read 4, iclass 29, count 0 2006.173.06:12:10.14#ibcon#about to read 5, iclass 29, count 0 2006.173.06:12:10.14#ibcon#read 5, iclass 29, count 0 2006.173.06:12:10.14#ibcon#about to read 6, iclass 29, count 0 2006.173.06:12:10.14#ibcon#read 6, iclass 29, count 0 2006.173.06:12:10.14#ibcon#end of sib2, iclass 29, count 0 2006.173.06:12:10.14#ibcon#*after write, iclass 29, count 0 2006.173.06:12:10.14#ibcon#*before return 0, iclass 29, count 0 2006.173.06:12:10.14#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.06:12:10.14#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.06:12:10.14#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.06:12:10.14#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.06:12:10.14$vck44/valo=4,624.99 2006.173.06:12:10.14#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.06:12:10.14#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.06:12:10.14#ibcon#ireg 17 cls_cnt 0 2006.173.06:12:10.14#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.06:12:10.14#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.06:12:10.14#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.06:12:10.14#ibcon#enter wrdev, iclass 31, count 0 2006.173.06:12:10.14#ibcon#first serial, iclass 31, count 0 2006.173.06:12:10.14#ibcon#enter sib2, iclass 31, count 0 2006.173.06:12:10.14#ibcon#flushed, iclass 31, count 0 2006.173.06:12:10.14#ibcon#about to write, iclass 31, count 0 2006.173.06:12:10.14#ibcon#wrote, iclass 31, count 0 2006.173.06:12:10.14#ibcon#about to read 3, iclass 31, count 0 2006.173.06:12:10.16#ibcon#read 3, iclass 31, count 0 2006.173.06:12:10.16#ibcon#about to read 4, iclass 31, count 0 2006.173.06:12:10.16#ibcon#read 4, iclass 31, count 0 2006.173.06:12:10.16#ibcon#about to read 5, iclass 31, count 0 2006.173.06:12:10.16#ibcon#read 5, iclass 31, count 0 2006.173.06:12:10.16#ibcon#about to read 6, iclass 31, count 0 2006.173.06:12:10.16#ibcon#read 6, iclass 31, count 0 2006.173.06:12:10.16#ibcon#end of sib2, iclass 31, count 0 2006.173.06:12:10.16#ibcon#*mode == 0, iclass 31, count 0 2006.173.06:12:10.16#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.06:12:10.16#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.06:12:10.16#ibcon#*before write, iclass 31, count 0 2006.173.06:12:10.16#ibcon#enter sib2, iclass 31, count 0 2006.173.06:12:10.16#ibcon#flushed, iclass 31, count 0 2006.173.06:12:10.16#ibcon#about to write, iclass 31, count 0 2006.173.06:12:10.16#ibcon#wrote, iclass 31, count 0 2006.173.06:12:10.16#ibcon#about to read 3, iclass 31, count 0 2006.173.06:12:10.20#ibcon#read 3, iclass 31, count 0 2006.173.06:12:10.20#ibcon#about to read 4, iclass 31, count 0 2006.173.06:12:10.20#ibcon#read 4, iclass 31, count 0 2006.173.06:12:10.20#ibcon#about to read 5, iclass 31, count 0 2006.173.06:12:10.20#ibcon#read 5, iclass 31, count 0 2006.173.06:12:10.20#ibcon#about to read 6, iclass 31, count 0 2006.173.06:12:10.20#ibcon#read 6, iclass 31, count 0 2006.173.06:12:10.20#ibcon#end of sib2, iclass 31, count 0 2006.173.06:12:10.20#ibcon#*after write, iclass 31, count 0 2006.173.06:12:10.20#ibcon#*before return 0, iclass 31, count 0 2006.173.06:12:10.20#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.06:12:10.20#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.06:12:10.20#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.06:12:10.20#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.06:12:10.20$vck44/va=4,6 2006.173.06:12:10.20#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.173.06:12:10.20#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.173.06:12:10.20#ibcon#ireg 11 cls_cnt 2 2006.173.06:12:10.20#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.06:12:10.26#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.06:12:10.26#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.06:12:10.26#ibcon#enter wrdev, iclass 33, count 2 2006.173.06:12:10.26#ibcon#first serial, iclass 33, count 2 2006.173.06:12:10.26#ibcon#enter sib2, iclass 33, count 2 2006.173.06:12:10.26#ibcon#flushed, iclass 33, count 2 2006.173.06:12:10.26#ibcon#about to write, iclass 33, count 2 2006.173.06:12:10.26#ibcon#wrote, iclass 33, count 2 2006.173.06:12:10.26#ibcon#about to read 3, iclass 33, count 2 2006.173.06:12:10.28#ibcon#read 3, iclass 33, count 2 2006.173.06:12:10.28#ibcon#about to read 4, iclass 33, count 2 2006.173.06:12:10.28#ibcon#read 4, iclass 33, count 2 2006.173.06:12:10.28#ibcon#about to read 5, iclass 33, count 2 2006.173.06:12:10.28#ibcon#read 5, iclass 33, count 2 2006.173.06:12:10.28#ibcon#about to read 6, iclass 33, count 2 2006.173.06:12:10.28#ibcon#read 6, iclass 33, count 2 2006.173.06:12:10.28#ibcon#end of sib2, iclass 33, count 2 2006.173.06:12:10.28#ibcon#*mode == 0, iclass 33, count 2 2006.173.06:12:10.28#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.173.06:12:10.28#ibcon#[25=AT04-06\r\n] 2006.173.06:12:10.28#ibcon#*before write, iclass 33, count 2 2006.173.06:12:10.28#ibcon#enter sib2, iclass 33, count 2 2006.173.06:12:10.28#ibcon#flushed, iclass 33, count 2 2006.173.06:12:10.28#ibcon#about to write, iclass 33, count 2 2006.173.06:12:10.28#ibcon#wrote, iclass 33, count 2 2006.173.06:12:10.28#ibcon#about to read 3, iclass 33, count 2 2006.173.06:12:10.31#ibcon#read 3, iclass 33, count 2 2006.173.06:12:10.31#ibcon#about to read 4, iclass 33, count 2 2006.173.06:12:10.31#ibcon#read 4, iclass 33, count 2 2006.173.06:12:10.31#ibcon#about to read 5, iclass 33, count 2 2006.173.06:12:10.31#ibcon#read 5, iclass 33, count 2 2006.173.06:12:10.31#ibcon#about to read 6, iclass 33, count 2 2006.173.06:12:10.31#ibcon#read 6, iclass 33, count 2 2006.173.06:12:10.31#ibcon#end of sib2, iclass 33, count 2 2006.173.06:12:10.31#ibcon#*after write, iclass 33, count 2 2006.173.06:12:10.31#ibcon#*before return 0, iclass 33, count 2 2006.173.06:12:10.31#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.06:12:10.31#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.173.06:12:10.31#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.173.06:12:10.31#ibcon#ireg 7 cls_cnt 0 2006.173.06:12:10.31#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.06:12:10.43#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.06:12:10.43#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.06:12:10.43#ibcon#enter wrdev, iclass 33, count 0 2006.173.06:12:10.43#ibcon#first serial, iclass 33, count 0 2006.173.06:12:10.43#ibcon#enter sib2, iclass 33, count 0 2006.173.06:12:10.43#ibcon#flushed, iclass 33, count 0 2006.173.06:12:10.43#ibcon#about to write, iclass 33, count 0 2006.173.06:12:10.43#ibcon#wrote, iclass 33, count 0 2006.173.06:12:10.43#ibcon#about to read 3, iclass 33, count 0 2006.173.06:12:10.45#ibcon#read 3, iclass 33, count 0 2006.173.06:12:10.45#ibcon#about to read 4, iclass 33, count 0 2006.173.06:12:10.45#ibcon#read 4, iclass 33, count 0 2006.173.06:12:10.45#ibcon#about to read 5, iclass 33, count 0 2006.173.06:12:10.45#ibcon#read 5, iclass 33, count 0 2006.173.06:12:10.45#ibcon#about to read 6, iclass 33, count 0 2006.173.06:12:10.45#ibcon#read 6, iclass 33, count 0 2006.173.06:12:10.45#ibcon#end of sib2, iclass 33, count 0 2006.173.06:12:10.45#ibcon#*mode == 0, iclass 33, count 0 2006.173.06:12:10.45#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.06:12:10.45#ibcon#[25=USB\r\n] 2006.173.06:12:10.45#ibcon#*before write, iclass 33, count 0 2006.173.06:12:10.45#ibcon#enter sib2, iclass 33, count 0 2006.173.06:12:10.45#ibcon#flushed, iclass 33, count 0 2006.173.06:12:10.45#ibcon#about to write, iclass 33, count 0 2006.173.06:12:10.45#ibcon#wrote, iclass 33, count 0 2006.173.06:12:10.45#ibcon#about to read 3, iclass 33, count 0 2006.173.06:12:10.48#ibcon#read 3, iclass 33, count 0 2006.173.06:12:10.48#ibcon#about to read 4, iclass 33, count 0 2006.173.06:12:10.48#ibcon#read 4, iclass 33, count 0 2006.173.06:12:10.48#ibcon#about to read 5, iclass 33, count 0 2006.173.06:12:10.48#ibcon#read 5, iclass 33, count 0 2006.173.06:12:10.48#ibcon#about to read 6, iclass 33, count 0 2006.173.06:12:10.48#ibcon#read 6, iclass 33, count 0 2006.173.06:12:10.48#ibcon#end of sib2, iclass 33, count 0 2006.173.06:12:10.48#ibcon#*after write, iclass 33, count 0 2006.173.06:12:10.48#ibcon#*before return 0, iclass 33, count 0 2006.173.06:12:10.48#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.06:12:10.48#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.173.06:12:10.48#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.06:12:10.48#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.06:12:10.48$vck44/valo=5,734.99 2006.173.06:12:10.48#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.06:12:10.48#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.06:12:10.48#ibcon#ireg 17 cls_cnt 0 2006.173.06:12:10.48#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.06:12:10.48#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.06:12:10.48#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.06:12:10.48#ibcon#enter wrdev, iclass 35, count 0 2006.173.06:12:10.48#ibcon#first serial, iclass 35, count 0 2006.173.06:12:10.48#ibcon#enter sib2, iclass 35, count 0 2006.173.06:12:10.48#ibcon#flushed, iclass 35, count 0 2006.173.06:12:10.48#ibcon#about to write, iclass 35, count 0 2006.173.06:12:10.48#ibcon#wrote, iclass 35, count 0 2006.173.06:12:10.48#ibcon#about to read 3, iclass 35, count 0 2006.173.06:12:10.50#ibcon#read 3, iclass 35, count 0 2006.173.06:12:10.50#ibcon#about to read 4, iclass 35, count 0 2006.173.06:12:10.50#ibcon#read 4, iclass 35, count 0 2006.173.06:12:10.50#ibcon#about to read 5, iclass 35, count 0 2006.173.06:12:10.50#ibcon#read 5, iclass 35, count 0 2006.173.06:12:10.50#ibcon#about to read 6, iclass 35, count 0 2006.173.06:12:10.50#ibcon#read 6, iclass 35, count 0 2006.173.06:12:10.50#ibcon#end of sib2, iclass 35, count 0 2006.173.06:12:10.50#ibcon#*mode == 0, iclass 35, count 0 2006.173.06:12:10.50#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.06:12:10.50#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.06:12:10.50#ibcon#*before write, iclass 35, count 0 2006.173.06:12:10.50#ibcon#enter sib2, iclass 35, count 0 2006.173.06:12:10.50#ibcon#flushed, iclass 35, count 0 2006.173.06:12:10.50#ibcon#about to write, iclass 35, count 0 2006.173.06:12:10.50#ibcon#wrote, iclass 35, count 0 2006.173.06:12:10.50#ibcon#about to read 3, iclass 35, count 0 2006.173.06:12:10.54#ibcon#read 3, iclass 35, count 0 2006.173.06:12:10.54#ibcon#about to read 4, iclass 35, count 0 2006.173.06:12:10.54#ibcon#read 4, iclass 35, count 0 2006.173.06:12:10.54#ibcon#about to read 5, iclass 35, count 0 2006.173.06:12:10.54#ibcon#read 5, iclass 35, count 0 2006.173.06:12:10.54#ibcon#about to read 6, iclass 35, count 0 2006.173.06:12:10.54#ibcon#read 6, iclass 35, count 0 2006.173.06:12:10.54#ibcon#end of sib2, iclass 35, count 0 2006.173.06:12:10.54#ibcon#*after write, iclass 35, count 0 2006.173.06:12:10.54#ibcon#*before return 0, iclass 35, count 0 2006.173.06:12:10.54#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.06:12:10.54#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.06:12:10.54#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.06:12:10.54#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.06:12:10.54$vck44/va=5,4 2006.173.06:12:10.54#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.173.06:12:10.54#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.173.06:12:10.54#ibcon#ireg 11 cls_cnt 2 2006.173.06:12:10.54#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.06:12:10.60#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.06:12:10.60#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.06:12:10.60#ibcon#enter wrdev, iclass 37, count 2 2006.173.06:12:10.60#ibcon#first serial, iclass 37, count 2 2006.173.06:12:10.60#ibcon#enter sib2, iclass 37, count 2 2006.173.06:12:10.60#ibcon#flushed, iclass 37, count 2 2006.173.06:12:10.60#ibcon#about to write, iclass 37, count 2 2006.173.06:12:10.60#ibcon#wrote, iclass 37, count 2 2006.173.06:12:10.60#ibcon#about to read 3, iclass 37, count 2 2006.173.06:12:10.62#ibcon#read 3, iclass 37, count 2 2006.173.06:12:10.62#ibcon#about to read 4, iclass 37, count 2 2006.173.06:12:10.62#ibcon#read 4, iclass 37, count 2 2006.173.06:12:10.62#ibcon#about to read 5, iclass 37, count 2 2006.173.06:12:10.62#ibcon#read 5, iclass 37, count 2 2006.173.06:12:10.62#ibcon#about to read 6, iclass 37, count 2 2006.173.06:12:10.62#ibcon#read 6, iclass 37, count 2 2006.173.06:12:10.62#ibcon#end of sib2, iclass 37, count 2 2006.173.06:12:10.62#ibcon#*mode == 0, iclass 37, count 2 2006.173.06:12:10.62#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.173.06:12:10.62#ibcon#[25=AT05-04\r\n] 2006.173.06:12:10.62#ibcon#*before write, iclass 37, count 2 2006.173.06:12:10.62#ibcon#enter sib2, iclass 37, count 2 2006.173.06:12:10.62#ibcon#flushed, iclass 37, count 2 2006.173.06:12:10.62#ibcon#about to write, iclass 37, count 2 2006.173.06:12:10.62#ibcon#wrote, iclass 37, count 2 2006.173.06:12:10.62#ibcon#about to read 3, iclass 37, count 2 2006.173.06:12:10.65#ibcon#read 3, iclass 37, count 2 2006.173.06:12:10.65#ibcon#about to read 4, iclass 37, count 2 2006.173.06:12:10.65#ibcon#read 4, iclass 37, count 2 2006.173.06:12:10.65#ibcon#about to read 5, iclass 37, count 2 2006.173.06:12:10.65#ibcon#read 5, iclass 37, count 2 2006.173.06:12:10.65#ibcon#about to read 6, iclass 37, count 2 2006.173.06:12:10.65#ibcon#read 6, iclass 37, count 2 2006.173.06:12:10.65#ibcon#end of sib2, iclass 37, count 2 2006.173.06:12:10.65#ibcon#*after write, iclass 37, count 2 2006.173.06:12:10.65#ibcon#*before return 0, iclass 37, count 2 2006.173.06:12:10.65#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.06:12:10.65#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.173.06:12:10.65#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.173.06:12:10.65#ibcon#ireg 7 cls_cnt 0 2006.173.06:12:10.65#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.06:12:10.77#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.06:12:10.77#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.06:12:10.77#ibcon#enter wrdev, iclass 37, count 0 2006.173.06:12:10.77#ibcon#first serial, iclass 37, count 0 2006.173.06:12:10.77#ibcon#enter sib2, iclass 37, count 0 2006.173.06:12:10.77#ibcon#flushed, iclass 37, count 0 2006.173.06:12:10.77#ibcon#about to write, iclass 37, count 0 2006.173.06:12:10.77#ibcon#wrote, iclass 37, count 0 2006.173.06:12:10.77#ibcon#about to read 3, iclass 37, count 0 2006.173.06:12:10.79#ibcon#read 3, iclass 37, count 0 2006.173.06:12:10.79#ibcon#about to read 4, iclass 37, count 0 2006.173.06:12:10.79#ibcon#read 4, iclass 37, count 0 2006.173.06:12:10.79#ibcon#about to read 5, iclass 37, count 0 2006.173.06:12:10.79#ibcon#read 5, iclass 37, count 0 2006.173.06:12:10.79#ibcon#about to read 6, iclass 37, count 0 2006.173.06:12:10.79#ibcon#read 6, iclass 37, count 0 2006.173.06:12:10.79#ibcon#end of sib2, iclass 37, count 0 2006.173.06:12:10.79#ibcon#*mode == 0, iclass 37, count 0 2006.173.06:12:10.79#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.06:12:10.79#ibcon#[25=USB\r\n] 2006.173.06:12:10.79#ibcon#*before write, iclass 37, count 0 2006.173.06:12:10.79#ibcon#enter sib2, iclass 37, count 0 2006.173.06:12:10.79#ibcon#flushed, iclass 37, count 0 2006.173.06:12:10.79#ibcon#about to write, iclass 37, count 0 2006.173.06:12:10.79#ibcon#wrote, iclass 37, count 0 2006.173.06:12:10.79#ibcon#about to read 3, iclass 37, count 0 2006.173.06:12:10.82#ibcon#read 3, iclass 37, count 0 2006.173.06:12:10.82#ibcon#about to read 4, iclass 37, count 0 2006.173.06:12:10.82#ibcon#read 4, iclass 37, count 0 2006.173.06:12:10.82#ibcon#about to read 5, iclass 37, count 0 2006.173.06:12:10.82#ibcon#read 5, iclass 37, count 0 2006.173.06:12:10.82#ibcon#about to read 6, iclass 37, count 0 2006.173.06:12:10.82#ibcon#read 6, iclass 37, count 0 2006.173.06:12:10.82#ibcon#end of sib2, iclass 37, count 0 2006.173.06:12:10.82#ibcon#*after write, iclass 37, count 0 2006.173.06:12:10.82#ibcon#*before return 0, iclass 37, count 0 2006.173.06:12:10.82#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.06:12:10.82#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.173.06:12:10.82#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.06:12:10.82#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.06:12:10.82$vck44/valo=6,814.99 2006.173.06:12:10.82#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.06:12:10.82#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.06:12:10.82#ibcon#ireg 17 cls_cnt 0 2006.173.06:12:10.82#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.06:12:10.82#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.06:12:10.82#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.06:12:10.82#ibcon#enter wrdev, iclass 39, count 0 2006.173.06:12:10.82#ibcon#first serial, iclass 39, count 0 2006.173.06:12:10.82#ibcon#enter sib2, iclass 39, count 0 2006.173.06:12:10.82#ibcon#flushed, iclass 39, count 0 2006.173.06:12:10.82#ibcon#about to write, iclass 39, count 0 2006.173.06:12:10.82#ibcon#wrote, iclass 39, count 0 2006.173.06:12:10.82#ibcon#about to read 3, iclass 39, count 0 2006.173.06:12:10.84#ibcon#read 3, iclass 39, count 0 2006.173.06:12:10.84#ibcon#about to read 4, iclass 39, count 0 2006.173.06:12:10.84#ibcon#read 4, iclass 39, count 0 2006.173.06:12:10.84#ibcon#about to read 5, iclass 39, count 0 2006.173.06:12:10.84#ibcon#read 5, iclass 39, count 0 2006.173.06:12:10.84#ibcon#about to read 6, iclass 39, count 0 2006.173.06:12:10.84#ibcon#read 6, iclass 39, count 0 2006.173.06:12:10.84#ibcon#end of sib2, iclass 39, count 0 2006.173.06:12:10.84#ibcon#*mode == 0, iclass 39, count 0 2006.173.06:12:10.84#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.06:12:10.84#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.06:12:10.84#ibcon#*before write, iclass 39, count 0 2006.173.06:12:10.84#ibcon#enter sib2, iclass 39, count 0 2006.173.06:12:10.84#ibcon#flushed, iclass 39, count 0 2006.173.06:12:10.84#ibcon#about to write, iclass 39, count 0 2006.173.06:12:10.84#ibcon#wrote, iclass 39, count 0 2006.173.06:12:10.84#ibcon#about to read 3, iclass 39, count 0 2006.173.06:12:10.88#ibcon#read 3, iclass 39, count 0 2006.173.06:12:10.88#ibcon#about to read 4, iclass 39, count 0 2006.173.06:12:10.88#ibcon#read 4, iclass 39, count 0 2006.173.06:12:10.88#ibcon#about to read 5, iclass 39, count 0 2006.173.06:12:10.88#ibcon#read 5, iclass 39, count 0 2006.173.06:12:10.88#ibcon#about to read 6, iclass 39, count 0 2006.173.06:12:10.88#ibcon#read 6, iclass 39, count 0 2006.173.06:12:10.88#ibcon#end of sib2, iclass 39, count 0 2006.173.06:12:10.88#ibcon#*after write, iclass 39, count 0 2006.173.06:12:10.88#ibcon#*before return 0, iclass 39, count 0 2006.173.06:12:10.88#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.06:12:10.88#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.06:12:10.88#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.06:12:10.88#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.06:12:10.88$vck44/va=6,3 2006.173.06:12:10.88#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.06:12:10.88#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.06:12:10.88#ibcon#ireg 11 cls_cnt 2 2006.173.06:12:10.88#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.06:12:10.94#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.06:12:10.94#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.06:12:10.94#ibcon#enter wrdev, iclass 3, count 2 2006.173.06:12:10.94#ibcon#first serial, iclass 3, count 2 2006.173.06:12:10.94#ibcon#enter sib2, iclass 3, count 2 2006.173.06:12:10.94#ibcon#flushed, iclass 3, count 2 2006.173.06:12:10.94#ibcon#about to write, iclass 3, count 2 2006.173.06:12:10.94#ibcon#wrote, iclass 3, count 2 2006.173.06:12:10.94#ibcon#about to read 3, iclass 3, count 2 2006.173.06:12:10.96#ibcon#read 3, iclass 3, count 2 2006.173.06:12:10.96#ibcon#about to read 4, iclass 3, count 2 2006.173.06:12:10.96#ibcon#read 4, iclass 3, count 2 2006.173.06:12:10.96#ibcon#about to read 5, iclass 3, count 2 2006.173.06:12:10.96#ibcon#read 5, iclass 3, count 2 2006.173.06:12:10.96#ibcon#about to read 6, iclass 3, count 2 2006.173.06:12:10.96#ibcon#read 6, iclass 3, count 2 2006.173.06:12:10.96#ibcon#end of sib2, iclass 3, count 2 2006.173.06:12:10.96#ibcon#*mode == 0, iclass 3, count 2 2006.173.06:12:10.96#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.06:12:10.96#ibcon#[25=AT06-03\r\n] 2006.173.06:12:10.96#ibcon#*before write, iclass 3, count 2 2006.173.06:12:10.96#ibcon#enter sib2, iclass 3, count 2 2006.173.06:12:10.96#ibcon#flushed, iclass 3, count 2 2006.173.06:12:10.96#ibcon#about to write, iclass 3, count 2 2006.173.06:12:10.96#ibcon#wrote, iclass 3, count 2 2006.173.06:12:10.96#ibcon#about to read 3, iclass 3, count 2 2006.173.06:12:10.99#ibcon#read 3, iclass 3, count 2 2006.173.06:12:10.99#ibcon#about to read 4, iclass 3, count 2 2006.173.06:12:10.99#ibcon#read 4, iclass 3, count 2 2006.173.06:12:10.99#ibcon#about to read 5, iclass 3, count 2 2006.173.06:12:10.99#ibcon#read 5, iclass 3, count 2 2006.173.06:12:10.99#ibcon#about to read 6, iclass 3, count 2 2006.173.06:12:10.99#ibcon#read 6, iclass 3, count 2 2006.173.06:12:10.99#ibcon#end of sib2, iclass 3, count 2 2006.173.06:12:10.99#ibcon#*after write, iclass 3, count 2 2006.173.06:12:10.99#ibcon#*before return 0, iclass 3, count 2 2006.173.06:12:10.99#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.06:12:10.99#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.06:12:10.99#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.06:12:10.99#ibcon#ireg 7 cls_cnt 0 2006.173.06:12:10.99#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.06:12:11.11#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.06:12:11.11#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.06:12:11.11#ibcon#enter wrdev, iclass 3, count 0 2006.173.06:12:11.11#ibcon#first serial, iclass 3, count 0 2006.173.06:12:11.11#ibcon#enter sib2, iclass 3, count 0 2006.173.06:12:11.11#ibcon#flushed, iclass 3, count 0 2006.173.06:12:11.11#ibcon#about to write, iclass 3, count 0 2006.173.06:12:11.11#ibcon#wrote, iclass 3, count 0 2006.173.06:12:11.11#ibcon#about to read 3, iclass 3, count 0 2006.173.06:12:11.13#ibcon#read 3, iclass 3, count 0 2006.173.06:12:11.13#ibcon#about to read 4, iclass 3, count 0 2006.173.06:12:11.13#ibcon#read 4, iclass 3, count 0 2006.173.06:12:11.13#ibcon#about to read 5, iclass 3, count 0 2006.173.06:12:11.13#ibcon#read 5, iclass 3, count 0 2006.173.06:12:11.13#ibcon#about to read 6, iclass 3, count 0 2006.173.06:12:11.13#ibcon#read 6, iclass 3, count 0 2006.173.06:12:11.13#ibcon#end of sib2, iclass 3, count 0 2006.173.06:12:11.13#ibcon#*mode == 0, iclass 3, count 0 2006.173.06:12:11.13#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.06:12:11.13#ibcon#[25=USB\r\n] 2006.173.06:12:11.13#ibcon#*before write, iclass 3, count 0 2006.173.06:12:11.13#ibcon#enter sib2, iclass 3, count 0 2006.173.06:12:11.13#ibcon#flushed, iclass 3, count 0 2006.173.06:12:11.13#ibcon#about to write, iclass 3, count 0 2006.173.06:12:11.13#ibcon#wrote, iclass 3, count 0 2006.173.06:12:11.13#ibcon#about to read 3, iclass 3, count 0 2006.173.06:12:11.16#ibcon#read 3, iclass 3, count 0 2006.173.06:12:11.16#ibcon#about to read 4, iclass 3, count 0 2006.173.06:12:11.16#ibcon#read 4, iclass 3, count 0 2006.173.06:12:11.16#ibcon#about to read 5, iclass 3, count 0 2006.173.06:12:11.16#ibcon#read 5, iclass 3, count 0 2006.173.06:12:11.16#ibcon#about to read 6, iclass 3, count 0 2006.173.06:12:11.16#ibcon#read 6, iclass 3, count 0 2006.173.06:12:11.16#ibcon#end of sib2, iclass 3, count 0 2006.173.06:12:11.16#ibcon#*after write, iclass 3, count 0 2006.173.06:12:11.16#ibcon#*before return 0, iclass 3, count 0 2006.173.06:12:11.16#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.06:12:11.16#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.06:12:11.16#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.06:12:11.16#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.06:12:11.16$vck44/valo=7,864.99 2006.173.06:12:11.16#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.06:12:11.16#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.06:12:11.16#ibcon#ireg 17 cls_cnt 0 2006.173.06:12:11.16#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.06:12:11.16#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.06:12:11.16#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.06:12:11.16#ibcon#enter wrdev, iclass 5, count 0 2006.173.06:12:11.16#ibcon#first serial, iclass 5, count 0 2006.173.06:12:11.16#ibcon#enter sib2, iclass 5, count 0 2006.173.06:12:11.16#ibcon#flushed, iclass 5, count 0 2006.173.06:12:11.16#ibcon#about to write, iclass 5, count 0 2006.173.06:12:11.16#ibcon#wrote, iclass 5, count 0 2006.173.06:12:11.16#ibcon#about to read 3, iclass 5, count 0 2006.173.06:12:11.18#ibcon#read 3, iclass 5, count 0 2006.173.06:12:11.18#ibcon#about to read 4, iclass 5, count 0 2006.173.06:12:11.18#ibcon#read 4, iclass 5, count 0 2006.173.06:12:11.18#ibcon#about to read 5, iclass 5, count 0 2006.173.06:12:11.18#ibcon#read 5, iclass 5, count 0 2006.173.06:12:11.18#ibcon#about to read 6, iclass 5, count 0 2006.173.06:12:11.18#ibcon#read 6, iclass 5, count 0 2006.173.06:12:11.18#ibcon#end of sib2, iclass 5, count 0 2006.173.06:12:11.18#ibcon#*mode == 0, iclass 5, count 0 2006.173.06:12:11.18#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.06:12:11.18#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.06:12:11.18#ibcon#*before write, iclass 5, count 0 2006.173.06:12:11.18#ibcon#enter sib2, iclass 5, count 0 2006.173.06:12:11.18#ibcon#flushed, iclass 5, count 0 2006.173.06:12:11.18#ibcon#about to write, iclass 5, count 0 2006.173.06:12:11.18#ibcon#wrote, iclass 5, count 0 2006.173.06:12:11.18#ibcon#about to read 3, iclass 5, count 0 2006.173.06:12:11.22#ibcon#read 3, iclass 5, count 0 2006.173.06:12:11.22#ibcon#about to read 4, iclass 5, count 0 2006.173.06:12:11.22#ibcon#read 4, iclass 5, count 0 2006.173.06:12:11.22#ibcon#about to read 5, iclass 5, count 0 2006.173.06:12:11.22#ibcon#read 5, iclass 5, count 0 2006.173.06:12:11.22#ibcon#about to read 6, iclass 5, count 0 2006.173.06:12:11.22#ibcon#read 6, iclass 5, count 0 2006.173.06:12:11.22#ibcon#end of sib2, iclass 5, count 0 2006.173.06:12:11.22#ibcon#*after write, iclass 5, count 0 2006.173.06:12:11.22#ibcon#*before return 0, iclass 5, count 0 2006.173.06:12:11.22#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.06:12:11.22#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.06:12:11.22#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.06:12:11.22#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.06:12:11.22$vck44/va=7,4 2006.173.06:12:11.22#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.173.06:12:11.22#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.173.06:12:11.22#ibcon#ireg 11 cls_cnt 2 2006.173.06:12:11.22#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.06:12:11.28#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.06:12:11.28#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.06:12:11.28#ibcon#enter wrdev, iclass 7, count 2 2006.173.06:12:11.28#ibcon#first serial, iclass 7, count 2 2006.173.06:12:11.28#ibcon#enter sib2, iclass 7, count 2 2006.173.06:12:11.28#ibcon#flushed, iclass 7, count 2 2006.173.06:12:11.28#ibcon#about to write, iclass 7, count 2 2006.173.06:12:11.28#ibcon#wrote, iclass 7, count 2 2006.173.06:12:11.28#ibcon#about to read 3, iclass 7, count 2 2006.173.06:12:11.30#ibcon#read 3, iclass 7, count 2 2006.173.06:12:11.30#ibcon#about to read 4, iclass 7, count 2 2006.173.06:12:11.30#ibcon#read 4, iclass 7, count 2 2006.173.06:12:11.30#ibcon#about to read 5, iclass 7, count 2 2006.173.06:12:11.30#ibcon#read 5, iclass 7, count 2 2006.173.06:12:11.30#ibcon#about to read 6, iclass 7, count 2 2006.173.06:12:11.30#ibcon#read 6, iclass 7, count 2 2006.173.06:12:11.30#ibcon#end of sib2, iclass 7, count 2 2006.173.06:12:11.30#ibcon#*mode == 0, iclass 7, count 2 2006.173.06:12:11.30#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.173.06:12:11.30#ibcon#[25=AT07-04\r\n] 2006.173.06:12:11.30#ibcon#*before write, iclass 7, count 2 2006.173.06:12:11.30#ibcon#enter sib2, iclass 7, count 2 2006.173.06:12:11.30#ibcon#flushed, iclass 7, count 2 2006.173.06:12:11.30#ibcon#about to write, iclass 7, count 2 2006.173.06:12:11.30#ibcon#wrote, iclass 7, count 2 2006.173.06:12:11.30#ibcon#about to read 3, iclass 7, count 2 2006.173.06:12:11.33#ibcon#read 3, iclass 7, count 2 2006.173.06:12:11.33#ibcon#about to read 4, iclass 7, count 2 2006.173.06:12:11.33#ibcon#read 4, iclass 7, count 2 2006.173.06:12:11.33#ibcon#about to read 5, iclass 7, count 2 2006.173.06:12:11.33#ibcon#read 5, iclass 7, count 2 2006.173.06:12:11.33#ibcon#about to read 6, iclass 7, count 2 2006.173.06:12:11.33#ibcon#read 6, iclass 7, count 2 2006.173.06:12:11.33#ibcon#end of sib2, iclass 7, count 2 2006.173.06:12:11.33#ibcon#*after write, iclass 7, count 2 2006.173.06:12:11.33#ibcon#*before return 0, iclass 7, count 2 2006.173.06:12:11.33#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.06:12:11.33#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.173.06:12:11.33#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.173.06:12:11.33#ibcon#ireg 7 cls_cnt 0 2006.173.06:12:11.33#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.06:12:11.45#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.06:12:11.45#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.06:12:11.45#ibcon#enter wrdev, iclass 7, count 0 2006.173.06:12:11.45#ibcon#first serial, iclass 7, count 0 2006.173.06:12:11.45#ibcon#enter sib2, iclass 7, count 0 2006.173.06:12:11.45#ibcon#flushed, iclass 7, count 0 2006.173.06:12:11.45#ibcon#about to write, iclass 7, count 0 2006.173.06:12:11.45#ibcon#wrote, iclass 7, count 0 2006.173.06:12:11.45#ibcon#about to read 3, iclass 7, count 0 2006.173.06:12:11.47#ibcon#read 3, iclass 7, count 0 2006.173.06:12:11.47#ibcon#about to read 4, iclass 7, count 0 2006.173.06:12:11.47#ibcon#read 4, iclass 7, count 0 2006.173.06:12:11.47#ibcon#about to read 5, iclass 7, count 0 2006.173.06:12:11.47#ibcon#read 5, iclass 7, count 0 2006.173.06:12:11.47#ibcon#about to read 6, iclass 7, count 0 2006.173.06:12:11.47#ibcon#read 6, iclass 7, count 0 2006.173.06:12:11.47#ibcon#end of sib2, iclass 7, count 0 2006.173.06:12:11.47#ibcon#*mode == 0, iclass 7, count 0 2006.173.06:12:11.47#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.06:12:11.47#ibcon#[25=USB\r\n] 2006.173.06:12:11.47#ibcon#*before write, iclass 7, count 0 2006.173.06:12:11.47#ibcon#enter sib2, iclass 7, count 0 2006.173.06:12:11.47#ibcon#flushed, iclass 7, count 0 2006.173.06:12:11.47#ibcon#about to write, iclass 7, count 0 2006.173.06:12:11.47#ibcon#wrote, iclass 7, count 0 2006.173.06:12:11.47#ibcon#about to read 3, iclass 7, count 0 2006.173.06:12:11.50#ibcon#read 3, iclass 7, count 0 2006.173.06:12:11.50#ibcon#about to read 4, iclass 7, count 0 2006.173.06:12:11.50#ibcon#read 4, iclass 7, count 0 2006.173.06:12:11.50#ibcon#about to read 5, iclass 7, count 0 2006.173.06:12:11.50#ibcon#read 5, iclass 7, count 0 2006.173.06:12:11.50#ibcon#about to read 6, iclass 7, count 0 2006.173.06:12:11.50#ibcon#read 6, iclass 7, count 0 2006.173.06:12:11.50#ibcon#end of sib2, iclass 7, count 0 2006.173.06:12:11.50#ibcon#*after write, iclass 7, count 0 2006.173.06:12:11.50#ibcon#*before return 0, iclass 7, count 0 2006.173.06:12:11.50#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.06:12:11.50#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.173.06:12:11.50#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.06:12:11.50#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.06:12:11.50$vck44/valo=8,884.99 2006.173.06:12:11.50#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.06:12:11.50#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.06:12:11.50#ibcon#ireg 17 cls_cnt 0 2006.173.06:12:11.50#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.06:12:11.50#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.06:12:11.50#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.06:12:11.50#ibcon#enter wrdev, iclass 11, count 0 2006.173.06:12:11.50#ibcon#first serial, iclass 11, count 0 2006.173.06:12:11.50#ibcon#enter sib2, iclass 11, count 0 2006.173.06:12:11.50#ibcon#flushed, iclass 11, count 0 2006.173.06:12:11.50#ibcon#about to write, iclass 11, count 0 2006.173.06:12:11.50#ibcon#wrote, iclass 11, count 0 2006.173.06:12:11.50#ibcon#about to read 3, iclass 11, count 0 2006.173.06:12:11.52#ibcon#read 3, iclass 11, count 0 2006.173.06:12:11.52#ibcon#about to read 4, iclass 11, count 0 2006.173.06:12:11.52#ibcon#read 4, iclass 11, count 0 2006.173.06:12:11.52#ibcon#about to read 5, iclass 11, count 0 2006.173.06:12:11.52#ibcon#read 5, iclass 11, count 0 2006.173.06:12:11.52#ibcon#about to read 6, iclass 11, count 0 2006.173.06:12:11.52#ibcon#read 6, iclass 11, count 0 2006.173.06:12:11.52#ibcon#end of sib2, iclass 11, count 0 2006.173.06:12:11.52#ibcon#*mode == 0, iclass 11, count 0 2006.173.06:12:11.52#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.06:12:11.52#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.06:12:11.52#ibcon#*before write, iclass 11, count 0 2006.173.06:12:11.52#ibcon#enter sib2, iclass 11, count 0 2006.173.06:12:11.52#ibcon#flushed, iclass 11, count 0 2006.173.06:12:11.52#ibcon#about to write, iclass 11, count 0 2006.173.06:12:11.52#ibcon#wrote, iclass 11, count 0 2006.173.06:12:11.52#ibcon#about to read 3, iclass 11, count 0 2006.173.06:12:11.56#ibcon#read 3, iclass 11, count 0 2006.173.06:12:11.56#ibcon#about to read 4, iclass 11, count 0 2006.173.06:12:11.56#ibcon#read 4, iclass 11, count 0 2006.173.06:12:11.56#ibcon#about to read 5, iclass 11, count 0 2006.173.06:12:11.56#ibcon#read 5, iclass 11, count 0 2006.173.06:12:11.56#ibcon#about to read 6, iclass 11, count 0 2006.173.06:12:11.56#ibcon#read 6, iclass 11, count 0 2006.173.06:12:11.56#ibcon#end of sib2, iclass 11, count 0 2006.173.06:12:11.56#ibcon#*after write, iclass 11, count 0 2006.173.06:12:11.56#ibcon#*before return 0, iclass 11, count 0 2006.173.06:12:11.56#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.06:12:11.56#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.06:12:11.56#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.06:12:11.56#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.06:12:11.56$vck44/va=8,4 2006.173.06:12:11.56#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.173.06:12:11.56#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.173.06:12:11.56#ibcon#ireg 11 cls_cnt 2 2006.173.06:12:11.56#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.06:12:11.62#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.06:12:11.62#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.06:12:11.62#ibcon#enter wrdev, iclass 13, count 2 2006.173.06:12:11.62#ibcon#first serial, iclass 13, count 2 2006.173.06:12:11.62#ibcon#enter sib2, iclass 13, count 2 2006.173.06:12:11.62#ibcon#flushed, iclass 13, count 2 2006.173.06:12:11.62#ibcon#about to write, iclass 13, count 2 2006.173.06:12:11.62#ibcon#wrote, iclass 13, count 2 2006.173.06:12:11.62#ibcon#about to read 3, iclass 13, count 2 2006.173.06:12:11.64#ibcon#read 3, iclass 13, count 2 2006.173.06:12:11.64#ibcon#about to read 4, iclass 13, count 2 2006.173.06:12:11.64#ibcon#read 4, iclass 13, count 2 2006.173.06:12:11.64#ibcon#about to read 5, iclass 13, count 2 2006.173.06:12:11.64#ibcon#read 5, iclass 13, count 2 2006.173.06:12:11.64#ibcon#about to read 6, iclass 13, count 2 2006.173.06:12:11.64#ibcon#read 6, iclass 13, count 2 2006.173.06:12:11.64#ibcon#end of sib2, iclass 13, count 2 2006.173.06:12:11.64#ibcon#*mode == 0, iclass 13, count 2 2006.173.06:12:11.64#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.173.06:12:11.64#ibcon#[25=AT08-04\r\n] 2006.173.06:12:11.64#ibcon#*before write, iclass 13, count 2 2006.173.06:12:11.64#ibcon#enter sib2, iclass 13, count 2 2006.173.06:12:11.64#ibcon#flushed, iclass 13, count 2 2006.173.06:12:11.64#ibcon#about to write, iclass 13, count 2 2006.173.06:12:11.64#ibcon#wrote, iclass 13, count 2 2006.173.06:12:11.64#ibcon#about to read 3, iclass 13, count 2 2006.173.06:12:11.67#ibcon#read 3, iclass 13, count 2 2006.173.06:12:11.67#ibcon#about to read 4, iclass 13, count 2 2006.173.06:12:11.67#ibcon#read 4, iclass 13, count 2 2006.173.06:12:11.67#ibcon#about to read 5, iclass 13, count 2 2006.173.06:12:11.67#ibcon#read 5, iclass 13, count 2 2006.173.06:12:11.67#ibcon#about to read 6, iclass 13, count 2 2006.173.06:12:11.67#ibcon#read 6, iclass 13, count 2 2006.173.06:12:11.67#ibcon#end of sib2, iclass 13, count 2 2006.173.06:12:11.67#ibcon#*after write, iclass 13, count 2 2006.173.06:12:11.67#ibcon#*before return 0, iclass 13, count 2 2006.173.06:12:11.67#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.06:12:11.67#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.173.06:12:11.67#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.173.06:12:11.67#ibcon#ireg 7 cls_cnt 0 2006.173.06:12:11.67#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.06:12:11.79#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.06:12:11.79#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.06:12:11.79#ibcon#enter wrdev, iclass 13, count 0 2006.173.06:12:11.79#ibcon#first serial, iclass 13, count 0 2006.173.06:12:11.79#ibcon#enter sib2, iclass 13, count 0 2006.173.06:12:11.79#ibcon#flushed, iclass 13, count 0 2006.173.06:12:11.79#ibcon#about to write, iclass 13, count 0 2006.173.06:12:11.79#ibcon#wrote, iclass 13, count 0 2006.173.06:12:11.79#ibcon#about to read 3, iclass 13, count 0 2006.173.06:12:11.81#ibcon#read 3, iclass 13, count 0 2006.173.06:12:11.81#ibcon#about to read 4, iclass 13, count 0 2006.173.06:12:11.81#ibcon#read 4, iclass 13, count 0 2006.173.06:12:11.81#ibcon#about to read 5, iclass 13, count 0 2006.173.06:12:11.81#ibcon#read 5, iclass 13, count 0 2006.173.06:12:11.81#ibcon#about to read 6, iclass 13, count 0 2006.173.06:12:11.81#ibcon#read 6, iclass 13, count 0 2006.173.06:12:11.81#ibcon#end of sib2, iclass 13, count 0 2006.173.06:12:11.81#ibcon#*mode == 0, iclass 13, count 0 2006.173.06:12:11.81#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.06:12:11.81#ibcon#[25=USB\r\n] 2006.173.06:12:11.81#ibcon#*before write, iclass 13, count 0 2006.173.06:12:11.81#ibcon#enter sib2, iclass 13, count 0 2006.173.06:12:11.81#ibcon#flushed, iclass 13, count 0 2006.173.06:12:11.81#ibcon#about to write, iclass 13, count 0 2006.173.06:12:11.81#ibcon#wrote, iclass 13, count 0 2006.173.06:12:11.81#ibcon#about to read 3, iclass 13, count 0 2006.173.06:12:11.84#ibcon#read 3, iclass 13, count 0 2006.173.06:12:11.84#ibcon#about to read 4, iclass 13, count 0 2006.173.06:12:11.84#ibcon#read 4, iclass 13, count 0 2006.173.06:12:11.84#ibcon#about to read 5, iclass 13, count 0 2006.173.06:12:11.84#ibcon#read 5, iclass 13, count 0 2006.173.06:12:11.84#ibcon#about to read 6, iclass 13, count 0 2006.173.06:12:11.84#ibcon#read 6, iclass 13, count 0 2006.173.06:12:11.84#ibcon#end of sib2, iclass 13, count 0 2006.173.06:12:11.84#ibcon#*after write, iclass 13, count 0 2006.173.06:12:11.84#ibcon#*before return 0, iclass 13, count 0 2006.173.06:12:11.84#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.06:12:11.84#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.173.06:12:11.84#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.06:12:11.84#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.06:12:11.84$vck44/vblo=1,629.99 2006.173.06:12:11.84#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.06:12:11.84#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.06:12:11.84#ibcon#ireg 17 cls_cnt 0 2006.173.06:12:11.84#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.06:12:11.84#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.06:12:11.84#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.06:12:11.84#ibcon#enter wrdev, iclass 15, count 0 2006.173.06:12:11.84#ibcon#first serial, iclass 15, count 0 2006.173.06:12:11.84#ibcon#enter sib2, iclass 15, count 0 2006.173.06:12:11.84#ibcon#flushed, iclass 15, count 0 2006.173.06:12:11.84#ibcon#about to write, iclass 15, count 0 2006.173.06:12:11.84#ibcon#wrote, iclass 15, count 0 2006.173.06:12:11.84#ibcon#about to read 3, iclass 15, count 0 2006.173.06:12:11.86#ibcon#read 3, iclass 15, count 0 2006.173.06:12:11.86#ibcon#about to read 4, iclass 15, count 0 2006.173.06:12:11.86#ibcon#read 4, iclass 15, count 0 2006.173.06:12:11.86#ibcon#about to read 5, iclass 15, count 0 2006.173.06:12:11.86#ibcon#read 5, iclass 15, count 0 2006.173.06:12:11.86#ibcon#about to read 6, iclass 15, count 0 2006.173.06:12:11.86#ibcon#read 6, iclass 15, count 0 2006.173.06:12:11.86#ibcon#end of sib2, iclass 15, count 0 2006.173.06:12:11.86#ibcon#*mode == 0, iclass 15, count 0 2006.173.06:12:11.86#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.06:12:11.86#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.06:12:11.86#ibcon#*before write, iclass 15, count 0 2006.173.06:12:11.86#ibcon#enter sib2, iclass 15, count 0 2006.173.06:12:11.86#ibcon#flushed, iclass 15, count 0 2006.173.06:12:11.86#ibcon#about to write, iclass 15, count 0 2006.173.06:12:11.86#ibcon#wrote, iclass 15, count 0 2006.173.06:12:11.86#ibcon#about to read 3, iclass 15, count 0 2006.173.06:12:11.90#ibcon#read 3, iclass 15, count 0 2006.173.06:12:11.90#ibcon#about to read 4, iclass 15, count 0 2006.173.06:12:11.90#ibcon#read 4, iclass 15, count 0 2006.173.06:12:11.90#ibcon#about to read 5, iclass 15, count 0 2006.173.06:12:11.90#ibcon#read 5, iclass 15, count 0 2006.173.06:12:11.90#ibcon#about to read 6, iclass 15, count 0 2006.173.06:12:11.90#ibcon#read 6, iclass 15, count 0 2006.173.06:12:11.90#ibcon#end of sib2, iclass 15, count 0 2006.173.06:12:11.90#ibcon#*after write, iclass 15, count 0 2006.173.06:12:11.90#ibcon#*before return 0, iclass 15, count 0 2006.173.06:12:11.90#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.06:12:11.90#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.06:12:11.90#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.06:12:11.90#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.06:12:11.90$vck44/vb=1,4 2006.173.06:12:11.90#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.06:12:11.90#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.06:12:11.90#ibcon#ireg 11 cls_cnt 2 2006.173.06:12:11.90#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.06:12:11.90#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.06:12:11.90#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.06:12:11.90#ibcon#enter wrdev, iclass 17, count 2 2006.173.06:12:11.90#ibcon#first serial, iclass 17, count 2 2006.173.06:12:11.90#ibcon#enter sib2, iclass 17, count 2 2006.173.06:12:11.90#ibcon#flushed, iclass 17, count 2 2006.173.06:12:11.90#ibcon#about to write, iclass 17, count 2 2006.173.06:12:11.90#ibcon#wrote, iclass 17, count 2 2006.173.06:12:11.90#ibcon#about to read 3, iclass 17, count 2 2006.173.06:12:11.92#ibcon#read 3, iclass 17, count 2 2006.173.06:12:11.92#ibcon#about to read 4, iclass 17, count 2 2006.173.06:12:11.92#ibcon#read 4, iclass 17, count 2 2006.173.06:12:11.92#ibcon#about to read 5, iclass 17, count 2 2006.173.06:12:11.92#ibcon#read 5, iclass 17, count 2 2006.173.06:12:11.92#ibcon#about to read 6, iclass 17, count 2 2006.173.06:12:11.92#ibcon#read 6, iclass 17, count 2 2006.173.06:12:11.92#ibcon#end of sib2, iclass 17, count 2 2006.173.06:12:11.92#ibcon#*mode == 0, iclass 17, count 2 2006.173.06:12:11.92#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.06:12:11.92#ibcon#[27=AT01-04\r\n] 2006.173.06:12:11.92#ibcon#*before write, iclass 17, count 2 2006.173.06:12:11.92#ibcon#enter sib2, iclass 17, count 2 2006.173.06:12:11.92#ibcon#flushed, iclass 17, count 2 2006.173.06:12:11.92#ibcon#about to write, iclass 17, count 2 2006.173.06:12:11.92#ibcon#wrote, iclass 17, count 2 2006.173.06:12:11.92#ibcon#about to read 3, iclass 17, count 2 2006.173.06:12:11.95#ibcon#read 3, iclass 17, count 2 2006.173.06:12:11.95#ibcon#about to read 4, iclass 17, count 2 2006.173.06:12:11.95#ibcon#read 4, iclass 17, count 2 2006.173.06:12:11.95#ibcon#about to read 5, iclass 17, count 2 2006.173.06:12:11.95#ibcon#read 5, iclass 17, count 2 2006.173.06:12:11.95#ibcon#about to read 6, iclass 17, count 2 2006.173.06:12:11.95#ibcon#read 6, iclass 17, count 2 2006.173.06:12:11.95#ibcon#end of sib2, iclass 17, count 2 2006.173.06:12:11.95#ibcon#*after write, iclass 17, count 2 2006.173.06:12:11.95#ibcon#*before return 0, iclass 17, count 2 2006.173.06:12:11.95#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.06:12:11.95#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.06:12:11.95#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.06:12:11.95#ibcon#ireg 7 cls_cnt 0 2006.173.06:12:11.95#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.06:12:12.07#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.06:12:12.07#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.06:12:12.07#ibcon#enter wrdev, iclass 17, count 0 2006.173.06:12:12.07#ibcon#first serial, iclass 17, count 0 2006.173.06:12:12.07#ibcon#enter sib2, iclass 17, count 0 2006.173.06:12:12.07#ibcon#flushed, iclass 17, count 0 2006.173.06:12:12.07#ibcon#about to write, iclass 17, count 0 2006.173.06:12:12.07#ibcon#wrote, iclass 17, count 0 2006.173.06:12:12.07#ibcon#about to read 3, iclass 17, count 0 2006.173.06:12:12.09#ibcon#read 3, iclass 17, count 0 2006.173.06:12:12.09#ibcon#about to read 4, iclass 17, count 0 2006.173.06:12:12.09#ibcon#read 4, iclass 17, count 0 2006.173.06:12:12.09#ibcon#about to read 5, iclass 17, count 0 2006.173.06:12:12.09#ibcon#read 5, iclass 17, count 0 2006.173.06:12:12.09#ibcon#about to read 6, iclass 17, count 0 2006.173.06:12:12.09#ibcon#read 6, iclass 17, count 0 2006.173.06:12:12.09#ibcon#end of sib2, iclass 17, count 0 2006.173.06:12:12.09#ibcon#*mode == 0, iclass 17, count 0 2006.173.06:12:12.09#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.06:12:12.09#ibcon#[27=USB\r\n] 2006.173.06:12:12.09#ibcon#*before write, iclass 17, count 0 2006.173.06:12:12.09#ibcon#enter sib2, iclass 17, count 0 2006.173.06:12:12.09#ibcon#flushed, iclass 17, count 0 2006.173.06:12:12.09#ibcon#about to write, iclass 17, count 0 2006.173.06:12:12.09#ibcon#wrote, iclass 17, count 0 2006.173.06:12:12.09#ibcon#about to read 3, iclass 17, count 0 2006.173.06:12:12.12#ibcon#read 3, iclass 17, count 0 2006.173.06:12:12.12#ibcon#about to read 4, iclass 17, count 0 2006.173.06:12:12.12#ibcon#read 4, iclass 17, count 0 2006.173.06:12:12.12#ibcon#about to read 5, iclass 17, count 0 2006.173.06:12:12.12#ibcon#read 5, iclass 17, count 0 2006.173.06:12:12.12#ibcon#about to read 6, iclass 17, count 0 2006.173.06:12:12.12#ibcon#read 6, iclass 17, count 0 2006.173.06:12:12.12#ibcon#end of sib2, iclass 17, count 0 2006.173.06:12:12.12#ibcon#*after write, iclass 17, count 0 2006.173.06:12:12.12#ibcon#*before return 0, iclass 17, count 0 2006.173.06:12:12.12#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.06:12:12.12#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.06:12:12.12#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.06:12:12.12#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.06:12:12.12$vck44/vblo=2,634.99 2006.173.06:12:12.12#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.06:12:12.12#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.06:12:12.12#ibcon#ireg 17 cls_cnt 0 2006.173.06:12:12.12#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.06:12:12.12#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.06:12:12.12#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.06:12:12.12#ibcon#enter wrdev, iclass 19, count 0 2006.173.06:12:12.12#ibcon#first serial, iclass 19, count 0 2006.173.06:12:12.12#ibcon#enter sib2, iclass 19, count 0 2006.173.06:12:12.12#ibcon#flushed, iclass 19, count 0 2006.173.06:12:12.12#ibcon#about to write, iclass 19, count 0 2006.173.06:12:12.12#ibcon#wrote, iclass 19, count 0 2006.173.06:12:12.12#ibcon#about to read 3, iclass 19, count 0 2006.173.06:12:12.14#ibcon#read 3, iclass 19, count 0 2006.173.06:12:12.14#ibcon#about to read 4, iclass 19, count 0 2006.173.06:12:12.14#ibcon#read 4, iclass 19, count 0 2006.173.06:12:12.14#ibcon#about to read 5, iclass 19, count 0 2006.173.06:12:12.14#ibcon#read 5, iclass 19, count 0 2006.173.06:12:12.14#ibcon#about to read 6, iclass 19, count 0 2006.173.06:12:12.14#ibcon#read 6, iclass 19, count 0 2006.173.06:12:12.14#ibcon#end of sib2, iclass 19, count 0 2006.173.06:12:12.14#ibcon#*mode == 0, iclass 19, count 0 2006.173.06:12:12.14#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.06:12:12.14#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.06:12:12.14#ibcon#*before write, iclass 19, count 0 2006.173.06:12:12.14#ibcon#enter sib2, iclass 19, count 0 2006.173.06:12:12.14#ibcon#flushed, iclass 19, count 0 2006.173.06:12:12.14#ibcon#about to write, iclass 19, count 0 2006.173.06:12:12.14#ibcon#wrote, iclass 19, count 0 2006.173.06:12:12.14#ibcon#about to read 3, iclass 19, count 0 2006.173.06:12:12.18#ibcon#read 3, iclass 19, count 0 2006.173.06:12:12.18#ibcon#about to read 4, iclass 19, count 0 2006.173.06:12:12.18#ibcon#read 4, iclass 19, count 0 2006.173.06:12:12.18#ibcon#about to read 5, iclass 19, count 0 2006.173.06:12:12.18#ibcon#read 5, iclass 19, count 0 2006.173.06:12:12.18#ibcon#about to read 6, iclass 19, count 0 2006.173.06:12:12.18#ibcon#read 6, iclass 19, count 0 2006.173.06:12:12.18#ibcon#end of sib2, iclass 19, count 0 2006.173.06:12:12.18#ibcon#*after write, iclass 19, count 0 2006.173.06:12:12.18#ibcon#*before return 0, iclass 19, count 0 2006.173.06:12:12.18#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.06:12:12.18#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.06:12:12.18#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.06:12:12.18#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.06:12:12.18$vck44/vb=2,4 2006.173.06:12:12.18#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.06:12:12.18#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.06:12:12.18#ibcon#ireg 11 cls_cnt 2 2006.173.06:12:12.18#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.06:12:12.24#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.06:12:12.24#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.06:12:12.24#ibcon#enter wrdev, iclass 21, count 2 2006.173.06:12:12.24#ibcon#first serial, iclass 21, count 2 2006.173.06:12:12.24#ibcon#enter sib2, iclass 21, count 2 2006.173.06:12:12.24#ibcon#flushed, iclass 21, count 2 2006.173.06:12:12.24#ibcon#about to write, iclass 21, count 2 2006.173.06:12:12.24#ibcon#wrote, iclass 21, count 2 2006.173.06:12:12.24#ibcon#about to read 3, iclass 21, count 2 2006.173.06:12:12.26#ibcon#read 3, iclass 21, count 2 2006.173.06:12:12.26#ibcon#about to read 4, iclass 21, count 2 2006.173.06:12:12.26#ibcon#read 4, iclass 21, count 2 2006.173.06:12:12.26#ibcon#about to read 5, iclass 21, count 2 2006.173.06:12:12.26#ibcon#read 5, iclass 21, count 2 2006.173.06:12:12.26#ibcon#about to read 6, iclass 21, count 2 2006.173.06:12:12.26#ibcon#read 6, iclass 21, count 2 2006.173.06:12:12.26#ibcon#end of sib2, iclass 21, count 2 2006.173.06:12:12.26#ibcon#*mode == 0, iclass 21, count 2 2006.173.06:12:12.26#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.06:12:12.26#ibcon#[27=AT02-04\r\n] 2006.173.06:12:12.26#ibcon#*before write, iclass 21, count 2 2006.173.06:12:12.26#ibcon#enter sib2, iclass 21, count 2 2006.173.06:12:12.26#ibcon#flushed, iclass 21, count 2 2006.173.06:12:12.26#ibcon#about to write, iclass 21, count 2 2006.173.06:12:12.26#ibcon#wrote, iclass 21, count 2 2006.173.06:12:12.26#ibcon#about to read 3, iclass 21, count 2 2006.173.06:12:12.29#ibcon#read 3, iclass 21, count 2 2006.173.06:12:12.29#ibcon#about to read 4, iclass 21, count 2 2006.173.06:12:12.29#ibcon#read 4, iclass 21, count 2 2006.173.06:12:12.29#ibcon#about to read 5, iclass 21, count 2 2006.173.06:12:12.29#ibcon#read 5, iclass 21, count 2 2006.173.06:12:12.29#ibcon#about to read 6, iclass 21, count 2 2006.173.06:12:12.29#ibcon#read 6, iclass 21, count 2 2006.173.06:12:12.29#ibcon#end of sib2, iclass 21, count 2 2006.173.06:12:12.29#ibcon#*after write, iclass 21, count 2 2006.173.06:12:12.29#ibcon#*before return 0, iclass 21, count 2 2006.173.06:12:12.29#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.06:12:12.29#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.06:12:12.29#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.06:12:12.29#ibcon#ireg 7 cls_cnt 0 2006.173.06:12:12.29#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.06:12:12.41#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.06:12:12.41#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.06:12:12.41#ibcon#enter wrdev, iclass 21, count 0 2006.173.06:12:12.41#ibcon#first serial, iclass 21, count 0 2006.173.06:12:12.41#ibcon#enter sib2, iclass 21, count 0 2006.173.06:12:12.41#ibcon#flushed, iclass 21, count 0 2006.173.06:12:12.41#ibcon#about to write, iclass 21, count 0 2006.173.06:12:12.41#ibcon#wrote, iclass 21, count 0 2006.173.06:12:12.41#ibcon#about to read 3, iclass 21, count 0 2006.173.06:12:12.43#ibcon#read 3, iclass 21, count 0 2006.173.06:12:12.43#ibcon#about to read 4, iclass 21, count 0 2006.173.06:12:12.43#ibcon#read 4, iclass 21, count 0 2006.173.06:12:12.43#ibcon#about to read 5, iclass 21, count 0 2006.173.06:12:12.43#ibcon#read 5, iclass 21, count 0 2006.173.06:12:12.43#ibcon#about to read 6, iclass 21, count 0 2006.173.06:12:12.43#ibcon#read 6, iclass 21, count 0 2006.173.06:12:12.43#ibcon#end of sib2, iclass 21, count 0 2006.173.06:12:12.43#ibcon#*mode == 0, iclass 21, count 0 2006.173.06:12:12.43#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.06:12:12.43#ibcon#[27=USB\r\n] 2006.173.06:12:12.43#ibcon#*before write, iclass 21, count 0 2006.173.06:12:12.43#ibcon#enter sib2, iclass 21, count 0 2006.173.06:12:12.43#ibcon#flushed, iclass 21, count 0 2006.173.06:12:12.43#ibcon#about to write, iclass 21, count 0 2006.173.06:12:12.43#ibcon#wrote, iclass 21, count 0 2006.173.06:12:12.43#ibcon#about to read 3, iclass 21, count 0 2006.173.06:12:12.46#ibcon#read 3, iclass 21, count 0 2006.173.06:12:12.46#ibcon#about to read 4, iclass 21, count 0 2006.173.06:12:12.46#ibcon#read 4, iclass 21, count 0 2006.173.06:12:12.46#ibcon#about to read 5, iclass 21, count 0 2006.173.06:12:12.46#ibcon#read 5, iclass 21, count 0 2006.173.06:12:12.46#ibcon#about to read 6, iclass 21, count 0 2006.173.06:12:12.46#ibcon#read 6, iclass 21, count 0 2006.173.06:12:12.46#ibcon#end of sib2, iclass 21, count 0 2006.173.06:12:12.46#ibcon#*after write, iclass 21, count 0 2006.173.06:12:12.46#ibcon#*before return 0, iclass 21, count 0 2006.173.06:12:12.46#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.06:12:12.46#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.06:12:12.46#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.06:12:12.46#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.06:12:12.46$vck44/vblo=3,649.99 2006.173.06:12:12.46#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.06:12:12.46#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.06:12:12.46#ibcon#ireg 17 cls_cnt 0 2006.173.06:12:12.46#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.06:12:12.46#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.06:12:12.46#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.06:12:12.46#ibcon#enter wrdev, iclass 23, count 0 2006.173.06:12:12.46#ibcon#first serial, iclass 23, count 0 2006.173.06:12:12.46#ibcon#enter sib2, iclass 23, count 0 2006.173.06:12:12.46#ibcon#flushed, iclass 23, count 0 2006.173.06:12:12.46#ibcon#about to write, iclass 23, count 0 2006.173.06:12:12.46#ibcon#wrote, iclass 23, count 0 2006.173.06:12:12.46#ibcon#about to read 3, iclass 23, count 0 2006.173.06:12:12.48#ibcon#read 3, iclass 23, count 0 2006.173.06:12:12.48#ibcon#about to read 4, iclass 23, count 0 2006.173.06:12:12.48#ibcon#read 4, iclass 23, count 0 2006.173.06:12:12.48#ibcon#about to read 5, iclass 23, count 0 2006.173.06:12:12.48#ibcon#read 5, iclass 23, count 0 2006.173.06:12:12.48#ibcon#about to read 6, iclass 23, count 0 2006.173.06:12:12.48#ibcon#read 6, iclass 23, count 0 2006.173.06:12:12.48#ibcon#end of sib2, iclass 23, count 0 2006.173.06:12:12.48#ibcon#*mode == 0, iclass 23, count 0 2006.173.06:12:12.48#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.06:12:12.48#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.06:12:12.48#ibcon#*before write, iclass 23, count 0 2006.173.06:12:12.48#ibcon#enter sib2, iclass 23, count 0 2006.173.06:12:12.48#ibcon#flushed, iclass 23, count 0 2006.173.06:12:12.48#ibcon#about to write, iclass 23, count 0 2006.173.06:12:12.48#ibcon#wrote, iclass 23, count 0 2006.173.06:12:12.48#ibcon#about to read 3, iclass 23, count 0 2006.173.06:12:12.52#ibcon#read 3, iclass 23, count 0 2006.173.06:12:12.52#ibcon#about to read 4, iclass 23, count 0 2006.173.06:12:12.52#ibcon#read 4, iclass 23, count 0 2006.173.06:12:12.52#ibcon#about to read 5, iclass 23, count 0 2006.173.06:12:12.52#ibcon#read 5, iclass 23, count 0 2006.173.06:12:12.52#ibcon#about to read 6, iclass 23, count 0 2006.173.06:12:12.52#ibcon#read 6, iclass 23, count 0 2006.173.06:12:12.52#ibcon#end of sib2, iclass 23, count 0 2006.173.06:12:12.52#ibcon#*after write, iclass 23, count 0 2006.173.06:12:12.52#ibcon#*before return 0, iclass 23, count 0 2006.173.06:12:12.52#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.06:12:12.52#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.06:12:12.52#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.06:12:12.52#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.06:12:12.52$vck44/vb=3,4 2006.173.06:12:12.52#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.06:12:12.52#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.06:12:12.52#ibcon#ireg 11 cls_cnt 2 2006.173.06:12:12.52#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.06:12:12.58#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.06:12:12.58#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.06:12:12.58#ibcon#enter wrdev, iclass 25, count 2 2006.173.06:12:12.58#ibcon#first serial, iclass 25, count 2 2006.173.06:12:12.58#ibcon#enter sib2, iclass 25, count 2 2006.173.06:12:12.58#ibcon#flushed, iclass 25, count 2 2006.173.06:12:12.58#ibcon#about to write, iclass 25, count 2 2006.173.06:12:12.58#ibcon#wrote, iclass 25, count 2 2006.173.06:12:12.58#ibcon#about to read 3, iclass 25, count 2 2006.173.06:12:12.60#ibcon#read 3, iclass 25, count 2 2006.173.06:12:12.60#ibcon#about to read 4, iclass 25, count 2 2006.173.06:12:12.60#ibcon#read 4, iclass 25, count 2 2006.173.06:12:12.60#ibcon#about to read 5, iclass 25, count 2 2006.173.06:12:12.60#ibcon#read 5, iclass 25, count 2 2006.173.06:12:12.60#ibcon#about to read 6, iclass 25, count 2 2006.173.06:12:12.60#ibcon#read 6, iclass 25, count 2 2006.173.06:12:12.60#ibcon#end of sib2, iclass 25, count 2 2006.173.06:12:12.60#ibcon#*mode == 0, iclass 25, count 2 2006.173.06:12:12.60#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.06:12:12.60#ibcon#[27=AT03-04\r\n] 2006.173.06:12:12.60#ibcon#*before write, iclass 25, count 2 2006.173.06:12:12.60#ibcon#enter sib2, iclass 25, count 2 2006.173.06:12:12.60#ibcon#flushed, iclass 25, count 2 2006.173.06:12:12.60#ibcon#about to write, iclass 25, count 2 2006.173.06:12:12.60#ibcon#wrote, iclass 25, count 2 2006.173.06:12:12.60#ibcon#about to read 3, iclass 25, count 2 2006.173.06:12:12.63#ibcon#read 3, iclass 25, count 2 2006.173.06:12:12.63#ibcon#about to read 4, iclass 25, count 2 2006.173.06:12:12.63#ibcon#read 4, iclass 25, count 2 2006.173.06:12:12.63#ibcon#about to read 5, iclass 25, count 2 2006.173.06:12:12.63#ibcon#read 5, iclass 25, count 2 2006.173.06:12:12.63#ibcon#about to read 6, iclass 25, count 2 2006.173.06:12:12.63#ibcon#read 6, iclass 25, count 2 2006.173.06:12:12.63#ibcon#end of sib2, iclass 25, count 2 2006.173.06:12:12.63#ibcon#*after write, iclass 25, count 2 2006.173.06:12:12.63#ibcon#*before return 0, iclass 25, count 2 2006.173.06:12:12.63#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.06:12:12.63#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.06:12:12.63#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.06:12:12.63#ibcon#ireg 7 cls_cnt 0 2006.173.06:12:12.63#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.06:12:12.75#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.06:12:12.75#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.06:12:12.75#ibcon#enter wrdev, iclass 25, count 0 2006.173.06:12:12.75#ibcon#first serial, iclass 25, count 0 2006.173.06:12:12.75#ibcon#enter sib2, iclass 25, count 0 2006.173.06:12:12.75#ibcon#flushed, iclass 25, count 0 2006.173.06:12:12.75#ibcon#about to write, iclass 25, count 0 2006.173.06:12:12.75#ibcon#wrote, iclass 25, count 0 2006.173.06:12:12.75#ibcon#about to read 3, iclass 25, count 0 2006.173.06:12:12.77#ibcon#read 3, iclass 25, count 0 2006.173.06:12:12.77#ibcon#about to read 4, iclass 25, count 0 2006.173.06:12:12.77#ibcon#read 4, iclass 25, count 0 2006.173.06:12:12.77#ibcon#about to read 5, iclass 25, count 0 2006.173.06:12:12.77#ibcon#read 5, iclass 25, count 0 2006.173.06:12:12.77#ibcon#about to read 6, iclass 25, count 0 2006.173.06:12:12.77#ibcon#read 6, iclass 25, count 0 2006.173.06:12:12.77#ibcon#end of sib2, iclass 25, count 0 2006.173.06:12:12.77#ibcon#*mode == 0, iclass 25, count 0 2006.173.06:12:12.77#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.06:12:12.77#ibcon#[27=USB\r\n] 2006.173.06:12:12.77#ibcon#*before write, iclass 25, count 0 2006.173.06:12:12.77#ibcon#enter sib2, iclass 25, count 0 2006.173.06:12:12.77#ibcon#flushed, iclass 25, count 0 2006.173.06:12:12.77#ibcon#about to write, iclass 25, count 0 2006.173.06:12:12.77#ibcon#wrote, iclass 25, count 0 2006.173.06:12:12.77#ibcon#about to read 3, iclass 25, count 0 2006.173.06:12:12.80#ibcon#read 3, iclass 25, count 0 2006.173.06:12:12.80#ibcon#about to read 4, iclass 25, count 0 2006.173.06:12:12.80#ibcon#read 4, iclass 25, count 0 2006.173.06:12:12.80#ibcon#about to read 5, iclass 25, count 0 2006.173.06:12:12.80#ibcon#read 5, iclass 25, count 0 2006.173.06:12:12.80#ibcon#about to read 6, iclass 25, count 0 2006.173.06:12:12.80#ibcon#read 6, iclass 25, count 0 2006.173.06:12:12.80#ibcon#end of sib2, iclass 25, count 0 2006.173.06:12:12.80#ibcon#*after write, iclass 25, count 0 2006.173.06:12:12.80#ibcon#*before return 0, iclass 25, count 0 2006.173.06:12:12.80#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.06:12:12.80#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.06:12:12.80#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.06:12:12.80#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.06:12:12.80$vck44/vblo=4,679.99 2006.173.06:12:12.80#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.06:12:12.80#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.06:12:12.80#ibcon#ireg 17 cls_cnt 0 2006.173.06:12:12.80#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.06:12:12.80#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.06:12:12.80#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.06:12:12.80#ibcon#enter wrdev, iclass 27, count 0 2006.173.06:12:12.80#ibcon#first serial, iclass 27, count 0 2006.173.06:12:12.80#ibcon#enter sib2, iclass 27, count 0 2006.173.06:12:12.80#ibcon#flushed, iclass 27, count 0 2006.173.06:12:12.80#ibcon#about to write, iclass 27, count 0 2006.173.06:12:12.80#ibcon#wrote, iclass 27, count 0 2006.173.06:12:12.80#ibcon#about to read 3, iclass 27, count 0 2006.173.06:12:12.82#ibcon#read 3, iclass 27, count 0 2006.173.06:12:12.82#ibcon#about to read 4, iclass 27, count 0 2006.173.06:12:12.82#ibcon#read 4, iclass 27, count 0 2006.173.06:12:12.82#ibcon#about to read 5, iclass 27, count 0 2006.173.06:12:12.82#ibcon#read 5, iclass 27, count 0 2006.173.06:12:12.82#ibcon#about to read 6, iclass 27, count 0 2006.173.06:12:12.82#ibcon#read 6, iclass 27, count 0 2006.173.06:12:12.82#ibcon#end of sib2, iclass 27, count 0 2006.173.06:12:12.82#ibcon#*mode == 0, iclass 27, count 0 2006.173.06:12:12.82#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.06:12:12.82#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.06:12:12.82#ibcon#*before write, iclass 27, count 0 2006.173.06:12:12.82#ibcon#enter sib2, iclass 27, count 0 2006.173.06:12:12.82#ibcon#flushed, iclass 27, count 0 2006.173.06:12:12.82#ibcon#about to write, iclass 27, count 0 2006.173.06:12:12.82#ibcon#wrote, iclass 27, count 0 2006.173.06:12:12.82#ibcon#about to read 3, iclass 27, count 0 2006.173.06:12:12.86#ibcon#read 3, iclass 27, count 0 2006.173.06:12:12.86#ibcon#about to read 4, iclass 27, count 0 2006.173.06:12:12.86#ibcon#read 4, iclass 27, count 0 2006.173.06:12:12.86#ibcon#about to read 5, iclass 27, count 0 2006.173.06:12:12.86#ibcon#read 5, iclass 27, count 0 2006.173.06:12:12.86#ibcon#about to read 6, iclass 27, count 0 2006.173.06:12:12.86#ibcon#read 6, iclass 27, count 0 2006.173.06:12:12.86#ibcon#end of sib2, iclass 27, count 0 2006.173.06:12:12.86#ibcon#*after write, iclass 27, count 0 2006.173.06:12:12.86#ibcon#*before return 0, iclass 27, count 0 2006.173.06:12:12.86#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.06:12:12.86#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.06:12:12.86#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.06:12:12.86#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.06:12:12.86$vck44/vb=4,4 2006.173.06:12:12.86#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.06:12:12.86#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.06:12:12.86#ibcon#ireg 11 cls_cnt 2 2006.173.06:12:12.86#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.06:12:12.92#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.06:12:12.92#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.06:12:12.92#ibcon#enter wrdev, iclass 29, count 2 2006.173.06:12:12.92#ibcon#first serial, iclass 29, count 2 2006.173.06:12:12.92#ibcon#enter sib2, iclass 29, count 2 2006.173.06:12:12.92#ibcon#flushed, iclass 29, count 2 2006.173.06:12:12.92#ibcon#about to write, iclass 29, count 2 2006.173.06:12:12.92#ibcon#wrote, iclass 29, count 2 2006.173.06:12:12.92#ibcon#about to read 3, iclass 29, count 2 2006.173.06:12:12.94#ibcon#read 3, iclass 29, count 2 2006.173.06:12:12.94#ibcon#about to read 4, iclass 29, count 2 2006.173.06:12:12.94#ibcon#read 4, iclass 29, count 2 2006.173.06:12:12.94#ibcon#about to read 5, iclass 29, count 2 2006.173.06:12:12.94#ibcon#read 5, iclass 29, count 2 2006.173.06:12:12.94#ibcon#about to read 6, iclass 29, count 2 2006.173.06:12:12.94#ibcon#read 6, iclass 29, count 2 2006.173.06:12:12.94#ibcon#end of sib2, iclass 29, count 2 2006.173.06:12:12.94#ibcon#*mode == 0, iclass 29, count 2 2006.173.06:12:12.94#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.06:12:12.94#ibcon#[27=AT04-04\r\n] 2006.173.06:12:12.94#ibcon#*before write, iclass 29, count 2 2006.173.06:12:12.94#ibcon#enter sib2, iclass 29, count 2 2006.173.06:12:12.94#ibcon#flushed, iclass 29, count 2 2006.173.06:12:12.94#ibcon#about to write, iclass 29, count 2 2006.173.06:12:12.94#ibcon#wrote, iclass 29, count 2 2006.173.06:12:12.94#ibcon#about to read 3, iclass 29, count 2 2006.173.06:12:12.97#ibcon#read 3, iclass 29, count 2 2006.173.06:12:12.97#ibcon#about to read 4, iclass 29, count 2 2006.173.06:12:12.97#ibcon#read 4, iclass 29, count 2 2006.173.06:12:12.97#ibcon#about to read 5, iclass 29, count 2 2006.173.06:12:12.97#ibcon#read 5, iclass 29, count 2 2006.173.06:12:12.97#ibcon#about to read 6, iclass 29, count 2 2006.173.06:12:12.97#ibcon#read 6, iclass 29, count 2 2006.173.06:12:12.97#ibcon#end of sib2, iclass 29, count 2 2006.173.06:12:12.97#ibcon#*after write, iclass 29, count 2 2006.173.06:12:12.97#ibcon#*before return 0, iclass 29, count 2 2006.173.06:12:12.97#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.06:12:12.97#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.06:12:12.97#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.06:12:12.97#ibcon#ireg 7 cls_cnt 0 2006.173.06:12:12.97#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.06:12:13.09#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.06:12:13.09#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.06:12:13.09#ibcon#enter wrdev, iclass 29, count 0 2006.173.06:12:13.09#ibcon#first serial, iclass 29, count 0 2006.173.06:12:13.09#ibcon#enter sib2, iclass 29, count 0 2006.173.06:12:13.09#ibcon#flushed, iclass 29, count 0 2006.173.06:12:13.09#ibcon#about to write, iclass 29, count 0 2006.173.06:12:13.09#ibcon#wrote, iclass 29, count 0 2006.173.06:12:13.09#ibcon#about to read 3, iclass 29, count 0 2006.173.06:12:13.11#ibcon#read 3, iclass 29, count 0 2006.173.06:12:13.11#ibcon#about to read 4, iclass 29, count 0 2006.173.06:12:13.11#ibcon#read 4, iclass 29, count 0 2006.173.06:12:13.11#ibcon#about to read 5, iclass 29, count 0 2006.173.06:12:13.11#ibcon#read 5, iclass 29, count 0 2006.173.06:12:13.11#ibcon#about to read 6, iclass 29, count 0 2006.173.06:12:13.11#ibcon#read 6, iclass 29, count 0 2006.173.06:12:13.11#ibcon#end of sib2, iclass 29, count 0 2006.173.06:12:13.11#ibcon#*mode == 0, iclass 29, count 0 2006.173.06:12:13.11#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.06:12:13.11#ibcon#[27=USB\r\n] 2006.173.06:12:13.11#ibcon#*before write, iclass 29, count 0 2006.173.06:12:13.11#ibcon#enter sib2, iclass 29, count 0 2006.173.06:12:13.11#ibcon#flushed, iclass 29, count 0 2006.173.06:12:13.11#ibcon#about to write, iclass 29, count 0 2006.173.06:12:13.11#ibcon#wrote, iclass 29, count 0 2006.173.06:12:13.11#ibcon#about to read 3, iclass 29, count 0 2006.173.06:12:13.14#ibcon#read 3, iclass 29, count 0 2006.173.06:12:13.14#ibcon#about to read 4, iclass 29, count 0 2006.173.06:12:13.14#ibcon#read 4, iclass 29, count 0 2006.173.06:12:13.14#ibcon#about to read 5, iclass 29, count 0 2006.173.06:12:13.14#ibcon#read 5, iclass 29, count 0 2006.173.06:12:13.14#ibcon#about to read 6, iclass 29, count 0 2006.173.06:12:13.14#ibcon#read 6, iclass 29, count 0 2006.173.06:12:13.14#ibcon#end of sib2, iclass 29, count 0 2006.173.06:12:13.14#ibcon#*after write, iclass 29, count 0 2006.173.06:12:13.14#ibcon#*before return 0, iclass 29, count 0 2006.173.06:12:13.14#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.06:12:13.14#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.06:12:13.14#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.06:12:13.14#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.06:12:13.14$vck44/vblo=5,709.99 2006.173.06:12:13.14#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.06:12:13.14#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.06:12:13.14#ibcon#ireg 17 cls_cnt 0 2006.173.06:12:13.14#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.06:12:13.14#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.06:12:13.14#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.06:12:13.14#ibcon#enter wrdev, iclass 31, count 0 2006.173.06:12:13.14#ibcon#first serial, iclass 31, count 0 2006.173.06:12:13.14#ibcon#enter sib2, iclass 31, count 0 2006.173.06:12:13.14#ibcon#flushed, iclass 31, count 0 2006.173.06:12:13.14#ibcon#about to write, iclass 31, count 0 2006.173.06:12:13.14#ibcon#wrote, iclass 31, count 0 2006.173.06:12:13.14#ibcon#about to read 3, iclass 31, count 0 2006.173.06:12:13.16#ibcon#read 3, iclass 31, count 0 2006.173.06:12:13.16#ibcon#about to read 4, iclass 31, count 0 2006.173.06:12:13.16#ibcon#read 4, iclass 31, count 0 2006.173.06:12:13.16#ibcon#about to read 5, iclass 31, count 0 2006.173.06:12:13.16#ibcon#read 5, iclass 31, count 0 2006.173.06:12:13.16#ibcon#about to read 6, iclass 31, count 0 2006.173.06:12:13.16#ibcon#read 6, iclass 31, count 0 2006.173.06:12:13.16#ibcon#end of sib2, iclass 31, count 0 2006.173.06:12:13.16#ibcon#*mode == 0, iclass 31, count 0 2006.173.06:12:13.16#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.06:12:13.16#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.06:12:13.16#ibcon#*before write, iclass 31, count 0 2006.173.06:12:13.16#ibcon#enter sib2, iclass 31, count 0 2006.173.06:12:13.16#ibcon#flushed, iclass 31, count 0 2006.173.06:12:13.16#ibcon#about to write, iclass 31, count 0 2006.173.06:12:13.16#ibcon#wrote, iclass 31, count 0 2006.173.06:12:13.16#ibcon#about to read 3, iclass 31, count 0 2006.173.06:12:13.20#ibcon#read 3, iclass 31, count 0 2006.173.06:12:13.20#ibcon#about to read 4, iclass 31, count 0 2006.173.06:12:13.20#ibcon#read 4, iclass 31, count 0 2006.173.06:12:13.20#ibcon#about to read 5, iclass 31, count 0 2006.173.06:12:13.20#ibcon#read 5, iclass 31, count 0 2006.173.06:12:13.20#ibcon#about to read 6, iclass 31, count 0 2006.173.06:12:13.20#ibcon#read 6, iclass 31, count 0 2006.173.06:12:13.20#ibcon#end of sib2, iclass 31, count 0 2006.173.06:12:13.20#ibcon#*after write, iclass 31, count 0 2006.173.06:12:13.20#ibcon#*before return 0, iclass 31, count 0 2006.173.06:12:13.20#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.06:12:13.20#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.06:12:13.20#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.06:12:13.20#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.06:12:13.20$vck44/vb=5,4 2006.173.06:12:13.20#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.173.06:12:13.20#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.173.06:12:13.20#ibcon#ireg 11 cls_cnt 2 2006.173.06:12:13.20#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.06:12:13.26#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.06:12:13.26#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.06:12:13.26#ibcon#enter wrdev, iclass 33, count 2 2006.173.06:12:13.26#ibcon#first serial, iclass 33, count 2 2006.173.06:12:13.26#ibcon#enter sib2, iclass 33, count 2 2006.173.06:12:13.26#ibcon#flushed, iclass 33, count 2 2006.173.06:12:13.26#ibcon#about to write, iclass 33, count 2 2006.173.06:12:13.26#ibcon#wrote, iclass 33, count 2 2006.173.06:12:13.26#ibcon#about to read 3, iclass 33, count 2 2006.173.06:12:13.28#ibcon#read 3, iclass 33, count 2 2006.173.06:12:13.28#ibcon#about to read 4, iclass 33, count 2 2006.173.06:12:13.28#ibcon#read 4, iclass 33, count 2 2006.173.06:12:13.28#ibcon#about to read 5, iclass 33, count 2 2006.173.06:12:13.28#ibcon#read 5, iclass 33, count 2 2006.173.06:12:13.28#ibcon#about to read 6, iclass 33, count 2 2006.173.06:12:13.28#ibcon#read 6, iclass 33, count 2 2006.173.06:12:13.28#ibcon#end of sib2, iclass 33, count 2 2006.173.06:12:13.28#ibcon#*mode == 0, iclass 33, count 2 2006.173.06:12:13.28#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.173.06:12:13.28#ibcon#[27=AT05-04\r\n] 2006.173.06:12:13.28#ibcon#*before write, iclass 33, count 2 2006.173.06:12:13.28#ibcon#enter sib2, iclass 33, count 2 2006.173.06:12:13.28#ibcon#flushed, iclass 33, count 2 2006.173.06:12:13.28#ibcon#about to write, iclass 33, count 2 2006.173.06:12:13.28#ibcon#wrote, iclass 33, count 2 2006.173.06:12:13.28#ibcon#about to read 3, iclass 33, count 2 2006.173.06:12:13.31#ibcon#read 3, iclass 33, count 2 2006.173.06:12:13.31#ibcon#about to read 4, iclass 33, count 2 2006.173.06:12:13.31#ibcon#read 4, iclass 33, count 2 2006.173.06:12:13.31#ibcon#about to read 5, iclass 33, count 2 2006.173.06:12:13.31#ibcon#read 5, iclass 33, count 2 2006.173.06:12:13.31#ibcon#about to read 6, iclass 33, count 2 2006.173.06:12:13.31#ibcon#read 6, iclass 33, count 2 2006.173.06:12:13.31#ibcon#end of sib2, iclass 33, count 2 2006.173.06:12:13.31#ibcon#*after write, iclass 33, count 2 2006.173.06:12:13.31#ibcon#*before return 0, iclass 33, count 2 2006.173.06:12:13.31#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.06:12:13.31#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.173.06:12:13.31#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.173.06:12:13.31#ibcon#ireg 7 cls_cnt 0 2006.173.06:12:13.31#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.06:12:13.43#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.06:12:13.43#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.06:12:13.43#ibcon#enter wrdev, iclass 33, count 0 2006.173.06:12:13.43#ibcon#first serial, iclass 33, count 0 2006.173.06:12:13.43#ibcon#enter sib2, iclass 33, count 0 2006.173.06:12:13.43#ibcon#flushed, iclass 33, count 0 2006.173.06:12:13.43#ibcon#about to write, iclass 33, count 0 2006.173.06:12:13.43#ibcon#wrote, iclass 33, count 0 2006.173.06:12:13.43#ibcon#about to read 3, iclass 33, count 0 2006.173.06:12:13.45#ibcon#read 3, iclass 33, count 0 2006.173.06:12:13.45#ibcon#about to read 4, iclass 33, count 0 2006.173.06:12:13.45#ibcon#read 4, iclass 33, count 0 2006.173.06:12:13.45#ibcon#about to read 5, iclass 33, count 0 2006.173.06:12:13.45#ibcon#read 5, iclass 33, count 0 2006.173.06:12:13.45#ibcon#about to read 6, iclass 33, count 0 2006.173.06:12:13.45#ibcon#read 6, iclass 33, count 0 2006.173.06:12:13.45#ibcon#end of sib2, iclass 33, count 0 2006.173.06:12:13.45#ibcon#*mode == 0, iclass 33, count 0 2006.173.06:12:13.45#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.06:12:13.45#ibcon#[27=USB\r\n] 2006.173.06:12:13.45#ibcon#*before write, iclass 33, count 0 2006.173.06:12:13.45#ibcon#enter sib2, iclass 33, count 0 2006.173.06:12:13.45#ibcon#flushed, iclass 33, count 0 2006.173.06:12:13.45#ibcon#about to write, iclass 33, count 0 2006.173.06:12:13.45#ibcon#wrote, iclass 33, count 0 2006.173.06:12:13.45#ibcon#about to read 3, iclass 33, count 0 2006.173.06:12:13.48#ibcon#read 3, iclass 33, count 0 2006.173.06:12:13.48#ibcon#about to read 4, iclass 33, count 0 2006.173.06:12:13.48#ibcon#read 4, iclass 33, count 0 2006.173.06:12:13.48#ibcon#about to read 5, iclass 33, count 0 2006.173.06:12:13.48#ibcon#read 5, iclass 33, count 0 2006.173.06:12:13.48#ibcon#about to read 6, iclass 33, count 0 2006.173.06:12:13.48#ibcon#read 6, iclass 33, count 0 2006.173.06:12:13.48#ibcon#end of sib2, iclass 33, count 0 2006.173.06:12:13.48#ibcon#*after write, iclass 33, count 0 2006.173.06:12:13.48#ibcon#*before return 0, iclass 33, count 0 2006.173.06:12:13.48#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.06:12:13.48#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.173.06:12:13.48#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.06:12:13.48#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.06:12:13.48$vck44/vblo=6,719.99 2006.173.06:12:13.48#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.06:12:13.48#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.06:12:13.48#ibcon#ireg 17 cls_cnt 0 2006.173.06:12:13.48#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.06:12:13.48#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.06:12:13.48#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.06:12:13.48#ibcon#enter wrdev, iclass 35, count 0 2006.173.06:12:13.48#ibcon#first serial, iclass 35, count 0 2006.173.06:12:13.48#ibcon#enter sib2, iclass 35, count 0 2006.173.06:12:13.48#ibcon#flushed, iclass 35, count 0 2006.173.06:12:13.48#ibcon#about to write, iclass 35, count 0 2006.173.06:12:13.48#ibcon#wrote, iclass 35, count 0 2006.173.06:12:13.48#ibcon#about to read 3, iclass 35, count 0 2006.173.06:12:13.50#ibcon#read 3, iclass 35, count 0 2006.173.06:12:13.50#ibcon#about to read 4, iclass 35, count 0 2006.173.06:12:13.50#ibcon#read 4, iclass 35, count 0 2006.173.06:12:13.50#ibcon#about to read 5, iclass 35, count 0 2006.173.06:12:13.50#ibcon#read 5, iclass 35, count 0 2006.173.06:12:13.50#ibcon#about to read 6, iclass 35, count 0 2006.173.06:12:13.50#ibcon#read 6, iclass 35, count 0 2006.173.06:12:13.50#ibcon#end of sib2, iclass 35, count 0 2006.173.06:12:13.50#ibcon#*mode == 0, iclass 35, count 0 2006.173.06:12:13.50#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.06:12:13.50#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.06:12:13.50#ibcon#*before write, iclass 35, count 0 2006.173.06:12:13.50#ibcon#enter sib2, iclass 35, count 0 2006.173.06:12:13.50#ibcon#flushed, iclass 35, count 0 2006.173.06:12:13.50#ibcon#about to write, iclass 35, count 0 2006.173.06:12:13.50#ibcon#wrote, iclass 35, count 0 2006.173.06:12:13.50#ibcon#about to read 3, iclass 35, count 0 2006.173.06:12:13.54#ibcon#read 3, iclass 35, count 0 2006.173.06:12:13.54#ibcon#about to read 4, iclass 35, count 0 2006.173.06:12:13.54#ibcon#read 4, iclass 35, count 0 2006.173.06:12:13.54#ibcon#about to read 5, iclass 35, count 0 2006.173.06:12:13.54#ibcon#read 5, iclass 35, count 0 2006.173.06:12:13.54#ibcon#about to read 6, iclass 35, count 0 2006.173.06:12:13.54#ibcon#read 6, iclass 35, count 0 2006.173.06:12:13.54#ibcon#end of sib2, iclass 35, count 0 2006.173.06:12:13.54#ibcon#*after write, iclass 35, count 0 2006.173.06:12:13.54#ibcon#*before return 0, iclass 35, count 0 2006.173.06:12:13.54#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.06:12:13.54#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.06:12:13.54#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.06:12:13.54#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.06:12:13.54$vck44/vb=6,4 2006.173.06:12:13.54#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.173.06:12:13.54#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.173.06:12:13.54#ibcon#ireg 11 cls_cnt 2 2006.173.06:12:13.54#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.06:12:13.60#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.06:12:13.60#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.06:12:13.60#ibcon#enter wrdev, iclass 37, count 2 2006.173.06:12:13.60#ibcon#first serial, iclass 37, count 2 2006.173.06:12:13.60#ibcon#enter sib2, iclass 37, count 2 2006.173.06:12:13.60#ibcon#flushed, iclass 37, count 2 2006.173.06:12:13.60#ibcon#about to write, iclass 37, count 2 2006.173.06:12:13.60#ibcon#wrote, iclass 37, count 2 2006.173.06:12:13.60#ibcon#about to read 3, iclass 37, count 2 2006.173.06:12:13.62#ibcon#read 3, iclass 37, count 2 2006.173.06:12:13.62#ibcon#about to read 4, iclass 37, count 2 2006.173.06:12:13.62#ibcon#read 4, iclass 37, count 2 2006.173.06:12:13.62#ibcon#about to read 5, iclass 37, count 2 2006.173.06:12:13.62#ibcon#read 5, iclass 37, count 2 2006.173.06:12:13.62#ibcon#about to read 6, iclass 37, count 2 2006.173.06:12:13.62#ibcon#read 6, iclass 37, count 2 2006.173.06:12:13.62#ibcon#end of sib2, iclass 37, count 2 2006.173.06:12:13.62#ibcon#*mode == 0, iclass 37, count 2 2006.173.06:12:13.62#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.173.06:12:13.62#ibcon#[27=AT06-04\r\n] 2006.173.06:12:13.62#ibcon#*before write, iclass 37, count 2 2006.173.06:12:13.62#ibcon#enter sib2, iclass 37, count 2 2006.173.06:12:13.62#ibcon#flushed, iclass 37, count 2 2006.173.06:12:13.62#ibcon#about to write, iclass 37, count 2 2006.173.06:12:13.62#ibcon#wrote, iclass 37, count 2 2006.173.06:12:13.62#ibcon#about to read 3, iclass 37, count 2 2006.173.06:12:13.65#ibcon#read 3, iclass 37, count 2 2006.173.06:12:13.65#ibcon#about to read 4, iclass 37, count 2 2006.173.06:12:13.65#ibcon#read 4, iclass 37, count 2 2006.173.06:12:13.65#ibcon#about to read 5, iclass 37, count 2 2006.173.06:12:13.65#ibcon#read 5, iclass 37, count 2 2006.173.06:12:13.65#ibcon#about to read 6, iclass 37, count 2 2006.173.06:12:13.65#ibcon#read 6, iclass 37, count 2 2006.173.06:12:13.65#ibcon#end of sib2, iclass 37, count 2 2006.173.06:12:13.65#ibcon#*after write, iclass 37, count 2 2006.173.06:12:13.65#ibcon#*before return 0, iclass 37, count 2 2006.173.06:12:13.65#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.06:12:13.65#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.173.06:12:13.65#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.173.06:12:13.65#ibcon#ireg 7 cls_cnt 0 2006.173.06:12:13.65#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.06:12:13.77#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.06:12:13.77#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.06:12:13.77#ibcon#enter wrdev, iclass 37, count 0 2006.173.06:12:13.77#ibcon#first serial, iclass 37, count 0 2006.173.06:12:13.77#ibcon#enter sib2, iclass 37, count 0 2006.173.06:12:13.77#ibcon#flushed, iclass 37, count 0 2006.173.06:12:13.77#ibcon#about to write, iclass 37, count 0 2006.173.06:12:13.77#ibcon#wrote, iclass 37, count 0 2006.173.06:12:13.77#ibcon#about to read 3, iclass 37, count 0 2006.173.06:12:13.79#ibcon#read 3, iclass 37, count 0 2006.173.06:12:13.79#ibcon#about to read 4, iclass 37, count 0 2006.173.06:12:13.79#ibcon#read 4, iclass 37, count 0 2006.173.06:12:13.79#ibcon#about to read 5, iclass 37, count 0 2006.173.06:12:13.79#ibcon#read 5, iclass 37, count 0 2006.173.06:12:13.79#ibcon#about to read 6, iclass 37, count 0 2006.173.06:12:13.79#ibcon#read 6, iclass 37, count 0 2006.173.06:12:13.79#ibcon#end of sib2, iclass 37, count 0 2006.173.06:12:13.79#ibcon#*mode == 0, iclass 37, count 0 2006.173.06:12:13.79#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.06:12:13.79#ibcon#[27=USB\r\n] 2006.173.06:12:13.79#ibcon#*before write, iclass 37, count 0 2006.173.06:12:13.79#ibcon#enter sib2, iclass 37, count 0 2006.173.06:12:13.79#ibcon#flushed, iclass 37, count 0 2006.173.06:12:13.79#ibcon#about to write, iclass 37, count 0 2006.173.06:12:13.79#ibcon#wrote, iclass 37, count 0 2006.173.06:12:13.79#ibcon#about to read 3, iclass 37, count 0 2006.173.06:12:13.82#ibcon#read 3, iclass 37, count 0 2006.173.06:12:13.82#ibcon#about to read 4, iclass 37, count 0 2006.173.06:12:13.82#ibcon#read 4, iclass 37, count 0 2006.173.06:12:13.82#ibcon#about to read 5, iclass 37, count 0 2006.173.06:12:13.82#ibcon#read 5, iclass 37, count 0 2006.173.06:12:13.82#ibcon#about to read 6, iclass 37, count 0 2006.173.06:12:13.82#ibcon#read 6, iclass 37, count 0 2006.173.06:12:13.82#ibcon#end of sib2, iclass 37, count 0 2006.173.06:12:13.82#ibcon#*after write, iclass 37, count 0 2006.173.06:12:13.82#ibcon#*before return 0, iclass 37, count 0 2006.173.06:12:13.82#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.06:12:13.82#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.173.06:12:13.82#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.06:12:13.82#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.06:12:13.82$vck44/vblo=7,734.99 2006.173.06:12:13.82#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.06:12:13.82#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.06:12:13.82#ibcon#ireg 17 cls_cnt 0 2006.173.06:12:13.82#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.06:12:13.82#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.06:12:13.82#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.06:12:13.82#ibcon#enter wrdev, iclass 39, count 0 2006.173.06:12:13.82#ibcon#first serial, iclass 39, count 0 2006.173.06:12:13.82#ibcon#enter sib2, iclass 39, count 0 2006.173.06:12:13.82#ibcon#flushed, iclass 39, count 0 2006.173.06:12:13.82#ibcon#about to write, iclass 39, count 0 2006.173.06:12:13.82#ibcon#wrote, iclass 39, count 0 2006.173.06:12:13.82#ibcon#about to read 3, iclass 39, count 0 2006.173.06:12:13.84#ibcon#read 3, iclass 39, count 0 2006.173.06:12:13.84#ibcon#about to read 4, iclass 39, count 0 2006.173.06:12:13.84#ibcon#read 4, iclass 39, count 0 2006.173.06:12:13.84#ibcon#about to read 5, iclass 39, count 0 2006.173.06:12:13.84#ibcon#read 5, iclass 39, count 0 2006.173.06:12:13.84#ibcon#about to read 6, iclass 39, count 0 2006.173.06:12:13.84#ibcon#read 6, iclass 39, count 0 2006.173.06:12:13.84#ibcon#end of sib2, iclass 39, count 0 2006.173.06:12:13.84#ibcon#*mode == 0, iclass 39, count 0 2006.173.06:12:13.84#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.06:12:13.84#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.06:12:13.84#ibcon#*before write, iclass 39, count 0 2006.173.06:12:13.84#ibcon#enter sib2, iclass 39, count 0 2006.173.06:12:13.84#ibcon#flushed, iclass 39, count 0 2006.173.06:12:13.84#ibcon#about to write, iclass 39, count 0 2006.173.06:12:13.84#ibcon#wrote, iclass 39, count 0 2006.173.06:12:13.84#ibcon#about to read 3, iclass 39, count 0 2006.173.06:12:13.88#ibcon#read 3, iclass 39, count 0 2006.173.06:12:13.88#ibcon#about to read 4, iclass 39, count 0 2006.173.06:12:13.88#ibcon#read 4, iclass 39, count 0 2006.173.06:12:13.88#ibcon#about to read 5, iclass 39, count 0 2006.173.06:12:13.88#ibcon#read 5, iclass 39, count 0 2006.173.06:12:13.88#ibcon#about to read 6, iclass 39, count 0 2006.173.06:12:13.88#ibcon#read 6, iclass 39, count 0 2006.173.06:12:13.88#ibcon#end of sib2, iclass 39, count 0 2006.173.06:12:13.88#ibcon#*after write, iclass 39, count 0 2006.173.06:12:13.88#ibcon#*before return 0, iclass 39, count 0 2006.173.06:12:13.88#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.06:12:13.88#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.06:12:13.88#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.06:12:13.88#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.06:12:13.88$vck44/vb=7,4 2006.173.06:12:13.88#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.06:12:13.88#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.06:12:13.88#ibcon#ireg 11 cls_cnt 2 2006.173.06:12:13.88#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.06:12:13.94#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.06:12:13.94#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.06:12:13.94#ibcon#enter wrdev, iclass 3, count 2 2006.173.06:12:13.94#ibcon#first serial, iclass 3, count 2 2006.173.06:12:13.94#ibcon#enter sib2, iclass 3, count 2 2006.173.06:12:13.94#ibcon#flushed, iclass 3, count 2 2006.173.06:12:13.94#ibcon#about to write, iclass 3, count 2 2006.173.06:12:13.94#ibcon#wrote, iclass 3, count 2 2006.173.06:12:13.94#ibcon#about to read 3, iclass 3, count 2 2006.173.06:12:13.96#ibcon#read 3, iclass 3, count 2 2006.173.06:12:13.96#ibcon#about to read 4, iclass 3, count 2 2006.173.06:12:13.96#ibcon#read 4, iclass 3, count 2 2006.173.06:12:13.96#ibcon#about to read 5, iclass 3, count 2 2006.173.06:12:13.96#ibcon#read 5, iclass 3, count 2 2006.173.06:12:13.96#ibcon#about to read 6, iclass 3, count 2 2006.173.06:12:13.96#ibcon#read 6, iclass 3, count 2 2006.173.06:12:13.96#ibcon#end of sib2, iclass 3, count 2 2006.173.06:12:13.96#ibcon#*mode == 0, iclass 3, count 2 2006.173.06:12:13.96#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.06:12:13.96#ibcon#[27=AT07-04\r\n] 2006.173.06:12:13.96#ibcon#*before write, iclass 3, count 2 2006.173.06:12:13.96#ibcon#enter sib2, iclass 3, count 2 2006.173.06:12:13.96#ibcon#flushed, iclass 3, count 2 2006.173.06:12:13.96#ibcon#about to write, iclass 3, count 2 2006.173.06:12:13.96#ibcon#wrote, iclass 3, count 2 2006.173.06:12:13.96#ibcon#about to read 3, iclass 3, count 2 2006.173.06:12:13.99#ibcon#read 3, iclass 3, count 2 2006.173.06:12:13.99#ibcon#about to read 4, iclass 3, count 2 2006.173.06:12:13.99#ibcon#read 4, iclass 3, count 2 2006.173.06:12:13.99#ibcon#about to read 5, iclass 3, count 2 2006.173.06:12:13.99#ibcon#read 5, iclass 3, count 2 2006.173.06:12:13.99#ibcon#about to read 6, iclass 3, count 2 2006.173.06:12:13.99#ibcon#read 6, iclass 3, count 2 2006.173.06:12:13.99#ibcon#end of sib2, iclass 3, count 2 2006.173.06:12:13.99#ibcon#*after write, iclass 3, count 2 2006.173.06:12:13.99#ibcon#*before return 0, iclass 3, count 2 2006.173.06:12:13.99#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.06:12:13.99#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.06:12:13.99#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.06:12:13.99#ibcon#ireg 7 cls_cnt 0 2006.173.06:12:13.99#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.06:12:14.11#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.06:12:14.11#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.06:12:14.11#ibcon#enter wrdev, iclass 3, count 0 2006.173.06:12:14.11#ibcon#first serial, iclass 3, count 0 2006.173.06:12:14.11#ibcon#enter sib2, iclass 3, count 0 2006.173.06:12:14.11#ibcon#flushed, iclass 3, count 0 2006.173.06:12:14.11#ibcon#about to write, iclass 3, count 0 2006.173.06:12:14.11#ibcon#wrote, iclass 3, count 0 2006.173.06:12:14.11#ibcon#about to read 3, iclass 3, count 0 2006.173.06:12:14.13#ibcon#read 3, iclass 3, count 0 2006.173.06:12:14.13#ibcon#about to read 4, iclass 3, count 0 2006.173.06:12:14.13#ibcon#read 4, iclass 3, count 0 2006.173.06:12:14.13#ibcon#about to read 5, iclass 3, count 0 2006.173.06:12:14.13#ibcon#read 5, iclass 3, count 0 2006.173.06:12:14.13#ibcon#about to read 6, iclass 3, count 0 2006.173.06:12:14.13#ibcon#read 6, iclass 3, count 0 2006.173.06:12:14.13#ibcon#end of sib2, iclass 3, count 0 2006.173.06:12:14.13#ibcon#*mode == 0, iclass 3, count 0 2006.173.06:12:14.13#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.06:12:14.13#ibcon#[27=USB\r\n] 2006.173.06:12:14.13#ibcon#*before write, iclass 3, count 0 2006.173.06:12:14.13#ibcon#enter sib2, iclass 3, count 0 2006.173.06:12:14.13#ibcon#flushed, iclass 3, count 0 2006.173.06:12:14.13#ibcon#about to write, iclass 3, count 0 2006.173.06:12:14.13#ibcon#wrote, iclass 3, count 0 2006.173.06:12:14.13#ibcon#about to read 3, iclass 3, count 0 2006.173.06:12:14.16#ibcon#read 3, iclass 3, count 0 2006.173.06:12:14.16#ibcon#about to read 4, iclass 3, count 0 2006.173.06:12:14.16#ibcon#read 4, iclass 3, count 0 2006.173.06:12:14.16#ibcon#about to read 5, iclass 3, count 0 2006.173.06:12:14.16#ibcon#read 5, iclass 3, count 0 2006.173.06:12:14.16#ibcon#about to read 6, iclass 3, count 0 2006.173.06:12:14.16#ibcon#read 6, iclass 3, count 0 2006.173.06:12:14.16#ibcon#end of sib2, iclass 3, count 0 2006.173.06:12:14.16#ibcon#*after write, iclass 3, count 0 2006.173.06:12:14.16#ibcon#*before return 0, iclass 3, count 0 2006.173.06:12:14.16#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.06:12:14.16#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.06:12:14.16#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.06:12:14.16#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.06:12:14.16$vck44/vblo=8,744.99 2006.173.06:12:14.16#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.06:12:14.16#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.06:12:14.16#ibcon#ireg 17 cls_cnt 0 2006.173.06:12:14.16#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.06:12:14.16#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.06:12:14.16#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.06:12:14.16#ibcon#enter wrdev, iclass 5, count 0 2006.173.06:12:14.16#ibcon#first serial, iclass 5, count 0 2006.173.06:12:14.16#ibcon#enter sib2, iclass 5, count 0 2006.173.06:12:14.16#ibcon#flushed, iclass 5, count 0 2006.173.06:12:14.16#ibcon#about to write, iclass 5, count 0 2006.173.06:12:14.16#ibcon#wrote, iclass 5, count 0 2006.173.06:12:14.16#ibcon#about to read 3, iclass 5, count 0 2006.173.06:12:14.18#ibcon#read 3, iclass 5, count 0 2006.173.06:12:14.18#ibcon#about to read 4, iclass 5, count 0 2006.173.06:12:14.18#ibcon#read 4, iclass 5, count 0 2006.173.06:12:14.18#ibcon#about to read 5, iclass 5, count 0 2006.173.06:12:14.18#ibcon#read 5, iclass 5, count 0 2006.173.06:12:14.18#ibcon#about to read 6, iclass 5, count 0 2006.173.06:12:14.18#ibcon#read 6, iclass 5, count 0 2006.173.06:12:14.18#ibcon#end of sib2, iclass 5, count 0 2006.173.06:12:14.18#ibcon#*mode == 0, iclass 5, count 0 2006.173.06:12:14.18#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.06:12:14.18#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.06:12:14.18#ibcon#*before write, iclass 5, count 0 2006.173.06:12:14.18#ibcon#enter sib2, iclass 5, count 0 2006.173.06:12:14.18#ibcon#flushed, iclass 5, count 0 2006.173.06:12:14.18#ibcon#about to write, iclass 5, count 0 2006.173.06:12:14.18#ibcon#wrote, iclass 5, count 0 2006.173.06:12:14.18#ibcon#about to read 3, iclass 5, count 0 2006.173.06:12:14.22#ibcon#read 3, iclass 5, count 0 2006.173.06:12:14.22#ibcon#about to read 4, iclass 5, count 0 2006.173.06:12:14.22#ibcon#read 4, iclass 5, count 0 2006.173.06:12:14.22#ibcon#about to read 5, iclass 5, count 0 2006.173.06:12:14.22#ibcon#read 5, iclass 5, count 0 2006.173.06:12:14.22#ibcon#about to read 6, iclass 5, count 0 2006.173.06:12:14.22#ibcon#read 6, iclass 5, count 0 2006.173.06:12:14.22#ibcon#end of sib2, iclass 5, count 0 2006.173.06:12:14.22#ibcon#*after write, iclass 5, count 0 2006.173.06:12:14.22#ibcon#*before return 0, iclass 5, count 0 2006.173.06:12:14.22#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.06:12:14.22#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.06:12:14.22#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.06:12:14.22#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.06:12:14.22$vck44/vb=8,4 2006.173.06:12:14.22#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.173.06:12:14.22#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.173.06:12:14.22#ibcon#ireg 11 cls_cnt 2 2006.173.06:12:14.22#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.06:12:14.28#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.06:12:14.28#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.06:12:14.28#ibcon#enter wrdev, iclass 7, count 2 2006.173.06:12:14.28#ibcon#first serial, iclass 7, count 2 2006.173.06:12:14.28#ibcon#enter sib2, iclass 7, count 2 2006.173.06:12:14.28#ibcon#flushed, iclass 7, count 2 2006.173.06:12:14.28#ibcon#about to write, iclass 7, count 2 2006.173.06:12:14.28#ibcon#wrote, iclass 7, count 2 2006.173.06:12:14.28#ibcon#about to read 3, iclass 7, count 2 2006.173.06:12:14.30#ibcon#read 3, iclass 7, count 2 2006.173.06:12:14.30#ibcon#about to read 4, iclass 7, count 2 2006.173.06:12:14.30#ibcon#read 4, iclass 7, count 2 2006.173.06:12:14.30#ibcon#about to read 5, iclass 7, count 2 2006.173.06:12:14.30#ibcon#read 5, iclass 7, count 2 2006.173.06:12:14.30#ibcon#about to read 6, iclass 7, count 2 2006.173.06:12:14.30#ibcon#read 6, iclass 7, count 2 2006.173.06:12:14.30#ibcon#end of sib2, iclass 7, count 2 2006.173.06:12:14.30#ibcon#*mode == 0, iclass 7, count 2 2006.173.06:12:14.30#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.173.06:12:14.30#ibcon#[27=AT08-04\r\n] 2006.173.06:12:14.30#ibcon#*before write, iclass 7, count 2 2006.173.06:12:14.30#ibcon#enter sib2, iclass 7, count 2 2006.173.06:12:14.30#ibcon#flushed, iclass 7, count 2 2006.173.06:12:14.30#ibcon#about to write, iclass 7, count 2 2006.173.06:12:14.30#ibcon#wrote, iclass 7, count 2 2006.173.06:12:14.30#ibcon#about to read 3, iclass 7, count 2 2006.173.06:12:14.33#ibcon#read 3, iclass 7, count 2 2006.173.06:12:14.33#ibcon#about to read 4, iclass 7, count 2 2006.173.06:12:14.33#ibcon#read 4, iclass 7, count 2 2006.173.06:12:14.33#ibcon#about to read 5, iclass 7, count 2 2006.173.06:12:14.33#ibcon#read 5, iclass 7, count 2 2006.173.06:12:14.33#ibcon#about to read 6, iclass 7, count 2 2006.173.06:12:14.33#ibcon#read 6, iclass 7, count 2 2006.173.06:12:14.33#ibcon#end of sib2, iclass 7, count 2 2006.173.06:12:14.33#ibcon#*after write, iclass 7, count 2 2006.173.06:12:14.33#ibcon#*before return 0, iclass 7, count 2 2006.173.06:12:14.33#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.06:12:14.33#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.173.06:12:14.33#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.173.06:12:14.33#ibcon#ireg 7 cls_cnt 0 2006.173.06:12:14.33#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.06:12:14.45#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.06:12:14.45#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.06:12:14.45#ibcon#enter wrdev, iclass 7, count 0 2006.173.06:12:14.45#ibcon#first serial, iclass 7, count 0 2006.173.06:12:14.45#ibcon#enter sib2, iclass 7, count 0 2006.173.06:12:14.45#ibcon#flushed, iclass 7, count 0 2006.173.06:12:14.45#ibcon#about to write, iclass 7, count 0 2006.173.06:12:14.45#ibcon#wrote, iclass 7, count 0 2006.173.06:12:14.45#ibcon#about to read 3, iclass 7, count 0 2006.173.06:12:14.47#ibcon#read 3, iclass 7, count 0 2006.173.06:12:14.47#ibcon#about to read 4, iclass 7, count 0 2006.173.06:12:14.47#ibcon#read 4, iclass 7, count 0 2006.173.06:12:14.47#ibcon#about to read 5, iclass 7, count 0 2006.173.06:12:14.47#ibcon#read 5, iclass 7, count 0 2006.173.06:12:14.47#ibcon#about to read 6, iclass 7, count 0 2006.173.06:12:14.47#ibcon#read 6, iclass 7, count 0 2006.173.06:12:14.47#ibcon#end of sib2, iclass 7, count 0 2006.173.06:12:14.47#ibcon#*mode == 0, iclass 7, count 0 2006.173.06:12:14.47#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.06:12:14.47#ibcon#[27=USB\r\n] 2006.173.06:12:14.47#ibcon#*before write, iclass 7, count 0 2006.173.06:12:14.47#ibcon#enter sib2, iclass 7, count 0 2006.173.06:12:14.47#ibcon#flushed, iclass 7, count 0 2006.173.06:12:14.47#ibcon#about to write, iclass 7, count 0 2006.173.06:12:14.47#ibcon#wrote, iclass 7, count 0 2006.173.06:12:14.47#ibcon#about to read 3, iclass 7, count 0 2006.173.06:12:14.50#ibcon#read 3, iclass 7, count 0 2006.173.06:12:14.50#ibcon#about to read 4, iclass 7, count 0 2006.173.06:12:14.50#ibcon#read 4, iclass 7, count 0 2006.173.06:12:14.50#ibcon#about to read 5, iclass 7, count 0 2006.173.06:12:14.50#ibcon#read 5, iclass 7, count 0 2006.173.06:12:14.50#ibcon#about to read 6, iclass 7, count 0 2006.173.06:12:14.50#ibcon#read 6, iclass 7, count 0 2006.173.06:12:14.50#ibcon#end of sib2, iclass 7, count 0 2006.173.06:12:14.50#ibcon#*after write, iclass 7, count 0 2006.173.06:12:14.50#ibcon#*before return 0, iclass 7, count 0 2006.173.06:12:14.50#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.06:12:14.50#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.173.06:12:14.50#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.06:12:14.50#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.06:12:14.50$vck44/vabw=wide 2006.173.06:12:14.50#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.06:12:14.50#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.06:12:14.50#ibcon#ireg 8 cls_cnt 0 2006.173.06:12:14.50#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.06:12:14.50#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.06:12:14.50#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.06:12:14.50#ibcon#enter wrdev, iclass 11, count 0 2006.173.06:12:14.50#ibcon#first serial, iclass 11, count 0 2006.173.06:12:14.50#ibcon#enter sib2, iclass 11, count 0 2006.173.06:12:14.50#ibcon#flushed, iclass 11, count 0 2006.173.06:12:14.50#ibcon#about to write, iclass 11, count 0 2006.173.06:12:14.50#ibcon#wrote, iclass 11, count 0 2006.173.06:12:14.50#ibcon#about to read 3, iclass 11, count 0 2006.173.06:12:14.52#ibcon#read 3, iclass 11, count 0 2006.173.06:12:14.52#ibcon#about to read 4, iclass 11, count 0 2006.173.06:12:14.52#ibcon#read 4, iclass 11, count 0 2006.173.06:12:14.52#ibcon#about to read 5, iclass 11, count 0 2006.173.06:12:14.52#ibcon#read 5, iclass 11, count 0 2006.173.06:12:14.52#ibcon#about to read 6, iclass 11, count 0 2006.173.06:12:14.52#ibcon#read 6, iclass 11, count 0 2006.173.06:12:14.52#ibcon#end of sib2, iclass 11, count 0 2006.173.06:12:14.52#ibcon#*mode == 0, iclass 11, count 0 2006.173.06:12:14.52#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.06:12:14.52#ibcon#[25=BW32\r\n] 2006.173.06:12:14.52#ibcon#*before write, iclass 11, count 0 2006.173.06:12:14.52#ibcon#enter sib2, iclass 11, count 0 2006.173.06:12:14.52#ibcon#flushed, iclass 11, count 0 2006.173.06:12:14.52#ibcon#about to write, iclass 11, count 0 2006.173.06:12:14.52#ibcon#wrote, iclass 11, count 0 2006.173.06:12:14.52#ibcon#about to read 3, iclass 11, count 0 2006.173.06:12:14.55#ibcon#read 3, iclass 11, count 0 2006.173.06:12:14.55#ibcon#about to read 4, iclass 11, count 0 2006.173.06:12:14.55#ibcon#read 4, iclass 11, count 0 2006.173.06:12:14.55#ibcon#about to read 5, iclass 11, count 0 2006.173.06:12:14.55#ibcon#read 5, iclass 11, count 0 2006.173.06:12:14.55#ibcon#about to read 6, iclass 11, count 0 2006.173.06:12:14.55#ibcon#read 6, iclass 11, count 0 2006.173.06:12:14.55#ibcon#end of sib2, iclass 11, count 0 2006.173.06:12:14.55#ibcon#*after write, iclass 11, count 0 2006.173.06:12:14.55#ibcon#*before return 0, iclass 11, count 0 2006.173.06:12:14.55#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.06:12:14.55#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.06:12:14.55#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.06:12:14.55#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.06:12:14.55$vck44/vbbw=wide 2006.173.06:12:14.55#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.06:12:14.55#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.06:12:14.55#ibcon#ireg 8 cls_cnt 0 2006.173.06:12:14.55#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.06:12:14.62#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.06:12:14.62#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.06:12:14.62#ibcon#enter wrdev, iclass 13, count 0 2006.173.06:12:14.62#ibcon#first serial, iclass 13, count 0 2006.173.06:12:14.62#ibcon#enter sib2, iclass 13, count 0 2006.173.06:12:14.62#ibcon#flushed, iclass 13, count 0 2006.173.06:12:14.62#ibcon#about to write, iclass 13, count 0 2006.173.06:12:14.62#ibcon#wrote, iclass 13, count 0 2006.173.06:12:14.62#ibcon#about to read 3, iclass 13, count 0 2006.173.06:12:14.64#ibcon#read 3, iclass 13, count 0 2006.173.06:12:14.64#ibcon#about to read 4, iclass 13, count 0 2006.173.06:12:14.64#ibcon#read 4, iclass 13, count 0 2006.173.06:12:14.64#ibcon#about to read 5, iclass 13, count 0 2006.173.06:12:14.64#ibcon#read 5, iclass 13, count 0 2006.173.06:12:14.64#ibcon#about to read 6, iclass 13, count 0 2006.173.06:12:14.64#ibcon#read 6, iclass 13, count 0 2006.173.06:12:14.64#ibcon#end of sib2, iclass 13, count 0 2006.173.06:12:14.64#ibcon#*mode == 0, iclass 13, count 0 2006.173.06:12:14.64#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.06:12:14.64#ibcon#[27=BW32\r\n] 2006.173.06:12:14.64#ibcon#*before write, iclass 13, count 0 2006.173.06:12:14.64#ibcon#enter sib2, iclass 13, count 0 2006.173.06:12:14.64#ibcon#flushed, iclass 13, count 0 2006.173.06:12:14.64#ibcon#about to write, iclass 13, count 0 2006.173.06:12:14.64#ibcon#wrote, iclass 13, count 0 2006.173.06:12:14.64#ibcon#about to read 3, iclass 13, count 0 2006.173.06:12:14.67#ibcon#read 3, iclass 13, count 0 2006.173.06:12:14.67#ibcon#about to read 4, iclass 13, count 0 2006.173.06:12:14.67#ibcon#read 4, iclass 13, count 0 2006.173.06:12:14.67#ibcon#about to read 5, iclass 13, count 0 2006.173.06:12:14.67#ibcon#read 5, iclass 13, count 0 2006.173.06:12:14.67#ibcon#about to read 6, iclass 13, count 0 2006.173.06:12:14.67#ibcon#read 6, iclass 13, count 0 2006.173.06:12:14.67#ibcon#end of sib2, iclass 13, count 0 2006.173.06:12:14.67#ibcon#*after write, iclass 13, count 0 2006.173.06:12:14.67#ibcon#*before return 0, iclass 13, count 0 2006.173.06:12:14.67#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.06:12:14.67#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.06:12:14.67#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.06:12:14.67#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.06:12:14.67$setupk4/ifdk4 2006.173.06:12:14.67$ifdk4/lo= 2006.173.06:12:14.67$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.06:12:14.67$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.06:12:14.67$ifdk4/patch= 2006.173.06:12:14.67$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.06:12:14.67$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.06:12:14.67$setupk4/!*+20s 2006.173.06:12:19.86#abcon#<5=/01 0.6 0.9 23.86 751005.2\r\n> 2006.173.06:12:19.88#abcon#{5=INTERFACE CLEAR} 2006.173.06:12:19.94#abcon#[5=S1D000X0/0*\r\n] 2006.173.06:12:27.13#trakl#Source acquired 2006.173.06:12:29.13#flagr#flagr/antenna,acquired 2006.173.06:12:29.18$setupk4/"tpicd 2006.173.06:12:29.18$setupk4/echo=off 2006.173.06:12:29.18$setupk4/xlog=off 2006.173.06:12:29.18:!2006.173.06:12:35 2006.173.06:12:35.00:preob 2006.173.06:12:36.13/onsource/TRACKING 2006.173.06:12:36.13:!2006.173.06:12:45 2006.173.06:12:45.00:"tape 2006.173.06:12:45.00:"st=record 2006.173.06:12:45.00:data_valid=on 2006.173.06:12:45.00:midob 2006.173.06:12:45.13/onsource/TRACKING 2006.173.06:12:45.13/wx/23.85,1005.2,76 2006.173.06:12:45.28/cable/+6.5057E-03 2006.173.06:12:46.37/va/01,07,usb,yes,40,43 2006.173.06:12:46.37/va/02,06,usb,yes,40,41 2006.173.06:12:46.37/va/03,05,usb,yes,51,53 2006.173.06:12:46.37/va/04,06,usb,yes,41,43 2006.173.06:12:46.37/va/05,04,usb,yes,32,33 2006.173.06:12:46.37/va/06,03,usb,yes,45,45 2006.173.06:12:46.37/va/07,04,usb,yes,37,38 2006.173.06:12:46.37/va/08,04,usb,yes,31,38 2006.173.06:12:46.60/valo/01,524.99,yes,locked 2006.173.06:12:46.60/valo/02,534.99,yes,locked 2006.173.06:12:46.60/valo/03,564.99,yes,locked 2006.173.06:12:46.60/valo/04,624.99,yes,locked 2006.173.06:12:46.60/valo/05,734.99,yes,locked 2006.173.06:12:46.60/valo/06,814.99,yes,locked 2006.173.06:12:46.60/valo/07,864.99,yes,locked 2006.173.06:12:46.60/valo/08,884.99,yes,locked 2006.173.06:12:47.69/vb/01,04,usb,yes,32,30 2006.173.06:12:47.69/vb/02,04,usb,yes,35,34 2006.173.06:12:47.69/vb/03,04,usb,yes,31,35 2006.173.06:12:47.69/vb/04,04,usb,yes,36,35 2006.173.06:12:47.69/vb/05,04,usb,yes,28,31 2006.173.06:12:47.69/vb/06,04,usb,yes,33,29 2006.173.06:12:47.69/vb/07,04,usb,yes,33,33 2006.173.06:12:47.69/vb/08,04,usb,yes,30,34 2006.173.06:12:47.92/vblo/01,629.99,yes,locked 2006.173.06:12:47.92/vblo/02,634.99,yes,locked 2006.173.06:12:47.92/vblo/03,649.99,yes,locked 2006.173.06:12:47.92/vblo/04,679.99,yes,locked 2006.173.06:12:47.92/vblo/05,709.99,yes,locked 2006.173.06:12:47.92/vblo/06,719.99,yes,locked 2006.173.06:12:47.92/vblo/07,734.99,yes,locked 2006.173.06:12:47.92/vblo/08,744.99,yes,locked 2006.173.06:12:48.07/vabw/8 2006.173.06:12:48.22/vbbw/8 2006.173.06:12:48.31/xfe/off,on,15.2 2006.173.06:12:48.68/ifatt/23,28,28,28 2006.173.06:12:49.07/fmout-gps/S +4.03E-07 2006.173.06:12:49.11:!2006.173.06:13:25 2006.173.06:13:25.00:data_valid=off 2006.173.06:13:25.00:"et 2006.173.06:13:25.00:!+3s 2006.173.06:13:28.01:"tape 2006.173.06:13:28.01:postob 2006.173.06:13:28.13/cable/+6.5048E-03 2006.173.06:13:28.13/wx/23.86,1005.2,78 2006.173.06:13:29.07/fmout-gps/S +4.03E-07 2006.173.06:13:29.07:scan_name=173-0618,jd0606,400 2006.173.06:13:29.07:source=oq208,140700.39,282714.7,2000.0,ccw 2006.173.06:13:30.13#flagr#flagr/antenna,new-source 2006.173.06:13:30.13:checkk5 2006.173.06:13:30.48/chk_autoobs//k5ts1/ autoobs is running! 2006.173.06:13:30.87/chk_autoobs//k5ts2/ autoobs is running! 2006.173.06:13:31.27/chk_autoobs//k5ts3/ autoobs is running! 2006.173.06:13:31.67/chk_autoobs//k5ts4/ autoobs is running! 2006.173.06:13:32.06/chk_obsdata//k5ts1/T1730612??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.06:13:32.47/chk_obsdata//k5ts2/T1730612??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.06:13:32.85/chk_obsdata//k5ts3/T1730612??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.06:13:33.26/chk_obsdata//k5ts4/T1730612??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.06:13:33.98/k5log//k5ts1_log_newline 2006.173.06:13:34.68/k5log//k5ts2_log_newline 2006.173.06:13:35.38/k5log//k5ts3_log_newline 2006.173.06:13:36.07/k5log//k5ts4_log_newline 2006.173.06:13:36.09/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.06:13:36.09:setupk4=1 2006.173.06:13:36.10$setupk4/echo=on 2006.173.06:13:36.10$setupk4/pcalon 2006.173.06:13:36.10$pcalon/"no phase cal control is implemented here 2006.173.06:13:36.10$setupk4/"tpicd=stop 2006.173.06:13:36.10$setupk4/"rec=synch_on 2006.173.06:13:36.10$setupk4/"rec_mode=128 2006.173.06:13:36.10$setupk4/!* 2006.173.06:13:36.10$setupk4/recpk4 2006.173.06:13:36.10$recpk4/recpatch= 2006.173.06:13:36.10$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.06:13:36.10$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.06:13:36.10$setupk4/vck44 2006.173.06:13:36.10$vck44/valo=1,524.99 2006.173.06:13:36.10#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.06:13:36.10#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.06:13:36.10#ibcon#ireg 17 cls_cnt 0 2006.173.06:13:36.10#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.06:13:36.10#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.06:13:36.10#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.06:13:36.10#ibcon#enter wrdev, iclass 14, count 0 2006.173.06:13:36.10#ibcon#first serial, iclass 14, count 0 2006.173.06:13:36.10#ibcon#enter sib2, iclass 14, count 0 2006.173.06:13:36.10#ibcon#flushed, iclass 14, count 0 2006.173.06:13:36.10#ibcon#about to write, iclass 14, count 0 2006.173.06:13:36.10#ibcon#wrote, iclass 14, count 0 2006.173.06:13:36.10#ibcon#about to read 3, iclass 14, count 0 2006.173.06:13:36.12#ibcon#read 3, iclass 14, count 0 2006.173.06:13:36.12#ibcon#about to read 4, iclass 14, count 0 2006.173.06:13:36.12#ibcon#read 4, iclass 14, count 0 2006.173.06:13:36.12#ibcon#about to read 5, iclass 14, count 0 2006.173.06:13:36.12#ibcon#read 5, iclass 14, count 0 2006.173.06:13:36.12#ibcon#about to read 6, iclass 14, count 0 2006.173.06:13:36.12#ibcon#read 6, iclass 14, count 0 2006.173.06:13:36.12#ibcon#end of sib2, iclass 14, count 0 2006.173.06:13:36.12#ibcon#*mode == 0, iclass 14, count 0 2006.173.06:13:36.12#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.06:13:36.12#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.06:13:36.12#ibcon#*before write, iclass 14, count 0 2006.173.06:13:36.12#ibcon#enter sib2, iclass 14, count 0 2006.173.06:13:36.12#ibcon#flushed, iclass 14, count 0 2006.173.06:13:36.12#ibcon#about to write, iclass 14, count 0 2006.173.06:13:36.12#ibcon#wrote, iclass 14, count 0 2006.173.06:13:36.12#ibcon#about to read 3, iclass 14, count 0 2006.173.06:13:36.17#ibcon#read 3, iclass 14, count 0 2006.173.06:13:36.17#ibcon#about to read 4, iclass 14, count 0 2006.173.06:13:36.17#ibcon#read 4, iclass 14, count 0 2006.173.06:13:36.17#ibcon#about to read 5, iclass 14, count 0 2006.173.06:13:36.17#ibcon#read 5, iclass 14, count 0 2006.173.06:13:36.17#ibcon#about to read 6, iclass 14, count 0 2006.173.06:13:36.17#ibcon#read 6, iclass 14, count 0 2006.173.06:13:36.17#ibcon#end of sib2, iclass 14, count 0 2006.173.06:13:36.17#ibcon#*after write, iclass 14, count 0 2006.173.06:13:36.17#ibcon#*before return 0, iclass 14, count 0 2006.173.06:13:36.17#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.06:13:36.17#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.06:13:36.17#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.06:13:36.17#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.06:13:36.17$vck44/va=1,7 2006.173.06:13:36.17#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.06:13:36.17#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.06:13:36.17#ibcon#ireg 11 cls_cnt 2 2006.173.06:13:36.17#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.06:13:36.17#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.06:13:36.17#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.06:13:36.17#ibcon#enter wrdev, iclass 16, count 2 2006.173.06:13:36.17#ibcon#first serial, iclass 16, count 2 2006.173.06:13:36.17#ibcon#enter sib2, iclass 16, count 2 2006.173.06:13:36.17#ibcon#flushed, iclass 16, count 2 2006.173.06:13:36.17#ibcon#about to write, iclass 16, count 2 2006.173.06:13:36.17#ibcon#wrote, iclass 16, count 2 2006.173.06:13:36.17#ibcon#about to read 3, iclass 16, count 2 2006.173.06:13:36.19#ibcon#read 3, iclass 16, count 2 2006.173.06:13:36.19#ibcon#about to read 4, iclass 16, count 2 2006.173.06:13:36.19#ibcon#read 4, iclass 16, count 2 2006.173.06:13:36.19#ibcon#about to read 5, iclass 16, count 2 2006.173.06:13:36.19#ibcon#read 5, iclass 16, count 2 2006.173.06:13:36.19#ibcon#about to read 6, iclass 16, count 2 2006.173.06:13:36.19#ibcon#read 6, iclass 16, count 2 2006.173.06:13:36.19#ibcon#end of sib2, iclass 16, count 2 2006.173.06:13:36.19#ibcon#*mode == 0, iclass 16, count 2 2006.173.06:13:36.19#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.06:13:36.19#ibcon#[25=AT01-07\r\n] 2006.173.06:13:36.19#ibcon#*before write, iclass 16, count 2 2006.173.06:13:36.19#ibcon#enter sib2, iclass 16, count 2 2006.173.06:13:36.19#ibcon#flushed, iclass 16, count 2 2006.173.06:13:36.19#ibcon#about to write, iclass 16, count 2 2006.173.06:13:36.19#ibcon#wrote, iclass 16, count 2 2006.173.06:13:36.19#ibcon#about to read 3, iclass 16, count 2 2006.173.06:13:36.22#ibcon#read 3, iclass 16, count 2 2006.173.06:13:36.22#ibcon#about to read 4, iclass 16, count 2 2006.173.06:13:36.22#ibcon#read 4, iclass 16, count 2 2006.173.06:13:36.22#ibcon#about to read 5, iclass 16, count 2 2006.173.06:13:36.22#ibcon#read 5, iclass 16, count 2 2006.173.06:13:36.22#ibcon#about to read 6, iclass 16, count 2 2006.173.06:13:36.22#ibcon#read 6, iclass 16, count 2 2006.173.06:13:36.22#ibcon#end of sib2, iclass 16, count 2 2006.173.06:13:36.22#ibcon#*after write, iclass 16, count 2 2006.173.06:13:36.22#ibcon#*before return 0, iclass 16, count 2 2006.173.06:13:36.22#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.06:13:36.22#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.06:13:36.22#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.06:13:36.22#ibcon#ireg 7 cls_cnt 0 2006.173.06:13:36.22#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.06:13:36.34#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.06:13:36.34#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.06:13:36.34#ibcon#enter wrdev, iclass 16, count 0 2006.173.06:13:36.34#ibcon#first serial, iclass 16, count 0 2006.173.06:13:36.34#ibcon#enter sib2, iclass 16, count 0 2006.173.06:13:36.34#ibcon#flushed, iclass 16, count 0 2006.173.06:13:36.34#ibcon#about to write, iclass 16, count 0 2006.173.06:13:36.34#ibcon#wrote, iclass 16, count 0 2006.173.06:13:36.34#ibcon#about to read 3, iclass 16, count 0 2006.173.06:13:36.36#ibcon#read 3, iclass 16, count 0 2006.173.06:13:36.36#ibcon#about to read 4, iclass 16, count 0 2006.173.06:13:36.36#ibcon#read 4, iclass 16, count 0 2006.173.06:13:36.36#ibcon#about to read 5, iclass 16, count 0 2006.173.06:13:36.36#ibcon#read 5, iclass 16, count 0 2006.173.06:13:36.36#ibcon#about to read 6, iclass 16, count 0 2006.173.06:13:36.36#ibcon#read 6, iclass 16, count 0 2006.173.06:13:36.36#ibcon#end of sib2, iclass 16, count 0 2006.173.06:13:36.36#ibcon#*mode == 0, iclass 16, count 0 2006.173.06:13:36.36#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.06:13:36.36#ibcon#[25=USB\r\n] 2006.173.06:13:36.36#ibcon#*before write, iclass 16, count 0 2006.173.06:13:36.36#ibcon#enter sib2, iclass 16, count 0 2006.173.06:13:36.36#ibcon#flushed, iclass 16, count 0 2006.173.06:13:36.36#ibcon#about to write, iclass 16, count 0 2006.173.06:13:36.36#ibcon#wrote, iclass 16, count 0 2006.173.06:13:36.36#ibcon#about to read 3, iclass 16, count 0 2006.173.06:13:36.39#ibcon#read 3, iclass 16, count 0 2006.173.06:13:36.39#ibcon#about to read 4, iclass 16, count 0 2006.173.06:13:36.39#ibcon#read 4, iclass 16, count 0 2006.173.06:13:36.39#ibcon#about to read 5, iclass 16, count 0 2006.173.06:13:36.39#ibcon#read 5, iclass 16, count 0 2006.173.06:13:36.39#ibcon#about to read 6, iclass 16, count 0 2006.173.06:13:36.39#ibcon#read 6, iclass 16, count 0 2006.173.06:13:36.39#ibcon#end of sib2, iclass 16, count 0 2006.173.06:13:36.39#ibcon#*after write, iclass 16, count 0 2006.173.06:13:36.39#ibcon#*before return 0, iclass 16, count 0 2006.173.06:13:36.39#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.06:13:36.39#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.06:13:36.39#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.06:13:36.39#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.06:13:36.39$vck44/valo=2,534.99 2006.173.06:13:36.39#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.06:13:36.39#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.06:13:36.39#ibcon#ireg 17 cls_cnt 0 2006.173.06:13:36.39#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.06:13:36.39#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.06:13:36.39#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.06:13:36.39#ibcon#enter wrdev, iclass 18, count 0 2006.173.06:13:36.39#ibcon#first serial, iclass 18, count 0 2006.173.06:13:36.39#ibcon#enter sib2, iclass 18, count 0 2006.173.06:13:36.39#ibcon#flushed, iclass 18, count 0 2006.173.06:13:36.39#ibcon#about to write, iclass 18, count 0 2006.173.06:13:36.39#ibcon#wrote, iclass 18, count 0 2006.173.06:13:36.39#ibcon#about to read 3, iclass 18, count 0 2006.173.06:13:36.41#ibcon#read 3, iclass 18, count 0 2006.173.06:13:36.41#ibcon#about to read 4, iclass 18, count 0 2006.173.06:13:36.41#ibcon#read 4, iclass 18, count 0 2006.173.06:13:36.41#ibcon#about to read 5, iclass 18, count 0 2006.173.06:13:36.41#ibcon#read 5, iclass 18, count 0 2006.173.06:13:36.41#ibcon#about to read 6, iclass 18, count 0 2006.173.06:13:36.41#ibcon#read 6, iclass 18, count 0 2006.173.06:13:36.41#ibcon#end of sib2, iclass 18, count 0 2006.173.06:13:36.41#ibcon#*mode == 0, iclass 18, count 0 2006.173.06:13:36.41#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.06:13:36.41#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.06:13:36.41#ibcon#*before write, iclass 18, count 0 2006.173.06:13:36.41#ibcon#enter sib2, iclass 18, count 0 2006.173.06:13:36.41#ibcon#flushed, iclass 18, count 0 2006.173.06:13:36.41#ibcon#about to write, iclass 18, count 0 2006.173.06:13:36.41#ibcon#wrote, iclass 18, count 0 2006.173.06:13:36.41#ibcon#about to read 3, iclass 18, count 0 2006.173.06:13:36.45#ibcon#read 3, iclass 18, count 0 2006.173.06:13:36.45#ibcon#about to read 4, iclass 18, count 0 2006.173.06:13:36.45#ibcon#read 4, iclass 18, count 0 2006.173.06:13:36.45#ibcon#about to read 5, iclass 18, count 0 2006.173.06:13:36.45#ibcon#read 5, iclass 18, count 0 2006.173.06:13:36.45#ibcon#about to read 6, iclass 18, count 0 2006.173.06:13:36.45#ibcon#read 6, iclass 18, count 0 2006.173.06:13:36.45#ibcon#end of sib2, iclass 18, count 0 2006.173.06:13:36.45#ibcon#*after write, iclass 18, count 0 2006.173.06:13:36.45#ibcon#*before return 0, iclass 18, count 0 2006.173.06:13:36.45#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.06:13:36.45#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.06:13:36.45#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.06:13:36.45#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.06:13:36.45$vck44/va=2,6 2006.173.06:13:36.45#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.06:13:36.45#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.06:13:36.45#ibcon#ireg 11 cls_cnt 2 2006.173.06:13:36.45#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.06:13:36.51#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.06:13:36.51#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.06:13:36.51#ibcon#enter wrdev, iclass 20, count 2 2006.173.06:13:36.51#ibcon#first serial, iclass 20, count 2 2006.173.06:13:36.51#ibcon#enter sib2, iclass 20, count 2 2006.173.06:13:36.51#ibcon#flushed, iclass 20, count 2 2006.173.06:13:36.51#ibcon#about to write, iclass 20, count 2 2006.173.06:13:36.51#ibcon#wrote, iclass 20, count 2 2006.173.06:13:36.51#ibcon#about to read 3, iclass 20, count 2 2006.173.06:13:36.53#ibcon#read 3, iclass 20, count 2 2006.173.06:13:36.53#ibcon#about to read 4, iclass 20, count 2 2006.173.06:13:36.53#ibcon#read 4, iclass 20, count 2 2006.173.06:13:36.53#ibcon#about to read 5, iclass 20, count 2 2006.173.06:13:36.53#ibcon#read 5, iclass 20, count 2 2006.173.06:13:36.53#ibcon#about to read 6, iclass 20, count 2 2006.173.06:13:36.53#ibcon#read 6, iclass 20, count 2 2006.173.06:13:36.53#ibcon#end of sib2, iclass 20, count 2 2006.173.06:13:36.53#ibcon#*mode == 0, iclass 20, count 2 2006.173.06:13:36.53#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.06:13:36.53#ibcon#[25=AT02-06\r\n] 2006.173.06:13:36.53#ibcon#*before write, iclass 20, count 2 2006.173.06:13:36.53#ibcon#enter sib2, iclass 20, count 2 2006.173.06:13:36.53#ibcon#flushed, iclass 20, count 2 2006.173.06:13:36.53#ibcon#about to write, iclass 20, count 2 2006.173.06:13:36.53#ibcon#wrote, iclass 20, count 2 2006.173.06:13:36.53#ibcon#about to read 3, iclass 20, count 2 2006.173.06:13:36.56#ibcon#read 3, iclass 20, count 2 2006.173.06:13:36.56#ibcon#about to read 4, iclass 20, count 2 2006.173.06:13:36.56#ibcon#read 4, iclass 20, count 2 2006.173.06:13:36.56#ibcon#about to read 5, iclass 20, count 2 2006.173.06:13:36.56#ibcon#read 5, iclass 20, count 2 2006.173.06:13:36.56#ibcon#about to read 6, iclass 20, count 2 2006.173.06:13:36.56#ibcon#read 6, iclass 20, count 2 2006.173.06:13:36.56#ibcon#end of sib2, iclass 20, count 2 2006.173.06:13:36.56#ibcon#*after write, iclass 20, count 2 2006.173.06:13:36.56#ibcon#*before return 0, iclass 20, count 2 2006.173.06:13:36.56#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.06:13:36.56#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.06:13:36.56#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.06:13:36.56#ibcon#ireg 7 cls_cnt 0 2006.173.06:13:36.56#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.06:13:36.68#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.06:13:36.68#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.06:13:36.68#ibcon#enter wrdev, iclass 20, count 0 2006.173.06:13:36.68#ibcon#first serial, iclass 20, count 0 2006.173.06:13:36.68#ibcon#enter sib2, iclass 20, count 0 2006.173.06:13:36.68#ibcon#flushed, iclass 20, count 0 2006.173.06:13:36.68#ibcon#about to write, iclass 20, count 0 2006.173.06:13:36.68#ibcon#wrote, iclass 20, count 0 2006.173.06:13:36.68#ibcon#about to read 3, iclass 20, count 0 2006.173.06:13:36.70#ibcon#read 3, iclass 20, count 0 2006.173.06:13:36.70#ibcon#about to read 4, iclass 20, count 0 2006.173.06:13:36.70#ibcon#read 4, iclass 20, count 0 2006.173.06:13:36.70#ibcon#about to read 5, iclass 20, count 0 2006.173.06:13:36.70#ibcon#read 5, iclass 20, count 0 2006.173.06:13:36.70#ibcon#about to read 6, iclass 20, count 0 2006.173.06:13:36.70#ibcon#read 6, iclass 20, count 0 2006.173.06:13:36.70#ibcon#end of sib2, iclass 20, count 0 2006.173.06:13:36.70#ibcon#*mode == 0, iclass 20, count 0 2006.173.06:13:36.70#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.06:13:36.70#ibcon#[25=USB\r\n] 2006.173.06:13:36.70#ibcon#*before write, iclass 20, count 0 2006.173.06:13:36.70#ibcon#enter sib2, iclass 20, count 0 2006.173.06:13:36.70#ibcon#flushed, iclass 20, count 0 2006.173.06:13:36.70#ibcon#about to write, iclass 20, count 0 2006.173.06:13:36.70#ibcon#wrote, iclass 20, count 0 2006.173.06:13:36.70#ibcon#about to read 3, iclass 20, count 0 2006.173.06:13:36.73#ibcon#read 3, iclass 20, count 0 2006.173.06:13:36.73#ibcon#about to read 4, iclass 20, count 0 2006.173.06:13:36.73#ibcon#read 4, iclass 20, count 0 2006.173.06:13:36.73#ibcon#about to read 5, iclass 20, count 0 2006.173.06:13:36.73#ibcon#read 5, iclass 20, count 0 2006.173.06:13:36.73#ibcon#about to read 6, iclass 20, count 0 2006.173.06:13:36.73#ibcon#read 6, iclass 20, count 0 2006.173.06:13:36.73#ibcon#end of sib2, iclass 20, count 0 2006.173.06:13:36.73#ibcon#*after write, iclass 20, count 0 2006.173.06:13:36.73#ibcon#*before return 0, iclass 20, count 0 2006.173.06:13:36.73#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.06:13:36.73#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.06:13:36.73#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.06:13:36.73#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.06:13:36.73$vck44/valo=3,564.99 2006.173.06:13:36.73#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.06:13:36.73#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.06:13:36.73#ibcon#ireg 17 cls_cnt 0 2006.173.06:13:36.73#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.06:13:36.73#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.06:13:36.73#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.06:13:36.73#ibcon#enter wrdev, iclass 22, count 0 2006.173.06:13:36.73#ibcon#first serial, iclass 22, count 0 2006.173.06:13:36.73#ibcon#enter sib2, iclass 22, count 0 2006.173.06:13:36.73#ibcon#flushed, iclass 22, count 0 2006.173.06:13:36.73#ibcon#about to write, iclass 22, count 0 2006.173.06:13:36.73#ibcon#wrote, iclass 22, count 0 2006.173.06:13:36.73#ibcon#about to read 3, iclass 22, count 0 2006.173.06:13:36.75#ibcon#read 3, iclass 22, count 0 2006.173.06:13:36.75#ibcon#about to read 4, iclass 22, count 0 2006.173.06:13:36.75#ibcon#read 4, iclass 22, count 0 2006.173.06:13:36.75#ibcon#about to read 5, iclass 22, count 0 2006.173.06:13:36.75#ibcon#read 5, iclass 22, count 0 2006.173.06:13:36.75#ibcon#about to read 6, iclass 22, count 0 2006.173.06:13:36.75#ibcon#read 6, iclass 22, count 0 2006.173.06:13:36.75#ibcon#end of sib2, iclass 22, count 0 2006.173.06:13:36.75#ibcon#*mode == 0, iclass 22, count 0 2006.173.06:13:36.75#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.06:13:36.75#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.06:13:36.75#ibcon#*before write, iclass 22, count 0 2006.173.06:13:36.75#ibcon#enter sib2, iclass 22, count 0 2006.173.06:13:36.75#ibcon#flushed, iclass 22, count 0 2006.173.06:13:36.75#ibcon#about to write, iclass 22, count 0 2006.173.06:13:36.75#ibcon#wrote, iclass 22, count 0 2006.173.06:13:36.75#ibcon#about to read 3, iclass 22, count 0 2006.173.06:13:36.79#ibcon#read 3, iclass 22, count 0 2006.173.06:13:36.79#ibcon#about to read 4, iclass 22, count 0 2006.173.06:13:36.79#ibcon#read 4, iclass 22, count 0 2006.173.06:13:36.79#ibcon#about to read 5, iclass 22, count 0 2006.173.06:13:36.79#ibcon#read 5, iclass 22, count 0 2006.173.06:13:36.79#ibcon#about to read 6, iclass 22, count 0 2006.173.06:13:36.79#ibcon#read 6, iclass 22, count 0 2006.173.06:13:36.79#ibcon#end of sib2, iclass 22, count 0 2006.173.06:13:36.79#ibcon#*after write, iclass 22, count 0 2006.173.06:13:36.79#ibcon#*before return 0, iclass 22, count 0 2006.173.06:13:36.79#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.06:13:36.79#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.06:13:36.79#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.06:13:36.79#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.06:13:36.79$vck44/va=3,5 2006.173.06:13:36.79#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.06:13:36.79#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.06:13:36.79#ibcon#ireg 11 cls_cnt 2 2006.173.06:13:36.79#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.06:13:36.85#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.06:13:36.85#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.06:13:36.85#ibcon#enter wrdev, iclass 24, count 2 2006.173.06:13:36.85#ibcon#first serial, iclass 24, count 2 2006.173.06:13:36.85#ibcon#enter sib2, iclass 24, count 2 2006.173.06:13:36.85#ibcon#flushed, iclass 24, count 2 2006.173.06:13:36.85#ibcon#about to write, iclass 24, count 2 2006.173.06:13:36.85#ibcon#wrote, iclass 24, count 2 2006.173.06:13:36.85#ibcon#about to read 3, iclass 24, count 2 2006.173.06:13:36.87#ibcon#read 3, iclass 24, count 2 2006.173.06:13:36.87#ibcon#about to read 4, iclass 24, count 2 2006.173.06:13:36.87#ibcon#read 4, iclass 24, count 2 2006.173.06:13:36.87#ibcon#about to read 5, iclass 24, count 2 2006.173.06:13:36.87#ibcon#read 5, iclass 24, count 2 2006.173.06:13:36.87#ibcon#about to read 6, iclass 24, count 2 2006.173.06:13:36.87#ibcon#read 6, iclass 24, count 2 2006.173.06:13:36.87#ibcon#end of sib2, iclass 24, count 2 2006.173.06:13:36.87#ibcon#*mode == 0, iclass 24, count 2 2006.173.06:13:36.87#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.06:13:36.87#ibcon#[25=AT03-05\r\n] 2006.173.06:13:36.87#ibcon#*before write, iclass 24, count 2 2006.173.06:13:36.87#ibcon#enter sib2, iclass 24, count 2 2006.173.06:13:36.87#ibcon#flushed, iclass 24, count 2 2006.173.06:13:36.87#ibcon#about to write, iclass 24, count 2 2006.173.06:13:36.87#ibcon#wrote, iclass 24, count 2 2006.173.06:13:36.87#ibcon#about to read 3, iclass 24, count 2 2006.173.06:13:36.90#ibcon#read 3, iclass 24, count 2 2006.173.06:13:36.90#ibcon#about to read 4, iclass 24, count 2 2006.173.06:13:36.90#ibcon#read 4, iclass 24, count 2 2006.173.06:13:36.90#ibcon#about to read 5, iclass 24, count 2 2006.173.06:13:36.90#ibcon#read 5, iclass 24, count 2 2006.173.06:13:36.90#ibcon#about to read 6, iclass 24, count 2 2006.173.06:13:36.90#ibcon#read 6, iclass 24, count 2 2006.173.06:13:36.90#ibcon#end of sib2, iclass 24, count 2 2006.173.06:13:36.90#ibcon#*after write, iclass 24, count 2 2006.173.06:13:36.90#ibcon#*before return 0, iclass 24, count 2 2006.173.06:13:36.90#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.06:13:36.90#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.06:13:36.90#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.06:13:36.90#ibcon#ireg 7 cls_cnt 0 2006.173.06:13:36.90#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.06:13:37.02#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.06:13:37.02#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.06:13:37.02#ibcon#enter wrdev, iclass 24, count 0 2006.173.06:13:37.02#ibcon#first serial, iclass 24, count 0 2006.173.06:13:37.02#ibcon#enter sib2, iclass 24, count 0 2006.173.06:13:37.02#ibcon#flushed, iclass 24, count 0 2006.173.06:13:37.02#ibcon#about to write, iclass 24, count 0 2006.173.06:13:37.02#ibcon#wrote, iclass 24, count 0 2006.173.06:13:37.02#ibcon#about to read 3, iclass 24, count 0 2006.173.06:13:37.04#ibcon#read 3, iclass 24, count 0 2006.173.06:13:37.04#ibcon#about to read 4, iclass 24, count 0 2006.173.06:13:37.04#ibcon#read 4, iclass 24, count 0 2006.173.06:13:37.04#ibcon#about to read 5, iclass 24, count 0 2006.173.06:13:37.04#ibcon#read 5, iclass 24, count 0 2006.173.06:13:37.04#ibcon#about to read 6, iclass 24, count 0 2006.173.06:13:37.04#ibcon#read 6, iclass 24, count 0 2006.173.06:13:37.04#ibcon#end of sib2, iclass 24, count 0 2006.173.06:13:37.04#ibcon#*mode == 0, iclass 24, count 0 2006.173.06:13:37.04#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.06:13:37.04#ibcon#[25=USB\r\n] 2006.173.06:13:37.04#ibcon#*before write, iclass 24, count 0 2006.173.06:13:37.04#ibcon#enter sib2, iclass 24, count 0 2006.173.06:13:37.04#ibcon#flushed, iclass 24, count 0 2006.173.06:13:37.04#ibcon#about to write, iclass 24, count 0 2006.173.06:13:37.04#ibcon#wrote, iclass 24, count 0 2006.173.06:13:37.04#ibcon#about to read 3, iclass 24, count 0 2006.173.06:13:37.07#ibcon#read 3, iclass 24, count 0 2006.173.06:13:37.07#ibcon#about to read 4, iclass 24, count 0 2006.173.06:13:37.07#ibcon#read 4, iclass 24, count 0 2006.173.06:13:37.07#ibcon#about to read 5, iclass 24, count 0 2006.173.06:13:37.07#ibcon#read 5, iclass 24, count 0 2006.173.06:13:37.07#ibcon#about to read 6, iclass 24, count 0 2006.173.06:13:37.07#ibcon#read 6, iclass 24, count 0 2006.173.06:13:37.07#ibcon#end of sib2, iclass 24, count 0 2006.173.06:13:37.07#ibcon#*after write, iclass 24, count 0 2006.173.06:13:37.07#ibcon#*before return 0, iclass 24, count 0 2006.173.06:13:37.07#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.06:13:37.07#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.06:13:37.07#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.06:13:37.07#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.06:13:37.07$vck44/valo=4,624.99 2006.173.06:13:37.07#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.06:13:37.07#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.06:13:37.07#ibcon#ireg 17 cls_cnt 0 2006.173.06:13:37.07#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.06:13:37.07#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.06:13:37.07#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.06:13:37.07#ibcon#enter wrdev, iclass 26, count 0 2006.173.06:13:37.07#ibcon#first serial, iclass 26, count 0 2006.173.06:13:37.07#ibcon#enter sib2, iclass 26, count 0 2006.173.06:13:37.07#ibcon#flushed, iclass 26, count 0 2006.173.06:13:37.07#ibcon#about to write, iclass 26, count 0 2006.173.06:13:37.07#ibcon#wrote, iclass 26, count 0 2006.173.06:13:37.07#ibcon#about to read 3, iclass 26, count 0 2006.173.06:13:37.09#ibcon#read 3, iclass 26, count 0 2006.173.06:13:37.09#ibcon#about to read 4, iclass 26, count 0 2006.173.06:13:37.09#ibcon#read 4, iclass 26, count 0 2006.173.06:13:37.09#ibcon#about to read 5, iclass 26, count 0 2006.173.06:13:37.09#ibcon#read 5, iclass 26, count 0 2006.173.06:13:37.09#ibcon#about to read 6, iclass 26, count 0 2006.173.06:13:37.09#ibcon#read 6, iclass 26, count 0 2006.173.06:13:37.09#ibcon#end of sib2, iclass 26, count 0 2006.173.06:13:37.09#ibcon#*mode == 0, iclass 26, count 0 2006.173.06:13:37.09#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.06:13:37.09#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.06:13:37.09#ibcon#*before write, iclass 26, count 0 2006.173.06:13:37.09#ibcon#enter sib2, iclass 26, count 0 2006.173.06:13:37.09#ibcon#flushed, iclass 26, count 0 2006.173.06:13:37.09#ibcon#about to write, iclass 26, count 0 2006.173.06:13:37.09#ibcon#wrote, iclass 26, count 0 2006.173.06:13:37.09#ibcon#about to read 3, iclass 26, count 0 2006.173.06:13:37.13#ibcon#read 3, iclass 26, count 0 2006.173.06:13:37.13#ibcon#about to read 4, iclass 26, count 0 2006.173.06:13:37.13#ibcon#read 4, iclass 26, count 0 2006.173.06:13:37.13#ibcon#about to read 5, iclass 26, count 0 2006.173.06:13:37.13#ibcon#read 5, iclass 26, count 0 2006.173.06:13:37.13#ibcon#about to read 6, iclass 26, count 0 2006.173.06:13:37.13#ibcon#read 6, iclass 26, count 0 2006.173.06:13:37.13#ibcon#end of sib2, iclass 26, count 0 2006.173.06:13:37.13#ibcon#*after write, iclass 26, count 0 2006.173.06:13:37.13#ibcon#*before return 0, iclass 26, count 0 2006.173.06:13:37.13#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.06:13:37.13#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.06:13:37.13#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.06:13:37.13#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.06:13:37.13$vck44/va=4,6 2006.173.06:13:37.13#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.06:13:37.13#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.06:13:37.13#ibcon#ireg 11 cls_cnt 2 2006.173.06:13:37.13#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.06:13:37.19#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.06:13:37.19#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.06:13:37.19#ibcon#enter wrdev, iclass 28, count 2 2006.173.06:13:37.19#ibcon#first serial, iclass 28, count 2 2006.173.06:13:37.19#ibcon#enter sib2, iclass 28, count 2 2006.173.06:13:37.19#ibcon#flushed, iclass 28, count 2 2006.173.06:13:37.19#ibcon#about to write, iclass 28, count 2 2006.173.06:13:37.19#ibcon#wrote, iclass 28, count 2 2006.173.06:13:37.19#ibcon#about to read 3, iclass 28, count 2 2006.173.06:13:37.21#ibcon#read 3, iclass 28, count 2 2006.173.06:13:37.21#ibcon#about to read 4, iclass 28, count 2 2006.173.06:13:37.21#ibcon#read 4, iclass 28, count 2 2006.173.06:13:37.21#ibcon#about to read 5, iclass 28, count 2 2006.173.06:13:37.21#ibcon#read 5, iclass 28, count 2 2006.173.06:13:37.21#ibcon#about to read 6, iclass 28, count 2 2006.173.06:13:37.21#ibcon#read 6, iclass 28, count 2 2006.173.06:13:37.21#ibcon#end of sib2, iclass 28, count 2 2006.173.06:13:37.21#ibcon#*mode == 0, iclass 28, count 2 2006.173.06:13:37.21#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.06:13:37.21#ibcon#[25=AT04-06\r\n] 2006.173.06:13:37.21#ibcon#*before write, iclass 28, count 2 2006.173.06:13:37.21#ibcon#enter sib2, iclass 28, count 2 2006.173.06:13:37.21#ibcon#flushed, iclass 28, count 2 2006.173.06:13:37.21#ibcon#about to write, iclass 28, count 2 2006.173.06:13:37.21#ibcon#wrote, iclass 28, count 2 2006.173.06:13:37.21#ibcon#about to read 3, iclass 28, count 2 2006.173.06:13:37.24#ibcon#read 3, iclass 28, count 2 2006.173.06:13:37.24#ibcon#about to read 4, iclass 28, count 2 2006.173.06:13:37.24#ibcon#read 4, iclass 28, count 2 2006.173.06:13:37.24#ibcon#about to read 5, iclass 28, count 2 2006.173.06:13:37.24#ibcon#read 5, iclass 28, count 2 2006.173.06:13:37.24#ibcon#about to read 6, iclass 28, count 2 2006.173.06:13:37.24#ibcon#read 6, iclass 28, count 2 2006.173.06:13:37.24#ibcon#end of sib2, iclass 28, count 2 2006.173.06:13:37.24#ibcon#*after write, iclass 28, count 2 2006.173.06:13:37.24#ibcon#*before return 0, iclass 28, count 2 2006.173.06:13:37.24#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.06:13:37.24#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.06:13:37.24#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.06:13:37.24#ibcon#ireg 7 cls_cnt 0 2006.173.06:13:37.24#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.06:13:37.36#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.06:13:37.36#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.06:13:37.36#ibcon#enter wrdev, iclass 28, count 0 2006.173.06:13:37.36#ibcon#first serial, iclass 28, count 0 2006.173.06:13:37.36#ibcon#enter sib2, iclass 28, count 0 2006.173.06:13:37.36#ibcon#flushed, iclass 28, count 0 2006.173.06:13:37.36#ibcon#about to write, iclass 28, count 0 2006.173.06:13:37.36#ibcon#wrote, iclass 28, count 0 2006.173.06:13:37.36#ibcon#about to read 3, iclass 28, count 0 2006.173.06:13:37.38#ibcon#read 3, iclass 28, count 0 2006.173.06:13:37.38#ibcon#about to read 4, iclass 28, count 0 2006.173.06:13:37.38#ibcon#read 4, iclass 28, count 0 2006.173.06:13:37.38#ibcon#about to read 5, iclass 28, count 0 2006.173.06:13:37.38#ibcon#read 5, iclass 28, count 0 2006.173.06:13:37.38#ibcon#about to read 6, iclass 28, count 0 2006.173.06:13:37.38#ibcon#read 6, iclass 28, count 0 2006.173.06:13:37.38#ibcon#end of sib2, iclass 28, count 0 2006.173.06:13:37.38#ibcon#*mode == 0, iclass 28, count 0 2006.173.06:13:37.38#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.06:13:37.38#ibcon#[25=USB\r\n] 2006.173.06:13:37.38#ibcon#*before write, iclass 28, count 0 2006.173.06:13:37.38#ibcon#enter sib2, iclass 28, count 0 2006.173.06:13:37.38#ibcon#flushed, iclass 28, count 0 2006.173.06:13:37.38#ibcon#about to write, iclass 28, count 0 2006.173.06:13:37.38#ibcon#wrote, iclass 28, count 0 2006.173.06:13:37.38#ibcon#about to read 3, iclass 28, count 0 2006.173.06:13:37.41#ibcon#read 3, iclass 28, count 0 2006.173.06:13:37.41#ibcon#about to read 4, iclass 28, count 0 2006.173.06:13:37.41#ibcon#read 4, iclass 28, count 0 2006.173.06:13:37.41#ibcon#about to read 5, iclass 28, count 0 2006.173.06:13:37.41#ibcon#read 5, iclass 28, count 0 2006.173.06:13:37.41#ibcon#about to read 6, iclass 28, count 0 2006.173.06:13:37.41#ibcon#read 6, iclass 28, count 0 2006.173.06:13:37.41#ibcon#end of sib2, iclass 28, count 0 2006.173.06:13:37.41#ibcon#*after write, iclass 28, count 0 2006.173.06:13:37.41#ibcon#*before return 0, iclass 28, count 0 2006.173.06:13:37.41#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.06:13:37.41#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.06:13:37.41#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.06:13:37.41#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.06:13:37.41$vck44/valo=5,734.99 2006.173.06:13:37.41#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.06:13:37.41#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.06:13:37.41#ibcon#ireg 17 cls_cnt 0 2006.173.06:13:37.41#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.06:13:37.41#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.06:13:37.41#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.06:13:37.41#ibcon#enter wrdev, iclass 30, count 0 2006.173.06:13:37.41#ibcon#first serial, iclass 30, count 0 2006.173.06:13:37.41#ibcon#enter sib2, iclass 30, count 0 2006.173.06:13:37.41#ibcon#flushed, iclass 30, count 0 2006.173.06:13:37.41#ibcon#about to write, iclass 30, count 0 2006.173.06:13:37.41#ibcon#wrote, iclass 30, count 0 2006.173.06:13:37.41#ibcon#about to read 3, iclass 30, count 0 2006.173.06:13:37.43#ibcon#read 3, iclass 30, count 0 2006.173.06:13:37.43#ibcon#about to read 4, iclass 30, count 0 2006.173.06:13:37.43#ibcon#read 4, iclass 30, count 0 2006.173.06:13:37.43#ibcon#about to read 5, iclass 30, count 0 2006.173.06:13:37.43#ibcon#read 5, iclass 30, count 0 2006.173.06:13:37.43#ibcon#about to read 6, iclass 30, count 0 2006.173.06:13:37.43#ibcon#read 6, iclass 30, count 0 2006.173.06:13:37.43#ibcon#end of sib2, iclass 30, count 0 2006.173.06:13:37.43#ibcon#*mode == 0, iclass 30, count 0 2006.173.06:13:37.43#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.06:13:37.43#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.06:13:37.43#ibcon#*before write, iclass 30, count 0 2006.173.06:13:37.43#ibcon#enter sib2, iclass 30, count 0 2006.173.06:13:37.43#ibcon#flushed, iclass 30, count 0 2006.173.06:13:37.43#ibcon#about to write, iclass 30, count 0 2006.173.06:13:37.43#ibcon#wrote, iclass 30, count 0 2006.173.06:13:37.43#ibcon#about to read 3, iclass 30, count 0 2006.173.06:13:37.47#ibcon#read 3, iclass 30, count 0 2006.173.06:13:37.47#ibcon#about to read 4, iclass 30, count 0 2006.173.06:13:37.47#ibcon#read 4, iclass 30, count 0 2006.173.06:13:37.47#ibcon#about to read 5, iclass 30, count 0 2006.173.06:13:37.47#ibcon#read 5, iclass 30, count 0 2006.173.06:13:37.47#ibcon#about to read 6, iclass 30, count 0 2006.173.06:13:37.47#ibcon#read 6, iclass 30, count 0 2006.173.06:13:37.47#ibcon#end of sib2, iclass 30, count 0 2006.173.06:13:37.47#ibcon#*after write, iclass 30, count 0 2006.173.06:13:37.47#ibcon#*before return 0, iclass 30, count 0 2006.173.06:13:37.47#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.06:13:37.47#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.06:13:37.47#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.06:13:37.47#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.06:13:37.47$vck44/va=5,4 2006.173.06:13:37.47#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.173.06:13:37.47#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.173.06:13:37.47#ibcon#ireg 11 cls_cnt 2 2006.173.06:13:37.47#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.06:13:37.53#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.06:13:37.53#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.06:13:37.53#ibcon#enter wrdev, iclass 32, count 2 2006.173.06:13:37.53#ibcon#first serial, iclass 32, count 2 2006.173.06:13:37.53#ibcon#enter sib2, iclass 32, count 2 2006.173.06:13:37.53#ibcon#flushed, iclass 32, count 2 2006.173.06:13:37.53#ibcon#about to write, iclass 32, count 2 2006.173.06:13:37.53#ibcon#wrote, iclass 32, count 2 2006.173.06:13:37.53#ibcon#about to read 3, iclass 32, count 2 2006.173.06:13:37.55#ibcon#read 3, iclass 32, count 2 2006.173.06:13:37.55#ibcon#about to read 4, iclass 32, count 2 2006.173.06:13:37.55#ibcon#read 4, iclass 32, count 2 2006.173.06:13:37.55#ibcon#about to read 5, iclass 32, count 2 2006.173.06:13:37.55#ibcon#read 5, iclass 32, count 2 2006.173.06:13:37.55#ibcon#about to read 6, iclass 32, count 2 2006.173.06:13:37.55#ibcon#read 6, iclass 32, count 2 2006.173.06:13:37.55#ibcon#end of sib2, iclass 32, count 2 2006.173.06:13:37.55#ibcon#*mode == 0, iclass 32, count 2 2006.173.06:13:37.55#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.173.06:13:37.55#ibcon#[25=AT05-04\r\n] 2006.173.06:13:37.55#ibcon#*before write, iclass 32, count 2 2006.173.06:13:37.55#ibcon#enter sib2, iclass 32, count 2 2006.173.06:13:37.55#ibcon#flushed, iclass 32, count 2 2006.173.06:13:37.55#ibcon#about to write, iclass 32, count 2 2006.173.06:13:37.55#ibcon#wrote, iclass 32, count 2 2006.173.06:13:37.55#ibcon#about to read 3, iclass 32, count 2 2006.173.06:13:37.58#ibcon#read 3, iclass 32, count 2 2006.173.06:13:37.58#ibcon#about to read 4, iclass 32, count 2 2006.173.06:13:37.58#ibcon#read 4, iclass 32, count 2 2006.173.06:13:37.58#ibcon#about to read 5, iclass 32, count 2 2006.173.06:13:37.58#ibcon#read 5, iclass 32, count 2 2006.173.06:13:37.58#ibcon#about to read 6, iclass 32, count 2 2006.173.06:13:37.58#ibcon#read 6, iclass 32, count 2 2006.173.06:13:37.58#ibcon#end of sib2, iclass 32, count 2 2006.173.06:13:37.58#ibcon#*after write, iclass 32, count 2 2006.173.06:13:37.58#ibcon#*before return 0, iclass 32, count 2 2006.173.06:13:37.58#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.06:13:37.58#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.173.06:13:37.58#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.173.06:13:37.58#ibcon#ireg 7 cls_cnt 0 2006.173.06:13:37.58#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.06:13:37.70#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.06:13:37.70#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.06:13:37.70#ibcon#enter wrdev, iclass 32, count 0 2006.173.06:13:37.70#ibcon#first serial, iclass 32, count 0 2006.173.06:13:37.70#ibcon#enter sib2, iclass 32, count 0 2006.173.06:13:37.70#ibcon#flushed, iclass 32, count 0 2006.173.06:13:37.70#ibcon#about to write, iclass 32, count 0 2006.173.06:13:37.70#ibcon#wrote, iclass 32, count 0 2006.173.06:13:37.70#ibcon#about to read 3, iclass 32, count 0 2006.173.06:13:37.72#ibcon#read 3, iclass 32, count 0 2006.173.06:13:37.72#ibcon#about to read 4, iclass 32, count 0 2006.173.06:13:37.72#ibcon#read 4, iclass 32, count 0 2006.173.06:13:37.72#ibcon#about to read 5, iclass 32, count 0 2006.173.06:13:37.72#ibcon#read 5, iclass 32, count 0 2006.173.06:13:37.72#ibcon#about to read 6, iclass 32, count 0 2006.173.06:13:37.72#ibcon#read 6, iclass 32, count 0 2006.173.06:13:37.72#ibcon#end of sib2, iclass 32, count 0 2006.173.06:13:37.72#ibcon#*mode == 0, iclass 32, count 0 2006.173.06:13:37.72#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.06:13:37.72#ibcon#[25=USB\r\n] 2006.173.06:13:37.72#ibcon#*before write, iclass 32, count 0 2006.173.06:13:37.72#ibcon#enter sib2, iclass 32, count 0 2006.173.06:13:37.72#ibcon#flushed, iclass 32, count 0 2006.173.06:13:37.72#ibcon#about to write, iclass 32, count 0 2006.173.06:13:37.72#ibcon#wrote, iclass 32, count 0 2006.173.06:13:37.72#ibcon#about to read 3, iclass 32, count 0 2006.173.06:13:37.75#ibcon#read 3, iclass 32, count 0 2006.173.06:13:37.75#ibcon#about to read 4, iclass 32, count 0 2006.173.06:13:37.75#ibcon#read 4, iclass 32, count 0 2006.173.06:13:37.75#ibcon#about to read 5, iclass 32, count 0 2006.173.06:13:37.75#ibcon#read 5, iclass 32, count 0 2006.173.06:13:37.75#ibcon#about to read 6, iclass 32, count 0 2006.173.06:13:37.75#ibcon#read 6, iclass 32, count 0 2006.173.06:13:37.75#ibcon#end of sib2, iclass 32, count 0 2006.173.06:13:37.75#ibcon#*after write, iclass 32, count 0 2006.173.06:13:37.75#ibcon#*before return 0, iclass 32, count 0 2006.173.06:13:37.75#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.06:13:37.75#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.173.06:13:37.75#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.06:13:37.75#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.06:13:37.75$vck44/valo=6,814.99 2006.173.06:13:37.75#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.06:13:37.75#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.06:13:37.75#ibcon#ireg 17 cls_cnt 0 2006.173.06:13:37.75#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.06:13:37.75#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.06:13:37.75#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.06:13:37.75#ibcon#enter wrdev, iclass 34, count 0 2006.173.06:13:37.75#ibcon#first serial, iclass 34, count 0 2006.173.06:13:37.75#ibcon#enter sib2, iclass 34, count 0 2006.173.06:13:37.75#ibcon#flushed, iclass 34, count 0 2006.173.06:13:37.75#ibcon#about to write, iclass 34, count 0 2006.173.06:13:37.75#ibcon#wrote, iclass 34, count 0 2006.173.06:13:37.75#ibcon#about to read 3, iclass 34, count 0 2006.173.06:13:37.77#ibcon#read 3, iclass 34, count 0 2006.173.06:13:37.77#ibcon#about to read 4, iclass 34, count 0 2006.173.06:13:37.77#ibcon#read 4, iclass 34, count 0 2006.173.06:13:37.77#ibcon#about to read 5, iclass 34, count 0 2006.173.06:13:37.77#ibcon#read 5, iclass 34, count 0 2006.173.06:13:37.77#ibcon#about to read 6, iclass 34, count 0 2006.173.06:13:37.77#ibcon#read 6, iclass 34, count 0 2006.173.06:13:37.77#ibcon#end of sib2, iclass 34, count 0 2006.173.06:13:37.77#ibcon#*mode == 0, iclass 34, count 0 2006.173.06:13:37.77#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.06:13:37.77#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.06:13:37.77#ibcon#*before write, iclass 34, count 0 2006.173.06:13:37.77#ibcon#enter sib2, iclass 34, count 0 2006.173.06:13:37.77#ibcon#flushed, iclass 34, count 0 2006.173.06:13:37.77#ibcon#about to write, iclass 34, count 0 2006.173.06:13:37.77#ibcon#wrote, iclass 34, count 0 2006.173.06:13:37.77#ibcon#about to read 3, iclass 34, count 0 2006.173.06:13:37.81#ibcon#read 3, iclass 34, count 0 2006.173.06:13:37.81#ibcon#about to read 4, iclass 34, count 0 2006.173.06:13:37.81#ibcon#read 4, iclass 34, count 0 2006.173.06:13:37.81#ibcon#about to read 5, iclass 34, count 0 2006.173.06:13:37.81#ibcon#read 5, iclass 34, count 0 2006.173.06:13:37.81#ibcon#about to read 6, iclass 34, count 0 2006.173.06:13:37.81#ibcon#read 6, iclass 34, count 0 2006.173.06:13:37.81#ibcon#end of sib2, iclass 34, count 0 2006.173.06:13:37.81#ibcon#*after write, iclass 34, count 0 2006.173.06:13:37.81#ibcon#*before return 0, iclass 34, count 0 2006.173.06:13:37.81#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.06:13:37.81#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.06:13:37.81#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.06:13:37.81#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.06:13:37.81$vck44/va=6,3 2006.173.06:13:37.81#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.06:13:37.81#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.06:13:37.81#ibcon#ireg 11 cls_cnt 2 2006.173.06:13:37.81#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.06:13:37.87#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.06:13:37.87#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.06:13:37.87#ibcon#enter wrdev, iclass 36, count 2 2006.173.06:13:37.87#ibcon#first serial, iclass 36, count 2 2006.173.06:13:37.87#ibcon#enter sib2, iclass 36, count 2 2006.173.06:13:37.87#ibcon#flushed, iclass 36, count 2 2006.173.06:13:37.87#ibcon#about to write, iclass 36, count 2 2006.173.06:13:37.87#ibcon#wrote, iclass 36, count 2 2006.173.06:13:37.87#ibcon#about to read 3, iclass 36, count 2 2006.173.06:13:37.89#ibcon#read 3, iclass 36, count 2 2006.173.06:13:37.89#ibcon#about to read 4, iclass 36, count 2 2006.173.06:13:37.89#ibcon#read 4, iclass 36, count 2 2006.173.06:13:37.89#ibcon#about to read 5, iclass 36, count 2 2006.173.06:13:37.89#ibcon#read 5, iclass 36, count 2 2006.173.06:13:37.89#ibcon#about to read 6, iclass 36, count 2 2006.173.06:13:37.89#ibcon#read 6, iclass 36, count 2 2006.173.06:13:37.89#ibcon#end of sib2, iclass 36, count 2 2006.173.06:13:37.89#ibcon#*mode == 0, iclass 36, count 2 2006.173.06:13:37.89#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.06:13:37.89#ibcon#[25=AT06-03\r\n] 2006.173.06:13:37.89#ibcon#*before write, iclass 36, count 2 2006.173.06:13:37.89#ibcon#enter sib2, iclass 36, count 2 2006.173.06:13:37.89#ibcon#flushed, iclass 36, count 2 2006.173.06:13:37.89#ibcon#about to write, iclass 36, count 2 2006.173.06:13:37.89#ibcon#wrote, iclass 36, count 2 2006.173.06:13:37.89#ibcon#about to read 3, iclass 36, count 2 2006.173.06:13:37.92#ibcon#read 3, iclass 36, count 2 2006.173.06:13:37.92#ibcon#about to read 4, iclass 36, count 2 2006.173.06:13:37.92#ibcon#read 4, iclass 36, count 2 2006.173.06:13:37.92#ibcon#about to read 5, iclass 36, count 2 2006.173.06:13:37.92#ibcon#read 5, iclass 36, count 2 2006.173.06:13:37.92#ibcon#about to read 6, iclass 36, count 2 2006.173.06:13:37.92#ibcon#read 6, iclass 36, count 2 2006.173.06:13:37.92#ibcon#end of sib2, iclass 36, count 2 2006.173.06:13:37.92#ibcon#*after write, iclass 36, count 2 2006.173.06:13:37.92#ibcon#*before return 0, iclass 36, count 2 2006.173.06:13:37.92#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.06:13:37.92#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.06:13:37.92#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.06:13:37.92#ibcon#ireg 7 cls_cnt 0 2006.173.06:13:37.92#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.06:13:38.04#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.06:13:38.04#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.06:13:38.04#ibcon#enter wrdev, iclass 36, count 0 2006.173.06:13:38.04#ibcon#first serial, iclass 36, count 0 2006.173.06:13:38.04#ibcon#enter sib2, iclass 36, count 0 2006.173.06:13:38.04#ibcon#flushed, iclass 36, count 0 2006.173.06:13:38.04#ibcon#about to write, iclass 36, count 0 2006.173.06:13:38.04#ibcon#wrote, iclass 36, count 0 2006.173.06:13:38.04#ibcon#about to read 3, iclass 36, count 0 2006.173.06:13:38.06#ibcon#read 3, iclass 36, count 0 2006.173.06:13:38.06#ibcon#about to read 4, iclass 36, count 0 2006.173.06:13:38.06#ibcon#read 4, iclass 36, count 0 2006.173.06:13:38.06#ibcon#about to read 5, iclass 36, count 0 2006.173.06:13:38.06#ibcon#read 5, iclass 36, count 0 2006.173.06:13:38.06#ibcon#about to read 6, iclass 36, count 0 2006.173.06:13:38.06#ibcon#read 6, iclass 36, count 0 2006.173.06:13:38.06#ibcon#end of sib2, iclass 36, count 0 2006.173.06:13:38.06#ibcon#*mode == 0, iclass 36, count 0 2006.173.06:13:38.06#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.06:13:38.06#ibcon#[25=USB\r\n] 2006.173.06:13:38.06#ibcon#*before write, iclass 36, count 0 2006.173.06:13:38.06#ibcon#enter sib2, iclass 36, count 0 2006.173.06:13:38.06#ibcon#flushed, iclass 36, count 0 2006.173.06:13:38.06#ibcon#about to write, iclass 36, count 0 2006.173.06:13:38.06#ibcon#wrote, iclass 36, count 0 2006.173.06:13:38.06#ibcon#about to read 3, iclass 36, count 0 2006.173.06:13:38.09#ibcon#read 3, iclass 36, count 0 2006.173.06:13:38.09#ibcon#about to read 4, iclass 36, count 0 2006.173.06:13:38.09#ibcon#read 4, iclass 36, count 0 2006.173.06:13:38.09#ibcon#about to read 5, iclass 36, count 0 2006.173.06:13:38.09#ibcon#read 5, iclass 36, count 0 2006.173.06:13:38.09#ibcon#about to read 6, iclass 36, count 0 2006.173.06:13:38.09#ibcon#read 6, iclass 36, count 0 2006.173.06:13:38.09#ibcon#end of sib2, iclass 36, count 0 2006.173.06:13:38.09#ibcon#*after write, iclass 36, count 0 2006.173.06:13:38.09#ibcon#*before return 0, iclass 36, count 0 2006.173.06:13:38.09#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.06:13:38.09#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.06:13:38.09#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.06:13:38.09#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.06:13:38.09$vck44/valo=7,864.99 2006.173.06:13:38.09#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.06:13:38.09#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.06:13:38.09#ibcon#ireg 17 cls_cnt 0 2006.173.06:13:38.09#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.06:13:38.09#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.06:13:38.09#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.06:13:38.09#ibcon#enter wrdev, iclass 38, count 0 2006.173.06:13:38.09#ibcon#first serial, iclass 38, count 0 2006.173.06:13:38.09#ibcon#enter sib2, iclass 38, count 0 2006.173.06:13:38.09#ibcon#flushed, iclass 38, count 0 2006.173.06:13:38.09#ibcon#about to write, iclass 38, count 0 2006.173.06:13:38.09#ibcon#wrote, iclass 38, count 0 2006.173.06:13:38.09#ibcon#about to read 3, iclass 38, count 0 2006.173.06:13:38.11#ibcon#read 3, iclass 38, count 0 2006.173.06:13:38.11#ibcon#about to read 4, iclass 38, count 0 2006.173.06:13:38.11#ibcon#read 4, iclass 38, count 0 2006.173.06:13:38.11#ibcon#about to read 5, iclass 38, count 0 2006.173.06:13:38.11#ibcon#read 5, iclass 38, count 0 2006.173.06:13:38.11#ibcon#about to read 6, iclass 38, count 0 2006.173.06:13:38.11#ibcon#read 6, iclass 38, count 0 2006.173.06:13:38.11#ibcon#end of sib2, iclass 38, count 0 2006.173.06:13:38.11#ibcon#*mode == 0, iclass 38, count 0 2006.173.06:13:38.11#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.06:13:38.11#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.06:13:38.11#ibcon#*before write, iclass 38, count 0 2006.173.06:13:38.11#ibcon#enter sib2, iclass 38, count 0 2006.173.06:13:38.11#ibcon#flushed, iclass 38, count 0 2006.173.06:13:38.11#ibcon#about to write, iclass 38, count 0 2006.173.06:13:38.11#ibcon#wrote, iclass 38, count 0 2006.173.06:13:38.11#ibcon#about to read 3, iclass 38, count 0 2006.173.06:13:38.15#ibcon#read 3, iclass 38, count 0 2006.173.06:13:38.15#ibcon#about to read 4, iclass 38, count 0 2006.173.06:13:38.15#ibcon#read 4, iclass 38, count 0 2006.173.06:13:38.15#ibcon#about to read 5, iclass 38, count 0 2006.173.06:13:38.15#ibcon#read 5, iclass 38, count 0 2006.173.06:13:38.15#ibcon#about to read 6, iclass 38, count 0 2006.173.06:13:38.15#ibcon#read 6, iclass 38, count 0 2006.173.06:13:38.15#ibcon#end of sib2, iclass 38, count 0 2006.173.06:13:38.15#ibcon#*after write, iclass 38, count 0 2006.173.06:13:38.15#ibcon#*before return 0, iclass 38, count 0 2006.173.06:13:38.15#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.06:13:38.15#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.06:13:38.15#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.06:13:38.15#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.06:13:38.15$vck44/va=7,4 2006.173.06:13:38.15#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.06:13:38.15#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.06:13:38.15#ibcon#ireg 11 cls_cnt 2 2006.173.06:13:38.15#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.06:13:38.21#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.06:13:38.21#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.06:13:38.21#ibcon#enter wrdev, iclass 40, count 2 2006.173.06:13:38.21#ibcon#first serial, iclass 40, count 2 2006.173.06:13:38.21#ibcon#enter sib2, iclass 40, count 2 2006.173.06:13:38.21#ibcon#flushed, iclass 40, count 2 2006.173.06:13:38.21#ibcon#about to write, iclass 40, count 2 2006.173.06:13:38.21#ibcon#wrote, iclass 40, count 2 2006.173.06:13:38.21#ibcon#about to read 3, iclass 40, count 2 2006.173.06:13:38.23#ibcon#read 3, iclass 40, count 2 2006.173.06:13:38.23#ibcon#about to read 4, iclass 40, count 2 2006.173.06:13:38.23#ibcon#read 4, iclass 40, count 2 2006.173.06:13:38.23#ibcon#about to read 5, iclass 40, count 2 2006.173.06:13:38.23#ibcon#read 5, iclass 40, count 2 2006.173.06:13:38.23#ibcon#about to read 6, iclass 40, count 2 2006.173.06:13:38.23#ibcon#read 6, iclass 40, count 2 2006.173.06:13:38.23#ibcon#end of sib2, iclass 40, count 2 2006.173.06:13:38.23#ibcon#*mode == 0, iclass 40, count 2 2006.173.06:13:38.23#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.06:13:38.23#ibcon#[25=AT07-04\r\n] 2006.173.06:13:38.23#ibcon#*before write, iclass 40, count 2 2006.173.06:13:38.23#ibcon#enter sib2, iclass 40, count 2 2006.173.06:13:38.23#ibcon#flushed, iclass 40, count 2 2006.173.06:13:38.23#ibcon#about to write, iclass 40, count 2 2006.173.06:13:38.23#ibcon#wrote, iclass 40, count 2 2006.173.06:13:38.23#ibcon#about to read 3, iclass 40, count 2 2006.173.06:13:38.26#ibcon#read 3, iclass 40, count 2 2006.173.06:13:38.26#ibcon#about to read 4, iclass 40, count 2 2006.173.06:13:38.26#ibcon#read 4, iclass 40, count 2 2006.173.06:13:38.26#ibcon#about to read 5, iclass 40, count 2 2006.173.06:13:38.26#ibcon#read 5, iclass 40, count 2 2006.173.06:13:38.26#ibcon#about to read 6, iclass 40, count 2 2006.173.06:13:38.26#ibcon#read 6, iclass 40, count 2 2006.173.06:13:38.26#ibcon#end of sib2, iclass 40, count 2 2006.173.06:13:38.26#ibcon#*after write, iclass 40, count 2 2006.173.06:13:38.26#ibcon#*before return 0, iclass 40, count 2 2006.173.06:13:38.26#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.06:13:38.26#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.06:13:38.26#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.06:13:38.26#ibcon#ireg 7 cls_cnt 0 2006.173.06:13:38.26#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.06:13:38.38#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.06:13:38.38#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.06:13:38.38#ibcon#enter wrdev, iclass 40, count 0 2006.173.06:13:38.38#ibcon#first serial, iclass 40, count 0 2006.173.06:13:38.38#ibcon#enter sib2, iclass 40, count 0 2006.173.06:13:38.38#ibcon#flushed, iclass 40, count 0 2006.173.06:13:38.38#ibcon#about to write, iclass 40, count 0 2006.173.06:13:38.38#ibcon#wrote, iclass 40, count 0 2006.173.06:13:38.38#ibcon#about to read 3, iclass 40, count 0 2006.173.06:13:38.40#ibcon#read 3, iclass 40, count 0 2006.173.06:13:38.40#ibcon#about to read 4, iclass 40, count 0 2006.173.06:13:38.40#ibcon#read 4, iclass 40, count 0 2006.173.06:13:38.40#ibcon#about to read 5, iclass 40, count 0 2006.173.06:13:38.40#ibcon#read 5, iclass 40, count 0 2006.173.06:13:38.40#ibcon#about to read 6, iclass 40, count 0 2006.173.06:13:38.40#ibcon#read 6, iclass 40, count 0 2006.173.06:13:38.40#ibcon#end of sib2, iclass 40, count 0 2006.173.06:13:38.40#ibcon#*mode == 0, iclass 40, count 0 2006.173.06:13:38.40#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.06:13:38.40#ibcon#[25=USB\r\n] 2006.173.06:13:38.40#ibcon#*before write, iclass 40, count 0 2006.173.06:13:38.40#ibcon#enter sib2, iclass 40, count 0 2006.173.06:13:38.40#ibcon#flushed, iclass 40, count 0 2006.173.06:13:38.40#ibcon#about to write, iclass 40, count 0 2006.173.06:13:38.40#ibcon#wrote, iclass 40, count 0 2006.173.06:13:38.40#ibcon#about to read 3, iclass 40, count 0 2006.173.06:13:38.43#ibcon#read 3, iclass 40, count 0 2006.173.06:13:38.43#ibcon#about to read 4, iclass 40, count 0 2006.173.06:13:38.43#ibcon#read 4, iclass 40, count 0 2006.173.06:13:38.43#ibcon#about to read 5, iclass 40, count 0 2006.173.06:13:38.43#ibcon#read 5, iclass 40, count 0 2006.173.06:13:38.43#ibcon#about to read 6, iclass 40, count 0 2006.173.06:13:38.43#ibcon#read 6, iclass 40, count 0 2006.173.06:13:38.43#ibcon#end of sib2, iclass 40, count 0 2006.173.06:13:38.43#ibcon#*after write, iclass 40, count 0 2006.173.06:13:38.43#ibcon#*before return 0, iclass 40, count 0 2006.173.06:13:38.43#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.06:13:38.43#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.06:13:38.43#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.06:13:38.43#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.06:13:38.43$vck44/valo=8,884.99 2006.173.06:13:38.43#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.06:13:38.43#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.06:13:38.43#ibcon#ireg 17 cls_cnt 0 2006.173.06:13:38.43#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.06:13:38.43#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.06:13:38.43#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.06:13:38.43#ibcon#enter wrdev, iclass 4, count 0 2006.173.06:13:38.43#ibcon#first serial, iclass 4, count 0 2006.173.06:13:38.43#ibcon#enter sib2, iclass 4, count 0 2006.173.06:13:38.43#ibcon#flushed, iclass 4, count 0 2006.173.06:13:38.43#ibcon#about to write, iclass 4, count 0 2006.173.06:13:38.43#ibcon#wrote, iclass 4, count 0 2006.173.06:13:38.43#ibcon#about to read 3, iclass 4, count 0 2006.173.06:13:38.45#ibcon#read 3, iclass 4, count 0 2006.173.06:13:38.45#ibcon#about to read 4, iclass 4, count 0 2006.173.06:13:38.45#ibcon#read 4, iclass 4, count 0 2006.173.06:13:38.45#ibcon#about to read 5, iclass 4, count 0 2006.173.06:13:38.45#ibcon#read 5, iclass 4, count 0 2006.173.06:13:38.45#ibcon#about to read 6, iclass 4, count 0 2006.173.06:13:38.45#ibcon#read 6, iclass 4, count 0 2006.173.06:13:38.45#ibcon#end of sib2, iclass 4, count 0 2006.173.06:13:38.45#ibcon#*mode == 0, iclass 4, count 0 2006.173.06:13:38.45#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.06:13:38.45#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.06:13:38.45#ibcon#*before write, iclass 4, count 0 2006.173.06:13:38.45#ibcon#enter sib2, iclass 4, count 0 2006.173.06:13:38.45#ibcon#flushed, iclass 4, count 0 2006.173.06:13:38.45#ibcon#about to write, iclass 4, count 0 2006.173.06:13:38.45#ibcon#wrote, iclass 4, count 0 2006.173.06:13:38.45#ibcon#about to read 3, iclass 4, count 0 2006.173.06:13:38.49#ibcon#read 3, iclass 4, count 0 2006.173.06:13:38.49#ibcon#about to read 4, iclass 4, count 0 2006.173.06:13:38.49#ibcon#read 4, iclass 4, count 0 2006.173.06:13:38.49#ibcon#about to read 5, iclass 4, count 0 2006.173.06:13:38.49#ibcon#read 5, iclass 4, count 0 2006.173.06:13:38.49#ibcon#about to read 6, iclass 4, count 0 2006.173.06:13:38.49#ibcon#read 6, iclass 4, count 0 2006.173.06:13:38.49#ibcon#end of sib2, iclass 4, count 0 2006.173.06:13:38.49#ibcon#*after write, iclass 4, count 0 2006.173.06:13:38.49#ibcon#*before return 0, iclass 4, count 0 2006.173.06:13:38.49#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.06:13:38.49#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.06:13:38.49#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.06:13:38.49#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.06:13:38.49$vck44/va=8,4 2006.173.06:13:38.49#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.06:13:38.49#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.06:13:38.49#ibcon#ireg 11 cls_cnt 2 2006.173.06:13:38.49#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.06:13:38.55#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.06:13:38.55#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.06:13:38.55#ibcon#enter wrdev, iclass 6, count 2 2006.173.06:13:38.55#ibcon#first serial, iclass 6, count 2 2006.173.06:13:38.55#ibcon#enter sib2, iclass 6, count 2 2006.173.06:13:38.55#ibcon#flushed, iclass 6, count 2 2006.173.06:13:38.55#ibcon#about to write, iclass 6, count 2 2006.173.06:13:38.55#ibcon#wrote, iclass 6, count 2 2006.173.06:13:38.55#ibcon#about to read 3, iclass 6, count 2 2006.173.06:13:38.57#ibcon#read 3, iclass 6, count 2 2006.173.06:13:38.57#ibcon#about to read 4, iclass 6, count 2 2006.173.06:13:38.57#ibcon#read 4, iclass 6, count 2 2006.173.06:13:38.57#ibcon#about to read 5, iclass 6, count 2 2006.173.06:13:38.57#ibcon#read 5, iclass 6, count 2 2006.173.06:13:38.57#ibcon#about to read 6, iclass 6, count 2 2006.173.06:13:38.57#ibcon#read 6, iclass 6, count 2 2006.173.06:13:38.57#ibcon#end of sib2, iclass 6, count 2 2006.173.06:13:38.57#ibcon#*mode == 0, iclass 6, count 2 2006.173.06:13:38.57#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.06:13:38.57#ibcon#[25=AT08-04\r\n] 2006.173.06:13:38.57#ibcon#*before write, iclass 6, count 2 2006.173.06:13:38.57#ibcon#enter sib2, iclass 6, count 2 2006.173.06:13:38.57#ibcon#flushed, iclass 6, count 2 2006.173.06:13:38.57#ibcon#about to write, iclass 6, count 2 2006.173.06:13:38.57#ibcon#wrote, iclass 6, count 2 2006.173.06:13:38.57#ibcon#about to read 3, iclass 6, count 2 2006.173.06:13:38.60#ibcon#read 3, iclass 6, count 2 2006.173.06:13:38.60#ibcon#about to read 4, iclass 6, count 2 2006.173.06:13:38.60#ibcon#read 4, iclass 6, count 2 2006.173.06:13:38.60#ibcon#about to read 5, iclass 6, count 2 2006.173.06:13:38.60#ibcon#read 5, iclass 6, count 2 2006.173.06:13:38.60#ibcon#about to read 6, iclass 6, count 2 2006.173.06:13:38.60#ibcon#read 6, iclass 6, count 2 2006.173.06:13:38.60#ibcon#end of sib2, iclass 6, count 2 2006.173.06:13:38.60#ibcon#*after write, iclass 6, count 2 2006.173.06:13:38.60#ibcon#*before return 0, iclass 6, count 2 2006.173.06:13:38.60#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.06:13:38.60#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.06:13:38.60#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.06:13:38.60#ibcon#ireg 7 cls_cnt 0 2006.173.06:13:38.60#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.06:13:38.72#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.06:13:38.72#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.06:13:38.72#ibcon#enter wrdev, iclass 6, count 0 2006.173.06:13:38.72#ibcon#first serial, iclass 6, count 0 2006.173.06:13:38.72#ibcon#enter sib2, iclass 6, count 0 2006.173.06:13:38.72#ibcon#flushed, iclass 6, count 0 2006.173.06:13:38.72#ibcon#about to write, iclass 6, count 0 2006.173.06:13:38.72#ibcon#wrote, iclass 6, count 0 2006.173.06:13:38.72#ibcon#about to read 3, iclass 6, count 0 2006.173.06:13:38.74#ibcon#read 3, iclass 6, count 0 2006.173.06:13:38.74#ibcon#about to read 4, iclass 6, count 0 2006.173.06:13:38.74#ibcon#read 4, iclass 6, count 0 2006.173.06:13:38.74#ibcon#about to read 5, iclass 6, count 0 2006.173.06:13:38.74#ibcon#read 5, iclass 6, count 0 2006.173.06:13:38.74#ibcon#about to read 6, iclass 6, count 0 2006.173.06:13:38.74#ibcon#read 6, iclass 6, count 0 2006.173.06:13:38.74#ibcon#end of sib2, iclass 6, count 0 2006.173.06:13:38.74#ibcon#*mode == 0, iclass 6, count 0 2006.173.06:13:38.74#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.06:13:38.74#ibcon#[25=USB\r\n] 2006.173.06:13:38.74#ibcon#*before write, iclass 6, count 0 2006.173.06:13:38.74#ibcon#enter sib2, iclass 6, count 0 2006.173.06:13:38.74#ibcon#flushed, iclass 6, count 0 2006.173.06:13:38.74#ibcon#about to write, iclass 6, count 0 2006.173.06:13:38.74#ibcon#wrote, iclass 6, count 0 2006.173.06:13:38.74#ibcon#about to read 3, iclass 6, count 0 2006.173.06:13:38.77#ibcon#read 3, iclass 6, count 0 2006.173.06:13:38.77#ibcon#about to read 4, iclass 6, count 0 2006.173.06:13:38.77#ibcon#read 4, iclass 6, count 0 2006.173.06:13:38.77#ibcon#about to read 5, iclass 6, count 0 2006.173.06:13:38.77#ibcon#read 5, iclass 6, count 0 2006.173.06:13:38.77#ibcon#about to read 6, iclass 6, count 0 2006.173.06:13:38.77#ibcon#read 6, iclass 6, count 0 2006.173.06:13:38.77#ibcon#end of sib2, iclass 6, count 0 2006.173.06:13:38.77#ibcon#*after write, iclass 6, count 0 2006.173.06:13:38.77#ibcon#*before return 0, iclass 6, count 0 2006.173.06:13:38.77#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.06:13:38.77#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.06:13:38.77#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.06:13:38.77#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.06:13:38.77$vck44/vblo=1,629.99 2006.173.06:13:38.77#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.06:13:38.77#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.06:13:38.77#ibcon#ireg 17 cls_cnt 0 2006.173.06:13:38.77#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.06:13:38.77#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.06:13:38.77#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.06:13:38.77#ibcon#enter wrdev, iclass 10, count 0 2006.173.06:13:38.77#ibcon#first serial, iclass 10, count 0 2006.173.06:13:38.77#ibcon#enter sib2, iclass 10, count 0 2006.173.06:13:38.77#ibcon#flushed, iclass 10, count 0 2006.173.06:13:38.77#ibcon#about to write, iclass 10, count 0 2006.173.06:13:38.77#ibcon#wrote, iclass 10, count 0 2006.173.06:13:38.77#ibcon#about to read 3, iclass 10, count 0 2006.173.06:13:38.79#ibcon#read 3, iclass 10, count 0 2006.173.06:13:38.79#ibcon#about to read 4, iclass 10, count 0 2006.173.06:13:38.79#ibcon#read 4, iclass 10, count 0 2006.173.06:13:38.79#ibcon#about to read 5, iclass 10, count 0 2006.173.06:13:38.79#ibcon#read 5, iclass 10, count 0 2006.173.06:13:38.79#ibcon#about to read 6, iclass 10, count 0 2006.173.06:13:38.79#ibcon#read 6, iclass 10, count 0 2006.173.06:13:38.79#ibcon#end of sib2, iclass 10, count 0 2006.173.06:13:38.79#ibcon#*mode == 0, iclass 10, count 0 2006.173.06:13:38.79#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.06:13:38.79#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.06:13:38.79#ibcon#*before write, iclass 10, count 0 2006.173.06:13:38.79#ibcon#enter sib2, iclass 10, count 0 2006.173.06:13:38.79#ibcon#flushed, iclass 10, count 0 2006.173.06:13:38.79#ibcon#about to write, iclass 10, count 0 2006.173.06:13:38.79#ibcon#wrote, iclass 10, count 0 2006.173.06:13:38.79#ibcon#about to read 3, iclass 10, count 0 2006.173.06:13:38.83#ibcon#read 3, iclass 10, count 0 2006.173.06:13:38.83#ibcon#about to read 4, iclass 10, count 0 2006.173.06:13:38.83#ibcon#read 4, iclass 10, count 0 2006.173.06:13:38.83#ibcon#about to read 5, iclass 10, count 0 2006.173.06:13:38.83#ibcon#read 5, iclass 10, count 0 2006.173.06:13:38.83#ibcon#about to read 6, iclass 10, count 0 2006.173.06:13:38.83#ibcon#read 6, iclass 10, count 0 2006.173.06:13:38.83#ibcon#end of sib2, iclass 10, count 0 2006.173.06:13:38.83#ibcon#*after write, iclass 10, count 0 2006.173.06:13:38.83#ibcon#*before return 0, iclass 10, count 0 2006.173.06:13:38.83#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.06:13:38.83#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.06:13:38.83#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.06:13:38.83#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.06:13:38.83$vck44/vb=1,4 2006.173.06:13:38.83#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.06:13:38.83#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.06:13:38.83#ibcon#ireg 11 cls_cnt 2 2006.173.06:13:38.83#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.06:13:38.83#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.06:13:38.83#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.06:13:38.83#ibcon#enter wrdev, iclass 12, count 2 2006.173.06:13:38.83#ibcon#first serial, iclass 12, count 2 2006.173.06:13:38.83#ibcon#enter sib2, iclass 12, count 2 2006.173.06:13:38.83#ibcon#flushed, iclass 12, count 2 2006.173.06:13:38.83#ibcon#about to write, iclass 12, count 2 2006.173.06:13:38.83#ibcon#wrote, iclass 12, count 2 2006.173.06:13:38.83#ibcon#about to read 3, iclass 12, count 2 2006.173.06:13:38.85#ibcon#read 3, iclass 12, count 2 2006.173.06:13:38.85#ibcon#about to read 4, iclass 12, count 2 2006.173.06:13:38.85#ibcon#read 4, iclass 12, count 2 2006.173.06:13:38.85#ibcon#about to read 5, iclass 12, count 2 2006.173.06:13:38.85#ibcon#read 5, iclass 12, count 2 2006.173.06:13:38.85#ibcon#about to read 6, iclass 12, count 2 2006.173.06:13:38.85#ibcon#read 6, iclass 12, count 2 2006.173.06:13:38.85#ibcon#end of sib2, iclass 12, count 2 2006.173.06:13:38.85#ibcon#*mode == 0, iclass 12, count 2 2006.173.06:13:38.85#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.06:13:38.85#ibcon#[27=AT01-04\r\n] 2006.173.06:13:38.85#ibcon#*before write, iclass 12, count 2 2006.173.06:13:38.85#ibcon#enter sib2, iclass 12, count 2 2006.173.06:13:38.85#ibcon#flushed, iclass 12, count 2 2006.173.06:13:38.85#ibcon#about to write, iclass 12, count 2 2006.173.06:13:38.85#ibcon#wrote, iclass 12, count 2 2006.173.06:13:38.85#ibcon#about to read 3, iclass 12, count 2 2006.173.06:13:38.88#ibcon#read 3, iclass 12, count 2 2006.173.06:13:38.88#ibcon#about to read 4, iclass 12, count 2 2006.173.06:13:38.88#ibcon#read 4, iclass 12, count 2 2006.173.06:13:38.88#ibcon#about to read 5, iclass 12, count 2 2006.173.06:13:38.88#ibcon#read 5, iclass 12, count 2 2006.173.06:13:38.88#ibcon#about to read 6, iclass 12, count 2 2006.173.06:13:38.88#ibcon#read 6, iclass 12, count 2 2006.173.06:13:38.88#ibcon#end of sib2, iclass 12, count 2 2006.173.06:13:38.88#ibcon#*after write, iclass 12, count 2 2006.173.06:13:38.88#ibcon#*before return 0, iclass 12, count 2 2006.173.06:13:38.88#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.06:13:38.88#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.06:13:38.88#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.06:13:38.88#ibcon#ireg 7 cls_cnt 0 2006.173.06:13:38.88#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.06:13:39.00#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.06:13:39.00#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.06:13:39.00#ibcon#enter wrdev, iclass 12, count 0 2006.173.06:13:39.00#ibcon#first serial, iclass 12, count 0 2006.173.06:13:39.00#ibcon#enter sib2, iclass 12, count 0 2006.173.06:13:39.00#ibcon#flushed, iclass 12, count 0 2006.173.06:13:39.00#ibcon#about to write, iclass 12, count 0 2006.173.06:13:39.00#ibcon#wrote, iclass 12, count 0 2006.173.06:13:39.00#ibcon#about to read 3, iclass 12, count 0 2006.173.06:13:39.02#ibcon#read 3, iclass 12, count 0 2006.173.06:13:39.02#ibcon#about to read 4, iclass 12, count 0 2006.173.06:13:39.02#ibcon#read 4, iclass 12, count 0 2006.173.06:13:39.02#ibcon#about to read 5, iclass 12, count 0 2006.173.06:13:39.02#ibcon#read 5, iclass 12, count 0 2006.173.06:13:39.02#ibcon#about to read 6, iclass 12, count 0 2006.173.06:13:39.02#ibcon#read 6, iclass 12, count 0 2006.173.06:13:39.02#ibcon#end of sib2, iclass 12, count 0 2006.173.06:13:39.02#ibcon#*mode == 0, iclass 12, count 0 2006.173.06:13:39.02#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.06:13:39.02#ibcon#[27=USB\r\n] 2006.173.06:13:39.02#ibcon#*before write, iclass 12, count 0 2006.173.06:13:39.02#ibcon#enter sib2, iclass 12, count 0 2006.173.06:13:39.02#ibcon#flushed, iclass 12, count 0 2006.173.06:13:39.02#ibcon#about to write, iclass 12, count 0 2006.173.06:13:39.02#ibcon#wrote, iclass 12, count 0 2006.173.06:13:39.02#ibcon#about to read 3, iclass 12, count 0 2006.173.06:13:39.05#ibcon#read 3, iclass 12, count 0 2006.173.06:13:39.05#ibcon#about to read 4, iclass 12, count 0 2006.173.06:13:39.05#ibcon#read 4, iclass 12, count 0 2006.173.06:13:39.05#ibcon#about to read 5, iclass 12, count 0 2006.173.06:13:39.05#ibcon#read 5, iclass 12, count 0 2006.173.06:13:39.05#ibcon#about to read 6, iclass 12, count 0 2006.173.06:13:39.05#ibcon#read 6, iclass 12, count 0 2006.173.06:13:39.05#ibcon#end of sib2, iclass 12, count 0 2006.173.06:13:39.05#ibcon#*after write, iclass 12, count 0 2006.173.06:13:39.05#ibcon#*before return 0, iclass 12, count 0 2006.173.06:13:39.05#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.06:13:39.05#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.06:13:39.05#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.06:13:39.05#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.06:13:39.05$vck44/vblo=2,634.99 2006.173.06:13:39.05#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.06:13:39.05#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.06:13:39.05#ibcon#ireg 17 cls_cnt 0 2006.173.06:13:39.05#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.06:13:39.05#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.06:13:39.05#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.06:13:39.05#ibcon#enter wrdev, iclass 14, count 0 2006.173.06:13:39.05#ibcon#first serial, iclass 14, count 0 2006.173.06:13:39.05#ibcon#enter sib2, iclass 14, count 0 2006.173.06:13:39.05#ibcon#flushed, iclass 14, count 0 2006.173.06:13:39.05#ibcon#about to write, iclass 14, count 0 2006.173.06:13:39.05#ibcon#wrote, iclass 14, count 0 2006.173.06:13:39.05#ibcon#about to read 3, iclass 14, count 0 2006.173.06:13:39.07#ibcon#read 3, iclass 14, count 0 2006.173.06:13:39.07#ibcon#about to read 4, iclass 14, count 0 2006.173.06:13:39.07#ibcon#read 4, iclass 14, count 0 2006.173.06:13:39.07#ibcon#about to read 5, iclass 14, count 0 2006.173.06:13:39.07#ibcon#read 5, iclass 14, count 0 2006.173.06:13:39.07#ibcon#about to read 6, iclass 14, count 0 2006.173.06:13:39.07#ibcon#read 6, iclass 14, count 0 2006.173.06:13:39.07#ibcon#end of sib2, iclass 14, count 0 2006.173.06:13:39.07#ibcon#*mode == 0, iclass 14, count 0 2006.173.06:13:39.07#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.06:13:39.07#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.06:13:39.07#ibcon#*before write, iclass 14, count 0 2006.173.06:13:39.07#ibcon#enter sib2, iclass 14, count 0 2006.173.06:13:39.07#ibcon#flushed, iclass 14, count 0 2006.173.06:13:39.07#ibcon#about to write, iclass 14, count 0 2006.173.06:13:39.07#ibcon#wrote, iclass 14, count 0 2006.173.06:13:39.07#ibcon#about to read 3, iclass 14, count 0 2006.173.06:13:39.11#ibcon#read 3, iclass 14, count 0 2006.173.06:13:39.11#ibcon#about to read 4, iclass 14, count 0 2006.173.06:13:39.11#ibcon#read 4, iclass 14, count 0 2006.173.06:13:39.11#ibcon#about to read 5, iclass 14, count 0 2006.173.06:13:39.11#ibcon#read 5, iclass 14, count 0 2006.173.06:13:39.11#ibcon#about to read 6, iclass 14, count 0 2006.173.06:13:39.11#ibcon#read 6, iclass 14, count 0 2006.173.06:13:39.11#ibcon#end of sib2, iclass 14, count 0 2006.173.06:13:39.11#ibcon#*after write, iclass 14, count 0 2006.173.06:13:39.11#ibcon#*before return 0, iclass 14, count 0 2006.173.06:13:39.11#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.06:13:39.11#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.06:13:39.11#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.06:13:39.11#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.06:13:39.11$vck44/vb=2,4 2006.173.06:13:39.11#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.06:13:39.11#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.06:13:39.11#ibcon#ireg 11 cls_cnt 2 2006.173.06:13:39.11#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.06:13:39.17#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.06:13:39.17#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.06:13:39.17#ibcon#enter wrdev, iclass 16, count 2 2006.173.06:13:39.17#ibcon#first serial, iclass 16, count 2 2006.173.06:13:39.17#ibcon#enter sib2, iclass 16, count 2 2006.173.06:13:39.17#ibcon#flushed, iclass 16, count 2 2006.173.06:13:39.17#ibcon#about to write, iclass 16, count 2 2006.173.06:13:39.17#ibcon#wrote, iclass 16, count 2 2006.173.06:13:39.17#ibcon#about to read 3, iclass 16, count 2 2006.173.06:13:39.19#ibcon#read 3, iclass 16, count 2 2006.173.06:13:39.19#ibcon#about to read 4, iclass 16, count 2 2006.173.06:13:39.19#ibcon#read 4, iclass 16, count 2 2006.173.06:13:39.19#ibcon#about to read 5, iclass 16, count 2 2006.173.06:13:39.19#ibcon#read 5, iclass 16, count 2 2006.173.06:13:39.19#ibcon#about to read 6, iclass 16, count 2 2006.173.06:13:39.19#ibcon#read 6, iclass 16, count 2 2006.173.06:13:39.19#ibcon#end of sib2, iclass 16, count 2 2006.173.06:13:39.19#ibcon#*mode == 0, iclass 16, count 2 2006.173.06:13:39.19#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.06:13:39.19#ibcon#[27=AT02-04\r\n] 2006.173.06:13:39.19#ibcon#*before write, iclass 16, count 2 2006.173.06:13:39.19#ibcon#enter sib2, iclass 16, count 2 2006.173.06:13:39.19#ibcon#flushed, iclass 16, count 2 2006.173.06:13:39.19#ibcon#about to write, iclass 16, count 2 2006.173.06:13:39.19#ibcon#wrote, iclass 16, count 2 2006.173.06:13:39.19#ibcon#about to read 3, iclass 16, count 2 2006.173.06:13:39.22#ibcon#read 3, iclass 16, count 2 2006.173.06:13:39.22#ibcon#about to read 4, iclass 16, count 2 2006.173.06:13:39.22#ibcon#read 4, iclass 16, count 2 2006.173.06:13:39.22#ibcon#about to read 5, iclass 16, count 2 2006.173.06:13:39.22#ibcon#read 5, iclass 16, count 2 2006.173.06:13:39.22#ibcon#about to read 6, iclass 16, count 2 2006.173.06:13:39.22#ibcon#read 6, iclass 16, count 2 2006.173.06:13:39.22#ibcon#end of sib2, iclass 16, count 2 2006.173.06:13:39.22#ibcon#*after write, iclass 16, count 2 2006.173.06:13:39.22#ibcon#*before return 0, iclass 16, count 2 2006.173.06:13:39.22#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.06:13:39.22#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.06:13:39.22#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.06:13:39.22#ibcon#ireg 7 cls_cnt 0 2006.173.06:13:39.22#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.06:13:39.34#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.06:13:39.34#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.06:13:39.34#ibcon#enter wrdev, iclass 16, count 0 2006.173.06:13:39.34#ibcon#first serial, iclass 16, count 0 2006.173.06:13:39.34#ibcon#enter sib2, iclass 16, count 0 2006.173.06:13:39.34#ibcon#flushed, iclass 16, count 0 2006.173.06:13:39.34#ibcon#about to write, iclass 16, count 0 2006.173.06:13:39.34#ibcon#wrote, iclass 16, count 0 2006.173.06:13:39.34#ibcon#about to read 3, iclass 16, count 0 2006.173.06:13:39.36#ibcon#read 3, iclass 16, count 0 2006.173.06:13:39.36#ibcon#about to read 4, iclass 16, count 0 2006.173.06:13:39.36#ibcon#read 4, iclass 16, count 0 2006.173.06:13:39.36#ibcon#about to read 5, iclass 16, count 0 2006.173.06:13:39.36#ibcon#read 5, iclass 16, count 0 2006.173.06:13:39.36#ibcon#about to read 6, iclass 16, count 0 2006.173.06:13:39.36#ibcon#read 6, iclass 16, count 0 2006.173.06:13:39.36#ibcon#end of sib2, iclass 16, count 0 2006.173.06:13:39.36#ibcon#*mode == 0, iclass 16, count 0 2006.173.06:13:39.36#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.06:13:39.36#ibcon#[27=USB\r\n] 2006.173.06:13:39.36#ibcon#*before write, iclass 16, count 0 2006.173.06:13:39.36#ibcon#enter sib2, iclass 16, count 0 2006.173.06:13:39.36#ibcon#flushed, iclass 16, count 0 2006.173.06:13:39.36#ibcon#about to write, iclass 16, count 0 2006.173.06:13:39.36#ibcon#wrote, iclass 16, count 0 2006.173.06:13:39.36#ibcon#about to read 3, iclass 16, count 0 2006.173.06:13:39.39#ibcon#read 3, iclass 16, count 0 2006.173.06:13:39.39#ibcon#about to read 4, iclass 16, count 0 2006.173.06:13:39.39#ibcon#read 4, iclass 16, count 0 2006.173.06:13:39.39#ibcon#about to read 5, iclass 16, count 0 2006.173.06:13:39.39#ibcon#read 5, iclass 16, count 0 2006.173.06:13:39.39#ibcon#about to read 6, iclass 16, count 0 2006.173.06:13:39.39#ibcon#read 6, iclass 16, count 0 2006.173.06:13:39.39#ibcon#end of sib2, iclass 16, count 0 2006.173.06:13:39.39#ibcon#*after write, iclass 16, count 0 2006.173.06:13:39.39#ibcon#*before return 0, iclass 16, count 0 2006.173.06:13:39.39#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.06:13:39.39#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.06:13:39.39#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.06:13:39.39#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.06:13:39.39$vck44/vblo=3,649.99 2006.173.06:13:39.39#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.06:13:39.39#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.06:13:39.39#ibcon#ireg 17 cls_cnt 0 2006.173.06:13:39.39#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.06:13:39.39#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.06:13:39.39#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.06:13:39.39#ibcon#enter wrdev, iclass 18, count 0 2006.173.06:13:39.39#ibcon#first serial, iclass 18, count 0 2006.173.06:13:39.39#ibcon#enter sib2, iclass 18, count 0 2006.173.06:13:39.39#ibcon#flushed, iclass 18, count 0 2006.173.06:13:39.39#ibcon#about to write, iclass 18, count 0 2006.173.06:13:39.39#ibcon#wrote, iclass 18, count 0 2006.173.06:13:39.39#ibcon#about to read 3, iclass 18, count 0 2006.173.06:13:39.41#ibcon#read 3, iclass 18, count 0 2006.173.06:13:39.41#ibcon#about to read 4, iclass 18, count 0 2006.173.06:13:39.41#ibcon#read 4, iclass 18, count 0 2006.173.06:13:39.41#ibcon#about to read 5, iclass 18, count 0 2006.173.06:13:39.41#ibcon#read 5, iclass 18, count 0 2006.173.06:13:39.41#ibcon#about to read 6, iclass 18, count 0 2006.173.06:13:39.41#ibcon#read 6, iclass 18, count 0 2006.173.06:13:39.41#ibcon#end of sib2, iclass 18, count 0 2006.173.06:13:39.41#ibcon#*mode == 0, iclass 18, count 0 2006.173.06:13:39.41#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.06:13:39.41#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.06:13:39.41#ibcon#*before write, iclass 18, count 0 2006.173.06:13:39.41#ibcon#enter sib2, iclass 18, count 0 2006.173.06:13:39.41#ibcon#flushed, iclass 18, count 0 2006.173.06:13:39.41#ibcon#about to write, iclass 18, count 0 2006.173.06:13:39.41#ibcon#wrote, iclass 18, count 0 2006.173.06:13:39.41#ibcon#about to read 3, iclass 18, count 0 2006.173.06:13:39.45#ibcon#read 3, iclass 18, count 0 2006.173.06:13:39.45#ibcon#about to read 4, iclass 18, count 0 2006.173.06:13:39.45#ibcon#read 4, iclass 18, count 0 2006.173.06:13:39.45#ibcon#about to read 5, iclass 18, count 0 2006.173.06:13:39.45#ibcon#read 5, iclass 18, count 0 2006.173.06:13:39.45#ibcon#about to read 6, iclass 18, count 0 2006.173.06:13:39.45#ibcon#read 6, iclass 18, count 0 2006.173.06:13:39.45#ibcon#end of sib2, iclass 18, count 0 2006.173.06:13:39.45#ibcon#*after write, iclass 18, count 0 2006.173.06:13:39.45#ibcon#*before return 0, iclass 18, count 0 2006.173.06:13:39.45#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.06:13:39.45#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.06:13:39.45#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.06:13:39.45#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.06:13:39.45$vck44/vb=3,4 2006.173.06:13:39.45#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.06:13:39.45#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.06:13:39.45#ibcon#ireg 11 cls_cnt 2 2006.173.06:13:39.45#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.06:13:39.51#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.06:13:39.51#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.06:13:39.51#ibcon#enter wrdev, iclass 20, count 2 2006.173.06:13:39.51#ibcon#first serial, iclass 20, count 2 2006.173.06:13:39.51#ibcon#enter sib2, iclass 20, count 2 2006.173.06:13:39.51#ibcon#flushed, iclass 20, count 2 2006.173.06:13:39.51#ibcon#about to write, iclass 20, count 2 2006.173.06:13:39.51#ibcon#wrote, iclass 20, count 2 2006.173.06:13:39.51#ibcon#about to read 3, iclass 20, count 2 2006.173.06:13:39.53#ibcon#read 3, iclass 20, count 2 2006.173.06:13:39.53#ibcon#about to read 4, iclass 20, count 2 2006.173.06:13:39.53#ibcon#read 4, iclass 20, count 2 2006.173.06:13:39.53#ibcon#about to read 5, iclass 20, count 2 2006.173.06:13:39.53#ibcon#read 5, iclass 20, count 2 2006.173.06:13:39.53#ibcon#about to read 6, iclass 20, count 2 2006.173.06:13:39.53#ibcon#read 6, iclass 20, count 2 2006.173.06:13:39.53#ibcon#end of sib2, iclass 20, count 2 2006.173.06:13:39.53#ibcon#*mode == 0, iclass 20, count 2 2006.173.06:13:39.53#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.06:13:39.53#ibcon#[27=AT03-04\r\n] 2006.173.06:13:39.53#ibcon#*before write, iclass 20, count 2 2006.173.06:13:39.53#ibcon#enter sib2, iclass 20, count 2 2006.173.06:13:39.53#ibcon#flushed, iclass 20, count 2 2006.173.06:13:39.53#ibcon#about to write, iclass 20, count 2 2006.173.06:13:39.53#ibcon#wrote, iclass 20, count 2 2006.173.06:13:39.53#ibcon#about to read 3, iclass 20, count 2 2006.173.06:13:39.56#ibcon#read 3, iclass 20, count 2 2006.173.06:13:39.56#ibcon#about to read 4, iclass 20, count 2 2006.173.06:13:39.56#ibcon#read 4, iclass 20, count 2 2006.173.06:13:39.56#ibcon#about to read 5, iclass 20, count 2 2006.173.06:13:39.56#ibcon#read 5, iclass 20, count 2 2006.173.06:13:39.56#ibcon#about to read 6, iclass 20, count 2 2006.173.06:13:39.56#ibcon#read 6, iclass 20, count 2 2006.173.06:13:39.56#ibcon#end of sib2, iclass 20, count 2 2006.173.06:13:39.56#ibcon#*after write, iclass 20, count 2 2006.173.06:13:39.56#ibcon#*before return 0, iclass 20, count 2 2006.173.06:13:39.56#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.06:13:39.56#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.06:13:39.56#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.06:13:39.56#ibcon#ireg 7 cls_cnt 0 2006.173.06:13:39.56#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.06:13:39.68#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.06:13:39.68#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.06:13:39.68#ibcon#enter wrdev, iclass 20, count 0 2006.173.06:13:39.68#ibcon#first serial, iclass 20, count 0 2006.173.06:13:39.68#ibcon#enter sib2, iclass 20, count 0 2006.173.06:13:39.68#ibcon#flushed, iclass 20, count 0 2006.173.06:13:39.68#ibcon#about to write, iclass 20, count 0 2006.173.06:13:39.68#ibcon#wrote, iclass 20, count 0 2006.173.06:13:39.68#ibcon#about to read 3, iclass 20, count 0 2006.173.06:13:39.70#ibcon#read 3, iclass 20, count 0 2006.173.06:13:39.70#ibcon#about to read 4, iclass 20, count 0 2006.173.06:13:39.70#ibcon#read 4, iclass 20, count 0 2006.173.06:13:39.70#ibcon#about to read 5, iclass 20, count 0 2006.173.06:13:39.70#ibcon#read 5, iclass 20, count 0 2006.173.06:13:39.70#ibcon#about to read 6, iclass 20, count 0 2006.173.06:13:39.70#ibcon#read 6, iclass 20, count 0 2006.173.06:13:39.70#ibcon#end of sib2, iclass 20, count 0 2006.173.06:13:39.70#ibcon#*mode == 0, iclass 20, count 0 2006.173.06:13:39.70#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.06:13:39.70#ibcon#[27=USB\r\n] 2006.173.06:13:39.70#ibcon#*before write, iclass 20, count 0 2006.173.06:13:39.70#ibcon#enter sib2, iclass 20, count 0 2006.173.06:13:39.70#ibcon#flushed, iclass 20, count 0 2006.173.06:13:39.70#ibcon#about to write, iclass 20, count 0 2006.173.06:13:39.70#ibcon#wrote, iclass 20, count 0 2006.173.06:13:39.70#ibcon#about to read 3, iclass 20, count 0 2006.173.06:13:39.73#ibcon#read 3, iclass 20, count 0 2006.173.06:13:39.73#ibcon#about to read 4, iclass 20, count 0 2006.173.06:13:39.73#ibcon#read 4, iclass 20, count 0 2006.173.06:13:39.73#ibcon#about to read 5, iclass 20, count 0 2006.173.06:13:39.73#ibcon#read 5, iclass 20, count 0 2006.173.06:13:39.73#ibcon#about to read 6, iclass 20, count 0 2006.173.06:13:39.73#ibcon#read 6, iclass 20, count 0 2006.173.06:13:39.73#ibcon#end of sib2, iclass 20, count 0 2006.173.06:13:39.73#ibcon#*after write, iclass 20, count 0 2006.173.06:13:39.73#ibcon#*before return 0, iclass 20, count 0 2006.173.06:13:39.73#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.06:13:39.73#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.06:13:39.73#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.06:13:39.73#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.06:13:39.73$vck44/vblo=4,679.99 2006.173.06:13:39.73#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.06:13:39.73#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.06:13:39.73#ibcon#ireg 17 cls_cnt 0 2006.173.06:13:39.73#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.06:13:39.73#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.06:13:39.73#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.06:13:39.73#ibcon#enter wrdev, iclass 22, count 0 2006.173.06:13:39.73#ibcon#first serial, iclass 22, count 0 2006.173.06:13:39.73#ibcon#enter sib2, iclass 22, count 0 2006.173.06:13:39.73#ibcon#flushed, iclass 22, count 0 2006.173.06:13:39.73#ibcon#about to write, iclass 22, count 0 2006.173.06:13:39.73#ibcon#wrote, iclass 22, count 0 2006.173.06:13:39.73#ibcon#about to read 3, iclass 22, count 0 2006.173.06:13:39.75#ibcon#read 3, iclass 22, count 0 2006.173.06:13:39.75#ibcon#about to read 4, iclass 22, count 0 2006.173.06:13:39.75#ibcon#read 4, iclass 22, count 0 2006.173.06:13:39.75#ibcon#about to read 5, iclass 22, count 0 2006.173.06:13:39.75#ibcon#read 5, iclass 22, count 0 2006.173.06:13:39.75#ibcon#about to read 6, iclass 22, count 0 2006.173.06:13:39.75#ibcon#read 6, iclass 22, count 0 2006.173.06:13:39.75#ibcon#end of sib2, iclass 22, count 0 2006.173.06:13:39.75#ibcon#*mode == 0, iclass 22, count 0 2006.173.06:13:39.75#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.06:13:39.75#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.06:13:39.75#ibcon#*before write, iclass 22, count 0 2006.173.06:13:39.75#ibcon#enter sib2, iclass 22, count 0 2006.173.06:13:39.75#ibcon#flushed, iclass 22, count 0 2006.173.06:13:39.75#ibcon#about to write, iclass 22, count 0 2006.173.06:13:39.75#ibcon#wrote, iclass 22, count 0 2006.173.06:13:39.75#ibcon#about to read 3, iclass 22, count 0 2006.173.06:13:39.79#ibcon#read 3, iclass 22, count 0 2006.173.06:13:39.79#ibcon#about to read 4, iclass 22, count 0 2006.173.06:13:39.79#ibcon#read 4, iclass 22, count 0 2006.173.06:13:39.79#ibcon#about to read 5, iclass 22, count 0 2006.173.06:13:39.79#ibcon#read 5, iclass 22, count 0 2006.173.06:13:39.79#ibcon#about to read 6, iclass 22, count 0 2006.173.06:13:39.79#ibcon#read 6, iclass 22, count 0 2006.173.06:13:39.79#ibcon#end of sib2, iclass 22, count 0 2006.173.06:13:39.79#ibcon#*after write, iclass 22, count 0 2006.173.06:13:39.79#ibcon#*before return 0, iclass 22, count 0 2006.173.06:13:39.79#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.06:13:39.79#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.06:13:39.79#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.06:13:39.79#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.06:13:39.79$vck44/vb=4,4 2006.173.06:13:39.79#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.06:13:39.79#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.06:13:39.79#ibcon#ireg 11 cls_cnt 2 2006.173.06:13:39.79#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.06:13:39.85#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.06:13:39.85#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.06:13:39.85#ibcon#enter wrdev, iclass 24, count 2 2006.173.06:13:39.85#ibcon#first serial, iclass 24, count 2 2006.173.06:13:39.85#ibcon#enter sib2, iclass 24, count 2 2006.173.06:13:39.85#ibcon#flushed, iclass 24, count 2 2006.173.06:13:39.85#ibcon#about to write, iclass 24, count 2 2006.173.06:13:39.85#ibcon#wrote, iclass 24, count 2 2006.173.06:13:39.85#ibcon#about to read 3, iclass 24, count 2 2006.173.06:13:39.87#ibcon#read 3, iclass 24, count 2 2006.173.06:13:39.87#ibcon#about to read 4, iclass 24, count 2 2006.173.06:13:39.87#ibcon#read 4, iclass 24, count 2 2006.173.06:13:39.87#ibcon#about to read 5, iclass 24, count 2 2006.173.06:13:39.87#ibcon#read 5, iclass 24, count 2 2006.173.06:13:39.87#ibcon#about to read 6, iclass 24, count 2 2006.173.06:13:39.87#ibcon#read 6, iclass 24, count 2 2006.173.06:13:39.87#ibcon#end of sib2, iclass 24, count 2 2006.173.06:13:39.87#ibcon#*mode == 0, iclass 24, count 2 2006.173.06:13:39.87#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.06:13:39.87#ibcon#[27=AT04-04\r\n] 2006.173.06:13:39.87#ibcon#*before write, iclass 24, count 2 2006.173.06:13:39.87#ibcon#enter sib2, iclass 24, count 2 2006.173.06:13:39.87#ibcon#flushed, iclass 24, count 2 2006.173.06:13:39.87#ibcon#about to write, iclass 24, count 2 2006.173.06:13:39.87#ibcon#wrote, iclass 24, count 2 2006.173.06:13:39.87#ibcon#about to read 3, iclass 24, count 2 2006.173.06:13:39.90#ibcon#read 3, iclass 24, count 2 2006.173.06:13:39.90#ibcon#about to read 4, iclass 24, count 2 2006.173.06:13:39.90#ibcon#read 4, iclass 24, count 2 2006.173.06:13:39.90#ibcon#about to read 5, iclass 24, count 2 2006.173.06:13:39.90#ibcon#read 5, iclass 24, count 2 2006.173.06:13:39.90#ibcon#about to read 6, iclass 24, count 2 2006.173.06:13:39.90#ibcon#read 6, iclass 24, count 2 2006.173.06:13:39.90#ibcon#end of sib2, iclass 24, count 2 2006.173.06:13:39.90#ibcon#*after write, iclass 24, count 2 2006.173.06:13:39.90#ibcon#*before return 0, iclass 24, count 2 2006.173.06:13:39.90#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.06:13:39.90#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.06:13:39.90#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.06:13:39.90#ibcon#ireg 7 cls_cnt 0 2006.173.06:13:39.90#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.06:13:40.02#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.06:13:40.02#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.06:13:40.02#ibcon#enter wrdev, iclass 24, count 0 2006.173.06:13:40.02#ibcon#first serial, iclass 24, count 0 2006.173.06:13:40.02#ibcon#enter sib2, iclass 24, count 0 2006.173.06:13:40.02#ibcon#flushed, iclass 24, count 0 2006.173.06:13:40.02#ibcon#about to write, iclass 24, count 0 2006.173.06:13:40.02#ibcon#wrote, iclass 24, count 0 2006.173.06:13:40.02#ibcon#about to read 3, iclass 24, count 0 2006.173.06:13:40.04#ibcon#read 3, iclass 24, count 0 2006.173.06:13:40.04#ibcon#about to read 4, iclass 24, count 0 2006.173.06:13:40.04#ibcon#read 4, iclass 24, count 0 2006.173.06:13:40.04#ibcon#about to read 5, iclass 24, count 0 2006.173.06:13:40.04#ibcon#read 5, iclass 24, count 0 2006.173.06:13:40.04#ibcon#about to read 6, iclass 24, count 0 2006.173.06:13:40.04#ibcon#read 6, iclass 24, count 0 2006.173.06:13:40.04#ibcon#end of sib2, iclass 24, count 0 2006.173.06:13:40.04#ibcon#*mode == 0, iclass 24, count 0 2006.173.06:13:40.04#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.06:13:40.04#ibcon#[27=USB\r\n] 2006.173.06:13:40.04#ibcon#*before write, iclass 24, count 0 2006.173.06:13:40.04#ibcon#enter sib2, iclass 24, count 0 2006.173.06:13:40.04#ibcon#flushed, iclass 24, count 0 2006.173.06:13:40.04#ibcon#about to write, iclass 24, count 0 2006.173.06:13:40.04#ibcon#wrote, iclass 24, count 0 2006.173.06:13:40.04#ibcon#about to read 3, iclass 24, count 0 2006.173.06:13:40.07#ibcon#read 3, iclass 24, count 0 2006.173.06:13:40.07#ibcon#about to read 4, iclass 24, count 0 2006.173.06:13:40.07#ibcon#read 4, iclass 24, count 0 2006.173.06:13:40.07#ibcon#about to read 5, iclass 24, count 0 2006.173.06:13:40.07#ibcon#read 5, iclass 24, count 0 2006.173.06:13:40.07#ibcon#about to read 6, iclass 24, count 0 2006.173.06:13:40.07#ibcon#read 6, iclass 24, count 0 2006.173.06:13:40.07#ibcon#end of sib2, iclass 24, count 0 2006.173.06:13:40.07#ibcon#*after write, iclass 24, count 0 2006.173.06:13:40.07#ibcon#*before return 0, iclass 24, count 0 2006.173.06:13:40.07#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.06:13:40.07#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.06:13:40.07#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.06:13:40.07#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.06:13:40.07$vck44/vblo=5,709.99 2006.173.06:13:40.07#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.06:13:40.07#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.06:13:40.07#ibcon#ireg 17 cls_cnt 0 2006.173.06:13:40.07#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.06:13:40.07#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.06:13:40.07#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.06:13:40.07#ibcon#enter wrdev, iclass 26, count 0 2006.173.06:13:40.07#ibcon#first serial, iclass 26, count 0 2006.173.06:13:40.07#ibcon#enter sib2, iclass 26, count 0 2006.173.06:13:40.07#ibcon#flushed, iclass 26, count 0 2006.173.06:13:40.07#ibcon#about to write, iclass 26, count 0 2006.173.06:13:40.07#ibcon#wrote, iclass 26, count 0 2006.173.06:13:40.07#ibcon#about to read 3, iclass 26, count 0 2006.173.06:13:40.09#ibcon#read 3, iclass 26, count 0 2006.173.06:13:40.09#ibcon#about to read 4, iclass 26, count 0 2006.173.06:13:40.09#ibcon#read 4, iclass 26, count 0 2006.173.06:13:40.09#ibcon#about to read 5, iclass 26, count 0 2006.173.06:13:40.09#ibcon#read 5, iclass 26, count 0 2006.173.06:13:40.09#ibcon#about to read 6, iclass 26, count 0 2006.173.06:13:40.09#ibcon#read 6, iclass 26, count 0 2006.173.06:13:40.09#ibcon#end of sib2, iclass 26, count 0 2006.173.06:13:40.09#ibcon#*mode == 0, iclass 26, count 0 2006.173.06:13:40.09#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.06:13:40.09#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.06:13:40.09#ibcon#*before write, iclass 26, count 0 2006.173.06:13:40.09#ibcon#enter sib2, iclass 26, count 0 2006.173.06:13:40.09#ibcon#flushed, iclass 26, count 0 2006.173.06:13:40.09#ibcon#about to write, iclass 26, count 0 2006.173.06:13:40.09#ibcon#wrote, iclass 26, count 0 2006.173.06:13:40.09#ibcon#about to read 3, iclass 26, count 0 2006.173.06:13:40.13#ibcon#read 3, iclass 26, count 0 2006.173.06:13:40.13#ibcon#about to read 4, iclass 26, count 0 2006.173.06:13:40.13#ibcon#read 4, iclass 26, count 0 2006.173.06:13:40.13#ibcon#about to read 5, iclass 26, count 0 2006.173.06:13:40.13#ibcon#read 5, iclass 26, count 0 2006.173.06:13:40.13#ibcon#about to read 6, iclass 26, count 0 2006.173.06:13:40.13#ibcon#read 6, iclass 26, count 0 2006.173.06:13:40.13#ibcon#end of sib2, iclass 26, count 0 2006.173.06:13:40.13#ibcon#*after write, iclass 26, count 0 2006.173.06:13:40.13#ibcon#*before return 0, iclass 26, count 0 2006.173.06:13:40.13#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.06:13:40.13#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.06:13:40.13#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.06:13:40.13#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.06:13:40.13$vck44/vb=5,4 2006.173.06:13:40.13#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.06:13:40.13#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.06:13:40.13#ibcon#ireg 11 cls_cnt 2 2006.173.06:13:40.13#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.06:13:40.19#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.06:13:40.19#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.06:13:40.19#ibcon#enter wrdev, iclass 28, count 2 2006.173.06:13:40.19#ibcon#first serial, iclass 28, count 2 2006.173.06:13:40.19#ibcon#enter sib2, iclass 28, count 2 2006.173.06:13:40.19#ibcon#flushed, iclass 28, count 2 2006.173.06:13:40.19#ibcon#about to write, iclass 28, count 2 2006.173.06:13:40.19#ibcon#wrote, iclass 28, count 2 2006.173.06:13:40.19#ibcon#about to read 3, iclass 28, count 2 2006.173.06:13:40.21#ibcon#read 3, iclass 28, count 2 2006.173.06:13:40.21#ibcon#about to read 4, iclass 28, count 2 2006.173.06:13:40.21#ibcon#read 4, iclass 28, count 2 2006.173.06:13:40.21#ibcon#about to read 5, iclass 28, count 2 2006.173.06:13:40.21#ibcon#read 5, iclass 28, count 2 2006.173.06:13:40.21#ibcon#about to read 6, iclass 28, count 2 2006.173.06:13:40.21#ibcon#read 6, iclass 28, count 2 2006.173.06:13:40.21#ibcon#end of sib2, iclass 28, count 2 2006.173.06:13:40.21#ibcon#*mode == 0, iclass 28, count 2 2006.173.06:13:40.21#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.06:13:40.21#ibcon#[27=AT05-04\r\n] 2006.173.06:13:40.21#ibcon#*before write, iclass 28, count 2 2006.173.06:13:40.21#ibcon#enter sib2, iclass 28, count 2 2006.173.06:13:40.21#ibcon#flushed, iclass 28, count 2 2006.173.06:13:40.21#ibcon#about to write, iclass 28, count 2 2006.173.06:13:40.21#ibcon#wrote, iclass 28, count 2 2006.173.06:13:40.21#ibcon#about to read 3, iclass 28, count 2 2006.173.06:13:40.24#ibcon#read 3, iclass 28, count 2 2006.173.06:13:40.24#ibcon#about to read 4, iclass 28, count 2 2006.173.06:13:40.24#ibcon#read 4, iclass 28, count 2 2006.173.06:13:40.24#ibcon#about to read 5, iclass 28, count 2 2006.173.06:13:40.24#ibcon#read 5, iclass 28, count 2 2006.173.06:13:40.24#ibcon#about to read 6, iclass 28, count 2 2006.173.06:13:40.24#ibcon#read 6, iclass 28, count 2 2006.173.06:13:40.24#ibcon#end of sib2, iclass 28, count 2 2006.173.06:13:40.24#ibcon#*after write, iclass 28, count 2 2006.173.06:13:40.24#ibcon#*before return 0, iclass 28, count 2 2006.173.06:13:40.24#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.06:13:40.24#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.06:13:40.24#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.06:13:40.24#ibcon#ireg 7 cls_cnt 0 2006.173.06:13:40.24#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.06:13:40.36#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.06:13:40.36#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.06:13:40.36#ibcon#enter wrdev, iclass 28, count 0 2006.173.06:13:40.36#ibcon#first serial, iclass 28, count 0 2006.173.06:13:40.36#ibcon#enter sib2, iclass 28, count 0 2006.173.06:13:40.36#ibcon#flushed, iclass 28, count 0 2006.173.06:13:40.36#ibcon#about to write, iclass 28, count 0 2006.173.06:13:40.36#ibcon#wrote, iclass 28, count 0 2006.173.06:13:40.36#ibcon#about to read 3, iclass 28, count 0 2006.173.06:13:40.38#ibcon#read 3, iclass 28, count 0 2006.173.06:13:40.38#ibcon#about to read 4, iclass 28, count 0 2006.173.06:13:40.38#ibcon#read 4, iclass 28, count 0 2006.173.06:13:40.38#ibcon#about to read 5, iclass 28, count 0 2006.173.06:13:40.38#ibcon#read 5, iclass 28, count 0 2006.173.06:13:40.38#ibcon#about to read 6, iclass 28, count 0 2006.173.06:13:40.38#ibcon#read 6, iclass 28, count 0 2006.173.06:13:40.38#ibcon#end of sib2, iclass 28, count 0 2006.173.06:13:40.38#ibcon#*mode == 0, iclass 28, count 0 2006.173.06:13:40.38#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.06:13:40.38#ibcon#[27=USB\r\n] 2006.173.06:13:40.38#ibcon#*before write, iclass 28, count 0 2006.173.06:13:40.38#ibcon#enter sib2, iclass 28, count 0 2006.173.06:13:40.38#ibcon#flushed, iclass 28, count 0 2006.173.06:13:40.38#ibcon#about to write, iclass 28, count 0 2006.173.06:13:40.38#ibcon#wrote, iclass 28, count 0 2006.173.06:13:40.38#ibcon#about to read 3, iclass 28, count 0 2006.173.06:13:40.41#ibcon#read 3, iclass 28, count 0 2006.173.06:13:40.41#ibcon#about to read 4, iclass 28, count 0 2006.173.06:13:40.41#ibcon#read 4, iclass 28, count 0 2006.173.06:13:40.41#ibcon#about to read 5, iclass 28, count 0 2006.173.06:13:40.41#ibcon#read 5, iclass 28, count 0 2006.173.06:13:40.41#ibcon#about to read 6, iclass 28, count 0 2006.173.06:13:40.41#ibcon#read 6, iclass 28, count 0 2006.173.06:13:40.41#ibcon#end of sib2, iclass 28, count 0 2006.173.06:13:40.41#ibcon#*after write, iclass 28, count 0 2006.173.06:13:40.41#ibcon#*before return 0, iclass 28, count 0 2006.173.06:13:40.41#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.06:13:40.41#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.06:13:40.41#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.06:13:40.41#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.06:13:40.41$vck44/vblo=6,719.99 2006.173.06:13:40.41#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.06:13:40.41#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.06:13:40.41#ibcon#ireg 17 cls_cnt 0 2006.173.06:13:40.41#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.06:13:40.41#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.06:13:40.41#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.06:13:40.41#ibcon#enter wrdev, iclass 30, count 0 2006.173.06:13:40.41#ibcon#first serial, iclass 30, count 0 2006.173.06:13:40.41#ibcon#enter sib2, iclass 30, count 0 2006.173.06:13:40.41#ibcon#flushed, iclass 30, count 0 2006.173.06:13:40.41#ibcon#about to write, iclass 30, count 0 2006.173.06:13:40.41#ibcon#wrote, iclass 30, count 0 2006.173.06:13:40.41#ibcon#about to read 3, iclass 30, count 0 2006.173.06:13:40.43#ibcon#read 3, iclass 30, count 0 2006.173.06:13:40.43#ibcon#about to read 4, iclass 30, count 0 2006.173.06:13:40.43#ibcon#read 4, iclass 30, count 0 2006.173.06:13:40.43#ibcon#about to read 5, iclass 30, count 0 2006.173.06:13:40.43#ibcon#read 5, iclass 30, count 0 2006.173.06:13:40.43#ibcon#about to read 6, iclass 30, count 0 2006.173.06:13:40.43#ibcon#read 6, iclass 30, count 0 2006.173.06:13:40.43#ibcon#end of sib2, iclass 30, count 0 2006.173.06:13:40.43#ibcon#*mode == 0, iclass 30, count 0 2006.173.06:13:40.43#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.06:13:40.43#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.06:13:40.43#ibcon#*before write, iclass 30, count 0 2006.173.06:13:40.43#ibcon#enter sib2, iclass 30, count 0 2006.173.06:13:40.43#ibcon#flushed, iclass 30, count 0 2006.173.06:13:40.43#ibcon#about to write, iclass 30, count 0 2006.173.06:13:40.43#ibcon#wrote, iclass 30, count 0 2006.173.06:13:40.43#ibcon#about to read 3, iclass 30, count 0 2006.173.06:13:40.47#ibcon#read 3, iclass 30, count 0 2006.173.06:13:40.47#ibcon#about to read 4, iclass 30, count 0 2006.173.06:13:40.47#ibcon#read 4, iclass 30, count 0 2006.173.06:13:40.47#ibcon#about to read 5, iclass 30, count 0 2006.173.06:13:40.47#ibcon#read 5, iclass 30, count 0 2006.173.06:13:40.47#ibcon#about to read 6, iclass 30, count 0 2006.173.06:13:40.47#ibcon#read 6, iclass 30, count 0 2006.173.06:13:40.47#ibcon#end of sib2, iclass 30, count 0 2006.173.06:13:40.47#ibcon#*after write, iclass 30, count 0 2006.173.06:13:40.47#ibcon#*before return 0, iclass 30, count 0 2006.173.06:13:40.47#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.06:13:40.47#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.06:13:40.47#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.06:13:40.47#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.06:13:40.47$vck44/vb=6,4 2006.173.06:13:40.47#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.173.06:13:40.47#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.173.06:13:40.47#ibcon#ireg 11 cls_cnt 2 2006.173.06:13:40.47#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.06:13:40.53#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.06:13:40.53#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.06:13:40.53#ibcon#enter wrdev, iclass 32, count 2 2006.173.06:13:40.53#ibcon#first serial, iclass 32, count 2 2006.173.06:13:40.53#ibcon#enter sib2, iclass 32, count 2 2006.173.06:13:40.53#ibcon#flushed, iclass 32, count 2 2006.173.06:13:40.53#ibcon#about to write, iclass 32, count 2 2006.173.06:13:40.53#ibcon#wrote, iclass 32, count 2 2006.173.06:13:40.53#ibcon#about to read 3, iclass 32, count 2 2006.173.06:13:40.55#ibcon#read 3, iclass 32, count 2 2006.173.06:13:40.55#ibcon#about to read 4, iclass 32, count 2 2006.173.06:13:40.55#ibcon#read 4, iclass 32, count 2 2006.173.06:13:40.55#ibcon#about to read 5, iclass 32, count 2 2006.173.06:13:40.55#ibcon#read 5, iclass 32, count 2 2006.173.06:13:40.55#ibcon#about to read 6, iclass 32, count 2 2006.173.06:13:40.55#ibcon#read 6, iclass 32, count 2 2006.173.06:13:40.55#ibcon#end of sib2, iclass 32, count 2 2006.173.06:13:40.55#ibcon#*mode == 0, iclass 32, count 2 2006.173.06:13:40.55#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.173.06:13:40.55#ibcon#[27=AT06-04\r\n] 2006.173.06:13:40.55#ibcon#*before write, iclass 32, count 2 2006.173.06:13:40.55#ibcon#enter sib2, iclass 32, count 2 2006.173.06:13:40.55#ibcon#flushed, iclass 32, count 2 2006.173.06:13:40.55#ibcon#about to write, iclass 32, count 2 2006.173.06:13:40.55#ibcon#wrote, iclass 32, count 2 2006.173.06:13:40.55#ibcon#about to read 3, iclass 32, count 2 2006.173.06:13:40.58#ibcon#read 3, iclass 32, count 2 2006.173.06:13:40.58#ibcon#about to read 4, iclass 32, count 2 2006.173.06:13:40.58#ibcon#read 4, iclass 32, count 2 2006.173.06:13:40.58#ibcon#about to read 5, iclass 32, count 2 2006.173.06:13:40.58#ibcon#read 5, iclass 32, count 2 2006.173.06:13:40.58#ibcon#about to read 6, iclass 32, count 2 2006.173.06:13:40.58#ibcon#read 6, iclass 32, count 2 2006.173.06:13:40.58#ibcon#end of sib2, iclass 32, count 2 2006.173.06:13:40.58#ibcon#*after write, iclass 32, count 2 2006.173.06:13:40.58#ibcon#*before return 0, iclass 32, count 2 2006.173.06:13:40.58#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.06:13:40.58#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.173.06:13:40.58#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.173.06:13:40.58#ibcon#ireg 7 cls_cnt 0 2006.173.06:13:40.58#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.06:13:40.70#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.06:13:40.70#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.06:13:40.70#ibcon#enter wrdev, iclass 32, count 0 2006.173.06:13:40.70#ibcon#first serial, iclass 32, count 0 2006.173.06:13:40.70#ibcon#enter sib2, iclass 32, count 0 2006.173.06:13:40.70#ibcon#flushed, iclass 32, count 0 2006.173.06:13:40.70#ibcon#about to write, iclass 32, count 0 2006.173.06:13:40.70#ibcon#wrote, iclass 32, count 0 2006.173.06:13:40.70#ibcon#about to read 3, iclass 32, count 0 2006.173.06:13:40.72#ibcon#read 3, iclass 32, count 0 2006.173.06:13:40.72#ibcon#about to read 4, iclass 32, count 0 2006.173.06:13:40.72#ibcon#read 4, iclass 32, count 0 2006.173.06:13:40.72#ibcon#about to read 5, iclass 32, count 0 2006.173.06:13:40.72#ibcon#read 5, iclass 32, count 0 2006.173.06:13:40.72#ibcon#about to read 6, iclass 32, count 0 2006.173.06:13:40.72#ibcon#read 6, iclass 32, count 0 2006.173.06:13:40.72#ibcon#end of sib2, iclass 32, count 0 2006.173.06:13:40.72#ibcon#*mode == 0, iclass 32, count 0 2006.173.06:13:40.72#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.06:13:40.72#ibcon#[27=USB\r\n] 2006.173.06:13:40.72#ibcon#*before write, iclass 32, count 0 2006.173.06:13:40.72#ibcon#enter sib2, iclass 32, count 0 2006.173.06:13:40.72#ibcon#flushed, iclass 32, count 0 2006.173.06:13:40.72#ibcon#about to write, iclass 32, count 0 2006.173.06:13:40.72#ibcon#wrote, iclass 32, count 0 2006.173.06:13:40.72#ibcon#about to read 3, iclass 32, count 0 2006.173.06:13:40.75#ibcon#read 3, iclass 32, count 0 2006.173.06:13:40.75#ibcon#about to read 4, iclass 32, count 0 2006.173.06:13:40.75#ibcon#read 4, iclass 32, count 0 2006.173.06:13:40.75#ibcon#about to read 5, iclass 32, count 0 2006.173.06:13:40.75#ibcon#read 5, iclass 32, count 0 2006.173.06:13:40.75#ibcon#about to read 6, iclass 32, count 0 2006.173.06:13:40.75#ibcon#read 6, iclass 32, count 0 2006.173.06:13:40.75#ibcon#end of sib2, iclass 32, count 0 2006.173.06:13:40.75#ibcon#*after write, iclass 32, count 0 2006.173.06:13:40.75#ibcon#*before return 0, iclass 32, count 0 2006.173.06:13:40.75#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.06:13:40.75#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.173.06:13:40.75#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.06:13:40.75#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.06:13:40.75$vck44/vblo=7,734.99 2006.173.06:13:40.75#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.06:13:40.75#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.06:13:40.75#ibcon#ireg 17 cls_cnt 0 2006.173.06:13:40.75#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.06:13:40.75#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.06:13:40.75#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.06:13:40.75#ibcon#enter wrdev, iclass 34, count 0 2006.173.06:13:40.75#ibcon#first serial, iclass 34, count 0 2006.173.06:13:40.75#ibcon#enter sib2, iclass 34, count 0 2006.173.06:13:40.75#ibcon#flushed, iclass 34, count 0 2006.173.06:13:40.75#ibcon#about to write, iclass 34, count 0 2006.173.06:13:40.75#ibcon#wrote, iclass 34, count 0 2006.173.06:13:40.75#ibcon#about to read 3, iclass 34, count 0 2006.173.06:13:40.77#ibcon#read 3, iclass 34, count 0 2006.173.06:13:40.77#ibcon#about to read 4, iclass 34, count 0 2006.173.06:13:40.77#ibcon#read 4, iclass 34, count 0 2006.173.06:13:40.77#ibcon#about to read 5, iclass 34, count 0 2006.173.06:13:40.77#ibcon#read 5, iclass 34, count 0 2006.173.06:13:40.77#ibcon#about to read 6, iclass 34, count 0 2006.173.06:13:40.77#ibcon#read 6, iclass 34, count 0 2006.173.06:13:40.77#ibcon#end of sib2, iclass 34, count 0 2006.173.06:13:40.77#ibcon#*mode == 0, iclass 34, count 0 2006.173.06:13:40.77#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.06:13:40.77#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.06:13:40.77#ibcon#*before write, iclass 34, count 0 2006.173.06:13:40.77#ibcon#enter sib2, iclass 34, count 0 2006.173.06:13:40.77#ibcon#flushed, iclass 34, count 0 2006.173.06:13:40.77#ibcon#about to write, iclass 34, count 0 2006.173.06:13:40.77#ibcon#wrote, iclass 34, count 0 2006.173.06:13:40.77#ibcon#about to read 3, iclass 34, count 0 2006.173.06:13:40.81#ibcon#read 3, iclass 34, count 0 2006.173.06:13:40.81#ibcon#about to read 4, iclass 34, count 0 2006.173.06:13:40.81#ibcon#read 4, iclass 34, count 0 2006.173.06:13:40.81#ibcon#about to read 5, iclass 34, count 0 2006.173.06:13:40.81#ibcon#read 5, iclass 34, count 0 2006.173.06:13:40.81#ibcon#about to read 6, iclass 34, count 0 2006.173.06:13:40.81#ibcon#read 6, iclass 34, count 0 2006.173.06:13:40.81#ibcon#end of sib2, iclass 34, count 0 2006.173.06:13:40.81#ibcon#*after write, iclass 34, count 0 2006.173.06:13:40.81#ibcon#*before return 0, iclass 34, count 0 2006.173.06:13:40.81#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.06:13:40.81#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.06:13:40.81#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.06:13:40.81#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.06:13:40.81$vck44/vb=7,4 2006.173.06:13:40.81#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.06:13:40.81#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.06:13:40.81#ibcon#ireg 11 cls_cnt 2 2006.173.06:13:40.81#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.06:13:40.87#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.06:13:40.87#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.06:13:40.87#ibcon#enter wrdev, iclass 36, count 2 2006.173.06:13:40.87#ibcon#first serial, iclass 36, count 2 2006.173.06:13:40.87#ibcon#enter sib2, iclass 36, count 2 2006.173.06:13:40.87#ibcon#flushed, iclass 36, count 2 2006.173.06:13:40.87#ibcon#about to write, iclass 36, count 2 2006.173.06:13:40.87#ibcon#wrote, iclass 36, count 2 2006.173.06:13:40.87#ibcon#about to read 3, iclass 36, count 2 2006.173.06:13:40.89#ibcon#read 3, iclass 36, count 2 2006.173.06:13:40.89#ibcon#about to read 4, iclass 36, count 2 2006.173.06:13:40.89#ibcon#read 4, iclass 36, count 2 2006.173.06:13:40.89#ibcon#about to read 5, iclass 36, count 2 2006.173.06:13:40.89#ibcon#read 5, iclass 36, count 2 2006.173.06:13:40.89#ibcon#about to read 6, iclass 36, count 2 2006.173.06:13:40.89#ibcon#read 6, iclass 36, count 2 2006.173.06:13:40.89#ibcon#end of sib2, iclass 36, count 2 2006.173.06:13:40.89#ibcon#*mode == 0, iclass 36, count 2 2006.173.06:13:40.89#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.06:13:40.89#ibcon#[27=AT07-04\r\n] 2006.173.06:13:40.89#ibcon#*before write, iclass 36, count 2 2006.173.06:13:40.89#ibcon#enter sib2, iclass 36, count 2 2006.173.06:13:40.89#ibcon#flushed, iclass 36, count 2 2006.173.06:13:40.89#ibcon#about to write, iclass 36, count 2 2006.173.06:13:40.89#ibcon#wrote, iclass 36, count 2 2006.173.06:13:40.89#ibcon#about to read 3, iclass 36, count 2 2006.173.06:13:40.92#ibcon#read 3, iclass 36, count 2 2006.173.06:13:40.92#ibcon#about to read 4, iclass 36, count 2 2006.173.06:13:40.92#ibcon#read 4, iclass 36, count 2 2006.173.06:13:40.92#ibcon#about to read 5, iclass 36, count 2 2006.173.06:13:40.92#ibcon#read 5, iclass 36, count 2 2006.173.06:13:40.92#ibcon#about to read 6, iclass 36, count 2 2006.173.06:13:40.92#ibcon#read 6, iclass 36, count 2 2006.173.06:13:40.92#ibcon#end of sib2, iclass 36, count 2 2006.173.06:13:40.92#ibcon#*after write, iclass 36, count 2 2006.173.06:13:40.92#ibcon#*before return 0, iclass 36, count 2 2006.173.06:13:40.92#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.06:13:40.92#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.06:13:40.92#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.06:13:40.92#ibcon#ireg 7 cls_cnt 0 2006.173.06:13:40.92#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.06:13:41.04#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.06:13:41.04#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.06:13:41.04#ibcon#enter wrdev, iclass 36, count 0 2006.173.06:13:41.04#ibcon#first serial, iclass 36, count 0 2006.173.06:13:41.04#ibcon#enter sib2, iclass 36, count 0 2006.173.06:13:41.04#ibcon#flushed, iclass 36, count 0 2006.173.06:13:41.04#ibcon#about to write, iclass 36, count 0 2006.173.06:13:41.04#ibcon#wrote, iclass 36, count 0 2006.173.06:13:41.04#ibcon#about to read 3, iclass 36, count 0 2006.173.06:13:41.06#ibcon#read 3, iclass 36, count 0 2006.173.06:13:41.06#ibcon#about to read 4, iclass 36, count 0 2006.173.06:13:41.06#ibcon#read 4, iclass 36, count 0 2006.173.06:13:41.06#ibcon#about to read 5, iclass 36, count 0 2006.173.06:13:41.06#ibcon#read 5, iclass 36, count 0 2006.173.06:13:41.06#ibcon#about to read 6, iclass 36, count 0 2006.173.06:13:41.06#ibcon#read 6, iclass 36, count 0 2006.173.06:13:41.06#ibcon#end of sib2, iclass 36, count 0 2006.173.06:13:41.06#ibcon#*mode == 0, iclass 36, count 0 2006.173.06:13:41.06#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.06:13:41.06#ibcon#[27=USB\r\n] 2006.173.06:13:41.06#ibcon#*before write, iclass 36, count 0 2006.173.06:13:41.06#ibcon#enter sib2, iclass 36, count 0 2006.173.06:13:41.06#ibcon#flushed, iclass 36, count 0 2006.173.06:13:41.06#ibcon#about to write, iclass 36, count 0 2006.173.06:13:41.06#ibcon#wrote, iclass 36, count 0 2006.173.06:13:41.06#ibcon#about to read 3, iclass 36, count 0 2006.173.06:13:41.09#ibcon#read 3, iclass 36, count 0 2006.173.06:13:41.09#ibcon#about to read 4, iclass 36, count 0 2006.173.06:13:41.09#ibcon#read 4, iclass 36, count 0 2006.173.06:13:41.09#ibcon#about to read 5, iclass 36, count 0 2006.173.06:13:41.09#ibcon#read 5, iclass 36, count 0 2006.173.06:13:41.09#ibcon#about to read 6, iclass 36, count 0 2006.173.06:13:41.09#ibcon#read 6, iclass 36, count 0 2006.173.06:13:41.09#ibcon#end of sib2, iclass 36, count 0 2006.173.06:13:41.09#ibcon#*after write, iclass 36, count 0 2006.173.06:13:41.09#ibcon#*before return 0, iclass 36, count 0 2006.173.06:13:41.09#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.06:13:41.09#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.06:13:41.09#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.06:13:41.09#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.06:13:41.09$vck44/vblo=8,744.99 2006.173.06:13:41.09#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.06:13:41.09#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.06:13:41.09#ibcon#ireg 17 cls_cnt 0 2006.173.06:13:41.09#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.06:13:41.09#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.06:13:41.09#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.06:13:41.09#ibcon#enter wrdev, iclass 38, count 0 2006.173.06:13:41.09#ibcon#first serial, iclass 38, count 0 2006.173.06:13:41.09#ibcon#enter sib2, iclass 38, count 0 2006.173.06:13:41.09#ibcon#flushed, iclass 38, count 0 2006.173.06:13:41.09#ibcon#about to write, iclass 38, count 0 2006.173.06:13:41.09#ibcon#wrote, iclass 38, count 0 2006.173.06:13:41.09#ibcon#about to read 3, iclass 38, count 0 2006.173.06:13:41.11#ibcon#read 3, iclass 38, count 0 2006.173.06:13:41.11#ibcon#about to read 4, iclass 38, count 0 2006.173.06:13:41.11#ibcon#read 4, iclass 38, count 0 2006.173.06:13:41.11#ibcon#about to read 5, iclass 38, count 0 2006.173.06:13:41.11#ibcon#read 5, iclass 38, count 0 2006.173.06:13:41.11#ibcon#about to read 6, iclass 38, count 0 2006.173.06:13:41.11#ibcon#read 6, iclass 38, count 0 2006.173.06:13:41.11#ibcon#end of sib2, iclass 38, count 0 2006.173.06:13:41.11#ibcon#*mode == 0, iclass 38, count 0 2006.173.06:13:41.11#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.06:13:41.11#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.06:13:41.11#ibcon#*before write, iclass 38, count 0 2006.173.06:13:41.11#ibcon#enter sib2, iclass 38, count 0 2006.173.06:13:41.11#ibcon#flushed, iclass 38, count 0 2006.173.06:13:41.11#ibcon#about to write, iclass 38, count 0 2006.173.06:13:41.11#ibcon#wrote, iclass 38, count 0 2006.173.06:13:41.11#ibcon#about to read 3, iclass 38, count 0 2006.173.06:13:41.15#ibcon#read 3, iclass 38, count 0 2006.173.06:13:41.15#ibcon#about to read 4, iclass 38, count 0 2006.173.06:13:41.15#ibcon#read 4, iclass 38, count 0 2006.173.06:13:41.15#ibcon#about to read 5, iclass 38, count 0 2006.173.06:13:41.15#ibcon#read 5, iclass 38, count 0 2006.173.06:13:41.15#ibcon#about to read 6, iclass 38, count 0 2006.173.06:13:41.15#ibcon#read 6, iclass 38, count 0 2006.173.06:13:41.15#ibcon#end of sib2, iclass 38, count 0 2006.173.06:13:41.15#ibcon#*after write, iclass 38, count 0 2006.173.06:13:41.15#ibcon#*before return 0, iclass 38, count 0 2006.173.06:13:41.15#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.06:13:41.15#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.06:13:41.15#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.06:13:41.15#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.06:13:41.15$vck44/vb=8,4 2006.173.06:13:41.15#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.06:13:41.15#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.06:13:41.15#ibcon#ireg 11 cls_cnt 2 2006.173.06:13:41.15#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.06:13:41.21#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.06:13:41.21#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.06:13:41.21#ibcon#enter wrdev, iclass 40, count 2 2006.173.06:13:41.21#ibcon#first serial, iclass 40, count 2 2006.173.06:13:41.21#ibcon#enter sib2, iclass 40, count 2 2006.173.06:13:41.21#ibcon#flushed, iclass 40, count 2 2006.173.06:13:41.21#ibcon#about to write, iclass 40, count 2 2006.173.06:13:41.21#ibcon#wrote, iclass 40, count 2 2006.173.06:13:41.21#ibcon#about to read 3, iclass 40, count 2 2006.173.06:13:41.22#abcon#<5=/01 0.6 1.0 23.87 791005.2\r\n> 2006.173.06:13:41.23#ibcon#read 3, iclass 40, count 2 2006.173.06:13:41.23#ibcon#about to read 4, iclass 40, count 2 2006.173.06:13:41.23#ibcon#read 4, iclass 40, count 2 2006.173.06:13:41.23#ibcon#about to read 5, iclass 40, count 2 2006.173.06:13:41.23#ibcon#read 5, iclass 40, count 2 2006.173.06:13:41.23#ibcon#about to read 6, iclass 40, count 2 2006.173.06:13:41.23#ibcon#read 6, iclass 40, count 2 2006.173.06:13:41.23#ibcon#end of sib2, iclass 40, count 2 2006.173.06:13:41.23#ibcon#*mode == 0, iclass 40, count 2 2006.173.06:13:41.23#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.06:13:41.23#ibcon#[27=AT08-04\r\n] 2006.173.06:13:41.23#ibcon#*before write, iclass 40, count 2 2006.173.06:13:41.23#ibcon#enter sib2, iclass 40, count 2 2006.173.06:13:41.23#ibcon#flushed, iclass 40, count 2 2006.173.06:13:41.23#ibcon#about to write, iclass 40, count 2 2006.173.06:13:41.23#ibcon#wrote, iclass 40, count 2 2006.173.06:13:41.23#ibcon#about to read 3, iclass 40, count 2 2006.173.06:13:41.24#abcon#{5=INTERFACE CLEAR} 2006.173.06:13:41.26#ibcon#read 3, iclass 40, count 2 2006.173.06:13:41.26#ibcon#about to read 4, iclass 40, count 2 2006.173.06:13:41.26#ibcon#read 4, iclass 40, count 2 2006.173.06:13:41.26#ibcon#about to read 5, iclass 40, count 2 2006.173.06:13:41.26#ibcon#read 5, iclass 40, count 2 2006.173.06:13:41.26#ibcon#about to read 6, iclass 40, count 2 2006.173.06:13:41.26#ibcon#read 6, iclass 40, count 2 2006.173.06:13:41.26#ibcon#end of sib2, iclass 40, count 2 2006.173.06:13:41.26#ibcon#*after write, iclass 40, count 2 2006.173.06:13:41.26#ibcon#*before return 0, iclass 40, count 2 2006.173.06:13:41.26#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.06:13:41.26#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.06:13:41.26#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.06:13:41.26#ibcon#ireg 7 cls_cnt 0 2006.173.06:13:41.26#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.06:13:41.30#abcon#[5=S1D000X0/0*\r\n] 2006.173.06:13:41.38#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.06:13:41.38#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.06:13:41.38#ibcon#enter wrdev, iclass 40, count 0 2006.173.06:13:41.38#ibcon#first serial, iclass 40, count 0 2006.173.06:13:41.38#ibcon#enter sib2, iclass 40, count 0 2006.173.06:13:41.38#ibcon#flushed, iclass 40, count 0 2006.173.06:13:41.38#ibcon#about to write, iclass 40, count 0 2006.173.06:13:41.38#ibcon#wrote, iclass 40, count 0 2006.173.06:13:41.38#ibcon#about to read 3, iclass 40, count 0 2006.173.06:13:41.40#ibcon#read 3, iclass 40, count 0 2006.173.06:13:41.40#ibcon#about to read 4, iclass 40, count 0 2006.173.06:13:41.40#ibcon#read 4, iclass 40, count 0 2006.173.06:13:41.40#ibcon#about to read 5, iclass 40, count 0 2006.173.06:13:41.40#ibcon#read 5, iclass 40, count 0 2006.173.06:13:41.40#ibcon#about to read 6, iclass 40, count 0 2006.173.06:13:41.40#ibcon#read 6, iclass 40, count 0 2006.173.06:13:41.40#ibcon#end of sib2, iclass 40, count 0 2006.173.06:13:41.40#ibcon#*mode == 0, iclass 40, count 0 2006.173.06:13:41.40#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.06:13:41.40#ibcon#[27=USB\r\n] 2006.173.06:13:41.40#ibcon#*before write, iclass 40, count 0 2006.173.06:13:41.40#ibcon#enter sib2, iclass 40, count 0 2006.173.06:13:41.40#ibcon#flushed, iclass 40, count 0 2006.173.06:13:41.40#ibcon#about to write, iclass 40, count 0 2006.173.06:13:41.40#ibcon#wrote, iclass 40, count 0 2006.173.06:13:41.40#ibcon#about to read 3, iclass 40, count 0 2006.173.06:13:41.43#ibcon#read 3, iclass 40, count 0 2006.173.06:13:41.43#ibcon#about to read 4, iclass 40, count 0 2006.173.06:13:41.43#ibcon#read 4, iclass 40, count 0 2006.173.06:13:41.43#ibcon#about to read 5, iclass 40, count 0 2006.173.06:13:41.43#ibcon#read 5, iclass 40, count 0 2006.173.06:13:41.43#ibcon#about to read 6, iclass 40, count 0 2006.173.06:13:41.43#ibcon#read 6, iclass 40, count 0 2006.173.06:13:41.43#ibcon#end of sib2, iclass 40, count 0 2006.173.06:13:41.43#ibcon#*after write, iclass 40, count 0 2006.173.06:13:41.43#ibcon#*before return 0, iclass 40, count 0 2006.173.06:13:41.43#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.06:13:41.43#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.06:13:41.43#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.06:13:41.43#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.06:13:41.43$vck44/vabw=wide 2006.173.06:13:41.43#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.06:13:41.43#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.06:13:41.43#ibcon#ireg 8 cls_cnt 0 2006.173.06:13:41.43#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.06:13:41.43#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.06:13:41.43#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.06:13:41.43#ibcon#enter wrdev, iclass 10, count 0 2006.173.06:13:41.43#ibcon#first serial, iclass 10, count 0 2006.173.06:13:41.43#ibcon#enter sib2, iclass 10, count 0 2006.173.06:13:41.43#ibcon#flushed, iclass 10, count 0 2006.173.06:13:41.43#ibcon#about to write, iclass 10, count 0 2006.173.06:13:41.43#ibcon#wrote, iclass 10, count 0 2006.173.06:13:41.43#ibcon#about to read 3, iclass 10, count 0 2006.173.06:13:41.45#ibcon#read 3, iclass 10, count 0 2006.173.06:13:41.45#ibcon#about to read 4, iclass 10, count 0 2006.173.06:13:41.45#ibcon#read 4, iclass 10, count 0 2006.173.06:13:41.45#ibcon#about to read 5, iclass 10, count 0 2006.173.06:13:41.45#ibcon#read 5, iclass 10, count 0 2006.173.06:13:41.45#ibcon#about to read 6, iclass 10, count 0 2006.173.06:13:41.45#ibcon#read 6, iclass 10, count 0 2006.173.06:13:41.45#ibcon#end of sib2, iclass 10, count 0 2006.173.06:13:41.45#ibcon#*mode == 0, iclass 10, count 0 2006.173.06:13:41.45#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.06:13:41.45#ibcon#[25=BW32\r\n] 2006.173.06:13:41.45#ibcon#*before write, iclass 10, count 0 2006.173.06:13:41.45#ibcon#enter sib2, iclass 10, count 0 2006.173.06:13:41.45#ibcon#flushed, iclass 10, count 0 2006.173.06:13:41.45#ibcon#about to write, iclass 10, count 0 2006.173.06:13:41.45#ibcon#wrote, iclass 10, count 0 2006.173.06:13:41.45#ibcon#about to read 3, iclass 10, count 0 2006.173.06:13:41.48#ibcon#read 3, iclass 10, count 0 2006.173.06:13:41.48#ibcon#about to read 4, iclass 10, count 0 2006.173.06:13:41.48#ibcon#read 4, iclass 10, count 0 2006.173.06:13:41.48#ibcon#about to read 5, iclass 10, count 0 2006.173.06:13:41.48#ibcon#read 5, iclass 10, count 0 2006.173.06:13:41.48#ibcon#about to read 6, iclass 10, count 0 2006.173.06:13:41.48#ibcon#read 6, iclass 10, count 0 2006.173.06:13:41.48#ibcon#end of sib2, iclass 10, count 0 2006.173.06:13:41.48#ibcon#*after write, iclass 10, count 0 2006.173.06:13:41.48#ibcon#*before return 0, iclass 10, count 0 2006.173.06:13:41.48#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.06:13:41.48#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.06:13:41.48#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.06:13:41.48#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.06:13:41.48$vck44/vbbw=wide 2006.173.06:13:41.48#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.06:13:41.48#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.06:13:41.48#ibcon#ireg 8 cls_cnt 0 2006.173.06:13:41.48#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.06:13:41.55#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.06:13:41.55#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.06:13:41.55#ibcon#enter wrdev, iclass 12, count 0 2006.173.06:13:41.55#ibcon#first serial, iclass 12, count 0 2006.173.06:13:41.55#ibcon#enter sib2, iclass 12, count 0 2006.173.06:13:41.55#ibcon#flushed, iclass 12, count 0 2006.173.06:13:41.55#ibcon#about to write, iclass 12, count 0 2006.173.06:13:41.55#ibcon#wrote, iclass 12, count 0 2006.173.06:13:41.55#ibcon#about to read 3, iclass 12, count 0 2006.173.06:13:41.57#ibcon#read 3, iclass 12, count 0 2006.173.06:13:41.57#ibcon#about to read 4, iclass 12, count 0 2006.173.06:13:41.57#ibcon#read 4, iclass 12, count 0 2006.173.06:13:41.57#ibcon#about to read 5, iclass 12, count 0 2006.173.06:13:41.57#ibcon#read 5, iclass 12, count 0 2006.173.06:13:41.57#ibcon#about to read 6, iclass 12, count 0 2006.173.06:13:41.57#ibcon#read 6, iclass 12, count 0 2006.173.06:13:41.57#ibcon#end of sib2, iclass 12, count 0 2006.173.06:13:41.57#ibcon#*mode == 0, iclass 12, count 0 2006.173.06:13:41.57#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.06:13:41.57#ibcon#[27=BW32\r\n] 2006.173.06:13:41.57#ibcon#*before write, iclass 12, count 0 2006.173.06:13:41.57#ibcon#enter sib2, iclass 12, count 0 2006.173.06:13:41.57#ibcon#flushed, iclass 12, count 0 2006.173.06:13:41.57#ibcon#about to write, iclass 12, count 0 2006.173.06:13:41.57#ibcon#wrote, iclass 12, count 0 2006.173.06:13:41.57#ibcon#about to read 3, iclass 12, count 0 2006.173.06:13:41.60#ibcon#read 3, iclass 12, count 0 2006.173.06:13:41.60#ibcon#about to read 4, iclass 12, count 0 2006.173.06:13:41.60#ibcon#read 4, iclass 12, count 0 2006.173.06:13:41.60#ibcon#about to read 5, iclass 12, count 0 2006.173.06:13:41.60#ibcon#read 5, iclass 12, count 0 2006.173.06:13:41.60#ibcon#about to read 6, iclass 12, count 0 2006.173.06:13:41.60#ibcon#read 6, iclass 12, count 0 2006.173.06:13:41.60#ibcon#end of sib2, iclass 12, count 0 2006.173.06:13:41.60#ibcon#*after write, iclass 12, count 0 2006.173.06:13:41.60#ibcon#*before return 0, iclass 12, count 0 2006.173.06:13:41.60#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.06:13:41.60#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.06:13:41.60#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.06:13:41.60#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.06:13:41.60$setupk4/ifdk4 2006.173.06:13:41.60$ifdk4/lo= 2006.173.06:13:41.60$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.06:13:41.60$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.06:13:41.60$ifdk4/patch= 2006.173.06:13:41.60$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.06:13:41.60$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.06:13:41.60$setupk4/!*+20s 2006.173.06:13:48.14#trakl#Source acquired 2006.173.06:13:49.14#flagr#flagr/antenna,acquired 2006.173.06:13:51.48#abcon#<5=/01 0.6 0.9 23.88 791005.2\r\n> 2006.173.06:13:51.50#abcon#{5=INTERFACE CLEAR} 2006.173.06:13:51.56#abcon#[5=S1D000X0/0*\r\n] 2006.173.06:13:56.11$setupk4/"tpicd 2006.173.06:13:56.11$setupk4/echo=off 2006.173.06:13:56.11$setupk4/xlog=off 2006.173.06:13:56.11:!2006.173.06:17:54 2006.173.06:17:54.00:preob 2006.173.06:17:54.14/onsource/TRACKING 2006.173.06:17:54.14:!2006.173.06:18:04 2006.173.06:18:04.00:"tape 2006.173.06:18:04.00:"st=record 2006.173.06:18:04.00:data_valid=on 2006.173.06:18:04.01:midob 2006.173.06:18:05.14/onsource/TRACKING 2006.173.06:18:05.14/wx/23.91,1005.1,80 2006.173.06:18:05.24/cable/+6.5042E-03 2006.173.06:18:06.33/va/01,07,usb,yes,35,38 2006.173.06:18:06.33/va/02,06,usb,yes,35,36 2006.173.06:18:06.33/va/03,05,usb,yes,45,46 2006.173.06:18:06.33/va/04,06,usb,yes,36,38 2006.173.06:18:06.33/va/05,04,usb,yes,28,28 2006.173.06:18:06.33/va/06,03,usb,yes,39,39 2006.173.06:18:06.33/va/07,04,usb,yes,32,33 2006.173.06:18:06.33/va/08,04,usb,yes,27,33 2006.173.06:18:06.56/valo/01,524.99,yes,locked 2006.173.06:18:06.56/valo/02,534.99,yes,locked 2006.173.06:18:06.56/valo/03,564.99,yes,locked 2006.173.06:18:06.56/valo/04,624.99,yes,locked 2006.173.06:18:06.56/valo/05,734.99,yes,locked 2006.173.06:18:06.56/valo/06,814.99,yes,locked 2006.173.06:18:06.56/valo/07,864.99,yes,locked 2006.173.06:18:06.56/valo/08,884.99,yes,locked 2006.173.06:18:07.65/vb/01,04,usb,yes,29,27 2006.173.06:18:07.65/vb/02,04,usb,yes,32,32 2006.173.06:18:07.65/vb/03,04,usb,yes,29,32 2006.173.06:18:07.65/vb/04,04,usb,yes,33,32 2006.173.06:18:07.65/vb/05,04,usb,yes,26,28 2006.173.06:18:07.65/vb/06,04,usb,yes,30,26 2006.173.06:18:07.65/vb/07,04,usb,yes,30,30 2006.173.06:18:07.65/vb/08,04,usb,yes,27,31 2006.173.06:18:07.88/vblo/01,629.99,yes,locked 2006.173.06:18:07.88/vblo/02,634.99,yes,locked 2006.173.06:18:07.88/vblo/03,649.99,yes,locked 2006.173.06:18:07.88/vblo/04,679.99,yes,locked 2006.173.06:18:07.88/vblo/05,709.99,yes,locked 2006.173.06:18:07.88/vblo/06,719.99,yes,locked 2006.173.06:18:07.88/vblo/07,734.99,yes,locked 2006.173.06:18:07.88/vblo/08,744.99,yes,locked 2006.173.06:18:08.03/vabw/8 2006.173.06:18:08.18/vbbw/8 2006.173.06:18:08.27/xfe/off,on,15.2 2006.173.06:18:08.65/ifatt/23,28,28,28 2006.173.06:18:09.08/fmout-gps/S +4.00E-07 2006.173.06:18:09.12:!2006.173.06:24:44 2006.173.06:24:44.00:data_valid=off 2006.173.06:24:44.00:"et 2006.173.06:24:44.00:!+3s 2006.173.06:24:47.01:"tape 2006.173.06:24:47.01:postob 2006.173.06:24:47.16/cable/+6.5030E-03 2006.173.06:24:47.16/wx/23.86,1005.2,76 2006.173.06:24:48.08/fmout-gps/S +4.01E-07 2006.173.06:24:48.08:scan_name=173-0632,jd0606,50 2006.173.06:24:48.08:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.173.06:24:48.14#flagr#flagr/antenna,new-source 2006.173.06:24:49.14:checkk5 2006.173.06:24:49.54/chk_autoobs//k5ts1/ autoobs is running! 2006.173.06:24:49.94/chk_autoobs//k5ts2/ autoobs is running! 2006.173.06:24:50.35/chk_autoobs//k5ts3/ autoobs is running! 2006.173.06:24:50.76/chk_autoobs//k5ts4/ autoobs is running! 2006.173.06:24:51.16/chk_obsdata//k5ts1/T1730618??a.dat file size is correct (nominal:1600MB, actual:1596MB). 2006.173.06:24:51.56/chk_obsdata//k5ts2/T1730618??b.dat file size is correct (nominal:1600MB, actual:1596MB). 2006.173.06:24:51.98/chk_obsdata//k5ts3/T1730618??c.dat file size is correct (nominal:1600MB, actual:1596MB). 2006.173.06:24:52.40/chk_obsdata//k5ts4/T1730618??d.dat file size is correct (nominal:1600MB, actual:1596MB). 2006.173.06:24:53.15/k5log//k5ts1_log_newline 2006.173.06:24:53.85/k5log//k5ts2_log_newline 2006.173.06:24:54.58/k5log//k5ts3_log_newline 2006.173.06:24:55.30/k5log//k5ts4_log_newline 2006.173.06:24:55.33/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.06:24:55.33:setupk4=1 2006.173.06:24:55.33$setupk4/echo=on 2006.173.06:24:55.33$setupk4/pcalon 2006.173.06:24:55.33$pcalon/"no phase cal control is implemented here 2006.173.06:24:55.33$setupk4/"tpicd=stop 2006.173.06:24:55.33$setupk4/"rec=synch_on 2006.173.06:24:55.33$setupk4/"rec_mode=128 2006.173.06:24:55.33$setupk4/!* 2006.173.06:24:55.33$setupk4/recpk4 2006.173.06:24:55.33$recpk4/recpatch= 2006.173.06:24:55.33$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.06:24:55.33$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.06:24:55.34$setupk4/vck44 2006.173.06:24:55.34$vck44/valo=1,524.99 2006.173.06:24:55.34#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.06:24:55.34#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.06:24:55.34#ibcon#ireg 17 cls_cnt 0 2006.173.06:24:55.34#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.06:24:55.34#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.06:24:55.34#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.06:24:55.34#ibcon#enter wrdev, iclass 29, count 0 2006.173.06:24:55.34#ibcon#first serial, iclass 29, count 0 2006.173.06:24:55.34#ibcon#enter sib2, iclass 29, count 0 2006.173.06:24:55.34#ibcon#flushed, iclass 29, count 0 2006.173.06:24:55.34#ibcon#about to write, iclass 29, count 0 2006.173.06:24:55.34#ibcon#wrote, iclass 29, count 0 2006.173.06:24:55.34#ibcon#about to read 3, iclass 29, count 0 2006.173.06:24:55.35#ibcon#read 3, iclass 29, count 0 2006.173.06:24:55.35#ibcon#about to read 4, iclass 29, count 0 2006.173.06:24:55.35#ibcon#read 4, iclass 29, count 0 2006.173.06:24:55.35#ibcon#about to read 5, iclass 29, count 0 2006.173.06:24:55.35#ibcon#read 5, iclass 29, count 0 2006.173.06:24:55.35#ibcon#about to read 6, iclass 29, count 0 2006.173.06:24:55.35#ibcon#read 6, iclass 29, count 0 2006.173.06:24:55.35#ibcon#end of sib2, iclass 29, count 0 2006.173.06:24:55.35#ibcon#*mode == 0, iclass 29, count 0 2006.173.06:24:55.35#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.06:24:55.35#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.06:24:55.35#ibcon#*before write, iclass 29, count 0 2006.173.06:24:55.35#ibcon#enter sib2, iclass 29, count 0 2006.173.06:24:55.35#ibcon#flushed, iclass 29, count 0 2006.173.06:24:55.35#ibcon#about to write, iclass 29, count 0 2006.173.06:24:55.35#ibcon#wrote, iclass 29, count 0 2006.173.06:24:55.35#ibcon#about to read 3, iclass 29, count 0 2006.173.06:24:55.40#ibcon#read 3, iclass 29, count 0 2006.173.06:24:55.40#ibcon#about to read 4, iclass 29, count 0 2006.173.06:24:55.40#ibcon#read 4, iclass 29, count 0 2006.173.06:24:55.40#ibcon#about to read 5, iclass 29, count 0 2006.173.06:24:55.40#ibcon#read 5, iclass 29, count 0 2006.173.06:24:55.40#ibcon#about to read 6, iclass 29, count 0 2006.173.06:24:55.40#ibcon#read 6, iclass 29, count 0 2006.173.06:24:55.40#ibcon#end of sib2, iclass 29, count 0 2006.173.06:24:55.40#ibcon#*after write, iclass 29, count 0 2006.173.06:24:55.40#ibcon#*before return 0, iclass 29, count 0 2006.173.06:24:55.40#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.06:24:55.40#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.06:24:55.40#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.06:24:55.40#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.06:24:55.40$vck44/va=1,7 2006.173.06:24:55.40#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.06:24:55.40#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.06:24:55.40#ibcon#ireg 11 cls_cnt 2 2006.173.06:24:55.40#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.06:24:55.40#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.06:24:55.40#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.06:24:55.40#ibcon#enter wrdev, iclass 31, count 2 2006.173.06:24:55.40#ibcon#first serial, iclass 31, count 2 2006.173.06:24:55.40#ibcon#enter sib2, iclass 31, count 2 2006.173.06:24:55.40#ibcon#flushed, iclass 31, count 2 2006.173.06:24:55.40#ibcon#about to write, iclass 31, count 2 2006.173.06:24:55.40#ibcon#wrote, iclass 31, count 2 2006.173.06:24:55.40#ibcon#about to read 3, iclass 31, count 2 2006.173.06:24:55.42#ibcon#read 3, iclass 31, count 2 2006.173.06:24:55.42#ibcon#about to read 4, iclass 31, count 2 2006.173.06:24:55.42#ibcon#read 4, iclass 31, count 2 2006.173.06:24:55.42#ibcon#about to read 5, iclass 31, count 2 2006.173.06:24:55.42#ibcon#read 5, iclass 31, count 2 2006.173.06:24:55.42#ibcon#about to read 6, iclass 31, count 2 2006.173.06:24:55.42#ibcon#read 6, iclass 31, count 2 2006.173.06:24:55.42#ibcon#end of sib2, iclass 31, count 2 2006.173.06:24:55.42#ibcon#*mode == 0, iclass 31, count 2 2006.173.06:24:55.42#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.06:24:55.42#ibcon#[25=AT01-07\r\n] 2006.173.06:24:55.42#ibcon#*before write, iclass 31, count 2 2006.173.06:24:55.42#ibcon#enter sib2, iclass 31, count 2 2006.173.06:24:55.42#ibcon#flushed, iclass 31, count 2 2006.173.06:24:55.42#ibcon#about to write, iclass 31, count 2 2006.173.06:24:55.42#ibcon#wrote, iclass 31, count 2 2006.173.06:24:55.42#ibcon#about to read 3, iclass 31, count 2 2006.173.06:24:55.45#ibcon#read 3, iclass 31, count 2 2006.173.06:24:55.45#ibcon#about to read 4, iclass 31, count 2 2006.173.06:24:55.45#ibcon#read 4, iclass 31, count 2 2006.173.06:24:55.45#ibcon#about to read 5, iclass 31, count 2 2006.173.06:24:55.45#ibcon#read 5, iclass 31, count 2 2006.173.06:24:55.45#ibcon#about to read 6, iclass 31, count 2 2006.173.06:24:55.45#ibcon#read 6, iclass 31, count 2 2006.173.06:24:55.45#ibcon#end of sib2, iclass 31, count 2 2006.173.06:24:55.45#ibcon#*after write, iclass 31, count 2 2006.173.06:24:55.45#ibcon#*before return 0, iclass 31, count 2 2006.173.06:24:55.45#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.06:24:55.45#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.06:24:55.45#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.06:24:55.45#ibcon#ireg 7 cls_cnt 0 2006.173.06:24:55.45#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.06:24:55.57#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.06:24:55.57#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.06:24:55.57#ibcon#enter wrdev, iclass 31, count 0 2006.173.06:24:55.57#ibcon#first serial, iclass 31, count 0 2006.173.06:24:55.57#ibcon#enter sib2, iclass 31, count 0 2006.173.06:24:55.57#ibcon#flushed, iclass 31, count 0 2006.173.06:24:55.57#ibcon#about to write, iclass 31, count 0 2006.173.06:24:55.57#ibcon#wrote, iclass 31, count 0 2006.173.06:24:55.57#ibcon#about to read 3, iclass 31, count 0 2006.173.06:24:55.59#ibcon#read 3, iclass 31, count 0 2006.173.06:24:55.59#ibcon#about to read 4, iclass 31, count 0 2006.173.06:24:55.59#ibcon#read 4, iclass 31, count 0 2006.173.06:24:55.59#ibcon#about to read 5, iclass 31, count 0 2006.173.06:24:55.59#ibcon#read 5, iclass 31, count 0 2006.173.06:24:55.59#ibcon#about to read 6, iclass 31, count 0 2006.173.06:24:55.59#ibcon#read 6, iclass 31, count 0 2006.173.06:24:55.59#ibcon#end of sib2, iclass 31, count 0 2006.173.06:24:55.59#ibcon#*mode == 0, iclass 31, count 0 2006.173.06:24:55.59#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.06:24:55.59#ibcon#[25=USB\r\n] 2006.173.06:24:55.59#ibcon#*before write, iclass 31, count 0 2006.173.06:24:55.59#ibcon#enter sib2, iclass 31, count 0 2006.173.06:24:55.59#ibcon#flushed, iclass 31, count 0 2006.173.06:24:55.59#ibcon#about to write, iclass 31, count 0 2006.173.06:24:55.59#ibcon#wrote, iclass 31, count 0 2006.173.06:24:55.59#ibcon#about to read 3, iclass 31, count 0 2006.173.06:24:55.62#ibcon#read 3, iclass 31, count 0 2006.173.06:24:55.62#ibcon#about to read 4, iclass 31, count 0 2006.173.06:24:55.62#ibcon#read 4, iclass 31, count 0 2006.173.06:24:55.62#ibcon#about to read 5, iclass 31, count 0 2006.173.06:24:55.62#ibcon#read 5, iclass 31, count 0 2006.173.06:24:55.62#ibcon#about to read 6, iclass 31, count 0 2006.173.06:24:55.62#ibcon#read 6, iclass 31, count 0 2006.173.06:24:55.62#ibcon#end of sib2, iclass 31, count 0 2006.173.06:24:55.62#ibcon#*after write, iclass 31, count 0 2006.173.06:24:55.62#ibcon#*before return 0, iclass 31, count 0 2006.173.06:24:55.62#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.06:24:55.62#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.06:24:55.62#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.06:24:55.62#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.06:24:55.62$vck44/valo=2,534.99 2006.173.06:24:55.62#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.06:24:55.62#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.06:24:55.62#ibcon#ireg 17 cls_cnt 0 2006.173.06:24:55.62#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.06:24:55.62#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.06:24:55.62#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.06:24:55.62#ibcon#enter wrdev, iclass 33, count 0 2006.173.06:24:55.62#ibcon#first serial, iclass 33, count 0 2006.173.06:24:55.62#ibcon#enter sib2, iclass 33, count 0 2006.173.06:24:55.62#ibcon#flushed, iclass 33, count 0 2006.173.06:24:55.62#ibcon#about to write, iclass 33, count 0 2006.173.06:24:55.62#ibcon#wrote, iclass 33, count 0 2006.173.06:24:55.62#ibcon#about to read 3, iclass 33, count 0 2006.173.06:24:55.64#ibcon#read 3, iclass 33, count 0 2006.173.06:24:55.64#ibcon#about to read 4, iclass 33, count 0 2006.173.06:24:55.64#ibcon#read 4, iclass 33, count 0 2006.173.06:24:55.64#ibcon#about to read 5, iclass 33, count 0 2006.173.06:24:55.64#ibcon#read 5, iclass 33, count 0 2006.173.06:24:55.64#ibcon#about to read 6, iclass 33, count 0 2006.173.06:24:55.64#ibcon#read 6, iclass 33, count 0 2006.173.06:24:55.64#ibcon#end of sib2, iclass 33, count 0 2006.173.06:24:55.64#ibcon#*mode == 0, iclass 33, count 0 2006.173.06:24:55.64#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.06:24:55.64#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.06:24:55.64#ibcon#*before write, iclass 33, count 0 2006.173.06:24:55.64#ibcon#enter sib2, iclass 33, count 0 2006.173.06:24:55.64#ibcon#flushed, iclass 33, count 0 2006.173.06:24:55.64#ibcon#about to write, iclass 33, count 0 2006.173.06:24:55.64#ibcon#wrote, iclass 33, count 0 2006.173.06:24:55.64#ibcon#about to read 3, iclass 33, count 0 2006.173.06:24:55.68#ibcon#read 3, iclass 33, count 0 2006.173.06:24:55.68#ibcon#about to read 4, iclass 33, count 0 2006.173.06:24:55.68#ibcon#read 4, iclass 33, count 0 2006.173.06:24:55.68#ibcon#about to read 5, iclass 33, count 0 2006.173.06:24:55.68#ibcon#read 5, iclass 33, count 0 2006.173.06:24:55.68#ibcon#about to read 6, iclass 33, count 0 2006.173.06:24:55.68#ibcon#read 6, iclass 33, count 0 2006.173.06:24:55.68#ibcon#end of sib2, iclass 33, count 0 2006.173.06:24:55.68#ibcon#*after write, iclass 33, count 0 2006.173.06:24:55.68#ibcon#*before return 0, iclass 33, count 0 2006.173.06:24:55.68#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.06:24:55.68#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.06:24:55.68#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.06:24:55.68#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.06:24:55.68$vck44/va=2,6 2006.173.06:24:55.68#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.06:24:55.68#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.06:24:55.68#ibcon#ireg 11 cls_cnt 2 2006.173.06:24:55.68#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.06:24:55.74#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.06:24:55.74#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.06:24:55.74#ibcon#enter wrdev, iclass 35, count 2 2006.173.06:24:55.74#ibcon#first serial, iclass 35, count 2 2006.173.06:24:55.74#ibcon#enter sib2, iclass 35, count 2 2006.173.06:24:55.74#ibcon#flushed, iclass 35, count 2 2006.173.06:24:55.74#ibcon#about to write, iclass 35, count 2 2006.173.06:24:55.74#ibcon#wrote, iclass 35, count 2 2006.173.06:24:55.74#ibcon#about to read 3, iclass 35, count 2 2006.173.06:24:55.76#ibcon#read 3, iclass 35, count 2 2006.173.06:24:55.76#ibcon#about to read 4, iclass 35, count 2 2006.173.06:24:55.76#ibcon#read 4, iclass 35, count 2 2006.173.06:24:55.76#ibcon#about to read 5, iclass 35, count 2 2006.173.06:24:55.76#ibcon#read 5, iclass 35, count 2 2006.173.06:24:55.76#ibcon#about to read 6, iclass 35, count 2 2006.173.06:24:55.76#ibcon#read 6, iclass 35, count 2 2006.173.06:24:55.76#ibcon#end of sib2, iclass 35, count 2 2006.173.06:24:55.76#ibcon#*mode == 0, iclass 35, count 2 2006.173.06:24:55.76#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.06:24:55.76#ibcon#[25=AT02-06\r\n] 2006.173.06:24:55.76#ibcon#*before write, iclass 35, count 2 2006.173.06:24:55.76#ibcon#enter sib2, iclass 35, count 2 2006.173.06:24:55.76#ibcon#flushed, iclass 35, count 2 2006.173.06:24:55.76#ibcon#about to write, iclass 35, count 2 2006.173.06:24:55.76#ibcon#wrote, iclass 35, count 2 2006.173.06:24:55.76#ibcon#about to read 3, iclass 35, count 2 2006.173.06:24:55.79#ibcon#read 3, iclass 35, count 2 2006.173.06:24:55.79#ibcon#about to read 4, iclass 35, count 2 2006.173.06:24:55.79#ibcon#read 4, iclass 35, count 2 2006.173.06:24:55.79#ibcon#about to read 5, iclass 35, count 2 2006.173.06:24:55.79#ibcon#read 5, iclass 35, count 2 2006.173.06:24:55.79#ibcon#about to read 6, iclass 35, count 2 2006.173.06:24:55.79#ibcon#read 6, iclass 35, count 2 2006.173.06:24:55.79#ibcon#end of sib2, iclass 35, count 2 2006.173.06:24:55.79#ibcon#*after write, iclass 35, count 2 2006.173.06:24:55.79#ibcon#*before return 0, iclass 35, count 2 2006.173.06:24:55.79#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.06:24:55.79#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.06:24:55.79#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.06:24:55.79#ibcon#ireg 7 cls_cnt 0 2006.173.06:24:55.79#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.06:24:55.91#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.06:24:55.91#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.06:24:55.91#ibcon#enter wrdev, iclass 35, count 0 2006.173.06:24:55.91#ibcon#first serial, iclass 35, count 0 2006.173.06:24:55.91#ibcon#enter sib2, iclass 35, count 0 2006.173.06:24:55.91#ibcon#flushed, iclass 35, count 0 2006.173.06:24:55.91#ibcon#about to write, iclass 35, count 0 2006.173.06:24:55.91#ibcon#wrote, iclass 35, count 0 2006.173.06:24:55.91#ibcon#about to read 3, iclass 35, count 0 2006.173.06:24:55.93#ibcon#read 3, iclass 35, count 0 2006.173.06:24:55.93#ibcon#about to read 4, iclass 35, count 0 2006.173.06:24:55.93#ibcon#read 4, iclass 35, count 0 2006.173.06:24:55.93#ibcon#about to read 5, iclass 35, count 0 2006.173.06:24:55.93#ibcon#read 5, iclass 35, count 0 2006.173.06:24:55.93#ibcon#about to read 6, iclass 35, count 0 2006.173.06:24:55.93#ibcon#read 6, iclass 35, count 0 2006.173.06:24:55.93#ibcon#end of sib2, iclass 35, count 0 2006.173.06:24:55.93#ibcon#*mode == 0, iclass 35, count 0 2006.173.06:24:55.93#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.06:24:55.93#ibcon#[25=USB\r\n] 2006.173.06:24:55.93#ibcon#*before write, iclass 35, count 0 2006.173.06:24:55.93#ibcon#enter sib2, iclass 35, count 0 2006.173.06:24:55.93#ibcon#flushed, iclass 35, count 0 2006.173.06:24:55.93#ibcon#about to write, iclass 35, count 0 2006.173.06:24:55.93#ibcon#wrote, iclass 35, count 0 2006.173.06:24:55.93#ibcon#about to read 3, iclass 35, count 0 2006.173.06:24:55.96#ibcon#read 3, iclass 35, count 0 2006.173.06:24:55.96#ibcon#about to read 4, iclass 35, count 0 2006.173.06:24:55.96#ibcon#read 4, iclass 35, count 0 2006.173.06:24:55.96#ibcon#about to read 5, iclass 35, count 0 2006.173.06:24:55.96#ibcon#read 5, iclass 35, count 0 2006.173.06:24:55.96#ibcon#about to read 6, iclass 35, count 0 2006.173.06:24:55.96#ibcon#read 6, iclass 35, count 0 2006.173.06:24:55.96#ibcon#end of sib2, iclass 35, count 0 2006.173.06:24:55.96#ibcon#*after write, iclass 35, count 0 2006.173.06:24:55.96#ibcon#*before return 0, iclass 35, count 0 2006.173.06:24:55.96#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.06:24:55.96#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.06:24:55.96#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.06:24:55.96#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.06:24:55.96$vck44/valo=3,564.99 2006.173.06:24:55.96#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.06:24:55.96#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.06:24:55.96#ibcon#ireg 17 cls_cnt 0 2006.173.06:24:55.96#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.06:24:55.96#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.06:24:55.96#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.06:24:55.96#ibcon#enter wrdev, iclass 37, count 0 2006.173.06:24:55.96#ibcon#first serial, iclass 37, count 0 2006.173.06:24:55.96#ibcon#enter sib2, iclass 37, count 0 2006.173.06:24:55.96#ibcon#flushed, iclass 37, count 0 2006.173.06:24:55.96#ibcon#about to write, iclass 37, count 0 2006.173.06:24:55.96#ibcon#wrote, iclass 37, count 0 2006.173.06:24:55.96#ibcon#about to read 3, iclass 37, count 0 2006.173.06:24:55.98#ibcon#read 3, iclass 37, count 0 2006.173.06:24:55.98#ibcon#about to read 4, iclass 37, count 0 2006.173.06:24:55.98#ibcon#read 4, iclass 37, count 0 2006.173.06:24:55.98#ibcon#about to read 5, iclass 37, count 0 2006.173.06:24:55.98#ibcon#read 5, iclass 37, count 0 2006.173.06:24:55.98#ibcon#about to read 6, iclass 37, count 0 2006.173.06:24:55.98#ibcon#read 6, iclass 37, count 0 2006.173.06:24:55.98#ibcon#end of sib2, iclass 37, count 0 2006.173.06:24:55.98#ibcon#*mode == 0, iclass 37, count 0 2006.173.06:24:55.98#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.06:24:55.98#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.06:24:55.98#ibcon#*before write, iclass 37, count 0 2006.173.06:24:55.98#ibcon#enter sib2, iclass 37, count 0 2006.173.06:24:55.98#ibcon#flushed, iclass 37, count 0 2006.173.06:24:55.98#ibcon#about to write, iclass 37, count 0 2006.173.06:24:55.98#ibcon#wrote, iclass 37, count 0 2006.173.06:24:55.98#ibcon#about to read 3, iclass 37, count 0 2006.173.06:24:56.02#ibcon#read 3, iclass 37, count 0 2006.173.06:24:56.02#ibcon#about to read 4, iclass 37, count 0 2006.173.06:24:56.02#ibcon#read 4, iclass 37, count 0 2006.173.06:24:56.02#ibcon#about to read 5, iclass 37, count 0 2006.173.06:24:56.02#ibcon#read 5, iclass 37, count 0 2006.173.06:24:56.02#ibcon#about to read 6, iclass 37, count 0 2006.173.06:24:56.02#ibcon#read 6, iclass 37, count 0 2006.173.06:24:56.02#ibcon#end of sib2, iclass 37, count 0 2006.173.06:24:56.02#ibcon#*after write, iclass 37, count 0 2006.173.06:24:56.02#ibcon#*before return 0, iclass 37, count 0 2006.173.06:24:56.02#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.06:24:56.02#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.06:24:56.02#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.06:24:56.02#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.06:24:56.02$vck44/va=3,5 2006.173.06:24:56.02#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.06:24:56.02#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.06:24:56.02#ibcon#ireg 11 cls_cnt 2 2006.173.06:24:56.02#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.06:24:56.08#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.06:24:56.08#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.06:24:56.08#ibcon#enter wrdev, iclass 39, count 2 2006.173.06:24:56.08#ibcon#first serial, iclass 39, count 2 2006.173.06:24:56.08#ibcon#enter sib2, iclass 39, count 2 2006.173.06:24:56.08#ibcon#flushed, iclass 39, count 2 2006.173.06:24:56.08#ibcon#about to write, iclass 39, count 2 2006.173.06:24:56.08#ibcon#wrote, iclass 39, count 2 2006.173.06:24:56.08#ibcon#about to read 3, iclass 39, count 2 2006.173.06:24:56.10#ibcon#read 3, iclass 39, count 2 2006.173.06:24:56.10#ibcon#about to read 4, iclass 39, count 2 2006.173.06:24:56.10#ibcon#read 4, iclass 39, count 2 2006.173.06:24:56.10#ibcon#about to read 5, iclass 39, count 2 2006.173.06:24:56.10#ibcon#read 5, iclass 39, count 2 2006.173.06:24:56.10#ibcon#about to read 6, iclass 39, count 2 2006.173.06:24:56.10#ibcon#read 6, iclass 39, count 2 2006.173.06:24:56.10#ibcon#end of sib2, iclass 39, count 2 2006.173.06:24:56.10#ibcon#*mode == 0, iclass 39, count 2 2006.173.06:24:56.10#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.06:24:56.10#ibcon#[25=AT03-05\r\n] 2006.173.06:24:56.10#ibcon#*before write, iclass 39, count 2 2006.173.06:24:56.10#ibcon#enter sib2, iclass 39, count 2 2006.173.06:24:56.10#ibcon#flushed, iclass 39, count 2 2006.173.06:24:56.10#ibcon#about to write, iclass 39, count 2 2006.173.06:24:56.10#ibcon#wrote, iclass 39, count 2 2006.173.06:24:56.10#ibcon#about to read 3, iclass 39, count 2 2006.173.06:24:56.13#ibcon#read 3, iclass 39, count 2 2006.173.06:24:56.13#ibcon#about to read 4, iclass 39, count 2 2006.173.06:24:56.13#ibcon#read 4, iclass 39, count 2 2006.173.06:24:56.13#ibcon#about to read 5, iclass 39, count 2 2006.173.06:24:56.13#ibcon#read 5, iclass 39, count 2 2006.173.06:24:56.13#ibcon#about to read 6, iclass 39, count 2 2006.173.06:24:56.13#ibcon#read 6, iclass 39, count 2 2006.173.06:24:56.13#ibcon#end of sib2, iclass 39, count 2 2006.173.06:24:56.13#ibcon#*after write, iclass 39, count 2 2006.173.06:24:56.13#ibcon#*before return 0, iclass 39, count 2 2006.173.06:24:56.13#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.06:24:56.13#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.06:24:56.13#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.06:24:56.13#ibcon#ireg 7 cls_cnt 0 2006.173.06:24:56.13#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.06:24:56.25#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.06:24:56.25#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.06:24:56.25#ibcon#enter wrdev, iclass 39, count 0 2006.173.06:24:56.25#ibcon#first serial, iclass 39, count 0 2006.173.06:24:56.25#ibcon#enter sib2, iclass 39, count 0 2006.173.06:24:56.25#ibcon#flushed, iclass 39, count 0 2006.173.06:24:56.25#ibcon#about to write, iclass 39, count 0 2006.173.06:24:56.25#ibcon#wrote, iclass 39, count 0 2006.173.06:24:56.25#ibcon#about to read 3, iclass 39, count 0 2006.173.06:24:56.27#ibcon#read 3, iclass 39, count 0 2006.173.06:24:56.27#ibcon#about to read 4, iclass 39, count 0 2006.173.06:24:56.27#ibcon#read 4, iclass 39, count 0 2006.173.06:24:56.27#ibcon#about to read 5, iclass 39, count 0 2006.173.06:24:56.27#ibcon#read 5, iclass 39, count 0 2006.173.06:24:56.27#ibcon#about to read 6, iclass 39, count 0 2006.173.06:24:56.27#ibcon#read 6, iclass 39, count 0 2006.173.06:24:56.27#ibcon#end of sib2, iclass 39, count 0 2006.173.06:24:56.27#ibcon#*mode == 0, iclass 39, count 0 2006.173.06:24:56.27#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.06:24:56.27#ibcon#[25=USB\r\n] 2006.173.06:24:56.27#ibcon#*before write, iclass 39, count 0 2006.173.06:24:56.27#ibcon#enter sib2, iclass 39, count 0 2006.173.06:24:56.27#ibcon#flushed, iclass 39, count 0 2006.173.06:24:56.27#ibcon#about to write, iclass 39, count 0 2006.173.06:24:56.27#ibcon#wrote, iclass 39, count 0 2006.173.06:24:56.27#ibcon#about to read 3, iclass 39, count 0 2006.173.06:24:56.30#ibcon#read 3, iclass 39, count 0 2006.173.06:24:56.30#ibcon#about to read 4, iclass 39, count 0 2006.173.06:24:56.30#ibcon#read 4, iclass 39, count 0 2006.173.06:24:56.30#ibcon#about to read 5, iclass 39, count 0 2006.173.06:24:56.30#ibcon#read 5, iclass 39, count 0 2006.173.06:24:56.30#ibcon#about to read 6, iclass 39, count 0 2006.173.06:24:56.30#ibcon#read 6, iclass 39, count 0 2006.173.06:24:56.30#ibcon#end of sib2, iclass 39, count 0 2006.173.06:24:56.30#ibcon#*after write, iclass 39, count 0 2006.173.06:24:56.30#ibcon#*before return 0, iclass 39, count 0 2006.173.06:24:56.30#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.06:24:56.30#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.06:24:56.30#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.06:24:56.30#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.06:24:56.30$vck44/valo=4,624.99 2006.173.06:24:56.30#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.06:24:56.30#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.06:24:56.30#ibcon#ireg 17 cls_cnt 0 2006.173.06:24:56.30#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.06:24:56.30#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.06:24:56.30#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.06:24:56.30#ibcon#enter wrdev, iclass 3, count 0 2006.173.06:24:56.30#ibcon#first serial, iclass 3, count 0 2006.173.06:24:56.30#ibcon#enter sib2, iclass 3, count 0 2006.173.06:24:56.30#ibcon#flushed, iclass 3, count 0 2006.173.06:24:56.30#ibcon#about to write, iclass 3, count 0 2006.173.06:24:56.30#ibcon#wrote, iclass 3, count 0 2006.173.06:24:56.30#ibcon#about to read 3, iclass 3, count 0 2006.173.06:24:56.32#ibcon#read 3, iclass 3, count 0 2006.173.06:24:56.32#ibcon#about to read 4, iclass 3, count 0 2006.173.06:24:56.32#ibcon#read 4, iclass 3, count 0 2006.173.06:24:56.32#ibcon#about to read 5, iclass 3, count 0 2006.173.06:24:56.32#ibcon#read 5, iclass 3, count 0 2006.173.06:24:56.32#ibcon#about to read 6, iclass 3, count 0 2006.173.06:24:56.32#ibcon#read 6, iclass 3, count 0 2006.173.06:24:56.32#ibcon#end of sib2, iclass 3, count 0 2006.173.06:24:56.32#ibcon#*mode == 0, iclass 3, count 0 2006.173.06:24:56.32#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.06:24:56.32#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.06:24:56.32#ibcon#*before write, iclass 3, count 0 2006.173.06:24:56.32#ibcon#enter sib2, iclass 3, count 0 2006.173.06:24:56.32#ibcon#flushed, iclass 3, count 0 2006.173.06:24:56.32#ibcon#about to write, iclass 3, count 0 2006.173.06:24:56.32#ibcon#wrote, iclass 3, count 0 2006.173.06:24:56.32#ibcon#about to read 3, iclass 3, count 0 2006.173.06:24:56.36#ibcon#read 3, iclass 3, count 0 2006.173.06:24:56.36#ibcon#about to read 4, iclass 3, count 0 2006.173.06:24:56.36#ibcon#read 4, iclass 3, count 0 2006.173.06:24:56.36#ibcon#about to read 5, iclass 3, count 0 2006.173.06:24:56.36#ibcon#read 5, iclass 3, count 0 2006.173.06:24:56.36#ibcon#about to read 6, iclass 3, count 0 2006.173.06:24:56.36#ibcon#read 6, iclass 3, count 0 2006.173.06:24:56.36#ibcon#end of sib2, iclass 3, count 0 2006.173.06:24:56.36#ibcon#*after write, iclass 3, count 0 2006.173.06:24:56.36#ibcon#*before return 0, iclass 3, count 0 2006.173.06:24:56.36#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.06:24:56.36#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.06:24:56.36#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.06:24:56.36#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.06:24:56.36$vck44/va=4,6 2006.173.06:24:56.36#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.06:24:56.36#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.06:24:56.36#ibcon#ireg 11 cls_cnt 2 2006.173.06:24:56.36#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.06:24:56.42#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.06:24:56.42#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.06:24:56.42#ibcon#enter wrdev, iclass 5, count 2 2006.173.06:24:56.42#ibcon#first serial, iclass 5, count 2 2006.173.06:24:56.42#ibcon#enter sib2, iclass 5, count 2 2006.173.06:24:56.42#ibcon#flushed, iclass 5, count 2 2006.173.06:24:56.42#ibcon#about to write, iclass 5, count 2 2006.173.06:24:56.42#ibcon#wrote, iclass 5, count 2 2006.173.06:24:56.42#ibcon#about to read 3, iclass 5, count 2 2006.173.06:24:56.44#ibcon#read 3, iclass 5, count 2 2006.173.06:24:56.44#ibcon#about to read 4, iclass 5, count 2 2006.173.06:24:56.44#ibcon#read 4, iclass 5, count 2 2006.173.06:24:56.44#ibcon#about to read 5, iclass 5, count 2 2006.173.06:24:56.44#ibcon#read 5, iclass 5, count 2 2006.173.06:24:56.44#ibcon#about to read 6, iclass 5, count 2 2006.173.06:24:56.44#ibcon#read 6, iclass 5, count 2 2006.173.06:24:56.44#ibcon#end of sib2, iclass 5, count 2 2006.173.06:24:56.44#ibcon#*mode == 0, iclass 5, count 2 2006.173.06:24:56.44#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.06:24:56.44#ibcon#[25=AT04-06\r\n] 2006.173.06:24:56.44#ibcon#*before write, iclass 5, count 2 2006.173.06:24:56.44#ibcon#enter sib2, iclass 5, count 2 2006.173.06:24:56.44#ibcon#flushed, iclass 5, count 2 2006.173.06:24:56.44#ibcon#about to write, iclass 5, count 2 2006.173.06:24:56.44#ibcon#wrote, iclass 5, count 2 2006.173.06:24:56.44#ibcon#about to read 3, iclass 5, count 2 2006.173.06:24:56.47#ibcon#read 3, iclass 5, count 2 2006.173.06:24:56.47#ibcon#about to read 4, iclass 5, count 2 2006.173.06:24:56.47#ibcon#read 4, iclass 5, count 2 2006.173.06:24:56.47#ibcon#about to read 5, iclass 5, count 2 2006.173.06:24:56.47#ibcon#read 5, iclass 5, count 2 2006.173.06:24:56.47#ibcon#about to read 6, iclass 5, count 2 2006.173.06:24:56.47#ibcon#read 6, iclass 5, count 2 2006.173.06:24:56.47#ibcon#end of sib2, iclass 5, count 2 2006.173.06:24:56.47#ibcon#*after write, iclass 5, count 2 2006.173.06:24:56.47#ibcon#*before return 0, iclass 5, count 2 2006.173.06:24:56.47#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.06:24:56.47#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.06:24:56.47#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.06:24:56.47#ibcon#ireg 7 cls_cnt 0 2006.173.06:24:56.47#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.06:24:56.59#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.06:24:56.59#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.06:24:56.59#ibcon#enter wrdev, iclass 5, count 0 2006.173.06:24:56.59#ibcon#first serial, iclass 5, count 0 2006.173.06:24:56.59#ibcon#enter sib2, iclass 5, count 0 2006.173.06:24:56.59#ibcon#flushed, iclass 5, count 0 2006.173.06:24:56.59#ibcon#about to write, iclass 5, count 0 2006.173.06:24:56.59#ibcon#wrote, iclass 5, count 0 2006.173.06:24:56.59#ibcon#about to read 3, iclass 5, count 0 2006.173.06:24:56.61#ibcon#read 3, iclass 5, count 0 2006.173.06:24:56.61#ibcon#about to read 4, iclass 5, count 0 2006.173.06:24:56.61#ibcon#read 4, iclass 5, count 0 2006.173.06:24:56.61#ibcon#about to read 5, iclass 5, count 0 2006.173.06:24:56.61#ibcon#read 5, iclass 5, count 0 2006.173.06:24:56.61#ibcon#about to read 6, iclass 5, count 0 2006.173.06:24:56.61#ibcon#read 6, iclass 5, count 0 2006.173.06:24:56.61#ibcon#end of sib2, iclass 5, count 0 2006.173.06:24:56.61#ibcon#*mode == 0, iclass 5, count 0 2006.173.06:24:56.61#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.06:24:56.61#ibcon#[25=USB\r\n] 2006.173.06:24:56.61#ibcon#*before write, iclass 5, count 0 2006.173.06:24:56.61#ibcon#enter sib2, iclass 5, count 0 2006.173.06:24:56.61#ibcon#flushed, iclass 5, count 0 2006.173.06:24:56.61#ibcon#about to write, iclass 5, count 0 2006.173.06:24:56.61#ibcon#wrote, iclass 5, count 0 2006.173.06:24:56.61#ibcon#about to read 3, iclass 5, count 0 2006.173.06:24:56.64#ibcon#read 3, iclass 5, count 0 2006.173.06:24:56.64#ibcon#about to read 4, iclass 5, count 0 2006.173.06:24:56.64#ibcon#read 4, iclass 5, count 0 2006.173.06:24:56.64#ibcon#about to read 5, iclass 5, count 0 2006.173.06:24:56.64#ibcon#read 5, iclass 5, count 0 2006.173.06:24:56.64#ibcon#about to read 6, iclass 5, count 0 2006.173.06:24:56.64#ibcon#read 6, iclass 5, count 0 2006.173.06:24:56.64#ibcon#end of sib2, iclass 5, count 0 2006.173.06:24:56.64#ibcon#*after write, iclass 5, count 0 2006.173.06:24:56.64#ibcon#*before return 0, iclass 5, count 0 2006.173.06:24:56.64#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.06:24:56.64#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.06:24:56.64#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.06:24:56.64#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.06:24:56.64$vck44/valo=5,734.99 2006.173.06:24:56.64#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.06:24:56.64#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.06:24:56.64#ibcon#ireg 17 cls_cnt 0 2006.173.06:24:56.64#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.06:24:56.64#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.06:24:56.64#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.06:24:56.64#ibcon#enter wrdev, iclass 7, count 0 2006.173.06:24:56.64#ibcon#first serial, iclass 7, count 0 2006.173.06:24:56.64#ibcon#enter sib2, iclass 7, count 0 2006.173.06:24:56.64#ibcon#flushed, iclass 7, count 0 2006.173.06:24:56.64#ibcon#about to write, iclass 7, count 0 2006.173.06:24:56.64#ibcon#wrote, iclass 7, count 0 2006.173.06:24:56.64#ibcon#about to read 3, iclass 7, count 0 2006.173.06:24:56.66#ibcon#read 3, iclass 7, count 0 2006.173.06:24:56.66#ibcon#about to read 4, iclass 7, count 0 2006.173.06:24:56.66#ibcon#read 4, iclass 7, count 0 2006.173.06:24:56.66#ibcon#about to read 5, iclass 7, count 0 2006.173.06:24:56.66#ibcon#read 5, iclass 7, count 0 2006.173.06:24:56.66#ibcon#about to read 6, iclass 7, count 0 2006.173.06:24:56.66#ibcon#read 6, iclass 7, count 0 2006.173.06:24:56.66#ibcon#end of sib2, iclass 7, count 0 2006.173.06:24:56.66#ibcon#*mode == 0, iclass 7, count 0 2006.173.06:24:56.66#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.06:24:56.66#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.06:24:56.66#ibcon#*before write, iclass 7, count 0 2006.173.06:24:56.66#ibcon#enter sib2, iclass 7, count 0 2006.173.06:24:56.66#ibcon#flushed, iclass 7, count 0 2006.173.06:24:56.66#ibcon#about to write, iclass 7, count 0 2006.173.06:24:56.66#ibcon#wrote, iclass 7, count 0 2006.173.06:24:56.66#ibcon#about to read 3, iclass 7, count 0 2006.173.06:24:56.70#ibcon#read 3, iclass 7, count 0 2006.173.06:24:56.70#ibcon#about to read 4, iclass 7, count 0 2006.173.06:24:56.70#ibcon#read 4, iclass 7, count 0 2006.173.06:24:56.70#ibcon#about to read 5, iclass 7, count 0 2006.173.06:24:56.70#ibcon#read 5, iclass 7, count 0 2006.173.06:24:56.70#ibcon#about to read 6, iclass 7, count 0 2006.173.06:24:56.70#ibcon#read 6, iclass 7, count 0 2006.173.06:24:56.70#ibcon#end of sib2, iclass 7, count 0 2006.173.06:24:56.70#ibcon#*after write, iclass 7, count 0 2006.173.06:24:56.70#ibcon#*before return 0, iclass 7, count 0 2006.173.06:24:56.70#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.06:24:56.70#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.06:24:56.70#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.06:24:56.70#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.06:24:56.70$vck44/va=5,4 2006.173.06:24:56.70#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.06:24:56.70#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.06:24:56.70#ibcon#ireg 11 cls_cnt 2 2006.173.06:24:56.70#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.06:24:56.76#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.06:24:56.76#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.06:24:56.76#ibcon#enter wrdev, iclass 11, count 2 2006.173.06:24:56.76#ibcon#first serial, iclass 11, count 2 2006.173.06:24:56.76#ibcon#enter sib2, iclass 11, count 2 2006.173.06:24:56.76#ibcon#flushed, iclass 11, count 2 2006.173.06:24:56.76#ibcon#about to write, iclass 11, count 2 2006.173.06:24:56.76#ibcon#wrote, iclass 11, count 2 2006.173.06:24:56.76#ibcon#about to read 3, iclass 11, count 2 2006.173.06:24:56.78#ibcon#read 3, iclass 11, count 2 2006.173.06:24:56.78#ibcon#about to read 4, iclass 11, count 2 2006.173.06:24:56.78#ibcon#read 4, iclass 11, count 2 2006.173.06:24:56.78#ibcon#about to read 5, iclass 11, count 2 2006.173.06:24:56.78#ibcon#read 5, iclass 11, count 2 2006.173.06:24:56.78#ibcon#about to read 6, iclass 11, count 2 2006.173.06:24:56.78#ibcon#read 6, iclass 11, count 2 2006.173.06:24:56.78#ibcon#end of sib2, iclass 11, count 2 2006.173.06:24:56.78#ibcon#*mode == 0, iclass 11, count 2 2006.173.06:24:56.78#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.06:24:56.78#ibcon#[25=AT05-04\r\n] 2006.173.06:24:56.78#ibcon#*before write, iclass 11, count 2 2006.173.06:24:56.78#ibcon#enter sib2, iclass 11, count 2 2006.173.06:24:56.78#ibcon#flushed, iclass 11, count 2 2006.173.06:24:56.78#ibcon#about to write, iclass 11, count 2 2006.173.06:24:56.78#ibcon#wrote, iclass 11, count 2 2006.173.06:24:56.78#ibcon#about to read 3, iclass 11, count 2 2006.173.06:24:56.81#ibcon#read 3, iclass 11, count 2 2006.173.06:24:56.81#ibcon#about to read 4, iclass 11, count 2 2006.173.06:24:56.81#ibcon#read 4, iclass 11, count 2 2006.173.06:24:56.81#ibcon#about to read 5, iclass 11, count 2 2006.173.06:24:56.81#ibcon#read 5, iclass 11, count 2 2006.173.06:24:56.81#ibcon#about to read 6, iclass 11, count 2 2006.173.06:24:56.81#ibcon#read 6, iclass 11, count 2 2006.173.06:24:56.81#ibcon#end of sib2, iclass 11, count 2 2006.173.06:24:56.81#ibcon#*after write, iclass 11, count 2 2006.173.06:24:56.81#ibcon#*before return 0, iclass 11, count 2 2006.173.06:24:56.81#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.06:24:56.81#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.06:24:56.81#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.06:24:56.81#ibcon#ireg 7 cls_cnt 0 2006.173.06:24:56.81#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.06:24:56.93#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.06:24:56.93#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.06:24:56.93#ibcon#enter wrdev, iclass 11, count 0 2006.173.06:24:56.93#ibcon#first serial, iclass 11, count 0 2006.173.06:24:56.93#ibcon#enter sib2, iclass 11, count 0 2006.173.06:24:56.93#ibcon#flushed, iclass 11, count 0 2006.173.06:24:56.93#ibcon#about to write, iclass 11, count 0 2006.173.06:24:56.93#ibcon#wrote, iclass 11, count 0 2006.173.06:24:56.93#ibcon#about to read 3, iclass 11, count 0 2006.173.06:24:56.95#ibcon#read 3, iclass 11, count 0 2006.173.06:24:56.95#ibcon#about to read 4, iclass 11, count 0 2006.173.06:24:56.95#ibcon#read 4, iclass 11, count 0 2006.173.06:24:56.95#ibcon#about to read 5, iclass 11, count 0 2006.173.06:24:56.95#ibcon#read 5, iclass 11, count 0 2006.173.06:24:56.95#ibcon#about to read 6, iclass 11, count 0 2006.173.06:24:56.95#ibcon#read 6, iclass 11, count 0 2006.173.06:24:56.95#ibcon#end of sib2, iclass 11, count 0 2006.173.06:24:56.95#ibcon#*mode == 0, iclass 11, count 0 2006.173.06:24:56.95#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.06:24:56.95#ibcon#[25=USB\r\n] 2006.173.06:24:56.95#ibcon#*before write, iclass 11, count 0 2006.173.06:24:56.95#ibcon#enter sib2, iclass 11, count 0 2006.173.06:24:56.95#ibcon#flushed, iclass 11, count 0 2006.173.06:24:56.95#ibcon#about to write, iclass 11, count 0 2006.173.06:24:56.95#ibcon#wrote, iclass 11, count 0 2006.173.06:24:56.95#ibcon#about to read 3, iclass 11, count 0 2006.173.06:24:56.98#ibcon#read 3, iclass 11, count 0 2006.173.06:24:56.98#ibcon#about to read 4, iclass 11, count 0 2006.173.06:24:56.98#ibcon#read 4, iclass 11, count 0 2006.173.06:24:56.98#ibcon#about to read 5, iclass 11, count 0 2006.173.06:24:56.98#ibcon#read 5, iclass 11, count 0 2006.173.06:24:56.98#ibcon#about to read 6, iclass 11, count 0 2006.173.06:24:56.98#ibcon#read 6, iclass 11, count 0 2006.173.06:24:56.98#ibcon#end of sib2, iclass 11, count 0 2006.173.06:24:56.98#ibcon#*after write, iclass 11, count 0 2006.173.06:24:56.98#ibcon#*before return 0, iclass 11, count 0 2006.173.06:24:56.98#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.06:24:56.98#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.06:24:56.98#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.06:24:56.98#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.06:24:56.98$vck44/valo=6,814.99 2006.173.06:24:56.98#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.06:24:56.98#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.06:24:56.98#ibcon#ireg 17 cls_cnt 0 2006.173.06:24:56.98#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.06:24:56.98#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.06:24:56.98#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.06:24:56.98#ibcon#enter wrdev, iclass 13, count 0 2006.173.06:24:56.98#ibcon#first serial, iclass 13, count 0 2006.173.06:24:56.98#ibcon#enter sib2, iclass 13, count 0 2006.173.06:24:56.98#ibcon#flushed, iclass 13, count 0 2006.173.06:24:56.98#ibcon#about to write, iclass 13, count 0 2006.173.06:24:56.98#ibcon#wrote, iclass 13, count 0 2006.173.06:24:56.98#ibcon#about to read 3, iclass 13, count 0 2006.173.06:24:57.00#ibcon#read 3, iclass 13, count 0 2006.173.06:24:57.00#ibcon#about to read 4, iclass 13, count 0 2006.173.06:24:57.00#ibcon#read 4, iclass 13, count 0 2006.173.06:24:57.00#ibcon#about to read 5, iclass 13, count 0 2006.173.06:24:57.00#ibcon#read 5, iclass 13, count 0 2006.173.06:24:57.00#ibcon#about to read 6, iclass 13, count 0 2006.173.06:24:57.00#ibcon#read 6, iclass 13, count 0 2006.173.06:24:57.00#ibcon#end of sib2, iclass 13, count 0 2006.173.06:24:57.00#ibcon#*mode == 0, iclass 13, count 0 2006.173.06:24:57.00#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.06:24:57.00#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.06:24:57.00#ibcon#*before write, iclass 13, count 0 2006.173.06:24:57.00#ibcon#enter sib2, iclass 13, count 0 2006.173.06:24:57.00#ibcon#flushed, iclass 13, count 0 2006.173.06:24:57.00#ibcon#about to write, iclass 13, count 0 2006.173.06:24:57.00#ibcon#wrote, iclass 13, count 0 2006.173.06:24:57.00#ibcon#about to read 3, iclass 13, count 0 2006.173.06:24:57.04#ibcon#read 3, iclass 13, count 0 2006.173.06:24:57.04#ibcon#about to read 4, iclass 13, count 0 2006.173.06:24:57.04#ibcon#read 4, iclass 13, count 0 2006.173.06:24:57.04#ibcon#about to read 5, iclass 13, count 0 2006.173.06:24:57.04#ibcon#read 5, iclass 13, count 0 2006.173.06:24:57.04#ibcon#about to read 6, iclass 13, count 0 2006.173.06:24:57.04#ibcon#read 6, iclass 13, count 0 2006.173.06:24:57.04#ibcon#end of sib2, iclass 13, count 0 2006.173.06:24:57.04#ibcon#*after write, iclass 13, count 0 2006.173.06:24:57.04#ibcon#*before return 0, iclass 13, count 0 2006.173.06:24:57.04#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.06:24:57.04#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.06:24:57.04#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.06:24:57.04#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.06:24:57.04$vck44/va=6,3 2006.173.06:24:57.04#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.06:24:57.04#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.06:24:57.04#ibcon#ireg 11 cls_cnt 2 2006.173.06:24:57.04#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.06:24:57.10#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.06:24:57.10#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.06:24:57.10#ibcon#enter wrdev, iclass 15, count 2 2006.173.06:24:57.10#ibcon#first serial, iclass 15, count 2 2006.173.06:24:57.10#ibcon#enter sib2, iclass 15, count 2 2006.173.06:24:57.10#ibcon#flushed, iclass 15, count 2 2006.173.06:24:57.10#ibcon#about to write, iclass 15, count 2 2006.173.06:24:57.10#ibcon#wrote, iclass 15, count 2 2006.173.06:24:57.10#ibcon#about to read 3, iclass 15, count 2 2006.173.06:24:57.12#ibcon#read 3, iclass 15, count 2 2006.173.06:24:57.12#ibcon#about to read 4, iclass 15, count 2 2006.173.06:24:57.12#ibcon#read 4, iclass 15, count 2 2006.173.06:24:57.12#ibcon#about to read 5, iclass 15, count 2 2006.173.06:24:57.12#ibcon#read 5, iclass 15, count 2 2006.173.06:24:57.12#ibcon#about to read 6, iclass 15, count 2 2006.173.06:24:57.12#ibcon#read 6, iclass 15, count 2 2006.173.06:24:57.12#ibcon#end of sib2, iclass 15, count 2 2006.173.06:24:57.12#ibcon#*mode == 0, iclass 15, count 2 2006.173.06:24:57.12#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.06:24:57.12#ibcon#[25=AT06-03\r\n] 2006.173.06:24:57.12#ibcon#*before write, iclass 15, count 2 2006.173.06:24:57.12#ibcon#enter sib2, iclass 15, count 2 2006.173.06:24:57.12#ibcon#flushed, iclass 15, count 2 2006.173.06:24:57.12#ibcon#about to write, iclass 15, count 2 2006.173.06:24:57.12#ibcon#wrote, iclass 15, count 2 2006.173.06:24:57.12#ibcon#about to read 3, iclass 15, count 2 2006.173.06:24:57.15#ibcon#read 3, iclass 15, count 2 2006.173.06:24:57.15#ibcon#about to read 4, iclass 15, count 2 2006.173.06:24:57.15#ibcon#read 4, iclass 15, count 2 2006.173.06:24:57.15#ibcon#about to read 5, iclass 15, count 2 2006.173.06:24:57.15#ibcon#read 5, iclass 15, count 2 2006.173.06:24:57.15#ibcon#about to read 6, iclass 15, count 2 2006.173.06:24:57.15#ibcon#read 6, iclass 15, count 2 2006.173.06:24:57.15#ibcon#end of sib2, iclass 15, count 2 2006.173.06:24:57.15#ibcon#*after write, iclass 15, count 2 2006.173.06:24:57.15#ibcon#*before return 0, iclass 15, count 2 2006.173.06:24:57.15#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.06:24:57.15#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.06:24:57.15#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.06:24:57.15#ibcon#ireg 7 cls_cnt 0 2006.173.06:24:57.15#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.06:24:57.27#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.06:24:57.27#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.06:24:57.27#ibcon#enter wrdev, iclass 15, count 0 2006.173.06:24:57.27#ibcon#first serial, iclass 15, count 0 2006.173.06:24:57.27#ibcon#enter sib2, iclass 15, count 0 2006.173.06:24:57.27#ibcon#flushed, iclass 15, count 0 2006.173.06:24:57.27#ibcon#about to write, iclass 15, count 0 2006.173.06:24:57.27#ibcon#wrote, iclass 15, count 0 2006.173.06:24:57.27#ibcon#about to read 3, iclass 15, count 0 2006.173.06:24:57.29#ibcon#read 3, iclass 15, count 0 2006.173.06:24:57.29#ibcon#about to read 4, iclass 15, count 0 2006.173.06:24:57.29#ibcon#read 4, iclass 15, count 0 2006.173.06:24:57.29#ibcon#about to read 5, iclass 15, count 0 2006.173.06:24:57.29#ibcon#read 5, iclass 15, count 0 2006.173.06:24:57.29#ibcon#about to read 6, iclass 15, count 0 2006.173.06:24:57.29#ibcon#read 6, iclass 15, count 0 2006.173.06:24:57.29#ibcon#end of sib2, iclass 15, count 0 2006.173.06:24:57.29#ibcon#*mode == 0, iclass 15, count 0 2006.173.06:24:57.29#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.06:24:57.29#ibcon#[25=USB\r\n] 2006.173.06:24:57.29#ibcon#*before write, iclass 15, count 0 2006.173.06:24:57.29#ibcon#enter sib2, iclass 15, count 0 2006.173.06:24:57.29#ibcon#flushed, iclass 15, count 0 2006.173.06:24:57.29#ibcon#about to write, iclass 15, count 0 2006.173.06:24:57.29#ibcon#wrote, iclass 15, count 0 2006.173.06:24:57.29#ibcon#about to read 3, iclass 15, count 0 2006.173.06:24:57.32#ibcon#read 3, iclass 15, count 0 2006.173.06:24:57.32#ibcon#about to read 4, iclass 15, count 0 2006.173.06:24:57.32#ibcon#read 4, iclass 15, count 0 2006.173.06:24:57.32#ibcon#about to read 5, iclass 15, count 0 2006.173.06:24:57.32#ibcon#read 5, iclass 15, count 0 2006.173.06:24:57.32#ibcon#about to read 6, iclass 15, count 0 2006.173.06:24:57.32#ibcon#read 6, iclass 15, count 0 2006.173.06:24:57.32#ibcon#end of sib2, iclass 15, count 0 2006.173.06:24:57.32#ibcon#*after write, iclass 15, count 0 2006.173.06:24:57.32#ibcon#*before return 0, iclass 15, count 0 2006.173.06:24:57.32#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.06:24:57.32#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.06:24:57.32#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.06:24:57.32#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.06:24:57.32$vck44/valo=7,864.99 2006.173.06:24:57.32#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.06:24:57.32#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.06:24:57.32#ibcon#ireg 17 cls_cnt 0 2006.173.06:24:57.32#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.06:24:57.32#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.06:24:57.32#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.06:24:57.32#ibcon#enter wrdev, iclass 17, count 0 2006.173.06:24:57.32#ibcon#first serial, iclass 17, count 0 2006.173.06:24:57.32#ibcon#enter sib2, iclass 17, count 0 2006.173.06:24:57.32#ibcon#flushed, iclass 17, count 0 2006.173.06:24:57.32#ibcon#about to write, iclass 17, count 0 2006.173.06:24:57.32#ibcon#wrote, iclass 17, count 0 2006.173.06:24:57.32#ibcon#about to read 3, iclass 17, count 0 2006.173.06:24:57.34#ibcon#read 3, iclass 17, count 0 2006.173.06:24:57.34#ibcon#about to read 4, iclass 17, count 0 2006.173.06:24:57.34#ibcon#read 4, iclass 17, count 0 2006.173.06:24:57.34#ibcon#about to read 5, iclass 17, count 0 2006.173.06:24:57.34#ibcon#read 5, iclass 17, count 0 2006.173.06:24:57.34#ibcon#about to read 6, iclass 17, count 0 2006.173.06:24:57.34#ibcon#read 6, iclass 17, count 0 2006.173.06:24:57.34#ibcon#end of sib2, iclass 17, count 0 2006.173.06:24:57.34#ibcon#*mode == 0, iclass 17, count 0 2006.173.06:24:57.34#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.06:24:57.34#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.06:24:57.34#ibcon#*before write, iclass 17, count 0 2006.173.06:24:57.34#ibcon#enter sib2, iclass 17, count 0 2006.173.06:24:57.34#ibcon#flushed, iclass 17, count 0 2006.173.06:24:57.34#ibcon#about to write, iclass 17, count 0 2006.173.06:24:57.34#ibcon#wrote, iclass 17, count 0 2006.173.06:24:57.34#ibcon#about to read 3, iclass 17, count 0 2006.173.06:24:57.38#ibcon#read 3, iclass 17, count 0 2006.173.06:24:57.38#ibcon#about to read 4, iclass 17, count 0 2006.173.06:24:57.38#ibcon#read 4, iclass 17, count 0 2006.173.06:24:57.38#ibcon#about to read 5, iclass 17, count 0 2006.173.06:24:57.38#ibcon#read 5, iclass 17, count 0 2006.173.06:24:57.38#ibcon#about to read 6, iclass 17, count 0 2006.173.06:24:57.38#ibcon#read 6, iclass 17, count 0 2006.173.06:24:57.38#ibcon#end of sib2, iclass 17, count 0 2006.173.06:24:57.38#ibcon#*after write, iclass 17, count 0 2006.173.06:24:57.38#ibcon#*before return 0, iclass 17, count 0 2006.173.06:24:57.38#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.06:24:57.38#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.06:24:57.38#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.06:24:57.38#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.06:24:57.38$vck44/va=7,4 2006.173.06:24:57.38#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.06:24:57.38#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.06:24:57.38#ibcon#ireg 11 cls_cnt 2 2006.173.06:24:57.38#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.06:24:57.44#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.06:24:57.44#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.06:24:57.44#ibcon#enter wrdev, iclass 19, count 2 2006.173.06:24:57.44#ibcon#first serial, iclass 19, count 2 2006.173.06:24:57.44#ibcon#enter sib2, iclass 19, count 2 2006.173.06:24:57.44#ibcon#flushed, iclass 19, count 2 2006.173.06:24:57.44#ibcon#about to write, iclass 19, count 2 2006.173.06:24:57.44#ibcon#wrote, iclass 19, count 2 2006.173.06:24:57.44#ibcon#about to read 3, iclass 19, count 2 2006.173.06:24:57.46#ibcon#read 3, iclass 19, count 2 2006.173.06:24:57.46#ibcon#about to read 4, iclass 19, count 2 2006.173.06:24:57.46#ibcon#read 4, iclass 19, count 2 2006.173.06:24:57.46#ibcon#about to read 5, iclass 19, count 2 2006.173.06:24:57.46#ibcon#read 5, iclass 19, count 2 2006.173.06:24:57.46#ibcon#about to read 6, iclass 19, count 2 2006.173.06:24:57.46#ibcon#read 6, iclass 19, count 2 2006.173.06:24:57.46#ibcon#end of sib2, iclass 19, count 2 2006.173.06:24:57.46#ibcon#*mode == 0, iclass 19, count 2 2006.173.06:24:57.46#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.06:24:57.46#ibcon#[25=AT07-04\r\n] 2006.173.06:24:57.46#ibcon#*before write, iclass 19, count 2 2006.173.06:24:57.46#ibcon#enter sib2, iclass 19, count 2 2006.173.06:24:57.46#ibcon#flushed, iclass 19, count 2 2006.173.06:24:57.46#ibcon#about to write, iclass 19, count 2 2006.173.06:24:57.46#ibcon#wrote, iclass 19, count 2 2006.173.06:24:57.46#ibcon#about to read 3, iclass 19, count 2 2006.173.06:24:57.49#ibcon#read 3, iclass 19, count 2 2006.173.06:24:57.49#ibcon#about to read 4, iclass 19, count 2 2006.173.06:24:57.49#ibcon#read 4, iclass 19, count 2 2006.173.06:24:57.49#ibcon#about to read 5, iclass 19, count 2 2006.173.06:24:57.49#ibcon#read 5, iclass 19, count 2 2006.173.06:24:57.49#ibcon#about to read 6, iclass 19, count 2 2006.173.06:24:57.49#ibcon#read 6, iclass 19, count 2 2006.173.06:24:57.49#ibcon#end of sib2, iclass 19, count 2 2006.173.06:24:57.49#ibcon#*after write, iclass 19, count 2 2006.173.06:24:57.49#ibcon#*before return 0, iclass 19, count 2 2006.173.06:24:57.49#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.06:24:57.49#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.06:24:57.49#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.06:24:57.49#ibcon#ireg 7 cls_cnt 0 2006.173.06:24:57.49#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.06:24:57.61#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.06:24:57.61#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.06:24:57.61#ibcon#enter wrdev, iclass 19, count 0 2006.173.06:24:57.61#ibcon#first serial, iclass 19, count 0 2006.173.06:24:57.61#ibcon#enter sib2, iclass 19, count 0 2006.173.06:24:57.61#ibcon#flushed, iclass 19, count 0 2006.173.06:24:57.61#ibcon#about to write, iclass 19, count 0 2006.173.06:24:57.61#ibcon#wrote, iclass 19, count 0 2006.173.06:24:57.61#ibcon#about to read 3, iclass 19, count 0 2006.173.06:24:57.63#ibcon#read 3, iclass 19, count 0 2006.173.06:24:57.63#ibcon#about to read 4, iclass 19, count 0 2006.173.06:24:57.63#ibcon#read 4, iclass 19, count 0 2006.173.06:24:57.63#ibcon#about to read 5, iclass 19, count 0 2006.173.06:24:57.63#ibcon#read 5, iclass 19, count 0 2006.173.06:24:57.63#ibcon#about to read 6, iclass 19, count 0 2006.173.06:24:57.63#ibcon#read 6, iclass 19, count 0 2006.173.06:24:57.63#ibcon#end of sib2, iclass 19, count 0 2006.173.06:24:57.63#ibcon#*mode == 0, iclass 19, count 0 2006.173.06:24:57.63#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.06:24:57.63#ibcon#[25=USB\r\n] 2006.173.06:24:57.63#ibcon#*before write, iclass 19, count 0 2006.173.06:24:57.63#ibcon#enter sib2, iclass 19, count 0 2006.173.06:24:57.63#ibcon#flushed, iclass 19, count 0 2006.173.06:24:57.63#ibcon#about to write, iclass 19, count 0 2006.173.06:24:57.63#ibcon#wrote, iclass 19, count 0 2006.173.06:24:57.63#ibcon#about to read 3, iclass 19, count 0 2006.173.06:24:57.66#ibcon#read 3, iclass 19, count 0 2006.173.06:24:57.66#ibcon#about to read 4, iclass 19, count 0 2006.173.06:24:57.66#ibcon#read 4, iclass 19, count 0 2006.173.06:24:57.66#ibcon#about to read 5, iclass 19, count 0 2006.173.06:24:57.66#ibcon#read 5, iclass 19, count 0 2006.173.06:24:57.66#ibcon#about to read 6, iclass 19, count 0 2006.173.06:24:57.66#ibcon#read 6, iclass 19, count 0 2006.173.06:24:57.66#ibcon#end of sib2, iclass 19, count 0 2006.173.06:24:57.66#ibcon#*after write, iclass 19, count 0 2006.173.06:24:57.66#ibcon#*before return 0, iclass 19, count 0 2006.173.06:24:57.66#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.06:24:57.66#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.06:24:57.66#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.06:24:57.66#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.06:24:57.66$vck44/valo=8,884.99 2006.173.06:24:57.66#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.06:24:57.66#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.06:24:57.66#ibcon#ireg 17 cls_cnt 0 2006.173.06:24:57.66#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.06:24:57.66#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.06:24:57.66#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.06:24:57.66#ibcon#enter wrdev, iclass 21, count 0 2006.173.06:24:57.66#ibcon#first serial, iclass 21, count 0 2006.173.06:24:57.66#ibcon#enter sib2, iclass 21, count 0 2006.173.06:24:57.66#ibcon#flushed, iclass 21, count 0 2006.173.06:24:57.66#ibcon#about to write, iclass 21, count 0 2006.173.06:24:57.66#ibcon#wrote, iclass 21, count 0 2006.173.06:24:57.66#ibcon#about to read 3, iclass 21, count 0 2006.173.06:24:57.68#ibcon#read 3, iclass 21, count 0 2006.173.06:24:57.68#ibcon#about to read 4, iclass 21, count 0 2006.173.06:24:57.68#ibcon#read 4, iclass 21, count 0 2006.173.06:24:57.68#ibcon#about to read 5, iclass 21, count 0 2006.173.06:24:57.68#ibcon#read 5, iclass 21, count 0 2006.173.06:24:57.68#ibcon#about to read 6, iclass 21, count 0 2006.173.06:24:57.68#ibcon#read 6, iclass 21, count 0 2006.173.06:24:57.68#ibcon#end of sib2, iclass 21, count 0 2006.173.06:24:57.68#ibcon#*mode == 0, iclass 21, count 0 2006.173.06:24:57.68#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.06:24:57.68#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.06:24:57.68#ibcon#*before write, iclass 21, count 0 2006.173.06:24:57.68#ibcon#enter sib2, iclass 21, count 0 2006.173.06:24:57.68#ibcon#flushed, iclass 21, count 0 2006.173.06:24:57.68#ibcon#about to write, iclass 21, count 0 2006.173.06:24:57.68#ibcon#wrote, iclass 21, count 0 2006.173.06:24:57.68#ibcon#about to read 3, iclass 21, count 0 2006.173.06:24:57.72#ibcon#read 3, iclass 21, count 0 2006.173.06:24:57.72#ibcon#about to read 4, iclass 21, count 0 2006.173.06:24:57.72#ibcon#read 4, iclass 21, count 0 2006.173.06:24:57.72#ibcon#about to read 5, iclass 21, count 0 2006.173.06:24:57.72#ibcon#read 5, iclass 21, count 0 2006.173.06:24:57.72#ibcon#about to read 6, iclass 21, count 0 2006.173.06:24:57.72#ibcon#read 6, iclass 21, count 0 2006.173.06:24:57.72#ibcon#end of sib2, iclass 21, count 0 2006.173.06:24:57.72#ibcon#*after write, iclass 21, count 0 2006.173.06:24:57.72#ibcon#*before return 0, iclass 21, count 0 2006.173.06:24:57.72#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.06:24:57.72#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.06:24:57.72#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.06:24:57.72#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.06:24:57.72$vck44/va=8,4 2006.173.06:24:57.72#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.06:24:57.72#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.06:24:57.72#ibcon#ireg 11 cls_cnt 2 2006.173.06:24:57.72#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.06:24:57.78#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.06:24:57.78#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.06:24:57.78#ibcon#enter wrdev, iclass 23, count 2 2006.173.06:24:57.78#ibcon#first serial, iclass 23, count 2 2006.173.06:24:57.78#ibcon#enter sib2, iclass 23, count 2 2006.173.06:24:57.78#ibcon#flushed, iclass 23, count 2 2006.173.06:24:57.78#ibcon#about to write, iclass 23, count 2 2006.173.06:24:57.78#ibcon#wrote, iclass 23, count 2 2006.173.06:24:57.78#ibcon#about to read 3, iclass 23, count 2 2006.173.06:24:57.80#ibcon#read 3, iclass 23, count 2 2006.173.06:24:57.80#ibcon#about to read 4, iclass 23, count 2 2006.173.06:24:57.80#ibcon#read 4, iclass 23, count 2 2006.173.06:24:57.80#ibcon#about to read 5, iclass 23, count 2 2006.173.06:24:57.80#ibcon#read 5, iclass 23, count 2 2006.173.06:24:57.80#ibcon#about to read 6, iclass 23, count 2 2006.173.06:24:57.80#ibcon#read 6, iclass 23, count 2 2006.173.06:24:57.80#ibcon#end of sib2, iclass 23, count 2 2006.173.06:24:57.80#ibcon#*mode == 0, iclass 23, count 2 2006.173.06:24:57.80#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.06:24:57.80#ibcon#[25=AT08-04\r\n] 2006.173.06:24:57.80#ibcon#*before write, iclass 23, count 2 2006.173.06:24:57.80#ibcon#enter sib2, iclass 23, count 2 2006.173.06:24:57.80#ibcon#flushed, iclass 23, count 2 2006.173.06:24:57.80#ibcon#about to write, iclass 23, count 2 2006.173.06:24:57.80#ibcon#wrote, iclass 23, count 2 2006.173.06:24:57.80#ibcon#about to read 3, iclass 23, count 2 2006.173.06:24:57.83#ibcon#read 3, iclass 23, count 2 2006.173.06:24:57.83#ibcon#about to read 4, iclass 23, count 2 2006.173.06:24:57.83#ibcon#read 4, iclass 23, count 2 2006.173.06:24:57.83#ibcon#about to read 5, iclass 23, count 2 2006.173.06:24:57.83#ibcon#read 5, iclass 23, count 2 2006.173.06:24:57.83#ibcon#about to read 6, iclass 23, count 2 2006.173.06:24:57.83#ibcon#read 6, iclass 23, count 2 2006.173.06:24:57.83#ibcon#end of sib2, iclass 23, count 2 2006.173.06:24:57.83#ibcon#*after write, iclass 23, count 2 2006.173.06:24:57.83#ibcon#*before return 0, iclass 23, count 2 2006.173.06:24:57.83#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.06:24:57.83#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.06:24:57.83#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.06:24:57.83#ibcon#ireg 7 cls_cnt 0 2006.173.06:24:57.83#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.06:24:57.95#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.06:24:57.95#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.06:24:57.95#ibcon#enter wrdev, iclass 23, count 0 2006.173.06:24:57.95#ibcon#first serial, iclass 23, count 0 2006.173.06:24:57.95#ibcon#enter sib2, iclass 23, count 0 2006.173.06:24:57.95#ibcon#flushed, iclass 23, count 0 2006.173.06:24:57.95#ibcon#about to write, iclass 23, count 0 2006.173.06:24:57.95#ibcon#wrote, iclass 23, count 0 2006.173.06:24:57.95#ibcon#about to read 3, iclass 23, count 0 2006.173.06:24:57.97#ibcon#read 3, iclass 23, count 0 2006.173.06:24:57.97#ibcon#about to read 4, iclass 23, count 0 2006.173.06:24:57.97#ibcon#read 4, iclass 23, count 0 2006.173.06:24:57.97#ibcon#about to read 5, iclass 23, count 0 2006.173.06:24:57.97#ibcon#read 5, iclass 23, count 0 2006.173.06:24:57.97#ibcon#about to read 6, iclass 23, count 0 2006.173.06:24:57.97#ibcon#read 6, iclass 23, count 0 2006.173.06:24:57.97#ibcon#end of sib2, iclass 23, count 0 2006.173.06:24:57.97#ibcon#*mode == 0, iclass 23, count 0 2006.173.06:24:57.97#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.06:24:57.97#ibcon#[25=USB\r\n] 2006.173.06:24:57.97#ibcon#*before write, iclass 23, count 0 2006.173.06:24:57.97#ibcon#enter sib2, iclass 23, count 0 2006.173.06:24:57.97#ibcon#flushed, iclass 23, count 0 2006.173.06:24:57.97#ibcon#about to write, iclass 23, count 0 2006.173.06:24:57.97#ibcon#wrote, iclass 23, count 0 2006.173.06:24:57.97#ibcon#about to read 3, iclass 23, count 0 2006.173.06:24:58.00#ibcon#read 3, iclass 23, count 0 2006.173.06:24:58.00#ibcon#about to read 4, iclass 23, count 0 2006.173.06:24:58.00#ibcon#read 4, iclass 23, count 0 2006.173.06:24:58.00#ibcon#about to read 5, iclass 23, count 0 2006.173.06:24:58.00#ibcon#read 5, iclass 23, count 0 2006.173.06:24:58.00#ibcon#about to read 6, iclass 23, count 0 2006.173.06:24:58.00#ibcon#read 6, iclass 23, count 0 2006.173.06:24:58.00#ibcon#end of sib2, iclass 23, count 0 2006.173.06:24:58.00#ibcon#*after write, iclass 23, count 0 2006.173.06:24:58.00#ibcon#*before return 0, iclass 23, count 0 2006.173.06:24:58.00#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.06:24:58.00#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.06:24:58.00#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.06:24:58.00#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.06:24:58.00$vck44/vblo=1,629.99 2006.173.06:24:58.00#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.06:24:58.00#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.06:24:58.00#ibcon#ireg 17 cls_cnt 0 2006.173.06:24:58.00#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.06:24:58.00#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.06:24:58.00#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.06:24:58.00#ibcon#enter wrdev, iclass 25, count 0 2006.173.06:24:58.00#ibcon#first serial, iclass 25, count 0 2006.173.06:24:58.00#ibcon#enter sib2, iclass 25, count 0 2006.173.06:24:58.00#ibcon#flushed, iclass 25, count 0 2006.173.06:24:58.00#ibcon#about to write, iclass 25, count 0 2006.173.06:24:58.00#ibcon#wrote, iclass 25, count 0 2006.173.06:24:58.00#ibcon#about to read 3, iclass 25, count 0 2006.173.06:24:58.02#ibcon#read 3, iclass 25, count 0 2006.173.06:24:58.02#ibcon#about to read 4, iclass 25, count 0 2006.173.06:24:58.02#ibcon#read 4, iclass 25, count 0 2006.173.06:24:58.02#ibcon#about to read 5, iclass 25, count 0 2006.173.06:24:58.02#ibcon#read 5, iclass 25, count 0 2006.173.06:24:58.02#ibcon#about to read 6, iclass 25, count 0 2006.173.06:24:58.02#ibcon#read 6, iclass 25, count 0 2006.173.06:24:58.02#ibcon#end of sib2, iclass 25, count 0 2006.173.06:24:58.02#ibcon#*mode == 0, iclass 25, count 0 2006.173.06:24:58.02#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.06:24:58.02#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.06:24:58.02#ibcon#*before write, iclass 25, count 0 2006.173.06:24:58.02#ibcon#enter sib2, iclass 25, count 0 2006.173.06:24:58.02#ibcon#flushed, iclass 25, count 0 2006.173.06:24:58.02#ibcon#about to write, iclass 25, count 0 2006.173.06:24:58.02#ibcon#wrote, iclass 25, count 0 2006.173.06:24:58.02#ibcon#about to read 3, iclass 25, count 0 2006.173.06:24:58.06#ibcon#read 3, iclass 25, count 0 2006.173.06:24:58.06#ibcon#about to read 4, iclass 25, count 0 2006.173.06:24:58.06#ibcon#read 4, iclass 25, count 0 2006.173.06:24:58.06#ibcon#about to read 5, iclass 25, count 0 2006.173.06:24:58.06#ibcon#read 5, iclass 25, count 0 2006.173.06:24:58.06#ibcon#about to read 6, iclass 25, count 0 2006.173.06:24:58.06#ibcon#read 6, iclass 25, count 0 2006.173.06:24:58.06#ibcon#end of sib2, iclass 25, count 0 2006.173.06:24:58.06#ibcon#*after write, iclass 25, count 0 2006.173.06:24:58.06#ibcon#*before return 0, iclass 25, count 0 2006.173.06:24:58.06#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.06:24:58.06#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.06:24:58.06#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.06:24:58.06#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.06:24:58.06$vck44/vb=1,4 2006.173.06:24:58.06#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.06:24:58.06#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.06:24:58.06#ibcon#ireg 11 cls_cnt 2 2006.173.06:24:58.06#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.06:24:58.06#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.06:24:58.06#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.06:24:58.06#ibcon#enter wrdev, iclass 27, count 2 2006.173.06:24:58.06#ibcon#first serial, iclass 27, count 2 2006.173.06:24:58.06#ibcon#enter sib2, iclass 27, count 2 2006.173.06:24:58.06#ibcon#flushed, iclass 27, count 2 2006.173.06:24:58.06#ibcon#about to write, iclass 27, count 2 2006.173.06:24:58.06#ibcon#wrote, iclass 27, count 2 2006.173.06:24:58.06#ibcon#about to read 3, iclass 27, count 2 2006.173.06:24:58.08#ibcon#read 3, iclass 27, count 2 2006.173.06:24:58.08#ibcon#about to read 4, iclass 27, count 2 2006.173.06:24:58.08#ibcon#read 4, iclass 27, count 2 2006.173.06:24:58.08#ibcon#about to read 5, iclass 27, count 2 2006.173.06:24:58.08#ibcon#read 5, iclass 27, count 2 2006.173.06:24:58.08#ibcon#about to read 6, iclass 27, count 2 2006.173.06:24:58.08#ibcon#read 6, iclass 27, count 2 2006.173.06:24:58.08#ibcon#end of sib2, iclass 27, count 2 2006.173.06:24:58.08#ibcon#*mode == 0, iclass 27, count 2 2006.173.06:24:58.08#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.06:24:58.08#ibcon#[27=AT01-04\r\n] 2006.173.06:24:58.08#ibcon#*before write, iclass 27, count 2 2006.173.06:24:58.08#ibcon#enter sib2, iclass 27, count 2 2006.173.06:24:58.08#ibcon#flushed, iclass 27, count 2 2006.173.06:24:58.08#ibcon#about to write, iclass 27, count 2 2006.173.06:24:58.08#ibcon#wrote, iclass 27, count 2 2006.173.06:24:58.08#ibcon#about to read 3, iclass 27, count 2 2006.173.06:24:58.11#ibcon#read 3, iclass 27, count 2 2006.173.06:24:58.11#ibcon#about to read 4, iclass 27, count 2 2006.173.06:24:58.11#ibcon#read 4, iclass 27, count 2 2006.173.06:24:58.11#ibcon#about to read 5, iclass 27, count 2 2006.173.06:24:58.11#ibcon#read 5, iclass 27, count 2 2006.173.06:24:58.11#ibcon#about to read 6, iclass 27, count 2 2006.173.06:24:58.11#ibcon#read 6, iclass 27, count 2 2006.173.06:24:58.11#ibcon#end of sib2, iclass 27, count 2 2006.173.06:24:58.11#ibcon#*after write, iclass 27, count 2 2006.173.06:24:58.11#ibcon#*before return 0, iclass 27, count 2 2006.173.06:24:58.11#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.06:24:58.11#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.06:24:58.11#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.06:24:58.11#ibcon#ireg 7 cls_cnt 0 2006.173.06:24:58.11#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.06:24:58.23#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.06:24:58.23#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.06:24:58.23#ibcon#enter wrdev, iclass 27, count 0 2006.173.06:24:58.23#ibcon#first serial, iclass 27, count 0 2006.173.06:24:58.23#ibcon#enter sib2, iclass 27, count 0 2006.173.06:24:58.23#ibcon#flushed, iclass 27, count 0 2006.173.06:24:58.23#ibcon#about to write, iclass 27, count 0 2006.173.06:24:58.23#ibcon#wrote, iclass 27, count 0 2006.173.06:24:58.23#ibcon#about to read 3, iclass 27, count 0 2006.173.06:24:58.25#ibcon#read 3, iclass 27, count 0 2006.173.06:24:58.25#ibcon#about to read 4, iclass 27, count 0 2006.173.06:24:58.25#ibcon#read 4, iclass 27, count 0 2006.173.06:24:58.25#ibcon#about to read 5, iclass 27, count 0 2006.173.06:24:58.25#ibcon#read 5, iclass 27, count 0 2006.173.06:24:58.25#ibcon#about to read 6, iclass 27, count 0 2006.173.06:24:58.25#ibcon#read 6, iclass 27, count 0 2006.173.06:24:58.25#ibcon#end of sib2, iclass 27, count 0 2006.173.06:24:58.25#ibcon#*mode == 0, iclass 27, count 0 2006.173.06:24:58.25#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.06:24:58.25#ibcon#[27=USB\r\n] 2006.173.06:24:58.25#ibcon#*before write, iclass 27, count 0 2006.173.06:24:58.25#ibcon#enter sib2, iclass 27, count 0 2006.173.06:24:58.25#ibcon#flushed, iclass 27, count 0 2006.173.06:24:58.25#ibcon#about to write, iclass 27, count 0 2006.173.06:24:58.25#ibcon#wrote, iclass 27, count 0 2006.173.06:24:58.25#ibcon#about to read 3, iclass 27, count 0 2006.173.06:24:58.28#ibcon#read 3, iclass 27, count 0 2006.173.06:24:58.28#ibcon#about to read 4, iclass 27, count 0 2006.173.06:24:58.28#ibcon#read 4, iclass 27, count 0 2006.173.06:24:58.28#ibcon#about to read 5, iclass 27, count 0 2006.173.06:24:58.28#ibcon#read 5, iclass 27, count 0 2006.173.06:24:58.28#ibcon#about to read 6, iclass 27, count 0 2006.173.06:24:58.28#ibcon#read 6, iclass 27, count 0 2006.173.06:24:58.28#ibcon#end of sib2, iclass 27, count 0 2006.173.06:24:58.28#ibcon#*after write, iclass 27, count 0 2006.173.06:24:58.28#ibcon#*before return 0, iclass 27, count 0 2006.173.06:24:58.28#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.06:24:58.28#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.06:24:58.28#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.06:24:58.28#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.06:24:58.28$vck44/vblo=2,634.99 2006.173.06:24:58.28#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.06:24:58.28#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.06:24:58.28#ibcon#ireg 17 cls_cnt 0 2006.173.06:24:58.28#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.06:24:58.28#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.06:24:58.28#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.06:24:58.28#ibcon#enter wrdev, iclass 29, count 0 2006.173.06:24:58.28#ibcon#first serial, iclass 29, count 0 2006.173.06:24:58.28#ibcon#enter sib2, iclass 29, count 0 2006.173.06:24:58.28#ibcon#flushed, iclass 29, count 0 2006.173.06:24:58.28#ibcon#about to write, iclass 29, count 0 2006.173.06:24:58.28#ibcon#wrote, iclass 29, count 0 2006.173.06:24:58.28#ibcon#about to read 3, iclass 29, count 0 2006.173.06:24:58.30#ibcon#read 3, iclass 29, count 0 2006.173.06:24:58.30#ibcon#about to read 4, iclass 29, count 0 2006.173.06:24:58.30#ibcon#read 4, iclass 29, count 0 2006.173.06:24:58.30#ibcon#about to read 5, iclass 29, count 0 2006.173.06:24:58.30#ibcon#read 5, iclass 29, count 0 2006.173.06:24:58.30#ibcon#about to read 6, iclass 29, count 0 2006.173.06:24:58.30#ibcon#read 6, iclass 29, count 0 2006.173.06:24:58.30#ibcon#end of sib2, iclass 29, count 0 2006.173.06:24:58.30#ibcon#*mode == 0, iclass 29, count 0 2006.173.06:24:58.30#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.06:24:58.30#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.06:24:58.30#ibcon#*before write, iclass 29, count 0 2006.173.06:24:58.30#ibcon#enter sib2, iclass 29, count 0 2006.173.06:24:58.30#ibcon#flushed, iclass 29, count 0 2006.173.06:24:58.30#ibcon#about to write, iclass 29, count 0 2006.173.06:24:58.30#ibcon#wrote, iclass 29, count 0 2006.173.06:24:58.30#ibcon#about to read 3, iclass 29, count 0 2006.173.06:24:58.34#ibcon#read 3, iclass 29, count 0 2006.173.06:24:58.34#ibcon#about to read 4, iclass 29, count 0 2006.173.06:24:58.34#ibcon#read 4, iclass 29, count 0 2006.173.06:24:58.34#ibcon#about to read 5, iclass 29, count 0 2006.173.06:24:58.34#ibcon#read 5, iclass 29, count 0 2006.173.06:24:58.34#ibcon#about to read 6, iclass 29, count 0 2006.173.06:24:58.34#ibcon#read 6, iclass 29, count 0 2006.173.06:24:58.34#ibcon#end of sib2, iclass 29, count 0 2006.173.06:24:58.34#ibcon#*after write, iclass 29, count 0 2006.173.06:24:58.34#ibcon#*before return 0, iclass 29, count 0 2006.173.06:24:58.34#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.06:24:58.34#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.06:24:58.34#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.06:24:58.34#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.06:24:58.34$vck44/vb=2,4 2006.173.06:24:58.34#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.06:24:58.34#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.06:24:58.34#ibcon#ireg 11 cls_cnt 2 2006.173.06:24:58.34#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.06:24:58.40#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.06:24:58.40#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.06:24:58.40#ibcon#enter wrdev, iclass 31, count 2 2006.173.06:24:58.40#ibcon#first serial, iclass 31, count 2 2006.173.06:24:58.40#ibcon#enter sib2, iclass 31, count 2 2006.173.06:24:58.40#ibcon#flushed, iclass 31, count 2 2006.173.06:24:58.40#ibcon#about to write, iclass 31, count 2 2006.173.06:24:58.40#ibcon#wrote, iclass 31, count 2 2006.173.06:24:58.40#ibcon#about to read 3, iclass 31, count 2 2006.173.06:24:58.42#ibcon#read 3, iclass 31, count 2 2006.173.06:24:58.42#ibcon#about to read 4, iclass 31, count 2 2006.173.06:24:58.42#ibcon#read 4, iclass 31, count 2 2006.173.06:24:58.42#ibcon#about to read 5, iclass 31, count 2 2006.173.06:24:58.42#ibcon#read 5, iclass 31, count 2 2006.173.06:24:58.42#ibcon#about to read 6, iclass 31, count 2 2006.173.06:24:58.42#ibcon#read 6, iclass 31, count 2 2006.173.06:24:58.42#ibcon#end of sib2, iclass 31, count 2 2006.173.06:24:58.42#ibcon#*mode == 0, iclass 31, count 2 2006.173.06:24:58.42#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.06:24:58.42#ibcon#[27=AT02-04\r\n] 2006.173.06:24:58.42#ibcon#*before write, iclass 31, count 2 2006.173.06:24:58.42#ibcon#enter sib2, iclass 31, count 2 2006.173.06:24:58.42#ibcon#flushed, iclass 31, count 2 2006.173.06:24:58.42#ibcon#about to write, iclass 31, count 2 2006.173.06:24:58.42#ibcon#wrote, iclass 31, count 2 2006.173.06:24:58.42#ibcon#about to read 3, iclass 31, count 2 2006.173.06:24:58.45#ibcon#read 3, iclass 31, count 2 2006.173.06:24:58.45#ibcon#about to read 4, iclass 31, count 2 2006.173.06:24:58.45#ibcon#read 4, iclass 31, count 2 2006.173.06:24:58.45#ibcon#about to read 5, iclass 31, count 2 2006.173.06:24:58.45#ibcon#read 5, iclass 31, count 2 2006.173.06:24:58.45#ibcon#about to read 6, iclass 31, count 2 2006.173.06:24:58.45#ibcon#read 6, iclass 31, count 2 2006.173.06:24:58.45#ibcon#end of sib2, iclass 31, count 2 2006.173.06:24:58.45#ibcon#*after write, iclass 31, count 2 2006.173.06:24:58.45#ibcon#*before return 0, iclass 31, count 2 2006.173.06:24:58.45#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.06:24:58.45#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.06:24:58.45#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.06:24:58.45#ibcon#ireg 7 cls_cnt 0 2006.173.06:24:58.45#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.06:24:58.57#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.06:24:58.57#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.06:24:58.57#ibcon#enter wrdev, iclass 31, count 0 2006.173.06:24:58.57#ibcon#first serial, iclass 31, count 0 2006.173.06:24:58.57#ibcon#enter sib2, iclass 31, count 0 2006.173.06:24:58.57#ibcon#flushed, iclass 31, count 0 2006.173.06:24:58.57#ibcon#about to write, iclass 31, count 0 2006.173.06:24:58.57#ibcon#wrote, iclass 31, count 0 2006.173.06:24:58.57#ibcon#about to read 3, iclass 31, count 0 2006.173.06:24:58.59#ibcon#read 3, iclass 31, count 0 2006.173.06:24:58.59#ibcon#about to read 4, iclass 31, count 0 2006.173.06:24:58.59#ibcon#read 4, iclass 31, count 0 2006.173.06:24:58.59#ibcon#about to read 5, iclass 31, count 0 2006.173.06:24:58.59#ibcon#read 5, iclass 31, count 0 2006.173.06:24:58.59#ibcon#about to read 6, iclass 31, count 0 2006.173.06:24:58.59#ibcon#read 6, iclass 31, count 0 2006.173.06:24:58.59#ibcon#end of sib2, iclass 31, count 0 2006.173.06:24:58.59#ibcon#*mode == 0, iclass 31, count 0 2006.173.06:24:58.59#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.06:24:58.59#ibcon#[27=USB\r\n] 2006.173.06:24:58.59#ibcon#*before write, iclass 31, count 0 2006.173.06:24:58.59#ibcon#enter sib2, iclass 31, count 0 2006.173.06:24:58.59#ibcon#flushed, iclass 31, count 0 2006.173.06:24:58.59#ibcon#about to write, iclass 31, count 0 2006.173.06:24:58.59#ibcon#wrote, iclass 31, count 0 2006.173.06:24:58.59#ibcon#about to read 3, iclass 31, count 0 2006.173.06:24:58.62#ibcon#read 3, iclass 31, count 0 2006.173.06:24:58.62#ibcon#about to read 4, iclass 31, count 0 2006.173.06:24:58.62#ibcon#read 4, iclass 31, count 0 2006.173.06:24:58.62#ibcon#about to read 5, iclass 31, count 0 2006.173.06:24:58.62#ibcon#read 5, iclass 31, count 0 2006.173.06:24:58.62#ibcon#about to read 6, iclass 31, count 0 2006.173.06:24:58.62#ibcon#read 6, iclass 31, count 0 2006.173.06:24:58.62#ibcon#end of sib2, iclass 31, count 0 2006.173.06:24:58.62#ibcon#*after write, iclass 31, count 0 2006.173.06:24:58.62#ibcon#*before return 0, iclass 31, count 0 2006.173.06:24:58.62#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.06:24:58.62#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.06:24:58.62#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.06:24:58.62#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.06:24:58.62$vck44/vblo=3,649.99 2006.173.06:24:58.62#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.06:24:58.62#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.06:24:58.62#ibcon#ireg 17 cls_cnt 0 2006.173.06:24:58.62#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.06:24:58.62#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.06:24:58.62#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.06:24:58.62#ibcon#enter wrdev, iclass 33, count 0 2006.173.06:24:58.62#ibcon#first serial, iclass 33, count 0 2006.173.06:24:58.62#ibcon#enter sib2, iclass 33, count 0 2006.173.06:24:58.62#ibcon#flushed, iclass 33, count 0 2006.173.06:24:58.62#ibcon#about to write, iclass 33, count 0 2006.173.06:24:58.62#ibcon#wrote, iclass 33, count 0 2006.173.06:24:58.62#ibcon#about to read 3, iclass 33, count 0 2006.173.06:24:58.64#ibcon#read 3, iclass 33, count 0 2006.173.06:24:58.64#ibcon#about to read 4, iclass 33, count 0 2006.173.06:24:58.64#ibcon#read 4, iclass 33, count 0 2006.173.06:24:58.64#ibcon#about to read 5, iclass 33, count 0 2006.173.06:24:58.64#ibcon#read 5, iclass 33, count 0 2006.173.06:24:58.64#ibcon#about to read 6, iclass 33, count 0 2006.173.06:24:58.64#ibcon#read 6, iclass 33, count 0 2006.173.06:24:58.64#ibcon#end of sib2, iclass 33, count 0 2006.173.06:24:58.64#ibcon#*mode == 0, iclass 33, count 0 2006.173.06:24:58.64#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.06:24:58.64#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.06:24:58.64#ibcon#*before write, iclass 33, count 0 2006.173.06:24:58.64#ibcon#enter sib2, iclass 33, count 0 2006.173.06:24:58.64#ibcon#flushed, iclass 33, count 0 2006.173.06:24:58.64#ibcon#about to write, iclass 33, count 0 2006.173.06:24:58.64#ibcon#wrote, iclass 33, count 0 2006.173.06:24:58.64#ibcon#about to read 3, iclass 33, count 0 2006.173.06:24:58.68#ibcon#read 3, iclass 33, count 0 2006.173.06:24:58.68#ibcon#about to read 4, iclass 33, count 0 2006.173.06:24:58.68#ibcon#read 4, iclass 33, count 0 2006.173.06:24:58.68#ibcon#about to read 5, iclass 33, count 0 2006.173.06:24:58.68#ibcon#read 5, iclass 33, count 0 2006.173.06:24:58.68#ibcon#about to read 6, iclass 33, count 0 2006.173.06:24:58.68#ibcon#read 6, iclass 33, count 0 2006.173.06:24:58.68#ibcon#end of sib2, iclass 33, count 0 2006.173.06:24:58.68#ibcon#*after write, iclass 33, count 0 2006.173.06:24:58.68#ibcon#*before return 0, iclass 33, count 0 2006.173.06:24:58.68#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.06:24:58.68#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.06:24:58.68#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.06:24:58.68#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.06:24:58.68$vck44/vb=3,4 2006.173.06:24:58.68#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.06:24:58.68#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.06:24:58.68#ibcon#ireg 11 cls_cnt 2 2006.173.06:24:58.68#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.06:24:58.74#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.06:24:58.74#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.06:24:58.74#ibcon#enter wrdev, iclass 35, count 2 2006.173.06:24:58.74#ibcon#first serial, iclass 35, count 2 2006.173.06:24:58.74#ibcon#enter sib2, iclass 35, count 2 2006.173.06:24:58.74#ibcon#flushed, iclass 35, count 2 2006.173.06:24:58.74#ibcon#about to write, iclass 35, count 2 2006.173.06:24:58.74#ibcon#wrote, iclass 35, count 2 2006.173.06:24:58.74#ibcon#about to read 3, iclass 35, count 2 2006.173.06:24:58.76#ibcon#read 3, iclass 35, count 2 2006.173.06:24:58.76#ibcon#about to read 4, iclass 35, count 2 2006.173.06:24:58.76#ibcon#read 4, iclass 35, count 2 2006.173.06:24:58.76#ibcon#about to read 5, iclass 35, count 2 2006.173.06:24:58.76#ibcon#read 5, iclass 35, count 2 2006.173.06:24:58.76#ibcon#about to read 6, iclass 35, count 2 2006.173.06:24:58.76#ibcon#read 6, iclass 35, count 2 2006.173.06:24:58.76#ibcon#end of sib2, iclass 35, count 2 2006.173.06:24:58.76#ibcon#*mode == 0, iclass 35, count 2 2006.173.06:24:58.76#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.06:24:58.76#ibcon#[27=AT03-04\r\n] 2006.173.06:24:58.76#ibcon#*before write, iclass 35, count 2 2006.173.06:24:58.76#ibcon#enter sib2, iclass 35, count 2 2006.173.06:24:58.76#ibcon#flushed, iclass 35, count 2 2006.173.06:24:58.76#ibcon#about to write, iclass 35, count 2 2006.173.06:24:58.76#ibcon#wrote, iclass 35, count 2 2006.173.06:24:58.76#ibcon#about to read 3, iclass 35, count 2 2006.173.06:24:58.79#ibcon#read 3, iclass 35, count 2 2006.173.06:24:58.79#ibcon#about to read 4, iclass 35, count 2 2006.173.06:24:58.79#ibcon#read 4, iclass 35, count 2 2006.173.06:24:58.79#ibcon#about to read 5, iclass 35, count 2 2006.173.06:24:58.79#ibcon#read 5, iclass 35, count 2 2006.173.06:24:58.79#ibcon#about to read 6, iclass 35, count 2 2006.173.06:24:58.79#ibcon#read 6, iclass 35, count 2 2006.173.06:24:58.79#ibcon#end of sib2, iclass 35, count 2 2006.173.06:24:58.79#ibcon#*after write, iclass 35, count 2 2006.173.06:24:58.79#ibcon#*before return 0, iclass 35, count 2 2006.173.06:24:58.79#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.06:24:58.79#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.06:24:58.79#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.06:24:58.79#ibcon#ireg 7 cls_cnt 0 2006.173.06:24:58.79#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.06:24:58.91#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.06:24:58.91#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.06:24:58.91#ibcon#enter wrdev, iclass 35, count 0 2006.173.06:24:58.91#ibcon#first serial, iclass 35, count 0 2006.173.06:24:58.91#ibcon#enter sib2, iclass 35, count 0 2006.173.06:24:58.91#ibcon#flushed, iclass 35, count 0 2006.173.06:24:58.91#ibcon#about to write, iclass 35, count 0 2006.173.06:24:58.91#ibcon#wrote, iclass 35, count 0 2006.173.06:24:58.91#ibcon#about to read 3, iclass 35, count 0 2006.173.06:24:58.93#ibcon#read 3, iclass 35, count 0 2006.173.06:24:58.93#ibcon#about to read 4, iclass 35, count 0 2006.173.06:24:58.93#ibcon#read 4, iclass 35, count 0 2006.173.06:24:58.93#ibcon#about to read 5, iclass 35, count 0 2006.173.06:24:58.93#ibcon#read 5, iclass 35, count 0 2006.173.06:24:58.93#ibcon#about to read 6, iclass 35, count 0 2006.173.06:24:58.93#ibcon#read 6, iclass 35, count 0 2006.173.06:24:58.93#ibcon#end of sib2, iclass 35, count 0 2006.173.06:24:58.93#ibcon#*mode == 0, iclass 35, count 0 2006.173.06:24:58.93#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.06:24:58.93#ibcon#[27=USB\r\n] 2006.173.06:24:58.93#ibcon#*before write, iclass 35, count 0 2006.173.06:24:58.93#ibcon#enter sib2, iclass 35, count 0 2006.173.06:24:58.93#ibcon#flushed, iclass 35, count 0 2006.173.06:24:58.93#ibcon#about to write, iclass 35, count 0 2006.173.06:24:58.93#ibcon#wrote, iclass 35, count 0 2006.173.06:24:58.93#ibcon#about to read 3, iclass 35, count 0 2006.173.06:24:58.96#ibcon#read 3, iclass 35, count 0 2006.173.06:24:58.96#ibcon#about to read 4, iclass 35, count 0 2006.173.06:24:58.96#ibcon#read 4, iclass 35, count 0 2006.173.06:24:58.96#ibcon#about to read 5, iclass 35, count 0 2006.173.06:24:58.96#ibcon#read 5, iclass 35, count 0 2006.173.06:24:58.96#ibcon#about to read 6, iclass 35, count 0 2006.173.06:24:58.96#ibcon#read 6, iclass 35, count 0 2006.173.06:24:58.96#ibcon#end of sib2, iclass 35, count 0 2006.173.06:24:58.96#ibcon#*after write, iclass 35, count 0 2006.173.06:24:58.96#ibcon#*before return 0, iclass 35, count 0 2006.173.06:24:58.96#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.06:24:58.96#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.06:24:58.96#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.06:24:58.96#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.06:24:58.96$vck44/vblo=4,679.99 2006.173.06:24:58.96#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.06:24:58.96#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.06:24:58.96#ibcon#ireg 17 cls_cnt 0 2006.173.06:24:58.96#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.06:24:58.96#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.06:24:58.96#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.06:24:58.96#ibcon#enter wrdev, iclass 37, count 0 2006.173.06:24:58.96#ibcon#first serial, iclass 37, count 0 2006.173.06:24:58.96#ibcon#enter sib2, iclass 37, count 0 2006.173.06:24:58.96#ibcon#flushed, iclass 37, count 0 2006.173.06:24:58.96#ibcon#about to write, iclass 37, count 0 2006.173.06:24:58.96#ibcon#wrote, iclass 37, count 0 2006.173.06:24:58.96#ibcon#about to read 3, iclass 37, count 0 2006.173.06:24:58.98#ibcon#read 3, iclass 37, count 0 2006.173.06:24:58.98#ibcon#about to read 4, iclass 37, count 0 2006.173.06:24:58.98#ibcon#read 4, iclass 37, count 0 2006.173.06:24:58.98#ibcon#about to read 5, iclass 37, count 0 2006.173.06:24:58.98#ibcon#read 5, iclass 37, count 0 2006.173.06:24:58.98#ibcon#about to read 6, iclass 37, count 0 2006.173.06:24:58.98#ibcon#read 6, iclass 37, count 0 2006.173.06:24:58.98#ibcon#end of sib2, iclass 37, count 0 2006.173.06:24:58.98#ibcon#*mode == 0, iclass 37, count 0 2006.173.06:24:58.98#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.06:24:58.98#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.06:24:58.98#ibcon#*before write, iclass 37, count 0 2006.173.06:24:58.98#ibcon#enter sib2, iclass 37, count 0 2006.173.06:24:58.98#ibcon#flushed, iclass 37, count 0 2006.173.06:24:58.98#ibcon#about to write, iclass 37, count 0 2006.173.06:24:58.98#ibcon#wrote, iclass 37, count 0 2006.173.06:24:58.98#ibcon#about to read 3, iclass 37, count 0 2006.173.06:24:59.02#ibcon#read 3, iclass 37, count 0 2006.173.06:24:59.02#ibcon#about to read 4, iclass 37, count 0 2006.173.06:24:59.02#ibcon#read 4, iclass 37, count 0 2006.173.06:24:59.02#ibcon#about to read 5, iclass 37, count 0 2006.173.06:24:59.02#ibcon#read 5, iclass 37, count 0 2006.173.06:24:59.02#ibcon#about to read 6, iclass 37, count 0 2006.173.06:24:59.02#ibcon#read 6, iclass 37, count 0 2006.173.06:24:59.02#ibcon#end of sib2, iclass 37, count 0 2006.173.06:24:59.02#ibcon#*after write, iclass 37, count 0 2006.173.06:24:59.02#ibcon#*before return 0, iclass 37, count 0 2006.173.06:24:59.02#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.06:24:59.02#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.06:24:59.02#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.06:24:59.02#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.06:24:59.02$vck44/vb=4,4 2006.173.06:24:59.02#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.06:24:59.02#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.06:24:59.02#ibcon#ireg 11 cls_cnt 2 2006.173.06:24:59.02#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.06:24:59.08#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.06:24:59.08#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.06:24:59.08#ibcon#enter wrdev, iclass 39, count 2 2006.173.06:24:59.08#ibcon#first serial, iclass 39, count 2 2006.173.06:24:59.08#ibcon#enter sib2, iclass 39, count 2 2006.173.06:24:59.08#ibcon#flushed, iclass 39, count 2 2006.173.06:24:59.08#ibcon#about to write, iclass 39, count 2 2006.173.06:24:59.08#ibcon#wrote, iclass 39, count 2 2006.173.06:24:59.08#ibcon#about to read 3, iclass 39, count 2 2006.173.06:24:59.10#ibcon#read 3, iclass 39, count 2 2006.173.06:24:59.10#ibcon#about to read 4, iclass 39, count 2 2006.173.06:24:59.10#ibcon#read 4, iclass 39, count 2 2006.173.06:24:59.10#ibcon#about to read 5, iclass 39, count 2 2006.173.06:24:59.10#ibcon#read 5, iclass 39, count 2 2006.173.06:24:59.10#ibcon#about to read 6, iclass 39, count 2 2006.173.06:24:59.10#ibcon#read 6, iclass 39, count 2 2006.173.06:24:59.10#ibcon#end of sib2, iclass 39, count 2 2006.173.06:24:59.10#ibcon#*mode == 0, iclass 39, count 2 2006.173.06:24:59.10#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.06:24:59.10#ibcon#[27=AT04-04\r\n] 2006.173.06:24:59.10#ibcon#*before write, iclass 39, count 2 2006.173.06:24:59.10#ibcon#enter sib2, iclass 39, count 2 2006.173.06:24:59.10#ibcon#flushed, iclass 39, count 2 2006.173.06:24:59.10#ibcon#about to write, iclass 39, count 2 2006.173.06:24:59.10#ibcon#wrote, iclass 39, count 2 2006.173.06:24:59.10#ibcon#about to read 3, iclass 39, count 2 2006.173.06:24:59.13#ibcon#read 3, iclass 39, count 2 2006.173.06:24:59.13#ibcon#about to read 4, iclass 39, count 2 2006.173.06:24:59.13#ibcon#read 4, iclass 39, count 2 2006.173.06:24:59.13#ibcon#about to read 5, iclass 39, count 2 2006.173.06:24:59.13#ibcon#read 5, iclass 39, count 2 2006.173.06:24:59.13#ibcon#about to read 6, iclass 39, count 2 2006.173.06:24:59.13#ibcon#read 6, iclass 39, count 2 2006.173.06:24:59.13#ibcon#end of sib2, iclass 39, count 2 2006.173.06:24:59.13#ibcon#*after write, iclass 39, count 2 2006.173.06:24:59.13#ibcon#*before return 0, iclass 39, count 2 2006.173.06:24:59.13#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.06:24:59.13#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.06:24:59.13#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.06:24:59.13#ibcon#ireg 7 cls_cnt 0 2006.173.06:24:59.13#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.06:24:59.25#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.06:24:59.25#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.06:24:59.25#ibcon#enter wrdev, iclass 39, count 0 2006.173.06:24:59.25#ibcon#first serial, iclass 39, count 0 2006.173.06:24:59.25#ibcon#enter sib2, iclass 39, count 0 2006.173.06:24:59.25#ibcon#flushed, iclass 39, count 0 2006.173.06:24:59.25#ibcon#about to write, iclass 39, count 0 2006.173.06:24:59.25#ibcon#wrote, iclass 39, count 0 2006.173.06:24:59.25#ibcon#about to read 3, iclass 39, count 0 2006.173.06:24:59.27#ibcon#read 3, iclass 39, count 0 2006.173.06:24:59.27#ibcon#about to read 4, iclass 39, count 0 2006.173.06:24:59.27#ibcon#read 4, iclass 39, count 0 2006.173.06:24:59.27#ibcon#about to read 5, iclass 39, count 0 2006.173.06:24:59.27#ibcon#read 5, iclass 39, count 0 2006.173.06:24:59.27#ibcon#about to read 6, iclass 39, count 0 2006.173.06:24:59.27#ibcon#read 6, iclass 39, count 0 2006.173.06:24:59.27#ibcon#end of sib2, iclass 39, count 0 2006.173.06:24:59.27#ibcon#*mode == 0, iclass 39, count 0 2006.173.06:24:59.27#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.06:24:59.27#ibcon#[27=USB\r\n] 2006.173.06:24:59.27#ibcon#*before write, iclass 39, count 0 2006.173.06:24:59.27#ibcon#enter sib2, iclass 39, count 0 2006.173.06:24:59.27#ibcon#flushed, iclass 39, count 0 2006.173.06:24:59.27#ibcon#about to write, iclass 39, count 0 2006.173.06:24:59.27#ibcon#wrote, iclass 39, count 0 2006.173.06:24:59.27#ibcon#about to read 3, iclass 39, count 0 2006.173.06:24:59.30#ibcon#read 3, iclass 39, count 0 2006.173.06:24:59.30#ibcon#about to read 4, iclass 39, count 0 2006.173.06:24:59.30#ibcon#read 4, iclass 39, count 0 2006.173.06:24:59.30#ibcon#about to read 5, iclass 39, count 0 2006.173.06:24:59.30#ibcon#read 5, iclass 39, count 0 2006.173.06:24:59.30#ibcon#about to read 6, iclass 39, count 0 2006.173.06:24:59.30#ibcon#read 6, iclass 39, count 0 2006.173.06:24:59.30#ibcon#end of sib2, iclass 39, count 0 2006.173.06:24:59.30#ibcon#*after write, iclass 39, count 0 2006.173.06:24:59.30#ibcon#*before return 0, iclass 39, count 0 2006.173.06:24:59.30#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.06:24:59.30#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.06:24:59.30#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.06:24:59.30#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.06:24:59.30$vck44/vblo=5,709.99 2006.173.06:24:59.30#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.06:24:59.30#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.06:24:59.30#ibcon#ireg 17 cls_cnt 0 2006.173.06:24:59.30#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.06:24:59.30#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.06:24:59.30#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.06:24:59.30#ibcon#enter wrdev, iclass 3, count 0 2006.173.06:24:59.30#ibcon#first serial, iclass 3, count 0 2006.173.06:24:59.30#ibcon#enter sib2, iclass 3, count 0 2006.173.06:24:59.30#ibcon#flushed, iclass 3, count 0 2006.173.06:24:59.30#ibcon#about to write, iclass 3, count 0 2006.173.06:24:59.30#ibcon#wrote, iclass 3, count 0 2006.173.06:24:59.30#ibcon#about to read 3, iclass 3, count 0 2006.173.06:24:59.32#ibcon#read 3, iclass 3, count 0 2006.173.06:24:59.32#ibcon#about to read 4, iclass 3, count 0 2006.173.06:24:59.32#ibcon#read 4, iclass 3, count 0 2006.173.06:24:59.32#ibcon#about to read 5, iclass 3, count 0 2006.173.06:24:59.32#ibcon#read 5, iclass 3, count 0 2006.173.06:24:59.32#ibcon#about to read 6, iclass 3, count 0 2006.173.06:24:59.32#ibcon#read 6, iclass 3, count 0 2006.173.06:24:59.32#ibcon#end of sib2, iclass 3, count 0 2006.173.06:24:59.32#ibcon#*mode == 0, iclass 3, count 0 2006.173.06:24:59.32#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.06:24:59.32#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.06:24:59.32#ibcon#*before write, iclass 3, count 0 2006.173.06:24:59.32#ibcon#enter sib2, iclass 3, count 0 2006.173.06:24:59.32#ibcon#flushed, iclass 3, count 0 2006.173.06:24:59.32#ibcon#about to write, iclass 3, count 0 2006.173.06:24:59.32#ibcon#wrote, iclass 3, count 0 2006.173.06:24:59.32#ibcon#about to read 3, iclass 3, count 0 2006.173.06:24:59.36#ibcon#read 3, iclass 3, count 0 2006.173.06:24:59.36#ibcon#about to read 4, iclass 3, count 0 2006.173.06:24:59.36#ibcon#read 4, iclass 3, count 0 2006.173.06:24:59.36#ibcon#about to read 5, iclass 3, count 0 2006.173.06:24:59.36#ibcon#read 5, iclass 3, count 0 2006.173.06:24:59.36#ibcon#about to read 6, iclass 3, count 0 2006.173.06:24:59.36#ibcon#read 6, iclass 3, count 0 2006.173.06:24:59.36#ibcon#end of sib2, iclass 3, count 0 2006.173.06:24:59.36#ibcon#*after write, iclass 3, count 0 2006.173.06:24:59.36#ibcon#*before return 0, iclass 3, count 0 2006.173.06:24:59.36#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.06:24:59.36#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.06:24:59.36#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.06:24:59.36#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.06:24:59.36$vck44/vb=5,4 2006.173.06:24:59.36#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.06:24:59.36#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.06:24:59.36#ibcon#ireg 11 cls_cnt 2 2006.173.06:24:59.36#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.06:24:59.42#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.06:24:59.42#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.06:24:59.42#ibcon#enter wrdev, iclass 5, count 2 2006.173.06:24:59.42#ibcon#first serial, iclass 5, count 2 2006.173.06:24:59.42#ibcon#enter sib2, iclass 5, count 2 2006.173.06:24:59.42#ibcon#flushed, iclass 5, count 2 2006.173.06:24:59.42#ibcon#about to write, iclass 5, count 2 2006.173.06:24:59.42#ibcon#wrote, iclass 5, count 2 2006.173.06:24:59.42#ibcon#about to read 3, iclass 5, count 2 2006.173.06:24:59.44#ibcon#read 3, iclass 5, count 2 2006.173.06:24:59.44#ibcon#about to read 4, iclass 5, count 2 2006.173.06:24:59.44#ibcon#read 4, iclass 5, count 2 2006.173.06:24:59.44#ibcon#about to read 5, iclass 5, count 2 2006.173.06:24:59.44#ibcon#read 5, iclass 5, count 2 2006.173.06:24:59.44#ibcon#about to read 6, iclass 5, count 2 2006.173.06:24:59.44#ibcon#read 6, iclass 5, count 2 2006.173.06:24:59.44#ibcon#end of sib2, iclass 5, count 2 2006.173.06:24:59.44#ibcon#*mode == 0, iclass 5, count 2 2006.173.06:24:59.44#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.06:24:59.44#ibcon#[27=AT05-04\r\n] 2006.173.06:24:59.44#ibcon#*before write, iclass 5, count 2 2006.173.06:24:59.44#ibcon#enter sib2, iclass 5, count 2 2006.173.06:24:59.44#ibcon#flushed, iclass 5, count 2 2006.173.06:24:59.44#ibcon#about to write, iclass 5, count 2 2006.173.06:24:59.44#ibcon#wrote, iclass 5, count 2 2006.173.06:24:59.44#ibcon#about to read 3, iclass 5, count 2 2006.173.06:24:59.47#ibcon#read 3, iclass 5, count 2 2006.173.06:24:59.47#ibcon#about to read 4, iclass 5, count 2 2006.173.06:24:59.47#ibcon#read 4, iclass 5, count 2 2006.173.06:24:59.47#ibcon#about to read 5, iclass 5, count 2 2006.173.06:24:59.47#ibcon#read 5, iclass 5, count 2 2006.173.06:24:59.47#ibcon#about to read 6, iclass 5, count 2 2006.173.06:24:59.47#ibcon#read 6, iclass 5, count 2 2006.173.06:24:59.47#ibcon#end of sib2, iclass 5, count 2 2006.173.06:24:59.47#ibcon#*after write, iclass 5, count 2 2006.173.06:24:59.47#ibcon#*before return 0, iclass 5, count 2 2006.173.06:24:59.47#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.06:24:59.47#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.06:24:59.47#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.06:24:59.47#ibcon#ireg 7 cls_cnt 0 2006.173.06:24:59.47#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.06:24:59.59#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.06:24:59.59#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.06:24:59.59#ibcon#enter wrdev, iclass 5, count 0 2006.173.06:24:59.59#ibcon#first serial, iclass 5, count 0 2006.173.06:24:59.59#ibcon#enter sib2, iclass 5, count 0 2006.173.06:24:59.59#ibcon#flushed, iclass 5, count 0 2006.173.06:24:59.59#ibcon#about to write, iclass 5, count 0 2006.173.06:24:59.59#ibcon#wrote, iclass 5, count 0 2006.173.06:24:59.59#ibcon#about to read 3, iclass 5, count 0 2006.173.06:24:59.61#ibcon#read 3, iclass 5, count 0 2006.173.06:24:59.61#ibcon#about to read 4, iclass 5, count 0 2006.173.06:24:59.61#ibcon#read 4, iclass 5, count 0 2006.173.06:24:59.61#ibcon#about to read 5, iclass 5, count 0 2006.173.06:24:59.61#ibcon#read 5, iclass 5, count 0 2006.173.06:24:59.61#ibcon#about to read 6, iclass 5, count 0 2006.173.06:24:59.61#ibcon#read 6, iclass 5, count 0 2006.173.06:24:59.61#ibcon#end of sib2, iclass 5, count 0 2006.173.06:24:59.61#ibcon#*mode == 0, iclass 5, count 0 2006.173.06:24:59.61#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.06:24:59.61#ibcon#[27=USB\r\n] 2006.173.06:24:59.61#ibcon#*before write, iclass 5, count 0 2006.173.06:24:59.61#ibcon#enter sib2, iclass 5, count 0 2006.173.06:24:59.61#ibcon#flushed, iclass 5, count 0 2006.173.06:24:59.61#ibcon#about to write, iclass 5, count 0 2006.173.06:24:59.61#ibcon#wrote, iclass 5, count 0 2006.173.06:24:59.61#ibcon#about to read 3, iclass 5, count 0 2006.173.06:24:59.64#ibcon#read 3, iclass 5, count 0 2006.173.06:24:59.64#ibcon#about to read 4, iclass 5, count 0 2006.173.06:24:59.64#ibcon#read 4, iclass 5, count 0 2006.173.06:24:59.64#ibcon#about to read 5, iclass 5, count 0 2006.173.06:24:59.64#ibcon#read 5, iclass 5, count 0 2006.173.06:24:59.64#ibcon#about to read 6, iclass 5, count 0 2006.173.06:24:59.64#ibcon#read 6, iclass 5, count 0 2006.173.06:24:59.64#ibcon#end of sib2, iclass 5, count 0 2006.173.06:24:59.64#ibcon#*after write, iclass 5, count 0 2006.173.06:24:59.64#ibcon#*before return 0, iclass 5, count 0 2006.173.06:24:59.64#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.06:24:59.64#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.06:24:59.64#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.06:24:59.64#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.06:24:59.64$vck44/vblo=6,719.99 2006.173.06:24:59.64#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.06:24:59.64#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.06:24:59.64#ibcon#ireg 17 cls_cnt 0 2006.173.06:24:59.64#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.06:24:59.64#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.06:24:59.64#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.06:24:59.64#ibcon#enter wrdev, iclass 7, count 0 2006.173.06:24:59.64#ibcon#first serial, iclass 7, count 0 2006.173.06:24:59.64#ibcon#enter sib2, iclass 7, count 0 2006.173.06:24:59.64#ibcon#flushed, iclass 7, count 0 2006.173.06:24:59.64#ibcon#about to write, iclass 7, count 0 2006.173.06:24:59.64#ibcon#wrote, iclass 7, count 0 2006.173.06:24:59.64#ibcon#about to read 3, iclass 7, count 0 2006.173.06:24:59.66#ibcon#read 3, iclass 7, count 0 2006.173.06:24:59.66#ibcon#about to read 4, iclass 7, count 0 2006.173.06:24:59.66#ibcon#read 4, iclass 7, count 0 2006.173.06:24:59.66#ibcon#about to read 5, iclass 7, count 0 2006.173.06:24:59.66#ibcon#read 5, iclass 7, count 0 2006.173.06:24:59.66#ibcon#about to read 6, iclass 7, count 0 2006.173.06:24:59.66#ibcon#read 6, iclass 7, count 0 2006.173.06:24:59.66#ibcon#end of sib2, iclass 7, count 0 2006.173.06:24:59.66#ibcon#*mode == 0, iclass 7, count 0 2006.173.06:24:59.66#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.06:24:59.66#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.06:24:59.66#ibcon#*before write, iclass 7, count 0 2006.173.06:24:59.66#ibcon#enter sib2, iclass 7, count 0 2006.173.06:24:59.66#ibcon#flushed, iclass 7, count 0 2006.173.06:24:59.66#ibcon#about to write, iclass 7, count 0 2006.173.06:24:59.66#ibcon#wrote, iclass 7, count 0 2006.173.06:24:59.66#ibcon#about to read 3, iclass 7, count 0 2006.173.06:24:59.70#ibcon#read 3, iclass 7, count 0 2006.173.06:24:59.70#ibcon#about to read 4, iclass 7, count 0 2006.173.06:24:59.70#ibcon#read 4, iclass 7, count 0 2006.173.06:24:59.70#ibcon#about to read 5, iclass 7, count 0 2006.173.06:24:59.70#ibcon#read 5, iclass 7, count 0 2006.173.06:24:59.70#ibcon#about to read 6, iclass 7, count 0 2006.173.06:24:59.70#ibcon#read 6, iclass 7, count 0 2006.173.06:24:59.70#ibcon#end of sib2, iclass 7, count 0 2006.173.06:24:59.70#ibcon#*after write, iclass 7, count 0 2006.173.06:24:59.70#ibcon#*before return 0, iclass 7, count 0 2006.173.06:24:59.70#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.06:24:59.70#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.06:24:59.70#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.06:24:59.70#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.06:24:59.70$vck44/vb=6,4 2006.173.06:24:59.70#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.06:24:59.70#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.06:24:59.70#ibcon#ireg 11 cls_cnt 2 2006.173.06:24:59.70#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.06:24:59.76#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.06:24:59.76#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.06:24:59.76#ibcon#enter wrdev, iclass 11, count 2 2006.173.06:24:59.76#ibcon#first serial, iclass 11, count 2 2006.173.06:24:59.76#ibcon#enter sib2, iclass 11, count 2 2006.173.06:24:59.76#ibcon#flushed, iclass 11, count 2 2006.173.06:24:59.76#ibcon#about to write, iclass 11, count 2 2006.173.06:24:59.76#ibcon#wrote, iclass 11, count 2 2006.173.06:24:59.76#ibcon#about to read 3, iclass 11, count 2 2006.173.06:24:59.78#ibcon#read 3, iclass 11, count 2 2006.173.06:24:59.78#ibcon#about to read 4, iclass 11, count 2 2006.173.06:24:59.78#ibcon#read 4, iclass 11, count 2 2006.173.06:24:59.78#ibcon#about to read 5, iclass 11, count 2 2006.173.06:24:59.78#ibcon#read 5, iclass 11, count 2 2006.173.06:24:59.78#ibcon#about to read 6, iclass 11, count 2 2006.173.06:24:59.78#ibcon#read 6, iclass 11, count 2 2006.173.06:24:59.78#ibcon#end of sib2, iclass 11, count 2 2006.173.06:24:59.78#ibcon#*mode == 0, iclass 11, count 2 2006.173.06:24:59.78#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.06:24:59.78#ibcon#[27=AT06-04\r\n] 2006.173.06:24:59.78#ibcon#*before write, iclass 11, count 2 2006.173.06:24:59.78#ibcon#enter sib2, iclass 11, count 2 2006.173.06:24:59.78#ibcon#flushed, iclass 11, count 2 2006.173.06:24:59.78#ibcon#about to write, iclass 11, count 2 2006.173.06:24:59.78#ibcon#wrote, iclass 11, count 2 2006.173.06:24:59.78#ibcon#about to read 3, iclass 11, count 2 2006.173.06:24:59.81#ibcon#read 3, iclass 11, count 2 2006.173.06:24:59.81#ibcon#about to read 4, iclass 11, count 2 2006.173.06:24:59.81#ibcon#read 4, iclass 11, count 2 2006.173.06:24:59.81#ibcon#about to read 5, iclass 11, count 2 2006.173.06:24:59.81#ibcon#read 5, iclass 11, count 2 2006.173.06:24:59.81#ibcon#about to read 6, iclass 11, count 2 2006.173.06:24:59.81#ibcon#read 6, iclass 11, count 2 2006.173.06:24:59.81#ibcon#end of sib2, iclass 11, count 2 2006.173.06:24:59.81#ibcon#*after write, iclass 11, count 2 2006.173.06:24:59.81#ibcon#*before return 0, iclass 11, count 2 2006.173.06:24:59.81#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.06:24:59.81#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.06:24:59.81#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.06:24:59.81#ibcon#ireg 7 cls_cnt 0 2006.173.06:24:59.81#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.06:24:59.93#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.06:24:59.93#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.06:24:59.93#ibcon#enter wrdev, iclass 11, count 0 2006.173.06:24:59.93#ibcon#first serial, iclass 11, count 0 2006.173.06:24:59.93#ibcon#enter sib2, iclass 11, count 0 2006.173.06:24:59.93#ibcon#flushed, iclass 11, count 0 2006.173.06:24:59.93#ibcon#about to write, iclass 11, count 0 2006.173.06:24:59.93#ibcon#wrote, iclass 11, count 0 2006.173.06:24:59.93#ibcon#about to read 3, iclass 11, count 0 2006.173.06:24:59.95#ibcon#read 3, iclass 11, count 0 2006.173.06:24:59.95#ibcon#about to read 4, iclass 11, count 0 2006.173.06:24:59.95#ibcon#read 4, iclass 11, count 0 2006.173.06:24:59.95#ibcon#about to read 5, iclass 11, count 0 2006.173.06:24:59.95#ibcon#read 5, iclass 11, count 0 2006.173.06:24:59.95#ibcon#about to read 6, iclass 11, count 0 2006.173.06:24:59.95#ibcon#read 6, iclass 11, count 0 2006.173.06:24:59.95#ibcon#end of sib2, iclass 11, count 0 2006.173.06:24:59.95#ibcon#*mode == 0, iclass 11, count 0 2006.173.06:24:59.95#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.06:24:59.95#ibcon#[27=USB\r\n] 2006.173.06:24:59.95#ibcon#*before write, iclass 11, count 0 2006.173.06:24:59.95#ibcon#enter sib2, iclass 11, count 0 2006.173.06:24:59.95#ibcon#flushed, iclass 11, count 0 2006.173.06:24:59.95#ibcon#about to write, iclass 11, count 0 2006.173.06:24:59.95#ibcon#wrote, iclass 11, count 0 2006.173.06:24:59.95#ibcon#about to read 3, iclass 11, count 0 2006.173.06:24:59.98#ibcon#read 3, iclass 11, count 0 2006.173.06:24:59.98#ibcon#about to read 4, iclass 11, count 0 2006.173.06:24:59.98#ibcon#read 4, iclass 11, count 0 2006.173.06:24:59.98#ibcon#about to read 5, iclass 11, count 0 2006.173.06:24:59.98#ibcon#read 5, iclass 11, count 0 2006.173.06:24:59.98#ibcon#about to read 6, iclass 11, count 0 2006.173.06:24:59.98#ibcon#read 6, iclass 11, count 0 2006.173.06:24:59.98#ibcon#end of sib2, iclass 11, count 0 2006.173.06:24:59.98#ibcon#*after write, iclass 11, count 0 2006.173.06:24:59.98#ibcon#*before return 0, iclass 11, count 0 2006.173.06:24:59.98#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.06:24:59.98#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.06:24:59.98#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.06:24:59.98#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.06:24:59.98$vck44/vblo=7,734.99 2006.173.06:24:59.98#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.06:24:59.98#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.06:24:59.98#ibcon#ireg 17 cls_cnt 0 2006.173.06:24:59.98#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.06:24:59.98#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.06:24:59.98#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.06:24:59.98#ibcon#enter wrdev, iclass 13, count 0 2006.173.06:24:59.98#ibcon#first serial, iclass 13, count 0 2006.173.06:24:59.98#ibcon#enter sib2, iclass 13, count 0 2006.173.06:24:59.98#ibcon#flushed, iclass 13, count 0 2006.173.06:24:59.98#ibcon#about to write, iclass 13, count 0 2006.173.06:24:59.98#ibcon#wrote, iclass 13, count 0 2006.173.06:24:59.98#ibcon#about to read 3, iclass 13, count 0 2006.173.06:25:00.00#ibcon#read 3, iclass 13, count 0 2006.173.06:25:00.00#ibcon#about to read 4, iclass 13, count 0 2006.173.06:25:00.00#ibcon#read 4, iclass 13, count 0 2006.173.06:25:00.00#ibcon#about to read 5, iclass 13, count 0 2006.173.06:25:00.00#ibcon#read 5, iclass 13, count 0 2006.173.06:25:00.00#ibcon#about to read 6, iclass 13, count 0 2006.173.06:25:00.00#ibcon#read 6, iclass 13, count 0 2006.173.06:25:00.00#ibcon#end of sib2, iclass 13, count 0 2006.173.06:25:00.00#ibcon#*mode == 0, iclass 13, count 0 2006.173.06:25:00.00#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.06:25:00.00#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.06:25:00.00#ibcon#*before write, iclass 13, count 0 2006.173.06:25:00.00#ibcon#enter sib2, iclass 13, count 0 2006.173.06:25:00.00#ibcon#flushed, iclass 13, count 0 2006.173.06:25:00.00#ibcon#about to write, iclass 13, count 0 2006.173.06:25:00.00#ibcon#wrote, iclass 13, count 0 2006.173.06:25:00.00#ibcon#about to read 3, iclass 13, count 0 2006.173.06:25:00.04#ibcon#read 3, iclass 13, count 0 2006.173.06:25:00.04#ibcon#about to read 4, iclass 13, count 0 2006.173.06:25:00.04#ibcon#read 4, iclass 13, count 0 2006.173.06:25:00.04#ibcon#about to read 5, iclass 13, count 0 2006.173.06:25:00.04#ibcon#read 5, iclass 13, count 0 2006.173.06:25:00.04#ibcon#about to read 6, iclass 13, count 0 2006.173.06:25:00.04#ibcon#read 6, iclass 13, count 0 2006.173.06:25:00.04#ibcon#end of sib2, iclass 13, count 0 2006.173.06:25:00.04#ibcon#*after write, iclass 13, count 0 2006.173.06:25:00.04#ibcon#*before return 0, iclass 13, count 0 2006.173.06:25:00.04#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.06:25:00.04#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.06:25:00.04#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.06:25:00.04#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.06:25:00.04$vck44/vb=7,4 2006.173.06:25:00.04#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.06:25:00.04#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.06:25:00.04#ibcon#ireg 11 cls_cnt 2 2006.173.06:25:00.04#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.06:25:00.10#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.06:25:00.10#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.06:25:00.10#ibcon#enter wrdev, iclass 15, count 2 2006.173.06:25:00.10#ibcon#first serial, iclass 15, count 2 2006.173.06:25:00.10#ibcon#enter sib2, iclass 15, count 2 2006.173.06:25:00.10#ibcon#flushed, iclass 15, count 2 2006.173.06:25:00.10#ibcon#about to write, iclass 15, count 2 2006.173.06:25:00.10#ibcon#wrote, iclass 15, count 2 2006.173.06:25:00.10#ibcon#about to read 3, iclass 15, count 2 2006.173.06:25:00.12#ibcon#read 3, iclass 15, count 2 2006.173.06:25:00.12#ibcon#about to read 4, iclass 15, count 2 2006.173.06:25:00.12#ibcon#read 4, iclass 15, count 2 2006.173.06:25:00.12#ibcon#about to read 5, iclass 15, count 2 2006.173.06:25:00.12#ibcon#read 5, iclass 15, count 2 2006.173.06:25:00.12#ibcon#about to read 6, iclass 15, count 2 2006.173.06:25:00.12#ibcon#read 6, iclass 15, count 2 2006.173.06:25:00.12#ibcon#end of sib2, iclass 15, count 2 2006.173.06:25:00.12#ibcon#*mode == 0, iclass 15, count 2 2006.173.06:25:00.12#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.06:25:00.12#ibcon#[27=AT07-04\r\n] 2006.173.06:25:00.12#ibcon#*before write, iclass 15, count 2 2006.173.06:25:00.12#ibcon#enter sib2, iclass 15, count 2 2006.173.06:25:00.12#ibcon#flushed, iclass 15, count 2 2006.173.06:25:00.12#ibcon#about to write, iclass 15, count 2 2006.173.06:25:00.12#ibcon#wrote, iclass 15, count 2 2006.173.06:25:00.12#ibcon#about to read 3, iclass 15, count 2 2006.173.06:25:00.15#ibcon#read 3, iclass 15, count 2 2006.173.06:25:00.15#ibcon#about to read 4, iclass 15, count 2 2006.173.06:25:00.15#ibcon#read 4, iclass 15, count 2 2006.173.06:25:00.15#ibcon#about to read 5, iclass 15, count 2 2006.173.06:25:00.15#ibcon#read 5, iclass 15, count 2 2006.173.06:25:00.15#ibcon#about to read 6, iclass 15, count 2 2006.173.06:25:00.15#ibcon#read 6, iclass 15, count 2 2006.173.06:25:00.15#ibcon#end of sib2, iclass 15, count 2 2006.173.06:25:00.15#ibcon#*after write, iclass 15, count 2 2006.173.06:25:00.15#ibcon#*before return 0, iclass 15, count 2 2006.173.06:25:00.15#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.06:25:00.15#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.06:25:00.15#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.06:25:00.15#ibcon#ireg 7 cls_cnt 0 2006.173.06:25:00.15#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.06:25:00.27#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.06:25:00.27#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.06:25:00.27#ibcon#enter wrdev, iclass 15, count 0 2006.173.06:25:00.27#ibcon#first serial, iclass 15, count 0 2006.173.06:25:00.27#ibcon#enter sib2, iclass 15, count 0 2006.173.06:25:00.27#ibcon#flushed, iclass 15, count 0 2006.173.06:25:00.27#ibcon#about to write, iclass 15, count 0 2006.173.06:25:00.27#ibcon#wrote, iclass 15, count 0 2006.173.06:25:00.27#ibcon#about to read 3, iclass 15, count 0 2006.173.06:25:00.29#ibcon#read 3, iclass 15, count 0 2006.173.06:25:00.29#ibcon#about to read 4, iclass 15, count 0 2006.173.06:25:00.29#ibcon#read 4, iclass 15, count 0 2006.173.06:25:00.29#ibcon#about to read 5, iclass 15, count 0 2006.173.06:25:00.29#ibcon#read 5, iclass 15, count 0 2006.173.06:25:00.29#ibcon#about to read 6, iclass 15, count 0 2006.173.06:25:00.29#ibcon#read 6, iclass 15, count 0 2006.173.06:25:00.29#ibcon#end of sib2, iclass 15, count 0 2006.173.06:25:00.29#ibcon#*mode == 0, iclass 15, count 0 2006.173.06:25:00.29#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.06:25:00.29#ibcon#[27=USB\r\n] 2006.173.06:25:00.29#ibcon#*before write, iclass 15, count 0 2006.173.06:25:00.29#ibcon#enter sib2, iclass 15, count 0 2006.173.06:25:00.29#ibcon#flushed, iclass 15, count 0 2006.173.06:25:00.29#ibcon#about to write, iclass 15, count 0 2006.173.06:25:00.29#ibcon#wrote, iclass 15, count 0 2006.173.06:25:00.29#ibcon#about to read 3, iclass 15, count 0 2006.173.06:25:00.32#ibcon#read 3, iclass 15, count 0 2006.173.06:25:00.32#ibcon#about to read 4, iclass 15, count 0 2006.173.06:25:00.32#ibcon#read 4, iclass 15, count 0 2006.173.06:25:00.32#ibcon#about to read 5, iclass 15, count 0 2006.173.06:25:00.32#ibcon#read 5, iclass 15, count 0 2006.173.06:25:00.32#ibcon#about to read 6, iclass 15, count 0 2006.173.06:25:00.32#ibcon#read 6, iclass 15, count 0 2006.173.06:25:00.32#ibcon#end of sib2, iclass 15, count 0 2006.173.06:25:00.32#ibcon#*after write, iclass 15, count 0 2006.173.06:25:00.32#ibcon#*before return 0, iclass 15, count 0 2006.173.06:25:00.32#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.06:25:00.32#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.06:25:00.32#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.06:25:00.32#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.06:25:00.32$vck44/vblo=8,744.99 2006.173.06:25:00.32#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.06:25:00.32#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.06:25:00.32#ibcon#ireg 17 cls_cnt 0 2006.173.06:25:00.32#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.06:25:00.32#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.06:25:00.32#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.06:25:00.32#ibcon#enter wrdev, iclass 17, count 0 2006.173.06:25:00.32#ibcon#first serial, iclass 17, count 0 2006.173.06:25:00.32#ibcon#enter sib2, iclass 17, count 0 2006.173.06:25:00.32#ibcon#flushed, iclass 17, count 0 2006.173.06:25:00.32#ibcon#about to write, iclass 17, count 0 2006.173.06:25:00.32#ibcon#wrote, iclass 17, count 0 2006.173.06:25:00.32#ibcon#about to read 3, iclass 17, count 0 2006.173.06:25:00.34#ibcon#read 3, iclass 17, count 0 2006.173.06:25:00.34#ibcon#about to read 4, iclass 17, count 0 2006.173.06:25:00.34#ibcon#read 4, iclass 17, count 0 2006.173.06:25:00.34#ibcon#about to read 5, iclass 17, count 0 2006.173.06:25:00.34#ibcon#read 5, iclass 17, count 0 2006.173.06:25:00.34#ibcon#about to read 6, iclass 17, count 0 2006.173.06:25:00.34#ibcon#read 6, iclass 17, count 0 2006.173.06:25:00.34#ibcon#end of sib2, iclass 17, count 0 2006.173.06:25:00.34#ibcon#*mode == 0, iclass 17, count 0 2006.173.06:25:00.34#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.06:25:00.34#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.06:25:00.34#ibcon#*before write, iclass 17, count 0 2006.173.06:25:00.34#ibcon#enter sib2, iclass 17, count 0 2006.173.06:25:00.34#ibcon#flushed, iclass 17, count 0 2006.173.06:25:00.34#ibcon#about to write, iclass 17, count 0 2006.173.06:25:00.34#ibcon#wrote, iclass 17, count 0 2006.173.06:25:00.34#ibcon#about to read 3, iclass 17, count 0 2006.173.06:25:00.38#ibcon#read 3, iclass 17, count 0 2006.173.06:25:00.38#ibcon#about to read 4, iclass 17, count 0 2006.173.06:25:00.38#ibcon#read 4, iclass 17, count 0 2006.173.06:25:00.38#ibcon#about to read 5, iclass 17, count 0 2006.173.06:25:00.38#ibcon#read 5, iclass 17, count 0 2006.173.06:25:00.38#ibcon#about to read 6, iclass 17, count 0 2006.173.06:25:00.38#ibcon#read 6, iclass 17, count 0 2006.173.06:25:00.38#ibcon#end of sib2, iclass 17, count 0 2006.173.06:25:00.38#ibcon#*after write, iclass 17, count 0 2006.173.06:25:00.38#ibcon#*before return 0, iclass 17, count 0 2006.173.06:25:00.38#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.06:25:00.38#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.06:25:00.38#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.06:25:00.38#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.06:25:00.38$vck44/vb=8,4 2006.173.06:25:00.38#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.06:25:00.38#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.06:25:00.38#ibcon#ireg 11 cls_cnt 2 2006.173.06:25:00.38#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.06:25:00.44#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.06:25:00.44#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.06:25:00.44#ibcon#enter wrdev, iclass 19, count 2 2006.173.06:25:00.44#ibcon#first serial, iclass 19, count 2 2006.173.06:25:00.44#ibcon#enter sib2, iclass 19, count 2 2006.173.06:25:00.44#ibcon#flushed, iclass 19, count 2 2006.173.06:25:00.44#ibcon#about to write, iclass 19, count 2 2006.173.06:25:00.44#ibcon#wrote, iclass 19, count 2 2006.173.06:25:00.44#ibcon#about to read 3, iclass 19, count 2 2006.173.06:25:00.46#ibcon#read 3, iclass 19, count 2 2006.173.06:25:00.46#ibcon#about to read 4, iclass 19, count 2 2006.173.06:25:00.46#ibcon#read 4, iclass 19, count 2 2006.173.06:25:00.46#ibcon#about to read 5, iclass 19, count 2 2006.173.06:25:00.46#ibcon#read 5, iclass 19, count 2 2006.173.06:25:00.46#ibcon#about to read 6, iclass 19, count 2 2006.173.06:25:00.46#ibcon#read 6, iclass 19, count 2 2006.173.06:25:00.46#ibcon#end of sib2, iclass 19, count 2 2006.173.06:25:00.46#ibcon#*mode == 0, iclass 19, count 2 2006.173.06:25:00.46#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.06:25:00.46#ibcon#[27=AT08-04\r\n] 2006.173.06:25:00.46#ibcon#*before write, iclass 19, count 2 2006.173.06:25:00.46#ibcon#enter sib2, iclass 19, count 2 2006.173.06:25:00.46#ibcon#flushed, iclass 19, count 2 2006.173.06:25:00.46#ibcon#about to write, iclass 19, count 2 2006.173.06:25:00.46#ibcon#wrote, iclass 19, count 2 2006.173.06:25:00.46#ibcon#about to read 3, iclass 19, count 2 2006.173.06:25:00.49#ibcon#read 3, iclass 19, count 2 2006.173.06:25:00.49#ibcon#about to read 4, iclass 19, count 2 2006.173.06:25:00.49#ibcon#read 4, iclass 19, count 2 2006.173.06:25:00.49#ibcon#about to read 5, iclass 19, count 2 2006.173.06:25:00.49#ibcon#read 5, iclass 19, count 2 2006.173.06:25:00.49#ibcon#about to read 6, iclass 19, count 2 2006.173.06:25:00.49#ibcon#read 6, iclass 19, count 2 2006.173.06:25:00.49#ibcon#end of sib2, iclass 19, count 2 2006.173.06:25:00.49#ibcon#*after write, iclass 19, count 2 2006.173.06:25:00.49#ibcon#*before return 0, iclass 19, count 2 2006.173.06:25:00.49#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.06:25:00.49#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.06:25:00.49#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.06:25:00.49#ibcon#ireg 7 cls_cnt 0 2006.173.06:25:00.49#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.06:25:00.61#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.06:25:00.61#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.06:25:00.61#ibcon#enter wrdev, iclass 19, count 0 2006.173.06:25:00.61#ibcon#first serial, iclass 19, count 0 2006.173.06:25:00.61#ibcon#enter sib2, iclass 19, count 0 2006.173.06:25:00.61#ibcon#flushed, iclass 19, count 0 2006.173.06:25:00.61#ibcon#about to write, iclass 19, count 0 2006.173.06:25:00.61#ibcon#wrote, iclass 19, count 0 2006.173.06:25:00.61#ibcon#about to read 3, iclass 19, count 0 2006.173.06:25:00.63#ibcon#read 3, iclass 19, count 0 2006.173.06:25:00.63#ibcon#about to read 4, iclass 19, count 0 2006.173.06:25:00.63#ibcon#read 4, iclass 19, count 0 2006.173.06:25:00.63#ibcon#about to read 5, iclass 19, count 0 2006.173.06:25:00.63#ibcon#read 5, iclass 19, count 0 2006.173.06:25:00.63#ibcon#about to read 6, iclass 19, count 0 2006.173.06:25:00.63#ibcon#read 6, iclass 19, count 0 2006.173.06:25:00.63#ibcon#end of sib2, iclass 19, count 0 2006.173.06:25:00.63#ibcon#*mode == 0, iclass 19, count 0 2006.173.06:25:00.63#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.06:25:00.63#ibcon#[27=USB\r\n] 2006.173.06:25:00.63#ibcon#*before write, iclass 19, count 0 2006.173.06:25:00.63#ibcon#enter sib2, iclass 19, count 0 2006.173.06:25:00.63#ibcon#flushed, iclass 19, count 0 2006.173.06:25:00.63#ibcon#about to write, iclass 19, count 0 2006.173.06:25:00.63#ibcon#wrote, iclass 19, count 0 2006.173.06:25:00.63#ibcon#about to read 3, iclass 19, count 0 2006.173.06:25:00.66#ibcon#read 3, iclass 19, count 0 2006.173.06:25:00.66#ibcon#about to read 4, iclass 19, count 0 2006.173.06:25:00.66#ibcon#read 4, iclass 19, count 0 2006.173.06:25:00.66#ibcon#about to read 5, iclass 19, count 0 2006.173.06:25:00.66#ibcon#read 5, iclass 19, count 0 2006.173.06:25:00.66#ibcon#about to read 6, iclass 19, count 0 2006.173.06:25:00.66#ibcon#read 6, iclass 19, count 0 2006.173.06:25:00.66#ibcon#end of sib2, iclass 19, count 0 2006.173.06:25:00.66#ibcon#*after write, iclass 19, count 0 2006.173.06:25:00.66#ibcon#*before return 0, iclass 19, count 0 2006.173.06:25:00.66#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.06:25:00.66#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.06:25:00.66#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.06:25:00.66#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.06:25:00.66$vck44/vabw=wide 2006.173.06:25:00.66#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.06:25:00.66#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.06:25:00.66#ibcon#ireg 8 cls_cnt 0 2006.173.06:25:00.66#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.06:25:00.66#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.06:25:00.66#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.06:25:00.66#ibcon#enter wrdev, iclass 21, count 0 2006.173.06:25:00.66#ibcon#first serial, iclass 21, count 0 2006.173.06:25:00.66#ibcon#enter sib2, iclass 21, count 0 2006.173.06:25:00.66#ibcon#flushed, iclass 21, count 0 2006.173.06:25:00.66#ibcon#about to write, iclass 21, count 0 2006.173.06:25:00.66#ibcon#wrote, iclass 21, count 0 2006.173.06:25:00.66#ibcon#about to read 3, iclass 21, count 0 2006.173.06:25:00.68#ibcon#read 3, iclass 21, count 0 2006.173.06:25:00.68#ibcon#about to read 4, iclass 21, count 0 2006.173.06:25:00.68#ibcon#read 4, iclass 21, count 0 2006.173.06:25:00.68#ibcon#about to read 5, iclass 21, count 0 2006.173.06:25:00.68#ibcon#read 5, iclass 21, count 0 2006.173.06:25:00.68#ibcon#about to read 6, iclass 21, count 0 2006.173.06:25:00.68#ibcon#read 6, iclass 21, count 0 2006.173.06:25:00.68#ibcon#end of sib2, iclass 21, count 0 2006.173.06:25:00.68#ibcon#*mode == 0, iclass 21, count 0 2006.173.06:25:00.68#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.06:25:00.68#ibcon#[25=BW32\r\n] 2006.173.06:25:00.68#ibcon#*before write, iclass 21, count 0 2006.173.06:25:00.68#ibcon#enter sib2, iclass 21, count 0 2006.173.06:25:00.68#ibcon#flushed, iclass 21, count 0 2006.173.06:25:00.68#ibcon#about to write, iclass 21, count 0 2006.173.06:25:00.68#ibcon#wrote, iclass 21, count 0 2006.173.06:25:00.68#ibcon#about to read 3, iclass 21, count 0 2006.173.06:25:00.71#ibcon#read 3, iclass 21, count 0 2006.173.06:25:00.71#ibcon#about to read 4, iclass 21, count 0 2006.173.06:25:00.71#ibcon#read 4, iclass 21, count 0 2006.173.06:25:00.71#ibcon#about to read 5, iclass 21, count 0 2006.173.06:25:00.71#ibcon#read 5, iclass 21, count 0 2006.173.06:25:00.71#ibcon#about to read 6, iclass 21, count 0 2006.173.06:25:00.71#ibcon#read 6, iclass 21, count 0 2006.173.06:25:00.71#ibcon#end of sib2, iclass 21, count 0 2006.173.06:25:00.71#ibcon#*after write, iclass 21, count 0 2006.173.06:25:00.71#ibcon#*before return 0, iclass 21, count 0 2006.173.06:25:00.71#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.06:25:00.71#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.06:25:00.71#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.06:25:00.71#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.06:25:00.71$vck44/vbbw=wide 2006.173.06:25:00.71#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.06:25:00.71#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.06:25:00.71#ibcon#ireg 8 cls_cnt 0 2006.173.06:25:00.71#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.06:25:00.78#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.06:25:00.78#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.06:25:00.78#ibcon#enter wrdev, iclass 23, count 0 2006.173.06:25:00.78#ibcon#first serial, iclass 23, count 0 2006.173.06:25:00.78#ibcon#enter sib2, iclass 23, count 0 2006.173.06:25:00.78#ibcon#flushed, iclass 23, count 0 2006.173.06:25:00.78#ibcon#about to write, iclass 23, count 0 2006.173.06:25:00.78#ibcon#wrote, iclass 23, count 0 2006.173.06:25:00.78#ibcon#about to read 3, iclass 23, count 0 2006.173.06:25:00.80#ibcon#read 3, iclass 23, count 0 2006.173.06:25:00.80#ibcon#about to read 4, iclass 23, count 0 2006.173.06:25:00.80#ibcon#read 4, iclass 23, count 0 2006.173.06:25:00.80#ibcon#about to read 5, iclass 23, count 0 2006.173.06:25:00.80#ibcon#read 5, iclass 23, count 0 2006.173.06:25:00.80#ibcon#about to read 6, iclass 23, count 0 2006.173.06:25:00.80#ibcon#read 6, iclass 23, count 0 2006.173.06:25:00.80#ibcon#end of sib2, iclass 23, count 0 2006.173.06:25:00.80#ibcon#*mode == 0, iclass 23, count 0 2006.173.06:25:00.80#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.06:25:00.80#ibcon#[27=BW32\r\n] 2006.173.06:25:00.80#ibcon#*before write, iclass 23, count 0 2006.173.06:25:00.80#ibcon#enter sib2, iclass 23, count 0 2006.173.06:25:00.80#ibcon#flushed, iclass 23, count 0 2006.173.06:25:00.80#ibcon#about to write, iclass 23, count 0 2006.173.06:25:00.80#ibcon#wrote, iclass 23, count 0 2006.173.06:25:00.80#ibcon#about to read 3, iclass 23, count 0 2006.173.06:25:00.83#ibcon#read 3, iclass 23, count 0 2006.173.06:25:00.83#ibcon#about to read 4, iclass 23, count 0 2006.173.06:25:00.83#ibcon#read 4, iclass 23, count 0 2006.173.06:25:00.83#ibcon#about to read 5, iclass 23, count 0 2006.173.06:25:00.83#ibcon#read 5, iclass 23, count 0 2006.173.06:25:00.83#ibcon#about to read 6, iclass 23, count 0 2006.173.06:25:00.83#ibcon#read 6, iclass 23, count 0 2006.173.06:25:00.83#ibcon#end of sib2, iclass 23, count 0 2006.173.06:25:00.83#ibcon#*after write, iclass 23, count 0 2006.173.06:25:00.83#ibcon#*before return 0, iclass 23, count 0 2006.173.06:25:00.83#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.06:25:00.83#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.06:25:00.83#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.06:25:00.83#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.06:25:00.83$setupk4/ifdk4 2006.173.06:25:00.83$ifdk4/lo= 2006.173.06:25:00.83$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.06:25:00.83$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.06:25:00.83$ifdk4/patch= 2006.173.06:25:00.83$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.06:25:00.83$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.06:25:00.83$setupk4/!*+20s 2006.173.06:25:02.76#abcon#<5=/16 0.6 1.0 23.86 761005.2\r\n> 2006.173.06:25:02.78#abcon#{5=INTERFACE CLEAR} 2006.173.06:25:02.84#abcon#[5=S1D000X0/0*\r\n] 2006.173.06:25:12.93#abcon#<5=/16 0.6 1.0 23.86 761005.1\r\n> 2006.173.06:25:12.95#abcon#{5=INTERFACE CLEAR} 2006.173.06:25:13.01#abcon#[5=S1D000X0/0*\r\n] 2006.173.06:25:15.34$setupk4/"tpicd 2006.173.06:25:15.34$setupk4/echo=off 2006.173.06:25:15.34$setupk4/xlog=off 2006.173.06:25:15.34:!2006.173.06:32:24 2006.173.06:26:05.14#trakl#Source acquired 2006.173.06:26:06.14#flagr#flagr/antenna,acquired 2006.173.06:32:24.00:preob 2006.173.06:32:25.14/onsource/TRACKING 2006.173.06:32:25.14:!2006.173.06:32:34 2006.173.06:32:34.00:"tape 2006.173.06:32:34.00:"st=record 2006.173.06:32:34.00:data_valid=on 2006.173.06:32:34.00:midob 2006.173.06:32:34.14/onsource/TRACKING 2006.173.06:32:34.14/wx/23.85,1005.0,76 2006.173.06:32:34.30/cable/+6.5036E-03 2006.173.06:32:35.39/va/01,07,usb,yes,35,38 2006.173.06:32:35.39/va/02,06,usb,yes,35,35 2006.173.06:32:35.39/va/03,05,usb,yes,44,46 2006.173.06:32:35.39/va/04,06,usb,yes,35,37 2006.173.06:32:35.39/va/05,04,usb,yes,28,28 2006.173.06:32:35.39/va/06,03,usb,yes,39,39 2006.173.06:32:35.39/va/07,04,usb,yes,31,33 2006.173.06:32:35.39/va/08,04,usb,yes,27,32 2006.173.06:32:35.62/valo/01,524.99,yes,locked 2006.173.06:32:35.62/valo/02,534.99,yes,locked 2006.173.06:32:35.62/valo/03,564.99,yes,locked 2006.173.06:32:35.62/valo/04,624.99,yes,locked 2006.173.06:32:35.62/valo/05,734.99,yes,locked 2006.173.06:32:35.62/valo/06,814.99,yes,locked 2006.173.06:32:35.62/valo/07,864.99,yes,locked 2006.173.06:32:35.62/valo/08,884.99,yes,locked 2006.173.06:32:36.71/vb/01,04,usb,yes,29,27 2006.173.06:32:36.71/vb/02,04,usb,yes,32,31 2006.173.06:32:36.71/vb/03,04,usb,yes,28,31 2006.173.06:32:36.71/vb/04,04,usb,yes,33,32 2006.173.06:32:36.71/vb/05,04,usb,yes,25,28 2006.173.06:32:36.71/vb/06,04,usb,yes,30,26 2006.173.06:32:36.71/vb/07,04,usb,yes,30,29 2006.173.06:32:36.71/vb/08,04,usb,yes,27,30 2006.173.06:32:36.94/vblo/01,629.99,yes,locked 2006.173.06:32:36.94/vblo/02,634.99,yes,locked 2006.173.06:32:36.94/vblo/03,649.99,yes,locked 2006.173.06:32:36.94/vblo/04,679.99,yes,locked 2006.173.06:32:36.94/vblo/05,709.99,yes,locked 2006.173.06:32:36.94/vblo/06,719.99,yes,locked 2006.173.06:32:36.94/vblo/07,734.99,yes,locked 2006.173.06:32:36.94/vblo/08,744.99,yes,locked 2006.173.06:32:37.09/vabw/8 2006.173.06:32:37.24/vbbw/8 2006.173.06:32:37.33/xfe/off,on,15.2 2006.173.06:32:37.73/ifatt/23,28,28,28 2006.173.06:32:38.08/fmout-gps/S +3.99E-07 2006.173.06:32:38.13:!2006.173.06:33:24 2006.173.06:33:24.00:data_valid=off 2006.173.06:33:24.00:"et 2006.173.06:33:24.00:!+3s 2006.173.06:33:27.02:"tape 2006.173.06:33:27.02:postob 2006.173.06:33:27.09/cable/+6.5034E-03 2006.173.06:33:27.09/wx/23.83,1005.0,76 2006.173.06:33:28.08/fmout-gps/S +3.98E-07 2006.173.06:33:28.08:scan_name=173-0635,jd0606,60 2006.173.06:33:28.08:source=0727-115,073019.11,-114112.6,2000.0,ccw 2006.173.06:33:29.14#flagr#flagr/antenna,new-source 2006.173.06:33:29.14:checkk5 2006.173.06:33:29.60/chk_autoobs//k5ts1/ autoobs is running! 2006.173.06:33:30.02/chk_autoobs//k5ts2/ autoobs is running! 2006.173.06:33:30.41/chk_autoobs//k5ts3/ autoobs is running! 2006.173.06:33:30.80/chk_autoobs//k5ts4/ autoobs is running! 2006.173.06:33:31.21/chk_obsdata//k5ts1/T1730632??a.dat file size is correct (nominal:200MB, actual:196MB). 2006.173.06:33:31.61/chk_obsdata//k5ts2/T1730632??b.dat file size is correct (nominal:200MB, actual:196MB). 2006.173.06:33:32.01/chk_obsdata//k5ts3/T1730632??c.dat file size is correct (nominal:200MB, actual:196MB). 2006.173.06:33:32.41/chk_obsdata//k5ts4/T1730632??d.dat file size is correct (nominal:200MB, actual:196MB). 2006.173.06:33:33.12/k5log//k5ts1_log_newline 2006.173.06:33:33.83/k5log//k5ts2_log_newline 2006.173.06:33:34.53/k5log//k5ts3_log_newline 2006.173.06:33:35.24/k5log//k5ts4_log_newline 2006.173.06:33:35.26/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.06:33:35.26:setupk4=1 2006.173.06:33:35.26$setupk4/echo=on 2006.173.06:33:35.26$setupk4/pcalon 2006.173.06:33:35.26$pcalon/"no phase cal control is implemented here 2006.173.06:33:35.26$setupk4/"tpicd=stop 2006.173.06:33:35.26$setupk4/"rec=synch_on 2006.173.06:33:35.26$setupk4/"rec_mode=128 2006.173.06:33:35.26$setupk4/!* 2006.173.06:33:35.26$setupk4/recpk4 2006.173.06:33:35.26$recpk4/recpatch= 2006.173.06:33:35.27$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.06:33:35.27$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.06:33:35.27$setupk4/vck44 2006.173.06:33:35.27$vck44/valo=1,524.99 2006.173.06:33:35.27#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.06:33:35.27#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.06:33:35.27#ibcon#ireg 17 cls_cnt 0 2006.173.06:33:35.27#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.06:33:35.27#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.06:33:35.27#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.06:33:35.27#ibcon#enter wrdev, iclass 16, count 0 2006.173.06:33:35.27#ibcon#first serial, iclass 16, count 0 2006.173.06:33:35.27#ibcon#enter sib2, iclass 16, count 0 2006.173.06:33:35.27#ibcon#flushed, iclass 16, count 0 2006.173.06:33:35.27#ibcon#about to write, iclass 16, count 0 2006.173.06:33:35.27#ibcon#wrote, iclass 16, count 0 2006.173.06:33:35.27#ibcon#about to read 3, iclass 16, count 0 2006.173.06:33:35.28#ibcon#read 3, iclass 16, count 0 2006.173.06:33:35.28#ibcon#about to read 4, iclass 16, count 0 2006.173.06:33:35.29#ibcon#read 4, iclass 16, count 0 2006.173.06:33:35.29#ibcon#about to read 5, iclass 16, count 0 2006.173.06:33:35.29#ibcon#read 5, iclass 16, count 0 2006.173.06:33:35.29#ibcon#about to read 6, iclass 16, count 0 2006.173.06:33:35.29#ibcon#read 6, iclass 16, count 0 2006.173.06:33:35.29#ibcon#end of sib2, iclass 16, count 0 2006.173.06:33:35.29#ibcon#*mode == 0, iclass 16, count 0 2006.173.06:33:35.29#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.06:33:35.29#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.06:33:35.29#ibcon#*before write, iclass 16, count 0 2006.173.06:33:35.29#ibcon#enter sib2, iclass 16, count 0 2006.173.06:33:35.29#ibcon#flushed, iclass 16, count 0 2006.173.06:33:35.29#ibcon#about to write, iclass 16, count 0 2006.173.06:33:35.29#ibcon#wrote, iclass 16, count 0 2006.173.06:33:35.29#ibcon#about to read 3, iclass 16, count 0 2006.173.06:33:35.33#ibcon#read 3, iclass 16, count 0 2006.173.06:33:35.33#ibcon#about to read 4, iclass 16, count 0 2006.173.06:33:35.34#ibcon#read 4, iclass 16, count 0 2006.173.06:33:35.34#ibcon#about to read 5, iclass 16, count 0 2006.173.06:33:35.34#ibcon#read 5, iclass 16, count 0 2006.173.06:33:35.34#ibcon#about to read 6, iclass 16, count 0 2006.173.06:33:35.34#ibcon#read 6, iclass 16, count 0 2006.173.06:33:35.34#ibcon#end of sib2, iclass 16, count 0 2006.173.06:33:35.34#ibcon#*after write, iclass 16, count 0 2006.173.06:33:35.34#ibcon#*before return 0, iclass 16, count 0 2006.173.06:33:35.34#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.06:33:35.34#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.06:33:35.34#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.06:33:35.34#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.06:33:35.34$vck44/va=1,7 2006.173.06:33:35.34#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.06:33:35.34#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.06:33:35.34#ibcon#ireg 11 cls_cnt 2 2006.173.06:33:35.34#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.06:33:35.34#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.06:33:35.34#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.06:33:35.34#ibcon#enter wrdev, iclass 18, count 2 2006.173.06:33:35.34#ibcon#first serial, iclass 18, count 2 2006.173.06:33:35.34#ibcon#enter sib2, iclass 18, count 2 2006.173.06:33:35.34#ibcon#flushed, iclass 18, count 2 2006.173.06:33:35.34#ibcon#about to write, iclass 18, count 2 2006.173.06:33:35.34#ibcon#wrote, iclass 18, count 2 2006.173.06:33:35.34#ibcon#about to read 3, iclass 18, count 2 2006.173.06:33:35.35#ibcon#read 3, iclass 18, count 2 2006.173.06:33:35.35#ibcon#about to read 4, iclass 18, count 2 2006.173.06:33:35.35#ibcon#read 4, iclass 18, count 2 2006.173.06:33:35.35#ibcon#about to read 5, iclass 18, count 2 2006.173.06:33:35.36#ibcon#read 5, iclass 18, count 2 2006.173.06:33:35.36#ibcon#about to read 6, iclass 18, count 2 2006.173.06:33:35.36#ibcon#read 6, iclass 18, count 2 2006.173.06:33:35.36#ibcon#end of sib2, iclass 18, count 2 2006.173.06:33:35.36#ibcon#*mode == 0, iclass 18, count 2 2006.173.06:33:35.36#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.06:33:35.36#ibcon#[25=AT01-07\r\n] 2006.173.06:33:35.36#ibcon#*before write, iclass 18, count 2 2006.173.06:33:35.36#ibcon#enter sib2, iclass 18, count 2 2006.173.06:33:35.36#ibcon#flushed, iclass 18, count 2 2006.173.06:33:35.36#ibcon#about to write, iclass 18, count 2 2006.173.06:33:35.36#ibcon#wrote, iclass 18, count 2 2006.173.06:33:35.36#ibcon#about to read 3, iclass 18, count 2 2006.173.06:33:35.38#ibcon#read 3, iclass 18, count 2 2006.173.06:33:35.39#ibcon#about to read 4, iclass 18, count 2 2006.173.06:33:35.39#ibcon#read 4, iclass 18, count 2 2006.173.06:33:35.39#ibcon#about to read 5, iclass 18, count 2 2006.173.06:33:35.39#ibcon#read 5, iclass 18, count 2 2006.173.06:33:35.39#ibcon#about to read 6, iclass 18, count 2 2006.173.06:33:35.39#ibcon#read 6, iclass 18, count 2 2006.173.06:33:35.39#ibcon#end of sib2, iclass 18, count 2 2006.173.06:33:35.39#ibcon#*after write, iclass 18, count 2 2006.173.06:33:35.39#ibcon#*before return 0, iclass 18, count 2 2006.173.06:33:35.39#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.06:33:35.39#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.06:33:35.39#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.06:33:35.39#ibcon#ireg 7 cls_cnt 0 2006.173.06:33:35.39#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.06:33:35.50#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.06:33:35.50#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.06:33:35.50#ibcon#enter wrdev, iclass 18, count 0 2006.173.06:33:35.51#ibcon#first serial, iclass 18, count 0 2006.173.06:33:35.51#ibcon#enter sib2, iclass 18, count 0 2006.173.06:33:35.51#ibcon#flushed, iclass 18, count 0 2006.173.06:33:35.51#ibcon#about to write, iclass 18, count 0 2006.173.06:33:35.51#ibcon#wrote, iclass 18, count 0 2006.173.06:33:35.51#ibcon#about to read 3, iclass 18, count 0 2006.173.06:33:35.52#ibcon#read 3, iclass 18, count 0 2006.173.06:33:35.52#ibcon#about to read 4, iclass 18, count 0 2006.173.06:33:35.53#ibcon#read 4, iclass 18, count 0 2006.173.06:33:35.53#ibcon#about to read 5, iclass 18, count 0 2006.173.06:33:35.53#ibcon#read 5, iclass 18, count 0 2006.173.06:33:35.53#ibcon#about to read 6, iclass 18, count 0 2006.173.06:33:35.53#ibcon#read 6, iclass 18, count 0 2006.173.06:33:35.53#ibcon#end of sib2, iclass 18, count 0 2006.173.06:33:35.53#ibcon#*mode == 0, iclass 18, count 0 2006.173.06:33:35.53#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.06:33:35.53#ibcon#[25=USB\r\n] 2006.173.06:33:35.53#ibcon#*before write, iclass 18, count 0 2006.173.06:33:35.53#ibcon#enter sib2, iclass 18, count 0 2006.173.06:33:35.53#ibcon#flushed, iclass 18, count 0 2006.173.06:33:35.53#ibcon#about to write, iclass 18, count 0 2006.173.06:33:35.53#ibcon#wrote, iclass 18, count 0 2006.173.06:33:35.53#ibcon#about to read 3, iclass 18, count 0 2006.173.06:33:35.55#ibcon#read 3, iclass 18, count 0 2006.173.06:33:35.55#ibcon#about to read 4, iclass 18, count 0 2006.173.06:33:35.55#ibcon#read 4, iclass 18, count 0 2006.173.06:33:35.55#ibcon#about to read 5, iclass 18, count 0 2006.173.06:33:35.56#ibcon#read 5, iclass 18, count 0 2006.173.06:33:35.56#ibcon#about to read 6, iclass 18, count 0 2006.173.06:33:35.56#ibcon#read 6, iclass 18, count 0 2006.173.06:33:35.56#ibcon#end of sib2, iclass 18, count 0 2006.173.06:33:35.56#ibcon#*after write, iclass 18, count 0 2006.173.06:33:35.56#ibcon#*before return 0, iclass 18, count 0 2006.173.06:33:35.56#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.06:33:35.56#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.06:33:35.56#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.06:33:35.56#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.06:33:35.56$vck44/valo=2,534.99 2006.173.06:33:35.56#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.06:33:35.56#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.06:33:35.56#ibcon#ireg 17 cls_cnt 0 2006.173.06:33:35.56#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.06:33:35.56#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.06:33:35.56#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.06:33:35.56#ibcon#enter wrdev, iclass 20, count 0 2006.173.06:33:35.56#ibcon#first serial, iclass 20, count 0 2006.173.06:33:35.56#ibcon#enter sib2, iclass 20, count 0 2006.173.06:33:35.56#ibcon#flushed, iclass 20, count 0 2006.173.06:33:35.56#ibcon#about to write, iclass 20, count 0 2006.173.06:33:35.56#ibcon#wrote, iclass 20, count 0 2006.173.06:33:35.56#ibcon#about to read 3, iclass 20, count 0 2006.173.06:33:35.57#ibcon#read 3, iclass 20, count 0 2006.173.06:33:35.57#ibcon#about to read 4, iclass 20, count 0 2006.173.06:33:35.58#ibcon#read 4, iclass 20, count 0 2006.173.06:33:35.58#ibcon#about to read 5, iclass 20, count 0 2006.173.06:33:35.58#ibcon#read 5, iclass 20, count 0 2006.173.06:33:35.58#ibcon#about to read 6, iclass 20, count 0 2006.173.06:33:35.58#ibcon#read 6, iclass 20, count 0 2006.173.06:33:35.58#ibcon#end of sib2, iclass 20, count 0 2006.173.06:33:35.58#ibcon#*mode == 0, iclass 20, count 0 2006.173.06:33:35.58#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.06:33:35.58#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.06:33:35.58#ibcon#*before write, iclass 20, count 0 2006.173.06:33:35.58#ibcon#enter sib2, iclass 20, count 0 2006.173.06:33:35.58#ibcon#flushed, iclass 20, count 0 2006.173.06:33:35.58#ibcon#about to write, iclass 20, count 0 2006.173.06:33:35.58#ibcon#wrote, iclass 20, count 0 2006.173.06:33:35.58#ibcon#about to read 3, iclass 20, count 0 2006.173.06:33:35.61#ibcon#read 3, iclass 20, count 0 2006.173.06:33:35.61#ibcon#about to read 4, iclass 20, count 0 2006.173.06:33:35.61#ibcon#read 4, iclass 20, count 0 2006.173.06:33:35.62#ibcon#about to read 5, iclass 20, count 0 2006.173.06:33:35.62#ibcon#read 5, iclass 20, count 0 2006.173.06:33:35.62#ibcon#about to read 6, iclass 20, count 0 2006.173.06:33:35.62#ibcon#read 6, iclass 20, count 0 2006.173.06:33:35.62#ibcon#end of sib2, iclass 20, count 0 2006.173.06:33:35.62#ibcon#*after write, iclass 20, count 0 2006.173.06:33:35.62#ibcon#*before return 0, iclass 20, count 0 2006.173.06:33:35.62#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.06:33:35.62#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.06:33:35.62#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.06:33:35.62#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.06:33:35.62$vck44/va=2,6 2006.173.06:33:35.62#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.06:33:35.62#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.06:33:35.62#ibcon#ireg 11 cls_cnt 2 2006.173.06:33:35.62#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.06:33:35.67#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.06:33:35.67#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.06:33:35.67#ibcon#enter wrdev, iclass 22, count 2 2006.173.06:33:35.68#ibcon#first serial, iclass 22, count 2 2006.173.06:33:35.68#ibcon#enter sib2, iclass 22, count 2 2006.173.06:33:35.68#ibcon#flushed, iclass 22, count 2 2006.173.06:33:35.68#ibcon#about to write, iclass 22, count 2 2006.173.06:33:35.68#ibcon#wrote, iclass 22, count 2 2006.173.06:33:35.68#ibcon#about to read 3, iclass 22, count 2 2006.173.06:33:35.69#ibcon#read 3, iclass 22, count 2 2006.173.06:33:35.69#ibcon#about to read 4, iclass 22, count 2 2006.173.06:33:35.69#ibcon#read 4, iclass 22, count 2 2006.173.06:33:35.69#ibcon#about to read 5, iclass 22, count 2 2006.173.06:33:35.69#ibcon#read 5, iclass 22, count 2 2006.173.06:33:35.70#ibcon#about to read 6, iclass 22, count 2 2006.173.06:33:35.70#ibcon#read 6, iclass 22, count 2 2006.173.06:33:35.70#ibcon#end of sib2, iclass 22, count 2 2006.173.06:33:35.70#ibcon#*mode == 0, iclass 22, count 2 2006.173.06:33:35.70#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.06:33:35.70#ibcon#[25=AT02-06\r\n] 2006.173.06:33:35.70#ibcon#*before write, iclass 22, count 2 2006.173.06:33:35.70#ibcon#enter sib2, iclass 22, count 2 2006.173.06:33:35.70#ibcon#flushed, iclass 22, count 2 2006.173.06:33:35.70#ibcon#about to write, iclass 22, count 2 2006.173.06:33:35.70#ibcon#wrote, iclass 22, count 2 2006.173.06:33:35.70#ibcon#about to read 3, iclass 22, count 2 2006.173.06:33:35.72#ibcon#read 3, iclass 22, count 2 2006.173.06:33:35.72#ibcon#about to read 4, iclass 22, count 2 2006.173.06:33:35.72#ibcon#read 4, iclass 22, count 2 2006.173.06:33:35.73#ibcon#about to read 5, iclass 22, count 2 2006.173.06:33:35.73#ibcon#read 5, iclass 22, count 2 2006.173.06:33:35.73#ibcon#about to read 6, iclass 22, count 2 2006.173.06:33:35.73#ibcon#read 6, iclass 22, count 2 2006.173.06:33:35.73#ibcon#end of sib2, iclass 22, count 2 2006.173.06:33:35.73#ibcon#*after write, iclass 22, count 2 2006.173.06:33:35.73#ibcon#*before return 0, iclass 22, count 2 2006.173.06:33:35.73#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.06:33:35.73#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.06:33:35.73#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.06:33:35.73#ibcon#ireg 7 cls_cnt 0 2006.173.06:33:35.73#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.06:33:35.84#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.06:33:35.84#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.06:33:35.84#ibcon#enter wrdev, iclass 22, count 0 2006.173.06:33:35.85#ibcon#first serial, iclass 22, count 0 2006.173.06:33:35.85#ibcon#enter sib2, iclass 22, count 0 2006.173.06:33:35.85#ibcon#flushed, iclass 22, count 0 2006.173.06:33:35.85#ibcon#about to write, iclass 22, count 0 2006.173.06:33:35.85#ibcon#wrote, iclass 22, count 0 2006.173.06:33:35.85#ibcon#about to read 3, iclass 22, count 0 2006.173.06:33:35.86#ibcon#read 3, iclass 22, count 0 2006.173.06:33:35.86#ibcon#about to read 4, iclass 22, count 0 2006.173.06:33:35.86#ibcon#read 4, iclass 22, count 0 2006.173.06:33:35.86#ibcon#about to read 5, iclass 22, count 0 2006.173.06:33:35.87#ibcon#read 5, iclass 22, count 0 2006.173.06:33:35.87#ibcon#about to read 6, iclass 22, count 0 2006.173.06:33:35.87#ibcon#read 6, iclass 22, count 0 2006.173.06:33:35.87#ibcon#end of sib2, iclass 22, count 0 2006.173.06:33:35.87#ibcon#*mode == 0, iclass 22, count 0 2006.173.06:33:35.87#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.06:33:35.87#ibcon#[25=USB\r\n] 2006.173.06:33:35.87#ibcon#*before write, iclass 22, count 0 2006.173.06:33:35.87#ibcon#enter sib2, iclass 22, count 0 2006.173.06:33:35.87#ibcon#flushed, iclass 22, count 0 2006.173.06:33:35.87#ibcon#about to write, iclass 22, count 0 2006.173.06:33:35.87#ibcon#wrote, iclass 22, count 0 2006.173.06:33:35.87#ibcon#about to read 3, iclass 22, count 0 2006.173.06:33:35.89#ibcon#read 3, iclass 22, count 0 2006.173.06:33:35.89#ibcon#about to read 4, iclass 22, count 0 2006.173.06:33:35.89#ibcon#read 4, iclass 22, count 0 2006.173.06:33:35.90#ibcon#about to read 5, iclass 22, count 0 2006.173.06:33:35.90#ibcon#read 5, iclass 22, count 0 2006.173.06:33:35.90#ibcon#about to read 6, iclass 22, count 0 2006.173.06:33:35.90#ibcon#read 6, iclass 22, count 0 2006.173.06:33:35.90#ibcon#end of sib2, iclass 22, count 0 2006.173.06:33:35.90#ibcon#*after write, iclass 22, count 0 2006.173.06:33:35.90#ibcon#*before return 0, iclass 22, count 0 2006.173.06:33:35.90#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.06:33:35.90#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.06:33:35.90#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.06:33:35.90#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.06:33:35.90$vck44/valo=3,564.99 2006.173.06:33:35.90#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.06:33:35.90#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.06:33:35.90#ibcon#ireg 17 cls_cnt 0 2006.173.06:33:35.90#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.06:33:35.90#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.06:33:35.90#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.06:33:35.90#ibcon#enter wrdev, iclass 24, count 0 2006.173.06:33:35.90#ibcon#first serial, iclass 24, count 0 2006.173.06:33:35.90#ibcon#enter sib2, iclass 24, count 0 2006.173.06:33:35.90#ibcon#flushed, iclass 24, count 0 2006.173.06:33:35.90#ibcon#about to write, iclass 24, count 0 2006.173.06:33:35.90#ibcon#wrote, iclass 24, count 0 2006.173.06:33:35.90#ibcon#about to read 3, iclass 24, count 0 2006.173.06:33:35.91#ibcon#read 3, iclass 24, count 0 2006.173.06:33:35.91#ibcon#about to read 4, iclass 24, count 0 2006.173.06:33:35.91#ibcon#read 4, iclass 24, count 0 2006.173.06:33:35.91#ibcon#about to read 5, iclass 24, count 0 2006.173.06:33:35.92#ibcon#read 5, iclass 24, count 0 2006.173.06:33:35.92#ibcon#about to read 6, iclass 24, count 0 2006.173.06:33:35.92#ibcon#read 6, iclass 24, count 0 2006.173.06:33:35.92#ibcon#end of sib2, iclass 24, count 0 2006.173.06:33:35.92#ibcon#*mode == 0, iclass 24, count 0 2006.173.06:33:35.92#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.06:33:35.92#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.06:33:35.92#ibcon#*before write, iclass 24, count 0 2006.173.06:33:35.92#ibcon#enter sib2, iclass 24, count 0 2006.173.06:33:35.92#ibcon#flushed, iclass 24, count 0 2006.173.06:33:35.92#ibcon#about to write, iclass 24, count 0 2006.173.06:33:35.92#ibcon#wrote, iclass 24, count 0 2006.173.06:33:35.92#ibcon#about to read 3, iclass 24, count 0 2006.173.06:33:35.95#ibcon#read 3, iclass 24, count 0 2006.173.06:33:35.95#ibcon#about to read 4, iclass 24, count 0 2006.173.06:33:35.95#ibcon#read 4, iclass 24, count 0 2006.173.06:33:35.96#ibcon#about to read 5, iclass 24, count 0 2006.173.06:33:35.96#ibcon#read 5, iclass 24, count 0 2006.173.06:33:35.96#ibcon#about to read 6, iclass 24, count 0 2006.173.06:33:35.96#ibcon#read 6, iclass 24, count 0 2006.173.06:33:35.96#ibcon#end of sib2, iclass 24, count 0 2006.173.06:33:35.96#ibcon#*after write, iclass 24, count 0 2006.173.06:33:35.96#ibcon#*before return 0, iclass 24, count 0 2006.173.06:33:35.96#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.06:33:35.96#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.06:33:35.96#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.06:33:35.96#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.06:33:35.96$vck44/va=3,5 2006.173.06:33:35.96#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.06:33:35.96#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.06:33:35.96#ibcon#ireg 11 cls_cnt 2 2006.173.06:33:35.96#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.06:33:36.01#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.06:33:36.01#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.06:33:36.01#ibcon#enter wrdev, iclass 26, count 2 2006.173.06:33:36.02#ibcon#first serial, iclass 26, count 2 2006.173.06:33:36.02#ibcon#enter sib2, iclass 26, count 2 2006.173.06:33:36.02#ibcon#flushed, iclass 26, count 2 2006.173.06:33:36.02#ibcon#about to write, iclass 26, count 2 2006.173.06:33:36.02#ibcon#wrote, iclass 26, count 2 2006.173.06:33:36.02#ibcon#about to read 3, iclass 26, count 2 2006.173.06:33:36.03#ibcon#read 3, iclass 26, count 2 2006.173.06:33:36.03#ibcon#about to read 4, iclass 26, count 2 2006.173.06:33:36.03#ibcon#read 4, iclass 26, count 2 2006.173.06:33:36.03#ibcon#about to read 5, iclass 26, count 2 2006.173.06:33:36.04#ibcon#read 5, iclass 26, count 2 2006.173.06:33:36.04#ibcon#about to read 6, iclass 26, count 2 2006.173.06:33:36.04#ibcon#read 6, iclass 26, count 2 2006.173.06:33:36.04#ibcon#end of sib2, iclass 26, count 2 2006.173.06:33:36.04#ibcon#*mode == 0, iclass 26, count 2 2006.173.06:33:36.04#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.06:33:36.04#ibcon#[25=AT03-05\r\n] 2006.173.06:33:36.04#ibcon#*before write, iclass 26, count 2 2006.173.06:33:36.04#ibcon#enter sib2, iclass 26, count 2 2006.173.06:33:36.04#ibcon#flushed, iclass 26, count 2 2006.173.06:33:36.04#ibcon#about to write, iclass 26, count 2 2006.173.06:33:36.04#ibcon#wrote, iclass 26, count 2 2006.173.06:33:36.04#ibcon#about to read 3, iclass 26, count 2 2006.173.06:33:36.06#ibcon#read 3, iclass 26, count 2 2006.173.06:33:36.06#ibcon#about to read 4, iclass 26, count 2 2006.173.06:33:36.06#ibcon#read 4, iclass 26, count 2 2006.173.06:33:36.07#ibcon#about to read 5, iclass 26, count 2 2006.173.06:33:36.07#ibcon#read 5, iclass 26, count 2 2006.173.06:33:36.07#ibcon#about to read 6, iclass 26, count 2 2006.173.06:33:36.07#ibcon#read 6, iclass 26, count 2 2006.173.06:33:36.07#ibcon#end of sib2, iclass 26, count 2 2006.173.06:33:36.07#ibcon#*after write, iclass 26, count 2 2006.173.06:33:36.07#ibcon#*before return 0, iclass 26, count 2 2006.173.06:33:36.07#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.06:33:36.07#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.06:33:36.07#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.06:33:36.07#ibcon#ireg 7 cls_cnt 0 2006.173.06:33:36.07#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.06:33:36.19#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.06:33:36.19#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.06:33:36.19#ibcon#enter wrdev, iclass 26, count 0 2006.173.06:33:36.19#ibcon#first serial, iclass 26, count 0 2006.173.06:33:36.19#ibcon#enter sib2, iclass 26, count 0 2006.173.06:33:36.19#ibcon#flushed, iclass 26, count 0 2006.173.06:33:36.19#ibcon#about to write, iclass 26, count 0 2006.173.06:33:36.19#ibcon#wrote, iclass 26, count 0 2006.173.06:33:36.19#ibcon#about to read 3, iclass 26, count 0 2006.173.06:33:36.20#ibcon#read 3, iclass 26, count 0 2006.173.06:33:36.21#ibcon#about to read 4, iclass 26, count 0 2006.173.06:33:36.21#ibcon#read 4, iclass 26, count 0 2006.173.06:33:36.21#ibcon#about to read 5, iclass 26, count 0 2006.173.06:33:36.21#ibcon#read 5, iclass 26, count 0 2006.173.06:33:36.21#ibcon#about to read 6, iclass 26, count 0 2006.173.06:33:36.21#ibcon#read 6, iclass 26, count 0 2006.173.06:33:36.21#ibcon#end of sib2, iclass 26, count 0 2006.173.06:33:36.21#ibcon#*mode == 0, iclass 26, count 0 2006.173.06:33:36.21#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.06:33:36.21#ibcon#[25=USB\r\n] 2006.173.06:33:36.21#ibcon#*before write, iclass 26, count 0 2006.173.06:33:36.21#ibcon#enter sib2, iclass 26, count 0 2006.173.06:33:36.21#ibcon#flushed, iclass 26, count 0 2006.173.06:33:36.21#ibcon#about to write, iclass 26, count 0 2006.173.06:33:36.21#ibcon#wrote, iclass 26, count 0 2006.173.06:33:36.21#ibcon#about to read 3, iclass 26, count 0 2006.173.06:33:36.23#ibcon#read 3, iclass 26, count 0 2006.173.06:33:36.24#ibcon#about to read 4, iclass 26, count 0 2006.173.06:33:36.24#ibcon#read 4, iclass 26, count 0 2006.173.06:33:36.24#ibcon#about to read 5, iclass 26, count 0 2006.173.06:33:36.24#ibcon#read 5, iclass 26, count 0 2006.173.06:33:36.24#ibcon#about to read 6, iclass 26, count 0 2006.173.06:33:36.24#ibcon#read 6, iclass 26, count 0 2006.173.06:33:36.24#ibcon#end of sib2, iclass 26, count 0 2006.173.06:33:36.24#ibcon#*after write, iclass 26, count 0 2006.173.06:33:36.24#ibcon#*before return 0, iclass 26, count 0 2006.173.06:33:36.24#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.06:33:36.24#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.06:33:36.24#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.06:33:36.24#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.06:33:36.24$vck44/valo=4,624.99 2006.173.06:33:36.24#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.06:33:36.24#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.06:33:36.24#ibcon#ireg 17 cls_cnt 0 2006.173.06:33:36.24#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.06:33:36.24#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.06:33:36.24#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.06:33:36.24#ibcon#enter wrdev, iclass 28, count 0 2006.173.06:33:36.24#ibcon#first serial, iclass 28, count 0 2006.173.06:33:36.24#ibcon#enter sib2, iclass 28, count 0 2006.173.06:33:36.24#ibcon#flushed, iclass 28, count 0 2006.173.06:33:36.24#ibcon#about to write, iclass 28, count 0 2006.173.06:33:36.24#ibcon#wrote, iclass 28, count 0 2006.173.06:33:36.24#ibcon#about to read 3, iclass 28, count 0 2006.173.06:33:36.25#ibcon#read 3, iclass 28, count 0 2006.173.06:33:36.26#ibcon#about to read 4, iclass 28, count 0 2006.173.06:33:36.26#ibcon#read 4, iclass 28, count 0 2006.173.06:33:36.26#ibcon#about to read 5, iclass 28, count 0 2006.173.06:33:36.26#ibcon#read 5, iclass 28, count 0 2006.173.06:33:36.26#ibcon#about to read 6, iclass 28, count 0 2006.173.06:33:36.26#ibcon#read 6, iclass 28, count 0 2006.173.06:33:36.26#ibcon#end of sib2, iclass 28, count 0 2006.173.06:33:36.26#ibcon#*mode == 0, iclass 28, count 0 2006.173.06:33:36.26#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.06:33:36.26#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.06:33:36.26#ibcon#*before write, iclass 28, count 0 2006.173.06:33:36.26#ibcon#enter sib2, iclass 28, count 0 2006.173.06:33:36.26#ibcon#flushed, iclass 28, count 0 2006.173.06:33:36.26#ibcon#about to write, iclass 28, count 0 2006.173.06:33:36.26#ibcon#wrote, iclass 28, count 0 2006.173.06:33:36.26#ibcon#about to read 3, iclass 28, count 0 2006.173.06:33:36.29#ibcon#read 3, iclass 28, count 0 2006.173.06:33:36.29#ibcon#about to read 4, iclass 28, count 0 2006.173.06:33:36.30#ibcon#read 4, iclass 28, count 0 2006.173.06:33:36.30#ibcon#about to read 5, iclass 28, count 0 2006.173.06:33:36.30#ibcon#read 5, iclass 28, count 0 2006.173.06:33:36.30#ibcon#about to read 6, iclass 28, count 0 2006.173.06:33:36.30#ibcon#read 6, iclass 28, count 0 2006.173.06:33:36.30#ibcon#end of sib2, iclass 28, count 0 2006.173.06:33:36.30#ibcon#*after write, iclass 28, count 0 2006.173.06:33:36.30#ibcon#*before return 0, iclass 28, count 0 2006.173.06:33:36.30#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.06:33:36.30#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.06:33:36.30#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.06:33:36.30#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.06:33:36.30$vck44/va=4,6 2006.173.06:33:36.30#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.06:33:36.30#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.06:33:36.30#ibcon#ireg 11 cls_cnt 2 2006.173.06:33:36.30#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.06:33:36.35#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.06:33:36.35#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.06:33:36.35#ibcon#enter wrdev, iclass 30, count 2 2006.173.06:33:36.36#ibcon#first serial, iclass 30, count 2 2006.173.06:33:36.36#ibcon#enter sib2, iclass 30, count 2 2006.173.06:33:36.36#ibcon#flushed, iclass 30, count 2 2006.173.06:33:36.36#ibcon#about to write, iclass 30, count 2 2006.173.06:33:36.36#ibcon#wrote, iclass 30, count 2 2006.173.06:33:36.36#ibcon#about to read 3, iclass 30, count 2 2006.173.06:33:36.37#ibcon#read 3, iclass 30, count 2 2006.173.06:33:36.37#ibcon#about to read 4, iclass 30, count 2 2006.173.06:33:36.38#ibcon#read 4, iclass 30, count 2 2006.173.06:33:36.38#ibcon#about to read 5, iclass 30, count 2 2006.173.06:33:36.38#ibcon#read 5, iclass 30, count 2 2006.173.06:33:36.38#ibcon#about to read 6, iclass 30, count 2 2006.173.06:33:36.38#ibcon#read 6, iclass 30, count 2 2006.173.06:33:36.38#ibcon#end of sib2, iclass 30, count 2 2006.173.06:33:36.38#ibcon#*mode == 0, iclass 30, count 2 2006.173.06:33:36.38#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.06:33:36.38#ibcon#[25=AT04-06\r\n] 2006.173.06:33:36.38#ibcon#*before write, iclass 30, count 2 2006.173.06:33:36.38#ibcon#enter sib2, iclass 30, count 2 2006.173.06:33:36.38#ibcon#flushed, iclass 30, count 2 2006.173.06:33:36.38#ibcon#about to write, iclass 30, count 2 2006.173.06:33:36.38#ibcon#wrote, iclass 30, count 2 2006.173.06:33:36.38#ibcon#about to read 3, iclass 30, count 2 2006.173.06:33:36.40#ibcon#read 3, iclass 30, count 2 2006.173.06:33:36.41#ibcon#about to read 4, iclass 30, count 2 2006.173.06:33:36.41#ibcon#read 4, iclass 30, count 2 2006.173.06:33:36.41#ibcon#about to read 5, iclass 30, count 2 2006.173.06:33:36.41#ibcon#read 5, iclass 30, count 2 2006.173.06:33:36.41#ibcon#about to read 6, iclass 30, count 2 2006.173.06:33:36.41#ibcon#read 6, iclass 30, count 2 2006.173.06:33:36.41#ibcon#end of sib2, iclass 30, count 2 2006.173.06:33:36.41#ibcon#*after write, iclass 30, count 2 2006.173.06:33:36.41#ibcon#*before return 0, iclass 30, count 2 2006.173.06:33:36.41#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.06:33:36.41#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.06:33:36.41#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.06:33:36.41#ibcon#ireg 7 cls_cnt 0 2006.173.06:33:36.41#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.06:33:36.52#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.06:33:36.52#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.06:33:36.52#ibcon#enter wrdev, iclass 30, count 0 2006.173.06:33:36.53#ibcon#first serial, iclass 30, count 0 2006.173.06:33:36.53#ibcon#enter sib2, iclass 30, count 0 2006.173.06:33:36.53#ibcon#flushed, iclass 30, count 0 2006.173.06:33:36.53#ibcon#about to write, iclass 30, count 0 2006.173.06:33:36.53#ibcon#wrote, iclass 30, count 0 2006.173.06:33:36.53#ibcon#about to read 3, iclass 30, count 0 2006.173.06:33:36.54#ibcon#read 3, iclass 30, count 0 2006.173.06:33:36.55#ibcon#about to read 4, iclass 30, count 0 2006.173.06:33:36.55#ibcon#read 4, iclass 30, count 0 2006.173.06:33:36.55#ibcon#about to read 5, iclass 30, count 0 2006.173.06:33:36.55#ibcon#read 5, iclass 30, count 0 2006.173.06:33:36.55#ibcon#about to read 6, iclass 30, count 0 2006.173.06:33:36.55#ibcon#read 6, iclass 30, count 0 2006.173.06:33:36.55#ibcon#end of sib2, iclass 30, count 0 2006.173.06:33:36.55#ibcon#*mode == 0, iclass 30, count 0 2006.173.06:33:36.55#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.06:33:36.55#ibcon#[25=USB\r\n] 2006.173.06:33:36.55#ibcon#*before write, iclass 30, count 0 2006.173.06:33:36.55#ibcon#enter sib2, iclass 30, count 0 2006.173.06:33:36.55#ibcon#flushed, iclass 30, count 0 2006.173.06:33:36.55#ibcon#about to write, iclass 30, count 0 2006.173.06:33:36.55#ibcon#wrote, iclass 30, count 0 2006.173.06:33:36.55#ibcon#about to read 3, iclass 30, count 0 2006.173.06:33:36.57#ibcon#read 3, iclass 30, count 0 2006.173.06:33:36.57#ibcon#about to read 4, iclass 30, count 0 2006.173.06:33:36.58#ibcon#read 4, iclass 30, count 0 2006.173.06:33:36.58#ibcon#about to read 5, iclass 30, count 0 2006.173.06:33:36.58#ibcon#read 5, iclass 30, count 0 2006.173.06:33:36.58#ibcon#about to read 6, iclass 30, count 0 2006.173.06:33:36.58#ibcon#read 6, iclass 30, count 0 2006.173.06:33:36.58#ibcon#end of sib2, iclass 30, count 0 2006.173.06:33:36.58#ibcon#*after write, iclass 30, count 0 2006.173.06:33:36.58#ibcon#*before return 0, iclass 30, count 0 2006.173.06:33:36.58#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.06:33:36.58#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.06:33:36.58#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.06:33:36.58#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.06:33:36.58$vck44/valo=5,734.99 2006.173.06:33:36.58#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.06:33:36.58#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.06:33:36.58#ibcon#ireg 17 cls_cnt 0 2006.173.06:33:36.58#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.06:33:36.58#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.06:33:36.58#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.06:33:36.58#ibcon#enter wrdev, iclass 32, count 0 2006.173.06:33:36.58#ibcon#first serial, iclass 32, count 0 2006.173.06:33:36.58#ibcon#enter sib2, iclass 32, count 0 2006.173.06:33:36.58#ibcon#flushed, iclass 32, count 0 2006.173.06:33:36.58#ibcon#about to write, iclass 32, count 0 2006.173.06:33:36.58#ibcon#wrote, iclass 32, count 0 2006.173.06:33:36.58#ibcon#about to read 3, iclass 32, count 0 2006.173.06:33:36.59#ibcon#read 3, iclass 32, count 0 2006.173.06:33:36.59#ibcon#about to read 4, iclass 32, count 0 2006.173.06:33:36.59#ibcon#read 4, iclass 32, count 0 2006.173.06:33:36.60#ibcon#about to read 5, iclass 32, count 0 2006.173.06:33:36.60#ibcon#read 5, iclass 32, count 0 2006.173.06:33:36.60#ibcon#about to read 6, iclass 32, count 0 2006.173.06:33:36.60#ibcon#read 6, iclass 32, count 0 2006.173.06:33:36.60#ibcon#end of sib2, iclass 32, count 0 2006.173.06:33:36.60#ibcon#*mode == 0, iclass 32, count 0 2006.173.06:33:36.60#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.06:33:36.60#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.06:33:36.60#ibcon#*before write, iclass 32, count 0 2006.173.06:33:36.60#ibcon#enter sib2, iclass 32, count 0 2006.173.06:33:36.60#ibcon#flushed, iclass 32, count 0 2006.173.06:33:36.60#ibcon#about to write, iclass 32, count 0 2006.173.06:33:36.60#ibcon#wrote, iclass 32, count 0 2006.173.06:33:36.60#ibcon#about to read 3, iclass 32, count 0 2006.173.06:33:36.63#ibcon#read 3, iclass 32, count 0 2006.173.06:33:36.63#ibcon#about to read 4, iclass 32, count 0 2006.173.06:33:36.64#ibcon#read 4, iclass 32, count 0 2006.173.06:33:36.64#ibcon#about to read 5, iclass 32, count 0 2006.173.06:33:36.64#ibcon#read 5, iclass 32, count 0 2006.173.06:33:36.64#ibcon#about to read 6, iclass 32, count 0 2006.173.06:33:36.64#ibcon#read 6, iclass 32, count 0 2006.173.06:33:36.64#ibcon#end of sib2, iclass 32, count 0 2006.173.06:33:36.64#ibcon#*after write, iclass 32, count 0 2006.173.06:33:36.64#ibcon#*before return 0, iclass 32, count 0 2006.173.06:33:36.64#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.06:33:36.64#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.06:33:36.64#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.06:33:36.64#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.06:33:36.64$vck44/va=5,4 2006.173.06:33:36.64#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.06:33:36.64#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.06:33:36.64#ibcon#ireg 11 cls_cnt 2 2006.173.06:33:36.64#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.06:33:36.69#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.06:33:36.69#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.06:33:36.69#ibcon#enter wrdev, iclass 34, count 2 2006.173.06:33:36.70#ibcon#first serial, iclass 34, count 2 2006.173.06:33:36.70#ibcon#enter sib2, iclass 34, count 2 2006.173.06:33:36.70#ibcon#flushed, iclass 34, count 2 2006.173.06:33:36.70#ibcon#about to write, iclass 34, count 2 2006.173.06:33:36.70#ibcon#wrote, iclass 34, count 2 2006.173.06:33:36.70#ibcon#about to read 3, iclass 34, count 2 2006.173.06:33:36.71#ibcon#read 3, iclass 34, count 2 2006.173.06:33:36.71#ibcon#about to read 4, iclass 34, count 2 2006.173.06:33:36.71#ibcon#read 4, iclass 34, count 2 2006.173.06:33:36.71#ibcon#about to read 5, iclass 34, count 2 2006.173.06:33:36.72#ibcon#read 5, iclass 34, count 2 2006.173.06:33:36.72#ibcon#about to read 6, iclass 34, count 2 2006.173.06:33:36.72#ibcon#read 6, iclass 34, count 2 2006.173.06:33:36.72#ibcon#end of sib2, iclass 34, count 2 2006.173.06:33:36.72#ibcon#*mode == 0, iclass 34, count 2 2006.173.06:33:36.72#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.06:33:36.72#ibcon#[25=AT05-04\r\n] 2006.173.06:33:36.72#ibcon#*before write, iclass 34, count 2 2006.173.06:33:36.72#ibcon#enter sib2, iclass 34, count 2 2006.173.06:33:36.72#ibcon#flushed, iclass 34, count 2 2006.173.06:33:36.72#ibcon#about to write, iclass 34, count 2 2006.173.06:33:36.72#ibcon#wrote, iclass 34, count 2 2006.173.06:33:36.72#ibcon#about to read 3, iclass 34, count 2 2006.173.06:33:36.74#ibcon#read 3, iclass 34, count 2 2006.173.06:33:36.75#ibcon#about to read 4, iclass 34, count 2 2006.173.06:33:36.75#ibcon#read 4, iclass 34, count 2 2006.173.06:33:36.75#ibcon#about to read 5, iclass 34, count 2 2006.173.06:33:36.75#ibcon#read 5, iclass 34, count 2 2006.173.06:33:36.75#ibcon#about to read 6, iclass 34, count 2 2006.173.06:33:36.75#ibcon#read 6, iclass 34, count 2 2006.173.06:33:36.75#ibcon#end of sib2, iclass 34, count 2 2006.173.06:33:36.75#ibcon#*after write, iclass 34, count 2 2006.173.06:33:36.75#ibcon#*before return 0, iclass 34, count 2 2006.173.06:33:36.75#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.06:33:36.75#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.06:33:36.75#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.06:33:36.75#ibcon#ireg 7 cls_cnt 0 2006.173.06:33:36.75#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.06:33:36.86#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.06:33:36.86#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.06:33:36.86#ibcon#enter wrdev, iclass 34, count 0 2006.173.06:33:36.87#ibcon#first serial, iclass 34, count 0 2006.173.06:33:36.87#ibcon#enter sib2, iclass 34, count 0 2006.173.06:33:36.87#ibcon#flushed, iclass 34, count 0 2006.173.06:33:36.87#ibcon#about to write, iclass 34, count 0 2006.173.06:33:36.87#ibcon#wrote, iclass 34, count 0 2006.173.06:33:36.87#ibcon#about to read 3, iclass 34, count 0 2006.173.06:33:36.88#ibcon#read 3, iclass 34, count 0 2006.173.06:33:36.88#ibcon#about to read 4, iclass 34, count 0 2006.173.06:33:36.88#ibcon#read 4, iclass 34, count 0 2006.173.06:33:36.88#ibcon#about to read 5, iclass 34, count 0 2006.173.06:33:36.89#ibcon#read 5, iclass 34, count 0 2006.173.06:33:36.89#ibcon#about to read 6, iclass 34, count 0 2006.173.06:33:36.89#ibcon#read 6, iclass 34, count 0 2006.173.06:33:36.89#ibcon#end of sib2, iclass 34, count 0 2006.173.06:33:36.89#ibcon#*mode == 0, iclass 34, count 0 2006.173.06:33:36.89#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.06:33:36.89#ibcon#[25=USB\r\n] 2006.173.06:33:36.89#ibcon#*before write, iclass 34, count 0 2006.173.06:33:36.89#ibcon#enter sib2, iclass 34, count 0 2006.173.06:33:36.89#ibcon#flushed, iclass 34, count 0 2006.173.06:33:36.89#ibcon#about to write, iclass 34, count 0 2006.173.06:33:36.89#ibcon#wrote, iclass 34, count 0 2006.173.06:33:36.89#ibcon#about to read 3, iclass 34, count 0 2006.173.06:33:36.91#ibcon#read 3, iclass 34, count 0 2006.173.06:33:36.91#ibcon#about to read 4, iclass 34, count 0 2006.173.06:33:36.91#ibcon#read 4, iclass 34, count 0 2006.173.06:33:36.91#ibcon#about to read 5, iclass 34, count 0 2006.173.06:33:36.92#ibcon#read 5, iclass 34, count 0 2006.173.06:33:36.92#ibcon#about to read 6, iclass 34, count 0 2006.173.06:33:36.92#ibcon#read 6, iclass 34, count 0 2006.173.06:33:36.92#ibcon#end of sib2, iclass 34, count 0 2006.173.06:33:36.92#ibcon#*after write, iclass 34, count 0 2006.173.06:33:36.92#ibcon#*before return 0, iclass 34, count 0 2006.173.06:33:36.92#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.06:33:36.92#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.06:33:36.92#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.06:33:36.92#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.06:33:36.92$vck44/valo=6,814.99 2006.173.06:33:36.92#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.06:33:36.92#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.06:33:36.92#ibcon#ireg 17 cls_cnt 0 2006.173.06:33:36.92#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.06:33:36.92#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.06:33:36.92#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.06:33:36.92#ibcon#enter wrdev, iclass 36, count 0 2006.173.06:33:36.92#ibcon#first serial, iclass 36, count 0 2006.173.06:33:36.92#ibcon#enter sib2, iclass 36, count 0 2006.173.06:33:36.92#ibcon#flushed, iclass 36, count 0 2006.173.06:33:36.92#ibcon#about to write, iclass 36, count 0 2006.173.06:33:36.92#ibcon#wrote, iclass 36, count 0 2006.173.06:33:36.92#ibcon#about to read 3, iclass 36, count 0 2006.173.06:33:36.93#ibcon#read 3, iclass 36, count 0 2006.173.06:33:36.93#ibcon#about to read 4, iclass 36, count 0 2006.173.06:33:36.93#ibcon#read 4, iclass 36, count 0 2006.173.06:33:36.93#ibcon#about to read 5, iclass 36, count 0 2006.173.06:33:36.93#ibcon#read 5, iclass 36, count 0 2006.173.06:33:36.94#ibcon#about to read 6, iclass 36, count 0 2006.173.06:33:36.94#ibcon#read 6, iclass 36, count 0 2006.173.06:33:36.94#ibcon#end of sib2, iclass 36, count 0 2006.173.06:33:36.94#ibcon#*mode == 0, iclass 36, count 0 2006.173.06:33:36.94#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.06:33:36.94#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.06:33:36.94#ibcon#*before write, iclass 36, count 0 2006.173.06:33:36.94#ibcon#enter sib2, iclass 36, count 0 2006.173.06:33:36.94#ibcon#flushed, iclass 36, count 0 2006.173.06:33:36.94#ibcon#about to write, iclass 36, count 0 2006.173.06:33:36.94#ibcon#wrote, iclass 36, count 0 2006.173.06:33:36.94#ibcon#about to read 3, iclass 36, count 0 2006.173.06:33:36.97#ibcon#read 3, iclass 36, count 0 2006.173.06:33:36.97#ibcon#about to read 4, iclass 36, count 0 2006.173.06:33:36.97#ibcon#read 4, iclass 36, count 0 2006.173.06:33:36.98#ibcon#about to read 5, iclass 36, count 0 2006.173.06:33:36.98#ibcon#read 5, iclass 36, count 0 2006.173.06:33:36.98#ibcon#about to read 6, iclass 36, count 0 2006.173.06:33:36.98#ibcon#read 6, iclass 36, count 0 2006.173.06:33:36.98#ibcon#end of sib2, iclass 36, count 0 2006.173.06:33:36.98#ibcon#*after write, iclass 36, count 0 2006.173.06:33:36.98#ibcon#*before return 0, iclass 36, count 0 2006.173.06:33:36.98#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.06:33:36.98#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.06:33:36.98#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.06:33:36.98#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.06:33:36.98$vck44/va=6,3 2006.173.06:33:36.98#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.06:33:36.98#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.06:33:36.98#ibcon#ireg 11 cls_cnt 2 2006.173.06:33:36.98#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.06:33:37.03#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.06:33:37.03#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.06:33:37.03#ibcon#enter wrdev, iclass 38, count 2 2006.173.06:33:37.03#ibcon#first serial, iclass 38, count 2 2006.173.06:33:37.04#ibcon#enter sib2, iclass 38, count 2 2006.173.06:33:37.04#ibcon#flushed, iclass 38, count 2 2006.173.06:33:37.04#ibcon#about to write, iclass 38, count 2 2006.173.06:33:37.04#ibcon#wrote, iclass 38, count 2 2006.173.06:33:37.04#ibcon#about to read 3, iclass 38, count 2 2006.173.06:33:37.05#ibcon#read 3, iclass 38, count 2 2006.173.06:33:37.05#ibcon#about to read 4, iclass 38, count 2 2006.173.06:33:37.05#ibcon#read 4, iclass 38, count 2 2006.173.06:33:37.05#ibcon#about to read 5, iclass 38, count 2 2006.173.06:33:37.05#ibcon#read 5, iclass 38, count 2 2006.173.06:33:37.06#ibcon#about to read 6, iclass 38, count 2 2006.173.06:33:37.06#ibcon#read 6, iclass 38, count 2 2006.173.06:33:37.06#ibcon#end of sib2, iclass 38, count 2 2006.173.06:33:37.06#ibcon#*mode == 0, iclass 38, count 2 2006.173.06:33:37.06#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.06:33:37.06#ibcon#[25=AT06-03\r\n] 2006.173.06:33:37.06#ibcon#*before write, iclass 38, count 2 2006.173.06:33:37.06#ibcon#enter sib2, iclass 38, count 2 2006.173.06:33:37.06#ibcon#flushed, iclass 38, count 2 2006.173.06:33:37.06#ibcon#about to write, iclass 38, count 2 2006.173.06:33:37.06#ibcon#wrote, iclass 38, count 2 2006.173.06:33:37.06#ibcon#about to read 3, iclass 38, count 2 2006.173.06:33:37.08#ibcon#read 3, iclass 38, count 2 2006.173.06:33:37.08#ibcon#about to read 4, iclass 38, count 2 2006.173.06:33:37.09#ibcon#read 4, iclass 38, count 2 2006.173.06:33:37.09#ibcon#about to read 5, iclass 38, count 2 2006.173.06:33:37.09#ibcon#read 5, iclass 38, count 2 2006.173.06:33:37.09#ibcon#about to read 6, iclass 38, count 2 2006.173.06:33:37.09#ibcon#read 6, iclass 38, count 2 2006.173.06:33:37.09#ibcon#end of sib2, iclass 38, count 2 2006.173.06:33:37.09#ibcon#*after write, iclass 38, count 2 2006.173.06:33:37.09#ibcon#*before return 0, iclass 38, count 2 2006.173.06:33:37.09#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.06:33:37.09#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.06:33:37.09#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.06:33:37.09#ibcon#ireg 7 cls_cnt 0 2006.173.06:33:37.09#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.06:33:37.20#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.06:33:37.20#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.06:33:37.20#ibcon#enter wrdev, iclass 38, count 0 2006.173.06:33:37.21#ibcon#first serial, iclass 38, count 0 2006.173.06:33:37.21#ibcon#enter sib2, iclass 38, count 0 2006.173.06:33:37.21#ibcon#flushed, iclass 38, count 0 2006.173.06:33:37.21#ibcon#about to write, iclass 38, count 0 2006.173.06:33:37.21#ibcon#wrote, iclass 38, count 0 2006.173.06:33:37.21#ibcon#about to read 3, iclass 38, count 0 2006.173.06:33:37.22#ibcon#read 3, iclass 38, count 0 2006.173.06:33:37.22#ibcon#about to read 4, iclass 38, count 0 2006.173.06:33:37.22#ibcon#read 4, iclass 38, count 0 2006.173.06:33:37.22#ibcon#about to read 5, iclass 38, count 0 2006.173.06:33:37.22#ibcon#read 5, iclass 38, count 0 2006.173.06:33:37.23#ibcon#about to read 6, iclass 38, count 0 2006.173.06:33:37.23#ibcon#read 6, iclass 38, count 0 2006.173.06:33:37.23#ibcon#end of sib2, iclass 38, count 0 2006.173.06:33:37.23#ibcon#*mode == 0, iclass 38, count 0 2006.173.06:33:37.23#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.06:33:37.23#ibcon#[25=USB\r\n] 2006.173.06:33:37.23#ibcon#*before write, iclass 38, count 0 2006.173.06:33:37.23#ibcon#enter sib2, iclass 38, count 0 2006.173.06:33:37.23#ibcon#flushed, iclass 38, count 0 2006.173.06:33:37.23#ibcon#about to write, iclass 38, count 0 2006.173.06:33:37.23#ibcon#wrote, iclass 38, count 0 2006.173.06:33:37.23#ibcon#about to read 3, iclass 38, count 0 2006.173.06:33:37.25#ibcon#read 3, iclass 38, count 0 2006.173.06:33:37.25#ibcon#about to read 4, iclass 38, count 0 2006.173.06:33:37.25#ibcon#read 4, iclass 38, count 0 2006.173.06:33:37.25#ibcon#about to read 5, iclass 38, count 0 2006.173.06:33:37.26#ibcon#read 5, iclass 38, count 0 2006.173.06:33:37.26#ibcon#about to read 6, iclass 38, count 0 2006.173.06:33:37.26#ibcon#read 6, iclass 38, count 0 2006.173.06:33:37.26#ibcon#end of sib2, iclass 38, count 0 2006.173.06:33:37.26#ibcon#*after write, iclass 38, count 0 2006.173.06:33:37.26#ibcon#*before return 0, iclass 38, count 0 2006.173.06:33:37.26#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.06:33:37.26#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.06:33:37.26#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.06:33:37.26#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.06:33:37.26$vck44/valo=7,864.99 2006.173.06:33:37.26#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.06:33:37.26#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.06:33:37.26#ibcon#ireg 17 cls_cnt 0 2006.173.06:33:37.26#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.06:33:37.26#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.06:33:37.26#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.06:33:37.26#ibcon#enter wrdev, iclass 40, count 0 2006.173.06:33:37.26#ibcon#first serial, iclass 40, count 0 2006.173.06:33:37.26#ibcon#enter sib2, iclass 40, count 0 2006.173.06:33:37.26#ibcon#flushed, iclass 40, count 0 2006.173.06:33:37.26#ibcon#about to write, iclass 40, count 0 2006.173.06:33:37.26#ibcon#wrote, iclass 40, count 0 2006.173.06:33:37.26#ibcon#about to read 3, iclass 40, count 0 2006.173.06:33:37.27#ibcon#read 3, iclass 40, count 0 2006.173.06:33:37.27#ibcon#about to read 4, iclass 40, count 0 2006.173.06:33:37.28#ibcon#read 4, iclass 40, count 0 2006.173.06:33:37.28#ibcon#about to read 5, iclass 40, count 0 2006.173.06:33:37.28#ibcon#read 5, iclass 40, count 0 2006.173.06:33:37.28#ibcon#about to read 6, iclass 40, count 0 2006.173.06:33:37.28#ibcon#read 6, iclass 40, count 0 2006.173.06:33:37.28#ibcon#end of sib2, iclass 40, count 0 2006.173.06:33:37.28#ibcon#*mode == 0, iclass 40, count 0 2006.173.06:33:37.28#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.06:33:37.28#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.06:33:37.28#ibcon#*before write, iclass 40, count 0 2006.173.06:33:37.28#ibcon#enter sib2, iclass 40, count 0 2006.173.06:33:37.28#ibcon#flushed, iclass 40, count 0 2006.173.06:33:37.28#ibcon#about to write, iclass 40, count 0 2006.173.06:33:37.28#ibcon#wrote, iclass 40, count 0 2006.173.06:33:37.28#ibcon#about to read 3, iclass 40, count 0 2006.173.06:33:37.31#ibcon#read 3, iclass 40, count 0 2006.173.06:33:37.32#ibcon#about to read 4, iclass 40, count 0 2006.173.06:33:37.32#ibcon#read 4, iclass 40, count 0 2006.173.06:33:37.32#ibcon#about to read 5, iclass 40, count 0 2006.173.06:33:37.32#ibcon#read 5, iclass 40, count 0 2006.173.06:33:37.32#ibcon#about to read 6, iclass 40, count 0 2006.173.06:33:37.32#ibcon#read 6, iclass 40, count 0 2006.173.06:33:37.32#ibcon#end of sib2, iclass 40, count 0 2006.173.06:33:37.32#ibcon#*after write, iclass 40, count 0 2006.173.06:33:37.32#ibcon#*before return 0, iclass 40, count 0 2006.173.06:33:37.32#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.06:33:37.32#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.06:33:37.32#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.06:33:37.32#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.06:33:37.32$vck44/va=7,4 2006.173.06:33:37.32#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.06:33:37.32#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.06:33:37.32#ibcon#ireg 11 cls_cnt 2 2006.173.06:33:37.32#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.06:33:37.37#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.06:33:37.37#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.06:33:37.37#ibcon#enter wrdev, iclass 4, count 2 2006.173.06:33:37.38#ibcon#first serial, iclass 4, count 2 2006.173.06:33:37.38#ibcon#enter sib2, iclass 4, count 2 2006.173.06:33:37.38#ibcon#flushed, iclass 4, count 2 2006.173.06:33:37.38#ibcon#about to write, iclass 4, count 2 2006.173.06:33:37.38#ibcon#wrote, iclass 4, count 2 2006.173.06:33:37.38#ibcon#about to read 3, iclass 4, count 2 2006.173.06:33:37.39#ibcon#read 3, iclass 4, count 2 2006.173.06:33:37.39#ibcon#about to read 4, iclass 4, count 2 2006.173.06:33:37.39#ibcon#read 4, iclass 4, count 2 2006.173.06:33:37.39#ibcon#about to read 5, iclass 4, count 2 2006.173.06:33:37.40#ibcon#read 5, iclass 4, count 2 2006.173.06:33:37.40#ibcon#about to read 6, iclass 4, count 2 2006.173.06:33:37.40#ibcon#read 6, iclass 4, count 2 2006.173.06:33:37.40#ibcon#end of sib2, iclass 4, count 2 2006.173.06:33:37.40#ibcon#*mode == 0, iclass 4, count 2 2006.173.06:33:37.40#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.06:33:37.40#ibcon#[25=AT07-04\r\n] 2006.173.06:33:37.40#ibcon#*before write, iclass 4, count 2 2006.173.06:33:37.40#ibcon#enter sib2, iclass 4, count 2 2006.173.06:33:37.40#ibcon#flushed, iclass 4, count 2 2006.173.06:33:37.40#ibcon#about to write, iclass 4, count 2 2006.173.06:33:37.40#ibcon#wrote, iclass 4, count 2 2006.173.06:33:37.40#ibcon#about to read 3, iclass 4, count 2 2006.173.06:33:37.42#ibcon#read 3, iclass 4, count 2 2006.173.06:33:37.42#ibcon#about to read 4, iclass 4, count 2 2006.173.06:33:37.43#ibcon#read 4, iclass 4, count 2 2006.173.06:33:37.43#ibcon#about to read 5, iclass 4, count 2 2006.173.06:33:37.43#ibcon#read 5, iclass 4, count 2 2006.173.06:33:37.43#ibcon#about to read 6, iclass 4, count 2 2006.173.06:33:37.43#ibcon#read 6, iclass 4, count 2 2006.173.06:33:37.43#ibcon#end of sib2, iclass 4, count 2 2006.173.06:33:37.43#ibcon#*after write, iclass 4, count 2 2006.173.06:33:37.43#ibcon#*before return 0, iclass 4, count 2 2006.173.06:33:37.43#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.06:33:37.43#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.06:33:37.43#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.06:33:37.43#ibcon#ireg 7 cls_cnt 0 2006.173.06:33:37.43#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.06:33:37.54#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.06:33:37.54#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.06:33:37.54#ibcon#enter wrdev, iclass 4, count 0 2006.173.06:33:37.55#ibcon#first serial, iclass 4, count 0 2006.173.06:33:37.55#ibcon#enter sib2, iclass 4, count 0 2006.173.06:33:37.55#ibcon#flushed, iclass 4, count 0 2006.173.06:33:37.55#ibcon#about to write, iclass 4, count 0 2006.173.06:33:37.55#ibcon#wrote, iclass 4, count 0 2006.173.06:33:37.55#ibcon#about to read 3, iclass 4, count 0 2006.173.06:33:37.56#ibcon#read 3, iclass 4, count 0 2006.173.06:33:37.56#ibcon#about to read 4, iclass 4, count 0 2006.173.06:33:37.57#ibcon#read 4, iclass 4, count 0 2006.173.06:33:37.57#ibcon#about to read 5, iclass 4, count 0 2006.173.06:33:37.57#ibcon#read 5, iclass 4, count 0 2006.173.06:33:37.57#ibcon#about to read 6, iclass 4, count 0 2006.173.06:33:37.57#ibcon#read 6, iclass 4, count 0 2006.173.06:33:37.57#ibcon#end of sib2, iclass 4, count 0 2006.173.06:33:37.57#ibcon#*mode == 0, iclass 4, count 0 2006.173.06:33:37.57#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.06:33:37.57#ibcon#[25=USB\r\n] 2006.173.06:33:37.57#ibcon#*before write, iclass 4, count 0 2006.173.06:33:37.57#ibcon#enter sib2, iclass 4, count 0 2006.173.06:33:37.57#ibcon#flushed, iclass 4, count 0 2006.173.06:33:37.57#ibcon#about to write, iclass 4, count 0 2006.173.06:33:37.57#ibcon#wrote, iclass 4, count 0 2006.173.06:33:37.57#ibcon#about to read 3, iclass 4, count 0 2006.173.06:33:37.59#ibcon#read 3, iclass 4, count 0 2006.173.06:33:37.59#ibcon#about to read 4, iclass 4, count 0 2006.173.06:33:37.60#ibcon#read 4, iclass 4, count 0 2006.173.06:33:37.60#ibcon#about to read 5, iclass 4, count 0 2006.173.06:33:37.60#ibcon#read 5, iclass 4, count 0 2006.173.06:33:37.60#ibcon#about to read 6, iclass 4, count 0 2006.173.06:33:37.60#ibcon#read 6, iclass 4, count 0 2006.173.06:33:37.60#ibcon#end of sib2, iclass 4, count 0 2006.173.06:33:37.60#ibcon#*after write, iclass 4, count 0 2006.173.06:33:37.60#ibcon#*before return 0, iclass 4, count 0 2006.173.06:33:37.60#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.06:33:37.60#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.06:33:37.60#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.06:33:37.60#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.06:33:37.60$vck44/valo=8,884.99 2006.173.06:33:37.60#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.06:33:37.60#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.06:33:37.60#ibcon#ireg 17 cls_cnt 0 2006.173.06:33:37.60#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.06:33:37.60#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.06:33:37.60#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.06:33:37.60#ibcon#enter wrdev, iclass 6, count 0 2006.173.06:33:37.60#ibcon#first serial, iclass 6, count 0 2006.173.06:33:37.60#ibcon#enter sib2, iclass 6, count 0 2006.173.06:33:37.60#ibcon#flushed, iclass 6, count 0 2006.173.06:33:37.60#ibcon#about to write, iclass 6, count 0 2006.173.06:33:37.60#ibcon#wrote, iclass 6, count 0 2006.173.06:33:37.60#ibcon#about to read 3, iclass 6, count 0 2006.173.06:33:37.61#ibcon#read 3, iclass 6, count 0 2006.173.06:33:37.62#ibcon#about to read 4, iclass 6, count 0 2006.173.06:33:37.62#ibcon#read 4, iclass 6, count 0 2006.173.06:33:37.62#ibcon#about to read 5, iclass 6, count 0 2006.173.06:33:37.62#ibcon#read 5, iclass 6, count 0 2006.173.06:33:37.62#ibcon#about to read 6, iclass 6, count 0 2006.173.06:33:37.62#ibcon#read 6, iclass 6, count 0 2006.173.06:33:37.62#ibcon#end of sib2, iclass 6, count 0 2006.173.06:33:37.62#ibcon#*mode == 0, iclass 6, count 0 2006.173.06:33:37.62#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.06:33:37.62#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.06:33:37.62#ibcon#*before write, iclass 6, count 0 2006.173.06:33:37.62#ibcon#enter sib2, iclass 6, count 0 2006.173.06:33:37.62#ibcon#flushed, iclass 6, count 0 2006.173.06:33:37.62#ibcon#about to write, iclass 6, count 0 2006.173.06:33:37.62#ibcon#wrote, iclass 6, count 0 2006.173.06:33:37.62#ibcon#about to read 3, iclass 6, count 0 2006.173.06:33:37.65#ibcon#read 3, iclass 6, count 0 2006.173.06:33:37.65#ibcon#about to read 4, iclass 6, count 0 2006.173.06:33:37.66#ibcon#read 4, iclass 6, count 0 2006.173.06:33:37.66#ibcon#about to read 5, iclass 6, count 0 2006.173.06:33:37.66#ibcon#read 5, iclass 6, count 0 2006.173.06:33:37.66#ibcon#about to read 6, iclass 6, count 0 2006.173.06:33:37.66#ibcon#read 6, iclass 6, count 0 2006.173.06:33:37.66#ibcon#end of sib2, iclass 6, count 0 2006.173.06:33:37.66#ibcon#*after write, iclass 6, count 0 2006.173.06:33:37.66#ibcon#*before return 0, iclass 6, count 0 2006.173.06:33:37.66#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.06:33:37.66#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.06:33:37.66#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.06:33:37.66#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.06:33:37.66$vck44/va=8,4 2006.173.06:33:37.66#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.06:33:37.66#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.06:33:37.66#ibcon#ireg 11 cls_cnt 2 2006.173.06:33:37.66#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.06:33:37.71#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.06:33:37.71#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.06:33:37.71#ibcon#enter wrdev, iclass 10, count 2 2006.173.06:33:37.72#ibcon#first serial, iclass 10, count 2 2006.173.06:33:37.72#ibcon#enter sib2, iclass 10, count 2 2006.173.06:33:37.72#ibcon#flushed, iclass 10, count 2 2006.173.06:33:37.72#ibcon#about to write, iclass 10, count 2 2006.173.06:33:37.72#ibcon#wrote, iclass 10, count 2 2006.173.06:33:37.72#ibcon#about to read 3, iclass 10, count 2 2006.173.06:33:37.73#ibcon#read 3, iclass 10, count 2 2006.173.06:33:37.73#ibcon#about to read 4, iclass 10, count 2 2006.173.06:33:37.73#ibcon#read 4, iclass 10, count 2 2006.173.06:33:37.74#ibcon#about to read 5, iclass 10, count 2 2006.173.06:33:37.74#ibcon#read 5, iclass 10, count 2 2006.173.06:33:37.74#ibcon#about to read 6, iclass 10, count 2 2006.173.06:33:37.74#ibcon#read 6, iclass 10, count 2 2006.173.06:33:37.74#ibcon#end of sib2, iclass 10, count 2 2006.173.06:33:37.74#ibcon#*mode == 0, iclass 10, count 2 2006.173.06:33:37.74#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.06:33:37.74#ibcon#[25=AT08-04\r\n] 2006.173.06:33:37.74#ibcon#*before write, iclass 10, count 2 2006.173.06:33:37.74#ibcon#enter sib2, iclass 10, count 2 2006.173.06:33:37.74#ibcon#flushed, iclass 10, count 2 2006.173.06:33:37.74#ibcon#about to write, iclass 10, count 2 2006.173.06:33:37.74#ibcon#wrote, iclass 10, count 2 2006.173.06:33:37.74#ibcon#about to read 3, iclass 10, count 2 2006.173.06:33:37.76#ibcon#read 3, iclass 10, count 2 2006.173.06:33:37.76#ibcon#about to read 4, iclass 10, count 2 2006.173.06:33:37.77#ibcon#read 4, iclass 10, count 2 2006.173.06:33:37.77#ibcon#about to read 5, iclass 10, count 2 2006.173.06:33:37.77#ibcon#read 5, iclass 10, count 2 2006.173.06:33:37.77#ibcon#about to read 6, iclass 10, count 2 2006.173.06:33:37.77#ibcon#read 6, iclass 10, count 2 2006.173.06:33:37.77#ibcon#end of sib2, iclass 10, count 2 2006.173.06:33:37.77#ibcon#*after write, iclass 10, count 2 2006.173.06:33:37.77#ibcon#*before return 0, iclass 10, count 2 2006.173.06:33:37.77#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.06:33:37.77#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.06:33:37.77#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.06:33:37.77#ibcon#ireg 7 cls_cnt 0 2006.173.06:33:37.77#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.06:33:37.88#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.06:33:37.88#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.06:33:37.88#ibcon#enter wrdev, iclass 10, count 0 2006.173.06:33:37.89#ibcon#first serial, iclass 10, count 0 2006.173.06:33:37.89#ibcon#enter sib2, iclass 10, count 0 2006.173.06:33:37.89#ibcon#flushed, iclass 10, count 0 2006.173.06:33:37.89#ibcon#about to write, iclass 10, count 0 2006.173.06:33:37.89#ibcon#wrote, iclass 10, count 0 2006.173.06:33:37.89#ibcon#about to read 3, iclass 10, count 0 2006.173.06:33:37.90#ibcon#read 3, iclass 10, count 0 2006.173.06:33:37.90#ibcon#about to read 4, iclass 10, count 0 2006.173.06:33:37.91#ibcon#read 4, iclass 10, count 0 2006.173.06:33:37.91#ibcon#about to read 5, iclass 10, count 0 2006.173.06:33:37.91#ibcon#read 5, iclass 10, count 0 2006.173.06:33:37.91#ibcon#about to read 6, iclass 10, count 0 2006.173.06:33:37.91#ibcon#read 6, iclass 10, count 0 2006.173.06:33:37.91#ibcon#end of sib2, iclass 10, count 0 2006.173.06:33:37.91#ibcon#*mode == 0, iclass 10, count 0 2006.173.06:33:37.91#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.06:33:37.91#ibcon#[25=USB\r\n] 2006.173.06:33:37.91#ibcon#*before write, iclass 10, count 0 2006.173.06:33:37.91#ibcon#enter sib2, iclass 10, count 0 2006.173.06:33:37.91#ibcon#flushed, iclass 10, count 0 2006.173.06:33:37.91#ibcon#about to write, iclass 10, count 0 2006.173.06:33:37.91#ibcon#wrote, iclass 10, count 0 2006.173.06:33:37.91#ibcon#about to read 3, iclass 10, count 0 2006.173.06:33:37.93#ibcon#read 3, iclass 10, count 0 2006.173.06:33:37.93#ibcon#about to read 4, iclass 10, count 0 2006.173.06:33:37.94#ibcon#read 4, iclass 10, count 0 2006.173.06:33:37.94#ibcon#about to read 5, iclass 10, count 0 2006.173.06:33:37.94#ibcon#read 5, iclass 10, count 0 2006.173.06:33:37.94#ibcon#about to read 6, iclass 10, count 0 2006.173.06:33:37.94#ibcon#read 6, iclass 10, count 0 2006.173.06:33:37.94#ibcon#end of sib2, iclass 10, count 0 2006.173.06:33:37.94#ibcon#*after write, iclass 10, count 0 2006.173.06:33:37.94#ibcon#*before return 0, iclass 10, count 0 2006.173.06:33:37.94#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.06:33:37.94#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.06:33:37.94#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.06:33:37.94#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.06:33:37.94$vck44/vblo=1,629.99 2006.173.06:33:37.94#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.06:33:37.94#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.06:33:37.94#ibcon#ireg 17 cls_cnt 0 2006.173.06:33:37.94#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.06:33:37.94#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.06:33:37.94#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.06:33:37.94#ibcon#enter wrdev, iclass 12, count 0 2006.173.06:33:37.94#ibcon#first serial, iclass 12, count 0 2006.173.06:33:37.94#ibcon#enter sib2, iclass 12, count 0 2006.173.06:33:37.94#ibcon#flushed, iclass 12, count 0 2006.173.06:33:37.94#ibcon#about to write, iclass 12, count 0 2006.173.06:33:37.94#ibcon#wrote, iclass 12, count 0 2006.173.06:33:37.94#ibcon#about to read 3, iclass 12, count 0 2006.173.06:33:37.95#ibcon#read 3, iclass 12, count 0 2006.173.06:33:37.95#ibcon#about to read 4, iclass 12, count 0 2006.173.06:33:37.95#ibcon#read 4, iclass 12, count 0 2006.173.06:33:37.95#ibcon#about to read 5, iclass 12, count 0 2006.173.06:33:37.95#ibcon#read 5, iclass 12, count 0 2006.173.06:33:37.95#ibcon#about to read 6, iclass 12, count 0 2006.173.06:33:37.96#ibcon#read 6, iclass 12, count 0 2006.173.06:33:37.96#ibcon#end of sib2, iclass 12, count 0 2006.173.06:33:37.96#ibcon#*mode == 0, iclass 12, count 0 2006.173.06:33:37.96#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.06:33:37.96#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.06:33:37.96#ibcon#*before write, iclass 12, count 0 2006.173.06:33:37.96#ibcon#enter sib2, iclass 12, count 0 2006.173.06:33:37.96#ibcon#flushed, iclass 12, count 0 2006.173.06:33:37.96#ibcon#about to write, iclass 12, count 0 2006.173.06:33:37.96#ibcon#wrote, iclass 12, count 0 2006.173.06:33:37.96#ibcon#about to read 3, iclass 12, count 0 2006.173.06:33:37.99#ibcon#read 3, iclass 12, count 0 2006.173.06:33:37.99#ibcon#about to read 4, iclass 12, count 0 2006.173.06:33:38.00#ibcon#read 4, iclass 12, count 0 2006.173.06:33:38.00#ibcon#about to read 5, iclass 12, count 0 2006.173.06:33:38.00#ibcon#read 5, iclass 12, count 0 2006.173.06:33:38.00#ibcon#about to read 6, iclass 12, count 0 2006.173.06:33:38.00#ibcon#read 6, iclass 12, count 0 2006.173.06:33:38.00#ibcon#end of sib2, iclass 12, count 0 2006.173.06:33:38.00#ibcon#*after write, iclass 12, count 0 2006.173.06:33:38.00#ibcon#*before return 0, iclass 12, count 0 2006.173.06:33:38.00#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.06:33:38.00#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.06:33:38.00#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.06:33:38.00#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.06:33:38.00$vck44/vb=1,4 2006.173.06:33:38.00#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.06:33:38.00#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.06:33:38.00#ibcon#ireg 11 cls_cnt 2 2006.173.06:33:38.00#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.06:33:38.00#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.06:33:38.00#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.06:33:38.00#ibcon#enter wrdev, iclass 14, count 2 2006.173.06:33:38.00#ibcon#first serial, iclass 14, count 2 2006.173.06:33:38.00#ibcon#enter sib2, iclass 14, count 2 2006.173.06:33:38.00#ibcon#flushed, iclass 14, count 2 2006.173.06:33:38.00#ibcon#about to write, iclass 14, count 2 2006.173.06:33:38.00#ibcon#wrote, iclass 14, count 2 2006.173.06:33:38.00#ibcon#about to read 3, iclass 14, count 2 2006.173.06:33:38.01#ibcon#read 3, iclass 14, count 2 2006.173.06:33:38.01#ibcon#about to read 4, iclass 14, count 2 2006.173.06:33:38.02#ibcon#read 4, iclass 14, count 2 2006.173.06:33:38.02#ibcon#about to read 5, iclass 14, count 2 2006.173.06:33:38.02#ibcon#read 5, iclass 14, count 2 2006.173.06:33:38.02#ibcon#about to read 6, iclass 14, count 2 2006.173.06:33:38.02#ibcon#read 6, iclass 14, count 2 2006.173.06:33:38.02#ibcon#end of sib2, iclass 14, count 2 2006.173.06:33:38.02#ibcon#*mode == 0, iclass 14, count 2 2006.173.06:33:38.02#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.06:33:38.02#ibcon#[27=AT01-04\r\n] 2006.173.06:33:38.02#ibcon#*before write, iclass 14, count 2 2006.173.06:33:38.02#ibcon#enter sib2, iclass 14, count 2 2006.173.06:33:38.02#ibcon#flushed, iclass 14, count 2 2006.173.06:33:38.02#ibcon#about to write, iclass 14, count 2 2006.173.06:33:38.02#ibcon#wrote, iclass 14, count 2 2006.173.06:33:38.02#ibcon#about to read 3, iclass 14, count 2 2006.173.06:33:38.04#ibcon#read 3, iclass 14, count 2 2006.173.06:33:38.04#ibcon#about to read 4, iclass 14, count 2 2006.173.06:33:38.04#ibcon#read 4, iclass 14, count 2 2006.173.06:33:38.04#ibcon#about to read 5, iclass 14, count 2 2006.173.06:33:38.05#ibcon#read 5, iclass 14, count 2 2006.173.06:33:38.05#ibcon#about to read 6, iclass 14, count 2 2006.173.06:33:38.05#ibcon#read 6, iclass 14, count 2 2006.173.06:33:38.05#ibcon#end of sib2, iclass 14, count 2 2006.173.06:33:38.05#ibcon#*after write, iclass 14, count 2 2006.173.06:33:38.05#ibcon#*before return 0, iclass 14, count 2 2006.173.06:33:38.05#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.06:33:38.05#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.06:33:38.05#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.06:33:38.05#ibcon#ireg 7 cls_cnt 0 2006.173.06:33:38.05#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.06:33:38.16#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.06:33:38.16#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.06:33:38.16#ibcon#enter wrdev, iclass 14, count 0 2006.173.06:33:38.16#ibcon#first serial, iclass 14, count 0 2006.173.06:33:38.17#ibcon#enter sib2, iclass 14, count 0 2006.173.06:33:38.17#ibcon#flushed, iclass 14, count 0 2006.173.06:33:38.17#ibcon#about to write, iclass 14, count 0 2006.173.06:33:38.17#ibcon#wrote, iclass 14, count 0 2006.173.06:33:38.17#ibcon#about to read 3, iclass 14, count 0 2006.173.06:33:38.18#ibcon#read 3, iclass 14, count 0 2006.173.06:33:38.18#ibcon#about to read 4, iclass 14, count 0 2006.173.06:33:38.18#ibcon#read 4, iclass 14, count 0 2006.173.06:33:38.18#ibcon#about to read 5, iclass 14, count 0 2006.173.06:33:38.18#ibcon#read 5, iclass 14, count 0 2006.173.06:33:38.19#ibcon#about to read 6, iclass 14, count 0 2006.173.06:33:38.19#ibcon#read 6, iclass 14, count 0 2006.173.06:33:38.19#ibcon#end of sib2, iclass 14, count 0 2006.173.06:33:38.19#ibcon#*mode == 0, iclass 14, count 0 2006.173.06:33:38.19#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.06:33:38.19#ibcon#[27=USB\r\n] 2006.173.06:33:38.19#ibcon#*before write, iclass 14, count 0 2006.173.06:33:38.19#ibcon#enter sib2, iclass 14, count 0 2006.173.06:33:38.19#ibcon#flushed, iclass 14, count 0 2006.173.06:33:38.19#ibcon#about to write, iclass 14, count 0 2006.173.06:33:38.19#ibcon#wrote, iclass 14, count 0 2006.173.06:33:38.19#ibcon#about to read 3, iclass 14, count 0 2006.173.06:33:38.21#ibcon#read 3, iclass 14, count 0 2006.173.06:33:38.21#ibcon#about to read 4, iclass 14, count 0 2006.173.06:33:38.22#ibcon#read 4, iclass 14, count 0 2006.173.06:33:38.22#ibcon#about to read 5, iclass 14, count 0 2006.173.06:33:38.22#ibcon#read 5, iclass 14, count 0 2006.173.06:33:38.22#ibcon#about to read 6, iclass 14, count 0 2006.173.06:33:38.22#ibcon#read 6, iclass 14, count 0 2006.173.06:33:38.22#ibcon#end of sib2, iclass 14, count 0 2006.173.06:33:38.22#ibcon#*after write, iclass 14, count 0 2006.173.06:33:38.22#ibcon#*before return 0, iclass 14, count 0 2006.173.06:33:38.22#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.06:33:38.22#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.06:33:38.22#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.06:33:38.22#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.06:33:38.22$vck44/vblo=2,634.99 2006.173.06:33:38.22#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.06:33:38.22#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.06:33:38.22#ibcon#ireg 17 cls_cnt 0 2006.173.06:33:38.22#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.06:33:38.22#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.06:33:38.22#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.06:33:38.22#ibcon#enter wrdev, iclass 16, count 0 2006.173.06:33:38.22#ibcon#first serial, iclass 16, count 0 2006.173.06:33:38.22#ibcon#enter sib2, iclass 16, count 0 2006.173.06:33:38.22#ibcon#flushed, iclass 16, count 0 2006.173.06:33:38.22#ibcon#about to write, iclass 16, count 0 2006.173.06:33:38.22#ibcon#wrote, iclass 16, count 0 2006.173.06:33:38.22#ibcon#about to read 3, iclass 16, count 0 2006.173.06:33:38.23#ibcon#read 3, iclass 16, count 0 2006.173.06:33:38.23#ibcon#about to read 4, iclass 16, count 0 2006.173.06:33:38.23#ibcon#read 4, iclass 16, count 0 2006.173.06:33:38.23#ibcon#about to read 5, iclass 16, count 0 2006.173.06:33:38.24#ibcon#read 5, iclass 16, count 0 2006.173.06:33:38.24#ibcon#about to read 6, iclass 16, count 0 2006.173.06:33:38.24#ibcon#read 6, iclass 16, count 0 2006.173.06:33:38.24#ibcon#end of sib2, iclass 16, count 0 2006.173.06:33:38.24#ibcon#*mode == 0, iclass 16, count 0 2006.173.06:33:38.24#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.06:33:38.24#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.06:33:38.24#ibcon#*before write, iclass 16, count 0 2006.173.06:33:38.24#ibcon#enter sib2, iclass 16, count 0 2006.173.06:33:38.24#ibcon#flushed, iclass 16, count 0 2006.173.06:33:38.24#ibcon#about to write, iclass 16, count 0 2006.173.06:33:38.24#ibcon#wrote, iclass 16, count 0 2006.173.06:33:38.24#ibcon#about to read 3, iclass 16, count 0 2006.173.06:33:38.27#ibcon#read 3, iclass 16, count 0 2006.173.06:33:38.27#ibcon#about to read 4, iclass 16, count 0 2006.173.06:33:38.28#ibcon#read 4, iclass 16, count 0 2006.173.06:33:38.28#ibcon#about to read 5, iclass 16, count 0 2006.173.06:33:38.28#ibcon#read 5, iclass 16, count 0 2006.173.06:33:38.28#ibcon#about to read 6, iclass 16, count 0 2006.173.06:33:38.28#ibcon#read 6, iclass 16, count 0 2006.173.06:33:38.28#ibcon#end of sib2, iclass 16, count 0 2006.173.06:33:38.28#ibcon#*after write, iclass 16, count 0 2006.173.06:33:38.28#ibcon#*before return 0, iclass 16, count 0 2006.173.06:33:38.28#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.06:33:38.28#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.06:33:38.28#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.06:33:38.28#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.06:33:38.28$vck44/vb=2,4 2006.173.06:33:38.28#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.06:33:38.28#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.06:33:38.28#ibcon#ireg 11 cls_cnt 2 2006.173.06:33:38.28#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.06:33:38.33#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.06:33:38.33#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.06:33:38.33#ibcon#enter wrdev, iclass 18, count 2 2006.173.06:33:38.33#ibcon#first serial, iclass 18, count 2 2006.173.06:33:38.34#ibcon#enter sib2, iclass 18, count 2 2006.173.06:33:38.34#ibcon#flushed, iclass 18, count 2 2006.173.06:33:38.34#ibcon#about to write, iclass 18, count 2 2006.173.06:33:38.34#ibcon#wrote, iclass 18, count 2 2006.173.06:33:38.34#ibcon#about to read 3, iclass 18, count 2 2006.173.06:33:38.35#ibcon#read 3, iclass 18, count 2 2006.173.06:33:38.35#ibcon#about to read 4, iclass 18, count 2 2006.173.06:33:38.35#ibcon#read 4, iclass 18, count 2 2006.173.06:33:38.35#ibcon#about to read 5, iclass 18, count 2 2006.173.06:33:38.35#ibcon#read 5, iclass 18, count 2 2006.173.06:33:38.36#ibcon#about to read 6, iclass 18, count 2 2006.173.06:33:38.36#ibcon#read 6, iclass 18, count 2 2006.173.06:33:38.36#ibcon#end of sib2, iclass 18, count 2 2006.173.06:33:38.36#ibcon#*mode == 0, iclass 18, count 2 2006.173.06:33:38.36#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.06:33:38.36#ibcon#[27=AT02-04\r\n] 2006.173.06:33:38.36#ibcon#*before write, iclass 18, count 2 2006.173.06:33:38.36#ibcon#enter sib2, iclass 18, count 2 2006.173.06:33:38.36#ibcon#flushed, iclass 18, count 2 2006.173.06:33:38.36#ibcon#about to write, iclass 18, count 2 2006.173.06:33:38.36#ibcon#wrote, iclass 18, count 2 2006.173.06:33:38.36#ibcon#about to read 3, iclass 18, count 2 2006.173.06:33:38.38#ibcon#read 3, iclass 18, count 2 2006.173.06:33:38.38#ibcon#about to read 4, iclass 18, count 2 2006.173.06:33:38.39#ibcon#read 4, iclass 18, count 2 2006.173.06:33:38.39#ibcon#about to read 5, iclass 18, count 2 2006.173.06:33:38.39#ibcon#read 5, iclass 18, count 2 2006.173.06:33:38.39#ibcon#about to read 6, iclass 18, count 2 2006.173.06:33:38.39#ibcon#read 6, iclass 18, count 2 2006.173.06:33:38.39#ibcon#end of sib2, iclass 18, count 2 2006.173.06:33:38.39#ibcon#*after write, iclass 18, count 2 2006.173.06:33:38.39#ibcon#*before return 0, iclass 18, count 2 2006.173.06:33:38.39#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.06:33:38.39#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.06:33:38.39#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.06:33:38.39#ibcon#ireg 7 cls_cnt 0 2006.173.06:33:38.39#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.06:33:38.50#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.06:33:38.50#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.06:33:38.50#ibcon#enter wrdev, iclass 18, count 0 2006.173.06:33:38.51#ibcon#first serial, iclass 18, count 0 2006.173.06:33:38.51#ibcon#enter sib2, iclass 18, count 0 2006.173.06:33:38.51#ibcon#flushed, iclass 18, count 0 2006.173.06:33:38.51#ibcon#about to write, iclass 18, count 0 2006.173.06:33:38.51#ibcon#wrote, iclass 18, count 0 2006.173.06:33:38.51#ibcon#about to read 3, iclass 18, count 0 2006.173.06:33:38.52#ibcon#read 3, iclass 18, count 0 2006.173.06:33:38.53#ibcon#about to read 4, iclass 18, count 0 2006.173.06:33:38.53#ibcon#read 4, iclass 18, count 0 2006.173.06:33:38.53#ibcon#about to read 5, iclass 18, count 0 2006.173.06:33:38.53#ibcon#read 5, iclass 18, count 0 2006.173.06:33:38.53#ibcon#about to read 6, iclass 18, count 0 2006.173.06:33:38.53#ibcon#read 6, iclass 18, count 0 2006.173.06:33:38.53#ibcon#end of sib2, iclass 18, count 0 2006.173.06:33:38.53#ibcon#*mode == 0, iclass 18, count 0 2006.173.06:33:38.53#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.06:33:38.53#ibcon#[27=USB\r\n] 2006.173.06:33:38.53#ibcon#*before write, iclass 18, count 0 2006.173.06:33:38.53#ibcon#enter sib2, iclass 18, count 0 2006.173.06:33:38.53#ibcon#flushed, iclass 18, count 0 2006.173.06:33:38.53#ibcon#about to write, iclass 18, count 0 2006.173.06:33:38.53#ibcon#wrote, iclass 18, count 0 2006.173.06:33:38.53#ibcon#about to read 3, iclass 18, count 0 2006.173.06:33:38.55#ibcon#read 3, iclass 18, count 0 2006.173.06:33:38.56#ibcon#about to read 4, iclass 18, count 0 2006.173.06:33:38.56#ibcon#read 4, iclass 18, count 0 2006.173.06:33:38.56#ibcon#about to read 5, iclass 18, count 0 2006.173.06:33:38.56#ibcon#read 5, iclass 18, count 0 2006.173.06:33:38.56#ibcon#about to read 6, iclass 18, count 0 2006.173.06:33:38.56#ibcon#read 6, iclass 18, count 0 2006.173.06:33:38.56#ibcon#end of sib2, iclass 18, count 0 2006.173.06:33:38.56#ibcon#*after write, iclass 18, count 0 2006.173.06:33:38.56#ibcon#*before return 0, iclass 18, count 0 2006.173.06:33:38.56#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.06:33:38.56#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.06:33:38.56#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.06:33:38.56#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.06:33:38.56$vck44/vblo=3,649.99 2006.173.06:33:38.56#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.06:33:38.56#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.06:33:38.56#ibcon#ireg 17 cls_cnt 0 2006.173.06:33:38.56#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.06:33:38.56#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.06:33:38.56#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.06:33:38.56#ibcon#enter wrdev, iclass 20, count 0 2006.173.06:33:38.56#ibcon#first serial, iclass 20, count 0 2006.173.06:33:38.56#ibcon#enter sib2, iclass 20, count 0 2006.173.06:33:38.56#ibcon#flushed, iclass 20, count 0 2006.173.06:33:38.56#ibcon#about to write, iclass 20, count 0 2006.173.06:33:38.56#ibcon#wrote, iclass 20, count 0 2006.173.06:33:38.56#ibcon#about to read 3, iclass 20, count 0 2006.173.06:33:38.57#ibcon#read 3, iclass 20, count 0 2006.173.06:33:38.58#ibcon#about to read 4, iclass 20, count 0 2006.173.06:33:38.58#ibcon#read 4, iclass 20, count 0 2006.173.06:33:38.58#ibcon#about to read 5, iclass 20, count 0 2006.173.06:33:38.58#ibcon#read 5, iclass 20, count 0 2006.173.06:33:38.58#ibcon#about to read 6, iclass 20, count 0 2006.173.06:33:38.58#ibcon#read 6, iclass 20, count 0 2006.173.06:33:38.58#ibcon#end of sib2, iclass 20, count 0 2006.173.06:33:38.58#ibcon#*mode == 0, iclass 20, count 0 2006.173.06:33:38.58#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.06:33:38.58#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.06:33:38.58#ibcon#*before write, iclass 20, count 0 2006.173.06:33:38.58#ibcon#enter sib2, iclass 20, count 0 2006.173.06:33:38.58#ibcon#flushed, iclass 20, count 0 2006.173.06:33:38.58#ibcon#about to write, iclass 20, count 0 2006.173.06:33:38.58#ibcon#wrote, iclass 20, count 0 2006.173.06:33:38.58#ibcon#about to read 3, iclass 20, count 0 2006.173.06:33:38.61#ibcon#read 3, iclass 20, count 0 2006.173.06:33:38.62#ibcon#about to read 4, iclass 20, count 0 2006.173.06:33:38.62#ibcon#read 4, iclass 20, count 0 2006.173.06:33:38.62#ibcon#about to read 5, iclass 20, count 0 2006.173.06:33:38.62#ibcon#read 5, iclass 20, count 0 2006.173.06:33:38.62#ibcon#about to read 6, iclass 20, count 0 2006.173.06:33:38.62#ibcon#read 6, iclass 20, count 0 2006.173.06:33:38.62#ibcon#end of sib2, iclass 20, count 0 2006.173.06:33:38.62#ibcon#*after write, iclass 20, count 0 2006.173.06:33:38.62#ibcon#*before return 0, iclass 20, count 0 2006.173.06:33:38.62#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.06:33:38.62#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.06:33:38.62#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.06:33:38.62#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.06:33:38.62$vck44/vb=3,4 2006.173.06:33:38.62#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.06:33:38.62#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.06:33:38.62#ibcon#ireg 11 cls_cnt 2 2006.173.06:33:38.62#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.06:33:38.67#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.06:33:38.67#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.06:33:38.67#ibcon#enter wrdev, iclass 22, count 2 2006.173.06:33:38.68#ibcon#first serial, iclass 22, count 2 2006.173.06:33:38.68#ibcon#enter sib2, iclass 22, count 2 2006.173.06:33:38.68#ibcon#flushed, iclass 22, count 2 2006.173.06:33:38.68#ibcon#about to write, iclass 22, count 2 2006.173.06:33:38.68#ibcon#wrote, iclass 22, count 2 2006.173.06:33:38.68#ibcon#about to read 3, iclass 22, count 2 2006.173.06:33:38.69#ibcon#read 3, iclass 22, count 2 2006.173.06:33:38.69#ibcon#about to read 4, iclass 22, count 2 2006.173.06:33:38.70#ibcon#read 4, iclass 22, count 2 2006.173.06:33:38.70#ibcon#about to read 5, iclass 22, count 2 2006.173.06:33:38.70#ibcon#read 5, iclass 22, count 2 2006.173.06:33:38.70#ibcon#about to read 6, iclass 22, count 2 2006.173.06:33:38.70#ibcon#read 6, iclass 22, count 2 2006.173.06:33:38.70#ibcon#end of sib2, iclass 22, count 2 2006.173.06:33:38.70#ibcon#*mode == 0, iclass 22, count 2 2006.173.06:33:38.70#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.06:33:38.70#ibcon#[27=AT03-04\r\n] 2006.173.06:33:38.70#ibcon#*before write, iclass 22, count 2 2006.173.06:33:38.70#ibcon#enter sib2, iclass 22, count 2 2006.173.06:33:38.70#ibcon#flushed, iclass 22, count 2 2006.173.06:33:38.70#ibcon#about to write, iclass 22, count 2 2006.173.06:33:38.70#ibcon#wrote, iclass 22, count 2 2006.173.06:33:38.70#ibcon#about to read 3, iclass 22, count 2 2006.173.06:33:38.72#ibcon#read 3, iclass 22, count 2 2006.173.06:33:38.72#ibcon#about to read 4, iclass 22, count 2 2006.173.06:33:38.73#ibcon#read 4, iclass 22, count 2 2006.173.06:33:38.73#ibcon#about to read 5, iclass 22, count 2 2006.173.06:33:38.73#ibcon#read 5, iclass 22, count 2 2006.173.06:33:38.73#ibcon#about to read 6, iclass 22, count 2 2006.173.06:33:38.73#ibcon#read 6, iclass 22, count 2 2006.173.06:33:38.73#ibcon#end of sib2, iclass 22, count 2 2006.173.06:33:38.73#ibcon#*after write, iclass 22, count 2 2006.173.06:33:38.73#ibcon#*before return 0, iclass 22, count 2 2006.173.06:33:38.73#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.06:33:38.73#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.06:33:38.73#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.06:33:38.73#ibcon#ireg 7 cls_cnt 0 2006.173.06:33:38.73#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.06:33:38.84#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.06:33:38.84#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.06:33:38.84#ibcon#enter wrdev, iclass 22, count 0 2006.173.06:33:38.84#ibcon#first serial, iclass 22, count 0 2006.173.06:33:38.85#ibcon#enter sib2, iclass 22, count 0 2006.173.06:33:38.85#ibcon#flushed, iclass 22, count 0 2006.173.06:33:38.85#ibcon#about to write, iclass 22, count 0 2006.173.06:33:38.85#ibcon#wrote, iclass 22, count 0 2006.173.06:33:38.85#ibcon#about to read 3, iclass 22, count 0 2006.173.06:33:38.86#ibcon#read 3, iclass 22, count 0 2006.173.06:33:38.86#ibcon#about to read 4, iclass 22, count 0 2006.173.06:33:38.86#ibcon#read 4, iclass 22, count 0 2006.173.06:33:38.87#ibcon#about to read 5, iclass 22, count 0 2006.173.06:33:38.87#ibcon#read 5, iclass 22, count 0 2006.173.06:33:38.87#ibcon#about to read 6, iclass 22, count 0 2006.173.06:33:38.87#ibcon#read 6, iclass 22, count 0 2006.173.06:33:38.87#ibcon#end of sib2, iclass 22, count 0 2006.173.06:33:38.87#ibcon#*mode == 0, iclass 22, count 0 2006.173.06:33:38.87#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.06:33:38.87#ibcon#[27=USB\r\n] 2006.173.06:33:38.87#ibcon#*before write, iclass 22, count 0 2006.173.06:33:38.87#ibcon#enter sib2, iclass 22, count 0 2006.173.06:33:38.87#ibcon#flushed, iclass 22, count 0 2006.173.06:33:38.87#ibcon#about to write, iclass 22, count 0 2006.173.06:33:38.87#ibcon#wrote, iclass 22, count 0 2006.173.06:33:38.87#ibcon#about to read 3, iclass 22, count 0 2006.173.06:33:38.89#ibcon#read 3, iclass 22, count 0 2006.173.06:33:38.89#ibcon#about to read 4, iclass 22, count 0 2006.173.06:33:38.90#ibcon#read 4, iclass 22, count 0 2006.173.06:33:38.90#ibcon#about to read 5, iclass 22, count 0 2006.173.06:33:38.90#ibcon#read 5, iclass 22, count 0 2006.173.06:33:38.90#ibcon#about to read 6, iclass 22, count 0 2006.173.06:33:38.90#ibcon#read 6, iclass 22, count 0 2006.173.06:33:38.90#ibcon#end of sib2, iclass 22, count 0 2006.173.06:33:38.90#ibcon#*after write, iclass 22, count 0 2006.173.06:33:38.90#ibcon#*before return 0, iclass 22, count 0 2006.173.06:33:38.90#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.06:33:38.90#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.06:33:38.90#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.06:33:38.90#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.06:33:38.90$vck44/vblo=4,679.99 2006.173.06:33:38.90#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.06:33:38.90#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.06:33:38.90#ibcon#ireg 17 cls_cnt 0 2006.173.06:33:38.90#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.06:33:38.90#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.06:33:38.90#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.06:33:38.90#ibcon#enter wrdev, iclass 24, count 0 2006.173.06:33:38.90#ibcon#first serial, iclass 24, count 0 2006.173.06:33:38.90#ibcon#enter sib2, iclass 24, count 0 2006.173.06:33:38.90#ibcon#flushed, iclass 24, count 0 2006.173.06:33:38.90#ibcon#about to write, iclass 24, count 0 2006.173.06:33:38.90#ibcon#wrote, iclass 24, count 0 2006.173.06:33:38.90#ibcon#about to read 3, iclass 24, count 0 2006.173.06:33:38.91#ibcon#read 3, iclass 24, count 0 2006.173.06:33:38.91#ibcon#about to read 4, iclass 24, count 0 2006.173.06:33:38.92#ibcon#read 4, iclass 24, count 0 2006.173.06:33:38.92#ibcon#about to read 5, iclass 24, count 0 2006.173.06:33:38.92#ibcon#read 5, iclass 24, count 0 2006.173.06:33:38.92#ibcon#about to read 6, iclass 24, count 0 2006.173.06:33:38.92#ibcon#read 6, iclass 24, count 0 2006.173.06:33:38.92#ibcon#end of sib2, iclass 24, count 0 2006.173.06:33:38.92#ibcon#*mode == 0, iclass 24, count 0 2006.173.06:33:38.92#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.06:33:38.92#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.06:33:38.92#ibcon#*before write, iclass 24, count 0 2006.173.06:33:38.92#ibcon#enter sib2, iclass 24, count 0 2006.173.06:33:38.92#ibcon#flushed, iclass 24, count 0 2006.173.06:33:38.92#ibcon#about to write, iclass 24, count 0 2006.173.06:33:38.92#ibcon#wrote, iclass 24, count 0 2006.173.06:33:38.92#ibcon#about to read 3, iclass 24, count 0 2006.173.06:33:38.95#ibcon#read 3, iclass 24, count 0 2006.173.06:33:38.95#ibcon#about to read 4, iclass 24, count 0 2006.173.06:33:38.96#ibcon#read 4, iclass 24, count 0 2006.173.06:33:38.96#ibcon#about to read 5, iclass 24, count 0 2006.173.06:33:38.96#ibcon#read 5, iclass 24, count 0 2006.173.06:33:38.96#ibcon#about to read 6, iclass 24, count 0 2006.173.06:33:38.96#ibcon#read 6, iclass 24, count 0 2006.173.06:33:38.96#ibcon#end of sib2, iclass 24, count 0 2006.173.06:33:38.96#ibcon#*after write, iclass 24, count 0 2006.173.06:33:38.96#ibcon#*before return 0, iclass 24, count 0 2006.173.06:33:38.96#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.06:33:38.96#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.06:33:38.96#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.06:33:38.96#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.06:33:38.96$vck44/vb=4,4 2006.173.06:33:38.96#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.06:33:38.96#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.06:33:38.96#ibcon#ireg 11 cls_cnt 2 2006.173.06:33:38.96#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.06:33:39.01#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.06:33:39.01#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.06:33:39.01#ibcon#enter wrdev, iclass 26, count 2 2006.173.06:33:39.02#ibcon#first serial, iclass 26, count 2 2006.173.06:33:39.02#ibcon#enter sib2, iclass 26, count 2 2006.173.06:33:39.02#ibcon#flushed, iclass 26, count 2 2006.173.06:33:39.02#ibcon#about to write, iclass 26, count 2 2006.173.06:33:39.02#ibcon#wrote, iclass 26, count 2 2006.173.06:33:39.02#ibcon#about to read 3, iclass 26, count 2 2006.173.06:33:39.03#ibcon#read 3, iclass 26, count 2 2006.173.06:33:39.03#ibcon#about to read 4, iclass 26, count 2 2006.173.06:33:39.03#ibcon#read 4, iclass 26, count 2 2006.173.06:33:39.04#ibcon#about to read 5, iclass 26, count 2 2006.173.06:33:39.04#ibcon#read 5, iclass 26, count 2 2006.173.06:33:39.04#ibcon#about to read 6, iclass 26, count 2 2006.173.06:33:39.04#ibcon#read 6, iclass 26, count 2 2006.173.06:33:39.04#ibcon#end of sib2, iclass 26, count 2 2006.173.06:33:39.04#ibcon#*mode == 0, iclass 26, count 2 2006.173.06:33:39.04#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.06:33:39.04#ibcon#[27=AT04-04\r\n] 2006.173.06:33:39.04#ibcon#*before write, iclass 26, count 2 2006.173.06:33:39.04#ibcon#enter sib2, iclass 26, count 2 2006.173.06:33:39.04#ibcon#flushed, iclass 26, count 2 2006.173.06:33:39.04#ibcon#about to write, iclass 26, count 2 2006.173.06:33:39.04#ibcon#wrote, iclass 26, count 2 2006.173.06:33:39.04#ibcon#about to read 3, iclass 26, count 2 2006.173.06:33:39.06#ibcon#read 3, iclass 26, count 2 2006.173.06:33:39.06#ibcon#about to read 4, iclass 26, count 2 2006.173.06:33:39.07#ibcon#read 4, iclass 26, count 2 2006.173.06:33:39.07#ibcon#about to read 5, iclass 26, count 2 2006.173.06:33:39.07#ibcon#read 5, iclass 26, count 2 2006.173.06:33:39.07#ibcon#about to read 6, iclass 26, count 2 2006.173.06:33:39.07#ibcon#read 6, iclass 26, count 2 2006.173.06:33:39.07#ibcon#end of sib2, iclass 26, count 2 2006.173.06:33:39.07#ibcon#*after write, iclass 26, count 2 2006.173.06:33:39.07#ibcon#*before return 0, iclass 26, count 2 2006.173.06:33:39.07#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.06:33:39.07#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.06:33:39.07#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.06:33:39.07#ibcon#ireg 7 cls_cnt 0 2006.173.06:33:39.07#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.06:33:39.18#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.06:33:39.18#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.06:33:39.18#ibcon#enter wrdev, iclass 26, count 0 2006.173.06:33:39.19#ibcon#first serial, iclass 26, count 0 2006.173.06:33:39.19#ibcon#enter sib2, iclass 26, count 0 2006.173.06:33:39.19#ibcon#flushed, iclass 26, count 0 2006.173.06:33:39.19#ibcon#about to write, iclass 26, count 0 2006.173.06:33:39.19#ibcon#wrote, iclass 26, count 0 2006.173.06:33:39.19#ibcon#about to read 3, iclass 26, count 0 2006.173.06:33:39.20#ibcon#read 3, iclass 26, count 0 2006.173.06:33:39.20#ibcon#about to read 4, iclass 26, count 0 2006.173.06:33:39.20#ibcon#read 4, iclass 26, count 0 2006.173.06:33:39.20#ibcon#about to read 5, iclass 26, count 0 2006.173.06:33:39.20#ibcon#read 5, iclass 26, count 0 2006.173.06:33:39.21#ibcon#about to read 6, iclass 26, count 0 2006.173.06:33:39.21#ibcon#read 6, iclass 26, count 0 2006.173.06:33:39.21#ibcon#end of sib2, iclass 26, count 0 2006.173.06:33:39.21#ibcon#*mode == 0, iclass 26, count 0 2006.173.06:33:39.21#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.06:33:39.21#ibcon#[27=USB\r\n] 2006.173.06:33:39.21#ibcon#*before write, iclass 26, count 0 2006.173.06:33:39.21#ibcon#enter sib2, iclass 26, count 0 2006.173.06:33:39.21#ibcon#flushed, iclass 26, count 0 2006.173.06:33:39.21#ibcon#about to write, iclass 26, count 0 2006.173.06:33:39.21#ibcon#wrote, iclass 26, count 0 2006.173.06:33:39.21#ibcon#about to read 3, iclass 26, count 0 2006.173.06:33:39.23#ibcon#read 3, iclass 26, count 0 2006.173.06:33:39.23#ibcon#about to read 4, iclass 26, count 0 2006.173.06:33:39.23#ibcon#read 4, iclass 26, count 0 2006.173.06:33:39.23#ibcon#about to read 5, iclass 26, count 0 2006.173.06:33:39.24#ibcon#read 5, iclass 26, count 0 2006.173.06:33:39.24#ibcon#about to read 6, iclass 26, count 0 2006.173.06:33:39.24#ibcon#read 6, iclass 26, count 0 2006.173.06:33:39.24#ibcon#end of sib2, iclass 26, count 0 2006.173.06:33:39.24#ibcon#*after write, iclass 26, count 0 2006.173.06:33:39.24#ibcon#*before return 0, iclass 26, count 0 2006.173.06:33:39.24#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.06:33:39.24#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.06:33:39.24#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.06:33:39.24#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.06:33:39.24$vck44/vblo=5,709.99 2006.173.06:33:39.24#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.06:33:39.24#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.06:33:39.24#ibcon#ireg 17 cls_cnt 0 2006.173.06:33:39.24#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.06:33:39.24#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.06:33:39.24#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.06:33:39.24#ibcon#enter wrdev, iclass 28, count 0 2006.173.06:33:39.24#ibcon#first serial, iclass 28, count 0 2006.173.06:33:39.24#ibcon#enter sib2, iclass 28, count 0 2006.173.06:33:39.24#ibcon#flushed, iclass 28, count 0 2006.173.06:33:39.24#ibcon#about to write, iclass 28, count 0 2006.173.06:33:39.24#ibcon#wrote, iclass 28, count 0 2006.173.06:33:39.24#ibcon#about to read 3, iclass 28, count 0 2006.173.06:33:39.25#ibcon#read 3, iclass 28, count 0 2006.173.06:33:39.25#ibcon#about to read 4, iclass 28, count 0 2006.173.06:33:39.25#ibcon#read 4, iclass 28, count 0 2006.173.06:33:39.25#ibcon#about to read 5, iclass 28, count 0 2006.173.06:33:39.25#ibcon#read 5, iclass 28, count 0 2006.173.06:33:39.26#ibcon#about to read 6, iclass 28, count 0 2006.173.06:33:39.26#ibcon#read 6, iclass 28, count 0 2006.173.06:33:39.26#ibcon#end of sib2, iclass 28, count 0 2006.173.06:33:39.26#ibcon#*mode == 0, iclass 28, count 0 2006.173.06:33:39.26#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.06:33:39.26#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.06:33:39.26#ibcon#*before write, iclass 28, count 0 2006.173.06:33:39.26#ibcon#enter sib2, iclass 28, count 0 2006.173.06:33:39.26#ibcon#flushed, iclass 28, count 0 2006.173.06:33:39.26#ibcon#about to write, iclass 28, count 0 2006.173.06:33:39.26#ibcon#wrote, iclass 28, count 0 2006.173.06:33:39.26#ibcon#about to read 3, iclass 28, count 0 2006.173.06:33:39.29#ibcon#read 3, iclass 28, count 0 2006.173.06:33:39.29#ibcon#about to read 4, iclass 28, count 0 2006.173.06:33:39.29#ibcon#read 4, iclass 28, count 0 2006.173.06:33:39.30#ibcon#about to read 5, iclass 28, count 0 2006.173.06:33:39.30#ibcon#read 5, iclass 28, count 0 2006.173.06:33:39.30#ibcon#about to read 6, iclass 28, count 0 2006.173.06:33:39.30#ibcon#read 6, iclass 28, count 0 2006.173.06:33:39.30#ibcon#end of sib2, iclass 28, count 0 2006.173.06:33:39.30#ibcon#*after write, iclass 28, count 0 2006.173.06:33:39.30#ibcon#*before return 0, iclass 28, count 0 2006.173.06:33:39.30#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.06:33:39.30#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.06:33:39.30#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.06:33:39.30#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.06:33:39.30$vck44/vb=5,4 2006.173.06:33:39.30#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.06:33:39.30#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.06:33:39.30#ibcon#ireg 11 cls_cnt 2 2006.173.06:33:39.30#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.06:33:39.35#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.06:33:39.35#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.06:33:39.35#ibcon#enter wrdev, iclass 30, count 2 2006.173.06:33:39.35#ibcon#first serial, iclass 30, count 2 2006.173.06:33:39.35#ibcon#enter sib2, iclass 30, count 2 2006.173.06:33:39.36#ibcon#flushed, iclass 30, count 2 2006.173.06:33:39.36#ibcon#about to write, iclass 30, count 2 2006.173.06:33:39.36#ibcon#wrote, iclass 30, count 2 2006.173.06:33:39.36#ibcon#about to read 3, iclass 30, count 2 2006.173.06:33:39.37#ibcon#read 3, iclass 30, count 2 2006.173.06:33:39.37#ibcon#about to read 4, iclass 30, count 2 2006.173.06:33:39.38#ibcon#read 4, iclass 30, count 2 2006.173.06:33:39.38#ibcon#about to read 5, iclass 30, count 2 2006.173.06:33:39.38#ibcon#read 5, iclass 30, count 2 2006.173.06:33:39.38#ibcon#about to read 6, iclass 30, count 2 2006.173.06:33:39.38#ibcon#read 6, iclass 30, count 2 2006.173.06:33:39.38#ibcon#end of sib2, iclass 30, count 2 2006.173.06:33:39.38#ibcon#*mode == 0, iclass 30, count 2 2006.173.06:33:39.38#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.06:33:39.38#ibcon#[27=AT05-04\r\n] 2006.173.06:33:39.38#ibcon#*before write, iclass 30, count 2 2006.173.06:33:39.38#ibcon#enter sib2, iclass 30, count 2 2006.173.06:33:39.38#ibcon#flushed, iclass 30, count 2 2006.173.06:33:39.38#ibcon#about to write, iclass 30, count 2 2006.173.06:33:39.38#ibcon#wrote, iclass 30, count 2 2006.173.06:33:39.38#ibcon#about to read 3, iclass 30, count 2 2006.173.06:33:39.40#ibcon#read 3, iclass 30, count 2 2006.173.06:33:39.40#ibcon#about to read 4, iclass 30, count 2 2006.173.06:33:39.40#ibcon#read 4, iclass 30, count 2 2006.173.06:33:39.40#ibcon#about to read 5, iclass 30, count 2 2006.173.06:33:39.40#ibcon#read 5, iclass 30, count 2 2006.173.06:33:39.40#ibcon#about to read 6, iclass 30, count 2 2006.173.06:33:39.41#ibcon#read 6, iclass 30, count 2 2006.173.06:33:39.41#ibcon#end of sib2, iclass 30, count 2 2006.173.06:33:39.41#ibcon#*after write, iclass 30, count 2 2006.173.06:33:39.41#ibcon#*before return 0, iclass 30, count 2 2006.173.06:33:39.41#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.06:33:39.41#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.06:33:39.41#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.06:33:39.41#ibcon#ireg 7 cls_cnt 0 2006.173.06:33:39.41#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.06:33:39.52#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.06:33:39.52#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.06:33:39.52#ibcon#enter wrdev, iclass 30, count 0 2006.173.06:33:39.52#ibcon#first serial, iclass 30, count 0 2006.173.06:33:39.53#ibcon#enter sib2, iclass 30, count 0 2006.173.06:33:39.53#ibcon#flushed, iclass 30, count 0 2006.173.06:33:39.53#ibcon#about to write, iclass 30, count 0 2006.173.06:33:39.53#ibcon#wrote, iclass 30, count 0 2006.173.06:33:39.53#ibcon#about to read 3, iclass 30, count 0 2006.173.06:33:39.54#ibcon#read 3, iclass 30, count 0 2006.173.06:33:39.54#ibcon#about to read 4, iclass 30, count 0 2006.173.06:33:39.55#ibcon#read 4, iclass 30, count 0 2006.173.06:33:39.55#ibcon#about to read 5, iclass 30, count 0 2006.173.06:33:39.55#ibcon#read 5, iclass 30, count 0 2006.173.06:33:39.55#ibcon#about to read 6, iclass 30, count 0 2006.173.06:33:39.55#ibcon#read 6, iclass 30, count 0 2006.173.06:33:39.55#ibcon#end of sib2, iclass 30, count 0 2006.173.06:33:39.55#ibcon#*mode == 0, iclass 30, count 0 2006.173.06:33:39.55#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.06:33:39.55#ibcon#[27=USB\r\n] 2006.173.06:33:39.55#ibcon#*before write, iclass 30, count 0 2006.173.06:33:39.55#ibcon#enter sib2, iclass 30, count 0 2006.173.06:33:39.55#ibcon#flushed, iclass 30, count 0 2006.173.06:33:39.55#ibcon#about to write, iclass 30, count 0 2006.173.06:33:39.55#ibcon#wrote, iclass 30, count 0 2006.173.06:33:39.55#ibcon#about to read 3, iclass 30, count 0 2006.173.06:33:39.57#ibcon#read 3, iclass 30, count 0 2006.173.06:33:39.57#ibcon#about to read 4, iclass 30, count 0 2006.173.06:33:39.57#ibcon#read 4, iclass 30, count 0 2006.173.06:33:39.57#ibcon#about to read 5, iclass 30, count 0 2006.173.06:33:39.57#ibcon#read 5, iclass 30, count 0 2006.173.06:33:39.57#ibcon#about to read 6, iclass 30, count 0 2006.173.06:33:39.58#ibcon#read 6, iclass 30, count 0 2006.173.06:33:39.58#ibcon#end of sib2, iclass 30, count 0 2006.173.06:33:39.58#ibcon#*after write, iclass 30, count 0 2006.173.06:33:39.58#ibcon#*before return 0, iclass 30, count 0 2006.173.06:33:39.58#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.06:33:39.58#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.06:33:39.58#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.06:33:39.58#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.06:33:39.58$vck44/vblo=6,719.99 2006.173.06:33:39.58#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.06:33:39.58#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.06:33:39.58#ibcon#ireg 17 cls_cnt 0 2006.173.06:33:39.58#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.06:33:39.58#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.06:33:39.58#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.06:33:39.58#ibcon#enter wrdev, iclass 32, count 0 2006.173.06:33:39.58#ibcon#first serial, iclass 32, count 0 2006.173.06:33:39.58#ibcon#enter sib2, iclass 32, count 0 2006.173.06:33:39.58#ibcon#flushed, iclass 32, count 0 2006.173.06:33:39.58#ibcon#about to write, iclass 32, count 0 2006.173.06:33:39.58#ibcon#wrote, iclass 32, count 0 2006.173.06:33:39.58#ibcon#about to read 3, iclass 32, count 0 2006.173.06:33:39.59#ibcon#read 3, iclass 32, count 0 2006.173.06:33:39.59#ibcon#about to read 4, iclass 32, count 0 2006.173.06:33:39.60#ibcon#read 4, iclass 32, count 0 2006.173.06:33:39.60#ibcon#about to read 5, iclass 32, count 0 2006.173.06:33:39.60#ibcon#read 5, iclass 32, count 0 2006.173.06:33:39.60#ibcon#about to read 6, iclass 32, count 0 2006.173.06:33:39.60#ibcon#read 6, iclass 32, count 0 2006.173.06:33:39.60#ibcon#end of sib2, iclass 32, count 0 2006.173.06:33:39.60#ibcon#*mode == 0, iclass 32, count 0 2006.173.06:33:39.60#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.06:33:39.60#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.06:33:39.60#ibcon#*before write, iclass 32, count 0 2006.173.06:33:39.60#ibcon#enter sib2, iclass 32, count 0 2006.173.06:33:39.60#ibcon#flushed, iclass 32, count 0 2006.173.06:33:39.60#ibcon#about to write, iclass 32, count 0 2006.173.06:33:39.60#ibcon#wrote, iclass 32, count 0 2006.173.06:33:39.60#ibcon#about to read 3, iclass 32, count 0 2006.173.06:33:39.63#ibcon#read 3, iclass 32, count 0 2006.173.06:33:39.64#ibcon#about to read 4, iclass 32, count 0 2006.173.06:33:39.64#ibcon#read 4, iclass 32, count 0 2006.173.06:33:39.64#ibcon#about to read 5, iclass 32, count 0 2006.173.06:33:39.64#ibcon#read 5, iclass 32, count 0 2006.173.06:33:39.64#ibcon#about to read 6, iclass 32, count 0 2006.173.06:33:39.64#ibcon#read 6, iclass 32, count 0 2006.173.06:33:39.64#ibcon#end of sib2, iclass 32, count 0 2006.173.06:33:39.64#ibcon#*after write, iclass 32, count 0 2006.173.06:33:39.64#ibcon#*before return 0, iclass 32, count 0 2006.173.06:33:39.64#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.06:33:39.64#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.06:33:39.64#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.06:33:39.64#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.06:33:39.64$vck44/vb=6,4 2006.173.06:33:39.64#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.06:33:39.64#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.06:33:39.64#ibcon#ireg 11 cls_cnt 2 2006.173.06:33:39.64#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.06:33:39.69#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.06:33:39.69#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.06:33:39.69#ibcon#enter wrdev, iclass 34, count 2 2006.173.06:33:39.70#ibcon#first serial, iclass 34, count 2 2006.173.06:33:39.70#ibcon#enter sib2, iclass 34, count 2 2006.173.06:33:39.70#ibcon#flushed, iclass 34, count 2 2006.173.06:33:39.70#ibcon#about to write, iclass 34, count 2 2006.173.06:33:39.70#ibcon#wrote, iclass 34, count 2 2006.173.06:33:39.70#ibcon#about to read 3, iclass 34, count 2 2006.173.06:33:39.71#ibcon#read 3, iclass 34, count 2 2006.173.06:33:39.71#ibcon#about to read 4, iclass 34, count 2 2006.173.06:33:39.72#ibcon#read 4, iclass 34, count 2 2006.173.06:33:39.72#ibcon#about to read 5, iclass 34, count 2 2006.173.06:33:39.72#ibcon#read 5, iclass 34, count 2 2006.173.06:33:39.72#ibcon#about to read 6, iclass 34, count 2 2006.173.06:33:39.72#ibcon#read 6, iclass 34, count 2 2006.173.06:33:39.72#ibcon#end of sib2, iclass 34, count 2 2006.173.06:33:39.72#ibcon#*mode == 0, iclass 34, count 2 2006.173.06:33:39.72#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.06:33:39.72#ibcon#[27=AT06-04\r\n] 2006.173.06:33:39.72#ibcon#*before write, iclass 34, count 2 2006.173.06:33:39.72#ibcon#enter sib2, iclass 34, count 2 2006.173.06:33:39.72#ibcon#flushed, iclass 34, count 2 2006.173.06:33:39.72#ibcon#about to write, iclass 34, count 2 2006.173.06:33:39.72#ibcon#wrote, iclass 34, count 2 2006.173.06:33:39.72#ibcon#about to read 3, iclass 34, count 2 2006.173.06:33:39.74#ibcon#read 3, iclass 34, count 2 2006.173.06:33:39.74#ibcon#about to read 4, iclass 34, count 2 2006.173.06:33:39.75#ibcon#read 4, iclass 34, count 2 2006.173.06:33:39.75#ibcon#about to read 5, iclass 34, count 2 2006.173.06:33:39.75#ibcon#read 5, iclass 34, count 2 2006.173.06:33:39.75#ibcon#about to read 6, iclass 34, count 2 2006.173.06:33:39.75#ibcon#read 6, iclass 34, count 2 2006.173.06:33:39.75#ibcon#end of sib2, iclass 34, count 2 2006.173.06:33:39.75#ibcon#*after write, iclass 34, count 2 2006.173.06:33:39.75#ibcon#*before return 0, iclass 34, count 2 2006.173.06:33:39.75#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.06:33:39.75#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.06:33:39.75#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.06:33:39.75#ibcon#ireg 7 cls_cnt 0 2006.173.06:33:39.75#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.06:33:39.86#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.06:33:39.86#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.06:33:39.87#ibcon#enter wrdev, iclass 34, count 0 2006.173.06:33:39.87#ibcon#first serial, iclass 34, count 0 2006.173.06:33:39.87#ibcon#enter sib2, iclass 34, count 0 2006.173.06:33:39.87#ibcon#flushed, iclass 34, count 0 2006.173.06:33:39.87#ibcon#about to write, iclass 34, count 0 2006.173.06:33:39.87#ibcon#wrote, iclass 34, count 0 2006.173.06:33:39.87#ibcon#about to read 3, iclass 34, count 0 2006.173.06:33:39.88#ibcon#read 3, iclass 34, count 0 2006.173.06:33:39.88#ibcon#about to read 4, iclass 34, count 0 2006.173.06:33:39.88#ibcon#read 4, iclass 34, count 0 2006.173.06:33:39.89#ibcon#about to read 5, iclass 34, count 0 2006.173.06:33:39.89#ibcon#read 5, iclass 34, count 0 2006.173.06:33:39.89#ibcon#about to read 6, iclass 34, count 0 2006.173.06:33:39.89#ibcon#read 6, iclass 34, count 0 2006.173.06:33:39.89#ibcon#end of sib2, iclass 34, count 0 2006.173.06:33:39.89#ibcon#*mode == 0, iclass 34, count 0 2006.173.06:33:39.89#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.06:33:39.89#ibcon#[27=USB\r\n] 2006.173.06:33:39.89#ibcon#*before write, iclass 34, count 0 2006.173.06:33:39.89#ibcon#enter sib2, iclass 34, count 0 2006.173.06:33:39.89#ibcon#flushed, iclass 34, count 0 2006.173.06:33:39.89#ibcon#about to write, iclass 34, count 0 2006.173.06:33:39.89#ibcon#wrote, iclass 34, count 0 2006.173.06:33:39.89#ibcon#about to read 3, iclass 34, count 0 2006.173.06:33:39.91#ibcon#read 3, iclass 34, count 0 2006.173.06:33:39.91#ibcon#about to read 4, iclass 34, count 0 2006.173.06:33:39.91#ibcon#read 4, iclass 34, count 0 2006.173.06:33:39.92#ibcon#about to read 5, iclass 34, count 0 2006.173.06:33:39.92#ibcon#read 5, iclass 34, count 0 2006.173.06:33:39.92#ibcon#about to read 6, iclass 34, count 0 2006.173.06:33:39.92#ibcon#read 6, iclass 34, count 0 2006.173.06:33:39.92#ibcon#end of sib2, iclass 34, count 0 2006.173.06:33:39.92#ibcon#*after write, iclass 34, count 0 2006.173.06:33:39.92#ibcon#*before return 0, iclass 34, count 0 2006.173.06:33:39.92#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.06:33:39.92#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.06:33:39.92#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.06:33:39.92#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.06:33:39.92$vck44/vblo=7,734.99 2006.173.06:33:39.92#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.06:33:39.92#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.06:33:39.92#ibcon#ireg 17 cls_cnt 0 2006.173.06:33:39.92#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.06:33:39.92#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.06:33:39.92#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.06:33:39.92#ibcon#enter wrdev, iclass 36, count 0 2006.173.06:33:39.92#ibcon#first serial, iclass 36, count 0 2006.173.06:33:39.92#ibcon#enter sib2, iclass 36, count 0 2006.173.06:33:39.92#ibcon#flushed, iclass 36, count 0 2006.173.06:33:39.92#ibcon#about to write, iclass 36, count 0 2006.173.06:33:39.92#ibcon#wrote, iclass 36, count 0 2006.173.06:33:39.92#ibcon#about to read 3, iclass 36, count 0 2006.173.06:33:39.93#ibcon#read 3, iclass 36, count 0 2006.173.06:33:39.93#ibcon#about to read 4, iclass 36, count 0 2006.173.06:33:39.93#ibcon#read 4, iclass 36, count 0 2006.173.06:33:39.93#ibcon#about to read 5, iclass 36, count 0 2006.173.06:33:39.94#ibcon#read 5, iclass 36, count 0 2006.173.06:33:39.94#ibcon#about to read 6, iclass 36, count 0 2006.173.06:33:39.94#ibcon#read 6, iclass 36, count 0 2006.173.06:33:39.94#ibcon#end of sib2, iclass 36, count 0 2006.173.06:33:39.94#ibcon#*mode == 0, iclass 36, count 0 2006.173.06:33:39.94#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.06:33:39.94#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.06:33:39.94#ibcon#*before write, iclass 36, count 0 2006.173.06:33:39.94#ibcon#enter sib2, iclass 36, count 0 2006.173.06:33:39.94#ibcon#flushed, iclass 36, count 0 2006.173.06:33:39.94#ibcon#about to write, iclass 36, count 0 2006.173.06:33:39.94#ibcon#wrote, iclass 36, count 0 2006.173.06:33:39.94#ibcon#about to read 3, iclass 36, count 0 2006.173.06:33:39.97#ibcon#read 3, iclass 36, count 0 2006.173.06:33:39.97#ibcon#about to read 4, iclass 36, count 0 2006.173.06:33:39.97#ibcon#read 4, iclass 36, count 0 2006.173.06:33:39.97#ibcon#about to read 5, iclass 36, count 0 2006.173.06:33:39.98#ibcon#read 5, iclass 36, count 0 2006.173.06:33:39.98#ibcon#about to read 6, iclass 36, count 0 2006.173.06:33:39.98#ibcon#read 6, iclass 36, count 0 2006.173.06:33:39.98#ibcon#end of sib2, iclass 36, count 0 2006.173.06:33:39.98#ibcon#*after write, iclass 36, count 0 2006.173.06:33:39.98#ibcon#*before return 0, iclass 36, count 0 2006.173.06:33:39.98#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.06:33:39.98#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.06:33:39.98#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.06:33:39.98#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.06:33:39.98$vck44/vb=7,4 2006.173.06:33:39.98#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.06:33:39.98#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.06:33:39.98#ibcon#ireg 11 cls_cnt 2 2006.173.06:33:39.98#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.06:33:40.03#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.06:33:40.03#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.06:33:40.03#ibcon#enter wrdev, iclass 38, count 2 2006.173.06:33:40.04#ibcon#first serial, iclass 38, count 2 2006.173.06:33:40.04#ibcon#enter sib2, iclass 38, count 2 2006.173.06:33:40.04#ibcon#flushed, iclass 38, count 2 2006.173.06:33:40.04#ibcon#about to write, iclass 38, count 2 2006.173.06:33:40.04#ibcon#wrote, iclass 38, count 2 2006.173.06:33:40.04#ibcon#about to read 3, iclass 38, count 2 2006.173.06:33:40.05#ibcon#read 3, iclass 38, count 2 2006.173.06:33:40.05#ibcon#about to read 4, iclass 38, count 2 2006.173.06:33:40.05#ibcon#read 4, iclass 38, count 2 2006.173.06:33:40.05#ibcon#about to read 5, iclass 38, count 2 2006.173.06:33:40.05#ibcon#read 5, iclass 38, count 2 2006.173.06:33:40.06#ibcon#about to read 6, iclass 38, count 2 2006.173.06:33:40.06#ibcon#read 6, iclass 38, count 2 2006.173.06:33:40.06#ibcon#end of sib2, iclass 38, count 2 2006.173.06:33:40.06#ibcon#*mode == 0, iclass 38, count 2 2006.173.06:33:40.06#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.06:33:40.06#ibcon#[27=AT07-04\r\n] 2006.173.06:33:40.06#ibcon#*before write, iclass 38, count 2 2006.173.06:33:40.06#ibcon#enter sib2, iclass 38, count 2 2006.173.06:33:40.06#ibcon#flushed, iclass 38, count 2 2006.173.06:33:40.06#ibcon#about to write, iclass 38, count 2 2006.173.06:33:40.06#ibcon#wrote, iclass 38, count 2 2006.173.06:33:40.06#ibcon#about to read 3, iclass 38, count 2 2006.173.06:33:40.08#ibcon#read 3, iclass 38, count 2 2006.173.06:33:40.08#ibcon#about to read 4, iclass 38, count 2 2006.173.06:33:40.08#ibcon#read 4, iclass 38, count 2 2006.173.06:33:40.08#ibcon#about to read 5, iclass 38, count 2 2006.173.06:33:40.08#ibcon#read 5, iclass 38, count 2 2006.173.06:33:40.09#ibcon#about to read 6, iclass 38, count 2 2006.173.06:33:40.09#ibcon#read 6, iclass 38, count 2 2006.173.06:33:40.09#ibcon#end of sib2, iclass 38, count 2 2006.173.06:33:40.09#ibcon#*after write, iclass 38, count 2 2006.173.06:33:40.09#ibcon#*before return 0, iclass 38, count 2 2006.173.06:33:40.09#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.06:33:40.09#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.06:33:40.09#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.06:33:40.09#ibcon#ireg 7 cls_cnt 0 2006.173.06:33:40.09#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.06:33:40.20#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.06:33:40.20#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.06:33:40.20#ibcon#enter wrdev, iclass 38, count 0 2006.173.06:33:40.20#ibcon#first serial, iclass 38, count 0 2006.173.06:33:40.21#ibcon#enter sib2, iclass 38, count 0 2006.173.06:33:40.21#ibcon#flushed, iclass 38, count 0 2006.173.06:33:40.21#ibcon#about to write, iclass 38, count 0 2006.173.06:33:40.21#ibcon#wrote, iclass 38, count 0 2006.173.06:33:40.21#ibcon#about to read 3, iclass 38, count 0 2006.173.06:33:40.22#ibcon#read 3, iclass 38, count 0 2006.173.06:33:40.22#ibcon#about to read 4, iclass 38, count 0 2006.173.06:33:40.22#ibcon#read 4, iclass 38, count 0 2006.173.06:33:40.22#ibcon#about to read 5, iclass 38, count 0 2006.173.06:33:40.23#ibcon#read 5, iclass 38, count 0 2006.173.06:33:40.23#ibcon#about to read 6, iclass 38, count 0 2006.173.06:33:40.23#ibcon#read 6, iclass 38, count 0 2006.173.06:33:40.23#ibcon#end of sib2, iclass 38, count 0 2006.173.06:33:40.23#ibcon#*mode == 0, iclass 38, count 0 2006.173.06:33:40.23#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.06:33:40.23#ibcon#[27=USB\r\n] 2006.173.06:33:40.23#ibcon#*before write, iclass 38, count 0 2006.173.06:33:40.23#ibcon#enter sib2, iclass 38, count 0 2006.173.06:33:40.23#ibcon#flushed, iclass 38, count 0 2006.173.06:33:40.23#ibcon#about to write, iclass 38, count 0 2006.173.06:33:40.23#ibcon#wrote, iclass 38, count 0 2006.173.06:33:40.23#ibcon#about to read 3, iclass 38, count 0 2006.173.06:33:40.25#ibcon#read 3, iclass 38, count 0 2006.173.06:33:40.25#ibcon#about to read 4, iclass 38, count 0 2006.173.06:33:40.25#ibcon#read 4, iclass 38, count 0 2006.173.06:33:40.25#ibcon#about to read 5, iclass 38, count 0 2006.173.06:33:40.25#ibcon#read 5, iclass 38, count 0 2006.173.06:33:40.26#ibcon#about to read 6, iclass 38, count 0 2006.173.06:33:40.26#ibcon#read 6, iclass 38, count 0 2006.173.06:33:40.26#ibcon#end of sib2, iclass 38, count 0 2006.173.06:33:40.26#ibcon#*after write, iclass 38, count 0 2006.173.06:33:40.26#ibcon#*before return 0, iclass 38, count 0 2006.173.06:33:40.26#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.06:33:40.26#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.06:33:40.26#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.06:33:40.26#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.06:33:40.26$vck44/vblo=8,744.99 2006.173.06:33:40.26#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.06:33:40.26#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.06:33:40.26#ibcon#ireg 17 cls_cnt 0 2006.173.06:33:40.26#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.06:33:40.26#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.06:33:40.26#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.06:33:40.26#ibcon#enter wrdev, iclass 40, count 0 2006.173.06:33:40.26#ibcon#first serial, iclass 40, count 0 2006.173.06:33:40.26#ibcon#enter sib2, iclass 40, count 0 2006.173.06:33:40.26#ibcon#flushed, iclass 40, count 0 2006.173.06:33:40.26#ibcon#about to write, iclass 40, count 0 2006.173.06:33:40.26#ibcon#wrote, iclass 40, count 0 2006.173.06:33:40.26#ibcon#about to read 3, iclass 40, count 0 2006.173.06:33:40.27#ibcon#read 3, iclass 40, count 0 2006.173.06:33:40.27#ibcon#about to read 4, iclass 40, count 0 2006.173.06:33:40.27#ibcon#read 4, iclass 40, count 0 2006.173.06:33:40.27#ibcon#about to read 5, iclass 40, count 0 2006.173.06:33:40.27#ibcon#read 5, iclass 40, count 0 2006.173.06:33:40.28#ibcon#about to read 6, iclass 40, count 0 2006.173.06:33:40.28#ibcon#read 6, iclass 40, count 0 2006.173.06:33:40.28#ibcon#end of sib2, iclass 40, count 0 2006.173.06:33:40.28#ibcon#*mode == 0, iclass 40, count 0 2006.173.06:33:40.28#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.06:33:40.28#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.06:33:40.28#ibcon#*before write, iclass 40, count 0 2006.173.06:33:40.28#ibcon#enter sib2, iclass 40, count 0 2006.173.06:33:40.28#ibcon#flushed, iclass 40, count 0 2006.173.06:33:40.28#ibcon#about to write, iclass 40, count 0 2006.173.06:33:40.28#ibcon#wrote, iclass 40, count 0 2006.173.06:33:40.28#ibcon#about to read 3, iclass 40, count 0 2006.173.06:33:40.31#ibcon#read 3, iclass 40, count 0 2006.173.06:33:40.31#ibcon#about to read 4, iclass 40, count 0 2006.173.06:33:40.31#ibcon#read 4, iclass 40, count 0 2006.173.06:33:40.31#ibcon#about to read 5, iclass 40, count 0 2006.173.06:33:40.31#ibcon#read 5, iclass 40, count 0 2006.173.06:33:40.32#ibcon#about to read 6, iclass 40, count 0 2006.173.06:33:40.32#ibcon#read 6, iclass 40, count 0 2006.173.06:33:40.32#ibcon#end of sib2, iclass 40, count 0 2006.173.06:33:40.32#ibcon#*after write, iclass 40, count 0 2006.173.06:33:40.32#ibcon#*before return 0, iclass 40, count 0 2006.173.06:33:40.32#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.06:33:40.32#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.06:33:40.32#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.06:33:40.32#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.06:33:40.32$vck44/vb=8,4 2006.173.06:33:40.32#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.06:33:40.32#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.06:33:40.32#ibcon#ireg 11 cls_cnt 2 2006.173.06:33:40.32#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.06:33:40.37#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.06:33:40.37#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.06:33:40.37#ibcon#enter wrdev, iclass 4, count 2 2006.173.06:33:40.37#ibcon#first serial, iclass 4, count 2 2006.173.06:33:40.37#ibcon#enter sib2, iclass 4, count 2 2006.173.06:33:40.38#ibcon#flushed, iclass 4, count 2 2006.173.06:33:40.38#ibcon#about to write, iclass 4, count 2 2006.173.06:33:40.38#ibcon#wrote, iclass 4, count 2 2006.173.06:33:40.38#ibcon#about to read 3, iclass 4, count 2 2006.173.06:33:40.39#ibcon#read 3, iclass 4, count 2 2006.173.06:33:40.39#ibcon#about to read 4, iclass 4, count 2 2006.173.06:33:40.40#ibcon#read 4, iclass 4, count 2 2006.173.06:33:40.40#ibcon#about to read 5, iclass 4, count 2 2006.173.06:33:40.40#ibcon#read 5, iclass 4, count 2 2006.173.06:33:40.40#ibcon#about to read 6, iclass 4, count 2 2006.173.06:33:40.40#ibcon#read 6, iclass 4, count 2 2006.173.06:33:40.40#ibcon#end of sib2, iclass 4, count 2 2006.173.06:33:40.40#ibcon#*mode == 0, iclass 4, count 2 2006.173.06:33:40.40#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.06:33:40.40#ibcon#[27=AT08-04\r\n] 2006.173.06:33:40.40#ibcon#*before write, iclass 4, count 2 2006.173.06:33:40.40#ibcon#enter sib2, iclass 4, count 2 2006.173.06:33:40.40#ibcon#flushed, iclass 4, count 2 2006.173.06:33:40.40#ibcon#about to write, iclass 4, count 2 2006.173.06:33:40.40#ibcon#wrote, iclass 4, count 2 2006.173.06:33:40.40#ibcon#about to read 3, iclass 4, count 2 2006.173.06:33:40.42#ibcon#read 3, iclass 4, count 2 2006.173.06:33:40.42#ibcon#about to read 4, iclass 4, count 2 2006.173.06:33:40.42#ibcon#read 4, iclass 4, count 2 2006.173.06:33:40.42#ibcon#about to read 5, iclass 4, count 2 2006.173.06:33:40.42#ibcon#read 5, iclass 4, count 2 2006.173.06:33:40.43#ibcon#about to read 6, iclass 4, count 2 2006.173.06:33:40.43#ibcon#read 6, iclass 4, count 2 2006.173.06:33:40.43#ibcon#end of sib2, iclass 4, count 2 2006.173.06:33:40.43#ibcon#*after write, iclass 4, count 2 2006.173.06:33:40.43#ibcon#*before return 0, iclass 4, count 2 2006.173.06:33:40.43#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.06:33:40.43#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.06:33:40.43#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.06:33:40.43#ibcon#ireg 7 cls_cnt 0 2006.173.06:33:40.43#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.06:33:40.54#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.06:33:40.54#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.06:33:40.54#ibcon#enter wrdev, iclass 4, count 0 2006.173.06:33:40.55#ibcon#first serial, iclass 4, count 0 2006.173.06:33:40.55#ibcon#enter sib2, iclass 4, count 0 2006.173.06:33:40.55#ibcon#flushed, iclass 4, count 0 2006.173.06:33:40.55#ibcon#about to write, iclass 4, count 0 2006.173.06:33:40.55#ibcon#wrote, iclass 4, count 0 2006.173.06:33:40.55#ibcon#about to read 3, iclass 4, count 0 2006.173.06:33:40.56#ibcon#read 3, iclass 4, count 0 2006.173.06:33:40.56#ibcon#about to read 4, iclass 4, count 0 2006.173.06:33:40.56#ibcon#read 4, iclass 4, count 0 2006.173.06:33:40.56#ibcon#about to read 5, iclass 4, count 0 2006.173.06:33:40.56#ibcon#read 5, iclass 4, count 0 2006.173.06:33:40.56#ibcon#about to read 6, iclass 4, count 0 2006.173.06:33:40.57#ibcon#read 6, iclass 4, count 0 2006.173.06:33:40.57#ibcon#end of sib2, iclass 4, count 0 2006.173.06:33:40.57#ibcon#*mode == 0, iclass 4, count 0 2006.173.06:33:40.57#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.06:33:40.57#ibcon#[27=USB\r\n] 2006.173.06:33:40.57#ibcon#*before write, iclass 4, count 0 2006.173.06:33:40.57#ibcon#enter sib2, iclass 4, count 0 2006.173.06:33:40.57#ibcon#flushed, iclass 4, count 0 2006.173.06:33:40.57#ibcon#about to write, iclass 4, count 0 2006.173.06:33:40.57#ibcon#wrote, iclass 4, count 0 2006.173.06:33:40.57#ibcon#about to read 3, iclass 4, count 0 2006.173.06:33:40.59#ibcon#read 3, iclass 4, count 0 2006.173.06:33:40.59#ibcon#about to read 4, iclass 4, count 0 2006.173.06:33:40.59#ibcon#read 4, iclass 4, count 0 2006.173.06:33:40.60#ibcon#about to read 5, iclass 4, count 0 2006.173.06:33:40.60#ibcon#read 5, iclass 4, count 0 2006.173.06:33:40.60#ibcon#about to read 6, iclass 4, count 0 2006.173.06:33:40.60#ibcon#read 6, iclass 4, count 0 2006.173.06:33:40.60#ibcon#end of sib2, iclass 4, count 0 2006.173.06:33:40.60#ibcon#*after write, iclass 4, count 0 2006.173.06:33:40.60#ibcon#*before return 0, iclass 4, count 0 2006.173.06:33:40.60#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.06:33:40.60#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.06:33:40.60#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.06:33:40.60#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.06:33:40.60$vck44/vabw=wide 2006.173.06:33:40.60#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.06:33:40.60#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.06:33:40.60#ibcon#ireg 8 cls_cnt 0 2006.173.06:33:40.60#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.06:33:40.60#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.06:33:40.60#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.06:33:40.60#ibcon#enter wrdev, iclass 6, count 0 2006.173.06:33:40.60#ibcon#first serial, iclass 6, count 0 2006.173.06:33:40.60#ibcon#enter sib2, iclass 6, count 0 2006.173.06:33:40.60#ibcon#flushed, iclass 6, count 0 2006.173.06:33:40.60#ibcon#about to write, iclass 6, count 0 2006.173.06:33:40.60#ibcon#wrote, iclass 6, count 0 2006.173.06:33:40.60#ibcon#about to read 3, iclass 6, count 0 2006.173.06:33:40.61#ibcon#read 3, iclass 6, count 0 2006.173.06:33:40.61#ibcon#about to read 4, iclass 6, count 0 2006.173.06:33:40.61#ibcon#read 4, iclass 6, count 0 2006.173.06:33:40.61#ibcon#about to read 5, iclass 6, count 0 2006.173.06:33:40.61#ibcon#read 5, iclass 6, count 0 2006.173.06:33:40.62#ibcon#about to read 6, iclass 6, count 0 2006.173.06:33:40.62#ibcon#read 6, iclass 6, count 0 2006.173.06:33:40.62#ibcon#end of sib2, iclass 6, count 0 2006.173.06:33:40.62#ibcon#*mode == 0, iclass 6, count 0 2006.173.06:33:40.62#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.06:33:40.62#ibcon#[25=BW32\r\n] 2006.173.06:33:40.62#ibcon#*before write, iclass 6, count 0 2006.173.06:33:40.62#ibcon#enter sib2, iclass 6, count 0 2006.173.06:33:40.62#ibcon#flushed, iclass 6, count 0 2006.173.06:33:40.62#ibcon#about to write, iclass 6, count 0 2006.173.06:33:40.62#ibcon#wrote, iclass 6, count 0 2006.173.06:33:40.62#ibcon#about to read 3, iclass 6, count 0 2006.173.06:33:40.64#ibcon#read 3, iclass 6, count 0 2006.173.06:33:40.64#ibcon#about to read 4, iclass 6, count 0 2006.173.06:33:40.64#ibcon#read 4, iclass 6, count 0 2006.173.06:33:40.64#ibcon#about to read 5, iclass 6, count 0 2006.173.06:33:40.64#ibcon#read 5, iclass 6, count 0 2006.173.06:33:40.64#ibcon#about to read 6, iclass 6, count 0 2006.173.06:33:40.65#ibcon#read 6, iclass 6, count 0 2006.173.06:33:40.65#ibcon#end of sib2, iclass 6, count 0 2006.173.06:33:40.65#ibcon#*after write, iclass 6, count 0 2006.173.06:33:40.65#ibcon#*before return 0, iclass 6, count 0 2006.173.06:33:40.65#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.06:33:40.65#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.06:33:40.65#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.06:33:40.65#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.06:33:40.65$vck44/vbbw=wide 2006.173.06:33:40.65#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.06:33:40.65#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.06:33:40.65#ibcon#ireg 8 cls_cnt 0 2006.173.06:33:40.65#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.06:33:40.71#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.06:33:40.71#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.06:33:40.71#ibcon#enter wrdev, iclass 10, count 0 2006.173.06:33:40.72#ibcon#first serial, iclass 10, count 0 2006.173.06:33:40.72#ibcon#enter sib2, iclass 10, count 0 2006.173.06:33:40.72#ibcon#flushed, iclass 10, count 0 2006.173.06:33:40.72#ibcon#about to write, iclass 10, count 0 2006.173.06:33:40.72#ibcon#wrote, iclass 10, count 0 2006.173.06:33:40.72#ibcon#about to read 3, iclass 10, count 0 2006.173.06:33:40.73#ibcon#read 3, iclass 10, count 0 2006.173.06:33:40.74#ibcon#about to read 4, iclass 10, count 0 2006.173.06:33:40.74#ibcon#read 4, iclass 10, count 0 2006.173.06:33:40.74#ibcon#about to read 5, iclass 10, count 0 2006.173.06:33:40.74#ibcon#read 5, iclass 10, count 0 2006.173.06:33:40.74#ibcon#about to read 6, iclass 10, count 0 2006.173.06:33:40.74#ibcon#read 6, iclass 10, count 0 2006.173.06:33:40.74#ibcon#end of sib2, iclass 10, count 0 2006.173.06:33:40.74#ibcon#*mode == 0, iclass 10, count 0 2006.173.06:33:40.74#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.06:33:40.74#ibcon#[27=BW32\r\n] 2006.173.06:33:40.74#ibcon#*before write, iclass 10, count 0 2006.173.06:33:40.74#ibcon#enter sib2, iclass 10, count 0 2006.173.06:33:40.74#ibcon#flushed, iclass 10, count 0 2006.173.06:33:40.74#ibcon#about to write, iclass 10, count 0 2006.173.06:33:40.74#ibcon#wrote, iclass 10, count 0 2006.173.06:33:40.74#ibcon#about to read 3, iclass 10, count 0 2006.173.06:33:40.76#ibcon#read 3, iclass 10, count 0 2006.173.06:33:40.77#ibcon#about to read 4, iclass 10, count 0 2006.173.06:33:40.77#ibcon#read 4, iclass 10, count 0 2006.173.06:33:40.77#ibcon#about to read 5, iclass 10, count 0 2006.173.06:33:40.77#ibcon#read 5, iclass 10, count 0 2006.173.06:33:40.77#ibcon#about to read 6, iclass 10, count 0 2006.173.06:33:40.77#ibcon#read 6, iclass 10, count 0 2006.173.06:33:40.77#ibcon#end of sib2, iclass 10, count 0 2006.173.06:33:40.77#ibcon#*after write, iclass 10, count 0 2006.173.06:33:40.77#ibcon#*before return 0, iclass 10, count 0 2006.173.06:33:40.77#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.06:33:40.77#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.06:33:40.77#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.06:33:40.77#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.06:33:40.77$setupk4/ifdk4 2006.173.06:33:40.77$ifdk4/lo= 2006.173.06:33:40.77$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.06:33:40.77$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.06:33:40.77$ifdk4/patch= 2006.173.06:33:40.77$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.06:33:40.77$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.06:33:40.77$setupk4/!*+20s 2006.173.06:33:41.56#abcon#<5=/15 0.6 0.9 23.82 771005.0\r\n> 2006.173.06:33:41.58#abcon#{5=INTERFACE CLEAR} 2006.173.06:33:41.64#abcon#[5=S1D000X0/0*\r\n] 2006.173.06:33:51.73#abcon#<5=/15 0.6 0.9 23.82 771005.0\r\n> 2006.173.06:33:51.75#abcon#{5=INTERFACE CLEAR} 2006.173.06:33:51.81#abcon#[5=S1D000X0/0*\r\n] 2006.173.06:33:55.28$setupk4/"tpicd 2006.173.06:33:55.29$setupk4/echo=off 2006.173.06:33:55.29$setupk4/xlog=off 2006.173.06:33:55.29:!2006.173.06:35:31 2006.173.06:34:01.14#trakl#Source acquired 2006.173.06:34:01.15#flagr#flagr/antenna,acquired 2006.173.06:35:31.02:preob 2006.173.06:35:32.15/onsource/TRACKING 2006.173.06:35:32.15:!2006.173.06:35:41 2006.173.06:35:41.02:"tape 2006.173.06:35:41.02:"st=record 2006.173.06:35:41.02:data_valid=on 2006.173.06:35:41.02:midob 2006.173.06:35:42.15/onsource/TRACKING 2006.173.06:35:42.15/wx/23.80,1005.0,78 2006.173.06:35:42.20/cable/+6.5048E-03 2006.173.06:35:43.29/va/01,07,usb,yes,36,39 2006.173.06:35:43.29/va/02,06,usb,yes,36,37 2006.173.06:35:43.29/va/03,05,usb,yes,45,47 2006.173.06:35:43.29/va/04,06,usb,yes,37,39 2006.173.06:35:43.29/va/05,04,usb,yes,29,29 2006.173.06:35:43.29/va/06,03,usb,yes,40,40 2006.173.06:35:43.29/va/07,04,usb,yes,33,34 2006.173.06:35:43.29/va/08,04,usb,yes,28,33 2006.173.06:35:43.52/valo/01,524.99,yes,locked 2006.173.06:35:43.52/valo/02,534.99,yes,locked 2006.173.06:35:43.52/valo/03,564.99,yes,locked 2006.173.06:35:43.52/valo/04,624.99,yes,locked 2006.173.06:35:43.52/valo/05,734.99,yes,locked 2006.173.06:35:43.52/valo/06,814.99,yes,locked 2006.173.06:35:43.52/valo/07,864.99,yes,locked 2006.173.06:35:43.52/valo/08,884.99,yes,locked 2006.173.06:35:44.61/vb/01,04,usb,yes,30,28 2006.173.06:35:44.61/vb/02,04,usb,yes,32,32 2006.173.06:35:44.61/vb/03,04,usb,yes,29,32 2006.173.06:35:44.61/vb/04,04,usb,yes,33,32 2006.173.06:35:44.61/vb/05,04,usb,yes,26,28 2006.173.06:35:44.61/vb/06,04,usb,yes,30,27 2006.173.06:35:44.61/vb/07,04,usb,yes,30,30 2006.173.06:35:44.61/vb/08,04,usb,yes,28,31 2006.173.06:35:44.85/vblo/01,629.99,yes,locked 2006.173.06:35:44.85/vblo/02,634.99,yes,locked 2006.173.06:35:44.85/vblo/03,649.99,yes,locked 2006.173.06:35:44.85/vblo/04,679.99,yes,locked 2006.173.06:35:44.85/vblo/05,709.99,yes,locked 2006.173.06:35:44.85/vblo/06,719.99,yes,locked 2006.173.06:35:44.85/vblo/07,734.99,yes,locked 2006.173.06:35:44.85/vblo/08,744.99,yes,locked 2006.173.06:35:45.00/vabw/8 2006.173.06:35:45.15/vbbw/8 2006.173.06:35:45.24/xfe/off,on,15.2 2006.173.06:35:45.62/ifatt/23,28,28,28 2006.173.06:35:46.08/fmout-gps/S +3.98E-07 2006.173.06:35:46.13:!2006.173.06:36:41 2006.173.06:36:41.01:data_valid=off 2006.173.06:36:41.02:"et 2006.173.06:36:41.02:!+3s 2006.173.06:36:44.04:"tape 2006.173.06:36:44.04:postob 2006.173.06:36:44.12/cable/+6.5038E-03 2006.173.06:36:44.13/wx/23.78,1005.0,78 2006.173.06:36:44.18/fmout-gps/S +3.98E-07 2006.173.06:36:44.18:scan_name=173-0638,jd0606,120 2006.173.06:36:44.19:source=1334-127,133739.78,-125724.7,2000.0,ccw 2006.173.06:36:45.14#flagr#flagr/antenna,new-source 2006.173.06:36:45.15:checkk5 2006.173.06:36:45.50/chk_autoobs//k5ts1/ autoobs is running! 2006.173.06:36:45.91/chk_autoobs//k5ts2/ autoobs is running! 2006.173.06:36:46.33/chk_autoobs//k5ts3/ autoobs is running! 2006.173.06:36:46.72/chk_autoobs//k5ts4/ autoobs is running! 2006.173.06:36:47.12/chk_obsdata//k5ts1/T1730635??a.dat file size is correct (nominal:240MB, actual:240MB). 2006.173.06:36:47.54/chk_obsdata//k5ts2/T1730635??b.dat file size is correct (nominal:240MB, actual:240MB). 2006.173.06:36:47.94/chk_obsdata//k5ts3/T1730635??c.dat file size is correct (nominal:240MB, actual:240MB). 2006.173.06:36:48.34/chk_obsdata//k5ts4/T1730635??d.dat file size is correct (nominal:240MB, actual:240MB). 2006.173.06:36:49.05/k5log//k5ts1_log_newline 2006.173.06:36:49.74/k5log//k5ts2_log_newline 2006.173.06:36:50.45/k5log//k5ts3_log_newline 2006.173.06:36:51.15/k5log//k5ts4_log_newline 2006.173.06:36:51.18/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.06:36:51.18:setupk4=1 2006.173.06:36:51.18$setupk4/echo=on 2006.173.06:36:51.18$setupk4/pcalon 2006.173.06:36:51.18$pcalon/"no phase cal control is implemented here 2006.173.06:36:51.18$setupk4/"tpicd=stop 2006.173.06:36:51.18$setupk4/"rec=synch_on 2006.173.06:36:51.18$setupk4/"rec_mode=128 2006.173.06:36:51.18$setupk4/!* 2006.173.06:36:51.18$setupk4/recpk4 2006.173.06:36:51.18$recpk4/recpatch= 2006.173.06:36:51.18$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.06:36:51.18$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.06:36:51.18$setupk4/vck44 2006.173.06:36:51.18$vck44/valo=1,524.99 2006.173.06:36:51.18#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.06:36:51.18#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.06:36:51.18#ibcon#ireg 17 cls_cnt 0 2006.173.06:36:51.18#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.06:36:51.18#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.06:36:51.18#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.06:36:51.18#ibcon#enter wrdev, iclass 19, count 0 2006.173.06:36:51.18#ibcon#first serial, iclass 19, count 0 2006.173.06:36:51.18#ibcon#enter sib2, iclass 19, count 0 2006.173.06:36:51.18#ibcon#flushed, iclass 19, count 0 2006.173.06:36:51.18#ibcon#about to write, iclass 19, count 0 2006.173.06:36:51.18#ibcon#wrote, iclass 19, count 0 2006.173.06:36:51.18#ibcon#about to read 3, iclass 19, count 0 2006.173.06:36:51.19#ibcon#read 3, iclass 19, count 0 2006.173.06:36:51.19#ibcon#about to read 4, iclass 19, count 0 2006.173.06:36:51.19#ibcon#read 4, iclass 19, count 0 2006.173.06:36:51.19#ibcon#about to read 5, iclass 19, count 0 2006.173.06:36:51.19#ibcon#read 5, iclass 19, count 0 2006.173.06:36:51.19#ibcon#about to read 6, iclass 19, count 0 2006.173.06:36:51.19#ibcon#read 6, iclass 19, count 0 2006.173.06:36:51.19#ibcon#end of sib2, iclass 19, count 0 2006.173.06:36:51.19#ibcon#*mode == 0, iclass 19, count 0 2006.173.06:36:51.19#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.06:36:51.19#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.06:36:51.19#ibcon#*before write, iclass 19, count 0 2006.173.06:36:51.19#ibcon#enter sib2, iclass 19, count 0 2006.173.06:36:51.19#ibcon#flushed, iclass 19, count 0 2006.173.06:36:51.19#ibcon#about to write, iclass 19, count 0 2006.173.06:36:51.19#ibcon#wrote, iclass 19, count 0 2006.173.06:36:51.19#ibcon#about to read 3, iclass 19, count 0 2006.173.06:36:51.24#ibcon#read 3, iclass 19, count 0 2006.173.06:36:51.24#ibcon#about to read 4, iclass 19, count 0 2006.173.06:36:51.24#ibcon#read 4, iclass 19, count 0 2006.173.06:36:51.24#ibcon#about to read 5, iclass 19, count 0 2006.173.06:36:51.24#ibcon#read 5, iclass 19, count 0 2006.173.06:36:51.24#ibcon#about to read 6, iclass 19, count 0 2006.173.06:36:51.24#ibcon#read 6, iclass 19, count 0 2006.173.06:36:51.24#ibcon#end of sib2, iclass 19, count 0 2006.173.06:36:51.24#ibcon#*after write, iclass 19, count 0 2006.173.06:36:51.24#ibcon#*before return 0, iclass 19, count 0 2006.173.06:36:51.24#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.06:36:51.24#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.06:36:51.24#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.06:36:51.24#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.06:36:51.24$vck44/va=1,7 2006.173.06:36:51.24#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.06:36:51.24#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.06:36:51.24#ibcon#ireg 11 cls_cnt 2 2006.173.06:36:51.24#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.06:36:51.24#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.06:36:51.24#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.06:36:51.24#ibcon#enter wrdev, iclass 21, count 2 2006.173.06:36:51.24#ibcon#first serial, iclass 21, count 2 2006.173.06:36:51.24#ibcon#enter sib2, iclass 21, count 2 2006.173.06:36:51.24#ibcon#flushed, iclass 21, count 2 2006.173.06:36:51.24#ibcon#about to write, iclass 21, count 2 2006.173.06:36:51.24#ibcon#wrote, iclass 21, count 2 2006.173.06:36:51.24#ibcon#about to read 3, iclass 21, count 2 2006.173.06:36:51.26#ibcon#read 3, iclass 21, count 2 2006.173.06:36:51.26#ibcon#about to read 4, iclass 21, count 2 2006.173.06:36:51.26#ibcon#read 4, iclass 21, count 2 2006.173.06:36:51.26#ibcon#about to read 5, iclass 21, count 2 2006.173.06:36:51.26#ibcon#read 5, iclass 21, count 2 2006.173.06:36:51.26#ibcon#about to read 6, iclass 21, count 2 2006.173.06:36:51.26#ibcon#read 6, iclass 21, count 2 2006.173.06:36:51.26#ibcon#end of sib2, iclass 21, count 2 2006.173.06:36:51.26#ibcon#*mode == 0, iclass 21, count 2 2006.173.06:36:51.26#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.06:36:51.26#ibcon#[25=AT01-07\r\n] 2006.173.06:36:51.26#ibcon#*before write, iclass 21, count 2 2006.173.06:36:51.26#ibcon#enter sib2, iclass 21, count 2 2006.173.06:36:51.26#ibcon#flushed, iclass 21, count 2 2006.173.06:36:51.26#ibcon#about to write, iclass 21, count 2 2006.173.06:36:51.26#ibcon#wrote, iclass 21, count 2 2006.173.06:36:51.26#ibcon#about to read 3, iclass 21, count 2 2006.173.06:36:51.29#ibcon#read 3, iclass 21, count 2 2006.173.06:36:51.29#ibcon#about to read 4, iclass 21, count 2 2006.173.06:36:51.29#ibcon#read 4, iclass 21, count 2 2006.173.06:36:51.29#ibcon#about to read 5, iclass 21, count 2 2006.173.06:36:51.29#ibcon#read 5, iclass 21, count 2 2006.173.06:36:51.29#ibcon#about to read 6, iclass 21, count 2 2006.173.06:36:51.29#ibcon#read 6, iclass 21, count 2 2006.173.06:36:51.29#ibcon#end of sib2, iclass 21, count 2 2006.173.06:36:51.29#ibcon#*after write, iclass 21, count 2 2006.173.06:36:51.29#ibcon#*before return 0, iclass 21, count 2 2006.173.06:36:51.29#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.06:36:51.29#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.06:36:51.29#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.06:36:51.29#ibcon#ireg 7 cls_cnt 0 2006.173.06:36:51.29#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.06:36:51.41#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.06:36:51.41#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.06:36:51.41#ibcon#enter wrdev, iclass 21, count 0 2006.173.06:36:51.41#ibcon#first serial, iclass 21, count 0 2006.173.06:36:51.41#ibcon#enter sib2, iclass 21, count 0 2006.173.06:36:51.41#ibcon#flushed, iclass 21, count 0 2006.173.06:36:51.41#ibcon#about to write, iclass 21, count 0 2006.173.06:36:51.41#ibcon#wrote, iclass 21, count 0 2006.173.06:36:51.41#ibcon#about to read 3, iclass 21, count 0 2006.173.06:36:51.43#ibcon#read 3, iclass 21, count 0 2006.173.06:36:51.43#ibcon#about to read 4, iclass 21, count 0 2006.173.06:36:51.43#ibcon#read 4, iclass 21, count 0 2006.173.06:36:51.43#ibcon#about to read 5, iclass 21, count 0 2006.173.06:36:51.43#ibcon#read 5, iclass 21, count 0 2006.173.06:36:51.43#ibcon#about to read 6, iclass 21, count 0 2006.173.06:36:51.43#ibcon#read 6, iclass 21, count 0 2006.173.06:36:51.43#ibcon#end of sib2, iclass 21, count 0 2006.173.06:36:51.43#ibcon#*mode == 0, iclass 21, count 0 2006.173.06:36:51.43#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.06:36:51.43#ibcon#[25=USB\r\n] 2006.173.06:36:51.43#ibcon#*before write, iclass 21, count 0 2006.173.06:36:51.43#ibcon#enter sib2, iclass 21, count 0 2006.173.06:36:51.43#ibcon#flushed, iclass 21, count 0 2006.173.06:36:51.43#ibcon#about to write, iclass 21, count 0 2006.173.06:36:51.43#ibcon#wrote, iclass 21, count 0 2006.173.06:36:51.43#ibcon#about to read 3, iclass 21, count 0 2006.173.06:36:51.46#ibcon#read 3, iclass 21, count 0 2006.173.06:36:51.46#ibcon#about to read 4, iclass 21, count 0 2006.173.06:36:51.46#ibcon#read 4, iclass 21, count 0 2006.173.06:36:51.46#ibcon#about to read 5, iclass 21, count 0 2006.173.06:36:51.46#ibcon#read 5, iclass 21, count 0 2006.173.06:36:51.46#ibcon#about to read 6, iclass 21, count 0 2006.173.06:36:51.46#ibcon#read 6, iclass 21, count 0 2006.173.06:36:51.46#ibcon#end of sib2, iclass 21, count 0 2006.173.06:36:51.46#ibcon#*after write, iclass 21, count 0 2006.173.06:36:51.46#ibcon#*before return 0, iclass 21, count 0 2006.173.06:36:51.46#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.06:36:51.46#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.06:36:51.46#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.06:36:51.46#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.06:36:51.46$vck44/valo=2,534.99 2006.173.06:36:51.46#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.06:36:51.46#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.06:36:51.46#ibcon#ireg 17 cls_cnt 0 2006.173.06:36:51.46#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.06:36:51.46#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.06:36:51.46#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.06:36:51.46#ibcon#enter wrdev, iclass 23, count 0 2006.173.06:36:51.46#ibcon#first serial, iclass 23, count 0 2006.173.06:36:51.46#ibcon#enter sib2, iclass 23, count 0 2006.173.06:36:51.46#ibcon#flushed, iclass 23, count 0 2006.173.06:36:51.46#ibcon#about to write, iclass 23, count 0 2006.173.06:36:51.46#ibcon#wrote, iclass 23, count 0 2006.173.06:36:51.46#ibcon#about to read 3, iclass 23, count 0 2006.173.06:36:51.48#ibcon#read 3, iclass 23, count 0 2006.173.06:36:51.48#ibcon#about to read 4, iclass 23, count 0 2006.173.06:36:51.48#ibcon#read 4, iclass 23, count 0 2006.173.06:36:51.48#ibcon#about to read 5, iclass 23, count 0 2006.173.06:36:51.48#ibcon#read 5, iclass 23, count 0 2006.173.06:36:51.48#ibcon#about to read 6, iclass 23, count 0 2006.173.06:36:51.48#ibcon#read 6, iclass 23, count 0 2006.173.06:36:51.48#ibcon#end of sib2, iclass 23, count 0 2006.173.06:36:51.48#ibcon#*mode == 0, iclass 23, count 0 2006.173.06:36:51.48#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.06:36:51.48#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.06:36:51.48#ibcon#*before write, iclass 23, count 0 2006.173.06:36:51.48#ibcon#enter sib2, iclass 23, count 0 2006.173.06:36:51.48#ibcon#flushed, iclass 23, count 0 2006.173.06:36:51.48#ibcon#about to write, iclass 23, count 0 2006.173.06:36:51.48#ibcon#wrote, iclass 23, count 0 2006.173.06:36:51.48#ibcon#about to read 3, iclass 23, count 0 2006.173.06:36:51.52#ibcon#read 3, iclass 23, count 0 2006.173.06:36:51.52#ibcon#about to read 4, iclass 23, count 0 2006.173.06:36:51.52#ibcon#read 4, iclass 23, count 0 2006.173.06:36:51.52#ibcon#about to read 5, iclass 23, count 0 2006.173.06:36:51.52#ibcon#read 5, iclass 23, count 0 2006.173.06:36:51.52#ibcon#about to read 6, iclass 23, count 0 2006.173.06:36:51.52#ibcon#read 6, iclass 23, count 0 2006.173.06:36:51.52#ibcon#end of sib2, iclass 23, count 0 2006.173.06:36:51.52#ibcon#*after write, iclass 23, count 0 2006.173.06:36:51.52#ibcon#*before return 0, iclass 23, count 0 2006.173.06:36:51.52#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.06:36:51.52#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.06:36:51.52#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.06:36:51.52#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.06:36:51.52$vck44/va=2,6 2006.173.06:36:51.52#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.06:36:51.52#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.06:36:51.52#ibcon#ireg 11 cls_cnt 2 2006.173.06:36:51.52#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.06:36:51.58#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.06:36:51.58#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.06:36:51.58#ibcon#enter wrdev, iclass 25, count 2 2006.173.06:36:51.58#ibcon#first serial, iclass 25, count 2 2006.173.06:36:51.58#ibcon#enter sib2, iclass 25, count 2 2006.173.06:36:51.58#ibcon#flushed, iclass 25, count 2 2006.173.06:36:51.58#ibcon#about to write, iclass 25, count 2 2006.173.06:36:51.58#ibcon#wrote, iclass 25, count 2 2006.173.06:36:51.58#ibcon#about to read 3, iclass 25, count 2 2006.173.06:36:51.60#ibcon#read 3, iclass 25, count 2 2006.173.06:36:51.60#ibcon#about to read 4, iclass 25, count 2 2006.173.06:36:51.60#ibcon#read 4, iclass 25, count 2 2006.173.06:36:51.60#ibcon#about to read 5, iclass 25, count 2 2006.173.06:36:51.60#ibcon#read 5, iclass 25, count 2 2006.173.06:36:51.60#ibcon#about to read 6, iclass 25, count 2 2006.173.06:36:51.60#ibcon#read 6, iclass 25, count 2 2006.173.06:36:51.60#ibcon#end of sib2, iclass 25, count 2 2006.173.06:36:51.60#ibcon#*mode == 0, iclass 25, count 2 2006.173.06:36:51.60#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.06:36:51.60#ibcon#[25=AT02-06\r\n] 2006.173.06:36:51.60#ibcon#*before write, iclass 25, count 2 2006.173.06:36:51.60#ibcon#enter sib2, iclass 25, count 2 2006.173.06:36:51.60#ibcon#flushed, iclass 25, count 2 2006.173.06:36:51.60#ibcon#about to write, iclass 25, count 2 2006.173.06:36:51.60#ibcon#wrote, iclass 25, count 2 2006.173.06:36:51.60#ibcon#about to read 3, iclass 25, count 2 2006.173.06:36:51.63#ibcon#read 3, iclass 25, count 2 2006.173.06:36:51.63#ibcon#about to read 4, iclass 25, count 2 2006.173.06:36:51.63#ibcon#read 4, iclass 25, count 2 2006.173.06:36:51.63#ibcon#about to read 5, iclass 25, count 2 2006.173.06:36:51.63#ibcon#read 5, iclass 25, count 2 2006.173.06:36:51.63#ibcon#about to read 6, iclass 25, count 2 2006.173.06:36:51.63#ibcon#read 6, iclass 25, count 2 2006.173.06:36:51.63#ibcon#end of sib2, iclass 25, count 2 2006.173.06:36:51.63#ibcon#*after write, iclass 25, count 2 2006.173.06:36:51.63#ibcon#*before return 0, iclass 25, count 2 2006.173.06:36:51.63#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.06:36:51.63#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.06:36:51.63#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.06:36:51.63#ibcon#ireg 7 cls_cnt 0 2006.173.06:36:51.63#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.06:36:51.75#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.06:36:51.75#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.06:36:51.75#ibcon#enter wrdev, iclass 25, count 0 2006.173.06:36:51.75#ibcon#first serial, iclass 25, count 0 2006.173.06:36:51.75#ibcon#enter sib2, iclass 25, count 0 2006.173.06:36:51.75#ibcon#flushed, iclass 25, count 0 2006.173.06:36:51.75#ibcon#about to write, iclass 25, count 0 2006.173.06:36:51.75#ibcon#wrote, iclass 25, count 0 2006.173.06:36:51.75#ibcon#about to read 3, iclass 25, count 0 2006.173.06:36:51.77#ibcon#read 3, iclass 25, count 0 2006.173.06:36:51.77#ibcon#about to read 4, iclass 25, count 0 2006.173.06:36:51.77#ibcon#read 4, iclass 25, count 0 2006.173.06:36:51.77#ibcon#about to read 5, iclass 25, count 0 2006.173.06:36:51.77#ibcon#read 5, iclass 25, count 0 2006.173.06:36:51.77#ibcon#about to read 6, iclass 25, count 0 2006.173.06:36:51.77#ibcon#read 6, iclass 25, count 0 2006.173.06:36:51.77#ibcon#end of sib2, iclass 25, count 0 2006.173.06:36:51.77#ibcon#*mode == 0, iclass 25, count 0 2006.173.06:36:51.77#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.06:36:51.77#ibcon#[25=USB\r\n] 2006.173.06:36:51.77#ibcon#*before write, iclass 25, count 0 2006.173.06:36:51.77#ibcon#enter sib2, iclass 25, count 0 2006.173.06:36:51.77#ibcon#flushed, iclass 25, count 0 2006.173.06:36:51.77#ibcon#about to write, iclass 25, count 0 2006.173.06:36:51.77#ibcon#wrote, iclass 25, count 0 2006.173.06:36:51.77#ibcon#about to read 3, iclass 25, count 0 2006.173.06:36:51.80#ibcon#read 3, iclass 25, count 0 2006.173.06:36:51.80#ibcon#about to read 4, iclass 25, count 0 2006.173.06:36:51.80#ibcon#read 4, iclass 25, count 0 2006.173.06:36:51.80#ibcon#about to read 5, iclass 25, count 0 2006.173.06:36:51.80#ibcon#read 5, iclass 25, count 0 2006.173.06:36:51.80#ibcon#about to read 6, iclass 25, count 0 2006.173.06:36:51.80#ibcon#read 6, iclass 25, count 0 2006.173.06:36:51.80#ibcon#end of sib2, iclass 25, count 0 2006.173.06:36:51.80#ibcon#*after write, iclass 25, count 0 2006.173.06:36:51.80#ibcon#*before return 0, iclass 25, count 0 2006.173.06:36:51.80#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.06:36:51.80#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.06:36:51.80#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.06:36:51.80#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.06:36:51.80$vck44/valo=3,564.99 2006.173.06:36:51.80#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.06:36:51.80#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.06:36:51.80#ibcon#ireg 17 cls_cnt 0 2006.173.06:36:51.80#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.06:36:51.80#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.06:36:51.80#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.06:36:51.80#ibcon#enter wrdev, iclass 27, count 0 2006.173.06:36:51.80#ibcon#first serial, iclass 27, count 0 2006.173.06:36:51.80#ibcon#enter sib2, iclass 27, count 0 2006.173.06:36:51.80#ibcon#flushed, iclass 27, count 0 2006.173.06:36:51.80#ibcon#about to write, iclass 27, count 0 2006.173.06:36:51.80#ibcon#wrote, iclass 27, count 0 2006.173.06:36:51.81#ibcon#about to read 3, iclass 27, count 0 2006.173.06:36:51.82#ibcon#read 3, iclass 27, count 0 2006.173.06:36:51.82#ibcon#about to read 4, iclass 27, count 0 2006.173.06:36:51.82#ibcon#read 4, iclass 27, count 0 2006.173.06:36:51.82#ibcon#about to read 5, iclass 27, count 0 2006.173.06:36:51.82#ibcon#read 5, iclass 27, count 0 2006.173.06:36:51.82#ibcon#about to read 6, iclass 27, count 0 2006.173.06:36:51.82#ibcon#read 6, iclass 27, count 0 2006.173.06:36:51.82#ibcon#end of sib2, iclass 27, count 0 2006.173.06:36:51.82#ibcon#*mode == 0, iclass 27, count 0 2006.173.06:36:51.82#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.06:36:51.82#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.06:36:51.82#ibcon#*before write, iclass 27, count 0 2006.173.06:36:51.82#ibcon#enter sib2, iclass 27, count 0 2006.173.06:36:51.82#ibcon#flushed, iclass 27, count 0 2006.173.06:36:51.82#ibcon#about to write, iclass 27, count 0 2006.173.06:36:51.82#ibcon#wrote, iclass 27, count 0 2006.173.06:36:51.82#ibcon#about to read 3, iclass 27, count 0 2006.173.06:36:51.86#ibcon#read 3, iclass 27, count 0 2006.173.06:36:51.86#ibcon#about to read 4, iclass 27, count 0 2006.173.06:36:51.86#ibcon#read 4, iclass 27, count 0 2006.173.06:36:51.86#ibcon#about to read 5, iclass 27, count 0 2006.173.06:36:51.86#ibcon#read 5, iclass 27, count 0 2006.173.06:36:51.86#ibcon#about to read 6, iclass 27, count 0 2006.173.06:36:51.86#ibcon#read 6, iclass 27, count 0 2006.173.06:36:51.86#ibcon#end of sib2, iclass 27, count 0 2006.173.06:36:51.86#ibcon#*after write, iclass 27, count 0 2006.173.06:36:51.86#ibcon#*before return 0, iclass 27, count 0 2006.173.06:36:51.86#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.06:36:51.86#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.06:36:51.86#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.06:36:51.86#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.06:36:51.86$vck44/va=3,5 2006.173.06:36:51.86#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.06:36:51.86#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.06:36:51.86#ibcon#ireg 11 cls_cnt 2 2006.173.06:36:51.86#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.06:36:51.92#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.06:36:51.92#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.06:36:51.92#ibcon#enter wrdev, iclass 29, count 2 2006.173.06:36:51.92#ibcon#first serial, iclass 29, count 2 2006.173.06:36:51.92#ibcon#enter sib2, iclass 29, count 2 2006.173.06:36:51.92#ibcon#flushed, iclass 29, count 2 2006.173.06:36:51.92#ibcon#about to write, iclass 29, count 2 2006.173.06:36:51.92#ibcon#wrote, iclass 29, count 2 2006.173.06:36:51.92#ibcon#about to read 3, iclass 29, count 2 2006.173.06:36:51.94#ibcon#read 3, iclass 29, count 2 2006.173.06:36:51.94#ibcon#about to read 4, iclass 29, count 2 2006.173.06:36:51.94#ibcon#read 4, iclass 29, count 2 2006.173.06:36:51.94#ibcon#about to read 5, iclass 29, count 2 2006.173.06:36:51.94#ibcon#read 5, iclass 29, count 2 2006.173.06:36:51.94#ibcon#about to read 6, iclass 29, count 2 2006.173.06:36:51.94#ibcon#read 6, iclass 29, count 2 2006.173.06:36:51.94#ibcon#end of sib2, iclass 29, count 2 2006.173.06:36:51.94#ibcon#*mode == 0, iclass 29, count 2 2006.173.06:36:51.94#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.06:36:51.94#ibcon#[25=AT03-05\r\n] 2006.173.06:36:51.94#ibcon#*before write, iclass 29, count 2 2006.173.06:36:51.94#ibcon#enter sib2, iclass 29, count 2 2006.173.06:36:51.94#ibcon#flushed, iclass 29, count 2 2006.173.06:36:51.94#ibcon#about to write, iclass 29, count 2 2006.173.06:36:51.94#ibcon#wrote, iclass 29, count 2 2006.173.06:36:51.94#ibcon#about to read 3, iclass 29, count 2 2006.173.06:36:51.97#ibcon#read 3, iclass 29, count 2 2006.173.06:36:51.97#ibcon#about to read 4, iclass 29, count 2 2006.173.06:36:51.97#ibcon#read 4, iclass 29, count 2 2006.173.06:36:51.97#ibcon#about to read 5, iclass 29, count 2 2006.173.06:36:51.97#ibcon#read 5, iclass 29, count 2 2006.173.06:36:51.97#ibcon#about to read 6, iclass 29, count 2 2006.173.06:36:51.97#ibcon#read 6, iclass 29, count 2 2006.173.06:36:51.97#ibcon#end of sib2, iclass 29, count 2 2006.173.06:36:51.97#ibcon#*after write, iclass 29, count 2 2006.173.06:36:51.97#ibcon#*before return 0, iclass 29, count 2 2006.173.06:36:51.97#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.06:36:51.97#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.06:36:51.97#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.06:36:51.97#ibcon#ireg 7 cls_cnt 0 2006.173.06:36:51.97#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.06:36:52.09#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.06:36:52.09#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.06:36:52.09#ibcon#enter wrdev, iclass 29, count 0 2006.173.06:36:52.09#ibcon#first serial, iclass 29, count 0 2006.173.06:36:52.09#ibcon#enter sib2, iclass 29, count 0 2006.173.06:36:52.09#ibcon#flushed, iclass 29, count 0 2006.173.06:36:52.09#ibcon#about to write, iclass 29, count 0 2006.173.06:36:52.09#ibcon#wrote, iclass 29, count 0 2006.173.06:36:52.09#ibcon#about to read 3, iclass 29, count 0 2006.173.06:36:52.11#ibcon#read 3, iclass 29, count 0 2006.173.06:36:52.11#ibcon#about to read 4, iclass 29, count 0 2006.173.06:36:52.11#ibcon#read 4, iclass 29, count 0 2006.173.06:36:52.11#ibcon#about to read 5, iclass 29, count 0 2006.173.06:36:52.11#ibcon#read 5, iclass 29, count 0 2006.173.06:36:52.11#ibcon#about to read 6, iclass 29, count 0 2006.173.06:36:52.11#ibcon#read 6, iclass 29, count 0 2006.173.06:36:52.11#ibcon#end of sib2, iclass 29, count 0 2006.173.06:36:52.11#ibcon#*mode == 0, iclass 29, count 0 2006.173.06:36:52.11#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.06:36:52.11#ibcon#[25=USB\r\n] 2006.173.06:36:52.11#ibcon#*before write, iclass 29, count 0 2006.173.06:36:52.11#ibcon#enter sib2, iclass 29, count 0 2006.173.06:36:52.11#ibcon#flushed, iclass 29, count 0 2006.173.06:36:52.11#ibcon#about to write, iclass 29, count 0 2006.173.06:36:52.11#ibcon#wrote, iclass 29, count 0 2006.173.06:36:52.11#ibcon#about to read 3, iclass 29, count 0 2006.173.06:36:52.14#ibcon#read 3, iclass 29, count 0 2006.173.06:36:52.14#ibcon#about to read 4, iclass 29, count 0 2006.173.06:36:52.14#ibcon#read 4, iclass 29, count 0 2006.173.06:36:52.14#ibcon#about to read 5, iclass 29, count 0 2006.173.06:36:52.14#ibcon#read 5, iclass 29, count 0 2006.173.06:36:52.14#ibcon#about to read 6, iclass 29, count 0 2006.173.06:36:52.14#ibcon#read 6, iclass 29, count 0 2006.173.06:36:52.14#ibcon#end of sib2, iclass 29, count 0 2006.173.06:36:52.14#ibcon#*after write, iclass 29, count 0 2006.173.06:36:52.14#ibcon#*before return 0, iclass 29, count 0 2006.173.06:36:52.14#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.06:36:52.14#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.06:36:52.14#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.06:36:52.14#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.06:36:52.14$vck44/valo=4,624.99 2006.173.06:36:52.14#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.06:36:52.14#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.06:36:52.14#ibcon#ireg 17 cls_cnt 0 2006.173.06:36:52.14#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.06:36:52.14#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.06:36:52.14#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.06:36:52.14#ibcon#enter wrdev, iclass 31, count 0 2006.173.06:36:52.14#ibcon#first serial, iclass 31, count 0 2006.173.06:36:52.14#ibcon#enter sib2, iclass 31, count 0 2006.173.06:36:52.14#ibcon#flushed, iclass 31, count 0 2006.173.06:36:52.14#ibcon#about to write, iclass 31, count 0 2006.173.06:36:52.15#ibcon#wrote, iclass 31, count 0 2006.173.06:36:52.15#ibcon#about to read 3, iclass 31, count 0 2006.173.06:36:52.16#ibcon#read 3, iclass 31, count 0 2006.173.06:36:52.16#ibcon#about to read 4, iclass 31, count 0 2006.173.06:36:52.16#ibcon#read 4, iclass 31, count 0 2006.173.06:36:52.16#ibcon#about to read 5, iclass 31, count 0 2006.173.06:36:52.16#ibcon#read 5, iclass 31, count 0 2006.173.06:36:52.16#ibcon#about to read 6, iclass 31, count 0 2006.173.06:36:52.16#ibcon#read 6, iclass 31, count 0 2006.173.06:36:52.16#ibcon#end of sib2, iclass 31, count 0 2006.173.06:36:52.16#ibcon#*mode == 0, iclass 31, count 0 2006.173.06:36:52.16#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.06:36:52.16#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.06:36:52.16#ibcon#*before write, iclass 31, count 0 2006.173.06:36:52.16#ibcon#enter sib2, iclass 31, count 0 2006.173.06:36:52.16#ibcon#flushed, iclass 31, count 0 2006.173.06:36:52.16#ibcon#about to write, iclass 31, count 0 2006.173.06:36:52.16#ibcon#wrote, iclass 31, count 0 2006.173.06:36:52.16#ibcon#about to read 3, iclass 31, count 0 2006.173.06:36:52.20#ibcon#read 3, iclass 31, count 0 2006.173.06:36:52.20#ibcon#about to read 4, iclass 31, count 0 2006.173.06:36:52.20#ibcon#read 4, iclass 31, count 0 2006.173.06:36:52.20#ibcon#about to read 5, iclass 31, count 0 2006.173.06:36:52.20#ibcon#read 5, iclass 31, count 0 2006.173.06:36:52.20#ibcon#about to read 6, iclass 31, count 0 2006.173.06:36:52.20#ibcon#read 6, iclass 31, count 0 2006.173.06:36:52.20#ibcon#end of sib2, iclass 31, count 0 2006.173.06:36:52.20#ibcon#*after write, iclass 31, count 0 2006.173.06:36:52.20#ibcon#*before return 0, iclass 31, count 0 2006.173.06:36:52.20#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.06:36:52.20#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.06:36:52.20#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.06:36:52.20#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.06:36:52.20$vck44/va=4,6 2006.173.06:36:52.20#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.173.06:36:52.20#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.173.06:36:52.20#ibcon#ireg 11 cls_cnt 2 2006.173.06:36:52.20#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.06:36:52.26#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.06:36:52.26#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.06:36:52.26#ibcon#enter wrdev, iclass 33, count 2 2006.173.06:36:52.26#ibcon#first serial, iclass 33, count 2 2006.173.06:36:52.26#ibcon#enter sib2, iclass 33, count 2 2006.173.06:36:52.26#ibcon#flushed, iclass 33, count 2 2006.173.06:36:52.26#ibcon#about to write, iclass 33, count 2 2006.173.06:36:52.26#ibcon#wrote, iclass 33, count 2 2006.173.06:36:52.26#ibcon#about to read 3, iclass 33, count 2 2006.173.06:36:52.28#ibcon#read 3, iclass 33, count 2 2006.173.06:36:52.28#ibcon#about to read 4, iclass 33, count 2 2006.173.06:36:52.28#ibcon#read 4, iclass 33, count 2 2006.173.06:36:52.28#ibcon#about to read 5, iclass 33, count 2 2006.173.06:36:52.28#ibcon#read 5, iclass 33, count 2 2006.173.06:36:52.28#ibcon#about to read 6, iclass 33, count 2 2006.173.06:36:52.28#ibcon#read 6, iclass 33, count 2 2006.173.06:36:52.28#ibcon#end of sib2, iclass 33, count 2 2006.173.06:36:52.28#ibcon#*mode == 0, iclass 33, count 2 2006.173.06:36:52.28#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.173.06:36:52.28#ibcon#[25=AT04-06\r\n] 2006.173.06:36:52.28#ibcon#*before write, iclass 33, count 2 2006.173.06:36:52.28#ibcon#enter sib2, iclass 33, count 2 2006.173.06:36:52.28#ibcon#flushed, iclass 33, count 2 2006.173.06:36:52.28#ibcon#about to write, iclass 33, count 2 2006.173.06:36:52.28#ibcon#wrote, iclass 33, count 2 2006.173.06:36:52.28#ibcon#about to read 3, iclass 33, count 2 2006.173.06:36:52.31#ibcon#read 3, iclass 33, count 2 2006.173.06:36:52.31#ibcon#about to read 4, iclass 33, count 2 2006.173.06:36:52.31#ibcon#read 4, iclass 33, count 2 2006.173.06:36:52.31#ibcon#about to read 5, iclass 33, count 2 2006.173.06:36:52.31#ibcon#read 5, iclass 33, count 2 2006.173.06:36:52.31#ibcon#about to read 6, iclass 33, count 2 2006.173.06:36:52.31#ibcon#read 6, iclass 33, count 2 2006.173.06:36:52.31#ibcon#end of sib2, iclass 33, count 2 2006.173.06:36:52.31#ibcon#*after write, iclass 33, count 2 2006.173.06:36:52.31#ibcon#*before return 0, iclass 33, count 2 2006.173.06:36:52.31#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.06:36:52.31#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.173.06:36:52.31#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.173.06:36:52.31#ibcon#ireg 7 cls_cnt 0 2006.173.06:36:52.31#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.06:36:52.43#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.06:36:52.43#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.06:36:52.43#ibcon#enter wrdev, iclass 33, count 0 2006.173.06:36:52.43#ibcon#first serial, iclass 33, count 0 2006.173.06:36:52.43#ibcon#enter sib2, iclass 33, count 0 2006.173.06:36:52.43#ibcon#flushed, iclass 33, count 0 2006.173.06:36:52.43#ibcon#about to write, iclass 33, count 0 2006.173.06:36:52.43#ibcon#wrote, iclass 33, count 0 2006.173.06:36:52.43#ibcon#about to read 3, iclass 33, count 0 2006.173.06:36:52.45#ibcon#read 3, iclass 33, count 0 2006.173.06:36:52.45#ibcon#about to read 4, iclass 33, count 0 2006.173.06:36:52.45#ibcon#read 4, iclass 33, count 0 2006.173.06:36:52.45#ibcon#about to read 5, iclass 33, count 0 2006.173.06:36:52.45#ibcon#read 5, iclass 33, count 0 2006.173.06:36:52.45#ibcon#about to read 6, iclass 33, count 0 2006.173.06:36:52.45#ibcon#read 6, iclass 33, count 0 2006.173.06:36:52.45#ibcon#end of sib2, iclass 33, count 0 2006.173.06:36:52.45#ibcon#*mode == 0, iclass 33, count 0 2006.173.06:36:52.45#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.06:36:52.45#ibcon#[25=USB\r\n] 2006.173.06:36:52.45#ibcon#*before write, iclass 33, count 0 2006.173.06:36:52.45#ibcon#enter sib2, iclass 33, count 0 2006.173.06:36:52.45#ibcon#flushed, iclass 33, count 0 2006.173.06:36:52.45#ibcon#about to write, iclass 33, count 0 2006.173.06:36:52.45#ibcon#wrote, iclass 33, count 0 2006.173.06:36:52.45#ibcon#about to read 3, iclass 33, count 0 2006.173.06:36:52.48#ibcon#read 3, iclass 33, count 0 2006.173.06:36:52.48#ibcon#about to read 4, iclass 33, count 0 2006.173.06:36:52.48#ibcon#read 4, iclass 33, count 0 2006.173.06:36:52.48#ibcon#about to read 5, iclass 33, count 0 2006.173.06:36:52.48#ibcon#read 5, iclass 33, count 0 2006.173.06:36:52.48#ibcon#about to read 6, iclass 33, count 0 2006.173.06:36:52.48#ibcon#read 6, iclass 33, count 0 2006.173.06:36:52.48#ibcon#end of sib2, iclass 33, count 0 2006.173.06:36:52.48#ibcon#*after write, iclass 33, count 0 2006.173.06:36:52.48#ibcon#*before return 0, iclass 33, count 0 2006.173.06:36:52.48#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.06:36:52.48#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.173.06:36:52.48#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.06:36:52.48#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.06:36:52.48$vck44/valo=5,734.99 2006.173.06:36:52.48#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.06:36:52.48#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.06:36:52.48#ibcon#ireg 17 cls_cnt 0 2006.173.06:36:52.48#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.06:36:52.48#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.06:36:52.48#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.06:36:52.48#ibcon#enter wrdev, iclass 35, count 0 2006.173.06:36:52.48#ibcon#first serial, iclass 35, count 0 2006.173.06:36:52.48#ibcon#enter sib2, iclass 35, count 0 2006.173.06:36:52.48#ibcon#flushed, iclass 35, count 0 2006.173.06:36:52.48#ibcon#about to write, iclass 35, count 0 2006.173.06:36:52.48#ibcon#wrote, iclass 35, count 0 2006.173.06:36:52.48#ibcon#about to read 3, iclass 35, count 0 2006.173.06:36:52.50#ibcon#read 3, iclass 35, count 0 2006.173.06:36:52.50#ibcon#about to read 4, iclass 35, count 0 2006.173.06:36:52.50#ibcon#read 4, iclass 35, count 0 2006.173.06:36:52.50#ibcon#about to read 5, iclass 35, count 0 2006.173.06:36:52.50#ibcon#read 5, iclass 35, count 0 2006.173.06:36:52.50#ibcon#about to read 6, iclass 35, count 0 2006.173.06:36:52.50#ibcon#read 6, iclass 35, count 0 2006.173.06:36:52.50#ibcon#end of sib2, iclass 35, count 0 2006.173.06:36:52.50#ibcon#*mode == 0, iclass 35, count 0 2006.173.06:36:52.50#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.06:36:52.50#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.06:36:52.50#ibcon#*before write, iclass 35, count 0 2006.173.06:36:52.50#ibcon#enter sib2, iclass 35, count 0 2006.173.06:36:52.50#ibcon#flushed, iclass 35, count 0 2006.173.06:36:52.50#ibcon#about to write, iclass 35, count 0 2006.173.06:36:52.50#ibcon#wrote, iclass 35, count 0 2006.173.06:36:52.50#ibcon#about to read 3, iclass 35, count 0 2006.173.06:36:52.54#ibcon#read 3, iclass 35, count 0 2006.173.06:36:52.54#ibcon#about to read 4, iclass 35, count 0 2006.173.06:36:52.54#ibcon#read 4, iclass 35, count 0 2006.173.06:36:52.54#ibcon#about to read 5, iclass 35, count 0 2006.173.06:36:52.54#ibcon#read 5, iclass 35, count 0 2006.173.06:36:52.54#ibcon#about to read 6, iclass 35, count 0 2006.173.06:36:52.54#ibcon#read 6, iclass 35, count 0 2006.173.06:36:52.54#ibcon#end of sib2, iclass 35, count 0 2006.173.06:36:52.54#ibcon#*after write, iclass 35, count 0 2006.173.06:36:52.54#ibcon#*before return 0, iclass 35, count 0 2006.173.06:36:52.54#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.06:36:52.54#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.06:36:52.54#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.06:36:52.54#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.06:36:52.54$vck44/va=5,4 2006.173.06:36:52.54#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.173.06:36:52.54#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.173.06:36:52.54#ibcon#ireg 11 cls_cnt 2 2006.173.06:36:52.54#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.06:36:52.60#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.06:36:52.60#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.06:36:52.60#ibcon#enter wrdev, iclass 37, count 2 2006.173.06:36:52.60#ibcon#first serial, iclass 37, count 2 2006.173.06:36:52.60#ibcon#enter sib2, iclass 37, count 2 2006.173.06:36:52.60#ibcon#flushed, iclass 37, count 2 2006.173.06:36:52.60#ibcon#about to write, iclass 37, count 2 2006.173.06:36:52.60#ibcon#wrote, iclass 37, count 2 2006.173.06:36:52.60#ibcon#about to read 3, iclass 37, count 2 2006.173.06:36:52.62#ibcon#read 3, iclass 37, count 2 2006.173.06:36:52.62#ibcon#about to read 4, iclass 37, count 2 2006.173.06:36:52.62#ibcon#read 4, iclass 37, count 2 2006.173.06:36:52.62#ibcon#about to read 5, iclass 37, count 2 2006.173.06:36:52.62#ibcon#read 5, iclass 37, count 2 2006.173.06:36:52.62#ibcon#about to read 6, iclass 37, count 2 2006.173.06:36:52.62#ibcon#read 6, iclass 37, count 2 2006.173.06:36:52.62#ibcon#end of sib2, iclass 37, count 2 2006.173.06:36:52.62#ibcon#*mode == 0, iclass 37, count 2 2006.173.06:36:52.62#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.173.06:36:52.62#ibcon#[25=AT05-04\r\n] 2006.173.06:36:52.62#ibcon#*before write, iclass 37, count 2 2006.173.06:36:52.62#ibcon#enter sib2, iclass 37, count 2 2006.173.06:36:52.62#ibcon#flushed, iclass 37, count 2 2006.173.06:36:52.62#ibcon#about to write, iclass 37, count 2 2006.173.06:36:52.62#ibcon#wrote, iclass 37, count 2 2006.173.06:36:52.62#ibcon#about to read 3, iclass 37, count 2 2006.173.06:36:52.65#ibcon#read 3, iclass 37, count 2 2006.173.06:36:52.65#ibcon#about to read 4, iclass 37, count 2 2006.173.06:36:52.65#ibcon#read 4, iclass 37, count 2 2006.173.06:36:52.65#ibcon#about to read 5, iclass 37, count 2 2006.173.06:36:52.65#ibcon#read 5, iclass 37, count 2 2006.173.06:36:52.65#ibcon#about to read 6, iclass 37, count 2 2006.173.06:36:52.65#ibcon#read 6, iclass 37, count 2 2006.173.06:36:52.65#ibcon#end of sib2, iclass 37, count 2 2006.173.06:36:52.65#ibcon#*after write, iclass 37, count 2 2006.173.06:36:52.65#ibcon#*before return 0, iclass 37, count 2 2006.173.06:36:52.65#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.06:36:52.65#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.173.06:36:52.65#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.173.06:36:52.65#ibcon#ireg 7 cls_cnt 0 2006.173.06:36:52.65#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.06:36:52.77#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.06:36:52.77#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.06:36:52.77#ibcon#enter wrdev, iclass 37, count 0 2006.173.06:36:52.77#ibcon#first serial, iclass 37, count 0 2006.173.06:36:52.77#ibcon#enter sib2, iclass 37, count 0 2006.173.06:36:52.77#ibcon#flushed, iclass 37, count 0 2006.173.06:36:52.77#ibcon#about to write, iclass 37, count 0 2006.173.06:36:52.77#ibcon#wrote, iclass 37, count 0 2006.173.06:36:52.77#ibcon#about to read 3, iclass 37, count 0 2006.173.06:36:52.79#ibcon#read 3, iclass 37, count 0 2006.173.06:36:52.79#ibcon#about to read 4, iclass 37, count 0 2006.173.06:36:52.79#ibcon#read 4, iclass 37, count 0 2006.173.06:36:52.79#ibcon#about to read 5, iclass 37, count 0 2006.173.06:36:52.79#ibcon#read 5, iclass 37, count 0 2006.173.06:36:52.79#ibcon#about to read 6, iclass 37, count 0 2006.173.06:36:52.79#ibcon#read 6, iclass 37, count 0 2006.173.06:36:52.79#ibcon#end of sib2, iclass 37, count 0 2006.173.06:36:52.79#ibcon#*mode == 0, iclass 37, count 0 2006.173.06:36:52.79#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.06:36:52.79#ibcon#[25=USB\r\n] 2006.173.06:36:52.79#ibcon#*before write, iclass 37, count 0 2006.173.06:36:52.79#ibcon#enter sib2, iclass 37, count 0 2006.173.06:36:52.79#ibcon#flushed, iclass 37, count 0 2006.173.06:36:52.79#ibcon#about to write, iclass 37, count 0 2006.173.06:36:52.79#ibcon#wrote, iclass 37, count 0 2006.173.06:36:52.79#ibcon#about to read 3, iclass 37, count 0 2006.173.06:36:52.82#ibcon#read 3, iclass 37, count 0 2006.173.06:36:52.82#ibcon#about to read 4, iclass 37, count 0 2006.173.06:36:52.82#ibcon#read 4, iclass 37, count 0 2006.173.06:36:52.82#ibcon#about to read 5, iclass 37, count 0 2006.173.06:36:52.82#ibcon#read 5, iclass 37, count 0 2006.173.06:36:52.82#ibcon#about to read 6, iclass 37, count 0 2006.173.06:36:52.82#ibcon#read 6, iclass 37, count 0 2006.173.06:36:52.82#ibcon#end of sib2, iclass 37, count 0 2006.173.06:36:52.82#ibcon#*after write, iclass 37, count 0 2006.173.06:36:52.82#ibcon#*before return 0, iclass 37, count 0 2006.173.06:36:52.82#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.06:36:52.82#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.173.06:36:52.82#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.06:36:52.82#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.06:36:52.82$vck44/valo=6,814.99 2006.173.06:36:52.82#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.06:36:52.82#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.06:36:52.82#ibcon#ireg 17 cls_cnt 0 2006.173.06:36:52.82#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.06:36:52.82#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.06:36:52.82#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.06:36:52.82#ibcon#enter wrdev, iclass 39, count 0 2006.173.06:36:52.82#ibcon#first serial, iclass 39, count 0 2006.173.06:36:52.82#ibcon#enter sib2, iclass 39, count 0 2006.173.06:36:52.82#ibcon#flushed, iclass 39, count 0 2006.173.06:36:52.82#ibcon#about to write, iclass 39, count 0 2006.173.06:36:52.82#ibcon#wrote, iclass 39, count 0 2006.173.06:36:52.82#ibcon#about to read 3, iclass 39, count 0 2006.173.06:36:52.84#ibcon#read 3, iclass 39, count 0 2006.173.06:36:52.84#ibcon#about to read 4, iclass 39, count 0 2006.173.06:36:52.84#ibcon#read 4, iclass 39, count 0 2006.173.06:36:52.84#ibcon#about to read 5, iclass 39, count 0 2006.173.06:36:52.84#ibcon#read 5, iclass 39, count 0 2006.173.06:36:52.84#ibcon#about to read 6, iclass 39, count 0 2006.173.06:36:52.84#ibcon#read 6, iclass 39, count 0 2006.173.06:36:52.84#ibcon#end of sib2, iclass 39, count 0 2006.173.06:36:52.84#ibcon#*mode == 0, iclass 39, count 0 2006.173.06:36:52.84#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.06:36:52.84#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.06:36:52.84#ibcon#*before write, iclass 39, count 0 2006.173.06:36:52.84#ibcon#enter sib2, iclass 39, count 0 2006.173.06:36:52.84#ibcon#flushed, iclass 39, count 0 2006.173.06:36:52.84#ibcon#about to write, iclass 39, count 0 2006.173.06:36:52.84#ibcon#wrote, iclass 39, count 0 2006.173.06:36:52.84#ibcon#about to read 3, iclass 39, count 0 2006.173.06:36:52.88#ibcon#read 3, iclass 39, count 0 2006.173.06:36:52.88#ibcon#about to read 4, iclass 39, count 0 2006.173.06:36:52.88#ibcon#read 4, iclass 39, count 0 2006.173.06:36:52.88#ibcon#about to read 5, iclass 39, count 0 2006.173.06:36:52.88#ibcon#read 5, iclass 39, count 0 2006.173.06:36:52.88#ibcon#about to read 6, iclass 39, count 0 2006.173.06:36:52.88#ibcon#read 6, iclass 39, count 0 2006.173.06:36:52.88#ibcon#end of sib2, iclass 39, count 0 2006.173.06:36:52.88#ibcon#*after write, iclass 39, count 0 2006.173.06:36:52.88#ibcon#*before return 0, iclass 39, count 0 2006.173.06:36:52.88#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.06:36:52.88#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.06:36:52.88#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.06:36:52.88#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.06:36:52.88$vck44/va=6,3 2006.173.06:36:52.88#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.06:36:52.88#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.06:36:52.88#ibcon#ireg 11 cls_cnt 2 2006.173.06:36:52.88#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.06:36:52.94#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.06:36:52.94#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.06:36:52.94#ibcon#enter wrdev, iclass 3, count 2 2006.173.06:36:52.94#ibcon#first serial, iclass 3, count 2 2006.173.06:36:52.94#ibcon#enter sib2, iclass 3, count 2 2006.173.06:36:52.94#ibcon#flushed, iclass 3, count 2 2006.173.06:36:52.94#ibcon#about to write, iclass 3, count 2 2006.173.06:36:52.94#ibcon#wrote, iclass 3, count 2 2006.173.06:36:52.94#ibcon#about to read 3, iclass 3, count 2 2006.173.06:36:52.96#ibcon#read 3, iclass 3, count 2 2006.173.06:36:52.96#ibcon#about to read 4, iclass 3, count 2 2006.173.06:36:52.96#ibcon#read 4, iclass 3, count 2 2006.173.06:36:52.96#ibcon#about to read 5, iclass 3, count 2 2006.173.06:36:52.96#ibcon#read 5, iclass 3, count 2 2006.173.06:36:52.96#ibcon#about to read 6, iclass 3, count 2 2006.173.06:36:52.96#ibcon#read 6, iclass 3, count 2 2006.173.06:36:52.96#ibcon#end of sib2, iclass 3, count 2 2006.173.06:36:52.96#ibcon#*mode == 0, iclass 3, count 2 2006.173.06:36:52.96#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.06:36:52.96#ibcon#[25=AT06-03\r\n] 2006.173.06:36:52.96#ibcon#*before write, iclass 3, count 2 2006.173.06:36:52.96#ibcon#enter sib2, iclass 3, count 2 2006.173.06:36:52.96#ibcon#flushed, iclass 3, count 2 2006.173.06:36:52.96#ibcon#about to write, iclass 3, count 2 2006.173.06:36:52.96#ibcon#wrote, iclass 3, count 2 2006.173.06:36:52.96#ibcon#about to read 3, iclass 3, count 2 2006.173.06:36:52.99#ibcon#read 3, iclass 3, count 2 2006.173.06:36:52.99#ibcon#about to read 4, iclass 3, count 2 2006.173.06:36:52.99#ibcon#read 4, iclass 3, count 2 2006.173.06:36:52.99#ibcon#about to read 5, iclass 3, count 2 2006.173.06:36:52.99#ibcon#read 5, iclass 3, count 2 2006.173.06:36:52.99#ibcon#about to read 6, iclass 3, count 2 2006.173.06:36:52.99#ibcon#read 6, iclass 3, count 2 2006.173.06:36:52.99#ibcon#end of sib2, iclass 3, count 2 2006.173.06:36:52.99#ibcon#*after write, iclass 3, count 2 2006.173.06:36:52.99#ibcon#*before return 0, iclass 3, count 2 2006.173.06:36:52.99#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.06:36:52.99#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.06:36:52.99#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.06:36:52.99#ibcon#ireg 7 cls_cnt 0 2006.173.06:36:52.99#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.06:36:53.11#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.06:36:53.11#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.06:36:53.11#ibcon#enter wrdev, iclass 3, count 0 2006.173.06:36:53.11#ibcon#first serial, iclass 3, count 0 2006.173.06:36:53.11#ibcon#enter sib2, iclass 3, count 0 2006.173.06:36:53.11#ibcon#flushed, iclass 3, count 0 2006.173.06:36:53.11#ibcon#about to write, iclass 3, count 0 2006.173.06:36:53.11#ibcon#wrote, iclass 3, count 0 2006.173.06:36:53.11#ibcon#about to read 3, iclass 3, count 0 2006.173.06:36:53.13#ibcon#read 3, iclass 3, count 0 2006.173.06:36:53.13#ibcon#about to read 4, iclass 3, count 0 2006.173.06:36:53.13#ibcon#read 4, iclass 3, count 0 2006.173.06:36:53.13#ibcon#about to read 5, iclass 3, count 0 2006.173.06:36:53.13#ibcon#read 5, iclass 3, count 0 2006.173.06:36:53.13#ibcon#about to read 6, iclass 3, count 0 2006.173.06:36:53.13#ibcon#read 6, iclass 3, count 0 2006.173.06:36:53.13#ibcon#end of sib2, iclass 3, count 0 2006.173.06:36:53.13#ibcon#*mode == 0, iclass 3, count 0 2006.173.06:36:53.13#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.06:36:53.13#ibcon#[25=USB\r\n] 2006.173.06:36:53.13#ibcon#*before write, iclass 3, count 0 2006.173.06:36:53.13#ibcon#enter sib2, iclass 3, count 0 2006.173.06:36:53.13#ibcon#flushed, iclass 3, count 0 2006.173.06:36:53.13#ibcon#about to write, iclass 3, count 0 2006.173.06:36:53.13#ibcon#wrote, iclass 3, count 0 2006.173.06:36:53.13#ibcon#about to read 3, iclass 3, count 0 2006.173.06:36:53.16#ibcon#read 3, iclass 3, count 0 2006.173.06:36:53.16#ibcon#about to read 4, iclass 3, count 0 2006.173.06:36:53.16#ibcon#read 4, iclass 3, count 0 2006.173.06:36:53.16#ibcon#about to read 5, iclass 3, count 0 2006.173.06:36:53.16#ibcon#read 5, iclass 3, count 0 2006.173.06:36:53.16#ibcon#about to read 6, iclass 3, count 0 2006.173.06:36:53.16#ibcon#read 6, iclass 3, count 0 2006.173.06:36:53.16#ibcon#end of sib2, iclass 3, count 0 2006.173.06:36:53.16#ibcon#*after write, iclass 3, count 0 2006.173.06:36:53.16#ibcon#*before return 0, iclass 3, count 0 2006.173.06:36:53.16#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.06:36:53.16#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.06:36:53.16#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.06:36:53.16#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.06:36:53.16$vck44/valo=7,864.99 2006.173.06:36:53.16#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.06:36:53.16#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.06:36:53.16#ibcon#ireg 17 cls_cnt 0 2006.173.06:36:53.16#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.06:36:53.16#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.06:36:53.16#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.06:36:53.16#ibcon#enter wrdev, iclass 5, count 0 2006.173.06:36:53.16#ibcon#first serial, iclass 5, count 0 2006.173.06:36:53.16#ibcon#enter sib2, iclass 5, count 0 2006.173.06:36:53.16#ibcon#flushed, iclass 5, count 0 2006.173.06:36:53.16#ibcon#about to write, iclass 5, count 0 2006.173.06:36:53.16#ibcon#wrote, iclass 5, count 0 2006.173.06:36:53.16#ibcon#about to read 3, iclass 5, count 0 2006.173.06:36:53.18#ibcon#read 3, iclass 5, count 0 2006.173.06:36:53.18#ibcon#about to read 4, iclass 5, count 0 2006.173.06:36:53.18#ibcon#read 4, iclass 5, count 0 2006.173.06:36:53.18#ibcon#about to read 5, iclass 5, count 0 2006.173.06:36:53.18#ibcon#read 5, iclass 5, count 0 2006.173.06:36:53.18#ibcon#about to read 6, iclass 5, count 0 2006.173.06:36:53.18#ibcon#read 6, iclass 5, count 0 2006.173.06:36:53.18#ibcon#end of sib2, iclass 5, count 0 2006.173.06:36:53.18#ibcon#*mode == 0, iclass 5, count 0 2006.173.06:36:53.18#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.06:36:53.18#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.06:36:53.18#ibcon#*before write, iclass 5, count 0 2006.173.06:36:53.18#ibcon#enter sib2, iclass 5, count 0 2006.173.06:36:53.18#ibcon#flushed, iclass 5, count 0 2006.173.06:36:53.18#ibcon#about to write, iclass 5, count 0 2006.173.06:36:53.18#ibcon#wrote, iclass 5, count 0 2006.173.06:36:53.18#ibcon#about to read 3, iclass 5, count 0 2006.173.06:36:53.22#ibcon#read 3, iclass 5, count 0 2006.173.06:36:53.22#ibcon#about to read 4, iclass 5, count 0 2006.173.06:36:53.22#ibcon#read 4, iclass 5, count 0 2006.173.06:36:53.22#ibcon#about to read 5, iclass 5, count 0 2006.173.06:36:53.22#ibcon#read 5, iclass 5, count 0 2006.173.06:36:53.22#ibcon#about to read 6, iclass 5, count 0 2006.173.06:36:53.22#ibcon#read 6, iclass 5, count 0 2006.173.06:36:53.22#ibcon#end of sib2, iclass 5, count 0 2006.173.06:36:53.22#ibcon#*after write, iclass 5, count 0 2006.173.06:36:53.22#ibcon#*before return 0, iclass 5, count 0 2006.173.06:36:53.22#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.06:36:53.22#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.06:36:53.22#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.06:36:53.22#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.06:36:53.22$vck44/va=7,4 2006.173.06:36:53.22#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.173.06:36:53.22#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.173.06:36:53.22#ibcon#ireg 11 cls_cnt 2 2006.173.06:36:53.22#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.06:36:53.28#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.06:36:53.28#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.06:36:53.28#ibcon#enter wrdev, iclass 7, count 2 2006.173.06:36:53.28#ibcon#first serial, iclass 7, count 2 2006.173.06:36:53.28#ibcon#enter sib2, iclass 7, count 2 2006.173.06:36:53.28#ibcon#flushed, iclass 7, count 2 2006.173.06:36:53.28#ibcon#about to write, iclass 7, count 2 2006.173.06:36:53.28#ibcon#wrote, iclass 7, count 2 2006.173.06:36:53.28#ibcon#about to read 3, iclass 7, count 2 2006.173.06:36:53.30#ibcon#read 3, iclass 7, count 2 2006.173.06:36:53.30#ibcon#about to read 4, iclass 7, count 2 2006.173.06:36:53.30#ibcon#read 4, iclass 7, count 2 2006.173.06:36:53.30#ibcon#about to read 5, iclass 7, count 2 2006.173.06:36:53.30#ibcon#read 5, iclass 7, count 2 2006.173.06:36:53.30#ibcon#about to read 6, iclass 7, count 2 2006.173.06:36:53.30#ibcon#read 6, iclass 7, count 2 2006.173.06:36:53.30#ibcon#end of sib2, iclass 7, count 2 2006.173.06:36:53.30#ibcon#*mode == 0, iclass 7, count 2 2006.173.06:36:53.30#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.173.06:36:53.30#ibcon#[25=AT07-04\r\n] 2006.173.06:36:53.30#ibcon#*before write, iclass 7, count 2 2006.173.06:36:53.30#ibcon#enter sib2, iclass 7, count 2 2006.173.06:36:53.30#ibcon#flushed, iclass 7, count 2 2006.173.06:36:53.30#ibcon#about to write, iclass 7, count 2 2006.173.06:36:53.30#ibcon#wrote, iclass 7, count 2 2006.173.06:36:53.30#ibcon#about to read 3, iclass 7, count 2 2006.173.06:36:53.33#ibcon#read 3, iclass 7, count 2 2006.173.06:36:53.33#ibcon#about to read 4, iclass 7, count 2 2006.173.06:36:53.33#ibcon#read 4, iclass 7, count 2 2006.173.06:36:53.33#ibcon#about to read 5, iclass 7, count 2 2006.173.06:36:53.33#ibcon#read 5, iclass 7, count 2 2006.173.06:36:53.33#ibcon#about to read 6, iclass 7, count 2 2006.173.06:36:53.33#ibcon#read 6, iclass 7, count 2 2006.173.06:36:53.33#ibcon#end of sib2, iclass 7, count 2 2006.173.06:36:53.33#ibcon#*after write, iclass 7, count 2 2006.173.06:36:53.33#ibcon#*before return 0, iclass 7, count 2 2006.173.06:36:53.33#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.06:36:53.33#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.173.06:36:53.33#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.173.06:36:53.33#ibcon#ireg 7 cls_cnt 0 2006.173.06:36:53.33#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.06:36:53.45#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.06:36:53.45#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.06:36:53.45#ibcon#enter wrdev, iclass 7, count 0 2006.173.06:36:53.45#ibcon#first serial, iclass 7, count 0 2006.173.06:36:53.45#ibcon#enter sib2, iclass 7, count 0 2006.173.06:36:53.45#ibcon#flushed, iclass 7, count 0 2006.173.06:36:53.45#ibcon#about to write, iclass 7, count 0 2006.173.06:36:53.45#ibcon#wrote, iclass 7, count 0 2006.173.06:36:53.45#ibcon#about to read 3, iclass 7, count 0 2006.173.06:36:53.47#ibcon#read 3, iclass 7, count 0 2006.173.06:36:53.47#ibcon#about to read 4, iclass 7, count 0 2006.173.06:36:53.47#ibcon#read 4, iclass 7, count 0 2006.173.06:36:53.47#ibcon#about to read 5, iclass 7, count 0 2006.173.06:36:53.47#ibcon#read 5, iclass 7, count 0 2006.173.06:36:53.47#ibcon#about to read 6, iclass 7, count 0 2006.173.06:36:53.47#ibcon#read 6, iclass 7, count 0 2006.173.06:36:53.47#ibcon#end of sib2, iclass 7, count 0 2006.173.06:36:53.47#ibcon#*mode == 0, iclass 7, count 0 2006.173.06:36:53.47#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.06:36:53.47#ibcon#[25=USB\r\n] 2006.173.06:36:53.47#ibcon#*before write, iclass 7, count 0 2006.173.06:36:53.47#ibcon#enter sib2, iclass 7, count 0 2006.173.06:36:53.47#ibcon#flushed, iclass 7, count 0 2006.173.06:36:53.47#ibcon#about to write, iclass 7, count 0 2006.173.06:36:53.47#ibcon#wrote, iclass 7, count 0 2006.173.06:36:53.47#ibcon#about to read 3, iclass 7, count 0 2006.173.06:36:53.50#ibcon#read 3, iclass 7, count 0 2006.173.06:36:53.50#ibcon#about to read 4, iclass 7, count 0 2006.173.06:36:53.50#ibcon#read 4, iclass 7, count 0 2006.173.06:36:53.50#ibcon#about to read 5, iclass 7, count 0 2006.173.06:36:53.50#ibcon#read 5, iclass 7, count 0 2006.173.06:36:53.50#ibcon#about to read 6, iclass 7, count 0 2006.173.06:36:53.50#ibcon#read 6, iclass 7, count 0 2006.173.06:36:53.50#ibcon#end of sib2, iclass 7, count 0 2006.173.06:36:53.50#ibcon#*after write, iclass 7, count 0 2006.173.06:36:53.50#ibcon#*before return 0, iclass 7, count 0 2006.173.06:36:53.50#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.06:36:53.50#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.173.06:36:53.50#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.06:36:53.50#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.06:36:53.50$vck44/valo=8,884.99 2006.173.06:36:53.50#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.06:36:53.50#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.06:36:53.50#ibcon#ireg 17 cls_cnt 0 2006.173.06:36:53.50#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.06:36:53.50#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.06:36:53.50#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.06:36:53.50#ibcon#enter wrdev, iclass 11, count 0 2006.173.06:36:53.50#ibcon#first serial, iclass 11, count 0 2006.173.06:36:53.50#ibcon#enter sib2, iclass 11, count 0 2006.173.06:36:53.50#ibcon#flushed, iclass 11, count 0 2006.173.06:36:53.50#ibcon#about to write, iclass 11, count 0 2006.173.06:36:53.51#ibcon#wrote, iclass 11, count 0 2006.173.06:36:53.51#ibcon#about to read 3, iclass 11, count 0 2006.173.06:36:53.52#ibcon#read 3, iclass 11, count 0 2006.173.06:36:53.52#ibcon#about to read 4, iclass 11, count 0 2006.173.06:36:53.52#ibcon#read 4, iclass 11, count 0 2006.173.06:36:53.52#ibcon#about to read 5, iclass 11, count 0 2006.173.06:36:53.52#ibcon#read 5, iclass 11, count 0 2006.173.06:36:53.52#ibcon#about to read 6, iclass 11, count 0 2006.173.06:36:53.52#ibcon#read 6, iclass 11, count 0 2006.173.06:36:53.52#ibcon#end of sib2, iclass 11, count 0 2006.173.06:36:53.52#ibcon#*mode == 0, iclass 11, count 0 2006.173.06:36:53.52#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.06:36:53.52#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.06:36:53.52#ibcon#*before write, iclass 11, count 0 2006.173.06:36:53.52#ibcon#enter sib2, iclass 11, count 0 2006.173.06:36:53.52#ibcon#flushed, iclass 11, count 0 2006.173.06:36:53.52#ibcon#about to write, iclass 11, count 0 2006.173.06:36:53.52#ibcon#wrote, iclass 11, count 0 2006.173.06:36:53.52#ibcon#about to read 3, iclass 11, count 0 2006.173.06:36:53.56#ibcon#read 3, iclass 11, count 0 2006.173.06:36:53.56#ibcon#about to read 4, iclass 11, count 0 2006.173.06:36:53.56#ibcon#read 4, iclass 11, count 0 2006.173.06:36:53.56#ibcon#about to read 5, iclass 11, count 0 2006.173.06:36:53.56#ibcon#read 5, iclass 11, count 0 2006.173.06:36:53.56#ibcon#about to read 6, iclass 11, count 0 2006.173.06:36:53.56#ibcon#read 6, iclass 11, count 0 2006.173.06:36:53.56#ibcon#end of sib2, iclass 11, count 0 2006.173.06:36:53.56#ibcon#*after write, iclass 11, count 0 2006.173.06:36:53.56#ibcon#*before return 0, iclass 11, count 0 2006.173.06:36:53.56#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.06:36:53.56#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.06:36:53.56#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.06:36:53.56#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.06:36:53.56$vck44/va=8,4 2006.173.06:36:53.56#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.173.06:36:53.56#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.173.06:36:53.56#ibcon#ireg 11 cls_cnt 2 2006.173.06:36:53.56#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.06:36:53.62#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.06:36:53.62#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.06:36:53.62#ibcon#enter wrdev, iclass 13, count 2 2006.173.06:36:53.62#ibcon#first serial, iclass 13, count 2 2006.173.06:36:53.62#ibcon#enter sib2, iclass 13, count 2 2006.173.06:36:53.62#ibcon#flushed, iclass 13, count 2 2006.173.06:36:53.62#ibcon#about to write, iclass 13, count 2 2006.173.06:36:53.62#ibcon#wrote, iclass 13, count 2 2006.173.06:36:53.62#ibcon#about to read 3, iclass 13, count 2 2006.173.06:36:53.64#ibcon#read 3, iclass 13, count 2 2006.173.06:36:53.64#ibcon#about to read 4, iclass 13, count 2 2006.173.06:36:53.64#ibcon#read 4, iclass 13, count 2 2006.173.06:36:53.64#ibcon#about to read 5, iclass 13, count 2 2006.173.06:36:53.64#ibcon#read 5, iclass 13, count 2 2006.173.06:36:53.64#ibcon#about to read 6, iclass 13, count 2 2006.173.06:36:53.64#ibcon#read 6, iclass 13, count 2 2006.173.06:36:53.64#ibcon#end of sib2, iclass 13, count 2 2006.173.06:36:53.64#ibcon#*mode == 0, iclass 13, count 2 2006.173.06:36:53.64#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.173.06:36:53.64#ibcon#[25=AT08-04\r\n] 2006.173.06:36:53.64#ibcon#*before write, iclass 13, count 2 2006.173.06:36:53.64#ibcon#enter sib2, iclass 13, count 2 2006.173.06:36:53.64#ibcon#flushed, iclass 13, count 2 2006.173.06:36:53.64#ibcon#about to write, iclass 13, count 2 2006.173.06:36:53.64#ibcon#wrote, iclass 13, count 2 2006.173.06:36:53.64#ibcon#about to read 3, iclass 13, count 2 2006.173.06:36:53.67#ibcon#read 3, iclass 13, count 2 2006.173.06:36:53.67#ibcon#about to read 4, iclass 13, count 2 2006.173.06:36:53.67#ibcon#read 4, iclass 13, count 2 2006.173.06:36:53.67#ibcon#about to read 5, iclass 13, count 2 2006.173.06:36:53.67#ibcon#read 5, iclass 13, count 2 2006.173.06:36:53.67#ibcon#about to read 6, iclass 13, count 2 2006.173.06:36:53.67#ibcon#read 6, iclass 13, count 2 2006.173.06:36:53.67#ibcon#end of sib2, iclass 13, count 2 2006.173.06:36:53.67#ibcon#*after write, iclass 13, count 2 2006.173.06:36:53.67#ibcon#*before return 0, iclass 13, count 2 2006.173.06:36:53.67#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.06:36:53.67#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.173.06:36:53.67#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.173.06:36:53.67#ibcon#ireg 7 cls_cnt 0 2006.173.06:36:53.67#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.06:36:53.79#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.06:36:53.79#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.06:36:53.79#ibcon#enter wrdev, iclass 13, count 0 2006.173.06:36:53.79#ibcon#first serial, iclass 13, count 0 2006.173.06:36:53.79#ibcon#enter sib2, iclass 13, count 0 2006.173.06:36:53.79#ibcon#flushed, iclass 13, count 0 2006.173.06:36:53.79#ibcon#about to write, iclass 13, count 0 2006.173.06:36:53.79#ibcon#wrote, iclass 13, count 0 2006.173.06:36:53.79#ibcon#about to read 3, iclass 13, count 0 2006.173.06:36:53.81#ibcon#read 3, iclass 13, count 0 2006.173.06:36:53.81#ibcon#about to read 4, iclass 13, count 0 2006.173.06:36:53.81#ibcon#read 4, iclass 13, count 0 2006.173.06:36:53.81#ibcon#about to read 5, iclass 13, count 0 2006.173.06:36:53.81#ibcon#read 5, iclass 13, count 0 2006.173.06:36:53.81#ibcon#about to read 6, iclass 13, count 0 2006.173.06:36:53.81#ibcon#read 6, iclass 13, count 0 2006.173.06:36:53.81#ibcon#end of sib2, iclass 13, count 0 2006.173.06:36:53.81#ibcon#*mode == 0, iclass 13, count 0 2006.173.06:36:53.81#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.06:36:53.81#ibcon#[25=USB\r\n] 2006.173.06:36:53.81#ibcon#*before write, iclass 13, count 0 2006.173.06:36:53.81#ibcon#enter sib2, iclass 13, count 0 2006.173.06:36:53.81#ibcon#flushed, iclass 13, count 0 2006.173.06:36:53.81#ibcon#about to write, iclass 13, count 0 2006.173.06:36:53.81#ibcon#wrote, iclass 13, count 0 2006.173.06:36:53.81#ibcon#about to read 3, iclass 13, count 0 2006.173.06:36:53.84#ibcon#read 3, iclass 13, count 0 2006.173.06:36:53.84#ibcon#about to read 4, iclass 13, count 0 2006.173.06:36:53.84#ibcon#read 4, iclass 13, count 0 2006.173.06:36:53.84#ibcon#about to read 5, iclass 13, count 0 2006.173.06:36:53.84#ibcon#read 5, iclass 13, count 0 2006.173.06:36:53.84#ibcon#about to read 6, iclass 13, count 0 2006.173.06:36:53.84#ibcon#read 6, iclass 13, count 0 2006.173.06:36:53.84#ibcon#end of sib2, iclass 13, count 0 2006.173.06:36:53.84#ibcon#*after write, iclass 13, count 0 2006.173.06:36:53.84#ibcon#*before return 0, iclass 13, count 0 2006.173.06:36:53.84#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.06:36:53.84#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.173.06:36:53.84#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.06:36:53.84#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.06:36:53.84$vck44/vblo=1,629.99 2006.173.06:36:53.84#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.06:36:53.84#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.06:36:53.84#ibcon#ireg 17 cls_cnt 0 2006.173.06:36:53.84#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.06:36:53.84#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.06:36:53.84#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.06:36:53.84#ibcon#enter wrdev, iclass 15, count 0 2006.173.06:36:53.84#ibcon#first serial, iclass 15, count 0 2006.173.06:36:53.84#ibcon#enter sib2, iclass 15, count 0 2006.173.06:36:53.84#ibcon#flushed, iclass 15, count 0 2006.173.06:36:53.84#ibcon#about to write, iclass 15, count 0 2006.173.06:36:53.84#ibcon#wrote, iclass 15, count 0 2006.173.06:36:53.84#ibcon#about to read 3, iclass 15, count 0 2006.173.06:36:53.86#ibcon#read 3, iclass 15, count 0 2006.173.06:36:53.86#ibcon#about to read 4, iclass 15, count 0 2006.173.06:36:53.86#ibcon#read 4, iclass 15, count 0 2006.173.06:36:53.86#ibcon#about to read 5, iclass 15, count 0 2006.173.06:36:53.86#ibcon#read 5, iclass 15, count 0 2006.173.06:36:53.86#ibcon#about to read 6, iclass 15, count 0 2006.173.06:36:53.86#ibcon#read 6, iclass 15, count 0 2006.173.06:36:53.86#ibcon#end of sib2, iclass 15, count 0 2006.173.06:36:53.86#ibcon#*mode == 0, iclass 15, count 0 2006.173.06:36:53.86#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.06:36:53.86#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.06:36:53.86#ibcon#*before write, iclass 15, count 0 2006.173.06:36:53.86#ibcon#enter sib2, iclass 15, count 0 2006.173.06:36:53.86#ibcon#flushed, iclass 15, count 0 2006.173.06:36:53.86#ibcon#about to write, iclass 15, count 0 2006.173.06:36:53.86#ibcon#wrote, iclass 15, count 0 2006.173.06:36:53.86#ibcon#about to read 3, iclass 15, count 0 2006.173.06:36:53.90#ibcon#read 3, iclass 15, count 0 2006.173.06:36:53.90#ibcon#about to read 4, iclass 15, count 0 2006.173.06:36:53.90#ibcon#read 4, iclass 15, count 0 2006.173.06:36:53.90#ibcon#about to read 5, iclass 15, count 0 2006.173.06:36:53.90#ibcon#read 5, iclass 15, count 0 2006.173.06:36:53.90#ibcon#about to read 6, iclass 15, count 0 2006.173.06:36:53.90#ibcon#read 6, iclass 15, count 0 2006.173.06:36:53.90#ibcon#end of sib2, iclass 15, count 0 2006.173.06:36:53.90#ibcon#*after write, iclass 15, count 0 2006.173.06:36:53.90#ibcon#*before return 0, iclass 15, count 0 2006.173.06:36:53.90#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.06:36:53.90#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.06:36:53.90#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.06:36:53.90#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.06:36:53.90$vck44/vb=1,4 2006.173.06:36:53.90#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.06:36:53.90#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.06:36:53.90#ibcon#ireg 11 cls_cnt 2 2006.173.06:36:53.90#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.06:36:53.90#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.06:36:53.90#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.06:36:53.90#ibcon#enter wrdev, iclass 17, count 2 2006.173.06:36:53.90#ibcon#first serial, iclass 17, count 2 2006.173.06:36:53.90#ibcon#enter sib2, iclass 17, count 2 2006.173.06:36:53.90#ibcon#flushed, iclass 17, count 2 2006.173.06:36:53.90#ibcon#about to write, iclass 17, count 2 2006.173.06:36:53.90#ibcon#wrote, iclass 17, count 2 2006.173.06:36:53.90#ibcon#about to read 3, iclass 17, count 2 2006.173.06:36:53.92#ibcon#read 3, iclass 17, count 2 2006.173.06:36:53.92#ibcon#about to read 4, iclass 17, count 2 2006.173.06:36:53.92#ibcon#read 4, iclass 17, count 2 2006.173.06:36:53.92#ibcon#about to read 5, iclass 17, count 2 2006.173.06:36:53.92#ibcon#read 5, iclass 17, count 2 2006.173.06:36:53.92#ibcon#about to read 6, iclass 17, count 2 2006.173.06:36:53.92#ibcon#read 6, iclass 17, count 2 2006.173.06:36:53.92#ibcon#end of sib2, iclass 17, count 2 2006.173.06:36:53.92#ibcon#*mode == 0, iclass 17, count 2 2006.173.06:36:53.92#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.06:36:53.92#ibcon#[27=AT01-04\r\n] 2006.173.06:36:53.92#ibcon#*before write, iclass 17, count 2 2006.173.06:36:53.92#ibcon#enter sib2, iclass 17, count 2 2006.173.06:36:53.92#ibcon#flushed, iclass 17, count 2 2006.173.06:36:53.92#ibcon#about to write, iclass 17, count 2 2006.173.06:36:53.92#ibcon#wrote, iclass 17, count 2 2006.173.06:36:53.92#ibcon#about to read 3, iclass 17, count 2 2006.173.06:36:53.95#ibcon#read 3, iclass 17, count 2 2006.173.06:36:53.95#ibcon#about to read 4, iclass 17, count 2 2006.173.06:36:53.95#ibcon#read 4, iclass 17, count 2 2006.173.06:36:53.95#ibcon#about to read 5, iclass 17, count 2 2006.173.06:36:53.95#ibcon#read 5, iclass 17, count 2 2006.173.06:36:53.95#ibcon#about to read 6, iclass 17, count 2 2006.173.06:36:53.95#ibcon#read 6, iclass 17, count 2 2006.173.06:36:53.95#ibcon#end of sib2, iclass 17, count 2 2006.173.06:36:53.95#ibcon#*after write, iclass 17, count 2 2006.173.06:36:53.95#ibcon#*before return 0, iclass 17, count 2 2006.173.06:36:53.95#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.06:36:53.95#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.06:36:53.95#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.06:36:53.95#ibcon#ireg 7 cls_cnt 0 2006.173.06:36:53.95#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.06:36:54.07#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.06:36:54.07#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.06:36:54.07#ibcon#enter wrdev, iclass 17, count 0 2006.173.06:36:54.07#ibcon#first serial, iclass 17, count 0 2006.173.06:36:54.07#ibcon#enter sib2, iclass 17, count 0 2006.173.06:36:54.07#ibcon#flushed, iclass 17, count 0 2006.173.06:36:54.07#ibcon#about to write, iclass 17, count 0 2006.173.06:36:54.07#ibcon#wrote, iclass 17, count 0 2006.173.06:36:54.07#ibcon#about to read 3, iclass 17, count 0 2006.173.06:36:54.09#ibcon#read 3, iclass 17, count 0 2006.173.06:36:54.09#ibcon#about to read 4, iclass 17, count 0 2006.173.06:36:54.09#ibcon#read 4, iclass 17, count 0 2006.173.06:36:54.09#ibcon#about to read 5, iclass 17, count 0 2006.173.06:36:54.09#ibcon#read 5, iclass 17, count 0 2006.173.06:36:54.09#ibcon#about to read 6, iclass 17, count 0 2006.173.06:36:54.09#ibcon#read 6, iclass 17, count 0 2006.173.06:36:54.09#ibcon#end of sib2, iclass 17, count 0 2006.173.06:36:54.09#ibcon#*mode == 0, iclass 17, count 0 2006.173.06:36:54.09#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.06:36:54.09#ibcon#[27=USB\r\n] 2006.173.06:36:54.09#ibcon#*before write, iclass 17, count 0 2006.173.06:36:54.09#ibcon#enter sib2, iclass 17, count 0 2006.173.06:36:54.09#ibcon#flushed, iclass 17, count 0 2006.173.06:36:54.09#ibcon#about to write, iclass 17, count 0 2006.173.06:36:54.09#ibcon#wrote, iclass 17, count 0 2006.173.06:36:54.09#ibcon#about to read 3, iclass 17, count 0 2006.173.06:36:54.12#ibcon#read 3, iclass 17, count 0 2006.173.06:36:54.12#ibcon#about to read 4, iclass 17, count 0 2006.173.06:36:54.12#ibcon#read 4, iclass 17, count 0 2006.173.06:36:54.12#ibcon#about to read 5, iclass 17, count 0 2006.173.06:36:54.12#ibcon#read 5, iclass 17, count 0 2006.173.06:36:54.12#ibcon#about to read 6, iclass 17, count 0 2006.173.06:36:54.12#ibcon#read 6, iclass 17, count 0 2006.173.06:36:54.12#ibcon#end of sib2, iclass 17, count 0 2006.173.06:36:54.12#ibcon#*after write, iclass 17, count 0 2006.173.06:36:54.12#ibcon#*before return 0, iclass 17, count 0 2006.173.06:36:54.12#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.06:36:54.12#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.06:36:54.12#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.06:36:54.12#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.06:36:54.12$vck44/vblo=2,634.99 2006.173.06:36:54.12#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.06:36:54.12#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.06:36:54.12#ibcon#ireg 17 cls_cnt 0 2006.173.06:36:54.12#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.06:36:54.12#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.06:36:54.12#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.06:36:54.12#ibcon#enter wrdev, iclass 19, count 0 2006.173.06:36:54.12#ibcon#first serial, iclass 19, count 0 2006.173.06:36:54.12#ibcon#enter sib2, iclass 19, count 0 2006.173.06:36:54.13#ibcon#flushed, iclass 19, count 0 2006.173.06:36:54.13#ibcon#about to write, iclass 19, count 0 2006.173.06:36:54.13#ibcon#wrote, iclass 19, count 0 2006.173.06:36:54.13#ibcon#about to read 3, iclass 19, count 0 2006.173.06:36:54.14#ibcon#read 3, iclass 19, count 0 2006.173.06:36:54.14#ibcon#about to read 4, iclass 19, count 0 2006.173.06:36:54.14#ibcon#read 4, iclass 19, count 0 2006.173.06:36:54.14#ibcon#about to read 5, iclass 19, count 0 2006.173.06:36:54.14#ibcon#read 5, iclass 19, count 0 2006.173.06:36:54.14#ibcon#about to read 6, iclass 19, count 0 2006.173.06:36:54.14#ibcon#read 6, iclass 19, count 0 2006.173.06:36:54.14#ibcon#end of sib2, iclass 19, count 0 2006.173.06:36:54.14#ibcon#*mode == 0, iclass 19, count 0 2006.173.06:36:54.14#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.06:36:54.14#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.06:36:54.14#ibcon#*before write, iclass 19, count 0 2006.173.06:36:54.14#ibcon#enter sib2, iclass 19, count 0 2006.173.06:36:54.14#ibcon#flushed, iclass 19, count 0 2006.173.06:36:54.14#ibcon#about to write, iclass 19, count 0 2006.173.06:36:54.14#ibcon#wrote, iclass 19, count 0 2006.173.06:36:54.14#ibcon#about to read 3, iclass 19, count 0 2006.173.06:36:54.18#ibcon#read 3, iclass 19, count 0 2006.173.06:36:54.18#ibcon#about to read 4, iclass 19, count 0 2006.173.06:36:54.18#ibcon#read 4, iclass 19, count 0 2006.173.06:36:54.18#ibcon#about to read 5, iclass 19, count 0 2006.173.06:36:54.18#ibcon#read 5, iclass 19, count 0 2006.173.06:36:54.18#ibcon#about to read 6, iclass 19, count 0 2006.173.06:36:54.18#ibcon#read 6, iclass 19, count 0 2006.173.06:36:54.18#ibcon#end of sib2, iclass 19, count 0 2006.173.06:36:54.18#ibcon#*after write, iclass 19, count 0 2006.173.06:36:54.18#ibcon#*before return 0, iclass 19, count 0 2006.173.06:36:54.18#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.06:36:54.18#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.06:36:54.18#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.06:36:54.18#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.06:36:54.18$vck44/vb=2,4 2006.173.06:36:54.18#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.06:36:54.18#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.06:36:54.18#ibcon#ireg 11 cls_cnt 2 2006.173.06:36:54.18#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.06:36:54.24#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.06:36:54.24#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.06:36:54.24#ibcon#enter wrdev, iclass 21, count 2 2006.173.06:36:54.24#ibcon#first serial, iclass 21, count 2 2006.173.06:36:54.24#ibcon#enter sib2, iclass 21, count 2 2006.173.06:36:54.24#ibcon#flushed, iclass 21, count 2 2006.173.06:36:54.24#ibcon#about to write, iclass 21, count 2 2006.173.06:36:54.24#ibcon#wrote, iclass 21, count 2 2006.173.06:36:54.24#ibcon#about to read 3, iclass 21, count 2 2006.173.06:36:54.26#ibcon#read 3, iclass 21, count 2 2006.173.06:36:54.26#ibcon#about to read 4, iclass 21, count 2 2006.173.06:36:54.26#ibcon#read 4, iclass 21, count 2 2006.173.06:36:54.26#ibcon#about to read 5, iclass 21, count 2 2006.173.06:36:54.26#ibcon#read 5, iclass 21, count 2 2006.173.06:36:54.26#ibcon#about to read 6, iclass 21, count 2 2006.173.06:36:54.26#ibcon#read 6, iclass 21, count 2 2006.173.06:36:54.26#ibcon#end of sib2, iclass 21, count 2 2006.173.06:36:54.26#ibcon#*mode == 0, iclass 21, count 2 2006.173.06:36:54.26#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.06:36:54.26#ibcon#[27=AT02-04\r\n] 2006.173.06:36:54.26#ibcon#*before write, iclass 21, count 2 2006.173.06:36:54.26#ibcon#enter sib2, iclass 21, count 2 2006.173.06:36:54.26#ibcon#flushed, iclass 21, count 2 2006.173.06:36:54.26#ibcon#about to write, iclass 21, count 2 2006.173.06:36:54.26#ibcon#wrote, iclass 21, count 2 2006.173.06:36:54.26#ibcon#about to read 3, iclass 21, count 2 2006.173.06:36:54.29#ibcon#read 3, iclass 21, count 2 2006.173.06:36:54.29#ibcon#about to read 4, iclass 21, count 2 2006.173.06:36:54.29#ibcon#read 4, iclass 21, count 2 2006.173.06:36:54.29#ibcon#about to read 5, iclass 21, count 2 2006.173.06:36:54.29#ibcon#read 5, iclass 21, count 2 2006.173.06:36:54.29#ibcon#about to read 6, iclass 21, count 2 2006.173.06:36:54.29#ibcon#read 6, iclass 21, count 2 2006.173.06:36:54.29#ibcon#end of sib2, iclass 21, count 2 2006.173.06:36:54.29#ibcon#*after write, iclass 21, count 2 2006.173.06:36:54.29#ibcon#*before return 0, iclass 21, count 2 2006.173.06:36:54.29#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.06:36:54.29#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.06:36:54.29#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.06:36:54.29#ibcon#ireg 7 cls_cnt 0 2006.173.06:36:54.29#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.06:36:54.41#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.06:36:54.41#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.06:36:54.41#ibcon#enter wrdev, iclass 21, count 0 2006.173.06:36:54.41#ibcon#first serial, iclass 21, count 0 2006.173.06:36:54.41#ibcon#enter sib2, iclass 21, count 0 2006.173.06:36:54.41#ibcon#flushed, iclass 21, count 0 2006.173.06:36:54.41#ibcon#about to write, iclass 21, count 0 2006.173.06:36:54.41#ibcon#wrote, iclass 21, count 0 2006.173.06:36:54.41#ibcon#about to read 3, iclass 21, count 0 2006.173.06:36:54.43#ibcon#read 3, iclass 21, count 0 2006.173.06:36:54.43#ibcon#about to read 4, iclass 21, count 0 2006.173.06:36:54.43#ibcon#read 4, iclass 21, count 0 2006.173.06:36:54.43#ibcon#about to read 5, iclass 21, count 0 2006.173.06:36:54.43#ibcon#read 5, iclass 21, count 0 2006.173.06:36:54.43#ibcon#about to read 6, iclass 21, count 0 2006.173.06:36:54.43#ibcon#read 6, iclass 21, count 0 2006.173.06:36:54.43#ibcon#end of sib2, iclass 21, count 0 2006.173.06:36:54.43#ibcon#*mode == 0, iclass 21, count 0 2006.173.06:36:54.43#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.06:36:54.43#ibcon#[27=USB\r\n] 2006.173.06:36:54.43#ibcon#*before write, iclass 21, count 0 2006.173.06:36:54.43#ibcon#enter sib2, iclass 21, count 0 2006.173.06:36:54.43#ibcon#flushed, iclass 21, count 0 2006.173.06:36:54.43#ibcon#about to write, iclass 21, count 0 2006.173.06:36:54.43#ibcon#wrote, iclass 21, count 0 2006.173.06:36:54.43#ibcon#about to read 3, iclass 21, count 0 2006.173.06:36:54.46#ibcon#read 3, iclass 21, count 0 2006.173.06:36:54.46#ibcon#about to read 4, iclass 21, count 0 2006.173.06:36:54.46#ibcon#read 4, iclass 21, count 0 2006.173.06:36:54.46#ibcon#about to read 5, iclass 21, count 0 2006.173.06:36:54.46#ibcon#read 5, iclass 21, count 0 2006.173.06:36:54.46#ibcon#about to read 6, iclass 21, count 0 2006.173.06:36:54.46#ibcon#read 6, iclass 21, count 0 2006.173.06:36:54.46#ibcon#end of sib2, iclass 21, count 0 2006.173.06:36:54.46#ibcon#*after write, iclass 21, count 0 2006.173.06:36:54.46#ibcon#*before return 0, iclass 21, count 0 2006.173.06:36:54.46#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.06:36:54.46#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.06:36:54.46#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.06:36:54.46#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.06:36:54.46$vck44/vblo=3,649.99 2006.173.06:36:54.46#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.06:36:54.46#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.06:36:54.46#ibcon#ireg 17 cls_cnt 0 2006.173.06:36:54.46#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.06:36:54.46#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.06:36:54.46#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.06:36:54.46#ibcon#enter wrdev, iclass 23, count 0 2006.173.06:36:54.46#ibcon#first serial, iclass 23, count 0 2006.173.06:36:54.46#ibcon#enter sib2, iclass 23, count 0 2006.173.06:36:54.46#ibcon#flushed, iclass 23, count 0 2006.173.06:36:54.46#ibcon#about to write, iclass 23, count 0 2006.173.06:36:54.46#ibcon#wrote, iclass 23, count 0 2006.173.06:36:54.46#ibcon#about to read 3, iclass 23, count 0 2006.173.06:36:54.48#ibcon#read 3, iclass 23, count 0 2006.173.06:36:54.48#ibcon#about to read 4, iclass 23, count 0 2006.173.06:36:54.48#ibcon#read 4, iclass 23, count 0 2006.173.06:36:54.48#ibcon#about to read 5, iclass 23, count 0 2006.173.06:36:54.48#ibcon#read 5, iclass 23, count 0 2006.173.06:36:54.48#ibcon#about to read 6, iclass 23, count 0 2006.173.06:36:54.48#ibcon#read 6, iclass 23, count 0 2006.173.06:36:54.48#ibcon#end of sib2, iclass 23, count 0 2006.173.06:36:54.48#ibcon#*mode == 0, iclass 23, count 0 2006.173.06:36:54.48#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.06:36:54.48#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.06:36:54.48#ibcon#*before write, iclass 23, count 0 2006.173.06:36:54.48#ibcon#enter sib2, iclass 23, count 0 2006.173.06:36:54.48#ibcon#flushed, iclass 23, count 0 2006.173.06:36:54.48#ibcon#about to write, iclass 23, count 0 2006.173.06:36:54.48#ibcon#wrote, iclass 23, count 0 2006.173.06:36:54.48#ibcon#about to read 3, iclass 23, count 0 2006.173.06:36:54.52#ibcon#read 3, iclass 23, count 0 2006.173.06:36:54.52#ibcon#about to read 4, iclass 23, count 0 2006.173.06:36:54.52#ibcon#read 4, iclass 23, count 0 2006.173.06:36:54.52#ibcon#about to read 5, iclass 23, count 0 2006.173.06:36:54.52#ibcon#read 5, iclass 23, count 0 2006.173.06:36:54.52#ibcon#about to read 6, iclass 23, count 0 2006.173.06:36:54.52#ibcon#read 6, iclass 23, count 0 2006.173.06:36:54.52#ibcon#end of sib2, iclass 23, count 0 2006.173.06:36:54.52#ibcon#*after write, iclass 23, count 0 2006.173.06:36:54.52#ibcon#*before return 0, iclass 23, count 0 2006.173.06:36:54.52#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.06:36:54.52#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.06:36:54.52#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.06:36:54.52#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.06:36:54.52$vck44/vb=3,4 2006.173.06:36:54.52#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.06:36:54.52#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.06:36:54.52#ibcon#ireg 11 cls_cnt 2 2006.173.06:36:54.52#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.06:36:54.58#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.06:36:54.58#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.06:36:54.58#ibcon#enter wrdev, iclass 25, count 2 2006.173.06:36:54.58#ibcon#first serial, iclass 25, count 2 2006.173.06:36:54.58#ibcon#enter sib2, iclass 25, count 2 2006.173.06:36:54.58#ibcon#flushed, iclass 25, count 2 2006.173.06:36:54.58#ibcon#about to write, iclass 25, count 2 2006.173.06:36:54.58#ibcon#wrote, iclass 25, count 2 2006.173.06:36:54.58#ibcon#about to read 3, iclass 25, count 2 2006.173.06:36:54.60#ibcon#read 3, iclass 25, count 2 2006.173.06:36:54.60#ibcon#about to read 4, iclass 25, count 2 2006.173.06:36:54.60#ibcon#read 4, iclass 25, count 2 2006.173.06:36:54.60#ibcon#about to read 5, iclass 25, count 2 2006.173.06:36:54.60#ibcon#read 5, iclass 25, count 2 2006.173.06:36:54.60#ibcon#about to read 6, iclass 25, count 2 2006.173.06:36:54.60#ibcon#read 6, iclass 25, count 2 2006.173.06:36:54.60#ibcon#end of sib2, iclass 25, count 2 2006.173.06:36:54.60#ibcon#*mode == 0, iclass 25, count 2 2006.173.06:36:54.60#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.06:36:54.60#ibcon#[27=AT03-04\r\n] 2006.173.06:36:54.60#ibcon#*before write, iclass 25, count 2 2006.173.06:36:54.60#ibcon#enter sib2, iclass 25, count 2 2006.173.06:36:54.60#ibcon#flushed, iclass 25, count 2 2006.173.06:36:54.60#ibcon#about to write, iclass 25, count 2 2006.173.06:36:54.60#ibcon#wrote, iclass 25, count 2 2006.173.06:36:54.60#ibcon#about to read 3, iclass 25, count 2 2006.173.06:36:54.63#ibcon#read 3, iclass 25, count 2 2006.173.06:36:54.63#ibcon#about to read 4, iclass 25, count 2 2006.173.06:36:54.63#ibcon#read 4, iclass 25, count 2 2006.173.06:36:54.63#ibcon#about to read 5, iclass 25, count 2 2006.173.06:36:54.63#ibcon#read 5, iclass 25, count 2 2006.173.06:36:54.63#ibcon#about to read 6, iclass 25, count 2 2006.173.06:36:54.63#ibcon#read 6, iclass 25, count 2 2006.173.06:36:54.63#ibcon#end of sib2, iclass 25, count 2 2006.173.06:36:54.63#ibcon#*after write, iclass 25, count 2 2006.173.06:36:54.63#ibcon#*before return 0, iclass 25, count 2 2006.173.06:36:54.63#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.06:36:54.63#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.06:36:54.63#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.06:36:54.63#ibcon#ireg 7 cls_cnt 0 2006.173.06:36:54.63#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.06:36:54.75#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.06:36:54.75#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.06:36:54.75#ibcon#enter wrdev, iclass 25, count 0 2006.173.06:36:54.75#ibcon#first serial, iclass 25, count 0 2006.173.06:36:54.75#ibcon#enter sib2, iclass 25, count 0 2006.173.06:36:54.75#ibcon#flushed, iclass 25, count 0 2006.173.06:36:54.75#ibcon#about to write, iclass 25, count 0 2006.173.06:36:54.75#ibcon#wrote, iclass 25, count 0 2006.173.06:36:54.75#ibcon#about to read 3, iclass 25, count 0 2006.173.06:36:54.77#ibcon#read 3, iclass 25, count 0 2006.173.06:36:54.77#ibcon#about to read 4, iclass 25, count 0 2006.173.06:36:54.77#ibcon#read 4, iclass 25, count 0 2006.173.06:36:54.77#ibcon#about to read 5, iclass 25, count 0 2006.173.06:36:54.77#ibcon#read 5, iclass 25, count 0 2006.173.06:36:54.77#ibcon#about to read 6, iclass 25, count 0 2006.173.06:36:54.77#ibcon#read 6, iclass 25, count 0 2006.173.06:36:54.77#ibcon#end of sib2, iclass 25, count 0 2006.173.06:36:54.77#ibcon#*mode == 0, iclass 25, count 0 2006.173.06:36:54.77#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.06:36:54.77#ibcon#[27=USB\r\n] 2006.173.06:36:54.77#ibcon#*before write, iclass 25, count 0 2006.173.06:36:54.77#ibcon#enter sib2, iclass 25, count 0 2006.173.06:36:54.77#ibcon#flushed, iclass 25, count 0 2006.173.06:36:54.77#ibcon#about to write, iclass 25, count 0 2006.173.06:36:54.77#ibcon#wrote, iclass 25, count 0 2006.173.06:36:54.77#ibcon#about to read 3, iclass 25, count 0 2006.173.06:36:54.79#abcon#<5=/15 0.6 1.0 23.78 791005.0\r\n> 2006.173.06:36:54.80#ibcon#read 3, iclass 25, count 0 2006.173.06:36:54.80#ibcon#about to read 4, iclass 25, count 0 2006.173.06:36:54.80#ibcon#read 4, iclass 25, count 0 2006.173.06:36:54.80#ibcon#about to read 5, iclass 25, count 0 2006.173.06:36:54.80#ibcon#read 5, iclass 25, count 0 2006.173.06:36:54.80#ibcon#about to read 6, iclass 25, count 0 2006.173.06:36:54.80#ibcon#read 6, iclass 25, count 0 2006.173.06:36:54.80#ibcon#end of sib2, iclass 25, count 0 2006.173.06:36:54.80#ibcon#*after write, iclass 25, count 0 2006.173.06:36:54.80#ibcon#*before return 0, iclass 25, count 0 2006.173.06:36:54.80#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.06:36:54.80#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.06:36:54.80#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.06:36:54.80#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.06:36:54.80$vck44/vblo=4,679.99 2006.173.06:36:54.80#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.06:36:54.80#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.06:36:54.80#ibcon#ireg 17 cls_cnt 0 2006.173.06:36:54.80#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.06:36:54.80#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.06:36:54.80#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.06:36:54.80#ibcon#enter wrdev, iclass 30, count 0 2006.173.06:36:54.80#ibcon#first serial, iclass 30, count 0 2006.173.06:36:54.80#ibcon#enter sib2, iclass 30, count 0 2006.173.06:36:54.80#ibcon#flushed, iclass 30, count 0 2006.173.06:36:54.80#ibcon#about to write, iclass 30, count 0 2006.173.06:36:54.80#ibcon#wrote, iclass 30, count 0 2006.173.06:36:54.80#ibcon#about to read 3, iclass 30, count 0 2006.173.06:36:54.81#abcon#{5=INTERFACE CLEAR} 2006.173.06:36:54.82#ibcon#read 3, iclass 30, count 0 2006.173.06:36:54.82#ibcon#about to read 4, iclass 30, count 0 2006.173.06:36:54.82#ibcon#read 4, iclass 30, count 0 2006.173.06:36:54.82#ibcon#about to read 5, iclass 30, count 0 2006.173.06:36:54.82#ibcon#read 5, iclass 30, count 0 2006.173.06:36:54.82#ibcon#about to read 6, iclass 30, count 0 2006.173.06:36:54.82#ibcon#read 6, iclass 30, count 0 2006.173.06:36:54.82#ibcon#end of sib2, iclass 30, count 0 2006.173.06:36:54.82#ibcon#*mode == 0, iclass 30, count 0 2006.173.06:36:54.82#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.06:36:54.82#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.06:36:54.82#ibcon#*before write, iclass 30, count 0 2006.173.06:36:54.82#ibcon#enter sib2, iclass 30, count 0 2006.173.06:36:54.82#ibcon#flushed, iclass 30, count 0 2006.173.06:36:54.82#ibcon#about to write, iclass 30, count 0 2006.173.06:36:54.82#ibcon#wrote, iclass 30, count 0 2006.173.06:36:54.82#ibcon#about to read 3, iclass 30, count 0 2006.173.06:36:54.86#ibcon#read 3, iclass 30, count 0 2006.173.06:36:54.86#ibcon#about to read 4, iclass 30, count 0 2006.173.06:36:54.86#ibcon#read 4, iclass 30, count 0 2006.173.06:36:54.86#ibcon#about to read 5, iclass 30, count 0 2006.173.06:36:54.86#ibcon#read 5, iclass 30, count 0 2006.173.06:36:54.86#ibcon#about to read 6, iclass 30, count 0 2006.173.06:36:54.86#ibcon#read 6, iclass 30, count 0 2006.173.06:36:54.86#ibcon#end of sib2, iclass 30, count 0 2006.173.06:36:54.86#ibcon#*after write, iclass 30, count 0 2006.173.06:36:54.86#ibcon#*before return 0, iclass 30, count 0 2006.173.06:36:54.86#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.06:36:54.86#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.06:36:54.86#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.06:36:54.86#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.06:36:54.86$vck44/vb=4,4 2006.173.06:36:54.86#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.173.06:36:54.86#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.173.06:36:54.86#ibcon#ireg 11 cls_cnt 2 2006.173.06:36:54.86#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.06:36:54.87#abcon#[5=S1D000X0/0*\r\n] 2006.173.06:36:54.92#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.06:36:54.92#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.06:36:54.92#ibcon#enter wrdev, iclass 33, count 2 2006.173.06:36:54.92#ibcon#first serial, iclass 33, count 2 2006.173.06:36:54.92#ibcon#enter sib2, iclass 33, count 2 2006.173.06:36:54.92#ibcon#flushed, iclass 33, count 2 2006.173.06:36:54.92#ibcon#about to write, iclass 33, count 2 2006.173.06:36:54.92#ibcon#wrote, iclass 33, count 2 2006.173.06:36:54.92#ibcon#about to read 3, iclass 33, count 2 2006.173.06:36:54.94#ibcon#read 3, iclass 33, count 2 2006.173.06:36:54.94#ibcon#about to read 4, iclass 33, count 2 2006.173.06:36:54.94#ibcon#read 4, iclass 33, count 2 2006.173.06:36:54.94#ibcon#about to read 5, iclass 33, count 2 2006.173.06:36:54.94#ibcon#read 5, iclass 33, count 2 2006.173.06:36:54.94#ibcon#about to read 6, iclass 33, count 2 2006.173.06:36:54.94#ibcon#read 6, iclass 33, count 2 2006.173.06:36:54.94#ibcon#end of sib2, iclass 33, count 2 2006.173.06:36:54.94#ibcon#*mode == 0, iclass 33, count 2 2006.173.06:36:54.94#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.173.06:36:54.94#ibcon#[27=AT04-04\r\n] 2006.173.06:36:54.94#ibcon#*before write, iclass 33, count 2 2006.173.06:36:54.94#ibcon#enter sib2, iclass 33, count 2 2006.173.06:36:54.94#ibcon#flushed, iclass 33, count 2 2006.173.06:36:54.94#ibcon#about to write, iclass 33, count 2 2006.173.06:36:54.94#ibcon#wrote, iclass 33, count 2 2006.173.06:36:54.94#ibcon#about to read 3, iclass 33, count 2 2006.173.06:36:54.97#ibcon#read 3, iclass 33, count 2 2006.173.06:36:54.97#ibcon#about to read 4, iclass 33, count 2 2006.173.06:36:54.97#ibcon#read 4, iclass 33, count 2 2006.173.06:36:54.97#ibcon#about to read 5, iclass 33, count 2 2006.173.06:36:54.97#ibcon#read 5, iclass 33, count 2 2006.173.06:36:54.97#ibcon#about to read 6, iclass 33, count 2 2006.173.06:36:54.97#ibcon#read 6, iclass 33, count 2 2006.173.06:36:54.97#ibcon#end of sib2, iclass 33, count 2 2006.173.06:36:54.97#ibcon#*after write, iclass 33, count 2 2006.173.06:36:54.97#ibcon#*before return 0, iclass 33, count 2 2006.173.06:36:54.97#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.06:36:54.97#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.173.06:36:54.97#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.173.06:36:54.97#ibcon#ireg 7 cls_cnt 0 2006.173.06:36:54.97#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.06:36:55.09#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.06:36:55.09#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.06:36:55.09#ibcon#enter wrdev, iclass 33, count 0 2006.173.06:36:55.09#ibcon#first serial, iclass 33, count 0 2006.173.06:36:55.09#ibcon#enter sib2, iclass 33, count 0 2006.173.06:36:55.09#ibcon#flushed, iclass 33, count 0 2006.173.06:36:55.09#ibcon#about to write, iclass 33, count 0 2006.173.06:36:55.09#ibcon#wrote, iclass 33, count 0 2006.173.06:36:55.09#ibcon#about to read 3, iclass 33, count 0 2006.173.06:36:55.11#ibcon#read 3, iclass 33, count 0 2006.173.06:36:55.11#ibcon#about to read 4, iclass 33, count 0 2006.173.06:36:55.11#ibcon#read 4, iclass 33, count 0 2006.173.06:36:55.11#ibcon#about to read 5, iclass 33, count 0 2006.173.06:36:55.11#ibcon#read 5, iclass 33, count 0 2006.173.06:36:55.11#ibcon#about to read 6, iclass 33, count 0 2006.173.06:36:55.11#ibcon#read 6, iclass 33, count 0 2006.173.06:36:55.11#ibcon#end of sib2, iclass 33, count 0 2006.173.06:36:55.11#ibcon#*mode == 0, iclass 33, count 0 2006.173.06:36:55.11#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.06:36:55.11#ibcon#[27=USB\r\n] 2006.173.06:36:55.11#ibcon#*before write, iclass 33, count 0 2006.173.06:36:55.11#ibcon#enter sib2, iclass 33, count 0 2006.173.06:36:55.11#ibcon#flushed, iclass 33, count 0 2006.173.06:36:55.11#ibcon#about to write, iclass 33, count 0 2006.173.06:36:55.11#ibcon#wrote, iclass 33, count 0 2006.173.06:36:55.11#ibcon#about to read 3, iclass 33, count 0 2006.173.06:36:55.14#ibcon#read 3, iclass 33, count 0 2006.173.06:36:55.14#ibcon#about to read 4, iclass 33, count 0 2006.173.06:36:55.14#ibcon#read 4, iclass 33, count 0 2006.173.06:36:55.14#ibcon#about to read 5, iclass 33, count 0 2006.173.06:36:55.14#ibcon#read 5, iclass 33, count 0 2006.173.06:36:55.14#ibcon#about to read 6, iclass 33, count 0 2006.173.06:36:55.14#ibcon#read 6, iclass 33, count 0 2006.173.06:36:55.14#ibcon#end of sib2, iclass 33, count 0 2006.173.06:36:55.14#ibcon#*after write, iclass 33, count 0 2006.173.06:36:55.14#ibcon#*before return 0, iclass 33, count 0 2006.173.06:36:55.14#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.06:36:55.14#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.173.06:36:55.14#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.06:36:55.14#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.06:36:55.14$vck44/vblo=5,709.99 2006.173.06:36:55.14#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.06:36:55.14#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.06:36:55.14#ibcon#ireg 17 cls_cnt 0 2006.173.06:36:55.14#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.06:36:55.14#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.06:36:55.14#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.06:36:55.14#ibcon#enter wrdev, iclass 35, count 0 2006.173.06:36:55.14#ibcon#first serial, iclass 35, count 0 2006.173.06:36:55.14#ibcon#enter sib2, iclass 35, count 0 2006.173.06:36:55.14#ibcon#flushed, iclass 35, count 0 2006.173.06:36:55.14#ibcon#about to write, iclass 35, count 0 2006.173.06:36:55.14#ibcon#wrote, iclass 35, count 0 2006.173.06:36:55.15#ibcon#about to read 3, iclass 35, count 0 2006.173.06:36:55.16#ibcon#read 3, iclass 35, count 0 2006.173.06:36:55.16#ibcon#about to read 4, iclass 35, count 0 2006.173.06:36:55.16#ibcon#read 4, iclass 35, count 0 2006.173.06:36:55.16#ibcon#about to read 5, iclass 35, count 0 2006.173.06:36:55.16#ibcon#read 5, iclass 35, count 0 2006.173.06:36:55.16#ibcon#about to read 6, iclass 35, count 0 2006.173.06:36:55.16#ibcon#read 6, iclass 35, count 0 2006.173.06:36:55.16#ibcon#end of sib2, iclass 35, count 0 2006.173.06:36:55.16#ibcon#*mode == 0, iclass 35, count 0 2006.173.06:36:55.16#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.06:36:55.16#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.06:36:55.16#ibcon#*before write, iclass 35, count 0 2006.173.06:36:55.16#ibcon#enter sib2, iclass 35, count 0 2006.173.06:36:55.16#ibcon#flushed, iclass 35, count 0 2006.173.06:36:55.16#ibcon#about to write, iclass 35, count 0 2006.173.06:36:55.16#ibcon#wrote, iclass 35, count 0 2006.173.06:36:55.16#ibcon#about to read 3, iclass 35, count 0 2006.173.06:36:55.20#ibcon#read 3, iclass 35, count 0 2006.173.06:36:55.20#ibcon#about to read 4, iclass 35, count 0 2006.173.06:36:55.20#ibcon#read 4, iclass 35, count 0 2006.173.06:36:55.20#ibcon#about to read 5, iclass 35, count 0 2006.173.06:36:55.20#ibcon#read 5, iclass 35, count 0 2006.173.06:36:55.20#ibcon#about to read 6, iclass 35, count 0 2006.173.06:36:55.20#ibcon#read 6, iclass 35, count 0 2006.173.06:36:55.20#ibcon#end of sib2, iclass 35, count 0 2006.173.06:36:55.20#ibcon#*after write, iclass 35, count 0 2006.173.06:36:55.20#ibcon#*before return 0, iclass 35, count 0 2006.173.06:36:55.20#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.06:36:55.20#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.06:36:55.20#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.06:36:55.20#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.06:36:55.20$vck44/vb=5,4 2006.173.06:36:55.20#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.173.06:36:55.20#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.173.06:36:55.20#ibcon#ireg 11 cls_cnt 2 2006.173.06:36:55.20#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.06:36:55.26#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.06:36:55.26#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.06:36:55.26#ibcon#enter wrdev, iclass 37, count 2 2006.173.06:36:55.26#ibcon#first serial, iclass 37, count 2 2006.173.06:36:55.26#ibcon#enter sib2, iclass 37, count 2 2006.173.06:36:55.26#ibcon#flushed, iclass 37, count 2 2006.173.06:36:55.26#ibcon#about to write, iclass 37, count 2 2006.173.06:36:55.26#ibcon#wrote, iclass 37, count 2 2006.173.06:36:55.26#ibcon#about to read 3, iclass 37, count 2 2006.173.06:36:55.28#ibcon#read 3, iclass 37, count 2 2006.173.06:36:55.28#ibcon#about to read 4, iclass 37, count 2 2006.173.06:36:55.28#ibcon#read 4, iclass 37, count 2 2006.173.06:36:55.28#ibcon#about to read 5, iclass 37, count 2 2006.173.06:36:55.28#ibcon#read 5, iclass 37, count 2 2006.173.06:36:55.28#ibcon#about to read 6, iclass 37, count 2 2006.173.06:36:55.28#ibcon#read 6, iclass 37, count 2 2006.173.06:36:55.28#ibcon#end of sib2, iclass 37, count 2 2006.173.06:36:55.28#ibcon#*mode == 0, iclass 37, count 2 2006.173.06:36:55.28#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.173.06:36:55.28#ibcon#[27=AT05-04\r\n] 2006.173.06:36:55.28#ibcon#*before write, iclass 37, count 2 2006.173.06:36:55.28#ibcon#enter sib2, iclass 37, count 2 2006.173.06:36:55.28#ibcon#flushed, iclass 37, count 2 2006.173.06:36:55.28#ibcon#about to write, iclass 37, count 2 2006.173.06:36:55.29#ibcon#wrote, iclass 37, count 2 2006.173.06:36:55.29#ibcon#about to read 3, iclass 37, count 2 2006.173.06:36:55.31#ibcon#read 3, iclass 37, count 2 2006.173.06:36:55.31#ibcon#about to read 4, iclass 37, count 2 2006.173.06:36:55.31#ibcon#read 4, iclass 37, count 2 2006.173.06:36:55.31#ibcon#about to read 5, iclass 37, count 2 2006.173.06:36:55.31#ibcon#read 5, iclass 37, count 2 2006.173.06:36:55.31#ibcon#about to read 6, iclass 37, count 2 2006.173.06:36:55.31#ibcon#read 6, iclass 37, count 2 2006.173.06:36:55.31#ibcon#end of sib2, iclass 37, count 2 2006.173.06:36:55.31#ibcon#*after write, iclass 37, count 2 2006.173.06:36:55.31#ibcon#*before return 0, iclass 37, count 2 2006.173.06:36:55.31#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.06:36:55.31#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.173.06:36:55.31#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.173.06:36:55.31#ibcon#ireg 7 cls_cnt 0 2006.173.06:36:55.31#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.06:36:55.43#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.06:36:55.43#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.06:36:55.43#ibcon#enter wrdev, iclass 37, count 0 2006.173.06:36:55.43#ibcon#first serial, iclass 37, count 0 2006.173.06:36:55.43#ibcon#enter sib2, iclass 37, count 0 2006.173.06:36:55.43#ibcon#flushed, iclass 37, count 0 2006.173.06:36:55.43#ibcon#about to write, iclass 37, count 0 2006.173.06:36:55.43#ibcon#wrote, iclass 37, count 0 2006.173.06:36:55.43#ibcon#about to read 3, iclass 37, count 0 2006.173.06:36:55.45#ibcon#read 3, iclass 37, count 0 2006.173.06:36:55.45#ibcon#about to read 4, iclass 37, count 0 2006.173.06:36:55.45#ibcon#read 4, iclass 37, count 0 2006.173.06:36:55.45#ibcon#about to read 5, iclass 37, count 0 2006.173.06:36:55.45#ibcon#read 5, iclass 37, count 0 2006.173.06:36:55.45#ibcon#about to read 6, iclass 37, count 0 2006.173.06:36:55.45#ibcon#read 6, iclass 37, count 0 2006.173.06:36:55.45#ibcon#end of sib2, iclass 37, count 0 2006.173.06:36:55.45#ibcon#*mode == 0, iclass 37, count 0 2006.173.06:36:55.45#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.06:36:55.45#ibcon#[27=USB\r\n] 2006.173.06:36:55.45#ibcon#*before write, iclass 37, count 0 2006.173.06:36:55.45#ibcon#enter sib2, iclass 37, count 0 2006.173.06:36:55.45#ibcon#flushed, iclass 37, count 0 2006.173.06:36:55.45#ibcon#about to write, iclass 37, count 0 2006.173.06:36:55.45#ibcon#wrote, iclass 37, count 0 2006.173.06:36:55.45#ibcon#about to read 3, iclass 37, count 0 2006.173.06:36:55.48#ibcon#read 3, iclass 37, count 0 2006.173.06:36:55.48#ibcon#about to read 4, iclass 37, count 0 2006.173.06:36:55.48#ibcon#read 4, iclass 37, count 0 2006.173.06:36:55.48#ibcon#about to read 5, iclass 37, count 0 2006.173.06:36:55.48#ibcon#read 5, iclass 37, count 0 2006.173.06:36:55.48#ibcon#about to read 6, iclass 37, count 0 2006.173.06:36:55.48#ibcon#read 6, iclass 37, count 0 2006.173.06:36:55.48#ibcon#end of sib2, iclass 37, count 0 2006.173.06:36:55.48#ibcon#*after write, iclass 37, count 0 2006.173.06:36:55.48#ibcon#*before return 0, iclass 37, count 0 2006.173.06:36:55.48#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.06:36:55.48#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.173.06:36:55.48#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.06:36:55.48#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.06:36:55.48$vck44/vblo=6,719.99 2006.173.06:36:55.48#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.06:36:55.48#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.06:36:55.48#ibcon#ireg 17 cls_cnt 0 2006.173.06:36:55.48#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.06:36:55.48#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.06:36:55.48#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.06:36:55.48#ibcon#enter wrdev, iclass 39, count 0 2006.173.06:36:55.48#ibcon#first serial, iclass 39, count 0 2006.173.06:36:55.48#ibcon#enter sib2, iclass 39, count 0 2006.173.06:36:55.48#ibcon#flushed, iclass 39, count 0 2006.173.06:36:55.48#ibcon#about to write, iclass 39, count 0 2006.173.06:36:55.48#ibcon#wrote, iclass 39, count 0 2006.173.06:36:55.48#ibcon#about to read 3, iclass 39, count 0 2006.173.06:36:55.50#ibcon#read 3, iclass 39, count 0 2006.173.06:36:55.50#ibcon#about to read 4, iclass 39, count 0 2006.173.06:36:55.50#ibcon#read 4, iclass 39, count 0 2006.173.06:36:55.50#ibcon#about to read 5, iclass 39, count 0 2006.173.06:36:55.50#ibcon#read 5, iclass 39, count 0 2006.173.06:36:55.50#ibcon#about to read 6, iclass 39, count 0 2006.173.06:36:55.50#ibcon#read 6, iclass 39, count 0 2006.173.06:36:55.50#ibcon#end of sib2, iclass 39, count 0 2006.173.06:36:55.50#ibcon#*mode == 0, iclass 39, count 0 2006.173.06:36:55.50#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.06:36:55.50#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.06:36:55.50#ibcon#*before write, iclass 39, count 0 2006.173.06:36:55.50#ibcon#enter sib2, iclass 39, count 0 2006.173.06:36:55.50#ibcon#flushed, iclass 39, count 0 2006.173.06:36:55.50#ibcon#about to write, iclass 39, count 0 2006.173.06:36:55.50#ibcon#wrote, iclass 39, count 0 2006.173.06:36:55.50#ibcon#about to read 3, iclass 39, count 0 2006.173.06:36:55.54#ibcon#read 3, iclass 39, count 0 2006.173.06:36:55.54#ibcon#about to read 4, iclass 39, count 0 2006.173.06:36:55.54#ibcon#read 4, iclass 39, count 0 2006.173.06:36:55.54#ibcon#about to read 5, iclass 39, count 0 2006.173.06:36:55.54#ibcon#read 5, iclass 39, count 0 2006.173.06:36:55.54#ibcon#about to read 6, iclass 39, count 0 2006.173.06:36:55.54#ibcon#read 6, iclass 39, count 0 2006.173.06:36:55.54#ibcon#end of sib2, iclass 39, count 0 2006.173.06:36:55.54#ibcon#*after write, iclass 39, count 0 2006.173.06:36:55.54#ibcon#*before return 0, iclass 39, count 0 2006.173.06:36:55.54#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.06:36:55.54#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.06:36:55.54#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.06:36:55.54#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.06:36:55.54$vck44/vb=6,4 2006.173.06:36:55.54#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.06:36:55.54#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.06:36:55.54#ibcon#ireg 11 cls_cnt 2 2006.173.06:36:55.54#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.06:36:55.60#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.06:36:55.60#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.06:36:55.60#ibcon#enter wrdev, iclass 3, count 2 2006.173.06:36:55.60#ibcon#first serial, iclass 3, count 2 2006.173.06:36:55.60#ibcon#enter sib2, iclass 3, count 2 2006.173.06:36:55.60#ibcon#flushed, iclass 3, count 2 2006.173.06:36:55.60#ibcon#about to write, iclass 3, count 2 2006.173.06:36:55.60#ibcon#wrote, iclass 3, count 2 2006.173.06:36:55.60#ibcon#about to read 3, iclass 3, count 2 2006.173.06:36:55.62#ibcon#read 3, iclass 3, count 2 2006.173.06:36:55.62#ibcon#about to read 4, iclass 3, count 2 2006.173.06:36:55.62#ibcon#read 4, iclass 3, count 2 2006.173.06:36:55.62#ibcon#about to read 5, iclass 3, count 2 2006.173.06:36:55.62#ibcon#read 5, iclass 3, count 2 2006.173.06:36:55.62#ibcon#about to read 6, iclass 3, count 2 2006.173.06:36:55.62#ibcon#read 6, iclass 3, count 2 2006.173.06:36:55.62#ibcon#end of sib2, iclass 3, count 2 2006.173.06:36:55.62#ibcon#*mode == 0, iclass 3, count 2 2006.173.06:36:55.62#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.06:36:55.62#ibcon#[27=AT06-04\r\n] 2006.173.06:36:55.62#ibcon#*before write, iclass 3, count 2 2006.173.06:36:55.62#ibcon#enter sib2, iclass 3, count 2 2006.173.06:36:55.62#ibcon#flushed, iclass 3, count 2 2006.173.06:36:55.62#ibcon#about to write, iclass 3, count 2 2006.173.06:36:55.62#ibcon#wrote, iclass 3, count 2 2006.173.06:36:55.62#ibcon#about to read 3, iclass 3, count 2 2006.173.06:36:55.65#ibcon#read 3, iclass 3, count 2 2006.173.06:36:55.65#ibcon#about to read 4, iclass 3, count 2 2006.173.06:36:55.65#ibcon#read 4, iclass 3, count 2 2006.173.06:36:55.65#ibcon#about to read 5, iclass 3, count 2 2006.173.06:36:55.65#ibcon#read 5, iclass 3, count 2 2006.173.06:36:55.65#ibcon#about to read 6, iclass 3, count 2 2006.173.06:36:55.65#ibcon#read 6, iclass 3, count 2 2006.173.06:36:55.65#ibcon#end of sib2, iclass 3, count 2 2006.173.06:36:55.65#ibcon#*after write, iclass 3, count 2 2006.173.06:36:55.65#ibcon#*before return 0, iclass 3, count 2 2006.173.06:36:55.65#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.06:36:55.65#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.06:36:55.65#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.06:36:55.65#ibcon#ireg 7 cls_cnt 0 2006.173.06:36:55.65#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.06:36:55.77#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.06:36:55.77#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.06:36:55.77#ibcon#enter wrdev, iclass 3, count 0 2006.173.06:36:55.77#ibcon#first serial, iclass 3, count 0 2006.173.06:36:55.77#ibcon#enter sib2, iclass 3, count 0 2006.173.06:36:55.77#ibcon#flushed, iclass 3, count 0 2006.173.06:36:55.77#ibcon#about to write, iclass 3, count 0 2006.173.06:36:55.77#ibcon#wrote, iclass 3, count 0 2006.173.06:36:55.77#ibcon#about to read 3, iclass 3, count 0 2006.173.06:36:55.79#ibcon#read 3, iclass 3, count 0 2006.173.06:36:55.79#ibcon#about to read 4, iclass 3, count 0 2006.173.06:36:55.79#ibcon#read 4, iclass 3, count 0 2006.173.06:36:55.79#ibcon#about to read 5, iclass 3, count 0 2006.173.06:36:55.79#ibcon#read 5, iclass 3, count 0 2006.173.06:36:55.79#ibcon#about to read 6, iclass 3, count 0 2006.173.06:36:55.79#ibcon#read 6, iclass 3, count 0 2006.173.06:36:55.79#ibcon#end of sib2, iclass 3, count 0 2006.173.06:36:55.79#ibcon#*mode == 0, iclass 3, count 0 2006.173.06:36:55.79#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.06:36:55.79#ibcon#[27=USB\r\n] 2006.173.06:36:55.79#ibcon#*before write, iclass 3, count 0 2006.173.06:36:55.79#ibcon#enter sib2, iclass 3, count 0 2006.173.06:36:55.79#ibcon#flushed, iclass 3, count 0 2006.173.06:36:55.79#ibcon#about to write, iclass 3, count 0 2006.173.06:36:55.79#ibcon#wrote, iclass 3, count 0 2006.173.06:36:55.79#ibcon#about to read 3, iclass 3, count 0 2006.173.06:36:55.82#ibcon#read 3, iclass 3, count 0 2006.173.06:36:55.82#ibcon#about to read 4, iclass 3, count 0 2006.173.06:36:55.82#ibcon#read 4, iclass 3, count 0 2006.173.06:36:55.82#ibcon#about to read 5, iclass 3, count 0 2006.173.06:36:55.82#ibcon#read 5, iclass 3, count 0 2006.173.06:36:55.82#ibcon#about to read 6, iclass 3, count 0 2006.173.06:36:55.82#ibcon#read 6, iclass 3, count 0 2006.173.06:36:55.82#ibcon#end of sib2, iclass 3, count 0 2006.173.06:36:55.82#ibcon#*after write, iclass 3, count 0 2006.173.06:36:55.82#ibcon#*before return 0, iclass 3, count 0 2006.173.06:36:55.82#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.06:36:55.82#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.06:36:55.82#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.06:36:55.82#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.06:36:55.82$vck44/vblo=7,734.99 2006.173.06:36:55.82#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.06:36:55.82#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.06:36:55.82#ibcon#ireg 17 cls_cnt 0 2006.173.06:36:55.82#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.06:36:55.82#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.06:36:55.82#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.06:36:55.82#ibcon#enter wrdev, iclass 5, count 0 2006.173.06:36:55.82#ibcon#first serial, iclass 5, count 0 2006.173.06:36:55.82#ibcon#enter sib2, iclass 5, count 0 2006.173.06:36:55.82#ibcon#flushed, iclass 5, count 0 2006.173.06:36:55.82#ibcon#about to write, iclass 5, count 0 2006.173.06:36:55.82#ibcon#wrote, iclass 5, count 0 2006.173.06:36:55.82#ibcon#about to read 3, iclass 5, count 0 2006.173.06:36:55.84#ibcon#read 3, iclass 5, count 0 2006.173.06:36:55.84#ibcon#about to read 4, iclass 5, count 0 2006.173.06:36:55.84#ibcon#read 4, iclass 5, count 0 2006.173.06:36:55.84#ibcon#about to read 5, iclass 5, count 0 2006.173.06:36:55.84#ibcon#read 5, iclass 5, count 0 2006.173.06:36:55.84#ibcon#about to read 6, iclass 5, count 0 2006.173.06:36:55.84#ibcon#read 6, iclass 5, count 0 2006.173.06:36:55.84#ibcon#end of sib2, iclass 5, count 0 2006.173.06:36:55.84#ibcon#*mode == 0, iclass 5, count 0 2006.173.06:36:55.84#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.06:36:55.84#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.06:36:55.84#ibcon#*before write, iclass 5, count 0 2006.173.06:36:55.84#ibcon#enter sib2, iclass 5, count 0 2006.173.06:36:55.84#ibcon#flushed, iclass 5, count 0 2006.173.06:36:55.84#ibcon#about to write, iclass 5, count 0 2006.173.06:36:55.84#ibcon#wrote, iclass 5, count 0 2006.173.06:36:55.84#ibcon#about to read 3, iclass 5, count 0 2006.173.06:36:55.88#ibcon#read 3, iclass 5, count 0 2006.173.06:36:55.88#ibcon#about to read 4, iclass 5, count 0 2006.173.06:36:55.88#ibcon#read 4, iclass 5, count 0 2006.173.06:36:55.88#ibcon#about to read 5, iclass 5, count 0 2006.173.06:36:55.88#ibcon#read 5, iclass 5, count 0 2006.173.06:36:55.88#ibcon#about to read 6, iclass 5, count 0 2006.173.06:36:55.88#ibcon#read 6, iclass 5, count 0 2006.173.06:36:55.88#ibcon#end of sib2, iclass 5, count 0 2006.173.06:36:55.88#ibcon#*after write, iclass 5, count 0 2006.173.06:36:55.88#ibcon#*before return 0, iclass 5, count 0 2006.173.06:36:55.88#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.06:36:55.88#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.06:36:55.88#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.06:36:55.88#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.06:36:55.88$vck44/vb=7,4 2006.173.06:36:55.88#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.173.06:36:55.88#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.173.06:36:55.88#ibcon#ireg 11 cls_cnt 2 2006.173.06:36:55.88#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.06:36:55.94#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.06:36:55.94#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.06:36:55.94#ibcon#enter wrdev, iclass 7, count 2 2006.173.06:36:55.94#ibcon#first serial, iclass 7, count 2 2006.173.06:36:55.94#ibcon#enter sib2, iclass 7, count 2 2006.173.06:36:55.94#ibcon#flushed, iclass 7, count 2 2006.173.06:36:55.94#ibcon#about to write, iclass 7, count 2 2006.173.06:36:55.94#ibcon#wrote, iclass 7, count 2 2006.173.06:36:55.94#ibcon#about to read 3, iclass 7, count 2 2006.173.06:36:55.96#ibcon#read 3, iclass 7, count 2 2006.173.06:36:55.96#ibcon#about to read 4, iclass 7, count 2 2006.173.06:36:55.96#ibcon#read 4, iclass 7, count 2 2006.173.06:36:55.96#ibcon#about to read 5, iclass 7, count 2 2006.173.06:36:55.96#ibcon#read 5, iclass 7, count 2 2006.173.06:36:55.96#ibcon#about to read 6, iclass 7, count 2 2006.173.06:36:55.96#ibcon#read 6, iclass 7, count 2 2006.173.06:36:55.96#ibcon#end of sib2, iclass 7, count 2 2006.173.06:36:55.96#ibcon#*mode == 0, iclass 7, count 2 2006.173.06:36:55.96#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.173.06:36:55.96#ibcon#[27=AT07-04\r\n] 2006.173.06:36:55.96#ibcon#*before write, iclass 7, count 2 2006.173.06:36:55.96#ibcon#enter sib2, iclass 7, count 2 2006.173.06:36:55.96#ibcon#flushed, iclass 7, count 2 2006.173.06:36:55.96#ibcon#about to write, iclass 7, count 2 2006.173.06:36:55.96#ibcon#wrote, iclass 7, count 2 2006.173.06:36:55.96#ibcon#about to read 3, iclass 7, count 2 2006.173.06:36:55.99#ibcon#read 3, iclass 7, count 2 2006.173.06:36:55.99#ibcon#about to read 4, iclass 7, count 2 2006.173.06:36:55.99#ibcon#read 4, iclass 7, count 2 2006.173.06:36:55.99#ibcon#about to read 5, iclass 7, count 2 2006.173.06:36:55.99#ibcon#read 5, iclass 7, count 2 2006.173.06:36:55.99#ibcon#about to read 6, iclass 7, count 2 2006.173.06:36:55.99#ibcon#read 6, iclass 7, count 2 2006.173.06:36:55.99#ibcon#end of sib2, iclass 7, count 2 2006.173.06:36:55.99#ibcon#*after write, iclass 7, count 2 2006.173.06:36:55.99#ibcon#*before return 0, iclass 7, count 2 2006.173.06:36:55.99#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.06:36:55.99#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.173.06:36:55.99#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.173.06:36:55.99#ibcon#ireg 7 cls_cnt 0 2006.173.06:36:55.99#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.06:36:56.11#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.06:36:56.11#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.06:36:56.11#ibcon#enter wrdev, iclass 7, count 0 2006.173.06:36:56.11#ibcon#first serial, iclass 7, count 0 2006.173.06:36:56.11#ibcon#enter sib2, iclass 7, count 0 2006.173.06:36:56.11#ibcon#flushed, iclass 7, count 0 2006.173.06:36:56.11#ibcon#about to write, iclass 7, count 0 2006.173.06:36:56.11#ibcon#wrote, iclass 7, count 0 2006.173.06:36:56.11#ibcon#about to read 3, iclass 7, count 0 2006.173.06:36:56.13#ibcon#read 3, iclass 7, count 0 2006.173.06:36:56.13#ibcon#about to read 4, iclass 7, count 0 2006.173.06:36:56.13#ibcon#read 4, iclass 7, count 0 2006.173.06:36:56.13#ibcon#about to read 5, iclass 7, count 0 2006.173.06:36:56.13#ibcon#read 5, iclass 7, count 0 2006.173.06:36:56.13#ibcon#about to read 6, iclass 7, count 0 2006.173.06:36:56.13#ibcon#read 6, iclass 7, count 0 2006.173.06:36:56.13#ibcon#end of sib2, iclass 7, count 0 2006.173.06:36:56.13#ibcon#*mode == 0, iclass 7, count 0 2006.173.06:36:56.13#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.06:36:56.13#ibcon#[27=USB\r\n] 2006.173.06:36:56.13#ibcon#*before write, iclass 7, count 0 2006.173.06:36:56.13#ibcon#enter sib2, iclass 7, count 0 2006.173.06:36:56.13#ibcon#flushed, iclass 7, count 0 2006.173.06:36:56.13#ibcon#about to write, iclass 7, count 0 2006.173.06:36:56.13#ibcon#wrote, iclass 7, count 0 2006.173.06:36:56.13#ibcon#about to read 3, iclass 7, count 0 2006.173.06:36:56.16#ibcon#read 3, iclass 7, count 0 2006.173.06:36:56.16#ibcon#about to read 4, iclass 7, count 0 2006.173.06:36:56.16#ibcon#read 4, iclass 7, count 0 2006.173.06:36:56.16#ibcon#about to read 5, iclass 7, count 0 2006.173.06:36:56.16#ibcon#read 5, iclass 7, count 0 2006.173.06:36:56.16#ibcon#about to read 6, iclass 7, count 0 2006.173.06:36:56.16#ibcon#read 6, iclass 7, count 0 2006.173.06:36:56.16#ibcon#end of sib2, iclass 7, count 0 2006.173.06:36:56.16#ibcon#*after write, iclass 7, count 0 2006.173.06:36:56.16#ibcon#*before return 0, iclass 7, count 0 2006.173.06:36:56.16#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.06:36:56.16#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.173.06:36:56.16#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.06:36:56.16#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.06:36:56.16$vck44/vblo=8,744.99 2006.173.06:36:56.16#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.06:36:56.16#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.06:36:56.16#ibcon#ireg 17 cls_cnt 0 2006.173.06:36:56.16#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.06:36:56.16#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.06:36:56.16#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.06:36:56.16#ibcon#enter wrdev, iclass 11, count 0 2006.173.06:36:56.16#ibcon#first serial, iclass 11, count 0 2006.173.06:36:56.16#ibcon#enter sib2, iclass 11, count 0 2006.173.06:36:56.16#ibcon#flushed, iclass 11, count 0 2006.173.06:36:56.16#ibcon#about to write, iclass 11, count 0 2006.173.06:36:56.16#ibcon#wrote, iclass 11, count 0 2006.173.06:36:56.16#ibcon#about to read 3, iclass 11, count 0 2006.173.06:36:56.18#ibcon#read 3, iclass 11, count 0 2006.173.06:36:56.18#ibcon#about to read 4, iclass 11, count 0 2006.173.06:36:56.18#ibcon#read 4, iclass 11, count 0 2006.173.06:36:56.18#ibcon#about to read 5, iclass 11, count 0 2006.173.06:36:56.18#ibcon#read 5, iclass 11, count 0 2006.173.06:36:56.18#ibcon#about to read 6, iclass 11, count 0 2006.173.06:36:56.18#ibcon#read 6, iclass 11, count 0 2006.173.06:36:56.18#ibcon#end of sib2, iclass 11, count 0 2006.173.06:36:56.18#ibcon#*mode == 0, iclass 11, count 0 2006.173.06:36:56.18#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.06:36:56.18#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.06:36:56.18#ibcon#*before write, iclass 11, count 0 2006.173.06:36:56.18#ibcon#enter sib2, iclass 11, count 0 2006.173.06:36:56.18#ibcon#flushed, iclass 11, count 0 2006.173.06:36:56.18#ibcon#about to write, iclass 11, count 0 2006.173.06:36:56.18#ibcon#wrote, iclass 11, count 0 2006.173.06:36:56.18#ibcon#about to read 3, iclass 11, count 0 2006.173.06:36:56.22#ibcon#read 3, iclass 11, count 0 2006.173.06:36:56.22#ibcon#about to read 4, iclass 11, count 0 2006.173.06:36:56.22#ibcon#read 4, iclass 11, count 0 2006.173.06:36:56.22#ibcon#about to read 5, iclass 11, count 0 2006.173.06:36:56.22#ibcon#read 5, iclass 11, count 0 2006.173.06:36:56.22#ibcon#about to read 6, iclass 11, count 0 2006.173.06:36:56.22#ibcon#read 6, iclass 11, count 0 2006.173.06:36:56.22#ibcon#end of sib2, iclass 11, count 0 2006.173.06:36:56.22#ibcon#*after write, iclass 11, count 0 2006.173.06:36:56.22#ibcon#*before return 0, iclass 11, count 0 2006.173.06:36:56.22#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.06:36:56.22#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.06:36:56.22#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.06:36:56.22#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.06:36:56.22$vck44/vb=8,4 2006.173.06:36:56.22#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.173.06:36:56.22#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.173.06:36:56.22#ibcon#ireg 11 cls_cnt 2 2006.173.06:36:56.22#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.06:36:56.28#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.06:36:56.28#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.06:36:56.28#ibcon#enter wrdev, iclass 13, count 2 2006.173.06:36:56.28#ibcon#first serial, iclass 13, count 2 2006.173.06:36:56.28#ibcon#enter sib2, iclass 13, count 2 2006.173.06:36:56.28#ibcon#flushed, iclass 13, count 2 2006.173.06:36:56.28#ibcon#about to write, iclass 13, count 2 2006.173.06:36:56.28#ibcon#wrote, iclass 13, count 2 2006.173.06:36:56.28#ibcon#about to read 3, iclass 13, count 2 2006.173.06:36:56.30#ibcon#read 3, iclass 13, count 2 2006.173.06:36:56.30#ibcon#about to read 4, iclass 13, count 2 2006.173.06:36:56.30#ibcon#read 4, iclass 13, count 2 2006.173.06:36:56.30#ibcon#about to read 5, iclass 13, count 2 2006.173.06:36:56.30#ibcon#read 5, iclass 13, count 2 2006.173.06:36:56.30#ibcon#about to read 6, iclass 13, count 2 2006.173.06:36:56.30#ibcon#read 6, iclass 13, count 2 2006.173.06:36:56.30#ibcon#end of sib2, iclass 13, count 2 2006.173.06:36:56.30#ibcon#*mode == 0, iclass 13, count 2 2006.173.06:36:56.30#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.173.06:36:56.30#ibcon#[27=AT08-04\r\n] 2006.173.06:36:56.30#ibcon#*before write, iclass 13, count 2 2006.173.06:36:56.30#ibcon#enter sib2, iclass 13, count 2 2006.173.06:36:56.30#ibcon#flushed, iclass 13, count 2 2006.173.06:36:56.30#ibcon#about to write, iclass 13, count 2 2006.173.06:36:56.30#ibcon#wrote, iclass 13, count 2 2006.173.06:36:56.30#ibcon#about to read 3, iclass 13, count 2 2006.173.06:36:56.33#ibcon#read 3, iclass 13, count 2 2006.173.06:36:56.33#ibcon#about to read 4, iclass 13, count 2 2006.173.06:36:56.33#ibcon#read 4, iclass 13, count 2 2006.173.06:36:56.33#ibcon#about to read 5, iclass 13, count 2 2006.173.06:36:56.33#ibcon#read 5, iclass 13, count 2 2006.173.06:36:56.33#ibcon#about to read 6, iclass 13, count 2 2006.173.06:36:56.33#ibcon#read 6, iclass 13, count 2 2006.173.06:36:56.33#ibcon#end of sib2, iclass 13, count 2 2006.173.06:36:56.33#ibcon#*after write, iclass 13, count 2 2006.173.06:36:56.33#ibcon#*before return 0, iclass 13, count 2 2006.173.06:36:56.33#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.06:36:56.33#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.173.06:36:56.33#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.173.06:36:56.33#ibcon#ireg 7 cls_cnt 0 2006.173.06:36:56.33#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.06:36:56.45#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.06:36:56.45#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.06:36:56.45#ibcon#enter wrdev, iclass 13, count 0 2006.173.06:36:56.45#ibcon#first serial, iclass 13, count 0 2006.173.06:36:56.45#ibcon#enter sib2, iclass 13, count 0 2006.173.06:36:56.45#ibcon#flushed, iclass 13, count 0 2006.173.06:36:56.45#ibcon#about to write, iclass 13, count 0 2006.173.06:36:56.45#ibcon#wrote, iclass 13, count 0 2006.173.06:36:56.45#ibcon#about to read 3, iclass 13, count 0 2006.173.06:36:56.47#ibcon#read 3, iclass 13, count 0 2006.173.06:36:56.47#ibcon#about to read 4, iclass 13, count 0 2006.173.06:36:56.47#ibcon#read 4, iclass 13, count 0 2006.173.06:36:56.47#ibcon#about to read 5, iclass 13, count 0 2006.173.06:36:56.47#ibcon#read 5, iclass 13, count 0 2006.173.06:36:56.47#ibcon#about to read 6, iclass 13, count 0 2006.173.06:36:56.47#ibcon#read 6, iclass 13, count 0 2006.173.06:36:56.47#ibcon#end of sib2, iclass 13, count 0 2006.173.06:36:56.47#ibcon#*mode == 0, iclass 13, count 0 2006.173.06:36:56.47#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.06:36:56.47#ibcon#[27=USB\r\n] 2006.173.06:36:56.47#ibcon#*before write, iclass 13, count 0 2006.173.06:36:56.47#ibcon#enter sib2, iclass 13, count 0 2006.173.06:36:56.47#ibcon#flushed, iclass 13, count 0 2006.173.06:36:56.47#ibcon#about to write, iclass 13, count 0 2006.173.06:36:56.47#ibcon#wrote, iclass 13, count 0 2006.173.06:36:56.47#ibcon#about to read 3, iclass 13, count 0 2006.173.06:36:56.50#ibcon#read 3, iclass 13, count 0 2006.173.06:36:56.50#ibcon#about to read 4, iclass 13, count 0 2006.173.06:36:56.50#ibcon#read 4, iclass 13, count 0 2006.173.06:36:56.50#ibcon#about to read 5, iclass 13, count 0 2006.173.06:36:56.50#ibcon#read 5, iclass 13, count 0 2006.173.06:36:56.50#ibcon#about to read 6, iclass 13, count 0 2006.173.06:36:56.50#ibcon#read 6, iclass 13, count 0 2006.173.06:36:56.50#ibcon#end of sib2, iclass 13, count 0 2006.173.06:36:56.50#ibcon#*after write, iclass 13, count 0 2006.173.06:36:56.50#ibcon#*before return 0, iclass 13, count 0 2006.173.06:36:56.50#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.06:36:56.50#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.173.06:36:56.50#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.06:36:56.50#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.06:36:56.50$vck44/vabw=wide 2006.173.06:36:56.50#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.06:36:56.50#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.06:36:56.50#ibcon#ireg 8 cls_cnt 0 2006.173.06:36:56.50#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.06:36:56.50#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.06:36:56.50#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.06:36:56.50#ibcon#enter wrdev, iclass 15, count 0 2006.173.06:36:56.50#ibcon#first serial, iclass 15, count 0 2006.173.06:36:56.50#ibcon#enter sib2, iclass 15, count 0 2006.173.06:36:56.50#ibcon#flushed, iclass 15, count 0 2006.173.06:36:56.50#ibcon#about to write, iclass 15, count 0 2006.173.06:36:56.50#ibcon#wrote, iclass 15, count 0 2006.173.06:36:56.50#ibcon#about to read 3, iclass 15, count 0 2006.173.06:36:56.52#ibcon#read 3, iclass 15, count 0 2006.173.06:36:56.52#ibcon#about to read 4, iclass 15, count 0 2006.173.06:36:56.52#ibcon#read 4, iclass 15, count 0 2006.173.06:36:56.52#ibcon#about to read 5, iclass 15, count 0 2006.173.06:36:56.52#ibcon#read 5, iclass 15, count 0 2006.173.06:36:56.52#ibcon#about to read 6, iclass 15, count 0 2006.173.06:36:56.52#ibcon#read 6, iclass 15, count 0 2006.173.06:36:56.52#ibcon#end of sib2, iclass 15, count 0 2006.173.06:36:56.52#ibcon#*mode == 0, iclass 15, count 0 2006.173.06:36:56.52#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.06:36:56.52#ibcon#[25=BW32\r\n] 2006.173.06:36:56.52#ibcon#*before write, iclass 15, count 0 2006.173.06:36:56.52#ibcon#enter sib2, iclass 15, count 0 2006.173.06:36:56.52#ibcon#flushed, iclass 15, count 0 2006.173.06:36:56.52#ibcon#about to write, iclass 15, count 0 2006.173.06:36:56.52#ibcon#wrote, iclass 15, count 0 2006.173.06:36:56.52#ibcon#about to read 3, iclass 15, count 0 2006.173.06:36:56.55#ibcon#read 3, iclass 15, count 0 2006.173.06:36:56.55#ibcon#about to read 4, iclass 15, count 0 2006.173.06:36:56.55#ibcon#read 4, iclass 15, count 0 2006.173.06:36:56.55#ibcon#about to read 5, iclass 15, count 0 2006.173.06:36:56.55#ibcon#read 5, iclass 15, count 0 2006.173.06:36:56.55#ibcon#about to read 6, iclass 15, count 0 2006.173.06:36:56.55#ibcon#read 6, iclass 15, count 0 2006.173.06:36:56.55#ibcon#end of sib2, iclass 15, count 0 2006.173.06:36:56.55#ibcon#*after write, iclass 15, count 0 2006.173.06:36:56.55#ibcon#*before return 0, iclass 15, count 0 2006.173.06:36:56.55#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.06:36:56.55#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.06:36:56.55#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.06:36:56.55#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.06:36:56.55$vck44/vbbw=wide 2006.173.06:36:56.55#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.06:36:56.55#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.06:36:56.55#ibcon#ireg 8 cls_cnt 0 2006.173.06:36:56.55#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.06:36:56.62#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.06:36:56.62#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.06:36:56.62#ibcon#enter wrdev, iclass 17, count 0 2006.173.06:36:56.62#ibcon#first serial, iclass 17, count 0 2006.173.06:36:56.62#ibcon#enter sib2, iclass 17, count 0 2006.173.06:36:56.62#ibcon#flushed, iclass 17, count 0 2006.173.06:36:56.62#ibcon#about to write, iclass 17, count 0 2006.173.06:36:56.62#ibcon#wrote, iclass 17, count 0 2006.173.06:36:56.62#ibcon#about to read 3, iclass 17, count 0 2006.173.06:36:56.64#ibcon#read 3, iclass 17, count 0 2006.173.06:36:56.64#ibcon#about to read 4, iclass 17, count 0 2006.173.06:36:56.64#ibcon#read 4, iclass 17, count 0 2006.173.06:36:56.64#ibcon#about to read 5, iclass 17, count 0 2006.173.06:36:56.64#ibcon#read 5, iclass 17, count 0 2006.173.06:36:56.64#ibcon#about to read 6, iclass 17, count 0 2006.173.06:36:56.64#ibcon#read 6, iclass 17, count 0 2006.173.06:36:56.64#ibcon#end of sib2, iclass 17, count 0 2006.173.06:36:56.64#ibcon#*mode == 0, iclass 17, count 0 2006.173.06:36:56.64#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.06:36:56.64#ibcon#[27=BW32\r\n] 2006.173.06:36:56.64#ibcon#*before write, iclass 17, count 0 2006.173.06:36:56.64#ibcon#enter sib2, iclass 17, count 0 2006.173.06:36:56.64#ibcon#flushed, iclass 17, count 0 2006.173.06:36:56.64#ibcon#about to write, iclass 17, count 0 2006.173.06:36:56.64#ibcon#wrote, iclass 17, count 0 2006.173.06:36:56.64#ibcon#about to read 3, iclass 17, count 0 2006.173.06:36:56.67#ibcon#read 3, iclass 17, count 0 2006.173.06:36:56.67#ibcon#about to read 4, iclass 17, count 0 2006.173.06:36:56.67#ibcon#read 4, iclass 17, count 0 2006.173.06:36:56.67#ibcon#about to read 5, iclass 17, count 0 2006.173.06:36:56.67#ibcon#read 5, iclass 17, count 0 2006.173.06:36:56.67#ibcon#about to read 6, iclass 17, count 0 2006.173.06:36:56.67#ibcon#read 6, iclass 17, count 0 2006.173.06:36:56.67#ibcon#end of sib2, iclass 17, count 0 2006.173.06:36:56.67#ibcon#*after write, iclass 17, count 0 2006.173.06:36:56.67#ibcon#*before return 0, iclass 17, count 0 2006.173.06:36:56.67#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.06:36:56.67#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.06:36:56.67#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.06:36:56.67#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.06:36:56.67$setupk4/ifdk4 2006.173.06:36:56.67$ifdk4/lo= 2006.173.06:36:56.67$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.06:36:56.68$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.06:36:56.68$ifdk4/patch= 2006.173.06:36:56.68$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.06:36:56.68$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.06:36:56.68$setupk4/!*+20s 2006.173.06:37:04.96#abcon#<5=/15 0.6 1.0 23.78 791005.0\r\n> 2006.173.06:37:04.98#abcon#{5=INTERFACE CLEAR} 2006.173.06:37:05.04#abcon#[5=S1D000X0/0*\r\n] 2006.173.06:37:11.20$setupk4/"tpicd 2006.173.06:37:11.20$setupk4/echo=off 2006.173.06:37:11.20$setupk4/xlog=off 2006.173.06:37:11.20:!2006.173.06:38:48 2006.173.06:37:26.13#trakl#Source acquired 2006.173.06:37:28.13#flagr#flagr/antenna,acquired 2006.173.06:38:48.00:preob 2006.173.06:38:48.13/onsource/TRACKING 2006.173.06:38:48.13:!2006.173.06:38:58 2006.173.06:38:58.00:"tape 2006.173.06:38:58.00:"st=record 2006.173.06:38:58.00:data_valid=on 2006.173.06:38:58.00:midob 2006.173.06:38:58.14/onsource/TRACKING 2006.173.06:38:58.15/wx/23.76,1005.0,79 2006.173.06:38:58.20/cable/+6.5034E-03 2006.173.06:38:59.29/va/01,07,usb,yes,37,40 2006.173.06:38:59.29/va/02,06,usb,yes,37,38 2006.173.06:38:59.29/va/03,05,usb,yes,47,49 2006.173.06:38:59.29/va/04,06,usb,yes,38,40 2006.173.06:38:59.29/va/05,04,usb,yes,30,30 2006.173.06:38:59.29/va/06,03,usb,yes,42,41 2006.173.06:38:59.29/va/07,04,usb,yes,34,35 2006.173.06:38:59.29/va/08,04,usb,yes,29,35 2006.173.06:38:59.52/valo/01,524.99,yes,locked 2006.173.06:38:59.52/valo/02,534.99,yes,locked 2006.173.06:38:59.52/valo/03,564.99,yes,locked 2006.173.06:38:59.52/valo/04,624.99,yes,locked 2006.173.06:38:59.52/valo/05,734.99,yes,locked 2006.173.06:38:59.52/valo/06,814.99,yes,locked 2006.173.06:38:59.52/valo/07,864.99,yes,locked 2006.173.06:38:59.52/valo/08,884.99,yes,locked 2006.173.06:39:00.61/vb/01,04,usb,yes,30,28 2006.173.06:39:00.61/vb/02,04,usb,yes,32,32 2006.173.06:39:00.61/vb/03,04,usb,yes,29,32 2006.173.06:39:00.61/vb/04,04,usb,yes,33,32 2006.173.06:39:00.61/vb/05,04,usb,yes,26,28 2006.173.06:39:00.61/vb/06,04,usb,yes,31,27 2006.173.06:39:00.61/vb/07,04,usb,yes,30,30 2006.173.06:39:00.61/vb/08,04,usb,yes,28,31 2006.173.06:39:00.85/vblo/01,629.99,yes,locked 2006.173.06:39:00.85/vblo/02,634.99,yes,locked 2006.173.06:39:00.85/vblo/03,649.99,yes,locked 2006.173.06:39:00.85/vblo/04,679.99,yes,locked 2006.173.06:39:00.85/vblo/05,709.99,yes,locked 2006.173.06:39:00.85/vblo/06,719.99,yes,locked 2006.173.06:39:00.85/vblo/07,734.99,yes,locked 2006.173.06:39:00.85/vblo/08,744.99,yes,locked 2006.173.06:39:01.00/vabw/8 2006.173.06:39:01.15/vbbw/8 2006.173.06:39:01.28/xfe/off,on,14.7 2006.173.06:39:01.65/ifatt/23,28,28,28 2006.173.06:39:02.07/fmout-gps/S +3.99E-07 2006.173.06:39:02.12:!2006.173.06:40:58 2006.173.06:40:58.01:data_valid=off 2006.173.06:40:58.02:"et 2006.173.06:40:58.02:!+3s 2006.173.06:41:01.03:"tape 2006.173.06:41:01.04:postob 2006.173.06:41:01.25/cable/+6.5025E-03 2006.173.06:41:01.26/wx/23.73,1005.0,80 2006.173.06:41:01.31/fmout-gps/S +4.01E-07 2006.173.06:41:01.32:scan_name=173-0642,jd0606,90 2006.173.06:41:01.32:source=3c274,123049.42,122328.0,2000.0,ccw 2006.173.06:41:02.14#flagr#flagr/antenna,new-source 2006.173.06:41:02.15:checkk5 2006.173.06:41:02.55/chk_autoobs//k5ts1/ autoobs is running! 2006.173.06:41:02.95/chk_autoobs//k5ts2/ autoobs is running! 2006.173.06:41:03.35/chk_autoobs//k5ts3/ autoobs is running! 2006.173.06:41:03.75/chk_autoobs//k5ts4/ autoobs is running! 2006.173.06:41:04.15/chk_obsdata//k5ts1/T1730638??a.dat file size is correct (nominal:480MB, actual:476MB). 2006.173.06:41:04.55/chk_obsdata//k5ts2/T1730638??b.dat file size is correct (nominal:480MB, actual:476MB). 2006.173.06:41:04.95/chk_obsdata//k5ts3/T1730638??c.dat file size is correct (nominal:480MB, actual:476MB). 2006.173.06:41:05.35/chk_obsdata//k5ts4/T1730638??d.dat file size is correct (nominal:480MB, actual:476MB). 2006.173.06:41:06.07/k5log//k5ts1_log_newline 2006.173.06:41:06.79/k5log//k5ts2_log_newline 2006.173.06:41:07.51/k5log//k5ts3_log_newline 2006.173.06:41:08.22/k5log//k5ts4_log_newline 2006.173.06:41:08.24/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.06:41:08.24:setupk4=1 2006.173.06:41:08.24$setupk4/echo=on 2006.173.06:41:08.24$setupk4/pcalon 2006.173.06:41:08.24$pcalon/"no phase cal control is implemented here 2006.173.06:41:08.24$setupk4/"tpicd=stop 2006.173.06:41:08.24$setupk4/"rec=synch_on 2006.173.06:41:08.24$setupk4/"rec_mode=128 2006.173.06:41:08.24$setupk4/!* 2006.173.06:41:08.24$setupk4/recpk4 2006.173.06:41:08.24$recpk4/recpatch= 2006.173.06:41:08.25$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.06:41:08.25$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.06:41:08.25$setupk4/vck44 2006.173.06:41:08.25$vck44/valo=1,524.99 2006.173.06:41:08.25#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.06:41:08.25#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.06:41:08.25#ibcon#ireg 17 cls_cnt 0 2006.173.06:41:08.25#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.06:41:08.25#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.06:41:08.25#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.06:41:08.25#ibcon#enter wrdev, iclass 10, count 0 2006.173.06:41:08.25#ibcon#first serial, iclass 10, count 0 2006.173.06:41:08.25#ibcon#enter sib2, iclass 10, count 0 2006.173.06:41:08.25#ibcon#flushed, iclass 10, count 0 2006.173.06:41:08.25#ibcon#about to write, iclass 10, count 0 2006.173.06:41:08.25#ibcon#wrote, iclass 10, count 0 2006.173.06:41:08.25#ibcon#about to read 3, iclass 10, count 0 2006.173.06:41:08.26#ibcon#read 3, iclass 10, count 0 2006.173.06:41:08.26#ibcon#about to read 4, iclass 10, count 0 2006.173.06:41:08.26#ibcon#read 4, iclass 10, count 0 2006.173.06:41:08.26#ibcon#about to read 5, iclass 10, count 0 2006.173.06:41:08.26#ibcon#read 5, iclass 10, count 0 2006.173.06:41:08.26#ibcon#about to read 6, iclass 10, count 0 2006.173.06:41:08.26#ibcon#read 6, iclass 10, count 0 2006.173.06:41:08.26#ibcon#end of sib2, iclass 10, count 0 2006.173.06:41:08.26#ibcon#*mode == 0, iclass 10, count 0 2006.173.06:41:08.26#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.06:41:08.26#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.06:41:08.26#ibcon#*before write, iclass 10, count 0 2006.173.06:41:08.26#ibcon#enter sib2, iclass 10, count 0 2006.173.06:41:08.26#ibcon#flushed, iclass 10, count 0 2006.173.06:41:08.26#ibcon#about to write, iclass 10, count 0 2006.173.06:41:08.26#ibcon#wrote, iclass 10, count 0 2006.173.06:41:08.26#ibcon#about to read 3, iclass 10, count 0 2006.173.06:41:08.31#ibcon#read 3, iclass 10, count 0 2006.173.06:41:08.31#ibcon#about to read 4, iclass 10, count 0 2006.173.06:41:08.31#ibcon#read 4, iclass 10, count 0 2006.173.06:41:08.31#ibcon#about to read 5, iclass 10, count 0 2006.173.06:41:08.31#ibcon#read 5, iclass 10, count 0 2006.173.06:41:08.31#ibcon#about to read 6, iclass 10, count 0 2006.173.06:41:08.31#ibcon#read 6, iclass 10, count 0 2006.173.06:41:08.31#ibcon#end of sib2, iclass 10, count 0 2006.173.06:41:08.31#ibcon#*after write, iclass 10, count 0 2006.173.06:41:08.31#ibcon#*before return 0, iclass 10, count 0 2006.173.06:41:08.31#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.06:41:08.31#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.06:41:08.31#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.06:41:08.31#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.06:41:08.31$vck44/va=1,7 2006.173.06:41:08.31#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.06:41:08.31#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.06:41:08.31#ibcon#ireg 11 cls_cnt 2 2006.173.06:41:08.31#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.06:41:08.31#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.06:41:08.31#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.06:41:08.31#ibcon#enter wrdev, iclass 12, count 2 2006.173.06:41:08.31#ibcon#first serial, iclass 12, count 2 2006.173.06:41:08.31#ibcon#enter sib2, iclass 12, count 2 2006.173.06:41:08.31#ibcon#flushed, iclass 12, count 2 2006.173.06:41:08.31#ibcon#about to write, iclass 12, count 2 2006.173.06:41:08.31#ibcon#wrote, iclass 12, count 2 2006.173.06:41:08.31#ibcon#about to read 3, iclass 12, count 2 2006.173.06:41:08.33#ibcon#read 3, iclass 12, count 2 2006.173.06:41:08.33#ibcon#about to read 4, iclass 12, count 2 2006.173.06:41:08.33#ibcon#read 4, iclass 12, count 2 2006.173.06:41:08.33#ibcon#about to read 5, iclass 12, count 2 2006.173.06:41:08.33#ibcon#read 5, iclass 12, count 2 2006.173.06:41:08.33#ibcon#about to read 6, iclass 12, count 2 2006.173.06:41:08.33#ibcon#read 6, iclass 12, count 2 2006.173.06:41:08.33#ibcon#end of sib2, iclass 12, count 2 2006.173.06:41:08.33#ibcon#*mode == 0, iclass 12, count 2 2006.173.06:41:08.33#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.06:41:08.33#ibcon#[25=AT01-07\r\n] 2006.173.06:41:08.33#ibcon#*before write, iclass 12, count 2 2006.173.06:41:08.33#ibcon#enter sib2, iclass 12, count 2 2006.173.06:41:08.33#ibcon#flushed, iclass 12, count 2 2006.173.06:41:08.33#ibcon#about to write, iclass 12, count 2 2006.173.06:41:08.33#ibcon#wrote, iclass 12, count 2 2006.173.06:41:08.33#ibcon#about to read 3, iclass 12, count 2 2006.173.06:41:08.36#ibcon#read 3, iclass 12, count 2 2006.173.06:41:08.36#ibcon#about to read 4, iclass 12, count 2 2006.173.06:41:08.36#ibcon#read 4, iclass 12, count 2 2006.173.06:41:08.36#ibcon#about to read 5, iclass 12, count 2 2006.173.06:41:08.36#ibcon#read 5, iclass 12, count 2 2006.173.06:41:08.36#ibcon#about to read 6, iclass 12, count 2 2006.173.06:41:08.36#ibcon#read 6, iclass 12, count 2 2006.173.06:41:08.36#ibcon#end of sib2, iclass 12, count 2 2006.173.06:41:08.36#ibcon#*after write, iclass 12, count 2 2006.173.06:41:08.36#ibcon#*before return 0, iclass 12, count 2 2006.173.06:41:08.36#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.06:41:08.36#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.06:41:08.36#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.06:41:08.36#ibcon#ireg 7 cls_cnt 0 2006.173.06:41:08.36#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.06:41:08.48#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.06:41:08.48#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.06:41:08.48#ibcon#enter wrdev, iclass 12, count 0 2006.173.06:41:08.48#ibcon#first serial, iclass 12, count 0 2006.173.06:41:08.48#ibcon#enter sib2, iclass 12, count 0 2006.173.06:41:08.48#ibcon#flushed, iclass 12, count 0 2006.173.06:41:08.48#ibcon#about to write, iclass 12, count 0 2006.173.06:41:08.48#ibcon#wrote, iclass 12, count 0 2006.173.06:41:08.48#ibcon#about to read 3, iclass 12, count 0 2006.173.06:41:08.50#ibcon#read 3, iclass 12, count 0 2006.173.06:41:08.50#ibcon#about to read 4, iclass 12, count 0 2006.173.06:41:08.50#ibcon#read 4, iclass 12, count 0 2006.173.06:41:08.50#ibcon#about to read 5, iclass 12, count 0 2006.173.06:41:08.50#ibcon#read 5, iclass 12, count 0 2006.173.06:41:08.50#ibcon#about to read 6, iclass 12, count 0 2006.173.06:41:08.50#ibcon#read 6, iclass 12, count 0 2006.173.06:41:08.50#ibcon#end of sib2, iclass 12, count 0 2006.173.06:41:08.50#ibcon#*mode == 0, iclass 12, count 0 2006.173.06:41:08.50#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.06:41:08.50#ibcon#[25=USB\r\n] 2006.173.06:41:08.50#ibcon#*before write, iclass 12, count 0 2006.173.06:41:08.50#ibcon#enter sib2, iclass 12, count 0 2006.173.06:41:08.50#ibcon#flushed, iclass 12, count 0 2006.173.06:41:08.50#ibcon#about to write, iclass 12, count 0 2006.173.06:41:08.50#ibcon#wrote, iclass 12, count 0 2006.173.06:41:08.50#ibcon#about to read 3, iclass 12, count 0 2006.173.06:41:08.53#ibcon#read 3, iclass 12, count 0 2006.173.06:41:08.53#ibcon#about to read 4, iclass 12, count 0 2006.173.06:41:08.53#ibcon#read 4, iclass 12, count 0 2006.173.06:41:08.53#ibcon#about to read 5, iclass 12, count 0 2006.173.06:41:08.53#ibcon#read 5, iclass 12, count 0 2006.173.06:41:08.53#ibcon#about to read 6, iclass 12, count 0 2006.173.06:41:08.53#ibcon#read 6, iclass 12, count 0 2006.173.06:41:08.53#ibcon#end of sib2, iclass 12, count 0 2006.173.06:41:08.53#ibcon#*after write, iclass 12, count 0 2006.173.06:41:08.53#ibcon#*before return 0, iclass 12, count 0 2006.173.06:41:08.53#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.06:41:08.53#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.06:41:08.53#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.06:41:08.53#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.06:41:08.53$vck44/valo=2,534.99 2006.173.06:41:08.53#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.06:41:08.53#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.06:41:08.53#ibcon#ireg 17 cls_cnt 0 2006.173.06:41:08.53#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.06:41:08.53#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.06:41:08.53#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.06:41:08.53#ibcon#enter wrdev, iclass 14, count 0 2006.173.06:41:08.53#ibcon#first serial, iclass 14, count 0 2006.173.06:41:08.53#ibcon#enter sib2, iclass 14, count 0 2006.173.06:41:08.53#ibcon#flushed, iclass 14, count 0 2006.173.06:41:08.53#ibcon#about to write, iclass 14, count 0 2006.173.06:41:08.53#ibcon#wrote, iclass 14, count 0 2006.173.06:41:08.53#ibcon#about to read 3, iclass 14, count 0 2006.173.06:41:08.55#ibcon#read 3, iclass 14, count 0 2006.173.06:41:08.55#ibcon#about to read 4, iclass 14, count 0 2006.173.06:41:08.55#ibcon#read 4, iclass 14, count 0 2006.173.06:41:08.55#ibcon#about to read 5, iclass 14, count 0 2006.173.06:41:08.55#ibcon#read 5, iclass 14, count 0 2006.173.06:41:08.55#ibcon#about to read 6, iclass 14, count 0 2006.173.06:41:08.55#ibcon#read 6, iclass 14, count 0 2006.173.06:41:08.55#ibcon#end of sib2, iclass 14, count 0 2006.173.06:41:08.55#ibcon#*mode == 0, iclass 14, count 0 2006.173.06:41:08.55#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.06:41:08.55#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.06:41:08.55#ibcon#*before write, iclass 14, count 0 2006.173.06:41:08.55#ibcon#enter sib2, iclass 14, count 0 2006.173.06:41:08.55#ibcon#flushed, iclass 14, count 0 2006.173.06:41:08.55#ibcon#about to write, iclass 14, count 0 2006.173.06:41:08.55#ibcon#wrote, iclass 14, count 0 2006.173.06:41:08.55#ibcon#about to read 3, iclass 14, count 0 2006.173.06:41:08.59#ibcon#read 3, iclass 14, count 0 2006.173.06:41:08.59#ibcon#about to read 4, iclass 14, count 0 2006.173.06:41:08.59#ibcon#read 4, iclass 14, count 0 2006.173.06:41:08.59#ibcon#about to read 5, iclass 14, count 0 2006.173.06:41:08.59#ibcon#read 5, iclass 14, count 0 2006.173.06:41:08.59#ibcon#about to read 6, iclass 14, count 0 2006.173.06:41:08.59#ibcon#read 6, iclass 14, count 0 2006.173.06:41:08.59#ibcon#end of sib2, iclass 14, count 0 2006.173.06:41:08.59#ibcon#*after write, iclass 14, count 0 2006.173.06:41:08.59#ibcon#*before return 0, iclass 14, count 0 2006.173.06:41:08.59#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.06:41:08.59#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.06:41:08.59#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.06:41:08.59#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.06:41:08.59$vck44/va=2,6 2006.173.06:41:08.59#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.06:41:08.59#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.06:41:08.59#ibcon#ireg 11 cls_cnt 2 2006.173.06:41:08.59#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.06:41:08.65#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.06:41:08.65#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.06:41:08.65#ibcon#enter wrdev, iclass 16, count 2 2006.173.06:41:08.65#ibcon#first serial, iclass 16, count 2 2006.173.06:41:08.65#ibcon#enter sib2, iclass 16, count 2 2006.173.06:41:08.65#ibcon#flushed, iclass 16, count 2 2006.173.06:41:08.65#ibcon#about to write, iclass 16, count 2 2006.173.06:41:08.65#ibcon#wrote, iclass 16, count 2 2006.173.06:41:08.65#ibcon#about to read 3, iclass 16, count 2 2006.173.06:41:08.67#ibcon#read 3, iclass 16, count 2 2006.173.06:41:08.67#ibcon#about to read 4, iclass 16, count 2 2006.173.06:41:08.67#ibcon#read 4, iclass 16, count 2 2006.173.06:41:08.67#ibcon#about to read 5, iclass 16, count 2 2006.173.06:41:08.67#ibcon#read 5, iclass 16, count 2 2006.173.06:41:08.67#ibcon#about to read 6, iclass 16, count 2 2006.173.06:41:08.67#ibcon#read 6, iclass 16, count 2 2006.173.06:41:08.67#ibcon#end of sib2, iclass 16, count 2 2006.173.06:41:08.67#ibcon#*mode == 0, iclass 16, count 2 2006.173.06:41:08.67#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.06:41:08.67#ibcon#[25=AT02-06\r\n] 2006.173.06:41:08.67#ibcon#*before write, iclass 16, count 2 2006.173.06:41:08.67#ibcon#enter sib2, iclass 16, count 2 2006.173.06:41:08.67#ibcon#flushed, iclass 16, count 2 2006.173.06:41:08.67#ibcon#about to write, iclass 16, count 2 2006.173.06:41:08.67#ibcon#wrote, iclass 16, count 2 2006.173.06:41:08.67#ibcon#about to read 3, iclass 16, count 2 2006.173.06:41:08.70#ibcon#read 3, iclass 16, count 2 2006.173.06:41:08.70#ibcon#about to read 4, iclass 16, count 2 2006.173.06:41:08.70#ibcon#read 4, iclass 16, count 2 2006.173.06:41:08.70#ibcon#about to read 5, iclass 16, count 2 2006.173.06:41:08.70#ibcon#read 5, iclass 16, count 2 2006.173.06:41:08.70#ibcon#about to read 6, iclass 16, count 2 2006.173.06:41:08.70#ibcon#read 6, iclass 16, count 2 2006.173.06:41:08.70#ibcon#end of sib2, iclass 16, count 2 2006.173.06:41:08.70#ibcon#*after write, iclass 16, count 2 2006.173.06:41:08.70#ibcon#*before return 0, iclass 16, count 2 2006.173.06:41:08.70#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.06:41:08.70#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.06:41:08.70#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.06:41:08.70#ibcon#ireg 7 cls_cnt 0 2006.173.06:41:08.70#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.06:41:08.82#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.06:41:08.82#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.06:41:08.82#ibcon#enter wrdev, iclass 16, count 0 2006.173.06:41:08.82#ibcon#first serial, iclass 16, count 0 2006.173.06:41:08.82#ibcon#enter sib2, iclass 16, count 0 2006.173.06:41:08.82#ibcon#flushed, iclass 16, count 0 2006.173.06:41:08.82#ibcon#about to write, iclass 16, count 0 2006.173.06:41:08.82#ibcon#wrote, iclass 16, count 0 2006.173.06:41:08.82#ibcon#about to read 3, iclass 16, count 0 2006.173.06:41:08.84#ibcon#read 3, iclass 16, count 0 2006.173.06:41:08.84#ibcon#about to read 4, iclass 16, count 0 2006.173.06:41:08.84#ibcon#read 4, iclass 16, count 0 2006.173.06:41:08.84#ibcon#about to read 5, iclass 16, count 0 2006.173.06:41:08.84#ibcon#read 5, iclass 16, count 0 2006.173.06:41:08.84#ibcon#about to read 6, iclass 16, count 0 2006.173.06:41:08.84#ibcon#read 6, iclass 16, count 0 2006.173.06:41:08.84#ibcon#end of sib2, iclass 16, count 0 2006.173.06:41:08.84#ibcon#*mode == 0, iclass 16, count 0 2006.173.06:41:08.84#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.06:41:08.84#ibcon#[25=USB\r\n] 2006.173.06:41:08.84#ibcon#*before write, iclass 16, count 0 2006.173.06:41:08.84#ibcon#enter sib2, iclass 16, count 0 2006.173.06:41:08.84#ibcon#flushed, iclass 16, count 0 2006.173.06:41:08.84#ibcon#about to write, iclass 16, count 0 2006.173.06:41:08.84#ibcon#wrote, iclass 16, count 0 2006.173.06:41:08.84#ibcon#about to read 3, iclass 16, count 0 2006.173.06:41:08.87#ibcon#read 3, iclass 16, count 0 2006.173.06:41:08.87#ibcon#about to read 4, iclass 16, count 0 2006.173.06:41:08.87#ibcon#read 4, iclass 16, count 0 2006.173.06:41:08.87#ibcon#about to read 5, iclass 16, count 0 2006.173.06:41:08.87#ibcon#read 5, iclass 16, count 0 2006.173.06:41:08.87#ibcon#about to read 6, iclass 16, count 0 2006.173.06:41:08.87#ibcon#read 6, iclass 16, count 0 2006.173.06:41:08.87#ibcon#end of sib2, iclass 16, count 0 2006.173.06:41:08.87#ibcon#*after write, iclass 16, count 0 2006.173.06:41:08.87#ibcon#*before return 0, iclass 16, count 0 2006.173.06:41:08.87#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.06:41:08.87#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.06:41:08.87#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.06:41:08.87#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.06:41:08.87$vck44/valo=3,564.99 2006.173.06:41:08.87#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.06:41:08.87#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.06:41:08.87#ibcon#ireg 17 cls_cnt 0 2006.173.06:41:08.87#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.06:41:08.87#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.06:41:08.87#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.06:41:08.87#ibcon#enter wrdev, iclass 18, count 0 2006.173.06:41:08.87#ibcon#first serial, iclass 18, count 0 2006.173.06:41:08.87#ibcon#enter sib2, iclass 18, count 0 2006.173.06:41:08.87#ibcon#flushed, iclass 18, count 0 2006.173.06:41:08.87#ibcon#about to write, iclass 18, count 0 2006.173.06:41:08.87#ibcon#wrote, iclass 18, count 0 2006.173.06:41:08.87#ibcon#about to read 3, iclass 18, count 0 2006.173.06:41:08.89#ibcon#read 3, iclass 18, count 0 2006.173.06:41:08.89#ibcon#about to read 4, iclass 18, count 0 2006.173.06:41:08.89#ibcon#read 4, iclass 18, count 0 2006.173.06:41:08.89#ibcon#about to read 5, iclass 18, count 0 2006.173.06:41:08.89#ibcon#read 5, iclass 18, count 0 2006.173.06:41:08.89#ibcon#about to read 6, iclass 18, count 0 2006.173.06:41:08.89#ibcon#read 6, iclass 18, count 0 2006.173.06:41:08.89#ibcon#end of sib2, iclass 18, count 0 2006.173.06:41:08.89#ibcon#*mode == 0, iclass 18, count 0 2006.173.06:41:08.89#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.06:41:08.89#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.06:41:08.89#ibcon#*before write, iclass 18, count 0 2006.173.06:41:08.89#ibcon#enter sib2, iclass 18, count 0 2006.173.06:41:08.89#ibcon#flushed, iclass 18, count 0 2006.173.06:41:08.89#ibcon#about to write, iclass 18, count 0 2006.173.06:41:08.89#ibcon#wrote, iclass 18, count 0 2006.173.06:41:08.89#ibcon#about to read 3, iclass 18, count 0 2006.173.06:41:08.93#ibcon#read 3, iclass 18, count 0 2006.173.06:41:08.93#ibcon#about to read 4, iclass 18, count 0 2006.173.06:41:08.93#ibcon#read 4, iclass 18, count 0 2006.173.06:41:08.93#ibcon#about to read 5, iclass 18, count 0 2006.173.06:41:08.93#ibcon#read 5, iclass 18, count 0 2006.173.06:41:08.93#ibcon#about to read 6, iclass 18, count 0 2006.173.06:41:08.93#ibcon#read 6, iclass 18, count 0 2006.173.06:41:08.93#ibcon#end of sib2, iclass 18, count 0 2006.173.06:41:08.93#ibcon#*after write, iclass 18, count 0 2006.173.06:41:08.93#ibcon#*before return 0, iclass 18, count 0 2006.173.06:41:08.93#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.06:41:08.93#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.06:41:08.93#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.06:41:08.93#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.06:41:08.93$vck44/va=3,5 2006.173.06:41:08.93#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.06:41:08.93#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.06:41:08.93#ibcon#ireg 11 cls_cnt 2 2006.173.06:41:08.93#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.06:41:08.99#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.06:41:08.99#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.06:41:08.99#ibcon#enter wrdev, iclass 20, count 2 2006.173.06:41:08.99#ibcon#first serial, iclass 20, count 2 2006.173.06:41:08.99#ibcon#enter sib2, iclass 20, count 2 2006.173.06:41:08.99#ibcon#flushed, iclass 20, count 2 2006.173.06:41:08.99#ibcon#about to write, iclass 20, count 2 2006.173.06:41:08.99#ibcon#wrote, iclass 20, count 2 2006.173.06:41:08.99#ibcon#about to read 3, iclass 20, count 2 2006.173.06:41:09.01#ibcon#read 3, iclass 20, count 2 2006.173.06:41:09.01#ibcon#about to read 4, iclass 20, count 2 2006.173.06:41:09.01#ibcon#read 4, iclass 20, count 2 2006.173.06:41:09.01#ibcon#about to read 5, iclass 20, count 2 2006.173.06:41:09.01#ibcon#read 5, iclass 20, count 2 2006.173.06:41:09.01#ibcon#about to read 6, iclass 20, count 2 2006.173.06:41:09.01#ibcon#read 6, iclass 20, count 2 2006.173.06:41:09.01#ibcon#end of sib2, iclass 20, count 2 2006.173.06:41:09.01#ibcon#*mode == 0, iclass 20, count 2 2006.173.06:41:09.01#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.06:41:09.01#ibcon#[25=AT03-05\r\n] 2006.173.06:41:09.01#ibcon#*before write, iclass 20, count 2 2006.173.06:41:09.01#ibcon#enter sib2, iclass 20, count 2 2006.173.06:41:09.01#ibcon#flushed, iclass 20, count 2 2006.173.06:41:09.01#ibcon#about to write, iclass 20, count 2 2006.173.06:41:09.01#ibcon#wrote, iclass 20, count 2 2006.173.06:41:09.01#ibcon#about to read 3, iclass 20, count 2 2006.173.06:41:09.04#ibcon#read 3, iclass 20, count 2 2006.173.06:41:09.04#ibcon#about to read 4, iclass 20, count 2 2006.173.06:41:09.04#ibcon#read 4, iclass 20, count 2 2006.173.06:41:09.04#ibcon#about to read 5, iclass 20, count 2 2006.173.06:41:09.04#ibcon#read 5, iclass 20, count 2 2006.173.06:41:09.04#ibcon#about to read 6, iclass 20, count 2 2006.173.06:41:09.04#ibcon#read 6, iclass 20, count 2 2006.173.06:41:09.04#ibcon#end of sib2, iclass 20, count 2 2006.173.06:41:09.04#ibcon#*after write, iclass 20, count 2 2006.173.06:41:09.04#ibcon#*before return 0, iclass 20, count 2 2006.173.06:41:09.04#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.06:41:09.04#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.06:41:09.04#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.06:41:09.04#ibcon#ireg 7 cls_cnt 0 2006.173.06:41:09.04#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.06:41:09.16#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.06:41:09.16#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.06:41:09.16#ibcon#enter wrdev, iclass 20, count 0 2006.173.06:41:09.16#ibcon#first serial, iclass 20, count 0 2006.173.06:41:09.16#ibcon#enter sib2, iclass 20, count 0 2006.173.06:41:09.16#ibcon#flushed, iclass 20, count 0 2006.173.06:41:09.16#ibcon#about to write, iclass 20, count 0 2006.173.06:41:09.16#ibcon#wrote, iclass 20, count 0 2006.173.06:41:09.16#ibcon#about to read 3, iclass 20, count 0 2006.173.06:41:09.18#ibcon#read 3, iclass 20, count 0 2006.173.06:41:09.18#ibcon#about to read 4, iclass 20, count 0 2006.173.06:41:09.18#ibcon#read 4, iclass 20, count 0 2006.173.06:41:09.18#ibcon#about to read 5, iclass 20, count 0 2006.173.06:41:09.18#ibcon#read 5, iclass 20, count 0 2006.173.06:41:09.18#ibcon#about to read 6, iclass 20, count 0 2006.173.06:41:09.18#ibcon#read 6, iclass 20, count 0 2006.173.06:41:09.18#ibcon#end of sib2, iclass 20, count 0 2006.173.06:41:09.18#ibcon#*mode == 0, iclass 20, count 0 2006.173.06:41:09.18#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.06:41:09.18#ibcon#[25=USB\r\n] 2006.173.06:41:09.18#ibcon#*before write, iclass 20, count 0 2006.173.06:41:09.18#ibcon#enter sib2, iclass 20, count 0 2006.173.06:41:09.18#ibcon#flushed, iclass 20, count 0 2006.173.06:41:09.18#ibcon#about to write, iclass 20, count 0 2006.173.06:41:09.18#ibcon#wrote, iclass 20, count 0 2006.173.06:41:09.18#ibcon#about to read 3, iclass 20, count 0 2006.173.06:41:09.18#abcon#<5=/15 0.5 1.0 23.73 801005.0\r\n> 2006.173.06:41:09.20#abcon#{5=INTERFACE CLEAR} 2006.173.06:41:09.21#ibcon#read 3, iclass 20, count 0 2006.173.06:41:09.21#ibcon#about to read 4, iclass 20, count 0 2006.173.06:41:09.21#ibcon#read 4, iclass 20, count 0 2006.173.06:41:09.21#ibcon#about to read 5, iclass 20, count 0 2006.173.06:41:09.21#ibcon#read 5, iclass 20, count 0 2006.173.06:41:09.21#ibcon#about to read 6, iclass 20, count 0 2006.173.06:41:09.21#ibcon#read 6, iclass 20, count 0 2006.173.06:41:09.21#ibcon#end of sib2, iclass 20, count 0 2006.173.06:41:09.21#ibcon#*after write, iclass 20, count 0 2006.173.06:41:09.21#ibcon#*before return 0, iclass 20, count 0 2006.173.06:41:09.21#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.06:41:09.21#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.06:41:09.21#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.06:41:09.21#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.06:41:09.21$vck44/valo=4,624.99 2006.173.06:41:09.21#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.06:41:09.21#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.06:41:09.21#ibcon#ireg 17 cls_cnt 0 2006.173.06:41:09.21#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.06:41:09.21#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.06:41:09.21#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.06:41:09.21#ibcon#enter wrdev, iclass 25, count 0 2006.173.06:41:09.21#ibcon#first serial, iclass 25, count 0 2006.173.06:41:09.21#ibcon#enter sib2, iclass 25, count 0 2006.173.06:41:09.21#ibcon#flushed, iclass 25, count 0 2006.173.06:41:09.21#ibcon#about to write, iclass 25, count 0 2006.173.06:41:09.21#ibcon#wrote, iclass 25, count 0 2006.173.06:41:09.21#ibcon#about to read 3, iclass 25, count 0 2006.173.06:41:09.23#ibcon#read 3, iclass 25, count 0 2006.173.06:41:09.23#ibcon#about to read 4, iclass 25, count 0 2006.173.06:41:09.23#ibcon#read 4, iclass 25, count 0 2006.173.06:41:09.23#ibcon#about to read 5, iclass 25, count 0 2006.173.06:41:09.23#ibcon#read 5, iclass 25, count 0 2006.173.06:41:09.23#ibcon#about to read 6, iclass 25, count 0 2006.173.06:41:09.23#ibcon#read 6, iclass 25, count 0 2006.173.06:41:09.23#ibcon#end of sib2, iclass 25, count 0 2006.173.06:41:09.23#ibcon#*mode == 0, iclass 25, count 0 2006.173.06:41:09.23#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.06:41:09.23#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.06:41:09.23#ibcon#*before write, iclass 25, count 0 2006.173.06:41:09.23#ibcon#enter sib2, iclass 25, count 0 2006.173.06:41:09.23#ibcon#flushed, iclass 25, count 0 2006.173.06:41:09.23#ibcon#about to write, iclass 25, count 0 2006.173.06:41:09.23#ibcon#wrote, iclass 25, count 0 2006.173.06:41:09.23#ibcon#about to read 3, iclass 25, count 0 2006.173.06:41:09.26#abcon#[5=S1D000X0/0*\r\n] 2006.173.06:41:09.27#ibcon#read 3, iclass 25, count 0 2006.173.06:41:09.27#ibcon#about to read 4, iclass 25, count 0 2006.173.06:41:09.27#ibcon#read 4, iclass 25, count 0 2006.173.06:41:09.27#ibcon#about to read 5, iclass 25, count 0 2006.173.06:41:09.27#ibcon#read 5, iclass 25, count 0 2006.173.06:41:09.27#ibcon#about to read 6, iclass 25, count 0 2006.173.06:41:09.27#ibcon#read 6, iclass 25, count 0 2006.173.06:41:09.27#ibcon#end of sib2, iclass 25, count 0 2006.173.06:41:09.27#ibcon#*after write, iclass 25, count 0 2006.173.06:41:09.27#ibcon#*before return 0, iclass 25, count 0 2006.173.06:41:09.27#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.06:41:09.27#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.06:41:09.27#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.06:41:09.27#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.06:41:09.27$vck44/va=4,6 2006.173.06:41:09.27#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.06:41:09.27#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.06:41:09.27#ibcon#ireg 11 cls_cnt 2 2006.173.06:41:09.27#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.06:41:09.33#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.06:41:09.33#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.06:41:09.33#ibcon#enter wrdev, iclass 28, count 2 2006.173.06:41:09.33#ibcon#first serial, iclass 28, count 2 2006.173.06:41:09.33#ibcon#enter sib2, iclass 28, count 2 2006.173.06:41:09.33#ibcon#flushed, iclass 28, count 2 2006.173.06:41:09.33#ibcon#about to write, iclass 28, count 2 2006.173.06:41:09.33#ibcon#wrote, iclass 28, count 2 2006.173.06:41:09.33#ibcon#about to read 3, iclass 28, count 2 2006.173.06:41:09.35#ibcon#read 3, iclass 28, count 2 2006.173.06:41:09.35#ibcon#about to read 4, iclass 28, count 2 2006.173.06:41:09.35#ibcon#read 4, iclass 28, count 2 2006.173.06:41:09.35#ibcon#about to read 5, iclass 28, count 2 2006.173.06:41:09.35#ibcon#read 5, iclass 28, count 2 2006.173.06:41:09.35#ibcon#about to read 6, iclass 28, count 2 2006.173.06:41:09.35#ibcon#read 6, iclass 28, count 2 2006.173.06:41:09.35#ibcon#end of sib2, iclass 28, count 2 2006.173.06:41:09.35#ibcon#*mode == 0, iclass 28, count 2 2006.173.06:41:09.35#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.06:41:09.35#ibcon#[25=AT04-06\r\n] 2006.173.06:41:09.35#ibcon#*before write, iclass 28, count 2 2006.173.06:41:09.35#ibcon#enter sib2, iclass 28, count 2 2006.173.06:41:09.35#ibcon#flushed, iclass 28, count 2 2006.173.06:41:09.35#ibcon#about to write, iclass 28, count 2 2006.173.06:41:09.35#ibcon#wrote, iclass 28, count 2 2006.173.06:41:09.35#ibcon#about to read 3, iclass 28, count 2 2006.173.06:41:09.38#ibcon#read 3, iclass 28, count 2 2006.173.06:41:09.38#ibcon#about to read 4, iclass 28, count 2 2006.173.06:41:09.38#ibcon#read 4, iclass 28, count 2 2006.173.06:41:09.38#ibcon#about to read 5, iclass 28, count 2 2006.173.06:41:09.38#ibcon#read 5, iclass 28, count 2 2006.173.06:41:09.38#ibcon#about to read 6, iclass 28, count 2 2006.173.06:41:09.38#ibcon#read 6, iclass 28, count 2 2006.173.06:41:09.38#ibcon#end of sib2, iclass 28, count 2 2006.173.06:41:09.38#ibcon#*after write, iclass 28, count 2 2006.173.06:41:09.38#ibcon#*before return 0, iclass 28, count 2 2006.173.06:41:09.38#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.06:41:09.38#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.06:41:09.38#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.06:41:09.38#ibcon#ireg 7 cls_cnt 0 2006.173.06:41:09.38#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.06:41:09.50#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.06:41:09.50#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.06:41:09.50#ibcon#enter wrdev, iclass 28, count 0 2006.173.06:41:09.50#ibcon#first serial, iclass 28, count 0 2006.173.06:41:09.50#ibcon#enter sib2, iclass 28, count 0 2006.173.06:41:09.50#ibcon#flushed, iclass 28, count 0 2006.173.06:41:09.50#ibcon#about to write, iclass 28, count 0 2006.173.06:41:09.50#ibcon#wrote, iclass 28, count 0 2006.173.06:41:09.50#ibcon#about to read 3, iclass 28, count 0 2006.173.06:41:09.52#ibcon#read 3, iclass 28, count 0 2006.173.06:41:09.52#ibcon#about to read 4, iclass 28, count 0 2006.173.06:41:09.52#ibcon#read 4, iclass 28, count 0 2006.173.06:41:09.52#ibcon#about to read 5, iclass 28, count 0 2006.173.06:41:09.52#ibcon#read 5, iclass 28, count 0 2006.173.06:41:09.52#ibcon#about to read 6, iclass 28, count 0 2006.173.06:41:09.52#ibcon#read 6, iclass 28, count 0 2006.173.06:41:09.52#ibcon#end of sib2, iclass 28, count 0 2006.173.06:41:09.52#ibcon#*mode == 0, iclass 28, count 0 2006.173.06:41:09.52#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.06:41:09.52#ibcon#[25=USB\r\n] 2006.173.06:41:09.52#ibcon#*before write, iclass 28, count 0 2006.173.06:41:09.52#ibcon#enter sib2, iclass 28, count 0 2006.173.06:41:09.52#ibcon#flushed, iclass 28, count 0 2006.173.06:41:09.52#ibcon#about to write, iclass 28, count 0 2006.173.06:41:09.52#ibcon#wrote, iclass 28, count 0 2006.173.06:41:09.52#ibcon#about to read 3, iclass 28, count 0 2006.173.06:41:09.55#ibcon#read 3, iclass 28, count 0 2006.173.06:41:09.55#ibcon#about to read 4, iclass 28, count 0 2006.173.06:41:09.55#ibcon#read 4, iclass 28, count 0 2006.173.06:41:09.55#ibcon#about to read 5, iclass 28, count 0 2006.173.06:41:09.55#ibcon#read 5, iclass 28, count 0 2006.173.06:41:09.55#ibcon#about to read 6, iclass 28, count 0 2006.173.06:41:09.55#ibcon#read 6, iclass 28, count 0 2006.173.06:41:09.55#ibcon#end of sib2, iclass 28, count 0 2006.173.06:41:09.55#ibcon#*after write, iclass 28, count 0 2006.173.06:41:09.55#ibcon#*before return 0, iclass 28, count 0 2006.173.06:41:09.55#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.06:41:09.55#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.06:41:09.55#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.06:41:09.55#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.06:41:09.55$vck44/valo=5,734.99 2006.173.06:41:09.55#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.06:41:09.55#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.06:41:09.55#ibcon#ireg 17 cls_cnt 0 2006.173.06:41:09.55#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.06:41:09.55#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.06:41:09.55#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.06:41:09.55#ibcon#enter wrdev, iclass 30, count 0 2006.173.06:41:09.55#ibcon#first serial, iclass 30, count 0 2006.173.06:41:09.55#ibcon#enter sib2, iclass 30, count 0 2006.173.06:41:09.55#ibcon#flushed, iclass 30, count 0 2006.173.06:41:09.55#ibcon#about to write, iclass 30, count 0 2006.173.06:41:09.55#ibcon#wrote, iclass 30, count 0 2006.173.06:41:09.55#ibcon#about to read 3, iclass 30, count 0 2006.173.06:41:09.57#ibcon#read 3, iclass 30, count 0 2006.173.06:41:09.57#ibcon#about to read 4, iclass 30, count 0 2006.173.06:41:09.57#ibcon#read 4, iclass 30, count 0 2006.173.06:41:09.57#ibcon#about to read 5, iclass 30, count 0 2006.173.06:41:09.57#ibcon#read 5, iclass 30, count 0 2006.173.06:41:09.57#ibcon#about to read 6, iclass 30, count 0 2006.173.06:41:09.57#ibcon#read 6, iclass 30, count 0 2006.173.06:41:09.57#ibcon#end of sib2, iclass 30, count 0 2006.173.06:41:09.57#ibcon#*mode == 0, iclass 30, count 0 2006.173.06:41:09.57#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.06:41:09.57#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.06:41:09.57#ibcon#*before write, iclass 30, count 0 2006.173.06:41:09.57#ibcon#enter sib2, iclass 30, count 0 2006.173.06:41:09.57#ibcon#flushed, iclass 30, count 0 2006.173.06:41:09.57#ibcon#about to write, iclass 30, count 0 2006.173.06:41:09.57#ibcon#wrote, iclass 30, count 0 2006.173.06:41:09.57#ibcon#about to read 3, iclass 30, count 0 2006.173.06:41:09.61#ibcon#read 3, iclass 30, count 0 2006.173.06:41:09.61#ibcon#about to read 4, iclass 30, count 0 2006.173.06:41:09.61#ibcon#read 4, iclass 30, count 0 2006.173.06:41:09.61#ibcon#about to read 5, iclass 30, count 0 2006.173.06:41:09.61#ibcon#read 5, iclass 30, count 0 2006.173.06:41:09.61#ibcon#about to read 6, iclass 30, count 0 2006.173.06:41:09.61#ibcon#read 6, iclass 30, count 0 2006.173.06:41:09.61#ibcon#end of sib2, iclass 30, count 0 2006.173.06:41:09.61#ibcon#*after write, iclass 30, count 0 2006.173.06:41:09.61#ibcon#*before return 0, iclass 30, count 0 2006.173.06:41:09.61#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.06:41:09.61#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.06:41:09.61#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.06:41:09.61#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.06:41:09.61$vck44/va=5,4 2006.173.06:41:09.61#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.173.06:41:09.61#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.173.06:41:09.61#ibcon#ireg 11 cls_cnt 2 2006.173.06:41:09.61#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.06:41:09.67#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.06:41:09.67#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.06:41:09.67#ibcon#enter wrdev, iclass 32, count 2 2006.173.06:41:09.67#ibcon#first serial, iclass 32, count 2 2006.173.06:41:09.67#ibcon#enter sib2, iclass 32, count 2 2006.173.06:41:09.67#ibcon#flushed, iclass 32, count 2 2006.173.06:41:09.67#ibcon#about to write, iclass 32, count 2 2006.173.06:41:09.67#ibcon#wrote, iclass 32, count 2 2006.173.06:41:09.67#ibcon#about to read 3, iclass 32, count 2 2006.173.06:41:09.69#ibcon#read 3, iclass 32, count 2 2006.173.06:41:09.69#ibcon#about to read 4, iclass 32, count 2 2006.173.06:41:09.69#ibcon#read 4, iclass 32, count 2 2006.173.06:41:09.69#ibcon#about to read 5, iclass 32, count 2 2006.173.06:41:09.69#ibcon#read 5, iclass 32, count 2 2006.173.06:41:09.69#ibcon#about to read 6, iclass 32, count 2 2006.173.06:41:09.69#ibcon#read 6, iclass 32, count 2 2006.173.06:41:09.69#ibcon#end of sib2, iclass 32, count 2 2006.173.06:41:09.69#ibcon#*mode == 0, iclass 32, count 2 2006.173.06:41:09.69#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.173.06:41:09.69#ibcon#[25=AT05-04\r\n] 2006.173.06:41:09.69#ibcon#*before write, iclass 32, count 2 2006.173.06:41:09.69#ibcon#enter sib2, iclass 32, count 2 2006.173.06:41:09.69#ibcon#flushed, iclass 32, count 2 2006.173.06:41:09.69#ibcon#about to write, iclass 32, count 2 2006.173.06:41:09.69#ibcon#wrote, iclass 32, count 2 2006.173.06:41:09.69#ibcon#about to read 3, iclass 32, count 2 2006.173.06:41:09.72#ibcon#read 3, iclass 32, count 2 2006.173.06:41:09.72#ibcon#about to read 4, iclass 32, count 2 2006.173.06:41:09.72#ibcon#read 4, iclass 32, count 2 2006.173.06:41:09.72#ibcon#about to read 5, iclass 32, count 2 2006.173.06:41:09.72#ibcon#read 5, iclass 32, count 2 2006.173.06:41:09.72#ibcon#about to read 6, iclass 32, count 2 2006.173.06:41:09.72#ibcon#read 6, iclass 32, count 2 2006.173.06:41:09.72#ibcon#end of sib2, iclass 32, count 2 2006.173.06:41:09.72#ibcon#*after write, iclass 32, count 2 2006.173.06:41:09.72#ibcon#*before return 0, iclass 32, count 2 2006.173.06:41:09.72#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.06:41:09.72#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.173.06:41:09.72#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.173.06:41:09.72#ibcon#ireg 7 cls_cnt 0 2006.173.06:41:09.72#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.06:41:09.84#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.06:41:09.84#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.06:41:09.84#ibcon#enter wrdev, iclass 32, count 0 2006.173.06:41:09.84#ibcon#first serial, iclass 32, count 0 2006.173.06:41:09.84#ibcon#enter sib2, iclass 32, count 0 2006.173.06:41:09.84#ibcon#flushed, iclass 32, count 0 2006.173.06:41:09.84#ibcon#about to write, iclass 32, count 0 2006.173.06:41:09.84#ibcon#wrote, iclass 32, count 0 2006.173.06:41:09.84#ibcon#about to read 3, iclass 32, count 0 2006.173.06:41:09.86#ibcon#read 3, iclass 32, count 0 2006.173.06:41:09.86#ibcon#about to read 4, iclass 32, count 0 2006.173.06:41:09.86#ibcon#read 4, iclass 32, count 0 2006.173.06:41:09.86#ibcon#about to read 5, iclass 32, count 0 2006.173.06:41:09.86#ibcon#read 5, iclass 32, count 0 2006.173.06:41:09.86#ibcon#about to read 6, iclass 32, count 0 2006.173.06:41:09.86#ibcon#read 6, iclass 32, count 0 2006.173.06:41:09.86#ibcon#end of sib2, iclass 32, count 0 2006.173.06:41:09.86#ibcon#*mode == 0, iclass 32, count 0 2006.173.06:41:09.86#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.06:41:09.86#ibcon#[25=USB\r\n] 2006.173.06:41:09.86#ibcon#*before write, iclass 32, count 0 2006.173.06:41:09.86#ibcon#enter sib2, iclass 32, count 0 2006.173.06:41:09.86#ibcon#flushed, iclass 32, count 0 2006.173.06:41:09.86#ibcon#about to write, iclass 32, count 0 2006.173.06:41:09.86#ibcon#wrote, iclass 32, count 0 2006.173.06:41:09.86#ibcon#about to read 3, iclass 32, count 0 2006.173.06:41:09.89#ibcon#read 3, iclass 32, count 0 2006.173.06:41:09.89#ibcon#about to read 4, iclass 32, count 0 2006.173.06:41:09.89#ibcon#read 4, iclass 32, count 0 2006.173.06:41:09.89#ibcon#about to read 5, iclass 32, count 0 2006.173.06:41:09.89#ibcon#read 5, iclass 32, count 0 2006.173.06:41:09.89#ibcon#about to read 6, iclass 32, count 0 2006.173.06:41:09.89#ibcon#read 6, iclass 32, count 0 2006.173.06:41:09.89#ibcon#end of sib2, iclass 32, count 0 2006.173.06:41:09.89#ibcon#*after write, iclass 32, count 0 2006.173.06:41:09.89#ibcon#*before return 0, iclass 32, count 0 2006.173.06:41:09.89#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.06:41:09.89#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.173.06:41:09.89#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.06:41:09.89#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.06:41:09.89$vck44/valo=6,814.99 2006.173.06:41:09.89#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.06:41:09.89#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.06:41:09.89#ibcon#ireg 17 cls_cnt 0 2006.173.06:41:09.89#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.06:41:09.89#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.06:41:09.89#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.06:41:09.89#ibcon#enter wrdev, iclass 34, count 0 2006.173.06:41:09.89#ibcon#first serial, iclass 34, count 0 2006.173.06:41:09.89#ibcon#enter sib2, iclass 34, count 0 2006.173.06:41:09.89#ibcon#flushed, iclass 34, count 0 2006.173.06:41:09.89#ibcon#about to write, iclass 34, count 0 2006.173.06:41:09.89#ibcon#wrote, iclass 34, count 0 2006.173.06:41:09.89#ibcon#about to read 3, iclass 34, count 0 2006.173.06:41:09.91#ibcon#read 3, iclass 34, count 0 2006.173.06:41:09.91#ibcon#about to read 4, iclass 34, count 0 2006.173.06:41:09.91#ibcon#read 4, iclass 34, count 0 2006.173.06:41:09.91#ibcon#about to read 5, iclass 34, count 0 2006.173.06:41:09.91#ibcon#read 5, iclass 34, count 0 2006.173.06:41:09.91#ibcon#about to read 6, iclass 34, count 0 2006.173.06:41:09.91#ibcon#read 6, iclass 34, count 0 2006.173.06:41:09.91#ibcon#end of sib2, iclass 34, count 0 2006.173.06:41:09.91#ibcon#*mode == 0, iclass 34, count 0 2006.173.06:41:09.91#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.06:41:09.91#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.06:41:09.91#ibcon#*before write, iclass 34, count 0 2006.173.06:41:09.91#ibcon#enter sib2, iclass 34, count 0 2006.173.06:41:09.91#ibcon#flushed, iclass 34, count 0 2006.173.06:41:09.91#ibcon#about to write, iclass 34, count 0 2006.173.06:41:09.91#ibcon#wrote, iclass 34, count 0 2006.173.06:41:09.91#ibcon#about to read 3, iclass 34, count 0 2006.173.06:41:09.95#ibcon#read 3, iclass 34, count 0 2006.173.06:41:09.95#ibcon#about to read 4, iclass 34, count 0 2006.173.06:41:09.95#ibcon#read 4, iclass 34, count 0 2006.173.06:41:09.95#ibcon#about to read 5, iclass 34, count 0 2006.173.06:41:09.95#ibcon#read 5, iclass 34, count 0 2006.173.06:41:09.95#ibcon#about to read 6, iclass 34, count 0 2006.173.06:41:09.95#ibcon#read 6, iclass 34, count 0 2006.173.06:41:09.95#ibcon#end of sib2, iclass 34, count 0 2006.173.06:41:09.95#ibcon#*after write, iclass 34, count 0 2006.173.06:41:09.95#ibcon#*before return 0, iclass 34, count 0 2006.173.06:41:09.95#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.06:41:09.95#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.06:41:09.95#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.06:41:09.95#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.06:41:09.95$vck44/va=6,3 2006.173.06:41:09.95#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.06:41:09.95#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.06:41:09.95#ibcon#ireg 11 cls_cnt 2 2006.173.06:41:09.95#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.06:41:10.01#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.06:41:10.01#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.06:41:10.01#ibcon#enter wrdev, iclass 36, count 2 2006.173.06:41:10.01#ibcon#first serial, iclass 36, count 2 2006.173.06:41:10.01#ibcon#enter sib2, iclass 36, count 2 2006.173.06:41:10.01#ibcon#flushed, iclass 36, count 2 2006.173.06:41:10.01#ibcon#about to write, iclass 36, count 2 2006.173.06:41:10.01#ibcon#wrote, iclass 36, count 2 2006.173.06:41:10.01#ibcon#about to read 3, iclass 36, count 2 2006.173.06:41:10.03#ibcon#read 3, iclass 36, count 2 2006.173.06:41:10.03#ibcon#about to read 4, iclass 36, count 2 2006.173.06:41:10.03#ibcon#read 4, iclass 36, count 2 2006.173.06:41:10.03#ibcon#about to read 5, iclass 36, count 2 2006.173.06:41:10.03#ibcon#read 5, iclass 36, count 2 2006.173.06:41:10.03#ibcon#about to read 6, iclass 36, count 2 2006.173.06:41:10.03#ibcon#read 6, iclass 36, count 2 2006.173.06:41:10.03#ibcon#end of sib2, iclass 36, count 2 2006.173.06:41:10.03#ibcon#*mode == 0, iclass 36, count 2 2006.173.06:41:10.03#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.06:41:10.03#ibcon#[25=AT06-03\r\n] 2006.173.06:41:10.03#ibcon#*before write, iclass 36, count 2 2006.173.06:41:10.03#ibcon#enter sib2, iclass 36, count 2 2006.173.06:41:10.03#ibcon#flushed, iclass 36, count 2 2006.173.06:41:10.03#ibcon#about to write, iclass 36, count 2 2006.173.06:41:10.03#ibcon#wrote, iclass 36, count 2 2006.173.06:41:10.03#ibcon#about to read 3, iclass 36, count 2 2006.173.06:41:10.06#ibcon#read 3, iclass 36, count 2 2006.173.06:41:10.06#ibcon#about to read 4, iclass 36, count 2 2006.173.06:41:10.06#ibcon#read 4, iclass 36, count 2 2006.173.06:41:10.06#ibcon#about to read 5, iclass 36, count 2 2006.173.06:41:10.06#ibcon#read 5, iclass 36, count 2 2006.173.06:41:10.06#ibcon#about to read 6, iclass 36, count 2 2006.173.06:41:10.06#ibcon#read 6, iclass 36, count 2 2006.173.06:41:10.06#ibcon#end of sib2, iclass 36, count 2 2006.173.06:41:10.06#ibcon#*after write, iclass 36, count 2 2006.173.06:41:10.06#ibcon#*before return 0, iclass 36, count 2 2006.173.06:41:10.06#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.06:41:10.06#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.06:41:10.06#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.06:41:10.06#ibcon#ireg 7 cls_cnt 0 2006.173.06:41:10.06#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.06:41:10.18#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.06:41:10.18#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.06:41:10.18#ibcon#enter wrdev, iclass 36, count 0 2006.173.06:41:10.18#ibcon#first serial, iclass 36, count 0 2006.173.06:41:10.18#ibcon#enter sib2, iclass 36, count 0 2006.173.06:41:10.18#ibcon#flushed, iclass 36, count 0 2006.173.06:41:10.18#ibcon#about to write, iclass 36, count 0 2006.173.06:41:10.18#ibcon#wrote, iclass 36, count 0 2006.173.06:41:10.18#ibcon#about to read 3, iclass 36, count 0 2006.173.06:41:10.20#ibcon#read 3, iclass 36, count 0 2006.173.06:41:10.20#ibcon#about to read 4, iclass 36, count 0 2006.173.06:41:10.20#ibcon#read 4, iclass 36, count 0 2006.173.06:41:10.20#ibcon#about to read 5, iclass 36, count 0 2006.173.06:41:10.20#ibcon#read 5, iclass 36, count 0 2006.173.06:41:10.20#ibcon#about to read 6, iclass 36, count 0 2006.173.06:41:10.20#ibcon#read 6, iclass 36, count 0 2006.173.06:41:10.20#ibcon#end of sib2, iclass 36, count 0 2006.173.06:41:10.20#ibcon#*mode == 0, iclass 36, count 0 2006.173.06:41:10.20#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.06:41:10.20#ibcon#[25=USB\r\n] 2006.173.06:41:10.20#ibcon#*before write, iclass 36, count 0 2006.173.06:41:10.20#ibcon#enter sib2, iclass 36, count 0 2006.173.06:41:10.20#ibcon#flushed, iclass 36, count 0 2006.173.06:41:10.20#ibcon#about to write, iclass 36, count 0 2006.173.06:41:10.20#ibcon#wrote, iclass 36, count 0 2006.173.06:41:10.20#ibcon#about to read 3, iclass 36, count 0 2006.173.06:41:10.23#ibcon#read 3, iclass 36, count 0 2006.173.06:41:10.23#ibcon#about to read 4, iclass 36, count 0 2006.173.06:41:10.23#ibcon#read 4, iclass 36, count 0 2006.173.06:41:10.23#ibcon#about to read 5, iclass 36, count 0 2006.173.06:41:10.23#ibcon#read 5, iclass 36, count 0 2006.173.06:41:10.23#ibcon#about to read 6, iclass 36, count 0 2006.173.06:41:10.23#ibcon#read 6, iclass 36, count 0 2006.173.06:41:10.23#ibcon#end of sib2, iclass 36, count 0 2006.173.06:41:10.23#ibcon#*after write, iclass 36, count 0 2006.173.06:41:10.23#ibcon#*before return 0, iclass 36, count 0 2006.173.06:41:10.23#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.06:41:10.23#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.06:41:10.23#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.06:41:10.23#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.06:41:10.23$vck44/valo=7,864.99 2006.173.06:41:10.23#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.06:41:10.23#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.06:41:10.23#ibcon#ireg 17 cls_cnt 0 2006.173.06:41:10.23#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.06:41:10.23#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.06:41:10.23#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.06:41:10.23#ibcon#enter wrdev, iclass 38, count 0 2006.173.06:41:10.23#ibcon#first serial, iclass 38, count 0 2006.173.06:41:10.23#ibcon#enter sib2, iclass 38, count 0 2006.173.06:41:10.23#ibcon#flushed, iclass 38, count 0 2006.173.06:41:10.23#ibcon#about to write, iclass 38, count 0 2006.173.06:41:10.23#ibcon#wrote, iclass 38, count 0 2006.173.06:41:10.23#ibcon#about to read 3, iclass 38, count 0 2006.173.06:41:10.25#ibcon#read 3, iclass 38, count 0 2006.173.06:41:10.25#ibcon#about to read 4, iclass 38, count 0 2006.173.06:41:10.25#ibcon#read 4, iclass 38, count 0 2006.173.06:41:10.25#ibcon#about to read 5, iclass 38, count 0 2006.173.06:41:10.25#ibcon#read 5, iclass 38, count 0 2006.173.06:41:10.25#ibcon#about to read 6, iclass 38, count 0 2006.173.06:41:10.25#ibcon#read 6, iclass 38, count 0 2006.173.06:41:10.25#ibcon#end of sib2, iclass 38, count 0 2006.173.06:41:10.25#ibcon#*mode == 0, iclass 38, count 0 2006.173.06:41:10.25#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.06:41:10.25#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.06:41:10.25#ibcon#*before write, iclass 38, count 0 2006.173.06:41:10.25#ibcon#enter sib2, iclass 38, count 0 2006.173.06:41:10.25#ibcon#flushed, iclass 38, count 0 2006.173.06:41:10.25#ibcon#about to write, iclass 38, count 0 2006.173.06:41:10.25#ibcon#wrote, iclass 38, count 0 2006.173.06:41:10.25#ibcon#about to read 3, iclass 38, count 0 2006.173.06:41:10.29#ibcon#read 3, iclass 38, count 0 2006.173.06:41:10.29#ibcon#about to read 4, iclass 38, count 0 2006.173.06:41:10.29#ibcon#read 4, iclass 38, count 0 2006.173.06:41:10.29#ibcon#about to read 5, iclass 38, count 0 2006.173.06:41:10.29#ibcon#read 5, iclass 38, count 0 2006.173.06:41:10.29#ibcon#about to read 6, iclass 38, count 0 2006.173.06:41:10.29#ibcon#read 6, iclass 38, count 0 2006.173.06:41:10.29#ibcon#end of sib2, iclass 38, count 0 2006.173.06:41:10.29#ibcon#*after write, iclass 38, count 0 2006.173.06:41:10.29#ibcon#*before return 0, iclass 38, count 0 2006.173.06:41:10.29#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.06:41:10.29#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.06:41:10.29#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.06:41:10.29#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.06:41:10.29$vck44/va=7,4 2006.173.06:41:10.29#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.06:41:10.29#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.06:41:10.29#ibcon#ireg 11 cls_cnt 2 2006.173.06:41:10.29#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.06:41:10.35#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.06:41:10.35#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.06:41:10.35#ibcon#enter wrdev, iclass 40, count 2 2006.173.06:41:10.35#ibcon#first serial, iclass 40, count 2 2006.173.06:41:10.35#ibcon#enter sib2, iclass 40, count 2 2006.173.06:41:10.35#ibcon#flushed, iclass 40, count 2 2006.173.06:41:10.35#ibcon#about to write, iclass 40, count 2 2006.173.06:41:10.35#ibcon#wrote, iclass 40, count 2 2006.173.06:41:10.35#ibcon#about to read 3, iclass 40, count 2 2006.173.06:41:10.37#ibcon#read 3, iclass 40, count 2 2006.173.06:41:10.37#ibcon#about to read 4, iclass 40, count 2 2006.173.06:41:10.37#ibcon#read 4, iclass 40, count 2 2006.173.06:41:10.37#ibcon#about to read 5, iclass 40, count 2 2006.173.06:41:10.37#ibcon#read 5, iclass 40, count 2 2006.173.06:41:10.37#ibcon#about to read 6, iclass 40, count 2 2006.173.06:41:10.37#ibcon#read 6, iclass 40, count 2 2006.173.06:41:10.37#ibcon#end of sib2, iclass 40, count 2 2006.173.06:41:10.37#ibcon#*mode == 0, iclass 40, count 2 2006.173.06:41:10.37#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.06:41:10.37#ibcon#[25=AT07-04\r\n] 2006.173.06:41:10.37#ibcon#*before write, iclass 40, count 2 2006.173.06:41:10.37#ibcon#enter sib2, iclass 40, count 2 2006.173.06:41:10.37#ibcon#flushed, iclass 40, count 2 2006.173.06:41:10.37#ibcon#about to write, iclass 40, count 2 2006.173.06:41:10.37#ibcon#wrote, iclass 40, count 2 2006.173.06:41:10.37#ibcon#about to read 3, iclass 40, count 2 2006.173.06:41:10.40#ibcon#read 3, iclass 40, count 2 2006.173.06:41:10.40#ibcon#about to read 4, iclass 40, count 2 2006.173.06:41:10.40#ibcon#read 4, iclass 40, count 2 2006.173.06:41:10.40#ibcon#about to read 5, iclass 40, count 2 2006.173.06:41:10.40#ibcon#read 5, iclass 40, count 2 2006.173.06:41:10.40#ibcon#about to read 6, iclass 40, count 2 2006.173.06:41:10.40#ibcon#read 6, iclass 40, count 2 2006.173.06:41:10.40#ibcon#end of sib2, iclass 40, count 2 2006.173.06:41:10.40#ibcon#*after write, iclass 40, count 2 2006.173.06:41:10.40#ibcon#*before return 0, iclass 40, count 2 2006.173.06:41:10.40#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.06:41:10.40#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.06:41:10.40#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.06:41:10.40#ibcon#ireg 7 cls_cnt 0 2006.173.06:41:10.40#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.06:41:10.52#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.06:41:10.52#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.06:41:10.52#ibcon#enter wrdev, iclass 40, count 0 2006.173.06:41:10.52#ibcon#first serial, iclass 40, count 0 2006.173.06:41:10.52#ibcon#enter sib2, iclass 40, count 0 2006.173.06:41:10.52#ibcon#flushed, iclass 40, count 0 2006.173.06:41:10.52#ibcon#about to write, iclass 40, count 0 2006.173.06:41:10.52#ibcon#wrote, iclass 40, count 0 2006.173.06:41:10.52#ibcon#about to read 3, iclass 40, count 0 2006.173.06:41:10.54#ibcon#read 3, iclass 40, count 0 2006.173.06:41:10.54#ibcon#about to read 4, iclass 40, count 0 2006.173.06:41:10.54#ibcon#read 4, iclass 40, count 0 2006.173.06:41:10.54#ibcon#about to read 5, iclass 40, count 0 2006.173.06:41:10.54#ibcon#read 5, iclass 40, count 0 2006.173.06:41:10.54#ibcon#about to read 6, iclass 40, count 0 2006.173.06:41:10.54#ibcon#read 6, iclass 40, count 0 2006.173.06:41:10.54#ibcon#end of sib2, iclass 40, count 0 2006.173.06:41:10.54#ibcon#*mode == 0, iclass 40, count 0 2006.173.06:41:10.54#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.06:41:10.54#ibcon#[25=USB\r\n] 2006.173.06:41:10.54#ibcon#*before write, iclass 40, count 0 2006.173.06:41:10.54#ibcon#enter sib2, iclass 40, count 0 2006.173.06:41:10.54#ibcon#flushed, iclass 40, count 0 2006.173.06:41:10.54#ibcon#about to write, iclass 40, count 0 2006.173.06:41:10.54#ibcon#wrote, iclass 40, count 0 2006.173.06:41:10.54#ibcon#about to read 3, iclass 40, count 0 2006.173.06:41:10.57#ibcon#read 3, iclass 40, count 0 2006.173.06:41:10.57#ibcon#about to read 4, iclass 40, count 0 2006.173.06:41:10.57#ibcon#read 4, iclass 40, count 0 2006.173.06:41:10.57#ibcon#about to read 5, iclass 40, count 0 2006.173.06:41:10.57#ibcon#read 5, iclass 40, count 0 2006.173.06:41:10.57#ibcon#about to read 6, iclass 40, count 0 2006.173.06:41:10.57#ibcon#read 6, iclass 40, count 0 2006.173.06:41:10.57#ibcon#end of sib2, iclass 40, count 0 2006.173.06:41:10.57#ibcon#*after write, iclass 40, count 0 2006.173.06:41:10.57#ibcon#*before return 0, iclass 40, count 0 2006.173.06:41:10.57#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.06:41:10.57#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.06:41:10.57#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.06:41:10.57#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.06:41:10.57$vck44/valo=8,884.99 2006.173.06:41:10.57#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.06:41:10.57#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.06:41:10.57#ibcon#ireg 17 cls_cnt 0 2006.173.06:41:10.57#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.06:41:10.57#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.06:41:10.57#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.06:41:10.57#ibcon#enter wrdev, iclass 4, count 0 2006.173.06:41:10.57#ibcon#first serial, iclass 4, count 0 2006.173.06:41:10.57#ibcon#enter sib2, iclass 4, count 0 2006.173.06:41:10.57#ibcon#flushed, iclass 4, count 0 2006.173.06:41:10.57#ibcon#about to write, iclass 4, count 0 2006.173.06:41:10.57#ibcon#wrote, iclass 4, count 0 2006.173.06:41:10.57#ibcon#about to read 3, iclass 4, count 0 2006.173.06:41:10.59#ibcon#read 3, iclass 4, count 0 2006.173.06:41:10.59#ibcon#about to read 4, iclass 4, count 0 2006.173.06:41:10.59#ibcon#read 4, iclass 4, count 0 2006.173.06:41:10.59#ibcon#about to read 5, iclass 4, count 0 2006.173.06:41:10.59#ibcon#read 5, iclass 4, count 0 2006.173.06:41:10.59#ibcon#about to read 6, iclass 4, count 0 2006.173.06:41:10.59#ibcon#read 6, iclass 4, count 0 2006.173.06:41:10.59#ibcon#end of sib2, iclass 4, count 0 2006.173.06:41:10.59#ibcon#*mode == 0, iclass 4, count 0 2006.173.06:41:10.59#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.06:41:10.59#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.06:41:10.59#ibcon#*before write, iclass 4, count 0 2006.173.06:41:10.59#ibcon#enter sib2, iclass 4, count 0 2006.173.06:41:10.59#ibcon#flushed, iclass 4, count 0 2006.173.06:41:10.59#ibcon#about to write, iclass 4, count 0 2006.173.06:41:10.59#ibcon#wrote, iclass 4, count 0 2006.173.06:41:10.59#ibcon#about to read 3, iclass 4, count 0 2006.173.06:41:10.63#ibcon#read 3, iclass 4, count 0 2006.173.06:41:10.63#ibcon#about to read 4, iclass 4, count 0 2006.173.06:41:10.63#ibcon#read 4, iclass 4, count 0 2006.173.06:41:10.63#ibcon#about to read 5, iclass 4, count 0 2006.173.06:41:10.63#ibcon#read 5, iclass 4, count 0 2006.173.06:41:10.63#ibcon#about to read 6, iclass 4, count 0 2006.173.06:41:10.63#ibcon#read 6, iclass 4, count 0 2006.173.06:41:10.63#ibcon#end of sib2, iclass 4, count 0 2006.173.06:41:10.63#ibcon#*after write, iclass 4, count 0 2006.173.06:41:10.63#ibcon#*before return 0, iclass 4, count 0 2006.173.06:41:10.63#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.06:41:10.63#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.06:41:10.63#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.06:41:10.63#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.06:41:10.63$vck44/va=8,4 2006.173.06:41:10.63#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.06:41:10.63#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.06:41:10.63#ibcon#ireg 11 cls_cnt 2 2006.173.06:41:10.63#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.06:41:10.69#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.06:41:10.69#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.06:41:10.69#ibcon#enter wrdev, iclass 6, count 2 2006.173.06:41:10.69#ibcon#first serial, iclass 6, count 2 2006.173.06:41:10.69#ibcon#enter sib2, iclass 6, count 2 2006.173.06:41:10.69#ibcon#flushed, iclass 6, count 2 2006.173.06:41:10.69#ibcon#about to write, iclass 6, count 2 2006.173.06:41:10.69#ibcon#wrote, iclass 6, count 2 2006.173.06:41:10.69#ibcon#about to read 3, iclass 6, count 2 2006.173.06:41:10.71#ibcon#read 3, iclass 6, count 2 2006.173.06:41:10.71#ibcon#about to read 4, iclass 6, count 2 2006.173.06:41:10.71#ibcon#read 4, iclass 6, count 2 2006.173.06:41:10.71#ibcon#about to read 5, iclass 6, count 2 2006.173.06:41:10.71#ibcon#read 5, iclass 6, count 2 2006.173.06:41:10.71#ibcon#about to read 6, iclass 6, count 2 2006.173.06:41:10.71#ibcon#read 6, iclass 6, count 2 2006.173.06:41:10.71#ibcon#end of sib2, iclass 6, count 2 2006.173.06:41:10.71#ibcon#*mode == 0, iclass 6, count 2 2006.173.06:41:10.71#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.06:41:10.71#ibcon#[25=AT08-04\r\n] 2006.173.06:41:10.71#ibcon#*before write, iclass 6, count 2 2006.173.06:41:10.71#ibcon#enter sib2, iclass 6, count 2 2006.173.06:41:10.71#ibcon#flushed, iclass 6, count 2 2006.173.06:41:10.71#ibcon#about to write, iclass 6, count 2 2006.173.06:41:10.71#ibcon#wrote, iclass 6, count 2 2006.173.06:41:10.71#ibcon#about to read 3, iclass 6, count 2 2006.173.06:41:10.74#ibcon#read 3, iclass 6, count 2 2006.173.06:41:10.74#ibcon#about to read 4, iclass 6, count 2 2006.173.06:41:10.74#ibcon#read 4, iclass 6, count 2 2006.173.06:41:10.74#ibcon#about to read 5, iclass 6, count 2 2006.173.06:41:10.74#ibcon#read 5, iclass 6, count 2 2006.173.06:41:10.74#ibcon#about to read 6, iclass 6, count 2 2006.173.06:41:10.74#ibcon#read 6, iclass 6, count 2 2006.173.06:41:10.74#ibcon#end of sib2, iclass 6, count 2 2006.173.06:41:10.74#ibcon#*after write, iclass 6, count 2 2006.173.06:41:10.74#ibcon#*before return 0, iclass 6, count 2 2006.173.06:41:10.74#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.06:41:10.74#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.06:41:10.74#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.06:41:10.74#ibcon#ireg 7 cls_cnt 0 2006.173.06:41:10.74#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.06:41:10.86#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.06:41:10.86#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.06:41:10.86#ibcon#enter wrdev, iclass 6, count 0 2006.173.06:41:10.86#ibcon#first serial, iclass 6, count 0 2006.173.06:41:10.86#ibcon#enter sib2, iclass 6, count 0 2006.173.06:41:10.86#ibcon#flushed, iclass 6, count 0 2006.173.06:41:10.86#ibcon#about to write, iclass 6, count 0 2006.173.06:41:10.86#ibcon#wrote, iclass 6, count 0 2006.173.06:41:10.86#ibcon#about to read 3, iclass 6, count 0 2006.173.06:41:10.88#ibcon#read 3, iclass 6, count 0 2006.173.06:41:10.88#ibcon#about to read 4, iclass 6, count 0 2006.173.06:41:10.88#ibcon#read 4, iclass 6, count 0 2006.173.06:41:10.88#ibcon#about to read 5, iclass 6, count 0 2006.173.06:41:10.88#ibcon#read 5, iclass 6, count 0 2006.173.06:41:10.88#ibcon#about to read 6, iclass 6, count 0 2006.173.06:41:10.88#ibcon#read 6, iclass 6, count 0 2006.173.06:41:10.88#ibcon#end of sib2, iclass 6, count 0 2006.173.06:41:10.88#ibcon#*mode == 0, iclass 6, count 0 2006.173.06:41:10.88#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.06:41:10.88#ibcon#[25=USB\r\n] 2006.173.06:41:10.88#ibcon#*before write, iclass 6, count 0 2006.173.06:41:10.88#ibcon#enter sib2, iclass 6, count 0 2006.173.06:41:10.88#ibcon#flushed, iclass 6, count 0 2006.173.06:41:10.88#ibcon#about to write, iclass 6, count 0 2006.173.06:41:10.88#ibcon#wrote, iclass 6, count 0 2006.173.06:41:10.88#ibcon#about to read 3, iclass 6, count 0 2006.173.06:41:10.91#ibcon#read 3, iclass 6, count 0 2006.173.06:41:10.91#ibcon#about to read 4, iclass 6, count 0 2006.173.06:41:10.91#ibcon#read 4, iclass 6, count 0 2006.173.06:41:10.91#ibcon#about to read 5, iclass 6, count 0 2006.173.06:41:10.91#ibcon#read 5, iclass 6, count 0 2006.173.06:41:10.91#ibcon#about to read 6, iclass 6, count 0 2006.173.06:41:10.91#ibcon#read 6, iclass 6, count 0 2006.173.06:41:10.91#ibcon#end of sib2, iclass 6, count 0 2006.173.06:41:10.91#ibcon#*after write, iclass 6, count 0 2006.173.06:41:10.91#ibcon#*before return 0, iclass 6, count 0 2006.173.06:41:10.91#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.06:41:10.91#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.06:41:10.91#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.06:41:10.91#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.06:41:10.91$vck44/vblo=1,629.99 2006.173.06:41:10.91#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.06:41:10.91#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.06:41:10.91#ibcon#ireg 17 cls_cnt 0 2006.173.06:41:10.91#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.06:41:10.91#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.06:41:10.91#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.06:41:10.91#ibcon#enter wrdev, iclass 10, count 0 2006.173.06:41:10.91#ibcon#first serial, iclass 10, count 0 2006.173.06:41:10.91#ibcon#enter sib2, iclass 10, count 0 2006.173.06:41:10.91#ibcon#flushed, iclass 10, count 0 2006.173.06:41:10.91#ibcon#about to write, iclass 10, count 0 2006.173.06:41:10.91#ibcon#wrote, iclass 10, count 0 2006.173.06:41:10.91#ibcon#about to read 3, iclass 10, count 0 2006.173.06:41:10.93#ibcon#read 3, iclass 10, count 0 2006.173.06:41:10.93#ibcon#about to read 4, iclass 10, count 0 2006.173.06:41:10.93#ibcon#read 4, iclass 10, count 0 2006.173.06:41:10.93#ibcon#about to read 5, iclass 10, count 0 2006.173.06:41:10.93#ibcon#read 5, iclass 10, count 0 2006.173.06:41:10.93#ibcon#about to read 6, iclass 10, count 0 2006.173.06:41:10.93#ibcon#read 6, iclass 10, count 0 2006.173.06:41:10.93#ibcon#end of sib2, iclass 10, count 0 2006.173.06:41:10.93#ibcon#*mode == 0, iclass 10, count 0 2006.173.06:41:10.93#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.06:41:10.93#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.06:41:10.93#ibcon#*before write, iclass 10, count 0 2006.173.06:41:10.93#ibcon#enter sib2, iclass 10, count 0 2006.173.06:41:10.93#ibcon#flushed, iclass 10, count 0 2006.173.06:41:10.93#ibcon#about to write, iclass 10, count 0 2006.173.06:41:10.93#ibcon#wrote, iclass 10, count 0 2006.173.06:41:10.93#ibcon#about to read 3, iclass 10, count 0 2006.173.06:41:10.97#ibcon#read 3, iclass 10, count 0 2006.173.06:41:10.97#ibcon#about to read 4, iclass 10, count 0 2006.173.06:41:10.97#ibcon#read 4, iclass 10, count 0 2006.173.06:41:10.97#ibcon#about to read 5, iclass 10, count 0 2006.173.06:41:10.97#ibcon#read 5, iclass 10, count 0 2006.173.06:41:10.97#ibcon#about to read 6, iclass 10, count 0 2006.173.06:41:10.97#ibcon#read 6, iclass 10, count 0 2006.173.06:41:10.97#ibcon#end of sib2, iclass 10, count 0 2006.173.06:41:10.97#ibcon#*after write, iclass 10, count 0 2006.173.06:41:10.97#ibcon#*before return 0, iclass 10, count 0 2006.173.06:41:10.97#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.06:41:10.97#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.06:41:10.97#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.06:41:10.97#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.06:41:10.97$vck44/vb=1,4 2006.173.06:41:10.97#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.06:41:10.97#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.06:41:10.97#ibcon#ireg 11 cls_cnt 2 2006.173.06:41:10.97#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.06:41:10.97#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.06:41:10.97#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.06:41:10.97#ibcon#enter wrdev, iclass 12, count 2 2006.173.06:41:10.97#ibcon#first serial, iclass 12, count 2 2006.173.06:41:10.97#ibcon#enter sib2, iclass 12, count 2 2006.173.06:41:10.97#ibcon#flushed, iclass 12, count 2 2006.173.06:41:10.97#ibcon#about to write, iclass 12, count 2 2006.173.06:41:10.97#ibcon#wrote, iclass 12, count 2 2006.173.06:41:10.97#ibcon#about to read 3, iclass 12, count 2 2006.173.06:41:10.99#ibcon#read 3, iclass 12, count 2 2006.173.06:41:10.99#ibcon#about to read 4, iclass 12, count 2 2006.173.06:41:10.99#ibcon#read 4, iclass 12, count 2 2006.173.06:41:10.99#ibcon#about to read 5, iclass 12, count 2 2006.173.06:41:10.99#ibcon#read 5, iclass 12, count 2 2006.173.06:41:10.99#ibcon#about to read 6, iclass 12, count 2 2006.173.06:41:10.99#ibcon#read 6, iclass 12, count 2 2006.173.06:41:10.99#ibcon#end of sib2, iclass 12, count 2 2006.173.06:41:10.99#ibcon#*mode == 0, iclass 12, count 2 2006.173.06:41:10.99#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.06:41:10.99#ibcon#[27=AT01-04\r\n] 2006.173.06:41:10.99#ibcon#*before write, iclass 12, count 2 2006.173.06:41:10.99#ibcon#enter sib2, iclass 12, count 2 2006.173.06:41:10.99#ibcon#flushed, iclass 12, count 2 2006.173.06:41:10.99#ibcon#about to write, iclass 12, count 2 2006.173.06:41:10.99#ibcon#wrote, iclass 12, count 2 2006.173.06:41:10.99#ibcon#about to read 3, iclass 12, count 2 2006.173.06:41:11.02#ibcon#read 3, iclass 12, count 2 2006.173.06:41:11.02#ibcon#about to read 4, iclass 12, count 2 2006.173.06:41:11.02#ibcon#read 4, iclass 12, count 2 2006.173.06:41:11.02#ibcon#about to read 5, iclass 12, count 2 2006.173.06:41:11.02#ibcon#read 5, iclass 12, count 2 2006.173.06:41:11.02#ibcon#about to read 6, iclass 12, count 2 2006.173.06:41:11.02#ibcon#read 6, iclass 12, count 2 2006.173.06:41:11.02#ibcon#end of sib2, iclass 12, count 2 2006.173.06:41:11.02#ibcon#*after write, iclass 12, count 2 2006.173.06:41:11.02#ibcon#*before return 0, iclass 12, count 2 2006.173.06:41:11.02#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.06:41:11.02#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.06:41:11.02#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.06:41:11.02#ibcon#ireg 7 cls_cnt 0 2006.173.06:41:11.02#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.06:41:11.14#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.06:41:11.14#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.06:41:11.14#ibcon#enter wrdev, iclass 12, count 0 2006.173.06:41:11.14#ibcon#first serial, iclass 12, count 0 2006.173.06:41:11.14#ibcon#enter sib2, iclass 12, count 0 2006.173.06:41:11.14#ibcon#flushed, iclass 12, count 0 2006.173.06:41:11.14#ibcon#about to write, iclass 12, count 0 2006.173.06:41:11.14#ibcon#wrote, iclass 12, count 0 2006.173.06:41:11.14#ibcon#about to read 3, iclass 12, count 0 2006.173.06:41:11.16#ibcon#read 3, iclass 12, count 0 2006.173.06:41:11.16#ibcon#about to read 4, iclass 12, count 0 2006.173.06:41:11.16#ibcon#read 4, iclass 12, count 0 2006.173.06:41:11.16#ibcon#about to read 5, iclass 12, count 0 2006.173.06:41:11.16#ibcon#read 5, iclass 12, count 0 2006.173.06:41:11.16#ibcon#about to read 6, iclass 12, count 0 2006.173.06:41:11.16#ibcon#read 6, iclass 12, count 0 2006.173.06:41:11.16#ibcon#end of sib2, iclass 12, count 0 2006.173.06:41:11.16#ibcon#*mode == 0, iclass 12, count 0 2006.173.06:41:11.16#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.06:41:11.16#ibcon#[27=USB\r\n] 2006.173.06:41:11.16#ibcon#*before write, iclass 12, count 0 2006.173.06:41:11.16#ibcon#enter sib2, iclass 12, count 0 2006.173.06:41:11.16#ibcon#flushed, iclass 12, count 0 2006.173.06:41:11.16#ibcon#about to write, iclass 12, count 0 2006.173.06:41:11.16#ibcon#wrote, iclass 12, count 0 2006.173.06:41:11.16#ibcon#about to read 3, iclass 12, count 0 2006.173.06:41:11.19#ibcon#read 3, iclass 12, count 0 2006.173.06:41:11.19#ibcon#about to read 4, iclass 12, count 0 2006.173.06:41:11.19#ibcon#read 4, iclass 12, count 0 2006.173.06:41:11.19#ibcon#about to read 5, iclass 12, count 0 2006.173.06:41:11.19#ibcon#read 5, iclass 12, count 0 2006.173.06:41:11.19#ibcon#about to read 6, iclass 12, count 0 2006.173.06:41:11.19#ibcon#read 6, iclass 12, count 0 2006.173.06:41:11.19#ibcon#end of sib2, iclass 12, count 0 2006.173.06:41:11.19#ibcon#*after write, iclass 12, count 0 2006.173.06:41:11.19#ibcon#*before return 0, iclass 12, count 0 2006.173.06:41:11.19#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.06:41:11.19#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.06:41:11.19#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.06:41:11.19#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.06:41:11.19$vck44/vblo=2,634.99 2006.173.06:41:11.19#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.06:41:11.19#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.06:41:11.19#ibcon#ireg 17 cls_cnt 0 2006.173.06:41:11.19#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.06:41:11.19#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.06:41:11.19#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.06:41:11.19#ibcon#enter wrdev, iclass 14, count 0 2006.173.06:41:11.19#ibcon#first serial, iclass 14, count 0 2006.173.06:41:11.19#ibcon#enter sib2, iclass 14, count 0 2006.173.06:41:11.19#ibcon#flushed, iclass 14, count 0 2006.173.06:41:11.19#ibcon#about to write, iclass 14, count 0 2006.173.06:41:11.19#ibcon#wrote, iclass 14, count 0 2006.173.06:41:11.19#ibcon#about to read 3, iclass 14, count 0 2006.173.06:41:11.21#ibcon#read 3, iclass 14, count 0 2006.173.06:41:11.21#ibcon#about to read 4, iclass 14, count 0 2006.173.06:41:11.21#ibcon#read 4, iclass 14, count 0 2006.173.06:41:11.21#ibcon#about to read 5, iclass 14, count 0 2006.173.06:41:11.21#ibcon#read 5, iclass 14, count 0 2006.173.06:41:11.21#ibcon#about to read 6, iclass 14, count 0 2006.173.06:41:11.21#ibcon#read 6, iclass 14, count 0 2006.173.06:41:11.21#ibcon#end of sib2, iclass 14, count 0 2006.173.06:41:11.21#ibcon#*mode == 0, iclass 14, count 0 2006.173.06:41:11.21#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.06:41:11.21#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.06:41:11.21#ibcon#*before write, iclass 14, count 0 2006.173.06:41:11.21#ibcon#enter sib2, iclass 14, count 0 2006.173.06:41:11.21#ibcon#flushed, iclass 14, count 0 2006.173.06:41:11.21#ibcon#about to write, iclass 14, count 0 2006.173.06:41:11.21#ibcon#wrote, iclass 14, count 0 2006.173.06:41:11.21#ibcon#about to read 3, iclass 14, count 0 2006.173.06:41:11.25#ibcon#read 3, iclass 14, count 0 2006.173.06:41:11.25#ibcon#about to read 4, iclass 14, count 0 2006.173.06:41:11.25#ibcon#read 4, iclass 14, count 0 2006.173.06:41:11.25#ibcon#about to read 5, iclass 14, count 0 2006.173.06:41:11.25#ibcon#read 5, iclass 14, count 0 2006.173.06:41:11.25#ibcon#about to read 6, iclass 14, count 0 2006.173.06:41:11.25#ibcon#read 6, iclass 14, count 0 2006.173.06:41:11.25#ibcon#end of sib2, iclass 14, count 0 2006.173.06:41:11.25#ibcon#*after write, iclass 14, count 0 2006.173.06:41:11.25#ibcon#*before return 0, iclass 14, count 0 2006.173.06:41:11.25#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.06:41:11.25#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.06:41:11.25#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.06:41:11.25#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.06:41:11.25$vck44/vb=2,4 2006.173.06:41:11.25#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.06:41:11.25#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.06:41:11.25#ibcon#ireg 11 cls_cnt 2 2006.173.06:41:11.25#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.06:41:11.31#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.06:41:11.31#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.06:41:11.31#ibcon#enter wrdev, iclass 16, count 2 2006.173.06:41:11.31#ibcon#first serial, iclass 16, count 2 2006.173.06:41:11.31#ibcon#enter sib2, iclass 16, count 2 2006.173.06:41:11.31#ibcon#flushed, iclass 16, count 2 2006.173.06:41:11.31#ibcon#about to write, iclass 16, count 2 2006.173.06:41:11.31#ibcon#wrote, iclass 16, count 2 2006.173.06:41:11.31#ibcon#about to read 3, iclass 16, count 2 2006.173.06:41:11.33#ibcon#read 3, iclass 16, count 2 2006.173.06:41:11.33#ibcon#about to read 4, iclass 16, count 2 2006.173.06:41:11.33#ibcon#read 4, iclass 16, count 2 2006.173.06:41:11.33#ibcon#about to read 5, iclass 16, count 2 2006.173.06:41:11.33#ibcon#read 5, iclass 16, count 2 2006.173.06:41:11.33#ibcon#about to read 6, iclass 16, count 2 2006.173.06:41:11.33#ibcon#read 6, iclass 16, count 2 2006.173.06:41:11.33#ibcon#end of sib2, iclass 16, count 2 2006.173.06:41:11.33#ibcon#*mode == 0, iclass 16, count 2 2006.173.06:41:11.33#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.06:41:11.33#ibcon#[27=AT02-04\r\n] 2006.173.06:41:11.33#ibcon#*before write, iclass 16, count 2 2006.173.06:41:11.33#ibcon#enter sib2, iclass 16, count 2 2006.173.06:41:11.33#ibcon#flushed, iclass 16, count 2 2006.173.06:41:11.33#ibcon#about to write, iclass 16, count 2 2006.173.06:41:11.33#ibcon#wrote, iclass 16, count 2 2006.173.06:41:11.33#ibcon#about to read 3, iclass 16, count 2 2006.173.06:41:11.36#ibcon#read 3, iclass 16, count 2 2006.173.06:41:11.36#ibcon#about to read 4, iclass 16, count 2 2006.173.06:41:11.36#ibcon#read 4, iclass 16, count 2 2006.173.06:41:11.36#ibcon#about to read 5, iclass 16, count 2 2006.173.06:41:11.36#ibcon#read 5, iclass 16, count 2 2006.173.06:41:11.36#ibcon#about to read 6, iclass 16, count 2 2006.173.06:41:11.36#ibcon#read 6, iclass 16, count 2 2006.173.06:41:11.36#ibcon#end of sib2, iclass 16, count 2 2006.173.06:41:11.36#ibcon#*after write, iclass 16, count 2 2006.173.06:41:11.36#ibcon#*before return 0, iclass 16, count 2 2006.173.06:41:11.36#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.06:41:11.36#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.06:41:11.36#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.06:41:11.36#ibcon#ireg 7 cls_cnt 0 2006.173.06:41:11.36#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.06:41:11.48#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.06:41:11.48#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.06:41:11.48#ibcon#enter wrdev, iclass 16, count 0 2006.173.06:41:11.48#ibcon#first serial, iclass 16, count 0 2006.173.06:41:11.48#ibcon#enter sib2, iclass 16, count 0 2006.173.06:41:11.48#ibcon#flushed, iclass 16, count 0 2006.173.06:41:11.48#ibcon#about to write, iclass 16, count 0 2006.173.06:41:11.48#ibcon#wrote, iclass 16, count 0 2006.173.06:41:11.48#ibcon#about to read 3, iclass 16, count 0 2006.173.06:41:11.50#ibcon#read 3, iclass 16, count 0 2006.173.06:41:11.50#ibcon#about to read 4, iclass 16, count 0 2006.173.06:41:11.50#ibcon#read 4, iclass 16, count 0 2006.173.06:41:11.50#ibcon#about to read 5, iclass 16, count 0 2006.173.06:41:11.50#ibcon#read 5, iclass 16, count 0 2006.173.06:41:11.50#ibcon#about to read 6, iclass 16, count 0 2006.173.06:41:11.50#ibcon#read 6, iclass 16, count 0 2006.173.06:41:11.50#ibcon#end of sib2, iclass 16, count 0 2006.173.06:41:11.50#ibcon#*mode == 0, iclass 16, count 0 2006.173.06:41:11.50#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.06:41:11.50#ibcon#[27=USB\r\n] 2006.173.06:41:11.50#ibcon#*before write, iclass 16, count 0 2006.173.06:41:11.50#ibcon#enter sib2, iclass 16, count 0 2006.173.06:41:11.50#ibcon#flushed, iclass 16, count 0 2006.173.06:41:11.50#ibcon#about to write, iclass 16, count 0 2006.173.06:41:11.50#ibcon#wrote, iclass 16, count 0 2006.173.06:41:11.50#ibcon#about to read 3, iclass 16, count 0 2006.173.06:41:11.53#ibcon#read 3, iclass 16, count 0 2006.173.06:41:11.53#ibcon#about to read 4, iclass 16, count 0 2006.173.06:41:11.53#ibcon#read 4, iclass 16, count 0 2006.173.06:41:11.53#ibcon#about to read 5, iclass 16, count 0 2006.173.06:41:11.53#ibcon#read 5, iclass 16, count 0 2006.173.06:41:11.53#ibcon#about to read 6, iclass 16, count 0 2006.173.06:41:11.53#ibcon#read 6, iclass 16, count 0 2006.173.06:41:11.53#ibcon#end of sib2, iclass 16, count 0 2006.173.06:41:11.53#ibcon#*after write, iclass 16, count 0 2006.173.06:41:11.53#ibcon#*before return 0, iclass 16, count 0 2006.173.06:41:11.53#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.06:41:11.53#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.06:41:11.53#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.06:41:11.53#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.06:41:11.53$vck44/vblo=3,649.99 2006.173.06:41:11.53#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.06:41:11.53#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.06:41:11.53#ibcon#ireg 17 cls_cnt 0 2006.173.06:41:11.53#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.06:41:11.53#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.06:41:11.53#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.06:41:11.53#ibcon#enter wrdev, iclass 18, count 0 2006.173.06:41:11.53#ibcon#first serial, iclass 18, count 0 2006.173.06:41:11.53#ibcon#enter sib2, iclass 18, count 0 2006.173.06:41:11.53#ibcon#flushed, iclass 18, count 0 2006.173.06:41:11.53#ibcon#about to write, iclass 18, count 0 2006.173.06:41:11.53#ibcon#wrote, iclass 18, count 0 2006.173.06:41:11.53#ibcon#about to read 3, iclass 18, count 0 2006.173.06:41:11.55#ibcon#read 3, iclass 18, count 0 2006.173.06:41:11.55#ibcon#about to read 4, iclass 18, count 0 2006.173.06:41:11.55#ibcon#read 4, iclass 18, count 0 2006.173.06:41:11.55#ibcon#about to read 5, iclass 18, count 0 2006.173.06:41:11.55#ibcon#read 5, iclass 18, count 0 2006.173.06:41:11.55#ibcon#about to read 6, iclass 18, count 0 2006.173.06:41:11.55#ibcon#read 6, iclass 18, count 0 2006.173.06:41:11.55#ibcon#end of sib2, iclass 18, count 0 2006.173.06:41:11.55#ibcon#*mode == 0, iclass 18, count 0 2006.173.06:41:11.55#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.06:41:11.55#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.06:41:11.55#ibcon#*before write, iclass 18, count 0 2006.173.06:41:11.55#ibcon#enter sib2, iclass 18, count 0 2006.173.06:41:11.55#ibcon#flushed, iclass 18, count 0 2006.173.06:41:11.55#ibcon#about to write, iclass 18, count 0 2006.173.06:41:11.55#ibcon#wrote, iclass 18, count 0 2006.173.06:41:11.55#ibcon#about to read 3, iclass 18, count 0 2006.173.06:41:11.59#ibcon#read 3, iclass 18, count 0 2006.173.06:41:11.59#ibcon#about to read 4, iclass 18, count 0 2006.173.06:41:11.59#ibcon#read 4, iclass 18, count 0 2006.173.06:41:11.59#ibcon#about to read 5, iclass 18, count 0 2006.173.06:41:11.59#ibcon#read 5, iclass 18, count 0 2006.173.06:41:11.59#ibcon#about to read 6, iclass 18, count 0 2006.173.06:41:11.59#ibcon#read 6, iclass 18, count 0 2006.173.06:41:11.59#ibcon#end of sib2, iclass 18, count 0 2006.173.06:41:11.59#ibcon#*after write, iclass 18, count 0 2006.173.06:41:11.59#ibcon#*before return 0, iclass 18, count 0 2006.173.06:41:11.59#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.06:41:11.59#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.06:41:11.59#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.06:41:11.59#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.06:41:11.59$vck44/vb=3,4 2006.173.06:41:11.59#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.06:41:11.59#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.06:41:11.59#ibcon#ireg 11 cls_cnt 2 2006.173.06:41:11.59#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.06:41:11.65#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.06:41:11.65#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.06:41:11.65#ibcon#enter wrdev, iclass 20, count 2 2006.173.06:41:11.65#ibcon#first serial, iclass 20, count 2 2006.173.06:41:11.65#ibcon#enter sib2, iclass 20, count 2 2006.173.06:41:11.65#ibcon#flushed, iclass 20, count 2 2006.173.06:41:11.65#ibcon#about to write, iclass 20, count 2 2006.173.06:41:11.65#ibcon#wrote, iclass 20, count 2 2006.173.06:41:11.65#ibcon#about to read 3, iclass 20, count 2 2006.173.06:41:11.67#ibcon#read 3, iclass 20, count 2 2006.173.06:41:11.67#ibcon#about to read 4, iclass 20, count 2 2006.173.06:41:11.67#ibcon#read 4, iclass 20, count 2 2006.173.06:41:11.67#ibcon#about to read 5, iclass 20, count 2 2006.173.06:41:11.67#ibcon#read 5, iclass 20, count 2 2006.173.06:41:11.67#ibcon#about to read 6, iclass 20, count 2 2006.173.06:41:11.67#ibcon#read 6, iclass 20, count 2 2006.173.06:41:11.67#ibcon#end of sib2, iclass 20, count 2 2006.173.06:41:11.67#ibcon#*mode == 0, iclass 20, count 2 2006.173.06:41:11.67#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.06:41:11.67#ibcon#[27=AT03-04\r\n] 2006.173.06:41:11.67#ibcon#*before write, iclass 20, count 2 2006.173.06:41:11.67#ibcon#enter sib2, iclass 20, count 2 2006.173.06:41:11.67#ibcon#flushed, iclass 20, count 2 2006.173.06:41:11.67#ibcon#about to write, iclass 20, count 2 2006.173.06:41:11.67#ibcon#wrote, iclass 20, count 2 2006.173.06:41:11.67#ibcon#about to read 3, iclass 20, count 2 2006.173.06:41:11.70#ibcon#read 3, iclass 20, count 2 2006.173.06:41:11.70#ibcon#about to read 4, iclass 20, count 2 2006.173.06:41:11.70#ibcon#read 4, iclass 20, count 2 2006.173.06:41:11.70#ibcon#about to read 5, iclass 20, count 2 2006.173.06:41:11.70#ibcon#read 5, iclass 20, count 2 2006.173.06:41:11.70#ibcon#about to read 6, iclass 20, count 2 2006.173.06:41:11.70#ibcon#read 6, iclass 20, count 2 2006.173.06:41:11.70#ibcon#end of sib2, iclass 20, count 2 2006.173.06:41:11.70#ibcon#*after write, iclass 20, count 2 2006.173.06:41:11.70#ibcon#*before return 0, iclass 20, count 2 2006.173.06:41:11.70#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.06:41:11.70#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.06:41:11.70#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.06:41:11.70#ibcon#ireg 7 cls_cnt 0 2006.173.06:41:11.70#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.06:41:11.82#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.06:41:11.82#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.06:41:11.82#ibcon#enter wrdev, iclass 20, count 0 2006.173.06:41:11.82#ibcon#first serial, iclass 20, count 0 2006.173.06:41:11.82#ibcon#enter sib2, iclass 20, count 0 2006.173.06:41:11.82#ibcon#flushed, iclass 20, count 0 2006.173.06:41:11.82#ibcon#about to write, iclass 20, count 0 2006.173.06:41:11.82#ibcon#wrote, iclass 20, count 0 2006.173.06:41:11.82#ibcon#about to read 3, iclass 20, count 0 2006.173.06:41:11.84#ibcon#read 3, iclass 20, count 0 2006.173.06:41:11.84#ibcon#about to read 4, iclass 20, count 0 2006.173.06:41:11.84#ibcon#read 4, iclass 20, count 0 2006.173.06:41:11.84#ibcon#about to read 5, iclass 20, count 0 2006.173.06:41:11.84#ibcon#read 5, iclass 20, count 0 2006.173.06:41:11.84#ibcon#about to read 6, iclass 20, count 0 2006.173.06:41:11.84#ibcon#read 6, iclass 20, count 0 2006.173.06:41:11.84#ibcon#end of sib2, iclass 20, count 0 2006.173.06:41:11.84#ibcon#*mode == 0, iclass 20, count 0 2006.173.06:41:11.84#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.06:41:11.84#ibcon#[27=USB\r\n] 2006.173.06:41:11.84#ibcon#*before write, iclass 20, count 0 2006.173.06:41:11.84#ibcon#enter sib2, iclass 20, count 0 2006.173.06:41:11.84#ibcon#flushed, iclass 20, count 0 2006.173.06:41:11.84#ibcon#about to write, iclass 20, count 0 2006.173.06:41:11.84#ibcon#wrote, iclass 20, count 0 2006.173.06:41:11.84#ibcon#about to read 3, iclass 20, count 0 2006.173.06:41:11.87#ibcon#read 3, iclass 20, count 0 2006.173.06:41:11.87#ibcon#about to read 4, iclass 20, count 0 2006.173.06:41:11.87#ibcon#read 4, iclass 20, count 0 2006.173.06:41:11.87#ibcon#about to read 5, iclass 20, count 0 2006.173.06:41:11.87#ibcon#read 5, iclass 20, count 0 2006.173.06:41:11.87#ibcon#about to read 6, iclass 20, count 0 2006.173.06:41:11.87#ibcon#read 6, iclass 20, count 0 2006.173.06:41:11.87#ibcon#end of sib2, iclass 20, count 0 2006.173.06:41:11.87#ibcon#*after write, iclass 20, count 0 2006.173.06:41:11.87#ibcon#*before return 0, iclass 20, count 0 2006.173.06:41:11.87#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.06:41:11.87#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.06:41:11.87#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.06:41:11.87#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.06:41:11.87$vck44/vblo=4,679.99 2006.173.06:41:11.87#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.06:41:11.87#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.06:41:11.87#ibcon#ireg 17 cls_cnt 0 2006.173.06:41:11.87#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.06:41:11.87#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.06:41:11.87#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.06:41:11.87#ibcon#enter wrdev, iclass 22, count 0 2006.173.06:41:11.87#ibcon#first serial, iclass 22, count 0 2006.173.06:41:11.87#ibcon#enter sib2, iclass 22, count 0 2006.173.06:41:11.87#ibcon#flushed, iclass 22, count 0 2006.173.06:41:11.87#ibcon#about to write, iclass 22, count 0 2006.173.06:41:11.87#ibcon#wrote, iclass 22, count 0 2006.173.06:41:11.87#ibcon#about to read 3, iclass 22, count 0 2006.173.06:41:11.89#ibcon#read 3, iclass 22, count 0 2006.173.06:41:11.89#ibcon#about to read 4, iclass 22, count 0 2006.173.06:41:11.89#ibcon#read 4, iclass 22, count 0 2006.173.06:41:11.89#ibcon#about to read 5, iclass 22, count 0 2006.173.06:41:11.89#ibcon#read 5, iclass 22, count 0 2006.173.06:41:11.89#ibcon#about to read 6, iclass 22, count 0 2006.173.06:41:11.89#ibcon#read 6, iclass 22, count 0 2006.173.06:41:11.89#ibcon#end of sib2, iclass 22, count 0 2006.173.06:41:11.89#ibcon#*mode == 0, iclass 22, count 0 2006.173.06:41:11.89#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.06:41:11.89#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.06:41:11.89#ibcon#*before write, iclass 22, count 0 2006.173.06:41:11.89#ibcon#enter sib2, iclass 22, count 0 2006.173.06:41:11.89#ibcon#flushed, iclass 22, count 0 2006.173.06:41:11.89#ibcon#about to write, iclass 22, count 0 2006.173.06:41:11.89#ibcon#wrote, iclass 22, count 0 2006.173.06:41:11.89#ibcon#about to read 3, iclass 22, count 0 2006.173.06:41:11.93#ibcon#read 3, iclass 22, count 0 2006.173.06:41:11.93#ibcon#about to read 4, iclass 22, count 0 2006.173.06:41:11.93#ibcon#read 4, iclass 22, count 0 2006.173.06:41:11.93#ibcon#about to read 5, iclass 22, count 0 2006.173.06:41:11.93#ibcon#read 5, iclass 22, count 0 2006.173.06:41:11.93#ibcon#about to read 6, iclass 22, count 0 2006.173.06:41:11.93#ibcon#read 6, iclass 22, count 0 2006.173.06:41:11.93#ibcon#end of sib2, iclass 22, count 0 2006.173.06:41:11.93#ibcon#*after write, iclass 22, count 0 2006.173.06:41:11.93#ibcon#*before return 0, iclass 22, count 0 2006.173.06:41:11.93#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.06:41:11.93#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.06:41:11.93#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.06:41:11.93#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.06:41:11.93$vck44/vb=4,4 2006.173.06:41:11.93#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.06:41:11.93#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.06:41:11.93#ibcon#ireg 11 cls_cnt 2 2006.173.06:41:11.93#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.06:41:11.99#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.06:41:11.99#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.06:41:11.99#ibcon#enter wrdev, iclass 24, count 2 2006.173.06:41:11.99#ibcon#first serial, iclass 24, count 2 2006.173.06:41:11.99#ibcon#enter sib2, iclass 24, count 2 2006.173.06:41:11.99#ibcon#flushed, iclass 24, count 2 2006.173.06:41:11.99#ibcon#about to write, iclass 24, count 2 2006.173.06:41:11.99#ibcon#wrote, iclass 24, count 2 2006.173.06:41:11.99#ibcon#about to read 3, iclass 24, count 2 2006.173.06:41:12.01#ibcon#read 3, iclass 24, count 2 2006.173.06:41:12.01#ibcon#about to read 4, iclass 24, count 2 2006.173.06:41:12.01#ibcon#read 4, iclass 24, count 2 2006.173.06:41:12.01#ibcon#about to read 5, iclass 24, count 2 2006.173.06:41:12.01#ibcon#read 5, iclass 24, count 2 2006.173.06:41:12.01#ibcon#about to read 6, iclass 24, count 2 2006.173.06:41:12.01#ibcon#read 6, iclass 24, count 2 2006.173.06:41:12.01#ibcon#end of sib2, iclass 24, count 2 2006.173.06:41:12.01#ibcon#*mode == 0, iclass 24, count 2 2006.173.06:41:12.01#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.06:41:12.01#ibcon#[27=AT04-04\r\n] 2006.173.06:41:12.01#ibcon#*before write, iclass 24, count 2 2006.173.06:41:12.01#ibcon#enter sib2, iclass 24, count 2 2006.173.06:41:12.01#ibcon#flushed, iclass 24, count 2 2006.173.06:41:12.01#ibcon#about to write, iclass 24, count 2 2006.173.06:41:12.01#ibcon#wrote, iclass 24, count 2 2006.173.06:41:12.01#ibcon#about to read 3, iclass 24, count 2 2006.173.06:41:12.04#ibcon#read 3, iclass 24, count 2 2006.173.06:41:12.04#ibcon#about to read 4, iclass 24, count 2 2006.173.06:41:12.04#ibcon#read 4, iclass 24, count 2 2006.173.06:41:12.04#ibcon#about to read 5, iclass 24, count 2 2006.173.06:41:12.04#ibcon#read 5, iclass 24, count 2 2006.173.06:41:12.04#ibcon#about to read 6, iclass 24, count 2 2006.173.06:41:12.04#ibcon#read 6, iclass 24, count 2 2006.173.06:41:12.04#ibcon#end of sib2, iclass 24, count 2 2006.173.06:41:12.04#ibcon#*after write, iclass 24, count 2 2006.173.06:41:12.04#ibcon#*before return 0, iclass 24, count 2 2006.173.06:41:12.04#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.06:41:12.04#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.06:41:12.04#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.06:41:12.04#ibcon#ireg 7 cls_cnt 0 2006.173.06:41:12.04#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.06:41:12.16#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.06:41:12.16#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.06:41:12.16#ibcon#enter wrdev, iclass 24, count 0 2006.173.06:41:12.16#ibcon#first serial, iclass 24, count 0 2006.173.06:41:12.16#ibcon#enter sib2, iclass 24, count 0 2006.173.06:41:12.16#ibcon#flushed, iclass 24, count 0 2006.173.06:41:12.16#ibcon#about to write, iclass 24, count 0 2006.173.06:41:12.16#ibcon#wrote, iclass 24, count 0 2006.173.06:41:12.16#ibcon#about to read 3, iclass 24, count 0 2006.173.06:41:12.18#ibcon#read 3, iclass 24, count 0 2006.173.06:41:12.18#ibcon#about to read 4, iclass 24, count 0 2006.173.06:41:12.18#ibcon#read 4, iclass 24, count 0 2006.173.06:41:12.18#ibcon#about to read 5, iclass 24, count 0 2006.173.06:41:12.18#ibcon#read 5, iclass 24, count 0 2006.173.06:41:12.18#ibcon#about to read 6, iclass 24, count 0 2006.173.06:41:12.18#ibcon#read 6, iclass 24, count 0 2006.173.06:41:12.18#ibcon#end of sib2, iclass 24, count 0 2006.173.06:41:12.18#ibcon#*mode == 0, iclass 24, count 0 2006.173.06:41:12.18#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.06:41:12.18#ibcon#[27=USB\r\n] 2006.173.06:41:12.18#ibcon#*before write, iclass 24, count 0 2006.173.06:41:12.18#ibcon#enter sib2, iclass 24, count 0 2006.173.06:41:12.18#ibcon#flushed, iclass 24, count 0 2006.173.06:41:12.18#ibcon#about to write, iclass 24, count 0 2006.173.06:41:12.18#ibcon#wrote, iclass 24, count 0 2006.173.06:41:12.18#ibcon#about to read 3, iclass 24, count 0 2006.173.06:41:12.21#ibcon#read 3, iclass 24, count 0 2006.173.06:41:12.21#ibcon#about to read 4, iclass 24, count 0 2006.173.06:41:12.21#ibcon#read 4, iclass 24, count 0 2006.173.06:41:12.21#ibcon#about to read 5, iclass 24, count 0 2006.173.06:41:12.21#ibcon#read 5, iclass 24, count 0 2006.173.06:41:12.21#ibcon#about to read 6, iclass 24, count 0 2006.173.06:41:12.21#ibcon#read 6, iclass 24, count 0 2006.173.06:41:12.21#ibcon#end of sib2, iclass 24, count 0 2006.173.06:41:12.21#ibcon#*after write, iclass 24, count 0 2006.173.06:41:12.21#ibcon#*before return 0, iclass 24, count 0 2006.173.06:41:12.21#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.06:41:12.21#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.06:41:12.21#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.06:41:12.21#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.06:41:12.21$vck44/vblo=5,709.99 2006.173.06:41:12.21#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.06:41:12.21#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.06:41:12.21#ibcon#ireg 17 cls_cnt 0 2006.173.06:41:12.21#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.06:41:12.21#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.06:41:12.21#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.06:41:12.21#ibcon#enter wrdev, iclass 26, count 0 2006.173.06:41:12.21#ibcon#first serial, iclass 26, count 0 2006.173.06:41:12.21#ibcon#enter sib2, iclass 26, count 0 2006.173.06:41:12.21#ibcon#flushed, iclass 26, count 0 2006.173.06:41:12.21#ibcon#about to write, iclass 26, count 0 2006.173.06:41:12.21#ibcon#wrote, iclass 26, count 0 2006.173.06:41:12.21#ibcon#about to read 3, iclass 26, count 0 2006.173.06:41:12.23#ibcon#read 3, iclass 26, count 0 2006.173.06:41:12.23#ibcon#about to read 4, iclass 26, count 0 2006.173.06:41:12.23#ibcon#read 4, iclass 26, count 0 2006.173.06:41:12.23#ibcon#about to read 5, iclass 26, count 0 2006.173.06:41:12.23#ibcon#read 5, iclass 26, count 0 2006.173.06:41:12.23#ibcon#about to read 6, iclass 26, count 0 2006.173.06:41:12.23#ibcon#read 6, iclass 26, count 0 2006.173.06:41:12.23#ibcon#end of sib2, iclass 26, count 0 2006.173.06:41:12.23#ibcon#*mode == 0, iclass 26, count 0 2006.173.06:41:12.23#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.06:41:12.23#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.06:41:12.23#ibcon#*before write, iclass 26, count 0 2006.173.06:41:12.23#ibcon#enter sib2, iclass 26, count 0 2006.173.06:41:12.23#ibcon#flushed, iclass 26, count 0 2006.173.06:41:12.23#ibcon#about to write, iclass 26, count 0 2006.173.06:41:12.23#ibcon#wrote, iclass 26, count 0 2006.173.06:41:12.23#ibcon#about to read 3, iclass 26, count 0 2006.173.06:41:12.27#ibcon#read 3, iclass 26, count 0 2006.173.06:41:12.27#ibcon#about to read 4, iclass 26, count 0 2006.173.06:41:12.27#ibcon#read 4, iclass 26, count 0 2006.173.06:41:12.27#ibcon#about to read 5, iclass 26, count 0 2006.173.06:41:12.27#ibcon#read 5, iclass 26, count 0 2006.173.06:41:12.27#ibcon#about to read 6, iclass 26, count 0 2006.173.06:41:12.27#ibcon#read 6, iclass 26, count 0 2006.173.06:41:12.27#ibcon#end of sib2, iclass 26, count 0 2006.173.06:41:12.27#ibcon#*after write, iclass 26, count 0 2006.173.06:41:12.27#ibcon#*before return 0, iclass 26, count 0 2006.173.06:41:12.27#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.06:41:12.27#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.06:41:12.27#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.06:41:12.27#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.06:41:12.27$vck44/vb=5,4 2006.173.06:41:12.27#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.06:41:12.27#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.06:41:12.27#ibcon#ireg 11 cls_cnt 2 2006.173.06:41:12.27#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.06:41:12.33#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.06:41:12.33#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.06:41:12.33#ibcon#enter wrdev, iclass 28, count 2 2006.173.06:41:12.33#ibcon#first serial, iclass 28, count 2 2006.173.06:41:12.33#ibcon#enter sib2, iclass 28, count 2 2006.173.06:41:12.33#ibcon#flushed, iclass 28, count 2 2006.173.06:41:12.33#ibcon#about to write, iclass 28, count 2 2006.173.06:41:12.33#ibcon#wrote, iclass 28, count 2 2006.173.06:41:12.33#ibcon#about to read 3, iclass 28, count 2 2006.173.06:41:12.35#ibcon#read 3, iclass 28, count 2 2006.173.06:41:12.35#ibcon#about to read 4, iclass 28, count 2 2006.173.06:41:12.35#ibcon#read 4, iclass 28, count 2 2006.173.06:41:12.35#ibcon#about to read 5, iclass 28, count 2 2006.173.06:41:12.35#ibcon#read 5, iclass 28, count 2 2006.173.06:41:12.35#ibcon#about to read 6, iclass 28, count 2 2006.173.06:41:12.35#ibcon#read 6, iclass 28, count 2 2006.173.06:41:12.35#ibcon#end of sib2, iclass 28, count 2 2006.173.06:41:12.35#ibcon#*mode == 0, iclass 28, count 2 2006.173.06:41:12.35#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.06:41:12.35#ibcon#[27=AT05-04\r\n] 2006.173.06:41:12.35#ibcon#*before write, iclass 28, count 2 2006.173.06:41:12.35#ibcon#enter sib2, iclass 28, count 2 2006.173.06:41:12.35#ibcon#flushed, iclass 28, count 2 2006.173.06:41:12.35#ibcon#about to write, iclass 28, count 2 2006.173.06:41:12.35#ibcon#wrote, iclass 28, count 2 2006.173.06:41:12.35#ibcon#about to read 3, iclass 28, count 2 2006.173.06:41:12.38#ibcon#read 3, iclass 28, count 2 2006.173.06:41:12.38#ibcon#about to read 4, iclass 28, count 2 2006.173.06:41:12.38#ibcon#read 4, iclass 28, count 2 2006.173.06:41:12.38#ibcon#about to read 5, iclass 28, count 2 2006.173.06:41:12.38#ibcon#read 5, iclass 28, count 2 2006.173.06:41:12.38#ibcon#about to read 6, iclass 28, count 2 2006.173.06:41:12.38#ibcon#read 6, iclass 28, count 2 2006.173.06:41:12.38#ibcon#end of sib2, iclass 28, count 2 2006.173.06:41:12.38#ibcon#*after write, iclass 28, count 2 2006.173.06:41:12.38#ibcon#*before return 0, iclass 28, count 2 2006.173.06:41:12.38#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.06:41:12.38#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.06:41:12.38#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.06:41:12.38#ibcon#ireg 7 cls_cnt 0 2006.173.06:41:12.38#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.06:41:12.50#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.06:41:12.50#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.06:41:12.50#ibcon#enter wrdev, iclass 28, count 0 2006.173.06:41:12.50#ibcon#first serial, iclass 28, count 0 2006.173.06:41:12.50#ibcon#enter sib2, iclass 28, count 0 2006.173.06:41:12.50#ibcon#flushed, iclass 28, count 0 2006.173.06:41:12.50#ibcon#about to write, iclass 28, count 0 2006.173.06:41:12.50#ibcon#wrote, iclass 28, count 0 2006.173.06:41:12.50#ibcon#about to read 3, iclass 28, count 0 2006.173.06:41:12.52#ibcon#read 3, iclass 28, count 0 2006.173.06:41:12.52#ibcon#about to read 4, iclass 28, count 0 2006.173.06:41:12.52#ibcon#read 4, iclass 28, count 0 2006.173.06:41:12.52#ibcon#about to read 5, iclass 28, count 0 2006.173.06:41:12.52#ibcon#read 5, iclass 28, count 0 2006.173.06:41:12.52#ibcon#about to read 6, iclass 28, count 0 2006.173.06:41:12.52#ibcon#read 6, iclass 28, count 0 2006.173.06:41:12.52#ibcon#end of sib2, iclass 28, count 0 2006.173.06:41:12.52#ibcon#*mode == 0, iclass 28, count 0 2006.173.06:41:12.52#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.06:41:12.52#ibcon#[27=USB\r\n] 2006.173.06:41:12.52#ibcon#*before write, iclass 28, count 0 2006.173.06:41:12.52#ibcon#enter sib2, iclass 28, count 0 2006.173.06:41:12.52#ibcon#flushed, iclass 28, count 0 2006.173.06:41:12.52#ibcon#about to write, iclass 28, count 0 2006.173.06:41:12.52#ibcon#wrote, iclass 28, count 0 2006.173.06:41:12.52#ibcon#about to read 3, iclass 28, count 0 2006.173.06:41:12.55#ibcon#read 3, iclass 28, count 0 2006.173.06:41:12.55#ibcon#about to read 4, iclass 28, count 0 2006.173.06:41:12.55#ibcon#read 4, iclass 28, count 0 2006.173.06:41:12.55#ibcon#about to read 5, iclass 28, count 0 2006.173.06:41:12.55#ibcon#read 5, iclass 28, count 0 2006.173.06:41:12.55#ibcon#about to read 6, iclass 28, count 0 2006.173.06:41:12.55#ibcon#read 6, iclass 28, count 0 2006.173.06:41:12.55#ibcon#end of sib2, iclass 28, count 0 2006.173.06:41:12.55#ibcon#*after write, iclass 28, count 0 2006.173.06:41:12.55#ibcon#*before return 0, iclass 28, count 0 2006.173.06:41:12.55#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.06:41:12.55#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.06:41:12.55#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.06:41:12.55#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.06:41:12.55$vck44/vblo=6,719.99 2006.173.06:41:12.55#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.06:41:12.55#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.06:41:12.55#ibcon#ireg 17 cls_cnt 0 2006.173.06:41:12.55#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.06:41:12.55#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.06:41:12.55#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.06:41:12.55#ibcon#enter wrdev, iclass 30, count 0 2006.173.06:41:12.55#ibcon#first serial, iclass 30, count 0 2006.173.06:41:12.55#ibcon#enter sib2, iclass 30, count 0 2006.173.06:41:12.55#ibcon#flushed, iclass 30, count 0 2006.173.06:41:12.55#ibcon#about to write, iclass 30, count 0 2006.173.06:41:12.55#ibcon#wrote, iclass 30, count 0 2006.173.06:41:12.55#ibcon#about to read 3, iclass 30, count 0 2006.173.06:41:12.57#ibcon#read 3, iclass 30, count 0 2006.173.06:41:12.57#ibcon#about to read 4, iclass 30, count 0 2006.173.06:41:12.57#ibcon#read 4, iclass 30, count 0 2006.173.06:41:12.57#ibcon#about to read 5, iclass 30, count 0 2006.173.06:41:12.57#ibcon#read 5, iclass 30, count 0 2006.173.06:41:12.57#ibcon#about to read 6, iclass 30, count 0 2006.173.06:41:12.57#ibcon#read 6, iclass 30, count 0 2006.173.06:41:12.57#ibcon#end of sib2, iclass 30, count 0 2006.173.06:41:12.57#ibcon#*mode == 0, iclass 30, count 0 2006.173.06:41:12.57#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.06:41:12.57#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.06:41:12.57#ibcon#*before write, iclass 30, count 0 2006.173.06:41:12.57#ibcon#enter sib2, iclass 30, count 0 2006.173.06:41:12.57#ibcon#flushed, iclass 30, count 0 2006.173.06:41:12.57#ibcon#about to write, iclass 30, count 0 2006.173.06:41:12.57#ibcon#wrote, iclass 30, count 0 2006.173.06:41:12.57#ibcon#about to read 3, iclass 30, count 0 2006.173.06:41:12.61#ibcon#read 3, iclass 30, count 0 2006.173.06:41:12.61#ibcon#about to read 4, iclass 30, count 0 2006.173.06:41:12.61#ibcon#read 4, iclass 30, count 0 2006.173.06:41:12.61#ibcon#about to read 5, iclass 30, count 0 2006.173.06:41:12.61#ibcon#read 5, iclass 30, count 0 2006.173.06:41:12.61#ibcon#about to read 6, iclass 30, count 0 2006.173.06:41:12.61#ibcon#read 6, iclass 30, count 0 2006.173.06:41:12.61#ibcon#end of sib2, iclass 30, count 0 2006.173.06:41:12.61#ibcon#*after write, iclass 30, count 0 2006.173.06:41:12.61#ibcon#*before return 0, iclass 30, count 0 2006.173.06:41:12.61#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.06:41:12.61#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.06:41:12.61#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.06:41:12.61#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.06:41:12.61$vck44/vb=6,4 2006.173.06:41:12.61#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.173.06:41:12.61#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.173.06:41:12.61#ibcon#ireg 11 cls_cnt 2 2006.173.06:41:12.61#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.06:41:12.67#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.06:41:12.67#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.06:41:12.67#ibcon#enter wrdev, iclass 32, count 2 2006.173.06:41:12.67#ibcon#first serial, iclass 32, count 2 2006.173.06:41:12.67#ibcon#enter sib2, iclass 32, count 2 2006.173.06:41:12.67#ibcon#flushed, iclass 32, count 2 2006.173.06:41:12.67#ibcon#about to write, iclass 32, count 2 2006.173.06:41:12.67#ibcon#wrote, iclass 32, count 2 2006.173.06:41:12.67#ibcon#about to read 3, iclass 32, count 2 2006.173.06:41:12.69#ibcon#read 3, iclass 32, count 2 2006.173.06:41:12.69#ibcon#about to read 4, iclass 32, count 2 2006.173.06:41:12.69#ibcon#read 4, iclass 32, count 2 2006.173.06:41:12.69#ibcon#about to read 5, iclass 32, count 2 2006.173.06:41:12.69#ibcon#read 5, iclass 32, count 2 2006.173.06:41:12.69#ibcon#about to read 6, iclass 32, count 2 2006.173.06:41:12.69#ibcon#read 6, iclass 32, count 2 2006.173.06:41:12.69#ibcon#end of sib2, iclass 32, count 2 2006.173.06:41:12.69#ibcon#*mode == 0, iclass 32, count 2 2006.173.06:41:12.69#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.173.06:41:12.69#ibcon#[27=AT06-04\r\n] 2006.173.06:41:12.69#ibcon#*before write, iclass 32, count 2 2006.173.06:41:12.69#ibcon#enter sib2, iclass 32, count 2 2006.173.06:41:12.69#ibcon#flushed, iclass 32, count 2 2006.173.06:41:12.69#ibcon#about to write, iclass 32, count 2 2006.173.06:41:12.69#ibcon#wrote, iclass 32, count 2 2006.173.06:41:12.69#ibcon#about to read 3, iclass 32, count 2 2006.173.06:41:12.72#ibcon#read 3, iclass 32, count 2 2006.173.06:41:12.72#ibcon#about to read 4, iclass 32, count 2 2006.173.06:41:12.72#ibcon#read 4, iclass 32, count 2 2006.173.06:41:12.72#ibcon#about to read 5, iclass 32, count 2 2006.173.06:41:12.72#ibcon#read 5, iclass 32, count 2 2006.173.06:41:12.72#ibcon#about to read 6, iclass 32, count 2 2006.173.06:41:12.72#ibcon#read 6, iclass 32, count 2 2006.173.06:41:12.72#ibcon#end of sib2, iclass 32, count 2 2006.173.06:41:12.72#ibcon#*after write, iclass 32, count 2 2006.173.06:41:12.72#ibcon#*before return 0, iclass 32, count 2 2006.173.06:41:12.72#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.06:41:12.72#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.173.06:41:12.72#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.173.06:41:12.72#ibcon#ireg 7 cls_cnt 0 2006.173.06:41:12.72#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.06:41:12.84#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.06:41:12.84#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.06:41:12.84#ibcon#enter wrdev, iclass 32, count 0 2006.173.06:41:12.84#ibcon#first serial, iclass 32, count 0 2006.173.06:41:12.84#ibcon#enter sib2, iclass 32, count 0 2006.173.06:41:12.84#ibcon#flushed, iclass 32, count 0 2006.173.06:41:12.84#ibcon#about to write, iclass 32, count 0 2006.173.06:41:12.84#ibcon#wrote, iclass 32, count 0 2006.173.06:41:12.84#ibcon#about to read 3, iclass 32, count 0 2006.173.06:41:12.86#ibcon#read 3, iclass 32, count 0 2006.173.06:41:12.86#ibcon#about to read 4, iclass 32, count 0 2006.173.06:41:12.86#ibcon#read 4, iclass 32, count 0 2006.173.06:41:12.86#ibcon#about to read 5, iclass 32, count 0 2006.173.06:41:12.86#ibcon#read 5, iclass 32, count 0 2006.173.06:41:12.86#ibcon#about to read 6, iclass 32, count 0 2006.173.06:41:12.86#ibcon#read 6, iclass 32, count 0 2006.173.06:41:12.86#ibcon#end of sib2, iclass 32, count 0 2006.173.06:41:12.86#ibcon#*mode == 0, iclass 32, count 0 2006.173.06:41:12.86#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.06:41:12.86#ibcon#[27=USB\r\n] 2006.173.06:41:12.86#ibcon#*before write, iclass 32, count 0 2006.173.06:41:12.86#ibcon#enter sib2, iclass 32, count 0 2006.173.06:41:12.86#ibcon#flushed, iclass 32, count 0 2006.173.06:41:12.86#ibcon#about to write, iclass 32, count 0 2006.173.06:41:12.86#ibcon#wrote, iclass 32, count 0 2006.173.06:41:12.86#ibcon#about to read 3, iclass 32, count 0 2006.173.06:41:12.89#ibcon#read 3, iclass 32, count 0 2006.173.06:41:12.89#ibcon#about to read 4, iclass 32, count 0 2006.173.06:41:12.89#ibcon#read 4, iclass 32, count 0 2006.173.06:41:12.89#ibcon#about to read 5, iclass 32, count 0 2006.173.06:41:12.89#ibcon#read 5, iclass 32, count 0 2006.173.06:41:12.89#ibcon#about to read 6, iclass 32, count 0 2006.173.06:41:12.89#ibcon#read 6, iclass 32, count 0 2006.173.06:41:12.89#ibcon#end of sib2, iclass 32, count 0 2006.173.06:41:12.89#ibcon#*after write, iclass 32, count 0 2006.173.06:41:12.89#ibcon#*before return 0, iclass 32, count 0 2006.173.06:41:12.89#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.06:41:12.89#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.173.06:41:12.89#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.06:41:12.89#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.06:41:12.89$vck44/vblo=7,734.99 2006.173.06:41:12.89#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.06:41:12.89#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.06:41:12.89#ibcon#ireg 17 cls_cnt 0 2006.173.06:41:12.89#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.06:41:12.89#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.06:41:12.89#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.06:41:12.89#ibcon#enter wrdev, iclass 34, count 0 2006.173.06:41:12.89#ibcon#first serial, iclass 34, count 0 2006.173.06:41:12.89#ibcon#enter sib2, iclass 34, count 0 2006.173.06:41:12.89#ibcon#flushed, iclass 34, count 0 2006.173.06:41:12.89#ibcon#about to write, iclass 34, count 0 2006.173.06:41:12.89#ibcon#wrote, iclass 34, count 0 2006.173.06:41:12.89#ibcon#about to read 3, iclass 34, count 0 2006.173.06:41:12.91#ibcon#read 3, iclass 34, count 0 2006.173.06:41:12.91#ibcon#about to read 4, iclass 34, count 0 2006.173.06:41:12.91#ibcon#read 4, iclass 34, count 0 2006.173.06:41:12.91#ibcon#about to read 5, iclass 34, count 0 2006.173.06:41:12.91#ibcon#read 5, iclass 34, count 0 2006.173.06:41:12.91#ibcon#about to read 6, iclass 34, count 0 2006.173.06:41:12.91#ibcon#read 6, iclass 34, count 0 2006.173.06:41:12.91#ibcon#end of sib2, iclass 34, count 0 2006.173.06:41:12.91#ibcon#*mode == 0, iclass 34, count 0 2006.173.06:41:12.91#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.06:41:12.91#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.06:41:12.91#ibcon#*before write, iclass 34, count 0 2006.173.06:41:12.91#ibcon#enter sib2, iclass 34, count 0 2006.173.06:41:12.91#ibcon#flushed, iclass 34, count 0 2006.173.06:41:12.91#ibcon#about to write, iclass 34, count 0 2006.173.06:41:12.91#ibcon#wrote, iclass 34, count 0 2006.173.06:41:12.91#ibcon#about to read 3, iclass 34, count 0 2006.173.06:41:12.95#ibcon#read 3, iclass 34, count 0 2006.173.06:41:12.95#ibcon#about to read 4, iclass 34, count 0 2006.173.06:41:12.95#ibcon#read 4, iclass 34, count 0 2006.173.06:41:12.95#ibcon#about to read 5, iclass 34, count 0 2006.173.06:41:12.95#ibcon#read 5, iclass 34, count 0 2006.173.06:41:12.95#ibcon#about to read 6, iclass 34, count 0 2006.173.06:41:12.95#ibcon#read 6, iclass 34, count 0 2006.173.06:41:12.95#ibcon#end of sib2, iclass 34, count 0 2006.173.06:41:12.95#ibcon#*after write, iclass 34, count 0 2006.173.06:41:12.95#ibcon#*before return 0, iclass 34, count 0 2006.173.06:41:12.95#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.06:41:12.95#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.06:41:12.95#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.06:41:12.95#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.06:41:12.95$vck44/vb=7,4 2006.173.06:41:12.95#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.06:41:12.95#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.06:41:12.95#ibcon#ireg 11 cls_cnt 2 2006.173.06:41:12.95#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.06:41:13.01#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.06:41:13.01#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.06:41:13.01#ibcon#enter wrdev, iclass 36, count 2 2006.173.06:41:13.01#ibcon#first serial, iclass 36, count 2 2006.173.06:41:13.01#ibcon#enter sib2, iclass 36, count 2 2006.173.06:41:13.01#ibcon#flushed, iclass 36, count 2 2006.173.06:41:13.01#ibcon#about to write, iclass 36, count 2 2006.173.06:41:13.01#ibcon#wrote, iclass 36, count 2 2006.173.06:41:13.01#ibcon#about to read 3, iclass 36, count 2 2006.173.06:41:13.03#ibcon#read 3, iclass 36, count 2 2006.173.06:41:13.03#ibcon#about to read 4, iclass 36, count 2 2006.173.06:41:13.03#ibcon#read 4, iclass 36, count 2 2006.173.06:41:13.03#ibcon#about to read 5, iclass 36, count 2 2006.173.06:41:13.03#ibcon#read 5, iclass 36, count 2 2006.173.06:41:13.03#ibcon#about to read 6, iclass 36, count 2 2006.173.06:41:13.03#ibcon#read 6, iclass 36, count 2 2006.173.06:41:13.03#ibcon#end of sib2, iclass 36, count 2 2006.173.06:41:13.03#ibcon#*mode == 0, iclass 36, count 2 2006.173.06:41:13.03#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.06:41:13.03#ibcon#[27=AT07-04\r\n] 2006.173.06:41:13.03#ibcon#*before write, iclass 36, count 2 2006.173.06:41:13.03#ibcon#enter sib2, iclass 36, count 2 2006.173.06:41:13.03#ibcon#flushed, iclass 36, count 2 2006.173.06:41:13.03#ibcon#about to write, iclass 36, count 2 2006.173.06:41:13.03#ibcon#wrote, iclass 36, count 2 2006.173.06:41:13.03#ibcon#about to read 3, iclass 36, count 2 2006.173.06:41:13.06#ibcon#read 3, iclass 36, count 2 2006.173.06:41:13.06#ibcon#about to read 4, iclass 36, count 2 2006.173.06:41:13.06#ibcon#read 4, iclass 36, count 2 2006.173.06:41:13.06#ibcon#about to read 5, iclass 36, count 2 2006.173.06:41:13.06#ibcon#read 5, iclass 36, count 2 2006.173.06:41:13.06#ibcon#about to read 6, iclass 36, count 2 2006.173.06:41:13.06#ibcon#read 6, iclass 36, count 2 2006.173.06:41:13.06#ibcon#end of sib2, iclass 36, count 2 2006.173.06:41:13.06#ibcon#*after write, iclass 36, count 2 2006.173.06:41:13.06#ibcon#*before return 0, iclass 36, count 2 2006.173.06:41:13.06#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.06:41:13.06#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.06:41:13.06#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.06:41:13.06#ibcon#ireg 7 cls_cnt 0 2006.173.06:41:13.06#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.06:41:13.18#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.06:41:13.18#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.06:41:13.18#ibcon#enter wrdev, iclass 36, count 0 2006.173.06:41:13.18#ibcon#first serial, iclass 36, count 0 2006.173.06:41:13.18#ibcon#enter sib2, iclass 36, count 0 2006.173.06:41:13.18#ibcon#flushed, iclass 36, count 0 2006.173.06:41:13.18#ibcon#about to write, iclass 36, count 0 2006.173.06:41:13.18#ibcon#wrote, iclass 36, count 0 2006.173.06:41:13.18#ibcon#about to read 3, iclass 36, count 0 2006.173.06:41:13.20#ibcon#read 3, iclass 36, count 0 2006.173.06:41:13.20#ibcon#about to read 4, iclass 36, count 0 2006.173.06:41:13.20#ibcon#read 4, iclass 36, count 0 2006.173.06:41:13.20#ibcon#about to read 5, iclass 36, count 0 2006.173.06:41:13.20#ibcon#read 5, iclass 36, count 0 2006.173.06:41:13.20#ibcon#about to read 6, iclass 36, count 0 2006.173.06:41:13.20#ibcon#read 6, iclass 36, count 0 2006.173.06:41:13.20#ibcon#end of sib2, iclass 36, count 0 2006.173.06:41:13.20#ibcon#*mode == 0, iclass 36, count 0 2006.173.06:41:13.20#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.06:41:13.20#ibcon#[27=USB\r\n] 2006.173.06:41:13.20#ibcon#*before write, iclass 36, count 0 2006.173.06:41:13.20#ibcon#enter sib2, iclass 36, count 0 2006.173.06:41:13.20#ibcon#flushed, iclass 36, count 0 2006.173.06:41:13.20#ibcon#about to write, iclass 36, count 0 2006.173.06:41:13.20#ibcon#wrote, iclass 36, count 0 2006.173.06:41:13.20#ibcon#about to read 3, iclass 36, count 0 2006.173.06:41:13.23#ibcon#read 3, iclass 36, count 0 2006.173.06:41:13.23#ibcon#about to read 4, iclass 36, count 0 2006.173.06:41:13.23#ibcon#read 4, iclass 36, count 0 2006.173.06:41:13.23#ibcon#about to read 5, iclass 36, count 0 2006.173.06:41:13.23#ibcon#read 5, iclass 36, count 0 2006.173.06:41:13.23#ibcon#about to read 6, iclass 36, count 0 2006.173.06:41:13.23#ibcon#read 6, iclass 36, count 0 2006.173.06:41:13.23#ibcon#end of sib2, iclass 36, count 0 2006.173.06:41:13.23#ibcon#*after write, iclass 36, count 0 2006.173.06:41:13.23#ibcon#*before return 0, iclass 36, count 0 2006.173.06:41:13.23#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.06:41:13.23#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.06:41:13.23#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.06:41:13.23#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.06:41:13.23$vck44/vblo=8,744.99 2006.173.06:41:13.23#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.06:41:13.23#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.06:41:13.23#ibcon#ireg 17 cls_cnt 0 2006.173.06:41:13.23#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.06:41:13.23#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.06:41:13.23#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.06:41:13.23#ibcon#enter wrdev, iclass 38, count 0 2006.173.06:41:13.23#ibcon#first serial, iclass 38, count 0 2006.173.06:41:13.23#ibcon#enter sib2, iclass 38, count 0 2006.173.06:41:13.23#ibcon#flushed, iclass 38, count 0 2006.173.06:41:13.23#ibcon#about to write, iclass 38, count 0 2006.173.06:41:13.23#ibcon#wrote, iclass 38, count 0 2006.173.06:41:13.23#ibcon#about to read 3, iclass 38, count 0 2006.173.06:41:13.25#ibcon#read 3, iclass 38, count 0 2006.173.06:41:13.25#ibcon#about to read 4, iclass 38, count 0 2006.173.06:41:13.25#ibcon#read 4, iclass 38, count 0 2006.173.06:41:13.25#ibcon#about to read 5, iclass 38, count 0 2006.173.06:41:13.25#ibcon#read 5, iclass 38, count 0 2006.173.06:41:13.25#ibcon#about to read 6, iclass 38, count 0 2006.173.06:41:13.25#ibcon#read 6, iclass 38, count 0 2006.173.06:41:13.25#ibcon#end of sib2, iclass 38, count 0 2006.173.06:41:13.25#ibcon#*mode == 0, iclass 38, count 0 2006.173.06:41:13.25#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.06:41:13.25#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.06:41:13.25#ibcon#*before write, iclass 38, count 0 2006.173.06:41:13.25#ibcon#enter sib2, iclass 38, count 0 2006.173.06:41:13.25#ibcon#flushed, iclass 38, count 0 2006.173.06:41:13.25#ibcon#about to write, iclass 38, count 0 2006.173.06:41:13.25#ibcon#wrote, iclass 38, count 0 2006.173.06:41:13.25#ibcon#about to read 3, iclass 38, count 0 2006.173.06:41:13.29#ibcon#read 3, iclass 38, count 0 2006.173.06:41:13.29#ibcon#about to read 4, iclass 38, count 0 2006.173.06:41:13.29#ibcon#read 4, iclass 38, count 0 2006.173.06:41:13.29#ibcon#about to read 5, iclass 38, count 0 2006.173.06:41:13.29#ibcon#read 5, iclass 38, count 0 2006.173.06:41:13.29#ibcon#about to read 6, iclass 38, count 0 2006.173.06:41:13.29#ibcon#read 6, iclass 38, count 0 2006.173.06:41:13.29#ibcon#end of sib2, iclass 38, count 0 2006.173.06:41:13.29#ibcon#*after write, iclass 38, count 0 2006.173.06:41:13.29#ibcon#*before return 0, iclass 38, count 0 2006.173.06:41:13.29#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.06:41:13.29#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.06:41:13.29#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.06:41:13.29#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.06:41:13.29$vck44/vb=8,4 2006.173.06:41:13.29#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.06:41:13.29#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.06:41:13.29#ibcon#ireg 11 cls_cnt 2 2006.173.06:41:13.29#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.06:41:13.35#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.06:41:13.35#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.06:41:13.35#ibcon#enter wrdev, iclass 40, count 2 2006.173.06:41:13.35#ibcon#first serial, iclass 40, count 2 2006.173.06:41:13.35#ibcon#enter sib2, iclass 40, count 2 2006.173.06:41:13.35#ibcon#flushed, iclass 40, count 2 2006.173.06:41:13.35#ibcon#about to write, iclass 40, count 2 2006.173.06:41:13.35#ibcon#wrote, iclass 40, count 2 2006.173.06:41:13.35#ibcon#about to read 3, iclass 40, count 2 2006.173.06:41:13.37#ibcon#read 3, iclass 40, count 2 2006.173.06:41:13.37#ibcon#about to read 4, iclass 40, count 2 2006.173.06:41:13.37#ibcon#read 4, iclass 40, count 2 2006.173.06:41:13.37#ibcon#about to read 5, iclass 40, count 2 2006.173.06:41:13.37#ibcon#read 5, iclass 40, count 2 2006.173.06:41:13.37#ibcon#about to read 6, iclass 40, count 2 2006.173.06:41:13.37#ibcon#read 6, iclass 40, count 2 2006.173.06:41:13.37#ibcon#end of sib2, iclass 40, count 2 2006.173.06:41:13.37#ibcon#*mode == 0, iclass 40, count 2 2006.173.06:41:13.37#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.06:41:13.37#ibcon#[27=AT08-04\r\n] 2006.173.06:41:13.37#ibcon#*before write, iclass 40, count 2 2006.173.06:41:13.37#ibcon#enter sib2, iclass 40, count 2 2006.173.06:41:13.37#ibcon#flushed, iclass 40, count 2 2006.173.06:41:13.37#ibcon#about to write, iclass 40, count 2 2006.173.06:41:13.37#ibcon#wrote, iclass 40, count 2 2006.173.06:41:13.37#ibcon#about to read 3, iclass 40, count 2 2006.173.06:41:13.40#ibcon#read 3, iclass 40, count 2 2006.173.06:41:13.40#ibcon#about to read 4, iclass 40, count 2 2006.173.06:41:13.40#ibcon#read 4, iclass 40, count 2 2006.173.06:41:13.40#ibcon#about to read 5, iclass 40, count 2 2006.173.06:41:13.40#ibcon#read 5, iclass 40, count 2 2006.173.06:41:13.40#ibcon#about to read 6, iclass 40, count 2 2006.173.06:41:13.40#ibcon#read 6, iclass 40, count 2 2006.173.06:41:13.40#ibcon#end of sib2, iclass 40, count 2 2006.173.06:41:13.40#ibcon#*after write, iclass 40, count 2 2006.173.06:41:13.40#ibcon#*before return 0, iclass 40, count 2 2006.173.06:41:13.40#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.06:41:13.40#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.06:41:13.40#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.06:41:13.40#ibcon#ireg 7 cls_cnt 0 2006.173.06:41:13.40#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.06:41:13.52#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.06:41:13.52#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.06:41:13.52#ibcon#enter wrdev, iclass 40, count 0 2006.173.06:41:13.52#ibcon#first serial, iclass 40, count 0 2006.173.06:41:13.52#ibcon#enter sib2, iclass 40, count 0 2006.173.06:41:13.52#ibcon#flushed, iclass 40, count 0 2006.173.06:41:13.52#ibcon#about to write, iclass 40, count 0 2006.173.06:41:13.52#ibcon#wrote, iclass 40, count 0 2006.173.06:41:13.52#ibcon#about to read 3, iclass 40, count 0 2006.173.06:41:13.54#ibcon#read 3, iclass 40, count 0 2006.173.06:41:13.54#ibcon#about to read 4, iclass 40, count 0 2006.173.06:41:13.54#ibcon#read 4, iclass 40, count 0 2006.173.06:41:13.54#ibcon#about to read 5, iclass 40, count 0 2006.173.06:41:13.54#ibcon#read 5, iclass 40, count 0 2006.173.06:41:13.54#ibcon#about to read 6, iclass 40, count 0 2006.173.06:41:13.54#ibcon#read 6, iclass 40, count 0 2006.173.06:41:13.54#ibcon#end of sib2, iclass 40, count 0 2006.173.06:41:13.54#ibcon#*mode == 0, iclass 40, count 0 2006.173.06:41:13.54#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.06:41:13.54#ibcon#[27=USB\r\n] 2006.173.06:41:13.54#ibcon#*before write, iclass 40, count 0 2006.173.06:41:13.54#ibcon#enter sib2, iclass 40, count 0 2006.173.06:41:13.54#ibcon#flushed, iclass 40, count 0 2006.173.06:41:13.54#ibcon#about to write, iclass 40, count 0 2006.173.06:41:13.54#ibcon#wrote, iclass 40, count 0 2006.173.06:41:13.54#ibcon#about to read 3, iclass 40, count 0 2006.173.06:41:13.57#ibcon#read 3, iclass 40, count 0 2006.173.06:41:13.57#ibcon#about to read 4, iclass 40, count 0 2006.173.06:41:13.57#ibcon#read 4, iclass 40, count 0 2006.173.06:41:13.57#ibcon#about to read 5, iclass 40, count 0 2006.173.06:41:13.57#ibcon#read 5, iclass 40, count 0 2006.173.06:41:13.57#ibcon#about to read 6, iclass 40, count 0 2006.173.06:41:13.57#ibcon#read 6, iclass 40, count 0 2006.173.06:41:13.57#ibcon#end of sib2, iclass 40, count 0 2006.173.06:41:13.57#ibcon#*after write, iclass 40, count 0 2006.173.06:41:13.57#ibcon#*before return 0, iclass 40, count 0 2006.173.06:41:13.57#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.06:41:13.57#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.06:41:13.57#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.06:41:13.57#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.06:41:13.57$vck44/vabw=wide 2006.173.06:41:13.57#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.06:41:13.57#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.06:41:13.57#ibcon#ireg 8 cls_cnt 0 2006.173.06:41:13.57#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.06:41:13.57#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.06:41:13.57#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.06:41:13.57#ibcon#enter wrdev, iclass 4, count 0 2006.173.06:41:13.57#ibcon#first serial, iclass 4, count 0 2006.173.06:41:13.57#ibcon#enter sib2, iclass 4, count 0 2006.173.06:41:13.57#ibcon#flushed, iclass 4, count 0 2006.173.06:41:13.57#ibcon#about to write, iclass 4, count 0 2006.173.06:41:13.57#ibcon#wrote, iclass 4, count 0 2006.173.06:41:13.57#ibcon#about to read 3, iclass 4, count 0 2006.173.06:41:13.59#ibcon#read 3, iclass 4, count 0 2006.173.06:41:13.59#ibcon#about to read 4, iclass 4, count 0 2006.173.06:41:13.59#ibcon#read 4, iclass 4, count 0 2006.173.06:41:13.59#ibcon#about to read 5, iclass 4, count 0 2006.173.06:41:13.59#ibcon#read 5, iclass 4, count 0 2006.173.06:41:13.59#ibcon#about to read 6, iclass 4, count 0 2006.173.06:41:13.59#ibcon#read 6, iclass 4, count 0 2006.173.06:41:13.59#ibcon#end of sib2, iclass 4, count 0 2006.173.06:41:13.59#ibcon#*mode == 0, iclass 4, count 0 2006.173.06:41:13.59#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.06:41:13.59#ibcon#[25=BW32\r\n] 2006.173.06:41:13.59#ibcon#*before write, iclass 4, count 0 2006.173.06:41:13.59#ibcon#enter sib2, iclass 4, count 0 2006.173.06:41:13.59#ibcon#flushed, iclass 4, count 0 2006.173.06:41:13.59#ibcon#about to write, iclass 4, count 0 2006.173.06:41:13.59#ibcon#wrote, iclass 4, count 0 2006.173.06:41:13.59#ibcon#about to read 3, iclass 4, count 0 2006.173.06:41:13.62#ibcon#read 3, iclass 4, count 0 2006.173.06:41:13.62#ibcon#about to read 4, iclass 4, count 0 2006.173.06:41:13.62#ibcon#read 4, iclass 4, count 0 2006.173.06:41:13.62#ibcon#about to read 5, iclass 4, count 0 2006.173.06:41:13.62#ibcon#read 5, iclass 4, count 0 2006.173.06:41:13.62#ibcon#about to read 6, iclass 4, count 0 2006.173.06:41:13.62#ibcon#read 6, iclass 4, count 0 2006.173.06:41:13.62#ibcon#end of sib2, iclass 4, count 0 2006.173.06:41:13.62#ibcon#*after write, iclass 4, count 0 2006.173.06:41:13.62#ibcon#*before return 0, iclass 4, count 0 2006.173.06:41:13.62#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.06:41:13.62#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.06:41:13.62#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.06:41:13.62#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.06:41:13.62$vck44/vbbw=wide 2006.173.06:41:13.62#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.06:41:13.62#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.06:41:13.62#ibcon#ireg 8 cls_cnt 0 2006.173.06:41:13.62#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.06:41:13.69#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.06:41:13.69#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.06:41:13.69#ibcon#enter wrdev, iclass 6, count 0 2006.173.06:41:13.69#ibcon#first serial, iclass 6, count 0 2006.173.06:41:13.69#ibcon#enter sib2, iclass 6, count 0 2006.173.06:41:13.69#ibcon#flushed, iclass 6, count 0 2006.173.06:41:13.69#ibcon#about to write, iclass 6, count 0 2006.173.06:41:13.69#ibcon#wrote, iclass 6, count 0 2006.173.06:41:13.69#ibcon#about to read 3, iclass 6, count 0 2006.173.06:41:13.71#ibcon#read 3, iclass 6, count 0 2006.173.06:41:13.71#ibcon#about to read 4, iclass 6, count 0 2006.173.06:41:13.71#ibcon#read 4, iclass 6, count 0 2006.173.06:41:13.71#ibcon#about to read 5, iclass 6, count 0 2006.173.06:41:13.71#ibcon#read 5, iclass 6, count 0 2006.173.06:41:13.71#ibcon#about to read 6, iclass 6, count 0 2006.173.06:41:13.71#ibcon#read 6, iclass 6, count 0 2006.173.06:41:13.71#ibcon#end of sib2, iclass 6, count 0 2006.173.06:41:13.71#ibcon#*mode == 0, iclass 6, count 0 2006.173.06:41:13.71#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.06:41:13.71#ibcon#[27=BW32\r\n] 2006.173.06:41:13.71#ibcon#*before write, iclass 6, count 0 2006.173.06:41:13.71#ibcon#enter sib2, iclass 6, count 0 2006.173.06:41:13.71#ibcon#flushed, iclass 6, count 0 2006.173.06:41:13.71#ibcon#about to write, iclass 6, count 0 2006.173.06:41:13.71#ibcon#wrote, iclass 6, count 0 2006.173.06:41:13.71#ibcon#about to read 3, iclass 6, count 0 2006.173.06:41:13.74#ibcon#read 3, iclass 6, count 0 2006.173.06:41:13.74#ibcon#about to read 4, iclass 6, count 0 2006.173.06:41:13.74#ibcon#read 4, iclass 6, count 0 2006.173.06:41:13.74#ibcon#about to read 5, iclass 6, count 0 2006.173.06:41:13.74#ibcon#read 5, iclass 6, count 0 2006.173.06:41:13.74#ibcon#about to read 6, iclass 6, count 0 2006.173.06:41:13.74#ibcon#read 6, iclass 6, count 0 2006.173.06:41:13.74#ibcon#end of sib2, iclass 6, count 0 2006.173.06:41:13.74#ibcon#*after write, iclass 6, count 0 2006.173.06:41:13.74#ibcon#*before return 0, iclass 6, count 0 2006.173.06:41:13.74#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.06:41:13.74#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.06:41:13.74#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.06:41:13.74#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.06:41:13.74$setupk4/ifdk4 2006.173.06:41:13.74$ifdk4/lo= 2006.173.06:41:13.74$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.06:41:13.74$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.06:41:13.74$ifdk4/patch= 2006.173.06:41:13.74$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.06:41:13.74$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.06:41:13.74$setupk4/!*+20s 2006.173.06:41:19.35#abcon#<5=/15 0.5 1.0 23.73 801005.0\r\n> 2006.173.06:41:19.37#abcon#{5=INTERFACE CLEAR} 2006.173.06:41:19.43#abcon#[5=S1D000X0/0*\r\n] 2006.173.06:41:25.14#trakl#Source acquired 2006.173.06:41:25.14#flagr#flagr/antenna,acquired 2006.173.06:41:28.25$setupk4/"tpicd 2006.173.06:41:28.25$setupk4/echo=off 2006.173.06:41:28.25$setupk4/xlog=off 2006.173.06:41:28.25:!2006.173.06:42:44 2006.173.06:42:44.00:preob 2006.173.06:42:44.14/onsource/TRACKING 2006.173.06:42:44.14:!2006.173.06:42:54 2006.173.06:42:54.00:"tape 2006.173.06:42:54.00:"st=record 2006.173.06:42:54.00:data_valid=on 2006.173.06:42:54.00:midob 2006.173.06:42:55.14/onsource/TRACKING 2006.173.06:42:55.14/wx/23.72,1005.0,81 2006.173.06:42:55.32/cable/+6.5033E-03 2006.173.06:42:56.41/va/01,07,usb,yes,38,41 2006.173.06:42:56.41/va/02,06,usb,yes,38,38 2006.173.06:42:56.41/va/03,05,usb,yes,48,50 2006.173.06:42:56.41/va/04,06,usb,yes,38,40 2006.173.06:42:56.41/va/05,04,usb,yes,30,31 2006.173.06:42:56.41/va/06,03,usb,yes,42,42 2006.173.06:42:56.41/va/07,04,usb,yes,34,35 2006.173.06:42:56.41/va/08,04,usb,yes,29,35 2006.173.06:42:56.64/valo/01,524.99,yes,locked 2006.173.06:42:56.64/valo/02,534.99,yes,locked 2006.173.06:42:56.64/valo/03,564.99,yes,locked 2006.173.06:42:56.64/valo/04,624.99,yes,locked 2006.173.06:42:56.64/valo/05,734.99,yes,locked 2006.173.06:42:56.64/valo/06,814.99,yes,locked 2006.173.06:42:56.64/valo/07,864.99,yes,locked 2006.173.06:42:56.64/valo/08,884.99,yes,locked 2006.173.06:42:57.73/vb/01,04,usb,yes,36,33 2006.173.06:42:57.73/vb/02,04,usb,yes,38,38 2006.173.06:42:57.73/vb/03,04,usb,yes,35,39 2006.173.06:42:57.73/vb/04,04,usb,yes,40,39 2006.173.06:42:57.73/vb/05,04,usb,yes,31,34 2006.173.06:42:57.73/vb/06,04,usb,yes,37,32 2006.173.06:42:57.73/vb/07,04,usb,yes,36,36 2006.173.06:42:57.73/vb/08,04,usb,yes,33,37 2006.173.06:42:57.97/vblo/01,629.99,yes,locked 2006.173.06:42:57.97/vblo/02,634.99,yes,locked 2006.173.06:42:57.97/vblo/03,649.99,yes,locked 2006.173.06:42:57.97/vblo/04,679.99,yes,locked 2006.173.06:42:57.97/vblo/05,709.99,yes,locked 2006.173.06:42:57.97/vblo/06,719.99,yes,locked 2006.173.06:42:57.97/vblo/07,734.99,yes,locked 2006.173.06:42:57.97/vblo/08,744.99,yes,locked 2006.173.06:42:58.12/vabw/8 2006.173.06:42:58.27/vbbw/8 2006.173.06:42:58.36/xfe/off,on,14.7 2006.173.06:42:58.75/ifatt/23,28,28,28 2006.173.06:42:59.07/fmout-gps/S +4.02E-07 2006.173.06:42:59.11:!2006.173.06:44:24 2006.173.06:44:24.01:data_valid=off 2006.173.06:44:24.02:"et 2006.173.06:44:24.02:!+3s 2006.173.06:44:27.03:"tape 2006.173.06:44:27.04:postob 2006.173.06:44:27.15/cable/+6.5023E-03 2006.173.06:44:27.16/wx/23.71,1004.9,80 2006.173.06:44:27.21/fmout-gps/S +4.02E-07 2006.173.06:44:27.22:scan_name=173-0652,jd0606,440 2006.173.06:44:27.22:source=1418+546,141946.60,542314.8,2000.0,ccw 2006.173.06:44:28.14#flagr#flagr/antenna,new-source 2006.173.06:44:28.15:checkk5 2006.173.06:44:28.53/chk_autoobs//k5ts1/ autoobs is running! 2006.173.06:44:28.93/chk_autoobs//k5ts2/ autoobs is running! 2006.173.06:44:29.34/chk_autoobs//k5ts3/ autoobs is running! 2006.173.06:44:29.73/chk_autoobs//k5ts4/ autoobs is running! 2006.173.06:44:30.12/chk_obsdata//k5ts1/T1730642??a.dat file size is correct (nominal:360MB, actual:360MB). 2006.173.06:44:30.54/chk_obsdata//k5ts2/T1730642??b.dat file size is correct (nominal:360MB, actual:360MB). 2006.173.06:44:30.93/chk_obsdata//k5ts3/T1730642??c.dat file size is correct (nominal:360MB, actual:360MB). 2006.173.06:44:31.34/chk_obsdata//k5ts4/T1730642??d.dat file size is correct (nominal:360MB, actual:360MB). 2006.173.06:44:32.06/k5log//k5ts1_log_newline 2006.173.06:44:32.77/k5log//k5ts2_log_newline 2006.173.06:44:33.48/k5log//k5ts3_log_newline 2006.173.06:44:34.19/k5log//k5ts4_log_newline 2006.173.06:44:34.21/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.06:44:34.21:setupk4=1 2006.173.06:44:34.21$setupk4/echo=on 2006.173.06:44:34.21$setupk4/pcalon 2006.173.06:44:34.21$pcalon/"no phase cal control is implemented here 2006.173.06:44:34.21$setupk4/"tpicd=stop 2006.173.06:44:34.21$setupk4/"rec=synch_on 2006.173.06:44:34.21$setupk4/"rec_mode=128 2006.173.06:44:34.22$setupk4/!* 2006.173.06:44:34.22$setupk4/recpk4 2006.173.06:44:34.22$recpk4/recpatch= 2006.173.06:44:34.22$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.06:44:34.22$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.06:44:34.22$setupk4/vck44 2006.173.06:44:34.22$vck44/valo=1,524.99 2006.173.06:44:34.22#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.06:44:34.22#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.06:44:34.22#ibcon#ireg 17 cls_cnt 0 2006.173.06:44:34.22#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.06:44:34.22#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.06:44:34.22#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.06:44:34.22#ibcon#enter wrdev, iclass 21, count 0 2006.173.06:44:34.22#ibcon#first serial, iclass 21, count 0 2006.173.06:44:34.22#ibcon#enter sib2, iclass 21, count 0 2006.173.06:44:34.22#ibcon#flushed, iclass 21, count 0 2006.173.06:44:34.22#ibcon#about to write, iclass 21, count 0 2006.173.06:44:34.22#ibcon#wrote, iclass 21, count 0 2006.173.06:44:34.22#ibcon#about to read 3, iclass 21, count 0 2006.173.06:44:34.23#ibcon#read 3, iclass 21, count 0 2006.173.06:44:34.23#ibcon#about to read 4, iclass 21, count 0 2006.173.06:44:34.23#ibcon#read 4, iclass 21, count 0 2006.173.06:44:34.23#ibcon#about to read 5, iclass 21, count 0 2006.173.06:44:34.23#ibcon#read 5, iclass 21, count 0 2006.173.06:44:34.23#ibcon#about to read 6, iclass 21, count 0 2006.173.06:44:34.23#ibcon#read 6, iclass 21, count 0 2006.173.06:44:34.23#ibcon#end of sib2, iclass 21, count 0 2006.173.06:44:34.23#ibcon#*mode == 0, iclass 21, count 0 2006.173.06:44:34.23#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.06:44:34.23#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.06:44:34.23#ibcon#*before write, iclass 21, count 0 2006.173.06:44:34.23#ibcon#enter sib2, iclass 21, count 0 2006.173.06:44:34.23#ibcon#flushed, iclass 21, count 0 2006.173.06:44:34.23#ibcon#about to write, iclass 21, count 0 2006.173.06:44:34.23#ibcon#wrote, iclass 21, count 0 2006.173.06:44:34.23#ibcon#about to read 3, iclass 21, count 0 2006.173.06:44:34.28#ibcon#read 3, iclass 21, count 0 2006.173.06:44:34.28#ibcon#about to read 4, iclass 21, count 0 2006.173.06:44:34.28#ibcon#read 4, iclass 21, count 0 2006.173.06:44:34.28#ibcon#about to read 5, iclass 21, count 0 2006.173.06:44:34.28#ibcon#read 5, iclass 21, count 0 2006.173.06:44:34.28#ibcon#about to read 6, iclass 21, count 0 2006.173.06:44:34.28#ibcon#read 6, iclass 21, count 0 2006.173.06:44:34.28#ibcon#end of sib2, iclass 21, count 0 2006.173.06:44:34.28#ibcon#*after write, iclass 21, count 0 2006.173.06:44:34.28#ibcon#*before return 0, iclass 21, count 0 2006.173.06:44:34.28#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.06:44:34.28#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.06:44:34.28#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.06:44:34.28#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.06:44:34.28$vck44/va=1,7 2006.173.06:44:34.28#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.06:44:34.28#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.06:44:34.28#ibcon#ireg 11 cls_cnt 2 2006.173.06:44:34.28#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.06:44:34.28#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.06:44:34.28#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.06:44:34.28#ibcon#enter wrdev, iclass 23, count 2 2006.173.06:44:34.28#ibcon#first serial, iclass 23, count 2 2006.173.06:44:34.28#ibcon#enter sib2, iclass 23, count 2 2006.173.06:44:34.28#ibcon#flushed, iclass 23, count 2 2006.173.06:44:34.28#ibcon#about to write, iclass 23, count 2 2006.173.06:44:34.28#ibcon#wrote, iclass 23, count 2 2006.173.06:44:34.28#ibcon#about to read 3, iclass 23, count 2 2006.173.06:44:34.30#ibcon#read 3, iclass 23, count 2 2006.173.06:44:34.30#ibcon#about to read 4, iclass 23, count 2 2006.173.06:44:34.30#ibcon#read 4, iclass 23, count 2 2006.173.06:44:34.30#ibcon#about to read 5, iclass 23, count 2 2006.173.06:44:34.30#ibcon#read 5, iclass 23, count 2 2006.173.06:44:34.30#ibcon#about to read 6, iclass 23, count 2 2006.173.06:44:34.30#ibcon#read 6, iclass 23, count 2 2006.173.06:44:34.30#ibcon#end of sib2, iclass 23, count 2 2006.173.06:44:34.30#ibcon#*mode == 0, iclass 23, count 2 2006.173.06:44:34.30#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.06:44:34.30#ibcon#[25=AT01-07\r\n] 2006.173.06:44:34.30#ibcon#*before write, iclass 23, count 2 2006.173.06:44:34.30#ibcon#enter sib2, iclass 23, count 2 2006.173.06:44:34.30#ibcon#flushed, iclass 23, count 2 2006.173.06:44:34.30#ibcon#about to write, iclass 23, count 2 2006.173.06:44:34.30#ibcon#wrote, iclass 23, count 2 2006.173.06:44:34.30#ibcon#about to read 3, iclass 23, count 2 2006.173.06:44:34.33#ibcon#read 3, iclass 23, count 2 2006.173.06:44:34.33#ibcon#about to read 4, iclass 23, count 2 2006.173.06:44:34.33#ibcon#read 4, iclass 23, count 2 2006.173.06:44:34.33#ibcon#about to read 5, iclass 23, count 2 2006.173.06:44:34.33#ibcon#read 5, iclass 23, count 2 2006.173.06:44:34.33#ibcon#about to read 6, iclass 23, count 2 2006.173.06:44:34.33#ibcon#read 6, iclass 23, count 2 2006.173.06:44:34.33#ibcon#end of sib2, iclass 23, count 2 2006.173.06:44:34.33#ibcon#*after write, iclass 23, count 2 2006.173.06:44:34.33#ibcon#*before return 0, iclass 23, count 2 2006.173.06:44:34.33#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.06:44:34.33#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.06:44:34.33#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.06:44:34.33#ibcon#ireg 7 cls_cnt 0 2006.173.06:44:34.33#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.06:44:34.45#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.06:44:34.45#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.06:44:34.45#ibcon#enter wrdev, iclass 23, count 0 2006.173.06:44:34.45#ibcon#first serial, iclass 23, count 0 2006.173.06:44:34.45#ibcon#enter sib2, iclass 23, count 0 2006.173.06:44:34.45#ibcon#flushed, iclass 23, count 0 2006.173.06:44:34.45#ibcon#about to write, iclass 23, count 0 2006.173.06:44:34.45#ibcon#wrote, iclass 23, count 0 2006.173.06:44:34.45#ibcon#about to read 3, iclass 23, count 0 2006.173.06:44:34.47#ibcon#read 3, iclass 23, count 0 2006.173.06:44:34.47#ibcon#about to read 4, iclass 23, count 0 2006.173.06:44:34.47#ibcon#read 4, iclass 23, count 0 2006.173.06:44:34.47#ibcon#about to read 5, iclass 23, count 0 2006.173.06:44:34.47#ibcon#read 5, iclass 23, count 0 2006.173.06:44:34.47#ibcon#about to read 6, iclass 23, count 0 2006.173.06:44:34.47#ibcon#read 6, iclass 23, count 0 2006.173.06:44:34.47#ibcon#end of sib2, iclass 23, count 0 2006.173.06:44:34.47#ibcon#*mode == 0, iclass 23, count 0 2006.173.06:44:34.47#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.06:44:34.47#ibcon#[25=USB\r\n] 2006.173.06:44:34.47#ibcon#*before write, iclass 23, count 0 2006.173.06:44:34.47#ibcon#enter sib2, iclass 23, count 0 2006.173.06:44:34.47#ibcon#flushed, iclass 23, count 0 2006.173.06:44:34.47#ibcon#about to write, iclass 23, count 0 2006.173.06:44:34.47#ibcon#wrote, iclass 23, count 0 2006.173.06:44:34.47#ibcon#about to read 3, iclass 23, count 0 2006.173.06:44:34.50#ibcon#read 3, iclass 23, count 0 2006.173.06:44:34.50#ibcon#about to read 4, iclass 23, count 0 2006.173.06:44:34.50#ibcon#read 4, iclass 23, count 0 2006.173.06:44:34.50#ibcon#about to read 5, iclass 23, count 0 2006.173.06:44:34.50#ibcon#read 5, iclass 23, count 0 2006.173.06:44:34.50#ibcon#about to read 6, iclass 23, count 0 2006.173.06:44:34.50#ibcon#read 6, iclass 23, count 0 2006.173.06:44:34.50#ibcon#end of sib2, iclass 23, count 0 2006.173.06:44:34.50#ibcon#*after write, iclass 23, count 0 2006.173.06:44:34.50#ibcon#*before return 0, iclass 23, count 0 2006.173.06:44:34.50#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.06:44:34.50#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.06:44:34.50#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.06:44:34.50#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.06:44:34.50$vck44/valo=2,534.99 2006.173.06:44:34.50#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.06:44:34.50#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.06:44:34.50#ibcon#ireg 17 cls_cnt 0 2006.173.06:44:34.50#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.06:44:34.50#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.06:44:34.50#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.06:44:34.50#ibcon#enter wrdev, iclass 25, count 0 2006.173.06:44:34.50#ibcon#first serial, iclass 25, count 0 2006.173.06:44:34.50#ibcon#enter sib2, iclass 25, count 0 2006.173.06:44:34.50#ibcon#flushed, iclass 25, count 0 2006.173.06:44:34.50#ibcon#about to write, iclass 25, count 0 2006.173.06:44:34.50#ibcon#wrote, iclass 25, count 0 2006.173.06:44:34.50#ibcon#about to read 3, iclass 25, count 0 2006.173.06:44:34.52#ibcon#read 3, iclass 25, count 0 2006.173.06:44:34.52#ibcon#about to read 4, iclass 25, count 0 2006.173.06:44:34.52#ibcon#read 4, iclass 25, count 0 2006.173.06:44:34.52#ibcon#about to read 5, iclass 25, count 0 2006.173.06:44:34.52#ibcon#read 5, iclass 25, count 0 2006.173.06:44:34.52#ibcon#about to read 6, iclass 25, count 0 2006.173.06:44:34.52#ibcon#read 6, iclass 25, count 0 2006.173.06:44:34.52#ibcon#end of sib2, iclass 25, count 0 2006.173.06:44:34.52#ibcon#*mode == 0, iclass 25, count 0 2006.173.06:44:34.52#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.06:44:34.52#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.06:44:34.52#ibcon#*before write, iclass 25, count 0 2006.173.06:44:34.52#ibcon#enter sib2, iclass 25, count 0 2006.173.06:44:34.52#ibcon#flushed, iclass 25, count 0 2006.173.06:44:34.52#ibcon#about to write, iclass 25, count 0 2006.173.06:44:34.52#ibcon#wrote, iclass 25, count 0 2006.173.06:44:34.52#ibcon#about to read 3, iclass 25, count 0 2006.173.06:44:34.56#ibcon#read 3, iclass 25, count 0 2006.173.06:44:34.56#ibcon#about to read 4, iclass 25, count 0 2006.173.06:44:34.56#ibcon#read 4, iclass 25, count 0 2006.173.06:44:34.56#ibcon#about to read 5, iclass 25, count 0 2006.173.06:44:34.56#ibcon#read 5, iclass 25, count 0 2006.173.06:44:34.56#ibcon#about to read 6, iclass 25, count 0 2006.173.06:44:34.56#ibcon#read 6, iclass 25, count 0 2006.173.06:44:34.56#ibcon#end of sib2, iclass 25, count 0 2006.173.06:44:34.56#ibcon#*after write, iclass 25, count 0 2006.173.06:44:34.56#ibcon#*before return 0, iclass 25, count 0 2006.173.06:44:34.56#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.06:44:34.56#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.06:44:34.56#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.06:44:34.56#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.06:44:34.56$vck44/va=2,6 2006.173.06:44:34.56#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.06:44:34.56#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.06:44:34.56#ibcon#ireg 11 cls_cnt 2 2006.173.06:44:34.56#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.06:44:34.62#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.06:44:34.62#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.06:44:34.62#ibcon#enter wrdev, iclass 27, count 2 2006.173.06:44:34.62#ibcon#first serial, iclass 27, count 2 2006.173.06:44:34.62#ibcon#enter sib2, iclass 27, count 2 2006.173.06:44:34.62#ibcon#flushed, iclass 27, count 2 2006.173.06:44:34.62#ibcon#about to write, iclass 27, count 2 2006.173.06:44:34.62#ibcon#wrote, iclass 27, count 2 2006.173.06:44:34.62#ibcon#about to read 3, iclass 27, count 2 2006.173.06:44:34.64#ibcon#read 3, iclass 27, count 2 2006.173.06:44:34.64#ibcon#about to read 4, iclass 27, count 2 2006.173.06:44:34.64#ibcon#read 4, iclass 27, count 2 2006.173.06:44:34.64#ibcon#about to read 5, iclass 27, count 2 2006.173.06:44:34.64#ibcon#read 5, iclass 27, count 2 2006.173.06:44:34.64#ibcon#about to read 6, iclass 27, count 2 2006.173.06:44:34.64#ibcon#read 6, iclass 27, count 2 2006.173.06:44:34.64#ibcon#end of sib2, iclass 27, count 2 2006.173.06:44:34.64#ibcon#*mode == 0, iclass 27, count 2 2006.173.06:44:34.64#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.06:44:34.64#ibcon#[25=AT02-06\r\n] 2006.173.06:44:34.64#ibcon#*before write, iclass 27, count 2 2006.173.06:44:34.64#ibcon#enter sib2, iclass 27, count 2 2006.173.06:44:34.64#ibcon#flushed, iclass 27, count 2 2006.173.06:44:34.64#ibcon#about to write, iclass 27, count 2 2006.173.06:44:34.64#ibcon#wrote, iclass 27, count 2 2006.173.06:44:34.64#ibcon#about to read 3, iclass 27, count 2 2006.173.06:44:34.67#ibcon#read 3, iclass 27, count 2 2006.173.06:44:34.67#ibcon#about to read 4, iclass 27, count 2 2006.173.06:44:34.67#ibcon#read 4, iclass 27, count 2 2006.173.06:44:34.67#ibcon#about to read 5, iclass 27, count 2 2006.173.06:44:34.67#ibcon#read 5, iclass 27, count 2 2006.173.06:44:34.67#ibcon#about to read 6, iclass 27, count 2 2006.173.06:44:34.67#ibcon#read 6, iclass 27, count 2 2006.173.06:44:34.67#ibcon#end of sib2, iclass 27, count 2 2006.173.06:44:34.67#ibcon#*after write, iclass 27, count 2 2006.173.06:44:34.67#ibcon#*before return 0, iclass 27, count 2 2006.173.06:44:34.67#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.06:44:34.67#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.06:44:34.67#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.06:44:34.67#ibcon#ireg 7 cls_cnt 0 2006.173.06:44:34.67#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.06:44:34.79#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.06:44:34.79#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.06:44:34.79#ibcon#enter wrdev, iclass 27, count 0 2006.173.06:44:34.79#ibcon#first serial, iclass 27, count 0 2006.173.06:44:34.79#ibcon#enter sib2, iclass 27, count 0 2006.173.06:44:34.79#ibcon#flushed, iclass 27, count 0 2006.173.06:44:34.79#ibcon#about to write, iclass 27, count 0 2006.173.06:44:34.79#ibcon#wrote, iclass 27, count 0 2006.173.06:44:34.79#ibcon#about to read 3, iclass 27, count 0 2006.173.06:44:34.81#ibcon#read 3, iclass 27, count 0 2006.173.06:44:34.81#ibcon#about to read 4, iclass 27, count 0 2006.173.06:44:34.81#ibcon#read 4, iclass 27, count 0 2006.173.06:44:34.81#ibcon#about to read 5, iclass 27, count 0 2006.173.06:44:34.81#ibcon#read 5, iclass 27, count 0 2006.173.06:44:34.81#ibcon#about to read 6, iclass 27, count 0 2006.173.06:44:34.81#ibcon#read 6, iclass 27, count 0 2006.173.06:44:34.81#ibcon#end of sib2, iclass 27, count 0 2006.173.06:44:34.81#ibcon#*mode == 0, iclass 27, count 0 2006.173.06:44:34.81#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.06:44:34.81#ibcon#[25=USB\r\n] 2006.173.06:44:34.81#ibcon#*before write, iclass 27, count 0 2006.173.06:44:34.81#ibcon#enter sib2, iclass 27, count 0 2006.173.06:44:34.81#ibcon#flushed, iclass 27, count 0 2006.173.06:44:34.81#ibcon#about to write, iclass 27, count 0 2006.173.06:44:34.81#ibcon#wrote, iclass 27, count 0 2006.173.06:44:34.81#ibcon#about to read 3, iclass 27, count 0 2006.173.06:44:34.84#ibcon#read 3, iclass 27, count 0 2006.173.06:44:34.84#ibcon#about to read 4, iclass 27, count 0 2006.173.06:44:34.84#ibcon#read 4, iclass 27, count 0 2006.173.06:44:34.84#ibcon#about to read 5, iclass 27, count 0 2006.173.06:44:34.84#ibcon#read 5, iclass 27, count 0 2006.173.06:44:34.84#ibcon#about to read 6, iclass 27, count 0 2006.173.06:44:34.84#ibcon#read 6, iclass 27, count 0 2006.173.06:44:34.84#ibcon#end of sib2, iclass 27, count 0 2006.173.06:44:34.84#ibcon#*after write, iclass 27, count 0 2006.173.06:44:34.84#ibcon#*before return 0, iclass 27, count 0 2006.173.06:44:34.84#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.06:44:34.84#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.06:44:34.84#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.06:44:34.84#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.06:44:34.84$vck44/valo=3,564.99 2006.173.06:44:34.84#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.06:44:34.84#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.06:44:34.84#ibcon#ireg 17 cls_cnt 0 2006.173.06:44:34.84#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.06:44:34.84#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.06:44:34.84#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.06:44:34.84#ibcon#enter wrdev, iclass 29, count 0 2006.173.06:44:34.84#ibcon#first serial, iclass 29, count 0 2006.173.06:44:34.84#ibcon#enter sib2, iclass 29, count 0 2006.173.06:44:34.84#ibcon#flushed, iclass 29, count 0 2006.173.06:44:34.84#ibcon#about to write, iclass 29, count 0 2006.173.06:44:34.84#ibcon#wrote, iclass 29, count 0 2006.173.06:44:34.84#ibcon#about to read 3, iclass 29, count 0 2006.173.06:44:34.86#ibcon#read 3, iclass 29, count 0 2006.173.06:44:34.86#ibcon#about to read 4, iclass 29, count 0 2006.173.06:44:34.86#ibcon#read 4, iclass 29, count 0 2006.173.06:44:34.86#ibcon#about to read 5, iclass 29, count 0 2006.173.06:44:34.86#ibcon#read 5, iclass 29, count 0 2006.173.06:44:34.86#ibcon#about to read 6, iclass 29, count 0 2006.173.06:44:34.86#ibcon#read 6, iclass 29, count 0 2006.173.06:44:34.86#ibcon#end of sib2, iclass 29, count 0 2006.173.06:44:34.86#ibcon#*mode == 0, iclass 29, count 0 2006.173.06:44:34.86#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.06:44:34.86#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.06:44:34.86#ibcon#*before write, iclass 29, count 0 2006.173.06:44:34.86#ibcon#enter sib2, iclass 29, count 0 2006.173.06:44:34.86#ibcon#flushed, iclass 29, count 0 2006.173.06:44:34.86#ibcon#about to write, iclass 29, count 0 2006.173.06:44:34.86#ibcon#wrote, iclass 29, count 0 2006.173.06:44:34.86#ibcon#about to read 3, iclass 29, count 0 2006.173.06:44:34.90#ibcon#read 3, iclass 29, count 0 2006.173.06:44:34.90#ibcon#about to read 4, iclass 29, count 0 2006.173.06:44:34.90#ibcon#read 4, iclass 29, count 0 2006.173.06:44:34.90#ibcon#about to read 5, iclass 29, count 0 2006.173.06:44:34.90#ibcon#read 5, iclass 29, count 0 2006.173.06:44:34.90#ibcon#about to read 6, iclass 29, count 0 2006.173.06:44:34.90#ibcon#read 6, iclass 29, count 0 2006.173.06:44:34.90#ibcon#end of sib2, iclass 29, count 0 2006.173.06:44:34.90#ibcon#*after write, iclass 29, count 0 2006.173.06:44:34.90#ibcon#*before return 0, iclass 29, count 0 2006.173.06:44:34.90#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.06:44:34.90#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.06:44:34.90#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.06:44:34.90#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.06:44:34.90$vck44/va=3,5 2006.173.06:44:34.90#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.06:44:34.90#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.06:44:34.90#ibcon#ireg 11 cls_cnt 2 2006.173.06:44:34.90#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.06:44:34.96#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.06:44:34.96#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.06:44:34.96#ibcon#enter wrdev, iclass 31, count 2 2006.173.06:44:34.96#ibcon#first serial, iclass 31, count 2 2006.173.06:44:34.96#ibcon#enter sib2, iclass 31, count 2 2006.173.06:44:34.96#ibcon#flushed, iclass 31, count 2 2006.173.06:44:34.96#ibcon#about to write, iclass 31, count 2 2006.173.06:44:34.96#ibcon#wrote, iclass 31, count 2 2006.173.06:44:34.96#ibcon#about to read 3, iclass 31, count 2 2006.173.06:44:34.98#ibcon#read 3, iclass 31, count 2 2006.173.06:44:34.98#ibcon#about to read 4, iclass 31, count 2 2006.173.06:44:34.98#ibcon#read 4, iclass 31, count 2 2006.173.06:44:34.98#ibcon#about to read 5, iclass 31, count 2 2006.173.06:44:34.98#ibcon#read 5, iclass 31, count 2 2006.173.06:44:34.98#ibcon#about to read 6, iclass 31, count 2 2006.173.06:44:34.98#ibcon#read 6, iclass 31, count 2 2006.173.06:44:34.98#ibcon#end of sib2, iclass 31, count 2 2006.173.06:44:34.98#ibcon#*mode == 0, iclass 31, count 2 2006.173.06:44:34.98#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.06:44:34.98#ibcon#[25=AT03-05\r\n] 2006.173.06:44:34.98#ibcon#*before write, iclass 31, count 2 2006.173.06:44:34.98#ibcon#enter sib2, iclass 31, count 2 2006.173.06:44:34.98#ibcon#flushed, iclass 31, count 2 2006.173.06:44:34.98#ibcon#about to write, iclass 31, count 2 2006.173.06:44:34.98#ibcon#wrote, iclass 31, count 2 2006.173.06:44:34.98#ibcon#about to read 3, iclass 31, count 2 2006.173.06:44:35.01#ibcon#read 3, iclass 31, count 2 2006.173.06:44:35.01#ibcon#about to read 4, iclass 31, count 2 2006.173.06:44:35.01#ibcon#read 4, iclass 31, count 2 2006.173.06:44:35.01#ibcon#about to read 5, iclass 31, count 2 2006.173.06:44:35.01#ibcon#read 5, iclass 31, count 2 2006.173.06:44:35.01#ibcon#about to read 6, iclass 31, count 2 2006.173.06:44:35.01#ibcon#read 6, iclass 31, count 2 2006.173.06:44:35.01#ibcon#end of sib2, iclass 31, count 2 2006.173.06:44:35.01#ibcon#*after write, iclass 31, count 2 2006.173.06:44:35.01#ibcon#*before return 0, iclass 31, count 2 2006.173.06:44:35.01#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.06:44:35.01#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.06:44:35.01#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.06:44:35.01#ibcon#ireg 7 cls_cnt 0 2006.173.06:44:35.01#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.06:44:35.13#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.06:44:35.13#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.06:44:35.13#ibcon#enter wrdev, iclass 31, count 0 2006.173.06:44:35.13#ibcon#first serial, iclass 31, count 0 2006.173.06:44:35.13#ibcon#enter sib2, iclass 31, count 0 2006.173.06:44:35.13#ibcon#flushed, iclass 31, count 0 2006.173.06:44:35.13#ibcon#about to write, iclass 31, count 0 2006.173.06:44:35.13#ibcon#wrote, iclass 31, count 0 2006.173.06:44:35.13#ibcon#about to read 3, iclass 31, count 0 2006.173.06:44:35.15#ibcon#read 3, iclass 31, count 0 2006.173.06:44:35.15#ibcon#about to read 4, iclass 31, count 0 2006.173.06:44:35.15#ibcon#read 4, iclass 31, count 0 2006.173.06:44:35.15#ibcon#about to read 5, iclass 31, count 0 2006.173.06:44:35.15#ibcon#read 5, iclass 31, count 0 2006.173.06:44:35.15#ibcon#about to read 6, iclass 31, count 0 2006.173.06:44:35.15#ibcon#read 6, iclass 31, count 0 2006.173.06:44:35.15#ibcon#end of sib2, iclass 31, count 0 2006.173.06:44:35.15#ibcon#*mode == 0, iclass 31, count 0 2006.173.06:44:35.15#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.06:44:35.15#ibcon#[25=USB\r\n] 2006.173.06:44:35.15#ibcon#*before write, iclass 31, count 0 2006.173.06:44:35.15#ibcon#enter sib2, iclass 31, count 0 2006.173.06:44:35.15#ibcon#flushed, iclass 31, count 0 2006.173.06:44:35.15#ibcon#about to write, iclass 31, count 0 2006.173.06:44:35.15#ibcon#wrote, iclass 31, count 0 2006.173.06:44:35.15#ibcon#about to read 3, iclass 31, count 0 2006.173.06:44:35.18#ibcon#read 3, iclass 31, count 0 2006.173.06:44:35.18#ibcon#about to read 4, iclass 31, count 0 2006.173.06:44:35.18#ibcon#read 4, iclass 31, count 0 2006.173.06:44:35.18#ibcon#about to read 5, iclass 31, count 0 2006.173.06:44:35.18#ibcon#read 5, iclass 31, count 0 2006.173.06:44:35.18#ibcon#about to read 6, iclass 31, count 0 2006.173.06:44:35.18#ibcon#read 6, iclass 31, count 0 2006.173.06:44:35.18#ibcon#end of sib2, iclass 31, count 0 2006.173.06:44:35.18#ibcon#*after write, iclass 31, count 0 2006.173.06:44:35.18#ibcon#*before return 0, iclass 31, count 0 2006.173.06:44:35.18#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.06:44:35.18#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.06:44:35.18#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.06:44:35.18#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.06:44:35.18$vck44/valo=4,624.99 2006.173.06:44:35.18#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.06:44:35.18#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.06:44:35.18#ibcon#ireg 17 cls_cnt 0 2006.173.06:44:35.18#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.06:44:35.18#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.06:44:35.18#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.06:44:35.18#ibcon#enter wrdev, iclass 33, count 0 2006.173.06:44:35.18#ibcon#first serial, iclass 33, count 0 2006.173.06:44:35.18#ibcon#enter sib2, iclass 33, count 0 2006.173.06:44:35.18#ibcon#flushed, iclass 33, count 0 2006.173.06:44:35.18#ibcon#about to write, iclass 33, count 0 2006.173.06:44:35.18#ibcon#wrote, iclass 33, count 0 2006.173.06:44:35.18#ibcon#about to read 3, iclass 33, count 0 2006.173.06:44:35.20#ibcon#read 3, iclass 33, count 0 2006.173.06:44:35.20#ibcon#about to read 4, iclass 33, count 0 2006.173.06:44:35.20#ibcon#read 4, iclass 33, count 0 2006.173.06:44:35.20#ibcon#about to read 5, iclass 33, count 0 2006.173.06:44:35.20#ibcon#read 5, iclass 33, count 0 2006.173.06:44:35.20#ibcon#about to read 6, iclass 33, count 0 2006.173.06:44:35.20#ibcon#read 6, iclass 33, count 0 2006.173.06:44:35.20#ibcon#end of sib2, iclass 33, count 0 2006.173.06:44:35.20#ibcon#*mode == 0, iclass 33, count 0 2006.173.06:44:35.20#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.06:44:35.20#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.06:44:35.20#ibcon#*before write, iclass 33, count 0 2006.173.06:44:35.20#ibcon#enter sib2, iclass 33, count 0 2006.173.06:44:35.20#ibcon#flushed, iclass 33, count 0 2006.173.06:44:35.20#ibcon#about to write, iclass 33, count 0 2006.173.06:44:35.20#ibcon#wrote, iclass 33, count 0 2006.173.06:44:35.20#ibcon#about to read 3, iclass 33, count 0 2006.173.06:44:35.24#ibcon#read 3, iclass 33, count 0 2006.173.06:44:35.24#ibcon#about to read 4, iclass 33, count 0 2006.173.06:44:35.24#ibcon#read 4, iclass 33, count 0 2006.173.06:44:35.24#ibcon#about to read 5, iclass 33, count 0 2006.173.06:44:35.24#ibcon#read 5, iclass 33, count 0 2006.173.06:44:35.24#ibcon#about to read 6, iclass 33, count 0 2006.173.06:44:35.24#ibcon#read 6, iclass 33, count 0 2006.173.06:44:35.24#ibcon#end of sib2, iclass 33, count 0 2006.173.06:44:35.24#ibcon#*after write, iclass 33, count 0 2006.173.06:44:35.24#ibcon#*before return 0, iclass 33, count 0 2006.173.06:44:35.24#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.06:44:35.24#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.06:44:35.24#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.06:44:35.24#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.06:44:35.24$vck44/va=4,6 2006.173.06:44:35.24#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.06:44:35.24#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.06:44:35.24#ibcon#ireg 11 cls_cnt 2 2006.173.06:44:35.24#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.06:44:35.30#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.06:44:35.30#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.06:44:35.30#ibcon#enter wrdev, iclass 35, count 2 2006.173.06:44:35.30#ibcon#first serial, iclass 35, count 2 2006.173.06:44:35.30#ibcon#enter sib2, iclass 35, count 2 2006.173.06:44:35.30#ibcon#flushed, iclass 35, count 2 2006.173.06:44:35.30#ibcon#about to write, iclass 35, count 2 2006.173.06:44:35.30#ibcon#wrote, iclass 35, count 2 2006.173.06:44:35.30#ibcon#about to read 3, iclass 35, count 2 2006.173.06:44:35.32#ibcon#read 3, iclass 35, count 2 2006.173.06:44:35.32#ibcon#about to read 4, iclass 35, count 2 2006.173.06:44:35.32#ibcon#read 4, iclass 35, count 2 2006.173.06:44:35.32#ibcon#about to read 5, iclass 35, count 2 2006.173.06:44:35.32#ibcon#read 5, iclass 35, count 2 2006.173.06:44:35.32#ibcon#about to read 6, iclass 35, count 2 2006.173.06:44:35.32#ibcon#read 6, iclass 35, count 2 2006.173.06:44:35.32#ibcon#end of sib2, iclass 35, count 2 2006.173.06:44:35.32#ibcon#*mode == 0, iclass 35, count 2 2006.173.06:44:35.32#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.06:44:35.32#ibcon#[25=AT04-06\r\n] 2006.173.06:44:35.32#ibcon#*before write, iclass 35, count 2 2006.173.06:44:35.32#ibcon#enter sib2, iclass 35, count 2 2006.173.06:44:35.32#ibcon#flushed, iclass 35, count 2 2006.173.06:44:35.32#ibcon#about to write, iclass 35, count 2 2006.173.06:44:35.32#ibcon#wrote, iclass 35, count 2 2006.173.06:44:35.32#ibcon#about to read 3, iclass 35, count 2 2006.173.06:44:35.35#ibcon#read 3, iclass 35, count 2 2006.173.06:44:35.35#ibcon#about to read 4, iclass 35, count 2 2006.173.06:44:35.35#ibcon#read 4, iclass 35, count 2 2006.173.06:44:35.35#ibcon#about to read 5, iclass 35, count 2 2006.173.06:44:35.35#ibcon#read 5, iclass 35, count 2 2006.173.06:44:35.35#ibcon#about to read 6, iclass 35, count 2 2006.173.06:44:35.35#ibcon#read 6, iclass 35, count 2 2006.173.06:44:35.35#ibcon#end of sib2, iclass 35, count 2 2006.173.06:44:35.35#ibcon#*after write, iclass 35, count 2 2006.173.06:44:35.35#ibcon#*before return 0, iclass 35, count 2 2006.173.06:44:35.35#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.06:44:35.35#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.06:44:35.35#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.06:44:35.35#ibcon#ireg 7 cls_cnt 0 2006.173.06:44:35.35#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.06:44:35.47#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.06:44:35.47#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.06:44:35.47#ibcon#enter wrdev, iclass 35, count 0 2006.173.06:44:35.47#ibcon#first serial, iclass 35, count 0 2006.173.06:44:35.47#ibcon#enter sib2, iclass 35, count 0 2006.173.06:44:35.47#ibcon#flushed, iclass 35, count 0 2006.173.06:44:35.47#ibcon#about to write, iclass 35, count 0 2006.173.06:44:35.47#ibcon#wrote, iclass 35, count 0 2006.173.06:44:35.47#ibcon#about to read 3, iclass 35, count 0 2006.173.06:44:35.49#ibcon#read 3, iclass 35, count 0 2006.173.06:44:35.49#ibcon#about to read 4, iclass 35, count 0 2006.173.06:44:35.49#ibcon#read 4, iclass 35, count 0 2006.173.06:44:35.49#ibcon#about to read 5, iclass 35, count 0 2006.173.06:44:35.49#ibcon#read 5, iclass 35, count 0 2006.173.06:44:35.49#ibcon#about to read 6, iclass 35, count 0 2006.173.06:44:35.49#ibcon#read 6, iclass 35, count 0 2006.173.06:44:35.49#ibcon#end of sib2, iclass 35, count 0 2006.173.06:44:35.49#ibcon#*mode == 0, iclass 35, count 0 2006.173.06:44:35.49#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.06:44:35.49#ibcon#[25=USB\r\n] 2006.173.06:44:35.49#ibcon#*before write, iclass 35, count 0 2006.173.06:44:35.49#ibcon#enter sib2, iclass 35, count 0 2006.173.06:44:35.49#ibcon#flushed, iclass 35, count 0 2006.173.06:44:35.49#ibcon#about to write, iclass 35, count 0 2006.173.06:44:35.49#ibcon#wrote, iclass 35, count 0 2006.173.06:44:35.49#ibcon#about to read 3, iclass 35, count 0 2006.173.06:44:35.52#ibcon#read 3, iclass 35, count 0 2006.173.06:44:35.52#ibcon#about to read 4, iclass 35, count 0 2006.173.06:44:35.52#ibcon#read 4, iclass 35, count 0 2006.173.06:44:35.52#ibcon#about to read 5, iclass 35, count 0 2006.173.06:44:35.52#ibcon#read 5, iclass 35, count 0 2006.173.06:44:35.52#ibcon#about to read 6, iclass 35, count 0 2006.173.06:44:35.52#ibcon#read 6, iclass 35, count 0 2006.173.06:44:35.52#ibcon#end of sib2, iclass 35, count 0 2006.173.06:44:35.52#ibcon#*after write, iclass 35, count 0 2006.173.06:44:35.52#ibcon#*before return 0, iclass 35, count 0 2006.173.06:44:35.52#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.06:44:35.52#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.06:44:35.52#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.06:44:35.52#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.06:44:35.52$vck44/valo=5,734.99 2006.173.06:44:35.52#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.06:44:35.52#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.06:44:35.52#ibcon#ireg 17 cls_cnt 0 2006.173.06:44:35.52#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.06:44:35.52#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.06:44:35.52#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.06:44:35.52#ibcon#enter wrdev, iclass 37, count 0 2006.173.06:44:35.52#ibcon#first serial, iclass 37, count 0 2006.173.06:44:35.52#ibcon#enter sib2, iclass 37, count 0 2006.173.06:44:35.52#ibcon#flushed, iclass 37, count 0 2006.173.06:44:35.52#ibcon#about to write, iclass 37, count 0 2006.173.06:44:35.52#ibcon#wrote, iclass 37, count 0 2006.173.06:44:35.52#ibcon#about to read 3, iclass 37, count 0 2006.173.06:44:35.54#ibcon#read 3, iclass 37, count 0 2006.173.06:44:35.54#ibcon#about to read 4, iclass 37, count 0 2006.173.06:44:35.54#ibcon#read 4, iclass 37, count 0 2006.173.06:44:35.54#ibcon#about to read 5, iclass 37, count 0 2006.173.06:44:35.54#ibcon#read 5, iclass 37, count 0 2006.173.06:44:35.54#ibcon#about to read 6, iclass 37, count 0 2006.173.06:44:35.54#ibcon#read 6, iclass 37, count 0 2006.173.06:44:35.54#ibcon#end of sib2, iclass 37, count 0 2006.173.06:44:35.54#ibcon#*mode == 0, iclass 37, count 0 2006.173.06:44:35.54#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.06:44:35.54#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.06:44:35.54#ibcon#*before write, iclass 37, count 0 2006.173.06:44:35.54#ibcon#enter sib2, iclass 37, count 0 2006.173.06:44:35.54#ibcon#flushed, iclass 37, count 0 2006.173.06:44:35.54#ibcon#about to write, iclass 37, count 0 2006.173.06:44:35.54#ibcon#wrote, iclass 37, count 0 2006.173.06:44:35.54#ibcon#about to read 3, iclass 37, count 0 2006.173.06:44:35.58#ibcon#read 3, iclass 37, count 0 2006.173.06:44:35.58#ibcon#about to read 4, iclass 37, count 0 2006.173.06:44:35.58#ibcon#read 4, iclass 37, count 0 2006.173.06:44:35.58#ibcon#about to read 5, iclass 37, count 0 2006.173.06:44:35.58#ibcon#read 5, iclass 37, count 0 2006.173.06:44:35.58#ibcon#about to read 6, iclass 37, count 0 2006.173.06:44:35.58#ibcon#read 6, iclass 37, count 0 2006.173.06:44:35.58#ibcon#end of sib2, iclass 37, count 0 2006.173.06:44:35.58#ibcon#*after write, iclass 37, count 0 2006.173.06:44:35.58#ibcon#*before return 0, iclass 37, count 0 2006.173.06:44:35.58#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.06:44:35.58#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.06:44:35.58#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.06:44:35.58#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.06:44:35.58$vck44/va=5,4 2006.173.06:44:35.58#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.06:44:35.58#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.06:44:35.58#ibcon#ireg 11 cls_cnt 2 2006.173.06:44:35.58#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.06:44:35.64#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.06:44:35.64#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.06:44:35.64#ibcon#enter wrdev, iclass 39, count 2 2006.173.06:44:35.64#ibcon#first serial, iclass 39, count 2 2006.173.06:44:35.64#ibcon#enter sib2, iclass 39, count 2 2006.173.06:44:35.64#ibcon#flushed, iclass 39, count 2 2006.173.06:44:35.64#ibcon#about to write, iclass 39, count 2 2006.173.06:44:35.64#ibcon#wrote, iclass 39, count 2 2006.173.06:44:35.64#ibcon#about to read 3, iclass 39, count 2 2006.173.06:44:35.66#ibcon#read 3, iclass 39, count 2 2006.173.06:44:35.66#ibcon#about to read 4, iclass 39, count 2 2006.173.06:44:35.66#ibcon#read 4, iclass 39, count 2 2006.173.06:44:35.66#ibcon#about to read 5, iclass 39, count 2 2006.173.06:44:35.66#ibcon#read 5, iclass 39, count 2 2006.173.06:44:35.66#ibcon#about to read 6, iclass 39, count 2 2006.173.06:44:35.66#ibcon#read 6, iclass 39, count 2 2006.173.06:44:35.66#ibcon#end of sib2, iclass 39, count 2 2006.173.06:44:35.66#ibcon#*mode == 0, iclass 39, count 2 2006.173.06:44:35.66#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.06:44:35.66#ibcon#[25=AT05-04\r\n] 2006.173.06:44:35.66#ibcon#*before write, iclass 39, count 2 2006.173.06:44:35.66#ibcon#enter sib2, iclass 39, count 2 2006.173.06:44:35.66#ibcon#flushed, iclass 39, count 2 2006.173.06:44:35.66#ibcon#about to write, iclass 39, count 2 2006.173.06:44:35.66#ibcon#wrote, iclass 39, count 2 2006.173.06:44:35.66#ibcon#about to read 3, iclass 39, count 2 2006.173.06:44:35.69#ibcon#read 3, iclass 39, count 2 2006.173.06:44:35.69#ibcon#about to read 4, iclass 39, count 2 2006.173.06:44:35.69#ibcon#read 4, iclass 39, count 2 2006.173.06:44:35.69#ibcon#about to read 5, iclass 39, count 2 2006.173.06:44:35.69#ibcon#read 5, iclass 39, count 2 2006.173.06:44:35.69#ibcon#about to read 6, iclass 39, count 2 2006.173.06:44:35.69#ibcon#read 6, iclass 39, count 2 2006.173.06:44:35.69#ibcon#end of sib2, iclass 39, count 2 2006.173.06:44:35.69#ibcon#*after write, iclass 39, count 2 2006.173.06:44:35.69#ibcon#*before return 0, iclass 39, count 2 2006.173.06:44:35.69#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.06:44:35.69#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.06:44:35.69#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.06:44:35.69#ibcon#ireg 7 cls_cnt 0 2006.173.06:44:35.69#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.06:44:35.81#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.06:44:35.81#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.06:44:35.81#ibcon#enter wrdev, iclass 39, count 0 2006.173.06:44:35.81#ibcon#first serial, iclass 39, count 0 2006.173.06:44:35.81#ibcon#enter sib2, iclass 39, count 0 2006.173.06:44:35.81#ibcon#flushed, iclass 39, count 0 2006.173.06:44:35.81#ibcon#about to write, iclass 39, count 0 2006.173.06:44:35.81#ibcon#wrote, iclass 39, count 0 2006.173.06:44:35.81#ibcon#about to read 3, iclass 39, count 0 2006.173.06:44:35.83#ibcon#read 3, iclass 39, count 0 2006.173.06:44:35.83#ibcon#about to read 4, iclass 39, count 0 2006.173.06:44:35.83#ibcon#read 4, iclass 39, count 0 2006.173.06:44:35.83#ibcon#about to read 5, iclass 39, count 0 2006.173.06:44:35.83#ibcon#read 5, iclass 39, count 0 2006.173.06:44:35.83#ibcon#about to read 6, iclass 39, count 0 2006.173.06:44:35.83#ibcon#read 6, iclass 39, count 0 2006.173.06:44:35.83#ibcon#end of sib2, iclass 39, count 0 2006.173.06:44:35.83#ibcon#*mode == 0, iclass 39, count 0 2006.173.06:44:35.83#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.06:44:35.83#ibcon#[25=USB\r\n] 2006.173.06:44:35.83#ibcon#*before write, iclass 39, count 0 2006.173.06:44:35.83#ibcon#enter sib2, iclass 39, count 0 2006.173.06:44:35.83#ibcon#flushed, iclass 39, count 0 2006.173.06:44:35.83#ibcon#about to write, iclass 39, count 0 2006.173.06:44:35.83#ibcon#wrote, iclass 39, count 0 2006.173.06:44:35.83#ibcon#about to read 3, iclass 39, count 0 2006.173.06:44:35.86#ibcon#read 3, iclass 39, count 0 2006.173.06:44:35.86#ibcon#about to read 4, iclass 39, count 0 2006.173.06:44:35.86#ibcon#read 4, iclass 39, count 0 2006.173.06:44:35.86#ibcon#about to read 5, iclass 39, count 0 2006.173.06:44:35.86#ibcon#read 5, iclass 39, count 0 2006.173.06:44:35.86#ibcon#about to read 6, iclass 39, count 0 2006.173.06:44:35.86#ibcon#read 6, iclass 39, count 0 2006.173.06:44:35.86#ibcon#end of sib2, iclass 39, count 0 2006.173.06:44:35.86#ibcon#*after write, iclass 39, count 0 2006.173.06:44:35.86#ibcon#*before return 0, iclass 39, count 0 2006.173.06:44:35.86#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.06:44:35.86#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.06:44:35.86#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.06:44:35.86#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.06:44:35.86$vck44/valo=6,814.99 2006.173.06:44:35.86#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.06:44:35.86#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.06:44:35.86#ibcon#ireg 17 cls_cnt 0 2006.173.06:44:35.86#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.06:44:35.86#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.06:44:35.86#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.06:44:35.86#ibcon#enter wrdev, iclass 3, count 0 2006.173.06:44:35.86#ibcon#first serial, iclass 3, count 0 2006.173.06:44:35.86#ibcon#enter sib2, iclass 3, count 0 2006.173.06:44:35.86#ibcon#flushed, iclass 3, count 0 2006.173.06:44:35.86#ibcon#about to write, iclass 3, count 0 2006.173.06:44:35.86#ibcon#wrote, iclass 3, count 0 2006.173.06:44:35.86#ibcon#about to read 3, iclass 3, count 0 2006.173.06:44:35.88#ibcon#read 3, iclass 3, count 0 2006.173.06:44:35.88#ibcon#about to read 4, iclass 3, count 0 2006.173.06:44:35.88#ibcon#read 4, iclass 3, count 0 2006.173.06:44:35.88#ibcon#about to read 5, iclass 3, count 0 2006.173.06:44:35.88#ibcon#read 5, iclass 3, count 0 2006.173.06:44:35.88#ibcon#about to read 6, iclass 3, count 0 2006.173.06:44:35.88#ibcon#read 6, iclass 3, count 0 2006.173.06:44:35.88#ibcon#end of sib2, iclass 3, count 0 2006.173.06:44:35.88#ibcon#*mode == 0, iclass 3, count 0 2006.173.06:44:35.88#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.06:44:35.88#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.06:44:35.88#ibcon#*before write, iclass 3, count 0 2006.173.06:44:35.88#ibcon#enter sib2, iclass 3, count 0 2006.173.06:44:35.88#ibcon#flushed, iclass 3, count 0 2006.173.06:44:35.88#ibcon#about to write, iclass 3, count 0 2006.173.06:44:35.88#ibcon#wrote, iclass 3, count 0 2006.173.06:44:35.88#ibcon#about to read 3, iclass 3, count 0 2006.173.06:44:35.92#ibcon#read 3, iclass 3, count 0 2006.173.06:44:35.92#ibcon#about to read 4, iclass 3, count 0 2006.173.06:44:35.92#ibcon#read 4, iclass 3, count 0 2006.173.06:44:35.92#ibcon#about to read 5, iclass 3, count 0 2006.173.06:44:35.92#ibcon#read 5, iclass 3, count 0 2006.173.06:44:35.92#ibcon#about to read 6, iclass 3, count 0 2006.173.06:44:35.92#ibcon#read 6, iclass 3, count 0 2006.173.06:44:35.92#ibcon#end of sib2, iclass 3, count 0 2006.173.06:44:35.92#ibcon#*after write, iclass 3, count 0 2006.173.06:44:35.92#ibcon#*before return 0, iclass 3, count 0 2006.173.06:44:35.92#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.06:44:35.92#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.06:44:35.92#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.06:44:35.92#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.06:44:35.92$vck44/va=6,3 2006.173.06:44:35.92#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.06:44:35.92#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.06:44:35.92#ibcon#ireg 11 cls_cnt 2 2006.173.06:44:35.92#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.06:44:35.98#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.06:44:35.98#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.06:44:35.98#ibcon#enter wrdev, iclass 5, count 2 2006.173.06:44:35.98#ibcon#first serial, iclass 5, count 2 2006.173.06:44:35.98#ibcon#enter sib2, iclass 5, count 2 2006.173.06:44:35.98#ibcon#flushed, iclass 5, count 2 2006.173.06:44:35.98#ibcon#about to write, iclass 5, count 2 2006.173.06:44:35.98#ibcon#wrote, iclass 5, count 2 2006.173.06:44:35.98#ibcon#about to read 3, iclass 5, count 2 2006.173.06:44:36.00#ibcon#read 3, iclass 5, count 2 2006.173.06:44:36.00#ibcon#about to read 4, iclass 5, count 2 2006.173.06:44:36.00#ibcon#read 4, iclass 5, count 2 2006.173.06:44:36.00#ibcon#about to read 5, iclass 5, count 2 2006.173.06:44:36.00#ibcon#read 5, iclass 5, count 2 2006.173.06:44:36.00#ibcon#about to read 6, iclass 5, count 2 2006.173.06:44:36.00#ibcon#read 6, iclass 5, count 2 2006.173.06:44:36.00#ibcon#end of sib2, iclass 5, count 2 2006.173.06:44:36.00#ibcon#*mode == 0, iclass 5, count 2 2006.173.06:44:36.00#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.06:44:36.00#ibcon#[25=AT06-03\r\n] 2006.173.06:44:36.00#ibcon#*before write, iclass 5, count 2 2006.173.06:44:36.00#ibcon#enter sib2, iclass 5, count 2 2006.173.06:44:36.00#ibcon#flushed, iclass 5, count 2 2006.173.06:44:36.00#ibcon#about to write, iclass 5, count 2 2006.173.06:44:36.00#ibcon#wrote, iclass 5, count 2 2006.173.06:44:36.00#ibcon#about to read 3, iclass 5, count 2 2006.173.06:44:36.03#ibcon#read 3, iclass 5, count 2 2006.173.06:44:36.03#ibcon#about to read 4, iclass 5, count 2 2006.173.06:44:36.03#ibcon#read 4, iclass 5, count 2 2006.173.06:44:36.03#ibcon#about to read 5, iclass 5, count 2 2006.173.06:44:36.03#ibcon#read 5, iclass 5, count 2 2006.173.06:44:36.03#ibcon#about to read 6, iclass 5, count 2 2006.173.06:44:36.03#ibcon#read 6, iclass 5, count 2 2006.173.06:44:36.03#ibcon#end of sib2, iclass 5, count 2 2006.173.06:44:36.03#ibcon#*after write, iclass 5, count 2 2006.173.06:44:36.03#ibcon#*before return 0, iclass 5, count 2 2006.173.06:44:36.03#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.06:44:36.03#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.06:44:36.03#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.06:44:36.03#ibcon#ireg 7 cls_cnt 0 2006.173.06:44:36.03#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.06:44:36.15#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.06:44:36.15#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.06:44:36.15#ibcon#enter wrdev, iclass 5, count 0 2006.173.06:44:36.15#ibcon#first serial, iclass 5, count 0 2006.173.06:44:36.15#ibcon#enter sib2, iclass 5, count 0 2006.173.06:44:36.15#ibcon#flushed, iclass 5, count 0 2006.173.06:44:36.15#ibcon#about to write, iclass 5, count 0 2006.173.06:44:36.15#ibcon#wrote, iclass 5, count 0 2006.173.06:44:36.15#ibcon#about to read 3, iclass 5, count 0 2006.173.06:44:36.17#ibcon#read 3, iclass 5, count 0 2006.173.06:44:36.17#ibcon#about to read 4, iclass 5, count 0 2006.173.06:44:36.17#ibcon#read 4, iclass 5, count 0 2006.173.06:44:36.17#ibcon#about to read 5, iclass 5, count 0 2006.173.06:44:36.17#ibcon#read 5, iclass 5, count 0 2006.173.06:44:36.17#ibcon#about to read 6, iclass 5, count 0 2006.173.06:44:36.17#ibcon#read 6, iclass 5, count 0 2006.173.06:44:36.17#ibcon#end of sib2, iclass 5, count 0 2006.173.06:44:36.17#ibcon#*mode == 0, iclass 5, count 0 2006.173.06:44:36.17#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.06:44:36.17#ibcon#[25=USB\r\n] 2006.173.06:44:36.17#ibcon#*before write, iclass 5, count 0 2006.173.06:44:36.17#ibcon#enter sib2, iclass 5, count 0 2006.173.06:44:36.17#ibcon#flushed, iclass 5, count 0 2006.173.06:44:36.17#ibcon#about to write, iclass 5, count 0 2006.173.06:44:36.17#ibcon#wrote, iclass 5, count 0 2006.173.06:44:36.17#ibcon#about to read 3, iclass 5, count 0 2006.173.06:44:36.20#ibcon#read 3, iclass 5, count 0 2006.173.06:44:36.20#ibcon#about to read 4, iclass 5, count 0 2006.173.06:44:36.20#ibcon#read 4, iclass 5, count 0 2006.173.06:44:36.20#ibcon#about to read 5, iclass 5, count 0 2006.173.06:44:36.20#ibcon#read 5, iclass 5, count 0 2006.173.06:44:36.20#ibcon#about to read 6, iclass 5, count 0 2006.173.06:44:36.20#ibcon#read 6, iclass 5, count 0 2006.173.06:44:36.20#ibcon#end of sib2, iclass 5, count 0 2006.173.06:44:36.20#ibcon#*after write, iclass 5, count 0 2006.173.06:44:36.20#ibcon#*before return 0, iclass 5, count 0 2006.173.06:44:36.20#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.06:44:36.20#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.06:44:36.20#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.06:44:36.20#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.06:44:36.20$vck44/valo=7,864.99 2006.173.06:44:36.20#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.06:44:36.20#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.06:44:36.20#ibcon#ireg 17 cls_cnt 0 2006.173.06:44:36.20#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.06:44:36.20#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.06:44:36.20#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.06:44:36.20#ibcon#enter wrdev, iclass 7, count 0 2006.173.06:44:36.20#ibcon#first serial, iclass 7, count 0 2006.173.06:44:36.20#ibcon#enter sib2, iclass 7, count 0 2006.173.06:44:36.20#ibcon#flushed, iclass 7, count 0 2006.173.06:44:36.20#ibcon#about to write, iclass 7, count 0 2006.173.06:44:36.20#ibcon#wrote, iclass 7, count 0 2006.173.06:44:36.20#ibcon#about to read 3, iclass 7, count 0 2006.173.06:44:36.22#ibcon#read 3, iclass 7, count 0 2006.173.06:44:36.22#ibcon#about to read 4, iclass 7, count 0 2006.173.06:44:36.22#ibcon#read 4, iclass 7, count 0 2006.173.06:44:36.22#ibcon#about to read 5, iclass 7, count 0 2006.173.06:44:36.22#ibcon#read 5, iclass 7, count 0 2006.173.06:44:36.22#ibcon#about to read 6, iclass 7, count 0 2006.173.06:44:36.22#ibcon#read 6, iclass 7, count 0 2006.173.06:44:36.22#ibcon#end of sib2, iclass 7, count 0 2006.173.06:44:36.22#ibcon#*mode == 0, iclass 7, count 0 2006.173.06:44:36.22#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.06:44:36.22#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.06:44:36.22#ibcon#*before write, iclass 7, count 0 2006.173.06:44:36.22#ibcon#enter sib2, iclass 7, count 0 2006.173.06:44:36.22#ibcon#flushed, iclass 7, count 0 2006.173.06:44:36.22#ibcon#about to write, iclass 7, count 0 2006.173.06:44:36.22#ibcon#wrote, iclass 7, count 0 2006.173.06:44:36.22#ibcon#about to read 3, iclass 7, count 0 2006.173.06:44:36.26#ibcon#read 3, iclass 7, count 0 2006.173.06:44:36.26#ibcon#about to read 4, iclass 7, count 0 2006.173.06:44:36.26#ibcon#read 4, iclass 7, count 0 2006.173.06:44:36.26#ibcon#about to read 5, iclass 7, count 0 2006.173.06:44:36.26#ibcon#read 5, iclass 7, count 0 2006.173.06:44:36.26#ibcon#about to read 6, iclass 7, count 0 2006.173.06:44:36.26#ibcon#read 6, iclass 7, count 0 2006.173.06:44:36.26#ibcon#end of sib2, iclass 7, count 0 2006.173.06:44:36.26#ibcon#*after write, iclass 7, count 0 2006.173.06:44:36.26#ibcon#*before return 0, iclass 7, count 0 2006.173.06:44:36.26#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.06:44:36.26#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.06:44:36.26#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.06:44:36.26#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.06:44:36.26$vck44/va=7,4 2006.173.06:44:36.26#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.06:44:36.26#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.06:44:36.26#ibcon#ireg 11 cls_cnt 2 2006.173.06:44:36.26#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.06:44:36.32#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.06:44:36.32#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.06:44:36.32#ibcon#enter wrdev, iclass 11, count 2 2006.173.06:44:36.32#ibcon#first serial, iclass 11, count 2 2006.173.06:44:36.32#ibcon#enter sib2, iclass 11, count 2 2006.173.06:44:36.32#ibcon#flushed, iclass 11, count 2 2006.173.06:44:36.32#ibcon#about to write, iclass 11, count 2 2006.173.06:44:36.32#ibcon#wrote, iclass 11, count 2 2006.173.06:44:36.32#ibcon#about to read 3, iclass 11, count 2 2006.173.06:44:36.34#ibcon#read 3, iclass 11, count 2 2006.173.06:44:36.34#ibcon#about to read 4, iclass 11, count 2 2006.173.06:44:36.34#ibcon#read 4, iclass 11, count 2 2006.173.06:44:36.34#ibcon#about to read 5, iclass 11, count 2 2006.173.06:44:36.34#ibcon#read 5, iclass 11, count 2 2006.173.06:44:36.34#ibcon#about to read 6, iclass 11, count 2 2006.173.06:44:36.34#ibcon#read 6, iclass 11, count 2 2006.173.06:44:36.34#ibcon#end of sib2, iclass 11, count 2 2006.173.06:44:36.34#ibcon#*mode == 0, iclass 11, count 2 2006.173.06:44:36.34#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.06:44:36.34#ibcon#[25=AT07-04\r\n] 2006.173.06:44:36.34#ibcon#*before write, iclass 11, count 2 2006.173.06:44:36.34#ibcon#enter sib2, iclass 11, count 2 2006.173.06:44:36.34#ibcon#flushed, iclass 11, count 2 2006.173.06:44:36.34#ibcon#about to write, iclass 11, count 2 2006.173.06:44:36.34#ibcon#wrote, iclass 11, count 2 2006.173.06:44:36.34#ibcon#about to read 3, iclass 11, count 2 2006.173.06:44:36.37#ibcon#read 3, iclass 11, count 2 2006.173.06:44:36.37#ibcon#about to read 4, iclass 11, count 2 2006.173.06:44:36.37#ibcon#read 4, iclass 11, count 2 2006.173.06:44:36.37#ibcon#about to read 5, iclass 11, count 2 2006.173.06:44:36.37#ibcon#read 5, iclass 11, count 2 2006.173.06:44:36.37#ibcon#about to read 6, iclass 11, count 2 2006.173.06:44:36.37#ibcon#read 6, iclass 11, count 2 2006.173.06:44:36.37#ibcon#end of sib2, iclass 11, count 2 2006.173.06:44:36.37#ibcon#*after write, iclass 11, count 2 2006.173.06:44:36.37#ibcon#*before return 0, iclass 11, count 2 2006.173.06:44:36.37#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.06:44:36.37#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.06:44:36.37#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.06:44:36.37#ibcon#ireg 7 cls_cnt 0 2006.173.06:44:36.37#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.06:44:36.49#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.06:44:36.49#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.06:44:36.49#ibcon#enter wrdev, iclass 11, count 0 2006.173.06:44:36.49#ibcon#first serial, iclass 11, count 0 2006.173.06:44:36.49#ibcon#enter sib2, iclass 11, count 0 2006.173.06:44:36.49#ibcon#flushed, iclass 11, count 0 2006.173.06:44:36.49#ibcon#about to write, iclass 11, count 0 2006.173.06:44:36.49#ibcon#wrote, iclass 11, count 0 2006.173.06:44:36.49#ibcon#about to read 3, iclass 11, count 0 2006.173.06:44:36.51#ibcon#read 3, iclass 11, count 0 2006.173.06:44:36.51#ibcon#about to read 4, iclass 11, count 0 2006.173.06:44:36.51#ibcon#read 4, iclass 11, count 0 2006.173.06:44:36.51#ibcon#about to read 5, iclass 11, count 0 2006.173.06:44:36.51#ibcon#read 5, iclass 11, count 0 2006.173.06:44:36.51#ibcon#about to read 6, iclass 11, count 0 2006.173.06:44:36.51#ibcon#read 6, iclass 11, count 0 2006.173.06:44:36.51#ibcon#end of sib2, iclass 11, count 0 2006.173.06:44:36.51#ibcon#*mode == 0, iclass 11, count 0 2006.173.06:44:36.51#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.06:44:36.51#ibcon#[25=USB\r\n] 2006.173.06:44:36.51#ibcon#*before write, iclass 11, count 0 2006.173.06:44:36.51#ibcon#enter sib2, iclass 11, count 0 2006.173.06:44:36.51#ibcon#flushed, iclass 11, count 0 2006.173.06:44:36.51#ibcon#about to write, iclass 11, count 0 2006.173.06:44:36.51#ibcon#wrote, iclass 11, count 0 2006.173.06:44:36.51#ibcon#about to read 3, iclass 11, count 0 2006.173.06:44:36.54#ibcon#read 3, iclass 11, count 0 2006.173.06:44:36.54#ibcon#about to read 4, iclass 11, count 0 2006.173.06:44:36.54#ibcon#read 4, iclass 11, count 0 2006.173.06:44:36.54#ibcon#about to read 5, iclass 11, count 0 2006.173.06:44:36.54#ibcon#read 5, iclass 11, count 0 2006.173.06:44:36.54#ibcon#about to read 6, iclass 11, count 0 2006.173.06:44:36.54#ibcon#read 6, iclass 11, count 0 2006.173.06:44:36.54#ibcon#end of sib2, iclass 11, count 0 2006.173.06:44:36.54#ibcon#*after write, iclass 11, count 0 2006.173.06:44:36.54#ibcon#*before return 0, iclass 11, count 0 2006.173.06:44:36.54#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.06:44:36.54#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.06:44:36.54#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.06:44:36.54#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.06:44:36.54$vck44/valo=8,884.99 2006.173.06:44:36.54#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.06:44:36.54#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.06:44:36.54#ibcon#ireg 17 cls_cnt 0 2006.173.06:44:36.54#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.06:44:36.54#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.06:44:36.54#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.06:44:36.54#ibcon#enter wrdev, iclass 13, count 0 2006.173.06:44:36.54#ibcon#first serial, iclass 13, count 0 2006.173.06:44:36.54#ibcon#enter sib2, iclass 13, count 0 2006.173.06:44:36.54#ibcon#flushed, iclass 13, count 0 2006.173.06:44:36.54#ibcon#about to write, iclass 13, count 0 2006.173.06:44:36.54#ibcon#wrote, iclass 13, count 0 2006.173.06:44:36.54#ibcon#about to read 3, iclass 13, count 0 2006.173.06:44:36.56#ibcon#read 3, iclass 13, count 0 2006.173.06:44:36.56#ibcon#about to read 4, iclass 13, count 0 2006.173.06:44:36.56#ibcon#read 4, iclass 13, count 0 2006.173.06:44:36.56#ibcon#about to read 5, iclass 13, count 0 2006.173.06:44:36.56#ibcon#read 5, iclass 13, count 0 2006.173.06:44:36.56#ibcon#about to read 6, iclass 13, count 0 2006.173.06:44:36.56#ibcon#read 6, iclass 13, count 0 2006.173.06:44:36.56#ibcon#end of sib2, iclass 13, count 0 2006.173.06:44:36.56#ibcon#*mode == 0, iclass 13, count 0 2006.173.06:44:36.56#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.06:44:36.56#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.06:44:36.56#ibcon#*before write, iclass 13, count 0 2006.173.06:44:36.56#ibcon#enter sib2, iclass 13, count 0 2006.173.06:44:36.56#ibcon#flushed, iclass 13, count 0 2006.173.06:44:36.56#ibcon#about to write, iclass 13, count 0 2006.173.06:44:36.56#ibcon#wrote, iclass 13, count 0 2006.173.06:44:36.56#ibcon#about to read 3, iclass 13, count 0 2006.173.06:44:36.60#ibcon#read 3, iclass 13, count 0 2006.173.06:44:36.60#ibcon#about to read 4, iclass 13, count 0 2006.173.06:44:36.60#ibcon#read 4, iclass 13, count 0 2006.173.06:44:36.60#ibcon#about to read 5, iclass 13, count 0 2006.173.06:44:36.60#ibcon#read 5, iclass 13, count 0 2006.173.06:44:36.60#ibcon#about to read 6, iclass 13, count 0 2006.173.06:44:36.60#ibcon#read 6, iclass 13, count 0 2006.173.06:44:36.60#ibcon#end of sib2, iclass 13, count 0 2006.173.06:44:36.60#ibcon#*after write, iclass 13, count 0 2006.173.06:44:36.60#ibcon#*before return 0, iclass 13, count 0 2006.173.06:44:36.60#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.06:44:36.60#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.06:44:36.60#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.06:44:36.60#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.06:44:36.60$vck44/va=8,4 2006.173.06:44:36.60#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.06:44:36.60#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.06:44:36.60#ibcon#ireg 11 cls_cnt 2 2006.173.06:44:36.60#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.06:44:36.66#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.06:44:36.66#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.06:44:36.66#ibcon#enter wrdev, iclass 15, count 2 2006.173.06:44:36.66#ibcon#first serial, iclass 15, count 2 2006.173.06:44:36.66#ibcon#enter sib2, iclass 15, count 2 2006.173.06:44:36.66#ibcon#flushed, iclass 15, count 2 2006.173.06:44:36.66#ibcon#about to write, iclass 15, count 2 2006.173.06:44:36.66#ibcon#wrote, iclass 15, count 2 2006.173.06:44:36.66#ibcon#about to read 3, iclass 15, count 2 2006.173.06:44:36.68#ibcon#read 3, iclass 15, count 2 2006.173.06:44:36.68#ibcon#about to read 4, iclass 15, count 2 2006.173.06:44:36.68#ibcon#read 4, iclass 15, count 2 2006.173.06:44:36.68#ibcon#about to read 5, iclass 15, count 2 2006.173.06:44:36.68#ibcon#read 5, iclass 15, count 2 2006.173.06:44:36.68#ibcon#about to read 6, iclass 15, count 2 2006.173.06:44:36.68#ibcon#read 6, iclass 15, count 2 2006.173.06:44:36.68#ibcon#end of sib2, iclass 15, count 2 2006.173.06:44:36.68#ibcon#*mode == 0, iclass 15, count 2 2006.173.06:44:36.68#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.06:44:36.68#ibcon#[25=AT08-04\r\n] 2006.173.06:44:36.68#ibcon#*before write, iclass 15, count 2 2006.173.06:44:36.68#ibcon#enter sib2, iclass 15, count 2 2006.173.06:44:36.68#ibcon#flushed, iclass 15, count 2 2006.173.06:44:36.68#ibcon#about to write, iclass 15, count 2 2006.173.06:44:36.68#ibcon#wrote, iclass 15, count 2 2006.173.06:44:36.68#ibcon#about to read 3, iclass 15, count 2 2006.173.06:44:36.71#ibcon#read 3, iclass 15, count 2 2006.173.06:44:36.71#ibcon#about to read 4, iclass 15, count 2 2006.173.06:44:36.71#ibcon#read 4, iclass 15, count 2 2006.173.06:44:36.71#ibcon#about to read 5, iclass 15, count 2 2006.173.06:44:36.71#ibcon#read 5, iclass 15, count 2 2006.173.06:44:36.71#ibcon#about to read 6, iclass 15, count 2 2006.173.06:44:36.71#ibcon#read 6, iclass 15, count 2 2006.173.06:44:36.71#ibcon#end of sib2, iclass 15, count 2 2006.173.06:44:36.71#ibcon#*after write, iclass 15, count 2 2006.173.06:44:36.71#ibcon#*before return 0, iclass 15, count 2 2006.173.06:44:36.71#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.06:44:36.71#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.06:44:36.71#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.06:44:36.71#ibcon#ireg 7 cls_cnt 0 2006.173.06:44:36.71#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.06:44:36.83#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.06:44:36.83#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.06:44:36.83#ibcon#enter wrdev, iclass 15, count 0 2006.173.06:44:36.83#ibcon#first serial, iclass 15, count 0 2006.173.06:44:36.83#ibcon#enter sib2, iclass 15, count 0 2006.173.06:44:36.83#ibcon#flushed, iclass 15, count 0 2006.173.06:44:36.83#ibcon#about to write, iclass 15, count 0 2006.173.06:44:36.83#ibcon#wrote, iclass 15, count 0 2006.173.06:44:36.83#ibcon#about to read 3, iclass 15, count 0 2006.173.06:44:36.85#ibcon#read 3, iclass 15, count 0 2006.173.06:44:36.85#ibcon#about to read 4, iclass 15, count 0 2006.173.06:44:36.85#ibcon#read 4, iclass 15, count 0 2006.173.06:44:36.85#ibcon#about to read 5, iclass 15, count 0 2006.173.06:44:36.85#ibcon#read 5, iclass 15, count 0 2006.173.06:44:36.85#ibcon#about to read 6, iclass 15, count 0 2006.173.06:44:36.85#ibcon#read 6, iclass 15, count 0 2006.173.06:44:36.85#ibcon#end of sib2, iclass 15, count 0 2006.173.06:44:36.85#ibcon#*mode == 0, iclass 15, count 0 2006.173.06:44:36.85#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.06:44:36.85#ibcon#[25=USB\r\n] 2006.173.06:44:36.85#ibcon#*before write, iclass 15, count 0 2006.173.06:44:36.85#ibcon#enter sib2, iclass 15, count 0 2006.173.06:44:36.85#ibcon#flushed, iclass 15, count 0 2006.173.06:44:36.85#ibcon#about to write, iclass 15, count 0 2006.173.06:44:36.85#ibcon#wrote, iclass 15, count 0 2006.173.06:44:36.85#ibcon#about to read 3, iclass 15, count 0 2006.173.06:44:36.88#ibcon#read 3, iclass 15, count 0 2006.173.06:44:36.88#ibcon#about to read 4, iclass 15, count 0 2006.173.06:44:36.88#ibcon#read 4, iclass 15, count 0 2006.173.06:44:36.88#ibcon#about to read 5, iclass 15, count 0 2006.173.06:44:36.88#ibcon#read 5, iclass 15, count 0 2006.173.06:44:36.88#ibcon#about to read 6, iclass 15, count 0 2006.173.06:44:36.88#ibcon#read 6, iclass 15, count 0 2006.173.06:44:36.88#ibcon#end of sib2, iclass 15, count 0 2006.173.06:44:36.88#ibcon#*after write, iclass 15, count 0 2006.173.06:44:36.88#ibcon#*before return 0, iclass 15, count 0 2006.173.06:44:36.88#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.06:44:36.88#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.06:44:36.88#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.06:44:36.88#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.06:44:36.88$vck44/vblo=1,629.99 2006.173.06:44:36.88#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.06:44:36.88#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.06:44:36.88#ibcon#ireg 17 cls_cnt 0 2006.173.06:44:36.88#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.06:44:36.88#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.06:44:36.88#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.06:44:36.88#ibcon#enter wrdev, iclass 17, count 0 2006.173.06:44:36.88#ibcon#first serial, iclass 17, count 0 2006.173.06:44:36.88#ibcon#enter sib2, iclass 17, count 0 2006.173.06:44:36.88#ibcon#flushed, iclass 17, count 0 2006.173.06:44:36.88#ibcon#about to write, iclass 17, count 0 2006.173.06:44:36.88#ibcon#wrote, iclass 17, count 0 2006.173.06:44:36.88#ibcon#about to read 3, iclass 17, count 0 2006.173.06:44:36.90#ibcon#read 3, iclass 17, count 0 2006.173.06:44:36.90#ibcon#about to read 4, iclass 17, count 0 2006.173.06:44:36.90#ibcon#read 4, iclass 17, count 0 2006.173.06:44:36.90#ibcon#about to read 5, iclass 17, count 0 2006.173.06:44:36.90#ibcon#read 5, iclass 17, count 0 2006.173.06:44:36.90#ibcon#about to read 6, iclass 17, count 0 2006.173.06:44:36.90#ibcon#read 6, iclass 17, count 0 2006.173.06:44:36.90#ibcon#end of sib2, iclass 17, count 0 2006.173.06:44:36.90#ibcon#*mode == 0, iclass 17, count 0 2006.173.06:44:36.90#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.06:44:36.90#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.06:44:36.90#ibcon#*before write, iclass 17, count 0 2006.173.06:44:36.90#ibcon#enter sib2, iclass 17, count 0 2006.173.06:44:36.90#ibcon#flushed, iclass 17, count 0 2006.173.06:44:36.90#ibcon#about to write, iclass 17, count 0 2006.173.06:44:36.90#ibcon#wrote, iclass 17, count 0 2006.173.06:44:36.90#ibcon#about to read 3, iclass 17, count 0 2006.173.06:44:36.94#ibcon#read 3, iclass 17, count 0 2006.173.06:44:36.94#ibcon#about to read 4, iclass 17, count 0 2006.173.06:44:36.94#ibcon#read 4, iclass 17, count 0 2006.173.06:44:36.94#ibcon#about to read 5, iclass 17, count 0 2006.173.06:44:36.94#ibcon#read 5, iclass 17, count 0 2006.173.06:44:36.94#ibcon#about to read 6, iclass 17, count 0 2006.173.06:44:36.94#ibcon#read 6, iclass 17, count 0 2006.173.06:44:36.94#ibcon#end of sib2, iclass 17, count 0 2006.173.06:44:36.94#ibcon#*after write, iclass 17, count 0 2006.173.06:44:36.94#ibcon#*before return 0, iclass 17, count 0 2006.173.06:44:36.94#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.06:44:36.94#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.06:44:36.94#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.06:44:36.94#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.06:44:36.94$vck44/vb=1,4 2006.173.06:44:36.94#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.06:44:36.94#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.06:44:36.94#ibcon#ireg 11 cls_cnt 2 2006.173.06:44:36.94#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.06:44:36.94#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.06:44:36.94#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.06:44:36.94#ibcon#enter wrdev, iclass 19, count 2 2006.173.06:44:36.94#ibcon#first serial, iclass 19, count 2 2006.173.06:44:36.94#ibcon#enter sib2, iclass 19, count 2 2006.173.06:44:36.94#ibcon#flushed, iclass 19, count 2 2006.173.06:44:36.94#ibcon#about to write, iclass 19, count 2 2006.173.06:44:36.94#ibcon#wrote, iclass 19, count 2 2006.173.06:44:36.94#ibcon#about to read 3, iclass 19, count 2 2006.173.06:44:36.96#ibcon#read 3, iclass 19, count 2 2006.173.06:44:36.96#ibcon#about to read 4, iclass 19, count 2 2006.173.06:44:36.96#ibcon#read 4, iclass 19, count 2 2006.173.06:44:36.96#ibcon#about to read 5, iclass 19, count 2 2006.173.06:44:36.96#ibcon#read 5, iclass 19, count 2 2006.173.06:44:36.96#ibcon#about to read 6, iclass 19, count 2 2006.173.06:44:36.96#ibcon#read 6, iclass 19, count 2 2006.173.06:44:36.96#ibcon#end of sib2, iclass 19, count 2 2006.173.06:44:36.96#ibcon#*mode == 0, iclass 19, count 2 2006.173.06:44:36.96#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.06:44:36.96#ibcon#[27=AT01-04\r\n] 2006.173.06:44:36.96#ibcon#*before write, iclass 19, count 2 2006.173.06:44:36.96#ibcon#enter sib2, iclass 19, count 2 2006.173.06:44:36.96#ibcon#flushed, iclass 19, count 2 2006.173.06:44:36.96#ibcon#about to write, iclass 19, count 2 2006.173.06:44:36.96#ibcon#wrote, iclass 19, count 2 2006.173.06:44:36.96#ibcon#about to read 3, iclass 19, count 2 2006.173.06:44:36.99#ibcon#read 3, iclass 19, count 2 2006.173.06:44:36.99#ibcon#about to read 4, iclass 19, count 2 2006.173.06:44:36.99#ibcon#read 4, iclass 19, count 2 2006.173.06:44:36.99#ibcon#about to read 5, iclass 19, count 2 2006.173.06:44:36.99#ibcon#read 5, iclass 19, count 2 2006.173.06:44:36.99#ibcon#about to read 6, iclass 19, count 2 2006.173.06:44:36.99#ibcon#read 6, iclass 19, count 2 2006.173.06:44:36.99#ibcon#end of sib2, iclass 19, count 2 2006.173.06:44:36.99#ibcon#*after write, iclass 19, count 2 2006.173.06:44:36.99#ibcon#*before return 0, iclass 19, count 2 2006.173.06:44:36.99#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.06:44:36.99#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.06:44:36.99#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.06:44:36.99#ibcon#ireg 7 cls_cnt 0 2006.173.06:44:36.99#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.06:44:37.11#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.06:44:37.11#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.06:44:37.11#ibcon#enter wrdev, iclass 19, count 0 2006.173.06:44:37.11#ibcon#first serial, iclass 19, count 0 2006.173.06:44:37.11#ibcon#enter sib2, iclass 19, count 0 2006.173.06:44:37.11#ibcon#flushed, iclass 19, count 0 2006.173.06:44:37.11#ibcon#about to write, iclass 19, count 0 2006.173.06:44:37.11#ibcon#wrote, iclass 19, count 0 2006.173.06:44:37.11#ibcon#about to read 3, iclass 19, count 0 2006.173.06:44:37.13#ibcon#read 3, iclass 19, count 0 2006.173.06:44:37.13#ibcon#about to read 4, iclass 19, count 0 2006.173.06:44:37.13#ibcon#read 4, iclass 19, count 0 2006.173.06:44:37.13#ibcon#about to read 5, iclass 19, count 0 2006.173.06:44:37.13#ibcon#read 5, iclass 19, count 0 2006.173.06:44:37.13#ibcon#about to read 6, iclass 19, count 0 2006.173.06:44:37.13#ibcon#read 6, iclass 19, count 0 2006.173.06:44:37.13#ibcon#end of sib2, iclass 19, count 0 2006.173.06:44:37.13#ibcon#*mode == 0, iclass 19, count 0 2006.173.06:44:37.13#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.06:44:37.13#ibcon#[27=USB\r\n] 2006.173.06:44:37.13#ibcon#*before write, iclass 19, count 0 2006.173.06:44:37.13#ibcon#enter sib2, iclass 19, count 0 2006.173.06:44:37.13#ibcon#flushed, iclass 19, count 0 2006.173.06:44:37.13#ibcon#about to write, iclass 19, count 0 2006.173.06:44:37.13#ibcon#wrote, iclass 19, count 0 2006.173.06:44:37.13#ibcon#about to read 3, iclass 19, count 0 2006.173.06:44:37.16#ibcon#read 3, iclass 19, count 0 2006.173.06:44:37.16#ibcon#about to read 4, iclass 19, count 0 2006.173.06:44:37.16#ibcon#read 4, iclass 19, count 0 2006.173.06:44:37.16#ibcon#about to read 5, iclass 19, count 0 2006.173.06:44:37.16#ibcon#read 5, iclass 19, count 0 2006.173.06:44:37.16#ibcon#about to read 6, iclass 19, count 0 2006.173.06:44:37.16#ibcon#read 6, iclass 19, count 0 2006.173.06:44:37.16#ibcon#end of sib2, iclass 19, count 0 2006.173.06:44:37.16#ibcon#*after write, iclass 19, count 0 2006.173.06:44:37.16#ibcon#*before return 0, iclass 19, count 0 2006.173.06:44:37.16#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.06:44:37.16#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.06:44:37.16#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.06:44:37.16#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.06:44:37.16$vck44/vblo=2,634.99 2006.173.06:44:37.16#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.06:44:37.16#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.06:44:37.16#ibcon#ireg 17 cls_cnt 0 2006.173.06:44:37.16#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.06:44:37.16#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.06:44:37.16#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.06:44:37.16#ibcon#enter wrdev, iclass 21, count 0 2006.173.06:44:37.16#ibcon#first serial, iclass 21, count 0 2006.173.06:44:37.16#ibcon#enter sib2, iclass 21, count 0 2006.173.06:44:37.16#ibcon#flushed, iclass 21, count 0 2006.173.06:44:37.16#ibcon#about to write, iclass 21, count 0 2006.173.06:44:37.16#ibcon#wrote, iclass 21, count 0 2006.173.06:44:37.16#ibcon#about to read 3, iclass 21, count 0 2006.173.06:44:37.18#ibcon#read 3, iclass 21, count 0 2006.173.06:44:37.18#ibcon#about to read 4, iclass 21, count 0 2006.173.06:44:37.18#ibcon#read 4, iclass 21, count 0 2006.173.06:44:37.18#ibcon#about to read 5, iclass 21, count 0 2006.173.06:44:37.18#ibcon#read 5, iclass 21, count 0 2006.173.06:44:37.18#ibcon#about to read 6, iclass 21, count 0 2006.173.06:44:37.18#ibcon#read 6, iclass 21, count 0 2006.173.06:44:37.18#ibcon#end of sib2, iclass 21, count 0 2006.173.06:44:37.18#ibcon#*mode == 0, iclass 21, count 0 2006.173.06:44:37.18#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.06:44:37.18#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.06:44:37.18#ibcon#*before write, iclass 21, count 0 2006.173.06:44:37.18#ibcon#enter sib2, iclass 21, count 0 2006.173.06:44:37.18#ibcon#flushed, iclass 21, count 0 2006.173.06:44:37.18#ibcon#about to write, iclass 21, count 0 2006.173.06:44:37.18#ibcon#wrote, iclass 21, count 0 2006.173.06:44:37.18#ibcon#about to read 3, iclass 21, count 0 2006.173.06:44:37.22#ibcon#read 3, iclass 21, count 0 2006.173.06:44:37.22#ibcon#about to read 4, iclass 21, count 0 2006.173.06:44:37.22#ibcon#read 4, iclass 21, count 0 2006.173.06:44:37.22#ibcon#about to read 5, iclass 21, count 0 2006.173.06:44:37.22#ibcon#read 5, iclass 21, count 0 2006.173.06:44:37.22#ibcon#about to read 6, iclass 21, count 0 2006.173.06:44:37.22#ibcon#read 6, iclass 21, count 0 2006.173.06:44:37.22#ibcon#end of sib2, iclass 21, count 0 2006.173.06:44:37.22#ibcon#*after write, iclass 21, count 0 2006.173.06:44:37.22#ibcon#*before return 0, iclass 21, count 0 2006.173.06:44:37.22#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.06:44:37.22#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.06:44:37.22#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.06:44:37.22#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.06:44:37.22$vck44/vb=2,4 2006.173.06:44:37.22#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.06:44:37.22#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.06:44:37.22#ibcon#ireg 11 cls_cnt 2 2006.173.06:44:37.22#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.06:44:37.28#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.06:44:37.28#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.06:44:37.28#ibcon#enter wrdev, iclass 23, count 2 2006.173.06:44:37.28#ibcon#first serial, iclass 23, count 2 2006.173.06:44:37.28#ibcon#enter sib2, iclass 23, count 2 2006.173.06:44:37.28#ibcon#flushed, iclass 23, count 2 2006.173.06:44:37.28#ibcon#about to write, iclass 23, count 2 2006.173.06:44:37.28#ibcon#wrote, iclass 23, count 2 2006.173.06:44:37.28#ibcon#about to read 3, iclass 23, count 2 2006.173.06:44:37.30#ibcon#read 3, iclass 23, count 2 2006.173.06:44:37.30#ibcon#about to read 4, iclass 23, count 2 2006.173.06:44:37.30#ibcon#read 4, iclass 23, count 2 2006.173.06:44:37.30#ibcon#about to read 5, iclass 23, count 2 2006.173.06:44:37.30#ibcon#read 5, iclass 23, count 2 2006.173.06:44:37.30#ibcon#about to read 6, iclass 23, count 2 2006.173.06:44:37.30#ibcon#read 6, iclass 23, count 2 2006.173.06:44:37.30#ibcon#end of sib2, iclass 23, count 2 2006.173.06:44:37.30#ibcon#*mode == 0, iclass 23, count 2 2006.173.06:44:37.30#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.06:44:37.30#ibcon#[27=AT02-04\r\n] 2006.173.06:44:37.30#ibcon#*before write, iclass 23, count 2 2006.173.06:44:37.30#ibcon#enter sib2, iclass 23, count 2 2006.173.06:44:37.30#ibcon#flushed, iclass 23, count 2 2006.173.06:44:37.30#ibcon#about to write, iclass 23, count 2 2006.173.06:44:37.30#ibcon#wrote, iclass 23, count 2 2006.173.06:44:37.30#ibcon#about to read 3, iclass 23, count 2 2006.173.06:44:37.33#ibcon#read 3, iclass 23, count 2 2006.173.06:44:37.33#ibcon#about to read 4, iclass 23, count 2 2006.173.06:44:37.33#ibcon#read 4, iclass 23, count 2 2006.173.06:44:37.33#ibcon#about to read 5, iclass 23, count 2 2006.173.06:44:37.33#ibcon#read 5, iclass 23, count 2 2006.173.06:44:37.33#ibcon#about to read 6, iclass 23, count 2 2006.173.06:44:37.33#ibcon#read 6, iclass 23, count 2 2006.173.06:44:37.33#ibcon#end of sib2, iclass 23, count 2 2006.173.06:44:37.33#ibcon#*after write, iclass 23, count 2 2006.173.06:44:37.33#ibcon#*before return 0, iclass 23, count 2 2006.173.06:44:37.33#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.06:44:37.33#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.06:44:37.33#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.06:44:37.33#ibcon#ireg 7 cls_cnt 0 2006.173.06:44:37.33#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.06:44:37.45#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.06:44:37.45#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.06:44:37.45#ibcon#enter wrdev, iclass 23, count 0 2006.173.06:44:37.45#ibcon#first serial, iclass 23, count 0 2006.173.06:44:37.45#ibcon#enter sib2, iclass 23, count 0 2006.173.06:44:37.45#ibcon#flushed, iclass 23, count 0 2006.173.06:44:37.45#ibcon#about to write, iclass 23, count 0 2006.173.06:44:37.45#ibcon#wrote, iclass 23, count 0 2006.173.06:44:37.45#ibcon#about to read 3, iclass 23, count 0 2006.173.06:44:37.47#ibcon#read 3, iclass 23, count 0 2006.173.06:44:37.47#ibcon#about to read 4, iclass 23, count 0 2006.173.06:44:37.47#ibcon#read 4, iclass 23, count 0 2006.173.06:44:37.47#ibcon#about to read 5, iclass 23, count 0 2006.173.06:44:37.47#ibcon#read 5, iclass 23, count 0 2006.173.06:44:37.47#ibcon#about to read 6, iclass 23, count 0 2006.173.06:44:37.47#ibcon#read 6, iclass 23, count 0 2006.173.06:44:37.47#ibcon#end of sib2, iclass 23, count 0 2006.173.06:44:37.47#ibcon#*mode == 0, iclass 23, count 0 2006.173.06:44:37.47#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.06:44:37.47#ibcon#[27=USB\r\n] 2006.173.06:44:37.47#ibcon#*before write, iclass 23, count 0 2006.173.06:44:37.47#ibcon#enter sib2, iclass 23, count 0 2006.173.06:44:37.47#ibcon#flushed, iclass 23, count 0 2006.173.06:44:37.47#ibcon#about to write, iclass 23, count 0 2006.173.06:44:37.47#ibcon#wrote, iclass 23, count 0 2006.173.06:44:37.47#ibcon#about to read 3, iclass 23, count 0 2006.173.06:44:37.50#ibcon#read 3, iclass 23, count 0 2006.173.06:44:37.50#ibcon#about to read 4, iclass 23, count 0 2006.173.06:44:37.50#ibcon#read 4, iclass 23, count 0 2006.173.06:44:37.50#ibcon#about to read 5, iclass 23, count 0 2006.173.06:44:37.50#ibcon#read 5, iclass 23, count 0 2006.173.06:44:37.50#ibcon#about to read 6, iclass 23, count 0 2006.173.06:44:37.50#ibcon#read 6, iclass 23, count 0 2006.173.06:44:37.50#ibcon#end of sib2, iclass 23, count 0 2006.173.06:44:37.50#ibcon#*after write, iclass 23, count 0 2006.173.06:44:37.50#ibcon#*before return 0, iclass 23, count 0 2006.173.06:44:37.50#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.06:44:37.50#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.06:44:37.50#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.06:44:37.50#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.06:44:37.50$vck44/vblo=3,649.99 2006.173.06:44:37.50#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.06:44:37.50#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.06:44:37.50#ibcon#ireg 17 cls_cnt 0 2006.173.06:44:37.50#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.06:44:37.50#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.06:44:37.50#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.06:44:37.50#ibcon#enter wrdev, iclass 25, count 0 2006.173.06:44:37.50#ibcon#first serial, iclass 25, count 0 2006.173.06:44:37.50#ibcon#enter sib2, iclass 25, count 0 2006.173.06:44:37.50#ibcon#flushed, iclass 25, count 0 2006.173.06:44:37.50#ibcon#about to write, iclass 25, count 0 2006.173.06:44:37.50#ibcon#wrote, iclass 25, count 0 2006.173.06:44:37.50#ibcon#about to read 3, iclass 25, count 0 2006.173.06:44:37.52#ibcon#read 3, iclass 25, count 0 2006.173.06:44:37.52#ibcon#about to read 4, iclass 25, count 0 2006.173.06:44:37.52#ibcon#read 4, iclass 25, count 0 2006.173.06:44:37.52#ibcon#about to read 5, iclass 25, count 0 2006.173.06:44:37.52#ibcon#read 5, iclass 25, count 0 2006.173.06:44:37.52#ibcon#about to read 6, iclass 25, count 0 2006.173.06:44:37.52#ibcon#read 6, iclass 25, count 0 2006.173.06:44:37.52#ibcon#end of sib2, iclass 25, count 0 2006.173.06:44:37.52#ibcon#*mode == 0, iclass 25, count 0 2006.173.06:44:37.52#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.06:44:37.52#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.06:44:37.52#ibcon#*before write, iclass 25, count 0 2006.173.06:44:37.52#ibcon#enter sib2, iclass 25, count 0 2006.173.06:44:37.52#ibcon#flushed, iclass 25, count 0 2006.173.06:44:37.52#ibcon#about to write, iclass 25, count 0 2006.173.06:44:37.52#ibcon#wrote, iclass 25, count 0 2006.173.06:44:37.52#ibcon#about to read 3, iclass 25, count 0 2006.173.06:44:37.56#ibcon#read 3, iclass 25, count 0 2006.173.06:44:37.56#ibcon#about to read 4, iclass 25, count 0 2006.173.06:44:37.56#ibcon#read 4, iclass 25, count 0 2006.173.06:44:37.56#ibcon#about to read 5, iclass 25, count 0 2006.173.06:44:37.56#ibcon#read 5, iclass 25, count 0 2006.173.06:44:37.56#ibcon#about to read 6, iclass 25, count 0 2006.173.06:44:37.56#ibcon#read 6, iclass 25, count 0 2006.173.06:44:37.56#ibcon#end of sib2, iclass 25, count 0 2006.173.06:44:37.56#ibcon#*after write, iclass 25, count 0 2006.173.06:44:37.56#ibcon#*before return 0, iclass 25, count 0 2006.173.06:44:37.56#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.06:44:37.56#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.06:44:37.56#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.06:44:37.56#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.06:44:37.56$vck44/vb=3,4 2006.173.06:44:37.56#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.06:44:37.56#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.06:44:37.56#ibcon#ireg 11 cls_cnt 2 2006.173.06:44:37.56#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.06:44:37.62#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.06:44:37.62#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.06:44:37.62#ibcon#enter wrdev, iclass 27, count 2 2006.173.06:44:37.62#ibcon#first serial, iclass 27, count 2 2006.173.06:44:37.62#ibcon#enter sib2, iclass 27, count 2 2006.173.06:44:37.62#ibcon#flushed, iclass 27, count 2 2006.173.06:44:37.62#ibcon#about to write, iclass 27, count 2 2006.173.06:44:37.62#ibcon#wrote, iclass 27, count 2 2006.173.06:44:37.62#ibcon#about to read 3, iclass 27, count 2 2006.173.06:44:37.64#ibcon#read 3, iclass 27, count 2 2006.173.06:44:37.64#ibcon#about to read 4, iclass 27, count 2 2006.173.06:44:37.64#ibcon#read 4, iclass 27, count 2 2006.173.06:44:37.64#ibcon#about to read 5, iclass 27, count 2 2006.173.06:44:37.64#ibcon#read 5, iclass 27, count 2 2006.173.06:44:37.64#ibcon#about to read 6, iclass 27, count 2 2006.173.06:44:37.64#ibcon#read 6, iclass 27, count 2 2006.173.06:44:37.64#ibcon#end of sib2, iclass 27, count 2 2006.173.06:44:37.64#ibcon#*mode == 0, iclass 27, count 2 2006.173.06:44:37.64#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.06:44:37.64#ibcon#[27=AT03-04\r\n] 2006.173.06:44:37.64#ibcon#*before write, iclass 27, count 2 2006.173.06:44:37.64#ibcon#enter sib2, iclass 27, count 2 2006.173.06:44:37.64#ibcon#flushed, iclass 27, count 2 2006.173.06:44:37.64#ibcon#about to write, iclass 27, count 2 2006.173.06:44:37.64#ibcon#wrote, iclass 27, count 2 2006.173.06:44:37.64#ibcon#about to read 3, iclass 27, count 2 2006.173.06:44:37.67#ibcon#read 3, iclass 27, count 2 2006.173.06:44:37.67#ibcon#about to read 4, iclass 27, count 2 2006.173.06:44:37.67#ibcon#read 4, iclass 27, count 2 2006.173.06:44:37.67#ibcon#about to read 5, iclass 27, count 2 2006.173.06:44:37.67#ibcon#read 5, iclass 27, count 2 2006.173.06:44:37.67#ibcon#about to read 6, iclass 27, count 2 2006.173.06:44:37.67#ibcon#read 6, iclass 27, count 2 2006.173.06:44:37.67#ibcon#end of sib2, iclass 27, count 2 2006.173.06:44:37.67#ibcon#*after write, iclass 27, count 2 2006.173.06:44:37.67#ibcon#*before return 0, iclass 27, count 2 2006.173.06:44:37.67#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.06:44:37.67#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.06:44:37.67#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.06:44:37.67#ibcon#ireg 7 cls_cnt 0 2006.173.06:44:37.67#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.06:44:37.79#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.06:44:37.79#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.06:44:37.79#ibcon#enter wrdev, iclass 27, count 0 2006.173.06:44:37.79#ibcon#first serial, iclass 27, count 0 2006.173.06:44:37.79#ibcon#enter sib2, iclass 27, count 0 2006.173.06:44:37.79#ibcon#flushed, iclass 27, count 0 2006.173.06:44:37.79#ibcon#about to write, iclass 27, count 0 2006.173.06:44:37.79#ibcon#wrote, iclass 27, count 0 2006.173.06:44:37.79#ibcon#about to read 3, iclass 27, count 0 2006.173.06:44:37.81#ibcon#read 3, iclass 27, count 0 2006.173.06:44:37.81#ibcon#about to read 4, iclass 27, count 0 2006.173.06:44:37.81#ibcon#read 4, iclass 27, count 0 2006.173.06:44:37.81#ibcon#about to read 5, iclass 27, count 0 2006.173.06:44:37.81#ibcon#read 5, iclass 27, count 0 2006.173.06:44:37.81#ibcon#about to read 6, iclass 27, count 0 2006.173.06:44:37.81#ibcon#read 6, iclass 27, count 0 2006.173.06:44:37.81#ibcon#end of sib2, iclass 27, count 0 2006.173.06:44:37.81#ibcon#*mode == 0, iclass 27, count 0 2006.173.06:44:37.81#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.06:44:37.81#ibcon#[27=USB\r\n] 2006.173.06:44:37.81#ibcon#*before write, iclass 27, count 0 2006.173.06:44:37.81#ibcon#enter sib2, iclass 27, count 0 2006.173.06:44:37.81#ibcon#flushed, iclass 27, count 0 2006.173.06:44:37.81#ibcon#about to write, iclass 27, count 0 2006.173.06:44:37.81#ibcon#wrote, iclass 27, count 0 2006.173.06:44:37.81#ibcon#about to read 3, iclass 27, count 0 2006.173.06:44:37.84#ibcon#read 3, iclass 27, count 0 2006.173.06:44:37.84#ibcon#about to read 4, iclass 27, count 0 2006.173.06:44:37.84#ibcon#read 4, iclass 27, count 0 2006.173.06:44:37.84#ibcon#about to read 5, iclass 27, count 0 2006.173.06:44:37.84#ibcon#read 5, iclass 27, count 0 2006.173.06:44:37.84#ibcon#about to read 6, iclass 27, count 0 2006.173.06:44:37.84#ibcon#read 6, iclass 27, count 0 2006.173.06:44:37.84#ibcon#end of sib2, iclass 27, count 0 2006.173.06:44:37.84#ibcon#*after write, iclass 27, count 0 2006.173.06:44:37.84#ibcon#*before return 0, iclass 27, count 0 2006.173.06:44:37.84#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.06:44:37.84#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.06:44:37.84#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.06:44:37.84#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.06:44:37.84$vck44/vblo=4,679.99 2006.173.06:44:37.84#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.06:44:37.84#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.06:44:37.84#ibcon#ireg 17 cls_cnt 0 2006.173.06:44:37.84#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.06:44:37.84#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.06:44:37.84#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.06:44:37.84#ibcon#enter wrdev, iclass 29, count 0 2006.173.06:44:37.84#ibcon#first serial, iclass 29, count 0 2006.173.06:44:37.84#ibcon#enter sib2, iclass 29, count 0 2006.173.06:44:37.84#ibcon#flushed, iclass 29, count 0 2006.173.06:44:37.84#ibcon#about to write, iclass 29, count 0 2006.173.06:44:37.84#ibcon#wrote, iclass 29, count 0 2006.173.06:44:37.84#ibcon#about to read 3, iclass 29, count 0 2006.173.06:44:37.86#ibcon#read 3, iclass 29, count 0 2006.173.06:44:37.86#ibcon#about to read 4, iclass 29, count 0 2006.173.06:44:37.86#ibcon#read 4, iclass 29, count 0 2006.173.06:44:37.86#ibcon#about to read 5, iclass 29, count 0 2006.173.06:44:37.86#ibcon#read 5, iclass 29, count 0 2006.173.06:44:37.86#ibcon#about to read 6, iclass 29, count 0 2006.173.06:44:37.86#ibcon#read 6, iclass 29, count 0 2006.173.06:44:37.86#ibcon#end of sib2, iclass 29, count 0 2006.173.06:44:37.86#ibcon#*mode == 0, iclass 29, count 0 2006.173.06:44:37.86#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.06:44:37.86#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.06:44:37.86#ibcon#*before write, iclass 29, count 0 2006.173.06:44:37.86#ibcon#enter sib2, iclass 29, count 0 2006.173.06:44:37.86#ibcon#flushed, iclass 29, count 0 2006.173.06:44:37.86#ibcon#about to write, iclass 29, count 0 2006.173.06:44:37.86#ibcon#wrote, iclass 29, count 0 2006.173.06:44:37.86#ibcon#about to read 3, iclass 29, count 0 2006.173.06:44:37.90#ibcon#read 3, iclass 29, count 0 2006.173.06:44:37.90#ibcon#about to read 4, iclass 29, count 0 2006.173.06:44:37.90#ibcon#read 4, iclass 29, count 0 2006.173.06:44:37.90#ibcon#about to read 5, iclass 29, count 0 2006.173.06:44:37.90#ibcon#read 5, iclass 29, count 0 2006.173.06:44:37.90#ibcon#about to read 6, iclass 29, count 0 2006.173.06:44:37.90#ibcon#read 6, iclass 29, count 0 2006.173.06:44:37.90#ibcon#end of sib2, iclass 29, count 0 2006.173.06:44:37.90#ibcon#*after write, iclass 29, count 0 2006.173.06:44:37.90#ibcon#*before return 0, iclass 29, count 0 2006.173.06:44:37.90#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.06:44:37.90#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.06:44:37.90#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.06:44:37.90#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.06:44:37.90$vck44/vb=4,4 2006.173.06:44:37.90#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.06:44:37.90#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.06:44:37.90#ibcon#ireg 11 cls_cnt 2 2006.173.06:44:37.90#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.06:44:37.96#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.06:44:37.96#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.06:44:37.96#ibcon#enter wrdev, iclass 31, count 2 2006.173.06:44:37.96#ibcon#first serial, iclass 31, count 2 2006.173.06:44:37.96#ibcon#enter sib2, iclass 31, count 2 2006.173.06:44:37.96#ibcon#flushed, iclass 31, count 2 2006.173.06:44:37.96#ibcon#about to write, iclass 31, count 2 2006.173.06:44:37.96#ibcon#wrote, iclass 31, count 2 2006.173.06:44:37.96#ibcon#about to read 3, iclass 31, count 2 2006.173.06:44:37.98#ibcon#read 3, iclass 31, count 2 2006.173.06:44:37.98#ibcon#about to read 4, iclass 31, count 2 2006.173.06:44:37.98#ibcon#read 4, iclass 31, count 2 2006.173.06:44:37.98#ibcon#about to read 5, iclass 31, count 2 2006.173.06:44:37.98#ibcon#read 5, iclass 31, count 2 2006.173.06:44:37.98#ibcon#about to read 6, iclass 31, count 2 2006.173.06:44:37.98#ibcon#read 6, iclass 31, count 2 2006.173.06:44:37.98#ibcon#end of sib2, iclass 31, count 2 2006.173.06:44:37.98#ibcon#*mode == 0, iclass 31, count 2 2006.173.06:44:37.98#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.06:44:37.98#ibcon#[27=AT04-04\r\n] 2006.173.06:44:37.98#ibcon#*before write, iclass 31, count 2 2006.173.06:44:37.98#ibcon#enter sib2, iclass 31, count 2 2006.173.06:44:37.98#ibcon#flushed, iclass 31, count 2 2006.173.06:44:37.98#ibcon#about to write, iclass 31, count 2 2006.173.06:44:37.98#ibcon#wrote, iclass 31, count 2 2006.173.06:44:37.98#ibcon#about to read 3, iclass 31, count 2 2006.173.06:44:38.01#ibcon#read 3, iclass 31, count 2 2006.173.06:44:38.01#ibcon#about to read 4, iclass 31, count 2 2006.173.06:44:38.01#ibcon#read 4, iclass 31, count 2 2006.173.06:44:38.01#ibcon#about to read 5, iclass 31, count 2 2006.173.06:44:38.01#ibcon#read 5, iclass 31, count 2 2006.173.06:44:38.01#ibcon#about to read 6, iclass 31, count 2 2006.173.06:44:38.01#ibcon#read 6, iclass 31, count 2 2006.173.06:44:38.01#ibcon#end of sib2, iclass 31, count 2 2006.173.06:44:38.01#ibcon#*after write, iclass 31, count 2 2006.173.06:44:38.01#ibcon#*before return 0, iclass 31, count 2 2006.173.06:44:38.01#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.06:44:38.01#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.06:44:38.01#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.06:44:38.01#ibcon#ireg 7 cls_cnt 0 2006.173.06:44:38.01#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.06:44:38.13#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.06:44:38.13#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.06:44:38.13#ibcon#enter wrdev, iclass 31, count 0 2006.173.06:44:38.13#ibcon#first serial, iclass 31, count 0 2006.173.06:44:38.13#ibcon#enter sib2, iclass 31, count 0 2006.173.06:44:38.13#ibcon#flushed, iclass 31, count 0 2006.173.06:44:38.13#ibcon#about to write, iclass 31, count 0 2006.173.06:44:38.13#ibcon#wrote, iclass 31, count 0 2006.173.06:44:38.13#ibcon#about to read 3, iclass 31, count 0 2006.173.06:44:38.15#ibcon#read 3, iclass 31, count 0 2006.173.06:44:38.15#ibcon#about to read 4, iclass 31, count 0 2006.173.06:44:38.15#ibcon#read 4, iclass 31, count 0 2006.173.06:44:38.15#ibcon#about to read 5, iclass 31, count 0 2006.173.06:44:38.15#ibcon#read 5, iclass 31, count 0 2006.173.06:44:38.15#ibcon#about to read 6, iclass 31, count 0 2006.173.06:44:38.15#ibcon#read 6, iclass 31, count 0 2006.173.06:44:38.15#ibcon#end of sib2, iclass 31, count 0 2006.173.06:44:38.15#ibcon#*mode == 0, iclass 31, count 0 2006.173.06:44:38.15#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.06:44:38.15#ibcon#[27=USB\r\n] 2006.173.06:44:38.15#ibcon#*before write, iclass 31, count 0 2006.173.06:44:38.15#ibcon#enter sib2, iclass 31, count 0 2006.173.06:44:38.15#ibcon#flushed, iclass 31, count 0 2006.173.06:44:38.15#ibcon#about to write, iclass 31, count 0 2006.173.06:44:38.15#ibcon#wrote, iclass 31, count 0 2006.173.06:44:38.15#ibcon#about to read 3, iclass 31, count 0 2006.173.06:44:38.18#ibcon#read 3, iclass 31, count 0 2006.173.06:44:38.18#ibcon#about to read 4, iclass 31, count 0 2006.173.06:44:38.18#ibcon#read 4, iclass 31, count 0 2006.173.06:44:38.18#ibcon#about to read 5, iclass 31, count 0 2006.173.06:44:38.18#ibcon#read 5, iclass 31, count 0 2006.173.06:44:38.18#ibcon#about to read 6, iclass 31, count 0 2006.173.06:44:38.18#ibcon#read 6, iclass 31, count 0 2006.173.06:44:38.18#ibcon#end of sib2, iclass 31, count 0 2006.173.06:44:38.18#ibcon#*after write, iclass 31, count 0 2006.173.06:44:38.18#ibcon#*before return 0, iclass 31, count 0 2006.173.06:44:38.18#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.06:44:38.18#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.06:44:38.18#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.06:44:38.18#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.06:44:38.18$vck44/vblo=5,709.99 2006.173.06:44:38.18#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.06:44:38.18#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.06:44:38.18#ibcon#ireg 17 cls_cnt 0 2006.173.06:44:38.18#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.06:44:38.18#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.06:44:38.18#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.06:44:38.18#ibcon#enter wrdev, iclass 33, count 0 2006.173.06:44:38.18#ibcon#first serial, iclass 33, count 0 2006.173.06:44:38.18#ibcon#enter sib2, iclass 33, count 0 2006.173.06:44:38.18#ibcon#flushed, iclass 33, count 0 2006.173.06:44:38.18#ibcon#about to write, iclass 33, count 0 2006.173.06:44:38.18#ibcon#wrote, iclass 33, count 0 2006.173.06:44:38.18#ibcon#about to read 3, iclass 33, count 0 2006.173.06:44:38.20#ibcon#read 3, iclass 33, count 0 2006.173.06:44:38.20#ibcon#about to read 4, iclass 33, count 0 2006.173.06:44:38.20#ibcon#read 4, iclass 33, count 0 2006.173.06:44:38.20#ibcon#about to read 5, iclass 33, count 0 2006.173.06:44:38.20#ibcon#read 5, iclass 33, count 0 2006.173.06:44:38.20#ibcon#about to read 6, iclass 33, count 0 2006.173.06:44:38.20#ibcon#read 6, iclass 33, count 0 2006.173.06:44:38.20#ibcon#end of sib2, iclass 33, count 0 2006.173.06:44:38.20#ibcon#*mode == 0, iclass 33, count 0 2006.173.06:44:38.20#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.06:44:38.20#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.06:44:38.20#ibcon#*before write, iclass 33, count 0 2006.173.06:44:38.20#ibcon#enter sib2, iclass 33, count 0 2006.173.06:44:38.20#ibcon#flushed, iclass 33, count 0 2006.173.06:44:38.20#ibcon#about to write, iclass 33, count 0 2006.173.06:44:38.20#ibcon#wrote, iclass 33, count 0 2006.173.06:44:38.20#ibcon#about to read 3, iclass 33, count 0 2006.173.06:44:38.24#ibcon#read 3, iclass 33, count 0 2006.173.06:44:38.24#ibcon#about to read 4, iclass 33, count 0 2006.173.06:44:38.24#ibcon#read 4, iclass 33, count 0 2006.173.06:44:38.24#ibcon#about to read 5, iclass 33, count 0 2006.173.06:44:38.24#ibcon#read 5, iclass 33, count 0 2006.173.06:44:38.24#ibcon#about to read 6, iclass 33, count 0 2006.173.06:44:38.24#ibcon#read 6, iclass 33, count 0 2006.173.06:44:38.24#ibcon#end of sib2, iclass 33, count 0 2006.173.06:44:38.24#ibcon#*after write, iclass 33, count 0 2006.173.06:44:38.24#ibcon#*before return 0, iclass 33, count 0 2006.173.06:44:38.24#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.06:44:38.24#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.06:44:38.24#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.06:44:38.24#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.06:44:38.24$vck44/vb=5,4 2006.173.06:44:38.24#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.06:44:38.24#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.06:44:38.24#ibcon#ireg 11 cls_cnt 2 2006.173.06:44:38.24#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.06:44:38.30#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.06:44:38.30#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.06:44:38.30#ibcon#enter wrdev, iclass 35, count 2 2006.173.06:44:38.30#ibcon#first serial, iclass 35, count 2 2006.173.06:44:38.30#ibcon#enter sib2, iclass 35, count 2 2006.173.06:44:38.30#ibcon#flushed, iclass 35, count 2 2006.173.06:44:38.30#ibcon#about to write, iclass 35, count 2 2006.173.06:44:38.30#ibcon#wrote, iclass 35, count 2 2006.173.06:44:38.30#ibcon#about to read 3, iclass 35, count 2 2006.173.06:44:38.32#ibcon#read 3, iclass 35, count 2 2006.173.06:44:38.32#ibcon#about to read 4, iclass 35, count 2 2006.173.06:44:38.32#ibcon#read 4, iclass 35, count 2 2006.173.06:44:38.32#ibcon#about to read 5, iclass 35, count 2 2006.173.06:44:38.32#ibcon#read 5, iclass 35, count 2 2006.173.06:44:38.32#ibcon#about to read 6, iclass 35, count 2 2006.173.06:44:38.32#ibcon#read 6, iclass 35, count 2 2006.173.06:44:38.32#ibcon#end of sib2, iclass 35, count 2 2006.173.06:44:38.32#ibcon#*mode == 0, iclass 35, count 2 2006.173.06:44:38.32#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.06:44:38.32#ibcon#[27=AT05-04\r\n] 2006.173.06:44:38.32#ibcon#*before write, iclass 35, count 2 2006.173.06:44:38.32#ibcon#enter sib2, iclass 35, count 2 2006.173.06:44:38.32#ibcon#flushed, iclass 35, count 2 2006.173.06:44:38.32#ibcon#about to write, iclass 35, count 2 2006.173.06:44:38.32#ibcon#wrote, iclass 35, count 2 2006.173.06:44:38.32#ibcon#about to read 3, iclass 35, count 2 2006.173.06:44:38.35#ibcon#read 3, iclass 35, count 2 2006.173.06:44:38.35#ibcon#about to read 4, iclass 35, count 2 2006.173.06:44:38.35#ibcon#read 4, iclass 35, count 2 2006.173.06:44:38.35#ibcon#about to read 5, iclass 35, count 2 2006.173.06:44:38.35#ibcon#read 5, iclass 35, count 2 2006.173.06:44:38.35#ibcon#about to read 6, iclass 35, count 2 2006.173.06:44:38.35#ibcon#read 6, iclass 35, count 2 2006.173.06:44:38.35#ibcon#end of sib2, iclass 35, count 2 2006.173.06:44:38.35#ibcon#*after write, iclass 35, count 2 2006.173.06:44:38.35#ibcon#*before return 0, iclass 35, count 2 2006.173.06:44:38.35#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.06:44:38.35#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.06:44:38.35#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.06:44:38.35#ibcon#ireg 7 cls_cnt 0 2006.173.06:44:38.35#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.06:44:38.47#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.06:44:38.47#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.06:44:38.47#ibcon#enter wrdev, iclass 35, count 0 2006.173.06:44:38.47#ibcon#first serial, iclass 35, count 0 2006.173.06:44:38.47#ibcon#enter sib2, iclass 35, count 0 2006.173.06:44:38.47#ibcon#flushed, iclass 35, count 0 2006.173.06:44:38.47#ibcon#about to write, iclass 35, count 0 2006.173.06:44:38.47#ibcon#wrote, iclass 35, count 0 2006.173.06:44:38.47#ibcon#about to read 3, iclass 35, count 0 2006.173.06:44:38.49#ibcon#read 3, iclass 35, count 0 2006.173.06:44:38.49#ibcon#about to read 4, iclass 35, count 0 2006.173.06:44:38.49#ibcon#read 4, iclass 35, count 0 2006.173.06:44:38.49#ibcon#about to read 5, iclass 35, count 0 2006.173.06:44:38.49#ibcon#read 5, iclass 35, count 0 2006.173.06:44:38.49#ibcon#about to read 6, iclass 35, count 0 2006.173.06:44:38.49#ibcon#read 6, iclass 35, count 0 2006.173.06:44:38.49#ibcon#end of sib2, iclass 35, count 0 2006.173.06:44:38.49#ibcon#*mode == 0, iclass 35, count 0 2006.173.06:44:38.49#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.06:44:38.49#ibcon#[27=USB\r\n] 2006.173.06:44:38.49#ibcon#*before write, iclass 35, count 0 2006.173.06:44:38.49#ibcon#enter sib2, iclass 35, count 0 2006.173.06:44:38.49#ibcon#flushed, iclass 35, count 0 2006.173.06:44:38.49#ibcon#about to write, iclass 35, count 0 2006.173.06:44:38.49#ibcon#wrote, iclass 35, count 0 2006.173.06:44:38.49#ibcon#about to read 3, iclass 35, count 0 2006.173.06:44:38.52#ibcon#read 3, iclass 35, count 0 2006.173.06:44:38.52#ibcon#about to read 4, iclass 35, count 0 2006.173.06:44:38.52#ibcon#read 4, iclass 35, count 0 2006.173.06:44:38.52#ibcon#about to read 5, iclass 35, count 0 2006.173.06:44:38.52#ibcon#read 5, iclass 35, count 0 2006.173.06:44:38.52#ibcon#about to read 6, iclass 35, count 0 2006.173.06:44:38.52#ibcon#read 6, iclass 35, count 0 2006.173.06:44:38.52#ibcon#end of sib2, iclass 35, count 0 2006.173.06:44:38.52#ibcon#*after write, iclass 35, count 0 2006.173.06:44:38.52#ibcon#*before return 0, iclass 35, count 0 2006.173.06:44:38.52#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.06:44:38.52#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.06:44:38.52#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.06:44:38.52#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.06:44:38.52$vck44/vblo=6,719.99 2006.173.06:44:38.52#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.06:44:38.52#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.06:44:38.52#ibcon#ireg 17 cls_cnt 0 2006.173.06:44:38.52#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.06:44:38.52#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.06:44:38.52#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.06:44:38.52#ibcon#enter wrdev, iclass 37, count 0 2006.173.06:44:38.52#ibcon#first serial, iclass 37, count 0 2006.173.06:44:38.52#ibcon#enter sib2, iclass 37, count 0 2006.173.06:44:38.52#ibcon#flushed, iclass 37, count 0 2006.173.06:44:38.52#ibcon#about to write, iclass 37, count 0 2006.173.06:44:38.52#ibcon#wrote, iclass 37, count 0 2006.173.06:44:38.52#ibcon#about to read 3, iclass 37, count 0 2006.173.06:44:38.54#ibcon#read 3, iclass 37, count 0 2006.173.06:44:38.54#ibcon#about to read 4, iclass 37, count 0 2006.173.06:44:38.54#ibcon#read 4, iclass 37, count 0 2006.173.06:44:38.54#ibcon#about to read 5, iclass 37, count 0 2006.173.06:44:38.54#ibcon#read 5, iclass 37, count 0 2006.173.06:44:38.54#ibcon#about to read 6, iclass 37, count 0 2006.173.06:44:38.54#ibcon#read 6, iclass 37, count 0 2006.173.06:44:38.54#ibcon#end of sib2, iclass 37, count 0 2006.173.06:44:38.54#ibcon#*mode == 0, iclass 37, count 0 2006.173.06:44:38.54#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.06:44:38.54#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.06:44:38.54#ibcon#*before write, iclass 37, count 0 2006.173.06:44:38.54#ibcon#enter sib2, iclass 37, count 0 2006.173.06:44:38.54#ibcon#flushed, iclass 37, count 0 2006.173.06:44:38.54#ibcon#about to write, iclass 37, count 0 2006.173.06:44:38.54#ibcon#wrote, iclass 37, count 0 2006.173.06:44:38.54#ibcon#about to read 3, iclass 37, count 0 2006.173.06:44:38.58#ibcon#read 3, iclass 37, count 0 2006.173.06:44:38.58#ibcon#about to read 4, iclass 37, count 0 2006.173.06:44:38.58#ibcon#read 4, iclass 37, count 0 2006.173.06:44:38.58#ibcon#about to read 5, iclass 37, count 0 2006.173.06:44:38.58#ibcon#read 5, iclass 37, count 0 2006.173.06:44:38.58#ibcon#about to read 6, iclass 37, count 0 2006.173.06:44:38.58#ibcon#read 6, iclass 37, count 0 2006.173.06:44:38.58#ibcon#end of sib2, iclass 37, count 0 2006.173.06:44:38.58#ibcon#*after write, iclass 37, count 0 2006.173.06:44:38.58#ibcon#*before return 0, iclass 37, count 0 2006.173.06:44:38.58#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.06:44:38.58#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.06:44:38.58#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.06:44:38.58#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.06:44:38.58$vck44/vb=6,4 2006.173.06:44:38.58#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.06:44:38.58#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.06:44:38.58#ibcon#ireg 11 cls_cnt 2 2006.173.06:44:38.58#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.06:44:38.64#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.06:44:38.64#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.06:44:38.64#ibcon#enter wrdev, iclass 39, count 2 2006.173.06:44:38.64#ibcon#first serial, iclass 39, count 2 2006.173.06:44:38.64#ibcon#enter sib2, iclass 39, count 2 2006.173.06:44:38.64#ibcon#flushed, iclass 39, count 2 2006.173.06:44:38.64#ibcon#about to write, iclass 39, count 2 2006.173.06:44:38.64#ibcon#wrote, iclass 39, count 2 2006.173.06:44:38.64#ibcon#about to read 3, iclass 39, count 2 2006.173.06:44:38.66#ibcon#read 3, iclass 39, count 2 2006.173.06:44:38.66#ibcon#about to read 4, iclass 39, count 2 2006.173.06:44:38.66#ibcon#read 4, iclass 39, count 2 2006.173.06:44:38.66#ibcon#about to read 5, iclass 39, count 2 2006.173.06:44:38.66#ibcon#read 5, iclass 39, count 2 2006.173.06:44:38.66#ibcon#about to read 6, iclass 39, count 2 2006.173.06:44:38.66#ibcon#read 6, iclass 39, count 2 2006.173.06:44:38.66#ibcon#end of sib2, iclass 39, count 2 2006.173.06:44:38.66#ibcon#*mode == 0, iclass 39, count 2 2006.173.06:44:38.66#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.06:44:38.66#ibcon#[27=AT06-04\r\n] 2006.173.06:44:38.66#ibcon#*before write, iclass 39, count 2 2006.173.06:44:38.66#ibcon#enter sib2, iclass 39, count 2 2006.173.06:44:38.66#ibcon#flushed, iclass 39, count 2 2006.173.06:44:38.66#ibcon#about to write, iclass 39, count 2 2006.173.06:44:38.66#ibcon#wrote, iclass 39, count 2 2006.173.06:44:38.66#ibcon#about to read 3, iclass 39, count 2 2006.173.06:44:38.69#ibcon#read 3, iclass 39, count 2 2006.173.06:44:38.69#ibcon#about to read 4, iclass 39, count 2 2006.173.06:44:38.69#ibcon#read 4, iclass 39, count 2 2006.173.06:44:38.69#ibcon#about to read 5, iclass 39, count 2 2006.173.06:44:38.69#ibcon#read 5, iclass 39, count 2 2006.173.06:44:38.69#ibcon#about to read 6, iclass 39, count 2 2006.173.06:44:38.69#ibcon#read 6, iclass 39, count 2 2006.173.06:44:38.69#ibcon#end of sib2, iclass 39, count 2 2006.173.06:44:38.69#ibcon#*after write, iclass 39, count 2 2006.173.06:44:38.69#ibcon#*before return 0, iclass 39, count 2 2006.173.06:44:38.69#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.06:44:38.69#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.06:44:38.69#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.06:44:38.69#ibcon#ireg 7 cls_cnt 0 2006.173.06:44:38.69#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.06:44:38.81#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.06:44:38.81#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.06:44:38.81#ibcon#enter wrdev, iclass 39, count 0 2006.173.06:44:38.81#ibcon#first serial, iclass 39, count 0 2006.173.06:44:38.81#ibcon#enter sib2, iclass 39, count 0 2006.173.06:44:38.81#ibcon#flushed, iclass 39, count 0 2006.173.06:44:38.81#ibcon#about to write, iclass 39, count 0 2006.173.06:44:38.81#ibcon#wrote, iclass 39, count 0 2006.173.06:44:38.81#ibcon#about to read 3, iclass 39, count 0 2006.173.06:44:38.83#ibcon#read 3, iclass 39, count 0 2006.173.06:44:38.83#ibcon#about to read 4, iclass 39, count 0 2006.173.06:44:38.83#ibcon#read 4, iclass 39, count 0 2006.173.06:44:38.83#ibcon#about to read 5, iclass 39, count 0 2006.173.06:44:38.83#ibcon#read 5, iclass 39, count 0 2006.173.06:44:38.83#ibcon#about to read 6, iclass 39, count 0 2006.173.06:44:38.83#ibcon#read 6, iclass 39, count 0 2006.173.06:44:38.83#ibcon#end of sib2, iclass 39, count 0 2006.173.06:44:38.83#ibcon#*mode == 0, iclass 39, count 0 2006.173.06:44:38.83#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.06:44:38.83#ibcon#[27=USB\r\n] 2006.173.06:44:38.83#ibcon#*before write, iclass 39, count 0 2006.173.06:44:38.83#ibcon#enter sib2, iclass 39, count 0 2006.173.06:44:38.83#ibcon#flushed, iclass 39, count 0 2006.173.06:44:38.83#ibcon#about to write, iclass 39, count 0 2006.173.06:44:38.83#ibcon#wrote, iclass 39, count 0 2006.173.06:44:38.83#ibcon#about to read 3, iclass 39, count 0 2006.173.06:44:38.86#ibcon#read 3, iclass 39, count 0 2006.173.06:44:38.86#ibcon#about to read 4, iclass 39, count 0 2006.173.06:44:38.86#ibcon#read 4, iclass 39, count 0 2006.173.06:44:38.86#ibcon#about to read 5, iclass 39, count 0 2006.173.06:44:38.86#ibcon#read 5, iclass 39, count 0 2006.173.06:44:38.86#ibcon#about to read 6, iclass 39, count 0 2006.173.06:44:38.86#ibcon#read 6, iclass 39, count 0 2006.173.06:44:38.86#ibcon#end of sib2, iclass 39, count 0 2006.173.06:44:38.86#ibcon#*after write, iclass 39, count 0 2006.173.06:44:38.86#ibcon#*before return 0, iclass 39, count 0 2006.173.06:44:38.86#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.06:44:38.86#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.06:44:38.86#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.06:44:38.86#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.06:44:38.86$vck44/vblo=7,734.99 2006.173.06:44:38.86#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.06:44:38.86#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.06:44:38.86#ibcon#ireg 17 cls_cnt 0 2006.173.06:44:38.86#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.06:44:38.86#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.06:44:38.86#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.06:44:38.86#ibcon#enter wrdev, iclass 3, count 0 2006.173.06:44:38.86#ibcon#first serial, iclass 3, count 0 2006.173.06:44:38.86#ibcon#enter sib2, iclass 3, count 0 2006.173.06:44:38.86#ibcon#flushed, iclass 3, count 0 2006.173.06:44:38.86#ibcon#about to write, iclass 3, count 0 2006.173.06:44:38.86#ibcon#wrote, iclass 3, count 0 2006.173.06:44:38.86#ibcon#about to read 3, iclass 3, count 0 2006.173.06:44:38.88#ibcon#read 3, iclass 3, count 0 2006.173.06:44:38.88#ibcon#about to read 4, iclass 3, count 0 2006.173.06:44:38.88#ibcon#read 4, iclass 3, count 0 2006.173.06:44:38.88#ibcon#about to read 5, iclass 3, count 0 2006.173.06:44:38.88#ibcon#read 5, iclass 3, count 0 2006.173.06:44:38.88#ibcon#about to read 6, iclass 3, count 0 2006.173.06:44:38.88#ibcon#read 6, iclass 3, count 0 2006.173.06:44:38.88#ibcon#end of sib2, iclass 3, count 0 2006.173.06:44:38.88#ibcon#*mode == 0, iclass 3, count 0 2006.173.06:44:38.88#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.06:44:38.88#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.06:44:38.88#ibcon#*before write, iclass 3, count 0 2006.173.06:44:38.88#ibcon#enter sib2, iclass 3, count 0 2006.173.06:44:38.88#ibcon#flushed, iclass 3, count 0 2006.173.06:44:38.88#ibcon#about to write, iclass 3, count 0 2006.173.06:44:38.88#ibcon#wrote, iclass 3, count 0 2006.173.06:44:38.88#ibcon#about to read 3, iclass 3, count 0 2006.173.06:44:38.92#ibcon#read 3, iclass 3, count 0 2006.173.06:44:38.92#ibcon#about to read 4, iclass 3, count 0 2006.173.06:44:38.92#ibcon#read 4, iclass 3, count 0 2006.173.06:44:38.92#ibcon#about to read 5, iclass 3, count 0 2006.173.06:44:38.92#ibcon#read 5, iclass 3, count 0 2006.173.06:44:38.92#ibcon#about to read 6, iclass 3, count 0 2006.173.06:44:38.92#ibcon#read 6, iclass 3, count 0 2006.173.06:44:38.92#ibcon#end of sib2, iclass 3, count 0 2006.173.06:44:38.92#ibcon#*after write, iclass 3, count 0 2006.173.06:44:38.92#ibcon#*before return 0, iclass 3, count 0 2006.173.06:44:38.92#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.06:44:38.92#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.06:44:38.92#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.06:44:38.92#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.06:44:38.92$vck44/vb=7,4 2006.173.06:44:38.92#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.06:44:38.92#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.06:44:38.92#ibcon#ireg 11 cls_cnt 2 2006.173.06:44:38.92#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.06:44:38.98#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.06:44:38.98#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.06:44:38.98#ibcon#enter wrdev, iclass 5, count 2 2006.173.06:44:38.98#ibcon#first serial, iclass 5, count 2 2006.173.06:44:38.98#ibcon#enter sib2, iclass 5, count 2 2006.173.06:44:38.98#ibcon#flushed, iclass 5, count 2 2006.173.06:44:38.98#ibcon#about to write, iclass 5, count 2 2006.173.06:44:38.98#ibcon#wrote, iclass 5, count 2 2006.173.06:44:38.98#ibcon#about to read 3, iclass 5, count 2 2006.173.06:44:39.00#ibcon#read 3, iclass 5, count 2 2006.173.06:44:39.00#ibcon#about to read 4, iclass 5, count 2 2006.173.06:44:39.00#ibcon#read 4, iclass 5, count 2 2006.173.06:44:39.00#ibcon#about to read 5, iclass 5, count 2 2006.173.06:44:39.00#ibcon#read 5, iclass 5, count 2 2006.173.06:44:39.00#ibcon#about to read 6, iclass 5, count 2 2006.173.06:44:39.00#ibcon#read 6, iclass 5, count 2 2006.173.06:44:39.00#ibcon#end of sib2, iclass 5, count 2 2006.173.06:44:39.00#ibcon#*mode == 0, iclass 5, count 2 2006.173.06:44:39.00#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.06:44:39.00#ibcon#[27=AT07-04\r\n] 2006.173.06:44:39.00#ibcon#*before write, iclass 5, count 2 2006.173.06:44:39.00#ibcon#enter sib2, iclass 5, count 2 2006.173.06:44:39.00#ibcon#flushed, iclass 5, count 2 2006.173.06:44:39.00#ibcon#about to write, iclass 5, count 2 2006.173.06:44:39.00#ibcon#wrote, iclass 5, count 2 2006.173.06:44:39.00#ibcon#about to read 3, iclass 5, count 2 2006.173.06:44:39.03#ibcon#read 3, iclass 5, count 2 2006.173.06:44:39.03#ibcon#about to read 4, iclass 5, count 2 2006.173.06:44:39.03#ibcon#read 4, iclass 5, count 2 2006.173.06:44:39.03#ibcon#about to read 5, iclass 5, count 2 2006.173.06:44:39.03#ibcon#read 5, iclass 5, count 2 2006.173.06:44:39.03#ibcon#about to read 6, iclass 5, count 2 2006.173.06:44:39.03#ibcon#read 6, iclass 5, count 2 2006.173.06:44:39.03#ibcon#end of sib2, iclass 5, count 2 2006.173.06:44:39.03#ibcon#*after write, iclass 5, count 2 2006.173.06:44:39.03#ibcon#*before return 0, iclass 5, count 2 2006.173.06:44:39.03#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.06:44:39.03#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.06:44:39.03#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.06:44:39.03#ibcon#ireg 7 cls_cnt 0 2006.173.06:44:39.03#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.06:44:39.15#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.06:44:39.15#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.06:44:39.15#ibcon#enter wrdev, iclass 5, count 0 2006.173.06:44:39.15#ibcon#first serial, iclass 5, count 0 2006.173.06:44:39.15#ibcon#enter sib2, iclass 5, count 0 2006.173.06:44:39.15#ibcon#flushed, iclass 5, count 0 2006.173.06:44:39.15#ibcon#about to write, iclass 5, count 0 2006.173.06:44:39.15#ibcon#wrote, iclass 5, count 0 2006.173.06:44:39.15#ibcon#about to read 3, iclass 5, count 0 2006.173.06:44:39.17#ibcon#read 3, iclass 5, count 0 2006.173.06:44:39.17#ibcon#about to read 4, iclass 5, count 0 2006.173.06:44:39.17#ibcon#read 4, iclass 5, count 0 2006.173.06:44:39.17#ibcon#about to read 5, iclass 5, count 0 2006.173.06:44:39.17#ibcon#read 5, iclass 5, count 0 2006.173.06:44:39.17#ibcon#about to read 6, iclass 5, count 0 2006.173.06:44:39.17#ibcon#read 6, iclass 5, count 0 2006.173.06:44:39.17#ibcon#end of sib2, iclass 5, count 0 2006.173.06:44:39.17#ibcon#*mode == 0, iclass 5, count 0 2006.173.06:44:39.17#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.06:44:39.17#ibcon#[27=USB\r\n] 2006.173.06:44:39.17#ibcon#*before write, iclass 5, count 0 2006.173.06:44:39.17#ibcon#enter sib2, iclass 5, count 0 2006.173.06:44:39.17#ibcon#flushed, iclass 5, count 0 2006.173.06:44:39.17#ibcon#about to write, iclass 5, count 0 2006.173.06:44:39.17#ibcon#wrote, iclass 5, count 0 2006.173.06:44:39.17#ibcon#about to read 3, iclass 5, count 0 2006.173.06:44:39.20#ibcon#read 3, iclass 5, count 0 2006.173.06:44:39.20#ibcon#about to read 4, iclass 5, count 0 2006.173.06:44:39.20#ibcon#read 4, iclass 5, count 0 2006.173.06:44:39.20#ibcon#about to read 5, iclass 5, count 0 2006.173.06:44:39.20#ibcon#read 5, iclass 5, count 0 2006.173.06:44:39.20#ibcon#about to read 6, iclass 5, count 0 2006.173.06:44:39.20#ibcon#read 6, iclass 5, count 0 2006.173.06:44:39.20#ibcon#end of sib2, iclass 5, count 0 2006.173.06:44:39.20#ibcon#*after write, iclass 5, count 0 2006.173.06:44:39.20#ibcon#*before return 0, iclass 5, count 0 2006.173.06:44:39.20#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.06:44:39.20#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.06:44:39.20#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.06:44:39.20#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.06:44:39.20$vck44/vblo=8,744.99 2006.173.06:44:39.20#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.06:44:39.20#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.06:44:39.20#ibcon#ireg 17 cls_cnt 0 2006.173.06:44:39.20#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.06:44:39.20#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.06:44:39.20#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.06:44:39.20#ibcon#enter wrdev, iclass 7, count 0 2006.173.06:44:39.20#ibcon#first serial, iclass 7, count 0 2006.173.06:44:39.20#ibcon#enter sib2, iclass 7, count 0 2006.173.06:44:39.20#ibcon#flushed, iclass 7, count 0 2006.173.06:44:39.20#ibcon#about to write, iclass 7, count 0 2006.173.06:44:39.20#ibcon#wrote, iclass 7, count 0 2006.173.06:44:39.20#ibcon#about to read 3, iclass 7, count 0 2006.173.06:44:39.22#ibcon#read 3, iclass 7, count 0 2006.173.06:44:39.22#ibcon#about to read 4, iclass 7, count 0 2006.173.06:44:39.22#ibcon#read 4, iclass 7, count 0 2006.173.06:44:39.22#ibcon#about to read 5, iclass 7, count 0 2006.173.06:44:39.22#ibcon#read 5, iclass 7, count 0 2006.173.06:44:39.22#ibcon#about to read 6, iclass 7, count 0 2006.173.06:44:39.22#ibcon#read 6, iclass 7, count 0 2006.173.06:44:39.22#ibcon#end of sib2, iclass 7, count 0 2006.173.06:44:39.22#ibcon#*mode == 0, iclass 7, count 0 2006.173.06:44:39.22#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.06:44:39.22#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.06:44:39.22#ibcon#*before write, iclass 7, count 0 2006.173.06:44:39.22#ibcon#enter sib2, iclass 7, count 0 2006.173.06:44:39.22#ibcon#flushed, iclass 7, count 0 2006.173.06:44:39.22#ibcon#about to write, iclass 7, count 0 2006.173.06:44:39.22#ibcon#wrote, iclass 7, count 0 2006.173.06:44:39.22#ibcon#about to read 3, iclass 7, count 0 2006.173.06:44:39.26#ibcon#read 3, iclass 7, count 0 2006.173.06:44:39.26#ibcon#about to read 4, iclass 7, count 0 2006.173.06:44:39.26#ibcon#read 4, iclass 7, count 0 2006.173.06:44:39.26#ibcon#about to read 5, iclass 7, count 0 2006.173.06:44:39.26#ibcon#read 5, iclass 7, count 0 2006.173.06:44:39.26#ibcon#about to read 6, iclass 7, count 0 2006.173.06:44:39.26#ibcon#read 6, iclass 7, count 0 2006.173.06:44:39.26#ibcon#end of sib2, iclass 7, count 0 2006.173.06:44:39.26#ibcon#*after write, iclass 7, count 0 2006.173.06:44:39.26#ibcon#*before return 0, iclass 7, count 0 2006.173.06:44:39.26#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.06:44:39.26#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.06:44:39.26#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.06:44:39.26#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.06:44:39.26$vck44/vb=8,4 2006.173.06:44:39.26#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.06:44:39.26#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.06:44:39.26#ibcon#ireg 11 cls_cnt 2 2006.173.06:44:39.26#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.06:44:39.32#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.06:44:39.32#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.06:44:39.32#ibcon#enter wrdev, iclass 11, count 2 2006.173.06:44:39.32#ibcon#first serial, iclass 11, count 2 2006.173.06:44:39.32#ibcon#enter sib2, iclass 11, count 2 2006.173.06:44:39.32#ibcon#flushed, iclass 11, count 2 2006.173.06:44:39.32#ibcon#about to write, iclass 11, count 2 2006.173.06:44:39.32#ibcon#wrote, iclass 11, count 2 2006.173.06:44:39.32#ibcon#about to read 3, iclass 11, count 2 2006.173.06:44:39.34#ibcon#read 3, iclass 11, count 2 2006.173.06:44:39.34#ibcon#about to read 4, iclass 11, count 2 2006.173.06:44:39.34#ibcon#read 4, iclass 11, count 2 2006.173.06:44:39.34#ibcon#about to read 5, iclass 11, count 2 2006.173.06:44:39.34#ibcon#read 5, iclass 11, count 2 2006.173.06:44:39.34#ibcon#about to read 6, iclass 11, count 2 2006.173.06:44:39.34#ibcon#read 6, iclass 11, count 2 2006.173.06:44:39.34#ibcon#end of sib2, iclass 11, count 2 2006.173.06:44:39.34#ibcon#*mode == 0, iclass 11, count 2 2006.173.06:44:39.34#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.06:44:39.34#ibcon#[27=AT08-04\r\n] 2006.173.06:44:39.34#ibcon#*before write, iclass 11, count 2 2006.173.06:44:39.34#ibcon#enter sib2, iclass 11, count 2 2006.173.06:44:39.34#ibcon#flushed, iclass 11, count 2 2006.173.06:44:39.34#ibcon#about to write, iclass 11, count 2 2006.173.06:44:39.34#ibcon#wrote, iclass 11, count 2 2006.173.06:44:39.34#ibcon#about to read 3, iclass 11, count 2 2006.173.06:44:39.37#ibcon#read 3, iclass 11, count 2 2006.173.06:44:39.37#ibcon#about to read 4, iclass 11, count 2 2006.173.06:44:39.37#ibcon#read 4, iclass 11, count 2 2006.173.06:44:39.37#ibcon#about to read 5, iclass 11, count 2 2006.173.06:44:39.37#ibcon#read 5, iclass 11, count 2 2006.173.06:44:39.37#ibcon#about to read 6, iclass 11, count 2 2006.173.06:44:39.37#ibcon#read 6, iclass 11, count 2 2006.173.06:44:39.37#ibcon#end of sib2, iclass 11, count 2 2006.173.06:44:39.37#ibcon#*after write, iclass 11, count 2 2006.173.06:44:39.37#ibcon#*before return 0, iclass 11, count 2 2006.173.06:44:39.37#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.06:44:39.37#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.06:44:39.37#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.06:44:39.37#ibcon#ireg 7 cls_cnt 0 2006.173.06:44:39.37#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.06:44:39.49#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.06:44:39.49#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.06:44:39.49#ibcon#enter wrdev, iclass 11, count 0 2006.173.06:44:39.49#ibcon#first serial, iclass 11, count 0 2006.173.06:44:39.49#ibcon#enter sib2, iclass 11, count 0 2006.173.06:44:39.49#ibcon#flushed, iclass 11, count 0 2006.173.06:44:39.49#ibcon#about to write, iclass 11, count 0 2006.173.06:44:39.49#ibcon#wrote, iclass 11, count 0 2006.173.06:44:39.49#ibcon#about to read 3, iclass 11, count 0 2006.173.06:44:39.51#ibcon#read 3, iclass 11, count 0 2006.173.06:44:39.51#ibcon#about to read 4, iclass 11, count 0 2006.173.06:44:39.51#ibcon#read 4, iclass 11, count 0 2006.173.06:44:39.51#ibcon#about to read 5, iclass 11, count 0 2006.173.06:44:39.51#ibcon#read 5, iclass 11, count 0 2006.173.06:44:39.51#ibcon#about to read 6, iclass 11, count 0 2006.173.06:44:39.51#ibcon#read 6, iclass 11, count 0 2006.173.06:44:39.51#ibcon#end of sib2, iclass 11, count 0 2006.173.06:44:39.51#ibcon#*mode == 0, iclass 11, count 0 2006.173.06:44:39.51#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.06:44:39.51#ibcon#[27=USB\r\n] 2006.173.06:44:39.51#ibcon#*before write, iclass 11, count 0 2006.173.06:44:39.51#ibcon#enter sib2, iclass 11, count 0 2006.173.06:44:39.51#ibcon#flushed, iclass 11, count 0 2006.173.06:44:39.51#ibcon#about to write, iclass 11, count 0 2006.173.06:44:39.51#ibcon#wrote, iclass 11, count 0 2006.173.06:44:39.51#ibcon#about to read 3, iclass 11, count 0 2006.173.06:44:39.54#ibcon#read 3, iclass 11, count 0 2006.173.06:44:39.54#ibcon#about to read 4, iclass 11, count 0 2006.173.06:44:39.54#ibcon#read 4, iclass 11, count 0 2006.173.06:44:39.54#ibcon#about to read 5, iclass 11, count 0 2006.173.06:44:39.54#ibcon#read 5, iclass 11, count 0 2006.173.06:44:39.54#ibcon#about to read 6, iclass 11, count 0 2006.173.06:44:39.54#ibcon#read 6, iclass 11, count 0 2006.173.06:44:39.54#ibcon#end of sib2, iclass 11, count 0 2006.173.06:44:39.54#ibcon#*after write, iclass 11, count 0 2006.173.06:44:39.54#ibcon#*before return 0, iclass 11, count 0 2006.173.06:44:39.54#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.06:44:39.54#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.06:44:39.54#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.06:44:39.54#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.06:44:39.54$vck44/vabw=wide 2006.173.06:44:39.54#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.06:44:39.54#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.06:44:39.54#ibcon#ireg 8 cls_cnt 0 2006.173.06:44:39.54#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.06:44:39.54#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.06:44:39.54#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.06:44:39.54#ibcon#enter wrdev, iclass 13, count 0 2006.173.06:44:39.54#ibcon#first serial, iclass 13, count 0 2006.173.06:44:39.54#ibcon#enter sib2, iclass 13, count 0 2006.173.06:44:39.54#ibcon#flushed, iclass 13, count 0 2006.173.06:44:39.54#ibcon#about to write, iclass 13, count 0 2006.173.06:44:39.54#ibcon#wrote, iclass 13, count 0 2006.173.06:44:39.54#ibcon#about to read 3, iclass 13, count 0 2006.173.06:44:39.56#ibcon#read 3, iclass 13, count 0 2006.173.06:44:39.56#ibcon#about to read 4, iclass 13, count 0 2006.173.06:44:39.56#ibcon#read 4, iclass 13, count 0 2006.173.06:44:39.56#ibcon#about to read 5, iclass 13, count 0 2006.173.06:44:39.56#ibcon#read 5, iclass 13, count 0 2006.173.06:44:39.56#ibcon#about to read 6, iclass 13, count 0 2006.173.06:44:39.56#ibcon#read 6, iclass 13, count 0 2006.173.06:44:39.56#ibcon#end of sib2, iclass 13, count 0 2006.173.06:44:39.56#ibcon#*mode == 0, iclass 13, count 0 2006.173.06:44:39.56#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.06:44:39.56#ibcon#[25=BW32\r\n] 2006.173.06:44:39.56#ibcon#*before write, iclass 13, count 0 2006.173.06:44:39.56#ibcon#enter sib2, iclass 13, count 0 2006.173.06:44:39.56#ibcon#flushed, iclass 13, count 0 2006.173.06:44:39.56#ibcon#about to write, iclass 13, count 0 2006.173.06:44:39.56#ibcon#wrote, iclass 13, count 0 2006.173.06:44:39.56#ibcon#about to read 3, iclass 13, count 0 2006.173.06:44:39.59#ibcon#read 3, iclass 13, count 0 2006.173.06:44:39.59#ibcon#about to read 4, iclass 13, count 0 2006.173.06:44:39.59#ibcon#read 4, iclass 13, count 0 2006.173.06:44:39.59#ibcon#about to read 5, iclass 13, count 0 2006.173.06:44:39.59#ibcon#read 5, iclass 13, count 0 2006.173.06:44:39.59#ibcon#about to read 6, iclass 13, count 0 2006.173.06:44:39.59#ibcon#read 6, iclass 13, count 0 2006.173.06:44:39.59#ibcon#end of sib2, iclass 13, count 0 2006.173.06:44:39.59#ibcon#*after write, iclass 13, count 0 2006.173.06:44:39.59#ibcon#*before return 0, iclass 13, count 0 2006.173.06:44:39.59#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.06:44:39.59#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.06:44:39.59#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.06:44:39.59#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.06:44:39.59$vck44/vbbw=wide 2006.173.06:44:39.59#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.06:44:39.59#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.06:44:39.59#ibcon#ireg 8 cls_cnt 0 2006.173.06:44:39.59#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.06:44:39.66#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.06:44:39.66#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.06:44:39.66#ibcon#enter wrdev, iclass 15, count 0 2006.173.06:44:39.66#ibcon#first serial, iclass 15, count 0 2006.173.06:44:39.66#ibcon#enter sib2, iclass 15, count 0 2006.173.06:44:39.66#ibcon#flushed, iclass 15, count 0 2006.173.06:44:39.66#ibcon#about to write, iclass 15, count 0 2006.173.06:44:39.66#ibcon#wrote, iclass 15, count 0 2006.173.06:44:39.66#ibcon#about to read 3, iclass 15, count 0 2006.173.06:44:39.68#ibcon#read 3, iclass 15, count 0 2006.173.06:44:39.68#ibcon#about to read 4, iclass 15, count 0 2006.173.06:44:39.68#ibcon#read 4, iclass 15, count 0 2006.173.06:44:39.68#ibcon#about to read 5, iclass 15, count 0 2006.173.06:44:39.68#ibcon#read 5, iclass 15, count 0 2006.173.06:44:39.68#ibcon#about to read 6, iclass 15, count 0 2006.173.06:44:39.68#ibcon#read 6, iclass 15, count 0 2006.173.06:44:39.68#ibcon#end of sib2, iclass 15, count 0 2006.173.06:44:39.68#ibcon#*mode == 0, iclass 15, count 0 2006.173.06:44:39.68#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.06:44:39.68#ibcon#[27=BW32\r\n] 2006.173.06:44:39.68#ibcon#*before write, iclass 15, count 0 2006.173.06:44:39.68#ibcon#enter sib2, iclass 15, count 0 2006.173.06:44:39.68#ibcon#flushed, iclass 15, count 0 2006.173.06:44:39.68#ibcon#about to write, iclass 15, count 0 2006.173.06:44:39.68#ibcon#wrote, iclass 15, count 0 2006.173.06:44:39.68#ibcon#about to read 3, iclass 15, count 0 2006.173.06:44:39.71#ibcon#read 3, iclass 15, count 0 2006.173.06:44:39.71#ibcon#about to read 4, iclass 15, count 0 2006.173.06:44:39.71#ibcon#read 4, iclass 15, count 0 2006.173.06:44:39.71#ibcon#about to read 5, iclass 15, count 0 2006.173.06:44:39.71#ibcon#read 5, iclass 15, count 0 2006.173.06:44:39.71#ibcon#about to read 6, iclass 15, count 0 2006.173.06:44:39.71#ibcon#read 6, iclass 15, count 0 2006.173.06:44:39.71#ibcon#end of sib2, iclass 15, count 0 2006.173.06:44:39.71#ibcon#*after write, iclass 15, count 0 2006.173.06:44:39.71#ibcon#*before return 0, iclass 15, count 0 2006.173.06:44:39.71#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.06:44:39.71#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.06:44:39.71#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.06:44:39.71#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.06:44:39.71$setupk4/ifdk4 2006.173.06:44:39.71$ifdk4/lo= 2006.173.06:44:39.71$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.06:44:39.71$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.06:44:39.71$ifdk4/patch= 2006.173.06:44:39.71$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.06:44:39.71$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.06:44:39.71$setupk4/!*+20s 2006.173.06:44:42.76#abcon#<5=/15 0.5 0.9 23.70 801004.9\r\n> 2006.173.06:44:42.78#abcon#{5=INTERFACE CLEAR} 2006.173.06:44:42.84#abcon#[5=S1D000X0/0*\r\n] 2006.173.06:44:52.93#abcon#<5=/15 0.5 0.8 23.69 801004.9\r\n> 2006.173.06:44:52.95#abcon#{5=INTERFACE CLEAR} 2006.173.06:44:53.01#abcon#[5=S1D000X0/0*\r\n] 2006.173.06:44:54.23$setupk4/"tpicd 2006.173.06:44:54.23$setupk4/echo=off 2006.173.06:44:54.23$setupk4/xlog=off 2006.173.06:44:54.23:!2006.173.06:51:50 2006.173.06:45:00.14#trakl#Source acquired 2006.173.06:45:00.14#flagr#flagr/antenna,acquired 2006.173.06:51:50.00:preob 2006.173.06:51:50.14/onsource/TRACKING 2006.173.06:51:50.14:!2006.173.06:52:00 2006.173.06:52:00.00:"tape 2006.173.06:52:00.00:"st=record 2006.173.06:52:00.00:data_valid=on 2006.173.06:52:00.00:midob 2006.173.06:52:00.14/onsource/TRACKING 2006.173.06:52:00.14/wx/23.68,1004.9,80 2006.173.06:52:00.33/cable/+6.5053E-03 2006.173.06:52:01.42/va/01,07,usb,yes,35,37 2006.173.06:52:01.42/va/02,06,usb,yes,34,35 2006.173.06:52:01.42/va/03,05,usb,yes,44,46 2006.173.06:52:01.42/va/04,06,usb,yes,35,37 2006.173.06:52:01.42/va/05,04,usb,yes,27,28 2006.173.06:52:01.42/va/06,03,usb,yes,39,38 2006.173.06:52:01.42/va/07,04,usb,yes,31,32 2006.173.06:52:01.42/va/08,04,usb,yes,26,32 2006.173.06:52:01.65/valo/01,524.99,yes,locked 2006.173.06:52:01.65/valo/02,534.99,yes,locked 2006.173.06:52:01.65/valo/03,564.99,yes,locked 2006.173.06:52:01.65/valo/04,624.99,yes,locked 2006.173.06:52:01.65/valo/05,734.99,yes,locked 2006.173.06:52:01.65/valo/06,814.99,yes,locked 2006.173.06:52:01.65/valo/07,864.99,yes,locked 2006.173.06:52:01.65/valo/08,884.99,yes,locked 2006.173.06:52:02.74/vb/01,04,usb,yes,29,27 2006.173.06:52:02.74/vb/02,04,usb,yes,31,31 2006.173.06:52:02.74/vb/03,04,usb,yes,28,31 2006.173.06:52:02.74/vb/04,04,usb,yes,33,32 2006.173.06:52:02.74/vb/05,04,usb,yes,25,28 2006.173.06:52:02.74/vb/06,04,usb,yes,30,26 2006.173.06:52:02.74/vb/07,04,usb,yes,29,29 2006.173.06:52:02.74/vb/08,04,usb,yes,27,30 2006.173.06:52:02.97/vblo/01,629.99,yes,locked 2006.173.06:52:02.97/vblo/02,634.99,yes,locked 2006.173.06:52:02.97/vblo/03,649.99,yes,locked 2006.173.06:52:02.97/vblo/04,679.99,yes,locked 2006.173.06:52:02.97/vblo/05,709.99,yes,locked 2006.173.06:52:02.97/vblo/06,719.99,yes,locked 2006.173.06:52:02.97/vblo/07,734.99,yes,locked 2006.173.06:52:02.97/vblo/08,744.99,yes,locked 2006.173.06:52:03.12/vabw/8 2006.173.06:52:03.27/vbbw/8 2006.173.06:52:03.36/xfe/off,on,14.7 2006.173.06:52:03.75/ifatt/23,28,28,28 2006.173.06:52:04.08/fmout-gps/S +3.99E-07 2006.173.06:52:04.12:!2006.173.06:59:20 2006.173.06:59:20.00:data_valid=off 2006.173.06:59:20.00:"et 2006.173.06:59:20.01:!+3s 2006.173.06:59:23.02:"tape 2006.173.06:59:23.02:postob 2006.173.06:59:23.13/cable/+6.5036E-03 2006.173.06:59:23.13/wx/23.73,1004.9,79 2006.173.06:59:24.08/fmout-gps/S +3.98E-07 2006.173.06:59:24.08:scan_name=173-0705,jd0606,40 2006.173.06:59:24.09:source=3c345,164258.81,394837.0,2000.0,ccw 2006.173.06:59:25.14#flagr#flagr/antenna,new-source 2006.173.06:59:25.14:checkk5 2006.173.06:59:25.56/chk_autoobs//k5ts1/ autoobs is running! 2006.173.06:59:25.95/chk_autoobs//k5ts2/ autoobs is running! 2006.173.06:59:26.36/chk_autoobs//k5ts3/ autoobs is running! 2006.173.06:59:26.77/chk_autoobs//k5ts4/ autoobs is running! 2006.173.06:59:27.17/chk_obsdata//k5ts1/T1730652??a.dat file size is correct (nominal:1760MB, actual:1760MB). 2006.173.06:59:27.57/chk_obsdata//k5ts2/T1730652??b.dat file size is correct (nominal:1760MB, actual:1760MB). 2006.173.06:59:27.97/chk_obsdata//k5ts3/T1730652??c.dat file size is correct (nominal:1760MB, actual:1760MB). 2006.173.06:59:28.35/chk_obsdata//k5ts4/T1730652??d.dat file size is correct (nominal:1760MB, actual:1760MB). 2006.173.06:59:29.08/k5log//k5ts1_log_newline 2006.173.06:59:29.79/k5log//k5ts2_log_newline 2006.173.06:59:30.50/k5log//k5ts3_log_newline 2006.173.06:59:31.20/k5log//k5ts4_log_newline 2006.173.06:59:31.22/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.06:59:31.22:setupk4=1 2006.173.06:59:31.22$setupk4/echo=on 2006.173.06:59:31.22$setupk4/pcalon 2006.173.06:59:31.22$pcalon/"no phase cal control is implemented here 2006.173.06:59:31.22$setupk4/"tpicd=stop 2006.173.06:59:31.22$setupk4/"rec=synch_on 2006.173.06:59:31.22$setupk4/"rec_mode=128 2006.173.06:59:31.23$setupk4/!* 2006.173.06:59:31.23$setupk4/recpk4 2006.173.06:59:31.23$recpk4/recpatch= 2006.173.06:59:31.23$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.06:59:31.23$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.06:59:31.23$setupk4/vck44 2006.173.06:59:31.23$vck44/valo=1,524.99 2006.173.06:59:31.23#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.06:59:31.23#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.06:59:31.23#ibcon#ireg 17 cls_cnt 0 2006.173.06:59:31.23#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.06:59:31.23#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.06:59:31.23#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.06:59:31.23#ibcon#enter wrdev, iclass 12, count 0 2006.173.06:59:31.23#ibcon#first serial, iclass 12, count 0 2006.173.06:59:31.23#ibcon#enter sib2, iclass 12, count 0 2006.173.06:59:31.23#ibcon#flushed, iclass 12, count 0 2006.173.06:59:31.23#ibcon#about to write, iclass 12, count 0 2006.173.06:59:31.23#ibcon#wrote, iclass 12, count 0 2006.173.06:59:31.23#ibcon#about to read 3, iclass 12, count 0 2006.173.06:59:31.25#ibcon#read 3, iclass 12, count 0 2006.173.06:59:31.25#ibcon#about to read 4, iclass 12, count 0 2006.173.06:59:31.25#ibcon#read 4, iclass 12, count 0 2006.173.06:59:31.25#ibcon#about to read 5, iclass 12, count 0 2006.173.06:59:31.25#ibcon#read 5, iclass 12, count 0 2006.173.06:59:31.25#ibcon#about to read 6, iclass 12, count 0 2006.173.06:59:31.25#ibcon#read 6, iclass 12, count 0 2006.173.06:59:31.25#ibcon#end of sib2, iclass 12, count 0 2006.173.06:59:31.25#ibcon#*mode == 0, iclass 12, count 0 2006.173.06:59:31.25#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.06:59:31.25#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.06:59:31.25#ibcon#*before write, iclass 12, count 0 2006.173.06:59:31.25#ibcon#enter sib2, iclass 12, count 0 2006.173.06:59:31.25#ibcon#flushed, iclass 12, count 0 2006.173.06:59:31.25#ibcon#about to write, iclass 12, count 0 2006.173.06:59:31.25#ibcon#wrote, iclass 12, count 0 2006.173.06:59:31.25#ibcon#about to read 3, iclass 12, count 0 2006.173.06:59:31.30#ibcon#read 3, iclass 12, count 0 2006.173.06:59:31.30#ibcon#about to read 4, iclass 12, count 0 2006.173.06:59:31.30#ibcon#read 4, iclass 12, count 0 2006.173.06:59:31.30#ibcon#about to read 5, iclass 12, count 0 2006.173.06:59:31.30#ibcon#read 5, iclass 12, count 0 2006.173.06:59:31.30#ibcon#about to read 6, iclass 12, count 0 2006.173.06:59:31.30#ibcon#read 6, iclass 12, count 0 2006.173.06:59:31.30#ibcon#end of sib2, iclass 12, count 0 2006.173.06:59:31.30#ibcon#*after write, iclass 12, count 0 2006.173.06:59:31.30#ibcon#*before return 0, iclass 12, count 0 2006.173.06:59:31.30#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.06:59:31.30#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.06:59:31.30#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.06:59:31.30#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.06:59:31.30$vck44/va=1,7 2006.173.06:59:31.30#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.06:59:31.30#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.06:59:31.30#ibcon#ireg 11 cls_cnt 2 2006.173.06:59:31.30#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.06:59:31.30#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.06:59:31.30#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.06:59:31.30#ibcon#enter wrdev, iclass 14, count 2 2006.173.06:59:31.30#ibcon#first serial, iclass 14, count 2 2006.173.06:59:31.30#ibcon#enter sib2, iclass 14, count 2 2006.173.06:59:31.30#ibcon#flushed, iclass 14, count 2 2006.173.06:59:31.30#ibcon#about to write, iclass 14, count 2 2006.173.06:59:31.30#ibcon#wrote, iclass 14, count 2 2006.173.06:59:31.30#ibcon#about to read 3, iclass 14, count 2 2006.173.06:59:31.32#ibcon#read 3, iclass 14, count 2 2006.173.06:59:31.32#ibcon#about to read 4, iclass 14, count 2 2006.173.06:59:31.32#ibcon#read 4, iclass 14, count 2 2006.173.06:59:31.32#ibcon#about to read 5, iclass 14, count 2 2006.173.06:59:31.32#ibcon#read 5, iclass 14, count 2 2006.173.06:59:31.32#ibcon#about to read 6, iclass 14, count 2 2006.173.06:59:31.32#ibcon#read 6, iclass 14, count 2 2006.173.06:59:31.32#ibcon#end of sib2, iclass 14, count 2 2006.173.06:59:31.32#ibcon#*mode == 0, iclass 14, count 2 2006.173.06:59:31.32#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.06:59:31.32#ibcon#[25=AT01-07\r\n] 2006.173.06:59:31.32#ibcon#*before write, iclass 14, count 2 2006.173.06:59:31.32#ibcon#enter sib2, iclass 14, count 2 2006.173.06:59:31.32#ibcon#flushed, iclass 14, count 2 2006.173.06:59:31.32#ibcon#about to write, iclass 14, count 2 2006.173.06:59:31.32#ibcon#wrote, iclass 14, count 2 2006.173.06:59:31.32#ibcon#about to read 3, iclass 14, count 2 2006.173.06:59:31.35#ibcon#read 3, iclass 14, count 2 2006.173.06:59:31.35#ibcon#about to read 4, iclass 14, count 2 2006.173.06:59:31.35#ibcon#read 4, iclass 14, count 2 2006.173.06:59:31.35#ibcon#about to read 5, iclass 14, count 2 2006.173.06:59:31.35#ibcon#read 5, iclass 14, count 2 2006.173.06:59:31.35#ibcon#about to read 6, iclass 14, count 2 2006.173.06:59:31.35#ibcon#read 6, iclass 14, count 2 2006.173.06:59:31.35#ibcon#end of sib2, iclass 14, count 2 2006.173.06:59:31.35#ibcon#*after write, iclass 14, count 2 2006.173.06:59:31.35#ibcon#*before return 0, iclass 14, count 2 2006.173.06:59:31.35#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.06:59:31.35#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.06:59:31.35#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.06:59:31.35#ibcon#ireg 7 cls_cnt 0 2006.173.06:59:31.35#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.06:59:31.47#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.06:59:31.47#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.06:59:31.47#ibcon#enter wrdev, iclass 14, count 0 2006.173.06:59:31.47#ibcon#first serial, iclass 14, count 0 2006.173.06:59:31.47#ibcon#enter sib2, iclass 14, count 0 2006.173.06:59:31.47#ibcon#flushed, iclass 14, count 0 2006.173.06:59:31.47#ibcon#about to write, iclass 14, count 0 2006.173.06:59:31.47#ibcon#wrote, iclass 14, count 0 2006.173.06:59:31.47#ibcon#about to read 3, iclass 14, count 0 2006.173.06:59:31.49#ibcon#read 3, iclass 14, count 0 2006.173.06:59:31.49#ibcon#about to read 4, iclass 14, count 0 2006.173.06:59:31.49#ibcon#read 4, iclass 14, count 0 2006.173.06:59:31.49#ibcon#about to read 5, iclass 14, count 0 2006.173.06:59:31.49#ibcon#read 5, iclass 14, count 0 2006.173.06:59:31.49#ibcon#about to read 6, iclass 14, count 0 2006.173.06:59:31.49#ibcon#read 6, iclass 14, count 0 2006.173.06:59:31.49#ibcon#end of sib2, iclass 14, count 0 2006.173.06:59:31.49#ibcon#*mode == 0, iclass 14, count 0 2006.173.06:59:31.49#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.06:59:31.49#ibcon#[25=USB\r\n] 2006.173.06:59:31.49#ibcon#*before write, iclass 14, count 0 2006.173.06:59:31.49#ibcon#enter sib2, iclass 14, count 0 2006.173.06:59:31.49#ibcon#flushed, iclass 14, count 0 2006.173.06:59:31.49#ibcon#about to write, iclass 14, count 0 2006.173.06:59:31.49#ibcon#wrote, iclass 14, count 0 2006.173.06:59:31.49#ibcon#about to read 3, iclass 14, count 0 2006.173.06:59:31.52#ibcon#read 3, iclass 14, count 0 2006.173.06:59:31.52#ibcon#about to read 4, iclass 14, count 0 2006.173.06:59:31.52#ibcon#read 4, iclass 14, count 0 2006.173.06:59:31.52#ibcon#about to read 5, iclass 14, count 0 2006.173.06:59:31.52#ibcon#read 5, iclass 14, count 0 2006.173.06:59:31.52#ibcon#about to read 6, iclass 14, count 0 2006.173.06:59:31.52#ibcon#read 6, iclass 14, count 0 2006.173.06:59:31.52#ibcon#end of sib2, iclass 14, count 0 2006.173.06:59:31.52#ibcon#*after write, iclass 14, count 0 2006.173.06:59:31.52#ibcon#*before return 0, iclass 14, count 0 2006.173.06:59:31.52#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.06:59:31.52#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.06:59:31.52#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.06:59:31.52#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.06:59:31.52$vck44/valo=2,534.99 2006.173.06:59:31.52#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.06:59:31.52#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.06:59:31.52#ibcon#ireg 17 cls_cnt 0 2006.173.06:59:31.52#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.06:59:31.52#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.06:59:31.52#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.06:59:31.52#ibcon#enter wrdev, iclass 16, count 0 2006.173.06:59:31.52#ibcon#first serial, iclass 16, count 0 2006.173.06:59:31.52#ibcon#enter sib2, iclass 16, count 0 2006.173.06:59:31.52#ibcon#flushed, iclass 16, count 0 2006.173.06:59:31.52#ibcon#about to write, iclass 16, count 0 2006.173.06:59:31.52#ibcon#wrote, iclass 16, count 0 2006.173.06:59:31.52#ibcon#about to read 3, iclass 16, count 0 2006.173.06:59:31.54#ibcon#read 3, iclass 16, count 0 2006.173.06:59:31.54#ibcon#about to read 4, iclass 16, count 0 2006.173.06:59:31.54#ibcon#read 4, iclass 16, count 0 2006.173.06:59:31.54#ibcon#about to read 5, iclass 16, count 0 2006.173.06:59:31.54#ibcon#read 5, iclass 16, count 0 2006.173.06:59:31.54#ibcon#about to read 6, iclass 16, count 0 2006.173.06:59:31.54#ibcon#read 6, iclass 16, count 0 2006.173.06:59:31.54#ibcon#end of sib2, iclass 16, count 0 2006.173.06:59:31.54#ibcon#*mode == 0, iclass 16, count 0 2006.173.06:59:31.54#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.06:59:31.54#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.06:59:31.54#ibcon#*before write, iclass 16, count 0 2006.173.06:59:31.54#ibcon#enter sib2, iclass 16, count 0 2006.173.06:59:31.54#ibcon#flushed, iclass 16, count 0 2006.173.06:59:31.54#ibcon#about to write, iclass 16, count 0 2006.173.06:59:31.54#ibcon#wrote, iclass 16, count 0 2006.173.06:59:31.54#ibcon#about to read 3, iclass 16, count 0 2006.173.06:59:31.58#ibcon#read 3, iclass 16, count 0 2006.173.06:59:31.58#ibcon#about to read 4, iclass 16, count 0 2006.173.06:59:31.58#ibcon#read 4, iclass 16, count 0 2006.173.06:59:31.58#ibcon#about to read 5, iclass 16, count 0 2006.173.06:59:31.58#ibcon#read 5, iclass 16, count 0 2006.173.06:59:31.58#ibcon#about to read 6, iclass 16, count 0 2006.173.06:59:31.58#ibcon#read 6, iclass 16, count 0 2006.173.06:59:31.58#ibcon#end of sib2, iclass 16, count 0 2006.173.06:59:31.58#ibcon#*after write, iclass 16, count 0 2006.173.06:59:31.58#ibcon#*before return 0, iclass 16, count 0 2006.173.06:59:31.58#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.06:59:31.58#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.06:59:31.58#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.06:59:31.58#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.06:59:31.58$vck44/va=2,6 2006.173.06:59:31.58#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.06:59:31.58#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.06:59:31.58#ibcon#ireg 11 cls_cnt 2 2006.173.06:59:31.58#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.06:59:31.64#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.06:59:31.64#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.06:59:31.64#ibcon#enter wrdev, iclass 18, count 2 2006.173.06:59:31.64#ibcon#first serial, iclass 18, count 2 2006.173.06:59:31.64#ibcon#enter sib2, iclass 18, count 2 2006.173.06:59:31.64#ibcon#flushed, iclass 18, count 2 2006.173.06:59:31.64#ibcon#about to write, iclass 18, count 2 2006.173.06:59:31.64#ibcon#wrote, iclass 18, count 2 2006.173.06:59:31.64#ibcon#about to read 3, iclass 18, count 2 2006.173.06:59:31.66#ibcon#read 3, iclass 18, count 2 2006.173.06:59:31.66#ibcon#about to read 4, iclass 18, count 2 2006.173.06:59:31.66#ibcon#read 4, iclass 18, count 2 2006.173.06:59:31.66#ibcon#about to read 5, iclass 18, count 2 2006.173.06:59:31.66#ibcon#read 5, iclass 18, count 2 2006.173.06:59:31.66#ibcon#about to read 6, iclass 18, count 2 2006.173.06:59:31.66#ibcon#read 6, iclass 18, count 2 2006.173.06:59:31.66#ibcon#end of sib2, iclass 18, count 2 2006.173.06:59:31.66#ibcon#*mode == 0, iclass 18, count 2 2006.173.06:59:31.66#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.06:59:31.66#ibcon#[25=AT02-06\r\n] 2006.173.06:59:31.66#ibcon#*before write, iclass 18, count 2 2006.173.06:59:31.66#ibcon#enter sib2, iclass 18, count 2 2006.173.06:59:31.66#ibcon#flushed, iclass 18, count 2 2006.173.06:59:31.66#ibcon#about to write, iclass 18, count 2 2006.173.06:59:31.66#ibcon#wrote, iclass 18, count 2 2006.173.06:59:31.66#ibcon#about to read 3, iclass 18, count 2 2006.173.06:59:31.69#ibcon#read 3, iclass 18, count 2 2006.173.06:59:31.69#ibcon#about to read 4, iclass 18, count 2 2006.173.06:59:31.69#ibcon#read 4, iclass 18, count 2 2006.173.06:59:31.69#ibcon#about to read 5, iclass 18, count 2 2006.173.06:59:31.69#ibcon#read 5, iclass 18, count 2 2006.173.06:59:31.69#ibcon#about to read 6, iclass 18, count 2 2006.173.06:59:31.69#ibcon#read 6, iclass 18, count 2 2006.173.06:59:31.69#ibcon#end of sib2, iclass 18, count 2 2006.173.06:59:31.69#ibcon#*after write, iclass 18, count 2 2006.173.06:59:31.69#ibcon#*before return 0, iclass 18, count 2 2006.173.06:59:31.69#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.06:59:31.69#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.06:59:31.69#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.06:59:31.69#ibcon#ireg 7 cls_cnt 0 2006.173.06:59:31.69#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.06:59:31.81#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.06:59:31.81#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.06:59:31.81#ibcon#enter wrdev, iclass 18, count 0 2006.173.06:59:31.81#ibcon#first serial, iclass 18, count 0 2006.173.06:59:31.81#ibcon#enter sib2, iclass 18, count 0 2006.173.06:59:31.81#ibcon#flushed, iclass 18, count 0 2006.173.06:59:31.81#ibcon#about to write, iclass 18, count 0 2006.173.06:59:31.81#ibcon#wrote, iclass 18, count 0 2006.173.06:59:31.81#ibcon#about to read 3, iclass 18, count 0 2006.173.06:59:31.83#ibcon#read 3, iclass 18, count 0 2006.173.06:59:31.83#ibcon#about to read 4, iclass 18, count 0 2006.173.06:59:31.83#ibcon#read 4, iclass 18, count 0 2006.173.06:59:31.83#ibcon#about to read 5, iclass 18, count 0 2006.173.06:59:31.83#ibcon#read 5, iclass 18, count 0 2006.173.06:59:31.83#ibcon#about to read 6, iclass 18, count 0 2006.173.06:59:31.83#ibcon#read 6, iclass 18, count 0 2006.173.06:59:31.83#ibcon#end of sib2, iclass 18, count 0 2006.173.06:59:31.83#ibcon#*mode == 0, iclass 18, count 0 2006.173.06:59:31.83#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.06:59:31.83#ibcon#[25=USB\r\n] 2006.173.06:59:31.83#ibcon#*before write, iclass 18, count 0 2006.173.06:59:31.83#ibcon#enter sib2, iclass 18, count 0 2006.173.06:59:31.83#ibcon#flushed, iclass 18, count 0 2006.173.06:59:31.83#ibcon#about to write, iclass 18, count 0 2006.173.06:59:31.83#ibcon#wrote, iclass 18, count 0 2006.173.06:59:31.83#ibcon#about to read 3, iclass 18, count 0 2006.173.06:59:31.86#ibcon#read 3, iclass 18, count 0 2006.173.06:59:31.86#ibcon#about to read 4, iclass 18, count 0 2006.173.06:59:31.86#ibcon#read 4, iclass 18, count 0 2006.173.06:59:31.86#ibcon#about to read 5, iclass 18, count 0 2006.173.06:59:31.86#ibcon#read 5, iclass 18, count 0 2006.173.06:59:31.86#ibcon#about to read 6, iclass 18, count 0 2006.173.06:59:31.86#ibcon#read 6, iclass 18, count 0 2006.173.06:59:31.86#ibcon#end of sib2, iclass 18, count 0 2006.173.06:59:31.86#ibcon#*after write, iclass 18, count 0 2006.173.06:59:31.86#ibcon#*before return 0, iclass 18, count 0 2006.173.06:59:31.86#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.06:59:31.86#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.06:59:31.86#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.06:59:31.86#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.06:59:31.86$vck44/valo=3,564.99 2006.173.06:59:31.86#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.06:59:31.86#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.06:59:31.86#ibcon#ireg 17 cls_cnt 0 2006.173.06:59:31.86#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.06:59:31.86#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.06:59:31.86#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.06:59:31.86#ibcon#enter wrdev, iclass 20, count 0 2006.173.06:59:31.86#ibcon#first serial, iclass 20, count 0 2006.173.06:59:31.86#ibcon#enter sib2, iclass 20, count 0 2006.173.06:59:31.86#ibcon#flushed, iclass 20, count 0 2006.173.06:59:31.86#ibcon#about to write, iclass 20, count 0 2006.173.06:59:31.86#ibcon#wrote, iclass 20, count 0 2006.173.06:59:31.86#ibcon#about to read 3, iclass 20, count 0 2006.173.06:59:31.88#ibcon#read 3, iclass 20, count 0 2006.173.06:59:31.88#ibcon#about to read 4, iclass 20, count 0 2006.173.06:59:31.88#ibcon#read 4, iclass 20, count 0 2006.173.06:59:31.88#ibcon#about to read 5, iclass 20, count 0 2006.173.06:59:31.88#ibcon#read 5, iclass 20, count 0 2006.173.06:59:31.88#ibcon#about to read 6, iclass 20, count 0 2006.173.06:59:31.88#ibcon#read 6, iclass 20, count 0 2006.173.06:59:31.88#ibcon#end of sib2, iclass 20, count 0 2006.173.06:59:31.88#ibcon#*mode == 0, iclass 20, count 0 2006.173.06:59:31.88#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.06:59:31.88#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.06:59:31.88#ibcon#*before write, iclass 20, count 0 2006.173.06:59:31.88#ibcon#enter sib2, iclass 20, count 0 2006.173.06:59:31.88#ibcon#flushed, iclass 20, count 0 2006.173.06:59:31.88#ibcon#about to write, iclass 20, count 0 2006.173.06:59:31.88#ibcon#wrote, iclass 20, count 0 2006.173.06:59:31.88#ibcon#about to read 3, iclass 20, count 0 2006.173.06:59:31.92#ibcon#read 3, iclass 20, count 0 2006.173.06:59:31.92#ibcon#about to read 4, iclass 20, count 0 2006.173.06:59:31.92#ibcon#read 4, iclass 20, count 0 2006.173.06:59:31.92#ibcon#about to read 5, iclass 20, count 0 2006.173.06:59:31.92#ibcon#read 5, iclass 20, count 0 2006.173.06:59:31.92#ibcon#about to read 6, iclass 20, count 0 2006.173.06:59:31.92#ibcon#read 6, iclass 20, count 0 2006.173.06:59:31.92#ibcon#end of sib2, iclass 20, count 0 2006.173.06:59:31.92#ibcon#*after write, iclass 20, count 0 2006.173.06:59:31.92#ibcon#*before return 0, iclass 20, count 0 2006.173.06:59:31.92#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.06:59:31.92#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.06:59:31.92#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.06:59:31.92#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.06:59:31.92$vck44/va=3,5 2006.173.06:59:31.92#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.06:59:31.92#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.06:59:31.92#ibcon#ireg 11 cls_cnt 2 2006.173.06:59:31.92#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.06:59:31.98#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.06:59:31.98#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.06:59:31.98#ibcon#enter wrdev, iclass 22, count 2 2006.173.06:59:31.98#ibcon#first serial, iclass 22, count 2 2006.173.06:59:31.98#ibcon#enter sib2, iclass 22, count 2 2006.173.06:59:31.98#ibcon#flushed, iclass 22, count 2 2006.173.06:59:31.98#ibcon#about to write, iclass 22, count 2 2006.173.06:59:31.98#ibcon#wrote, iclass 22, count 2 2006.173.06:59:31.98#ibcon#about to read 3, iclass 22, count 2 2006.173.06:59:32.00#ibcon#read 3, iclass 22, count 2 2006.173.06:59:32.00#ibcon#about to read 4, iclass 22, count 2 2006.173.06:59:32.00#ibcon#read 4, iclass 22, count 2 2006.173.06:59:32.00#ibcon#about to read 5, iclass 22, count 2 2006.173.06:59:32.00#ibcon#read 5, iclass 22, count 2 2006.173.06:59:32.00#ibcon#about to read 6, iclass 22, count 2 2006.173.06:59:32.00#ibcon#read 6, iclass 22, count 2 2006.173.06:59:32.00#ibcon#end of sib2, iclass 22, count 2 2006.173.06:59:32.00#ibcon#*mode == 0, iclass 22, count 2 2006.173.06:59:32.00#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.06:59:32.00#ibcon#[25=AT03-05\r\n] 2006.173.06:59:32.00#ibcon#*before write, iclass 22, count 2 2006.173.06:59:32.00#ibcon#enter sib2, iclass 22, count 2 2006.173.06:59:32.00#ibcon#flushed, iclass 22, count 2 2006.173.06:59:32.00#ibcon#about to write, iclass 22, count 2 2006.173.06:59:32.00#ibcon#wrote, iclass 22, count 2 2006.173.06:59:32.00#ibcon#about to read 3, iclass 22, count 2 2006.173.06:59:32.03#ibcon#read 3, iclass 22, count 2 2006.173.06:59:32.03#ibcon#about to read 4, iclass 22, count 2 2006.173.06:59:32.03#ibcon#read 4, iclass 22, count 2 2006.173.06:59:32.03#ibcon#about to read 5, iclass 22, count 2 2006.173.06:59:32.03#ibcon#read 5, iclass 22, count 2 2006.173.06:59:32.03#ibcon#about to read 6, iclass 22, count 2 2006.173.06:59:32.03#ibcon#read 6, iclass 22, count 2 2006.173.06:59:32.03#ibcon#end of sib2, iclass 22, count 2 2006.173.06:59:32.03#ibcon#*after write, iclass 22, count 2 2006.173.06:59:32.03#ibcon#*before return 0, iclass 22, count 2 2006.173.06:59:32.03#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.06:59:32.03#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.06:59:32.03#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.06:59:32.03#ibcon#ireg 7 cls_cnt 0 2006.173.06:59:32.03#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.06:59:32.15#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.06:59:32.15#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.06:59:32.15#ibcon#enter wrdev, iclass 22, count 0 2006.173.06:59:32.15#ibcon#first serial, iclass 22, count 0 2006.173.06:59:32.15#ibcon#enter sib2, iclass 22, count 0 2006.173.06:59:32.15#ibcon#flushed, iclass 22, count 0 2006.173.06:59:32.15#ibcon#about to write, iclass 22, count 0 2006.173.06:59:32.15#ibcon#wrote, iclass 22, count 0 2006.173.06:59:32.15#ibcon#about to read 3, iclass 22, count 0 2006.173.06:59:32.17#ibcon#read 3, iclass 22, count 0 2006.173.06:59:32.17#ibcon#about to read 4, iclass 22, count 0 2006.173.06:59:32.17#ibcon#read 4, iclass 22, count 0 2006.173.06:59:32.17#ibcon#about to read 5, iclass 22, count 0 2006.173.06:59:32.17#ibcon#read 5, iclass 22, count 0 2006.173.06:59:32.17#ibcon#about to read 6, iclass 22, count 0 2006.173.06:59:32.17#ibcon#read 6, iclass 22, count 0 2006.173.06:59:32.17#ibcon#end of sib2, iclass 22, count 0 2006.173.06:59:32.17#ibcon#*mode == 0, iclass 22, count 0 2006.173.06:59:32.17#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.06:59:32.17#ibcon#[25=USB\r\n] 2006.173.06:59:32.17#ibcon#*before write, iclass 22, count 0 2006.173.06:59:32.17#ibcon#enter sib2, iclass 22, count 0 2006.173.06:59:32.17#ibcon#flushed, iclass 22, count 0 2006.173.06:59:32.17#ibcon#about to write, iclass 22, count 0 2006.173.06:59:32.17#ibcon#wrote, iclass 22, count 0 2006.173.06:59:32.17#ibcon#about to read 3, iclass 22, count 0 2006.173.06:59:32.20#ibcon#read 3, iclass 22, count 0 2006.173.06:59:32.20#ibcon#about to read 4, iclass 22, count 0 2006.173.06:59:32.20#ibcon#read 4, iclass 22, count 0 2006.173.06:59:32.20#ibcon#about to read 5, iclass 22, count 0 2006.173.06:59:32.20#ibcon#read 5, iclass 22, count 0 2006.173.06:59:32.20#ibcon#about to read 6, iclass 22, count 0 2006.173.06:59:32.20#ibcon#read 6, iclass 22, count 0 2006.173.06:59:32.20#ibcon#end of sib2, iclass 22, count 0 2006.173.06:59:32.20#ibcon#*after write, iclass 22, count 0 2006.173.06:59:32.20#ibcon#*before return 0, iclass 22, count 0 2006.173.06:59:32.20#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.06:59:32.20#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.06:59:32.20#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.06:59:32.20#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.06:59:32.20$vck44/valo=4,624.99 2006.173.06:59:32.20#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.06:59:32.20#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.06:59:32.20#ibcon#ireg 17 cls_cnt 0 2006.173.06:59:32.20#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.06:59:32.20#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.06:59:32.20#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.06:59:32.20#ibcon#enter wrdev, iclass 24, count 0 2006.173.06:59:32.20#ibcon#first serial, iclass 24, count 0 2006.173.06:59:32.20#ibcon#enter sib2, iclass 24, count 0 2006.173.06:59:32.20#ibcon#flushed, iclass 24, count 0 2006.173.06:59:32.20#ibcon#about to write, iclass 24, count 0 2006.173.06:59:32.20#ibcon#wrote, iclass 24, count 0 2006.173.06:59:32.20#ibcon#about to read 3, iclass 24, count 0 2006.173.06:59:32.22#ibcon#read 3, iclass 24, count 0 2006.173.06:59:32.22#ibcon#about to read 4, iclass 24, count 0 2006.173.06:59:32.22#ibcon#read 4, iclass 24, count 0 2006.173.06:59:32.22#ibcon#about to read 5, iclass 24, count 0 2006.173.06:59:32.22#ibcon#read 5, iclass 24, count 0 2006.173.06:59:32.22#ibcon#about to read 6, iclass 24, count 0 2006.173.06:59:32.22#ibcon#read 6, iclass 24, count 0 2006.173.06:59:32.22#ibcon#end of sib2, iclass 24, count 0 2006.173.06:59:32.22#ibcon#*mode == 0, iclass 24, count 0 2006.173.06:59:32.22#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.06:59:32.22#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.06:59:32.22#ibcon#*before write, iclass 24, count 0 2006.173.06:59:32.22#ibcon#enter sib2, iclass 24, count 0 2006.173.06:59:32.22#ibcon#flushed, iclass 24, count 0 2006.173.06:59:32.22#ibcon#about to write, iclass 24, count 0 2006.173.06:59:32.22#ibcon#wrote, iclass 24, count 0 2006.173.06:59:32.22#ibcon#about to read 3, iclass 24, count 0 2006.173.06:59:32.26#ibcon#read 3, iclass 24, count 0 2006.173.06:59:32.26#ibcon#about to read 4, iclass 24, count 0 2006.173.06:59:32.26#ibcon#read 4, iclass 24, count 0 2006.173.06:59:32.26#ibcon#about to read 5, iclass 24, count 0 2006.173.06:59:32.26#ibcon#read 5, iclass 24, count 0 2006.173.06:59:32.26#ibcon#about to read 6, iclass 24, count 0 2006.173.06:59:32.26#ibcon#read 6, iclass 24, count 0 2006.173.06:59:32.26#ibcon#end of sib2, iclass 24, count 0 2006.173.06:59:32.26#ibcon#*after write, iclass 24, count 0 2006.173.06:59:32.26#ibcon#*before return 0, iclass 24, count 0 2006.173.06:59:32.26#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.06:59:32.26#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.06:59:32.26#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.06:59:32.26#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.06:59:32.26$vck44/va=4,6 2006.173.06:59:32.26#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.06:59:32.26#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.06:59:32.26#ibcon#ireg 11 cls_cnt 2 2006.173.06:59:32.26#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.06:59:32.32#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.06:59:32.32#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.06:59:32.32#ibcon#enter wrdev, iclass 26, count 2 2006.173.06:59:32.32#ibcon#first serial, iclass 26, count 2 2006.173.06:59:32.32#ibcon#enter sib2, iclass 26, count 2 2006.173.06:59:32.32#ibcon#flushed, iclass 26, count 2 2006.173.06:59:32.32#ibcon#about to write, iclass 26, count 2 2006.173.06:59:32.32#ibcon#wrote, iclass 26, count 2 2006.173.06:59:32.32#ibcon#about to read 3, iclass 26, count 2 2006.173.06:59:32.34#ibcon#read 3, iclass 26, count 2 2006.173.06:59:32.34#ibcon#about to read 4, iclass 26, count 2 2006.173.06:59:32.34#ibcon#read 4, iclass 26, count 2 2006.173.06:59:32.34#ibcon#about to read 5, iclass 26, count 2 2006.173.06:59:32.34#ibcon#read 5, iclass 26, count 2 2006.173.06:59:32.34#ibcon#about to read 6, iclass 26, count 2 2006.173.06:59:32.34#ibcon#read 6, iclass 26, count 2 2006.173.06:59:32.34#ibcon#end of sib2, iclass 26, count 2 2006.173.06:59:32.34#ibcon#*mode == 0, iclass 26, count 2 2006.173.06:59:32.34#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.06:59:32.34#ibcon#[25=AT04-06\r\n] 2006.173.06:59:32.34#ibcon#*before write, iclass 26, count 2 2006.173.06:59:32.34#ibcon#enter sib2, iclass 26, count 2 2006.173.06:59:32.34#ibcon#flushed, iclass 26, count 2 2006.173.06:59:32.34#ibcon#about to write, iclass 26, count 2 2006.173.06:59:32.34#ibcon#wrote, iclass 26, count 2 2006.173.06:59:32.34#ibcon#about to read 3, iclass 26, count 2 2006.173.06:59:32.37#ibcon#read 3, iclass 26, count 2 2006.173.06:59:32.37#ibcon#about to read 4, iclass 26, count 2 2006.173.06:59:32.37#ibcon#read 4, iclass 26, count 2 2006.173.06:59:32.37#ibcon#about to read 5, iclass 26, count 2 2006.173.06:59:32.37#ibcon#read 5, iclass 26, count 2 2006.173.06:59:32.37#ibcon#about to read 6, iclass 26, count 2 2006.173.06:59:32.37#ibcon#read 6, iclass 26, count 2 2006.173.06:59:32.37#ibcon#end of sib2, iclass 26, count 2 2006.173.06:59:32.37#ibcon#*after write, iclass 26, count 2 2006.173.06:59:32.37#ibcon#*before return 0, iclass 26, count 2 2006.173.06:59:32.37#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.06:59:32.37#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.06:59:32.37#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.06:59:32.37#ibcon#ireg 7 cls_cnt 0 2006.173.06:59:32.37#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.06:59:32.49#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.06:59:32.49#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.06:59:32.49#ibcon#enter wrdev, iclass 26, count 0 2006.173.06:59:32.49#ibcon#first serial, iclass 26, count 0 2006.173.06:59:32.49#ibcon#enter sib2, iclass 26, count 0 2006.173.06:59:32.49#ibcon#flushed, iclass 26, count 0 2006.173.06:59:32.49#ibcon#about to write, iclass 26, count 0 2006.173.06:59:32.49#ibcon#wrote, iclass 26, count 0 2006.173.06:59:32.49#ibcon#about to read 3, iclass 26, count 0 2006.173.06:59:32.51#ibcon#read 3, iclass 26, count 0 2006.173.06:59:32.51#ibcon#about to read 4, iclass 26, count 0 2006.173.06:59:32.51#ibcon#read 4, iclass 26, count 0 2006.173.06:59:32.51#ibcon#about to read 5, iclass 26, count 0 2006.173.06:59:32.51#ibcon#read 5, iclass 26, count 0 2006.173.06:59:32.51#ibcon#about to read 6, iclass 26, count 0 2006.173.06:59:32.51#ibcon#read 6, iclass 26, count 0 2006.173.06:59:32.51#ibcon#end of sib2, iclass 26, count 0 2006.173.06:59:32.51#ibcon#*mode == 0, iclass 26, count 0 2006.173.06:59:32.51#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.06:59:32.51#ibcon#[25=USB\r\n] 2006.173.06:59:32.51#ibcon#*before write, iclass 26, count 0 2006.173.06:59:32.51#ibcon#enter sib2, iclass 26, count 0 2006.173.06:59:32.51#ibcon#flushed, iclass 26, count 0 2006.173.06:59:32.51#ibcon#about to write, iclass 26, count 0 2006.173.06:59:32.51#ibcon#wrote, iclass 26, count 0 2006.173.06:59:32.51#ibcon#about to read 3, iclass 26, count 0 2006.173.06:59:32.54#ibcon#read 3, iclass 26, count 0 2006.173.06:59:32.54#ibcon#about to read 4, iclass 26, count 0 2006.173.06:59:32.54#ibcon#read 4, iclass 26, count 0 2006.173.06:59:32.54#ibcon#about to read 5, iclass 26, count 0 2006.173.06:59:32.54#ibcon#read 5, iclass 26, count 0 2006.173.06:59:32.54#ibcon#about to read 6, iclass 26, count 0 2006.173.06:59:32.54#ibcon#read 6, iclass 26, count 0 2006.173.06:59:32.54#ibcon#end of sib2, iclass 26, count 0 2006.173.06:59:32.54#ibcon#*after write, iclass 26, count 0 2006.173.06:59:32.54#ibcon#*before return 0, iclass 26, count 0 2006.173.06:59:32.54#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.06:59:32.54#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.06:59:32.54#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.06:59:32.54#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.06:59:32.54$vck44/valo=5,734.99 2006.173.06:59:32.54#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.06:59:32.54#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.06:59:32.54#ibcon#ireg 17 cls_cnt 0 2006.173.06:59:32.54#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.06:59:32.54#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.06:59:32.54#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.06:59:32.54#ibcon#enter wrdev, iclass 28, count 0 2006.173.06:59:32.54#ibcon#first serial, iclass 28, count 0 2006.173.06:59:32.54#ibcon#enter sib2, iclass 28, count 0 2006.173.06:59:32.54#ibcon#flushed, iclass 28, count 0 2006.173.06:59:32.54#ibcon#about to write, iclass 28, count 0 2006.173.06:59:32.54#ibcon#wrote, iclass 28, count 0 2006.173.06:59:32.54#ibcon#about to read 3, iclass 28, count 0 2006.173.06:59:32.56#ibcon#read 3, iclass 28, count 0 2006.173.06:59:32.56#ibcon#about to read 4, iclass 28, count 0 2006.173.06:59:32.56#ibcon#read 4, iclass 28, count 0 2006.173.06:59:32.56#ibcon#about to read 5, iclass 28, count 0 2006.173.06:59:32.56#ibcon#read 5, iclass 28, count 0 2006.173.06:59:32.56#ibcon#about to read 6, iclass 28, count 0 2006.173.06:59:32.56#ibcon#read 6, iclass 28, count 0 2006.173.06:59:32.56#ibcon#end of sib2, iclass 28, count 0 2006.173.06:59:32.56#ibcon#*mode == 0, iclass 28, count 0 2006.173.06:59:32.56#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.06:59:32.56#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.06:59:32.56#ibcon#*before write, iclass 28, count 0 2006.173.06:59:32.56#ibcon#enter sib2, iclass 28, count 0 2006.173.06:59:32.56#ibcon#flushed, iclass 28, count 0 2006.173.06:59:32.56#ibcon#about to write, iclass 28, count 0 2006.173.06:59:32.56#ibcon#wrote, iclass 28, count 0 2006.173.06:59:32.56#ibcon#about to read 3, iclass 28, count 0 2006.173.06:59:32.60#ibcon#read 3, iclass 28, count 0 2006.173.06:59:32.60#ibcon#about to read 4, iclass 28, count 0 2006.173.06:59:32.60#ibcon#read 4, iclass 28, count 0 2006.173.06:59:32.60#ibcon#about to read 5, iclass 28, count 0 2006.173.06:59:32.60#ibcon#read 5, iclass 28, count 0 2006.173.06:59:32.60#ibcon#about to read 6, iclass 28, count 0 2006.173.06:59:32.60#ibcon#read 6, iclass 28, count 0 2006.173.06:59:32.60#ibcon#end of sib2, iclass 28, count 0 2006.173.06:59:32.60#ibcon#*after write, iclass 28, count 0 2006.173.06:59:32.60#ibcon#*before return 0, iclass 28, count 0 2006.173.06:59:32.60#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.06:59:32.60#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.06:59:32.60#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.06:59:32.60#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.06:59:32.60$vck44/va=5,4 2006.173.06:59:32.60#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.06:59:32.60#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.06:59:32.60#ibcon#ireg 11 cls_cnt 2 2006.173.06:59:32.60#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.06:59:32.66#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.06:59:32.66#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.06:59:32.66#ibcon#enter wrdev, iclass 30, count 2 2006.173.06:59:32.66#ibcon#first serial, iclass 30, count 2 2006.173.06:59:32.66#ibcon#enter sib2, iclass 30, count 2 2006.173.06:59:32.66#ibcon#flushed, iclass 30, count 2 2006.173.06:59:32.66#ibcon#about to write, iclass 30, count 2 2006.173.06:59:32.66#ibcon#wrote, iclass 30, count 2 2006.173.06:59:32.66#ibcon#about to read 3, iclass 30, count 2 2006.173.06:59:32.68#ibcon#read 3, iclass 30, count 2 2006.173.06:59:32.68#ibcon#about to read 4, iclass 30, count 2 2006.173.06:59:32.68#ibcon#read 4, iclass 30, count 2 2006.173.06:59:32.68#ibcon#about to read 5, iclass 30, count 2 2006.173.06:59:32.68#ibcon#read 5, iclass 30, count 2 2006.173.06:59:32.68#ibcon#about to read 6, iclass 30, count 2 2006.173.06:59:32.68#ibcon#read 6, iclass 30, count 2 2006.173.06:59:32.68#ibcon#end of sib2, iclass 30, count 2 2006.173.06:59:32.68#ibcon#*mode == 0, iclass 30, count 2 2006.173.06:59:32.68#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.06:59:32.68#ibcon#[25=AT05-04\r\n] 2006.173.06:59:32.68#ibcon#*before write, iclass 30, count 2 2006.173.06:59:32.68#ibcon#enter sib2, iclass 30, count 2 2006.173.06:59:32.68#ibcon#flushed, iclass 30, count 2 2006.173.06:59:32.68#ibcon#about to write, iclass 30, count 2 2006.173.06:59:32.68#ibcon#wrote, iclass 30, count 2 2006.173.06:59:32.68#ibcon#about to read 3, iclass 30, count 2 2006.173.06:59:32.71#ibcon#read 3, iclass 30, count 2 2006.173.06:59:32.71#ibcon#about to read 4, iclass 30, count 2 2006.173.06:59:32.71#ibcon#read 4, iclass 30, count 2 2006.173.06:59:32.71#ibcon#about to read 5, iclass 30, count 2 2006.173.06:59:32.71#ibcon#read 5, iclass 30, count 2 2006.173.06:59:32.71#ibcon#about to read 6, iclass 30, count 2 2006.173.06:59:32.71#ibcon#read 6, iclass 30, count 2 2006.173.06:59:32.71#ibcon#end of sib2, iclass 30, count 2 2006.173.06:59:32.71#ibcon#*after write, iclass 30, count 2 2006.173.06:59:32.71#ibcon#*before return 0, iclass 30, count 2 2006.173.06:59:32.71#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.06:59:32.71#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.06:59:32.71#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.06:59:32.71#ibcon#ireg 7 cls_cnt 0 2006.173.06:59:32.71#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.06:59:32.83#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.06:59:32.83#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.06:59:32.83#ibcon#enter wrdev, iclass 30, count 0 2006.173.06:59:32.83#ibcon#first serial, iclass 30, count 0 2006.173.06:59:32.83#ibcon#enter sib2, iclass 30, count 0 2006.173.06:59:32.83#ibcon#flushed, iclass 30, count 0 2006.173.06:59:32.83#ibcon#about to write, iclass 30, count 0 2006.173.06:59:32.83#ibcon#wrote, iclass 30, count 0 2006.173.06:59:32.83#ibcon#about to read 3, iclass 30, count 0 2006.173.06:59:32.85#ibcon#read 3, iclass 30, count 0 2006.173.06:59:32.85#ibcon#about to read 4, iclass 30, count 0 2006.173.06:59:32.85#ibcon#read 4, iclass 30, count 0 2006.173.06:59:32.85#ibcon#about to read 5, iclass 30, count 0 2006.173.06:59:32.85#ibcon#read 5, iclass 30, count 0 2006.173.06:59:32.85#ibcon#about to read 6, iclass 30, count 0 2006.173.06:59:32.85#ibcon#read 6, iclass 30, count 0 2006.173.06:59:32.85#ibcon#end of sib2, iclass 30, count 0 2006.173.06:59:32.85#ibcon#*mode == 0, iclass 30, count 0 2006.173.06:59:32.85#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.06:59:32.85#ibcon#[25=USB\r\n] 2006.173.06:59:32.85#ibcon#*before write, iclass 30, count 0 2006.173.06:59:32.85#ibcon#enter sib2, iclass 30, count 0 2006.173.06:59:32.85#ibcon#flushed, iclass 30, count 0 2006.173.06:59:32.85#ibcon#about to write, iclass 30, count 0 2006.173.06:59:32.85#ibcon#wrote, iclass 30, count 0 2006.173.06:59:32.85#ibcon#about to read 3, iclass 30, count 0 2006.173.06:59:32.88#ibcon#read 3, iclass 30, count 0 2006.173.06:59:32.88#ibcon#about to read 4, iclass 30, count 0 2006.173.06:59:32.88#ibcon#read 4, iclass 30, count 0 2006.173.06:59:32.88#ibcon#about to read 5, iclass 30, count 0 2006.173.06:59:32.88#ibcon#read 5, iclass 30, count 0 2006.173.06:59:32.88#ibcon#about to read 6, iclass 30, count 0 2006.173.06:59:32.88#ibcon#read 6, iclass 30, count 0 2006.173.06:59:32.88#ibcon#end of sib2, iclass 30, count 0 2006.173.06:59:32.88#ibcon#*after write, iclass 30, count 0 2006.173.06:59:32.88#ibcon#*before return 0, iclass 30, count 0 2006.173.06:59:32.88#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.06:59:32.88#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.06:59:32.88#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.06:59:32.88#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.06:59:32.88$vck44/valo=6,814.99 2006.173.06:59:32.88#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.06:59:32.88#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.06:59:32.88#ibcon#ireg 17 cls_cnt 0 2006.173.06:59:32.88#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.06:59:32.88#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.06:59:32.88#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.06:59:32.88#ibcon#enter wrdev, iclass 32, count 0 2006.173.06:59:32.88#ibcon#first serial, iclass 32, count 0 2006.173.06:59:32.88#ibcon#enter sib2, iclass 32, count 0 2006.173.06:59:32.88#ibcon#flushed, iclass 32, count 0 2006.173.06:59:32.88#ibcon#about to write, iclass 32, count 0 2006.173.06:59:32.88#ibcon#wrote, iclass 32, count 0 2006.173.06:59:32.88#ibcon#about to read 3, iclass 32, count 0 2006.173.06:59:32.90#ibcon#read 3, iclass 32, count 0 2006.173.06:59:32.90#ibcon#about to read 4, iclass 32, count 0 2006.173.06:59:32.90#ibcon#read 4, iclass 32, count 0 2006.173.06:59:32.90#ibcon#about to read 5, iclass 32, count 0 2006.173.06:59:32.90#ibcon#read 5, iclass 32, count 0 2006.173.06:59:32.90#ibcon#about to read 6, iclass 32, count 0 2006.173.06:59:32.90#ibcon#read 6, iclass 32, count 0 2006.173.06:59:32.90#ibcon#end of sib2, iclass 32, count 0 2006.173.06:59:32.90#ibcon#*mode == 0, iclass 32, count 0 2006.173.06:59:32.90#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.06:59:32.90#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.06:59:32.90#ibcon#*before write, iclass 32, count 0 2006.173.06:59:32.90#ibcon#enter sib2, iclass 32, count 0 2006.173.06:59:32.90#ibcon#flushed, iclass 32, count 0 2006.173.06:59:32.90#ibcon#about to write, iclass 32, count 0 2006.173.06:59:32.90#ibcon#wrote, iclass 32, count 0 2006.173.06:59:32.90#ibcon#about to read 3, iclass 32, count 0 2006.173.06:59:32.94#ibcon#read 3, iclass 32, count 0 2006.173.06:59:32.94#ibcon#about to read 4, iclass 32, count 0 2006.173.06:59:32.94#ibcon#read 4, iclass 32, count 0 2006.173.06:59:32.94#ibcon#about to read 5, iclass 32, count 0 2006.173.06:59:32.94#ibcon#read 5, iclass 32, count 0 2006.173.06:59:32.94#ibcon#about to read 6, iclass 32, count 0 2006.173.06:59:32.94#ibcon#read 6, iclass 32, count 0 2006.173.06:59:32.94#ibcon#end of sib2, iclass 32, count 0 2006.173.06:59:32.94#ibcon#*after write, iclass 32, count 0 2006.173.06:59:32.94#ibcon#*before return 0, iclass 32, count 0 2006.173.06:59:32.94#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.06:59:32.94#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.06:59:32.94#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.06:59:32.94#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.06:59:32.94$vck44/va=6,3 2006.173.06:59:32.94#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.06:59:32.94#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.06:59:32.94#ibcon#ireg 11 cls_cnt 2 2006.173.06:59:32.94#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.06:59:33.00#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.06:59:33.00#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.06:59:33.00#ibcon#enter wrdev, iclass 34, count 2 2006.173.06:59:33.00#ibcon#first serial, iclass 34, count 2 2006.173.06:59:33.00#ibcon#enter sib2, iclass 34, count 2 2006.173.06:59:33.00#ibcon#flushed, iclass 34, count 2 2006.173.06:59:33.00#ibcon#about to write, iclass 34, count 2 2006.173.06:59:33.00#ibcon#wrote, iclass 34, count 2 2006.173.06:59:33.00#ibcon#about to read 3, iclass 34, count 2 2006.173.06:59:33.02#ibcon#read 3, iclass 34, count 2 2006.173.06:59:33.02#ibcon#about to read 4, iclass 34, count 2 2006.173.06:59:33.02#ibcon#read 4, iclass 34, count 2 2006.173.06:59:33.02#ibcon#about to read 5, iclass 34, count 2 2006.173.06:59:33.02#ibcon#read 5, iclass 34, count 2 2006.173.06:59:33.02#ibcon#about to read 6, iclass 34, count 2 2006.173.06:59:33.02#ibcon#read 6, iclass 34, count 2 2006.173.06:59:33.02#ibcon#end of sib2, iclass 34, count 2 2006.173.06:59:33.02#ibcon#*mode == 0, iclass 34, count 2 2006.173.06:59:33.02#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.06:59:33.02#ibcon#[25=AT06-03\r\n] 2006.173.06:59:33.02#ibcon#*before write, iclass 34, count 2 2006.173.06:59:33.02#ibcon#enter sib2, iclass 34, count 2 2006.173.06:59:33.02#ibcon#flushed, iclass 34, count 2 2006.173.06:59:33.02#ibcon#about to write, iclass 34, count 2 2006.173.06:59:33.02#ibcon#wrote, iclass 34, count 2 2006.173.06:59:33.02#ibcon#about to read 3, iclass 34, count 2 2006.173.06:59:33.05#ibcon#read 3, iclass 34, count 2 2006.173.06:59:33.05#ibcon#about to read 4, iclass 34, count 2 2006.173.06:59:33.05#ibcon#read 4, iclass 34, count 2 2006.173.06:59:33.05#ibcon#about to read 5, iclass 34, count 2 2006.173.06:59:33.05#ibcon#read 5, iclass 34, count 2 2006.173.06:59:33.05#ibcon#about to read 6, iclass 34, count 2 2006.173.06:59:33.05#ibcon#read 6, iclass 34, count 2 2006.173.06:59:33.05#ibcon#end of sib2, iclass 34, count 2 2006.173.06:59:33.05#ibcon#*after write, iclass 34, count 2 2006.173.06:59:33.05#ibcon#*before return 0, iclass 34, count 2 2006.173.06:59:33.05#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.06:59:33.05#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.06:59:33.05#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.06:59:33.05#ibcon#ireg 7 cls_cnt 0 2006.173.06:59:33.05#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.06:59:33.17#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.06:59:33.17#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.06:59:33.17#ibcon#enter wrdev, iclass 34, count 0 2006.173.06:59:33.17#ibcon#first serial, iclass 34, count 0 2006.173.06:59:33.17#ibcon#enter sib2, iclass 34, count 0 2006.173.06:59:33.17#ibcon#flushed, iclass 34, count 0 2006.173.06:59:33.17#ibcon#about to write, iclass 34, count 0 2006.173.06:59:33.17#ibcon#wrote, iclass 34, count 0 2006.173.06:59:33.17#ibcon#about to read 3, iclass 34, count 0 2006.173.06:59:33.19#ibcon#read 3, iclass 34, count 0 2006.173.06:59:33.19#ibcon#about to read 4, iclass 34, count 0 2006.173.06:59:33.19#ibcon#read 4, iclass 34, count 0 2006.173.06:59:33.19#ibcon#about to read 5, iclass 34, count 0 2006.173.06:59:33.19#ibcon#read 5, iclass 34, count 0 2006.173.06:59:33.19#ibcon#about to read 6, iclass 34, count 0 2006.173.06:59:33.19#ibcon#read 6, iclass 34, count 0 2006.173.06:59:33.19#ibcon#end of sib2, iclass 34, count 0 2006.173.06:59:33.19#ibcon#*mode == 0, iclass 34, count 0 2006.173.06:59:33.19#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.06:59:33.19#ibcon#[25=USB\r\n] 2006.173.06:59:33.19#ibcon#*before write, iclass 34, count 0 2006.173.06:59:33.19#ibcon#enter sib2, iclass 34, count 0 2006.173.06:59:33.19#ibcon#flushed, iclass 34, count 0 2006.173.06:59:33.19#ibcon#about to write, iclass 34, count 0 2006.173.06:59:33.19#ibcon#wrote, iclass 34, count 0 2006.173.06:59:33.19#ibcon#about to read 3, iclass 34, count 0 2006.173.06:59:33.22#ibcon#read 3, iclass 34, count 0 2006.173.06:59:33.22#ibcon#about to read 4, iclass 34, count 0 2006.173.06:59:33.22#ibcon#read 4, iclass 34, count 0 2006.173.06:59:33.22#ibcon#about to read 5, iclass 34, count 0 2006.173.06:59:33.22#ibcon#read 5, iclass 34, count 0 2006.173.06:59:33.22#ibcon#about to read 6, iclass 34, count 0 2006.173.06:59:33.22#ibcon#read 6, iclass 34, count 0 2006.173.06:59:33.22#ibcon#end of sib2, iclass 34, count 0 2006.173.06:59:33.22#ibcon#*after write, iclass 34, count 0 2006.173.06:59:33.22#ibcon#*before return 0, iclass 34, count 0 2006.173.06:59:33.22#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.06:59:33.22#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.06:59:33.22#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.06:59:33.22#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.06:59:33.22$vck44/valo=7,864.99 2006.173.06:59:33.22#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.06:59:33.22#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.06:59:33.22#ibcon#ireg 17 cls_cnt 0 2006.173.06:59:33.22#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.06:59:33.22#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.06:59:33.22#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.06:59:33.22#ibcon#enter wrdev, iclass 36, count 0 2006.173.06:59:33.22#ibcon#first serial, iclass 36, count 0 2006.173.06:59:33.22#ibcon#enter sib2, iclass 36, count 0 2006.173.06:59:33.22#ibcon#flushed, iclass 36, count 0 2006.173.06:59:33.22#ibcon#about to write, iclass 36, count 0 2006.173.06:59:33.22#ibcon#wrote, iclass 36, count 0 2006.173.06:59:33.22#ibcon#about to read 3, iclass 36, count 0 2006.173.06:59:33.24#ibcon#read 3, iclass 36, count 0 2006.173.06:59:33.24#ibcon#about to read 4, iclass 36, count 0 2006.173.06:59:33.24#ibcon#read 4, iclass 36, count 0 2006.173.06:59:33.24#ibcon#about to read 5, iclass 36, count 0 2006.173.06:59:33.24#ibcon#read 5, iclass 36, count 0 2006.173.06:59:33.24#ibcon#about to read 6, iclass 36, count 0 2006.173.06:59:33.24#ibcon#read 6, iclass 36, count 0 2006.173.06:59:33.24#ibcon#end of sib2, iclass 36, count 0 2006.173.06:59:33.24#ibcon#*mode == 0, iclass 36, count 0 2006.173.06:59:33.24#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.06:59:33.24#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.06:59:33.24#ibcon#*before write, iclass 36, count 0 2006.173.06:59:33.24#ibcon#enter sib2, iclass 36, count 0 2006.173.06:59:33.24#ibcon#flushed, iclass 36, count 0 2006.173.06:59:33.24#ibcon#about to write, iclass 36, count 0 2006.173.06:59:33.24#ibcon#wrote, iclass 36, count 0 2006.173.06:59:33.24#ibcon#about to read 3, iclass 36, count 0 2006.173.06:59:33.28#ibcon#read 3, iclass 36, count 0 2006.173.06:59:33.28#ibcon#about to read 4, iclass 36, count 0 2006.173.06:59:33.28#ibcon#read 4, iclass 36, count 0 2006.173.06:59:33.28#ibcon#about to read 5, iclass 36, count 0 2006.173.06:59:33.28#ibcon#read 5, iclass 36, count 0 2006.173.06:59:33.28#ibcon#about to read 6, iclass 36, count 0 2006.173.06:59:33.28#ibcon#read 6, iclass 36, count 0 2006.173.06:59:33.28#ibcon#end of sib2, iclass 36, count 0 2006.173.06:59:33.28#ibcon#*after write, iclass 36, count 0 2006.173.06:59:33.28#ibcon#*before return 0, iclass 36, count 0 2006.173.06:59:33.28#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.06:59:33.28#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.06:59:33.28#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.06:59:33.28#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.06:59:33.28$vck44/va=7,4 2006.173.06:59:33.28#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.06:59:33.28#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.06:59:33.28#ibcon#ireg 11 cls_cnt 2 2006.173.06:59:33.28#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.06:59:33.34#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.06:59:33.34#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.06:59:33.34#ibcon#enter wrdev, iclass 38, count 2 2006.173.06:59:33.34#ibcon#first serial, iclass 38, count 2 2006.173.06:59:33.34#ibcon#enter sib2, iclass 38, count 2 2006.173.06:59:33.34#ibcon#flushed, iclass 38, count 2 2006.173.06:59:33.34#ibcon#about to write, iclass 38, count 2 2006.173.06:59:33.34#ibcon#wrote, iclass 38, count 2 2006.173.06:59:33.34#ibcon#about to read 3, iclass 38, count 2 2006.173.06:59:33.36#ibcon#read 3, iclass 38, count 2 2006.173.06:59:33.36#ibcon#about to read 4, iclass 38, count 2 2006.173.06:59:33.36#ibcon#read 4, iclass 38, count 2 2006.173.06:59:33.36#ibcon#about to read 5, iclass 38, count 2 2006.173.06:59:33.36#ibcon#read 5, iclass 38, count 2 2006.173.06:59:33.36#ibcon#about to read 6, iclass 38, count 2 2006.173.06:59:33.36#ibcon#read 6, iclass 38, count 2 2006.173.06:59:33.36#ibcon#end of sib2, iclass 38, count 2 2006.173.06:59:33.36#ibcon#*mode == 0, iclass 38, count 2 2006.173.06:59:33.36#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.06:59:33.36#ibcon#[25=AT07-04\r\n] 2006.173.06:59:33.36#ibcon#*before write, iclass 38, count 2 2006.173.06:59:33.36#ibcon#enter sib2, iclass 38, count 2 2006.173.06:59:33.36#ibcon#flushed, iclass 38, count 2 2006.173.06:59:33.36#ibcon#about to write, iclass 38, count 2 2006.173.06:59:33.36#ibcon#wrote, iclass 38, count 2 2006.173.06:59:33.36#ibcon#about to read 3, iclass 38, count 2 2006.173.06:59:33.39#ibcon#read 3, iclass 38, count 2 2006.173.06:59:33.39#ibcon#about to read 4, iclass 38, count 2 2006.173.06:59:33.39#ibcon#read 4, iclass 38, count 2 2006.173.06:59:33.39#ibcon#about to read 5, iclass 38, count 2 2006.173.06:59:33.39#ibcon#read 5, iclass 38, count 2 2006.173.06:59:33.39#ibcon#about to read 6, iclass 38, count 2 2006.173.06:59:33.39#ibcon#read 6, iclass 38, count 2 2006.173.06:59:33.39#ibcon#end of sib2, iclass 38, count 2 2006.173.06:59:33.39#ibcon#*after write, iclass 38, count 2 2006.173.06:59:33.39#ibcon#*before return 0, iclass 38, count 2 2006.173.06:59:33.39#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.06:59:33.39#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.06:59:33.39#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.06:59:33.39#ibcon#ireg 7 cls_cnt 0 2006.173.06:59:33.39#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.06:59:33.51#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.06:59:33.51#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.06:59:33.51#ibcon#enter wrdev, iclass 38, count 0 2006.173.06:59:33.51#ibcon#first serial, iclass 38, count 0 2006.173.06:59:33.51#ibcon#enter sib2, iclass 38, count 0 2006.173.06:59:33.51#ibcon#flushed, iclass 38, count 0 2006.173.06:59:33.51#ibcon#about to write, iclass 38, count 0 2006.173.06:59:33.51#ibcon#wrote, iclass 38, count 0 2006.173.06:59:33.51#ibcon#about to read 3, iclass 38, count 0 2006.173.06:59:33.53#ibcon#read 3, iclass 38, count 0 2006.173.06:59:33.53#ibcon#about to read 4, iclass 38, count 0 2006.173.06:59:33.53#ibcon#read 4, iclass 38, count 0 2006.173.06:59:33.53#ibcon#about to read 5, iclass 38, count 0 2006.173.06:59:33.53#ibcon#read 5, iclass 38, count 0 2006.173.06:59:33.53#ibcon#about to read 6, iclass 38, count 0 2006.173.06:59:33.53#ibcon#read 6, iclass 38, count 0 2006.173.06:59:33.53#ibcon#end of sib2, iclass 38, count 0 2006.173.06:59:33.53#ibcon#*mode == 0, iclass 38, count 0 2006.173.06:59:33.53#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.06:59:33.53#ibcon#[25=USB\r\n] 2006.173.06:59:33.53#ibcon#*before write, iclass 38, count 0 2006.173.06:59:33.53#ibcon#enter sib2, iclass 38, count 0 2006.173.06:59:33.53#ibcon#flushed, iclass 38, count 0 2006.173.06:59:33.53#ibcon#about to write, iclass 38, count 0 2006.173.06:59:33.53#ibcon#wrote, iclass 38, count 0 2006.173.06:59:33.53#ibcon#about to read 3, iclass 38, count 0 2006.173.06:59:33.56#ibcon#read 3, iclass 38, count 0 2006.173.06:59:33.56#ibcon#about to read 4, iclass 38, count 0 2006.173.06:59:33.56#ibcon#read 4, iclass 38, count 0 2006.173.06:59:33.56#ibcon#about to read 5, iclass 38, count 0 2006.173.06:59:33.56#ibcon#read 5, iclass 38, count 0 2006.173.06:59:33.56#ibcon#about to read 6, iclass 38, count 0 2006.173.06:59:33.56#ibcon#read 6, iclass 38, count 0 2006.173.06:59:33.56#ibcon#end of sib2, iclass 38, count 0 2006.173.06:59:33.56#ibcon#*after write, iclass 38, count 0 2006.173.06:59:33.56#ibcon#*before return 0, iclass 38, count 0 2006.173.06:59:33.56#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.06:59:33.56#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.06:59:33.56#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.06:59:33.56#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.06:59:33.56$vck44/valo=8,884.99 2006.173.06:59:33.56#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.06:59:33.56#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.06:59:33.56#ibcon#ireg 17 cls_cnt 0 2006.173.06:59:33.56#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.06:59:33.56#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.06:59:33.56#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.06:59:33.56#ibcon#enter wrdev, iclass 40, count 0 2006.173.06:59:33.56#ibcon#first serial, iclass 40, count 0 2006.173.06:59:33.56#ibcon#enter sib2, iclass 40, count 0 2006.173.06:59:33.56#ibcon#flushed, iclass 40, count 0 2006.173.06:59:33.56#ibcon#about to write, iclass 40, count 0 2006.173.06:59:33.56#ibcon#wrote, iclass 40, count 0 2006.173.06:59:33.56#ibcon#about to read 3, iclass 40, count 0 2006.173.06:59:33.58#ibcon#read 3, iclass 40, count 0 2006.173.06:59:33.58#ibcon#about to read 4, iclass 40, count 0 2006.173.06:59:33.58#ibcon#read 4, iclass 40, count 0 2006.173.06:59:33.58#ibcon#about to read 5, iclass 40, count 0 2006.173.06:59:33.58#ibcon#read 5, iclass 40, count 0 2006.173.06:59:33.58#ibcon#about to read 6, iclass 40, count 0 2006.173.06:59:33.58#ibcon#read 6, iclass 40, count 0 2006.173.06:59:33.58#ibcon#end of sib2, iclass 40, count 0 2006.173.06:59:33.58#ibcon#*mode == 0, iclass 40, count 0 2006.173.06:59:33.58#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.06:59:33.58#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.06:59:33.58#ibcon#*before write, iclass 40, count 0 2006.173.06:59:33.58#ibcon#enter sib2, iclass 40, count 0 2006.173.06:59:33.58#ibcon#flushed, iclass 40, count 0 2006.173.06:59:33.58#ibcon#about to write, iclass 40, count 0 2006.173.06:59:33.58#ibcon#wrote, iclass 40, count 0 2006.173.06:59:33.58#ibcon#about to read 3, iclass 40, count 0 2006.173.06:59:33.62#ibcon#read 3, iclass 40, count 0 2006.173.06:59:33.62#ibcon#about to read 4, iclass 40, count 0 2006.173.06:59:33.62#ibcon#read 4, iclass 40, count 0 2006.173.06:59:33.62#ibcon#about to read 5, iclass 40, count 0 2006.173.06:59:33.62#ibcon#read 5, iclass 40, count 0 2006.173.06:59:33.62#ibcon#about to read 6, iclass 40, count 0 2006.173.06:59:33.62#ibcon#read 6, iclass 40, count 0 2006.173.06:59:33.62#ibcon#end of sib2, iclass 40, count 0 2006.173.06:59:33.62#ibcon#*after write, iclass 40, count 0 2006.173.06:59:33.62#ibcon#*before return 0, iclass 40, count 0 2006.173.06:59:33.62#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.06:59:33.62#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.06:59:33.62#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.06:59:33.62#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.06:59:33.62$vck44/va=8,4 2006.173.06:59:33.62#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.06:59:33.62#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.06:59:33.62#ibcon#ireg 11 cls_cnt 2 2006.173.06:59:33.62#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.06:59:33.68#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.06:59:33.68#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.06:59:33.68#ibcon#enter wrdev, iclass 4, count 2 2006.173.06:59:33.68#ibcon#first serial, iclass 4, count 2 2006.173.06:59:33.68#ibcon#enter sib2, iclass 4, count 2 2006.173.06:59:33.68#ibcon#flushed, iclass 4, count 2 2006.173.06:59:33.68#ibcon#about to write, iclass 4, count 2 2006.173.06:59:33.68#ibcon#wrote, iclass 4, count 2 2006.173.06:59:33.68#ibcon#about to read 3, iclass 4, count 2 2006.173.06:59:33.70#ibcon#read 3, iclass 4, count 2 2006.173.06:59:33.70#ibcon#about to read 4, iclass 4, count 2 2006.173.06:59:33.70#ibcon#read 4, iclass 4, count 2 2006.173.06:59:33.70#ibcon#about to read 5, iclass 4, count 2 2006.173.06:59:33.70#ibcon#read 5, iclass 4, count 2 2006.173.06:59:33.70#ibcon#about to read 6, iclass 4, count 2 2006.173.06:59:33.70#ibcon#read 6, iclass 4, count 2 2006.173.06:59:33.70#ibcon#end of sib2, iclass 4, count 2 2006.173.06:59:33.70#ibcon#*mode == 0, iclass 4, count 2 2006.173.06:59:33.70#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.06:59:33.70#ibcon#[25=AT08-04\r\n] 2006.173.06:59:33.70#ibcon#*before write, iclass 4, count 2 2006.173.06:59:33.70#ibcon#enter sib2, iclass 4, count 2 2006.173.06:59:33.70#ibcon#flushed, iclass 4, count 2 2006.173.06:59:33.70#ibcon#about to write, iclass 4, count 2 2006.173.06:59:33.70#ibcon#wrote, iclass 4, count 2 2006.173.06:59:33.70#ibcon#about to read 3, iclass 4, count 2 2006.173.06:59:33.73#ibcon#read 3, iclass 4, count 2 2006.173.06:59:33.73#ibcon#about to read 4, iclass 4, count 2 2006.173.06:59:33.73#ibcon#read 4, iclass 4, count 2 2006.173.06:59:33.73#ibcon#about to read 5, iclass 4, count 2 2006.173.06:59:33.73#ibcon#read 5, iclass 4, count 2 2006.173.06:59:33.73#ibcon#about to read 6, iclass 4, count 2 2006.173.06:59:33.73#ibcon#read 6, iclass 4, count 2 2006.173.06:59:33.73#ibcon#end of sib2, iclass 4, count 2 2006.173.06:59:33.73#ibcon#*after write, iclass 4, count 2 2006.173.06:59:33.73#ibcon#*before return 0, iclass 4, count 2 2006.173.06:59:33.73#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.06:59:33.73#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.06:59:33.73#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.06:59:33.73#ibcon#ireg 7 cls_cnt 0 2006.173.06:59:33.73#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.06:59:33.85#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.06:59:33.85#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.06:59:33.85#ibcon#enter wrdev, iclass 4, count 0 2006.173.06:59:33.85#ibcon#first serial, iclass 4, count 0 2006.173.06:59:33.85#ibcon#enter sib2, iclass 4, count 0 2006.173.06:59:33.85#ibcon#flushed, iclass 4, count 0 2006.173.06:59:33.85#ibcon#about to write, iclass 4, count 0 2006.173.06:59:33.85#ibcon#wrote, iclass 4, count 0 2006.173.06:59:33.85#ibcon#about to read 3, iclass 4, count 0 2006.173.06:59:33.87#ibcon#read 3, iclass 4, count 0 2006.173.06:59:33.87#ibcon#about to read 4, iclass 4, count 0 2006.173.06:59:33.87#ibcon#read 4, iclass 4, count 0 2006.173.06:59:33.87#ibcon#about to read 5, iclass 4, count 0 2006.173.06:59:33.87#ibcon#read 5, iclass 4, count 0 2006.173.06:59:33.87#ibcon#about to read 6, iclass 4, count 0 2006.173.06:59:33.87#ibcon#read 6, iclass 4, count 0 2006.173.06:59:33.87#ibcon#end of sib2, iclass 4, count 0 2006.173.06:59:33.87#ibcon#*mode == 0, iclass 4, count 0 2006.173.06:59:33.87#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.06:59:33.87#ibcon#[25=USB\r\n] 2006.173.06:59:33.87#ibcon#*before write, iclass 4, count 0 2006.173.06:59:33.87#ibcon#enter sib2, iclass 4, count 0 2006.173.06:59:33.87#ibcon#flushed, iclass 4, count 0 2006.173.06:59:33.87#ibcon#about to write, iclass 4, count 0 2006.173.06:59:33.87#ibcon#wrote, iclass 4, count 0 2006.173.06:59:33.87#ibcon#about to read 3, iclass 4, count 0 2006.173.06:59:33.90#ibcon#read 3, iclass 4, count 0 2006.173.06:59:33.90#ibcon#about to read 4, iclass 4, count 0 2006.173.06:59:33.90#ibcon#read 4, iclass 4, count 0 2006.173.06:59:33.90#ibcon#about to read 5, iclass 4, count 0 2006.173.06:59:33.90#ibcon#read 5, iclass 4, count 0 2006.173.06:59:33.90#ibcon#about to read 6, iclass 4, count 0 2006.173.06:59:33.90#ibcon#read 6, iclass 4, count 0 2006.173.06:59:33.90#ibcon#end of sib2, iclass 4, count 0 2006.173.06:59:33.90#ibcon#*after write, iclass 4, count 0 2006.173.06:59:33.90#ibcon#*before return 0, iclass 4, count 0 2006.173.06:59:33.90#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.06:59:33.90#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.06:59:33.90#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.06:59:33.90#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.06:59:33.90$vck44/vblo=1,629.99 2006.173.06:59:33.90#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.06:59:33.90#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.06:59:33.90#ibcon#ireg 17 cls_cnt 0 2006.173.06:59:33.90#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.06:59:33.90#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.06:59:33.90#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.06:59:33.90#ibcon#enter wrdev, iclass 6, count 0 2006.173.06:59:33.90#ibcon#first serial, iclass 6, count 0 2006.173.06:59:33.90#ibcon#enter sib2, iclass 6, count 0 2006.173.06:59:33.90#ibcon#flushed, iclass 6, count 0 2006.173.06:59:33.90#ibcon#about to write, iclass 6, count 0 2006.173.06:59:33.90#ibcon#wrote, iclass 6, count 0 2006.173.06:59:33.90#ibcon#about to read 3, iclass 6, count 0 2006.173.06:59:33.92#ibcon#read 3, iclass 6, count 0 2006.173.06:59:33.92#ibcon#about to read 4, iclass 6, count 0 2006.173.06:59:33.92#ibcon#read 4, iclass 6, count 0 2006.173.06:59:33.92#ibcon#about to read 5, iclass 6, count 0 2006.173.06:59:33.92#ibcon#read 5, iclass 6, count 0 2006.173.06:59:33.92#ibcon#about to read 6, iclass 6, count 0 2006.173.06:59:33.92#ibcon#read 6, iclass 6, count 0 2006.173.06:59:33.92#ibcon#end of sib2, iclass 6, count 0 2006.173.06:59:33.92#ibcon#*mode == 0, iclass 6, count 0 2006.173.06:59:33.92#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.06:59:33.92#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.06:59:33.92#ibcon#*before write, iclass 6, count 0 2006.173.06:59:33.92#ibcon#enter sib2, iclass 6, count 0 2006.173.06:59:33.92#ibcon#flushed, iclass 6, count 0 2006.173.06:59:33.92#ibcon#about to write, iclass 6, count 0 2006.173.06:59:33.92#ibcon#wrote, iclass 6, count 0 2006.173.06:59:33.92#ibcon#about to read 3, iclass 6, count 0 2006.173.06:59:33.96#ibcon#read 3, iclass 6, count 0 2006.173.06:59:33.96#ibcon#about to read 4, iclass 6, count 0 2006.173.06:59:33.96#ibcon#read 4, iclass 6, count 0 2006.173.06:59:33.96#ibcon#about to read 5, iclass 6, count 0 2006.173.06:59:33.96#ibcon#read 5, iclass 6, count 0 2006.173.06:59:33.96#ibcon#about to read 6, iclass 6, count 0 2006.173.06:59:33.96#ibcon#read 6, iclass 6, count 0 2006.173.06:59:33.96#ibcon#end of sib2, iclass 6, count 0 2006.173.06:59:33.96#ibcon#*after write, iclass 6, count 0 2006.173.06:59:33.96#ibcon#*before return 0, iclass 6, count 0 2006.173.06:59:33.96#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.06:59:33.96#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.06:59:33.96#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.06:59:33.96#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.06:59:33.96$vck44/vb=1,4 2006.173.06:59:33.96#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.06:59:33.96#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.06:59:33.96#ibcon#ireg 11 cls_cnt 2 2006.173.06:59:33.96#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.06:59:33.96#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.06:59:33.96#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.06:59:33.96#ibcon#enter wrdev, iclass 10, count 2 2006.173.06:59:33.96#ibcon#first serial, iclass 10, count 2 2006.173.06:59:33.96#ibcon#enter sib2, iclass 10, count 2 2006.173.06:59:33.96#ibcon#flushed, iclass 10, count 2 2006.173.06:59:33.96#ibcon#about to write, iclass 10, count 2 2006.173.06:59:33.96#ibcon#wrote, iclass 10, count 2 2006.173.06:59:33.96#ibcon#about to read 3, iclass 10, count 2 2006.173.06:59:33.98#ibcon#read 3, iclass 10, count 2 2006.173.06:59:33.98#ibcon#about to read 4, iclass 10, count 2 2006.173.06:59:33.98#ibcon#read 4, iclass 10, count 2 2006.173.06:59:33.98#ibcon#about to read 5, iclass 10, count 2 2006.173.06:59:33.98#ibcon#read 5, iclass 10, count 2 2006.173.06:59:33.98#ibcon#about to read 6, iclass 10, count 2 2006.173.06:59:33.98#ibcon#read 6, iclass 10, count 2 2006.173.06:59:33.98#ibcon#end of sib2, iclass 10, count 2 2006.173.06:59:33.98#ibcon#*mode == 0, iclass 10, count 2 2006.173.06:59:33.98#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.06:59:33.98#ibcon#[27=AT01-04\r\n] 2006.173.06:59:33.98#ibcon#*before write, iclass 10, count 2 2006.173.06:59:33.98#ibcon#enter sib2, iclass 10, count 2 2006.173.06:59:33.98#ibcon#flushed, iclass 10, count 2 2006.173.06:59:33.98#ibcon#about to write, iclass 10, count 2 2006.173.06:59:33.98#ibcon#wrote, iclass 10, count 2 2006.173.06:59:33.98#ibcon#about to read 3, iclass 10, count 2 2006.173.06:59:34.01#ibcon#read 3, iclass 10, count 2 2006.173.06:59:34.01#ibcon#about to read 4, iclass 10, count 2 2006.173.06:59:34.01#ibcon#read 4, iclass 10, count 2 2006.173.06:59:34.01#ibcon#about to read 5, iclass 10, count 2 2006.173.06:59:34.01#ibcon#read 5, iclass 10, count 2 2006.173.06:59:34.01#ibcon#about to read 6, iclass 10, count 2 2006.173.06:59:34.01#ibcon#read 6, iclass 10, count 2 2006.173.06:59:34.01#ibcon#end of sib2, iclass 10, count 2 2006.173.06:59:34.01#ibcon#*after write, iclass 10, count 2 2006.173.06:59:34.01#ibcon#*before return 0, iclass 10, count 2 2006.173.06:59:34.01#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.06:59:34.01#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.06:59:34.01#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.06:59:34.01#ibcon#ireg 7 cls_cnt 0 2006.173.06:59:34.01#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.06:59:34.13#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.06:59:34.13#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.06:59:34.13#ibcon#enter wrdev, iclass 10, count 0 2006.173.06:59:34.13#ibcon#first serial, iclass 10, count 0 2006.173.06:59:34.13#ibcon#enter sib2, iclass 10, count 0 2006.173.06:59:34.13#ibcon#flushed, iclass 10, count 0 2006.173.06:59:34.13#ibcon#about to write, iclass 10, count 0 2006.173.06:59:34.13#ibcon#wrote, iclass 10, count 0 2006.173.06:59:34.13#ibcon#about to read 3, iclass 10, count 0 2006.173.06:59:34.15#ibcon#read 3, iclass 10, count 0 2006.173.06:59:34.15#ibcon#about to read 4, iclass 10, count 0 2006.173.06:59:34.15#ibcon#read 4, iclass 10, count 0 2006.173.06:59:34.15#ibcon#about to read 5, iclass 10, count 0 2006.173.06:59:34.15#ibcon#read 5, iclass 10, count 0 2006.173.06:59:34.15#ibcon#about to read 6, iclass 10, count 0 2006.173.06:59:34.15#ibcon#read 6, iclass 10, count 0 2006.173.06:59:34.15#ibcon#end of sib2, iclass 10, count 0 2006.173.06:59:34.15#ibcon#*mode == 0, iclass 10, count 0 2006.173.06:59:34.15#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.06:59:34.15#ibcon#[27=USB\r\n] 2006.173.06:59:34.15#ibcon#*before write, iclass 10, count 0 2006.173.06:59:34.15#ibcon#enter sib2, iclass 10, count 0 2006.173.06:59:34.15#ibcon#flushed, iclass 10, count 0 2006.173.06:59:34.15#ibcon#about to write, iclass 10, count 0 2006.173.06:59:34.15#ibcon#wrote, iclass 10, count 0 2006.173.06:59:34.15#ibcon#about to read 3, iclass 10, count 0 2006.173.06:59:34.18#ibcon#read 3, iclass 10, count 0 2006.173.06:59:34.18#ibcon#about to read 4, iclass 10, count 0 2006.173.06:59:34.18#ibcon#read 4, iclass 10, count 0 2006.173.06:59:34.18#ibcon#about to read 5, iclass 10, count 0 2006.173.06:59:34.18#ibcon#read 5, iclass 10, count 0 2006.173.06:59:34.18#ibcon#about to read 6, iclass 10, count 0 2006.173.06:59:34.18#ibcon#read 6, iclass 10, count 0 2006.173.06:59:34.18#ibcon#end of sib2, iclass 10, count 0 2006.173.06:59:34.18#ibcon#*after write, iclass 10, count 0 2006.173.06:59:34.18#ibcon#*before return 0, iclass 10, count 0 2006.173.06:59:34.18#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.06:59:34.18#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.06:59:34.18#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.06:59:34.18#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.06:59:34.18$vck44/vblo=2,634.99 2006.173.06:59:34.18#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.06:59:34.18#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.06:59:34.18#ibcon#ireg 17 cls_cnt 0 2006.173.06:59:34.18#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.06:59:34.18#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.06:59:34.18#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.06:59:34.18#ibcon#enter wrdev, iclass 12, count 0 2006.173.06:59:34.18#ibcon#first serial, iclass 12, count 0 2006.173.06:59:34.18#ibcon#enter sib2, iclass 12, count 0 2006.173.06:59:34.18#ibcon#flushed, iclass 12, count 0 2006.173.06:59:34.18#ibcon#about to write, iclass 12, count 0 2006.173.06:59:34.18#ibcon#wrote, iclass 12, count 0 2006.173.06:59:34.18#ibcon#about to read 3, iclass 12, count 0 2006.173.06:59:34.20#ibcon#read 3, iclass 12, count 0 2006.173.06:59:34.20#ibcon#about to read 4, iclass 12, count 0 2006.173.06:59:34.20#ibcon#read 4, iclass 12, count 0 2006.173.06:59:34.20#ibcon#about to read 5, iclass 12, count 0 2006.173.06:59:34.20#ibcon#read 5, iclass 12, count 0 2006.173.06:59:34.20#ibcon#about to read 6, iclass 12, count 0 2006.173.06:59:34.20#ibcon#read 6, iclass 12, count 0 2006.173.06:59:34.20#ibcon#end of sib2, iclass 12, count 0 2006.173.06:59:34.20#ibcon#*mode == 0, iclass 12, count 0 2006.173.06:59:34.20#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.06:59:34.20#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.06:59:34.20#ibcon#*before write, iclass 12, count 0 2006.173.06:59:34.20#ibcon#enter sib2, iclass 12, count 0 2006.173.06:59:34.20#ibcon#flushed, iclass 12, count 0 2006.173.06:59:34.20#ibcon#about to write, iclass 12, count 0 2006.173.06:59:34.20#ibcon#wrote, iclass 12, count 0 2006.173.06:59:34.20#ibcon#about to read 3, iclass 12, count 0 2006.173.06:59:34.24#ibcon#read 3, iclass 12, count 0 2006.173.06:59:34.24#ibcon#about to read 4, iclass 12, count 0 2006.173.06:59:34.24#ibcon#read 4, iclass 12, count 0 2006.173.06:59:34.24#ibcon#about to read 5, iclass 12, count 0 2006.173.06:59:34.24#ibcon#read 5, iclass 12, count 0 2006.173.06:59:34.24#ibcon#about to read 6, iclass 12, count 0 2006.173.06:59:34.24#ibcon#read 6, iclass 12, count 0 2006.173.06:59:34.24#ibcon#end of sib2, iclass 12, count 0 2006.173.06:59:34.24#ibcon#*after write, iclass 12, count 0 2006.173.06:59:34.24#ibcon#*before return 0, iclass 12, count 0 2006.173.06:59:34.24#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.06:59:34.24#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.06:59:34.24#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.06:59:34.24#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.06:59:34.24$vck44/vb=2,4 2006.173.06:59:34.24#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.06:59:34.24#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.06:59:34.24#ibcon#ireg 11 cls_cnt 2 2006.173.06:59:34.24#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.06:59:34.30#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.06:59:34.30#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.06:59:34.30#ibcon#enter wrdev, iclass 14, count 2 2006.173.06:59:34.30#ibcon#first serial, iclass 14, count 2 2006.173.06:59:34.30#ibcon#enter sib2, iclass 14, count 2 2006.173.06:59:34.30#ibcon#flushed, iclass 14, count 2 2006.173.06:59:34.30#ibcon#about to write, iclass 14, count 2 2006.173.06:59:34.30#ibcon#wrote, iclass 14, count 2 2006.173.06:59:34.30#ibcon#about to read 3, iclass 14, count 2 2006.173.06:59:34.32#ibcon#read 3, iclass 14, count 2 2006.173.06:59:34.32#ibcon#about to read 4, iclass 14, count 2 2006.173.06:59:34.32#ibcon#read 4, iclass 14, count 2 2006.173.06:59:34.32#ibcon#about to read 5, iclass 14, count 2 2006.173.06:59:34.32#ibcon#read 5, iclass 14, count 2 2006.173.06:59:34.32#ibcon#about to read 6, iclass 14, count 2 2006.173.06:59:34.32#ibcon#read 6, iclass 14, count 2 2006.173.06:59:34.32#ibcon#end of sib2, iclass 14, count 2 2006.173.06:59:34.32#ibcon#*mode == 0, iclass 14, count 2 2006.173.06:59:34.32#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.06:59:34.32#ibcon#[27=AT02-04\r\n] 2006.173.06:59:34.32#ibcon#*before write, iclass 14, count 2 2006.173.06:59:34.32#ibcon#enter sib2, iclass 14, count 2 2006.173.06:59:34.32#ibcon#flushed, iclass 14, count 2 2006.173.06:59:34.32#ibcon#about to write, iclass 14, count 2 2006.173.06:59:34.32#ibcon#wrote, iclass 14, count 2 2006.173.06:59:34.32#ibcon#about to read 3, iclass 14, count 2 2006.173.06:59:34.35#ibcon#read 3, iclass 14, count 2 2006.173.06:59:34.35#ibcon#about to read 4, iclass 14, count 2 2006.173.06:59:34.35#ibcon#read 4, iclass 14, count 2 2006.173.06:59:34.35#ibcon#about to read 5, iclass 14, count 2 2006.173.06:59:34.35#ibcon#read 5, iclass 14, count 2 2006.173.06:59:34.35#ibcon#about to read 6, iclass 14, count 2 2006.173.06:59:34.35#ibcon#read 6, iclass 14, count 2 2006.173.06:59:34.35#ibcon#end of sib2, iclass 14, count 2 2006.173.06:59:34.35#ibcon#*after write, iclass 14, count 2 2006.173.06:59:34.35#ibcon#*before return 0, iclass 14, count 2 2006.173.06:59:34.35#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.06:59:34.35#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.06:59:34.35#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.06:59:34.35#ibcon#ireg 7 cls_cnt 0 2006.173.06:59:34.35#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.06:59:34.47#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.06:59:34.47#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.06:59:34.47#ibcon#enter wrdev, iclass 14, count 0 2006.173.06:59:34.47#ibcon#first serial, iclass 14, count 0 2006.173.06:59:34.47#ibcon#enter sib2, iclass 14, count 0 2006.173.06:59:34.47#ibcon#flushed, iclass 14, count 0 2006.173.06:59:34.47#ibcon#about to write, iclass 14, count 0 2006.173.06:59:34.47#ibcon#wrote, iclass 14, count 0 2006.173.06:59:34.47#ibcon#about to read 3, iclass 14, count 0 2006.173.06:59:34.49#ibcon#read 3, iclass 14, count 0 2006.173.06:59:34.49#ibcon#about to read 4, iclass 14, count 0 2006.173.06:59:34.49#ibcon#read 4, iclass 14, count 0 2006.173.06:59:34.49#ibcon#about to read 5, iclass 14, count 0 2006.173.06:59:34.49#ibcon#read 5, iclass 14, count 0 2006.173.06:59:34.49#ibcon#about to read 6, iclass 14, count 0 2006.173.06:59:34.49#ibcon#read 6, iclass 14, count 0 2006.173.06:59:34.49#ibcon#end of sib2, iclass 14, count 0 2006.173.06:59:34.49#ibcon#*mode == 0, iclass 14, count 0 2006.173.06:59:34.49#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.06:59:34.49#ibcon#[27=USB\r\n] 2006.173.06:59:34.49#ibcon#*before write, iclass 14, count 0 2006.173.06:59:34.49#ibcon#enter sib2, iclass 14, count 0 2006.173.06:59:34.49#ibcon#flushed, iclass 14, count 0 2006.173.06:59:34.49#ibcon#about to write, iclass 14, count 0 2006.173.06:59:34.49#ibcon#wrote, iclass 14, count 0 2006.173.06:59:34.49#ibcon#about to read 3, iclass 14, count 0 2006.173.06:59:34.52#ibcon#read 3, iclass 14, count 0 2006.173.06:59:34.52#ibcon#about to read 4, iclass 14, count 0 2006.173.06:59:34.52#ibcon#read 4, iclass 14, count 0 2006.173.06:59:34.52#ibcon#about to read 5, iclass 14, count 0 2006.173.06:59:34.52#ibcon#read 5, iclass 14, count 0 2006.173.06:59:34.52#ibcon#about to read 6, iclass 14, count 0 2006.173.06:59:34.52#ibcon#read 6, iclass 14, count 0 2006.173.06:59:34.52#ibcon#end of sib2, iclass 14, count 0 2006.173.06:59:34.52#ibcon#*after write, iclass 14, count 0 2006.173.06:59:34.52#ibcon#*before return 0, iclass 14, count 0 2006.173.06:59:34.52#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.06:59:34.52#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.06:59:34.52#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.06:59:34.52#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.06:59:34.52$vck44/vblo=3,649.99 2006.173.06:59:34.52#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.06:59:34.52#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.06:59:34.52#ibcon#ireg 17 cls_cnt 0 2006.173.06:59:34.52#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.06:59:34.52#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.06:59:34.52#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.06:59:34.52#ibcon#enter wrdev, iclass 16, count 0 2006.173.06:59:34.52#ibcon#first serial, iclass 16, count 0 2006.173.06:59:34.52#ibcon#enter sib2, iclass 16, count 0 2006.173.06:59:34.52#ibcon#flushed, iclass 16, count 0 2006.173.06:59:34.52#ibcon#about to write, iclass 16, count 0 2006.173.06:59:34.52#ibcon#wrote, iclass 16, count 0 2006.173.06:59:34.52#ibcon#about to read 3, iclass 16, count 0 2006.173.06:59:34.54#ibcon#read 3, iclass 16, count 0 2006.173.06:59:34.54#ibcon#about to read 4, iclass 16, count 0 2006.173.06:59:34.54#ibcon#read 4, iclass 16, count 0 2006.173.06:59:34.54#ibcon#about to read 5, iclass 16, count 0 2006.173.06:59:34.54#ibcon#read 5, iclass 16, count 0 2006.173.06:59:34.54#ibcon#about to read 6, iclass 16, count 0 2006.173.06:59:34.54#ibcon#read 6, iclass 16, count 0 2006.173.06:59:34.54#ibcon#end of sib2, iclass 16, count 0 2006.173.06:59:34.54#ibcon#*mode == 0, iclass 16, count 0 2006.173.06:59:34.54#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.06:59:34.54#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.06:59:34.54#ibcon#*before write, iclass 16, count 0 2006.173.06:59:34.54#ibcon#enter sib2, iclass 16, count 0 2006.173.06:59:34.54#ibcon#flushed, iclass 16, count 0 2006.173.06:59:34.54#ibcon#about to write, iclass 16, count 0 2006.173.06:59:34.54#ibcon#wrote, iclass 16, count 0 2006.173.06:59:34.54#ibcon#about to read 3, iclass 16, count 0 2006.173.06:59:34.58#ibcon#read 3, iclass 16, count 0 2006.173.06:59:34.58#ibcon#about to read 4, iclass 16, count 0 2006.173.06:59:34.58#ibcon#read 4, iclass 16, count 0 2006.173.06:59:34.58#ibcon#about to read 5, iclass 16, count 0 2006.173.06:59:34.58#ibcon#read 5, iclass 16, count 0 2006.173.06:59:34.58#ibcon#about to read 6, iclass 16, count 0 2006.173.06:59:34.58#ibcon#read 6, iclass 16, count 0 2006.173.06:59:34.58#ibcon#end of sib2, iclass 16, count 0 2006.173.06:59:34.58#ibcon#*after write, iclass 16, count 0 2006.173.06:59:34.58#ibcon#*before return 0, iclass 16, count 0 2006.173.06:59:34.58#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.06:59:34.58#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.06:59:34.58#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.06:59:34.58#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.06:59:34.58$vck44/vb=3,4 2006.173.06:59:34.58#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.06:59:34.58#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.06:59:34.58#ibcon#ireg 11 cls_cnt 2 2006.173.06:59:34.58#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.06:59:34.64#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.06:59:34.64#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.06:59:34.64#ibcon#enter wrdev, iclass 18, count 2 2006.173.06:59:34.64#ibcon#first serial, iclass 18, count 2 2006.173.06:59:34.64#ibcon#enter sib2, iclass 18, count 2 2006.173.06:59:34.64#ibcon#flushed, iclass 18, count 2 2006.173.06:59:34.64#ibcon#about to write, iclass 18, count 2 2006.173.06:59:34.64#ibcon#wrote, iclass 18, count 2 2006.173.06:59:34.64#ibcon#about to read 3, iclass 18, count 2 2006.173.06:59:34.66#ibcon#read 3, iclass 18, count 2 2006.173.06:59:34.66#ibcon#about to read 4, iclass 18, count 2 2006.173.06:59:34.66#ibcon#read 4, iclass 18, count 2 2006.173.06:59:34.66#ibcon#about to read 5, iclass 18, count 2 2006.173.06:59:34.66#ibcon#read 5, iclass 18, count 2 2006.173.06:59:34.66#ibcon#about to read 6, iclass 18, count 2 2006.173.06:59:34.66#ibcon#read 6, iclass 18, count 2 2006.173.06:59:34.66#ibcon#end of sib2, iclass 18, count 2 2006.173.06:59:34.66#ibcon#*mode == 0, iclass 18, count 2 2006.173.06:59:34.66#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.06:59:34.66#ibcon#[27=AT03-04\r\n] 2006.173.06:59:34.66#ibcon#*before write, iclass 18, count 2 2006.173.06:59:34.66#ibcon#enter sib2, iclass 18, count 2 2006.173.06:59:34.66#ibcon#flushed, iclass 18, count 2 2006.173.06:59:34.66#ibcon#about to write, iclass 18, count 2 2006.173.06:59:34.66#ibcon#wrote, iclass 18, count 2 2006.173.06:59:34.66#ibcon#about to read 3, iclass 18, count 2 2006.173.06:59:34.69#ibcon#read 3, iclass 18, count 2 2006.173.06:59:34.69#ibcon#about to read 4, iclass 18, count 2 2006.173.06:59:34.69#ibcon#read 4, iclass 18, count 2 2006.173.06:59:34.69#ibcon#about to read 5, iclass 18, count 2 2006.173.06:59:34.69#ibcon#read 5, iclass 18, count 2 2006.173.06:59:34.69#ibcon#about to read 6, iclass 18, count 2 2006.173.06:59:34.69#ibcon#read 6, iclass 18, count 2 2006.173.06:59:34.69#ibcon#end of sib2, iclass 18, count 2 2006.173.06:59:34.69#ibcon#*after write, iclass 18, count 2 2006.173.06:59:34.69#ibcon#*before return 0, iclass 18, count 2 2006.173.06:59:34.69#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.06:59:34.69#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.06:59:34.69#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.06:59:34.69#ibcon#ireg 7 cls_cnt 0 2006.173.06:59:34.69#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.06:59:34.81#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.06:59:34.81#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.06:59:34.81#ibcon#enter wrdev, iclass 18, count 0 2006.173.06:59:34.81#ibcon#first serial, iclass 18, count 0 2006.173.06:59:34.81#ibcon#enter sib2, iclass 18, count 0 2006.173.06:59:34.81#ibcon#flushed, iclass 18, count 0 2006.173.06:59:34.81#ibcon#about to write, iclass 18, count 0 2006.173.06:59:34.81#ibcon#wrote, iclass 18, count 0 2006.173.06:59:34.81#ibcon#about to read 3, iclass 18, count 0 2006.173.06:59:34.83#ibcon#read 3, iclass 18, count 0 2006.173.06:59:34.83#ibcon#about to read 4, iclass 18, count 0 2006.173.06:59:34.83#ibcon#read 4, iclass 18, count 0 2006.173.06:59:34.83#ibcon#about to read 5, iclass 18, count 0 2006.173.06:59:34.83#ibcon#read 5, iclass 18, count 0 2006.173.06:59:34.83#ibcon#about to read 6, iclass 18, count 0 2006.173.06:59:34.83#ibcon#read 6, iclass 18, count 0 2006.173.06:59:34.83#ibcon#end of sib2, iclass 18, count 0 2006.173.06:59:34.83#ibcon#*mode == 0, iclass 18, count 0 2006.173.06:59:34.83#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.06:59:34.83#ibcon#[27=USB\r\n] 2006.173.06:59:34.83#ibcon#*before write, iclass 18, count 0 2006.173.06:59:34.83#ibcon#enter sib2, iclass 18, count 0 2006.173.06:59:34.83#ibcon#flushed, iclass 18, count 0 2006.173.06:59:34.83#ibcon#about to write, iclass 18, count 0 2006.173.06:59:34.83#ibcon#wrote, iclass 18, count 0 2006.173.06:59:34.83#ibcon#about to read 3, iclass 18, count 0 2006.173.06:59:34.86#ibcon#read 3, iclass 18, count 0 2006.173.06:59:34.86#ibcon#about to read 4, iclass 18, count 0 2006.173.06:59:34.86#ibcon#read 4, iclass 18, count 0 2006.173.06:59:34.86#ibcon#about to read 5, iclass 18, count 0 2006.173.06:59:34.86#ibcon#read 5, iclass 18, count 0 2006.173.06:59:34.86#ibcon#about to read 6, iclass 18, count 0 2006.173.06:59:34.86#ibcon#read 6, iclass 18, count 0 2006.173.06:59:34.86#ibcon#end of sib2, iclass 18, count 0 2006.173.06:59:34.86#ibcon#*after write, iclass 18, count 0 2006.173.06:59:34.86#ibcon#*before return 0, iclass 18, count 0 2006.173.06:59:34.86#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.06:59:34.86#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.06:59:34.86#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.06:59:34.86#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.06:59:34.86$vck44/vblo=4,679.99 2006.173.06:59:34.86#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.06:59:34.86#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.06:59:34.86#ibcon#ireg 17 cls_cnt 0 2006.173.06:59:34.86#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.06:59:34.86#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.06:59:34.86#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.06:59:34.86#ibcon#enter wrdev, iclass 20, count 0 2006.173.06:59:34.86#ibcon#first serial, iclass 20, count 0 2006.173.06:59:34.86#ibcon#enter sib2, iclass 20, count 0 2006.173.06:59:34.86#ibcon#flushed, iclass 20, count 0 2006.173.06:59:34.86#ibcon#about to write, iclass 20, count 0 2006.173.06:59:34.86#ibcon#wrote, iclass 20, count 0 2006.173.06:59:34.86#ibcon#about to read 3, iclass 20, count 0 2006.173.06:59:34.88#ibcon#read 3, iclass 20, count 0 2006.173.06:59:34.88#ibcon#about to read 4, iclass 20, count 0 2006.173.06:59:34.88#ibcon#read 4, iclass 20, count 0 2006.173.06:59:34.88#ibcon#about to read 5, iclass 20, count 0 2006.173.06:59:34.88#ibcon#read 5, iclass 20, count 0 2006.173.06:59:34.88#ibcon#about to read 6, iclass 20, count 0 2006.173.06:59:34.88#ibcon#read 6, iclass 20, count 0 2006.173.06:59:34.88#ibcon#end of sib2, iclass 20, count 0 2006.173.06:59:34.88#ibcon#*mode == 0, iclass 20, count 0 2006.173.06:59:34.88#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.06:59:34.88#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.06:59:34.88#ibcon#*before write, iclass 20, count 0 2006.173.06:59:34.88#ibcon#enter sib2, iclass 20, count 0 2006.173.06:59:34.88#ibcon#flushed, iclass 20, count 0 2006.173.06:59:34.88#ibcon#about to write, iclass 20, count 0 2006.173.06:59:34.88#ibcon#wrote, iclass 20, count 0 2006.173.06:59:34.88#ibcon#about to read 3, iclass 20, count 0 2006.173.06:59:34.92#ibcon#read 3, iclass 20, count 0 2006.173.06:59:34.92#ibcon#about to read 4, iclass 20, count 0 2006.173.06:59:34.92#ibcon#read 4, iclass 20, count 0 2006.173.06:59:34.92#ibcon#about to read 5, iclass 20, count 0 2006.173.06:59:34.92#ibcon#read 5, iclass 20, count 0 2006.173.06:59:34.92#ibcon#about to read 6, iclass 20, count 0 2006.173.06:59:34.92#ibcon#read 6, iclass 20, count 0 2006.173.06:59:34.92#ibcon#end of sib2, iclass 20, count 0 2006.173.06:59:34.92#ibcon#*after write, iclass 20, count 0 2006.173.06:59:34.92#ibcon#*before return 0, iclass 20, count 0 2006.173.06:59:34.92#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.06:59:34.92#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.06:59:34.92#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.06:59:34.92#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.06:59:34.92$vck44/vb=4,4 2006.173.06:59:34.92#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.06:59:34.92#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.06:59:34.92#ibcon#ireg 11 cls_cnt 2 2006.173.06:59:34.92#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.06:59:34.98#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.06:59:34.98#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.06:59:34.98#ibcon#enter wrdev, iclass 22, count 2 2006.173.06:59:34.98#ibcon#first serial, iclass 22, count 2 2006.173.06:59:34.98#ibcon#enter sib2, iclass 22, count 2 2006.173.06:59:34.98#ibcon#flushed, iclass 22, count 2 2006.173.06:59:34.98#ibcon#about to write, iclass 22, count 2 2006.173.06:59:34.98#ibcon#wrote, iclass 22, count 2 2006.173.06:59:34.98#ibcon#about to read 3, iclass 22, count 2 2006.173.06:59:35.00#ibcon#read 3, iclass 22, count 2 2006.173.06:59:35.00#ibcon#about to read 4, iclass 22, count 2 2006.173.06:59:35.00#ibcon#read 4, iclass 22, count 2 2006.173.06:59:35.00#ibcon#about to read 5, iclass 22, count 2 2006.173.06:59:35.00#ibcon#read 5, iclass 22, count 2 2006.173.06:59:35.00#ibcon#about to read 6, iclass 22, count 2 2006.173.06:59:35.00#ibcon#read 6, iclass 22, count 2 2006.173.06:59:35.00#ibcon#end of sib2, iclass 22, count 2 2006.173.06:59:35.00#ibcon#*mode == 0, iclass 22, count 2 2006.173.06:59:35.00#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.06:59:35.00#ibcon#[27=AT04-04\r\n] 2006.173.06:59:35.00#ibcon#*before write, iclass 22, count 2 2006.173.06:59:35.00#ibcon#enter sib2, iclass 22, count 2 2006.173.06:59:35.00#ibcon#flushed, iclass 22, count 2 2006.173.06:59:35.00#ibcon#about to write, iclass 22, count 2 2006.173.06:59:35.00#ibcon#wrote, iclass 22, count 2 2006.173.06:59:35.00#ibcon#about to read 3, iclass 22, count 2 2006.173.06:59:35.03#ibcon#read 3, iclass 22, count 2 2006.173.06:59:35.03#ibcon#about to read 4, iclass 22, count 2 2006.173.06:59:35.03#ibcon#read 4, iclass 22, count 2 2006.173.06:59:35.03#ibcon#about to read 5, iclass 22, count 2 2006.173.06:59:35.03#ibcon#read 5, iclass 22, count 2 2006.173.06:59:35.03#ibcon#about to read 6, iclass 22, count 2 2006.173.06:59:35.03#ibcon#read 6, iclass 22, count 2 2006.173.06:59:35.03#ibcon#end of sib2, iclass 22, count 2 2006.173.06:59:35.03#ibcon#*after write, iclass 22, count 2 2006.173.06:59:35.03#ibcon#*before return 0, iclass 22, count 2 2006.173.06:59:35.03#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.06:59:35.03#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.06:59:35.03#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.06:59:35.03#ibcon#ireg 7 cls_cnt 0 2006.173.06:59:35.03#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.06:59:35.15#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.06:59:35.15#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.06:59:35.15#ibcon#enter wrdev, iclass 22, count 0 2006.173.06:59:35.15#ibcon#first serial, iclass 22, count 0 2006.173.06:59:35.15#ibcon#enter sib2, iclass 22, count 0 2006.173.06:59:35.15#ibcon#flushed, iclass 22, count 0 2006.173.06:59:35.15#ibcon#about to write, iclass 22, count 0 2006.173.06:59:35.15#ibcon#wrote, iclass 22, count 0 2006.173.06:59:35.15#ibcon#about to read 3, iclass 22, count 0 2006.173.06:59:35.17#ibcon#read 3, iclass 22, count 0 2006.173.06:59:35.17#ibcon#about to read 4, iclass 22, count 0 2006.173.06:59:35.17#ibcon#read 4, iclass 22, count 0 2006.173.06:59:35.17#ibcon#about to read 5, iclass 22, count 0 2006.173.06:59:35.17#ibcon#read 5, iclass 22, count 0 2006.173.06:59:35.17#ibcon#about to read 6, iclass 22, count 0 2006.173.06:59:35.17#ibcon#read 6, iclass 22, count 0 2006.173.06:59:35.17#ibcon#end of sib2, iclass 22, count 0 2006.173.06:59:35.17#ibcon#*mode == 0, iclass 22, count 0 2006.173.06:59:35.17#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.06:59:35.17#ibcon#[27=USB\r\n] 2006.173.06:59:35.17#ibcon#*before write, iclass 22, count 0 2006.173.06:59:35.17#ibcon#enter sib2, iclass 22, count 0 2006.173.06:59:35.17#ibcon#flushed, iclass 22, count 0 2006.173.06:59:35.17#ibcon#about to write, iclass 22, count 0 2006.173.06:59:35.17#ibcon#wrote, iclass 22, count 0 2006.173.06:59:35.17#ibcon#about to read 3, iclass 22, count 0 2006.173.06:59:35.20#ibcon#read 3, iclass 22, count 0 2006.173.06:59:35.20#ibcon#about to read 4, iclass 22, count 0 2006.173.06:59:35.20#ibcon#read 4, iclass 22, count 0 2006.173.06:59:35.20#ibcon#about to read 5, iclass 22, count 0 2006.173.06:59:35.20#ibcon#read 5, iclass 22, count 0 2006.173.06:59:35.20#ibcon#about to read 6, iclass 22, count 0 2006.173.06:59:35.20#ibcon#read 6, iclass 22, count 0 2006.173.06:59:35.20#ibcon#end of sib2, iclass 22, count 0 2006.173.06:59:35.20#ibcon#*after write, iclass 22, count 0 2006.173.06:59:35.20#ibcon#*before return 0, iclass 22, count 0 2006.173.06:59:35.20#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.06:59:35.20#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.06:59:35.20#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.06:59:35.20#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.06:59:35.20$vck44/vblo=5,709.99 2006.173.06:59:35.20#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.06:59:35.20#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.06:59:35.20#ibcon#ireg 17 cls_cnt 0 2006.173.06:59:35.20#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.06:59:35.20#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.06:59:35.20#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.06:59:35.20#ibcon#enter wrdev, iclass 24, count 0 2006.173.06:59:35.20#ibcon#first serial, iclass 24, count 0 2006.173.06:59:35.20#ibcon#enter sib2, iclass 24, count 0 2006.173.06:59:35.20#ibcon#flushed, iclass 24, count 0 2006.173.06:59:35.20#ibcon#about to write, iclass 24, count 0 2006.173.06:59:35.20#ibcon#wrote, iclass 24, count 0 2006.173.06:59:35.20#ibcon#about to read 3, iclass 24, count 0 2006.173.06:59:35.22#ibcon#read 3, iclass 24, count 0 2006.173.06:59:35.22#ibcon#about to read 4, iclass 24, count 0 2006.173.06:59:35.22#ibcon#read 4, iclass 24, count 0 2006.173.06:59:35.22#ibcon#about to read 5, iclass 24, count 0 2006.173.06:59:35.22#ibcon#read 5, iclass 24, count 0 2006.173.06:59:35.22#ibcon#about to read 6, iclass 24, count 0 2006.173.06:59:35.22#ibcon#read 6, iclass 24, count 0 2006.173.06:59:35.22#ibcon#end of sib2, iclass 24, count 0 2006.173.06:59:35.22#ibcon#*mode == 0, iclass 24, count 0 2006.173.06:59:35.22#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.06:59:35.22#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.06:59:35.22#ibcon#*before write, iclass 24, count 0 2006.173.06:59:35.22#ibcon#enter sib2, iclass 24, count 0 2006.173.06:59:35.22#ibcon#flushed, iclass 24, count 0 2006.173.06:59:35.22#ibcon#about to write, iclass 24, count 0 2006.173.06:59:35.22#ibcon#wrote, iclass 24, count 0 2006.173.06:59:35.22#ibcon#about to read 3, iclass 24, count 0 2006.173.06:59:35.26#ibcon#read 3, iclass 24, count 0 2006.173.06:59:35.26#ibcon#about to read 4, iclass 24, count 0 2006.173.06:59:35.26#ibcon#read 4, iclass 24, count 0 2006.173.06:59:35.26#ibcon#about to read 5, iclass 24, count 0 2006.173.06:59:35.26#ibcon#read 5, iclass 24, count 0 2006.173.06:59:35.26#ibcon#about to read 6, iclass 24, count 0 2006.173.06:59:35.26#ibcon#read 6, iclass 24, count 0 2006.173.06:59:35.26#ibcon#end of sib2, iclass 24, count 0 2006.173.06:59:35.26#ibcon#*after write, iclass 24, count 0 2006.173.06:59:35.26#ibcon#*before return 0, iclass 24, count 0 2006.173.06:59:35.26#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.06:59:35.26#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.06:59:35.26#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.06:59:35.26#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.06:59:35.26$vck44/vb=5,4 2006.173.06:59:35.26#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.06:59:35.26#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.06:59:35.26#ibcon#ireg 11 cls_cnt 2 2006.173.06:59:35.26#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.06:59:35.32#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.06:59:35.32#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.06:59:35.32#ibcon#enter wrdev, iclass 26, count 2 2006.173.06:59:35.32#ibcon#first serial, iclass 26, count 2 2006.173.06:59:35.32#ibcon#enter sib2, iclass 26, count 2 2006.173.06:59:35.32#ibcon#flushed, iclass 26, count 2 2006.173.06:59:35.32#ibcon#about to write, iclass 26, count 2 2006.173.06:59:35.32#ibcon#wrote, iclass 26, count 2 2006.173.06:59:35.32#ibcon#about to read 3, iclass 26, count 2 2006.173.06:59:35.34#ibcon#read 3, iclass 26, count 2 2006.173.06:59:35.34#ibcon#about to read 4, iclass 26, count 2 2006.173.06:59:35.34#ibcon#read 4, iclass 26, count 2 2006.173.06:59:35.34#ibcon#about to read 5, iclass 26, count 2 2006.173.06:59:35.34#ibcon#read 5, iclass 26, count 2 2006.173.06:59:35.34#ibcon#about to read 6, iclass 26, count 2 2006.173.06:59:35.34#ibcon#read 6, iclass 26, count 2 2006.173.06:59:35.34#ibcon#end of sib2, iclass 26, count 2 2006.173.06:59:35.34#ibcon#*mode == 0, iclass 26, count 2 2006.173.06:59:35.34#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.06:59:35.34#ibcon#[27=AT05-04\r\n] 2006.173.06:59:35.34#ibcon#*before write, iclass 26, count 2 2006.173.06:59:35.34#ibcon#enter sib2, iclass 26, count 2 2006.173.06:59:35.34#ibcon#flushed, iclass 26, count 2 2006.173.06:59:35.34#ibcon#about to write, iclass 26, count 2 2006.173.06:59:35.34#ibcon#wrote, iclass 26, count 2 2006.173.06:59:35.34#ibcon#about to read 3, iclass 26, count 2 2006.173.06:59:35.37#ibcon#read 3, iclass 26, count 2 2006.173.06:59:35.37#ibcon#about to read 4, iclass 26, count 2 2006.173.06:59:35.37#ibcon#read 4, iclass 26, count 2 2006.173.06:59:35.37#ibcon#about to read 5, iclass 26, count 2 2006.173.06:59:35.37#ibcon#read 5, iclass 26, count 2 2006.173.06:59:35.37#ibcon#about to read 6, iclass 26, count 2 2006.173.06:59:35.37#ibcon#read 6, iclass 26, count 2 2006.173.06:59:35.37#ibcon#end of sib2, iclass 26, count 2 2006.173.06:59:35.37#ibcon#*after write, iclass 26, count 2 2006.173.06:59:35.37#ibcon#*before return 0, iclass 26, count 2 2006.173.06:59:35.37#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.06:59:35.37#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.06:59:35.37#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.06:59:35.37#ibcon#ireg 7 cls_cnt 0 2006.173.06:59:35.37#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.06:59:35.49#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.06:59:35.49#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.06:59:35.49#ibcon#enter wrdev, iclass 26, count 0 2006.173.06:59:35.49#ibcon#first serial, iclass 26, count 0 2006.173.06:59:35.49#ibcon#enter sib2, iclass 26, count 0 2006.173.06:59:35.49#ibcon#flushed, iclass 26, count 0 2006.173.06:59:35.49#ibcon#about to write, iclass 26, count 0 2006.173.06:59:35.49#ibcon#wrote, iclass 26, count 0 2006.173.06:59:35.49#ibcon#about to read 3, iclass 26, count 0 2006.173.06:59:35.51#ibcon#read 3, iclass 26, count 0 2006.173.06:59:35.51#ibcon#about to read 4, iclass 26, count 0 2006.173.06:59:35.51#ibcon#read 4, iclass 26, count 0 2006.173.06:59:35.51#ibcon#about to read 5, iclass 26, count 0 2006.173.06:59:35.51#ibcon#read 5, iclass 26, count 0 2006.173.06:59:35.51#ibcon#about to read 6, iclass 26, count 0 2006.173.06:59:35.51#ibcon#read 6, iclass 26, count 0 2006.173.06:59:35.51#ibcon#end of sib2, iclass 26, count 0 2006.173.06:59:35.51#ibcon#*mode == 0, iclass 26, count 0 2006.173.06:59:35.51#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.06:59:35.51#ibcon#[27=USB\r\n] 2006.173.06:59:35.51#ibcon#*before write, iclass 26, count 0 2006.173.06:59:35.51#ibcon#enter sib2, iclass 26, count 0 2006.173.06:59:35.51#ibcon#flushed, iclass 26, count 0 2006.173.06:59:35.51#ibcon#about to write, iclass 26, count 0 2006.173.06:59:35.51#ibcon#wrote, iclass 26, count 0 2006.173.06:59:35.51#ibcon#about to read 3, iclass 26, count 0 2006.173.06:59:35.54#ibcon#read 3, iclass 26, count 0 2006.173.06:59:35.54#ibcon#about to read 4, iclass 26, count 0 2006.173.06:59:35.54#ibcon#read 4, iclass 26, count 0 2006.173.06:59:35.54#ibcon#about to read 5, iclass 26, count 0 2006.173.06:59:35.54#ibcon#read 5, iclass 26, count 0 2006.173.06:59:35.54#ibcon#about to read 6, iclass 26, count 0 2006.173.06:59:35.54#ibcon#read 6, iclass 26, count 0 2006.173.06:59:35.54#ibcon#end of sib2, iclass 26, count 0 2006.173.06:59:35.54#ibcon#*after write, iclass 26, count 0 2006.173.06:59:35.54#ibcon#*before return 0, iclass 26, count 0 2006.173.06:59:35.54#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.06:59:35.54#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.06:59:35.54#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.06:59:35.54#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.06:59:35.54$vck44/vblo=6,719.99 2006.173.06:59:35.54#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.06:59:35.54#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.06:59:35.54#ibcon#ireg 17 cls_cnt 0 2006.173.06:59:35.54#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.06:59:35.54#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.06:59:35.54#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.06:59:35.54#ibcon#enter wrdev, iclass 28, count 0 2006.173.06:59:35.54#ibcon#first serial, iclass 28, count 0 2006.173.06:59:35.54#ibcon#enter sib2, iclass 28, count 0 2006.173.06:59:35.54#ibcon#flushed, iclass 28, count 0 2006.173.06:59:35.54#ibcon#about to write, iclass 28, count 0 2006.173.06:59:35.54#ibcon#wrote, iclass 28, count 0 2006.173.06:59:35.54#ibcon#about to read 3, iclass 28, count 0 2006.173.06:59:35.56#ibcon#read 3, iclass 28, count 0 2006.173.06:59:35.56#ibcon#about to read 4, iclass 28, count 0 2006.173.06:59:35.56#ibcon#read 4, iclass 28, count 0 2006.173.06:59:35.56#ibcon#about to read 5, iclass 28, count 0 2006.173.06:59:35.56#ibcon#read 5, iclass 28, count 0 2006.173.06:59:35.56#ibcon#about to read 6, iclass 28, count 0 2006.173.06:59:35.56#ibcon#read 6, iclass 28, count 0 2006.173.06:59:35.56#ibcon#end of sib2, iclass 28, count 0 2006.173.06:59:35.56#ibcon#*mode == 0, iclass 28, count 0 2006.173.06:59:35.56#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.06:59:35.56#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.06:59:35.56#ibcon#*before write, iclass 28, count 0 2006.173.06:59:35.56#ibcon#enter sib2, iclass 28, count 0 2006.173.06:59:35.56#ibcon#flushed, iclass 28, count 0 2006.173.06:59:35.56#ibcon#about to write, iclass 28, count 0 2006.173.06:59:35.56#ibcon#wrote, iclass 28, count 0 2006.173.06:59:35.56#ibcon#about to read 3, iclass 28, count 0 2006.173.06:59:35.60#ibcon#read 3, iclass 28, count 0 2006.173.06:59:35.60#ibcon#about to read 4, iclass 28, count 0 2006.173.06:59:35.60#ibcon#read 4, iclass 28, count 0 2006.173.06:59:35.60#ibcon#about to read 5, iclass 28, count 0 2006.173.06:59:35.60#ibcon#read 5, iclass 28, count 0 2006.173.06:59:35.60#ibcon#about to read 6, iclass 28, count 0 2006.173.06:59:35.60#ibcon#read 6, iclass 28, count 0 2006.173.06:59:35.60#ibcon#end of sib2, iclass 28, count 0 2006.173.06:59:35.60#ibcon#*after write, iclass 28, count 0 2006.173.06:59:35.60#ibcon#*before return 0, iclass 28, count 0 2006.173.06:59:35.60#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.06:59:35.60#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.06:59:35.60#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.06:59:35.60#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.06:59:35.60$vck44/vb=6,4 2006.173.06:59:35.60#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.06:59:35.60#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.06:59:35.60#ibcon#ireg 11 cls_cnt 2 2006.173.06:59:35.60#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.06:59:35.66#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.06:59:35.66#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.06:59:35.66#ibcon#enter wrdev, iclass 30, count 2 2006.173.06:59:35.66#ibcon#first serial, iclass 30, count 2 2006.173.06:59:35.66#ibcon#enter sib2, iclass 30, count 2 2006.173.06:59:35.66#ibcon#flushed, iclass 30, count 2 2006.173.06:59:35.66#ibcon#about to write, iclass 30, count 2 2006.173.06:59:35.66#ibcon#wrote, iclass 30, count 2 2006.173.06:59:35.66#ibcon#about to read 3, iclass 30, count 2 2006.173.06:59:35.68#ibcon#read 3, iclass 30, count 2 2006.173.06:59:35.68#ibcon#about to read 4, iclass 30, count 2 2006.173.06:59:35.68#ibcon#read 4, iclass 30, count 2 2006.173.06:59:35.68#ibcon#about to read 5, iclass 30, count 2 2006.173.06:59:35.68#ibcon#read 5, iclass 30, count 2 2006.173.06:59:35.68#ibcon#about to read 6, iclass 30, count 2 2006.173.06:59:35.68#ibcon#read 6, iclass 30, count 2 2006.173.06:59:35.68#ibcon#end of sib2, iclass 30, count 2 2006.173.06:59:35.68#ibcon#*mode == 0, iclass 30, count 2 2006.173.06:59:35.68#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.06:59:35.68#ibcon#[27=AT06-04\r\n] 2006.173.06:59:35.68#ibcon#*before write, iclass 30, count 2 2006.173.06:59:35.68#ibcon#enter sib2, iclass 30, count 2 2006.173.06:59:35.68#ibcon#flushed, iclass 30, count 2 2006.173.06:59:35.68#ibcon#about to write, iclass 30, count 2 2006.173.06:59:35.68#ibcon#wrote, iclass 30, count 2 2006.173.06:59:35.68#ibcon#about to read 3, iclass 30, count 2 2006.173.06:59:35.71#ibcon#read 3, iclass 30, count 2 2006.173.06:59:35.71#ibcon#about to read 4, iclass 30, count 2 2006.173.06:59:35.71#ibcon#read 4, iclass 30, count 2 2006.173.06:59:35.71#ibcon#about to read 5, iclass 30, count 2 2006.173.06:59:35.71#ibcon#read 5, iclass 30, count 2 2006.173.06:59:35.71#ibcon#about to read 6, iclass 30, count 2 2006.173.06:59:35.71#ibcon#read 6, iclass 30, count 2 2006.173.06:59:35.71#ibcon#end of sib2, iclass 30, count 2 2006.173.06:59:35.71#ibcon#*after write, iclass 30, count 2 2006.173.06:59:35.71#ibcon#*before return 0, iclass 30, count 2 2006.173.06:59:35.71#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.06:59:35.71#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.06:59:35.71#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.06:59:35.71#ibcon#ireg 7 cls_cnt 0 2006.173.06:59:35.71#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.06:59:35.83#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.06:59:35.83#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.06:59:35.83#ibcon#enter wrdev, iclass 30, count 0 2006.173.06:59:35.83#ibcon#first serial, iclass 30, count 0 2006.173.06:59:35.83#ibcon#enter sib2, iclass 30, count 0 2006.173.06:59:35.83#ibcon#flushed, iclass 30, count 0 2006.173.06:59:35.83#ibcon#about to write, iclass 30, count 0 2006.173.06:59:35.83#ibcon#wrote, iclass 30, count 0 2006.173.06:59:35.83#ibcon#about to read 3, iclass 30, count 0 2006.173.06:59:35.85#ibcon#read 3, iclass 30, count 0 2006.173.06:59:35.85#ibcon#about to read 4, iclass 30, count 0 2006.173.06:59:35.85#ibcon#read 4, iclass 30, count 0 2006.173.06:59:35.85#ibcon#about to read 5, iclass 30, count 0 2006.173.06:59:35.85#ibcon#read 5, iclass 30, count 0 2006.173.06:59:35.85#ibcon#about to read 6, iclass 30, count 0 2006.173.06:59:35.85#ibcon#read 6, iclass 30, count 0 2006.173.06:59:35.85#ibcon#end of sib2, iclass 30, count 0 2006.173.06:59:35.85#ibcon#*mode == 0, iclass 30, count 0 2006.173.06:59:35.85#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.06:59:35.85#ibcon#[27=USB\r\n] 2006.173.06:59:35.85#ibcon#*before write, iclass 30, count 0 2006.173.06:59:35.85#ibcon#enter sib2, iclass 30, count 0 2006.173.06:59:35.85#ibcon#flushed, iclass 30, count 0 2006.173.06:59:35.85#ibcon#about to write, iclass 30, count 0 2006.173.06:59:35.85#ibcon#wrote, iclass 30, count 0 2006.173.06:59:35.85#ibcon#about to read 3, iclass 30, count 0 2006.173.06:59:35.88#ibcon#read 3, iclass 30, count 0 2006.173.06:59:35.88#ibcon#about to read 4, iclass 30, count 0 2006.173.06:59:35.88#ibcon#read 4, iclass 30, count 0 2006.173.06:59:35.88#ibcon#about to read 5, iclass 30, count 0 2006.173.06:59:35.88#ibcon#read 5, iclass 30, count 0 2006.173.06:59:35.88#ibcon#about to read 6, iclass 30, count 0 2006.173.06:59:35.88#ibcon#read 6, iclass 30, count 0 2006.173.06:59:35.88#ibcon#end of sib2, iclass 30, count 0 2006.173.06:59:35.88#ibcon#*after write, iclass 30, count 0 2006.173.06:59:35.88#ibcon#*before return 0, iclass 30, count 0 2006.173.06:59:35.88#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.06:59:35.88#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.06:59:35.88#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.06:59:35.88#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.06:59:35.88$vck44/vblo=7,734.99 2006.173.06:59:35.88#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.06:59:35.88#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.06:59:35.88#ibcon#ireg 17 cls_cnt 0 2006.173.06:59:35.88#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.06:59:35.88#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.06:59:35.88#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.06:59:35.88#ibcon#enter wrdev, iclass 32, count 0 2006.173.06:59:35.88#ibcon#first serial, iclass 32, count 0 2006.173.06:59:35.88#ibcon#enter sib2, iclass 32, count 0 2006.173.06:59:35.88#ibcon#flushed, iclass 32, count 0 2006.173.06:59:35.88#ibcon#about to write, iclass 32, count 0 2006.173.06:59:35.88#ibcon#wrote, iclass 32, count 0 2006.173.06:59:35.88#ibcon#about to read 3, iclass 32, count 0 2006.173.06:59:35.90#ibcon#read 3, iclass 32, count 0 2006.173.06:59:35.90#ibcon#about to read 4, iclass 32, count 0 2006.173.06:59:35.90#ibcon#read 4, iclass 32, count 0 2006.173.06:59:35.90#ibcon#about to read 5, iclass 32, count 0 2006.173.06:59:35.90#ibcon#read 5, iclass 32, count 0 2006.173.06:59:35.90#ibcon#about to read 6, iclass 32, count 0 2006.173.06:59:35.90#ibcon#read 6, iclass 32, count 0 2006.173.06:59:35.90#ibcon#end of sib2, iclass 32, count 0 2006.173.06:59:35.90#ibcon#*mode == 0, iclass 32, count 0 2006.173.06:59:35.90#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.06:59:35.90#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.06:59:35.90#ibcon#*before write, iclass 32, count 0 2006.173.06:59:35.90#ibcon#enter sib2, iclass 32, count 0 2006.173.06:59:35.90#ibcon#flushed, iclass 32, count 0 2006.173.06:59:35.90#ibcon#about to write, iclass 32, count 0 2006.173.06:59:35.90#ibcon#wrote, iclass 32, count 0 2006.173.06:59:35.90#ibcon#about to read 3, iclass 32, count 0 2006.173.06:59:35.94#ibcon#read 3, iclass 32, count 0 2006.173.06:59:35.94#ibcon#about to read 4, iclass 32, count 0 2006.173.06:59:35.94#ibcon#read 4, iclass 32, count 0 2006.173.06:59:35.94#ibcon#about to read 5, iclass 32, count 0 2006.173.06:59:35.94#ibcon#read 5, iclass 32, count 0 2006.173.06:59:35.94#ibcon#about to read 6, iclass 32, count 0 2006.173.06:59:35.94#ibcon#read 6, iclass 32, count 0 2006.173.06:59:35.94#ibcon#end of sib2, iclass 32, count 0 2006.173.06:59:35.94#ibcon#*after write, iclass 32, count 0 2006.173.06:59:35.94#ibcon#*before return 0, iclass 32, count 0 2006.173.06:59:35.94#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.06:59:35.94#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.06:59:35.94#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.06:59:35.94#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.06:59:35.94$vck44/vb=7,4 2006.173.06:59:35.94#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.06:59:35.94#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.06:59:35.94#ibcon#ireg 11 cls_cnt 2 2006.173.06:59:35.94#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.06:59:36.00#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.06:59:36.00#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.06:59:36.00#ibcon#enter wrdev, iclass 34, count 2 2006.173.06:59:36.00#ibcon#first serial, iclass 34, count 2 2006.173.06:59:36.00#ibcon#enter sib2, iclass 34, count 2 2006.173.06:59:36.00#ibcon#flushed, iclass 34, count 2 2006.173.06:59:36.00#ibcon#about to write, iclass 34, count 2 2006.173.06:59:36.00#ibcon#wrote, iclass 34, count 2 2006.173.06:59:36.00#ibcon#about to read 3, iclass 34, count 2 2006.173.06:59:36.02#ibcon#read 3, iclass 34, count 2 2006.173.06:59:36.02#ibcon#about to read 4, iclass 34, count 2 2006.173.06:59:36.02#ibcon#read 4, iclass 34, count 2 2006.173.06:59:36.02#ibcon#about to read 5, iclass 34, count 2 2006.173.06:59:36.02#ibcon#read 5, iclass 34, count 2 2006.173.06:59:36.02#ibcon#about to read 6, iclass 34, count 2 2006.173.06:59:36.02#ibcon#read 6, iclass 34, count 2 2006.173.06:59:36.02#ibcon#end of sib2, iclass 34, count 2 2006.173.06:59:36.02#ibcon#*mode == 0, iclass 34, count 2 2006.173.06:59:36.02#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.06:59:36.02#ibcon#[27=AT07-04\r\n] 2006.173.06:59:36.02#ibcon#*before write, iclass 34, count 2 2006.173.06:59:36.02#ibcon#enter sib2, iclass 34, count 2 2006.173.06:59:36.02#ibcon#flushed, iclass 34, count 2 2006.173.06:59:36.02#ibcon#about to write, iclass 34, count 2 2006.173.06:59:36.02#ibcon#wrote, iclass 34, count 2 2006.173.06:59:36.02#ibcon#about to read 3, iclass 34, count 2 2006.173.06:59:36.05#ibcon#read 3, iclass 34, count 2 2006.173.06:59:36.05#ibcon#about to read 4, iclass 34, count 2 2006.173.06:59:36.05#ibcon#read 4, iclass 34, count 2 2006.173.06:59:36.05#ibcon#about to read 5, iclass 34, count 2 2006.173.06:59:36.05#ibcon#read 5, iclass 34, count 2 2006.173.06:59:36.05#ibcon#about to read 6, iclass 34, count 2 2006.173.06:59:36.05#ibcon#read 6, iclass 34, count 2 2006.173.06:59:36.05#ibcon#end of sib2, iclass 34, count 2 2006.173.06:59:36.05#ibcon#*after write, iclass 34, count 2 2006.173.06:59:36.05#ibcon#*before return 0, iclass 34, count 2 2006.173.06:59:36.05#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.06:59:36.05#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.06:59:36.05#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.06:59:36.05#ibcon#ireg 7 cls_cnt 0 2006.173.06:59:36.05#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.06:59:36.17#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.06:59:36.17#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.06:59:36.17#ibcon#enter wrdev, iclass 34, count 0 2006.173.06:59:36.17#ibcon#first serial, iclass 34, count 0 2006.173.06:59:36.17#ibcon#enter sib2, iclass 34, count 0 2006.173.06:59:36.17#ibcon#flushed, iclass 34, count 0 2006.173.06:59:36.17#ibcon#about to write, iclass 34, count 0 2006.173.06:59:36.17#ibcon#wrote, iclass 34, count 0 2006.173.06:59:36.17#ibcon#about to read 3, iclass 34, count 0 2006.173.06:59:36.19#ibcon#read 3, iclass 34, count 0 2006.173.06:59:36.19#ibcon#about to read 4, iclass 34, count 0 2006.173.06:59:36.19#ibcon#read 4, iclass 34, count 0 2006.173.06:59:36.19#ibcon#about to read 5, iclass 34, count 0 2006.173.06:59:36.19#ibcon#read 5, iclass 34, count 0 2006.173.06:59:36.19#ibcon#about to read 6, iclass 34, count 0 2006.173.06:59:36.19#ibcon#read 6, iclass 34, count 0 2006.173.06:59:36.19#ibcon#end of sib2, iclass 34, count 0 2006.173.06:59:36.19#ibcon#*mode == 0, iclass 34, count 0 2006.173.06:59:36.19#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.06:59:36.19#ibcon#[27=USB\r\n] 2006.173.06:59:36.19#ibcon#*before write, iclass 34, count 0 2006.173.06:59:36.19#ibcon#enter sib2, iclass 34, count 0 2006.173.06:59:36.19#ibcon#flushed, iclass 34, count 0 2006.173.06:59:36.19#ibcon#about to write, iclass 34, count 0 2006.173.06:59:36.19#ibcon#wrote, iclass 34, count 0 2006.173.06:59:36.19#ibcon#about to read 3, iclass 34, count 0 2006.173.06:59:36.22#ibcon#read 3, iclass 34, count 0 2006.173.06:59:36.22#ibcon#about to read 4, iclass 34, count 0 2006.173.06:59:36.22#ibcon#read 4, iclass 34, count 0 2006.173.06:59:36.22#ibcon#about to read 5, iclass 34, count 0 2006.173.06:59:36.22#ibcon#read 5, iclass 34, count 0 2006.173.06:59:36.22#ibcon#about to read 6, iclass 34, count 0 2006.173.06:59:36.22#ibcon#read 6, iclass 34, count 0 2006.173.06:59:36.22#ibcon#end of sib2, iclass 34, count 0 2006.173.06:59:36.22#ibcon#*after write, iclass 34, count 0 2006.173.06:59:36.22#ibcon#*before return 0, iclass 34, count 0 2006.173.06:59:36.22#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.06:59:36.22#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.06:59:36.22#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.06:59:36.22#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.06:59:36.22$vck44/vblo=8,744.99 2006.173.06:59:36.22#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.06:59:36.22#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.06:59:36.22#ibcon#ireg 17 cls_cnt 0 2006.173.06:59:36.22#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.06:59:36.22#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.06:59:36.22#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.06:59:36.22#ibcon#enter wrdev, iclass 36, count 0 2006.173.06:59:36.22#ibcon#first serial, iclass 36, count 0 2006.173.06:59:36.22#ibcon#enter sib2, iclass 36, count 0 2006.173.06:59:36.22#ibcon#flushed, iclass 36, count 0 2006.173.06:59:36.22#ibcon#about to write, iclass 36, count 0 2006.173.06:59:36.22#ibcon#wrote, iclass 36, count 0 2006.173.06:59:36.22#ibcon#about to read 3, iclass 36, count 0 2006.173.06:59:36.24#ibcon#read 3, iclass 36, count 0 2006.173.06:59:36.24#ibcon#about to read 4, iclass 36, count 0 2006.173.06:59:36.24#ibcon#read 4, iclass 36, count 0 2006.173.06:59:36.24#ibcon#about to read 5, iclass 36, count 0 2006.173.06:59:36.24#ibcon#read 5, iclass 36, count 0 2006.173.06:59:36.24#ibcon#about to read 6, iclass 36, count 0 2006.173.06:59:36.24#ibcon#read 6, iclass 36, count 0 2006.173.06:59:36.24#ibcon#end of sib2, iclass 36, count 0 2006.173.06:59:36.24#ibcon#*mode == 0, iclass 36, count 0 2006.173.06:59:36.24#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.06:59:36.24#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.06:59:36.24#ibcon#*before write, iclass 36, count 0 2006.173.06:59:36.24#ibcon#enter sib2, iclass 36, count 0 2006.173.06:59:36.24#ibcon#flushed, iclass 36, count 0 2006.173.06:59:36.24#ibcon#about to write, iclass 36, count 0 2006.173.06:59:36.24#ibcon#wrote, iclass 36, count 0 2006.173.06:59:36.24#ibcon#about to read 3, iclass 36, count 0 2006.173.06:59:36.28#ibcon#read 3, iclass 36, count 0 2006.173.06:59:36.28#ibcon#about to read 4, iclass 36, count 0 2006.173.06:59:36.28#ibcon#read 4, iclass 36, count 0 2006.173.06:59:36.28#ibcon#about to read 5, iclass 36, count 0 2006.173.06:59:36.28#ibcon#read 5, iclass 36, count 0 2006.173.06:59:36.28#ibcon#about to read 6, iclass 36, count 0 2006.173.06:59:36.28#ibcon#read 6, iclass 36, count 0 2006.173.06:59:36.28#ibcon#end of sib2, iclass 36, count 0 2006.173.06:59:36.28#ibcon#*after write, iclass 36, count 0 2006.173.06:59:36.28#ibcon#*before return 0, iclass 36, count 0 2006.173.06:59:36.28#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.06:59:36.28#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.06:59:36.28#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.06:59:36.28#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.06:59:36.28$vck44/vb=8,4 2006.173.06:59:36.28#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.06:59:36.28#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.06:59:36.28#ibcon#ireg 11 cls_cnt 2 2006.173.06:59:36.28#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.06:59:36.34#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.06:59:36.34#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.06:59:36.34#ibcon#enter wrdev, iclass 38, count 2 2006.173.06:59:36.34#ibcon#first serial, iclass 38, count 2 2006.173.06:59:36.34#ibcon#enter sib2, iclass 38, count 2 2006.173.06:59:36.34#ibcon#flushed, iclass 38, count 2 2006.173.06:59:36.34#ibcon#about to write, iclass 38, count 2 2006.173.06:59:36.34#ibcon#wrote, iclass 38, count 2 2006.173.06:59:36.34#ibcon#about to read 3, iclass 38, count 2 2006.173.06:59:36.36#ibcon#read 3, iclass 38, count 2 2006.173.06:59:36.36#ibcon#about to read 4, iclass 38, count 2 2006.173.06:59:36.36#ibcon#read 4, iclass 38, count 2 2006.173.06:59:36.36#ibcon#about to read 5, iclass 38, count 2 2006.173.06:59:36.36#ibcon#read 5, iclass 38, count 2 2006.173.06:59:36.36#ibcon#about to read 6, iclass 38, count 2 2006.173.06:59:36.36#ibcon#read 6, iclass 38, count 2 2006.173.06:59:36.36#ibcon#end of sib2, iclass 38, count 2 2006.173.06:59:36.36#ibcon#*mode == 0, iclass 38, count 2 2006.173.06:59:36.36#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.06:59:36.36#ibcon#[27=AT08-04\r\n] 2006.173.06:59:36.36#ibcon#*before write, iclass 38, count 2 2006.173.06:59:36.36#ibcon#enter sib2, iclass 38, count 2 2006.173.06:59:36.36#ibcon#flushed, iclass 38, count 2 2006.173.06:59:36.36#ibcon#about to write, iclass 38, count 2 2006.173.06:59:36.36#ibcon#wrote, iclass 38, count 2 2006.173.06:59:36.36#ibcon#about to read 3, iclass 38, count 2 2006.173.06:59:36.39#ibcon#read 3, iclass 38, count 2 2006.173.06:59:36.39#ibcon#about to read 4, iclass 38, count 2 2006.173.06:59:36.39#ibcon#read 4, iclass 38, count 2 2006.173.06:59:36.39#ibcon#about to read 5, iclass 38, count 2 2006.173.06:59:36.39#ibcon#read 5, iclass 38, count 2 2006.173.06:59:36.39#ibcon#about to read 6, iclass 38, count 2 2006.173.06:59:36.39#ibcon#read 6, iclass 38, count 2 2006.173.06:59:36.39#ibcon#end of sib2, iclass 38, count 2 2006.173.06:59:36.39#ibcon#*after write, iclass 38, count 2 2006.173.06:59:36.39#ibcon#*before return 0, iclass 38, count 2 2006.173.06:59:36.39#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.06:59:36.39#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.06:59:36.39#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.06:59:36.39#ibcon#ireg 7 cls_cnt 0 2006.173.06:59:36.39#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.06:59:36.51#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.06:59:36.51#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.06:59:36.51#ibcon#enter wrdev, iclass 38, count 0 2006.173.06:59:36.51#ibcon#first serial, iclass 38, count 0 2006.173.06:59:36.51#ibcon#enter sib2, iclass 38, count 0 2006.173.06:59:36.51#ibcon#flushed, iclass 38, count 0 2006.173.06:59:36.51#ibcon#about to write, iclass 38, count 0 2006.173.06:59:36.51#ibcon#wrote, iclass 38, count 0 2006.173.06:59:36.51#ibcon#about to read 3, iclass 38, count 0 2006.173.06:59:36.53#ibcon#read 3, iclass 38, count 0 2006.173.06:59:36.53#ibcon#about to read 4, iclass 38, count 0 2006.173.06:59:36.53#ibcon#read 4, iclass 38, count 0 2006.173.06:59:36.53#ibcon#about to read 5, iclass 38, count 0 2006.173.06:59:36.53#ibcon#read 5, iclass 38, count 0 2006.173.06:59:36.53#ibcon#about to read 6, iclass 38, count 0 2006.173.06:59:36.53#ibcon#read 6, iclass 38, count 0 2006.173.06:59:36.53#ibcon#end of sib2, iclass 38, count 0 2006.173.06:59:36.53#ibcon#*mode == 0, iclass 38, count 0 2006.173.06:59:36.53#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.06:59:36.53#ibcon#[27=USB\r\n] 2006.173.06:59:36.53#ibcon#*before write, iclass 38, count 0 2006.173.06:59:36.53#ibcon#enter sib2, iclass 38, count 0 2006.173.06:59:36.53#ibcon#flushed, iclass 38, count 0 2006.173.06:59:36.53#ibcon#about to write, iclass 38, count 0 2006.173.06:59:36.53#ibcon#wrote, iclass 38, count 0 2006.173.06:59:36.53#ibcon#about to read 3, iclass 38, count 0 2006.173.06:59:36.56#ibcon#read 3, iclass 38, count 0 2006.173.06:59:36.56#ibcon#about to read 4, iclass 38, count 0 2006.173.06:59:36.56#ibcon#read 4, iclass 38, count 0 2006.173.06:59:36.56#ibcon#about to read 5, iclass 38, count 0 2006.173.06:59:36.56#ibcon#read 5, iclass 38, count 0 2006.173.06:59:36.56#ibcon#about to read 6, iclass 38, count 0 2006.173.06:59:36.56#ibcon#read 6, iclass 38, count 0 2006.173.06:59:36.56#ibcon#end of sib2, iclass 38, count 0 2006.173.06:59:36.56#ibcon#*after write, iclass 38, count 0 2006.173.06:59:36.56#ibcon#*before return 0, iclass 38, count 0 2006.173.06:59:36.56#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.06:59:36.56#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.06:59:36.56#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.06:59:36.56#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.06:59:36.56$vck44/vabw=wide 2006.173.06:59:36.56#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.06:59:36.56#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.06:59:36.56#ibcon#ireg 8 cls_cnt 0 2006.173.06:59:36.56#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.06:59:36.56#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.06:59:36.56#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.06:59:36.56#ibcon#enter wrdev, iclass 40, count 0 2006.173.06:59:36.56#ibcon#first serial, iclass 40, count 0 2006.173.06:59:36.56#ibcon#enter sib2, iclass 40, count 0 2006.173.06:59:36.56#ibcon#flushed, iclass 40, count 0 2006.173.06:59:36.56#ibcon#about to write, iclass 40, count 0 2006.173.06:59:36.56#ibcon#wrote, iclass 40, count 0 2006.173.06:59:36.56#ibcon#about to read 3, iclass 40, count 0 2006.173.06:59:36.58#ibcon#read 3, iclass 40, count 0 2006.173.06:59:36.58#ibcon#about to read 4, iclass 40, count 0 2006.173.06:59:36.58#ibcon#read 4, iclass 40, count 0 2006.173.06:59:36.58#ibcon#about to read 5, iclass 40, count 0 2006.173.06:59:36.58#ibcon#read 5, iclass 40, count 0 2006.173.06:59:36.58#ibcon#about to read 6, iclass 40, count 0 2006.173.06:59:36.58#ibcon#read 6, iclass 40, count 0 2006.173.06:59:36.58#ibcon#end of sib2, iclass 40, count 0 2006.173.06:59:36.58#ibcon#*mode == 0, iclass 40, count 0 2006.173.06:59:36.58#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.06:59:36.58#ibcon#[25=BW32\r\n] 2006.173.06:59:36.58#ibcon#*before write, iclass 40, count 0 2006.173.06:59:36.58#ibcon#enter sib2, iclass 40, count 0 2006.173.06:59:36.58#ibcon#flushed, iclass 40, count 0 2006.173.06:59:36.58#ibcon#about to write, iclass 40, count 0 2006.173.06:59:36.58#ibcon#wrote, iclass 40, count 0 2006.173.06:59:36.58#ibcon#about to read 3, iclass 40, count 0 2006.173.06:59:36.61#ibcon#read 3, iclass 40, count 0 2006.173.06:59:36.61#ibcon#about to read 4, iclass 40, count 0 2006.173.06:59:36.61#ibcon#read 4, iclass 40, count 0 2006.173.06:59:36.61#ibcon#about to read 5, iclass 40, count 0 2006.173.06:59:36.61#ibcon#read 5, iclass 40, count 0 2006.173.06:59:36.61#ibcon#about to read 6, iclass 40, count 0 2006.173.06:59:36.61#ibcon#read 6, iclass 40, count 0 2006.173.06:59:36.61#ibcon#end of sib2, iclass 40, count 0 2006.173.06:59:36.61#ibcon#*after write, iclass 40, count 0 2006.173.06:59:36.61#ibcon#*before return 0, iclass 40, count 0 2006.173.06:59:36.61#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.06:59:36.61#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.06:59:36.61#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.06:59:36.61#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.06:59:36.61$vck44/vbbw=wide 2006.173.06:59:36.61#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.06:59:36.61#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.06:59:36.61#ibcon#ireg 8 cls_cnt 0 2006.173.06:59:36.61#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.06:59:36.68#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.06:59:36.68#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.06:59:36.68#ibcon#enter wrdev, iclass 4, count 0 2006.173.06:59:36.68#ibcon#first serial, iclass 4, count 0 2006.173.06:59:36.68#ibcon#enter sib2, iclass 4, count 0 2006.173.06:59:36.68#ibcon#flushed, iclass 4, count 0 2006.173.06:59:36.68#ibcon#about to write, iclass 4, count 0 2006.173.06:59:36.68#ibcon#wrote, iclass 4, count 0 2006.173.06:59:36.68#ibcon#about to read 3, iclass 4, count 0 2006.173.06:59:36.70#ibcon#read 3, iclass 4, count 0 2006.173.06:59:36.70#ibcon#about to read 4, iclass 4, count 0 2006.173.06:59:36.70#ibcon#read 4, iclass 4, count 0 2006.173.06:59:36.70#ibcon#about to read 5, iclass 4, count 0 2006.173.06:59:36.70#ibcon#read 5, iclass 4, count 0 2006.173.06:59:36.70#ibcon#about to read 6, iclass 4, count 0 2006.173.06:59:36.70#ibcon#read 6, iclass 4, count 0 2006.173.06:59:36.70#ibcon#end of sib2, iclass 4, count 0 2006.173.06:59:36.70#ibcon#*mode == 0, iclass 4, count 0 2006.173.06:59:36.70#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.06:59:36.70#ibcon#[27=BW32\r\n] 2006.173.06:59:36.70#ibcon#*before write, iclass 4, count 0 2006.173.06:59:36.70#ibcon#enter sib2, iclass 4, count 0 2006.173.06:59:36.70#ibcon#flushed, iclass 4, count 0 2006.173.06:59:36.70#ibcon#about to write, iclass 4, count 0 2006.173.06:59:36.70#ibcon#wrote, iclass 4, count 0 2006.173.06:59:36.70#ibcon#about to read 3, iclass 4, count 0 2006.173.06:59:36.73#ibcon#read 3, iclass 4, count 0 2006.173.06:59:36.73#ibcon#about to read 4, iclass 4, count 0 2006.173.06:59:36.73#ibcon#read 4, iclass 4, count 0 2006.173.06:59:36.73#ibcon#about to read 5, iclass 4, count 0 2006.173.06:59:36.73#ibcon#read 5, iclass 4, count 0 2006.173.06:59:36.73#ibcon#about to read 6, iclass 4, count 0 2006.173.06:59:36.73#ibcon#read 6, iclass 4, count 0 2006.173.06:59:36.73#ibcon#end of sib2, iclass 4, count 0 2006.173.06:59:36.73#ibcon#*after write, iclass 4, count 0 2006.173.06:59:36.73#ibcon#*before return 0, iclass 4, count 0 2006.173.06:59:36.73#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.06:59:36.73#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.06:59:36.73#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.06:59:36.73#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.06:59:36.73$setupk4/ifdk4 2006.173.06:59:36.73$ifdk4/lo= 2006.173.06:59:36.73$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.06:59:36.73$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.06:59:36.73$ifdk4/patch= 2006.173.06:59:36.73$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.06:59:36.73$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.06:59:36.73$setupk4/!*+20s 2006.173.06:59:38.18#abcon#<5=/16 0.4 0.8 23.73 791004.9\r\n> 2006.173.06:59:38.20#abcon#{5=INTERFACE CLEAR} 2006.173.06:59:38.26#abcon#[5=S1D000X0/0*\r\n] 2006.173.06:59:46.14#trakl#Source acquired 2006.173.06:59:48.14#flagr#flagr/antenna,acquired 2006.173.06:59:48.35#abcon#<5=/16 0.4 0.8 23.73 801004.9\r\n> 2006.173.06:59:48.37#abcon#{5=INTERFACE CLEAR} 2006.173.06:59:48.43#abcon#[5=S1D000X0/0*\r\n] 2006.173.06:59:51.24$setupk4/"tpicd 2006.173.06:59:51.24$setupk4/echo=off 2006.173.06:59:51.24$setupk4/xlog=off 2006.173.06:59:51.24:!2006.173.07:05:30 2006.173.07:05:30.00:preob 2006.173.07:05:31.14/onsource/TRACKING 2006.173.07:05:31.14:!2006.173.07:05:40 2006.173.07:05:40.00:"tape 2006.173.07:05:40.00:"st=record 2006.173.07:05:40.00:data_valid=on 2006.173.07:05:40.00:midob 2006.173.07:05:40.14/onsource/TRACKING 2006.173.07:05:40.14/wx/23.69,1004.8,78 2006.173.07:05:40.34/cable/+6.5023E-03 2006.173.07:05:41.43/va/01,07,usb,yes,37,40 2006.173.07:05:41.43/va/02,06,usb,yes,37,38 2006.173.07:05:41.43/va/03,05,usb,yes,47,49 2006.173.07:05:41.43/va/04,06,usb,yes,38,40 2006.173.07:05:41.43/va/05,04,usb,yes,30,30 2006.173.07:05:41.43/va/06,03,usb,yes,42,42 2006.173.07:05:41.43/va/07,04,usb,yes,34,35 2006.173.07:05:41.43/va/08,04,usb,yes,29,35 2006.173.07:05:41.66/valo/01,524.99,yes,locked 2006.173.07:05:41.66/valo/02,534.99,yes,locked 2006.173.07:05:41.66/valo/03,564.99,yes,locked 2006.173.07:05:41.66/valo/04,624.99,yes,locked 2006.173.07:05:41.66/valo/05,734.99,yes,locked 2006.173.07:05:41.66/valo/06,814.99,yes,locked 2006.173.07:05:41.66/valo/07,864.99,yes,locked 2006.173.07:05:41.66/valo/08,884.99,yes,locked 2006.173.07:05:42.75/vb/01,04,usb,yes,31,28 2006.173.07:05:42.75/vb/02,04,usb,yes,33,33 2006.173.07:05:42.75/vb/03,04,usb,yes,30,33 2006.173.07:05:42.75/vb/04,04,usb,yes,34,33 2006.173.07:05:42.75/vb/05,04,usb,yes,27,29 2006.173.07:05:42.75/vb/06,04,usb,yes,31,27 2006.173.07:05:42.75/vb/07,04,usb,yes,31,31 2006.173.07:05:42.75/vb/08,04,usb,yes,29,32 2006.173.07:05:42.98/vblo/01,629.99,yes,locked 2006.173.07:05:42.98/vblo/02,634.99,yes,locked 2006.173.07:05:42.98/vblo/03,649.99,yes,locked 2006.173.07:05:42.98/vblo/04,679.99,yes,locked 2006.173.07:05:42.98/vblo/05,709.99,yes,locked 2006.173.07:05:42.98/vblo/06,719.99,yes,locked 2006.173.07:05:42.98/vblo/07,734.99,yes,locked 2006.173.07:05:42.98/vblo/08,744.99,yes,locked 2006.173.07:05:43.13/vabw/8 2006.173.07:05:43.28/vbbw/8 2006.173.07:05:43.37/xfe/off,on,14.7 2006.173.07:05:43.75/ifatt/23,28,28,28 2006.173.07:05:44.08/fmout-gps/S +3.95E-07 2006.173.07:05:44.12:!2006.173.07:06:20 2006.173.07:06:20.00:data_valid=off 2006.173.07:06:20.00:"et 2006.173.07:06:20.00:!+3s 2006.173.07:06:23.02:"tape 2006.173.07:06:23.02:postob 2006.173.07:06:23.08/cable/+6.5006E-03 2006.173.07:06:23.08/wx/23.69,1004.8,78 2006.173.07:06:24.08/fmout-gps/S +3.94E-07 2006.173.07:06:24.08:scan_name=173-0708,jd0606,370 2006.173.07:06:24.08:source=1308+326,131028.66,322043.8,2000.0,ccw 2006.173.07:06:25.14#flagr#flagr/antenna,new-source 2006.173.07:06:25.14:checkk5 2006.173.07:06:25.56/chk_autoobs//k5ts1/ autoobs is running! 2006.173.07:06:25.96/chk_autoobs//k5ts2/ autoobs is running! 2006.173.07:06:26.36/chk_autoobs//k5ts3/ autoobs is running! 2006.173.07:06:26.75/chk_autoobs//k5ts4/ autoobs is running! 2006.173.07:06:27.13/chk_obsdata//k5ts1/T1730705??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.173.07:06:27.56/chk_obsdata//k5ts2/T1730705??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.173.07:06:27.97/chk_obsdata//k5ts3/T1730705??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.173.07:06:28.37/chk_obsdata//k5ts4/T1730705??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.173.07:06:29.09/k5log//k5ts1_log_newline 2006.173.07:06:29.81/k5log//k5ts2_log_newline 2006.173.07:06:30.53/k5log//k5ts3_log_newline 2006.173.07:06:31.24/k5log//k5ts4_log_newline 2006.173.07:06:31.26/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.07:06:31.26:setupk4=1 2006.173.07:06:31.26$setupk4/echo=on 2006.173.07:06:31.26$setupk4/pcalon 2006.173.07:06:31.26$pcalon/"no phase cal control is implemented here 2006.173.07:06:31.26$setupk4/"tpicd=stop 2006.173.07:06:31.26$setupk4/"rec=synch_on 2006.173.07:06:31.26$setupk4/"rec_mode=128 2006.173.07:06:31.26$setupk4/!* 2006.173.07:06:31.26$setupk4/recpk4 2006.173.07:06:31.26$recpk4/recpatch= 2006.173.07:06:31.27$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.07:06:31.27$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.07:06:31.27$setupk4/vck44 2006.173.07:06:31.27$vck44/valo=1,524.99 2006.173.07:06:31.27#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.07:06:31.27#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.07:06:31.27#ibcon#ireg 17 cls_cnt 0 2006.173.07:06:31.27#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.07:06:31.27#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.07:06:31.27#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.07:06:31.27#ibcon#enter wrdev, iclass 31, count 0 2006.173.07:06:31.27#ibcon#first serial, iclass 31, count 0 2006.173.07:06:31.27#ibcon#enter sib2, iclass 31, count 0 2006.173.07:06:31.27#ibcon#flushed, iclass 31, count 0 2006.173.07:06:31.27#ibcon#about to write, iclass 31, count 0 2006.173.07:06:31.27#ibcon#wrote, iclass 31, count 0 2006.173.07:06:31.27#ibcon#about to read 3, iclass 31, count 0 2006.173.07:06:31.29#ibcon#read 3, iclass 31, count 0 2006.173.07:06:31.29#ibcon#about to read 4, iclass 31, count 0 2006.173.07:06:31.29#ibcon#read 4, iclass 31, count 0 2006.173.07:06:31.29#ibcon#about to read 5, iclass 31, count 0 2006.173.07:06:31.29#ibcon#read 5, iclass 31, count 0 2006.173.07:06:31.29#ibcon#about to read 6, iclass 31, count 0 2006.173.07:06:31.29#ibcon#read 6, iclass 31, count 0 2006.173.07:06:31.29#ibcon#end of sib2, iclass 31, count 0 2006.173.07:06:31.29#ibcon#*mode == 0, iclass 31, count 0 2006.173.07:06:31.29#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.07:06:31.29#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.07:06:31.29#ibcon#*before write, iclass 31, count 0 2006.173.07:06:31.29#ibcon#enter sib2, iclass 31, count 0 2006.173.07:06:31.29#ibcon#flushed, iclass 31, count 0 2006.173.07:06:31.29#ibcon#about to write, iclass 31, count 0 2006.173.07:06:31.29#ibcon#wrote, iclass 31, count 0 2006.173.07:06:31.29#ibcon#about to read 3, iclass 31, count 0 2006.173.07:06:31.34#ibcon#read 3, iclass 31, count 0 2006.173.07:06:31.34#ibcon#about to read 4, iclass 31, count 0 2006.173.07:06:31.34#ibcon#read 4, iclass 31, count 0 2006.173.07:06:31.34#ibcon#about to read 5, iclass 31, count 0 2006.173.07:06:31.34#ibcon#read 5, iclass 31, count 0 2006.173.07:06:31.34#ibcon#about to read 6, iclass 31, count 0 2006.173.07:06:31.34#ibcon#read 6, iclass 31, count 0 2006.173.07:06:31.34#ibcon#end of sib2, iclass 31, count 0 2006.173.07:06:31.34#ibcon#*after write, iclass 31, count 0 2006.173.07:06:31.34#ibcon#*before return 0, iclass 31, count 0 2006.173.07:06:31.34#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.07:06:31.34#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.07:06:31.34#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.07:06:31.34#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.07:06:31.34$vck44/va=1,7 2006.173.07:06:31.34#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.173.07:06:31.34#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.173.07:06:31.34#ibcon#ireg 11 cls_cnt 2 2006.173.07:06:31.34#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.07:06:31.34#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.07:06:31.34#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.07:06:31.34#ibcon#enter wrdev, iclass 33, count 2 2006.173.07:06:31.34#ibcon#first serial, iclass 33, count 2 2006.173.07:06:31.34#ibcon#enter sib2, iclass 33, count 2 2006.173.07:06:31.34#ibcon#flushed, iclass 33, count 2 2006.173.07:06:31.34#ibcon#about to write, iclass 33, count 2 2006.173.07:06:31.34#ibcon#wrote, iclass 33, count 2 2006.173.07:06:31.34#ibcon#about to read 3, iclass 33, count 2 2006.173.07:06:31.36#ibcon#read 3, iclass 33, count 2 2006.173.07:06:31.36#ibcon#about to read 4, iclass 33, count 2 2006.173.07:06:31.36#ibcon#read 4, iclass 33, count 2 2006.173.07:06:31.36#ibcon#about to read 5, iclass 33, count 2 2006.173.07:06:31.36#ibcon#read 5, iclass 33, count 2 2006.173.07:06:31.36#ibcon#about to read 6, iclass 33, count 2 2006.173.07:06:31.36#ibcon#read 6, iclass 33, count 2 2006.173.07:06:31.36#ibcon#end of sib2, iclass 33, count 2 2006.173.07:06:31.36#ibcon#*mode == 0, iclass 33, count 2 2006.173.07:06:31.36#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.173.07:06:31.36#ibcon#[25=AT01-07\r\n] 2006.173.07:06:31.36#ibcon#*before write, iclass 33, count 2 2006.173.07:06:31.36#ibcon#enter sib2, iclass 33, count 2 2006.173.07:06:31.36#ibcon#flushed, iclass 33, count 2 2006.173.07:06:31.36#ibcon#about to write, iclass 33, count 2 2006.173.07:06:31.36#ibcon#wrote, iclass 33, count 2 2006.173.07:06:31.36#ibcon#about to read 3, iclass 33, count 2 2006.173.07:06:31.39#ibcon#read 3, iclass 33, count 2 2006.173.07:06:31.39#ibcon#about to read 4, iclass 33, count 2 2006.173.07:06:31.39#ibcon#read 4, iclass 33, count 2 2006.173.07:06:31.39#ibcon#about to read 5, iclass 33, count 2 2006.173.07:06:31.39#ibcon#read 5, iclass 33, count 2 2006.173.07:06:31.39#ibcon#about to read 6, iclass 33, count 2 2006.173.07:06:31.39#ibcon#read 6, iclass 33, count 2 2006.173.07:06:31.39#ibcon#end of sib2, iclass 33, count 2 2006.173.07:06:31.39#ibcon#*after write, iclass 33, count 2 2006.173.07:06:31.39#ibcon#*before return 0, iclass 33, count 2 2006.173.07:06:31.39#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.07:06:31.39#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.173.07:06:31.39#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.173.07:06:31.39#ibcon#ireg 7 cls_cnt 0 2006.173.07:06:31.39#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.07:06:31.51#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.07:06:31.51#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.07:06:31.51#ibcon#enter wrdev, iclass 33, count 0 2006.173.07:06:31.51#ibcon#first serial, iclass 33, count 0 2006.173.07:06:31.51#ibcon#enter sib2, iclass 33, count 0 2006.173.07:06:31.51#ibcon#flushed, iclass 33, count 0 2006.173.07:06:31.51#ibcon#about to write, iclass 33, count 0 2006.173.07:06:31.51#ibcon#wrote, iclass 33, count 0 2006.173.07:06:31.51#ibcon#about to read 3, iclass 33, count 0 2006.173.07:06:31.53#ibcon#read 3, iclass 33, count 0 2006.173.07:06:31.53#ibcon#about to read 4, iclass 33, count 0 2006.173.07:06:31.53#ibcon#read 4, iclass 33, count 0 2006.173.07:06:31.53#ibcon#about to read 5, iclass 33, count 0 2006.173.07:06:31.53#ibcon#read 5, iclass 33, count 0 2006.173.07:06:31.53#ibcon#about to read 6, iclass 33, count 0 2006.173.07:06:31.53#ibcon#read 6, iclass 33, count 0 2006.173.07:06:31.53#ibcon#end of sib2, iclass 33, count 0 2006.173.07:06:31.53#ibcon#*mode == 0, iclass 33, count 0 2006.173.07:06:31.53#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.07:06:31.53#ibcon#[25=USB\r\n] 2006.173.07:06:31.53#ibcon#*before write, iclass 33, count 0 2006.173.07:06:31.53#ibcon#enter sib2, iclass 33, count 0 2006.173.07:06:31.53#ibcon#flushed, iclass 33, count 0 2006.173.07:06:31.53#ibcon#about to write, iclass 33, count 0 2006.173.07:06:31.53#ibcon#wrote, iclass 33, count 0 2006.173.07:06:31.53#ibcon#about to read 3, iclass 33, count 0 2006.173.07:06:31.56#ibcon#read 3, iclass 33, count 0 2006.173.07:06:31.56#ibcon#about to read 4, iclass 33, count 0 2006.173.07:06:31.56#ibcon#read 4, iclass 33, count 0 2006.173.07:06:31.56#ibcon#about to read 5, iclass 33, count 0 2006.173.07:06:31.56#ibcon#read 5, iclass 33, count 0 2006.173.07:06:31.56#ibcon#about to read 6, iclass 33, count 0 2006.173.07:06:31.56#ibcon#read 6, iclass 33, count 0 2006.173.07:06:31.56#ibcon#end of sib2, iclass 33, count 0 2006.173.07:06:31.56#ibcon#*after write, iclass 33, count 0 2006.173.07:06:31.56#ibcon#*before return 0, iclass 33, count 0 2006.173.07:06:31.56#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.07:06:31.56#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.173.07:06:31.56#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.07:06:31.56#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.07:06:31.56$vck44/valo=2,534.99 2006.173.07:06:31.56#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.07:06:31.56#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.07:06:31.56#ibcon#ireg 17 cls_cnt 0 2006.173.07:06:31.56#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.07:06:31.56#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.07:06:31.56#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.07:06:31.56#ibcon#enter wrdev, iclass 35, count 0 2006.173.07:06:31.56#ibcon#first serial, iclass 35, count 0 2006.173.07:06:31.56#ibcon#enter sib2, iclass 35, count 0 2006.173.07:06:31.56#ibcon#flushed, iclass 35, count 0 2006.173.07:06:31.56#ibcon#about to write, iclass 35, count 0 2006.173.07:06:31.56#ibcon#wrote, iclass 35, count 0 2006.173.07:06:31.56#ibcon#about to read 3, iclass 35, count 0 2006.173.07:06:31.58#ibcon#read 3, iclass 35, count 0 2006.173.07:06:31.58#ibcon#about to read 4, iclass 35, count 0 2006.173.07:06:31.58#ibcon#read 4, iclass 35, count 0 2006.173.07:06:31.58#ibcon#about to read 5, iclass 35, count 0 2006.173.07:06:31.58#ibcon#read 5, iclass 35, count 0 2006.173.07:06:31.58#ibcon#about to read 6, iclass 35, count 0 2006.173.07:06:31.58#ibcon#read 6, iclass 35, count 0 2006.173.07:06:31.58#ibcon#end of sib2, iclass 35, count 0 2006.173.07:06:31.58#ibcon#*mode == 0, iclass 35, count 0 2006.173.07:06:31.58#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.07:06:31.58#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.07:06:31.58#ibcon#*before write, iclass 35, count 0 2006.173.07:06:31.58#ibcon#enter sib2, iclass 35, count 0 2006.173.07:06:31.58#ibcon#flushed, iclass 35, count 0 2006.173.07:06:31.58#ibcon#about to write, iclass 35, count 0 2006.173.07:06:31.58#ibcon#wrote, iclass 35, count 0 2006.173.07:06:31.58#ibcon#about to read 3, iclass 35, count 0 2006.173.07:06:31.62#ibcon#read 3, iclass 35, count 0 2006.173.07:06:31.62#ibcon#about to read 4, iclass 35, count 0 2006.173.07:06:31.62#ibcon#read 4, iclass 35, count 0 2006.173.07:06:31.62#ibcon#about to read 5, iclass 35, count 0 2006.173.07:06:31.62#ibcon#read 5, iclass 35, count 0 2006.173.07:06:31.62#ibcon#about to read 6, iclass 35, count 0 2006.173.07:06:31.62#ibcon#read 6, iclass 35, count 0 2006.173.07:06:31.62#ibcon#end of sib2, iclass 35, count 0 2006.173.07:06:31.62#ibcon#*after write, iclass 35, count 0 2006.173.07:06:31.62#ibcon#*before return 0, iclass 35, count 0 2006.173.07:06:31.62#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.07:06:31.62#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.07:06:31.62#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.07:06:31.62#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.07:06:31.62$vck44/va=2,6 2006.173.07:06:31.62#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.173.07:06:31.62#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.173.07:06:31.62#ibcon#ireg 11 cls_cnt 2 2006.173.07:06:31.62#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.07:06:31.68#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.07:06:31.68#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.07:06:31.68#ibcon#enter wrdev, iclass 37, count 2 2006.173.07:06:31.68#ibcon#first serial, iclass 37, count 2 2006.173.07:06:31.68#ibcon#enter sib2, iclass 37, count 2 2006.173.07:06:31.68#ibcon#flushed, iclass 37, count 2 2006.173.07:06:31.68#ibcon#about to write, iclass 37, count 2 2006.173.07:06:31.68#ibcon#wrote, iclass 37, count 2 2006.173.07:06:31.68#ibcon#about to read 3, iclass 37, count 2 2006.173.07:06:31.70#ibcon#read 3, iclass 37, count 2 2006.173.07:06:31.70#ibcon#about to read 4, iclass 37, count 2 2006.173.07:06:31.70#ibcon#read 4, iclass 37, count 2 2006.173.07:06:31.70#ibcon#about to read 5, iclass 37, count 2 2006.173.07:06:31.70#ibcon#read 5, iclass 37, count 2 2006.173.07:06:31.70#ibcon#about to read 6, iclass 37, count 2 2006.173.07:06:31.70#ibcon#read 6, iclass 37, count 2 2006.173.07:06:31.70#ibcon#end of sib2, iclass 37, count 2 2006.173.07:06:31.70#ibcon#*mode == 0, iclass 37, count 2 2006.173.07:06:31.70#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.173.07:06:31.70#ibcon#[25=AT02-06\r\n] 2006.173.07:06:31.70#ibcon#*before write, iclass 37, count 2 2006.173.07:06:31.70#ibcon#enter sib2, iclass 37, count 2 2006.173.07:06:31.70#ibcon#flushed, iclass 37, count 2 2006.173.07:06:31.70#ibcon#about to write, iclass 37, count 2 2006.173.07:06:31.70#ibcon#wrote, iclass 37, count 2 2006.173.07:06:31.70#ibcon#about to read 3, iclass 37, count 2 2006.173.07:06:31.73#ibcon#read 3, iclass 37, count 2 2006.173.07:06:31.73#ibcon#about to read 4, iclass 37, count 2 2006.173.07:06:31.73#ibcon#read 4, iclass 37, count 2 2006.173.07:06:31.73#ibcon#about to read 5, iclass 37, count 2 2006.173.07:06:31.73#ibcon#read 5, iclass 37, count 2 2006.173.07:06:31.73#ibcon#about to read 6, iclass 37, count 2 2006.173.07:06:31.73#ibcon#read 6, iclass 37, count 2 2006.173.07:06:31.73#ibcon#end of sib2, iclass 37, count 2 2006.173.07:06:31.73#ibcon#*after write, iclass 37, count 2 2006.173.07:06:31.73#ibcon#*before return 0, iclass 37, count 2 2006.173.07:06:31.73#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.07:06:31.73#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.173.07:06:31.73#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.173.07:06:31.73#ibcon#ireg 7 cls_cnt 0 2006.173.07:06:31.73#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.07:06:31.85#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.07:06:31.85#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.07:06:31.85#ibcon#enter wrdev, iclass 37, count 0 2006.173.07:06:31.85#ibcon#first serial, iclass 37, count 0 2006.173.07:06:31.85#ibcon#enter sib2, iclass 37, count 0 2006.173.07:06:31.85#ibcon#flushed, iclass 37, count 0 2006.173.07:06:31.85#ibcon#about to write, iclass 37, count 0 2006.173.07:06:31.85#ibcon#wrote, iclass 37, count 0 2006.173.07:06:31.85#ibcon#about to read 3, iclass 37, count 0 2006.173.07:06:31.87#ibcon#read 3, iclass 37, count 0 2006.173.07:06:31.87#ibcon#about to read 4, iclass 37, count 0 2006.173.07:06:31.87#ibcon#read 4, iclass 37, count 0 2006.173.07:06:31.87#ibcon#about to read 5, iclass 37, count 0 2006.173.07:06:31.87#ibcon#read 5, iclass 37, count 0 2006.173.07:06:31.87#ibcon#about to read 6, iclass 37, count 0 2006.173.07:06:31.87#ibcon#read 6, iclass 37, count 0 2006.173.07:06:31.87#ibcon#end of sib2, iclass 37, count 0 2006.173.07:06:31.87#ibcon#*mode == 0, iclass 37, count 0 2006.173.07:06:31.87#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.07:06:31.87#ibcon#[25=USB\r\n] 2006.173.07:06:31.87#ibcon#*before write, iclass 37, count 0 2006.173.07:06:31.87#ibcon#enter sib2, iclass 37, count 0 2006.173.07:06:31.87#ibcon#flushed, iclass 37, count 0 2006.173.07:06:31.87#ibcon#about to write, iclass 37, count 0 2006.173.07:06:31.87#ibcon#wrote, iclass 37, count 0 2006.173.07:06:31.87#ibcon#about to read 3, iclass 37, count 0 2006.173.07:06:31.90#ibcon#read 3, iclass 37, count 0 2006.173.07:06:31.90#ibcon#about to read 4, iclass 37, count 0 2006.173.07:06:31.90#ibcon#read 4, iclass 37, count 0 2006.173.07:06:31.90#ibcon#about to read 5, iclass 37, count 0 2006.173.07:06:31.90#ibcon#read 5, iclass 37, count 0 2006.173.07:06:31.90#ibcon#about to read 6, iclass 37, count 0 2006.173.07:06:31.90#ibcon#read 6, iclass 37, count 0 2006.173.07:06:31.90#ibcon#end of sib2, iclass 37, count 0 2006.173.07:06:31.90#ibcon#*after write, iclass 37, count 0 2006.173.07:06:31.90#ibcon#*before return 0, iclass 37, count 0 2006.173.07:06:31.90#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.07:06:31.90#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.173.07:06:31.90#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.07:06:31.90#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.07:06:31.90$vck44/valo=3,564.99 2006.173.07:06:31.90#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.07:06:31.90#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.07:06:31.90#ibcon#ireg 17 cls_cnt 0 2006.173.07:06:31.90#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.07:06:31.90#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.07:06:31.90#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.07:06:31.90#ibcon#enter wrdev, iclass 39, count 0 2006.173.07:06:31.90#ibcon#first serial, iclass 39, count 0 2006.173.07:06:31.90#ibcon#enter sib2, iclass 39, count 0 2006.173.07:06:31.90#ibcon#flushed, iclass 39, count 0 2006.173.07:06:31.90#ibcon#about to write, iclass 39, count 0 2006.173.07:06:31.90#ibcon#wrote, iclass 39, count 0 2006.173.07:06:31.90#ibcon#about to read 3, iclass 39, count 0 2006.173.07:06:31.92#ibcon#read 3, iclass 39, count 0 2006.173.07:06:31.92#ibcon#about to read 4, iclass 39, count 0 2006.173.07:06:31.92#ibcon#read 4, iclass 39, count 0 2006.173.07:06:31.92#ibcon#about to read 5, iclass 39, count 0 2006.173.07:06:31.92#ibcon#read 5, iclass 39, count 0 2006.173.07:06:31.92#ibcon#about to read 6, iclass 39, count 0 2006.173.07:06:31.92#ibcon#read 6, iclass 39, count 0 2006.173.07:06:31.92#ibcon#end of sib2, iclass 39, count 0 2006.173.07:06:31.92#ibcon#*mode == 0, iclass 39, count 0 2006.173.07:06:31.92#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.07:06:31.92#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.07:06:31.92#ibcon#*before write, iclass 39, count 0 2006.173.07:06:31.92#ibcon#enter sib2, iclass 39, count 0 2006.173.07:06:31.92#ibcon#flushed, iclass 39, count 0 2006.173.07:06:31.92#ibcon#about to write, iclass 39, count 0 2006.173.07:06:31.92#ibcon#wrote, iclass 39, count 0 2006.173.07:06:31.92#ibcon#about to read 3, iclass 39, count 0 2006.173.07:06:31.96#ibcon#read 3, iclass 39, count 0 2006.173.07:06:31.96#ibcon#about to read 4, iclass 39, count 0 2006.173.07:06:31.96#ibcon#read 4, iclass 39, count 0 2006.173.07:06:31.96#ibcon#about to read 5, iclass 39, count 0 2006.173.07:06:31.96#ibcon#read 5, iclass 39, count 0 2006.173.07:06:31.96#ibcon#about to read 6, iclass 39, count 0 2006.173.07:06:31.96#ibcon#read 6, iclass 39, count 0 2006.173.07:06:31.96#ibcon#end of sib2, iclass 39, count 0 2006.173.07:06:31.96#ibcon#*after write, iclass 39, count 0 2006.173.07:06:31.96#ibcon#*before return 0, iclass 39, count 0 2006.173.07:06:31.96#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.07:06:31.96#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.07:06:31.96#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.07:06:31.96#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.07:06:31.96$vck44/va=3,5 2006.173.07:06:31.96#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.07:06:31.96#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.07:06:31.96#ibcon#ireg 11 cls_cnt 2 2006.173.07:06:31.96#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.07:06:32.02#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.07:06:32.02#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.07:06:32.02#ibcon#enter wrdev, iclass 3, count 2 2006.173.07:06:32.02#ibcon#first serial, iclass 3, count 2 2006.173.07:06:32.02#ibcon#enter sib2, iclass 3, count 2 2006.173.07:06:32.02#ibcon#flushed, iclass 3, count 2 2006.173.07:06:32.02#ibcon#about to write, iclass 3, count 2 2006.173.07:06:32.02#ibcon#wrote, iclass 3, count 2 2006.173.07:06:32.02#ibcon#about to read 3, iclass 3, count 2 2006.173.07:06:32.04#ibcon#read 3, iclass 3, count 2 2006.173.07:06:32.04#ibcon#about to read 4, iclass 3, count 2 2006.173.07:06:32.04#ibcon#read 4, iclass 3, count 2 2006.173.07:06:32.04#ibcon#about to read 5, iclass 3, count 2 2006.173.07:06:32.04#ibcon#read 5, iclass 3, count 2 2006.173.07:06:32.04#ibcon#about to read 6, iclass 3, count 2 2006.173.07:06:32.04#ibcon#read 6, iclass 3, count 2 2006.173.07:06:32.04#ibcon#end of sib2, iclass 3, count 2 2006.173.07:06:32.04#ibcon#*mode == 0, iclass 3, count 2 2006.173.07:06:32.04#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.07:06:32.04#ibcon#[25=AT03-05\r\n] 2006.173.07:06:32.04#ibcon#*before write, iclass 3, count 2 2006.173.07:06:32.04#ibcon#enter sib2, iclass 3, count 2 2006.173.07:06:32.04#ibcon#flushed, iclass 3, count 2 2006.173.07:06:32.04#ibcon#about to write, iclass 3, count 2 2006.173.07:06:32.04#ibcon#wrote, iclass 3, count 2 2006.173.07:06:32.04#ibcon#about to read 3, iclass 3, count 2 2006.173.07:06:32.07#ibcon#read 3, iclass 3, count 2 2006.173.07:06:32.07#ibcon#about to read 4, iclass 3, count 2 2006.173.07:06:32.07#ibcon#read 4, iclass 3, count 2 2006.173.07:06:32.07#ibcon#about to read 5, iclass 3, count 2 2006.173.07:06:32.07#ibcon#read 5, iclass 3, count 2 2006.173.07:06:32.07#ibcon#about to read 6, iclass 3, count 2 2006.173.07:06:32.07#ibcon#read 6, iclass 3, count 2 2006.173.07:06:32.07#ibcon#end of sib2, iclass 3, count 2 2006.173.07:06:32.07#ibcon#*after write, iclass 3, count 2 2006.173.07:06:32.07#ibcon#*before return 0, iclass 3, count 2 2006.173.07:06:32.07#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.07:06:32.07#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.07:06:32.07#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.07:06:32.07#ibcon#ireg 7 cls_cnt 0 2006.173.07:06:32.07#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.07:06:32.19#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.07:06:32.19#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.07:06:32.19#ibcon#enter wrdev, iclass 3, count 0 2006.173.07:06:32.19#ibcon#first serial, iclass 3, count 0 2006.173.07:06:32.19#ibcon#enter sib2, iclass 3, count 0 2006.173.07:06:32.19#ibcon#flushed, iclass 3, count 0 2006.173.07:06:32.19#ibcon#about to write, iclass 3, count 0 2006.173.07:06:32.19#ibcon#wrote, iclass 3, count 0 2006.173.07:06:32.19#ibcon#about to read 3, iclass 3, count 0 2006.173.07:06:32.21#ibcon#read 3, iclass 3, count 0 2006.173.07:06:32.21#ibcon#about to read 4, iclass 3, count 0 2006.173.07:06:32.21#ibcon#read 4, iclass 3, count 0 2006.173.07:06:32.21#ibcon#about to read 5, iclass 3, count 0 2006.173.07:06:32.21#ibcon#read 5, iclass 3, count 0 2006.173.07:06:32.21#ibcon#about to read 6, iclass 3, count 0 2006.173.07:06:32.21#ibcon#read 6, iclass 3, count 0 2006.173.07:06:32.21#ibcon#end of sib2, iclass 3, count 0 2006.173.07:06:32.21#ibcon#*mode == 0, iclass 3, count 0 2006.173.07:06:32.21#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.07:06:32.21#ibcon#[25=USB\r\n] 2006.173.07:06:32.21#ibcon#*before write, iclass 3, count 0 2006.173.07:06:32.21#ibcon#enter sib2, iclass 3, count 0 2006.173.07:06:32.21#ibcon#flushed, iclass 3, count 0 2006.173.07:06:32.21#ibcon#about to write, iclass 3, count 0 2006.173.07:06:32.21#ibcon#wrote, iclass 3, count 0 2006.173.07:06:32.21#ibcon#about to read 3, iclass 3, count 0 2006.173.07:06:32.24#ibcon#read 3, iclass 3, count 0 2006.173.07:06:32.24#ibcon#about to read 4, iclass 3, count 0 2006.173.07:06:32.24#ibcon#read 4, iclass 3, count 0 2006.173.07:06:32.24#ibcon#about to read 5, iclass 3, count 0 2006.173.07:06:32.24#ibcon#read 5, iclass 3, count 0 2006.173.07:06:32.24#ibcon#about to read 6, iclass 3, count 0 2006.173.07:06:32.24#ibcon#read 6, iclass 3, count 0 2006.173.07:06:32.24#ibcon#end of sib2, iclass 3, count 0 2006.173.07:06:32.24#ibcon#*after write, iclass 3, count 0 2006.173.07:06:32.24#ibcon#*before return 0, iclass 3, count 0 2006.173.07:06:32.24#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.07:06:32.24#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.07:06:32.24#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.07:06:32.24#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.07:06:32.24$vck44/valo=4,624.99 2006.173.07:06:32.24#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.07:06:32.24#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.07:06:32.24#ibcon#ireg 17 cls_cnt 0 2006.173.07:06:32.24#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.07:06:32.24#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.07:06:32.24#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.07:06:32.24#ibcon#enter wrdev, iclass 5, count 0 2006.173.07:06:32.24#ibcon#first serial, iclass 5, count 0 2006.173.07:06:32.24#ibcon#enter sib2, iclass 5, count 0 2006.173.07:06:32.24#ibcon#flushed, iclass 5, count 0 2006.173.07:06:32.24#ibcon#about to write, iclass 5, count 0 2006.173.07:06:32.24#ibcon#wrote, iclass 5, count 0 2006.173.07:06:32.24#ibcon#about to read 3, iclass 5, count 0 2006.173.07:06:32.26#ibcon#read 3, iclass 5, count 0 2006.173.07:06:32.26#ibcon#about to read 4, iclass 5, count 0 2006.173.07:06:32.26#ibcon#read 4, iclass 5, count 0 2006.173.07:06:32.26#ibcon#about to read 5, iclass 5, count 0 2006.173.07:06:32.26#ibcon#read 5, iclass 5, count 0 2006.173.07:06:32.26#ibcon#about to read 6, iclass 5, count 0 2006.173.07:06:32.26#ibcon#read 6, iclass 5, count 0 2006.173.07:06:32.26#ibcon#end of sib2, iclass 5, count 0 2006.173.07:06:32.26#ibcon#*mode == 0, iclass 5, count 0 2006.173.07:06:32.26#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.07:06:32.26#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.07:06:32.26#ibcon#*before write, iclass 5, count 0 2006.173.07:06:32.26#ibcon#enter sib2, iclass 5, count 0 2006.173.07:06:32.26#ibcon#flushed, iclass 5, count 0 2006.173.07:06:32.26#ibcon#about to write, iclass 5, count 0 2006.173.07:06:32.26#ibcon#wrote, iclass 5, count 0 2006.173.07:06:32.26#ibcon#about to read 3, iclass 5, count 0 2006.173.07:06:32.30#ibcon#read 3, iclass 5, count 0 2006.173.07:06:32.30#ibcon#about to read 4, iclass 5, count 0 2006.173.07:06:32.30#ibcon#read 4, iclass 5, count 0 2006.173.07:06:32.30#ibcon#about to read 5, iclass 5, count 0 2006.173.07:06:32.30#ibcon#read 5, iclass 5, count 0 2006.173.07:06:32.30#ibcon#about to read 6, iclass 5, count 0 2006.173.07:06:32.30#ibcon#read 6, iclass 5, count 0 2006.173.07:06:32.30#ibcon#end of sib2, iclass 5, count 0 2006.173.07:06:32.30#ibcon#*after write, iclass 5, count 0 2006.173.07:06:32.30#ibcon#*before return 0, iclass 5, count 0 2006.173.07:06:32.30#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.07:06:32.30#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.07:06:32.30#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.07:06:32.30#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.07:06:32.30$vck44/va=4,6 2006.173.07:06:32.30#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.173.07:06:32.30#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.173.07:06:32.30#ibcon#ireg 11 cls_cnt 2 2006.173.07:06:32.30#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.07:06:32.36#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.07:06:32.36#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.07:06:32.36#ibcon#enter wrdev, iclass 7, count 2 2006.173.07:06:32.36#ibcon#first serial, iclass 7, count 2 2006.173.07:06:32.36#ibcon#enter sib2, iclass 7, count 2 2006.173.07:06:32.36#ibcon#flushed, iclass 7, count 2 2006.173.07:06:32.36#ibcon#about to write, iclass 7, count 2 2006.173.07:06:32.36#ibcon#wrote, iclass 7, count 2 2006.173.07:06:32.36#ibcon#about to read 3, iclass 7, count 2 2006.173.07:06:32.38#ibcon#read 3, iclass 7, count 2 2006.173.07:06:32.38#ibcon#about to read 4, iclass 7, count 2 2006.173.07:06:32.38#ibcon#read 4, iclass 7, count 2 2006.173.07:06:32.38#ibcon#about to read 5, iclass 7, count 2 2006.173.07:06:32.38#ibcon#read 5, iclass 7, count 2 2006.173.07:06:32.38#ibcon#about to read 6, iclass 7, count 2 2006.173.07:06:32.38#ibcon#read 6, iclass 7, count 2 2006.173.07:06:32.38#ibcon#end of sib2, iclass 7, count 2 2006.173.07:06:32.38#ibcon#*mode == 0, iclass 7, count 2 2006.173.07:06:32.38#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.173.07:06:32.38#ibcon#[25=AT04-06\r\n] 2006.173.07:06:32.38#ibcon#*before write, iclass 7, count 2 2006.173.07:06:32.38#ibcon#enter sib2, iclass 7, count 2 2006.173.07:06:32.38#ibcon#flushed, iclass 7, count 2 2006.173.07:06:32.38#ibcon#about to write, iclass 7, count 2 2006.173.07:06:32.38#ibcon#wrote, iclass 7, count 2 2006.173.07:06:32.38#ibcon#about to read 3, iclass 7, count 2 2006.173.07:06:32.41#ibcon#read 3, iclass 7, count 2 2006.173.07:06:32.41#ibcon#about to read 4, iclass 7, count 2 2006.173.07:06:32.41#ibcon#read 4, iclass 7, count 2 2006.173.07:06:32.41#ibcon#about to read 5, iclass 7, count 2 2006.173.07:06:32.41#ibcon#read 5, iclass 7, count 2 2006.173.07:06:32.41#ibcon#about to read 6, iclass 7, count 2 2006.173.07:06:32.41#ibcon#read 6, iclass 7, count 2 2006.173.07:06:32.41#ibcon#end of sib2, iclass 7, count 2 2006.173.07:06:32.41#ibcon#*after write, iclass 7, count 2 2006.173.07:06:32.41#ibcon#*before return 0, iclass 7, count 2 2006.173.07:06:32.41#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.07:06:32.41#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.173.07:06:32.41#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.173.07:06:32.41#ibcon#ireg 7 cls_cnt 0 2006.173.07:06:32.41#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.07:06:32.53#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.07:06:32.53#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.07:06:32.53#ibcon#enter wrdev, iclass 7, count 0 2006.173.07:06:32.53#ibcon#first serial, iclass 7, count 0 2006.173.07:06:32.53#ibcon#enter sib2, iclass 7, count 0 2006.173.07:06:32.53#ibcon#flushed, iclass 7, count 0 2006.173.07:06:32.53#ibcon#about to write, iclass 7, count 0 2006.173.07:06:32.53#ibcon#wrote, iclass 7, count 0 2006.173.07:06:32.53#ibcon#about to read 3, iclass 7, count 0 2006.173.07:06:32.55#ibcon#read 3, iclass 7, count 0 2006.173.07:06:32.55#ibcon#about to read 4, iclass 7, count 0 2006.173.07:06:32.55#ibcon#read 4, iclass 7, count 0 2006.173.07:06:32.55#ibcon#about to read 5, iclass 7, count 0 2006.173.07:06:32.55#ibcon#read 5, iclass 7, count 0 2006.173.07:06:32.55#ibcon#about to read 6, iclass 7, count 0 2006.173.07:06:32.55#ibcon#read 6, iclass 7, count 0 2006.173.07:06:32.55#ibcon#end of sib2, iclass 7, count 0 2006.173.07:06:32.55#ibcon#*mode == 0, iclass 7, count 0 2006.173.07:06:32.55#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.07:06:32.55#ibcon#[25=USB\r\n] 2006.173.07:06:32.55#ibcon#*before write, iclass 7, count 0 2006.173.07:06:32.55#ibcon#enter sib2, iclass 7, count 0 2006.173.07:06:32.55#ibcon#flushed, iclass 7, count 0 2006.173.07:06:32.55#ibcon#about to write, iclass 7, count 0 2006.173.07:06:32.55#ibcon#wrote, iclass 7, count 0 2006.173.07:06:32.55#ibcon#about to read 3, iclass 7, count 0 2006.173.07:06:32.58#ibcon#read 3, iclass 7, count 0 2006.173.07:06:32.58#ibcon#about to read 4, iclass 7, count 0 2006.173.07:06:32.58#ibcon#read 4, iclass 7, count 0 2006.173.07:06:32.58#ibcon#about to read 5, iclass 7, count 0 2006.173.07:06:32.58#ibcon#read 5, iclass 7, count 0 2006.173.07:06:32.58#ibcon#about to read 6, iclass 7, count 0 2006.173.07:06:32.58#ibcon#read 6, iclass 7, count 0 2006.173.07:06:32.58#ibcon#end of sib2, iclass 7, count 0 2006.173.07:06:32.58#ibcon#*after write, iclass 7, count 0 2006.173.07:06:32.58#ibcon#*before return 0, iclass 7, count 0 2006.173.07:06:32.58#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.07:06:32.58#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.173.07:06:32.58#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.07:06:32.58#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.07:06:32.58$vck44/valo=5,734.99 2006.173.07:06:32.58#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.07:06:32.58#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.07:06:32.58#ibcon#ireg 17 cls_cnt 0 2006.173.07:06:32.58#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.07:06:32.58#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.07:06:32.58#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.07:06:32.58#ibcon#enter wrdev, iclass 11, count 0 2006.173.07:06:32.58#ibcon#first serial, iclass 11, count 0 2006.173.07:06:32.58#ibcon#enter sib2, iclass 11, count 0 2006.173.07:06:32.58#ibcon#flushed, iclass 11, count 0 2006.173.07:06:32.58#ibcon#about to write, iclass 11, count 0 2006.173.07:06:32.58#ibcon#wrote, iclass 11, count 0 2006.173.07:06:32.58#ibcon#about to read 3, iclass 11, count 0 2006.173.07:06:32.60#ibcon#read 3, iclass 11, count 0 2006.173.07:06:32.60#ibcon#about to read 4, iclass 11, count 0 2006.173.07:06:32.60#ibcon#read 4, iclass 11, count 0 2006.173.07:06:32.60#ibcon#about to read 5, iclass 11, count 0 2006.173.07:06:32.60#ibcon#read 5, iclass 11, count 0 2006.173.07:06:32.60#ibcon#about to read 6, iclass 11, count 0 2006.173.07:06:32.60#ibcon#read 6, iclass 11, count 0 2006.173.07:06:32.60#ibcon#end of sib2, iclass 11, count 0 2006.173.07:06:32.60#ibcon#*mode == 0, iclass 11, count 0 2006.173.07:06:32.60#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.07:06:32.60#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.07:06:32.60#ibcon#*before write, iclass 11, count 0 2006.173.07:06:32.60#ibcon#enter sib2, iclass 11, count 0 2006.173.07:06:32.60#ibcon#flushed, iclass 11, count 0 2006.173.07:06:32.60#ibcon#about to write, iclass 11, count 0 2006.173.07:06:32.60#ibcon#wrote, iclass 11, count 0 2006.173.07:06:32.60#ibcon#about to read 3, iclass 11, count 0 2006.173.07:06:32.64#ibcon#read 3, iclass 11, count 0 2006.173.07:06:32.64#ibcon#about to read 4, iclass 11, count 0 2006.173.07:06:32.64#ibcon#read 4, iclass 11, count 0 2006.173.07:06:32.64#ibcon#about to read 5, iclass 11, count 0 2006.173.07:06:32.64#ibcon#read 5, iclass 11, count 0 2006.173.07:06:32.64#ibcon#about to read 6, iclass 11, count 0 2006.173.07:06:32.64#ibcon#read 6, iclass 11, count 0 2006.173.07:06:32.64#ibcon#end of sib2, iclass 11, count 0 2006.173.07:06:32.64#ibcon#*after write, iclass 11, count 0 2006.173.07:06:32.64#ibcon#*before return 0, iclass 11, count 0 2006.173.07:06:32.64#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.07:06:32.64#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.07:06:32.64#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.07:06:32.64#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.07:06:32.64$vck44/va=5,4 2006.173.07:06:32.64#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.173.07:06:32.64#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.173.07:06:32.64#ibcon#ireg 11 cls_cnt 2 2006.173.07:06:32.64#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.07:06:32.70#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.07:06:32.70#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.07:06:32.70#ibcon#enter wrdev, iclass 13, count 2 2006.173.07:06:32.70#ibcon#first serial, iclass 13, count 2 2006.173.07:06:32.70#ibcon#enter sib2, iclass 13, count 2 2006.173.07:06:32.70#ibcon#flushed, iclass 13, count 2 2006.173.07:06:32.70#ibcon#about to write, iclass 13, count 2 2006.173.07:06:32.70#ibcon#wrote, iclass 13, count 2 2006.173.07:06:32.70#ibcon#about to read 3, iclass 13, count 2 2006.173.07:06:32.72#ibcon#read 3, iclass 13, count 2 2006.173.07:06:32.72#ibcon#about to read 4, iclass 13, count 2 2006.173.07:06:32.72#ibcon#read 4, iclass 13, count 2 2006.173.07:06:32.72#ibcon#about to read 5, iclass 13, count 2 2006.173.07:06:32.72#ibcon#read 5, iclass 13, count 2 2006.173.07:06:32.72#ibcon#about to read 6, iclass 13, count 2 2006.173.07:06:32.72#ibcon#read 6, iclass 13, count 2 2006.173.07:06:32.72#ibcon#end of sib2, iclass 13, count 2 2006.173.07:06:32.72#ibcon#*mode == 0, iclass 13, count 2 2006.173.07:06:32.72#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.173.07:06:32.72#ibcon#[25=AT05-04\r\n] 2006.173.07:06:32.72#ibcon#*before write, iclass 13, count 2 2006.173.07:06:32.72#ibcon#enter sib2, iclass 13, count 2 2006.173.07:06:32.72#ibcon#flushed, iclass 13, count 2 2006.173.07:06:32.72#ibcon#about to write, iclass 13, count 2 2006.173.07:06:32.72#ibcon#wrote, iclass 13, count 2 2006.173.07:06:32.72#ibcon#about to read 3, iclass 13, count 2 2006.173.07:06:32.75#ibcon#read 3, iclass 13, count 2 2006.173.07:06:32.75#ibcon#about to read 4, iclass 13, count 2 2006.173.07:06:32.75#ibcon#read 4, iclass 13, count 2 2006.173.07:06:32.75#ibcon#about to read 5, iclass 13, count 2 2006.173.07:06:32.75#ibcon#read 5, iclass 13, count 2 2006.173.07:06:32.75#ibcon#about to read 6, iclass 13, count 2 2006.173.07:06:32.75#ibcon#read 6, iclass 13, count 2 2006.173.07:06:32.75#ibcon#end of sib2, iclass 13, count 2 2006.173.07:06:32.75#ibcon#*after write, iclass 13, count 2 2006.173.07:06:32.75#ibcon#*before return 0, iclass 13, count 2 2006.173.07:06:32.75#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.07:06:32.75#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.173.07:06:32.75#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.173.07:06:32.75#ibcon#ireg 7 cls_cnt 0 2006.173.07:06:32.75#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.07:06:32.87#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.07:06:32.87#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.07:06:32.87#ibcon#enter wrdev, iclass 13, count 0 2006.173.07:06:32.87#ibcon#first serial, iclass 13, count 0 2006.173.07:06:32.87#ibcon#enter sib2, iclass 13, count 0 2006.173.07:06:32.87#ibcon#flushed, iclass 13, count 0 2006.173.07:06:32.87#ibcon#about to write, iclass 13, count 0 2006.173.07:06:32.87#ibcon#wrote, iclass 13, count 0 2006.173.07:06:32.87#ibcon#about to read 3, iclass 13, count 0 2006.173.07:06:32.89#ibcon#read 3, iclass 13, count 0 2006.173.07:06:32.89#ibcon#about to read 4, iclass 13, count 0 2006.173.07:06:32.89#ibcon#read 4, iclass 13, count 0 2006.173.07:06:32.89#ibcon#about to read 5, iclass 13, count 0 2006.173.07:06:32.89#ibcon#read 5, iclass 13, count 0 2006.173.07:06:32.89#ibcon#about to read 6, iclass 13, count 0 2006.173.07:06:32.89#ibcon#read 6, iclass 13, count 0 2006.173.07:06:32.89#ibcon#end of sib2, iclass 13, count 0 2006.173.07:06:32.89#ibcon#*mode == 0, iclass 13, count 0 2006.173.07:06:32.89#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.07:06:32.89#ibcon#[25=USB\r\n] 2006.173.07:06:32.89#ibcon#*before write, iclass 13, count 0 2006.173.07:06:32.89#ibcon#enter sib2, iclass 13, count 0 2006.173.07:06:32.89#ibcon#flushed, iclass 13, count 0 2006.173.07:06:32.89#ibcon#about to write, iclass 13, count 0 2006.173.07:06:32.89#ibcon#wrote, iclass 13, count 0 2006.173.07:06:32.89#ibcon#about to read 3, iclass 13, count 0 2006.173.07:06:32.92#ibcon#read 3, iclass 13, count 0 2006.173.07:06:32.92#ibcon#about to read 4, iclass 13, count 0 2006.173.07:06:32.92#ibcon#read 4, iclass 13, count 0 2006.173.07:06:32.92#ibcon#about to read 5, iclass 13, count 0 2006.173.07:06:32.92#ibcon#read 5, iclass 13, count 0 2006.173.07:06:32.92#ibcon#about to read 6, iclass 13, count 0 2006.173.07:06:32.92#ibcon#read 6, iclass 13, count 0 2006.173.07:06:32.92#ibcon#end of sib2, iclass 13, count 0 2006.173.07:06:32.92#ibcon#*after write, iclass 13, count 0 2006.173.07:06:32.92#ibcon#*before return 0, iclass 13, count 0 2006.173.07:06:32.92#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.07:06:32.92#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.173.07:06:32.92#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.07:06:32.92#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.07:06:32.92$vck44/valo=6,814.99 2006.173.07:06:32.92#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.07:06:32.92#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.07:06:32.92#ibcon#ireg 17 cls_cnt 0 2006.173.07:06:32.92#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.07:06:32.92#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.07:06:32.92#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.07:06:32.92#ibcon#enter wrdev, iclass 15, count 0 2006.173.07:06:32.92#ibcon#first serial, iclass 15, count 0 2006.173.07:06:32.92#ibcon#enter sib2, iclass 15, count 0 2006.173.07:06:32.92#ibcon#flushed, iclass 15, count 0 2006.173.07:06:32.92#ibcon#about to write, iclass 15, count 0 2006.173.07:06:32.92#ibcon#wrote, iclass 15, count 0 2006.173.07:06:32.92#ibcon#about to read 3, iclass 15, count 0 2006.173.07:06:32.94#ibcon#read 3, iclass 15, count 0 2006.173.07:06:32.94#ibcon#about to read 4, iclass 15, count 0 2006.173.07:06:32.94#ibcon#read 4, iclass 15, count 0 2006.173.07:06:32.94#ibcon#about to read 5, iclass 15, count 0 2006.173.07:06:32.94#ibcon#read 5, iclass 15, count 0 2006.173.07:06:32.94#ibcon#about to read 6, iclass 15, count 0 2006.173.07:06:32.94#ibcon#read 6, iclass 15, count 0 2006.173.07:06:32.94#ibcon#end of sib2, iclass 15, count 0 2006.173.07:06:32.94#ibcon#*mode == 0, iclass 15, count 0 2006.173.07:06:32.94#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.07:06:32.94#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.07:06:32.94#ibcon#*before write, iclass 15, count 0 2006.173.07:06:32.94#ibcon#enter sib2, iclass 15, count 0 2006.173.07:06:32.94#ibcon#flushed, iclass 15, count 0 2006.173.07:06:32.94#ibcon#about to write, iclass 15, count 0 2006.173.07:06:32.94#ibcon#wrote, iclass 15, count 0 2006.173.07:06:32.94#ibcon#about to read 3, iclass 15, count 0 2006.173.07:06:32.98#ibcon#read 3, iclass 15, count 0 2006.173.07:06:32.98#ibcon#about to read 4, iclass 15, count 0 2006.173.07:06:32.98#ibcon#read 4, iclass 15, count 0 2006.173.07:06:32.98#ibcon#about to read 5, iclass 15, count 0 2006.173.07:06:32.98#ibcon#read 5, iclass 15, count 0 2006.173.07:06:32.98#ibcon#about to read 6, iclass 15, count 0 2006.173.07:06:32.98#ibcon#read 6, iclass 15, count 0 2006.173.07:06:32.98#ibcon#end of sib2, iclass 15, count 0 2006.173.07:06:32.98#ibcon#*after write, iclass 15, count 0 2006.173.07:06:32.98#ibcon#*before return 0, iclass 15, count 0 2006.173.07:06:32.98#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.07:06:32.98#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.07:06:32.98#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.07:06:32.98#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.07:06:32.98$vck44/va=6,3 2006.173.07:06:32.98#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.07:06:32.98#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.07:06:32.98#ibcon#ireg 11 cls_cnt 2 2006.173.07:06:32.98#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.07:06:33.04#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.07:06:33.04#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.07:06:33.04#ibcon#enter wrdev, iclass 17, count 2 2006.173.07:06:33.04#ibcon#first serial, iclass 17, count 2 2006.173.07:06:33.04#ibcon#enter sib2, iclass 17, count 2 2006.173.07:06:33.04#ibcon#flushed, iclass 17, count 2 2006.173.07:06:33.04#ibcon#about to write, iclass 17, count 2 2006.173.07:06:33.04#ibcon#wrote, iclass 17, count 2 2006.173.07:06:33.04#ibcon#about to read 3, iclass 17, count 2 2006.173.07:06:33.06#ibcon#read 3, iclass 17, count 2 2006.173.07:06:33.06#ibcon#about to read 4, iclass 17, count 2 2006.173.07:06:33.06#ibcon#read 4, iclass 17, count 2 2006.173.07:06:33.06#ibcon#about to read 5, iclass 17, count 2 2006.173.07:06:33.06#ibcon#read 5, iclass 17, count 2 2006.173.07:06:33.06#ibcon#about to read 6, iclass 17, count 2 2006.173.07:06:33.06#ibcon#read 6, iclass 17, count 2 2006.173.07:06:33.06#ibcon#end of sib2, iclass 17, count 2 2006.173.07:06:33.06#ibcon#*mode == 0, iclass 17, count 2 2006.173.07:06:33.06#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.07:06:33.06#ibcon#[25=AT06-03\r\n] 2006.173.07:06:33.06#ibcon#*before write, iclass 17, count 2 2006.173.07:06:33.06#ibcon#enter sib2, iclass 17, count 2 2006.173.07:06:33.06#ibcon#flushed, iclass 17, count 2 2006.173.07:06:33.06#ibcon#about to write, iclass 17, count 2 2006.173.07:06:33.06#ibcon#wrote, iclass 17, count 2 2006.173.07:06:33.06#ibcon#about to read 3, iclass 17, count 2 2006.173.07:06:33.09#ibcon#read 3, iclass 17, count 2 2006.173.07:06:33.09#ibcon#about to read 4, iclass 17, count 2 2006.173.07:06:33.09#ibcon#read 4, iclass 17, count 2 2006.173.07:06:33.09#ibcon#about to read 5, iclass 17, count 2 2006.173.07:06:33.09#ibcon#read 5, iclass 17, count 2 2006.173.07:06:33.09#ibcon#about to read 6, iclass 17, count 2 2006.173.07:06:33.09#ibcon#read 6, iclass 17, count 2 2006.173.07:06:33.09#ibcon#end of sib2, iclass 17, count 2 2006.173.07:06:33.09#ibcon#*after write, iclass 17, count 2 2006.173.07:06:33.09#ibcon#*before return 0, iclass 17, count 2 2006.173.07:06:33.09#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.07:06:33.09#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.07:06:33.09#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.07:06:33.09#ibcon#ireg 7 cls_cnt 0 2006.173.07:06:33.09#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.07:06:33.21#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.07:06:33.21#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.07:06:33.21#ibcon#enter wrdev, iclass 17, count 0 2006.173.07:06:33.21#ibcon#first serial, iclass 17, count 0 2006.173.07:06:33.21#ibcon#enter sib2, iclass 17, count 0 2006.173.07:06:33.21#ibcon#flushed, iclass 17, count 0 2006.173.07:06:33.21#ibcon#about to write, iclass 17, count 0 2006.173.07:06:33.21#ibcon#wrote, iclass 17, count 0 2006.173.07:06:33.21#ibcon#about to read 3, iclass 17, count 0 2006.173.07:06:33.23#ibcon#read 3, iclass 17, count 0 2006.173.07:06:33.23#ibcon#about to read 4, iclass 17, count 0 2006.173.07:06:33.23#ibcon#read 4, iclass 17, count 0 2006.173.07:06:33.23#ibcon#about to read 5, iclass 17, count 0 2006.173.07:06:33.23#ibcon#read 5, iclass 17, count 0 2006.173.07:06:33.23#ibcon#about to read 6, iclass 17, count 0 2006.173.07:06:33.23#ibcon#read 6, iclass 17, count 0 2006.173.07:06:33.23#ibcon#end of sib2, iclass 17, count 0 2006.173.07:06:33.23#ibcon#*mode == 0, iclass 17, count 0 2006.173.07:06:33.23#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.07:06:33.23#ibcon#[25=USB\r\n] 2006.173.07:06:33.23#ibcon#*before write, iclass 17, count 0 2006.173.07:06:33.23#ibcon#enter sib2, iclass 17, count 0 2006.173.07:06:33.23#ibcon#flushed, iclass 17, count 0 2006.173.07:06:33.23#ibcon#about to write, iclass 17, count 0 2006.173.07:06:33.23#ibcon#wrote, iclass 17, count 0 2006.173.07:06:33.23#ibcon#about to read 3, iclass 17, count 0 2006.173.07:06:33.26#ibcon#read 3, iclass 17, count 0 2006.173.07:06:33.26#ibcon#about to read 4, iclass 17, count 0 2006.173.07:06:33.26#ibcon#read 4, iclass 17, count 0 2006.173.07:06:33.26#ibcon#about to read 5, iclass 17, count 0 2006.173.07:06:33.26#ibcon#read 5, iclass 17, count 0 2006.173.07:06:33.26#ibcon#about to read 6, iclass 17, count 0 2006.173.07:06:33.26#ibcon#read 6, iclass 17, count 0 2006.173.07:06:33.26#ibcon#end of sib2, iclass 17, count 0 2006.173.07:06:33.26#ibcon#*after write, iclass 17, count 0 2006.173.07:06:33.26#ibcon#*before return 0, iclass 17, count 0 2006.173.07:06:33.26#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.07:06:33.26#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.07:06:33.26#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.07:06:33.26#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.07:06:33.26$vck44/valo=7,864.99 2006.173.07:06:33.26#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.07:06:33.26#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.07:06:33.26#ibcon#ireg 17 cls_cnt 0 2006.173.07:06:33.26#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.07:06:33.26#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.07:06:33.26#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.07:06:33.26#ibcon#enter wrdev, iclass 19, count 0 2006.173.07:06:33.26#ibcon#first serial, iclass 19, count 0 2006.173.07:06:33.26#ibcon#enter sib2, iclass 19, count 0 2006.173.07:06:33.26#ibcon#flushed, iclass 19, count 0 2006.173.07:06:33.26#ibcon#about to write, iclass 19, count 0 2006.173.07:06:33.26#ibcon#wrote, iclass 19, count 0 2006.173.07:06:33.26#ibcon#about to read 3, iclass 19, count 0 2006.173.07:06:33.28#ibcon#read 3, iclass 19, count 0 2006.173.07:06:33.28#ibcon#about to read 4, iclass 19, count 0 2006.173.07:06:33.28#ibcon#read 4, iclass 19, count 0 2006.173.07:06:33.28#ibcon#about to read 5, iclass 19, count 0 2006.173.07:06:33.28#ibcon#read 5, iclass 19, count 0 2006.173.07:06:33.28#ibcon#about to read 6, iclass 19, count 0 2006.173.07:06:33.28#ibcon#read 6, iclass 19, count 0 2006.173.07:06:33.28#ibcon#end of sib2, iclass 19, count 0 2006.173.07:06:33.28#ibcon#*mode == 0, iclass 19, count 0 2006.173.07:06:33.28#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.07:06:33.28#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.07:06:33.28#ibcon#*before write, iclass 19, count 0 2006.173.07:06:33.28#ibcon#enter sib2, iclass 19, count 0 2006.173.07:06:33.28#ibcon#flushed, iclass 19, count 0 2006.173.07:06:33.28#ibcon#about to write, iclass 19, count 0 2006.173.07:06:33.28#ibcon#wrote, iclass 19, count 0 2006.173.07:06:33.28#ibcon#about to read 3, iclass 19, count 0 2006.173.07:06:33.32#ibcon#read 3, iclass 19, count 0 2006.173.07:06:33.32#ibcon#about to read 4, iclass 19, count 0 2006.173.07:06:33.32#ibcon#read 4, iclass 19, count 0 2006.173.07:06:33.32#ibcon#about to read 5, iclass 19, count 0 2006.173.07:06:33.32#ibcon#read 5, iclass 19, count 0 2006.173.07:06:33.32#ibcon#about to read 6, iclass 19, count 0 2006.173.07:06:33.32#ibcon#read 6, iclass 19, count 0 2006.173.07:06:33.32#ibcon#end of sib2, iclass 19, count 0 2006.173.07:06:33.32#ibcon#*after write, iclass 19, count 0 2006.173.07:06:33.32#ibcon#*before return 0, iclass 19, count 0 2006.173.07:06:33.32#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.07:06:33.32#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.07:06:33.32#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.07:06:33.32#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.07:06:33.32$vck44/va=7,4 2006.173.07:06:33.32#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.07:06:33.32#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.07:06:33.32#ibcon#ireg 11 cls_cnt 2 2006.173.07:06:33.32#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.07:06:33.38#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.07:06:33.38#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.07:06:33.38#ibcon#enter wrdev, iclass 21, count 2 2006.173.07:06:33.38#ibcon#first serial, iclass 21, count 2 2006.173.07:06:33.38#ibcon#enter sib2, iclass 21, count 2 2006.173.07:06:33.38#ibcon#flushed, iclass 21, count 2 2006.173.07:06:33.38#ibcon#about to write, iclass 21, count 2 2006.173.07:06:33.38#ibcon#wrote, iclass 21, count 2 2006.173.07:06:33.38#ibcon#about to read 3, iclass 21, count 2 2006.173.07:06:33.40#ibcon#read 3, iclass 21, count 2 2006.173.07:06:33.40#ibcon#about to read 4, iclass 21, count 2 2006.173.07:06:33.40#ibcon#read 4, iclass 21, count 2 2006.173.07:06:33.40#ibcon#about to read 5, iclass 21, count 2 2006.173.07:06:33.40#ibcon#read 5, iclass 21, count 2 2006.173.07:06:33.40#ibcon#about to read 6, iclass 21, count 2 2006.173.07:06:33.40#ibcon#read 6, iclass 21, count 2 2006.173.07:06:33.40#ibcon#end of sib2, iclass 21, count 2 2006.173.07:06:33.40#ibcon#*mode == 0, iclass 21, count 2 2006.173.07:06:33.40#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.07:06:33.40#ibcon#[25=AT07-04\r\n] 2006.173.07:06:33.40#ibcon#*before write, iclass 21, count 2 2006.173.07:06:33.40#ibcon#enter sib2, iclass 21, count 2 2006.173.07:06:33.40#ibcon#flushed, iclass 21, count 2 2006.173.07:06:33.40#ibcon#about to write, iclass 21, count 2 2006.173.07:06:33.40#ibcon#wrote, iclass 21, count 2 2006.173.07:06:33.40#ibcon#about to read 3, iclass 21, count 2 2006.173.07:06:33.43#ibcon#read 3, iclass 21, count 2 2006.173.07:06:33.43#ibcon#about to read 4, iclass 21, count 2 2006.173.07:06:33.43#ibcon#read 4, iclass 21, count 2 2006.173.07:06:33.43#ibcon#about to read 5, iclass 21, count 2 2006.173.07:06:33.43#ibcon#read 5, iclass 21, count 2 2006.173.07:06:33.43#ibcon#about to read 6, iclass 21, count 2 2006.173.07:06:33.43#ibcon#read 6, iclass 21, count 2 2006.173.07:06:33.43#ibcon#end of sib2, iclass 21, count 2 2006.173.07:06:33.43#ibcon#*after write, iclass 21, count 2 2006.173.07:06:33.43#ibcon#*before return 0, iclass 21, count 2 2006.173.07:06:33.43#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.07:06:33.43#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.07:06:33.43#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.07:06:33.43#ibcon#ireg 7 cls_cnt 0 2006.173.07:06:33.43#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.07:06:33.55#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.07:06:33.55#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.07:06:33.55#ibcon#enter wrdev, iclass 21, count 0 2006.173.07:06:33.55#ibcon#first serial, iclass 21, count 0 2006.173.07:06:33.55#ibcon#enter sib2, iclass 21, count 0 2006.173.07:06:33.55#ibcon#flushed, iclass 21, count 0 2006.173.07:06:33.55#ibcon#about to write, iclass 21, count 0 2006.173.07:06:33.55#ibcon#wrote, iclass 21, count 0 2006.173.07:06:33.55#ibcon#about to read 3, iclass 21, count 0 2006.173.07:06:33.57#ibcon#read 3, iclass 21, count 0 2006.173.07:06:33.57#ibcon#about to read 4, iclass 21, count 0 2006.173.07:06:33.57#ibcon#read 4, iclass 21, count 0 2006.173.07:06:33.57#ibcon#about to read 5, iclass 21, count 0 2006.173.07:06:33.57#ibcon#read 5, iclass 21, count 0 2006.173.07:06:33.57#ibcon#about to read 6, iclass 21, count 0 2006.173.07:06:33.57#ibcon#read 6, iclass 21, count 0 2006.173.07:06:33.57#ibcon#end of sib2, iclass 21, count 0 2006.173.07:06:33.57#ibcon#*mode == 0, iclass 21, count 0 2006.173.07:06:33.57#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.07:06:33.57#ibcon#[25=USB\r\n] 2006.173.07:06:33.57#ibcon#*before write, iclass 21, count 0 2006.173.07:06:33.57#ibcon#enter sib2, iclass 21, count 0 2006.173.07:06:33.57#ibcon#flushed, iclass 21, count 0 2006.173.07:06:33.57#ibcon#about to write, iclass 21, count 0 2006.173.07:06:33.57#ibcon#wrote, iclass 21, count 0 2006.173.07:06:33.57#ibcon#about to read 3, iclass 21, count 0 2006.173.07:06:33.60#ibcon#read 3, iclass 21, count 0 2006.173.07:06:33.60#ibcon#about to read 4, iclass 21, count 0 2006.173.07:06:33.60#ibcon#read 4, iclass 21, count 0 2006.173.07:06:33.60#ibcon#about to read 5, iclass 21, count 0 2006.173.07:06:33.60#ibcon#read 5, iclass 21, count 0 2006.173.07:06:33.60#ibcon#about to read 6, iclass 21, count 0 2006.173.07:06:33.60#ibcon#read 6, iclass 21, count 0 2006.173.07:06:33.60#ibcon#end of sib2, iclass 21, count 0 2006.173.07:06:33.60#ibcon#*after write, iclass 21, count 0 2006.173.07:06:33.60#ibcon#*before return 0, iclass 21, count 0 2006.173.07:06:33.60#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.07:06:33.60#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.07:06:33.60#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.07:06:33.60#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.07:06:33.60$vck44/valo=8,884.99 2006.173.07:06:33.60#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.07:06:33.60#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.07:06:33.60#ibcon#ireg 17 cls_cnt 0 2006.173.07:06:33.60#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.07:06:33.60#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.07:06:33.60#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.07:06:33.60#ibcon#enter wrdev, iclass 23, count 0 2006.173.07:06:33.60#ibcon#first serial, iclass 23, count 0 2006.173.07:06:33.60#ibcon#enter sib2, iclass 23, count 0 2006.173.07:06:33.60#ibcon#flushed, iclass 23, count 0 2006.173.07:06:33.60#ibcon#about to write, iclass 23, count 0 2006.173.07:06:33.60#ibcon#wrote, iclass 23, count 0 2006.173.07:06:33.60#ibcon#about to read 3, iclass 23, count 0 2006.173.07:06:33.62#ibcon#read 3, iclass 23, count 0 2006.173.07:06:33.62#ibcon#about to read 4, iclass 23, count 0 2006.173.07:06:33.62#ibcon#read 4, iclass 23, count 0 2006.173.07:06:33.62#ibcon#about to read 5, iclass 23, count 0 2006.173.07:06:33.62#ibcon#read 5, iclass 23, count 0 2006.173.07:06:33.62#ibcon#about to read 6, iclass 23, count 0 2006.173.07:06:33.62#ibcon#read 6, iclass 23, count 0 2006.173.07:06:33.62#ibcon#end of sib2, iclass 23, count 0 2006.173.07:06:33.62#ibcon#*mode == 0, iclass 23, count 0 2006.173.07:06:33.62#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.07:06:33.62#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.07:06:33.62#ibcon#*before write, iclass 23, count 0 2006.173.07:06:33.62#ibcon#enter sib2, iclass 23, count 0 2006.173.07:06:33.62#ibcon#flushed, iclass 23, count 0 2006.173.07:06:33.62#ibcon#about to write, iclass 23, count 0 2006.173.07:06:33.62#ibcon#wrote, iclass 23, count 0 2006.173.07:06:33.62#ibcon#about to read 3, iclass 23, count 0 2006.173.07:06:33.66#ibcon#read 3, iclass 23, count 0 2006.173.07:06:33.66#ibcon#about to read 4, iclass 23, count 0 2006.173.07:06:33.66#ibcon#read 4, iclass 23, count 0 2006.173.07:06:33.66#ibcon#about to read 5, iclass 23, count 0 2006.173.07:06:33.66#ibcon#read 5, iclass 23, count 0 2006.173.07:06:33.66#ibcon#about to read 6, iclass 23, count 0 2006.173.07:06:33.66#ibcon#read 6, iclass 23, count 0 2006.173.07:06:33.66#ibcon#end of sib2, iclass 23, count 0 2006.173.07:06:33.66#ibcon#*after write, iclass 23, count 0 2006.173.07:06:33.66#ibcon#*before return 0, iclass 23, count 0 2006.173.07:06:33.66#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.07:06:33.66#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.07:06:33.66#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.07:06:33.66#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.07:06:33.66$vck44/va=8,4 2006.173.07:06:33.66#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.07:06:33.66#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.07:06:33.66#ibcon#ireg 11 cls_cnt 2 2006.173.07:06:33.66#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.07:06:33.72#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.07:06:33.72#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.07:06:33.72#ibcon#enter wrdev, iclass 25, count 2 2006.173.07:06:33.72#ibcon#first serial, iclass 25, count 2 2006.173.07:06:33.72#ibcon#enter sib2, iclass 25, count 2 2006.173.07:06:33.72#ibcon#flushed, iclass 25, count 2 2006.173.07:06:33.72#ibcon#about to write, iclass 25, count 2 2006.173.07:06:33.72#ibcon#wrote, iclass 25, count 2 2006.173.07:06:33.72#ibcon#about to read 3, iclass 25, count 2 2006.173.07:06:33.74#ibcon#read 3, iclass 25, count 2 2006.173.07:06:33.74#ibcon#about to read 4, iclass 25, count 2 2006.173.07:06:33.74#ibcon#read 4, iclass 25, count 2 2006.173.07:06:33.74#ibcon#about to read 5, iclass 25, count 2 2006.173.07:06:33.74#ibcon#read 5, iclass 25, count 2 2006.173.07:06:33.74#ibcon#about to read 6, iclass 25, count 2 2006.173.07:06:33.74#ibcon#read 6, iclass 25, count 2 2006.173.07:06:33.74#ibcon#end of sib2, iclass 25, count 2 2006.173.07:06:33.74#ibcon#*mode == 0, iclass 25, count 2 2006.173.07:06:33.74#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.07:06:33.74#ibcon#[25=AT08-04\r\n] 2006.173.07:06:33.74#ibcon#*before write, iclass 25, count 2 2006.173.07:06:33.74#ibcon#enter sib2, iclass 25, count 2 2006.173.07:06:33.74#ibcon#flushed, iclass 25, count 2 2006.173.07:06:33.74#ibcon#about to write, iclass 25, count 2 2006.173.07:06:33.74#ibcon#wrote, iclass 25, count 2 2006.173.07:06:33.74#ibcon#about to read 3, iclass 25, count 2 2006.173.07:06:33.77#ibcon#read 3, iclass 25, count 2 2006.173.07:06:33.77#ibcon#about to read 4, iclass 25, count 2 2006.173.07:06:33.77#ibcon#read 4, iclass 25, count 2 2006.173.07:06:33.77#ibcon#about to read 5, iclass 25, count 2 2006.173.07:06:33.77#ibcon#read 5, iclass 25, count 2 2006.173.07:06:33.77#ibcon#about to read 6, iclass 25, count 2 2006.173.07:06:33.77#ibcon#read 6, iclass 25, count 2 2006.173.07:06:33.77#ibcon#end of sib2, iclass 25, count 2 2006.173.07:06:33.77#ibcon#*after write, iclass 25, count 2 2006.173.07:06:33.77#ibcon#*before return 0, iclass 25, count 2 2006.173.07:06:33.77#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.07:06:33.77#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.07:06:33.77#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.07:06:33.77#ibcon#ireg 7 cls_cnt 0 2006.173.07:06:33.77#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.07:06:33.89#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.07:06:33.89#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.07:06:33.89#ibcon#enter wrdev, iclass 25, count 0 2006.173.07:06:33.89#ibcon#first serial, iclass 25, count 0 2006.173.07:06:33.89#ibcon#enter sib2, iclass 25, count 0 2006.173.07:06:33.89#ibcon#flushed, iclass 25, count 0 2006.173.07:06:33.89#ibcon#about to write, iclass 25, count 0 2006.173.07:06:33.89#ibcon#wrote, iclass 25, count 0 2006.173.07:06:33.89#ibcon#about to read 3, iclass 25, count 0 2006.173.07:06:33.91#ibcon#read 3, iclass 25, count 0 2006.173.07:06:33.91#ibcon#about to read 4, iclass 25, count 0 2006.173.07:06:33.91#ibcon#read 4, iclass 25, count 0 2006.173.07:06:33.91#ibcon#about to read 5, iclass 25, count 0 2006.173.07:06:33.91#ibcon#read 5, iclass 25, count 0 2006.173.07:06:33.91#ibcon#about to read 6, iclass 25, count 0 2006.173.07:06:33.91#ibcon#read 6, iclass 25, count 0 2006.173.07:06:33.91#ibcon#end of sib2, iclass 25, count 0 2006.173.07:06:33.91#ibcon#*mode == 0, iclass 25, count 0 2006.173.07:06:33.91#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.07:06:33.91#ibcon#[25=USB\r\n] 2006.173.07:06:33.91#ibcon#*before write, iclass 25, count 0 2006.173.07:06:33.91#ibcon#enter sib2, iclass 25, count 0 2006.173.07:06:33.91#ibcon#flushed, iclass 25, count 0 2006.173.07:06:33.91#ibcon#about to write, iclass 25, count 0 2006.173.07:06:33.91#ibcon#wrote, iclass 25, count 0 2006.173.07:06:33.91#ibcon#about to read 3, iclass 25, count 0 2006.173.07:06:33.94#ibcon#read 3, iclass 25, count 0 2006.173.07:06:33.94#ibcon#about to read 4, iclass 25, count 0 2006.173.07:06:33.94#ibcon#read 4, iclass 25, count 0 2006.173.07:06:33.94#ibcon#about to read 5, iclass 25, count 0 2006.173.07:06:33.94#ibcon#read 5, iclass 25, count 0 2006.173.07:06:33.94#ibcon#about to read 6, iclass 25, count 0 2006.173.07:06:33.94#ibcon#read 6, iclass 25, count 0 2006.173.07:06:33.94#ibcon#end of sib2, iclass 25, count 0 2006.173.07:06:33.94#ibcon#*after write, iclass 25, count 0 2006.173.07:06:33.94#ibcon#*before return 0, iclass 25, count 0 2006.173.07:06:33.94#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.07:06:33.94#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.07:06:33.94#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.07:06:33.94#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.07:06:33.94$vck44/vblo=1,629.99 2006.173.07:06:33.94#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.07:06:33.94#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.07:06:33.94#ibcon#ireg 17 cls_cnt 0 2006.173.07:06:33.94#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.07:06:33.94#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.07:06:33.94#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.07:06:33.94#ibcon#enter wrdev, iclass 27, count 0 2006.173.07:06:33.94#ibcon#first serial, iclass 27, count 0 2006.173.07:06:33.94#ibcon#enter sib2, iclass 27, count 0 2006.173.07:06:33.94#ibcon#flushed, iclass 27, count 0 2006.173.07:06:33.94#ibcon#about to write, iclass 27, count 0 2006.173.07:06:33.94#ibcon#wrote, iclass 27, count 0 2006.173.07:06:33.94#ibcon#about to read 3, iclass 27, count 0 2006.173.07:06:33.96#ibcon#read 3, iclass 27, count 0 2006.173.07:06:33.96#ibcon#about to read 4, iclass 27, count 0 2006.173.07:06:33.96#ibcon#read 4, iclass 27, count 0 2006.173.07:06:33.96#ibcon#about to read 5, iclass 27, count 0 2006.173.07:06:33.96#ibcon#read 5, iclass 27, count 0 2006.173.07:06:33.96#ibcon#about to read 6, iclass 27, count 0 2006.173.07:06:33.96#ibcon#read 6, iclass 27, count 0 2006.173.07:06:33.96#ibcon#end of sib2, iclass 27, count 0 2006.173.07:06:33.96#ibcon#*mode == 0, iclass 27, count 0 2006.173.07:06:33.96#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.07:06:33.96#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.07:06:33.96#ibcon#*before write, iclass 27, count 0 2006.173.07:06:33.96#ibcon#enter sib2, iclass 27, count 0 2006.173.07:06:33.96#ibcon#flushed, iclass 27, count 0 2006.173.07:06:33.96#ibcon#about to write, iclass 27, count 0 2006.173.07:06:33.96#ibcon#wrote, iclass 27, count 0 2006.173.07:06:33.96#ibcon#about to read 3, iclass 27, count 0 2006.173.07:06:34.00#ibcon#read 3, iclass 27, count 0 2006.173.07:06:34.00#ibcon#about to read 4, iclass 27, count 0 2006.173.07:06:34.00#ibcon#read 4, iclass 27, count 0 2006.173.07:06:34.00#ibcon#about to read 5, iclass 27, count 0 2006.173.07:06:34.00#ibcon#read 5, iclass 27, count 0 2006.173.07:06:34.00#ibcon#about to read 6, iclass 27, count 0 2006.173.07:06:34.00#ibcon#read 6, iclass 27, count 0 2006.173.07:06:34.00#ibcon#end of sib2, iclass 27, count 0 2006.173.07:06:34.00#ibcon#*after write, iclass 27, count 0 2006.173.07:06:34.00#ibcon#*before return 0, iclass 27, count 0 2006.173.07:06:34.00#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.07:06:34.00#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.07:06:34.00#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.07:06:34.00#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.07:06:34.00$vck44/vb=1,4 2006.173.07:06:34.00#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.07:06:34.00#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.07:06:34.00#ibcon#ireg 11 cls_cnt 2 2006.173.07:06:34.00#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.07:06:34.00#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.07:06:34.00#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.07:06:34.00#ibcon#enter wrdev, iclass 29, count 2 2006.173.07:06:34.00#ibcon#first serial, iclass 29, count 2 2006.173.07:06:34.00#ibcon#enter sib2, iclass 29, count 2 2006.173.07:06:34.00#ibcon#flushed, iclass 29, count 2 2006.173.07:06:34.00#ibcon#about to write, iclass 29, count 2 2006.173.07:06:34.00#ibcon#wrote, iclass 29, count 2 2006.173.07:06:34.00#ibcon#about to read 3, iclass 29, count 2 2006.173.07:06:34.02#ibcon#read 3, iclass 29, count 2 2006.173.07:06:34.02#ibcon#about to read 4, iclass 29, count 2 2006.173.07:06:34.02#ibcon#read 4, iclass 29, count 2 2006.173.07:06:34.02#ibcon#about to read 5, iclass 29, count 2 2006.173.07:06:34.02#ibcon#read 5, iclass 29, count 2 2006.173.07:06:34.02#ibcon#about to read 6, iclass 29, count 2 2006.173.07:06:34.02#ibcon#read 6, iclass 29, count 2 2006.173.07:06:34.02#ibcon#end of sib2, iclass 29, count 2 2006.173.07:06:34.02#ibcon#*mode == 0, iclass 29, count 2 2006.173.07:06:34.02#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.07:06:34.02#ibcon#[27=AT01-04\r\n] 2006.173.07:06:34.02#ibcon#*before write, iclass 29, count 2 2006.173.07:06:34.02#ibcon#enter sib2, iclass 29, count 2 2006.173.07:06:34.02#ibcon#flushed, iclass 29, count 2 2006.173.07:06:34.02#ibcon#about to write, iclass 29, count 2 2006.173.07:06:34.02#ibcon#wrote, iclass 29, count 2 2006.173.07:06:34.02#ibcon#about to read 3, iclass 29, count 2 2006.173.07:06:34.05#ibcon#read 3, iclass 29, count 2 2006.173.07:06:34.05#ibcon#about to read 4, iclass 29, count 2 2006.173.07:06:34.05#ibcon#read 4, iclass 29, count 2 2006.173.07:06:34.05#ibcon#about to read 5, iclass 29, count 2 2006.173.07:06:34.05#ibcon#read 5, iclass 29, count 2 2006.173.07:06:34.05#ibcon#about to read 6, iclass 29, count 2 2006.173.07:06:34.05#ibcon#read 6, iclass 29, count 2 2006.173.07:06:34.05#ibcon#end of sib2, iclass 29, count 2 2006.173.07:06:34.05#ibcon#*after write, iclass 29, count 2 2006.173.07:06:34.05#ibcon#*before return 0, iclass 29, count 2 2006.173.07:06:34.05#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.07:06:34.05#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.07:06:34.05#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.07:06:34.05#ibcon#ireg 7 cls_cnt 0 2006.173.07:06:34.05#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.07:06:34.17#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.07:06:34.17#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.07:06:34.17#ibcon#enter wrdev, iclass 29, count 0 2006.173.07:06:34.17#ibcon#first serial, iclass 29, count 0 2006.173.07:06:34.17#ibcon#enter sib2, iclass 29, count 0 2006.173.07:06:34.17#ibcon#flushed, iclass 29, count 0 2006.173.07:06:34.17#ibcon#about to write, iclass 29, count 0 2006.173.07:06:34.17#ibcon#wrote, iclass 29, count 0 2006.173.07:06:34.17#ibcon#about to read 3, iclass 29, count 0 2006.173.07:06:34.19#ibcon#read 3, iclass 29, count 0 2006.173.07:06:34.19#ibcon#about to read 4, iclass 29, count 0 2006.173.07:06:34.19#ibcon#read 4, iclass 29, count 0 2006.173.07:06:34.19#ibcon#about to read 5, iclass 29, count 0 2006.173.07:06:34.19#ibcon#read 5, iclass 29, count 0 2006.173.07:06:34.19#ibcon#about to read 6, iclass 29, count 0 2006.173.07:06:34.19#ibcon#read 6, iclass 29, count 0 2006.173.07:06:34.19#ibcon#end of sib2, iclass 29, count 0 2006.173.07:06:34.19#ibcon#*mode == 0, iclass 29, count 0 2006.173.07:06:34.19#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.07:06:34.19#ibcon#[27=USB\r\n] 2006.173.07:06:34.19#ibcon#*before write, iclass 29, count 0 2006.173.07:06:34.19#ibcon#enter sib2, iclass 29, count 0 2006.173.07:06:34.19#ibcon#flushed, iclass 29, count 0 2006.173.07:06:34.19#ibcon#about to write, iclass 29, count 0 2006.173.07:06:34.19#ibcon#wrote, iclass 29, count 0 2006.173.07:06:34.19#ibcon#about to read 3, iclass 29, count 0 2006.173.07:06:34.22#ibcon#read 3, iclass 29, count 0 2006.173.07:06:34.22#ibcon#about to read 4, iclass 29, count 0 2006.173.07:06:34.22#ibcon#read 4, iclass 29, count 0 2006.173.07:06:34.22#ibcon#about to read 5, iclass 29, count 0 2006.173.07:06:34.22#ibcon#read 5, iclass 29, count 0 2006.173.07:06:34.22#ibcon#about to read 6, iclass 29, count 0 2006.173.07:06:34.22#ibcon#read 6, iclass 29, count 0 2006.173.07:06:34.22#ibcon#end of sib2, iclass 29, count 0 2006.173.07:06:34.22#ibcon#*after write, iclass 29, count 0 2006.173.07:06:34.22#ibcon#*before return 0, iclass 29, count 0 2006.173.07:06:34.22#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.07:06:34.22#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.07:06:34.22#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.07:06:34.22#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.07:06:34.22$vck44/vblo=2,634.99 2006.173.07:06:34.22#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.07:06:34.22#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.07:06:34.22#ibcon#ireg 17 cls_cnt 0 2006.173.07:06:34.22#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.07:06:34.22#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.07:06:34.22#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.07:06:34.22#ibcon#enter wrdev, iclass 31, count 0 2006.173.07:06:34.22#ibcon#first serial, iclass 31, count 0 2006.173.07:06:34.22#ibcon#enter sib2, iclass 31, count 0 2006.173.07:06:34.22#ibcon#flushed, iclass 31, count 0 2006.173.07:06:34.22#ibcon#about to write, iclass 31, count 0 2006.173.07:06:34.22#ibcon#wrote, iclass 31, count 0 2006.173.07:06:34.22#ibcon#about to read 3, iclass 31, count 0 2006.173.07:06:34.24#ibcon#read 3, iclass 31, count 0 2006.173.07:06:34.24#ibcon#about to read 4, iclass 31, count 0 2006.173.07:06:34.24#ibcon#read 4, iclass 31, count 0 2006.173.07:06:34.24#ibcon#about to read 5, iclass 31, count 0 2006.173.07:06:34.24#ibcon#read 5, iclass 31, count 0 2006.173.07:06:34.24#ibcon#about to read 6, iclass 31, count 0 2006.173.07:06:34.24#ibcon#read 6, iclass 31, count 0 2006.173.07:06:34.24#ibcon#end of sib2, iclass 31, count 0 2006.173.07:06:34.24#ibcon#*mode == 0, iclass 31, count 0 2006.173.07:06:34.24#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.07:06:34.24#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.07:06:34.24#ibcon#*before write, iclass 31, count 0 2006.173.07:06:34.24#ibcon#enter sib2, iclass 31, count 0 2006.173.07:06:34.24#ibcon#flushed, iclass 31, count 0 2006.173.07:06:34.24#ibcon#about to write, iclass 31, count 0 2006.173.07:06:34.24#ibcon#wrote, iclass 31, count 0 2006.173.07:06:34.24#ibcon#about to read 3, iclass 31, count 0 2006.173.07:06:34.28#ibcon#read 3, iclass 31, count 0 2006.173.07:06:34.28#ibcon#about to read 4, iclass 31, count 0 2006.173.07:06:34.28#ibcon#read 4, iclass 31, count 0 2006.173.07:06:34.28#ibcon#about to read 5, iclass 31, count 0 2006.173.07:06:34.28#ibcon#read 5, iclass 31, count 0 2006.173.07:06:34.28#ibcon#about to read 6, iclass 31, count 0 2006.173.07:06:34.28#ibcon#read 6, iclass 31, count 0 2006.173.07:06:34.28#ibcon#end of sib2, iclass 31, count 0 2006.173.07:06:34.28#ibcon#*after write, iclass 31, count 0 2006.173.07:06:34.28#ibcon#*before return 0, iclass 31, count 0 2006.173.07:06:34.28#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.07:06:34.28#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.07:06:34.28#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.07:06:34.28#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.07:06:34.28$vck44/vb=2,4 2006.173.07:06:34.28#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.173.07:06:34.28#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.173.07:06:34.28#ibcon#ireg 11 cls_cnt 2 2006.173.07:06:34.28#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.07:06:34.34#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.07:06:34.34#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.07:06:34.34#ibcon#enter wrdev, iclass 33, count 2 2006.173.07:06:34.34#ibcon#first serial, iclass 33, count 2 2006.173.07:06:34.34#ibcon#enter sib2, iclass 33, count 2 2006.173.07:06:34.34#ibcon#flushed, iclass 33, count 2 2006.173.07:06:34.34#ibcon#about to write, iclass 33, count 2 2006.173.07:06:34.34#ibcon#wrote, iclass 33, count 2 2006.173.07:06:34.34#ibcon#about to read 3, iclass 33, count 2 2006.173.07:06:34.36#ibcon#read 3, iclass 33, count 2 2006.173.07:06:34.36#ibcon#about to read 4, iclass 33, count 2 2006.173.07:06:34.36#ibcon#read 4, iclass 33, count 2 2006.173.07:06:34.36#ibcon#about to read 5, iclass 33, count 2 2006.173.07:06:34.36#ibcon#read 5, iclass 33, count 2 2006.173.07:06:34.36#ibcon#about to read 6, iclass 33, count 2 2006.173.07:06:34.36#ibcon#read 6, iclass 33, count 2 2006.173.07:06:34.36#ibcon#end of sib2, iclass 33, count 2 2006.173.07:06:34.36#ibcon#*mode == 0, iclass 33, count 2 2006.173.07:06:34.36#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.173.07:06:34.36#ibcon#[27=AT02-04\r\n] 2006.173.07:06:34.36#ibcon#*before write, iclass 33, count 2 2006.173.07:06:34.36#ibcon#enter sib2, iclass 33, count 2 2006.173.07:06:34.36#ibcon#flushed, iclass 33, count 2 2006.173.07:06:34.36#ibcon#about to write, iclass 33, count 2 2006.173.07:06:34.36#ibcon#wrote, iclass 33, count 2 2006.173.07:06:34.36#ibcon#about to read 3, iclass 33, count 2 2006.173.07:06:34.39#ibcon#read 3, iclass 33, count 2 2006.173.07:06:34.39#ibcon#about to read 4, iclass 33, count 2 2006.173.07:06:34.39#ibcon#read 4, iclass 33, count 2 2006.173.07:06:34.39#ibcon#about to read 5, iclass 33, count 2 2006.173.07:06:34.39#ibcon#read 5, iclass 33, count 2 2006.173.07:06:34.39#ibcon#about to read 6, iclass 33, count 2 2006.173.07:06:34.39#ibcon#read 6, iclass 33, count 2 2006.173.07:06:34.39#ibcon#end of sib2, iclass 33, count 2 2006.173.07:06:34.39#ibcon#*after write, iclass 33, count 2 2006.173.07:06:34.39#ibcon#*before return 0, iclass 33, count 2 2006.173.07:06:34.39#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.07:06:34.39#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.173.07:06:34.39#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.173.07:06:34.39#ibcon#ireg 7 cls_cnt 0 2006.173.07:06:34.39#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.07:06:34.51#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.07:06:34.51#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.07:06:34.51#ibcon#enter wrdev, iclass 33, count 0 2006.173.07:06:34.51#ibcon#first serial, iclass 33, count 0 2006.173.07:06:34.51#ibcon#enter sib2, iclass 33, count 0 2006.173.07:06:34.51#ibcon#flushed, iclass 33, count 0 2006.173.07:06:34.51#ibcon#about to write, iclass 33, count 0 2006.173.07:06:34.51#ibcon#wrote, iclass 33, count 0 2006.173.07:06:34.51#ibcon#about to read 3, iclass 33, count 0 2006.173.07:06:34.53#ibcon#read 3, iclass 33, count 0 2006.173.07:06:34.53#ibcon#about to read 4, iclass 33, count 0 2006.173.07:06:34.53#ibcon#read 4, iclass 33, count 0 2006.173.07:06:34.53#ibcon#about to read 5, iclass 33, count 0 2006.173.07:06:34.53#ibcon#read 5, iclass 33, count 0 2006.173.07:06:34.53#ibcon#about to read 6, iclass 33, count 0 2006.173.07:06:34.53#ibcon#read 6, iclass 33, count 0 2006.173.07:06:34.53#ibcon#end of sib2, iclass 33, count 0 2006.173.07:06:34.53#ibcon#*mode == 0, iclass 33, count 0 2006.173.07:06:34.53#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.07:06:34.53#ibcon#[27=USB\r\n] 2006.173.07:06:34.53#ibcon#*before write, iclass 33, count 0 2006.173.07:06:34.53#ibcon#enter sib2, iclass 33, count 0 2006.173.07:06:34.53#ibcon#flushed, iclass 33, count 0 2006.173.07:06:34.53#ibcon#about to write, iclass 33, count 0 2006.173.07:06:34.53#ibcon#wrote, iclass 33, count 0 2006.173.07:06:34.53#ibcon#about to read 3, iclass 33, count 0 2006.173.07:06:34.56#ibcon#read 3, iclass 33, count 0 2006.173.07:06:34.56#ibcon#about to read 4, iclass 33, count 0 2006.173.07:06:34.56#ibcon#read 4, iclass 33, count 0 2006.173.07:06:34.56#ibcon#about to read 5, iclass 33, count 0 2006.173.07:06:34.56#ibcon#read 5, iclass 33, count 0 2006.173.07:06:34.56#ibcon#about to read 6, iclass 33, count 0 2006.173.07:06:34.56#ibcon#read 6, iclass 33, count 0 2006.173.07:06:34.56#ibcon#end of sib2, iclass 33, count 0 2006.173.07:06:34.56#ibcon#*after write, iclass 33, count 0 2006.173.07:06:34.56#ibcon#*before return 0, iclass 33, count 0 2006.173.07:06:34.56#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.07:06:34.56#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.173.07:06:34.56#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.07:06:34.56#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.07:06:34.56$vck44/vblo=3,649.99 2006.173.07:06:34.56#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.07:06:34.56#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.07:06:34.56#ibcon#ireg 17 cls_cnt 0 2006.173.07:06:34.56#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.07:06:34.56#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.07:06:34.56#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.07:06:34.56#ibcon#enter wrdev, iclass 35, count 0 2006.173.07:06:34.56#ibcon#first serial, iclass 35, count 0 2006.173.07:06:34.56#ibcon#enter sib2, iclass 35, count 0 2006.173.07:06:34.56#ibcon#flushed, iclass 35, count 0 2006.173.07:06:34.56#ibcon#about to write, iclass 35, count 0 2006.173.07:06:34.56#ibcon#wrote, iclass 35, count 0 2006.173.07:06:34.56#ibcon#about to read 3, iclass 35, count 0 2006.173.07:06:34.58#ibcon#read 3, iclass 35, count 0 2006.173.07:06:34.58#ibcon#about to read 4, iclass 35, count 0 2006.173.07:06:34.58#ibcon#read 4, iclass 35, count 0 2006.173.07:06:34.58#ibcon#about to read 5, iclass 35, count 0 2006.173.07:06:34.58#ibcon#read 5, iclass 35, count 0 2006.173.07:06:34.58#ibcon#about to read 6, iclass 35, count 0 2006.173.07:06:34.58#ibcon#read 6, iclass 35, count 0 2006.173.07:06:34.58#ibcon#end of sib2, iclass 35, count 0 2006.173.07:06:34.58#ibcon#*mode == 0, iclass 35, count 0 2006.173.07:06:34.58#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.07:06:34.58#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.07:06:34.58#ibcon#*before write, iclass 35, count 0 2006.173.07:06:34.58#ibcon#enter sib2, iclass 35, count 0 2006.173.07:06:34.58#ibcon#flushed, iclass 35, count 0 2006.173.07:06:34.58#ibcon#about to write, iclass 35, count 0 2006.173.07:06:34.58#ibcon#wrote, iclass 35, count 0 2006.173.07:06:34.58#ibcon#about to read 3, iclass 35, count 0 2006.173.07:06:34.62#ibcon#read 3, iclass 35, count 0 2006.173.07:06:34.62#ibcon#about to read 4, iclass 35, count 0 2006.173.07:06:34.62#ibcon#read 4, iclass 35, count 0 2006.173.07:06:34.62#ibcon#about to read 5, iclass 35, count 0 2006.173.07:06:34.62#ibcon#read 5, iclass 35, count 0 2006.173.07:06:34.62#ibcon#about to read 6, iclass 35, count 0 2006.173.07:06:34.62#ibcon#read 6, iclass 35, count 0 2006.173.07:06:34.62#ibcon#end of sib2, iclass 35, count 0 2006.173.07:06:34.62#ibcon#*after write, iclass 35, count 0 2006.173.07:06:34.62#ibcon#*before return 0, iclass 35, count 0 2006.173.07:06:34.62#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.07:06:34.62#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.07:06:34.62#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.07:06:34.62#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.07:06:34.62$vck44/vb=3,4 2006.173.07:06:34.62#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.173.07:06:34.62#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.173.07:06:34.62#ibcon#ireg 11 cls_cnt 2 2006.173.07:06:34.62#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.07:06:34.68#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.07:06:34.68#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.07:06:34.68#ibcon#enter wrdev, iclass 37, count 2 2006.173.07:06:34.68#ibcon#first serial, iclass 37, count 2 2006.173.07:06:34.68#ibcon#enter sib2, iclass 37, count 2 2006.173.07:06:34.68#ibcon#flushed, iclass 37, count 2 2006.173.07:06:34.68#ibcon#about to write, iclass 37, count 2 2006.173.07:06:34.68#ibcon#wrote, iclass 37, count 2 2006.173.07:06:34.68#ibcon#about to read 3, iclass 37, count 2 2006.173.07:06:34.70#ibcon#read 3, iclass 37, count 2 2006.173.07:06:34.70#ibcon#about to read 4, iclass 37, count 2 2006.173.07:06:34.70#ibcon#read 4, iclass 37, count 2 2006.173.07:06:34.70#ibcon#about to read 5, iclass 37, count 2 2006.173.07:06:34.70#ibcon#read 5, iclass 37, count 2 2006.173.07:06:34.70#ibcon#about to read 6, iclass 37, count 2 2006.173.07:06:34.70#ibcon#read 6, iclass 37, count 2 2006.173.07:06:34.70#ibcon#end of sib2, iclass 37, count 2 2006.173.07:06:34.70#ibcon#*mode == 0, iclass 37, count 2 2006.173.07:06:34.70#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.173.07:06:34.70#ibcon#[27=AT03-04\r\n] 2006.173.07:06:34.70#ibcon#*before write, iclass 37, count 2 2006.173.07:06:34.70#ibcon#enter sib2, iclass 37, count 2 2006.173.07:06:34.70#ibcon#flushed, iclass 37, count 2 2006.173.07:06:34.70#ibcon#about to write, iclass 37, count 2 2006.173.07:06:34.70#ibcon#wrote, iclass 37, count 2 2006.173.07:06:34.70#ibcon#about to read 3, iclass 37, count 2 2006.173.07:06:34.73#ibcon#read 3, iclass 37, count 2 2006.173.07:06:34.73#ibcon#about to read 4, iclass 37, count 2 2006.173.07:06:34.73#ibcon#read 4, iclass 37, count 2 2006.173.07:06:34.73#ibcon#about to read 5, iclass 37, count 2 2006.173.07:06:34.73#ibcon#read 5, iclass 37, count 2 2006.173.07:06:34.73#ibcon#about to read 6, iclass 37, count 2 2006.173.07:06:34.73#ibcon#read 6, iclass 37, count 2 2006.173.07:06:34.73#ibcon#end of sib2, iclass 37, count 2 2006.173.07:06:34.73#ibcon#*after write, iclass 37, count 2 2006.173.07:06:34.73#ibcon#*before return 0, iclass 37, count 2 2006.173.07:06:34.73#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.07:06:34.73#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.173.07:06:34.73#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.173.07:06:34.73#ibcon#ireg 7 cls_cnt 0 2006.173.07:06:34.73#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.07:06:34.85#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.07:06:34.85#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.07:06:34.85#ibcon#enter wrdev, iclass 37, count 0 2006.173.07:06:34.85#ibcon#first serial, iclass 37, count 0 2006.173.07:06:34.85#ibcon#enter sib2, iclass 37, count 0 2006.173.07:06:34.85#ibcon#flushed, iclass 37, count 0 2006.173.07:06:34.85#ibcon#about to write, iclass 37, count 0 2006.173.07:06:34.85#ibcon#wrote, iclass 37, count 0 2006.173.07:06:34.85#ibcon#about to read 3, iclass 37, count 0 2006.173.07:06:34.87#ibcon#read 3, iclass 37, count 0 2006.173.07:06:34.87#ibcon#about to read 4, iclass 37, count 0 2006.173.07:06:34.87#ibcon#read 4, iclass 37, count 0 2006.173.07:06:34.87#ibcon#about to read 5, iclass 37, count 0 2006.173.07:06:34.87#ibcon#read 5, iclass 37, count 0 2006.173.07:06:34.87#ibcon#about to read 6, iclass 37, count 0 2006.173.07:06:34.87#ibcon#read 6, iclass 37, count 0 2006.173.07:06:34.87#ibcon#end of sib2, iclass 37, count 0 2006.173.07:06:34.87#ibcon#*mode == 0, iclass 37, count 0 2006.173.07:06:34.87#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.07:06:34.87#ibcon#[27=USB\r\n] 2006.173.07:06:34.87#ibcon#*before write, iclass 37, count 0 2006.173.07:06:34.87#ibcon#enter sib2, iclass 37, count 0 2006.173.07:06:34.87#ibcon#flushed, iclass 37, count 0 2006.173.07:06:34.87#ibcon#about to write, iclass 37, count 0 2006.173.07:06:34.87#ibcon#wrote, iclass 37, count 0 2006.173.07:06:34.87#ibcon#about to read 3, iclass 37, count 0 2006.173.07:06:34.90#ibcon#read 3, iclass 37, count 0 2006.173.07:06:34.90#ibcon#about to read 4, iclass 37, count 0 2006.173.07:06:34.90#ibcon#read 4, iclass 37, count 0 2006.173.07:06:34.90#ibcon#about to read 5, iclass 37, count 0 2006.173.07:06:34.90#ibcon#read 5, iclass 37, count 0 2006.173.07:06:34.90#ibcon#about to read 6, iclass 37, count 0 2006.173.07:06:34.90#ibcon#read 6, iclass 37, count 0 2006.173.07:06:34.90#ibcon#end of sib2, iclass 37, count 0 2006.173.07:06:34.90#ibcon#*after write, iclass 37, count 0 2006.173.07:06:34.90#ibcon#*before return 0, iclass 37, count 0 2006.173.07:06:34.90#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.07:06:34.90#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.173.07:06:34.90#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.07:06:34.90#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.07:06:34.90$vck44/vblo=4,679.99 2006.173.07:06:34.90#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.07:06:34.90#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.07:06:34.90#ibcon#ireg 17 cls_cnt 0 2006.173.07:06:34.90#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.07:06:34.90#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.07:06:34.90#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.07:06:34.90#ibcon#enter wrdev, iclass 39, count 0 2006.173.07:06:34.90#ibcon#first serial, iclass 39, count 0 2006.173.07:06:34.90#ibcon#enter sib2, iclass 39, count 0 2006.173.07:06:34.90#ibcon#flushed, iclass 39, count 0 2006.173.07:06:34.90#ibcon#about to write, iclass 39, count 0 2006.173.07:06:34.90#ibcon#wrote, iclass 39, count 0 2006.173.07:06:34.90#ibcon#about to read 3, iclass 39, count 0 2006.173.07:06:34.92#ibcon#read 3, iclass 39, count 0 2006.173.07:06:34.92#ibcon#about to read 4, iclass 39, count 0 2006.173.07:06:34.92#ibcon#read 4, iclass 39, count 0 2006.173.07:06:34.92#ibcon#about to read 5, iclass 39, count 0 2006.173.07:06:34.92#ibcon#read 5, iclass 39, count 0 2006.173.07:06:34.92#ibcon#about to read 6, iclass 39, count 0 2006.173.07:06:34.92#ibcon#read 6, iclass 39, count 0 2006.173.07:06:34.92#ibcon#end of sib2, iclass 39, count 0 2006.173.07:06:34.92#ibcon#*mode == 0, iclass 39, count 0 2006.173.07:06:34.92#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.07:06:34.92#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.07:06:34.92#ibcon#*before write, iclass 39, count 0 2006.173.07:06:34.92#ibcon#enter sib2, iclass 39, count 0 2006.173.07:06:34.92#ibcon#flushed, iclass 39, count 0 2006.173.07:06:34.92#ibcon#about to write, iclass 39, count 0 2006.173.07:06:34.92#ibcon#wrote, iclass 39, count 0 2006.173.07:06:34.92#ibcon#about to read 3, iclass 39, count 0 2006.173.07:06:34.96#ibcon#read 3, iclass 39, count 0 2006.173.07:06:34.96#ibcon#about to read 4, iclass 39, count 0 2006.173.07:06:34.96#ibcon#read 4, iclass 39, count 0 2006.173.07:06:34.96#ibcon#about to read 5, iclass 39, count 0 2006.173.07:06:34.96#ibcon#read 5, iclass 39, count 0 2006.173.07:06:34.96#ibcon#about to read 6, iclass 39, count 0 2006.173.07:06:34.96#ibcon#read 6, iclass 39, count 0 2006.173.07:06:34.96#ibcon#end of sib2, iclass 39, count 0 2006.173.07:06:34.96#ibcon#*after write, iclass 39, count 0 2006.173.07:06:34.96#ibcon#*before return 0, iclass 39, count 0 2006.173.07:06:34.96#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.07:06:34.96#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.07:06:34.96#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.07:06:34.96#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.07:06:34.96$vck44/vb=4,4 2006.173.07:06:34.96#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.07:06:34.96#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.07:06:34.96#ibcon#ireg 11 cls_cnt 2 2006.173.07:06:34.96#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.07:06:35.02#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.07:06:35.02#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.07:06:35.02#ibcon#enter wrdev, iclass 3, count 2 2006.173.07:06:35.02#ibcon#first serial, iclass 3, count 2 2006.173.07:06:35.02#ibcon#enter sib2, iclass 3, count 2 2006.173.07:06:35.02#ibcon#flushed, iclass 3, count 2 2006.173.07:06:35.02#ibcon#about to write, iclass 3, count 2 2006.173.07:06:35.02#ibcon#wrote, iclass 3, count 2 2006.173.07:06:35.02#ibcon#about to read 3, iclass 3, count 2 2006.173.07:06:35.04#ibcon#read 3, iclass 3, count 2 2006.173.07:06:35.04#ibcon#about to read 4, iclass 3, count 2 2006.173.07:06:35.04#ibcon#read 4, iclass 3, count 2 2006.173.07:06:35.04#ibcon#about to read 5, iclass 3, count 2 2006.173.07:06:35.04#ibcon#read 5, iclass 3, count 2 2006.173.07:06:35.04#ibcon#about to read 6, iclass 3, count 2 2006.173.07:06:35.04#ibcon#read 6, iclass 3, count 2 2006.173.07:06:35.04#ibcon#end of sib2, iclass 3, count 2 2006.173.07:06:35.04#ibcon#*mode == 0, iclass 3, count 2 2006.173.07:06:35.04#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.07:06:35.04#ibcon#[27=AT04-04\r\n] 2006.173.07:06:35.04#ibcon#*before write, iclass 3, count 2 2006.173.07:06:35.04#ibcon#enter sib2, iclass 3, count 2 2006.173.07:06:35.04#ibcon#flushed, iclass 3, count 2 2006.173.07:06:35.04#ibcon#about to write, iclass 3, count 2 2006.173.07:06:35.04#ibcon#wrote, iclass 3, count 2 2006.173.07:06:35.04#ibcon#about to read 3, iclass 3, count 2 2006.173.07:06:35.07#ibcon#read 3, iclass 3, count 2 2006.173.07:06:35.07#ibcon#about to read 4, iclass 3, count 2 2006.173.07:06:35.07#ibcon#read 4, iclass 3, count 2 2006.173.07:06:35.07#ibcon#about to read 5, iclass 3, count 2 2006.173.07:06:35.07#ibcon#read 5, iclass 3, count 2 2006.173.07:06:35.07#ibcon#about to read 6, iclass 3, count 2 2006.173.07:06:35.07#ibcon#read 6, iclass 3, count 2 2006.173.07:06:35.07#ibcon#end of sib2, iclass 3, count 2 2006.173.07:06:35.07#ibcon#*after write, iclass 3, count 2 2006.173.07:06:35.07#ibcon#*before return 0, iclass 3, count 2 2006.173.07:06:35.07#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.07:06:35.07#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.07:06:35.07#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.07:06:35.07#ibcon#ireg 7 cls_cnt 0 2006.173.07:06:35.07#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.07:06:35.19#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.07:06:35.19#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.07:06:35.19#ibcon#enter wrdev, iclass 3, count 0 2006.173.07:06:35.19#ibcon#first serial, iclass 3, count 0 2006.173.07:06:35.19#ibcon#enter sib2, iclass 3, count 0 2006.173.07:06:35.19#ibcon#flushed, iclass 3, count 0 2006.173.07:06:35.19#ibcon#about to write, iclass 3, count 0 2006.173.07:06:35.19#ibcon#wrote, iclass 3, count 0 2006.173.07:06:35.19#ibcon#about to read 3, iclass 3, count 0 2006.173.07:06:35.21#ibcon#read 3, iclass 3, count 0 2006.173.07:06:35.21#ibcon#about to read 4, iclass 3, count 0 2006.173.07:06:35.21#ibcon#read 4, iclass 3, count 0 2006.173.07:06:35.21#ibcon#about to read 5, iclass 3, count 0 2006.173.07:06:35.21#ibcon#read 5, iclass 3, count 0 2006.173.07:06:35.21#ibcon#about to read 6, iclass 3, count 0 2006.173.07:06:35.21#ibcon#read 6, iclass 3, count 0 2006.173.07:06:35.21#ibcon#end of sib2, iclass 3, count 0 2006.173.07:06:35.21#ibcon#*mode == 0, iclass 3, count 0 2006.173.07:06:35.21#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.07:06:35.21#ibcon#[27=USB\r\n] 2006.173.07:06:35.21#ibcon#*before write, iclass 3, count 0 2006.173.07:06:35.21#ibcon#enter sib2, iclass 3, count 0 2006.173.07:06:35.21#ibcon#flushed, iclass 3, count 0 2006.173.07:06:35.21#ibcon#about to write, iclass 3, count 0 2006.173.07:06:35.21#ibcon#wrote, iclass 3, count 0 2006.173.07:06:35.21#ibcon#about to read 3, iclass 3, count 0 2006.173.07:06:35.24#abcon#<5=/02 0.4 0.8 23.70 791004.8\r\n> 2006.173.07:06:35.24#ibcon#read 3, iclass 3, count 0 2006.173.07:06:35.24#ibcon#about to read 4, iclass 3, count 0 2006.173.07:06:35.24#ibcon#read 4, iclass 3, count 0 2006.173.07:06:35.24#ibcon#about to read 5, iclass 3, count 0 2006.173.07:06:35.24#ibcon#read 5, iclass 3, count 0 2006.173.07:06:35.24#ibcon#about to read 6, iclass 3, count 0 2006.173.07:06:35.24#ibcon#read 6, iclass 3, count 0 2006.173.07:06:35.24#ibcon#end of sib2, iclass 3, count 0 2006.173.07:06:35.24#ibcon#*after write, iclass 3, count 0 2006.173.07:06:35.24#ibcon#*before return 0, iclass 3, count 0 2006.173.07:06:35.24#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.07:06:35.24#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.07:06:35.24#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.07:06:35.24#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.07:06:35.24$vck44/vblo=5,709.99 2006.173.07:06:35.24#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.07:06:35.24#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.07:06:35.24#ibcon#ireg 17 cls_cnt 0 2006.173.07:06:35.24#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.07:06:35.24#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.07:06:35.24#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.07:06:35.24#ibcon#enter wrdev, iclass 10, count 0 2006.173.07:06:35.24#ibcon#first serial, iclass 10, count 0 2006.173.07:06:35.24#ibcon#enter sib2, iclass 10, count 0 2006.173.07:06:35.24#ibcon#flushed, iclass 10, count 0 2006.173.07:06:35.24#ibcon#about to write, iclass 10, count 0 2006.173.07:06:35.24#ibcon#wrote, iclass 10, count 0 2006.173.07:06:35.24#ibcon#about to read 3, iclass 10, count 0 2006.173.07:06:35.26#ibcon#read 3, iclass 10, count 0 2006.173.07:06:35.26#ibcon#about to read 4, iclass 10, count 0 2006.173.07:06:35.26#ibcon#read 4, iclass 10, count 0 2006.173.07:06:35.26#ibcon#about to read 5, iclass 10, count 0 2006.173.07:06:35.26#ibcon#read 5, iclass 10, count 0 2006.173.07:06:35.26#ibcon#about to read 6, iclass 10, count 0 2006.173.07:06:35.26#ibcon#read 6, iclass 10, count 0 2006.173.07:06:35.26#ibcon#end of sib2, iclass 10, count 0 2006.173.07:06:35.26#ibcon#*mode == 0, iclass 10, count 0 2006.173.07:06:35.26#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.07:06:35.26#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.07:06:35.26#ibcon#*before write, iclass 10, count 0 2006.173.07:06:35.26#ibcon#enter sib2, iclass 10, count 0 2006.173.07:06:35.26#ibcon#flushed, iclass 10, count 0 2006.173.07:06:35.26#ibcon#about to write, iclass 10, count 0 2006.173.07:06:35.26#ibcon#wrote, iclass 10, count 0 2006.173.07:06:35.26#ibcon#about to read 3, iclass 10, count 0 2006.173.07:06:35.26#abcon#{5=INTERFACE CLEAR} 2006.173.07:06:35.30#ibcon#read 3, iclass 10, count 0 2006.173.07:06:35.30#ibcon#about to read 4, iclass 10, count 0 2006.173.07:06:35.30#ibcon#read 4, iclass 10, count 0 2006.173.07:06:35.30#ibcon#about to read 5, iclass 10, count 0 2006.173.07:06:35.30#ibcon#read 5, iclass 10, count 0 2006.173.07:06:35.30#ibcon#about to read 6, iclass 10, count 0 2006.173.07:06:35.30#ibcon#read 6, iclass 10, count 0 2006.173.07:06:35.30#ibcon#end of sib2, iclass 10, count 0 2006.173.07:06:35.30#ibcon#*after write, iclass 10, count 0 2006.173.07:06:35.30#ibcon#*before return 0, iclass 10, count 0 2006.173.07:06:35.30#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.07:06:35.30#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.07:06:35.30#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.07:06:35.30#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.07:06:35.30$vck44/vb=5,4 2006.173.07:06:35.30#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.07:06:35.30#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.07:06:35.30#ibcon#ireg 11 cls_cnt 2 2006.173.07:06:35.30#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.07:06:35.32#abcon#[5=S1D000X0/0*\r\n] 2006.173.07:06:35.36#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.07:06:35.36#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.07:06:35.36#ibcon#enter wrdev, iclass 12, count 2 2006.173.07:06:35.36#ibcon#first serial, iclass 12, count 2 2006.173.07:06:35.36#ibcon#enter sib2, iclass 12, count 2 2006.173.07:06:35.36#ibcon#flushed, iclass 12, count 2 2006.173.07:06:35.36#ibcon#about to write, iclass 12, count 2 2006.173.07:06:35.36#ibcon#wrote, iclass 12, count 2 2006.173.07:06:35.36#ibcon#about to read 3, iclass 12, count 2 2006.173.07:06:35.38#ibcon#read 3, iclass 12, count 2 2006.173.07:06:35.38#ibcon#about to read 4, iclass 12, count 2 2006.173.07:06:35.38#ibcon#read 4, iclass 12, count 2 2006.173.07:06:35.38#ibcon#about to read 5, iclass 12, count 2 2006.173.07:06:35.38#ibcon#read 5, iclass 12, count 2 2006.173.07:06:35.38#ibcon#about to read 6, iclass 12, count 2 2006.173.07:06:35.38#ibcon#read 6, iclass 12, count 2 2006.173.07:06:35.38#ibcon#end of sib2, iclass 12, count 2 2006.173.07:06:35.38#ibcon#*mode == 0, iclass 12, count 2 2006.173.07:06:35.38#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.07:06:35.38#ibcon#[27=AT05-04\r\n] 2006.173.07:06:35.38#ibcon#*before write, iclass 12, count 2 2006.173.07:06:35.38#ibcon#enter sib2, iclass 12, count 2 2006.173.07:06:35.38#ibcon#flushed, iclass 12, count 2 2006.173.07:06:35.38#ibcon#about to write, iclass 12, count 2 2006.173.07:06:35.38#ibcon#wrote, iclass 12, count 2 2006.173.07:06:35.38#ibcon#about to read 3, iclass 12, count 2 2006.173.07:06:35.41#ibcon#read 3, iclass 12, count 2 2006.173.07:06:35.41#ibcon#about to read 4, iclass 12, count 2 2006.173.07:06:35.41#ibcon#read 4, iclass 12, count 2 2006.173.07:06:35.41#ibcon#about to read 5, iclass 12, count 2 2006.173.07:06:35.41#ibcon#read 5, iclass 12, count 2 2006.173.07:06:35.41#ibcon#about to read 6, iclass 12, count 2 2006.173.07:06:35.41#ibcon#read 6, iclass 12, count 2 2006.173.07:06:35.41#ibcon#end of sib2, iclass 12, count 2 2006.173.07:06:35.41#ibcon#*after write, iclass 12, count 2 2006.173.07:06:35.41#ibcon#*before return 0, iclass 12, count 2 2006.173.07:06:35.41#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.07:06:35.41#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.07:06:35.41#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.07:06:35.41#ibcon#ireg 7 cls_cnt 0 2006.173.07:06:35.41#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.07:06:35.53#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.07:06:35.53#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.07:06:35.53#ibcon#enter wrdev, iclass 12, count 0 2006.173.07:06:35.53#ibcon#first serial, iclass 12, count 0 2006.173.07:06:35.53#ibcon#enter sib2, iclass 12, count 0 2006.173.07:06:35.53#ibcon#flushed, iclass 12, count 0 2006.173.07:06:35.53#ibcon#about to write, iclass 12, count 0 2006.173.07:06:35.53#ibcon#wrote, iclass 12, count 0 2006.173.07:06:35.53#ibcon#about to read 3, iclass 12, count 0 2006.173.07:06:35.55#ibcon#read 3, iclass 12, count 0 2006.173.07:06:35.55#ibcon#about to read 4, iclass 12, count 0 2006.173.07:06:35.55#ibcon#read 4, iclass 12, count 0 2006.173.07:06:35.55#ibcon#about to read 5, iclass 12, count 0 2006.173.07:06:35.55#ibcon#read 5, iclass 12, count 0 2006.173.07:06:35.55#ibcon#about to read 6, iclass 12, count 0 2006.173.07:06:35.55#ibcon#read 6, iclass 12, count 0 2006.173.07:06:35.55#ibcon#end of sib2, iclass 12, count 0 2006.173.07:06:35.55#ibcon#*mode == 0, iclass 12, count 0 2006.173.07:06:35.55#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.07:06:35.55#ibcon#[27=USB\r\n] 2006.173.07:06:35.55#ibcon#*before write, iclass 12, count 0 2006.173.07:06:35.55#ibcon#enter sib2, iclass 12, count 0 2006.173.07:06:35.55#ibcon#flushed, iclass 12, count 0 2006.173.07:06:35.55#ibcon#about to write, iclass 12, count 0 2006.173.07:06:35.55#ibcon#wrote, iclass 12, count 0 2006.173.07:06:35.55#ibcon#about to read 3, iclass 12, count 0 2006.173.07:06:35.58#ibcon#read 3, iclass 12, count 0 2006.173.07:06:35.58#ibcon#about to read 4, iclass 12, count 0 2006.173.07:06:35.58#ibcon#read 4, iclass 12, count 0 2006.173.07:06:35.58#ibcon#about to read 5, iclass 12, count 0 2006.173.07:06:35.58#ibcon#read 5, iclass 12, count 0 2006.173.07:06:35.58#ibcon#about to read 6, iclass 12, count 0 2006.173.07:06:35.58#ibcon#read 6, iclass 12, count 0 2006.173.07:06:35.58#ibcon#end of sib2, iclass 12, count 0 2006.173.07:06:35.58#ibcon#*after write, iclass 12, count 0 2006.173.07:06:35.58#ibcon#*before return 0, iclass 12, count 0 2006.173.07:06:35.58#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.07:06:35.58#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.07:06:35.58#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.07:06:35.58#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.07:06:35.58$vck44/vblo=6,719.99 2006.173.07:06:35.58#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.07:06:35.58#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.07:06:35.58#ibcon#ireg 17 cls_cnt 0 2006.173.07:06:35.58#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.07:06:35.58#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.07:06:35.58#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.07:06:35.58#ibcon#enter wrdev, iclass 15, count 0 2006.173.07:06:35.58#ibcon#first serial, iclass 15, count 0 2006.173.07:06:35.58#ibcon#enter sib2, iclass 15, count 0 2006.173.07:06:35.58#ibcon#flushed, iclass 15, count 0 2006.173.07:06:35.58#ibcon#about to write, iclass 15, count 0 2006.173.07:06:35.58#ibcon#wrote, iclass 15, count 0 2006.173.07:06:35.58#ibcon#about to read 3, iclass 15, count 0 2006.173.07:06:35.60#ibcon#read 3, iclass 15, count 0 2006.173.07:06:35.60#ibcon#about to read 4, iclass 15, count 0 2006.173.07:06:35.60#ibcon#read 4, iclass 15, count 0 2006.173.07:06:35.60#ibcon#about to read 5, iclass 15, count 0 2006.173.07:06:35.60#ibcon#read 5, iclass 15, count 0 2006.173.07:06:35.60#ibcon#about to read 6, iclass 15, count 0 2006.173.07:06:35.60#ibcon#read 6, iclass 15, count 0 2006.173.07:06:35.60#ibcon#end of sib2, iclass 15, count 0 2006.173.07:06:35.60#ibcon#*mode == 0, iclass 15, count 0 2006.173.07:06:35.60#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.07:06:35.60#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.07:06:35.60#ibcon#*before write, iclass 15, count 0 2006.173.07:06:35.60#ibcon#enter sib2, iclass 15, count 0 2006.173.07:06:35.60#ibcon#flushed, iclass 15, count 0 2006.173.07:06:35.60#ibcon#about to write, iclass 15, count 0 2006.173.07:06:35.60#ibcon#wrote, iclass 15, count 0 2006.173.07:06:35.60#ibcon#about to read 3, iclass 15, count 0 2006.173.07:06:35.64#ibcon#read 3, iclass 15, count 0 2006.173.07:06:35.64#ibcon#about to read 4, iclass 15, count 0 2006.173.07:06:35.64#ibcon#read 4, iclass 15, count 0 2006.173.07:06:35.64#ibcon#about to read 5, iclass 15, count 0 2006.173.07:06:35.64#ibcon#read 5, iclass 15, count 0 2006.173.07:06:35.64#ibcon#about to read 6, iclass 15, count 0 2006.173.07:06:35.64#ibcon#read 6, iclass 15, count 0 2006.173.07:06:35.64#ibcon#end of sib2, iclass 15, count 0 2006.173.07:06:35.64#ibcon#*after write, iclass 15, count 0 2006.173.07:06:35.64#ibcon#*before return 0, iclass 15, count 0 2006.173.07:06:35.64#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.07:06:35.64#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.07:06:35.64#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.07:06:35.64#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.07:06:35.64$vck44/vb=6,4 2006.173.07:06:35.64#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.07:06:35.64#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.07:06:35.64#ibcon#ireg 11 cls_cnt 2 2006.173.07:06:35.64#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.07:06:35.70#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.07:06:35.70#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.07:06:35.70#ibcon#enter wrdev, iclass 17, count 2 2006.173.07:06:35.70#ibcon#first serial, iclass 17, count 2 2006.173.07:06:35.70#ibcon#enter sib2, iclass 17, count 2 2006.173.07:06:35.70#ibcon#flushed, iclass 17, count 2 2006.173.07:06:35.70#ibcon#about to write, iclass 17, count 2 2006.173.07:06:35.70#ibcon#wrote, iclass 17, count 2 2006.173.07:06:35.70#ibcon#about to read 3, iclass 17, count 2 2006.173.07:06:35.72#ibcon#read 3, iclass 17, count 2 2006.173.07:06:35.72#ibcon#about to read 4, iclass 17, count 2 2006.173.07:06:35.72#ibcon#read 4, iclass 17, count 2 2006.173.07:06:35.72#ibcon#about to read 5, iclass 17, count 2 2006.173.07:06:35.72#ibcon#read 5, iclass 17, count 2 2006.173.07:06:35.72#ibcon#about to read 6, iclass 17, count 2 2006.173.07:06:35.72#ibcon#read 6, iclass 17, count 2 2006.173.07:06:35.72#ibcon#end of sib2, iclass 17, count 2 2006.173.07:06:35.72#ibcon#*mode == 0, iclass 17, count 2 2006.173.07:06:35.72#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.07:06:35.72#ibcon#[27=AT06-04\r\n] 2006.173.07:06:35.72#ibcon#*before write, iclass 17, count 2 2006.173.07:06:35.72#ibcon#enter sib2, iclass 17, count 2 2006.173.07:06:35.72#ibcon#flushed, iclass 17, count 2 2006.173.07:06:35.72#ibcon#about to write, iclass 17, count 2 2006.173.07:06:35.72#ibcon#wrote, iclass 17, count 2 2006.173.07:06:35.72#ibcon#about to read 3, iclass 17, count 2 2006.173.07:06:35.75#ibcon#read 3, iclass 17, count 2 2006.173.07:06:35.75#ibcon#about to read 4, iclass 17, count 2 2006.173.07:06:35.75#ibcon#read 4, iclass 17, count 2 2006.173.07:06:35.75#ibcon#about to read 5, iclass 17, count 2 2006.173.07:06:35.75#ibcon#read 5, iclass 17, count 2 2006.173.07:06:35.75#ibcon#about to read 6, iclass 17, count 2 2006.173.07:06:35.75#ibcon#read 6, iclass 17, count 2 2006.173.07:06:35.75#ibcon#end of sib2, iclass 17, count 2 2006.173.07:06:35.75#ibcon#*after write, iclass 17, count 2 2006.173.07:06:35.75#ibcon#*before return 0, iclass 17, count 2 2006.173.07:06:35.75#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.07:06:35.75#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.07:06:35.75#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.07:06:35.75#ibcon#ireg 7 cls_cnt 0 2006.173.07:06:35.75#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.07:06:35.87#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.07:06:35.87#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.07:06:35.87#ibcon#enter wrdev, iclass 17, count 0 2006.173.07:06:35.87#ibcon#first serial, iclass 17, count 0 2006.173.07:06:35.87#ibcon#enter sib2, iclass 17, count 0 2006.173.07:06:35.87#ibcon#flushed, iclass 17, count 0 2006.173.07:06:35.87#ibcon#about to write, iclass 17, count 0 2006.173.07:06:35.87#ibcon#wrote, iclass 17, count 0 2006.173.07:06:35.87#ibcon#about to read 3, iclass 17, count 0 2006.173.07:06:35.89#ibcon#read 3, iclass 17, count 0 2006.173.07:06:35.89#ibcon#about to read 4, iclass 17, count 0 2006.173.07:06:35.89#ibcon#read 4, iclass 17, count 0 2006.173.07:06:35.89#ibcon#about to read 5, iclass 17, count 0 2006.173.07:06:35.89#ibcon#read 5, iclass 17, count 0 2006.173.07:06:35.89#ibcon#about to read 6, iclass 17, count 0 2006.173.07:06:35.89#ibcon#read 6, iclass 17, count 0 2006.173.07:06:35.89#ibcon#end of sib2, iclass 17, count 0 2006.173.07:06:35.89#ibcon#*mode == 0, iclass 17, count 0 2006.173.07:06:35.89#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.07:06:35.89#ibcon#[27=USB\r\n] 2006.173.07:06:35.89#ibcon#*before write, iclass 17, count 0 2006.173.07:06:35.89#ibcon#enter sib2, iclass 17, count 0 2006.173.07:06:35.89#ibcon#flushed, iclass 17, count 0 2006.173.07:06:35.89#ibcon#about to write, iclass 17, count 0 2006.173.07:06:35.89#ibcon#wrote, iclass 17, count 0 2006.173.07:06:35.89#ibcon#about to read 3, iclass 17, count 0 2006.173.07:06:35.92#ibcon#read 3, iclass 17, count 0 2006.173.07:06:35.92#ibcon#about to read 4, iclass 17, count 0 2006.173.07:06:35.92#ibcon#read 4, iclass 17, count 0 2006.173.07:06:35.92#ibcon#about to read 5, iclass 17, count 0 2006.173.07:06:35.92#ibcon#read 5, iclass 17, count 0 2006.173.07:06:35.92#ibcon#about to read 6, iclass 17, count 0 2006.173.07:06:35.92#ibcon#read 6, iclass 17, count 0 2006.173.07:06:35.92#ibcon#end of sib2, iclass 17, count 0 2006.173.07:06:35.92#ibcon#*after write, iclass 17, count 0 2006.173.07:06:35.92#ibcon#*before return 0, iclass 17, count 0 2006.173.07:06:35.92#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.07:06:35.92#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.07:06:35.92#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.07:06:35.92#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.07:06:35.92$vck44/vblo=7,734.99 2006.173.07:06:35.92#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.07:06:35.92#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.07:06:35.92#ibcon#ireg 17 cls_cnt 0 2006.173.07:06:35.92#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.07:06:35.92#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.07:06:35.92#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.07:06:35.92#ibcon#enter wrdev, iclass 19, count 0 2006.173.07:06:35.92#ibcon#first serial, iclass 19, count 0 2006.173.07:06:35.92#ibcon#enter sib2, iclass 19, count 0 2006.173.07:06:35.92#ibcon#flushed, iclass 19, count 0 2006.173.07:06:35.92#ibcon#about to write, iclass 19, count 0 2006.173.07:06:35.92#ibcon#wrote, iclass 19, count 0 2006.173.07:06:35.92#ibcon#about to read 3, iclass 19, count 0 2006.173.07:06:35.94#ibcon#read 3, iclass 19, count 0 2006.173.07:06:35.94#ibcon#about to read 4, iclass 19, count 0 2006.173.07:06:35.94#ibcon#read 4, iclass 19, count 0 2006.173.07:06:35.94#ibcon#about to read 5, iclass 19, count 0 2006.173.07:06:35.94#ibcon#read 5, iclass 19, count 0 2006.173.07:06:35.94#ibcon#about to read 6, iclass 19, count 0 2006.173.07:06:35.94#ibcon#read 6, iclass 19, count 0 2006.173.07:06:35.94#ibcon#end of sib2, iclass 19, count 0 2006.173.07:06:35.94#ibcon#*mode == 0, iclass 19, count 0 2006.173.07:06:35.94#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.07:06:35.94#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.07:06:35.94#ibcon#*before write, iclass 19, count 0 2006.173.07:06:35.94#ibcon#enter sib2, iclass 19, count 0 2006.173.07:06:35.94#ibcon#flushed, iclass 19, count 0 2006.173.07:06:35.94#ibcon#about to write, iclass 19, count 0 2006.173.07:06:35.94#ibcon#wrote, iclass 19, count 0 2006.173.07:06:35.94#ibcon#about to read 3, iclass 19, count 0 2006.173.07:06:35.98#ibcon#read 3, iclass 19, count 0 2006.173.07:06:35.98#ibcon#about to read 4, iclass 19, count 0 2006.173.07:06:35.98#ibcon#read 4, iclass 19, count 0 2006.173.07:06:35.98#ibcon#about to read 5, iclass 19, count 0 2006.173.07:06:35.98#ibcon#read 5, iclass 19, count 0 2006.173.07:06:35.98#ibcon#about to read 6, iclass 19, count 0 2006.173.07:06:35.98#ibcon#read 6, iclass 19, count 0 2006.173.07:06:35.98#ibcon#end of sib2, iclass 19, count 0 2006.173.07:06:35.98#ibcon#*after write, iclass 19, count 0 2006.173.07:06:35.98#ibcon#*before return 0, iclass 19, count 0 2006.173.07:06:35.98#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.07:06:35.98#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.07:06:35.98#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.07:06:35.98#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.07:06:35.98$vck44/vb=7,4 2006.173.07:06:35.98#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.07:06:35.98#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.07:06:35.98#ibcon#ireg 11 cls_cnt 2 2006.173.07:06:35.98#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.07:06:36.04#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.07:06:36.04#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.07:06:36.04#ibcon#enter wrdev, iclass 21, count 2 2006.173.07:06:36.04#ibcon#first serial, iclass 21, count 2 2006.173.07:06:36.04#ibcon#enter sib2, iclass 21, count 2 2006.173.07:06:36.04#ibcon#flushed, iclass 21, count 2 2006.173.07:06:36.04#ibcon#about to write, iclass 21, count 2 2006.173.07:06:36.04#ibcon#wrote, iclass 21, count 2 2006.173.07:06:36.04#ibcon#about to read 3, iclass 21, count 2 2006.173.07:06:36.06#ibcon#read 3, iclass 21, count 2 2006.173.07:06:36.06#ibcon#about to read 4, iclass 21, count 2 2006.173.07:06:36.06#ibcon#read 4, iclass 21, count 2 2006.173.07:06:36.06#ibcon#about to read 5, iclass 21, count 2 2006.173.07:06:36.06#ibcon#read 5, iclass 21, count 2 2006.173.07:06:36.06#ibcon#about to read 6, iclass 21, count 2 2006.173.07:06:36.06#ibcon#read 6, iclass 21, count 2 2006.173.07:06:36.06#ibcon#end of sib2, iclass 21, count 2 2006.173.07:06:36.06#ibcon#*mode == 0, iclass 21, count 2 2006.173.07:06:36.06#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.07:06:36.06#ibcon#[27=AT07-04\r\n] 2006.173.07:06:36.06#ibcon#*before write, iclass 21, count 2 2006.173.07:06:36.06#ibcon#enter sib2, iclass 21, count 2 2006.173.07:06:36.06#ibcon#flushed, iclass 21, count 2 2006.173.07:06:36.06#ibcon#about to write, iclass 21, count 2 2006.173.07:06:36.06#ibcon#wrote, iclass 21, count 2 2006.173.07:06:36.06#ibcon#about to read 3, iclass 21, count 2 2006.173.07:06:36.09#ibcon#read 3, iclass 21, count 2 2006.173.07:06:36.09#ibcon#about to read 4, iclass 21, count 2 2006.173.07:06:36.09#ibcon#read 4, iclass 21, count 2 2006.173.07:06:36.09#ibcon#about to read 5, iclass 21, count 2 2006.173.07:06:36.09#ibcon#read 5, iclass 21, count 2 2006.173.07:06:36.09#ibcon#about to read 6, iclass 21, count 2 2006.173.07:06:36.09#ibcon#read 6, iclass 21, count 2 2006.173.07:06:36.09#ibcon#end of sib2, iclass 21, count 2 2006.173.07:06:36.09#ibcon#*after write, iclass 21, count 2 2006.173.07:06:36.09#ibcon#*before return 0, iclass 21, count 2 2006.173.07:06:36.09#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.07:06:36.09#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.07:06:36.09#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.07:06:36.09#ibcon#ireg 7 cls_cnt 0 2006.173.07:06:36.09#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.07:06:36.21#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.07:06:36.21#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.07:06:36.21#ibcon#enter wrdev, iclass 21, count 0 2006.173.07:06:36.21#ibcon#first serial, iclass 21, count 0 2006.173.07:06:36.21#ibcon#enter sib2, iclass 21, count 0 2006.173.07:06:36.21#ibcon#flushed, iclass 21, count 0 2006.173.07:06:36.21#ibcon#about to write, iclass 21, count 0 2006.173.07:06:36.21#ibcon#wrote, iclass 21, count 0 2006.173.07:06:36.21#ibcon#about to read 3, iclass 21, count 0 2006.173.07:06:36.23#ibcon#read 3, iclass 21, count 0 2006.173.07:06:36.23#ibcon#about to read 4, iclass 21, count 0 2006.173.07:06:36.23#ibcon#read 4, iclass 21, count 0 2006.173.07:06:36.23#ibcon#about to read 5, iclass 21, count 0 2006.173.07:06:36.23#ibcon#read 5, iclass 21, count 0 2006.173.07:06:36.23#ibcon#about to read 6, iclass 21, count 0 2006.173.07:06:36.23#ibcon#read 6, iclass 21, count 0 2006.173.07:06:36.23#ibcon#end of sib2, iclass 21, count 0 2006.173.07:06:36.23#ibcon#*mode == 0, iclass 21, count 0 2006.173.07:06:36.23#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.07:06:36.23#ibcon#[27=USB\r\n] 2006.173.07:06:36.23#ibcon#*before write, iclass 21, count 0 2006.173.07:06:36.23#ibcon#enter sib2, iclass 21, count 0 2006.173.07:06:36.23#ibcon#flushed, iclass 21, count 0 2006.173.07:06:36.23#ibcon#about to write, iclass 21, count 0 2006.173.07:06:36.23#ibcon#wrote, iclass 21, count 0 2006.173.07:06:36.23#ibcon#about to read 3, iclass 21, count 0 2006.173.07:06:36.26#ibcon#read 3, iclass 21, count 0 2006.173.07:06:36.26#ibcon#about to read 4, iclass 21, count 0 2006.173.07:06:36.26#ibcon#read 4, iclass 21, count 0 2006.173.07:06:36.26#ibcon#about to read 5, iclass 21, count 0 2006.173.07:06:36.26#ibcon#read 5, iclass 21, count 0 2006.173.07:06:36.26#ibcon#about to read 6, iclass 21, count 0 2006.173.07:06:36.26#ibcon#read 6, iclass 21, count 0 2006.173.07:06:36.26#ibcon#end of sib2, iclass 21, count 0 2006.173.07:06:36.26#ibcon#*after write, iclass 21, count 0 2006.173.07:06:36.26#ibcon#*before return 0, iclass 21, count 0 2006.173.07:06:36.26#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.07:06:36.26#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.07:06:36.26#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.07:06:36.26#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.07:06:36.26$vck44/vblo=8,744.99 2006.173.07:06:36.26#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.07:06:36.26#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.07:06:36.26#ibcon#ireg 17 cls_cnt 0 2006.173.07:06:36.26#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.07:06:36.26#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.07:06:36.26#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.07:06:36.26#ibcon#enter wrdev, iclass 23, count 0 2006.173.07:06:36.26#ibcon#first serial, iclass 23, count 0 2006.173.07:06:36.26#ibcon#enter sib2, iclass 23, count 0 2006.173.07:06:36.26#ibcon#flushed, iclass 23, count 0 2006.173.07:06:36.26#ibcon#about to write, iclass 23, count 0 2006.173.07:06:36.26#ibcon#wrote, iclass 23, count 0 2006.173.07:06:36.26#ibcon#about to read 3, iclass 23, count 0 2006.173.07:06:36.28#ibcon#read 3, iclass 23, count 0 2006.173.07:06:36.28#ibcon#about to read 4, iclass 23, count 0 2006.173.07:06:36.28#ibcon#read 4, iclass 23, count 0 2006.173.07:06:36.28#ibcon#about to read 5, iclass 23, count 0 2006.173.07:06:36.28#ibcon#read 5, iclass 23, count 0 2006.173.07:06:36.28#ibcon#about to read 6, iclass 23, count 0 2006.173.07:06:36.28#ibcon#read 6, iclass 23, count 0 2006.173.07:06:36.28#ibcon#end of sib2, iclass 23, count 0 2006.173.07:06:36.28#ibcon#*mode == 0, iclass 23, count 0 2006.173.07:06:36.28#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.07:06:36.28#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.07:06:36.28#ibcon#*before write, iclass 23, count 0 2006.173.07:06:36.28#ibcon#enter sib2, iclass 23, count 0 2006.173.07:06:36.28#ibcon#flushed, iclass 23, count 0 2006.173.07:06:36.28#ibcon#about to write, iclass 23, count 0 2006.173.07:06:36.28#ibcon#wrote, iclass 23, count 0 2006.173.07:06:36.28#ibcon#about to read 3, iclass 23, count 0 2006.173.07:06:36.32#ibcon#read 3, iclass 23, count 0 2006.173.07:06:36.32#ibcon#about to read 4, iclass 23, count 0 2006.173.07:06:36.32#ibcon#read 4, iclass 23, count 0 2006.173.07:06:36.32#ibcon#about to read 5, iclass 23, count 0 2006.173.07:06:36.32#ibcon#read 5, iclass 23, count 0 2006.173.07:06:36.32#ibcon#about to read 6, iclass 23, count 0 2006.173.07:06:36.32#ibcon#read 6, iclass 23, count 0 2006.173.07:06:36.32#ibcon#end of sib2, iclass 23, count 0 2006.173.07:06:36.32#ibcon#*after write, iclass 23, count 0 2006.173.07:06:36.32#ibcon#*before return 0, iclass 23, count 0 2006.173.07:06:36.32#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.07:06:36.32#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.07:06:36.32#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.07:06:36.32#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.07:06:36.32$vck44/vb=8,4 2006.173.07:06:36.32#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.07:06:36.32#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.07:06:36.32#ibcon#ireg 11 cls_cnt 2 2006.173.07:06:36.32#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.07:06:36.38#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.07:06:36.38#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.07:06:36.38#ibcon#enter wrdev, iclass 25, count 2 2006.173.07:06:36.38#ibcon#first serial, iclass 25, count 2 2006.173.07:06:36.38#ibcon#enter sib2, iclass 25, count 2 2006.173.07:06:36.38#ibcon#flushed, iclass 25, count 2 2006.173.07:06:36.38#ibcon#about to write, iclass 25, count 2 2006.173.07:06:36.38#ibcon#wrote, iclass 25, count 2 2006.173.07:06:36.38#ibcon#about to read 3, iclass 25, count 2 2006.173.07:06:36.40#ibcon#read 3, iclass 25, count 2 2006.173.07:06:36.40#ibcon#about to read 4, iclass 25, count 2 2006.173.07:06:36.40#ibcon#read 4, iclass 25, count 2 2006.173.07:06:36.40#ibcon#about to read 5, iclass 25, count 2 2006.173.07:06:36.40#ibcon#read 5, iclass 25, count 2 2006.173.07:06:36.40#ibcon#about to read 6, iclass 25, count 2 2006.173.07:06:36.40#ibcon#read 6, iclass 25, count 2 2006.173.07:06:36.40#ibcon#end of sib2, iclass 25, count 2 2006.173.07:06:36.40#ibcon#*mode == 0, iclass 25, count 2 2006.173.07:06:36.40#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.07:06:36.40#ibcon#[27=AT08-04\r\n] 2006.173.07:06:36.40#ibcon#*before write, iclass 25, count 2 2006.173.07:06:36.40#ibcon#enter sib2, iclass 25, count 2 2006.173.07:06:36.40#ibcon#flushed, iclass 25, count 2 2006.173.07:06:36.40#ibcon#about to write, iclass 25, count 2 2006.173.07:06:36.40#ibcon#wrote, iclass 25, count 2 2006.173.07:06:36.40#ibcon#about to read 3, iclass 25, count 2 2006.173.07:06:36.43#ibcon#read 3, iclass 25, count 2 2006.173.07:06:36.43#ibcon#about to read 4, iclass 25, count 2 2006.173.07:06:36.43#ibcon#read 4, iclass 25, count 2 2006.173.07:06:36.43#ibcon#about to read 5, iclass 25, count 2 2006.173.07:06:36.43#ibcon#read 5, iclass 25, count 2 2006.173.07:06:36.43#ibcon#about to read 6, iclass 25, count 2 2006.173.07:06:36.43#ibcon#read 6, iclass 25, count 2 2006.173.07:06:36.43#ibcon#end of sib2, iclass 25, count 2 2006.173.07:06:36.43#ibcon#*after write, iclass 25, count 2 2006.173.07:06:36.43#ibcon#*before return 0, iclass 25, count 2 2006.173.07:06:36.43#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.07:06:36.43#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.07:06:36.43#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.07:06:36.43#ibcon#ireg 7 cls_cnt 0 2006.173.07:06:36.43#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.07:06:36.55#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.07:06:36.55#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.07:06:36.55#ibcon#enter wrdev, iclass 25, count 0 2006.173.07:06:36.55#ibcon#first serial, iclass 25, count 0 2006.173.07:06:36.55#ibcon#enter sib2, iclass 25, count 0 2006.173.07:06:36.55#ibcon#flushed, iclass 25, count 0 2006.173.07:06:36.55#ibcon#about to write, iclass 25, count 0 2006.173.07:06:36.55#ibcon#wrote, iclass 25, count 0 2006.173.07:06:36.55#ibcon#about to read 3, iclass 25, count 0 2006.173.07:06:36.57#ibcon#read 3, iclass 25, count 0 2006.173.07:06:36.57#ibcon#about to read 4, iclass 25, count 0 2006.173.07:06:36.57#ibcon#read 4, iclass 25, count 0 2006.173.07:06:36.57#ibcon#about to read 5, iclass 25, count 0 2006.173.07:06:36.57#ibcon#read 5, iclass 25, count 0 2006.173.07:06:36.57#ibcon#about to read 6, iclass 25, count 0 2006.173.07:06:36.57#ibcon#read 6, iclass 25, count 0 2006.173.07:06:36.57#ibcon#end of sib2, iclass 25, count 0 2006.173.07:06:36.57#ibcon#*mode == 0, iclass 25, count 0 2006.173.07:06:36.57#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.07:06:36.57#ibcon#[27=USB\r\n] 2006.173.07:06:36.57#ibcon#*before write, iclass 25, count 0 2006.173.07:06:36.57#ibcon#enter sib2, iclass 25, count 0 2006.173.07:06:36.57#ibcon#flushed, iclass 25, count 0 2006.173.07:06:36.57#ibcon#about to write, iclass 25, count 0 2006.173.07:06:36.57#ibcon#wrote, iclass 25, count 0 2006.173.07:06:36.57#ibcon#about to read 3, iclass 25, count 0 2006.173.07:06:36.60#ibcon#read 3, iclass 25, count 0 2006.173.07:06:36.60#ibcon#about to read 4, iclass 25, count 0 2006.173.07:06:36.60#ibcon#read 4, iclass 25, count 0 2006.173.07:06:36.60#ibcon#about to read 5, iclass 25, count 0 2006.173.07:06:36.60#ibcon#read 5, iclass 25, count 0 2006.173.07:06:36.60#ibcon#about to read 6, iclass 25, count 0 2006.173.07:06:36.60#ibcon#read 6, iclass 25, count 0 2006.173.07:06:36.60#ibcon#end of sib2, iclass 25, count 0 2006.173.07:06:36.60#ibcon#*after write, iclass 25, count 0 2006.173.07:06:36.60#ibcon#*before return 0, iclass 25, count 0 2006.173.07:06:36.60#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.07:06:36.60#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.07:06:36.60#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.07:06:36.60#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.07:06:36.60$vck44/vabw=wide 2006.173.07:06:36.60#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.07:06:36.60#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.07:06:36.60#ibcon#ireg 8 cls_cnt 0 2006.173.07:06:36.60#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.07:06:36.60#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.07:06:36.60#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.07:06:36.60#ibcon#enter wrdev, iclass 27, count 0 2006.173.07:06:36.60#ibcon#first serial, iclass 27, count 0 2006.173.07:06:36.60#ibcon#enter sib2, iclass 27, count 0 2006.173.07:06:36.60#ibcon#flushed, iclass 27, count 0 2006.173.07:06:36.60#ibcon#about to write, iclass 27, count 0 2006.173.07:06:36.60#ibcon#wrote, iclass 27, count 0 2006.173.07:06:36.60#ibcon#about to read 3, iclass 27, count 0 2006.173.07:06:36.62#ibcon#read 3, iclass 27, count 0 2006.173.07:06:36.62#ibcon#about to read 4, iclass 27, count 0 2006.173.07:06:36.62#ibcon#read 4, iclass 27, count 0 2006.173.07:06:36.62#ibcon#about to read 5, iclass 27, count 0 2006.173.07:06:36.62#ibcon#read 5, iclass 27, count 0 2006.173.07:06:36.62#ibcon#about to read 6, iclass 27, count 0 2006.173.07:06:36.62#ibcon#read 6, iclass 27, count 0 2006.173.07:06:36.62#ibcon#end of sib2, iclass 27, count 0 2006.173.07:06:36.62#ibcon#*mode == 0, iclass 27, count 0 2006.173.07:06:36.62#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.07:06:36.62#ibcon#[25=BW32\r\n] 2006.173.07:06:36.62#ibcon#*before write, iclass 27, count 0 2006.173.07:06:36.62#ibcon#enter sib2, iclass 27, count 0 2006.173.07:06:36.62#ibcon#flushed, iclass 27, count 0 2006.173.07:06:36.62#ibcon#about to write, iclass 27, count 0 2006.173.07:06:36.62#ibcon#wrote, iclass 27, count 0 2006.173.07:06:36.62#ibcon#about to read 3, iclass 27, count 0 2006.173.07:06:36.65#ibcon#read 3, iclass 27, count 0 2006.173.07:06:36.65#ibcon#about to read 4, iclass 27, count 0 2006.173.07:06:36.65#ibcon#read 4, iclass 27, count 0 2006.173.07:06:36.65#ibcon#about to read 5, iclass 27, count 0 2006.173.07:06:36.65#ibcon#read 5, iclass 27, count 0 2006.173.07:06:36.65#ibcon#about to read 6, iclass 27, count 0 2006.173.07:06:36.65#ibcon#read 6, iclass 27, count 0 2006.173.07:06:36.65#ibcon#end of sib2, iclass 27, count 0 2006.173.07:06:36.65#ibcon#*after write, iclass 27, count 0 2006.173.07:06:36.65#ibcon#*before return 0, iclass 27, count 0 2006.173.07:06:36.65#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.07:06:36.65#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.07:06:36.65#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.07:06:36.65#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.07:06:36.65$vck44/vbbw=wide 2006.173.07:06:36.65#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.07:06:36.65#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.07:06:36.65#ibcon#ireg 8 cls_cnt 0 2006.173.07:06:36.65#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.07:06:36.72#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.07:06:36.72#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.07:06:36.72#ibcon#enter wrdev, iclass 29, count 0 2006.173.07:06:36.72#ibcon#first serial, iclass 29, count 0 2006.173.07:06:36.72#ibcon#enter sib2, iclass 29, count 0 2006.173.07:06:36.72#ibcon#flushed, iclass 29, count 0 2006.173.07:06:36.72#ibcon#about to write, iclass 29, count 0 2006.173.07:06:36.72#ibcon#wrote, iclass 29, count 0 2006.173.07:06:36.72#ibcon#about to read 3, iclass 29, count 0 2006.173.07:06:36.74#ibcon#read 3, iclass 29, count 0 2006.173.07:06:36.74#ibcon#about to read 4, iclass 29, count 0 2006.173.07:06:36.74#ibcon#read 4, iclass 29, count 0 2006.173.07:06:36.74#ibcon#about to read 5, iclass 29, count 0 2006.173.07:06:36.74#ibcon#read 5, iclass 29, count 0 2006.173.07:06:36.74#ibcon#about to read 6, iclass 29, count 0 2006.173.07:06:36.74#ibcon#read 6, iclass 29, count 0 2006.173.07:06:36.74#ibcon#end of sib2, iclass 29, count 0 2006.173.07:06:36.74#ibcon#*mode == 0, iclass 29, count 0 2006.173.07:06:36.74#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.07:06:36.74#ibcon#[27=BW32\r\n] 2006.173.07:06:36.74#ibcon#*before write, iclass 29, count 0 2006.173.07:06:36.74#ibcon#enter sib2, iclass 29, count 0 2006.173.07:06:36.74#ibcon#flushed, iclass 29, count 0 2006.173.07:06:36.74#ibcon#about to write, iclass 29, count 0 2006.173.07:06:36.74#ibcon#wrote, iclass 29, count 0 2006.173.07:06:36.74#ibcon#about to read 3, iclass 29, count 0 2006.173.07:06:36.77#ibcon#read 3, iclass 29, count 0 2006.173.07:06:36.77#ibcon#about to read 4, iclass 29, count 0 2006.173.07:06:36.77#ibcon#read 4, iclass 29, count 0 2006.173.07:06:36.77#ibcon#about to read 5, iclass 29, count 0 2006.173.07:06:36.77#ibcon#read 5, iclass 29, count 0 2006.173.07:06:36.77#ibcon#about to read 6, iclass 29, count 0 2006.173.07:06:36.77#ibcon#read 6, iclass 29, count 0 2006.173.07:06:36.77#ibcon#end of sib2, iclass 29, count 0 2006.173.07:06:36.77#ibcon#*after write, iclass 29, count 0 2006.173.07:06:36.77#ibcon#*before return 0, iclass 29, count 0 2006.173.07:06:36.77#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.07:06:36.77#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.07:06:36.77#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.07:06:36.77#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.07:06:36.77$setupk4/ifdk4 2006.173.07:06:36.77$ifdk4/lo= 2006.173.07:06:36.77$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.07:06:36.77$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.07:06:36.77$ifdk4/patch= 2006.173.07:06:36.77$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.07:06:36.77$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.07:06:36.77$setupk4/!*+20s 2006.173.07:06:45.41#abcon#<5=/02 0.4 0.8 23.70 791004.8\r\n> 2006.173.07:06:45.43#abcon#{5=INTERFACE CLEAR} 2006.173.07:06:45.49#abcon#[5=S1D000X0/0*\r\n] 2006.173.07:06:48.14#trakl#Source acquired 2006.173.07:06:50.14#flagr#flagr/antenna,acquired 2006.173.07:06:51.27$setupk4/"tpicd 2006.173.07:06:51.27$setupk4/echo=off 2006.173.07:06:51.27$setupk4/xlog=off 2006.173.07:06:51.27:!2006.173.07:08:16 2006.173.07:08:16.00:preob 2006.173.07:08:16.14/onsource/TRACKING 2006.173.07:08:16.14:!2006.173.07:08:26 2006.173.07:08:26.00:"tape 2006.173.07:08:26.00:"st=record 2006.173.07:08:26.00:data_valid=on 2006.173.07:08:26.00:midob 2006.173.07:08:26.14/onsource/TRACKING 2006.173.07:08:26.14/wx/23.73,1004.8,80 2006.173.07:08:26.22/cable/+6.5017E-03 2006.173.07:08:27.31/va/01,07,usb,yes,34,37 2006.173.07:08:27.31/va/02,06,usb,yes,34,35 2006.173.07:08:27.31/va/03,05,usb,yes,43,45 2006.173.07:08:27.31/va/04,06,usb,yes,35,37 2006.173.07:08:27.31/va/05,04,usb,yes,27,28 2006.173.07:08:27.31/va/06,03,usb,yes,38,38 2006.173.07:08:27.31/va/07,04,usb,yes,31,32 2006.173.07:08:27.31/va/08,04,usb,yes,26,32 2006.173.07:08:27.54/valo/01,524.99,yes,locked 2006.173.07:08:27.54/valo/02,534.99,yes,locked 2006.173.07:08:27.54/valo/03,564.99,yes,locked 2006.173.07:08:27.54/valo/04,624.99,yes,locked 2006.173.07:08:27.54/valo/05,734.99,yes,locked 2006.173.07:08:27.54/valo/06,814.99,yes,locked 2006.173.07:08:27.54/valo/07,864.99,yes,locked 2006.173.07:08:27.54/valo/08,884.99,yes,locked 2006.173.07:08:28.63/vb/01,04,usb,yes,29,27 2006.173.07:08:28.63/vb/02,04,usb,yes,31,31 2006.173.07:08:28.63/vb/03,04,usb,yes,28,31 2006.173.07:08:28.63/vb/04,04,usb,yes,32,31 2006.173.07:08:28.63/vb/05,04,usb,yes,25,27 2006.173.07:08:28.63/vb/06,04,usb,yes,29,26 2006.173.07:08:28.63/vb/07,04,usb,yes,29,29 2006.173.07:08:28.63/vb/08,04,usb,yes,27,30 2006.173.07:08:28.86/vblo/01,629.99,yes,locked 2006.173.07:08:28.86/vblo/02,634.99,yes,locked 2006.173.07:08:28.86/vblo/03,649.99,yes,locked 2006.173.07:08:28.86/vblo/04,679.99,yes,locked 2006.173.07:08:28.86/vblo/05,709.99,yes,locked 2006.173.07:08:28.86/vblo/06,719.99,yes,locked 2006.173.07:08:28.86/vblo/07,734.99,yes,locked 2006.173.07:08:28.86/vblo/08,744.99,yes,locked 2006.173.07:08:29.01/vabw/8 2006.173.07:08:29.16/vbbw/8 2006.173.07:08:29.34/xfe/off,on,15.0 2006.173.07:08:29.71/ifatt/23,28,28,28 2006.173.07:08:30.08/fmout-gps/S +3.94E-07 2006.173.07:08:30.12:!2006.173.07:14:36 2006.173.07:14:36.00:data_valid=off 2006.173.07:14:36.01:"et 2006.173.07:14:36.01:!+3s 2006.173.07:14:39.04:"tape 2006.173.07:14:39.05:postob 2006.173.07:14:39.23/cable/+6.5016E-03 2006.173.07:14:39.24/wx/23.82,1004.7,81 2006.173.07:14:39.29/fmout-gps/S +3.96E-07 2006.173.07:14:39.30:scan_name=173-0720,jd0606,70 2006.173.07:14:39.30:source=0727-115,073019.11,-114112.6,2000.0,ccw 2006.173.07:14:41.14#flagr#flagr/antenna,new-source 2006.173.07:14:41.15:checkk5 2006.173.07:14:41.69/chk_autoobs//k5ts1/ autoobs is running! 2006.173.07:14:42.26/chk_autoobs//k5ts2/ autoobs is running! 2006.173.07:14:42.75/chk_autoobs//k5ts3/ autoobs is running! 2006.173.07:14:43.25/chk_autoobs//k5ts4/ autoobs is running! 2006.173.07:14:43.77/chk_obsdata//k5ts1/T1730708??a.dat file size is correct (nominal:1480MB, actual:1476MB). 2006.173.07:14:44.32/chk_obsdata//k5ts2/T1730708??b.dat file size is correct (nominal:1480MB, actual:1476MB). 2006.173.07:14:44.83/chk_obsdata//k5ts3/T1730708??c.dat file size is correct (nominal:1480MB, actual:1476MB). 2006.173.07:14:45.34/chk_obsdata//k5ts4/T1730708??d.dat file size is correct (nominal:1480MB, actual:1476MB). 2006.173.07:14:46.30/k5log//k5ts1_log_newline 2006.173.07:14:47.26/k5log//k5ts2_log_newline 2006.173.07:14:48.20/k5log//k5ts3_log_newline 2006.173.07:14:49.11/k5log//k5ts4_log_newline 2006.173.07:14:49.14/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.07:14:49.14:setupk4=1 2006.173.07:14:49.14$setupk4/echo=on 2006.173.07:14:49.14$setupk4/pcalon 2006.173.07:14:49.14$pcalon/"no phase cal control is implemented here 2006.173.07:14:49.14$setupk4/"tpicd=stop 2006.173.07:14:49.14$setupk4/"rec=synch_on 2006.173.07:14:49.14$setupk4/"rec_mode=128 2006.173.07:14:49.14$setupk4/!* 2006.173.07:14:49.14$setupk4/recpk4 2006.173.07:14:49.14$recpk4/recpatch= 2006.173.07:14:49.15$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.07:14:49.15$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.07:14:49.15$setupk4/vck44 2006.173.07:14:49.15$vck44/valo=1,524.99 2006.173.07:14:49.15#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.07:14:49.15#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.07:14:49.15#ibcon#ireg 17 cls_cnt 0 2006.173.07:14:49.15#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.07:14:49.15#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.07:14:49.15#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.07:14:49.15#ibcon#enter wrdev, iclass 3, count 0 2006.173.07:14:49.15#ibcon#first serial, iclass 3, count 0 2006.173.07:14:49.15#ibcon#enter sib2, iclass 3, count 0 2006.173.07:14:49.15#ibcon#flushed, iclass 3, count 0 2006.173.07:14:49.15#ibcon#about to write, iclass 3, count 0 2006.173.07:14:49.15#ibcon#wrote, iclass 3, count 0 2006.173.07:14:49.15#ibcon#about to read 3, iclass 3, count 0 2006.173.07:14:49.16#ibcon#read 3, iclass 3, count 0 2006.173.07:14:49.16#ibcon#about to read 4, iclass 3, count 0 2006.173.07:14:49.16#ibcon#read 4, iclass 3, count 0 2006.173.07:14:49.16#ibcon#about to read 5, iclass 3, count 0 2006.173.07:14:49.16#ibcon#read 5, iclass 3, count 0 2006.173.07:14:49.16#ibcon#about to read 6, iclass 3, count 0 2006.173.07:14:49.16#ibcon#read 6, iclass 3, count 0 2006.173.07:14:49.16#ibcon#end of sib2, iclass 3, count 0 2006.173.07:14:49.16#ibcon#*mode == 0, iclass 3, count 0 2006.173.07:14:49.16#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.07:14:49.16#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.07:14:49.16#ibcon#*before write, iclass 3, count 0 2006.173.07:14:49.16#ibcon#enter sib2, iclass 3, count 0 2006.173.07:14:49.16#ibcon#flushed, iclass 3, count 0 2006.173.07:14:49.16#ibcon#about to write, iclass 3, count 0 2006.173.07:14:49.16#ibcon#wrote, iclass 3, count 0 2006.173.07:14:49.16#ibcon#about to read 3, iclass 3, count 0 2006.173.07:14:49.21#ibcon#read 3, iclass 3, count 0 2006.173.07:14:49.21#ibcon#about to read 4, iclass 3, count 0 2006.173.07:14:49.21#ibcon#read 4, iclass 3, count 0 2006.173.07:14:49.21#ibcon#about to read 5, iclass 3, count 0 2006.173.07:14:49.21#ibcon#read 5, iclass 3, count 0 2006.173.07:14:49.21#ibcon#about to read 6, iclass 3, count 0 2006.173.07:14:49.21#ibcon#read 6, iclass 3, count 0 2006.173.07:14:49.21#ibcon#end of sib2, iclass 3, count 0 2006.173.07:14:49.21#ibcon#*after write, iclass 3, count 0 2006.173.07:14:49.21#ibcon#*before return 0, iclass 3, count 0 2006.173.07:14:49.21#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.07:14:49.21#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.07:14:49.21#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.07:14:49.21#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.07:14:49.21$vck44/va=1,7 2006.173.07:14:49.22#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.07:14:49.22#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.07:14:49.22#ibcon#ireg 11 cls_cnt 2 2006.173.07:14:49.22#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.07:14:49.22#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.07:14:49.22#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.07:14:49.22#ibcon#enter wrdev, iclass 5, count 2 2006.173.07:14:49.22#ibcon#first serial, iclass 5, count 2 2006.173.07:14:49.22#ibcon#enter sib2, iclass 5, count 2 2006.173.07:14:49.22#ibcon#flushed, iclass 5, count 2 2006.173.07:14:49.22#ibcon#about to write, iclass 5, count 2 2006.173.07:14:49.22#ibcon#wrote, iclass 5, count 2 2006.173.07:14:49.22#ibcon#about to read 3, iclass 5, count 2 2006.173.07:14:49.23#ibcon#read 3, iclass 5, count 2 2006.173.07:14:49.23#ibcon#about to read 4, iclass 5, count 2 2006.173.07:14:49.23#ibcon#read 4, iclass 5, count 2 2006.173.07:14:49.23#ibcon#about to read 5, iclass 5, count 2 2006.173.07:14:49.23#ibcon#read 5, iclass 5, count 2 2006.173.07:14:49.23#ibcon#about to read 6, iclass 5, count 2 2006.173.07:14:49.23#ibcon#read 6, iclass 5, count 2 2006.173.07:14:49.23#ibcon#end of sib2, iclass 5, count 2 2006.173.07:14:49.23#ibcon#*mode == 0, iclass 5, count 2 2006.173.07:14:49.23#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.07:14:49.23#ibcon#[25=AT01-07\r\n] 2006.173.07:14:49.23#ibcon#*before write, iclass 5, count 2 2006.173.07:14:49.23#ibcon#enter sib2, iclass 5, count 2 2006.173.07:14:49.23#ibcon#flushed, iclass 5, count 2 2006.173.07:14:49.23#ibcon#about to write, iclass 5, count 2 2006.173.07:14:49.23#ibcon#wrote, iclass 5, count 2 2006.173.07:14:49.23#ibcon#about to read 3, iclass 5, count 2 2006.173.07:14:49.26#ibcon#read 3, iclass 5, count 2 2006.173.07:14:49.26#ibcon#about to read 4, iclass 5, count 2 2006.173.07:14:49.26#ibcon#read 4, iclass 5, count 2 2006.173.07:14:49.26#ibcon#about to read 5, iclass 5, count 2 2006.173.07:14:49.26#ibcon#read 5, iclass 5, count 2 2006.173.07:14:49.26#ibcon#about to read 6, iclass 5, count 2 2006.173.07:14:49.26#ibcon#read 6, iclass 5, count 2 2006.173.07:14:49.26#ibcon#end of sib2, iclass 5, count 2 2006.173.07:14:49.26#ibcon#*after write, iclass 5, count 2 2006.173.07:14:49.26#ibcon#*before return 0, iclass 5, count 2 2006.173.07:14:49.26#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.07:14:49.26#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.07:14:49.26#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.07:14:49.26#ibcon#ireg 7 cls_cnt 0 2006.173.07:14:49.26#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.07:14:49.38#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.07:14:49.38#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.07:14:49.38#ibcon#enter wrdev, iclass 5, count 0 2006.173.07:14:49.38#ibcon#first serial, iclass 5, count 0 2006.173.07:14:49.38#ibcon#enter sib2, iclass 5, count 0 2006.173.07:14:49.38#ibcon#flushed, iclass 5, count 0 2006.173.07:14:49.38#ibcon#about to write, iclass 5, count 0 2006.173.07:14:49.38#ibcon#wrote, iclass 5, count 0 2006.173.07:14:49.38#ibcon#about to read 3, iclass 5, count 0 2006.173.07:14:49.40#ibcon#read 3, iclass 5, count 0 2006.173.07:14:49.40#ibcon#about to read 4, iclass 5, count 0 2006.173.07:14:49.40#ibcon#read 4, iclass 5, count 0 2006.173.07:14:49.40#ibcon#about to read 5, iclass 5, count 0 2006.173.07:14:49.40#ibcon#read 5, iclass 5, count 0 2006.173.07:14:49.40#ibcon#about to read 6, iclass 5, count 0 2006.173.07:14:49.40#ibcon#read 6, iclass 5, count 0 2006.173.07:14:49.40#ibcon#end of sib2, iclass 5, count 0 2006.173.07:14:49.40#ibcon#*mode == 0, iclass 5, count 0 2006.173.07:14:49.40#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.07:14:49.40#ibcon#[25=USB\r\n] 2006.173.07:14:49.40#ibcon#*before write, iclass 5, count 0 2006.173.07:14:49.40#ibcon#enter sib2, iclass 5, count 0 2006.173.07:14:49.40#ibcon#flushed, iclass 5, count 0 2006.173.07:14:49.40#ibcon#about to write, iclass 5, count 0 2006.173.07:14:49.40#ibcon#wrote, iclass 5, count 0 2006.173.07:14:49.40#ibcon#about to read 3, iclass 5, count 0 2006.173.07:14:49.43#ibcon#read 3, iclass 5, count 0 2006.173.07:14:49.43#ibcon#about to read 4, iclass 5, count 0 2006.173.07:14:49.43#ibcon#read 4, iclass 5, count 0 2006.173.07:14:49.43#ibcon#about to read 5, iclass 5, count 0 2006.173.07:14:49.43#ibcon#read 5, iclass 5, count 0 2006.173.07:14:49.43#ibcon#about to read 6, iclass 5, count 0 2006.173.07:14:49.43#ibcon#read 6, iclass 5, count 0 2006.173.07:14:49.43#ibcon#end of sib2, iclass 5, count 0 2006.173.07:14:49.43#ibcon#*after write, iclass 5, count 0 2006.173.07:14:49.43#ibcon#*before return 0, iclass 5, count 0 2006.173.07:14:49.43#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.07:14:49.43#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.07:14:49.43#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.07:14:49.43#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.07:14:49.44$vck44/valo=2,534.99 2006.173.07:14:49.44#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.07:14:49.44#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.07:14:49.44#ibcon#ireg 17 cls_cnt 0 2006.173.07:14:49.44#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.07:14:49.44#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.07:14:49.44#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.07:14:49.44#ibcon#enter wrdev, iclass 7, count 0 2006.173.07:14:49.44#ibcon#first serial, iclass 7, count 0 2006.173.07:14:49.44#ibcon#enter sib2, iclass 7, count 0 2006.173.07:14:49.44#ibcon#flushed, iclass 7, count 0 2006.173.07:14:49.44#ibcon#about to write, iclass 7, count 0 2006.173.07:14:49.44#ibcon#wrote, iclass 7, count 0 2006.173.07:14:49.44#ibcon#about to read 3, iclass 7, count 0 2006.173.07:14:49.45#ibcon#read 3, iclass 7, count 0 2006.173.07:14:49.45#ibcon#about to read 4, iclass 7, count 0 2006.173.07:14:49.45#ibcon#read 4, iclass 7, count 0 2006.173.07:14:49.45#ibcon#about to read 5, iclass 7, count 0 2006.173.07:14:49.45#ibcon#read 5, iclass 7, count 0 2006.173.07:14:49.45#ibcon#about to read 6, iclass 7, count 0 2006.173.07:14:49.45#ibcon#read 6, iclass 7, count 0 2006.173.07:14:49.45#ibcon#end of sib2, iclass 7, count 0 2006.173.07:14:49.45#ibcon#*mode == 0, iclass 7, count 0 2006.173.07:14:49.45#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.07:14:49.45#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.07:14:49.45#ibcon#*before write, iclass 7, count 0 2006.173.07:14:49.45#ibcon#enter sib2, iclass 7, count 0 2006.173.07:14:49.45#ibcon#flushed, iclass 7, count 0 2006.173.07:14:49.45#ibcon#about to write, iclass 7, count 0 2006.173.07:14:49.45#ibcon#wrote, iclass 7, count 0 2006.173.07:14:49.45#ibcon#about to read 3, iclass 7, count 0 2006.173.07:14:49.49#ibcon#read 3, iclass 7, count 0 2006.173.07:14:49.49#ibcon#about to read 4, iclass 7, count 0 2006.173.07:14:49.49#ibcon#read 4, iclass 7, count 0 2006.173.07:14:49.49#ibcon#about to read 5, iclass 7, count 0 2006.173.07:14:49.49#ibcon#read 5, iclass 7, count 0 2006.173.07:14:49.49#ibcon#about to read 6, iclass 7, count 0 2006.173.07:14:49.49#ibcon#read 6, iclass 7, count 0 2006.173.07:14:49.49#ibcon#end of sib2, iclass 7, count 0 2006.173.07:14:49.49#ibcon#*after write, iclass 7, count 0 2006.173.07:14:49.49#ibcon#*before return 0, iclass 7, count 0 2006.173.07:14:49.49#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.07:14:49.49#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.07:14:49.49#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.07:14:49.49#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.07:14:49.50$vck44/va=2,6 2006.173.07:14:49.50#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.07:14:49.50#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.07:14:49.50#ibcon#ireg 11 cls_cnt 2 2006.173.07:14:49.50#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.07:14:49.54#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.07:14:49.54#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.07:14:49.54#ibcon#enter wrdev, iclass 11, count 2 2006.173.07:14:49.54#ibcon#first serial, iclass 11, count 2 2006.173.07:14:49.54#ibcon#enter sib2, iclass 11, count 2 2006.173.07:14:49.54#ibcon#flushed, iclass 11, count 2 2006.173.07:14:49.54#ibcon#about to write, iclass 11, count 2 2006.173.07:14:49.54#ibcon#wrote, iclass 11, count 2 2006.173.07:14:49.54#ibcon#about to read 3, iclass 11, count 2 2006.173.07:14:49.56#ibcon#read 3, iclass 11, count 2 2006.173.07:14:49.56#ibcon#about to read 4, iclass 11, count 2 2006.173.07:14:49.56#ibcon#read 4, iclass 11, count 2 2006.173.07:14:49.56#ibcon#about to read 5, iclass 11, count 2 2006.173.07:14:49.56#ibcon#read 5, iclass 11, count 2 2006.173.07:14:49.56#ibcon#about to read 6, iclass 11, count 2 2006.173.07:14:49.56#ibcon#read 6, iclass 11, count 2 2006.173.07:14:49.56#ibcon#end of sib2, iclass 11, count 2 2006.173.07:14:49.56#ibcon#*mode == 0, iclass 11, count 2 2006.173.07:14:49.56#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.07:14:49.56#ibcon#[25=AT02-06\r\n] 2006.173.07:14:49.56#ibcon#*before write, iclass 11, count 2 2006.173.07:14:49.56#ibcon#enter sib2, iclass 11, count 2 2006.173.07:14:49.56#ibcon#flushed, iclass 11, count 2 2006.173.07:14:49.56#ibcon#about to write, iclass 11, count 2 2006.173.07:14:49.56#ibcon#wrote, iclass 11, count 2 2006.173.07:14:49.56#ibcon#about to read 3, iclass 11, count 2 2006.173.07:14:49.59#ibcon#read 3, iclass 11, count 2 2006.173.07:14:49.59#ibcon#about to read 4, iclass 11, count 2 2006.173.07:14:49.59#ibcon#read 4, iclass 11, count 2 2006.173.07:14:49.59#ibcon#about to read 5, iclass 11, count 2 2006.173.07:14:49.59#ibcon#read 5, iclass 11, count 2 2006.173.07:14:49.59#ibcon#about to read 6, iclass 11, count 2 2006.173.07:14:49.59#ibcon#read 6, iclass 11, count 2 2006.173.07:14:49.59#ibcon#end of sib2, iclass 11, count 2 2006.173.07:14:49.59#ibcon#*after write, iclass 11, count 2 2006.173.07:14:49.59#ibcon#*before return 0, iclass 11, count 2 2006.173.07:14:49.59#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.07:14:49.59#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.07:14:49.59#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.07:14:49.59#ibcon#ireg 7 cls_cnt 0 2006.173.07:14:49.59#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.07:14:49.71#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.07:14:49.71#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.07:14:49.71#ibcon#enter wrdev, iclass 11, count 0 2006.173.07:14:49.71#ibcon#first serial, iclass 11, count 0 2006.173.07:14:49.71#ibcon#enter sib2, iclass 11, count 0 2006.173.07:14:49.71#ibcon#flushed, iclass 11, count 0 2006.173.07:14:49.71#ibcon#about to write, iclass 11, count 0 2006.173.07:14:49.71#ibcon#wrote, iclass 11, count 0 2006.173.07:14:49.71#ibcon#about to read 3, iclass 11, count 0 2006.173.07:14:49.73#ibcon#read 3, iclass 11, count 0 2006.173.07:14:49.73#ibcon#about to read 4, iclass 11, count 0 2006.173.07:14:49.73#ibcon#read 4, iclass 11, count 0 2006.173.07:14:49.73#ibcon#about to read 5, iclass 11, count 0 2006.173.07:14:49.73#ibcon#read 5, iclass 11, count 0 2006.173.07:14:49.73#ibcon#about to read 6, iclass 11, count 0 2006.173.07:14:49.73#ibcon#read 6, iclass 11, count 0 2006.173.07:14:49.73#ibcon#end of sib2, iclass 11, count 0 2006.173.07:14:49.73#ibcon#*mode == 0, iclass 11, count 0 2006.173.07:14:49.73#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.07:14:49.73#ibcon#[25=USB\r\n] 2006.173.07:14:49.73#ibcon#*before write, iclass 11, count 0 2006.173.07:14:49.73#ibcon#enter sib2, iclass 11, count 0 2006.173.07:14:49.73#ibcon#flushed, iclass 11, count 0 2006.173.07:14:49.73#ibcon#about to write, iclass 11, count 0 2006.173.07:14:49.73#ibcon#wrote, iclass 11, count 0 2006.173.07:14:49.73#ibcon#about to read 3, iclass 11, count 0 2006.173.07:14:49.76#ibcon#read 3, iclass 11, count 0 2006.173.07:14:49.76#ibcon#about to read 4, iclass 11, count 0 2006.173.07:14:49.76#ibcon#read 4, iclass 11, count 0 2006.173.07:14:49.76#ibcon#about to read 5, iclass 11, count 0 2006.173.07:14:49.76#ibcon#read 5, iclass 11, count 0 2006.173.07:14:49.76#ibcon#about to read 6, iclass 11, count 0 2006.173.07:14:49.76#ibcon#read 6, iclass 11, count 0 2006.173.07:14:49.76#ibcon#end of sib2, iclass 11, count 0 2006.173.07:14:49.76#ibcon#*after write, iclass 11, count 0 2006.173.07:14:49.76#ibcon#*before return 0, iclass 11, count 0 2006.173.07:14:49.76#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.07:14:49.76#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.07:14:49.76#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.07:14:49.76#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.07:14:49.76$vck44/valo=3,564.99 2006.173.07:14:49.76#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.07:14:49.76#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.07:14:49.76#ibcon#ireg 17 cls_cnt 0 2006.173.07:14:49.77#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.07:14:49.77#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.07:14:49.77#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.07:14:49.77#ibcon#enter wrdev, iclass 13, count 0 2006.173.07:14:49.77#ibcon#first serial, iclass 13, count 0 2006.173.07:14:49.77#ibcon#enter sib2, iclass 13, count 0 2006.173.07:14:49.77#ibcon#flushed, iclass 13, count 0 2006.173.07:14:49.77#ibcon#about to write, iclass 13, count 0 2006.173.07:14:49.77#ibcon#wrote, iclass 13, count 0 2006.173.07:14:49.77#ibcon#about to read 3, iclass 13, count 0 2006.173.07:14:49.78#ibcon#read 3, iclass 13, count 0 2006.173.07:14:49.78#ibcon#about to read 4, iclass 13, count 0 2006.173.07:14:49.78#ibcon#read 4, iclass 13, count 0 2006.173.07:14:49.78#ibcon#about to read 5, iclass 13, count 0 2006.173.07:14:49.78#ibcon#read 5, iclass 13, count 0 2006.173.07:14:49.78#ibcon#about to read 6, iclass 13, count 0 2006.173.07:14:49.78#ibcon#read 6, iclass 13, count 0 2006.173.07:14:49.78#ibcon#end of sib2, iclass 13, count 0 2006.173.07:14:49.78#ibcon#*mode == 0, iclass 13, count 0 2006.173.07:14:49.78#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.07:14:49.78#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.07:14:49.78#ibcon#*before write, iclass 13, count 0 2006.173.07:14:49.78#ibcon#enter sib2, iclass 13, count 0 2006.173.07:14:49.78#ibcon#flushed, iclass 13, count 0 2006.173.07:14:49.78#ibcon#about to write, iclass 13, count 0 2006.173.07:14:49.78#ibcon#wrote, iclass 13, count 0 2006.173.07:14:49.78#ibcon#about to read 3, iclass 13, count 0 2006.173.07:14:49.82#ibcon#read 3, iclass 13, count 0 2006.173.07:14:49.82#ibcon#about to read 4, iclass 13, count 0 2006.173.07:14:49.82#ibcon#read 4, iclass 13, count 0 2006.173.07:14:49.82#ibcon#about to read 5, iclass 13, count 0 2006.173.07:14:49.82#ibcon#read 5, iclass 13, count 0 2006.173.07:14:49.82#ibcon#about to read 6, iclass 13, count 0 2006.173.07:14:49.82#ibcon#read 6, iclass 13, count 0 2006.173.07:14:49.82#ibcon#end of sib2, iclass 13, count 0 2006.173.07:14:49.82#ibcon#*after write, iclass 13, count 0 2006.173.07:14:49.82#ibcon#*before return 0, iclass 13, count 0 2006.173.07:14:49.82#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.07:14:49.82#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.07:14:49.82#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.07:14:49.82#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.07:14:49.82$vck44/va=3,5 2006.173.07:14:49.82#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.07:14:49.82#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.07:14:49.82#ibcon#ireg 11 cls_cnt 2 2006.173.07:14:49.82#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.07:14:49.88#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.07:14:49.88#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.07:14:49.88#ibcon#enter wrdev, iclass 15, count 2 2006.173.07:14:49.88#ibcon#first serial, iclass 15, count 2 2006.173.07:14:49.88#ibcon#enter sib2, iclass 15, count 2 2006.173.07:14:49.88#ibcon#flushed, iclass 15, count 2 2006.173.07:14:49.88#ibcon#about to write, iclass 15, count 2 2006.173.07:14:49.88#ibcon#wrote, iclass 15, count 2 2006.173.07:14:49.88#ibcon#about to read 3, iclass 15, count 2 2006.173.07:14:49.90#ibcon#read 3, iclass 15, count 2 2006.173.07:14:49.90#ibcon#about to read 4, iclass 15, count 2 2006.173.07:14:49.90#ibcon#read 4, iclass 15, count 2 2006.173.07:14:49.90#ibcon#about to read 5, iclass 15, count 2 2006.173.07:14:49.90#ibcon#read 5, iclass 15, count 2 2006.173.07:14:49.90#ibcon#about to read 6, iclass 15, count 2 2006.173.07:14:49.90#ibcon#read 6, iclass 15, count 2 2006.173.07:14:49.90#ibcon#end of sib2, iclass 15, count 2 2006.173.07:14:49.90#ibcon#*mode == 0, iclass 15, count 2 2006.173.07:14:49.90#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.07:14:49.90#ibcon#[25=AT03-05\r\n] 2006.173.07:14:49.90#ibcon#*before write, iclass 15, count 2 2006.173.07:14:49.90#ibcon#enter sib2, iclass 15, count 2 2006.173.07:14:49.90#ibcon#flushed, iclass 15, count 2 2006.173.07:14:49.90#ibcon#about to write, iclass 15, count 2 2006.173.07:14:49.90#ibcon#wrote, iclass 15, count 2 2006.173.07:14:49.90#ibcon#about to read 3, iclass 15, count 2 2006.173.07:14:49.93#ibcon#read 3, iclass 15, count 2 2006.173.07:14:49.93#ibcon#about to read 4, iclass 15, count 2 2006.173.07:14:49.93#ibcon#read 4, iclass 15, count 2 2006.173.07:14:49.93#ibcon#about to read 5, iclass 15, count 2 2006.173.07:14:49.93#ibcon#read 5, iclass 15, count 2 2006.173.07:14:49.93#ibcon#about to read 6, iclass 15, count 2 2006.173.07:14:49.93#ibcon#read 6, iclass 15, count 2 2006.173.07:14:49.93#ibcon#end of sib2, iclass 15, count 2 2006.173.07:14:49.93#ibcon#*after write, iclass 15, count 2 2006.173.07:14:49.93#ibcon#*before return 0, iclass 15, count 2 2006.173.07:14:49.93#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.07:14:49.93#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.07:14:49.93#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.07:14:49.93#ibcon#ireg 7 cls_cnt 0 2006.173.07:14:49.93#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.07:14:50.05#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.07:14:50.05#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.07:14:50.05#ibcon#enter wrdev, iclass 15, count 0 2006.173.07:14:50.05#ibcon#first serial, iclass 15, count 0 2006.173.07:14:50.05#ibcon#enter sib2, iclass 15, count 0 2006.173.07:14:50.05#ibcon#flushed, iclass 15, count 0 2006.173.07:14:50.05#ibcon#about to write, iclass 15, count 0 2006.173.07:14:50.05#ibcon#wrote, iclass 15, count 0 2006.173.07:14:50.05#ibcon#about to read 3, iclass 15, count 0 2006.173.07:14:50.07#ibcon#read 3, iclass 15, count 0 2006.173.07:14:50.07#ibcon#about to read 4, iclass 15, count 0 2006.173.07:14:50.07#ibcon#read 4, iclass 15, count 0 2006.173.07:14:50.07#ibcon#about to read 5, iclass 15, count 0 2006.173.07:14:50.07#ibcon#read 5, iclass 15, count 0 2006.173.07:14:50.07#ibcon#about to read 6, iclass 15, count 0 2006.173.07:14:50.07#ibcon#read 6, iclass 15, count 0 2006.173.07:14:50.07#ibcon#end of sib2, iclass 15, count 0 2006.173.07:14:50.07#ibcon#*mode == 0, iclass 15, count 0 2006.173.07:14:50.07#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.07:14:50.07#ibcon#[25=USB\r\n] 2006.173.07:14:50.07#ibcon#*before write, iclass 15, count 0 2006.173.07:14:50.07#ibcon#enter sib2, iclass 15, count 0 2006.173.07:14:50.07#ibcon#flushed, iclass 15, count 0 2006.173.07:14:50.07#ibcon#about to write, iclass 15, count 0 2006.173.07:14:50.07#ibcon#wrote, iclass 15, count 0 2006.173.07:14:50.07#ibcon#about to read 3, iclass 15, count 0 2006.173.07:14:50.10#ibcon#read 3, iclass 15, count 0 2006.173.07:14:50.10#ibcon#about to read 4, iclass 15, count 0 2006.173.07:14:50.10#ibcon#read 4, iclass 15, count 0 2006.173.07:14:50.10#ibcon#about to read 5, iclass 15, count 0 2006.173.07:14:50.10#ibcon#read 5, iclass 15, count 0 2006.173.07:14:50.10#ibcon#about to read 6, iclass 15, count 0 2006.173.07:14:50.10#ibcon#read 6, iclass 15, count 0 2006.173.07:14:50.10#ibcon#end of sib2, iclass 15, count 0 2006.173.07:14:50.10#ibcon#*after write, iclass 15, count 0 2006.173.07:14:50.10#ibcon#*before return 0, iclass 15, count 0 2006.173.07:14:50.10#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.07:14:50.10#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.07:14:50.10#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.07:14:50.10#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.07:14:50.10$vck44/valo=4,624.99 2006.173.07:14:50.10#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.07:14:50.10#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.07:14:50.10#ibcon#ireg 17 cls_cnt 0 2006.173.07:14:50.10#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.07:14:50.10#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.07:14:50.10#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.07:14:50.10#ibcon#enter wrdev, iclass 17, count 0 2006.173.07:14:50.10#ibcon#first serial, iclass 17, count 0 2006.173.07:14:50.10#ibcon#enter sib2, iclass 17, count 0 2006.173.07:14:50.10#ibcon#flushed, iclass 17, count 0 2006.173.07:14:50.10#ibcon#about to write, iclass 17, count 0 2006.173.07:14:50.11#ibcon#wrote, iclass 17, count 0 2006.173.07:14:50.11#ibcon#about to read 3, iclass 17, count 0 2006.173.07:14:50.12#ibcon#read 3, iclass 17, count 0 2006.173.07:14:50.12#ibcon#about to read 4, iclass 17, count 0 2006.173.07:14:50.12#ibcon#read 4, iclass 17, count 0 2006.173.07:14:50.12#ibcon#about to read 5, iclass 17, count 0 2006.173.07:14:50.12#ibcon#read 5, iclass 17, count 0 2006.173.07:14:50.12#ibcon#about to read 6, iclass 17, count 0 2006.173.07:14:50.12#ibcon#read 6, iclass 17, count 0 2006.173.07:14:50.12#ibcon#end of sib2, iclass 17, count 0 2006.173.07:14:50.12#ibcon#*mode == 0, iclass 17, count 0 2006.173.07:14:50.12#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.07:14:50.12#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.07:14:50.12#ibcon#*before write, iclass 17, count 0 2006.173.07:14:50.12#ibcon#enter sib2, iclass 17, count 0 2006.173.07:14:50.12#ibcon#flushed, iclass 17, count 0 2006.173.07:14:50.12#ibcon#about to write, iclass 17, count 0 2006.173.07:14:50.12#ibcon#wrote, iclass 17, count 0 2006.173.07:14:50.12#ibcon#about to read 3, iclass 17, count 0 2006.173.07:14:50.16#ibcon#read 3, iclass 17, count 0 2006.173.07:14:50.16#ibcon#about to read 4, iclass 17, count 0 2006.173.07:14:50.16#ibcon#read 4, iclass 17, count 0 2006.173.07:14:50.16#ibcon#about to read 5, iclass 17, count 0 2006.173.07:14:50.16#ibcon#read 5, iclass 17, count 0 2006.173.07:14:50.16#ibcon#about to read 6, iclass 17, count 0 2006.173.07:14:50.16#ibcon#read 6, iclass 17, count 0 2006.173.07:14:50.16#ibcon#end of sib2, iclass 17, count 0 2006.173.07:14:50.16#ibcon#*after write, iclass 17, count 0 2006.173.07:14:50.16#ibcon#*before return 0, iclass 17, count 0 2006.173.07:14:50.16#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.07:14:50.16#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.07:14:50.16#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.07:14:50.16#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.07:14:50.16$vck44/va=4,6 2006.173.07:14:50.16#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.07:14:50.16#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.07:14:50.16#ibcon#ireg 11 cls_cnt 2 2006.173.07:14:50.16#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.07:14:50.22#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.07:14:50.22#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.07:14:50.22#ibcon#enter wrdev, iclass 19, count 2 2006.173.07:14:50.22#ibcon#first serial, iclass 19, count 2 2006.173.07:14:50.22#ibcon#enter sib2, iclass 19, count 2 2006.173.07:14:50.22#ibcon#flushed, iclass 19, count 2 2006.173.07:14:50.22#ibcon#about to write, iclass 19, count 2 2006.173.07:14:50.22#ibcon#wrote, iclass 19, count 2 2006.173.07:14:50.22#ibcon#about to read 3, iclass 19, count 2 2006.173.07:14:50.24#ibcon#read 3, iclass 19, count 2 2006.173.07:14:50.24#ibcon#about to read 4, iclass 19, count 2 2006.173.07:14:50.24#ibcon#read 4, iclass 19, count 2 2006.173.07:14:50.24#ibcon#about to read 5, iclass 19, count 2 2006.173.07:14:50.24#ibcon#read 5, iclass 19, count 2 2006.173.07:14:50.24#ibcon#about to read 6, iclass 19, count 2 2006.173.07:14:50.24#ibcon#read 6, iclass 19, count 2 2006.173.07:14:50.24#ibcon#end of sib2, iclass 19, count 2 2006.173.07:14:50.24#ibcon#*mode == 0, iclass 19, count 2 2006.173.07:14:50.24#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.07:14:50.24#ibcon#[25=AT04-06\r\n] 2006.173.07:14:50.24#ibcon#*before write, iclass 19, count 2 2006.173.07:14:50.24#ibcon#enter sib2, iclass 19, count 2 2006.173.07:14:50.24#ibcon#flushed, iclass 19, count 2 2006.173.07:14:50.24#ibcon#about to write, iclass 19, count 2 2006.173.07:14:50.24#ibcon#wrote, iclass 19, count 2 2006.173.07:14:50.24#ibcon#about to read 3, iclass 19, count 2 2006.173.07:14:50.27#ibcon#read 3, iclass 19, count 2 2006.173.07:14:50.27#ibcon#about to read 4, iclass 19, count 2 2006.173.07:14:50.27#ibcon#read 4, iclass 19, count 2 2006.173.07:14:50.27#ibcon#about to read 5, iclass 19, count 2 2006.173.07:14:50.27#ibcon#read 5, iclass 19, count 2 2006.173.07:14:50.27#ibcon#about to read 6, iclass 19, count 2 2006.173.07:14:50.27#ibcon#read 6, iclass 19, count 2 2006.173.07:14:50.27#ibcon#end of sib2, iclass 19, count 2 2006.173.07:14:50.27#ibcon#*after write, iclass 19, count 2 2006.173.07:14:50.27#ibcon#*before return 0, iclass 19, count 2 2006.173.07:14:50.27#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.07:14:50.27#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.07:14:50.27#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.07:14:50.27#ibcon#ireg 7 cls_cnt 0 2006.173.07:14:50.27#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.07:14:50.39#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.07:14:50.39#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.07:14:50.39#ibcon#enter wrdev, iclass 19, count 0 2006.173.07:14:50.39#ibcon#first serial, iclass 19, count 0 2006.173.07:14:50.39#ibcon#enter sib2, iclass 19, count 0 2006.173.07:14:50.39#ibcon#flushed, iclass 19, count 0 2006.173.07:14:50.39#ibcon#about to write, iclass 19, count 0 2006.173.07:14:50.39#ibcon#wrote, iclass 19, count 0 2006.173.07:14:50.39#ibcon#about to read 3, iclass 19, count 0 2006.173.07:14:50.41#ibcon#read 3, iclass 19, count 0 2006.173.07:14:50.41#ibcon#about to read 4, iclass 19, count 0 2006.173.07:14:50.41#ibcon#read 4, iclass 19, count 0 2006.173.07:14:50.41#ibcon#about to read 5, iclass 19, count 0 2006.173.07:14:50.41#ibcon#read 5, iclass 19, count 0 2006.173.07:14:50.41#ibcon#about to read 6, iclass 19, count 0 2006.173.07:14:50.41#ibcon#read 6, iclass 19, count 0 2006.173.07:14:50.41#ibcon#end of sib2, iclass 19, count 0 2006.173.07:14:50.41#ibcon#*mode == 0, iclass 19, count 0 2006.173.07:14:50.41#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.07:14:50.41#ibcon#[25=USB\r\n] 2006.173.07:14:50.41#ibcon#*before write, iclass 19, count 0 2006.173.07:14:50.41#ibcon#enter sib2, iclass 19, count 0 2006.173.07:14:50.41#ibcon#flushed, iclass 19, count 0 2006.173.07:14:50.41#ibcon#about to write, iclass 19, count 0 2006.173.07:14:50.41#ibcon#wrote, iclass 19, count 0 2006.173.07:14:50.41#ibcon#about to read 3, iclass 19, count 0 2006.173.07:14:50.44#ibcon#read 3, iclass 19, count 0 2006.173.07:14:50.44#ibcon#about to read 4, iclass 19, count 0 2006.173.07:14:50.44#ibcon#read 4, iclass 19, count 0 2006.173.07:14:50.44#ibcon#about to read 5, iclass 19, count 0 2006.173.07:14:50.44#ibcon#read 5, iclass 19, count 0 2006.173.07:14:50.44#ibcon#about to read 6, iclass 19, count 0 2006.173.07:14:50.44#ibcon#read 6, iclass 19, count 0 2006.173.07:14:50.44#ibcon#end of sib2, iclass 19, count 0 2006.173.07:14:50.44#ibcon#*after write, iclass 19, count 0 2006.173.07:14:50.44#ibcon#*before return 0, iclass 19, count 0 2006.173.07:14:50.44#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.07:14:50.44#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.07:14:50.44#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.07:14:50.44#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.07:14:50.44$vck44/valo=5,734.99 2006.173.07:14:50.44#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.07:14:50.44#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.07:14:50.44#ibcon#ireg 17 cls_cnt 0 2006.173.07:14:50.44#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.07:14:50.44#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.07:14:50.44#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.07:14:50.44#ibcon#enter wrdev, iclass 21, count 0 2006.173.07:14:50.45#ibcon#first serial, iclass 21, count 0 2006.173.07:14:50.45#ibcon#enter sib2, iclass 21, count 0 2006.173.07:14:50.45#ibcon#flushed, iclass 21, count 0 2006.173.07:14:50.45#ibcon#about to write, iclass 21, count 0 2006.173.07:14:50.45#ibcon#wrote, iclass 21, count 0 2006.173.07:14:50.45#ibcon#about to read 3, iclass 21, count 0 2006.173.07:14:50.46#ibcon#read 3, iclass 21, count 0 2006.173.07:14:50.46#ibcon#about to read 4, iclass 21, count 0 2006.173.07:14:50.46#ibcon#read 4, iclass 21, count 0 2006.173.07:14:50.46#ibcon#about to read 5, iclass 21, count 0 2006.173.07:14:50.46#ibcon#read 5, iclass 21, count 0 2006.173.07:14:50.46#ibcon#about to read 6, iclass 21, count 0 2006.173.07:14:50.46#ibcon#read 6, iclass 21, count 0 2006.173.07:14:50.46#ibcon#end of sib2, iclass 21, count 0 2006.173.07:14:50.46#ibcon#*mode == 0, iclass 21, count 0 2006.173.07:14:50.46#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.07:14:50.46#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.07:14:50.46#ibcon#*before write, iclass 21, count 0 2006.173.07:14:50.46#ibcon#enter sib2, iclass 21, count 0 2006.173.07:14:50.46#ibcon#flushed, iclass 21, count 0 2006.173.07:14:50.46#ibcon#about to write, iclass 21, count 0 2006.173.07:14:50.46#ibcon#wrote, iclass 21, count 0 2006.173.07:14:50.46#ibcon#about to read 3, iclass 21, count 0 2006.173.07:14:50.50#ibcon#read 3, iclass 21, count 0 2006.173.07:14:50.50#ibcon#about to read 4, iclass 21, count 0 2006.173.07:14:50.50#ibcon#read 4, iclass 21, count 0 2006.173.07:14:50.50#ibcon#about to read 5, iclass 21, count 0 2006.173.07:14:50.50#ibcon#read 5, iclass 21, count 0 2006.173.07:14:50.50#ibcon#about to read 6, iclass 21, count 0 2006.173.07:14:50.50#ibcon#read 6, iclass 21, count 0 2006.173.07:14:50.50#ibcon#end of sib2, iclass 21, count 0 2006.173.07:14:50.50#ibcon#*after write, iclass 21, count 0 2006.173.07:14:50.50#ibcon#*before return 0, iclass 21, count 0 2006.173.07:14:50.50#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.07:14:50.50#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.07:14:50.50#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.07:14:50.50#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.07:14:50.50$vck44/va=5,4 2006.173.07:14:50.50#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.07:14:50.50#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.07:14:50.50#ibcon#ireg 11 cls_cnt 2 2006.173.07:14:50.50#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.07:14:50.56#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.07:14:50.56#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.07:14:50.56#ibcon#enter wrdev, iclass 23, count 2 2006.173.07:14:50.56#ibcon#first serial, iclass 23, count 2 2006.173.07:14:50.56#ibcon#enter sib2, iclass 23, count 2 2006.173.07:14:50.56#ibcon#flushed, iclass 23, count 2 2006.173.07:14:50.69#ibcon#about to write, iclass 23, count 2 2006.173.07:14:50.69#ibcon#wrote, iclass 23, count 2 2006.173.07:14:50.69#ibcon#about to read 3, iclass 23, count 2 2006.173.07:14:50.70#ibcon#read 3, iclass 23, count 2 2006.173.07:14:50.70#ibcon#about to read 4, iclass 23, count 2 2006.173.07:14:50.70#ibcon#read 4, iclass 23, count 2 2006.173.07:14:50.70#ibcon#about to read 5, iclass 23, count 2 2006.173.07:14:50.70#ibcon#read 5, iclass 23, count 2 2006.173.07:14:50.70#ibcon#about to read 6, iclass 23, count 2 2006.173.07:14:50.71#ibcon#read 6, iclass 23, count 2 2006.173.07:14:50.71#ibcon#end of sib2, iclass 23, count 2 2006.173.07:14:50.71#ibcon#*mode == 0, iclass 23, count 2 2006.173.07:14:50.71#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.07:14:50.71#ibcon#[25=AT05-04\r\n] 2006.173.07:14:50.71#ibcon#*before write, iclass 23, count 2 2006.173.07:14:50.71#ibcon#enter sib2, iclass 23, count 2 2006.173.07:14:50.71#ibcon#flushed, iclass 23, count 2 2006.173.07:14:50.71#ibcon#about to write, iclass 23, count 2 2006.173.07:14:50.71#ibcon#wrote, iclass 23, count 2 2006.173.07:14:50.71#ibcon#about to read 3, iclass 23, count 2 2006.173.07:14:50.74#ibcon#read 3, iclass 23, count 2 2006.173.07:14:50.74#ibcon#about to read 4, iclass 23, count 2 2006.173.07:14:50.74#ibcon#read 4, iclass 23, count 2 2006.173.07:14:50.74#ibcon#about to read 5, iclass 23, count 2 2006.173.07:14:50.74#ibcon#read 5, iclass 23, count 2 2006.173.07:14:50.74#ibcon#about to read 6, iclass 23, count 2 2006.173.07:14:50.74#ibcon#read 6, iclass 23, count 2 2006.173.07:14:50.74#ibcon#end of sib2, iclass 23, count 2 2006.173.07:14:50.74#ibcon#*after write, iclass 23, count 2 2006.173.07:14:50.74#ibcon#*before return 0, iclass 23, count 2 2006.173.07:14:50.74#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.07:14:50.74#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.07:14:50.74#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.07:14:50.74#ibcon#ireg 7 cls_cnt 0 2006.173.07:14:50.74#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.07:14:50.86#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.07:14:50.86#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.07:14:50.86#ibcon#enter wrdev, iclass 23, count 0 2006.173.07:14:50.86#ibcon#first serial, iclass 23, count 0 2006.173.07:14:50.86#ibcon#enter sib2, iclass 23, count 0 2006.173.07:14:50.86#ibcon#flushed, iclass 23, count 0 2006.173.07:14:50.86#ibcon#about to write, iclass 23, count 0 2006.173.07:14:50.86#ibcon#wrote, iclass 23, count 0 2006.173.07:14:50.86#ibcon#about to read 3, iclass 23, count 0 2006.173.07:14:50.88#ibcon#read 3, iclass 23, count 0 2006.173.07:14:50.88#ibcon#about to read 4, iclass 23, count 0 2006.173.07:14:50.88#ibcon#read 4, iclass 23, count 0 2006.173.07:14:50.88#ibcon#about to read 5, iclass 23, count 0 2006.173.07:14:50.88#ibcon#read 5, iclass 23, count 0 2006.173.07:14:50.88#ibcon#about to read 6, iclass 23, count 0 2006.173.07:14:50.88#ibcon#read 6, iclass 23, count 0 2006.173.07:14:50.88#ibcon#end of sib2, iclass 23, count 0 2006.173.07:14:50.88#ibcon#*mode == 0, iclass 23, count 0 2006.173.07:14:50.88#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.07:14:50.88#ibcon#[25=USB\r\n] 2006.173.07:14:50.88#ibcon#*before write, iclass 23, count 0 2006.173.07:14:50.88#ibcon#enter sib2, iclass 23, count 0 2006.173.07:14:50.88#ibcon#flushed, iclass 23, count 0 2006.173.07:14:50.88#ibcon#about to write, iclass 23, count 0 2006.173.07:14:50.88#ibcon#wrote, iclass 23, count 0 2006.173.07:14:50.88#ibcon#about to read 3, iclass 23, count 0 2006.173.07:14:50.91#ibcon#read 3, iclass 23, count 0 2006.173.07:14:50.91#ibcon#about to read 4, iclass 23, count 0 2006.173.07:14:50.91#ibcon#read 4, iclass 23, count 0 2006.173.07:14:50.91#ibcon#about to read 5, iclass 23, count 0 2006.173.07:14:50.91#ibcon#read 5, iclass 23, count 0 2006.173.07:14:50.91#ibcon#about to read 6, iclass 23, count 0 2006.173.07:14:50.91#ibcon#read 6, iclass 23, count 0 2006.173.07:14:50.91#ibcon#end of sib2, iclass 23, count 0 2006.173.07:14:50.91#ibcon#*after write, iclass 23, count 0 2006.173.07:14:50.91#ibcon#*before return 0, iclass 23, count 0 2006.173.07:14:50.91#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.07:14:50.91#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.07:14:50.91#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.07:14:50.91#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.07:14:50.91$vck44/valo=6,814.99 2006.173.07:14:50.91#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.07:14:50.91#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.07:14:50.91#ibcon#ireg 17 cls_cnt 0 2006.173.07:14:50.91#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.07:14:50.91#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.07:14:50.91#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.07:14:50.91#ibcon#enter wrdev, iclass 25, count 0 2006.173.07:14:50.91#ibcon#first serial, iclass 25, count 0 2006.173.07:14:50.91#ibcon#enter sib2, iclass 25, count 0 2006.173.07:14:50.92#ibcon#flushed, iclass 25, count 0 2006.173.07:14:50.92#ibcon#about to write, iclass 25, count 0 2006.173.07:14:50.92#ibcon#wrote, iclass 25, count 0 2006.173.07:14:50.92#ibcon#about to read 3, iclass 25, count 0 2006.173.07:14:50.93#ibcon#read 3, iclass 25, count 0 2006.173.07:14:50.93#ibcon#about to read 4, iclass 25, count 0 2006.173.07:14:50.93#ibcon#read 4, iclass 25, count 0 2006.173.07:14:50.93#ibcon#about to read 5, iclass 25, count 0 2006.173.07:14:50.93#ibcon#read 5, iclass 25, count 0 2006.173.07:14:50.93#ibcon#about to read 6, iclass 25, count 0 2006.173.07:14:50.93#ibcon#read 6, iclass 25, count 0 2006.173.07:14:50.93#ibcon#end of sib2, iclass 25, count 0 2006.173.07:14:50.93#ibcon#*mode == 0, iclass 25, count 0 2006.173.07:14:50.93#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.07:14:50.93#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.07:14:50.93#ibcon#*before write, iclass 25, count 0 2006.173.07:14:50.93#ibcon#enter sib2, iclass 25, count 0 2006.173.07:14:50.93#ibcon#flushed, iclass 25, count 0 2006.173.07:14:50.93#ibcon#about to write, iclass 25, count 0 2006.173.07:14:50.93#ibcon#wrote, iclass 25, count 0 2006.173.07:14:50.93#ibcon#about to read 3, iclass 25, count 0 2006.173.07:14:50.97#ibcon#read 3, iclass 25, count 0 2006.173.07:14:50.97#ibcon#about to read 4, iclass 25, count 0 2006.173.07:14:50.97#ibcon#read 4, iclass 25, count 0 2006.173.07:14:50.97#ibcon#about to read 5, iclass 25, count 0 2006.173.07:14:50.97#ibcon#read 5, iclass 25, count 0 2006.173.07:14:50.97#ibcon#about to read 6, iclass 25, count 0 2006.173.07:14:50.97#ibcon#read 6, iclass 25, count 0 2006.173.07:14:50.97#ibcon#end of sib2, iclass 25, count 0 2006.173.07:14:50.97#ibcon#*after write, iclass 25, count 0 2006.173.07:14:50.97#ibcon#*before return 0, iclass 25, count 0 2006.173.07:14:50.97#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.07:14:50.97#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.07:14:50.97#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.07:14:50.97#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.07:14:50.97$vck44/va=6,3 2006.173.07:14:50.97#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.07:14:50.97#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.07:14:50.97#ibcon#ireg 11 cls_cnt 2 2006.173.07:14:50.97#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.07:14:51.03#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.07:14:51.03#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.07:14:51.03#ibcon#enter wrdev, iclass 27, count 2 2006.173.07:14:51.03#ibcon#first serial, iclass 27, count 2 2006.173.07:14:51.03#ibcon#enter sib2, iclass 27, count 2 2006.173.07:14:51.03#ibcon#flushed, iclass 27, count 2 2006.173.07:14:51.03#ibcon#about to write, iclass 27, count 2 2006.173.07:14:51.03#ibcon#wrote, iclass 27, count 2 2006.173.07:14:51.03#ibcon#about to read 3, iclass 27, count 2 2006.173.07:14:51.05#ibcon#read 3, iclass 27, count 2 2006.173.07:14:51.05#ibcon#about to read 4, iclass 27, count 2 2006.173.07:14:51.05#ibcon#read 4, iclass 27, count 2 2006.173.07:14:51.05#ibcon#about to read 5, iclass 27, count 2 2006.173.07:14:51.05#ibcon#read 5, iclass 27, count 2 2006.173.07:14:51.05#ibcon#about to read 6, iclass 27, count 2 2006.173.07:14:51.05#ibcon#read 6, iclass 27, count 2 2006.173.07:14:51.05#ibcon#end of sib2, iclass 27, count 2 2006.173.07:14:51.05#ibcon#*mode == 0, iclass 27, count 2 2006.173.07:14:51.05#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.07:14:51.05#ibcon#[25=AT06-03\r\n] 2006.173.07:14:51.05#ibcon#*before write, iclass 27, count 2 2006.173.07:14:51.05#ibcon#enter sib2, iclass 27, count 2 2006.173.07:14:51.05#ibcon#flushed, iclass 27, count 2 2006.173.07:14:51.05#ibcon#about to write, iclass 27, count 2 2006.173.07:14:51.05#ibcon#wrote, iclass 27, count 2 2006.173.07:14:51.05#ibcon#about to read 3, iclass 27, count 2 2006.173.07:14:51.08#ibcon#read 3, iclass 27, count 2 2006.173.07:14:51.08#ibcon#about to read 4, iclass 27, count 2 2006.173.07:14:51.08#ibcon#read 4, iclass 27, count 2 2006.173.07:14:51.08#ibcon#about to read 5, iclass 27, count 2 2006.173.07:14:51.08#ibcon#read 5, iclass 27, count 2 2006.173.07:14:51.08#ibcon#about to read 6, iclass 27, count 2 2006.173.07:14:51.08#ibcon#read 6, iclass 27, count 2 2006.173.07:14:51.08#ibcon#end of sib2, iclass 27, count 2 2006.173.07:14:51.08#ibcon#*after write, iclass 27, count 2 2006.173.07:14:51.08#ibcon#*before return 0, iclass 27, count 2 2006.173.07:14:51.08#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.07:14:51.08#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.07:14:51.08#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.07:14:51.08#ibcon#ireg 7 cls_cnt 0 2006.173.07:14:51.08#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.07:14:51.20#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.07:14:51.20#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.07:14:51.20#ibcon#enter wrdev, iclass 27, count 0 2006.173.07:14:51.20#ibcon#first serial, iclass 27, count 0 2006.173.07:14:51.20#ibcon#enter sib2, iclass 27, count 0 2006.173.07:14:51.20#ibcon#flushed, iclass 27, count 0 2006.173.07:14:51.20#ibcon#about to write, iclass 27, count 0 2006.173.07:14:51.20#ibcon#wrote, iclass 27, count 0 2006.173.07:14:51.20#ibcon#about to read 3, iclass 27, count 0 2006.173.07:14:51.22#ibcon#read 3, iclass 27, count 0 2006.173.07:14:51.22#ibcon#about to read 4, iclass 27, count 0 2006.173.07:14:51.22#ibcon#read 4, iclass 27, count 0 2006.173.07:14:51.22#ibcon#about to read 5, iclass 27, count 0 2006.173.07:14:51.22#ibcon#read 5, iclass 27, count 0 2006.173.07:14:51.22#ibcon#about to read 6, iclass 27, count 0 2006.173.07:14:51.22#ibcon#read 6, iclass 27, count 0 2006.173.07:14:51.22#ibcon#end of sib2, iclass 27, count 0 2006.173.07:14:51.22#ibcon#*mode == 0, iclass 27, count 0 2006.173.07:14:51.22#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.07:14:51.22#ibcon#[25=USB\r\n] 2006.173.07:14:51.22#ibcon#*before write, iclass 27, count 0 2006.173.07:14:51.22#ibcon#enter sib2, iclass 27, count 0 2006.173.07:14:51.22#ibcon#flushed, iclass 27, count 0 2006.173.07:14:51.22#ibcon#about to write, iclass 27, count 0 2006.173.07:14:51.22#ibcon#wrote, iclass 27, count 0 2006.173.07:14:51.22#ibcon#about to read 3, iclass 27, count 0 2006.173.07:14:51.25#ibcon#read 3, iclass 27, count 0 2006.173.07:14:51.25#ibcon#about to read 4, iclass 27, count 0 2006.173.07:14:51.25#ibcon#read 4, iclass 27, count 0 2006.173.07:14:51.25#ibcon#about to read 5, iclass 27, count 0 2006.173.07:14:51.25#ibcon#read 5, iclass 27, count 0 2006.173.07:14:51.25#ibcon#about to read 6, iclass 27, count 0 2006.173.07:14:51.25#ibcon#read 6, iclass 27, count 0 2006.173.07:14:51.25#ibcon#end of sib2, iclass 27, count 0 2006.173.07:14:51.25#ibcon#*after write, iclass 27, count 0 2006.173.07:14:51.25#ibcon#*before return 0, iclass 27, count 0 2006.173.07:14:51.25#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.07:14:51.25#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.07:14:51.25#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.07:14:51.25#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.07:14:51.25$vck44/valo=7,864.99 2006.173.07:14:51.25#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.07:14:51.25#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.07:14:51.25#ibcon#ireg 17 cls_cnt 0 2006.173.07:14:51.25#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.07:14:51.25#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.07:14:51.25#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.07:14:51.25#ibcon#enter wrdev, iclass 29, count 0 2006.173.07:14:51.26#ibcon#first serial, iclass 29, count 0 2006.173.07:14:51.26#ibcon#enter sib2, iclass 29, count 0 2006.173.07:14:51.26#ibcon#flushed, iclass 29, count 0 2006.173.07:14:51.26#ibcon#about to write, iclass 29, count 0 2006.173.07:14:51.26#ibcon#wrote, iclass 29, count 0 2006.173.07:14:51.26#ibcon#about to read 3, iclass 29, count 0 2006.173.07:14:51.27#ibcon#read 3, iclass 29, count 0 2006.173.07:14:51.27#ibcon#about to read 4, iclass 29, count 0 2006.173.07:14:51.27#ibcon#read 4, iclass 29, count 0 2006.173.07:14:51.27#ibcon#about to read 5, iclass 29, count 0 2006.173.07:14:51.27#ibcon#read 5, iclass 29, count 0 2006.173.07:14:51.27#ibcon#about to read 6, iclass 29, count 0 2006.173.07:14:51.27#ibcon#read 6, iclass 29, count 0 2006.173.07:14:51.27#ibcon#end of sib2, iclass 29, count 0 2006.173.07:14:51.27#ibcon#*mode == 0, iclass 29, count 0 2006.173.07:14:51.27#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.07:14:51.27#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.07:14:51.27#ibcon#*before write, iclass 29, count 0 2006.173.07:14:51.27#ibcon#enter sib2, iclass 29, count 0 2006.173.07:14:51.27#ibcon#flushed, iclass 29, count 0 2006.173.07:14:51.27#ibcon#about to write, iclass 29, count 0 2006.173.07:14:51.27#ibcon#wrote, iclass 29, count 0 2006.173.07:14:51.27#ibcon#about to read 3, iclass 29, count 0 2006.173.07:14:51.31#ibcon#read 3, iclass 29, count 0 2006.173.07:14:51.31#ibcon#about to read 4, iclass 29, count 0 2006.173.07:14:51.31#ibcon#read 4, iclass 29, count 0 2006.173.07:14:51.31#ibcon#about to read 5, iclass 29, count 0 2006.173.07:14:51.31#ibcon#read 5, iclass 29, count 0 2006.173.07:14:51.31#ibcon#about to read 6, iclass 29, count 0 2006.173.07:14:51.31#ibcon#read 6, iclass 29, count 0 2006.173.07:14:51.31#ibcon#end of sib2, iclass 29, count 0 2006.173.07:14:51.31#ibcon#*after write, iclass 29, count 0 2006.173.07:14:51.31#ibcon#*before return 0, iclass 29, count 0 2006.173.07:14:51.31#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.07:14:51.31#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.07:14:51.31#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.07:14:51.31#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.07:14:51.31$vck44/va=7,4 2006.173.07:14:51.31#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.07:14:51.31#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.07:14:51.31#ibcon#ireg 11 cls_cnt 2 2006.173.07:14:51.31#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.07:14:51.37#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.07:14:51.37#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.07:14:51.37#ibcon#enter wrdev, iclass 31, count 2 2006.173.07:14:51.37#ibcon#first serial, iclass 31, count 2 2006.173.07:14:51.37#ibcon#enter sib2, iclass 31, count 2 2006.173.07:14:51.37#ibcon#flushed, iclass 31, count 2 2006.173.07:14:51.37#ibcon#about to write, iclass 31, count 2 2006.173.07:14:51.37#ibcon#wrote, iclass 31, count 2 2006.173.07:14:51.37#ibcon#about to read 3, iclass 31, count 2 2006.173.07:14:51.39#ibcon#read 3, iclass 31, count 2 2006.173.07:14:51.39#ibcon#about to read 4, iclass 31, count 2 2006.173.07:14:51.39#ibcon#read 4, iclass 31, count 2 2006.173.07:14:51.39#ibcon#about to read 5, iclass 31, count 2 2006.173.07:14:51.39#ibcon#read 5, iclass 31, count 2 2006.173.07:14:51.39#ibcon#about to read 6, iclass 31, count 2 2006.173.07:14:51.39#ibcon#read 6, iclass 31, count 2 2006.173.07:14:51.39#ibcon#end of sib2, iclass 31, count 2 2006.173.07:14:51.39#ibcon#*mode == 0, iclass 31, count 2 2006.173.07:14:51.39#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.07:14:51.39#ibcon#[25=AT07-04\r\n] 2006.173.07:14:51.39#ibcon#*before write, iclass 31, count 2 2006.173.07:14:51.39#ibcon#enter sib2, iclass 31, count 2 2006.173.07:14:51.39#ibcon#flushed, iclass 31, count 2 2006.173.07:14:51.39#ibcon#about to write, iclass 31, count 2 2006.173.07:14:51.39#ibcon#wrote, iclass 31, count 2 2006.173.07:14:51.39#ibcon#about to read 3, iclass 31, count 2 2006.173.07:14:51.42#ibcon#read 3, iclass 31, count 2 2006.173.07:14:51.42#ibcon#about to read 4, iclass 31, count 2 2006.173.07:14:51.42#ibcon#read 4, iclass 31, count 2 2006.173.07:14:51.42#ibcon#about to read 5, iclass 31, count 2 2006.173.07:14:51.42#ibcon#read 5, iclass 31, count 2 2006.173.07:14:51.42#ibcon#about to read 6, iclass 31, count 2 2006.173.07:14:51.42#ibcon#read 6, iclass 31, count 2 2006.173.07:14:51.42#ibcon#end of sib2, iclass 31, count 2 2006.173.07:14:51.42#ibcon#*after write, iclass 31, count 2 2006.173.07:14:51.42#ibcon#*before return 0, iclass 31, count 2 2006.173.07:14:51.42#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.07:14:51.42#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.07:14:51.42#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.07:14:51.42#ibcon#ireg 7 cls_cnt 0 2006.173.07:14:51.42#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.07:14:51.54#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.07:14:51.54#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.07:14:51.54#ibcon#enter wrdev, iclass 31, count 0 2006.173.07:14:51.54#ibcon#first serial, iclass 31, count 0 2006.173.07:14:51.54#ibcon#enter sib2, iclass 31, count 0 2006.173.07:14:51.54#ibcon#flushed, iclass 31, count 0 2006.173.07:14:51.54#ibcon#about to write, iclass 31, count 0 2006.173.07:14:51.54#ibcon#wrote, iclass 31, count 0 2006.173.07:14:51.54#ibcon#about to read 3, iclass 31, count 0 2006.173.07:14:51.56#ibcon#read 3, iclass 31, count 0 2006.173.07:14:51.56#ibcon#about to read 4, iclass 31, count 0 2006.173.07:14:51.56#ibcon#read 4, iclass 31, count 0 2006.173.07:14:51.56#ibcon#about to read 5, iclass 31, count 0 2006.173.07:14:51.56#ibcon#read 5, iclass 31, count 0 2006.173.07:14:51.56#ibcon#about to read 6, iclass 31, count 0 2006.173.07:14:51.56#ibcon#read 6, iclass 31, count 0 2006.173.07:14:51.56#ibcon#end of sib2, iclass 31, count 0 2006.173.07:14:51.56#ibcon#*mode == 0, iclass 31, count 0 2006.173.07:14:51.56#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.07:14:51.56#ibcon#[25=USB\r\n] 2006.173.07:14:51.56#ibcon#*before write, iclass 31, count 0 2006.173.07:14:51.56#ibcon#enter sib2, iclass 31, count 0 2006.173.07:14:51.56#ibcon#flushed, iclass 31, count 0 2006.173.07:14:51.56#ibcon#about to write, iclass 31, count 0 2006.173.07:14:51.56#ibcon#wrote, iclass 31, count 0 2006.173.07:14:51.56#ibcon#about to read 3, iclass 31, count 0 2006.173.07:14:51.59#ibcon#read 3, iclass 31, count 0 2006.173.07:14:51.59#ibcon#about to read 4, iclass 31, count 0 2006.173.07:14:51.59#ibcon#read 4, iclass 31, count 0 2006.173.07:14:51.59#ibcon#about to read 5, iclass 31, count 0 2006.173.07:14:51.59#ibcon#read 5, iclass 31, count 0 2006.173.07:14:51.59#ibcon#about to read 6, iclass 31, count 0 2006.173.07:14:51.59#ibcon#read 6, iclass 31, count 0 2006.173.07:14:51.59#ibcon#end of sib2, iclass 31, count 0 2006.173.07:14:51.59#ibcon#*after write, iclass 31, count 0 2006.173.07:14:51.59#ibcon#*before return 0, iclass 31, count 0 2006.173.07:14:51.59#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.07:14:51.59#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.07:14:51.59#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.07:14:51.59#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.07:14:51.59$vck44/valo=8,884.99 2006.173.07:14:51.59#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.07:14:51.59#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.07:14:51.59#ibcon#ireg 17 cls_cnt 0 2006.173.07:14:51.59#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.07:14:51.59#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.07:14:51.59#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.07:14:51.59#ibcon#enter wrdev, iclass 33, count 0 2006.173.07:14:51.59#ibcon#first serial, iclass 33, count 0 2006.173.07:14:51.59#ibcon#enter sib2, iclass 33, count 0 2006.173.07:14:51.59#ibcon#flushed, iclass 33, count 0 2006.173.07:14:51.59#ibcon#about to write, iclass 33, count 0 2006.173.07:14:51.60#ibcon#wrote, iclass 33, count 0 2006.173.07:14:51.60#ibcon#about to read 3, iclass 33, count 0 2006.173.07:14:51.61#ibcon#read 3, iclass 33, count 0 2006.173.07:14:51.61#ibcon#about to read 4, iclass 33, count 0 2006.173.07:14:51.61#ibcon#read 4, iclass 33, count 0 2006.173.07:14:51.61#ibcon#about to read 5, iclass 33, count 0 2006.173.07:14:51.61#ibcon#read 5, iclass 33, count 0 2006.173.07:14:51.61#ibcon#about to read 6, iclass 33, count 0 2006.173.07:14:51.61#ibcon#read 6, iclass 33, count 0 2006.173.07:14:51.61#ibcon#end of sib2, iclass 33, count 0 2006.173.07:14:51.61#ibcon#*mode == 0, iclass 33, count 0 2006.173.07:14:51.61#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.07:14:51.61#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.07:14:51.61#ibcon#*before write, iclass 33, count 0 2006.173.07:14:51.61#ibcon#enter sib2, iclass 33, count 0 2006.173.07:14:51.61#ibcon#flushed, iclass 33, count 0 2006.173.07:14:51.61#ibcon#about to write, iclass 33, count 0 2006.173.07:14:51.61#ibcon#wrote, iclass 33, count 0 2006.173.07:14:51.61#ibcon#about to read 3, iclass 33, count 0 2006.173.07:14:51.65#ibcon#read 3, iclass 33, count 0 2006.173.07:14:51.65#ibcon#about to read 4, iclass 33, count 0 2006.173.07:14:51.65#ibcon#read 4, iclass 33, count 0 2006.173.07:14:51.65#ibcon#about to read 5, iclass 33, count 0 2006.173.07:14:51.65#ibcon#read 5, iclass 33, count 0 2006.173.07:14:51.65#ibcon#about to read 6, iclass 33, count 0 2006.173.07:14:51.65#ibcon#read 6, iclass 33, count 0 2006.173.07:14:51.65#ibcon#end of sib2, iclass 33, count 0 2006.173.07:14:51.65#ibcon#*after write, iclass 33, count 0 2006.173.07:14:51.65#ibcon#*before return 0, iclass 33, count 0 2006.173.07:14:51.65#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.07:14:51.65#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.07:14:51.65#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.07:14:51.65#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.07:14:51.65$vck44/va=8,4 2006.173.07:14:51.65#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.07:14:51.65#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.07:14:51.65#ibcon#ireg 11 cls_cnt 2 2006.173.07:14:51.65#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.07:14:51.71#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.07:14:51.71#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.07:14:51.71#ibcon#enter wrdev, iclass 35, count 2 2006.173.07:14:51.71#ibcon#first serial, iclass 35, count 2 2006.173.07:14:51.71#ibcon#enter sib2, iclass 35, count 2 2006.173.07:14:51.71#ibcon#flushed, iclass 35, count 2 2006.173.07:14:51.71#ibcon#about to write, iclass 35, count 2 2006.173.07:14:51.71#ibcon#wrote, iclass 35, count 2 2006.173.07:14:51.71#ibcon#about to read 3, iclass 35, count 2 2006.173.07:14:51.73#ibcon#read 3, iclass 35, count 2 2006.173.07:14:51.73#ibcon#about to read 4, iclass 35, count 2 2006.173.07:14:51.73#ibcon#read 4, iclass 35, count 2 2006.173.07:14:51.73#ibcon#about to read 5, iclass 35, count 2 2006.173.07:14:51.73#ibcon#read 5, iclass 35, count 2 2006.173.07:14:51.73#ibcon#about to read 6, iclass 35, count 2 2006.173.07:14:51.73#ibcon#read 6, iclass 35, count 2 2006.173.07:14:51.73#ibcon#end of sib2, iclass 35, count 2 2006.173.07:14:51.73#ibcon#*mode == 0, iclass 35, count 2 2006.173.07:14:51.73#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.07:14:51.73#ibcon#[25=AT08-04\r\n] 2006.173.07:14:51.73#ibcon#*before write, iclass 35, count 2 2006.173.07:14:51.73#ibcon#enter sib2, iclass 35, count 2 2006.173.07:14:51.73#ibcon#flushed, iclass 35, count 2 2006.173.07:14:51.73#ibcon#about to write, iclass 35, count 2 2006.173.07:14:51.73#ibcon#wrote, iclass 35, count 2 2006.173.07:14:51.73#ibcon#about to read 3, iclass 35, count 2 2006.173.07:14:51.76#ibcon#read 3, iclass 35, count 2 2006.173.07:14:51.76#ibcon#about to read 4, iclass 35, count 2 2006.173.07:14:51.76#ibcon#read 4, iclass 35, count 2 2006.173.07:14:51.76#ibcon#about to read 5, iclass 35, count 2 2006.173.07:14:51.76#ibcon#read 5, iclass 35, count 2 2006.173.07:14:51.76#ibcon#about to read 6, iclass 35, count 2 2006.173.07:14:51.76#ibcon#read 6, iclass 35, count 2 2006.173.07:14:51.76#ibcon#end of sib2, iclass 35, count 2 2006.173.07:14:51.76#ibcon#*after write, iclass 35, count 2 2006.173.07:14:51.76#ibcon#*before return 0, iclass 35, count 2 2006.173.07:14:51.76#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.07:14:51.76#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.07:14:51.76#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.07:14:51.76#ibcon#ireg 7 cls_cnt 0 2006.173.07:14:51.76#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.07:14:51.88#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.07:14:51.88#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.07:14:51.88#ibcon#enter wrdev, iclass 35, count 0 2006.173.07:14:51.88#ibcon#first serial, iclass 35, count 0 2006.173.07:14:51.88#ibcon#enter sib2, iclass 35, count 0 2006.173.07:14:51.88#ibcon#flushed, iclass 35, count 0 2006.173.07:14:51.88#ibcon#about to write, iclass 35, count 0 2006.173.07:14:51.88#ibcon#wrote, iclass 35, count 0 2006.173.07:14:51.88#ibcon#about to read 3, iclass 35, count 0 2006.173.07:14:51.90#ibcon#read 3, iclass 35, count 0 2006.173.07:14:51.90#ibcon#about to read 4, iclass 35, count 0 2006.173.07:14:51.90#ibcon#read 4, iclass 35, count 0 2006.173.07:14:51.90#ibcon#about to read 5, iclass 35, count 0 2006.173.07:14:51.90#ibcon#read 5, iclass 35, count 0 2006.173.07:14:51.90#ibcon#about to read 6, iclass 35, count 0 2006.173.07:14:51.90#ibcon#read 6, iclass 35, count 0 2006.173.07:14:51.90#ibcon#end of sib2, iclass 35, count 0 2006.173.07:14:51.90#ibcon#*mode == 0, iclass 35, count 0 2006.173.07:14:51.90#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.07:14:51.90#ibcon#[25=USB\r\n] 2006.173.07:14:51.90#ibcon#*before write, iclass 35, count 0 2006.173.07:14:51.90#ibcon#enter sib2, iclass 35, count 0 2006.173.07:14:51.90#ibcon#flushed, iclass 35, count 0 2006.173.07:14:51.90#ibcon#about to write, iclass 35, count 0 2006.173.07:14:51.90#ibcon#wrote, iclass 35, count 0 2006.173.07:14:51.90#ibcon#about to read 3, iclass 35, count 0 2006.173.07:14:51.93#ibcon#read 3, iclass 35, count 0 2006.173.07:14:51.93#ibcon#about to read 4, iclass 35, count 0 2006.173.07:14:51.93#ibcon#read 4, iclass 35, count 0 2006.173.07:14:51.93#ibcon#about to read 5, iclass 35, count 0 2006.173.07:14:51.93#ibcon#read 5, iclass 35, count 0 2006.173.07:14:51.93#ibcon#about to read 6, iclass 35, count 0 2006.173.07:14:51.93#ibcon#read 6, iclass 35, count 0 2006.173.07:14:51.93#ibcon#end of sib2, iclass 35, count 0 2006.173.07:14:51.93#ibcon#*after write, iclass 35, count 0 2006.173.07:14:51.93#ibcon#*before return 0, iclass 35, count 0 2006.173.07:14:51.93#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.07:14:51.93#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.07:14:51.93#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.07:14:51.93#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.07:14:51.93$vck44/vblo=1,629.99 2006.173.07:14:51.93#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.07:14:51.93#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.07:14:51.93#ibcon#ireg 17 cls_cnt 0 2006.173.07:14:51.93#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.07:14:51.93#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.07:14:51.94#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.07:14:51.94#ibcon#enter wrdev, iclass 37, count 0 2006.173.07:14:51.94#ibcon#first serial, iclass 37, count 0 2006.173.07:14:51.94#ibcon#enter sib2, iclass 37, count 0 2006.173.07:14:51.94#ibcon#flushed, iclass 37, count 0 2006.173.07:14:51.94#ibcon#about to write, iclass 37, count 0 2006.173.07:14:51.94#ibcon#wrote, iclass 37, count 0 2006.173.07:14:51.94#ibcon#about to read 3, iclass 37, count 0 2006.173.07:14:51.95#ibcon#read 3, iclass 37, count 0 2006.173.07:14:51.95#ibcon#about to read 4, iclass 37, count 0 2006.173.07:14:51.95#ibcon#read 4, iclass 37, count 0 2006.173.07:14:51.95#ibcon#about to read 5, iclass 37, count 0 2006.173.07:14:51.95#ibcon#read 5, iclass 37, count 0 2006.173.07:14:51.95#ibcon#about to read 6, iclass 37, count 0 2006.173.07:14:51.95#ibcon#read 6, iclass 37, count 0 2006.173.07:14:51.95#ibcon#end of sib2, iclass 37, count 0 2006.173.07:14:51.95#ibcon#*mode == 0, iclass 37, count 0 2006.173.07:14:51.95#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.07:14:51.95#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.07:14:51.95#ibcon#*before write, iclass 37, count 0 2006.173.07:14:51.95#ibcon#enter sib2, iclass 37, count 0 2006.173.07:14:51.95#ibcon#flushed, iclass 37, count 0 2006.173.07:14:51.95#ibcon#about to write, iclass 37, count 0 2006.173.07:14:51.95#ibcon#wrote, iclass 37, count 0 2006.173.07:14:51.95#ibcon#about to read 3, iclass 37, count 0 2006.173.07:14:51.99#ibcon#read 3, iclass 37, count 0 2006.173.07:14:51.99#ibcon#about to read 4, iclass 37, count 0 2006.173.07:14:51.99#ibcon#read 4, iclass 37, count 0 2006.173.07:14:51.99#ibcon#about to read 5, iclass 37, count 0 2006.173.07:14:51.99#ibcon#read 5, iclass 37, count 0 2006.173.07:14:51.99#ibcon#about to read 6, iclass 37, count 0 2006.173.07:14:51.99#ibcon#read 6, iclass 37, count 0 2006.173.07:14:51.99#ibcon#end of sib2, iclass 37, count 0 2006.173.07:14:51.99#ibcon#*after write, iclass 37, count 0 2006.173.07:14:51.99#ibcon#*before return 0, iclass 37, count 0 2006.173.07:14:51.99#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.07:14:51.99#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.07:14:51.99#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.07:14:51.99#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.07:14:51.99$vck44/vb=1,4 2006.173.07:14:51.99#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.07:14:51.99#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.07:14:51.99#ibcon#ireg 11 cls_cnt 2 2006.173.07:14:51.99#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.07:14:51.99#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.07:14:51.99#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.07:14:51.99#ibcon#enter wrdev, iclass 39, count 2 2006.173.07:14:51.99#ibcon#first serial, iclass 39, count 2 2006.173.07:14:52.00#ibcon#enter sib2, iclass 39, count 2 2006.173.07:14:52.00#ibcon#flushed, iclass 39, count 2 2006.173.07:14:52.00#ibcon#about to write, iclass 39, count 2 2006.173.07:14:52.00#ibcon#wrote, iclass 39, count 2 2006.173.07:14:52.00#ibcon#about to read 3, iclass 39, count 2 2006.173.07:14:52.01#ibcon#read 3, iclass 39, count 2 2006.173.07:14:52.01#ibcon#about to read 4, iclass 39, count 2 2006.173.07:14:52.01#ibcon#read 4, iclass 39, count 2 2006.173.07:14:52.01#ibcon#about to read 5, iclass 39, count 2 2006.173.07:14:52.01#ibcon#read 5, iclass 39, count 2 2006.173.07:14:52.01#ibcon#about to read 6, iclass 39, count 2 2006.173.07:14:52.01#ibcon#read 6, iclass 39, count 2 2006.173.07:14:52.01#ibcon#end of sib2, iclass 39, count 2 2006.173.07:14:52.01#ibcon#*mode == 0, iclass 39, count 2 2006.173.07:14:52.01#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.07:14:52.01#ibcon#[27=AT01-04\r\n] 2006.173.07:14:52.01#ibcon#*before write, iclass 39, count 2 2006.173.07:14:52.01#ibcon#enter sib2, iclass 39, count 2 2006.173.07:14:52.01#ibcon#flushed, iclass 39, count 2 2006.173.07:14:52.01#ibcon#about to write, iclass 39, count 2 2006.173.07:14:52.01#ibcon#wrote, iclass 39, count 2 2006.173.07:14:52.01#ibcon#about to read 3, iclass 39, count 2 2006.173.07:14:52.04#ibcon#read 3, iclass 39, count 2 2006.173.07:14:52.04#ibcon#about to read 4, iclass 39, count 2 2006.173.07:14:52.04#ibcon#read 4, iclass 39, count 2 2006.173.07:14:52.04#ibcon#about to read 5, iclass 39, count 2 2006.173.07:14:52.04#ibcon#read 5, iclass 39, count 2 2006.173.07:14:52.04#ibcon#about to read 6, iclass 39, count 2 2006.173.07:14:52.04#ibcon#read 6, iclass 39, count 2 2006.173.07:14:52.04#ibcon#end of sib2, iclass 39, count 2 2006.173.07:14:52.04#ibcon#*after write, iclass 39, count 2 2006.173.07:14:52.04#ibcon#*before return 0, iclass 39, count 2 2006.173.07:14:52.04#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.07:14:52.04#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.07:14:52.04#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.07:14:52.04#ibcon#ireg 7 cls_cnt 0 2006.173.07:14:52.04#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.07:14:52.16#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.07:14:52.16#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.07:14:52.16#ibcon#enter wrdev, iclass 39, count 0 2006.173.07:14:52.16#ibcon#first serial, iclass 39, count 0 2006.173.07:14:52.16#ibcon#enter sib2, iclass 39, count 0 2006.173.07:14:52.16#ibcon#flushed, iclass 39, count 0 2006.173.07:14:52.16#ibcon#about to write, iclass 39, count 0 2006.173.07:14:52.16#ibcon#wrote, iclass 39, count 0 2006.173.07:14:52.16#ibcon#about to read 3, iclass 39, count 0 2006.173.07:14:52.18#ibcon#read 3, iclass 39, count 0 2006.173.07:14:52.18#ibcon#about to read 4, iclass 39, count 0 2006.173.07:14:52.18#ibcon#read 4, iclass 39, count 0 2006.173.07:14:52.18#ibcon#about to read 5, iclass 39, count 0 2006.173.07:14:52.18#ibcon#read 5, iclass 39, count 0 2006.173.07:14:52.18#ibcon#about to read 6, iclass 39, count 0 2006.173.07:14:52.18#ibcon#read 6, iclass 39, count 0 2006.173.07:14:52.18#ibcon#end of sib2, iclass 39, count 0 2006.173.07:14:52.18#ibcon#*mode == 0, iclass 39, count 0 2006.173.07:14:52.18#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.07:14:52.18#ibcon#[27=USB\r\n] 2006.173.07:14:52.18#ibcon#*before write, iclass 39, count 0 2006.173.07:14:52.18#ibcon#enter sib2, iclass 39, count 0 2006.173.07:14:52.18#ibcon#flushed, iclass 39, count 0 2006.173.07:14:52.18#ibcon#about to write, iclass 39, count 0 2006.173.07:14:52.18#ibcon#wrote, iclass 39, count 0 2006.173.07:14:52.18#ibcon#about to read 3, iclass 39, count 0 2006.173.07:14:52.21#ibcon#read 3, iclass 39, count 0 2006.173.07:14:52.21#ibcon#about to read 4, iclass 39, count 0 2006.173.07:14:52.21#ibcon#read 4, iclass 39, count 0 2006.173.07:14:52.21#ibcon#about to read 5, iclass 39, count 0 2006.173.07:14:52.21#ibcon#read 5, iclass 39, count 0 2006.173.07:14:52.21#ibcon#about to read 6, iclass 39, count 0 2006.173.07:14:52.21#ibcon#read 6, iclass 39, count 0 2006.173.07:14:52.21#ibcon#end of sib2, iclass 39, count 0 2006.173.07:14:52.21#ibcon#*after write, iclass 39, count 0 2006.173.07:14:52.21#ibcon#*before return 0, iclass 39, count 0 2006.173.07:14:52.21#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.07:14:52.21#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.07:14:52.21#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.07:14:52.21#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.07:14:52.21$vck44/vblo=2,634.99 2006.173.07:14:52.21#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.07:14:52.21#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.07:14:52.21#ibcon#ireg 17 cls_cnt 0 2006.173.07:14:52.21#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.07:14:52.21#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.07:14:52.21#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.07:14:52.21#ibcon#enter wrdev, iclass 3, count 0 2006.173.07:14:52.22#ibcon#first serial, iclass 3, count 0 2006.173.07:14:52.22#ibcon#enter sib2, iclass 3, count 0 2006.173.07:14:52.22#ibcon#flushed, iclass 3, count 0 2006.173.07:14:52.22#ibcon#about to write, iclass 3, count 0 2006.173.07:14:52.22#ibcon#wrote, iclass 3, count 0 2006.173.07:14:52.22#ibcon#about to read 3, iclass 3, count 0 2006.173.07:14:52.23#ibcon#read 3, iclass 3, count 0 2006.173.07:14:52.23#ibcon#about to read 4, iclass 3, count 0 2006.173.07:14:52.23#ibcon#read 4, iclass 3, count 0 2006.173.07:14:52.23#ibcon#about to read 5, iclass 3, count 0 2006.173.07:14:52.23#ibcon#read 5, iclass 3, count 0 2006.173.07:14:52.23#ibcon#about to read 6, iclass 3, count 0 2006.173.07:14:52.23#ibcon#read 6, iclass 3, count 0 2006.173.07:14:52.23#ibcon#end of sib2, iclass 3, count 0 2006.173.07:14:52.23#ibcon#*mode == 0, iclass 3, count 0 2006.173.07:14:52.23#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.07:14:52.23#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.07:14:52.23#ibcon#*before write, iclass 3, count 0 2006.173.07:14:52.23#ibcon#enter sib2, iclass 3, count 0 2006.173.07:14:52.23#ibcon#flushed, iclass 3, count 0 2006.173.07:14:52.23#ibcon#about to write, iclass 3, count 0 2006.173.07:14:52.23#ibcon#wrote, iclass 3, count 0 2006.173.07:14:52.23#ibcon#about to read 3, iclass 3, count 0 2006.173.07:14:52.27#ibcon#read 3, iclass 3, count 0 2006.173.07:14:52.27#ibcon#about to read 4, iclass 3, count 0 2006.173.07:14:52.27#ibcon#read 4, iclass 3, count 0 2006.173.07:14:52.27#ibcon#about to read 5, iclass 3, count 0 2006.173.07:14:52.27#ibcon#read 5, iclass 3, count 0 2006.173.07:14:52.27#ibcon#about to read 6, iclass 3, count 0 2006.173.07:14:52.27#ibcon#read 6, iclass 3, count 0 2006.173.07:14:52.27#ibcon#end of sib2, iclass 3, count 0 2006.173.07:14:52.27#ibcon#*after write, iclass 3, count 0 2006.173.07:14:52.27#ibcon#*before return 0, iclass 3, count 0 2006.173.07:14:52.27#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.07:14:52.27#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.07:14:52.27#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.07:14:52.27#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.07:14:52.27$vck44/vb=2,4 2006.173.07:14:52.27#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.07:14:52.27#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.07:14:52.27#ibcon#ireg 11 cls_cnt 2 2006.173.07:14:52.27#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.07:14:52.33#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.07:14:52.33#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.07:14:52.33#ibcon#enter wrdev, iclass 5, count 2 2006.173.07:14:52.33#ibcon#first serial, iclass 5, count 2 2006.173.07:14:52.33#ibcon#enter sib2, iclass 5, count 2 2006.173.07:14:52.33#ibcon#flushed, iclass 5, count 2 2006.173.07:14:52.33#ibcon#about to write, iclass 5, count 2 2006.173.07:14:52.33#ibcon#wrote, iclass 5, count 2 2006.173.07:14:52.33#ibcon#about to read 3, iclass 5, count 2 2006.173.07:14:52.35#ibcon#read 3, iclass 5, count 2 2006.173.07:14:52.35#ibcon#about to read 4, iclass 5, count 2 2006.173.07:14:52.35#ibcon#read 4, iclass 5, count 2 2006.173.07:14:52.35#ibcon#about to read 5, iclass 5, count 2 2006.173.07:14:52.35#ibcon#read 5, iclass 5, count 2 2006.173.07:14:52.35#ibcon#about to read 6, iclass 5, count 2 2006.173.07:14:52.35#ibcon#read 6, iclass 5, count 2 2006.173.07:14:52.35#ibcon#end of sib2, iclass 5, count 2 2006.173.07:14:52.35#ibcon#*mode == 0, iclass 5, count 2 2006.173.07:14:52.35#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.07:14:52.35#ibcon#[27=AT02-04\r\n] 2006.173.07:14:52.35#ibcon#*before write, iclass 5, count 2 2006.173.07:14:52.35#ibcon#enter sib2, iclass 5, count 2 2006.173.07:14:52.35#ibcon#flushed, iclass 5, count 2 2006.173.07:14:52.35#ibcon#about to write, iclass 5, count 2 2006.173.07:14:52.35#ibcon#wrote, iclass 5, count 2 2006.173.07:14:53.04#ibcon#about to read 3, iclass 5, count 2 2006.173.07:14:53.04#ibcon#read 3, iclass 5, count 2 2006.173.07:14:53.04#ibcon#about to read 4, iclass 5, count 2 2006.173.07:14:53.04#ibcon#read 4, iclass 5, count 2 2006.173.07:14:53.04#ibcon#about to read 5, iclass 5, count 2 2006.173.07:14:53.04#ibcon#read 5, iclass 5, count 2 2006.173.07:14:53.04#ibcon#about to read 6, iclass 5, count 2 2006.173.07:14:53.04#ibcon#read 6, iclass 5, count 2 2006.173.07:14:53.04#ibcon#end of sib2, iclass 5, count 2 2006.173.07:14:53.04#ibcon#*after write, iclass 5, count 2 2006.173.07:14:53.04#ibcon#*before return 0, iclass 5, count 2 2006.173.07:14:53.04#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.07:14:53.04#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.07:14:53.04#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.07:14:53.04#ibcon#ireg 7 cls_cnt 0 2006.173.07:14:53.04#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.07:14:53.15#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.07:14:53.15#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.07:14:53.15#ibcon#enter wrdev, iclass 5, count 0 2006.173.07:14:53.15#ibcon#first serial, iclass 5, count 0 2006.173.07:14:53.15#ibcon#enter sib2, iclass 5, count 0 2006.173.07:14:53.15#ibcon#flushed, iclass 5, count 0 2006.173.07:14:53.15#ibcon#about to write, iclass 5, count 0 2006.173.07:14:53.15#ibcon#wrote, iclass 5, count 0 2006.173.07:14:53.15#ibcon#about to read 3, iclass 5, count 0 2006.173.07:14:53.17#ibcon#read 3, iclass 5, count 0 2006.173.07:14:53.17#ibcon#about to read 4, iclass 5, count 0 2006.173.07:14:53.17#ibcon#read 4, iclass 5, count 0 2006.173.07:14:53.17#ibcon#about to read 5, iclass 5, count 0 2006.173.07:14:53.17#ibcon#read 5, iclass 5, count 0 2006.173.07:14:53.17#ibcon#about to read 6, iclass 5, count 0 2006.173.07:14:53.17#ibcon#read 6, iclass 5, count 0 2006.173.07:14:53.17#ibcon#end of sib2, iclass 5, count 0 2006.173.07:14:53.17#ibcon#*mode == 0, iclass 5, count 0 2006.173.07:14:53.17#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.07:14:53.17#ibcon#[27=USB\r\n] 2006.173.07:14:53.17#ibcon#*before write, iclass 5, count 0 2006.173.07:14:53.17#ibcon#enter sib2, iclass 5, count 0 2006.173.07:14:53.17#ibcon#flushed, iclass 5, count 0 2006.173.07:14:53.17#ibcon#about to write, iclass 5, count 0 2006.173.07:14:53.17#ibcon#wrote, iclass 5, count 0 2006.173.07:14:53.17#ibcon#about to read 3, iclass 5, count 0 2006.173.07:14:53.20#ibcon#read 3, iclass 5, count 0 2006.173.07:14:53.20#ibcon#about to read 4, iclass 5, count 0 2006.173.07:14:53.20#ibcon#read 4, iclass 5, count 0 2006.173.07:14:53.20#ibcon#about to read 5, iclass 5, count 0 2006.173.07:14:53.20#ibcon#read 5, iclass 5, count 0 2006.173.07:14:53.20#ibcon#about to read 6, iclass 5, count 0 2006.173.07:14:53.20#ibcon#read 6, iclass 5, count 0 2006.173.07:14:53.20#ibcon#end of sib2, iclass 5, count 0 2006.173.07:14:53.20#ibcon#*after write, iclass 5, count 0 2006.173.07:14:53.20#ibcon#*before return 0, iclass 5, count 0 2006.173.07:14:53.20#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.07:14:53.20#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.07:14:53.20#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.07:14:53.20#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.07:14:53.20$vck44/vblo=3,649.99 2006.173.07:14:53.20#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.07:14:53.20#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.07:14:53.20#ibcon#ireg 17 cls_cnt 0 2006.173.07:14:53.20#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.07:14:53.20#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.07:14:53.20#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.07:14:53.20#ibcon#enter wrdev, iclass 7, count 0 2006.173.07:14:53.20#ibcon#first serial, iclass 7, count 0 2006.173.07:14:53.20#ibcon#enter sib2, iclass 7, count 0 2006.173.07:14:53.21#ibcon#flushed, iclass 7, count 0 2006.173.07:14:53.21#ibcon#about to write, iclass 7, count 0 2006.173.07:14:53.21#ibcon#wrote, iclass 7, count 0 2006.173.07:14:53.21#ibcon#about to read 3, iclass 7, count 0 2006.173.07:14:53.22#ibcon#read 3, iclass 7, count 0 2006.173.07:14:53.22#ibcon#about to read 4, iclass 7, count 0 2006.173.07:14:53.22#ibcon#read 4, iclass 7, count 0 2006.173.07:14:53.22#ibcon#about to read 5, iclass 7, count 0 2006.173.07:14:53.22#ibcon#read 5, iclass 7, count 0 2006.173.07:14:53.22#ibcon#about to read 6, iclass 7, count 0 2006.173.07:14:53.22#ibcon#read 6, iclass 7, count 0 2006.173.07:14:53.22#ibcon#end of sib2, iclass 7, count 0 2006.173.07:14:53.22#ibcon#*mode == 0, iclass 7, count 0 2006.173.07:14:53.22#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.07:14:53.22#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.07:14:53.22#ibcon#*before write, iclass 7, count 0 2006.173.07:14:53.22#ibcon#enter sib2, iclass 7, count 0 2006.173.07:14:53.22#ibcon#flushed, iclass 7, count 0 2006.173.07:14:53.22#ibcon#about to write, iclass 7, count 0 2006.173.07:14:53.22#ibcon#wrote, iclass 7, count 0 2006.173.07:14:53.22#ibcon#about to read 3, iclass 7, count 0 2006.173.07:14:53.26#ibcon#read 3, iclass 7, count 0 2006.173.07:14:53.26#ibcon#about to read 4, iclass 7, count 0 2006.173.07:14:53.26#ibcon#read 4, iclass 7, count 0 2006.173.07:14:53.26#ibcon#about to read 5, iclass 7, count 0 2006.173.07:14:53.26#ibcon#read 5, iclass 7, count 0 2006.173.07:14:53.26#ibcon#about to read 6, iclass 7, count 0 2006.173.07:14:53.26#ibcon#read 6, iclass 7, count 0 2006.173.07:14:53.26#ibcon#end of sib2, iclass 7, count 0 2006.173.07:14:53.26#ibcon#*after write, iclass 7, count 0 2006.173.07:14:53.26#ibcon#*before return 0, iclass 7, count 0 2006.173.07:14:53.26#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.07:14:53.26#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.07:14:53.26#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.07:14:53.26#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.07:14:53.26$vck44/vb=3,4 2006.173.07:14:53.26#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.07:14:53.26#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.07:14:53.26#ibcon#ireg 11 cls_cnt 2 2006.173.07:14:53.26#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.07:14:53.32#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.07:14:53.32#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.07:14:53.32#ibcon#enter wrdev, iclass 11, count 2 2006.173.07:14:53.32#ibcon#first serial, iclass 11, count 2 2006.173.07:14:53.32#ibcon#enter sib2, iclass 11, count 2 2006.173.07:14:53.32#ibcon#flushed, iclass 11, count 2 2006.173.07:14:53.32#ibcon#about to write, iclass 11, count 2 2006.173.07:14:53.32#ibcon#wrote, iclass 11, count 2 2006.173.07:14:53.32#ibcon#about to read 3, iclass 11, count 2 2006.173.07:14:53.34#ibcon#read 3, iclass 11, count 2 2006.173.07:14:53.34#ibcon#about to read 4, iclass 11, count 2 2006.173.07:14:53.34#ibcon#read 4, iclass 11, count 2 2006.173.07:14:53.34#ibcon#about to read 5, iclass 11, count 2 2006.173.07:14:53.34#ibcon#read 5, iclass 11, count 2 2006.173.07:14:53.34#ibcon#about to read 6, iclass 11, count 2 2006.173.07:14:53.34#ibcon#read 6, iclass 11, count 2 2006.173.07:14:53.34#ibcon#end of sib2, iclass 11, count 2 2006.173.07:14:53.34#ibcon#*mode == 0, iclass 11, count 2 2006.173.07:14:53.34#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.07:14:53.34#ibcon#[27=AT03-04\r\n] 2006.173.07:14:53.34#ibcon#*before write, iclass 11, count 2 2006.173.07:14:53.34#ibcon#enter sib2, iclass 11, count 2 2006.173.07:14:53.34#ibcon#flushed, iclass 11, count 2 2006.173.07:14:53.34#ibcon#about to write, iclass 11, count 2 2006.173.07:14:53.34#ibcon#wrote, iclass 11, count 2 2006.173.07:14:53.34#ibcon#about to read 3, iclass 11, count 2 2006.173.07:14:53.37#ibcon#read 3, iclass 11, count 2 2006.173.07:14:53.37#ibcon#about to read 4, iclass 11, count 2 2006.173.07:14:53.37#ibcon#read 4, iclass 11, count 2 2006.173.07:14:53.37#ibcon#about to read 5, iclass 11, count 2 2006.173.07:14:53.37#ibcon#read 5, iclass 11, count 2 2006.173.07:14:53.37#ibcon#about to read 6, iclass 11, count 2 2006.173.07:14:53.37#ibcon#read 6, iclass 11, count 2 2006.173.07:14:53.37#ibcon#end of sib2, iclass 11, count 2 2006.173.07:14:53.37#ibcon#*after write, iclass 11, count 2 2006.173.07:14:53.37#ibcon#*before return 0, iclass 11, count 2 2006.173.07:14:53.37#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.07:14:53.37#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.07:14:53.37#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.07:14:53.37#ibcon#ireg 7 cls_cnt 0 2006.173.07:14:53.37#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.07:14:53.49#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.07:14:53.49#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.07:14:53.49#ibcon#enter wrdev, iclass 11, count 0 2006.173.07:14:53.49#ibcon#first serial, iclass 11, count 0 2006.173.07:14:53.49#ibcon#enter sib2, iclass 11, count 0 2006.173.07:14:53.49#ibcon#flushed, iclass 11, count 0 2006.173.07:14:53.49#ibcon#about to write, iclass 11, count 0 2006.173.07:14:53.49#ibcon#wrote, iclass 11, count 0 2006.173.07:14:53.49#ibcon#about to read 3, iclass 11, count 0 2006.173.07:14:53.51#ibcon#read 3, iclass 11, count 0 2006.173.07:14:53.51#ibcon#about to read 4, iclass 11, count 0 2006.173.07:14:53.51#ibcon#read 4, iclass 11, count 0 2006.173.07:14:53.51#ibcon#about to read 5, iclass 11, count 0 2006.173.07:14:53.51#ibcon#read 5, iclass 11, count 0 2006.173.07:14:53.51#ibcon#about to read 6, iclass 11, count 0 2006.173.07:14:53.51#ibcon#read 6, iclass 11, count 0 2006.173.07:14:53.51#ibcon#end of sib2, iclass 11, count 0 2006.173.07:14:53.51#ibcon#*mode == 0, iclass 11, count 0 2006.173.07:14:53.51#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.07:14:53.51#ibcon#[27=USB\r\n] 2006.173.07:14:53.51#ibcon#*before write, iclass 11, count 0 2006.173.07:14:53.51#ibcon#enter sib2, iclass 11, count 0 2006.173.07:14:53.51#ibcon#flushed, iclass 11, count 0 2006.173.07:14:53.51#ibcon#about to write, iclass 11, count 0 2006.173.07:14:53.51#ibcon#wrote, iclass 11, count 0 2006.173.07:14:53.51#ibcon#about to read 3, iclass 11, count 0 2006.173.07:14:53.54#ibcon#read 3, iclass 11, count 0 2006.173.07:14:53.54#ibcon#about to read 4, iclass 11, count 0 2006.173.07:14:53.54#ibcon#read 4, iclass 11, count 0 2006.173.07:14:53.54#ibcon#about to read 5, iclass 11, count 0 2006.173.07:14:53.54#ibcon#read 5, iclass 11, count 0 2006.173.07:14:53.54#ibcon#about to read 6, iclass 11, count 0 2006.173.07:14:53.54#ibcon#read 6, iclass 11, count 0 2006.173.07:14:53.54#ibcon#end of sib2, iclass 11, count 0 2006.173.07:14:53.54#ibcon#*after write, iclass 11, count 0 2006.173.07:14:53.54#ibcon#*before return 0, iclass 11, count 0 2006.173.07:14:53.54#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.07:14:53.54#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.07:14:53.54#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.07:14:53.54#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.07:14:53.54$vck44/vblo=4,679.99 2006.173.07:14:53.54#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.07:14:53.54#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.07:14:53.54#ibcon#ireg 17 cls_cnt 0 2006.173.07:14:53.54#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.07:14:53.54#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.07:14:53.54#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.07:14:53.54#ibcon#enter wrdev, iclass 13, count 0 2006.173.07:14:53.54#ibcon#first serial, iclass 13, count 0 2006.173.07:14:53.54#ibcon#enter sib2, iclass 13, count 0 2006.173.07:14:53.54#ibcon#flushed, iclass 13, count 0 2006.173.07:14:53.54#ibcon#about to write, iclass 13, count 0 2006.173.07:14:53.54#ibcon#wrote, iclass 13, count 0 2006.173.07:14:53.54#ibcon#about to read 3, iclass 13, count 0 2006.173.07:14:53.56#ibcon#read 3, iclass 13, count 0 2006.173.07:14:53.56#ibcon#about to read 4, iclass 13, count 0 2006.173.07:14:53.56#ibcon#read 4, iclass 13, count 0 2006.173.07:14:53.56#ibcon#about to read 5, iclass 13, count 0 2006.173.07:14:53.56#ibcon#read 5, iclass 13, count 0 2006.173.07:14:53.56#ibcon#about to read 6, iclass 13, count 0 2006.173.07:14:53.56#ibcon#read 6, iclass 13, count 0 2006.173.07:14:53.56#ibcon#end of sib2, iclass 13, count 0 2006.173.07:14:53.56#ibcon#*mode == 0, iclass 13, count 0 2006.173.07:14:53.56#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.07:14:53.56#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.07:14:53.56#ibcon#*before write, iclass 13, count 0 2006.173.07:14:53.56#ibcon#enter sib2, iclass 13, count 0 2006.173.07:14:53.56#ibcon#flushed, iclass 13, count 0 2006.173.07:14:53.56#ibcon#about to write, iclass 13, count 0 2006.173.07:14:53.56#ibcon#wrote, iclass 13, count 0 2006.173.07:14:53.56#ibcon#about to read 3, iclass 13, count 0 2006.173.07:14:53.60#ibcon#read 3, iclass 13, count 0 2006.173.07:14:53.60#ibcon#about to read 4, iclass 13, count 0 2006.173.07:14:53.60#ibcon#read 4, iclass 13, count 0 2006.173.07:14:53.60#ibcon#about to read 5, iclass 13, count 0 2006.173.07:14:53.60#ibcon#read 5, iclass 13, count 0 2006.173.07:14:53.60#ibcon#about to read 6, iclass 13, count 0 2006.173.07:14:53.60#ibcon#read 6, iclass 13, count 0 2006.173.07:14:53.60#ibcon#end of sib2, iclass 13, count 0 2006.173.07:14:53.60#ibcon#*after write, iclass 13, count 0 2006.173.07:14:53.60#ibcon#*before return 0, iclass 13, count 0 2006.173.07:14:53.60#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.07:14:53.60#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.07:14:53.60#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.07:14:53.60#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.07:14:53.60$vck44/vb=4,4 2006.173.07:14:53.60#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.07:14:53.60#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.07:14:53.60#ibcon#ireg 11 cls_cnt 2 2006.173.07:14:53.60#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.07:14:53.66#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.07:14:53.66#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.07:14:53.66#ibcon#enter wrdev, iclass 15, count 2 2006.173.07:14:53.66#ibcon#first serial, iclass 15, count 2 2006.173.07:14:53.66#ibcon#enter sib2, iclass 15, count 2 2006.173.07:14:53.66#ibcon#flushed, iclass 15, count 2 2006.173.07:14:53.66#ibcon#about to write, iclass 15, count 2 2006.173.07:14:53.66#ibcon#wrote, iclass 15, count 2 2006.173.07:14:53.66#ibcon#about to read 3, iclass 15, count 2 2006.173.07:14:53.68#ibcon#read 3, iclass 15, count 2 2006.173.07:14:53.68#ibcon#about to read 4, iclass 15, count 2 2006.173.07:14:53.68#ibcon#read 4, iclass 15, count 2 2006.173.07:14:53.68#ibcon#about to read 5, iclass 15, count 2 2006.173.07:14:53.68#ibcon#read 5, iclass 15, count 2 2006.173.07:14:53.68#ibcon#about to read 6, iclass 15, count 2 2006.173.07:14:53.68#ibcon#read 6, iclass 15, count 2 2006.173.07:14:53.68#ibcon#end of sib2, iclass 15, count 2 2006.173.07:14:53.68#ibcon#*mode == 0, iclass 15, count 2 2006.173.07:14:53.68#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.07:14:53.68#ibcon#[27=AT04-04\r\n] 2006.173.07:14:53.68#ibcon#*before write, iclass 15, count 2 2006.173.07:14:53.68#ibcon#enter sib2, iclass 15, count 2 2006.173.07:14:53.68#ibcon#flushed, iclass 15, count 2 2006.173.07:14:53.68#ibcon#about to write, iclass 15, count 2 2006.173.07:14:53.68#ibcon#wrote, iclass 15, count 2 2006.173.07:14:53.68#ibcon#about to read 3, iclass 15, count 2 2006.173.07:14:53.71#ibcon#read 3, iclass 15, count 2 2006.173.07:14:53.71#ibcon#about to read 4, iclass 15, count 2 2006.173.07:14:53.71#ibcon#read 4, iclass 15, count 2 2006.173.07:14:53.71#ibcon#about to read 5, iclass 15, count 2 2006.173.07:14:53.71#ibcon#read 5, iclass 15, count 2 2006.173.07:14:53.71#ibcon#about to read 6, iclass 15, count 2 2006.173.07:14:53.71#ibcon#read 6, iclass 15, count 2 2006.173.07:14:53.71#ibcon#end of sib2, iclass 15, count 2 2006.173.07:14:53.71#ibcon#*after write, iclass 15, count 2 2006.173.07:14:53.71#ibcon#*before return 0, iclass 15, count 2 2006.173.07:14:53.71#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.07:14:53.71#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.07:14:53.71#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.07:14:53.71#ibcon#ireg 7 cls_cnt 0 2006.173.07:14:53.71#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.07:14:53.83#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.07:14:53.83#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.07:14:53.83#ibcon#enter wrdev, iclass 15, count 0 2006.173.07:14:53.83#ibcon#first serial, iclass 15, count 0 2006.173.07:14:53.83#ibcon#enter sib2, iclass 15, count 0 2006.173.07:14:53.83#ibcon#flushed, iclass 15, count 0 2006.173.07:14:53.83#ibcon#about to write, iclass 15, count 0 2006.173.07:14:53.83#ibcon#wrote, iclass 15, count 0 2006.173.07:14:53.83#ibcon#about to read 3, iclass 15, count 0 2006.173.07:14:53.85#ibcon#read 3, iclass 15, count 0 2006.173.07:14:53.85#ibcon#about to read 4, iclass 15, count 0 2006.173.07:14:53.85#ibcon#read 4, iclass 15, count 0 2006.173.07:14:53.85#ibcon#about to read 5, iclass 15, count 0 2006.173.07:14:53.85#ibcon#read 5, iclass 15, count 0 2006.173.07:14:53.85#ibcon#about to read 6, iclass 15, count 0 2006.173.07:14:53.85#ibcon#read 6, iclass 15, count 0 2006.173.07:14:53.85#ibcon#end of sib2, iclass 15, count 0 2006.173.07:14:53.85#ibcon#*mode == 0, iclass 15, count 0 2006.173.07:14:53.85#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.07:14:53.85#ibcon#[27=USB\r\n] 2006.173.07:14:53.85#ibcon#*before write, iclass 15, count 0 2006.173.07:14:53.85#ibcon#enter sib2, iclass 15, count 0 2006.173.07:14:53.85#ibcon#flushed, iclass 15, count 0 2006.173.07:14:53.85#ibcon#about to write, iclass 15, count 0 2006.173.07:14:53.85#ibcon#wrote, iclass 15, count 0 2006.173.07:14:53.85#ibcon#about to read 3, iclass 15, count 0 2006.173.07:14:53.88#ibcon#read 3, iclass 15, count 0 2006.173.07:14:53.88#ibcon#about to read 4, iclass 15, count 0 2006.173.07:14:53.88#ibcon#read 4, iclass 15, count 0 2006.173.07:14:53.88#ibcon#about to read 5, iclass 15, count 0 2006.173.07:14:53.88#ibcon#read 5, iclass 15, count 0 2006.173.07:14:53.88#ibcon#about to read 6, iclass 15, count 0 2006.173.07:14:53.88#ibcon#read 6, iclass 15, count 0 2006.173.07:14:53.88#ibcon#end of sib2, iclass 15, count 0 2006.173.07:14:53.88#ibcon#*after write, iclass 15, count 0 2006.173.07:14:53.88#ibcon#*before return 0, iclass 15, count 0 2006.173.07:14:53.88#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.07:14:53.88#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.07:14:53.88#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.07:14:53.88#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.07:14:53.88$vck44/vblo=5,709.99 2006.173.07:14:53.88#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.07:14:53.88#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.07:14:53.88#ibcon#ireg 17 cls_cnt 0 2006.173.07:14:53.88#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.07:14:53.88#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.07:14:53.88#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.07:14:53.88#ibcon#enter wrdev, iclass 17, count 0 2006.173.07:14:53.88#ibcon#first serial, iclass 17, count 0 2006.173.07:14:53.88#ibcon#enter sib2, iclass 17, count 0 2006.173.07:14:53.88#ibcon#flushed, iclass 17, count 0 2006.173.07:14:53.88#ibcon#about to write, iclass 17, count 0 2006.173.07:14:53.89#ibcon#wrote, iclass 17, count 0 2006.173.07:14:53.89#ibcon#about to read 3, iclass 17, count 0 2006.173.07:14:53.90#ibcon#read 3, iclass 17, count 0 2006.173.07:14:53.90#ibcon#about to read 4, iclass 17, count 0 2006.173.07:14:53.90#ibcon#read 4, iclass 17, count 0 2006.173.07:14:53.90#ibcon#about to read 5, iclass 17, count 0 2006.173.07:14:53.90#ibcon#read 5, iclass 17, count 0 2006.173.07:14:53.90#ibcon#about to read 6, iclass 17, count 0 2006.173.07:14:53.90#ibcon#read 6, iclass 17, count 0 2006.173.07:14:53.90#ibcon#end of sib2, iclass 17, count 0 2006.173.07:14:53.90#ibcon#*mode == 0, iclass 17, count 0 2006.173.07:14:53.90#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.07:14:53.90#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.07:14:53.90#ibcon#*before write, iclass 17, count 0 2006.173.07:14:53.90#ibcon#enter sib2, iclass 17, count 0 2006.173.07:14:53.90#ibcon#flushed, iclass 17, count 0 2006.173.07:14:53.90#ibcon#about to write, iclass 17, count 0 2006.173.07:14:53.90#ibcon#wrote, iclass 17, count 0 2006.173.07:14:53.90#ibcon#about to read 3, iclass 17, count 0 2006.173.07:14:53.94#ibcon#read 3, iclass 17, count 0 2006.173.07:14:53.94#ibcon#about to read 4, iclass 17, count 0 2006.173.07:14:53.94#ibcon#read 4, iclass 17, count 0 2006.173.07:14:53.94#ibcon#about to read 5, iclass 17, count 0 2006.173.07:14:53.94#ibcon#read 5, iclass 17, count 0 2006.173.07:14:53.94#ibcon#about to read 6, iclass 17, count 0 2006.173.07:14:53.94#ibcon#read 6, iclass 17, count 0 2006.173.07:14:53.94#ibcon#end of sib2, iclass 17, count 0 2006.173.07:14:53.94#ibcon#*after write, iclass 17, count 0 2006.173.07:14:53.94#ibcon#*before return 0, iclass 17, count 0 2006.173.07:14:53.94#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.07:14:53.94#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.07:14:53.94#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.07:14:53.94#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.07:14:53.94$vck44/vb=5,4 2006.173.07:14:53.94#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.07:14:53.94#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.07:14:53.94#ibcon#ireg 11 cls_cnt 2 2006.173.07:14:53.94#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.07:14:54.00#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.07:14:54.00#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.07:14:54.00#ibcon#enter wrdev, iclass 19, count 2 2006.173.07:14:54.00#ibcon#first serial, iclass 19, count 2 2006.173.07:14:54.00#ibcon#enter sib2, iclass 19, count 2 2006.173.07:14:54.00#ibcon#flushed, iclass 19, count 2 2006.173.07:14:54.00#ibcon#about to write, iclass 19, count 2 2006.173.07:14:54.00#ibcon#wrote, iclass 19, count 2 2006.173.07:14:54.00#ibcon#about to read 3, iclass 19, count 2 2006.173.07:14:54.02#ibcon#read 3, iclass 19, count 2 2006.173.07:14:54.02#ibcon#about to read 4, iclass 19, count 2 2006.173.07:14:54.02#ibcon#read 4, iclass 19, count 2 2006.173.07:14:54.02#ibcon#about to read 5, iclass 19, count 2 2006.173.07:14:54.02#ibcon#read 5, iclass 19, count 2 2006.173.07:14:54.02#ibcon#about to read 6, iclass 19, count 2 2006.173.07:14:54.02#ibcon#read 6, iclass 19, count 2 2006.173.07:14:54.02#ibcon#end of sib2, iclass 19, count 2 2006.173.07:14:54.02#ibcon#*mode == 0, iclass 19, count 2 2006.173.07:14:54.02#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.07:14:54.02#ibcon#[27=AT05-04\r\n] 2006.173.07:14:54.02#ibcon#*before write, iclass 19, count 2 2006.173.07:14:54.02#ibcon#enter sib2, iclass 19, count 2 2006.173.07:14:54.02#ibcon#flushed, iclass 19, count 2 2006.173.07:14:54.02#ibcon#about to write, iclass 19, count 2 2006.173.07:14:54.02#ibcon#wrote, iclass 19, count 2 2006.173.07:14:54.02#ibcon#about to read 3, iclass 19, count 2 2006.173.07:14:54.05#ibcon#read 3, iclass 19, count 2 2006.173.07:14:54.05#ibcon#about to read 4, iclass 19, count 2 2006.173.07:14:54.05#ibcon#read 4, iclass 19, count 2 2006.173.07:14:54.05#ibcon#about to read 5, iclass 19, count 2 2006.173.07:14:54.05#ibcon#read 5, iclass 19, count 2 2006.173.07:14:54.05#ibcon#about to read 6, iclass 19, count 2 2006.173.07:14:54.05#ibcon#read 6, iclass 19, count 2 2006.173.07:14:54.05#ibcon#end of sib2, iclass 19, count 2 2006.173.07:14:54.05#ibcon#*after write, iclass 19, count 2 2006.173.07:14:54.05#ibcon#*before return 0, iclass 19, count 2 2006.173.07:14:54.05#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.07:14:54.05#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.07:14:54.05#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.07:14:54.05#ibcon#ireg 7 cls_cnt 0 2006.173.07:14:54.05#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.07:14:54.17#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.07:14:54.17#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.07:14:54.17#ibcon#enter wrdev, iclass 19, count 0 2006.173.07:14:54.17#ibcon#first serial, iclass 19, count 0 2006.173.07:14:54.17#ibcon#enter sib2, iclass 19, count 0 2006.173.07:14:54.17#ibcon#flushed, iclass 19, count 0 2006.173.07:14:54.17#ibcon#about to write, iclass 19, count 0 2006.173.07:14:54.17#ibcon#wrote, iclass 19, count 0 2006.173.07:14:54.17#ibcon#about to read 3, iclass 19, count 0 2006.173.07:14:54.19#ibcon#read 3, iclass 19, count 0 2006.173.07:14:54.19#ibcon#about to read 4, iclass 19, count 0 2006.173.07:14:54.19#ibcon#read 4, iclass 19, count 0 2006.173.07:14:54.19#ibcon#about to read 5, iclass 19, count 0 2006.173.07:14:54.19#ibcon#read 5, iclass 19, count 0 2006.173.07:14:54.19#ibcon#about to read 6, iclass 19, count 0 2006.173.07:14:54.19#ibcon#read 6, iclass 19, count 0 2006.173.07:14:54.19#ibcon#end of sib2, iclass 19, count 0 2006.173.07:14:54.19#ibcon#*mode == 0, iclass 19, count 0 2006.173.07:14:54.19#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.07:14:54.19#ibcon#[27=USB\r\n] 2006.173.07:14:54.19#ibcon#*before write, iclass 19, count 0 2006.173.07:14:54.19#ibcon#enter sib2, iclass 19, count 0 2006.173.07:14:54.19#ibcon#flushed, iclass 19, count 0 2006.173.07:14:54.19#ibcon#about to write, iclass 19, count 0 2006.173.07:14:54.19#ibcon#wrote, iclass 19, count 0 2006.173.07:14:54.19#ibcon#about to read 3, iclass 19, count 0 2006.173.07:14:54.22#ibcon#read 3, iclass 19, count 0 2006.173.07:14:54.22#ibcon#about to read 4, iclass 19, count 0 2006.173.07:14:54.22#ibcon#read 4, iclass 19, count 0 2006.173.07:14:54.22#ibcon#about to read 5, iclass 19, count 0 2006.173.07:14:54.22#ibcon#read 5, iclass 19, count 0 2006.173.07:14:54.22#ibcon#about to read 6, iclass 19, count 0 2006.173.07:14:54.22#ibcon#read 6, iclass 19, count 0 2006.173.07:14:54.22#ibcon#end of sib2, iclass 19, count 0 2006.173.07:14:54.22#ibcon#*after write, iclass 19, count 0 2006.173.07:14:54.22#ibcon#*before return 0, iclass 19, count 0 2006.173.07:14:54.22#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.07:14:54.22#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.07:14:54.22#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.07:14:54.22#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.07:14:54.22$vck44/vblo=6,719.99 2006.173.07:14:54.22#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.07:14:54.22#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.07:14:54.22#ibcon#ireg 17 cls_cnt 0 2006.173.07:14:54.22#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.07:14:54.22#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.07:14:54.22#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.07:14:54.22#ibcon#enter wrdev, iclass 21, count 0 2006.173.07:14:54.22#ibcon#first serial, iclass 21, count 0 2006.173.07:14:54.23#ibcon#enter sib2, iclass 21, count 0 2006.173.07:14:54.23#ibcon#flushed, iclass 21, count 0 2006.173.07:14:54.23#ibcon#about to write, iclass 21, count 0 2006.173.07:14:54.23#ibcon#wrote, iclass 21, count 0 2006.173.07:14:54.23#ibcon#about to read 3, iclass 21, count 0 2006.173.07:14:54.24#ibcon#read 3, iclass 21, count 0 2006.173.07:14:54.24#ibcon#about to read 4, iclass 21, count 0 2006.173.07:14:54.24#ibcon#read 4, iclass 21, count 0 2006.173.07:14:54.24#ibcon#about to read 5, iclass 21, count 0 2006.173.07:14:54.24#ibcon#read 5, iclass 21, count 0 2006.173.07:14:54.24#ibcon#about to read 6, iclass 21, count 0 2006.173.07:14:54.24#ibcon#read 6, iclass 21, count 0 2006.173.07:14:54.24#ibcon#end of sib2, iclass 21, count 0 2006.173.07:14:54.24#ibcon#*mode == 0, iclass 21, count 0 2006.173.07:14:54.24#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.07:14:54.24#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.07:14:54.24#ibcon#*before write, iclass 21, count 0 2006.173.07:14:54.24#ibcon#enter sib2, iclass 21, count 0 2006.173.07:14:54.24#ibcon#flushed, iclass 21, count 0 2006.173.07:14:54.24#ibcon#about to write, iclass 21, count 0 2006.173.07:14:54.24#ibcon#wrote, iclass 21, count 0 2006.173.07:14:54.24#ibcon#about to read 3, iclass 21, count 0 2006.173.07:14:54.28#ibcon#read 3, iclass 21, count 0 2006.173.07:14:54.28#ibcon#about to read 4, iclass 21, count 0 2006.173.07:14:54.28#ibcon#read 4, iclass 21, count 0 2006.173.07:14:54.28#ibcon#about to read 5, iclass 21, count 0 2006.173.07:14:54.28#ibcon#read 5, iclass 21, count 0 2006.173.07:14:54.28#ibcon#about to read 6, iclass 21, count 0 2006.173.07:14:54.28#ibcon#read 6, iclass 21, count 0 2006.173.07:14:54.28#ibcon#end of sib2, iclass 21, count 0 2006.173.07:14:54.28#ibcon#*after write, iclass 21, count 0 2006.173.07:14:54.28#ibcon#*before return 0, iclass 21, count 0 2006.173.07:14:54.28#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.07:14:54.28#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.07:14:54.28#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.07:14:54.28#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.07:14:54.28$vck44/vb=6,4 2006.173.07:14:54.28#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.07:14:54.28#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.07:14:54.28#ibcon#ireg 11 cls_cnt 2 2006.173.07:14:54.28#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.07:14:54.34#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.07:14:54.34#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.07:14:54.34#ibcon#enter wrdev, iclass 23, count 2 2006.173.07:14:54.34#ibcon#first serial, iclass 23, count 2 2006.173.07:14:54.34#ibcon#enter sib2, iclass 23, count 2 2006.173.07:14:54.34#ibcon#flushed, iclass 23, count 2 2006.173.07:14:54.34#ibcon#about to write, iclass 23, count 2 2006.173.07:14:54.34#ibcon#wrote, iclass 23, count 2 2006.173.07:14:54.34#ibcon#about to read 3, iclass 23, count 2 2006.173.07:14:54.36#ibcon#read 3, iclass 23, count 2 2006.173.07:14:54.36#ibcon#about to read 4, iclass 23, count 2 2006.173.07:14:54.36#ibcon#read 4, iclass 23, count 2 2006.173.07:14:54.36#ibcon#about to read 5, iclass 23, count 2 2006.173.07:14:54.36#ibcon#read 5, iclass 23, count 2 2006.173.07:14:54.36#ibcon#about to read 6, iclass 23, count 2 2006.173.07:14:54.36#ibcon#read 6, iclass 23, count 2 2006.173.07:14:54.36#ibcon#end of sib2, iclass 23, count 2 2006.173.07:14:54.36#ibcon#*mode == 0, iclass 23, count 2 2006.173.07:14:54.36#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.07:14:54.36#ibcon#[27=AT06-04\r\n] 2006.173.07:14:54.36#ibcon#*before write, iclass 23, count 2 2006.173.07:14:54.36#ibcon#enter sib2, iclass 23, count 2 2006.173.07:14:54.36#ibcon#flushed, iclass 23, count 2 2006.173.07:14:54.36#ibcon#about to write, iclass 23, count 2 2006.173.07:14:54.36#ibcon#wrote, iclass 23, count 2 2006.173.07:14:54.36#ibcon#about to read 3, iclass 23, count 2 2006.173.07:14:54.39#ibcon#read 3, iclass 23, count 2 2006.173.07:14:55.01#ibcon#about to read 4, iclass 23, count 2 2006.173.07:14:55.01#ibcon#read 4, iclass 23, count 2 2006.173.07:14:55.01#ibcon#about to read 5, iclass 23, count 2 2006.173.07:14:55.01#ibcon#read 5, iclass 23, count 2 2006.173.07:14:55.01#ibcon#about to read 6, iclass 23, count 2 2006.173.07:14:55.01#ibcon#read 6, iclass 23, count 2 2006.173.07:14:55.01#ibcon#end of sib2, iclass 23, count 2 2006.173.07:14:55.01#ibcon#*after write, iclass 23, count 2 2006.173.07:14:55.01#ibcon#*before return 0, iclass 23, count 2 2006.173.07:14:55.01#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.07:14:55.01#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.07:14:55.01#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.07:14:55.01#ibcon#ireg 7 cls_cnt 0 2006.173.07:14:55.01#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.07:14:55.12#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.07:14:55.12#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.07:14:55.12#ibcon#enter wrdev, iclass 23, count 0 2006.173.07:14:55.12#ibcon#first serial, iclass 23, count 0 2006.173.07:14:55.12#ibcon#enter sib2, iclass 23, count 0 2006.173.07:14:55.12#ibcon#flushed, iclass 23, count 0 2006.173.07:14:55.12#ibcon#about to write, iclass 23, count 0 2006.173.07:14:55.12#ibcon#wrote, iclass 23, count 0 2006.173.07:14:55.12#ibcon#about to read 3, iclass 23, count 0 2006.173.07:14:55.14#ibcon#read 3, iclass 23, count 0 2006.173.07:14:55.14#ibcon#about to read 4, iclass 23, count 0 2006.173.07:14:55.14#ibcon#read 4, iclass 23, count 0 2006.173.07:14:55.14#ibcon#about to read 5, iclass 23, count 0 2006.173.07:14:55.14#ibcon#read 5, iclass 23, count 0 2006.173.07:14:55.14#ibcon#about to read 6, iclass 23, count 0 2006.173.07:14:55.14#ibcon#read 6, iclass 23, count 0 2006.173.07:14:55.14#ibcon#end of sib2, iclass 23, count 0 2006.173.07:14:55.14#ibcon#*mode == 0, iclass 23, count 0 2006.173.07:14:55.14#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.07:14:55.14#ibcon#[27=USB\r\n] 2006.173.07:14:55.14#ibcon#*before write, iclass 23, count 0 2006.173.07:14:55.14#ibcon#enter sib2, iclass 23, count 0 2006.173.07:14:55.14#ibcon#flushed, iclass 23, count 0 2006.173.07:14:55.14#ibcon#about to write, iclass 23, count 0 2006.173.07:14:55.14#ibcon#wrote, iclass 23, count 0 2006.173.07:14:55.14#ibcon#about to read 3, iclass 23, count 0 2006.173.07:14:55.17#ibcon#read 3, iclass 23, count 0 2006.173.07:14:55.17#ibcon#about to read 4, iclass 23, count 0 2006.173.07:14:55.17#ibcon#read 4, iclass 23, count 0 2006.173.07:14:55.17#ibcon#about to read 5, iclass 23, count 0 2006.173.07:14:55.17#ibcon#read 5, iclass 23, count 0 2006.173.07:14:55.17#ibcon#about to read 6, iclass 23, count 0 2006.173.07:14:55.17#ibcon#read 6, iclass 23, count 0 2006.173.07:14:55.17#ibcon#end of sib2, iclass 23, count 0 2006.173.07:14:55.17#ibcon#*after write, iclass 23, count 0 2006.173.07:14:55.17#ibcon#*before return 0, iclass 23, count 0 2006.173.07:14:55.17#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.07:14:55.17#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.07:14:55.17#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.07:14:55.17#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.07:14:55.17$vck44/vblo=7,734.99 2006.173.07:14:55.17#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.07:14:55.17#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.07:14:55.17#ibcon#ireg 17 cls_cnt 0 2006.173.07:14:55.17#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.07:14:55.17#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.07:14:55.17#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.07:14:55.17#ibcon#enter wrdev, iclass 25, count 0 2006.173.07:14:55.17#ibcon#first serial, iclass 25, count 0 2006.173.07:14:55.17#ibcon#enter sib2, iclass 25, count 0 2006.173.07:14:55.17#ibcon#flushed, iclass 25, count 0 2006.173.07:14:55.17#ibcon#about to write, iclass 25, count 0 2006.173.07:14:55.17#ibcon#wrote, iclass 25, count 0 2006.173.07:14:55.18#ibcon#about to read 3, iclass 25, count 0 2006.173.07:14:55.19#ibcon#read 3, iclass 25, count 0 2006.173.07:14:55.19#ibcon#about to read 4, iclass 25, count 0 2006.173.07:14:55.19#ibcon#read 4, iclass 25, count 0 2006.173.07:14:55.19#ibcon#about to read 5, iclass 25, count 0 2006.173.07:14:55.19#ibcon#read 5, iclass 25, count 0 2006.173.07:14:55.19#ibcon#about to read 6, iclass 25, count 0 2006.173.07:14:55.19#ibcon#read 6, iclass 25, count 0 2006.173.07:14:55.19#ibcon#end of sib2, iclass 25, count 0 2006.173.07:14:55.19#ibcon#*mode == 0, iclass 25, count 0 2006.173.07:14:55.19#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.07:14:55.19#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.07:14:55.19#ibcon#*before write, iclass 25, count 0 2006.173.07:14:55.19#ibcon#enter sib2, iclass 25, count 0 2006.173.07:14:55.19#ibcon#flushed, iclass 25, count 0 2006.173.07:14:55.19#ibcon#about to write, iclass 25, count 0 2006.173.07:14:55.19#ibcon#wrote, iclass 25, count 0 2006.173.07:14:55.19#ibcon#about to read 3, iclass 25, count 0 2006.173.07:14:55.23#ibcon#read 3, iclass 25, count 0 2006.173.07:14:55.23#ibcon#about to read 4, iclass 25, count 0 2006.173.07:14:55.23#ibcon#read 4, iclass 25, count 0 2006.173.07:14:55.23#ibcon#about to read 5, iclass 25, count 0 2006.173.07:14:55.23#ibcon#read 5, iclass 25, count 0 2006.173.07:14:55.23#ibcon#about to read 6, iclass 25, count 0 2006.173.07:14:55.23#ibcon#read 6, iclass 25, count 0 2006.173.07:14:55.23#ibcon#end of sib2, iclass 25, count 0 2006.173.07:14:55.23#ibcon#*after write, iclass 25, count 0 2006.173.07:14:55.23#ibcon#*before return 0, iclass 25, count 0 2006.173.07:14:55.23#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.07:14:55.23#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.07:14:55.23#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.07:14:55.23#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.07:14:55.23$vck44/vb=7,4 2006.173.07:14:55.23#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.07:14:55.23#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.07:14:55.23#ibcon#ireg 11 cls_cnt 2 2006.173.07:14:55.23#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.07:14:55.29#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.07:14:55.29#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.07:14:55.29#ibcon#enter wrdev, iclass 27, count 2 2006.173.07:14:55.29#ibcon#first serial, iclass 27, count 2 2006.173.07:14:55.29#ibcon#enter sib2, iclass 27, count 2 2006.173.07:14:55.29#ibcon#flushed, iclass 27, count 2 2006.173.07:14:55.29#ibcon#about to write, iclass 27, count 2 2006.173.07:14:55.29#ibcon#wrote, iclass 27, count 2 2006.173.07:14:55.29#ibcon#about to read 3, iclass 27, count 2 2006.173.07:14:55.31#ibcon#read 3, iclass 27, count 2 2006.173.07:14:55.31#ibcon#about to read 4, iclass 27, count 2 2006.173.07:14:55.31#ibcon#read 4, iclass 27, count 2 2006.173.07:14:55.31#ibcon#about to read 5, iclass 27, count 2 2006.173.07:14:55.31#ibcon#read 5, iclass 27, count 2 2006.173.07:14:55.31#ibcon#about to read 6, iclass 27, count 2 2006.173.07:14:55.31#ibcon#read 6, iclass 27, count 2 2006.173.07:14:55.31#ibcon#end of sib2, iclass 27, count 2 2006.173.07:14:55.31#ibcon#*mode == 0, iclass 27, count 2 2006.173.07:14:55.31#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.07:14:55.31#ibcon#[27=AT07-04\r\n] 2006.173.07:14:55.31#ibcon#*before write, iclass 27, count 2 2006.173.07:14:55.31#ibcon#enter sib2, iclass 27, count 2 2006.173.07:14:55.31#ibcon#flushed, iclass 27, count 2 2006.173.07:14:55.31#ibcon#about to write, iclass 27, count 2 2006.173.07:14:55.31#ibcon#wrote, iclass 27, count 2 2006.173.07:14:55.31#ibcon#about to read 3, iclass 27, count 2 2006.173.07:14:55.34#ibcon#read 3, iclass 27, count 2 2006.173.07:14:55.34#ibcon#about to read 4, iclass 27, count 2 2006.173.07:14:55.34#ibcon#read 4, iclass 27, count 2 2006.173.07:14:55.34#ibcon#about to read 5, iclass 27, count 2 2006.173.07:14:55.34#ibcon#read 5, iclass 27, count 2 2006.173.07:14:55.34#ibcon#about to read 6, iclass 27, count 2 2006.173.07:14:55.34#ibcon#read 6, iclass 27, count 2 2006.173.07:14:55.34#ibcon#end of sib2, iclass 27, count 2 2006.173.07:14:55.34#ibcon#*after write, iclass 27, count 2 2006.173.07:14:55.34#ibcon#*before return 0, iclass 27, count 2 2006.173.07:14:55.34#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.07:14:55.34#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.07:14:55.34#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.07:14:55.34#ibcon#ireg 7 cls_cnt 0 2006.173.07:14:55.34#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.07:14:55.46#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.07:14:55.46#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.07:14:55.46#ibcon#enter wrdev, iclass 27, count 0 2006.173.07:14:55.46#ibcon#first serial, iclass 27, count 0 2006.173.07:14:55.46#ibcon#enter sib2, iclass 27, count 0 2006.173.07:14:55.46#ibcon#flushed, iclass 27, count 0 2006.173.07:14:55.46#ibcon#about to write, iclass 27, count 0 2006.173.07:14:55.46#ibcon#wrote, iclass 27, count 0 2006.173.07:14:55.46#ibcon#about to read 3, iclass 27, count 0 2006.173.07:14:55.48#ibcon#read 3, iclass 27, count 0 2006.173.07:14:55.48#ibcon#about to read 4, iclass 27, count 0 2006.173.07:14:55.48#ibcon#read 4, iclass 27, count 0 2006.173.07:14:55.48#ibcon#about to read 5, iclass 27, count 0 2006.173.07:14:55.48#ibcon#read 5, iclass 27, count 0 2006.173.07:14:55.48#ibcon#about to read 6, iclass 27, count 0 2006.173.07:14:55.48#ibcon#read 6, iclass 27, count 0 2006.173.07:14:55.48#ibcon#end of sib2, iclass 27, count 0 2006.173.07:14:55.48#ibcon#*mode == 0, iclass 27, count 0 2006.173.07:14:55.48#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.07:14:55.48#ibcon#[27=USB\r\n] 2006.173.07:14:55.48#ibcon#*before write, iclass 27, count 0 2006.173.07:14:55.48#ibcon#enter sib2, iclass 27, count 0 2006.173.07:14:55.48#ibcon#flushed, iclass 27, count 0 2006.173.07:14:55.48#ibcon#about to write, iclass 27, count 0 2006.173.07:14:55.48#ibcon#wrote, iclass 27, count 0 2006.173.07:14:55.48#ibcon#about to read 3, iclass 27, count 0 2006.173.07:14:55.51#ibcon#read 3, iclass 27, count 0 2006.173.07:14:55.51#ibcon#about to read 4, iclass 27, count 0 2006.173.07:14:55.51#ibcon#read 4, iclass 27, count 0 2006.173.07:14:55.51#ibcon#about to read 5, iclass 27, count 0 2006.173.07:14:55.51#ibcon#read 5, iclass 27, count 0 2006.173.07:14:55.51#ibcon#about to read 6, iclass 27, count 0 2006.173.07:14:55.51#ibcon#read 6, iclass 27, count 0 2006.173.07:14:55.51#ibcon#end of sib2, iclass 27, count 0 2006.173.07:14:55.51#ibcon#*after write, iclass 27, count 0 2006.173.07:14:55.51#ibcon#*before return 0, iclass 27, count 0 2006.173.07:14:55.51#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.07:14:55.51#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.07:14:55.51#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.07:14:55.51#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.07:14:55.51$vck44/vblo=8,744.99 2006.173.07:14:55.51#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.07:14:55.51#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.07:14:55.51#ibcon#ireg 17 cls_cnt 0 2006.173.07:14:55.51#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.07:14:55.51#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.07:14:55.51#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.07:14:55.51#ibcon#enter wrdev, iclass 29, count 0 2006.173.07:14:55.51#ibcon#first serial, iclass 29, count 0 2006.173.07:14:55.51#ibcon#enter sib2, iclass 29, count 0 2006.173.07:14:55.51#ibcon#flushed, iclass 29, count 0 2006.173.07:14:55.51#ibcon#about to write, iclass 29, count 0 2006.173.07:14:55.51#ibcon#wrote, iclass 29, count 0 2006.173.07:14:55.51#ibcon#about to read 3, iclass 29, count 0 2006.173.07:14:55.53#ibcon#read 3, iclass 29, count 0 2006.173.07:14:55.53#ibcon#about to read 4, iclass 29, count 0 2006.173.07:14:55.53#ibcon#read 4, iclass 29, count 0 2006.173.07:14:55.53#ibcon#about to read 5, iclass 29, count 0 2006.173.07:14:55.53#ibcon#read 5, iclass 29, count 0 2006.173.07:14:55.53#ibcon#about to read 6, iclass 29, count 0 2006.173.07:14:55.53#ibcon#read 6, iclass 29, count 0 2006.173.07:14:55.53#ibcon#end of sib2, iclass 29, count 0 2006.173.07:14:55.53#ibcon#*mode == 0, iclass 29, count 0 2006.173.07:14:55.53#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.07:14:55.53#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.07:14:55.53#ibcon#*before write, iclass 29, count 0 2006.173.07:14:55.53#ibcon#enter sib2, iclass 29, count 0 2006.173.07:14:55.53#ibcon#flushed, iclass 29, count 0 2006.173.07:14:55.53#ibcon#about to write, iclass 29, count 0 2006.173.07:14:55.53#ibcon#wrote, iclass 29, count 0 2006.173.07:14:55.53#ibcon#about to read 3, iclass 29, count 0 2006.173.07:14:55.57#ibcon#read 3, iclass 29, count 0 2006.173.07:14:55.57#ibcon#about to read 4, iclass 29, count 0 2006.173.07:14:55.57#ibcon#read 4, iclass 29, count 0 2006.173.07:14:55.57#ibcon#about to read 5, iclass 29, count 0 2006.173.07:14:55.57#ibcon#read 5, iclass 29, count 0 2006.173.07:14:55.57#ibcon#about to read 6, iclass 29, count 0 2006.173.07:14:55.57#ibcon#read 6, iclass 29, count 0 2006.173.07:14:55.57#ibcon#end of sib2, iclass 29, count 0 2006.173.07:14:55.57#ibcon#*after write, iclass 29, count 0 2006.173.07:14:55.57#ibcon#*before return 0, iclass 29, count 0 2006.173.07:14:55.57#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.07:14:55.57#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.07:14:55.57#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.07:14:55.57#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.07:14:55.57$vck44/vb=8,4 2006.173.07:14:55.57#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.07:14:55.57#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.07:14:55.57#ibcon#ireg 11 cls_cnt 2 2006.173.07:14:55.57#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.07:14:55.63#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.07:14:55.63#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.07:14:55.63#ibcon#enter wrdev, iclass 31, count 2 2006.173.07:14:55.63#ibcon#first serial, iclass 31, count 2 2006.173.07:14:55.63#ibcon#enter sib2, iclass 31, count 2 2006.173.07:14:55.63#ibcon#flushed, iclass 31, count 2 2006.173.07:14:55.63#ibcon#about to write, iclass 31, count 2 2006.173.07:14:55.63#ibcon#wrote, iclass 31, count 2 2006.173.07:14:55.63#ibcon#about to read 3, iclass 31, count 2 2006.173.07:14:55.65#ibcon#read 3, iclass 31, count 2 2006.173.07:14:55.65#ibcon#about to read 4, iclass 31, count 2 2006.173.07:14:55.65#ibcon#read 4, iclass 31, count 2 2006.173.07:14:55.65#ibcon#about to read 5, iclass 31, count 2 2006.173.07:14:55.65#ibcon#read 5, iclass 31, count 2 2006.173.07:14:55.65#ibcon#about to read 6, iclass 31, count 2 2006.173.07:14:55.65#ibcon#read 6, iclass 31, count 2 2006.173.07:14:55.65#ibcon#end of sib2, iclass 31, count 2 2006.173.07:14:55.65#ibcon#*mode == 0, iclass 31, count 2 2006.173.07:14:55.65#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.07:14:55.65#ibcon#[27=AT08-04\r\n] 2006.173.07:14:55.65#ibcon#*before write, iclass 31, count 2 2006.173.07:14:55.65#ibcon#enter sib2, iclass 31, count 2 2006.173.07:14:55.65#ibcon#flushed, iclass 31, count 2 2006.173.07:14:55.65#ibcon#about to write, iclass 31, count 2 2006.173.07:14:55.65#ibcon#wrote, iclass 31, count 2 2006.173.07:14:55.65#ibcon#about to read 3, iclass 31, count 2 2006.173.07:14:55.68#ibcon#read 3, iclass 31, count 2 2006.173.07:14:55.68#ibcon#about to read 4, iclass 31, count 2 2006.173.07:14:55.68#ibcon#read 4, iclass 31, count 2 2006.173.07:14:55.68#ibcon#about to read 5, iclass 31, count 2 2006.173.07:14:55.68#ibcon#read 5, iclass 31, count 2 2006.173.07:14:55.68#ibcon#about to read 6, iclass 31, count 2 2006.173.07:14:55.68#ibcon#read 6, iclass 31, count 2 2006.173.07:14:55.68#ibcon#end of sib2, iclass 31, count 2 2006.173.07:14:55.68#ibcon#*after write, iclass 31, count 2 2006.173.07:14:55.68#ibcon#*before return 0, iclass 31, count 2 2006.173.07:14:55.68#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.07:14:55.68#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.07:14:55.68#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.07:14:55.68#ibcon#ireg 7 cls_cnt 0 2006.173.07:14:55.68#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.07:14:55.80#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.07:14:55.80#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.07:14:55.80#ibcon#enter wrdev, iclass 31, count 0 2006.173.07:14:55.80#ibcon#first serial, iclass 31, count 0 2006.173.07:14:55.80#ibcon#enter sib2, iclass 31, count 0 2006.173.07:14:55.80#ibcon#flushed, iclass 31, count 0 2006.173.07:14:55.80#ibcon#about to write, iclass 31, count 0 2006.173.07:14:55.80#ibcon#wrote, iclass 31, count 0 2006.173.07:14:55.80#ibcon#about to read 3, iclass 31, count 0 2006.173.07:14:55.82#ibcon#read 3, iclass 31, count 0 2006.173.07:14:55.82#ibcon#about to read 4, iclass 31, count 0 2006.173.07:14:55.82#ibcon#read 4, iclass 31, count 0 2006.173.07:14:55.82#ibcon#about to read 5, iclass 31, count 0 2006.173.07:14:55.82#ibcon#read 5, iclass 31, count 0 2006.173.07:14:55.82#ibcon#about to read 6, iclass 31, count 0 2006.173.07:14:55.82#ibcon#read 6, iclass 31, count 0 2006.173.07:14:55.82#ibcon#end of sib2, iclass 31, count 0 2006.173.07:14:55.82#ibcon#*mode == 0, iclass 31, count 0 2006.173.07:14:55.82#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.07:14:55.82#ibcon#[27=USB\r\n] 2006.173.07:14:55.82#ibcon#*before write, iclass 31, count 0 2006.173.07:14:55.82#ibcon#enter sib2, iclass 31, count 0 2006.173.07:14:55.82#ibcon#flushed, iclass 31, count 0 2006.173.07:14:55.82#ibcon#about to write, iclass 31, count 0 2006.173.07:14:55.82#ibcon#wrote, iclass 31, count 0 2006.173.07:14:55.82#ibcon#about to read 3, iclass 31, count 0 2006.173.07:14:55.85#ibcon#read 3, iclass 31, count 0 2006.173.07:14:55.85#ibcon#about to read 4, iclass 31, count 0 2006.173.07:14:55.85#ibcon#read 4, iclass 31, count 0 2006.173.07:14:55.85#ibcon#about to read 5, iclass 31, count 0 2006.173.07:14:55.85#ibcon#read 5, iclass 31, count 0 2006.173.07:14:55.85#ibcon#about to read 6, iclass 31, count 0 2006.173.07:14:55.85#ibcon#read 6, iclass 31, count 0 2006.173.07:14:55.85#ibcon#end of sib2, iclass 31, count 0 2006.173.07:14:55.85#ibcon#*after write, iclass 31, count 0 2006.173.07:14:55.85#ibcon#*before return 0, iclass 31, count 0 2006.173.07:14:55.85#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.07:14:55.85#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.07:14:55.85#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.07:14:55.85#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.07:14:55.85$vck44/vabw=wide 2006.173.07:14:55.85#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.07:14:55.85#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.07:14:55.85#ibcon#ireg 8 cls_cnt 0 2006.173.07:14:55.85#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.07:14:55.85#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.07:14:55.85#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.07:14:55.85#ibcon#enter wrdev, iclass 33, count 0 2006.173.07:14:55.85#ibcon#first serial, iclass 33, count 0 2006.173.07:14:55.85#ibcon#enter sib2, iclass 33, count 0 2006.173.07:14:55.85#ibcon#flushed, iclass 33, count 0 2006.173.07:14:55.85#ibcon#about to write, iclass 33, count 0 2006.173.07:14:55.85#ibcon#wrote, iclass 33, count 0 2006.173.07:14:55.85#ibcon#about to read 3, iclass 33, count 0 2006.173.07:14:55.87#ibcon#read 3, iclass 33, count 0 2006.173.07:14:55.87#ibcon#about to read 4, iclass 33, count 0 2006.173.07:14:55.87#ibcon#read 4, iclass 33, count 0 2006.173.07:14:55.87#ibcon#about to read 5, iclass 33, count 0 2006.173.07:14:55.87#ibcon#read 5, iclass 33, count 0 2006.173.07:14:55.87#ibcon#about to read 6, iclass 33, count 0 2006.173.07:14:55.87#ibcon#read 6, iclass 33, count 0 2006.173.07:14:55.87#ibcon#end of sib2, iclass 33, count 0 2006.173.07:14:55.87#ibcon#*mode == 0, iclass 33, count 0 2006.173.07:14:55.87#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.07:14:55.87#ibcon#[25=BW32\r\n] 2006.173.07:14:55.87#ibcon#*before write, iclass 33, count 0 2006.173.07:14:55.87#ibcon#enter sib2, iclass 33, count 0 2006.173.07:14:55.87#ibcon#flushed, iclass 33, count 0 2006.173.07:14:55.87#ibcon#about to write, iclass 33, count 0 2006.173.07:14:55.87#ibcon#wrote, iclass 33, count 0 2006.173.07:14:55.87#ibcon#about to read 3, iclass 33, count 0 2006.173.07:14:55.90#ibcon#read 3, iclass 33, count 0 2006.173.07:14:55.90#ibcon#about to read 4, iclass 33, count 0 2006.173.07:14:55.90#ibcon#read 4, iclass 33, count 0 2006.173.07:14:55.90#ibcon#about to read 5, iclass 33, count 0 2006.173.07:14:55.90#ibcon#read 5, iclass 33, count 0 2006.173.07:14:55.90#ibcon#about to read 6, iclass 33, count 0 2006.173.07:14:55.90#ibcon#read 6, iclass 33, count 0 2006.173.07:14:55.90#ibcon#end of sib2, iclass 33, count 0 2006.173.07:14:55.90#ibcon#*after write, iclass 33, count 0 2006.173.07:14:55.90#ibcon#*before return 0, iclass 33, count 0 2006.173.07:14:55.90#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.07:14:55.90#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.07:14:55.90#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.07:14:55.90#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.07:14:55.90$vck44/vbbw=wide 2006.173.07:14:55.90#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.07:14:55.90#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.07:14:55.90#ibcon#ireg 8 cls_cnt 0 2006.173.07:14:55.90#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.07:14:55.97#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.07:14:55.97#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.07:14:55.97#ibcon#enter wrdev, iclass 35, count 0 2006.173.07:14:55.97#ibcon#first serial, iclass 35, count 0 2006.173.07:14:55.97#ibcon#enter sib2, iclass 35, count 0 2006.173.07:14:55.97#ibcon#flushed, iclass 35, count 0 2006.173.07:14:55.97#ibcon#about to write, iclass 35, count 0 2006.173.07:14:55.97#ibcon#wrote, iclass 35, count 0 2006.173.07:14:55.97#ibcon#about to read 3, iclass 35, count 0 2006.173.07:14:55.99#ibcon#read 3, iclass 35, count 0 2006.173.07:14:55.99#ibcon#about to read 4, iclass 35, count 0 2006.173.07:14:55.99#ibcon#read 4, iclass 35, count 0 2006.173.07:14:55.99#ibcon#about to read 5, iclass 35, count 0 2006.173.07:14:55.99#ibcon#read 5, iclass 35, count 0 2006.173.07:14:55.99#ibcon#about to read 6, iclass 35, count 0 2006.173.07:14:55.99#ibcon#read 6, iclass 35, count 0 2006.173.07:14:55.99#ibcon#end of sib2, iclass 35, count 0 2006.173.07:14:55.99#ibcon#*mode == 0, iclass 35, count 0 2006.173.07:14:55.99#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.07:14:55.99#ibcon#[27=BW32\r\n] 2006.173.07:14:55.99#ibcon#*before write, iclass 35, count 0 2006.173.07:14:55.99#ibcon#enter sib2, iclass 35, count 0 2006.173.07:14:55.99#ibcon#flushed, iclass 35, count 0 2006.173.07:14:55.99#ibcon#about to write, iclass 35, count 0 2006.173.07:14:55.99#ibcon#wrote, iclass 35, count 0 2006.173.07:14:55.99#ibcon#about to read 3, iclass 35, count 0 2006.173.07:14:56.02#ibcon#read 3, iclass 35, count 0 2006.173.07:14:56.02#ibcon#about to read 4, iclass 35, count 0 2006.173.07:14:56.02#ibcon#read 4, iclass 35, count 0 2006.173.07:14:56.02#ibcon#about to read 5, iclass 35, count 0 2006.173.07:14:56.02#ibcon#read 5, iclass 35, count 0 2006.173.07:14:56.02#ibcon#about to read 6, iclass 35, count 0 2006.173.07:14:56.02#ibcon#read 6, iclass 35, count 0 2006.173.07:14:56.02#ibcon#end of sib2, iclass 35, count 0 2006.173.07:14:56.02#ibcon#*after write, iclass 35, count 0 2006.173.07:14:56.02#ibcon#*before return 0, iclass 35, count 0 2006.173.07:14:56.02#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.07:14:56.02#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.07:14:56.02#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.07:14:56.02#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.07:14:56.02$setupk4/ifdk4 2006.173.07:14:56.02$ifdk4/lo= 2006.173.07:14:56.03$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.07:14:56.03$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.07:14:56.03$ifdk4/patch= 2006.173.07:14:56.03$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.07:14:56.03$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.07:14:56.03$setupk4/!*+20s 2006.173.07:14:56.57#abcon#<5=/04 0.3 0.8 23.81 811004.6\r\n> 2006.173.07:14:56.59#abcon#{5=INTERFACE CLEAR} 2006.173.07:14:56.65#abcon#[5=S1D000X0/0*\r\n] 2006.173.07:15:06.74#abcon#<5=/03 0.3 0.8 23.82 811004.6\r\n> 2006.173.07:15:06.76#abcon#{5=INTERFACE CLEAR} 2006.173.07:15:06.82#abcon#[5=S1D000X0/0*\r\n] 2006.173.07:15:09.16$setupk4/"tpicd 2006.173.07:15:09.16$setupk4/echo=off 2006.173.07:15:09.16$setupk4/xlog=off 2006.173.07:15:09.16:!2006.173.07:20:32 2006.173.07:15:36.14#trakl#Source acquired 2006.173.07:15:36.15#flagr#flagr/antenna,acquired 2006.173.07:20:32.00:preob 2006.173.07:20:32.13/onsource/TRACKING 2006.173.07:20:32.13:!2006.173.07:20:42 2006.173.07:20:42.00:"tape 2006.173.07:20:42.00:"st=record 2006.173.07:20:42.00:data_valid=on 2006.173.07:20:42.01:midob 2006.173.07:20:43.13/onsource/TRACKING 2006.173.07:20:43.13/wx/23.78,1004.5,83 2006.173.07:20:43.25/cable/+6.5041E-03 2006.173.07:20:44.34/va/01,07,usb,yes,37,39 2006.173.07:20:44.34/va/02,06,usb,yes,36,37 2006.173.07:20:44.34/va/03,05,usb,yes,46,48 2006.173.07:20:44.34/va/04,06,usb,yes,37,39 2006.173.07:20:44.34/va/05,04,usb,yes,29,30 2006.173.07:20:44.34/va/06,03,usb,yes,41,41 2006.173.07:20:44.34/va/07,04,usb,yes,33,34 2006.173.07:20:44.34/va/08,04,usb,yes,28,34 2006.173.07:20:44.57/valo/01,524.99,yes,locked 2006.173.07:20:44.57/valo/02,534.99,yes,locked 2006.173.07:20:44.57/valo/03,564.99,yes,locked 2006.173.07:20:44.57/valo/04,624.99,yes,locked 2006.173.07:20:44.57/valo/05,734.99,yes,locked 2006.173.07:20:44.57/valo/06,814.99,yes,locked 2006.173.07:20:44.57/valo/07,864.99,yes,locked 2006.173.07:20:44.57/valo/08,884.99,yes,locked 2006.173.07:20:45.66/vb/01,04,usb,yes,30,28 2006.173.07:20:45.66/vb/02,04,usb,yes,32,33 2006.173.07:20:45.66/vb/03,04,usb,yes,29,32 2006.173.07:20:45.66/vb/04,04,usb,yes,34,33 2006.173.07:20:45.66/vb/05,04,usb,yes,26,29 2006.173.07:20:45.66/vb/06,04,usb,yes,31,27 2006.173.07:20:45.66/vb/07,04,usb,yes,30,30 2006.173.07:20:45.66/vb/08,04,usb,yes,28,31 2006.173.07:20:45.90/vblo/01,629.99,yes,locked 2006.173.07:20:45.90/vblo/02,634.99,yes,locked 2006.173.07:20:45.90/vblo/03,649.99,yes,locked 2006.173.07:20:45.90/vblo/04,679.99,yes,locked 2006.173.07:20:45.90/vblo/05,709.99,yes,locked 2006.173.07:20:45.90/vblo/06,719.99,yes,locked 2006.173.07:20:45.90/vblo/07,734.99,yes,locked 2006.173.07:20:45.90/vblo/08,744.99,yes,locked 2006.173.07:20:46.05/vabw/8 2006.173.07:20:46.20/vbbw/8 2006.173.07:20:46.29/xfe/off,on,15.2 2006.173.07:20:46.67/ifatt/23,28,28,28 2006.173.07:20:47.07/fmout-gps/S +3.97E-07 2006.173.07:20:47.11:!2006.173.07:21:52 2006.173.07:21:52.01:data_valid=off 2006.173.07:21:52.02:"et 2006.173.07:21:52.02:!+3s 2006.173.07:21:55.03:"tape 2006.173.07:21:55.04:postob 2006.173.07:21:55.25/cable/+6.5035E-03 2006.173.07:21:55.26/wx/23.78,1004.5,83 2006.173.07:21:55.31/fmout-gps/S +3.97E-07 2006.173.07:21:55.32:scan_name=173-0724,jd0606,110 2006.173.07:21:55.32:source=1334-127,133739.78,-125724.7,2000.0,ccw 2006.173.07:21:56.14#flagr#flagr/antenna,new-source 2006.173.07:21:56.15:checkk5 2006.173.07:21:56.56/chk_autoobs//k5ts1/ autoobs is running! 2006.173.07:21:56.97/chk_autoobs//k5ts2/ autoobs is running! 2006.173.07:21:57.37/chk_autoobs//k5ts3/ autoobs is running! 2006.173.07:21:57.78/chk_autoobs//k5ts4/ autoobs is running! 2006.173.07:21:58.21/chk_obsdata//k5ts1/T1730720??a.dat file size is correct (nominal:280MB, actual:276MB). 2006.173.07:21:58.61/chk_obsdata//k5ts2/T1730720??b.dat file size is correct (nominal:280MB, actual:276MB). 2006.173.07:21:59.03/chk_obsdata//k5ts3/T1730720??c.dat file size is correct (nominal:280MB, actual:276MB). 2006.173.07:21:59.42/chk_obsdata//k5ts4/T1730720??d.dat file size is correct (nominal:280MB, actual:276MB). 2006.173.07:22:00.15/k5log//k5ts1_log_newline 2006.173.07:22:00.85/k5log//k5ts2_log_newline 2006.173.07:22:01.56/k5log//k5ts3_log_newline 2006.173.07:22:02.27/k5log//k5ts4_log_newline 2006.173.07:22:02.29/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.07:22:02.29:setupk4=1 2006.173.07:22:02.29$setupk4/echo=on 2006.173.07:22:02.29$setupk4/pcalon 2006.173.07:22:02.29$pcalon/"no phase cal control is implemented here 2006.173.07:22:02.29$setupk4/"tpicd=stop 2006.173.07:22:02.29$setupk4/"rec=synch_on 2006.173.07:22:02.29$setupk4/"rec_mode=128 2006.173.07:22:02.29$setupk4/!* 2006.173.07:22:02.29$setupk4/recpk4 2006.173.07:22:02.30$recpk4/recpatch= 2006.173.07:22:02.30$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.07:22:02.30$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.07:22:02.30$setupk4/vck44 2006.173.07:22:02.30$vck44/valo=1,524.99 2006.173.07:22:02.30#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.07:22:02.30#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.07:22:02.30#ibcon#ireg 17 cls_cnt 0 2006.173.07:22:02.30#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.07:22:02.30#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.07:22:02.30#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.07:22:02.30#ibcon#enter wrdev, iclass 23, count 0 2006.173.07:22:02.30#ibcon#first serial, iclass 23, count 0 2006.173.07:22:02.30#ibcon#enter sib2, iclass 23, count 0 2006.173.07:22:02.30#ibcon#flushed, iclass 23, count 0 2006.173.07:22:02.30#ibcon#about to write, iclass 23, count 0 2006.173.07:22:02.30#ibcon#wrote, iclass 23, count 0 2006.173.07:22:02.30#ibcon#about to read 3, iclass 23, count 0 2006.173.07:22:02.31#ibcon#read 3, iclass 23, count 0 2006.173.07:22:02.31#ibcon#about to read 4, iclass 23, count 0 2006.173.07:22:02.31#ibcon#read 4, iclass 23, count 0 2006.173.07:22:02.31#ibcon#about to read 5, iclass 23, count 0 2006.173.07:22:02.31#ibcon#read 5, iclass 23, count 0 2006.173.07:22:02.31#ibcon#about to read 6, iclass 23, count 0 2006.173.07:22:02.31#ibcon#read 6, iclass 23, count 0 2006.173.07:22:02.31#ibcon#end of sib2, iclass 23, count 0 2006.173.07:22:02.31#ibcon#*mode == 0, iclass 23, count 0 2006.173.07:22:02.31#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.07:22:02.31#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.07:22:02.31#ibcon#*before write, iclass 23, count 0 2006.173.07:22:02.31#ibcon#enter sib2, iclass 23, count 0 2006.173.07:22:02.31#ibcon#flushed, iclass 23, count 0 2006.173.07:22:02.31#ibcon#about to write, iclass 23, count 0 2006.173.07:22:02.31#ibcon#wrote, iclass 23, count 0 2006.173.07:22:02.31#ibcon#about to read 3, iclass 23, count 0 2006.173.07:22:02.36#ibcon#read 3, iclass 23, count 0 2006.173.07:22:02.36#ibcon#about to read 4, iclass 23, count 0 2006.173.07:22:02.36#ibcon#read 4, iclass 23, count 0 2006.173.07:22:02.36#ibcon#about to read 5, iclass 23, count 0 2006.173.07:22:02.36#ibcon#read 5, iclass 23, count 0 2006.173.07:22:02.36#ibcon#about to read 6, iclass 23, count 0 2006.173.07:22:02.36#ibcon#read 6, iclass 23, count 0 2006.173.07:22:02.36#ibcon#end of sib2, iclass 23, count 0 2006.173.07:22:02.36#ibcon#*after write, iclass 23, count 0 2006.173.07:22:02.36#ibcon#*before return 0, iclass 23, count 0 2006.173.07:22:02.36#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.07:22:02.36#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.07:22:02.36#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.07:22:02.36#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.07:22:02.36$vck44/va=1,7 2006.173.07:22:02.36#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.07:22:02.36#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.07:22:02.36#ibcon#ireg 11 cls_cnt 2 2006.173.07:22:02.36#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.07:22:02.36#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.07:22:02.36#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.07:22:02.36#ibcon#enter wrdev, iclass 25, count 2 2006.173.07:22:02.36#ibcon#first serial, iclass 25, count 2 2006.173.07:22:02.36#ibcon#enter sib2, iclass 25, count 2 2006.173.07:22:02.36#ibcon#flushed, iclass 25, count 2 2006.173.07:22:02.36#ibcon#about to write, iclass 25, count 2 2006.173.07:22:02.36#ibcon#wrote, iclass 25, count 2 2006.173.07:22:02.36#ibcon#about to read 3, iclass 25, count 2 2006.173.07:22:02.38#ibcon#read 3, iclass 25, count 2 2006.173.07:22:02.38#ibcon#about to read 4, iclass 25, count 2 2006.173.07:22:02.38#ibcon#read 4, iclass 25, count 2 2006.173.07:22:02.38#ibcon#about to read 5, iclass 25, count 2 2006.173.07:22:02.38#ibcon#read 5, iclass 25, count 2 2006.173.07:22:02.38#ibcon#about to read 6, iclass 25, count 2 2006.173.07:22:02.38#ibcon#read 6, iclass 25, count 2 2006.173.07:22:02.38#ibcon#end of sib2, iclass 25, count 2 2006.173.07:22:02.38#ibcon#*mode == 0, iclass 25, count 2 2006.173.07:22:02.38#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.07:22:02.38#ibcon#[25=AT01-07\r\n] 2006.173.07:22:02.38#ibcon#*before write, iclass 25, count 2 2006.173.07:22:02.38#ibcon#enter sib2, iclass 25, count 2 2006.173.07:22:02.38#ibcon#flushed, iclass 25, count 2 2006.173.07:22:02.38#ibcon#about to write, iclass 25, count 2 2006.173.07:22:02.38#ibcon#wrote, iclass 25, count 2 2006.173.07:22:02.38#ibcon#about to read 3, iclass 25, count 2 2006.173.07:22:02.41#ibcon#read 3, iclass 25, count 2 2006.173.07:22:02.41#ibcon#about to read 4, iclass 25, count 2 2006.173.07:22:02.41#ibcon#read 4, iclass 25, count 2 2006.173.07:22:02.41#ibcon#about to read 5, iclass 25, count 2 2006.173.07:22:02.41#ibcon#read 5, iclass 25, count 2 2006.173.07:22:02.41#ibcon#about to read 6, iclass 25, count 2 2006.173.07:22:02.41#ibcon#read 6, iclass 25, count 2 2006.173.07:22:02.41#ibcon#end of sib2, iclass 25, count 2 2006.173.07:22:02.41#ibcon#*after write, iclass 25, count 2 2006.173.07:22:02.41#ibcon#*before return 0, iclass 25, count 2 2006.173.07:22:02.41#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.07:22:02.41#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.07:22:02.41#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.07:22:02.41#ibcon#ireg 7 cls_cnt 0 2006.173.07:22:02.41#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.07:22:02.53#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.07:22:02.53#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.07:22:02.53#ibcon#enter wrdev, iclass 25, count 0 2006.173.07:22:02.53#ibcon#first serial, iclass 25, count 0 2006.173.07:22:02.53#ibcon#enter sib2, iclass 25, count 0 2006.173.07:22:02.53#ibcon#flushed, iclass 25, count 0 2006.173.07:22:02.53#ibcon#about to write, iclass 25, count 0 2006.173.07:22:02.53#ibcon#wrote, iclass 25, count 0 2006.173.07:22:02.53#ibcon#about to read 3, iclass 25, count 0 2006.173.07:22:02.55#ibcon#read 3, iclass 25, count 0 2006.173.07:22:02.55#ibcon#about to read 4, iclass 25, count 0 2006.173.07:22:02.55#ibcon#read 4, iclass 25, count 0 2006.173.07:22:02.55#ibcon#about to read 5, iclass 25, count 0 2006.173.07:22:02.55#ibcon#read 5, iclass 25, count 0 2006.173.07:22:02.55#ibcon#about to read 6, iclass 25, count 0 2006.173.07:22:02.55#ibcon#read 6, iclass 25, count 0 2006.173.07:22:02.55#ibcon#end of sib2, iclass 25, count 0 2006.173.07:22:02.55#ibcon#*mode == 0, iclass 25, count 0 2006.173.07:22:02.55#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.07:22:02.55#ibcon#[25=USB\r\n] 2006.173.07:22:02.55#ibcon#*before write, iclass 25, count 0 2006.173.07:22:02.55#ibcon#enter sib2, iclass 25, count 0 2006.173.07:22:02.55#ibcon#flushed, iclass 25, count 0 2006.173.07:22:02.55#ibcon#about to write, iclass 25, count 0 2006.173.07:22:02.55#ibcon#wrote, iclass 25, count 0 2006.173.07:22:02.55#ibcon#about to read 3, iclass 25, count 0 2006.173.07:22:02.58#ibcon#read 3, iclass 25, count 0 2006.173.07:22:02.58#ibcon#about to read 4, iclass 25, count 0 2006.173.07:22:02.58#ibcon#read 4, iclass 25, count 0 2006.173.07:22:02.58#ibcon#about to read 5, iclass 25, count 0 2006.173.07:22:02.58#ibcon#read 5, iclass 25, count 0 2006.173.07:22:02.58#ibcon#about to read 6, iclass 25, count 0 2006.173.07:22:02.58#ibcon#read 6, iclass 25, count 0 2006.173.07:22:02.58#ibcon#end of sib2, iclass 25, count 0 2006.173.07:22:02.58#ibcon#*after write, iclass 25, count 0 2006.173.07:22:02.58#ibcon#*before return 0, iclass 25, count 0 2006.173.07:22:02.58#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.07:22:02.58#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.07:22:02.58#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.07:22:02.58#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.07:22:02.58$vck44/valo=2,534.99 2006.173.07:22:02.58#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.07:22:02.58#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.07:22:02.58#ibcon#ireg 17 cls_cnt 0 2006.173.07:22:02.58#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.07:22:02.58#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.07:22:02.58#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.07:22:02.58#ibcon#enter wrdev, iclass 27, count 0 2006.173.07:22:02.58#ibcon#first serial, iclass 27, count 0 2006.173.07:22:02.58#ibcon#enter sib2, iclass 27, count 0 2006.173.07:22:02.58#ibcon#flushed, iclass 27, count 0 2006.173.07:22:02.58#ibcon#about to write, iclass 27, count 0 2006.173.07:22:02.58#ibcon#wrote, iclass 27, count 0 2006.173.07:22:02.58#ibcon#about to read 3, iclass 27, count 0 2006.173.07:22:02.60#ibcon#read 3, iclass 27, count 0 2006.173.07:22:02.60#ibcon#about to read 4, iclass 27, count 0 2006.173.07:22:02.60#ibcon#read 4, iclass 27, count 0 2006.173.07:22:02.60#ibcon#about to read 5, iclass 27, count 0 2006.173.07:22:02.60#ibcon#read 5, iclass 27, count 0 2006.173.07:22:02.60#ibcon#about to read 6, iclass 27, count 0 2006.173.07:22:02.60#ibcon#read 6, iclass 27, count 0 2006.173.07:22:02.60#ibcon#end of sib2, iclass 27, count 0 2006.173.07:22:02.60#ibcon#*mode == 0, iclass 27, count 0 2006.173.07:22:02.60#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.07:22:02.60#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.07:22:02.60#ibcon#*before write, iclass 27, count 0 2006.173.07:22:02.60#ibcon#enter sib2, iclass 27, count 0 2006.173.07:22:02.60#ibcon#flushed, iclass 27, count 0 2006.173.07:22:02.60#ibcon#about to write, iclass 27, count 0 2006.173.07:22:02.60#ibcon#wrote, iclass 27, count 0 2006.173.07:22:02.60#ibcon#about to read 3, iclass 27, count 0 2006.173.07:22:02.64#ibcon#read 3, iclass 27, count 0 2006.173.07:22:02.64#ibcon#about to read 4, iclass 27, count 0 2006.173.07:22:02.64#ibcon#read 4, iclass 27, count 0 2006.173.07:22:02.64#ibcon#about to read 5, iclass 27, count 0 2006.173.07:22:02.64#ibcon#read 5, iclass 27, count 0 2006.173.07:22:02.64#ibcon#about to read 6, iclass 27, count 0 2006.173.07:22:02.64#ibcon#read 6, iclass 27, count 0 2006.173.07:22:02.64#ibcon#end of sib2, iclass 27, count 0 2006.173.07:22:02.64#ibcon#*after write, iclass 27, count 0 2006.173.07:22:02.64#ibcon#*before return 0, iclass 27, count 0 2006.173.07:22:02.64#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.07:22:02.64#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.07:22:02.64#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.07:22:02.64#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.07:22:02.64$vck44/va=2,6 2006.173.07:22:02.64#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.07:22:02.64#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.07:22:02.64#ibcon#ireg 11 cls_cnt 2 2006.173.07:22:02.64#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.07:22:02.70#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.07:22:02.70#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.07:22:02.70#ibcon#enter wrdev, iclass 29, count 2 2006.173.07:22:02.70#ibcon#first serial, iclass 29, count 2 2006.173.07:22:02.70#ibcon#enter sib2, iclass 29, count 2 2006.173.07:22:02.70#ibcon#flushed, iclass 29, count 2 2006.173.07:22:02.70#ibcon#about to write, iclass 29, count 2 2006.173.07:22:02.70#ibcon#wrote, iclass 29, count 2 2006.173.07:22:02.70#ibcon#about to read 3, iclass 29, count 2 2006.173.07:22:02.72#ibcon#read 3, iclass 29, count 2 2006.173.07:22:02.72#ibcon#about to read 4, iclass 29, count 2 2006.173.07:22:02.72#ibcon#read 4, iclass 29, count 2 2006.173.07:22:02.72#ibcon#about to read 5, iclass 29, count 2 2006.173.07:22:02.72#ibcon#read 5, iclass 29, count 2 2006.173.07:22:02.72#ibcon#about to read 6, iclass 29, count 2 2006.173.07:22:02.72#ibcon#read 6, iclass 29, count 2 2006.173.07:22:02.72#ibcon#end of sib2, iclass 29, count 2 2006.173.07:22:02.72#ibcon#*mode == 0, iclass 29, count 2 2006.173.07:22:02.72#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.07:22:02.72#ibcon#[25=AT02-06\r\n] 2006.173.07:22:02.72#ibcon#*before write, iclass 29, count 2 2006.173.07:22:02.72#ibcon#enter sib2, iclass 29, count 2 2006.173.07:22:02.72#ibcon#flushed, iclass 29, count 2 2006.173.07:22:02.72#ibcon#about to write, iclass 29, count 2 2006.173.07:22:02.72#ibcon#wrote, iclass 29, count 2 2006.173.07:22:02.72#ibcon#about to read 3, iclass 29, count 2 2006.173.07:22:02.75#ibcon#read 3, iclass 29, count 2 2006.173.07:22:02.75#ibcon#about to read 4, iclass 29, count 2 2006.173.07:22:02.75#ibcon#read 4, iclass 29, count 2 2006.173.07:22:02.75#ibcon#about to read 5, iclass 29, count 2 2006.173.07:22:02.75#ibcon#read 5, iclass 29, count 2 2006.173.07:22:02.75#ibcon#about to read 6, iclass 29, count 2 2006.173.07:22:02.75#ibcon#read 6, iclass 29, count 2 2006.173.07:22:02.75#ibcon#end of sib2, iclass 29, count 2 2006.173.07:22:02.75#ibcon#*after write, iclass 29, count 2 2006.173.07:22:02.75#ibcon#*before return 0, iclass 29, count 2 2006.173.07:22:02.75#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.07:22:02.75#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.07:22:02.75#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.07:22:02.75#ibcon#ireg 7 cls_cnt 0 2006.173.07:22:02.75#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.07:22:02.87#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.07:22:02.87#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.07:22:02.87#ibcon#enter wrdev, iclass 29, count 0 2006.173.07:22:02.87#ibcon#first serial, iclass 29, count 0 2006.173.07:22:02.87#ibcon#enter sib2, iclass 29, count 0 2006.173.07:22:02.87#ibcon#flushed, iclass 29, count 0 2006.173.07:22:02.87#ibcon#about to write, iclass 29, count 0 2006.173.07:22:02.87#ibcon#wrote, iclass 29, count 0 2006.173.07:22:02.87#ibcon#about to read 3, iclass 29, count 0 2006.173.07:22:02.89#ibcon#read 3, iclass 29, count 0 2006.173.07:22:02.89#ibcon#about to read 4, iclass 29, count 0 2006.173.07:22:02.89#ibcon#read 4, iclass 29, count 0 2006.173.07:22:02.89#ibcon#about to read 5, iclass 29, count 0 2006.173.07:22:02.89#ibcon#read 5, iclass 29, count 0 2006.173.07:22:02.89#ibcon#about to read 6, iclass 29, count 0 2006.173.07:22:02.89#ibcon#read 6, iclass 29, count 0 2006.173.07:22:02.89#ibcon#end of sib2, iclass 29, count 0 2006.173.07:22:02.89#ibcon#*mode == 0, iclass 29, count 0 2006.173.07:22:02.89#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.07:22:02.89#ibcon#[25=USB\r\n] 2006.173.07:22:02.89#ibcon#*before write, iclass 29, count 0 2006.173.07:22:02.89#ibcon#enter sib2, iclass 29, count 0 2006.173.07:22:02.89#ibcon#flushed, iclass 29, count 0 2006.173.07:22:02.89#ibcon#about to write, iclass 29, count 0 2006.173.07:22:02.89#ibcon#wrote, iclass 29, count 0 2006.173.07:22:02.89#ibcon#about to read 3, iclass 29, count 0 2006.173.07:22:02.92#ibcon#read 3, iclass 29, count 0 2006.173.07:22:02.92#ibcon#about to read 4, iclass 29, count 0 2006.173.07:22:02.92#ibcon#read 4, iclass 29, count 0 2006.173.07:22:02.92#ibcon#about to read 5, iclass 29, count 0 2006.173.07:22:02.92#ibcon#read 5, iclass 29, count 0 2006.173.07:22:02.92#ibcon#about to read 6, iclass 29, count 0 2006.173.07:22:02.92#ibcon#read 6, iclass 29, count 0 2006.173.07:22:02.92#ibcon#end of sib2, iclass 29, count 0 2006.173.07:22:02.92#ibcon#*after write, iclass 29, count 0 2006.173.07:22:02.92#ibcon#*before return 0, iclass 29, count 0 2006.173.07:22:02.92#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.07:22:02.92#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.07:22:02.92#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.07:22:02.92#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.07:22:02.92$vck44/valo=3,564.99 2006.173.07:22:02.92#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.07:22:02.92#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.07:22:02.92#ibcon#ireg 17 cls_cnt 0 2006.173.07:22:02.92#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.07:22:02.92#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.07:22:02.92#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.07:22:02.92#ibcon#enter wrdev, iclass 31, count 0 2006.173.07:22:02.92#ibcon#first serial, iclass 31, count 0 2006.173.07:22:02.92#ibcon#enter sib2, iclass 31, count 0 2006.173.07:22:02.92#ibcon#flushed, iclass 31, count 0 2006.173.07:22:02.92#ibcon#about to write, iclass 31, count 0 2006.173.07:22:02.92#ibcon#wrote, iclass 31, count 0 2006.173.07:22:02.92#ibcon#about to read 3, iclass 31, count 0 2006.173.07:22:02.94#ibcon#read 3, iclass 31, count 0 2006.173.07:22:02.94#ibcon#about to read 4, iclass 31, count 0 2006.173.07:22:02.94#ibcon#read 4, iclass 31, count 0 2006.173.07:22:02.94#ibcon#about to read 5, iclass 31, count 0 2006.173.07:22:02.94#ibcon#read 5, iclass 31, count 0 2006.173.07:22:02.94#ibcon#about to read 6, iclass 31, count 0 2006.173.07:22:02.94#ibcon#read 6, iclass 31, count 0 2006.173.07:22:02.94#ibcon#end of sib2, iclass 31, count 0 2006.173.07:22:02.94#ibcon#*mode == 0, iclass 31, count 0 2006.173.07:22:02.94#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.07:22:02.94#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.07:22:02.94#ibcon#*before write, iclass 31, count 0 2006.173.07:22:02.94#ibcon#enter sib2, iclass 31, count 0 2006.173.07:22:02.94#ibcon#flushed, iclass 31, count 0 2006.173.07:22:02.94#ibcon#about to write, iclass 31, count 0 2006.173.07:22:02.94#ibcon#wrote, iclass 31, count 0 2006.173.07:22:02.94#ibcon#about to read 3, iclass 31, count 0 2006.173.07:22:02.98#ibcon#read 3, iclass 31, count 0 2006.173.07:22:02.98#ibcon#about to read 4, iclass 31, count 0 2006.173.07:22:02.98#ibcon#read 4, iclass 31, count 0 2006.173.07:22:02.98#ibcon#about to read 5, iclass 31, count 0 2006.173.07:22:02.98#ibcon#read 5, iclass 31, count 0 2006.173.07:22:02.98#ibcon#about to read 6, iclass 31, count 0 2006.173.07:22:02.98#ibcon#read 6, iclass 31, count 0 2006.173.07:22:02.98#ibcon#end of sib2, iclass 31, count 0 2006.173.07:22:02.98#ibcon#*after write, iclass 31, count 0 2006.173.07:22:02.98#ibcon#*before return 0, iclass 31, count 0 2006.173.07:22:02.98#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.07:22:02.98#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.07:22:02.98#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.07:22:02.98#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.07:22:02.98$vck44/va=3,5 2006.173.07:22:02.98#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.173.07:22:02.98#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.173.07:22:02.98#ibcon#ireg 11 cls_cnt 2 2006.173.07:22:02.98#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.07:22:03.04#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.07:22:03.04#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.07:22:03.04#ibcon#enter wrdev, iclass 33, count 2 2006.173.07:22:03.04#ibcon#first serial, iclass 33, count 2 2006.173.07:22:03.04#ibcon#enter sib2, iclass 33, count 2 2006.173.07:22:03.04#ibcon#flushed, iclass 33, count 2 2006.173.07:22:03.04#ibcon#about to write, iclass 33, count 2 2006.173.07:22:03.04#ibcon#wrote, iclass 33, count 2 2006.173.07:22:03.04#ibcon#about to read 3, iclass 33, count 2 2006.173.07:22:03.06#ibcon#read 3, iclass 33, count 2 2006.173.07:22:03.06#ibcon#about to read 4, iclass 33, count 2 2006.173.07:22:03.06#ibcon#read 4, iclass 33, count 2 2006.173.07:22:03.06#ibcon#about to read 5, iclass 33, count 2 2006.173.07:22:03.06#ibcon#read 5, iclass 33, count 2 2006.173.07:22:03.06#ibcon#about to read 6, iclass 33, count 2 2006.173.07:22:03.06#ibcon#read 6, iclass 33, count 2 2006.173.07:22:03.06#ibcon#end of sib2, iclass 33, count 2 2006.173.07:22:03.06#ibcon#*mode == 0, iclass 33, count 2 2006.173.07:22:03.06#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.173.07:22:03.06#ibcon#[25=AT03-05\r\n] 2006.173.07:22:03.06#ibcon#*before write, iclass 33, count 2 2006.173.07:22:03.06#ibcon#enter sib2, iclass 33, count 2 2006.173.07:22:03.06#ibcon#flushed, iclass 33, count 2 2006.173.07:22:03.06#ibcon#about to write, iclass 33, count 2 2006.173.07:22:03.06#ibcon#wrote, iclass 33, count 2 2006.173.07:22:03.06#ibcon#about to read 3, iclass 33, count 2 2006.173.07:22:03.09#ibcon#read 3, iclass 33, count 2 2006.173.07:22:03.09#ibcon#about to read 4, iclass 33, count 2 2006.173.07:22:03.09#ibcon#read 4, iclass 33, count 2 2006.173.07:22:03.09#ibcon#about to read 5, iclass 33, count 2 2006.173.07:22:03.09#ibcon#read 5, iclass 33, count 2 2006.173.07:22:03.09#ibcon#about to read 6, iclass 33, count 2 2006.173.07:22:03.09#ibcon#read 6, iclass 33, count 2 2006.173.07:22:03.09#ibcon#end of sib2, iclass 33, count 2 2006.173.07:22:03.09#ibcon#*after write, iclass 33, count 2 2006.173.07:22:03.09#ibcon#*before return 0, iclass 33, count 2 2006.173.07:22:03.09#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.07:22:03.09#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.173.07:22:03.09#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.173.07:22:03.09#ibcon#ireg 7 cls_cnt 0 2006.173.07:22:03.09#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.07:22:03.21#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.07:22:03.21#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.07:22:03.21#ibcon#enter wrdev, iclass 33, count 0 2006.173.07:22:03.21#ibcon#first serial, iclass 33, count 0 2006.173.07:22:03.21#ibcon#enter sib2, iclass 33, count 0 2006.173.07:22:03.21#ibcon#flushed, iclass 33, count 0 2006.173.07:22:03.21#ibcon#about to write, iclass 33, count 0 2006.173.07:22:03.21#ibcon#wrote, iclass 33, count 0 2006.173.07:22:03.21#ibcon#about to read 3, iclass 33, count 0 2006.173.07:22:03.23#ibcon#read 3, iclass 33, count 0 2006.173.07:22:03.23#ibcon#about to read 4, iclass 33, count 0 2006.173.07:22:03.23#ibcon#read 4, iclass 33, count 0 2006.173.07:22:03.23#ibcon#about to read 5, iclass 33, count 0 2006.173.07:22:03.23#ibcon#read 5, iclass 33, count 0 2006.173.07:22:03.23#ibcon#about to read 6, iclass 33, count 0 2006.173.07:22:03.23#ibcon#read 6, iclass 33, count 0 2006.173.07:22:03.23#ibcon#end of sib2, iclass 33, count 0 2006.173.07:22:03.23#ibcon#*mode == 0, iclass 33, count 0 2006.173.07:22:03.23#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.07:22:03.23#ibcon#[25=USB\r\n] 2006.173.07:22:03.23#ibcon#*before write, iclass 33, count 0 2006.173.07:22:03.23#ibcon#enter sib2, iclass 33, count 0 2006.173.07:22:03.23#ibcon#flushed, iclass 33, count 0 2006.173.07:22:03.23#ibcon#about to write, iclass 33, count 0 2006.173.07:22:03.23#ibcon#wrote, iclass 33, count 0 2006.173.07:22:03.23#ibcon#about to read 3, iclass 33, count 0 2006.173.07:22:03.26#ibcon#read 3, iclass 33, count 0 2006.173.07:22:03.26#ibcon#about to read 4, iclass 33, count 0 2006.173.07:22:03.26#ibcon#read 4, iclass 33, count 0 2006.173.07:22:03.26#ibcon#about to read 5, iclass 33, count 0 2006.173.07:22:03.26#ibcon#read 5, iclass 33, count 0 2006.173.07:22:03.26#ibcon#about to read 6, iclass 33, count 0 2006.173.07:22:03.26#ibcon#read 6, iclass 33, count 0 2006.173.07:22:03.26#ibcon#end of sib2, iclass 33, count 0 2006.173.07:22:03.26#ibcon#*after write, iclass 33, count 0 2006.173.07:22:03.26#ibcon#*before return 0, iclass 33, count 0 2006.173.07:22:03.26#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.07:22:03.26#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.173.07:22:03.26#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.07:22:03.26#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.07:22:03.26$vck44/valo=4,624.99 2006.173.07:22:03.26#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.07:22:03.26#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.07:22:03.26#ibcon#ireg 17 cls_cnt 0 2006.173.07:22:03.26#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.07:22:03.26#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.07:22:03.26#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.07:22:03.26#ibcon#enter wrdev, iclass 35, count 0 2006.173.07:22:03.26#ibcon#first serial, iclass 35, count 0 2006.173.07:22:03.26#ibcon#enter sib2, iclass 35, count 0 2006.173.07:22:03.26#ibcon#flushed, iclass 35, count 0 2006.173.07:22:03.26#ibcon#about to write, iclass 35, count 0 2006.173.07:22:03.26#ibcon#wrote, iclass 35, count 0 2006.173.07:22:03.26#ibcon#about to read 3, iclass 35, count 0 2006.173.07:22:03.28#ibcon#read 3, iclass 35, count 0 2006.173.07:22:03.28#ibcon#about to read 4, iclass 35, count 0 2006.173.07:22:03.28#ibcon#read 4, iclass 35, count 0 2006.173.07:22:03.28#ibcon#about to read 5, iclass 35, count 0 2006.173.07:22:03.28#ibcon#read 5, iclass 35, count 0 2006.173.07:22:03.28#ibcon#about to read 6, iclass 35, count 0 2006.173.07:22:03.28#ibcon#read 6, iclass 35, count 0 2006.173.07:22:03.28#ibcon#end of sib2, iclass 35, count 0 2006.173.07:22:03.28#ibcon#*mode == 0, iclass 35, count 0 2006.173.07:22:03.28#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.07:22:03.28#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.07:22:03.28#ibcon#*before write, iclass 35, count 0 2006.173.07:22:03.28#ibcon#enter sib2, iclass 35, count 0 2006.173.07:22:03.28#ibcon#flushed, iclass 35, count 0 2006.173.07:22:03.28#ibcon#about to write, iclass 35, count 0 2006.173.07:22:03.28#ibcon#wrote, iclass 35, count 0 2006.173.07:22:03.28#ibcon#about to read 3, iclass 35, count 0 2006.173.07:22:03.32#ibcon#read 3, iclass 35, count 0 2006.173.07:22:03.32#ibcon#about to read 4, iclass 35, count 0 2006.173.07:22:03.32#ibcon#read 4, iclass 35, count 0 2006.173.07:22:03.32#ibcon#about to read 5, iclass 35, count 0 2006.173.07:22:03.32#ibcon#read 5, iclass 35, count 0 2006.173.07:22:03.32#ibcon#about to read 6, iclass 35, count 0 2006.173.07:22:03.32#ibcon#read 6, iclass 35, count 0 2006.173.07:22:03.32#ibcon#end of sib2, iclass 35, count 0 2006.173.07:22:03.32#ibcon#*after write, iclass 35, count 0 2006.173.07:22:03.32#ibcon#*before return 0, iclass 35, count 0 2006.173.07:22:03.32#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.07:22:03.32#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.07:22:03.32#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.07:22:03.32#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.07:22:03.32$vck44/va=4,6 2006.173.07:22:03.32#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.173.07:22:03.32#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.173.07:22:03.32#ibcon#ireg 11 cls_cnt 2 2006.173.07:22:03.32#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.07:22:03.38#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.07:22:03.38#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.07:22:03.38#ibcon#enter wrdev, iclass 37, count 2 2006.173.07:22:03.38#ibcon#first serial, iclass 37, count 2 2006.173.07:22:03.38#ibcon#enter sib2, iclass 37, count 2 2006.173.07:22:03.38#ibcon#flushed, iclass 37, count 2 2006.173.07:22:03.38#ibcon#about to write, iclass 37, count 2 2006.173.07:22:03.38#ibcon#wrote, iclass 37, count 2 2006.173.07:22:03.38#ibcon#about to read 3, iclass 37, count 2 2006.173.07:22:03.40#ibcon#read 3, iclass 37, count 2 2006.173.07:22:03.40#ibcon#about to read 4, iclass 37, count 2 2006.173.07:22:03.40#ibcon#read 4, iclass 37, count 2 2006.173.07:22:03.40#ibcon#about to read 5, iclass 37, count 2 2006.173.07:22:03.40#ibcon#read 5, iclass 37, count 2 2006.173.07:22:03.40#ibcon#about to read 6, iclass 37, count 2 2006.173.07:22:03.40#ibcon#read 6, iclass 37, count 2 2006.173.07:22:03.40#ibcon#end of sib2, iclass 37, count 2 2006.173.07:22:03.40#ibcon#*mode == 0, iclass 37, count 2 2006.173.07:22:03.40#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.173.07:22:03.40#ibcon#[25=AT04-06\r\n] 2006.173.07:22:03.40#ibcon#*before write, iclass 37, count 2 2006.173.07:22:03.40#ibcon#enter sib2, iclass 37, count 2 2006.173.07:22:03.40#ibcon#flushed, iclass 37, count 2 2006.173.07:22:03.40#ibcon#about to write, iclass 37, count 2 2006.173.07:22:03.40#ibcon#wrote, iclass 37, count 2 2006.173.07:22:03.40#ibcon#about to read 3, iclass 37, count 2 2006.173.07:22:03.43#ibcon#read 3, iclass 37, count 2 2006.173.07:22:03.43#ibcon#about to read 4, iclass 37, count 2 2006.173.07:22:03.43#ibcon#read 4, iclass 37, count 2 2006.173.07:22:03.43#ibcon#about to read 5, iclass 37, count 2 2006.173.07:22:03.43#ibcon#read 5, iclass 37, count 2 2006.173.07:22:03.43#ibcon#about to read 6, iclass 37, count 2 2006.173.07:22:03.43#ibcon#read 6, iclass 37, count 2 2006.173.07:22:03.43#ibcon#end of sib2, iclass 37, count 2 2006.173.07:22:03.43#ibcon#*after write, iclass 37, count 2 2006.173.07:22:03.43#ibcon#*before return 0, iclass 37, count 2 2006.173.07:22:03.43#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.07:22:03.43#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.173.07:22:03.43#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.173.07:22:03.43#ibcon#ireg 7 cls_cnt 0 2006.173.07:22:03.43#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.07:22:03.55#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.07:22:03.55#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.07:22:03.55#ibcon#enter wrdev, iclass 37, count 0 2006.173.07:22:03.55#ibcon#first serial, iclass 37, count 0 2006.173.07:22:03.55#ibcon#enter sib2, iclass 37, count 0 2006.173.07:22:03.55#ibcon#flushed, iclass 37, count 0 2006.173.07:22:03.55#ibcon#about to write, iclass 37, count 0 2006.173.07:22:03.55#ibcon#wrote, iclass 37, count 0 2006.173.07:22:03.55#ibcon#about to read 3, iclass 37, count 0 2006.173.07:22:03.57#ibcon#read 3, iclass 37, count 0 2006.173.07:22:03.57#ibcon#about to read 4, iclass 37, count 0 2006.173.07:22:03.57#ibcon#read 4, iclass 37, count 0 2006.173.07:22:03.57#ibcon#about to read 5, iclass 37, count 0 2006.173.07:22:03.57#ibcon#read 5, iclass 37, count 0 2006.173.07:22:03.57#ibcon#about to read 6, iclass 37, count 0 2006.173.07:22:03.57#ibcon#read 6, iclass 37, count 0 2006.173.07:22:03.57#ibcon#end of sib2, iclass 37, count 0 2006.173.07:22:03.57#ibcon#*mode == 0, iclass 37, count 0 2006.173.07:22:03.57#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.07:22:03.57#ibcon#[25=USB\r\n] 2006.173.07:22:03.57#ibcon#*before write, iclass 37, count 0 2006.173.07:22:03.57#ibcon#enter sib2, iclass 37, count 0 2006.173.07:22:03.57#ibcon#flushed, iclass 37, count 0 2006.173.07:22:03.57#ibcon#about to write, iclass 37, count 0 2006.173.07:22:03.57#ibcon#wrote, iclass 37, count 0 2006.173.07:22:03.57#ibcon#about to read 3, iclass 37, count 0 2006.173.07:22:03.60#ibcon#read 3, iclass 37, count 0 2006.173.07:22:03.60#ibcon#about to read 4, iclass 37, count 0 2006.173.07:22:03.60#ibcon#read 4, iclass 37, count 0 2006.173.07:22:03.60#ibcon#about to read 5, iclass 37, count 0 2006.173.07:22:03.60#ibcon#read 5, iclass 37, count 0 2006.173.07:22:03.60#ibcon#about to read 6, iclass 37, count 0 2006.173.07:22:03.60#ibcon#read 6, iclass 37, count 0 2006.173.07:22:03.60#ibcon#end of sib2, iclass 37, count 0 2006.173.07:22:03.60#ibcon#*after write, iclass 37, count 0 2006.173.07:22:03.60#ibcon#*before return 0, iclass 37, count 0 2006.173.07:22:03.60#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.07:22:03.60#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.173.07:22:03.60#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.07:22:03.60#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.07:22:03.60$vck44/valo=5,734.99 2006.173.07:22:03.60#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.07:22:03.60#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.07:22:03.60#ibcon#ireg 17 cls_cnt 0 2006.173.07:22:03.60#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.07:22:03.60#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.07:22:03.60#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.07:22:03.60#ibcon#enter wrdev, iclass 39, count 0 2006.173.07:22:03.60#ibcon#first serial, iclass 39, count 0 2006.173.07:22:03.60#ibcon#enter sib2, iclass 39, count 0 2006.173.07:22:03.60#ibcon#flushed, iclass 39, count 0 2006.173.07:22:03.60#ibcon#about to write, iclass 39, count 0 2006.173.07:22:03.60#ibcon#wrote, iclass 39, count 0 2006.173.07:22:03.60#ibcon#about to read 3, iclass 39, count 0 2006.173.07:22:03.62#ibcon#read 3, iclass 39, count 0 2006.173.07:22:03.62#ibcon#about to read 4, iclass 39, count 0 2006.173.07:22:03.62#ibcon#read 4, iclass 39, count 0 2006.173.07:22:03.62#ibcon#about to read 5, iclass 39, count 0 2006.173.07:22:03.62#ibcon#read 5, iclass 39, count 0 2006.173.07:22:03.62#ibcon#about to read 6, iclass 39, count 0 2006.173.07:22:03.62#ibcon#read 6, iclass 39, count 0 2006.173.07:22:03.62#ibcon#end of sib2, iclass 39, count 0 2006.173.07:22:03.62#ibcon#*mode == 0, iclass 39, count 0 2006.173.07:22:03.62#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.07:22:03.62#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.07:22:03.62#ibcon#*before write, iclass 39, count 0 2006.173.07:22:03.62#ibcon#enter sib2, iclass 39, count 0 2006.173.07:22:03.62#ibcon#flushed, iclass 39, count 0 2006.173.07:22:03.62#ibcon#about to write, iclass 39, count 0 2006.173.07:22:03.62#ibcon#wrote, iclass 39, count 0 2006.173.07:22:03.62#ibcon#about to read 3, iclass 39, count 0 2006.173.07:22:03.66#ibcon#read 3, iclass 39, count 0 2006.173.07:22:03.66#ibcon#about to read 4, iclass 39, count 0 2006.173.07:22:03.66#ibcon#read 4, iclass 39, count 0 2006.173.07:22:03.66#ibcon#about to read 5, iclass 39, count 0 2006.173.07:22:03.66#ibcon#read 5, iclass 39, count 0 2006.173.07:22:03.66#ibcon#about to read 6, iclass 39, count 0 2006.173.07:22:03.66#ibcon#read 6, iclass 39, count 0 2006.173.07:22:03.66#ibcon#end of sib2, iclass 39, count 0 2006.173.07:22:03.66#ibcon#*after write, iclass 39, count 0 2006.173.07:22:03.66#ibcon#*before return 0, iclass 39, count 0 2006.173.07:22:03.66#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.07:22:03.66#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.07:22:03.66#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.07:22:03.66#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.07:22:03.66$vck44/va=5,4 2006.173.07:22:03.66#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.07:22:03.66#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.07:22:03.66#ibcon#ireg 11 cls_cnt 2 2006.173.07:22:03.66#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.07:22:03.72#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.07:22:03.72#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.07:22:03.72#ibcon#enter wrdev, iclass 3, count 2 2006.173.07:22:03.72#ibcon#first serial, iclass 3, count 2 2006.173.07:22:03.72#ibcon#enter sib2, iclass 3, count 2 2006.173.07:22:03.72#ibcon#flushed, iclass 3, count 2 2006.173.07:22:03.72#ibcon#about to write, iclass 3, count 2 2006.173.07:22:03.72#ibcon#wrote, iclass 3, count 2 2006.173.07:22:03.72#ibcon#about to read 3, iclass 3, count 2 2006.173.07:22:03.74#ibcon#read 3, iclass 3, count 2 2006.173.07:22:03.74#ibcon#about to read 4, iclass 3, count 2 2006.173.07:22:03.74#ibcon#read 4, iclass 3, count 2 2006.173.07:22:03.74#ibcon#about to read 5, iclass 3, count 2 2006.173.07:22:03.74#ibcon#read 5, iclass 3, count 2 2006.173.07:22:03.74#ibcon#about to read 6, iclass 3, count 2 2006.173.07:22:03.74#ibcon#read 6, iclass 3, count 2 2006.173.07:22:03.74#ibcon#end of sib2, iclass 3, count 2 2006.173.07:22:03.74#ibcon#*mode == 0, iclass 3, count 2 2006.173.07:22:03.74#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.07:22:03.74#ibcon#[25=AT05-04\r\n] 2006.173.07:22:03.74#ibcon#*before write, iclass 3, count 2 2006.173.07:22:03.74#ibcon#enter sib2, iclass 3, count 2 2006.173.07:22:03.74#ibcon#flushed, iclass 3, count 2 2006.173.07:22:03.74#ibcon#about to write, iclass 3, count 2 2006.173.07:22:03.74#ibcon#wrote, iclass 3, count 2 2006.173.07:22:03.74#ibcon#about to read 3, iclass 3, count 2 2006.173.07:22:03.77#ibcon#read 3, iclass 3, count 2 2006.173.07:22:03.77#ibcon#about to read 4, iclass 3, count 2 2006.173.07:22:03.77#ibcon#read 4, iclass 3, count 2 2006.173.07:22:03.77#ibcon#about to read 5, iclass 3, count 2 2006.173.07:22:03.77#ibcon#read 5, iclass 3, count 2 2006.173.07:22:03.77#ibcon#about to read 6, iclass 3, count 2 2006.173.07:22:03.77#ibcon#read 6, iclass 3, count 2 2006.173.07:22:03.77#ibcon#end of sib2, iclass 3, count 2 2006.173.07:22:03.77#ibcon#*after write, iclass 3, count 2 2006.173.07:22:03.77#ibcon#*before return 0, iclass 3, count 2 2006.173.07:22:03.77#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.07:22:03.77#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.07:22:03.77#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.07:22:03.77#ibcon#ireg 7 cls_cnt 0 2006.173.07:22:03.77#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.07:22:03.89#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.07:22:03.89#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.07:22:03.89#ibcon#enter wrdev, iclass 3, count 0 2006.173.07:22:03.89#ibcon#first serial, iclass 3, count 0 2006.173.07:22:03.89#ibcon#enter sib2, iclass 3, count 0 2006.173.07:22:03.89#ibcon#flushed, iclass 3, count 0 2006.173.07:22:03.89#ibcon#about to write, iclass 3, count 0 2006.173.07:22:03.89#ibcon#wrote, iclass 3, count 0 2006.173.07:22:03.89#ibcon#about to read 3, iclass 3, count 0 2006.173.07:22:03.91#ibcon#read 3, iclass 3, count 0 2006.173.07:22:03.91#ibcon#about to read 4, iclass 3, count 0 2006.173.07:22:03.91#ibcon#read 4, iclass 3, count 0 2006.173.07:22:03.91#ibcon#about to read 5, iclass 3, count 0 2006.173.07:22:03.91#ibcon#read 5, iclass 3, count 0 2006.173.07:22:03.91#ibcon#about to read 6, iclass 3, count 0 2006.173.07:22:03.91#ibcon#read 6, iclass 3, count 0 2006.173.07:22:03.91#ibcon#end of sib2, iclass 3, count 0 2006.173.07:22:03.91#ibcon#*mode == 0, iclass 3, count 0 2006.173.07:22:03.91#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.07:22:03.91#ibcon#[25=USB\r\n] 2006.173.07:22:03.91#ibcon#*before write, iclass 3, count 0 2006.173.07:22:03.91#ibcon#enter sib2, iclass 3, count 0 2006.173.07:22:03.91#ibcon#flushed, iclass 3, count 0 2006.173.07:22:03.91#ibcon#about to write, iclass 3, count 0 2006.173.07:22:03.91#ibcon#wrote, iclass 3, count 0 2006.173.07:22:03.91#ibcon#about to read 3, iclass 3, count 0 2006.173.07:22:03.94#ibcon#read 3, iclass 3, count 0 2006.173.07:22:03.94#ibcon#about to read 4, iclass 3, count 0 2006.173.07:22:03.94#ibcon#read 4, iclass 3, count 0 2006.173.07:22:03.94#ibcon#about to read 5, iclass 3, count 0 2006.173.07:22:03.94#ibcon#read 5, iclass 3, count 0 2006.173.07:22:03.94#ibcon#about to read 6, iclass 3, count 0 2006.173.07:22:03.94#ibcon#read 6, iclass 3, count 0 2006.173.07:22:03.94#ibcon#end of sib2, iclass 3, count 0 2006.173.07:22:03.94#ibcon#*after write, iclass 3, count 0 2006.173.07:22:03.94#ibcon#*before return 0, iclass 3, count 0 2006.173.07:22:03.94#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.07:22:03.94#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.07:22:03.94#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.07:22:03.94#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.07:22:03.94$vck44/valo=6,814.99 2006.173.07:22:03.94#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.07:22:03.94#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.07:22:03.94#ibcon#ireg 17 cls_cnt 0 2006.173.07:22:03.94#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.07:22:03.94#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.07:22:03.94#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.07:22:03.94#ibcon#enter wrdev, iclass 5, count 0 2006.173.07:22:03.94#ibcon#first serial, iclass 5, count 0 2006.173.07:22:03.94#ibcon#enter sib2, iclass 5, count 0 2006.173.07:22:03.94#ibcon#flushed, iclass 5, count 0 2006.173.07:22:03.94#ibcon#about to write, iclass 5, count 0 2006.173.07:22:03.94#ibcon#wrote, iclass 5, count 0 2006.173.07:22:03.94#ibcon#about to read 3, iclass 5, count 0 2006.173.07:22:03.96#ibcon#read 3, iclass 5, count 0 2006.173.07:22:03.96#ibcon#about to read 4, iclass 5, count 0 2006.173.07:22:03.96#ibcon#read 4, iclass 5, count 0 2006.173.07:22:03.96#ibcon#about to read 5, iclass 5, count 0 2006.173.07:22:03.96#ibcon#read 5, iclass 5, count 0 2006.173.07:22:03.96#ibcon#about to read 6, iclass 5, count 0 2006.173.07:22:03.96#ibcon#read 6, iclass 5, count 0 2006.173.07:22:03.96#ibcon#end of sib2, iclass 5, count 0 2006.173.07:22:03.96#ibcon#*mode == 0, iclass 5, count 0 2006.173.07:22:03.96#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.07:22:03.96#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.07:22:03.96#ibcon#*before write, iclass 5, count 0 2006.173.07:22:03.96#ibcon#enter sib2, iclass 5, count 0 2006.173.07:22:03.96#ibcon#flushed, iclass 5, count 0 2006.173.07:22:03.96#ibcon#about to write, iclass 5, count 0 2006.173.07:22:03.96#ibcon#wrote, iclass 5, count 0 2006.173.07:22:03.96#ibcon#about to read 3, iclass 5, count 0 2006.173.07:22:04.00#ibcon#read 3, iclass 5, count 0 2006.173.07:22:04.00#ibcon#about to read 4, iclass 5, count 0 2006.173.07:22:04.00#ibcon#read 4, iclass 5, count 0 2006.173.07:22:04.00#ibcon#about to read 5, iclass 5, count 0 2006.173.07:22:04.00#ibcon#read 5, iclass 5, count 0 2006.173.07:22:04.00#ibcon#about to read 6, iclass 5, count 0 2006.173.07:22:04.00#ibcon#read 6, iclass 5, count 0 2006.173.07:22:04.00#ibcon#end of sib2, iclass 5, count 0 2006.173.07:22:04.00#ibcon#*after write, iclass 5, count 0 2006.173.07:22:04.00#ibcon#*before return 0, iclass 5, count 0 2006.173.07:22:04.00#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.07:22:04.00#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.07:22:04.00#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.07:22:04.00#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.07:22:04.00$vck44/va=6,3 2006.173.07:22:04.00#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.173.07:22:04.00#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.173.07:22:04.00#ibcon#ireg 11 cls_cnt 2 2006.173.07:22:04.00#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.07:22:04.06#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.07:22:04.06#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.07:22:04.06#ibcon#enter wrdev, iclass 7, count 2 2006.173.07:22:04.06#ibcon#first serial, iclass 7, count 2 2006.173.07:22:04.06#ibcon#enter sib2, iclass 7, count 2 2006.173.07:22:04.06#ibcon#flushed, iclass 7, count 2 2006.173.07:22:04.06#ibcon#about to write, iclass 7, count 2 2006.173.07:22:04.06#ibcon#wrote, iclass 7, count 2 2006.173.07:22:04.06#ibcon#about to read 3, iclass 7, count 2 2006.173.07:22:04.08#ibcon#read 3, iclass 7, count 2 2006.173.07:22:04.08#ibcon#about to read 4, iclass 7, count 2 2006.173.07:22:04.08#ibcon#read 4, iclass 7, count 2 2006.173.07:22:04.08#ibcon#about to read 5, iclass 7, count 2 2006.173.07:22:04.08#ibcon#read 5, iclass 7, count 2 2006.173.07:22:04.08#ibcon#about to read 6, iclass 7, count 2 2006.173.07:22:04.08#ibcon#read 6, iclass 7, count 2 2006.173.07:22:04.08#ibcon#end of sib2, iclass 7, count 2 2006.173.07:22:04.08#ibcon#*mode == 0, iclass 7, count 2 2006.173.07:22:04.08#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.173.07:22:04.08#ibcon#[25=AT06-03\r\n] 2006.173.07:22:04.08#ibcon#*before write, iclass 7, count 2 2006.173.07:22:04.08#ibcon#enter sib2, iclass 7, count 2 2006.173.07:22:04.08#ibcon#flushed, iclass 7, count 2 2006.173.07:22:04.08#ibcon#about to write, iclass 7, count 2 2006.173.07:22:04.08#ibcon#wrote, iclass 7, count 2 2006.173.07:22:04.08#ibcon#about to read 3, iclass 7, count 2 2006.173.07:22:04.11#ibcon#read 3, iclass 7, count 2 2006.173.07:22:04.11#ibcon#about to read 4, iclass 7, count 2 2006.173.07:22:04.11#ibcon#read 4, iclass 7, count 2 2006.173.07:22:04.11#ibcon#about to read 5, iclass 7, count 2 2006.173.07:22:04.11#ibcon#read 5, iclass 7, count 2 2006.173.07:22:04.11#ibcon#about to read 6, iclass 7, count 2 2006.173.07:22:04.11#ibcon#read 6, iclass 7, count 2 2006.173.07:22:04.11#ibcon#end of sib2, iclass 7, count 2 2006.173.07:22:04.11#ibcon#*after write, iclass 7, count 2 2006.173.07:22:04.11#ibcon#*before return 0, iclass 7, count 2 2006.173.07:22:04.11#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.07:22:04.11#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.173.07:22:04.11#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.173.07:22:04.11#ibcon#ireg 7 cls_cnt 0 2006.173.07:22:04.11#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.07:22:04.23#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.07:22:04.23#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.07:22:04.23#ibcon#enter wrdev, iclass 7, count 0 2006.173.07:22:04.23#ibcon#first serial, iclass 7, count 0 2006.173.07:22:04.23#ibcon#enter sib2, iclass 7, count 0 2006.173.07:22:04.23#ibcon#flushed, iclass 7, count 0 2006.173.07:22:04.23#ibcon#about to write, iclass 7, count 0 2006.173.07:22:04.23#ibcon#wrote, iclass 7, count 0 2006.173.07:22:04.23#ibcon#about to read 3, iclass 7, count 0 2006.173.07:22:04.25#ibcon#read 3, iclass 7, count 0 2006.173.07:22:04.25#ibcon#about to read 4, iclass 7, count 0 2006.173.07:22:04.25#ibcon#read 4, iclass 7, count 0 2006.173.07:22:04.25#ibcon#about to read 5, iclass 7, count 0 2006.173.07:22:04.25#ibcon#read 5, iclass 7, count 0 2006.173.07:22:04.25#ibcon#about to read 6, iclass 7, count 0 2006.173.07:22:04.25#ibcon#read 6, iclass 7, count 0 2006.173.07:22:04.25#ibcon#end of sib2, iclass 7, count 0 2006.173.07:22:04.25#ibcon#*mode == 0, iclass 7, count 0 2006.173.07:22:04.25#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.07:22:04.25#ibcon#[25=USB\r\n] 2006.173.07:22:04.25#ibcon#*before write, iclass 7, count 0 2006.173.07:22:04.25#ibcon#enter sib2, iclass 7, count 0 2006.173.07:22:04.25#ibcon#flushed, iclass 7, count 0 2006.173.07:22:04.25#ibcon#about to write, iclass 7, count 0 2006.173.07:22:04.25#ibcon#wrote, iclass 7, count 0 2006.173.07:22:04.25#ibcon#about to read 3, iclass 7, count 0 2006.173.07:22:04.28#ibcon#read 3, iclass 7, count 0 2006.173.07:22:04.28#ibcon#about to read 4, iclass 7, count 0 2006.173.07:22:04.28#ibcon#read 4, iclass 7, count 0 2006.173.07:22:04.28#ibcon#about to read 5, iclass 7, count 0 2006.173.07:22:04.28#ibcon#read 5, iclass 7, count 0 2006.173.07:22:04.28#ibcon#about to read 6, iclass 7, count 0 2006.173.07:22:04.28#ibcon#read 6, iclass 7, count 0 2006.173.07:22:04.28#ibcon#end of sib2, iclass 7, count 0 2006.173.07:22:04.28#ibcon#*after write, iclass 7, count 0 2006.173.07:22:04.28#ibcon#*before return 0, iclass 7, count 0 2006.173.07:22:04.28#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.07:22:04.28#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.173.07:22:04.28#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.07:22:04.28#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.07:22:04.28$vck44/valo=7,864.99 2006.173.07:22:04.28#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.07:22:04.28#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.07:22:04.28#ibcon#ireg 17 cls_cnt 0 2006.173.07:22:04.28#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.07:22:04.28#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.07:22:04.28#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.07:22:04.28#ibcon#enter wrdev, iclass 11, count 0 2006.173.07:22:04.28#ibcon#first serial, iclass 11, count 0 2006.173.07:22:04.28#ibcon#enter sib2, iclass 11, count 0 2006.173.07:22:04.28#ibcon#flushed, iclass 11, count 0 2006.173.07:22:04.28#ibcon#about to write, iclass 11, count 0 2006.173.07:22:04.28#ibcon#wrote, iclass 11, count 0 2006.173.07:22:04.28#ibcon#about to read 3, iclass 11, count 0 2006.173.07:22:04.30#ibcon#read 3, iclass 11, count 0 2006.173.07:22:04.30#ibcon#about to read 4, iclass 11, count 0 2006.173.07:22:04.30#ibcon#read 4, iclass 11, count 0 2006.173.07:22:04.30#ibcon#about to read 5, iclass 11, count 0 2006.173.07:22:04.30#ibcon#read 5, iclass 11, count 0 2006.173.07:22:04.30#ibcon#about to read 6, iclass 11, count 0 2006.173.07:22:04.30#ibcon#read 6, iclass 11, count 0 2006.173.07:22:04.30#ibcon#end of sib2, iclass 11, count 0 2006.173.07:22:04.30#ibcon#*mode == 0, iclass 11, count 0 2006.173.07:22:04.30#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.07:22:04.30#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.07:22:04.30#ibcon#*before write, iclass 11, count 0 2006.173.07:22:04.30#ibcon#enter sib2, iclass 11, count 0 2006.173.07:22:04.30#ibcon#flushed, iclass 11, count 0 2006.173.07:22:04.30#ibcon#about to write, iclass 11, count 0 2006.173.07:22:04.30#ibcon#wrote, iclass 11, count 0 2006.173.07:22:04.30#ibcon#about to read 3, iclass 11, count 0 2006.173.07:22:04.34#ibcon#read 3, iclass 11, count 0 2006.173.07:22:04.34#ibcon#about to read 4, iclass 11, count 0 2006.173.07:22:04.34#ibcon#read 4, iclass 11, count 0 2006.173.07:22:04.34#ibcon#about to read 5, iclass 11, count 0 2006.173.07:22:04.34#ibcon#read 5, iclass 11, count 0 2006.173.07:22:04.34#ibcon#about to read 6, iclass 11, count 0 2006.173.07:22:04.34#ibcon#read 6, iclass 11, count 0 2006.173.07:22:04.34#ibcon#end of sib2, iclass 11, count 0 2006.173.07:22:04.34#ibcon#*after write, iclass 11, count 0 2006.173.07:22:04.34#ibcon#*before return 0, iclass 11, count 0 2006.173.07:22:04.34#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.07:22:04.34#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.07:22:04.34#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.07:22:04.34#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.07:22:04.34$vck44/va=7,4 2006.173.07:22:04.34#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.173.07:22:04.34#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.173.07:22:04.34#ibcon#ireg 11 cls_cnt 2 2006.173.07:22:04.34#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.07:22:04.40#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.07:22:04.40#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.07:22:04.40#ibcon#enter wrdev, iclass 13, count 2 2006.173.07:22:04.40#ibcon#first serial, iclass 13, count 2 2006.173.07:22:04.40#ibcon#enter sib2, iclass 13, count 2 2006.173.07:22:04.40#ibcon#flushed, iclass 13, count 2 2006.173.07:22:04.40#ibcon#about to write, iclass 13, count 2 2006.173.07:22:04.40#ibcon#wrote, iclass 13, count 2 2006.173.07:22:04.40#ibcon#about to read 3, iclass 13, count 2 2006.173.07:22:04.42#ibcon#read 3, iclass 13, count 2 2006.173.07:22:04.42#ibcon#about to read 4, iclass 13, count 2 2006.173.07:22:04.42#ibcon#read 4, iclass 13, count 2 2006.173.07:22:04.42#ibcon#about to read 5, iclass 13, count 2 2006.173.07:22:04.42#ibcon#read 5, iclass 13, count 2 2006.173.07:22:04.42#ibcon#about to read 6, iclass 13, count 2 2006.173.07:22:04.42#ibcon#read 6, iclass 13, count 2 2006.173.07:22:04.42#ibcon#end of sib2, iclass 13, count 2 2006.173.07:22:04.42#ibcon#*mode == 0, iclass 13, count 2 2006.173.07:22:04.42#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.173.07:22:04.42#ibcon#[25=AT07-04\r\n] 2006.173.07:22:04.42#ibcon#*before write, iclass 13, count 2 2006.173.07:22:04.42#ibcon#enter sib2, iclass 13, count 2 2006.173.07:22:04.42#ibcon#flushed, iclass 13, count 2 2006.173.07:22:04.42#ibcon#about to write, iclass 13, count 2 2006.173.07:22:04.42#ibcon#wrote, iclass 13, count 2 2006.173.07:22:04.42#ibcon#about to read 3, iclass 13, count 2 2006.173.07:22:04.45#ibcon#read 3, iclass 13, count 2 2006.173.07:22:04.45#ibcon#about to read 4, iclass 13, count 2 2006.173.07:22:04.45#ibcon#read 4, iclass 13, count 2 2006.173.07:22:04.45#ibcon#about to read 5, iclass 13, count 2 2006.173.07:22:04.45#ibcon#read 5, iclass 13, count 2 2006.173.07:22:04.45#ibcon#about to read 6, iclass 13, count 2 2006.173.07:22:04.45#ibcon#read 6, iclass 13, count 2 2006.173.07:22:04.45#ibcon#end of sib2, iclass 13, count 2 2006.173.07:22:04.45#ibcon#*after write, iclass 13, count 2 2006.173.07:22:04.45#ibcon#*before return 0, iclass 13, count 2 2006.173.07:22:04.45#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.07:22:04.45#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.173.07:22:04.45#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.173.07:22:04.45#ibcon#ireg 7 cls_cnt 0 2006.173.07:22:04.45#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.07:22:04.57#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.07:22:04.57#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.07:22:04.57#ibcon#enter wrdev, iclass 13, count 0 2006.173.07:22:04.57#ibcon#first serial, iclass 13, count 0 2006.173.07:22:04.57#ibcon#enter sib2, iclass 13, count 0 2006.173.07:22:04.57#ibcon#flushed, iclass 13, count 0 2006.173.07:22:04.57#ibcon#about to write, iclass 13, count 0 2006.173.07:22:04.57#ibcon#wrote, iclass 13, count 0 2006.173.07:22:04.57#ibcon#about to read 3, iclass 13, count 0 2006.173.07:22:04.59#ibcon#read 3, iclass 13, count 0 2006.173.07:22:04.59#ibcon#about to read 4, iclass 13, count 0 2006.173.07:22:04.59#ibcon#read 4, iclass 13, count 0 2006.173.07:22:04.59#ibcon#about to read 5, iclass 13, count 0 2006.173.07:22:04.59#ibcon#read 5, iclass 13, count 0 2006.173.07:22:04.59#ibcon#about to read 6, iclass 13, count 0 2006.173.07:22:04.59#ibcon#read 6, iclass 13, count 0 2006.173.07:22:04.59#ibcon#end of sib2, iclass 13, count 0 2006.173.07:22:04.59#ibcon#*mode == 0, iclass 13, count 0 2006.173.07:22:04.59#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.07:22:04.59#ibcon#[25=USB\r\n] 2006.173.07:22:04.59#ibcon#*before write, iclass 13, count 0 2006.173.07:22:04.59#ibcon#enter sib2, iclass 13, count 0 2006.173.07:22:04.59#ibcon#flushed, iclass 13, count 0 2006.173.07:22:04.59#ibcon#about to write, iclass 13, count 0 2006.173.07:22:04.59#ibcon#wrote, iclass 13, count 0 2006.173.07:22:04.59#ibcon#about to read 3, iclass 13, count 0 2006.173.07:22:04.62#ibcon#read 3, iclass 13, count 0 2006.173.07:22:04.62#ibcon#about to read 4, iclass 13, count 0 2006.173.07:22:04.62#ibcon#read 4, iclass 13, count 0 2006.173.07:22:04.62#ibcon#about to read 5, iclass 13, count 0 2006.173.07:22:04.62#ibcon#read 5, iclass 13, count 0 2006.173.07:22:04.62#ibcon#about to read 6, iclass 13, count 0 2006.173.07:22:04.62#ibcon#read 6, iclass 13, count 0 2006.173.07:22:04.62#ibcon#end of sib2, iclass 13, count 0 2006.173.07:22:04.62#ibcon#*after write, iclass 13, count 0 2006.173.07:22:04.62#ibcon#*before return 0, iclass 13, count 0 2006.173.07:22:04.62#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.07:22:04.62#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.173.07:22:04.62#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.07:22:04.62#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.07:22:04.62$vck44/valo=8,884.99 2006.173.07:22:04.62#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.07:22:04.62#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.07:22:04.62#ibcon#ireg 17 cls_cnt 0 2006.173.07:22:04.62#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.07:22:04.62#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.07:22:04.62#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.07:22:04.62#ibcon#enter wrdev, iclass 15, count 0 2006.173.07:22:04.62#ibcon#first serial, iclass 15, count 0 2006.173.07:22:04.62#ibcon#enter sib2, iclass 15, count 0 2006.173.07:22:04.62#ibcon#flushed, iclass 15, count 0 2006.173.07:22:04.62#ibcon#about to write, iclass 15, count 0 2006.173.07:22:04.62#ibcon#wrote, iclass 15, count 0 2006.173.07:22:04.62#ibcon#about to read 3, iclass 15, count 0 2006.173.07:22:04.64#ibcon#read 3, iclass 15, count 0 2006.173.07:22:04.64#ibcon#about to read 4, iclass 15, count 0 2006.173.07:22:04.64#ibcon#read 4, iclass 15, count 0 2006.173.07:22:04.64#ibcon#about to read 5, iclass 15, count 0 2006.173.07:22:04.64#ibcon#read 5, iclass 15, count 0 2006.173.07:22:04.64#ibcon#about to read 6, iclass 15, count 0 2006.173.07:22:04.64#ibcon#read 6, iclass 15, count 0 2006.173.07:22:04.64#ibcon#end of sib2, iclass 15, count 0 2006.173.07:22:04.64#ibcon#*mode == 0, iclass 15, count 0 2006.173.07:22:04.64#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.07:22:04.64#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.07:22:04.64#ibcon#*before write, iclass 15, count 0 2006.173.07:22:04.64#ibcon#enter sib2, iclass 15, count 0 2006.173.07:22:04.64#ibcon#flushed, iclass 15, count 0 2006.173.07:22:04.64#ibcon#about to write, iclass 15, count 0 2006.173.07:22:04.64#ibcon#wrote, iclass 15, count 0 2006.173.07:22:04.64#ibcon#about to read 3, iclass 15, count 0 2006.173.07:22:04.68#ibcon#read 3, iclass 15, count 0 2006.173.07:22:04.68#ibcon#about to read 4, iclass 15, count 0 2006.173.07:22:04.68#ibcon#read 4, iclass 15, count 0 2006.173.07:22:04.68#ibcon#about to read 5, iclass 15, count 0 2006.173.07:22:04.68#ibcon#read 5, iclass 15, count 0 2006.173.07:22:04.68#ibcon#about to read 6, iclass 15, count 0 2006.173.07:22:04.68#ibcon#read 6, iclass 15, count 0 2006.173.07:22:04.68#ibcon#end of sib2, iclass 15, count 0 2006.173.07:22:04.68#ibcon#*after write, iclass 15, count 0 2006.173.07:22:04.68#ibcon#*before return 0, iclass 15, count 0 2006.173.07:22:04.68#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.07:22:04.68#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.07:22:04.68#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.07:22:04.68#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.07:22:04.68$vck44/va=8,4 2006.173.07:22:04.68#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.07:22:04.68#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.07:22:04.68#ibcon#ireg 11 cls_cnt 2 2006.173.07:22:04.68#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.07:22:04.74#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.07:22:04.74#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.07:22:04.74#ibcon#enter wrdev, iclass 17, count 2 2006.173.07:22:04.74#ibcon#first serial, iclass 17, count 2 2006.173.07:22:04.74#ibcon#enter sib2, iclass 17, count 2 2006.173.07:22:04.74#ibcon#flushed, iclass 17, count 2 2006.173.07:22:04.74#ibcon#about to write, iclass 17, count 2 2006.173.07:22:04.74#ibcon#wrote, iclass 17, count 2 2006.173.07:22:04.74#ibcon#about to read 3, iclass 17, count 2 2006.173.07:22:04.76#ibcon#read 3, iclass 17, count 2 2006.173.07:22:04.76#ibcon#about to read 4, iclass 17, count 2 2006.173.07:22:04.76#ibcon#read 4, iclass 17, count 2 2006.173.07:22:04.76#ibcon#about to read 5, iclass 17, count 2 2006.173.07:22:04.76#ibcon#read 5, iclass 17, count 2 2006.173.07:22:04.76#ibcon#about to read 6, iclass 17, count 2 2006.173.07:22:04.76#ibcon#read 6, iclass 17, count 2 2006.173.07:22:04.76#ibcon#end of sib2, iclass 17, count 2 2006.173.07:22:04.76#ibcon#*mode == 0, iclass 17, count 2 2006.173.07:22:04.76#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.07:22:04.76#ibcon#[25=AT08-04\r\n] 2006.173.07:22:04.76#ibcon#*before write, iclass 17, count 2 2006.173.07:22:04.76#ibcon#enter sib2, iclass 17, count 2 2006.173.07:22:04.76#ibcon#flushed, iclass 17, count 2 2006.173.07:22:04.76#ibcon#about to write, iclass 17, count 2 2006.173.07:22:04.76#ibcon#wrote, iclass 17, count 2 2006.173.07:22:04.76#ibcon#about to read 3, iclass 17, count 2 2006.173.07:22:04.79#ibcon#read 3, iclass 17, count 2 2006.173.07:22:04.79#ibcon#about to read 4, iclass 17, count 2 2006.173.07:22:04.79#ibcon#read 4, iclass 17, count 2 2006.173.07:22:04.79#ibcon#about to read 5, iclass 17, count 2 2006.173.07:22:04.79#ibcon#read 5, iclass 17, count 2 2006.173.07:22:04.79#ibcon#about to read 6, iclass 17, count 2 2006.173.07:22:04.79#ibcon#read 6, iclass 17, count 2 2006.173.07:22:04.79#ibcon#end of sib2, iclass 17, count 2 2006.173.07:22:04.79#ibcon#*after write, iclass 17, count 2 2006.173.07:22:04.79#ibcon#*before return 0, iclass 17, count 2 2006.173.07:22:04.79#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.07:22:04.79#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.07:22:04.79#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.07:22:04.79#ibcon#ireg 7 cls_cnt 0 2006.173.07:22:04.79#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.07:22:04.91#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.07:22:04.91#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.07:22:04.91#ibcon#enter wrdev, iclass 17, count 0 2006.173.07:22:04.91#ibcon#first serial, iclass 17, count 0 2006.173.07:22:04.91#ibcon#enter sib2, iclass 17, count 0 2006.173.07:22:04.91#ibcon#flushed, iclass 17, count 0 2006.173.07:22:04.91#ibcon#about to write, iclass 17, count 0 2006.173.07:22:04.91#ibcon#wrote, iclass 17, count 0 2006.173.07:22:04.91#ibcon#about to read 3, iclass 17, count 0 2006.173.07:22:04.93#ibcon#read 3, iclass 17, count 0 2006.173.07:22:04.93#ibcon#about to read 4, iclass 17, count 0 2006.173.07:22:04.93#ibcon#read 4, iclass 17, count 0 2006.173.07:22:04.93#ibcon#about to read 5, iclass 17, count 0 2006.173.07:22:04.93#ibcon#read 5, iclass 17, count 0 2006.173.07:22:04.93#ibcon#about to read 6, iclass 17, count 0 2006.173.07:22:04.93#ibcon#read 6, iclass 17, count 0 2006.173.07:22:04.93#ibcon#end of sib2, iclass 17, count 0 2006.173.07:22:04.93#ibcon#*mode == 0, iclass 17, count 0 2006.173.07:22:04.93#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.07:22:04.93#ibcon#[25=USB\r\n] 2006.173.07:22:04.93#ibcon#*before write, iclass 17, count 0 2006.173.07:22:04.93#ibcon#enter sib2, iclass 17, count 0 2006.173.07:22:04.93#ibcon#flushed, iclass 17, count 0 2006.173.07:22:04.93#ibcon#about to write, iclass 17, count 0 2006.173.07:22:04.93#ibcon#wrote, iclass 17, count 0 2006.173.07:22:04.93#ibcon#about to read 3, iclass 17, count 0 2006.173.07:22:04.96#ibcon#read 3, iclass 17, count 0 2006.173.07:22:04.96#ibcon#about to read 4, iclass 17, count 0 2006.173.07:22:04.96#ibcon#read 4, iclass 17, count 0 2006.173.07:22:04.96#ibcon#about to read 5, iclass 17, count 0 2006.173.07:22:04.96#ibcon#read 5, iclass 17, count 0 2006.173.07:22:04.96#ibcon#about to read 6, iclass 17, count 0 2006.173.07:22:04.96#ibcon#read 6, iclass 17, count 0 2006.173.07:22:04.96#ibcon#end of sib2, iclass 17, count 0 2006.173.07:22:04.96#ibcon#*after write, iclass 17, count 0 2006.173.07:22:04.96#ibcon#*before return 0, iclass 17, count 0 2006.173.07:22:04.96#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.07:22:04.96#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.07:22:04.96#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.07:22:04.96#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.07:22:04.96$vck44/vblo=1,629.99 2006.173.07:22:04.96#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.07:22:04.96#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.07:22:04.96#ibcon#ireg 17 cls_cnt 0 2006.173.07:22:04.96#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.07:22:04.96#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.07:22:04.96#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.07:22:04.96#ibcon#enter wrdev, iclass 19, count 0 2006.173.07:22:04.96#ibcon#first serial, iclass 19, count 0 2006.173.07:22:04.96#ibcon#enter sib2, iclass 19, count 0 2006.173.07:22:04.96#ibcon#flushed, iclass 19, count 0 2006.173.07:22:04.96#ibcon#about to write, iclass 19, count 0 2006.173.07:22:04.96#ibcon#wrote, iclass 19, count 0 2006.173.07:22:04.96#ibcon#about to read 3, iclass 19, count 0 2006.173.07:22:04.98#ibcon#read 3, iclass 19, count 0 2006.173.07:22:04.98#ibcon#about to read 4, iclass 19, count 0 2006.173.07:22:04.98#ibcon#read 4, iclass 19, count 0 2006.173.07:22:04.98#ibcon#about to read 5, iclass 19, count 0 2006.173.07:22:04.98#ibcon#read 5, iclass 19, count 0 2006.173.07:22:04.98#ibcon#about to read 6, iclass 19, count 0 2006.173.07:22:04.98#ibcon#read 6, iclass 19, count 0 2006.173.07:22:04.98#ibcon#end of sib2, iclass 19, count 0 2006.173.07:22:04.98#ibcon#*mode == 0, iclass 19, count 0 2006.173.07:22:04.98#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.07:22:04.98#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.07:22:04.98#ibcon#*before write, iclass 19, count 0 2006.173.07:22:04.98#ibcon#enter sib2, iclass 19, count 0 2006.173.07:22:04.98#ibcon#flushed, iclass 19, count 0 2006.173.07:22:04.98#ibcon#about to write, iclass 19, count 0 2006.173.07:22:04.98#ibcon#wrote, iclass 19, count 0 2006.173.07:22:04.98#ibcon#about to read 3, iclass 19, count 0 2006.173.07:22:05.02#ibcon#read 3, iclass 19, count 0 2006.173.07:22:05.02#ibcon#about to read 4, iclass 19, count 0 2006.173.07:22:05.02#ibcon#read 4, iclass 19, count 0 2006.173.07:22:05.02#ibcon#about to read 5, iclass 19, count 0 2006.173.07:22:05.02#ibcon#read 5, iclass 19, count 0 2006.173.07:22:05.02#ibcon#about to read 6, iclass 19, count 0 2006.173.07:22:05.02#ibcon#read 6, iclass 19, count 0 2006.173.07:22:05.02#ibcon#end of sib2, iclass 19, count 0 2006.173.07:22:05.02#ibcon#*after write, iclass 19, count 0 2006.173.07:22:05.02#ibcon#*before return 0, iclass 19, count 0 2006.173.07:22:05.02#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.07:22:05.02#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.07:22:05.02#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.07:22:05.02#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.07:22:05.02$vck44/vb=1,4 2006.173.07:22:05.02#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.07:22:05.02#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.07:22:05.02#ibcon#ireg 11 cls_cnt 2 2006.173.07:22:05.02#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.07:22:05.02#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.07:22:05.02#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.07:22:05.02#ibcon#enter wrdev, iclass 21, count 2 2006.173.07:22:05.02#ibcon#first serial, iclass 21, count 2 2006.173.07:22:05.02#ibcon#enter sib2, iclass 21, count 2 2006.173.07:22:05.02#ibcon#flushed, iclass 21, count 2 2006.173.07:22:05.02#ibcon#about to write, iclass 21, count 2 2006.173.07:22:05.02#ibcon#wrote, iclass 21, count 2 2006.173.07:22:05.02#ibcon#about to read 3, iclass 21, count 2 2006.173.07:22:05.04#ibcon#read 3, iclass 21, count 2 2006.173.07:22:05.04#ibcon#about to read 4, iclass 21, count 2 2006.173.07:22:05.04#ibcon#read 4, iclass 21, count 2 2006.173.07:22:05.04#ibcon#about to read 5, iclass 21, count 2 2006.173.07:22:05.04#ibcon#read 5, iclass 21, count 2 2006.173.07:22:05.04#ibcon#about to read 6, iclass 21, count 2 2006.173.07:22:05.04#ibcon#read 6, iclass 21, count 2 2006.173.07:22:05.04#ibcon#end of sib2, iclass 21, count 2 2006.173.07:22:05.04#ibcon#*mode == 0, iclass 21, count 2 2006.173.07:22:05.04#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.07:22:05.04#ibcon#[27=AT01-04\r\n] 2006.173.07:22:05.04#ibcon#*before write, iclass 21, count 2 2006.173.07:22:05.04#ibcon#enter sib2, iclass 21, count 2 2006.173.07:22:05.04#ibcon#flushed, iclass 21, count 2 2006.173.07:22:05.04#ibcon#about to write, iclass 21, count 2 2006.173.07:22:05.04#ibcon#wrote, iclass 21, count 2 2006.173.07:22:05.04#ibcon#about to read 3, iclass 21, count 2 2006.173.07:22:05.07#ibcon#read 3, iclass 21, count 2 2006.173.07:22:05.07#ibcon#about to read 4, iclass 21, count 2 2006.173.07:22:05.07#ibcon#read 4, iclass 21, count 2 2006.173.07:22:05.07#ibcon#about to read 5, iclass 21, count 2 2006.173.07:22:05.07#ibcon#read 5, iclass 21, count 2 2006.173.07:22:05.07#ibcon#about to read 6, iclass 21, count 2 2006.173.07:22:05.07#ibcon#read 6, iclass 21, count 2 2006.173.07:22:05.07#ibcon#end of sib2, iclass 21, count 2 2006.173.07:22:05.07#ibcon#*after write, iclass 21, count 2 2006.173.07:22:05.07#ibcon#*before return 0, iclass 21, count 2 2006.173.07:22:05.07#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.07:22:05.07#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.07:22:05.07#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.07:22:05.07#ibcon#ireg 7 cls_cnt 0 2006.173.07:22:05.07#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.07:22:05.19#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.07:22:05.19#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.07:22:05.19#ibcon#enter wrdev, iclass 21, count 0 2006.173.07:22:05.19#ibcon#first serial, iclass 21, count 0 2006.173.07:22:05.19#ibcon#enter sib2, iclass 21, count 0 2006.173.07:22:05.19#ibcon#flushed, iclass 21, count 0 2006.173.07:22:05.19#ibcon#about to write, iclass 21, count 0 2006.173.07:22:05.19#ibcon#wrote, iclass 21, count 0 2006.173.07:22:05.19#ibcon#about to read 3, iclass 21, count 0 2006.173.07:22:05.21#ibcon#read 3, iclass 21, count 0 2006.173.07:22:05.21#ibcon#about to read 4, iclass 21, count 0 2006.173.07:22:05.21#ibcon#read 4, iclass 21, count 0 2006.173.07:22:05.21#ibcon#about to read 5, iclass 21, count 0 2006.173.07:22:05.21#ibcon#read 5, iclass 21, count 0 2006.173.07:22:05.21#ibcon#about to read 6, iclass 21, count 0 2006.173.07:22:05.21#ibcon#read 6, iclass 21, count 0 2006.173.07:22:05.21#ibcon#end of sib2, iclass 21, count 0 2006.173.07:22:05.21#ibcon#*mode == 0, iclass 21, count 0 2006.173.07:22:05.21#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.07:22:05.21#ibcon#[27=USB\r\n] 2006.173.07:22:05.21#ibcon#*before write, iclass 21, count 0 2006.173.07:22:05.21#ibcon#enter sib2, iclass 21, count 0 2006.173.07:22:05.21#ibcon#flushed, iclass 21, count 0 2006.173.07:22:05.21#ibcon#about to write, iclass 21, count 0 2006.173.07:22:05.21#ibcon#wrote, iclass 21, count 0 2006.173.07:22:05.21#ibcon#about to read 3, iclass 21, count 0 2006.173.07:22:05.24#ibcon#read 3, iclass 21, count 0 2006.173.07:22:05.24#ibcon#about to read 4, iclass 21, count 0 2006.173.07:22:05.24#ibcon#read 4, iclass 21, count 0 2006.173.07:22:05.24#ibcon#about to read 5, iclass 21, count 0 2006.173.07:22:05.24#ibcon#read 5, iclass 21, count 0 2006.173.07:22:05.24#ibcon#about to read 6, iclass 21, count 0 2006.173.07:22:05.24#ibcon#read 6, iclass 21, count 0 2006.173.07:22:05.24#ibcon#end of sib2, iclass 21, count 0 2006.173.07:22:05.24#ibcon#*after write, iclass 21, count 0 2006.173.07:22:05.24#ibcon#*before return 0, iclass 21, count 0 2006.173.07:22:05.24#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.07:22:05.24#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.07:22:05.24#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.07:22:05.24#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.07:22:05.24$vck44/vblo=2,634.99 2006.173.07:22:05.24#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.07:22:05.24#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.07:22:05.24#ibcon#ireg 17 cls_cnt 0 2006.173.07:22:05.24#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.07:22:05.24#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.07:22:05.24#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.07:22:05.24#ibcon#enter wrdev, iclass 23, count 0 2006.173.07:22:05.24#ibcon#first serial, iclass 23, count 0 2006.173.07:22:05.24#ibcon#enter sib2, iclass 23, count 0 2006.173.07:22:05.24#ibcon#flushed, iclass 23, count 0 2006.173.07:22:05.24#ibcon#about to write, iclass 23, count 0 2006.173.07:22:05.24#ibcon#wrote, iclass 23, count 0 2006.173.07:22:05.24#ibcon#about to read 3, iclass 23, count 0 2006.173.07:22:05.26#ibcon#read 3, iclass 23, count 0 2006.173.07:22:05.26#ibcon#about to read 4, iclass 23, count 0 2006.173.07:22:05.26#ibcon#read 4, iclass 23, count 0 2006.173.07:22:05.26#ibcon#about to read 5, iclass 23, count 0 2006.173.07:22:05.26#ibcon#read 5, iclass 23, count 0 2006.173.07:22:05.26#ibcon#about to read 6, iclass 23, count 0 2006.173.07:22:05.26#ibcon#read 6, iclass 23, count 0 2006.173.07:22:05.26#ibcon#end of sib2, iclass 23, count 0 2006.173.07:22:05.26#ibcon#*mode == 0, iclass 23, count 0 2006.173.07:22:05.26#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.07:22:05.26#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.07:22:05.26#ibcon#*before write, iclass 23, count 0 2006.173.07:22:05.26#ibcon#enter sib2, iclass 23, count 0 2006.173.07:22:05.26#ibcon#flushed, iclass 23, count 0 2006.173.07:22:05.26#ibcon#about to write, iclass 23, count 0 2006.173.07:22:05.26#ibcon#wrote, iclass 23, count 0 2006.173.07:22:05.26#ibcon#about to read 3, iclass 23, count 0 2006.173.07:22:05.30#ibcon#read 3, iclass 23, count 0 2006.173.07:22:05.30#ibcon#about to read 4, iclass 23, count 0 2006.173.07:22:05.30#ibcon#read 4, iclass 23, count 0 2006.173.07:22:05.30#ibcon#about to read 5, iclass 23, count 0 2006.173.07:22:05.30#ibcon#read 5, iclass 23, count 0 2006.173.07:22:05.30#ibcon#about to read 6, iclass 23, count 0 2006.173.07:22:05.30#ibcon#read 6, iclass 23, count 0 2006.173.07:22:05.30#ibcon#end of sib2, iclass 23, count 0 2006.173.07:22:05.30#ibcon#*after write, iclass 23, count 0 2006.173.07:22:05.30#ibcon#*before return 0, iclass 23, count 0 2006.173.07:22:05.30#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.07:22:05.30#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.07:22:05.30#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.07:22:05.30#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.07:22:05.30$vck44/vb=2,4 2006.173.07:22:05.30#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.07:22:05.30#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.07:22:05.30#ibcon#ireg 11 cls_cnt 2 2006.173.07:22:05.30#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.07:22:05.36#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.07:22:05.36#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.07:22:05.36#ibcon#enter wrdev, iclass 25, count 2 2006.173.07:22:05.36#ibcon#first serial, iclass 25, count 2 2006.173.07:22:05.36#ibcon#enter sib2, iclass 25, count 2 2006.173.07:22:05.36#ibcon#flushed, iclass 25, count 2 2006.173.07:22:05.36#ibcon#about to write, iclass 25, count 2 2006.173.07:22:05.36#ibcon#wrote, iclass 25, count 2 2006.173.07:22:05.36#ibcon#about to read 3, iclass 25, count 2 2006.173.07:22:05.38#ibcon#read 3, iclass 25, count 2 2006.173.07:22:05.38#ibcon#about to read 4, iclass 25, count 2 2006.173.07:22:05.38#ibcon#read 4, iclass 25, count 2 2006.173.07:22:05.38#ibcon#about to read 5, iclass 25, count 2 2006.173.07:22:05.38#ibcon#read 5, iclass 25, count 2 2006.173.07:22:05.38#ibcon#about to read 6, iclass 25, count 2 2006.173.07:22:05.38#ibcon#read 6, iclass 25, count 2 2006.173.07:22:05.38#ibcon#end of sib2, iclass 25, count 2 2006.173.07:22:05.38#ibcon#*mode == 0, iclass 25, count 2 2006.173.07:22:05.38#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.07:22:05.38#ibcon#[27=AT02-04\r\n] 2006.173.07:22:05.38#ibcon#*before write, iclass 25, count 2 2006.173.07:22:05.38#ibcon#enter sib2, iclass 25, count 2 2006.173.07:22:05.38#ibcon#flushed, iclass 25, count 2 2006.173.07:22:05.38#ibcon#about to write, iclass 25, count 2 2006.173.07:22:05.38#ibcon#wrote, iclass 25, count 2 2006.173.07:22:05.38#ibcon#about to read 3, iclass 25, count 2 2006.173.07:22:05.41#ibcon#read 3, iclass 25, count 2 2006.173.07:22:05.41#ibcon#about to read 4, iclass 25, count 2 2006.173.07:22:05.41#ibcon#read 4, iclass 25, count 2 2006.173.07:22:05.41#ibcon#about to read 5, iclass 25, count 2 2006.173.07:22:05.41#ibcon#read 5, iclass 25, count 2 2006.173.07:22:05.41#ibcon#about to read 6, iclass 25, count 2 2006.173.07:22:05.41#ibcon#read 6, iclass 25, count 2 2006.173.07:22:05.41#ibcon#end of sib2, iclass 25, count 2 2006.173.07:22:05.41#ibcon#*after write, iclass 25, count 2 2006.173.07:22:05.41#ibcon#*before return 0, iclass 25, count 2 2006.173.07:22:05.41#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.07:22:05.41#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.07:22:05.41#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.07:22:05.41#ibcon#ireg 7 cls_cnt 0 2006.173.07:22:05.41#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.07:22:05.53#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.07:22:05.53#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.07:22:05.53#ibcon#enter wrdev, iclass 25, count 0 2006.173.07:22:05.53#ibcon#first serial, iclass 25, count 0 2006.173.07:22:05.53#ibcon#enter sib2, iclass 25, count 0 2006.173.07:22:05.53#ibcon#flushed, iclass 25, count 0 2006.173.07:22:05.53#ibcon#about to write, iclass 25, count 0 2006.173.07:22:05.53#ibcon#wrote, iclass 25, count 0 2006.173.07:22:05.53#ibcon#about to read 3, iclass 25, count 0 2006.173.07:22:05.55#ibcon#read 3, iclass 25, count 0 2006.173.07:22:05.55#ibcon#about to read 4, iclass 25, count 0 2006.173.07:22:05.55#ibcon#read 4, iclass 25, count 0 2006.173.07:22:05.55#ibcon#about to read 5, iclass 25, count 0 2006.173.07:22:05.55#ibcon#read 5, iclass 25, count 0 2006.173.07:22:05.55#ibcon#about to read 6, iclass 25, count 0 2006.173.07:22:05.55#ibcon#read 6, iclass 25, count 0 2006.173.07:22:05.55#ibcon#end of sib2, iclass 25, count 0 2006.173.07:22:05.55#ibcon#*mode == 0, iclass 25, count 0 2006.173.07:22:05.55#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.07:22:05.55#ibcon#[27=USB\r\n] 2006.173.07:22:05.55#ibcon#*before write, iclass 25, count 0 2006.173.07:22:05.55#ibcon#enter sib2, iclass 25, count 0 2006.173.07:22:05.55#ibcon#flushed, iclass 25, count 0 2006.173.07:22:05.55#ibcon#about to write, iclass 25, count 0 2006.173.07:22:05.55#ibcon#wrote, iclass 25, count 0 2006.173.07:22:05.55#ibcon#about to read 3, iclass 25, count 0 2006.173.07:22:05.58#ibcon#read 3, iclass 25, count 0 2006.173.07:22:05.58#ibcon#about to read 4, iclass 25, count 0 2006.173.07:22:05.58#ibcon#read 4, iclass 25, count 0 2006.173.07:22:05.58#ibcon#about to read 5, iclass 25, count 0 2006.173.07:22:05.58#ibcon#read 5, iclass 25, count 0 2006.173.07:22:05.58#ibcon#about to read 6, iclass 25, count 0 2006.173.07:22:05.58#ibcon#read 6, iclass 25, count 0 2006.173.07:22:05.58#ibcon#end of sib2, iclass 25, count 0 2006.173.07:22:05.58#ibcon#*after write, iclass 25, count 0 2006.173.07:22:05.58#ibcon#*before return 0, iclass 25, count 0 2006.173.07:22:05.58#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.07:22:05.58#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.07:22:05.58#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.07:22:05.58#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.07:22:05.58$vck44/vblo=3,649.99 2006.173.07:22:05.58#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.07:22:05.58#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.07:22:05.58#ibcon#ireg 17 cls_cnt 0 2006.173.07:22:05.58#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.07:22:05.58#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.07:22:05.58#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.07:22:05.58#ibcon#enter wrdev, iclass 27, count 0 2006.173.07:22:05.58#ibcon#first serial, iclass 27, count 0 2006.173.07:22:05.58#ibcon#enter sib2, iclass 27, count 0 2006.173.07:22:05.58#ibcon#flushed, iclass 27, count 0 2006.173.07:22:05.58#ibcon#about to write, iclass 27, count 0 2006.173.07:22:05.58#ibcon#wrote, iclass 27, count 0 2006.173.07:22:05.58#ibcon#about to read 3, iclass 27, count 0 2006.173.07:22:05.60#ibcon#read 3, iclass 27, count 0 2006.173.07:22:05.60#ibcon#about to read 4, iclass 27, count 0 2006.173.07:22:05.60#ibcon#read 4, iclass 27, count 0 2006.173.07:22:05.60#ibcon#about to read 5, iclass 27, count 0 2006.173.07:22:05.60#ibcon#read 5, iclass 27, count 0 2006.173.07:22:05.60#ibcon#about to read 6, iclass 27, count 0 2006.173.07:22:05.60#ibcon#read 6, iclass 27, count 0 2006.173.07:22:05.60#ibcon#end of sib2, iclass 27, count 0 2006.173.07:22:05.60#ibcon#*mode == 0, iclass 27, count 0 2006.173.07:22:05.60#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.07:22:05.60#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.07:22:05.60#ibcon#*before write, iclass 27, count 0 2006.173.07:22:05.60#ibcon#enter sib2, iclass 27, count 0 2006.173.07:22:05.60#ibcon#flushed, iclass 27, count 0 2006.173.07:22:05.60#ibcon#about to write, iclass 27, count 0 2006.173.07:22:05.60#ibcon#wrote, iclass 27, count 0 2006.173.07:22:05.60#ibcon#about to read 3, iclass 27, count 0 2006.173.07:22:05.64#ibcon#read 3, iclass 27, count 0 2006.173.07:22:05.64#ibcon#about to read 4, iclass 27, count 0 2006.173.07:22:05.64#ibcon#read 4, iclass 27, count 0 2006.173.07:22:05.64#ibcon#about to read 5, iclass 27, count 0 2006.173.07:22:05.64#ibcon#read 5, iclass 27, count 0 2006.173.07:22:05.64#ibcon#about to read 6, iclass 27, count 0 2006.173.07:22:05.64#ibcon#read 6, iclass 27, count 0 2006.173.07:22:05.64#ibcon#end of sib2, iclass 27, count 0 2006.173.07:22:05.64#ibcon#*after write, iclass 27, count 0 2006.173.07:22:05.64#ibcon#*before return 0, iclass 27, count 0 2006.173.07:22:05.64#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.07:22:05.64#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.07:22:05.64#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.07:22:05.64#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.07:22:05.64$vck44/vb=3,4 2006.173.07:22:05.64#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.07:22:05.64#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.07:22:05.64#ibcon#ireg 11 cls_cnt 2 2006.173.07:22:05.64#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.07:22:05.70#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.07:22:05.70#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.07:22:05.70#ibcon#enter wrdev, iclass 29, count 2 2006.173.07:22:05.70#ibcon#first serial, iclass 29, count 2 2006.173.07:22:05.70#ibcon#enter sib2, iclass 29, count 2 2006.173.07:22:05.70#ibcon#flushed, iclass 29, count 2 2006.173.07:22:05.70#ibcon#about to write, iclass 29, count 2 2006.173.07:22:05.70#ibcon#wrote, iclass 29, count 2 2006.173.07:22:05.70#ibcon#about to read 3, iclass 29, count 2 2006.173.07:22:05.72#ibcon#read 3, iclass 29, count 2 2006.173.07:22:05.72#ibcon#about to read 4, iclass 29, count 2 2006.173.07:22:05.72#ibcon#read 4, iclass 29, count 2 2006.173.07:22:05.72#ibcon#about to read 5, iclass 29, count 2 2006.173.07:22:05.72#ibcon#read 5, iclass 29, count 2 2006.173.07:22:05.72#ibcon#about to read 6, iclass 29, count 2 2006.173.07:22:05.72#ibcon#read 6, iclass 29, count 2 2006.173.07:22:05.72#ibcon#end of sib2, iclass 29, count 2 2006.173.07:22:05.72#ibcon#*mode == 0, iclass 29, count 2 2006.173.07:22:05.72#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.07:22:05.72#ibcon#[27=AT03-04\r\n] 2006.173.07:22:05.72#ibcon#*before write, iclass 29, count 2 2006.173.07:22:05.72#ibcon#enter sib2, iclass 29, count 2 2006.173.07:22:05.72#ibcon#flushed, iclass 29, count 2 2006.173.07:22:05.72#ibcon#about to write, iclass 29, count 2 2006.173.07:22:05.72#ibcon#wrote, iclass 29, count 2 2006.173.07:22:05.72#ibcon#about to read 3, iclass 29, count 2 2006.173.07:22:05.75#ibcon#read 3, iclass 29, count 2 2006.173.07:22:05.75#ibcon#about to read 4, iclass 29, count 2 2006.173.07:22:05.75#ibcon#read 4, iclass 29, count 2 2006.173.07:22:05.75#ibcon#about to read 5, iclass 29, count 2 2006.173.07:22:05.75#ibcon#read 5, iclass 29, count 2 2006.173.07:22:05.75#ibcon#about to read 6, iclass 29, count 2 2006.173.07:22:05.75#ibcon#read 6, iclass 29, count 2 2006.173.07:22:05.75#ibcon#end of sib2, iclass 29, count 2 2006.173.07:22:05.75#ibcon#*after write, iclass 29, count 2 2006.173.07:22:05.75#ibcon#*before return 0, iclass 29, count 2 2006.173.07:22:05.75#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.07:22:05.75#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.07:22:05.75#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.07:22:05.75#ibcon#ireg 7 cls_cnt 0 2006.173.07:22:05.75#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.07:22:05.87#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.07:22:05.87#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.07:22:05.87#ibcon#enter wrdev, iclass 29, count 0 2006.173.07:22:05.87#ibcon#first serial, iclass 29, count 0 2006.173.07:22:05.87#ibcon#enter sib2, iclass 29, count 0 2006.173.07:22:05.87#ibcon#flushed, iclass 29, count 0 2006.173.07:22:05.87#ibcon#about to write, iclass 29, count 0 2006.173.07:22:05.87#ibcon#wrote, iclass 29, count 0 2006.173.07:22:05.87#ibcon#about to read 3, iclass 29, count 0 2006.173.07:22:05.89#ibcon#read 3, iclass 29, count 0 2006.173.07:22:05.89#ibcon#about to read 4, iclass 29, count 0 2006.173.07:22:05.89#ibcon#read 4, iclass 29, count 0 2006.173.07:22:05.89#ibcon#about to read 5, iclass 29, count 0 2006.173.07:22:05.89#ibcon#read 5, iclass 29, count 0 2006.173.07:22:05.89#ibcon#about to read 6, iclass 29, count 0 2006.173.07:22:05.89#ibcon#read 6, iclass 29, count 0 2006.173.07:22:05.89#ibcon#end of sib2, iclass 29, count 0 2006.173.07:22:05.89#ibcon#*mode == 0, iclass 29, count 0 2006.173.07:22:05.89#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.07:22:05.89#ibcon#[27=USB\r\n] 2006.173.07:22:05.89#ibcon#*before write, iclass 29, count 0 2006.173.07:22:05.89#ibcon#enter sib2, iclass 29, count 0 2006.173.07:22:05.89#ibcon#flushed, iclass 29, count 0 2006.173.07:22:05.89#ibcon#about to write, iclass 29, count 0 2006.173.07:22:05.89#ibcon#wrote, iclass 29, count 0 2006.173.07:22:05.89#ibcon#about to read 3, iclass 29, count 0 2006.173.07:22:05.92#ibcon#read 3, iclass 29, count 0 2006.173.07:22:05.92#ibcon#about to read 4, iclass 29, count 0 2006.173.07:22:05.92#ibcon#read 4, iclass 29, count 0 2006.173.07:22:05.92#ibcon#about to read 5, iclass 29, count 0 2006.173.07:22:05.92#ibcon#read 5, iclass 29, count 0 2006.173.07:22:05.92#ibcon#about to read 6, iclass 29, count 0 2006.173.07:22:05.92#ibcon#read 6, iclass 29, count 0 2006.173.07:22:05.92#ibcon#end of sib2, iclass 29, count 0 2006.173.07:22:05.92#ibcon#*after write, iclass 29, count 0 2006.173.07:22:05.92#ibcon#*before return 0, iclass 29, count 0 2006.173.07:22:05.92#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.07:22:05.92#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.07:22:05.92#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.07:22:05.92#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.07:22:05.92$vck44/vblo=4,679.99 2006.173.07:22:05.92#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.07:22:05.92#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.07:22:05.92#ibcon#ireg 17 cls_cnt 0 2006.173.07:22:05.92#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.07:22:05.92#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.07:22:05.92#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.07:22:05.92#ibcon#enter wrdev, iclass 31, count 0 2006.173.07:22:05.92#ibcon#first serial, iclass 31, count 0 2006.173.07:22:05.92#ibcon#enter sib2, iclass 31, count 0 2006.173.07:22:05.92#ibcon#flushed, iclass 31, count 0 2006.173.07:22:05.92#ibcon#about to write, iclass 31, count 0 2006.173.07:22:05.92#ibcon#wrote, iclass 31, count 0 2006.173.07:22:05.92#ibcon#about to read 3, iclass 31, count 0 2006.173.07:22:05.94#ibcon#read 3, iclass 31, count 0 2006.173.07:22:05.94#ibcon#about to read 4, iclass 31, count 0 2006.173.07:22:05.94#ibcon#read 4, iclass 31, count 0 2006.173.07:22:05.94#ibcon#about to read 5, iclass 31, count 0 2006.173.07:22:05.94#ibcon#read 5, iclass 31, count 0 2006.173.07:22:05.94#ibcon#about to read 6, iclass 31, count 0 2006.173.07:22:05.94#ibcon#read 6, iclass 31, count 0 2006.173.07:22:05.94#ibcon#end of sib2, iclass 31, count 0 2006.173.07:22:05.94#ibcon#*mode == 0, iclass 31, count 0 2006.173.07:22:05.94#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.07:22:05.94#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.07:22:05.94#ibcon#*before write, iclass 31, count 0 2006.173.07:22:05.94#ibcon#enter sib2, iclass 31, count 0 2006.173.07:22:05.94#ibcon#flushed, iclass 31, count 0 2006.173.07:22:05.94#ibcon#about to write, iclass 31, count 0 2006.173.07:22:05.94#ibcon#wrote, iclass 31, count 0 2006.173.07:22:05.94#ibcon#about to read 3, iclass 31, count 0 2006.173.07:22:05.98#ibcon#read 3, iclass 31, count 0 2006.173.07:22:05.98#ibcon#about to read 4, iclass 31, count 0 2006.173.07:22:05.98#ibcon#read 4, iclass 31, count 0 2006.173.07:22:05.98#ibcon#about to read 5, iclass 31, count 0 2006.173.07:22:05.98#ibcon#read 5, iclass 31, count 0 2006.173.07:22:05.98#ibcon#about to read 6, iclass 31, count 0 2006.173.07:22:05.98#ibcon#read 6, iclass 31, count 0 2006.173.07:22:05.98#ibcon#end of sib2, iclass 31, count 0 2006.173.07:22:05.98#ibcon#*after write, iclass 31, count 0 2006.173.07:22:05.98#ibcon#*before return 0, iclass 31, count 0 2006.173.07:22:05.98#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.07:22:05.98#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.07:22:05.98#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.07:22:05.98#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.07:22:05.98$vck44/vb=4,4 2006.173.07:22:05.98#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.173.07:22:05.98#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.173.07:22:05.98#ibcon#ireg 11 cls_cnt 2 2006.173.07:22:05.98#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.07:22:06.04#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.07:22:06.04#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.07:22:06.04#ibcon#enter wrdev, iclass 33, count 2 2006.173.07:22:06.04#ibcon#first serial, iclass 33, count 2 2006.173.07:22:06.04#ibcon#enter sib2, iclass 33, count 2 2006.173.07:22:06.04#ibcon#flushed, iclass 33, count 2 2006.173.07:22:06.04#ibcon#about to write, iclass 33, count 2 2006.173.07:22:06.04#ibcon#wrote, iclass 33, count 2 2006.173.07:22:06.04#ibcon#about to read 3, iclass 33, count 2 2006.173.07:22:06.06#ibcon#read 3, iclass 33, count 2 2006.173.07:22:06.06#ibcon#about to read 4, iclass 33, count 2 2006.173.07:22:06.06#ibcon#read 4, iclass 33, count 2 2006.173.07:22:06.06#ibcon#about to read 5, iclass 33, count 2 2006.173.07:22:06.06#ibcon#read 5, iclass 33, count 2 2006.173.07:22:06.06#ibcon#about to read 6, iclass 33, count 2 2006.173.07:22:06.06#ibcon#read 6, iclass 33, count 2 2006.173.07:22:06.06#ibcon#end of sib2, iclass 33, count 2 2006.173.07:22:06.06#ibcon#*mode == 0, iclass 33, count 2 2006.173.07:22:06.06#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.173.07:22:06.06#ibcon#[27=AT04-04\r\n] 2006.173.07:22:06.06#ibcon#*before write, iclass 33, count 2 2006.173.07:22:06.06#ibcon#enter sib2, iclass 33, count 2 2006.173.07:22:06.06#ibcon#flushed, iclass 33, count 2 2006.173.07:22:06.06#ibcon#about to write, iclass 33, count 2 2006.173.07:22:06.06#ibcon#wrote, iclass 33, count 2 2006.173.07:22:06.06#ibcon#about to read 3, iclass 33, count 2 2006.173.07:22:06.09#ibcon#read 3, iclass 33, count 2 2006.173.07:22:06.09#ibcon#about to read 4, iclass 33, count 2 2006.173.07:22:06.09#ibcon#read 4, iclass 33, count 2 2006.173.07:22:06.09#ibcon#about to read 5, iclass 33, count 2 2006.173.07:22:06.09#ibcon#read 5, iclass 33, count 2 2006.173.07:22:06.09#ibcon#about to read 6, iclass 33, count 2 2006.173.07:22:06.09#ibcon#read 6, iclass 33, count 2 2006.173.07:22:06.09#ibcon#end of sib2, iclass 33, count 2 2006.173.07:22:06.09#ibcon#*after write, iclass 33, count 2 2006.173.07:22:06.09#ibcon#*before return 0, iclass 33, count 2 2006.173.07:22:06.09#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.07:22:06.09#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.173.07:22:06.09#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.173.07:22:06.09#ibcon#ireg 7 cls_cnt 0 2006.173.07:22:06.09#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.07:22:06.21#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.07:22:06.21#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.07:22:06.21#ibcon#enter wrdev, iclass 33, count 0 2006.173.07:22:06.21#ibcon#first serial, iclass 33, count 0 2006.173.07:22:06.21#ibcon#enter sib2, iclass 33, count 0 2006.173.07:22:06.21#ibcon#flushed, iclass 33, count 0 2006.173.07:22:06.21#ibcon#about to write, iclass 33, count 0 2006.173.07:22:06.21#ibcon#wrote, iclass 33, count 0 2006.173.07:22:06.21#ibcon#about to read 3, iclass 33, count 0 2006.173.07:22:06.23#ibcon#read 3, iclass 33, count 0 2006.173.07:22:06.23#ibcon#about to read 4, iclass 33, count 0 2006.173.07:22:06.23#ibcon#read 4, iclass 33, count 0 2006.173.07:22:06.23#ibcon#about to read 5, iclass 33, count 0 2006.173.07:22:06.23#ibcon#read 5, iclass 33, count 0 2006.173.07:22:06.23#ibcon#about to read 6, iclass 33, count 0 2006.173.07:22:06.23#ibcon#read 6, iclass 33, count 0 2006.173.07:22:06.23#ibcon#end of sib2, iclass 33, count 0 2006.173.07:22:06.23#ibcon#*mode == 0, iclass 33, count 0 2006.173.07:22:06.23#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.07:22:06.23#ibcon#[27=USB\r\n] 2006.173.07:22:06.23#ibcon#*before write, iclass 33, count 0 2006.173.07:22:06.23#ibcon#enter sib2, iclass 33, count 0 2006.173.07:22:06.23#ibcon#flushed, iclass 33, count 0 2006.173.07:22:06.23#ibcon#about to write, iclass 33, count 0 2006.173.07:22:06.23#ibcon#wrote, iclass 33, count 0 2006.173.07:22:06.23#ibcon#about to read 3, iclass 33, count 0 2006.173.07:22:06.26#ibcon#read 3, iclass 33, count 0 2006.173.07:22:06.26#ibcon#about to read 4, iclass 33, count 0 2006.173.07:22:06.26#ibcon#read 4, iclass 33, count 0 2006.173.07:22:06.26#ibcon#about to read 5, iclass 33, count 0 2006.173.07:22:06.26#ibcon#read 5, iclass 33, count 0 2006.173.07:22:06.26#ibcon#about to read 6, iclass 33, count 0 2006.173.07:22:06.26#ibcon#read 6, iclass 33, count 0 2006.173.07:22:06.26#ibcon#end of sib2, iclass 33, count 0 2006.173.07:22:06.26#ibcon#*after write, iclass 33, count 0 2006.173.07:22:06.26#ibcon#*before return 0, iclass 33, count 0 2006.173.07:22:06.26#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.07:22:06.26#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.173.07:22:06.26#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.07:22:06.26#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.07:22:06.26$vck44/vblo=5,709.99 2006.173.07:22:06.26#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.07:22:06.26#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.07:22:06.26#ibcon#ireg 17 cls_cnt 0 2006.173.07:22:06.26#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.07:22:06.26#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.07:22:06.26#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.07:22:06.26#ibcon#enter wrdev, iclass 35, count 0 2006.173.07:22:06.26#ibcon#first serial, iclass 35, count 0 2006.173.07:22:06.26#ibcon#enter sib2, iclass 35, count 0 2006.173.07:22:06.26#ibcon#flushed, iclass 35, count 0 2006.173.07:22:06.26#ibcon#about to write, iclass 35, count 0 2006.173.07:22:06.26#ibcon#wrote, iclass 35, count 0 2006.173.07:22:06.26#ibcon#about to read 3, iclass 35, count 0 2006.173.07:22:06.28#ibcon#read 3, iclass 35, count 0 2006.173.07:22:06.28#ibcon#about to read 4, iclass 35, count 0 2006.173.07:22:06.28#ibcon#read 4, iclass 35, count 0 2006.173.07:22:06.28#ibcon#about to read 5, iclass 35, count 0 2006.173.07:22:06.28#ibcon#read 5, iclass 35, count 0 2006.173.07:22:06.28#ibcon#about to read 6, iclass 35, count 0 2006.173.07:22:06.28#ibcon#read 6, iclass 35, count 0 2006.173.07:22:06.28#ibcon#end of sib2, iclass 35, count 0 2006.173.07:22:06.28#ibcon#*mode == 0, iclass 35, count 0 2006.173.07:22:06.28#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.07:22:06.28#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.07:22:06.28#ibcon#*before write, iclass 35, count 0 2006.173.07:22:06.28#ibcon#enter sib2, iclass 35, count 0 2006.173.07:22:06.28#ibcon#flushed, iclass 35, count 0 2006.173.07:22:06.28#ibcon#about to write, iclass 35, count 0 2006.173.07:22:06.28#ibcon#wrote, iclass 35, count 0 2006.173.07:22:06.28#ibcon#about to read 3, iclass 35, count 0 2006.173.07:22:06.32#ibcon#read 3, iclass 35, count 0 2006.173.07:22:06.32#ibcon#about to read 4, iclass 35, count 0 2006.173.07:22:06.32#ibcon#read 4, iclass 35, count 0 2006.173.07:22:06.32#ibcon#about to read 5, iclass 35, count 0 2006.173.07:22:06.32#ibcon#read 5, iclass 35, count 0 2006.173.07:22:06.32#ibcon#about to read 6, iclass 35, count 0 2006.173.07:22:06.32#ibcon#read 6, iclass 35, count 0 2006.173.07:22:06.32#ibcon#end of sib2, iclass 35, count 0 2006.173.07:22:06.32#ibcon#*after write, iclass 35, count 0 2006.173.07:22:06.32#ibcon#*before return 0, iclass 35, count 0 2006.173.07:22:06.32#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.07:22:06.32#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.07:22:06.32#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.07:22:06.32#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.07:22:06.32$vck44/vb=5,4 2006.173.07:22:06.32#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.173.07:22:06.32#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.173.07:22:06.32#ibcon#ireg 11 cls_cnt 2 2006.173.07:22:06.32#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.07:22:06.38#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.07:22:06.38#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.07:22:06.38#ibcon#enter wrdev, iclass 37, count 2 2006.173.07:22:06.38#ibcon#first serial, iclass 37, count 2 2006.173.07:22:06.38#ibcon#enter sib2, iclass 37, count 2 2006.173.07:22:06.38#ibcon#flushed, iclass 37, count 2 2006.173.07:22:06.38#ibcon#about to write, iclass 37, count 2 2006.173.07:22:06.38#ibcon#wrote, iclass 37, count 2 2006.173.07:22:06.38#ibcon#about to read 3, iclass 37, count 2 2006.173.07:22:06.40#ibcon#read 3, iclass 37, count 2 2006.173.07:22:06.40#ibcon#about to read 4, iclass 37, count 2 2006.173.07:22:06.40#ibcon#read 4, iclass 37, count 2 2006.173.07:22:06.40#ibcon#about to read 5, iclass 37, count 2 2006.173.07:22:06.40#ibcon#read 5, iclass 37, count 2 2006.173.07:22:06.40#ibcon#about to read 6, iclass 37, count 2 2006.173.07:22:06.40#ibcon#read 6, iclass 37, count 2 2006.173.07:22:06.40#ibcon#end of sib2, iclass 37, count 2 2006.173.07:22:06.40#ibcon#*mode == 0, iclass 37, count 2 2006.173.07:22:06.40#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.173.07:22:06.40#ibcon#[27=AT05-04\r\n] 2006.173.07:22:06.40#ibcon#*before write, iclass 37, count 2 2006.173.07:22:06.40#ibcon#enter sib2, iclass 37, count 2 2006.173.07:22:06.40#ibcon#flushed, iclass 37, count 2 2006.173.07:22:06.40#ibcon#about to write, iclass 37, count 2 2006.173.07:22:06.40#ibcon#wrote, iclass 37, count 2 2006.173.07:22:06.40#ibcon#about to read 3, iclass 37, count 2 2006.173.07:22:06.43#ibcon#read 3, iclass 37, count 2 2006.173.07:22:06.43#ibcon#about to read 4, iclass 37, count 2 2006.173.07:22:06.43#ibcon#read 4, iclass 37, count 2 2006.173.07:22:06.43#ibcon#about to read 5, iclass 37, count 2 2006.173.07:22:06.43#ibcon#read 5, iclass 37, count 2 2006.173.07:22:06.43#ibcon#about to read 6, iclass 37, count 2 2006.173.07:22:06.43#ibcon#read 6, iclass 37, count 2 2006.173.07:22:06.43#ibcon#end of sib2, iclass 37, count 2 2006.173.07:22:06.43#ibcon#*after write, iclass 37, count 2 2006.173.07:22:06.43#ibcon#*before return 0, iclass 37, count 2 2006.173.07:22:06.43#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.07:22:06.43#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.173.07:22:06.43#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.173.07:22:06.43#ibcon#ireg 7 cls_cnt 0 2006.173.07:22:06.43#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.07:22:06.55#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.07:22:06.55#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.07:22:06.55#ibcon#enter wrdev, iclass 37, count 0 2006.173.07:22:06.55#ibcon#first serial, iclass 37, count 0 2006.173.07:22:06.55#ibcon#enter sib2, iclass 37, count 0 2006.173.07:22:06.55#ibcon#flushed, iclass 37, count 0 2006.173.07:22:06.55#ibcon#about to write, iclass 37, count 0 2006.173.07:22:06.55#ibcon#wrote, iclass 37, count 0 2006.173.07:22:06.55#ibcon#about to read 3, iclass 37, count 0 2006.173.07:22:06.57#ibcon#read 3, iclass 37, count 0 2006.173.07:22:06.57#ibcon#about to read 4, iclass 37, count 0 2006.173.07:22:06.57#ibcon#read 4, iclass 37, count 0 2006.173.07:22:06.57#ibcon#about to read 5, iclass 37, count 0 2006.173.07:22:06.57#ibcon#read 5, iclass 37, count 0 2006.173.07:22:06.57#ibcon#about to read 6, iclass 37, count 0 2006.173.07:22:06.57#ibcon#read 6, iclass 37, count 0 2006.173.07:22:06.57#ibcon#end of sib2, iclass 37, count 0 2006.173.07:22:06.57#ibcon#*mode == 0, iclass 37, count 0 2006.173.07:22:06.57#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.07:22:06.57#ibcon#[27=USB\r\n] 2006.173.07:22:06.57#ibcon#*before write, iclass 37, count 0 2006.173.07:22:06.57#ibcon#enter sib2, iclass 37, count 0 2006.173.07:22:06.57#ibcon#flushed, iclass 37, count 0 2006.173.07:22:06.57#ibcon#about to write, iclass 37, count 0 2006.173.07:22:06.57#ibcon#wrote, iclass 37, count 0 2006.173.07:22:06.57#ibcon#about to read 3, iclass 37, count 0 2006.173.07:22:06.60#ibcon#read 3, iclass 37, count 0 2006.173.07:22:06.60#ibcon#about to read 4, iclass 37, count 0 2006.173.07:22:06.60#ibcon#read 4, iclass 37, count 0 2006.173.07:22:06.60#ibcon#about to read 5, iclass 37, count 0 2006.173.07:22:06.60#ibcon#read 5, iclass 37, count 0 2006.173.07:22:06.60#ibcon#about to read 6, iclass 37, count 0 2006.173.07:22:06.60#ibcon#read 6, iclass 37, count 0 2006.173.07:22:06.60#ibcon#end of sib2, iclass 37, count 0 2006.173.07:22:06.60#ibcon#*after write, iclass 37, count 0 2006.173.07:22:06.60#ibcon#*before return 0, iclass 37, count 0 2006.173.07:22:06.60#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.07:22:06.60#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.173.07:22:06.60#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.07:22:06.60#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.07:22:06.60$vck44/vblo=6,719.99 2006.173.07:22:06.60#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.07:22:06.60#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.07:22:06.60#ibcon#ireg 17 cls_cnt 0 2006.173.07:22:06.60#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.07:22:06.60#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.07:22:06.60#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.07:22:06.60#ibcon#enter wrdev, iclass 39, count 0 2006.173.07:22:06.60#ibcon#first serial, iclass 39, count 0 2006.173.07:22:06.60#ibcon#enter sib2, iclass 39, count 0 2006.173.07:22:06.60#ibcon#flushed, iclass 39, count 0 2006.173.07:22:06.60#ibcon#about to write, iclass 39, count 0 2006.173.07:22:06.60#ibcon#wrote, iclass 39, count 0 2006.173.07:22:06.60#ibcon#about to read 3, iclass 39, count 0 2006.173.07:22:06.62#ibcon#read 3, iclass 39, count 0 2006.173.07:22:06.62#ibcon#about to read 4, iclass 39, count 0 2006.173.07:22:06.62#ibcon#read 4, iclass 39, count 0 2006.173.07:22:06.62#ibcon#about to read 5, iclass 39, count 0 2006.173.07:22:06.62#ibcon#read 5, iclass 39, count 0 2006.173.07:22:06.62#ibcon#about to read 6, iclass 39, count 0 2006.173.07:22:06.62#ibcon#read 6, iclass 39, count 0 2006.173.07:22:06.62#ibcon#end of sib2, iclass 39, count 0 2006.173.07:22:06.62#ibcon#*mode == 0, iclass 39, count 0 2006.173.07:22:06.62#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.07:22:06.62#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.07:22:06.62#ibcon#*before write, iclass 39, count 0 2006.173.07:22:06.62#ibcon#enter sib2, iclass 39, count 0 2006.173.07:22:06.62#ibcon#flushed, iclass 39, count 0 2006.173.07:22:06.62#ibcon#about to write, iclass 39, count 0 2006.173.07:22:06.62#ibcon#wrote, iclass 39, count 0 2006.173.07:22:06.62#ibcon#about to read 3, iclass 39, count 0 2006.173.07:22:06.66#ibcon#read 3, iclass 39, count 0 2006.173.07:22:06.66#ibcon#about to read 4, iclass 39, count 0 2006.173.07:22:06.66#ibcon#read 4, iclass 39, count 0 2006.173.07:22:06.66#ibcon#about to read 5, iclass 39, count 0 2006.173.07:22:06.66#ibcon#read 5, iclass 39, count 0 2006.173.07:22:06.66#ibcon#about to read 6, iclass 39, count 0 2006.173.07:22:06.66#ibcon#read 6, iclass 39, count 0 2006.173.07:22:06.66#ibcon#end of sib2, iclass 39, count 0 2006.173.07:22:06.66#ibcon#*after write, iclass 39, count 0 2006.173.07:22:06.66#ibcon#*before return 0, iclass 39, count 0 2006.173.07:22:06.66#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.07:22:06.66#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.07:22:06.66#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.07:22:06.66#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.07:22:06.66$vck44/vb=6,4 2006.173.07:22:06.66#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.07:22:06.66#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.07:22:06.66#ibcon#ireg 11 cls_cnt 2 2006.173.07:22:06.66#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.07:22:06.72#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.07:22:06.72#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.07:22:06.72#ibcon#enter wrdev, iclass 3, count 2 2006.173.07:22:06.72#ibcon#first serial, iclass 3, count 2 2006.173.07:22:06.72#ibcon#enter sib2, iclass 3, count 2 2006.173.07:22:06.72#ibcon#flushed, iclass 3, count 2 2006.173.07:22:06.72#ibcon#about to write, iclass 3, count 2 2006.173.07:22:06.72#ibcon#wrote, iclass 3, count 2 2006.173.07:22:06.72#ibcon#about to read 3, iclass 3, count 2 2006.173.07:22:06.74#ibcon#read 3, iclass 3, count 2 2006.173.07:22:06.74#ibcon#about to read 4, iclass 3, count 2 2006.173.07:22:06.74#ibcon#read 4, iclass 3, count 2 2006.173.07:22:06.74#ibcon#about to read 5, iclass 3, count 2 2006.173.07:22:06.74#ibcon#read 5, iclass 3, count 2 2006.173.07:22:06.74#ibcon#about to read 6, iclass 3, count 2 2006.173.07:22:06.74#ibcon#read 6, iclass 3, count 2 2006.173.07:22:06.74#ibcon#end of sib2, iclass 3, count 2 2006.173.07:22:06.74#ibcon#*mode == 0, iclass 3, count 2 2006.173.07:22:06.74#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.07:22:06.74#ibcon#[27=AT06-04\r\n] 2006.173.07:22:06.74#ibcon#*before write, iclass 3, count 2 2006.173.07:22:06.74#ibcon#enter sib2, iclass 3, count 2 2006.173.07:22:06.74#ibcon#flushed, iclass 3, count 2 2006.173.07:22:06.74#ibcon#about to write, iclass 3, count 2 2006.173.07:22:06.74#ibcon#wrote, iclass 3, count 2 2006.173.07:22:06.74#ibcon#about to read 3, iclass 3, count 2 2006.173.07:22:06.77#ibcon#read 3, iclass 3, count 2 2006.173.07:22:06.77#ibcon#about to read 4, iclass 3, count 2 2006.173.07:22:06.77#ibcon#read 4, iclass 3, count 2 2006.173.07:22:06.77#ibcon#about to read 5, iclass 3, count 2 2006.173.07:22:06.77#ibcon#read 5, iclass 3, count 2 2006.173.07:22:06.77#ibcon#about to read 6, iclass 3, count 2 2006.173.07:22:06.77#ibcon#read 6, iclass 3, count 2 2006.173.07:22:06.77#ibcon#end of sib2, iclass 3, count 2 2006.173.07:22:06.77#ibcon#*after write, iclass 3, count 2 2006.173.07:22:06.77#ibcon#*before return 0, iclass 3, count 2 2006.173.07:22:06.77#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.07:22:06.77#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.07:22:06.77#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.07:22:06.77#ibcon#ireg 7 cls_cnt 0 2006.173.07:22:06.77#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.07:22:06.82#abcon#<5=/02 0.4 0.6 23.78 831004.5\r\n> 2006.173.07:22:06.84#abcon#{5=INTERFACE CLEAR} 2006.173.07:22:06.89#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.07:22:06.89#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.07:22:06.89#ibcon#enter wrdev, iclass 3, count 0 2006.173.07:22:06.89#ibcon#first serial, iclass 3, count 0 2006.173.07:22:06.89#ibcon#enter sib2, iclass 3, count 0 2006.173.07:22:06.89#ibcon#flushed, iclass 3, count 0 2006.173.07:22:06.89#ibcon#about to write, iclass 3, count 0 2006.173.07:22:06.89#ibcon#wrote, iclass 3, count 0 2006.173.07:22:06.89#ibcon#about to read 3, iclass 3, count 0 2006.173.07:22:06.90#abcon#[5=S1D000X0/0*\r\n] 2006.173.07:22:06.91#ibcon#read 3, iclass 3, count 0 2006.173.07:22:06.91#ibcon#about to read 4, iclass 3, count 0 2006.173.07:22:06.91#ibcon#read 4, iclass 3, count 0 2006.173.07:22:06.91#ibcon#about to read 5, iclass 3, count 0 2006.173.07:22:06.91#ibcon#read 5, iclass 3, count 0 2006.173.07:22:06.91#ibcon#about to read 6, iclass 3, count 0 2006.173.07:22:06.91#ibcon#read 6, iclass 3, count 0 2006.173.07:22:06.91#ibcon#end of sib2, iclass 3, count 0 2006.173.07:22:06.91#ibcon#*mode == 0, iclass 3, count 0 2006.173.07:22:06.91#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.07:22:06.91#ibcon#[27=USB\r\n] 2006.173.07:22:06.91#ibcon#*before write, iclass 3, count 0 2006.173.07:22:06.91#ibcon#enter sib2, iclass 3, count 0 2006.173.07:22:06.91#ibcon#flushed, iclass 3, count 0 2006.173.07:22:06.91#ibcon#about to write, iclass 3, count 0 2006.173.07:22:06.91#ibcon#wrote, iclass 3, count 0 2006.173.07:22:06.91#ibcon#about to read 3, iclass 3, count 0 2006.173.07:22:06.94#ibcon#read 3, iclass 3, count 0 2006.173.07:22:06.94#ibcon#about to read 4, iclass 3, count 0 2006.173.07:22:06.94#ibcon#read 4, iclass 3, count 0 2006.173.07:22:06.94#ibcon#about to read 5, iclass 3, count 0 2006.173.07:22:06.94#ibcon#read 5, iclass 3, count 0 2006.173.07:22:06.94#ibcon#about to read 6, iclass 3, count 0 2006.173.07:22:06.94#ibcon#read 6, iclass 3, count 0 2006.173.07:22:06.94#ibcon#end of sib2, iclass 3, count 0 2006.173.07:22:06.94#ibcon#*after write, iclass 3, count 0 2006.173.07:22:06.94#ibcon#*before return 0, iclass 3, count 0 2006.173.07:22:06.94#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.07:22:06.94#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.07:22:06.94#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.07:22:06.94#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.07:22:06.94$vck44/vblo=7,734.99 2006.173.07:22:06.94#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.07:22:06.94#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.07:22:06.94#ibcon#ireg 17 cls_cnt 0 2006.173.07:22:06.94#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.07:22:06.94#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.07:22:06.94#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.07:22:06.94#ibcon#enter wrdev, iclass 11, count 0 2006.173.07:22:06.94#ibcon#first serial, iclass 11, count 0 2006.173.07:22:06.94#ibcon#enter sib2, iclass 11, count 0 2006.173.07:22:06.94#ibcon#flushed, iclass 11, count 0 2006.173.07:22:06.94#ibcon#about to write, iclass 11, count 0 2006.173.07:22:06.94#ibcon#wrote, iclass 11, count 0 2006.173.07:22:06.94#ibcon#about to read 3, iclass 11, count 0 2006.173.07:22:06.96#ibcon#read 3, iclass 11, count 0 2006.173.07:22:06.96#ibcon#about to read 4, iclass 11, count 0 2006.173.07:22:06.96#ibcon#read 4, iclass 11, count 0 2006.173.07:22:06.96#ibcon#about to read 5, iclass 11, count 0 2006.173.07:22:06.96#ibcon#read 5, iclass 11, count 0 2006.173.07:22:06.96#ibcon#about to read 6, iclass 11, count 0 2006.173.07:22:06.96#ibcon#read 6, iclass 11, count 0 2006.173.07:22:06.96#ibcon#end of sib2, iclass 11, count 0 2006.173.07:22:06.96#ibcon#*mode == 0, iclass 11, count 0 2006.173.07:22:06.96#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.07:22:06.96#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.07:22:06.96#ibcon#*before write, iclass 11, count 0 2006.173.07:22:06.96#ibcon#enter sib2, iclass 11, count 0 2006.173.07:22:06.96#ibcon#flushed, iclass 11, count 0 2006.173.07:22:06.96#ibcon#about to write, iclass 11, count 0 2006.173.07:22:06.96#ibcon#wrote, iclass 11, count 0 2006.173.07:22:06.96#ibcon#about to read 3, iclass 11, count 0 2006.173.07:22:07.00#ibcon#read 3, iclass 11, count 0 2006.173.07:22:07.00#ibcon#about to read 4, iclass 11, count 0 2006.173.07:22:07.00#ibcon#read 4, iclass 11, count 0 2006.173.07:22:07.00#ibcon#about to read 5, iclass 11, count 0 2006.173.07:22:07.00#ibcon#read 5, iclass 11, count 0 2006.173.07:22:07.00#ibcon#about to read 6, iclass 11, count 0 2006.173.07:22:07.00#ibcon#read 6, iclass 11, count 0 2006.173.07:22:07.00#ibcon#end of sib2, iclass 11, count 0 2006.173.07:22:07.00#ibcon#*after write, iclass 11, count 0 2006.173.07:22:07.00#ibcon#*before return 0, iclass 11, count 0 2006.173.07:22:07.00#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.07:22:07.00#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.07:22:07.00#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.07:22:07.00#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.07:22:07.00$vck44/vb=7,4 2006.173.07:22:07.00#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.173.07:22:07.00#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.173.07:22:07.00#ibcon#ireg 11 cls_cnt 2 2006.173.07:22:07.00#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.07:22:07.06#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.07:22:07.06#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.07:22:07.06#ibcon#enter wrdev, iclass 13, count 2 2006.173.07:22:07.06#ibcon#first serial, iclass 13, count 2 2006.173.07:22:07.06#ibcon#enter sib2, iclass 13, count 2 2006.173.07:22:07.06#ibcon#flushed, iclass 13, count 2 2006.173.07:22:07.06#ibcon#about to write, iclass 13, count 2 2006.173.07:22:07.06#ibcon#wrote, iclass 13, count 2 2006.173.07:22:07.06#ibcon#about to read 3, iclass 13, count 2 2006.173.07:22:07.08#ibcon#read 3, iclass 13, count 2 2006.173.07:22:07.08#ibcon#about to read 4, iclass 13, count 2 2006.173.07:22:07.08#ibcon#read 4, iclass 13, count 2 2006.173.07:22:07.08#ibcon#about to read 5, iclass 13, count 2 2006.173.07:22:07.08#ibcon#read 5, iclass 13, count 2 2006.173.07:22:07.08#ibcon#about to read 6, iclass 13, count 2 2006.173.07:22:07.08#ibcon#read 6, iclass 13, count 2 2006.173.07:22:07.08#ibcon#end of sib2, iclass 13, count 2 2006.173.07:22:07.08#ibcon#*mode == 0, iclass 13, count 2 2006.173.07:22:07.08#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.173.07:22:07.08#ibcon#[27=AT07-04\r\n] 2006.173.07:22:07.08#ibcon#*before write, iclass 13, count 2 2006.173.07:22:07.08#ibcon#enter sib2, iclass 13, count 2 2006.173.07:22:07.08#ibcon#flushed, iclass 13, count 2 2006.173.07:22:07.08#ibcon#about to write, iclass 13, count 2 2006.173.07:22:07.08#ibcon#wrote, iclass 13, count 2 2006.173.07:22:07.08#ibcon#about to read 3, iclass 13, count 2 2006.173.07:22:07.11#ibcon#read 3, iclass 13, count 2 2006.173.07:22:07.11#ibcon#about to read 4, iclass 13, count 2 2006.173.07:22:07.11#ibcon#read 4, iclass 13, count 2 2006.173.07:22:07.11#ibcon#about to read 5, iclass 13, count 2 2006.173.07:22:07.11#ibcon#read 5, iclass 13, count 2 2006.173.07:22:07.11#ibcon#about to read 6, iclass 13, count 2 2006.173.07:22:07.11#ibcon#read 6, iclass 13, count 2 2006.173.07:22:07.11#ibcon#end of sib2, iclass 13, count 2 2006.173.07:22:07.11#ibcon#*after write, iclass 13, count 2 2006.173.07:22:07.11#ibcon#*before return 0, iclass 13, count 2 2006.173.07:22:07.11#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.07:22:07.11#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.173.07:22:07.11#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.173.07:22:07.11#ibcon#ireg 7 cls_cnt 0 2006.173.07:22:07.11#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.07:22:07.23#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.07:22:07.23#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.07:22:07.23#ibcon#enter wrdev, iclass 13, count 0 2006.173.07:22:07.23#ibcon#first serial, iclass 13, count 0 2006.173.07:22:07.23#ibcon#enter sib2, iclass 13, count 0 2006.173.07:22:07.23#ibcon#flushed, iclass 13, count 0 2006.173.07:22:07.23#ibcon#about to write, iclass 13, count 0 2006.173.07:22:07.23#ibcon#wrote, iclass 13, count 0 2006.173.07:22:07.23#ibcon#about to read 3, iclass 13, count 0 2006.173.07:22:07.25#ibcon#read 3, iclass 13, count 0 2006.173.07:22:07.25#ibcon#about to read 4, iclass 13, count 0 2006.173.07:22:07.25#ibcon#read 4, iclass 13, count 0 2006.173.07:22:07.25#ibcon#about to read 5, iclass 13, count 0 2006.173.07:22:07.25#ibcon#read 5, iclass 13, count 0 2006.173.07:22:07.25#ibcon#about to read 6, iclass 13, count 0 2006.173.07:22:07.25#ibcon#read 6, iclass 13, count 0 2006.173.07:22:07.25#ibcon#end of sib2, iclass 13, count 0 2006.173.07:22:07.25#ibcon#*mode == 0, iclass 13, count 0 2006.173.07:22:07.25#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.07:22:07.25#ibcon#[27=USB\r\n] 2006.173.07:22:07.25#ibcon#*before write, iclass 13, count 0 2006.173.07:22:07.25#ibcon#enter sib2, iclass 13, count 0 2006.173.07:22:07.25#ibcon#flushed, iclass 13, count 0 2006.173.07:22:07.25#ibcon#about to write, iclass 13, count 0 2006.173.07:22:07.25#ibcon#wrote, iclass 13, count 0 2006.173.07:22:07.25#ibcon#about to read 3, iclass 13, count 0 2006.173.07:22:07.28#ibcon#read 3, iclass 13, count 0 2006.173.07:22:07.28#ibcon#about to read 4, iclass 13, count 0 2006.173.07:22:07.28#ibcon#read 4, iclass 13, count 0 2006.173.07:22:07.28#ibcon#about to read 5, iclass 13, count 0 2006.173.07:22:07.28#ibcon#read 5, iclass 13, count 0 2006.173.07:22:07.28#ibcon#about to read 6, iclass 13, count 0 2006.173.07:22:07.28#ibcon#read 6, iclass 13, count 0 2006.173.07:22:07.28#ibcon#end of sib2, iclass 13, count 0 2006.173.07:22:07.28#ibcon#*after write, iclass 13, count 0 2006.173.07:22:07.28#ibcon#*before return 0, iclass 13, count 0 2006.173.07:22:07.28#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.07:22:07.28#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.173.07:22:07.28#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.07:22:07.28#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.07:22:07.28$vck44/vblo=8,744.99 2006.173.07:22:07.28#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.07:22:07.28#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.07:22:07.28#ibcon#ireg 17 cls_cnt 0 2006.173.07:22:07.28#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.07:22:07.28#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.07:22:07.28#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.07:22:07.28#ibcon#enter wrdev, iclass 15, count 0 2006.173.07:22:07.28#ibcon#first serial, iclass 15, count 0 2006.173.07:22:07.28#ibcon#enter sib2, iclass 15, count 0 2006.173.07:22:07.28#ibcon#flushed, iclass 15, count 0 2006.173.07:22:07.28#ibcon#about to write, iclass 15, count 0 2006.173.07:22:07.28#ibcon#wrote, iclass 15, count 0 2006.173.07:22:07.28#ibcon#about to read 3, iclass 15, count 0 2006.173.07:22:07.30#ibcon#read 3, iclass 15, count 0 2006.173.07:22:07.30#ibcon#about to read 4, iclass 15, count 0 2006.173.07:22:07.30#ibcon#read 4, iclass 15, count 0 2006.173.07:22:07.30#ibcon#about to read 5, iclass 15, count 0 2006.173.07:22:07.30#ibcon#read 5, iclass 15, count 0 2006.173.07:22:07.30#ibcon#about to read 6, iclass 15, count 0 2006.173.07:22:07.30#ibcon#read 6, iclass 15, count 0 2006.173.07:22:07.30#ibcon#end of sib2, iclass 15, count 0 2006.173.07:22:07.30#ibcon#*mode == 0, iclass 15, count 0 2006.173.07:22:07.30#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.07:22:07.30#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.07:22:07.30#ibcon#*before write, iclass 15, count 0 2006.173.07:22:07.30#ibcon#enter sib2, iclass 15, count 0 2006.173.07:22:07.30#ibcon#flushed, iclass 15, count 0 2006.173.07:22:07.30#ibcon#about to write, iclass 15, count 0 2006.173.07:22:07.30#ibcon#wrote, iclass 15, count 0 2006.173.07:22:07.30#ibcon#about to read 3, iclass 15, count 0 2006.173.07:22:07.34#ibcon#read 3, iclass 15, count 0 2006.173.07:22:07.34#ibcon#about to read 4, iclass 15, count 0 2006.173.07:22:07.34#ibcon#read 4, iclass 15, count 0 2006.173.07:22:07.34#ibcon#about to read 5, iclass 15, count 0 2006.173.07:22:07.34#ibcon#read 5, iclass 15, count 0 2006.173.07:22:07.34#ibcon#about to read 6, iclass 15, count 0 2006.173.07:22:07.34#ibcon#read 6, iclass 15, count 0 2006.173.07:22:07.34#ibcon#end of sib2, iclass 15, count 0 2006.173.07:22:07.34#ibcon#*after write, iclass 15, count 0 2006.173.07:22:07.34#ibcon#*before return 0, iclass 15, count 0 2006.173.07:22:07.34#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.07:22:07.34#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.07:22:07.34#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.07:22:07.34#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.07:22:07.34$vck44/vb=8,4 2006.173.07:22:07.34#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.07:22:07.34#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.07:22:07.34#ibcon#ireg 11 cls_cnt 2 2006.173.07:22:07.34#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.07:22:07.40#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.07:22:07.40#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.07:22:07.40#ibcon#enter wrdev, iclass 17, count 2 2006.173.07:22:07.40#ibcon#first serial, iclass 17, count 2 2006.173.07:22:07.40#ibcon#enter sib2, iclass 17, count 2 2006.173.07:22:07.40#ibcon#flushed, iclass 17, count 2 2006.173.07:22:07.40#ibcon#about to write, iclass 17, count 2 2006.173.07:22:07.40#ibcon#wrote, iclass 17, count 2 2006.173.07:22:07.40#ibcon#about to read 3, iclass 17, count 2 2006.173.07:22:07.42#ibcon#read 3, iclass 17, count 2 2006.173.07:22:07.42#ibcon#about to read 4, iclass 17, count 2 2006.173.07:22:07.42#ibcon#read 4, iclass 17, count 2 2006.173.07:22:07.42#ibcon#about to read 5, iclass 17, count 2 2006.173.07:22:07.42#ibcon#read 5, iclass 17, count 2 2006.173.07:22:07.42#ibcon#about to read 6, iclass 17, count 2 2006.173.07:22:07.42#ibcon#read 6, iclass 17, count 2 2006.173.07:22:07.42#ibcon#end of sib2, iclass 17, count 2 2006.173.07:22:07.42#ibcon#*mode == 0, iclass 17, count 2 2006.173.07:22:07.42#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.07:22:07.42#ibcon#[27=AT08-04\r\n] 2006.173.07:22:07.42#ibcon#*before write, iclass 17, count 2 2006.173.07:22:07.42#ibcon#enter sib2, iclass 17, count 2 2006.173.07:22:07.42#ibcon#flushed, iclass 17, count 2 2006.173.07:22:07.42#ibcon#about to write, iclass 17, count 2 2006.173.07:22:07.42#ibcon#wrote, iclass 17, count 2 2006.173.07:22:07.42#ibcon#about to read 3, iclass 17, count 2 2006.173.07:22:07.45#ibcon#read 3, iclass 17, count 2 2006.173.07:22:07.45#ibcon#about to read 4, iclass 17, count 2 2006.173.07:22:07.45#ibcon#read 4, iclass 17, count 2 2006.173.07:22:07.45#ibcon#about to read 5, iclass 17, count 2 2006.173.07:22:07.45#ibcon#read 5, iclass 17, count 2 2006.173.07:22:07.45#ibcon#about to read 6, iclass 17, count 2 2006.173.07:22:07.45#ibcon#read 6, iclass 17, count 2 2006.173.07:22:07.45#ibcon#end of sib2, iclass 17, count 2 2006.173.07:22:07.45#ibcon#*after write, iclass 17, count 2 2006.173.07:22:07.45#ibcon#*before return 0, iclass 17, count 2 2006.173.07:22:07.45#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.07:22:07.45#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.07:22:07.45#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.07:22:07.45#ibcon#ireg 7 cls_cnt 0 2006.173.07:22:07.45#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.07:22:07.57#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.07:22:07.57#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.07:22:07.57#ibcon#enter wrdev, iclass 17, count 0 2006.173.07:22:07.57#ibcon#first serial, iclass 17, count 0 2006.173.07:22:07.57#ibcon#enter sib2, iclass 17, count 0 2006.173.07:22:07.57#ibcon#flushed, iclass 17, count 0 2006.173.07:22:07.57#ibcon#about to write, iclass 17, count 0 2006.173.07:22:07.57#ibcon#wrote, iclass 17, count 0 2006.173.07:22:07.57#ibcon#about to read 3, iclass 17, count 0 2006.173.07:22:07.59#ibcon#read 3, iclass 17, count 0 2006.173.07:22:07.59#ibcon#about to read 4, iclass 17, count 0 2006.173.07:22:07.59#ibcon#read 4, iclass 17, count 0 2006.173.07:22:07.59#ibcon#about to read 5, iclass 17, count 0 2006.173.07:22:07.59#ibcon#read 5, iclass 17, count 0 2006.173.07:22:07.59#ibcon#about to read 6, iclass 17, count 0 2006.173.07:22:07.59#ibcon#read 6, iclass 17, count 0 2006.173.07:22:07.59#ibcon#end of sib2, iclass 17, count 0 2006.173.07:22:07.59#ibcon#*mode == 0, iclass 17, count 0 2006.173.07:22:07.59#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.07:22:07.59#ibcon#[27=USB\r\n] 2006.173.07:22:07.59#ibcon#*before write, iclass 17, count 0 2006.173.07:22:07.59#ibcon#enter sib2, iclass 17, count 0 2006.173.07:22:07.59#ibcon#flushed, iclass 17, count 0 2006.173.07:22:07.59#ibcon#about to write, iclass 17, count 0 2006.173.07:22:07.59#ibcon#wrote, iclass 17, count 0 2006.173.07:22:07.59#ibcon#about to read 3, iclass 17, count 0 2006.173.07:22:07.62#ibcon#read 3, iclass 17, count 0 2006.173.07:22:07.62#ibcon#about to read 4, iclass 17, count 0 2006.173.07:22:07.62#ibcon#read 4, iclass 17, count 0 2006.173.07:22:07.62#ibcon#about to read 5, iclass 17, count 0 2006.173.07:22:07.62#ibcon#read 5, iclass 17, count 0 2006.173.07:22:07.62#ibcon#about to read 6, iclass 17, count 0 2006.173.07:22:07.62#ibcon#read 6, iclass 17, count 0 2006.173.07:22:07.62#ibcon#end of sib2, iclass 17, count 0 2006.173.07:22:07.62#ibcon#*after write, iclass 17, count 0 2006.173.07:22:07.62#ibcon#*before return 0, iclass 17, count 0 2006.173.07:22:07.62#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.07:22:07.62#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.07:22:07.62#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.07:22:07.62#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.07:22:07.62$vck44/vabw=wide 2006.173.07:22:07.62#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.07:22:07.62#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.07:22:07.62#ibcon#ireg 8 cls_cnt 0 2006.173.07:22:07.62#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.07:22:07.62#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.07:22:07.62#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.07:22:07.62#ibcon#enter wrdev, iclass 19, count 0 2006.173.07:22:07.62#ibcon#first serial, iclass 19, count 0 2006.173.07:22:07.62#ibcon#enter sib2, iclass 19, count 0 2006.173.07:22:07.62#ibcon#flushed, iclass 19, count 0 2006.173.07:22:07.62#ibcon#about to write, iclass 19, count 0 2006.173.07:22:07.62#ibcon#wrote, iclass 19, count 0 2006.173.07:22:07.62#ibcon#about to read 3, iclass 19, count 0 2006.173.07:22:07.64#ibcon#read 3, iclass 19, count 0 2006.173.07:22:07.64#ibcon#about to read 4, iclass 19, count 0 2006.173.07:22:07.64#ibcon#read 4, iclass 19, count 0 2006.173.07:22:07.64#ibcon#about to read 5, iclass 19, count 0 2006.173.07:22:07.64#ibcon#read 5, iclass 19, count 0 2006.173.07:22:07.64#ibcon#about to read 6, iclass 19, count 0 2006.173.07:22:07.64#ibcon#read 6, iclass 19, count 0 2006.173.07:22:07.64#ibcon#end of sib2, iclass 19, count 0 2006.173.07:22:07.64#ibcon#*mode == 0, iclass 19, count 0 2006.173.07:22:07.64#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.07:22:07.64#ibcon#[25=BW32\r\n] 2006.173.07:22:07.64#ibcon#*before write, iclass 19, count 0 2006.173.07:22:07.64#ibcon#enter sib2, iclass 19, count 0 2006.173.07:22:07.64#ibcon#flushed, iclass 19, count 0 2006.173.07:22:07.64#ibcon#about to write, iclass 19, count 0 2006.173.07:22:07.64#ibcon#wrote, iclass 19, count 0 2006.173.07:22:07.64#ibcon#about to read 3, iclass 19, count 0 2006.173.07:22:07.67#ibcon#read 3, iclass 19, count 0 2006.173.07:22:07.67#ibcon#about to read 4, iclass 19, count 0 2006.173.07:22:07.67#ibcon#read 4, iclass 19, count 0 2006.173.07:22:07.67#ibcon#about to read 5, iclass 19, count 0 2006.173.07:22:07.67#ibcon#read 5, iclass 19, count 0 2006.173.07:22:07.67#ibcon#about to read 6, iclass 19, count 0 2006.173.07:22:07.67#ibcon#read 6, iclass 19, count 0 2006.173.07:22:07.67#ibcon#end of sib2, iclass 19, count 0 2006.173.07:22:07.67#ibcon#*after write, iclass 19, count 0 2006.173.07:22:07.67#ibcon#*before return 0, iclass 19, count 0 2006.173.07:22:07.67#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.07:22:07.67#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.07:22:07.67#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.07:22:07.67#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.07:22:07.67$vck44/vbbw=wide 2006.173.07:22:07.67#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.07:22:07.67#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.07:22:07.67#ibcon#ireg 8 cls_cnt 0 2006.173.07:22:07.67#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.07:22:07.74#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.07:22:07.74#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.07:22:07.74#ibcon#enter wrdev, iclass 21, count 0 2006.173.07:22:07.74#ibcon#first serial, iclass 21, count 0 2006.173.07:22:07.74#ibcon#enter sib2, iclass 21, count 0 2006.173.07:22:07.74#ibcon#flushed, iclass 21, count 0 2006.173.07:22:07.74#ibcon#about to write, iclass 21, count 0 2006.173.07:22:07.74#ibcon#wrote, iclass 21, count 0 2006.173.07:22:07.74#ibcon#about to read 3, iclass 21, count 0 2006.173.07:22:07.76#ibcon#read 3, iclass 21, count 0 2006.173.07:22:07.76#ibcon#about to read 4, iclass 21, count 0 2006.173.07:22:07.76#ibcon#read 4, iclass 21, count 0 2006.173.07:22:07.76#ibcon#about to read 5, iclass 21, count 0 2006.173.07:22:07.76#ibcon#read 5, iclass 21, count 0 2006.173.07:22:07.76#ibcon#about to read 6, iclass 21, count 0 2006.173.07:22:07.76#ibcon#read 6, iclass 21, count 0 2006.173.07:22:07.76#ibcon#end of sib2, iclass 21, count 0 2006.173.07:22:07.76#ibcon#*mode == 0, iclass 21, count 0 2006.173.07:22:07.76#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.07:22:07.76#ibcon#[27=BW32\r\n] 2006.173.07:22:07.76#ibcon#*before write, iclass 21, count 0 2006.173.07:22:07.76#ibcon#enter sib2, iclass 21, count 0 2006.173.07:22:07.76#ibcon#flushed, iclass 21, count 0 2006.173.07:22:07.76#ibcon#about to write, iclass 21, count 0 2006.173.07:22:07.76#ibcon#wrote, iclass 21, count 0 2006.173.07:22:07.76#ibcon#about to read 3, iclass 21, count 0 2006.173.07:22:07.79#ibcon#read 3, iclass 21, count 0 2006.173.07:22:07.79#ibcon#about to read 4, iclass 21, count 0 2006.173.07:22:07.79#ibcon#read 4, iclass 21, count 0 2006.173.07:22:07.79#ibcon#about to read 5, iclass 21, count 0 2006.173.07:22:07.79#ibcon#read 5, iclass 21, count 0 2006.173.07:22:07.79#ibcon#about to read 6, iclass 21, count 0 2006.173.07:22:07.79#ibcon#read 6, iclass 21, count 0 2006.173.07:22:07.79#ibcon#end of sib2, iclass 21, count 0 2006.173.07:22:07.79#ibcon#*after write, iclass 21, count 0 2006.173.07:22:07.79#ibcon#*before return 0, iclass 21, count 0 2006.173.07:22:07.79#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.07:22:07.79#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.07:22:07.79#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.07:22:07.79#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.07:22:07.79$setupk4/ifdk4 2006.173.07:22:07.79$ifdk4/lo= 2006.173.07:22:07.79$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.07:22:07.79$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.07:22:07.79$ifdk4/patch= 2006.173.07:22:07.79$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.07:22:07.79$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.07:22:07.79$setupk4/!*+20s 2006.173.07:22:16.99#abcon#<5=/02 0.4 0.6 23.78 831004.5\r\n> 2006.173.07:22:17.01#abcon#{5=INTERFACE CLEAR} 2006.173.07:22:17.07#abcon#[5=S1D000X0/0*\r\n] 2006.173.07:22:22.30$setupk4/"tpicd 2006.173.07:22:22.30$setupk4/echo=off 2006.173.07:22:22.30$setupk4/xlog=off 2006.173.07:22:22.30:!2006.173.07:23:59 2006.173.07:22:37.14#trakl#Source acquired 2006.173.07:22:37.14#flagr#flagr/antenna,acquired 2006.173.07:23:59.00:preob 2006.173.07:23:59.14/onsource/TRACKING 2006.173.07:23:59.14:!2006.173.07:24:09 2006.173.07:24:09.00:"tape 2006.173.07:24:09.00:"st=record 2006.173.07:24:09.00:data_valid=on 2006.173.07:24:09.00:midob 2006.173.07:24:10.14/onsource/TRACKING 2006.173.07:24:10.14/wx/23.76,1004.6,82 2006.173.07:24:10.21/cable/+6.5008E-03 2006.173.07:24:11.30/va/01,07,usb,yes,36,39 2006.173.07:24:11.30/va/02,06,usb,yes,36,37 2006.173.07:24:11.30/va/03,05,usb,yes,45,47 2006.173.07:24:11.30/va/04,06,usb,yes,37,39 2006.173.07:24:11.30/va/05,04,usb,yes,29,29 2006.173.07:24:11.30/va/06,03,usb,yes,40,40 2006.173.07:24:11.30/va/07,04,usb,yes,33,34 2006.173.07:24:11.30/va/08,04,usb,yes,28,33 2006.173.07:24:11.53/valo/01,524.99,yes,locked 2006.173.07:24:11.53/valo/02,534.99,yes,locked 2006.173.07:24:11.53/valo/03,564.99,yes,locked 2006.173.07:24:11.53/valo/04,624.99,yes,locked 2006.173.07:24:11.53/valo/05,734.99,yes,locked 2006.173.07:24:11.53/valo/06,814.99,yes,locked 2006.173.07:24:11.53/valo/07,864.99,yes,locked 2006.173.07:24:11.53/valo/08,884.99,yes,locked 2006.173.07:24:12.62/vb/01,04,usb,yes,29,27 2006.173.07:24:12.62/vb/02,04,usb,yes,31,31 2006.173.07:24:12.62/vb/03,04,usb,yes,28,31 2006.173.07:24:12.62/vb/04,04,usb,yes,33,32 2006.173.07:24:12.62/vb/05,04,usb,yes,25,28 2006.173.07:24:12.62/vb/06,04,usb,yes,30,26 2006.173.07:24:12.62/vb/07,04,usb,yes,29,29 2006.173.07:24:12.62/vb/08,04,usb,yes,27,30 2006.173.07:24:12.86/vblo/01,629.99,yes,locked 2006.173.07:24:12.86/vblo/02,634.99,yes,locked 2006.173.07:24:12.86/vblo/03,649.99,yes,locked 2006.173.07:24:12.86/vblo/04,679.99,yes,locked 2006.173.07:24:12.86/vblo/05,709.99,yes,locked 2006.173.07:24:12.86/vblo/06,719.99,yes,locked 2006.173.07:24:12.86/vblo/07,734.99,yes,locked 2006.173.07:24:12.86/vblo/08,744.99,yes,locked 2006.173.07:24:13.01/vabw/8 2006.173.07:24:13.16/vbbw/8 2006.173.07:24:13.25/xfe/off,on,15.0 2006.173.07:24:13.65/ifatt/23,28,28,28 2006.173.07:24:14.07/fmout-gps/S +3.95E-07 2006.173.07:24:14.12:!2006.173.07:25:59 2006.173.07:25:59.01:data_valid=off 2006.173.07:25:59.02:"et 2006.173.07:25:59.02:!+3s 2006.173.07:26:02.03:"tape 2006.173.07:26:02.03:postob 2006.173.07:26:02.21/cable/+6.5025E-03 2006.173.07:26:02.21/wx/23.76,1004.6,83 2006.173.07:26:02.27/fmout-gps/S +3.95E-07 2006.173.07:26:02.28:scan_name=173-0727,jd0606,90 2006.173.07:26:02.28:source=3c274,123049.42,122328.0,2000.0,ccw 2006.173.07:26:03.14#flagr#flagr/antenna,new-source 2006.173.07:26:03.14:checkk5 2006.173.07:26:03.58/chk_autoobs//k5ts1/ autoobs is running! 2006.173.07:26:03.97/chk_autoobs//k5ts2/ autoobs is running! 2006.173.07:26:04.37/chk_autoobs//k5ts3/ autoobs is running! 2006.173.07:26:04.78/chk_autoobs//k5ts4/ autoobs is running! 2006.173.07:26:05.16/chk_obsdata//k5ts1/T1730724??a.dat file size is correct (nominal:440MB, actual:436MB). 2006.173.07:26:05.57/chk_obsdata//k5ts2/T1730724??b.dat file size is correct (nominal:440MB, actual:436MB). 2006.173.07:26:05.96/chk_obsdata//k5ts3/T1730724??c.dat file size is correct (nominal:440MB, actual:436MB). 2006.173.07:26:06.36/chk_obsdata//k5ts4/T1730724??d.dat file size is correct (nominal:440MB, actual:436MB). 2006.173.07:26:07.09/k5log//k5ts1_log_newline 2006.173.07:26:07.79/k5log//k5ts2_log_newline 2006.173.07:26:08.50/k5log//k5ts3_log_newline 2006.173.07:26:09.20/k5log//k5ts4_log_newline 2006.173.07:26:09.23/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.07:26:09.23:setupk4=1 2006.173.07:26:09.23$setupk4/echo=on 2006.173.07:26:09.23$setupk4/pcalon 2006.173.07:26:09.23$pcalon/"no phase cal control is implemented here 2006.173.07:26:09.23$setupk4/"tpicd=stop 2006.173.07:26:09.23$setupk4/"rec=synch_on 2006.173.07:26:09.23$setupk4/"rec_mode=128 2006.173.07:26:09.23$setupk4/!* 2006.173.07:26:09.23$setupk4/recpk4 2006.173.07:26:09.23$recpk4/recpatch= 2006.173.07:26:09.23$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.07:26:09.23$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.07:26:09.23$setupk4/vck44 2006.173.07:26:09.23$vck44/valo=1,524.99 2006.173.07:26:09.23#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.07:26:09.23#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.07:26:09.23#ibcon#ireg 17 cls_cnt 0 2006.173.07:26:09.23#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.07:26:09.23#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.07:26:09.23#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.07:26:09.23#ibcon#enter wrdev, iclass 10, count 0 2006.173.07:26:09.23#ibcon#first serial, iclass 10, count 0 2006.173.07:26:09.23#ibcon#enter sib2, iclass 10, count 0 2006.173.07:26:09.23#ibcon#flushed, iclass 10, count 0 2006.173.07:26:09.23#ibcon#about to write, iclass 10, count 0 2006.173.07:26:09.23#ibcon#wrote, iclass 10, count 0 2006.173.07:26:09.23#ibcon#about to read 3, iclass 10, count 0 2006.173.07:26:09.25#ibcon#read 3, iclass 10, count 0 2006.173.07:26:09.25#ibcon#about to read 4, iclass 10, count 0 2006.173.07:26:09.25#ibcon#read 4, iclass 10, count 0 2006.173.07:26:09.25#ibcon#about to read 5, iclass 10, count 0 2006.173.07:26:09.25#ibcon#read 5, iclass 10, count 0 2006.173.07:26:09.25#ibcon#about to read 6, iclass 10, count 0 2006.173.07:26:09.25#ibcon#read 6, iclass 10, count 0 2006.173.07:26:09.25#ibcon#end of sib2, iclass 10, count 0 2006.173.07:26:09.25#ibcon#*mode == 0, iclass 10, count 0 2006.173.07:26:09.25#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.07:26:09.25#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.07:26:09.25#ibcon#*before write, iclass 10, count 0 2006.173.07:26:09.25#ibcon#enter sib2, iclass 10, count 0 2006.173.07:26:09.25#ibcon#flushed, iclass 10, count 0 2006.173.07:26:09.25#ibcon#about to write, iclass 10, count 0 2006.173.07:26:09.25#ibcon#wrote, iclass 10, count 0 2006.173.07:26:09.25#ibcon#about to read 3, iclass 10, count 0 2006.173.07:26:09.30#ibcon#read 3, iclass 10, count 0 2006.173.07:26:09.30#ibcon#about to read 4, iclass 10, count 0 2006.173.07:26:09.30#ibcon#read 4, iclass 10, count 0 2006.173.07:26:09.30#ibcon#about to read 5, iclass 10, count 0 2006.173.07:26:09.30#ibcon#read 5, iclass 10, count 0 2006.173.07:26:09.30#ibcon#about to read 6, iclass 10, count 0 2006.173.07:26:09.30#ibcon#read 6, iclass 10, count 0 2006.173.07:26:09.30#ibcon#end of sib2, iclass 10, count 0 2006.173.07:26:09.30#ibcon#*after write, iclass 10, count 0 2006.173.07:26:09.30#ibcon#*before return 0, iclass 10, count 0 2006.173.07:26:09.30#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.07:26:09.30#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.07:26:09.30#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.07:26:09.30#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.07:26:09.30$vck44/va=1,7 2006.173.07:26:09.30#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.07:26:09.30#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.07:26:09.30#ibcon#ireg 11 cls_cnt 2 2006.173.07:26:09.30#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.07:26:09.30#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.07:26:09.30#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.07:26:09.30#ibcon#enter wrdev, iclass 12, count 2 2006.173.07:26:09.30#ibcon#first serial, iclass 12, count 2 2006.173.07:26:09.30#ibcon#enter sib2, iclass 12, count 2 2006.173.07:26:09.30#ibcon#flushed, iclass 12, count 2 2006.173.07:26:09.30#ibcon#about to write, iclass 12, count 2 2006.173.07:26:09.30#ibcon#wrote, iclass 12, count 2 2006.173.07:26:09.30#ibcon#about to read 3, iclass 12, count 2 2006.173.07:26:09.32#ibcon#read 3, iclass 12, count 2 2006.173.07:26:09.32#ibcon#about to read 4, iclass 12, count 2 2006.173.07:26:09.32#ibcon#read 4, iclass 12, count 2 2006.173.07:26:09.32#ibcon#about to read 5, iclass 12, count 2 2006.173.07:26:09.32#ibcon#read 5, iclass 12, count 2 2006.173.07:26:09.32#ibcon#about to read 6, iclass 12, count 2 2006.173.07:26:09.32#ibcon#read 6, iclass 12, count 2 2006.173.07:26:09.32#ibcon#end of sib2, iclass 12, count 2 2006.173.07:26:09.32#ibcon#*mode == 0, iclass 12, count 2 2006.173.07:26:09.32#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.07:26:09.32#ibcon#[25=AT01-07\r\n] 2006.173.07:26:09.32#ibcon#*before write, iclass 12, count 2 2006.173.07:26:09.32#ibcon#enter sib2, iclass 12, count 2 2006.173.07:26:09.32#ibcon#flushed, iclass 12, count 2 2006.173.07:26:09.32#ibcon#about to write, iclass 12, count 2 2006.173.07:26:09.32#ibcon#wrote, iclass 12, count 2 2006.173.07:26:09.32#ibcon#about to read 3, iclass 12, count 2 2006.173.07:26:09.35#ibcon#read 3, iclass 12, count 2 2006.173.07:26:09.35#ibcon#about to read 4, iclass 12, count 2 2006.173.07:26:09.35#ibcon#read 4, iclass 12, count 2 2006.173.07:26:09.35#ibcon#about to read 5, iclass 12, count 2 2006.173.07:26:09.35#ibcon#read 5, iclass 12, count 2 2006.173.07:26:09.35#ibcon#about to read 6, iclass 12, count 2 2006.173.07:26:09.35#ibcon#read 6, iclass 12, count 2 2006.173.07:26:09.35#ibcon#end of sib2, iclass 12, count 2 2006.173.07:26:09.35#ibcon#*after write, iclass 12, count 2 2006.173.07:26:09.35#ibcon#*before return 0, iclass 12, count 2 2006.173.07:26:09.35#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.07:26:09.35#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.07:26:09.35#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.07:26:09.35#ibcon#ireg 7 cls_cnt 0 2006.173.07:26:09.35#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.07:26:09.47#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.07:26:09.47#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.07:26:09.47#ibcon#enter wrdev, iclass 12, count 0 2006.173.07:26:09.47#ibcon#first serial, iclass 12, count 0 2006.173.07:26:09.47#ibcon#enter sib2, iclass 12, count 0 2006.173.07:26:09.47#ibcon#flushed, iclass 12, count 0 2006.173.07:26:09.47#ibcon#about to write, iclass 12, count 0 2006.173.07:26:09.47#ibcon#wrote, iclass 12, count 0 2006.173.07:26:09.47#ibcon#about to read 3, iclass 12, count 0 2006.173.07:26:09.49#ibcon#read 3, iclass 12, count 0 2006.173.07:26:09.49#ibcon#about to read 4, iclass 12, count 0 2006.173.07:26:09.49#ibcon#read 4, iclass 12, count 0 2006.173.07:26:09.49#ibcon#about to read 5, iclass 12, count 0 2006.173.07:26:09.49#ibcon#read 5, iclass 12, count 0 2006.173.07:26:09.49#ibcon#about to read 6, iclass 12, count 0 2006.173.07:26:09.49#ibcon#read 6, iclass 12, count 0 2006.173.07:26:09.49#ibcon#end of sib2, iclass 12, count 0 2006.173.07:26:09.49#ibcon#*mode == 0, iclass 12, count 0 2006.173.07:26:09.49#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.07:26:09.49#ibcon#[25=USB\r\n] 2006.173.07:26:09.49#ibcon#*before write, iclass 12, count 0 2006.173.07:26:09.49#ibcon#enter sib2, iclass 12, count 0 2006.173.07:26:09.49#ibcon#flushed, iclass 12, count 0 2006.173.07:26:09.49#ibcon#about to write, iclass 12, count 0 2006.173.07:26:09.49#ibcon#wrote, iclass 12, count 0 2006.173.07:26:09.49#ibcon#about to read 3, iclass 12, count 0 2006.173.07:26:09.52#ibcon#read 3, iclass 12, count 0 2006.173.07:26:09.52#ibcon#about to read 4, iclass 12, count 0 2006.173.07:26:09.52#ibcon#read 4, iclass 12, count 0 2006.173.07:26:09.52#ibcon#about to read 5, iclass 12, count 0 2006.173.07:26:09.52#ibcon#read 5, iclass 12, count 0 2006.173.07:26:09.52#ibcon#about to read 6, iclass 12, count 0 2006.173.07:26:09.52#ibcon#read 6, iclass 12, count 0 2006.173.07:26:09.52#ibcon#end of sib2, iclass 12, count 0 2006.173.07:26:09.52#ibcon#*after write, iclass 12, count 0 2006.173.07:26:09.52#ibcon#*before return 0, iclass 12, count 0 2006.173.07:26:09.52#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.07:26:09.52#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.07:26:09.52#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.07:26:09.52#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.07:26:09.52$vck44/valo=2,534.99 2006.173.07:26:09.52#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.07:26:09.52#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.07:26:09.52#ibcon#ireg 17 cls_cnt 0 2006.173.07:26:09.52#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.07:26:09.52#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.07:26:09.52#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.07:26:09.52#ibcon#enter wrdev, iclass 14, count 0 2006.173.07:26:09.52#ibcon#first serial, iclass 14, count 0 2006.173.07:26:09.52#ibcon#enter sib2, iclass 14, count 0 2006.173.07:26:09.52#ibcon#flushed, iclass 14, count 0 2006.173.07:26:09.52#ibcon#about to write, iclass 14, count 0 2006.173.07:26:09.52#ibcon#wrote, iclass 14, count 0 2006.173.07:26:09.52#ibcon#about to read 3, iclass 14, count 0 2006.173.07:26:09.54#ibcon#read 3, iclass 14, count 0 2006.173.07:26:09.54#ibcon#about to read 4, iclass 14, count 0 2006.173.07:26:09.54#ibcon#read 4, iclass 14, count 0 2006.173.07:26:09.54#ibcon#about to read 5, iclass 14, count 0 2006.173.07:26:09.54#ibcon#read 5, iclass 14, count 0 2006.173.07:26:09.54#ibcon#about to read 6, iclass 14, count 0 2006.173.07:26:09.54#ibcon#read 6, iclass 14, count 0 2006.173.07:26:09.54#ibcon#end of sib2, iclass 14, count 0 2006.173.07:26:09.54#ibcon#*mode == 0, iclass 14, count 0 2006.173.07:26:09.54#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.07:26:09.54#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.07:26:09.54#ibcon#*before write, iclass 14, count 0 2006.173.07:26:09.54#ibcon#enter sib2, iclass 14, count 0 2006.173.07:26:09.54#ibcon#flushed, iclass 14, count 0 2006.173.07:26:09.54#ibcon#about to write, iclass 14, count 0 2006.173.07:26:09.54#ibcon#wrote, iclass 14, count 0 2006.173.07:26:09.54#ibcon#about to read 3, iclass 14, count 0 2006.173.07:26:09.58#ibcon#read 3, iclass 14, count 0 2006.173.07:26:09.58#ibcon#about to read 4, iclass 14, count 0 2006.173.07:26:09.58#ibcon#read 4, iclass 14, count 0 2006.173.07:26:09.58#ibcon#about to read 5, iclass 14, count 0 2006.173.07:26:09.58#ibcon#read 5, iclass 14, count 0 2006.173.07:26:09.58#ibcon#about to read 6, iclass 14, count 0 2006.173.07:26:09.58#ibcon#read 6, iclass 14, count 0 2006.173.07:26:09.58#ibcon#end of sib2, iclass 14, count 0 2006.173.07:26:09.58#ibcon#*after write, iclass 14, count 0 2006.173.07:26:09.58#ibcon#*before return 0, iclass 14, count 0 2006.173.07:26:09.58#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.07:26:09.58#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.07:26:09.58#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.07:26:09.58#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.07:26:09.58$vck44/va=2,6 2006.173.07:26:09.58#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.07:26:09.58#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.07:26:09.58#ibcon#ireg 11 cls_cnt 2 2006.173.07:26:09.58#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.07:26:09.64#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.07:26:09.64#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.07:26:09.64#ibcon#enter wrdev, iclass 16, count 2 2006.173.07:26:09.64#ibcon#first serial, iclass 16, count 2 2006.173.07:26:09.64#ibcon#enter sib2, iclass 16, count 2 2006.173.07:26:09.64#ibcon#flushed, iclass 16, count 2 2006.173.07:26:09.64#ibcon#about to write, iclass 16, count 2 2006.173.07:26:09.64#ibcon#wrote, iclass 16, count 2 2006.173.07:26:09.64#ibcon#about to read 3, iclass 16, count 2 2006.173.07:26:09.66#ibcon#read 3, iclass 16, count 2 2006.173.07:26:09.66#ibcon#about to read 4, iclass 16, count 2 2006.173.07:26:09.66#ibcon#read 4, iclass 16, count 2 2006.173.07:26:09.66#ibcon#about to read 5, iclass 16, count 2 2006.173.07:26:09.66#ibcon#read 5, iclass 16, count 2 2006.173.07:26:09.66#ibcon#about to read 6, iclass 16, count 2 2006.173.07:26:09.66#ibcon#read 6, iclass 16, count 2 2006.173.07:26:09.66#ibcon#end of sib2, iclass 16, count 2 2006.173.07:26:09.66#ibcon#*mode == 0, iclass 16, count 2 2006.173.07:26:09.66#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.07:26:09.66#ibcon#[25=AT02-06\r\n] 2006.173.07:26:09.66#ibcon#*before write, iclass 16, count 2 2006.173.07:26:09.66#ibcon#enter sib2, iclass 16, count 2 2006.173.07:26:09.66#ibcon#flushed, iclass 16, count 2 2006.173.07:26:09.66#ibcon#about to write, iclass 16, count 2 2006.173.07:26:09.66#ibcon#wrote, iclass 16, count 2 2006.173.07:26:09.66#ibcon#about to read 3, iclass 16, count 2 2006.173.07:26:09.69#ibcon#read 3, iclass 16, count 2 2006.173.07:26:09.69#ibcon#about to read 4, iclass 16, count 2 2006.173.07:26:09.69#ibcon#read 4, iclass 16, count 2 2006.173.07:26:09.69#ibcon#about to read 5, iclass 16, count 2 2006.173.07:26:09.69#ibcon#read 5, iclass 16, count 2 2006.173.07:26:09.69#ibcon#about to read 6, iclass 16, count 2 2006.173.07:26:09.69#ibcon#read 6, iclass 16, count 2 2006.173.07:26:09.69#ibcon#end of sib2, iclass 16, count 2 2006.173.07:26:09.69#ibcon#*after write, iclass 16, count 2 2006.173.07:26:09.69#ibcon#*before return 0, iclass 16, count 2 2006.173.07:26:09.69#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.07:26:09.69#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.07:26:09.69#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.07:26:09.69#ibcon#ireg 7 cls_cnt 0 2006.173.07:26:09.69#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.07:26:09.81#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.07:26:09.81#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.07:26:09.81#ibcon#enter wrdev, iclass 16, count 0 2006.173.07:26:09.81#ibcon#first serial, iclass 16, count 0 2006.173.07:26:09.81#ibcon#enter sib2, iclass 16, count 0 2006.173.07:26:09.81#ibcon#flushed, iclass 16, count 0 2006.173.07:26:09.81#ibcon#about to write, iclass 16, count 0 2006.173.07:26:09.81#ibcon#wrote, iclass 16, count 0 2006.173.07:26:09.81#ibcon#about to read 3, iclass 16, count 0 2006.173.07:26:09.83#ibcon#read 3, iclass 16, count 0 2006.173.07:26:09.83#ibcon#about to read 4, iclass 16, count 0 2006.173.07:26:09.83#ibcon#read 4, iclass 16, count 0 2006.173.07:26:09.83#ibcon#about to read 5, iclass 16, count 0 2006.173.07:26:09.83#ibcon#read 5, iclass 16, count 0 2006.173.07:26:09.83#ibcon#about to read 6, iclass 16, count 0 2006.173.07:26:09.83#ibcon#read 6, iclass 16, count 0 2006.173.07:26:09.83#ibcon#end of sib2, iclass 16, count 0 2006.173.07:26:09.83#ibcon#*mode == 0, iclass 16, count 0 2006.173.07:26:09.83#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.07:26:09.83#ibcon#[25=USB\r\n] 2006.173.07:26:09.83#ibcon#*before write, iclass 16, count 0 2006.173.07:26:09.83#ibcon#enter sib2, iclass 16, count 0 2006.173.07:26:09.83#ibcon#flushed, iclass 16, count 0 2006.173.07:26:09.83#ibcon#about to write, iclass 16, count 0 2006.173.07:26:09.83#ibcon#wrote, iclass 16, count 0 2006.173.07:26:09.83#ibcon#about to read 3, iclass 16, count 0 2006.173.07:26:09.86#ibcon#read 3, iclass 16, count 0 2006.173.07:26:09.86#ibcon#about to read 4, iclass 16, count 0 2006.173.07:26:09.86#ibcon#read 4, iclass 16, count 0 2006.173.07:26:09.86#ibcon#about to read 5, iclass 16, count 0 2006.173.07:26:09.86#ibcon#read 5, iclass 16, count 0 2006.173.07:26:09.86#ibcon#about to read 6, iclass 16, count 0 2006.173.07:26:09.86#ibcon#read 6, iclass 16, count 0 2006.173.07:26:09.86#ibcon#end of sib2, iclass 16, count 0 2006.173.07:26:09.86#ibcon#*after write, iclass 16, count 0 2006.173.07:26:09.86#ibcon#*before return 0, iclass 16, count 0 2006.173.07:26:09.86#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.07:26:09.86#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.07:26:09.86#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.07:26:09.86#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.07:26:09.86$vck44/valo=3,564.99 2006.173.07:26:09.86#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.07:26:09.86#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.07:26:09.86#ibcon#ireg 17 cls_cnt 0 2006.173.07:26:09.86#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.07:26:09.86#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.07:26:09.86#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.07:26:09.86#ibcon#enter wrdev, iclass 18, count 0 2006.173.07:26:09.86#ibcon#first serial, iclass 18, count 0 2006.173.07:26:09.86#ibcon#enter sib2, iclass 18, count 0 2006.173.07:26:09.86#ibcon#flushed, iclass 18, count 0 2006.173.07:26:09.86#ibcon#about to write, iclass 18, count 0 2006.173.07:26:09.86#ibcon#wrote, iclass 18, count 0 2006.173.07:26:09.86#ibcon#about to read 3, iclass 18, count 0 2006.173.07:26:09.88#ibcon#read 3, iclass 18, count 0 2006.173.07:26:09.88#ibcon#about to read 4, iclass 18, count 0 2006.173.07:26:09.88#ibcon#read 4, iclass 18, count 0 2006.173.07:26:09.88#ibcon#about to read 5, iclass 18, count 0 2006.173.07:26:09.88#ibcon#read 5, iclass 18, count 0 2006.173.07:26:09.88#ibcon#about to read 6, iclass 18, count 0 2006.173.07:26:09.88#ibcon#read 6, iclass 18, count 0 2006.173.07:26:09.88#ibcon#end of sib2, iclass 18, count 0 2006.173.07:26:09.88#ibcon#*mode == 0, iclass 18, count 0 2006.173.07:26:09.88#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.07:26:09.88#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.07:26:09.88#ibcon#*before write, iclass 18, count 0 2006.173.07:26:09.88#ibcon#enter sib2, iclass 18, count 0 2006.173.07:26:09.88#ibcon#flushed, iclass 18, count 0 2006.173.07:26:09.88#ibcon#about to write, iclass 18, count 0 2006.173.07:26:09.88#ibcon#wrote, iclass 18, count 0 2006.173.07:26:09.88#ibcon#about to read 3, iclass 18, count 0 2006.173.07:26:09.92#ibcon#read 3, iclass 18, count 0 2006.173.07:26:09.92#ibcon#about to read 4, iclass 18, count 0 2006.173.07:26:09.92#ibcon#read 4, iclass 18, count 0 2006.173.07:26:09.92#ibcon#about to read 5, iclass 18, count 0 2006.173.07:26:09.92#ibcon#read 5, iclass 18, count 0 2006.173.07:26:09.92#ibcon#about to read 6, iclass 18, count 0 2006.173.07:26:09.92#ibcon#read 6, iclass 18, count 0 2006.173.07:26:09.92#ibcon#end of sib2, iclass 18, count 0 2006.173.07:26:09.92#ibcon#*after write, iclass 18, count 0 2006.173.07:26:09.92#ibcon#*before return 0, iclass 18, count 0 2006.173.07:26:09.92#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.07:26:09.92#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.07:26:09.92#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.07:26:09.92#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.07:26:09.92$vck44/va=3,5 2006.173.07:26:09.92#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.07:26:09.92#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.07:26:09.92#ibcon#ireg 11 cls_cnt 2 2006.173.07:26:09.92#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.07:26:09.98#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.07:26:09.98#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.07:26:09.98#ibcon#enter wrdev, iclass 20, count 2 2006.173.07:26:09.98#ibcon#first serial, iclass 20, count 2 2006.173.07:26:09.98#ibcon#enter sib2, iclass 20, count 2 2006.173.07:26:09.98#ibcon#flushed, iclass 20, count 2 2006.173.07:26:09.98#ibcon#about to write, iclass 20, count 2 2006.173.07:26:09.98#ibcon#wrote, iclass 20, count 2 2006.173.07:26:09.98#ibcon#about to read 3, iclass 20, count 2 2006.173.07:26:10.00#ibcon#read 3, iclass 20, count 2 2006.173.07:26:10.00#ibcon#about to read 4, iclass 20, count 2 2006.173.07:26:10.00#ibcon#read 4, iclass 20, count 2 2006.173.07:26:10.00#ibcon#about to read 5, iclass 20, count 2 2006.173.07:26:10.00#ibcon#read 5, iclass 20, count 2 2006.173.07:26:10.00#ibcon#about to read 6, iclass 20, count 2 2006.173.07:26:10.00#ibcon#read 6, iclass 20, count 2 2006.173.07:26:10.00#ibcon#end of sib2, iclass 20, count 2 2006.173.07:26:10.00#ibcon#*mode == 0, iclass 20, count 2 2006.173.07:26:10.00#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.07:26:10.00#ibcon#[25=AT03-05\r\n] 2006.173.07:26:10.00#ibcon#*before write, iclass 20, count 2 2006.173.07:26:10.00#ibcon#enter sib2, iclass 20, count 2 2006.173.07:26:10.00#ibcon#flushed, iclass 20, count 2 2006.173.07:26:10.00#ibcon#about to write, iclass 20, count 2 2006.173.07:26:10.00#ibcon#wrote, iclass 20, count 2 2006.173.07:26:10.00#ibcon#about to read 3, iclass 20, count 2 2006.173.07:26:10.03#ibcon#read 3, iclass 20, count 2 2006.173.07:26:10.03#ibcon#about to read 4, iclass 20, count 2 2006.173.07:26:10.03#ibcon#read 4, iclass 20, count 2 2006.173.07:26:10.03#ibcon#about to read 5, iclass 20, count 2 2006.173.07:26:10.03#ibcon#read 5, iclass 20, count 2 2006.173.07:26:10.03#ibcon#about to read 6, iclass 20, count 2 2006.173.07:26:10.03#ibcon#read 6, iclass 20, count 2 2006.173.07:26:10.03#ibcon#end of sib2, iclass 20, count 2 2006.173.07:26:10.03#ibcon#*after write, iclass 20, count 2 2006.173.07:26:10.03#ibcon#*before return 0, iclass 20, count 2 2006.173.07:26:10.03#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.07:26:10.03#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.07:26:10.03#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.07:26:10.03#ibcon#ireg 7 cls_cnt 0 2006.173.07:26:10.03#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.07:26:10.15#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.07:26:10.15#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.07:26:10.15#ibcon#enter wrdev, iclass 20, count 0 2006.173.07:26:10.15#ibcon#first serial, iclass 20, count 0 2006.173.07:26:10.15#ibcon#enter sib2, iclass 20, count 0 2006.173.07:26:10.15#ibcon#flushed, iclass 20, count 0 2006.173.07:26:10.15#ibcon#about to write, iclass 20, count 0 2006.173.07:26:10.15#ibcon#wrote, iclass 20, count 0 2006.173.07:26:10.15#ibcon#about to read 3, iclass 20, count 0 2006.173.07:26:10.17#ibcon#read 3, iclass 20, count 0 2006.173.07:26:10.17#ibcon#about to read 4, iclass 20, count 0 2006.173.07:26:10.17#ibcon#read 4, iclass 20, count 0 2006.173.07:26:10.17#ibcon#about to read 5, iclass 20, count 0 2006.173.07:26:10.17#ibcon#read 5, iclass 20, count 0 2006.173.07:26:10.17#ibcon#about to read 6, iclass 20, count 0 2006.173.07:26:10.17#ibcon#read 6, iclass 20, count 0 2006.173.07:26:10.17#ibcon#end of sib2, iclass 20, count 0 2006.173.07:26:10.17#ibcon#*mode == 0, iclass 20, count 0 2006.173.07:26:10.17#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.07:26:10.17#ibcon#[25=USB\r\n] 2006.173.07:26:10.17#ibcon#*before write, iclass 20, count 0 2006.173.07:26:10.17#ibcon#enter sib2, iclass 20, count 0 2006.173.07:26:10.17#ibcon#flushed, iclass 20, count 0 2006.173.07:26:10.17#ibcon#about to write, iclass 20, count 0 2006.173.07:26:10.17#ibcon#wrote, iclass 20, count 0 2006.173.07:26:10.17#ibcon#about to read 3, iclass 20, count 0 2006.173.07:26:10.20#ibcon#read 3, iclass 20, count 0 2006.173.07:26:10.20#ibcon#about to read 4, iclass 20, count 0 2006.173.07:26:10.20#ibcon#read 4, iclass 20, count 0 2006.173.07:26:10.20#ibcon#about to read 5, iclass 20, count 0 2006.173.07:26:10.20#ibcon#read 5, iclass 20, count 0 2006.173.07:26:10.20#ibcon#about to read 6, iclass 20, count 0 2006.173.07:26:10.20#ibcon#read 6, iclass 20, count 0 2006.173.07:26:10.20#ibcon#end of sib2, iclass 20, count 0 2006.173.07:26:10.20#ibcon#*after write, iclass 20, count 0 2006.173.07:26:10.20#ibcon#*before return 0, iclass 20, count 0 2006.173.07:26:10.20#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.07:26:10.20#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.07:26:10.20#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.07:26:10.20#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.07:26:10.20$vck44/valo=4,624.99 2006.173.07:26:10.20#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.07:26:10.20#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.07:26:10.20#ibcon#ireg 17 cls_cnt 0 2006.173.07:26:10.20#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.07:26:10.20#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.07:26:10.20#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.07:26:10.20#ibcon#enter wrdev, iclass 22, count 0 2006.173.07:26:10.20#ibcon#first serial, iclass 22, count 0 2006.173.07:26:10.20#ibcon#enter sib2, iclass 22, count 0 2006.173.07:26:10.20#ibcon#flushed, iclass 22, count 0 2006.173.07:26:10.20#ibcon#about to write, iclass 22, count 0 2006.173.07:26:10.20#ibcon#wrote, iclass 22, count 0 2006.173.07:26:10.20#ibcon#about to read 3, iclass 22, count 0 2006.173.07:26:10.22#ibcon#read 3, iclass 22, count 0 2006.173.07:26:10.22#ibcon#about to read 4, iclass 22, count 0 2006.173.07:26:10.22#ibcon#read 4, iclass 22, count 0 2006.173.07:26:10.22#ibcon#about to read 5, iclass 22, count 0 2006.173.07:26:10.22#ibcon#read 5, iclass 22, count 0 2006.173.07:26:10.22#ibcon#about to read 6, iclass 22, count 0 2006.173.07:26:10.22#ibcon#read 6, iclass 22, count 0 2006.173.07:26:10.22#ibcon#end of sib2, iclass 22, count 0 2006.173.07:26:10.22#ibcon#*mode == 0, iclass 22, count 0 2006.173.07:26:10.22#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.07:26:10.22#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.07:26:10.22#ibcon#*before write, iclass 22, count 0 2006.173.07:26:10.22#ibcon#enter sib2, iclass 22, count 0 2006.173.07:26:10.22#ibcon#flushed, iclass 22, count 0 2006.173.07:26:10.22#ibcon#about to write, iclass 22, count 0 2006.173.07:26:10.22#ibcon#wrote, iclass 22, count 0 2006.173.07:26:10.22#ibcon#about to read 3, iclass 22, count 0 2006.173.07:26:10.26#ibcon#read 3, iclass 22, count 0 2006.173.07:26:10.26#ibcon#about to read 4, iclass 22, count 0 2006.173.07:26:10.26#ibcon#read 4, iclass 22, count 0 2006.173.07:26:10.26#ibcon#about to read 5, iclass 22, count 0 2006.173.07:26:10.26#ibcon#read 5, iclass 22, count 0 2006.173.07:26:10.26#ibcon#about to read 6, iclass 22, count 0 2006.173.07:26:10.26#ibcon#read 6, iclass 22, count 0 2006.173.07:26:10.26#ibcon#end of sib2, iclass 22, count 0 2006.173.07:26:10.26#ibcon#*after write, iclass 22, count 0 2006.173.07:26:10.26#ibcon#*before return 0, iclass 22, count 0 2006.173.07:26:10.26#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.07:26:10.26#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.07:26:10.26#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.07:26:10.26#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.07:26:10.26$vck44/va=4,6 2006.173.07:26:10.26#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.07:26:10.26#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.07:26:10.26#ibcon#ireg 11 cls_cnt 2 2006.173.07:26:10.26#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.07:26:10.32#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.07:26:10.32#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.07:26:10.32#ibcon#enter wrdev, iclass 24, count 2 2006.173.07:26:10.32#ibcon#first serial, iclass 24, count 2 2006.173.07:26:10.32#ibcon#enter sib2, iclass 24, count 2 2006.173.07:26:10.32#ibcon#flushed, iclass 24, count 2 2006.173.07:26:10.32#ibcon#about to write, iclass 24, count 2 2006.173.07:26:10.32#ibcon#wrote, iclass 24, count 2 2006.173.07:26:10.32#ibcon#about to read 3, iclass 24, count 2 2006.173.07:26:10.34#ibcon#read 3, iclass 24, count 2 2006.173.07:26:10.34#ibcon#about to read 4, iclass 24, count 2 2006.173.07:26:10.34#ibcon#read 4, iclass 24, count 2 2006.173.07:26:10.34#ibcon#about to read 5, iclass 24, count 2 2006.173.07:26:10.34#ibcon#read 5, iclass 24, count 2 2006.173.07:26:10.34#ibcon#about to read 6, iclass 24, count 2 2006.173.07:26:10.34#ibcon#read 6, iclass 24, count 2 2006.173.07:26:10.34#ibcon#end of sib2, iclass 24, count 2 2006.173.07:26:10.34#ibcon#*mode == 0, iclass 24, count 2 2006.173.07:26:10.34#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.07:26:10.34#ibcon#[25=AT04-06\r\n] 2006.173.07:26:10.34#ibcon#*before write, iclass 24, count 2 2006.173.07:26:10.34#ibcon#enter sib2, iclass 24, count 2 2006.173.07:26:10.34#ibcon#flushed, iclass 24, count 2 2006.173.07:26:10.34#ibcon#about to write, iclass 24, count 2 2006.173.07:26:10.34#ibcon#wrote, iclass 24, count 2 2006.173.07:26:10.34#ibcon#about to read 3, iclass 24, count 2 2006.173.07:26:10.37#ibcon#read 3, iclass 24, count 2 2006.173.07:26:10.37#ibcon#about to read 4, iclass 24, count 2 2006.173.07:26:10.37#ibcon#read 4, iclass 24, count 2 2006.173.07:26:10.37#ibcon#about to read 5, iclass 24, count 2 2006.173.07:26:10.37#ibcon#read 5, iclass 24, count 2 2006.173.07:26:10.37#ibcon#about to read 6, iclass 24, count 2 2006.173.07:26:10.37#ibcon#read 6, iclass 24, count 2 2006.173.07:26:10.37#ibcon#end of sib2, iclass 24, count 2 2006.173.07:26:10.37#ibcon#*after write, iclass 24, count 2 2006.173.07:26:10.37#ibcon#*before return 0, iclass 24, count 2 2006.173.07:26:10.37#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.07:26:10.37#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.07:26:10.37#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.07:26:10.37#ibcon#ireg 7 cls_cnt 0 2006.173.07:26:10.37#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.07:26:10.49#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.07:26:10.49#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.07:26:10.49#ibcon#enter wrdev, iclass 24, count 0 2006.173.07:26:10.49#ibcon#first serial, iclass 24, count 0 2006.173.07:26:10.49#ibcon#enter sib2, iclass 24, count 0 2006.173.07:26:10.49#ibcon#flushed, iclass 24, count 0 2006.173.07:26:10.49#ibcon#about to write, iclass 24, count 0 2006.173.07:26:10.49#ibcon#wrote, iclass 24, count 0 2006.173.07:26:10.49#ibcon#about to read 3, iclass 24, count 0 2006.173.07:26:10.51#ibcon#read 3, iclass 24, count 0 2006.173.07:26:10.51#ibcon#about to read 4, iclass 24, count 0 2006.173.07:26:10.51#ibcon#read 4, iclass 24, count 0 2006.173.07:26:10.51#ibcon#about to read 5, iclass 24, count 0 2006.173.07:26:10.51#ibcon#read 5, iclass 24, count 0 2006.173.07:26:10.51#ibcon#about to read 6, iclass 24, count 0 2006.173.07:26:10.51#ibcon#read 6, iclass 24, count 0 2006.173.07:26:10.51#ibcon#end of sib2, iclass 24, count 0 2006.173.07:26:10.51#ibcon#*mode == 0, iclass 24, count 0 2006.173.07:26:10.51#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.07:26:10.51#ibcon#[25=USB\r\n] 2006.173.07:26:10.51#ibcon#*before write, iclass 24, count 0 2006.173.07:26:10.51#ibcon#enter sib2, iclass 24, count 0 2006.173.07:26:10.51#ibcon#flushed, iclass 24, count 0 2006.173.07:26:10.51#ibcon#about to write, iclass 24, count 0 2006.173.07:26:10.51#ibcon#wrote, iclass 24, count 0 2006.173.07:26:10.51#ibcon#about to read 3, iclass 24, count 0 2006.173.07:26:10.54#ibcon#read 3, iclass 24, count 0 2006.173.07:26:10.54#ibcon#about to read 4, iclass 24, count 0 2006.173.07:26:10.54#ibcon#read 4, iclass 24, count 0 2006.173.07:26:10.54#ibcon#about to read 5, iclass 24, count 0 2006.173.07:26:10.54#ibcon#read 5, iclass 24, count 0 2006.173.07:26:10.54#ibcon#about to read 6, iclass 24, count 0 2006.173.07:26:10.54#ibcon#read 6, iclass 24, count 0 2006.173.07:26:10.54#ibcon#end of sib2, iclass 24, count 0 2006.173.07:26:10.54#ibcon#*after write, iclass 24, count 0 2006.173.07:26:10.54#ibcon#*before return 0, iclass 24, count 0 2006.173.07:26:10.54#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.07:26:10.54#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.07:26:10.54#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.07:26:10.54#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.07:26:10.54$vck44/valo=5,734.99 2006.173.07:26:10.54#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.07:26:10.54#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.07:26:10.54#ibcon#ireg 17 cls_cnt 0 2006.173.07:26:10.54#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.07:26:10.54#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.07:26:10.54#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.07:26:10.54#ibcon#enter wrdev, iclass 26, count 0 2006.173.07:26:10.54#ibcon#first serial, iclass 26, count 0 2006.173.07:26:10.54#ibcon#enter sib2, iclass 26, count 0 2006.173.07:26:10.54#ibcon#flushed, iclass 26, count 0 2006.173.07:26:10.54#ibcon#about to write, iclass 26, count 0 2006.173.07:26:10.54#ibcon#wrote, iclass 26, count 0 2006.173.07:26:10.54#ibcon#about to read 3, iclass 26, count 0 2006.173.07:26:10.56#ibcon#read 3, iclass 26, count 0 2006.173.07:26:10.56#ibcon#about to read 4, iclass 26, count 0 2006.173.07:26:10.56#ibcon#read 4, iclass 26, count 0 2006.173.07:26:10.56#ibcon#about to read 5, iclass 26, count 0 2006.173.07:26:10.56#ibcon#read 5, iclass 26, count 0 2006.173.07:26:10.56#ibcon#about to read 6, iclass 26, count 0 2006.173.07:26:10.56#ibcon#read 6, iclass 26, count 0 2006.173.07:26:10.56#ibcon#end of sib2, iclass 26, count 0 2006.173.07:26:10.56#ibcon#*mode == 0, iclass 26, count 0 2006.173.07:26:10.56#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.07:26:10.56#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.07:26:10.56#ibcon#*before write, iclass 26, count 0 2006.173.07:26:10.56#ibcon#enter sib2, iclass 26, count 0 2006.173.07:26:10.56#ibcon#flushed, iclass 26, count 0 2006.173.07:26:10.56#ibcon#about to write, iclass 26, count 0 2006.173.07:26:10.56#ibcon#wrote, iclass 26, count 0 2006.173.07:26:10.56#ibcon#about to read 3, iclass 26, count 0 2006.173.07:26:10.60#ibcon#read 3, iclass 26, count 0 2006.173.07:26:10.60#ibcon#about to read 4, iclass 26, count 0 2006.173.07:26:10.60#ibcon#read 4, iclass 26, count 0 2006.173.07:26:10.60#ibcon#about to read 5, iclass 26, count 0 2006.173.07:26:10.60#ibcon#read 5, iclass 26, count 0 2006.173.07:26:10.60#ibcon#about to read 6, iclass 26, count 0 2006.173.07:26:10.60#ibcon#read 6, iclass 26, count 0 2006.173.07:26:10.60#ibcon#end of sib2, iclass 26, count 0 2006.173.07:26:10.60#ibcon#*after write, iclass 26, count 0 2006.173.07:26:10.60#ibcon#*before return 0, iclass 26, count 0 2006.173.07:26:10.60#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.07:26:10.60#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.07:26:10.60#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.07:26:10.60#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.07:26:10.60$vck44/va=5,4 2006.173.07:26:10.60#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.07:26:10.60#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.07:26:10.60#ibcon#ireg 11 cls_cnt 2 2006.173.07:26:10.60#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.07:26:10.66#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.07:26:10.66#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.07:26:10.66#ibcon#enter wrdev, iclass 28, count 2 2006.173.07:26:10.66#ibcon#first serial, iclass 28, count 2 2006.173.07:26:10.66#ibcon#enter sib2, iclass 28, count 2 2006.173.07:26:10.66#ibcon#flushed, iclass 28, count 2 2006.173.07:26:10.66#ibcon#about to write, iclass 28, count 2 2006.173.07:26:10.66#ibcon#wrote, iclass 28, count 2 2006.173.07:26:10.66#ibcon#about to read 3, iclass 28, count 2 2006.173.07:26:10.68#ibcon#read 3, iclass 28, count 2 2006.173.07:26:10.68#ibcon#about to read 4, iclass 28, count 2 2006.173.07:26:10.68#ibcon#read 4, iclass 28, count 2 2006.173.07:26:10.68#ibcon#about to read 5, iclass 28, count 2 2006.173.07:26:10.68#ibcon#read 5, iclass 28, count 2 2006.173.07:26:10.68#ibcon#about to read 6, iclass 28, count 2 2006.173.07:26:10.68#ibcon#read 6, iclass 28, count 2 2006.173.07:26:10.68#ibcon#end of sib2, iclass 28, count 2 2006.173.07:26:10.68#ibcon#*mode == 0, iclass 28, count 2 2006.173.07:26:10.68#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.07:26:10.68#ibcon#[25=AT05-04\r\n] 2006.173.07:26:10.68#ibcon#*before write, iclass 28, count 2 2006.173.07:26:10.68#ibcon#enter sib2, iclass 28, count 2 2006.173.07:26:10.68#ibcon#flushed, iclass 28, count 2 2006.173.07:26:10.68#ibcon#about to write, iclass 28, count 2 2006.173.07:26:10.68#ibcon#wrote, iclass 28, count 2 2006.173.07:26:10.68#ibcon#about to read 3, iclass 28, count 2 2006.173.07:26:10.71#ibcon#read 3, iclass 28, count 2 2006.173.07:26:10.71#ibcon#about to read 4, iclass 28, count 2 2006.173.07:26:10.71#ibcon#read 4, iclass 28, count 2 2006.173.07:26:10.71#ibcon#about to read 5, iclass 28, count 2 2006.173.07:26:10.71#ibcon#read 5, iclass 28, count 2 2006.173.07:26:10.71#ibcon#about to read 6, iclass 28, count 2 2006.173.07:26:10.71#ibcon#read 6, iclass 28, count 2 2006.173.07:26:10.71#ibcon#end of sib2, iclass 28, count 2 2006.173.07:26:10.71#ibcon#*after write, iclass 28, count 2 2006.173.07:26:10.71#ibcon#*before return 0, iclass 28, count 2 2006.173.07:26:10.71#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.07:26:10.71#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.07:26:10.71#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.07:26:10.71#ibcon#ireg 7 cls_cnt 0 2006.173.07:26:10.71#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.07:26:10.83#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.07:26:10.83#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.07:26:10.83#ibcon#enter wrdev, iclass 28, count 0 2006.173.07:26:10.83#ibcon#first serial, iclass 28, count 0 2006.173.07:26:10.83#ibcon#enter sib2, iclass 28, count 0 2006.173.07:26:10.83#ibcon#flushed, iclass 28, count 0 2006.173.07:26:10.83#ibcon#about to write, iclass 28, count 0 2006.173.07:26:10.83#ibcon#wrote, iclass 28, count 0 2006.173.07:26:10.83#ibcon#about to read 3, iclass 28, count 0 2006.173.07:26:10.85#ibcon#read 3, iclass 28, count 0 2006.173.07:26:10.85#ibcon#about to read 4, iclass 28, count 0 2006.173.07:26:10.85#ibcon#read 4, iclass 28, count 0 2006.173.07:26:10.85#ibcon#about to read 5, iclass 28, count 0 2006.173.07:26:10.85#ibcon#read 5, iclass 28, count 0 2006.173.07:26:10.85#ibcon#about to read 6, iclass 28, count 0 2006.173.07:26:10.85#ibcon#read 6, iclass 28, count 0 2006.173.07:26:10.85#ibcon#end of sib2, iclass 28, count 0 2006.173.07:26:10.85#ibcon#*mode == 0, iclass 28, count 0 2006.173.07:26:10.85#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.07:26:10.85#ibcon#[25=USB\r\n] 2006.173.07:26:10.85#ibcon#*before write, iclass 28, count 0 2006.173.07:26:10.85#ibcon#enter sib2, iclass 28, count 0 2006.173.07:26:10.85#ibcon#flushed, iclass 28, count 0 2006.173.07:26:10.85#ibcon#about to write, iclass 28, count 0 2006.173.07:26:10.85#ibcon#wrote, iclass 28, count 0 2006.173.07:26:10.85#ibcon#about to read 3, iclass 28, count 0 2006.173.07:26:10.88#ibcon#read 3, iclass 28, count 0 2006.173.07:26:10.88#ibcon#about to read 4, iclass 28, count 0 2006.173.07:26:10.88#ibcon#read 4, iclass 28, count 0 2006.173.07:26:10.88#ibcon#about to read 5, iclass 28, count 0 2006.173.07:26:10.88#ibcon#read 5, iclass 28, count 0 2006.173.07:26:10.88#ibcon#about to read 6, iclass 28, count 0 2006.173.07:26:10.88#ibcon#read 6, iclass 28, count 0 2006.173.07:26:10.88#ibcon#end of sib2, iclass 28, count 0 2006.173.07:26:10.88#ibcon#*after write, iclass 28, count 0 2006.173.07:26:10.88#ibcon#*before return 0, iclass 28, count 0 2006.173.07:26:10.88#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.07:26:10.88#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.07:26:10.88#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.07:26:10.88#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.07:26:10.88$vck44/valo=6,814.99 2006.173.07:26:10.88#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.07:26:10.88#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.07:26:10.88#ibcon#ireg 17 cls_cnt 0 2006.173.07:26:10.88#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.07:26:10.88#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.07:26:10.88#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.07:26:10.88#ibcon#enter wrdev, iclass 30, count 0 2006.173.07:26:10.88#ibcon#first serial, iclass 30, count 0 2006.173.07:26:10.88#ibcon#enter sib2, iclass 30, count 0 2006.173.07:26:10.88#ibcon#flushed, iclass 30, count 0 2006.173.07:26:10.88#ibcon#about to write, iclass 30, count 0 2006.173.07:26:10.88#ibcon#wrote, iclass 30, count 0 2006.173.07:26:10.88#ibcon#about to read 3, iclass 30, count 0 2006.173.07:26:10.90#ibcon#read 3, iclass 30, count 0 2006.173.07:26:10.90#ibcon#about to read 4, iclass 30, count 0 2006.173.07:26:10.90#ibcon#read 4, iclass 30, count 0 2006.173.07:26:10.90#ibcon#about to read 5, iclass 30, count 0 2006.173.07:26:10.90#ibcon#read 5, iclass 30, count 0 2006.173.07:26:10.90#ibcon#about to read 6, iclass 30, count 0 2006.173.07:26:10.90#ibcon#read 6, iclass 30, count 0 2006.173.07:26:10.90#ibcon#end of sib2, iclass 30, count 0 2006.173.07:26:10.90#ibcon#*mode == 0, iclass 30, count 0 2006.173.07:26:10.90#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.07:26:10.90#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.07:26:10.90#ibcon#*before write, iclass 30, count 0 2006.173.07:26:10.90#ibcon#enter sib2, iclass 30, count 0 2006.173.07:26:10.90#ibcon#flushed, iclass 30, count 0 2006.173.07:26:10.90#ibcon#about to write, iclass 30, count 0 2006.173.07:26:10.90#ibcon#wrote, iclass 30, count 0 2006.173.07:26:10.90#ibcon#about to read 3, iclass 30, count 0 2006.173.07:26:10.94#ibcon#read 3, iclass 30, count 0 2006.173.07:26:10.94#ibcon#about to read 4, iclass 30, count 0 2006.173.07:26:10.94#ibcon#read 4, iclass 30, count 0 2006.173.07:26:10.94#ibcon#about to read 5, iclass 30, count 0 2006.173.07:26:10.94#ibcon#read 5, iclass 30, count 0 2006.173.07:26:10.94#ibcon#about to read 6, iclass 30, count 0 2006.173.07:26:10.94#ibcon#read 6, iclass 30, count 0 2006.173.07:26:10.94#ibcon#end of sib2, iclass 30, count 0 2006.173.07:26:10.94#ibcon#*after write, iclass 30, count 0 2006.173.07:26:10.94#ibcon#*before return 0, iclass 30, count 0 2006.173.07:26:10.94#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.07:26:10.94#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.07:26:10.94#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.07:26:10.94#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.07:26:10.94$vck44/va=6,3 2006.173.07:26:10.94#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.173.07:26:10.94#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.173.07:26:10.94#ibcon#ireg 11 cls_cnt 2 2006.173.07:26:10.94#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.07:26:11.00#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.07:26:11.00#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.07:26:11.00#ibcon#enter wrdev, iclass 32, count 2 2006.173.07:26:11.00#ibcon#first serial, iclass 32, count 2 2006.173.07:26:11.00#ibcon#enter sib2, iclass 32, count 2 2006.173.07:26:11.00#ibcon#flushed, iclass 32, count 2 2006.173.07:26:11.00#ibcon#about to write, iclass 32, count 2 2006.173.07:26:11.00#ibcon#wrote, iclass 32, count 2 2006.173.07:26:11.00#ibcon#about to read 3, iclass 32, count 2 2006.173.07:26:11.02#ibcon#read 3, iclass 32, count 2 2006.173.07:26:11.02#ibcon#about to read 4, iclass 32, count 2 2006.173.07:26:11.02#ibcon#read 4, iclass 32, count 2 2006.173.07:26:11.02#ibcon#about to read 5, iclass 32, count 2 2006.173.07:26:11.02#ibcon#read 5, iclass 32, count 2 2006.173.07:26:11.02#ibcon#about to read 6, iclass 32, count 2 2006.173.07:26:11.02#ibcon#read 6, iclass 32, count 2 2006.173.07:26:11.02#ibcon#end of sib2, iclass 32, count 2 2006.173.07:26:11.02#ibcon#*mode == 0, iclass 32, count 2 2006.173.07:26:11.02#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.173.07:26:11.02#ibcon#[25=AT06-03\r\n] 2006.173.07:26:11.02#ibcon#*before write, iclass 32, count 2 2006.173.07:26:11.02#ibcon#enter sib2, iclass 32, count 2 2006.173.07:26:11.02#ibcon#flushed, iclass 32, count 2 2006.173.07:26:11.02#ibcon#about to write, iclass 32, count 2 2006.173.07:26:11.02#ibcon#wrote, iclass 32, count 2 2006.173.07:26:11.02#ibcon#about to read 3, iclass 32, count 2 2006.173.07:26:11.05#abcon#<5=/02 0.3 0.6 23.76 831004.5\r\n> 2006.173.07:26:11.05#ibcon#read 3, iclass 32, count 2 2006.173.07:26:11.05#ibcon#about to read 4, iclass 32, count 2 2006.173.07:26:11.05#ibcon#read 4, iclass 32, count 2 2006.173.07:26:11.05#ibcon#about to read 5, iclass 32, count 2 2006.173.07:26:11.05#ibcon#read 5, iclass 32, count 2 2006.173.07:26:11.05#ibcon#about to read 6, iclass 32, count 2 2006.173.07:26:11.05#ibcon#read 6, iclass 32, count 2 2006.173.07:26:11.05#ibcon#end of sib2, iclass 32, count 2 2006.173.07:26:11.05#ibcon#*after write, iclass 32, count 2 2006.173.07:26:11.05#ibcon#*before return 0, iclass 32, count 2 2006.173.07:26:11.05#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.07:26:11.05#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.173.07:26:11.05#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.173.07:26:11.05#ibcon#ireg 7 cls_cnt 0 2006.173.07:26:11.05#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.07:26:11.07#abcon#{5=INTERFACE CLEAR} 2006.173.07:26:11.13#abcon#[5=S1D000X0/0*\r\n] 2006.173.07:26:11.17#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.07:26:11.17#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.07:26:11.17#ibcon#enter wrdev, iclass 32, count 0 2006.173.07:26:11.17#ibcon#first serial, iclass 32, count 0 2006.173.07:26:11.17#ibcon#enter sib2, iclass 32, count 0 2006.173.07:26:11.17#ibcon#flushed, iclass 32, count 0 2006.173.07:26:11.17#ibcon#about to write, iclass 32, count 0 2006.173.07:26:11.17#ibcon#wrote, iclass 32, count 0 2006.173.07:26:11.17#ibcon#about to read 3, iclass 32, count 0 2006.173.07:26:11.19#ibcon#read 3, iclass 32, count 0 2006.173.07:26:11.19#ibcon#about to read 4, iclass 32, count 0 2006.173.07:26:11.19#ibcon#read 4, iclass 32, count 0 2006.173.07:26:11.19#ibcon#about to read 5, iclass 32, count 0 2006.173.07:26:11.19#ibcon#read 5, iclass 32, count 0 2006.173.07:26:11.19#ibcon#about to read 6, iclass 32, count 0 2006.173.07:26:11.19#ibcon#read 6, iclass 32, count 0 2006.173.07:26:11.19#ibcon#end of sib2, iclass 32, count 0 2006.173.07:26:11.19#ibcon#*mode == 0, iclass 32, count 0 2006.173.07:26:11.19#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.07:26:11.19#ibcon#[25=USB\r\n] 2006.173.07:26:11.19#ibcon#*before write, iclass 32, count 0 2006.173.07:26:11.19#ibcon#enter sib2, iclass 32, count 0 2006.173.07:26:11.19#ibcon#flushed, iclass 32, count 0 2006.173.07:26:11.19#ibcon#about to write, iclass 32, count 0 2006.173.07:26:11.19#ibcon#wrote, iclass 32, count 0 2006.173.07:26:11.19#ibcon#about to read 3, iclass 32, count 0 2006.173.07:26:11.22#ibcon#read 3, iclass 32, count 0 2006.173.07:26:11.22#ibcon#about to read 4, iclass 32, count 0 2006.173.07:26:11.22#ibcon#read 4, iclass 32, count 0 2006.173.07:26:11.22#ibcon#about to read 5, iclass 32, count 0 2006.173.07:26:11.22#ibcon#read 5, iclass 32, count 0 2006.173.07:26:11.22#ibcon#about to read 6, iclass 32, count 0 2006.173.07:26:11.22#ibcon#read 6, iclass 32, count 0 2006.173.07:26:11.22#ibcon#end of sib2, iclass 32, count 0 2006.173.07:26:11.22#ibcon#*after write, iclass 32, count 0 2006.173.07:26:11.22#ibcon#*before return 0, iclass 32, count 0 2006.173.07:26:11.22#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.07:26:11.22#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.173.07:26:11.22#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.07:26:11.22#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.07:26:11.22$vck44/valo=7,864.99 2006.173.07:26:11.22#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.07:26:11.22#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.07:26:11.22#ibcon#ireg 17 cls_cnt 0 2006.173.07:26:11.22#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.07:26:11.22#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.07:26:11.22#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.07:26:11.22#ibcon#enter wrdev, iclass 38, count 0 2006.173.07:26:11.22#ibcon#first serial, iclass 38, count 0 2006.173.07:26:11.22#ibcon#enter sib2, iclass 38, count 0 2006.173.07:26:11.22#ibcon#flushed, iclass 38, count 0 2006.173.07:26:11.22#ibcon#about to write, iclass 38, count 0 2006.173.07:26:11.22#ibcon#wrote, iclass 38, count 0 2006.173.07:26:11.22#ibcon#about to read 3, iclass 38, count 0 2006.173.07:26:11.24#ibcon#read 3, iclass 38, count 0 2006.173.07:26:11.24#ibcon#about to read 4, iclass 38, count 0 2006.173.07:26:11.24#ibcon#read 4, iclass 38, count 0 2006.173.07:26:11.24#ibcon#about to read 5, iclass 38, count 0 2006.173.07:26:11.24#ibcon#read 5, iclass 38, count 0 2006.173.07:26:11.24#ibcon#about to read 6, iclass 38, count 0 2006.173.07:26:11.24#ibcon#read 6, iclass 38, count 0 2006.173.07:26:11.24#ibcon#end of sib2, iclass 38, count 0 2006.173.07:26:11.24#ibcon#*mode == 0, iclass 38, count 0 2006.173.07:26:11.24#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.07:26:11.24#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.07:26:11.24#ibcon#*before write, iclass 38, count 0 2006.173.07:26:11.24#ibcon#enter sib2, iclass 38, count 0 2006.173.07:26:11.24#ibcon#flushed, iclass 38, count 0 2006.173.07:26:11.24#ibcon#about to write, iclass 38, count 0 2006.173.07:26:11.24#ibcon#wrote, iclass 38, count 0 2006.173.07:26:11.24#ibcon#about to read 3, iclass 38, count 0 2006.173.07:26:11.28#ibcon#read 3, iclass 38, count 0 2006.173.07:26:11.28#ibcon#about to read 4, iclass 38, count 0 2006.173.07:26:11.28#ibcon#read 4, iclass 38, count 0 2006.173.07:26:11.28#ibcon#about to read 5, iclass 38, count 0 2006.173.07:26:11.28#ibcon#read 5, iclass 38, count 0 2006.173.07:26:11.28#ibcon#about to read 6, iclass 38, count 0 2006.173.07:26:11.28#ibcon#read 6, iclass 38, count 0 2006.173.07:26:11.28#ibcon#end of sib2, iclass 38, count 0 2006.173.07:26:11.28#ibcon#*after write, iclass 38, count 0 2006.173.07:26:11.28#ibcon#*before return 0, iclass 38, count 0 2006.173.07:26:11.28#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.07:26:11.28#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.07:26:11.28#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.07:26:11.28#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.07:26:11.28$vck44/va=7,4 2006.173.07:26:11.28#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.07:26:11.28#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.07:26:11.28#ibcon#ireg 11 cls_cnt 2 2006.173.07:26:11.28#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.07:26:11.34#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.07:26:11.34#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.07:26:11.34#ibcon#enter wrdev, iclass 40, count 2 2006.173.07:26:11.34#ibcon#first serial, iclass 40, count 2 2006.173.07:26:11.34#ibcon#enter sib2, iclass 40, count 2 2006.173.07:26:11.34#ibcon#flushed, iclass 40, count 2 2006.173.07:26:11.34#ibcon#about to write, iclass 40, count 2 2006.173.07:26:11.34#ibcon#wrote, iclass 40, count 2 2006.173.07:26:11.34#ibcon#about to read 3, iclass 40, count 2 2006.173.07:26:11.36#ibcon#read 3, iclass 40, count 2 2006.173.07:26:11.36#ibcon#about to read 4, iclass 40, count 2 2006.173.07:26:11.36#ibcon#read 4, iclass 40, count 2 2006.173.07:26:11.36#ibcon#about to read 5, iclass 40, count 2 2006.173.07:26:11.36#ibcon#read 5, iclass 40, count 2 2006.173.07:26:11.36#ibcon#about to read 6, iclass 40, count 2 2006.173.07:26:11.36#ibcon#read 6, iclass 40, count 2 2006.173.07:26:11.36#ibcon#end of sib2, iclass 40, count 2 2006.173.07:26:11.36#ibcon#*mode == 0, iclass 40, count 2 2006.173.07:26:11.36#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.07:26:11.36#ibcon#[25=AT07-04\r\n] 2006.173.07:26:11.36#ibcon#*before write, iclass 40, count 2 2006.173.07:26:11.36#ibcon#enter sib2, iclass 40, count 2 2006.173.07:26:11.36#ibcon#flushed, iclass 40, count 2 2006.173.07:26:11.36#ibcon#about to write, iclass 40, count 2 2006.173.07:26:11.36#ibcon#wrote, iclass 40, count 2 2006.173.07:26:11.36#ibcon#about to read 3, iclass 40, count 2 2006.173.07:26:11.39#ibcon#read 3, iclass 40, count 2 2006.173.07:26:11.39#ibcon#about to read 4, iclass 40, count 2 2006.173.07:26:11.39#ibcon#read 4, iclass 40, count 2 2006.173.07:26:11.39#ibcon#about to read 5, iclass 40, count 2 2006.173.07:26:11.39#ibcon#read 5, iclass 40, count 2 2006.173.07:26:11.39#ibcon#about to read 6, iclass 40, count 2 2006.173.07:26:11.39#ibcon#read 6, iclass 40, count 2 2006.173.07:26:11.39#ibcon#end of sib2, iclass 40, count 2 2006.173.07:26:11.39#ibcon#*after write, iclass 40, count 2 2006.173.07:26:11.39#ibcon#*before return 0, iclass 40, count 2 2006.173.07:26:11.39#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.07:26:11.39#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.07:26:11.39#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.07:26:11.39#ibcon#ireg 7 cls_cnt 0 2006.173.07:26:11.39#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.07:26:11.51#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.07:26:11.51#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.07:26:11.51#ibcon#enter wrdev, iclass 40, count 0 2006.173.07:26:11.51#ibcon#first serial, iclass 40, count 0 2006.173.07:26:11.51#ibcon#enter sib2, iclass 40, count 0 2006.173.07:26:11.51#ibcon#flushed, iclass 40, count 0 2006.173.07:26:11.51#ibcon#about to write, iclass 40, count 0 2006.173.07:26:11.51#ibcon#wrote, iclass 40, count 0 2006.173.07:26:11.51#ibcon#about to read 3, iclass 40, count 0 2006.173.07:26:11.53#ibcon#read 3, iclass 40, count 0 2006.173.07:26:11.53#ibcon#about to read 4, iclass 40, count 0 2006.173.07:26:11.53#ibcon#read 4, iclass 40, count 0 2006.173.07:26:11.53#ibcon#about to read 5, iclass 40, count 0 2006.173.07:26:11.53#ibcon#read 5, iclass 40, count 0 2006.173.07:26:11.53#ibcon#about to read 6, iclass 40, count 0 2006.173.07:26:11.53#ibcon#read 6, iclass 40, count 0 2006.173.07:26:11.53#ibcon#end of sib2, iclass 40, count 0 2006.173.07:26:11.53#ibcon#*mode == 0, iclass 40, count 0 2006.173.07:26:11.53#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.07:26:11.53#ibcon#[25=USB\r\n] 2006.173.07:26:11.53#ibcon#*before write, iclass 40, count 0 2006.173.07:26:11.53#ibcon#enter sib2, iclass 40, count 0 2006.173.07:26:11.53#ibcon#flushed, iclass 40, count 0 2006.173.07:26:11.53#ibcon#about to write, iclass 40, count 0 2006.173.07:26:11.53#ibcon#wrote, iclass 40, count 0 2006.173.07:26:11.53#ibcon#about to read 3, iclass 40, count 0 2006.173.07:26:11.56#ibcon#read 3, iclass 40, count 0 2006.173.07:26:11.56#ibcon#about to read 4, iclass 40, count 0 2006.173.07:26:11.56#ibcon#read 4, iclass 40, count 0 2006.173.07:26:11.56#ibcon#about to read 5, iclass 40, count 0 2006.173.07:26:11.56#ibcon#read 5, iclass 40, count 0 2006.173.07:26:11.56#ibcon#about to read 6, iclass 40, count 0 2006.173.07:26:11.56#ibcon#read 6, iclass 40, count 0 2006.173.07:26:11.56#ibcon#end of sib2, iclass 40, count 0 2006.173.07:26:11.56#ibcon#*after write, iclass 40, count 0 2006.173.07:26:11.56#ibcon#*before return 0, iclass 40, count 0 2006.173.07:26:11.56#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.07:26:11.56#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.07:26:11.56#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.07:26:11.56#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.07:26:11.56$vck44/valo=8,884.99 2006.173.07:26:11.56#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.07:26:11.56#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.07:26:11.56#ibcon#ireg 17 cls_cnt 0 2006.173.07:26:11.56#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.07:26:11.56#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.07:26:11.56#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.07:26:11.56#ibcon#enter wrdev, iclass 4, count 0 2006.173.07:26:11.56#ibcon#first serial, iclass 4, count 0 2006.173.07:26:11.56#ibcon#enter sib2, iclass 4, count 0 2006.173.07:26:11.56#ibcon#flushed, iclass 4, count 0 2006.173.07:26:11.56#ibcon#about to write, iclass 4, count 0 2006.173.07:26:11.56#ibcon#wrote, iclass 4, count 0 2006.173.07:26:11.56#ibcon#about to read 3, iclass 4, count 0 2006.173.07:26:11.58#ibcon#read 3, iclass 4, count 0 2006.173.07:26:11.58#ibcon#about to read 4, iclass 4, count 0 2006.173.07:26:11.58#ibcon#read 4, iclass 4, count 0 2006.173.07:26:11.58#ibcon#about to read 5, iclass 4, count 0 2006.173.07:26:11.58#ibcon#read 5, iclass 4, count 0 2006.173.07:26:11.58#ibcon#about to read 6, iclass 4, count 0 2006.173.07:26:11.58#ibcon#read 6, iclass 4, count 0 2006.173.07:26:11.58#ibcon#end of sib2, iclass 4, count 0 2006.173.07:26:11.58#ibcon#*mode == 0, iclass 4, count 0 2006.173.07:26:11.58#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.07:26:11.58#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.07:26:11.58#ibcon#*before write, iclass 4, count 0 2006.173.07:26:11.58#ibcon#enter sib2, iclass 4, count 0 2006.173.07:26:11.58#ibcon#flushed, iclass 4, count 0 2006.173.07:26:11.58#ibcon#about to write, iclass 4, count 0 2006.173.07:26:11.58#ibcon#wrote, iclass 4, count 0 2006.173.07:26:11.58#ibcon#about to read 3, iclass 4, count 0 2006.173.07:26:11.62#ibcon#read 3, iclass 4, count 0 2006.173.07:26:11.62#ibcon#about to read 4, iclass 4, count 0 2006.173.07:26:11.62#ibcon#read 4, iclass 4, count 0 2006.173.07:26:11.62#ibcon#about to read 5, iclass 4, count 0 2006.173.07:26:11.62#ibcon#read 5, iclass 4, count 0 2006.173.07:26:11.62#ibcon#about to read 6, iclass 4, count 0 2006.173.07:26:11.62#ibcon#read 6, iclass 4, count 0 2006.173.07:26:11.62#ibcon#end of sib2, iclass 4, count 0 2006.173.07:26:11.62#ibcon#*after write, iclass 4, count 0 2006.173.07:26:11.62#ibcon#*before return 0, iclass 4, count 0 2006.173.07:26:11.62#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.07:26:11.62#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.07:26:11.62#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.07:26:11.62#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.07:26:11.62$vck44/va=8,4 2006.173.07:26:11.62#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.07:26:11.62#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.07:26:11.62#ibcon#ireg 11 cls_cnt 2 2006.173.07:26:11.62#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.07:26:11.68#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.07:26:11.68#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.07:26:11.68#ibcon#enter wrdev, iclass 6, count 2 2006.173.07:26:11.68#ibcon#first serial, iclass 6, count 2 2006.173.07:26:11.68#ibcon#enter sib2, iclass 6, count 2 2006.173.07:26:11.68#ibcon#flushed, iclass 6, count 2 2006.173.07:26:11.68#ibcon#about to write, iclass 6, count 2 2006.173.07:26:11.68#ibcon#wrote, iclass 6, count 2 2006.173.07:26:11.68#ibcon#about to read 3, iclass 6, count 2 2006.173.07:26:11.70#ibcon#read 3, iclass 6, count 2 2006.173.07:26:11.70#ibcon#about to read 4, iclass 6, count 2 2006.173.07:26:11.70#ibcon#read 4, iclass 6, count 2 2006.173.07:26:11.70#ibcon#about to read 5, iclass 6, count 2 2006.173.07:26:11.70#ibcon#read 5, iclass 6, count 2 2006.173.07:26:11.70#ibcon#about to read 6, iclass 6, count 2 2006.173.07:26:11.70#ibcon#read 6, iclass 6, count 2 2006.173.07:26:11.70#ibcon#end of sib2, iclass 6, count 2 2006.173.07:26:11.70#ibcon#*mode == 0, iclass 6, count 2 2006.173.07:26:11.70#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.07:26:11.70#ibcon#[25=AT08-04\r\n] 2006.173.07:26:11.70#ibcon#*before write, iclass 6, count 2 2006.173.07:26:11.70#ibcon#enter sib2, iclass 6, count 2 2006.173.07:26:11.70#ibcon#flushed, iclass 6, count 2 2006.173.07:26:11.70#ibcon#about to write, iclass 6, count 2 2006.173.07:26:11.70#ibcon#wrote, iclass 6, count 2 2006.173.07:26:11.70#ibcon#about to read 3, iclass 6, count 2 2006.173.07:26:11.73#ibcon#read 3, iclass 6, count 2 2006.173.07:26:11.73#ibcon#about to read 4, iclass 6, count 2 2006.173.07:26:11.73#ibcon#read 4, iclass 6, count 2 2006.173.07:26:11.73#ibcon#about to read 5, iclass 6, count 2 2006.173.07:26:11.73#ibcon#read 5, iclass 6, count 2 2006.173.07:26:11.73#ibcon#about to read 6, iclass 6, count 2 2006.173.07:26:11.73#ibcon#read 6, iclass 6, count 2 2006.173.07:26:11.73#ibcon#end of sib2, iclass 6, count 2 2006.173.07:26:11.73#ibcon#*after write, iclass 6, count 2 2006.173.07:26:11.73#ibcon#*before return 0, iclass 6, count 2 2006.173.07:26:11.73#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.07:26:11.73#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.07:26:11.73#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.07:26:11.73#ibcon#ireg 7 cls_cnt 0 2006.173.07:26:11.73#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.07:26:11.85#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.07:26:11.85#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.07:26:11.85#ibcon#enter wrdev, iclass 6, count 0 2006.173.07:26:11.85#ibcon#first serial, iclass 6, count 0 2006.173.07:26:11.85#ibcon#enter sib2, iclass 6, count 0 2006.173.07:26:11.85#ibcon#flushed, iclass 6, count 0 2006.173.07:26:11.85#ibcon#about to write, iclass 6, count 0 2006.173.07:26:11.85#ibcon#wrote, iclass 6, count 0 2006.173.07:26:11.85#ibcon#about to read 3, iclass 6, count 0 2006.173.07:26:11.87#ibcon#read 3, iclass 6, count 0 2006.173.07:26:11.87#ibcon#about to read 4, iclass 6, count 0 2006.173.07:26:11.87#ibcon#read 4, iclass 6, count 0 2006.173.07:26:11.87#ibcon#about to read 5, iclass 6, count 0 2006.173.07:26:11.87#ibcon#read 5, iclass 6, count 0 2006.173.07:26:11.87#ibcon#about to read 6, iclass 6, count 0 2006.173.07:26:11.87#ibcon#read 6, iclass 6, count 0 2006.173.07:26:11.87#ibcon#end of sib2, iclass 6, count 0 2006.173.07:26:11.87#ibcon#*mode == 0, iclass 6, count 0 2006.173.07:26:11.87#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.07:26:11.87#ibcon#[25=USB\r\n] 2006.173.07:26:11.87#ibcon#*before write, iclass 6, count 0 2006.173.07:26:11.87#ibcon#enter sib2, iclass 6, count 0 2006.173.07:26:11.87#ibcon#flushed, iclass 6, count 0 2006.173.07:26:11.87#ibcon#about to write, iclass 6, count 0 2006.173.07:26:11.87#ibcon#wrote, iclass 6, count 0 2006.173.07:26:11.87#ibcon#about to read 3, iclass 6, count 0 2006.173.07:26:11.90#ibcon#read 3, iclass 6, count 0 2006.173.07:26:11.90#ibcon#about to read 4, iclass 6, count 0 2006.173.07:26:11.90#ibcon#read 4, iclass 6, count 0 2006.173.07:26:11.90#ibcon#about to read 5, iclass 6, count 0 2006.173.07:26:11.90#ibcon#read 5, iclass 6, count 0 2006.173.07:26:11.90#ibcon#about to read 6, iclass 6, count 0 2006.173.07:26:11.90#ibcon#read 6, iclass 6, count 0 2006.173.07:26:11.90#ibcon#end of sib2, iclass 6, count 0 2006.173.07:26:11.90#ibcon#*after write, iclass 6, count 0 2006.173.07:26:11.90#ibcon#*before return 0, iclass 6, count 0 2006.173.07:26:11.90#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.07:26:11.90#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.07:26:11.90#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.07:26:11.90#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.07:26:11.90$vck44/vblo=1,629.99 2006.173.07:26:11.90#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.07:26:11.90#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.07:26:11.90#ibcon#ireg 17 cls_cnt 0 2006.173.07:26:11.90#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.07:26:11.90#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.07:26:11.90#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.07:26:11.90#ibcon#enter wrdev, iclass 10, count 0 2006.173.07:26:11.90#ibcon#first serial, iclass 10, count 0 2006.173.07:26:11.90#ibcon#enter sib2, iclass 10, count 0 2006.173.07:26:11.90#ibcon#flushed, iclass 10, count 0 2006.173.07:26:11.90#ibcon#about to write, iclass 10, count 0 2006.173.07:26:11.90#ibcon#wrote, iclass 10, count 0 2006.173.07:26:11.90#ibcon#about to read 3, iclass 10, count 0 2006.173.07:26:11.92#ibcon#read 3, iclass 10, count 0 2006.173.07:26:11.92#ibcon#about to read 4, iclass 10, count 0 2006.173.07:26:11.92#ibcon#read 4, iclass 10, count 0 2006.173.07:26:11.92#ibcon#about to read 5, iclass 10, count 0 2006.173.07:26:11.92#ibcon#read 5, iclass 10, count 0 2006.173.07:26:11.92#ibcon#about to read 6, iclass 10, count 0 2006.173.07:26:11.92#ibcon#read 6, iclass 10, count 0 2006.173.07:26:11.92#ibcon#end of sib2, iclass 10, count 0 2006.173.07:26:11.92#ibcon#*mode == 0, iclass 10, count 0 2006.173.07:26:11.92#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.07:26:11.92#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.07:26:11.92#ibcon#*before write, iclass 10, count 0 2006.173.07:26:11.92#ibcon#enter sib2, iclass 10, count 0 2006.173.07:26:11.92#ibcon#flushed, iclass 10, count 0 2006.173.07:26:11.92#ibcon#about to write, iclass 10, count 0 2006.173.07:26:11.92#ibcon#wrote, iclass 10, count 0 2006.173.07:26:11.92#ibcon#about to read 3, iclass 10, count 0 2006.173.07:26:11.96#ibcon#read 3, iclass 10, count 0 2006.173.07:26:11.96#ibcon#about to read 4, iclass 10, count 0 2006.173.07:26:11.96#ibcon#read 4, iclass 10, count 0 2006.173.07:26:11.96#ibcon#about to read 5, iclass 10, count 0 2006.173.07:26:11.96#ibcon#read 5, iclass 10, count 0 2006.173.07:26:11.96#ibcon#about to read 6, iclass 10, count 0 2006.173.07:26:11.96#ibcon#read 6, iclass 10, count 0 2006.173.07:26:11.96#ibcon#end of sib2, iclass 10, count 0 2006.173.07:26:11.96#ibcon#*after write, iclass 10, count 0 2006.173.07:26:11.96#ibcon#*before return 0, iclass 10, count 0 2006.173.07:26:11.96#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.07:26:11.96#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.07:26:11.96#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.07:26:11.96#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.07:26:11.96$vck44/vb=1,4 2006.173.07:26:11.96#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.07:26:11.96#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.07:26:11.96#ibcon#ireg 11 cls_cnt 2 2006.173.07:26:11.96#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.07:26:11.96#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.07:26:11.96#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.07:26:11.96#ibcon#enter wrdev, iclass 12, count 2 2006.173.07:26:11.96#ibcon#first serial, iclass 12, count 2 2006.173.07:26:11.96#ibcon#enter sib2, iclass 12, count 2 2006.173.07:26:11.96#ibcon#flushed, iclass 12, count 2 2006.173.07:26:11.96#ibcon#about to write, iclass 12, count 2 2006.173.07:26:11.96#ibcon#wrote, iclass 12, count 2 2006.173.07:26:11.96#ibcon#about to read 3, iclass 12, count 2 2006.173.07:26:11.98#ibcon#read 3, iclass 12, count 2 2006.173.07:26:11.98#ibcon#about to read 4, iclass 12, count 2 2006.173.07:26:11.98#ibcon#read 4, iclass 12, count 2 2006.173.07:26:11.98#ibcon#about to read 5, iclass 12, count 2 2006.173.07:26:11.98#ibcon#read 5, iclass 12, count 2 2006.173.07:26:11.98#ibcon#about to read 6, iclass 12, count 2 2006.173.07:26:11.98#ibcon#read 6, iclass 12, count 2 2006.173.07:26:11.98#ibcon#end of sib2, iclass 12, count 2 2006.173.07:26:11.98#ibcon#*mode == 0, iclass 12, count 2 2006.173.07:26:11.98#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.07:26:11.98#ibcon#[27=AT01-04\r\n] 2006.173.07:26:11.98#ibcon#*before write, iclass 12, count 2 2006.173.07:26:11.98#ibcon#enter sib2, iclass 12, count 2 2006.173.07:26:11.98#ibcon#flushed, iclass 12, count 2 2006.173.07:26:11.98#ibcon#about to write, iclass 12, count 2 2006.173.07:26:11.98#ibcon#wrote, iclass 12, count 2 2006.173.07:26:11.98#ibcon#about to read 3, iclass 12, count 2 2006.173.07:26:12.01#ibcon#read 3, iclass 12, count 2 2006.173.07:26:12.01#ibcon#about to read 4, iclass 12, count 2 2006.173.07:26:12.01#ibcon#read 4, iclass 12, count 2 2006.173.07:26:12.01#ibcon#about to read 5, iclass 12, count 2 2006.173.07:26:12.01#ibcon#read 5, iclass 12, count 2 2006.173.07:26:12.01#ibcon#about to read 6, iclass 12, count 2 2006.173.07:26:12.01#ibcon#read 6, iclass 12, count 2 2006.173.07:26:12.01#ibcon#end of sib2, iclass 12, count 2 2006.173.07:26:12.01#ibcon#*after write, iclass 12, count 2 2006.173.07:26:12.01#ibcon#*before return 0, iclass 12, count 2 2006.173.07:26:12.01#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.07:26:12.01#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.07:26:12.01#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.07:26:12.01#ibcon#ireg 7 cls_cnt 0 2006.173.07:26:12.01#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.07:26:12.13#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.07:26:12.13#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.07:26:12.13#ibcon#enter wrdev, iclass 12, count 0 2006.173.07:26:12.13#ibcon#first serial, iclass 12, count 0 2006.173.07:26:12.13#ibcon#enter sib2, iclass 12, count 0 2006.173.07:26:12.13#ibcon#flushed, iclass 12, count 0 2006.173.07:26:12.13#ibcon#about to write, iclass 12, count 0 2006.173.07:26:12.13#ibcon#wrote, iclass 12, count 0 2006.173.07:26:12.13#ibcon#about to read 3, iclass 12, count 0 2006.173.07:26:12.15#ibcon#read 3, iclass 12, count 0 2006.173.07:26:12.15#ibcon#about to read 4, iclass 12, count 0 2006.173.07:26:12.15#ibcon#read 4, iclass 12, count 0 2006.173.07:26:12.15#ibcon#about to read 5, iclass 12, count 0 2006.173.07:26:12.15#ibcon#read 5, iclass 12, count 0 2006.173.07:26:12.15#ibcon#about to read 6, iclass 12, count 0 2006.173.07:26:12.15#ibcon#read 6, iclass 12, count 0 2006.173.07:26:12.15#ibcon#end of sib2, iclass 12, count 0 2006.173.07:26:12.15#ibcon#*mode == 0, iclass 12, count 0 2006.173.07:26:12.15#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.07:26:12.15#ibcon#[27=USB\r\n] 2006.173.07:26:12.15#ibcon#*before write, iclass 12, count 0 2006.173.07:26:12.15#ibcon#enter sib2, iclass 12, count 0 2006.173.07:26:12.15#ibcon#flushed, iclass 12, count 0 2006.173.07:26:12.15#ibcon#about to write, iclass 12, count 0 2006.173.07:26:12.15#ibcon#wrote, iclass 12, count 0 2006.173.07:26:12.15#ibcon#about to read 3, iclass 12, count 0 2006.173.07:26:12.18#ibcon#read 3, iclass 12, count 0 2006.173.07:26:12.18#ibcon#about to read 4, iclass 12, count 0 2006.173.07:26:12.18#ibcon#read 4, iclass 12, count 0 2006.173.07:26:12.18#ibcon#about to read 5, iclass 12, count 0 2006.173.07:26:12.18#ibcon#read 5, iclass 12, count 0 2006.173.07:26:12.18#ibcon#about to read 6, iclass 12, count 0 2006.173.07:26:12.18#ibcon#read 6, iclass 12, count 0 2006.173.07:26:12.18#ibcon#end of sib2, iclass 12, count 0 2006.173.07:26:12.18#ibcon#*after write, iclass 12, count 0 2006.173.07:26:12.18#ibcon#*before return 0, iclass 12, count 0 2006.173.07:26:12.18#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.07:26:12.18#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.07:26:12.18#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.07:26:12.18#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.07:26:12.18$vck44/vblo=2,634.99 2006.173.07:26:12.18#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.07:26:12.18#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.07:26:12.18#ibcon#ireg 17 cls_cnt 0 2006.173.07:26:12.18#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.07:26:12.18#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.07:26:12.18#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.07:26:12.18#ibcon#enter wrdev, iclass 14, count 0 2006.173.07:26:12.18#ibcon#first serial, iclass 14, count 0 2006.173.07:26:12.18#ibcon#enter sib2, iclass 14, count 0 2006.173.07:26:12.18#ibcon#flushed, iclass 14, count 0 2006.173.07:26:12.18#ibcon#about to write, iclass 14, count 0 2006.173.07:26:12.18#ibcon#wrote, iclass 14, count 0 2006.173.07:26:12.18#ibcon#about to read 3, iclass 14, count 0 2006.173.07:26:12.20#ibcon#read 3, iclass 14, count 0 2006.173.07:26:12.20#ibcon#about to read 4, iclass 14, count 0 2006.173.07:26:12.20#ibcon#read 4, iclass 14, count 0 2006.173.07:26:12.20#ibcon#about to read 5, iclass 14, count 0 2006.173.07:26:12.20#ibcon#read 5, iclass 14, count 0 2006.173.07:26:12.20#ibcon#about to read 6, iclass 14, count 0 2006.173.07:26:12.20#ibcon#read 6, iclass 14, count 0 2006.173.07:26:12.20#ibcon#end of sib2, iclass 14, count 0 2006.173.07:26:12.20#ibcon#*mode == 0, iclass 14, count 0 2006.173.07:26:12.20#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.07:26:12.20#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.07:26:12.20#ibcon#*before write, iclass 14, count 0 2006.173.07:26:12.20#ibcon#enter sib2, iclass 14, count 0 2006.173.07:26:12.20#ibcon#flushed, iclass 14, count 0 2006.173.07:26:12.20#ibcon#about to write, iclass 14, count 0 2006.173.07:26:12.20#ibcon#wrote, iclass 14, count 0 2006.173.07:26:12.20#ibcon#about to read 3, iclass 14, count 0 2006.173.07:26:12.24#ibcon#read 3, iclass 14, count 0 2006.173.07:26:12.24#ibcon#about to read 4, iclass 14, count 0 2006.173.07:26:12.24#ibcon#read 4, iclass 14, count 0 2006.173.07:26:12.24#ibcon#about to read 5, iclass 14, count 0 2006.173.07:26:12.24#ibcon#read 5, iclass 14, count 0 2006.173.07:26:12.24#ibcon#about to read 6, iclass 14, count 0 2006.173.07:26:12.24#ibcon#read 6, iclass 14, count 0 2006.173.07:26:12.24#ibcon#end of sib2, iclass 14, count 0 2006.173.07:26:12.24#ibcon#*after write, iclass 14, count 0 2006.173.07:26:12.24#ibcon#*before return 0, iclass 14, count 0 2006.173.07:26:12.24#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.07:26:12.24#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.07:26:12.24#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.07:26:12.24#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.07:26:12.24$vck44/vb=2,4 2006.173.07:26:12.24#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.07:26:12.24#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.07:26:12.24#ibcon#ireg 11 cls_cnt 2 2006.173.07:26:12.24#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.07:26:12.30#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.07:26:12.30#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.07:26:12.30#ibcon#enter wrdev, iclass 16, count 2 2006.173.07:26:12.30#ibcon#first serial, iclass 16, count 2 2006.173.07:26:12.30#ibcon#enter sib2, iclass 16, count 2 2006.173.07:26:12.30#ibcon#flushed, iclass 16, count 2 2006.173.07:26:12.30#ibcon#about to write, iclass 16, count 2 2006.173.07:26:12.30#ibcon#wrote, iclass 16, count 2 2006.173.07:26:12.30#ibcon#about to read 3, iclass 16, count 2 2006.173.07:26:12.32#ibcon#read 3, iclass 16, count 2 2006.173.07:26:12.32#ibcon#about to read 4, iclass 16, count 2 2006.173.07:26:12.32#ibcon#read 4, iclass 16, count 2 2006.173.07:26:12.32#ibcon#about to read 5, iclass 16, count 2 2006.173.07:26:12.32#ibcon#read 5, iclass 16, count 2 2006.173.07:26:12.32#ibcon#about to read 6, iclass 16, count 2 2006.173.07:26:12.32#ibcon#read 6, iclass 16, count 2 2006.173.07:26:12.32#ibcon#end of sib2, iclass 16, count 2 2006.173.07:26:12.32#ibcon#*mode == 0, iclass 16, count 2 2006.173.07:26:12.32#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.07:26:12.32#ibcon#[27=AT02-04\r\n] 2006.173.07:26:12.32#ibcon#*before write, iclass 16, count 2 2006.173.07:26:12.32#ibcon#enter sib2, iclass 16, count 2 2006.173.07:26:12.32#ibcon#flushed, iclass 16, count 2 2006.173.07:26:12.32#ibcon#about to write, iclass 16, count 2 2006.173.07:26:12.32#ibcon#wrote, iclass 16, count 2 2006.173.07:26:12.32#ibcon#about to read 3, iclass 16, count 2 2006.173.07:26:12.35#ibcon#read 3, iclass 16, count 2 2006.173.07:26:12.35#ibcon#about to read 4, iclass 16, count 2 2006.173.07:26:12.35#ibcon#read 4, iclass 16, count 2 2006.173.07:26:12.35#ibcon#about to read 5, iclass 16, count 2 2006.173.07:26:12.35#ibcon#read 5, iclass 16, count 2 2006.173.07:26:12.35#ibcon#about to read 6, iclass 16, count 2 2006.173.07:26:12.35#ibcon#read 6, iclass 16, count 2 2006.173.07:26:12.35#ibcon#end of sib2, iclass 16, count 2 2006.173.07:26:12.35#ibcon#*after write, iclass 16, count 2 2006.173.07:26:12.35#ibcon#*before return 0, iclass 16, count 2 2006.173.07:26:12.35#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.07:26:12.35#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.07:26:12.35#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.07:26:12.35#ibcon#ireg 7 cls_cnt 0 2006.173.07:26:12.35#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.07:26:12.47#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.07:26:12.47#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.07:26:12.47#ibcon#enter wrdev, iclass 16, count 0 2006.173.07:26:12.47#ibcon#first serial, iclass 16, count 0 2006.173.07:26:12.47#ibcon#enter sib2, iclass 16, count 0 2006.173.07:26:12.47#ibcon#flushed, iclass 16, count 0 2006.173.07:26:12.47#ibcon#about to write, iclass 16, count 0 2006.173.07:26:12.47#ibcon#wrote, iclass 16, count 0 2006.173.07:26:12.47#ibcon#about to read 3, iclass 16, count 0 2006.173.07:26:12.49#ibcon#read 3, iclass 16, count 0 2006.173.07:26:12.49#ibcon#about to read 4, iclass 16, count 0 2006.173.07:26:12.49#ibcon#read 4, iclass 16, count 0 2006.173.07:26:12.49#ibcon#about to read 5, iclass 16, count 0 2006.173.07:26:12.49#ibcon#read 5, iclass 16, count 0 2006.173.07:26:12.49#ibcon#about to read 6, iclass 16, count 0 2006.173.07:26:12.49#ibcon#read 6, iclass 16, count 0 2006.173.07:26:12.49#ibcon#end of sib2, iclass 16, count 0 2006.173.07:26:12.49#ibcon#*mode == 0, iclass 16, count 0 2006.173.07:26:12.49#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.07:26:12.49#ibcon#[27=USB\r\n] 2006.173.07:26:12.49#ibcon#*before write, iclass 16, count 0 2006.173.07:26:12.49#ibcon#enter sib2, iclass 16, count 0 2006.173.07:26:12.49#ibcon#flushed, iclass 16, count 0 2006.173.07:26:12.49#ibcon#about to write, iclass 16, count 0 2006.173.07:26:12.49#ibcon#wrote, iclass 16, count 0 2006.173.07:26:12.49#ibcon#about to read 3, iclass 16, count 0 2006.173.07:26:12.52#ibcon#read 3, iclass 16, count 0 2006.173.07:26:12.52#ibcon#about to read 4, iclass 16, count 0 2006.173.07:26:12.52#ibcon#read 4, iclass 16, count 0 2006.173.07:26:12.52#ibcon#about to read 5, iclass 16, count 0 2006.173.07:26:12.52#ibcon#read 5, iclass 16, count 0 2006.173.07:26:12.52#ibcon#about to read 6, iclass 16, count 0 2006.173.07:26:12.52#ibcon#read 6, iclass 16, count 0 2006.173.07:26:12.52#ibcon#end of sib2, iclass 16, count 0 2006.173.07:26:12.52#ibcon#*after write, iclass 16, count 0 2006.173.07:26:12.52#ibcon#*before return 0, iclass 16, count 0 2006.173.07:26:12.52#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.07:26:12.52#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.07:26:12.52#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.07:26:12.52#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.07:26:12.52$vck44/vblo=3,649.99 2006.173.07:26:12.52#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.07:26:12.52#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.07:26:12.52#ibcon#ireg 17 cls_cnt 0 2006.173.07:26:12.52#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.07:26:12.52#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.07:26:12.52#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.07:26:12.52#ibcon#enter wrdev, iclass 18, count 0 2006.173.07:26:12.52#ibcon#first serial, iclass 18, count 0 2006.173.07:26:12.52#ibcon#enter sib2, iclass 18, count 0 2006.173.07:26:12.52#ibcon#flushed, iclass 18, count 0 2006.173.07:26:12.52#ibcon#about to write, iclass 18, count 0 2006.173.07:26:12.52#ibcon#wrote, iclass 18, count 0 2006.173.07:26:12.52#ibcon#about to read 3, iclass 18, count 0 2006.173.07:26:12.54#ibcon#read 3, iclass 18, count 0 2006.173.07:26:12.54#ibcon#about to read 4, iclass 18, count 0 2006.173.07:26:12.54#ibcon#read 4, iclass 18, count 0 2006.173.07:26:12.54#ibcon#about to read 5, iclass 18, count 0 2006.173.07:26:12.54#ibcon#read 5, iclass 18, count 0 2006.173.07:26:12.54#ibcon#about to read 6, iclass 18, count 0 2006.173.07:26:12.54#ibcon#read 6, iclass 18, count 0 2006.173.07:26:12.54#ibcon#end of sib2, iclass 18, count 0 2006.173.07:26:12.54#ibcon#*mode == 0, iclass 18, count 0 2006.173.07:26:12.54#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.07:26:12.54#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.07:26:12.54#ibcon#*before write, iclass 18, count 0 2006.173.07:26:12.54#ibcon#enter sib2, iclass 18, count 0 2006.173.07:26:12.54#ibcon#flushed, iclass 18, count 0 2006.173.07:26:12.54#ibcon#about to write, iclass 18, count 0 2006.173.07:26:12.54#ibcon#wrote, iclass 18, count 0 2006.173.07:26:12.54#ibcon#about to read 3, iclass 18, count 0 2006.173.07:26:12.58#ibcon#read 3, iclass 18, count 0 2006.173.07:26:12.58#ibcon#about to read 4, iclass 18, count 0 2006.173.07:26:12.58#ibcon#read 4, iclass 18, count 0 2006.173.07:26:12.58#ibcon#about to read 5, iclass 18, count 0 2006.173.07:26:12.58#ibcon#read 5, iclass 18, count 0 2006.173.07:26:12.58#ibcon#about to read 6, iclass 18, count 0 2006.173.07:26:12.58#ibcon#read 6, iclass 18, count 0 2006.173.07:26:12.58#ibcon#end of sib2, iclass 18, count 0 2006.173.07:26:12.58#ibcon#*after write, iclass 18, count 0 2006.173.07:26:12.58#ibcon#*before return 0, iclass 18, count 0 2006.173.07:26:12.58#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.07:26:12.58#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.07:26:12.58#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.07:26:12.58#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.07:26:12.58$vck44/vb=3,4 2006.173.07:26:12.58#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.07:26:12.58#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.07:26:12.58#ibcon#ireg 11 cls_cnt 2 2006.173.07:26:12.58#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.07:26:12.64#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.07:26:12.64#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.07:26:12.64#ibcon#enter wrdev, iclass 20, count 2 2006.173.07:26:12.64#ibcon#first serial, iclass 20, count 2 2006.173.07:26:12.64#ibcon#enter sib2, iclass 20, count 2 2006.173.07:26:12.64#ibcon#flushed, iclass 20, count 2 2006.173.07:26:12.64#ibcon#about to write, iclass 20, count 2 2006.173.07:26:12.64#ibcon#wrote, iclass 20, count 2 2006.173.07:26:12.64#ibcon#about to read 3, iclass 20, count 2 2006.173.07:26:12.66#ibcon#read 3, iclass 20, count 2 2006.173.07:26:12.66#ibcon#about to read 4, iclass 20, count 2 2006.173.07:26:12.66#ibcon#read 4, iclass 20, count 2 2006.173.07:26:12.66#ibcon#about to read 5, iclass 20, count 2 2006.173.07:26:12.66#ibcon#read 5, iclass 20, count 2 2006.173.07:26:12.66#ibcon#about to read 6, iclass 20, count 2 2006.173.07:26:12.66#ibcon#read 6, iclass 20, count 2 2006.173.07:26:12.66#ibcon#end of sib2, iclass 20, count 2 2006.173.07:26:12.66#ibcon#*mode == 0, iclass 20, count 2 2006.173.07:26:12.66#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.07:26:12.66#ibcon#[27=AT03-04\r\n] 2006.173.07:26:12.66#ibcon#*before write, iclass 20, count 2 2006.173.07:26:12.66#ibcon#enter sib2, iclass 20, count 2 2006.173.07:26:12.66#ibcon#flushed, iclass 20, count 2 2006.173.07:26:12.66#ibcon#about to write, iclass 20, count 2 2006.173.07:26:12.66#ibcon#wrote, iclass 20, count 2 2006.173.07:26:12.66#ibcon#about to read 3, iclass 20, count 2 2006.173.07:26:12.69#ibcon#read 3, iclass 20, count 2 2006.173.07:26:12.69#ibcon#about to read 4, iclass 20, count 2 2006.173.07:26:12.69#ibcon#read 4, iclass 20, count 2 2006.173.07:26:12.69#ibcon#about to read 5, iclass 20, count 2 2006.173.07:26:12.69#ibcon#read 5, iclass 20, count 2 2006.173.07:26:12.69#ibcon#about to read 6, iclass 20, count 2 2006.173.07:26:12.69#ibcon#read 6, iclass 20, count 2 2006.173.07:26:12.69#ibcon#end of sib2, iclass 20, count 2 2006.173.07:26:12.69#ibcon#*after write, iclass 20, count 2 2006.173.07:26:12.69#ibcon#*before return 0, iclass 20, count 2 2006.173.07:26:12.69#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.07:26:12.69#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.07:26:12.69#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.07:26:12.69#ibcon#ireg 7 cls_cnt 0 2006.173.07:26:12.69#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.07:26:12.81#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.07:26:12.81#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.07:26:12.81#ibcon#enter wrdev, iclass 20, count 0 2006.173.07:26:12.81#ibcon#first serial, iclass 20, count 0 2006.173.07:26:12.81#ibcon#enter sib2, iclass 20, count 0 2006.173.07:26:12.81#ibcon#flushed, iclass 20, count 0 2006.173.07:26:12.81#ibcon#about to write, iclass 20, count 0 2006.173.07:26:12.81#ibcon#wrote, iclass 20, count 0 2006.173.07:26:12.81#ibcon#about to read 3, iclass 20, count 0 2006.173.07:26:12.83#ibcon#read 3, iclass 20, count 0 2006.173.07:26:12.83#ibcon#about to read 4, iclass 20, count 0 2006.173.07:26:12.83#ibcon#read 4, iclass 20, count 0 2006.173.07:26:12.83#ibcon#about to read 5, iclass 20, count 0 2006.173.07:26:12.83#ibcon#read 5, iclass 20, count 0 2006.173.07:26:12.83#ibcon#about to read 6, iclass 20, count 0 2006.173.07:26:12.83#ibcon#read 6, iclass 20, count 0 2006.173.07:26:12.83#ibcon#end of sib2, iclass 20, count 0 2006.173.07:26:12.83#ibcon#*mode == 0, iclass 20, count 0 2006.173.07:26:12.83#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.07:26:12.83#ibcon#[27=USB\r\n] 2006.173.07:26:12.83#ibcon#*before write, iclass 20, count 0 2006.173.07:26:12.83#ibcon#enter sib2, iclass 20, count 0 2006.173.07:26:12.83#ibcon#flushed, iclass 20, count 0 2006.173.07:26:12.83#ibcon#about to write, iclass 20, count 0 2006.173.07:26:12.83#ibcon#wrote, iclass 20, count 0 2006.173.07:26:12.83#ibcon#about to read 3, iclass 20, count 0 2006.173.07:26:12.86#ibcon#read 3, iclass 20, count 0 2006.173.07:26:12.86#ibcon#about to read 4, iclass 20, count 0 2006.173.07:26:12.86#ibcon#read 4, iclass 20, count 0 2006.173.07:26:12.86#ibcon#about to read 5, iclass 20, count 0 2006.173.07:26:12.86#ibcon#read 5, iclass 20, count 0 2006.173.07:26:12.86#ibcon#about to read 6, iclass 20, count 0 2006.173.07:26:12.86#ibcon#read 6, iclass 20, count 0 2006.173.07:26:12.86#ibcon#end of sib2, iclass 20, count 0 2006.173.07:26:12.86#ibcon#*after write, iclass 20, count 0 2006.173.07:26:12.86#ibcon#*before return 0, iclass 20, count 0 2006.173.07:26:12.86#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.07:26:12.86#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.07:26:12.86#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.07:26:12.86#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.07:26:12.86$vck44/vblo=4,679.99 2006.173.07:26:12.86#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.07:26:12.86#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.07:26:12.86#ibcon#ireg 17 cls_cnt 0 2006.173.07:26:12.86#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.07:26:12.86#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.07:26:12.86#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.07:26:12.86#ibcon#enter wrdev, iclass 22, count 0 2006.173.07:26:12.86#ibcon#first serial, iclass 22, count 0 2006.173.07:26:12.86#ibcon#enter sib2, iclass 22, count 0 2006.173.07:26:12.86#ibcon#flushed, iclass 22, count 0 2006.173.07:26:12.86#ibcon#about to write, iclass 22, count 0 2006.173.07:26:12.86#ibcon#wrote, iclass 22, count 0 2006.173.07:26:12.86#ibcon#about to read 3, iclass 22, count 0 2006.173.07:26:12.88#ibcon#read 3, iclass 22, count 0 2006.173.07:26:12.88#ibcon#about to read 4, iclass 22, count 0 2006.173.07:26:12.88#ibcon#read 4, iclass 22, count 0 2006.173.07:26:12.88#ibcon#about to read 5, iclass 22, count 0 2006.173.07:26:12.88#ibcon#read 5, iclass 22, count 0 2006.173.07:26:12.88#ibcon#about to read 6, iclass 22, count 0 2006.173.07:26:12.88#ibcon#read 6, iclass 22, count 0 2006.173.07:26:12.88#ibcon#end of sib2, iclass 22, count 0 2006.173.07:26:12.88#ibcon#*mode == 0, iclass 22, count 0 2006.173.07:26:12.88#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.07:26:12.88#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.07:26:12.88#ibcon#*before write, iclass 22, count 0 2006.173.07:26:12.88#ibcon#enter sib2, iclass 22, count 0 2006.173.07:26:12.88#ibcon#flushed, iclass 22, count 0 2006.173.07:26:12.88#ibcon#about to write, iclass 22, count 0 2006.173.07:26:12.88#ibcon#wrote, iclass 22, count 0 2006.173.07:26:12.88#ibcon#about to read 3, iclass 22, count 0 2006.173.07:26:12.92#ibcon#read 3, iclass 22, count 0 2006.173.07:26:12.92#ibcon#about to read 4, iclass 22, count 0 2006.173.07:26:12.92#ibcon#read 4, iclass 22, count 0 2006.173.07:26:12.92#ibcon#about to read 5, iclass 22, count 0 2006.173.07:26:12.92#ibcon#read 5, iclass 22, count 0 2006.173.07:26:12.92#ibcon#about to read 6, iclass 22, count 0 2006.173.07:26:12.92#ibcon#read 6, iclass 22, count 0 2006.173.07:26:12.92#ibcon#end of sib2, iclass 22, count 0 2006.173.07:26:12.92#ibcon#*after write, iclass 22, count 0 2006.173.07:26:12.92#ibcon#*before return 0, iclass 22, count 0 2006.173.07:26:12.92#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.07:26:12.92#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.07:26:12.92#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.07:26:12.92#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.07:26:12.92$vck44/vb=4,4 2006.173.07:26:12.92#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.07:26:12.92#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.07:26:12.92#ibcon#ireg 11 cls_cnt 2 2006.173.07:26:12.92#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.07:26:12.98#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.07:26:12.98#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.07:26:12.98#ibcon#enter wrdev, iclass 24, count 2 2006.173.07:26:12.98#ibcon#first serial, iclass 24, count 2 2006.173.07:26:12.98#ibcon#enter sib2, iclass 24, count 2 2006.173.07:26:12.98#ibcon#flushed, iclass 24, count 2 2006.173.07:26:12.98#ibcon#about to write, iclass 24, count 2 2006.173.07:26:12.98#ibcon#wrote, iclass 24, count 2 2006.173.07:26:12.98#ibcon#about to read 3, iclass 24, count 2 2006.173.07:26:13.00#ibcon#read 3, iclass 24, count 2 2006.173.07:26:13.00#ibcon#about to read 4, iclass 24, count 2 2006.173.07:26:13.00#ibcon#read 4, iclass 24, count 2 2006.173.07:26:13.00#ibcon#about to read 5, iclass 24, count 2 2006.173.07:26:13.00#ibcon#read 5, iclass 24, count 2 2006.173.07:26:13.00#ibcon#about to read 6, iclass 24, count 2 2006.173.07:26:13.00#ibcon#read 6, iclass 24, count 2 2006.173.07:26:13.00#ibcon#end of sib2, iclass 24, count 2 2006.173.07:26:13.00#ibcon#*mode == 0, iclass 24, count 2 2006.173.07:26:13.00#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.07:26:13.00#ibcon#[27=AT04-04\r\n] 2006.173.07:26:13.00#ibcon#*before write, iclass 24, count 2 2006.173.07:26:13.00#ibcon#enter sib2, iclass 24, count 2 2006.173.07:26:13.00#ibcon#flushed, iclass 24, count 2 2006.173.07:26:13.00#ibcon#about to write, iclass 24, count 2 2006.173.07:26:13.00#ibcon#wrote, iclass 24, count 2 2006.173.07:26:13.00#ibcon#about to read 3, iclass 24, count 2 2006.173.07:26:13.03#ibcon#read 3, iclass 24, count 2 2006.173.07:26:13.03#ibcon#about to read 4, iclass 24, count 2 2006.173.07:26:13.03#ibcon#read 4, iclass 24, count 2 2006.173.07:26:13.03#ibcon#about to read 5, iclass 24, count 2 2006.173.07:26:13.03#ibcon#read 5, iclass 24, count 2 2006.173.07:26:13.03#ibcon#about to read 6, iclass 24, count 2 2006.173.07:26:13.03#ibcon#read 6, iclass 24, count 2 2006.173.07:26:13.03#ibcon#end of sib2, iclass 24, count 2 2006.173.07:26:13.03#ibcon#*after write, iclass 24, count 2 2006.173.07:26:13.03#ibcon#*before return 0, iclass 24, count 2 2006.173.07:26:13.03#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.07:26:13.03#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.07:26:13.03#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.07:26:13.03#ibcon#ireg 7 cls_cnt 0 2006.173.07:26:13.03#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.07:26:13.15#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.07:26:13.15#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.07:26:13.15#ibcon#enter wrdev, iclass 24, count 0 2006.173.07:26:13.15#ibcon#first serial, iclass 24, count 0 2006.173.07:26:13.15#ibcon#enter sib2, iclass 24, count 0 2006.173.07:26:13.15#ibcon#flushed, iclass 24, count 0 2006.173.07:26:13.15#ibcon#about to write, iclass 24, count 0 2006.173.07:26:13.15#ibcon#wrote, iclass 24, count 0 2006.173.07:26:13.15#ibcon#about to read 3, iclass 24, count 0 2006.173.07:26:13.17#ibcon#read 3, iclass 24, count 0 2006.173.07:26:13.17#ibcon#about to read 4, iclass 24, count 0 2006.173.07:26:13.17#ibcon#read 4, iclass 24, count 0 2006.173.07:26:13.17#ibcon#about to read 5, iclass 24, count 0 2006.173.07:26:13.17#ibcon#read 5, iclass 24, count 0 2006.173.07:26:13.17#ibcon#about to read 6, iclass 24, count 0 2006.173.07:26:13.17#ibcon#read 6, iclass 24, count 0 2006.173.07:26:13.17#ibcon#end of sib2, iclass 24, count 0 2006.173.07:26:13.17#ibcon#*mode == 0, iclass 24, count 0 2006.173.07:26:13.17#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.07:26:13.17#ibcon#[27=USB\r\n] 2006.173.07:26:13.17#ibcon#*before write, iclass 24, count 0 2006.173.07:26:13.17#ibcon#enter sib2, iclass 24, count 0 2006.173.07:26:13.17#ibcon#flushed, iclass 24, count 0 2006.173.07:26:13.17#ibcon#about to write, iclass 24, count 0 2006.173.07:26:13.17#ibcon#wrote, iclass 24, count 0 2006.173.07:26:13.17#ibcon#about to read 3, iclass 24, count 0 2006.173.07:26:13.20#ibcon#read 3, iclass 24, count 0 2006.173.07:26:13.20#ibcon#about to read 4, iclass 24, count 0 2006.173.07:26:13.20#ibcon#read 4, iclass 24, count 0 2006.173.07:26:13.20#ibcon#about to read 5, iclass 24, count 0 2006.173.07:26:13.20#ibcon#read 5, iclass 24, count 0 2006.173.07:26:13.20#ibcon#about to read 6, iclass 24, count 0 2006.173.07:26:13.20#ibcon#read 6, iclass 24, count 0 2006.173.07:26:13.20#ibcon#end of sib2, iclass 24, count 0 2006.173.07:26:13.20#ibcon#*after write, iclass 24, count 0 2006.173.07:26:13.20#ibcon#*before return 0, iclass 24, count 0 2006.173.07:26:13.20#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.07:26:13.20#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.07:26:13.20#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.07:26:13.20#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.07:26:13.20$vck44/vblo=5,709.99 2006.173.07:26:13.20#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.07:26:13.20#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.07:26:13.20#ibcon#ireg 17 cls_cnt 0 2006.173.07:26:13.20#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.07:26:13.20#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.07:26:13.20#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.07:26:13.20#ibcon#enter wrdev, iclass 26, count 0 2006.173.07:26:13.20#ibcon#first serial, iclass 26, count 0 2006.173.07:26:13.20#ibcon#enter sib2, iclass 26, count 0 2006.173.07:26:13.20#ibcon#flushed, iclass 26, count 0 2006.173.07:26:13.20#ibcon#about to write, iclass 26, count 0 2006.173.07:26:13.20#ibcon#wrote, iclass 26, count 0 2006.173.07:26:13.20#ibcon#about to read 3, iclass 26, count 0 2006.173.07:26:13.22#ibcon#read 3, iclass 26, count 0 2006.173.07:26:13.22#ibcon#about to read 4, iclass 26, count 0 2006.173.07:26:13.22#ibcon#read 4, iclass 26, count 0 2006.173.07:26:13.22#ibcon#about to read 5, iclass 26, count 0 2006.173.07:26:13.22#ibcon#read 5, iclass 26, count 0 2006.173.07:26:13.22#ibcon#about to read 6, iclass 26, count 0 2006.173.07:26:13.22#ibcon#read 6, iclass 26, count 0 2006.173.07:26:13.22#ibcon#end of sib2, iclass 26, count 0 2006.173.07:26:13.22#ibcon#*mode == 0, iclass 26, count 0 2006.173.07:26:13.22#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.07:26:13.22#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.07:26:13.22#ibcon#*before write, iclass 26, count 0 2006.173.07:26:13.22#ibcon#enter sib2, iclass 26, count 0 2006.173.07:26:13.22#ibcon#flushed, iclass 26, count 0 2006.173.07:26:13.22#ibcon#about to write, iclass 26, count 0 2006.173.07:26:13.22#ibcon#wrote, iclass 26, count 0 2006.173.07:26:13.22#ibcon#about to read 3, iclass 26, count 0 2006.173.07:26:13.26#ibcon#read 3, iclass 26, count 0 2006.173.07:26:13.26#ibcon#about to read 4, iclass 26, count 0 2006.173.07:26:13.26#ibcon#read 4, iclass 26, count 0 2006.173.07:26:13.26#ibcon#about to read 5, iclass 26, count 0 2006.173.07:26:13.26#ibcon#read 5, iclass 26, count 0 2006.173.07:26:13.26#ibcon#about to read 6, iclass 26, count 0 2006.173.07:26:13.26#ibcon#read 6, iclass 26, count 0 2006.173.07:26:13.26#ibcon#end of sib2, iclass 26, count 0 2006.173.07:26:13.26#ibcon#*after write, iclass 26, count 0 2006.173.07:26:13.26#ibcon#*before return 0, iclass 26, count 0 2006.173.07:26:13.26#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.07:26:13.26#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.07:26:13.26#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.07:26:13.26#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.07:26:13.26$vck44/vb=5,4 2006.173.07:26:13.26#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.07:26:13.26#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.07:26:13.26#ibcon#ireg 11 cls_cnt 2 2006.173.07:26:13.26#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.07:26:13.32#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.07:26:13.32#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.07:26:13.32#ibcon#enter wrdev, iclass 28, count 2 2006.173.07:26:13.32#ibcon#first serial, iclass 28, count 2 2006.173.07:26:13.32#ibcon#enter sib2, iclass 28, count 2 2006.173.07:26:13.32#ibcon#flushed, iclass 28, count 2 2006.173.07:26:13.32#ibcon#about to write, iclass 28, count 2 2006.173.07:26:13.32#ibcon#wrote, iclass 28, count 2 2006.173.07:26:13.32#ibcon#about to read 3, iclass 28, count 2 2006.173.07:26:13.34#ibcon#read 3, iclass 28, count 2 2006.173.07:26:13.34#ibcon#about to read 4, iclass 28, count 2 2006.173.07:26:13.34#ibcon#read 4, iclass 28, count 2 2006.173.07:26:13.34#ibcon#about to read 5, iclass 28, count 2 2006.173.07:26:13.34#ibcon#read 5, iclass 28, count 2 2006.173.07:26:13.34#ibcon#about to read 6, iclass 28, count 2 2006.173.07:26:13.34#ibcon#read 6, iclass 28, count 2 2006.173.07:26:13.34#ibcon#end of sib2, iclass 28, count 2 2006.173.07:26:13.34#ibcon#*mode == 0, iclass 28, count 2 2006.173.07:26:13.34#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.07:26:13.34#ibcon#[27=AT05-04\r\n] 2006.173.07:26:13.34#ibcon#*before write, iclass 28, count 2 2006.173.07:26:13.34#ibcon#enter sib2, iclass 28, count 2 2006.173.07:26:13.34#ibcon#flushed, iclass 28, count 2 2006.173.07:26:13.34#ibcon#about to write, iclass 28, count 2 2006.173.07:26:13.34#ibcon#wrote, iclass 28, count 2 2006.173.07:26:13.34#ibcon#about to read 3, iclass 28, count 2 2006.173.07:26:13.37#ibcon#read 3, iclass 28, count 2 2006.173.07:26:13.37#ibcon#about to read 4, iclass 28, count 2 2006.173.07:26:13.37#ibcon#read 4, iclass 28, count 2 2006.173.07:26:13.37#ibcon#about to read 5, iclass 28, count 2 2006.173.07:26:13.37#ibcon#read 5, iclass 28, count 2 2006.173.07:26:13.37#ibcon#about to read 6, iclass 28, count 2 2006.173.07:26:13.37#ibcon#read 6, iclass 28, count 2 2006.173.07:26:13.37#ibcon#end of sib2, iclass 28, count 2 2006.173.07:26:13.37#ibcon#*after write, iclass 28, count 2 2006.173.07:26:13.37#ibcon#*before return 0, iclass 28, count 2 2006.173.07:26:13.37#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.07:26:13.37#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.07:26:13.37#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.07:26:13.37#ibcon#ireg 7 cls_cnt 0 2006.173.07:26:13.37#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.07:26:13.49#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.07:26:13.49#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.07:26:13.49#ibcon#enter wrdev, iclass 28, count 0 2006.173.07:26:13.49#ibcon#first serial, iclass 28, count 0 2006.173.07:26:13.49#ibcon#enter sib2, iclass 28, count 0 2006.173.07:26:13.49#ibcon#flushed, iclass 28, count 0 2006.173.07:26:13.49#ibcon#about to write, iclass 28, count 0 2006.173.07:26:13.49#ibcon#wrote, iclass 28, count 0 2006.173.07:26:13.49#ibcon#about to read 3, iclass 28, count 0 2006.173.07:26:13.51#ibcon#read 3, iclass 28, count 0 2006.173.07:26:13.51#ibcon#about to read 4, iclass 28, count 0 2006.173.07:26:13.51#ibcon#read 4, iclass 28, count 0 2006.173.07:26:13.51#ibcon#about to read 5, iclass 28, count 0 2006.173.07:26:13.51#ibcon#read 5, iclass 28, count 0 2006.173.07:26:13.51#ibcon#about to read 6, iclass 28, count 0 2006.173.07:26:13.51#ibcon#read 6, iclass 28, count 0 2006.173.07:26:13.51#ibcon#end of sib2, iclass 28, count 0 2006.173.07:26:13.51#ibcon#*mode == 0, iclass 28, count 0 2006.173.07:26:13.51#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.07:26:13.51#ibcon#[27=USB\r\n] 2006.173.07:26:13.51#ibcon#*before write, iclass 28, count 0 2006.173.07:26:13.51#ibcon#enter sib2, iclass 28, count 0 2006.173.07:26:13.51#ibcon#flushed, iclass 28, count 0 2006.173.07:26:13.51#ibcon#about to write, iclass 28, count 0 2006.173.07:26:13.51#ibcon#wrote, iclass 28, count 0 2006.173.07:26:13.51#ibcon#about to read 3, iclass 28, count 0 2006.173.07:26:13.54#ibcon#read 3, iclass 28, count 0 2006.173.07:26:13.54#ibcon#about to read 4, iclass 28, count 0 2006.173.07:26:13.54#ibcon#read 4, iclass 28, count 0 2006.173.07:26:13.54#ibcon#about to read 5, iclass 28, count 0 2006.173.07:26:13.54#ibcon#read 5, iclass 28, count 0 2006.173.07:26:13.54#ibcon#about to read 6, iclass 28, count 0 2006.173.07:26:13.54#ibcon#read 6, iclass 28, count 0 2006.173.07:26:13.54#ibcon#end of sib2, iclass 28, count 0 2006.173.07:26:13.54#ibcon#*after write, iclass 28, count 0 2006.173.07:26:13.54#ibcon#*before return 0, iclass 28, count 0 2006.173.07:26:13.54#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.07:26:13.54#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.07:26:13.54#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.07:26:13.54#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.07:26:13.54$vck44/vblo=6,719.99 2006.173.07:26:13.54#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.07:26:13.54#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.07:26:13.54#ibcon#ireg 17 cls_cnt 0 2006.173.07:26:13.54#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.07:26:13.54#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.07:26:13.54#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.07:26:13.54#ibcon#enter wrdev, iclass 30, count 0 2006.173.07:26:13.54#ibcon#first serial, iclass 30, count 0 2006.173.07:26:13.54#ibcon#enter sib2, iclass 30, count 0 2006.173.07:26:13.54#ibcon#flushed, iclass 30, count 0 2006.173.07:26:13.54#ibcon#about to write, iclass 30, count 0 2006.173.07:26:13.54#ibcon#wrote, iclass 30, count 0 2006.173.07:26:13.54#ibcon#about to read 3, iclass 30, count 0 2006.173.07:26:13.56#ibcon#read 3, iclass 30, count 0 2006.173.07:26:13.56#ibcon#about to read 4, iclass 30, count 0 2006.173.07:26:13.56#ibcon#read 4, iclass 30, count 0 2006.173.07:26:13.56#ibcon#about to read 5, iclass 30, count 0 2006.173.07:26:13.56#ibcon#read 5, iclass 30, count 0 2006.173.07:26:13.56#ibcon#about to read 6, iclass 30, count 0 2006.173.07:26:13.56#ibcon#read 6, iclass 30, count 0 2006.173.07:26:13.56#ibcon#end of sib2, iclass 30, count 0 2006.173.07:26:13.56#ibcon#*mode == 0, iclass 30, count 0 2006.173.07:26:13.56#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.07:26:13.56#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.07:26:13.56#ibcon#*before write, iclass 30, count 0 2006.173.07:26:13.56#ibcon#enter sib2, iclass 30, count 0 2006.173.07:26:13.56#ibcon#flushed, iclass 30, count 0 2006.173.07:26:13.56#ibcon#about to write, iclass 30, count 0 2006.173.07:26:13.56#ibcon#wrote, iclass 30, count 0 2006.173.07:26:13.56#ibcon#about to read 3, iclass 30, count 0 2006.173.07:26:13.60#ibcon#read 3, iclass 30, count 0 2006.173.07:26:13.60#ibcon#about to read 4, iclass 30, count 0 2006.173.07:26:13.60#ibcon#read 4, iclass 30, count 0 2006.173.07:26:13.60#ibcon#about to read 5, iclass 30, count 0 2006.173.07:26:13.60#ibcon#read 5, iclass 30, count 0 2006.173.07:26:13.60#ibcon#about to read 6, iclass 30, count 0 2006.173.07:26:13.60#ibcon#read 6, iclass 30, count 0 2006.173.07:26:13.60#ibcon#end of sib2, iclass 30, count 0 2006.173.07:26:13.60#ibcon#*after write, iclass 30, count 0 2006.173.07:26:13.60#ibcon#*before return 0, iclass 30, count 0 2006.173.07:26:13.60#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.07:26:13.60#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.07:26:13.60#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.07:26:13.60#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.07:26:13.60$vck44/vb=6,4 2006.173.07:26:13.60#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.173.07:26:13.60#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.173.07:26:13.60#ibcon#ireg 11 cls_cnt 2 2006.173.07:26:13.60#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.07:26:13.66#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.07:26:13.66#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.07:26:13.66#ibcon#enter wrdev, iclass 32, count 2 2006.173.07:26:13.66#ibcon#first serial, iclass 32, count 2 2006.173.07:26:13.66#ibcon#enter sib2, iclass 32, count 2 2006.173.07:26:13.66#ibcon#flushed, iclass 32, count 2 2006.173.07:26:13.66#ibcon#about to write, iclass 32, count 2 2006.173.07:26:13.66#ibcon#wrote, iclass 32, count 2 2006.173.07:26:13.66#ibcon#about to read 3, iclass 32, count 2 2006.173.07:26:13.68#ibcon#read 3, iclass 32, count 2 2006.173.07:26:13.68#ibcon#about to read 4, iclass 32, count 2 2006.173.07:26:13.68#ibcon#read 4, iclass 32, count 2 2006.173.07:26:13.68#ibcon#about to read 5, iclass 32, count 2 2006.173.07:26:13.68#ibcon#read 5, iclass 32, count 2 2006.173.07:26:13.68#ibcon#about to read 6, iclass 32, count 2 2006.173.07:26:13.68#ibcon#read 6, iclass 32, count 2 2006.173.07:26:13.68#ibcon#end of sib2, iclass 32, count 2 2006.173.07:26:13.68#ibcon#*mode == 0, iclass 32, count 2 2006.173.07:26:13.68#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.173.07:26:13.68#ibcon#[27=AT06-04\r\n] 2006.173.07:26:13.68#ibcon#*before write, iclass 32, count 2 2006.173.07:26:13.68#ibcon#enter sib2, iclass 32, count 2 2006.173.07:26:13.68#ibcon#flushed, iclass 32, count 2 2006.173.07:26:13.68#ibcon#about to write, iclass 32, count 2 2006.173.07:26:13.68#ibcon#wrote, iclass 32, count 2 2006.173.07:26:13.68#ibcon#about to read 3, iclass 32, count 2 2006.173.07:26:13.71#ibcon#read 3, iclass 32, count 2 2006.173.07:26:13.71#ibcon#about to read 4, iclass 32, count 2 2006.173.07:26:13.71#ibcon#read 4, iclass 32, count 2 2006.173.07:26:13.71#ibcon#about to read 5, iclass 32, count 2 2006.173.07:26:13.71#ibcon#read 5, iclass 32, count 2 2006.173.07:26:13.71#ibcon#about to read 6, iclass 32, count 2 2006.173.07:26:13.71#ibcon#read 6, iclass 32, count 2 2006.173.07:26:13.71#ibcon#end of sib2, iclass 32, count 2 2006.173.07:26:13.71#ibcon#*after write, iclass 32, count 2 2006.173.07:26:13.71#ibcon#*before return 0, iclass 32, count 2 2006.173.07:26:13.71#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.07:26:13.71#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.173.07:26:13.71#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.173.07:26:13.71#ibcon#ireg 7 cls_cnt 0 2006.173.07:26:13.71#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.07:26:13.83#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.07:26:13.83#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.07:26:13.83#ibcon#enter wrdev, iclass 32, count 0 2006.173.07:26:13.83#ibcon#first serial, iclass 32, count 0 2006.173.07:26:13.83#ibcon#enter sib2, iclass 32, count 0 2006.173.07:26:13.83#ibcon#flushed, iclass 32, count 0 2006.173.07:26:13.83#ibcon#about to write, iclass 32, count 0 2006.173.07:26:13.83#ibcon#wrote, iclass 32, count 0 2006.173.07:26:13.83#ibcon#about to read 3, iclass 32, count 0 2006.173.07:26:13.85#ibcon#read 3, iclass 32, count 0 2006.173.07:26:13.85#ibcon#about to read 4, iclass 32, count 0 2006.173.07:26:13.85#ibcon#read 4, iclass 32, count 0 2006.173.07:26:13.85#ibcon#about to read 5, iclass 32, count 0 2006.173.07:26:13.85#ibcon#read 5, iclass 32, count 0 2006.173.07:26:13.85#ibcon#about to read 6, iclass 32, count 0 2006.173.07:26:13.85#ibcon#read 6, iclass 32, count 0 2006.173.07:26:13.85#ibcon#end of sib2, iclass 32, count 0 2006.173.07:26:13.85#ibcon#*mode == 0, iclass 32, count 0 2006.173.07:26:13.85#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.07:26:13.85#ibcon#[27=USB\r\n] 2006.173.07:26:13.85#ibcon#*before write, iclass 32, count 0 2006.173.07:26:13.85#ibcon#enter sib2, iclass 32, count 0 2006.173.07:26:13.85#ibcon#flushed, iclass 32, count 0 2006.173.07:26:13.85#ibcon#about to write, iclass 32, count 0 2006.173.07:26:13.85#ibcon#wrote, iclass 32, count 0 2006.173.07:26:13.85#ibcon#about to read 3, iclass 32, count 0 2006.173.07:26:13.88#ibcon#read 3, iclass 32, count 0 2006.173.07:26:13.88#ibcon#about to read 4, iclass 32, count 0 2006.173.07:26:13.88#ibcon#read 4, iclass 32, count 0 2006.173.07:26:13.88#ibcon#about to read 5, iclass 32, count 0 2006.173.07:26:13.88#ibcon#read 5, iclass 32, count 0 2006.173.07:26:13.88#ibcon#about to read 6, iclass 32, count 0 2006.173.07:26:13.88#ibcon#read 6, iclass 32, count 0 2006.173.07:26:13.88#ibcon#end of sib2, iclass 32, count 0 2006.173.07:26:13.88#ibcon#*after write, iclass 32, count 0 2006.173.07:26:13.88#ibcon#*before return 0, iclass 32, count 0 2006.173.07:26:13.88#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.07:26:13.88#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.173.07:26:13.88#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.07:26:13.88#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.07:26:13.88$vck44/vblo=7,734.99 2006.173.07:26:13.88#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.07:26:13.88#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.07:26:13.88#ibcon#ireg 17 cls_cnt 0 2006.173.07:26:13.88#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.07:26:13.88#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.07:26:13.88#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.07:26:13.88#ibcon#enter wrdev, iclass 34, count 0 2006.173.07:26:13.88#ibcon#first serial, iclass 34, count 0 2006.173.07:26:13.88#ibcon#enter sib2, iclass 34, count 0 2006.173.07:26:13.88#ibcon#flushed, iclass 34, count 0 2006.173.07:26:13.88#ibcon#about to write, iclass 34, count 0 2006.173.07:26:13.88#ibcon#wrote, iclass 34, count 0 2006.173.07:26:13.88#ibcon#about to read 3, iclass 34, count 0 2006.173.07:26:13.90#ibcon#read 3, iclass 34, count 0 2006.173.07:26:13.90#ibcon#about to read 4, iclass 34, count 0 2006.173.07:26:13.90#ibcon#read 4, iclass 34, count 0 2006.173.07:26:13.90#ibcon#about to read 5, iclass 34, count 0 2006.173.07:26:13.90#ibcon#read 5, iclass 34, count 0 2006.173.07:26:13.90#ibcon#about to read 6, iclass 34, count 0 2006.173.07:26:13.90#ibcon#read 6, iclass 34, count 0 2006.173.07:26:13.90#ibcon#end of sib2, iclass 34, count 0 2006.173.07:26:13.90#ibcon#*mode == 0, iclass 34, count 0 2006.173.07:26:13.90#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.07:26:13.90#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.07:26:13.90#ibcon#*before write, iclass 34, count 0 2006.173.07:26:13.90#ibcon#enter sib2, iclass 34, count 0 2006.173.07:26:13.90#ibcon#flushed, iclass 34, count 0 2006.173.07:26:13.90#ibcon#about to write, iclass 34, count 0 2006.173.07:26:13.90#ibcon#wrote, iclass 34, count 0 2006.173.07:26:13.90#ibcon#about to read 3, iclass 34, count 0 2006.173.07:26:13.94#ibcon#read 3, iclass 34, count 0 2006.173.07:26:13.94#ibcon#about to read 4, iclass 34, count 0 2006.173.07:26:13.94#ibcon#read 4, iclass 34, count 0 2006.173.07:26:13.94#ibcon#about to read 5, iclass 34, count 0 2006.173.07:26:13.94#ibcon#read 5, iclass 34, count 0 2006.173.07:26:13.94#ibcon#about to read 6, iclass 34, count 0 2006.173.07:26:13.94#ibcon#read 6, iclass 34, count 0 2006.173.07:26:13.94#ibcon#end of sib2, iclass 34, count 0 2006.173.07:26:13.94#ibcon#*after write, iclass 34, count 0 2006.173.07:26:13.94#ibcon#*before return 0, iclass 34, count 0 2006.173.07:26:13.94#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.07:26:13.94#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.07:26:13.94#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.07:26:13.94#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.07:26:13.94$vck44/vb=7,4 2006.173.07:26:13.94#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.07:26:13.94#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.07:26:13.94#ibcon#ireg 11 cls_cnt 2 2006.173.07:26:13.94#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.07:26:14.00#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.07:26:14.00#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.07:26:14.00#ibcon#enter wrdev, iclass 36, count 2 2006.173.07:26:14.00#ibcon#first serial, iclass 36, count 2 2006.173.07:26:14.00#ibcon#enter sib2, iclass 36, count 2 2006.173.07:26:14.00#ibcon#flushed, iclass 36, count 2 2006.173.07:26:14.00#ibcon#about to write, iclass 36, count 2 2006.173.07:26:14.00#ibcon#wrote, iclass 36, count 2 2006.173.07:26:14.00#ibcon#about to read 3, iclass 36, count 2 2006.173.07:26:14.02#ibcon#read 3, iclass 36, count 2 2006.173.07:26:14.02#ibcon#about to read 4, iclass 36, count 2 2006.173.07:26:14.02#ibcon#read 4, iclass 36, count 2 2006.173.07:26:14.02#ibcon#about to read 5, iclass 36, count 2 2006.173.07:26:14.02#ibcon#read 5, iclass 36, count 2 2006.173.07:26:14.02#ibcon#about to read 6, iclass 36, count 2 2006.173.07:26:14.02#ibcon#read 6, iclass 36, count 2 2006.173.07:26:14.02#ibcon#end of sib2, iclass 36, count 2 2006.173.07:26:14.02#ibcon#*mode == 0, iclass 36, count 2 2006.173.07:26:14.02#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.07:26:14.02#ibcon#[27=AT07-04\r\n] 2006.173.07:26:14.02#ibcon#*before write, iclass 36, count 2 2006.173.07:26:14.02#ibcon#enter sib2, iclass 36, count 2 2006.173.07:26:14.02#ibcon#flushed, iclass 36, count 2 2006.173.07:26:14.02#ibcon#about to write, iclass 36, count 2 2006.173.07:26:14.02#ibcon#wrote, iclass 36, count 2 2006.173.07:26:14.02#ibcon#about to read 3, iclass 36, count 2 2006.173.07:26:14.05#ibcon#read 3, iclass 36, count 2 2006.173.07:26:14.05#ibcon#about to read 4, iclass 36, count 2 2006.173.07:26:14.05#ibcon#read 4, iclass 36, count 2 2006.173.07:26:14.05#ibcon#about to read 5, iclass 36, count 2 2006.173.07:26:14.05#ibcon#read 5, iclass 36, count 2 2006.173.07:26:14.05#ibcon#about to read 6, iclass 36, count 2 2006.173.07:26:14.05#ibcon#read 6, iclass 36, count 2 2006.173.07:26:14.05#ibcon#end of sib2, iclass 36, count 2 2006.173.07:26:14.05#ibcon#*after write, iclass 36, count 2 2006.173.07:26:14.05#ibcon#*before return 0, iclass 36, count 2 2006.173.07:26:14.05#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.07:26:14.05#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.07:26:14.05#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.07:26:14.05#ibcon#ireg 7 cls_cnt 0 2006.173.07:26:14.05#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.07:26:14.17#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.07:26:14.17#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.07:26:14.17#ibcon#enter wrdev, iclass 36, count 0 2006.173.07:26:14.17#ibcon#first serial, iclass 36, count 0 2006.173.07:26:14.17#ibcon#enter sib2, iclass 36, count 0 2006.173.07:26:14.17#ibcon#flushed, iclass 36, count 0 2006.173.07:26:14.17#ibcon#about to write, iclass 36, count 0 2006.173.07:26:14.17#ibcon#wrote, iclass 36, count 0 2006.173.07:26:14.17#ibcon#about to read 3, iclass 36, count 0 2006.173.07:26:14.19#ibcon#read 3, iclass 36, count 0 2006.173.07:26:14.19#ibcon#about to read 4, iclass 36, count 0 2006.173.07:26:14.19#ibcon#read 4, iclass 36, count 0 2006.173.07:26:14.19#ibcon#about to read 5, iclass 36, count 0 2006.173.07:26:14.19#ibcon#read 5, iclass 36, count 0 2006.173.07:26:14.19#ibcon#about to read 6, iclass 36, count 0 2006.173.07:26:14.19#ibcon#read 6, iclass 36, count 0 2006.173.07:26:14.19#ibcon#end of sib2, iclass 36, count 0 2006.173.07:26:14.19#ibcon#*mode == 0, iclass 36, count 0 2006.173.07:26:14.19#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.07:26:14.19#ibcon#[27=USB\r\n] 2006.173.07:26:14.19#ibcon#*before write, iclass 36, count 0 2006.173.07:26:14.19#ibcon#enter sib2, iclass 36, count 0 2006.173.07:26:14.19#ibcon#flushed, iclass 36, count 0 2006.173.07:26:14.19#ibcon#about to write, iclass 36, count 0 2006.173.07:26:14.19#ibcon#wrote, iclass 36, count 0 2006.173.07:26:14.19#ibcon#about to read 3, iclass 36, count 0 2006.173.07:26:14.22#ibcon#read 3, iclass 36, count 0 2006.173.07:26:14.22#ibcon#about to read 4, iclass 36, count 0 2006.173.07:26:14.22#ibcon#read 4, iclass 36, count 0 2006.173.07:26:14.22#ibcon#about to read 5, iclass 36, count 0 2006.173.07:26:14.22#ibcon#read 5, iclass 36, count 0 2006.173.07:26:14.22#ibcon#about to read 6, iclass 36, count 0 2006.173.07:26:14.22#ibcon#read 6, iclass 36, count 0 2006.173.07:26:14.22#ibcon#end of sib2, iclass 36, count 0 2006.173.07:26:14.22#ibcon#*after write, iclass 36, count 0 2006.173.07:26:14.22#ibcon#*before return 0, iclass 36, count 0 2006.173.07:26:14.22#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.07:26:14.22#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.07:26:14.22#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.07:26:14.22#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.07:26:14.22$vck44/vblo=8,744.99 2006.173.07:26:14.22#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.07:26:14.22#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.07:26:14.22#ibcon#ireg 17 cls_cnt 0 2006.173.07:26:14.22#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.07:26:14.22#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.07:26:14.22#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.07:26:14.22#ibcon#enter wrdev, iclass 38, count 0 2006.173.07:26:14.22#ibcon#first serial, iclass 38, count 0 2006.173.07:26:14.22#ibcon#enter sib2, iclass 38, count 0 2006.173.07:26:14.22#ibcon#flushed, iclass 38, count 0 2006.173.07:26:14.22#ibcon#about to write, iclass 38, count 0 2006.173.07:26:14.22#ibcon#wrote, iclass 38, count 0 2006.173.07:26:14.22#ibcon#about to read 3, iclass 38, count 0 2006.173.07:26:14.24#ibcon#read 3, iclass 38, count 0 2006.173.07:26:14.24#ibcon#about to read 4, iclass 38, count 0 2006.173.07:26:14.24#ibcon#read 4, iclass 38, count 0 2006.173.07:26:14.24#ibcon#about to read 5, iclass 38, count 0 2006.173.07:26:14.24#ibcon#read 5, iclass 38, count 0 2006.173.07:26:14.24#ibcon#about to read 6, iclass 38, count 0 2006.173.07:26:14.24#ibcon#read 6, iclass 38, count 0 2006.173.07:26:14.24#ibcon#end of sib2, iclass 38, count 0 2006.173.07:26:14.24#ibcon#*mode == 0, iclass 38, count 0 2006.173.07:26:14.24#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.07:26:14.24#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.07:26:14.24#ibcon#*before write, iclass 38, count 0 2006.173.07:26:14.24#ibcon#enter sib2, iclass 38, count 0 2006.173.07:26:14.24#ibcon#flushed, iclass 38, count 0 2006.173.07:26:14.24#ibcon#about to write, iclass 38, count 0 2006.173.07:26:14.24#ibcon#wrote, iclass 38, count 0 2006.173.07:26:14.24#ibcon#about to read 3, iclass 38, count 0 2006.173.07:26:14.28#ibcon#read 3, iclass 38, count 0 2006.173.07:26:14.28#ibcon#about to read 4, iclass 38, count 0 2006.173.07:26:14.28#ibcon#read 4, iclass 38, count 0 2006.173.07:26:14.28#ibcon#about to read 5, iclass 38, count 0 2006.173.07:26:14.28#ibcon#read 5, iclass 38, count 0 2006.173.07:26:14.28#ibcon#about to read 6, iclass 38, count 0 2006.173.07:26:14.28#ibcon#read 6, iclass 38, count 0 2006.173.07:26:14.28#ibcon#end of sib2, iclass 38, count 0 2006.173.07:26:14.28#ibcon#*after write, iclass 38, count 0 2006.173.07:26:14.28#ibcon#*before return 0, iclass 38, count 0 2006.173.07:26:14.28#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.07:26:14.28#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.07:26:14.28#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.07:26:14.28#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.07:26:14.28$vck44/vb=8,4 2006.173.07:26:14.28#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.07:26:14.28#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.07:26:14.28#ibcon#ireg 11 cls_cnt 2 2006.173.07:26:14.28#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.07:26:14.34#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.07:26:14.34#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.07:26:14.34#ibcon#enter wrdev, iclass 40, count 2 2006.173.07:26:14.34#ibcon#first serial, iclass 40, count 2 2006.173.07:26:14.34#ibcon#enter sib2, iclass 40, count 2 2006.173.07:26:14.34#ibcon#flushed, iclass 40, count 2 2006.173.07:26:14.34#ibcon#about to write, iclass 40, count 2 2006.173.07:26:14.34#ibcon#wrote, iclass 40, count 2 2006.173.07:26:14.34#ibcon#about to read 3, iclass 40, count 2 2006.173.07:26:14.36#ibcon#read 3, iclass 40, count 2 2006.173.07:26:14.36#ibcon#about to read 4, iclass 40, count 2 2006.173.07:26:14.36#ibcon#read 4, iclass 40, count 2 2006.173.07:26:14.36#ibcon#about to read 5, iclass 40, count 2 2006.173.07:26:14.36#ibcon#read 5, iclass 40, count 2 2006.173.07:26:14.36#ibcon#about to read 6, iclass 40, count 2 2006.173.07:26:14.36#ibcon#read 6, iclass 40, count 2 2006.173.07:26:14.36#ibcon#end of sib2, iclass 40, count 2 2006.173.07:26:14.36#ibcon#*mode == 0, iclass 40, count 2 2006.173.07:26:14.36#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.07:26:14.36#ibcon#[27=AT08-04\r\n] 2006.173.07:26:14.36#ibcon#*before write, iclass 40, count 2 2006.173.07:26:14.36#ibcon#enter sib2, iclass 40, count 2 2006.173.07:26:14.36#ibcon#flushed, iclass 40, count 2 2006.173.07:26:14.36#ibcon#about to write, iclass 40, count 2 2006.173.07:26:14.36#ibcon#wrote, iclass 40, count 2 2006.173.07:26:14.36#ibcon#about to read 3, iclass 40, count 2 2006.173.07:26:14.39#ibcon#read 3, iclass 40, count 2 2006.173.07:26:14.39#ibcon#about to read 4, iclass 40, count 2 2006.173.07:26:14.39#ibcon#read 4, iclass 40, count 2 2006.173.07:26:14.39#ibcon#about to read 5, iclass 40, count 2 2006.173.07:26:14.39#ibcon#read 5, iclass 40, count 2 2006.173.07:26:14.39#ibcon#about to read 6, iclass 40, count 2 2006.173.07:26:14.39#ibcon#read 6, iclass 40, count 2 2006.173.07:26:14.39#ibcon#end of sib2, iclass 40, count 2 2006.173.07:26:14.39#ibcon#*after write, iclass 40, count 2 2006.173.07:26:14.39#ibcon#*before return 0, iclass 40, count 2 2006.173.07:26:14.39#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.07:26:14.39#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.07:26:14.39#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.07:26:14.39#ibcon#ireg 7 cls_cnt 0 2006.173.07:26:14.39#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.07:26:14.51#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.07:26:14.51#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.07:26:14.51#ibcon#enter wrdev, iclass 40, count 0 2006.173.07:26:14.51#ibcon#first serial, iclass 40, count 0 2006.173.07:26:14.51#ibcon#enter sib2, iclass 40, count 0 2006.173.07:26:14.51#ibcon#flushed, iclass 40, count 0 2006.173.07:26:14.51#ibcon#about to write, iclass 40, count 0 2006.173.07:26:14.51#ibcon#wrote, iclass 40, count 0 2006.173.07:26:14.51#ibcon#about to read 3, iclass 40, count 0 2006.173.07:26:14.53#ibcon#read 3, iclass 40, count 0 2006.173.07:26:14.53#ibcon#about to read 4, iclass 40, count 0 2006.173.07:26:14.53#ibcon#read 4, iclass 40, count 0 2006.173.07:26:14.53#ibcon#about to read 5, iclass 40, count 0 2006.173.07:26:14.53#ibcon#read 5, iclass 40, count 0 2006.173.07:26:14.53#ibcon#about to read 6, iclass 40, count 0 2006.173.07:26:14.53#ibcon#read 6, iclass 40, count 0 2006.173.07:26:14.53#ibcon#end of sib2, iclass 40, count 0 2006.173.07:26:14.53#ibcon#*mode == 0, iclass 40, count 0 2006.173.07:26:14.53#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.07:26:14.53#ibcon#[27=USB\r\n] 2006.173.07:26:14.53#ibcon#*before write, iclass 40, count 0 2006.173.07:26:14.53#ibcon#enter sib2, iclass 40, count 0 2006.173.07:26:14.53#ibcon#flushed, iclass 40, count 0 2006.173.07:26:14.53#ibcon#about to write, iclass 40, count 0 2006.173.07:26:14.53#ibcon#wrote, iclass 40, count 0 2006.173.07:26:14.53#ibcon#about to read 3, iclass 40, count 0 2006.173.07:26:14.56#ibcon#read 3, iclass 40, count 0 2006.173.07:26:14.56#ibcon#about to read 4, iclass 40, count 0 2006.173.07:26:14.56#ibcon#read 4, iclass 40, count 0 2006.173.07:26:14.56#ibcon#about to read 5, iclass 40, count 0 2006.173.07:26:14.56#ibcon#read 5, iclass 40, count 0 2006.173.07:26:14.56#ibcon#about to read 6, iclass 40, count 0 2006.173.07:26:14.56#ibcon#read 6, iclass 40, count 0 2006.173.07:26:14.56#ibcon#end of sib2, iclass 40, count 0 2006.173.07:26:14.56#ibcon#*after write, iclass 40, count 0 2006.173.07:26:14.56#ibcon#*before return 0, iclass 40, count 0 2006.173.07:26:14.56#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.07:26:14.56#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.07:26:14.56#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.07:26:14.56#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.07:26:14.56$vck44/vabw=wide 2006.173.07:26:14.56#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.07:26:14.56#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.07:26:14.56#ibcon#ireg 8 cls_cnt 0 2006.173.07:26:14.56#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.07:26:14.56#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.07:26:14.56#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.07:26:14.56#ibcon#enter wrdev, iclass 4, count 0 2006.173.07:26:14.56#ibcon#first serial, iclass 4, count 0 2006.173.07:26:14.56#ibcon#enter sib2, iclass 4, count 0 2006.173.07:26:14.56#ibcon#flushed, iclass 4, count 0 2006.173.07:26:14.56#ibcon#about to write, iclass 4, count 0 2006.173.07:26:14.56#ibcon#wrote, iclass 4, count 0 2006.173.07:26:14.56#ibcon#about to read 3, iclass 4, count 0 2006.173.07:26:14.58#ibcon#read 3, iclass 4, count 0 2006.173.07:26:14.58#ibcon#about to read 4, iclass 4, count 0 2006.173.07:26:14.58#ibcon#read 4, iclass 4, count 0 2006.173.07:26:14.58#ibcon#about to read 5, iclass 4, count 0 2006.173.07:26:14.58#ibcon#read 5, iclass 4, count 0 2006.173.07:26:14.58#ibcon#about to read 6, iclass 4, count 0 2006.173.07:26:14.58#ibcon#read 6, iclass 4, count 0 2006.173.07:26:14.58#ibcon#end of sib2, iclass 4, count 0 2006.173.07:26:14.58#ibcon#*mode == 0, iclass 4, count 0 2006.173.07:26:14.58#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.07:26:14.58#ibcon#[25=BW32\r\n] 2006.173.07:26:14.58#ibcon#*before write, iclass 4, count 0 2006.173.07:26:14.58#ibcon#enter sib2, iclass 4, count 0 2006.173.07:26:14.58#ibcon#flushed, iclass 4, count 0 2006.173.07:26:14.58#ibcon#about to write, iclass 4, count 0 2006.173.07:26:14.58#ibcon#wrote, iclass 4, count 0 2006.173.07:26:14.58#ibcon#about to read 3, iclass 4, count 0 2006.173.07:26:14.61#ibcon#read 3, iclass 4, count 0 2006.173.07:26:14.61#ibcon#about to read 4, iclass 4, count 0 2006.173.07:26:14.61#ibcon#read 4, iclass 4, count 0 2006.173.07:26:14.61#ibcon#about to read 5, iclass 4, count 0 2006.173.07:26:14.61#ibcon#read 5, iclass 4, count 0 2006.173.07:26:14.61#ibcon#about to read 6, iclass 4, count 0 2006.173.07:26:14.61#ibcon#read 6, iclass 4, count 0 2006.173.07:26:14.61#ibcon#end of sib2, iclass 4, count 0 2006.173.07:26:14.61#ibcon#*after write, iclass 4, count 0 2006.173.07:26:14.61#ibcon#*before return 0, iclass 4, count 0 2006.173.07:26:14.61#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.07:26:14.61#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.07:26:14.61#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.07:26:14.61#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.07:26:14.61$vck44/vbbw=wide 2006.173.07:26:14.61#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.07:26:14.61#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.07:26:14.61#ibcon#ireg 8 cls_cnt 0 2006.173.07:26:14.61#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.07:26:14.68#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.07:26:14.68#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.07:26:14.68#ibcon#enter wrdev, iclass 6, count 0 2006.173.07:26:14.68#ibcon#first serial, iclass 6, count 0 2006.173.07:26:14.68#ibcon#enter sib2, iclass 6, count 0 2006.173.07:26:14.68#ibcon#flushed, iclass 6, count 0 2006.173.07:26:14.68#ibcon#about to write, iclass 6, count 0 2006.173.07:26:14.68#ibcon#wrote, iclass 6, count 0 2006.173.07:26:14.68#ibcon#about to read 3, iclass 6, count 0 2006.173.07:26:14.70#ibcon#read 3, iclass 6, count 0 2006.173.07:26:14.70#ibcon#about to read 4, iclass 6, count 0 2006.173.07:26:14.70#ibcon#read 4, iclass 6, count 0 2006.173.07:26:14.70#ibcon#about to read 5, iclass 6, count 0 2006.173.07:26:14.70#ibcon#read 5, iclass 6, count 0 2006.173.07:26:14.70#ibcon#about to read 6, iclass 6, count 0 2006.173.07:26:14.70#ibcon#read 6, iclass 6, count 0 2006.173.07:26:14.70#ibcon#end of sib2, iclass 6, count 0 2006.173.07:26:14.70#ibcon#*mode == 0, iclass 6, count 0 2006.173.07:26:14.70#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.07:26:14.70#ibcon#[27=BW32\r\n] 2006.173.07:26:14.70#ibcon#*before write, iclass 6, count 0 2006.173.07:26:14.70#ibcon#enter sib2, iclass 6, count 0 2006.173.07:26:14.70#ibcon#flushed, iclass 6, count 0 2006.173.07:26:14.70#ibcon#about to write, iclass 6, count 0 2006.173.07:26:14.70#ibcon#wrote, iclass 6, count 0 2006.173.07:26:14.70#ibcon#about to read 3, iclass 6, count 0 2006.173.07:26:14.73#ibcon#read 3, iclass 6, count 0 2006.173.07:26:14.73#ibcon#about to read 4, iclass 6, count 0 2006.173.07:26:14.73#ibcon#read 4, iclass 6, count 0 2006.173.07:26:14.73#ibcon#about to read 5, iclass 6, count 0 2006.173.07:26:14.73#ibcon#read 5, iclass 6, count 0 2006.173.07:26:14.73#ibcon#about to read 6, iclass 6, count 0 2006.173.07:26:14.73#ibcon#read 6, iclass 6, count 0 2006.173.07:26:14.73#ibcon#end of sib2, iclass 6, count 0 2006.173.07:26:14.73#ibcon#*after write, iclass 6, count 0 2006.173.07:26:14.73#ibcon#*before return 0, iclass 6, count 0 2006.173.07:26:14.73#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.07:26:14.73#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.07:26:14.73#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.07:26:14.73#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.07:26:14.73$setupk4/ifdk4 2006.173.07:26:14.73$ifdk4/lo= 2006.173.07:26:14.73$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.07:26:14.73$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.07:26:14.73$ifdk4/patch= 2006.173.07:26:14.73$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.07:26:14.73$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.07:26:14.73$setupk4/!*+20s 2006.173.07:26:21.22#abcon#<5=/02 0.4 0.6 23.76 831004.5\r\n> 2006.173.07:26:21.24#abcon#{5=INTERFACE CLEAR} 2006.173.07:26:21.30#abcon#[5=S1D000X0/0*\r\n] 2006.173.07:26:24.14#trakl#Source acquired 2006.173.07:26:25.14#flagr#flagr/antenna,acquired 2006.173.07:26:29.24$setupk4/"tpicd 2006.173.07:26:29.24$setupk4/echo=off 2006.173.07:26:29.24$setupk4/xlog=off 2006.173.07:26:29.24:!2006.173.07:27:25 2006.173.07:27:25.00:preob 2006.173.07:27:26.13/onsource/TRACKING 2006.173.07:27:26.13:!2006.173.07:27:35 2006.173.07:27:35.00:"tape 2006.173.07:27:35.00:"st=record 2006.173.07:27:35.00:data_valid=on 2006.173.07:27:35.00:midob 2006.173.07:27:35.13/onsource/TRACKING 2006.173.07:27:35.13/wx/23.76,1004.5,83 2006.173.07:27:35.24/cable/+6.4983E-03 2006.173.07:27:36.33/va/01,07,usb,yes,38,40 2006.173.07:27:36.33/va/02,06,usb,yes,37,38 2006.173.07:27:36.33/va/03,05,usb,yes,47,49 2006.173.07:27:36.33/va/04,06,usb,yes,38,40 2006.173.07:27:36.33/va/05,04,usb,yes,30,30 2006.173.07:27:36.33/va/06,03,usb,yes,42,42 2006.173.07:27:36.33/va/07,04,usb,yes,34,35 2006.173.07:27:36.33/va/08,04,usb,yes,29,35 2006.173.07:27:36.56/valo/01,524.99,yes,locked 2006.173.07:27:36.56/valo/02,534.99,yes,locked 2006.173.07:27:36.56/valo/03,564.99,yes,locked 2006.173.07:27:36.56/valo/04,624.99,yes,locked 2006.173.07:27:36.56/valo/05,734.99,yes,locked 2006.173.07:27:36.56/valo/06,814.99,yes,locked 2006.173.07:27:36.56/valo/07,864.99,yes,locked 2006.173.07:27:36.56/valo/08,884.99,yes,locked 2006.173.07:27:37.65/vb/01,04,usb,yes,36,33 2006.173.07:27:37.65/vb/02,04,usb,yes,38,38 2006.173.07:27:37.65/vb/03,04,usb,yes,35,38 2006.173.07:27:37.65/vb/04,04,usb,yes,40,39 2006.173.07:27:37.65/vb/05,04,usb,yes,31,34 2006.173.07:27:37.65/vb/06,04,usb,yes,36,32 2006.173.07:27:37.65/vb/07,04,usb,yes,36,36 2006.173.07:27:37.65/vb/08,04,usb,yes,33,37 2006.173.07:27:37.88/vblo/01,629.99,yes,locked 2006.173.07:27:37.88/vblo/02,634.99,yes,locked 2006.173.07:27:37.88/vblo/03,649.99,yes,locked 2006.173.07:27:37.88/vblo/04,679.99,yes,locked 2006.173.07:27:37.88/vblo/05,709.99,yes,locked 2006.173.07:27:37.88/vblo/06,719.99,yes,locked 2006.173.07:27:37.88/vblo/07,734.99,yes,locked 2006.173.07:27:37.88/vblo/08,744.99,yes,locked 2006.173.07:27:38.03/vabw/8 2006.173.07:27:38.18/vbbw/8 2006.173.07:27:38.27/xfe/off,on,15.0 2006.173.07:27:38.66/ifatt/23,28,28,28 2006.173.07:27:39.07/fmout-gps/S +3.95E-07 2006.173.07:27:39.11:!2006.173.07:29:05 2006.173.07:29:05.00:data_valid=off 2006.173.07:29:05.00:"et 2006.173.07:29:05.00:!+3s 2006.173.07:29:08.01:"tape 2006.173.07:29:08.01:postob 2006.173.07:29:08.13/cable/+6.5018E-03 2006.173.07:29:08.13/wx/23.77,1004.5,82 2006.173.07:29:09.07/fmout-gps/S +3.95E-07 2006.173.07:29:09.07:scan_name=173-0736,jd0606,50 2006.173.07:29:09.07:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.173.07:29:09.13#flagr#flagr/antenna,new-source 2006.173.07:29:10.14:checkk5 2006.173.07:29:10.49/chk_autoobs//k5ts1/ autoobs is running! 2006.173.07:29:10.88/chk_autoobs//k5ts2/ autoobs is running! 2006.173.07:29:11.31/chk_autoobs//k5ts3/ autoobs is running! 2006.173.07:29:11.69/chk_autoobs//k5ts4/ autoobs is running! 2006.173.07:29:12.07/chk_obsdata//k5ts1/T1730727??a.dat file size is correct (nominal:360MB, actual:356MB). 2006.173.07:29:12.47/chk_obsdata//k5ts2/T1730727??b.dat file size is correct (nominal:360MB, actual:356MB). 2006.173.07:29:12.86/chk_obsdata//k5ts3/T1730727??c.dat file size is correct (nominal:360MB, actual:356MB). 2006.173.07:29:13.27/chk_obsdata//k5ts4/T1730727??d.dat file size is correct (nominal:360MB, actual:356MB). 2006.173.07:29:14.01/k5log//k5ts1_log_newline 2006.173.07:29:14.72/k5log//k5ts2_log_newline 2006.173.07:29:15.43/k5log//k5ts3_log_newline 2006.173.07:29:16.14/k5log//k5ts4_log_newline 2006.173.07:29:16.16/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.07:29:16.16:setupk4=1 2006.173.07:29:16.16$setupk4/echo=on 2006.173.07:29:16.16$setupk4/pcalon 2006.173.07:29:16.16$pcalon/"no phase cal control is implemented here 2006.173.07:29:16.16$setupk4/"tpicd=stop 2006.173.07:29:16.16$setupk4/"rec=synch_on 2006.173.07:29:16.16$setupk4/"rec_mode=128 2006.173.07:29:16.16$setupk4/!* 2006.173.07:29:16.16$setupk4/recpk4 2006.173.07:29:16.16$recpk4/recpatch= 2006.173.07:29:16.16$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.07:29:16.16$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.07:29:16.16$setupk4/vck44 2006.173.07:29:16.16$vck44/valo=1,524.99 2006.173.07:29:16.16#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.07:29:16.16#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.07:29:16.16#ibcon#ireg 17 cls_cnt 0 2006.173.07:29:16.16#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.07:29:16.16#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.07:29:16.16#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.07:29:16.16#ibcon#enter wrdev, iclass 13, count 0 2006.173.07:29:16.16#ibcon#first serial, iclass 13, count 0 2006.173.07:29:16.17#ibcon#enter sib2, iclass 13, count 0 2006.173.07:29:16.17#ibcon#flushed, iclass 13, count 0 2006.173.07:29:16.17#ibcon#about to write, iclass 13, count 0 2006.173.07:29:16.17#ibcon#wrote, iclass 13, count 0 2006.173.07:29:16.17#ibcon#about to read 3, iclass 13, count 0 2006.173.07:29:16.18#ibcon#read 3, iclass 13, count 0 2006.173.07:29:16.18#ibcon#about to read 4, iclass 13, count 0 2006.173.07:29:16.18#ibcon#read 4, iclass 13, count 0 2006.173.07:29:16.18#ibcon#about to read 5, iclass 13, count 0 2006.173.07:29:16.18#ibcon#read 5, iclass 13, count 0 2006.173.07:29:16.18#ibcon#about to read 6, iclass 13, count 0 2006.173.07:29:16.18#ibcon#read 6, iclass 13, count 0 2006.173.07:29:16.18#ibcon#end of sib2, iclass 13, count 0 2006.173.07:29:16.18#ibcon#*mode == 0, iclass 13, count 0 2006.173.07:29:16.18#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.07:29:16.18#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.07:29:16.18#ibcon#*before write, iclass 13, count 0 2006.173.07:29:16.18#ibcon#enter sib2, iclass 13, count 0 2006.173.07:29:16.18#ibcon#flushed, iclass 13, count 0 2006.173.07:29:16.18#ibcon#about to write, iclass 13, count 0 2006.173.07:29:16.18#ibcon#wrote, iclass 13, count 0 2006.173.07:29:16.18#ibcon#about to read 3, iclass 13, count 0 2006.173.07:29:16.23#ibcon#read 3, iclass 13, count 0 2006.173.07:29:16.23#ibcon#about to read 4, iclass 13, count 0 2006.173.07:29:16.23#ibcon#read 4, iclass 13, count 0 2006.173.07:29:16.23#ibcon#about to read 5, iclass 13, count 0 2006.173.07:29:16.23#ibcon#read 5, iclass 13, count 0 2006.173.07:29:16.23#ibcon#about to read 6, iclass 13, count 0 2006.173.07:29:16.23#ibcon#read 6, iclass 13, count 0 2006.173.07:29:16.23#ibcon#end of sib2, iclass 13, count 0 2006.173.07:29:16.23#ibcon#*after write, iclass 13, count 0 2006.173.07:29:16.23#ibcon#*before return 0, iclass 13, count 0 2006.173.07:29:16.23#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.07:29:16.23#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.07:29:16.23#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.07:29:16.23#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.07:29:16.23$vck44/va=1,7 2006.173.07:29:16.23#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.07:29:16.23#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.07:29:16.23#ibcon#ireg 11 cls_cnt 2 2006.173.07:29:16.23#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.07:29:16.23#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.07:29:16.23#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.07:29:16.23#ibcon#enter wrdev, iclass 15, count 2 2006.173.07:29:16.23#ibcon#first serial, iclass 15, count 2 2006.173.07:29:16.23#ibcon#enter sib2, iclass 15, count 2 2006.173.07:29:16.23#ibcon#flushed, iclass 15, count 2 2006.173.07:29:16.23#ibcon#about to write, iclass 15, count 2 2006.173.07:29:16.23#ibcon#wrote, iclass 15, count 2 2006.173.07:29:16.23#ibcon#about to read 3, iclass 15, count 2 2006.173.07:29:16.25#ibcon#read 3, iclass 15, count 2 2006.173.07:29:16.25#ibcon#about to read 4, iclass 15, count 2 2006.173.07:29:16.25#ibcon#read 4, iclass 15, count 2 2006.173.07:29:16.25#ibcon#about to read 5, iclass 15, count 2 2006.173.07:29:16.25#ibcon#read 5, iclass 15, count 2 2006.173.07:29:16.25#ibcon#about to read 6, iclass 15, count 2 2006.173.07:29:16.25#ibcon#read 6, iclass 15, count 2 2006.173.07:29:16.25#ibcon#end of sib2, iclass 15, count 2 2006.173.07:29:16.25#ibcon#*mode == 0, iclass 15, count 2 2006.173.07:29:16.25#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.07:29:16.25#ibcon#[25=AT01-07\r\n] 2006.173.07:29:16.25#ibcon#*before write, iclass 15, count 2 2006.173.07:29:16.25#ibcon#enter sib2, iclass 15, count 2 2006.173.07:29:16.25#ibcon#flushed, iclass 15, count 2 2006.173.07:29:16.25#ibcon#about to write, iclass 15, count 2 2006.173.07:29:16.25#ibcon#wrote, iclass 15, count 2 2006.173.07:29:16.25#ibcon#about to read 3, iclass 15, count 2 2006.173.07:29:16.28#ibcon#read 3, iclass 15, count 2 2006.173.07:29:16.28#ibcon#about to read 4, iclass 15, count 2 2006.173.07:29:16.28#ibcon#read 4, iclass 15, count 2 2006.173.07:29:16.28#ibcon#about to read 5, iclass 15, count 2 2006.173.07:29:16.28#ibcon#read 5, iclass 15, count 2 2006.173.07:29:16.28#ibcon#about to read 6, iclass 15, count 2 2006.173.07:29:16.28#ibcon#read 6, iclass 15, count 2 2006.173.07:29:16.28#ibcon#end of sib2, iclass 15, count 2 2006.173.07:29:16.28#ibcon#*after write, iclass 15, count 2 2006.173.07:29:16.28#ibcon#*before return 0, iclass 15, count 2 2006.173.07:29:16.28#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.07:29:16.28#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.07:29:16.28#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.07:29:16.28#ibcon#ireg 7 cls_cnt 0 2006.173.07:29:16.28#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.07:29:16.40#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.07:29:16.40#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.07:29:16.40#ibcon#enter wrdev, iclass 15, count 0 2006.173.07:29:16.40#ibcon#first serial, iclass 15, count 0 2006.173.07:29:16.40#ibcon#enter sib2, iclass 15, count 0 2006.173.07:29:16.40#ibcon#flushed, iclass 15, count 0 2006.173.07:29:16.40#ibcon#about to write, iclass 15, count 0 2006.173.07:29:16.40#ibcon#wrote, iclass 15, count 0 2006.173.07:29:16.40#ibcon#about to read 3, iclass 15, count 0 2006.173.07:29:16.42#ibcon#read 3, iclass 15, count 0 2006.173.07:29:16.42#ibcon#about to read 4, iclass 15, count 0 2006.173.07:29:16.42#ibcon#read 4, iclass 15, count 0 2006.173.07:29:16.42#ibcon#about to read 5, iclass 15, count 0 2006.173.07:29:16.42#ibcon#read 5, iclass 15, count 0 2006.173.07:29:16.42#ibcon#about to read 6, iclass 15, count 0 2006.173.07:29:16.42#ibcon#read 6, iclass 15, count 0 2006.173.07:29:16.42#ibcon#end of sib2, iclass 15, count 0 2006.173.07:29:16.42#ibcon#*mode == 0, iclass 15, count 0 2006.173.07:29:16.42#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.07:29:16.42#ibcon#[25=USB\r\n] 2006.173.07:29:16.42#ibcon#*before write, iclass 15, count 0 2006.173.07:29:16.42#ibcon#enter sib2, iclass 15, count 0 2006.173.07:29:16.42#ibcon#flushed, iclass 15, count 0 2006.173.07:29:16.42#ibcon#about to write, iclass 15, count 0 2006.173.07:29:16.42#ibcon#wrote, iclass 15, count 0 2006.173.07:29:16.42#ibcon#about to read 3, iclass 15, count 0 2006.173.07:29:16.45#ibcon#read 3, iclass 15, count 0 2006.173.07:29:16.45#ibcon#about to read 4, iclass 15, count 0 2006.173.07:29:16.45#ibcon#read 4, iclass 15, count 0 2006.173.07:29:16.45#ibcon#about to read 5, iclass 15, count 0 2006.173.07:29:16.45#ibcon#read 5, iclass 15, count 0 2006.173.07:29:16.45#ibcon#about to read 6, iclass 15, count 0 2006.173.07:29:16.45#ibcon#read 6, iclass 15, count 0 2006.173.07:29:16.45#ibcon#end of sib2, iclass 15, count 0 2006.173.07:29:16.45#ibcon#*after write, iclass 15, count 0 2006.173.07:29:16.45#ibcon#*before return 0, iclass 15, count 0 2006.173.07:29:16.45#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.07:29:16.45#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.07:29:16.45#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.07:29:16.45#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.07:29:16.45$vck44/valo=2,534.99 2006.173.07:29:16.45#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.07:29:16.45#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.07:29:16.45#ibcon#ireg 17 cls_cnt 0 2006.173.07:29:16.45#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.07:29:16.45#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.07:29:16.45#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.07:29:16.45#ibcon#enter wrdev, iclass 17, count 0 2006.173.07:29:16.45#ibcon#first serial, iclass 17, count 0 2006.173.07:29:16.45#ibcon#enter sib2, iclass 17, count 0 2006.173.07:29:16.45#ibcon#flushed, iclass 17, count 0 2006.173.07:29:16.45#ibcon#about to write, iclass 17, count 0 2006.173.07:29:16.45#ibcon#wrote, iclass 17, count 0 2006.173.07:29:16.45#ibcon#about to read 3, iclass 17, count 0 2006.173.07:29:16.47#ibcon#read 3, iclass 17, count 0 2006.173.07:29:16.47#ibcon#about to read 4, iclass 17, count 0 2006.173.07:29:16.47#ibcon#read 4, iclass 17, count 0 2006.173.07:29:16.47#ibcon#about to read 5, iclass 17, count 0 2006.173.07:29:16.47#ibcon#read 5, iclass 17, count 0 2006.173.07:29:16.47#ibcon#about to read 6, iclass 17, count 0 2006.173.07:29:16.47#ibcon#read 6, iclass 17, count 0 2006.173.07:29:16.47#ibcon#end of sib2, iclass 17, count 0 2006.173.07:29:16.47#ibcon#*mode == 0, iclass 17, count 0 2006.173.07:29:16.47#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.07:29:16.47#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.07:29:16.47#ibcon#*before write, iclass 17, count 0 2006.173.07:29:16.47#ibcon#enter sib2, iclass 17, count 0 2006.173.07:29:16.47#ibcon#flushed, iclass 17, count 0 2006.173.07:29:16.47#ibcon#about to write, iclass 17, count 0 2006.173.07:29:16.47#ibcon#wrote, iclass 17, count 0 2006.173.07:29:16.47#ibcon#about to read 3, iclass 17, count 0 2006.173.07:29:16.51#ibcon#read 3, iclass 17, count 0 2006.173.07:29:16.51#ibcon#about to read 4, iclass 17, count 0 2006.173.07:29:16.51#ibcon#read 4, iclass 17, count 0 2006.173.07:29:16.51#ibcon#about to read 5, iclass 17, count 0 2006.173.07:29:16.51#ibcon#read 5, iclass 17, count 0 2006.173.07:29:16.51#ibcon#about to read 6, iclass 17, count 0 2006.173.07:29:16.51#ibcon#read 6, iclass 17, count 0 2006.173.07:29:16.51#ibcon#end of sib2, iclass 17, count 0 2006.173.07:29:16.51#ibcon#*after write, iclass 17, count 0 2006.173.07:29:16.51#ibcon#*before return 0, iclass 17, count 0 2006.173.07:29:16.51#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.07:29:16.51#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.07:29:16.51#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.07:29:16.51#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.07:29:16.51$vck44/va=2,6 2006.173.07:29:16.51#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.07:29:16.51#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.07:29:16.51#ibcon#ireg 11 cls_cnt 2 2006.173.07:29:16.51#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.07:29:16.57#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.07:29:16.57#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.07:29:16.57#ibcon#enter wrdev, iclass 19, count 2 2006.173.07:29:16.57#ibcon#first serial, iclass 19, count 2 2006.173.07:29:16.57#ibcon#enter sib2, iclass 19, count 2 2006.173.07:29:16.57#ibcon#flushed, iclass 19, count 2 2006.173.07:29:16.57#ibcon#about to write, iclass 19, count 2 2006.173.07:29:16.57#ibcon#wrote, iclass 19, count 2 2006.173.07:29:16.57#ibcon#about to read 3, iclass 19, count 2 2006.173.07:29:16.59#ibcon#read 3, iclass 19, count 2 2006.173.07:29:16.59#ibcon#about to read 4, iclass 19, count 2 2006.173.07:29:16.59#ibcon#read 4, iclass 19, count 2 2006.173.07:29:16.59#ibcon#about to read 5, iclass 19, count 2 2006.173.07:29:16.59#ibcon#read 5, iclass 19, count 2 2006.173.07:29:16.59#ibcon#about to read 6, iclass 19, count 2 2006.173.07:29:16.59#ibcon#read 6, iclass 19, count 2 2006.173.07:29:16.59#ibcon#end of sib2, iclass 19, count 2 2006.173.07:29:16.59#ibcon#*mode == 0, iclass 19, count 2 2006.173.07:29:16.59#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.07:29:16.59#ibcon#[25=AT02-06\r\n] 2006.173.07:29:16.59#ibcon#*before write, iclass 19, count 2 2006.173.07:29:16.59#ibcon#enter sib2, iclass 19, count 2 2006.173.07:29:16.59#ibcon#flushed, iclass 19, count 2 2006.173.07:29:16.59#ibcon#about to write, iclass 19, count 2 2006.173.07:29:16.59#ibcon#wrote, iclass 19, count 2 2006.173.07:29:16.59#ibcon#about to read 3, iclass 19, count 2 2006.173.07:29:16.62#ibcon#read 3, iclass 19, count 2 2006.173.07:29:16.62#ibcon#about to read 4, iclass 19, count 2 2006.173.07:29:16.62#ibcon#read 4, iclass 19, count 2 2006.173.07:29:16.62#ibcon#about to read 5, iclass 19, count 2 2006.173.07:29:16.62#ibcon#read 5, iclass 19, count 2 2006.173.07:29:16.62#ibcon#about to read 6, iclass 19, count 2 2006.173.07:29:16.62#ibcon#read 6, iclass 19, count 2 2006.173.07:29:16.62#ibcon#end of sib2, iclass 19, count 2 2006.173.07:29:16.62#ibcon#*after write, iclass 19, count 2 2006.173.07:29:16.62#ibcon#*before return 0, iclass 19, count 2 2006.173.07:29:16.62#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.07:29:16.62#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.07:29:16.62#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.07:29:16.62#ibcon#ireg 7 cls_cnt 0 2006.173.07:29:16.62#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.07:29:16.74#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.07:29:16.74#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.07:29:16.74#ibcon#enter wrdev, iclass 19, count 0 2006.173.07:29:16.74#ibcon#first serial, iclass 19, count 0 2006.173.07:29:16.74#ibcon#enter sib2, iclass 19, count 0 2006.173.07:29:16.74#ibcon#flushed, iclass 19, count 0 2006.173.07:29:16.74#ibcon#about to write, iclass 19, count 0 2006.173.07:29:16.74#ibcon#wrote, iclass 19, count 0 2006.173.07:29:16.74#ibcon#about to read 3, iclass 19, count 0 2006.173.07:29:16.76#ibcon#read 3, iclass 19, count 0 2006.173.07:29:16.76#ibcon#about to read 4, iclass 19, count 0 2006.173.07:29:16.76#ibcon#read 4, iclass 19, count 0 2006.173.07:29:16.76#ibcon#about to read 5, iclass 19, count 0 2006.173.07:29:16.76#ibcon#read 5, iclass 19, count 0 2006.173.07:29:16.76#ibcon#about to read 6, iclass 19, count 0 2006.173.07:29:16.76#ibcon#read 6, iclass 19, count 0 2006.173.07:29:16.76#ibcon#end of sib2, iclass 19, count 0 2006.173.07:29:16.76#ibcon#*mode == 0, iclass 19, count 0 2006.173.07:29:16.76#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.07:29:16.76#ibcon#[25=USB\r\n] 2006.173.07:29:16.76#ibcon#*before write, iclass 19, count 0 2006.173.07:29:16.76#ibcon#enter sib2, iclass 19, count 0 2006.173.07:29:16.76#ibcon#flushed, iclass 19, count 0 2006.173.07:29:16.76#ibcon#about to write, iclass 19, count 0 2006.173.07:29:16.76#ibcon#wrote, iclass 19, count 0 2006.173.07:29:16.76#ibcon#about to read 3, iclass 19, count 0 2006.173.07:29:16.79#ibcon#read 3, iclass 19, count 0 2006.173.07:29:16.79#ibcon#about to read 4, iclass 19, count 0 2006.173.07:29:16.79#ibcon#read 4, iclass 19, count 0 2006.173.07:29:16.79#ibcon#about to read 5, iclass 19, count 0 2006.173.07:29:16.79#ibcon#read 5, iclass 19, count 0 2006.173.07:29:16.79#ibcon#about to read 6, iclass 19, count 0 2006.173.07:29:16.79#ibcon#read 6, iclass 19, count 0 2006.173.07:29:16.79#ibcon#end of sib2, iclass 19, count 0 2006.173.07:29:16.79#ibcon#*after write, iclass 19, count 0 2006.173.07:29:16.79#ibcon#*before return 0, iclass 19, count 0 2006.173.07:29:16.79#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.07:29:16.79#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.07:29:16.79#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.07:29:16.79#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.07:29:16.79$vck44/valo=3,564.99 2006.173.07:29:16.79#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.07:29:16.79#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.07:29:16.79#ibcon#ireg 17 cls_cnt 0 2006.173.07:29:16.79#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.07:29:16.79#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.07:29:16.79#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.07:29:16.79#ibcon#enter wrdev, iclass 21, count 0 2006.173.07:29:16.79#ibcon#first serial, iclass 21, count 0 2006.173.07:29:16.79#ibcon#enter sib2, iclass 21, count 0 2006.173.07:29:16.79#ibcon#flushed, iclass 21, count 0 2006.173.07:29:16.79#ibcon#about to write, iclass 21, count 0 2006.173.07:29:16.79#ibcon#wrote, iclass 21, count 0 2006.173.07:29:16.79#ibcon#about to read 3, iclass 21, count 0 2006.173.07:29:16.81#ibcon#read 3, iclass 21, count 0 2006.173.07:29:16.81#ibcon#about to read 4, iclass 21, count 0 2006.173.07:29:16.81#ibcon#read 4, iclass 21, count 0 2006.173.07:29:16.81#ibcon#about to read 5, iclass 21, count 0 2006.173.07:29:16.81#ibcon#read 5, iclass 21, count 0 2006.173.07:29:16.81#ibcon#about to read 6, iclass 21, count 0 2006.173.07:29:16.81#ibcon#read 6, iclass 21, count 0 2006.173.07:29:16.81#ibcon#end of sib2, iclass 21, count 0 2006.173.07:29:16.81#ibcon#*mode == 0, iclass 21, count 0 2006.173.07:29:16.81#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.07:29:16.81#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.07:29:16.81#ibcon#*before write, iclass 21, count 0 2006.173.07:29:16.81#ibcon#enter sib2, iclass 21, count 0 2006.173.07:29:16.81#ibcon#flushed, iclass 21, count 0 2006.173.07:29:16.81#ibcon#about to write, iclass 21, count 0 2006.173.07:29:16.81#ibcon#wrote, iclass 21, count 0 2006.173.07:29:16.81#ibcon#about to read 3, iclass 21, count 0 2006.173.07:29:16.85#ibcon#read 3, iclass 21, count 0 2006.173.07:29:16.85#ibcon#about to read 4, iclass 21, count 0 2006.173.07:29:16.85#ibcon#read 4, iclass 21, count 0 2006.173.07:29:16.85#ibcon#about to read 5, iclass 21, count 0 2006.173.07:29:16.85#ibcon#read 5, iclass 21, count 0 2006.173.07:29:16.85#ibcon#about to read 6, iclass 21, count 0 2006.173.07:29:16.85#ibcon#read 6, iclass 21, count 0 2006.173.07:29:16.85#ibcon#end of sib2, iclass 21, count 0 2006.173.07:29:16.85#ibcon#*after write, iclass 21, count 0 2006.173.07:29:16.85#ibcon#*before return 0, iclass 21, count 0 2006.173.07:29:16.85#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.07:29:16.85#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.07:29:16.85#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.07:29:16.85#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.07:29:16.85$vck44/va=3,5 2006.173.07:29:16.85#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.07:29:16.85#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.07:29:16.85#ibcon#ireg 11 cls_cnt 2 2006.173.07:29:16.85#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.07:29:16.91#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.07:29:16.91#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.07:29:16.91#ibcon#enter wrdev, iclass 23, count 2 2006.173.07:29:16.91#ibcon#first serial, iclass 23, count 2 2006.173.07:29:16.91#ibcon#enter sib2, iclass 23, count 2 2006.173.07:29:16.91#ibcon#flushed, iclass 23, count 2 2006.173.07:29:16.91#ibcon#about to write, iclass 23, count 2 2006.173.07:29:16.91#ibcon#wrote, iclass 23, count 2 2006.173.07:29:16.91#ibcon#about to read 3, iclass 23, count 2 2006.173.07:29:16.93#ibcon#read 3, iclass 23, count 2 2006.173.07:29:16.93#ibcon#about to read 4, iclass 23, count 2 2006.173.07:29:16.93#ibcon#read 4, iclass 23, count 2 2006.173.07:29:16.93#ibcon#about to read 5, iclass 23, count 2 2006.173.07:29:16.93#ibcon#read 5, iclass 23, count 2 2006.173.07:29:16.93#ibcon#about to read 6, iclass 23, count 2 2006.173.07:29:16.93#ibcon#read 6, iclass 23, count 2 2006.173.07:29:16.93#ibcon#end of sib2, iclass 23, count 2 2006.173.07:29:16.93#ibcon#*mode == 0, iclass 23, count 2 2006.173.07:29:16.93#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.07:29:16.93#ibcon#[25=AT03-05\r\n] 2006.173.07:29:16.93#ibcon#*before write, iclass 23, count 2 2006.173.07:29:16.93#ibcon#enter sib2, iclass 23, count 2 2006.173.07:29:16.93#ibcon#flushed, iclass 23, count 2 2006.173.07:29:16.93#ibcon#about to write, iclass 23, count 2 2006.173.07:29:16.93#ibcon#wrote, iclass 23, count 2 2006.173.07:29:16.93#ibcon#about to read 3, iclass 23, count 2 2006.173.07:29:16.96#ibcon#read 3, iclass 23, count 2 2006.173.07:29:16.96#ibcon#about to read 4, iclass 23, count 2 2006.173.07:29:16.96#ibcon#read 4, iclass 23, count 2 2006.173.07:29:16.96#ibcon#about to read 5, iclass 23, count 2 2006.173.07:29:16.96#ibcon#read 5, iclass 23, count 2 2006.173.07:29:16.96#ibcon#about to read 6, iclass 23, count 2 2006.173.07:29:16.96#ibcon#read 6, iclass 23, count 2 2006.173.07:29:16.96#ibcon#end of sib2, iclass 23, count 2 2006.173.07:29:16.96#ibcon#*after write, iclass 23, count 2 2006.173.07:29:16.96#ibcon#*before return 0, iclass 23, count 2 2006.173.07:29:16.96#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.07:29:16.96#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.07:29:16.96#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.07:29:16.96#ibcon#ireg 7 cls_cnt 0 2006.173.07:29:16.96#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.07:29:17.08#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.07:29:17.08#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.07:29:17.08#ibcon#enter wrdev, iclass 23, count 0 2006.173.07:29:17.08#ibcon#first serial, iclass 23, count 0 2006.173.07:29:17.08#ibcon#enter sib2, iclass 23, count 0 2006.173.07:29:17.08#ibcon#flushed, iclass 23, count 0 2006.173.07:29:17.08#ibcon#about to write, iclass 23, count 0 2006.173.07:29:17.08#ibcon#wrote, iclass 23, count 0 2006.173.07:29:17.08#ibcon#about to read 3, iclass 23, count 0 2006.173.07:29:17.10#ibcon#read 3, iclass 23, count 0 2006.173.07:29:17.10#ibcon#about to read 4, iclass 23, count 0 2006.173.07:29:17.10#ibcon#read 4, iclass 23, count 0 2006.173.07:29:17.10#ibcon#about to read 5, iclass 23, count 0 2006.173.07:29:17.10#ibcon#read 5, iclass 23, count 0 2006.173.07:29:17.10#ibcon#about to read 6, iclass 23, count 0 2006.173.07:29:17.10#ibcon#read 6, iclass 23, count 0 2006.173.07:29:17.10#ibcon#end of sib2, iclass 23, count 0 2006.173.07:29:17.10#ibcon#*mode == 0, iclass 23, count 0 2006.173.07:29:17.10#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.07:29:17.10#ibcon#[25=USB\r\n] 2006.173.07:29:17.10#ibcon#*before write, iclass 23, count 0 2006.173.07:29:17.10#ibcon#enter sib2, iclass 23, count 0 2006.173.07:29:17.10#ibcon#flushed, iclass 23, count 0 2006.173.07:29:17.10#ibcon#about to write, iclass 23, count 0 2006.173.07:29:17.10#ibcon#wrote, iclass 23, count 0 2006.173.07:29:17.10#ibcon#about to read 3, iclass 23, count 0 2006.173.07:29:17.13#ibcon#read 3, iclass 23, count 0 2006.173.07:29:17.13#ibcon#about to read 4, iclass 23, count 0 2006.173.07:29:17.13#ibcon#read 4, iclass 23, count 0 2006.173.07:29:17.13#ibcon#about to read 5, iclass 23, count 0 2006.173.07:29:17.13#ibcon#read 5, iclass 23, count 0 2006.173.07:29:17.13#ibcon#about to read 6, iclass 23, count 0 2006.173.07:29:17.13#ibcon#read 6, iclass 23, count 0 2006.173.07:29:17.13#ibcon#end of sib2, iclass 23, count 0 2006.173.07:29:17.13#ibcon#*after write, iclass 23, count 0 2006.173.07:29:17.13#ibcon#*before return 0, iclass 23, count 0 2006.173.07:29:17.13#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.07:29:17.13#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.07:29:17.13#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.07:29:17.13#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.07:29:17.13$vck44/valo=4,624.99 2006.173.07:29:17.13#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.07:29:17.13#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.07:29:17.13#ibcon#ireg 17 cls_cnt 0 2006.173.07:29:17.13#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.07:29:17.13#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.07:29:17.13#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.07:29:17.13#ibcon#enter wrdev, iclass 25, count 0 2006.173.07:29:17.13#ibcon#first serial, iclass 25, count 0 2006.173.07:29:17.13#ibcon#enter sib2, iclass 25, count 0 2006.173.07:29:17.13#ibcon#flushed, iclass 25, count 0 2006.173.07:29:17.13#ibcon#about to write, iclass 25, count 0 2006.173.07:29:17.13#ibcon#wrote, iclass 25, count 0 2006.173.07:29:17.13#ibcon#about to read 3, iclass 25, count 0 2006.173.07:29:17.15#ibcon#read 3, iclass 25, count 0 2006.173.07:29:17.15#ibcon#about to read 4, iclass 25, count 0 2006.173.07:29:17.15#ibcon#read 4, iclass 25, count 0 2006.173.07:29:17.15#ibcon#about to read 5, iclass 25, count 0 2006.173.07:29:17.15#ibcon#read 5, iclass 25, count 0 2006.173.07:29:17.15#ibcon#about to read 6, iclass 25, count 0 2006.173.07:29:17.15#ibcon#read 6, iclass 25, count 0 2006.173.07:29:17.15#ibcon#end of sib2, iclass 25, count 0 2006.173.07:29:17.15#ibcon#*mode == 0, iclass 25, count 0 2006.173.07:29:17.15#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.07:29:17.15#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.07:29:17.15#ibcon#*before write, iclass 25, count 0 2006.173.07:29:17.15#ibcon#enter sib2, iclass 25, count 0 2006.173.07:29:17.15#ibcon#flushed, iclass 25, count 0 2006.173.07:29:17.15#ibcon#about to write, iclass 25, count 0 2006.173.07:29:17.15#ibcon#wrote, iclass 25, count 0 2006.173.07:29:17.15#ibcon#about to read 3, iclass 25, count 0 2006.173.07:29:17.19#ibcon#read 3, iclass 25, count 0 2006.173.07:29:17.19#ibcon#about to read 4, iclass 25, count 0 2006.173.07:29:17.19#ibcon#read 4, iclass 25, count 0 2006.173.07:29:17.19#ibcon#about to read 5, iclass 25, count 0 2006.173.07:29:17.19#ibcon#read 5, iclass 25, count 0 2006.173.07:29:17.19#ibcon#about to read 6, iclass 25, count 0 2006.173.07:29:17.19#ibcon#read 6, iclass 25, count 0 2006.173.07:29:17.19#ibcon#end of sib2, iclass 25, count 0 2006.173.07:29:17.19#ibcon#*after write, iclass 25, count 0 2006.173.07:29:17.19#ibcon#*before return 0, iclass 25, count 0 2006.173.07:29:17.19#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.07:29:17.19#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.07:29:17.19#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.07:29:17.19#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.07:29:17.19$vck44/va=4,6 2006.173.07:29:17.19#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.07:29:17.19#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.07:29:17.19#ibcon#ireg 11 cls_cnt 2 2006.173.07:29:17.19#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.07:29:17.25#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.07:29:17.25#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.07:29:17.25#ibcon#enter wrdev, iclass 27, count 2 2006.173.07:29:17.25#ibcon#first serial, iclass 27, count 2 2006.173.07:29:17.25#ibcon#enter sib2, iclass 27, count 2 2006.173.07:29:17.25#ibcon#flushed, iclass 27, count 2 2006.173.07:29:17.25#ibcon#about to write, iclass 27, count 2 2006.173.07:29:17.25#ibcon#wrote, iclass 27, count 2 2006.173.07:29:17.25#ibcon#about to read 3, iclass 27, count 2 2006.173.07:29:17.27#ibcon#read 3, iclass 27, count 2 2006.173.07:29:17.27#ibcon#about to read 4, iclass 27, count 2 2006.173.07:29:17.27#ibcon#read 4, iclass 27, count 2 2006.173.07:29:17.27#ibcon#about to read 5, iclass 27, count 2 2006.173.07:29:17.27#ibcon#read 5, iclass 27, count 2 2006.173.07:29:17.27#ibcon#about to read 6, iclass 27, count 2 2006.173.07:29:17.27#ibcon#read 6, iclass 27, count 2 2006.173.07:29:17.27#ibcon#end of sib2, iclass 27, count 2 2006.173.07:29:17.27#ibcon#*mode == 0, iclass 27, count 2 2006.173.07:29:17.27#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.07:29:17.27#ibcon#[25=AT04-06\r\n] 2006.173.07:29:17.27#ibcon#*before write, iclass 27, count 2 2006.173.07:29:17.27#ibcon#enter sib2, iclass 27, count 2 2006.173.07:29:17.27#ibcon#flushed, iclass 27, count 2 2006.173.07:29:17.27#ibcon#about to write, iclass 27, count 2 2006.173.07:29:17.27#ibcon#wrote, iclass 27, count 2 2006.173.07:29:17.27#ibcon#about to read 3, iclass 27, count 2 2006.173.07:29:17.30#ibcon#read 3, iclass 27, count 2 2006.173.07:29:17.30#ibcon#about to read 4, iclass 27, count 2 2006.173.07:29:17.30#ibcon#read 4, iclass 27, count 2 2006.173.07:29:17.30#ibcon#about to read 5, iclass 27, count 2 2006.173.07:29:17.30#ibcon#read 5, iclass 27, count 2 2006.173.07:29:17.30#ibcon#about to read 6, iclass 27, count 2 2006.173.07:29:17.30#ibcon#read 6, iclass 27, count 2 2006.173.07:29:17.30#ibcon#end of sib2, iclass 27, count 2 2006.173.07:29:17.30#ibcon#*after write, iclass 27, count 2 2006.173.07:29:17.30#ibcon#*before return 0, iclass 27, count 2 2006.173.07:29:17.30#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.07:29:17.30#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.07:29:17.30#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.07:29:17.30#ibcon#ireg 7 cls_cnt 0 2006.173.07:29:17.30#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.07:29:17.42#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.07:29:17.42#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.07:29:17.42#ibcon#enter wrdev, iclass 27, count 0 2006.173.07:29:17.42#ibcon#first serial, iclass 27, count 0 2006.173.07:29:17.42#ibcon#enter sib2, iclass 27, count 0 2006.173.07:29:17.42#ibcon#flushed, iclass 27, count 0 2006.173.07:29:17.42#ibcon#about to write, iclass 27, count 0 2006.173.07:29:17.42#ibcon#wrote, iclass 27, count 0 2006.173.07:29:17.42#ibcon#about to read 3, iclass 27, count 0 2006.173.07:29:17.44#ibcon#read 3, iclass 27, count 0 2006.173.07:29:17.44#ibcon#about to read 4, iclass 27, count 0 2006.173.07:29:17.44#ibcon#read 4, iclass 27, count 0 2006.173.07:29:17.44#ibcon#about to read 5, iclass 27, count 0 2006.173.07:29:17.44#ibcon#read 5, iclass 27, count 0 2006.173.07:29:17.44#ibcon#about to read 6, iclass 27, count 0 2006.173.07:29:17.44#ibcon#read 6, iclass 27, count 0 2006.173.07:29:17.44#ibcon#end of sib2, iclass 27, count 0 2006.173.07:29:17.44#ibcon#*mode == 0, iclass 27, count 0 2006.173.07:29:17.44#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.07:29:17.44#ibcon#[25=USB\r\n] 2006.173.07:29:17.44#ibcon#*before write, iclass 27, count 0 2006.173.07:29:17.44#ibcon#enter sib2, iclass 27, count 0 2006.173.07:29:17.44#ibcon#flushed, iclass 27, count 0 2006.173.07:29:17.44#ibcon#about to write, iclass 27, count 0 2006.173.07:29:17.44#ibcon#wrote, iclass 27, count 0 2006.173.07:29:17.44#ibcon#about to read 3, iclass 27, count 0 2006.173.07:29:17.47#ibcon#read 3, iclass 27, count 0 2006.173.07:29:17.47#ibcon#about to read 4, iclass 27, count 0 2006.173.07:29:17.47#ibcon#read 4, iclass 27, count 0 2006.173.07:29:17.47#ibcon#about to read 5, iclass 27, count 0 2006.173.07:29:17.47#ibcon#read 5, iclass 27, count 0 2006.173.07:29:17.47#ibcon#about to read 6, iclass 27, count 0 2006.173.07:29:17.47#ibcon#read 6, iclass 27, count 0 2006.173.07:29:17.47#ibcon#end of sib2, iclass 27, count 0 2006.173.07:29:17.47#ibcon#*after write, iclass 27, count 0 2006.173.07:29:17.47#ibcon#*before return 0, iclass 27, count 0 2006.173.07:29:17.47#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.07:29:17.47#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.07:29:17.47#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.07:29:17.47#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.07:29:17.47$vck44/valo=5,734.99 2006.173.07:29:17.47#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.07:29:17.47#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.07:29:17.47#ibcon#ireg 17 cls_cnt 0 2006.173.07:29:17.47#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.07:29:17.47#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.07:29:17.47#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.07:29:17.47#ibcon#enter wrdev, iclass 29, count 0 2006.173.07:29:17.47#ibcon#first serial, iclass 29, count 0 2006.173.07:29:17.47#ibcon#enter sib2, iclass 29, count 0 2006.173.07:29:17.47#ibcon#flushed, iclass 29, count 0 2006.173.07:29:17.47#ibcon#about to write, iclass 29, count 0 2006.173.07:29:17.47#ibcon#wrote, iclass 29, count 0 2006.173.07:29:17.47#ibcon#about to read 3, iclass 29, count 0 2006.173.07:29:17.49#ibcon#read 3, iclass 29, count 0 2006.173.07:29:17.49#ibcon#about to read 4, iclass 29, count 0 2006.173.07:29:17.49#ibcon#read 4, iclass 29, count 0 2006.173.07:29:17.49#ibcon#about to read 5, iclass 29, count 0 2006.173.07:29:17.49#ibcon#read 5, iclass 29, count 0 2006.173.07:29:17.49#ibcon#about to read 6, iclass 29, count 0 2006.173.07:29:17.49#ibcon#read 6, iclass 29, count 0 2006.173.07:29:17.49#ibcon#end of sib2, iclass 29, count 0 2006.173.07:29:17.49#ibcon#*mode == 0, iclass 29, count 0 2006.173.07:29:17.49#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.07:29:17.49#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.07:29:17.49#ibcon#*before write, iclass 29, count 0 2006.173.07:29:17.49#ibcon#enter sib2, iclass 29, count 0 2006.173.07:29:17.49#ibcon#flushed, iclass 29, count 0 2006.173.07:29:17.49#ibcon#about to write, iclass 29, count 0 2006.173.07:29:17.49#ibcon#wrote, iclass 29, count 0 2006.173.07:29:17.49#ibcon#about to read 3, iclass 29, count 0 2006.173.07:29:17.53#ibcon#read 3, iclass 29, count 0 2006.173.07:29:17.53#ibcon#about to read 4, iclass 29, count 0 2006.173.07:29:17.53#ibcon#read 4, iclass 29, count 0 2006.173.07:29:17.53#ibcon#about to read 5, iclass 29, count 0 2006.173.07:29:17.53#ibcon#read 5, iclass 29, count 0 2006.173.07:29:17.53#ibcon#about to read 6, iclass 29, count 0 2006.173.07:29:17.53#ibcon#read 6, iclass 29, count 0 2006.173.07:29:17.53#ibcon#end of sib2, iclass 29, count 0 2006.173.07:29:17.53#ibcon#*after write, iclass 29, count 0 2006.173.07:29:17.53#ibcon#*before return 0, iclass 29, count 0 2006.173.07:29:17.53#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.07:29:17.53#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.07:29:17.53#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.07:29:17.53#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.07:29:17.53$vck44/va=5,4 2006.173.07:29:17.53#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.07:29:17.53#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.07:29:17.53#ibcon#ireg 11 cls_cnt 2 2006.173.07:29:17.53#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.07:29:17.59#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.07:29:17.59#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.07:29:17.59#ibcon#enter wrdev, iclass 31, count 2 2006.173.07:29:17.59#ibcon#first serial, iclass 31, count 2 2006.173.07:29:17.59#ibcon#enter sib2, iclass 31, count 2 2006.173.07:29:17.59#ibcon#flushed, iclass 31, count 2 2006.173.07:29:17.59#ibcon#about to write, iclass 31, count 2 2006.173.07:29:17.59#ibcon#wrote, iclass 31, count 2 2006.173.07:29:17.59#ibcon#about to read 3, iclass 31, count 2 2006.173.07:29:17.61#ibcon#read 3, iclass 31, count 2 2006.173.07:29:17.61#ibcon#about to read 4, iclass 31, count 2 2006.173.07:29:17.61#ibcon#read 4, iclass 31, count 2 2006.173.07:29:17.61#ibcon#about to read 5, iclass 31, count 2 2006.173.07:29:17.61#ibcon#read 5, iclass 31, count 2 2006.173.07:29:17.61#ibcon#about to read 6, iclass 31, count 2 2006.173.07:29:17.61#ibcon#read 6, iclass 31, count 2 2006.173.07:29:17.61#ibcon#end of sib2, iclass 31, count 2 2006.173.07:29:17.61#ibcon#*mode == 0, iclass 31, count 2 2006.173.07:29:17.61#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.07:29:17.61#ibcon#[25=AT05-04\r\n] 2006.173.07:29:17.61#ibcon#*before write, iclass 31, count 2 2006.173.07:29:17.61#ibcon#enter sib2, iclass 31, count 2 2006.173.07:29:17.61#ibcon#flushed, iclass 31, count 2 2006.173.07:29:17.61#ibcon#about to write, iclass 31, count 2 2006.173.07:29:17.61#ibcon#wrote, iclass 31, count 2 2006.173.07:29:17.61#ibcon#about to read 3, iclass 31, count 2 2006.173.07:29:17.64#ibcon#read 3, iclass 31, count 2 2006.173.07:29:17.64#ibcon#about to read 4, iclass 31, count 2 2006.173.07:29:17.64#ibcon#read 4, iclass 31, count 2 2006.173.07:29:17.64#ibcon#about to read 5, iclass 31, count 2 2006.173.07:29:17.64#ibcon#read 5, iclass 31, count 2 2006.173.07:29:17.64#ibcon#about to read 6, iclass 31, count 2 2006.173.07:29:17.64#ibcon#read 6, iclass 31, count 2 2006.173.07:29:17.64#ibcon#end of sib2, iclass 31, count 2 2006.173.07:29:17.64#ibcon#*after write, iclass 31, count 2 2006.173.07:29:17.64#ibcon#*before return 0, iclass 31, count 2 2006.173.07:29:17.64#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.07:29:17.64#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.07:29:17.64#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.07:29:17.64#ibcon#ireg 7 cls_cnt 0 2006.173.07:29:17.64#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.07:29:17.76#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.07:29:17.76#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.07:29:17.76#ibcon#enter wrdev, iclass 31, count 0 2006.173.07:29:17.76#ibcon#first serial, iclass 31, count 0 2006.173.07:29:17.76#ibcon#enter sib2, iclass 31, count 0 2006.173.07:29:17.76#ibcon#flushed, iclass 31, count 0 2006.173.07:29:17.76#ibcon#about to write, iclass 31, count 0 2006.173.07:29:17.76#ibcon#wrote, iclass 31, count 0 2006.173.07:29:17.76#ibcon#about to read 3, iclass 31, count 0 2006.173.07:29:17.78#ibcon#read 3, iclass 31, count 0 2006.173.07:29:17.78#ibcon#about to read 4, iclass 31, count 0 2006.173.07:29:17.78#ibcon#read 4, iclass 31, count 0 2006.173.07:29:17.78#ibcon#about to read 5, iclass 31, count 0 2006.173.07:29:17.78#ibcon#read 5, iclass 31, count 0 2006.173.07:29:17.78#ibcon#about to read 6, iclass 31, count 0 2006.173.07:29:17.78#ibcon#read 6, iclass 31, count 0 2006.173.07:29:17.78#ibcon#end of sib2, iclass 31, count 0 2006.173.07:29:17.78#ibcon#*mode == 0, iclass 31, count 0 2006.173.07:29:17.78#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.07:29:17.78#ibcon#[25=USB\r\n] 2006.173.07:29:17.78#ibcon#*before write, iclass 31, count 0 2006.173.07:29:17.78#ibcon#enter sib2, iclass 31, count 0 2006.173.07:29:17.78#ibcon#flushed, iclass 31, count 0 2006.173.07:29:17.78#ibcon#about to write, iclass 31, count 0 2006.173.07:29:17.78#ibcon#wrote, iclass 31, count 0 2006.173.07:29:17.78#ibcon#about to read 3, iclass 31, count 0 2006.173.07:29:17.81#ibcon#read 3, iclass 31, count 0 2006.173.07:29:17.81#ibcon#about to read 4, iclass 31, count 0 2006.173.07:29:17.81#ibcon#read 4, iclass 31, count 0 2006.173.07:29:17.81#ibcon#about to read 5, iclass 31, count 0 2006.173.07:29:17.81#ibcon#read 5, iclass 31, count 0 2006.173.07:29:17.81#ibcon#about to read 6, iclass 31, count 0 2006.173.07:29:17.81#ibcon#read 6, iclass 31, count 0 2006.173.07:29:17.81#ibcon#end of sib2, iclass 31, count 0 2006.173.07:29:17.81#ibcon#*after write, iclass 31, count 0 2006.173.07:29:17.81#ibcon#*before return 0, iclass 31, count 0 2006.173.07:29:17.81#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.07:29:17.81#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.07:29:17.81#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.07:29:17.81#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.07:29:17.81$vck44/valo=6,814.99 2006.173.07:29:17.81#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.07:29:17.81#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.07:29:17.81#ibcon#ireg 17 cls_cnt 0 2006.173.07:29:17.81#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.07:29:17.81#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.07:29:17.81#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.07:29:17.81#ibcon#enter wrdev, iclass 33, count 0 2006.173.07:29:17.81#ibcon#first serial, iclass 33, count 0 2006.173.07:29:17.81#ibcon#enter sib2, iclass 33, count 0 2006.173.07:29:17.81#ibcon#flushed, iclass 33, count 0 2006.173.07:29:17.81#ibcon#about to write, iclass 33, count 0 2006.173.07:29:17.81#ibcon#wrote, iclass 33, count 0 2006.173.07:29:17.81#ibcon#about to read 3, iclass 33, count 0 2006.173.07:29:17.83#ibcon#read 3, iclass 33, count 0 2006.173.07:29:17.83#ibcon#about to read 4, iclass 33, count 0 2006.173.07:29:17.83#ibcon#read 4, iclass 33, count 0 2006.173.07:29:17.83#ibcon#about to read 5, iclass 33, count 0 2006.173.07:29:17.83#ibcon#read 5, iclass 33, count 0 2006.173.07:29:17.83#ibcon#about to read 6, iclass 33, count 0 2006.173.07:29:17.83#ibcon#read 6, iclass 33, count 0 2006.173.07:29:17.83#ibcon#end of sib2, iclass 33, count 0 2006.173.07:29:17.83#ibcon#*mode == 0, iclass 33, count 0 2006.173.07:29:17.83#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.07:29:17.83#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.07:29:17.83#ibcon#*before write, iclass 33, count 0 2006.173.07:29:17.83#ibcon#enter sib2, iclass 33, count 0 2006.173.07:29:17.83#ibcon#flushed, iclass 33, count 0 2006.173.07:29:17.83#ibcon#about to write, iclass 33, count 0 2006.173.07:29:17.83#ibcon#wrote, iclass 33, count 0 2006.173.07:29:17.83#ibcon#about to read 3, iclass 33, count 0 2006.173.07:29:17.87#ibcon#read 3, iclass 33, count 0 2006.173.07:29:17.87#ibcon#about to read 4, iclass 33, count 0 2006.173.07:29:17.87#ibcon#read 4, iclass 33, count 0 2006.173.07:29:17.87#ibcon#about to read 5, iclass 33, count 0 2006.173.07:29:17.87#ibcon#read 5, iclass 33, count 0 2006.173.07:29:17.87#ibcon#about to read 6, iclass 33, count 0 2006.173.07:29:17.87#ibcon#read 6, iclass 33, count 0 2006.173.07:29:17.87#ibcon#end of sib2, iclass 33, count 0 2006.173.07:29:17.87#ibcon#*after write, iclass 33, count 0 2006.173.07:29:17.87#ibcon#*before return 0, iclass 33, count 0 2006.173.07:29:17.87#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.07:29:17.87#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.07:29:17.87#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.07:29:17.87#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.07:29:17.87$vck44/va=6,3 2006.173.07:29:17.87#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.07:29:17.87#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.07:29:17.87#ibcon#ireg 11 cls_cnt 2 2006.173.07:29:17.87#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.07:29:17.93#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.07:29:17.93#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.07:29:17.93#ibcon#enter wrdev, iclass 35, count 2 2006.173.07:29:17.93#ibcon#first serial, iclass 35, count 2 2006.173.07:29:17.93#ibcon#enter sib2, iclass 35, count 2 2006.173.07:29:17.93#ibcon#flushed, iclass 35, count 2 2006.173.07:29:17.93#ibcon#about to write, iclass 35, count 2 2006.173.07:29:17.93#ibcon#wrote, iclass 35, count 2 2006.173.07:29:17.93#ibcon#about to read 3, iclass 35, count 2 2006.173.07:29:17.95#ibcon#read 3, iclass 35, count 2 2006.173.07:29:17.95#ibcon#about to read 4, iclass 35, count 2 2006.173.07:29:17.95#ibcon#read 4, iclass 35, count 2 2006.173.07:29:17.95#ibcon#about to read 5, iclass 35, count 2 2006.173.07:29:17.95#ibcon#read 5, iclass 35, count 2 2006.173.07:29:17.95#ibcon#about to read 6, iclass 35, count 2 2006.173.07:29:17.95#ibcon#read 6, iclass 35, count 2 2006.173.07:29:17.95#ibcon#end of sib2, iclass 35, count 2 2006.173.07:29:17.95#ibcon#*mode == 0, iclass 35, count 2 2006.173.07:29:17.95#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.07:29:17.95#ibcon#[25=AT06-03\r\n] 2006.173.07:29:17.95#ibcon#*before write, iclass 35, count 2 2006.173.07:29:17.95#ibcon#enter sib2, iclass 35, count 2 2006.173.07:29:17.95#ibcon#flushed, iclass 35, count 2 2006.173.07:29:17.95#ibcon#about to write, iclass 35, count 2 2006.173.07:29:17.95#ibcon#wrote, iclass 35, count 2 2006.173.07:29:17.95#ibcon#about to read 3, iclass 35, count 2 2006.173.07:29:17.98#ibcon#read 3, iclass 35, count 2 2006.173.07:29:17.98#ibcon#about to read 4, iclass 35, count 2 2006.173.07:29:17.98#ibcon#read 4, iclass 35, count 2 2006.173.07:29:17.98#ibcon#about to read 5, iclass 35, count 2 2006.173.07:29:17.98#ibcon#read 5, iclass 35, count 2 2006.173.07:29:17.98#ibcon#about to read 6, iclass 35, count 2 2006.173.07:29:17.98#ibcon#read 6, iclass 35, count 2 2006.173.07:29:17.98#ibcon#end of sib2, iclass 35, count 2 2006.173.07:29:17.98#ibcon#*after write, iclass 35, count 2 2006.173.07:29:17.98#ibcon#*before return 0, iclass 35, count 2 2006.173.07:29:17.98#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.07:29:17.98#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.07:29:17.98#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.07:29:17.98#ibcon#ireg 7 cls_cnt 0 2006.173.07:29:17.98#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.07:29:18.10#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.07:29:18.10#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.07:29:18.10#ibcon#enter wrdev, iclass 35, count 0 2006.173.07:29:18.10#ibcon#first serial, iclass 35, count 0 2006.173.07:29:18.10#ibcon#enter sib2, iclass 35, count 0 2006.173.07:29:18.10#ibcon#flushed, iclass 35, count 0 2006.173.07:29:18.10#ibcon#about to write, iclass 35, count 0 2006.173.07:29:18.10#ibcon#wrote, iclass 35, count 0 2006.173.07:29:18.10#ibcon#about to read 3, iclass 35, count 0 2006.173.07:29:18.12#ibcon#read 3, iclass 35, count 0 2006.173.07:29:18.12#ibcon#about to read 4, iclass 35, count 0 2006.173.07:29:18.12#ibcon#read 4, iclass 35, count 0 2006.173.07:29:18.12#ibcon#about to read 5, iclass 35, count 0 2006.173.07:29:18.12#ibcon#read 5, iclass 35, count 0 2006.173.07:29:18.12#ibcon#about to read 6, iclass 35, count 0 2006.173.07:29:18.12#ibcon#read 6, iclass 35, count 0 2006.173.07:29:18.12#ibcon#end of sib2, iclass 35, count 0 2006.173.07:29:18.12#ibcon#*mode == 0, iclass 35, count 0 2006.173.07:29:18.12#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.07:29:18.12#ibcon#[25=USB\r\n] 2006.173.07:29:18.12#ibcon#*before write, iclass 35, count 0 2006.173.07:29:18.12#ibcon#enter sib2, iclass 35, count 0 2006.173.07:29:18.12#ibcon#flushed, iclass 35, count 0 2006.173.07:29:18.12#ibcon#about to write, iclass 35, count 0 2006.173.07:29:18.12#ibcon#wrote, iclass 35, count 0 2006.173.07:29:18.12#ibcon#about to read 3, iclass 35, count 0 2006.173.07:29:18.15#ibcon#read 3, iclass 35, count 0 2006.173.07:29:18.15#ibcon#about to read 4, iclass 35, count 0 2006.173.07:29:18.15#ibcon#read 4, iclass 35, count 0 2006.173.07:29:18.15#ibcon#about to read 5, iclass 35, count 0 2006.173.07:29:18.15#ibcon#read 5, iclass 35, count 0 2006.173.07:29:18.15#ibcon#about to read 6, iclass 35, count 0 2006.173.07:29:18.15#ibcon#read 6, iclass 35, count 0 2006.173.07:29:18.15#ibcon#end of sib2, iclass 35, count 0 2006.173.07:29:18.15#ibcon#*after write, iclass 35, count 0 2006.173.07:29:18.15#ibcon#*before return 0, iclass 35, count 0 2006.173.07:29:18.15#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.07:29:18.15#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.07:29:18.15#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.07:29:18.15#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.07:29:18.15$vck44/valo=7,864.99 2006.173.07:29:18.15#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.07:29:18.15#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.07:29:18.15#ibcon#ireg 17 cls_cnt 0 2006.173.07:29:18.15#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.07:29:18.15#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.07:29:18.15#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.07:29:18.15#ibcon#enter wrdev, iclass 37, count 0 2006.173.07:29:18.15#ibcon#first serial, iclass 37, count 0 2006.173.07:29:18.15#ibcon#enter sib2, iclass 37, count 0 2006.173.07:29:18.15#ibcon#flushed, iclass 37, count 0 2006.173.07:29:18.15#ibcon#about to write, iclass 37, count 0 2006.173.07:29:18.15#ibcon#wrote, iclass 37, count 0 2006.173.07:29:18.15#ibcon#about to read 3, iclass 37, count 0 2006.173.07:29:18.17#ibcon#read 3, iclass 37, count 0 2006.173.07:29:18.17#ibcon#about to read 4, iclass 37, count 0 2006.173.07:29:18.17#ibcon#read 4, iclass 37, count 0 2006.173.07:29:18.17#ibcon#about to read 5, iclass 37, count 0 2006.173.07:29:18.17#ibcon#read 5, iclass 37, count 0 2006.173.07:29:18.17#ibcon#about to read 6, iclass 37, count 0 2006.173.07:29:18.17#ibcon#read 6, iclass 37, count 0 2006.173.07:29:18.17#ibcon#end of sib2, iclass 37, count 0 2006.173.07:29:18.17#ibcon#*mode == 0, iclass 37, count 0 2006.173.07:29:18.17#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.07:29:18.17#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.07:29:18.17#ibcon#*before write, iclass 37, count 0 2006.173.07:29:18.17#ibcon#enter sib2, iclass 37, count 0 2006.173.07:29:18.17#ibcon#flushed, iclass 37, count 0 2006.173.07:29:18.17#ibcon#about to write, iclass 37, count 0 2006.173.07:29:18.17#ibcon#wrote, iclass 37, count 0 2006.173.07:29:18.17#ibcon#about to read 3, iclass 37, count 0 2006.173.07:29:18.21#ibcon#read 3, iclass 37, count 0 2006.173.07:29:18.21#ibcon#about to read 4, iclass 37, count 0 2006.173.07:29:18.21#ibcon#read 4, iclass 37, count 0 2006.173.07:29:18.21#ibcon#about to read 5, iclass 37, count 0 2006.173.07:29:18.21#ibcon#read 5, iclass 37, count 0 2006.173.07:29:18.21#ibcon#about to read 6, iclass 37, count 0 2006.173.07:29:18.21#ibcon#read 6, iclass 37, count 0 2006.173.07:29:18.21#ibcon#end of sib2, iclass 37, count 0 2006.173.07:29:18.21#ibcon#*after write, iclass 37, count 0 2006.173.07:29:18.21#ibcon#*before return 0, iclass 37, count 0 2006.173.07:29:18.21#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.07:29:18.21#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.07:29:18.21#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.07:29:18.21#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.07:29:18.21$vck44/va=7,4 2006.173.07:29:18.21#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.07:29:18.21#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.07:29:18.21#ibcon#ireg 11 cls_cnt 2 2006.173.07:29:18.21#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.07:29:18.27#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.07:29:18.27#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.07:29:18.27#ibcon#enter wrdev, iclass 39, count 2 2006.173.07:29:18.27#ibcon#first serial, iclass 39, count 2 2006.173.07:29:18.27#ibcon#enter sib2, iclass 39, count 2 2006.173.07:29:18.27#ibcon#flushed, iclass 39, count 2 2006.173.07:29:18.27#ibcon#about to write, iclass 39, count 2 2006.173.07:29:18.27#ibcon#wrote, iclass 39, count 2 2006.173.07:29:18.27#ibcon#about to read 3, iclass 39, count 2 2006.173.07:29:18.29#ibcon#read 3, iclass 39, count 2 2006.173.07:29:18.29#ibcon#about to read 4, iclass 39, count 2 2006.173.07:29:18.29#ibcon#read 4, iclass 39, count 2 2006.173.07:29:18.29#ibcon#about to read 5, iclass 39, count 2 2006.173.07:29:18.29#ibcon#read 5, iclass 39, count 2 2006.173.07:29:18.29#ibcon#about to read 6, iclass 39, count 2 2006.173.07:29:18.29#ibcon#read 6, iclass 39, count 2 2006.173.07:29:18.29#ibcon#end of sib2, iclass 39, count 2 2006.173.07:29:18.29#ibcon#*mode == 0, iclass 39, count 2 2006.173.07:29:18.29#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.07:29:18.29#ibcon#[25=AT07-04\r\n] 2006.173.07:29:18.29#ibcon#*before write, iclass 39, count 2 2006.173.07:29:18.29#ibcon#enter sib2, iclass 39, count 2 2006.173.07:29:18.29#ibcon#flushed, iclass 39, count 2 2006.173.07:29:18.29#ibcon#about to write, iclass 39, count 2 2006.173.07:29:18.29#ibcon#wrote, iclass 39, count 2 2006.173.07:29:18.29#ibcon#about to read 3, iclass 39, count 2 2006.173.07:29:18.32#ibcon#read 3, iclass 39, count 2 2006.173.07:29:18.32#ibcon#about to read 4, iclass 39, count 2 2006.173.07:29:18.32#ibcon#read 4, iclass 39, count 2 2006.173.07:29:18.32#ibcon#about to read 5, iclass 39, count 2 2006.173.07:29:18.32#ibcon#read 5, iclass 39, count 2 2006.173.07:29:18.32#ibcon#about to read 6, iclass 39, count 2 2006.173.07:29:18.32#ibcon#read 6, iclass 39, count 2 2006.173.07:29:18.32#ibcon#end of sib2, iclass 39, count 2 2006.173.07:29:18.32#ibcon#*after write, iclass 39, count 2 2006.173.07:29:18.32#ibcon#*before return 0, iclass 39, count 2 2006.173.07:29:18.32#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.07:29:18.32#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.07:29:18.32#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.07:29:18.32#ibcon#ireg 7 cls_cnt 0 2006.173.07:29:18.32#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.07:29:18.44#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.07:29:18.44#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.07:29:18.44#ibcon#enter wrdev, iclass 39, count 0 2006.173.07:29:18.44#ibcon#first serial, iclass 39, count 0 2006.173.07:29:18.44#ibcon#enter sib2, iclass 39, count 0 2006.173.07:29:18.44#ibcon#flushed, iclass 39, count 0 2006.173.07:29:18.44#ibcon#about to write, iclass 39, count 0 2006.173.07:29:18.44#ibcon#wrote, iclass 39, count 0 2006.173.07:29:18.44#ibcon#about to read 3, iclass 39, count 0 2006.173.07:29:18.46#ibcon#read 3, iclass 39, count 0 2006.173.07:29:18.46#ibcon#about to read 4, iclass 39, count 0 2006.173.07:29:18.46#ibcon#read 4, iclass 39, count 0 2006.173.07:29:18.46#ibcon#about to read 5, iclass 39, count 0 2006.173.07:29:18.46#ibcon#read 5, iclass 39, count 0 2006.173.07:29:18.46#ibcon#about to read 6, iclass 39, count 0 2006.173.07:29:18.46#ibcon#read 6, iclass 39, count 0 2006.173.07:29:18.46#ibcon#end of sib2, iclass 39, count 0 2006.173.07:29:18.46#ibcon#*mode == 0, iclass 39, count 0 2006.173.07:29:18.46#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.07:29:18.46#ibcon#[25=USB\r\n] 2006.173.07:29:18.46#ibcon#*before write, iclass 39, count 0 2006.173.07:29:18.46#ibcon#enter sib2, iclass 39, count 0 2006.173.07:29:18.46#ibcon#flushed, iclass 39, count 0 2006.173.07:29:18.46#ibcon#about to write, iclass 39, count 0 2006.173.07:29:18.46#ibcon#wrote, iclass 39, count 0 2006.173.07:29:18.46#ibcon#about to read 3, iclass 39, count 0 2006.173.07:29:18.49#ibcon#read 3, iclass 39, count 0 2006.173.07:29:18.49#ibcon#about to read 4, iclass 39, count 0 2006.173.07:29:18.49#ibcon#read 4, iclass 39, count 0 2006.173.07:29:18.49#ibcon#about to read 5, iclass 39, count 0 2006.173.07:29:18.49#ibcon#read 5, iclass 39, count 0 2006.173.07:29:18.49#ibcon#about to read 6, iclass 39, count 0 2006.173.07:29:18.49#ibcon#read 6, iclass 39, count 0 2006.173.07:29:18.49#ibcon#end of sib2, iclass 39, count 0 2006.173.07:29:18.49#ibcon#*after write, iclass 39, count 0 2006.173.07:29:18.49#ibcon#*before return 0, iclass 39, count 0 2006.173.07:29:18.49#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.07:29:18.49#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.07:29:18.49#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.07:29:18.49#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.07:29:18.49$vck44/valo=8,884.99 2006.173.07:29:18.49#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.07:29:18.49#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.07:29:18.49#ibcon#ireg 17 cls_cnt 0 2006.173.07:29:18.49#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.07:29:18.49#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.07:29:18.49#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.07:29:18.49#ibcon#enter wrdev, iclass 3, count 0 2006.173.07:29:18.49#ibcon#first serial, iclass 3, count 0 2006.173.07:29:18.49#ibcon#enter sib2, iclass 3, count 0 2006.173.07:29:18.49#ibcon#flushed, iclass 3, count 0 2006.173.07:29:18.49#ibcon#about to write, iclass 3, count 0 2006.173.07:29:18.49#ibcon#wrote, iclass 3, count 0 2006.173.07:29:18.49#ibcon#about to read 3, iclass 3, count 0 2006.173.07:29:18.51#ibcon#read 3, iclass 3, count 0 2006.173.07:29:18.51#ibcon#about to read 4, iclass 3, count 0 2006.173.07:29:18.51#ibcon#read 4, iclass 3, count 0 2006.173.07:29:18.51#ibcon#about to read 5, iclass 3, count 0 2006.173.07:29:18.51#ibcon#read 5, iclass 3, count 0 2006.173.07:29:18.51#ibcon#about to read 6, iclass 3, count 0 2006.173.07:29:18.51#ibcon#read 6, iclass 3, count 0 2006.173.07:29:18.51#ibcon#end of sib2, iclass 3, count 0 2006.173.07:29:18.51#ibcon#*mode == 0, iclass 3, count 0 2006.173.07:29:18.51#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.07:29:18.51#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.07:29:18.51#ibcon#*before write, iclass 3, count 0 2006.173.07:29:18.51#ibcon#enter sib2, iclass 3, count 0 2006.173.07:29:18.51#ibcon#flushed, iclass 3, count 0 2006.173.07:29:18.51#ibcon#about to write, iclass 3, count 0 2006.173.07:29:18.51#ibcon#wrote, iclass 3, count 0 2006.173.07:29:18.51#ibcon#about to read 3, iclass 3, count 0 2006.173.07:29:18.55#ibcon#read 3, iclass 3, count 0 2006.173.07:29:18.55#ibcon#about to read 4, iclass 3, count 0 2006.173.07:29:18.55#ibcon#read 4, iclass 3, count 0 2006.173.07:29:18.55#ibcon#about to read 5, iclass 3, count 0 2006.173.07:29:18.55#ibcon#read 5, iclass 3, count 0 2006.173.07:29:18.55#ibcon#about to read 6, iclass 3, count 0 2006.173.07:29:18.55#ibcon#read 6, iclass 3, count 0 2006.173.07:29:18.55#ibcon#end of sib2, iclass 3, count 0 2006.173.07:29:18.55#ibcon#*after write, iclass 3, count 0 2006.173.07:29:18.55#ibcon#*before return 0, iclass 3, count 0 2006.173.07:29:18.55#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.07:29:18.55#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.07:29:18.55#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.07:29:18.55#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.07:29:18.55$vck44/va=8,4 2006.173.07:29:18.55#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.07:29:18.55#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.07:29:18.55#ibcon#ireg 11 cls_cnt 2 2006.173.07:29:18.55#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.07:29:18.61#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.07:29:18.61#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.07:29:18.61#ibcon#enter wrdev, iclass 5, count 2 2006.173.07:29:18.61#ibcon#first serial, iclass 5, count 2 2006.173.07:29:18.61#ibcon#enter sib2, iclass 5, count 2 2006.173.07:29:18.61#ibcon#flushed, iclass 5, count 2 2006.173.07:29:18.61#ibcon#about to write, iclass 5, count 2 2006.173.07:29:18.61#ibcon#wrote, iclass 5, count 2 2006.173.07:29:18.61#ibcon#about to read 3, iclass 5, count 2 2006.173.07:29:18.63#ibcon#read 3, iclass 5, count 2 2006.173.07:29:18.63#ibcon#about to read 4, iclass 5, count 2 2006.173.07:29:18.63#ibcon#read 4, iclass 5, count 2 2006.173.07:29:18.63#ibcon#about to read 5, iclass 5, count 2 2006.173.07:29:18.63#ibcon#read 5, iclass 5, count 2 2006.173.07:29:18.63#ibcon#about to read 6, iclass 5, count 2 2006.173.07:29:18.63#ibcon#read 6, iclass 5, count 2 2006.173.07:29:18.63#ibcon#end of sib2, iclass 5, count 2 2006.173.07:29:18.63#ibcon#*mode == 0, iclass 5, count 2 2006.173.07:29:18.63#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.07:29:18.63#ibcon#[25=AT08-04\r\n] 2006.173.07:29:18.63#ibcon#*before write, iclass 5, count 2 2006.173.07:29:18.63#ibcon#enter sib2, iclass 5, count 2 2006.173.07:29:18.63#ibcon#flushed, iclass 5, count 2 2006.173.07:29:18.63#ibcon#about to write, iclass 5, count 2 2006.173.07:29:18.63#ibcon#wrote, iclass 5, count 2 2006.173.07:29:18.63#ibcon#about to read 3, iclass 5, count 2 2006.173.07:29:18.66#ibcon#read 3, iclass 5, count 2 2006.173.07:29:18.66#ibcon#about to read 4, iclass 5, count 2 2006.173.07:29:18.66#ibcon#read 4, iclass 5, count 2 2006.173.07:29:18.66#ibcon#about to read 5, iclass 5, count 2 2006.173.07:29:18.66#ibcon#read 5, iclass 5, count 2 2006.173.07:29:18.66#ibcon#about to read 6, iclass 5, count 2 2006.173.07:29:18.66#ibcon#read 6, iclass 5, count 2 2006.173.07:29:18.66#ibcon#end of sib2, iclass 5, count 2 2006.173.07:29:18.66#ibcon#*after write, iclass 5, count 2 2006.173.07:29:18.66#ibcon#*before return 0, iclass 5, count 2 2006.173.07:29:18.66#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.07:29:18.66#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.07:29:18.66#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.07:29:18.66#ibcon#ireg 7 cls_cnt 0 2006.173.07:29:18.66#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.07:29:18.78#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.07:29:18.78#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.07:29:18.78#ibcon#enter wrdev, iclass 5, count 0 2006.173.07:29:18.78#ibcon#first serial, iclass 5, count 0 2006.173.07:29:18.78#ibcon#enter sib2, iclass 5, count 0 2006.173.07:29:18.78#ibcon#flushed, iclass 5, count 0 2006.173.07:29:18.78#ibcon#about to write, iclass 5, count 0 2006.173.07:29:18.78#ibcon#wrote, iclass 5, count 0 2006.173.07:29:18.78#ibcon#about to read 3, iclass 5, count 0 2006.173.07:29:18.80#ibcon#read 3, iclass 5, count 0 2006.173.07:29:18.80#ibcon#about to read 4, iclass 5, count 0 2006.173.07:29:18.80#ibcon#read 4, iclass 5, count 0 2006.173.07:29:18.80#ibcon#about to read 5, iclass 5, count 0 2006.173.07:29:18.80#ibcon#read 5, iclass 5, count 0 2006.173.07:29:18.80#ibcon#about to read 6, iclass 5, count 0 2006.173.07:29:18.80#ibcon#read 6, iclass 5, count 0 2006.173.07:29:18.80#ibcon#end of sib2, iclass 5, count 0 2006.173.07:29:18.80#ibcon#*mode == 0, iclass 5, count 0 2006.173.07:29:18.80#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.07:29:18.80#ibcon#[25=USB\r\n] 2006.173.07:29:18.80#ibcon#*before write, iclass 5, count 0 2006.173.07:29:18.80#ibcon#enter sib2, iclass 5, count 0 2006.173.07:29:18.80#ibcon#flushed, iclass 5, count 0 2006.173.07:29:18.80#ibcon#about to write, iclass 5, count 0 2006.173.07:29:18.80#ibcon#wrote, iclass 5, count 0 2006.173.07:29:18.80#ibcon#about to read 3, iclass 5, count 0 2006.173.07:29:18.83#ibcon#read 3, iclass 5, count 0 2006.173.07:29:18.83#ibcon#about to read 4, iclass 5, count 0 2006.173.07:29:18.83#ibcon#read 4, iclass 5, count 0 2006.173.07:29:18.83#ibcon#about to read 5, iclass 5, count 0 2006.173.07:29:18.83#ibcon#read 5, iclass 5, count 0 2006.173.07:29:18.83#ibcon#about to read 6, iclass 5, count 0 2006.173.07:29:18.83#ibcon#read 6, iclass 5, count 0 2006.173.07:29:18.83#ibcon#end of sib2, iclass 5, count 0 2006.173.07:29:18.83#ibcon#*after write, iclass 5, count 0 2006.173.07:29:18.83#ibcon#*before return 0, iclass 5, count 0 2006.173.07:29:18.83#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.07:29:18.83#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.07:29:18.83#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.07:29:18.83#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.07:29:18.83$vck44/vblo=1,629.99 2006.173.07:29:18.83#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.07:29:18.83#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.07:29:18.83#ibcon#ireg 17 cls_cnt 0 2006.173.07:29:18.83#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.07:29:18.83#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.07:29:18.83#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.07:29:18.83#ibcon#enter wrdev, iclass 7, count 0 2006.173.07:29:18.83#ibcon#first serial, iclass 7, count 0 2006.173.07:29:18.83#ibcon#enter sib2, iclass 7, count 0 2006.173.07:29:18.83#ibcon#flushed, iclass 7, count 0 2006.173.07:29:18.83#ibcon#about to write, iclass 7, count 0 2006.173.07:29:18.83#ibcon#wrote, iclass 7, count 0 2006.173.07:29:18.83#ibcon#about to read 3, iclass 7, count 0 2006.173.07:29:18.85#ibcon#read 3, iclass 7, count 0 2006.173.07:29:18.85#ibcon#about to read 4, iclass 7, count 0 2006.173.07:29:18.85#ibcon#read 4, iclass 7, count 0 2006.173.07:29:18.85#ibcon#about to read 5, iclass 7, count 0 2006.173.07:29:18.85#ibcon#read 5, iclass 7, count 0 2006.173.07:29:18.85#ibcon#about to read 6, iclass 7, count 0 2006.173.07:29:18.85#ibcon#read 6, iclass 7, count 0 2006.173.07:29:18.85#ibcon#end of sib2, iclass 7, count 0 2006.173.07:29:18.85#ibcon#*mode == 0, iclass 7, count 0 2006.173.07:29:18.85#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.07:29:18.85#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.07:29:18.85#ibcon#*before write, iclass 7, count 0 2006.173.07:29:18.85#ibcon#enter sib2, iclass 7, count 0 2006.173.07:29:18.85#ibcon#flushed, iclass 7, count 0 2006.173.07:29:18.85#ibcon#about to write, iclass 7, count 0 2006.173.07:29:18.85#ibcon#wrote, iclass 7, count 0 2006.173.07:29:18.85#ibcon#about to read 3, iclass 7, count 0 2006.173.07:29:18.89#ibcon#read 3, iclass 7, count 0 2006.173.07:29:18.89#ibcon#about to read 4, iclass 7, count 0 2006.173.07:29:18.89#ibcon#read 4, iclass 7, count 0 2006.173.07:29:18.89#ibcon#about to read 5, iclass 7, count 0 2006.173.07:29:18.89#ibcon#read 5, iclass 7, count 0 2006.173.07:29:18.89#ibcon#about to read 6, iclass 7, count 0 2006.173.07:29:18.89#ibcon#read 6, iclass 7, count 0 2006.173.07:29:18.89#ibcon#end of sib2, iclass 7, count 0 2006.173.07:29:18.89#ibcon#*after write, iclass 7, count 0 2006.173.07:29:18.89#ibcon#*before return 0, iclass 7, count 0 2006.173.07:29:18.89#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.07:29:18.89#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.07:29:18.89#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.07:29:18.89#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.07:29:18.89$vck44/vb=1,4 2006.173.07:29:18.89#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.07:29:18.89#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.07:29:18.89#ibcon#ireg 11 cls_cnt 2 2006.173.07:29:18.89#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.07:29:18.89#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.07:29:18.89#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.07:29:18.89#ibcon#enter wrdev, iclass 11, count 2 2006.173.07:29:18.89#ibcon#first serial, iclass 11, count 2 2006.173.07:29:18.89#ibcon#enter sib2, iclass 11, count 2 2006.173.07:29:18.89#ibcon#flushed, iclass 11, count 2 2006.173.07:29:18.89#ibcon#about to write, iclass 11, count 2 2006.173.07:29:18.89#ibcon#wrote, iclass 11, count 2 2006.173.07:29:18.89#ibcon#about to read 3, iclass 11, count 2 2006.173.07:29:18.91#ibcon#read 3, iclass 11, count 2 2006.173.07:29:18.91#ibcon#about to read 4, iclass 11, count 2 2006.173.07:29:18.91#ibcon#read 4, iclass 11, count 2 2006.173.07:29:18.91#ibcon#about to read 5, iclass 11, count 2 2006.173.07:29:18.91#ibcon#read 5, iclass 11, count 2 2006.173.07:29:18.91#ibcon#about to read 6, iclass 11, count 2 2006.173.07:29:18.91#ibcon#read 6, iclass 11, count 2 2006.173.07:29:18.91#ibcon#end of sib2, iclass 11, count 2 2006.173.07:29:18.91#ibcon#*mode == 0, iclass 11, count 2 2006.173.07:29:18.91#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.07:29:18.91#ibcon#[27=AT01-04\r\n] 2006.173.07:29:18.91#ibcon#*before write, iclass 11, count 2 2006.173.07:29:18.91#ibcon#enter sib2, iclass 11, count 2 2006.173.07:29:18.91#ibcon#flushed, iclass 11, count 2 2006.173.07:29:18.91#ibcon#about to write, iclass 11, count 2 2006.173.07:29:18.91#ibcon#wrote, iclass 11, count 2 2006.173.07:29:18.91#ibcon#about to read 3, iclass 11, count 2 2006.173.07:29:18.94#ibcon#read 3, iclass 11, count 2 2006.173.07:29:18.94#ibcon#about to read 4, iclass 11, count 2 2006.173.07:29:18.94#ibcon#read 4, iclass 11, count 2 2006.173.07:29:18.94#ibcon#about to read 5, iclass 11, count 2 2006.173.07:29:18.94#ibcon#read 5, iclass 11, count 2 2006.173.07:29:18.94#ibcon#about to read 6, iclass 11, count 2 2006.173.07:29:18.94#ibcon#read 6, iclass 11, count 2 2006.173.07:29:18.94#ibcon#end of sib2, iclass 11, count 2 2006.173.07:29:18.94#ibcon#*after write, iclass 11, count 2 2006.173.07:29:18.94#ibcon#*before return 0, iclass 11, count 2 2006.173.07:29:18.94#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.07:29:18.94#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.07:29:18.94#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.07:29:18.94#ibcon#ireg 7 cls_cnt 0 2006.173.07:29:18.94#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.07:29:19.06#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.07:29:19.06#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.07:29:19.06#ibcon#enter wrdev, iclass 11, count 0 2006.173.07:29:19.06#ibcon#first serial, iclass 11, count 0 2006.173.07:29:19.06#ibcon#enter sib2, iclass 11, count 0 2006.173.07:29:19.06#ibcon#flushed, iclass 11, count 0 2006.173.07:29:19.06#ibcon#about to write, iclass 11, count 0 2006.173.07:29:19.06#ibcon#wrote, iclass 11, count 0 2006.173.07:29:19.06#ibcon#about to read 3, iclass 11, count 0 2006.173.07:29:19.08#ibcon#read 3, iclass 11, count 0 2006.173.07:29:19.08#ibcon#about to read 4, iclass 11, count 0 2006.173.07:29:19.08#ibcon#read 4, iclass 11, count 0 2006.173.07:29:19.08#ibcon#about to read 5, iclass 11, count 0 2006.173.07:29:19.08#ibcon#read 5, iclass 11, count 0 2006.173.07:29:19.08#ibcon#about to read 6, iclass 11, count 0 2006.173.07:29:19.08#ibcon#read 6, iclass 11, count 0 2006.173.07:29:19.08#ibcon#end of sib2, iclass 11, count 0 2006.173.07:29:19.08#ibcon#*mode == 0, iclass 11, count 0 2006.173.07:29:19.08#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.07:29:19.08#ibcon#[27=USB\r\n] 2006.173.07:29:19.08#ibcon#*before write, iclass 11, count 0 2006.173.07:29:19.08#ibcon#enter sib2, iclass 11, count 0 2006.173.07:29:19.08#ibcon#flushed, iclass 11, count 0 2006.173.07:29:19.08#ibcon#about to write, iclass 11, count 0 2006.173.07:29:19.08#ibcon#wrote, iclass 11, count 0 2006.173.07:29:19.08#ibcon#about to read 3, iclass 11, count 0 2006.173.07:29:19.11#ibcon#read 3, iclass 11, count 0 2006.173.07:29:19.11#ibcon#about to read 4, iclass 11, count 0 2006.173.07:29:19.11#ibcon#read 4, iclass 11, count 0 2006.173.07:29:19.11#ibcon#about to read 5, iclass 11, count 0 2006.173.07:29:19.11#ibcon#read 5, iclass 11, count 0 2006.173.07:29:19.11#ibcon#about to read 6, iclass 11, count 0 2006.173.07:29:19.11#ibcon#read 6, iclass 11, count 0 2006.173.07:29:19.11#ibcon#end of sib2, iclass 11, count 0 2006.173.07:29:19.11#ibcon#*after write, iclass 11, count 0 2006.173.07:29:19.11#ibcon#*before return 0, iclass 11, count 0 2006.173.07:29:19.11#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.07:29:19.11#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.07:29:19.11#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.07:29:19.11#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.07:29:19.11$vck44/vblo=2,634.99 2006.173.07:29:19.11#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.07:29:19.11#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.07:29:19.11#ibcon#ireg 17 cls_cnt 0 2006.173.07:29:19.11#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.07:29:19.11#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.07:29:19.11#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.07:29:19.11#ibcon#enter wrdev, iclass 13, count 0 2006.173.07:29:19.11#ibcon#first serial, iclass 13, count 0 2006.173.07:29:19.11#ibcon#enter sib2, iclass 13, count 0 2006.173.07:29:19.11#ibcon#flushed, iclass 13, count 0 2006.173.07:29:19.11#ibcon#about to write, iclass 13, count 0 2006.173.07:29:19.11#ibcon#wrote, iclass 13, count 0 2006.173.07:29:19.11#ibcon#about to read 3, iclass 13, count 0 2006.173.07:29:19.13#ibcon#read 3, iclass 13, count 0 2006.173.07:29:19.13#ibcon#about to read 4, iclass 13, count 0 2006.173.07:29:19.13#ibcon#read 4, iclass 13, count 0 2006.173.07:29:19.13#ibcon#about to read 5, iclass 13, count 0 2006.173.07:29:19.13#ibcon#read 5, iclass 13, count 0 2006.173.07:29:19.13#ibcon#about to read 6, iclass 13, count 0 2006.173.07:29:19.13#ibcon#read 6, iclass 13, count 0 2006.173.07:29:19.13#ibcon#end of sib2, iclass 13, count 0 2006.173.07:29:19.13#ibcon#*mode == 0, iclass 13, count 0 2006.173.07:29:19.13#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.07:29:19.13#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.07:29:19.13#ibcon#*before write, iclass 13, count 0 2006.173.07:29:19.13#ibcon#enter sib2, iclass 13, count 0 2006.173.07:29:19.13#ibcon#flushed, iclass 13, count 0 2006.173.07:29:19.13#ibcon#about to write, iclass 13, count 0 2006.173.07:29:19.13#ibcon#wrote, iclass 13, count 0 2006.173.07:29:19.13#ibcon#about to read 3, iclass 13, count 0 2006.173.07:29:19.17#ibcon#read 3, iclass 13, count 0 2006.173.07:29:19.17#ibcon#about to read 4, iclass 13, count 0 2006.173.07:29:19.17#ibcon#read 4, iclass 13, count 0 2006.173.07:29:19.17#ibcon#about to read 5, iclass 13, count 0 2006.173.07:29:19.17#ibcon#read 5, iclass 13, count 0 2006.173.07:29:19.17#ibcon#about to read 6, iclass 13, count 0 2006.173.07:29:19.17#ibcon#read 6, iclass 13, count 0 2006.173.07:29:19.17#ibcon#end of sib2, iclass 13, count 0 2006.173.07:29:19.17#ibcon#*after write, iclass 13, count 0 2006.173.07:29:19.17#ibcon#*before return 0, iclass 13, count 0 2006.173.07:29:19.17#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.07:29:19.17#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.07:29:19.17#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.07:29:19.17#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.07:29:19.17$vck44/vb=2,4 2006.173.07:29:19.17#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.07:29:19.17#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.07:29:19.17#ibcon#ireg 11 cls_cnt 2 2006.173.07:29:19.17#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.07:29:19.23#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.07:29:19.23#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.07:29:19.23#ibcon#enter wrdev, iclass 15, count 2 2006.173.07:29:19.23#ibcon#first serial, iclass 15, count 2 2006.173.07:29:19.23#ibcon#enter sib2, iclass 15, count 2 2006.173.07:29:19.23#ibcon#flushed, iclass 15, count 2 2006.173.07:29:19.23#ibcon#about to write, iclass 15, count 2 2006.173.07:29:19.23#ibcon#wrote, iclass 15, count 2 2006.173.07:29:19.23#ibcon#about to read 3, iclass 15, count 2 2006.173.07:29:19.25#ibcon#read 3, iclass 15, count 2 2006.173.07:29:19.25#ibcon#about to read 4, iclass 15, count 2 2006.173.07:29:19.25#ibcon#read 4, iclass 15, count 2 2006.173.07:29:19.25#ibcon#about to read 5, iclass 15, count 2 2006.173.07:29:19.25#ibcon#read 5, iclass 15, count 2 2006.173.07:29:19.25#ibcon#about to read 6, iclass 15, count 2 2006.173.07:29:19.25#ibcon#read 6, iclass 15, count 2 2006.173.07:29:19.25#ibcon#end of sib2, iclass 15, count 2 2006.173.07:29:19.25#ibcon#*mode == 0, iclass 15, count 2 2006.173.07:29:19.25#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.07:29:19.25#ibcon#[27=AT02-04\r\n] 2006.173.07:29:19.25#ibcon#*before write, iclass 15, count 2 2006.173.07:29:19.25#ibcon#enter sib2, iclass 15, count 2 2006.173.07:29:19.25#ibcon#flushed, iclass 15, count 2 2006.173.07:29:19.25#ibcon#about to write, iclass 15, count 2 2006.173.07:29:19.25#ibcon#wrote, iclass 15, count 2 2006.173.07:29:19.25#ibcon#about to read 3, iclass 15, count 2 2006.173.07:29:19.28#ibcon#read 3, iclass 15, count 2 2006.173.07:29:19.28#ibcon#about to read 4, iclass 15, count 2 2006.173.07:29:19.28#ibcon#read 4, iclass 15, count 2 2006.173.07:29:19.28#ibcon#about to read 5, iclass 15, count 2 2006.173.07:29:19.28#ibcon#read 5, iclass 15, count 2 2006.173.07:29:19.28#ibcon#about to read 6, iclass 15, count 2 2006.173.07:29:19.28#ibcon#read 6, iclass 15, count 2 2006.173.07:29:19.28#ibcon#end of sib2, iclass 15, count 2 2006.173.07:29:19.28#ibcon#*after write, iclass 15, count 2 2006.173.07:29:19.28#ibcon#*before return 0, iclass 15, count 2 2006.173.07:29:19.28#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.07:29:19.28#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.07:29:19.28#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.07:29:19.28#ibcon#ireg 7 cls_cnt 0 2006.173.07:29:19.28#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.07:29:19.40#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.07:29:19.40#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.07:29:19.40#ibcon#enter wrdev, iclass 15, count 0 2006.173.07:29:19.40#ibcon#first serial, iclass 15, count 0 2006.173.07:29:19.40#ibcon#enter sib2, iclass 15, count 0 2006.173.07:29:19.40#ibcon#flushed, iclass 15, count 0 2006.173.07:29:19.40#ibcon#about to write, iclass 15, count 0 2006.173.07:29:19.40#ibcon#wrote, iclass 15, count 0 2006.173.07:29:19.40#ibcon#about to read 3, iclass 15, count 0 2006.173.07:29:19.42#ibcon#read 3, iclass 15, count 0 2006.173.07:29:19.42#ibcon#about to read 4, iclass 15, count 0 2006.173.07:29:19.42#ibcon#read 4, iclass 15, count 0 2006.173.07:29:19.42#ibcon#about to read 5, iclass 15, count 0 2006.173.07:29:19.42#ibcon#read 5, iclass 15, count 0 2006.173.07:29:19.42#ibcon#about to read 6, iclass 15, count 0 2006.173.07:29:19.42#ibcon#read 6, iclass 15, count 0 2006.173.07:29:19.42#ibcon#end of sib2, iclass 15, count 0 2006.173.07:29:19.42#ibcon#*mode == 0, iclass 15, count 0 2006.173.07:29:19.42#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.07:29:19.42#ibcon#[27=USB\r\n] 2006.173.07:29:19.42#ibcon#*before write, iclass 15, count 0 2006.173.07:29:19.42#ibcon#enter sib2, iclass 15, count 0 2006.173.07:29:19.42#ibcon#flushed, iclass 15, count 0 2006.173.07:29:19.42#ibcon#about to write, iclass 15, count 0 2006.173.07:29:19.42#ibcon#wrote, iclass 15, count 0 2006.173.07:29:19.42#ibcon#about to read 3, iclass 15, count 0 2006.173.07:29:19.45#ibcon#read 3, iclass 15, count 0 2006.173.07:29:19.45#ibcon#about to read 4, iclass 15, count 0 2006.173.07:29:19.45#ibcon#read 4, iclass 15, count 0 2006.173.07:29:19.45#ibcon#about to read 5, iclass 15, count 0 2006.173.07:29:19.45#ibcon#read 5, iclass 15, count 0 2006.173.07:29:19.45#ibcon#about to read 6, iclass 15, count 0 2006.173.07:29:19.45#ibcon#read 6, iclass 15, count 0 2006.173.07:29:19.45#ibcon#end of sib2, iclass 15, count 0 2006.173.07:29:19.45#ibcon#*after write, iclass 15, count 0 2006.173.07:29:19.45#ibcon#*before return 0, iclass 15, count 0 2006.173.07:29:19.45#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.07:29:19.45#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.07:29:19.45#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.07:29:19.45#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.07:29:19.45$vck44/vblo=3,649.99 2006.173.07:29:19.45#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.07:29:19.45#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.07:29:19.45#ibcon#ireg 17 cls_cnt 0 2006.173.07:29:19.45#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.07:29:19.45#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.07:29:19.45#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.07:29:19.45#ibcon#enter wrdev, iclass 17, count 0 2006.173.07:29:19.45#ibcon#first serial, iclass 17, count 0 2006.173.07:29:19.45#ibcon#enter sib2, iclass 17, count 0 2006.173.07:29:19.45#ibcon#flushed, iclass 17, count 0 2006.173.07:29:19.45#ibcon#about to write, iclass 17, count 0 2006.173.07:29:19.45#ibcon#wrote, iclass 17, count 0 2006.173.07:29:19.45#ibcon#about to read 3, iclass 17, count 0 2006.173.07:29:19.47#ibcon#read 3, iclass 17, count 0 2006.173.07:29:19.47#ibcon#about to read 4, iclass 17, count 0 2006.173.07:29:19.47#ibcon#read 4, iclass 17, count 0 2006.173.07:29:19.47#ibcon#about to read 5, iclass 17, count 0 2006.173.07:29:19.47#ibcon#read 5, iclass 17, count 0 2006.173.07:29:19.47#ibcon#about to read 6, iclass 17, count 0 2006.173.07:29:19.47#ibcon#read 6, iclass 17, count 0 2006.173.07:29:19.47#ibcon#end of sib2, iclass 17, count 0 2006.173.07:29:19.47#ibcon#*mode == 0, iclass 17, count 0 2006.173.07:29:19.47#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.07:29:19.47#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.07:29:19.47#ibcon#*before write, iclass 17, count 0 2006.173.07:29:19.47#ibcon#enter sib2, iclass 17, count 0 2006.173.07:29:19.47#ibcon#flushed, iclass 17, count 0 2006.173.07:29:19.47#ibcon#about to write, iclass 17, count 0 2006.173.07:29:19.47#ibcon#wrote, iclass 17, count 0 2006.173.07:29:19.47#ibcon#about to read 3, iclass 17, count 0 2006.173.07:29:19.51#ibcon#read 3, iclass 17, count 0 2006.173.07:29:19.51#ibcon#about to read 4, iclass 17, count 0 2006.173.07:29:19.51#ibcon#read 4, iclass 17, count 0 2006.173.07:29:19.51#ibcon#about to read 5, iclass 17, count 0 2006.173.07:29:19.51#ibcon#read 5, iclass 17, count 0 2006.173.07:29:19.51#ibcon#about to read 6, iclass 17, count 0 2006.173.07:29:19.51#ibcon#read 6, iclass 17, count 0 2006.173.07:29:19.51#ibcon#end of sib2, iclass 17, count 0 2006.173.07:29:19.51#ibcon#*after write, iclass 17, count 0 2006.173.07:29:19.51#ibcon#*before return 0, iclass 17, count 0 2006.173.07:29:19.51#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.07:29:19.51#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.07:29:19.51#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.07:29:19.51#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.07:29:19.51$vck44/vb=3,4 2006.173.07:29:19.51#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.07:29:19.51#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.07:29:19.51#ibcon#ireg 11 cls_cnt 2 2006.173.07:29:19.51#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.07:29:19.57#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.07:29:19.57#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.07:29:19.57#ibcon#enter wrdev, iclass 19, count 2 2006.173.07:29:19.57#ibcon#first serial, iclass 19, count 2 2006.173.07:29:19.57#ibcon#enter sib2, iclass 19, count 2 2006.173.07:29:19.57#ibcon#flushed, iclass 19, count 2 2006.173.07:29:19.57#ibcon#about to write, iclass 19, count 2 2006.173.07:29:19.57#ibcon#wrote, iclass 19, count 2 2006.173.07:29:19.57#ibcon#about to read 3, iclass 19, count 2 2006.173.07:29:19.59#ibcon#read 3, iclass 19, count 2 2006.173.07:29:19.59#ibcon#about to read 4, iclass 19, count 2 2006.173.07:29:19.59#ibcon#read 4, iclass 19, count 2 2006.173.07:29:19.59#ibcon#about to read 5, iclass 19, count 2 2006.173.07:29:19.59#ibcon#read 5, iclass 19, count 2 2006.173.07:29:19.59#ibcon#about to read 6, iclass 19, count 2 2006.173.07:29:19.59#ibcon#read 6, iclass 19, count 2 2006.173.07:29:19.59#ibcon#end of sib2, iclass 19, count 2 2006.173.07:29:19.59#ibcon#*mode == 0, iclass 19, count 2 2006.173.07:29:19.59#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.07:29:19.59#ibcon#[27=AT03-04\r\n] 2006.173.07:29:19.59#ibcon#*before write, iclass 19, count 2 2006.173.07:29:19.59#ibcon#enter sib2, iclass 19, count 2 2006.173.07:29:19.59#ibcon#flushed, iclass 19, count 2 2006.173.07:29:19.59#ibcon#about to write, iclass 19, count 2 2006.173.07:29:19.59#ibcon#wrote, iclass 19, count 2 2006.173.07:29:19.59#ibcon#about to read 3, iclass 19, count 2 2006.173.07:29:19.62#ibcon#read 3, iclass 19, count 2 2006.173.07:29:19.62#ibcon#about to read 4, iclass 19, count 2 2006.173.07:29:19.62#ibcon#read 4, iclass 19, count 2 2006.173.07:29:19.62#ibcon#about to read 5, iclass 19, count 2 2006.173.07:29:19.62#ibcon#read 5, iclass 19, count 2 2006.173.07:29:19.62#ibcon#about to read 6, iclass 19, count 2 2006.173.07:29:19.62#ibcon#read 6, iclass 19, count 2 2006.173.07:29:19.62#ibcon#end of sib2, iclass 19, count 2 2006.173.07:29:19.62#ibcon#*after write, iclass 19, count 2 2006.173.07:29:19.62#ibcon#*before return 0, iclass 19, count 2 2006.173.07:29:19.62#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.07:29:19.62#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.07:29:19.62#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.07:29:19.62#ibcon#ireg 7 cls_cnt 0 2006.173.07:29:19.62#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.07:29:19.74#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.07:29:19.74#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.07:29:19.74#ibcon#enter wrdev, iclass 19, count 0 2006.173.07:29:19.74#ibcon#first serial, iclass 19, count 0 2006.173.07:29:19.74#ibcon#enter sib2, iclass 19, count 0 2006.173.07:29:19.74#ibcon#flushed, iclass 19, count 0 2006.173.07:29:19.74#ibcon#about to write, iclass 19, count 0 2006.173.07:29:19.74#ibcon#wrote, iclass 19, count 0 2006.173.07:29:19.74#ibcon#about to read 3, iclass 19, count 0 2006.173.07:29:19.76#ibcon#read 3, iclass 19, count 0 2006.173.07:29:19.76#ibcon#about to read 4, iclass 19, count 0 2006.173.07:29:19.76#ibcon#read 4, iclass 19, count 0 2006.173.07:29:19.76#ibcon#about to read 5, iclass 19, count 0 2006.173.07:29:19.76#ibcon#read 5, iclass 19, count 0 2006.173.07:29:19.76#ibcon#about to read 6, iclass 19, count 0 2006.173.07:29:19.76#ibcon#read 6, iclass 19, count 0 2006.173.07:29:19.76#ibcon#end of sib2, iclass 19, count 0 2006.173.07:29:19.76#ibcon#*mode == 0, iclass 19, count 0 2006.173.07:29:19.76#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.07:29:19.76#ibcon#[27=USB\r\n] 2006.173.07:29:19.76#ibcon#*before write, iclass 19, count 0 2006.173.07:29:19.76#ibcon#enter sib2, iclass 19, count 0 2006.173.07:29:19.76#ibcon#flushed, iclass 19, count 0 2006.173.07:29:19.76#ibcon#about to write, iclass 19, count 0 2006.173.07:29:19.76#ibcon#wrote, iclass 19, count 0 2006.173.07:29:19.76#ibcon#about to read 3, iclass 19, count 0 2006.173.07:29:19.79#ibcon#read 3, iclass 19, count 0 2006.173.07:29:19.79#ibcon#about to read 4, iclass 19, count 0 2006.173.07:29:19.79#ibcon#read 4, iclass 19, count 0 2006.173.07:29:19.79#ibcon#about to read 5, iclass 19, count 0 2006.173.07:29:19.79#ibcon#read 5, iclass 19, count 0 2006.173.07:29:19.79#ibcon#about to read 6, iclass 19, count 0 2006.173.07:29:19.79#ibcon#read 6, iclass 19, count 0 2006.173.07:29:19.79#ibcon#end of sib2, iclass 19, count 0 2006.173.07:29:19.79#ibcon#*after write, iclass 19, count 0 2006.173.07:29:19.79#ibcon#*before return 0, iclass 19, count 0 2006.173.07:29:19.79#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.07:29:19.79#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.07:29:19.79#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.07:29:19.79#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.07:29:19.79$vck44/vblo=4,679.99 2006.173.07:29:19.79#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.07:29:19.79#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.07:29:19.79#ibcon#ireg 17 cls_cnt 0 2006.173.07:29:19.79#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.07:29:19.79#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.07:29:19.79#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.07:29:19.79#ibcon#enter wrdev, iclass 21, count 0 2006.173.07:29:19.79#ibcon#first serial, iclass 21, count 0 2006.173.07:29:19.79#ibcon#enter sib2, iclass 21, count 0 2006.173.07:29:19.79#ibcon#flushed, iclass 21, count 0 2006.173.07:29:19.79#ibcon#about to write, iclass 21, count 0 2006.173.07:29:19.79#ibcon#wrote, iclass 21, count 0 2006.173.07:29:19.79#ibcon#about to read 3, iclass 21, count 0 2006.173.07:29:19.81#ibcon#read 3, iclass 21, count 0 2006.173.07:29:19.81#ibcon#about to read 4, iclass 21, count 0 2006.173.07:29:19.81#ibcon#read 4, iclass 21, count 0 2006.173.07:29:19.81#ibcon#about to read 5, iclass 21, count 0 2006.173.07:29:19.81#ibcon#read 5, iclass 21, count 0 2006.173.07:29:19.81#ibcon#about to read 6, iclass 21, count 0 2006.173.07:29:19.81#ibcon#read 6, iclass 21, count 0 2006.173.07:29:19.81#ibcon#end of sib2, iclass 21, count 0 2006.173.07:29:19.81#ibcon#*mode == 0, iclass 21, count 0 2006.173.07:29:19.81#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.07:29:19.81#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.07:29:19.81#ibcon#*before write, iclass 21, count 0 2006.173.07:29:19.81#ibcon#enter sib2, iclass 21, count 0 2006.173.07:29:19.81#ibcon#flushed, iclass 21, count 0 2006.173.07:29:19.81#ibcon#about to write, iclass 21, count 0 2006.173.07:29:19.81#ibcon#wrote, iclass 21, count 0 2006.173.07:29:19.81#ibcon#about to read 3, iclass 21, count 0 2006.173.07:29:19.85#ibcon#read 3, iclass 21, count 0 2006.173.07:29:19.85#ibcon#about to read 4, iclass 21, count 0 2006.173.07:29:19.85#ibcon#read 4, iclass 21, count 0 2006.173.07:29:19.85#ibcon#about to read 5, iclass 21, count 0 2006.173.07:29:19.85#ibcon#read 5, iclass 21, count 0 2006.173.07:29:19.85#ibcon#about to read 6, iclass 21, count 0 2006.173.07:29:19.85#ibcon#read 6, iclass 21, count 0 2006.173.07:29:19.85#ibcon#end of sib2, iclass 21, count 0 2006.173.07:29:19.85#ibcon#*after write, iclass 21, count 0 2006.173.07:29:19.85#ibcon#*before return 0, iclass 21, count 0 2006.173.07:29:19.85#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.07:29:19.85#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.07:29:19.85#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.07:29:19.85#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.07:29:19.85$vck44/vb=4,4 2006.173.07:29:19.85#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.07:29:19.85#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.07:29:19.85#ibcon#ireg 11 cls_cnt 2 2006.173.07:29:19.85#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.07:29:19.91#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.07:29:19.91#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.07:29:19.91#ibcon#enter wrdev, iclass 23, count 2 2006.173.07:29:19.91#ibcon#first serial, iclass 23, count 2 2006.173.07:29:19.91#ibcon#enter sib2, iclass 23, count 2 2006.173.07:29:19.91#ibcon#flushed, iclass 23, count 2 2006.173.07:29:19.91#ibcon#about to write, iclass 23, count 2 2006.173.07:29:19.91#ibcon#wrote, iclass 23, count 2 2006.173.07:29:19.91#ibcon#about to read 3, iclass 23, count 2 2006.173.07:29:19.93#ibcon#read 3, iclass 23, count 2 2006.173.07:29:19.93#ibcon#about to read 4, iclass 23, count 2 2006.173.07:29:19.93#ibcon#read 4, iclass 23, count 2 2006.173.07:29:19.93#ibcon#about to read 5, iclass 23, count 2 2006.173.07:29:19.93#ibcon#read 5, iclass 23, count 2 2006.173.07:29:19.93#ibcon#about to read 6, iclass 23, count 2 2006.173.07:29:19.93#ibcon#read 6, iclass 23, count 2 2006.173.07:29:19.93#ibcon#end of sib2, iclass 23, count 2 2006.173.07:29:19.93#ibcon#*mode == 0, iclass 23, count 2 2006.173.07:29:19.93#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.07:29:19.93#ibcon#[27=AT04-04\r\n] 2006.173.07:29:19.93#ibcon#*before write, iclass 23, count 2 2006.173.07:29:19.93#ibcon#enter sib2, iclass 23, count 2 2006.173.07:29:19.93#ibcon#flushed, iclass 23, count 2 2006.173.07:29:19.93#ibcon#about to write, iclass 23, count 2 2006.173.07:29:19.93#ibcon#wrote, iclass 23, count 2 2006.173.07:29:19.93#ibcon#about to read 3, iclass 23, count 2 2006.173.07:29:19.96#ibcon#read 3, iclass 23, count 2 2006.173.07:29:19.96#ibcon#about to read 4, iclass 23, count 2 2006.173.07:29:19.96#ibcon#read 4, iclass 23, count 2 2006.173.07:29:19.96#ibcon#about to read 5, iclass 23, count 2 2006.173.07:29:19.96#ibcon#read 5, iclass 23, count 2 2006.173.07:29:19.96#ibcon#about to read 6, iclass 23, count 2 2006.173.07:29:19.96#ibcon#read 6, iclass 23, count 2 2006.173.07:29:19.96#ibcon#end of sib2, iclass 23, count 2 2006.173.07:29:19.96#ibcon#*after write, iclass 23, count 2 2006.173.07:29:19.96#ibcon#*before return 0, iclass 23, count 2 2006.173.07:29:19.96#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.07:29:19.96#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.07:29:19.96#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.07:29:19.96#ibcon#ireg 7 cls_cnt 0 2006.173.07:29:19.96#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.07:29:20.08#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.07:29:20.08#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.07:29:20.08#ibcon#enter wrdev, iclass 23, count 0 2006.173.07:29:20.08#ibcon#first serial, iclass 23, count 0 2006.173.07:29:20.08#ibcon#enter sib2, iclass 23, count 0 2006.173.07:29:20.08#ibcon#flushed, iclass 23, count 0 2006.173.07:29:20.08#ibcon#about to write, iclass 23, count 0 2006.173.07:29:20.08#ibcon#wrote, iclass 23, count 0 2006.173.07:29:20.08#ibcon#about to read 3, iclass 23, count 0 2006.173.07:29:20.10#ibcon#read 3, iclass 23, count 0 2006.173.07:29:20.10#ibcon#about to read 4, iclass 23, count 0 2006.173.07:29:20.10#ibcon#read 4, iclass 23, count 0 2006.173.07:29:20.10#ibcon#about to read 5, iclass 23, count 0 2006.173.07:29:20.10#ibcon#read 5, iclass 23, count 0 2006.173.07:29:20.10#ibcon#about to read 6, iclass 23, count 0 2006.173.07:29:20.10#ibcon#read 6, iclass 23, count 0 2006.173.07:29:20.10#ibcon#end of sib2, iclass 23, count 0 2006.173.07:29:20.10#ibcon#*mode == 0, iclass 23, count 0 2006.173.07:29:20.10#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.07:29:20.10#ibcon#[27=USB\r\n] 2006.173.07:29:20.10#ibcon#*before write, iclass 23, count 0 2006.173.07:29:20.10#ibcon#enter sib2, iclass 23, count 0 2006.173.07:29:20.10#ibcon#flushed, iclass 23, count 0 2006.173.07:29:20.10#ibcon#about to write, iclass 23, count 0 2006.173.07:29:20.10#ibcon#wrote, iclass 23, count 0 2006.173.07:29:20.10#ibcon#about to read 3, iclass 23, count 0 2006.173.07:29:20.13#ibcon#read 3, iclass 23, count 0 2006.173.07:29:20.13#ibcon#about to read 4, iclass 23, count 0 2006.173.07:29:20.13#ibcon#read 4, iclass 23, count 0 2006.173.07:29:20.13#ibcon#about to read 5, iclass 23, count 0 2006.173.07:29:20.13#ibcon#read 5, iclass 23, count 0 2006.173.07:29:20.13#ibcon#about to read 6, iclass 23, count 0 2006.173.07:29:20.13#ibcon#read 6, iclass 23, count 0 2006.173.07:29:20.13#ibcon#end of sib2, iclass 23, count 0 2006.173.07:29:20.13#ibcon#*after write, iclass 23, count 0 2006.173.07:29:20.13#ibcon#*before return 0, iclass 23, count 0 2006.173.07:29:20.13#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.07:29:20.13#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.07:29:20.13#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.07:29:20.13#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.07:29:20.13$vck44/vblo=5,709.99 2006.173.07:29:20.13#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.07:29:20.13#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.07:29:20.13#ibcon#ireg 17 cls_cnt 0 2006.173.07:29:20.13#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.07:29:20.13#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.07:29:20.13#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.07:29:20.13#ibcon#enter wrdev, iclass 25, count 0 2006.173.07:29:20.13#ibcon#first serial, iclass 25, count 0 2006.173.07:29:20.13#ibcon#enter sib2, iclass 25, count 0 2006.173.07:29:20.13#ibcon#flushed, iclass 25, count 0 2006.173.07:29:20.13#ibcon#about to write, iclass 25, count 0 2006.173.07:29:20.13#ibcon#wrote, iclass 25, count 0 2006.173.07:29:20.13#ibcon#about to read 3, iclass 25, count 0 2006.173.07:29:20.15#ibcon#read 3, iclass 25, count 0 2006.173.07:29:20.15#ibcon#about to read 4, iclass 25, count 0 2006.173.07:29:20.15#ibcon#read 4, iclass 25, count 0 2006.173.07:29:20.15#ibcon#about to read 5, iclass 25, count 0 2006.173.07:29:20.15#ibcon#read 5, iclass 25, count 0 2006.173.07:29:20.15#ibcon#about to read 6, iclass 25, count 0 2006.173.07:29:20.15#ibcon#read 6, iclass 25, count 0 2006.173.07:29:20.15#ibcon#end of sib2, iclass 25, count 0 2006.173.07:29:20.15#ibcon#*mode == 0, iclass 25, count 0 2006.173.07:29:20.15#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.07:29:20.15#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.07:29:20.15#ibcon#*before write, iclass 25, count 0 2006.173.07:29:20.15#ibcon#enter sib2, iclass 25, count 0 2006.173.07:29:20.15#ibcon#flushed, iclass 25, count 0 2006.173.07:29:20.15#ibcon#about to write, iclass 25, count 0 2006.173.07:29:20.15#ibcon#wrote, iclass 25, count 0 2006.173.07:29:20.15#ibcon#about to read 3, iclass 25, count 0 2006.173.07:29:20.19#ibcon#read 3, iclass 25, count 0 2006.173.07:29:20.19#ibcon#about to read 4, iclass 25, count 0 2006.173.07:29:20.19#ibcon#read 4, iclass 25, count 0 2006.173.07:29:20.19#ibcon#about to read 5, iclass 25, count 0 2006.173.07:29:20.19#ibcon#read 5, iclass 25, count 0 2006.173.07:29:20.19#ibcon#about to read 6, iclass 25, count 0 2006.173.07:29:20.19#ibcon#read 6, iclass 25, count 0 2006.173.07:29:20.19#ibcon#end of sib2, iclass 25, count 0 2006.173.07:29:20.19#ibcon#*after write, iclass 25, count 0 2006.173.07:29:20.19#ibcon#*before return 0, iclass 25, count 0 2006.173.07:29:20.19#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.07:29:20.19#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.07:29:20.19#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.07:29:20.19#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.07:29:20.19$vck44/vb=5,4 2006.173.07:29:20.19#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.07:29:20.19#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.07:29:20.19#ibcon#ireg 11 cls_cnt 2 2006.173.07:29:20.19#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.07:29:20.25#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.07:29:20.25#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.07:29:20.25#ibcon#enter wrdev, iclass 27, count 2 2006.173.07:29:20.25#ibcon#first serial, iclass 27, count 2 2006.173.07:29:20.25#ibcon#enter sib2, iclass 27, count 2 2006.173.07:29:20.25#ibcon#flushed, iclass 27, count 2 2006.173.07:29:20.25#ibcon#about to write, iclass 27, count 2 2006.173.07:29:20.25#ibcon#wrote, iclass 27, count 2 2006.173.07:29:20.25#ibcon#about to read 3, iclass 27, count 2 2006.173.07:29:20.27#ibcon#read 3, iclass 27, count 2 2006.173.07:29:20.27#ibcon#about to read 4, iclass 27, count 2 2006.173.07:29:20.27#ibcon#read 4, iclass 27, count 2 2006.173.07:29:20.27#ibcon#about to read 5, iclass 27, count 2 2006.173.07:29:20.27#ibcon#read 5, iclass 27, count 2 2006.173.07:29:20.27#ibcon#about to read 6, iclass 27, count 2 2006.173.07:29:20.27#ibcon#read 6, iclass 27, count 2 2006.173.07:29:20.27#ibcon#end of sib2, iclass 27, count 2 2006.173.07:29:20.27#ibcon#*mode == 0, iclass 27, count 2 2006.173.07:29:20.27#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.07:29:20.27#ibcon#[27=AT05-04\r\n] 2006.173.07:29:20.27#ibcon#*before write, iclass 27, count 2 2006.173.07:29:20.27#ibcon#enter sib2, iclass 27, count 2 2006.173.07:29:20.27#ibcon#flushed, iclass 27, count 2 2006.173.07:29:20.27#ibcon#about to write, iclass 27, count 2 2006.173.07:29:20.27#ibcon#wrote, iclass 27, count 2 2006.173.07:29:20.27#ibcon#about to read 3, iclass 27, count 2 2006.173.07:29:20.30#ibcon#read 3, iclass 27, count 2 2006.173.07:29:20.30#ibcon#about to read 4, iclass 27, count 2 2006.173.07:29:20.30#ibcon#read 4, iclass 27, count 2 2006.173.07:29:20.30#ibcon#about to read 5, iclass 27, count 2 2006.173.07:29:20.30#ibcon#read 5, iclass 27, count 2 2006.173.07:29:20.30#ibcon#about to read 6, iclass 27, count 2 2006.173.07:29:20.30#ibcon#read 6, iclass 27, count 2 2006.173.07:29:20.30#ibcon#end of sib2, iclass 27, count 2 2006.173.07:29:20.30#ibcon#*after write, iclass 27, count 2 2006.173.07:29:20.30#ibcon#*before return 0, iclass 27, count 2 2006.173.07:29:20.30#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.07:29:20.30#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.07:29:20.30#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.07:29:20.30#ibcon#ireg 7 cls_cnt 0 2006.173.07:29:20.30#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.07:29:20.42#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.07:29:20.42#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.07:29:20.42#ibcon#enter wrdev, iclass 27, count 0 2006.173.07:29:20.42#ibcon#first serial, iclass 27, count 0 2006.173.07:29:20.42#ibcon#enter sib2, iclass 27, count 0 2006.173.07:29:20.42#ibcon#flushed, iclass 27, count 0 2006.173.07:29:20.42#ibcon#about to write, iclass 27, count 0 2006.173.07:29:20.42#ibcon#wrote, iclass 27, count 0 2006.173.07:29:20.42#ibcon#about to read 3, iclass 27, count 0 2006.173.07:29:20.44#ibcon#read 3, iclass 27, count 0 2006.173.07:29:20.44#ibcon#about to read 4, iclass 27, count 0 2006.173.07:29:20.44#ibcon#read 4, iclass 27, count 0 2006.173.07:29:20.44#ibcon#about to read 5, iclass 27, count 0 2006.173.07:29:20.44#ibcon#read 5, iclass 27, count 0 2006.173.07:29:20.44#ibcon#about to read 6, iclass 27, count 0 2006.173.07:29:20.44#ibcon#read 6, iclass 27, count 0 2006.173.07:29:20.44#ibcon#end of sib2, iclass 27, count 0 2006.173.07:29:20.44#ibcon#*mode == 0, iclass 27, count 0 2006.173.07:29:20.44#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.07:29:20.44#ibcon#[27=USB\r\n] 2006.173.07:29:20.44#ibcon#*before write, iclass 27, count 0 2006.173.07:29:20.44#ibcon#enter sib2, iclass 27, count 0 2006.173.07:29:20.44#ibcon#flushed, iclass 27, count 0 2006.173.07:29:20.44#ibcon#about to write, iclass 27, count 0 2006.173.07:29:20.44#ibcon#wrote, iclass 27, count 0 2006.173.07:29:20.44#ibcon#about to read 3, iclass 27, count 0 2006.173.07:29:20.47#ibcon#read 3, iclass 27, count 0 2006.173.07:29:20.47#ibcon#about to read 4, iclass 27, count 0 2006.173.07:29:20.47#ibcon#read 4, iclass 27, count 0 2006.173.07:29:20.47#ibcon#about to read 5, iclass 27, count 0 2006.173.07:29:20.47#ibcon#read 5, iclass 27, count 0 2006.173.07:29:20.47#ibcon#about to read 6, iclass 27, count 0 2006.173.07:29:20.47#ibcon#read 6, iclass 27, count 0 2006.173.07:29:20.47#ibcon#end of sib2, iclass 27, count 0 2006.173.07:29:20.47#ibcon#*after write, iclass 27, count 0 2006.173.07:29:20.47#ibcon#*before return 0, iclass 27, count 0 2006.173.07:29:20.47#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.07:29:20.47#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.07:29:20.47#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.07:29:20.47#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.07:29:20.47$vck44/vblo=6,719.99 2006.173.07:29:20.47#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.07:29:20.47#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.07:29:20.47#ibcon#ireg 17 cls_cnt 0 2006.173.07:29:20.47#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.07:29:20.47#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.07:29:20.47#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.07:29:20.47#ibcon#enter wrdev, iclass 29, count 0 2006.173.07:29:20.47#ibcon#first serial, iclass 29, count 0 2006.173.07:29:20.47#ibcon#enter sib2, iclass 29, count 0 2006.173.07:29:20.47#ibcon#flushed, iclass 29, count 0 2006.173.07:29:20.47#ibcon#about to write, iclass 29, count 0 2006.173.07:29:20.47#ibcon#wrote, iclass 29, count 0 2006.173.07:29:20.47#ibcon#about to read 3, iclass 29, count 0 2006.173.07:29:20.49#ibcon#read 3, iclass 29, count 0 2006.173.07:29:20.49#ibcon#about to read 4, iclass 29, count 0 2006.173.07:29:20.49#ibcon#read 4, iclass 29, count 0 2006.173.07:29:20.49#ibcon#about to read 5, iclass 29, count 0 2006.173.07:29:20.49#ibcon#read 5, iclass 29, count 0 2006.173.07:29:20.49#ibcon#about to read 6, iclass 29, count 0 2006.173.07:29:20.49#ibcon#read 6, iclass 29, count 0 2006.173.07:29:20.49#ibcon#end of sib2, iclass 29, count 0 2006.173.07:29:20.49#ibcon#*mode == 0, iclass 29, count 0 2006.173.07:29:20.49#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.07:29:20.49#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.07:29:20.49#ibcon#*before write, iclass 29, count 0 2006.173.07:29:20.49#ibcon#enter sib2, iclass 29, count 0 2006.173.07:29:20.49#ibcon#flushed, iclass 29, count 0 2006.173.07:29:20.49#ibcon#about to write, iclass 29, count 0 2006.173.07:29:20.49#ibcon#wrote, iclass 29, count 0 2006.173.07:29:20.49#ibcon#about to read 3, iclass 29, count 0 2006.173.07:29:20.53#ibcon#read 3, iclass 29, count 0 2006.173.07:29:20.53#ibcon#about to read 4, iclass 29, count 0 2006.173.07:29:20.53#ibcon#read 4, iclass 29, count 0 2006.173.07:29:20.53#ibcon#about to read 5, iclass 29, count 0 2006.173.07:29:20.53#ibcon#read 5, iclass 29, count 0 2006.173.07:29:20.53#ibcon#about to read 6, iclass 29, count 0 2006.173.07:29:20.53#ibcon#read 6, iclass 29, count 0 2006.173.07:29:20.53#ibcon#end of sib2, iclass 29, count 0 2006.173.07:29:20.53#ibcon#*after write, iclass 29, count 0 2006.173.07:29:20.53#ibcon#*before return 0, iclass 29, count 0 2006.173.07:29:20.53#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.07:29:20.53#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.07:29:20.53#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.07:29:20.53#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.07:29:20.53$vck44/vb=6,4 2006.173.07:29:20.53#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.07:29:20.53#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.07:29:20.53#ibcon#ireg 11 cls_cnt 2 2006.173.07:29:20.53#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.07:29:20.59#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.07:29:20.59#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.07:29:20.59#ibcon#enter wrdev, iclass 31, count 2 2006.173.07:29:20.59#ibcon#first serial, iclass 31, count 2 2006.173.07:29:20.59#ibcon#enter sib2, iclass 31, count 2 2006.173.07:29:20.59#ibcon#flushed, iclass 31, count 2 2006.173.07:29:20.59#ibcon#about to write, iclass 31, count 2 2006.173.07:29:20.59#ibcon#wrote, iclass 31, count 2 2006.173.07:29:20.59#ibcon#about to read 3, iclass 31, count 2 2006.173.07:29:20.61#ibcon#read 3, iclass 31, count 2 2006.173.07:29:20.61#ibcon#about to read 4, iclass 31, count 2 2006.173.07:29:20.61#ibcon#read 4, iclass 31, count 2 2006.173.07:29:20.61#ibcon#about to read 5, iclass 31, count 2 2006.173.07:29:20.61#ibcon#read 5, iclass 31, count 2 2006.173.07:29:20.61#ibcon#about to read 6, iclass 31, count 2 2006.173.07:29:20.61#ibcon#read 6, iclass 31, count 2 2006.173.07:29:20.61#ibcon#end of sib2, iclass 31, count 2 2006.173.07:29:20.61#ibcon#*mode == 0, iclass 31, count 2 2006.173.07:29:20.61#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.07:29:20.61#ibcon#[27=AT06-04\r\n] 2006.173.07:29:20.61#ibcon#*before write, iclass 31, count 2 2006.173.07:29:20.61#ibcon#enter sib2, iclass 31, count 2 2006.173.07:29:20.61#ibcon#flushed, iclass 31, count 2 2006.173.07:29:20.61#ibcon#about to write, iclass 31, count 2 2006.173.07:29:20.61#ibcon#wrote, iclass 31, count 2 2006.173.07:29:20.61#ibcon#about to read 3, iclass 31, count 2 2006.173.07:29:20.64#ibcon#read 3, iclass 31, count 2 2006.173.07:29:20.64#ibcon#about to read 4, iclass 31, count 2 2006.173.07:29:20.64#ibcon#read 4, iclass 31, count 2 2006.173.07:29:20.64#ibcon#about to read 5, iclass 31, count 2 2006.173.07:29:20.64#ibcon#read 5, iclass 31, count 2 2006.173.07:29:20.64#ibcon#about to read 6, iclass 31, count 2 2006.173.07:29:20.64#ibcon#read 6, iclass 31, count 2 2006.173.07:29:20.64#ibcon#end of sib2, iclass 31, count 2 2006.173.07:29:20.64#ibcon#*after write, iclass 31, count 2 2006.173.07:29:20.64#ibcon#*before return 0, iclass 31, count 2 2006.173.07:29:20.64#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.07:29:20.64#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.07:29:20.64#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.07:29:20.64#ibcon#ireg 7 cls_cnt 0 2006.173.07:29:20.64#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.07:29:20.76#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.07:29:20.76#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.07:29:20.76#ibcon#enter wrdev, iclass 31, count 0 2006.173.07:29:20.76#ibcon#first serial, iclass 31, count 0 2006.173.07:29:20.76#ibcon#enter sib2, iclass 31, count 0 2006.173.07:29:20.76#ibcon#flushed, iclass 31, count 0 2006.173.07:29:20.76#ibcon#about to write, iclass 31, count 0 2006.173.07:29:20.76#ibcon#wrote, iclass 31, count 0 2006.173.07:29:20.76#ibcon#about to read 3, iclass 31, count 0 2006.173.07:29:20.78#ibcon#read 3, iclass 31, count 0 2006.173.07:29:20.78#ibcon#about to read 4, iclass 31, count 0 2006.173.07:29:20.78#ibcon#read 4, iclass 31, count 0 2006.173.07:29:20.78#ibcon#about to read 5, iclass 31, count 0 2006.173.07:29:20.78#ibcon#read 5, iclass 31, count 0 2006.173.07:29:20.78#ibcon#about to read 6, iclass 31, count 0 2006.173.07:29:20.78#ibcon#read 6, iclass 31, count 0 2006.173.07:29:20.78#ibcon#end of sib2, iclass 31, count 0 2006.173.07:29:20.78#ibcon#*mode == 0, iclass 31, count 0 2006.173.07:29:20.78#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.07:29:20.78#ibcon#[27=USB\r\n] 2006.173.07:29:20.78#ibcon#*before write, iclass 31, count 0 2006.173.07:29:20.78#ibcon#enter sib2, iclass 31, count 0 2006.173.07:29:20.78#ibcon#flushed, iclass 31, count 0 2006.173.07:29:20.78#ibcon#about to write, iclass 31, count 0 2006.173.07:29:20.78#ibcon#wrote, iclass 31, count 0 2006.173.07:29:20.78#ibcon#about to read 3, iclass 31, count 0 2006.173.07:29:20.81#ibcon#read 3, iclass 31, count 0 2006.173.07:29:20.81#ibcon#about to read 4, iclass 31, count 0 2006.173.07:29:20.81#ibcon#read 4, iclass 31, count 0 2006.173.07:29:20.81#ibcon#about to read 5, iclass 31, count 0 2006.173.07:29:20.81#ibcon#read 5, iclass 31, count 0 2006.173.07:29:20.81#ibcon#about to read 6, iclass 31, count 0 2006.173.07:29:20.81#ibcon#read 6, iclass 31, count 0 2006.173.07:29:20.81#ibcon#end of sib2, iclass 31, count 0 2006.173.07:29:20.81#ibcon#*after write, iclass 31, count 0 2006.173.07:29:20.81#ibcon#*before return 0, iclass 31, count 0 2006.173.07:29:20.81#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.07:29:20.81#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.07:29:20.81#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.07:29:20.81#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.07:29:20.81$vck44/vblo=7,734.99 2006.173.07:29:20.81#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.07:29:20.81#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.07:29:20.81#ibcon#ireg 17 cls_cnt 0 2006.173.07:29:20.81#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.07:29:20.81#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.07:29:20.81#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.07:29:20.81#ibcon#enter wrdev, iclass 33, count 0 2006.173.07:29:20.81#ibcon#first serial, iclass 33, count 0 2006.173.07:29:20.81#ibcon#enter sib2, iclass 33, count 0 2006.173.07:29:20.81#ibcon#flushed, iclass 33, count 0 2006.173.07:29:20.81#ibcon#about to write, iclass 33, count 0 2006.173.07:29:20.81#ibcon#wrote, iclass 33, count 0 2006.173.07:29:20.81#ibcon#about to read 3, iclass 33, count 0 2006.173.07:29:20.83#ibcon#read 3, iclass 33, count 0 2006.173.07:29:20.83#ibcon#about to read 4, iclass 33, count 0 2006.173.07:29:20.83#ibcon#read 4, iclass 33, count 0 2006.173.07:29:20.83#ibcon#about to read 5, iclass 33, count 0 2006.173.07:29:20.83#ibcon#read 5, iclass 33, count 0 2006.173.07:29:20.83#ibcon#about to read 6, iclass 33, count 0 2006.173.07:29:20.83#ibcon#read 6, iclass 33, count 0 2006.173.07:29:20.83#ibcon#end of sib2, iclass 33, count 0 2006.173.07:29:20.83#ibcon#*mode == 0, iclass 33, count 0 2006.173.07:29:20.83#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.07:29:20.83#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.07:29:20.83#ibcon#*before write, iclass 33, count 0 2006.173.07:29:20.83#ibcon#enter sib2, iclass 33, count 0 2006.173.07:29:20.83#ibcon#flushed, iclass 33, count 0 2006.173.07:29:20.83#ibcon#about to write, iclass 33, count 0 2006.173.07:29:20.83#ibcon#wrote, iclass 33, count 0 2006.173.07:29:20.83#ibcon#about to read 3, iclass 33, count 0 2006.173.07:29:20.87#ibcon#read 3, iclass 33, count 0 2006.173.07:29:20.87#ibcon#about to read 4, iclass 33, count 0 2006.173.07:29:20.87#ibcon#read 4, iclass 33, count 0 2006.173.07:29:20.87#ibcon#about to read 5, iclass 33, count 0 2006.173.07:29:20.87#ibcon#read 5, iclass 33, count 0 2006.173.07:29:20.87#ibcon#about to read 6, iclass 33, count 0 2006.173.07:29:20.87#ibcon#read 6, iclass 33, count 0 2006.173.07:29:20.87#ibcon#end of sib2, iclass 33, count 0 2006.173.07:29:20.87#ibcon#*after write, iclass 33, count 0 2006.173.07:29:20.87#ibcon#*before return 0, iclass 33, count 0 2006.173.07:29:20.87#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.07:29:20.87#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.07:29:20.87#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.07:29:20.87#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.07:29:20.87$vck44/vb=7,4 2006.173.07:29:20.87#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.07:29:20.87#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.07:29:20.87#ibcon#ireg 11 cls_cnt 2 2006.173.07:29:20.87#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.07:29:20.93#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.07:29:20.93#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.07:29:20.93#ibcon#enter wrdev, iclass 35, count 2 2006.173.07:29:20.93#ibcon#first serial, iclass 35, count 2 2006.173.07:29:20.93#ibcon#enter sib2, iclass 35, count 2 2006.173.07:29:20.93#ibcon#flushed, iclass 35, count 2 2006.173.07:29:20.93#ibcon#about to write, iclass 35, count 2 2006.173.07:29:20.93#ibcon#wrote, iclass 35, count 2 2006.173.07:29:20.93#ibcon#about to read 3, iclass 35, count 2 2006.173.07:29:20.95#ibcon#read 3, iclass 35, count 2 2006.173.07:29:20.95#ibcon#about to read 4, iclass 35, count 2 2006.173.07:29:20.95#ibcon#read 4, iclass 35, count 2 2006.173.07:29:20.95#ibcon#about to read 5, iclass 35, count 2 2006.173.07:29:20.95#ibcon#read 5, iclass 35, count 2 2006.173.07:29:20.95#ibcon#about to read 6, iclass 35, count 2 2006.173.07:29:20.95#ibcon#read 6, iclass 35, count 2 2006.173.07:29:20.95#ibcon#end of sib2, iclass 35, count 2 2006.173.07:29:20.95#ibcon#*mode == 0, iclass 35, count 2 2006.173.07:29:20.95#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.07:29:20.95#ibcon#[27=AT07-04\r\n] 2006.173.07:29:20.95#ibcon#*before write, iclass 35, count 2 2006.173.07:29:20.95#ibcon#enter sib2, iclass 35, count 2 2006.173.07:29:20.95#ibcon#flushed, iclass 35, count 2 2006.173.07:29:20.95#ibcon#about to write, iclass 35, count 2 2006.173.07:29:20.95#ibcon#wrote, iclass 35, count 2 2006.173.07:29:20.95#ibcon#about to read 3, iclass 35, count 2 2006.173.07:29:20.98#ibcon#read 3, iclass 35, count 2 2006.173.07:29:20.98#ibcon#about to read 4, iclass 35, count 2 2006.173.07:29:20.98#ibcon#read 4, iclass 35, count 2 2006.173.07:29:20.98#ibcon#about to read 5, iclass 35, count 2 2006.173.07:29:20.98#ibcon#read 5, iclass 35, count 2 2006.173.07:29:20.98#ibcon#about to read 6, iclass 35, count 2 2006.173.07:29:20.98#ibcon#read 6, iclass 35, count 2 2006.173.07:29:20.98#ibcon#end of sib2, iclass 35, count 2 2006.173.07:29:20.98#ibcon#*after write, iclass 35, count 2 2006.173.07:29:20.98#ibcon#*before return 0, iclass 35, count 2 2006.173.07:29:20.98#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.07:29:20.98#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.07:29:20.98#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.07:29:20.98#ibcon#ireg 7 cls_cnt 0 2006.173.07:29:20.98#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.07:29:21.10#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.07:29:21.10#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.07:29:21.10#ibcon#enter wrdev, iclass 35, count 0 2006.173.07:29:21.10#ibcon#first serial, iclass 35, count 0 2006.173.07:29:21.10#ibcon#enter sib2, iclass 35, count 0 2006.173.07:29:21.10#ibcon#flushed, iclass 35, count 0 2006.173.07:29:21.10#ibcon#about to write, iclass 35, count 0 2006.173.07:29:21.10#ibcon#wrote, iclass 35, count 0 2006.173.07:29:21.10#ibcon#about to read 3, iclass 35, count 0 2006.173.07:29:21.12#ibcon#read 3, iclass 35, count 0 2006.173.07:29:21.12#ibcon#about to read 4, iclass 35, count 0 2006.173.07:29:21.12#ibcon#read 4, iclass 35, count 0 2006.173.07:29:21.12#ibcon#about to read 5, iclass 35, count 0 2006.173.07:29:21.12#ibcon#read 5, iclass 35, count 0 2006.173.07:29:21.12#ibcon#about to read 6, iclass 35, count 0 2006.173.07:29:21.12#ibcon#read 6, iclass 35, count 0 2006.173.07:29:21.12#ibcon#end of sib2, iclass 35, count 0 2006.173.07:29:21.12#ibcon#*mode == 0, iclass 35, count 0 2006.173.07:29:21.12#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.07:29:21.12#ibcon#[27=USB\r\n] 2006.173.07:29:21.12#ibcon#*before write, iclass 35, count 0 2006.173.07:29:21.12#ibcon#enter sib2, iclass 35, count 0 2006.173.07:29:21.12#ibcon#flushed, iclass 35, count 0 2006.173.07:29:21.12#ibcon#about to write, iclass 35, count 0 2006.173.07:29:21.12#ibcon#wrote, iclass 35, count 0 2006.173.07:29:21.12#ibcon#about to read 3, iclass 35, count 0 2006.173.07:29:21.15#ibcon#read 3, iclass 35, count 0 2006.173.07:29:21.15#ibcon#about to read 4, iclass 35, count 0 2006.173.07:29:21.15#ibcon#read 4, iclass 35, count 0 2006.173.07:29:21.15#ibcon#about to read 5, iclass 35, count 0 2006.173.07:29:21.15#ibcon#read 5, iclass 35, count 0 2006.173.07:29:21.15#ibcon#about to read 6, iclass 35, count 0 2006.173.07:29:21.15#ibcon#read 6, iclass 35, count 0 2006.173.07:29:21.15#ibcon#end of sib2, iclass 35, count 0 2006.173.07:29:21.15#ibcon#*after write, iclass 35, count 0 2006.173.07:29:21.15#ibcon#*before return 0, iclass 35, count 0 2006.173.07:29:21.15#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.07:29:21.15#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.07:29:21.15#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.07:29:21.15#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.07:29:21.15$vck44/vblo=8,744.99 2006.173.07:29:21.15#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.07:29:21.15#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.07:29:21.15#ibcon#ireg 17 cls_cnt 0 2006.173.07:29:21.15#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.07:29:21.15#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.07:29:21.15#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.07:29:21.15#ibcon#enter wrdev, iclass 37, count 0 2006.173.07:29:21.15#ibcon#first serial, iclass 37, count 0 2006.173.07:29:21.15#ibcon#enter sib2, iclass 37, count 0 2006.173.07:29:21.15#ibcon#flushed, iclass 37, count 0 2006.173.07:29:21.15#ibcon#about to write, iclass 37, count 0 2006.173.07:29:21.15#ibcon#wrote, iclass 37, count 0 2006.173.07:29:21.15#ibcon#about to read 3, iclass 37, count 0 2006.173.07:29:21.17#ibcon#read 3, iclass 37, count 0 2006.173.07:29:21.17#ibcon#about to read 4, iclass 37, count 0 2006.173.07:29:21.17#ibcon#read 4, iclass 37, count 0 2006.173.07:29:21.17#ibcon#about to read 5, iclass 37, count 0 2006.173.07:29:21.17#ibcon#read 5, iclass 37, count 0 2006.173.07:29:21.17#ibcon#about to read 6, iclass 37, count 0 2006.173.07:29:21.17#ibcon#read 6, iclass 37, count 0 2006.173.07:29:21.17#ibcon#end of sib2, iclass 37, count 0 2006.173.07:29:21.17#ibcon#*mode == 0, iclass 37, count 0 2006.173.07:29:21.17#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.07:29:21.17#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.07:29:21.17#ibcon#*before write, iclass 37, count 0 2006.173.07:29:21.17#ibcon#enter sib2, iclass 37, count 0 2006.173.07:29:21.17#ibcon#flushed, iclass 37, count 0 2006.173.07:29:21.17#ibcon#about to write, iclass 37, count 0 2006.173.07:29:21.17#ibcon#wrote, iclass 37, count 0 2006.173.07:29:21.17#ibcon#about to read 3, iclass 37, count 0 2006.173.07:29:21.21#ibcon#read 3, iclass 37, count 0 2006.173.07:29:21.21#ibcon#about to read 4, iclass 37, count 0 2006.173.07:29:21.21#ibcon#read 4, iclass 37, count 0 2006.173.07:29:21.21#ibcon#about to read 5, iclass 37, count 0 2006.173.07:29:21.21#ibcon#read 5, iclass 37, count 0 2006.173.07:29:21.21#ibcon#about to read 6, iclass 37, count 0 2006.173.07:29:21.21#ibcon#read 6, iclass 37, count 0 2006.173.07:29:21.21#ibcon#end of sib2, iclass 37, count 0 2006.173.07:29:21.21#ibcon#*after write, iclass 37, count 0 2006.173.07:29:21.21#ibcon#*before return 0, iclass 37, count 0 2006.173.07:29:21.21#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.07:29:21.21#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.07:29:21.21#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.07:29:21.21#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.07:29:21.21$vck44/vb=8,4 2006.173.07:29:21.21#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.07:29:21.21#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.07:29:21.21#ibcon#ireg 11 cls_cnt 2 2006.173.07:29:21.21#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.07:29:21.27#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.07:29:21.27#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.07:29:21.27#ibcon#enter wrdev, iclass 39, count 2 2006.173.07:29:21.27#ibcon#first serial, iclass 39, count 2 2006.173.07:29:21.27#ibcon#enter sib2, iclass 39, count 2 2006.173.07:29:21.27#ibcon#flushed, iclass 39, count 2 2006.173.07:29:21.27#ibcon#about to write, iclass 39, count 2 2006.173.07:29:21.27#ibcon#wrote, iclass 39, count 2 2006.173.07:29:21.27#ibcon#about to read 3, iclass 39, count 2 2006.173.07:29:21.29#ibcon#read 3, iclass 39, count 2 2006.173.07:29:21.29#ibcon#about to read 4, iclass 39, count 2 2006.173.07:29:21.29#ibcon#read 4, iclass 39, count 2 2006.173.07:29:21.29#ibcon#about to read 5, iclass 39, count 2 2006.173.07:29:21.29#ibcon#read 5, iclass 39, count 2 2006.173.07:29:21.29#ibcon#about to read 6, iclass 39, count 2 2006.173.07:29:21.29#ibcon#read 6, iclass 39, count 2 2006.173.07:29:21.29#ibcon#end of sib2, iclass 39, count 2 2006.173.07:29:21.29#ibcon#*mode == 0, iclass 39, count 2 2006.173.07:29:21.29#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.07:29:21.29#ibcon#[27=AT08-04\r\n] 2006.173.07:29:21.29#ibcon#*before write, iclass 39, count 2 2006.173.07:29:21.29#ibcon#enter sib2, iclass 39, count 2 2006.173.07:29:21.29#ibcon#flushed, iclass 39, count 2 2006.173.07:29:21.29#ibcon#about to write, iclass 39, count 2 2006.173.07:29:21.29#ibcon#wrote, iclass 39, count 2 2006.173.07:29:21.29#ibcon#about to read 3, iclass 39, count 2 2006.173.07:29:21.32#ibcon#read 3, iclass 39, count 2 2006.173.07:29:21.32#ibcon#about to read 4, iclass 39, count 2 2006.173.07:29:21.32#ibcon#read 4, iclass 39, count 2 2006.173.07:29:21.32#ibcon#about to read 5, iclass 39, count 2 2006.173.07:29:21.32#ibcon#read 5, iclass 39, count 2 2006.173.07:29:21.32#ibcon#about to read 6, iclass 39, count 2 2006.173.07:29:21.32#ibcon#read 6, iclass 39, count 2 2006.173.07:29:21.32#ibcon#end of sib2, iclass 39, count 2 2006.173.07:29:21.32#ibcon#*after write, iclass 39, count 2 2006.173.07:29:21.32#ibcon#*before return 0, iclass 39, count 2 2006.173.07:29:21.32#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.07:29:21.32#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.07:29:21.32#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.07:29:21.32#ibcon#ireg 7 cls_cnt 0 2006.173.07:29:21.32#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.07:29:21.44#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.07:29:21.44#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.07:29:21.44#ibcon#enter wrdev, iclass 39, count 0 2006.173.07:29:21.44#ibcon#first serial, iclass 39, count 0 2006.173.07:29:21.44#ibcon#enter sib2, iclass 39, count 0 2006.173.07:29:21.44#ibcon#flushed, iclass 39, count 0 2006.173.07:29:21.44#ibcon#about to write, iclass 39, count 0 2006.173.07:29:21.44#ibcon#wrote, iclass 39, count 0 2006.173.07:29:21.44#ibcon#about to read 3, iclass 39, count 0 2006.173.07:29:21.46#ibcon#read 3, iclass 39, count 0 2006.173.07:29:21.46#ibcon#about to read 4, iclass 39, count 0 2006.173.07:29:21.46#ibcon#read 4, iclass 39, count 0 2006.173.07:29:21.46#ibcon#about to read 5, iclass 39, count 0 2006.173.07:29:21.46#ibcon#read 5, iclass 39, count 0 2006.173.07:29:21.46#ibcon#about to read 6, iclass 39, count 0 2006.173.07:29:21.46#ibcon#read 6, iclass 39, count 0 2006.173.07:29:21.46#ibcon#end of sib2, iclass 39, count 0 2006.173.07:29:21.46#ibcon#*mode == 0, iclass 39, count 0 2006.173.07:29:21.46#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.07:29:21.46#ibcon#[27=USB\r\n] 2006.173.07:29:21.46#ibcon#*before write, iclass 39, count 0 2006.173.07:29:21.46#ibcon#enter sib2, iclass 39, count 0 2006.173.07:29:21.46#ibcon#flushed, iclass 39, count 0 2006.173.07:29:21.46#ibcon#about to write, iclass 39, count 0 2006.173.07:29:21.46#ibcon#wrote, iclass 39, count 0 2006.173.07:29:21.46#ibcon#about to read 3, iclass 39, count 0 2006.173.07:29:21.49#ibcon#read 3, iclass 39, count 0 2006.173.07:29:21.49#ibcon#about to read 4, iclass 39, count 0 2006.173.07:29:21.49#ibcon#read 4, iclass 39, count 0 2006.173.07:29:21.49#ibcon#about to read 5, iclass 39, count 0 2006.173.07:29:21.49#ibcon#read 5, iclass 39, count 0 2006.173.07:29:21.49#ibcon#about to read 6, iclass 39, count 0 2006.173.07:29:21.49#ibcon#read 6, iclass 39, count 0 2006.173.07:29:21.49#ibcon#end of sib2, iclass 39, count 0 2006.173.07:29:21.49#ibcon#*after write, iclass 39, count 0 2006.173.07:29:21.49#ibcon#*before return 0, iclass 39, count 0 2006.173.07:29:21.49#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.07:29:21.49#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.07:29:21.49#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.07:29:21.49#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.07:29:21.49$vck44/vabw=wide 2006.173.07:29:21.49#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.07:29:21.49#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.07:29:21.49#ibcon#ireg 8 cls_cnt 0 2006.173.07:29:21.49#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.07:29:21.49#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.07:29:21.49#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.07:29:21.49#ibcon#enter wrdev, iclass 3, count 0 2006.173.07:29:21.49#ibcon#first serial, iclass 3, count 0 2006.173.07:29:21.49#ibcon#enter sib2, iclass 3, count 0 2006.173.07:29:21.49#ibcon#flushed, iclass 3, count 0 2006.173.07:29:21.49#ibcon#about to write, iclass 3, count 0 2006.173.07:29:21.49#ibcon#wrote, iclass 3, count 0 2006.173.07:29:21.49#ibcon#about to read 3, iclass 3, count 0 2006.173.07:29:21.51#ibcon#read 3, iclass 3, count 0 2006.173.07:29:21.51#ibcon#about to read 4, iclass 3, count 0 2006.173.07:29:21.51#ibcon#read 4, iclass 3, count 0 2006.173.07:29:21.51#ibcon#about to read 5, iclass 3, count 0 2006.173.07:29:21.51#ibcon#read 5, iclass 3, count 0 2006.173.07:29:21.51#ibcon#about to read 6, iclass 3, count 0 2006.173.07:29:21.51#ibcon#read 6, iclass 3, count 0 2006.173.07:29:21.51#ibcon#end of sib2, iclass 3, count 0 2006.173.07:29:21.51#ibcon#*mode == 0, iclass 3, count 0 2006.173.07:29:21.51#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.07:29:21.51#ibcon#[25=BW32\r\n] 2006.173.07:29:21.51#ibcon#*before write, iclass 3, count 0 2006.173.07:29:21.51#ibcon#enter sib2, iclass 3, count 0 2006.173.07:29:21.51#ibcon#flushed, iclass 3, count 0 2006.173.07:29:21.51#ibcon#about to write, iclass 3, count 0 2006.173.07:29:21.51#ibcon#wrote, iclass 3, count 0 2006.173.07:29:21.51#ibcon#about to read 3, iclass 3, count 0 2006.173.07:29:21.54#ibcon#read 3, iclass 3, count 0 2006.173.07:29:21.54#ibcon#about to read 4, iclass 3, count 0 2006.173.07:29:21.54#ibcon#read 4, iclass 3, count 0 2006.173.07:29:21.54#ibcon#about to read 5, iclass 3, count 0 2006.173.07:29:21.54#ibcon#read 5, iclass 3, count 0 2006.173.07:29:21.54#ibcon#about to read 6, iclass 3, count 0 2006.173.07:29:21.54#ibcon#read 6, iclass 3, count 0 2006.173.07:29:21.54#ibcon#end of sib2, iclass 3, count 0 2006.173.07:29:21.54#ibcon#*after write, iclass 3, count 0 2006.173.07:29:21.54#ibcon#*before return 0, iclass 3, count 0 2006.173.07:29:21.54#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.07:29:21.54#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.07:29:21.54#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.07:29:21.54#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.07:29:21.54$vck44/vbbw=wide 2006.173.07:29:21.54#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.07:29:21.54#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.07:29:21.54#ibcon#ireg 8 cls_cnt 0 2006.173.07:29:21.54#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.07:29:21.61#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.07:29:21.61#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.07:29:21.61#ibcon#enter wrdev, iclass 5, count 0 2006.173.07:29:21.61#ibcon#first serial, iclass 5, count 0 2006.173.07:29:21.61#ibcon#enter sib2, iclass 5, count 0 2006.173.07:29:21.61#ibcon#flushed, iclass 5, count 0 2006.173.07:29:21.61#ibcon#about to write, iclass 5, count 0 2006.173.07:29:21.61#ibcon#wrote, iclass 5, count 0 2006.173.07:29:21.61#ibcon#about to read 3, iclass 5, count 0 2006.173.07:29:21.63#ibcon#read 3, iclass 5, count 0 2006.173.07:29:21.63#ibcon#about to read 4, iclass 5, count 0 2006.173.07:29:21.63#ibcon#read 4, iclass 5, count 0 2006.173.07:29:21.63#ibcon#about to read 5, iclass 5, count 0 2006.173.07:29:21.63#ibcon#read 5, iclass 5, count 0 2006.173.07:29:21.63#ibcon#about to read 6, iclass 5, count 0 2006.173.07:29:21.63#ibcon#read 6, iclass 5, count 0 2006.173.07:29:21.63#ibcon#end of sib2, iclass 5, count 0 2006.173.07:29:21.63#ibcon#*mode == 0, iclass 5, count 0 2006.173.07:29:21.63#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.07:29:21.63#ibcon#[27=BW32\r\n] 2006.173.07:29:21.63#ibcon#*before write, iclass 5, count 0 2006.173.07:29:21.63#ibcon#enter sib2, iclass 5, count 0 2006.173.07:29:21.63#ibcon#flushed, iclass 5, count 0 2006.173.07:29:21.63#ibcon#about to write, iclass 5, count 0 2006.173.07:29:21.63#ibcon#wrote, iclass 5, count 0 2006.173.07:29:21.63#ibcon#about to read 3, iclass 5, count 0 2006.173.07:29:21.66#ibcon#read 3, iclass 5, count 0 2006.173.07:29:21.66#ibcon#about to read 4, iclass 5, count 0 2006.173.07:29:21.66#ibcon#read 4, iclass 5, count 0 2006.173.07:29:21.66#ibcon#about to read 5, iclass 5, count 0 2006.173.07:29:21.66#ibcon#read 5, iclass 5, count 0 2006.173.07:29:21.66#ibcon#about to read 6, iclass 5, count 0 2006.173.07:29:21.66#ibcon#read 6, iclass 5, count 0 2006.173.07:29:21.66#ibcon#end of sib2, iclass 5, count 0 2006.173.07:29:21.66#ibcon#*after write, iclass 5, count 0 2006.173.07:29:21.66#ibcon#*before return 0, iclass 5, count 0 2006.173.07:29:21.66#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.07:29:21.66#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.07:29:21.66#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.07:29:21.66#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.07:29:21.66$setupk4/ifdk4 2006.173.07:29:21.66$ifdk4/lo= 2006.173.07:29:21.66$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.07:29:21.66$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.07:29:21.66$ifdk4/patch= 2006.173.07:29:21.66$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.07:29:21.66$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.07:29:21.66$setupk4/!*+20s 2006.173.07:29:24.28#abcon#<5=/01 0.4 0.9 23.77 821004.5\r\n> 2006.173.07:29:24.30#abcon#{5=INTERFACE CLEAR} 2006.173.07:29:24.36#abcon#[5=S1D000X0/0*\r\n] 2006.173.07:29:34.45#abcon#<5=/01 0.4 0.9 23.77 821004.5\r\n> 2006.173.07:29:34.47#abcon#{5=INTERFACE CLEAR} 2006.173.07:29:34.53#abcon#[5=S1D000X0/0*\r\n] 2006.173.07:29:36.17$setupk4/"tpicd 2006.173.07:29:36.17$setupk4/echo=off 2006.173.07:29:36.17$setupk4/xlog=off 2006.173.07:29:36.17:!2006.173.07:36:47 2006.173.07:30:11.14#trakl#Source acquired 2006.173.07:30:12.14#flagr#flagr/antenna,acquired 2006.173.07:36:47.00:preob 2006.173.07:36:47.13/onsource/TRACKING 2006.173.07:36:47.13:!2006.173.07:36:57 2006.173.07:36:57.00:"tape 2006.173.07:36:57.00:"st=record 2006.173.07:36:57.00:data_valid=on 2006.173.07:36:57.00:midob 2006.173.07:36:57.13/onsource/TRACKING 2006.173.07:36:57.13/wx/23.74,1004.5,85 2006.173.07:36:57.32/cable/+6.5031E-03 2006.173.07:36:58.41/va/01,07,usb,yes,36,38 2006.173.07:36:58.41/va/02,06,usb,yes,35,36 2006.173.07:36:58.41/va/03,05,usb,yes,45,47 2006.173.07:36:58.41/va/04,06,usb,yes,36,38 2006.173.07:36:58.41/va/05,04,usb,yes,28,29 2006.173.07:36:58.41/va/06,03,usb,yes,40,40 2006.173.07:36:58.41/va/07,04,usb,yes,32,33 2006.173.07:36:58.41/va/08,04,usb,yes,27,33 2006.173.07:36:58.64/valo/01,524.99,yes,locked 2006.173.07:36:58.64/valo/02,534.99,yes,locked 2006.173.07:36:58.64/valo/03,564.99,yes,locked 2006.173.07:36:58.64/valo/04,624.99,yes,locked 2006.173.07:36:58.64/valo/05,734.99,yes,locked 2006.173.07:36:58.64/valo/06,814.99,yes,locked 2006.173.07:36:58.64/valo/07,864.99,yes,locked 2006.173.07:36:58.64/valo/08,884.99,yes,locked 2006.173.07:36:59.73/vb/01,04,usb,yes,30,27 2006.173.07:36:59.73/vb/02,04,usb,yes,32,32 2006.173.07:36:59.73/vb/03,04,usb,yes,29,32 2006.173.07:36:59.73/vb/04,04,usb,yes,33,32 2006.173.07:36:59.73/vb/05,04,usb,yes,26,29 2006.173.07:36:59.73/vb/06,04,usb,yes,30,27 2006.173.07:36:59.73/vb/07,04,usb,yes,31,30 2006.173.07:36:59.73/vb/08,04,usb,yes,31,31 2006.173.07:36:59.97/vblo/01,629.99,yes,locked 2006.173.07:36:59.97/vblo/02,634.99,yes,locked 2006.173.07:36:59.97/vblo/03,649.99,yes,locked 2006.173.07:36:59.97/vblo/04,679.99,yes,locked 2006.173.07:36:59.97/vblo/05,709.99,yes,locked 2006.173.07:36:59.97/vblo/06,719.99,yes,locked 2006.173.07:36:59.97/vblo/07,734.99,yes,locked 2006.173.07:36:59.97/vblo/08,744.99,yes,locked 2006.173.07:37:00.12/vabw/8 2006.173.07:37:00.27/vbbw/8 2006.173.07:37:00.36/xfe/off,on,14.5 2006.173.07:37:00.74/ifatt/23,28,28,28 2006.173.07:37:01.07/fmout-gps/S +3.97E-07 2006.173.07:37:01.11:!2006.173.07:37:47 2006.173.07:37:47.00:data_valid=off 2006.173.07:37:47.00:"et 2006.173.07:37:47.00:!+3s 2006.173.07:37:50.01:"tape 2006.173.07:37:50.01:postob 2006.173.07:37:50.20/cable/+6.5023E-03 2006.173.07:37:50.20/wx/23.75,1004.4,85 2006.173.07:37:51.08/fmout-gps/S +3.97E-07 2006.173.07:37:51.08:scan_name=173-0740,jd0606,220 2006.173.07:37:51.08:source=1044+719,104827.62,714335.9,2000.0,neutral 2006.173.07:37:52.14#flagr#flagr/antenna,new-source 2006.173.07:37:52.14:checkk5 2006.173.07:37:52.50/chk_autoobs//k5ts1/ autoobs is running! 2006.173.07:37:52.90/chk_autoobs//k5ts2/ autoobs is running! 2006.173.07:37:53.33/chk_autoobs//k5ts3/ autoobs is running! 2006.173.07:37:53.73/chk_autoobs//k5ts4/ autoobs is running! 2006.173.07:37:54.11/chk_obsdata//k5ts1/T1730736??a.dat file size is correct (nominal:200MB, actual:196MB). 2006.173.07:37:54.51/chk_obsdata//k5ts2/T1730736??b.dat file size is correct (nominal:200MB, actual:196MB). 2006.173.07:37:54.92/chk_obsdata//k5ts3/T1730736??c.dat file size is correct (nominal:200MB, actual:196MB). 2006.173.07:37:55.33/chk_obsdata//k5ts4/T1730736??d.dat file size is correct (nominal:200MB, actual:196MB). 2006.173.07:37:56.06/k5log//k5ts1_log_newline 2006.173.07:37:56.78/k5log//k5ts2_log_newline 2006.173.07:37:57.49/k5log//k5ts3_log_newline 2006.173.07:37:58.20/k5log//k5ts4_log_newline 2006.173.07:37:58.22/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.07:37:58.22:setupk4=1 2006.173.07:37:58.22$setupk4/echo=on 2006.173.07:37:58.22$setupk4/pcalon 2006.173.07:37:58.22$pcalon/"no phase cal control is implemented here 2006.173.07:37:58.22$setupk4/"tpicd=stop 2006.173.07:37:58.22$setupk4/"rec=synch_on 2006.173.07:37:58.22$setupk4/"rec_mode=128 2006.173.07:37:58.22$setupk4/!* 2006.173.07:37:58.22$setupk4/recpk4 2006.173.07:37:58.22$recpk4/recpatch= 2006.173.07:37:58.23$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.07:37:58.23$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.07:37:58.23$setupk4/vck44 2006.173.07:37:58.23$vck44/valo=1,524.99 2006.173.07:37:58.23#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.07:37:58.23#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.07:37:58.23#ibcon#ireg 17 cls_cnt 0 2006.173.07:37:58.23#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.07:37:58.23#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.07:37:58.23#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.07:37:58.23#ibcon#enter wrdev, iclass 36, count 0 2006.173.07:37:58.23#ibcon#first serial, iclass 36, count 0 2006.173.07:37:58.23#ibcon#enter sib2, iclass 36, count 0 2006.173.07:37:58.23#ibcon#flushed, iclass 36, count 0 2006.173.07:37:58.23#ibcon#about to write, iclass 36, count 0 2006.173.07:37:58.23#ibcon#wrote, iclass 36, count 0 2006.173.07:37:58.23#ibcon#about to read 3, iclass 36, count 0 2006.173.07:37:58.25#ibcon#read 3, iclass 36, count 0 2006.173.07:37:58.25#ibcon#about to read 4, iclass 36, count 0 2006.173.07:37:58.25#ibcon#read 4, iclass 36, count 0 2006.173.07:37:58.25#ibcon#about to read 5, iclass 36, count 0 2006.173.07:37:58.25#ibcon#read 5, iclass 36, count 0 2006.173.07:37:58.25#ibcon#about to read 6, iclass 36, count 0 2006.173.07:37:58.25#ibcon#read 6, iclass 36, count 0 2006.173.07:37:58.25#ibcon#end of sib2, iclass 36, count 0 2006.173.07:37:58.25#ibcon#*mode == 0, iclass 36, count 0 2006.173.07:37:58.25#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.07:37:58.25#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.07:37:58.25#ibcon#*before write, iclass 36, count 0 2006.173.07:37:58.25#ibcon#enter sib2, iclass 36, count 0 2006.173.07:37:58.25#ibcon#flushed, iclass 36, count 0 2006.173.07:37:58.25#ibcon#about to write, iclass 36, count 0 2006.173.07:37:58.25#ibcon#wrote, iclass 36, count 0 2006.173.07:37:58.25#ibcon#about to read 3, iclass 36, count 0 2006.173.07:37:58.30#ibcon#read 3, iclass 36, count 0 2006.173.07:37:58.30#ibcon#about to read 4, iclass 36, count 0 2006.173.07:37:58.30#ibcon#read 4, iclass 36, count 0 2006.173.07:37:58.30#ibcon#about to read 5, iclass 36, count 0 2006.173.07:37:58.30#ibcon#read 5, iclass 36, count 0 2006.173.07:37:58.30#ibcon#about to read 6, iclass 36, count 0 2006.173.07:37:58.30#ibcon#read 6, iclass 36, count 0 2006.173.07:37:58.30#ibcon#end of sib2, iclass 36, count 0 2006.173.07:37:58.30#ibcon#*after write, iclass 36, count 0 2006.173.07:37:58.30#ibcon#*before return 0, iclass 36, count 0 2006.173.07:37:58.30#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.07:37:58.30#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.07:37:58.30#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.07:37:58.30#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.07:37:58.30$vck44/va=1,7 2006.173.07:37:58.30#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.07:37:58.30#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.07:37:58.30#ibcon#ireg 11 cls_cnt 2 2006.173.07:37:58.30#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.07:37:58.30#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.07:37:58.30#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.07:37:58.30#ibcon#enter wrdev, iclass 38, count 2 2006.173.07:37:58.30#ibcon#first serial, iclass 38, count 2 2006.173.07:37:58.30#ibcon#enter sib2, iclass 38, count 2 2006.173.07:37:58.30#ibcon#flushed, iclass 38, count 2 2006.173.07:37:58.30#ibcon#about to write, iclass 38, count 2 2006.173.07:37:58.30#ibcon#wrote, iclass 38, count 2 2006.173.07:37:58.30#ibcon#about to read 3, iclass 38, count 2 2006.173.07:37:58.32#ibcon#read 3, iclass 38, count 2 2006.173.07:37:58.32#ibcon#about to read 4, iclass 38, count 2 2006.173.07:37:58.32#ibcon#read 4, iclass 38, count 2 2006.173.07:37:58.32#ibcon#about to read 5, iclass 38, count 2 2006.173.07:37:58.32#ibcon#read 5, iclass 38, count 2 2006.173.07:37:58.32#ibcon#about to read 6, iclass 38, count 2 2006.173.07:37:58.32#ibcon#read 6, iclass 38, count 2 2006.173.07:37:58.32#ibcon#end of sib2, iclass 38, count 2 2006.173.07:37:58.32#ibcon#*mode == 0, iclass 38, count 2 2006.173.07:37:58.32#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.07:37:58.32#ibcon#[25=AT01-07\r\n] 2006.173.07:37:58.32#ibcon#*before write, iclass 38, count 2 2006.173.07:37:58.32#ibcon#enter sib2, iclass 38, count 2 2006.173.07:37:58.32#ibcon#flushed, iclass 38, count 2 2006.173.07:37:58.32#ibcon#about to write, iclass 38, count 2 2006.173.07:37:58.32#ibcon#wrote, iclass 38, count 2 2006.173.07:37:58.32#ibcon#about to read 3, iclass 38, count 2 2006.173.07:37:58.35#ibcon#read 3, iclass 38, count 2 2006.173.07:37:58.35#ibcon#about to read 4, iclass 38, count 2 2006.173.07:37:58.35#ibcon#read 4, iclass 38, count 2 2006.173.07:37:58.35#ibcon#about to read 5, iclass 38, count 2 2006.173.07:37:58.35#ibcon#read 5, iclass 38, count 2 2006.173.07:37:58.35#ibcon#about to read 6, iclass 38, count 2 2006.173.07:37:58.35#ibcon#read 6, iclass 38, count 2 2006.173.07:37:58.35#ibcon#end of sib2, iclass 38, count 2 2006.173.07:37:58.35#ibcon#*after write, iclass 38, count 2 2006.173.07:37:58.35#ibcon#*before return 0, iclass 38, count 2 2006.173.07:37:58.35#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.07:37:58.35#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.07:37:58.35#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.07:37:58.35#ibcon#ireg 7 cls_cnt 0 2006.173.07:37:58.35#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.07:37:58.47#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.07:37:58.47#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.07:37:58.47#ibcon#enter wrdev, iclass 38, count 0 2006.173.07:37:58.47#ibcon#first serial, iclass 38, count 0 2006.173.07:37:58.47#ibcon#enter sib2, iclass 38, count 0 2006.173.07:37:58.47#ibcon#flushed, iclass 38, count 0 2006.173.07:37:58.47#ibcon#about to write, iclass 38, count 0 2006.173.07:37:58.47#ibcon#wrote, iclass 38, count 0 2006.173.07:37:58.47#ibcon#about to read 3, iclass 38, count 0 2006.173.07:37:58.49#ibcon#read 3, iclass 38, count 0 2006.173.07:37:58.49#ibcon#about to read 4, iclass 38, count 0 2006.173.07:37:58.49#ibcon#read 4, iclass 38, count 0 2006.173.07:37:58.49#ibcon#about to read 5, iclass 38, count 0 2006.173.07:37:58.49#ibcon#read 5, iclass 38, count 0 2006.173.07:37:58.49#ibcon#about to read 6, iclass 38, count 0 2006.173.07:37:58.49#ibcon#read 6, iclass 38, count 0 2006.173.07:37:58.49#ibcon#end of sib2, iclass 38, count 0 2006.173.07:37:58.49#ibcon#*mode == 0, iclass 38, count 0 2006.173.07:37:58.49#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.07:37:58.49#ibcon#[25=USB\r\n] 2006.173.07:37:58.49#ibcon#*before write, iclass 38, count 0 2006.173.07:37:58.49#ibcon#enter sib2, iclass 38, count 0 2006.173.07:37:58.49#ibcon#flushed, iclass 38, count 0 2006.173.07:37:58.49#ibcon#about to write, iclass 38, count 0 2006.173.07:37:58.49#ibcon#wrote, iclass 38, count 0 2006.173.07:37:58.49#ibcon#about to read 3, iclass 38, count 0 2006.173.07:37:58.52#ibcon#read 3, iclass 38, count 0 2006.173.07:37:58.52#ibcon#about to read 4, iclass 38, count 0 2006.173.07:37:58.52#ibcon#read 4, iclass 38, count 0 2006.173.07:37:58.52#ibcon#about to read 5, iclass 38, count 0 2006.173.07:37:58.52#ibcon#read 5, iclass 38, count 0 2006.173.07:37:58.52#ibcon#about to read 6, iclass 38, count 0 2006.173.07:37:58.52#ibcon#read 6, iclass 38, count 0 2006.173.07:37:58.52#ibcon#end of sib2, iclass 38, count 0 2006.173.07:37:58.52#ibcon#*after write, iclass 38, count 0 2006.173.07:37:58.52#ibcon#*before return 0, iclass 38, count 0 2006.173.07:37:58.52#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.07:37:58.52#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.07:37:58.52#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.07:37:58.52#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.07:37:58.52$vck44/valo=2,534.99 2006.173.07:37:58.52#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.07:37:58.52#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.07:37:58.52#ibcon#ireg 17 cls_cnt 0 2006.173.07:37:58.52#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.07:37:58.52#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.07:37:58.52#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.07:37:58.52#ibcon#enter wrdev, iclass 40, count 0 2006.173.07:37:58.52#ibcon#first serial, iclass 40, count 0 2006.173.07:37:58.52#ibcon#enter sib2, iclass 40, count 0 2006.173.07:37:58.52#ibcon#flushed, iclass 40, count 0 2006.173.07:37:58.52#ibcon#about to write, iclass 40, count 0 2006.173.07:37:58.52#ibcon#wrote, iclass 40, count 0 2006.173.07:37:58.52#ibcon#about to read 3, iclass 40, count 0 2006.173.07:37:58.54#ibcon#read 3, iclass 40, count 0 2006.173.07:37:58.54#ibcon#about to read 4, iclass 40, count 0 2006.173.07:37:58.54#ibcon#read 4, iclass 40, count 0 2006.173.07:37:58.54#ibcon#about to read 5, iclass 40, count 0 2006.173.07:37:58.54#ibcon#read 5, iclass 40, count 0 2006.173.07:37:58.54#ibcon#about to read 6, iclass 40, count 0 2006.173.07:37:58.54#ibcon#read 6, iclass 40, count 0 2006.173.07:37:58.54#ibcon#end of sib2, iclass 40, count 0 2006.173.07:37:58.54#ibcon#*mode == 0, iclass 40, count 0 2006.173.07:37:58.54#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.07:37:58.54#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.07:37:58.54#ibcon#*before write, iclass 40, count 0 2006.173.07:37:58.54#ibcon#enter sib2, iclass 40, count 0 2006.173.07:37:58.54#ibcon#flushed, iclass 40, count 0 2006.173.07:37:58.54#ibcon#about to write, iclass 40, count 0 2006.173.07:37:58.54#ibcon#wrote, iclass 40, count 0 2006.173.07:37:58.54#ibcon#about to read 3, iclass 40, count 0 2006.173.07:37:58.58#ibcon#read 3, iclass 40, count 0 2006.173.07:37:58.58#ibcon#about to read 4, iclass 40, count 0 2006.173.07:37:58.58#ibcon#read 4, iclass 40, count 0 2006.173.07:37:58.58#ibcon#about to read 5, iclass 40, count 0 2006.173.07:37:58.58#ibcon#read 5, iclass 40, count 0 2006.173.07:37:58.58#ibcon#about to read 6, iclass 40, count 0 2006.173.07:37:58.58#ibcon#read 6, iclass 40, count 0 2006.173.07:37:58.58#ibcon#end of sib2, iclass 40, count 0 2006.173.07:37:58.58#ibcon#*after write, iclass 40, count 0 2006.173.07:37:58.58#ibcon#*before return 0, iclass 40, count 0 2006.173.07:37:58.58#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.07:37:58.58#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.07:37:58.58#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.07:37:58.58#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.07:37:58.58$vck44/va=2,6 2006.173.07:37:58.58#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.07:37:58.58#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.07:37:58.58#ibcon#ireg 11 cls_cnt 2 2006.173.07:37:58.58#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.07:37:58.64#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.07:37:58.64#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.07:37:58.64#ibcon#enter wrdev, iclass 4, count 2 2006.173.07:37:58.64#ibcon#first serial, iclass 4, count 2 2006.173.07:37:58.64#ibcon#enter sib2, iclass 4, count 2 2006.173.07:37:58.64#ibcon#flushed, iclass 4, count 2 2006.173.07:37:58.64#ibcon#about to write, iclass 4, count 2 2006.173.07:37:58.64#ibcon#wrote, iclass 4, count 2 2006.173.07:37:58.64#ibcon#about to read 3, iclass 4, count 2 2006.173.07:37:58.66#ibcon#read 3, iclass 4, count 2 2006.173.07:37:58.66#ibcon#about to read 4, iclass 4, count 2 2006.173.07:37:58.66#ibcon#read 4, iclass 4, count 2 2006.173.07:37:58.66#ibcon#about to read 5, iclass 4, count 2 2006.173.07:37:58.66#ibcon#read 5, iclass 4, count 2 2006.173.07:37:58.66#ibcon#about to read 6, iclass 4, count 2 2006.173.07:37:58.66#ibcon#read 6, iclass 4, count 2 2006.173.07:37:58.66#ibcon#end of sib2, iclass 4, count 2 2006.173.07:37:58.66#ibcon#*mode == 0, iclass 4, count 2 2006.173.07:37:58.66#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.07:37:58.66#ibcon#[25=AT02-06\r\n] 2006.173.07:37:58.66#ibcon#*before write, iclass 4, count 2 2006.173.07:37:58.66#ibcon#enter sib2, iclass 4, count 2 2006.173.07:37:58.66#ibcon#flushed, iclass 4, count 2 2006.173.07:37:58.66#ibcon#about to write, iclass 4, count 2 2006.173.07:37:58.66#ibcon#wrote, iclass 4, count 2 2006.173.07:37:58.66#ibcon#about to read 3, iclass 4, count 2 2006.173.07:37:58.69#ibcon#read 3, iclass 4, count 2 2006.173.07:37:58.69#ibcon#about to read 4, iclass 4, count 2 2006.173.07:37:58.69#ibcon#read 4, iclass 4, count 2 2006.173.07:37:58.69#ibcon#about to read 5, iclass 4, count 2 2006.173.07:37:58.69#ibcon#read 5, iclass 4, count 2 2006.173.07:37:58.69#ibcon#about to read 6, iclass 4, count 2 2006.173.07:37:58.69#ibcon#read 6, iclass 4, count 2 2006.173.07:37:58.69#ibcon#end of sib2, iclass 4, count 2 2006.173.07:37:58.69#ibcon#*after write, iclass 4, count 2 2006.173.07:37:58.69#ibcon#*before return 0, iclass 4, count 2 2006.173.07:37:58.69#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.07:37:58.69#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.07:37:58.69#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.07:37:58.69#ibcon#ireg 7 cls_cnt 0 2006.173.07:37:58.69#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.07:37:58.81#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.07:37:58.81#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.07:37:58.81#ibcon#enter wrdev, iclass 4, count 0 2006.173.07:37:58.81#ibcon#first serial, iclass 4, count 0 2006.173.07:37:58.81#ibcon#enter sib2, iclass 4, count 0 2006.173.07:37:58.81#ibcon#flushed, iclass 4, count 0 2006.173.07:37:58.81#ibcon#about to write, iclass 4, count 0 2006.173.07:37:58.81#ibcon#wrote, iclass 4, count 0 2006.173.07:37:58.81#ibcon#about to read 3, iclass 4, count 0 2006.173.07:37:58.83#ibcon#read 3, iclass 4, count 0 2006.173.07:37:58.83#ibcon#about to read 4, iclass 4, count 0 2006.173.07:37:58.83#ibcon#read 4, iclass 4, count 0 2006.173.07:37:58.83#ibcon#about to read 5, iclass 4, count 0 2006.173.07:37:58.83#ibcon#read 5, iclass 4, count 0 2006.173.07:37:58.83#ibcon#about to read 6, iclass 4, count 0 2006.173.07:37:58.83#ibcon#read 6, iclass 4, count 0 2006.173.07:37:58.83#ibcon#end of sib2, iclass 4, count 0 2006.173.07:37:58.83#ibcon#*mode == 0, iclass 4, count 0 2006.173.07:37:58.83#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.07:37:58.83#ibcon#[25=USB\r\n] 2006.173.07:37:58.83#ibcon#*before write, iclass 4, count 0 2006.173.07:37:58.83#ibcon#enter sib2, iclass 4, count 0 2006.173.07:37:58.83#ibcon#flushed, iclass 4, count 0 2006.173.07:37:58.83#ibcon#about to write, iclass 4, count 0 2006.173.07:37:58.83#ibcon#wrote, iclass 4, count 0 2006.173.07:37:58.83#ibcon#about to read 3, iclass 4, count 0 2006.173.07:37:58.86#ibcon#read 3, iclass 4, count 0 2006.173.07:37:58.86#ibcon#about to read 4, iclass 4, count 0 2006.173.07:37:58.86#ibcon#read 4, iclass 4, count 0 2006.173.07:37:58.86#ibcon#about to read 5, iclass 4, count 0 2006.173.07:37:58.86#ibcon#read 5, iclass 4, count 0 2006.173.07:37:58.86#ibcon#about to read 6, iclass 4, count 0 2006.173.07:37:58.86#ibcon#read 6, iclass 4, count 0 2006.173.07:37:58.86#ibcon#end of sib2, iclass 4, count 0 2006.173.07:37:58.86#ibcon#*after write, iclass 4, count 0 2006.173.07:37:58.86#ibcon#*before return 0, iclass 4, count 0 2006.173.07:37:58.86#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.07:37:58.86#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.07:37:58.86#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.07:37:58.86#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.07:37:58.86$vck44/valo=3,564.99 2006.173.07:37:58.86#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.07:37:58.86#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.07:37:58.86#ibcon#ireg 17 cls_cnt 0 2006.173.07:37:58.86#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.07:37:58.86#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.07:37:58.86#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.07:37:58.86#ibcon#enter wrdev, iclass 6, count 0 2006.173.07:37:58.86#ibcon#first serial, iclass 6, count 0 2006.173.07:37:58.86#ibcon#enter sib2, iclass 6, count 0 2006.173.07:37:58.86#ibcon#flushed, iclass 6, count 0 2006.173.07:37:58.86#ibcon#about to write, iclass 6, count 0 2006.173.07:37:58.86#ibcon#wrote, iclass 6, count 0 2006.173.07:37:58.86#ibcon#about to read 3, iclass 6, count 0 2006.173.07:37:58.88#ibcon#read 3, iclass 6, count 0 2006.173.07:37:58.88#ibcon#about to read 4, iclass 6, count 0 2006.173.07:37:58.88#ibcon#read 4, iclass 6, count 0 2006.173.07:37:58.88#ibcon#about to read 5, iclass 6, count 0 2006.173.07:37:58.88#ibcon#read 5, iclass 6, count 0 2006.173.07:37:58.88#ibcon#about to read 6, iclass 6, count 0 2006.173.07:37:58.88#ibcon#read 6, iclass 6, count 0 2006.173.07:37:58.88#ibcon#end of sib2, iclass 6, count 0 2006.173.07:37:58.88#ibcon#*mode == 0, iclass 6, count 0 2006.173.07:37:58.88#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.07:37:58.88#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.07:37:58.88#ibcon#*before write, iclass 6, count 0 2006.173.07:37:58.88#ibcon#enter sib2, iclass 6, count 0 2006.173.07:37:58.88#ibcon#flushed, iclass 6, count 0 2006.173.07:37:58.88#ibcon#about to write, iclass 6, count 0 2006.173.07:37:58.88#ibcon#wrote, iclass 6, count 0 2006.173.07:37:58.88#ibcon#about to read 3, iclass 6, count 0 2006.173.07:37:58.92#ibcon#read 3, iclass 6, count 0 2006.173.07:37:58.92#ibcon#about to read 4, iclass 6, count 0 2006.173.07:37:58.92#ibcon#read 4, iclass 6, count 0 2006.173.07:37:58.92#ibcon#about to read 5, iclass 6, count 0 2006.173.07:37:58.92#ibcon#read 5, iclass 6, count 0 2006.173.07:37:58.92#ibcon#about to read 6, iclass 6, count 0 2006.173.07:37:58.92#ibcon#read 6, iclass 6, count 0 2006.173.07:37:58.92#ibcon#end of sib2, iclass 6, count 0 2006.173.07:37:58.92#ibcon#*after write, iclass 6, count 0 2006.173.07:37:58.92#ibcon#*before return 0, iclass 6, count 0 2006.173.07:37:58.92#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.07:37:58.92#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.07:37:58.92#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.07:37:58.92#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.07:37:58.92$vck44/va=3,5 2006.173.07:37:58.92#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.07:37:58.92#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.07:37:58.92#ibcon#ireg 11 cls_cnt 2 2006.173.07:37:58.92#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.07:37:58.98#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.07:37:58.98#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.07:37:58.98#ibcon#enter wrdev, iclass 10, count 2 2006.173.07:37:58.98#ibcon#first serial, iclass 10, count 2 2006.173.07:37:58.98#ibcon#enter sib2, iclass 10, count 2 2006.173.07:37:58.98#ibcon#flushed, iclass 10, count 2 2006.173.07:37:58.98#ibcon#about to write, iclass 10, count 2 2006.173.07:37:58.98#ibcon#wrote, iclass 10, count 2 2006.173.07:37:58.98#ibcon#about to read 3, iclass 10, count 2 2006.173.07:37:59.00#ibcon#read 3, iclass 10, count 2 2006.173.07:37:59.00#ibcon#about to read 4, iclass 10, count 2 2006.173.07:37:59.00#ibcon#read 4, iclass 10, count 2 2006.173.07:37:59.00#ibcon#about to read 5, iclass 10, count 2 2006.173.07:37:59.00#ibcon#read 5, iclass 10, count 2 2006.173.07:37:59.00#ibcon#about to read 6, iclass 10, count 2 2006.173.07:37:59.00#ibcon#read 6, iclass 10, count 2 2006.173.07:37:59.00#ibcon#end of sib2, iclass 10, count 2 2006.173.07:37:59.00#ibcon#*mode == 0, iclass 10, count 2 2006.173.07:37:59.00#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.07:37:59.00#ibcon#[25=AT03-05\r\n] 2006.173.07:37:59.00#ibcon#*before write, iclass 10, count 2 2006.173.07:37:59.00#ibcon#enter sib2, iclass 10, count 2 2006.173.07:37:59.00#ibcon#flushed, iclass 10, count 2 2006.173.07:37:59.00#ibcon#about to write, iclass 10, count 2 2006.173.07:37:59.00#ibcon#wrote, iclass 10, count 2 2006.173.07:37:59.00#ibcon#about to read 3, iclass 10, count 2 2006.173.07:37:59.03#ibcon#read 3, iclass 10, count 2 2006.173.07:37:59.03#ibcon#about to read 4, iclass 10, count 2 2006.173.07:37:59.03#ibcon#read 4, iclass 10, count 2 2006.173.07:37:59.03#ibcon#about to read 5, iclass 10, count 2 2006.173.07:37:59.03#ibcon#read 5, iclass 10, count 2 2006.173.07:37:59.03#ibcon#about to read 6, iclass 10, count 2 2006.173.07:37:59.03#ibcon#read 6, iclass 10, count 2 2006.173.07:37:59.03#ibcon#end of sib2, iclass 10, count 2 2006.173.07:37:59.03#ibcon#*after write, iclass 10, count 2 2006.173.07:37:59.03#ibcon#*before return 0, iclass 10, count 2 2006.173.07:37:59.03#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.07:37:59.03#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.07:37:59.03#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.07:37:59.03#ibcon#ireg 7 cls_cnt 0 2006.173.07:37:59.03#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.07:37:59.15#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.07:37:59.15#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.07:37:59.15#ibcon#enter wrdev, iclass 10, count 0 2006.173.07:37:59.15#ibcon#first serial, iclass 10, count 0 2006.173.07:37:59.15#ibcon#enter sib2, iclass 10, count 0 2006.173.07:37:59.15#ibcon#flushed, iclass 10, count 0 2006.173.07:37:59.15#ibcon#about to write, iclass 10, count 0 2006.173.07:37:59.15#ibcon#wrote, iclass 10, count 0 2006.173.07:37:59.15#ibcon#about to read 3, iclass 10, count 0 2006.173.07:37:59.17#ibcon#read 3, iclass 10, count 0 2006.173.07:37:59.17#ibcon#about to read 4, iclass 10, count 0 2006.173.07:37:59.17#ibcon#read 4, iclass 10, count 0 2006.173.07:37:59.17#ibcon#about to read 5, iclass 10, count 0 2006.173.07:37:59.17#ibcon#read 5, iclass 10, count 0 2006.173.07:37:59.17#ibcon#about to read 6, iclass 10, count 0 2006.173.07:37:59.17#ibcon#read 6, iclass 10, count 0 2006.173.07:37:59.17#ibcon#end of sib2, iclass 10, count 0 2006.173.07:37:59.17#ibcon#*mode == 0, iclass 10, count 0 2006.173.07:37:59.17#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.07:37:59.17#ibcon#[25=USB\r\n] 2006.173.07:37:59.17#ibcon#*before write, iclass 10, count 0 2006.173.07:37:59.17#ibcon#enter sib2, iclass 10, count 0 2006.173.07:37:59.17#ibcon#flushed, iclass 10, count 0 2006.173.07:37:59.17#ibcon#about to write, iclass 10, count 0 2006.173.07:37:59.17#ibcon#wrote, iclass 10, count 0 2006.173.07:37:59.17#ibcon#about to read 3, iclass 10, count 0 2006.173.07:37:59.20#ibcon#read 3, iclass 10, count 0 2006.173.07:37:59.20#ibcon#about to read 4, iclass 10, count 0 2006.173.07:37:59.20#ibcon#read 4, iclass 10, count 0 2006.173.07:37:59.20#ibcon#about to read 5, iclass 10, count 0 2006.173.07:37:59.20#ibcon#read 5, iclass 10, count 0 2006.173.07:37:59.20#ibcon#about to read 6, iclass 10, count 0 2006.173.07:37:59.20#ibcon#read 6, iclass 10, count 0 2006.173.07:37:59.20#ibcon#end of sib2, iclass 10, count 0 2006.173.07:37:59.20#ibcon#*after write, iclass 10, count 0 2006.173.07:37:59.20#ibcon#*before return 0, iclass 10, count 0 2006.173.07:37:59.20#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.07:37:59.20#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.07:37:59.20#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.07:37:59.20#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.07:37:59.20$vck44/valo=4,624.99 2006.173.07:37:59.20#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.07:37:59.20#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.07:37:59.20#ibcon#ireg 17 cls_cnt 0 2006.173.07:37:59.20#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.07:37:59.20#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.07:37:59.20#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.07:37:59.20#ibcon#enter wrdev, iclass 12, count 0 2006.173.07:37:59.20#ibcon#first serial, iclass 12, count 0 2006.173.07:37:59.20#ibcon#enter sib2, iclass 12, count 0 2006.173.07:37:59.20#ibcon#flushed, iclass 12, count 0 2006.173.07:37:59.20#ibcon#about to write, iclass 12, count 0 2006.173.07:37:59.20#ibcon#wrote, iclass 12, count 0 2006.173.07:37:59.20#ibcon#about to read 3, iclass 12, count 0 2006.173.07:37:59.22#ibcon#read 3, iclass 12, count 0 2006.173.07:37:59.22#ibcon#about to read 4, iclass 12, count 0 2006.173.07:37:59.22#ibcon#read 4, iclass 12, count 0 2006.173.07:37:59.22#ibcon#about to read 5, iclass 12, count 0 2006.173.07:37:59.22#ibcon#read 5, iclass 12, count 0 2006.173.07:37:59.22#ibcon#about to read 6, iclass 12, count 0 2006.173.07:37:59.22#ibcon#read 6, iclass 12, count 0 2006.173.07:37:59.22#ibcon#end of sib2, iclass 12, count 0 2006.173.07:37:59.22#ibcon#*mode == 0, iclass 12, count 0 2006.173.07:37:59.22#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.07:37:59.22#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.07:37:59.22#ibcon#*before write, iclass 12, count 0 2006.173.07:37:59.22#ibcon#enter sib2, iclass 12, count 0 2006.173.07:37:59.22#ibcon#flushed, iclass 12, count 0 2006.173.07:37:59.22#ibcon#about to write, iclass 12, count 0 2006.173.07:37:59.22#ibcon#wrote, iclass 12, count 0 2006.173.07:37:59.22#ibcon#about to read 3, iclass 12, count 0 2006.173.07:37:59.26#ibcon#read 3, iclass 12, count 0 2006.173.07:37:59.26#ibcon#about to read 4, iclass 12, count 0 2006.173.07:37:59.26#ibcon#read 4, iclass 12, count 0 2006.173.07:37:59.26#ibcon#about to read 5, iclass 12, count 0 2006.173.07:37:59.26#ibcon#read 5, iclass 12, count 0 2006.173.07:37:59.26#ibcon#about to read 6, iclass 12, count 0 2006.173.07:37:59.26#ibcon#read 6, iclass 12, count 0 2006.173.07:37:59.26#ibcon#end of sib2, iclass 12, count 0 2006.173.07:37:59.26#ibcon#*after write, iclass 12, count 0 2006.173.07:37:59.26#ibcon#*before return 0, iclass 12, count 0 2006.173.07:37:59.26#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.07:37:59.26#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.07:37:59.26#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.07:37:59.26#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.07:37:59.26$vck44/va=4,6 2006.173.07:37:59.26#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.07:37:59.26#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.07:37:59.26#ibcon#ireg 11 cls_cnt 2 2006.173.07:37:59.26#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.07:37:59.32#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.07:37:59.32#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.07:37:59.32#ibcon#enter wrdev, iclass 14, count 2 2006.173.07:37:59.32#ibcon#first serial, iclass 14, count 2 2006.173.07:37:59.32#ibcon#enter sib2, iclass 14, count 2 2006.173.07:37:59.32#ibcon#flushed, iclass 14, count 2 2006.173.07:37:59.32#ibcon#about to write, iclass 14, count 2 2006.173.07:37:59.32#ibcon#wrote, iclass 14, count 2 2006.173.07:37:59.32#ibcon#about to read 3, iclass 14, count 2 2006.173.07:37:59.34#ibcon#read 3, iclass 14, count 2 2006.173.07:37:59.34#ibcon#about to read 4, iclass 14, count 2 2006.173.07:37:59.34#ibcon#read 4, iclass 14, count 2 2006.173.07:37:59.34#ibcon#about to read 5, iclass 14, count 2 2006.173.07:37:59.34#ibcon#read 5, iclass 14, count 2 2006.173.07:37:59.34#ibcon#about to read 6, iclass 14, count 2 2006.173.07:37:59.34#ibcon#read 6, iclass 14, count 2 2006.173.07:37:59.34#ibcon#end of sib2, iclass 14, count 2 2006.173.07:37:59.34#ibcon#*mode == 0, iclass 14, count 2 2006.173.07:37:59.34#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.07:37:59.34#ibcon#[25=AT04-06\r\n] 2006.173.07:37:59.34#ibcon#*before write, iclass 14, count 2 2006.173.07:37:59.34#ibcon#enter sib2, iclass 14, count 2 2006.173.07:37:59.34#ibcon#flushed, iclass 14, count 2 2006.173.07:37:59.34#ibcon#about to write, iclass 14, count 2 2006.173.07:37:59.34#ibcon#wrote, iclass 14, count 2 2006.173.07:37:59.34#ibcon#about to read 3, iclass 14, count 2 2006.173.07:37:59.37#ibcon#read 3, iclass 14, count 2 2006.173.07:37:59.37#ibcon#about to read 4, iclass 14, count 2 2006.173.07:37:59.37#ibcon#read 4, iclass 14, count 2 2006.173.07:37:59.37#ibcon#about to read 5, iclass 14, count 2 2006.173.07:37:59.37#ibcon#read 5, iclass 14, count 2 2006.173.07:37:59.37#ibcon#about to read 6, iclass 14, count 2 2006.173.07:37:59.37#ibcon#read 6, iclass 14, count 2 2006.173.07:37:59.37#ibcon#end of sib2, iclass 14, count 2 2006.173.07:37:59.37#ibcon#*after write, iclass 14, count 2 2006.173.07:37:59.37#ibcon#*before return 0, iclass 14, count 2 2006.173.07:37:59.37#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.07:37:59.37#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.07:37:59.37#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.07:37:59.37#ibcon#ireg 7 cls_cnt 0 2006.173.07:37:59.37#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.07:37:59.49#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.07:37:59.49#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.07:37:59.49#ibcon#enter wrdev, iclass 14, count 0 2006.173.07:37:59.49#ibcon#first serial, iclass 14, count 0 2006.173.07:37:59.49#ibcon#enter sib2, iclass 14, count 0 2006.173.07:37:59.49#ibcon#flushed, iclass 14, count 0 2006.173.07:37:59.49#ibcon#about to write, iclass 14, count 0 2006.173.07:37:59.49#ibcon#wrote, iclass 14, count 0 2006.173.07:37:59.49#ibcon#about to read 3, iclass 14, count 0 2006.173.07:37:59.51#ibcon#read 3, iclass 14, count 0 2006.173.07:37:59.51#ibcon#about to read 4, iclass 14, count 0 2006.173.07:37:59.51#ibcon#read 4, iclass 14, count 0 2006.173.07:37:59.51#ibcon#about to read 5, iclass 14, count 0 2006.173.07:37:59.51#ibcon#read 5, iclass 14, count 0 2006.173.07:37:59.51#ibcon#about to read 6, iclass 14, count 0 2006.173.07:37:59.51#ibcon#read 6, iclass 14, count 0 2006.173.07:37:59.51#ibcon#end of sib2, iclass 14, count 0 2006.173.07:37:59.51#ibcon#*mode == 0, iclass 14, count 0 2006.173.07:37:59.51#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.07:37:59.51#ibcon#[25=USB\r\n] 2006.173.07:37:59.51#ibcon#*before write, iclass 14, count 0 2006.173.07:37:59.51#ibcon#enter sib2, iclass 14, count 0 2006.173.07:37:59.51#ibcon#flushed, iclass 14, count 0 2006.173.07:37:59.51#ibcon#about to write, iclass 14, count 0 2006.173.07:37:59.51#ibcon#wrote, iclass 14, count 0 2006.173.07:37:59.51#ibcon#about to read 3, iclass 14, count 0 2006.173.07:37:59.54#ibcon#read 3, iclass 14, count 0 2006.173.07:37:59.54#ibcon#about to read 4, iclass 14, count 0 2006.173.07:37:59.54#ibcon#read 4, iclass 14, count 0 2006.173.07:37:59.54#ibcon#about to read 5, iclass 14, count 0 2006.173.07:37:59.54#ibcon#read 5, iclass 14, count 0 2006.173.07:37:59.54#ibcon#about to read 6, iclass 14, count 0 2006.173.07:37:59.54#ibcon#read 6, iclass 14, count 0 2006.173.07:37:59.54#ibcon#end of sib2, iclass 14, count 0 2006.173.07:37:59.54#ibcon#*after write, iclass 14, count 0 2006.173.07:37:59.54#ibcon#*before return 0, iclass 14, count 0 2006.173.07:37:59.54#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.07:37:59.54#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.07:37:59.54#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.07:37:59.54#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.07:37:59.54$vck44/valo=5,734.99 2006.173.07:37:59.54#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.07:37:59.54#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.07:37:59.54#ibcon#ireg 17 cls_cnt 0 2006.173.07:37:59.54#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.07:37:59.54#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.07:37:59.54#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.07:37:59.54#ibcon#enter wrdev, iclass 16, count 0 2006.173.07:37:59.54#ibcon#first serial, iclass 16, count 0 2006.173.07:37:59.54#ibcon#enter sib2, iclass 16, count 0 2006.173.07:37:59.54#ibcon#flushed, iclass 16, count 0 2006.173.07:37:59.54#ibcon#about to write, iclass 16, count 0 2006.173.07:37:59.54#ibcon#wrote, iclass 16, count 0 2006.173.07:37:59.54#ibcon#about to read 3, iclass 16, count 0 2006.173.07:37:59.56#ibcon#read 3, iclass 16, count 0 2006.173.07:37:59.56#ibcon#about to read 4, iclass 16, count 0 2006.173.07:37:59.56#ibcon#read 4, iclass 16, count 0 2006.173.07:37:59.56#ibcon#about to read 5, iclass 16, count 0 2006.173.07:37:59.56#ibcon#read 5, iclass 16, count 0 2006.173.07:37:59.56#ibcon#about to read 6, iclass 16, count 0 2006.173.07:37:59.56#ibcon#read 6, iclass 16, count 0 2006.173.07:37:59.56#ibcon#end of sib2, iclass 16, count 0 2006.173.07:37:59.56#ibcon#*mode == 0, iclass 16, count 0 2006.173.07:37:59.56#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.07:37:59.56#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.07:37:59.56#ibcon#*before write, iclass 16, count 0 2006.173.07:37:59.56#ibcon#enter sib2, iclass 16, count 0 2006.173.07:37:59.56#ibcon#flushed, iclass 16, count 0 2006.173.07:37:59.56#ibcon#about to write, iclass 16, count 0 2006.173.07:37:59.56#ibcon#wrote, iclass 16, count 0 2006.173.07:37:59.56#ibcon#about to read 3, iclass 16, count 0 2006.173.07:37:59.60#ibcon#read 3, iclass 16, count 0 2006.173.07:37:59.60#ibcon#about to read 4, iclass 16, count 0 2006.173.07:37:59.60#ibcon#read 4, iclass 16, count 0 2006.173.07:37:59.60#ibcon#about to read 5, iclass 16, count 0 2006.173.07:37:59.60#ibcon#read 5, iclass 16, count 0 2006.173.07:37:59.60#ibcon#about to read 6, iclass 16, count 0 2006.173.07:37:59.60#ibcon#read 6, iclass 16, count 0 2006.173.07:37:59.60#ibcon#end of sib2, iclass 16, count 0 2006.173.07:37:59.60#ibcon#*after write, iclass 16, count 0 2006.173.07:37:59.60#ibcon#*before return 0, iclass 16, count 0 2006.173.07:37:59.60#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.07:37:59.60#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.07:37:59.60#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.07:37:59.60#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.07:37:59.60$vck44/va=5,4 2006.173.07:37:59.60#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.07:37:59.60#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.07:37:59.60#ibcon#ireg 11 cls_cnt 2 2006.173.07:37:59.60#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.07:37:59.66#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.07:37:59.66#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.07:37:59.66#ibcon#enter wrdev, iclass 18, count 2 2006.173.07:37:59.66#ibcon#first serial, iclass 18, count 2 2006.173.07:37:59.66#ibcon#enter sib2, iclass 18, count 2 2006.173.07:37:59.66#ibcon#flushed, iclass 18, count 2 2006.173.07:37:59.66#ibcon#about to write, iclass 18, count 2 2006.173.07:37:59.66#ibcon#wrote, iclass 18, count 2 2006.173.07:37:59.66#ibcon#about to read 3, iclass 18, count 2 2006.173.07:37:59.68#ibcon#read 3, iclass 18, count 2 2006.173.07:37:59.68#ibcon#about to read 4, iclass 18, count 2 2006.173.07:37:59.68#ibcon#read 4, iclass 18, count 2 2006.173.07:37:59.68#ibcon#about to read 5, iclass 18, count 2 2006.173.07:37:59.68#ibcon#read 5, iclass 18, count 2 2006.173.07:37:59.68#ibcon#about to read 6, iclass 18, count 2 2006.173.07:37:59.68#ibcon#read 6, iclass 18, count 2 2006.173.07:37:59.68#ibcon#end of sib2, iclass 18, count 2 2006.173.07:37:59.68#ibcon#*mode == 0, iclass 18, count 2 2006.173.07:37:59.68#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.07:37:59.68#ibcon#[25=AT05-04\r\n] 2006.173.07:37:59.68#ibcon#*before write, iclass 18, count 2 2006.173.07:37:59.68#ibcon#enter sib2, iclass 18, count 2 2006.173.07:37:59.68#ibcon#flushed, iclass 18, count 2 2006.173.07:37:59.68#ibcon#about to write, iclass 18, count 2 2006.173.07:37:59.68#ibcon#wrote, iclass 18, count 2 2006.173.07:37:59.68#ibcon#about to read 3, iclass 18, count 2 2006.173.07:37:59.71#ibcon#read 3, iclass 18, count 2 2006.173.07:37:59.71#ibcon#about to read 4, iclass 18, count 2 2006.173.07:37:59.71#ibcon#read 4, iclass 18, count 2 2006.173.07:37:59.71#ibcon#about to read 5, iclass 18, count 2 2006.173.07:37:59.71#ibcon#read 5, iclass 18, count 2 2006.173.07:37:59.71#ibcon#about to read 6, iclass 18, count 2 2006.173.07:37:59.71#ibcon#read 6, iclass 18, count 2 2006.173.07:37:59.71#ibcon#end of sib2, iclass 18, count 2 2006.173.07:37:59.71#ibcon#*after write, iclass 18, count 2 2006.173.07:37:59.71#ibcon#*before return 0, iclass 18, count 2 2006.173.07:37:59.71#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.07:37:59.71#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.07:37:59.71#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.07:37:59.71#ibcon#ireg 7 cls_cnt 0 2006.173.07:37:59.71#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.07:37:59.83#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.07:37:59.83#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.07:37:59.83#ibcon#enter wrdev, iclass 18, count 0 2006.173.07:37:59.83#ibcon#first serial, iclass 18, count 0 2006.173.07:37:59.83#ibcon#enter sib2, iclass 18, count 0 2006.173.07:37:59.83#ibcon#flushed, iclass 18, count 0 2006.173.07:37:59.83#ibcon#about to write, iclass 18, count 0 2006.173.07:37:59.83#ibcon#wrote, iclass 18, count 0 2006.173.07:37:59.83#ibcon#about to read 3, iclass 18, count 0 2006.173.07:37:59.85#ibcon#read 3, iclass 18, count 0 2006.173.07:37:59.85#ibcon#about to read 4, iclass 18, count 0 2006.173.07:37:59.85#ibcon#read 4, iclass 18, count 0 2006.173.07:37:59.85#ibcon#about to read 5, iclass 18, count 0 2006.173.07:37:59.85#ibcon#read 5, iclass 18, count 0 2006.173.07:37:59.85#ibcon#about to read 6, iclass 18, count 0 2006.173.07:37:59.85#ibcon#read 6, iclass 18, count 0 2006.173.07:37:59.85#ibcon#end of sib2, iclass 18, count 0 2006.173.07:37:59.85#ibcon#*mode == 0, iclass 18, count 0 2006.173.07:37:59.85#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.07:37:59.85#ibcon#[25=USB\r\n] 2006.173.07:37:59.85#ibcon#*before write, iclass 18, count 0 2006.173.07:37:59.85#ibcon#enter sib2, iclass 18, count 0 2006.173.07:37:59.85#ibcon#flushed, iclass 18, count 0 2006.173.07:37:59.85#ibcon#about to write, iclass 18, count 0 2006.173.07:37:59.85#ibcon#wrote, iclass 18, count 0 2006.173.07:37:59.85#ibcon#about to read 3, iclass 18, count 0 2006.173.07:37:59.88#ibcon#read 3, iclass 18, count 0 2006.173.07:37:59.88#ibcon#about to read 4, iclass 18, count 0 2006.173.07:37:59.88#ibcon#read 4, iclass 18, count 0 2006.173.07:37:59.88#ibcon#about to read 5, iclass 18, count 0 2006.173.07:37:59.88#ibcon#read 5, iclass 18, count 0 2006.173.07:37:59.88#ibcon#about to read 6, iclass 18, count 0 2006.173.07:37:59.88#ibcon#read 6, iclass 18, count 0 2006.173.07:37:59.88#ibcon#end of sib2, iclass 18, count 0 2006.173.07:37:59.88#ibcon#*after write, iclass 18, count 0 2006.173.07:37:59.88#ibcon#*before return 0, iclass 18, count 0 2006.173.07:37:59.88#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.07:37:59.88#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.07:37:59.88#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.07:37:59.88#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.07:37:59.88$vck44/valo=6,814.99 2006.173.07:37:59.88#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.07:37:59.88#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.07:37:59.88#ibcon#ireg 17 cls_cnt 0 2006.173.07:37:59.88#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.07:37:59.88#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.07:37:59.88#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.07:37:59.88#ibcon#enter wrdev, iclass 20, count 0 2006.173.07:37:59.88#ibcon#first serial, iclass 20, count 0 2006.173.07:37:59.88#ibcon#enter sib2, iclass 20, count 0 2006.173.07:37:59.88#ibcon#flushed, iclass 20, count 0 2006.173.07:37:59.88#ibcon#about to write, iclass 20, count 0 2006.173.07:37:59.88#ibcon#wrote, iclass 20, count 0 2006.173.07:37:59.88#ibcon#about to read 3, iclass 20, count 0 2006.173.07:37:59.90#ibcon#read 3, iclass 20, count 0 2006.173.07:37:59.90#ibcon#about to read 4, iclass 20, count 0 2006.173.07:37:59.90#ibcon#read 4, iclass 20, count 0 2006.173.07:37:59.90#ibcon#about to read 5, iclass 20, count 0 2006.173.07:37:59.90#ibcon#read 5, iclass 20, count 0 2006.173.07:37:59.90#ibcon#about to read 6, iclass 20, count 0 2006.173.07:37:59.90#ibcon#read 6, iclass 20, count 0 2006.173.07:37:59.90#ibcon#end of sib2, iclass 20, count 0 2006.173.07:37:59.90#ibcon#*mode == 0, iclass 20, count 0 2006.173.07:37:59.90#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.07:37:59.90#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.07:37:59.90#ibcon#*before write, iclass 20, count 0 2006.173.07:37:59.90#ibcon#enter sib2, iclass 20, count 0 2006.173.07:37:59.90#ibcon#flushed, iclass 20, count 0 2006.173.07:37:59.90#ibcon#about to write, iclass 20, count 0 2006.173.07:37:59.90#ibcon#wrote, iclass 20, count 0 2006.173.07:37:59.90#ibcon#about to read 3, iclass 20, count 0 2006.173.07:37:59.94#ibcon#read 3, iclass 20, count 0 2006.173.07:37:59.94#ibcon#about to read 4, iclass 20, count 0 2006.173.07:37:59.94#ibcon#read 4, iclass 20, count 0 2006.173.07:37:59.94#ibcon#about to read 5, iclass 20, count 0 2006.173.07:37:59.94#ibcon#read 5, iclass 20, count 0 2006.173.07:37:59.94#ibcon#about to read 6, iclass 20, count 0 2006.173.07:37:59.94#ibcon#read 6, iclass 20, count 0 2006.173.07:37:59.94#ibcon#end of sib2, iclass 20, count 0 2006.173.07:37:59.94#ibcon#*after write, iclass 20, count 0 2006.173.07:37:59.94#ibcon#*before return 0, iclass 20, count 0 2006.173.07:37:59.94#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.07:37:59.94#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.07:37:59.94#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.07:37:59.94#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.07:37:59.94$vck44/va=6,3 2006.173.07:37:59.94#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.07:37:59.94#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.07:37:59.94#ibcon#ireg 11 cls_cnt 2 2006.173.07:37:59.94#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.07:38:00.00#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.07:38:00.00#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.07:38:00.00#ibcon#enter wrdev, iclass 22, count 2 2006.173.07:38:00.00#ibcon#first serial, iclass 22, count 2 2006.173.07:38:00.00#ibcon#enter sib2, iclass 22, count 2 2006.173.07:38:00.00#ibcon#flushed, iclass 22, count 2 2006.173.07:38:00.00#ibcon#about to write, iclass 22, count 2 2006.173.07:38:00.00#ibcon#wrote, iclass 22, count 2 2006.173.07:38:00.00#ibcon#about to read 3, iclass 22, count 2 2006.173.07:38:00.02#ibcon#read 3, iclass 22, count 2 2006.173.07:38:00.02#ibcon#about to read 4, iclass 22, count 2 2006.173.07:38:00.02#ibcon#read 4, iclass 22, count 2 2006.173.07:38:00.02#ibcon#about to read 5, iclass 22, count 2 2006.173.07:38:00.02#ibcon#read 5, iclass 22, count 2 2006.173.07:38:00.02#ibcon#about to read 6, iclass 22, count 2 2006.173.07:38:00.02#ibcon#read 6, iclass 22, count 2 2006.173.07:38:00.02#ibcon#end of sib2, iclass 22, count 2 2006.173.07:38:00.02#ibcon#*mode == 0, iclass 22, count 2 2006.173.07:38:00.02#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.07:38:00.02#ibcon#[25=AT06-03\r\n] 2006.173.07:38:00.02#ibcon#*before write, iclass 22, count 2 2006.173.07:38:00.02#ibcon#enter sib2, iclass 22, count 2 2006.173.07:38:00.02#ibcon#flushed, iclass 22, count 2 2006.173.07:38:00.02#ibcon#about to write, iclass 22, count 2 2006.173.07:38:00.02#ibcon#wrote, iclass 22, count 2 2006.173.07:38:00.02#ibcon#about to read 3, iclass 22, count 2 2006.173.07:38:00.05#ibcon#read 3, iclass 22, count 2 2006.173.07:38:00.05#ibcon#about to read 4, iclass 22, count 2 2006.173.07:38:00.05#ibcon#read 4, iclass 22, count 2 2006.173.07:38:00.05#ibcon#about to read 5, iclass 22, count 2 2006.173.07:38:00.05#ibcon#read 5, iclass 22, count 2 2006.173.07:38:00.05#ibcon#about to read 6, iclass 22, count 2 2006.173.07:38:00.05#ibcon#read 6, iclass 22, count 2 2006.173.07:38:00.05#ibcon#end of sib2, iclass 22, count 2 2006.173.07:38:00.05#ibcon#*after write, iclass 22, count 2 2006.173.07:38:00.05#ibcon#*before return 0, iclass 22, count 2 2006.173.07:38:00.05#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.07:38:00.05#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.07:38:00.05#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.07:38:00.05#ibcon#ireg 7 cls_cnt 0 2006.173.07:38:00.05#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.07:38:00.17#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.07:38:00.17#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.07:38:00.17#ibcon#enter wrdev, iclass 22, count 0 2006.173.07:38:00.17#ibcon#first serial, iclass 22, count 0 2006.173.07:38:00.17#ibcon#enter sib2, iclass 22, count 0 2006.173.07:38:00.17#ibcon#flushed, iclass 22, count 0 2006.173.07:38:00.17#ibcon#about to write, iclass 22, count 0 2006.173.07:38:00.17#ibcon#wrote, iclass 22, count 0 2006.173.07:38:00.17#ibcon#about to read 3, iclass 22, count 0 2006.173.07:38:00.19#ibcon#read 3, iclass 22, count 0 2006.173.07:38:00.19#ibcon#about to read 4, iclass 22, count 0 2006.173.07:38:00.19#ibcon#read 4, iclass 22, count 0 2006.173.07:38:00.19#ibcon#about to read 5, iclass 22, count 0 2006.173.07:38:00.19#ibcon#read 5, iclass 22, count 0 2006.173.07:38:00.19#ibcon#about to read 6, iclass 22, count 0 2006.173.07:38:00.19#ibcon#read 6, iclass 22, count 0 2006.173.07:38:00.19#ibcon#end of sib2, iclass 22, count 0 2006.173.07:38:00.19#ibcon#*mode == 0, iclass 22, count 0 2006.173.07:38:00.19#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.07:38:00.19#ibcon#[25=USB\r\n] 2006.173.07:38:00.19#ibcon#*before write, iclass 22, count 0 2006.173.07:38:00.19#ibcon#enter sib2, iclass 22, count 0 2006.173.07:38:00.19#ibcon#flushed, iclass 22, count 0 2006.173.07:38:00.19#ibcon#about to write, iclass 22, count 0 2006.173.07:38:00.19#ibcon#wrote, iclass 22, count 0 2006.173.07:38:00.19#ibcon#about to read 3, iclass 22, count 0 2006.173.07:38:00.22#ibcon#read 3, iclass 22, count 0 2006.173.07:38:00.22#ibcon#about to read 4, iclass 22, count 0 2006.173.07:38:00.22#ibcon#read 4, iclass 22, count 0 2006.173.07:38:00.22#ibcon#about to read 5, iclass 22, count 0 2006.173.07:38:00.22#ibcon#read 5, iclass 22, count 0 2006.173.07:38:00.22#ibcon#about to read 6, iclass 22, count 0 2006.173.07:38:00.22#ibcon#read 6, iclass 22, count 0 2006.173.07:38:00.22#ibcon#end of sib2, iclass 22, count 0 2006.173.07:38:00.22#ibcon#*after write, iclass 22, count 0 2006.173.07:38:00.22#ibcon#*before return 0, iclass 22, count 0 2006.173.07:38:00.22#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.07:38:00.22#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.07:38:00.22#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.07:38:00.22#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.07:38:00.22$vck44/valo=7,864.99 2006.173.07:38:00.22#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.07:38:00.22#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.07:38:00.22#ibcon#ireg 17 cls_cnt 0 2006.173.07:38:00.22#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.07:38:00.22#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.07:38:00.22#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.07:38:00.22#ibcon#enter wrdev, iclass 24, count 0 2006.173.07:38:00.22#ibcon#first serial, iclass 24, count 0 2006.173.07:38:00.22#ibcon#enter sib2, iclass 24, count 0 2006.173.07:38:00.22#ibcon#flushed, iclass 24, count 0 2006.173.07:38:00.22#ibcon#about to write, iclass 24, count 0 2006.173.07:38:00.22#ibcon#wrote, iclass 24, count 0 2006.173.07:38:00.22#ibcon#about to read 3, iclass 24, count 0 2006.173.07:38:00.24#ibcon#read 3, iclass 24, count 0 2006.173.07:38:00.24#ibcon#about to read 4, iclass 24, count 0 2006.173.07:38:00.24#ibcon#read 4, iclass 24, count 0 2006.173.07:38:00.24#ibcon#about to read 5, iclass 24, count 0 2006.173.07:38:00.24#ibcon#read 5, iclass 24, count 0 2006.173.07:38:00.24#ibcon#about to read 6, iclass 24, count 0 2006.173.07:38:00.24#ibcon#read 6, iclass 24, count 0 2006.173.07:38:00.24#ibcon#end of sib2, iclass 24, count 0 2006.173.07:38:00.24#ibcon#*mode == 0, iclass 24, count 0 2006.173.07:38:00.24#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.07:38:00.24#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.07:38:00.24#ibcon#*before write, iclass 24, count 0 2006.173.07:38:00.24#ibcon#enter sib2, iclass 24, count 0 2006.173.07:38:00.24#ibcon#flushed, iclass 24, count 0 2006.173.07:38:00.24#ibcon#about to write, iclass 24, count 0 2006.173.07:38:00.24#ibcon#wrote, iclass 24, count 0 2006.173.07:38:00.24#ibcon#about to read 3, iclass 24, count 0 2006.173.07:38:00.28#ibcon#read 3, iclass 24, count 0 2006.173.07:38:00.28#ibcon#about to read 4, iclass 24, count 0 2006.173.07:38:00.28#ibcon#read 4, iclass 24, count 0 2006.173.07:38:00.28#ibcon#about to read 5, iclass 24, count 0 2006.173.07:38:00.28#ibcon#read 5, iclass 24, count 0 2006.173.07:38:00.28#ibcon#about to read 6, iclass 24, count 0 2006.173.07:38:00.28#ibcon#read 6, iclass 24, count 0 2006.173.07:38:00.28#ibcon#end of sib2, iclass 24, count 0 2006.173.07:38:00.28#ibcon#*after write, iclass 24, count 0 2006.173.07:38:00.28#ibcon#*before return 0, iclass 24, count 0 2006.173.07:38:00.28#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.07:38:00.28#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.07:38:00.28#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.07:38:00.28#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.07:38:00.28$vck44/va=7,4 2006.173.07:38:00.28#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.07:38:00.28#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.07:38:00.28#ibcon#ireg 11 cls_cnt 2 2006.173.07:38:00.28#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.07:38:00.34#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.07:38:00.34#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.07:38:00.34#ibcon#enter wrdev, iclass 26, count 2 2006.173.07:38:00.34#ibcon#first serial, iclass 26, count 2 2006.173.07:38:00.34#ibcon#enter sib2, iclass 26, count 2 2006.173.07:38:00.34#ibcon#flushed, iclass 26, count 2 2006.173.07:38:00.34#ibcon#about to write, iclass 26, count 2 2006.173.07:38:00.34#ibcon#wrote, iclass 26, count 2 2006.173.07:38:00.34#ibcon#about to read 3, iclass 26, count 2 2006.173.07:38:00.36#ibcon#read 3, iclass 26, count 2 2006.173.07:38:00.36#ibcon#about to read 4, iclass 26, count 2 2006.173.07:38:00.36#ibcon#read 4, iclass 26, count 2 2006.173.07:38:00.36#ibcon#about to read 5, iclass 26, count 2 2006.173.07:38:00.36#ibcon#read 5, iclass 26, count 2 2006.173.07:38:00.36#ibcon#about to read 6, iclass 26, count 2 2006.173.07:38:00.36#ibcon#read 6, iclass 26, count 2 2006.173.07:38:00.36#ibcon#end of sib2, iclass 26, count 2 2006.173.07:38:00.36#ibcon#*mode == 0, iclass 26, count 2 2006.173.07:38:00.36#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.07:38:00.36#ibcon#[25=AT07-04\r\n] 2006.173.07:38:00.36#ibcon#*before write, iclass 26, count 2 2006.173.07:38:00.36#ibcon#enter sib2, iclass 26, count 2 2006.173.07:38:00.36#ibcon#flushed, iclass 26, count 2 2006.173.07:38:00.36#ibcon#about to write, iclass 26, count 2 2006.173.07:38:00.36#ibcon#wrote, iclass 26, count 2 2006.173.07:38:00.36#ibcon#about to read 3, iclass 26, count 2 2006.173.07:38:00.39#ibcon#read 3, iclass 26, count 2 2006.173.07:38:00.39#ibcon#about to read 4, iclass 26, count 2 2006.173.07:38:00.39#ibcon#read 4, iclass 26, count 2 2006.173.07:38:00.39#ibcon#about to read 5, iclass 26, count 2 2006.173.07:38:00.39#ibcon#read 5, iclass 26, count 2 2006.173.07:38:00.39#ibcon#about to read 6, iclass 26, count 2 2006.173.07:38:00.39#ibcon#read 6, iclass 26, count 2 2006.173.07:38:00.39#ibcon#end of sib2, iclass 26, count 2 2006.173.07:38:00.39#ibcon#*after write, iclass 26, count 2 2006.173.07:38:00.39#ibcon#*before return 0, iclass 26, count 2 2006.173.07:38:00.39#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.07:38:00.39#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.07:38:00.39#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.07:38:00.39#ibcon#ireg 7 cls_cnt 0 2006.173.07:38:00.39#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.07:38:00.51#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.07:38:00.51#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.07:38:00.51#ibcon#enter wrdev, iclass 26, count 0 2006.173.07:38:00.51#ibcon#first serial, iclass 26, count 0 2006.173.07:38:00.51#ibcon#enter sib2, iclass 26, count 0 2006.173.07:38:00.51#ibcon#flushed, iclass 26, count 0 2006.173.07:38:00.51#ibcon#about to write, iclass 26, count 0 2006.173.07:38:00.51#ibcon#wrote, iclass 26, count 0 2006.173.07:38:00.51#ibcon#about to read 3, iclass 26, count 0 2006.173.07:38:00.53#ibcon#read 3, iclass 26, count 0 2006.173.07:38:00.53#ibcon#about to read 4, iclass 26, count 0 2006.173.07:38:00.53#ibcon#read 4, iclass 26, count 0 2006.173.07:38:00.53#ibcon#about to read 5, iclass 26, count 0 2006.173.07:38:00.53#ibcon#read 5, iclass 26, count 0 2006.173.07:38:00.53#ibcon#about to read 6, iclass 26, count 0 2006.173.07:38:00.53#ibcon#read 6, iclass 26, count 0 2006.173.07:38:00.53#ibcon#end of sib2, iclass 26, count 0 2006.173.07:38:00.53#ibcon#*mode == 0, iclass 26, count 0 2006.173.07:38:00.53#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.07:38:00.53#ibcon#[25=USB\r\n] 2006.173.07:38:00.53#ibcon#*before write, iclass 26, count 0 2006.173.07:38:00.53#ibcon#enter sib2, iclass 26, count 0 2006.173.07:38:00.53#ibcon#flushed, iclass 26, count 0 2006.173.07:38:00.53#ibcon#about to write, iclass 26, count 0 2006.173.07:38:00.53#ibcon#wrote, iclass 26, count 0 2006.173.07:38:00.53#ibcon#about to read 3, iclass 26, count 0 2006.173.07:38:00.56#ibcon#read 3, iclass 26, count 0 2006.173.07:38:00.56#ibcon#about to read 4, iclass 26, count 0 2006.173.07:38:00.56#ibcon#read 4, iclass 26, count 0 2006.173.07:38:00.56#ibcon#about to read 5, iclass 26, count 0 2006.173.07:38:00.56#ibcon#read 5, iclass 26, count 0 2006.173.07:38:00.56#ibcon#about to read 6, iclass 26, count 0 2006.173.07:38:00.56#ibcon#read 6, iclass 26, count 0 2006.173.07:38:00.56#ibcon#end of sib2, iclass 26, count 0 2006.173.07:38:00.56#ibcon#*after write, iclass 26, count 0 2006.173.07:38:00.56#ibcon#*before return 0, iclass 26, count 0 2006.173.07:38:00.56#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.07:38:00.56#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.07:38:00.56#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.07:38:00.56#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.07:38:00.56$vck44/valo=8,884.99 2006.173.07:38:00.56#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.07:38:00.56#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.07:38:00.56#ibcon#ireg 17 cls_cnt 0 2006.173.07:38:00.56#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.07:38:00.56#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.07:38:00.56#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.07:38:00.56#ibcon#enter wrdev, iclass 28, count 0 2006.173.07:38:00.56#ibcon#first serial, iclass 28, count 0 2006.173.07:38:00.56#ibcon#enter sib2, iclass 28, count 0 2006.173.07:38:00.56#ibcon#flushed, iclass 28, count 0 2006.173.07:38:00.56#ibcon#about to write, iclass 28, count 0 2006.173.07:38:00.56#ibcon#wrote, iclass 28, count 0 2006.173.07:38:00.56#ibcon#about to read 3, iclass 28, count 0 2006.173.07:38:00.58#ibcon#read 3, iclass 28, count 0 2006.173.07:38:00.58#ibcon#about to read 4, iclass 28, count 0 2006.173.07:38:00.58#ibcon#read 4, iclass 28, count 0 2006.173.07:38:00.58#ibcon#about to read 5, iclass 28, count 0 2006.173.07:38:00.58#ibcon#read 5, iclass 28, count 0 2006.173.07:38:00.58#ibcon#about to read 6, iclass 28, count 0 2006.173.07:38:00.58#ibcon#read 6, iclass 28, count 0 2006.173.07:38:00.58#ibcon#end of sib2, iclass 28, count 0 2006.173.07:38:00.58#ibcon#*mode == 0, iclass 28, count 0 2006.173.07:38:00.58#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.07:38:00.58#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.07:38:00.58#ibcon#*before write, iclass 28, count 0 2006.173.07:38:00.58#ibcon#enter sib2, iclass 28, count 0 2006.173.07:38:00.58#ibcon#flushed, iclass 28, count 0 2006.173.07:38:00.58#ibcon#about to write, iclass 28, count 0 2006.173.07:38:00.58#ibcon#wrote, iclass 28, count 0 2006.173.07:38:00.58#ibcon#about to read 3, iclass 28, count 0 2006.173.07:38:00.62#ibcon#read 3, iclass 28, count 0 2006.173.07:38:00.62#ibcon#about to read 4, iclass 28, count 0 2006.173.07:38:00.62#ibcon#read 4, iclass 28, count 0 2006.173.07:38:00.62#ibcon#about to read 5, iclass 28, count 0 2006.173.07:38:00.62#ibcon#read 5, iclass 28, count 0 2006.173.07:38:00.62#ibcon#about to read 6, iclass 28, count 0 2006.173.07:38:00.62#ibcon#read 6, iclass 28, count 0 2006.173.07:38:00.62#ibcon#end of sib2, iclass 28, count 0 2006.173.07:38:00.62#ibcon#*after write, iclass 28, count 0 2006.173.07:38:00.62#ibcon#*before return 0, iclass 28, count 0 2006.173.07:38:00.62#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.07:38:00.62#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.07:38:00.62#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.07:38:00.62#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.07:38:00.62$vck44/va=8,4 2006.173.07:38:00.62#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.07:38:00.62#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.07:38:00.62#ibcon#ireg 11 cls_cnt 2 2006.173.07:38:00.62#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.07:38:00.68#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.07:38:00.68#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.07:38:00.68#ibcon#enter wrdev, iclass 30, count 2 2006.173.07:38:00.68#ibcon#first serial, iclass 30, count 2 2006.173.07:38:00.68#ibcon#enter sib2, iclass 30, count 2 2006.173.07:38:00.68#ibcon#flushed, iclass 30, count 2 2006.173.07:38:00.68#ibcon#about to write, iclass 30, count 2 2006.173.07:38:00.68#ibcon#wrote, iclass 30, count 2 2006.173.07:38:00.68#ibcon#about to read 3, iclass 30, count 2 2006.173.07:38:00.70#ibcon#read 3, iclass 30, count 2 2006.173.07:38:00.70#ibcon#about to read 4, iclass 30, count 2 2006.173.07:38:00.70#ibcon#read 4, iclass 30, count 2 2006.173.07:38:00.70#ibcon#about to read 5, iclass 30, count 2 2006.173.07:38:00.70#ibcon#read 5, iclass 30, count 2 2006.173.07:38:00.70#ibcon#about to read 6, iclass 30, count 2 2006.173.07:38:00.70#ibcon#read 6, iclass 30, count 2 2006.173.07:38:00.70#ibcon#end of sib2, iclass 30, count 2 2006.173.07:38:00.70#ibcon#*mode == 0, iclass 30, count 2 2006.173.07:38:00.70#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.07:38:00.70#ibcon#[25=AT08-04\r\n] 2006.173.07:38:00.70#ibcon#*before write, iclass 30, count 2 2006.173.07:38:00.70#ibcon#enter sib2, iclass 30, count 2 2006.173.07:38:00.70#ibcon#flushed, iclass 30, count 2 2006.173.07:38:00.70#ibcon#about to write, iclass 30, count 2 2006.173.07:38:00.70#ibcon#wrote, iclass 30, count 2 2006.173.07:38:00.70#ibcon#about to read 3, iclass 30, count 2 2006.173.07:38:00.73#ibcon#read 3, iclass 30, count 2 2006.173.07:38:00.73#ibcon#about to read 4, iclass 30, count 2 2006.173.07:38:00.73#ibcon#read 4, iclass 30, count 2 2006.173.07:38:00.73#ibcon#about to read 5, iclass 30, count 2 2006.173.07:38:00.73#ibcon#read 5, iclass 30, count 2 2006.173.07:38:00.73#ibcon#about to read 6, iclass 30, count 2 2006.173.07:38:00.73#ibcon#read 6, iclass 30, count 2 2006.173.07:38:00.73#ibcon#end of sib2, iclass 30, count 2 2006.173.07:38:00.73#ibcon#*after write, iclass 30, count 2 2006.173.07:38:00.73#ibcon#*before return 0, iclass 30, count 2 2006.173.07:38:00.73#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.07:38:00.73#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.07:38:00.73#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.07:38:00.73#ibcon#ireg 7 cls_cnt 0 2006.173.07:38:00.73#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.07:38:00.85#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.07:38:00.85#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.07:38:00.85#ibcon#enter wrdev, iclass 30, count 0 2006.173.07:38:00.85#ibcon#first serial, iclass 30, count 0 2006.173.07:38:00.85#ibcon#enter sib2, iclass 30, count 0 2006.173.07:38:00.85#ibcon#flushed, iclass 30, count 0 2006.173.07:38:00.85#ibcon#about to write, iclass 30, count 0 2006.173.07:38:00.85#ibcon#wrote, iclass 30, count 0 2006.173.07:38:00.85#ibcon#about to read 3, iclass 30, count 0 2006.173.07:38:00.87#ibcon#read 3, iclass 30, count 0 2006.173.07:38:00.87#ibcon#about to read 4, iclass 30, count 0 2006.173.07:38:00.87#ibcon#read 4, iclass 30, count 0 2006.173.07:38:00.87#ibcon#about to read 5, iclass 30, count 0 2006.173.07:38:00.87#ibcon#read 5, iclass 30, count 0 2006.173.07:38:00.87#ibcon#about to read 6, iclass 30, count 0 2006.173.07:38:00.87#ibcon#read 6, iclass 30, count 0 2006.173.07:38:00.87#ibcon#end of sib2, iclass 30, count 0 2006.173.07:38:00.87#ibcon#*mode == 0, iclass 30, count 0 2006.173.07:38:00.87#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.07:38:00.87#ibcon#[25=USB\r\n] 2006.173.07:38:00.87#ibcon#*before write, iclass 30, count 0 2006.173.07:38:00.87#ibcon#enter sib2, iclass 30, count 0 2006.173.07:38:00.87#ibcon#flushed, iclass 30, count 0 2006.173.07:38:00.87#ibcon#about to write, iclass 30, count 0 2006.173.07:38:00.87#ibcon#wrote, iclass 30, count 0 2006.173.07:38:00.87#ibcon#about to read 3, iclass 30, count 0 2006.173.07:38:00.90#ibcon#read 3, iclass 30, count 0 2006.173.07:38:00.90#ibcon#about to read 4, iclass 30, count 0 2006.173.07:38:00.90#ibcon#read 4, iclass 30, count 0 2006.173.07:38:00.90#ibcon#about to read 5, iclass 30, count 0 2006.173.07:38:00.90#ibcon#read 5, iclass 30, count 0 2006.173.07:38:00.90#ibcon#about to read 6, iclass 30, count 0 2006.173.07:38:00.90#ibcon#read 6, iclass 30, count 0 2006.173.07:38:00.90#ibcon#end of sib2, iclass 30, count 0 2006.173.07:38:00.90#ibcon#*after write, iclass 30, count 0 2006.173.07:38:00.90#ibcon#*before return 0, iclass 30, count 0 2006.173.07:38:00.90#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.07:38:00.90#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.07:38:00.90#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.07:38:00.90#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.07:38:00.90$vck44/vblo=1,629.99 2006.173.07:38:00.90#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.07:38:00.90#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.07:38:00.90#ibcon#ireg 17 cls_cnt 0 2006.173.07:38:00.90#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.07:38:00.90#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.07:38:00.90#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.07:38:00.90#ibcon#enter wrdev, iclass 32, count 0 2006.173.07:38:00.90#ibcon#first serial, iclass 32, count 0 2006.173.07:38:00.90#ibcon#enter sib2, iclass 32, count 0 2006.173.07:38:00.90#ibcon#flushed, iclass 32, count 0 2006.173.07:38:00.90#ibcon#about to write, iclass 32, count 0 2006.173.07:38:00.90#ibcon#wrote, iclass 32, count 0 2006.173.07:38:00.90#ibcon#about to read 3, iclass 32, count 0 2006.173.07:38:00.92#ibcon#read 3, iclass 32, count 0 2006.173.07:38:00.92#ibcon#about to read 4, iclass 32, count 0 2006.173.07:38:00.92#ibcon#read 4, iclass 32, count 0 2006.173.07:38:00.92#ibcon#about to read 5, iclass 32, count 0 2006.173.07:38:00.92#ibcon#read 5, iclass 32, count 0 2006.173.07:38:00.92#ibcon#about to read 6, iclass 32, count 0 2006.173.07:38:00.92#ibcon#read 6, iclass 32, count 0 2006.173.07:38:00.92#ibcon#end of sib2, iclass 32, count 0 2006.173.07:38:00.92#ibcon#*mode == 0, iclass 32, count 0 2006.173.07:38:00.92#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.07:38:00.92#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.07:38:00.92#ibcon#*before write, iclass 32, count 0 2006.173.07:38:00.92#ibcon#enter sib2, iclass 32, count 0 2006.173.07:38:00.92#ibcon#flushed, iclass 32, count 0 2006.173.07:38:00.92#ibcon#about to write, iclass 32, count 0 2006.173.07:38:00.92#ibcon#wrote, iclass 32, count 0 2006.173.07:38:00.92#ibcon#about to read 3, iclass 32, count 0 2006.173.07:38:00.96#ibcon#read 3, iclass 32, count 0 2006.173.07:38:00.96#ibcon#about to read 4, iclass 32, count 0 2006.173.07:38:00.96#ibcon#read 4, iclass 32, count 0 2006.173.07:38:00.96#ibcon#about to read 5, iclass 32, count 0 2006.173.07:38:00.96#ibcon#read 5, iclass 32, count 0 2006.173.07:38:00.96#ibcon#about to read 6, iclass 32, count 0 2006.173.07:38:00.96#ibcon#read 6, iclass 32, count 0 2006.173.07:38:00.96#ibcon#end of sib2, iclass 32, count 0 2006.173.07:38:00.96#ibcon#*after write, iclass 32, count 0 2006.173.07:38:00.96#ibcon#*before return 0, iclass 32, count 0 2006.173.07:38:00.96#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.07:38:00.96#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.07:38:00.96#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.07:38:00.96#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.07:38:00.96$vck44/vb=1,4 2006.173.07:38:00.96#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.07:38:00.96#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.07:38:00.96#ibcon#ireg 11 cls_cnt 2 2006.173.07:38:00.96#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.07:38:00.96#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.07:38:00.96#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.07:38:00.96#ibcon#enter wrdev, iclass 34, count 2 2006.173.07:38:00.96#ibcon#first serial, iclass 34, count 2 2006.173.07:38:00.96#ibcon#enter sib2, iclass 34, count 2 2006.173.07:38:00.96#ibcon#flushed, iclass 34, count 2 2006.173.07:38:00.96#ibcon#about to write, iclass 34, count 2 2006.173.07:38:00.96#ibcon#wrote, iclass 34, count 2 2006.173.07:38:00.96#ibcon#about to read 3, iclass 34, count 2 2006.173.07:38:00.98#ibcon#read 3, iclass 34, count 2 2006.173.07:38:00.98#ibcon#about to read 4, iclass 34, count 2 2006.173.07:38:00.98#ibcon#read 4, iclass 34, count 2 2006.173.07:38:00.98#ibcon#about to read 5, iclass 34, count 2 2006.173.07:38:00.98#ibcon#read 5, iclass 34, count 2 2006.173.07:38:00.98#ibcon#about to read 6, iclass 34, count 2 2006.173.07:38:00.98#ibcon#read 6, iclass 34, count 2 2006.173.07:38:00.98#ibcon#end of sib2, iclass 34, count 2 2006.173.07:38:00.98#ibcon#*mode == 0, iclass 34, count 2 2006.173.07:38:00.98#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.07:38:00.98#ibcon#[27=AT01-04\r\n] 2006.173.07:38:00.98#ibcon#*before write, iclass 34, count 2 2006.173.07:38:00.98#ibcon#enter sib2, iclass 34, count 2 2006.173.07:38:00.98#ibcon#flushed, iclass 34, count 2 2006.173.07:38:00.98#ibcon#about to write, iclass 34, count 2 2006.173.07:38:00.98#ibcon#wrote, iclass 34, count 2 2006.173.07:38:00.98#ibcon#about to read 3, iclass 34, count 2 2006.173.07:38:01.01#ibcon#read 3, iclass 34, count 2 2006.173.07:38:01.01#ibcon#about to read 4, iclass 34, count 2 2006.173.07:38:01.01#ibcon#read 4, iclass 34, count 2 2006.173.07:38:01.01#ibcon#about to read 5, iclass 34, count 2 2006.173.07:38:01.01#ibcon#read 5, iclass 34, count 2 2006.173.07:38:01.01#ibcon#about to read 6, iclass 34, count 2 2006.173.07:38:01.01#ibcon#read 6, iclass 34, count 2 2006.173.07:38:01.01#ibcon#end of sib2, iclass 34, count 2 2006.173.07:38:01.01#ibcon#*after write, iclass 34, count 2 2006.173.07:38:01.01#ibcon#*before return 0, iclass 34, count 2 2006.173.07:38:01.01#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.07:38:01.01#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.07:38:01.01#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.07:38:01.01#ibcon#ireg 7 cls_cnt 0 2006.173.07:38:01.01#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.07:38:01.14#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.07:38:01.14#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.07:38:01.14#ibcon#enter wrdev, iclass 34, count 0 2006.173.07:38:01.14#ibcon#first serial, iclass 34, count 0 2006.173.07:38:01.14#ibcon#enter sib2, iclass 34, count 0 2006.173.07:38:01.14#ibcon#flushed, iclass 34, count 0 2006.173.07:38:01.14#ibcon#about to write, iclass 34, count 0 2006.173.07:38:01.14#ibcon#wrote, iclass 34, count 0 2006.173.07:38:01.14#ibcon#about to read 3, iclass 34, count 0 2006.173.07:38:01.16#ibcon#read 3, iclass 34, count 0 2006.173.07:38:01.16#ibcon#about to read 4, iclass 34, count 0 2006.173.07:38:01.16#ibcon#read 4, iclass 34, count 0 2006.173.07:38:01.16#ibcon#about to read 5, iclass 34, count 0 2006.173.07:38:01.16#ibcon#read 5, iclass 34, count 0 2006.173.07:38:01.16#ibcon#about to read 6, iclass 34, count 0 2006.173.07:38:01.16#ibcon#read 6, iclass 34, count 0 2006.173.07:38:01.16#ibcon#end of sib2, iclass 34, count 0 2006.173.07:38:01.16#ibcon#*mode == 0, iclass 34, count 0 2006.173.07:38:01.16#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.07:38:01.16#ibcon#[27=USB\r\n] 2006.173.07:38:01.16#ibcon#*before write, iclass 34, count 0 2006.173.07:38:01.16#ibcon#enter sib2, iclass 34, count 0 2006.173.07:38:01.16#ibcon#flushed, iclass 34, count 0 2006.173.07:38:01.16#ibcon#about to write, iclass 34, count 0 2006.173.07:38:01.16#ibcon#wrote, iclass 34, count 0 2006.173.07:38:01.16#ibcon#about to read 3, iclass 34, count 0 2006.173.07:38:01.19#ibcon#read 3, iclass 34, count 0 2006.173.07:38:01.19#ibcon#about to read 4, iclass 34, count 0 2006.173.07:38:01.19#ibcon#read 4, iclass 34, count 0 2006.173.07:38:01.19#ibcon#about to read 5, iclass 34, count 0 2006.173.07:38:01.19#ibcon#read 5, iclass 34, count 0 2006.173.07:38:01.19#ibcon#about to read 6, iclass 34, count 0 2006.173.07:38:01.19#ibcon#read 6, iclass 34, count 0 2006.173.07:38:01.19#ibcon#end of sib2, iclass 34, count 0 2006.173.07:38:01.19#ibcon#*after write, iclass 34, count 0 2006.173.07:38:01.19#ibcon#*before return 0, iclass 34, count 0 2006.173.07:38:01.19#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.07:38:01.19#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.07:38:01.19#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.07:38:01.19#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.07:38:01.19$vck44/vblo=2,634.99 2006.173.07:38:01.19#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.07:38:01.19#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.07:38:01.19#ibcon#ireg 17 cls_cnt 0 2006.173.07:38:01.19#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.07:38:01.19#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.07:38:01.19#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.07:38:01.19#ibcon#enter wrdev, iclass 36, count 0 2006.173.07:38:01.19#ibcon#first serial, iclass 36, count 0 2006.173.07:38:01.19#ibcon#enter sib2, iclass 36, count 0 2006.173.07:38:01.19#ibcon#flushed, iclass 36, count 0 2006.173.07:38:01.19#ibcon#about to write, iclass 36, count 0 2006.173.07:38:01.19#ibcon#wrote, iclass 36, count 0 2006.173.07:38:01.19#ibcon#about to read 3, iclass 36, count 0 2006.173.07:38:01.21#ibcon#read 3, iclass 36, count 0 2006.173.07:38:01.21#ibcon#about to read 4, iclass 36, count 0 2006.173.07:38:01.21#ibcon#read 4, iclass 36, count 0 2006.173.07:38:01.21#ibcon#about to read 5, iclass 36, count 0 2006.173.07:38:01.21#ibcon#read 5, iclass 36, count 0 2006.173.07:38:01.21#ibcon#about to read 6, iclass 36, count 0 2006.173.07:38:01.21#ibcon#read 6, iclass 36, count 0 2006.173.07:38:01.21#ibcon#end of sib2, iclass 36, count 0 2006.173.07:38:01.21#ibcon#*mode == 0, iclass 36, count 0 2006.173.07:38:01.21#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.07:38:01.21#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.07:38:01.21#ibcon#*before write, iclass 36, count 0 2006.173.07:38:01.21#ibcon#enter sib2, iclass 36, count 0 2006.173.07:38:01.21#ibcon#flushed, iclass 36, count 0 2006.173.07:38:01.21#ibcon#about to write, iclass 36, count 0 2006.173.07:38:01.21#ibcon#wrote, iclass 36, count 0 2006.173.07:38:01.21#ibcon#about to read 3, iclass 36, count 0 2006.173.07:38:01.25#ibcon#read 3, iclass 36, count 0 2006.173.07:38:01.25#ibcon#about to read 4, iclass 36, count 0 2006.173.07:38:01.25#ibcon#read 4, iclass 36, count 0 2006.173.07:38:01.25#ibcon#about to read 5, iclass 36, count 0 2006.173.07:38:01.25#ibcon#read 5, iclass 36, count 0 2006.173.07:38:01.25#ibcon#about to read 6, iclass 36, count 0 2006.173.07:38:01.25#ibcon#read 6, iclass 36, count 0 2006.173.07:38:01.25#ibcon#end of sib2, iclass 36, count 0 2006.173.07:38:01.25#ibcon#*after write, iclass 36, count 0 2006.173.07:38:01.25#ibcon#*before return 0, iclass 36, count 0 2006.173.07:38:01.25#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.07:38:01.25#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.07:38:01.25#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.07:38:01.25#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.07:38:01.25$vck44/vb=2,4 2006.173.07:38:01.25#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.07:38:01.25#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.07:38:01.25#ibcon#ireg 11 cls_cnt 2 2006.173.07:38:01.25#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.07:38:01.31#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.07:38:01.31#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.07:38:01.31#ibcon#enter wrdev, iclass 38, count 2 2006.173.07:38:01.31#ibcon#first serial, iclass 38, count 2 2006.173.07:38:01.31#ibcon#enter sib2, iclass 38, count 2 2006.173.07:38:01.31#ibcon#flushed, iclass 38, count 2 2006.173.07:38:01.31#ibcon#about to write, iclass 38, count 2 2006.173.07:38:01.31#ibcon#wrote, iclass 38, count 2 2006.173.07:38:01.31#ibcon#about to read 3, iclass 38, count 2 2006.173.07:38:01.33#ibcon#read 3, iclass 38, count 2 2006.173.07:38:01.33#ibcon#about to read 4, iclass 38, count 2 2006.173.07:38:01.33#ibcon#read 4, iclass 38, count 2 2006.173.07:38:01.33#ibcon#about to read 5, iclass 38, count 2 2006.173.07:38:01.33#ibcon#read 5, iclass 38, count 2 2006.173.07:38:01.33#ibcon#about to read 6, iclass 38, count 2 2006.173.07:38:01.33#ibcon#read 6, iclass 38, count 2 2006.173.07:38:01.33#ibcon#end of sib2, iclass 38, count 2 2006.173.07:38:01.33#ibcon#*mode == 0, iclass 38, count 2 2006.173.07:38:01.33#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.07:38:01.33#ibcon#[27=AT02-04\r\n] 2006.173.07:38:01.33#ibcon#*before write, iclass 38, count 2 2006.173.07:38:01.33#ibcon#enter sib2, iclass 38, count 2 2006.173.07:38:01.33#ibcon#flushed, iclass 38, count 2 2006.173.07:38:01.33#ibcon#about to write, iclass 38, count 2 2006.173.07:38:01.33#ibcon#wrote, iclass 38, count 2 2006.173.07:38:01.33#ibcon#about to read 3, iclass 38, count 2 2006.173.07:38:01.36#ibcon#read 3, iclass 38, count 2 2006.173.07:38:01.36#ibcon#about to read 4, iclass 38, count 2 2006.173.07:38:01.36#ibcon#read 4, iclass 38, count 2 2006.173.07:38:01.36#ibcon#about to read 5, iclass 38, count 2 2006.173.07:38:01.36#ibcon#read 5, iclass 38, count 2 2006.173.07:38:01.36#ibcon#about to read 6, iclass 38, count 2 2006.173.07:38:01.36#ibcon#read 6, iclass 38, count 2 2006.173.07:38:01.36#ibcon#end of sib2, iclass 38, count 2 2006.173.07:38:01.36#ibcon#*after write, iclass 38, count 2 2006.173.07:38:01.36#ibcon#*before return 0, iclass 38, count 2 2006.173.07:38:01.36#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.07:38:01.36#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.07:38:01.36#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.07:38:01.36#ibcon#ireg 7 cls_cnt 0 2006.173.07:38:01.36#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.07:38:01.48#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.07:38:01.48#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.07:38:01.48#ibcon#enter wrdev, iclass 38, count 0 2006.173.07:38:01.48#ibcon#first serial, iclass 38, count 0 2006.173.07:38:01.48#ibcon#enter sib2, iclass 38, count 0 2006.173.07:38:01.48#ibcon#flushed, iclass 38, count 0 2006.173.07:38:01.48#ibcon#about to write, iclass 38, count 0 2006.173.07:38:01.48#ibcon#wrote, iclass 38, count 0 2006.173.07:38:01.48#ibcon#about to read 3, iclass 38, count 0 2006.173.07:38:01.50#ibcon#read 3, iclass 38, count 0 2006.173.07:38:01.50#ibcon#about to read 4, iclass 38, count 0 2006.173.07:38:01.50#ibcon#read 4, iclass 38, count 0 2006.173.07:38:01.50#ibcon#about to read 5, iclass 38, count 0 2006.173.07:38:01.50#ibcon#read 5, iclass 38, count 0 2006.173.07:38:01.50#ibcon#about to read 6, iclass 38, count 0 2006.173.07:38:01.50#ibcon#read 6, iclass 38, count 0 2006.173.07:38:01.50#ibcon#end of sib2, iclass 38, count 0 2006.173.07:38:01.50#ibcon#*mode == 0, iclass 38, count 0 2006.173.07:38:01.50#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.07:38:01.50#ibcon#[27=USB\r\n] 2006.173.07:38:01.50#ibcon#*before write, iclass 38, count 0 2006.173.07:38:01.50#ibcon#enter sib2, iclass 38, count 0 2006.173.07:38:01.50#ibcon#flushed, iclass 38, count 0 2006.173.07:38:01.50#ibcon#about to write, iclass 38, count 0 2006.173.07:38:01.50#ibcon#wrote, iclass 38, count 0 2006.173.07:38:01.50#ibcon#about to read 3, iclass 38, count 0 2006.173.07:38:01.53#ibcon#read 3, iclass 38, count 0 2006.173.07:38:01.53#ibcon#about to read 4, iclass 38, count 0 2006.173.07:38:01.53#ibcon#read 4, iclass 38, count 0 2006.173.07:38:01.53#ibcon#about to read 5, iclass 38, count 0 2006.173.07:38:01.53#ibcon#read 5, iclass 38, count 0 2006.173.07:38:01.53#ibcon#about to read 6, iclass 38, count 0 2006.173.07:38:01.53#ibcon#read 6, iclass 38, count 0 2006.173.07:38:01.53#ibcon#end of sib2, iclass 38, count 0 2006.173.07:38:01.53#ibcon#*after write, iclass 38, count 0 2006.173.07:38:01.53#ibcon#*before return 0, iclass 38, count 0 2006.173.07:38:01.53#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.07:38:01.53#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.07:38:01.53#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.07:38:01.53#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.07:38:01.53$vck44/vblo=3,649.99 2006.173.07:38:01.53#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.07:38:01.53#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.07:38:01.53#ibcon#ireg 17 cls_cnt 0 2006.173.07:38:01.53#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.07:38:01.53#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.07:38:01.53#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.07:38:01.53#ibcon#enter wrdev, iclass 40, count 0 2006.173.07:38:01.53#ibcon#first serial, iclass 40, count 0 2006.173.07:38:01.53#ibcon#enter sib2, iclass 40, count 0 2006.173.07:38:01.53#ibcon#flushed, iclass 40, count 0 2006.173.07:38:01.53#ibcon#about to write, iclass 40, count 0 2006.173.07:38:01.53#ibcon#wrote, iclass 40, count 0 2006.173.07:38:01.53#ibcon#about to read 3, iclass 40, count 0 2006.173.07:38:01.55#ibcon#read 3, iclass 40, count 0 2006.173.07:38:01.55#ibcon#about to read 4, iclass 40, count 0 2006.173.07:38:01.55#ibcon#read 4, iclass 40, count 0 2006.173.07:38:01.55#ibcon#about to read 5, iclass 40, count 0 2006.173.07:38:01.55#ibcon#read 5, iclass 40, count 0 2006.173.07:38:01.55#ibcon#about to read 6, iclass 40, count 0 2006.173.07:38:01.55#ibcon#read 6, iclass 40, count 0 2006.173.07:38:01.55#ibcon#end of sib2, iclass 40, count 0 2006.173.07:38:01.55#ibcon#*mode == 0, iclass 40, count 0 2006.173.07:38:01.55#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.07:38:01.55#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.07:38:01.55#ibcon#*before write, iclass 40, count 0 2006.173.07:38:01.55#ibcon#enter sib2, iclass 40, count 0 2006.173.07:38:01.55#ibcon#flushed, iclass 40, count 0 2006.173.07:38:01.55#ibcon#about to write, iclass 40, count 0 2006.173.07:38:01.55#ibcon#wrote, iclass 40, count 0 2006.173.07:38:01.55#ibcon#about to read 3, iclass 40, count 0 2006.173.07:38:01.59#ibcon#read 3, iclass 40, count 0 2006.173.07:38:01.59#ibcon#about to read 4, iclass 40, count 0 2006.173.07:38:01.59#ibcon#read 4, iclass 40, count 0 2006.173.07:38:01.59#ibcon#about to read 5, iclass 40, count 0 2006.173.07:38:01.59#ibcon#read 5, iclass 40, count 0 2006.173.07:38:01.59#ibcon#about to read 6, iclass 40, count 0 2006.173.07:38:01.59#ibcon#read 6, iclass 40, count 0 2006.173.07:38:01.59#ibcon#end of sib2, iclass 40, count 0 2006.173.07:38:01.59#ibcon#*after write, iclass 40, count 0 2006.173.07:38:01.59#ibcon#*before return 0, iclass 40, count 0 2006.173.07:38:01.59#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.07:38:01.59#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.07:38:01.59#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.07:38:01.59#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.07:38:01.59$vck44/vb=3,4 2006.173.07:38:01.59#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.07:38:01.59#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.07:38:01.59#ibcon#ireg 11 cls_cnt 2 2006.173.07:38:01.59#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.07:38:01.65#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.07:38:01.65#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.07:38:01.65#ibcon#enter wrdev, iclass 4, count 2 2006.173.07:38:01.65#ibcon#first serial, iclass 4, count 2 2006.173.07:38:01.65#ibcon#enter sib2, iclass 4, count 2 2006.173.07:38:01.65#ibcon#flushed, iclass 4, count 2 2006.173.07:38:01.65#ibcon#about to write, iclass 4, count 2 2006.173.07:38:01.65#ibcon#wrote, iclass 4, count 2 2006.173.07:38:01.65#ibcon#about to read 3, iclass 4, count 2 2006.173.07:38:01.67#ibcon#read 3, iclass 4, count 2 2006.173.07:38:01.67#ibcon#about to read 4, iclass 4, count 2 2006.173.07:38:01.67#ibcon#read 4, iclass 4, count 2 2006.173.07:38:01.67#ibcon#about to read 5, iclass 4, count 2 2006.173.07:38:01.67#ibcon#read 5, iclass 4, count 2 2006.173.07:38:01.67#ibcon#about to read 6, iclass 4, count 2 2006.173.07:38:01.67#ibcon#read 6, iclass 4, count 2 2006.173.07:38:01.67#ibcon#end of sib2, iclass 4, count 2 2006.173.07:38:01.67#ibcon#*mode == 0, iclass 4, count 2 2006.173.07:38:01.67#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.07:38:01.67#ibcon#[27=AT03-04\r\n] 2006.173.07:38:01.67#ibcon#*before write, iclass 4, count 2 2006.173.07:38:01.67#ibcon#enter sib2, iclass 4, count 2 2006.173.07:38:01.67#ibcon#flushed, iclass 4, count 2 2006.173.07:38:01.67#ibcon#about to write, iclass 4, count 2 2006.173.07:38:01.67#ibcon#wrote, iclass 4, count 2 2006.173.07:38:01.67#ibcon#about to read 3, iclass 4, count 2 2006.173.07:38:01.70#ibcon#read 3, iclass 4, count 2 2006.173.07:38:01.70#ibcon#about to read 4, iclass 4, count 2 2006.173.07:38:01.70#ibcon#read 4, iclass 4, count 2 2006.173.07:38:01.70#ibcon#about to read 5, iclass 4, count 2 2006.173.07:38:01.70#ibcon#read 5, iclass 4, count 2 2006.173.07:38:01.70#ibcon#about to read 6, iclass 4, count 2 2006.173.07:38:01.70#ibcon#read 6, iclass 4, count 2 2006.173.07:38:01.70#ibcon#end of sib2, iclass 4, count 2 2006.173.07:38:01.70#ibcon#*after write, iclass 4, count 2 2006.173.07:38:01.70#ibcon#*before return 0, iclass 4, count 2 2006.173.07:38:01.70#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.07:38:01.70#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.07:38:01.70#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.07:38:01.70#ibcon#ireg 7 cls_cnt 0 2006.173.07:38:01.70#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.07:38:01.82#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.07:38:01.82#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.07:38:01.82#ibcon#enter wrdev, iclass 4, count 0 2006.173.07:38:01.82#ibcon#first serial, iclass 4, count 0 2006.173.07:38:01.82#ibcon#enter sib2, iclass 4, count 0 2006.173.07:38:01.82#ibcon#flushed, iclass 4, count 0 2006.173.07:38:01.82#ibcon#about to write, iclass 4, count 0 2006.173.07:38:01.82#ibcon#wrote, iclass 4, count 0 2006.173.07:38:01.82#ibcon#about to read 3, iclass 4, count 0 2006.173.07:38:01.84#ibcon#read 3, iclass 4, count 0 2006.173.07:38:01.84#ibcon#about to read 4, iclass 4, count 0 2006.173.07:38:01.84#ibcon#read 4, iclass 4, count 0 2006.173.07:38:01.84#ibcon#about to read 5, iclass 4, count 0 2006.173.07:38:01.84#ibcon#read 5, iclass 4, count 0 2006.173.07:38:01.84#ibcon#about to read 6, iclass 4, count 0 2006.173.07:38:01.84#ibcon#read 6, iclass 4, count 0 2006.173.07:38:01.84#ibcon#end of sib2, iclass 4, count 0 2006.173.07:38:01.84#ibcon#*mode == 0, iclass 4, count 0 2006.173.07:38:01.84#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.07:38:01.84#ibcon#[27=USB\r\n] 2006.173.07:38:01.84#ibcon#*before write, iclass 4, count 0 2006.173.07:38:01.84#ibcon#enter sib2, iclass 4, count 0 2006.173.07:38:01.84#ibcon#flushed, iclass 4, count 0 2006.173.07:38:01.84#ibcon#about to write, iclass 4, count 0 2006.173.07:38:01.84#ibcon#wrote, iclass 4, count 0 2006.173.07:38:01.84#ibcon#about to read 3, iclass 4, count 0 2006.173.07:38:01.87#ibcon#read 3, iclass 4, count 0 2006.173.07:38:01.87#ibcon#about to read 4, iclass 4, count 0 2006.173.07:38:01.87#ibcon#read 4, iclass 4, count 0 2006.173.07:38:01.87#ibcon#about to read 5, iclass 4, count 0 2006.173.07:38:01.87#ibcon#read 5, iclass 4, count 0 2006.173.07:38:01.87#ibcon#about to read 6, iclass 4, count 0 2006.173.07:38:01.87#ibcon#read 6, iclass 4, count 0 2006.173.07:38:01.87#ibcon#end of sib2, iclass 4, count 0 2006.173.07:38:01.87#ibcon#*after write, iclass 4, count 0 2006.173.07:38:01.87#ibcon#*before return 0, iclass 4, count 0 2006.173.07:38:01.87#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.07:38:01.87#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.07:38:01.87#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.07:38:01.87#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.07:38:01.87$vck44/vblo=4,679.99 2006.173.07:38:01.87#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.07:38:01.87#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.07:38:01.87#ibcon#ireg 17 cls_cnt 0 2006.173.07:38:01.87#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.07:38:01.87#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.07:38:01.87#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.07:38:01.87#ibcon#enter wrdev, iclass 6, count 0 2006.173.07:38:01.87#ibcon#first serial, iclass 6, count 0 2006.173.07:38:01.87#ibcon#enter sib2, iclass 6, count 0 2006.173.07:38:01.87#ibcon#flushed, iclass 6, count 0 2006.173.07:38:01.87#ibcon#about to write, iclass 6, count 0 2006.173.07:38:01.87#ibcon#wrote, iclass 6, count 0 2006.173.07:38:01.87#ibcon#about to read 3, iclass 6, count 0 2006.173.07:38:01.89#ibcon#read 3, iclass 6, count 0 2006.173.07:38:01.89#ibcon#about to read 4, iclass 6, count 0 2006.173.07:38:01.89#ibcon#read 4, iclass 6, count 0 2006.173.07:38:01.89#ibcon#about to read 5, iclass 6, count 0 2006.173.07:38:01.89#ibcon#read 5, iclass 6, count 0 2006.173.07:38:01.89#ibcon#about to read 6, iclass 6, count 0 2006.173.07:38:01.89#ibcon#read 6, iclass 6, count 0 2006.173.07:38:01.89#ibcon#end of sib2, iclass 6, count 0 2006.173.07:38:01.89#ibcon#*mode == 0, iclass 6, count 0 2006.173.07:38:01.89#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.07:38:01.89#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.07:38:01.89#ibcon#*before write, iclass 6, count 0 2006.173.07:38:01.89#ibcon#enter sib2, iclass 6, count 0 2006.173.07:38:01.89#ibcon#flushed, iclass 6, count 0 2006.173.07:38:01.89#ibcon#about to write, iclass 6, count 0 2006.173.07:38:01.89#ibcon#wrote, iclass 6, count 0 2006.173.07:38:01.89#ibcon#about to read 3, iclass 6, count 0 2006.173.07:38:01.93#ibcon#read 3, iclass 6, count 0 2006.173.07:38:01.93#ibcon#about to read 4, iclass 6, count 0 2006.173.07:38:01.93#ibcon#read 4, iclass 6, count 0 2006.173.07:38:01.93#ibcon#about to read 5, iclass 6, count 0 2006.173.07:38:01.93#ibcon#read 5, iclass 6, count 0 2006.173.07:38:01.93#ibcon#about to read 6, iclass 6, count 0 2006.173.07:38:01.93#ibcon#read 6, iclass 6, count 0 2006.173.07:38:01.93#ibcon#end of sib2, iclass 6, count 0 2006.173.07:38:01.93#ibcon#*after write, iclass 6, count 0 2006.173.07:38:01.93#ibcon#*before return 0, iclass 6, count 0 2006.173.07:38:01.93#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.07:38:01.93#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.07:38:01.93#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.07:38:01.93#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.07:38:01.93$vck44/vb=4,4 2006.173.07:38:01.93#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.07:38:01.93#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.07:38:01.93#ibcon#ireg 11 cls_cnt 2 2006.173.07:38:01.93#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.07:38:01.99#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.07:38:01.99#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.07:38:01.99#ibcon#enter wrdev, iclass 10, count 2 2006.173.07:38:01.99#ibcon#first serial, iclass 10, count 2 2006.173.07:38:01.99#ibcon#enter sib2, iclass 10, count 2 2006.173.07:38:01.99#ibcon#flushed, iclass 10, count 2 2006.173.07:38:01.99#ibcon#about to write, iclass 10, count 2 2006.173.07:38:01.99#ibcon#wrote, iclass 10, count 2 2006.173.07:38:01.99#ibcon#about to read 3, iclass 10, count 2 2006.173.07:38:02.01#ibcon#read 3, iclass 10, count 2 2006.173.07:38:02.01#ibcon#about to read 4, iclass 10, count 2 2006.173.07:38:02.01#ibcon#read 4, iclass 10, count 2 2006.173.07:38:02.01#ibcon#about to read 5, iclass 10, count 2 2006.173.07:38:02.01#ibcon#read 5, iclass 10, count 2 2006.173.07:38:02.01#ibcon#about to read 6, iclass 10, count 2 2006.173.07:38:02.01#ibcon#read 6, iclass 10, count 2 2006.173.07:38:02.01#ibcon#end of sib2, iclass 10, count 2 2006.173.07:38:02.01#ibcon#*mode == 0, iclass 10, count 2 2006.173.07:38:02.01#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.07:38:02.01#ibcon#[27=AT04-04\r\n] 2006.173.07:38:02.01#ibcon#*before write, iclass 10, count 2 2006.173.07:38:02.01#ibcon#enter sib2, iclass 10, count 2 2006.173.07:38:02.01#ibcon#flushed, iclass 10, count 2 2006.173.07:38:02.01#ibcon#about to write, iclass 10, count 2 2006.173.07:38:02.01#ibcon#wrote, iclass 10, count 2 2006.173.07:38:02.01#ibcon#about to read 3, iclass 10, count 2 2006.173.07:38:02.04#ibcon#read 3, iclass 10, count 2 2006.173.07:38:02.04#ibcon#about to read 4, iclass 10, count 2 2006.173.07:38:02.04#ibcon#read 4, iclass 10, count 2 2006.173.07:38:02.04#ibcon#about to read 5, iclass 10, count 2 2006.173.07:38:02.04#ibcon#read 5, iclass 10, count 2 2006.173.07:38:02.04#ibcon#about to read 6, iclass 10, count 2 2006.173.07:38:02.04#ibcon#read 6, iclass 10, count 2 2006.173.07:38:02.04#ibcon#end of sib2, iclass 10, count 2 2006.173.07:38:02.04#ibcon#*after write, iclass 10, count 2 2006.173.07:38:02.04#ibcon#*before return 0, iclass 10, count 2 2006.173.07:38:02.04#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.07:38:02.04#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.07:38:02.04#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.07:38:02.04#ibcon#ireg 7 cls_cnt 0 2006.173.07:38:02.04#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.07:38:02.16#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.07:38:02.16#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.07:38:02.16#ibcon#enter wrdev, iclass 10, count 0 2006.173.07:38:02.16#ibcon#first serial, iclass 10, count 0 2006.173.07:38:02.16#ibcon#enter sib2, iclass 10, count 0 2006.173.07:38:02.16#ibcon#flushed, iclass 10, count 0 2006.173.07:38:02.16#ibcon#about to write, iclass 10, count 0 2006.173.07:38:02.16#ibcon#wrote, iclass 10, count 0 2006.173.07:38:02.16#ibcon#about to read 3, iclass 10, count 0 2006.173.07:38:02.18#ibcon#read 3, iclass 10, count 0 2006.173.07:38:02.18#ibcon#about to read 4, iclass 10, count 0 2006.173.07:38:02.18#ibcon#read 4, iclass 10, count 0 2006.173.07:38:02.18#ibcon#about to read 5, iclass 10, count 0 2006.173.07:38:02.18#ibcon#read 5, iclass 10, count 0 2006.173.07:38:02.18#ibcon#about to read 6, iclass 10, count 0 2006.173.07:38:02.18#ibcon#read 6, iclass 10, count 0 2006.173.07:38:02.18#ibcon#end of sib2, iclass 10, count 0 2006.173.07:38:02.18#ibcon#*mode == 0, iclass 10, count 0 2006.173.07:38:02.18#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.07:38:02.18#ibcon#[27=USB\r\n] 2006.173.07:38:02.18#ibcon#*before write, iclass 10, count 0 2006.173.07:38:02.18#ibcon#enter sib2, iclass 10, count 0 2006.173.07:38:02.18#ibcon#flushed, iclass 10, count 0 2006.173.07:38:02.18#ibcon#about to write, iclass 10, count 0 2006.173.07:38:02.18#ibcon#wrote, iclass 10, count 0 2006.173.07:38:02.18#ibcon#about to read 3, iclass 10, count 0 2006.173.07:38:02.21#ibcon#read 3, iclass 10, count 0 2006.173.07:38:02.21#ibcon#about to read 4, iclass 10, count 0 2006.173.07:38:02.21#ibcon#read 4, iclass 10, count 0 2006.173.07:38:02.21#ibcon#about to read 5, iclass 10, count 0 2006.173.07:38:02.21#ibcon#read 5, iclass 10, count 0 2006.173.07:38:02.21#ibcon#about to read 6, iclass 10, count 0 2006.173.07:38:02.21#ibcon#read 6, iclass 10, count 0 2006.173.07:38:02.21#ibcon#end of sib2, iclass 10, count 0 2006.173.07:38:02.21#ibcon#*after write, iclass 10, count 0 2006.173.07:38:02.21#ibcon#*before return 0, iclass 10, count 0 2006.173.07:38:02.21#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.07:38:02.21#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.07:38:02.21#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.07:38:02.21#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.07:38:02.21$vck44/vblo=5,709.99 2006.173.07:38:02.21#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.07:38:02.21#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.07:38:02.21#ibcon#ireg 17 cls_cnt 0 2006.173.07:38:02.21#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.07:38:02.21#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.07:38:02.21#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.07:38:02.21#ibcon#enter wrdev, iclass 12, count 0 2006.173.07:38:02.21#ibcon#first serial, iclass 12, count 0 2006.173.07:38:02.21#ibcon#enter sib2, iclass 12, count 0 2006.173.07:38:02.21#ibcon#flushed, iclass 12, count 0 2006.173.07:38:02.21#ibcon#about to write, iclass 12, count 0 2006.173.07:38:02.21#ibcon#wrote, iclass 12, count 0 2006.173.07:38:02.21#ibcon#about to read 3, iclass 12, count 0 2006.173.07:38:02.23#ibcon#read 3, iclass 12, count 0 2006.173.07:38:02.23#ibcon#about to read 4, iclass 12, count 0 2006.173.07:38:02.23#ibcon#read 4, iclass 12, count 0 2006.173.07:38:02.23#ibcon#about to read 5, iclass 12, count 0 2006.173.07:38:02.23#ibcon#read 5, iclass 12, count 0 2006.173.07:38:02.23#ibcon#about to read 6, iclass 12, count 0 2006.173.07:38:02.23#ibcon#read 6, iclass 12, count 0 2006.173.07:38:02.23#ibcon#end of sib2, iclass 12, count 0 2006.173.07:38:02.23#ibcon#*mode == 0, iclass 12, count 0 2006.173.07:38:02.23#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.07:38:02.23#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.07:38:02.23#ibcon#*before write, iclass 12, count 0 2006.173.07:38:02.23#ibcon#enter sib2, iclass 12, count 0 2006.173.07:38:02.23#ibcon#flushed, iclass 12, count 0 2006.173.07:38:02.23#ibcon#about to write, iclass 12, count 0 2006.173.07:38:02.23#ibcon#wrote, iclass 12, count 0 2006.173.07:38:02.23#ibcon#about to read 3, iclass 12, count 0 2006.173.07:38:02.27#ibcon#read 3, iclass 12, count 0 2006.173.07:38:02.27#ibcon#about to read 4, iclass 12, count 0 2006.173.07:38:02.27#ibcon#read 4, iclass 12, count 0 2006.173.07:38:02.27#ibcon#about to read 5, iclass 12, count 0 2006.173.07:38:02.27#ibcon#read 5, iclass 12, count 0 2006.173.07:38:02.27#ibcon#about to read 6, iclass 12, count 0 2006.173.07:38:02.27#ibcon#read 6, iclass 12, count 0 2006.173.07:38:02.27#ibcon#end of sib2, iclass 12, count 0 2006.173.07:38:02.27#ibcon#*after write, iclass 12, count 0 2006.173.07:38:02.27#ibcon#*before return 0, iclass 12, count 0 2006.173.07:38:02.27#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.07:38:02.27#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.07:38:02.27#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.07:38:02.27#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.07:38:02.27$vck44/vb=5,4 2006.173.07:38:02.27#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.07:38:02.27#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.07:38:02.27#ibcon#ireg 11 cls_cnt 2 2006.173.07:38:02.27#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.07:38:02.33#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.07:38:02.33#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.07:38:02.33#ibcon#enter wrdev, iclass 14, count 2 2006.173.07:38:02.33#ibcon#first serial, iclass 14, count 2 2006.173.07:38:02.33#ibcon#enter sib2, iclass 14, count 2 2006.173.07:38:02.33#ibcon#flushed, iclass 14, count 2 2006.173.07:38:02.33#ibcon#about to write, iclass 14, count 2 2006.173.07:38:02.33#ibcon#wrote, iclass 14, count 2 2006.173.07:38:02.33#ibcon#about to read 3, iclass 14, count 2 2006.173.07:38:02.35#ibcon#read 3, iclass 14, count 2 2006.173.07:38:02.35#ibcon#about to read 4, iclass 14, count 2 2006.173.07:38:02.35#ibcon#read 4, iclass 14, count 2 2006.173.07:38:02.35#ibcon#about to read 5, iclass 14, count 2 2006.173.07:38:02.35#ibcon#read 5, iclass 14, count 2 2006.173.07:38:02.35#ibcon#about to read 6, iclass 14, count 2 2006.173.07:38:02.35#ibcon#read 6, iclass 14, count 2 2006.173.07:38:02.35#ibcon#end of sib2, iclass 14, count 2 2006.173.07:38:02.35#ibcon#*mode == 0, iclass 14, count 2 2006.173.07:38:02.35#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.07:38:02.35#ibcon#[27=AT05-04\r\n] 2006.173.07:38:02.35#ibcon#*before write, iclass 14, count 2 2006.173.07:38:02.35#ibcon#enter sib2, iclass 14, count 2 2006.173.07:38:02.35#ibcon#flushed, iclass 14, count 2 2006.173.07:38:02.35#ibcon#about to write, iclass 14, count 2 2006.173.07:38:02.35#ibcon#wrote, iclass 14, count 2 2006.173.07:38:02.35#ibcon#about to read 3, iclass 14, count 2 2006.173.07:38:02.38#ibcon#read 3, iclass 14, count 2 2006.173.07:38:02.38#ibcon#about to read 4, iclass 14, count 2 2006.173.07:38:02.38#ibcon#read 4, iclass 14, count 2 2006.173.07:38:02.38#ibcon#about to read 5, iclass 14, count 2 2006.173.07:38:02.38#ibcon#read 5, iclass 14, count 2 2006.173.07:38:02.38#ibcon#about to read 6, iclass 14, count 2 2006.173.07:38:02.38#ibcon#read 6, iclass 14, count 2 2006.173.07:38:02.38#ibcon#end of sib2, iclass 14, count 2 2006.173.07:38:02.38#ibcon#*after write, iclass 14, count 2 2006.173.07:38:02.38#ibcon#*before return 0, iclass 14, count 2 2006.173.07:38:02.38#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.07:38:02.38#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.07:38:02.38#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.07:38:02.38#ibcon#ireg 7 cls_cnt 0 2006.173.07:38:02.38#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.07:38:02.50#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.07:38:02.50#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.07:38:02.50#ibcon#enter wrdev, iclass 14, count 0 2006.173.07:38:02.50#ibcon#first serial, iclass 14, count 0 2006.173.07:38:02.50#ibcon#enter sib2, iclass 14, count 0 2006.173.07:38:02.50#ibcon#flushed, iclass 14, count 0 2006.173.07:38:02.50#ibcon#about to write, iclass 14, count 0 2006.173.07:38:02.50#ibcon#wrote, iclass 14, count 0 2006.173.07:38:02.50#ibcon#about to read 3, iclass 14, count 0 2006.173.07:38:02.52#ibcon#read 3, iclass 14, count 0 2006.173.07:38:02.52#ibcon#about to read 4, iclass 14, count 0 2006.173.07:38:02.52#ibcon#read 4, iclass 14, count 0 2006.173.07:38:02.52#ibcon#about to read 5, iclass 14, count 0 2006.173.07:38:02.52#ibcon#read 5, iclass 14, count 0 2006.173.07:38:02.52#ibcon#about to read 6, iclass 14, count 0 2006.173.07:38:02.52#ibcon#read 6, iclass 14, count 0 2006.173.07:38:02.52#ibcon#end of sib2, iclass 14, count 0 2006.173.07:38:02.52#ibcon#*mode == 0, iclass 14, count 0 2006.173.07:38:02.52#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.07:38:02.52#ibcon#[27=USB\r\n] 2006.173.07:38:02.52#ibcon#*before write, iclass 14, count 0 2006.173.07:38:02.52#ibcon#enter sib2, iclass 14, count 0 2006.173.07:38:02.52#ibcon#flushed, iclass 14, count 0 2006.173.07:38:02.52#ibcon#about to write, iclass 14, count 0 2006.173.07:38:02.52#ibcon#wrote, iclass 14, count 0 2006.173.07:38:02.52#ibcon#about to read 3, iclass 14, count 0 2006.173.07:38:02.55#ibcon#read 3, iclass 14, count 0 2006.173.07:38:02.55#ibcon#about to read 4, iclass 14, count 0 2006.173.07:38:02.55#ibcon#read 4, iclass 14, count 0 2006.173.07:38:02.55#ibcon#about to read 5, iclass 14, count 0 2006.173.07:38:02.55#ibcon#read 5, iclass 14, count 0 2006.173.07:38:02.55#ibcon#about to read 6, iclass 14, count 0 2006.173.07:38:02.55#ibcon#read 6, iclass 14, count 0 2006.173.07:38:02.55#ibcon#end of sib2, iclass 14, count 0 2006.173.07:38:02.55#ibcon#*after write, iclass 14, count 0 2006.173.07:38:02.55#ibcon#*before return 0, iclass 14, count 0 2006.173.07:38:02.55#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.07:38:02.55#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.07:38:02.55#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.07:38:02.55#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.07:38:02.55$vck44/vblo=6,719.99 2006.173.07:38:02.55#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.07:38:02.55#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.07:38:02.55#ibcon#ireg 17 cls_cnt 0 2006.173.07:38:02.55#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.07:38:02.55#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.07:38:02.55#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.07:38:02.55#ibcon#enter wrdev, iclass 16, count 0 2006.173.07:38:02.55#ibcon#first serial, iclass 16, count 0 2006.173.07:38:02.55#ibcon#enter sib2, iclass 16, count 0 2006.173.07:38:02.55#ibcon#flushed, iclass 16, count 0 2006.173.07:38:02.55#ibcon#about to write, iclass 16, count 0 2006.173.07:38:02.55#ibcon#wrote, iclass 16, count 0 2006.173.07:38:02.55#ibcon#about to read 3, iclass 16, count 0 2006.173.07:38:02.57#ibcon#read 3, iclass 16, count 0 2006.173.07:38:02.57#ibcon#about to read 4, iclass 16, count 0 2006.173.07:38:02.57#ibcon#read 4, iclass 16, count 0 2006.173.07:38:02.57#ibcon#about to read 5, iclass 16, count 0 2006.173.07:38:02.57#ibcon#read 5, iclass 16, count 0 2006.173.07:38:02.57#ibcon#about to read 6, iclass 16, count 0 2006.173.07:38:02.57#ibcon#read 6, iclass 16, count 0 2006.173.07:38:02.57#ibcon#end of sib2, iclass 16, count 0 2006.173.07:38:02.57#ibcon#*mode == 0, iclass 16, count 0 2006.173.07:38:02.57#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.07:38:02.57#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.07:38:02.57#ibcon#*before write, iclass 16, count 0 2006.173.07:38:02.57#ibcon#enter sib2, iclass 16, count 0 2006.173.07:38:02.57#ibcon#flushed, iclass 16, count 0 2006.173.07:38:02.57#ibcon#about to write, iclass 16, count 0 2006.173.07:38:02.57#ibcon#wrote, iclass 16, count 0 2006.173.07:38:02.57#ibcon#about to read 3, iclass 16, count 0 2006.173.07:38:02.61#ibcon#read 3, iclass 16, count 0 2006.173.07:38:02.61#ibcon#about to read 4, iclass 16, count 0 2006.173.07:38:02.61#ibcon#read 4, iclass 16, count 0 2006.173.07:38:02.61#ibcon#about to read 5, iclass 16, count 0 2006.173.07:38:02.61#ibcon#read 5, iclass 16, count 0 2006.173.07:38:02.61#ibcon#about to read 6, iclass 16, count 0 2006.173.07:38:02.61#ibcon#read 6, iclass 16, count 0 2006.173.07:38:02.61#ibcon#end of sib2, iclass 16, count 0 2006.173.07:38:02.61#ibcon#*after write, iclass 16, count 0 2006.173.07:38:02.61#ibcon#*before return 0, iclass 16, count 0 2006.173.07:38:02.61#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.07:38:02.61#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.07:38:02.61#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.07:38:02.61#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.07:38:02.61$vck44/vb=6,4 2006.173.07:38:02.61#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.07:38:02.61#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.07:38:02.61#ibcon#ireg 11 cls_cnt 2 2006.173.07:38:02.61#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.07:38:02.67#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.07:38:02.67#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.07:38:02.67#ibcon#enter wrdev, iclass 18, count 2 2006.173.07:38:02.67#ibcon#first serial, iclass 18, count 2 2006.173.07:38:02.67#ibcon#enter sib2, iclass 18, count 2 2006.173.07:38:02.67#ibcon#flushed, iclass 18, count 2 2006.173.07:38:02.67#ibcon#about to write, iclass 18, count 2 2006.173.07:38:02.67#ibcon#wrote, iclass 18, count 2 2006.173.07:38:02.67#ibcon#about to read 3, iclass 18, count 2 2006.173.07:38:02.69#ibcon#read 3, iclass 18, count 2 2006.173.07:38:02.69#ibcon#about to read 4, iclass 18, count 2 2006.173.07:38:02.69#ibcon#read 4, iclass 18, count 2 2006.173.07:38:02.69#ibcon#about to read 5, iclass 18, count 2 2006.173.07:38:02.69#ibcon#read 5, iclass 18, count 2 2006.173.07:38:02.69#ibcon#about to read 6, iclass 18, count 2 2006.173.07:38:02.69#ibcon#read 6, iclass 18, count 2 2006.173.07:38:02.69#ibcon#end of sib2, iclass 18, count 2 2006.173.07:38:02.69#ibcon#*mode == 0, iclass 18, count 2 2006.173.07:38:02.69#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.07:38:02.69#ibcon#[27=AT06-04\r\n] 2006.173.07:38:02.69#ibcon#*before write, iclass 18, count 2 2006.173.07:38:02.69#ibcon#enter sib2, iclass 18, count 2 2006.173.07:38:02.69#ibcon#flushed, iclass 18, count 2 2006.173.07:38:02.69#ibcon#about to write, iclass 18, count 2 2006.173.07:38:02.69#ibcon#wrote, iclass 18, count 2 2006.173.07:38:02.69#ibcon#about to read 3, iclass 18, count 2 2006.173.07:38:02.72#ibcon#read 3, iclass 18, count 2 2006.173.07:38:02.72#ibcon#about to read 4, iclass 18, count 2 2006.173.07:38:02.72#ibcon#read 4, iclass 18, count 2 2006.173.07:38:02.72#ibcon#about to read 5, iclass 18, count 2 2006.173.07:38:02.72#ibcon#read 5, iclass 18, count 2 2006.173.07:38:02.72#ibcon#about to read 6, iclass 18, count 2 2006.173.07:38:02.72#ibcon#read 6, iclass 18, count 2 2006.173.07:38:02.72#ibcon#end of sib2, iclass 18, count 2 2006.173.07:38:02.72#ibcon#*after write, iclass 18, count 2 2006.173.07:38:02.72#ibcon#*before return 0, iclass 18, count 2 2006.173.07:38:02.72#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.07:38:02.72#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.07:38:02.72#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.07:38:02.72#ibcon#ireg 7 cls_cnt 0 2006.173.07:38:02.72#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.07:38:02.84#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.07:38:02.84#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.07:38:02.84#ibcon#enter wrdev, iclass 18, count 0 2006.173.07:38:02.84#ibcon#first serial, iclass 18, count 0 2006.173.07:38:02.84#ibcon#enter sib2, iclass 18, count 0 2006.173.07:38:02.84#ibcon#flushed, iclass 18, count 0 2006.173.07:38:02.84#ibcon#about to write, iclass 18, count 0 2006.173.07:38:02.84#ibcon#wrote, iclass 18, count 0 2006.173.07:38:02.84#ibcon#about to read 3, iclass 18, count 0 2006.173.07:38:02.86#ibcon#read 3, iclass 18, count 0 2006.173.07:38:02.86#ibcon#about to read 4, iclass 18, count 0 2006.173.07:38:02.86#ibcon#read 4, iclass 18, count 0 2006.173.07:38:02.86#ibcon#about to read 5, iclass 18, count 0 2006.173.07:38:02.86#ibcon#read 5, iclass 18, count 0 2006.173.07:38:02.86#ibcon#about to read 6, iclass 18, count 0 2006.173.07:38:02.86#ibcon#read 6, iclass 18, count 0 2006.173.07:38:02.86#ibcon#end of sib2, iclass 18, count 0 2006.173.07:38:02.86#ibcon#*mode == 0, iclass 18, count 0 2006.173.07:38:02.86#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.07:38:02.86#ibcon#[27=USB\r\n] 2006.173.07:38:02.86#ibcon#*before write, iclass 18, count 0 2006.173.07:38:02.86#ibcon#enter sib2, iclass 18, count 0 2006.173.07:38:02.86#ibcon#flushed, iclass 18, count 0 2006.173.07:38:02.86#ibcon#about to write, iclass 18, count 0 2006.173.07:38:02.86#ibcon#wrote, iclass 18, count 0 2006.173.07:38:02.86#ibcon#about to read 3, iclass 18, count 0 2006.173.07:38:02.89#ibcon#read 3, iclass 18, count 0 2006.173.07:38:02.89#ibcon#about to read 4, iclass 18, count 0 2006.173.07:38:02.89#ibcon#read 4, iclass 18, count 0 2006.173.07:38:02.89#ibcon#about to read 5, iclass 18, count 0 2006.173.07:38:02.89#ibcon#read 5, iclass 18, count 0 2006.173.07:38:02.89#ibcon#about to read 6, iclass 18, count 0 2006.173.07:38:02.89#ibcon#read 6, iclass 18, count 0 2006.173.07:38:02.89#ibcon#end of sib2, iclass 18, count 0 2006.173.07:38:02.89#ibcon#*after write, iclass 18, count 0 2006.173.07:38:02.89#ibcon#*before return 0, iclass 18, count 0 2006.173.07:38:02.89#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.07:38:02.89#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.07:38:02.89#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.07:38:02.89#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.07:38:02.89$vck44/vblo=7,734.99 2006.173.07:38:02.89#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.07:38:02.89#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.07:38:02.89#ibcon#ireg 17 cls_cnt 0 2006.173.07:38:02.89#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.07:38:02.89#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.07:38:02.89#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.07:38:02.89#ibcon#enter wrdev, iclass 20, count 0 2006.173.07:38:02.89#ibcon#first serial, iclass 20, count 0 2006.173.07:38:02.89#ibcon#enter sib2, iclass 20, count 0 2006.173.07:38:02.89#ibcon#flushed, iclass 20, count 0 2006.173.07:38:02.89#ibcon#about to write, iclass 20, count 0 2006.173.07:38:02.89#ibcon#wrote, iclass 20, count 0 2006.173.07:38:02.89#ibcon#about to read 3, iclass 20, count 0 2006.173.07:38:02.91#ibcon#read 3, iclass 20, count 0 2006.173.07:38:02.91#ibcon#about to read 4, iclass 20, count 0 2006.173.07:38:02.91#ibcon#read 4, iclass 20, count 0 2006.173.07:38:02.91#ibcon#about to read 5, iclass 20, count 0 2006.173.07:38:02.91#ibcon#read 5, iclass 20, count 0 2006.173.07:38:02.91#ibcon#about to read 6, iclass 20, count 0 2006.173.07:38:02.91#ibcon#read 6, iclass 20, count 0 2006.173.07:38:02.91#ibcon#end of sib2, iclass 20, count 0 2006.173.07:38:02.91#ibcon#*mode == 0, iclass 20, count 0 2006.173.07:38:02.91#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.07:38:02.91#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.07:38:02.91#ibcon#*before write, iclass 20, count 0 2006.173.07:38:02.91#ibcon#enter sib2, iclass 20, count 0 2006.173.07:38:02.91#ibcon#flushed, iclass 20, count 0 2006.173.07:38:02.91#ibcon#about to write, iclass 20, count 0 2006.173.07:38:02.91#ibcon#wrote, iclass 20, count 0 2006.173.07:38:02.91#ibcon#about to read 3, iclass 20, count 0 2006.173.07:38:02.95#ibcon#read 3, iclass 20, count 0 2006.173.07:38:02.95#ibcon#about to read 4, iclass 20, count 0 2006.173.07:38:02.95#ibcon#read 4, iclass 20, count 0 2006.173.07:38:02.95#ibcon#about to read 5, iclass 20, count 0 2006.173.07:38:02.95#ibcon#read 5, iclass 20, count 0 2006.173.07:38:02.95#ibcon#about to read 6, iclass 20, count 0 2006.173.07:38:02.95#ibcon#read 6, iclass 20, count 0 2006.173.07:38:02.95#ibcon#end of sib2, iclass 20, count 0 2006.173.07:38:02.95#ibcon#*after write, iclass 20, count 0 2006.173.07:38:02.95#ibcon#*before return 0, iclass 20, count 0 2006.173.07:38:02.95#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.07:38:02.95#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.07:38:02.95#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.07:38:02.95#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.07:38:02.95$vck44/vb=7,4 2006.173.07:38:02.95#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.07:38:02.95#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.07:38:02.95#ibcon#ireg 11 cls_cnt 2 2006.173.07:38:02.95#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.07:38:03.01#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.07:38:03.01#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.07:38:03.01#ibcon#enter wrdev, iclass 22, count 2 2006.173.07:38:03.01#ibcon#first serial, iclass 22, count 2 2006.173.07:38:03.01#ibcon#enter sib2, iclass 22, count 2 2006.173.07:38:03.01#ibcon#flushed, iclass 22, count 2 2006.173.07:38:03.01#ibcon#about to write, iclass 22, count 2 2006.173.07:38:03.01#ibcon#wrote, iclass 22, count 2 2006.173.07:38:03.01#ibcon#about to read 3, iclass 22, count 2 2006.173.07:38:03.03#ibcon#read 3, iclass 22, count 2 2006.173.07:38:03.03#ibcon#about to read 4, iclass 22, count 2 2006.173.07:38:03.03#ibcon#read 4, iclass 22, count 2 2006.173.07:38:03.03#ibcon#about to read 5, iclass 22, count 2 2006.173.07:38:03.03#ibcon#read 5, iclass 22, count 2 2006.173.07:38:03.03#ibcon#about to read 6, iclass 22, count 2 2006.173.07:38:03.03#ibcon#read 6, iclass 22, count 2 2006.173.07:38:03.03#ibcon#end of sib2, iclass 22, count 2 2006.173.07:38:03.03#ibcon#*mode == 0, iclass 22, count 2 2006.173.07:38:03.03#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.07:38:03.03#ibcon#[27=AT07-04\r\n] 2006.173.07:38:03.03#ibcon#*before write, iclass 22, count 2 2006.173.07:38:03.03#ibcon#enter sib2, iclass 22, count 2 2006.173.07:38:03.03#ibcon#flushed, iclass 22, count 2 2006.173.07:38:03.03#ibcon#about to write, iclass 22, count 2 2006.173.07:38:03.03#ibcon#wrote, iclass 22, count 2 2006.173.07:38:03.03#ibcon#about to read 3, iclass 22, count 2 2006.173.07:38:03.06#ibcon#read 3, iclass 22, count 2 2006.173.07:38:03.06#ibcon#about to read 4, iclass 22, count 2 2006.173.07:38:03.06#ibcon#read 4, iclass 22, count 2 2006.173.07:38:03.06#ibcon#about to read 5, iclass 22, count 2 2006.173.07:38:03.06#ibcon#read 5, iclass 22, count 2 2006.173.07:38:03.06#ibcon#about to read 6, iclass 22, count 2 2006.173.07:38:03.06#ibcon#read 6, iclass 22, count 2 2006.173.07:38:03.06#ibcon#end of sib2, iclass 22, count 2 2006.173.07:38:03.06#ibcon#*after write, iclass 22, count 2 2006.173.07:38:03.06#ibcon#*before return 0, iclass 22, count 2 2006.173.07:38:03.06#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.07:38:03.06#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.07:38:03.06#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.07:38:03.06#ibcon#ireg 7 cls_cnt 0 2006.173.07:38:03.06#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.07:38:03.18#abcon#<5=/16 0.4 0.9 23.74 841004.4\r\n> 2006.173.07:38:03.18#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.07:38:03.18#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.07:38:03.18#ibcon#enter wrdev, iclass 22, count 0 2006.173.07:38:03.18#ibcon#first serial, iclass 22, count 0 2006.173.07:38:03.18#ibcon#enter sib2, iclass 22, count 0 2006.173.07:38:03.18#ibcon#flushed, iclass 22, count 0 2006.173.07:38:03.18#ibcon#about to write, iclass 22, count 0 2006.173.07:38:03.18#ibcon#wrote, iclass 22, count 0 2006.173.07:38:03.18#ibcon#about to read 3, iclass 22, count 0 2006.173.07:38:03.20#ibcon#read 3, iclass 22, count 0 2006.173.07:38:03.20#ibcon#about to read 4, iclass 22, count 0 2006.173.07:38:03.20#ibcon#read 4, iclass 22, count 0 2006.173.07:38:03.20#ibcon#about to read 5, iclass 22, count 0 2006.173.07:38:03.20#ibcon#read 5, iclass 22, count 0 2006.173.07:38:03.20#ibcon#about to read 6, iclass 22, count 0 2006.173.07:38:03.20#ibcon#read 6, iclass 22, count 0 2006.173.07:38:03.20#ibcon#end of sib2, iclass 22, count 0 2006.173.07:38:03.20#ibcon#*mode == 0, iclass 22, count 0 2006.173.07:38:03.20#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.07:38:03.20#ibcon#[27=USB\r\n] 2006.173.07:38:03.20#ibcon#*before write, iclass 22, count 0 2006.173.07:38:03.20#ibcon#enter sib2, iclass 22, count 0 2006.173.07:38:03.20#ibcon#flushed, iclass 22, count 0 2006.173.07:38:03.20#ibcon#about to write, iclass 22, count 0 2006.173.07:38:03.20#ibcon#wrote, iclass 22, count 0 2006.173.07:38:03.20#ibcon#about to read 3, iclass 22, count 0 2006.173.07:38:03.20#abcon#{5=INTERFACE CLEAR} 2006.173.07:38:03.23#ibcon#read 3, iclass 22, count 0 2006.173.07:38:03.23#ibcon#about to read 4, iclass 22, count 0 2006.173.07:38:03.23#ibcon#read 4, iclass 22, count 0 2006.173.07:38:03.23#ibcon#about to read 5, iclass 22, count 0 2006.173.07:38:03.23#ibcon#read 5, iclass 22, count 0 2006.173.07:38:03.23#ibcon#about to read 6, iclass 22, count 0 2006.173.07:38:03.23#ibcon#read 6, iclass 22, count 0 2006.173.07:38:03.23#ibcon#end of sib2, iclass 22, count 0 2006.173.07:38:03.23#ibcon#*after write, iclass 22, count 0 2006.173.07:38:03.23#ibcon#*before return 0, iclass 22, count 0 2006.173.07:38:03.23#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.07:38:03.23#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.07:38:03.23#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.07:38:03.23#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.07:38:03.23$vck44/vblo=8,744.99 2006.173.07:38:03.23#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.07:38:03.23#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.07:38:03.23#ibcon#ireg 17 cls_cnt 0 2006.173.07:38:03.23#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.07:38:03.23#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.07:38:03.23#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.07:38:03.23#ibcon#enter wrdev, iclass 27, count 0 2006.173.07:38:03.23#ibcon#first serial, iclass 27, count 0 2006.173.07:38:03.23#ibcon#enter sib2, iclass 27, count 0 2006.173.07:38:03.23#ibcon#flushed, iclass 27, count 0 2006.173.07:38:03.23#ibcon#about to write, iclass 27, count 0 2006.173.07:38:03.23#ibcon#wrote, iclass 27, count 0 2006.173.07:38:03.23#ibcon#about to read 3, iclass 27, count 0 2006.173.07:38:03.25#ibcon#read 3, iclass 27, count 0 2006.173.07:38:03.25#ibcon#about to read 4, iclass 27, count 0 2006.173.07:38:03.25#ibcon#read 4, iclass 27, count 0 2006.173.07:38:03.25#ibcon#about to read 5, iclass 27, count 0 2006.173.07:38:03.25#ibcon#read 5, iclass 27, count 0 2006.173.07:38:03.25#ibcon#about to read 6, iclass 27, count 0 2006.173.07:38:03.25#ibcon#read 6, iclass 27, count 0 2006.173.07:38:03.25#ibcon#end of sib2, iclass 27, count 0 2006.173.07:38:03.25#ibcon#*mode == 0, iclass 27, count 0 2006.173.07:38:03.25#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.07:38:03.25#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.07:38:03.25#ibcon#*before write, iclass 27, count 0 2006.173.07:38:03.25#ibcon#enter sib2, iclass 27, count 0 2006.173.07:38:03.25#ibcon#flushed, iclass 27, count 0 2006.173.07:38:03.25#ibcon#about to write, iclass 27, count 0 2006.173.07:38:03.25#ibcon#wrote, iclass 27, count 0 2006.173.07:38:03.25#ibcon#about to read 3, iclass 27, count 0 2006.173.07:38:03.26#abcon#[5=S1D000X0/0*\r\n] 2006.173.07:38:03.29#ibcon#read 3, iclass 27, count 0 2006.173.07:38:03.29#ibcon#about to read 4, iclass 27, count 0 2006.173.07:38:03.29#ibcon#read 4, iclass 27, count 0 2006.173.07:38:03.29#ibcon#about to read 5, iclass 27, count 0 2006.173.07:38:03.29#ibcon#read 5, iclass 27, count 0 2006.173.07:38:03.29#ibcon#about to read 6, iclass 27, count 0 2006.173.07:38:03.29#ibcon#read 6, iclass 27, count 0 2006.173.07:38:03.29#ibcon#end of sib2, iclass 27, count 0 2006.173.07:38:03.29#ibcon#*after write, iclass 27, count 0 2006.173.07:38:03.29#ibcon#*before return 0, iclass 27, count 0 2006.173.07:38:03.29#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.07:38:03.29#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.07:38:03.29#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.07:38:03.29#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.07:38:03.29$vck44/vb=8,4 2006.173.07:38:03.29#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.07:38:03.29#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.07:38:03.29#ibcon#ireg 11 cls_cnt 2 2006.173.07:38:03.29#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.07:38:03.35#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.07:38:03.35#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.07:38:03.35#ibcon#enter wrdev, iclass 30, count 2 2006.173.07:38:03.35#ibcon#first serial, iclass 30, count 2 2006.173.07:38:03.35#ibcon#enter sib2, iclass 30, count 2 2006.173.07:38:03.35#ibcon#flushed, iclass 30, count 2 2006.173.07:38:03.35#ibcon#about to write, iclass 30, count 2 2006.173.07:38:03.35#ibcon#wrote, iclass 30, count 2 2006.173.07:38:03.35#ibcon#about to read 3, iclass 30, count 2 2006.173.07:38:03.37#ibcon#read 3, iclass 30, count 2 2006.173.07:38:03.37#ibcon#about to read 4, iclass 30, count 2 2006.173.07:38:03.37#ibcon#read 4, iclass 30, count 2 2006.173.07:38:03.37#ibcon#about to read 5, iclass 30, count 2 2006.173.07:38:03.37#ibcon#read 5, iclass 30, count 2 2006.173.07:38:03.37#ibcon#about to read 6, iclass 30, count 2 2006.173.07:38:03.37#ibcon#read 6, iclass 30, count 2 2006.173.07:38:03.37#ibcon#end of sib2, iclass 30, count 2 2006.173.07:38:03.37#ibcon#*mode == 0, iclass 30, count 2 2006.173.07:38:03.37#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.07:38:03.37#ibcon#[27=AT08-04\r\n] 2006.173.07:38:03.37#ibcon#*before write, iclass 30, count 2 2006.173.07:38:03.37#ibcon#enter sib2, iclass 30, count 2 2006.173.07:38:03.37#ibcon#flushed, iclass 30, count 2 2006.173.07:38:03.37#ibcon#about to write, iclass 30, count 2 2006.173.07:38:03.37#ibcon#wrote, iclass 30, count 2 2006.173.07:38:03.37#ibcon#about to read 3, iclass 30, count 2 2006.173.07:38:03.40#ibcon#read 3, iclass 30, count 2 2006.173.07:38:03.40#ibcon#about to read 4, iclass 30, count 2 2006.173.07:38:03.40#ibcon#read 4, iclass 30, count 2 2006.173.07:38:03.40#ibcon#about to read 5, iclass 30, count 2 2006.173.07:38:03.40#ibcon#read 5, iclass 30, count 2 2006.173.07:38:03.40#ibcon#about to read 6, iclass 30, count 2 2006.173.07:38:03.40#ibcon#read 6, iclass 30, count 2 2006.173.07:38:03.40#ibcon#end of sib2, iclass 30, count 2 2006.173.07:38:03.40#ibcon#*after write, iclass 30, count 2 2006.173.07:38:03.40#ibcon#*before return 0, iclass 30, count 2 2006.173.07:38:03.40#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.07:38:03.40#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.07:38:03.40#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.07:38:03.40#ibcon#ireg 7 cls_cnt 0 2006.173.07:38:03.40#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.07:38:03.52#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.07:38:03.52#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.07:38:03.52#ibcon#enter wrdev, iclass 30, count 0 2006.173.07:38:03.52#ibcon#first serial, iclass 30, count 0 2006.173.07:38:03.52#ibcon#enter sib2, iclass 30, count 0 2006.173.07:38:03.52#ibcon#flushed, iclass 30, count 0 2006.173.07:38:03.52#ibcon#about to write, iclass 30, count 0 2006.173.07:38:03.52#ibcon#wrote, iclass 30, count 0 2006.173.07:38:03.52#ibcon#about to read 3, iclass 30, count 0 2006.173.07:38:03.54#ibcon#read 3, iclass 30, count 0 2006.173.07:38:03.54#ibcon#about to read 4, iclass 30, count 0 2006.173.07:38:03.54#ibcon#read 4, iclass 30, count 0 2006.173.07:38:03.54#ibcon#about to read 5, iclass 30, count 0 2006.173.07:38:03.54#ibcon#read 5, iclass 30, count 0 2006.173.07:38:03.54#ibcon#about to read 6, iclass 30, count 0 2006.173.07:38:03.54#ibcon#read 6, iclass 30, count 0 2006.173.07:38:03.54#ibcon#end of sib2, iclass 30, count 0 2006.173.07:38:03.54#ibcon#*mode == 0, iclass 30, count 0 2006.173.07:38:03.54#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.07:38:03.54#ibcon#[27=USB\r\n] 2006.173.07:38:03.54#ibcon#*before write, iclass 30, count 0 2006.173.07:38:03.54#ibcon#enter sib2, iclass 30, count 0 2006.173.07:38:03.54#ibcon#flushed, iclass 30, count 0 2006.173.07:38:03.54#ibcon#about to write, iclass 30, count 0 2006.173.07:38:03.54#ibcon#wrote, iclass 30, count 0 2006.173.07:38:03.54#ibcon#about to read 3, iclass 30, count 0 2006.173.07:38:03.57#ibcon#read 3, iclass 30, count 0 2006.173.07:38:03.57#ibcon#about to read 4, iclass 30, count 0 2006.173.07:38:03.57#ibcon#read 4, iclass 30, count 0 2006.173.07:38:03.57#ibcon#about to read 5, iclass 30, count 0 2006.173.07:38:03.57#ibcon#read 5, iclass 30, count 0 2006.173.07:38:03.57#ibcon#about to read 6, iclass 30, count 0 2006.173.07:38:03.57#ibcon#read 6, iclass 30, count 0 2006.173.07:38:03.57#ibcon#end of sib2, iclass 30, count 0 2006.173.07:38:03.57#ibcon#*after write, iclass 30, count 0 2006.173.07:38:03.57#ibcon#*before return 0, iclass 30, count 0 2006.173.07:38:03.57#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.07:38:03.57#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.07:38:03.57#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.07:38:03.57#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.07:38:03.57$vck44/vabw=wide 2006.173.07:38:03.57#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.07:38:03.57#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.07:38:03.57#ibcon#ireg 8 cls_cnt 0 2006.173.07:38:03.57#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.07:38:03.57#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.07:38:03.57#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.07:38:03.57#ibcon#enter wrdev, iclass 32, count 0 2006.173.07:38:03.57#ibcon#first serial, iclass 32, count 0 2006.173.07:38:03.57#ibcon#enter sib2, iclass 32, count 0 2006.173.07:38:03.57#ibcon#flushed, iclass 32, count 0 2006.173.07:38:03.57#ibcon#about to write, iclass 32, count 0 2006.173.07:38:03.57#ibcon#wrote, iclass 32, count 0 2006.173.07:38:03.57#ibcon#about to read 3, iclass 32, count 0 2006.173.07:38:03.59#ibcon#read 3, iclass 32, count 0 2006.173.07:38:03.59#ibcon#about to read 4, iclass 32, count 0 2006.173.07:38:03.59#ibcon#read 4, iclass 32, count 0 2006.173.07:38:03.59#ibcon#about to read 5, iclass 32, count 0 2006.173.07:38:03.59#ibcon#read 5, iclass 32, count 0 2006.173.07:38:03.59#ibcon#about to read 6, iclass 32, count 0 2006.173.07:38:03.59#ibcon#read 6, iclass 32, count 0 2006.173.07:38:03.59#ibcon#end of sib2, iclass 32, count 0 2006.173.07:38:03.59#ibcon#*mode == 0, iclass 32, count 0 2006.173.07:38:03.59#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.07:38:03.59#ibcon#[25=BW32\r\n] 2006.173.07:38:03.59#ibcon#*before write, iclass 32, count 0 2006.173.07:38:03.59#ibcon#enter sib2, iclass 32, count 0 2006.173.07:38:03.59#ibcon#flushed, iclass 32, count 0 2006.173.07:38:03.59#ibcon#about to write, iclass 32, count 0 2006.173.07:38:03.59#ibcon#wrote, iclass 32, count 0 2006.173.07:38:03.59#ibcon#about to read 3, iclass 32, count 0 2006.173.07:38:03.62#ibcon#read 3, iclass 32, count 0 2006.173.07:38:03.62#ibcon#about to read 4, iclass 32, count 0 2006.173.07:38:03.62#ibcon#read 4, iclass 32, count 0 2006.173.07:38:03.62#ibcon#about to read 5, iclass 32, count 0 2006.173.07:38:03.62#ibcon#read 5, iclass 32, count 0 2006.173.07:38:03.62#ibcon#about to read 6, iclass 32, count 0 2006.173.07:38:03.62#ibcon#read 6, iclass 32, count 0 2006.173.07:38:03.62#ibcon#end of sib2, iclass 32, count 0 2006.173.07:38:03.62#ibcon#*after write, iclass 32, count 0 2006.173.07:38:03.62#ibcon#*before return 0, iclass 32, count 0 2006.173.07:38:03.62#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.07:38:03.62#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.07:38:03.62#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.07:38:03.62#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.07:38:03.62$vck44/vbbw=wide 2006.173.07:38:03.62#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.07:38:03.62#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.07:38:03.62#ibcon#ireg 8 cls_cnt 0 2006.173.07:38:03.62#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.07:38:03.69#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.07:38:03.69#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.07:38:03.69#ibcon#enter wrdev, iclass 34, count 0 2006.173.07:38:03.69#ibcon#first serial, iclass 34, count 0 2006.173.07:38:03.69#ibcon#enter sib2, iclass 34, count 0 2006.173.07:38:03.69#ibcon#flushed, iclass 34, count 0 2006.173.07:38:03.69#ibcon#about to write, iclass 34, count 0 2006.173.07:38:03.69#ibcon#wrote, iclass 34, count 0 2006.173.07:38:03.69#ibcon#about to read 3, iclass 34, count 0 2006.173.07:38:03.71#ibcon#read 3, iclass 34, count 0 2006.173.07:38:03.71#ibcon#about to read 4, iclass 34, count 0 2006.173.07:38:03.71#ibcon#read 4, iclass 34, count 0 2006.173.07:38:03.71#ibcon#about to read 5, iclass 34, count 0 2006.173.07:38:03.71#ibcon#read 5, iclass 34, count 0 2006.173.07:38:03.71#ibcon#about to read 6, iclass 34, count 0 2006.173.07:38:03.71#ibcon#read 6, iclass 34, count 0 2006.173.07:38:03.71#ibcon#end of sib2, iclass 34, count 0 2006.173.07:38:03.71#ibcon#*mode == 0, iclass 34, count 0 2006.173.07:38:03.71#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.07:38:03.71#ibcon#[27=BW32\r\n] 2006.173.07:38:03.71#ibcon#*before write, iclass 34, count 0 2006.173.07:38:03.71#ibcon#enter sib2, iclass 34, count 0 2006.173.07:38:03.71#ibcon#flushed, iclass 34, count 0 2006.173.07:38:03.71#ibcon#about to write, iclass 34, count 0 2006.173.07:38:03.71#ibcon#wrote, iclass 34, count 0 2006.173.07:38:03.71#ibcon#about to read 3, iclass 34, count 0 2006.173.07:38:03.74#ibcon#read 3, iclass 34, count 0 2006.173.07:38:03.74#ibcon#about to read 4, iclass 34, count 0 2006.173.07:38:03.74#ibcon#read 4, iclass 34, count 0 2006.173.07:38:03.74#ibcon#about to read 5, iclass 34, count 0 2006.173.07:38:03.74#ibcon#read 5, iclass 34, count 0 2006.173.07:38:03.74#ibcon#about to read 6, iclass 34, count 0 2006.173.07:38:03.74#ibcon#read 6, iclass 34, count 0 2006.173.07:38:03.74#ibcon#end of sib2, iclass 34, count 0 2006.173.07:38:03.74#ibcon#*after write, iclass 34, count 0 2006.173.07:38:03.74#ibcon#*before return 0, iclass 34, count 0 2006.173.07:38:03.74#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.07:38:03.74#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.07:38:03.74#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.07:38:03.74#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.07:38:03.74$setupk4/ifdk4 2006.173.07:38:03.74$ifdk4/lo= 2006.173.07:38:03.74$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.07:38:03.74$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.07:38:03.74$ifdk4/patch= 2006.173.07:38:03.74$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.07:38:03.74$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.07:38:03.74$setupk4/!*+20s 2006.173.07:38:13.35#abcon#<5=/16 0.4 0.9 23.74 841004.4\r\n> 2006.173.07:38:13.37#abcon#{5=INTERFACE CLEAR} 2006.173.07:38:13.43#abcon#[5=S1D000X0/0*\r\n] 2006.173.07:38:18.23$setupk4/"tpicd 2006.173.07:38:18.23$setupk4/echo=off 2006.173.07:38:18.23$setupk4/xlog=off 2006.173.07:38:18.23:!2006.173.07:40:13 2006.173.07:38:20.14#trakl#Source acquired 2006.173.07:38:21.14#flagr#flagr/antenna,acquired 2006.173.07:40:13.00:preob 2006.173.07:40:13.14/onsource/TRACKING 2006.173.07:40:13.14:!2006.173.07:40:23 2006.173.07:40:23.00:"tape 2006.173.07:40:23.00:"st=record 2006.173.07:40:23.00:data_valid=on 2006.173.07:40:23.00:midob 2006.173.07:40:24.14/onsource/TRACKING 2006.173.07:40:24.14/wx/23.72,1004.4,84 2006.173.07:40:24.25/cable/+6.5026E-03 2006.173.07:40:25.34/va/01,07,usb,yes,34,37 2006.173.07:40:25.34/va/02,06,usb,yes,34,35 2006.173.07:40:25.34/va/03,05,usb,yes,43,45 2006.173.07:40:25.34/va/04,06,usb,yes,35,37 2006.173.07:40:25.34/va/05,04,usb,yes,27,28 2006.173.07:40:25.34/va/06,03,usb,yes,38,38 2006.173.07:40:25.34/va/07,04,usb,yes,31,32 2006.173.07:40:25.34/va/08,04,usb,yes,26,32 2006.173.07:40:25.57/valo/01,524.99,yes,locked 2006.173.07:40:25.57/valo/02,534.99,yes,locked 2006.173.07:40:25.57/valo/03,564.99,yes,locked 2006.173.07:40:25.57/valo/04,624.99,yes,locked 2006.173.07:40:25.57/valo/05,734.99,yes,locked 2006.173.07:40:25.57/valo/06,814.99,yes,locked 2006.173.07:40:25.57/valo/07,864.99,yes,locked 2006.173.07:40:25.57/valo/08,884.99,yes,locked 2006.173.07:40:26.66/vb/01,04,usb,yes,29,27 2006.173.07:40:26.66/vb/02,04,usb,yes,31,31 2006.173.07:40:26.66/vb/03,04,usb,yes,28,31 2006.173.07:40:26.66/vb/04,04,usb,yes,32,31 2006.173.07:40:26.66/vb/05,04,usb,yes,25,28 2006.173.07:40:26.66/vb/06,04,usb,yes,30,26 2006.173.07:40:26.66/vb/07,04,usb,yes,29,29 2006.173.07:40:26.66/vb/08,04,usb,yes,28,30 2006.173.07:40:26.89/vblo/01,629.99,yes,locked 2006.173.07:40:26.89/vblo/02,634.99,yes,locked 2006.173.07:40:26.89/vblo/03,649.99,yes,locked 2006.173.07:40:26.89/vblo/04,679.99,yes,locked 2006.173.07:40:26.89/vblo/05,709.99,yes,locked 2006.173.07:40:26.89/vblo/06,719.99,yes,locked 2006.173.07:40:26.89/vblo/07,734.99,yes,locked 2006.173.07:40:26.89/vblo/08,744.99,yes,locked 2006.173.07:40:27.04/vabw/8 2006.173.07:40:27.19/vbbw/8 2006.173.07:40:27.33/xfe/off,on,14.2 2006.173.07:40:27.71/ifatt/23,28,28,28 2006.173.07:40:28.08/fmout-gps/S +3.95E-07 2006.173.07:40:28.12:!2006.173.07:44:03 2006.173.07:44:03.00:data_valid=off 2006.173.07:44:03.00:"et 2006.173.07:44:03.00:!+3s 2006.173.07:44:06.02:"tape 2006.173.07:44:06.02:postob 2006.173.07:44:06.12/cable/+6.5014E-03 2006.173.07:44:06.12/wx/23.67,1004.4,83 2006.173.07:44:07.08/fmout-gps/S +3.93E-07 2006.173.07:44:07.08:scan_name=173-0747,jd0606,60 2006.173.07:44:07.08:source=1611+343,161341.06,341247.9,2000.0,cw 2006.173.07:44:08.13#flagr#flagr/antenna,new-source 2006.173.07:44:08.13:checkk5 2006.173.07:44:08.55/chk_autoobs//k5ts1/ autoobs is running! 2006.173.07:44:08.94/chk_autoobs//k5ts2/ autoobs is running! 2006.173.07:44:09.34/chk_autoobs//k5ts3/ autoobs is running! 2006.173.07:44:09.75/chk_autoobs//k5ts4/ autoobs is running! 2006.173.07:44:10.14/chk_obsdata//k5ts1/T1730740??a.dat file size is correct (nominal:880MB, actual:876MB). 2006.173.07:44:10.56/chk_obsdata//k5ts2/T1730740??b.dat file size is correct (nominal:880MB, actual:876MB). 2006.173.07:44:10.95/chk_obsdata//k5ts3/T1730740??c.dat file size is correct (nominal:880MB, actual:876MB). 2006.173.07:44:11.36/chk_obsdata//k5ts4/T1730740??d.dat file size is correct (nominal:880MB, actual:876MB). 2006.173.07:44:12.10/k5log//k5ts1_log_newline 2006.173.07:44:12.80/k5log//k5ts2_log_newline 2006.173.07:44:13.50/k5log//k5ts3_log_newline 2006.173.07:44:14.21/k5log//k5ts4_log_newline 2006.173.07:44:14.23/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.07:44:14.23:setupk4=1 2006.173.07:44:14.23$setupk4/echo=on 2006.173.07:44:14.23$setupk4/pcalon 2006.173.07:44:14.23$pcalon/"no phase cal control is implemented here 2006.173.07:44:14.23$setupk4/"tpicd=stop 2006.173.07:44:14.23$setupk4/"rec=synch_on 2006.173.07:44:14.23$setupk4/"rec_mode=128 2006.173.07:44:14.23$setupk4/!* 2006.173.07:44:14.23$setupk4/recpk4 2006.173.07:44:14.23$recpk4/recpatch= 2006.173.07:44:14.24$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.07:44:14.24$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.07:44:14.24$setupk4/vck44 2006.173.07:44:14.24$vck44/valo=1,524.99 2006.173.07:44:14.24#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.07:44:14.24#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.07:44:14.24#ibcon#ireg 17 cls_cnt 0 2006.173.07:44:14.24#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.07:44:14.24#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.07:44:14.24#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.07:44:14.24#ibcon#enter wrdev, iclass 39, count 0 2006.173.07:44:14.24#ibcon#first serial, iclass 39, count 0 2006.173.07:44:14.24#ibcon#enter sib2, iclass 39, count 0 2006.173.07:44:14.24#ibcon#flushed, iclass 39, count 0 2006.173.07:44:14.24#ibcon#about to write, iclass 39, count 0 2006.173.07:44:14.24#ibcon#wrote, iclass 39, count 0 2006.173.07:44:14.24#ibcon#about to read 3, iclass 39, count 0 2006.173.07:44:14.26#ibcon#read 3, iclass 39, count 0 2006.173.07:44:14.26#ibcon#about to read 4, iclass 39, count 0 2006.173.07:44:14.26#ibcon#read 4, iclass 39, count 0 2006.173.07:44:14.26#ibcon#about to read 5, iclass 39, count 0 2006.173.07:44:14.26#ibcon#read 5, iclass 39, count 0 2006.173.07:44:14.26#ibcon#about to read 6, iclass 39, count 0 2006.173.07:44:14.26#ibcon#read 6, iclass 39, count 0 2006.173.07:44:14.26#ibcon#end of sib2, iclass 39, count 0 2006.173.07:44:14.26#ibcon#*mode == 0, iclass 39, count 0 2006.173.07:44:14.26#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.07:44:14.26#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.07:44:14.26#ibcon#*before write, iclass 39, count 0 2006.173.07:44:14.26#ibcon#enter sib2, iclass 39, count 0 2006.173.07:44:14.26#ibcon#flushed, iclass 39, count 0 2006.173.07:44:14.26#ibcon#about to write, iclass 39, count 0 2006.173.07:44:14.26#ibcon#wrote, iclass 39, count 0 2006.173.07:44:14.26#ibcon#about to read 3, iclass 39, count 0 2006.173.07:44:14.31#ibcon#read 3, iclass 39, count 0 2006.173.07:44:14.31#ibcon#about to read 4, iclass 39, count 0 2006.173.07:44:14.31#ibcon#read 4, iclass 39, count 0 2006.173.07:44:14.31#ibcon#about to read 5, iclass 39, count 0 2006.173.07:44:14.31#ibcon#read 5, iclass 39, count 0 2006.173.07:44:14.31#ibcon#about to read 6, iclass 39, count 0 2006.173.07:44:14.31#ibcon#read 6, iclass 39, count 0 2006.173.07:44:14.31#ibcon#end of sib2, iclass 39, count 0 2006.173.07:44:14.31#ibcon#*after write, iclass 39, count 0 2006.173.07:44:14.31#ibcon#*before return 0, iclass 39, count 0 2006.173.07:44:14.31#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.07:44:14.31#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.07:44:14.31#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.07:44:14.31#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.07:44:14.31$vck44/va=1,7 2006.173.07:44:14.31#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.07:44:14.31#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.07:44:14.31#ibcon#ireg 11 cls_cnt 2 2006.173.07:44:14.31#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.07:44:14.31#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.07:44:14.31#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.07:44:14.31#ibcon#enter wrdev, iclass 3, count 2 2006.173.07:44:14.31#ibcon#first serial, iclass 3, count 2 2006.173.07:44:14.31#ibcon#enter sib2, iclass 3, count 2 2006.173.07:44:14.31#ibcon#flushed, iclass 3, count 2 2006.173.07:44:14.31#ibcon#about to write, iclass 3, count 2 2006.173.07:44:14.31#ibcon#wrote, iclass 3, count 2 2006.173.07:44:14.31#ibcon#about to read 3, iclass 3, count 2 2006.173.07:44:14.33#ibcon#read 3, iclass 3, count 2 2006.173.07:44:14.33#ibcon#about to read 4, iclass 3, count 2 2006.173.07:44:14.33#ibcon#read 4, iclass 3, count 2 2006.173.07:44:14.33#ibcon#about to read 5, iclass 3, count 2 2006.173.07:44:14.33#ibcon#read 5, iclass 3, count 2 2006.173.07:44:14.33#ibcon#about to read 6, iclass 3, count 2 2006.173.07:44:14.33#ibcon#read 6, iclass 3, count 2 2006.173.07:44:14.33#ibcon#end of sib2, iclass 3, count 2 2006.173.07:44:14.33#ibcon#*mode == 0, iclass 3, count 2 2006.173.07:44:14.33#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.07:44:14.33#ibcon#[25=AT01-07\r\n] 2006.173.07:44:14.33#ibcon#*before write, iclass 3, count 2 2006.173.07:44:14.33#ibcon#enter sib2, iclass 3, count 2 2006.173.07:44:14.33#ibcon#flushed, iclass 3, count 2 2006.173.07:44:14.33#ibcon#about to write, iclass 3, count 2 2006.173.07:44:14.33#ibcon#wrote, iclass 3, count 2 2006.173.07:44:14.33#ibcon#about to read 3, iclass 3, count 2 2006.173.07:44:14.36#ibcon#read 3, iclass 3, count 2 2006.173.07:44:14.36#ibcon#about to read 4, iclass 3, count 2 2006.173.07:44:14.36#ibcon#read 4, iclass 3, count 2 2006.173.07:44:14.36#ibcon#about to read 5, iclass 3, count 2 2006.173.07:44:14.36#ibcon#read 5, iclass 3, count 2 2006.173.07:44:14.36#ibcon#about to read 6, iclass 3, count 2 2006.173.07:44:14.36#ibcon#read 6, iclass 3, count 2 2006.173.07:44:14.36#ibcon#end of sib2, iclass 3, count 2 2006.173.07:44:14.36#ibcon#*after write, iclass 3, count 2 2006.173.07:44:14.36#ibcon#*before return 0, iclass 3, count 2 2006.173.07:44:14.36#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.07:44:14.36#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.07:44:14.36#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.07:44:14.36#ibcon#ireg 7 cls_cnt 0 2006.173.07:44:14.36#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.07:44:14.48#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.07:44:14.48#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.07:44:14.48#ibcon#enter wrdev, iclass 3, count 0 2006.173.07:44:14.48#ibcon#first serial, iclass 3, count 0 2006.173.07:44:14.48#ibcon#enter sib2, iclass 3, count 0 2006.173.07:44:14.48#ibcon#flushed, iclass 3, count 0 2006.173.07:44:14.48#ibcon#about to write, iclass 3, count 0 2006.173.07:44:14.48#ibcon#wrote, iclass 3, count 0 2006.173.07:44:14.48#ibcon#about to read 3, iclass 3, count 0 2006.173.07:44:14.50#ibcon#read 3, iclass 3, count 0 2006.173.07:44:14.50#ibcon#about to read 4, iclass 3, count 0 2006.173.07:44:14.50#ibcon#read 4, iclass 3, count 0 2006.173.07:44:14.50#ibcon#about to read 5, iclass 3, count 0 2006.173.07:44:14.50#ibcon#read 5, iclass 3, count 0 2006.173.07:44:14.50#ibcon#about to read 6, iclass 3, count 0 2006.173.07:44:14.50#ibcon#read 6, iclass 3, count 0 2006.173.07:44:14.50#ibcon#end of sib2, iclass 3, count 0 2006.173.07:44:14.50#ibcon#*mode == 0, iclass 3, count 0 2006.173.07:44:14.50#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.07:44:14.50#ibcon#[25=USB\r\n] 2006.173.07:44:14.50#ibcon#*before write, iclass 3, count 0 2006.173.07:44:14.50#ibcon#enter sib2, iclass 3, count 0 2006.173.07:44:14.50#ibcon#flushed, iclass 3, count 0 2006.173.07:44:14.50#ibcon#about to write, iclass 3, count 0 2006.173.07:44:14.50#ibcon#wrote, iclass 3, count 0 2006.173.07:44:14.50#ibcon#about to read 3, iclass 3, count 0 2006.173.07:44:14.53#ibcon#read 3, iclass 3, count 0 2006.173.07:44:14.53#ibcon#about to read 4, iclass 3, count 0 2006.173.07:44:14.53#ibcon#read 4, iclass 3, count 0 2006.173.07:44:14.53#ibcon#about to read 5, iclass 3, count 0 2006.173.07:44:14.53#ibcon#read 5, iclass 3, count 0 2006.173.07:44:14.53#ibcon#about to read 6, iclass 3, count 0 2006.173.07:44:14.53#ibcon#read 6, iclass 3, count 0 2006.173.07:44:14.53#ibcon#end of sib2, iclass 3, count 0 2006.173.07:44:14.53#ibcon#*after write, iclass 3, count 0 2006.173.07:44:14.53#ibcon#*before return 0, iclass 3, count 0 2006.173.07:44:14.53#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.07:44:14.53#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.07:44:14.53#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.07:44:14.53#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.07:44:14.53$vck44/valo=2,534.99 2006.173.07:44:14.53#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.07:44:14.53#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.07:44:14.53#ibcon#ireg 17 cls_cnt 0 2006.173.07:44:14.53#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.07:44:14.53#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.07:44:14.53#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.07:44:14.53#ibcon#enter wrdev, iclass 5, count 0 2006.173.07:44:14.53#ibcon#first serial, iclass 5, count 0 2006.173.07:44:14.53#ibcon#enter sib2, iclass 5, count 0 2006.173.07:44:14.53#ibcon#flushed, iclass 5, count 0 2006.173.07:44:14.53#ibcon#about to write, iclass 5, count 0 2006.173.07:44:14.53#ibcon#wrote, iclass 5, count 0 2006.173.07:44:14.53#ibcon#about to read 3, iclass 5, count 0 2006.173.07:44:14.55#ibcon#read 3, iclass 5, count 0 2006.173.07:44:14.55#ibcon#about to read 4, iclass 5, count 0 2006.173.07:44:14.55#ibcon#read 4, iclass 5, count 0 2006.173.07:44:14.55#ibcon#about to read 5, iclass 5, count 0 2006.173.07:44:14.55#ibcon#read 5, iclass 5, count 0 2006.173.07:44:14.55#ibcon#about to read 6, iclass 5, count 0 2006.173.07:44:14.55#ibcon#read 6, iclass 5, count 0 2006.173.07:44:14.55#ibcon#end of sib2, iclass 5, count 0 2006.173.07:44:14.55#ibcon#*mode == 0, iclass 5, count 0 2006.173.07:44:14.55#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.07:44:14.55#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.07:44:14.55#ibcon#*before write, iclass 5, count 0 2006.173.07:44:14.55#ibcon#enter sib2, iclass 5, count 0 2006.173.07:44:14.55#ibcon#flushed, iclass 5, count 0 2006.173.07:44:14.55#ibcon#about to write, iclass 5, count 0 2006.173.07:44:14.55#ibcon#wrote, iclass 5, count 0 2006.173.07:44:14.55#ibcon#about to read 3, iclass 5, count 0 2006.173.07:44:14.59#ibcon#read 3, iclass 5, count 0 2006.173.07:44:14.59#ibcon#about to read 4, iclass 5, count 0 2006.173.07:44:14.59#ibcon#read 4, iclass 5, count 0 2006.173.07:44:14.59#ibcon#about to read 5, iclass 5, count 0 2006.173.07:44:14.59#ibcon#read 5, iclass 5, count 0 2006.173.07:44:14.59#ibcon#about to read 6, iclass 5, count 0 2006.173.07:44:14.59#ibcon#read 6, iclass 5, count 0 2006.173.07:44:14.59#ibcon#end of sib2, iclass 5, count 0 2006.173.07:44:14.59#ibcon#*after write, iclass 5, count 0 2006.173.07:44:14.59#ibcon#*before return 0, iclass 5, count 0 2006.173.07:44:14.59#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.07:44:14.59#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.07:44:14.59#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.07:44:14.59#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.07:44:14.59$vck44/va=2,6 2006.173.07:44:14.59#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.173.07:44:14.59#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.173.07:44:14.59#ibcon#ireg 11 cls_cnt 2 2006.173.07:44:14.59#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.07:44:14.65#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.07:44:14.65#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.07:44:14.65#ibcon#enter wrdev, iclass 7, count 2 2006.173.07:44:14.65#ibcon#first serial, iclass 7, count 2 2006.173.07:44:14.65#ibcon#enter sib2, iclass 7, count 2 2006.173.07:44:14.65#ibcon#flushed, iclass 7, count 2 2006.173.07:44:14.65#ibcon#about to write, iclass 7, count 2 2006.173.07:44:14.65#ibcon#wrote, iclass 7, count 2 2006.173.07:44:14.65#ibcon#about to read 3, iclass 7, count 2 2006.173.07:44:14.67#ibcon#read 3, iclass 7, count 2 2006.173.07:44:14.67#ibcon#about to read 4, iclass 7, count 2 2006.173.07:44:14.67#ibcon#read 4, iclass 7, count 2 2006.173.07:44:14.67#ibcon#about to read 5, iclass 7, count 2 2006.173.07:44:14.67#ibcon#read 5, iclass 7, count 2 2006.173.07:44:14.67#ibcon#about to read 6, iclass 7, count 2 2006.173.07:44:14.67#ibcon#read 6, iclass 7, count 2 2006.173.07:44:14.67#ibcon#end of sib2, iclass 7, count 2 2006.173.07:44:14.67#ibcon#*mode == 0, iclass 7, count 2 2006.173.07:44:14.67#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.173.07:44:14.67#ibcon#[25=AT02-06\r\n] 2006.173.07:44:14.67#ibcon#*before write, iclass 7, count 2 2006.173.07:44:14.67#ibcon#enter sib2, iclass 7, count 2 2006.173.07:44:14.67#ibcon#flushed, iclass 7, count 2 2006.173.07:44:14.67#ibcon#about to write, iclass 7, count 2 2006.173.07:44:14.67#ibcon#wrote, iclass 7, count 2 2006.173.07:44:14.67#ibcon#about to read 3, iclass 7, count 2 2006.173.07:44:14.70#ibcon#read 3, iclass 7, count 2 2006.173.07:44:14.70#ibcon#about to read 4, iclass 7, count 2 2006.173.07:44:14.70#ibcon#read 4, iclass 7, count 2 2006.173.07:44:14.70#ibcon#about to read 5, iclass 7, count 2 2006.173.07:44:14.70#ibcon#read 5, iclass 7, count 2 2006.173.07:44:14.70#ibcon#about to read 6, iclass 7, count 2 2006.173.07:44:14.70#ibcon#read 6, iclass 7, count 2 2006.173.07:44:14.70#ibcon#end of sib2, iclass 7, count 2 2006.173.07:44:14.70#ibcon#*after write, iclass 7, count 2 2006.173.07:44:14.70#ibcon#*before return 0, iclass 7, count 2 2006.173.07:44:14.70#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.07:44:14.70#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.173.07:44:14.70#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.173.07:44:14.70#ibcon#ireg 7 cls_cnt 0 2006.173.07:44:14.70#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.07:44:14.82#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.07:44:14.82#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.07:44:14.82#ibcon#enter wrdev, iclass 7, count 0 2006.173.07:44:14.82#ibcon#first serial, iclass 7, count 0 2006.173.07:44:14.82#ibcon#enter sib2, iclass 7, count 0 2006.173.07:44:14.82#ibcon#flushed, iclass 7, count 0 2006.173.07:44:14.82#ibcon#about to write, iclass 7, count 0 2006.173.07:44:14.82#ibcon#wrote, iclass 7, count 0 2006.173.07:44:14.82#ibcon#about to read 3, iclass 7, count 0 2006.173.07:44:14.84#ibcon#read 3, iclass 7, count 0 2006.173.07:44:14.84#ibcon#about to read 4, iclass 7, count 0 2006.173.07:44:14.84#ibcon#read 4, iclass 7, count 0 2006.173.07:44:14.84#ibcon#about to read 5, iclass 7, count 0 2006.173.07:44:14.84#ibcon#read 5, iclass 7, count 0 2006.173.07:44:14.84#ibcon#about to read 6, iclass 7, count 0 2006.173.07:44:14.84#ibcon#read 6, iclass 7, count 0 2006.173.07:44:14.84#ibcon#end of sib2, iclass 7, count 0 2006.173.07:44:14.84#ibcon#*mode == 0, iclass 7, count 0 2006.173.07:44:14.84#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.07:44:14.84#ibcon#[25=USB\r\n] 2006.173.07:44:14.84#ibcon#*before write, iclass 7, count 0 2006.173.07:44:14.84#ibcon#enter sib2, iclass 7, count 0 2006.173.07:44:14.84#ibcon#flushed, iclass 7, count 0 2006.173.07:44:14.84#ibcon#about to write, iclass 7, count 0 2006.173.07:44:14.84#ibcon#wrote, iclass 7, count 0 2006.173.07:44:14.84#ibcon#about to read 3, iclass 7, count 0 2006.173.07:44:14.87#ibcon#read 3, iclass 7, count 0 2006.173.07:44:14.87#ibcon#about to read 4, iclass 7, count 0 2006.173.07:44:14.87#ibcon#read 4, iclass 7, count 0 2006.173.07:44:14.87#ibcon#about to read 5, iclass 7, count 0 2006.173.07:44:14.87#ibcon#read 5, iclass 7, count 0 2006.173.07:44:14.87#ibcon#about to read 6, iclass 7, count 0 2006.173.07:44:14.87#ibcon#read 6, iclass 7, count 0 2006.173.07:44:14.87#ibcon#end of sib2, iclass 7, count 0 2006.173.07:44:14.87#ibcon#*after write, iclass 7, count 0 2006.173.07:44:14.87#ibcon#*before return 0, iclass 7, count 0 2006.173.07:44:14.87#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.07:44:14.87#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.173.07:44:14.87#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.07:44:14.87#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.07:44:14.87$vck44/valo=3,564.99 2006.173.07:44:14.87#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.07:44:14.87#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.07:44:14.87#ibcon#ireg 17 cls_cnt 0 2006.173.07:44:14.87#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.07:44:14.87#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.07:44:14.87#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.07:44:14.87#ibcon#enter wrdev, iclass 11, count 0 2006.173.07:44:14.87#ibcon#first serial, iclass 11, count 0 2006.173.07:44:14.87#ibcon#enter sib2, iclass 11, count 0 2006.173.07:44:14.87#ibcon#flushed, iclass 11, count 0 2006.173.07:44:14.87#ibcon#about to write, iclass 11, count 0 2006.173.07:44:14.87#ibcon#wrote, iclass 11, count 0 2006.173.07:44:14.87#ibcon#about to read 3, iclass 11, count 0 2006.173.07:44:14.89#ibcon#read 3, iclass 11, count 0 2006.173.07:44:14.89#ibcon#about to read 4, iclass 11, count 0 2006.173.07:44:14.89#ibcon#read 4, iclass 11, count 0 2006.173.07:44:14.89#ibcon#about to read 5, iclass 11, count 0 2006.173.07:44:14.89#ibcon#read 5, iclass 11, count 0 2006.173.07:44:14.89#ibcon#about to read 6, iclass 11, count 0 2006.173.07:44:14.89#ibcon#read 6, iclass 11, count 0 2006.173.07:44:14.89#ibcon#end of sib2, iclass 11, count 0 2006.173.07:44:14.89#ibcon#*mode == 0, iclass 11, count 0 2006.173.07:44:14.89#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.07:44:14.89#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.07:44:14.89#ibcon#*before write, iclass 11, count 0 2006.173.07:44:14.89#ibcon#enter sib2, iclass 11, count 0 2006.173.07:44:14.89#ibcon#flushed, iclass 11, count 0 2006.173.07:44:14.89#ibcon#about to write, iclass 11, count 0 2006.173.07:44:14.89#ibcon#wrote, iclass 11, count 0 2006.173.07:44:14.89#ibcon#about to read 3, iclass 11, count 0 2006.173.07:44:14.93#ibcon#read 3, iclass 11, count 0 2006.173.07:44:14.93#ibcon#about to read 4, iclass 11, count 0 2006.173.07:44:14.93#ibcon#read 4, iclass 11, count 0 2006.173.07:44:14.93#ibcon#about to read 5, iclass 11, count 0 2006.173.07:44:14.93#ibcon#read 5, iclass 11, count 0 2006.173.07:44:14.93#ibcon#about to read 6, iclass 11, count 0 2006.173.07:44:14.93#ibcon#read 6, iclass 11, count 0 2006.173.07:44:14.93#ibcon#end of sib2, iclass 11, count 0 2006.173.07:44:14.93#ibcon#*after write, iclass 11, count 0 2006.173.07:44:14.93#ibcon#*before return 0, iclass 11, count 0 2006.173.07:44:14.93#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.07:44:14.93#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.07:44:14.93#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.07:44:14.93#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.07:44:14.93$vck44/va=3,5 2006.173.07:44:14.93#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.173.07:44:14.93#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.173.07:44:14.93#ibcon#ireg 11 cls_cnt 2 2006.173.07:44:14.93#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.07:44:14.99#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.07:44:14.99#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.07:44:14.99#ibcon#enter wrdev, iclass 13, count 2 2006.173.07:44:14.99#ibcon#first serial, iclass 13, count 2 2006.173.07:44:14.99#ibcon#enter sib2, iclass 13, count 2 2006.173.07:44:14.99#ibcon#flushed, iclass 13, count 2 2006.173.07:44:14.99#ibcon#about to write, iclass 13, count 2 2006.173.07:44:14.99#ibcon#wrote, iclass 13, count 2 2006.173.07:44:14.99#ibcon#about to read 3, iclass 13, count 2 2006.173.07:44:15.01#ibcon#read 3, iclass 13, count 2 2006.173.07:44:15.01#ibcon#about to read 4, iclass 13, count 2 2006.173.07:44:15.01#ibcon#read 4, iclass 13, count 2 2006.173.07:44:15.01#ibcon#about to read 5, iclass 13, count 2 2006.173.07:44:15.01#ibcon#read 5, iclass 13, count 2 2006.173.07:44:15.01#ibcon#about to read 6, iclass 13, count 2 2006.173.07:44:15.01#ibcon#read 6, iclass 13, count 2 2006.173.07:44:15.01#ibcon#end of sib2, iclass 13, count 2 2006.173.07:44:15.01#ibcon#*mode == 0, iclass 13, count 2 2006.173.07:44:15.01#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.173.07:44:15.01#ibcon#[25=AT03-05\r\n] 2006.173.07:44:15.01#ibcon#*before write, iclass 13, count 2 2006.173.07:44:15.01#ibcon#enter sib2, iclass 13, count 2 2006.173.07:44:15.01#ibcon#flushed, iclass 13, count 2 2006.173.07:44:15.01#ibcon#about to write, iclass 13, count 2 2006.173.07:44:15.01#ibcon#wrote, iclass 13, count 2 2006.173.07:44:15.01#ibcon#about to read 3, iclass 13, count 2 2006.173.07:44:15.04#ibcon#read 3, iclass 13, count 2 2006.173.07:44:15.04#ibcon#about to read 4, iclass 13, count 2 2006.173.07:44:15.04#ibcon#read 4, iclass 13, count 2 2006.173.07:44:15.04#ibcon#about to read 5, iclass 13, count 2 2006.173.07:44:15.04#ibcon#read 5, iclass 13, count 2 2006.173.07:44:15.04#ibcon#about to read 6, iclass 13, count 2 2006.173.07:44:15.04#ibcon#read 6, iclass 13, count 2 2006.173.07:44:15.04#ibcon#end of sib2, iclass 13, count 2 2006.173.07:44:15.04#ibcon#*after write, iclass 13, count 2 2006.173.07:44:15.04#ibcon#*before return 0, iclass 13, count 2 2006.173.07:44:15.04#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.07:44:15.04#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.173.07:44:15.04#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.173.07:44:15.04#ibcon#ireg 7 cls_cnt 0 2006.173.07:44:15.04#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.07:44:15.16#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.07:44:15.16#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.07:44:15.16#ibcon#enter wrdev, iclass 13, count 0 2006.173.07:44:15.16#ibcon#first serial, iclass 13, count 0 2006.173.07:44:15.16#ibcon#enter sib2, iclass 13, count 0 2006.173.07:44:15.16#ibcon#flushed, iclass 13, count 0 2006.173.07:44:15.16#ibcon#about to write, iclass 13, count 0 2006.173.07:44:15.16#ibcon#wrote, iclass 13, count 0 2006.173.07:44:15.16#ibcon#about to read 3, iclass 13, count 0 2006.173.07:44:15.18#ibcon#read 3, iclass 13, count 0 2006.173.07:44:15.18#ibcon#about to read 4, iclass 13, count 0 2006.173.07:44:15.18#ibcon#read 4, iclass 13, count 0 2006.173.07:44:15.18#ibcon#about to read 5, iclass 13, count 0 2006.173.07:44:15.18#ibcon#read 5, iclass 13, count 0 2006.173.07:44:15.18#ibcon#about to read 6, iclass 13, count 0 2006.173.07:44:15.18#ibcon#read 6, iclass 13, count 0 2006.173.07:44:15.18#ibcon#end of sib2, iclass 13, count 0 2006.173.07:44:15.18#ibcon#*mode == 0, iclass 13, count 0 2006.173.07:44:15.18#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.07:44:15.18#ibcon#[25=USB\r\n] 2006.173.07:44:15.18#ibcon#*before write, iclass 13, count 0 2006.173.07:44:15.18#ibcon#enter sib2, iclass 13, count 0 2006.173.07:44:15.18#ibcon#flushed, iclass 13, count 0 2006.173.07:44:15.18#ibcon#about to write, iclass 13, count 0 2006.173.07:44:15.18#ibcon#wrote, iclass 13, count 0 2006.173.07:44:15.18#ibcon#about to read 3, iclass 13, count 0 2006.173.07:44:15.21#ibcon#read 3, iclass 13, count 0 2006.173.07:44:15.21#ibcon#about to read 4, iclass 13, count 0 2006.173.07:44:15.21#ibcon#read 4, iclass 13, count 0 2006.173.07:44:15.21#ibcon#about to read 5, iclass 13, count 0 2006.173.07:44:15.21#ibcon#read 5, iclass 13, count 0 2006.173.07:44:15.21#ibcon#about to read 6, iclass 13, count 0 2006.173.07:44:15.21#ibcon#read 6, iclass 13, count 0 2006.173.07:44:15.21#ibcon#end of sib2, iclass 13, count 0 2006.173.07:44:15.21#ibcon#*after write, iclass 13, count 0 2006.173.07:44:15.21#ibcon#*before return 0, iclass 13, count 0 2006.173.07:44:15.21#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.07:44:15.21#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.173.07:44:15.21#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.07:44:15.21#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.07:44:15.21$vck44/valo=4,624.99 2006.173.07:44:15.21#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.07:44:15.21#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.07:44:15.21#ibcon#ireg 17 cls_cnt 0 2006.173.07:44:15.21#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.07:44:15.21#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.07:44:15.21#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.07:44:15.21#ibcon#enter wrdev, iclass 15, count 0 2006.173.07:44:15.21#ibcon#first serial, iclass 15, count 0 2006.173.07:44:15.21#ibcon#enter sib2, iclass 15, count 0 2006.173.07:44:15.21#ibcon#flushed, iclass 15, count 0 2006.173.07:44:15.21#ibcon#about to write, iclass 15, count 0 2006.173.07:44:15.21#ibcon#wrote, iclass 15, count 0 2006.173.07:44:15.21#ibcon#about to read 3, iclass 15, count 0 2006.173.07:44:15.23#ibcon#read 3, iclass 15, count 0 2006.173.07:44:15.23#ibcon#about to read 4, iclass 15, count 0 2006.173.07:44:15.23#ibcon#read 4, iclass 15, count 0 2006.173.07:44:15.23#ibcon#about to read 5, iclass 15, count 0 2006.173.07:44:15.23#ibcon#read 5, iclass 15, count 0 2006.173.07:44:15.23#ibcon#about to read 6, iclass 15, count 0 2006.173.07:44:15.23#ibcon#read 6, iclass 15, count 0 2006.173.07:44:15.23#ibcon#end of sib2, iclass 15, count 0 2006.173.07:44:15.23#ibcon#*mode == 0, iclass 15, count 0 2006.173.07:44:15.23#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.07:44:15.23#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.07:44:15.23#ibcon#*before write, iclass 15, count 0 2006.173.07:44:15.23#ibcon#enter sib2, iclass 15, count 0 2006.173.07:44:15.23#ibcon#flushed, iclass 15, count 0 2006.173.07:44:15.23#ibcon#about to write, iclass 15, count 0 2006.173.07:44:15.23#ibcon#wrote, iclass 15, count 0 2006.173.07:44:15.23#ibcon#about to read 3, iclass 15, count 0 2006.173.07:44:15.27#ibcon#read 3, iclass 15, count 0 2006.173.07:44:15.27#ibcon#about to read 4, iclass 15, count 0 2006.173.07:44:15.27#ibcon#read 4, iclass 15, count 0 2006.173.07:44:15.27#ibcon#about to read 5, iclass 15, count 0 2006.173.07:44:15.27#ibcon#read 5, iclass 15, count 0 2006.173.07:44:15.27#ibcon#about to read 6, iclass 15, count 0 2006.173.07:44:15.27#ibcon#read 6, iclass 15, count 0 2006.173.07:44:15.27#ibcon#end of sib2, iclass 15, count 0 2006.173.07:44:15.27#ibcon#*after write, iclass 15, count 0 2006.173.07:44:15.27#ibcon#*before return 0, iclass 15, count 0 2006.173.07:44:15.27#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.07:44:15.27#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.07:44:15.27#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.07:44:15.27#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.07:44:15.27$vck44/va=4,6 2006.173.07:44:15.27#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.07:44:15.27#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.07:44:15.27#ibcon#ireg 11 cls_cnt 2 2006.173.07:44:15.27#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.07:44:15.33#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.07:44:15.33#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.07:44:15.33#ibcon#enter wrdev, iclass 17, count 2 2006.173.07:44:15.33#ibcon#first serial, iclass 17, count 2 2006.173.07:44:15.33#ibcon#enter sib2, iclass 17, count 2 2006.173.07:44:15.33#ibcon#flushed, iclass 17, count 2 2006.173.07:44:15.33#ibcon#about to write, iclass 17, count 2 2006.173.07:44:15.33#ibcon#wrote, iclass 17, count 2 2006.173.07:44:15.33#ibcon#about to read 3, iclass 17, count 2 2006.173.07:44:15.35#ibcon#read 3, iclass 17, count 2 2006.173.07:44:15.35#ibcon#about to read 4, iclass 17, count 2 2006.173.07:44:15.35#ibcon#read 4, iclass 17, count 2 2006.173.07:44:15.35#ibcon#about to read 5, iclass 17, count 2 2006.173.07:44:15.35#ibcon#read 5, iclass 17, count 2 2006.173.07:44:15.35#ibcon#about to read 6, iclass 17, count 2 2006.173.07:44:15.35#ibcon#read 6, iclass 17, count 2 2006.173.07:44:15.35#ibcon#end of sib2, iclass 17, count 2 2006.173.07:44:15.35#ibcon#*mode == 0, iclass 17, count 2 2006.173.07:44:15.35#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.07:44:15.35#ibcon#[25=AT04-06\r\n] 2006.173.07:44:15.35#ibcon#*before write, iclass 17, count 2 2006.173.07:44:15.35#ibcon#enter sib2, iclass 17, count 2 2006.173.07:44:15.35#ibcon#flushed, iclass 17, count 2 2006.173.07:44:15.35#ibcon#about to write, iclass 17, count 2 2006.173.07:44:15.35#ibcon#wrote, iclass 17, count 2 2006.173.07:44:15.35#ibcon#about to read 3, iclass 17, count 2 2006.173.07:44:15.38#ibcon#read 3, iclass 17, count 2 2006.173.07:44:15.38#ibcon#about to read 4, iclass 17, count 2 2006.173.07:44:15.38#ibcon#read 4, iclass 17, count 2 2006.173.07:44:15.38#ibcon#about to read 5, iclass 17, count 2 2006.173.07:44:15.38#ibcon#read 5, iclass 17, count 2 2006.173.07:44:15.38#ibcon#about to read 6, iclass 17, count 2 2006.173.07:44:15.38#ibcon#read 6, iclass 17, count 2 2006.173.07:44:15.38#ibcon#end of sib2, iclass 17, count 2 2006.173.07:44:15.38#ibcon#*after write, iclass 17, count 2 2006.173.07:44:15.38#ibcon#*before return 0, iclass 17, count 2 2006.173.07:44:15.38#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.07:44:15.38#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.07:44:15.38#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.07:44:15.38#ibcon#ireg 7 cls_cnt 0 2006.173.07:44:15.38#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.07:44:15.50#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.07:44:15.50#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.07:44:15.50#ibcon#enter wrdev, iclass 17, count 0 2006.173.07:44:15.50#ibcon#first serial, iclass 17, count 0 2006.173.07:44:15.50#ibcon#enter sib2, iclass 17, count 0 2006.173.07:44:15.50#ibcon#flushed, iclass 17, count 0 2006.173.07:44:15.50#ibcon#about to write, iclass 17, count 0 2006.173.07:44:15.50#ibcon#wrote, iclass 17, count 0 2006.173.07:44:15.50#ibcon#about to read 3, iclass 17, count 0 2006.173.07:44:15.52#ibcon#read 3, iclass 17, count 0 2006.173.07:44:15.52#ibcon#about to read 4, iclass 17, count 0 2006.173.07:44:15.52#ibcon#read 4, iclass 17, count 0 2006.173.07:44:15.52#ibcon#about to read 5, iclass 17, count 0 2006.173.07:44:15.52#ibcon#read 5, iclass 17, count 0 2006.173.07:44:15.52#ibcon#about to read 6, iclass 17, count 0 2006.173.07:44:15.52#ibcon#read 6, iclass 17, count 0 2006.173.07:44:15.52#ibcon#end of sib2, iclass 17, count 0 2006.173.07:44:15.52#ibcon#*mode == 0, iclass 17, count 0 2006.173.07:44:15.52#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.07:44:15.52#ibcon#[25=USB\r\n] 2006.173.07:44:15.52#ibcon#*before write, iclass 17, count 0 2006.173.07:44:15.52#ibcon#enter sib2, iclass 17, count 0 2006.173.07:44:15.52#ibcon#flushed, iclass 17, count 0 2006.173.07:44:15.52#ibcon#about to write, iclass 17, count 0 2006.173.07:44:15.52#ibcon#wrote, iclass 17, count 0 2006.173.07:44:15.52#ibcon#about to read 3, iclass 17, count 0 2006.173.07:44:15.55#ibcon#read 3, iclass 17, count 0 2006.173.07:44:15.55#ibcon#about to read 4, iclass 17, count 0 2006.173.07:44:15.55#ibcon#read 4, iclass 17, count 0 2006.173.07:44:15.55#ibcon#about to read 5, iclass 17, count 0 2006.173.07:44:15.55#ibcon#read 5, iclass 17, count 0 2006.173.07:44:15.55#ibcon#about to read 6, iclass 17, count 0 2006.173.07:44:15.55#ibcon#read 6, iclass 17, count 0 2006.173.07:44:15.55#ibcon#end of sib2, iclass 17, count 0 2006.173.07:44:15.55#ibcon#*after write, iclass 17, count 0 2006.173.07:44:15.55#ibcon#*before return 0, iclass 17, count 0 2006.173.07:44:15.55#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.07:44:15.55#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.07:44:15.55#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.07:44:15.55#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.07:44:15.55$vck44/valo=5,734.99 2006.173.07:44:15.55#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.07:44:15.55#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.07:44:15.55#ibcon#ireg 17 cls_cnt 0 2006.173.07:44:15.55#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.07:44:15.55#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.07:44:15.55#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.07:44:15.55#ibcon#enter wrdev, iclass 19, count 0 2006.173.07:44:15.55#ibcon#first serial, iclass 19, count 0 2006.173.07:44:15.55#ibcon#enter sib2, iclass 19, count 0 2006.173.07:44:15.55#ibcon#flushed, iclass 19, count 0 2006.173.07:44:15.55#ibcon#about to write, iclass 19, count 0 2006.173.07:44:15.55#ibcon#wrote, iclass 19, count 0 2006.173.07:44:15.55#ibcon#about to read 3, iclass 19, count 0 2006.173.07:44:15.57#ibcon#read 3, iclass 19, count 0 2006.173.07:44:15.57#ibcon#about to read 4, iclass 19, count 0 2006.173.07:44:15.57#ibcon#read 4, iclass 19, count 0 2006.173.07:44:15.57#ibcon#about to read 5, iclass 19, count 0 2006.173.07:44:15.57#ibcon#read 5, iclass 19, count 0 2006.173.07:44:15.57#ibcon#about to read 6, iclass 19, count 0 2006.173.07:44:15.57#ibcon#read 6, iclass 19, count 0 2006.173.07:44:15.57#ibcon#end of sib2, iclass 19, count 0 2006.173.07:44:15.57#ibcon#*mode == 0, iclass 19, count 0 2006.173.07:44:15.57#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.07:44:15.57#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.07:44:15.57#ibcon#*before write, iclass 19, count 0 2006.173.07:44:15.57#ibcon#enter sib2, iclass 19, count 0 2006.173.07:44:15.57#ibcon#flushed, iclass 19, count 0 2006.173.07:44:15.57#ibcon#about to write, iclass 19, count 0 2006.173.07:44:15.57#ibcon#wrote, iclass 19, count 0 2006.173.07:44:15.57#ibcon#about to read 3, iclass 19, count 0 2006.173.07:44:15.61#ibcon#read 3, iclass 19, count 0 2006.173.07:44:15.61#ibcon#about to read 4, iclass 19, count 0 2006.173.07:44:15.61#ibcon#read 4, iclass 19, count 0 2006.173.07:44:15.61#ibcon#about to read 5, iclass 19, count 0 2006.173.07:44:15.61#ibcon#read 5, iclass 19, count 0 2006.173.07:44:15.61#ibcon#about to read 6, iclass 19, count 0 2006.173.07:44:15.61#ibcon#read 6, iclass 19, count 0 2006.173.07:44:15.61#ibcon#end of sib2, iclass 19, count 0 2006.173.07:44:15.61#ibcon#*after write, iclass 19, count 0 2006.173.07:44:15.61#ibcon#*before return 0, iclass 19, count 0 2006.173.07:44:15.61#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.07:44:15.61#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.07:44:15.61#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.07:44:15.61#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.07:44:15.61$vck44/va=5,4 2006.173.07:44:15.61#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.07:44:15.61#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.07:44:15.61#ibcon#ireg 11 cls_cnt 2 2006.173.07:44:15.61#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.07:44:15.67#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.07:44:15.67#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.07:44:15.67#ibcon#enter wrdev, iclass 21, count 2 2006.173.07:44:15.67#ibcon#first serial, iclass 21, count 2 2006.173.07:44:15.67#ibcon#enter sib2, iclass 21, count 2 2006.173.07:44:15.67#ibcon#flushed, iclass 21, count 2 2006.173.07:44:15.67#ibcon#about to write, iclass 21, count 2 2006.173.07:44:15.67#ibcon#wrote, iclass 21, count 2 2006.173.07:44:15.67#ibcon#about to read 3, iclass 21, count 2 2006.173.07:44:15.69#ibcon#read 3, iclass 21, count 2 2006.173.07:44:15.69#ibcon#about to read 4, iclass 21, count 2 2006.173.07:44:15.69#ibcon#read 4, iclass 21, count 2 2006.173.07:44:15.69#ibcon#about to read 5, iclass 21, count 2 2006.173.07:44:15.69#ibcon#read 5, iclass 21, count 2 2006.173.07:44:15.69#ibcon#about to read 6, iclass 21, count 2 2006.173.07:44:15.69#ibcon#read 6, iclass 21, count 2 2006.173.07:44:15.69#ibcon#end of sib2, iclass 21, count 2 2006.173.07:44:15.69#ibcon#*mode == 0, iclass 21, count 2 2006.173.07:44:15.69#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.07:44:15.69#ibcon#[25=AT05-04\r\n] 2006.173.07:44:15.69#ibcon#*before write, iclass 21, count 2 2006.173.07:44:15.69#ibcon#enter sib2, iclass 21, count 2 2006.173.07:44:15.69#ibcon#flushed, iclass 21, count 2 2006.173.07:44:15.69#ibcon#about to write, iclass 21, count 2 2006.173.07:44:15.69#ibcon#wrote, iclass 21, count 2 2006.173.07:44:15.69#ibcon#about to read 3, iclass 21, count 2 2006.173.07:44:15.72#ibcon#read 3, iclass 21, count 2 2006.173.07:44:15.72#ibcon#about to read 4, iclass 21, count 2 2006.173.07:44:15.72#ibcon#read 4, iclass 21, count 2 2006.173.07:44:15.72#ibcon#about to read 5, iclass 21, count 2 2006.173.07:44:15.72#ibcon#read 5, iclass 21, count 2 2006.173.07:44:15.72#ibcon#about to read 6, iclass 21, count 2 2006.173.07:44:15.72#ibcon#read 6, iclass 21, count 2 2006.173.07:44:15.72#ibcon#end of sib2, iclass 21, count 2 2006.173.07:44:15.72#ibcon#*after write, iclass 21, count 2 2006.173.07:44:15.72#ibcon#*before return 0, iclass 21, count 2 2006.173.07:44:15.72#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.07:44:15.72#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.07:44:15.72#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.07:44:15.72#ibcon#ireg 7 cls_cnt 0 2006.173.07:44:15.72#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.07:44:15.84#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.07:44:15.84#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.07:44:15.84#ibcon#enter wrdev, iclass 21, count 0 2006.173.07:44:15.84#ibcon#first serial, iclass 21, count 0 2006.173.07:44:15.84#ibcon#enter sib2, iclass 21, count 0 2006.173.07:44:15.84#ibcon#flushed, iclass 21, count 0 2006.173.07:44:15.84#ibcon#about to write, iclass 21, count 0 2006.173.07:44:15.84#ibcon#wrote, iclass 21, count 0 2006.173.07:44:15.84#ibcon#about to read 3, iclass 21, count 0 2006.173.07:44:15.86#ibcon#read 3, iclass 21, count 0 2006.173.07:44:15.86#ibcon#about to read 4, iclass 21, count 0 2006.173.07:44:15.86#ibcon#read 4, iclass 21, count 0 2006.173.07:44:15.86#ibcon#about to read 5, iclass 21, count 0 2006.173.07:44:15.86#ibcon#read 5, iclass 21, count 0 2006.173.07:44:15.86#ibcon#about to read 6, iclass 21, count 0 2006.173.07:44:15.86#ibcon#read 6, iclass 21, count 0 2006.173.07:44:15.86#ibcon#end of sib2, iclass 21, count 0 2006.173.07:44:15.86#ibcon#*mode == 0, iclass 21, count 0 2006.173.07:44:15.86#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.07:44:15.86#ibcon#[25=USB\r\n] 2006.173.07:44:15.86#ibcon#*before write, iclass 21, count 0 2006.173.07:44:15.86#ibcon#enter sib2, iclass 21, count 0 2006.173.07:44:15.86#ibcon#flushed, iclass 21, count 0 2006.173.07:44:15.86#ibcon#about to write, iclass 21, count 0 2006.173.07:44:15.86#ibcon#wrote, iclass 21, count 0 2006.173.07:44:15.86#ibcon#about to read 3, iclass 21, count 0 2006.173.07:44:15.89#ibcon#read 3, iclass 21, count 0 2006.173.07:44:15.89#ibcon#about to read 4, iclass 21, count 0 2006.173.07:44:15.89#ibcon#read 4, iclass 21, count 0 2006.173.07:44:15.89#ibcon#about to read 5, iclass 21, count 0 2006.173.07:44:15.89#ibcon#read 5, iclass 21, count 0 2006.173.07:44:15.89#ibcon#about to read 6, iclass 21, count 0 2006.173.07:44:15.89#ibcon#read 6, iclass 21, count 0 2006.173.07:44:15.89#ibcon#end of sib2, iclass 21, count 0 2006.173.07:44:15.89#ibcon#*after write, iclass 21, count 0 2006.173.07:44:15.89#ibcon#*before return 0, iclass 21, count 0 2006.173.07:44:15.89#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.07:44:15.89#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.07:44:15.89#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.07:44:15.89#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.07:44:15.89$vck44/valo=6,814.99 2006.173.07:44:15.89#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.07:44:15.89#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.07:44:15.89#ibcon#ireg 17 cls_cnt 0 2006.173.07:44:15.89#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.07:44:15.89#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.07:44:15.89#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.07:44:15.89#ibcon#enter wrdev, iclass 23, count 0 2006.173.07:44:15.89#ibcon#first serial, iclass 23, count 0 2006.173.07:44:15.89#ibcon#enter sib2, iclass 23, count 0 2006.173.07:44:15.89#ibcon#flushed, iclass 23, count 0 2006.173.07:44:15.89#ibcon#about to write, iclass 23, count 0 2006.173.07:44:15.89#ibcon#wrote, iclass 23, count 0 2006.173.07:44:15.89#ibcon#about to read 3, iclass 23, count 0 2006.173.07:44:15.91#ibcon#read 3, iclass 23, count 0 2006.173.07:44:15.91#ibcon#about to read 4, iclass 23, count 0 2006.173.07:44:15.91#ibcon#read 4, iclass 23, count 0 2006.173.07:44:15.91#ibcon#about to read 5, iclass 23, count 0 2006.173.07:44:15.91#ibcon#read 5, iclass 23, count 0 2006.173.07:44:15.91#ibcon#about to read 6, iclass 23, count 0 2006.173.07:44:15.91#ibcon#read 6, iclass 23, count 0 2006.173.07:44:15.91#ibcon#end of sib2, iclass 23, count 0 2006.173.07:44:15.91#ibcon#*mode == 0, iclass 23, count 0 2006.173.07:44:15.91#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.07:44:15.91#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.07:44:15.91#ibcon#*before write, iclass 23, count 0 2006.173.07:44:15.91#ibcon#enter sib2, iclass 23, count 0 2006.173.07:44:15.91#ibcon#flushed, iclass 23, count 0 2006.173.07:44:15.91#ibcon#about to write, iclass 23, count 0 2006.173.07:44:15.91#ibcon#wrote, iclass 23, count 0 2006.173.07:44:15.91#ibcon#about to read 3, iclass 23, count 0 2006.173.07:44:15.95#ibcon#read 3, iclass 23, count 0 2006.173.07:44:15.95#ibcon#about to read 4, iclass 23, count 0 2006.173.07:44:15.95#ibcon#read 4, iclass 23, count 0 2006.173.07:44:15.95#ibcon#about to read 5, iclass 23, count 0 2006.173.07:44:15.95#ibcon#read 5, iclass 23, count 0 2006.173.07:44:15.95#ibcon#about to read 6, iclass 23, count 0 2006.173.07:44:15.95#ibcon#read 6, iclass 23, count 0 2006.173.07:44:15.95#ibcon#end of sib2, iclass 23, count 0 2006.173.07:44:15.95#ibcon#*after write, iclass 23, count 0 2006.173.07:44:15.95#ibcon#*before return 0, iclass 23, count 0 2006.173.07:44:15.95#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.07:44:15.95#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.07:44:15.95#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.07:44:15.95#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.07:44:15.95$vck44/va=6,3 2006.173.07:44:15.95#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.07:44:15.95#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.07:44:15.95#ibcon#ireg 11 cls_cnt 2 2006.173.07:44:15.95#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.07:44:16.01#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.07:44:16.01#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.07:44:16.01#ibcon#enter wrdev, iclass 25, count 2 2006.173.07:44:16.01#ibcon#first serial, iclass 25, count 2 2006.173.07:44:16.01#ibcon#enter sib2, iclass 25, count 2 2006.173.07:44:16.01#ibcon#flushed, iclass 25, count 2 2006.173.07:44:16.01#ibcon#about to write, iclass 25, count 2 2006.173.07:44:16.01#ibcon#wrote, iclass 25, count 2 2006.173.07:44:16.01#ibcon#about to read 3, iclass 25, count 2 2006.173.07:44:16.03#ibcon#read 3, iclass 25, count 2 2006.173.07:44:16.03#ibcon#about to read 4, iclass 25, count 2 2006.173.07:44:16.03#ibcon#read 4, iclass 25, count 2 2006.173.07:44:16.03#ibcon#about to read 5, iclass 25, count 2 2006.173.07:44:16.03#ibcon#read 5, iclass 25, count 2 2006.173.07:44:16.03#ibcon#about to read 6, iclass 25, count 2 2006.173.07:44:16.03#ibcon#read 6, iclass 25, count 2 2006.173.07:44:16.03#ibcon#end of sib2, iclass 25, count 2 2006.173.07:44:16.03#ibcon#*mode == 0, iclass 25, count 2 2006.173.07:44:16.03#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.07:44:16.03#ibcon#[25=AT06-03\r\n] 2006.173.07:44:16.03#ibcon#*before write, iclass 25, count 2 2006.173.07:44:16.03#ibcon#enter sib2, iclass 25, count 2 2006.173.07:44:16.03#ibcon#flushed, iclass 25, count 2 2006.173.07:44:16.03#ibcon#about to write, iclass 25, count 2 2006.173.07:44:16.03#ibcon#wrote, iclass 25, count 2 2006.173.07:44:16.03#ibcon#about to read 3, iclass 25, count 2 2006.173.07:44:16.06#ibcon#read 3, iclass 25, count 2 2006.173.07:44:16.06#ibcon#about to read 4, iclass 25, count 2 2006.173.07:44:16.06#ibcon#read 4, iclass 25, count 2 2006.173.07:44:16.06#ibcon#about to read 5, iclass 25, count 2 2006.173.07:44:16.06#ibcon#read 5, iclass 25, count 2 2006.173.07:44:16.06#ibcon#about to read 6, iclass 25, count 2 2006.173.07:44:16.06#ibcon#read 6, iclass 25, count 2 2006.173.07:44:16.06#ibcon#end of sib2, iclass 25, count 2 2006.173.07:44:16.06#ibcon#*after write, iclass 25, count 2 2006.173.07:44:16.06#ibcon#*before return 0, iclass 25, count 2 2006.173.07:44:16.06#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.07:44:16.06#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.07:44:16.06#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.07:44:16.06#ibcon#ireg 7 cls_cnt 0 2006.173.07:44:16.06#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.07:44:16.18#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.07:44:16.18#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.07:44:16.18#ibcon#enter wrdev, iclass 25, count 0 2006.173.07:44:16.18#ibcon#first serial, iclass 25, count 0 2006.173.07:44:16.18#ibcon#enter sib2, iclass 25, count 0 2006.173.07:44:16.18#ibcon#flushed, iclass 25, count 0 2006.173.07:44:16.18#ibcon#about to write, iclass 25, count 0 2006.173.07:44:16.18#ibcon#wrote, iclass 25, count 0 2006.173.07:44:16.18#ibcon#about to read 3, iclass 25, count 0 2006.173.07:44:16.20#ibcon#read 3, iclass 25, count 0 2006.173.07:44:16.20#ibcon#about to read 4, iclass 25, count 0 2006.173.07:44:16.20#ibcon#read 4, iclass 25, count 0 2006.173.07:44:16.20#ibcon#about to read 5, iclass 25, count 0 2006.173.07:44:16.20#ibcon#read 5, iclass 25, count 0 2006.173.07:44:16.20#ibcon#about to read 6, iclass 25, count 0 2006.173.07:44:16.20#ibcon#read 6, iclass 25, count 0 2006.173.07:44:16.20#ibcon#end of sib2, iclass 25, count 0 2006.173.07:44:16.20#ibcon#*mode == 0, iclass 25, count 0 2006.173.07:44:16.20#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.07:44:16.20#ibcon#[25=USB\r\n] 2006.173.07:44:16.20#ibcon#*before write, iclass 25, count 0 2006.173.07:44:16.20#ibcon#enter sib2, iclass 25, count 0 2006.173.07:44:16.20#ibcon#flushed, iclass 25, count 0 2006.173.07:44:16.20#ibcon#about to write, iclass 25, count 0 2006.173.07:44:16.20#ibcon#wrote, iclass 25, count 0 2006.173.07:44:16.20#ibcon#about to read 3, iclass 25, count 0 2006.173.07:44:16.23#ibcon#read 3, iclass 25, count 0 2006.173.07:44:16.23#ibcon#about to read 4, iclass 25, count 0 2006.173.07:44:16.23#ibcon#read 4, iclass 25, count 0 2006.173.07:44:16.23#ibcon#about to read 5, iclass 25, count 0 2006.173.07:44:16.23#ibcon#read 5, iclass 25, count 0 2006.173.07:44:16.23#ibcon#about to read 6, iclass 25, count 0 2006.173.07:44:16.23#ibcon#read 6, iclass 25, count 0 2006.173.07:44:16.23#ibcon#end of sib2, iclass 25, count 0 2006.173.07:44:16.23#ibcon#*after write, iclass 25, count 0 2006.173.07:44:16.23#ibcon#*before return 0, iclass 25, count 0 2006.173.07:44:16.23#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.07:44:16.23#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.07:44:16.23#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.07:44:16.23#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.07:44:16.23$vck44/valo=7,864.99 2006.173.07:44:16.23#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.07:44:16.23#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.07:44:16.23#ibcon#ireg 17 cls_cnt 0 2006.173.07:44:16.23#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.07:44:16.23#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.07:44:16.23#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.07:44:16.23#ibcon#enter wrdev, iclass 27, count 0 2006.173.07:44:16.23#ibcon#first serial, iclass 27, count 0 2006.173.07:44:16.23#ibcon#enter sib2, iclass 27, count 0 2006.173.07:44:16.23#ibcon#flushed, iclass 27, count 0 2006.173.07:44:16.23#ibcon#about to write, iclass 27, count 0 2006.173.07:44:16.23#ibcon#wrote, iclass 27, count 0 2006.173.07:44:16.23#ibcon#about to read 3, iclass 27, count 0 2006.173.07:44:16.25#ibcon#read 3, iclass 27, count 0 2006.173.07:44:16.25#ibcon#about to read 4, iclass 27, count 0 2006.173.07:44:16.25#ibcon#read 4, iclass 27, count 0 2006.173.07:44:16.25#ibcon#about to read 5, iclass 27, count 0 2006.173.07:44:16.25#ibcon#read 5, iclass 27, count 0 2006.173.07:44:16.25#ibcon#about to read 6, iclass 27, count 0 2006.173.07:44:16.25#ibcon#read 6, iclass 27, count 0 2006.173.07:44:16.25#ibcon#end of sib2, iclass 27, count 0 2006.173.07:44:16.25#ibcon#*mode == 0, iclass 27, count 0 2006.173.07:44:16.25#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.07:44:16.25#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.07:44:16.25#ibcon#*before write, iclass 27, count 0 2006.173.07:44:16.25#ibcon#enter sib2, iclass 27, count 0 2006.173.07:44:16.25#ibcon#flushed, iclass 27, count 0 2006.173.07:44:16.25#ibcon#about to write, iclass 27, count 0 2006.173.07:44:16.25#ibcon#wrote, iclass 27, count 0 2006.173.07:44:16.25#ibcon#about to read 3, iclass 27, count 0 2006.173.07:44:16.29#ibcon#read 3, iclass 27, count 0 2006.173.07:44:16.29#ibcon#about to read 4, iclass 27, count 0 2006.173.07:44:16.29#ibcon#read 4, iclass 27, count 0 2006.173.07:44:16.29#ibcon#about to read 5, iclass 27, count 0 2006.173.07:44:16.29#ibcon#read 5, iclass 27, count 0 2006.173.07:44:16.29#ibcon#about to read 6, iclass 27, count 0 2006.173.07:44:16.29#ibcon#read 6, iclass 27, count 0 2006.173.07:44:16.29#ibcon#end of sib2, iclass 27, count 0 2006.173.07:44:16.29#ibcon#*after write, iclass 27, count 0 2006.173.07:44:16.29#ibcon#*before return 0, iclass 27, count 0 2006.173.07:44:16.29#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.07:44:16.29#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.07:44:16.29#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.07:44:16.29#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.07:44:16.29$vck44/va=7,4 2006.173.07:44:16.29#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.07:44:16.29#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.07:44:16.29#ibcon#ireg 11 cls_cnt 2 2006.173.07:44:16.29#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.07:44:16.35#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.07:44:16.35#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.07:44:16.35#ibcon#enter wrdev, iclass 29, count 2 2006.173.07:44:16.35#ibcon#first serial, iclass 29, count 2 2006.173.07:44:16.35#ibcon#enter sib2, iclass 29, count 2 2006.173.07:44:16.35#ibcon#flushed, iclass 29, count 2 2006.173.07:44:16.35#ibcon#about to write, iclass 29, count 2 2006.173.07:44:16.35#ibcon#wrote, iclass 29, count 2 2006.173.07:44:16.35#ibcon#about to read 3, iclass 29, count 2 2006.173.07:44:16.37#ibcon#read 3, iclass 29, count 2 2006.173.07:44:16.37#ibcon#about to read 4, iclass 29, count 2 2006.173.07:44:16.37#ibcon#read 4, iclass 29, count 2 2006.173.07:44:16.37#ibcon#about to read 5, iclass 29, count 2 2006.173.07:44:16.37#ibcon#read 5, iclass 29, count 2 2006.173.07:44:16.37#ibcon#about to read 6, iclass 29, count 2 2006.173.07:44:16.37#ibcon#read 6, iclass 29, count 2 2006.173.07:44:16.37#ibcon#end of sib2, iclass 29, count 2 2006.173.07:44:16.37#ibcon#*mode == 0, iclass 29, count 2 2006.173.07:44:16.37#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.07:44:16.37#ibcon#[25=AT07-04\r\n] 2006.173.07:44:16.37#ibcon#*before write, iclass 29, count 2 2006.173.07:44:16.37#ibcon#enter sib2, iclass 29, count 2 2006.173.07:44:16.37#ibcon#flushed, iclass 29, count 2 2006.173.07:44:16.37#ibcon#about to write, iclass 29, count 2 2006.173.07:44:16.37#ibcon#wrote, iclass 29, count 2 2006.173.07:44:16.37#ibcon#about to read 3, iclass 29, count 2 2006.173.07:44:16.40#ibcon#read 3, iclass 29, count 2 2006.173.07:44:16.40#ibcon#about to read 4, iclass 29, count 2 2006.173.07:44:16.40#ibcon#read 4, iclass 29, count 2 2006.173.07:44:16.40#ibcon#about to read 5, iclass 29, count 2 2006.173.07:44:16.40#ibcon#read 5, iclass 29, count 2 2006.173.07:44:16.40#ibcon#about to read 6, iclass 29, count 2 2006.173.07:44:16.40#ibcon#read 6, iclass 29, count 2 2006.173.07:44:16.40#ibcon#end of sib2, iclass 29, count 2 2006.173.07:44:16.40#ibcon#*after write, iclass 29, count 2 2006.173.07:44:16.40#ibcon#*before return 0, iclass 29, count 2 2006.173.07:44:16.40#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.07:44:16.40#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.07:44:16.40#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.07:44:16.40#ibcon#ireg 7 cls_cnt 0 2006.173.07:44:16.40#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.07:44:16.52#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.07:44:16.52#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.07:44:16.52#ibcon#enter wrdev, iclass 29, count 0 2006.173.07:44:16.52#ibcon#first serial, iclass 29, count 0 2006.173.07:44:16.52#ibcon#enter sib2, iclass 29, count 0 2006.173.07:44:16.52#ibcon#flushed, iclass 29, count 0 2006.173.07:44:16.52#ibcon#about to write, iclass 29, count 0 2006.173.07:44:16.52#ibcon#wrote, iclass 29, count 0 2006.173.07:44:16.52#ibcon#about to read 3, iclass 29, count 0 2006.173.07:44:16.54#ibcon#read 3, iclass 29, count 0 2006.173.07:44:16.54#ibcon#about to read 4, iclass 29, count 0 2006.173.07:44:16.54#ibcon#read 4, iclass 29, count 0 2006.173.07:44:16.54#ibcon#about to read 5, iclass 29, count 0 2006.173.07:44:16.54#ibcon#read 5, iclass 29, count 0 2006.173.07:44:16.54#ibcon#about to read 6, iclass 29, count 0 2006.173.07:44:16.54#ibcon#read 6, iclass 29, count 0 2006.173.07:44:16.54#ibcon#end of sib2, iclass 29, count 0 2006.173.07:44:16.54#ibcon#*mode == 0, iclass 29, count 0 2006.173.07:44:16.54#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.07:44:16.54#ibcon#[25=USB\r\n] 2006.173.07:44:16.54#ibcon#*before write, iclass 29, count 0 2006.173.07:44:16.54#ibcon#enter sib2, iclass 29, count 0 2006.173.07:44:16.54#ibcon#flushed, iclass 29, count 0 2006.173.07:44:16.54#ibcon#about to write, iclass 29, count 0 2006.173.07:44:16.54#ibcon#wrote, iclass 29, count 0 2006.173.07:44:16.54#ibcon#about to read 3, iclass 29, count 0 2006.173.07:44:16.57#ibcon#read 3, iclass 29, count 0 2006.173.07:44:16.57#ibcon#about to read 4, iclass 29, count 0 2006.173.07:44:16.57#ibcon#read 4, iclass 29, count 0 2006.173.07:44:16.57#ibcon#about to read 5, iclass 29, count 0 2006.173.07:44:16.57#ibcon#read 5, iclass 29, count 0 2006.173.07:44:16.57#ibcon#about to read 6, iclass 29, count 0 2006.173.07:44:16.57#ibcon#read 6, iclass 29, count 0 2006.173.07:44:16.57#ibcon#end of sib2, iclass 29, count 0 2006.173.07:44:16.57#ibcon#*after write, iclass 29, count 0 2006.173.07:44:16.57#ibcon#*before return 0, iclass 29, count 0 2006.173.07:44:16.57#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.07:44:16.57#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.07:44:16.57#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.07:44:16.57#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.07:44:16.57$vck44/valo=8,884.99 2006.173.07:44:16.57#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.07:44:16.57#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.07:44:16.57#ibcon#ireg 17 cls_cnt 0 2006.173.07:44:16.57#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.07:44:16.57#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.07:44:16.57#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.07:44:16.57#ibcon#enter wrdev, iclass 31, count 0 2006.173.07:44:16.57#ibcon#first serial, iclass 31, count 0 2006.173.07:44:16.57#ibcon#enter sib2, iclass 31, count 0 2006.173.07:44:16.57#ibcon#flushed, iclass 31, count 0 2006.173.07:44:16.57#ibcon#about to write, iclass 31, count 0 2006.173.07:44:16.57#ibcon#wrote, iclass 31, count 0 2006.173.07:44:16.57#ibcon#about to read 3, iclass 31, count 0 2006.173.07:44:16.59#ibcon#read 3, iclass 31, count 0 2006.173.07:44:16.59#ibcon#about to read 4, iclass 31, count 0 2006.173.07:44:16.59#ibcon#read 4, iclass 31, count 0 2006.173.07:44:16.59#ibcon#about to read 5, iclass 31, count 0 2006.173.07:44:16.59#ibcon#read 5, iclass 31, count 0 2006.173.07:44:16.59#ibcon#about to read 6, iclass 31, count 0 2006.173.07:44:16.59#ibcon#read 6, iclass 31, count 0 2006.173.07:44:16.59#ibcon#end of sib2, iclass 31, count 0 2006.173.07:44:16.59#ibcon#*mode == 0, iclass 31, count 0 2006.173.07:44:16.59#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.07:44:16.59#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.07:44:16.59#ibcon#*before write, iclass 31, count 0 2006.173.07:44:16.59#ibcon#enter sib2, iclass 31, count 0 2006.173.07:44:16.59#ibcon#flushed, iclass 31, count 0 2006.173.07:44:16.59#ibcon#about to write, iclass 31, count 0 2006.173.07:44:16.59#ibcon#wrote, iclass 31, count 0 2006.173.07:44:16.59#ibcon#about to read 3, iclass 31, count 0 2006.173.07:44:16.63#ibcon#read 3, iclass 31, count 0 2006.173.07:44:16.63#ibcon#about to read 4, iclass 31, count 0 2006.173.07:44:16.63#ibcon#read 4, iclass 31, count 0 2006.173.07:44:16.63#ibcon#about to read 5, iclass 31, count 0 2006.173.07:44:16.63#ibcon#read 5, iclass 31, count 0 2006.173.07:44:16.63#ibcon#about to read 6, iclass 31, count 0 2006.173.07:44:16.63#ibcon#read 6, iclass 31, count 0 2006.173.07:44:16.63#ibcon#end of sib2, iclass 31, count 0 2006.173.07:44:16.63#ibcon#*after write, iclass 31, count 0 2006.173.07:44:16.63#ibcon#*before return 0, iclass 31, count 0 2006.173.07:44:16.63#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.07:44:16.63#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.07:44:16.63#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.07:44:16.63#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.07:44:16.63$vck44/va=8,4 2006.173.07:44:16.63#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.173.07:44:16.63#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.173.07:44:16.63#ibcon#ireg 11 cls_cnt 2 2006.173.07:44:16.63#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.07:44:16.69#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.07:44:16.69#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.07:44:16.69#ibcon#enter wrdev, iclass 33, count 2 2006.173.07:44:16.69#ibcon#first serial, iclass 33, count 2 2006.173.07:44:16.69#ibcon#enter sib2, iclass 33, count 2 2006.173.07:44:16.69#ibcon#flushed, iclass 33, count 2 2006.173.07:44:16.69#ibcon#about to write, iclass 33, count 2 2006.173.07:44:16.69#ibcon#wrote, iclass 33, count 2 2006.173.07:44:16.69#ibcon#about to read 3, iclass 33, count 2 2006.173.07:44:16.71#ibcon#read 3, iclass 33, count 2 2006.173.07:44:16.71#ibcon#about to read 4, iclass 33, count 2 2006.173.07:44:16.71#ibcon#read 4, iclass 33, count 2 2006.173.07:44:16.71#ibcon#about to read 5, iclass 33, count 2 2006.173.07:44:16.71#ibcon#read 5, iclass 33, count 2 2006.173.07:44:16.71#ibcon#about to read 6, iclass 33, count 2 2006.173.07:44:16.71#ibcon#read 6, iclass 33, count 2 2006.173.07:44:16.71#ibcon#end of sib2, iclass 33, count 2 2006.173.07:44:16.71#ibcon#*mode == 0, iclass 33, count 2 2006.173.07:44:16.71#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.173.07:44:16.71#ibcon#[25=AT08-04\r\n] 2006.173.07:44:16.71#ibcon#*before write, iclass 33, count 2 2006.173.07:44:16.71#ibcon#enter sib2, iclass 33, count 2 2006.173.07:44:16.71#ibcon#flushed, iclass 33, count 2 2006.173.07:44:16.71#ibcon#about to write, iclass 33, count 2 2006.173.07:44:16.71#ibcon#wrote, iclass 33, count 2 2006.173.07:44:16.71#ibcon#about to read 3, iclass 33, count 2 2006.173.07:44:16.74#ibcon#read 3, iclass 33, count 2 2006.173.07:44:16.74#ibcon#about to read 4, iclass 33, count 2 2006.173.07:44:16.74#ibcon#read 4, iclass 33, count 2 2006.173.07:44:16.74#ibcon#about to read 5, iclass 33, count 2 2006.173.07:44:16.74#ibcon#read 5, iclass 33, count 2 2006.173.07:44:16.74#ibcon#about to read 6, iclass 33, count 2 2006.173.07:44:16.74#ibcon#read 6, iclass 33, count 2 2006.173.07:44:16.74#ibcon#end of sib2, iclass 33, count 2 2006.173.07:44:16.74#ibcon#*after write, iclass 33, count 2 2006.173.07:44:16.74#ibcon#*before return 0, iclass 33, count 2 2006.173.07:44:16.74#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.07:44:16.74#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.173.07:44:16.74#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.173.07:44:16.74#ibcon#ireg 7 cls_cnt 0 2006.173.07:44:16.74#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.07:44:16.86#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.07:44:16.86#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.07:44:16.86#ibcon#enter wrdev, iclass 33, count 0 2006.173.07:44:16.86#ibcon#first serial, iclass 33, count 0 2006.173.07:44:16.86#ibcon#enter sib2, iclass 33, count 0 2006.173.07:44:16.86#ibcon#flushed, iclass 33, count 0 2006.173.07:44:16.86#ibcon#about to write, iclass 33, count 0 2006.173.07:44:16.86#ibcon#wrote, iclass 33, count 0 2006.173.07:44:16.86#ibcon#about to read 3, iclass 33, count 0 2006.173.07:44:16.88#ibcon#read 3, iclass 33, count 0 2006.173.07:44:16.88#ibcon#about to read 4, iclass 33, count 0 2006.173.07:44:16.88#ibcon#read 4, iclass 33, count 0 2006.173.07:44:16.88#ibcon#about to read 5, iclass 33, count 0 2006.173.07:44:16.88#ibcon#read 5, iclass 33, count 0 2006.173.07:44:16.88#ibcon#about to read 6, iclass 33, count 0 2006.173.07:44:16.88#ibcon#read 6, iclass 33, count 0 2006.173.07:44:16.88#ibcon#end of sib2, iclass 33, count 0 2006.173.07:44:16.88#ibcon#*mode == 0, iclass 33, count 0 2006.173.07:44:16.88#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.07:44:16.88#ibcon#[25=USB\r\n] 2006.173.07:44:16.88#ibcon#*before write, iclass 33, count 0 2006.173.07:44:16.88#ibcon#enter sib2, iclass 33, count 0 2006.173.07:44:16.88#ibcon#flushed, iclass 33, count 0 2006.173.07:44:16.88#ibcon#about to write, iclass 33, count 0 2006.173.07:44:16.88#ibcon#wrote, iclass 33, count 0 2006.173.07:44:16.88#ibcon#about to read 3, iclass 33, count 0 2006.173.07:44:16.91#ibcon#read 3, iclass 33, count 0 2006.173.07:44:16.91#ibcon#about to read 4, iclass 33, count 0 2006.173.07:44:16.91#ibcon#read 4, iclass 33, count 0 2006.173.07:44:16.91#ibcon#about to read 5, iclass 33, count 0 2006.173.07:44:16.91#ibcon#read 5, iclass 33, count 0 2006.173.07:44:16.91#ibcon#about to read 6, iclass 33, count 0 2006.173.07:44:16.91#ibcon#read 6, iclass 33, count 0 2006.173.07:44:16.91#ibcon#end of sib2, iclass 33, count 0 2006.173.07:44:16.91#ibcon#*after write, iclass 33, count 0 2006.173.07:44:16.91#ibcon#*before return 0, iclass 33, count 0 2006.173.07:44:16.91#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.07:44:16.91#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.173.07:44:16.91#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.07:44:16.91#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.07:44:16.91$vck44/vblo=1,629.99 2006.173.07:44:16.91#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.07:44:16.91#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.07:44:16.91#ibcon#ireg 17 cls_cnt 0 2006.173.07:44:16.91#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.07:44:16.91#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.07:44:16.91#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.07:44:16.91#ibcon#enter wrdev, iclass 35, count 0 2006.173.07:44:16.91#ibcon#first serial, iclass 35, count 0 2006.173.07:44:16.91#ibcon#enter sib2, iclass 35, count 0 2006.173.07:44:16.91#ibcon#flushed, iclass 35, count 0 2006.173.07:44:16.91#ibcon#about to write, iclass 35, count 0 2006.173.07:44:16.91#ibcon#wrote, iclass 35, count 0 2006.173.07:44:16.91#ibcon#about to read 3, iclass 35, count 0 2006.173.07:44:16.93#ibcon#read 3, iclass 35, count 0 2006.173.07:44:16.93#ibcon#about to read 4, iclass 35, count 0 2006.173.07:44:16.93#ibcon#read 4, iclass 35, count 0 2006.173.07:44:16.93#ibcon#about to read 5, iclass 35, count 0 2006.173.07:44:16.93#ibcon#read 5, iclass 35, count 0 2006.173.07:44:16.93#ibcon#about to read 6, iclass 35, count 0 2006.173.07:44:16.93#ibcon#read 6, iclass 35, count 0 2006.173.07:44:16.93#ibcon#end of sib2, iclass 35, count 0 2006.173.07:44:16.93#ibcon#*mode == 0, iclass 35, count 0 2006.173.07:44:16.93#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.07:44:16.93#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.07:44:16.93#ibcon#*before write, iclass 35, count 0 2006.173.07:44:16.93#ibcon#enter sib2, iclass 35, count 0 2006.173.07:44:16.93#ibcon#flushed, iclass 35, count 0 2006.173.07:44:16.93#ibcon#about to write, iclass 35, count 0 2006.173.07:44:16.93#ibcon#wrote, iclass 35, count 0 2006.173.07:44:16.93#ibcon#about to read 3, iclass 35, count 0 2006.173.07:44:16.97#ibcon#read 3, iclass 35, count 0 2006.173.07:44:16.97#ibcon#about to read 4, iclass 35, count 0 2006.173.07:44:16.97#ibcon#read 4, iclass 35, count 0 2006.173.07:44:16.97#ibcon#about to read 5, iclass 35, count 0 2006.173.07:44:16.97#ibcon#read 5, iclass 35, count 0 2006.173.07:44:16.97#ibcon#about to read 6, iclass 35, count 0 2006.173.07:44:16.97#ibcon#read 6, iclass 35, count 0 2006.173.07:44:16.97#ibcon#end of sib2, iclass 35, count 0 2006.173.07:44:16.97#ibcon#*after write, iclass 35, count 0 2006.173.07:44:16.97#ibcon#*before return 0, iclass 35, count 0 2006.173.07:44:16.97#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.07:44:16.97#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.07:44:16.97#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.07:44:16.97#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.07:44:16.97$vck44/vb=1,4 2006.173.07:44:16.97#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.173.07:44:16.97#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.173.07:44:16.97#ibcon#ireg 11 cls_cnt 2 2006.173.07:44:16.97#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.07:44:16.97#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.07:44:16.97#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.07:44:16.97#ibcon#enter wrdev, iclass 37, count 2 2006.173.07:44:16.97#ibcon#first serial, iclass 37, count 2 2006.173.07:44:16.97#ibcon#enter sib2, iclass 37, count 2 2006.173.07:44:16.97#ibcon#flushed, iclass 37, count 2 2006.173.07:44:16.97#ibcon#about to write, iclass 37, count 2 2006.173.07:44:16.97#ibcon#wrote, iclass 37, count 2 2006.173.07:44:16.97#ibcon#about to read 3, iclass 37, count 2 2006.173.07:44:16.99#ibcon#read 3, iclass 37, count 2 2006.173.07:44:16.99#ibcon#about to read 4, iclass 37, count 2 2006.173.07:44:16.99#ibcon#read 4, iclass 37, count 2 2006.173.07:44:16.99#ibcon#about to read 5, iclass 37, count 2 2006.173.07:44:16.99#ibcon#read 5, iclass 37, count 2 2006.173.07:44:16.99#ibcon#about to read 6, iclass 37, count 2 2006.173.07:44:16.99#ibcon#read 6, iclass 37, count 2 2006.173.07:44:16.99#ibcon#end of sib2, iclass 37, count 2 2006.173.07:44:16.99#ibcon#*mode == 0, iclass 37, count 2 2006.173.07:44:16.99#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.173.07:44:16.99#ibcon#[27=AT01-04\r\n] 2006.173.07:44:16.99#ibcon#*before write, iclass 37, count 2 2006.173.07:44:16.99#ibcon#enter sib2, iclass 37, count 2 2006.173.07:44:16.99#ibcon#flushed, iclass 37, count 2 2006.173.07:44:16.99#ibcon#about to write, iclass 37, count 2 2006.173.07:44:16.99#ibcon#wrote, iclass 37, count 2 2006.173.07:44:16.99#ibcon#about to read 3, iclass 37, count 2 2006.173.07:44:17.02#ibcon#read 3, iclass 37, count 2 2006.173.07:44:17.02#ibcon#about to read 4, iclass 37, count 2 2006.173.07:44:17.02#ibcon#read 4, iclass 37, count 2 2006.173.07:44:17.02#ibcon#about to read 5, iclass 37, count 2 2006.173.07:44:17.02#ibcon#read 5, iclass 37, count 2 2006.173.07:44:17.02#ibcon#about to read 6, iclass 37, count 2 2006.173.07:44:17.02#ibcon#read 6, iclass 37, count 2 2006.173.07:44:17.02#ibcon#end of sib2, iclass 37, count 2 2006.173.07:44:17.02#ibcon#*after write, iclass 37, count 2 2006.173.07:44:17.02#ibcon#*before return 0, iclass 37, count 2 2006.173.07:44:17.02#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.07:44:17.02#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.173.07:44:17.02#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.173.07:44:17.02#ibcon#ireg 7 cls_cnt 0 2006.173.07:44:17.02#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.07:44:17.14#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.07:44:17.14#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.07:44:17.14#ibcon#enter wrdev, iclass 37, count 0 2006.173.07:44:17.14#ibcon#first serial, iclass 37, count 0 2006.173.07:44:17.14#ibcon#enter sib2, iclass 37, count 0 2006.173.07:44:17.14#ibcon#flushed, iclass 37, count 0 2006.173.07:44:17.14#ibcon#about to write, iclass 37, count 0 2006.173.07:44:17.14#ibcon#wrote, iclass 37, count 0 2006.173.07:44:17.14#ibcon#about to read 3, iclass 37, count 0 2006.173.07:44:17.16#ibcon#read 3, iclass 37, count 0 2006.173.07:44:17.16#ibcon#about to read 4, iclass 37, count 0 2006.173.07:44:17.16#ibcon#read 4, iclass 37, count 0 2006.173.07:44:17.16#ibcon#about to read 5, iclass 37, count 0 2006.173.07:44:17.16#ibcon#read 5, iclass 37, count 0 2006.173.07:44:17.16#ibcon#about to read 6, iclass 37, count 0 2006.173.07:44:17.16#ibcon#read 6, iclass 37, count 0 2006.173.07:44:17.16#ibcon#end of sib2, iclass 37, count 0 2006.173.07:44:17.16#ibcon#*mode == 0, iclass 37, count 0 2006.173.07:44:17.16#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.07:44:17.16#ibcon#[27=USB\r\n] 2006.173.07:44:17.16#ibcon#*before write, iclass 37, count 0 2006.173.07:44:17.16#ibcon#enter sib2, iclass 37, count 0 2006.173.07:44:17.16#ibcon#flushed, iclass 37, count 0 2006.173.07:44:17.16#ibcon#about to write, iclass 37, count 0 2006.173.07:44:17.16#ibcon#wrote, iclass 37, count 0 2006.173.07:44:17.16#ibcon#about to read 3, iclass 37, count 0 2006.173.07:44:17.19#ibcon#read 3, iclass 37, count 0 2006.173.07:44:17.19#ibcon#about to read 4, iclass 37, count 0 2006.173.07:44:17.19#ibcon#read 4, iclass 37, count 0 2006.173.07:44:17.19#ibcon#about to read 5, iclass 37, count 0 2006.173.07:44:17.19#ibcon#read 5, iclass 37, count 0 2006.173.07:44:17.19#ibcon#about to read 6, iclass 37, count 0 2006.173.07:44:17.19#ibcon#read 6, iclass 37, count 0 2006.173.07:44:17.19#ibcon#end of sib2, iclass 37, count 0 2006.173.07:44:17.19#ibcon#*after write, iclass 37, count 0 2006.173.07:44:17.19#ibcon#*before return 0, iclass 37, count 0 2006.173.07:44:17.19#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.07:44:17.19#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.173.07:44:17.19#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.07:44:17.19#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.07:44:17.19$vck44/vblo=2,634.99 2006.173.07:44:17.19#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.07:44:17.19#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.07:44:17.19#ibcon#ireg 17 cls_cnt 0 2006.173.07:44:17.19#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.07:44:17.19#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.07:44:17.19#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.07:44:17.19#ibcon#enter wrdev, iclass 39, count 0 2006.173.07:44:17.19#ibcon#first serial, iclass 39, count 0 2006.173.07:44:17.19#ibcon#enter sib2, iclass 39, count 0 2006.173.07:44:17.19#ibcon#flushed, iclass 39, count 0 2006.173.07:44:17.19#ibcon#about to write, iclass 39, count 0 2006.173.07:44:17.19#ibcon#wrote, iclass 39, count 0 2006.173.07:44:17.19#ibcon#about to read 3, iclass 39, count 0 2006.173.07:44:17.21#ibcon#read 3, iclass 39, count 0 2006.173.07:44:17.21#ibcon#about to read 4, iclass 39, count 0 2006.173.07:44:17.21#ibcon#read 4, iclass 39, count 0 2006.173.07:44:17.21#ibcon#about to read 5, iclass 39, count 0 2006.173.07:44:17.21#ibcon#read 5, iclass 39, count 0 2006.173.07:44:17.21#ibcon#about to read 6, iclass 39, count 0 2006.173.07:44:17.21#ibcon#read 6, iclass 39, count 0 2006.173.07:44:17.21#ibcon#end of sib2, iclass 39, count 0 2006.173.07:44:17.21#ibcon#*mode == 0, iclass 39, count 0 2006.173.07:44:17.21#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.07:44:17.21#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.07:44:17.21#ibcon#*before write, iclass 39, count 0 2006.173.07:44:17.21#ibcon#enter sib2, iclass 39, count 0 2006.173.07:44:17.21#ibcon#flushed, iclass 39, count 0 2006.173.07:44:17.21#ibcon#about to write, iclass 39, count 0 2006.173.07:44:17.21#ibcon#wrote, iclass 39, count 0 2006.173.07:44:17.21#ibcon#about to read 3, iclass 39, count 0 2006.173.07:44:17.25#ibcon#read 3, iclass 39, count 0 2006.173.07:44:17.25#ibcon#about to read 4, iclass 39, count 0 2006.173.07:44:17.25#ibcon#read 4, iclass 39, count 0 2006.173.07:44:17.25#ibcon#about to read 5, iclass 39, count 0 2006.173.07:44:17.25#ibcon#read 5, iclass 39, count 0 2006.173.07:44:17.25#ibcon#about to read 6, iclass 39, count 0 2006.173.07:44:17.25#ibcon#read 6, iclass 39, count 0 2006.173.07:44:17.25#ibcon#end of sib2, iclass 39, count 0 2006.173.07:44:17.25#ibcon#*after write, iclass 39, count 0 2006.173.07:44:17.25#ibcon#*before return 0, iclass 39, count 0 2006.173.07:44:17.25#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.07:44:17.25#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.07:44:17.25#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.07:44:17.25#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.07:44:17.25$vck44/vb=2,4 2006.173.07:44:17.25#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.07:44:17.25#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.07:44:17.25#ibcon#ireg 11 cls_cnt 2 2006.173.07:44:17.25#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.07:44:17.31#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.07:44:17.31#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.07:44:17.31#ibcon#enter wrdev, iclass 3, count 2 2006.173.07:44:17.31#ibcon#first serial, iclass 3, count 2 2006.173.07:44:17.31#ibcon#enter sib2, iclass 3, count 2 2006.173.07:44:17.31#ibcon#flushed, iclass 3, count 2 2006.173.07:44:17.31#ibcon#about to write, iclass 3, count 2 2006.173.07:44:17.31#ibcon#wrote, iclass 3, count 2 2006.173.07:44:17.31#ibcon#about to read 3, iclass 3, count 2 2006.173.07:44:17.33#ibcon#read 3, iclass 3, count 2 2006.173.07:44:17.33#ibcon#about to read 4, iclass 3, count 2 2006.173.07:44:17.33#ibcon#read 4, iclass 3, count 2 2006.173.07:44:17.33#ibcon#about to read 5, iclass 3, count 2 2006.173.07:44:17.33#ibcon#read 5, iclass 3, count 2 2006.173.07:44:17.33#ibcon#about to read 6, iclass 3, count 2 2006.173.07:44:17.33#ibcon#read 6, iclass 3, count 2 2006.173.07:44:17.33#ibcon#end of sib2, iclass 3, count 2 2006.173.07:44:17.33#ibcon#*mode == 0, iclass 3, count 2 2006.173.07:44:17.33#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.07:44:17.33#ibcon#[27=AT02-04\r\n] 2006.173.07:44:17.33#ibcon#*before write, iclass 3, count 2 2006.173.07:44:17.33#ibcon#enter sib2, iclass 3, count 2 2006.173.07:44:17.33#ibcon#flushed, iclass 3, count 2 2006.173.07:44:17.33#ibcon#about to write, iclass 3, count 2 2006.173.07:44:17.33#ibcon#wrote, iclass 3, count 2 2006.173.07:44:17.33#ibcon#about to read 3, iclass 3, count 2 2006.173.07:44:17.36#ibcon#read 3, iclass 3, count 2 2006.173.07:44:17.36#ibcon#about to read 4, iclass 3, count 2 2006.173.07:44:17.36#ibcon#read 4, iclass 3, count 2 2006.173.07:44:17.36#ibcon#about to read 5, iclass 3, count 2 2006.173.07:44:17.36#ibcon#read 5, iclass 3, count 2 2006.173.07:44:17.36#ibcon#about to read 6, iclass 3, count 2 2006.173.07:44:17.36#ibcon#read 6, iclass 3, count 2 2006.173.07:44:17.36#ibcon#end of sib2, iclass 3, count 2 2006.173.07:44:17.36#ibcon#*after write, iclass 3, count 2 2006.173.07:44:17.36#ibcon#*before return 0, iclass 3, count 2 2006.173.07:44:17.36#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.07:44:17.36#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.07:44:17.36#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.07:44:17.36#ibcon#ireg 7 cls_cnt 0 2006.173.07:44:17.36#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.07:44:17.48#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.07:44:17.48#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.07:44:17.48#ibcon#enter wrdev, iclass 3, count 0 2006.173.07:44:17.48#ibcon#first serial, iclass 3, count 0 2006.173.07:44:17.48#ibcon#enter sib2, iclass 3, count 0 2006.173.07:44:17.48#ibcon#flushed, iclass 3, count 0 2006.173.07:44:17.48#ibcon#about to write, iclass 3, count 0 2006.173.07:44:17.48#ibcon#wrote, iclass 3, count 0 2006.173.07:44:17.48#ibcon#about to read 3, iclass 3, count 0 2006.173.07:44:17.50#ibcon#read 3, iclass 3, count 0 2006.173.07:44:17.50#ibcon#about to read 4, iclass 3, count 0 2006.173.07:44:17.50#ibcon#read 4, iclass 3, count 0 2006.173.07:44:17.50#ibcon#about to read 5, iclass 3, count 0 2006.173.07:44:17.50#ibcon#read 5, iclass 3, count 0 2006.173.07:44:17.50#ibcon#about to read 6, iclass 3, count 0 2006.173.07:44:17.50#ibcon#read 6, iclass 3, count 0 2006.173.07:44:17.50#ibcon#end of sib2, iclass 3, count 0 2006.173.07:44:17.50#ibcon#*mode == 0, iclass 3, count 0 2006.173.07:44:17.50#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.07:44:17.50#ibcon#[27=USB\r\n] 2006.173.07:44:17.50#ibcon#*before write, iclass 3, count 0 2006.173.07:44:17.50#ibcon#enter sib2, iclass 3, count 0 2006.173.07:44:17.50#ibcon#flushed, iclass 3, count 0 2006.173.07:44:17.50#ibcon#about to write, iclass 3, count 0 2006.173.07:44:17.50#ibcon#wrote, iclass 3, count 0 2006.173.07:44:17.50#ibcon#about to read 3, iclass 3, count 0 2006.173.07:44:17.53#ibcon#read 3, iclass 3, count 0 2006.173.07:44:17.53#ibcon#about to read 4, iclass 3, count 0 2006.173.07:44:17.53#ibcon#read 4, iclass 3, count 0 2006.173.07:44:17.53#ibcon#about to read 5, iclass 3, count 0 2006.173.07:44:17.53#ibcon#read 5, iclass 3, count 0 2006.173.07:44:17.53#ibcon#about to read 6, iclass 3, count 0 2006.173.07:44:17.53#ibcon#read 6, iclass 3, count 0 2006.173.07:44:17.53#ibcon#end of sib2, iclass 3, count 0 2006.173.07:44:17.53#ibcon#*after write, iclass 3, count 0 2006.173.07:44:17.53#ibcon#*before return 0, iclass 3, count 0 2006.173.07:44:17.53#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.07:44:17.53#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.07:44:17.53#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.07:44:17.53#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.07:44:17.53$vck44/vblo=3,649.99 2006.173.07:44:17.53#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.07:44:17.53#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.07:44:17.53#ibcon#ireg 17 cls_cnt 0 2006.173.07:44:17.53#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.07:44:17.53#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.07:44:17.53#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.07:44:17.53#ibcon#enter wrdev, iclass 5, count 0 2006.173.07:44:17.53#ibcon#first serial, iclass 5, count 0 2006.173.07:44:17.53#ibcon#enter sib2, iclass 5, count 0 2006.173.07:44:17.53#ibcon#flushed, iclass 5, count 0 2006.173.07:44:17.53#ibcon#about to write, iclass 5, count 0 2006.173.07:44:17.53#ibcon#wrote, iclass 5, count 0 2006.173.07:44:17.53#ibcon#about to read 3, iclass 5, count 0 2006.173.07:44:17.55#ibcon#read 3, iclass 5, count 0 2006.173.07:44:17.55#ibcon#about to read 4, iclass 5, count 0 2006.173.07:44:17.55#ibcon#read 4, iclass 5, count 0 2006.173.07:44:17.55#ibcon#about to read 5, iclass 5, count 0 2006.173.07:44:17.55#ibcon#read 5, iclass 5, count 0 2006.173.07:44:17.55#ibcon#about to read 6, iclass 5, count 0 2006.173.07:44:17.55#ibcon#read 6, iclass 5, count 0 2006.173.07:44:17.55#ibcon#end of sib2, iclass 5, count 0 2006.173.07:44:17.55#ibcon#*mode == 0, iclass 5, count 0 2006.173.07:44:17.55#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.07:44:17.55#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.07:44:17.55#ibcon#*before write, iclass 5, count 0 2006.173.07:44:17.55#ibcon#enter sib2, iclass 5, count 0 2006.173.07:44:17.55#ibcon#flushed, iclass 5, count 0 2006.173.07:44:17.55#ibcon#about to write, iclass 5, count 0 2006.173.07:44:17.55#ibcon#wrote, iclass 5, count 0 2006.173.07:44:17.55#ibcon#about to read 3, iclass 5, count 0 2006.173.07:44:17.59#ibcon#read 3, iclass 5, count 0 2006.173.07:44:17.59#ibcon#about to read 4, iclass 5, count 0 2006.173.07:44:17.59#ibcon#read 4, iclass 5, count 0 2006.173.07:44:17.59#ibcon#about to read 5, iclass 5, count 0 2006.173.07:44:17.59#ibcon#read 5, iclass 5, count 0 2006.173.07:44:17.59#ibcon#about to read 6, iclass 5, count 0 2006.173.07:44:17.59#ibcon#read 6, iclass 5, count 0 2006.173.07:44:17.59#ibcon#end of sib2, iclass 5, count 0 2006.173.07:44:17.59#ibcon#*after write, iclass 5, count 0 2006.173.07:44:17.59#ibcon#*before return 0, iclass 5, count 0 2006.173.07:44:17.59#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.07:44:17.59#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.07:44:17.59#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.07:44:17.59#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.07:44:17.59$vck44/vb=3,4 2006.173.07:44:17.59#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.173.07:44:17.59#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.173.07:44:17.59#ibcon#ireg 11 cls_cnt 2 2006.173.07:44:17.59#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.07:44:17.65#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.07:44:17.65#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.07:44:17.65#ibcon#enter wrdev, iclass 7, count 2 2006.173.07:44:17.65#ibcon#first serial, iclass 7, count 2 2006.173.07:44:17.65#ibcon#enter sib2, iclass 7, count 2 2006.173.07:44:17.65#ibcon#flushed, iclass 7, count 2 2006.173.07:44:17.65#ibcon#about to write, iclass 7, count 2 2006.173.07:44:17.65#ibcon#wrote, iclass 7, count 2 2006.173.07:44:17.65#ibcon#about to read 3, iclass 7, count 2 2006.173.07:44:17.67#ibcon#read 3, iclass 7, count 2 2006.173.07:44:17.67#ibcon#about to read 4, iclass 7, count 2 2006.173.07:44:17.67#ibcon#read 4, iclass 7, count 2 2006.173.07:44:17.67#ibcon#about to read 5, iclass 7, count 2 2006.173.07:44:17.67#ibcon#read 5, iclass 7, count 2 2006.173.07:44:17.67#ibcon#about to read 6, iclass 7, count 2 2006.173.07:44:17.67#ibcon#read 6, iclass 7, count 2 2006.173.07:44:17.67#ibcon#end of sib2, iclass 7, count 2 2006.173.07:44:17.67#ibcon#*mode == 0, iclass 7, count 2 2006.173.07:44:17.67#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.173.07:44:17.67#ibcon#[27=AT03-04\r\n] 2006.173.07:44:17.67#ibcon#*before write, iclass 7, count 2 2006.173.07:44:17.67#ibcon#enter sib2, iclass 7, count 2 2006.173.07:44:17.67#ibcon#flushed, iclass 7, count 2 2006.173.07:44:17.67#ibcon#about to write, iclass 7, count 2 2006.173.07:44:17.67#ibcon#wrote, iclass 7, count 2 2006.173.07:44:17.67#ibcon#about to read 3, iclass 7, count 2 2006.173.07:44:17.70#ibcon#read 3, iclass 7, count 2 2006.173.07:44:17.70#ibcon#about to read 4, iclass 7, count 2 2006.173.07:44:17.70#ibcon#read 4, iclass 7, count 2 2006.173.07:44:17.70#ibcon#about to read 5, iclass 7, count 2 2006.173.07:44:17.70#ibcon#read 5, iclass 7, count 2 2006.173.07:44:17.70#ibcon#about to read 6, iclass 7, count 2 2006.173.07:44:17.70#ibcon#read 6, iclass 7, count 2 2006.173.07:44:17.70#ibcon#end of sib2, iclass 7, count 2 2006.173.07:44:17.70#ibcon#*after write, iclass 7, count 2 2006.173.07:44:17.70#ibcon#*before return 0, iclass 7, count 2 2006.173.07:44:17.70#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.07:44:17.70#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.173.07:44:17.70#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.173.07:44:17.70#ibcon#ireg 7 cls_cnt 0 2006.173.07:44:17.70#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.07:44:17.82#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.07:44:17.82#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.07:44:17.82#ibcon#enter wrdev, iclass 7, count 0 2006.173.07:44:17.82#ibcon#first serial, iclass 7, count 0 2006.173.07:44:17.82#ibcon#enter sib2, iclass 7, count 0 2006.173.07:44:17.82#ibcon#flushed, iclass 7, count 0 2006.173.07:44:17.82#ibcon#about to write, iclass 7, count 0 2006.173.07:44:17.82#ibcon#wrote, iclass 7, count 0 2006.173.07:44:17.82#ibcon#about to read 3, iclass 7, count 0 2006.173.07:44:17.84#ibcon#read 3, iclass 7, count 0 2006.173.07:44:17.84#ibcon#about to read 4, iclass 7, count 0 2006.173.07:44:17.84#ibcon#read 4, iclass 7, count 0 2006.173.07:44:17.84#ibcon#about to read 5, iclass 7, count 0 2006.173.07:44:17.84#ibcon#read 5, iclass 7, count 0 2006.173.07:44:17.84#ibcon#about to read 6, iclass 7, count 0 2006.173.07:44:17.84#ibcon#read 6, iclass 7, count 0 2006.173.07:44:17.84#ibcon#end of sib2, iclass 7, count 0 2006.173.07:44:17.84#ibcon#*mode == 0, iclass 7, count 0 2006.173.07:44:17.84#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.07:44:17.84#ibcon#[27=USB\r\n] 2006.173.07:44:17.84#ibcon#*before write, iclass 7, count 0 2006.173.07:44:17.84#ibcon#enter sib2, iclass 7, count 0 2006.173.07:44:17.84#ibcon#flushed, iclass 7, count 0 2006.173.07:44:17.84#ibcon#about to write, iclass 7, count 0 2006.173.07:44:17.84#ibcon#wrote, iclass 7, count 0 2006.173.07:44:17.84#ibcon#about to read 3, iclass 7, count 0 2006.173.07:44:17.87#ibcon#read 3, iclass 7, count 0 2006.173.07:44:17.87#ibcon#about to read 4, iclass 7, count 0 2006.173.07:44:17.87#ibcon#read 4, iclass 7, count 0 2006.173.07:44:17.87#ibcon#about to read 5, iclass 7, count 0 2006.173.07:44:17.87#ibcon#read 5, iclass 7, count 0 2006.173.07:44:17.87#ibcon#about to read 6, iclass 7, count 0 2006.173.07:44:17.87#ibcon#read 6, iclass 7, count 0 2006.173.07:44:17.87#ibcon#end of sib2, iclass 7, count 0 2006.173.07:44:17.87#ibcon#*after write, iclass 7, count 0 2006.173.07:44:17.87#ibcon#*before return 0, iclass 7, count 0 2006.173.07:44:17.87#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.07:44:17.87#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.173.07:44:17.87#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.07:44:17.87#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.07:44:17.87$vck44/vblo=4,679.99 2006.173.07:44:17.87#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.07:44:17.87#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.07:44:17.87#ibcon#ireg 17 cls_cnt 0 2006.173.07:44:17.87#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.07:44:17.87#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.07:44:17.87#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.07:44:17.87#ibcon#enter wrdev, iclass 11, count 0 2006.173.07:44:17.87#ibcon#first serial, iclass 11, count 0 2006.173.07:44:17.87#ibcon#enter sib2, iclass 11, count 0 2006.173.07:44:17.87#ibcon#flushed, iclass 11, count 0 2006.173.07:44:17.87#ibcon#about to write, iclass 11, count 0 2006.173.07:44:17.87#ibcon#wrote, iclass 11, count 0 2006.173.07:44:17.87#ibcon#about to read 3, iclass 11, count 0 2006.173.07:44:17.89#ibcon#read 3, iclass 11, count 0 2006.173.07:44:17.89#ibcon#about to read 4, iclass 11, count 0 2006.173.07:44:17.89#ibcon#read 4, iclass 11, count 0 2006.173.07:44:17.89#ibcon#about to read 5, iclass 11, count 0 2006.173.07:44:17.89#ibcon#read 5, iclass 11, count 0 2006.173.07:44:17.89#ibcon#about to read 6, iclass 11, count 0 2006.173.07:44:17.89#ibcon#read 6, iclass 11, count 0 2006.173.07:44:17.89#ibcon#end of sib2, iclass 11, count 0 2006.173.07:44:17.89#ibcon#*mode == 0, iclass 11, count 0 2006.173.07:44:17.89#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.07:44:17.89#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.07:44:17.89#ibcon#*before write, iclass 11, count 0 2006.173.07:44:17.89#ibcon#enter sib2, iclass 11, count 0 2006.173.07:44:17.89#ibcon#flushed, iclass 11, count 0 2006.173.07:44:17.89#ibcon#about to write, iclass 11, count 0 2006.173.07:44:17.89#ibcon#wrote, iclass 11, count 0 2006.173.07:44:17.89#ibcon#about to read 3, iclass 11, count 0 2006.173.07:44:17.93#ibcon#read 3, iclass 11, count 0 2006.173.07:44:17.93#ibcon#about to read 4, iclass 11, count 0 2006.173.07:44:17.93#ibcon#read 4, iclass 11, count 0 2006.173.07:44:17.93#ibcon#about to read 5, iclass 11, count 0 2006.173.07:44:17.93#ibcon#read 5, iclass 11, count 0 2006.173.07:44:17.93#ibcon#about to read 6, iclass 11, count 0 2006.173.07:44:17.93#ibcon#read 6, iclass 11, count 0 2006.173.07:44:17.93#ibcon#end of sib2, iclass 11, count 0 2006.173.07:44:17.93#ibcon#*after write, iclass 11, count 0 2006.173.07:44:17.93#ibcon#*before return 0, iclass 11, count 0 2006.173.07:44:17.93#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.07:44:17.93#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.07:44:17.93#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.07:44:17.93#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.07:44:17.93$vck44/vb=4,4 2006.173.07:44:17.93#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.173.07:44:17.93#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.173.07:44:17.93#ibcon#ireg 11 cls_cnt 2 2006.173.07:44:17.93#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.07:44:17.99#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.07:44:17.99#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.07:44:17.99#ibcon#enter wrdev, iclass 13, count 2 2006.173.07:44:17.99#ibcon#first serial, iclass 13, count 2 2006.173.07:44:17.99#ibcon#enter sib2, iclass 13, count 2 2006.173.07:44:17.99#ibcon#flushed, iclass 13, count 2 2006.173.07:44:17.99#ibcon#about to write, iclass 13, count 2 2006.173.07:44:17.99#ibcon#wrote, iclass 13, count 2 2006.173.07:44:17.99#ibcon#about to read 3, iclass 13, count 2 2006.173.07:44:18.01#ibcon#read 3, iclass 13, count 2 2006.173.07:44:18.01#ibcon#about to read 4, iclass 13, count 2 2006.173.07:44:18.01#ibcon#read 4, iclass 13, count 2 2006.173.07:44:18.01#ibcon#about to read 5, iclass 13, count 2 2006.173.07:44:18.01#ibcon#read 5, iclass 13, count 2 2006.173.07:44:18.01#ibcon#about to read 6, iclass 13, count 2 2006.173.07:44:18.01#ibcon#read 6, iclass 13, count 2 2006.173.07:44:18.01#ibcon#end of sib2, iclass 13, count 2 2006.173.07:44:18.01#ibcon#*mode == 0, iclass 13, count 2 2006.173.07:44:18.01#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.173.07:44:18.01#ibcon#[27=AT04-04\r\n] 2006.173.07:44:18.01#ibcon#*before write, iclass 13, count 2 2006.173.07:44:18.01#ibcon#enter sib2, iclass 13, count 2 2006.173.07:44:18.01#ibcon#flushed, iclass 13, count 2 2006.173.07:44:18.01#ibcon#about to write, iclass 13, count 2 2006.173.07:44:18.01#ibcon#wrote, iclass 13, count 2 2006.173.07:44:18.01#ibcon#about to read 3, iclass 13, count 2 2006.173.07:44:18.04#ibcon#read 3, iclass 13, count 2 2006.173.07:44:18.04#ibcon#about to read 4, iclass 13, count 2 2006.173.07:44:18.04#ibcon#read 4, iclass 13, count 2 2006.173.07:44:18.04#ibcon#about to read 5, iclass 13, count 2 2006.173.07:44:18.04#ibcon#read 5, iclass 13, count 2 2006.173.07:44:18.04#ibcon#about to read 6, iclass 13, count 2 2006.173.07:44:18.04#ibcon#read 6, iclass 13, count 2 2006.173.07:44:18.04#ibcon#end of sib2, iclass 13, count 2 2006.173.07:44:18.04#ibcon#*after write, iclass 13, count 2 2006.173.07:44:18.04#ibcon#*before return 0, iclass 13, count 2 2006.173.07:44:18.04#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.07:44:18.04#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.173.07:44:18.04#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.173.07:44:18.04#ibcon#ireg 7 cls_cnt 0 2006.173.07:44:18.04#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.07:44:18.16#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.07:44:18.16#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.07:44:18.16#ibcon#enter wrdev, iclass 13, count 0 2006.173.07:44:18.16#ibcon#first serial, iclass 13, count 0 2006.173.07:44:18.16#ibcon#enter sib2, iclass 13, count 0 2006.173.07:44:18.16#ibcon#flushed, iclass 13, count 0 2006.173.07:44:18.16#ibcon#about to write, iclass 13, count 0 2006.173.07:44:18.16#ibcon#wrote, iclass 13, count 0 2006.173.07:44:18.16#ibcon#about to read 3, iclass 13, count 0 2006.173.07:44:18.18#ibcon#read 3, iclass 13, count 0 2006.173.07:44:18.18#ibcon#about to read 4, iclass 13, count 0 2006.173.07:44:18.18#ibcon#read 4, iclass 13, count 0 2006.173.07:44:18.18#ibcon#about to read 5, iclass 13, count 0 2006.173.07:44:18.18#ibcon#read 5, iclass 13, count 0 2006.173.07:44:18.18#ibcon#about to read 6, iclass 13, count 0 2006.173.07:44:18.18#ibcon#read 6, iclass 13, count 0 2006.173.07:44:18.18#ibcon#end of sib2, iclass 13, count 0 2006.173.07:44:18.18#ibcon#*mode == 0, iclass 13, count 0 2006.173.07:44:18.18#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.07:44:18.18#ibcon#[27=USB\r\n] 2006.173.07:44:18.18#ibcon#*before write, iclass 13, count 0 2006.173.07:44:18.18#ibcon#enter sib2, iclass 13, count 0 2006.173.07:44:18.18#ibcon#flushed, iclass 13, count 0 2006.173.07:44:18.18#ibcon#about to write, iclass 13, count 0 2006.173.07:44:18.18#ibcon#wrote, iclass 13, count 0 2006.173.07:44:18.18#ibcon#about to read 3, iclass 13, count 0 2006.173.07:44:18.21#ibcon#read 3, iclass 13, count 0 2006.173.07:44:18.21#ibcon#about to read 4, iclass 13, count 0 2006.173.07:44:18.21#ibcon#read 4, iclass 13, count 0 2006.173.07:44:18.21#ibcon#about to read 5, iclass 13, count 0 2006.173.07:44:18.21#ibcon#read 5, iclass 13, count 0 2006.173.07:44:18.21#ibcon#about to read 6, iclass 13, count 0 2006.173.07:44:18.21#ibcon#read 6, iclass 13, count 0 2006.173.07:44:18.21#ibcon#end of sib2, iclass 13, count 0 2006.173.07:44:18.21#ibcon#*after write, iclass 13, count 0 2006.173.07:44:18.21#ibcon#*before return 0, iclass 13, count 0 2006.173.07:44:18.21#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.07:44:18.21#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.173.07:44:18.21#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.07:44:18.21#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.07:44:18.21$vck44/vblo=5,709.99 2006.173.07:44:18.21#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.07:44:18.21#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.07:44:18.21#ibcon#ireg 17 cls_cnt 0 2006.173.07:44:18.21#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.07:44:18.21#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.07:44:18.21#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.07:44:18.21#ibcon#enter wrdev, iclass 15, count 0 2006.173.07:44:18.21#ibcon#first serial, iclass 15, count 0 2006.173.07:44:18.21#ibcon#enter sib2, iclass 15, count 0 2006.173.07:44:18.21#ibcon#flushed, iclass 15, count 0 2006.173.07:44:18.21#ibcon#about to write, iclass 15, count 0 2006.173.07:44:18.21#ibcon#wrote, iclass 15, count 0 2006.173.07:44:18.21#ibcon#about to read 3, iclass 15, count 0 2006.173.07:44:18.23#ibcon#read 3, iclass 15, count 0 2006.173.07:44:18.23#ibcon#about to read 4, iclass 15, count 0 2006.173.07:44:18.23#ibcon#read 4, iclass 15, count 0 2006.173.07:44:18.23#ibcon#about to read 5, iclass 15, count 0 2006.173.07:44:18.23#ibcon#read 5, iclass 15, count 0 2006.173.07:44:18.23#ibcon#about to read 6, iclass 15, count 0 2006.173.07:44:18.23#ibcon#read 6, iclass 15, count 0 2006.173.07:44:18.23#ibcon#end of sib2, iclass 15, count 0 2006.173.07:44:18.23#ibcon#*mode == 0, iclass 15, count 0 2006.173.07:44:18.23#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.07:44:18.23#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.07:44:18.23#ibcon#*before write, iclass 15, count 0 2006.173.07:44:18.23#ibcon#enter sib2, iclass 15, count 0 2006.173.07:44:18.23#ibcon#flushed, iclass 15, count 0 2006.173.07:44:18.23#ibcon#about to write, iclass 15, count 0 2006.173.07:44:18.23#ibcon#wrote, iclass 15, count 0 2006.173.07:44:18.23#ibcon#about to read 3, iclass 15, count 0 2006.173.07:44:18.27#ibcon#read 3, iclass 15, count 0 2006.173.07:44:18.27#ibcon#about to read 4, iclass 15, count 0 2006.173.07:44:18.27#ibcon#read 4, iclass 15, count 0 2006.173.07:44:18.27#ibcon#about to read 5, iclass 15, count 0 2006.173.07:44:18.27#ibcon#read 5, iclass 15, count 0 2006.173.07:44:18.27#ibcon#about to read 6, iclass 15, count 0 2006.173.07:44:18.27#ibcon#read 6, iclass 15, count 0 2006.173.07:44:18.27#ibcon#end of sib2, iclass 15, count 0 2006.173.07:44:18.27#ibcon#*after write, iclass 15, count 0 2006.173.07:44:18.27#ibcon#*before return 0, iclass 15, count 0 2006.173.07:44:18.27#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.07:44:18.27#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.07:44:18.27#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.07:44:18.27#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.07:44:18.27$vck44/vb=5,4 2006.173.07:44:18.27#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.07:44:18.27#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.07:44:18.27#ibcon#ireg 11 cls_cnt 2 2006.173.07:44:18.27#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.07:44:18.33#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.07:44:18.33#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.07:44:18.33#ibcon#enter wrdev, iclass 17, count 2 2006.173.07:44:18.33#ibcon#first serial, iclass 17, count 2 2006.173.07:44:18.33#ibcon#enter sib2, iclass 17, count 2 2006.173.07:44:18.33#ibcon#flushed, iclass 17, count 2 2006.173.07:44:18.33#ibcon#about to write, iclass 17, count 2 2006.173.07:44:18.33#ibcon#wrote, iclass 17, count 2 2006.173.07:44:18.33#ibcon#about to read 3, iclass 17, count 2 2006.173.07:44:18.35#ibcon#read 3, iclass 17, count 2 2006.173.07:44:18.35#ibcon#about to read 4, iclass 17, count 2 2006.173.07:44:18.35#ibcon#read 4, iclass 17, count 2 2006.173.07:44:18.35#ibcon#about to read 5, iclass 17, count 2 2006.173.07:44:18.35#ibcon#read 5, iclass 17, count 2 2006.173.07:44:18.35#ibcon#about to read 6, iclass 17, count 2 2006.173.07:44:18.35#ibcon#read 6, iclass 17, count 2 2006.173.07:44:18.35#ibcon#end of sib2, iclass 17, count 2 2006.173.07:44:18.35#ibcon#*mode == 0, iclass 17, count 2 2006.173.07:44:18.35#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.07:44:18.35#ibcon#[27=AT05-04\r\n] 2006.173.07:44:18.35#ibcon#*before write, iclass 17, count 2 2006.173.07:44:18.35#ibcon#enter sib2, iclass 17, count 2 2006.173.07:44:18.35#ibcon#flushed, iclass 17, count 2 2006.173.07:44:18.35#ibcon#about to write, iclass 17, count 2 2006.173.07:44:18.35#ibcon#wrote, iclass 17, count 2 2006.173.07:44:18.35#ibcon#about to read 3, iclass 17, count 2 2006.173.07:44:18.38#ibcon#read 3, iclass 17, count 2 2006.173.07:44:18.38#ibcon#about to read 4, iclass 17, count 2 2006.173.07:44:18.38#ibcon#read 4, iclass 17, count 2 2006.173.07:44:18.38#ibcon#about to read 5, iclass 17, count 2 2006.173.07:44:18.38#ibcon#read 5, iclass 17, count 2 2006.173.07:44:18.38#ibcon#about to read 6, iclass 17, count 2 2006.173.07:44:18.38#ibcon#read 6, iclass 17, count 2 2006.173.07:44:18.38#ibcon#end of sib2, iclass 17, count 2 2006.173.07:44:18.38#ibcon#*after write, iclass 17, count 2 2006.173.07:44:18.38#ibcon#*before return 0, iclass 17, count 2 2006.173.07:44:18.38#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.07:44:18.38#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.07:44:18.38#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.07:44:18.38#ibcon#ireg 7 cls_cnt 0 2006.173.07:44:18.38#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.07:44:18.50#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.07:44:18.50#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.07:44:18.50#ibcon#enter wrdev, iclass 17, count 0 2006.173.07:44:18.50#ibcon#first serial, iclass 17, count 0 2006.173.07:44:18.50#ibcon#enter sib2, iclass 17, count 0 2006.173.07:44:18.50#ibcon#flushed, iclass 17, count 0 2006.173.07:44:18.50#ibcon#about to write, iclass 17, count 0 2006.173.07:44:18.50#ibcon#wrote, iclass 17, count 0 2006.173.07:44:18.50#ibcon#about to read 3, iclass 17, count 0 2006.173.07:44:18.52#ibcon#read 3, iclass 17, count 0 2006.173.07:44:18.52#ibcon#about to read 4, iclass 17, count 0 2006.173.07:44:18.52#ibcon#read 4, iclass 17, count 0 2006.173.07:44:18.52#ibcon#about to read 5, iclass 17, count 0 2006.173.07:44:18.52#ibcon#read 5, iclass 17, count 0 2006.173.07:44:18.52#ibcon#about to read 6, iclass 17, count 0 2006.173.07:44:18.52#ibcon#read 6, iclass 17, count 0 2006.173.07:44:18.52#ibcon#end of sib2, iclass 17, count 0 2006.173.07:44:18.52#ibcon#*mode == 0, iclass 17, count 0 2006.173.07:44:18.52#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.07:44:18.52#ibcon#[27=USB\r\n] 2006.173.07:44:18.52#ibcon#*before write, iclass 17, count 0 2006.173.07:44:18.52#ibcon#enter sib2, iclass 17, count 0 2006.173.07:44:18.52#ibcon#flushed, iclass 17, count 0 2006.173.07:44:18.52#ibcon#about to write, iclass 17, count 0 2006.173.07:44:18.52#ibcon#wrote, iclass 17, count 0 2006.173.07:44:18.52#ibcon#about to read 3, iclass 17, count 0 2006.173.07:44:18.55#ibcon#read 3, iclass 17, count 0 2006.173.07:44:18.55#ibcon#about to read 4, iclass 17, count 0 2006.173.07:44:18.55#ibcon#read 4, iclass 17, count 0 2006.173.07:44:18.55#ibcon#about to read 5, iclass 17, count 0 2006.173.07:44:18.55#ibcon#read 5, iclass 17, count 0 2006.173.07:44:18.55#ibcon#about to read 6, iclass 17, count 0 2006.173.07:44:18.55#ibcon#read 6, iclass 17, count 0 2006.173.07:44:18.55#ibcon#end of sib2, iclass 17, count 0 2006.173.07:44:18.55#ibcon#*after write, iclass 17, count 0 2006.173.07:44:18.55#ibcon#*before return 0, iclass 17, count 0 2006.173.07:44:18.55#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.07:44:18.55#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.07:44:18.55#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.07:44:18.55#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.07:44:18.55$vck44/vblo=6,719.99 2006.173.07:44:18.55#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.07:44:18.55#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.07:44:18.55#ibcon#ireg 17 cls_cnt 0 2006.173.07:44:18.55#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.07:44:18.55#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.07:44:18.55#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.07:44:18.55#ibcon#enter wrdev, iclass 19, count 0 2006.173.07:44:18.55#ibcon#first serial, iclass 19, count 0 2006.173.07:44:18.55#ibcon#enter sib2, iclass 19, count 0 2006.173.07:44:18.55#ibcon#flushed, iclass 19, count 0 2006.173.07:44:18.55#ibcon#about to write, iclass 19, count 0 2006.173.07:44:18.55#ibcon#wrote, iclass 19, count 0 2006.173.07:44:18.55#ibcon#about to read 3, iclass 19, count 0 2006.173.07:44:18.57#ibcon#read 3, iclass 19, count 0 2006.173.07:44:18.57#ibcon#about to read 4, iclass 19, count 0 2006.173.07:44:18.57#ibcon#read 4, iclass 19, count 0 2006.173.07:44:18.57#ibcon#about to read 5, iclass 19, count 0 2006.173.07:44:18.57#ibcon#read 5, iclass 19, count 0 2006.173.07:44:18.57#ibcon#about to read 6, iclass 19, count 0 2006.173.07:44:18.57#ibcon#read 6, iclass 19, count 0 2006.173.07:44:18.57#ibcon#end of sib2, iclass 19, count 0 2006.173.07:44:18.57#ibcon#*mode == 0, iclass 19, count 0 2006.173.07:44:18.57#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.07:44:18.57#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.07:44:18.57#ibcon#*before write, iclass 19, count 0 2006.173.07:44:18.57#ibcon#enter sib2, iclass 19, count 0 2006.173.07:44:18.57#ibcon#flushed, iclass 19, count 0 2006.173.07:44:18.57#ibcon#about to write, iclass 19, count 0 2006.173.07:44:18.57#ibcon#wrote, iclass 19, count 0 2006.173.07:44:18.57#ibcon#about to read 3, iclass 19, count 0 2006.173.07:44:18.61#ibcon#read 3, iclass 19, count 0 2006.173.07:44:18.61#ibcon#about to read 4, iclass 19, count 0 2006.173.07:44:18.61#ibcon#read 4, iclass 19, count 0 2006.173.07:44:18.61#ibcon#about to read 5, iclass 19, count 0 2006.173.07:44:18.61#ibcon#read 5, iclass 19, count 0 2006.173.07:44:18.61#ibcon#about to read 6, iclass 19, count 0 2006.173.07:44:18.61#ibcon#read 6, iclass 19, count 0 2006.173.07:44:18.61#ibcon#end of sib2, iclass 19, count 0 2006.173.07:44:18.61#ibcon#*after write, iclass 19, count 0 2006.173.07:44:18.61#ibcon#*before return 0, iclass 19, count 0 2006.173.07:44:18.61#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.07:44:18.61#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.07:44:18.61#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.07:44:18.61#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.07:44:18.61$vck44/vb=6,4 2006.173.07:44:18.61#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.07:44:18.61#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.07:44:18.61#ibcon#ireg 11 cls_cnt 2 2006.173.07:44:18.61#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.07:44:18.67#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.07:44:18.67#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.07:44:18.67#ibcon#enter wrdev, iclass 21, count 2 2006.173.07:44:18.67#ibcon#first serial, iclass 21, count 2 2006.173.07:44:18.67#ibcon#enter sib2, iclass 21, count 2 2006.173.07:44:18.67#ibcon#flushed, iclass 21, count 2 2006.173.07:44:18.67#ibcon#about to write, iclass 21, count 2 2006.173.07:44:18.67#ibcon#wrote, iclass 21, count 2 2006.173.07:44:18.67#ibcon#about to read 3, iclass 21, count 2 2006.173.07:44:18.69#ibcon#read 3, iclass 21, count 2 2006.173.07:44:18.69#ibcon#about to read 4, iclass 21, count 2 2006.173.07:44:18.69#ibcon#read 4, iclass 21, count 2 2006.173.07:44:18.69#ibcon#about to read 5, iclass 21, count 2 2006.173.07:44:18.69#ibcon#read 5, iclass 21, count 2 2006.173.07:44:18.69#ibcon#about to read 6, iclass 21, count 2 2006.173.07:44:18.69#ibcon#read 6, iclass 21, count 2 2006.173.07:44:18.69#ibcon#end of sib2, iclass 21, count 2 2006.173.07:44:18.69#ibcon#*mode == 0, iclass 21, count 2 2006.173.07:44:18.69#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.07:44:18.69#ibcon#[27=AT06-04\r\n] 2006.173.07:44:18.69#ibcon#*before write, iclass 21, count 2 2006.173.07:44:18.69#ibcon#enter sib2, iclass 21, count 2 2006.173.07:44:18.69#ibcon#flushed, iclass 21, count 2 2006.173.07:44:18.69#ibcon#about to write, iclass 21, count 2 2006.173.07:44:18.69#ibcon#wrote, iclass 21, count 2 2006.173.07:44:18.69#ibcon#about to read 3, iclass 21, count 2 2006.173.07:44:18.72#ibcon#read 3, iclass 21, count 2 2006.173.07:44:18.72#ibcon#about to read 4, iclass 21, count 2 2006.173.07:44:18.72#ibcon#read 4, iclass 21, count 2 2006.173.07:44:18.72#ibcon#about to read 5, iclass 21, count 2 2006.173.07:44:18.72#ibcon#read 5, iclass 21, count 2 2006.173.07:44:18.72#ibcon#about to read 6, iclass 21, count 2 2006.173.07:44:18.72#ibcon#read 6, iclass 21, count 2 2006.173.07:44:18.72#ibcon#end of sib2, iclass 21, count 2 2006.173.07:44:18.72#ibcon#*after write, iclass 21, count 2 2006.173.07:44:18.72#ibcon#*before return 0, iclass 21, count 2 2006.173.07:44:18.72#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.07:44:18.72#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.07:44:18.72#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.07:44:18.72#ibcon#ireg 7 cls_cnt 0 2006.173.07:44:18.72#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.07:44:18.84#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.07:44:18.84#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.07:44:18.84#ibcon#enter wrdev, iclass 21, count 0 2006.173.07:44:18.84#ibcon#first serial, iclass 21, count 0 2006.173.07:44:18.84#ibcon#enter sib2, iclass 21, count 0 2006.173.07:44:18.84#ibcon#flushed, iclass 21, count 0 2006.173.07:44:18.84#ibcon#about to write, iclass 21, count 0 2006.173.07:44:18.84#ibcon#wrote, iclass 21, count 0 2006.173.07:44:18.84#ibcon#about to read 3, iclass 21, count 0 2006.173.07:44:18.86#ibcon#read 3, iclass 21, count 0 2006.173.07:44:18.86#ibcon#about to read 4, iclass 21, count 0 2006.173.07:44:18.86#ibcon#read 4, iclass 21, count 0 2006.173.07:44:18.86#ibcon#about to read 5, iclass 21, count 0 2006.173.07:44:18.86#ibcon#read 5, iclass 21, count 0 2006.173.07:44:18.86#ibcon#about to read 6, iclass 21, count 0 2006.173.07:44:18.86#ibcon#read 6, iclass 21, count 0 2006.173.07:44:18.86#ibcon#end of sib2, iclass 21, count 0 2006.173.07:44:18.86#ibcon#*mode == 0, iclass 21, count 0 2006.173.07:44:18.86#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.07:44:18.86#ibcon#[27=USB\r\n] 2006.173.07:44:18.86#ibcon#*before write, iclass 21, count 0 2006.173.07:44:18.86#ibcon#enter sib2, iclass 21, count 0 2006.173.07:44:18.86#ibcon#flushed, iclass 21, count 0 2006.173.07:44:18.86#ibcon#about to write, iclass 21, count 0 2006.173.07:44:18.86#ibcon#wrote, iclass 21, count 0 2006.173.07:44:18.86#ibcon#about to read 3, iclass 21, count 0 2006.173.07:44:18.89#ibcon#read 3, iclass 21, count 0 2006.173.07:44:18.89#ibcon#about to read 4, iclass 21, count 0 2006.173.07:44:18.89#ibcon#read 4, iclass 21, count 0 2006.173.07:44:18.89#ibcon#about to read 5, iclass 21, count 0 2006.173.07:44:18.89#ibcon#read 5, iclass 21, count 0 2006.173.07:44:18.89#ibcon#about to read 6, iclass 21, count 0 2006.173.07:44:18.89#ibcon#read 6, iclass 21, count 0 2006.173.07:44:18.89#ibcon#end of sib2, iclass 21, count 0 2006.173.07:44:18.89#ibcon#*after write, iclass 21, count 0 2006.173.07:44:18.89#ibcon#*before return 0, iclass 21, count 0 2006.173.07:44:18.89#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.07:44:18.89#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.07:44:18.89#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.07:44:18.89#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.07:44:18.89$vck44/vblo=7,734.99 2006.173.07:44:18.89#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.07:44:18.89#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.07:44:18.89#ibcon#ireg 17 cls_cnt 0 2006.173.07:44:18.89#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.07:44:18.89#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.07:44:18.89#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.07:44:18.89#ibcon#enter wrdev, iclass 23, count 0 2006.173.07:44:18.89#ibcon#first serial, iclass 23, count 0 2006.173.07:44:18.89#ibcon#enter sib2, iclass 23, count 0 2006.173.07:44:18.89#ibcon#flushed, iclass 23, count 0 2006.173.07:44:18.89#ibcon#about to write, iclass 23, count 0 2006.173.07:44:18.89#ibcon#wrote, iclass 23, count 0 2006.173.07:44:18.89#ibcon#about to read 3, iclass 23, count 0 2006.173.07:44:18.91#ibcon#read 3, iclass 23, count 0 2006.173.07:44:18.91#ibcon#about to read 4, iclass 23, count 0 2006.173.07:44:18.91#ibcon#read 4, iclass 23, count 0 2006.173.07:44:18.91#ibcon#about to read 5, iclass 23, count 0 2006.173.07:44:18.91#ibcon#read 5, iclass 23, count 0 2006.173.07:44:18.91#ibcon#about to read 6, iclass 23, count 0 2006.173.07:44:18.91#ibcon#read 6, iclass 23, count 0 2006.173.07:44:18.91#ibcon#end of sib2, iclass 23, count 0 2006.173.07:44:18.91#ibcon#*mode == 0, iclass 23, count 0 2006.173.07:44:18.91#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.07:44:18.91#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.07:44:18.91#ibcon#*before write, iclass 23, count 0 2006.173.07:44:18.91#ibcon#enter sib2, iclass 23, count 0 2006.173.07:44:18.91#ibcon#flushed, iclass 23, count 0 2006.173.07:44:18.91#ibcon#about to write, iclass 23, count 0 2006.173.07:44:18.91#ibcon#wrote, iclass 23, count 0 2006.173.07:44:18.91#ibcon#about to read 3, iclass 23, count 0 2006.173.07:44:18.95#ibcon#read 3, iclass 23, count 0 2006.173.07:44:18.95#ibcon#about to read 4, iclass 23, count 0 2006.173.07:44:18.95#ibcon#read 4, iclass 23, count 0 2006.173.07:44:18.95#ibcon#about to read 5, iclass 23, count 0 2006.173.07:44:18.95#ibcon#read 5, iclass 23, count 0 2006.173.07:44:18.95#ibcon#about to read 6, iclass 23, count 0 2006.173.07:44:18.95#ibcon#read 6, iclass 23, count 0 2006.173.07:44:18.95#ibcon#end of sib2, iclass 23, count 0 2006.173.07:44:18.95#ibcon#*after write, iclass 23, count 0 2006.173.07:44:18.95#ibcon#*before return 0, iclass 23, count 0 2006.173.07:44:18.95#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.07:44:18.95#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.07:44:18.95#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.07:44:18.95#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.07:44:18.95$vck44/vb=7,4 2006.173.07:44:18.95#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.07:44:18.95#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.07:44:18.95#ibcon#ireg 11 cls_cnt 2 2006.173.07:44:18.95#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.07:44:19.01#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.07:44:19.01#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.07:44:19.01#ibcon#enter wrdev, iclass 25, count 2 2006.173.07:44:19.01#ibcon#first serial, iclass 25, count 2 2006.173.07:44:19.01#ibcon#enter sib2, iclass 25, count 2 2006.173.07:44:19.01#ibcon#flushed, iclass 25, count 2 2006.173.07:44:19.01#ibcon#about to write, iclass 25, count 2 2006.173.07:44:19.01#ibcon#wrote, iclass 25, count 2 2006.173.07:44:19.01#ibcon#about to read 3, iclass 25, count 2 2006.173.07:44:19.03#ibcon#read 3, iclass 25, count 2 2006.173.07:44:19.03#ibcon#about to read 4, iclass 25, count 2 2006.173.07:44:19.03#ibcon#read 4, iclass 25, count 2 2006.173.07:44:19.03#ibcon#about to read 5, iclass 25, count 2 2006.173.07:44:19.03#ibcon#read 5, iclass 25, count 2 2006.173.07:44:19.03#ibcon#about to read 6, iclass 25, count 2 2006.173.07:44:19.03#ibcon#read 6, iclass 25, count 2 2006.173.07:44:19.03#ibcon#end of sib2, iclass 25, count 2 2006.173.07:44:19.03#ibcon#*mode == 0, iclass 25, count 2 2006.173.07:44:19.03#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.07:44:19.03#ibcon#[27=AT07-04\r\n] 2006.173.07:44:19.03#ibcon#*before write, iclass 25, count 2 2006.173.07:44:19.03#ibcon#enter sib2, iclass 25, count 2 2006.173.07:44:19.03#ibcon#flushed, iclass 25, count 2 2006.173.07:44:19.03#ibcon#about to write, iclass 25, count 2 2006.173.07:44:19.03#ibcon#wrote, iclass 25, count 2 2006.173.07:44:19.03#ibcon#about to read 3, iclass 25, count 2 2006.173.07:44:19.06#ibcon#read 3, iclass 25, count 2 2006.173.07:44:19.06#ibcon#about to read 4, iclass 25, count 2 2006.173.07:44:19.06#ibcon#read 4, iclass 25, count 2 2006.173.07:44:19.06#ibcon#about to read 5, iclass 25, count 2 2006.173.07:44:19.06#ibcon#read 5, iclass 25, count 2 2006.173.07:44:19.06#ibcon#about to read 6, iclass 25, count 2 2006.173.07:44:19.06#ibcon#read 6, iclass 25, count 2 2006.173.07:44:19.06#ibcon#end of sib2, iclass 25, count 2 2006.173.07:44:19.06#ibcon#*after write, iclass 25, count 2 2006.173.07:44:19.06#ibcon#*before return 0, iclass 25, count 2 2006.173.07:44:19.06#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.07:44:19.06#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.07:44:19.06#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.07:44:19.06#ibcon#ireg 7 cls_cnt 0 2006.173.07:44:19.06#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.07:44:19.18#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.07:44:19.18#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.07:44:19.18#ibcon#enter wrdev, iclass 25, count 0 2006.173.07:44:19.18#ibcon#first serial, iclass 25, count 0 2006.173.07:44:19.18#ibcon#enter sib2, iclass 25, count 0 2006.173.07:44:19.18#ibcon#flushed, iclass 25, count 0 2006.173.07:44:19.18#ibcon#about to write, iclass 25, count 0 2006.173.07:44:19.18#ibcon#wrote, iclass 25, count 0 2006.173.07:44:19.18#ibcon#about to read 3, iclass 25, count 0 2006.173.07:44:19.20#ibcon#read 3, iclass 25, count 0 2006.173.07:44:19.20#ibcon#about to read 4, iclass 25, count 0 2006.173.07:44:19.20#ibcon#read 4, iclass 25, count 0 2006.173.07:44:19.20#ibcon#about to read 5, iclass 25, count 0 2006.173.07:44:19.20#ibcon#read 5, iclass 25, count 0 2006.173.07:44:19.20#ibcon#about to read 6, iclass 25, count 0 2006.173.07:44:19.20#ibcon#read 6, iclass 25, count 0 2006.173.07:44:19.20#ibcon#end of sib2, iclass 25, count 0 2006.173.07:44:19.20#ibcon#*mode == 0, iclass 25, count 0 2006.173.07:44:19.20#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.07:44:19.20#ibcon#[27=USB\r\n] 2006.173.07:44:19.20#ibcon#*before write, iclass 25, count 0 2006.173.07:44:19.20#ibcon#enter sib2, iclass 25, count 0 2006.173.07:44:19.20#ibcon#flushed, iclass 25, count 0 2006.173.07:44:19.20#ibcon#about to write, iclass 25, count 0 2006.173.07:44:19.20#ibcon#wrote, iclass 25, count 0 2006.173.07:44:19.20#ibcon#about to read 3, iclass 25, count 0 2006.173.07:44:19.23#ibcon#read 3, iclass 25, count 0 2006.173.07:44:19.23#ibcon#about to read 4, iclass 25, count 0 2006.173.07:44:19.23#ibcon#read 4, iclass 25, count 0 2006.173.07:44:19.23#ibcon#about to read 5, iclass 25, count 0 2006.173.07:44:19.23#ibcon#read 5, iclass 25, count 0 2006.173.07:44:19.23#ibcon#about to read 6, iclass 25, count 0 2006.173.07:44:19.23#ibcon#read 6, iclass 25, count 0 2006.173.07:44:19.23#ibcon#end of sib2, iclass 25, count 0 2006.173.07:44:19.23#ibcon#*after write, iclass 25, count 0 2006.173.07:44:19.23#ibcon#*before return 0, iclass 25, count 0 2006.173.07:44:19.23#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.07:44:19.23#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.07:44:19.23#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.07:44:19.23#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.07:44:19.23$vck44/vblo=8,744.99 2006.173.07:44:19.23#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.07:44:19.23#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.07:44:19.23#ibcon#ireg 17 cls_cnt 0 2006.173.07:44:19.23#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.07:44:19.23#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.07:44:19.23#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.07:44:19.23#ibcon#enter wrdev, iclass 27, count 0 2006.173.07:44:19.23#ibcon#first serial, iclass 27, count 0 2006.173.07:44:19.23#ibcon#enter sib2, iclass 27, count 0 2006.173.07:44:19.23#ibcon#flushed, iclass 27, count 0 2006.173.07:44:19.23#ibcon#about to write, iclass 27, count 0 2006.173.07:44:19.23#ibcon#wrote, iclass 27, count 0 2006.173.07:44:19.23#ibcon#about to read 3, iclass 27, count 0 2006.173.07:44:19.25#ibcon#read 3, iclass 27, count 0 2006.173.07:44:19.25#ibcon#about to read 4, iclass 27, count 0 2006.173.07:44:19.25#ibcon#read 4, iclass 27, count 0 2006.173.07:44:19.25#ibcon#about to read 5, iclass 27, count 0 2006.173.07:44:19.25#ibcon#read 5, iclass 27, count 0 2006.173.07:44:19.25#ibcon#about to read 6, iclass 27, count 0 2006.173.07:44:19.25#ibcon#read 6, iclass 27, count 0 2006.173.07:44:19.25#ibcon#end of sib2, iclass 27, count 0 2006.173.07:44:19.25#ibcon#*mode == 0, iclass 27, count 0 2006.173.07:44:19.25#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.07:44:19.25#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.07:44:19.25#ibcon#*before write, iclass 27, count 0 2006.173.07:44:19.25#ibcon#enter sib2, iclass 27, count 0 2006.173.07:44:19.25#ibcon#flushed, iclass 27, count 0 2006.173.07:44:19.25#ibcon#about to write, iclass 27, count 0 2006.173.07:44:19.25#ibcon#wrote, iclass 27, count 0 2006.173.07:44:19.25#ibcon#about to read 3, iclass 27, count 0 2006.173.07:44:19.29#ibcon#read 3, iclass 27, count 0 2006.173.07:44:19.29#ibcon#about to read 4, iclass 27, count 0 2006.173.07:44:19.29#ibcon#read 4, iclass 27, count 0 2006.173.07:44:19.29#ibcon#about to read 5, iclass 27, count 0 2006.173.07:44:19.29#ibcon#read 5, iclass 27, count 0 2006.173.07:44:19.29#ibcon#about to read 6, iclass 27, count 0 2006.173.07:44:19.29#ibcon#read 6, iclass 27, count 0 2006.173.07:44:19.29#ibcon#end of sib2, iclass 27, count 0 2006.173.07:44:19.29#ibcon#*after write, iclass 27, count 0 2006.173.07:44:19.29#ibcon#*before return 0, iclass 27, count 0 2006.173.07:44:19.29#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.07:44:19.29#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.07:44:19.29#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.07:44:19.29#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.07:44:19.29$vck44/vb=8,4 2006.173.07:44:19.29#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.07:44:19.29#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.07:44:19.29#ibcon#ireg 11 cls_cnt 2 2006.173.07:44:19.29#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.07:44:19.35#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.07:44:19.35#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.07:44:19.35#ibcon#enter wrdev, iclass 29, count 2 2006.173.07:44:19.35#ibcon#first serial, iclass 29, count 2 2006.173.07:44:19.35#ibcon#enter sib2, iclass 29, count 2 2006.173.07:44:19.35#ibcon#flushed, iclass 29, count 2 2006.173.07:44:19.35#ibcon#about to write, iclass 29, count 2 2006.173.07:44:19.35#ibcon#wrote, iclass 29, count 2 2006.173.07:44:19.35#ibcon#about to read 3, iclass 29, count 2 2006.173.07:44:19.37#ibcon#read 3, iclass 29, count 2 2006.173.07:44:19.37#ibcon#about to read 4, iclass 29, count 2 2006.173.07:44:19.37#ibcon#read 4, iclass 29, count 2 2006.173.07:44:19.37#ibcon#about to read 5, iclass 29, count 2 2006.173.07:44:19.37#ibcon#read 5, iclass 29, count 2 2006.173.07:44:19.37#ibcon#about to read 6, iclass 29, count 2 2006.173.07:44:19.37#ibcon#read 6, iclass 29, count 2 2006.173.07:44:19.37#ibcon#end of sib2, iclass 29, count 2 2006.173.07:44:19.37#ibcon#*mode == 0, iclass 29, count 2 2006.173.07:44:19.37#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.07:44:19.37#ibcon#[27=AT08-04\r\n] 2006.173.07:44:19.37#ibcon#*before write, iclass 29, count 2 2006.173.07:44:19.37#ibcon#enter sib2, iclass 29, count 2 2006.173.07:44:19.37#ibcon#flushed, iclass 29, count 2 2006.173.07:44:19.37#ibcon#about to write, iclass 29, count 2 2006.173.07:44:19.37#ibcon#wrote, iclass 29, count 2 2006.173.07:44:19.37#ibcon#about to read 3, iclass 29, count 2 2006.173.07:44:19.40#ibcon#read 3, iclass 29, count 2 2006.173.07:44:19.40#ibcon#about to read 4, iclass 29, count 2 2006.173.07:44:19.40#ibcon#read 4, iclass 29, count 2 2006.173.07:44:19.40#ibcon#about to read 5, iclass 29, count 2 2006.173.07:44:19.40#ibcon#read 5, iclass 29, count 2 2006.173.07:44:19.40#ibcon#about to read 6, iclass 29, count 2 2006.173.07:44:19.40#ibcon#read 6, iclass 29, count 2 2006.173.07:44:19.40#ibcon#end of sib2, iclass 29, count 2 2006.173.07:44:19.40#ibcon#*after write, iclass 29, count 2 2006.173.07:44:19.40#ibcon#*before return 0, iclass 29, count 2 2006.173.07:44:19.40#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.07:44:19.40#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.07:44:19.40#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.07:44:19.40#ibcon#ireg 7 cls_cnt 0 2006.173.07:44:19.40#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.07:44:19.52#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.07:44:19.52#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.07:44:19.52#ibcon#enter wrdev, iclass 29, count 0 2006.173.07:44:19.52#ibcon#first serial, iclass 29, count 0 2006.173.07:44:19.52#ibcon#enter sib2, iclass 29, count 0 2006.173.07:44:19.52#ibcon#flushed, iclass 29, count 0 2006.173.07:44:19.52#ibcon#about to write, iclass 29, count 0 2006.173.07:44:19.52#ibcon#wrote, iclass 29, count 0 2006.173.07:44:19.52#ibcon#about to read 3, iclass 29, count 0 2006.173.07:44:19.54#ibcon#read 3, iclass 29, count 0 2006.173.07:44:19.54#ibcon#about to read 4, iclass 29, count 0 2006.173.07:44:19.54#ibcon#read 4, iclass 29, count 0 2006.173.07:44:19.54#ibcon#about to read 5, iclass 29, count 0 2006.173.07:44:19.54#ibcon#read 5, iclass 29, count 0 2006.173.07:44:19.54#ibcon#about to read 6, iclass 29, count 0 2006.173.07:44:19.54#ibcon#read 6, iclass 29, count 0 2006.173.07:44:19.54#ibcon#end of sib2, iclass 29, count 0 2006.173.07:44:19.54#ibcon#*mode == 0, iclass 29, count 0 2006.173.07:44:19.54#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.07:44:19.54#ibcon#[27=USB\r\n] 2006.173.07:44:19.54#ibcon#*before write, iclass 29, count 0 2006.173.07:44:19.54#ibcon#enter sib2, iclass 29, count 0 2006.173.07:44:19.54#ibcon#flushed, iclass 29, count 0 2006.173.07:44:19.54#ibcon#about to write, iclass 29, count 0 2006.173.07:44:19.54#ibcon#wrote, iclass 29, count 0 2006.173.07:44:19.54#ibcon#about to read 3, iclass 29, count 0 2006.173.07:44:19.54#abcon#<5=/01 0.4 1.1 23.67 831004.4\r\n> 2006.173.07:44:19.56#abcon#{5=INTERFACE CLEAR} 2006.173.07:44:19.57#ibcon#read 3, iclass 29, count 0 2006.173.07:44:19.57#ibcon#about to read 4, iclass 29, count 0 2006.173.07:44:19.57#ibcon#read 4, iclass 29, count 0 2006.173.07:44:19.57#ibcon#about to read 5, iclass 29, count 0 2006.173.07:44:19.57#ibcon#read 5, iclass 29, count 0 2006.173.07:44:19.57#ibcon#about to read 6, iclass 29, count 0 2006.173.07:44:19.57#ibcon#read 6, iclass 29, count 0 2006.173.07:44:19.57#ibcon#end of sib2, iclass 29, count 0 2006.173.07:44:19.57#ibcon#*after write, iclass 29, count 0 2006.173.07:44:19.57#ibcon#*before return 0, iclass 29, count 0 2006.173.07:44:19.57#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.07:44:19.57#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.07:44:19.57#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.07:44:19.57#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.07:44:19.57$vck44/vabw=wide 2006.173.07:44:19.57#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.07:44:19.57#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.07:44:19.57#ibcon#ireg 8 cls_cnt 0 2006.173.07:44:19.57#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.07:44:19.57#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.07:44:19.57#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.07:44:19.57#ibcon#enter wrdev, iclass 34, count 0 2006.173.07:44:19.57#ibcon#first serial, iclass 34, count 0 2006.173.07:44:19.57#ibcon#enter sib2, iclass 34, count 0 2006.173.07:44:19.57#ibcon#flushed, iclass 34, count 0 2006.173.07:44:19.57#ibcon#about to write, iclass 34, count 0 2006.173.07:44:19.57#ibcon#wrote, iclass 34, count 0 2006.173.07:44:19.57#ibcon#about to read 3, iclass 34, count 0 2006.173.07:44:19.59#ibcon#read 3, iclass 34, count 0 2006.173.07:44:19.59#ibcon#about to read 4, iclass 34, count 0 2006.173.07:44:19.59#ibcon#read 4, iclass 34, count 0 2006.173.07:44:19.59#ibcon#about to read 5, iclass 34, count 0 2006.173.07:44:19.59#ibcon#read 5, iclass 34, count 0 2006.173.07:44:19.59#ibcon#about to read 6, iclass 34, count 0 2006.173.07:44:19.59#ibcon#read 6, iclass 34, count 0 2006.173.07:44:19.59#ibcon#end of sib2, iclass 34, count 0 2006.173.07:44:19.59#ibcon#*mode == 0, iclass 34, count 0 2006.173.07:44:19.59#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.07:44:19.59#ibcon#[25=BW32\r\n] 2006.173.07:44:19.59#ibcon#*before write, iclass 34, count 0 2006.173.07:44:19.59#ibcon#enter sib2, iclass 34, count 0 2006.173.07:44:19.59#ibcon#flushed, iclass 34, count 0 2006.173.07:44:19.59#ibcon#about to write, iclass 34, count 0 2006.173.07:44:19.59#ibcon#wrote, iclass 34, count 0 2006.173.07:44:19.59#ibcon#about to read 3, iclass 34, count 0 2006.173.07:44:19.62#abcon#[5=S1D000X0/0*\r\n] 2006.173.07:44:19.62#ibcon#read 3, iclass 34, count 0 2006.173.07:44:19.62#ibcon#about to read 4, iclass 34, count 0 2006.173.07:44:19.62#ibcon#read 4, iclass 34, count 0 2006.173.07:44:19.62#ibcon#about to read 5, iclass 34, count 0 2006.173.07:44:19.62#ibcon#read 5, iclass 34, count 0 2006.173.07:44:19.62#ibcon#about to read 6, iclass 34, count 0 2006.173.07:44:19.62#ibcon#read 6, iclass 34, count 0 2006.173.07:44:19.62#ibcon#end of sib2, iclass 34, count 0 2006.173.07:44:19.62#ibcon#*after write, iclass 34, count 0 2006.173.07:44:19.62#ibcon#*before return 0, iclass 34, count 0 2006.173.07:44:19.62#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.07:44:19.62#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.07:44:19.62#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.07:44:19.62#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.07:44:19.62$vck44/vbbw=wide 2006.173.07:44:19.62#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.07:44:19.62#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.07:44:19.62#ibcon#ireg 8 cls_cnt 0 2006.173.07:44:19.62#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.07:44:19.69#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.07:44:19.69#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.07:44:19.69#ibcon#enter wrdev, iclass 37, count 0 2006.173.07:44:19.69#ibcon#first serial, iclass 37, count 0 2006.173.07:44:19.69#ibcon#enter sib2, iclass 37, count 0 2006.173.07:44:19.69#ibcon#flushed, iclass 37, count 0 2006.173.07:44:19.69#ibcon#about to write, iclass 37, count 0 2006.173.07:44:19.69#ibcon#wrote, iclass 37, count 0 2006.173.07:44:19.69#ibcon#about to read 3, iclass 37, count 0 2006.173.07:44:19.71#ibcon#read 3, iclass 37, count 0 2006.173.07:44:19.71#ibcon#about to read 4, iclass 37, count 0 2006.173.07:44:19.71#ibcon#read 4, iclass 37, count 0 2006.173.07:44:19.71#ibcon#about to read 5, iclass 37, count 0 2006.173.07:44:19.71#ibcon#read 5, iclass 37, count 0 2006.173.07:44:19.71#ibcon#about to read 6, iclass 37, count 0 2006.173.07:44:19.71#ibcon#read 6, iclass 37, count 0 2006.173.07:44:19.71#ibcon#end of sib2, iclass 37, count 0 2006.173.07:44:19.71#ibcon#*mode == 0, iclass 37, count 0 2006.173.07:44:19.71#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.07:44:19.71#ibcon#[27=BW32\r\n] 2006.173.07:44:19.71#ibcon#*before write, iclass 37, count 0 2006.173.07:44:19.71#ibcon#enter sib2, iclass 37, count 0 2006.173.07:44:19.71#ibcon#flushed, iclass 37, count 0 2006.173.07:44:19.71#ibcon#about to write, iclass 37, count 0 2006.173.07:44:19.71#ibcon#wrote, iclass 37, count 0 2006.173.07:44:19.71#ibcon#about to read 3, iclass 37, count 0 2006.173.07:44:19.74#ibcon#read 3, iclass 37, count 0 2006.173.07:44:19.74#ibcon#about to read 4, iclass 37, count 0 2006.173.07:44:19.74#ibcon#read 4, iclass 37, count 0 2006.173.07:44:19.74#ibcon#about to read 5, iclass 37, count 0 2006.173.07:44:19.74#ibcon#read 5, iclass 37, count 0 2006.173.07:44:19.74#ibcon#about to read 6, iclass 37, count 0 2006.173.07:44:19.74#ibcon#read 6, iclass 37, count 0 2006.173.07:44:19.74#ibcon#end of sib2, iclass 37, count 0 2006.173.07:44:19.74#ibcon#*after write, iclass 37, count 0 2006.173.07:44:19.74#ibcon#*before return 0, iclass 37, count 0 2006.173.07:44:19.74#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.07:44:19.74#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.07:44:19.74#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.07:44:19.74#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.07:44:19.74$setupk4/ifdk4 2006.173.07:44:19.74$ifdk4/lo= 2006.173.07:44:19.74$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.07:44:19.74$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.07:44:19.74$ifdk4/patch= 2006.173.07:44:19.74$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.07:44:19.74$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.07:44:19.74$setupk4/!*+20s 2006.173.07:44:29.71#abcon#<5=/01 0.4 1.1 23.66 831004.4\r\n> 2006.173.07:44:29.73#abcon#{5=INTERFACE CLEAR} 2006.173.07:44:29.79#abcon#[5=S1D000X0/0*\r\n] 2006.173.07:44:34.24$setupk4/"tpicd 2006.173.07:44:34.24$setupk4/echo=off 2006.173.07:44:34.24$setupk4/xlog=off 2006.173.07:44:34.24:!2006.173.07:47:09 2006.173.07:44:39.13#trakl#Source acquired 2006.173.07:44:39.13#flagr#flagr/antenna,acquired 2006.173.07:47:09.00:preob 2006.173.07:47:10.14/onsource/TRACKING 2006.173.07:47:10.14:!2006.173.07:47:19 2006.173.07:47:19.00:"tape 2006.173.07:47:19.00:"st=record 2006.173.07:47:19.00:data_valid=on 2006.173.07:47:19.00:midob 2006.173.07:47:19.14/onsource/TRACKING 2006.173.07:47:19.14/wx/23.62,1004.4,80 2006.173.07:47:19.33/cable/+6.5013E-03 2006.173.07:47:20.42/va/01,07,usb,yes,36,39 2006.173.07:47:20.42/va/02,06,usb,yes,36,37 2006.173.07:47:20.42/va/03,05,usb,yes,46,47 2006.173.07:47:20.42/va/04,06,usb,yes,36,39 2006.173.07:47:20.42/va/05,04,usb,yes,29,29 2006.173.07:47:20.42/va/06,03,usb,yes,40,40 2006.173.07:47:20.42/va/07,04,usb,yes,33,34 2006.173.07:47:20.42/va/08,04,usb,yes,28,33 2006.173.07:47:20.65/valo/01,524.99,yes,locked 2006.173.07:47:20.65/valo/02,534.99,yes,locked 2006.173.07:47:20.65/valo/03,564.99,yes,locked 2006.173.07:47:20.65/valo/04,624.99,yes,locked 2006.173.07:47:20.65/valo/05,734.99,yes,locked 2006.173.07:47:20.65/valo/06,814.99,yes,locked 2006.173.07:47:20.65/valo/07,864.99,yes,locked 2006.173.07:47:20.65/valo/08,884.99,yes,locked 2006.173.07:47:21.74/vb/01,04,usb,yes,29,27 2006.173.07:47:21.74/vb/02,04,usb,yes,32,31 2006.173.07:47:21.74/vb/03,04,usb,yes,29,32 2006.173.07:47:21.74/vb/04,04,usb,yes,33,32 2006.173.07:47:21.74/vb/05,04,usb,yes,26,28 2006.173.07:47:21.74/vb/06,04,usb,yes,30,26 2006.173.07:47:21.74/vb/07,04,usb,yes,30,30 2006.173.07:47:21.74/vb/08,04,usb,yes,27,31 2006.173.07:47:21.98/vblo/01,629.99,yes,locked 2006.173.07:47:21.98/vblo/02,634.99,yes,locked 2006.173.07:47:21.98/vblo/03,649.99,yes,locked 2006.173.07:47:21.98/vblo/04,679.99,yes,locked 2006.173.07:47:21.98/vblo/05,709.99,yes,locked 2006.173.07:47:21.98/vblo/06,719.99,yes,locked 2006.173.07:47:21.98/vblo/07,734.99,yes,locked 2006.173.07:47:21.98/vblo/08,744.99,yes,locked 2006.173.07:47:22.13/vabw/8 2006.173.07:47:22.28/vbbw/8 2006.173.07:47:22.37/xfe/off,on,15.2 2006.173.07:47:22.74/ifatt/23,28,28,28 2006.173.07:47:23.08/fmout-gps/S +3.92E-07 2006.173.07:47:23.12:!2006.173.07:48:19 2006.173.07:48:19.00:data_valid=off 2006.173.07:48:19.00:"et 2006.173.07:48:19.00:!+3s 2006.173.07:48:22.02:"tape 2006.173.07:48:22.02:postob 2006.173.07:48:22.21/cable/+6.5020E-03 2006.173.07:48:22.21/wx/23.59,1004.4,81 2006.173.07:48:23.08/fmout-gps/S +3.92E-07 2006.173.07:48:23.08:scan_name=173-0755,jd0606,360 2006.173.07:48:23.08:source=1308+326,131028.66,322043.8,2000.0,cw 2006.173.07:48:23.14#flagr#flagr/antenna,new-source 2006.173.07:48:24.14:checkk5 2006.173.07:48:24.52/chk_autoobs//k5ts1/ autoobs is running! 2006.173.07:48:24.93/chk_autoobs//k5ts2/ autoobs is running! 2006.173.07:48:25.33/chk_autoobs//k5ts3/ autoobs is running! 2006.173.07:48:25.73/chk_autoobs//k5ts4/ autoobs is running! 2006.173.07:48:26.12/chk_obsdata//k5ts1/T1730747??a.dat file size is correct (nominal:240MB, actual:240MB). 2006.173.07:48:26.53/chk_obsdata//k5ts2/T1730747??b.dat file size is correct (nominal:240MB, actual:240MB). 2006.173.07:48:26.93/chk_obsdata//k5ts3/T1730747??c.dat file size is correct (nominal:240MB, actual:240MB). 2006.173.07:48:27.34/chk_obsdata//k5ts4/T1730747??d.dat file size is correct (nominal:240MB, actual:240MB). 2006.173.07:48:28.08/k5log//k5ts1_log_newline 2006.173.07:48:28.79/k5log//k5ts2_log_newline 2006.173.07:48:29.50/k5log//k5ts3_log_newline 2006.173.07:48:30.21/k5log//k5ts4_log_newline 2006.173.07:48:30.24/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.07:48:30.24:setupk4=1 2006.173.07:48:30.24$setupk4/echo=on 2006.173.07:48:30.24$setupk4/pcalon 2006.173.07:48:30.24$pcalon/"no phase cal control is implemented here 2006.173.07:48:30.24$setupk4/"tpicd=stop 2006.173.07:48:30.24$setupk4/"rec=synch_on 2006.173.07:48:30.24$setupk4/"rec_mode=128 2006.173.07:48:30.24$setupk4/!* 2006.173.07:48:30.24$setupk4/recpk4 2006.173.07:48:30.24$recpk4/recpatch= 2006.173.07:48:30.24$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.07:48:30.24$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.07:48:30.24$setupk4/vck44 2006.173.07:48:30.24$vck44/valo=1,524.99 2006.173.07:48:30.24#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.07:48:30.24#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.07:48:30.24#ibcon#ireg 17 cls_cnt 0 2006.173.07:48:30.24#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.07:48:30.24#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.07:48:30.24#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.07:48:30.24#ibcon#enter wrdev, iclass 30, count 0 2006.173.07:48:30.24#ibcon#first serial, iclass 30, count 0 2006.173.07:48:30.24#ibcon#enter sib2, iclass 30, count 0 2006.173.07:48:30.24#ibcon#flushed, iclass 30, count 0 2006.173.07:48:30.24#ibcon#about to write, iclass 30, count 0 2006.173.07:48:30.24#ibcon#wrote, iclass 30, count 0 2006.173.07:48:30.24#ibcon#about to read 3, iclass 30, count 0 2006.173.07:48:30.26#ibcon#read 3, iclass 30, count 0 2006.173.07:48:30.26#ibcon#about to read 4, iclass 30, count 0 2006.173.07:48:30.26#ibcon#read 4, iclass 30, count 0 2006.173.07:48:30.26#ibcon#about to read 5, iclass 30, count 0 2006.173.07:48:30.26#ibcon#read 5, iclass 30, count 0 2006.173.07:48:30.26#ibcon#about to read 6, iclass 30, count 0 2006.173.07:48:30.26#ibcon#read 6, iclass 30, count 0 2006.173.07:48:30.26#ibcon#end of sib2, iclass 30, count 0 2006.173.07:48:30.26#ibcon#*mode == 0, iclass 30, count 0 2006.173.07:48:30.26#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.07:48:30.26#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.07:48:30.26#ibcon#*before write, iclass 30, count 0 2006.173.07:48:30.26#ibcon#enter sib2, iclass 30, count 0 2006.173.07:48:30.26#ibcon#flushed, iclass 30, count 0 2006.173.07:48:30.26#ibcon#about to write, iclass 30, count 0 2006.173.07:48:30.26#ibcon#wrote, iclass 30, count 0 2006.173.07:48:30.26#ibcon#about to read 3, iclass 30, count 0 2006.173.07:48:30.31#ibcon#read 3, iclass 30, count 0 2006.173.07:48:30.31#ibcon#about to read 4, iclass 30, count 0 2006.173.07:48:30.31#ibcon#read 4, iclass 30, count 0 2006.173.07:48:30.31#ibcon#about to read 5, iclass 30, count 0 2006.173.07:48:30.31#ibcon#read 5, iclass 30, count 0 2006.173.07:48:30.31#ibcon#about to read 6, iclass 30, count 0 2006.173.07:48:30.31#ibcon#read 6, iclass 30, count 0 2006.173.07:48:30.31#ibcon#end of sib2, iclass 30, count 0 2006.173.07:48:30.31#ibcon#*after write, iclass 30, count 0 2006.173.07:48:30.31#ibcon#*before return 0, iclass 30, count 0 2006.173.07:48:30.31#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.07:48:30.31#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.07:48:30.31#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.07:48:30.31#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.07:48:30.31$vck44/va=1,7 2006.173.07:48:30.31#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.173.07:48:30.31#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.173.07:48:30.31#ibcon#ireg 11 cls_cnt 2 2006.173.07:48:30.31#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.07:48:30.31#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.07:48:30.31#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.07:48:30.31#ibcon#enter wrdev, iclass 32, count 2 2006.173.07:48:30.31#ibcon#first serial, iclass 32, count 2 2006.173.07:48:30.31#ibcon#enter sib2, iclass 32, count 2 2006.173.07:48:30.31#ibcon#flushed, iclass 32, count 2 2006.173.07:48:30.31#ibcon#about to write, iclass 32, count 2 2006.173.07:48:30.31#ibcon#wrote, iclass 32, count 2 2006.173.07:48:30.31#ibcon#about to read 3, iclass 32, count 2 2006.173.07:48:30.33#ibcon#read 3, iclass 32, count 2 2006.173.07:48:30.33#ibcon#about to read 4, iclass 32, count 2 2006.173.07:48:30.33#ibcon#read 4, iclass 32, count 2 2006.173.07:48:30.33#ibcon#about to read 5, iclass 32, count 2 2006.173.07:48:30.33#ibcon#read 5, iclass 32, count 2 2006.173.07:48:30.33#ibcon#about to read 6, iclass 32, count 2 2006.173.07:48:30.33#ibcon#read 6, iclass 32, count 2 2006.173.07:48:30.33#ibcon#end of sib2, iclass 32, count 2 2006.173.07:48:30.33#ibcon#*mode == 0, iclass 32, count 2 2006.173.07:48:30.33#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.173.07:48:30.33#ibcon#[25=AT01-07\r\n] 2006.173.07:48:30.33#ibcon#*before write, iclass 32, count 2 2006.173.07:48:30.33#ibcon#enter sib2, iclass 32, count 2 2006.173.07:48:30.33#ibcon#flushed, iclass 32, count 2 2006.173.07:48:30.33#ibcon#about to write, iclass 32, count 2 2006.173.07:48:30.33#ibcon#wrote, iclass 32, count 2 2006.173.07:48:30.33#ibcon#about to read 3, iclass 32, count 2 2006.173.07:48:30.36#ibcon#read 3, iclass 32, count 2 2006.173.07:48:30.36#ibcon#about to read 4, iclass 32, count 2 2006.173.07:48:30.36#ibcon#read 4, iclass 32, count 2 2006.173.07:48:30.36#ibcon#about to read 5, iclass 32, count 2 2006.173.07:48:30.36#ibcon#read 5, iclass 32, count 2 2006.173.07:48:30.36#ibcon#about to read 6, iclass 32, count 2 2006.173.07:48:30.36#ibcon#read 6, iclass 32, count 2 2006.173.07:48:30.36#ibcon#end of sib2, iclass 32, count 2 2006.173.07:48:30.36#ibcon#*after write, iclass 32, count 2 2006.173.07:48:30.36#ibcon#*before return 0, iclass 32, count 2 2006.173.07:48:30.36#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.07:48:30.36#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.173.07:48:30.36#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.173.07:48:30.36#ibcon#ireg 7 cls_cnt 0 2006.173.07:48:30.36#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.07:48:30.48#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.07:48:30.48#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.07:48:30.48#ibcon#enter wrdev, iclass 32, count 0 2006.173.07:48:30.48#ibcon#first serial, iclass 32, count 0 2006.173.07:48:30.48#ibcon#enter sib2, iclass 32, count 0 2006.173.07:48:30.48#ibcon#flushed, iclass 32, count 0 2006.173.07:48:30.48#ibcon#about to write, iclass 32, count 0 2006.173.07:48:30.48#ibcon#wrote, iclass 32, count 0 2006.173.07:48:30.48#ibcon#about to read 3, iclass 32, count 0 2006.173.07:48:30.50#ibcon#read 3, iclass 32, count 0 2006.173.07:48:30.50#ibcon#about to read 4, iclass 32, count 0 2006.173.07:48:30.50#ibcon#read 4, iclass 32, count 0 2006.173.07:48:30.50#ibcon#about to read 5, iclass 32, count 0 2006.173.07:48:30.50#ibcon#read 5, iclass 32, count 0 2006.173.07:48:30.50#ibcon#about to read 6, iclass 32, count 0 2006.173.07:48:30.50#ibcon#read 6, iclass 32, count 0 2006.173.07:48:30.50#ibcon#end of sib2, iclass 32, count 0 2006.173.07:48:30.50#ibcon#*mode == 0, iclass 32, count 0 2006.173.07:48:30.50#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.07:48:30.50#ibcon#[25=USB\r\n] 2006.173.07:48:30.50#ibcon#*before write, iclass 32, count 0 2006.173.07:48:30.50#ibcon#enter sib2, iclass 32, count 0 2006.173.07:48:30.50#ibcon#flushed, iclass 32, count 0 2006.173.07:48:30.50#ibcon#about to write, iclass 32, count 0 2006.173.07:48:30.50#ibcon#wrote, iclass 32, count 0 2006.173.07:48:30.50#ibcon#about to read 3, iclass 32, count 0 2006.173.07:48:30.53#ibcon#read 3, iclass 32, count 0 2006.173.07:48:30.53#ibcon#about to read 4, iclass 32, count 0 2006.173.07:48:30.53#ibcon#read 4, iclass 32, count 0 2006.173.07:48:30.53#ibcon#about to read 5, iclass 32, count 0 2006.173.07:48:30.53#ibcon#read 5, iclass 32, count 0 2006.173.07:48:30.53#ibcon#about to read 6, iclass 32, count 0 2006.173.07:48:30.53#ibcon#read 6, iclass 32, count 0 2006.173.07:48:30.53#ibcon#end of sib2, iclass 32, count 0 2006.173.07:48:30.53#ibcon#*after write, iclass 32, count 0 2006.173.07:48:30.53#ibcon#*before return 0, iclass 32, count 0 2006.173.07:48:30.53#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.07:48:30.53#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.173.07:48:30.53#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.07:48:30.53#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.07:48:30.53$vck44/valo=2,534.99 2006.173.07:48:30.53#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.07:48:30.53#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.07:48:30.53#ibcon#ireg 17 cls_cnt 0 2006.173.07:48:30.53#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.07:48:30.53#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.07:48:30.53#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.07:48:30.53#ibcon#enter wrdev, iclass 34, count 0 2006.173.07:48:30.53#ibcon#first serial, iclass 34, count 0 2006.173.07:48:30.53#ibcon#enter sib2, iclass 34, count 0 2006.173.07:48:30.53#ibcon#flushed, iclass 34, count 0 2006.173.07:48:30.53#ibcon#about to write, iclass 34, count 0 2006.173.07:48:30.53#ibcon#wrote, iclass 34, count 0 2006.173.07:48:30.53#ibcon#about to read 3, iclass 34, count 0 2006.173.07:48:30.55#ibcon#read 3, iclass 34, count 0 2006.173.07:48:30.55#ibcon#about to read 4, iclass 34, count 0 2006.173.07:48:30.55#ibcon#read 4, iclass 34, count 0 2006.173.07:48:30.55#ibcon#about to read 5, iclass 34, count 0 2006.173.07:48:30.55#ibcon#read 5, iclass 34, count 0 2006.173.07:48:30.55#ibcon#about to read 6, iclass 34, count 0 2006.173.07:48:30.55#ibcon#read 6, iclass 34, count 0 2006.173.07:48:30.55#ibcon#end of sib2, iclass 34, count 0 2006.173.07:48:30.55#ibcon#*mode == 0, iclass 34, count 0 2006.173.07:48:30.55#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.07:48:30.55#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.07:48:30.55#ibcon#*before write, iclass 34, count 0 2006.173.07:48:30.55#ibcon#enter sib2, iclass 34, count 0 2006.173.07:48:30.55#ibcon#flushed, iclass 34, count 0 2006.173.07:48:30.55#ibcon#about to write, iclass 34, count 0 2006.173.07:48:30.55#ibcon#wrote, iclass 34, count 0 2006.173.07:48:30.55#ibcon#about to read 3, iclass 34, count 0 2006.173.07:48:30.59#ibcon#read 3, iclass 34, count 0 2006.173.07:48:30.59#ibcon#about to read 4, iclass 34, count 0 2006.173.07:48:30.59#ibcon#read 4, iclass 34, count 0 2006.173.07:48:30.59#ibcon#about to read 5, iclass 34, count 0 2006.173.07:48:30.59#ibcon#read 5, iclass 34, count 0 2006.173.07:48:30.59#ibcon#about to read 6, iclass 34, count 0 2006.173.07:48:30.59#ibcon#read 6, iclass 34, count 0 2006.173.07:48:30.59#ibcon#end of sib2, iclass 34, count 0 2006.173.07:48:30.59#ibcon#*after write, iclass 34, count 0 2006.173.07:48:30.59#ibcon#*before return 0, iclass 34, count 0 2006.173.07:48:30.59#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.07:48:30.59#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.07:48:30.59#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.07:48:30.59#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.07:48:30.59$vck44/va=2,6 2006.173.07:48:30.59#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.07:48:30.59#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.07:48:30.59#ibcon#ireg 11 cls_cnt 2 2006.173.07:48:30.59#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.07:48:30.65#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.07:48:30.65#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.07:48:30.65#ibcon#enter wrdev, iclass 36, count 2 2006.173.07:48:30.65#ibcon#first serial, iclass 36, count 2 2006.173.07:48:30.65#ibcon#enter sib2, iclass 36, count 2 2006.173.07:48:30.65#ibcon#flushed, iclass 36, count 2 2006.173.07:48:30.65#ibcon#about to write, iclass 36, count 2 2006.173.07:48:30.65#ibcon#wrote, iclass 36, count 2 2006.173.07:48:30.65#ibcon#about to read 3, iclass 36, count 2 2006.173.07:48:30.67#ibcon#read 3, iclass 36, count 2 2006.173.07:48:30.67#ibcon#about to read 4, iclass 36, count 2 2006.173.07:48:30.67#ibcon#read 4, iclass 36, count 2 2006.173.07:48:30.67#ibcon#about to read 5, iclass 36, count 2 2006.173.07:48:30.67#ibcon#read 5, iclass 36, count 2 2006.173.07:48:30.67#ibcon#about to read 6, iclass 36, count 2 2006.173.07:48:30.67#ibcon#read 6, iclass 36, count 2 2006.173.07:48:30.67#ibcon#end of sib2, iclass 36, count 2 2006.173.07:48:30.67#ibcon#*mode == 0, iclass 36, count 2 2006.173.07:48:30.67#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.07:48:30.67#ibcon#[25=AT02-06\r\n] 2006.173.07:48:30.67#ibcon#*before write, iclass 36, count 2 2006.173.07:48:30.67#ibcon#enter sib2, iclass 36, count 2 2006.173.07:48:30.67#ibcon#flushed, iclass 36, count 2 2006.173.07:48:30.67#ibcon#about to write, iclass 36, count 2 2006.173.07:48:30.67#ibcon#wrote, iclass 36, count 2 2006.173.07:48:30.67#ibcon#about to read 3, iclass 36, count 2 2006.173.07:48:30.70#ibcon#read 3, iclass 36, count 2 2006.173.07:48:30.70#ibcon#about to read 4, iclass 36, count 2 2006.173.07:48:30.70#ibcon#read 4, iclass 36, count 2 2006.173.07:48:30.70#ibcon#about to read 5, iclass 36, count 2 2006.173.07:48:30.70#ibcon#read 5, iclass 36, count 2 2006.173.07:48:30.70#ibcon#about to read 6, iclass 36, count 2 2006.173.07:48:30.70#ibcon#read 6, iclass 36, count 2 2006.173.07:48:30.70#ibcon#end of sib2, iclass 36, count 2 2006.173.07:48:30.70#ibcon#*after write, iclass 36, count 2 2006.173.07:48:30.70#ibcon#*before return 0, iclass 36, count 2 2006.173.07:48:30.70#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.07:48:30.70#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.07:48:30.70#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.07:48:30.70#ibcon#ireg 7 cls_cnt 0 2006.173.07:48:30.70#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.07:48:30.82#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.07:48:30.82#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.07:48:30.82#ibcon#enter wrdev, iclass 36, count 0 2006.173.07:48:30.82#ibcon#first serial, iclass 36, count 0 2006.173.07:48:30.82#ibcon#enter sib2, iclass 36, count 0 2006.173.07:48:30.82#ibcon#flushed, iclass 36, count 0 2006.173.07:48:30.82#ibcon#about to write, iclass 36, count 0 2006.173.07:48:30.82#ibcon#wrote, iclass 36, count 0 2006.173.07:48:30.82#ibcon#about to read 3, iclass 36, count 0 2006.173.07:48:30.84#ibcon#read 3, iclass 36, count 0 2006.173.07:48:30.84#ibcon#about to read 4, iclass 36, count 0 2006.173.07:48:30.84#ibcon#read 4, iclass 36, count 0 2006.173.07:48:30.84#ibcon#about to read 5, iclass 36, count 0 2006.173.07:48:30.84#ibcon#read 5, iclass 36, count 0 2006.173.07:48:30.84#ibcon#about to read 6, iclass 36, count 0 2006.173.07:48:30.84#ibcon#read 6, iclass 36, count 0 2006.173.07:48:30.84#ibcon#end of sib2, iclass 36, count 0 2006.173.07:48:30.84#ibcon#*mode == 0, iclass 36, count 0 2006.173.07:48:30.84#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.07:48:30.84#ibcon#[25=USB\r\n] 2006.173.07:48:30.84#ibcon#*before write, iclass 36, count 0 2006.173.07:48:30.84#ibcon#enter sib2, iclass 36, count 0 2006.173.07:48:30.84#ibcon#flushed, iclass 36, count 0 2006.173.07:48:30.84#ibcon#about to write, iclass 36, count 0 2006.173.07:48:30.84#ibcon#wrote, iclass 36, count 0 2006.173.07:48:30.84#ibcon#about to read 3, iclass 36, count 0 2006.173.07:48:30.87#ibcon#read 3, iclass 36, count 0 2006.173.07:48:30.87#ibcon#about to read 4, iclass 36, count 0 2006.173.07:48:30.87#ibcon#read 4, iclass 36, count 0 2006.173.07:48:30.87#ibcon#about to read 5, iclass 36, count 0 2006.173.07:48:30.87#ibcon#read 5, iclass 36, count 0 2006.173.07:48:30.87#ibcon#about to read 6, iclass 36, count 0 2006.173.07:48:30.87#ibcon#read 6, iclass 36, count 0 2006.173.07:48:30.87#ibcon#end of sib2, iclass 36, count 0 2006.173.07:48:30.87#ibcon#*after write, iclass 36, count 0 2006.173.07:48:30.87#ibcon#*before return 0, iclass 36, count 0 2006.173.07:48:30.87#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.07:48:30.87#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.07:48:30.87#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.07:48:30.87#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.07:48:30.87$vck44/valo=3,564.99 2006.173.07:48:30.87#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.07:48:30.87#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.07:48:30.87#ibcon#ireg 17 cls_cnt 0 2006.173.07:48:30.87#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.07:48:30.87#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.07:48:30.87#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.07:48:30.87#ibcon#enter wrdev, iclass 38, count 0 2006.173.07:48:30.87#ibcon#first serial, iclass 38, count 0 2006.173.07:48:30.87#ibcon#enter sib2, iclass 38, count 0 2006.173.07:48:30.87#ibcon#flushed, iclass 38, count 0 2006.173.07:48:30.87#ibcon#about to write, iclass 38, count 0 2006.173.07:48:30.87#ibcon#wrote, iclass 38, count 0 2006.173.07:48:30.87#ibcon#about to read 3, iclass 38, count 0 2006.173.07:48:30.89#ibcon#read 3, iclass 38, count 0 2006.173.07:48:30.89#ibcon#about to read 4, iclass 38, count 0 2006.173.07:48:30.89#ibcon#read 4, iclass 38, count 0 2006.173.07:48:30.89#ibcon#about to read 5, iclass 38, count 0 2006.173.07:48:30.89#ibcon#read 5, iclass 38, count 0 2006.173.07:48:30.89#ibcon#about to read 6, iclass 38, count 0 2006.173.07:48:30.89#ibcon#read 6, iclass 38, count 0 2006.173.07:48:30.89#ibcon#end of sib2, iclass 38, count 0 2006.173.07:48:30.89#ibcon#*mode == 0, iclass 38, count 0 2006.173.07:48:30.89#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.07:48:30.89#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.07:48:30.89#ibcon#*before write, iclass 38, count 0 2006.173.07:48:30.89#ibcon#enter sib2, iclass 38, count 0 2006.173.07:48:30.89#ibcon#flushed, iclass 38, count 0 2006.173.07:48:30.89#ibcon#about to write, iclass 38, count 0 2006.173.07:48:30.89#ibcon#wrote, iclass 38, count 0 2006.173.07:48:30.89#ibcon#about to read 3, iclass 38, count 0 2006.173.07:48:30.93#ibcon#read 3, iclass 38, count 0 2006.173.07:48:30.93#ibcon#about to read 4, iclass 38, count 0 2006.173.07:48:30.93#ibcon#read 4, iclass 38, count 0 2006.173.07:48:30.93#ibcon#about to read 5, iclass 38, count 0 2006.173.07:48:30.93#ibcon#read 5, iclass 38, count 0 2006.173.07:48:30.93#ibcon#about to read 6, iclass 38, count 0 2006.173.07:48:30.93#ibcon#read 6, iclass 38, count 0 2006.173.07:48:30.93#ibcon#end of sib2, iclass 38, count 0 2006.173.07:48:30.93#ibcon#*after write, iclass 38, count 0 2006.173.07:48:30.93#ibcon#*before return 0, iclass 38, count 0 2006.173.07:48:30.93#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.07:48:30.93#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.07:48:30.93#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.07:48:30.93#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.07:48:30.93$vck44/va=3,5 2006.173.07:48:30.93#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.07:48:30.93#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.07:48:30.93#ibcon#ireg 11 cls_cnt 2 2006.173.07:48:30.93#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.07:48:30.99#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.07:48:30.99#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.07:48:30.99#ibcon#enter wrdev, iclass 40, count 2 2006.173.07:48:30.99#ibcon#first serial, iclass 40, count 2 2006.173.07:48:30.99#ibcon#enter sib2, iclass 40, count 2 2006.173.07:48:30.99#ibcon#flushed, iclass 40, count 2 2006.173.07:48:30.99#ibcon#about to write, iclass 40, count 2 2006.173.07:48:30.99#ibcon#wrote, iclass 40, count 2 2006.173.07:48:30.99#ibcon#about to read 3, iclass 40, count 2 2006.173.07:48:31.01#ibcon#read 3, iclass 40, count 2 2006.173.07:48:31.01#ibcon#about to read 4, iclass 40, count 2 2006.173.07:48:31.01#ibcon#read 4, iclass 40, count 2 2006.173.07:48:31.01#ibcon#about to read 5, iclass 40, count 2 2006.173.07:48:31.01#ibcon#read 5, iclass 40, count 2 2006.173.07:48:31.01#ibcon#about to read 6, iclass 40, count 2 2006.173.07:48:31.01#ibcon#read 6, iclass 40, count 2 2006.173.07:48:31.01#ibcon#end of sib2, iclass 40, count 2 2006.173.07:48:31.01#ibcon#*mode == 0, iclass 40, count 2 2006.173.07:48:31.01#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.07:48:31.01#ibcon#[25=AT03-05\r\n] 2006.173.07:48:31.01#ibcon#*before write, iclass 40, count 2 2006.173.07:48:31.01#ibcon#enter sib2, iclass 40, count 2 2006.173.07:48:31.01#ibcon#flushed, iclass 40, count 2 2006.173.07:48:31.01#ibcon#about to write, iclass 40, count 2 2006.173.07:48:31.01#ibcon#wrote, iclass 40, count 2 2006.173.07:48:31.01#ibcon#about to read 3, iclass 40, count 2 2006.173.07:48:31.04#ibcon#read 3, iclass 40, count 2 2006.173.07:48:31.04#ibcon#about to read 4, iclass 40, count 2 2006.173.07:48:31.04#ibcon#read 4, iclass 40, count 2 2006.173.07:48:31.04#ibcon#about to read 5, iclass 40, count 2 2006.173.07:48:31.04#ibcon#read 5, iclass 40, count 2 2006.173.07:48:31.04#ibcon#about to read 6, iclass 40, count 2 2006.173.07:48:31.04#ibcon#read 6, iclass 40, count 2 2006.173.07:48:31.04#ibcon#end of sib2, iclass 40, count 2 2006.173.07:48:31.04#ibcon#*after write, iclass 40, count 2 2006.173.07:48:31.04#ibcon#*before return 0, iclass 40, count 2 2006.173.07:48:31.04#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.07:48:31.04#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.07:48:31.04#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.07:48:31.04#ibcon#ireg 7 cls_cnt 0 2006.173.07:48:31.04#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.07:48:31.16#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.07:48:31.16#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.07:48:31.16#ibcon#enter wrdev, iclass 40, count 0 2006.173.07:48:31.16#ibcon#first serial, iclass 40, count 0 2006.173.07:48:31.16#ibcon#enter sib2, iclass 40, count 0 2006.173.07:48:31.16#ibcon#flushed, iclass 40, count 0 2006.173.07:48:31.16#ibcon#about to write, iclass 40, count 0 2006.173.07:48:31.16#ibcon#wrote, iclass 40, count 0 2006.173.07:48:31.16#ibcon#about to read 3, iclass 40, count 0 2006.173.07:48:31.18#ibcon#read 3, iclass 40, count 0 2006.173.07:48:31.18#ibcon#about to read 4, iclass 40, count 0 2006.173.07:48:31.18#ibcon#read 4, iclass 40, count 0 2006.173.07:48:31.18#ibcon#about to read 5, iclass 40, count 0 2006.173.07:48:31.18#ibcon#read 5, iclass 40, count 0 2006.173.07:48:31.18#ibcon#about to read 6, iclass 40, count 0 2006.173.07:48:31.18#ibcon#read 6, iclass 40, count 0 2006.173.07:48:31.18#ibcon#end of sib2, iclass 40, count 0 2006.173.07:48:31.18#ibcon#*mode == 0, iclass 40, count 0 2006.173.07:48:31.18#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.07:48:31.18#ibcon#[25=USB\r\n] 2006.173.07:48:31.18#ibcon#*before write, iclass 40, count 0 2006.173.07:48:31.18#ibcon#enter sib2, iclass 40, count 0 2006.173.07:48:31.18#ibcon#flushed, iclass 40, count 0 2006.173.07:48:31.18#ibcon#about to write, iclass 40, count 0 2006.173.07:48:31.18#ibcon#wrote, iclass 40, count 0 2006.173.07:48:31.18#ibcon#about to read 3, iclass 40, count 0 2006.173.07:48:31.21#ibcon#read 3, iclass 40, count 0 2006.173.07:48:31.21#ibcon#about to read 4, iclass 40, count 0 2006.173.07:48:31.21#ibcon#read 4, iclass 40, count 0 2006.173.07:48:31.21#ibcon#about to read 5, iclass 40, count 0 2006.173.07:48:31.21#ibcon#read 5, iclass 40, count 0 2006.173.07:48:31.21#ibcon#about to read 6, iclass 40, count 0 2006.173.07:48:31.21#ibcon#read 6, iclass 40, count 0 2006.173.07:48:31.21#ibcon#end of sib2, iclass 40, count 0 2006.173.07:48:31.21#ibcon#*after write, iclass 40, count 0 2006.173.07:48:31.21#ibcon#*before return 0, iclass 40, count 0 2006.173.07:48:31.21#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.07:48:31.21#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.07:48:31.21#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.07:48:31.21#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.07:48:31.21$vck44/valo=4,624.99 2006.173.07:48:31.21#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.07:48:31.21#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.07:48:31.21#ibcon#ireg 17 cls_cnt 0 2006.173.07:48:31.21#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.07:48:31.21#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.07:48:31.21#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.07:48:31.21#ibcon#enter wrdev, iclass 4, count 0 2006.173.07:48:31.21#ibcon#first serial, iclass 4, count 0 2006.173.07:48:31.21#ibcon#enter sib2, iclass 4, count 0 2006.173.07:48:31.21#ibcon#flushed, iclass 4, count 0 2006.173.07:48:31.21#ibcon#about to write, iclass 4, count 0 2006.173.07:48:31.21#ibcon#wrote, iclass 4, count 0 2006.173.07:48:31.21#ibcon#about to read 3, iclass 4, count 0 2006.173.07:48:31.23#ibcon#read 3, iclass 4, count 0 2006.173.07:48:31.23#ibcon#about to read 4, iclass 4, count 0 2006.173.07:48:31.23#ibcon#read 4, iclass 4, count 0 2006.173.07:48:31.23#ibcon#about to read 5, iclass 4, count 0 2006.173.07:48:31.23#ibcon#read 5, iclass 4, count 0 2006.173.07:48:31.23#ibcon#about to read 6, iclass 4, count 0 2006.173.07:48:31.23#ibcon#read 6, iclass 4, count 0 2006.173.07:48:31.23#ibcon#end of sib2, iclass 4, count 0 2006.173.07:48:31.23#ibcon#*mode == 0, iclass 4, count 0 2006.173.07:48:31.23#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.07:48:31.23#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.07:48:31.23#ibcon#*before write, iclass 4, count 0 2006.173.07:48:31.23#ibcon#enter sib2, iclass 4, count 0 2006.173.07:48:31.23#ibcon#flushed, iclass 4, count 0 2006.173.07:48:31.23#ibcon#about to write, iclass 4, count 0 2006.173.07:48:31.23#ibcon#wrote, iclass 4, count 0 2006.173.07:48:31.23#ibcon#about to read 3, iclass 4, count 0 2006.173.07:48:31.27#ibcon#read 3, iclass 4, count 0 2006.173.07:48:31.27#ibcon#about to read 4, iclass 4, count 0 2006.173.07:48:31.27#ibcon#read 4, iclass 4, count 0 2006.173.07:48:31.27#ibcon#about to read 5, iclass 4, count 0 2006.173.07:48:31.27#ibcon#read 5, iclass 4, count 0 2006.173.07:48:31.27#ibcon#about to read 6, iclass 4, count 0 2006.173.07:48:31.27#ibcon#read 6, iclass 4, count 0 2006.173.07:48:31.27#ibcon#end of sib2, iclass 4, count 0 2006.173.07:48:31.27#ibcon#*after write, iclass 4, count 0 2006.173.07:48:31.27#ibcon#*before return 0, iclass 4, count 0 2006.173.07:48:31.27#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.07:48:31.27#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.07:48:31.27#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.07:48:31.27#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.07:48:31.27$vck44/va=4,6 2006.173.07:48:31.27#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.07:48:31.27#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.07:48:31.27#ibcon#ireg 11 cls_cnt 2 2006.173.07:48:31.27#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.07:48:31.33#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.07:48:31.33#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.07:48:31.33#ibcon#enter wrdev, iclass 6, count 2 2006.173.07:48:31.33#ibcon#first serial, iclass 6, count 2 2006.173.07:48:31.33#ibcon#enter sib2, iclass 6, count 2 2006.173.07:48:31.33#ibcon#flushed, iclass 6, count 2 2006.173.07:48:31.33#ibcon#about to write, iclass 6, count 2 2006.173.07:48:31.33#ibcon#wrote, iclass 6, count 2 2006.173.07:48:31.33#ibcon#about to read 3, iclass 6, count 2 2006.173.07:48:31.35#ibcon#read 3, iclass 6, count 2 2006.173.07:48:31.35#ibcon#about to read 4, iclass 6, count 2 2006.173.07:48:31.35#ibcon#read 4, iclass 6, count 2 2006.173.07:48:31.35#ibcon#about to read 5, iclass 6, count 2 2006.173.07:48:31.35#ibcon#read 5, iclass 6, count 2 2006.173.07:48:31.35#ibcon#about to read 6, iclass 6, count 2 2006.173.07:48:31.35#ibcon#read 6, iclass 6, count 2 2006.173.07:48:31.35#ibcon#end of sib2, iclass 6, count 2 2006.173.07:48:31.35#ibcon#*mode == 0, iclass 6, count 2 2006.173.07:48:31.35#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.07:48:31.35#ibcon#[25=AT04-06\r\n] 2006.173.07:48:31.35#ibcon#*before write, iclass 6, count 2 2006.173.07:48:31.35#ibcon#enter sib2, iclass 6, count 2 2006.173.07:48:31.35#ibcon#flushed, iclass 6, count 2 2006.173.07:48:31.35#ibcon#about to write, iclass 6, count 2 2006.173.07:48:31.35#ibcon#wrote, iclass 6, count 2 2006.173.07:48:31.35#ibcon#about to read 3, iclass 6, count 2 2006.173.07:48:31.38#ibcon#read 3, iclass 6, count 2 2006.173.07:48:31.38#ibcon#about to read 4, iclass 6, count 2 2006.173.07:48:31.38#ibcon#read 4, iclass 6, count 2 2006.173.07:48:31.38#ibcon#about to read 5, iclass 6, count 2 2006.173.07:48:31.38#ibcon#read 5, iclass 6, count 2 2006.173.07:48:31.38#ibcon#about to read 6, iclass 6, count 2 2006.173.07:48:31.38#ibcon#read 6, iclass 6, count 2 2006.173.07:48:31.38#ibcon#end of sib2, iclass 6, count 2 2006.173.07:48:31.38#ibcon#*after write, iclass 6, count 2 2006.173.07:48:31.38#ibcon#*before return 0, iclass 6, count 2 2006.173.07:48:31.38#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.07:48:31.38#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.07:48:31.38#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.07:48:31.38#ibcon#ireg 7 cls_cnt 0 2006.173.07:48:31.38#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.07:48:31.50#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.07:48:31.50#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.07:48:31.50#ibcon#enter wrdev, iclass 6, count 0 2006.173.07:48:31.50#ibcon#first serial, iclass 6, count 0 2006.173.07:48:31.50#ibcon#enter sib2, iclass 6, count 0 2006.173.07:48:31.50#ibcon#flushed, iclass 6, count 0 2006.173.07:48:31.50#ibcon#about to write, iclass 6, count 0 2006.173.07:48:31.50#ibcon#wrote, iclass 6, count 0 2006.173.07:48:31.50#ibcon#about to read 3, iclass 6, count 0 2006.173.07:48:31.52#ibcon#read 3, iclass 6, count 0 2006.173.07:48:31.52#ibcon#about to read 4, iclass 6, count 0 2006.173.07:48:31.52#ibcon#read 4, iclass 6, count 0 2006.173.07:48:31.52#ibcon#about to read 5, iclass 6, count 0 2006.173.07:48:31.52#ibcon#read 5, iclass 6, count 0 2006.173.07:48:31.52#ibcon#about to read 6, iclass 6, count 0 2006.173.07:48:31.52#ibcon#read 6, iclass 6, count 0 2006.173.07:48:31.52#ibcon#end of sib2, iclass 6, count 0 2006.173.07:48:31.52#ibcon#*mode == 0, iclass 6, count 0 2006.173.07:48:31.52#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.07:48:31.52#ibcon#[25=USB\r\n] 2006.173.07:48:31.52#ibcon#*before write, iclass 6, count 0 2006.173.07:48:31.52#ibcon#enter sib2, iclass 6, count 0 2006.173.07:48:31.52#ibcon#flushed, iclass 6, count 0 2006.173.07:48:31.52#ibcon#about to write, iclass 6, count 0 2006.173.07:48:31.52#ibcon#wrote, iclass 6, count 0 2006.173.07:48:31.52#ibcon#about to read 3, iclass 6, count 0 2006.173.07:48:31.55#ibcon#read 3, iclass 6, count 0 2006.173.07:48:31.55#ibcon#about to read 4, iclass 6, count 0 2006.173.07:48:31.55#ibcon#read 4, iclass 6, count 0 2006.173.07:48:31.55#ibcon#about to read 5, iclass 6, count 0 2006.173.07:48:31.55#ibcon#read 5, iclass 6, count 0 2006.173.07:48:31.55#ibcon#about to read 6, iclass 6, count 0 2006.173.07:48:31.55#ibcon#read 6, iclass 6, count 0 2006.173.07:48:31.55#ibcon#end of sib2, iclass 6, count 0 2006.173.07:48:31.55#ibcon#*after write, iclass 6, count 0 2006.173.07:48:31.55#ibcon#*before return 0, iclass 6, count 0 2006.173.07:48:31.55#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.07:48:31.55#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.07:48:31.55#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.07:48:31.55#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.07:48:31.55$vck44/valo=5,734.99 2006.173.07:48:31.55#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.07:48:31.55#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.07:48:31.55#ibcon#ireg 17 cls_cnt 0 2006.173.07:48:31.55#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.07:48:31.55#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.07:48:31.55#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.07:48:31.55#ibcon#enter wrdev, iclass 10, count 0 2006.173.07:48:31.55#ibcon#first serial, iclass 10, count 0 2006.173.07:48:31.55#ibcon#enter sib2, iclass 10, count 0 2006.173.07:48:31.55#ibcon#flushed, iclass 10, count 0 2006.173.07:48:31.55#ibcon#about to write, iclass 10, count 0 2006.173.07:48:31.55#ibcon#wrote, iclass 10, count 0 2006.173.07:48:31.55#ibcon#about to read 3, iclass 10, count 0 2006.173.07:48:31.57#ibcon#read 3, iclass 10, count 0 2006.173.07:48:31.57#ibcon#about to read 4, iclass 10, count 0 2006.173.07:48:31.57#ibcon#read 4, iclass 10, count 0 2006.173.07:48:31.57#ibcon#about to read 5, iclass 10, count 0 2006.173.07:48:31.57#ibcon#read 5, iclass 10, count 0 2006.173.07:48:31.57#ibcon#about to read 6, iclass 10, count 0 2006.173.07:48:31.57#ibcon#read 6, iclass 10, count 0 2006.173.07:48:31.57#ibcon#end of sib2, iclass 10, count 0 2006.173.07:48:31.57#ibcon#*mode == 0, iclass 10, count 0 2006.173.07:48:31.57#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.07:48:31.57#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.07:48:31.57#ibcon#*before write, iclass 10, count 0 2006.173.07:48:31.57#ibcon#enter sib2, iclass 10, count 0 2006.173.07:48:31.57#ibcon#flushed, iclass 10, count 0 2006.173.07:48:31.57#ibcon#about to write, iclass 10, count 0 2006.173.07:48:31.57#ibcon#wrote, iclass 10, count 0 2006.173.07:48:31.57#ibcon#about to read 3, iclass 10, count 0 2006.173.07:48:31.61#ibcon#read 3, iclass 10, count 0 2006.173.07:48:31.61#ibcon#about to read 4, iclass 10, count 0 2006.173.07:48:31.61#ibcon#read 4, iclass 10, count 0 2006.173.07:48:31.61#ibcon#about to read 5, iclass 10, count 0 2006.173.07:48:31.61#ibcon#read 5, iclass 10, count 0 2006.173.07:48:31.61#ibcon#about to read 6, iclass 10, count 0 2006.173.07:48:31.61#ibcon#read 6, iclass 10, count 0 2006.173.07:48:31.61#ibcon#end of sib2, iclass 10, count 0 2006.173.07:48:31.61#ibcon#*after write, iclass 10, count 0 2006.173.07:48:31.61#ibcon#*before return 0, iclass 10, count 0 2006.173.07:48:31.61#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.07:48:31.61#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.07:48:31.61#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.07:48:31.61#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.07:48:31.61$vck44/va=5,4 2006.173.07:48:31.61#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.07:48:31.61#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.07:48:31.61#ibcon#ireg 11 cls_cnt 2 2006.173.07:48:31.61#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.07:48:31.67#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.07:48:31.67#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.07:48:31.67#ibcon#enter wrdev, iclass 12, count 2 2006.173.07:48:31.67#ibcon#first serial, iclass 12, count 2 2006.173.07:48:31.67#ibcon#enter sib2, iclass 12, count 2 2006.173.07:48:31.67#ibcon#flushed, iclass 12, count 2 2006.173.07:48:31.67#ibcon#about to write, iclass 12, count 2 2006.173.07:48:31.67#ibcon#wrote, iclass 12, count 2 2006.173.07:48:31.67#ibcon#about to read 3, iclass 12, count 2 2006.173.07:48:31.69#ibcon#read 3, iclass 12, count 2 2006.173.07:48:31.69#ibcon#about to read 4, iclass 12, count 2 2006.173.07:48:31.69#ibcon#read 4, iclass 12, count 2 2006.173.07:48:31.69#ibcon#about to read 5, iclass 12, count 2 2006.173.07:48:31.69#ibcon#read 5, iclass 12, count 2 2006.173.07:48:31.69#ibcon#about to read 6, iclass 12, count 2 2006.173.07:48:31.69#ibcon#read 6, iclass 12, count 2 2006.173.07:48:31.69#ibcon#end of sib2, iclass 12, count 2 2006.173.07:48:31.69#ibcon#*mode == 0, iclass 12, count 2 2006.173.07:48:31.69#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.07:48:31.69#ibcon#[25=AT05-04\r\n] 2006.173.07:48:31.69#ibcon#*before write, iclass 12, count 2 2006.173.07:48:31.69#ibcon#enter sib2, iclass 12, count 2 2006.173.07:48:31.69#ibcon#flushed, iclass 12, count 2 2006.173.07:48:31.69#ibcon#about to write, iclass 12, count 2 2006.173.07:48:31.69#ibcon#wrote, iclass 12, count 2 2006.173.07:48:31.69#ibcon#about to read 3, iclass 12, count 2 2006.173.07:48:31.72#ibcon#read 3, iclass 12, count 2 2006.173.07:48:31.72#ibcon#about to read 4, iclass 12, count 2 2006.173.07:48:31.72#ibcon#read 4, iclass 12, count 2 2006.173.07:48:31.72#ibcon#about to read 5, iclass 12, count 2 2006.173.07:48:31.72#ibcon#read 5, iclass 12, count 2 2006.173.07:48:31.72#ibcon#about to read 6, iclass 12, count 2 2006.173.07:48:31.72#ibcon#read 6, iclass 12, count 2 2006.173.07:48:31.72#ibcon#end of sib2, iclass 12, count 2 2006.173.07:48:31.72#ibcon#*after write, iclass 12, count 2 2006.173.07:48:31.72#ibcon#*before return 0, iclass 12, count 2 2006.173.07:48:31.72#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.07:48:31.72#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.07:48:31.72#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.07:48:31.72#ibcon#ireg 7 cls_cnt 0 2006.173.07:48:31.72#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.07:48:31.84#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.07:48:31.84#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.07:48:31.84#ibcon#enter wrdev, iclass 12, count 0 2006.173.07:48:31.84#ibcon#first serial, iclass 12, count 0 2006.173.07:48:31.84#ibcon#enter sib2, iclass 12, count 0 2006.173.07:48:31.84#ibcon#flushed, iclass 12, count 0 2006.173.07:48:31.84#ibcon#about to write, iclass 12, count 0 2006.173.07:48:31.84#ibcon#wrote, iclass 12, count 0 2006.173.07:48:31.84#ibcon#about to read 3, iclass 12, count 0 2006.173.07:48:31.86#ibcon#read 3, iclass 12, count 0 2006.173.07:48:31.86#ibcon#about to read 4, iclass 12, count 0 2006.173.07:48:31.86#ibcon#read 4, iclass 12, count 0 2006.173.07:48:31.86#ibcon#about to read 5, iclass 12, count 0 2006.173.07:48:31.86#ibcon#read 5, iclass 12, count 0 2006.173.07:48:31.86#ibcon#about to read 6, iclass 12, count 0 2006.173.07:48:31.86#ibcon#read 6, iclass 12, count 0 2006.173.07:48:31.86#ibcon#end of sib2, iclass 12, count 0 2006.173.07:48:31.86#ibcon#*mode == 0, iclass 12, count 0 2006.173.07:48:31.86#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.07:48:31.86#ibcon#[25=USB\r\n] 2006.173.07:48:31.86#ibcon#*before write, iclass 12, count 0 2006.173.07:48:31.86#ibcon#enter sib2, iclass 12, count 0 2006.173.07:48:31.86#ibcon#flushed, iclass 12, count 0 2006.173.07:48:31.86#ibcon#about to write, iclass 12, count 0 2006.173.07:48:31.86#ibcon#wrote, iclass 12, count 0 2006.173.07:48:31.86#ibcon#about to read 3, iclass 12, count 0 2006.173.07:48:31.89#ibcon#read 3, iclass 12, count 0 2006.173.07:48:31.89#ibcon#about to read 4, iclass 12, count 0 2006.173.07:48:31.89#ibcon#read 4, iclass 12, count 0 2006.173.07:48:31.89#ibcon#about to read 5, iclass 12, count 0 2006.173.07:48:31.89#ibcon#read 5, iclass 12, count 0 2006.173.07:48:31.89#ibcon#about to read 6, iclass 12, count 0 2006.173.07:48:31.89#ibcon#read 6, iclass 12, count 0 2006.173.07:48:31.89#ibcon#end of sib2, iclass 12, count 0 2006.173.07:48:31.89#ibcon#*after write, iclass 12, count 0 2006.173.07:48:31.89#ibcon#*before return 0, iclass 12, count 0 2006.173.07:48:31.89#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.07:48:31.89#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.07:48:31.89#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.07:48:31.89#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.07:48:31.89$vck44/valo=6,814.99 2006.173.07:48:31.89#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.07:48:31.89#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.07:48:31.89#ibcon#ireg 17 cls_cnt 0 2006.173.07:48:31.89#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.07:48:31.89#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.07:48:31.89#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.07:48:31.89#ibcon#enter wrdev, iclass 14, count 0 2006.173.07:48:31.89#ibcon#first serial, iclass 14, count 0 2006.173.07:48:31.89#ibcon#enter sib2, iclass 14, count 0 2006.173.07:48:31.89#ibcon#flushed, iclass 14, count 0 2006.173.07:48:31.89#ibcon#about to write, iclass 14, count 0 2006.173.07:48:31.89#ibcon#wrote, iclass 14, count 0 2006.173.07:48:31.89#ibcon#about to read 3, iclass 14, count 0 2006.173.07:48:31.91#ibcon#read 3, iclass 14, count 0 2006.173.07:48:31.91#ibcon#about to read 4, iclass 14, count 0 2006.173.07:48:31.91#ibcon#read 4, iclass 14, count 0 2006.173.07:48:31.91#ibcon#about to read 5, iclass 14, count 0 2006.173.07:48:31.91#ibcon#read 5, iclass 14, count 0 2006.173.07:48:31.91#ibcon#about to read 6, iclass 14, count 0 2006.173.07:48:31.91#ibcon#read 6, iclass 14, count 0 2006.173.07:48:31.91#ibcon#end of sib2, iclass 14, count 0 2006.173.07:48:31.91#ibcon#*mode == 0, iclass 14, count 0 2006.173.07:48:31.91#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.07:48:31.91#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.07:48:31.91#ibcon#*before write, iclass 14, count 0 2006.173.07:48:31.91#ibcon#enter sib2, iclass 14, count 0 2006.173.07:48:31.91#ibcon#flushed, iclass 14, count 0 2006.173.07:48:31.91#ibcon#about to write, iclass 14, count 0 2006.173.07:48:31.91#ibcon#wrote, iclass 14, count 0 2006.173.07:48:31.91#ibcon#about to read 3, iclass 14, count 0 2006.173.07:48:31.95#ibcon#read 3, iclass 14, count 0 2006.173.07:48:31.95#ibcon#about to read 4, iclass 14, count 0 2006.173.07:48:31.95#ibcon#read 4, iclass 14, count 0 2006.173.07:48:31.95#ibcon#about to read 5, iclass 14, count 0 2006.173.07:48:31.95#ibcon#read 5, iclass 14, count 0 2006.173.07:48:31.95#ibcon#about to read 6, iclass 14, count 0 2006.173.07:48:31.95#ibcon#read 6, iclass 14, count 0 2006.173.07:48:31.95#ibcon#end of sib2, iclass 14, count 0 2006.173.07:48:31.95#ibcon#*after write, iclass 14, count 0 2006.173.07:48:31.95#ibcon#*before return 0, iclass 14, count 0 2006.173.07:48:31.95#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.07:48:31.95#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.07:48:31.95#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.07:48:31.95#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.07:48:31.95$vck44/va=6,3 2006.173.07:48:31.95#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.07:48:31.95#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.07:48:31.95#ibcon#ireg 11 cls_cnt 2 2006.173.07:48:31.95#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.07:48:32.01#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.07:48:32.01#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.07:48:32.01#ibcon#enter wrdev, iclass 16, count 2 2006.173.07:48:32.01#ibcon#first serial, iclass 16, count 2 2006.173.07:48:32.01#ibcon#enter sib2, iclass 16, count 2 2006.173.07:48:32.01#ibcon#flushed, iclass 16, count 2 2006.173.07:48:32.01#ibcon#about to write, iclass 16, count 2 2006.173.07:48:32.01#ibcon#wrote, iclass 16, count 2 2006.173.07:48:32.01#ibcon#about to read 3, iclass 16, count 2 2006.173.07:48:32.03#ibcon#read 3, iclass 16, count 2 2006.173.07:48:32.03#ibcon#about to read 4, iclass 16, count 2 2006.173.07:48:32.03#ibcon#read 4, iclass 16, count 2 2006.173.07:48:32.03#ibcon#about to read 5, iclass 16, count 2 2006.173.07:48:32.03#ibcon#read 5, iclass 16, count 2 2006.173.07:48:32.03#ibcon#about to read 6, iclass 16, count 2 2006.173.07:48:32.03#ibcon#read 6, iclass 16, count 2 2006.173.07:48:32.03#ibcon#end of sib2, iclass 16, count 2 2006.173.07:48:32.03#ibcon#*mode == 0, iclass 16, count 2 2006.173.07:48:32.03#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.07:48:32.03#ibcon#[25=AT06-03\r\n] 2006.173.07:48:32.03#ibcon#*before write, iclass 16, count 2 2006.173.07:48:32.03#ibcon#enter sib2, iclass 16, count 2 2006.173.07:48:32.03#ibcon#flushed, iclass 16, count 2 2006.173.07:48:32.03#ibcon#about to write, iclass 16, count 2 2006.173.07:48:32.03#ibcon#wrote, iclass 16, count 2 2006.173.07:48:32.03#ibcon#about to read 3, iclass 16, count 2 2006.173.07:48:32.06#ibcon#read 3, iclass 16, count 2 2006.173.07:48:32.06#ibcon#about to read 4, iclass 16, count 2 2006.173.07:48:32.06#ibcon#read 4, iclass 16, count 2 2006.173.07:48:32.06#ibcon#about to read 5, iclass 16, count 2 2006.173.07:48:32.06#ibcon#read 5, iclass 16, count 2 2006.173.07:48:32.06#ibcon#about to read 6, iclass 16, count 2 2006.173.07:48:32.06#ibcon#read 6, iclass 16, count 2 2006.173.07:48:32.06#ibcon#end of sib2, iclass 16, count 2 2006.173.07:48:32.06#ibcon#*after write, iclass 16, count 2 2006.173.07:48:32.06#ibcon#*before return 0, iclass 16, count 2 2006.173.07:48:32.06#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.07:48:32.06#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.07:48:32.06#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.07:48:32.06#ibcon#ireg 7 cls_cnt 0 2006.173.07:48:32.06#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.07:48:32.18#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.07:48:32.18#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.07:48:32.18#ibcon#enter wrdev, iclass 16, count 0 2006.173.07:48:32.18#ibcon#first serial, iclass 16, count 0 2006.173.07:48:32.18#ibcon#enter sib2, iclass 16, count 0 2006.173.07:48:32.18#ibcon#flushed, iclass 16, count 0 2006.173.07:48:32.18#ibcon#about to write, iclass 16, count 0 2006.173.07:48:32.18#ibcon#wrote, iclass 16, count 0 2006.173.07:48:32.18#ibcon#about to read 3, iclass 16, count 0 2006.173.07:48:32.20#ibcon#read 3, iclass 16, count 0 2006.173.07:48:32.20#ibcon#about to read 4, iclass 16, count 0 2006.173.07:48:32.20#ibcon#read 4, iclass 16, count 0 2006.173.07:48:32.20#ibcon#about to read 5, iclass 16, count 0 2006.173.07:48:32.20#ibcon#read 5, iclass 16, count 0 2006.173.07:48:32.20#ibcon#about to read 6, iclass 16, count 0 2006.173.07:48:32.20#ibcon#read 6, iclass 16, count 0 2006.173.07:48:32.20#ibcon#end of sib2, iclass 16, count 0 2006.173.07:48:32.20#ibcon#*mode == 0, iclass 16, count 0 2006.173.07:48:32.20#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.07:48:32.20#ibcon#[25=USB\r\n] 2006.173.07:48:32.20#ibcon#*before write, iclass 16, count 0 2006.173.07:48:32.20#ibcon#enter sib2, iclass 16, count 0 2006.173.07:48:32.20#ibcon#flushed, iclass 16, count 0 2006.173.07:48:32.20#ibcon#about to write, iclass 16, count 0 2006.173.07:48:32.20#ibcon#wrote, iclass 16, count 0 2006.173.07:48:32.20#ibcon#about to read 3, iclass 16, count 0 2006.173.07:48:32.23#ibcon#read 3, iclass 16, count 0 2006.173.07:48:32.23#ibcon#about to read 4, iclass 16, count 0 2006.173.07:48:32.23#ibcon#read 4, iclass 16, count 0 2006.173.07:48:32.23#ibcon#about to read 5, iclass 16, count 0 2006.173.07:48:32.23#ibcon#read 5, iclass 16, count 0 2006.173.07:48:32.23#ibcon#about to read 6, iclass 16, count 0 2006.173.07:48:32.23#ibcon#read 6, iclass 16, count 0 2006.173.07:48:32.23#ibcon#end of sib2, iclass 16, count 0 2006.173.07:48:32.23#ibcon#*after write, iclass 16, count 0 2006.173.07:48:32.23#ibcon#*before return 0, iclass 16, count 0 2006.173.07:48:32.23#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.07:48:32.23#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.07:48:32.23#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.07:48:32.23#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.07:48:32.23$vck44/valo=7,864.99 2006.173.07:48:32.23#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.07:48:32.23#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.07:48:32.23#ibcon#ireg 17 cls_cnt 0 2006.173.07:48:32.23#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.07:48:32.23#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.07:48:32.23#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.07:48:32.23#ibcon#enter wrdev, iclass 18, count 0 2006.173.07:48:32.23#ibcon#first serial, iclass 18, count 0 2006.173.07:48:32.23#ibcon#enter sib2, iclass 18, count 0 2006.173.07:48:32.23#ibcon#flushed, iclass 18, count 0 2006.173.07:48:32.23#ibcon#about to write, iclass 18, count 0 2006.173.07:48:32.23#ibcon#wrote, iclass 18, count 0 2006.173.07:48:32.23#ibcon#about to read 3, iclass 18, count 0 2006.173.07:48:32.25#ibcon#read 3, iclass 18, count 0 2006.173.07:48:32.25#ibcon#about to read 4, iclass 18, count 0 2006.173.07:48:32.25#ibcon#read 4, iclass 18, count 0 2006.173.07:48:32.25#ibcon#about to read 5, iclass 18, count 0 2006.173.07:48:32.25#ibcon#read 5, iclass 18, count 0 2006.173.07:48:32.25#ibcon#about to read 6, iclass 18, count 0 2006.173.07:48:32.25#ibcon#read 6, iclass 18, count 0 2006.173.07:48:32.25#ibcon#end of sib2, iclass 18, count 0 2006.173.07:48:32.25#ibcon#*mode == 0, iclass 18, count 0 2006.173.07:48:32.25#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.07:48:32.25#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.07:48:32.25#ibcon#*before write, iclass 18, count 0 2006.173.07:48:32.25#ibcon#enter sib2, iclass 18, count 0 2006.173.07:48:32.25#ibcon#flushed, iclass 18, count 0 2006.173.07:48:32.25#ibcon#about to write, iclass 18, count 0 2006.173.07:48:32.25#ibcon#wrote, iclass 18, count 0 2006.173.07:48:32.25#ibcon#about to read 3, iclass 18, count 0 2006.173.07:48:32.29#ibcon#read 3, iclass 18, count 0 2006.173.07:48:32.29#ibcon#about to read 4, iclass 18, count 0 2006.173.07:48:32.29#ibcon#read 4, iclass 18, count 0 2006.173.07:48:32.29#ibcon#about to read 5, iclass 18, count 0 2006.173.07:48:32.29#ibcon#read 5, iclass 18, count 0 2006.173.07:48:32.29#ibcon#about to read 6, iclass 18, count 0 2006.173.07:48:32.29#ibcon#read 6, iclass 18, count 0 2006.173.07:48:32.29#ibcon#end of sib2, iclass 18, count 0 2006.173.07:48:32.29#ibcon#*after write, iclass 18, count 0 2006.173.07:48:32.29#ibcon#*before return 0, iclass 18, count 0 2006.173.07:48:32.29#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.07:48:32.29#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.07:48:32.29#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.07:48:32.29#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.07:48:32.29$vck44/va=7,4 2006.173.07:48:32.29#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.07:48:32.29#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.07:48:32.29#ibcon#ireg 11 cls_cnt 2 2006.173.07:48:32.29#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.07:48:32.35#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.07:48:32.35#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.07:48:32.35#ibcon#enter wrdev, iclass 20, count 2 2006.173.07:48:32.35#ibcon#first serial, iclass 20, count 2 2006.173.07:48:32.35#ibcon#enter sib2, iclass 20, count 2 2006.173.07:48:32.35#ibcon#flushed, iclass 20, count 2 2006.173.07:48:32.35#ibcon#about to write, iclass 20, count 2 2006.173.07:48:32.35#ibcon#wrote, iclass 20, count 2 2006.173.07:48:32.35#ibcon#about to read 3, iclass 20, count 2 2006.173.07:48:32.37#ibcon#read 3, iclass 20, count 2 2006.173.07:48:32.37#ibcon#about to read 4, iclass 20, count 2 2006.173.07:48:32.37#ibcon#read 4, iclass 20, count 2 2006.173.07:48:32.37#ibcon#about to read 5, iclass 20, count 2 2006.173.07:48:32.37#ibcon#read 5, iclass 20, count 2 2006.173.07:48:32.37#ibcon#about to read 6, iclass 20, count 2 2006.173.07:48:32.37#ibcon#read 6, iclass 20, count 2 2006.173.07:48:32.37#ibcon#end of sib2, iclass 20, count 2 2006.173.07:48:32.37#ibcon#*mode == 0, iclass 20, count 2 2006.173.07:48:32.37#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.07:48:32.37#ibcon#[25=AT07-04\r\n] 2006.173.07:48:32.37#ibcon#*before write, iclass 20, count 2 2006.173.07:48:32.37#ibcon#enter sib2, iclass 20, count 2 2006.173.07:48:32.37#ibcon#flushed, iclass 20, count 2 2006.173.07:48:32.37#ibcon#about to write, iclass 20, count 2 2006.173.07:48:32.37#ibcon#wrote, iclass 20, count 2 2006.173.07:48:32.37#ibcon#about to read 3, iclass 20, count 2 2006.173.07:48:32.40#ibcon#read 3, iclass 20, count 2 2006.173.07:48:32.40#ibcon#about to read 4, iclass 20, count 2 2006.173.07:48:32.40#ibcon#read 4, iclass 20, count 2 2006.173.07:48:32.40#ibcon#about to read 5, iclass 20, count 2 2006.173.07:48:32.40#ibcon#read 5, iclass 20, count 2 2006.173.07:48:32.40#ibcon#about to read 6, iclass 20, count 2 2006.173.07:48:32.40#ibcon#read 6, iclass 20, count 2 2006.173.07:48:32.40#ibcon#end of sib2, iclass 20, count 2 2006.173.07:48:32.40#ibcon#*after write, iclass 20, count 2 2006.173.07:48:32.40#ibcon#*before return 0, iclass 20, count 2 2006.173.07:48:32.40#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.07:48:32.40#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.07:48:32.40#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.07:48:32.40#ibcon#ireg 7 cls_cnt 0 2006.173.07:48:32.40#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.07:48:32.52#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.07:48:32.52#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.07:48:32.52#ibcon#enter wrdev, iclass 20, count 0 2006.173.07:48:32.52#ibcon#first serial, iclass 20, count 0 2006.173.07:48:32.52#ibcon#enter sib2, iclass 20, count 0 2006.173.07:48:32.52#ibcon#flushed, iclass 20, count 0 2006.173.07:48:32.52#ibcon#about to write, iclass 20, count 0 2006.173.07:48:32.52#ibcon#wrote, iclass 20, count 0 2006.173.07:48:32.52#ibcon#about to read 3, iclass 20, count 0 2006.173.07:48:32.54#ibcon#read 3, iclass 20, count 0 2006.173.07:48:32.54#ibcon#about to read 4, iclass 20, count 0 2006.173.07:48:32.54#ibcon#read 4, iclass 20, count 0 2006.173.07:48:32.54#ibcon#about to read 5, iclass 20, count 0 2006.173.07:48:32.54#ibcon#read 5, iclass 20, count 0 2006.173.07:48:32.54#ibcon#about to read 6, iclass 20, count 0 2006.173.07:48:32.54#ibcon#read 6, iclass 20, count 0 2006.173.07:48:32.54#ibcon#end of sib2, iclass 20, count 0 2006.173.07:48:32.54#ibcon#*mode == 0, iclass 20, count 0 2006.173.07:48:32.54#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.07:48:32.54#ibcon#[25=USB\r\n] 2006.173.07:48:32.54#ibcon#*before write, iclass 20, count 0 2006.173.07:48:32.54#ibcon#enter sib2, iclass 20, count 0 2006.173.07:48:32.54#ibcon#flushed, iclass 20, count 0 2006.173.07:48:32.54#ibcon#about to write, iclass 20, count 0 2006.173.07:48:32.54#ibcon#wrote, iclass 20, count 0 2006.173.07:48:32.54#ibcon#about to read 3, iclass 20, count 0 2006.173.07:48:32.57#ibcon#read 3, iclass 20, count 0 2006.173.07:48:32.57#ibcon#about to read 4, iclass 20, count 0 2006.173.07:48:32.57#ibcon#read 4, iclass 20, count 0 2006.173.07:48:32.57#ibcon#about to read 5, iclass 20, count 0 2006.173.07:48:32.57#ibcon#read 5, iclass 20, count 0 2006.173.07:48:32.57#ibcon#about to read 6, iclass 20, count 0 2006.173.07:48:32.57#ibcon#read 6, iclass 20, count 0 2006.173.07:48:32.57#ibcon#end of sib2, iclass 20, count 0 2006.173.07:48:32.57#ibcon#*after write, iclass 20, count 0 2006.173.07:48:32.57#ibcon#*before return 0, iclass 20, count 0 2006.173.07:48:32.57#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.07:48:32.57#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.07:48:32.57#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.07:48:32.57#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.07:48:32.57$vck44/valo=8,884.99 2006.173.07:48:32.57#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.07:48:32.57#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.07:48:32.57#ibcon#ireg 17 cls_cnt 0 2006.173.07:48:32.57#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.07:48:32.57#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.07:48:32.57#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.07:48:32.57#ibcon#enter wrdev, iclass 22, count 0 2006.173.07:48:32.57#ibcon#first serial, iclass 22, count 0 2006.173.07:48:32.57#ibcon#enter sib2, iclass 22, count 0 2006.173.07:48:32.57#ibcon#flushed, iclass 22, count 0 2006.173.07:48:32.57#ibcon#about to write, iclass 22, count 0 2006.173.07:48:32.57#ibcon#wrote, iclass 22, count 0 2006.173.07:48:32.57#ibcon#about to read 3, iclass 22, count 0 2006.173.07:48:32.59#ibcon#read 3, iclass 22, count 0 2006.173.07:48:32.59#ibcon#about to read 4, iclass 22, count 0 2006.173.07:48:32.59#ibcon#read 4, iclass 22, count 0 2006.173.07:48:32.59#ibcon#about to read 5, iclass 22, count 0 2006.173.07:48:32.59#ibcon#read 5, iclass 22, count 0 2006.173.07:48:32.59#ibcon#about to read 6, iclass 22, count 0 2006.173.07:48:32.59#ibcon#read 6, iclass 22, count 0 2006.173.07:48:32.59#ibcon#end of sib2, iclass 22, count 0 2006.173.07:48:32.59#ibcon#*mode == 0, iclass 22, count 0 2006.173.07:48:32.59#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.07:48:32.59#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.07:48:32.59#ibcon#*before write, iclass 22, count 0 2006.173.07:48:32.59#ibcon#enter sib2, iclass 22, count 0 2006.173.07:48:32.59#ibcon#flushed, iclass 22, count 0 2006.173.07:48:32.59#ibcon#about to write, iclass 22, count 0 2006.173.07:48:32.59#ibcon#wrote, iclass 22, count 0 2006.173.07:48:32.59#ibcon#about to read 3, iclass 22, count 0 2006.173.07:48:32.63#ibcon#read 3, iclass 22, count 0 2006.173.07:48:32.63#ibcon#about to read 4, iclass 22, count 0 2006.173.07:48:32.63#ibcon#read 4, iclass 22, count 0 2006.173.07:48:32.63#ibcon#about to read 5, iclass 22, count 0 2006.173.07:48:32.63#ibcon#read 5, iclass 22, count 0 2006.173.07:48:32.63#ibcon#about to read 6, iclass 22, count 0 2006.173.07:48:32.63#ibcon#read 6, iclass 22, count 0 2006.173.07:48:32.63#ibcon#end of sib2, iclass 22, count 0 2006.173.07:48:32.63#ibcon#*after write, iclass 22, count 0 2006.173.07:48:32.63#ibcon#*before return 0, iclass 22, count 0 2006.173.07:48:32.63#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.07:48:32.63#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.07:48:32.63#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.07:48:32.63#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.07:48:32.63$vck44/va=8,4 2006.173.07:48:32.63#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.07:48:32.63#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.07:48:32.63#ibcon#ireg 11 cls_cnt 2 2006.173.07:48:32.63#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.07:48:32.69#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.07:48:32.69#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.07:48:32.69#ibcon#enter wrdev, iclass 24, count 2 2006.173.07:48:32.69#ibcon#first serial, iclass 24, count 2 2006.173.07:48:32.69#ibcon#enter sib2, iclass 24, count 2 2006.173.07:48:32.69#ibcon#flushed, iclass 24, count 2 2006.173.07:48:32.69#ibcon#about to write, iclass 24, count 2 2006.173.07:48:32.69#ibcon#wrote, iclass 24, count 2 2006.173.07:48:32.69#ibcon#about to read 3, iclass 24, count 2 2006.173.07:48:32.71#ibcon#read 3, iclass 24, count 2 2006.173.07:48:32.71#ibcon#about to read 4, iclass 24, count 2 2006.173.07:48:32.71#ibcon#read 4, iclass 24, count 2 2006.173.07:48:32.71#ibcon#about to read 5, iclass 24, count 2 2006.173.07:48:32.71#ibcon#read 5, iclass 24, count 2 2006.173.07:48:32.71#ibcon#about to read 6, iclass 24, count 2 2006.173.07:48:32.71#ibcon#read 6, iclass 24, count 2 2006.173.07:48:32.71#ibcon#end of sib2, iclass 24, count 2 2006.173.07:48:32.71#ibcon#*mode == 0, iclass 24, count 2 2006.173.07:48:32.71#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.07:48:32.71#ibcon#[25=AT08-04\r\n] 2006.173.07:48:32.71#ibcon#*before write, iclass 24, count 2 2006.173.07:48:32.71#ibcon#enter sib2, iclass 24, count 2 2006.173.07:48:32.71#ibcon#flushed, iclass 24, count 2 2006.173.07:48:32.71#ibcon#about to write, iclass 24, count 2 2006.173.07:48:32.71#ibcon#wrote, iclass 24, count 2 2006.173.07:48:32.71#ibcon#about to read 3, iclass 24, count 2 2006.173.07:48:32.74#ibcon#read 3, iclass 24, count 2 2006.173.07:48:32.74#ibcon#about to read 4, iclass 24, count 2 2006.173.07:48:32.74#ibcon#read 4, iclass 24, count 2 2006.173.07:48:32.74#ibcon#about to read 5, iclass 24, count 2 2006.173.07:48:32.74#ibcon#read 5, iclass 24, count 2 2006.173.07:48:32.74#ibcon#about to read 6, iclass 24, count 2 2006.173.07:48:32.74#ibcon#read 6, iclass 24, count 2 2006.173.07:48:32.74#ibcon#end of sib2, iclass 24, count 2 2006.173.07:48:32.74#ibcon#*after write, iclass 24, count 2 2006.173.07:48:32.74#ibcon#*before return 0, iclass 24, count 2 2006.173.07:48:32.74#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.07:48:32.74#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.07:48:32.74#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.07:48:32.74#ibcon#ireg 7 cls_cnt 0 2006.173.07:48:32.74#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.07:48:32.86#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.07:48:32.86#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.07:48:32.86#ibcon#enter wrdev, iclass 24, count 0 2006.173.07:48:32.86#ibcon#first serial, iclass 24, count 0 2006.173.07:48:32.86#ibcon#enter sib2, iclass 24, count 0 2006.173.07:48:32.86#ibcon#flushed, iclass 24, count 0 2006.173.07:48:32.86#ibcon#about to write, iclass 24, count 0 2006.173.07:48:32.86#ibcon#wrote, iclass 24, count 0 2006.173.07:48:32.86#ibcon#about to read 3, iclass 24, count 0 2006.173.07:48:32.88#ibcon#read 3, iclass 24, count 0 2006.173.07:48:32.88#ibcon#about to read 4, iclass 24, count 0 2006.173.07:48:32.88#ibcon#read 4, iclass 24, count 0 2006.173.07:48:32.88#ibcon#about to read 5, iclass 24, count 0 2006.173.07:48:32.88#ibcon#read 5, iclass 24, count 0 2006.173.07:48:32.88#ibcon#about to read 6, iclass 24, count 0 2006.173.07:48:32.88#ibcon#read 6, iclass 24, count 0 2006.173.07:48:32.88#ibcon#end of sib2, iclass 24, count 0 2006.173.07:48:32.88#ibcon#*mode == 0, iclass 24, count 0 2006.173.07:48:32.88#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.07:48:32.88#ibcon#[25=USB\r\n] 2006.173.07:48:32.88#ibcon#*before write, iclass 24, count 0 2006.173.07:48:32.88#ibcon#enter sib2, iclass 24, count 0 2006.173.07:48:32.88#ibcon#flushed, iclass 24, count 0 2006.173.07:48:32.88#ibcon#about to write, iclass 24, count 0 2006.173.07:48:32.88#ibcon#wrote, iclass 24, count 0 2006.173.07:48:32.88#ibcon#about to read 3, iclass 24, count 0 2006.173.07:48:32.91#ibcon#read 3, iclass 24, count 0 2006.173.07:48:32.91#ibcon#about to read 4, iclass 24, count 0 2006.173.07:48:32.91#ibcon#read 4, iclass 24, count 0 2006.173.07:48:32.91#ibcon#about to read 5, iclass 24, count 0 2006.173.07:48:32.91#ibcon#read 5, iclass 24, count 0 2006.173.07:48:32.91#ibcon#about to read 6, iclass 24, count 0 2006.173.07:48:32.91#ibcon#read 6, iclass 24, count 0 2006.173.07:48:32.91#ibcon#end of sib2, iclass 24, count 0 2006.173.07:48:32.91#ibcon#*after write, iclass 24, count 0 2006.173.07:48:32.91#ibcon#*before return 0, iclass 24, count 0 2006.173.07:48:32.91#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.07:48:32.91#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.07:48:32.91#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.07:48:32.91#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.07:48:32.91$vck44/vblo=1,629.99 2006.173.07:48:32.91#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.07:48:32.91#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.07:48:32.91#ibcon#ireg 17 cls_cnt 0 2006.173.07:48:32.91#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.07:48:32.91#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.07:48:32.91#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.07:48:32.91#ibcon#enter wrdev, iclass 26, count 0 2006.173.07:48:32.91#ibcon#first serial, iclass 26, count 0 2006.173.07:48:32.91#ibcon#enter sib2, iclass 26, count 0 2006.173.07:48:32.91#ibcon#flushed, iclass 26, count 0 2006.173.07:48:32.91#ibcon#about to write, iclass 26, count 0 2006.173.07:48:32.91#ibcon#wrote, iclass 26, count 0 2006.173.07:48:32.91#ibcon#about to read 3, iclass 26, count 0 2006.173.07:48:32.93#ibcon#read 3, iclass 26, count 0 2006.173.07:48:32.93#ibcon#about to read 4, iclass 26, count 0 2006.173.07:48:32.93#ibcon#read 4, iclass 26, count 0 2006.173.07:48:32.93#ibcon#about to read 5, iclass 26, count 0 2006.173.07:48:32.93#ibcon#read 5, iclass 26, count 0 2006.173.07:48:32.93#ibcon#about to read 6, iclass 26, count 0 2006.173.07:48:32.93#ibcon#read 6, iclass 26, count 0 2006.173.07:48:32.93#ibcon#end of sib2, iclass 26, count 0 2006.173.07:48:32.93#ibcon#*mode == 0, iclass 26, count 0 2006.173.07:48:32.93#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.07:48:32.93#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.07:48:32.93#ibcon#*before write, iclass 26, count 0 2006.173.07:48:32.93#ibcon#enter sib2, iclass 26, count 0 2006.173.07:48:32.93#ibcon#flushed, iclass 26, count 0 2006.173.07:48:32.93#ibcon#about to write, iclass 26, count 0 2006.173.07:48:32.93#ibcon#wrote, iclass 26, count 0 2006.173.07:48:32.93#ibcon#about to read 3, iclass 26, count 0 2006.173.07:48:32.97#ibcon#read 3, iclass 26, count 0 2006.173.07:48:32.97#ibcon#about to read 4, iclass 26, count 0 2006.173.07:48:32.97#ibcon#read 4, iclass 26, count 0 2006.173.07:48:32.97#ibcon#about to read 5, iclass 26, count 0 2006.173.07:48:32.97#ibcon#read 5, iclass 26, count 0 2006.173.07:48:32.97#ibcon#about to read 6, iclass 26, count 0 2006.173.07:48:32.97#ibcon#read 6, iclass 26, count 0 2006.173.07:48:32.97#ibcon#end of sib2, iclass 26, count 0 2006.173.07:48:32.97#ibcon#*after write, iclass 26, count 0 2006.173.07:48:32.97#ibcon#*before return 0, iclass 26, count 0 2006.173.07:48:32.97#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.07:48:32.97#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.07:48:32.97#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.07:48:32.97#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.07:48:32.97$vck44/vb=1,4 2006.173.07:48:32.97#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.07:48:32.97#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.07:48:32.97#ibcon#ireg 11 cls_cnt 2 2006.173.07:48:32.97#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.07:48:32.97#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.07:48:32.97#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.07:48:32.97#ibcon#enter wrdev, iclass 28, count 2 2006.173.07:48:32.97#ibcon#first serial, iclass 28, count 2 2006.173.07:48:32.97#ibcon#enter sib2, iclass 28, count 2 2006.173.07:48:32.97#ibcon#flushed, iclass 28, count 2 2006.173.07:48:32.97#ibcon#about to write, iclass 28, count 2 2006.173.07:48:32.97#ibcon#wrote, iclass 28, count 2 2006.173.07:48:32.97#ibcon#about to read 3, iclass 28, count 2 2006.173.07:48:32.99#ibcon#read 3, iclass 28, count 2 2006.173.07:48:32.99#ibcon#about to read 4, iclass 28, count 2 2006.173.07:48:32.99#ibcon#read 4, iclass 28, count 2 2006.173.07:48:32.99#ibcon#about to read 5, iclass 28, count 2 2006.173.07:48:32.99#ibcon#read 5, iclass 28, count 2 2006.173.07:48:32.99#ibcon#about to read 6, iclass 28, count 2 2006.173.07:48:32.99#ibcon#read 6, iclass 28, count 2 2006.173.07:48:32.99#ibcon#end of sib2, iclass 28, count 2 2006.173.07:48:32.99#ibcon#*mode == 0, iclass 28, count 2 2006.173.07:48:32.99#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.07:48:32.99#ibcon#[27=AT01-04\r\n] 2006.173.07:48:32.99#ibcon#*before write, iclass 28, count 2 2006.173.07:48:32.99#ibcon#enter sib2, iclass 28, count 2 2006.173.07:48:32.99#ibcon#flushed, iclass 28, count 2 2006.173.07:48:32.99#ibcon#about to write, iclass 28, count 2 2006.173.07:48:32.99#ibcon#wrote, iclass 28, count 2 2006.173.07:48:32.99#ibcon#about to read 3, iclass 28, count 2 2006.173.07:48:33.02#ibcon#read 3, iclass 28, count 2 2006.173.07:48:33.02#ibcon#about to read 4, iclass 28, count 2 2006.173.07:48:33.02#ibcon#read 4, iclass 28, count 2 2006.173.07:48:33.02#ibcon#about to read 5, iclass 28, count 2 2006.173.07:48:33.02#ibcon#read 5, iclass 28, count 2 2006.173.07:48:33.02#ibcon#about to read 6, iclass 28, count 2 2006.173.07:48:33.02#ibcon#read 6, iclass 28, count 2 2006.173.07:48:33.02#ibcon#end of sib2, iclass 28, count 2 2006.173.07:48:33.02#ibcon#*after write, iclass 28, count 2 2006.173.07:48:33.02#ibcon#*before return 0, iclass 28, count 2 2006.173.07:48:33.02#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.07:48:33.02#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.07:48:33.02#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.07:48:33.02#ibcon#ireg 7 cls_cnt 0 2006.173.07:48:33.02#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.07:48:33.14#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.07:48:33.14#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.07:48:33.14#ibcon#enter wrdev, iclass 28, count 0 2006.173.07:48:33.14#ibcon#first serial, iclass 28, count 0 2006.173.07:48:33.14#ibcon#enter sib2, iclass 28, count 0 2006.173.07:48:33.14#ibcon#flushed, iclass 28, count 0 2006.173.07:48:33.14#ibcon#about to write, iclass 28, count 0 2006.173.07:48:33.14#ibcon#wrote, iclass 28, count 0 2006.173.07:48:33.14#ibcon#about to read 3, iclass 28, count 0 2006.173.07:48:33.16#ibcon#read 3, iclass 28, count 0 2006.173.07:48:33.16#ibcon#about to read 4, iclass 28, count 0 2006.173.07:48:33.16#ibcon#read 4, iclass 28, count 0 2006.173.07:48:33.16#ibcon#about to read 5, iclass 28, count 0 2006.173.07:48:33.16#ibcon#read 5, iclass 28, count 0 2006.173.07:48:33.16#ibcon#about to read 6, iclass 28, count 0 2006.173.07:48:33.16#ibcon#read 6, iclass 28, count 0 2006.173.07:48:33.16#ibcon#end of sib2, iclass 28, count 0 2006.173.07:48:33.16#ibcon#*mode == 0, iclass 28, count 0 2006.173.07:48:33.16#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.07:48:33.16#ibcon#[27=USB\r\n] 2006.173.07:48:33.16#ibcon#*before write, iclass 28, count 0 2006.173.07:48:33.16#ibcon#enter sib2, iclass 28, count 0 2006.173.07:48:33.16#ibcon#flushed, iclass 28, count 0 2006.173.07:48:33.16#ibcon#about to write, iclass 28, count 0 2006.173.07:48:33.16#ibcon#wrote, iclass 28, count 0 2006.173.07:48:33.16#ibcon#about to read 3, iclass 28, count 0 2006.173.07:48:33.19#ibcon#read 3, iclass 28, count 0 2006.173.07:48:33.19#ibcon#about to read 4, iclass 28, count 0 2006.173.07:48:33.19#ibcon#read 4, iclass 28, count 0 2006.173.07:48:33.19#ibcon#about to read 5, iclass 28, count 0 2006.173.07:48:33.19#ibcon#read 5, iclass 28, count 0 2006.173.07:48:33.19#ibcon#about to read 6, iclass 28, count 0 2006.173.07:48:33.19#ibcon#read 6, iclass 28, count 0 2006.173.07:48:33.19#ibcon#end of sib2, iclass 28, count 0 2006.173.07:48:33.19#ibcon#*after write, iclass 28, count 0 2006.173.07:48:33.19#ibcon#*before return 0, iclass 28, count 0 2006.173.07:48:33.19#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.07:48:33.19#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.07:48:33.19#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.07:48:33.19#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.07:48:33.19$vck44/vblo=2,634.99 2006.173.07:48:33.19#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.07:48:33.19#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.07:48:33.19#ibcon#ireg 17 cls_cnt 0 2006.173.07:48:33.19#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.07:48:33.19#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.07:48:33.19#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.07:48:33.19#ibcon#enter wrdev, iclass 30, count 0 2006.173.07:48:33.19#ibcon#first serial, iclass 30, count 0 2006.173.07:48:33.19#ibcon#enter sib2, iclass 30, count 0 2006.173.07:48:33.19#ibcon#flushed, iclass 30, count 0 2006.173.07:48:33.19#ibcon#about to write, iclass 30, count 0 2006.173.07:48:33.19#ibcon#wrote, iclass 30, count 0 2006.173.07:48:33.19#ibcon#about to read 3, iclass 30, count 0 2006.173.07:48:33.21#ibcon#read 3, iclass 30, count 0 2006.173.07:48:33.21#ibcon#about to read 4, iclass 30, count 0 2006.173.07:48:33.21#ibcon#read 4, iclass 30, count 0 2006.173.07:48:33.21#ibcon#about to read 5, iclass 30, count 0 2006.173.07:48:33.21#ibcon#read 5, iclass 30, count 0 2006.173.07:48:33.21#ibcon#about to read 6, iclass 30, count 0 2006.173.07:48:33.21#ibcon#read 6, iclass 30, count 0 2006.173.07:48:33.21#ibcon#end of sib2, iclass 30, count 0 2006.173.07:48:33.21#ibcon#*mode == 0, iclass 30, count 0 2006.173.07:48:33.21#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.07:48:33.21#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.07:48:33.21#ibcon#*before write, iclass 30, count 0 2006.173.07:48:33.21#ibcon#enter sib2, iclass 30, count 0 2006.173.07:48:33.21#ibcon#flushed, iclass 30, count 0 2006.173.07:48:33.21#ibcon#about to write, iclass 30, count 0 2006.173.07:48:33.21#ibcon#wrote, iclass 30, count 0 2006.173.07:48:33.21#ibcon#about to read 3, iclass 30, count 0 2006.173.07:48:33.25#ibcon#read 3, iclass 30, count 0 2006.173.07:48:33.25#ibcon#about to read 4, iclass 30, count 0 2006.173.07:48:33.25#ibcon#read 4, iclass 30, count 0 2006.173.07:48:33.25#ibcon#about to read 5, iclass 30, count 0 2006.173.07:48:33.25#ibcon#read 5, iclass 30, count 0 2006.173.07:48:33.25#ibcon#about to read 6, iclass 30, count 0 2006.173.07:48:33.25#ibcon#read 6, iclass 30, count 0 2006.173.07:48:33.25#ibcon#end of sib2, iclass 30, count 0 2006.173.07:48:33.25#ibcon#*after write, iclass 30, count 0 2006.173.07:48:33.25#ibcon#*before return 0, iclass 30, count 0 2006.173.07:48:33.25#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.07:48:33.25#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.07:48:33.25#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.07:48:33.25#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.07:48:33.25$vck44/vb=2,4 2006.173.07:48:33.25#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.173.07:48:33.25#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.173.07:48:33.25#ibcon#ireg 11 cls_cnt 2 2006.173.07:48:33.25#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.07:48:33.31#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.07:48:33.31#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.07:48:33.31#ibcon#enter wrdev, iclass 32, count 2 2006.173.07:48:33.31#ibcon#first serial, iclass 32, count 2 2006.173.07:48:33.31#ibcon#enter sib2, iclass 32, count 2 2006.173.07:48:33.31#ibcon#flushed, iclass 32, count 2 2006.173.07:48:33.31#ibcon#about to write, iclass 32, count 2 2006.173.07:48:33.31#ibcon#wrote, iclass 32, count 2 2006.173.07:48:33.31#ibcon#about to read 3, iclass 32, count 2 2006.173.07:48:33.33#ibcon#read 3, iclass 32, count 2 2006.173.07:48:33.33#ibcon#about to read 4, iclass 32, count 2 2006.173.07:48:33.33#ibcon#read 4, iclass 32, count 2 2006.173.07:48:33.33#ibcon#about to read 5, iclass 32, count 2 2006.173.07:48:33.33#ibcon#read 5, iclass 32, count 2 2006.173.07:48:33.33#ibcon#about to read 6, iclass 32, count 2 2006.173.07:48:33.33#ibcon#read 6, iclass 32, count 2 2006.173.07:48:33.33#ibcon#end of sib2, iclass 32, count 2 2006.173.07:48:33.33#ibcon#*mode == 0, iclass 32, count 2 2006.173.07:48:33.33#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.173.07:48:33.33#ibcon#[27=AT02-04\r\n] 2006.173.07:48:33.33#ibcon#*before write, iclass 32, count 2 2006.173.07:48:33.33#ibcon#enter sib2, iclass 32, count 2 2006.173.07:48:33.33#ibcon#flushed, iclass 32, count 2 2006.173.07:48:33.33#ibcon#about to write, iclass 32, count 2 2006.173.07:48:33.33#ibcon#wrote, iclass 32, count 2 2006.173.07:48:33.33#ibcon#about to read 3, iclass 32, count 2 2006.173.07:48:33.36#ibcon#read 3, iclass 32, count 2 2006.173.07:48:33.36#ibcon#about to read 4, iclass 32, count 2 2006.173.07:48:33.36#ibcon#read 4, iclass 32, count 2 2006.173.07:48:33.36#ibcon#about to read 5, iclass 32, count 2 2006.173.07:48:33.36#ibcon#read 5, iclass 32, count 2 2006.173.07:48:33.36#ibcon#about to read 6, iclass 32, count 2 2006.173.07:48:33.36#ibcon#read 6, iclass 32, count 2 2006.173.07:48:33.36#ibcon#end of sib2, iclass 32, count 2 2006.173.07:48:33.36#ibcon#*after write, iclass 32, count 2 2006.173.07:48:33.36#ibcon#*before return 0, iclass 32, count 2 2006.173.07:48:33.36#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.07:48:33.36#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.173.07:48:33.36#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.173.07:48:33.36#ibcon#ireg 7 cls_cnt 0 2006.173.07:48:33.36#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.07:48:33.48#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.07:48:33.48#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.07:48:33.48#ibcon#enter wrdev, iclass 32, count 0 2006.173.07:48:33.48#ibcon#first serial, iclass 32, count 0 2006.173.07:48:33.48#ibcon#enter sib2, iclass 32, count 0 2006.173.07:48:33.48#ibcon#flushed, iclass 32, count 0 2006.173.07:48:33.48#ibcon#about to write, iclass 32, count 0 2006.173.07:48:33.48#ibcon#wrote, iclass 32, count 0 2006.173.07:48:33.48#ibcon#about to read 3, iclass 32, count 0 2006.173.07:48:33.50#ibcon#read 3, iclass 32, count 0 2006.173.07:48:33.50#ibcon#about to read 4, iclass 32, count 0 2006.173.07:48:33.50#ibcon#read 4, iclass 32, count 0 2006.173.07:48:33.50#ibcon#about to read 5, iclass 32, count 0 2006.173.07:48:33.50#ibcon#read 5, iclass 32, count 0 2006.173.07:48:33.50#ibcon#about to read 6, iclass 32, count 0 2006.173.07:48:33.50#ibcon#read 6, iclass 32, count 0 2006.173.07:48:33.50#ibcon#end of sib2, iclass 32, count 0 2006.173.07:48:33.50#ibcon#*mode == 0, iclass 32, count 0 2006.173.07:48:33.50#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.07:48:33.50#ibcon#[27=USB\r\n] 2006.173.07:48:33.50#ibcon#*before write, iclass 32, count 0 2006.173.07:48:33.50#ibcon#enter sib2, iclass 32, count 0 2006.173.07:48:33.50#ibcon#flushed, iclass 32, count 0 2006.173.07:48:33.50#ibcon#about to write, iclass 32, count 0 2006.173.07:48:33.50#ibcon#wrote, iclass 32, count 0 2006.173.07:48:33.50#ibcon#about to read 3, iclass 32, count 0 2006.173.07:48:33.53#ibcon#read 3, iclass 32, count 0 2006.173.07:48:33.53#ibcon#about to read 4, iclass 32, count 0 2006.173.07:48:33.53#ibcon#read 4, iclass 32, count 0 2006.173.07:48:33.53#ibcon#about to read 5, iclass 32, count 0 2006.173.07:48:33.53#ibcon#read 5, iclass 32, count 0 2006.173.07:48:33.53#ibcon#about to read 6, iclass 32, count 0 2006.173.07:48:33.53#ibcon#read 6, iclass 32, count 0 2006.173.07:48:33.53#ibcon#end of sib2, iclass 32, count 0 2006.173.07:48:33.53#ibcon#*after write, iclass 32, count 0 2006.173.07:48:33.53#ibcon#*before return 0, iclass 32, count 0 2006.173.07:48:33.53#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.07:48:33.53#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.173.07:48:33.53#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.07:48:33.53#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.07:48:33.53$vck44/vblo=3,649.99 2006.173.07:48:33.53#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.07:48:33.53#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.07:48:33.53#ibcon#ireg 17 cls_cnt 0 2006.173.07:48:33.53#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.07:48:33.53#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.07:48:33.53#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.07:48:33.53#ibcon#enter wrdev, iclass 34, count 0 2006.173.07:48:33.53#ibcon#first serial, iclass 34, count 0 2006.173.07:48:33.53#ibcon#enter sib2, iclass 34, count 0 2006.173.07:48:33.53#ibcon#flushed, iclass 34, count 0 2006.173.07:48:33.53#ibcon#about to write, iclass 34, count 0 2006.173.07:48:33.53#ibcon#wrote, iclass 34, count 0 2006.173.07:48:33.53#ibcon#about to read 3, iclass 34, count 0 2006.173.07:48:33.55#ibcon#read 3, iclass 34, count 0 2006.173.07:48:33.55#ibcon#about to read 4, iclass 34, count 0 2006.173.07:48:33.55#ibcon#read 4, iclass 34, count 0 2006.173.07:48:33.55#ibcon#about to read 5, iclass 34, count 0 2006.173.07:48:33.55#ibcon#read 5, iclass 34, count 0 2006.173.07:48:33.55#ibcon#about to read 6, iclass 34, count 0 2006.173.07:48:33.55#ibcon#read 6, iclass 34, count 0 2006.173.07:48:33.55#ibcon#end of sib2, iclass 34, count 0 2006.173.07:48:33.55#ibcon#*mode == 0, iclass 34, count 0 2006.173.07:48:33.55#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.07:48:33.55#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.07:48:33.55#ibcon#*before write, iclass 34, count 0 2006.173.07:48:33.55#ibcon#enter sib2, iclass 34, count 0 2006.173.07:48:33.55#ibcon#flushed, iclass 34, count 0 2006.173.07:48:33.55#ibcon#about to write, iclass 34, count 0 2006.173.07:48:33.55#ibcon#wrote, iclass 34, count 0 2006.173.07:48:33.55#ibcon#about to read 3, iclass 34, count 0 2006.173.07:48:33.59#ibcon#read 3, iclass 34, count 0 2006.173.07:48:33.59#ibcon#about to read 4, iclass 34, count 0 2006.173.07:48:33.59#ibcon#read 4, iclass 34, count 0 2006.173.07:48:33.59#ibcon#about to read 5, iclass 34, count 0 2006.173.07:48:33.59#ibcon#read 5, iclass 34, count 0 2006.173.07:48:33.59#ibcon#about to read 6, iclass 34, count 0 2006.173.07:48:33.59#ibcon#read 6, iclass 34, count 0 2006.173.07:48:33.59#ibcon#end of sib2, iclass 34, count 0 2006.173.07:48:33.59#ibcon#*after write, iclass 34, count 0 2006.173.07:48:33.59#ibcon#*before return 0, iclass 34, count 0 2006.173.07:48:33.59#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.07:48:33.59#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.07:48:33.59#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.07:48:33.59#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.07:48:33.59$vck44/vb=3,4 2006.173.07:48:33.59#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.07:48:33.59#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.07:48:33.59#ibcon#ireg 11 cls_cnt 2 2006.173.07:48:33.59#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.07:48:33.65#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.07:48:33.65#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.07:48:33.65#ibcon#enter wrdev, iclass 36, count 2 2006.173.07:48:33.65#ibcon#first serial, iclass 36, count 2 2006.173.07:48:33.65#ibcon#enter sib2, iclass 36, count 2 2006.173.07:48:33.65#ibcon#flushed, iclass 36, count 2 2006.173.07:48:33.65#ibcon#about to write, iclass 36, count 2 2006.173.07:48:33.65#ibcon#wrote, iclass 36, count 2 2006.173.07:48:33.65#ibcon#about to read 3, iclass 36, count 2 2006.173.07:48:33.67#ibcon#read 3, iclass 36, count 2 2006.173.07:48:33.67#ibcon#about to read 4, iclass 36, count 2 2006.173.07:48:33.67#ibcon#read 4, iclass 36, count 2 2006.173.07:48:33.67#ibcon#about to read 5, iclass 36, count 2 2006.173.07:48:33.67#ibcon#read 5, iclass 36, count 2 2006.173.07:48:33.67#ibcon#about to read 6, iclass 36, count 2 2006.173.07:48:33.67#ibcon#read 6, iclass 36, count 2 2006.173.07:48:33.67#ibcon#end of sib2, iclass 36, count 2 2006.173.07:48:33.67#ibcon#*mode == 0, iclass 36, count 2 2006.173.07:48:33.67#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.07:48:33.67#ibcon#[27=AT03-04\r\n] 2006.173.07:48:33.67#ibcon#*before write, iclass 36, count 2 2006.173.07:48:33.67#ibcon#enter sib2, iclass 36, count 2 2006.173.07:48:33.67#ibcon#flushed, iclass 36, count 2 2006.173.07:48:33.67#ibcon#about to write, iclass 36, count 2 2006.173.07:48:33.67#ibcon#wrote, iclass 36, count 2 2006.173.07:48:33.67#ibcon#about to read 3, iclass 36, count 2 2006.173.07:48:33.70#ibcon#read 3, iclass 36, count 2 2006.173.07:48:33.70#ibcon#about to read 4, iclass 36, count 2 2006.173.07:48:33.70#ibcon#read 4, iclass 36, count 2 2006.173.07:48:33.70#ibcon#about to read 5, iclass 36, count 2 2006.173.07:48:33.70#ibcon#read 5, iclass 36, count 2 2006.173.07:48:33.70#ibcon#about to read 6, iclass 36, count 2 2006.173.07:48:33.70#ibcon#read 6, iclass 36, count 2 2006.173.07:48:33.70#ibcon#end of sib2, iclass 36, count 2 2006.173.07:48:33.70#ibcon#*after write, iclass 36, count 2 2006.173.07:48:33.70#ibcon#*before return 0, iclass 36, count 2 2006.173.07:48:33.70#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.07:48:33.70#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.07:48:33.70#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.07:48:33.70#ibcon#ireg 7 cls_cnt 0 2006.173.07:48:33.70#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.07:48:33.82#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.07:48:33.82#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.07:48:33.82#ibcon#enter wrdev, iclass 36, count 0 2006.173.07:48:33.82#ibcon#first serial, iclass 36, count 0 2006.173.07:48:33.82#ibcon#enter sib2, iclass 36, count 0 2006.173.07:48:33.82#ibcon#flushed, iclass 36, count 0 2006.173.07:48:33.82#ibcon#about to write, iclass 36, count 0 2006.173.07:48:33.82#ibcon#wrote, iclass 36, count 0 2006.173.07:48:33.82#ibcon#about to read 3, iclass 36, count 0 2006.173.07:48:33.84#ibcon#read 3, iclass 36, count 0 2006.173.07:48:33.84#ibcon#about to read 4, iclass 36, count 0 2006.173.07:48:33.84#ibcon#read 4, iclass 36, count 0 2006.173.07:48:33.84#ibcon#about to read 5, iclass 36, count 0 2006.173.07:48:33.84#ibcon#read 5, iclass 36, count 0 2006.173.07:48:33.84#ibcon#about to read 6, iclass 36, count 0 2006.173.07:48:33.84#ibcon#read 6, iclass 36, count 0 2006.173.07:48:33.84#ibcon#end of sib2, iclass 36, count 0 2006.173.07:48:33.84#ibcon#*mode == 0, iclass 36, count 0 2006.173.07:48:33.84#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.07:48:33.84#ibcon#[27=USB\r\n] 2006.173.07:48:33.84#ibcon#*before write, iclass 36, count 0 2006.173.07:48:33.84#ibcon#enter sib2, iclass 36, count 0 2006.173.07:48:33.84#ibcon#flushed, iclass 36, count 0 2006.173.07:48:33.84#ibcon#about to write, iclass 36, count 0 2006.173.07:48:33.84#ibcon#wrote, iclass 36, count 0 2006.173.07:48:33.84#ibcon#about to read 3, iclass 36, count 0 2006.173.07:48:33.87#ibcon#read 3, iclass 36, count 0 2006.173.07:48:33.87#ibcon#about to read 4, iclass 36, count 0 2006.173.07:48:33.87#ibcon#read 4, iclass 36, count 0 2006.173.07:48:33.87#ibcon#about to read 5, iclass 36, count 0 2006.173.07:48:33.87#ibcon#read 5, iclass 36, count 0 2006.173.07:48:33.87#ibcon#about to read 6, iclass 36, count 0 2006.173.07:48:33.87#ibcon#read 6, iclass 36, count 0 2006.173.07:48:33.87#ibcon#end of sib2, iclass 36, count 0 2006.173.07:48:33.87#ibcon#*after write, iclass 36, count 0 2006.173.07:48:33.87#ibcon#*before return 0, iclass 36, count 0 2006.173.07:48:33.87#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.07:48:33.87#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.07:48:33.87#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.07:48:33.87#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.07:48:33.87$vck44/vblo=4,679.99 2006.173.07:48:33.87#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.07:48:33.87#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.07:48:33.87#ibcon#ireg 17 cls_cnt 0 2006.173.07:48:33.87#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.07:48:33.87#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.07:48:33.87#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.07:48:33.87#ibcon#enter wrdev, iclass 38, count 0 2006.173.07:48:33.87#ibcon#first serial, iclass 38, count 0 2006.173.07:48:33.87#ibcon#enter sib2, iclass 38, count 0 2006.173.07:48:33.87#ibcon#flushed, iclass 38, count 0 2006.173.07:48:33.87#ibcon#about to write, iclass 38, count 0 2006.173.07:48:33.87#ibcon#wrote, iclass 38, count 0 2006.173.07:48:33.87#ibcon#about to read 3, iclass 38, count 0 2006.173.07:48:33.89#ibcon#read 3, iclass 38, count 0 2006.173.07:48:33.89#ibcon#about to read 4, iclass 38, count 0 2006.173.07:48:33.89#ibcon#read 4, iclass 38, count 0 2006.173.07:48:33.89#ibcon#about to read 5, iclass 38, count 0 2006.173.07:48:33.89#ibcon#read 5, iclass 38, count 0 2006.173.07:48:33.89#ibcon#about to read 6, iclass 38, count 0 2006.173.07:48:33.89#ibcon#read 6, iclass 38, count 0 2006.173.07:48:33.89#ibcon#end of sib2, iclass 38, count 0 2006.173.07:48:33.89#ibcon#*mode == 0, iclass 38, count 0 2006.173.07:48:33.89#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.07:48:33.89#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.07:48:33.89#ibcon#*before write, iclass 38, count 0 2006.173.07:48:33.89#ibcon#enter sib2, iclass 38, count 0 2006.173.07:48:33.89#ibcon#flushed, iclass 38, count 0 2006.173.07:48:33.89#ibcon#about to write, iclass 38, count 0 2006.173.07:48:33.89#ibcon#wrote, iclass 38, count 0 2006.173.07:48:33.89#ibcon#about to read 3, iclass 38, count 0 2006.173.07:48:33.93#ibcon#read 3, iclass 38, count 0 2006.173.07:48:33.93#ibcon#about to read 4, iclass 38, count 0 2006.173.07:48:33.93#ibcon#read 4, iclass 38, count 0 2006.173.07:48:33.93#ibcon#about to read 5, iclass 38, count 0 2006.173.07:48:33.93#ibcon#read 5, iclass 38, count 0 2006.173.07:48:33.93#ibcon#about to read 6, iclass 38, count 0 2006.173.07:48:33.93#ibcon#read 6, iclass 38, count 0 2006.173.07:48:33.93#ibcon#end of sib2, iclass 38, count 0 2006.173.07:48:33.93#ibcon#*after write, iclass 38, count 0 2006.173.07:48:33.93#ibcon#*before return 0, iclass 38, count 0 2006.173.07:48:33.93#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.07:48:33.93#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.07:48:33.93#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.07:48:33.93#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.07:48:33.93$vck44/vb=4,4 2006.173.07:48:33.93#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.07:48:33.93#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.07:48:33.93#ibcon#ireg 11 cls_cnt 2 2006.173.07:48:33.93#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.07:48:33.98#abcon#<5=/02 0.5 1.1 23.59 821004.3\r\n> 2006.173.07:48:33.99#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.07:48:33.99#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.07:48:33.99#ibcon#enter wrdev, iclass 40, count 2 2006.173.07:48:33.99#ibcon#first serial, iclass 40, count 2 2006.173.07:48:33.99#ibcon#enter sib2, iclass 40, count 2 2006.173.07:48:33.99#ibcon#flushed, iclass 40, count 2 2006.173.07:48:33.99#ibcon#about to write, iclass 40, count 2 2006.173.07:48:33.99#ibcon#wrote, iclass 40, count 2 2006.173.07:48:33.99#ibcon#about to read 3, iclass 40, count 2 2006.173.07:48:34.00#abcon#{5=INTERFACE CLEAR} 2006.173.07:48:34.01#ibcon#read 3, iclass 40, count 2 2006.173.07:48:34.01#ibcon#about to read 4, iclass 40, count 2 2006.173.07:48:34.01#ibcon#read 4, iclass 40, count 2 2006.173.07:48:34.01#ibcon#about to read 5, iclass 40, count 2 2006.173.07:48:34.01#ibcon#read 5, iclass 40, count 2 2006.173.07:48:34.01#ibcon#about to read 6, iclass 40, count 2 2006.173.07:48:34.01#ibcon#read 6, iclass 40, count 2 2006.173.07:48:34.01#ibcon#end of sib2, iclass 40, count 2 2006.173.07:48:34.01#ibcon#*mode == 0, iclass 40, count 2 2006.173.07:48:34.01#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.07:48:34.01#ibcon#[27=AT04-04\r\n] 2006.173.07:48:34.01#ibcon#*before write, iclass 40, count 2 2006.173.07:48:34.01#ibcon#enter sib2, iclass 40, count 2 2006.173.07:48:34.01#ibcon#flushed, iclass 40, count 2 2006.173.07:48:34.01#ibcon#about to write, iclass 40, count 2 2006.173.07:48:34.01#ibcon#wrote, iclass 40, count 2 2006.173.07:48:34.01#ibcon#about to read 3, iclass 40, count 2 2006.173.07:48:34.04#ibcon#read 3, iclass 40, count 2 2006.173.07:48:34.04#ibcon#about to read 4, iclass 40, count 2 2006.173.07:48:34.04#ibcon#read 4, iclass 40, count 2 2006.173.07:48:34.04#ibcon#about to read 5, iclass 40, count 2 2006.173.07:48:34.04#ibcon#read 5, iclass 40, count 2 2006.173.07:48:34.04#ibcon#about to read 6, iclass 40, count 2 2006.173.07:48:34.04#ibcon#read 6, iclass 40, count 2 2006.173.07:48:34.04#ibcon#end of sib2, iclass 40, count 2 2006.173.07:48:34.04#ibcon#*after write, iclass 40, count 2 2006.173.07:48:34.04#ibcon#*before return 0, iclass 40, count 2 2006.173.07:48:34.04#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.07:48:34.04#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.07:48:34.04#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.07:48:34.04#ibcon#ireg 7 cls_cnt 0 2006.173.07:48:34.04#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.07:48:34.06#abcon#[5=S1D000X0/0*\r\n] 2006.173.07:48:34.16#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.07:48:34.16#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.07:48:34.16#ibcon#enter wrdev, iclass 40, count 0 2006.173.07:48:34.16#ibcon#first serial, iclass 40, count 0 2006.173.07:48:34.16#ibcon#enter sib2, iclass 40, count 0 2006.173.07:48:34.16#ibcon#flushed, iclass 40, count 0 2006.173.07:48:34.16#ibcon#about to write, iclass 40, count 0 2006.173.07:48:34.16#ibcon#wrote, iclass 40, count 0 2006.173.07:48:34.16#ibcon#about to read 3, iclass 40, count 0 2006.173.07:48:34.18#ibcon#read 3, iclass 40, count 0 2006.173.07:48:34.18#ibcon#about to read 4, iclass 40, count 0 2006.173.07:48:34.18#ibcon#read 4, iclass 40, count 0 2006.173.07:48:34.18#ibcon#about to read 5, iclass 40, count 0 2006.173.07:48:34.18#ibcon#read 5, iclass 40, count 0 2006.173.07:48:34.18#ibcon#about to read 6, iclass 40, count 0 2006.173.07:48:34.18#ibcon#read 6, iclass 40, count 0 2006.173.07:48:34.18#ibcon#end of sib2, iclass 40, count 0 2006.173.07:48:34.18#ibcon#*mode == 0, iclass 40, count 0 2006.173.07:48:34.18#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.07:48:34.18#ibcon#[27=USB\r\n] 2006.173.07:48:34.18#ibcon#*before write, iclass 40, count 0 2006.173.07:48:34.18#ibcon#enter sib2, iclass 40, count 0 2006.173.07:48:34.18#ibcon#flushed, iclass 40, count 0 2006.173.07:48:34.18#ibcon#about to write, iclass 40, count 0 2006.173.07:48:34.18#ibcon#wrote, iclass 40, count 0 2006.173.07:48:34.18#ibcon#about to read 3, iclass 40, count 0 2006.173.07:48:34.21#ibcon#read 3, iclass 40, count 0 2006.173.07:48:34.21#ibcon#about to read 4, iclass 40, count 0 2006.173.07:48:34.21#ibcon#read 4, iclass 40, count 0 2006.173.07:48:34.21#ibcon#about to read 5, iclass 40, count 0 2006.173.07:48:34.21#ibcon#read 5, iclass 40, count 0 2006.173.07:48:34.21#ibcon#about to read 6, iclass 40, count 0 2006.173.07:48:34.21#ibcon#read 6, iclass 40, count 0 2006.173.07:48:34.21#ibcon#end of sib2, iclass 40, count 0 2006.173.07:48:34.21#ibcon#*after write, iclass 40, count 0 2006.173.07:48:34.21#ibcon#*before return 0, iclass 40, count 0 2006.173.07:48:34.21#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.07:48:34.21#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.07:48:34.21#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.07:48:34.21#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.07:48:34.21$vck44/vblo=5,709.99 2006.173.07:48:34.21#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.07:48:34.21#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.07:48:34.21#ibcon#ireg 17 cls_cnt 0 2006.173.07:48:34.21#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.07:48:34.21#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.07:48:34.21#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.07:48:34.21#ibcon#enter wrdev, iclass 10, count 0 2006.173.07:48:34.21#ibcon#first serial, iclass 10, count 0 2006.173.07:48:34.21#ibcon#enter sib2, iclass 10, count 0 2006.173.07:48:34.21#ibcon#flushed, iclass 10, count 0 2006.173.07:48:34.21#ibcon#about to write, iclass 10, count 0 2006.173.07:48:34.21#ibcon#wrote, iclass 10, count 0 2006.173.07:48:34.21#ibcon#about to read 3, iclass 10, count 0 2006.173.07:48:34.23#ibcon#read 3, iclass 10, count 0 2006.173.07:48:34.23#ibcon#about to read 4, iclass 10, count 0 2006.173.07:48:34.23#ibcon#read 4, iclass 10, count 0 2006.173.07:48:34.23#ibcon#about to read 5, iclass 10, count 0 2006.173.07:48:34.23#ibcon#read 5, iclass 10, count 0 2006.173.07:48:34.23#ibcon#about to read 6, iclass 10, count 0 2006.173.07:48:34.23#ibcon#read 6, iclass 10, count 0 2006.173.07:48:34.23#ibcon#end of sib2, iclass 10, count 0 2006.173.07:48:34.23#ibcon#*mode == 0, iclass 10, count 0 2006.173.07:48:34.23#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.07:48:34.23#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.07:48:34.23#ibcon#*before write, iclass 10, count 0 2006.173.07:48:34.23#ibcon#enter sib2, iclass 10, count 0 2006.173.07:48:34.23#ibcon#flushed, iclass 10, count 0 2006.173.07:48:34.23#ibcon#about to write, iclass 10, count 0 2006.173.07:48:34.23#ibcon#wrote, iclass 10, count 0 2006.173.07:48:34.23#ibcon#about to read 3, iclass 10, count 0 2006.173.07:48:34.27#ibcon#read 3, iclass 10, count 0 2006.173.07:48:34.27#ibcon#about to read 4, iclass 10, count 0 2006.173.07:48:34.27#ibcon#read 4, iclass 10, count 0 2006.173.07:48:34.27#ibcon#about to read 5, iclass 10, count 0 2006.173.07:48:34.27#ibcon#read 5, iclass 10, count 0 2006.173.07:48:34.27#ibcon#about to read 6, iclass 10, count 0 2006.173.07:48:34.27#ibcon#read 6, iclass 10, count 0 2006.173.07:48:34.27#ibcon#end of sib2, iclass 10, count 0 2006.173.07:48:34.27#ibcon#*after write, iclass 10, count 0 2006.173.07:48:34.27#ibcon#*before return 0, iclass 10, count 0 2006.173.07:48:34.27#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.07:48:34.27#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.07:48:34.27#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.07:48:34.27#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.07:48:34.27$vck44/vb=5,4 2006.173.07:48:34.27#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.07:48:34.27#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.07:48:34.27#ibcon#ireg 11 cls_cnt 2 2006.173.07:48:34.27#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.07:48:34.33#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.07:48:34.33#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.07:48:34.33#ibcon#enter wrdev, iclass 12, count 2 2006.173.07:48:34.33#ibcon#first serial, iclass 12, count 2 2006.173.07:48:34.33#ibcon#enter sib2, iclass 12, count 2 2006.173.07:48:34.33#ibcon#flushed, iclass 12, count 2 2006.173.07:48:34.33#ibcon#about to write, iclass 12, count 2 2006.173.07:48:34.33#ibcon#wrote, iclass 12, count 2 2006.173.07:48:34.33#ibcon#about to read 3, iclass 12, count 2 2006.173.07:48:34.35#ibcon#read 3, iclass 12, count 2 2006.173.07:48:34.35#ibcon#about to read 4, iclass 12, count 2 2006.173.07:48:34.35#ibcon#read 4, iclass 12, count 2 2006.173.07:48:34.35#ibcon#about to read 5, iclass 12, count 2 2006.173.07:48:34.35#ibcon#read 5, iclass 12, count 2 2006.173.07:48:34.35#ibcon#about to read 6, iclass 12, count 2 2006.173.07:48:34.35#ibcon#read 6, iclass 12, count 2 2006.173.07:48:34.35#ibcon#end of sib2, iclass 12, count 2 2006.173.07:48:34.35#ibcon#*mode == 0, iclass 12, count 2 2006.173.07:48:34.35#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.07:48:34.35#ibcon#[27=AT05-04\r\n] 2006.173.07:48:34.35#ibcon#*before write, iclass 12, count 2 2006.173.07:48:34.35#ibcon#enter sib2, iclass 12, count 2 2006.173.07:48:34.35#ibcon#flushed, iclass 12, count 2 2006.173.07:48:34.35#ibcon#about to write, iclass 12, count 2 2006.173.07:48:34.35#ibcon#wrote, iclass 12, count 2 2006.173.07:48:34.35#ibcon#about to read 3, iclass 12, count 2 2006.173.07:48:34.38#ibcon#read 3, iclass 12, count 2 2006.173.07:48:34.38#ibcon#about to read 4, iclass 12, count 2 2006.173.07:48:34.38#ibcon#read 4, iclass 12, count 2 2006.173.07:48:34.38#ibcon#about to read 5, iclass 12, count 2 2006.173.07:48:34.38#ibcon#read 5, iclass 12, count 2 2006.173.07:48:34.38#ibcon#about to read 6, iclass 12, count 2 2006.173.07:48:34.38#ibcon#read 6, iclass 12, count 2 2006.173.07:48:34.38#ibcon#end of sib2, iclass 12, count 2 2006.173.07:48:34.38#ibcon#*after write, iclass 12, count 2 2006.173.07:48:34.38#ibcon#*before return 0, iclass 12, count 2 2006.173.07:48:34.38#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.07:48:34.38#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.07:48:34.38#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.07:48:34.38#ibcon#ireg 7 cls_cnt 0 2006.173.07:48:34.38#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.07:48:34.50#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.07:48:34.50#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.07:48:34.50#ibcon#enter wrdev, iclass 12, count 0 2006.173.07:48:34.50#ibcon#first serial, iclass 12, count 0 2006.173.07:48:34.50#ibcon#enter sib2, iclass 12, count 0 2006.173.07:48:34.50#ibcon#flushed, iclass 12, count 0 2006.173.07:48:34.50#ibcon#about to write, iclass 12, count 0 2006.173.07:48:34.50#ibcon#wrote, iclass 12, count 0 2006.173.07:48:34.50#ibcon#about to read 3, iclass 12, count 0 2006.173.07:48:34.52#ibcon#read 3, iclass 12, count 0 2006.173.07:48:34.52#ibcon#about to read 4, iclass 12, count 0 2006.173.07:48:34.52#ibcon#read 4, iclass 12, count 0 2006.173.07:48:34.52#ibcon#about to read 5, iclass 12, count 0 2006.173.07:48:34.52#ibcon#read 5, iclass 12, count 0 2006.173.07:48:34.52#ibcon#about to read 6, iclass 12, count 0 2006.173.07:48:34.52#ibcon#read 6, iclass 12, count 0 2006.173.07:48:34.52#ibcon#end of sib2, iclass 12, count 0 2006.173.07:48:34.52#ibcon#*mode == 0, iclass 12, count 0 2006.173.07:48:34.52#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.07:48:34.52#ibcon#[27=USB\r\n] 2006.173.07:48:34.52#ibcon#*before write, iclass 12, count 0 2006.173.07:48:34.52#ibcon#enter sib2, iclass 12, count 0 2006.173.07:48:34.52#ibcon#flushed, iclass 12, count 0 2006.173.07:48:34.52#ibcon#about to write, iclass 12, count 0 2006.173.07:48:34.52#ibcon#wrote, iclass 12, count 0 2006.173.07:48:34.52#ibcon#about to read 3, iclass 12, count 0 2006.173.07:48:34.55#ibcon#read 3, iclass 12, count 0 2006.173.07:48:34.55#ibcon#about to read 4, iclass 12, count 0 2006.173.07:48:34.55#ibcon#read 4, iclass 12, count 0 2006.173.07:48:34.55#ibcon#about to read 5, iclass 12, count 0 2006.173.07:48:34.55#ibcon#read 5, iclass 12, count 0 2006.173.07:48:34.55#ibcon#about to read 6, iclass 12, count 0 2006.173.07:48:34.55#ibcon#read 6, iclass 12, count 0 2006.173.07:48:34.55#ibcon#end of sib2, iclass 12, count 0 2006.173.07:48:34.55#ibcon#*after write, iclass 12, count 0 2006.173.07:48:34.55#ibcon#*before return 0, iclass 12, count 0 2006.173.07:48:34.55#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.07:48:34.55#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.07:48:34.55#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.07:48:34.55#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.07:48:34.55$vck44/vblo=6,719.99 2006.173.07:48:34.55#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.07:48:34.55#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.07:48:34.55#ibcon#ireg 17 cls_cnt 0 2006.173.07:48:34.55#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.07:48:34.55#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.07:48:34.55#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.07:48:34.55#ibcon#enter wrdev, iclass 14, count 0 2006.173.07:48:34.55#ibcon#first serial, iclass 14, count 0 2006.173.07:48:34.55#ibcon#enter sib2, iclass 14, count 0 2006.173.07:48:34.55#ibcon#flushed, iclass 14, count 0 2006.173.07:48:34.55#ibcon#about to write, iclass 14, count 0 2006.173.07:48:34.55#ibcon#wrote, iclass 14, count 0 2006.173.07:48:34.55#ibcon#about to read 3, iclass 14, count 0 2006.173.07:48:34.57#ibcon#read 3, iclass 14, count 0 2006.173.07:48:34.57#ibcon#about to read 4, iclass 14, count 0 2006.173.07:48:34.57#ibcon#read 4, iclass 14, count 0 2006.173.07:48:34.57#ibcon#about to read 5, iclass 14, count 0 2006.173.07:48:34.57#ibcon#read 5, iclass 14, count 0 2006.173.07:48:34.57#ibcon#about to read 6, iclass 14, count 0 2006.173.07:48:34.57#ibcon#read 6, iclass 14, count 0 2006.173.07:48:34.57#ibcon#end of sib2, iclass 14, count 0 2006.173.07:48:34.57#ibcon#*mode == 0, iclass 14, count 0 2006.173.07:48:34.57#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.07:48:34.57#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.07:48:34.57#ibcon#*before write, iclass 14, count 0 2006.173.07:48:34.57#ibcon#enter sib2, iclass 14, count 0 2006.173.07:48:34.57#ibcon#flushed, iclass 14, count 0 2006.173.07:48:34.57#ibcon#about to write, iclass 14, count 0 2006.173.07:48:34.57#ibcon#wrote, iclass 14, count 0 2006.173.07:48:34.57#ibcon#about to read 3, iclass 14, count 0 2006.173.07:48:34.61#ibcon#read 3, iclass 14, count 0 2006.173.07:48:34.61#ibcon#about to read 4, iclass 14, count 0 2006.173.07:48:34.61#ibcon#read 4, iclass 14, count 0 2006.173.07:48:34.61#ibcon#about to read 5, iclass 14, count 0 2006.173.07:48:34.61#ibcon#read 5, iclass 14, count 0 2006.173.07:48:34.61#ibcon#about to read 6, iclass 14, count 0 2006.173.07:48:34.61#ibcon#read 6, iclass 14, count 0 2006.173.07:48:34.61#ibcon#end of sib2, iclass 14, count 0 2006.173.07:48:34.61#ibcon#*after write, iclass 14, count 0 2006.173.07:48:34.61#ibcon#*before return 0, iclass 14, count 0 2006.173.07:48:34.61#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.07:48:34.61#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.07:48:34.61#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.07:48:34.61#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.07:48:34.61$vck44/vb=6,4 2006.173.07:48:34.61#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.07:48:34.61#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.07:48:34.61#ibcon#ireg 11 cls_cnt 2 2006.173.07:48:34.61#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.07:48:34.67#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.07:48:34.67#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.07:48:34.67#ibcon#enter wrdev, iclass 16, count 2 2006.173.07:48:34.67#ibcon#first serial, iclass 16, count 2 2006.173.07:48:34.67#ibcon#enter sib2, iclass 16, count 2 2006.173.07:48:34.67#ibcon#flushed, iclass 16, count 2 2006.173.07:48:34.67#ibcon#about to write, iclass 16, count 2 2006.173.07:48:34.67#ibcon#wrote, iclass 16, count 2 2006.173.07:48:34.67#ibcon#about to read 3, iclass 16, count 2 2006.173.07:48:34.69#ibcon#read 3, iclass 16, count 2 2006.173.07:48:34.69#ibcon#about to read 4, iclass 16, count 2 2006.173.07:48:34.69#ibcon#read 4, iclass 16, count 2 2006.173.07:48:34.69#ibcon#about to read 5, iclass 16, count 2 2006.173.07:48:34.69#ibcon#read 5, iclass 16, count 2 2006.173.07:48:34.69#ibcon#about to read 6, iclass 16, count 2 2006.173.07:48:34.69#ibcon#read 6, iclass 16, count 2 2006.173.07:48:34.69#ibcon#end of sib2, iclass 16, count 2 2006.173.07:48:34.69#ibcon#*mode == 0, iclass 16, count 2 2006.173.07:48:34.69#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.07:48:34.69#ibcon#[27=AT06-04\r\n] 2006.173.07:48:34.69#ibcon#*before write, iclass 16, count 2 2006.173.07:48:34.69#ibcon#enter sib2, iclass 16, count 2 2006.173.07:48:34.69#ibcon#flushed, iclass 16, count 2 2006.173.07:48:34.69#ibcon#about to write, iclass 16, count 2 2006.173.07:48:34.69#ibcon#wrote, iclass 16, count 2 2006.173.07:48:34.69#ibcon#about to read 3, iclass 16, count 2 2006.173.07:48:34.72#ibcon#read 3, iclass 16, count 2 2006.173.07:48:34.72#ibcon#about to read 4, iclass 16, count 2 2006.173.07:48:34.72#ibcon#read 4, iclass 16, count 2 2006.173.07:48:34.72#ibcon#about to read 5, iclass 16, count 2 2006.173.07:48:34.72#ibcon#read 5, iclass 16, count 2 2006.173.07:48:34.72#ibcon#about to read 6, iclass 16, count 2 2006.173.07:48:34.72#ibcon#read 6, iclass 16, count 2 2006.173.07:48:34.72#ibcon#end of sib2, iclass 16, count 2 2006.173.07:48:34.72#ibcon#*after write, iclass 16, count 2 2006.173.07:48:34.72#ibcon#*before return 0, iclass 16, count 2 2006.173.07:48:34.72#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.07:48:34.72#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.07:48:34.72#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.07:48:34.72#ibcon#ireg 7 cls_cnt 0 2006.173.07:48:34.72#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.07:48:34.84#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.07:48:34.84#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.07:48:34.84#ibcon#enter wrdev, iclass 16, count 0 2006.173.07:48:34.84#ibcon#first serial, iclass 16, count 0 2006.173.07:48:34.84#ibcon#enter sib2, iclass 16, count 0 2006.173.07:48:34.84#ibcon#flushed, iclass 16, count 0 2006.173.07:48:34.84#ibcon#about to write, iclass 16, count 0 2006.173.07:48:34.84#ibcon#wrote, iclass 16, count 0 2006.173.07:48:34.84#ibcon#about to read 3, iclass 16, count 0 2006.173.07:48:34.86#ibcon#read 3, iclass 16, count 0 2006.173.07:48:34.86#ibcon#about to read 4, iclass 16, count 0 2006.173.07:48:34.86#ibcon#read 4, iclass 16, count 0 2006.173.07:48:34.86#ibcon#about to read 5, iclass 16, count 0 2006.173.07:48:34.86#ibcon#read 5, iclass 16, count 0 2006.173.07:48:34.86#ibcon#about to read 6, iclass 16, count 0 2006.173.07:48:34.86#ibcon#read 6, iclass 16, count 0 2006.173.07:48:34.86#ibcon#end of sib2, iclass 16, count 0 2006.173.07:48:34.86#ibcon#*mode == 0, iclass 16, count 0 2006.173.07:48:34.86#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.07:48:34.86#ibcon#[27=USB\r\n] 2006.173.07:48:34.86#ibcon#*before write, iclass 16, count 0 2006.173.07:48:34.86#ibcon#enter sib2, iclass 16, count 0 2006.173.07:48:34.86#ibcon#flushed, iclass 16, count 0 2006.173.07:48:34.86#ibcon#about to write, iclass 16, count 0 2006.173.07:48:34.86#ibcon#wrote, iclass 16, count 0 2006.173.07:48:34.86#ibcon#about to read 3, iclass 16, count 0 2006.173.07:48:34.89#ibcon#read 3, iclass 16, count 0 2006.173.07:48:34.89#ibcon#about to read 4, iclass 16, count 0 2006.173.07:48:34.89#ibcon#read 4, iclass 16, count 0 2006.173.07:48:34.89#ibcon#about to read 5, iclass 16, count 0 2006.173.07:48:34.89#ibcon#read 5, iclass 16, count 0 2006.173.07:48:34.89#ibcon#about to read 6, iclass 16, count 0 2006.173.07:48:34.89#ibcon#read 6, iclass 16, count 0 2006.173.07:48:34.89#ibcon#end of sib2, iclass 16, count 0 2006.173.07:48:34.89#ibcon#*after write, iclass 16, count 0 2006.173.07:48:34.89#ibcon#*before return 0, iclass 16, count 0 2006.173.07:48:34.89#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.07:48:34.89#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.07:48:34.89#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.07:48:34.89#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.07:48:34.89$vck44/vblo=7,734.99 2006.173.07:48:34.89#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.07:48:34.89#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.07:48:34.89#ibcon#ireg 17 cls_cnt 0 2006.173.07:48:34.89#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.07:48:34.89#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.07:48:34.89#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.07:48:34.89#ibcon#enter wrdev, iclass 18, count 0 2006.173.07:48:34.89#ibcon#first serial, iclass 18, count 0 2006.173.07:48:34.89#ibcon#enter sib2, iclass 18, count 0 2006.173.07:48:34.89#ibcon#flushed, iclass 18, count 0 2006.173.07:48:34.89#ibcon#about to write, iclass 18, count 0 2006.173.07:48:34.89#ibcon#wrote, iclass 18, count 0 2006.173.07:48:34.89#ibcon#about to read 3, iclass 18, count 0 2006.173.07:48:34.91#ibcon#read 3, iclass 18, count 0 2006.173.07:48:34.91#ibcon#about to read 4, iclass 18, count 0 2006.173.07:48:34.91#ibcon#read 4, iclass 18, count 0 2006.173.07:48:34.91#ibcon#about to read 5, iclass 18, count 0 2006.173.07:48:34.91#ibcon#read 5, iclass 18, count 0 2006.173.07:48:34.91#ibcon#about to read 6, iclass 18, count 0 2006.173.07:48:34.91#ibcon#read 6, iclass 18, count 0 2006.173.07:48:34.91#ibcon#end of sib2, iclass 18, count 0 2006.173.07:48:34.91#ibcon#*mode == 0, iclass 18, count 0 2006.173.07:48:34.91#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.07:48:34.91#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.07:48:34.91#ibcon#*before write, iclass 18, count 0 2006.173.07:48:34.91#ibcon#enter sib2, iclass 18, count 0 2006.173.07:48:34.91#ibcon#flushed, iclass 18, count 0 2006.173.07:48:34.91#ibcon#about to write, iclass 18, count 0 2006.173.07:48:34.91#ibcon#wrote, iclass 18, count 0 2006.173.07:48:34.91#ibcon#about to read 3, iclass 18, count 0 2006.173.07:48:34.95#ibcon#read 3, iclass 18, count 0 2006.173.07:48:34.95#ibcon#about to read 4, iclass 18, count 0 2006.173.07:48:34.95#ibcon#read 4, iclass 18, count 0 2006.173.07:48:34.95#ibcon#about to read 5, iclass 18, count 0 2006.173.07:48:34.95#ibcon#read 5, iclass 18, count 0 2006.173.07:48:34.95#ibcon#about to read 6, iclass 18, count 0 2006.173.07:48:34.95#ibcon#read 6, iclass 18, count 0 2006.173.07:48:34.95#ibcon#end of sib2, iclass 18, count 0 2006.173.07:48:34.95#ibcon#*after write, iclass 18, count 0 2006.173.07:48:34.95#ibcon#*before return 0, iclass 18, count 0 2006.173.07:48:34.95#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.07:48:34.95#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.07:48:34.95#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.07:48:34.95#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.07:48:34.95$vck44/vb=7,4 2006.173.07:48:34.95#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.07:48:34.95#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.07:48:34.95#ibcon#ireg 11 cls_cnt 2 2006.173.07:48:34.95#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.07:48:35.01#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.07:48:35.01#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.07:48:35.01#ibcon#enter wrdev, iclass 20, count 2 2006.173.07:48:35.01#ibcon#first serial, iclass 20, count 2 2006.173.07:48:35.01#ibcon#enter sib2, iclass 20, count 2 2006.173.07:48:35.01#ibcon#flushed, iclass 20, count 2 2006.173.07:48:35.01#ibcon#about to write, iclass 20, count 2 2006.173.07:48:35.01#ibcon#wrote, iclass 20, count 2 2006.173.07:48:35.01#ibcon#about to read 3, iclass 20, count 2 2006.173.07:48:35.03#ibcon#read 3, iclass 20, count 2 2006.173.07:48:35.03#ibcon#about to read 4, iclass 20, count 2 2006.173.07:48:35.03#ibcon#read 4, iclass 20, count 2 2006.173.07:48:35.03#ibcon#about to read 5, iclass 20, count 2 2006.173.07:48:35.03#ibcon#read 5, iclass 20, count 2 2006.173.07:48:35.03#ibcon#about to read 6, iclass 20, count 2 2006.173.07:48:35.03#ibcon#read 6, iclass 20, count 2 2006.173.07:48:35.03#ibcon#end of sib2, iclass 20, count 2 2006.173.07:48:35.03#ibcon#*mode == 0, iclass 20, count 2 2006.173.07:48:35.03#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.07:48:35.03#ibcon#[27=AT07-04\r\n] 2006.173.07:48:35.03#ibcon#*before write, iclass 20, count 2 2006.173.07:48:35.03#ibcon#enter sib2, iclass 20, count 2 2006.173.07:48:35.03#ibcon#flushed, iclass 20, count 2 2006.173.07:48:35.03#ibcon#about to write, iclass 20, count 2 2006.173.07:48:35.03#ibcon#wrote, iclass 20, count 2 2006.173.07:48:35.03#ibcon#about to read 3, iclass 20, count 2 2006.173.07:48:35.06#ibcon#read 3, iclass 20, count 2 2006.173.07:48:35.06#ibcon#about to read 4, iclass 20, count 2 2006.173.07:48:35.06#ibcon#read 4, iclass 20, count 2 2006.173.07:48:35.06#ibcon#about to read 5, iclass 20, count 2 2006.173.07:48:35.06#ibcon#read 5, iclass 20, count 2 2006.173.07:48:35.06#ibcon#about to read 6, iclass 20, count 2 2006.173.07:48:35.06#ibcon#read 6, iclass 20, count 2 2006.173.07:48:35.06#ibcon#end of sib2, iclass 20, count 2 2006.173.07:48:35.06#ibcon#*after write, iclass 20, count 2 2006.173.07:48:35.06#ibcon#*before return 0, iclass 20, count 2 2006.173.07:48:35.06#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.07:48:35.06#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.07:48:35.06#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.07:48:35.06#ibcon#ireg 7 cls_cnt 0 2006.173.07:48:35.06#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.07:48:35.18#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.07:48:35.18#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.07:48:35.18#ibcon#enter wrdev, iclass 20, count 0 2006.173.07:48:35.18#ibcon#first serial, iclass 20, count 0 2006.173.07:48:35.18#ibcon#enter sib2, iclass 20, count 0 2006.173.07:48:35.18#ibcon#flushed, iclass 20, count 0 2006.173.07:48:35.18#ibcon#about to write, iclass 20, count 0 2006.173.07:48:35.18#ibcon#wrote, iclass 20, count 0 2006.173.07:48:35.18#ibcon#about to read 3, iclass 20, count 0 2006.173.07:48:35.20#ibcon#read 3, iclass 20, count 0 2006.173.07:48:35.20#ibcon#about to read 4, iclass 20, count 0 2006.173.07:48:35.20#ibcon#read 4, iclass 20, count 0 2006.173.07:48:35.20#ibcon#about to read 5, iclass 20, count 0 2006.173.07:48:35.20#ibcon#read 5, iclass 20, count 0 2006.173.07:48:35.20#ibcon#about to read 6, iclass 20, count 0 2006.173.07:48:35.20#ibcon#read 6, iclass 20, count 0 2006.173.07:48:35.20#ibcon#end of sib2, iclass 20, count 0 2006.173.07:48:35.20#ibcon#*mode == 0, iclass 20, count 0 2006.173.07:48:35.20#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.07:48:35.20#ibcon#[27=USB\r\n] 2006.173.07:48:35.20#ibcon#*before write, iclass 20, count 0 2006.173.07:48:35.20#ibcon#enter sib2, iclass 20, count 0 2006.173.07:48:35.20#ibcon#flushed, iclass 20, count 0 2006.173.07:48:35.20#ibcon#about to write, iclass 20, count 0 2006.173.07:48:35.20#ibcon#wrote, iclass 20, count 0 2006.173.07:48:35.20#ibcon#about to read 3, iclass 20, count 0 2006.173.07:48:35.23#ibcon#read 3, iclass 20, count 0 2006.173.07:48:35.23#ibcon#about to read 4, iclass 20, count 0 2006.173.07:48:35.23#ibcon#read 4, iclass 20, count 0 2006.173.07:48:35.23#ibcon#about to read 5, iclass 20, count 0 2006.173.07:48:35.23#ibcon#read 5, iclass 20, count 0 2006.173.07:48:35.23#ibcon#about to read 6, iclass 20, count 0 2006.173.07:48:35.23#ibcon#read 6, iclass 20, count 0 2006.173.07:48:35.23#ibcon#end of sib2, iclass 20, count 0 2006.173.07:48:35.23#ibcon#*after write, iclass 20, count 0 2006.173.07:48:35.23#ibcon#*before return 0, iclass 20, count 0 2006.173.07:48:35.23#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.07:48:35.23#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.07:48:35.23#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.07:48:35.23#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.07:48:35.23$vck44/vblo=8,744.99 2006.173.07:48:35.23#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.07:48:35.23#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.07:48:35.23#ibcon#ireg 17 cls_cnt 0 2006.173.07:48:35.23#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.07:48:35.23#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.07:48:35.23#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.07:48:35.23#ibcon#enter wrdev, iclass 22, count 0 2006.173.07:48:35.23#ibcon#first serial, iclass 22, count 0 2006.173.07:48:35.23#ibcon#enter sib2, iclass 22, count 0 2006.173.07:48:35.23#ibcon#flushed, iclass 22, count 0 2006.173.07:48:35.23#ibcon#about to write, iclass 22, count 0 2006.173.07:48:35.23#ibcon#wrote, iclass 22, count 0 2006.173.07:48:35.23#ibcon#about to read 3, iclass 22, count 0 2006.173.07:48:35.25#ibcon#read 3, iclass 22, count 0 2006.173.07:48:35.25#ibcon#about to read 4, iclass 22, count 0 2006.173.07:48:35.25#ibcon#read 4, iclass 22, count 0 2006.173.07:48:35.25#ibcon#about to read 5, iclass 22, count 0 2006.173.07:48:35.25#ibcon#read 5, iclass 22, count 0 2006.173.07:48:35.25#ibcon#about to read 6, iclass 22, count 0 2006.173.07:48:35.25#ibcon#read 6, iclass 22, count 0 2006.173.07:48:35.25#ibcon#end of sib2, iclass 22, count 0 2006.173.07:48:35.25#ibcon#*mode == 0, iclass 22, count 0 2006.173.07:48:35.25#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.07:48:35.25#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.07:48:35.25#ibcon#*before write, iclass 22, count 0 2006.173.07:48:35.25#ibcon#enter sib2, iclass 22, count 0 2006.173.07:48:35.25#ibcon#flushed, iclass 22, count 0 2006.173.07:48:35.25#ibcon#about to write, iclass 22, count 0 2006.173.07:48:35.25#ibcon#wrote, iclass 22, count 0 2006.173.07:48:35.25#ibcon#about to read 3, iclass 22, count 0 2006.173.07:48:35.29#ibcon#read 3, iclass 22, count 0 2006.173.07:48:35.29#ibcon#about to read 4, iclass 22, count 0 2006.173.07:48:35.29#ibcon#read 4, iclass 22, count 0 2006.173.07:48:35.29#ibcon#about to read 5, iclass 22, count 0 2006.173.07:48:35.29#ibcon#read 5, iclass 22, count 0 2006.173.07:48:35.29#ibcon#about to read 6, iclass 22, count 0 2006.173.07:48:35.29#ibcon#read 6, iclass 22, count 0 2006.173.07:48:35.29#ibcon#end of sib2, iclass 22, count 0 2006.173.07:48:35.29#ibcon#*after write, iclass 22, count 0 2006.173.07:48:35.29#ibcon#*before return 0, iclass 22, count 0 2006.173.07:48:35.29#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.07:48:35.29#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.07:48:35.29#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.07:48:35.29#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.07:48:35.29$vck44/vb=8,4 2006.173.07:48:35.29#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.07:48:35.29#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.07:48:35.29#ibcon#ireg 11 cls_cnt 2 2006.173.07:48:35.29#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.07:48:35.35#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.07:48:35.35#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.07:48:35.35#ibcon#enter wrdev, iclass 24, count 2 2006.173.07:48:35.35#ibcon#first serial, iclass 24, count 2 2006.173.07:48:35.35#ibcon#enter sib2, iclass 24, count 2 2006.173.07:48:35.35#ibcon#flushed, iclass 24, count 2 2006.173.07:48:35.35#ibcon#about to write, iclass 24, count 2 2006.173.07:48:35.35#ibcon#wrote, iclass 24, count 2 2006.173.07:48:35.35#ibcon#about to read 3, iclass 24, count 2 2006.173.07:48:35.37#ibcon#read 3, iclass 24, count 2 2006.173.07:48:35.37#ibcon#about to read 4, iclass 24, count 2 2006.173.07:48:35.37#ibcon#read 4, iclass 24, count 2 2006.173.07:48:35.37#ibcon#about to read 5, iclass 24, count 2 2006.173.07:48:35.37#ibcon#read 5, iclass 24, count 2 2006.173.07:48:35.37#ibcon#about to read 6, iclass 24, count 2 2006.173.07:48:35.37#ibcon#read 6, iclass 24, count 2 2006.173.07:48:35.37#ibcon#end of sib2, iclass 24, count 2 2006.173.07:48:35.37#ibcon#*mode == 0, iclass 24, count 2 2006.173.07:48:35.37#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.07:48:35.37#ibcon#[27=AT08-04\r\n] 2006.173.07:48:35.37#ibcon#*before write, iclass 24, count 2 2006.173.07:48:35.37#ibcon#enter sib2, iclass 24, count 2 2006.173.07:48:35.37#ibcon#flushed, iclass 24, count 2 2006.173.07:48:35.37#ibcon#about to write, iclass 24, count 2 2006.173.07:48:35.37#ibcon#wrote, iclass 24, count 2 2006.173.07:48:35.37#ibcon#about to read 3, iclass 24, count 2 2006.173.07:48:35.40#ibcon#read 3, iclass 24, count 2 2006.173.07:48:35.40#ibcon#about to read 4, iclass 24, count 2 2006.173.07:48:35.40#ibcon#read 4, iclass 24, count 2 2006.173.07:48:35.40#ibcon#about to read 5, iclass 24, count 2 2006.173.07:48:35.40#ibcon#read 5, iclass 24, count 2 2006.173.07:48:35.40#ibcon#about to read 6, iclass 24, count 2 2006.173.07:48:35.40#ibcon#read 6, iclass 24, count 2 2006.173.07:48:35.40#ibcon#end of sib2, iclass 24, count 2 2006.173.07:48:35.40#ibcon#*after write, iclass 24, count 2 2006.173.07:48:35.40#ibcon#*before return 0, iclass 24, count 2 2006.173.07:48:35.40#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.07:48:35.40#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.07:48:35.40#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.07:48:35.40#ibcon#ireg 7 cls_cnt 0 2006.173.07:48:35.40#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.07:48:35.52#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.07:48:35.52#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.07:48:35.52#ibcon#enter wrdev, iclass 24, count 0 2006.173.07:48:35.52#ibcon#first serial, iclass 24, count 0 2006.173.07:48:35.52#ibcon#enter sib2, iclass 24, count 0 2006.173.07:48:35.52#ibcon#flushed, iclass 24, count 0 2006.173.07:48:35.52#ibcon#about to write, iclass 24, count 0 2006.173.07:48:35.52#ibcon#wrote, iclass 24, count 0 2006.173.07:48:35.52#ibcon#about to read 3, iclass 24, count 0 2006.173.07:48:35.54#ibcon#read 3, iclass 24, count 0 2006.173.07:48:35.54#ibcon#about to read 4, iclass 24, count 0 2006.173.07:48:35.54#ibcon#read 4, iclass 24, count 0 2006.173.07:48:35.54#ibcon#about to read 5, iclass 24, count 0 2006.173.07:48:35.54#ibcon#read 5, iclass 24, count 0 2006.173.07:48:35.54#ibcon#about to read 6, iclass 24, count 0 2006.173.07:48:35.54#ibcon#read 6, iclass 24, count 0 2006.173.07:48:35.54#ibcon#end of sib2, iclass 24, count 0 2006.173.07:48:35.54#ibcon#*mode == 0, iclass 24, count 0 2006.173.07:48:35.54#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.07:48:35.54#ibcon#[27=USB\r\n] 2006.173.07:48:35.54#ibcon#*before write, iclass 24, count 0 2006.173.07:48:35.54#ibcon#enter sib2, iclass 24, count 0 2006.173.07:48:35.54#ibcon#flushed, iclass 24, count 0 2006.173.07:48:35.54#ibcon#about to write, iclass 24, count 0 2006.173.07:48:35.54#ibcon#wrote, iclass 24, count 0 2006.173.07:48:35.54#ibcon#about to read 3, iclass 24, count 0 2006.173.07:48:35.57#ibcon#read 3, iclass 24, count 0 2006.173.07:48:35.57#ibcon#about to read 4, iclass 24, count 0 2006.173.07:48:35.57#ibcon#read 4, iclass 24, count 0 2006.173.07:48:35.57#ibcon#about to read 5, iclass 24, count 0 2006.173.07:48:35.57#ibcon#read 5, iclass 24, count 0 2006.173.07:48:35.57#ibcon#about to read 6, iclass 24, count 0 2006.173.07:48:35.57#ibcon#read 6, iclass 24, count 0 2006.173.07:48:35.57#ibcon#end of sib2, iclass 24, count 0 2006.173.07:48:35.57#ibcon#*after write, iclass 24, count 0 2006.173.07:48:35.57#ibcon#*before return 0, iclass 24, count 0 2006.173.07:48:35.57#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.07:48:35.57#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.07:48:35.57#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.07:48:35.57#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.07:48:35.57$vck44/vabw=wide 2006.173.07:48:35.57#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.07:48:35.57#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.07:48:35.57#ibcon#ireg 8 cls_cnt 0 2006.173.07:48:35.57#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.07:48:35.57#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.07:48:35.57#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.07:48:35.57#ibcon#enter wrdev, iclass 26, count 0 2006.173.07:48:35.57#ibcon#first serial, iclass 26, count 0 2006.173.07:48:35.57#ibcon#enter sib2, iclass 26, count 0 2006.173.07:48:35.57#ibcon#flushed, iclass 26, count 0 2006.173.07:48:35.57#ibcon#about to write, iclass 26, count 0 2006.173.07:48:35.57#ibcon#wrote, iclass 26, count 0 2006.173.07:48:35.57#ibcon#about to read 3, iclass 26, count 0 2006.173.07:48:35.59#ibcon#read 3, iclass 26, count 0 2006.173.07:48:35.59#ibcon#about to read 4, iclass 26, count 0 2006.173.07:48:35.59#ibcon#read 4, iclass 26, count 0 2006.173.07:48:35.59#ibcon#about to read 5, iclass 26, count 0 2006.173.07:48:35.59#ibcon#read 5, iclass 26, count 0 2006.173.07:48:35.59#ibcon#about to read 6, iclass 26, count 0 2006.173.07:48:35.59#ibcon#read 6, iclass 26, count 0 2006.173.07:48:35.59#ibcon#end of sib2, iclass 26, count 0 2006.173.07:48:35.59#ibcon#*mode == 0, iclass 26, count 0 2006.173.07:48:35.59#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.07:48:35.59#ibcon#[25=BW32\r\n] 2006.173.07:48:35.59#ibcon#*before write, iclass 26, count 0 2006.173.07:48:35.59#ibcon#enter sib2, iclass 26, count 0 2006.173.07:48:35.59#ibcon#flushed, iclass 26, count 0 2006.173.07:48:35.59#ibcon#about to write, iclass 26, count 0 2006.173.07:48:35.59#ibcon#wrote, iclass 26, count 0 2006.173.07:48:35.59#ibcon#about to read 3, iclass 26, count 0 2006.173.07:48:35.62#ibcon#read 3, iclass 26, count 0 2006.173.07:48:35.62#ibcon#about to read 4, iclass 26, count 0 2006.173.07:48:35.62#ibcon#read 4, iclass 26, count 0 2006.173.07:48:35.62#ibcon#about to read 5, iclass 26, count 0 2006.173.07:48:35.62#ibcon#read 5, iclass 26, count 0 2006.173.07:48:35.62#ibcon#about to read 6, iclass 26, count 0 2006.173.07:48:35.62#ibcon#read 6, iclass 26, count 0 2006.173.07:48:35.62#ibcon#end of sib2, iclass 26, count 0 2006.173.07:48:35.62#ibcon#*after write, iclass 26, count 0 2006.173.07:48:35.62#ibcon#*before return 0, iclass 26, count 0 2006.173.07:48:35.62#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.07:48:35.62#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.07:48:35.62#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.07:48:35.62#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.07:48:35.62$vck44/vbbw=wide 2006.173.07:48:35.62#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.07:48:35.62#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.07:48:35.62#ibcon#ireg 8 cls_cnt 0 2006.173.07:48:35.62#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.07:48:35.69#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.07:48:35.69#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.07:48:35.69#ibcon#enter wrdev, iclass 28, count 0 2006.173.07:48:35.69#ibcon#first serial, iclass 28, count 0 2006.173.07:48:35.69#ibcon#enter sib2, iclass 28, count 0 2006.173.07:48:35.69#ibcon#flushed, iclass 28, count 0 2006.173.07:48:35.69#ibcon#about to write, iclass 28, count 0 2006.173.07:48:35.69#ibcon#wrote, iclass 28, count 0 2006.173.07:48:35.69#ibcon#about to read 3, iclass 28, count 0 2006.173.07:48:35.71#ibcon#read 3, iclass 28, count 0 2006.173.07:48:35.71#ibcon#about to read 4, iclass 28, count 0 2006.173.07:48:35.71#ibcon#read 4, iclass 28, count 0 2006.173.07:48:35.71#ibcon#about to read 5, iclass 28, count 0 2006.173.07:48:35.71#ibcon#read 5, iclass 28, count 0 2006.173.07:48:35.71#ibcon#about to read 6, iclass 28, count 0 2006.173.07:48:35.71#ibcon#read 6, iclass 28, count 0 2006.173.07:48:35.71#ibcon#end of sib2, iclass 28, count 0 2006.173.07:48:35.71#ibcon#*mode == 0, iclass 28, count 0 2006.173.07:48:35.71#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.07:48:35.71#ibcon#[27=BW32\r\n] 2006.173.07:48:35.71#ibcon#*before write, iclass 28, count 0 2006.173.07:48:35.71#ibcon#enter sib2, iclass 28, count 0 2006.173.07:48:35.71#ibcon#flushed, iclass 28, count 0 2006.173.07:48:35.71#ibcon#about to write, iclass 28, count 0 2006.173.07:48:35.71#ibcon#wrote, iclass 28, count 0 2006.173.07:48:35.71#ibcon#about to read 3, iclass 28, count 0 2006.173.07:48:35.74#ibcon#read 3, iclass 28, count 0 2006.173.07:48:35.74#ibcon#about to read 4, iclass 28, count 0 2006.173.07:48:35.74#ibcon#read 4, iclass 28, count 0 2006.173.07:48:35.74#ibcon#about to read 5, iclass 28, count 0 2006.173.07:48:35.74#ibcon#read 5, iclass 28, count 0 2006.173.07:48:35.74#ibcon#about to read 6, iclass 28, count 0 2006.173.07:48:35.74#ibcon#read 6, iclass 28, count 0 2006.173.07:48:35.74#ibcon#end of sib2, iclass 28, count 0 2006.173.07:48:35.74#ibcon#*after write, iclass 28, count 0 2006.173.07:48:35.74#ibcon#*before return 0, iclass 28, count 0 2006.173.07:48:35.74#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.07:48:35.74#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.07:48:35.74#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.07:48:35.74#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.07:48:35.74$setupk4/ifdk4 2006.173.07:48:35.74$ifdk4/lo= 2006.173.07:48:35.74$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.07:48:35.74$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.07:48:35.74$ifdk4/patch= 2006.173.07:48:35.74$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.07:48:35.74$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.07:48:35.74$setupk4/!*+20s 2006.173.07:48:44.15#abcon#<5=/02 0.5 1.1 23.58 821004.4\r\n> 2006.173.07:48:44.17#abcon#{5=INTERFACE CLEAR} 2006.173.07:48:44.23#abcon#[5=S1D000X0/0*\r\n] 2006.173.07:48:48.14#trakl#Source acquired 2006.173.07:48:50.14#flagr#flagr/antenna,acquired 2006.173.07:48:50.25$setupk4/"tpicd 2006.173.07:48:50.25$setupk4/echo=off 2006.173.07:48:50.25$setupk4/xlog=off 2006.173.07:48:50.25:!2006.173.07:55:15 2006.173.07:55:15.00:preob 2006.173.07:55:15.14/onsource/TRACKING 2006.173.07:55:15.14:!2006.173.07:55:25 2006.173.07:55:25.00:"tape 2006.173.07:55:25.00:"st=record 2006.173.07:55:25.00:data_valid=on 2006.173.07:55:25.00:midob 2006.173.07:55:26.14/onsource/TRACKING 2006.173.07:55:26.14/wx/23.54,1004.1,83 2006.173.07:55:26.32/cable/+6.5015E-03 2006.173.07:55:27.41/va/01,07,usb,yes,34,37 2006.173.07:55:27.41/va/02,06,usb,yes,34,35 2006.173.07:55:27.41/va/03,05,usb,yes,43,45 2006.173.07:55:27.41/va/04,06,usb,yes,34,36 2006.173.07:55:27.41/va/05,04,usb,yes,27,28 2006.173.07:55:27.41/va/06,03,usb,yes,38,38 2006.173.07:55:27.41/va/07,04,usb,yes,31,32 2006.173.07:55:27.41/va/08,04,usb,yes,26,32 2006.173.07:55:27.64/valo/01,524.99,yes,locked 2006.173.07:55:27.64/valo/02,534.99,yes,locked 2006.173.07:55:27.64/valo/03,564.99,yes,locked 2006.173.07:55:27.64/valo/04,624.99,yes,locked 2006.173.07:55:27.64/valo/05,734.99,yes,locked 2006.173.07:55:27.64/valo/06,814.99,yes,locked 2006.173.07:55:27.64/valo/07,864.99,yes,locked 2006.173.07:55:27.64/valo/08,884.99,yes,locked 2006.173.07:55:28.73/vb/01,04,usb,yes,28,26 2006.173.07:55:28.73/vb/02,04,usb,yes,31,31 2006.173.07:55:28.73/vb/03,04,usb,yes,28,31 2006.173.07:55:28.73/vb/04,04,usb,yes,32,31 2006.173.07:55:28.73/vb/05,04,usb,yes,25,27 2006.173.07:55:28.73/vb/06,04,usb,yes,29,25 2006.173.07:55:28.73/vb/07,04,usb,yes,29,29 2006.173.07:55:28.73/vb/08,04,usb,yes,27,30 2006.173.07:55:28.96/vblo/01,629.99,yes,locked 2006.173.07:55:28.96/vblo/02,634.99,yes,locked 2006.173.07:55:28.96/vblo/03,649.99,yes,locked 2006.173.07:55:28.96/vblo/04,679.99,yes,locked 2006.173.07:55:28.96/vblo/05,709.99,yes,locked 2006.173.07:55:28.96/vblo/06,719.99,yes,locked 2006.173.07:55:28.96/vblo/07,734.99,yes,locked 2006.173.07:55:28.96/vblo/08,744.99,yes,locked 2006.173.07:55:29.11/vabw/8 2006.173.07:55:29.26/vbbw/8 2006.173.07:55:29.42/xfe/off,on,15.0 2006.173.07:55:29.79/ifatt/23,28,28,28 2006.173.07:55:30.07/fmout-gps/S +3.90E-07 2006.173.07:55:30.12:!2006.173.08:01:25 2006.173.08:01:25.00:data_valid=off 2006.173.08:01:25.00:"et 2006.173.08:01:25.00:!+3s 2006.173.08:01:28.01:"tape 2006.173.08:01:28.01:postob 2006.173.08:01:28.20/cable/+6.5010E-03 2006.173.08:01:28.20/wx/23.55,1004.0,83 2006.173.08:01:29.07/fmout-gps/S +3.90E-07 2006.173.08:01:29.07:scan_name=173-0803,jd0606,370 2006.173.08:01:29.07:source=0059+581,010245.76,582411.1,2000.0,ccw 2006.173.08:01:29.13#flagr#flagr/antenna,new-source 2006.173.08:01:30.13:checkk5 2006.173.08:01:30.54/chk_autoobs//k5ts1/ autoobs is running! 2006.173.08:01:30.95/chk_autoobs//k5ts2/ autoobs is running! 2006.173.08:01:31.36/chk_autoobs//k5ts3/ autoobs is running! 2006.173.08:01:31.75/chk_autoobs//k5ts4/ autoobs is running! 2006.173.08:01:32.15/chk_obsdata//k5ts1/T1730755??a.dat file size is correct (nominal:1440MB, actual:1436MB). 2006.173.08:01:32.55/chk_obsdata//k5ts2/T1730755??b.dat file size is correct (nominal:1440MB, actual:1436MB). 2006.173.08:01:32.96/chk_obsdata//k5ts3/T1730755??c.dat file size is correct (nominal:1440MB, actual:1436MB). 2006.173.08:01:33.36/chk_obsdata//k5ts4/T1730755??d.dat file size is correct (nominal:1440MB, actual:1436MB). 2006.173.08:01:34.08/k5log//k5ts1_log_newline 2006.173.08:01:34.78/k5log//k5ts2_log_newline 2006.173.08:01:35.50/k5log//k5ts3_log_newline 2006.173.08:01:36.21/k5log//k5ts4_log_newline 2006.173.08:01:36.24/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.08:01:36.24:setupk4=1 2006.173.08:01:36.24$setupk4/echo=on 2006.173.08:01:36.24$setupk4/pcalon 2006.173.08:01:36.24$pcalon/"no phase cal control is implemented here 2006.173.08:01:36.24$setupk4/"tpicd=stop 2006.173.08:01:36.24$setupk4/"rec=synch_on 2006.173.08:01:36.24$setupk4/"rec_mode=128 2006.173.08:01:36.24$setupk4/!* 2006.173.08:01:36.24$setupk4/recpk4 2006.173.08:01:36.24$recpk4/recpatch= 2006.173.08:01:36.24$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.08:01:36.24$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.08:01:36.24$setupk4/vck44 2006.173.08:01:36.24$vck44/valo=1,524.99 2006.173.08:01:36.24#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.08:01:36.24#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.08:01:36.24#ibcon#ireg 17 cls_cnt 0 2006.173.08:01:36.24#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.08:01:36.24#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.08:01:36.24#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.08:01:36.24#ibcon#enter wrdev, iclass 13, count 0 2006.173.08:01:36.24#ibcon#first serial, iclass 13, count 0 2006.173.08:01:36.24#ibcon#enter sib2, iclass 13, count 0 2006.173.08:01:36.24#ibcon#flushed, iclass 13, count 0 2006.173.08:01:36.24#ibcon#about to write, iclass 13, count 0 2006.173.08:01:36.24#ibcon#wrote, iclass 13, count 0 2006.173.08:01:36.24#ibcon#about to read 3, iclass 13, count 0 2006.173.08:01:36.25#ibcon#read 3, iclass 13, count 0 2006.173.08:01:36.25#ibcon#about to read 4, iclass 13, count 0 2006.173.08:01:36.25#ibcon#read 4, iclass 13, count 0 2006.173.08:01:36.25#ibcon#about to read 5, iclass 13, count 0 2006.173.08:01:36.25#ibcon#read 5, iclass 13, count 0 2006.173.08:01:36.25#ibcon#about to read 6, iclass 13, count 0 2006.173.08:01:36.25#ibcon#read 6, iclass 13, count 0 2006.173.08:01:36.25#ibcon#end of sib2, iclass 13, count 0 2006.173.08:01:36.25#ibcon#*mode == 0, iclass 13, count 0 2006.173.08:01:36.25#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.08:01:36.25#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.08:01:36.25#ibcon#*before write, iclass 13, count 0 2006.173.08:01:36.25#ibcon#enter sib2, iclass 13, count 0 2006.173.08:01:36.25#ibcon#flushed, iclass 13, count 0 2006.173.08:01:36.25#ibcon#about to write, iclass 13, count 0 2006.173.08:01:36.25#ibcon#wrote, iclass 13, count 0 2006.173.08:01:36.25#ibcon#about to read 3, iclass 13, count 0 2006.173.08:01:36.30#ibcon#read 3, iclass 13, count 0 2006.173.08:01:36.30#ibcon#about to read 4, iclass 13, count 0 2006.173.08:01:36.30#ibcon#read 4, iclass 13, count 0 2006.173.08:01:36.30#ibcon#about to read 5, iclass 13, count 0 2006.173.08:01:36.30#ibcon#read 5, iclass 13, count 0 2006.173.08:01:36.30#ibcon#about to read 6, iclass 13, count 0 2006.173.08:01:36.30#ibcon#read 6, iclass 13, count 0 2006.173.08:01:36.30#ibcon#end of sib2, iclass 13, count 0 2006.173.08:01:36.30#ibcon#*after write, iclass 13, count 0 2006.173.08:01:36.30#ibcon#*before return 0, iclass 13, count 0 2006.173.08:01:36.30#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.08:01:36.30#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.08:01:36.30#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.08:01:36.30#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.08:01:36.30$vck44/va=1,7 2006.173.08:01:36.30#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.08:01:36.30#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.08:01:36.30#ibcon#ireg 11 cls_cnt 2 2006.173.08:01:36.30#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.08:01:36.30#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.08:01:36.30#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.08:01:36.30#ibcon#enter wrdev, iclass 15, count 2 2006.173.08:01:36.30#ibcon#first serial, iclass 15, count 2 2006.173.08:01:36.30#ibcon#enter sib2, iclass 15, count 2 2006.173.08:01:36.30#ibcon#flushed, iclass 15, count 2 2006.173.08:01:36.30#ibcon#about to write, iclass 15, count 2 2006.173.08:01:36.30#ibcon#wrote, iclass 15, count 2 2006.173.08:01:36.30#ibcon#about to read 3, iclass 15, count 2 2006.173.08:01:36.32#ibcon#read 3, iclass 15, count 2 2006.173.08:01:36.32#ibcon#about to read 4, iclass 15, count 2 2006.173.08:01:36.32#ibcon#read 4, iclass 15, count 2 2006.173.08:01:36.32#ibcon#about to read 5, iclass 15, count 2 2006.173.08:01:36.32#ibcon#read 5, iclass 15, count 2 2006.173.08:01:36.32#ibcon#about to read 6, iclass 15, count 2 2006.173.08:01:36.32#ibcon#read 6, iclass 15, count 2 2006.173.08:01:36.32#ibcon#end of sib2, iclass 15, count 2 2006.173.08:01:36.32#ibcon#*mode == 0, iclass 15, count 2 2006.173.08:01:36.32#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.08:01:36.32#ibcon#[25=AT01-07\r\n] 2006.173.08:01:36.32#ibcon#*before write, iclass 15, count 2 2006.173.08:01:36.32#ibcon#enter sib2, iclass 15, count 2 2006.173.08:01:36.32#ibcon#flushed, iclass 15, count 2 2006.173.08:01:36.32#ibcon#about to write, iclass 15, count 2 2006.173.08:01:36.32#ibcon#wrote, iclass 15, count 2 2006.173.08:01:36.32#ibcon#about to read 3, iclass 15, count 2 2006.173.08:01:36.35#ibcon#read 3, iclass 15, count 2 2006.173.08:01:36.35#ibcon#about to read 4, iclass 15, count 2 2006.173.08:01:36.35#ibcon#read 4, iclass 15, count 2 2006.173.08:01:36.35#ibcon#about to read 5, iclass 15, count 2 2006.173.08:01:36.35#ibcon#read 5, iclass 15, count 2 2006.173.08:01:36.35#ibcon#about to read 6, iclass 15, count 2 2006.173.08:01:36.35#ibcon#read 6, iclass 15, count 2 2006.173.08:01:36.35#ibcon#end of sib2, iclass 15, count 2 2006.173.08:01:36.35#ibcon#*after write, iclass 15, count 2 2006.173.08:01:36.35#ibcon#*before return 0, iclass 15, count 2 2006.173.08:01:36.35#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.08:01:36.35#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.08:01:36.35#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.08:01:36.35#ibcon#ireg 7 cls_cnt 0 2006.173.08:01:36.35#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.08:01:36.47#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.08:01:36.47#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.08:01:36.47#ibcon#enter wrdev, iclass 15, count 0 2006.173.08:01:36.47#ibcon#first serial, iclass 15, count 0 2006.173.08:01:36.47#ibcon#enter sib2, iclass 15, count 0 2006.173.08:01:36.47#ibcon#flushed, iclass 15, count 0 2006.173.08:01:36.47#ibcon#about to write, iclass 15, count 0 2006.173.08:01:36.47#ibcon#wrote, iclass 15, count 0 2006.173.08:01:36.47#ibcon#about to read 3, iclass 15, count 0 2006.173.08:01:36.49#ibcon#read 3, iclass 15, count 0 2006.173.08:01:36.49#ibcon#about to read 4, iclass 15, count 0 2006.173.08:01:36.49#ibcon#read 4, iclass 15, count 0 2006.173.08:01:36.49#ibcon#about to read 5, iclass 15, count 0 2006.173.08:01:36.49#ibcon#read 5, iclass 15, count 0 2006.173.08:01:36.49#ibcon#about to read 6, iclass 15, count 0 2006.173.08:01:36.49#ibcon#read 6, iclass 15, count 0 2006.173.08:01:36.49#ibcon#end of sib2, iclass 15, count 0 2006.173.08:01:36.49#ibcon#*mode == 0, iclass 15, count 0 2006.173.08:01:36.49#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.08:01:36.49#ibcon#[25=USB\r\n] 2006.173.08:01:36.49#ibcon#*before write, iclass 15, count 0 2006.173.08:01:36.49#ibcon#enter sib2, iclass 15, count 0 2006.173.08:01:36.49#ibcon#flushed, iclass 15, count 0 2006.173.08:01:36.49#ibcon#about to write, iclass 15, count 0 2006.173.08:01:36.49#ibcon#wrote, iclass 15, count 0 2006.173.08:01:36.49#ibcon#about to read 3, iclass 15, count 0 2006.173.08:01:36.52#ibcon#read 3, iclass 15, count 0 2006.173.08:01:36.52#ibcon#about to read 4, iclass 15, count 0 2006.173.08:01:36.52#ibcon#read 4, iclass 15, count 0 2006.173.08:01:36.52#ibcon#about to read 5, iclass 15, count 0 2006.173.08:01:36.52#ibcon#read 5, iclass 15, count 0 2006.173.08:01:36.52#ibcon#about to read 6, iclass 15, count 0 2006.173.08:01:36.52#ibcon#read 6, iclass 15, count 0 2006.173.08:01:36.52#ibcon#end of sib2, iclass 15, count 0 2006.173.08:01:36.52#ibcon#*after write, iclass 15, count 0 2006.173.08:01:36.52#ibcon#*before return 0, iclass 15, count 0 2006.173.08:01:36.52#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.08:01:36.52#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.08:01:36.52#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.08:01:36.52#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.08:01:36.52$vck44/valo=2,534.99 2006.173.08:01:36.52#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.08:01:36.52#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.08:01:36.52#ibcon#ireg 17 cls_cnt 0 2006.173.08:01:36.52#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.08:01:36.52#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.08:01:36.52#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.08:01:36.52#ibcon#enter wrdev, iclass 17, count 0 2006.173.08:01:36.52#ibcon#first serial, iclass 17, count 0 2006.173.08:01:36.52#ibcon#enter sib2, iclass 17, count 0 2006.173.08:01:36.52#ibcon#flushed, iclass 17, count 0 2006.173.08:01:36.52#ibcon#about to write, iclass 17, count 0 2006.173.08:01:36.52#ibcon#wrote, iclass 17, count 0 2006.173.08:01:36.52#ibcon#about to read 3, iclass 17, count 0 2006.173.08:01:36.54#ibcon#read 3, iclass 17, count 0 2006.173.08:01:36.54#ibcon#about to read 4, iclass 17, count 0 2006.173.08:01:36.54#ibcon#read 4, iclass 17, count 0 2006.173.08:01:36.54#ibcon#about to read 5, iclass 17, count 0 2006.173.08:01:36.54#ibcon#read 5, iclass 17, count 0 2006.173.08:01:36.54#ibcon#about to read 6, iclass 17, count 0 2006.173.08:01:36.54#ibcon#read 6, iclass 17, count 0 2006.173.08:01:36.54#ibcon#end of sib2, iclass 17, count 0 2006.173.08:01:36.54#ibcon#*mode == 0, iclass 17, count 0 2006.173.08:01:36.54#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.08:01:36.54#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.08:01:36.54#ibcon#*before write, iclass 17, count 0 2006.173.08:01:36.54#ibcon#enter sib2, iclass 17, count 0 2006.173.08:01:36.54#ibcon#flushed, iclass 17, count 0 2006.173.08:01:36.54#ibcon#about to write, iclass 17, count 0 2006.173.08:01:36.54#ibcon#wrote, iclass 17, count 0 2006.173.08:01:36.54#ibcon#about to read 3, iclass 17, count 0 2006.173.08:01:36.58#ibcon#read 3, iclass 17, count 0 2006.173.08:01:36.58#ibcon#about to read 4, iclass 17, count 0 2006.173.08:01:36.58#ibcon#read 4, iclass 17, count 0 2006.173.08:01:36.58#ibcon#about to read 5, iclass 17, count 0 2006.173.08:01:36.58#ibcon#read 5, iclass 17, count 0 2006.173.08:01:36.58#ibcon#about to read 6, iclass 17, count 0 2006.173.08:01:36.58#ibcon#read 6, iclass 17, count 0 2006.173.08:01:36.58#ibcon#end of sib2, iclass 17, count 0 2006.173.08:01:36.58#ibcon#*after write, iclass 17, count 0 2006.173.08:01:36.58#ibcon#*before return 0, iclass 17, count 0 2006.173.08:01:36.58#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.08:01:36.58#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.08:01:36.58#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.08:01:36.58#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.08:01:36.58$vck44/va=2,6 2006.173.08:01:36.58#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.08:01:36.58#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.08:01:36.58#ibcon#ireg 11 cls_cnt 2 2006.173.08:01:36.58#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.08:01:36.64#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.08:01:36.64#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.08:01:36.64#ibcon#enter wrdev, iclass 19, count 2 2006.173.08:01:36.64#ibcon#first serial, iclass 19, count 2 2006.173.08:01:36.64#ibcon#enter sib2, iclass 19, count 2 2006.173.08:01:36.64#ibcon#flushed, iclass 19, count 2 2006.173.08:01:36.64#ibcon#about to write, iclass 19, count 2 2006.173.08:01:36.64#ibcon#wrote, iclass 19, count 2 2006.173.08:01:36.64#ibcon#about to read 3, iclass 19, count 2 2006.173.08:01:36.66#ibcon#read 3, iclass 19, count 2 2006.173.08:01:36.66#ibcon#about to read 4, iclass 19, count 2 2006.173.08:01:36.66#ibcon#read 4, iclass 19, count 2 2006.173.08:01:36.66#ibcon#about to read 5, iclass 19, count 2 2006.173.08:01:36.66#ibcon#read 5, iclass 19, count 2 2006.173.08:01:36.66#ibcon#about to read 6, iclass 19, count 2 2006.173.08:01:36.66#ibcon#read 6, iclass 19, count 2 2006.173.08:01:36.66#ibcon#end of sib2, iclass 19, count 2 2006.173.08:01:36.66#ibcon#*mode == 0, iclass 19, count 2 2006.173.08:01:36.66#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.08:01:36.66#ibcon#[25=AT02-06\r\n] 2006.173.08:01:36.66#ibcon#*before write, iclass 19, count 2 2006.173.08:01:36.66#ibcon#enter sib2, iclass 19, count 2 2006.173.08:01:36.66#ibcon#flushed, iclass 19, count 2 2006.173.08:01:36.66#ibcon#about to write, iclass 19, count 2 2006.173.08:01:36.66#ibcon#wrote, iclass 19, count 2 2006.173.08:01:36.66#ibcon#about to read 3, iclass 19, count 2 2006.173.08:01:36.69#ibcon#read 3, iclass 19, count 2 2006.173.08:01:36.69#ibcon#about to read 4, iclass 19, count 2 2006.173.08:01:36.69#ibcon#read 4, iclass 19, count 2 2006.173.08:01:36.69#ibcon#about to read 5, iclass 19, count 2 2006.173.08:01:36.69#ibcon#read 5, iclass 19, count 2 2006.173.08:01:36.69#ibcon#about to read 6, iclass 19, count 2 2006.173.08:01:36.69#ibcon#read 6, iclass 19, count 2 2006.173.08:01:36.69#ibcon#end of sib2, iclass 19, count 2 2006.173.08:01:36.69#ibcon#*after write, iclass 19, count 2 2006.173.08:01:36.69#ibcon#*before return 0, iclass 19, count 2 2006.173.08:01:36.69#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.08:01:36.69#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.08:01:36.69#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.08:01:36.69#ibcon#ireg 7 cls_cnt 0 2006.173.08:01:36.69#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.08:01:36.81#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.08:01:36.81#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.08:01:36.81#ibcon#enter wrdev, iclass 19, count 0 2006.173.08:01:36.81#ibcon#first serial, iclass 19, count 0 2006.173.08:01:36.81#ibcon#enter sib2, iclass 19, count 0 2006.173.08:01:36.81#ibcon#flushed, iclass 19, count 0 2006.173.08:01:36.81#ibcon#about to write, iclass 19, count 0 2006.173.08:01:36.81#ibcon#wrote, iclass 19, count 0 2006.173.08:01:36.81#ibcon#about to read 3, iclass 19, count 0 2006.173.08:01:36.83#ibcon#read 3, iclass 19, count 0 2006.173.08:01:36.83#ibcon#about to read 4, iclass 19, count 0 2006.173.08:01:36.83#ibcon#read 4, iclass 19, count 0 2006.173.08:01:36.83#ibcon#about to read 5, iclass 19, count 0 2006.173.08:01:36.83#ibcon#read 5, iclass 19, count 0 2006.173.08:01:36.83#ibcon#about to read 6, iclass 19, count 0 2006.173.08:01:36.83#ibcon#read 6, iclass 19, count 0 2006.173.08:01:36.83#ibcon#end of sib2, iclass 19, count 0 2006.173.08:01:36.83#ibcon#*mode == 0, iclass 19, count 0 2006.173.08:01:36.83#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.08:01:36.83#ibcon#[25=USB\r\n] 2006.173.08:01:36.83#ibcon#*before write, iclass 19, count 0 2006.173.08:01:36.83#ibcon#enter sib2, iclass 19, count 0 2006.173.08:01:36.83#ibcon#flushed, iclass 19, count 0 2006.173.08:01:36.83#ibcon#about to write, iclass 19, count 0 2006.173.08:01:36.83#ibcon#wrote, iclass 19, count 0 2006.173.08:01:36.83#ibcon#about to read 3, iclass 19, count 0 2006.173.08:01:36.86#ibcon#read 3, iclass 19, count 0 2006.173.08:01:36.86#ibcon#about to read 4, iclass 19, count 0 2006.173.08:01:36.86#ibcon#read 4, iclass 19, count 0 2006.173.08:01:36.86#ibcon#about to read 5, iclass 19, count 0 2006.173.08:01:36.86#ibcon#read 5, iclass 19, count 0 2006.173.08:01:36.86#ibcon#about to read 6, iclass 19, count 0 2006.173.08:01:36.86#ibcon#read 6, iclass 19, count 0 2006.173.08:01:36.86#ibcon#end of sib2, iclass 19, count 0 2006.173.08:01:36.86#ibcon#*after write, iclass 19, count 0 2006.173.08:01:36.86#ibcon#*before return 0, iclass 19, count 0 2006.173.08:01:36.86#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.08:01:36.86#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.08:01:36.86#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.08:01:36.86#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.08:01:36.86$vck44/valo=3,564.99 2006.173.08:01:36.86#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.08:01:36.86#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.08:01:36.86#ibcon#ireg 17 cls_cnt 0 2006.173.08:01:36.86#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.08:01:36.86#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.08:01:36.86#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.08:01:36.86#ibcon#enter wrdev, iclass 21, count 0 2006.173.08:01:36.86#ibcon#first serial, iclass 21, count 0 2006.173.08:01:36.86#ibcon#enter sib2, iclass 21, count 0 2006.173.08:01:36.86#ibcon#flushed, iclass 21, count 0 2006.173.08:01:36.86#ibcon#about to write, iclass 21, count 0 2006.173.08:01:36.86#ibcon#wrote, iclass 21, count 0 2006.173.08:01:36.86#ibcon#about to read 3, iclass 21, count 0 2006.173.08:01:36.88#ibcon#read 3, iclass 21, count 0 2006.173.08:01:36.88#ibcon#about to read 4, iclass 21, count 0 2006.173.08:01:36.88#ibcon#read 4, iclass 21, count 0 2006.173.08:01:36.88#ibcon#about to read 5, iclass 21, count 0 2006.173.08:01:36.88#ibcon#read 5, iclass 21, count 0 2006.173.08:01:36.88#ibcon#about to read 6, iclass 21, count 0 2006.173.08:01:36.88#ibcon#read 6, iclass 21, count 0 2006.173.08:01:36.88#ibcon#end of sib2, iclass 21, count 0 2006.173.08:01:36.88#ibcon#*mode == 0, iclass 21, count 0 2006.173.08:01:36.88#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.08:01:36.88#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.08:01:36.88#ibcon#*before write, iclass 21, count 0 2006.173.08:01:36.88#ibcon#enter sib2, iclass 21, count 0 2006.173.08:01:36.88#ibcon#flushed, iclass 21, count 0 2006.173.08:01:36.88#ibcon#about to write, iclass 21, count 0 2006.173.08:01:36.88#ibcon#wrote, iclass 21, count 0 2006.173.08:01:36.88#ibcon#about to read 3, iclass 21, count 0 2006.173.08:01:36.92#ibcon#read 3, iclass 21, count 0 2006.173.08:01:36.92#ibcon#about to read 4, iclass 21, count 0 2006.173.08:01:36.92#ibcon#read 4, iclass 21, count 0 2006.173.08:01:36.92#ibcon#about to read 5, iclass 21, count 0 2006.173.08:01:36.92#ibcon#read 5, iclass 21, count 0 2006.173.08:01:36.92#ibcon#about to read 6, iclass 21, count 0 2006.173.08:01:36.92#ibcon#read 6, iclass 21, count 0 2006.173.08:01:36.92#ibcon#end of sib2, iclass 21, count 0 2006.173.08:01:36.92#ibcon#*after write, iclass 21, count 0 2006.173.08:01:36.92#ibcon#*before return 0, iclass 21, count 0 2006.173.08:01:36.92#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.08:01:36.92#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.08:01:36.92#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.08:01:36.92#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.08:01:36.92$vck44/va=3,5 2006.173.08:01:36.92#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.08:01:36.92#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.08:01:36.92#ibcon#ireg 11 cls_cnt 2 2006.173.08:01:36.92#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.08:01:36.98#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.08:01:36.98#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.08:01:36.98#ibcon#enter wrdev, iclass 23, count 2 2006.173.08:01:36.98#ibcon#first serial, iclass 23, count 2 2006.173.08:01:36.98#ibcon#enter sib2, iclass 23, count 2 2006.173.08:01:36.98#ibcon#flushed, iclass 23, count 2 2006.173.08:01:36.98#ibcon#about to write, iclass 23, count 2 2006.173.08:01:36.98#ibcon#wrote, iclass 23, count 2 2006.173.08:01:36.98#ibcon#about to read 3, iclass 23, count 2 2006.173.08:01:37.00#ibcon#read 3, iclass 23, count 2 2006.173.08:01:37.00#ibcon#about to read 4, iclass 23, count 2 2006.173.08:01:37.00#ibcon#read 4, iclass 23, count 2 2006.173.08:01:37.00#ibcon#about to read 5, iclass 23, count 2 2006.173.08:01:37.00#ibcon#read 5, iclass 23, count 2 2006.173.08:01:37.00#ibcon#about to read 6, iclass 23, count 2 2006.173.08:01:37.00#ibcon#read 6, iclass 23, count 2 2006.173.08:01:37.00#ibcon#end of sib2, iclass 23, count 2 2006.173.08:01:37.00#ibcon#*mode == 0, iclass 23, count 2 2006.173.08:01:37.00#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.08:01:37.00#ibcon#[25=AT03-05\r\n] 2006.173.08:01:37.00#ibcon#*before write, iclass 23, count 2 2006.173.08:01:37.00#ibcon#enter sib2, iclass 23, count 2 2006.173.08:01:37.00#ibcon#flushed, iclass 23, count 2 2006.173.08:01:37.00#ibcon#about to write, iclass 23, count 2 2006.173.08:01:37.00#ibcon#wrote, iclass 23, count 2 2006.173.08:01:37.00#ibcon#about to read 3, iclass 23, count 2 2006.173.08:01:37.03#ibcon#read 3, iclass 23, count 2 2006.173.08:01:37.03#ibcon#about to read 4, iclass 23, count 2 2006.173.08:01:37.03#ibcon#read 4, iclass 23, count 2 2006.173.08:01:37.03#ibcon#about to read 5, iclass 23, count 2 2006.173.08:01:37.03#ibcon#read 5, iclass 23, count 2 2006.173.08:01:37.03#ibcon#about to read 6, iclass 23, count 2 2006.173.08:01:37.03#ibcon#read 6, iclass 23, count 2 2006.173.08:01:37.03#ibcon#end of sib2, iclass 23, count 2 2006.173.08:01:37.03#ibcon#*after write, iclass 23, count 2 2006.173.08:01:37.03#ibcon#*before return 0, iclass 23, count 2 2006.173.08:01:37.03#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.08:01:37.03#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.08:01:37.03#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.08:01:37.03#ibcon#ireg 7 cls_cnt 0 2006.173.08:01:37.03#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.08:01:37.15#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.08:01:37.15#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.08:01:37.15#ibcon#enter wrdev, iclass 23, count 0 2006.173.08:01:37.15#ibcon#first serial, iclass 23, count 0 2006.173.08:01:37.15#ibcon#enter sib2, iclass 23, count 0 2006.173.08:01:37.15#ibcon#flushed, iclass 23, count 0 2006.173.08:01:37.15#ibcon#about to write, iclass 23, count 0 2006.173.08:01:37.15#ibcon#wrote, iclass 23, count 0 2006.173.08:01:37.15#ibcon#about to read 3, iclass 23, count 0 2006.173.08:01:37.17#ibcon#read 3, iclass 23, count 0 2006.173.08:01:37.17#ibcon#about to read 4, iclass 23, count 0 2006.173.08:01:37.17#ibcon#read 4, iclass 23, count 0 2006.173.08:01:37.17#ibcon#about to read 5, iclass 23, count 0 2006.173.08:01:37.17#ibcon#read 5, iclass 23, count 0 2006.173.08:01:37.17#ibcon#about to read 6, iclass 23, count 0 2006.173.08:01:37.17#ibcon#read 6, iclass 23, count 0 2006.173.08:01:37.17#ibcon#end of sib2, iclass 23, count 0 2006.173.08:01:37.17#ibcon#*mode == 0, iclass 23, count 0 2006.173.08:01:37.17#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.08:01:37.17#ibcon#[25=USB\r\n] 2006.173.08:01:37.17#ibcon#*before write, iclass 23, count 0 2006.173.08:01:37.17#ibcon#enter sib2, iclass 23, count 0 2006.173.08:01:37.17#ibcon#flushed, iclass 23, count 0 2006.173.08:01:37.17#ibcon#about to write, iclass 23, count 0 2006.173.08:01:37.17#ibcon#wrote, iclass 23, count 0 2006.173.08:01:37.17#ibcon#about to read 3, iclass 23, count 0 2006.173.08:01:37.20#ibcon#read 3, iclass 23, count 0 2006.173.08:01:37.20#ibcon#about to read 4, iclass 23, count 0 2006.173.08:01:37.20#ibcon#read 4, iclass 23, count 0 2006.173.08:01:37.20#ibcon#about to read 5, iclass 23, count 0 2006.173.08:01:37.20#ibcon#read 5, iclass 23, count 0 2006.173.08:01:37.20#ibcon#about to read 6, iclass 23, count 0 2006.173.08:01:37.20#ibcon#read 6, iclass 23, count 0 2006.173.08:01:37.20#ibcon#end of sib2, iclass 23, count 0 2006.173.08:01:37.20#ibcon#*after write, iclass 23, count 0 2006.173.08:01:37.20#ibcon#*before return 0, iclass 23, count 0 2006.173.08:01:37.20#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.08:01:37.20#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.08:01:37.20#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.08:01:37.20#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.08:01:37.20$vck44/valo=4,624.99 2006.173.08:01:37.20#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.08:01:37.20#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.08:01:37.20#ibcon#ireg 17 cls_cnt 0 2006.173.08:01:37.20#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.08:01:37.20#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.08:01:37.20#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.08:01:37.20#ibcon#enter wrdev, iclass 25, count 0 2006.173.08:01:37.20#ibcon#first serial, iclass 25, count 0 2006.173.08:01:37.20#ibcon#enter sib2, iclass 25, count 0 2006.173.08:01:37.20#ibcon#flushed, iclass 25, count 0 2006.173.08:01:37.20#ibcon#about to write, iclass 25, count 0 2006.173.08:01:37.20#ibcon#wrote, iclass 25, count 0 2006.173.08:01:37.20#ibcon#about to read 3, iclass 25, count 0 2006.173.08:01:37.22#ibcon#read 3, iclass 25, count 0 2006.173.08:01:37.22#ibcon#about to read 4, iclass 25, count 0 2006.173.08:01:37.22#ibcon#read 4, iclass 25, count 0 2006.173.08:01:37.22#ibcon#about to read 5, iclass 25, count 0 2006.173.08:01:37.22#ibcon#read 5, iclass 25, count 0 2006.173.08:01:37.22#ibcon#about to read 6, iclass 25, count 0 2006.173.08:01:37.22#ibcon#read 6, iclass 25, count 0 2006.173.08:01:37.22#ibcon#end of sib2, iclass 25, count 0 2006.173.08:01:37.22#ibcon#*mode == 0, iclass 25, count 0 2006.173.08:01:37.22#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.08:01:37.22#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.08:01:37.22#ibcon#*before write, iclass 25, count 0 2006.173.08:01:37.22#ibcon#enter sib2, iclass 25, count 0 2006.173.08:01:37.22#ibcon#flushed, iclass 25, count 0 2006.173.08:01:37.22#ibcon#about to write, iclass 25, count 0 2006.173.08:01:37.22#ibcon#wrote, iclass 25, count 0 2006.173.08:01:37.22#ibcon#about to read 3, iclass 25, count 0 2006.173.08:01:37.26#abcon#<5=/03 0.8 1.3 23.55 831004.1\r\n> 2006.173.08:01:37.26#ibcon#read 3, iclass 25, count 0 2006.173.08:01:37.26#ibcon#about to read 4, iclass 25, count 0 2006.173.08:01:37.26#ibcon#read 4, iclass 25, count 0 2006.173.08:01:37.26#ibcon#about to read 5, iclass 25, count 0 2006.173.08:01:37.26#ibcon#read 5, iclass 25, count 0 2006.173.08:01:37.26#ibcon#about to read 6, iclass 25, count 0 2006.173.08:01:37.26#ibcon#read 6, iclass 25, count 0 2006.173.08:01:37.26#ibcon#end of sib2, iclass 25, count 0 2006.173.08:01:37.26#ibcon#*after write, iclass 25, count 0 2006.173.08:01:37.26#ibcon#*before return 0, iclass 25, count 0 2006.173.08:01:37.26#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.08:01:37.26#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.08:01:37.26#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.08:01:37.26#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.08:01:37.26$vck44/va=4,6 2006.173.08:01:37.26#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.08:01:37.26#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.08:01:37.26#ibcon#ireg 11 cls_cnt 2 2006.173.08:01:37.26#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.08:01:37.28#abcon#{5=INTERFACE CLEAR} 2006.173.08:01:37.32#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.08:01:37.32#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.08:01:37.32#ibcon#enter wrdev, iclass 30, count 2 2006.173.08:01:37.32#ibcon#first serial, iclass 30, count 2 2006.173.08:01:37.32#ibcon#enter sib2, iclass 30, count 2 2006.173.08:01:37.32#ibcon#flushed, iclass 30, count 2 2006.173.08:01:37.32#ibcon#about to write, iclass 30, count 2 2006.173.08:01:37.32#ibcon#wrote, iclass 30, count 2 2006.173.08:01:37.32#ibcon#about to read 3, iclass 30, count 2 2006.173.08:01:37.34#ibcon#read 3, iclass 30, count 2 2006.173.08:01:37.34#ibcon#about to read 4, iclass 30, count 2 2006.173.08:01:37.34#ibcon#read 4, iclass 30, count 2 2006.173.08:01:37.34#ibcon#about to read 5, iclass 30, count 2 2006.173.08:01:37.34#ibcon#read 5, iclass 30, count 2 2006.173.08:01:37.34#ibcon#about to read 6, iclass 30, count 2 2006.173.08:01:37.34#ibcon#read 6, iclass 30, count 2 2006.173.08:01:37.34#ibcon#end of sib2, iclass 30, count 2 2006.173.08:01:37.34#ibcon#*mode == 0, iclass 30, count 2 2006.173.08:01:37.34#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.08:01:37.34#ibcon#[25=AT04-06\r\n] 2006.173.08:01:37.34#ibcon#*before write, iclass 30, count 2 2006.173.08:01:37.34#ibcon#enter sib2, iclass 30, count 2 2006.173.08:01:37.34#ibcon#flushed, iclass 30, count 2 2006.173.08:01:37.34#ibcon#about to write, iclass 30, count 2 2006.173.08:01:37.34#ibcon#wrote, iclass 30, count 2 2006.173.08:01:37.34#ibcon#about to read 3, iclass 30, count 2 2006.173.08:01:37.34#abcon#[5=S1D000X0/0*\r\n] 2006.173.08:01:37.37#ibcon#read 3, iclass 30, count 2 2006.173.08:01:37.37#ibcon#about to read 4, iclass 30, count 2 2006.173.08:01:37.37#ibcon#read 4, iclass 30, count 2 2006.173.08:01:37.37#ibcon#about to read 5, iclass 30, count 2 2006.173.08:01:37.37#ibcon#read 5, iclass 30, count 2 2006.173.08:01:37.37#ibcon#about to read 6, iclass 30, count 2 2006.173.08:01:37.37#ibcon#read 6, iclass 30, count 2 2006.173.08:01:37.37#ibcon#end of sib2, iclass 30, count 2 2006.173.08:01:37.37#ibcon#*after write, iclass 30, count 2 2006.173.08:01:37.37#ibcon#*before return 0, iclass 30, count 2 2006.173.08:01:37.37#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.08:01:37.37#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.08:01:37.37#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.08:01:37.37#ibcon#ireg 7 cls_cnt 0 2006.173.08:01:37.37#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.08:01:37.49#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.08:01:37.49#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.08:01:37.49#ibcon#enter wrdev, iclass 30, count 0 2006.173.08:01:37.49#ibcon#first serial, iclass 30, count 0 2006.173.08:01:37.49#ibcon#enter sib2, iclass 30, count 0 2006.173.08:01:37.49#ibcon#flushed, iclass 30, count 0 2006.173.08:01:37.49#ibcon#about to write, iclass 30, count 0 2006.173.08:01:37.49#ibcon#wrote, iclass 30, count 0 2006.173.08:01:37.49#ibcon#about to read 3, iclass 30, count 0 2006.173.08:01:37.51#ibcon#read 3, iclass 30, count 0 2006.173.08:01:37.51#ibcon#about to read 4, iclass 30, count 0 2006.173.08:01:37.51#ibcon#read 4, iclass 30, count 0 2006.173.08:01:37.51#ibcon#about to read 5, iclass 30, count 0 2006.173.08:01:37.51#ibcon#read 5, iclass 30, count 0 2006.173.08:01:37.51#ibcon#about to read 6, iclass 30, count 0 2006.173.08:01:37.51#ibcon#read 6, iclass 30, count 0 2006.173.08:01:37.51#ibcon#end of sib2, iclass 30, count 0 2006.173.08:01:37.51#ibcon#*mode == 0, iclass 30, count 0 2006.173.08:01:37.51#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.08:01:37.51#ibcon#[25=USB\r\n] 2006.173.08:01:37.51#ibcon#*before write, iclass 30, count 0 2006.173.08:01:37.51#ibcon#enter sib2, iclass 30, count 0 2006.173.08:01:37.51#ibcon#flushed, iclass 30, count 0 2006.173.08:01:37.51#ibcon#about to write, iclass 30, count 0 2006.173.08:01:37.51#ibcon#wrote, iclass 30, count 0 2006.173.08:01:37.51#ibcon#about to read 3, iclass 30, count 0 2006.173.08:01:37.54#ibcon#read 3, iclass 30, count 0 2006.173.08:01:37.54#ibcon#about to read 4, iclass 30, count 0 2006.173.08:01:37.54#ibcon#read 4, iclass 30, count 0 2006.173.08:01:37.54#ibcon#about to read 5, iclass 30, count 0 2006.173.08:01:37.54#ibcon#read 5, iclass 30, count 0 2006.173.08:01:37.54#ibcon#about to read 6, iclass 30, count 0 2006.173.08:01:37.54#ibcon#read 6, iclass 30, count 0 2006.173.08:01:37.54#ibcon#end of sib2, iclass 30, count 0 2006.173.08:01:37.54#ibcon#*after write, iclass 30, count 0 2006.173.08:01:37.54#ibcon#*before return 0, iclass 30, count 0 2006.173.08:01:37.54#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.08:01:37.54#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.08:01:37.54#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.08:01:37.54#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.08:01:37.54$vck44/valo=5,734.99 2006.173.08:01:37.54#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.08:01:37.54#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.08:01:37.54#ibcon#ireg 17 cls_cnt 0 2006.173.08:01:37.54#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.08:01:37.54#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.08:01:37.54#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.08:01:37.54#ibcon#enter wrdev, iclass 33, count 0 2006.173.08:01:37.54#ibcon#first serial, iclass 33, count 0 2006.173.08:01:37.54#ibcon#enter sib2, iclass 33, count 0 2006.173.08:01:37.54#ibcon#flushed, iclass 33, count 0 2006.173.08:01:37.54#ibcon#about to write, iclass 33, count 0 2006.173.08:01:37.54#ibcon#wrote, iclass 33, count 0 2006.173.08:01:37.54#ibcon#about to read 3, iclass 33, count 0 2006.173.08:01:37.56#ibcon#read 3, iclass 33, count 0 2006.173.08:01:37.56#ibcon#about to read 4, iclass 33, count 0 2006.173.08:01:37.56#ibcon#read 4, iclass 33, count 0 2006.173.08:01:37.56#ibcon#about to read 5, iclass 33, count 0 2006.173.08:01:37.56#ibcon#read 5, iclass 33, count 0 2006.173.08:01:37.56#ibcon#about to read 6, iclass 33, count 0 2006.173.08:01:37.56#ibcon#read 6, iclass 33, count 0 2006.173.08:01:37.56#ibcon#end of sib2, iclass 33, count 0 2006.173.08:01:37.56#ibcon#*mode == 0, iclass 33, count 0 2006.173.08:01:37.56#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.08:01:37.56#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.08:01:37.56#ibcon#*before write, iclass 33, count 0 2006.173.08:01:37.56#ibcon#enter sib2, iclass 33, count 0 2006.173.08:01:37.56#ibcon#flushed, iclass 33, count 0 2006.173.08:01:37.56#ibcon#about to write, iclass 33, count 0 2006.173.08:01:37.56#ibcon#wrote, iclass 33, count 0 2006.173.08:01:37.56#ibcon#about to read 3, iclass 33, count 0 2006.173.08:01:37.60#ibcon#read 3, iclass 33, count 0 2006.173.08:01:37.60#ibcon#about to read 4, iclass 33, count 0 2006.173.08:01:37.60#ibcon#read 4, iclass 33, count 0 2006.173.08:01:37.60#ibcon#about to read 5, iclass 33, count 0 2006.173.08:01:37.60#ibcon#read 5, iclass 33, count 0 2006.173.08:01:37.60#ibcon#about to read 6, iclass 33, count 0 2006.173.08:01:37.60#ibcon#read 6, iclass 33, count 0 2006.173.08:01:37.60#ibcon#end of sib2, iclass 33, count 0 2006.173.08:01:37.60#ibcon#*after write, iclass 33, count 0 2006.173.08:01:37.60#ibcon#*before return 0, iclass 33, count 0 2006.173.08:01:37.60#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.08:01:37.60#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.08:01:37.60#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.08:01:37.60#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.08:01:37.60$vck44/va=5,4 2006.173.08:01:37.60#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.08:01:37.60#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.08:01:37.60#ibcon#ireg 11 cls_cnt 2 2006.173.08:01:37.60#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.08:01:37.66#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.08:01:37.66#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.08:01:37.66#ibcon#enter wrdev, iclass 35, count 2 2006.173.08:01:37.66#ibcon#first serial, iclass 35, count 2 2006.173.08:01:37.66#ibcon#enter sib2, iclass 35, count 2 2006.173.08:01:37.66#ibcon#flushed, iclass 35, count 2 2006.173.08:01:37.66#ibcon#about to write, iclass 35, count 2 2006.173.08:01:37.66#ibcon#wrote, iclass 35, count 2 2006.173.08:01:37.66#ibcon#about to read 3, iclass 35, count 2 2006.173.08:01:37.68#ibcon#read 3, iclass 35, count 2 2006.173.08:01:37.68#ibcon#about to read 4, iclass 35, count 2 2006.173.08:01:37.68#ibcon#read 4, iclass 35, count 2 2006.173.08:01:37.68#ibcon#about to read 5, iclass 35, count 2 2006.173.08:01:37.68#ibcon#read 5, iclass 35, count 2 2006.173.08:01:37.68#ibcon#about to read 6, iclass 35, count 2 2006.173.08:01:37.68#ibcon#read 6, iclass 35, count 2 2006.173.08:01:37.68#ibcon#end of sib2, iclass 35, count 2 2006.173.08:01:37.68#ibcon#*mode == 0, iclass 35, count 2 2006.173.08:01:37.68#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.08:01:37.68#ibcon#[25=AT05-04\r\n] 2006.173.08:01:37.68#ibcon#*before write, iclass 35, count 2 2006.173.08:01:37.68#ibcon#enter sib2, iclass 35, count 2 2006.173.08:01:37.68#ibcon#flushed, iclass 35, count 2 2006.173.08:01:37.68#ibcon#about to write, iclass 35, count 2 2006.173.08:01:37.68#ibcon#wrote, iclass 35, count 2 2006.173.08:01:37.68#ibcon#about to read 3, iclass 35, count 2 2006.173.08:01:37.71#ibcon#read 3, iclass 35, count 2 2006.173.08:01:37.71#ibcon#about to read 4, iclass 35, count 2 2006.173.08:01:37.71#ibcon#read 4, iclass 35, count 2 2006.173.08:01:37.71#ibcon#about to read 5, iclass 35, count 2 2006.173.08:01:37.71#ibcon#read 5, iclass 35, count 2 2006.173.08:01:37.71#ibcon#about to read 6, iclass 35, count 2 2006.173.08:01:37.71#ibcon#read 6, iclass 35, count 2 2006.173.08:01:37.71#ibcon#end of sib2, iclass 35, count 2 2006.173.08:01:37.71#ibcon#*after write, iclass 35, count 2 2006.173.08:01:37.71#ibcon#*before return 0, iclass 35, count 2 2006.173.08:01:37.71#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.08:01:37.71#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.08:01:37.71#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.08:01:37.71#ibcon#ireg 7 cls_cnt 0 2006.173.08:01:37.71#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.08:01:37.83#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.08:01:37.83#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.08:01:37.83#ibcon#enter wrdev, iclass 35, count 0 2006.173.08:01:37.83#ibcon#first serial, iclass 35, count 0 2006.173.08:01:37.83#ibcon#enter sib2, iclass 35, count 0 2006.173.08:01:37.83#ibcon#flushed, iclass 35, count 0 2006.173.08:01:37.83#ibcon#about to write, iclass 35, count 0 2006.173.08:01:37.83#ibcon#wrote, iclass 35, count 0 2006.173.08:01:37.83#ibcon#about to read 3, iclass 35, count 0 2006.173.08:01:37.85#ibcon#read 3, iclass 35, count 0 2006.173.08:01:37.85#ibcon#about to read 4, iclass 35, count 0 2006.173.08:01:37.85#ibcon#read 4, iclass 35, count 0 2006.173.08:01:37.85#ibcon#about to read 5, iclass 35, count 0 2006.173.08:01:37.85#ibcon#read 5, iclass 35, count 0 2006.173.08:01:37.85#ibcon#about to read 6, iclass 35, count 0 2006.173.08:01:37.85#ibcon#read 6, iclass 35, count 0 2006.173.08:01:37.85#ibcon#end of sib2, iclass 35, count 0 2006.173.08:01:37.85#ibcon#*mode == 0, iclass 35, count 0 2006.173.08:01:37.85#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.08:01:37.85#ibcon#[25=USB\r\n] 2006.173.08:01:37.85#ibcon#*before write, iclass 35, count 0 2006.173.08:01:37.85#ibcon#enter sib2, iclass 35, count 0 2006.173.08:01:37.85#ibcon#flushed, iclass 35, count 0 2006.173.08:01:37.85#ibcon#about to write, iclass 35, count 0 2006.173.08:01:37.85#ibcon#wrote, iclass 35, count 0 2006.173.08:01:37.85#ibcon#about to read 3, iclass 35, count 0 2006.173.08:01:37.88#ibcon#read 3, iclass 35, count 0 2006.173.08:01:37.88#ibcon#about to read 4, iclass 35, count 0 2006.173.08:01:37.88#ibcon#read 4, iclass 35, count 0 2006.173.08:01:37.88#ibcon#about to read 5, iclass 35, count 0 2006.173.08:01:37.88#ibcon#read 5, iclass 35, count 0 2006.173.08:01:37.88#ibcon#about to read 6, iclass 35, count 0 2006.173.08:01:37.88#ibcon#read 6, iclass 35, count 0 2006.173.08:01:37.88#ibcon#end of sib2, iclass 35, count 0 2006.173.08:01:37.88#ibcon#*after write, iclass 35, count 0 2006.173.08:01:37.88#ibcon#*before return 0, iclass 35, count 0 2006.173.08:01:37.88#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.08:01:37.88#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.08:01:37.88#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.08:01:37.88#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.08:01:37.88$vck44/valo=6,814.99 2006.173.08:01:37.88#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.08:01:37.88#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.08:01:37.88#ibcon#ireg 17 cls_cnt 0 2006.173.08:01:37.88#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.08:01:37.88#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.08:01:37.88#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.08:01:37.88#ibcon#enter wrdev, iclass 37, count 0 2006.173.08:01:37.88#ibcon#first serial, iclass 37, count 0 2006.173.08:01:37.88#ibcon#enter sib2, iclass 37, count 0 2006.173.08:01:37.88#ibcon#flushed, iclass 37, count 0 2006.173.08:01:37.88#ibcon#about to write, iclass 37, count 0 2006.173.08:01:37.88#ibcon#wrote, iclass 37, count 0 2006.173.08:01:37.88#ibcon#about to read 3, iclass 37, count 0 2006.173.08:01:37.90#ibcon#read 3, iclass 37, count 0 2006.173.08:01:37.90#ibcon#about to read 4, iclass 37, count 0 2006.173.08:01:37.90#ibcon#read 4, iclass 37, count 0 2006.173.08:01:37.90#ibcon#about to read 5, iclass 37, count 0 2006.173.08:01:37.90#ibcon#read 5, iclass 37, count 0 2006.173.08:01:37.90#ibcon#about to read 6, iclass 37, count 0 2006.173.08:01:37.90#ibcon#read 6, iclass 37, count 0 2006.173.08:01:37.90#ibcon#end of sib2, iclass 37, count 0 2006.173.08:01:37.90#ibcon#*mode == 0, iclass 37, count 0 2006.173.08:01:37.90#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.08:01:37.90#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.08:01:37.90#ibcon#*before write, iclass 37, count 0 2006.173.08:01:37.90#ibcon#enter sib2, iclass 37, count 0 2006.173.08:01:37.90#ibcon#flushed, iclass 37, count 0 2006.173.08:01:37.90#ibcon#about to write, iclass 37, count 0 2006.173.08:01:37.90#ibcon#wrote, iclass 37, count 0 2006.173.08:01:37.90#ibcon#about to read 3, iclass 37, count 0 2006.173.08:01:37.94#ibcon#read 3, iclass 37, count 0 2006.173.08:01:37.94#ibcon#about to read 4, iclass 37, count 0 2006.173.08:01:37.94#ibcon#read 4, iclass 37, count 0 2006.173.08:01:37.94#ibcon#about to read 5, iclass 37, count 0 2006.173.08:01:37.94#ibcon#read 5, iclass 37, count 0 2006.173.08:01:37.94#ibcon#about to read 6, iclass 37, count 0 2006.173.08:01:37.94#ibcon#read 6, iclass 37, count 0 2006.173.08:01:37.94#ibcon#end of sib2, iclass 37, count 0 2006.173.08:01:37.94#ibcon#*after write, iclass 37, count 0 2006.173.08:01:37.94#ibcon#*before return 0, iclass 37, count 0 2006.173.08:01:37.94#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.08:01:37.94#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.08:01:37.94#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.08:01:37.94#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.08:01:37.94$vck44/va=6,3 2006.173.08:01:37.94#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.08:01:37.94#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.08:01:37.94#ibcon#ireg 11 cls_cnt 2 2006.173.08:01:37.94#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.08:01:38.00#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.08:01:38.00#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.08:01:38.00#ibcon#enter wrdev, iclass 39, count 2 2006.173.08:01:38.00#ibcon#first serial, iclass 39, count 2 2006.173.08:01:38.00#ibcon#enter sib2, iclass 39, count 2 2006.173.08:01:38.00#ibcon#flushed, iclass 39, count 2 2006.173.08:01:38.00#ibcon#about to write, iclass 39, count 2 2006.173.08:01:38.00#ibcon#wrote, iclass 39, count 2 2006.173.08:01:38.00#ibcon#about to read 3, iclass 39, count 2 2006.173.08:01:38.02#ibcon#read 3, iclass 39, count 2 2006.173.08:01:38.02#ibcon#about to read 4, iclass 39, count 2 2006.173.08:01:38.02#ibcon#read 4, iclass 39, count 2 2006.173.08:01:38.02#ibcon#about to read 5, iclass 39, count 2 2006.173.08:01:38.02#ibcon#read 5, iclass 39, count 2 2006.173.08:01:38.02#ibcon#about to read 6, iclass 39, count 2 2006.173.08:01:38.02#ibcon#read 6, iclass 39, count 2 2006.173.08:01:38.02#ibcon#end of sib2, iclass 39, count 2 2006.173.08:01:38.02#ibcon#*mode == 0, iclass 39, count 2 2006.173.08:01:38.02#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.08:01:38.02#ibcon#[25=AT06-03\r\n] 2006.173.08:01:38.02#ibcon#*before write, iclass 39, count 2 2006.173.08:01:38.02#ibcon#enter sib2, iclass 39, count 2 2006.173.08:01:38.02#ibcon#flushed, iclass 39, count 2 2006.173.08:01:38.02#ibcon#about to write, iclass 39, count 2 2006.173.08:01:38.02#ibcon#wrote, iclass 39, count 2 2006.173.08:01:38.02#ibcon#about to read 3, iclass 39, count 2 2006.173.08:01:38.05#ibcon#read 3, iclass 39, count 2 2006.173.08:01:38.05#ibcon#about to read 4, iclass 39, count 2 2006.173.08:01:38.05#ibcon#read 4, iclass 39, count 2 2006.173.08:01:38.05#ibcon#about to read 5, iclass 39, count 2 2006.173.08:01:38.05#ibcon#read 5, iclass 39, count 2 2006.173.08:01:38.05#ibcon#about to read 6, iclass 39, count 2 2006.173.08:01:38.05#ibcon#read 6, iclass 39, count 2 2006.173.08:01:38.05#ibcon#end of sib2, iclass 39, count 2 2006.173.08:01:38.05#ibcon#*after write, iclass 39, count 2 2006.173.08:01:38.05#ibcon#*before return 0, iclass 39, count 2 2006.173.08:01:38.05#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.08:01:38.05#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.08:01:38.05#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.08:01:38.05#ibcon#ireg 7 cls_cnt 0 2006.173.08:01:38.05#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.08:01:38.17#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.08:01:38.17#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.08:01:38.17#ibcon#enter wrdev, iclass 39, count 0 2006.173.08:01:38.17#ibcon#first serial, iclass 39, count 0 2006.173.08:01:38.17#ibcon#enter sib2, iclass 39, count 0 2006.173.08:01:38.17#ibcon#flushed, iclass 39, count 0 2006.173.08:01:38.17#ibcon#about to write, iclass 39, count 0 2006.173.08:01:38.17#ibcon#wrote, iclass 39, count 0 2006.173.08:01:38.17#ibcon#about to read 3, iclass 39, count 0 2006.173.08:01:38.19#ibcon#read 3, iclass 39, count 0 2006.173.08:01:38.19#ibcon#about to read 4, iclass 39, count 0 2006.173.08:01:38.19#ibcon#read 4, iclass 39, count 0 2006.173.08:01:38.19#ibcon#about to read 5, iclass 39, count 0 2006.173.08:01:38.19#ibcon#read 5, iclass 39, count 0 2006.173.08:01:38.19#ibcon#about to read 6, iclass 39, count 0 2006.173.08:01:38.19#ibcon#read 6, iclass 39, count 0 2006.173.08:01:38.19#ibcon#end of sib2, iclass 39, count 0 2006.173.08:01:38.19#ibcon#*mode == 0, iclass 39, count 0 2006.173.08:01:38.19#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.08:01:38.19#ibcon#[25=USB\r\n] 2006.173.08:01:38.19#ibcon#*before write, iclass 39, count 0 2006.173.08:01:38.19#ibcon#enter sib2, iclass 39, count 0 2006.173.08:01:38.19#ibcon#flushed, iclass 39, count 0 2006.173.08:01:38.19#ibcon#about to write, iclass 39, count 0 2006.173.08:01:38.19#ibcon#wrote, iclass 39, count 0 2006.173.08:01:38.19#ibcon#about to read 3, iclass 39, count 0 2006.173.08:01:38.22#ibcon#read 3, iclass 39, count 0 2006.173.08:01:38.22#ibcon#about to read 4, iclass 39, count 0 2006.173.08:01:38.22#ibcon#read 4, iclass 39, count 0 2006.173.08:01:38.22#ibcon#about to read 5, iclass 39, count 0 2006.173.08:01:38.22#ibcon#read 5, iclass 39, count 0 2006.173.08:01:38.22#ibcon#about to read 6, iclass 39, count 0 2006.173.08:01:38.22#ibcon#read 6, iclass 39, count 0 2006.173.08:01:38.22#ibcon#end of sib2, iclass 39, count 0 2006.173.08:01:38.22#ibcon#*after write, iclass 39, count 0 2006.173.08:01:38.22#ibcon#*before return 0, iclass 39, count 0 2006.173.08:01:38.22#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.08:01:38.22#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.08:01:38.22#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.08:01:38.22#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.08:01:38.22$vck44/valo=7,864.99 2006.173.08:01:38.22#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.08:01:38.22#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.08:01:38.22#ibcon#ireg 17 cls_cnt 0 2006.173.08:01:38.22#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.08:01:38.22#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.08:01:38.22#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.08:01:38.22#ibcon#enter wrdev, iclass 3, count 0 2006.173.08:01:38.22#ibcon#first serial, iclass 3, count 0 2006.173.08:01:38.22#ibcon#enter sib2, iclass 3, count 0 2006.173.08:01:38.22#ibcon#flushed, iclass 3, count 0 2006.173.08:01:38.22#ibcon#about to write, iclass 3, count 0 2006.173.08:01:38.22#ibcon#wrote, iclass 3, count 0 2006.173.08:01:38.22#ibcon#about to read 3, iclass 3, count 0 2006.173.08:01:38.24#ibcon#read 3, iclass 3, count 0 2006.173.08:01:38.24#ibcon#about to read 4, iclass 3, count 0 2006.173.08:01:38.24#ibcon#read 4, iclass 3, count 0 2006.173.08:01:38.24#ibcon#about to read 5, iclass 3, count 0 2006.173.08:01:38.24#ibcon#read 5, iclass 3, count 0 2006.173.08:01:38.24#ibcon#about to read 6, iclass 3, count 0 2006.173.08:01:38.24#ibcon#read 6, iclass 3, count 0 2006.173.08:01:38.24#ibcon#end of sib2, iclass 3, count 0 2006.173.08:01:38.24#ibcon#*mode == 0, iclass 3, count 0 2006.173.08:01:38.24#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.08:01:38.24#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.08:01:38.24#ibcon#*before write, iclass 3, count 0 2006.173.08:01:38.24#ibcon#enter sib2, iclass 3, count 0 2006.173.08:01:38.24#ibcon#flushed, iclass 3, count 0 2006.173.08:01:38.24#ibcon#about to write, iclass 3, count 0 2006.173.08:01:38.24#ibcon#wrote, iclass 3, count 0 2006.173.08:01:38.24#ibcon#about to read 3, iclass 3, count 0 2006.173.08:01:38.28#ibcon#read 3, iclass 3, count 0 2006.173.08:01:38.28#ibcon#about to read 4, iclass 3, count 0 2006.173.08:01:38.28#ibcon#read 4, iclass 3, count 0 2006.173.08:01:38.28#ibcon#about to read 5, iclass 3, count 0 2006.173.08:01:38.28#ibcon#read 5, iclass 3, count 0 2006.173.08:01:38.28#ibcon#about to read 6, iclass 3, count 0 2006.173.08:01:38.28#ibcon#read 6, iclass 3, count 0 2006.173.08:01:38.28#ibcon#end of sib2, iclass 3, count 0 2006.173.08:01:38.28#ibcon#*after write, iclass 3, count 0 2006.173.08:01:38.28#ibcon#*before return 0, iclass 3, count 0 2006.173.08:01:38.28#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.08:01:38.28#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.08:01:38.28#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.08:01:38.28#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.08:01:38.28$vck44/va=7,4 2006.173.08:01:38.28#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.08:01:38.28#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.08:01:38.28#ibcon#ireg 11 cls_cnt 2 2006.173.08:01:38.28#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.08:01:38.34#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.08:01:38.34#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.08:01:38.34#ibcon#enter wrdev, iclass 5, count 2 2006.173.08:01:38.34#ibcon#first serial, iclass 5, count 2 2006.173.08:01:38.34#ibcon#enter sib2, iclass 5, count 2 2006.173.08:01:38.34#ibcon#flushed, iclass 5, count 2 2006.173.08:01:38.34#ibcon#about to write, iclass 5, count 2 2006.173.08:01:38.34#ibcon#wrote, iclass 5, count 2 2006.173.08:01:38.34#ibcon#about to read 3, iclass 5, count 2 2006.173.08:01:38.36#ibcon#read 3, iclass 5, count 2 2006.173.08:01:38.36#ibcon#about to read 4, iclass 5, count 2 2006.173.08:01:38.36#ibcon#read 4, iclass 5, count 2 2006.173.08:01:38.36#ibcon#about to read 5, iclass 5, count 2 2006.173.08:01:38.36#ibcon#read 5, iclass 5, count 2 2006.173.08:01:38.36#ibcon#about to read 6, iclass 5, count 2 2006.173.08:01:38.36#ibcon#read 6, iclass 5, count 2 2006.173.08:01:38.36#ibcon#end of sib2, iclass 5, count 2 2006.173.08:01:38.36#ibcon#*mode == 0, iclass 5, count 2 2006.173.08:01:38.36#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.08:01:38.36#ibcon#[25=AT07-04\r\n] 2006.173.08:01:38.36#ibcon#*before write, iclass 5, count 2 2006.173.08:01:38.36#ibcon#enter sib2, iclass 5, count 2 2006.173.08:01:38.36#ibcon#flushed, iclass 5, count 2 2006.173.08:01:38.36#ibcon#about to write, iclass 5, count 2 2006.173.08:01:38.36#ibcon#wrote, iclass 5, count 2 2006.173.08:01:38.36#ibcon#about to read 3, iclass 5, count 2 2006.173.08:01:38.39#ibcon#read 3, iclass 5, count 2 2006.173.08:01:38.39#ibcon#about to read 4, iclass 5, count 2 2006.173.08:01:38.39#ibcon#read 4, iclass 5, count 2 2006.173.08:01:38.39#ibcon#about to read 5, iclass 5, count 2 2006.173.08:01:38.39#ibcon#read 5, iclass 5, count 2 2006.173.08:01:38.39#ibcon#about to read 6, iclass 5, count 2 2006.173.08:01:38.39#ibcon#read 6, iclass 5, count 2 2006.173.08:01:38.39#ibcon#end of sib2, iclass 5, count 2 2006.173.08:01:38.39#ibcon#*after write, iclass 5, count 2 2006.173.08:01:38.39#ibcon#*before return 0, iclass 5, count 2 2006.173.08:01:38.39#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.08:01:38.39#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.08:01:38.39#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.08:01:38.39#ibcon#ireg 7 cls_cnt 0 2006.173.08:01:38.39#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.08:01:38.51#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.08:01:38.51#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.08:01:38.51#ibcon#enter wrdev, iclass 5, count 0 2006.173.08:01:38.51#ibcon#first serial, iclass 5, count 0 2006.173.08:01:38.51#ibcon#enter sib2, iclass 5, count 0 2006.173.08:01:38.51#ibcon#flushed, iclass 5, count 0 2006.173.08:01:38.51#ibcon#about to write, iclass 5, count 0 2006.173.08:01:38.51#ibcon#wrote, iclass 5, count 0 2006.173.08:01:38.51#ibcon#about to read 3, iclass 5, count 0 2006.173.08:01:38.53#ibcon#read 3, iclass 5, count 0 2006.173.08:01:38.53#ibcon#about to read 4, iclass 5, count 0 2006.173.08:01:38.53#ibcon#read 4, iclass 5, count 0 2006.173.08:01:38.53#ibcon#about to read 5, iclass 5, count 0 2006.173.08:01:38.53#ibcon#read 5, iclass 5, count 0 2006.173.08:01:38.53#ibcon#about to read 6, iclass 5, count 0 2006.173.08:01:38.53#ibcon#read 6, iclass 5, count 0 2006.173.08:01:38.53#ibcon#end of sib2, iclass 5, count 0 2006.173.08:01:38.53#ibcon#*mode == 0, iclass 5, count 0 2006.173.08:01:38.53#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.08:01:38.53#ibcon#[25=USB\r\n] 2006.173.08:01:38.53#ibcon#*before write, iclass 5, count 0 2006.173.08:01:38.53#ibcon#enter sib2, iclass 5, count 0 2006.173.08:01:38.53#ibcon#flushed, iclass 5, count 0 2006.173.08:01:38.53#ibcon#about to write, iclass 5, count 0 2006.173.08:01:38.53#ibcon#wrote, iclass 5, count 0 2006.173.08:01:38.53#ibcon#about to read 3, iclass 5, count 0 2006.173.08:01:38.56#ibcon#read 3, iclass 5, count 0 2006.173.08:01:38.56#ibcon#about to read 4, iclass 5, count 0 2006.173.08:01:38.56#ibcon#read 4, iclass 5, count 0 2006.173.08:01:38.56#ibcon#about to read 5, iclass 5, count 0 2006.173.08:01:38.56#ibcon#read 5, iclass 5, count 0 2006.173.08:01:38.56#ibcon#about to read 6, iclass 5, count 0 2006.173.08:01:38.56#ibcon#read 6, iclass 5, count 0 2006.173.08:01:38.56#ibcon#end of sib2, iclass 5, count 0 2006.173.08:01:38.56#ibcon#*after write, iclass 5, count 0 2006.173.08:01:38.56#ibcon#*before return 0, iclass 5, count 0 2006.173.08:01:38.56#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.08:01:38.56#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.08:01:38.56#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.08:01:38.56#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.08:01:38.56$vck44/valo=8,884.99 2006.173.08:01:38.56#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.08:01:38.56#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.08:01:38.56#ibcon#ireg 17 cls_cnt 0 2006.173.08:01:38.56#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.08:01:38.56#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.08:01:38.56#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.08:01:38.56#ibcon#enter wrdev, iclass 7, count 0 2006.173.08:01:38.56#ibcon#first serial, iclass 7, count 0 2006.173.08:01:38.56#ibcon#enter sib2, iclass 7, count 0 2006.173.08:01:38.56#ibcon#flushed, iclass 7, count 0 2006.173.08:01:38.56#ibcon#about to write, iclass 7, count 0 2006.173.08:01:38.56#ibcon#wrote, iclass 7, count 0 2006.173.08:01:38.56#ibcon#about to read 3, iclass 7, count 0 2006.173.08:01:38.58#ibcon#read 3, iclass 7, count 0 2006.173.08:01:38.58#ibcon#about to read 4, iclass 7, count 0 2006.173.08:01:38.58#ibcon#read 4, iclass 7, count 0 2006.173.08:01:38.58#ibcon#about to read 5, iclass 7, count 0 2006.173.08:01:38.58#ibcon#read 5, iclass 7, count 0 2006.173.08:01:38.58#ibcon#about to read 6, iclass 7, count 0 2006.173.08:01:38.58#ibcon#read 6, iclass 7, count 0 2006.173.08:01:38.58#ibcon#end of sib2, iclass 7, count 0 2006.173.08:01:38.58#ibcon#*mode == 0, iclass 7, count 0 2006.173.08:01:38.58#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.08:01:38.58#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.08:01:38.58#ibcon#*before write, iclass 7, count 0 2006.173.08:01:38.58#ibcon#enter sib2, iclass 7, count 0 2006.173.08:01:38.58#ibcon#flushed, iclass 7, count 0 2006.173.08:01:38.58#ibcon#about to write, iclass 7, count 0 2006.173.08:01:38.58#ibcon#wrote, iclass 7, count 0 2006.173.08:01:38.58#ibcon#about to read 3, iclass 7, count 0 2006.173.08:01:38.62#ibcon#read 3, iclass 7, count 0 2006.173.08:01:38.62#ibcon#about to read 4, iclass 7, count 0 2006.173.08:01:38.62#ibcon#read 4, iclass 7, count 0 2006.173.08:01:38.62#ibcon#about to read 5, iclass 7, count 0 2006.173.08:01:38.62#ibcon#read 5, iclass 7, count 0 2006.173.08:01:38.62#ibcon#about to read 6, iclass 7, count 0 2006.173.08:01:38.62#ibcon#read 6, iclass 7, count 0 2006.173.08:01:38.62#ibcon#end of sib2, iclass 7, count 0 2006.173.08:01:38.62#ibcon#*after write, iclass 7, count 0 2006.173.08:01:38.62#ibcon#*before return 0, iclass 7, count 0 2006.173.08:01:38.62#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.08:01:38.62#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.08:01:38.62#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.08:01:38.62#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.08:01:38.62$vck44/va=8,4 2006.173.08:01:38.62#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.08:01:38.62#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.08:01:38.62#ibcon#ireg 11 cls_cnt 2 2006.173.08:01:38.62#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.08:01:38.68#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.08:01:38.68#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.08:01:38.68#ibcon#enter wrdev, iclass 11, count 2 2006.173.08:01:38.68#ibcon#first serial, iclass 11, count 2 2006.173.08:01:38.68#ibcon#enter sib2, iclass 11, count 2 2006.173.08:01:38.68#ibcon#flushed, iclass 11, count 2 2006.173.08:01:38.68#ibcon#about to write, iclass 11, count 2 2006.173.08:01:38.68#ibcon#wrote, iclass 11, count 2 2006.173.08:01:38.68#ibcon#about to read 3, iclass 11, count 2 2006.173.08:01:38.70#ibcon#read 3, iclass 11, count 2 2006.173.08:01:38.70#ibcon#about to read 4, iclass 11, count 2 2006.173.08:01:38.70#ibcon#read 4, iclass 11, count 2 2006.173.08:01:38.70#ibcon#about to read 5, iclass 11, count 2 2006.173.08:01:38.70#ibcon#read 5, iclass 11, count 2 2006.173.08:01:38.70#ibcon#about to read 6, iclass 11, count 2 2006.173.08:01:38.70#ibcon#read 6, iclass 11, count 2 2006.173.08:01:38.70#ibcon#end of sib2, iclass 11, count 2 2006.173.08:01:38.70#ibcon#*mode == 0, iclass 11, count 2 2006.173.08:01:38.70#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.08:01:38.70#ibcon#[25=AT08-04\r\n] 2006.173.08:01:38.70#ibcon#*before write, iclass 11, count 2 2006.173.08:01:38.70#ibcon#enter sib2, iclass 11, count 2 2006.173.08:01:38.70#ibcon#flushed, iclass 11, count 2 2006.173.08:01:38.70#ibcon#about to write, iclass 11, count 2 2006.173.08:01:38.70#ibcon#wrote, iclass 11, count 2 2006.173.08:01:38.70#ibcon#about to read 3, iclass 11, count 2 2006.173.08:01:38.73#ibcon#read 3, iclass 11, count 2 2006.173.08:01:38.73#ibcon#about to read 4, iclass 11, count 2 2006.173.08:01:38.73#ibcon#read 4, iclass 11, count 2 2006.173.08:01:38.73#ibcon#about to read 5, iclass 11, count 2 2006.173.08:01:38.73#ibcon#read 5, iclass 11, count 2 2006.173.08:01:38.73#ibcon#about to read 6, iclass 11, count 2 2006.173.08:01:38.73#ibcon#read 6, iclass 11, count 2 2006.173.08:01:38.73#ibcon#end of sib2, iclass 11, count 2 2006.173.08:01:38.73#ibcon#*after write, iclass 11, count 2 2006.173.08:01:38.73#ibcon#*before return 0, iclass 11, count 2 2006.173.08:01:38.73#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.08:01:38.73#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.08:01:38.73#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.08:01:38.73#ibcon#ireg 7 cls_cnt 0 2006.173.08:01:38.73#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.08:01:38.85#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.08:01:38.85#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.08:01:38.85#ibcon#enter wrdev, iclass 11, count 0 2006.173.08:01:38.85#ibcon#first serial, iclass 11, count 0 2006.173.08:01:38.85#ibcon#enter sib2, iclass 11, count 0 2006.173.08:01:38.85#ibcon#flushed, iclass 11, count 0 2006.173.08:01:38.85#ibcon#about to write, iclass 11, count 0 2006.173.08:01:38.85#ibcon#wrote, iclass 11, count 0 2006.173.08:01:38.85#ibcon#about to read 3, iclass 11, count 0 2006.173.08:01:38.87#ibcon#read 3, iclass 11, count 0 2006.173.08:01:38.87#ibcon#about to read 4, iclass 11, count 0 2006.173.08:01:38.87#ibcon#read 4, iclass 11, count 0 2006.173.08:01:38.87#ibcon#about to read 5, iclass 11, count 0 2006.173.08:01:38.87#ibcon#read 5, iclass 11, count 0 2006.173.08:01:38.87#ibcon#about to read 6, iclass 11, count 0 2006.173.08:01:38.87#ibcon#read 6, iclass 11, count 0 2006.173.08:01:38.87#ibcon#end of sib2, iclass 11, count 0 2006.173.08:01:38.87#ibcon#*mode == 0, iclass 11, count 0 2006.173.08:01:38.87#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.08:01:38.87#ibcon#[25=USB\r\n] 2006.173.08:01:38.87#ibcon#*before write, iclass 11, count 0 2006.173.08:01:38.87#ibcon#enter sib2, iclass 11, count 0 2006.173.08:01:38.87#ibcon#flushed, iclass 11, count 0 2006.173.08:01:38.87#ibcon#about to write, iclass 11, count 0 2006.173.08:01:38.87#ibcon#wrote, iclass 11, count 0 2006.173.08:01:38.87#ibcon#about to read 3, iclass 11, count 0 2006.173.08:01:38.90#ibcon#read 3, iclass 11, count 0 2006.173.08:01:38.90#ibcon#about to read 4, iclass 11, count 0 2006.173.08:01:38.90#ibcon#read 4, iclass 11, count 0 2006.173.08:01:38.90#ibcon#about to read 5, iclass 11, count 0 2006.173.08:01:38.90#ibcon#read 5, iclass 11, count 0 2006.173.08:01:38.90#ibcon#about to read 6, iclass 11, count 0 2006.173.08:01:38.90#ibcon#read 6, iclass 11, count 0 2006.173.08:01:38.90#ibcon#end of sib2, iclass 11, count 0 2006.173.08:01:38.90#ibcon#*after write, iclass 11, count 0 2006.173.08:01:38.90#ibcon#*before return 0, iclass 11, count 0 2006.173.08:01:38.90#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.08:01:38.90#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.08:01:38.90#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.08:01:38.90#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.08:01:38.90$vck44/vblo=1,629.99 2006.173.08:01:38.90#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.08:01:38.90#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.08:01:38.90#ibcon#ireg 17 cls_cnt 0 2006.173.08:01:38.90#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.08:01:38.90#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.08:01:38.90#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.08:01:38.90#ibcon#enter wrdev, iclass 13, count 0 2006.173.08:01:38.90#ibcon#first serial, iclass 13, count 0 2006.173.08:01:38.90#ibcon#enter sib2, iclass 13, count 0 2006.173.08:01:38.90#ibcon#flushed, iclass 13, count 0 2006.173.08:01:38.90#ibcon#about to write, iclass 13, count 0 2006.173.08:01:38.90#ibcon#wrote, iclass 13, count 0 2006.173.08:01:38.90#ibcon#about to read 3, iclass 13, count 0 2006.173.08:01:38.92#ibcon#read 3, iclass 13, count 0 2006.173.08:01:38.92#ibcon#about to read 4, iclass 13, count 0 2006.173.08:01:38.92#ibcon#read 4, iclass 13, count 0 2006.173.08:01:38.92#ibcon#about to read 5, iclass 13, count 0 2006.173.08:01:38.92#ibcon#read 5, iclass 13, count 0 2006.173.08:01:38.92#ibcon#about to read 6, iclass 13, count 0 2006.173.08:01:38.92#ibcon#read 6, iclass 13, count 0 2006.173.08:01:38.92#ibcon#end of sib2, iclass 13, count 0 2006.173.08:01:38.92#ibcon#*mode == 0, iclass 13, count 0 2006.173.08:01:38.92#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.08:01:38.92#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.08:01:38.92#ibcon#*before write, iclass 13, count 0 2006.173.08:01:38.92#ibcon#enter sib2, iclass 13, count 0 2006.173.08:01:38.92#ibcon#flushed, iclass 13, count 0 2006.173.08:01:38.92#ibcon#about to write, iclass 13, count 0 2006.173.08:01:38.92#ibcon#wrote, iclass 13, count 0 2006.173.08:01:38.92#ibcon#about to read 3, iclass 13, count 0 2006.173.08:01:38.96#ibcon#read 3, iclass 13, count 0 2006.173.08:01:38.96#ibcon#about to read 4, iclass 13, count 0 2006.173.08:01:38.96#ibcon#read 4, iclass 13, count 0 2006.173.08:01:38.96#ibcon#about to read 5, iclass 13, count 0 2006.173.08:01:38.96#ibcon#read 5, iclass 13, count 0 2006.173.08:01:38.96#ibcon#about to read 6, iclass 13, count 0 2006.173.08:01:38.96#ibcon#read 6, iclass 13, count 0 2006.173.08:01:38.96#ibcon#end of sib2, iclass 13, count 0 2006.173.08:01:38.96#ibcon#*after write, iclass 13, count 0 2006.173.08:01:38.96#ibcon#*before return 0, iclass 13, count 0 2006.173.08:01:38.96#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.08:01:38.96#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.08:01:38.96#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.08:01:38.96#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.08:01:38.96$vck44/vb=1,4 2006.173.08:01:38.96#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.08:01:38.96#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.08:01:38.96#ibcon#ireg 11 cls_cnt 2 2006.173.08:01:38.96#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.08:01:38.96#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.08:01:38.96#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.08:01:38.96#ibcon#enter wrdev, iclass 15, count 2 2006.173.08:01:38.96#ibcon#first serial, iclass 15, count 2 2006.173.08:01:38.96#ibcon#enter sib2, iclass 15, count 2 2006.173.08:01:38.96#ibcon#flushed, iclass 15, count 2 2006.173.08:01:38.96#ibcon#about to write, iclass 15, count 2 2006.173.08:01:38.96#ibcon#wrote, iclass 15, count 2 2006.173.08:01:38.96#ibcon#about to read 3, iclass 15, count 2 2006.173.08:01:38.98#ibcon#read 3, iclass 15, count 2 2006.173.08:01:38.98#ibcon#about to read 4, iclass 15, count 2 2006.173.08:01:38.98#ibcon#read 4, iclass 15, count 2 2006.173.08:01:38.98#ibcon#about to read 5, iclass 15, count 2 2006.173.08:01:38.98#ibcon#read 5, iclass 15, count 2 2006.173.08:01:38.98#ibcon#about to read 6, iclass 15, count 2 2006.173.08:01:38.98#ibcon#read 6, iclass 15, count 2 2006.173.08:01:38.98#ibcon#end of sib2, iclass 15, count 2 2006.173.08:01:38.98#ibcon#*mode == 0, iclass 15, count 2 2006.173.08:01:38.98#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.08:01:38.98#ibcon#[27=AT01-04\r\n] 2006.173.08:01:38.98#ibcon#*before write, iclass 15, count 2 2006.173.08:01:38.98#ibcon#enter sib2, iclass 15, count 2 2006.173.08:01:38.98#ibcon#flushed, iclass 15, count 2 2006.173.08:01:38.98#ibcon#about to write, iclass 15, count 2 2006.173.08:01:38.98#ibcon#wrote, iclass 15, count 2 2006.173.08:01:38.98#ibcon#about to read 3, iclass 15, count 2 2006.173.08:01:39.01#ibcon#read 3, iclass 15, count 2 2006.173.08:01:39.01#ibcon#about to read 4, iclass 15, count 2 2006.173.08:01:39.01#ibcon#read 4, iclass 15, count 2 2006.173.08:01:39.01#ibcon#about to read 5, iclass 15, count 2 2006.173.08:01:39.01#ibcon#read 5, iclass 15, count 2 2006.173.08:01:39.01#ibcon#about to read 6, iclass 15, count 2 2006.173.08:01:39.01#ibcon#read 6, iclass 15, count 2 2006.173.08:01:39.01#ibcon#end of sib2, iclass 15, count 2 2006.173.08:01:39.01#ibcon#*after write, iclass 15, count 2 2006.173.08:01:39.01#ibcon#*before return 0, iclass 15, count 2 2006.173.08:01:39.01#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.08:01:39.01#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.08:01:39.01#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.08:01:39.01#ibcon#ireg 7 cls_cnt 0 2006.173.08:01:39.01#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.08:01:39.13#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.08:01:39.13#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.08:01:39.13#ibcon#enter wrdev, iclass 15, count 0 2006.173.08:01:39.13#ibcon#first serial, iclass 15, count 0 2006.173.08:01:39.13#ibcon#enter sib2, iclass 15, count 0 2006.173.08:01:39.13#ibcon#flushed, iclass 15, count 0 2006.173.08:01:39.13#ibcon#about to write, iclass 15, count 0 2006.173.08:01:39.13#ibcon#wrote, iclass 15, count 0 2006.173.08:01:39.13#ibcon#about to read 3, iclass 15, count 0 2006.173.08:01:39.15#ibcon#read 3, iclass 15, count 0 2006.173.08:01:39.15#ibcon#about to read 4, iclass 15, count 0 2006.173.08:01:39.15#ibcon#read 4, iclass 15, count 0 2006.173.08:01:39.15#ibcon#about to read 5, iclass 15, count 0 2006.173.08:01:39.15#ibcon#read 5, iclass 15, count 0 2006.173.08:01:39.15#ibcon#about to read 6, iclass 15, count 0 2006.173.08:01:39.15#ibcon#read 6, iclass 15, count 0 2006.173.08:01:39.15#ibcon#end of sib2, iclass 15, count 0 2006.173.08:01:39.15#ibcon#*mode == 0, iclass 15, count 0 2006.173.08:01:39.15#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.08:01:39.15#ibcon#[27=USB\r\n] 2006.173.08:01:39.15#ibcon#*before write, iclass 15, count 0 2006.173.08:01:39.15#ibcon#enter sib2, iclass 15, count 0 2006.173.08:01:39.15#ibcon#flushed, iclass 15, count 0 2006.173.08:01:39.15#ibcon#about to write, iclass 15, count 0 2006.173.08:01:39.15#ibcon#wrote, iclass 15, count 0 2006.173.08:01:39.15#ibcon#about to read 3, iclass 15, count 0 2006.173.08:01:39.18#ibcon#read 3, iclass 15, count 0 2006.173.08:01:39.18#ibcon#about to read 4, iclass 15, count 0 2006.173.08:01:39.18#ibcon#read 4, iclass 15, count 0 2006.173.08:01:39.18#ibcon#about to read 5, iclass 15, count 0 2006.173.08:01:39.18#ibcon#read 5, iclass 15, count 0 2006.173.08:01:39.18#ibcon#about to read 6, iclass 15, count 0 2006.173.08:01:39.18#ibcon#read 6, iclass 15, count 0 2006.173.08:01:39.18#ibcon#end of sib2, iclass 15, count 0 2006.173.08:01:39.18#ibcon#*after write, iclass 15, count 0 2006.173.08:01:39.18#ibcon#*before return 0, iclass 15, count 0 2006.173.08:01:39.18#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.08:01:39.18#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.08:01:39.18#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.08:01:39.18#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.08:01:39.18$vck44/vblo=2,634.99 2006.173.08:01:39.18#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.08:01:39.18#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.08:01:39.18#ibcon#ireg 17 cls_cnt 0 2006.173.08:01:39.18#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.08:01:39.18#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.08:01:39.18#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.08:01:39.18#ibcon#enter wrdev, iclass 17, count 0 2006.173.08:01:39.18#ibcon#first serial, iclass 17, count 0 2006.173.08:01:39.18#ibcon#enter sib2, iclass 17, count 0 2006.173.08:01:39.18#ibcon#flushed, iclass 17, count 0 2006.173.08:01:39.18#ibcon#about to write, iclass 17, count 0 2006.173.08:01:39.18#ibcon#wrote, iclass 17, count 0 2006.173.08:01:39.18#ibcon#about to read 3, iclass 17, count 0 2006.173.08:01:39.20#ibcon#read 3, iclass 17, count 0 2006.173.08:01:39.20#ibcon#about to read 4, iclass 17, count 0 2006.173.08:01:39.20#ibcon#read 4, iclass 17, count 0 2006.173.08:01:39.20#ibcon#about to read 5, iclass 17, count 0 2006.173.08:01:39.20#ibcon#read 5, iclass 17, count 0 2006.173.08:01:39.20#ibcon#about to read 6, iclass 17, count 0 2006.173.08:01:39.20#ibcon#read 6, iclass 17, count 0 2006.173.08:01:39.20#ibcon#end of sib2, iclass 17, count 0 2006.173.08:01:39.20#ibcon#*mode == 0, iclass 17, count 0 2006.173.08:01:39.20#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.08:01:39.20#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.08:01:39.20#ibcon#*before write, iclass 17, count 0 2006.173.08:01:39.20#ibcon#enter sib2, iclass 17, count 0 2006.173.08:01:39.20#ibcon#flushed, iclass 17, count 0 2006.173.08:01:39.20#ibcon#about to write, iclass 17, count 0 2006.173.08:01:39.20#ibcon#wrote, iclass 17, count 0 2006.173.08:01:39.20#ibcon#about to read 3, iclass 17, count 0 2006.173.08:01:39.24#ibcon#read 3, iclass 17, count 0 2006.173.08:01:39.24#ibcon#about to read 4, iclass 17, count 0 2006.173.08:01:39.24#ibcon#read 4, iclass 17, count 0 2006.173.08:01:39.24#ibcon#about to read 5, iclass 17, count 0 2006.173.08:01:39.24#ibcon#read 5, iclass 17, count 0 2006.173.08:01:39.24#ibcon#about to read 6, iclass 17, count 0 2006.173.08:01:39.24#ibcon#read 6, iclass 17, count 0 2006.173.08:01:39.24#ibcon#end of sib2, iclass 17, count 0 2006.173.08:01:39.24#ibcon#*after write, iclass 17, count 0 2006.173.08:01:39.24#ibcon#*before return 0, iclass 17, count 0 2006.173.08:01:39.24#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.08:01:39.24#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.08:01:39.24#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.08:01:39.24#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.08:01:39.24$vck44/vb=2,4 2006.173.08:01:39.24#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.08:01:39.24#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.08:01:39.24#ibcon#ireg 11 cls_cnt 2 2006.173.08:01:39.24#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.08:01:39.30#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.08:01:39.30#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.08:01:39.30#ibcon#enter wrdev, iclass 19, count 2 2006.173.08:01:39.30#ibcon#first serial, iclass 19, count 2 2006.173.08:01:39.30#ibcon#enter sib2, iclass 19, count 2 2006.173.08:01:39.30#ibcon#flushed, iclass 19, count 2 2006.173.08:01:39.30#ibcon#about to write, iclass 19, count 2 2006.173.08:01:39.30#ibcon#wrote, iclass 19, count 2 2006.173.08:01:39.30#ibcon#about to read 3, iclass 19, count 2 2006.173.08:01:39.32#ibcon#read 3, iclass 19, count 2 2006.173.08:01:39.32#ibcon#about to read 4, iclass 19, count 2 2006.173.08:01:39.32#ibcon#read 4, iclass 19, count 2 2006.173.08:01:39.32#ibcon#about to read 5, iclass 19, count 2 2006.173.08:01:39.32#ibcon#read 5, iclass 19, count 2 2006.173.08:01:39.32#ibcon#about to read 6, iclass 19, count 2 2006.173.08:01:39.32#ibcon#read 6, iclass 19, count 2 2006.173.08:01:39.32#ibcon#end of sib2, iclass 19, count 2 2006.173.08:01:39.32#ibcon#*mode == 0, iclass 19, count 2 2006.173.08:01:39.32#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.08:01:39.32#ibcon#[27=AT02-04\r\n] 2006.173.08:01:39.32#ibcon#*before write, iclass 19, count 2 2006.173.08:01:39.32#ibcon#enter sib2, iclass 19, count 2 2006.173.08:01:39.32#ibcon#flushed, iclass 19, count 2 2006.173.08:01:39.32#ibcon#about to write, iclass 19, count 2 2006.173.08:01:39.32#ibcon#wrote, iclass 19, count 2 2006.173.08:01:39.32#ibcon#about to read 3, iclass 19, count 2 2006.173.08:01:39.35#ibcon#read 3, iclass 19, count 2 2006.173.08:01:39.35#ibcon#about to read 4, iclass 19, count 2 2006.173.08:01:39.35#ibcon#read 4, iclass 19, count 2 2006.173.08:01:39.35#ibcon#about to read 5, iclass 19, count 2 2006.173.08:01:39.35#ibcon#read 5, iclass 19, count 2 2006.173.08:01:39.35#ibcon#about to read 6, iclass 19, count 2 2006.173.08:01:39.35#ibcon#read 6, iclass 19, count 2 2006.173.08:01:39.35#ibcon#end of sib2, iclass 19, count 2 2006.173.08:01:39.35#ibcon#*after write, iclass 19, count 2 2006.173.08:01:39.35#ibcon#*before return 0, iclass 19, count 2 2006.173.08:01:39.35#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.08:01:39.35#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.08:01:39.35#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.08:01:39.35#ibcon#ireg 7 cls_cnt 0 2006.173.08:01:39.35#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.08:01:39.47#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.08:01:39.47#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.08:01:39.47#ibcon#enter wrdev, iclass 19, count 0 2006.173.08:01:39.47#ibcon#first serial, iclass 19, count 0 2006.173.08:01:39.47#ibcon#enter sib2, iclass 19, count 0 2006.173.08:01:39.47#ibcon#flushed, iclass 19, count 0 2006.173.08:01:39.47#ibcon#about to write, iclass 19, count 0 2006.173.08:01:39.47#ibcon#wrote, iclass 19, count 0 2006.173.08:01:39.47#ibcon#about to read 3, iclass 19, count 0 2006.173.08:01:39.49#ibcon#read 3, iclass 19, count 0 2006.173.08:01:39.49#ibcon#about to read 4, iclass 19, count 0 2006.173.08:01:39.49#ibcon#read 4, iclass 19, count 0 2006.173.08:01:39.49#ibcon#about to read 5, iclass 19, count 0 2006.173.08:01:39.49#ibcon#read 5, iclass 19, count 0 2006.173.08:01:39.49#ibcon#about to read 6, iclass 19, count 0 2006.173.08:01:39.49#ibcon#read 6, iclass 19, count 0 2006.173.08:01:39.49#ibcon#end of sib2, iclass 19, count 0 2006.173.08:01:39.49#ibcon#*mode == 0, iclass 19, count 0 2006.173.08:01:39.49#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.08:01:39.49#ibcon#[27=USB\r\n] 2006.173.08:01:39.49#ibcon#*before write, iclass 19, count 0 2006.173.08:01:39.49#ibcon#enter sib2, iclass 19, count 0 2006.173.08:01:39.49#ibcon#flushed, iclass 19, count 0 2006.173.08:01:39.49#ibcon#about to write, iclass 19, count 0 2006.173.08:01:39.49#ibcon#wrote, iclass 19, count 0 2006.173.08:01:39.49#ibcon#about to read 3, iclass 19, count 0 2006.173.08:01:39.52#ibcon#read 3, iclass 19, count 0 2006.173.08:01:39.52#ibcon#about to read 4, iclass 19, count 0 2006.173.08:01:39.52#ibcon#read 4, iclass 19, count 0 2006.173.08:01:39.52#ibcon#about to read 5, iclass 19, count 0 2006.173.08:01:39.52#ibcon#read 5, iclass 19, count 0 2006.173.08:01:39.52#ibcon#about to read 6, iclass 19, count 0 2006.173.08:01:39.52#ibcon#read 6, iclass 19, count 0 2006.173.08:01:39.52#ibcon#end of sib2, iclass 19, count 0 2006.173.08:01:39.52#ibcon#*after write, iclass 19, count 0 2006.173.08:01:39.52#ibcon#*before return 0, iclass 19, count 0 2006.173.08:01:39.52#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.08:01:39.52#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.08:01:39.52#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.08:01:39.52#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.08:01:39.52$vck44/vblo=3,649.99 2006.173.08:01:39.52#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.08:01:39.52#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.08:01:39.52#ibcon#ireg 17 cls_cnt 0 2006.173.08:01:39.52#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.08:01:39.52#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.08:01:39.52#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.08:01:39.52#ibcon#enter wrdev, iclass 21, count 0 2006.173.08:01:39.52#ibcon#first serial, iclass 21, count 0 2006.173.08:01:39.52#ibcon#enter sib2, iclass 21, count 0 2006.173.08:01:39.52#ibcon#flushed, iclass 21, count 0 2006.173.08:01:39.52#ibcon#about to write, iclass 21, count 0 2006.173.08:01:39.52#ibcon#wrote, iclass 21, count 0 2006.173.08:01:39.52#ibcon#about to read 3, iclass 21, count 0 2006.173.08:01:39.54#ibcon#read 3, iclass 21, count 0 2006.173.08:01:39.54#ibcon#about to read 4, iclass 21, count 0 2006.173.08:01:39.54#ibcon#read 4, iclass 21, count 0 2006.173.08:01:39.54#ibcon#about to read 5, iclass 21, count 0 2006.173.08:01:39.54#ibcon#read 5, iclass 21, count 0 2006.173.08:01:39.54#ibcon#about to read 6, iclass 21, count 0 2006.173.08:01:39.54#ibcon#read 6, iclass 21, count 0 2006.173.08:01:39.54#ibcon#end of sib2, iclass 21, count 0 2006.173.08:01:39.54#ibcon#*mode == 0, iclass 21, count 0 2006.173.08:01:39.54#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.08:01:39.54#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.08:01:39.54#ibcon#*before write, iclass 21, count 0 2006.173.08:01:39.54#ibcon#enter sib2, iclass 21, count 0 2006.173.08:01:39.54#ibcon#flushed, iclass 21, count 0 2006.173.08:01:39.54#ibcon#about to write, iclass 21, count 0 2006.173.08:01:39.54#ibcon#wrote, iclass 21, count 0 2006.173.08:01:39.54#ibcon#about to read 3, iclass 21, count 0 2006.173.08:01:39.58#ibcon#read 3, iclass 21, count 0 2006.173.08:01:39.58#ibcon#about to read 4, iclass 21, count 0 2006.173.08:01:39.58#ibcon#read 4, iclass 21, count 0 2006.173.08:01:39.58#ibcon#about to read 5, iclass 21, count 0 2006.173.08:01:39.58#ibcon#read 5, iclass 21, count 0 2006.173.08:01:39.58#ibcon#about to read 6, iclass 21, count 0 2006.173.08:01:39.58#ibcon#read 6, iclass 21, count 0 2006.173.08:01:39.58#ibcon#end of sib2, iclass 21, count 0 2006.173.08:01:39.58#ibcon#*after write, iclass 21, count 0 2006.173.08:01:39.58#ibcon#*before return 0, iclass 21, count 0 2006.173.08:01:39.58#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.08:01:39.58#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.08:01:39.58#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.08:01:39.58#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.08:01:39.58$vck44/vb=3,4 2006.173.08:01:39.58#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.08:01:39.58#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.08:01:39.58#ibcon#ireg 11 cls_cnt 2 2006.173.08:01:39.58#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.08:01:39.64#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.08:01:39.64#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.08:01:39.64#ibcon#enter wrdev, iclass 23, count 2 2006.173.08:01:39.64#ibcon#first serial, iclass 23, count 2 2006.173.08:01:39.64#ibcon#enter sib2, iclass 23, count 2 2006.173.08:01:39.64#ibcon#flushed, iclass 23, count 2 2006.173.08:01:39.64#ibcon#about to write, iclass 23, count 2 2006.173.08:01:39.64#ibcon#wrote, iclass 23, count 2 2006.173.08:01:39.64#ibcon#about to read 3, iclass 23, count 2 2006.173.08:01:39.66#ibcon#read 3, iclass 23, count 2 2006.173.08:01:39.66#ibcon#about to read 4, iclass 23, count 2 2006.173.08:01:39.66#ibcon#read 4, iclass 23, count 2 2006.173.08:01:39.66#ibcon#about to read 5, iclass 23, count 2 2006.173.08:01:39.66#ibcon#read 5, iclass 23, count 2 2006.173.08:01:39.66#ibcon#about to read 6, iclass 23, count 2 2006.173.08:01:39.66#ibcon#read 6, iclass 23, count 2 2006.173.08:01:39.66#ibcon#end of sib2, iclass 23, count 2 2006.173.08:01:39.66#ibcon#*mode == 0, iclass 23, count 2 2006.173.08:01:39.66#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.08:01:39.66#ibcon#[27=AT03-04\r\n] 2006.173.08:01:39.66#ibcon#*before write, iclass 23, count 2 2006.173.08:01:39.66#ibcon#enter sib2, iclass 23, count 2 2006.173.08:01:39.66#ibcon#flushed, iclass 23, count 2 2006.173.08:01:39.66#ibcon#about to write, iclass 23, count 2 2006.173.08:01:39.66#ibcon#wrote, iclass 23, count 2 2006.173.08:01:39.66#ibcon#about to read 3, iclass 23, count 2 2006.173.08:01:39.69#ibcon#read 3, iclass 23, count 2 2006.173.08:01:39.69#ibcon#about to read 4, iclass 23, count 2 2006.173.08:01:39.69#ibcon#read 4, iclass 23, count 2 2006.173.08:01:39.69#ibcon#about to read 5, iclass 23, count 2 2006.173.08:01:39.69#ibcon#read 5, iclass 23, count 2 2006.173.08:01:39.69#ibcon#about to read 6, iclass 23, count 2 2006.173.08:01:39.69#ibcon#read 6, iclass 23, count 2 2006.173.08:01:39.69#ibcon#end of sib2, iclass 23, count 2 2006.173.08:01:39.69#ibcon#*after write, iclass 23, count 2 2006.173.08:01:39.69#ibcon#*before return 0, iclass 23, count 2 2006.173.08:01:39.69#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.08:01:39.69#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.08:01:39.69#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.08:01:39.69#ibcon#ireg 7 cls_cnt 0 2006.173.08:01:39.69#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.08:01:39.81#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.08:01:39.81#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.08:01:39.81#ibcon#enter wrdev, iclass 23, count 0 2006.173.08:01:39.81#ibcon#first serial, iclass 23, count 0 2006.173.08:01:39.81#ibcon#enter sib2, iclass 23, count 0 2006.173.08:01:39.81#ibcon#flushed, iclass 23, count 0 2006.173.08:01:39.81#ibcon#about to write, iclass 23, count 0 2006.173.08:01:39.81#ibcon#wrote, iclass 23, count 0 2006.173.08:01:39.81#ibcon#about to read 3, iclass 23, count 0 2006.173.08:01:39.83#ibcon#read 3, iclass 23, count 0 2006.173.08:01:39.83#ibcon#about to read 4, iclass 23, count 0 2006.173.08:01:39.83#ibcon#read 4, iclass 23, count 0 2006.173.08:01:39.83#ibcon#about to read 5, iclass 23, count 0 2006.173.08:01:39.83#ibcon#read 5, iclass 23, count 0 2006.173.08:01:39.83#ibcon#about to read 6, iclass 23, count 0 2006.173.08:01:39.83#ibcon#read 6, iclass 23, count 0 2006.173.08:01:39.83#ibcon#end of sib2, iclass 23, count 0 2006.173.08:01:39.83#ibcon#*mode == 0, iclass 23, count 0 2006.173.08:01:39.83#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.08:01:39.83#ibcon#[27=USB\r\n] 2006.173.08:01:39.83#ibcon#*before write, iclass 23, count 0 2006.173.08:01:39.83#ibcon#enter sib2, iclass 23, count 0 2006.173.08:01:39.83#ibcon#flushed, iclass 23, count 0 2006.173.08:01:39.83#ibcon#about to write, iclass 23, count 0 2006.173.08:01:39.83#ibcon#wrote, iclass 23, count 0 2006.173.08:01:39.83#ibcon#about to read 3, iclass 23, count 0 2006.173.08:01:39.86#ibcon#read 3, iclass 23, count 0 2006.173.08:01:39.86#ibcon#about to read 4, iclass 23, count 0 2006.173.08:01:39.86#ibcon#read 4, iclass 23, count 0 2006.173.08:01:39.86#ibcon#about to read 5, iclass 23, count 0 2006.173.08:01:39.86#ibcon#read 5, iclass 23, count 0 2006.173.08:01:39.86#ibcon#about to read 6, iclass 23, count 0 2006.173.08:01:39.86#ibcon#read 6, iclass 23, count 0 2006.173.08:01:39.86#ibcon#end of sib2, iclass 23, count 0 2006.173.08:01:39.86#ibcon#*after write, iclass 23, count 0 2006.173.08:01:39.86#ibcon#*before return 0, iclass 23, count 0 2006.173.08:01:39.86#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.08:01:39.86#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.08:01:39.86#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.08:01:39.86#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.08:01:39.86$vck44/vblo=4,679.99 2006.173.08:01:39.86#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.08:01:39.86#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.08:01:39.86#ibcon#ireg 17 cls_cnt 0 2006.173.08:01:39.86#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.08:01:39.86#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.08:01:39.86#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.08:01:39.86#ibcon#enter wrdev, iclass 25, count 0 2006.173.08:01:39.86#ibcon#first serial, iclass 25, count 0 2006.173.08:01:39.86#ibcon#enter sib2, iclass 25, count 0 2006.173.08:01:39.86#ibcon#flushed, iclass 25, count 0 2006.173.08:01:39.86#ibcon#about to write, iclass 25, count 0 2006.173.08:01:39.86#ibcon#wrote, iclass 25, count 0 2006.173.08:01:39.86#ibcon#about to read 3, iclass 25, count 0 2006.173.08:01:39.88#ibcon#read 3, iclass 25, count 0 2006.173.08:01:39.88#ibcon#about to read 4, iclass 25, count 0 2006.173.08:01:39.88#ibcon#read 4, iclass 25, count 0 2006.173.08:01:39.88#ibcon#about to read 5, iclass 25, count 0 2006.173.08:01:39.88#ibcon#read 5, iclass 25, count 0 2006.173.08:01:39.88#ibcon#about to read 6, iclass 25, count 0 2006.173.08:01:39.88#ibcon#read 6, iclass 25, count 0 2006.173.08:01:39.88#ibcon#end of sib2, iclass 25, count 0 2006.173.08:01:39.88#ibcon#*mode == 0, iclass 25, count 0 2006.173.08:01:39.88#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.08:01:39.88#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.08:01:39.88#ibcon#*before write, iclass 25, count 0 2006.173.08:01:39.88#ibcon#enter sib2, iclass 25, count 0 2006.173.08:01:39.88#ibcon#flushed, iclass 25, count 0 2006.173.08:01:39.88#ibcon#about to write, iclass 25, count 0 2006.173.08:01:39.88#ibcon#wrote, iclass 25, count 0 2006.173.08:01:39.88#ibcon#about to read 3, iclass 25, count 0 2006.173.08:01:39.92#ibcon#read 3, iclass 25, count 0 2006.173.08:01:39.92#ibcon#about to read 4, iclass 25, count 0 2006.173.08:01:39.92#ibcon#read 4, iclass 25, count 0 2006.173.08:01:39.92#ibcon#about to read 5, iclass 25, count 0 2006.173.08:01:39.92#ibcon#read 5, iclass 25, count 0 2006.173.08:01:39.92#ibcon#about to read 6, iclass 25, count 0 2006.173.08:01:39.92#ibcon#read 6, iclass 25, count 0 2006.173.08:01:39.92#ibcon#end of sib2, iclass 25, count 0 2006.173.08:01:39.92#ibcon#*after write, iclass 25, count 0 2006.173.08:01:39.92#ibcon#*before return 0, iclass 25, count 0 2006.173.08:01:39.92#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.08:01:39.92#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.08:01:39.92#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.08:01:39.92#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.08:01:39.92$vck44/vb=4,4 2006.173.08:01:39.92#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.08:01:39.92#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.08:01:39.92#ibcon#ireg 11 cls_cnt 2 2006.173.08:01:39.92#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.08:01:39.98#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.08:01:39.98#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.08:01:39.98#ibcon#enter wrdev, iclass 27, count 2 2006.173.08:01:39.98#ibcon#first serial, iclass 27, count 2 2006.173.08:01:39.98#ibcon#enter sib2, iclass 27, count 2 2006.173.08:01:39.98#ibcon#flushed, iclass 27, count 2 2006.173.08:01:39.98#ibcon#about to write, iclass 27, count 2 2006.173.08:01:39.98#ibcon#wrote, iclass 27, count 2 2006.173.08:01:39.98#ibcon#about to read 3, iclass 27, count 2 2006.173.08:01:40.00#ibcon#read 3, iclass 27, count 2 2006.173.08:01:40.00#ibcon#about to read 4, iclass 27, count 2 2006.173.08:01:40.00#ibcon#read 4, iclass 27, count 2 2006.173.08:01:40.00#ibcon#about to read 5, iclass 27, count 2 2006.173.08:01:40.00#ibcon#read 5, iclass 27, count 2 2006.173.08:01:40.00#ibcon#about to read 6, iclass 27, count 2 2006.173.08:01:40.00#ibcon#read 6, iclass 27, count 2 2006.173.08:01:40.00#ibcon#end of sib2, iclass 27, count 2 2006.173.08:01:40.00#ibcon#*mode == 0, iclass 27, count 2 2006.173.08:01:40.00#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.08:01:40.00#ibcon#[27=AT04-04\r\n] 2006.173.08:01:40.00#ibcon#*before write, iclass 27, count 2 2006.173.08:01:40.00#ibcon#enter sib2, iclass 27, count 2 2006.173.08:01:40.00#ibcon#flushed, iclass 27, count 2 2006.173.08:01:40.00#ibcon#about to write, iclass 27, count 2 2006.173.08:01:40.00#ibcon#wrote, iclass 27, count 2 2006.173.08:01:40.00#ibcon#about to read 3, iclass 27, count 2 2006.173.08:01:40.03#ibcon#read 3, iclass 27, count 2 2006.173.08:01:40.03#ibcon#about to read 4, iclass 27, count 2 2006.173.08:01:40.03#ibcon#read 4, iclass 27, count 2 2006.173.08:01:40.03#ibcon#about to read 5, iclass 27, count 2 2006.173.08:01:40.03#ibcon#read 5, iclass 27, count 2 2006.173.08:01:40.03#ibcon#about to read 6, iclass 27, count 2 2006.173.08:01:40.03#ibcon#read 6, iclass 27, count 2 2006.173.08:01:40.03#ibcon#end of sib2, iclass 27, count 2 2006.173.08:01:40.03#ibcon#*after write, iclass 27, count 2 2006.173.08:01:40.03#ibcon#*before return 0, iclass 27, count 2 2006.173.08:01:40.03#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.08:01:40.03#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.08:01:40.03#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.08:01:40.03#ibcon#ireg 7 cls_cnt 0 2006.173.08:01:40.03#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.08:01:40.15#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.08:01:40.15#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.08:01:40.15#ibcon#enter wrdev, iclass 27, count 0 2006.173.08:01:40.15#ibcon#first serial, iclass 27, count 0 2006.173.08:01:40.15#ibcon#enter sib2, iclass 27, count 0 2006.173.08:01:40.15#ibcon#flushed, iclass 27, count 0 2006.173.08:01:40.15#ibcon#about to write, iclass 27, count 0 2006.173.08:01:40.15#ibcon#wrote, iclass 27, count 0 2006.173.08:01:40.15#ibcon#about to read 3, iclass 27, count 0 2006.173.08:01:40.17#ibcon#read 3, iclass 27, count 0 2006.173.08:01:40.17#ibcon#about to read 4, iclass 27, count 0 2006.173.08:01:40.17#ibcon#read 4, iclass 27, count 0 2006.173.08:01:40.17#ibcon#about to read 5, iclass 27, count 0 2006.173.08:01:40.17#ibcon#read 5, iclass 27, count 0 2006.173.08:01:40.17#ibcon#about to read 6, iclass 27, count 0 2006.173.08:01:40.17#ibcon#read 6, iclass 27, count 0 2006.173.08:01:40.17#ibcon#end of sib2, iclass 27, count 0 2006.173.08:01:40.17#ibcon#*mode == 0, iclass 27, count 0 2006.173.08:01:40.17#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.08:01:40.17#ibcon#[27=USB\r\n] 2006.173.08:01:40.17#ibcon#*before write, iclass 27, count 0 2006.173.08:01:40.17#ibcon#enter sib2, iclass 27, count 0 2006.173.08:01:40.17#ibcon#flushed, iclass 27, count 0 2006.173.08:01:40.17#ibcon#about to write, iclass 27, count 0 2006.173.08:01:40.17#ibcon#wrote, iclass 27, count 0 2006.173.08:01:40.17#ibcon#about to read 3, iclass 27, count 0 2006.173.08:01:40.20#ibcon#read 3, iclass 27, count 0 2006.173.08:01:40.20#ibcon#about to read 4, iclass 27, count 0 2006.173.08:01:40.20#ibcon#read 4, iclass 27, count 0 2006.173.08:01:40.20#ibcon#about to read 5, iclass 27, count 0 2006.173.08:01:40.20#ibcon#read 5, iclass 27, count 0 2006.173.08:01:40.20#ibcon#about to read 6, iclass 27, count 0 2006.173.08:01:40.20#ibcon#read 6, iclass 27, count 0 2006.173.08:01:40.20#ibcon#end of sib2, iclass 27, count 0 2006.173.08:01:40.20#ibcon#*after write, iclass 27, count 0 2006.173.08:01:40.20#ibcon#*before return 0, iclass 27, count 0 2006.173.08:01:40.20#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.08:01:40.20#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.08:01:40.20#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.08:01:40.20#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.08:01:40.20$vck44/vblo=5,709.99 2006.173.08:01:40.20#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.08:01:40.20#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.08:01:40.20#ibcon#ireg 17 cls_cnt 0 2006.173.08:01:40.20#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.08:01:40.20#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.08:01:40.20#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.08:01:40.20#ibcon#enter wrdev, iclass 29, count 0 2006.173.08:01:40.20#ibcon#first serial, iclass 29, count 0 2006.173.08:01:40.20#ibcon#enter sib2, iclass 29, count 0 2006.173.08:01:40.20#ibcon#flushed, iclass 29, count 0 2006.173.08:01:40.20#ibcon#about to write, iclass 29, count 0 2006.173.08:01:40.20#ibcon#wrote, iclass 29, count 0 2006.173.08:01:40.20#ibcon#about to read 3, iclass 29, count 0 2006.173.08:01:40.22#ibcon#read 3, iclass 29, count 0 2006.173.08:01:40.22#ibcon#about to read 4, iclass 29, count 0 2006.173.08:01:40.22#ibcon#read 4, iclass 29, count 0 2006.173.08:01:40.22#ibcon#about to read 5, iclass 29, count 0 2006.173.08:01:40.22#ibcon#read 5, iclass 29, count 0 2006.173.08:01:40.22#ibcon#about to read 6, iclass 29, count 0 2006.173.08:01:40.22#ibcon#read 6, iclass 29, count 0 2006.173.08:01:40.22#ibcon#end of sib2, iclass 29, count 0 2006.173.08:01:40.22#ibcon#*mode == 0, iclass 29, count 0 2006.173.08:01:40.22#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.08:01:40.22#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.08:01:40.22#ibcon#*before write, iclass 29, count 0 2006.173.08:01:40.22#ibcon#enter sib2, iclass 29, count 0 2006.173.08:01:40.22#ibcon#flushed, iclass 29, count 0 2006.173.08:01:40.22#ibcon#about to write, iclass 29, count 0 2006.173.08:01:40.22#ibcon#wrote, iclass 29, count 0 2006.173.08:01:40.22#ibcon#about to read 3, iclass 29, count 0 2006.173.08:01:40.26#ibcon#read 3, iclass 29, count 0 2006.173.08:01:40.26#ibcon#about to read 4, iclass 29, count 0 2006.173.08:01:40.26#ibcon#read 4, iclass 29, count 0 2006.173.08:01:40.26#ibcon#about to read 5, iclass 29, count 0 2006.173.08:01:40.26#ibcon#read 5, iclass 29, count 0 2006.173.08:01:40.26#ibcon#about to read 6, iclass 29, count 0 2006.173.08:01:40.26#ibcon#read 6, iclass 29, count 0 2006.173.08:01:40.26#ibcon#end of sib2, iclass 29, count 0 2006.173.08:01:40.26#ibcon#*after write, iclass 29, count 0 2006.173.08:01:40.26#ibcon#*before return 0, iclass 29, count 0 2006.173.08:01:40.26#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.08:01:40.26#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.08:01:40.26#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.08:01:40.26#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.08:01:40.26$vck44/vb=5,4 2006.173.08:01:40.26#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.08:01:40.26#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.08:01:40.26#ibcon#ireg 11 cls_cnt 2 2006.173.08:01:40.26#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.08:01:40.32#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.08:01:40.32#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.08:01:40.32#ibcon#enter wrdev, iclass 31, count 2 2006.173.08:01:40.32#ibcon#first serial, iclass 31, count 2 2006.173.08:01:40.32#ibcon#enter sib2, iclass 31, count 2 2006.173.08:01:40.32#ibcon#flushed, iclass 31, count 2 2006.173.08:01:40.32#ibcon#about to write, iclass 31, count 2 2006.173.08:01:40.32#ibcon#wrote, iclass 31, count 2 2006.173.08:01:40.32#ibcon#about to read 3, iclass 31, count 2 2006.173.08:01:40.34#ibcon#read 3, iclass 31, count 2 2006.173.08:01:40.34#ibcon#about to read 4, iclass 31, count 2 2006.173.08:01:40.34#ibcon#read 4, iclass 31, count 2 2006.173.08:01:40.34#ibcon#about to read 5, iclass 31, count 2 2006.173.08:01:40.34#ibcon#read 5, iclass 31, count 2 2006.173.08:01:40.34#ibcon#about to read 6, iclass 31, count 2 2006.173.08:01:40.34#ibcon#read 6, iclass 31, count 2 2006.173.08:01:40.34#ibcon#end of sib2, iclass 31, count 2 2006.173.08:01:40.34#ibcon#*mode == 0, iclass 31, count 2 2006.173.08:01:40.34#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.08:01:40.34#ibcon#[27=AT05-04\r\n] 2006.173.08:01:40.34#ibcon#*before write, iclass 31, count 2 2006.173.08:01:40.34#ibcon#enter sib2, iclass 31, count 2 2006.173.08:01:40.34#ibcon#flushed, iclass 31, count 2 2006.173.08:01:40.34#ibcon#about to write, iclass 31, count 2 2006.173.08:01:40.34#ibcon#wrote, iclass 31, count 2 2006.173.08:01:40.34#ibcon#about to read 3, iclass 31, count 2 2006.173.08:01:40.37#ibcon#read 3, iclass 31, count 2 2006.173.08:01:40.37#ibcon#about to read 4, iclass 31, count 2 2006.173.08:01:40.37#ibcon#read 4, iclass 31, count 2 2006.173.08:01:40.37#ibcon#about to read 5, iclass 31, count 2 2006.173.08:01:40.37#ibcon#read 5, iclass 31, count 2 2006.173.08:01:40.37#ibcon#about to read 6, iclass 31, count 2 2006.173.08:01:40.37#ibcon#read 6, iclass 31, count 2 2006.173.08:01:40.37#ibcon#end of sib2, iclass 31, count 2 2006.173.08:01:40.37#ibcon#*after write, iclass 31, count 2 2006.173.08:01:40.37#ibcon#*before return 0, iclass 31, count 2 2006.173.08:01:40.37#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.08:01:40.37#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.08:01:40.37#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.08:01:40.37#ibcon#ireg 7 cls_cnt 0 2006.173.08:01:40.37#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.08:01:40.49#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.08:01:40.49#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.08:01:40.49#ibcon#enter wrdev, iclass 31, count 0 2006.173.08:01:40.49#ibcon#first serial, iclass 31, count 0 2006.173.08:01:40.49#ibcon#enter sib2, iclass 31, count 0 2006.173.08:01:40.49#ibcon#flushed, iclass 31, count 0 2006.173.08:01:40.49#ibcon#about to write, iclass 31, count 0 2006.173.08:01:40.49#ibcon#wrote, iclass 31, count 0 2006.173.08:01:40.49#ibcon#about to read 3, iclass 31, count 0 2006.173.08:01:40.51#ibcon#read 3, iclass 31, count 0 2006.173.08:01:40.51#ibcon#about to read 4, iclass 31, count 0 2006.173.08:01:40.51#ibcon#read 4, iclass 31, count 0 2006.173.08:01:40.51#ibcon#about to read 5, iclass 31, count 0 2006.173.08:01:40.51#ibcon#read 5, iclass 31, count 0 2006.173.08:01:40.51#ibcon#about to read 6, iclass 31, count 0 2006.173.08:01:40.51#ibcon#read 6, iclass 31, count 0 2006.173.08:01:40.51#ibcon#end of sib2, iclass 31, count 0 2006.173.08:01:40.51#ibcon#*mode == 0, iclass 31, count 0 2006.173.08:01:40.51#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.08:01:40.51#ibcon#[27=USB\r\n] 2006.173.08:01:40.51#ibcon#*before write, iclass 31, count 0 2006.173.08:01:40.51#ibcon#enter sib2, iclass 31, count 0 2006.173.08:01:40.51#ibcon#flushed, iclass 31, count 0 2006.173.08:01:40.51#ibcon#about to write, iclass 31, count 0 2006.173.08:01:40.51#ibcon#wrote, iclass 31, count 0 2006.173.08:01:40.51#ibcon#about to read 3, iclass 31, count 0 2006.173.08:01:40.54#ibcon#read 3, iclass 31, count 0 2006.173.08:01:40.54#ibcon#about to read 4, iclass 31, count 0 2006.173.08:01:40.54#ibcon#read 4, iclass 31, count 0 2006.173.08:01:40.54#ibcon#about to read 5, iclass 31, count 0 2006.173.08:01:40.54#ibcon#read 5, iclass 31, count 0 2006.173.08:01:40.54#ibcon#about to read 6, iclass 31, count 0 2006.173.08:01:40.54#ibcon#read 6, iclass 31, count 0 2006.173.08:01:40.54#ibcon#end of sib2, iclass 31, count 0 2006.173.08:01:40.54#ibcon#*after write, iclass 31, count 0 2006.173.08:01:40.54#ibcon#*before return 0, iclass 31, count 0 2006.173.08:01:40.54#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.08:01:40.54#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.08:01:40.54#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.08:01:40.54#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.08:01:40.54$vck44/vblo=6,719.99 2006.173.08:01:40.54#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.08:01:40.54#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.08:01:40.54#ibcon#ireg 17 cls_cnt 0 2006.173.08:01:40.54#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.08:01:40.54#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.08:01:40.54#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.08:01:40.54#ibcon#enter wrdev, iclass 33, count 0 2006.173.08:01:40.54#ibcon#first serial, iclass 33, count 0 2006.173.08:01:40.54#ibcon#enter sib2, iclass 33, count 0 2006.173.08:01:40.54#ibcon#flushed, iclass 33, count 0 2006.173.08:01:40.54#ibcon#about to write, iclass 33, count 0 2006.173.08:01:40.54#ibcon#wrote, iclass 33, count 0 2006.173.08:01:40.54#ibcon#about to read 3, iclass 33, count 0 2006.173.08:01:40.56#ibcon#read 3, iclass 33, count 0 2006.173.08:01:40.56#ibcon#about to read 4, iclass 33, count 0 2006.173.08:01:40.56#ibcon#read 4, iclass 33, count 0 2006.173.08:01:40.56#ibcon#about to read 5, iclass 33, count 0 2006.173.08:01:40.56#ibcon#read 5, iclass 33, count 0 2006.173.08:01:40.56#ibcon#about to read 6, iclass 33, count 0 2006.173.08:01:40.56#ibcon#read 6, iclass 33, count 0 2006.173.08:01:40.56#ibcon#end of sib2, iclass 33, count 0 2006.173.08:01:40.56#ibcon#*mode == 0, iclass 33, count 0 2006.173.08:01:40.56#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.08:01:40.56#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.08:01:40.56#ibcon#*before write, iclass 33, count 0 2006.173.08:01:40.56#ibcon#enter sib2, iclass 33, count 0 2006.173.08:01:40.56#ibcon#flushed, iclass 33, count 0 2006.173.08:01:40.56#ibcon#about to write, iclass 33, count 0 2006.173.08:01:40.56#ibcon#wrote, iclass 33, count 0 2006.173.08:01:40.56#ibcon#about to read 3, iclass 33, count 0 2006.173.08:01:40.60#ibcon#read 3, iclass 33, count 0 2006.173.08:01:40.60#ibcon#about to read 4, iclass 33, count 0 2006.173.08:01:40.60#ibcon#read 4, iclass 33, count 0 2006.173.08:01:40.60#ibcon#about to read 5, iclass 33, count 0 2006.173.08:01:40.60#ibcon#read 5, iclass 33, count 0 2006.173.08:01:40.60#ibcon#about to read 6, iclass 33, count 0 2006.173.08:01:40.60#ibcon#read 6, iclass 33, count 0 2006.173.08:01:40.60#ibcon#end of sib2, iclass 33, count 0 2006.173.08:01:40.60#ibcon#*after write, iclass 33, count 0 2006.173.08:01:40.60#ibcon#*before return 0, iclass 33, count 0 2006.173.08:01:40.60#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.08:01:40.60#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.08:01:40.60#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.08:01:40.60#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.08:01:40.60$vck44/vb=6,4 2006.173.08:01:40.60#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.08:01:40.60#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.08:01:40.60#ibcon#ireg 11 cls_cnt 2 2006.173.08:01:40.60#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.08:01:40.66#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.08:01:40.66#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.08:01:40.66#ibcon#enter wrdev, iclass 35, count 2 2006.173.08:01:40.66#ibcon#first serial, iclass 35, count 2 2006.173.08:01:40.66#ibcon#enter sib2, iclass 35, count 2 2006.173.08:01:40.66#ibcon#flushed, iclass 35, count 2 2006.173.08:01:40.66#ibcon#about to write, iclass 35, count 2 2006.173.08:01:40.66#ibcon#wrote, iclass 35, count 2 2006.173.08:01:40.66#ibcon#about to read 3, iclass 35, count 2 2006.173.08:01:40.68#ibcon#read 3, iclass 35, count 2 2006.173.08:01:40.68#ibcon#about to read 4, iclass 35, count 2 2006.173.08:01:40.68#ibcon#read 4, iclass 35, count 2 2006.173.08:01:40.68#ibcon#about to read 5, iclass 35, count 2 2006.173.08:01:40.68#ibcon#read 5, iclass 35, count 2 2006.173.08:01:40.68#ibcon#about to read 6, iclass 35, count 2 2006.173.08:01:40.68#ibcon#read 6, iclass 35, count 2 2006.173.08:01:40.68#ibcon#end of sib2, iclass 35, count 2 2006.173.08:01:40.68#ibcon#*mode == 0, iclass 35, count 2 2006.173.08:01:40.68#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.08:01:40.68#ibcon#[27=AT06-04\r\n] 2006.173.08:01:40.68#ibcon#*before write, iclass 35, count 2 2006.173.08:01:40.68#ibcon#enter sib2, iclass 35, count 2 2006.173.08:01:40.68#ibcon#flushed, iclass 35, count 2 2006.173.08:01:40.68#ibcon#about to write, iclass 35, count 2 2006.173.08:01:40.68#ibcon#wrote, iclass 35, count 2 2006.173.08:01:40.68#ibcon#about to read 3, iclass 35, count 2 2006.173.08:01:40.71#ibcon#read 3, iclass 35, count 2 2006.173.08:01:40.71#ibcon#about to read 4, iclass 35, count 2 2006.173.08:01:40.71#ibcon#read 4, iclass 35, count 2 2006.173.08:01:40.71#ibcon#about to read 5, iclass 35, count 2 2006.173.08:01:40.71#ibcon#read 5, iclass 35, count 2 2006.173.08:01:40.71#ibcon#about to read 6, iclass 35, count 2 2006.173.08:01:40.71#ibcon#read 6, iclass 35, count 2 2006.173.08:01:40.71#ibcon#end of sib2, iclass 35, count 2 2006.173.08:01:40.71#ibcon#*after write, iclass 35, count 2 2006.173.08:01:40.71#ibcon#*before return 0, iclass 35, count 2 2006.173.08:01:40.71#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.08:01:40.71#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.08:01:40.71#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.08:01:40.71#ibcon#ireg 7 cls_cnt 0 2006.173.08:01:40.71#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.08:01:40.83#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.08:01:40.83#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.08:01:40.83#ibcon#enter wrdev, iclass 35, count 0 2006.173.08:01:40.83#ibcon#first serial, iclass 35, count 0 2006.173.08:01:40.83#ibcon#enter sib2, iclass 35, count 0 2006.173.08:01:40.83#ibcon#flushed, iclass 35, count 0 2006.173.08:01:40.83#ibcon#about to write, iclass 35, count 0 2006.173.08:01:40.83#ibcon#wrote, iclass 35, count 0 2006.173.08:01:40.83#ibcon#about to read 3, iclass 35, count 0 2006.173.08:01:40.85#ibcon#read 3, iclass 35, count 0 2006.173.08:01:40.85#ibcon#about to read 4, iclass 35, count 0 2006.173.08:01:40.85#ibcon#read 4, iclass 35, count 0 2006.173.08:01:40.85#ibcon#about to read 5, iclass 35, count 0 2006.173.08:01:40.85#ibcon#read 5, iclass 35, count 0 2006.173.08:01:40.85#ibcon#about to read 6, iclass 35, count 0 2006.173.08:01:40.85#ibcon#read 6, iclass 35, count 0 2006.173.08:01:40.85#ibcon#end of sib2, iclass 35, count 0 2006.173.08:01:40.85#ibcon#*mode == 0, iclass 35, count 0 2006.173.08:01:40.85#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.08:01:40.85#ibcon#[27=USB\r\n] 2006.173.08:01:40.85#ibcon#*before write, iclass 35, count 0 2006.173.08:01:40.85#ibcon#enter sib2, iclass 35, count 0 2006.173.08:01:40.85#ibcon#flushed, iclass 35, count 0 2006.173.08:01:40.85#ibcon#about to write, iclass 35, count 0 2006.173.08:01:40.85#ibcon#wrote, iclass 35, count 0 2006.173.08:01:40.85#ibcon#about to read 3, iclass 35, count 0 2006.173.08:01:40.88#ibcon#read 3, iclass 35, count 0 2006.173.08:01:40.88#ibcon#about to read 4, iclass 35, count 0 2006.173.08:01:40.88#ibcon#read 4, iclass 35, count 0 2006.173.08:01:40.88#ibcon#about to read 5, iclass 35, count 0 2006.173.08:01:40.88#ibcon#read 5, iclass 35, count 0 2006.173.08:01:40.88#ibcon#about to read 6, iclass 35, count 0 2006.173.08:01:40.88#ibcon#read 6, iclass 35, count 0 2006.173.08:01:40.88#ibcon#end of sib2, iclass 35, count 0 2006.173.08:01:40.88#ibcon#*after write, iclass 35, count 0 2006.173.08:01:40.88#ibcon#*before return 0, iclass 35, count 0 2006.173.08:01:40.88#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.08:01:40.88#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.08:01:40.88#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.08:01:40.88#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.08:01:40.88$vck44/vblo=7,734.99 2006.173.08:01:40.88#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.08:01:40.88#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.08:01:40.88#ibcon#ireg 17 cls_cnt 0 2006.173.08:01:40.88#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.08:01:40.88#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.08:01:40.88#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.08:01:40.88#ibcon#enter wrdev, iclass 37, count 0 2006.173.08:01:40.88#ibcon#first serial, iclass 37, count 0 2006.173.08:01:40.88#ibcon#enter sib2, iclass 37, count 0 2006.173.08:01:40.88#ibcon#flushed, iclass 37, count 0 2006.173.08:01:40.88#ibcon#about to write, iclass 37, count 0 2006.173.08:01:40.88#ibcon#wrote, iclass 37, count 0 2006.173.08:01:40.88#ibcon#about to read 3, iclass 37, count 0 2006.173.08:01:40.90#ibcon#read 3, iclass 37, count 0 2006.173.08:01:40.90#ibcon#about to read 4, iclass 37, count 0 2006.173.08:01:40.90#ibcon#read 4, iclass 37, count 0 2006.173.08:01:40.90#ibcon#about to read 5, iclass 37, count 0 2006.173.08:01:40.90#ibcon#read 5, iclass 37, count 0 2006.173.08:01:40.90#ibcon#about to read 6, iclass 37, count 0 2006.173.08:01:40.90#ibcon#read 6, iclass 37, count 0 2006.173.08:01:40.90#ibcon#end of sib2, iclass 37, count 0 2006.173.08:01:40.90#ibcon#*mode == 0, iclass 37, count 0 2006.173.08:01:40.90#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.08:01:40.90#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.08:01:40.90#ibcon#*before write, iclass 37, count 0 2006.173.08:01:40.90#ibcon#enter sib2, iclass 37, count 0 2006.173.08:01:40.90#ibcon#flushed, iclass 37, count 0 2006.173.08:01:40.90#ibcon#about to write, iclass 37, count 0 2006.173.08:01:40.90#ibcon#wrote, iclass 37, count 0 2006.173.08:01:40.90#ibcon#about to read 3, iclass 37, count 0 2006.173.08:01:40.94#ibcon#read 3, iclass 37, count 0 2006.173.08:01:40.94#ibcon#about to read 4, iclass 37, count 0 2006.173.08:01:40.94#ibcon#read 4, iclass 37, count 0 2006.173.08:01:40.94#ibcon#about to read 5, iclass 37, count 0 2006.173.08:01:40.94#ibcon#read 5, iclass 37, count 0 2006.173.08:01:40.94#ibcon#about to read 6, iclass 37, count 0 2006.173.08:01:40.94#ibcon#read 6, iclass 37, count 0 2006.173.08:01:40.94#ibcon#end of sib2, iclass 37, count 0 2006.173.08:01:40.94#ibcon#*after write, iclass 37, count 0 2006.173.08:01:40.94#ibcon#*before return 0, iclass 37, count 0 2006.173.08:01:40.94#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.08:01:40.94#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.08:01:40.94#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.08:01:40.94#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.08:01:40.94$vck44/vb=7,4 2006.173.08:01:40.94#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.08:01:40.94#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.08:01:40.94#ibcon#ireg 11 cls_cnt 2 2006.173.08:01:40.94#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.08:01:41.00#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.08:01:41.00#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.08:01:41.00#ibcon#enter wrdev, iclass 39, count 2 2006.173.08:01:41.00#ibcon#first serial, iclass 39, count 2 2006.173.08:01:41.00#ibcon#enter sib2, iclass 39, count 2 2006.173.08:01:41.00#ibcon#flushed, iclass 39, count 2 2006.173.08:01:41.00#ibcon#about to write, iclass 39, count 2 2006.173.08:01:41.00#ibcon#wrote, iclass 39, count 2 2006.173.08:01:41.00#ibcon#about to read 3, iclass 39, count 2 2006.173.08:01:41.02#ibcon#read 3, iclass 39, count 2 2006.173.08:01:41.02#ibcon#about to read 4, iclass 39, count 2 2006.173.08:01:41.02#ibcon#read 4, iclass 39, count 2 2006.173.08:01:41.02#ibcon#about to read 5, iclass 39, count 2 2006.173.08:01:41.02#ibcon#read 5, iclass 39, count 2 2006.173.08:01:41.02#ibcon#about to read 6, iclass 39, count 2 2006.173.08:01:41.02#ibcon#read 6, iclass 39, count 2 2006.173.08:01:41.02#ibcon#end of sib2, iclass 39, count 2 2006.173.08:01:41.02#ibcon#*mode == 0, iclass 39, count 2 2006.173.08:01:41.02#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.08:01:41.02#ibcon#[27=AT07-04\r\n] 2006.173.08:01:41.02#ibcon#*before write, iclass 39, count 2 2006.173.08:01:41.02#ibcon#enter sib2, iclass 39, count 2 2006.173.08:01:41.02#ibcon#flushed, iclass 39, count 2 2006.173.08:01:41.02#ibcon#about to write, iclass 39, count 2 2006.173.08:01:41.02#ibcon#wrote, iclass 39, count 2 2006.173.08:01:41.02#ibcon#about to read 3, iclass 39, count 2 2006.173.08:01:41.05#ibcon#read 3, iclass 39, count 2 2006.173.08:01:41.05#ibcon#about to read 4, iclass 39, count 2 2006.173.08:01:41.05#ibcon#read 4, iclass 39, count 2 2006.173.08:01:41.05#ibcon#about to read 5, iclass 39, count 2 2006.173.08:01:41.05#ibcon#read 5, iclass 39, count 2 2006.173.08:01:41.05#ibcon#about to read 6, iclass 39, count 2 2006.173.08:01:41.05#ibcon#read 6, iclass 39, count 2 2006.173.08:01:41.05#ibcon#end of sib2, iclass 39, count 2 2006.173.08:01:41.05#ibcon#*after write, iclass 39, count 2 2006.173.08:01:41.05#ibcon#*before return 0, iclass 39, count 2 2006.173.08:01:41.05#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.08:01:41.05#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.08:01:41.05#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.08:01:41.05#ibcon#ireg 7 cls_cnt 0 2006.173.08:01:41.05#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.08:01:41.17#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.08:01:41.17#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.08:01:41.17#ibcon#enter wrdev, iclass 39, count 0 2006.173.08:01:41.17#ibcon#first serial, iclass 39, count 0 2006.173.08:01:41.17#ibcon#enter sib2, iclass 39, count 0 2006.173.08:01:41.17#ibcon#flushed, iclass 39, count 0 2006.173.08:01:41.17#ibcon#about to write, iclass 39, count 0 2006.173.08:01:41.17#ibcon#wrote, iclass 39, count 0 2006.173.08:01:41.17#ibcon#about to read 3, iclass 39, count 0 2006.173.08:01:41.19#ibcon#read 3, iclass 39, count 0 2006.173.08:01:41.19#ibcon#about to read 4, iclass 39, count 0 2006.173.08:01:41.19#ibcon#read 4, iclass 39, count 0 2006.173.08:01:41.19#ibcon#about to read 5, iclass 39, count 0 2006.173.08:01:41.19#ibcon#read 5, iclass 39, count 0 2006.173.08:01:41.19#ibcon#about to read 6, iclass 39, count 0 2006.173.08:01:41.19#ibcon#read 6, iclass 39, count 0 2006.173.08:01:41.19#ibcon#end of sib2, iclass 39, count 0 2006.173.08:01:41.19#ibcon#*mode == 0, iclass 39, count 0 2006.173.08:01:41.19#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.08:01:41.19#ibcon#[27=USB\r\n] 2006.173.08:01:41.19#ibcon#*before write, iclass 39, count 0 2006.173.08:01:41.19#ibcon#enter sib2, iclass 39, count 0 2006.173.08:01:41.19#ibcon#flushed, iclass 39, count 0 2006.173.08:01:41.19#ibcon#about to write, iclass 39, count 0 2006.173.08:01:41.19#ibcon#wrote, iclass 39, count 0 2006.173.08:01:41.19#ibcon#about to read 3, iclass 39, count 0 2006.173.08:01:41.22#ibcon#read 3, iclass 39, count 0 2006.173.08:01:41.22#ibcon#about to read 4, iclass 39, count 0 2006.173.08:01:41.22#ibcon#read 4, iclass 39, count 0 2006.173.08:01:41.22#ibcon#about to read 5, iclass 39, count 0 2006.173.08:01:41.22#ibcon#read 5, iclass 39, count 0 2006.173.08:01:41.22#ibcon#about to read 6, iclass 39, count 0 2006.173.08:01:41.22#ibcon#read 6, iclass 39, count 0 2006.173.08:01:41.22#ibcon#end of sib2, iclass 39, count 0 2006.173.08:01:41.22#ibcon#*after write, iclass 39, count 0 2006.173.08:01:41.22#ibcon#*before return 0, iclass 39, count 0 2006.173.08:01:41.22#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.08:01:41.22#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.08:01:41.22#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.08:01:41.22#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.08:01:41.22$vck44/vblo=8,744.99 2006.173.08:01:41.22#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.08:01:41.22#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.08:01:41.22#ibcon#ireg 17 cls_cnt 0 2006.173.08:01:41.22#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.08:01:41.22#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.08:01:41.22#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.08:01:41.22#ibcon#enter wrdev, iclass 3, count 0 2006.173.08:01:41.22#ibcon#first serial, iclass 3, count 0 2006.173.08:01:41.22#ibcon#enter sib2, iclass 3, count 0 2006.173.08:01:41.22#ibcon#flushed, iclass 3, count 0 2006.173.08:01:41.22#ibcon#about to write, iclass 3, count 0 2006.173.08:01:41.22#ibcon#wrote, iclass 3, count 0 2006.173.08:01:41.22#ibcon#about to read 3, iclass 3, count 0 2006.173.08:01:41.24#ibcon#read 3, iclass 3, count 0 2006.173.08:01:41.24#ibcon#about to read 4, iclass 3, count 0 2006.173.08:01:41.24#ibcon#read 4, iclass 3, count 0 2006.173.08:01:41.24#ibcon#about to read 5, iclass 3, count 0 2006.173.08:01:41.24#ibcon#read 5, iclass 3, count 0 2006.173.08:01:41.24#ibcon#about to read 6, iclass 3, count 0 2006.173.08:01:41.24#ibcon#read 6, iclass 3, count 0 2006.173.08:01:41.24#ibcon#end of sib2, iclass 3, count 0 2006.173.08:01:41.24#ibcon#*mode == 0, iclass 3, count 0 2006.173.08:01:41.24#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.08:01:41.24#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.08:01:41.24#ibcon#*before write, iclass 3, count 0 2006.173.08:01:41.24#ibcon#enter sib2, iclass 3, count 0 2006.173.08:01:41.24#ibcon#flushed, iclass 3, count 0 2006.173.08:01:41.24#ibcon#about to write, iclass 3, count 0 2006.173.08:01:41.24#ibcon#wrote, iclass 3, count 0 2006.173.08:01:41.24#ibcon#about to read 3, iclass 3, count 0 2006.173.08:01:41.28#ibcon#read 3, iclass 3, count 0 2006.173.08:01:41.28#ibcon#about to read 4, iclass 3, count 0 2006.173.08:01:41.28#ibcon#read 4, iclass 3, count 0 2006.173.08:01:41.28#ibcon#about to read 5, iclass 3, count 0 2006.173.08:01:41.28#ibcon#read 5, iclass 3, count 0 2006.173.08:01:41.28#ibcon#about to read 6, iclass 3, count 0 2006.173.08:01:41.28#ibcon#read 6, iclass 3, count 0 2006.173.08:01:41.28#ibcon#end of sib2, iclass 3, count 0 2006.173.08:01:41.28#ibcon#*after write, iclass 3, count 0 2006.173.08:01:41.28#ibcon#*before return 0, iclass 3, count 0 2006.173.08:01:41.28#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.08:01:41.28#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.08:01:41.28#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.08:01:41.28#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.08:01:41.28$vck44/vb=8,4 2006.173.08:01:41.28#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.08:01:41.28#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.08:01:41.28#ibcon#ireg 11 cls_cnt 2 2006.173.08:01:41.28#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.08:01:41.34#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.08:01:41.34#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.08:01:41.34#ibcon#enter wrdev, iclass 5, count 2 2006.173.08:01:41.34#ibcon#first serial, iclass 5, count 2 2006.173.08:01:41.34#ibcon#enter sib2, iclass 5, count 2 2006.173.08:01:41.34#ibcon#flushed, iclass 5, count 2 2006.173.08:01:41.34#ibcon#about to write, iclass 5, count 2 2006.173.08:01:41.34#ibcon#wrote, iclass 5, count 2 2006.173.08:01:41.34#ibcon#about to read 3, iclass 5, count 2 2006.173.08:01:41.36#ibcon#read 3, iclass 5, count 2 2006.173.08:01:41.36#ibcon#about to read 4, iclass 5, count 2 2006.173.08:01:41.36#ibcon#read 4, iclass 5, count 2 2006.173.08:01:41.36#ibcon#about to read 5, iclass 5, count 2 2006.173.08:01:41.36#ibcon#read 5, iclass 5, count 2 2006.173.08:01:41.36#ibcon#about to read 6, iclass 5, count 2 2006.173.08:01:41.36#ibcon#read 6, iclass 5, count 2 2006.173.08:01:41.36#ibcon#end of sib2, iclass 5, count 2 2006.173.08:01:41.36#ibcon#*mode == 0, iclass 5, count 2 2006.173.08:01:41.36#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.08:01:41.36#ibcon#[27=AT08-04\r\n] 2006.173.08:01:41.36#ibcon#*before write, iclass 5, count 2 2006.173.08:01:41.36#ibcon#enter sib2, iclass 5, count 2 2006.173.08:01:41.36#ibcon#flushed, iclass 5, count 2 2006.173.08:01:41.36#ibcon#about to write, iclass 5, count 2 2006.173.08:01:41.36#ibcon#wrote, iclass 5, count 2 2006.173.08:01:41.36#ibcon#about to read 3, iclass 5, count 2 2006.173.08:01:41.39#ibcon#read 3, iclass 5, count 2 2006.173.08:01:41.39#ibcon#about to read 4, iclass 5, count 2 2006.173.08:01:41.39#ibcon#read 4, iclass 5, count 2 2006.173.08:01:41.39#ibcon#about to read 5, iclass 5, count 2 2006.173.08:01:41.39#ibcon#read 5, iclass 5, count 2 2006.173.08:01:41.39#ibcon#about to read 6, iclass 5, count 2 2006.173.08:01:41.39#ibcon#read 6, iclass 5, count 2 2006.173.08:01:41.39#ibcon#end of sib2, iclass 5, count 2 2006.173.08:01:41.39#ibcon#*after write, iclass 5, count 2 2006.173.08:01:41.39#ibcon#*before return 0, iclass 5, count 2 2006.173.08:01:41.39#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.08:01:41.39#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.08:01:41.39#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.08:01:41.39#ibcon#ireg 7 cls_cnt 0 2006.173.08:01:41.39#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.08:01:41.51#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.08:01:41.51#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.08:01:41.51#ibcon#enter wrdev, iclass 5, count 0 2006.173.08:01:41.51#ibcon#first serial, iclass 5, count 0 2006.173.08:01:41.51#ibcon#enter sib2, iclass 5, count 0 2006.173.08:01:41.51#ibcon#flushed, iclass 5, count 0 2006.173.08:01:41.51#ibcon#about to write, iclass 5, count 0 2006.173.08:01:41.51#ibcon#wrote, iclass 5, count 0 2006.173.08:01:41.51#ibcon#about to read 3, iclass 5, count 0 2006.173.08:01:41.53#ibcon#read 3, iclass 5, count 0 2006.173.08:01:41.53#ibcon#about to read 4, iclass 5, count 0 2006.173.08:01:41.53#ibcon#read 4, iclass 5, count 0 2006.173.08:01:41.53#ibcon#about to read 5, iclass 5, count 0 2006.173.08:01:41.53#ibcon#read 5, iclass 5, count 0 2006.173.08:01:41.53#ibcon#about to read 6, iclass 5, count 0 2006.173.08:01:41.53#ibcon#read 6, iclass 5, count 0 2006.173.08:01:41.53#ibcon#end of sib2, iclass 5, count 0 2006.173.08:01:41.53#ibcon#*mode == 0, iclass 5, count 0 2006.173.08:01:41.53#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.08:01:41.53#ibcon#[27=USB\r\n] 2006.173.08:01:41.53#ibcon#*before write, iclass 5, count 0 2006.173.08:01:41.53#ibcon#enter sib2, iclass 5, count 0 2006.173.08:01:41.53#ibcon#flushed, iclass 5, count 0 2006.173.08:01:41.53#ibcon#about to write, iclass 5, count 0 2006.173.08:01:41.53#ibcon#wrote, iclass 5, count 0 2006.173.08:01:41.53#ibcon#about to read 3, iclass 5, count 0 2006.173.08:01:41.56#ibcon#read 3, iclass 5, count 0 2006.173.08:01:41.56#ibcon#about to read 4, iclass 5, count 0 2006.173.08:01:41.56#ibcon#read 4, iclass 5, count 0 2006.173.08:01:41.56#ibcon#about to read 5, iclass 5, count 0 2006.173.08:01:41.56#ibcon#read 5, iclass 5, count 0 2006.173.08:01:41.56#ibcon#about to read 6, iclass 5, count 0 2006.173.08:01:41.56#ibcon#read 6, iclass 5, count 0 2006.173.08:01:41.56#ibcon#end of sib2, iclass 5, count 0 2006.173.08:01:41.56#ibcon#*after write, iclass 5, count 0 2006.173.08:01:41.56#ibcon#*before return 0, iclass 5, count 0 2006.173.08:01:41.56#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.08:01:41.56#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.08:01:41.56#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.08:01:41.56#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.08:01:41.56$vck44/vabw=wide 2006.173.08:01:41.56#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.08:01:41.56#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.08:01:41.56#ibcon#ireg 8 cls_cnt 0 2006.173.08:01:41.56#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.08:01:41.56#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.08:01:41.56#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.08:01:41.56#ibcon#enter wrdev, iclass 7, count 0 2006.173.08:01:41.56#ibcon#first serial, iclass 7, count 0 2006.173.08:01:41.56#ibcon#enter sib2, iclass 7, count 0 2006.173.08:01:41.56#ibcon#flushed, iclass 7, count 0 2006.173.08:01:41.56#ibcon#about to write, iclass 7, count 0 2006.173.08:01:41.56#ibcon#wrote, iclass 7, count 0 2006.173.08:01:41.56#ibcon#about to read 3, iclass 7, count 0 2006.173.08:01:41.58#ibcon#read 3, iclass 7, count 0 2006.173.08:01:41.58#ibcon#about to read 4, iclass 7, count 0 2006.173.08:01:41.58#ibcon#read 4, iclass 7, count 0 2006.173.08:01:41.58#ibcon#about to read 5, iclass 7, count 0 2006.173.08:01:41.58#ibcon#read 5, iclass 7, count 0 2006.173.08:01:41.58#ibcon#about to read 6, iclass 7, count 0 2006.173.08:01:41.58#ibcon#read 6, iclass 7, count 0 2006.173.08:01:41.58#ibcon#end of sib2, iclass 7, count 0 2006.173.08:01:41.58#ibcon#*mode == 0, iclass 7, count 0 2006.173.08:01:41.58#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.08:01:41.58#ibcon#[25=BW32\r\n] 2006.173.08:01:41.58#ibcon#*before write, iclass 7, count 0 2006.173.08:01:41.58#ibcon#enter sib2, iclass 7, count 0 2006.173.08:01:41.58#ibcon#flushed, iclass 7, count 0 2006.173.08:01:41.58#ibcon#about to write, iclass 7, count 0 2006.173.08:01:41.58#ibcon#wrote, iclass 7, count 0 2006.173.08:01:41.58#ibcon#about to read 3, iclass 7, count 0 2006.173.08:01:41.61#ibcon#read 3, iclass 7, count 0 2006.173.08:01:41.61#ibcon#about to read 4, iclass 7, count 0 2006.173.08:01:41.61#ibcon#read 4, iclass 7, count 0 2006.173.08:01:41.61#ibcon#about to read 5, iclass 7, count 0 2006.173.08:01:41.61#ibcon#read 5, iclass 7, count 0 2006.173.08:01:41.61#ibcon#about to read 6, iclass 7, count 0 2006.173.08:01:41.61#ibcon#read 6, iclass 7, count 0 2006.173.08:01:41.61#ibcon#end of sib2, iclass 7, count 0 2006.173.08:01:41.61#ibcon#*after write, iclass 7, count 0 2006.173.08:01:41.61#ibcon#*before return 0, iclass 7, count 0 2006.173.08:01:41.61#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.08:01:41.61#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.08:01:41.61#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.08:01:41.61#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.08:01:41.61$vck44/vbbw=wide 2006.173.08:01:41.61#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.08:01:41.61#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.08:01:41.61#ibcon#ireg 8 cls_cnt 0 2006.173.08:01:41.61#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.08:01:41.68#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.08:01:41.68#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.08:01:41.68#ibcon#enter wrdev, iclass 11, count 0 2006.173.08:01:41.68#ibcon#first serial, iclass 11, count 0 2006.173.08:01:41.68#ibcon#enter sib2, iclass 11, count 0 2006.173.08:01:41.68#ibcon#flushed, iclass 11, count 0 2006.173.08:01:41.68#ibcon#about to write, iclass 11, count 0 2006.173.08:01:41.68#ibcon#wrote, iclass 11, count 0 2006.173.08:01:41.68#ibcon#about to read 3, iclass 11, count 0 2006.173.08:01:41.70#ibcon#read 3, iclass 11, count 0 2006.173.08:01:41.70#ibcon#about to read 4, iclass 11, count 0 2006.173.08:01:41.70#ibcon#read 4, iclass 11, count 0 2006.173.08:01:41.70#ibcon#about to read 5, iclass 11, count 0 2006.173.08:01:41.70#ibcon#read 5, iclass 11, count 0 2006.173.08:01:41.70#ibcon#about to read 6, iclass 11, count 0 2006.173.08:01:41.70#ibcon#read 6, iclass 11, count 0 2006.173.08:01:41.70#ibcon#end of sib2, iclass 11, count 0 2006.173.08:01:41.70#ibcon#*mode == 0, iclass 11, count 0 2006.173.08:01:41.70#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.08:01:41.70#ibcon#[27=BW32\r\n] 2006.173.08:01:41.70#ibcon#*before write, iclass 11, count 0 2006.173.08:01:41.70#ibcon#enter sib2, iclass 11, count 0 2006.173.08:01:41.70#ibcon#flushed, iclass 11, count 0 2006.173.08:01:41.70#ibcon#about to write, iclass 11, count 0 2006.173.08:01:41.70#ibcon#wrote, iclass 11, count 0 2006.173.08:01:41.70#ibcon#about to read 3, iclass 11, count 0 2006.173.08:01:41.73#ibcon#read 3, iclass 11, count 0 2006.173.08:01:41.73#ibcon#about to read 4, iclass 11, count 0 2006.173.08:01:41.73#ibcon#read 4, iclass 11, count 0 2006.173.08:01:41.73#ibcon#about to read 5, iclass 11, count 0 2006.173.08:01:41.73#ibcon#read 5, iclass 11, count 0 2006.173.08:01:41.73#ibcon#about to read 6, iclass 11, count 0 2006.173.08:01:41.73#ibcon#read 6, iclass 11, count 0 2006.173.08:01:41.73#ibcon#end of sib2, iclass 11, count 0 2006.173.08:01:41.73#ibcon#*after write, iclass 11, count 0 2006.173.08:01:41.73#ibcon#*before return 0, iclass 11, count 0 2006.173.08:01:41.73#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.08:01:41.73#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.08:01:41.73#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.08:01:41.73#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.08:01:41.73$setupk4/ifdk4 2006.173.08:01:41.73$ifdk4/lo= 2006.173.08:01:41.73$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.08:01:41.73$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.08:01:41.73$ifdk4/patch= 2006.173.08:01:41.73$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.08:01:41.73$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.08:01:41.73$setupk4/!*+20s 2006.173.08:01:47.43#abcon#<5=/03 0.8 1.3 23.55 831004.1\r\n> 2006.173.08:01:47.45#abcon#{5=INTERFACE CLEAR} 2006.173.08:01:47.51#abcon#[5=S1D000X0/0*\r\n] 2006.173.08:01:56.25$setupk4/"tpicd 2006.173.08:01:56.25$setupk4/echo=off 2006.173.08:01:56.25$setupk4/xlog=off 2006.173.08:01:56.25:!2006.173.08:03:29 2006.173.08:02:12.13#trakl#Source acquired 2006.173.08:02:14.13#flagr#flagr/antenna,acquired 2006.173.08:03:29.00:preob 2006.173.08:03:30.14/onsource/TRACKING 2006.173.08:03:30.14:!2006.173.08:03:39 2006.173.08:03:39.00:"tape 2006.173.08:03:39.00:"st=record 2006.173.08:03:39.00:data_valid=on 2006.173.08:03:39.00:midob 2006.173.08:03:39.14/onsource/TRACKING 2006.173.08:03:39.14/wx/23.54,1004.1,81 2006.173.08:03:39.21/cable/+6.5018E-03 2006.173.08:03:40.30/va/01,07,usb,yes,45,48 2006.173.08:03:40.30/va/02,06,usb,yes,45,45 2006.173.08:03:40.30/va/03,05,usb,yes,56,58 2006.173.08:03:40.30/va/04,06,usb,yes,46,48 2006.173.08:03:40.30/va/05,04,usb,yes,36,37 2006.173.08:03:40.30/va/06,03,usb,yes,50,50 2006.173.08:03:40.30/va/07,04,usb,yes,41,42 2006.173.08:03:40.30/va/08,04,usb,yes,35,42 2006.173.08:03:40.53/valo/01,524.99,yes,locked 2006.173.08:03:40.53/valo/02,534.99,yes,locked 2006.173.08:03:40.53/valo/03,564.99,yes,locked 2006.173.08:03:40.53/valo/04,624.99,yes,locked 2006.173.08:03:40.53/valo/05,734.99,yes,locked 2006.173.08:03:40.53/valo/06,814.99,yes,locked 2006.173.08:03:40.53/valo/07,864.99,yes,locked 2006.173.08:03:40.53/valo/08,884.99,yes,locked 2006.173.08:03:41.62/vb/01,04,usb,yes,34,31 2006.173.08:03:41.62/vb/02,04,usb,yes,36,36 2006.173.08:03:41.62/vb/03,04,usb,yes,33,36 2006.173.08:03:41.62/vb/04,04,usb,yes,38,37 2006.173.08:03:41.62/vb/05,04,usb,yes,30,32 2006.173.08:03:41.62/vb/06,04,usb,yes,35,31 2006.173.08:03:41.62/vb/07,04,usb,yes,35,34 2006.173.08:03:41.62/vb/08,04,usb,yes,32,35 2006.173.08:03:41.85/vblo/01,629.99,yes,locked 2006.173.08:03:41.85/vblo/02,634.99,yes,locked 2006.173.08:03:41.85/vblo/03,649.99,yes,locked 2006.173.08:03:41.85/vblo/04,679.99,yes,locked 2006.173.08:03:41.85/vblo/05,709.99,yes,locked 2006.173.08:03:41.85/vblo/06,719.99,yes,locked 2006.173.08:03:41.85/vblo/07,734.99,yes,locked 2006.173.08:03:41.85/vblo/08,744.99,yes,locked 2006.173.08:03:42.00/vabw/8 2006.173.08:03:42.15/vbbw/8 2006.173.08:03:42.24/xfe/off,on,14.5 2006.173.08:03:42.63/ifatt/23,28,28,28 2006.173.08:03:43.07/fmout-gps/S +3.91E-07 2006.173.08:03:43.11:!2006.173.08:09:49 2006.173.08:09:49.00:data_valid=off 2006.173.08:09:49.00:"et 2006.173.08:09:49.00:!+3s 2006.173.08:09:52.01:"tape 2006.173.08:09:52.01:postob 2006.173.08:09:52.13/cable/+6.5023E-03 2006.173.08:09:52.13/wx/23.56,1004.2,83 2006.173.08:09:53.08/fmout-gps/S +3.91E-07 2006.173.08:09:53.08:scan_name=173-0811,jd0606,80 2006.173.08:09:53.08:source=0727-115,073019.11,-114112.6,2000.0,ccw 2006.173.08:09:54.13#flagr#flagr/antenna,new-source 2006.173.08:09:54.13:checkk5 2006.173.08:09:54.55/chk_autoobs//k5ts1/ autoobs is running! 2006.173.08:09:54.96/chk_autoobs//k5ts2/ autoobs is running! 2006.173.08:09:55.38/chk_autoobs//k5ts3/ autoobs is running! 2006.173.08:09:55.78/chk_autoobs//k5ts4/ autoobs is running! 2006.173.08:09:56.16/chk_obsdata//k5ts1/T1730803??a.dat file size is correct (nominal:1480MB, actual:1476MB). 2006.173.08:09:56.57/chk_obsdata//k5ts2/T1730803??b.dat file size is correct (nominal:1480MB, actual:1476MB). 2006.173.08:09:56.98/chk_obsdata//k5ts3/T1730803??c.dat file size is correct (nominal:1480MB, actual:1476MB). 2006.173.08:09:57.39/chk_obsdata//k5ts4/T1730803??d.dat file size is correct (nominal:1480MB, actual:1476MB). 2006.173.08:09:58.13/k5log//k5ts1_log_newline 2006.173.08:09:58.84/k5log//k5ts2_log_newline 2006.173.08:09:59.56/k5log//k5ts3_log_newline 2006.173.08:10:00.27/k5log//k5ts4_log_newline 2006.173.08:10:00.29/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.08:10:00.29:setupk4=1 2006.173.08:10:00.29$setupk4/echo=on 2006.173.08:10:00.29$setupk4/pcalon 2006.173.08:10:00.29$pcalon/"no phase cal control is implemented here 2006.173.08:10:00.29$setupk4/"tpicd=stop 2006.173.08:10:00.29$setupk4/"rec=synch_on 2006.173.08:10:00.29$setupk4/"rec_mode=128 2006.173.08:10:00.29$setupk4/!* 2006.173.08:10:00.29$setupk4/recpk4 2006.173.08:10:00.29$recpk4/recpatch= 2006.173.08:10:00.29$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.08:10:00.29$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.08:10:00.29$setupk4/vck44 2006.173.08:10:00.29$vck44/valo=1,524.99 2006.173.08:10:00.29#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.08:10:00.29#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.08:10:00.29#ibcon#ireg 17 cls_cnt 0 2006.173.08:10:00.29#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.08:10:00.29#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.08:10:00.29#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.08:10:00.29#ibcon#enter wrdev, iclass 32, count 0 2006.173.08:10:00.29#ibcon#first serial, iclass 32, count 0 2006.173.08:10:00.29#ibcon#enter sib2, iclass 32, count 0 2006.173.08:10:00.29#ibcon#flushed, iclass 32, count 0 2006.173.08:10:00.30#ibcon#about to write, iclass 32, count 0 2006.173.08:10:00.30#ibcon#wrote, iclass 32, count 0 2006.173.08:10:00.30#ibcon#about to read 3, iclass 32, count 0 2006.173.08:10:00.31#ibcon#read 3, iclass 32, count 0 2006.173.08:10:00.31#ibcon#about to read 4, iclass 32, count 0 2006.173.08:10:00.31#ibcon#read 4, iclass 32, count 0 2006.173.08:10:00.31#ibcon#about to read 5, iclass 32, count 0 2006.173.08:10:00.31#ibcon#read 5, iclass 32, count 0 2006.173.08:10:00.31#ibcon#about to read 6, iclass 32, count 0 2006.173.08:10:00.31#ibcon#read 6, iclass 32, count 0 2006.173.08:10:00.31#ibcon#end of sib2, iclass 32, count 0 2006.173.08:10:00.31#ibcon#*mode == 0, iclass 32, count 0 2006.173.08:10:00.31#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.08:10:00.31#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.08:10:00.31#ibcon#*before write, iclass 32, count 0 2006.173.08:10:00.31#ibcon#enter sib2, iclass 32, count 0 2006.173.08:10:00.31#ibcon#flushed, iclass 32, count 0 2006.173.08:10:00.31#ibcon#about to write, iclass 32, count 0 2006.173.08:10:00.31#ibcon#wrote, iclass 32, count 0 2006.173.08:10:00.31#ibcon#about to read 3, iclass 32, count 0 2006.173.08:10:00.36#ibcon#read 3, iclass 32, count 0 2006.173.08:10:00.36#ibcon#about to read 4, iclass 32, count 0 2006.173.08:10:00.36#ibcon#read 4, iclass 32, count 0 2006.173.08:10:00.36#ibcon#about to read 5, iclass 32, count 0 2006.173.08:10:00.36#ibcon#read 5, iclass 32, count 0 2006.173.08:10:00.36#ibcon#about to read 6, iclass 32, count 0 2006.173.08:10:00.36#ibcon#read 6, iclass 32, count 0 2006.173.08:10:00.36#ibcon#end of sib2, iclass 32, count 0 2006.173.08:10:00.36#ibcon#*after write, iclass 32, count 0 2006.173.08:10:00.36#ibcon#*before return 0, iclass 32, count 0 2006.173.08:10:00.36#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.08:10:00.36#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.08:10:00.36#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.08:10:00.36#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.08:10:00.36$vck44/va=1,7 2006.173.08:10:00.36#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.08:10:00.36#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.08:10:00.36#ibcon#ireg 11 cls_cnt 2 2006.173.08:10:00.36#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.08:10:00.36#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.08:10:00.36#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.08:10:00.36#ibcon#enter wrdev, iclass 34, count 2 2006.173.08:10:00.36#ibcon#first serial, iclass 34, count 2 2006.173.08:10:00.36#ibcon#enter sib2, iclass 34, count 2 2006.173.08:10:00.36#ibcon#flushed, iclass 34, count 2 2006.173.08:10:00.36#ibcon#about to write, iclass 34, count 2 2006.173.08:10:00.36#ibcon#wrote, iclass 34, count 2 2006.173.08:10:00.36#ibcon#about to read 3, iclass 34, count 2 2006.173.08:10:00.38#ibcon#read 3, iclass 34, count 2 2006.173.08:10:00.38#ibcon#about to read 4, iclass 34, count 2 2006.173.08:10:00.38#ibcon#read 4, iclass 34, count 2 2006.173.08:10:00.38#ibcon#about to read 5, iclass 34, count 2 2006.173.08:10:00.38#ibcon#read 5, iclass 34, count 2 2006.173.08:10:00.38#ibcon#about to read 6, iclass 34, count 2 2006.173.08:10:00.38#ibcon#read 6, iclass 34, count 2 2006.173.08:10:00.38#ibcon#end of sib2, iclass 34, count 2 2006.173.08:10:00.38#ibcon#*mode == 0, iclass 34, count 2 2006.173.08:10:00.38#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.08:10:00.38#ibcon#[25=AT01-07\r\n] 2006.173.08:10:00.38#ibcon#*before write, iclass 34, count 2 2006.173.08:10:00.38#ibcon#enter sib2, iclass 34, count 2 2006.173.08:10:00.38#ibcon#flushed, iclass 34, count 2 2006.173.08:10:00.38#ibcon#about to write, iclass 34, count 2 2006.173.08:10:00.38#ibcon#wrote, iclass 34, count 2 2006.173.08:10:00.38#ibcon#about to read 3, iclass 34, count 2 2006.173.08:10:00.41#ibcon#read 3, iclass 34, count 2 2006.173.08:10:00.41#ibcon#about to read 4, iclass 34, count 2 2006.173.08:10:00.41#ibcon#read 4, iclass 34, count 2 2006.173.08:10:00.41#ibcon#about to read 5, iclass 34, count 2 2006.173.08:10:00.41#ibcon#read 5, iclass 34, count 2 2006.173.08:10:00.41#ibcon#about to read 6, iclass 34, count 2 2006.173.08:10:00.41#ibcon#read 6, iclass 34, count 2 2006.173.08:10:00.41#ibcon#end of sib2, iclass 34, count 2 2006.173.08:10:00.41#ibcon#*after write, iclass 34, count 2 2006.173.08:10:00.41#ibcon#*before return 0, iclass 34, count 2 2006.173.08:10:00.41#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.08:10:00.41#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.08:10:00.41#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.08:10:00.41#ibcon#ireg 7 cls_cnt 0 2006.173.08:10:00.41#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.08:10:00.53#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.08:10:00.53#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.08:10:00.53#ibcon#enter wrdev, iclass 34, count 0 2006.173.08:10:00.53#ibcon#first serial, iclass 34, count 0 2006.173.08:10:00.53#ibcon#enter sib2, iclass 34, count 0 2006.173.08:10:00.53#ibcon#flushed, iclass 34, count 0 2006.173.08:10:00.53#ibcon#about to write, iclass 34, count 0 2006.173.08:10:00.53#ibcon#wrote, iclass 34, count 0 2006.173.08:10:00.53#ibcon#about to read 3, iclass 34, count 0 2006.173.08:10:00.55#ibcon#read 3, iclass 34, count 0 2006.173.08:10:00.55#ibcon#about to read 4, iclass 34, count 0 2006.173.08:10:00.55#ibcon#read 4, iclass 34, count 0 2006.173.08:10:00.55#ibcon#about to read 5, iclass 34, count 0 2006.173.08:10:00.55#ibcon#read 5, iclass 34, count 0 2006.173.08:10:00.55#ibcon#about to read 6, iclass 34, count 0 2006.173.08:10:00.55#ibcon#read 6, iclass 34, count 0 2006.173.08:10:00.55#ibcon#end of sib2, iclass 34, count 0 2006.173.08:10:00.55#ibcon#*mode == 0, iclass 34, count 0 2006.173.08:10:00.55#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.08:10:00.55#ibcon#[25=USB\r\n] 2006.173.08:10:00.55#ibcon#*before write, iclass 34, count 0 2006.173.08:10:00.55#ibcon#enter sib2, iclass 34, count 0 2006.173.08:10:00.55#ibcon#flushed, iclass 34, count 0 2006.173.08:10:00.55#ibcon#about to write, iclass 34, count 0 2006.173.08:10:00.55#ibcon#wrote, iclass 34, count 0 2006.173.08:10:00.55#ibcon#about to read 3, iclass 34, count 0 2006.173.08:10:00.58#ibcon#read 3, iclass 34, count 0 2006.173.08:10:00.58#ibcon#about to read 4, iclass 34, count 0 2006.173.08:10:00.58#ibcon#read 4, iclass 34, count 0 2006.173.08:10:00.58#ibcon#about to read 5, iclass 34, count 0 2006.173.08:10:00.58#ibcon#read 5, iclass 34, count 0 2006.173.08:10:00.58#ibcon#about to read 6, iclass 34, count 0 2006.173.08:10:00.58#ibcon#read 6, iclass 34, count 0 2006.173.08:10:00.58#ibcon#end of sib2, iclass 34, count 0 2006.173.08:10:00.58#ibcon#*after write, iclass 34, count 0 2006.173.08:10:00.58#ibcon#*before return 0, iclass 34, count 0 2006.173.08:10:00.58#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.08:10:00.58#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.08:10:00.58#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.08:10:00.58#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.08:10:00.58$vck44/valo=2,534.99 2006.173.08:10:00.58#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.08:10:00.58#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.08:10:00.58#ibcon#ireg 17 cls_cnt 0 2006.173.08:10:00.58#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.08:10:00.58#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.08:10:00.58#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.08:10:00.58#ibcon#enter wrdev, iclass 36, count 0 2006.173.08:10:00.58#ibcon#first serial, iclass 36, count 0 2006.173.08:10:00.58#ibcon#enter sib2, iclass 36, count 0 2006.173.08:10:00.58#ibcon#flushed, iclass 36, count 0 2006.173.08:10:00.58#ibcon#about to write, iclass 36, count 0 2006.173.08:10:00.58#ibcon#wrote, iclass 36, count 0 2006.173.08:10:00.58#ibcon#about to read 3, iclass 36, count 0 2006.173.08:10:00.60#ibcon#read 3, iclass 36, count 0 2006.173.08:10:00.60#ibcon#about to read 4, iclass 36, count 0 2006.173.08:10:00.60#ibcon#read 4, iclass 36, count 0 2006.173.08:10:00.60#ibcon#about to read 5, iclass 36, count 0 2006.173.08:10:00.60#ibcon#read 5, iclass 36, count 0 2006.173.08:10:00.60#ibcon#about to read 6, iclass 36, count 0 2006.173.08:10:00.60#ibcon#read 6, iclass 36, count 0 2006.173.08:10:00.60#ibcon#end of sib2, iclass 36, count 0 2006.173.08:10:00.60#ibcon#*mode == 0, iclass 36, count 0 2006.173.08:10:00.60#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.08:10:00.60#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.08:10:00.60#ibcon#*before write, iclass 36, count 0 2006.173.08:10:00.60#ibcon#enter sib2, iclass 36, count 0 2006.173.08:10:00.60#ibcon#flushed, iclass 36, count 0 2006.173.08:10:00.60#ibcon#about to write, iclass 36, count 0 2006.173.08:10:00.60#ibcon#wrote, iclass 36, count 0 2006.173.08:10:00.60#ibcon#about to read 3, iclass 36, count 0 2006.173.08:10:00.64#ibcon#read 3, iclass 36, count 0 2006.173.08:10:00.64#ibcon#about to read 4, iclass 36, count 0 2006.173.08:10:00.64#ibcon#read 4, iclass 36, count 0 2006.173.08:10:00.64#ibcon#about to read 5, iclass 36, count 0 2006.173.08:10:00.64#ibcon#read 5, iclass 36, count 0 2006.173.08:10:00.64#ibcon#about to read 6, iclass 36, count 0 2006.173.08:10:00.64#ibcon#read 6, iclass 36, count 0 2006.173.08:10:00.64#ibcon#end of sib2, iclass 36, count 0 2006.173.08:10:00.64#ibcon#*after write, iclass 36, count 0 2006.173.08:10:00.64#ibcon#*before return 0, iclass 36, count 0 2006.173.08:10:00.64#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.08:10:00.64#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.08:10:00.64#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.08:10:00.64#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.08:10:00.64$vck44/va=2,6 2006.173.08:10:00.64#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.08:10:00.64#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.08:10:00.64#ibcon#ireg 11 cls_cnt 2 2006.173.08:10:00.64#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.08:10:00.70#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.08:10:00.70#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.08:10:00.70#ibcon#enter wrdev, iclass 38, count 2 2006.173.08:10:00.70#ibcon#first serial, iclass 38, count 2 2006.173.08:10:00.70#ibcon#enter sib2, iclass 38, count 2 2006.173.08:10:00.70#ibcon#flushed, iclass 38, count 2 2006.173.08:10:00.70#ibcon#about to write, iclass 38, count 2 2006.173.08:10:00.70#ibcon#wrote, iclass 38, count 2 2006.173.08:10:00.70#ibcon#about to read 3, iclass 38, count 2 2006.173.08:10:00.72#ibcon#read 3, iclass 38, count 2 2006.173.08:10:00.72#ibcon#about to read 4, iclass 38, count 2 2006.173.08:10:00.72#ibcon#read 4, iclass 38, count 2 2006.173.08:10:00.72#ibcon#about to read 5, iclass 38, count 2 2006.173.08:10:00.72#ibcon#read 5, iclass 38, count 2 2006.173.08:10:00.72#ibcon#about to read 6, iclass 38, count 2 2006.173.08:10:00.72#ibcon#read 6, iclass 38, count 2 2006.173.08:10:00.72#ibcon#end of sib2, iclass 38, count 2 2006.173.08:10:00.72#ibcon#*mode == 0, iclass 38, count 2 2006.173.08:10:00.72#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.08:10:00.72#ibcon#[25=AT02-06\r\n] 2006.173.08:10:00.72#ibcon#*before write, iclass 38, count 2 2006.173.08:10:00.72#ibcon#enter sib2, iclass 38, count 2 2006.173.08:10:00.72#ibcon#flushed, iclass 38, count 2 2006.173.08:10:00.72#ibcon#about to write, iclass 38, count 2 2006.173.08:10:00.72#ibcon#wrote, iclass 38, count 2 2006.173.08:10:00.72#ibcon#about to read 3, iclass 38, count 2 2006.173.08:10:00.75#ibcon#read 3, iclass 38, count 2 2006.173.08:10:00.75#ibcon#about to read 4, iclass 38, count 2 2006.173.08:10:00.75#ibcon#read 4, iclass 38, count 2 2006.173.08:10:00.75#ibcon#about to read 5, iclass 38, count 2 2006.173.08:10:00.75#ibcon#read 5, iclass 38, count 2 2006.173.08:10:00.75#ibcon#about to read 6, iclass 38, count 2 2006.173.08:10:00.75#ibcon#read 6, iclass 38, count 2 2006.173.08:10:00.75#ibcon#end of sib2, iclass 38, count 2 2006.173.08:10:00.75#ibcon#*after write, iclass 38, count 2 2006.173.08:10:00.75#ibcon#*before return 0, iclass 38, count 2 2006.173.08:10:00.75#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.08:10:00.75#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.08:10:00.75#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.08:10:00.75#ibcon#ireg 7 cls_cnt 0 2006.173.08:10:00.75#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.08:10:00.87#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.08:10:00.87#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.08:10:00.87#ibcon#enter wrdev, iclass 38, count 0 2006.173.08:10:00.87#ibcon#first serial, iclass 38, count 0 2006.173.08:10:00.87#ibcon#enter sib2, iclass 38, count 0 2006.173.08:10:00.87#ibcon#flushed, iclass 38, count 0 2006.173.08:10:00.87#ibcon#about to write, iclass 38, count 0 2006.173.08:10:00.87#ibcon#wrote, iclass 38, count 0 2006.173.08:10:00.87#ibcon#about to read 3, iclass 38, count 0 2006.173.08:10:00.89#ibcon#read 3, iclass 38, count 0 2006.173.08:10:00.89#ibcon#about to read 4, iclass 38, count 0 2006.173.08:10:00.89#ibcon#read 4, iclass 38, count 0 2006.173.08:10:00.89#ibcon#about to read 5, iclass 38, count 0 2006.173.08:10:00.89#ibcon#read 5, iclass 38, count 0 2006.173.08:10:00.89#ibcon#about to read 6, iclass 38, count 0 2006.173.08:10:00.89#ibcon#read 6, iclass 38, count 0 2006.173.08:10:00.89#ibcon#end of sib2, iclass 38, count 0 2006.173.08:10:00.89#ibcon#*mode == 0, iclass 38, count 0 2006.173.08:10:00.89#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.08:10:00.89#ibcon#[25=USB\r\n] 2006.173.08:10:00.89#ibcon#*before write, iclass 38, count 0 2006.173.08:10:00.89#ibcon#enter sib2, iclass 38, count 0 2006.173.08:10:00.89#ibcon#flushed, iclass 38, count 0 2006.173.08:10:00.89#ibcon#about to write, iclass 38, count 0 2006.173.08:10:00.89#ibcon#wrote, iclass 38, count 0 2006.173.08:10:00.89#ibcon#about to read 3, iclass 38, count 0 2006.173.08:10:00.92#ibcon#read 3, iclass 38, count 0 2006.173.08:10:00.92#ibcon#about to read 4, iclass 38, count 0 2006.173.08:10:00.92#ibcon#read 4, iclass 38, count 0 2006.173.08:10:00.92#ibcon#about to read 5, iclass 38, count 0 2006.173.08:10:00.92#ibcon#read 5, iclass 38, count 0 2006.173.08:10:00.92#ibcon#about to read 6, iclass 38, count 0 2006.173.08:10:00.92#ibcon#read 6, iclass 38, count 0 2006.173.08:10:00.92#ibcon#end of sib2, iclass 38, count 0 2006.173.08:10:00.92#ibcon#*after write, iclass 38, count 0 2006.173.08:10:00.92#ibcon#*before return 0, iclass 38, count 0 2006.173.08:10:00.92#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.08:10:00.92#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.08:10:00.92#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.08:10:00.92#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.08:10:00.92$vck44/valo=3,564.99 2006.173.08:10:00.92#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.08:10:00.92#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.08:10:00.92#ibcon#ireg 17 cls_cnt 0 2006.173.08:10:00.92#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.08:10:00.92#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.08:10:00.92#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.08:10:00.92#ibcon#enter wrdev, iclass 40, count 0 2006.173.08:10:00.92#ibcon#first serial, iclass 40, count 0 2006.173.08:10:00.92#ibcon#enter sib2, iclass 40, count 0 2006.173.08:10:00.92#ibcon#flushed, iclass 40, count 0 2006.173.08:10:00.92#ibcon#about to write, iclass 40, count 0 2006.173.08:10:00.92#ibcon#wrote, iclass 40, count 0 2006.173.08:10:00.92#ibcon#about to read 3, iclass 40, count 0 2006.173.08:10:00.94#ibcon#read 3, iclass 40, count 0 2006.173.08:10:00.94#ibcon#about to read 4, iclass 40, count 0 2006.173.08:10:00.94#ibcon#read 4, iclass 40, count 0 2006.173.08:10:00.94#ibcon#about to read 5, iclass 40, count 0 2006.173.08:10:00.94#ibcon#read 5, iclass 40, count 0 2006.173.08:10:00.94#ibcon#about to read 6, iclass 40, count 0 2006.173.08:10:00.94#ibcon#read 6, iclass 40, count 0 2006.173.08:10:00.94#ibcon#end of sib2, iclass 40, count 0 2006.173.08:10:00.94#ibcon#*mode == 0, iclass 40, count 0 2006.173.08:10:00.94#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.08:10:00.94#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.08:10:00.94#ibcon#*before write, iclass 40, count 0 2006.173.08:10:00.94#ibcon#enter sib2, iclass 40, count 0 2006.173.08:10:00.94#ibcon#flushed, iclass 40, count 0 2006.173.08:10:00.94#ibcon#about to write, iclass 40, count 0 2006.173.08:10:00.94#ibcon#wrote, iclass 40, count 0 2006.173.08:10:00.94#ibcon#about to read 3, iclass 40, count 0 2006.173.08:10:00.98#ibcon#read 3, iclass 40, count 0 2006.173.08:10:00.98#ibcon#about to read 4, iclass 40, count 0 2006.173.08:10:00.98#ibcon#read 4, iclass 40, count 0 2006.173.08:10:00.98#ibcon#about to read 5, iclass 40, count 0 2006.173.08:10:00.98#ibcon#read 5, iclass 40, count 0 2006.173.08:10:00.98#ibcon#about to read 6, iclass 40, count 0 2006.173.08:10:00.98#ibcon#read 6, iclass 40, count 0 2006.173.08:10:00.98#ibcon#end of sib2, iclass 40, count 0 2006.173.08:10:00.98#ibcon#*after write, iclass 40, count 0 2006.173.08:10:00.98#ibcon#*before return 0, iclass 40, count 0 2006.173.08:10:00.98#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.08:10:00.98#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.08:10:00.98#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.08:10:00.98#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.08:10:00.98$vck44/va=3,5 2006.173.08:10:00.98#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.08:10:00.98#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.08:10:00.98#ibcon#ireg 11 cls_cnt 2 2006.173.08:10:00.98#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.08:10:01.04#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.08:10:01.04#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.08:10:01.04#ibcon#enter wrdev, iclass 4, count 2 2006.173.08:10:01.04#ibcon#first serial, iclass 4, count 2 2006.173.08:10:01.04#ibcon#enter sib2, iclass 4, count 2 2006.173.08:10:01.04#ibcon#flushed, iclass 4, count 2 2006.173.08:10:01.04#ibcon#about to write, iclass 4, count 2 2006.173.08:10:01.04#ibcon#wrote, iclass 4, count 2 2006.173.08:10:01.04#ibcon#about to read 3, iclass 4, count 2 2006.173.08:10:01.06#ibcon#read 3, iclass 4, count 2 2006.173.08:10:01.06#ibcon#about to read 4, iclass 4, count 2 2006.173.08:10:01.06#ibcon#read 4, iclass 4, count 2 2006.173.08:10:01.06#ibcon#about to read 5, iclass 4, count 2 2006.173.08:10:01.06#ibcon#read 5, iclass 4, count 2 2006.173.08:10:01.06#ibcon#about to read 6, iclass 4, count 2 2006.173.08:10:01.06#ibcon#read 6, iclass 4, count 2 2006.173.08:10:01.06#ibcon#end of sib2, iclass 4, count 2 2006.173.08:10:01.06#ibcon#*mode == 0, iclass 4, count 2 2006.173.08:10:01.06#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.08:10:01.06#ibcon#[25=AT03-05\r\n] 2006.173.08:10:01.06#ibcon#*before write, iclass 4, count 2 2006.173.08:10:01.06#ibcon#enter sib2, iclass 4, count 2 2006.173.08:10:01.06#ibcon#flushed, iclass 4, count 2 2006.173.08:10:01.06#ibcon#about to write, iclass 4, count 2 2006.173.08:10:01.06#ibcon#wrote, iclass 4, count 2 2006.173.08:10:01.06#ibcon#about to read 3, iclass 4, count 2 2006.173.08:10:01.09#ibcon#read 3, iclass 4, count 2 2006.173.08:10:01.09#ibcon#about to read 4, iclass 4, count 2 2006.173.08:10:01.09#ibcon#read 4, iclass 4, count 2 2006.173.08:10:01.09#ibcon#about to read 5, iclass 4, count 2 2006.173.08:10:01.09#ibcon#read 5, iclass 4, count 2 2006.173.08:10:01.09#ibcon#about to read 6, iclass 4, count 2 2006.173.08:10:01.09#ibcon#read 6, iclass 4, count 2 2006.173.08:10:01.09#ibcon#end of sib2, iclass 4, count 2 2006.173.08:10:01.09#ibcon#*after write, iclass 4, count 2 2006.173.08:10:01.09#ibcon#*before return 0, iclass 4, count 2 2006.173.08:10:01.09#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.08:10:01.09#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.08:10:01.09#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.08:10:01.09#ibcon#ireg 7 cls_cnt 0 2006.173.08:10:01.09#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.08:10:01.21#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.08:10:01.21#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.08:10:01.21#ibcon#enter wrdev, iclass 4, count 0 2006.173.08:10:01.21#ibcon#first serial, iclass 4, count 0 2006.173.08:10:01.21#ibcon#enter sib2, iclass 4, count 0 2006.173.08:10:01.21#ibcon#flushed, iclass 4, count 0 2006.173.08:10:01.21#ibcon#about to write, iclass 4, count 0 2006.173.08:10:01.21#ibcon#wrote, iclass 4, count 0 2006.173.08:10:01.21#ibcon#about to read 3, iclass 4, count 0 2006.173.08:10:01.23#ibcon#read 3, iclass 4, count 0 2006.173.08:10:01.23#ibcon#about to read 4, iclass 4, count 0 2006.173.08:10:01.23#ibcon#read 4, iclass 4, count 0 2006.173.08:10:01.23#ibcon#about to read 5, iclass 4, count 0 2006.173.08:10:01.23#ibcon#read 5, iclass 4, count 0 2006.173.08:10:01.23#ibcon#about to read 6, iclass 4, count 0 2006.173.08:10:01.23#ibcon#read 6, iclass 4, count 0 2006.173.08:10:01.23#ibcon#end of sib2, iclass 4, count 0 2006.173.08:10:01.23#ibcon#*mode == 0, iclass 4, count 0 2006.173.08:10:01.23#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.08:10:01.23#ibcon#[25=USB\r\n] 2006.173.08:10:01.23#ibcon#*before write, iclass 4, count 0 2006.173.08:10:01.23#ibcon#enter sib2, iclass 4, count 0 2006.173.08:10:01.23#ibcon#flushed, iclass 4, count 0 2006.173.08:10:01.23#ibcon#about to write, iclass 4, count 0 2006.173.08:10:01.23#ibcon#wrote, iclass 4, count 0 2006.173.08:10:01.23#ibcon#about to read 3, iclass 4, count 0 2006.173.08:10:01.26#ibcon#read 3, iclass 4, count 0 2006.173.08:10:01.26#ibcon#about to read 4, iclass 4, count 0 2006.173.08:10:01.26#ibcon#read 4, iclass 4, count 0 2006.173.08:10:01.26#ibcon#about to read 5, iclass 4, count 0 2006.173.08:10:01.26#ibcon#read 5, iclass 4, count 0 2006.173.08:10:01.26#ibcon#about to read 6, iclass 4, count 0 2006.173.08:10:01.26#ibcon#read 6, iclass 4, count 0 2006.173.08:10:01.26#ibcon#end of sib2, iclass 4, count 0 2006.173.08:10:01.26#ibcon#*after write, iclass 4, count 0 2006.173.08:10:01.26#ibcon#*before return 0, iclass 4, count 0 2006.173.08:10:01.26#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.08:10:01.26#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.08:10:01.26#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.08:10:01.26#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.08:10:01.26$vck44/valo=4,624.99 2006.173.08:10:01.26#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.08:10:01.26#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.08:10:01.26#ibcon#ireg 17 cls_cnt 0 2006.173.08:10:01.26#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.08:10:01.26#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.08:10:01.26#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.08:10:01.26#ibcon#enter wrdev, iclass 6, count 0 2006.173.08:10:01.26#ibcon#first serial, iclass 6, count 0 2006.173.08:10:01.26#ibcon#enter sib2, iclass 6, count 0 2006.173.08:10:01.26#ibcon#flushed, iclass 6, count 0 2006.173.08:10:01.26#ibcon#about to write, iclass 6, count 0 2006.173.08:10:01.26#ibcon#wrote, iclass 6, count 0 2006.173.08:10:01.26#ibcon#about to read 3, iclass 6, count 0 2006.173.08:10:01.28#ibcon#read 3, iclass 6, count 0 2006.173.08:10:01.28#ibcon#about to read 4, iclass 6, count 0 2006.173.08:10:01.28#ibcon#read 4, iclass 6, count 0 2006.173.08:10:01.28#ibcon#about to read 5, iclass 6, count 0 2006.173.08:10:01.28#ibcon#read 5, iclass 6, count 0 2006.173.08:10:01.28#ibcon#about to read 6, iclass 6, count 0 2006.173.08:10:01.28#ibcon#read 6, iclass 6, count 0 2006.173.08:10:01.28#ibcon#end of sib2, iclass 6, count 0 2006.173.08:10:01.28#ibcon#*mode == 0, iclass 6, count 0 2006.173.08:10:01.28#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.08:10:01.28#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.08:10:01.28#ibcon#*before write, iclass 6, count 0 2006.173.08:10:01.28#ibcon#enter sib2, iclass 6, count 0 2006.173.08:10:01.28#ibcon#flushed, iclass 6, count 0 2006.173.08:10:01.28#ibcon#about to write, iclass 6, count 0 2006.173.08:10:01.28#ibcon#wrote, iclass 6, count 0 2006.173.08:10:01.28#ibcon#about to read 3, iclass 6, count 0 2006.173.08:10:01.32#ibcon#read 3, iclass 6, count 0 2006.173.08:10:01.32#ibcon#about to read 4, iclass 6, count 0 2006.173.08:10:01.32#ibcon#read 4, iclass 6, count 0 2006.173.08:10:01.32#ibcon#about to read 5, iclass 6, count 0 2006.173.08:10:01.32#ibcon#read 5, iclass 6, count 0 2006.173.08:10:01.32#ibcon#about to read 6, iclass 6, count 0 2006.173.08:10:01.32#ibcon#read 6, iclass 6, count 0 2006.173.08:10:01.32#ibcon#end of sib2, iclass 6, count 0 2006.173.08:10:01.32#ibcon#*after write, iclass 6, count 0 2006.173.08:10:01.32#ibcon#*before return 0, iclass 6, count 0 2006.173.08:10:01.32#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.08:10:01.32#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.08:10:01.32#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.08:10:01.32#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.08:10:01.32$vck44/va=4,6 2006.173.08:10:01.32#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.08:10:01.32#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.08:10:01.32#ibcon#ireg 11 cls_cnt 2 2006.173.08:10:01.32#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.08:10:01.38#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.08:10:01.38#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.08:10:01.38#ibcon#enter wrdev, iclass 10, count 2 2006.173.08:10:01.38#ibcon#first serial, iclass 10, count 2 2006.173.08:10:01.38#ibcon#enter sib2, iclass 10, count 2 2006.173.08:10:01.38#ibcon#flushed, iclass 10, count 2 2006.173.08:10:01.38#ibcon#about to write, iclass 10, count 2 2006.173.08:10:01.38#ibcon#wrote, iclass 10, count 2 2006.173.08:10:01.38#ibcon#about to read 3, iclass 10, count 2 2006.173.08:10:01.40#ibcon#read 3, iclass 10, count 2 2006.173.08:10:01.40#ibcon#about to read 4, iclass 10, count 2 2006.173.08:10:01.40#ibcon#read 4, iclass 10, count 2 2006.173.08:10:01.40#ibcon#about to read 5, iclass 10, count 2 2006.173.08:10:01.40#ibcon#read 5, iclass 10, count 2 2006.173.08:10:01.40#ibcon#about to read 6, iclass 10, count 2 2006.173.08:10:01.40#ibcon#read 6, iclass 10, count 2 2006.173.08:10:01.40#ibcon#end of sib2, iclass 10, count 2 2006.173.08:10:01.40#ibcon#*mode == 0, iclass 10, count 2 2006.173.08:10:01.40#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.08:10:01.40#ibcon#[25=AT04-06\r\n] 2006.173.08:10:01.40#ibcon#*before write, iclass 10, count 2 2006.173.08:10:01.40#ibcon#enter sib2, iclass 10, count 2 2006.173.08:10:01.40#ibcon#flushed, iclass 10, count 2 2006.173.08:10:01.40#ibcon#about to write, iclass 10, count 2 2006.173.08:10:01.40#ibcon#wrote, iclass 10, count 2 2006.173.08:10:01.40#ibcon#about to read 3, iclass 10, count 2 2006.173.08:10:01.43#ibcon#read 3, iclass 10, count 2 2006.173.08:10:01.43#ibcon#about to read 4, iclass 10, count 2 2006.173.08:10:01.43#ibcon#read 4, iclass 10, count 2 2006.173.08:10:01.43#ibcon#about to read 5, iclass 10, count 2 2006.173.08:10:01.43#ibcon#read 5, iclass 10, count 2 2006.173.08:10:01.43#ibcon#about to read 6, iclass 10, count 2 2006.173.08:10:01.43#ibcon#read 6, iclass 10, count 2 2006.173.08:10:01.43#ibcon#end of sib2, iclass 10, count 2 2006.173.08:10:01.43#ibcon#*after write, iclass 10, count 2 2006.173.08:10:01.43#ibcon#*before return 0, iclass 10, count 2 2006.173.08:10:01.43#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.08:10:01.43#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.08:10:01.43#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.08:10:01.43#ibcon#ireg 7 cls_cnt 0 2006.173.08:10:01.43#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.08:10:01.55#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.08:10:01.55#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.08:10:01.55#ibcon#enter wrdev, iclass 10, count 0 2006.173.08:10:01.55#ibcon#first serial, iclass 10, count 0 2006.173.08:10:01.55#ibcon#enter sib2, iclass 10, count 0 2006.173.08:10:01.55#ibcon#flushed, iclass 10, count 0 2006.173.08:10:01.55#ibcon#about to write, iclass 10, count 0 2006.173.08:10:01.55#ibcon#wrote, iclass 10, count 0 2006.173.08:10:01.55#ibcon#about to read 3, iclass 10, count 0 2006.173.08:10:01.57#ibcon#read 3, iclass 10, count 0 2006.173.08:10:01.57#ibcon#about to read 4, iclass 10, count 0 2006.173.08:10:01.57#ibcon#read 4, iclass 10, count 0 2006.173.08:10:01.57#ibcon#about to read 5, iclass 10, count 0 2006.173.08:10:01.57#ibcon#read 5, iclass 10, count 0 2006.173.08:10:01.57#ibcon#about to read 6, iclass 10, count 0 2006.173.08:10:01.57#ibcon#read 6, iclass 10, count 0 2006.173.08:10:01.57#ibcon#end of sib2, iclass 10, count 0 2006.173.08:10:01.57#ibcon#*mode == 0, iclass 10, count 0 2006.173.08:10:01.57#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.08:10:01.57#ibcon#[25=USB\r\n] 2006.173.08:10:01.57#ibcon#*before write, iclass 10, count 0 2006.173.08:10:01.57#ibcon#enter sib2, iclass 10, count 0 2006.173.08:10:01.57#ibcon#flushed, iclass 10, count 0 2006.173.08:10:01.57#ibcon#about to write, iclass 10, count 0 2006.173.08:10:01.57#ibcon#wrote, iclass 10, count 0 2006.173.08:10:01.57#ibcon#about to read 3, iclass 10, count 0 2006.173.08:10:01.60#ibcon#read 3, iclass 10, count 0 2006.173.08:10:01.60#ibcon#about to read 4, iclass 10, count 0 2006.173.08:10:01.60#ibcon#read 4, iclass 10, count 0 2006.173.08:10:01.60#ibcon#about to read 5, iclass 10, count 0 2006.173.08:10:01.60#ibcon#read 5, iclass 10, count 0 2006.173.08:10:01.60#ibcon#about to read 6, iclass 10, count 0 2006.173.08:10:01.60#ibcon#read 6, iclass 10, count 0 2006.173.08:10:01.60#ibcon#end of sib2, iclass 10, count 0 2006.173.08:10:01.60#ibcon#*after write, iclass 10, count 0 2006.173.08:10:01.60#ibcon#*before return 0, iclass 10, count 0 2006.173.08:10:01.60#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.08:10:01.60#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.08:10:01.60#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.08:10:01.60#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.08:10:01.60$vck44/valo=5,734.99 2006.173.08:10:01.60#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.08:10:01.60#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.08:10:01.60#ibcon#ireg 17 cls_cnt 0 2006.173.08:10:01.60#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.08:10:01.60#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.08:10:01.60#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.08:10:01.60#ibcon#enter wrdev, iclass 12, count 0 2006.173.08:10:01.60#ibcon#first serial, iclass 12, count 0 2006.173.08:10:01.60#ibcon#enter sib2, iclass 12, count 0 2006.173.08:10:01.60#ibcon#flushed, iclass 12, count 0 2006.173.08:10:01.60#ibcon#about to write, iclass 12, count 0 2006.173.08:10:01.60#ibcon#wrote, iclass 12, count 0 2006.173.08:10:01.60#ibcon#about to read 3, iclass 12, count 0 2006.173.08:10:01.62#ibcon#read 3, iclass 12, count 0 2006.173.08:10:01.62#ibcon#about to read 4, iclass 12, count 0 2006.173.08:10:01.62#ibcon#read 4, iclass 12, count 0 2006.173.08:10:01.62#ibcon#about to read 5, iclass 12, count 0 2006.173.08:10:01.62#ibcon#read 5, iclass 12, count 0 2006.173.08:10:01.62#ibcon#about to read 6, iclass 12, count 0 2006.173.08:10:01.62#ibcon#read 6, iclass 12, count 0 2006.173.08:10:01.62#ibcon#end of sib2, iclass 12, count 0 2006.173.08:10:01.62#ibcon#*mode == 0, iclass 12, count 0 2006.173.08:10:01.62#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.08:10:01.62#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.08:10:01.62#ibcon#*before write, iclass 12, count 0 2006.173.08:10:01.62#ibcon#enter sib2, iclass 12, count 0 2006.173.08:10:01.62#ibcon#flushed, iclass 12, count 0 2006.173.08:10:01.62#ibcon#about to write, iclass 12, count 0 2006.173.08:10:01.62#ibcon#wrote, iclass 12, count 0 2006.173.08:10:01.62#ibcon#about to read 3, iclass 12, count 0 2006.173.08:10:01.66#ibcon#read 3, iclass 12, count 0 2006.173.08:10:01.66#ibcon#about to read 4, iclass 12, count 0 2006.173.08:10:01.66#ibcon#read 4, iclass 12, count 0 2006.173.08:10:01.66#ibcon#about to read 5, iclass 12, count 0 2006.173.08:10:01.66#ibcon#read 5, iclass 12, count 0 2006.173.08:10:01.66#ibcon#about to read 6, iclass 12, count 0 2006.173.08:10:01.66#ibcon#read 6, iclass 12, count 0 2006.173.08:10:01.66#ibcon#end of sib2, iclass 12, count 0 2006.173.08:10:01.66#ibcon#*after write, iclass 12, count 0 2006.173.08:10:01.66#ibcon#*before return 0, iclass 12, count 0 2006.173.08:10:01.66#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.08:10:01.66#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.08:10:01.66#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.08:10:01.66#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.08:10:01.66$vck44/va=5,4 2006.173.08:10:01.66#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.08:10:01.66#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.08:10:01.66#ibcon#ireg 11 cls_cnt 2 2006.173.08:10:01.66#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.08:10:01.72#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.08:10:01.72#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.08:10:01.72#ibcon#enter wrdev, iclass 14, count 2 2006.173.08:10:01.72#ibcon#first serial, iclass 14, count 2 2006.173.08:10:01.72#ibcon#enter sib2, iclass 14, count 2 2006.173.08:10:01.72#ibcon#flushed, iclass 14, count 2 2006.173.08:10:01.72#ibcon#about to write, iclass 14, count 2 2006.173.08:10:01.72#ibcon#wrote, iclass 14, count 2 2006.173.08:10:01.72#ibcon#about to read 3, iclass 14, count 2 2006.173.08:10:01.74#ibcon#read 3, iclass 14, count 2 2006.173.08:10:01.74#ibcon#about to read 4, iclass 14, count 2 2006.173.08:10:01.74#ibcon#read 4, iclass 14, count 2 2006.173.08:10:01.74#ibcon#about to read 5, iclass 14, count 2 2006.173.08:10:01.74#ibcon#read 5, iclass 14, count 2 2006.173.08:10:01.74#ibcon#about to read 6, iclass 14, count 2 2006.173.08:10:01.74#ibcon#read 6, iclass 14, count 2 2006.173.08:10:01.74#ibcon#end of sib2, iclass 14, count 2 2006.173.08:10:01.74#ibcon#*mode == 0, iclass 14, count 2 2006.173.08:10:01.74#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.08:10:01.74#ibcon#[25=AT05-04\r\n] 2006.173.08:10:01.74#ibcon#*before write, iclass 14, count 2 2006.173.08:10:01.74#ibcon#enter sib2, iclass 14, count 2 2006.173.08:10:01.74#ibcon#flushed, iclass 14, count 2 2006.173.08:10:01.74#ibcon#about to write, iclass 14, count 2 2006.173.08:10:01.74#ibcon#wrote, iclass 14, count 2 2006.173.08:10:01.74#ibcon#about to read 3, iclass 14, count 2 2006.173.08:10:01.77#ibcon#read 3, iclass 14, count 2 2006.173.08:10:01.77#ibcon#about to read 4, iclass 14, count 2 2006.173.08:10:01.77#ibcon#read 4, iclass 14, count 2 2006.173.08:10:01.77#ibcon#about to read 5, iclass 14, count 2 2006.173.08:10:01.77#ibcon#read 5, iclass 14, count 2 2006.173.08:10:01.77#ibcon#about to read 6, iclass 14, count 2 2006.173.08:10:01.77#ibcon#read 6, iclass 14, count 2 2006.173.08:10:01.77#ibcon#end of sib2, iclass 14, count 2 2006.173.08:10:01.77#ibcon#*after write, iclass 14, count 2 2006.173.08:10:01.77#ibcon#*before return 0, iclass 14, count 2 2006.173.08:10:01.77#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.08:10:01.77#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.08:10:01.77#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.08:10:01.77#ibcon#ireg 7 cls_cnt 0 2006.173.08:10:01.77#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.08:10:01.89#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.08:10:01.89#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.08:10:01.89#ibcon#enter wrdev, iclass 14, count 0 2006.173.08:10:01.89#ibcon#first serial, iclass 14, count 0 2006.173.08:10:01.89#ibcon#enter sib2, iclass 14, count 0 2006.173.08:10:01.89#ibcon#flushed, iclass 14, count 0 2006.173.08:10:01.89#ibcon#about to write, iclass 14, count 0 2006.173.08:10:01.89#ibcon#wrote, iclass 14, count 0 2006.173.08:10:01.89#ibcon#about to read 3, iclass 14, count 0 2006.173.08:10:01.91#ibcon#read 3, iclass 14, count 0 2006.173.08:10:01.91#ibcon#about to read 4, iclass 14, count 0 2006.173.08:10:01.91#ibcon#read 4, iclass 14, count 0 2006.173.08:10:01.91#ibcon#about to read 5, iclass 14, count 0 2006.173.08:10:01.91#ibcon#read 5, iclass 14, count 0 2006.173.08:10:01.91#ibcon#about to read 6, iclass 14, count 0 2006.173.08:10:01.91#ibcon#read 6, iclass 14, count 0 2006.173.08:10:01.91#ibcon#end of sib2, iclass 14, count 0 2006.173.08:10:01.91#ibcon#*mode == 0, iclass 14, count 0 2006.173.08:10:01.91#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.08:10:01.91#ibcon#[25=USB\r\n] 2006.173.08:10:01.91#ibcon#*before write, iclass 14, count 0 2006.173.08:10:01.91#ibcon#enter sib2, iclass 14, count 0 2006.173.08:10:01.91#ibcon#flushed, iclass 14, count 0 2006.173.08:10:01.91#ibcon#about to write, iclass 14, count 0 2006.173.08:10:01.91#ibcon#wrote, iclass 14, count 0 2006.173.08:10:01.91#ibcon#about to read 3, iclass 14, count 0 2006.173.08:10:01.94#ibcon#read 3, iclass 14, count 0 2006.173.08:10:01.94#ibcon#about to read 4, iclass 14, count 0 2006.173.08:10:01.94#ibcon#read 4, iclass 14, count 0 2006.173.08:10:01.94#ibcon#about to read 5, iclass 14, count 0 2006.173.08:10:01.94#ibcon#read 5, iclass 14, count 0 2006.173.08:10:01.94#ibcon#about to read 6, iclass 14, count 0 2006.173.08:10:01.94#ibcon#read 6, iclass 14, count 0 2006.173.08:10:01.94#ibcon#end of sib2, iclass 14, count 0 2006.173.08:10:01.94#ibcon#*after write, iclass 14, count 0 2006.173.08:10:01.94#ibcon#*before return 0, iclass 14, count 0 2006.173.08:10:01.94#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.08:10:01.94#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.08:10:01.94#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.08:10:01.94#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.08:10:01.94$vck44/valo=6,814.99 2006.173.08:10:01.94#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.08:10:01.94#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.08:10:01.94#ibcon#ireg 17 cls_cnt 0 2006.173.08:10:01.94#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.08:10:01.94#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.08:10:01.94#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.08:10:01.94#ibcon#enter wrdev, iclass 16, count 0 2006.173.08:10:01.94#ibcon#first serial, iclass 16, count 0 2006.173.08:10:01.94#ibcon#enter sib2, iclass 16, count 0 2006.173.08:10:01.94#ibcon#flushed, iclass 16, count 0 2006.173.08:10:01.94#ibcon#about to write, iclass 16, count 0 2006.173.08:10:01.94#ibcon#wrote, iclass 16, count 0 2006.173.08:10:01.94#ibcon#about to read 3, iclass 16, count 0 2006.173.08:10:01.96#ibcon#read 3, iclass 16, count 0 2006.173.08:10:01.96#ibcon#about to read 4, iclass 16, count 0 2006.173.08:10:01.96#ibcon#read 4, iclass 16, count 0 2006.173.08:10:01.96#ibcon#about to read 5, iclass 16, count 0 2006.173.08:10:01.96#ibcon#read 5, iclass 16, count 0 2006.173.08:10:01.96#ibcon#about to read 6, iclass 16, count 0 2006.173.08:10:01.96#ibcon#read 6, iclass 16, count 0 2006.173.08:10:01.96#ibcon#end of sib2, iclass 16, count 0 2006.173.08:10:01.96#ibcon#*mode == 0, iclass 16, count 0 2006.173.08:10:01.96#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.08:10:01.96#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.08:10:01.96#ibcon#*before write, iclass 16, count 0 2006.173.08:10:01.96#ibcon#enter sib2, iclass 16, count 0 2006.173.08:10:01.96#ibcon#flushed, iclass 16, count 0 2006.173.08:10:01.96#ibcon#about to write, iclass 16, count 0 2006.173.08:10:01.96#ibcon#wrote, iclass 16, count 0 2006.173.08:10:01.96#ibcon#about to read 3, iclass 16, count 0 2006.173.08:10:02.00#ibcon#read 3, iclass 16, count 0 2006.173.08:10:02.00#ibcon#about to read 4, iclass 16, count 0 2006.173.08:10:02.00#ibcon#read 4, iclass 16, count 0 2006.173.08:10:02.00#ibcon#about to read 5, iclass 16, count 0 2006.173.08:10:02.00#ibcon#read 5, iclass 16, count 0 2006.173.08:10:02.00#ibcon#about to read 6, iclass 16, count 0 2006.173.08:10:02.00#ibcon#read 6, iclass 16, count 0 2006.173.08:10:02.00#ibcon#end of sib2, iclass 16, count 0 2006.173.08:10:02.00#ibcon#*after write, iclass 16, count 0 2006.173.08:10:02.00#ibcon#*before return 0, iclass 16, count 0 2006.173.08:10:02.00#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.08:10:02.00#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.08:10:02.00#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.08:10:02.00#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.08:10:02.00$vck44/va=6,3 2006.173.08:10:02.00#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.08:10:02.00#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.08:10:02.00#ibcon#ireg 11 cls_cnt 2 2006.173.08:10:02.00#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.08:10:02.06#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.08:10:02.06#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.08:10:02.06#ibcon#enter wrdev, iclass 18, count 2 2006.173.08:10:02.06#ibcon#first serial, iclass 18, count 2 2006.173.08:10:02.06#ibcon#enter sib2, iclass 18, count 2 2006.173.08:10:02.06#ibcon#flushed, iclass 18, count 2 2006.173.08:10:02.06#ibcon#about to write, iclass 18, count 2 2006.173.08:10:02.06#ibcon#wrote, iclass 18, count 2 2006.173.08:10:02.06#ibcon#about to read 3, iclass 18, count 2 2006.173.08:10:02.08#ibcon#read 3, iclass 18, count 2 2006.173.08:10:02.08#ibcon#about to read 4, iclass 18, count 2 2006.173.08:10:02.08#ibcon#read 4, iclass 18, count 2 2006.173.08:10:02.08#ibcon#about to read 5, iclass 18, count 2 2006.173.08:10:02.08#ibcon#read 5, iclass 18, count 2 2006.173.08:10:02.08#ibcon#about to read 6, iclass 18, count 2 2006.173.08:10:02.08#ibcon#read 6, iclass 18, count 2 2006.173.08:10:02.08#ibcon#end of sib2, iclass 18, count 2 2006.173.08:10:02.08#ibcon#*mode == 0, iclass 18, count 2 2006.173.08:10:02.08#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.08:10:02.08#ibcon#[25=AT06-03\r\n] 2006.173.08:10:02.08#ibcon#*before write, iclass 18, count 2 2006.173.08:10:02.08#ibcon#enter sib2, iclass 18, count 2 2006.173.08:10:02.08#ibcon#flushed, iclass 18, count 2 2006.173.08:10:02.08#ibcon#about to write, iclass 18, count 2 2006.173.08:10:02.08#ibcon#wrote, iclass 18, count 2 2006.173.08:10:02.08#ibcon#about to read 3, iclass 18, count 2 2006.173.08:10:02.11#ibcon#read 3, iclass 18, count 2 2006.173.08:10:02.11#ibcon#about to read 4, iclass 18, count 2 2006.173.08:10:02.11#ibcon#read 4, iclass 18, count 2 2006.173.08:10:02.11#ibcon#about to read 5, iclass 18, count 2 2006.173.08:10:02.11#ibcon#read 5, iclass 18, count 2 2006.173.08:10:02.11#ibcon#about to read 6, iclass 18, count 2 2006.173.08:10:02.11#ibcon#read 6, iclass 18, count 2 2006.173.08:10:02.11#ibcon#end of sib2, iclass 18, count 2 2006.173.08:10:02.11#ibcon#*after write, iclass 18, count 2 2006.173.08:10:02.11#ibcon#*before return 0, iclass 18, count 2 2006.173.08:10:02.11#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.08:10:02.11#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.08:10:02.11#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.08:10:02.11#ibcon#ireg 7 cls_cnt 0 2006.173.08:10:02.11#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.08:10:02.23#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.08:10:02.23#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.08:10:02.23#ibcon#enter wrdev, iclass 18, count 0 2006.173.08:10:02.23#ibcon#first serial, iclass 18, count 0 2006.173.08:10:02.23#ibcon#enter sib2, iclass 18, count 0 2006.173.08:10:02.23#ibcon#flushed, iclass 18, count 0 2006.173.08:10:02.23#ibcon#about to write, iclass 18, count 0 2006.173.08:10:02.23#ibcon#wrote, iclass 18, count 0 2006.173.08:10:02.23#ibcon#about to read 3, iclass 18, count 0 2006.173.08:10:02.25#ibcon#read 3, iclass 18, count 0 2006.173.08:10:02.25#ibcon#about to read 4, iclass 18, count 0 2006.173.08:10:02.25#ibcon#read 4, iclass 18, count 0 2006.173.08:10:02.25#ibcon#about to read 5, iclass 18, count 0 2006.173.08:10:02.25#ibcon#read 5, iclass 18, count 0 2006.173.08:10:02.25#ibcon#about to read 6, iclass 18, count 0 2006.173.08:10:02.25#ibcon#read 6, iclass 18, count 0 2006.173.08:10:02.25#ibcon#end of sib2, iclass 18, count 0 2006.173.08:10:02.25#ibcon#*mode == 0, iclass 18, count 0 2006.173.08:10:02.25#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.08:10:02.25#ibcon#[25=USB\r\n] 2006.173.08:10:02.25#ibcon#*before write, iclass 18, count 0 2006.173.08:10:02.25#ibcon#enter sib2, iclass 18, count 0 2006.173.08:10:02.25#ibcon#flushed, iclass 18, count 0 2006.173.08:10:02.25#ibcon#about to write, iclass 18, count 0 2006.173.08:10:02.25#ibcon#wrote, iclass 18, count 0 2006.173.08:10:02.25#ibcon#about to read 3, iclass 18, count 0 2006.173.08:10:02.28#ibcon#read 3, iclass 18, count 0 2006.173.08:10:02.28#ibcon#about to read 4, iclass 18, count 0 2006.173.08:10:02.28#ibcon#read 4, iclass 18, count 0 2006.173.08:10:02.28#ibcon#about to read 5, iclass 18, count 0 2006.173.08:10:02.28#ibcon#read 5, iclass 18, count 0 2006.173.08:10:02.28#ibcon#about to read 6, iclass 18, count 0 2006.173.08:10:02.28#ibcon#read 6, iclass 18, count 0 2006.173.08:10:02.28#ibcon#end of sib2, iclass 18, count 0 2006.173.08:10:02.28#ibcon#*after write, iclass 18, count 0 2006.173.08:10:02.28#ibcon#*before return 0, iclass 18, count 0 2006.173.08:10:02.28#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.08:10:02.28#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.08:10:02.28#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.08:10:02.28#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.08:10:02.28$vck44/valo=7,864.99 2006.173.08:10:02.28#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.08:10:02.28#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.08:10:02.28#ibcon#ireg 17 cls_cnt 0 2006.173.08:10:02.28#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.08:10:02.28#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.08:10:02.28#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.08:10:02.28#ibcon#enter wrdev, iclass 20, count 0 2006.173.08:10:02.28#ibcon#first serial, iclass 20, count 0 2006.173.08:10:02.28#ibcon#enter sib2, iclass 20, count 0 2006.173.08:10:02.28#ibcon#flushed, iclass 20, count 0 2006.173.08:10:02.28#ibcon#about to write, iclass 20, count 0 2006.173.08:10:02.28#ibcon#wrote, iclass 20, count 0 2006.173.08:10:02.28#ibcon#about to read 3, iclass 20, count 0 2006.173.08:10:02.30#ibcon#read 3, iclass 20, count 0 2006.173.08:10:02.30#ibcon#about to read 4, iclass 20, count 0 2006.173.08:10:02.30#ibcon#read 4, iclass 20, count 0 2006.173.08:10:02.30#ibcon#about to read 5, iclass 20, count 0 2006.173.08:10:02.30#ibcon#read 5, iclass 20, count 0 2006.173.08:10:02.30#ibcon#about to read 6, iclass 20, count 0 2006.173.08:10:02.30#ibcon#read 6, iclass 20, count 0 2006.173.08:10:02.30#ibcon#end of sib2, iclass 20, count 0 2006.173.08:10:02.30#ibcon#*mode == 0, iclass 20, count 0 2006.173.08:10:02.30#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.08:10:02.30#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.08:10:02.30#ibcon#*before write, iclass 20, count 0 2006.173.08:10:02.30#ibcon#enter sib2, iclass 20, count 0 2006.173.08:10:02.30#ibcon#flushed, iclass 20, count 0 2006.173.08:10:02.30#ibcon#about to write, iclass 20, count 0 2006.173.08:10:02.30#ibcon#wrote, iclass 20, count 0 2006.173.08:10:02.30#ibcon#about to read 3, iclass 20, count 0 2006.173.08:10:02.34#ibcon#read 3, iclass 20, count 0 2006.173.08:10:02.34#ibcon#about to read 4, iclass 20, count 0 2006.173.08:10:02.34#ibcon#read 4, iclass 20, count 0 2006.173.08:10:02.34#ibcon#about to read 5, iclass 20, count 0 2006.173.08:10:02.34#ibcon#read 5, iclass 20, count 0 2006.173.08:10:02.34#ibcon#about to read 6, iclass 20, count 0 2006.173.08:10:02.34#ibcon#read 6, iclass 20, count 0 2006.173.08:10:02.34#ibcon#end of sib2, iclass 20, count 0 2006.173.08:10:02.34#ibcon#*after write, iclass 20, count 0 2006.173.08:10:02.34#ibcon#*before return 0, iclass 20, count 0 2006.173.08:10:02.34#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.08:10:02.34#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.08:10:02.34#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.08:10:02.34#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.08:10:02.34$vck44/va=7,4 2006.173.08:10:02.34#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.08:10:02.34#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.08:10:02.34#ibcon#ireg 11 cls_cnt 2 2006.173.08:10:02.34#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.08:10:02.40#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.08:10:02.40#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.08:10:02.40#ibcon#enter wrdev, iclass 22, count 2 2006.173.08:10:02.40#ibcon#first serial, iclass 22, count 2 2006.173.08:10:02.40#ibcon#enter sib2, iclass 22, count 2 2006.173.08:10:02.40#ibcon#flushed, iclass 22, count 2 2006.173.08:10:02.40#ibcon#about to write, iclass 22, count 2 2006.173.08:10:02.40#ibcon#wrote, iclass 22, count 2 2006.173.08:10:02.40#ibcon#about to read 3, iclass 22, count 2 2006.173.08:10:02.42#ibcon#read 3, iclass 22, count 2 2006.173.08:10:02.42#ibcon#about to read 4, iclass 22, count 2 2006.173.08:10:02.42#ibcon#read 4, iclass 22, count 2 2006.173.08:10:02.42#ibcon#about to read 5, iclass 22, count 2 2006.173.08:10:02.42#ibcon#read 5, iclass 22, count 2 2006.173.08:10:02.42#ibcon#about to read 6, iclass 22, count 2 2006.173.08:10:02.42#ibcon#read 6, iclass 22, count 2 2006.173.08:10:02.42#ibcon#end of sib2, iclass 22, count 2 2006.173.08:10:02.42#ibcon#*mode == 0, iclass 22, count 2 2006.173.08:10:02.42#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.08:10:02.42#ibcon#[25=AT07-04\r\n] 2006.173.08:10:02.42#ibcon#*before write, iclass 22, count 2 2006.173.08:10:02.42#ibcon#enter sib2, iclass 22, count 2 2006.173.08:10:02.42#ibcon#flushed, iclass 22, count 2 2006.173.08:10:02.42#ibcon#about to write, iclass 22, count 2 2006.173.08:10:02.42#ibcon#wrote, iclass 22, count 2 2006.173.08:10:02.42#ibcon#about to read 3, iclass 22, count 2 2006.173.08:10:02.45#ibcon#read 3, iclass 22, count 2 2006.173.08:10:02.45#ibcon#about to read 4, iclass 22, count 2 2006.173.08:10:02.45#ibcon#read 4, iclass 22, count 2 2006.173.08:10:02.45#ibcon#about to read 5, iclass 22, count 2 2006.173.08:10:02.45#ibcon#read 5, iclass 22, count 2 2006.173.08:10:02.45#ibcon#about to read 6, iclass 22, count 2 2006.173.08:10:02.45#ibcon#read 6, iclass 22, count 2 2006.173.08:10:02.45#ibcon#end of sib2, iclass 22, count 2 2006.173.08:10:02.45#ibcon#*after write, iclass 22, count 2 2006.173.08:10:02.45#ibcon#*before return 0, iclass 22, count 2 2006.173.08:10:02.45#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.08:10:02.45#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.08:10:02.45#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.08:10:02.45#ibcon#ireg 7 cls_cnt 0 2006.173.08:10:02.45#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.08:10:02.57#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.08:10:02.57#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.08:10:02.57#ibcon#enter wrdev, iclass 22, count 0 2006.173.08:10:02.57#ibcon#first serial, iclass 22, count 0 2006.173.08:10:02.57#ibcon#enter sib2, iclass 22, count 0 2006.173.08:10:02.57#ibcon#flushed, iclass 22, count 0 2006.173.08:10:02.57#ibcon#about to write, iclass 22, count 0 2006.173.08:10:02.57#ibcon#wrote, iclass 22, count 0 2006.173.08:10:02.57#ibcon#about to read 3, iclass 22, count 0 2006.173.08:10:02.59#ibcon#read 3, iclass 22, count 0 2006.173.08:10:02.59#ibcon#about to read 4, iclass 22, count 0 2006.173.08:10:02.59#ibcon#read 4, iclass 22, count 0 2006.173.08:10:02.59#ibcon#about to read 5, iclass 22, count 0 2006.173.08:10:02.59#ibcon#read 5, iclass 22, count 0 2006.173.08:10:02.59#ibcon#about to read 6, iclass 22, count 0 2006.173.08:10:02.59#ibcon#read 6, iclass 22, count 0 2006.173.08:10:02.59#ibcon#end of sib2, iclass 22, count 0 2006.173.08:10:02.59#ibcon#*mode == 0, iclass 22, count 0 2006.173.08:10:02.59#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.08:10:02.59#ibcon#[25=USB\r\n] 2006.173.08:10:02.59#ibcon#*before write, iclass 22, count 0 2006.173.08:10:02.59#ibcon#enter sib2, iclass 22, count 0 2006.173.08:10:02.59#ibcon#flushed, iclass 22, count 0 2006.173.08:10:02.59#ibcon#about to write, iclass 22, count 0 2006.173.08:10:02.59#ibcon#wrote, iclass 22, count 0 2006.173.08:10:02.59#ibcon#about to read 3, iclass 22, count 0 2006.173.08:10:02.62#ibcon#read 3, iclass 22, count 0 2006.173.08:10:02.62#ibcon#about to read 4, iclass 22, count 0 2006.173.08:10:02.62#ibcon#read 4, iclass 22, count 0 2006.173.08:10:02.62#ibcon#about to read 5, iclass 22, count 0 2006.173.08:10:02.62#ibcon#read 5, iclass 22, count 0 2006.173.08:10:02.62#ibcon#about to read 6, iclass 22, count 0 2006.173.08:10:02.62#ibcon#read 6, iclass 22, count 0 2006.173.08:10:02.62#ibcon#end of sib2, iclass 22, count 0 2006.173.08:10:02.62#ibcon#*after write, iclass 22, count 0 2006.173.08:10:02.62#ibcon#*before return 0, iclass 22, count 0 2006.173.08:10:02.62#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.08:10:02.62#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.08:10:02.62#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.08:10:02.62#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.08:10:02.62$vck44/valo=8,884.99 2006.173.08:10:02.62#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.08:10:02.62#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.08:10:02.62#ibcon#ireg 17 cls_cnt 0 2006.173.08:10:02.62#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.08:10:02.62#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.08:10:02.62#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.08:10:02.62#ibcon#enter wrdev, iclass 24, count 0 2006.173.08:10:02.62#ibcon#first serial, iclass 24, count 0 2006.173.08:10:02.62#ibcon#enter sib2, iclass 24, count 0 2006.173.08:10:02.62#ibcon#flushed, iclass 24, count 0 2006.173.08:10:02.62#ibcon#about to write, iclass 24, count 0 2006.173.08:10:02.62#ibcon#wrote, iclass 24, count 0 2006.173.08:10:02.62#ibcon#about to read 3, iclass 24, count 0 2006.173.08:10:02.64#ibcon#read 3, iclass 24, count 0 2006.173.08:10:02.64#ibcon#about to read 4, iclass 24, count 0 2006.173.08:10:02.64#ibcon#read 4, iclass 24, count 0 2006.173.08:10:02.64#ibcon#about to read 5, iclass 24, count 0 2006.173.08:10:02.64#ibcon#read 5, iclass 24, count 0 2006.173.08:10:02.64#ibcon#about to read 6, iclass 24, count 0 2006.173.08:10:02.64#ibcon#read 6, iclass 24, count 0 2006.173.08:10:02.64#ibcon#end of sib2, iclass 24, count 0 2006.173.08:10:02.64#ibcon#*mode == 0, iclass 24, count 0 2006.173.08:10:02.64#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.08:10:02.64#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.08:10:02.64#ibcon#*before write, iclass 24, count 0 2006.173.08:10:02.64#ibcon#enter sib2, iclass 24, count 0 2006.173.08:10:02.64#ibcon#flushed, iclass 24, count 0 2006.173.08:10:02.64#ibcon#about to write, iclass 24, count 0 2006.173.08:10:02.64#ibcon#wrote, iclass 24, count 0 2006.173.08:10:02.64#ibcon#about to read 3, iclass 24, count 0 2006.173.08:10:02.68#ibcon#read 3, iclass 24, count 0 2006.173.08:10:02.68#ibcon#about to read 4, iclass 24, count 0 2006.173.08:10:02.68#ibcon#read 4, iclass 24, count 0 2006.173.08:10:02.68#ibcon#about to read 5, iclass 24, count 0 2006.173.08:10:02.68#ibcon#read 5, iclass 24, count 0 2006.173.08:10:02.68#ibcon#about to read 6, iclass 24, count 0 2006.173.08:10:02.68#ibcon#read 6, iclass 24, count 0 2006.173.08:10:02.68#ibcon#end of sib2, iclass 24, count 0 2006.173.08:10:02.68#ibcon#*after write, iclass 24, count 0 2006.173.08:10:02.68#ibcon#*before return 0, iclass 24, count 0 2006.173.08:10:02.68#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.08:10:02.68#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.08:10:02.68#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.08:10:02.68#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.08:10:02.68$vck44/va=8,4 2006.173.08:10:02.68#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.08:10:02.68#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.08:10:02.68#ibcon#ireg 11 cls_cnt 2 2006.173.08:10:02.68#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.08:10:02.74#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.08:10:02.74#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.08:10:02.74#ibcon#enter wrdev, iclass 26, count 2 2006.173.08:10:02.74#ibcon#first serial, iclass 26, count 2 2006.173.08:10:02.74#ibcon#enter sib2, iclass 26, count 2 2006.173.08:10:02.74#ibcon#flushed, iclass 26, count 2 2006.173.08:10:02.74#ibcon#about to write, iclass 26, count 2 2006.173.08:10:02.74#ibcon#wrote, iclass 26, count 2 2006.173.08:10:02.74#ibcon#about to read 3, iclass 26, count 2 2006.173.08:10:02.76#ibcon#read 3, iclass 26, count 2 2006.173.08:10:02.76#ibcon#about to read 4, iclass 26, count 2 2006.173.08:10:02.76#ibcon#read 4, iclass 26, count 2 2006.173.08:10:02.76#ibcon#about to read 5, iclass 26, count 2 2006.173.08:10:02.76#ibcon#read 5, iclass 26, count 2 2006.173.08:10:02.76#ibcon#about to read 6, iclass 26, count 2 2006.173.08:10:02.76#ibcon#read 6, iclass 26, count 2 2006.173.08:10:02.76#ibcon#end of sib2, iclass 26, count 2 2006.173.08:10:02.76#ibcon#*mode == 0, iclass 26, count 2 2006.173.08:10:02.76#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.08:10:02.76#ibcon#[25=AT08-04\r\n] 2006.173.08:10:02.76#ibcon#*before write, iclass 26, count 2 2006.173.08:10:02.76#ibcon#enter sib2, iclass 26, count 2 2006.173.08:10:02.76#ibcon#flushed, iclass 26, count 2 2006.173.08:10:02.76#ibcon#about to write, iclass 26, count 2 2006.173.08:10:02.76#ibcon#wrote, iclass 26, count 2 2006.173.08:10:02.76#ibcon#about to read 3, iclass 26, count 2 2006.173.08:10:02.79#ibcon#read 3, iclass 26, count 2 2006.173.08:10:02.79#ibcon#about to read 4, iclass 26, count 2 2006.173.08:10:02.79#ibcon#read 4, iclass 26, count 2 2006.173.08:10:02.79#ibcon#about to read 5, iclass 26, count 2 2006.173.08:10:02.79#ibcon#read 5, iclass 26, count 2 2006.173.08:10:02.79#ibcon#about to read 6, iclass 26, count 2 2006.173.08:10:02.79#ibcon#read 6, iclass 26, count 2 2006.173.08:10:02.79#ibcon#end of sib2, iclass 26, count 2 2006.173.08:10:02.79#ibcon#*after write, iclass 26, count 2 2006.173.08:10:02.79#ibcon#*before return 0, iclass 26, count 2 2006.173.08:10:02.79#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.08:10:02.79#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.08:10:02.79#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.08:10:02.79#ibcon#ireg 7 cls_cnt 0 2006.173.08:10:02.79#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.08:10:02.91#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.08:10:02.91#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.08:10:02.91#ibcon#enter wrdev, iclass 26, count 0 2006.173.08:10:02.91#ibcon#first serial, iclass 26, count 0 2006.173.08:10:02.91#ibcon#enter sib2, iclass 26, count 0 2006.173.08:10:02.91#ibcon#flushed, iclass 26, count 0 2006.173.08:10:02.91#ibcon#about to write, iclass 26, count 0 2006.173.08:10:02.91#ibcon#wrote, iclass 26, count 0 2006.173.08:10:02.91#ibcon#about to read 3, iclass 26, count 0 2006.173.08:10:02.93#ibcon#read 3, iclass 26, count 0 2006.173.08:10:02.93#ibcon#about to read 4, iclass 26, count 0 2006.173.08:10:02.93#ibcon#read 4, iclass 26, count 0 2006.173.08:10:02.93#ibcon#about to read 5, iclass 26, count 0 2006.173.08:10:02.93#ibcon#read 5, iclass 26, count 0 2006.173.08:10:02.93#ibcon#about to read 6, iclass 26, count 0 2006.173.08:10:02.93#ibcon#read 6, iclass 26, count 0 2006.173.08:10:02.93#ibcon#end of sib2, iclass 26, count 0 2006.173.08:10:02.93#ibcon#*mode == 0, iclass 26, count 0 2006.173.08:10:02.93#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.08:10:02.93#ibcon#[25=USB\r\n] 2006.173.08:10:02.93#ibcon#*before write, iclass 26, count 0 2006.173.08:10:02.93#ibcon#enter sib2, iclass 26, count 0 2006.173.08:10:02.93#ibcon#flushed, iclass 26, count 0 2006.173.08:10:02.93#ibcon#about to write, iclass 26, count 0 2006.173.08:10:02.93#ibcon#wrote, iclass 26, count 0 2006.173.08:10:02.93#ibcon#about to read 3, iclass 26, count 0 2006.173.08:10:02.96#ibcon#read 3, iclass 26, count 0 2006.173.08:10:02.96#ibcon#about to read 4, iclass 26, count 0 2006.173.08:10:02.96#ibcon#read 4, iclass 26, count 0 2006.173.08:10:02.96#ibcon#about to read 5, iclass 26, count 0 2006.173.08:10:02.96#ibcon#read 5, iclass 26, count 0 2006.173.08:10:02.96#ibcon#about to read 6, iclass 26, count 0 2006.173.08:10:02.96#ibcon#read 6, iclass 26, count 0 2006.173.08:10:02.96#ibcon#end of sib2, iclass 26, count 0 2006.173.08:10:02.96#ibcon#*after write, iclass 26, count 0 2006.173.08:10:02.96#ibcon#*before return 0, iclass 26, count 0 2006.173.08:10:02.96#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.08:10:02.96#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.08:10:02.96#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.08:10:02.96#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.08:10:02.96$vck44/vblo=1,629.99 2006.173.08:10:02.96#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.08:10:02.96#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.08:10:02.96#ibcon#ireg 17 cls_cnt 0 2006.173.08:10:02.96#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.08:10:02.96#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.08:10:02.96#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.08:10:02.96#ibcon#enter wrdev, iclass 28, count 0 2006.173.08:10:02.96#ibcon#first serial, iclass 28, count 0 2006.173.08:10:02.96#ibcon#enter sib2, iclass 28, count 0 2006.173.08:10:02.96#ibcon#flushed, iclass 28, count 0 2006.173.08:10:02.96#ibcon#about to write, iclass 28, count 0 2006.173.08:10:02.96#ibcon#wrote, iclass 28, count 0 2006.173.08:10:02.96#ibcon#about to read 3, iclass 28, count 0 2006.173.08:10:02.98#ibcon#read 3, iclass 28, count 0 2006.173.08:10:02.98#ibcon#about to read 4, iclass 28, count 0 2006.173.08:10:02.98#ibcon#read 4, iclass 28, count 0 2006.173.08:10:02.98#ibcon#about to read 5, iclass 28, count 0 2006.173.08:10:02.98#ibcon#read 5, iclass 28, count 0 2006.173.08:10:02.98#ibcon#about to read 6, iclass 28, count 0 2006.173.08:10:02.98#ibcon#read 6, iclass 28, count 0 2006.173.08:10:02.98#ibcon#end of sib2, iclass 28, count 0 2006.173.08:10:02.98#ibcon#*mode == 0, iclass 28, count 0 2006.173.08:10:02.98#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.08:10:02.98#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.08:10:02.98#ibcon#*before write, iclass 28, count 0 2006.173.08:10:02.98#ibcon#enter sib2, iclass 28, count 0 2006.173.08:10:02.98#ibcon#flushed, iclass 28, count 0 2006.173.08:10:02.98#ibcon#about to write, iclass 28, count 0 2006.173.08:10:02.98#ibcon#wrote, iclass 28, count 0 2006.173.08:10:02.98#ibcon#about to read 3, iclass 28, count 0 2006.173.08:10:03.02#ibcon#read 3, iclass 28, count 0 2006.173.08:10:03.02#ibcon#about to read 4, iclass 28, count 0 2006.173.08:10:03.02#ibcon#read 4, iclass 28, count 0 2006.173.08:10:03.02#ibcon#about to read 5, iclass 28, count 0 2006.173.08:10:03.02#ibcon#read 5, iclass 28, count 0 2006.173.08:10:03.02#ibcon#about to read 6, iclass 28, count 0 2006.173.08:10:03.02#ibcon#read 6, iclass 28, count 0 2006.173.08:10:03.02#ibcon#end of sib2, iclass 28, count 0 2006.173.08:10:03.02#ibcon#*after write, iclass 28, count 0 2006.173.08:10:03.02#ibcon#*before return 0, iclass 28, count 0 2006.173.08:10:03.02#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.08:10:03.02#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.08:10:03.02#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.08:10:03.02#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.08:10:03.02$vck44/vb=1,4 2006.173.08:10:03.02#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.08:10:03.02#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.08:10:03.02#ibcon#ireg 11 cls_cnt 2 2006.173.08:10:03.02#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.08:10:03.02#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.08:10:03.02#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.08:10:03.02#ibcon#enter wrdev, iclass 30, count 2 2006.173.08:10:03.02#ibcon#first serial, iclass 30, count 2 2006.173.08:10:03.02#ibcon#enter sib2, iclass 30, count 2 2006.173.08:10:03.02#ibcon#flushed, iclass 30, count 2 2006.173.08:10:03.02#ibcon#about to write, iclass 30, count 2 2006.173.08:10:03.02#ibcon#wrote, iclass 30, count 2 2006.173.08:10:03.02#ibcon#about to read 3, iclass 30, count 2 2006.173.08:10:03.04#ibcon#read 3, iclass 30, count 2 2006.173.08:10:03.04#ibcon#about to read 4, iclass 30, count 2 2006.173.08:10:03.04#ibcon#read 4, iclass 30, count 2 2006.173.08:10:03.04#ibcon#about to read 5, iclass 30, count 2 2006.173.08:10:03.04#ibcon#read 5, iclass 30, count 2 2006.173.08:10:03.04#ibcon#about to read 6, iclass 30, count 2 2006.173.08:10:03.04#ibcon#read 6, iclass 30, count 2 2006.173.08:10:03.04#ibcon#end of sib2, iclass 30, count 2 2006.173.08:10:03.04#ibcon#*mode == 0, iclass 30, count 2 2006.173.08:10:03.04#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.08:10:03.04#ibcon#[27=AT01-04\r\n] 2006.173.08:10:03.04#ibcon#*before write, iclass 30, count 2 2006.173.08:10:03.04#ibcon#enter sib2, iclass 30, count 2 2006.173.08:10:03.04#ibcon#flushed, iclass 30, count 2 2006.173.08:10:03.04#ibcon#about to write, iclass 30, count 2 2006.173.08:10:03.04#ibcon#wrote, iclass 30, count 2 2006.173.08:10:03.04#ibcon#about to read 3, iclass 30, count 2 2006.173.08:10:03.07#ibcon#read 3, iclass 30, count 2 2006.173.08:10:03.07#ibcon#about to read 4, iclass 30, count 2 2006.173.08:10:03.07#ibcon#read 4, iclass 30, count 2 2006.173.08:10:03.07#ibcon#about to read 5, iclass 30, count 2 2006.173.08:10:03.07#ibcon#read 5, iclass 30, count 2 2006.173.08:10:03.07#ibcon#about to read 6, iclass 30, count 2 2006.173.08:10:03.07#ibcon#read 6, iclass 30, count 2 2006.173.08:10:03.07#ibcon#end of sib2, iclass 30, count 2 2006.173.08:10:03.07#ibcon#*after write, iclass 30, count 2 2006.173.08:10:03.07#ibcon#*before return 0, iclass 30, count 2 2006.173.08:10:03.07#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.08:10:03.07#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.08:10:03.07#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.08:10:03.07#ibcon#ireg 7 cls_cnt 0 2006.173.08:10:03.07#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.08:10:03.19#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.08:10:03.19#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.08:10:03.19#ibcon#enter wrdev, iclass 30, count 0 2006.173.08:10:03.19#ibcon#first serial, iclass 30, count 0 2006.173.08:10:03.19#ibcon#enter sib2, iclass 30, count 0 2006.173.08:10:03.19#ibcon#flushed, iclass 30, count 0 2006.173.08:10:03.19#ibcon#about to write, iclass 30, count 0 2006.173.08:10:03.19#ibcon#wrote, iclass 30, count 0 2006.173.08:10:03.19#ibcon#about to read 3, iclass 30, count 0 2006.173.08:10:03.21#ibcon#read 3, iclass 30, count 0 2006.173.08:10:03.21#ibcon#about to read 4, iclass 30, count 0 2006.173.08:10:03.21#ibcon#read 4, iclass 30, count 0 2006.173.08:10:03.21#ibcon#about to read 5, iclass 30, count 0 2006.173.08:10:03.21#ibcon#read 5, iclass 30, count 0 2006.173.08:10:03.21#ibcon#about to read 6, iclass 30, count 0 2006.173.08:10:03.21#ibcon#read 6, iclass 30, count 0 2006.173.08:10:03.21#ibcon#end of sib2, iclass 30, count 0 2006.173.08:10:03.21#ibcon#*mode == 0, iclass 30, count 0 2006.173.08:10:03.21#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.08:10:03.21#ibcon#[27=USB\r\n] 2006.173.08:10:03.21#ibcon#*before write, iclass 30, count 0 2006.173.08:10:03.21#ibcon#enter sib2, iclass 30, count 0 2006.173.08:10:03.21#ibcon#flushed, iclass 30, count 0 2006.173.08:10:03.21#ibcon#about to write, iclass 30, count 0 2006.173.08:10:03.21#ibcon#wrote, iclass 30, count 0 2006.173.08:10:03.21#ibcon#about to read 3, iclass 30, count 0 2006.173.08:10:03.24#ibcon#read 3, iclass 30, count 0 2006.173.08:10:03.24#ibcon#about to read 4, iclass 30, count 0 2006.173.08:10:03.24#ibcon#read 4, iclass 30, count 0 2006.173.08:10:03.24#ibcon#about to read 5, iclass 30, count 0 2006.173.08:10:03.24#ibcon#read 5, iclass 30, count 0 2006.173.08:10:03.24#ibcon#about to read 6, iclass 30, count 0 2006.173.08:10:03.24#ibcon#read 6, iclass 30, count 0 2006.173.08:10:03.24#ibcon#end of sib2, iclass 30, count 0 2006.173.08:10:03.24#ibcon#*after write, iclass 30, count 0 2006.173.08:10:03.24#ibcon#*before return 0, iclass 30, count 0 2006.173.08:10:03.24#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.08:10:03.24#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.08:10:03.24#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.08:10:03.24#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.08:10:03.24$vck44/vblo=2,634.99 2006.173.08:10:03.24#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.08:10:03.24#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.08:10:03.24#ibcon#ireg 17 cls_cnt 0 2006.173.08:10:03.24#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.08:10:03.24#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.08:10:03.24#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.08:10:03.24#ibcon#enter wrdev, iclass 32, count 0 2006.173.08:10:03.24#ibcon#first serial, iclass 32, count 0 2006.173.08:10:03.24#ibcon#enter sib2, iclass 32, count 0 2006.173.08:10:03.24#ibcon#flushed, iclass 32, count 0 2006.173.08:10:03.24#ibcon#about to write, iclass 32, count 0 2006.173.08:10:03.24#ibcon#wrote, iclass 32, count 0 2006.173.08:10:03.24#ibcon#about to read 3, iclass 32, count 0 2006.173.08:10:03.26#ibcon#read 3, iclass 32, count 0 2006.173.08:10:03.26#ibcon#about to read 4, iclass 32, count 0 2006.173.08:10:03.26#ibcon#read 4, iclass 32, count 0 2006.173.08:10:03.26#ibcon#about to read 5, iclass 32, count 0 2006.173.08:10:03.26#ibcon#read 5, iclass 32, count 0 2006.173.08:10:03.26#ibcon#about to read 6, iclass 32, count 0 2006.173.08:10:03.26#ibcon#read 6, iclass 32, count 0 2006.173.08:10:03.26#ibcon#end of sib2, iclass 32, count 0 2006.173.08:10:03.26#ibcon#*mode == 0, iclass 32, count 0 2006.173.08:10:03.26#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.08:10:03.26#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.08:10:03.26#ibcon#*before write, iclass 32, count 0 2006.173.08:10:03.26#ibcon#enter sib2, iclass 32, count 0 2006.173.08:10:03.26#ibcon#flushed, iclass 32, count 0 2006.173.08:10:03.26#ibcon#about to write, iclass 32, count 0 2006.173.08:10:03.26#ibcon#wrote, iclass 32, count 0 2006.173.08:10:03.26#ibcon#about to read 3, iclass 32, count 0 2006.173.08:10:03.30#ibcon#read 3, iclass 32, count 0 2006.173.08:10:03.30#ibcon#about to read 4, iclass 32, count 0 2006.173.08:10:03.30#ibcon#read 4, iclass 32, count 0 2006.173.08:10:03.30#ibcon#about to read 5, iclass 32, count 0 2006.173.08:10:03.30#ibcon#read 5, iclass 32, count 0 2006.173.08:10:03.30#ibcon#about to read 6, iclass 32, count 0 2006.173.08:10:03.30#ibcon#read 6, iclass 32, count 0 2006.173.08:10:03.30#ibcon#end of sib2, iclass 32, count 0 2006.173.08:10:03.30#ibcon#*after write, iclass 32, count 0 2006.173.08:10:03.30#ibcon#*before return 0, iclass 32, count 0 2006.173.08:10:03.30#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.08:10:03.30#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.08:10:03.30#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.08:10:03.30#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.08:10:03.30$vck44/vb=2,4 2006.173.08:10:03.30#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.08:10:03.30#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.08:10:03.30#ibcon#ireg 11 cls_cnt 2 2006.173.08:10:03.30#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.08:10:03.36#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.08:10:03.36#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.08:10:03.36#ibcon#enter wrdev, iclass 34, count 2 2006.173.08:10:03.36#ibcon#first serial, iclass 34, count 2 2006.173.08:10:03.36#ibcon#enter sib2, iclass 34, count 2 2006.173.08:10:03.36#ibcon#flushed, iclass 34, count 2 2006.173.08:10:03.36#ibcon#about to write, iclass 34, count 2 2006.173.08:10:03.36#ibcon#wrote, iclass 34, count 2 2006.173.08:10:03.36#ibcon#about to read 3, iclass 34, count 2 2006.173.08:10:03.38#ibcon#read 3, iclass 34, count 2 2006.173.08:10:03.38#ibcon#about to read 4, iclass 34, count 2 2006.173.08:10:03.38#ibcon#read 4, iclass 34, count 2 2006.173.08:10:03.38#ibcon#about to read 5, iclass 34, count 2 2006.173.08:10:03.38#ibcon#read 5, iclass 34, count 2 2006.173.08:10:03.38#ibcon#about to read 6, iclass 34, count 2 2006.173.08:10:03.38#ibcon#read 6, iclass 34, count 2 2006.173.08:10:03.38#ibcon#end of sib2, iclass 34, count 2 2006.173.08:10:03.38#ibcon#*mode == 0, iclass 34, count 2 2006.173.08:10:03.38#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.08:10:03.38#ibcon#[27=AT02-04\r\n] 2006.173.08:10:03.38#ibcon#*before write, iclass 34, count 2 2006.173.08:10:03.38#ibcon#enter sib2, iclass 34, count 2 2006.173.08:10:03.38#ibcon#flushed, iclass 34, count 2 2006.173.08:10:03.38#ibcon#about to write, iclass 34, count 2 2006.173.08:10:03.38#ibcon#wrote, iclass 34, count 2 2006.173.08:10:03.38#ibcon#about to read 3, iclass 34, count 2 2006.173.08:10:03.41#ibcon#read 3, iclass 34, count 2 2006.173.08:10:03.41#ibcon#about to read 4, iclass 34, count 2 2006.173.08:10:03.41#ibcon#read 4, iclass 34, count 2 2006.173.08:10:03.41#ibcon#about to read 5, iclass 34, count 2 2006.173.08:10:03.41#ibcon#read 5, iclass 34, count 2 2006.173.08:10:03.41#ibcon#about to read 6, iclass 34, count 2 2006.173.08:10:03.41#ibcon#read 6, iclass 34, count 2 2006.173.08:10:03.41#ibcon#end of sib2, iclass 34, count 2 2006.173.08:10:03.41#ibcon#*after write, iclass 34, count 2 2006.173.08:10:03.41#ibcon#*before return 0, iclass 34, count 2 2006.173.08:10:03.41#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.08:10:03.41#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.08:10:03.41#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.08:10:03.41#ibcon#ireg 7 cls_cnt 0 2006.173.08:10:03.41#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.08:10:03.53#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.08:10:03.53#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.08:10:03.53#ibcon#enter wrdev, iclass 34, count 0 2006.173.08:10:03.53#ibcon#first serial, iclass 34, count 0 2006.173.08:10:03.53#ibcon#enter sib2, iclass 34, count 0 2006.173.08:10:03.53#ibcon#flushed, iclass 34, count 0 2006.173.08:10:03.53#ibcon#about to write, iclass 34, count 0 2006.173.08:10:03.53#ibcon#wrote, iclass 34, count 0 2006.173.08:10:03.53#ibcon#about to read 3, iclass 34, count 0 2006.173.08:10:03.55#ibcon#read 3, iclass 34, count 0 2006.173.08:10:03.55#ibcon#about to read 4, iclass 34, count 0 2006.173.08:10:03.55#ibcon#read 4, iclass 34, count 0 2006.173.08:10:03.55#ibcon#about to read 5, iclass 34, count 0 2006.173.08:10:03.55#ibcon#read 5, iclass 34, count 0 2006.173.08:10:03.55#ibcon#about to read 6, iclass 34, count 0 2006.173.08:10:03.55#ibcon#read 6, iclass 34, count 0 2006.173.08:10:03.55#ibcon#end of sib2, iclass 34, count 0 2006.173.08:10:03.55#ibcon#*mode == 0, iclass 34, count 0 2006.173.08:10:03.55#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.08:10:03.55#ibcon#[27=USB\r\n] 2006.173.08:10:03.55#ibcon#*before write, iclass 34, count 0 2006.173.08:10:03.55#ibcon#enter sib2, iclass 34, count 0 2006.173.08:10:03.55#ibcon#flushed, iclass 34, count 0 2006.173.08:10:03.55#ibcon#about to write, iclass 34, count 0 2006.173.08:10:03.55#ibcon#wrote, iclass 34, count 0 2006.173.08:10:03.55#ibcon#about to read 3, iclass 34, count 0 2006.173.08:10:03.58#ibcon#read 3, iclass 34, count 0 2006.173.08:10:03.58#ibcon#about to read 4, iclass 34, count 0 2006.173.08:10:03.58#ibcon#read 4, iclass 34, count 0 2006.173.08:10:03.58#ibcon#about to read 5, iclass 34, count 0 2006.173.08:10:03.58#ibcon#read 5, iclass 34, count 0 2006.173.08:10:03.58#ibcon#about to read 6, iclass 34, count 0 2006.173.08:10:03.58#ibcon#read 6, iclass 34, count 0 2006.173.08:10:03.58#ibcon#end of sib2, iclass 34, count 0 2006.173.08:10:03.58#ibcon#*after write, iclass 34, count 0 2006.173.08:10:03.58#ibcon#*before return 0, iclass 34, count 0 2006.173.08:10:03.58#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.08:10:03.58#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.08:10:03.58#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.08:10:03.58#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.08:10:03.58$vck44/vblo=3,649.99 2006.173.08:10:03.58#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.08:10:03.58#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.08:10:03.58#ibcon#ireg 17 cls_cnt 0 2006.173.08:10:03.58#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.08:10:03.58#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.08:10:03.58#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.08:10:03.58#ibcon#enter wrdev, iclass 36, count 0 2006.173.08:10:03.58#ibcon#first serial, iclass 36, count 0 2006.173.08:10:03.58#ibcon#enter sib2, iclass 36, count 0 2006.173.08:10:03.58#ibcon#flushed, iclass 36, count 0 2006.173.08:10:03.58#ibcon#about to write, iclass 36, count 0 2006.173.08:10:03.58#ibcon#wrote, iclass 36, count 0 2006.173.08:10:03.58#ibcon#about to read 3, iclass 36, count 0 2006.173.08:10:03.60#ibcon#read 3, iclass 36, count 0 2006.173.08:10:03.60#ibcon#about to read 4, iclass 36, count 0 2006.173.08:10:03.60#ibcon#read 4, iclass 36, count 0 2006.173.08:10:03.60#ibcon#about to read 5, iclass 36, count 0 2006.173.08:10:03.60#ibcon#read 5, iclass 36, count 0 2006.173.08:10:03.60#ibcon#about to read 6, iclass 36, count 0 2006.173.08:10:03.60#ibcon#read 6, iclass 36, count 0 2006.173.08:10:03.60#ibcon#end of sib2, iclass 36, count 0 2006.173.08:10:03.60#ibcon#*mode == 0, iclass 36, count 0 2006.173.08:10:03.60#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.08:10:03.60#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.08:10:03.60#ibcon#*before write, iclass 36, count 0 2006.173.08:10:03.60#ibcon#enter sib2, iclass 36, count 0 2006.173.08:10:03.60#ibcon#flushed, iclass 36, count 0 2006.173.08:10:03.60#ibcon#about to write, iclass 36, count 0 2006.173.08:10:03.60#ibcon#wrote, iclass 36, count 0 2006.173.08:10:03.60#ibcon#about to read 3, iclass 36, count 0 2006.173.08:10:03.64#ibcon#read 3, iclass 36, count 0 2006.173.08:10:03.64#ibcon#about to read 4, iclass 36, count 0 2006.173.08:10:03.64#ibcon#read 4, iclass 36, count 0 2006.173.08:10:03.64#ibcon#about to read 5, iclass 36, count 0 2006.173.08:10:03.64#ibcon#read 5, iclass 36, count 0 2006.173.08:10:03.64#ibcon#about to read 6, iclass 36, count 0 2006.173.08:10:03.64#ibcon#read 6, iclass 36, count 0 2006.173.08:10:03.64#ibcon#end of sib2, iclass 36, count 0 2006.173.08:10:03.64#ibcon#*after write, iclass 36, count 0 2006.173.08:10:03.64#ibcon#*before return 0, iclass 36, count 0 2006.173.08:10:03.64#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.08:10:03.64#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.08:10:03.64#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.08:10:03.64#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.08:10:03.64$vck44/vb=3,4 2006.173.08:10:03.64#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.08:10:03.64#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.08:10:03.64#ibcon#ireg 11 cls_cnt 2 2006.173.08:10:03.64#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.08:10:03.70#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.08:10:03.70#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.08:10:03.70#ibcon#enter wrdev, iclass 38, count 2 2006.173.08:10:03.70#ibcon#first serial, iclass 38, count 2 2006.173.08:10:03.70#ibcon#enter sib2, iclass 38, count 2 2006.173.08:10:03.70#ibcon#flushed, iclass 38, count 2 2006.173.08:10:03.70#ibcon#about to write, iclass 38, count 2 2006.173.08:10:03.70#ibcon#wrote, iclass 38, count 2 2006.173.08:10:03.70#ibcon#about to read 3, iclass 38, count 2 2006.173.08:10:03.72#ibcon#read 3, iclass 38, count 2 2006.173.08:10:03.72#ibcon#about to read 4, iclass 38, count 2 2006.173.08:10:03.72#ibcon#read 4, iclass 38, count 2 2006.173.08:10:03.72#ibcon#about to read 5, iclass 38, count 2 2006.173.08:10:03.72#ibcon#read 5, iclass 38, count 2 2006.173.08:10:03.72#ibcon#about to read 6, iclass 38, count 2 2006.173.08:10:03.72#ibcon#read 6, iclass 38, count 2 2006.173.08:10:03.72#ibcon#end of sib2, iclass 38, count 2 2006.173.08:10:03.72#ibcon#*mode == 0, iclass 38, count 2 2006.173.08:10:03.72#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.08:10:03.72#ibcon#[27=AT03-04\r\n] 2006.173.08:10:03.72#ibcon#*before write, iclass 38, count 2 2006.173.08:10:03.72#ibcon#enter sib2, iclass 38, count 2 2006.173.08:10:03.72#ibcon#flushed, iclass 38, count 2 2006.173.08:10:03.72#ibcon#about to write, iclass 38, count 2 2006.173.08:10:03.72#ibcon#wrote, iclass 38, count 2 2006.173.08:10:03.72#ibcon#about to read 3, iclass 38, count 2 2006.173.08:10:03.75#ibcon#read 3, iclass 38, count 2 2006.173.08:10:03.75#ibcon#about to read 4, iclass 38, count 2 2006.173.08:10:03.75#ibcon#read 4, iclass 38, count 2 2006.173.08:10:03.75#ibcon#about to read 5, iclass 38, count 2 2006.173.08:10:03.75#ibcon#read 5, iclass 38, count 2 2006.173.08:10:03.75#ibcon#about to read 6, iclass 38, count 2 2006.173.08:10:03.75#ibcon#read 6, iclass 38, count 2 2006.173.08:10:03.75#ibcon#end of sib2, iclass 38, count 2 2006.173.08:10:03.75#ibcon#*after write, iclass 38, count 2 2006.173.08:10:03.75#ibcon#*before return 0, iclass 38, count 2 2006.173.08:10:03.75#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.08:10:03.75#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.08:10:03.75#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.08:10:03.75#ibcon#ireg 7 cls_cnt 0 2006.173.08:10:03.75#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.08:10:03.87#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.08:10:03.87#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.08:10:03.87#ibcon#enter wrdev, iclass 38, count 0 2006.173.08:10:03.87#ibcon#first serial, iclass 38, count 0 2006.173.08:10:03.87#ibcon#enter sib2, iclass 38, count 0 2006.173.08:10:03.87#ibcon#flushed, iclass 38, count 0 2006.173.08:10:03.87#ibcon#about to write, iclass 38, count 0 2006.173.08:10:03.87#ibcon#wrote, iclass 38, count 0 2006.173.08:10:03.87#ibcon#about to read 3, iclass 38, count 0 2006.173.08:10:03.89#ibcon#read 3, iclass 38, count 0 2006.173.08:10:03.89#ibcon#about to read 4, iclass 38, count 0 2006.173.08:10:03.89#ibcon#read 4, iclass 38, count 0 2006.173.08:10:03.89#ibcon#about to read 5, iclass 38, count 0 2006.173.08:10:03.89#ibcon#read 5, iclass 38, count 0 2006.173.08:10:03.89#ibcon#about to read 6, iclass 38, count 0 2006.173.08:10:03.89#ibcon#read 6, iclass 38, count 0 2006.173.08:10:03.89#ibcon#end of sib2, iclass 38, count 0 2006.173.08:10:03.89#ibcon#*mode == 0, iclass 38, count 0 2006.173.08:10:03.89#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.08:10:03.89#ibcon#[27=USB\r\n] 2006.173.08:10:03.89#ibcon#*before write, iclass 38, count 0 2006.173.08:10:03.89#ibcon#enter sib2, iclass 38, count 0 2006.173.08:10:03.89#ibcon#flushed, iclass 38, count 0 2006.173.08:10:03.89#ibcon#about to write, iclass 38, count 0 2006.173.08:10:03.89#ibcon#wrote, iclass 38, count 0 2006.173.08:10:03.89#ibcon#about to read 3, iclass 38, count 0 2006.173.08:10:03.92#ibcon#read 3, iclass 38, count 0 2006.173.08:10:03.92#ibcon#about to read 4, iclass 38, count 0 2006.173.08:10:03.92#ibcon#read 4, iclass 38, count 0 2006.173.08:10:03.92#ibcon#about to read 5, iclass 38, count 0 2006.173.08:10:03.92#ibcon#read 5, iclass 38, count 0 2006.173.08:10:03.92#ibcon#about to read 6, iclass 38, count 0 2006.173.08:10:03.92#ibcon#read 6, iclass 38, count 0 2006.173.08:10:03.92#ibcon#end of sib2, iclass 38, count 0 2006.173.08:10:03.92#ibcon#*after write, iclass 38, count 0 2006.173.08:10:03.92#ibcon#*before return 0, iclass 38, count 0 2006.173.08:10:03.92#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.08:10:03.92#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.08:10:03.92#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.08:10:03.92#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.08:10:03.92$vck44/vblo=4,679.99 2006.173.08:10:03.92#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.08:10:03.92#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.08:10:03.92#ibcon#ireg 17 cls_cnt 0 2006.173.08:10:03.92#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.08:10:03.92#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.08:10:03.92#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.08:10:03.92#ibcon#enter wrdev, iclass 40, count 0 2006.173.08:10:03.92#ibcon#first serial, iclass 40, count 0 2006.173.08:10:03.92#ibcon#enter sib2, iclass 40, count 0 2006.173.08:10:03.92#ibcon#flushed, iclass 40, count 0 2006.173.08:10:03.92#ibcon#about to write, iclass 40, count 0 2006.173.08:10:03.92#ibcon#wrote, iclass 40, count 0 2006.173.08:10:03.92#ibcon#about to read 3, iclass 40, count 0 2006.173.08:10:03.94#ibcon#read 3, iclass 40, count 0 2006.173.08:10:03.94#ibcon#about to read 4, iclass 40, count 0 2006.173.08:10:03.94#ibcon#read 4, iclass 40, count 0 2006.173.08:10:03.94#ibcon#about to read 5, iclass 40, count 0 2006.173.08:10:03.94#ibcon#read 5, iclass 40, count 0 2006.173.08:10:03.94#ibcon#about to read 6, iclass 40, count 0 2006.173.08:10:03.94#ibcon#read 6, iclass 40, count 0 2006.173.08:10:03.94#ibcon#end of sib2, iclass 40, count 0 2006.173.08:10:03.94#ibcon#*mode == 0, iclass 40, count 0 2006.173.08:10:03.94#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.08:10:03.94#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.08:10:03.94#ibcon#*before write, iclass 40, count 0 2006.173.08:10:03.94#ibcon#enter sib2, iclass 40, count 0 2006.173.08:10:03.94#ibcon#flushed, iclass 40, count 0 2006.173.08:10:03.94#ibcon#about to write, iclass 40, count 0 2006.173.08:10:03.94#ibcon#wrote, iclass 40, count 0 2006.173.08:10:03.94#ibcon#about to read 3, iclass 40, count 0 2006.173.08:10:03.98#ibcon#read 3, iclass 40, count 0 2006.173.08:10:03.98#ibcon#about to read 4, iclass 40, count 0 2006.173.08:10:03.98#ibcon#read 4, iclass 40, count 0 2006.173.08:10:03.98#ibcon#about to read 5, iclass 40, count 0 2006.173.08:10:03.98#ibcon#read 5, iclass 40, count 0 2006.173.08:10:03.98#ibcon#about to read 6, iclass 40, count 0 2006.173.08:10:03.98#ibcon#read 6, iclass 40, count 0 2006.173.08:10:03.98#ibcon#end of sib2, iclass 40, count 0 2006.173.08:10:03.98#ibcon#*after write, iclass 40, count 0 2006.173.08:10:03.98#ibcon#*before return 0, iclass 40, count 0 2006.173.08:10:03.98#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.08:10:03.98#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.08:10:03.98#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.08:10:03.98#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.08:10:03.98$vck44/vb=4,4 2006.173.08:10:03.98#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.08:10:03.98#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.08:10:03.98#ibcon#ireg 11 cls_cnt 2 2006.173.08:10:03.98#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.08:10:04.04#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.08:10:04.04#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.08:10:04.04#ibcon#enter wrdev, iclass 4, count 2 2006.173.08:10:04.04#ibcon#first serial, iclass 4, count 2 2006.173.08:10:04.04#ibcon#enter sib2, iclass 4, count 2 2006.173.08:10:04.04#ibcon#flushed, iclass 4, count 2 2006.173.08:10:04.04#ibcon#about to write, iclass 4, count 2 2006.173.08:10:04.04#ibcon#wrote, iclass 4, count 2 2006.173.08:10:04.04#ibcon#about to read 3, iclass 4, count 2 2006.173.08:10:04.06#ibcon#read 3, iclass 4, count 2 2006.173.08:10:04.06#ibcon#about to read 4, iclass 4, count 2 2006.173.08:10:04.06#ibcon#read 4, iclass 4, count 2 2006.173.08:10:04.06#ibcon#about to read 5, iclass 4, count 2 2006.173.08:10:04.06#ibcon#read 5, iclass 4, count 2 2006.173.08:10:04.06#ibcon#about to read 6, iclass 4, count 2 2006.173.08:10:04.06#ibcon#read 6, iclass 4, count 2 2006.173.08:10:04.06#ibcon#end of sib2, iclass 4, count 2 2006.173.08:10:04.06#ibcon#*mode == 0, iclass 4, count 2 2006.173.08:10:04.06#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.08:10:04.06#ibcon#[27=AT04-04\r\n] 2006.173.08:10:04.06#ibcon#*before write, iclass 4, count 2 2006.173.08:10:04.06#ibcon#enter sib2, iclass 4, count 2 2006.173.08:10:04.06#ibcon#flushed, iclass 4, count 2 2006.173.08:10:04.06#ibcon#about to write, iclass 4, count 2 2006.173.08:10:04.06#ibcon#wrote, iclass 4, count 2 2006.173.08:10:04.06#ibcon#about to read 3, iclass 4, count 2 2006.173.08:10:04.09#ibcon#read 3, iclass 4, count 2 2006.173.08:10:04.09#ibcon#about to read 4, iclass 4, count 2 2006.173.08:10:04.09#ibcon#read 4, iclass 4, count 2 2006.173.08:10:04.09#ibcon#about to read 5, iclass 4, count 2 2006.173.08:10:04.09#ibcon#read 5, iclass 4, count 2 2006.173.08:10:04.09#ibcon#about to read 6, iclass 4, count 2 2006.173.08:10:04.09#ibcon#read 6, iclass 4, count 2 2006.173.08:10:04.09#ibcon#end of sib2, iclass 4, count 2 2006.173.08:10:04.09#ibcon#*after write, iclass 4, count 2 2006.173.08:10:04.09#ibcon#*before return 0, iclass 4, count 2 2006.173.08:10:04.09#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.08:10:04.09#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.08:10:04.09#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.08:10:04.09#ibcon#ireg 7 cls_cnt 0 2006.173.08:10:04.09#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.08:10:04.21#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.08:10:04.21#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.08:10:04.21#ibcon#enter wrdev, iclass 4, count 0 2006.173.08:10:04.21#ibcon#first serial, iclass 4, count 0 2006.173.08:10:04.21#ibcon#enter sib2, iclass 4, count 0 2006.173.08:10:04.21#ibcon#flushed, iclass 4, count 0 2006.173.08:10:04.21#ibcon#about to write, iclass 4, count 0 2006.173.08:10:04.21#ibcon#wrote, iclass 4, count 0 2006.173.08:10:04.21#ibcon#about to read 3, iclass 4, count 0 2006.173.08:10:04.23#ibcon#read 3, iclass 4, count 0 2006.173.08:10:04.23#ibcon#about to read 4, iclass 4, count 0 2006.173.08:10:04.23#ibcon#read 4, iclass 4, count 0 2006.173.08:10:04.23#ibcon#about to read 5, iclass 4, count 0 2006.173.08:10:04.23#ibcon#read 5, iclass 4, count 0 2006.173.08:10:04.23#ibcon#about to read 6, iclass 4, count 0 2006.173.08:10:04.23#ibcon#read 6, iclass 4, count 0 2006.173.08:10:04.23#ibcon#end of sib2, iclass 4, count 0 2006.173.08:10:04.23#ibcon#*mode == 0, iclass 4, count 0 2006.173.08:10:04.23#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.08:10:04.23#ibcon#[27=USB\r\n] 2006.173.08:10:04.23#ibcon#*before write, iclass 4, count 0 2006.173.08:10:04.23#ibcon#enter sib2, iclass 4, count 0 2006.173.08:10:04.23#ibcon#flushed, iclass 4, count 0 2006.173.08:10:04.23#ibcon#about to write, iclass 4, count 0 2006.173.08:10:04.23#ibcon#wrote, iclass 4, count 0 2006.173.08:10:04.23#ibcon#about to read 3, iclass 4, count 0 2006.173.08:10:04.26#ibcon#read 3, iclass 4, count 0 2006.173.08:10:04.26#ibcon#about to read 4, iclass 4, count 0 2006.173.08:10:04.26#ibcon#read 4, iclass 4, count 0 2006.173.08:10:04.26#ibcon#about to read 5, iclass 4, count 0 2006.173.08:10:04.26#ibcon#read 5, iclass 4, count 0 2006.173.08:10:04.26#ibcon#about to read 6, iclass 4, count 0 2006.173.08:10:04.26#ibcon#read 6, iclass 4, count 0 2006.173.08:10:04.26#ibcon#end of sib2, iclass 4, count 0 2006.173.08:10:04.26#ibcon#*after write, iclass 4, count 0 2006.173.08:10:04.26#ibcon#*before return 0, iclass 4, count 0 2006.173.08:10:04.26#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.08:10:04.26#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.08:10:04.26#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.08:10:04.26#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.08:10:04.26$vck44/vblo=5,709.99 2006.173.08:10:04.26#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.08:10:04.26#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.08:10:04.26#ibcon#ireg 17 cls_cnt 0 2006.173.08:10:04.26#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.08:10:04.26#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.08:10:04.26#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.08:10:04.26#ibcon#enter wrdev, iclass 6, count 0 2006.173.08:10:04.26#ibcon#first serial, iclass 6, count 0 2006.173.08:10:04.26#ibcon#enter sib2, iclass 6, count 0 2006.173.08:10:04.26#ibcon#flushed, iclass 6, count 0 2006.173.08:10:04.26#ibcon#about to write, iclass 6, count 0 2006.173.08:10:04.26#ibcon#wrote, iclass 6, count 0 2006.173.08:10:04.26#ibcon#about to read 3, iclass 6, count 0 2006.173.08:10:04.28#ibcon#read 3, iclass 6, count 0 2006.173.08:10:04.28#ibcon#about to read 4, iclass 6, count 0 2006.173.08:10:04.28#ibcon#read 4, iclass 6, count 0 2006.173.08:10:04.28#ibcon#about to read 5, iclass 6, count 0 2006.173.08:10:04.28#ibcon#read 5, iclass 6, count 0 2006.173.08:10:04.28#ibcon#about to read 6, iclass 6, count 0 2006.173.08:10:04.28#ibcon#read 6, iclass 6, count 0 2006.173.08:10:04.28#ibcon#end of sib2, iclass 6, count 0 2006.173.08:10:04.28#ibcon#*mode == 0, iclass 6, count 0 2006.173.08:10:04.28#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.08:10:04.28#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.08:10:04.28#ibcon#*before write, iclass 6, count 0 2006.173.08:10:04.28#ibcon#enter sib2, iclass 6, count 0 2006.173.08:10:04.28#ibcon#flushed, iclass 6, count 0 2006.173.08:10:04.28#ibcon#about to write, iclass 6, count 0 2006.173.08:10:04.28#ibcon#wrote, iclass 6, count 0 2006.173.08:10:04.28#ibcon#about to read 3, iclass 6, count 0 2006.173.08:10:04.32#ibcon#read 3, iclass 6, count 0 2006.173.08:10:04.32#ibcon#about to read 4, iclass 6, count 0 2006.173.08:10:04.32#ibcon#read 4, iclass 6, count 0 2006.173.08:10:04.32#ibcon#about to read 5, iclass 6, count 0 2006.173.08:10:04.32#ibcon#read 5, iclass 6, count 0 2006.173.08:10:04.32#ibcon#about to read 6, iclass 6, count 0 2006.173.08:10:04.32#ibcon#read 6, iclass 6, count 0 2006.173.08:10:04.32#ibcon#end of sib2, iclass 6, count 0 2006.173.08:10:04.32#ibcon#*after write, iclass 6, count 0 2006.173.08:10:04.32#ibcon#*before return 0, iclass 6, count 0 2006.173.08:10:04.32#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.08:10:04.32#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.08:10:04.32#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.08:10:04.32#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.08:10:04.32$vck44/vb=5,4 2006.173.08:10:04.32#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.08:10:04.32#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.08:10:04.32#ibcon#ireg 11 cls_cnt 2 2006.173.08:10:04.32#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.08:10:04.38#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.08:10:04.38#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.08:10:04.38#ibcon#enter wrdev, iclass 10, count 2 2006.173.08:10:04.38#ibcon#first serial, iclass 10, count 2 2006.173.08:10:04.38#ibcon#enter sib2, iclass 10, count 2 2006.173.08:10:04.38#ibcon#flushed, iclass 10, count 2 2006.173.08:10:04.38#ibcon#about to write, iclass 10, count 2 2006.173.08:10:04.38#ibcon#wrote, iclass 10, count 2 2006.173.08:10:04.38#ibcon#about to read 3, iclass 10, count 2 2006.173.08:10:04.40#ibcon#read 3, iclass 10, count 2 2006.173.08:10:04.40#ibcon#about to read 4, iclass 10, count 2 2006.173.08:10:04.40#ibcon#read 4, iclass 10, count 2 2006.173.08:10:04.40#ibcon#about to read 5, iclass 10, count 2 2006.173.08:10:04.40#ibcon#read 5, iclass 10, count 2 2006.173.08:10:04.40#ibcon#about to read 6, iclass 10, count 2 2006.173.08:10:04.40#ibcon#read 6, iclass 10, count 2 2006.173.08:10:04.40#ibcon#end of sib2, iclass 10, count 2 2006.173.08:10:04.40#ibcon#*mode == 0, iclass 10, count 2 2006.173.08:10:04.40#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.08:10:04.40#ibcon#[27=AT05-04\r\n] 2006.173.08:10:04.40#ibcon#*before write, iclass 10, count 2 2006.173.08:10:04.40#ibcon#enter sib2, iclass 10, count 2 2006.173.08:10:04.40#ibcon#flushed, iclass 10, count 2 2006.173.08:10:04.40#ibcon#about to write, iclass 10, count 2 2006.173.08:10:04.40#ibcon#wrote, iclass 10, count 2 2006.173.08:10:04.40#ibcon#about to read 3, iclass 10, count 2 2006.173.08:10:04.43#ibcon#read 3, iclass 10, count 2 2006.173.08:10:04.43#ibcon#about to read 4, iclass 10, count 2 2006.173.08:10:04.43#ibcon#read 4, iclass 10, count 2 2006.173.08:10:04.43#ibcon#about to read 5, iclass 10, count 2 2006.173.08:10:04.43#ibcon#read 5, iclass 10, count 2 2006.173.08:10:04.43#ibcon#about to read 6, iclass 10, count 2 2006.173.08:10:04.43#ibcon#read 6, iclass 10, count 2 2006.173.08:10:04.43#ibcon#end of sib2, iclass 10, count 2 2006.173.08:10:04.43#ibcon#*after write, iclass 10, count 2 2006.173.08:10:04.43#ibcon#*before return 0, iclass 10, count 2 2006.173.08:10:04.43#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.08:10:04.43#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.08:10:04.43#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.08:10:04.43#ibcon#ireg 7 cls_cnt 0 2006.173.08:10:04.43#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.08:10:04.55#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.08:10:04.55#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.08:10:04.55#ibcon#enter wrdev, iclass 10, count 0 2006.173.08:10:04.55#ibcon#first serial, iclass 10, count 0 2006.173.08:10:04.55#ibcon#enter sib2, iclass 10, count 0 2006.173.08:10:04.55#ibcon#flushed, iclass 10, count 0 2006.173.08:10:04.55#ibcon#about to write, iclass 10, count 0 2006.173.08:10:04.55#ibcon#wrote, iclass 10, count 0 2006.173.08:10:04.55#ibcon#about to read 3, iclass 10, count 0 2006.173.08:10:04.57#ibcon#read 3, iclass 10, count 0 2006.173.08:10:04.57#ibcon#about to read 4, iclass 10, count 0 2006.173.08:10:04.57#ibcon#read 4, iclass 10, count 0 2006.173.08:10:04.57#ibcon#about to read 5, iclass 10, count 0 2006.173.08:10:04.57#ibcon#read 5, iclass 10, count 0 2006.173.08:10:04.57#ibcon#about to read 6, iclass 10, count 0 2006.173.08:10:04.57#ibcon#read 6, iclass 10, count 0 2006.173.08:10:04.57#ibcon#end of sib2, iclass 10, count 0 2006.173.08:10:04.57#ibcon#*mode == 0, iclass 10, count 0 2006.173.08:10:04.57#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.08:10:04.57#ibcon#[27=USB\r\n] 2006.173.08:10:04.57#ibcon#*before write, iclass 10, count 0 2006.173.08:10:04.57#ibcon#enter sib2, iclass 10, count 0 2006.173.08:10:04.57#ibcon#flushed, iclass 10, count 0 2006.173.08:10:04.57#ibcon#about to write, iclass 10, count 0 2006.173.08:10:04.57#ibcon#wrote, iclass 10, count 0 2006.173.08:10:04.57#ibcon#about to read 3, iclass 10, count 0 2006.173.08:10:04.60#ibcon#read 3, iclass 10, count 0 2006.173.08:10:04.60#ibcon#about to read 4, iclass 10, count 0 2006.173.08:10:04.60#ibcon#read 4, iclass 10, count 0 2006.173.08:10:04.60#ibcon#about to read 5, iclass 10, count 0 2006.173.08:10:04.60#ibcon#read 5, iclass 10, count 0 2006.173.08:10:04.60#ibcon#about to read 6, iclass 10, count 0 2006.173.08:10:04.60#ibcon#read 6, iclass 10, count 0 2006.173.08:10:04.60#ibcon#end of sib2, iclass 10, count 0 2006.173.08:10:04.60#ibcon#*after write, iclass 10, count 0 2006.173.08:10:04.60#ibcon#*before return 0, iclass 10, count 0 2006.173.08:10:04.60#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.08:10:04.60#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.08:10:04.60#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.08:10:04.60#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.08:10:04.60$vck44/vblo=6,719.99 2006.173.08:10:04.60#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.08:10:04.60#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.08:10:04.60#ibcon#ireg 17 cls_cnt 0 2006.173.08:10:04.60#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.08:10:04.60#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.08:10:04.60#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.08:10:04.60#ibcon#enter wrdev, iclass 12, count 0 2006.173.08:10:04.60#ibcon#first serial, iclass 12, count 0 2006.173.08:10:04.60#ibcon#enter sib2, iclass 12, count 0 2006.173.08:10:04.60#ibcon#flushed, iclass 12, count 0 2006.173.08:10:04.60#ibcon#about to write, iclass 12, count 0 2006.173.08:10:04.60#ibcon#wrote, iclass 12, count 0 2006.173.08:10:04.60#ibcon#about to read 3, iclass 12, count 0 2006.173.08:10:04.62#ibcon#read 3, iclass 12, count 0 2006.173.08:10:04.62#ibcon#about to read 4, iclass 12, count 0 2006.173.08:10:04.62#ibcon#read 4, iclass 12, count 0 2006.173.08:10:04.62#ibcon#about to read 5, iclass 12, count 0 2006.173.08:10:04.62#ibcon#read 5, iclass 12, count 0 2006.173.08:10:04.62#ibcon#about to read 6, iclass 12, count 0 2006.173.08:10:04.62#ibcon#read 6, iclass 12, count 0 2006.173.08:10:04.62#ibcon#end of sib2, iclass 12, count 0 2006.173.08:10:04.62#ibcon#*mode == 0, iclass 12, count 0 2006.173.08:10:04.62#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.08:10:04.62#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.08:10:04.62#ibcon#*before write, iclass 12, count 0 2006.173.08:10:04.62#ibcon#enter sib2, iclass 12, count 0 2006.173.08:10:04.62#ibcon#flushed, iclass 12, count 0 2006.173.08:10:04.62#ibcon#about to write, iclass 12, count 0 2006.173.08:10:04.62#ibcon#wrote, iclass 12, count 0 2006.173.08:10:04.62#ibcon#about to read 3, iclass 12, count 0 2006.173.08:10:04.66#ibcon#read 3, iclass 12, count 0 2006.173.08:10:04.66#ibcon#about to read 4, iclass 12, count 0 2006.173.08:10:04.66#ibcon#read 4, iclass 12, count 0 2006.173.08:10:04.66#ibcon#about to read 5, iclass 12, count 0 2006.173.08:10:04.66#ibcon#read 5, iclass 12, count 0 2006.173.08:10:04.66#ibcon#about to read 6, iclass 12, count 0 2006.173.08:10:04.66#ibcon#read 6, iclass 12, count 0 2006.173.08:10:04.66#ibcon#end of sib2, iclass 12, count 0 2006.173.08:10:04.66#ibcon#*after write, iclass 12, count 0 2006.173.08:10:04.66#ibcon#*before return 0, iclass 12, count 0 2006.173.08:10:04.66#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.08:10:04.66#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.08:10:04.66#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.08:10:04.66#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.08:10:04.66$vck44/vb=6,4 2006.173.08:10:04.66#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.08:10:04.66#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.08:10:04.66#ibcon#ireg 11 cls_cnt 2 2006.173.08:10:04.66#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.08:10:04.72#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.08:10:04.72#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.08:10:04.72#ibcon#enter wrdev, iclass 14, count 2 2006.173.08:10:04.72#ibcon#first serial, iclass 14, count 2 2006.173.08:10:04.72#ibcon#enter sib2, iclass 14, count 2 2006.173.08:10:04.72#ibcon#flushed, iclass 14, count 2 2006.173.08:10:04.72#ibcon#about to write, iclass 14, count 2 2006.173.08:10:04.72#ibcon#wrote, iclass 14, count 2 2006.173.08:10:04.72#ibcon#about to read 3, iclass 14, count 2 2006.173.08:10:04.74#ibcon#read 3, iclass 14, count 2 2006.173.08:10:04.74#ibcon#about to read 4, iclass 14, count 2 2006.173.08:10:04.74#ibcon#read 4, iclass 14, count 2 2006.173.08:10:04.74#ibcon#about to read 5, iclass 14, count 2 2006.173.08:10:04.74#ibcon#read 5, iclass 14, count 2 2006.173.08:10:04.74#ibcon#about to read 6, iclass 14, count 2 2006.173.08:10:04.74#ibcon#read 6, iclass 14, count 2 2006.173.08:10:04.74#ibcon#end of sib2, iclass 14, count 2 2006.173.08:10:04.74#ibcon#*mode == 0, iclass 14, count 2 2006.173.08:10:04.74#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.08:10:04.74#ibcon#[27=AT06-04\r\n] 2006.173.08:10:04.74#ibcon#*before write, iclass 14, count 2 2006.173.08:10:04.74#ibcon#enter sib2, iclass 14, count 2 2006.173.08:10:04.74#ibcon#flushed, iclass 14, count 2 2006.173.08:10:04.74#ibcon#about to write, iclass 14, count 2 2006.173.08:10:04.74#ibcon#wrote, iclass 14, count 2 2006.173.08:10:04.74#ibcon#about to read 3, iclass 14, count 2 2006.173.08:10:04.77#ibcon#read 3, iclass 14, count 2 2006.173.08:10:04.77#ibcon#about to read 4, iclass 14, count 2 2006.173.08:10:04.77#ibcon#read 4, iclass 14, count 2 2006.173.08:10:04.77#ibcon#about to read 5, iclass 14, count 2 2006.173.08:10:04.77#ibcon#read 5, iclass 14, count 2 2006.173.08:10:04.77#ibcon#about to read 6, iclass 14, count 2 2006.173.08:10:04.77#ibcon#read 6, iclass 14, count 2 2006.173.08:10:04.77#ibcon#end of sib2, iclass 14, count 2 2006.173.08:10:04.77#ibcon#*after write, iclass 14, count 2 2006.173.08:10:04.77#ibcon#*before return 0, iclass 14, count 2 2006.173.08:10:04.77#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.08:10:04.77#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.08:10:04.77#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.08:10:04.77#ibcon#ireg 7 cls_cnt 0 2006.173.08:10:04.77#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.08:10:04.89#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.08:10:04.89#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.08:10:04.89#ibcon#enter wrdev, iclass 14, count 0 2006.173.08:10:04.89#ibcon#first serial, iclass 14, count 0 2006.173.08:10:04.89#ibcon#enter sib2, iclass 14, count 0 2006.173.08:10:04.89#ibcon#flushed, iclass 14, count 0 2006.173.08:10:04.89#ibcon#about to write, iclass 14, count 0 2006.173.08:10:04.89#ibcon#wrote, iclass 14, count 0 2006.173.08:10:04.89#ibcon#about to read 3, iclass 14, count 0 2006.173.08:10:04.91#ibcon#read 3, iclass 14, count 0 2006.173.08:10:04.91#ibcon#about to read 4, iclass 14, count 0 2006.173.08:10:04.91#ibcon#read 4, iclass 14, count 0 2006.173.08:10:04.91#ibcon#about to read 5, iclass 14, count 0 2006.173.08:10:04.91#ibcon#read 5, iclass 14, count 0 2006.173.08:10:04.91#ibcon#about to read 6, iclass 14, count 0 2006.173.08:10:04.91#ibcon#read 6, iclass 14, count 0 2006.173.08:10:04.91#ibcon#end of sib2, iclass 14, count 0 2006.173.08:10:04.91#ibcon#*mode == 0, iclass 14, count 0 2006.173.08:10:04.91#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.08:10:04.91#ibcon#[27=USB\r\n] 2006.173.08:10:04.91#ibcon#*before write, iclass 14, count 0 2006.173.08:10:04.91#ibcon#enter sib2, iclass 14, count 0 2006.173.08:10:04.91#ibcon#flushed, iclass 14, count 0 2006.173.08:10:04.91#ibcon#about to write, iclass 14, count 0 2006.173.08:10:04.91#ibcon#wrote, iclass 14, count 0 2006.173.08:10:04.91#ibcon#about to read 3, iclass 14, count 0 2006.173.08:10:04.94#ibcon#read 3, iclass 14, count 0 2006.173.08:10:04.94#ibcon#about to read 4, iclass 14, count 0 2006.173.08:10:04.94#ibcon#read 4, iclass 14, count 0 2006.173.08:10:04.94#ibcon#about to read 5, iclass 14, count 0 2006.173.08:10:04.94#ibcon#read 5, iclass 14, count 0 2006.173.08:10:04.94#ibcon#about to read 6, iclass 14, count 0 2006.173.08:10:04.94#ibcon#read 6, iclass 14, count 0 2006.173.08:10:04.94#ibcon#end of sib2, iclass 14, count 0 2006.173.08:10:04.94#ibcon#*after write, iclass 14, count 0 2006.173.08:10:04.94#ibcon#*before return 0, iclass 14, count 0 2006.173.08:10:04.94#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.08:10:04.94#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.08:10:04.94#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.08:10:04.94#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.08:10:04.94$vck44/vblo=7,734.99 2006.173.08:10:04.94#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.08:10:04.94#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.08:10:04.94#ibcon#ireg 17 cls_cnt 0 2006.173.08:10:04.94#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.08:10:04.94#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.08:10:04.94#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.08:10:04.94#ibcon#enter wrdev, iclass 16, count 0 2006.173.08:10:04.94#ibcon#first serial, iclass 16, count 0 2006.173.08:10:04.94#ibcon#enter sib2, iclass 16, count 0 2006.173.08:10:04.94#ibcon#flushed, iclass 16, count 0 2006.173.08:10:04.94#ibcon#about to write, iclass 16, count 0 2006.173.08:10:04.94#ibcon#wrote, iclass 16, count 0 2006.173.08:10:04.94#ibcon#about to read 3, iclass 16, count 0 2006.173.08:10:04.96#ibcon#read 3, iclass 16, count 0 2006.173.08:10:04.96#ibcon#about to read 4, iclass 16, count 0 2006.173.08:10:04.96#ibcon#read 4, iclass 16, count 0 2006.173.08:10:04.96#ibcon#about to read 5, iclass 16, count 0 2006.173.08:10:04.96#ibcon#read 5, iclass 16, count 0 2006.173.08:10:04.96#ibcon#about to read 6, iclass 16, count 0 2006.173.08:10:04.96#ibcon#read 6, iclass 16, count 0 2006.173.08:10:04.96#ibcon#end of sib2, iclass 16, count 0 2006.173.08:10:04.96#ibcon#*mode == 0, iclass 16, count 0 2006.173.08:10:04.96#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.08:10:04.96#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.08:10:04.96#ibcon#*before write, iclass 16, count 0 2006.173.08:10:04.96#ibcon#enter sib2, iclass 16, count 0 2006.173.08:10:04.96#ibcon#flushed, iclass 16, count 0 2006.173.08:10:04.96#ibcon#about to write, iclass 16, count 0 2006.173.08:10:04.96#ibcon#wrote, iclass 16, count 0 2006.173.08:10:04.96#ibcon#about to read 3, iclass 16, count 0 2006.173.08:10:05.00#ibcon#read 3, iclass 16, count 0 2006.173.08:10:05.00#ibcon#about to read 4, iclass 16, count 0 2006.173.08:10:05.00#ibcon#read 4, iclass 16, count 0 2006.173.08:10:05.00#ibcon#about to read 5, iclass 16, count 0 2006.173.08:10:05.00#ibcon#read 5, iclass 16, count 0 2006.173.08:10:05.00#ibcon#about to read 6, iclass 16, count 0 2006.173.08:10:05.00#ibcon#read 6, iclass 16, count 0 2006.173.08:10:05.00#ibcon#end of sib2, iclass 16, count 0 2006.173.08:10:05.00#ibcon#*after write, iclass 16, count 0 2006.173.08:10:05.00#ibcon#*before return 0, iclass 16, count 0 2006.173.08:10:05.00#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.08:10:05.00#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.08:10:05.00#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.08:10:05.00#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.08:10:05.00$vck44/vb=7,4 2006.173.08:10:05.00#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.08:10:05.00#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.08:10:05.00#ibcon#ireg 11 cls_cnt 2 2006.173.08:10:05.00#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.08:10:05.06#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.08:10:05.06#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.08:10:05.06#ibcon#enter wrdev, iclass 18, count 2 2006.173.08:10:05.06#ibcon#first serial, iclass 18, count 2 2006.173.08:10:05.06#ibcon#enter sib2, iclass 18, count 2 2006.173.08:10:05.06#ibcon#flushed, iclass 18, count 2 2006.173.08:10:05.06#ibcon#about to write, iclass 18, count 2 2006.173.08:10:05.06#ibcon#wrote, iclass 18, count 2 2006.173.08:10:05.06#ibcon#about to read 3, iclass 18, count 2 2006.173.08:10:05.08#ibcon#read 3, iclass 18, count 2 2006.173.08:10:05.08#ibcon#about to read 4, iclass 18, count 2 2006.173.08:10:05.08#ibcon#read 4, iclass 18, count 2 2006.173.08:10:05.08#ibcon#about to read 5, iclass 18, count 2 2006.173.08:10:05.08#ibcon#read 5, iclass 18, count 2 2006.173.08:10:05.08#ibcon#about to read 6, iclass 18, count 2 2006.173.08:10:05.08#ibcon#read 6, iclass 18, count 2 2006.173.08:10:05.08#ibcon#end of sib2, iclass 18, count 2 2006.173.08:10:05.08#ibcon#*mode == 0, iclass 18, count 2 2006.173.08:10:05.08#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.08:10:05.08#ibcon#[27=AT07-04\r\n] 2006.173.08:10:05.08#ibcon#*before write, iclass 18, count 2 2006.173.08:10:05.08#ibcon#enter sib2, iclass 18, count 2 2006.173.08:10:05.08#ibcon#flushed, iclass 18, count 2 2006.173.08:10:05.08#ibcon#about to write, iclass 18, count 2 2006.173.08:10:05.08#ibcon#wrote, iclass 18, count 2 2006.173.08:10:05.08#ibcon#about to read 3, iclass 18, count 2 2006.173.08:10:05.11#ibcon#read 3, iclass 18, count 2 2006.173.08:10:05.11#ibcon#about to read 4, iclass 18, count 2 2006.173.08:10:05.11#ibcon#read 4, iclass 18, count 2 2006.173.08:10:05.11#ibcon#about to read 5, iclass 18, count 2 2006.173.08:10:05.11#ibcon#read 5, iclass 18, count 2 2006.173.08:10:05.11#ibcon#about to read 6, iclass 18, count 2 2006.173.08:10:05.11#ibcon#read 6, iclass 18, count 2 2006.173.08:10:05.11#ibcon#end of sib2, iclass 18, count 2 2006.173.08:10:05.11#ibcon#*after write, iclass 18, count 2 2006.173.08:10:05.11#ibcon#*before return 0, iclass 18, count 2 2006.173.08:10:05.11#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.08:10:05.11#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.08:10:05.11#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.08:10:05.11#ibcon#ireg 7 cls_cnt 0 2006.173.08:10:05.11#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.08:10:05.23#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.08:10:05.23#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.08:10:05.23#ibcon#enter wrdev, iclass 18, count 0 2006.173.08:10:05.23#ibcon#first serial, iclass 18, count 0 2006.173.08:10:05.23#ibcon#enter sib2, iclass 18, count 0 2006.173.08:10:05.23#ibcon#flushed, iclass 18, count 0 2006.173.08:10:05.23#ibcon#about to write, iclass 18, count 0 2006.173.08:10:05.23#ibcon#wrote, iclass 18, count 0 2006.173.08:10:05.23#ibcon#about to read 3, iclass 18, count 0 2006.173.08:10:05.25#ibcon#read 3, iclass 18, count 0 2006.173.08:10:05.25#ibcon#about to read 4, iclass 18, count 0 2006.173.08:10:05.25#ibcon#read 4, iclass 18, count 0 2006.173.08:10:05.25#ibcon#about to read 5, iclass 18, count 0 2006.173.08:10:05.25#ibcon#read 5, iclass 18, count 0 2006.173.08:10:05.25#ibcon#about to read 6, iclass 18, count 0 2006.173.08:10:05.25#ibcon#read 6, iclass 18, count 0 2006.173.08:10:05.25#ibcon#end of sib2, iclass 18, count 0 2006.173.08:10:05.25#ibcon#*mode == 0, iclass 18, count 0 2006.173.08:10:05.25#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.08:10:05.25#ibcon#[27=USB\r\n] 2006.173.08:10:05.25#ibcon#*before write, iclass 18, count 0 2006.173.08:10:05.25#ibcon#enter sib2, iclass 18, count 0 2006.173.08:10:05.25#ibcon#flushed, iclass 18, count 0 2006.173.08:10:05.25#ibcon#about to write, iclass 18, count 0 2006.173.08:10:05.25#ibcon#wrote, iclass 18, count 0 2006.173.08:10:05.25#ibcon#about to read 3, iclass 18, count 0 2006.173.08:10:05.28#ibcon#read 3, iclass 18, count 0 2006.173.08:10:05.28#ibcon#about to read 4, iclass 18, count 0 2006.173.08:10:05.28#ibcon#read 4, iclass 18, count 0 2006.173.08:10:05.28#ibcon#about to read 5, iclass 18, count 0 2006.173.08:10:05.28#ibcon#read 5, iclass 18, count 0 2006.173.08:10:05.28#ibcon#about to read 6, iclass 18, count 0 2006.173.08:10:05.28#ibcon#read 6, iclass 18, count 0 2006.173.08:10:05.28#ibcon#end of sib2, iclass 18, count 0 2006.173.08:10:05.28#ibcon#*after write, iclass 18, count 0 2006.173.08:10:05.28#ibcon#*before return 0, iclass 18, count 0 2006.173.08:10:05.28#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.08:10:05.28#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.08:10:05.28#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.08:10:05.28#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.08:10:05.28$vck44/vblo=8,744.99 2006.173.08:10:05.28#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.08:10:05.28#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.08:10:05.28#ibcon#ireg 17 cls_cnt 0 2006.173.08:10:05.28#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.08:10:05.28#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.08:10:05.28#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.08:10:05.28#ibcon#enter wrdev, iclass 20, count 0 2006.173.08:10:05.28#ibcon#first serial, iclass 20, count 0 2006.173.08:10:05.28#ibcon#enter sib2, iclass 20, count 0 2006.173.08:10:05.28#ibcon#flushed, iclass 20, count 0 2006.173.08:10:05.28#ibcon#about to write, iclass 20, count 0 2006.173.08:10:05.28#ibcon#wrote, iclass 20, count 0 2006.173.08:10:05.28#ibcon#about to read 3, iclass 20, count 0 2006.173.08:10:05.30#ibcon#read 3, iclass 20, count 0 2006.173.08:10:05.30#ibcon#about to read 4, iclass 20, count 0 2006.173.08:10:05.30#ibcon#read 4, iclass 20, count 0 2006.173.08:10:05.30#ibcon#about to read 5, iclass 20, count 0 2006.173.08:10:05.30#ibcon#read 5, iclass 20, count 0 2006.173.08:10:05.30#ibcon#about to read 6, iclass 20, count 0 2006.173.08:10:05.30#ibcon#read 6, iclass 20, count 0 2006.173.08:10:05.30#ibcon#end of sib2, iclass 20, count 0 2006.173.08:10:05.30#ibcon#*mode == 0, iclass 20, count 0 2006.173.08:10:05.30#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.08:10:05.30#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.08:10:05.30#ibcon#*before write, iclass 20, count 0 2006.173.08:10:05.30#ibcon#enter sib2, iclass 20, count 0 2006.173.08:10:05.30#ibcon#flushed, iclass 20, count 0 2006.173.08:10:05.30#ibcon#about to write, iclass 20, count 0 2006.173.08:10:05.30#ibcon#wrote, iclass 20, count 0 2006.173.08:10:05.30#ibcon#about to read 3, iclass 20, count 0 2006.173.08:10:05.34#ibcon#read 3, iclass 20, count 0 2006.173.08:10:05.34#ibcon#about to read 4, iclass 20, count 0 2006.173.08:10:05.34#ibcon#read 4, iclass 20, count 0 2006.173.08:10:05.34#ibcon#about to read 5, iclass 20, count 0 2006.173.08:10:05.34#ibcon#read 5, iclass 20, count 0 2006.173.08:10:05.34#ibcon#about to read 6, iclass 20, count 0 2006.173.08:10:05.34#ibcon#read 6, iclass 20, count 0 2006.173.08:10:05.34#ibcon#end of sib2, iclass 20, count 0 2006.173.08:10:05.34#ibcon#*after write, iclass 20, count 0 2006.173.08:10:05.34#ibcon#*before return 0, iclass 20, count 0 2006.173.08:10:05.34#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.08:10:05.34#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.08:10:05.34#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.08:10:05.34#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.08:10:05.34$vck44/vb=8,4 2006.173.08:10:05.34#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.08:10:05.34#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.08:10:05.34#ibcon#ireg 11 cls_cnt 2 2006.173.08:10:05.34#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.08:10:05.40#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.08:10:05.40#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.08:10:05.40#ibcon#enter wrdev, iclass 22, count 2 2006.173.08:10:05.40#ibcon#first serial, iclass 22, count 2 2006.173.08:10:05.40#ibcon#enter sib2, iclass 22, count 2 2006.173.08:10:05.40#ibcon#flushed, iclass 22, count 2 2006.173.08:10:05.40#ibcon#about to write, iclass 22, count 2 2006.173.08:10:05.40#ibcon#wrote, iclass 22, count 2 2006.173.08:10:05.40#ibcon#about to read 3, iclass 22, count 2 2006.173.08:10:05.42#ibcon#read 3, iclass 22, count 2 2006.173.08:10:05.42#ibcon#about to read 4, iclass 22, count 2 2006.173.08:10:05.42#ibcon#read 4, iclass 22, count 2 2006.173.08:10:05.42#ibcon#about to read 5, iclass 22, count 2 2006.173.08:10:05.42#ibcon#read 5, iclass 22, count 2 2006.173.08:10:05.42#ibcon#about to read 6, iclass 22, count 2 2006.173.08:10:05.42#ibcon#read 6, iclass 22, count 2 2006.173.08:10:05.42#ibcon#end of sib2, iclass 22, count 2 2006.173.08:10:05.42#ibcon#*mode == 0, iclass 22, count 2 2006.173.08:10:05.42#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.08:10:05.42#ibcon#[27=AT08-04\r\n] 2006.173.08:10:05.42#ibcon#*before write, iclass 22, count 2 2006.173.08:10:05.42#ibcon#enter sib2, iclass 22, count 2 2006.173.08:10:05.42#ibcon#flushed, iclass 22, count 2 2006.173.08:10:05.42#ibcon#about to write, iclass 22, count 2 2006.173.08:10:05.42#ibcon#wrote, iclass 22, count 2 2006.173.08:10:05.42#ibcon#about to read 3, iclass 22, count 2 2006.173.08:10:05.45#ibcon#read 3, iclass 22, count 2 2006.173.08:10:05.45#ibcon#about to read 4, iclass 22, count 2 2006.173.08:10:05.45#ibcon#read 4, iclass 22, count 2 2006.173.08:10:05.45#ibcon#about to read 5, iclass 22, count 2 2006.173.08:10:05.45#ibcon#read 5, iclass 22, count 2 2006.173.08:10:05.45#ibcon#about to read 6, iclass 22, count 2 2006.173.08:10:05.45#ibcon#read 6, iclass 22, count 2 2006.173.08:10:05.45#ibcon#end of sib2, iclass 22, count 2 2006.173.08:10:05.45#ibcon#*after write, iclass 22, count 2 2006.173.08:10:05.45#ibcon#*before return 0, iclass 22, count 2 2006.173.08:10:05.45#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.08:10:05.45#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.08:10:05.45#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.08:10:05.45#ibcon#ireg 7 cls_cnt 0 2006.173.08:10:05.45#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.08:10:05.57#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.08:10:05.57#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.08:10:05.57#ibcon#enter wrdev, iclass 22, count 0 2006.173.08:10:05.57#ibcon#first serial, iclass 22, count 0 2006.173.08:10:05.57#ibcon#enter sib2, iclass 22, count 0 2006.173.08:10:05.57#ibcon#flushed, iclass 22, count 0 2006.173.08:10:05.57#ibcon#about to write, iclass 22, count 0 2006.173.08:10:05.57#ibcon#wrote, iclass 22, count 0 2006.173.08:10:05.57#ibcon#about to read 3, iclass 22, count 0 2006.173.08:10:05.59#ibcon#read 3, iclass 22, count 0 2006.173.08:10:05.59#ibcon#about to read 4, iclass 22, count 0 2006.173.08:10:05.59#ibcon#read 4, iclass 22, count 0 2006.173.08:10:05.59#ibcon#about to read 5, iclass 22, count 0 2006.173.08:10:05.59#ibcon#read 5, iclass 22, count 0 2006.173.08:10:05.59#ibcon#about to read 6, iclass 22, count 0 2006.173.08:10:05.59#ibcon#read 6, iclass 22, count 0 2006.173.08:10:05.59#ibcon#end of sib2, iclass 22, count 0 2006.173.08:10:05.59#ibcon#*mode == 0, iclass 22, count 0 2006.173.08:10:05.59#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.08:10:05.59#ibcon#[27=USB\r\n] 2006.173.08:10:05.59#ibcon#*before write, iclass 22, count 0 2006.173.08:10:05.59#ibcon#enter sib2, iclass 22, count 0 2006.173.08:10:05.59#ibcon#flushed, iclass 22, count 0 2006.173.08:10:05.59#ibcon#about to write, iclass 22, count 0 2006.173.08:10:05.59#ibcon#wrote, iclass 22, count 0 2006.173.08:10:05.59#ibcon#about to read 3, iclass 22, count 0 2006.173.08:10:05.62#ibcon#read 3, iclass 22, count 0 2006.173.08:10:05.62#ibcon#about to read 4, iclass 22, count 0 2006.173.08:10:05.62#ibcon#read 4, iclass 22, count 0 2006.173.08:10:05.62#ibcon#about to read 5, iclass 22, count 0 2006.173.08:10:05.62#ibcon#read 5, iclass 22, count 0 2006.173.08:10:05.62#ibcon#about to read 6, iclass 22, count 0 2006.173.08:10:05.62#ibcon#read 6, iclass 22, count 0 2006.173.08:10:05.62#ibcon#end of sib2, iclass 22, count 0 2006.173.08:10:05.62#ibcon#*after write, iclass 22, count 0 2006.173.08:10:05.62#ibcon#*before return 0, iclass 22, count 0 2006.173.08:10:05.62#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.08:10:05.62#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.08:10:05.62#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.08:10:05.62#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.08:10:05.62$vck44/vabw=wide 2006.173.08:10:05.62#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.08:10:05.62#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.08:10:05.62#ibcon#ireg 8 cls_cnt 0 2006.173.08:10:05.62#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.08:10:05.62#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.08:10:05.62#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.08:10:05.62#ibcon#enter wrdev, iclass 24, count 0 2006.173.08:10:05.62#ibcon#first serial, iclass 24, count 0 2006.173.08:10:05.62#ibcon#enter sib2, iclass 24, count 0 2006.173.08:10:05.62#ibcon#flushed, iclass 24, count 0 2006.173.08:10:05.62#ibcon#about to write, iclass 24, count 0 2006.173.08:10:05.62#ibcon#wrote, iclass 24, count 0 2006.173.08:10:05.62#ibcon#about to read 3, iclass 24, count 0 2006.173.08:10:05.64#ibcon#read 3, iclass 24, count 0 2006.173.08:10:05.64#ibcon#about to read 4, iclass 24, count 0 2006.173.08:10:05.64#ibcon#read 4, iclass 24, count 0 2006.173.08:10:05.64#ibcon#about to read 5, iclass 24, count 0 2006.173.08:10:05.64#ibcon#read 5, iclass 24, count 0 2006.173.08:10:05.64#ibcon#about to read 6, iclass 24, count 0 2006.173.08:10:05.64#ibcon#read 6, iclass 24, count 0 2006.173.08:10:05.64#ibcon#end of sib2, iclass 24, count 0 2006.173.08:10:05.64#ibcon#*mode == 0, iclass 24, count 0 2006.173.08:10:05.64#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.08:10:05.64#ibcon#[25=BW32\r\n] 2006.173.08:10:05.64#ibcon#*before write, iclass 24, count 0 2006.173.08:10:05.64#ibcon#enter sib2, iclass 24, count 0 2006.173.08:10:05.64#ibcon#flushed, iclass 24, count 0 2006.173.08:10:05.64#ibcon#about to write, iclass 24, count 0 2006.173.08:10:05.64#ibcon#wrote, iclass 24, count 0 2006.173.08:10:05.64#ibcon#about to read 3, iclass 24, count 0 2006.173.08:10:05.67#ibcon#read 3, iclass 24, count 0 2006.173.08:10:05.67#ibcon#about to read 4, iclass 24, count 0 2006.173.08:10:05.67#ibcon#read 4, iclass 24, count 0 2006.173.08:10:05.67#ibcon#about to read 5, iclass 24, count 0 2006.173.08:10:05.67#ibcon#read 5, iclass 24, count 0 2006.173.08:10:05.67#ibcon#about to read 6, iclass 24, count 0 2006.173.08:10:05.67#ibcon#read 6, iclass 24, count 0 2006.173.08:10:05.67#ibcon#end of sib2, iclass 24, count 0 2006.173.08:10:05.67#ibcon#*after write, iclass 24, count 0 2006.173.08:10:05.67#ibcon#*before return 0, iclass 24, count 0 2006.173.08:10:05.67#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.08:10:05.67#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.08:10:05.67#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.08:10:05.67#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.08:10:05.67$vck44/vbbw=wide 2006.173.08:10:05.67#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.08:10:05.67#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.08:10:05.67#ibcon#ireg 8 cls_cnt 0 2006.173.08:10:05.67#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.08:10:05.74#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.08:10:05.74#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.08:10:05.74#ibcon#enter wrdev, iclass 26, count 0 2006.173.08:10:05.74#ibcon#first serial, iclass 26, count 0 2006.173.08:10:05.74#ibcon#enter sib2, iclass 26, count 0 2006.173.08:10:05.74#ibcon#flushed, iclass 26, count 0 2006.173.08:10:05.74#ibcon#about to write, iclass 26, count 0 2006.173.08:10:05.74#ibcon#wrote, iclass 26, count 0 2006.173.08:10:05.74#ibcon#about to read 3, iclass 26, count 0 2006.173.08:10:05.76#ibcon#read 3, iclass 26, count 0 2006.173.08:10:05.76#ibcon#about to read 4, iclass 26, count 0 2006.173.08:10:05.76#ibcon#read 4, iclass 26, count 0 2006.173.08:10:05.76#ibcon#about to read 5, iclass 26, count 0 2006.173.08:10:05.76#ibcon#read 5, iclass 26, count 0 2006.173.08:10:05.76#ibcon#about to read 6, iclass 26, count 0 2006.173.08:10:05.76#ibcon#read 6, iclass 26, count 0 2006.173.08:10:05.76#ibcon#end of sib2, iclass 26, count 0 2006.173.08:10:05.76#ibcon#*mode == 0, iclass 26, count 0 2006.173.08:10:05.76#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.08:10:05.76#ibcon#[27=BW32\r\n] 2006.173.08:10:05.76#ibcon#*before write, iclass 26, count 0 2006.173.08:10:05.76#ibcon#enter sib2, iclass 26, count 0 2006.173.08:10:05.76#ibcon#flushed, iclass 26, count 0 2006.173.08:10:05.76#ibcon#about to write, iclass 26, count 0 2006.173.08:10:05.76#ibcon#wrote, iclass 26, count 0 2006.173.08:10:05.76#ibcon#about to read 3, iclass 26, count 0 2006.173.08:10:05.79#ibcon#read 3, iclass 26, count 0 2006.173.08:10:05.79#ibcon#about to read 4, iclass 26, count 0 2006.173.08:10:05.79#ibcon#read 4, iclass 26, count 0 2006.173.08:10:05.79#ibcon#about to read 5, iclass 26, count 0 2006.173.08:10:05.79#ibcon#read 5, iclass 26, count 0 2006.173.08:10:05.79#ibcon#about to read 6, iclass 26, count 0 2006.173.08:10:05.79#ibcon#read 6, iclass 26, count 0 2006.173.08:10:05.79#ibcon#end of sib2, iclass 26, count 0 2006.173.08:10:05.79#ibcon#*after write, iclass 26, count 0 2006.173.08:10:05.79#ibcon#*before return 0, iclass 26, count 0 2006.173.08:10:05.79#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.08:10:05.79#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.08:10:05.79#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.08:10:05.79#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.08:10:05.79$setupk4/ifdk4 2006.173.08:10:05.79$ifdk4/lo= 2006.173.08:10:05.79$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.08:10:05.79$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.08:10:05.79$ifdk4/patch= 2006.173.08:10:05.79$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.08:10:05.79$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.08:10:05.79$setupk4/!*+20s 2006.173.08:10:05.81#abcon#<5=/03 0.7 1.5 23.57 841004.2\r\n> 2006.173.08:10:05.83#abcon#{5=INTERFACE CLEAR} 2006.173.08:10:05.89#abcon#[5=S1D000X0/0*\r\n] 2006.173.08:10:15.98#abcon#<5=/03 0.7 1.5 23.57 841004.2\r\n> 2006.173.08:10:16.00#abcon#{5=INTERFACE CLEAR} 2006.173.08:10:16.06#abcon#[5=S1D000X0/0*\r\n] 2006.173.08:10:20.30$setupk4/"tpicd 2006.173.08:10:20.30$setupk4/echo=off 2006.173.08:10:20.30$setupk4/xlog=off 2006.173.08:10:20.30:!2006.173.08:11:36 2006.173.08:10:39.13#trakl#Source acquired 2006.173.08:10:40.13#flagr#flagr/antenna,acquired 2006.173.08:11:36.00:preob 2006.173.08:11:36.14/onsource/TRACKING 2006.173.08:11:36.14:!2006.173.08:11:46 2006.173.08:11:46.00:"tape 2006.173.08:11:46.00:"st=record 2006.173.08:11:46.00:data_valid=on 2006.173.08:11:46.00:midob 2006.173.08:11:46.14/onsource/TRACKING 2006.173.08:11:46.14/wx/23.60,1004.2,84 2006.173.08:11:46.25/cable/+6.5031E-03 2006.173.08:11:47.34/va/01,07,usb,yes,38,41 2006.173.08:11:47.34/va/02,06,usb,yes,38,39 2006.173.08:11:47.34/va/03,05,usb,yes,48,51 2006.173.08:11:47.34/va/04,06,usb,yes,39,41 2006.173.08:11:47.34/va/05,04,usb,yes,31,31 2006.173.08:11:47.34/va/06,03,usb,yes,43,43 2006.173.08:11:47.34/va/07,04,usb,yes,35,36 2006.173.08:11:47.34/va/08,04,usb,yes,30,36 2006.173.08:11:47.57/valo/01,524.99,yes,locked 2006.173.08:11:47.57/valo/02,534.99,yes,locked 2006.173.08:11:47.57/valo/03,564.99,yes,locked 2006.173.08:11:47.57/valo/04,624.99,yes,locked 2006.173.08:11:47.57/valo/05,734.99,yes,locked 2006.173.08:11:47.57/valo/06,814.99,yes,locked 2006.173.08:11:47.57/valo/07,864.99,yes,locked 2006.173.08:11:47.57/valo/08,884.99,yes,locked 2006.173.08:11:48.66/vb/01,04,usb,yes,31,28 2006.173.08:11:48.66/vb/02,04,usb,yes,33,33 2006.173.08:11:48.66/vb/03,04,usb,yes,30,33 2006.173.08:11:48.66/vb/04,04,usb,yes,35,33 2006.173.08:11:48.66/vb/05,04,usb,yes,27,29 2006.173.08:11:48.66/vb/06,04,usb,yes,32,28 2006.173.08:11:48.66/vb/07,04,usb,yes,31,31 2006.173.08:11:48.66/vb/08,04,usb,yes,29,32 2006.173.08:11:48.89/vblo/01,629.99,yes,locked 2006.173.08:11:48.89/vblo/02,634.99,yes,locked 2006.173.08:11:48.89/vblo/03,649.99,yes,locked 2006.173.08:11:48.89/vblo/04,679.99,yes,locked 2006.173.08:11:48.89/vblo/05,709.99,yes,locked 2006.173.08:11:48.89/vblo/06,719.99,yes,locked 2006.173.08:11:48.89/vblo/07,734.99,yes,locked 2006.173.08:11:48.89/vblo/08,744.99,yes,locked 2006.173.08:11:49.04/vabw/8 2006.173.08:11:49.19/vbbw/8 2006.173.08:11:49.28/xfe/off,on,15.2 2006.173.08:11:49.65/ifatt/23,28,28,28 2006.173.08:11:50.08/fmout-gps/S +3.89E-07 2006.173.08:11:50.12:!2006.173.08:13:06 2006.173.08:13:06.00:data_valid=off 2006.173.08:13:06.00:"et 2006.173.08:13:06.00:!+3s 2006.173.08:13:09.01:"tape 2006.173.08:13:09.01:postob 2006.173.08:13:09.12/cable/+6.5028E-03 2006.173.08:13:09.12/wx/23.61,1004.1,85 2006.173.08:13:10.08/fmout-gps/S +3.88E-07 2006.173.08:13:10.08:scan_name=173-0815,jd0606,100 2006.173.08:13:10.08:source=1334-127,133739.78,-125724.7,2000.0,ccw 2006.173.08:13:11.14#flagr#flagr/antenna,new-source 2006.173.08:13:11.14:checkk5 2006.173.08:13:11.54/chk_autoobs//k5ts1/ autoobs is running! 2006.173.08:13:11.95/chk_autoobs//k5ts2/ autoobs is running! 2006.173.08:13:12.37/chk_autoobs//k5ts3/ autoobs is running! 2006.173.08:13:12.77/chk_autoobs//k5ts4/ autoobs is running! 2006.173.08:13:13.17/chk_obsdata//k5ts1/T1730811??a.dat file size is correct (nominal:320MB, actual:316MB). 2006.173.08:13:13.58/chk_obsdata//k5ts2/T1730811??b.dat file size is correct (nominal:320MB, actual:316MB). 2006.173.08:13:13.96/chk_obsdata//k5ts3/T1730811??c.dat file size is correct (nominal:320MB, actual:316MB). 2006.173.08:13:14.34/chk_obsdata//k5ts4/T1730811??d.dat file size is correct (nominal:320MB, actual:316MB). 2006.173.08:13:15.07/k5log//k5ts1_log_newline 2006.173.08:13:15.79/k5log//k5ts2_log_newline 2006.173.08:13:16.50/k5log//k5ts3_log_newline 2006.173.08:13:17.21/k5log//k5ts4_log_newline 2006.173.08:13:17.23/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.08:13:17.23:setupk4=1 2006.173.08:13:17.23$setupk4/echo=on 2006.173.08:13:17.23$setupk4/pcalon 2006.173.08:13:17.24$pcalon/"no phase cal control is implemented here 2006.173.08:13:17.24$setupk4/"tpicd=stop 2006.173.08:13:17.24$setupk4/"rec=synch_on 2006.173.08:13:17.24$setupk4/"rec_mode=128 2006.173.08:13:17.24$setupk4/!* 2006.173.08:13:17.24$setupk4/recpk4 2006.173.08:13:17.24$recpk4/recpatch= 2006.173.08:13:17.24$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.08:13:17.24$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.08:13:17.24$setupk4/vck44 2006.173.08:13:17.24$vck44/valo=1,524.99 2006.173.08:13:17.24#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.08:13:17.24#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.08:13:17.24#ibcon#ireg 17 cls_cnt 0 2006.173.08:13:17.24#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.08:13:17.24#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.08:13:17.24#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.08:13:17.24#ibcon#enter wrdev, iclass 35, count 0 2006.173.08:13:17.24#ibcon#first serial, iclass 35, count 0 2006.173.08:13:17.24#ibcon#enter sib2, iclass 35, count 0 2006.173.08:13:17.24#ibcon#flushed, iclass 35, count 0 2006.173.08:13:17.24#ibcon#about to write, iclass 35, count 0 2006.173.08:13:17.24#ibcon#wrote, iclass 35, count 0 2006.173.08:13:17.24#ibcon#about to read 3, iclass 35, count 0 2006.173.08:13:17.26#ibcon#read 3, iclass 35, count 0 2006.173.08:13:17.26#ibcon#about to read 4, iclass 35, count 0 2006.173.08:13:17.26#ibcon#read 4, iclass 35, count 0 2006.173.08:13:17.26#ibcon#about to read 5, iclass 35, count 0 2006.173.08:13:17.26#ibcon#read 5, iclass 35, count 0 2006.173.08:13:17.26#ibcon#about to read 6, iclass 35, count 0 2006.173.08:13:17.26#ibcon#read 6, iclass 35, count 0 2006.173.08:13:17.26#ibcon#end of sib2, iclass 35, count 0 2006.173.08:13:17.26#ibcon#*mode == 0, iclass 35, count 0 2006.173.08:13:17.26#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.08:13:17.26#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.08:13:17.26#ibcon#*before write, iclass 35, count 0 2006.173.08:13:17.26#ibcon#enter sib2, iclass 35, count 0 2006.173.08:13:17.26#ibcon#flushed, iclass 35, count 0 2006.173.08:13:17.26#ibcon#about to write, iclass 35, count 0 2006.173.08:13:17.26#ibcon#wrote, iclass 35, count 0 2006.173.08:13:17.26#ibcon#about to read 3, iclass 35, count 0 2006.173.08:13:17.31#ibcon#read 3, iclass 35, count 0 2006.173.08:13:17.31#ibcon#about to read 4, iclass 35, count 0 2006.173.08:13:17.31#ibcon#read 4, iclass 35, count 0 2006.173.08:13:17.31#ibcon#about to read 5, iclass 35, count 0 2006.173.08:13:17.31#ibcon#read 5, iclass 35, count 0 2006.173.08:13:17.31#ibcon#about to read 6, iclass 35, count 0 2006.173.08:13:17.31#ibcon#read 6, iclass 35, count 0 2006.173.08:13:17.31#ibcon#end of sib2, iclass 35, count 0 2006.173.08:13:17.31#ibcon#*after write, iclass 35, count 0 2006.173.08:13:17.31#ibcon#*before return 0, iclass 35, count 0 2006.173.08:13:17.31#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.08:13:17.31#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.08:13:17.31#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.08:13:17.31#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.08:13:17.31$vck44/va=1,7 2006.173.08:13:17.31#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.173.08:13:17.31#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.173.08:13:17.31#ibcon#ireg 11 cls_cnt 2 2006.173.08:13:17.31#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.08:13:17.31#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.08:13:17.31#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.08:13:17.31#ibcon#enter wrdev, iclass 37, count 2 2006.173.08:13:17.31#ibcon#first serial, iclass 37, count 2 2006.173.08:13:17.31#ibcon#enter sib2, iclass 37, count 2 2006.173.08:13:17.31#ibcon#flushed, iclass 37, count 2 2006.173.08:13:17.31#ibcon#about to write, iclass 37, count 2 2006.173.08:13:17.31#ibcon#wrote, iclass 37, count 2 2006.173.08:13:17.31#ibcon#about to read 3, iclass 37, count 2 2006.173.08:13:17.33#ibcon#read 3, iclass 37, count 2 2006.173.08:13:17.33#ibcon#about to read 4, iclass 37, count 2 2006.173.08:13:17.33#ibcon#read 4, iclass 37, count 2 2006.173.08:13:17.33#ibcon#about to read 5, iclass 37, count 2 2006.173.08:13:17.33#ibcon#read 5, iclass 37, count 2 2006.173.08:13:17.33#ibcon#about to read 6, iclass 37, count 2 2006.173.08:13:17.33#ibcon#read 6, iclass 37, count 2 2006.173.08:13:17.33#ibcon#end of sib2, iclass 37, count 2 2006.173.08:13:17.33#ibcon#*mode == 0, iclass 37, count 2 2006.173.08:13:17.33#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.173.08:13:17.33#ibcon#[25=AT01-07\r\n] 2006.173.08:13:17.33#ibcon#*before write, iclass 37, count 2 2006.173.08:13:17.33#ibcon#enter sib2, iclass 37, count 2 2006.173.08:13:17.33#ibcon#flushed, iclass 37, count 2 2006.173.08:13:17.33#ibcon#about to write, iclass 37, count 2 2006.173.08:13:17.33#ibcon#wrote, iclass 37, count 2 2006.173.08:13:17.33#ibcon#about to read 3, iclass 37, count 2 2006.173.08:13:17.36#ibcon#read 3, iclass 37, count 2 2006.173.08:13:17.36#ibcon#about to read 4, iclass 37, count 2 2006.173.08:13:17.36#ibcon#read 4, iclass 37, count 2 2006.173.08:13:17.36#ibcon#about to read 5, iclass 37, count 2 2006.173.08:13:17.36#ibcon#read 5, iclass 37, count 2 2006.173.08:13:17.36#ibcon#about to read 6, iclass 37, count 2 2006.173.08:13:17.36#ibcon#read 6, iclass 37, count 2 2006.173.08:13:17.36#ibcon#end of sib2, iclass 37, count 2 2006.173.08:13:17.36#ibcon#*after write, iclass 37, count 2 2006.173.08:13:17.36#ibcon#*before return 0, iclass 37, count 2 2006.173.08:13:17.36#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.08:13:17.36#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.173.08:13:17.36#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.173.08:13:17.36#ibcon#ireg 7 cls_cnt 0 2006.173.08:13:17.36#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.08:13:17.48#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.08:13:17.48#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.08:13:17.48#ibcon#enter wrdev, iclass 37, count 0 2006.173.08:13:17.48#ibcon#first serial, iclass 37, count 0 2006.173.08:13:17.48#ibcon#enter sib2, iclass 37, count 0 2006.173.08:13:17.48#ibcon#flushed, iclass 37, count 0 2006.173.08:13:17.48#ibcon#about to write, iclass 37, count 0 2006.173.08:13:17.48#ibcon#wrote, iclass 37, count 0 2006.173.08:13:17.48#ibcon#about to read 3, iclass 37, count 0 2006.173.08:13:17.50#ibcon#read 3, iclass 37, count 0 2006.173.08:13:17.50#ibcon#about to read 4, iclass 37, count 0 2006.173.08:13:17.50#ibcon#read 4, iclass 37, count 0 2006.173.08:13:17.50#ibcon#about to read 5, iclass 37, count 0 2006.173.08:13:17.50#ibcon#read 5, iclass 37, count 0 2006.173.08:13:17.50#ibcon#about to read 6, iclass 37, count 0 2006.173.08:13:17.50#ibcon#read 6, iclass 37, count 0 2006.173.08:13:17.50#ibcon#end of sib2, iclass 37, count 0 2006.173.08:13:17.50#ibcon#*mode == 0, iclass 37, count 0 2006.173.08:13:17.50#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.08:13:17.50#ibcon#[25=USB\r\n] 2006.173.08:13:17.50#ibcon#*before write, iclass 37, count 0 2006.173.08:13:17.50#ibcon#enter sib2, iclass 37, count 0 2006.173.08:13:17.50#ibcon#flushed, iclass 37, count 0 2006.173.08:13:17.50#ibcon#about to write, iclass 37, count 0 2006.173.08:13:17.50#ibcon#wrote, iclass 37, count 0 2006.173.08:13:17.50#ibcon#about to read 3, iclass 37, count 0 2006.173.08:13:17.53#ibcon#read 3, iclass 37, count 0 2006.173.08:13:17.53#ibcon#about to read 4, iclass 37, count 0 2006.173.08:13:17.53#ibcon#read 4, iclass 37, count 0 2006.173.08:13:17.53#ibcon#about to read 5, iclass 37, count 0 2006.173.08:13:17.53#ibcon#read 5, iclass 37, count 0 2006.173.08:13:17.53#ibcon#about to read 6, iclass 37, count 0 2006.173.08:13:17.53#ibcon#read 6, iclass 37, count 0 2006.173.08:13:17.53#ibcon#end of sib2, iclass 37, count 0 2006.173.08:13:17.53#ibcon#*after write, iclass 37, count 0 2006.173.08:13:17.53#ibcon#*before return 0, iclass 37, count 0 2006.173.08:13:17.53#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.08:13:17.53#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.173.08:13:17.53#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.08:13:17.53#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.08:13:17.53$vck44/valo=2,534.99 2006.173.08:13:17.53#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.08:13:17.53#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.08:13:17.53#ibcon#ireg 17 cls_cnt 0 2006.173.08:13:17.53#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.08:13:17.53#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.08:13:17.53#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.08:13:17.53#ibcon#enter wrdev, iclass 39, count 0 2006.173.08:13:17.53#ibcon#first serial, iclass 39, count 0 2006.173.08:13:17.53#ibcon#enter sib2, iclass 39, count 0 2006.173.08:13:17.53#ibcon#flushed, iclass 39, count 0 2006.173.08:13:17.53#ibcon#about to write, iclass 39, count 0 2006.173.08:13:17.53#ibcon#wrote, iclass 39, count 0 2006.173.08:13:17.53#ibcon#about to read 3, iclass 39, count 0 2006.173.08:13:17.55#ibcon#read 3, iclass 39, count 0 2006.173.08:13:17.55#ibcon#about to read 4, iclass 39, count 0 2006.173.08:13:17.55#ibcon#read 4, iclass 39, count 0 2006.173.08:13:17.55#ibcon#about to read 5, iclass 39, count 0 2006.173.08:13:17.55#ibcon#read 5, iclass 39, count 0 2006.173.08:13:17.55#ibcon#about to read 6, iclass 39, count 0 2006.173.08:13:17.55#ibcon#read 6, iclass 39, count 0 2006.173.08:13:17.55#ibcon#end of sib2, iclass 39, count 0 2006.173.08:13:17.55#ibcon#*mode == 0, iclass 39, count 0 2006.173.08:13:17.55#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.08:13:17.55#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.08:13:17.55#ibcon#*before write, iclass 39, count 0 2006.173.08:13:17.55#ibcon#enter sib2, iclass 39, count 0 2006.173.08:13:17.55#ibcon#flushed, iclass 39, count 0 2006.173.08:13:17.55#ibcon#about to write, iclass 39, count 0 2006.173.08:13:17.55#ibcon#wrote, iclass 39, count 0 2006.173.08:13:17.55#ibcon#about to read 3, iclass 39, count 0 2006.173.08:13:17.59#ibcon#read 3, iclass 39, count 0 2006.173.08:13:17.59#ibcon#about to read 4, iclass 39, count 0 2006.173.08:13:17.59#ibcon#read 4, iclass 39, count 0 2006.173.08:13:17.59#ibcon#about to read 5, iclass 39, count 0 2006.173.08:13:17.59#ibcon#read 5, iclass 39, count 0 2006.173.08:13:17.59#ibcon#about to read 6, iclass 39, count 0 2006.173.08:13:17.59#ibcon#read 6, iclass 39, count 0 2006.173.08:13:17.59#ibcon#end of sib2, iclass 39, count 0 2006.173.08:13:17.59#ibcon#*after write, iclass 39, count 0 2006.173.08:13:17.59#ibcon#*before return 0, iclass 39, count 0 2006.173.08:13:17.59#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.08:13:17.59#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.08:13:17.59#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.08:13:17.59#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.08:13:17.59$vck44/va=2,6 2006.173.08:13:17.59#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.08:13:17.59#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.08:13:17.59#ibcon#ireg 11 cls_cnt 2 2006.173.08:13:17.59#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.08:13:17.65#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.08:13:17.65#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.08:13:17.65#ibcon#enter wrdev, iclass 3, count 2 2006.173.08:13:17.65#ibcon#first serial, iclass 3, count 2 2006.173.08:13:17.65#ibcon#enter sib2, iclass 3, count 2 2006.173.08:13:17.65#ibcon#flushed, iclass 3, count 2 2006.173.08:13:17.65#ibcon#about to write, iclass 3, count 2 2006.173.08:13:17.65#ibcon#wrote, iclass 3, count 2 2006.173.08:13:17.65#ibcon#about to read 3, iclass 3, count 2 2006.173.08:13:17.67#ibcon#read 3, iclass 3, count 2 2006.173.08:13:17.67#ibcon#about to read 4, iclass 3, count 2 2006.173.08:13:17.67#ibcon#read 4, iclass 3, count 2 2006.173.08:13:17.67#ibcon#about to read 5, iclass 3, count 2 2006.173.08:13:17.67#ibcon#read 5, iclass 3, count 2 2006.173.08:13:17.67#ibcon#about to read 6, iclass 3, count 2 2006.173.08:13:17.67#ibcon#read 6, iclass 3, count 2 2006.173.08:13:17.67#ibcon#end of sib2, iclass 3, count 2 2006.173.08:13:17.67#ibcon#*mode == 0, iclass 3, count 2 2006.173.08:13:17.67#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.08:13:17.67#ibcon#[25=AT02-06\r\n] 2006.173.08:13:17.67#ibcon#*before write, iclass 3, count 2 2006.173.08:13:17.67#ibcon#enter sib2, iclass 3, count 2 2006.173.08:13:17.67#ibcon#flushed, iclass 3, count 2 2006.173.08:13:17.67#ibcon#about to write, iclass 3, count 2 2006.173.08:13:17.67#ibcon#wrote, iclass 3, count 2 2006.173.08:13:17.67#ibcon#about to read 3, iclass 3, count 2 2006.173.08:13:17.70#ibcon#read 3, iclass 3, count 2 2006.173.08:13:17.70#ibcon#about to read 4, iclass 3, count 2 2006.173.08:13:17.70#ibcon#read 4, iclass 3, count 2 2006.173.08:13:17.70#ibcon#about to read 5, iclass 3, count 2 2006.173.08:13:17.70#ibcon#read 5, iclass 3, count 2 2006.173.08:13:17.70#ibcon#about to read 6, iclass 3, count 2 2006.173.08:13:17.70#ibcon#read 6, iclass 3, count 2 2006.173.08:13:17.70#ibcon#end of sib2, iclass 3, count 2 2006.173.08:13:17.70#ibcon#*after write, iclass 3, count 2 2006.173.08:13:17.70#ibcon#*before return 0, iclass 3, count 2 2006.173.08:13:17.70#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.08:13:17.70#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.08:13:17.70#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.08:13:17.70#ibcon#ireg 7 cls_cnt 0 2006.173.08:13:17.70#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.08:13:17.82#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.08:13:17.82#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.08:13:17.82#ibcon#enter wrdev, iclass 3, count 0 2006.173.08:13:17.82#ibcon#first serial, iclass 3, count 0 2006.173.08:13:17.82#ibcon#enter sib2, iclass 3, count 0 2006.173.08:13:17.82#ibcon#flushed, iclass 3, count 0 2006.173.08:13:17.82#ibcon#about to write, iclass 3, count 0 2006.173.08:13:17.82#ibcon#wrote, iclass 3, count 0 2006.173.08:13:17.82#ibcon#about to read 3, iclass 3, count 0 2006.173.08:13:17.84#ibcon#read 3, iclass 3, count 0 2006.173.08:13:17.84#ibcon#about to read 4, iclass 3, count 0 2006.173.08:13:17.84#ibcon#read 4, iclass 3, count 0 2006.173.08:13:17.84#ibcon#about to read 5, iclass 3, count 0 2006.173.08:13:17.84#ibcon#read 5, iclass 3, count 0 2006.173.08:13:17.84#ibcon#about to read 6, iclass 3, count 0 2006.173.08:13:17.84#ibcon#read 6, iclass 3, count 0 2006.173.08:13:17.84#ibcon#end of sib2, iclass 3, count 0 2006.173.08:13:17.84#ibcon#*mode == 0, iclass 3, count 0 2006.173.08:13:17.84#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.08:13:17.84#ibcon#[25=USB\r\n] 2006.173.08:13:17.84#ibcon#*before write, iclass 3, count 0 2006.173.08:13:17.84#ibcon#enter sib2, iclass 3, count 0 2006.173.08:13:17.84#ibcon#flushed, iclass 3, count 0 2006.173.08:13:17.84#ibcon#about to write, iclass 3, count 0 2006.173.08:13:17.84#ibcon#wrote, iclass 3, count 0 2006.173.08:13:17.84#ibcon#about to read 3, iclass 3, count 0 2006.173.08:13:17.87#ibcon#read 3, iclass 3, count 0 2006.173.08:13:17.87#ibcon#about to read 4, iclass 3, count 0 2006.173.08:13:17.87#ibcon#read 4, iclass 3, count 0 2006.173.08:13:17.87#ibcon#about to read 5, iclass 3, count 0 2006.173.08:13:17.87#ibcon#read 5, iclass 3, count 0 2006.173.08:13:17.87#ibcon#about to read 6, iclass 3, count 0 2006.173.08:13:17.87#ibcon#read 6, iclass 3, count 0 2006.173.08:13:17.87#ibcon#end of sib2, iclass 3, count 0 2006.173.08:13:17.87#ibcon#*after write, iclass 3, count 0 2006.173.08:13:17.87#ibcon#*before return 0, iclass 3, count 0 2006.173.08:13:17.87#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.08:13:17.87#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.08:13:17.87#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.08:13:17.87#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.08:13:17.87$vck44/valo=3,564.99 2006.173.08:13:17.87#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.08:13:17.87#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.08:13:17.87#ibcon#ireg 17 cls_cnt 0 2006.173.08:13:17.87#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.08:13:17.87#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.08:13:17.87#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.08:13:17.87#ibcon#enter wrdev, iclass 5, count 0 2006.173.08:13:17.87#ibcon#first serial, iclass 5, count 0 2006.173.08:13:17.87#ibcon#enter sib2, iclass 5, count 0 2006.173.08:13:17.87#ibcon#flushed, iclass 5, count 0 2006.173.08:13:17.87#ibcon#about to write, iclass 5, count 0 2006.173.08:13:17.87#ibcon#wrote, iclass 5, count 0 2006.173.08:13:17.87#ibcon#about to read 3, iclass 5, count 0 2006.173.08:13:17.89#ibcon#read 3, iclass 5, count 0 2006.173.08:13:17.89#ibcon#about to read 4, iclass 5, count 0 2006.173.08:13:17.89#ibcon#read 4, iclass 5, count 0 2006.173.08:13:17.89#ibcon#about to read 5, iclass 5, count 0 2006.173.08:13:17.89#ibcon#read 5, iclass 5, count 0 2006.173.08:13:17.89#ibcon#about to read 6, iclass 5, count 0 2006.173.08:13:17.89#ibcon#read 6, iclass 5, count 0 2006.173.08:13:17.89#ibcon#end of sib2, iclass 5, count 0 2006.173.08:13:17.89#ibcon#*mode == 0, iclass 5, count 0 2006.173.08:13:17.89#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.08:13:17.89#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.08:13:17.89#ibcon#*before write, iclass 5, count 0 2006.173.08:13:17.89#ibcon#enter sib2, iclass 5, count 0 2006.173.08:13:17.89#ibcon#flushed, iclass 5, count 0 2006.173.08:13:17.89#ibcon#about to write, iclass 5, count 0 2006.173.08:13:17.89#ibcon#wrote, iclass 5, count 0 2006.173.08:13:17.89#ibcon#about to read 3, iclass 5, count 0 2006.173.08:13:17.93#ibcon#read 3, iclass 5, count 0 2006.173.08:13:17.93#ibcon#about to read 4, iclass 5, count 0 2006.173.08:13:17.93#ibcon#read 4, iclass 5, count 0 2006.173.08:13:17.93#ibcon#about to read 5, iclass 5, count 0 2006.173.08:13:17.93#ibcon#read 5, iclass 5, count 0 2006.173.08:13:17.93#ibcon#about to read 6, iclass 5, count 0 2006.173.08:13:17.93#ibcon#read 6, iclass 5, count 0 2006.173.08:13:17.93#ibcon#end of sib2, iclass 5, count 0 2006.173.08:13:17.93#ibcon#*after write, iclass 5, count 0 2006.173.08:13:17.93#ibcon#*before return 0, iclass 5, count 0 2006.173.08:13:17.93#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.08:13:17.93#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.08:13:17.93#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.08:13:17.93#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.08:13:17.93$vck44/va=3,5 2006.173.08:13:17.93#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.173.08:13:17.93#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.173.08:13:17.93#ibcon#ireg 11 cls_cnt 2 2006.173.08:13:17.93#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.08:13:17.99#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.08:13:17.99#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.08:13:17.99#ibcon#enter wrdev, iclass 7, count 2 2006.173.08:13:17.99#ibcon#first serial, iclass 7, count 2 2006.173.08:13:17.99#ibcon#enter sib2, iclass 7, count 2 2006.173.08:13:17.99#ibcon#flushed, iclass 7, count 2 2006.173.08:13:17.99#ibcon#about to write, iclass 7, count 2 2006.173.08:13:17.99#ibcon#wrote, iclass 7, count 2 2006.173.08:13:17.99#ibcon#about to read 3, iclass 7, count 2 2006.173.08:13:18.01#ibcon#read 3, iclass 7, count 2 2006.173.08:13:18.01#ibcon#about to read 4, iclass 7, count 2 2006.173.08:13:18.01#ibcon#read 4, iclass 7, count 2 2006.173.08:13:18.01#ibcon#about to read 5, iclass 7, count 2 2006.173.08:13:18.01#ibcon#read 5, iclass 7, count 2 2006.173.08:13:18.01#ibcon#about to read 6, iclass 7, count 2 2006.173.08:13:18.01#ibcon#read 6, iclass 7, count 2 2006.173.08:13:18.01#ibcon#end of sib2, iclass 7, count 2 2006.173.08:13:18.01#ibcon#*mode == 0, iclass 7, count 2 2006.173.08:13:18.01#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.173.08:13:18.01#ibcon#[25=AT03-05\r\n] 2006.173.08:13:18.01#ibcon#*before write, iclass 7, count 2 2006.173.08:13:18.01#ibcon#enter sib2, iclass 7, count 2 2006.173.08:13:18.01#ibcon#flushed, iclass 7, count 2 2006.173.08:13:18.01#ibcon#about to write, iclass 7, count 2 2006.173.08:13:18.01#ibcon#wrote, iclass 7, count 2 2006.173.08:13:18.01#ibcon#about to read 3, iclass 7, count 2 2006.173.08:13:18.04#ibcon#read 3, iclass 7, count 2 2006.173.08:13:18.04#ibcon#about to read 4, iclass 7, count 2 2006.173.08:13:18.04#ibcon#read 4, iclass 7, count 2 2006.173.08:13:18.04#ibcon#about to read 5, iclass 7, count 2 2006.173.08:13:18.04#ibcon#read 5, iclass 7, count 2 2006.173.08:13:18.04#ibcon#about to read 6, iclass 7, count 2 2006.173.08:13:18.04#ibcon#read 6, iclass 7, count 2 2006.173.08:13:18.04#ibcon#end of sib2, iclass 7, count 2 2006.173.08:13:18.04#ibcon#*after write, iclass 7, count 2 2006.173.08:13:18.04#ibcon#*before return 0, iclass 7, count 2 2006.173.08:13:18.04#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.08:13:18.04#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.173.08:13:18.04#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.173.08:13:18.04#ibcon#ireg 7 cls_cnt 0 2006.173.08:13:18.04#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.08:13:18.16#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.08:13:18.16#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.08:13:18.16#ibcon#enter wrdev, iclass 7, count 0 2006.173.08:13:18.16#ibcon#first serial, iclass 7, count 0 2006.173.08:13:18.16#ibcon#enter sib2, iclass 7, count 0 2006.173.08:13:18.16#ibcon#flushed, iclass 7, count 0 2006.173.08:13:18.16#ibcon#about to write, iclass 7, count 0 2006.173.08:13:18.16#ibcon#wrote, iclass 7, count 0 2006.173.08:13:18.16#ibcon#about to read 3, iclass 7, count 0 2006.173.08:13:18.18#ibcon#read 3, iclass 7, count 0 2006.173.08:13:18.18#ibcon#about to read 4, iclass 7, count 0 2006.173.08:13:18.18#ibcon#read 4, iclass 7, count 0 2006.173.08:13:18.18#ibcon#about to read 5, iclass 7, count 0 2006.173.08:13:18.18#ibcon#read 5, iclass 7, count 0 2006.173.08:13:18.18#ibcon#about to read 6, iclass 7, count 0 2006.173.08:13:18.18#ibcon#read 6, iclass 7, count 0 2006.173.08:13:18.18#ibcon#end of sib2, iclass 7, count 0 2006.173.08:13:18.18#ibcon#*mode == 0, iclass 7, count 0 2006.173.08:13:18.18#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.08:13:18.18#ibcon#[25=USB\r\n] 2006.173.08:13:18.18#ibcon#*before write, iclass 7, count 0 2006.173.08:13:18.18#ibcon#enter sib2, iclass 7, count 0 2006.173.08:13:18.18#ibcon#flushed, iclass 7, count 0 2006.173.08:13:18.18#ibcon#about to write, iclass 7, count 0 2006.173.08:13:18.18#ibcon#wrote, iclass 7, count 0 2006.173.08:13:18.18#ibcon#about to read 3, iclass 7, count 0 2006.173.08:13:18.21#ibcon#read 3, iclass 7, count 0 2006.173.08:13:18.21#ibcon#about to read 4, iclass 7, count 0 2006.173.08:13:18.21#ibcon#read 4, iclass 7, count 0 2006.173.08:13:18.21#ibcon#about to read 5, iclass 7, count 0 2006.173.08:13:18.21#ibcon#read 5, iclass 7, count 0 2006.173.08:13:18.21#ibcon#about to read 6, iclass 7, count 0 2006.173.08:13:18.21#ibcon#read 6, iclass 7, count 0 2006.173.08:13:18.21#ibcon#end of sib2, iclass 7, count 0 2006.173.08:13:18.21#ibcon#*after write, iclass 7, count 0 2006.173.08:13:18.21#ibcon#*before return 0, iclass 7, count 0 2006.173.08:13:18.21#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.08:13:18.21#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.173.08:13:18.21#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.08:13:18.21#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.08:13:18.21$vck44/valo=4,624.99 2006.173.08:13:18.21#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.08:13:18.21#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.08:13:18.21#ibcon#ireg 17 cls_cnt 0 2006.173.08:13:18.21#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.08:13:18.21#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.08:13:18.21#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.08:13:18.21#ibcon#enter wrdev, iclass 11, count 0 2006.173.08:13:18.21#ibcon#first serial, iclass 11, count 0 2006.173.08:13:18.21#ibcon#enter sib2, iclass 11, count 0 2006.173.08:13:18.21#ibcon#flushed, iclass 11, count 0 2006.173.08:13:18.21#ibcon#about to write, iclass 11, count 0 2006.173.08:13:18.21#ibcon#wrote, iclass 11, count 0 2006.173.08:13:18.21#ibcon#about to read 3, iclass 11, count 0 2006.173.08:13:18.23#ibcon#read 3, iclass 11, count 0 2006.173.08:13:18.23#ibcon#about to read 4, iclass 11, count 0 2006.173.08:13:18.23#ibcon#read 4, iclass 11, count 0 2006.173.08:13:18.23#ibcon#about to read 5, iclass 11, count 0 2006.173.08:13:18.23#ibcon#read 5, iclass 11, count 0 2006.173.08:13:18.23#ibcon#about to read 6, iclass 11, count 0 2006.173.08:13:18.23#ibcon#read 6, iclass 11, count 0 2006.173.08:13:18.23#ibcon#end of sib2, iclass 11, count 0 2006.173.08:13:18.23#ibcon#*mode == 0, iclass 11, count 0 2006.173.08:13:18.23#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.08:13:18.23#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.08:13:18.23#ibcon#*before write, iclass 11, count 0 2006.173.08:13:18.23#ibcon#enter sib2, iclass 11, count 0 2006.173.08:13:18.23#ibcon#flushed, iclass 11, count 0 2006.173.08:13:18.23#ibcon#about to write, iclass 11, count 0 2006.173.08:13:18.23#ibcon#wrote, iclass 11, count 0 2006.173.08:13:18.23#ibcon#about to read 3, iclass 11, count 0 2006.173.08:13:18.27#ibcon#read 3, iclass 11, count 0 2006.173.08:13:18.27#ibcon#about to read 4, iclass 11, count 0 2006.173.08:13:18.27#ibcon#read 4, iclass 11, count 0 2006.173.08:13:18.27#ibcon#about to read 5, iclass 11, count 0 2006.173.08:13:18.27#ibcon#read 5, iclass 11, count 0 2006.173.08:13:18.27#ibcon#about to read 6, iclass 11, count 0 2006.173.08:13:18.27#ibcon#read 6, iclass 11, count 0 2006.173.08:13:18.27#ibcon#end of sib2, iclass 11, count 0 2006.173.08:13:18.27#ibcon#*after write, iclass 11, count 0 2006.173.08:13:18.27#ibcon#*before return 0, iclass 11, count 0 2006.173.08:13:18.27#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.08:13:18.27#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.08:13:18.27#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.08:13:18.27#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.08:13:18.27$vck44/va=4,6 2006.173.08:13:18.27#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.173.08:13:18.27#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.173.08:13:18.27#ibcon#ireg 11 cls_cnt 2 2006.173.08:13:18.27#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.08:13:18.33#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.08:13:18.33#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.08:13:18.33#ibcon#enter wrdev, iclass 13, count 2 2006.173.08:13:18.33#ibcon#first serial, iclass 13, count 2 2006.173.08:13:18.33#ibcon#enter sib2, iclass 13, count 2 2006.173.08:13:18.33#ibcon#flushed, iclass 13, count 2 2006.173.08:13:18.33#ibcon#about to write, iclass 13, count 2 2006.173.08:13:18.33#ibcon#wrote, iclass 13, count 2 2006.173.08:13:18.33#ibcon#about to read 3, iclass 13, count 2 2006.173.08:13:18.35#ibcon#read 3, iclass 13, count 2 2006.173.08:13:18.35#ibcon#about to read 4, iclass 13, count 2 2006.173.08:13:18.35#ibcon#read 4, iclass 13, count 2 2006.173.08:13:18.35#ibcon#about to read 5, iclass 13, count 2 2006.173.08:13:18.35#ibcon#read 5, iclass 13, count 2 2006.173.08:13:18.35#ibcon#about to read 6, iclass 13, count 2 2006.173.08:13:18.35#ibcon#read 6, iclass 13, count 2 2006.173.08:13:18.35#ibcon#end of sib2, iclass 13, count 2 2006.173.08:13:18.35#ibcon#*mode == 0, iclass 13, count 2 2006.173.08:13:18.35#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.173.08:13:18.35#ibcon#[25=AT04-06\r\n] 2006.173.08:13:18.35#ibcon#*before write, iclass 13, count 2 2006.173.08:13:18.35#ibcon#enter sib2, iclass 13, count 2 2006.173.08:13:18.35#ibcon#flushed, iclass 13, count 2 2006.173.08:13:18.35#ibcon#about to write, iclass 13, count 2 2006.173.08:13:18.35#ibcon#wrote, iclass 13, count 2 2006.173.08:13:18.35#ibcon#about to read 3, iclass 13, count 2 2006.173.08:13:18.38#ibcon#read 3, iclass 13, count 2 2006.173.08:13:18.38#ibcon#about to read 4, iclass 13, count 2 2006.173.08:13:18.38#ibcon#read 4, iclass 13, count 2 2006.173.08:13:18.38#ibcon#about to read 5, iclass 13, count 2 2006.173.08:13:18.38#ibcon#read 5, iclass 13, count 2 2006.173.08:13:18.38#ibcon#about to read 6, iclass 13, count 2 2006.173.08:13:18.38#ibcon#read 6, iclass 13, count 2 2006.173.08:13:18.38#ibcon#end of sib2, iclass 13, count 2 2006.173.08:13:18.38#ibcon#*after write, iclass 13, count 2 2006.173.08:13:18.38#ibcon#*before return 0, iclass 13, count 2 2006.173.08:13:18.38#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.08:13:18.38#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.173.08:13:18.38#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.173.08:13:18.38#ibcon#ireg 7 cls_cnt 0 2006.173.08:13:18.38#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.08:13:18.50#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.08:13:18.50#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.08:13:18.50#ibcon#enter wrdev, iclass 13, count 0 2006.173.08:13:18.50#ibcon#first serial, iclass 13, count 0 2006.173.08:13:18.50#ibcon#enter sib2, iclass 13, count 0 2006.173.08:13:18.50#ibcon#flushed, iclass 13, count 0 2006.173.08:13:18.50#ibcon#about to write, iclass 13, count 0 2006.173.08:13:18.50#ibcon#wrote, iclass 13, count 0 2006.173.08:13:18.50#ibcon#about to read 3, iclass 13, count 0 2006.173.08:13:18.52#ibcon#read 3, iclass 13, count 0 2006.173.08:13:18.52#ibcon#about to read 4, iclass 13, count 0 2006.173.08:13:18.52#ibcon#read 4, iclass 13, count 0 2006.173.08:13:18.52#ibcon#about to read 5, iclass 13, count 0 2006.173.08:13:18.52#ibcon#read 5, iclass 13, count 0 2006.173.08:13:18.52#ibcon#about to read 6, iclass 13, count 0 2006.173.08:13:18.52#ibcon#read 6, iclass 13, count 0 2006.173.08:13:18.52#ibcon#end of sib2, iclass 13, count 0 2006.173.08:13:18.52#ibcon#*mode == 0, iclass 13, count 0 2006.173.08:13:18.52#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.08:13:18.52#ibcon#[25=USB\r\n] 2006.173.08:13:18.52#ibcon#*before write, iclass 13, count 0 2006.173.08:13:18.52#ibcon#enter sib2, iclass 13, count 0 2006.173.08:13:18.52#ibcon#flushed, iclass 13, count 0 2006.173.08:13:18.52#ibcon#about to write, iclass 13, count 0 2006.173.08:13:18.52#ibcon#wrote, iclass 13, count 0 2006.173.08:13:18.52#ibcon#about to read 3, iclass 13, count 0 2006.173.08:13:18.55#ibcon#read 3, iclass 13, count 0 2006.173.08:13:18.55#ibcon#about to read 4, iclass 13, count 0 2006.173.08:13:18.55#ibcon#read 4, iclass 13, count 0 2006.173.08:13:18.55#ibcon#about to read 5, iclass 13, count 0 2006.173.08:13:18.55#ibcon#read 5, iclass 13, count 0 2006.173.08:13:18.55#ibcon#about to read 6, iclass 13, count 0 2006.173.08:13:18.55#ibcon#read 6, iclass 13, count 0 2006.173.08:13:18.55#ibcon#end of sib2, iclass 13, count 0 2006.173.08:13:18.55#ibcon#*after write, iclass 13, count 0 2006.173.08:13:18.55#ibcon#*before return 0, iclass 13, count 0 2006.173.08:13:18.55#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.08:13:18.55#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.173.08:13:18.55#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.08:13:18.55#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.08:13:18.55$vck44/valo=5,734.99 2006.173.08:13:18.55#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.08:13:18.55#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.08:13:18.55#ibcon#ireg 17 cls_cnt 0 2006.173.08:13:18.55#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.08:13:18.55#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.08:13:18.55#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.08:13:18.55#ibcon#enter wrdev, iclass 15, count 0 2006.173.08:13:18.55#ibcon#first serial, iclass 15, count 0 2006.173.08:13:18.55#ibcon#enter sib2, iclass 15, count 0 2006.173.08:13:18.55#ibcon#flushed, iclass 15, count 0 2006.173.08:13:18.55#ibcon#about to write, iclass 15, count 0 2006.173.08:13:18.55#ibcon#wrote, iclass 15, count 0 2006.173.08:13:18.55#ibcon#about to read 3, iclass 15, count 0 2006.173.08:13:18.57#ibcon#read 3, iclass 15, count 0 2006.173.08:13:18.57#ibcon#about to read 4, iclass 15, count 0 2006.173.08:13:18.57#ibcon#read 4, iclass 15, count 0 2006.173.08:13:18.57#ibcon#about to read 5, iclass 15, count 0 2006.173.08:13:18.57#ibcon#read 5, iclass 15, count 0 2006.173.08:13:18.57#ibcon#about to read 6, iclass 15, count 0 2006.173.08:13:18.57#ibcon#read 6, iclass 15, count 0 2006.173.08:13:18.57#ibcon#end of sib2, iclass 15, count 0 2006.173.08:13:18.57#ibcon#*mode == 0, iclass 15, count 0 2006.173.08:13:18.57#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.08:13:18.57#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.08:13:18.57#ibcon#*before write, iclass 15, count 0 2006.173.08:13:18.57#ibcon#enter sib2, iclass 15, count 0 2006.173.08:13:18.57#ibcon#flushed, iclass 15, count 0 2006.173.08:13:18.57#ibcon#about to write, iclass 15, count 0 2006.173.08:13:18.57#ibcon#wrote, iclass 15, count 0 2006.173.08:13:18.57#ibcon#about to read 3, iclass 15, count 0 2006.173.08:13:18.61#ibcon#read 3, iclass 15, count 0 2006.173.08:13:18.61#ibcon#about to read 4, iclass 15, count 0 2006.173.08:13:18.61#ibcon#read 4, iclass 15, count 0 2006.173.08:13:18.61#ibcon#about to read 5, iclass 15, count 0 2006.173.08:13:18.61#ibcon#read 5, iclass 15, count 0 2006.173.08:13:18.61#ibcon#about to read 6, iclass 15, count 0 2006.173.08:13:18.61#ibcon#read 6, iclass 15, count 0 2006.173.08:13:18.61#ibcon#end of sib2, iclass 15, count 0 2006.173.08:13:18.61#ibcon#*after write, iclass 15, count 0 2006.173.08:13:18.61#ibcon#*before return 0, iclass 15, count 0 2006.173.08:13:18.61#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.08:13:18.61#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.08:13:18.61#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.08:13:18.61#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.08:13:18.61$vck44/va=5,4 2006.173.08:13:18.61#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.08:13:18.61#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.08:13:18.61#ibcon#ireg 11 cls_cnt 2 2006.173.08:13:18.61#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.08:13:18.67#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.08:13:18.67#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.08:13:18.67#ibcon#enter wrdev, iclass 17, count 2 2006.173.08:13:18.67#ibcon#first serial, iclass 17, count 2 2006.173.08:13:18.67#ibcon#enter sib2, iclass 17, count 2 2006.173.08:13:18.67#ibcon#flushed, iclass 17, count 2 2006.173.08:13:18.67#ibcon#about to write, iclass 17, count 2 2006.173.08:13:18.67#ibcon#wrote, iclass 17, count 2 2006.173.08:13:18.67#ibcon#about to read 3, iclass 17, count 2 2006.173.08:13:18.69#ibcon#read 3, iclass 17, count 2 2006.173.08:13:18.69#ibcon#about to read 4, iclass 17, count 2 2006.173.08:13:18.69#ibcon#read 4, iclass 17, count 2 2006.173.08:13:18.69#ibcon#about to read 5, iclass 17, count 2 2006.173.08:13:18.69#ibcon#read 5, iclass 17, count 2 2006.173.08:13:18.69#ibcon#about to read 6, iclass 17, count 2 2006.173.08:13:18.69#ibcon#read 6, iclass 17, count 2 2006.173.08:13:18.69#ibcon#end of sib2, iclass 17, count 2 2006.173.08:13:18.69#ibcon#*mode == 0, iclass 17, count 2 2006.173.08:13:18.69#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.08:13:18.69#ibcon#[25=AT05-04\r\n] 2006.173.08:13:18.69#ibcon#*before write, iclass 17, count 2 2006.173.08:13:18.69#ibcon#enter sib2, iclass 17, count 2 2006.173.08:13:18.69#ibcon#flushed, iclass 17, count 2 2006.173.08:13:18.69#ibcon#about to write, iclass 17, count 2 2006.173.08:13:18.69#ibcon#wrote, iclass 17, count 2 2006.173.08:13:18.69#ibcon#about to read 3, iclass 17, count 2 2006.173.08:13:18.72#ibcon#read 3, iclass 17, count 2 2006.173.08:13:18.72#ibcon#about to read 4, iclass 17, count 2 2006.173.08:13:18.72#ibcon#read 4, iclass 17, count 2 2006.173.08:13:18.72#ibcon#about to read 5, iclass 17, count 2 2006.173.08:13:18.72#ibcon#read 5, iclass 17, count 2 2006.173.08:13:18.72#ibcon#about to read 6, iclass 17, count 2 2006.173.08:13:18.72#ibcon#read 6, iclass 17, count 2 2006.173.08:13:18.72#ibcon#end of sib2, iclass 17, count 2 2006.173.08:13:18.72#ibcon#*after write, iclass 17, count 2 2006.173.08:13:18.72#ibcon#*before return 0, iclass 17, count 2 2006.173.08:13:18.72#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.08:13:18.72#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.08:13:18.72#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.08:13:18.72#ibcon#ireg 7 cls_cnt 0 2006.173.08:13:18.72#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.08:13:18.84#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.08:13:18.84#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.08:13:18.84#ibcon#enter wrdev, iclass 17, count 0 2006.173.08:13:18.84#ibcon#first serial, iclass 17, count 0 2006.173.08:13:18.84#ibcon#enter sib2, iclass 17, count 0 2006.173.08:13:18.84#ibcon#flushed, iclass 17, count 0 2006.173.08:13:18.84#ibcon#about to write, iclass 17, count 0 2006.173.08:13:18.84#ibcon#wrote, iclass 17, count 0 2006.173.08:13:18.84#ibcon#about to read 3, iclass 17, count 0 2006.173.08:13:18.86#ibcon#read 3, iclass 17, count 0 2006.173.08:13:18.86#ibcon#about to read 4, iclass 17, count 0 2006.173.08:13:18.86#ibcon#read 4, iclass 17, count 0 2006.173.08:13:18.86#ibcon#about to read 5, iclass 17, count 0 2006.173.08:13:18.86#ibcon#read 5, iclass 17, count 0 2006.173.08:13:18.86#ibcon#about to read 6, iclass 17, count 0 2006.173.08:13:18.86#ibcon#read 6, iclass 17, count 0 2006.173.08:13:18.86#ibcon#end of sib2, iclass 17, count 0 2006.173.08:13:18.86#ibcon#*mode == 0, iclass 17, count 0 2006.173.08:13:18.86#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.08:13:18.86#ibcon#[25=USB\r\n] 2006.173.08:13:18.86#ibcon#*before write, iclass 17, count 0 2006.173.08:13:18.86#ibcon#enter sib2, iclass 17, count 0 2006.173.08:13:18.86#ibcon#flushed, iclass 17, count 0 2006.173.08:13:18.86#ibcon#about to write, iclass 17, count 0 2006.173.08:13:18.86#ibcon#wrote, iclass 17, count 0 2006.173.08:13:18.86#ibcon#about to read 3, iclass 17, count 0 2006.173.08:13:18.89#ibcon#read 3, iclass 17, count 0 2006.173.08:13:18.89#ibcon#about to read 4, iclass 17, count 0 2006.173.08:13:18.89#ibcon#read 4, iclass 17, count 0 2006.173.08:13:18.89#ibcon#about to read 5, iclass 17, count 0 2006.173.08:13:18.89#ibcon#read 5, iclass 17, count 0 2006.173.08:13:18.89#ibcon#about to read 6, iclass 17, count 0 2006.173.08:13:18.89#ibcon#read 6, iclass 17, count 0 2006.173.08:13:18.89#ibcon#end of sib2, iclass 17, count 0 2006.173.08:13:18.89#ibcon#*after write, iclass 17, count 0 2006.173.08:13:18.89#ibcon#*before return 0, iclass 17, count 0 2006.173.08:13:18.89#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.08:13:18.89#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.08:13:18.89#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.08:13:18.89#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.08:13:18.89$vck44/valo=6,814.99 2006.173.08:13:18.89#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.08:13:18.89#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.08:13:18.89#ibcon#ireg 17 cls_cnt 0 2006.173.08:13:18.89#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.08:13:18.89#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.08:13:18.89#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.08:13:18.89#ibcon#enter wrdev, iclass 19, count 0 2006.173.08:13:18.89#ibcon#first serial, iclass 19, count 0 2006.173.08:13:18.89#ibcon#enter sib2, iclass 19, count 0 2006.173.08:13:18.89#ibcon#flushed, iclass 19, count 0 2006.173.08:13:18.89#ibcon#about to write, iclass 19, count 0 2006.173.08:13:18.89#ibcon#wrote, iclass 19, count 0 2006.173.08:13:18.89#ibcon#about to read 3, iclass 19, count 0 2006.173.08:13:18.91#ibcon#read 3, iclass 19, count 0 2006.173.08:13:18.91#ibcon#about to read 4, iclass 19, count 0 2006.173.08:13:18.91#ibcon#read 4, iclass 19, count 0 2006.173.08:13:18.91#ibcon#about to read 5, iclass 19, count 0 2006.173.08:13:18.91#ibcon#read 5, iclass 19, count 0 2006.173.08:13:18.91#ibcon#about to read 6, iclass 19, count 0 2006.173.08:13:18.91#ibcon#read 6, iclass 19, count 0 2006.173.08:13:18.91#ibcon#end of sib2, iclass 19, count 0 2006.173.08:13:18.91#ibcon#*mode == 0, iclass 19, count 0 2006.173.08:13:18.91#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.08:13:18.91#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.08:13:18.91#ibcon#*before write, iclass 19, count 0 2006.173.08:13:18.91#ibcon#enter sib2, iclass 19, count 0 2006.173.08:13:18.91#ibcon#flushed, iclass 19, count 0 2006.173.08:13:18.91#ibcon#about to write, iclass 19, count 0 2006.173.08:13:18.91#ibcon#wrote, iclass 19, count 0 2006.173.08:13:18.91#ibcon#about to read 3, iclass 19, count 0 2006.173.08:13:18.95#ibcon#read 3, iclass 19, count 0 2006.173.08:13:18.95#ibcon#about to read 4, iclass 19, count 0 2006.173.08:13:18.95#ibcon#read 4, iclass 19, count 0 2006.173.08:13:18.95#ibcon#about to read 5, iclass 19, count 0 2006.173.08:13:18.95#ibcon#read 5, iclass 19, count 0 2006.173.08:13:18.95#ibcon#about to read 6, iclass 19, count 0 2006.173.08:13:18.95#ibcon#read 6, iclass 19, count 0 2006.173.08:13:18.95#ibcon#end of sib2, iclass 19, count 0 2006.173.08:13:18.95#ibcon#*after write, iclass 19, count 0 2006.173.08:13:18.95#ibcon#*before return 0, iclass 19, count 0 2006.173.08:13:18.95#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.08:13:18.95#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.08:13:18.95#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.08:13:18.95#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.08:13:18.95$vck44/va=6,3 2006.173.08:13:18.95#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.08:13:18.95#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.08:13:18.95#ibcon#ireg 11 cls_cnt 2 2006.173.08:13:18.95#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.08:13:19.01#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.08:13:19.01#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.08:13:19.01#ibcon#enter wrdev, iclass 21, count 2 2006.173.08:13:19.01#ibcon#first serial, iclass 21, count 2 2006.173.08:13:19.01#ibcon#enter sib2, iclass 21, count 2 2006.173.08:13:19.01#ibcon#flushed, iclass 21, count 2 2006.173.08:13:19.01#ibcon#about to write, iclass 21, count 2 2006.173.08:13:19.01#ibcon#wrote, iclass 21, count 2 2006.173.08:13:19.01#ibcon#about to read 3, iclass 21, count 2 2006.173.08:13:19.03#ibcon#read 3, iclass 21, count 2 2006.173.08:13:19.03#ibcon#about to read 4, iclass 21, count 2 2006.173.08:13:19.03#ibcon#read 4, iclass 21, count 2 2006.173.08:13:19.03#ibcon#about to read 5, iclass 21, count 2 2006.173.08:13:19.03#ibcon#read 5, iclass 21, count 2 2006.173.08:13:19.03#ibcon#about to read 6, iclass 21, count 2 2006.173.08:13:19.03#ibcon#read 6, iclass 21, count 2 2006.173.08:13:19.03#ibcon#end of sib2, iclass 21, count 2 2006.173.08:13:19.03#ibcon#*mode == 0, iclass 21, count 2 2006.173.08:13:19.03#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.08:13:19.03#ibcon#[25=AT06-03\r\n] 2006.173.08:13:19.03#ibcon#*before write, iclass 21, count 2 2006.173.08:13:19.03#ibcon#enter sib2, iclass 21, count 2 2006.173.08:13:19.03#ibcon#flushed, iclass 21, count 2 2006.173.08:13:19.03#ibcon#about to write, iclass 21, count 2 2006.173.08:13:19.03#ibcon#wrote, iclass 21, count 2 2006.173.08:13:19.03#ibcon#about to read 3, iclass 21, count 2 2006.173.08:13:19.06#ibcon#read 3, iclass 21, count 2 2006.173.08:13:19.06#ibcon#about to read 4, iclass 21, count 2 2006.173.08:13:19.06#ibcon#read 4, iclass 21, count 2 2006.173.08:13:19.06#ibcon#about to read 5, iclass 21, count 2 2006.173.08:13:19.06#ibcon#read 5, iclass 21, count 2 2006.173.08:13:19.06#ibcon#about to read 6, iclass 21, count 2 2006.173.08:13:19.06#ibcon#read 6, iclass 21, count 2 2006.173.08:13:19.06#ibcon#end of sib2, iclass 21, count 2 2006.173.08:13:19.06#ibcon#*after write, iclass 21, count 2 2006.173.08:13:19.06#ibcon#*before return 0, iclass 21, count 2 2006.173.08:13:19.06#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.08:13:19.06#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.08:13:19.06#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.08:13:19.06#ibcon#ireg 7 cls_cnt 0 2006.173.08:13:19.06#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.08:13:19.18#abcon#<5=/04 0.6 1.5 23.62 851004.1\r\n> 2006.173.08:13:19.18#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.08:13:19.18#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.08:13:19.18#ibcon#enter wrdev, iclass 21, count 0 2006.173.08:13:19.18#ibcon#first serial, iclass 21, count 0 2006.173.08:13:19.18#ibcon#enter sib2, iclass 21, count 0 2006.173.08:13:19.18#ibcon#flushed, iclass 21, count 0 2006.173.08:13:19.18#ibcon#about to write, iclass 21, count 0 2006.173.08:13:19.18#ibcon#wrote, iclass 21, count 0 2006.173.08:13:19.18#ibcon#about to read 3, iclass 21, count 0 2006.173.08:13:19.20#ibcon#read 3, iclass 21, count 0 2006.173.08:13:19.20#ibcon#about to read 4, iclass 21, count 0 2006.173.08:13:19.20#ibcon#read 4, iclass 21, count 0 2006.173.08:13:19.20#ibcon#about to read 5, iclass 21, count 0 2006.173.08:13:19.20#ibcon#read 5, iclass 21, count 0 2006.173.08:13:19.20#ibcon#about to read 6, iclass 21, count 0 2006.173.08:13:19.20#ibcon#read 6, iclass 21, count 0 2006.173.08:13:19.20#ibcon#end of sib2, iclass 21, count 0 2006.173.08:13:19.20#ibcon#*mode == 0, iclass 21, count 0 2006.173.08:13:19.20#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.08:13:19.20#ibcon#[25=USB\r\n] 2006.173.08:13:19.20#ibcon#*before write, iclass 21, count 0 2006.173.08:13:19.20#ibcon#enter sib2, iclass 21, count 0 2006.173.08:13:19.20#ibcon#flushed, iclass 21, count 0 2006.173.08:13:19.20#ibcon#about to write, iclass 21, count 0 2006.173.08:13:19.20#ibcon#wrote, iclass 21, count 0 2006.173.08:13:19.20#ibcon#about to read 3, iclass 21, count 0 2006.173.08:13:19.20#abcon#{5=INTERFACE CLEAR} 2006.173.08:13:19.23#ibcon#read 3, iclass 21, count 0 2006.173.08:13:19.23#ibcon#about to read 4, iclass 21, count 0 2006.173.08:13:19.23#ibcon#read 4, iclass 21, count 0 2006.173.08:13:19.23#ibcon#about to read 5, iclass 21, count 0 2006.173.08:13:19.23#ibcon#read 5, iclass 21, count 0 2006.173.08:13:19.23#ibcon#about to read 6, iclass 21, count 0 2006.173.08:13:19.23#ibcon#read 6, iclass 21, count 0 2006.173.08:13:19.23#ibcon#end of sib2, iclass 21, count 0 2006.173.08:13:19.23#ibcon#*after write, iclass 21, count 0 2006.173.08:13:19.23#ibcon#*before return 0, iclass 21, count 0 2006.173.08:13:19.23#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.08:13:19.23#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.08:13:19.23#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.08:13:19.23#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.08:13:19.23$vck44/valo=7,864.99 2006.173.08:13:19.23#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.08:13:19.23#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.08:13:19.23#ibcon#ireg 17 cls_cnt 0 2006.173.08:13:19.23#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.08:13:19.23#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.08:13:19.23#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.08:13:19.23#ibcon#enter wrdev, iclass 26, count 0 2006.173.08:13:19.23#ibcon#first serial, iclass 26, count 0 2006.173.08:13:19.23#ibcon#enter sib2, iclass 26, count 0 2006.173.08:13:19.23#ibcon#flushed, iclass 26, count 0 2006.173.08:13:19.23#ibcon#about to write, iclass 26, count 0 2006.173.08:13:19.23#ibcon#wrote, iclass 26, count 0 2006.173.08:13:19.23#ibcon#about to read 3, iclass 26, count 0 2006.173.08:13:19.25#ibcon#read 3, iclass 26, count 0 2006.173.08:13:19.25#ibcon#about to read 4, iclass 26, count 0 2006.173.08:13:19.25#ibcon#read 4, iclass 26, count 0 2006.173.08:13:19.25#ibcon#about to read 5, iclass 26, count 0 2006.173.08:13:19.25#ibcon#read 5, iclass 26, count 0 2006.173.08:13:19.25#ibcon#about to read 6, iclass 26, count 0 2006.173.08:13:19.25#ibcon#read 6, iclass 26, count 0 2006.173.08:13:19.25#ibcon#end of sib2, iclass 26, count 0 2006.173.08:13:19.25#ibcon#*mode == 0, iclass 26, count 0 2006.173.08:13:19.25#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.08:13:19.25#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.08:13:19.25#ibcon#*before write, iclass 26, count 0 2006.173.08:13:19.25#ibcon#enter sib2, iclass 26, count 0 2006.173.08:13:19.25#ibcon#flushed, iclass 26, count 0 2006.173.08:13:19.25#ibcon#about to write, iclass 26, count 0 2006.173.08:13:19.25#ibcon#wrote, iclass 26, count 0 2006.173.08:13:19.25#ibcon#about to read 3, iclass 26, count 0 2006.173.08:13:19.26#abcon#[5=S1D000X0/0*\r\n] 2006.173.08:13:19.29#ibcon#read 3, iclass 26, count 0 2006.173.08:13:19.29#ibcon#about to read 4, iclass 26, count 0 2006.173.08:13:19.29#ibcon#read 4, iclass 26, count 0 2006.173.08:13:19.29#ibcon#about to read 5, iclass 26, count 0 2006.173.08:13:19.29#ibcon#read 5, iclass 26, count 0 2006.173.08:13:19.29#ibcon#about to read 6, iclass 26, count 0 2006.173.08:13:19.29#ibcon#read 6, iclass 26, count 0 2006.173.08:13:19.29#ibcon#end of sib2, iclass 26, count 0 2006.173.08:13:19.29#ibcon#*after write, iclass 26, count 0 2006.173.08:13:19.29#ibcon#*before return 0, iclass 26, count 0 2006.173.08:13:19.29#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.08:13:19.29#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.08:13:19.29#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.08:13:19.29#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.08:13:19.29$vck44/va=7,4 2006.173.08:13:19.29#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.08:13:19.29#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.08:13:19.29#ibcon#ireg 11 cls_cnt 2 2006.173.08:13:19.29#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.08:13:19.35#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.08:13:19.35#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.08:13:19.35#ibcon#enter wrdev, iclass 29, count 2 2006.173.08:13:19.35#ibcon#first serial, iclass 29, count 2 2006.173.08:13:19.35#ibcon#enter sib2, iclass 29, count 2 2006.173.08:13:19.35#ibcon#flushed, iclass 29, count 2 2006.173.08:13:19.35#ibcon#about to write, iclass 29, count 2 2006.173.08:13:19.35#ibcon#wrote, iclass 29, count 2 2006.173.08:13:19.35#ibcon#about to read 3, iclass 29, count 2 2006.173.08:13:19.37#ibcon#read 3, iclass 29, count 2 2006.173.08:13:19.37#ibcon#about to read 4, iclass 29, count 2 2006.173.08:13:19.37#ibcon#read 4, iclass 29, count 2 2006.173.08:13:19.37#ibcon#about to read 5, iclass 29, count 2 2006.173.08:13:19.37#ibcon#read 5, iclass 29, count 2 2006.173.08:13:19.37#ibcon#about to read 6, iclass 29, count 2 2006.173.08:13:19.37#ibcon#read 6, iclass 29, count 2 2006.173.08:13:19.37#ibcon#end of sib2, iclass 29, count 2 2006.173.08:13:19.37#ibcon#*mode == 0, iclass 29, count 2 2006.173.08:13:19.37#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.08:13:19.37#ibcon#[25=AT07-04\r\n] 2006.173.08:13:19.37#ibcon#*before write, iclass 29, count 2 2006.173.08:13:19.37#ibcon#enter sib2, iclass 29, count 2 2006.173.08:13:19.37#ibcon#flushed, iclass 29, count 2 2006.173.08:13:19.37#ibcon#about to write, iclass 29, count 2 2006.173.08:13:19.37#ibcon#wrote, iclass 29, count 2 2006.173.08:13:19.37#ibcon#about to read 3, iclass 29, count 2 2006.173.08:13:19.40#ibcon#read 3, iclass 29, count 2 2006.173.08:13:19.40#ibcon#about to read 4, iclass 29, count 2 2006.173.08:13:19.40#ibcon#read 4, iclass 29, count 2 2006.173.08:13:19.40#ibcon#about to read 5, iclass 29, count 2 2006.173.08:13:19.40#ibcon#read 5, iclass 29, count 2 2006.173.08:13:19.40#ibcon#about to read 6, iclass 29, count 2 2006.173.08:13:19.40#ibcon#read 6, iclass 29, count 2 2006.173.08:13:19.40#ibcon#end of sib2, iclass 29, count 2 2006.173.08:13:19.40#ibcon#*after write, iclass 29, count 2 2006.173.08:13:19.40#ibcon#*before return 0, iclass 29, count 2 2006.173.08:13:19.40#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.08:13:19.40#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.08:13:19.40#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.08:13:19.40#ibcon#ireg 7 cls_cnt 0 2006.173.08:13:19.40#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.08:13:19.52#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.08:13:19.52#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.08:13:19.52#ibcon#enter wrdev, iclass 29, count 0 2006.173.08:13:19.52#ibcon#first serial, iclass 29, count 0 2006.173.08:13:19.52#ibcon#enter sib2, iclass 29, count 0 2006.173.08:13:19.52#ibcon#flushed, iclass 29, count 0 2006.173.08:13:19.52#ibcon#about to write, iclass 29, count 0 2006.173.08:13:19.52#ibcon#wrote, iclass 29, count 0 2006.173.08:13:19.52#ibcon#about to read 3, iclass 29, count 0 2006.173.08:13:19.54#ibcon#read 3, iclass 29, count 0 2006.173.08:13:19.54#ibcon#about to read 4, iclass 29, count 0 2006.173.08:13:19.54#ibcon#read 4, iclass 29, count 0 2006.173.08:13:19.54#ibcon#about to read 5, iclass 29, count 0 2006.173.08:13:19.54#ibcon#read 5, iclass 29, count 0 2006.173.08:13:19.54#ibcon#about to read 6, iclass 29, count 0 2006.173.08:13:19.54#ibcon#read 6, iclass 29, count 0 2006.173.08:13:19.54#ibcon#end of sib2, iclass 29, count 0 2006.173.08:13:19.54#ibcon#*mode == 0, iclass 29, count 0 2006.173.08:13:19.54#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.08:13:19.54#ibcon#[25=USB\r\n] 2006.173.08:13:19.54#ibcon#*before write, iclass 29, count 0 2006.173.08:13:19.54#ibcon#enter sib2, iclass 29, count 0 2006.173.08:13:19.54#ibcon#flushed, iclass 29, count 0 2006.173.08:13:19.54#ibcon#about to write, iclass 29, count 0 2006.173.08:13:19.54#ibcon#wrote, iclass 29, count 0 2006.173.08:13:19.54#ibcon#about to read 3, iclass 29, count 0 2006.173.08:13:19.57#ibcon#read 3, iclass 29, count 0 2006.173.08:13:19.57#ibcon#about to read 4, iclass 29, count 0 2006.173.08:13:19.57#ibcon#read 4, iclass 29, count 0 2006.173.08:13:19.57#ibcon#about to read 5, iclass 29, count 0 2006.173.08:13:19.57#ibcon#read 5, iclass 29, count 0 2006.173.08:13:19.57#ibcon#about to read 6, iclass 29, count 0 2006.173.08:13:19.57#ibcon#read 6, iclass 29, count 0 2006.173.08:13:19.57#ibcon#end of sib2, iclass 29, count 0 2006.173.08:13:19.57#ibcon#*after write, iclass 29, count 0 2006.173.08:13:19.57#ibcon#*before return 0, iclass 29, count 0 2006.173.08:13:19.57#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.08:13:19.57#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.08:13:19.57#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.08:13:19.57#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.08:13:19.57$vck44/valo=8,884.99 2006.173.08:13:19.57#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.08:13:19.57#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.08:13:19.57#ibcon#ireg 17 cls_cnt 0 2006.173.08:13:19.57#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.08:13:19.57#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.08:13:19.57#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.08:13:19.57#ibcon#enter wrdev, iclass 31, count 0 2006.173.08:13:19.57#ibcon#first serial, iclass 31, count 0 2006.173.08:13:19.57#ibcon#enter sib2, iclass 31, count 0 2006.173.08:13:19.57#ibcon#flushed, iclass 31, count 0 2006.173.08:13:19.57#ibcon#about to write, iclass 31, count 0 2006.173.08:13:19.57#ibcon#wrote, iclass 31, count 0 2006.173.08:13:19.57#ibcon#about to read 3, iclass 31, count 0 2006.173.08:13:19.59#ibcon#read 3, iclass 31, count 0 2006.173.08:13:19.59#ibcon#about to read 4, iclass 31, count 0 2006.173.08:13:19.59#ibcon#read 4, iclass 31, count 0 2006.173.08:13:19.59#ibcon#about to read 5, iclass 31, count 0 2006.173.08:13:19.59#ibcon#read 5, iclass 31, count 0 2006.173.08:13:19.59#ibcon#about to read 6, iclass 31, count 0 2006.173.08:13:19.59#ibcon#read 6, iclass 31, count 0 2006.173.08:13:19.59#ibcon#end of sib2, iclass 31, count 0 2006.173.08:13:19.59#ibcon#*mode == 0, iclass 31, count 0 2006.173.08:13:19.59#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.08:13:19.59#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.08:13:19.59#ibcon#*before write, iclass 31, count 0 2006.173.08:13:19.59#ibcon#enter sib2, iclass 31, count 0 2006.173.08:13:19.59#ibcon#flushed, iclass 31, count 0 2006.173.08:13:19.59#ibcon#about to write, iclass 31, count 0 2006.173.08:13:19.59#ibcon#wrote, iclass 31, count 0 2006.173.08:13:19.59#ibcon#about to read 3, iclass 31, count 0 2006.173.08:13:19.63#ibcon#read 3, iclass 31, count 0 2006.173.08:13:19.63#ibcon#about to read 4, iclass 31, count 0 2006.173.08:13:19.63#ibcon#read 4, iclass 31, count 0 2006.173.08:13:19.63#ibcon#about to read 5, iclass 31, count 0 2006.173.08:13:19.63#ibcon#read 5, iclass 31, count 0 2006.173.08:13:19.63#ibcon#about to read 6, iclass 31, count 0 2006.173.08:13:19.63#ibcon#read 6, iclass 31, count 0 2006.173.08:13:19.63#ibcon#end of sib2, iclass 31, count 0 2006.173.08:13:19.63#ibcon#*after write, iclass 31, count 0 2006.173.08:13:19.63#ibcon#*before return 0, iclass 31, count 0 2006.173.08:13:19.63#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.08:13:19.63#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.08:13:19.63#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.08:13:19.63#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.08:13:19.63$vck44/va=8,4 2006.173.08:13:19.63#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.173.08:13:19.63#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.173.08:13:19.63#ibcon#ireg 11 cls_cnt 2 2006.173.08:13:19.63#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.08:13:19.69#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.08:13:19.69#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.08:13:19.69#ibcon#enter wrdev, iclass 33, count 2 2006.173.08:13:19.69#ibcon#first serial, iclass 33, count 2 2006.173.08:13:19.69#ibcon#enter sib2, iclass 33, count 2 2006.173.08:13:19.69#ibcon#flushed, iclass 33, count 2 2006.173.08:13:19.69#ibcon#about to write, iclass 33, count 2 2006.173.08:13:19.69#ibcon#wrote, iclass 33, count 2 2006.173.08:13:19.69#ibcon#about to read 3, iclass 33, count 2 2006.173.08:13:19.71#ibcon#read 3, iclass 33, count 2 2006.173.08:13:19.71#ibcon#about to read 4, iclass 33, count 2 2006.173.08:13:19.71#ibcon#read 4, iclass 33, count 2 2006.173.08:13:19.71#ibcon#about to read 5, iclass 33, count 2 2006.173.08:13:19.71#ibcon#read 5, iclass 33, count 2 2006.173.08:13:19.71#ibcon#about to read 6, iclass 33, count 2 2006.173.08:13:19.71#ibcon#read 6, iclass 33, count 2 2006.173.08:13:19.71#ibcon#end of sib2, iclass 33, count 2 2006.173.08:13:19.71#ibcon#*mode == 0, iclass 33, count 2 2006.173.08:13:19.71#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.173.08:13:19.71#ibcon#[25=AT08-04\r\n] 2006.173.08:13:19.71#ibcon#*before write, iclass 33, count 2 2006.173.08:13:19.71#ibcon#enter sib2, iclass 33, count 2 2006.173.08:13:19.71#ibcon#flushed, iclass 33, count 2 2006.173.08:13:19.71#ibcon#about to write, iclass 33, count 2 2006.173.08:13:19.71#ibcon#wrote, iclass 33, count 2 2006.173.08:13:19.71#ibcon#about to read 3, iclass 33, count 2 2006.173.08:13:19.74#ibcon#read 3, iclass 33, count 2 2006.173.08:13:19.74#ibcon#about to read 4, iclass 33, count 2 2006.173.08:13:19.74#ibcon#read 4, iclass 33, count 2 2006.173.08:13:19.74#ibcon#about to read 5, iclass 33, count 2 2006.173.08:13:19.74#ibcon#read 5, iclass 33, count 2 2006.173.08:13:19.74#ibcon#about to read 6, iclass 33, count 2 2006.173.08:13:19.74#ibcon#read 6, iclass 33, count 2 2006.173.08:13:19.74#ibcon#end of sib2, iclass 33, count 2 2006.173.08:13:19.74#ibcon#*after write, iclass 33, count 2 2006.173.08:13:19.74#ibcon#*before return 0, iclass 33, count 2 2006.173.08:13:19.74#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.08:13:19.74#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.173.08:13:19.74#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.173.08:13:19.74#ibcon#ireg 7 cls_cnt 0 2006.173.08:13:19.74#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.08:13:19.86#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.08:13:19.86#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.08:13:19.86#ibcon#enter wrdev, iclass 33, count 0 2006.173.08:13:19.86#ibcon#first serial, iclass 33, count 0 2006.173.08:13:19.86#ibcon#enter sib2, iclass 33, count 0 2006.173.08:13:19.86#ibcon#flushed, iclass 33, count 0 2006.173.08:13:19.86#ibcon#about to write, iclass 33, count 0 2006.173.08:13:19.86#ibcon#wrote, iclass 33, count 0 2006.173.08:13:19.86#ibcon#about to read 3, iclass 33, count 0 2006.173.08:13:19.88#ibcon#read 3, iclass 33, count 0 2006.173.08:13:19.88#ibcon#about to read 4, iclass 33, count 0 2006.173.08:13:19.88#ibcon#read 4, iclass 33, count 0 2006.173.08:13:19.88#ibcon#about to read 5, iclass 33, count 0 2006.173.08:13:19.88#ibcon#read 5, iclass 33, count 0 2006.173.08:13:19.88#ibcon#about to read 6, iclass 33, count 0 2006.173.08:13:19.88#ibcon#read 6, iclass 33, count 0 2006.173.08:13:19.88#ibcon#end of sib2, iclass 33, count 0 2006.173.08:13:19.88#ibcon#*mode == 0, iclass 33, count 0 2006.173.08:13:19.88#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.08:13:19.88#ibcon#[25=USB\r\n] 2006.173.08:13:19.88#ibcon#*before write, iclass 33, count 0 2006.173.08:13:19.88#ibcon#enter sib2, iclass 33, count 0 2006.173.08:13:19.88#ibcon#flushed, iclass 33, count 0 2006.173.08:13:19.88#ibcon#about to write, iclass 33, count 0 2006.173.08:13:19.88#ibcon#wrote, iclass 33, count 0 2006.173.08:13:19.88#ibcon#about to read 3, iclass 33, count 0 2006.173.08:13:19.91#ibcon#read 3, iclass 33, count 0 2006.173.08:13:19.91#ibcon#about to read 4, iclass 33, count 0 2006.173.08:13:19.91#ibcon#read 4, iclass 33, count 0 2006.173.08:13:19.91#ibcon#about to read 5, iclass 33, count 0 2006.173.08:13:19.91#ibcon#read 5, iclass 33, count 0 2006.173.08:13:19.91#ibcon#about to read 6, iclass 33, count 0 2006.173.08:13:19.91#ibcon#read 6, iclass 33, count 0 2006.173.08:13:19.91#ibcon#end of sib2, iclass 33, count 0 2006.173.08:13:19.91#ibcon#*after write, iclass 33, count 0 2006.173.08:13:19.91#ibcon#*before return 0, iclass 33, count 0 2006.173.08:13:19.91#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.08:13:19.91#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.173.08:13:19.91#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.08:13:19.91#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.08:13:19.91$vck44/vblo=1,629.99 2006.173.08:13:19.91#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.08:13:19.91#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.08:13:19.91#ibcon#ireg 17 cls_cnt 0 2006.173.08:13:19.91#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.08:13:19.91#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.08:13:19.91#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.08:13:19.91#ibcon#enter wrdev, iclass 35, count 0 2006.173.08:13:19.91#ibcon#first serial, iclass 35, count 0 2006.173.08:13:19.91#ibcon#enter sib2, iclass 35, count 0 2006.173.08:13:19.91#ibcon#flushed, iclass 35, count 0 2006.173.08:13:19.91#ibcon#about to write, iclass 35, count 0 2006.173.08:13:19.91#ibcon#wrote, iclass 35, count 0 2006.173.08:13:19.91#ibcon#about to read 3, iclass 35, count 0 2006.173.08:13:19.93#ibcon#read 3, iclass 35, count 0 2006.173.08:13:19.93#ibcon#about to read 4, iclass 35, count 0 2006.173.08:13:19.93#ibcon#read 4, iclass 35, count 0 2006.173.08:13:19.93#ibcon#about to read 5, iclass 35, count 0 2006.173.08:13:19.93#ibcon#read 5, iclass 35, count 0 2006.173.08:13:19.93#ibcon#about to read 6, iclass 35, count 0 2006.173.08:13:19.93#ibcon#read 6, iclass 35, count 0 2006.173.08:13:19.93#ibcon#end of sib2, iclass 35, count 0 2006.173.08:13:19.93#ibcon#*mode == 0, iclass 35, count 0 2006.173.08:13:19.93#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.08:13:19.93#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.08:13:19.93#ibcon#*before write, iclass 35, count 0 2006.173.08:13:19.93#ibcon#enter sib2, iclass 35, count 0 2006.173.08:13:19.93#ibcon#flushed, iclass 35, count 0 2006.173.08:13:19.93#ibcon#about to write, iclass 35, count 0 2006.173.08:13:19.93#ibcon#wrote, iclass 35, count 0 2006.173.08:13:19.93#ibcon#about to read 3, iclass 35, count 0 2006.173.08:13:19.97#ibcon#read 3, iclass 35, count 0 2006.173.08:13:19.97#ibcon#about to read 4, iclass 35, count 0 2006.173.08:13:19.97#ibcon#read 4, iclass 35, count 0 2006.173.08:13:19.97#ibcon#about to read 5, iclass 35, count 0 2006.173.08:13:19.97#ibcon#read 5, iclass 35, count 0 2006.173.08:13:19.97#ibcon#about to read 6, iclass 35, count 0 2006.173.08:13:19.97#ibcon#read 6, iclass 35, count 0 2006.173.08:13:19.97#ibcon#end of sib2, iclass 35, count 0 2006.173.08:13:19.97#ibcon#*after write, iclass 35, count 0 2006.173.08:13:19.97#ibcon#*before return 0, iclass 35, count 0 2006.173.08:13:19.97#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.08:13:19.97#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.08:13:19.97#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.08:13:19.97#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.08:13:19.97$vck44/vb=1,4 2006.173.08:13:19.97#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.173.08:13:19.97#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.173.08:13:19.97#ibcon#ireg 11 cls_cnt 2 2006.173.08:13:19.97#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.08:13:19.97#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.08:13:19.97#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.08:13:19.97#ibcon#enter wrdev, iclass 37, count 2 2006.173.08:13:19.97#ibcon#first serial, iclass 37, count 2 2006.173.08:13:19.97#ibcon#enter sib2, iclass 37, count 2 2006.173.08:13:19.97#ibcon#flushed, iclass 37, count 2 2006.173.08:13:19.97#ibcon#about to write, iclass 37, count 2 2006.173.08:13:19.97#ibcon#wrote, iclass 37, count 2 2006.173.08:13:19.97#ibcon#about to read 3, iclass 37, count 2 2006.173.08:13:19.99#ibcon#read 3, iclass 37, count 2 2006.173.08:13:19.99#ibcon#about to read 4, iclass 37, count 2 2006.173.08:13:19.99#ibcon#read 4, iclass 37, count 2 2006.173.08:13:19.99#ibcon#about to read 5, iclass 37, count 2 2006.173.08:13:19.99#ibcon#read 5, iclass 37, count 2 2006.173.08:13:19.99#ibcon#about to read 6, iclass 37, count 2 2006.173.08:13:19.99#ibcon#read 6, iclass 37, count 2 2006.173.08:13:19.99#ibcon#end of sib2, iclass 37, count 2 2006.173.08:13:19.99#ibcon#*mode == 0, iclass 37, count 2 2006.173.08:13:19.99#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.173.08:13:19.99#ibcon#[27=AT01-04\r\n] 2006.173.08:13:19.99#ibcon#*before write, iclass 37, count 2 2006.173.08:13:19.99#ibcon#enter sib2, iclass 37, count 2 2006.173.08:13:19.99#ibcon#flushed, iclass 37, count 2 2006.173.08:13:19.99#ibcon#about to write, iclass 37, count 2 2006.173.08:13:19.99#ibcon#wrote, iclass 37, count 2 2006.173.08:13:19.99#ibcon#about to read 3, iclass 37, count 2 2006.173.08:13:20.02#ibcon#read 3, iclass 37, count 2 2006.173.08:13:20.02#ibcon#about to read 4, iclass 37, count 2 2006.173.08:13:20.02#ibcon#read 4, iclass 37, count 2 2006.173.08:13:20.02#ibcon#about to read 5, iclass 37, count 2 2006.173.08:13:20.02#ibcon#read 5, iclass 37, count 2 2006.173.08:13:20.02#ibcon#about to read 6, iclass 37, count 2 2006.173.08:13:20.02#ibcon#read 6, iclass 37, count 2 2006.173.08:13:20.02#ibcon#end of sib2, iclass 37, count 2 2006.173.08:13:20.02#ibcon#*after write, iclass 37, count 2 2006.173.08:13:20.02#ibcon#*before return 0, iclass 37, count 2 2006.173.08:13:20.02#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.08:13:20.02#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.173.08:13:20.02#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.173.08:13:20.02#ibcon#ireg 7 cls_cnt 0 2006.173.08:13:20.02#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.08:13:20.14#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.08:13:20.14#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.08:13:20.14#ibcon#enter wrdev, iclass 37, count 0 2006.173.08:13:20.14#ibcon#first serial, iclass 37, count 0 2006.173.08:13:20.14#ibcon#enter sib2, iclass 37, count 0 2006.173.08:13:20.14#ibcon#flushed, iclass 37, count 0 2006.173.08:13:20.14#ibcon#about to write, iclass 37, count 0 2006.173.08:13:20.14#ibcon#wrote, iclass 37, count 0 2006.173.08:13:20.14#ibcon#about to read 3, iclass 37, count 0 2006.173.08:13:20.16#ibcon#read 3, iclass 37, count 0 2006.173.08:13:20.16#ibcon#about to read 4, iclass 37, count 0 2006.173.08:13:20.16#ibcon#read 4, iclass 37, count 0 2006.173.08:13:20.16#ibcon#about to read 5, iclass 37, count 0 2006.173.08:13:20.16#ibcon#read 5, iclass 37, count 0 2006.173.08:13:20.16#ibcon#about to read 6, iclass 37, count 0 2006.173.08:13:20.16#ibcon#read 6, iclass 37, count 0 2006.173.08:13:20.16#ibcon#end of sib2, iclass 37, count 0 2006.173.08:13:20.16#ibcon#*mode == 0, iclass 37, count 0 2006.173.08:13:20.16#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.08:13:20.16#ibcon#[27=USB\r\n] 2006.173.08:13:20.16#ibcon#*before write, iclass 37, count 0 2006.173.08:13:20.16#ibcon#enter sib2, iclass 37, count 0 2006.173.08:13:20.16#ibcon#flushed, iclass 37, count 0 2006.173.08:13:20.16#ibcon#about to write, iclass 37, count 0 2006.173.08:13:20.16#ibcon#wrote, iclass 37, count 0 2006.173.08:13:20.16#ibcon#about to read 3, iclass 37, count 0 2006.173.08:13:20.19#ibcon#read 3, iclass 37, count 0 2006.173.08:13:20.19#ibcon#about to read 4, iclass 37, count 0 2006.173.08:13:20.19#ibcon#read 4, iclass 37, count 0 2006.173.08:13:20.19#ibcon#about to read 5, iclass 37, count 0 2006.173.08:13:20.19#ibcon#read 5, iclass 37, count 0 2006.173.08:13:20.19#ibcon#about to read 6, iclass 37, count 0 2006.173.08:13:20.19#ibcon#read 6, iclass 37, count 0 2006.173.08:13:20.19#ibcon#end of sib2, iclass 37, count 0 2006.173.08:13:20.19#ibcon#*after write, iclass 37, count 0 2006.173.08:13:20.19#ibcon#*before return 0, iclass 37, count 0 2006.173.08:13:20.19#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.08:13:20.19#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.173.08:13:20.19#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.08:13:20.19#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.08:13:20.19$vck44/vblo=2,634.99 2006.173.08:13:20.19#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.08:13:20.19#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.08:13:20.19#ibcon#ireg 17 cls_cnt 0 2006.173.08:13:20.19#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.08:13:20.19#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.08:13:20.19#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.08:13:20.19#ibcon#enter wrdev, iclass 39, count 0 2006.173.08:13:20.19#ibcon#first serial, iclass 39, count 0 2006.173.08:13:20.19#ibcon#enter sib2, iclass 39, count 0 2006.173.08:13:20.19#ibcon#flushed, iclass 39, count 0 2006.173.08:13:20.19#ibcon#about to write, iclass 39, count 0 2006.173.08:13:20.19#ibcon#wrote, iclass 39, count 0 2006.173.08:13:20.19#ibcon#about to read 3, iclass 39, count 0 2006.173.08:13:20.21#ibcon#read 3, iclass 39, count 0 2006.173.08:13:20.21#ibcon#about to read 4, iclass 39, count 0 2006.173.08:13:20.21#ibcon#read 4, iclass 39, count 0 2006.173.08:13:20.21#ibcon#about to read 5, iclass 39, count 0 2006.173.08:13:20.21#ibcon#read 5, iclass 39, count 0 2006.173.08:13:20.21#ibcon#about to read 6, iclass 39, count 0 2006.173.08:13:20.21#ibcon#read 6, iclass 39, count 0 2006.173.08:13:20.21#ibcon#end of sib2, iclass 39, count 0 2006.173.08:13:20.21#ibcon#*mode == 0, iclass 39, count 0 2006.173.08:13:20.21#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.08:13:20.21#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.08:13:20.21#ibcon#*before write, iclass 39, count 0 2006.173.08:13:20.21#ibcon#enter sib2, iclass 39, count 0 2006.173.08:13:20.21#ibcon#flushed, iclass 39, count 0 2006.173.08:13:20.21#ibcon#about to write, iclass 39, count 0 2006.173.08:13:20.21#ibcon#wrote, iclass 39, count 0 2006.173.08:13:20.21#ibcon#about to read 3, iclass 39, count 0 2006.173.08:13:20.25#ibcon#read 3, iclass 39, count 0 2006.173.08:13:20.25#ibcon#about to read 4, iclass 39, count 0 2006.173.08:13:20.25#ibcon#read 4, iclass 39, count 0 2006.173.08:13:20.25#ibcon#about to read 5, iclass 39, count 0 2006.173.08:13:20.25#ibcon#read 5, iclass 39, count 0 2006.173.08:13:20.25#ibcon#about to read 6, iclass 39, count 0 2006.173.08:13:20.25#ibcon#read 6, iclass 39, count 0 2006.173.08:13:20.25#ibcon#end of sib2, iclass 39, count 0 2006.173.08:13:20.25#ibcon#*after write, iclass 39, count 0 2006.173.08:13:20.25#ibcon#*before return 0, iclass 39, count 0 2006.173.08:13:20.25#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.08:13:20.25#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.08:13:20.25#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.08:13:20.25#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.08:13:20.25$vck44/vb=2,4 2006.173.08:13:20.25#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.08:13:20.25#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.08:13:20.25#ibcon#ireg 11 cls_cnt 2 2006.173.08:13:20.25#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.08:13:20.31#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.08:13:20.31#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.08:13:20.31#ibcon#enter wrdev, iclass 3, count 2 2006.173.08:13:20.31#ibcon#first serial, iclass 3, count 2 2006.173.08:13:20.31#ibcon#enter sib2, iclass 3, count 2 2006.173.08:13:20.31#ibcon#flushed, iclass 3, count 2 2006.173.08:13:20.31#ibcon#about to write, iclass 3, count 2 2006.173.08:13:20.31#ibcon#wrote, iclass 3, count 2 2006.173.08:13:20.31#ibcon#about to read 3, iclass 3, count 2 2006.173.08:13:20.33#ibcon#read 3, iclass 3, count 2 2006.173.08:13:20.33#ibcon#about to read 4, iclass 3, count 2 2006.173.08:13:20.33#ibcon#read 4, iclass 3, count 2 2006.173.08:13:20.33#ibcon#about to read 5, iclass 3, count 2 2006.173.08:13:20.33#ibcon#read 5, iclass 3, count 2 2006.173.08:13:20.33#ibcon#about to read 6, iclass 3, count 2 2006.173.08:13:20.33#ibcon#read 6, iclass 3, count 2 2006.173.08:13:20.33#ibcon#end of sib2, iclass 3, count 2 2006.173.08:13:20.33#ibcon#*mode == 0, iclass 3, count 2 2006.173.08:13:20.33#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.08:13:20.33#ibcon#[27=AT02-04\r\n] 2006.173.08:13:20.33#ibcon#*before write, iclass 3, count 2 2006.173.08:13:20.33#ibcon#enter sib2, iclass 3, count 2 2006.173.08:13:20.33#ibcon#flushed, iclass 3, count 2 2006.173.08:13:20.33#ibcon#about to write, iclass 3, count 2 2006.173.08:13:20.33#ibcon#wrote, iclass 3, count 2 2006.173.08:13:20.33#ibcon#about to read 3, iclass 3, count 2 2006.173.08:13:20.36#ibcon#read 3, iclass 3, count 2 2006.173.08:13:20.36#ibcon#about to read 4, iclass 3, count 2 2006.173.08:13:20.36#ibcon#read 4, iclass 3, count 2 2006.173.08:13:20.36#ibcon#about to read 5, iclass 3, count 2 2006.173.08:13:20.36#ibcon#read 5, iclass 3, count 2 2006.173.08:13:20.36#ibcon#about to read 6, iclass 3, count 2 2006.173.08:13:20.36#ibcon#read 6, iclass 3, count 2 2006.173.08:13:20.36#ibcon#end of sib2, iclass 3, count 2 2006.173.08:13:20.36#ibcon#*after write, iclass 3, count 2 2006.173.08:13:20.36#ibcon#*before return 0, iclass 3, count 2 2006.173.08:13:20.36#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.08:13:20.36#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.08:13:20.36#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.08:13:20.36#ibcon#ireg 7 cls_cnt 0 2006.173.08:13:20.36#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.08:13:20.48#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.08:13:20.48#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.08:13:20.48#ibcon#enter wrdev, iclass 3, count 0 2006.173.08:13:20.48#ibcon#first serial, iclass 3, count 0 2006.173.08:13:20.48#ibcon#enter sib2, iclass 3, count 0 2006.173.08:13:20.48#ibcon#flushed, iclass 3, count 0 2006.173.08:13:20.48#ibcon#about to write, iclass 3, count 0 2006.173.08:13:20.48#ibcon#wrote, iclass 3, count 0 2006.173.08:13:20.48#ibcon#about to read 3, iclass 3, count 0 2006.173.08:13:20.50#ibcon#read 3, iclass 3, count 0 2006.173.08:13:20.50#ibcon#about to read 4, iclass 3, count 0 2006.173.08:13:20.50#ibcon#read 4, iclass 3, count 0 2006.173.08:13:20.50#ibcon#about to read 5, iclass 3, count 0 2006.173.08:13:20.50#ibcon#read 5, iclass 3, count 0 2006.173.08:13:20.50#ibcon#about to read 6, iclass 3, count 0 2006.173.08:13:20.50#ibcon#read 6, iclass 3, count 0 2006.173.08:13:20.50#ibcon#end of sib2, iclass 3, count 0 2006.173.08:13:20.50#ibcon#*mode == 0, iclass 3, count 0 2006.173.08:13:20.50#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.08:13:20.50#ibcon#[27=USB\r\n] 2006.173.08:13:20.50#ibcon#*before write, iclass 3, count 0 2006.173.08:13:20.50#ibcon#enter sib2, iclass 3, count 0 2006.173.08:13:20.50#ibcon#flushed, iclass 3, count 0 2006.173.08:13:20.50#ibcon#about to write, iclass 3, count 0 2006.173.08:13:20.50#ibcon#wrote, iclass 3, count 0 2006.173.08:13:20.50#ibcon#about to read 3, iclass 3, count 0 2006.173.08:13:20.53#ibcon#read 3, iclass 3, count 0 2006.173.08:13:20.53#ibcon#about to read 4, iclass 3, count 0 2006.173.08:13:20.53#ibcon#read 4, iclass 3, count 0 2006.173.08:13:20.53#ibcon#about to read 5, iclass 3, count 0 2006.173.08:13:20.53#ibcon#read 5, iclass 3, count 0 2006.173.08:13:20.53#ibcon#about to read 6, iclass 3, count 0 2006.173.08:13:20.53#ibcon#read 6, iclass 3, count 0 2006.173.08:13:20.53#ibcon#end of sib2, iclass 3, count 0 2006.173.08:13:20.53#ibcon#*after write, iclass 3, count 0 2006.173.08:13:20.53#ibcon#*before return 0, iclass 3, count 0 2006.173.08:13:20.53#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.08:13:20.53#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.08:13:20.53#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.08:13:20.53#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.08:13:20.53$vck44/vblo=3,649.99 2006.173.08:13:20.53#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.08:13:20.53#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.08:13:20.53#ibcon#ireg 17 cls_cnt 0 2006.173.08:13:20.53#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.08:13:20.53#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.08:13:20.53#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.08:13:20.53#ibcon#enter wrdev, iclass 5, count 0 2006.173.08:13:20.53#ibcon#first serial, iclass 5, count 0 2006.173.08:13:20.53#ibcon#enter sib2, iclass 5, count 0 2006.173.08:13:20.53#ibcon#flushed, iclass 5, count 0 2006.173.08:13:20.53#ibcon#about to write, iclass 5, count 0 2006.173.08:13:20.53#ibcon#wrote, iclass 5, count 0 2006.173.08:13:20.53#ibcon#about to read 3, iclass 5, count 0 2006.173.08:13:20.55#ibcon#read 3, iclass 5, count 0 2006.173.08:13:20.55#ibcon#about to read 4, iclass 5, count 0 2006.173.08:13:20.55#ibcon#read 4, iclass 5, count 0 2006.173.08:13:20.55#ibcon#about to read 5, iclass 5, count 0 2006.173.08:13:20.55#ibcon#read 5, iclass 5, count 0 2006.173.08:13:20.55#ibcon#about to read 6, iclass 5, count 0 2006.173.08:13:20.55#ibcon#read 6, iclass 5, count 0 2006.173.08:13:20.55#ibcon#end of sib2, iclass 5, count 0 2006.173.08:13:20.55#ibcon#*mode == 0, iclass 5, count 0 2006.173.08:13:20.55#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.08:13:20.55#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.08:13:20.55#ibcon#*before write, iclass 5, count 0 2006.173.08:13:20.55#ibcon#enter sib2, iclass 5, count 0 2006.173.08:13:20.55#ibcon#flushed, iclass 5, count 0 2006.173.08:13:20.55#ibcon#about to write, iclass 5, count 0 2006.173.08:13:20.55#ibcon#wrote, iclass 5, count 0 2006.173.08:13:20.55#ibcon#about to read 3, iclass 5, count 0 2006.173.08:13:20.59#ibcon#read 3, iclass 5, count 0 2006.173.08:13:20.59#ibcon#about to read 4, iclass 5, count 0 2006.173.08:13:20.59#ibcon#read 4, iclass 5, count 0 2006.173.08:13:20.59#ibcon#about to read 5, iclass 5, count 0 2006.173.08:13:20.59#ibcon#read 5, iclass 5, count 0 2006.173.08:13:20.59#ibcon#about to read 6, iclass 5, count 0 2006.173.08:13:20.59#ibcon#read 6, iclass 5, count 0 2006.173.08:13:20.59#ibcon#end of sib2, iclass 5, count 0 2006.173.08:13:20.59#ibcon#*after write, iclass 5, count 0 2006.173.08:13:20.59#ibcon#*before return 0, iclass 5, count 0 2006.173.08:13:20.59#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.08:13:20.59#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.08:13:20.59#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.08:13:20.59#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.08:13:20.59$vck44/vb=3,4 2006.173.08:13:20.59#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.173.08:13:20.59#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.173.08:13:20.59#ibcon#ireg 11 cls_cnt 2 2006.173.08:13:20.59#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.08:13:20.65#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.08:13:20.65#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.08:13:20.65#ibcon#enter wrdev, iclass 7, count 2 2006.173.08:13:20.65#ibcon#first serial, iclass 7, count 2 2006.173.08:13:20.65#ibcon#enter sib2, iclass 7, count 2 2006.173.08:13:20.65#ibcon#flushed, iclass 7, count 2 2006.173.08:13:20.65#ibcon#about to write, iclass 7, count 2 2006.173.08:13:20.65#ibcon#wrote, iclass 7, count 2 2006.173.08:13:20.65#ibcon#about to read 3, iclass 7, count 2 2006.173.08:13:20.67#ibcon#read 3, iclass 7, count 2 2006.173.08:13:20.67#ibcon#about to read 4, iclass 7, count 2 2006.173.08:13:20.67#ibcon#read 4, iclass 7, count 2 2006.173.08:13:20.67#ibcon#about to read 5, iclass 7, count 2 2006.173.08:13:20.67#ibcon#read 5, iclass 7, count 2 2006.173.08:13:20.67#ibcon#about to read 6, iclass 7, count 2 2006.173.08:13:20.67#ibcon#read 6, iclass 7, count 2 2006.173.08:13:20.67#ibcon#end of sib2, iclass 7, count 2 2006.173.08:13:20.67#ibcon#*mode == 0, iclass 7, count 2 2006.173.08:13:20.67#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.173.08:13:20.67#ibcon#[27=AT03-04\r\n] 2006.173.08:13:20.67#ibcon#*before write, iclass 7, count 2 2006.173.08:13:20.67#ibcon#enter sib2, iclass 7, count 2 2006.173.08:13:20.67#ibcon#flushed, iclass 7, count 2 2006.173.08:13:20.67#ibcon#about to write, iclass 7, count 2 2006.173.08:13:20.67#ibcon#wrote, iclass 7, count 2 2006.173.08:13:20.67#ibcon#about to read 3, iclass 7, count 2 2006.173.08:13:20.70#ibcon#read 3, iclass 7, count 2 2006.173.08:13:20.70#ibcon#about to read 4, iclass 7, count 2 2006.173.08:13:20.70#ibcon#read 4, iclass 7, count 2 2006.173.08:13:20.70#ibcon#about to read 5, iclass 7, count 2 2006.173.08:13:20.70#ibcon#read 5, iclass 7, count 2 2006.173.08:13:20.70#ibcon#about to read 6, iclass 7, count 2 2006.173.08:13:20.70#ibcon#read 6, iclass 7, count 2 2006.173.08:13:20.70#ibcon#end of sib2, iclass 7, count 2 2006.173.08:13:20.70#ibcon#*after write, iclass 7, count 2 2006.173.08:13:20.70#ibcon#*before return 0, iclass 7, count 2 2006.173.08:13:20.70#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.08:13:20.70#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.173.08:13:20.70#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.173.08:13:20.70#ibcon#ireg 7 cls_cnt 0 2006.173.08:13:20.70#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.08:13:20.82#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.08:13:20.82#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.08:13:20.82#ibcon#enter wrdev, iclass 7, count 0 2006.173.08:13:20.82#ibcon#first serial, iclass 7, count 0 2006.173.08:13:20.82#ibcon#enter sib2, iclass 7, count 0 2006.173.08:13:20.82#ibcon#flushed, iclass 7, count 0 2006.173.08:13:20.82#ibcon#about to write, iclass 7, count 0 2006.173.08:13:20.82#ibcon#wrote, iclass 7, count 0 2006.173.08:13:20.82#ibcon#about to read 3, iclass 7, count 0 2006.173.08:13:20.84#ibcon#read 3, iclass 7, count 0 2006.173.08:13:20.84#ibcon#about to read 4, iclass 7, count 0 2006.173.08:13:20.84#ibcon#read 4, iclass 7, count 0 2006.173.08:13:20.84#ibcon#about to read 5, iclass 7, count 0 2006.173.08:13:20.84#ibcon#read 5, iclass 7, count 0 2006.173.08:13:20.84#ibcon#about to read 6, iclass 7, count 0 2006.173.08:13:20.84#ibcon#read 6, iclass 7, count 0 2006.173.08:13:20.84#ibcon#end of sib2, iclass 7, count 0 2006.173.08:13:20.84#ibcon#*mode == 0, iclass 7, count 0 2006.173.08:13:20.84#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.08:13:20.84#ibcon#[27=USB\r\n] 2006.173.08:13:20.84#ibcon#*before write, iclass 7, count 0 2006.173.08:13:20.84#ibcon#enter sib2, iclass 7, count 0 2006.173.08:13:20.84#ibcon#flushed, iclass 7, count 0 2006.173.08:13:20.84#ibcon#about to write, iclass 7, count 0 2006.173.08:13:20.84#ibcon#wrote, iclass 7, count 0 2006.173.08:13:20.84#ibcon#about to read 3, iclass 7, count 0 2006.173.08:13:20.87#ibcon#read 3, iclass 7, count 0 2006.173.08:13:20.87#ibcon#about to read 4, iclass 7, count 0 2006.173.08:13:20.87#ibcon#read 4, iclass 7, count 0 2006.173.08:13:20.87#ibcon#about to read 5, iclass 7, count 0 2006.173.08:13:20.87#ibcon#read 5, iclass 7, count 0 2006.173.08:13:20.87#ibcon#about to read 6, iclass 7, count 0 2006.173.08:13:20.87#ibcon#read 6, iclass 7, count 0 2006.173.08:13:20.87#ibcon#end of sib2, iclass 7, count 0 2006.173.08:13:20.87#ibcon#*after write, iclass 7, count 0 2006.173.08:13:20.87#ibcon#*before return 0, iclass 7, count 0 2006.173.08:13:20.87#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.08:13:20.87#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.173.08:13:20.87#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.08:13:20.87#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.08:13:20.87$vck44/vblo=4,679.99 2006.173.08:13:20.87#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.08:13:20.87#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.08:13:20.87#ibcon#ireg 17 cls_cnt 0 2006.173.08:13:20.87#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.08:13:20.87#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.08:13:20.87#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.08:13:20.87#ibcon#enter wrdev, iclass 11, count 0 2006.173.08:13:20.87#ibcon#first serial, iclass 11, count 0 2006.173.08:13:20.87#ibcon#enter sib2, iclass 11, count 0 2006.173.08:13:20.87#ibcon#flushed, iclass 11, count 0 2006.173.08:13:20.87#ibcon#about to write, iclass 11, count 0 2006.173.08:13:20.87#ibcon#wrote, iclass 11, count 0 2006.173.08:13:20.87#ibcon#about to read 3, iclass 11, count 0 2006.173.08:13:20.89#ibcon#read 3, iclass 11, count 0 2006.173.08:13:20.89#ibcon#about to read 4, iclass 11, count 0 2006.173.08:13:20.89#ibcon#read 4, iclass 11, count 0 2006.173.08:13:20.89#ibcon#about to read 5, iclass 11, count 0 2006.173.08:13:20.89#ibcon#read 5, iclass 11, count 0 2006.173.08:13:20.89#ibcon#about to read 6, iclass 11, count 0 2006.173.08:13:20.89#ibcon#read 6, iclass 11, count 0 2006.173.08:13:20.89#ibcon#end of sib2, iclass 11, count 0 2006.173.08:13:20.89#ibcon#*mode == 0, iclass 11, count 0 2006.173.08:13:20.89#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.08:13:20.89#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.08:13:20.89#ibcon#*before write, iclass 11, count 0 2006.173.08:13:20.89#ibcon#enter sib2, iclass 11, count 0 2006.173.08:13:20.89#ibcon#flushed, iclass 11, count 0 2006.173.08:13:20.89#ibcon#about to write, iclass 11, count 0 2006.173.08:13:20.89#ibcon#wrote, iclass 11, count 0 2006.173.08:13:20.89#ibcon#about to read 3, iclass 11, count 0 2006.173.08:13:20.93#ibcon#read 3, iclass 11, count 0 2006.173.08:13:20.93#ibcon#about to read 4, iclass 11, count 0 2006.173.08:13:20.93#ibcon#read 4, iclass 11, count 0 2006.173.08:13:20.93#ibcon#about to read 5, iclass 11, count 0 2006.173.08:13:20.93#ibcon#read 5, iclass 11, count 0 2006.173.08:13:20.93#ibcon#about to read 6, iclass 11, count 0 2006.173.08:13:20.93#ibcon#read 6, iclass 11, count 0 2006.173.08:13:20.93#ibcon#end of sib2, iclass 11, count 0 2006.173.08:13:20.93#ibcon#*after write, iclass 11, count 0 2006.173.08:13:20.93#ibcon#*before return 0, iclass 11, count 0 2006.173.08:13:20.93#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.08:13:20.93#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.08:13:20.93#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.08:13:20.93#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.08:13:20.93$vck44/vb=4,4 2006.173.08:13:20.93#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.173.08:13:20.93#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.173.08:13:20.93#ibcon#ireg 11 cls_cnt 2 2006.173.08:13:20.93#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.08:13:20.99#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.08:13:20.99#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.08:13:20.99#ibcon#enter wrdev, iclass 13, count 2 2006.173.08:13:20.99#ibcon#first serial, iclass 13, count 2 2006.173.08:13:20.99#ibcon#enter sib2, iclass 13, count 2 2006.173.08:13:20.99#ibcon#flushed, iclass 13, count 2 2006.173.08:13:20.99#ibcon#about to write, iclass 13, count 2 2006.173.08:13:20.99#ibcon#wrote, iclass 13, count 2 2006.173.08:13:20.99#ibcon#about to read 3, iclass 13, count 2 2006.173.08:13:21.01#ibcon#read 3, iclass 13, count 2 2006.173.08:13:21.01#ibcon#about to read 4, iclass 13, count 2 2006.173.08:13:21.01#ibcon#read 4, iclass 13, count 2 2006.173.08:13:21.01#ibcon#about to read 5, iclass 13, count 2 2006.173.08:13:21.01#ibcon#read 5, iclass 13, count 2 2006.173.08:13:21.01#ibcon#about to read 6, iclass 13, count 2 2006.173.08:13:21.01#ibcon#read 6, iclass 13, count 2 2006.173.08:13:21.01#ibcon#end of sib2, iclass 13, count 2 2006.173.08:13:21.01#ibcon#*mode == 0, iclass 13, count 2 2006.173.08:13:21.01#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.173.08:13:21.01#ibcon#[27=AT04-04\r\n] 2006.173.08:13:21.01#ibcon#*before write, iclass 13, count 2 2006.173.08:13:21.01#ibcon#enter sib2, iclass 13, count 2 2006.173.08:13:21.01#ibcon#flushed, iclass 13, count 2 2006.173.08:13:21.01#ibcon#about to write, iclass 13, count 2 2006.173.08:13:21.01#ibcon#wrote, iclass 13, count 2 2006.173.08:13:21.01#ibcon#about to read 3, iclass 13, count 2 2006.173.08:13:21.04#ibcon#read 3, iclass 13, count 2 2006.173.08:13:21.04#ibcon#about to read 4, iclass 13, count 2 2006.173.08:13:21.04#ibcon#read 4, iclass 13, count 2 2006.173.08:13:21.04#ibcon#about to read 5, iclass 13, count 2 2006.173.08:13:21.04#ibcon#read 5, iclass 13, count 2 2006.173.08:13:21.04#ibcon#about to read 6, iclass 13, count 2 2006.173.08:13:21.04#ibcon#read 6, iclass 13, count 2 2006.173.08:13:21.04#ibcon#end of sib2, iclass 13, count 2 2006.173.08:13:21.04#ibcon#*after write, iclass 13, count 2 2006.173.08:13:21.04#ibcon#*before return 0, iclass 13, count 2 2006.173.08:13:21.04#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.08:13:21.04#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.173.08:13:21.04#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.173.08:13:21.04#ibcon#ireg 7 cls_cnt 0 2006.173.08:13:21.04#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.08:13:21.16#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.08:13:21.16#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.08:13:21.16#ibcon#enter wrdev, iclass 13, count 0 2006.173.08:13:21.16#ibcon#first serial, iclass 13, count 0 2006.173.08:13:21.16#ibcon#enter sib2, iclass 13, count 0 2006.173.08:13:21.16#ibcon#flushed, iclass 13, count 0 2006.173.08:13:21.16#ibcon#about to write, iclass 13, count 0 2006.173.08:13:21.16#ibcon#wrote, iclass 13, count 0 2006.173.08:13:21.16#ibcon#about to read 3, iclass 13, count 0 2006.173.08:13:21.18#ibcon#read 3, iclass 13, count 0 2006.173.08:13:21.18#ibcon#about to read 4, iclass 13, count 0 2006.173.08:13:21.18#ibcon#read 4, iclass 13, count 0 2006.173.08:13:21.18#ibcon#about to read 5, iclass 13, count 0 2006.173.08:13:21.18#ibcon#read 5, iclass 13, count 0 2006.173.08:13:21.18#ibcon#about to read 6, iclass 13, count 0 2006.173.08:13:21.18#ibcon#read 6, iclass 13, count 0 2006.173.08:13:21.18#ibcon#end of sib2, iclass 13, count 0 2006.173.08:13:21.18#ibcon#*mode == 0, iclass 13, count 0 2006.173.08:13:21.18#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.08:13:21.18#ibcon#[27=USB\r\n] 2006.173.08:13:21.18#ibcon#*before write, iclass 13, count 0 2006.173.08:13:21.18#ibcon#enter sib2, iclass 13, count 0 2006.173.08:13:21.18#ibcon#flushed, iclass 13, count 0 2006.173.08:13:21.18#ibcon#about to write, iclass 13, count 0 2006.173.08:13:21.18#ibcon#wrote, iclass 13, count 0 2006.173.08:13:21.18#ibcon#about to read 3, iclass 13, count 0 2006.173.08:13:21.21#ibcon#read 3, iclass 13, count 0 2006.173.08:13:21.21#ibcon#about to read 4, iclass 13, count 0 2006.173.08:13:21.21#ibcon#read 4, iclass 13, count 0 2006.173.08:13:21.21#ibcon#about to read 5, iclass 13, count 0 2006.173.08:13:21.21#ibcon#read 5, iclass 13, count 0 2006.173.08:13:21.21#ibcon#about to read 6, iclass 13, count 0 2006.173.08:13:21.21#ibcon#read 6, iclass 13, count 0 2006.173.08:13:21.21#ibcon#end of sib2, iclass 13, count 0 2006.173.08:13:21.21#ibcon#*after write, iclass 13, count 0 2006.173.08:13:21.21#ibcon#*before return 0, iclass 13, count 0 2006.173.08:13:21.21#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.08:13:21.21#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.173.08:13:21.21#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.08:13:21.21#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.08:13:21.21$vck44/vblo=5,709.99 2006.173.08:13:21.21#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.08:13:21.21#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.08:13:21.21#ibcon#ireg 17 cls_cnt 0 2006.173.08:13:21.21#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.08:13:21.21#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.08:13:21.21#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.08:13:21.21#ibcon#enter wrdev, iclass 15, count 0 2006.173.08:13:21.21#ibcon#first serial, iclass 15, count 0 2006.173.08:13:21.21#ibcon#enter sib2, iclass 15, count 0 2006.173.08:13:21.21#ibcon#flushed, iclass 15, count 0 2006.173.08:13:21.21#ibcon#about to write, iclass 15, count 0 2006.173.08:13:21.21#ibcon#wrote, iclass 15, count 0 2006.173.08:13:21.21#ibcon#about to read 3, iclass 15, count 0 2006.173.08:13:21.23#ibcon#read 3, iclass 15, count 0 2006.173.08:13:21.23#ibcon#about to read 4, iclass 15, count 0 2006.173.08:13:21.23#ibcon#read 4, iclass 15, count 0 2006.173.08:13:21.23#ibcon#about to read 5, iclass 15, count 0 2006.173.08:13:21.23#ibcon#read 5, iclass 15, count 0 2006.173.08:13:21.23#ibcon#about to read 6, iclass 15, count 0 2006.173.08:13:21.23#ibcon#read 6, iclass 15, count 0 2006.173.08:13:21.23#ibcon#end of sib2, iclass 15, count 0 2006.173.08:13:21.23#ibcon#*mode == 0, iclass 15, count 0 2006.173.08:13:21.23#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.08:13:21.23#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.08:13:21.23#ibcon#*before write, iclass 15, count 0 2006.173.08:13:21.23#ibcon#enter sib2, iclass 15, count 0 2006.173.08:13:21.23#ibcon#flushed, iclass 15, count 0 2006.173.08:13:21.23#ibcon#about to write, iclass 15, count 0 2006.173.08:13:21.23#ibcon#wrote, iclass 15, count 0 2006.173.08:13:21.23#ibcon#about to read 3, iclass 15, count 0 2006.173.08:13:21.27#ibcon#read 3, iclass 15, count 0 2006.173.08:13:21.27#ibcon#about to read 4, iclass 15, count 0 2006.173.08:13:21.27#ibcon#read 4, iclass 15, count 0 2006.173.08:13:21.27#ibcon#about to read 5, iclass 15, count 0 2006.173.08:13:21.27#ibcon#read 5, iclass 15, count 0 2006.173.08:13:21.27#ibcon#about to read 6, iclass 15, count 0 2006.173.08:13:21.27#ibcon#read 6, iclass 15, count 0 2006.173.08:13:21.27#ibcon#end of sib2, iclass 15, count 0 2006.173.08:13:21.27#ibcon#*after write, iclass 15, count 0 2006.173.08:13:21.27#ibcon#*before return 0, iclass 15, count 0 2006.173.08:13:21.27#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.08:13:21.27#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.08:13:21.27#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.08:13:21.27#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.08:13:21.27$vck44/vb=5,4 2006.173.08:13:21.27#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.08:13:21.27#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.08:13:21.27#ibcon#ireg 11 cls_cnt 2 2006.173.08:13:21.27#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.08:13:21.33#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.08:13:21.33#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.08:13:21.33#ibcon#enter wrdev, iclass 17, count 2 2006.173.08:13:21.33#ibcon#first serial, iclass 17, count 2 2006.173.08:13:21.33#ibcon#enter sib2, iclass 17, count 2 2006.173.08:13:21.33#ibcon#flushed, iclass 17, count 2 2006.173.08:13:21.33#ibcon#about to write, iclass 17, count 2 2006.173.08:13:21.33#ibcon#wrote, iclass 17, count 2 2006.173.08:13:21.33#ibcon#about to read 3, iclass 17, count 2 2006.173.08:13:21.35#ibcon#read 3, iclass 17, count 2 2006.173.08:13:21.35#ibcon#about to read 4, iclass 17, count 2 2006.173.08:13:21.35#ibcon#read 4, iclass 17, count 2 2006.173.08:13:21.35#ibcon#about to read 5, iclass 17, count 2 2006.173.08:13:21.35#ibcon#read 5, iclass 17, count 2 2006.173.08:13:21.35#ibcon#about to read 6, iclass 17, count 2 2006.173.08:13:21.35#ibcon#read 6, iclass 17, count 2 2006.173.08:13:21.35#ibcon#end of sib2, iclass 17, count 2 2006.173.08:13:21.35#ibcon#*mode == 0, iclass 17, count 2 2006.173.08:13:21.35#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.08:13:21.35#ibcon#[27=AT05-04\r\n] 2006.173.08:13:21.35#ibcon#*before write, iclass 17, count 2 2006.173.08:13:21.35#ibcon#enter sib2, iclass 17, count 2 2006.173.08:13:21.35#ibcon#flushed, iclass 17, count 2 2006.173.08:13:21.35#ibcon#about to write, iclass 17, count 2 2006.173.08:13:21.35#ibcon#wrote, iclass 17, count 2 2006.173.08:13:21.35#ibcon#about to read 3, iclass 17, count 2 2006.173.08:13:21.38#ibcon#read 3, iclass 17, count 2 2006.173.08:13:21.38#ibcon#about to read 4, iclass 17, count 2 2006.173.08:13:21.38#ibcon#read 4, iclass 17, count 2 2006.173.08:13:21.38#ibcon#about to read 5, iclass 17, count 2 2006.173.08:13:21.38#ibcon#read 5, iclass 17, count 2 2006.173.08:13:21.38#ibcon#about to read 6, iclass 17, count 2 2006.173.08:13:21.38#ibcon#read 6, iclass 17, count 2 2006.173.08:13:21.38#ibcon#end of sib2, iclass 17, count 2 2006.173.08:13:21.38#ibcon#*after write, iclass 17, count 2 2006.173.08:13:21.38#ibcon#*before return 0, iclass 17, count 2 2006.173.08:13:21.38#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.08:13:21.38#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.08:13:21.38#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.08:13:21.38#ibcon#ireg 7 cls_cnt 0 2006.173.08:13:21.38#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.08:13:21.50#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.08:13:21.50#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.08:13:21.50#ibcon#enter wrdev, iclass 17, count 0 2006.173.08:13:21.50#ibcon#first serial, iclass 17, count 0 2006.173.08:13:21.50#ibcon#enter sib2, iclass 17, count 0 2006.173.08:13:21.50#ibcon#flushed, iclass 17, count 0 2006.173.08:13:21.50#ibcon#about to write, iclass 17, count 0 2006.173.08:13:21.50#ibcon#wrote, iclass 17, count 0 2006.173.08:13:21.50#ibcon#about to read 3, iclass 17, count 0 2006.173.08:13:21.52#ibcon#read 3, iclass 17, count 0 2006.173.08:13:21.52#ibcon#about to read 4, iclass 17, count 0 2006.173.08:13:21.52#ibcon#read 4, iclass 17, count 0 2006.173.08:13:21.52#ibcon#about to read 5, iclass 17, count 0 2006.173.08:13:21.52#ibcon#read 5, iclass 17, count 0 2006.173.08:13:21.52#ibcon#about to read 6, iclass 17, count 0 2006.173.08:13:21.52#ibcon#read 6, iclass 17, count 0 2006.173.08:13:21.52#ibcon#end of sib2, iclass 17, count 0 2006.173.08:13:21.52#ibcon#*mode == 0, iclass 17, count 0 2006.173.08:13:21.52#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.08:13:21.52#ibcon#[27=USB\r\n] 2006.173.08:13:21.52#ibcon#*before write, iclass 17, count 0 2006.173.08:13:21.52#ibcon#enter sib2, iclass 17, count 0 2006.173.08:13:21.52#ibcon#flushed, iclass 17, count 0 2006.173.08:13:21.52#ibcon#about to write, iclass 17, count 0 2006.173.08:13:21.52#ibcon#wrote, iclass 17, count 0 2006.173.08:13:21.52#ibcon#about to read 3, iclass 17, count 0 2006.173.08:13:21.55#ibcon#read 3, iclass 17, count 0 2006.173.08:13:21.55#ibcon#about to read 4, iclass 17, count 0 2006.173.08:13:21.55#ibcon#read 4, iclass 17, count 0 2006.173.08:13:21.55#ibcon#about to read 5, iclass 17, count 0 2006.173.08:13:21.55#ibcon#read 5, iclass 17, count 0 2006.173.08:13:21.55#ibcon#about to read 6, iclass 17, count 0 2006.173.08:13:21.55#ibcon#read 6, iclass 17, count 0 2006.173.08:13:21.55#ibcon#end of sib2, iclass 17, count 0 2006.173.08:13:21.55#ibcon#*after write, iclass 17, count 0 2006.173.08:13:21.55#ibcon#*before return 0, iclass 17, count 0 2006.173.08:13:21.55#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.08:13:21.55#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.08:13:21.55#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.08:13:21.55#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.08:13:21.55$vck44/vblo=6,719.99 2006.173.08:13:21.55#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.08:13:21.55#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.08:13:21.55#ibcon#ireg 17 cls_cnt 0 2006.173.08:13:21.55#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.08:13:21.55#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.08:13:21.55#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.08:13:21.55#ibcon#enter wrdev, iclass 19, count 0 2006.173.08:13:21.55#ibcon#first serial, iclass 19, count 0 2006.173.08:13:21.55#ibcon#enter sib2, iclass 19, count 0 2006.173.08:13:21.55#ibcon#flushed, iclass 19, count 0 2006.173.08:13:21.55#ibcon#about to write, iclass 19, count 0 2006.173.08:13:21.55#ibcon#wrote, iclass 19, count 0 2006.173.08:13:21.55#ibcon#about to read 3, iclass 19, count 0 2006.173.08:13:21.57#ibcon#read 3, iclass 19, count 0 2006.173.08:13:21.57#ibcon#about to read 4, iclass 19, count 0 2006.173.08:13:21.57#ibcon#read 4, iclass 19, count 0 2006.173.08:13:21.57#ibcon#about to read 5, iclass 19, count 0 2006.173.08:13:21.57#ibcon#read 5, iclass 19, count 0 2006.173.08:13:21.57#ibcon#about to read 6, iclass 19, count 0 2006.173.08:13:21.57#ibcon#read 6, iclass 19, count 0 2006.173.08:13:21.57#ibcon#end of sib2, iclass 19, count 0 2006.173.08:13:21.57#ibcon#*mode == 0, iclass 19, count 0 2006.173.08:13:21.57#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.08:13:21.57#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.08:13:21.57#ibcon#*before write, iclass 19, count 0 2006.173.08:13:21.57#ibcon#enter sib2, iclass 19, count 0 2006.173.08:13:21.57#ibcon#flushed, iclass 19, count 0 2006.173.08:13:21.57#ibcon#about to write, iclass 19, count 0 2006.173.08:13:21.57#ibcon#wrote, iclass 19, count 0 2006.173.08:13:21.57#ibcon#about to read 3, iclass 19, count 0 2006.173.08:13:21.61#ibcon#read 3, iclass 19, count 0 2006.173.08:13:21.61#ibcon#about to read 4, iclass 19, count 0 2006.173.08:13:21.61#ibcon#read 4, iclass 19, count 0 2006.173.08:13:21.61#ibcon#about to read 5, iclass 19, count 0 2006.173.08:13:21.61#ibcon#read 5, iclass 19, count 0 2006.173.08:13:21.61#ibcon#about to read 6, iclass 19, count 0 2006.173.08:13:21.61#ibcon#read 6, iclass 19, count 0 2006.173.08:13:21.61#ibcon#end of sib2, iclass 19, count 0 2006.173.08:13:21.61#ibcon#*after write, iclass 19, count 0 2006.173.08:13:21.61#ibcon#*before return 0, iclass 19, count 0 2006.173.08:13:21.61#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.08:13:21.61#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.08:13:21.61#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.08:13:21.61#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.08:13:21.61$vck44/vb=6,4 2006.173.08:13:21.61#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.08:13:21.61#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.08:13:21.61#ibcon#ireg 11 cls_cnt 2 2006.173.08:13:21.61#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.08:13:21.67#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.08:13:21.67#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.08:13:21.67#ibcon#enter wrdev, iclass 21, count 2 2006.173.08:13:21.67#ibcon#first serial, iclass 21, count 2 2006.173.08:13:21.67#ibcon#enter sib2, iclass 21, count 2 2006.173.08:13:21.67#ibcon#flushed, iclass 21, count 2 2006.173.08:13:21.67#ibcon#about to write, iclass 21, count 2 2006.173.08:13:21.67#ibcon#wrote, iclass 21, count 2 2006.173.08:13:21.67#ibcon#about to read 3, iclass 21, count 2 2006.173.08:13:21.69#ibcon#read 3, iclass 21, count 2 2006.173.08:13:21.69#ibcon#about to read 4, iclass 21, count 2 2006.173.08:13:21.69#ibcon#read 4, iclass 21, count 2 2006.173.08:13:21.69#ibcon#about to read 5, iclass 21, count 2 2006.173.08:13:21.69#ibcon#read 5, iclass 21, count 2 2006.173.08:13:21.69#ibcon#about to read 6, iclass 21, count 2 2006.173.08:13:21.69#ibcon#read 6, iclass 21, count 2 2006.173.08:13:21.69#ibcon#end of sib2, iclass 21, count 2 2006.173.08:13:21.69#ibcon#*mode == 0, iclass 21, count 2 2006.173.08:13:21.69#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.08:13:21.69#ibcon#[27=AT06-04\r\n] 2006.173.08:13:21.69#ibcon#*before write, iclass 21, count 2 2006.173.08:13:21.69#ibcon#enter sib2, iclass 21, count 2 2006.173.08:13:21.69#ibcon#flushed, iclass 21, count 2 2006.173.08:13:21.69#ibcon#about to write, iclass 21, count 2 2006.173.08:13:21.69#ibcon#wrote, iclass 21, count 2 2006.173.08:13:21.69#ibcon#about to read 3, iclass 21, count 2 2006.173.08:13:21.72#ibcon#read 3, iclass 21, count 2 2006.173.08:13:21.72#ibcon#about to read 4, iclass 21, count 2 2006.173.08:13:21.72#ibcon#read 4, iclass 21, count 2 2006.173.08:13:21.72#ibcon#about to read 5, iclass 21, count 2 2006.173.08:13:21.72#ibcon#read 5, iclass 21, count 2 2006.173.08:13:21.72#ibcon#about to read 6, iclass 21, count 2 2006.173.08:13:21.72#ibcon#read 6, iclass 21, count 2 2006.173.08:13:21.72#ibcon#end of sib2, iclass 21, count 2 2006.173.08:13:21.72#ibcon#*after write, iclass 21, count 2 2006.173.08:13:21.72#ibcon#*before return 0, iclass 21, count 2 2006.173.08:13:21.72#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.08:13:21.72#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.08:13:21.72#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.08:13:21.72#ibcon#ireg 7 cls_cnt 0 2006.173.08:13:21.72#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.08:13:21.84#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.08:13:21.84#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.08:13:21.84#ibcon#enter wrdev, iclass 21, count 0 2006.173.08:13:21.84#ibcon#first serial, iclass 21, count 0 2006.173.08:13:21.84#ibcon#enter sib2, iclass 21, count 0 2006.173.08:13:21.84#ibcon#flushed, iclass 21, count 0 2006.173.08:13:21.84#ibcon#about to write, iclass 21, count 0 2006.173.08:13:21.84#ibcon#wrote, iclass 21, count 0 2006.173.08:13:21.84#ibcon#about to read 3, iclass 21, count 0 2006.173.08:13:21.86#ibcon#read 3, iclass 21, count 0 2006.173.08:13:21.86#ibcon#about to read 4, iclass 21, count 0 2006.173.08:13:21.86#ibcon#read 4, iclass 21, count 0 2006.173.08:13:21.86#ibcon#about to read 5, iclass 21, count 0 2006.173.08:13:21.86#ibcon#read 5, iclass 21, count 0 2006.173.08:13:21.86#ibcon#about to read 6, iclass 21, count 0 2006.173.08:13:21.86#ibcon#read 6, iclass 21, count 0 2006.173.08:13:21.86#ibcon#end of sib2, iclass 21, count 0 2006.173.08:13:21.86#ibcon#*mode == 0, iclass 21, count 0 2006.173.08:13:21.86#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.08:13:21.86#ibcon#[27=USB\r\n] 2006.173.08:13:21.86#ibcon#*before write, iclass 21, count 0 2006.173.08:13:21.86#ibcon#enter sib2, iclass 21, count 0 2006.173.08:13:21.86#ibcon#flushed, iclass 21, count 0 2006.173.08:13:21.86#ibcon#about to write, iclass 21, count 0 2006.173.08:13:21.86#ibcon#wrote, iclass 21, count 0 2006.173.08:13:21.86#ibcon#about to read 3, iclass 21, count 0 2006.173.08:13:21.89#ibcon#read 3, iclass 21, count 0 2006.173.08:13:21.89#ibcon#about to read 4, iclass 21, count 0 2006.173.08:13:21.89#ibcon#read 4, iclass 21, count 0 2006.173.08:13:21.89#ibcon#about to read 5, iclass 21, count 0 2006.173.08:13:21.89#ibcon#read 5, iclass 21, count 0 2006.173.08:13:21.89#ibcon#about to read 6, iclass 21, count 0 2006.173.08:13:21.89#ibcon#read 6, iclass 21, count 0 2006.173.08:13:21.89#ibcon#end of sib2, iclass 21, count 0 2006.173.08:13:21.89#ibcon#*after write, iclass 21, count 0 2006.173.08:13:21.89#ibcon#*before return 0, iclass 21, count 0 2006.173.08:13:21.89#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.08:13:21.89#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.08:13:21.89#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.08:13:21.89#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.08:13:21.89$vck44/vblo=7,734.99 2006.173.08:13:21.89#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.08:13:21.89#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.08:13:21.89#ibcon#ireg 17 cls_cnt 0 2006.173.08:13:21.89#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.08:13:21.89#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.08:13:21.89#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.08:13:21.89#ibcon#enter wrdev, iclass 23, count 0 2006.173.08:13:21.89#ibcon#first serial, iclass 23, count 0 2006.173.08:13:21.89#ibcon#enter sib2, iclass 23, count 0 2006.173.08:13:21.89#ibcon#flushed, iclass 23, count 0 2006.173.08:13:21.89#ibcon#about to write, iclass 23, count 0 2006.173.08:13:21.89#ibcon#wrote, iclass 23, count 0 2006.173.08:13:21.89#ibcon#about to read 3, iclass 23, count 0 2006.173.08:13:21.91#ibcon#read 3, iclass 23, count 0 2006.173.08:13:21.91#ibcon#about to read 4, iclass 23, count 0 2006.173.08:13:21.91#ibcon#read 4, iclass 23, count 0 2006.173.08:13:21.91#ibcon#about to read 5, iclass 23, count 0 2006.173.08:13:21.91#ibcon#read 5, iclass 23, count 0 2006.173.08:13:21.91#ibcon#about to read 6, iclass 23, count 0 2006.173.08:13:21.91#ibcon#read 6, iclass 23, count 0 2006.173.08:13:21.91#ibcon#end of sib2, iclass 23, count 0 2006.173.08:13:21.91#ibcon#*mode == 0, iclass 23, count 0 2006.173.08:13:21.91#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.08:13:21.91#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.08:13:21.91#ibcon#*before write, iclass 23, count 0 2006.173.08:13:21.91#ibcon#enter sib2, iclass 23, count 0 2006.173.08:13:21.91#ibcon#flushed, iclass 23, count 0 2006.173.08:13:21.91#ibcon#about to write, iclass 23, count 0 2006.173.08:13:21.91#ibcon#wrote, iclass 23, count 0 2006.173.08:13:21.91#ibcon#about to read 3, iclass 23, count 0 2006.173.08:13:21.95#ibcon#read 3, iclass 23, count 0 2006.173.08:13:21.95#ibcon#about to read 4, iclass 23, count 0 2006.173.08:13:21.95#ibcon#read 4, iclass 23, count 0 2006.173.08:13:21.95#ibcon#about to read 5, iclass 23, count 0 2006.173.08:13:21.95#ibcon#read 5, iclass 23, count 0 2006.173.08:13:21.95#ibcon#about to read 6, iclass 23, count 0 2006.173.08:13:21.95#ibcon#read 6, iclass 23, count 0 2006.173.08:13:21.95#ibcon#end of sib2, iclass 23, count 0 2006.173.08:13:21.95#ibcon#*after write, iclass 23, count 0 2006.173.08:13:21.95#ibcon#*before return 0, iclass 23, count 0 2006.173.08:13:21.95#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.08:13:21.95#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.08:13:21.95#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.08:13:21.95#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.08:13:21.95$vck44/vb=7,4 2006.173.08:13:21.95#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.08:13:21.95#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.08:13:21.95#ibcon#ireg 11 cls_cnt 2 2006.173.08:13:21.95#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.08:13:22.01#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.08:13:22.01#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.08:13:22.01#ibcon#enter wrdev, iclass 25, count 2 2006.173.08:13:22.01#ibcon#first serial, iclass 25, count 2 2006.173.08:13:22.01#ibcon#enter sib2, iclass 25, count 2 2006.173.08:13:22.01#ibcon#flushed, iclass 25, count 2 2006.173.08:13:22.01#ibcon#about to write, iclass 25, count 2 2006.173.08:13:22.01#ibcon#wrote, iclass 25, count 2 2006.173.08:13:22.01#ibcon#about to read 3, iclass 25, count 2 2006.173.08:13:22.03#ibcon#read 3, iclass 25, count 2 2006.173.08:13:22.03#ibcon#about to read 4, iclass 25, count 2 2006.173.08:13:22.03#ibcon#read 4, iclass 25, count 2 2006.173.08:13:22.03#ibcon#about to read 5, iclass 25, count 2 2006.173.08:13:22.03#ibcon#read 5, iclass 25, count 2 2006.173.08:13:22.03#ibcon#about to read 6, iclass 25, count 2 2006.173.08:13:22.03#ibcon#read 6, iclass 25, count 2 2006.173.08:13:22.03#ibcon#end of sib2, iclass 25, count 2 2006.173.08:13:22.03#ibcon#*mode == 0, iclass 25, count 2 2006.173.08:13:22.03#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.08:13:22.03#ibcon#[27=AT07-04\r\n] 2006.173.08:13:22.03#ibcon#*before write, iclass 25, count 2 2006.173.08:13:22.03#ibcon#enter sib2, iclass 25, count 2 2006.173.08:13:22.03#ibcon#flushed, iclass 25, count 2 2006.173.08:13:22.03#ibcon#about to write, iclass 25, count 2 2006.173.08:13:22.03#ibcon#wrote, iclass 25, count 2 2006.173.08:13:22.03#ibcon#about to read 3, iclass 25, count 2 2006.173.08:13:22.06#ibcon#read 3, iclass 25, count 2 2006.173.08:13:22.06#ibcon#about to read 4, iclass 25, count 2 2006.173.08:13:22.06#ibcon#read 4, iclass 25, count 2 2006.173.08:13:22.06#ibcon#about to read 5, iclass 25, count 2 2006.173.08:13:22.06#ibcon#read 5, iclass 25, count 2 2006.173.08:13:22.06#ibcon#about to read 6, iclass 25, count 2 2006.173.08:13:22.06#ibcon#read 6, iclass 25, count 2 2006.173.08:13:22.06#ibcon#end of sib2, iclass 25, count 2 2006.173.08:13:22.06#ibcon#*after write, iclass 25, count 2 2006.173.08:13:22.06#ibcon#*before return 0, iclass 25, count 2 2006.173.08:13:22.06#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.08:13:22.06#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.08:13:22.06#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.08:13:22.06#ibcon#ireg 7 cls_cnt 0 2006.173.08:13:22.06#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.08:13:22.18#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.08:13:22.18#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.08:13:22.18#ibcon#enter wrdev, iclass 25, count 0 2006.173.08:13:22.18#ibcon#first serial, iclass 25, count 0 2006.173.08:13:22.18#ibcon#enter sib2, iclass 25, count 0 2006.173.08:13:22.18#ibcon#flushed, iclass 25, count 0 2006.173.08:13:22.18#ibcon#about to write, iclass 25, count 0 2006.173.08:13:22.18#ibcon#wrote, iclass 25, count 0 2006.173.08:13:22.18#ibcon#about to read 3, iclass 25, count 0 2006.173.08:13:22.20#ibcon#read 3, iclass 25, count 0 2006.173.08:13:22.20#ibcon#about to read 4, iclass 25, count 0 2006.173.08:13:22.20#ibcon#read 4, iclass 25, count 0 2006.173.08:13:22.20#ibcon#about to read 5, iclass 25, count 0 2006.173.08:13:22.20#ibcon#read 5, iclass 25, count 0 2006.173.08:13:22.20#ibcon#about to read 6, iclass 25, count 0 2006.173.08:13:22.20#ibcon#read 6, iclass 25, count 0 2006.173.08:13:22.20#ibcon#end of sib2, iclass 25, count 0 2006.173.08:13:22.20#ibcon#*mode == 0, iclass 25, count 0 2006.173.08:13:22.20#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.08:13:22.20#ibcon#[27=USB\r\n] 2006.173.08:13:22.20#ibcon#*before write, iclass 25, count 0 2006.173.08:13:22.20#ibcon#enter sib2, iclass 25, count 0 2006.173.08:13:22.20#ibcon#flushed, iclass 25, count 0 2006.173.08:13:22.20#ibcon#about to write, iclass 25, count 0 2006.173.08:13:22.20#ibcon#wrote, iclass 25, count 0 2006.173.08:13:22.20#ibcon#about to read 3, iclass 25, count 0 2006.173.08:13:22.23#ibcon#read 3, iclass 25, count 0 2006.173.08:13:22.23#ibcon#about to read 4, iclass 25, count 0 2006.173.08:13:22.23#ibcon#read 4, iclass 25, count 0 2006.173.08:13:22.23#ibcon#about to read 5, iclass 25, count 0 2006.173.08:13:22.23#ibcon#read 5, iclass 25, count 0 2006.173.08:13:22.23#ibcon#about to read 6, iclass 25, count 0 2006.173.08:13:22.23#ibcon#read 6, iclass 25, count 0 2006.173.08:13:22.23#ibcon#end of sib2, iclass 25, count 0 2006.173.08:13:22.23#ibcon#*after write, iclass 25, count 0 2006.173.08:13:22.23#ibcon#*before return 0, iclass 25, count 0 2006.173.08:13:22.23#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.08:13:22.23#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.08:13:22.23#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.08:13:22.23#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.08:13:22.23$vck44/vblo=8,744.99 2006.173.08:13:22.23#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.08:13:22.23#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.08:13:22.23#ibcon#ireg 17 cls_cnt 0 2006.173.08:13:22.23#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.08:13:22.23#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.08:13:22.23#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.08:13:22.23#ibcon#enter wrdev, iclass 27, count 0 2006.173.08:13:22.23#ibcon#first serial, iclass 27, count 0 2006.173.08:13:22.23#ibcon#enter sib2, iclass 27, count 0 2006.173.08:13:22.23#ibcon#flushed, iclass 27, count 0 2006.173.08:13:22.23#ibcon#about to write, iclass 27, count 0 2006.173.08:13:22.23#ibcon#wrote, iclass 27, count 0 2006.173.08:13:22.23#ibcon#about to read 3, iclass 27, count 0 2006.173.08:13:22.25#ibcon#read 3, iclass 27, count 0 2006.173.08:13:22.25#ibcon#about to read 4, iclass 27, count 0 2006.173.08:13:22.25#ibcon#read 4, iclass 27, count 0 2006.173.08:13:22.25#ibcon#about to read 5, iclass 27, count 0 2006.173.08:13:22.25#ibcon#read 5, iclass 27, count 0 2006.173.08:13:22.25#ibcon#about to read 6, iclass 27, count 0 2006.173.08:13:22.25#ibcon#read 6, iclass 27, count 0 2006.173.08:13:22.25#ibcon#end of sib2, iclass 27, count 0 2006.173.08:13:22.25#ibcon#*mode == 0, iclass 27, count 0 2006.173.08:13:22.25#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.08:13:22.25#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.08:13:22.25#ibcon#*before write, iclass 27, count 0 2006.173.08:13:22.25#ibcon#enter sib2, iclass 27, count 0 2006.173.08:13:22.25#ibcon#flushed, iclass 27, count 0 2006.173.08:13:22.25#ibcon#about to write, iclass 27, count 0 2006.173.08:13:22.25#ibcon#wrote, iclass 27, count 0 2006.173.08:13:22.25#ibcon#about to read 3, iclass 27, count 0 2006.173.08:13:22.29#ibcon#read 3, iclass 27, count 0 2006.173.08:13:22.29#ibcon#about to read 4, iclass 27, count 0 2006.173.08:13:22.29#ibcon#read 4, iclass 27, count 0 2006.173.08:13:22.29#ibcon#about to read 5, iclass 27, count 0 2006.173.08:13:22.29#ibcon#read 5, iclass 27, count 0 2006.173.08:13:22.29#ibcon#about to read 6, iclass 27, count 0 2006.173.08:13:22.29#ibcon#read 6, iclass 27, count 0 2006.173.08:13:22.29#ibcon#end of sib2, iclass 27, count 0 2006.173.08:13:22.29#ibcon#*after write, iclass 27, count 0 2006.173.08:13:22.29#ibcon#*before return 0, iclass 27, count 0 2006.173.08:13:22.29#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.08:13:22.29#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.08:13:22.29#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.08:13:22.29#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.08:13:22.29$vck44/vb=8,4 2006.173.08:13:22.29#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.08:13:22.29#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.08:13:22.29#ibcon#ireg 11 cls_cnt 2 2006.173.08:13:22.29#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.08:13:22.35#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.08:13:22.35#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.08:13:22.35#ibcon#enter wrdev, iclass 29, count 2 2006.173.08:13:22.35#ibcon#first serial, iclass 29, count 2 2006.173.08:13:22.35#ibcon#enter sib2, iclass 29, count 2 2006.173.08:13:22.35#ibcon#flushed, iclass 29, count 2 2006.173.08:13:22.35#ibcon#about to write, iclass 29, count 2 2006.173.08:13:22.35#ibcon#wrote, iclass 29, count 2 2006.173.08:13:22.35#ibcon#about to read 3, iclass 29, count 2 2006.173.08:13:22.37#ibcon#read 3, iclass 29, count 2 2006.173.08:13:22.37#ibcon#about to read 4, iclass 29, count 2 2006.173.08:13:22.37#ibcon#read 4, iclass 29, count 2 2006.173.08:13:22.37#ibcon#about to read 5, iclass 29, count 2 2006.173.08:13:22.37#ibcon#read 5, iclass 29, count 2 2006.173.08:13:22.37#ibcon#about to read 6, iclass 29, count 2 2006.173.08:13:22.37#ibcon#read 6, iclass 29, count 2 2006.173.08:13:22.37#ibcon#end of sib2, iclass 29, count 2 2006.173.08:13:22.37#ibcon#*mode == 0, iclass 29, count 2 2006.173.08:13:22.37#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.08:13:22.37#ibcon#[27=AT08-04\r\n] 2006.173.08:13:22.37#ibcon#*before write, iclass 29, count 2 2006.173.08:13:22.37#ibcon#enter sib2, iclass 29, count 2 2006.173.08:13:22.37#ibcon#flushed, iclass 29, count 2 2006.173.08:13:22.37#ibcon#about to write, iclass 29, count 2 2006.173.08:13:22.37#ibcon#wrote, iclass 29, count 2 2006.173.08:13:22.37#ibcon#about to read 3, iclass 29, count 2 2006.173.08:13:22.40#ibcon#read 3, iclass 29, count 2 2006.173.08:13:22.40#ibcon#about to read 4, iclass 29, count 2 2006.173.08:13:22.40#ibcon#read 4, iclass 29, count 2 2006.173.08:13:22.40#ibcon#about to read 5, iclass 29, count 2 2006.173.08:13:22.40#ibcon#read 5, iclass 29, count 2 2006.173.08:13:22.40#ibcon#about to read 6, iclass 29, count 2 2006.173.08:13:22.40#ibcon#read 6, iclass 29, count 2 2006.173.08:13:22.40#ibcon#end of sib2, iclass 29, count 2 2006.173.08:13:22.40#ibcon#*after write, iclass 29, count 2 2006.173.08:13:22.40#ibcon#*before return 0, iclass 29, count 2 2006.173.08:13:22.40#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.08:13:22.40#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.08:13:22.40#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.08:13:22.40#ibcon#ireg 7 cls_cnt 0 2006.173.08:13:22.40#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.08:13:22.52#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.08:13:22.52#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.08:13:22.52#ibcon#enter wrdev, iclass 29, count 0 2006.173.08:13:22.52#ibcon#first serial, iclass 29, count 0 2006.173.08:13:22.52#ibcon#enter sib2, iclass 29, count 0 2006.173.08:13:22.52#ibcon#flushed, iclass 29, count 0 2006.173.08:13:22.52#ibcon#about to write, iclass 29, count 0 2006.173.08:13:22.52#ibcon#wrote, iclass 29, count 0 2006.173.08:13:22.52#ibcon#about to read 3, iclass 29, count 0 2006.173.08:13:22.54#ibcon#read 3, iclass 29, count 0 2006.173.08:13:22.54#ibcon#about to read 4, iclass 29, count 0 2006.173.08:13:22.54#ibcon#read 4, iclass 29, count 0 2006.173.08:13:22.54#ibcon#about to read 5, iclass 29, count 0 2006.173.08:13:22.54#ibcon#read 5, iclass 29, count 0 2006.173.08:13:22.54#ibcon#about to read 6, iclass 29, count 0 2006.173.08:13:22.54#ibcon#read 6, iclass 29, count 0 2006.173.08:13:22.54#ibcon#end of sib2, iclass 29, count 0 2006.173.08:13:22.54#ibcon#*mode == 0, iclass 29, count 0 2006.173.08:13:22.54#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.08:13:22.54#ibcon#[27=USB\r\n] 2006.173.08:13:22.54#ibcon#*before write, iclass 29, count 0 2006.173.08:13:22.54#ibcon#enter sib2, iclass 29, count 0 2006.173.08:13:22.54#ibcon#flushed, iclass 29, count 0 2006.173.08:13:22.54#ibcon#about to write, iclass 29, count 0 2006.173.08:13:22.54#ibcon#wrote, iclass 29, count 0 2006.173.08:13:22.54#ibcon#about to read 3, iclass 29, count 0 2006.173.08:13:22.57#ibcon#read 3, iclass 29, count 0 2006.173.08:13:22.57#ibcon#about to read 4, iclass 29, count 0 2006.173.08:13:22.57#ibcon#read 4, iclass 29, count 0 2006.173.08:13:22.57#ibcon#about to read 5, iclass 29, count 0 2006.173.08:13:22.57#ibcon#read 5, iclass 29, count 0 2006.173.08:13:22.57#ibcon#about to read 6, iclass 29, count 0 2006.173.08:13:22.57#ibcon#read 6, iclass 29, count 0 2006.173.08:13:22.57#ibcon#end of sib2, iclass 29, count 0 2006.173.08:13:22.57#ibcon#*after write, iclass 29, count 0 2006.173.08:13:22.57#ibcon#*before return 0, iclass 29, count 0 2006.173.08:13:22.57#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.08:13:22.57#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.08:13:22.57#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.08:13:22.57#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.08:13:22.57$vck44/vabw=wide 2006.173.08:13:22.57#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.08:13:22.57#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.08:13:22.57#ibcon#ireg 8 cls_cnt 0 2006.173.08:13:22.57#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.08:13:22.57#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.08:13:22.57#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.08:13:22.57#ibcon#enter wrdev, iclass 31, count 0 2006.173.08:13:22.57#ibcon#first serial, iclass 31, count 0 2006.173.08:13:22.57#ibcon#enter sib2, iclass 31, count 0 2006.173.08:13:22.57#ibcon#flushed, iclass 31, count 0 2006.173.08:13:22.57#ibcon#about to write, iclass 31, count 0 2006.173.08:13:22.57#ibcon#wrote, iclass 31, count 0 2006.173.08:13:22.57#ibcon#about to read 3, iclass 31, count 0 2006.173.08:13:22.59#ibcon#read 3, iclass 31, count 0 2006.173.08:13:22.59#ibcon#about to read 4, iclass 31, count 0 2006.173.08:13:22.59#ibcon#read 4, iclass 31, count 0 2006.173.08:13:22.59#ibcon#about to read 5, iclass 31, count 0 2006.173.08:13:22.59#ibcon#read 5, iclass 31, count 0 2006.173.08:13:22.59#ibcon#about to read 6, iclass 31, count 0 2006.173.08:13:22.59#ibcon#read 6, iclass 31, count 0 2006.173.08:13:22.59#ibcon#end of sib2, iclass 31, count 0 2006.173.08:13:22.59#ibcon#*mode == 0, iclass 31, count 0 2006.173.08:13:22.59#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.08:13:22.59#ibcon#[25=BW32\r\n] 2006.173.08:13:22.59#ibcon#*before write, iclass 31, count 0 2006.173.08:13:22.59#ibcon#enter sib2, iclass 31, count 0 2006.173.08:13:22.59#ibcon#flushed, iclass 31, count 0 2006.173.08:13:22.59#ibcon#about to write, iclass 31, count 0 2006.173.08:13:22.59#ibcon#wrote, iclass 31, count 0 2006.173.08:13:22.59#ibcon#about to read 3, iclass 31, count 0 2006.173.08:13:22.62#ibcon#read 3, iclass 31, count 0 2006.173.08:13:22.62#ibcon#about to read 4, iclass 31, count 0 2006.173.08:13:22.62#ibcon#read 4, iclass 31, count 0 2006.173.08:13:22.62#ibcon#about to read 5, iclass 31, count 0 2006.173.08:13:22.62#ibcon#read 5, iclass 31, count 0 2006.173.08:13:22.62#ibcon#about to read 6, iclass 31, count 0 2006.173.08:13:22.62#ibcon#read 6, iclass 31, count 0 2006.173.08:13:22.62#ibcon#end of sib2, iclass 31, count 0 2006.173.08:13:22.62#ibcon#*after write, iclass 31, count 0 2006.173.08:13:22.62#ibcon#*before return 0, iclass 31, count 0 2006.173.08:13:22.62#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.08:13:22.62#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.08:13:22.62#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.08:13:22.62#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.08:13:22.62$vck44/vbbw=wide 2006.173.08:13:22.62#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.08:13:22.62#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.08:13:22.62#ibcon#ireg 8 cls_cnt 0 2006.173.08:13:22.62#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.08:13:22.69#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.08:13:22.69#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.08:13:22.69#ibcon#enter wrdev, iclass 33, count 0 2006.173.08:13:22.69#ibcon#first serial, iclass 33, count 0 2006.173.08:13:22.69#ibcon#enter sib2, iclass 33, count 0 2006.173.08:13:22.69#ibcon#flushed, iclass 33, count 0 2006.173.08:13:22.69#ibcon#about to write, iclass 33, count 0 2006.173.08:13:22.69#ibcon#wrote, iclass 33, count 0 2006.173.08:13:22.69#ibcon#about to read 3, iclass 33, count 0 2006.173.08:13:22.71#ibcon#read 3, iclass 33, count 0 2006.173.08:13:22.71#ibcon#about to read 4, iclass 33, count 0 2006.173.08:13:22.71#ibcon#read 4, iclass 33, count 0 2006.173.08:13:22.71#ibcon#about to read 5, iclass 33, count 0 2006.173.08:13:22.71#ibcon#read 5, iclass 33, count 0 2006.173.08:13:22.71#ibcon#about to read 6, iclass 33, count 0 2006.173.08:13:22.71#ibcon#read 6, iclass 33, count 0 2006.173.08:13:22.71#ibcon#end of sib2, iclass 33, count 0 2006.173.08:13:22.71#ibcon#*mode == 0, iclass 33, count 0 2006.173.08:13:22.71#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.08:13:22.71#ibcon#[27=BW32\r\n] 2006.173.08:13:22.71#ibcon#*before write, iclass 33, count 0 2006.173.08:13:22.71#ibcon#enter sib2, iclass 33, count 0 2006.173.08:13:22.71#ibcon#flushed, iclass 33, count 0 2006.173.08:13:22.71#ibcon#about to write, iclass 33, count 0 2006.173.08:13:22.71#ibcon#wrote, iclass 33, count 0 2006.173.08:13:22.71#ibcon#about to read 3, iclass 33, count 0 2006.173.08:13:22.74#ibcon#read 3, iclass 33, count 0 2006.173.08:13:22.74#ibcon#about to read 4, iclass 33, count 0 2006.173.08:13:22.74#ibcon#read 4, iclass 33, count 0 2006.173.08:13:22.74#ibcon#about to read 5, iclass 33, count 0 2006.173.08:13:22.74#ibcon#read 5, iclass 33, count 0 2006.173.08:13:22.74#ibcon#about to read 6, iclass 33, count 0 2006.173.08:13:22.74#ibcon#read 6, iclass 33, count 0 2006.173.08:13:22.74#ibcon#end of sib2, iclass 33, count 0 2006.173.08:13:22.74#ibcon#*after write, iclass 33, count 0 2006.173.08:13:22.74#ibcon#*before return 0, iclass 33, count 0 2006.173.08:13:22.74#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.08:13:22.74#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.08:13:22.74#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.08:13:22.74#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.08:13:22.74$setupk4/ifdk4 2006.173.08:13:22.74$ifdk4/lo= 2006.173.08:13:22.74$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.08:13:22.74$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.08:13:22.74$ifdk4/patch= 2006.173.08:13:22.74$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.08:13:22.74$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.08:13:22.74$setupk4/!*+20s 2006.173.08:13:29.35#abcon#<5=/03 0.6 1.2 23.62 851004.1\r\n> 2006.173.08:13:29.37#abcon#{5=INTERFACE CLEAR} 2006.173.08:13:29.43#abcon#[5=S1D000X0/0*\r\n] 2006.173.08:13:37.25$setupk4/"tpicd 2006.173.08:13:37.25$setupk4/echo=off 2006.173.08:13:37.25$setupk4/xlog=off 2006.173.08:13:37.25:!2006.173.08:15:31 2006.173.08:13:53.14#trakl#Source acquired 2006.173.08:13:55.14#flagr#flagr/antenna,acquired 2006.173.08:15:31.00:preob 2006.173.08:15:32.14/onsource/TRACKING 2006.173.08:15:32.14:!2006.173.08:15:41 2006.173.08:15:41.00:"tape 2006.173.08:15:41.00:"st=record 2006.173.08:15:41.00:data_valid=on 2006.173.08:15:41.00:midob 2006.173.08:15:41.14/onsource/TRACKING 2006.173.08:15:41.14/wx/23.64,1004.1,86 2006.173.08:15:41.25/cable/+6.5016E-03 2006.173.08:15:42.34/va/01,07,usb,yes,35,38 2006.173.08:15:42.34/va/02,06,usb,yes,35,36 2006.173.08:15:42.34/va/03,05,usb,yes,45,46 2006.173.08:15:42.34/va/04,06,usb,yes,36,38 2006.173.08:15:42.34/va/05,04,usb,yes,28,29 2006.173.08:15:42.34/va/06,03,usb,yes,39,39 2006.173.08:15:42.34/va/07,04,usb,yes,32,33 2006.173.08:15:42.34/va/08,04,usb,yes,27,33 2006.173.08:15:42.57/valo/01,524.99,yes,locked 2006.173.08:15:42.57/valo/02,534.99,yes,locked 2006.173.08:15:42.57/valo/03,564.99,yes,locked 2006.173.08:15:42.57/valo/04,624.99,yes,locked 2006.173.08:15:42.57/valo/05,734.99,yes,locked 2006.173.08:15:42.57/valo/06,814.99,yes,locked 2006.173.08:15:42.57/valo/07,864.99,yes,locked 2006.173.08:15:42.57/valo/08,884.99,yes,locked 2006.173.08:15:43.66/vb/01,04,usb,yes,29,27 2006.173.08:15:43.66/vb/02,04,usb,yes,32,32 2006.173.08:15:43.66/vb/03,04,usb,yes,29,32 2006.173.08:15:43.66/vb/04,04,usb,yes,33,32 2006.173.08:15:43.66/vb/05,04,usb,yes,26,28 2006.173.08:15:43.66/vb/06,04,usb,yes,30,26 2006.173.08:15:43.66/vb/07,04,usb,yes,30,30 2006.173.08:15:43.66/vb/08,04,usb,yes,27,31 2006.173.08:15:43.89/vblo/01,629.99,yes,locked 2006.173.08:15:43.89/vblo/02,634.99,yes,locked 2006.173.08:15:43.89/vblo/03,649.99,yes,locked 2006.173.08:15:43.89/vblo/04,679.99,yes,locked 2006.173.08:15:43.89/vblo/05,709.99,yes,locked 2006.173.08:15:43.89/vblo/06,719.99,yes,locked 2006.173.08:15:43.89/vblo/07,734.99,yes,locked 2006.173.08:15:43.89/vblo/08,744.99,yes,locked 2006.173.08:15:44.04/vabw/8 2006.173.08:15:44.19/vbbw/8 2006.173.08:15:44.28/xfe/off,on,14.7 2006.173.08:15:44.66/ifatt/23,28,28,28 2006.173.08:15:45.08/fmout-gps/S +3.88E-07 2006.173.08:15:45.12:!2006.173.08:17:21 2006.173.08:17:21.00:data_valid=off 2006.173.08:17:21.00:"et 2006.173.08:17:21.00:!+3s 2006.173.08:17:24.01:"tape 2006.173.08:17:24.01:postob 2006.173.08:17:24.10/cable/+6.4998E-03 2006.173.08:17:24.10/wx/23.64,1004.1,86 2006.173.08:17:25.08/fmout-gps/S +3.89E-07 2006.173.08:17:25.08:scan_name=173-0818,jd0606,90 2006.173.08:17:25.08:source=3c274,123049.42,122328.0,2000.0,ccw 2006.173.08:17:26.14#flagr#flagr/antenna,new-source 2006.173.08:17:26.14:checkk5 2006.173.08:17:26.50/chk_autoobs//k5ts1/ autoobs is running! 2006.173.08:17:26.90/chk_autoobs//k5ts2/ autoobs is running! 2006.173.08:17:27.32/chk_autoobs//k5ts3/ autoobs is running! 2006.173.08:17:27.72/chk_autoobs//k5ts4/ autoobs is running! 2006.173.08:17:28.11/chk_obsdata//k5ts1/T1730815??a.dat file size is correct (nominal:400MB, actual:396MB). 2006.173.08:17:28.52/chk_obsdata//k5ts2/T1730815??b.dat file size is correct (nominal:400MB, actual:396MB). 2006.173.08:17:28.92/chk_obsdata//k5ts3/T1730815??c.dat file size is correct (nominal:400MB, actual:396MB). 2006.173.08:17:29.33/chk_obsdata//k5ts4/T1730815??d.dat file size is correct (nominal:400MB, actual:396MB). 2006.173.08:17:30.04/k5log//k5ts1_log_newline 2006.173.08:17:30.74/k5log//k5ts2_log_newline 2006.173.08:17:31.44/k5log//k5ts3_log_newline 2006.173.08:17:32.15/k5log//k5ts4_log_newline 2006.173.08:17:32.18/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.08:17:32.18:setupk4=1 2006.173.08:17:32.18$setupk4/echo=on 2006.173.08:17:32.18$setupk4/pcalon 2006.173.08:17:32.18$pcalon/"no phase cal control is implemented here 2006.173.08:17:32.18$setupk4/"tpicd=stop 2006.173.08:17:32.18$setupk4/"rec=synch_on 2006.173.08:17:32.18$setupk4/"rec_mode=128 2006.173.08:17:32.18$setupk4/!* 2006.173.08:17:32.18$setupk4/recpk4 2006.173.08:17:32.18$recpk4/recpatch= 2006.173.08:17:32.19$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.08:17:32.19$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.08:17:32.19$setupk4/vck44 2006.173.08:17:32.19$vck44/valo=1,524.99 2006.173.08:17:32.19#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.08:17:32.19#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.08:17:32.19#ibcon#ireg 17 cls_cnt 0 2006.173.08:17:32.19#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.08:17:32.19#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.08:17:32.19#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.08:17:32.19#ibcon#enter wrdev, iclass 26, count 0 2006.173.08:17:32.19#ibcon#first serial, iclass 26, count 0 2006.173.08:17:32.19#ibcon#enter sib2, iclass 26, count 0 2006.173.08:17:32.19#ibcon#flushed, iclass 26, count 0 2006.173.08:17:32.19#ibcon#about to write, iclass 26, count 0 2006.173.08:17:32.19#ibcon#wrote, iclass 26, count 0 2006.173.08:17:32.19#ibcon#about to read 3, iclass 26, count 0 2006.173.08:17:32.21#ibcon#read 3, iclass 26, count 0 2006.173.08:17:32.21#ibcon#about to read 4, iclass 26, count 0 2006.173.08:17:32.21#ibcon#read 4, iclass 26, count 0 2006.173.08:17:32.21#ibcon#about to read 5, iclass 26, count 0 2006.173.08:17:32.21#ibcon#read 5, iclass 26, count 0 2006.173.08:17:32.21#ibcon#about to read 6, iclass 26, count 0 2006.173.08:17:32.21#ibcon#read 6, iclass 26, count 0 2006.173.08:17:32.21#ibcon#end of sib2, iclass 26, count 0 2006.173.08:17:32.21#ibcon#*mode == 0, iclass 26, count 0 2006.173.08:17:32.21#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.08:17:32.21#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.08:17:32.21#ibcon#*before write, iclass 26, count 0 2006.173.08:17:32.21#ibcon#enter sib2, iclass 26, count 0 2006.173.08:17:32.21#ibcon#flushed, iclass 26, count 0 2006.173.08:17:32.21#ibcon#about to write, iclass 26, count 0 2006.173.08:17:32.21#ibcon#wrote, iclass 26, count 0 2006.173.08:17:32.21#ibcon#about to read 3, iclass 26, count 0 2006.173.08:17:32.26#ibcon#read 3, iclass 26, count 0 2006.173.08:17:32.26#ibcon#about to read 4, iclass 26, count 0 2006.173.08:17:32.26#ibcon#read 4, iclass 26, count 0 2006.173.08:17:32.26#ibcon#about to read 5, iclass 26, count 0 2006.173.08:17:32.26#ibcon#read 5, iclass 26, count 0 2006.173.08:17:32.26#ibcon#about to read 6, iclass 26, count 0 2006.173.08:17:32.26#ibcon#read 6, iclass 26, count 0 2006.173.08:17:32.26#ibcon#end of sib2, iclass 26, count 0 2006.173.08:17:32.26#ibcon#*after write, iclass 26, count 0 2006.173.08:17:32.26#ibcon#*before return 0, iclass 26, count 0 2006.173.08:17:32.26#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.08:17:32.26#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.08:17:32.26#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.08:17:32.26#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.08:17:32.26$vck44/va=1,7 2006.173.08:17:32.26#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.08:17:32.26#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.08:17:32.26#ibcon#ireg 11 cls_cnt 2 2006.173.08:17:32.26#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.08:17:32.26#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.08:17:32.26#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.08:17:32.26#ibcon#enter wrdev, iclass 28, count 2 2006.173.08:17:32.26#ibcon#first serial, iclass 28, count 2 2006.173.08:17:32.26#ibcon#enter sib2, iclass 28, count 2 2006.173.08:17:32.26#ibcon#flushed, iclass 28, count 2 2006.173.08:17:32.26#ibcon#about to write, iclass 28, count 2 2006.173.08:17:32.26#ibcon#wrote, iclass 28, count 2 2006.173.08:17:32.26#ibcon#about to read 3, iclass 28, count 2 2006.173.08:17:32.28#ibcon#read 3, iclass 28, count 2 2006.173.08:17:32.28#ibcon#about to read 4, iclass 28, count 2 2006.173.08:17:32.28#ibcon#read 4, iclass 28, count 2 2006.173.08:17:32.28#ibcon#about to read 5, iclass 28, count 2 2006.173.08:17:32.28#ibcon#read 5, iclass 28, count 2 2006.173.08:17:32.28#ibcon#about to read 6, iclass 28, count 2 2006.173.08:17:32.28#ibcon#read 6, iclass 28, count 2 2006.173.08:17:32.28#ibcon#end of sib2, iclass 28, count 2 2006.173.08:17:32.28#ibcon#*mode == 0, iclass 28, count 2 2006.173.08:17:32.28#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.08:17:32.28#ibcon#[25=AT01-07\r\n] 2006.173.08:17:32.28#ibcon#*before write, iclass 28, count 2 2006.173.08:17:32.28#ibcon#enter sib2, iclass 28, count 2 2006.173.08:17:32.28#ibcon#flushed, iclass 28, count 2 2006.173.08:17:32.28#ibcon#about to write, iclass 28, count 2 2006.173.08:17:32.28#ibcon#wrote, iclass 28, count 2 2006.173.08:17:32.28#ibcon#about to read 3, iclass 28, count 2 2006.173.08:17:32.31#ibcon#read 3, iclass 28, count 2 2006.173.08:17:32.31#ibcon#about to read 4, iclass 28, count 2 2006.173.08:17:32.31#ibcon#read 4, iclass 28, count 2 2006.173.08:17:32.31#ibcon#about to read 5, iclass 28, count 2 2006.173.08:17:32.31#ibcon#read 5, iclass 28, count 2 2006.173.08:17:32.31#ibcon#about to read 6, iclass 28, count 2 2006.173.08:17:32.31#ibcon#read 6, iclass 28, count 2 2006.173.08:17:32.31#ibcon#end of sib2, iclass 28, count 2 2006.173.08:17:32.31#ibcon#*after write, iclass 28, count 2 2006.173.08:17:32.31#ibcon#*before return 0, iclass 28, count 2 2006.173.08:17:32.31#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.08:17:32.31#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.08:17:32.31#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.08:17:32.31#ibcon#ireg 7 cls_cnt 0 2006.173.08:17:32.31#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.08:17:32.43#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.08:17:32.43#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.08:17:32.43#ibcon#enter wrdev, iclass 28, count 0 2006.173.08:17:32.43#ibcon#first serial, iclass 28, count 0 2006.173.08:17:32.43#ibcon#enter sib2, iclass 28, count 0 2006.173.08:17:32.43#ibcon#flushed, iclass 28, count 0 2006.173.08:17:32.43#ibcon#about to write, iclass 28, count 0 2006.173.08:17:32.43#ibcon#wrote, iclass 28, count 0 2006.173.08:17:32.43#ibcon#about to read 3, iclass 28, count 0 2006.173.08:17:32.45#ibcon#read 3, iclass 28, count 0 2006.173.08:17:32.45#ibcon#about to read 4, iclass 28, count 0 2006.173.08:17:32.45#ibcon#read 4, iclass 28, count 0 2006.173.08:17:32.45#ibcon#about to read 5, iclass 28, count 0 2006.173.08:17:32.45#ibcon#read 5, iclass 28, count 0 2006.173.08:17:32.45#ibcon#about to read 6, iclass 28, count 0 2006.173.08:17:32.45#ibcon#read 6, iclass 28, count 0 2006.173.08:17:32.45#ibcon#end of sib2, iclass 28, count 0 2006.173.08:17:32.45#ibcon#*mode == 0, iclass 28, count 0 2006.173.08:17:32.45#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.08:17:32.45#ibcon#[25=USB\r\n] 2006.173.08:17:32.45#ibcon#*before write, iclass 28, count 0 2006.173.08:17:32.45#ibcon#enter sib2, iclass 28, count 0 2006.173.08:17:32.45#ibcon#flushed, iclass 28, count 0 2006.173.08:17:32.45#ibcon#about to write, iclass 28, count 0 2006.173.08:17:32.45#ibcon#wrote, iclass 28, count 0 2006.173.08:17:32.45#ibcon#about to read 3, iclass 28, count 0 2006.173.08:17:32.48#ibcon#read 3, iclass 28, count 0 2006.173.08:17:32.48#ibcon#about to read 4, iclass 28, count 0 2006.173.08:17:32.48#ibcon#read 4, iclass 28, count 0 2006.173.08:17:32.48#ibcon#about to read 5, iclass 28, count 0 2006.173.08:17:32.48#ibcon#read 5, iclass 28, count 0 2006.173.08:17:32.48#ibcon#about to read 6, iclass 28, count 0 2006.173.08:17:32.48#ibcon#read 6, iclass 28, count 0 2006.173.08:17:32.48#ibcon#end of sib2, iclass 28, count 0 2006.173.08:17:32.48#ibcon#*after write, iclass 28, count 0 2006.173.08:17:32.48#ibcon#*before return 0, iclass 28, count 0 2006.173.08:17:32.48#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.08:17:32.48#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.08:17:32.48#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.08:17:32.48#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.08:17:32.48$vck44/valo=2,534.99 2006.173.08:17:32.48#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.08:17:32.48#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.08:17:32.48#ibcon#ireg 17 cls_cnt 0 2006.173.08:17:32.48#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.08:17:32.48#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.08:17:32.48#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.08:17:32.48#ibcon#enter wrdev, iclass 30, count 0 2006.173.08:17:32.48#ibcon#first serial, iclass 30, count 0 2006.173.08:17:32.48#ibcon#enter sib2, iclass 30, count 0 2006.173.08:17:32.48#ibcon#flushed, iclass 30, count 0 2006.173.08:17:32.48#ibcon#about to write, iclass 30, count 0 2006.173.08:17:32.48#ibcon#wrote, iclass 30, count 0 2006.173.08:17:32.48#ibcon#about to read 3, iclass 30, count 0 2006.173.08:17:32.50#ibcon#read 3, iclass 30, count 0 2006.173.08:17:32.50#ibcon#about to read 4, iclass 30, count 0 2006.173.08:17:32.50#ibcon#read 4, iclass 30, count 0 2006.173.08:17:32.50#ibcon#about to read 5, iclass 30, count 0 2006.173.08:17:32.50#ibcon#read 5, iclass 30, count 0 2006.173.08:17:32.50#ibcon#about to read 6, iclass 30, count 0 2006.173.08:17:32.50#ibcon#read 6, iclass 30, count 0 2006.173.08:17:32.50#ibcon#end of sib2, iclass 30, count 0 2006.173.08:17:32.50#ibcon#*mode == 0, iclass 30, count 0 2006.173.08:17:32.50#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.08:17:32.50#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.08:17:32.50#ibcon#*before write, iclass 30, count 0 2006.173.08:17:32.50#ibcon#enter sib2, iclass 30, count 0 2006.173.08:17:32.50#ibcon#flushed, iclass 30, count 0 2006.173.08:17:32.50#ibcon#about to write, iclass 30, count 0 2006.173.08:17:32.50#ibcon#wrote, iclass 30, count 0 2006.173.08:17:32.50#ibcon#about to read 3, iclass 30, count 0 2006.173.08:17:32.54#ibcon#read 3, iclass 30, count 0 2006.173.08:17:32.54#ibcon#about to read 4, iclass 30, count 0 2006.173.08:17:32.54#ibcon#read 4, iclass 30, count 0 2006.173.08:17:32.54#ibcon#about to read 5, iclass 30, count 0 2006.173.08:17:32.54#ibcon#read 5, iclass 30, count 0 2006.173.08:17:32.54#ibcon#about to read 6, iclass 30, count 0 2006.173.08:17:32.54#ibcon#read 6, iclass 30, count 0 2006.173.08:17:32.54#ibcon#end of sib2, iclass 30, count 0 2006.173.08:17:32.54#ibcon#*after write, iclass 30, count 0 2006.173.08:17:32.54#ibcon#*before return 0, iclass 30, count 0 2006.173.08:17:32.54#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.08:17:32.54#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.08:17:32.54#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.08:17:32.54#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.08:17:32.54$vck44/va=2,6 2006.173.08:17:32.54#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.173.08:17:32.54#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.173.08:17:32.54#ibcon#ireg 11 cls_cnt 2 2006.173.08:17:32.54#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.08:17:32.60#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.08:17:32.60#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.08:17:32.60#ibcon#enter wrdev, iclass 32, count 2 2006.173.08:17:32.60#ibcon#first serial, iclass 32, count 2 2006.173.08:17:32.60#ibcon#enter sib2, iclass 32, count 2 2006.173.08:17:32.60#ibcon#flushed, iclass 32, count 2 2006.173.08:17:32.60#ibcon#about to write, iclass 32, count 2 2006.173.08:17:32.60#ibcon#wrote, iclass 32, count 2 2006.173.08:17:32.60#ibcon#about to read 3, iclass 32, count 2 2006.173.08:17:32.62#ibcon#read 3, iclass 32, count 2 2006.173.08:17:32.62#ibcon#about to read 4, iclass 32, count 2 2006.173.08:17:32.62#ibcon#read 4, iclass 32, count 2 2006.173.08:17:32.62#ibcon#about to read 5, iclass 32, count 2 2006.173.08:17:32.62#ibcon#read 5, iclass 32, count 2 2006.173.08:17:32.62#ibcon#about to read 6, iclass 32, count 2 2006.173.08:17:32.62#ibcon#read 6, iclass 32, count 2 2006.173.08:17:32.62#ibcon#end of sib2, iclass 32, count 2 2006.173.08:17:32.62#ibcon#*mode == 0, iclass 32, count 2 2006.173.08:17:32.62#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.173.08:17:32.62#ibcon#[25=AT02-06\r\n] 2006.173.08:17:32.62#ibcon#*before write, iclass 32, count 2 2006.173.08:17:32.62#ibcon#enter sib2, iclass 32, count 2 2006.173.08:17:32.62#ibcon#flushed, iclass 32, count 2 2006.173.08:17:32.62#ibcon#about to write, iclass 32, count 2 2006.173.08:17:32.62#ibcon#wrote, iclass 32, count 2 2006.173.08:17:32.62#ibcon#about to read 3, iclass 32, count 2 2006.173.08:17:32.65#ibcon#read 3, iclass 32, count 2 2006.173.08:17:32.65#ibcon#about to read 4, iclass 32, count 2 2006.173.08:17:32.65#ibcon#read 4, iclass 32, count 2 2006.173.08:17:32.65#ibcon#about to read 5, iclass 32, count 2 2006.173.08:17:32.65#ibcon#read 5, iclass 32, count 2 2006.173.08:17:32.65#ibcon#about to read 6, iclass 32, count 2 2006.173.08:17:32.65#ibcon#read 6, iclass 32, count 2 2006.173.08:17:32.65#ibcon#end of sib2, iclass 32, count 2 2006.173.08:17:32.65#ibcon#*after write, iclass 32, count 2 2006.173.08:17:32.65#ibcon#*before return 0, iclass 32, count 2 2006.173.08:17:32.65#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.08:17:32.65#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.173.08:17:32.65#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.173.08:17:32.65#ibcon#ireg 7 cls_cnt 0 2006.173.08:17:32.65#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.08:17:32.77#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.08:17:32.77#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.08:17:32.77#ibcon#enter wrdev, iclass 32, count 0 2006.173.08:17:32.77#ibcon#first serial, iclass 32, count 0 2006.173.08:17:32.77#ibcon#enter sib2, iclass 32, count 0 2006.173.08:17:32.77#ibcon#flushed, iclass 32, count 0 2006.173.08:17:32.77#ibcon#about to write, iclass 32, count 0 2006.173.08:17:32.77#ibcon#wrote, iclass 32, count 0 2006.173.08:17:32.77#ibcon#about to read 3, iclass 32, count 0 2006.173.08:17:32.79#ibcon#read 3, iclass 32, count 0 2006.173.08:17:32.79#ibcon#about to read 4, iclass 32, count 0 2006.173.08:17:32.79#ibcon#read 4, iclass 32, count 0 2006.173.08:17:32.79#ibcon#about to read 5, iclass 32, count 0 2006.173.08:17:32.79#ibcon#read 5, iclass 32, count 0 2006.173.08:17:32.79#ibcon#about to read 6, iclass 32, count 0 2006.173.08:17:32.79#ibcon#read 6, iclass 32, count 0 2006.173.08:17:32.79#ibcon#end of sib2, iclass 32, count 0 2006.173.08:17:32.79#ibcon#*mode == 0, iclass 32, count 0 2006.173.08:17:32.79#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.08:17:32.79#ibcon#[25=USB\r\n] 2006.173.08:17:32.79#ibcon#*before write, iclass 32, count 0 2006.173.08:17:32.79#ibcon#enter sib2, iclass 32, count 0 2006.173.08:17:32.79#ibcon#flushed, iclass 32, count 0 2006.173.08:17:32.79#ibcon#about to write, iclass 32, count 0 2006.173.08:17:32.79#ibcon#wrote, iclass 32, count 0 2006.173.08:17:32.79#ibcon#about to read 3, iclass 32, count 0 2006.173.08:17:32.82#ibcon#read 3, iclass 32, count 0 2006.173.08:17:32.82#ibcon#about to read 4, iclass 32, count 0 2006.173.08:17:32.82#ibcon#read 4, iclass 32, count 0 2006.173.08:17:32.82#ibcon#about to read 5, iclass 32, count 0 2006.173.08:17:32.82#ibcon#read 5, iclass 32, count 0 2006.173.08:17:32.82#ibcon#about to read 6, iclass 32, count 0 2006.173.08:17:32.82#ibcon#read 6, iclass 32, count 0 2006.173.08:17:32.82#ibcon#end of sib2, iclass 32, count 0 2006.173.08:17:32.82#ibcon#*after write, iclass 32, count 0 2006.173.08:17:32.82#ibcon#*before return 0, iclass 32, count 0 2006.173.08:17:32.82#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.08:17:32.82#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.173.08:17:32.82#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.08:17:32.82#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.08:17:32.82$vck44/valo=3,564.99 2006.173.08:17:32.82#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.08:17:32.82#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.08:17:32.82#ibcon#ireg 17 cls_cnt 0 2006.173.08:17:32.82#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.08:17:32.82#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.08:17:32.82#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.08:17:32.82#ibcon#enter wrdev, iclass 34, count 0 2006.173.08:17:32.82#ibcon#first serial, iclass 34, count 0 2006.173.08:17:32.82#ibcon#enter sib2, iclass 34, count 0 2006.173.08:17:32.82#ibcon#flushed, iclass 34, count 0 2006.173.08:17:32.82#ibcon#about to write, iclass 34, count 0 2006.173.08:17:32.82#ibcon#wrote, iclass 34, count 0 2006.173.08:17:32.82#ibcon#about to read 3, iclass 34, count 0 2006.173.08:17:32.84#ibcon#read 3, iclass 34, count 0 2006.173.08:17:32.84#ibcon#about to read 4, iclass 34, count 0 2006.173.08:17:32.84#ibcon#read 4, iclass 34, count 0 2006.173.08:17:32.84#ibcon#about to read 5, iclass 34, count 0 2006.173.08:17:32.84#ibcon#read 5, iclass 34, count 0 2006.173.08:17:32.84#ibcon#about to read 6, iclass 34, count 0 2006.173.08:17:32.84#ibcon#read 6, iclass 34, count 0 2006.173.08:17:32.84#ibcon#end of sib2, iclass 34, count 0 2006.173.08:17:32.84#ibcon#*mode == 0, iclass 34, count 0 2006.173.08:17:32.84#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.08:17:32.84#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.08:17:32.84#ibcon#*before write, iclass 34, count 0 2006.173.08:17:32.84#ibcon#enter sib2, iclass 34, count 0 2006.173.08:17:32.84#ibcon#flushed, iclass 34, count 0 2006.173.08:17:32.84#ibcon#about to write, iclass 34, count 0 2006.173.08:17:32.84#ibcon#wrote, iclass 34, count 0 2006.173.08:17:32.84#ibcon#about to read 3, iclass 34, count 0 2006.173.08:17:32.88#ibcon#read 3, iclass 34, count 0 2006.173.08:17:32.88#ibcon#about to read 4, iclass 34, count 0 2006.173.08:17:32.88#ibcon#read 4, iclass 34, count 0 2006.173.08:17:32.88#ibcon#about to read 5, iclass 34, count 0 2006.173.08:17:32.88#ibcon#read 5, iclass 34, count 0 2006.173.08:17:32.88#ibcon#about to read 6, iclass 34, count 0 2006.173.08:17:32.88#ibcon#read 6, iclass 34, count 0 2006.173.08:17:32.88#ibcon#end of sib2, iclass 34, count 0 2006.173.08:17:32.88#ibcon#*after write, iclass 34, count 0 2006.173.08:17:32.88#ibcon#*before return 0, iclass 34, count 0 2006.173.08:17:32.88#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.08:17:32.88#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.08:17:32.88#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.08:17:32.88#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.08:17:32.88$vck44/va=3,5 2006.173.08:17:32.88#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.08:17:32.88#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.08:17:32.88#ibcon#ireg 11 cls_cnt 2 2006.173.08:17:32.88#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.08:17:32.94#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.08:17:32.94#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.08:17:32.94#ibcon#enter wrdev, iclass 36, count 2 2006.173.08:17:32.94#ibcon#first serial, iclass 36, count 2 2006.173.08:17:32.94#ibcon#enter sib2, iclass 36, count 2 2006.173.08:17:32.94#ibcon#flushed, iclass 36, count 2 2006.173.08:17:32.94#ibcon#about to write, iclass 36, count 2 2006.173.08:17:32.94#ibcon#wrote, iclass 36, count 2 2006.173.08:17:32.94#ibcon#about to read 3, iclass 36, count 2 2006.173.08:17:32.96#ibcon#read 3, iclass 36, count 2 2006.173.08:17:32.96#ibcon#about to read 4, iclass 36, count 2 2006.173.08:17:32.96#ibcon#read 4, iclass 36, count 2 2006.173.08:17:32.96#ibcon#about to read 5, iclass 36, count 2 2006.173.08:17:32.96#ibcon#read 5, iclass 36, count 2 2006.173.08:17:32.96#ibcon#about to read 6, iclass 36, count 2 2006.173.08:17:32.96#ibcon#read 6, iclass 36, count 2 2006.173.08:17:32.96#ibcon#end of sib2, iclass 36, count 2 2006.173.08:17:32.96#ibcon#*mode == 0, iclass 36, count 2 2006.173.08:17:32.96#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.08:17:32.96#ibcon#[25=AT03-05\r\n] 2006.173.08:17:32.96#ibcon#*before write, iclass 36, count 2 2006.173.08:17:32.96#ibcon#enter sib2, iclass 36, count 2 2006.173.08:17:32.96#ibcon#flushed, iclass 36, count 2 2006.173.08:17:32.96#ibcon#about to write, iclass 36, count 2 2006.173.08:17:32.96#ibcon#wrote, iclass 36, count 2 2006.173.08:17:32.96#ibcon#about to read 3, iclass 36, count 2 2006.173.08:17:32.99#ibcon#read 3, iclass 36, count 2 2006.173.08:17:32.99#ibcon#about to read 4, iclass 36, count 2 2006.173.08:17:32.99#ibcon#read 4, iclass 36, count 2 2006.173.08:17:32.99#ibcon#about to read 5, iclass 36, count 2 2006.173.08:17:32.99#ibcon#read 5, iclass 36, count 2 2006.173.08:17:32.99#ibcon#about to read 6, iclass 36, count 2 2006.173.08:17:32.99#ibcon#read 6, iclass 36, count 2 2006.173.08:17:32.99#ibcon#end of sib2, iclass 36, count 2 2006.173.08:17:32.99#ibcon#*after write, iclass 36, count 2 2006.173.08:17:32.99#ibcon#*before return 0, iclass 36, count 2 2006.173.08:17:32.99#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.08:17:32.99#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.08:17:32.99#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.08:17:32.99#ibcon#ireg 7 cls_cnt 0 2006.173.08:17:32.99#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.08:17:33.11#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.08:17:33.11#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.08:17:33.11#ibcon#enter wrdev, iclass 36, count 0 2006.173.08:17:33.11#ibcon#first serial, iclass 36, count 0 2006.173.08:17:33.11#ibcon#enter sib2, iclass 36, count 0 2006.173.08:17:33.11#ibcon#flushed, iclass 36, count 0 2006.173.08:17:33.11#ibcon#about to write, iclass 36, count 0 2006.173.08:17:33.11#ibcon#wrote, iclass 36, count 0 2006.173.08:17:33.11#ibcon#about to read 3, iclass 36, count 0 2006.173.08:17:33.13#ibcon#read 3, iclass 36, count 0 2006.173.08:17:33.13#ibcon#about to read 4, iclass 36, count 0 2006.173.08:17:33.13#ibcon#read 4, iclass 36, count 0 2006.173.08:17:33.13#ibcon#about to read 5, iclass 36, count 0 2006.173.08:17:33.13#ibcon#read 5, iclass 36, count 0 2006.173.08:17:33.13#ibcon#about to read 6, iclass 36, count 0 2006.173.08:17:33.13#ibcon#read 6, iclass 36, count 0 2006.173.08:17:33.13#ibcon#end of sib2, iclass 36, count 0 2006.173.08:17:33.13#ibcon#*mode == 0, iclass 36, count 0 2006.173.08:17:33.13#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.08:17:33.13#ibcon#[25=USB\r\n] 2006.173.08:17:33.13#ibcon#*before write, iclass 36, count 0 2006.173.08:17:33.13#ibcon#enter sib2, iclass 36, count 0 2006.173.08:17:33.13#ibcon#flushed, iclass 36, count 0 2006.173.08:17:33.13#ibcon#about to write, iclass 36, count 0 2006.173.08:17:33.13#ibcon#wrote, iclass 36, count 0 2006.173.08:17:33.13#ibcon#about to read 3, iclass 36, count 0 2006.173.08:17:33.16#ibcon#read 3, iclass 36, count 0 2006.173.08:17:33.16#ibcon#about to read 4, iclass 36, count 0 2006.173.08:17:33.16#ibcon#read 4, iclass 36, count 0 2006.173.08:17:33.16#ibcon#about to read 5, iclass 36, count 0 2006.173.08:17:33.16#ibcon#read 5, iclass 36, count 0 2006.173.08:17:33.16#ibcon#about to read 6, iclass 36, count 0 2006.173.08:17:33.16#ibcon#read 6, iclass 36, count 0 2006.173.08:17:33.16#ibcon#end of sib2, iclass 36, count 0 2006.173.08:17:33.16#ibcon#*after write, iclass 36, count 0 2006.173.08:17:33.16#ibcon#*before return 0, iclass 36, count 0 2006.173.08:17:33.16#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.08:17:33.16#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.08:17:33.16#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.08:17:33.16#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.08:17:33.16$vck44/valo=4,624.99 2006.173.08:17:33.16#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.08:17:33.16#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.08:17:33.16#ibcon#ireg 17 cls_cnt 0 2006.173.08:17:33.16#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.08:17:33.16#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.08:17:33.16#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.08:17:33.16#ibcon#enter wrdev, iclass 38, count 0 2006.173.08:17:33.16#ibcon#first serial, iclass 38, count 0 2006.173.08:17:33.16#ibcon#enter sib2, iclass 38, count 0 2006.173.08:17:33.16#ibcon#flushed, iclass 38, count 0 2006.173.08:17:33.16#ibcon#about to write, iclass 38, count 0 2006.173.08:17:33.16#ibcon#wrote, iclass 38, count 0 2006.173.08:17:33.16#ibcon#about to read 3, iclass 38, count 0 2006.173.08:17:33.18#ibcon#read 3, iclass 38, count 0 2006.173.08:17:33.18#ibcon#about to read 4, iclass 38, count 0 2006.173.08:17:33.18#ibcon#read 4, iclass 38, count 0 2006.173.08:17:33.18#ibcon#about to read 5, iclass 38, count 0 2006.173.08:17:33.18#ibcon#read 5, iclass 38, count 0 2006.173.08:17:33.18#ibcon#about to read 6, iclass 38, count 0 2006.173.08:17:33.18#ibcon#read 6, iclass 38, count 0 2006.173.08:17:33.18#ibcon#end of sib2, iclass 38, count 0 2006.173.08:17:33.18#ibcon#*mode == 0, iclass 38, count 0 2006.173.08:17:33.18#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.08:17:33.18#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.08:17:33.18#ibcon#*before write, iclass 38, count 0 2006.173.08:17:33.18#ibcon#enter sib2, iclass 38, count 0 2006.173.08:17:33.18#ibcon#flushed, iclass 38, count 0 2006.173.08:17:33.18#ibcon#about to write, iclass 38, count 0 2006.173.08:17:33.18#ibcon#wrote, iclass 38, count 0 2006.173.08:17:33.18#ibcon#about to read 3, iclass 38, count 0 2006.173.08:17:33.22#ibcon#read 3, iclass 38, count 0 2006.173.08:17:33.22#ibcon#about to read 4, iclass 38, count 0 2006.173.08:17:33.22#ibcon#read 4, iclass 38, count 0 2006.173.08:17:33.22#ibcon#about to read 5, iclass 38, count 0 2006.173.08:17:33.22#ibcon#read 5, iclass 38, count 0 2006.173.08:17:33.22#ibcon#about to read 6, iclass 38, count 0 2006.173.08:17:33.22#ibcon#read 6, iclass 38, count 0 2006.173.08:17:33.22#ibcon#end of sib2, iclass 38, count 0 2006.173.08:17:33.22#ibcon#*after write, iclass 38, count 0 2006.173.08:17:33.22#ibcon#*before return 0, iclass 38, count 0 2006.173.08:17:33.22#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.08:17:33.22#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.08:17:33.22#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.08:17:33.22#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.08:17:33.22$vck44/va=4,6 2006.173.08:17:33.22#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.08:17:33.22#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.08:17:33.22#ibcon#ireg 11 cls_cnt 2 2006.173.08:17:33.22#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.08:17:33.28#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.08:17:33.28#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.08:17:33.28#ibcon#enter wrdev, iclass 40, count 2 2006.173.08:17:33.28#ibcon#first serial, iclass 40, count 2 2006.173.08:17:33.28#ibcon#enter sib2, iclass 40, count 2 2006.173.08:17:33.28#ibcon#flushed, iclass 40, count 2 2006.173.08:17:33.28#ibcon#about to write, iclass 40, count 2 2006.173.08:17:33.28#ibcon#wrote, iclass 40, count 2 2006.173.08:17:33.28#ibcon#about to read 3, iclass 40, count 2 2006.173.08:17:33.30#ibcon#read 3, iclass 40, count 2 2006.173.08:17:33.30#ibcon#about to read 4, iclass 40, count 2 2006.173.08:17:33.30#ibcon#read 4, iclass 40, count 2 2006.173.08:17:33.30#ibcon#about to read 5, iclass 40, count 2 2006.173.08:17:33.30#ibcon#read 5, iclass 40, count 2 2006.173.08:17:33.30#ibcon#about to read 6, iclass 40, count 2 2006.173.08:17:33.30#ibcon#read 6, iclass 40, count 2 2006.173.08:17:33.30#ibcon#end of sib2, iclass 40, count 2 2006.173.08:17:33.30#ibcon#*mode == 0, iclass 40, count 2 2006.173.08:17:33.30#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.08:17:33.30#ibcon#[25=AT04-06\r\n] 2006.173.08:17:33.30#ibcon#*before write, iclass 40, count 2 2006.173.08:17:33.30#ibcon#enter sib2, iclass 40, count 2 2006.173.08:17:33.30#ibcon#flushed, iclass 40, count 2 2006.173.08:17:33.30#ibcon#about to write, iclass 40, count 2 2006.173.08:17:33.30#ibcon#wrote, iclass 40, count 2 2006.173.08:17:33.30#ibcon#about to read 3, iclass 40, count 2 2006.173.08:17:33.33#ibcon#read 3, iclass 40, count 2 2006.173.08:17:33.33#ibcon#about to read 4, iclass 40, count 2 2006.173.08:17:33.33#ibcon#read 4, iclass 40, count 2 2006.173.08:17:33.33#ibcon#about to read 5, iclass 40, count 2 2006.173.08:17:33.33#ibcon#read 5, iclass 40, count 2 2006.173.08:17:33.33#ibcon#about to read 6, iclass 40, count 2 2006.173.08:17:33.33#ibcon#read 6, iclass 40, count 2 2006.173.08:17:33.33#ibcon#end of sib2, iclass 40, count 2 2006.173.08:17:33.33#ibcon#*after write, iclass 40, count 2 2006.173.08:17:33.33#ibcon#*before return 0, iclass 40, count 2 2006.173.08:17:33.33#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.08:17:33.33#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.08:17:33.33#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.08:17:33.33#ibcon#ireg 7 cls_cnt 0 2006.173.08:17:33.33#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.08:17:33.43#abcon#<5=/04 0.3 1.0 23.64 861004.1\r\n> 2006.173.08:17:33.45#abcon#{5=INTERFACE CLEAR} 2006.173.08:17:33.45#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.08:17:33.45#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.08:17:33.45#ibcon#enter wrdev, iclass 40, count 0 2006.173.08:17:33.45#ibcon#first serial, iclass 40, count 0 2006.173.08:17:33.45#ibcon#enter sib2, iclass 40, count 0 2006.173.08:17:33.45#ibcon#flushed, iclass 40, count 0 2006.173.08:17:33.45#ibcon#about to write, iclass 40, count 0 2006.173.08:17:33.45#ibcon#wrote, iclass 40, count 0 2006.173.08:17:33.45#ibcon#about to read 3, iclass 40, count 0 2006.173.08:17:33.47#ibcon#read 3, iclass 40, count 0 2006.173.08:17:33.47#ibcon#about to read 4, iclass 40, count 0 2006.173.08:17:33.47#ibcon#read 4, iclass 40, count 0 2006.173.08:17:33.47#ibcon#about to read 5, iclass 40, count 0 2006.173.08:17:33.47#ibcon#read 5, iclass 40, count 0 2006.173.08:17:33.47#ibcon#about to read 6, iclass 40, count 0 2006.173.08:17:33.47#ibcon#read 6, iclass 40, count 0 2006.173.08:17:33.47#ibcon#end of sib2, iclass 40, count 0 2006.173.08:17:33.47#ibcon#*mode == 0, iclass 40, count 0 2006.173.08:17:33.47#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.08:17:33.47#ibcon#[25=USB\r\n] 2006.173.08:17:33.47#ibcon#*before write, iclass 40, count 0 2006.173.08:17:33.47#ibcon#enter sib2, iclass 40, count 0 2006.173.08:17:33.47#ibcon#flushed, iclass 40, count 0 2006.173.08:17:33.47#ibcon#about to write, iclass 40, count 0 2006.173.08:17:33.47#ibcon#wrote, iclass 40, count 0 2006.173.08:17:33.47#ibcon#about to read 3, iclass 40, count 0 2006.173.08:17:33.50#ibcon#read 3, iclass 40, count 0 2006.173.08:17:33.50#ibcon#about to read 4, iclass 40, count 0 2006.173.08:17:33.50#ibcon#read 4, iclass 40, count 0 2006.173.08:17:33.50#ibcon#about to read 5, iclass 40, count 0 2006.173.08:17:33.50#ibcon#read 5, iclass 40, count 0 2006.173.08:17:33.50#ibcon#about to read 6, iclass 40, count 0 2006.173.08:17:33.50#ibcon#read 6, iclass 40, count 0 2006.173.08:17:33.50#ibcon#end of sib2, iclass 40, count 0 2006.173.08:17:33.50#ibcon#*after write, iclass 40, count 0 2006.173.08:17:33.50#ibcon#*before return 0, iclass 40, count 0 2006.173.08:17:33.50#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.08:17:33.50#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.08:17:33.50#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.08:17:33.50#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.08:17:33.50$vck44/valo=5,734.99 2006.173.08:17:33.50#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.08:17:33.50#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.08:17:33.50#ibcon#ireg 17 cls_cnt 0 2006.173.08:17:33.50#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.08:17:33.50#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.08:17:33.50#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.08:17:33.50#ibcon#enter wrdev, iclass 10, count 0 2006.173.08:17:33.50#ibcon#first serial, iclass 10, count 0 2006.173.08:17:33.50#ibcon#enter sib2, iclass 10, count 0 2006.173.08:17:33.50#ibcon#flushed, iclass 10, count 0 2006.173.08:17:33.50#ibcon#about to write, iclass 10, count 0 2006.173.08:17:33.50#ibcon#wrote, iclass 10, count 0 2006.173.08:17:33.50#ibcon#about to read 3, iclass 10, count 0 2006.173.08:17:33.51#abcon#[5=S1D000X0/0*\r\n] 2006.173.08:17:33.52#ibcon#read 3, iclass 10, count 0 2006.173.08:17:33.52#ibcon#about to read 4, iclass 10, count 0 2006.173.08:17:33.52#ibcon#read 4, iclass 10, count 0 2006.173.08:17:33.52#ibcon#about to read 5, iclass 10, count 0 2006.173.08:17:33.52#ibcon#read 5, iclass 10, count 0 2006.173.08:17:33.52#ibcon#about to read 6, iclass 10, count 0 2006.173.08:17:33.52#ibcon#read 6, iclass 10, count 0 2006.173.08:17:33.52#ibcon#end of sib2, iclass 10, count 0 2006.173.08:17:33.52#ibcon#*mode == 0, iclass 10, count 0 2006.173.08:17:33.52#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.08:17:33.52#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.08:17:33.52#ibcon#*before write, iclass 10, count 0 2006.173.08:17:33.52#ibcon#enter sib2, iclass 10, count 0 2006.173.08:17:33.52#ibcon#flushed, iclass 10, count 0 2006.173.08:17:33.52#ibcon#about to write, iclass 10, count 0 2006.173.08:17:33.52#ibcon#wrote, iclass 10, count 0 2006.173.08:17:33.52#ibcon#about to read 3, iclass 10, count 0 2006.173.08:17:33.56#ibcon#read 3, iclass 10, count 0 2006.173.08:17:33.56#ibcon#about to read 4, iclass 10, count 0 2006.173.08:17:33.56#ibcon#read 4, iclass 10, count 0 2006.173.08:17:33.56#ibcon#about to read 5, iclass 10, count 0 2006.173.08:17:33.56#ibcon#read 5, iclass 10, count 0 2006.173.08:17:33.56#ibcon#about to read 6, iclass 10, count 0 2006.173.08:17:33.56#ibcon#read 6, iclass 10, count 0 2006.173.08:17:33.56#ibcon#end of sib2, iclass 10, count 0 2006.173.08:17:33.56#ibcon#*after write, iclass 10, count 0 2006.173.08:17:33.56#ibcon#*before return 0, iclass 10, count 0 2006.173.08:17:33.56#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.08:17:33.56#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.08:17:33.56#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.08:17:33.56#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.08:17:33.56$vck44/va=5,4 2006.173.08:17:33.56#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.08:17:33.56#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.08:17:33.56#ibcon#ireg 11 cls_cnt 2 2006.173.08:17:33.56#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.08:17:33.62#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.08:17:33.62#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.08:17:33.62#ibcon#enter wrdev, iclass 12, count 2 2006.173.08:17:33.62#ibcon#first serial, iclass 12, count 2 2006.173.08:17:33.62#ibcon#enter sib2, iclass 12, count 2 2006.173.08:17:33.62#ibcon#flushed, iclass 12, count 2 2006.173.08:17:33.62#ibcon#about to write, iclass 12, count 2 2006.173.08:17:33.62#ibcon#wrote, iclass 12, count 2 2006.173.08:17:33.62#ibcon#about to read 3, iclass 12, count 2 2006.173.08:17:33.64#ibcon#read 3, iclass 12, count 2 2006.173.08:17:33.64#ibcon#about to read 4, iclass 12, count 2 2006.173.08:17:33.64#ibcon#read 4, iclass 12, count 2 2006.173.08:17:33.64#ibcon#about to read 5, iclass 12, count 2 2006.173.08:17:33.64#ibcon#read 5, iclass 12, count 2 2006.173.08:17:33.64#ibcon#about to read 6, iclass 12, count 2 2006.173.08:17:33.64#ibcon#read 6, iclass 12, count 2 2006.173.08:17:33.64#ibcon#end of sib2, iclass 12, count 2 2006.173.08:17:33.64#ibcon#*mode == 0, iclass 12, count 2 2006.173.08:17:33.64#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.08:17:33.64#ibcon#[25=AT05-04\r\n] 2006.173.08:17:33.64#ibcon#*before write, iclass 12, count 2 2006.173.08:17:33.64#ibcon#enter sib2, iclass 12, count 2 2006.173.08:17:33.64#ibcon#flushed, iclass 12, count 2 2006.173.08:17:33.64#ibcon#about to write, iclass 12, count 2 2006.173.08:17:33.64#ibcon#wrote, iclass 12, count 2 2006.173.08:17:33.64#ibcon#about to read 3, iclass 12, count 2 2006.173.08:17:33.67#ibcon#read 3, iclass 12, count 2 2006.173.08:17:33.67#ibcon#about to read 4, iclass 12, count 2 2006.173.08:17:33.67#ibcon#read 4, iclass 12, count 2 2006.173.08:17:33.67#ibcon#about to read 5, iclass 12, count 2 2006.173.08:17:33.67#ibcon#read 5, iclass 12, count 2 2006.173.08:17:33.67#ibcon#about to read 6, iclass 12, count 2 2006.173.08:17:33.67#ibcon#read 6, iclass 12, count 2 2006.173.08:17:33.67#ibcon#end of sib2, iclass 12, count 2 2006.173.08:17:33.67#ibcon#*after write, iclass 12, count 2 2006.173.08:17:33.67#ibcon#*before return 0, iclass 12, count 2 2006.173.08:17:33.67#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.08:17:33.67#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.08:17:33.67#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.08:17:33.67#ibcon#ireg 7 cls_cnt 0 2006.173.08:17:33.67#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.08:17:33.79#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.08:17:33.79#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.08:17:33.79#ibcon#enter wrdev, iclass 12, count 0 2006.173.08:17:33.79#ibcon#first serial, iclass 12, count 0 2006.173.08:17:33.79#ibcon#enter sib2, iclass 12, count 0 2006.173.08:17:33.79#ibcon#flushed, iclass 12, count 0 2006.173.08:17:33.79#ibcon#about to write, iclass 12, count 0 2006.173.08:17:33.79#ibcon#wrote, iclass 12, count 0 2006.173.08:17:33.79#ibcon#about to read 3, iclass 12, count 0 2006.173.08:17:33.81#ibcon#read 3, iclass 12, count 0 2006.173.08:17:33.81#ibcon#about to read 4, iclass 12, count 0 2006.173.08:17:33.81#ibcon#read 4, iclass 12, count 0 2006.173.08:17:33.81#ibcon#about to read 5, iclass 12, count 0 2006.173.08:17:33.81#ibcon#read 5, iclass 12, count 0 2006.173.08:17:33.81#ibcon#about to read 6, iclass 12, count 0 2006.173.08:17:33.81#ibcon#read 6, iclass 12, count 0 2006.173.08:17:33.81#ibcon#end of sib2, iclass 12, count 0 2006.173.08:17:33.81#ibcon#*mode == 0, iclass 12, count 0 2006.173.08:17:33.81#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.08:17:33.81#ibcon#[25=USB\r\n] 2006.173.08:17:33.81#ibcon#*before write, iclass 12, count 0 2006.173.08:17:33.81#ibcon#enter sib2, iclass 12, count 0 2006.173.08:17:33.81#ibcon#flushed, iclass 12, count 0 2006.173.08:17:33.81#ibcon#about to write, iclass 12, count 0 2006.173.08:17:33.81#ibcon#wrote, iclass 12, count 0 2006.173.08:17:33.81#ibcon#about to read 3, iclass 12, count 0 2006.173.08:17:33.84#ibcon#read 3, iclass 12, count 0 2006.173.08:17:33.84#ibcon#about to read 4, iclass 12, count 0 2006.173.08:17:33.84#ibcon#read 4, iclass 12, count 0 2006.173.08:17:33.84#ibcon#about to read 5, iclass 12, count 0 2006.173.08:17:33.84#ibcon#read 5, iclass 12, count 0 2006.173.08:17:33.84#ibcon#about to read 6, iclass 12, count 0 2006.173.08:17:33.84#ibcon#read 6, iclass 12, count 0 2006.173.08:17:33.84#ibcon#end of sib2, iclass 12, count 0 2006.173.08:17:33.84#ibcon#*after write, iclass 12, count 0 2006.173.08:17:33.84#ibcon#*before return 0, iclass 12, count 0 2006.173.08:17:33.84#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.08:17:33.84#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.08:17:33.84#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.08:17:33.84#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.08:17:33.84$vck44/valo=6,814.99 2006.173.08:17:33.84#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.08:17:33.84#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.08:17:33.84#ibcon#ireg 17 cls_cnt 0 2006.173.08:17:33.84#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.08:17:33.84#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.08:17:33.84#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.08:17:33.84#ibcon#enter wrdev, iclass 14, count 0 2006.173.08:17:33.84#ibcon#first serial, iclass 14, count 0 2006.173.08:17:33.84#ibcon#enter sib2, iclass 14, count 0 2006.173.08:17:33.84#ibcon#flushed, iclass 14, count 0 2006.173.08:17:33.84#ibcon#about to write, iclass 14, count 0 2006.173.08:17:33.84#ibcon#wrote, iclass 14, count 0 2006.173.08:17:33.84#ibcon#about to read 3, iclass 14, count 0 2006.173.08:17:33.86#ibcon#read 3, iclass 14, count 0 2006.173.08:17:33.86#ibcon#about to read 4, iclass 14, count 0 2006.173.08:17:33.86#ibcon#read 4, iclass 14, count 0 2006.173.08:17:33.86#ibcon#about to read 5, iclass 14, count 0 2006.173.08:17:33.86#ibcon#read 5, iclass 14, count 0 2006.173.08:17:33.86#ibcon#about to read 6, iclass 14, count 0 2006.173.08:17:33.86#ibcon#read 6, iclass 14, count 0 2006.173.08:17:33.86#ibcon#end of sib2, iclass 14, count 0 2006.173.08:17:33.86#ibcon#*mode == 0, iclass 14, count 0 2006.173.08:17:33.86#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.08:17:33.86#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.08:17:33.86#ibcon#*before write, iclass 14, count 0 2006.173.08:17:33.86#ibcon#enter sib2, iclass 14, count 0 2006.173.08:17:33.86#ibcon#flushed, iclass 14, count 0 2006.173.08:17:33.86#ibcon#about to write, iclass 14, count 0 2006.173.08:17:33.86#ibcon#wrote, iclass 14, count 0 2006.173.08:17:33.86#ibcon#about to read 3, iclass 14, count 0 2006.173.08:17:33.90#ibcon#read 3, iclass 14, count 0 2006.173.08:17:33.90#ibcon#about to read 4, iclass 14, count 0 2006.173.08:17:33.90#ibcon#read 4, iclass 14, count 0 2006.173.08:17:33.90#ibcon#about to read 5, iclass 14, count 0 2006.173.08:17:33.90#ibcon#read 5, iclass 14, count 0 2006.173.08:17:33.90#ibcon#about to read 6, iclass 14, count 0 2006.173.08:17:33.90#ibcon#read 6, iclass 14, count 0 2006.173.08:17:33.90#ibcon#end of sib2, iclass 14, count 0 2006.173.08:17:33.90#ibcon#*after write, iclass 14, count 0 2006.173.08:17:33.90#ibcon#*before return 0, iclass 14, count 0 2006.173.08:17:33.90#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.08:17:33.90#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.08:17:33.90#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.08:17:33.90#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.08:17:33.90$vck44/va=6,3 2006.173.08:17:33.90#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.08:17:33.90#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.08:17:33.90#ibcon#ireg 11 cls_cnt 2 2006.173.08:17:33.90#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.08:17:33.96#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.08:17:33.96#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.08:17:33.96#ibcon#enter wrdev, iclass 16, count 2 2006.173.08:17:33.96#ibcon#first serial, iclass 16, count 2 2006.173.08:17:33.96#ibcon#enter sib2, iclass 16, count 2 2006.173.08:17:33.96#ibcon#flushed, iclass 16, count 2 2006.173.08:17:33.96#ibcon#about to write, iclass 16, count 2 2006.173.08:17:33.96#ibcon#wrote, iclass 16, count 2 2006.173.08:17:33.96#ibcon#about to read 3, iclass 16, count 2 2006.173.08:17:33.98#ibcon#read 3, iclass 16, count 2 2006.173.08:17:33.98#ibcon#about to read 4, iclass 16, count 2 2006.173.08:17:33.98#ibcon#read 4, iclass 16, count 2 2006.173.08:17:33.98#ibcon#about to read 5, iclass 16, count 2 2006.173.08:17:33.98#ibcon#read 5, iclass 16, count 2 2006.173.08:17:33.98#ibcon#about to read 6, iclass 16, count 2 2006.173.08:17:33.98#ibcon#read 6, iclass 16, count 2 2006.173.08:17:33.98#ibcon#end of sib2, iclass 16, count 2 2006.173.08:17:33.98#ibcon#*mode == 0, iclass 16, count 2 2006.173.08:17:33.98#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.08:17:33.98#ibcon#[25=AT06-03\r\n] 2006.173.08:17:33.98#ibcon#*before write, iclass 16, count 2 2006.173.08:17:33.98#ibcon#enter sib2, iclass 16, count 2 2006.173.08:17:33.98#ibcon#flushed, iclass 16, count 2 2006.173.08:17:33.98#ibcon#about to write, iclass 16, count 2 2006.173.08:17:33.98#ibcon#wrote, iclass 16, count 2 2006.173.08:17:33.98#ibcon#about to read 3, iclass 16, count 2 2006.173.08:17:34.01#ibcon#read 3, iclass 16, count 2 2006.173.08:17:34.01#ibcon#about to read 4, iclass 16, count 2 2006.173.08:17:34.01#ibcon#read 4, iclass 16, count 2 2006.173.08:17:34.01#ibcon#about to read 5, iclass 16, count 2 2006.173.08:17:34.01#ibcon#read 5, iclass 16, count 2 2006.173.08:17:34.01#ibcon#about to read 6, iclass 16, count 2 2006.173.08:17:34.01#ibcon#read 6, iclass 16, count 2 2006.173.08:17:34.01#ibcon#end of sib2, iclass 16, count 2 2006.173.08:17:34.01#ibcon#*after write, iclass 16, count 2 2006.173.08:17:34.01#ibcon#*before return 0, iclass 16, count 2 2006.173.08:17:34.01#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.08:17:34.01#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.08:17:34.01#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.08:17:34.01#ibcon#ireg 7 cls_cnt 0 2006.173.08:17:34.01#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.08:17:34.13#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.08:17:34.13#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.08:17:34.13#ibcon#enter wrdev, iclass 16, count 0 2006.173.08:17:34.13#ibcon#first serial, iclass 16, count 0 2006.173.08:17:34.13#ibcon#enter sib2, iclass 16, count 0 2006.173.08:17:34.13#ibcon#flushed, iclass 16, count 0 2006.173.08:17:34.13#ibcon#about to write, iclass 16, count 0 2006.173.08:17:34.13#ibcon#wrote, iclass 16, count 0 2006.173.08:17:34.13#ibcon#about to read 3, iclass 16, count 0 2006.173.08:17:34.15#ibcon#read 3, iclass 16, count 0 2006.173.08:17:34.15#ibcon#about to read 4, iclass 16, count 0 2006.173.08:17:34.15#ibcon#read 4, iclass 16, count 0 2006.173.08:17:34.15#ibcon#about to read 5, iclass 16, count 0 2006.173.08:17:34.15#ibcon#read 5, iclass 16, count 0 2006.173.08:17:34.15#ibcon#about to read 6, iclass 16, count 0 2006.173.08:17:34.15#ibcon#read 6, iclass 16, count 0 2006.173.08:17:34.15#ibcon#end of sib2, iclass 16, count 0 2006.173.08:17:34.15#ibcon#*mode == 0, iclass 16, count 0 2006.173.08:17:34.15#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.08:17:34.15#ibcon#[25=USB\r\n] 2006.173.08:17:34.15#ibcon#*before write, iclass 16, count 0 2006.173.08:17:34.15#ibcon#enter sib2, iclass 16, count 0 2006.173.08:17:34.15#ibcon#flushed, iclass 16, count 0 2006.173.08:17:34.15#ibcon#about to write, iclass 16, count 0 2006.173.08:17:34.15#ibcon#wrote, iclass 16, count 0 2006.173.08:17:34.15#ibcon#about to read 3, iclass 16, count 0 2006.173.08:17:34.18#ibcon#read 3, iclass 16, count 0 2006.173.08:17:34.18#ibcon#about to read 4, iclass 16, count 0 2006.173.08:17:34.18#ibcon#read 4, iclass 16, count 0 2006.173.08:17:34.18#ibcon#about to read 5, iclass 16, count 0 2006.173.08:17:34.18#ibcon#read 5, iclass 16, count 0 2006.173.08:17:34.18#ibcon#about to read 6, iclass 16, count 0 2006.173.08:17:34.18#ibcon#read 6, iclass 16, count 0 2006.173.08:17:34.18#ibcon#end of sib2, iclass 16, count 0 2006.173.08:17:34.18#ibcon#*after write, iclass 16, count 0 2006.173.08:17:34.18#ibcon#*before return 0, iclass 16, count 0 2006.173.08:17:34.18#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.08:17:34.18#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.08:17:34.18#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.08:17:34.18#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.08:17:34.18$vck44/valo=7,864.99 2006.173.08:17:34.18#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.08:17:34.18#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.08:17:34.18#ibcon#ireg 17 cls_cnt 0 2006.173.08:17:34.18#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.08:17:34.18#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.08:17:34.18#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.08:17:34.18#ibcon#enter wrdev, iclass 18, count 0 2006.173.08:17:34.18#ibcon#first serial, iclass 18, count 0 2006.173.08:17:34.18#ibcon#enter sib2, iclass 18, count 0 2006.173.08:17:34.18#ibcon#flushed, iclass 18, count 0 2006.173.08:17:34.18#ibcon#about to write, iclass 18, count 0 2006.173.08:17:34.18#ibcon#wrote, iclass 18, count 0 2006.173.08:17:34.18#ibcon#about to read 3, iclass 18, count 0 2006.173.08:17:34.20#ibcon#read 3, iclass 18, count 0 2006.173.08:17:34.20#ibcon#about to read 4, iclass 18, count 0 2006.173.08:17:34.20#ibcon#read 4, iclass 18, count 0 2006.173.08:17:34.20#ibcon#about to read 5, iclass 18, count 0 2006.173.08:17:34.20#ibcon#read 5, iclass 18, count 0 2006.173.08:17:34.20#ibcon#about to read 6, iclass 18, count 0 2006.173.08:17:34.20#ibcon#read 6, iclass 18, count 0 2006.173.08:17:34.20#ibcon#end of sib2, iclass 18, count 0 2006.173.08:17:34.20#ibcon#*mode == 0, iclass 18, count 0 2006.173.08:17:34.20#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.08:17:34.20#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.08:17:34.20#ibcon#*before write, iclass 18, count 0 2006.173.08:17:34.20#ibcon#enter sib2, iclass 18, count 0 2006.173.08:17:34.20#ibcon#flushed, iclass 18, count 0 2006.173.08:17:34.20#ibcon#about to write, iclass 18, count 0 2006.173.08:17:34.20#ibcon#wrote, iclass 18, count 0 2006.173.08:17:34.20#ibcon#about to read 3, iclass 18, count 0 2006.173.08:17:34.24#ibcon#read 3, iclass 18, count 0 2006.173.08:17:34.24#ibcon#about to read 4, iclass 18, count 0 2006.173.08:17:34.24#ibcon#read 4, iclass 18, count 0 2006.173.08:17:34.24#ibcon#about to read 5, iclass 18, count 0 2006.173.08:17:34.24#ibcon#read 5, iclass 18, count 0 2006.173.08:17:34.24#ibcon#about to read 6, iclass 18, count 0 2006.173.08:17:34.24#ibcon#read 6, iclass 18, count 0 2006.173.08:17:34.24#ibcon#end of sib2, iclass 18, count 0 2006.173.08:17:34.24#ibcon#*after write, iclass 18, count 0 2006.173.08:17:34.24#ibcon#*before return 0, iclass 18, count 0 2006.173.08:17:34.24#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.08:17:34.24#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.08:17:34.24#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.08:17:34.24#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.08:17:34.24$vck44/va=7,4 2006.173.08:17:34.24#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.08:17:34.24#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.08:17:34.24#ibcon#ireg 11 cls_cnt 2 2006.173.08:17:34.24#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.08:17:34.30#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.08:17:34.30#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.08:17:34.30#ibcon#enter wrdev, iclass 20, count 2 2006.173.08:17:34.30#ibcon#first serial, iclass 20, count 2 2006.173.08:17:34.30#ibcon#enter sib2, iclass 20, count 2 2006.173.08:17:34.30#ibcon#flushed, iclass 20, count 2 2006.173.08:17:34.30#ibcon#about to write, iclass 20, count 2 2006.173.08:17:34.30#ibcon#wrote, iclass 20, count 2 2006.173.08:17:34.30#ibcon#about to read 3, iclass 20, count 2 2006.173.08:17:34.32#ibcon#read 3, iclass 20, count 2 2006.173.08:17:34.32#ibcon#about to read 4, iclass 20, count 2 2006.173.08:17:34.32#ibcon#read 4, iclass 20, count 2 2006.173.08:17:34.32#ibcon#about to read 5, iclass 20, count 2 2006.173.08:17:34.32#ibcon#read 5, iclass 20, count 2 2006.173.08:17:34.32#ibcon#about to read 6, iclass 20, count 2 2006.173.08:17:34.32#ibcon#read 6, iclass 20, count 2 2006.173.08:17:34.32#ibcon#end of sib2, iclass 20, count 2 2006.173.08:17:34.32#ibcon#*mode == 0, iclass 20, count 2 2006.173.08:17:34.32#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.08:17:34.32#ibcon#[25=AT07-04\r\n] 2006.173.08:17:34.32#ibcon#*before write, iclass 20, count 2 2006.173.08:17:34.32#ibcon#enter sib2, iclass 20, count 2 2006.173.08:17:34.32#ibcon#flushed, iclass 20, count 2 2006.173.08:17:34.32#ibcon#about to write, iclass 20, count 2 2006.173.08:17:34.32#ibcon#wrote, iclass 20, count 2 2006.173.08:17:34.32#ibcon#about to read 3, iclass 20, count 2 2006.173.08:17:34.35#ibcon#read 3, iclass 20, count 2 2006.173.08:17:34.35#ibcon#about to read 4, iclass 20, count 2 2006.173.08:17:34.35#ibcon#read 4, iclass 20, count 2 2006.173.08:17:34.35#ibcon#about to read 5, iclass 20, count 2 2006.173.08:17:34.35#ibcon#read 5, iclass 20, count 2 2006.173.08:17:34.35#ibcon#about to read 6, iclass 20, count 2 2006.173.08:17:34.35#ibcon#read 6, iclass 20, count 2 2006.173.08:17:34.35#ibcon#end of sib2, iclass 20, count 2 2006.173.08:17:34.35#ibcon#*after write, iclass 20, count 2 2006.173.08:17:34.35#ibcon#*before return 0, iclass 20, count 2 2006.173.08:17:34.35#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.08:17:34.35#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.08:17:34.35#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.08:17:34.35#ibcon#ireg 7 cls_cnt 0 2006.173.08:17:34.35#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.08:17:34.47#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.08:17:34.47#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.08:17:34.47#ibcon#enter wrdev, iclass 20, count 0 2006.173.08:17:34.47#ibcon#first serial, iclass 20, count 0 2006.173.08:17:34.47#ibcon#enter sib2, iclass 20, count 0 2006.173.08:17:34.47#ibcon#flushed, iclass 20, count 0 2006.173.08:17:34.47#ibcon#about to write, iclass 20, count 0 2006.173.08:17:34.47#ibcon#wrote, iclass 20, count 0 2006.173.08:17:34.47#ibcon#about to read 3, iclass 20, count 0 2006.173.08:17:34.49#ibcon#read 3, iclass 20, count 0 2006.173.08:17:34.49#ibcon#about to read 4, iclass 20, count 0 2006.173.08:17:34.49#ibcon#read 4, iclass 20, count 0 2006.173.08:17:34.49#ibcon#about to read 5, iclass 20, count 0 2006.173.08:17:34.49#ibcon#read 5, iclass 20, count 0 2006.173.08:17:34.49#ibcon#about to read 6, iclass 20, count 0 2006.173.08:17:34.49#ibcon#read 6, iclass 20, count 0 2006.173.08:17:34.49#ibcon#end of sib2, iclass 20, count 0 2006.173.08:17:34.49#ibcon#*mode == 0, iclass 20, count 0 2006.173.08:17:34.49#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.08:17:34.49#ibcon#[25=USB\r\n] 2006.173.08:17:34.49#ibcon#*before write, iclass 20, count 0 2006.173.08:17:34.49#ibcon#enter sib2, iclass 20, count 0 2006.173.08:17:34.49#ibcon#flushed, iclass 20, count 0 2006.173.08:17:34.49#ibcon#about to write, iclass 20, count 0 2006.173.08:17:34.49#ibcon#wrote, iclass 20, count 0 2006.173.08:17:34.49#ibcon#about to read 3, iclass 20, count 0 2006.173.08:17:34.52#ibcon#read 3, iclass 20, count 0 2006.173.08:17:34.52#ibcon#about to read 4, iclass 20, count 0 2006.173.08:17:34.52#ibcon#read 4, iclass 20, count 0 2006.173.08:17:34.52#ibcon#about to read 5, iclass 20, count 0 2006.173.08:17:34.52#ibcon#read 5, iclass 20, count 0 2006.173.08:17:34.52#ibcon#about to read 6, iclass 20, count 0 2006.173.08:17:34.52#ibcon#read 6, iclass 20, count 0 2006.173.08:17:34.52#ibcon#end of sib2, iclass 20, count 0 2006.173.08:17:34.52#ibcon#*after write, iclass 20, count 0 2006.173.08:17:34.52#ibcon#*before return 0, iclass 20, count 0 2006.173.08:17:34.52#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.08:17:34.52#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.08:17:34.52#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.08:17:34.52#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.08:17:34.52$vck44/valo=8,884.99 2006.173.08:17:34.52#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.08:17:34.52#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.08:17:34.52#ibcon#ireg 17 cls_cnt 0 2006.173.08:17:34.52#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.08:17:34.52#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.08:17:34.52#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.08:17:34.52#ibcon#enter wrdev, iclass 22, count 0 2006.173.08:17:34.52#ibcon#first serial, iclass 22, count 0 2006.173.08:17:34.52#ibcon#enter sib2, iclass 22, count 0 2006.173.08:17:34.52#ibcon#flushed, iclass 22, count 0 2006.173.08:17:34.52#ibcon#about to write, iclass 22, count 0 2006.173.08:17:34.52#ibcon#wrote, iclass 22, count 0 2006.173.08:17:34.52#ibcon#about to read 3, iclass 22, count 0 2006.173.08:17:34.54#ibcon#read 3, iclass 22, count 0 2006.173.08:17:34.54#ibcon#about to read 4, iclass 22, count 0 2006.173.08:17:34.54#ibcon#read 4, iclass 22, count 0 2006.173.08:17:34.54#ibcon#about to read 5, iclass 22, count 0 2006.173.08:17:34.54#ibcon#read 5, iclass 22, count 0 2006.173.08:17:34.54#ibcon#about to read 6, iclass 22, count 0 2006.173.08:17:34.54#ibcon#read 6, iclass 22, count 0 2006.173.08:17:34.54#ibcon#end of sib2, iclass 22, count 0 2006.173.08:17:34.54#ibcon#*mode == 0, iclass 22, count 0 2006.173.08:17:34.54#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.08:17:34.54#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.08:17:34.54#ibcon#*before write, iclass 22, count 0 2006.173.08:17:34.54#ibcon#enter sib2, iclass 22, count 0 2006.173.08:17:34.54#ibcon#flushed, iclass 22, count 0 2006.173.08:17:34.54#ibcon#about to write, iclass 22, count 0 2006.173.08:17:34.54#ibcon#wrote, iclass 22, count 0 2006.173.08:17:34.54#ibcon#about to read 3, iclass 22, count 0 2006.173.08:17:34.58#ibcon#read 3, iclass 22, count 0 2006.173.08:17:34.58#ibcon#about to read 4, iclass 22, count 0 2006.173.08:17:34.58#ibcon#read 4, iclass 22, count 0 2006.173.08:17:34.58#ibcon#about to read 5, iclass 22, count 0 2006.173.08:17:34.58#ibcon#read 5, iclass 22, count 0 2006.173.08:17:34.58#ibcon#about to read 6, iclass 22, count 0 2006.173.08:17:34.58#ibcon#read 6, iclass 22, count 0 2006.173.08:17:34.58#ibcon#end of sib2, iclass 22, count 0 2006.173.08:17:34.58#ibcon#*after write, iclass 22, count 0 2006.173.08:17:34.58#ibcon#*before return 0, iclass 22, count 0 2006.173.08:17:34.58#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.08:17:34.58#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.08:17:34.58#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.08:17:34.58#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.08:17:34.58$vck44/va=8,4 2006.173.08:17:34.58#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.08:17:34.58#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.08:17:34.58#ibcon#ireg 11 cls_cnt 2 2006.173.08:17:34.58#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.08:17:34.64#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.08:17:34.64#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.08:17:34.64#ibcon#enter wrdev, iclass 24, count 2 2006.173.08:17:34.64#ibcon#first serial, iclass 24, count 2 2006.173.08:17:34.64#ibcon#enter sib2, iclass 24, count 2 2006.173.08:17:34.64#ibcon#flushed, iclass 24, count 2 2006.173.08:17:34.64#ibcon#about to write, iclass 24, count 2 2006.173.08:17:34.64#ibcon#wrote, iclass 24, count 2 2006.173.08:17:34.64#ibcon#about to read 3, iclass 24, count 2 2006.173.08:17:34.66#ibcon#read 3, iclass 24, count 2 2006.173.08:17:34.66#ibcon#about to read 4, iclass 24, count 2 2006.173.08:17:34.66#ibcon#read 4, iclass 24, count 2 2006.173.08:17:34.66#ibcon#about to read 5, iclass 24, count 2 2006.173.08:17:34.66#ibcon#read 5, iclass 24, count 2 2006.173.08:17:34.66#ibcon#about to read 6, iclass 24, count 2 2006.173.08:17:34.66#ibcon#read 6, iclass 24, count 2 2006.173.08:17:34.66#ibcon#end of sib2, iclass 24, count 2 2006.173.08:17:34.66#ibcon#*mode == 0, iclass 24, count 2 2006.173.08:17:34.66#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.08:17:34.66#ibcon#[25=AT08-04\r\n] 2006.173.08:17:34.66#ibcon#*before write, iclass 24, count 2 2006.173.08:17:34.66#ibcon#enter sib2, iclass 24, count 2 2006.173.08:17:34.66#ibcon#flushed, iclass 24, count 2 2006.173.08:17:34.66#ibcon#about to write, iclass 24, count 2 2006.173.08:17:34.66#ibcon#wrote, iclass 24, count 2 2006.173.08:17:34.66#ibcon#about to read 3, iclass 24, count 2 2006.173.08:17:34.69#ibcon#read 3, iclass 24, count 2 2006.173.08:17:34.69#ibcon#about to read 4, iclass 24, count 2 2006.173.08:17:34.69#ibcon#read 4, iclass 24, count 2 2006.173.08:17:34.69#ibcon#about to read 5, iclass 24, count 2 2006.173.08:17:34.69#ibcon#read 5, iclass 24, count 2 2006.173.08:17:34.69#ibcon#about to read 6, iclass 24, count 2 2006.173.08:17:34.69#ibcon#read 6, iclass 24, count 2 2006.173.08:17:34.69#ibcon#end of sib2, iclass 24, count 2 2006.173.08:17:34.69#ibcon#*after write, iclass 24, count 2 2006.173.08:17:34.69#ibcon#*before return 0, iclass 24, count 2 2006.173.08:17:34.69#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.08:17:34.69#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.08:17:34.69#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.08:17:34.69#ibcon#ireg 7 cls_cnt 0 2006.173.08:17:34.69#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.08:17:34.81#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.08:17:34.81#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.08:17:34.81#ibcon#enter wrdev, iclass 24, count 0 2006.173.08:17:34.81#ibcon#first serial, iclass 24, count 0 2006.173.08:17:34.81#ibcon#enter sib2, iclass 24, count 0 2006.173.08:17:34.81#ibcon#flushed, iclass 24, count 0 2006.173.08:17:34.81#ibcon#about to write, iclass 24, count 0 2006.173.08:17:34.81#ibcon#wrote, iclass 24, count 0 2006.173.08:17:34.81#ibcon#about to read 3, iclass 24, count 0 2006.173.08:17:34.83#ibcon#read 3, iclass 24, count 0 2006.173.08:17:34.83#ibcon#about to read 4, iclass 24, count 0 2006.173.08:17:34.83#ibcon#read 4, iclass 24, count 0 2006.173.08:17:34.83#ibcon#about to read 5, iclass 24, count 0 2006.173.08:17:34.83#ibcon#read 5, iclass 24, count 0 2006.173.08:17:34.83#ibcon#about to read 6, iclass 24, count 0 2006.173.08:17:34.83#ibcon#read 6, iclass 24, count 0 2006.173.08:17:34.83#ibcon#end of sib2, iclass 24, count 0 2006.173.08:17:34.83#ibcon#*mode == 0, iclass 24, count 0 2006.173.08:17:34.83#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.08:17:34.83#ibcon#[25=USB\r\n] 2006.173.08:17:34.83#ibcon#*before write, iclass 24, count 0 2006.173.08:17:34.83#ibcon#enter sib2, iclass 24, count 0 2006.173.08:17:34.83#ibcon#flushed, iclass 24, count 0 2006.173.08:17:34.83#ibcon#about to write, iclass 24, count 0 2006.173.08:17:34.83#ibcon#wrote, iclass 24, count 0 2006.173.08:17:34.83#ibcon#about to read 3, iclass 24, count 0 2006.173.08:17:34.86#ibcon#read 3, iclass 24, count 0 2006.173.08:17:34.86#ibcon#about to read 4, iclass 24, count 0 2006.173.08:17:34.86#ibcon#read 4, iclass 24, count 0 2006.173.08:17:34.86#ibcon#about to read 5, iclass 24, count 0 2006.173.08:17:34.86#ibcon#read 5, iclass 24, count 0 2006.173.08:17:34.86#ibcon#about to read 6, iclass 24, count 0 2006.173.08:17:34.86#ibcon#read 6, iclass 24, count 0 2006.173.08:17:34.86#ibcon#end of sib2, iclass 24, count 0 2006.173.08:17:34.86#ibcon#*after write, iclass 24, count 0 2006.173.08:17:34.86#ibcon#*before return 0, iclass 24, count 0 2006.173.08:17:34.86#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.08:17:34.86#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.08:17:34.86#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.08:17:34.86#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.08:17:34.86$vck44/vblo=1,629.99 2006.173.08:17:34.86#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.08:17:34.86#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.08:17:34.86#ibcon#ireg 17 cls_cnt 0 2006.173.08:17:34.86#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.08:17:34.86#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.08:17:34.86#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.08:17:34.86#ibcon#enter wrdev, iclass 26, count 0 2006.173.08:17:34.86#ibcon#first serial, iclass 26, count 0 2006.173.08:17:34.86#ibcon#enter sib2, iclass 26, count 0 2006.173.08:17:34.86#ibcon#flushed, iclass 26, count 0 2006.173.08:17:34.86#ibcon#about to write, iclass 26, count 0 2006.173.08:17:34.86#ibcon#wrote, iclass 26, count 0 2006.173.08:17:34.86#ibcon#about to read 3, iclass 26, count 0 2006.173.08:17:34.88#ibcon#read 3, iclass 26, count 0 2006.173.08:17:34.88#ibcon#about to read 4, iclass 26, count 0 2006.173.08:17:34.88#ibcon#read 4, iclass 26, count 0 2006.173.08:17:34.88#ibcon#about to read 5, iclass 26, count 0 2006.173.08:17:34.88#ibcon#read 5, iclass 26, count 0 2006.173.08:17:34.88#ibcon#about to read 6, iclass 26, count 0 2006.173.08:17:34.88#ibcon#read 6, iclass 26, count 0 2006.173.08:17:34.88#ibcon#end of sib2, iclass 26, count 0 2006.173.08:17:34.88#ibcon#*mode == 0, iclass 26, count 0 2006.173.08:17:34.88#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.08:17:34.88#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.08:17:34.88#ibcon#*before write, iclass 26, count 0 2006.173.08:17:34.88#ibcon#enter sib2, iclass 26, count 0 2006.173.08:17:34.88#ibcon#flushed, iclass 26, count 0 2006.173.08:17:34.88#ibcon#about to write, iclass 26, count 0 2006.173.08:17:34.88#ibcon#wrote, iclass 26, count 0 2006.173.08:17:34.88#ibcon#about to read 3, iclass 26, count 0 2006.173.08:17:34.92#ibcon#read 3, iclass 26, count 0 2006.173.08:17:34.92#ibcon#about to read 4, iclass 26, count 0 2006.173.08:17:34.92#ibcon#read 4, iclass 26, count 0 2006.173.08:17:34.92#ibcon#about to read 5, iclass 26, count 0 2006.173.08:17:34.92#ibcon#read 5, iclass 26, count 0 2006.173.08:17:34.92#ibcon#about to read 6, iclass 26, count 0 2006.173.08:17:34.92#ibcon#read 6, iclass 26, count 0 2006.173.08:17:34.92#ibcon#end of sib2, iclass 26, count 0 2006.173.08:17:34.92#ibcon#*after write, iclass 26, count 0 2006.173.08:17:34.92#ibcon#*before return 0, iclass 26, count 0 2006.173.08:17:34.92#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.08:17:34.92#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.08:17:34.92#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.08:17:34.92#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.08:17:34.92$vck44/vb=1,4 2006.173.08:17:34.92#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.08:17:34.92#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.08:17:34.92#ibcon#ireg 11 cls_cnt 2 2006.173.08:17:34.92#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.08:17:34.92#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.08:17:34.92#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.08:17:34.92#ibcon#enter wrdev, iclass 28, count 2 2006.173.08:17:34.92#ibcon#first serial, iclass 28, count 2 2006.173.08:17:34.92#ibcon#enter sib2, iclass 28, count 2 2006.173.08:17:34.92#ibcon#flushed, iclass 28, count 2 2006.173.08:17:34.92#ibcon#about to write, iclass 28, count 2 2006.173.08:17:34.92#ibcon#wrote, iclass 28, count 2 2006.173.08:17:34.92#ibcon#about to read 3, iclass 28, count 2 2006.173.08:17:34.94#ibcon#read 3, iclass 28, count 2 2006.173.08:17:34.94#ibcon#about to read 4, iclass 28, count 2 2006.173.08:17:34.94#ibcon#read 4, iclass 28, count 2 2006.173.08:17:34.94#ibcon#about to read 5, iclass 28, count 2 2006.173.08:17:34.94#ibcon#read 5, iclass 28, count 2 2006.173.08:17:34.94#ibcon#about to read 6, iclass 28, count 2 2006.173.08:17:34.94#ibcon#read 6, iclass 28, count 2 2006.173.08:17:34.94#ibcon#end of sib2, iclass 28, count 2 2006.173.08:17:34.94#ibcon#*mode == 0, iclass 28, count 2 2006.173.08:17:34.94#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.08:17:34.94#ibcon#[27=AT01-04\r\n] 2006.173.08:17:34.94#ibcon#*before write, iclass 28, count 2 2006.173.08:17:34.94#ibcon#enter sib2, iclass 28, count 2 2006.173.08:17:34.94#ibcon#flushed, iclass 28, count 2 2006.173.08:17:34.94#ibcon#about to write, iclass 28, count 2 2006.173.08:17:34.94#ibcon#wrote, iclass 28, count 2 2006.173.08:17:34.94#ibcon#about to read 3, iclass 28, count 2 2006.173.08:17:34.97#ibcon#read 3, iclass 28, count 2 2006.173.08:17:34.97#ibcon#about to read 4, iclass 28, count 2 2006.173.08:17:34.97#ibcon#read 4, iclass 28, count 2 2006.173.08:17:34.97#ibcon#about to read 5, iclass 28, count 2 2006.173.08:17:34.97#ibcon#read 5, iclass 28, count 2 2006.173.08:17:34.97#ibcon#about to read 6, iclass 28, count 2 2006.173.08:17:34.97#ibcon#read 6, iclass 28, count 2 2006.173.08:17:34.97#ibcon#end of sib2, iclass 28, count 2 2006.173.08:17:34.97#ibcon#*after write, iclass 28, count 2 2006.173.08:17:34.97#ibcon#*before return 0, iclass 28, count 2 2006.173.08:17:34.97#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.08:17:34.97#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.08:17:34.97#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.08:17:34.97#ibcon#ireg 7 cls_cnt 0 2006.173.08:17:34.97#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.08:17:35.09#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.08:17:35.09#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.08:17:35.09#ibcon#enter wrdev, iclass 28, count 0 2006.173.08:17:35.09#ibcon#first serial, iclass 28, count 0 2006.173.08:17:35.09#ibcon#enter sib2, iclass 28, count 0 2006.173.08:17:35.09#ibcon#flushed, iclass 28, count 0 2006.173.08:17:35.09#ibcon#about to write, iclass 28, count 0 2006.173.08:17:35.09#ibcon#wrote, iclass 28, count 0 2006.173.08:17:35.09#ibcon#about to read 3, iclass 28, count 0 2006.173.08:17:35.11#ibcon#read 3, iclass 28, count 0 2006.173.08:17:35.11#ibcon#about to read 4, iclass 28, count 0 2006.173.08:17:35.11#ibcon#read 4, iclass 28, count 0 2006.173.08:17:35.11#ibcon#about to read 5, iclass 28, count 0 2006.173.08:17:35.11#ibcon#read 5, iclass 28, count 0 2006.173.08:17:35.11#ibcon#about to read 6, iclass 28, count 0 2006.173.08:17:35.11#ibcon#read 6, iclass 28, count 0 2006.173.08:17:35.11#ibcon#end of sib2, iclass 28, count 0 2006.173.08:17:35.11#ibcon#*mode == 0, iclass 28, count 0 2006.173.08:17:35.11#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.08:17:35.11#ibcon#[27=USB\r\n] 2006.173.08:17:35.11#ibcon#*before write, iclass 28, count 0 2006.173.08:17:35.11#ibcon#enter sib2, iclass 28, count 0 2006.173.08:17:35.11#ibcon#flushed, iclass 28, count 0 2006.173.08:17:35.11#ibcon#about to write, iclass 28, count 0 2006.173.08:17:35.11#ibcon#wrote, iclass 28, count 0 2006.173.08:17:35.11#ibcon#about to read 3, iclass 28, count 0 2006.173.08:17:35.14#ibcon#read 3, iclass 28, count 0 2006.173.08:17:35.14#ibcon#about to read 4, iclass 28, count 0 2006.173.08:17:35.14#ibcon#read 4, iclass 28, count 0 2006.173.08:17:35.14#ibcon#about to read 5, iclass 28, count 0 2006.173.08:17:35.14#ibcon#read 5, iclass 28, count 0 2006.173.08:17:35.14#ibcon#about to read 6, iclass 28, count 0 2006.173.08:17:35.14#ibcon#read 6, iclass 28, count 0 2006.173.08:17:35.14#ibcon#end of sib2, iclass 28, count 0 2006.173.08:17:35.14#ibcon#*after write, iclass 28, count 0 2006.173.08:17:35.14#ibcon#*before return 0, iclass 28, count 0 2006.173.08:17:35.14#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.08:17:35.14#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.08:17:35.14#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.08:17:35.14#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.08:17:35.14$vck44/vblo=2,634.99 2006.173.08:17:35.14#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.08:17:35.14#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.08:17:35.14#ibcon#ireg 17 cls_cnt 0 2006.173.08:17:35.14#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.08:17:35.14#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.08:17:35.14#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.08:17:35.14#ibcon#enter wrdev, iclass 30, count 0 2006.173.08:17:35.14#ibcon#first serial, iclass 30, count 0 2006.173.08:17:35.14#ibcon#enter sib2, iclass 30, count 0 2006.173.08:17:35.14#ibcon#flushed, iclass 30, count 0 2006.173.08:17:35.14#ibcon#about to write, iclass 30, count 0 2006.173.08:17:35.14#ibcon#wrote, iclass 30, count 0 2006.173.08:17:35.14#ibcon#about to read 3, iclass 30, count 0 2006.173.08:17:35.16#ibcon#read 3, iclass 30, count 0 2006.173.08:17:35.16#ibcon#about to read 4, iclass 30, count 0 2006.173.08:17:35.16#ibcon#read 4, iclass 30, count 0 2006.173.08:17:35.16#ibcon#about to read 5, iclass 30, count 0 2006.173.08:17:35.16#ibcon#read 5, iclass 30, count 0 2006.173.08:17:35.16#ibcon#about to read 6, iclass 30, count 0 2006.173.08:17:35.16#ibcon#read 6, iclass 30, count 0 2006.173.08:17:35.16#ibcon#end of sib2, iclass 30, count 0 2006.173.08:17:35.16#ibcon#*mode == 0, iclass 30, count 0 2006.173.08:17:35.16#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.08:17:35.16#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.08:17:35.16#ibcon#*before write, iclass 30, count 0 2006.173.08:17:35.16#ibcon#enter sib2, iclass 30, count 0 2006.173.08:17:35.16#ibcon#flushed, iclass 30, count 0 2006.173.08:17:35.16#ibcon#about to write, iclass 30, count 0 2006.173.08:17:35.16#ibcon#wrote, iclass 30, count 0 2006.173.08:17:35.16#ibcon#about to read 3, iclass 30, count 0 2006.173.08:17:35.20#ibcon#read 3, iclass 30, count 0 2006.173.08:17:35.20#ibcon#about to read 4, iclass 30, count 0 2006.173.08:17:35.20#ibcon#read 4, iclass 30, count 0 2006.173.08:17:35.20#ibcon#about to read 5, iclass 30, count 0 2006.173.08:17:35.20#ibcon#read 5, iclass 30, count 0 2006.173.08:17:35.20#ibcon#about to read 6, iclass 30, count 0 2006.173.08:17:35.20#ibcon#read 6, iclass 30, count 0 2006.173.08:17:35.20#ibcon#end of sib2, iclass 30, count 0 2006.173.08:17:35.20#ibcon#*after write, iclass 30, count 0 2006.173.08:17:35.20#ibcon#*before return 0, iclass 30, count 0 2006.173.08:17:35.20#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.08:17:35.20#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.08:17:35.20#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.08:17:35.20#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.08:17:35.20$vck44/vb=2,4 2006.173.08:17:35.20#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.173.08:17:35.20#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.173.08:17:35.20#ibcon#ireg 11 cls_cnt 2 2006.173.08:17:35.20#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.08:17:35.26#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.08:17:35.26#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.08:17:35.26#ibcon#enter wrdev, iclass 32, count 2 2006.173.08:17:35.26#ibcon#first serial, iclass 32, count 2 2006.173.08:17:35.26#ibcon#enter sib2, iclass 32, count 2 2006.173.08:17:35.26#ibcon#flushed, iclass 32, count 2 2006.173.08:17:35.26#ibcon#about to write, iclass 32, count 2 2006.173.08:17:35.26#ibcon#wrote, iclass 32, count 2 2006.173.08:17:35.26#ibcon#about to read 3, iclass 32, count 2 2006.173.08:17:35.28#ibcon#read 3, iclass 32, count 2 2006.173.08:17:35.28#ibcon#about to read 4, iclass 32, count 2 2006.173.08:17:35.28#ibcon#read 4, iclass 32, count 2 2006.173.08:17:35.28#ibcon#about to read 5, iclass 32, count 2 2006.173.08:17:35.28#ibcon#read 5, iclass 32, count 2 2006.173.08:17:35.28#ibcon#about to read 6, iclass 32, count 2 2006.173.08:17:35.28#ibcon#read 6, iclass 32, count 2 2006.173.08:17:35.28#ibcon#end of sib2, iclass 32, count 2 2006.173.08:17:35.28#ibcon#*mode == 0, iclass 32, count 2 2006.173.08:17:35.28#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.173.08:17:35.28#ibcon#[27=AT02-04\r\n] 2006.173.08:17:35.28#ibcon#*before write, iclass 32, count 2 2006.173.08:17:35.28#ibcon#enter sib2, iclass 32, count 2 2006.173.08:17:35.28#ibcon#flushed, iclass 32, count 2 2006.173.08:17:35.28#ibcon#about to write, iclass 32, count 2 2006.173.08:17:35.28#ibcon#wrote, iclass 32, count 2 2006.173.08:17:35.28#ibcon#about to read 3, iclass 32, count 2 2006.173.08:17:35.31#ibcon#read 3, iclass 32, count 2 2006.173.08:17:35.31#ibcon#about to read 4, iclass 32, count 2 2006.173.08:17:35.31#ibcon#read 4, iclass 32, count 2 2006.173.08:17:35.31#ibcon#about to read 5, iclass 32, count 2 2006.173.08:17:35.31#ibcon#read 5, iclass 32, count 2 2006.173.08:17:35.31#ibcon#about to read 6, iclass 32, count 2 2006.173.08:17:35.31#ibcon#read 6, iclass 32, count 2 2006.173.08:17:35.31#ibcon#end of sib2, iclass 32, count 2 2006.173.08:17:35.31#ibcon#*after write, iclass 32, count 2 2006.173.08:17:35.31#ibcon#*before return 0, iclass 32, count 2 2006.173.08:17:35.31#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.08:17:35.31#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.173.08:17:35.31#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.173.08:17:35.31#ibcon#ireg 7 cls_cnt 0 2006.173.08:17:35.31#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.08:17:35.43#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.08:17:35.43#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.08:17:35.43#ibcon#enter wrdev, iclass 32, count 0 2006.173.08:17:35.43#ibcon#first serial, iclass 32, count 0 2006.173.08:17:35.43#ibcon#enter sib2, iclass 32, count 0 2006.173.08:17:35.43#ibcon#flushed, iclass 32, count 0 2006.173.08:17:35.43#ibcon#about to write, iclass 32, count 0 2006.173.08:17:35.43#ibcon#wrote, iclass 32, count 0 2006.173.08:17:35.43#ibcon#about to read 3, iclass 32, count 0 2006.173.08:17:35.45#ibcon#read 3, iclass 32, count 0 2006.173.08:17:35.45#ibcon#about to read 4, iclass 32, count 0 2006.173.08:17:35.45#ibcon#read 4, iclass 32, count 0 2006.173.08:17:35.45#ibcon#about to read 5, iclass 32, count 0 2006.173.08:17:35.45#ibcon#read 5, iclass 32, count 0 2006.173.08:17:35.45#ibcon#about to read 6, iclass 32, count 0 2006.173.08:17:35.45#ibcon#read 6, iclass 32, count 0 2006.173.08:17:35.45#ibcon#end of sib2, iclass 32, count 0 2006.173.08:17:35.45#ibcon#*mode == 0, iclass 32, count 0 2006.173.08:17:35.45#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.08:17:35.45#ibcon#[27=USB\r\n] 2006.173.08:17:35.45#ibcon#*before write, iclass 32, count 0 2006.173.08:17:35.45#ibcon#enter sib2, iclass 32, count 0 2006.173.08:17:35.45#ibcon#flushed, iclass 32, count 0 2006.173.08:17:35.45#ibcon#about to write, iclass 32, count 0 2006.173.08:17:35.45#ibcon#wrote, iclass 32, count 0 2006.173.08:17:35.45#ibcon#about to read 3, iclass 32, count 0 2006.173.08:17:35.48#ibcon#read 3, iclass 32, count 0 2006.173.08:17:35.48#ibcon#about to read 4, iclass 32, count 0 2006.173.08:17:35.48#ibcon#read 4, iclass 32, count 0 2006.173.08:17:35.48#ibcon#about to read 5, iclass 32, count 0 2006.173.08:17:35.48#ibcon#read 5, iclass 32, count 0 2006.173.08:17:35.48#ibcon#about to read 6, iclass 32, count 0 2006.173.08:17:35.48#ibcon#read 6, iclass 32, count 0 2006.173.08:17:35.48#ibcon#end of sib2, iclass 32, count 0 2006.173.08:17:35.48#ibcon#*after write, iclass 32, count 0 2006.173.08:17:35.48#ibcon#*before return 0, iclass 32, count 0 2006.173.08:17:35.48#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.08:17:35.48#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.173.08:17:35.48#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.08:17:35.48#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.08:17:35.48$vck44/vblo=3,649.99 2006.173.08:17:35.48#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.08:17:35.48#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.08:17:35.48#ibcon#ireg 17 cls_cnt 0 2006.173.08:17:35.48#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.08:17:35.48#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.08:17:35.48#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.08:17:35.48#ibcon#enter wrdev, iclass 34, count 0 2006.173.08:17:35.48#ibcon#first serial, iclass 34, count 0 2006.173.08:17:35.48#ibcon#enter sib2, iclass 34, count 0 2006.173.08:17:35.48#ibcon#flushed, iclass 34, count 0 2006.173.08:17:35.48#ibcon#about to write, iclass 34, count 0 2006.173.08:17:35.48#ibcon#wrote, iclass 34, count 0 2006.173.08:17:35.48#ibcon#about to read 3, iclass 34, count 0 2006.173.08:17:35.50#ibcon#read 3, iclass 34, count 0 2006.173.08:17:35.50#ibcon#about to read 4, iclass 34, count 0 2006.173.08:17:35.50#ibcon#read 4, iclass 34, count 0 2006.173.08:17:35.50#ibcon#about to read 5, iclass 34, count 0 2006.173.08:17:35.50#ibcon#read 5, iclass 34, count 0 2006.173.08:17:35.50#ibcon#about to read 6, iclass 34, count 0 2006.173.08:17:35.50#ibcon#read 6, iclass 34, count 0 2006.173.08:17:35.50#ibcon#end of sib2, iclass 34, count 0 2006.173.08:17:35.50#ibcon#*mode == 0, iclass 34, count 0 2006.173.08:17:35.50#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.08:17:35.50#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.08:17:35.50#ibcon#*before write, iclass 34, count 0 2006.173.08:17:35.50#ibcon#enter sib2, iclass 34, count 0 2006.173.08:17:35.50#ibcon#flushed, iclass 34, count 0 2006.173.08:17:35.50#ibcon#about to write, iclass 34, count 0 2006.173.08:17:35.50#ibcon#wrote, iclass 34, count 0 2006.173.08:17:35.50#ibcon#about to read 3, iclass 34, count 0 2006.173.08:17:35.54#ibcon#read 3, iclass 34, count 0 2006.173.08:17:35.54#ibcon#about to read 4, iclass 34, count 0 2006.173.08:17:35.54#ibcon#read 4, iclass 34, count 0 2006.173.08:17:35.54#ibcon#about to read 5, iclass 34, count 0 2006.173.08:17:35.54#ibcon#read 5, iclass 34, count 0 2006.173.08:17:35.54#ibcon#about to read 6, iclass 34, count 0 2006.173.08:17:35.54#ibcon#read 6, iclass 34, count 0 2006.173.08:17:35.54#ibcon#end of sib2, iclass 34, count 0 2006.173.08:17:35.54#ibcon#*after write, iclass 34, count 0 2006.173.08:17:35.54#ibcon#*before return 0, iclass 34, count 0 2006.173.08:17:35.54#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.08:17:35.54#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.08:17:35.54#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.08:17:35.54#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.08:17:35.54$vck44/vb=3,4 2006.173.08:17:35.54#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.08:17:35.54#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.08:17:35.54#ibcon#ireg 11 cls_cnt 2 2006.173.08:17:35.54#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.08:17:35.60#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.08:17:35.60#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.08:17:35.60#ibcon#enter wrdev, iclass 36, count 2 2006.173.08:17:35.60#ibcon#first serial, iclass 36, count 2 2006.173.08:17:35.60#ibcon#enter sib2, iclass 36, count 2 2006.173.08:17:35.60#ibcon#flushed, iclass 36, count 2 2006.173.08:17:35.60#ibcon#about to write, iclass 36, count 2 2006.173.08:17:35.60#ibcon#wrote, iclass 36, count 2 2006.173.08:17:35.60#ibcon#about to read 3, iclass 36, count 2 2006.173.08:17:35.62#ibcon#read 3, iclass 36, count 2 2006.173.08:17:35.62#ibcon#about to read 4, iclass 36, count 2 2006.173.08:17:35.62#ibcon#read 4, iclass 36, count 2 2006.173.08:17:35.62#ibcon#about to read 5, iclass 36, count 2 2006.173.08:17:35.62#ibcon#read 5, iclass 36, count 2 2006.173.08:17:35.62#ibcon#about to read 6, iclass 36, count 2 2006.173.08:17:35.62#ibcon#read 6, iclass 36, count 2 2006.173.08:17:35.62#ibcon#end of sib2, iclass 36, count 2 2006.173.08:17:35.62#ibcon#*mode == 0, iclass 36, count 2 2006.173.08:17:35.62#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.08:17:35.62#ibcon#[27=AT03-04\r\n] 2006.173.08:17:35.62#ibcon#*before write, iclass 36, count 2 2006.173.08:17:35.62#ibcon#enter sib2, iclass 36, count 2 2006.173.08:17:35.62#ibcon#flushed, iclass 36, count 2 2006.173.08:17:35.62#ibcon#about to write, iclass 36, count 2 2006.173.08:17:35.62#ibcon#wrote, iclass 36, count 2 2006.173.08:17:35.62#ibcon#about to read 3, iclass 36, count 2 2006.173.08:17:35.65#ibcon#read 3, iclass 36, count 2 2006.173.08:17:35.65#ibcon#about to read 4, iclass 36, count 2 2006.173.08:17:35.65#ibcon#read 4, iclass 36, count 2 2006.173.08:17:35.65#ibcon#about to read 5, iclass 36, count 2 2006.173.08:17:35.65#ibcon#read 5, iclass 36, count 2 2006.173.08:17:35.65#ibcon#about to read 6, iclass 36, count 2 2006.173.08:17:35.65#ibcon#read 6, iclass 36, count 2 2006.173.08:17:35.65#ibcon#end of sib2, iclass 36, count 2 2006.173.08:17:35.65#ibcon#*after write, iclass 36, count 2 2006.173.08:17:35.65#ibcon#*before return 0, iclass 36, count 2 2006.173.08:17:35.65#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.08:17:35.65#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.08:17:35.65#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.08:17:35.65#ibcon#ireg 7 cls_cnt 0 2006.173.08:17:35.65#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.08:17:35.77#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.08:17:35.77#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.08:17:35.77#ibcon#enter wrdev, iclass 36, count 0 2006.173.08:17:35.77#ibcon#first serial, iclass 36, count 0 2006.173.08:17:35.77#ibcon#enter sib2, iclass 36, count 0 2006.173.08:17:35.77#ibcon#flushed, iclass 36, count 0 2006.173.08:17:35.77#ibcon#about to write, iclass 36, count 0 2006.173.08:17:35.77#ibcon#wrote, iclass 36, count 0 2006.173.08:17:35.77#ibcon#about to read 3, iclass 36, count 0 2006.173.08:17:35.79#ibcon#read 3, iclass 36, count 0 2006.173.08:17:35.79#ibcon#about to read 4, iclass 36, count 0 2006.173.08:17:35.79#ibcon#read 4, iclass 36, count 0 2006.173.08:17:35.79#ibcon#about to read 5, iclass 36, count 0 2006.173.08:17:35.79#ibcon#read 5, iclass 36, count 0 2006.173.08:17:35.79#ibcon#about to read 6, iclass 36, count 0 2006.173.08:17:35.79#ibcon#read 6, iclass 36, count 0 2006.173.08:17:35.79#ibcon#end of sib2, iclass 36, count 0 2006.173.08:17:35.79#ibcon#*mode == 0, iclass 36, count 0 2006.173.08:17:35.79#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.08:17:35.79#ibcon#[27=USB\r\n] 2006.173.08:17:35.79#ibcon#*before write, iclass 36, count 0 2006.173.08:17:35.79#ibcon#enter sib2, iclass 36, count 0 2006.173.08:17:35.79#ibcon#flushed, iclass 36, count 0 2006.173.08:17:35.79#ibcon#about to write, iclass 36, count 0 2006.173.08:17:35.79#ibcon#wrote, iclass 36, count 0 2006.173.08:17:35.79#ibcon#about to read 3, iclass 36, count 0 2006.173.08:17:35.82#ibcon#read 3, iclass 36, count 0 2006.173.08:17:35.82#ibcon#about to read 4, iclass 36, count 0 2006.173.08:17:35.82#ibcon#read 4, iclass 36, count 0 2006.173.08:17:35.82#ibcon#about to read 5, iclass 36, count 0 2006.173.08:17:35.82#ibcon#read 5, iclass 36, count 0 2006.173.08:17:35.82#ibcon#about to read 6, iclass 36, count 0 2006.173.08:17:35.82#ibcon#read 6, iclass 36, count 0 2006.173.08:17:35.82#ibcon#end of sib2, iclass 36, count 0 2006.173.08:17:35.82#ibcon#*after write, iclass 36, count 0 2006.173.08:17:35.82#ibcon#*before return 0, iclass 36, count 0 2006.173.08:17:35.82#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.08:17:35.82#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.08:17:35.82#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.08:17:35.82#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.08:17:35.82$vck44/vblo=4,679.99 2006.173.08:17:35.82#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.08:17:35.82#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.08:17:35.82#ibcon#ireg 17 cls_cnt 0 2006.173.08:17:35.82#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.08:17:35.82#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.08:17:35.82#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.08:17:35.82#ibcon#enter wrdev, iclass 38, count 0 2006.173.08:17:35.82#ibcon#first serial, iclass 38, count 0 2006.173.08:17:35.82#ibcon#enter sib2, iclass 38, count 0 2006.173.08:17:35.82#ibcon#flushed, iclass 38, count 0 2006.173.08:17:35.82#ibcon#about to write, iclass 38, count 0 2006.173.08:17:35.82#ibcon#wrote, iclass 38, count 0 2006.173.08:17:35.82#ibcon#about to read 3, iclass 38, count 0 2006.173.08:17:35.84#ibcon#read 3, iclass 38, count 0 2006.173.08:17:35.84#ibcon#about to read 4, iclass 38, count 0 2006.173.08:17:35.84#ibcon#read 4, iclass 38, count 0 2006.173.08:17:35.84#ibcon#about to read 5, iclass 38, count 0 2006.173.08:17:35.84#ibcon#read 5, iclass 38, count 0 2006.173.08:17:35.84#ibcon#about to read 6, iclass 38, count 0 2006.173.08:17:35.84#ibcon#read 6, iclass 38, count 0 2006.173.08:17:35.84#ibcon#end of sib2, iclass 38, count 0 2006.173.08:17:35.84#ibcon#*mode == 0, iclass 38, count 0 2006.173.08:17:35.84#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.08:17:35.84#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.08:17:35.84#ibcon#*before write, iclass 38, count 0 2006.173.08:17:35.84#ibcon#enter sib2, iclass 38, count 0 2006.173.08:17:35.84#ibcon#flushed, iclass 38, count 0 2006.173.08:17:35.84#ibcon#about to write, iclass 38, count 0 2006.173.08:17:35.84#ibcon#wrote, iclass 38, count 0 2006.173.08:17:35.84#ibcon#about to read 3, iclass 38, count 0 2006.173.08:17:35.88#ibcon#read 3, iclass 38, count 0 2006.173.08:17:35.88#ibcon#about to read 4, iclass 38, count 0 2006.173.08:17:35.88#ibcon#read 4, iclass 38, count 0 2006.173.08:17:35.88#ibcon#about to read 5, iclass 38, count 0 2006.173.08:17:35.88#ibcon#read 5, iclass 38, count 0 2006.173.08:17:35.88#ibcon#about to read 6, iclass 38, count 0 2006.173.08:17:35.88#ibcon#read 6, iclass 38, count 0 2006.173.08:17:35.88#ibcon#end of sib2, iclass 38, count 0 2006.173.08:17:35.88#ibcon#*after write, iclass 38, count 0 2006.173.08:17:35.88#ibcon#*before return 0, iclass 38, count 0 2006.173.08:17:35.88#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.08:17:35.88#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.08:17:35.88#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.08:17:35.88#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.08:17:35.88$vck44/vb=4,4 2006.173.08:17:35.88#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.08:17:35.88#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.08:17:35.88#ibcon#ireg 11 cls_cnt 2 2006.173.08:17:35.88#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.08:17:35.94#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.08:17:35.94#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.08:17:35.94#ibcon#enter wrdev, iclass 40, count 2 2006.173.08:17:35.94#ibcon#first serial, iclass 40, count 2 2006.173.08:17:35.94#ibcon#enter sib2, iclass 40, count 2 2006.173.08:17:35.94#ibcon#flushed, iclass 40, count 2 2006.173.08:17:35.94#ibcon#about to write, iclass 40, count 2 2006.173.08:17:35.94#ibcon#wrote, iclass 40, count 2 2006.173.08:17:35.94#ibcon#about to read 3, iclass 40, count 2 2006.173.08:17:35.96#ibcon#read 3, iclass 40, count 2 2006.173.08:17:35.96#ibcon#about to read 4, iclass 40, count 2 2006.173.08:17:35.96#ibcon#read 4, iclass 40, count 2 2006.173.08:17:35.96#ibcon#about to read 5, iclass 40, count 2 2006.173.08:17:35.96#ibcon#read 5, iclass 40, count 2 2006.173.08:17:35.96#ibcon#about to read 6, iclass 40, count 2 2006.173.08:17:35.96#ibcon#read 6, iclass 40, count 2 2006.173.08:17:35.96#ibcon#end of sib2, iclass 40, count 2 2006.173.08:17:35.96#ibcon#*mode == 0, iclass 40, count 2 2006.173.08:17:35.96#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.08:17:35.96#ibcon#[27=AT04-04\r\n] 2006.173.08:17:35.96#ibcon#*before write, iclass 40, count 2 2006.173.08:17:35.96#ibcon#enter sib2, iclass 40, count 2 2006.173.08:17:35.96#ibcon#flushed, iclass 40, count 2 2006.173.08:17:35.96#ibcon#about to write, iclass 40, count 2 2006.173.08:17:35.96#ibcon#wrote, iclass 40, count 2 2006.173.08:17:35.96#ibcon#about to read 3, iclass 40, count 2 2006.173.08:17:35.99#ibcon#read 3, iclass 40, count 2 2006.173.08:17:35.99#ibcon#about to read 4, iclass 40, count 2 2006.173.08:17:35.99#ibcon#read 4, iclass 40, count 2 2006.173.08:17:35.99#ibcon#about to read 5, iclass 40, count 2 2006.173.08:17:35.99#ibcon#read 5, iclass 40, count 2 2006.173.08:17:35.99#ibcon#about to read 6, iclass 40, count 2 2006.173.08:17:35.99#ibcon#read 6, iclass 40, count 2 2006.173.08:17:35.99#ibcon#end of sib2, iclass 40, count 2 2006.173.08:17:35.99#ibcon#*after write, iclass 40, count 2 2006.173.08:17:35.99#ibcon#*before return 0, iclass 40, count 2 2006.173.08:17:35.99#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.08:17:35.99#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.08:17:35.99#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.08:17:35.99#ibcon#ireg 7 cls_cnt 0 2006.173.08:17:35.99#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.08:17:36.11#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.08:17:36.11#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.08:17:36.11#ibcon#enter wrdev, iclass 40, count 0 2006.173.08:17:36.11#ibcon#first serial, iclass 40, count 0 2006.173.08:17:36.11#ibcon#enter sib2, iclass 40, count 0 2006.173.08:17:36.11#ibcon#flushed, iclass 40, count 0 2006.173.08:17:36.11#ibcon#about to write, iclass 40, count 0 2006.173.08:17:36.11#ibcon#wrote, iclass 40, count 0 2006.173.08:17:36.11#ibcon#about to read 3, iclass 40, count 0 2006.173.08:17:36.13#ibcon#read 3, iclass 40, count 0 2006.173.08:17:36.13#ibcon#about to read 4, iclass 40, count 0 2006.173.08:17:36.13#ibcon#read 4, iclass 40, count 0 2006.173.08:17:36.13#ibcon#about to read 5, iclass 40, count 0 2006.173.08:17:36.13#ibcon#read 5, iclass 40, count 0 2006.173.08:17:36.13#ibcon#about to read 6, iclass 40, count 0 2006.173.08:17:36.13#ibcon#read 6, iclass 40, count 0 2006.173.08:17:36.13#ibcon#end of sib2, iclass 40, count 0 2006.173.08:17:36.13#ibcon#*mode == 0, iclass 40, count 0 2006.173.08:17:36.13#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.08:17:36.13#ibcon#[27=USB\r\n] 2006.173.08:17:36.13#ibcon#*before write, iclass 40, count 0 2006.173.08:17:36.13#ibcon#enter sib2, iclass 40, count 0 2006.173.08:17:36.13#ibcon#flushed, iclass 40, count 0 2006.173.08:17:36.13#ibcon#about to write, iclass 40, count 0 2006.173.08:17:36.13#ibcon#wrote, iclass 40, count 0 2006.173.08:17:36.13#ibcon#about to read 3, iclass 40, count 0 2006.173.08:17:36.16#ibcon#read 3, iclass 40, count 0 2006.173.08:17:36.16#ibcon#about to read 4, iclass 40, count 0 2006.173.08:17:36.16#ibcon#read 4, iclass 40, count 0 2006.173.08:17:36.16#ibcon#about to read 5, iclass 40, count 0 2006.173.08:17:36.16#ibcon#read 5, iclass 40, count 0 2006.173.08:17:36.16#ibcon#about to read 6, iclass 40, count 0 2006.173.08:17:36.16#ibcon#read 6, iclass 40, count 0 2006.173.08:17:36.16#ibcon#end of sib2, iclass 40, count 0 2006.173.08:17:36.16#ibcon#*after write, iclass 40, count 0 2006.173.08:17:36.16#ibcon#*before return 0, iclass 40, count 0 2006.173.08:17:36.16#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.08:17:36.16#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.08:17:36.16#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.08:17:36.16#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.08:17:36.16$vck44/vblo=5,709.99 2006.173.08:17:36.16#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.08:17:36.16#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.08:17:36.16#ibcon#ireg 17 cls_cnt 0 2006.173.08:17:36.16#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.08:17:36.16#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.08:17:36.16#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.08:17:36.16#ibcon#enter wrdev, iclass 4, count 0 2006.173.08:17:36.16#ibcon#first serial, iclass 4, count 0 2006.173.08:17:36.16#ibcon#enter sib2, iclass 4, count 0 2006.173.08:17:36.16#ibcon#flushed, iclass 4, count 0 2006.173.08:17:36.16#ibcon#about to write, iclass 4, count 0 2006.173.08:17:36.16#ibcon#wrote, iclass 4, count 0 2006.173.08:17:36.16#ibcon#about to read 3, iclass 4, count 0 2006.173.08:17:36.18#ibcon#read 3, iclass 4, count 0 2006.173.08:17:36.18#ibcon#about to read 4, iclass 4, count 0 2006.173.08:17:36.18#ibcon#read 4, iclass 4, count 0 2006.173.08:17:36.18#ibcon#about to read 5, iclass 4, count 0 2006.173.08:17:36.18#ibcon#read 5, iclass 4, count 0 2006.173.08:17:36.18#ibcon#about to read 6, iclass 4, count 0 2006.173.08:17:36.18#ibcon#read 6, iclass 4, count 0 2006.173.08:17:36.18#ibcon#end of sib2, iclass 4, count 0 2006.173.08:17:36.18#ibcon#*mode == 0, iclass 4, count 0 2006.173.08:17:36.18#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.08:17:36.18#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.08:17:36.18#ibcon#*before write, iclass 4, count 0 2006.173.08:17:36.18#ibcon#enter sib2, iclass 4, count 0 2006.173.08:17:36.18#ibcon#flushed, iclass 4, count 0 2006.173.08:17:36.18#ibcon#about to write, iclass 4, count 0 2006.173.08:17:36.18#ibcon#wrote, iclass 4, count 0 2006.173.08:17:36.18#ibcon#about to read 3, iclass 4, count 0 2006.173.08:17:36.22#ibcon#read 3, iclass 4, count 0 2006.173.08:17:36.22#ibcon#about to read 4, iclass 4, count 0 2006.173.08:17:36.22#ibcon#read 4, iclass 4, count 0 2006.173.08:17:36.22#ibcon#about to read 5, iclass 4, count 0 2006.173.08:17:36.22#ibcon#read 5, iclass 4, count 0 2006.173.08:17:36.22#ibcon#about to read 6, iclass 4, count 0 2006.173.08:17:36.22#ibcon#read 6, iclass 4, count 0 2006.173.08:17:36.22#ibcon#end of sib2, iclass 4, count 0 2006.173.08:17:36.22#ibcon#*after write, iclass 4, count 0 2006.173.08:17:36.22#ibcon#*before return 0, iclass 4, count 0 2006.173.08:17:36.22#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.08:17:36.22#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.08:17:36.22#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.08:17:36.22#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.08:17:36.22$vck44/vb=5,4 2006.173.08:17:36.22#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.08:17:36.22#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.08:17:36.22#ibcon#ireg 11 cls_cnt 2 2006.173.08:17:36.22#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.08:17:36.28#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.08:17:36.28#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.08:17:36.28#ibcon#enter wrdev, iclass 6, count 2 2006.173.08:17:36.28#ibcon#first serial, iclass 6, count 2 2006.173.08:17:36.28#ibcon#enter sib2, iclass 6, count 2 2006.173.08:17:36.28#ibcon#flushed, iclass 6, count 2 2006.173.08:17:36.28#ibcon#about to write, iclass 6, count 2 2006.173.08:17:36.28#ibcon#wrote, iclass 6, count 2 2006.173.08:17:36.28#ibcon#about to read 3, iclass 6, count 2 2006.173.08:17:36.30#ibcon#read 3, iclass 6, count 2 2006.173.08:17:36.30#ibcon#about to read 4, iclass 6, count 2 2006.173.08:17:36.30#ibcon#read 4, iclass 6, count 2 2006.173.08:17:36.30#ibcon#about to read 5, iclass 6, count 2 2006.173.08:17:36.30#ibcon#read 5, iclass 6, count 2 2006.173.08:17:36.30#ibcon#about to read 6, iclass 6, count 2 2006.173.08:17:36.30#ibcon#read 6, iclass 6, count 2 2006.173.08:17:36.30#ibcon#end of sib2, iclass 6, count 2 2006.173.08:17:36.30#ibcon#*mode == 0, iclass 6, count 2 2006.173.08:17:36.30#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.08:17:36.30#ibcon#[27=AT05-04\r\n] 2006.173.08:17:36.30#ibcon#*before write, iclass 6, count 2 2006.173.08:17:36.30#ibcon#enter sib2, iclass 6, count 2 2006.173.08:17:36.30#ibcon#flushed, iclass 6, count 2 2006.173.08:17:36.30#ibcon#about to write, iclass 6, count 2 2006.173.08:17:36.30#ibcon#wrote, iclass 6, count 2 2006.173.08:17:36.30#ibcon#about to read 3, iclass 6, count 2 2006.173.08:17:36.33#ibcon#read 3, iclass 6, count 2 2006.173.08:17:36.33#ibcon#about to read 4, iclass 6, count 2 2006.173.08:17:36.33#ibcon#read 4, iclass 6, count 2 2006.173.08:17:36.33#ibcon#about to read 5, iclass 6, count 2 2006.173.08:17:36.33#ibcon#read 5, iclass 6, count 2 2006.173.08:17:36.33#ibcon#about to read 6, iclass 6, count 2 2006.173.08:17:36.33#ibcon#read 6, iclass 6, count 2 2006.173.08:17:36.33#ibcon#end of sib2, iclass 6, count 2 2006.173.08:17:36.33#ibcon#*after write, iclass 6, count 2 2006.173.08:17:36.33#ibcon#*before return 0, iclass 6, count 2 2006.173.08:17:36.33#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.08:17:36.33#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.08:17:36.33#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.08:17:36.33#ibcon#ireg 7 cls_cnt 0 2006.173.08:17:36.33#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.08:17:36.45#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.08:17:36.45#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.08:17:36.45#ibcon#enter wrdev, iclass 6, count 0 2006.173.08:17:36.45#ibcon#first serial, iclass 6, count 0 2006.173.08:17:36.45#ibcon#enter sib2, iclass 6, count 0 2006.173.08:17:36.45#ibcon#flushed, iclass 6, count 0 2006.173.08:17:36.45#ibcon#about to write, iclass 6, count 0 2006.173.08:17:36.45#ibcon#wrote, iclass 6, count 0 2006.173.08:17:36.45#ibcon#about to read 3, iclass 6, count 0 2006.173.08:17:36.47#ibcon#read 3, iclass 6, count 0 2006.173.08:17:36.47#ibcon#about to read 4, iclass 6, count 0 2006.173.08:17:36.47#ibcon#read 4, iclass 6, count 0 2006.173.08:17:36.47#ibcon#about to read 5, iclass 6, count 0 2006.173.08:17:36.47#ibcon#read 5, iclass 6, count 0 2006.173.08:17:36.47#ibcon#about to read 6, iclass 6, count 0 2006.173.08:17:36.47#ibcon#read 6, iclass 6, count 0 2006.173.08:17:36.47#ibcon#end of sib2, iclass 6, count 0 2006.173.08:17:36.47#ibcon#*mode == 0, iclass 6, count 0 2006.173.08:17:36.47#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.08:17:36.47#ibcon#[27=USB\r\n] 2006.173.08:17:36.47#ibcon#*before write, iclass 6, count 0 2006.173.08:17:36.47#ibcon#enter sib2, iclass 6, count 0 2006.173.08:17:36.47#ibcon#flushed, iclass 6, count 0 2006.173.08:17:36.47#ibcon#about to write, iclass 6, count 0 2006.173.08:17:36.47#ibcon#wrote, iclass 6, count 0 2006.173.08:17:36.47#ibcon#about to read 3, iclass 6, count 0 2006.173.08:17:36.50#ibcon#read 3, iclass 6, count 0 2006.173.08:17:36.50#ibcon#about to read 4, iclass 6, count 0 2006.173.08:17:36.50#ibcon#read 4, iclass 6, count 0 2006.173.08:17:36.50#ibcon#about to read 5, iclass 6, count 0 2006.173.08:17:36.50#ibcon#read 5, iclass 6, count 0 2006.173.08:17:36.50#ibcon#about to read 6, iclass 6, count 0 2006.173.08:17:36.50#ibcon#read 6, iclass 6, count 0 2006.173.08:17:36.50#ibcon#end of sib2, iclass 6, count 0 2006.173.08:17:36.50#ibcon#*after write, iclass 6, count 0 2006.173.08:17:36.50#ibcon#*before return 0, iclass 6, count 0 2006.173.08:17:36.50#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.08:17:36.50#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.08:17:36.50#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.08:17:36.50#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.08:17:36.50$vck44/vblo=6,719.99 2006.173.08:17:36.50#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.08:17:36.50#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.08:17:36.50#ibcon#ireg 17 cls_cnt 0 2006.173.08:17:36.50#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.08:17:36.50#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.08:17:36.50#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.08:17:36.50#ibcon#enter wrdev, iclass 10, count 0 2006.173.08:17:36.50#ibcon#first serial, iclass 10, count 0 2006.173.08:17:36.50#ibcon#enter sib2, iclass 10, count 0 2006.173.08:17:36.50#ibcon#flushed, iclass 10, count 0 2006.173.08:17:36.50#ibcon#about to write, iclass 10, count 0 2006.173.08:17:36.50#ibcon#wrote, iclass 10, count 0 2006.173.08:17:36.50#ibcon#about to read 3, iclass 10, count 0 2006.173.08:17:36.52#ibcon#read 3, iclass 10, count 0 2006.173.08:17:36.52#ibcon#about to read 4, iclass 10, count 0 2006.173.08:17:36.52#ibcon#read 4, iclass 10, count 0 2006.173.08:17:36.52#ibcon#about to read 5, iclass 10, count 0 2006.173.08:17:36.52#ibcon#read 5, iclass 10, count 0 2006.173.08:17:36.52#ibcon#about to read 6, iclass 10, count 0 2006.173.08:17:36.52#ibcon#read 6, iclass 10, count 0 2006.173.08:17:36.52#ibcon#end of sib2, iclass 10, count 0 2006.173.08:17:36.52#ibcon#*mode == 0, iclass 10, count 0 2006.173.08:17:36.52#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.08:17:36.52#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.08:17:36.52#ibcon#*before write, iclass 10, count 0 2006.173.08:17:36.52#ibcon#enter sib2, iclass 10, count 0 2006.173.08:17:36.52#ibcon#flushed, iclass 10, count 0 2006.173.08:17:36.52#ibcon#about to write, iclass 10, count 0 2006.173.08:17:36.52#ibcon#wrote, iclass 10, count 0 2006.173.08:17:36.52#ibcon#about to read 3, iclass 10, count 0 2006.173.08:17:36.56#ibcon#read 3, iclass 10, count 0 2006.173.08:17:36.56#ibcon#about to read 4, iclass 10, count 0 2006.173.08:17:36.56#ibcon#read 4, iclass 10, count 0 2006.173.08:17:36.56#ibcon#about to read 5, iclass 10, count 0 2006.173.08:17:36.56#ibcon#read 5, iclass 10, count 0 2006.173.08:17:36.56#ibcon#about to read 6, iclass 10, count 0 2006.173.08:17:36.56#ibcon#read 6, iclass 10, count 0 2006.173.08:17:36.56#ibcon#end of sib2, iclass 10, count 0 2006.173.08:17:36.56#ibcon#*after write, iclass 10, count 0 2006.173.08:17:36.56#ibcon#*before return 0, iclass 10, count 0 2006.173.08:17:36.56#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.08:17:36.56#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.08:17:36.56#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.08:17:36.56#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.08:17:36.56$vck44/vb=6,4 2006.173.08:17:36.56#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.08:17:36.56#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.08:17:36.56#ibcon#ireg 11 cls_cnt 2 2006.173.08:17:36.56#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.08:17:36.62#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.08:17:36.62#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.08:17:36.62#ibcon#enter wrdev, iclass 12, count 2 2006.173.08:17:36.62#ibcon#first serial, iclass 12, count 2 2006.173.08:17:36.62#ibcon#enter sib2, iclass 12, count 2 2006.173.08:17:36.62#ibcon#flushed, iclass 12, count 2 2006.173.08:17:36.62#ibcon#about to write, iclass 12, count 2 2006.173.08:17:36.62#ibcon#wrote, iclass 12, count 2 2006.173.08:17:36.62#ibcon#about to read 3, iclass 12, count 2 2006.173.08:17:36.64#ibcon#read 3, iclass 12, count 2 2006.173.08:17:36.64#ibcon#about to read 4, iclass 12, count 2 2006.173.08:17:36.64#ibcon#read 4, iclass 12, count 2 2006.173.08:17:36.64#ibcon#about to read 5, iclass 12, count 2 2006.173.08:17:36.64#ibcon#read 5, iclass 12, count 2 2006.173.08:17:36.64#ibcon#about to read 6, iclass 12, count 2 2006.173.08:17:36.64#ibcon#read 6, iclass 12, count 2 2006.173.08:17:36.64#ibcon#end of sib2, iclass 12, count 2 2006.173.08:17:36.64#ibcon#*mode == 0, iclass 12, count 2 2006.173.08:17:36.64#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.08:17:36.64#ibcon#[27=AT06-04\r\n] 2006.173.08:17:36.64#ibcon#*before write, iclass 12, count 2 2006.173.08:17:36.64#ibcon#enter sib2, iclass 12, count 2 2006.173.08:17:36.64#ibcon#flushed, iclass 12, count 2 2006.173.08:17:36.64#ibcon#about to write, iclass 12, count 2 2006.173.08:17:36.64#ibcon#wrote, iclass 12, count 2 2006.173.08:17:36.64#ibcon#about to read 3, iclass 12, count 2 2006.173.08:17:36.67#ibcon#read 3, iclass 12, count 2 2006.173.08:17:36.67#ibcon#about to read 4, iclass 12, count 2 2006.173.08:17:36.67#ibcon#read 4, iclass 12, count 2 2006.173.08:17:36.67#ibcon#about to read 5, iclass 12, count 2 2006.173.08:17:36.67#ibcon#read 5, iclass 12, count 2 2006.173.08:17:36.67#ibcon#about to read 6, iclass 12, count 2 2006.173.08:17:36.67#ibcon#read 6, iclass 12, count 2 2006.173.08:17:36.67#ibcon#end of sib2, iclass 12, count 2 2006.173.08:17:36.67#ibcon#*after write, iclass 12, count 2 2006.173.08:17:36.67#ibcon#*before return 0, iclass 12, count 2 2006.173.08:17:36.67#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.08:17:36.67#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.08:17:36.67#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.08:17:36.67#ibcon#ireg 7 cls_cnt 0 2006.173.08:17:36.67#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.08:17:36.79#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.08:17:36.79#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.08:17:36.79#ibcon#enter wrdev, iclass 12, count 0 2006.173.08:17:36.79#ibcon#first serial, iclass 12, count 0 2006.173.08:17:36.79#ibcon#enter sib2, iclass 12, count 0 2006.173.08:17:36.79#ibcon#flushed, iclass 12, count 0 2006.173.08:17:36.79#ibcon#about to write, iclass 12, count 0 2006.173.08:17:36.79#ibcon#wrote, iclass 12, count 0 2006.173.08:17:36.79#ibcon#about to read 3, iclass 12, count 0 2006.173.08:17:36.81#ibcon#read 3, iclass 12, count 0 2006.173.08:17:36.81#ibcon#about to read 4, iclass 12, count 0 2006.173.08:17:36.81#ibcon#read 4, iclass 12, count 0 2006.173.08:17:36.81#ibcon#about to read 5, iclass 12, count 0 2006.173.08:17:36.81#ibcon#read 5, iclass 12, count 0 2006.173.08:17:36.81#ibcon#about to read 6, iclass 12, count 0 2006.173.08:17:36.81#ibcon#read 6, iclass 12, count 0 2006.173.08:17:36.81#ibcon#end of sib2, iclass 12, count 0 2006.173.08:17:36.81#ibcon#*mode == 0, iclass 12, count 0 2006.173.08:17:36.81#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.08:17:36.81#ibcon#[27=USB\r\n] 2006.173.08:17:36.81#ibcon#*before write, iclass 12, count 0 2006.173.08:17:36.81#ibcon#enter sib2, iclass 12, count 0 2006.173.08:17:36.81#ibcon#flushed, iclass 12, count 0 2006.173.08:17:36.81#ibcon#about to write, iclass 12, count 0 2006.173.08:17:36.81#ibcon#wrote, iclass 12, count 0 2006.173.08:17:36.81#ibcon#about to read 3, iclass 12, count 0 2006.173.08:17:36.84#ibcon#read 3, iclass 12, count 0 2006.173.08:17:36.84#ibcon#about to read 4, iclass 12, count 0 2006.173.08:17:36.84#ibcon#read 4, iclass 12, count 0 2006.173.08:17:36.84#ibcon#about to read 5, iclass 12, count 0 2006.173.08:17:36.84#ibcon#read 5, iclass 12, count 0 2006.173.08:17:36.84#ibcon#about to read 6, iclass 12, count 0 2006.173.08:17:36.84#ibcon#read 6, iclass 12, count 0 2006.173.08:17:36.84#ibcon#end of sib2, iclass 12, count 0 2006.173.08:17:36.84#ibcon#*after write, iclass 12, count 0 2006.173.08:17:36.84#ibcon#*before return 0, iclass 12, count 0 2006.173.08:17:36.84#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.08:17:36.84#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.08:17:36.84#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.08:17:36.84#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.08:17:36.84$vck44/vblo=7,734.99 2006.173.08:17:36.84#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.08:17:36.84#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.08:17:36.84#ibcon#ireg 17 cls_cnt 0 2006.173.08:17:36.84#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.08:17:36.84#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.08:17:36.84#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.08:17:36.84#ibcon#enter wrdev, iclass 14, count 0 2006.173.08:17:36.84#ibcon#first serial, iclass 14, count 0 2006.173.08:17:36.84#ibcon#enter sib2, iclass 14, count 0 2006.173.08:17:36.84#ibcon#flushed, iclass 14, count 0 2006.173.08:17:36.84#ibcon#about to write, iclass 14, count 0 2006.173.08:17:36.84#ibcon#wrote, iclass 14, count 0 2006.173.08:17:36.84#ibcon#about to read 3, iclass 14, count 0 2006.173.08:17:36.86#ibcon#read 3, iclass 14, count 0 2006.173.08:17:36.86#ibcon#about to read 4, iclass 14, count 0 2006.173.08:17:36.86#ibcon#read 4, iclass 14, count 0 2006.173.08:17:36.86#ibcon#about to read 5, iclass 14, count 0 2006.173.08:17:36.86#ibcon#read 5, iclass 14, count 0 2006.173.08:17:36.86#ibcon#about to read 6, iclass 14, count 0 2006.173.08:17:36.86#ibcon#read 6, iclass 14, count 0 2006.173.08:17:36.86#ibcon#end of sib2, iclass 14, count 0 2006.173.08:17:36.86#ibcon#*mode == 0, iclass 14, count 0 2006.173.08:17:36.86#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.08:17:36.86#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.08:17:36.86#ibcon#*before write, iclass 14, count 0 2006.173.08:17:36.86#ibcon#enter sib2, iclass 14, count 0 2006.173.08:17:36.86#ibcon#flushed, iclass 14, count 0 2006.173.08:17:36.86#ibcon#about to write, iclass 14, count 0 2006.173.08:17:36.86#ibcon#wrote, iclass 14, count 0 2006.173.08:17:36.86#ibcon#about to read 3, iclass 14, count 0 2006.173.08:17:36.90#ibcon#read 3, iclass 14, count 0 2006.173.08:17:36.90#ibcon#about to read 4, iclass 14, count 0 2006.173.08:17:36.90#ibcon#read 4, iclass 14, count 0 2006.173.08:17:36.90#ibcon#about to read 5, iclass 14, count 0 2006.173.08:17:36.90#ibcon#read 5, iclass 14, count 0 2006.173.08:17:36.90#ibcon#about to read 6, iclass 14, count 0 2006.173.08:17:36.90#ibcon#read 6, iclass 14, count 0 2006.173.08:17:36.90#ibcon#end of sib2, iclass 14, count 0 2006.173.08:17:36.90#ibcon#*after write, iclass 14, count 0 2006.173.08:17:36.90#ibcon#*before return 0, iclass 14, count 0 2006.173.08:17:36.90#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.08:17:36.90#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.08:17:36.90#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.08:17:36.90#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.08:17:36.90$vck44/vb=7,4 2006.173.08:17:36.90#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.08:17:36.90#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.08:17:36.90#ibcon#ireg 11 cls_cnt 2 2006.173.08:17:36.90#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.08:17:36.96#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.08:17:36.96#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.08:17:36.96#ibcon#enter wrdev, iclass 16, count 2 2006.173.08:17:36.96#ibcon#first serial, iclass 16, count 2 2006.173.08:17:36.96#ibcon#enter sib2, iclass 16, count 2 2006.173.08:17:36.96#ibcon#flushed, iclass 16, count 2 2006.173.08:17:36.96#ibcon#about to write, iclass 16, count 2 2006.173.08:17:36.96#ibcon#wrote, iclass 16, count 2 2006.173.08:17:36.96#ibcon#about to read 3, iclass 16, count 2 2006.173.08:17:36.98#ibcon#read 3, iclass 16, count 2 2006.173.08:17:36.98#ibcon#about to read 4, iclass 16, count 2 2006.173.08:17:36.98#ibcon#read 4, iclass 16, count 2 2006.173.08:17:36.98#ibcon#about to read 5, iclass 16, count 2 2006.173.08:17:36.98#ibcon#read 5, iclass 16, count 2 2006.173.08:17:36.98#ibcon#about to read 6, iclass 16, count 2 2006.173.08:17:36.98#ibcon#read 6, iclass 16, count 2 2006.173.08:17:36.98#ibcon#end of sib2, iclass 16, count 2 2006.173.08:17:36.98#ibcon#*mode == 0, iclass 16, count 2 2006.173.08:17:36.98#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.08:17:36.98#ibcon#[27=AT07-04\r\n] 2006.173.08:17:36.98#ibcon#*before write, iclass 16, count 2 2006.173.08:17:36.98#ibcon#enter sib2, iclass 16, count 2 2006.173.08:17:36.98#ibcon#flushed, iclass 16, count 2 2006.173.08:17:36.98#ibcon#about to write, iclass 16, count 2 2006.173.08:17:36.98#ibcon#wrote, iclass 16, count 2 2006.173.08:17:36.98#ibcon#about to read 3, iclass 16, count 2 2006.173.08:17:37.01#ibcon#read 3, iclass 16, count 2 2006.173.08:17:37.01#ibcon#about to read 4, iclass 16, count 2 2006.173.08:17:37.01#ibcon#read 4, iclass 16, count 2 2006.173.08:17:37.01#ibcon#about to read 5, iclass 16, count 2 2006.173.08:17:37.01#ibcon#read 5, iclass 16, count 2 2006.173.08:17:37.01#ibcon#about to read 6, iclass 16, count 2 2006.173.08:17:37.01#ibcon#read 6, iclass 16, count 2 2006.173.08:17:37.01#ibcon#end of sib2, iclass 16, count 2 2006.173.08:17:37.01#ibcon#*after write, iclass 16, count 2 2006.173.08:17:37.01#ibcon#*before return 0, iclass 16, count 2 2006.173.08:17:37.01#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.08:17:37.01#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.08:17:37.01#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.08:17:37.01#ibcon#ireg 7 cls_cnt 0 2006.173.08:17:37.01#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.08:17:37.13#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.08:17:37.13#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.08:17:37.13#ibcon#enter wrdev, iclass 16, count 0 2006.173.08:17:37.13#ibcon#first serial, iclass 16, count 0 2006.173.08:17:37.13#ibcon#enter sib2, iclass 16, count 0 2006.173.08:17:37.13#ibcon#flushed, iclass 16, count 0 2006.173.08:17:37.13#ibcon#about to write, iclass 16, count 0 2006.173.08:17:37.13#ibcon#wrote, iclass 16, count 0 2006.173.08:17:37.13#ibcon#about to read 3, iclass 16, count 0 2006.173.08:17:37.15#ibcon#read 3, iclass 16, count 0 2006.173.08:17:37.15#ibcon#about to read 4, iclass 16, count 0 2006.173.08:17:37.15#ibcon#read 4, iclass 16, count 0 2006.173.08:17:37.15#ibcon#about to read 5, iclass 16, count 0 2006.173.08:17:37.15#ibcon#read 5, iclass 16, count 0 2006.173.08:17:37.15#ibcon#about to read 6, iclass 16, count 0 2006.173.08:17:37.15#ibcon#read 6, iclass 16, count 0 2006.173.08:17:37.15#ibcon#end of sib2, iclass 16, count 0 2006.173.08:17:37.15#ibcon#*mode == 0, iclass 16, count 0 2006.173.08:17:37.15#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.08:17:37.15#ibcon#[27=USB\r\n] 2006.173.08:17:37.15#ibcon#*before write, iclass 16, count 0 2006.173.08:17:37.15#ibcon#enter sib2, iclass 16, count 0 2006.173.08:17:37.15#ibcon#flushed, iclass 16, count 0 2006.173.08:17:37.15#ibcon#about to write, iclass 16, count 0 2006.173.08:17:37.15#ibcon#wrote, iclass 16, count 0 2006.173.08:17:37.15#ibcon#about to read 3, iclass 16, count 0 2006.173.08:17:37.18#ibcon#read 3, iclass 16, count 0 2006.173.08:17:37.18#ibcon#about to read 4, iclass 16, count 0 2006.173.08:17:37.18#ibcon#read 4, iclass 16, count 0 2006.173.08:17:37.18#ibcon#about to read 5, iclass 16, count 0 2006.173.08:17:37.18#ibcon#read 5, iclass 16, count 0 2006.173.08:17:37.18#ibcon#about to read 6, iclass 16, count 0 2006.173.08:17:37.18#ibcon#read 6, iclass 16, count 0 2006.173.08:17:37.18#ibcon#end of sib2, iclass 16, count 0 2006.173.08:17:37.18#ibcon#*after write, iclass 16, count 0 2006.173.08:17:37.18#ibcon#*before return 0, iclass 16, count 0 2006.173.08:17:37.18#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.08:17:37.18#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.08:17:37.18#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.08:17:37.18#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.08:17:37.18$vck44/vblo=8,744.99 2006.173.08:17:37.18#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.08:17:37.18#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.08:17:37.18#ibcon#ireg 17 cls_cnt 0 2006.173.08:17:37.18#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.08:17:37.18#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.08:17:37.18#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.08:17:37.18#ibcon#enter wrdev, iclass 18, count 0 2006.173.08:17:37.18#ibcon#first serial, iclass 18, count 0 2006.173.08:17:37.18#ibcon#enter sib2, iclass 18, count 0 2006.173.08:17:37.18#ibcon#flushed, iclass 18, count 0 2006.173.08:17:37.18#ibcon#about to write, iclass 18, count 0 2006.173.08:17:37.18#ibcon#wrote, iclass 18, count 0 2006.173.08:17:37.18#ibcon#about to read 3, iclass 18, count 0 2006.173.08:17:37.20#ibcon#read 3, iclass 18, count 0 2006.173.08:17:37.20#ibcon#about to read 4, iclass 18, count 0 2006.173.08:17:37.20#ibcon#read 4, iclass 18, count 0 2006.173.08:17:37.20#ibcon#about to read 5, iclass 18, count 0 2006.173.08:17:37.20#ibcon#read 5, iclass 18, count 0 2006.173.08:17:37.20#ibcon#about to read 6, iclass 18, count 0 2006.173.08:17:37.20#ibcon#read 6, iclass 18, count 0 2006.173.08:17:37.20#ibcon#end of sib2, iclass 18, count 0 2006.173.08:17:37.20#ibcon#*mode == 0, iclass 18, count 0 2006.173.08:17:37.20#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.08:17:37.20#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.08:17:37.20#ibcon#*before write, iclass 18, count 0 2006.173.08:17:37.20#ibcon#enter sib2, iclass 18, count 0 2006.173.08:17:37.20#ibcon#flushed, iclass 18, count 0 2006.173.08:17:37.20#ibcon#about to write, iclass 18, count 0 2006.173.08:17:37.20#ibcon#wrote, iclass 18, count 0 2006.173.08:17:37.20#ibcon#about to read 3, iclass 18, count 0 2006.173.08:17:37.24#ibcon#read 3, iclass 18, count 0 2006.173.08:17:37.24#ibcon#about to read 4, iclass 18, count 0 2006.173.08:17:37.24#ibcon#read 4, iclass 18, count 0 2006.173.08:17:37.24#ibcon#about to read 5, iclass 18, count 0 2006.173.08:17:37.24#ibcon#read 5, iclass 18, count 0 2006.173.08:17:37.24#ibcon#about to read 6, iclass 18, count 0 2006.173.08:17:37.24#ibcon#read 6, iclass 18, count 0 2006.173.08:17:37.24#ibcon#end of sib2, iclass 18, count 0 2006.173.08:17:37.24#ibcon#*after write, iclass 18, count 0 2006.173.08:17:37.24#ibcon#*before return 0, iclass 18, count 0 2006.173.08:17:37.24#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.08:17:37.24#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.08:17:37.24#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.08:17:37.24#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.08:17:37.24$vck44/vb=8,4 2006.173.08:17:37.24#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.08:17:37.24#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.08:17:37.24#ibcon#ireg 11 cls_cnt 2 2006.173.08:17:37.24#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.08:17:37.30#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.08:17:37.30#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.08:17:37.30#ibcon#enter wrdev, iclass 20, count 2 2006.173.08:17:37.30#ibcon#first serial, iclass 20, count 2 2006.173.08:17:37.30#ibcon#enter sib2, iclass 20, count 2 2006.173.08:17:37.30#ibcon#flushed, iclass 20, count 2 2006.173.08:17:37.30#ibcon#about to write, iclass 20, count 2 2006.173.08:17:37.30#ibcon#wrote, iclass 20, count 2 2006.173.08:17:37.30#ibcon#about to read 3, iclass 20, count 2 2006.173.08:17:37.32#ibcon#read 3, iclass 20, count 2 2006.173.08:17:37.32#ibcon#about to read 4, iclass 20, count 2 2006.173.08:17:37.32#ibcon#read 4, iclass 20, count 2 2006.173.08:17:37.32#ibcon#about to read 5, iclass 20, count 2 2006.173.08:17:37.32#ibcon#read 5, iclass 20, count 2 2006.173.08:17:37.32#ibcon#about to read 6, iclass 20, count 2 2006.173.08:17:37.32#ibcon#read 6, iclass 20, count 2 2006.173.08:17:37.32#ibcon#end of sib2, iclass 20, count 2 2006.173.08:17:37.32#ibcon#*mode == 0, iclass 20, count 2 2006.173.08:17:37.32#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.08:17:37.32#ibcon#[27=AT08-04\r\n] 2006.173.08:17:37.32#ibcon#*before write, iclass 20, count 2 2006.173.08:17:37.32#ibcon#enter sib2, iclass 20, count 2 2006.173.08:17:37.32#ibcon#flushed, iclass 20, count 2 2006.173.08:17:37.32#ibcon#about to write, iclass 20, count 2 2006.173.08:17:37.32#ibcon#wrote, iclass 20, count 2 2006.173.08:17:37.32#ibcon#about to read 3, iclass 20, count 2 2006.173.08:17:37.35#ibcon#read 3, iclass 20, count 2 2006.173.08:17:37.35#ibcon#about to read 4, iclass 20, count 2 2006.173.08:17:37.35#ibcon#read 4, iclass 20, count 2 2006.173.08:17:37.35#ibcon#about to read 5, iclass 20, count 2 2006.173.08:17:37.35#ibcon#read 5, iclass 20, count 2 2006.173.08:17:37.35#ibcon#about to read 6, iclass 20, count 2 2006.173.08:17:37.35#ibcon#read 6, iclass 20, count 2 2006.173.08:17:37.35#ibcon#end of sib2, iclass 20, count 2 2006.173.08:17:37.35#ibcon#*after write, iclass 20, count 2 2006.173.08:17:37.35#ibcon#*before return 0, iclass 20, count 2 2006.173.08:17:37.35#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.08:17:37.35#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.08:17:37.35#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.08:17:37.35#ibcon#ireg 7 cls_cnt 0 2006.173.08:17:37.35#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.08:17:37.47#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.08:17:37.47#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.08:17:37.47#ibcon#enter wrdev, iclass 20, count 0 2006.173.08:17:37.47#ibcon#first serial, iclass 20, count 0 2006.173.08:17:37.47#ibcon#enter sib2, iclass 20, count 0 2006.173.08:17:37.47#ibcon#flushed, iclass 20, count 0 2006.173.08:17:37.47#ibcon#about to write, iclass 20, count 0 2006.173.08:17:37.47#ibcon#wrote, iclass 20, count 0 2006.173.08:17:37.47#ibcon#about to read 3, iclass 20, count 0 2006.173.08:17:37.49#ibcon#read 3, iclass 20, count 0 2006.173.08:17:37.49#ibcon#about to read 4, iclass 20, count 0 2006.173.08:17:37.49#ibcon#read 4, iclass 20, count 0 2006.173.08:17:37.49#ibcon#about to read 5, iclass 20, count 0 2006.173.08:17:37.49#ibcon#read 5, iclass 20, count 0 2006.173.08:17:37.49#ibcon#about to read 6, iclass 20, count 0 2006.173.08:17:37.49#ibcon#read 6, iclass 20, count 0 2006.173.08:17:37.49#ibcon#end of sib2, iclass 20, count 0 2006.173.08:17:37.49#ibcon#*mode == 0, iclass 20, count 0 2006.173.08:17:37.49#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.08:17:37.49#ibcon#[27=USB\r\n] 2006.173.08:17:37.49#ibcon#*before write, iclass 20, count 0 2006.173.08:17:37.49#ibcon#enter sib2, iclass 20, count 0 2006.173.08:17:37.49#ibcon#flushed, iclass 20, count 0 2006.173.08:17:37.49#ibcon#about to write, iclass 20, count 0 2006.173.08:17:37.49#ibcon#wrote, iclass 20, count 0 2006.173.08:17:37.49#ibcon#about to read 3, iclass 20, count 0 2006.173.08:17:37.52#ibcon#read 3, iclass 20, count 0 2006.173.08:17:37.52#ibcon#about to read 4, iclass 20, count 0 2006.173.08:17:37.52#ibcon#read 4, iclass 20, count 0 2006.173.08:17:37.52#ibcon#about to read 5, iclass 20, count 0 2006.173.08:17:37.52#ibcon#read 5, iclass 20, count 0 2006.173.08:17:37.52#ibcon#about to read 6, iclass 20, count 0 2006.173.08:17:37.52#ibcon#read 6, iclass 20, count 0 2006.173.08:17:37.52#ibcon#end of sib2, iclass 20, count 0 2006.173.08:17:37.52#ibcon#*after write, iclass 20, count 0 2006.173.08:17:37.52#ibcon#*before return 0, iclass 20, count 0 2006.173.08:17:37.52#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.08:17:37.52#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.08:17:37.52#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.08:17:37.52#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.08:17:37.52$vck44/vabw=wide 2006.173.08:17:37.52#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.08:17:37.52#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.08:17:37.52#ibcon#ireg 8 cls_cnt 0 2006.173.08:17:37.52#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.08:17:37.52#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.08:17:37.52#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.08:17:37.52#ibcon#enter wrdev, iclass 22, count 0 2006.173.08:17:37.52#ibcon#first serial, iclass 22, count 0 2006.173.08:17:37.52#ibcon#enter sib2, iclass 22, count 0 2006.173.08:17:37.52#ibcon#flushed, iclass 22, count 0 2006.173.08:17:37.52#ibcon#about to write, iclass 22, count 0 2006.173.08:17:37.52#ibcon#wrote, iclass 22, count 0 2006.173.08:17:37.52#ibcon#about to read 3, iclass 22, count 0 2006.173.08:17:37.54#ibcon#read 3, iclass 22, count 0 2006.173.08:17:37.54#ibcon#about to read 4, iclass 22, count 0 2006.173.08:17:37.54#ibcon#read 4, iclass 22, count 0 2006.173.08:17:37.54#ibcon#about to read 5, iclass 22, count 0 2006.173.08:17:37.54#ibcon#read 5, iclass 22, count 0 2006.173.08:17:37.54#ibcon#about to read 6, iclass 22, count 0 2006.173.08:17:37.54#ibcon#read 6, iclass 22, count 0 2006.173.08:17:37.54#ibcon#end of sib2, iclass 22, count 0 2006.173.08:17:37.54#ibcon#*mode == 0, iclass 22, count 0 2006.173.08:17:37.54#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.08:17:37.54#ibcon#[25=BW32\r\n] 2006.173.08:17:37.54#ibcon#*before write, iclass 22, count 0 2006.173.08:17:37.54#ibcon#enter sib2, iclass 22, count 0 2006.173.08:17:37.54#ibcon#flushed, iclass 22, count 0 2006.173.08:17:37.54#ibcon#about to write, iclass 22, count 0 2006.173.08:17:37.54#ibcon#wrote, iclass 22, count 0 2006.173.08:17:37.54#ibcon#about to read 3, iclass 22, count 0 2006.173.08:17:37.57#ibcon#read 3, iclass 22, count 0 2006.173.08:17:37.57#ibcon#about to read 4, iclass 22, count 0 2006.173.08:17:37.57#ibcon#read 4, iclass 22, count 0 2006.173.08:17:37.57#ibcon#about to read 5, iclass 22, count 0 2006.173.08:17:37.57#ibcon#read 5, iclass 22, count 0 2006.173.08:17:37.57#ibcon#about to read 6, iclass 22, count 0 2006.173.08:17:37.57#ibcon#read 6, iclass 22, count 0 2006.173.08:17:37.57#ibcon#end of sib2, iclass 22, count 0 2006.173.08:17:37.57#ibcon#*after write, iclass 22, count 0 2006.173.08:17:37.57#ibcon#*before return 0, iclass 22, count 0 2006.173.08:17:37.57#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.08:17:37.57#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.08:17:37.57#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.08:17:37.57#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.08:17:37.57$vck44/vbbw=wide 2006.173.08:17:37.57#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.08:17:37.57#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.08:17:37.57#ibcon#ireg 8 cls_cnt 0 2006.173.08:17:37.57#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.08:17:37.64#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.08:17:37.64#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.08:17:37.64#ibcon#enter wrdev, iclass 24, count 0 2006.173.08:17:37.64#ibcon#first serial, iclass 24, count 0 2006.173.08:17:37.64#ibcon#enter sib2, iclass 24, count 0 2006.173.08:17:37.64#ibcon#flushed, iclass 24, count 0 2006.173.08:17:37.64#ibcon#about to write, iclass 24, count 0 2006.173.08:17:37.64#ibcon#wrote, iclass 24, count 0 2006.173.08:17:37.64#ibcon#about to read 3, iclass 24, count 0 2006.173.08:17:37.66#ibcon#read 3, iclass 24, count 0 2006.173.08:17:37.66#ibcon#about to read 4, iclass 24, count 0 2006.173.08:17:37.66#ibcon#read 4, iclass 24, count 0 2006.173.08:17:37.66#ibcon#about to read 5, iclass 24, count 0 2006.173.08:17:37.66#ibcon#read 5, iclass 24, count 0 2006.173.08:17:37.66#ibcon#about to read 6, iclass 24, count 0 2006.173.08:17:37.66#ibcon#read 6, iclass 24, count 0 2006.173.08:17:37.66#ibcon#end of sib2, iclass 24, count 0 2006.173.08:17:37.66#ibcon#*mode == 0, iclass 24, count 0 2006.173.08:17:37.66#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.08:17:37.66#ibcon#[27=BW32\r\n] 2006.173.08:17:37.66#ibcon#*before write, iclass 24, count 0 2006.173.08:17:37.66#ibcon#enter sib2, iclass 24, count 0 2006.173.08:17:37.66#ibcon#flushed, iclass 24, count 0 2006.173.08:17:37.66#ibcon#about to write, iclass 24, count 0 2006.173.08:17:37.66#ibcon#wrote, iclass 24, count 0 2006.173.08:17:37.66#ibcon#about to read 3, iclass 24, count 0 2006.173.08:17:37.69#ibcon#read 3, iclass 24, count 0 2006.173.08:17:37.69#ibcon#about to read 4, iclass 24, count 0 2006.173.08:17:37.69#ibcon#read 4, iclass 24, count 0 2006.173.08:17:37.69#ibcon#about to read 5, iclass 24, count 0 2006.173.08:17:37.69#ibcon#read 5, iclass 24, count 0 2006.173.08:17:37.69#ibcon#about to read 6, iclass 24, count 0 2006.173.08:17:37.69#ibcon#read 6, iclass 24, count 0 2006.173.08:17:37.69#ibcon#end of sib2, iclass 24, count 0 2006.173.08:17:37.69#ibcon#*after write, iclass 24, count 0 2006.173.08:17:37.69#ibcon#*before return 0, iclass 24, count 0 2006.173.08:17:37.69#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.08:17:37.69#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.08:17:37.69#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.08:17:37.69#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.08:17:37.69$setupk4/ifdk4 2006.173.08:17:37.69$ifdk4/lo= 2006.173.08:17:37.69$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.08:17:37.69$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.08:17:37.69$ifdk4/patch= 2006.173.08:17:37.69$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.08:17:37.69$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.08:17:37.69$setupk4/!*+20s 2006.173.08:17:43.60#abcon#<5=/04 0.4 1.0 23.64 861004.1\r\n> 2006.173.08:17:43.62#abcon#{5=INTERFACE CLEAR} 2006.173.08:17:43.68#abcon#[5=S1D000X0/0*\r\n] 2006.173.08:17:46.13#trakl#Source acquired 2006.173.08:17:48.13#flagr#flagr/antenna,acquired 2006.173.08:17:52.19$setupk4/"tpicd 2006.173.08:17:52.19$setupk4/echo=off 2006.173.08:17:52.19$setupk4/xlog=off 2006.173.08:17:52.19:!2006.173.08:18:47 2006.173.08:18:47.00:preob 2006.173.08:18:47.13/onsource/TRACKING 2006.173.08:18:47.13:!2006.173.08:18:57 2006.173.08:18:57.00:"tape 2006.173.08:18:57.00:"st=record 2006.173.08:18:57.00:data_valid=on 2006.173.08:18:57.00:midob 2006.173.08:18:57.13/onsource/TRACKING 2006.173.08:18:57.13/wx/23.64,1004.1,86 2006.173.08:18:57.22/cable/+6.4991E-03 2006.173.08:18:58.31/va/01,07,usb,yes,37,40 2006.173.08:18:58.31/va/02,06,usb,yes,37,38 2006.173.08:18:58.31/va/03,05,usb,yes,47,49 2006.173.08:18:58.31/va/04,06,usb,yes,38,40 2006.173.08:18:58.31/va/05,04,usb,yes,30,30 2006.173.08:18:58.31/va/06,03,usb,yes,42,41 2006.173.08:18:58.31/va/07,04,usb,yes,34,35 2006.173.08:18:58.31/va/08,04,usb,yes,28,34 2006.173.08:18:58.54/valo/01,524.99,yes,locked 2006.173.08:18:58.54/valo/02,534.99,yes,locked 2006.173.08:18:58.54/valo/03,564.99,yes,locked 2006.173.08:18:58.54/valo/04,624.99,yes,locked 2006.173.08:18:58.54/valo/05,734.99,yes,locked 2006.173.08:18:58.54/valo/06,814.99,yes,locked 2006.173.08:18:58.54/valo/07,864.99,yes,locked 2006.173.08:18:58.54/valo/08,884.99,yes,locked 2006.173.08:18:59.63/vb/01,04,usb,yes,36,33 2006.173.08:18:59.63/vb/02,04,usb,yes,38,38 2006.173.08:18:59.63/vb/03,04,usb,yes,35,39 2006.173.08:18:59.63/vb/04,04,usb,yes,40,39 2006.173.08:18:59.63/vb/05,04,usb,yes,31,34 2006.173.08:18:59.63/vb/06,04,usb,yes,36,32 2006.173.08:18:59.63/vb/07,04,usb,yes,36,36 2006.173.08:18:59.63/vb/08,04,usb,yes,33,37 2006.173.08:18:59.86/vblo/01,629.99,yes,locked 2006.173.08:18:59.86/vblo/02,634.99,yes,locked 2006.173.08:18:59.86/vblo/03,649.99,yes,locked 2006.173.08:18:59.86/vblo/04,679.99,yes,locked 2006.173.08:18:59.86/vblo/05,709.99,yes,locked 2006.173.08:18:59.86/vblo/06,719.99,yes,locked 2006.173.08:18:59.86/vblo/07,734.99,yes,locked 2006.173.08:18:59.86/vblo/08,744.99,yes,locked 2006.173.08:19:00.01/vabw/8 2006.173.08:19:00.16/vbbw/8 2006.173.08:19:00.25/xfe/off,on,15.2 2006.173.08:19:00.62/ifatt/23,28,28,28 2006.173.08:19:01.08/fmout-gps/S +3.90E-07 2006.173.08:19:01.12:!2006.173.08:20:27 2006.173.08:20:27.01:data_valid=off 2006.173.08:20:27.01:"et 2006.173.08:20:27.01:!+3s 2006.173.08:20:30.02:"tape 2006.173.08:20:30.02:postob 2006.173.08:20:30.12/cable/+6.5000E-03 2006.173.08:20:30.12/wx/23.61,1004.0,86 2006.173.08:20:31.08/fmout-gps/S +3.92E-07 2006.173.08:20:31.08:scan_name=173-0827,jd0606,420 2006.173.08:20:31.08:source=1418+546,141946.60,542314.8,2000.0,ccw 2006.173.08:20:31.14#flagr#flagr/antenna,new-source 2006.173.08:20:32.14:checkk5 2006.173.08:20:32.53/chk_autoobs//k5ts1/ autoobs is running! 2006.173.08:20:32.92/chk_autoobs//k5ts2/ autoobs is running! 2006.173.08:20:33.34/chk_autoobs//k5ts3/ autoobs is running! 2006.173.08:20:33.73/chk_autoobs//k5ts4/ autoobs is running! 2006.173.08:20:34.12/chk_obsdata//k5ts1/T1730818??a.dat file size is correct (nominal:360MB, actual:356MB). 2006.173.08:20:34.51/chk_obsdata//k5ts2/T1730818??b.dat file size is correct (nominal:360MB, actual:356MB). 2006.173.08:20:34.91/chk_obsdata//k5ts3/T1730818??c.dat file size is correct (nominal:360MB, actual:356MB). 2006.173.08:20:35.32/chk_obsdata//k5ts4/T1730818??d.dat file size is correct (nominal:360MB, actual:356MB). 2006.173.08:20:36.04/k5log//k5ts1_log_newline 2006.173.08:20:36.75/k5log//k5ts2_log_newline 2006.173.08:20:37.47/k5log//k5ts3_log_newline 2006.173.08:20:38.16/k5log//k5ts4_log_newline 2006.173.08:20:38.19/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.08:20:38.19:setupk4=1 2006.173.08:20:38.19$setupk4/echo=on 2006.173.08:20:38.19$setupk4/pcalon 2006.173.08:20:38.19$pcalon/"no phase cal control is implemented here 2006.173.08:20:38.19$setupk4/"tpicd=stop 2006.173.08:20:38.19$setupk4/"rec=synch_on 2006.173.08:20:38.19$setupk4/"rec_mode=128 2006.173.08:20:38.19$setupk4/!* 2006.173.08:20:38.19$setupk4/recpk4 2006.173.08:20:38.19$recpk4/recpatch= 2006.173.08:20:38.20$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.08:20:38.20$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.08:20:38.20$setupk4/vck44 2006.173.08:20:38.20$vck44/valo=1,524.99 2006.173.08:20:38.20#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.08:20:38.20#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.08:20:38.20#ibcon#ireg 17 cls_cnt 0 2006.173.08:20:38.20#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.08:20:38.20#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.08:20:38.20#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.08:20:38.20#ibcon#enter wrdev, iclass 29, count 0 2006.173.08:20:38.20#ibcon#first serial, iclass 29, count 0 2006.173.08:20:38.20#ibcon#enter sib2, iclass 29, count 0 2006.173.08:20:38.20#ibcon#flushed, iclass 29, count 0 2006.173.08:20:38.20#ibcon#about to write, iclass 29, count 0 2006.173.08:20:38.20#ibcon#wrote, iclass 29, count 0 2006.173.08:20:38.20#ibcon#about to read 3, iclass 29, count 0 2006.173.08:20:38.22#ibcon#read 3, iclass 29, count 0 2006.173.08:20:38.22#ibcon#about to read 4, iclass 29, count 0 2006.173.08:20:38.22#ibcon#read 4, iclass 29, count 0 2006.173.08:20:38.22#ibcon#about to read 5, iclass 29, count 0 2006.173.08:20:38.22#ibcon#read 5, iclass 29, count 0 2006.173.08:20:38.22#ibcon#about to read 6, iclass 29, count 0 2006.173.08:20:38.22#ibcon#read 6, iclass 29, count 0 2006.173.08:20:38.22#ibcon#end of sib2, iclass 29, count 0 2006.173.08:20:38.22#ibcon#*mode == 0, iclass 29, count 0 2006.173.08:20:38.22#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.08:20:38.22#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.08:20:38.22#ibcon#*before write, iclass 29, count 0 2006.173.08:20:38.22#ibcon#enter sib2, iclass 29, count 0 2006.173.08:20:38.22#ibcon#flushed, iclass 29, count 0 2006.173.08:20:38.22#ibcon#about to write, iclass 29, count 0 2006.173.08:20:38.22#ibcon#wrote, iclass 29, count 0 2006.173.08:20:38.22#ibcon#about to read 3, iclass 29, count 0 2006.173.08:20:38.27#ibcon#read 3, iclass 29, count 0 2006.173.08:20:38.27#ibcon#about to read 4, iclass 29, count 0 2006.173.08:20:38.27#ibcon#read 4, iclass 29, count 0 2006.173.08:20:38.27#ibcon#about to read 5, iclass 29, count 0 2006.173.08:20:38.27#ibcon#read 5, iclass 29, count 0 2006.173.08:20:38.27#ibcon#about to read 6, iclass 29, count 0 2006.173.08:20:38.27#ibcon#read 6, iclass 29, count 0 2006.173.08:20:38.27#ibcon#end of sib2, iclass 29, count 0 2006.173.08:20:38.27#ibcon#*after write, iclass 29, count 0 2006.173.08:20:38.27#ibcon#*before return 0, iclass 29, count 0 2006.173.08:20:38.27#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.08:20:38.27#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.08:20:38.27#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.08:20:38.27#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.08:20:38.27$vck44/va=1,7 2006.173.08:20:38.27#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.08:20:38.27#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.08:20:38.27#ibcon#ireg 11 cls_cnt 2 2006.173.08:20:38.27#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.08:20:38.27#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.08:20:38.27#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.08:20:38.27#ibcon#enter wrdev, iclass 31, count 2 2006.173.08:20:38.27#ibcon#first serial, iclass 31, count 2 2006.173.08:20:38.27#ibcon#enter sib2, iclass 31, count 2 2006.173.08:20:38.27#ibcon#flushed, iclass 31, count 2 2006.173.08:20:38.27#ibcon#about to write, iclass 31, count 2 2006.173.08:20:38.27#ibcon#wrote, iclass 31, count 2 2006.173.08:20:38.27#ibcon#about to read 3, iclass 31, count 2 2006.173.08:20:38.29#ibcon#read 3, iclass 31, count 2 2006.173.08:20:38.29#ibcon#about to read 4, iclass 31, count 2 2006.173.08:20:38.29#ibcon#read 4, iclass 31, count 2 2006.173.08:20:38.29#ibcon#about to read 5, iclass 31, count 2 2006.173.08:20:38.29#ibcon#read 5, iclass 31, count 2 2006.173.08:20:38.29#ibcon#about to read 6, iclass 31, count 2 2006.173.08:20:38.29#ibcon#read 6, iclass 31, count 2 2006.173.08:20:38.29#ibcon#end of sib2, iclass 31, count 2 2006.173.08:20:38.29#ibcon#*mode == 0, iclass 31, count 2 2006.173.08:20:38.29#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.08:20:38.29#ibcon#[25=AT01-07\r\n] 2006.173.08:20:38.29#ibcon#*before write, iclass 31, count 2 2006.173.08:20:38.29#ibcon#enter sib2, iclass 31, count 2 2006.173.08:20:38.29#ibcon#flushed, iclass 31, count 2 2006.173.08:20:38.29#ibcon#about to write, iclass 31, count 2 2006.173.08:20:38.29#ibcon#wrote, iclass 31, count 2 2006.173.08:20:38.29#ibcon#about to read 3, iclass 31, count 2 2006.173.08:20:38.32#ibcon#read 3, iclass 31, count 2 2006.173.08:20:38.32#ibcon#about to read 4, iclass 31, count 2 2006.173.08:20:38.32#ibcon#read 4, iclass 31, count 2 2006.173.08:20:38.32#ibcon#about to read 5, iclass 31, count 2 2006.173.08:20:38.32#ibcon#read 5, iclass 31, count 2 2006.173.08:20:38.32#ibcon#about to read 6, iclass 31, count 2 2006.173.08:20:38.32#ibcon#read 6, iclass 31, count 2 2006.173.08:20:38.32#ibcon#end of sib2, iclass 31, count 2 2006.173.08:20:38.32#ibcon#*after write, iclass 31, count 2 2006.173.08:20:38.32#ibcon#*before return 0, iclass 31, count 2 2006.173.08:20:38.32#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.08:20:38.32#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.08:20:38.32#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.08:20:38.32#ibcon#ireg 7 cls_cnt 0 2006.173.08:20:38.32#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.08:20:38.44#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.08:20:38.44#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.08:20:38.44#ibcon#enter wrdev, iclass 31, count 0 2006.173.08:20:38.44#ibcon#first serial, iclass 31, count 0 2006.173.08:20:38.44#ibcon#enter sib2, iclass 31, count 0 2006.173.08:20:38.44#ibcon#flushed, iclass 31, count 0 2006.173.08:20:38.44#ibcon#about to write, iclass 31, count 0 2006.173.08:20:38.44#ibcon#wrote, iclass 31, count 0 2006.173.08:20:38.44#ibcon#about to read 3, iclass 31, count 0 2006.173.08:20:38.46#ibcon#read 3, iclass 31, count 0 2006.173.08:20:38.46#ibcon#about to read 4, iclass 31, count 0 2006.173.08:20:38.46#ibcon#read 4, iclass 31, count 0 2006.173.08:20:38.46#ibcon#about to read 5, iclass 31, count 0 2006.173.08:20:38.46#ibcon#read 5, iclass 31, count 0 2006.173.08:20:38.46#ibcon#about to read 6, iclass 31, count 0 2006.173.08:20:38.46#ibcon#read 6, iclass 31, count 0 2006.173.08:20:38.46#ibcon#end of sib2, iclass 31, count 0 2006.173.08:20:38.46#ibcon#*mode == 0, iclass 31, count 0 2006.173.08:20:38.46#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.08:20:38.46#ibcon#[25=USB\r\n] 2006.173.08:20:38.46#ibcon#*before write, iclass 31, count 0 2006.173.08:20:38.46#ibcon#enter sib2, iclass 31, count 0 2006.173.08:20:38.46#ibcon#flushed, iclass 31, count 0 2006.173.08:20:38.46#ibcon#about to write, iclass 31, count 0 2006.173.08:20:38.46#ibcon#wrote, iclass 31, count 0 2006.173.08:20:38.46#ibcon#about to read 3, iclass 31, count 0 2006.173.08:20:38.49#ibcon#read 3, iclass 31, count 0 2006.173.08:20:38.49#ibcon#about to read 4, iclass 31, count 0 2006.173.08:20:38.49#ibcon#read 4, iclass 31, count 0 2006.173.08:20:38.49#ibcon#about to read 5, iclass 31, count 0 2006.173.08:20:38.49#ibcon#read 5, iclass 31, count 0 2006.173.08:20:38.49#ibcon#about to read 6, iclass 31, count 0 2006.173.08:20:38.49#ibcon#read 6, iclass 31, count 0 2006.173.08:20:38.49#ibcon#end of sib2, iclass 31, count 0 2006.173.08:20:38.49#ibcon#*after write, iclass 31, count 0 2006.173.08:20:38.49#ibcon#*before return 0, iclass 31, count 0 2006.173.08:20:38.49#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.08:20:38.49#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.08:20:38.49#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.08:20:38.49#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.08:20:38.49$vck44/valo=2,534.99 2006.173.08:20:38.49#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.08:20:38.49#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.08:20:38.49#ibcon#ireg 17 cls_cnt 0 2006.173.08:20:38.49#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.08:20:38.49#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.08:20:38.49#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.08:20:38.49#ibcon#enter wrdev, iclass 33, count 0 2006.173.08:20:38.49#ibcon#first serial, iclass 33, count 0 2006.173.08:20:38.49#ibcon#enter sib2, iclass 33, count 0 2006.173.08:20:38.49#ibcon#flushed, iclass 33, count 0 2006.173.08:20:38.49#ibcon#about to write, iclass 33, count 0 2006.173.08:20:38.49#ibcon#wrote, iclass 33, count 0 2006.173.08:20:38.49#ibcon#about to read 3, iclass 33, count 0 2006.173.08:20:38.51#ibcon#read 3, iclass 33, count 0 2006.173.08:20:38.51#ibcon#about to read 4, iclass 33, count 0 2006.173.08:20:38.51#ibcon#read 4, iclass 33, count 0 2006.173.08:20:38.51#ibcon#about to read 5, iclass 33, count 0 2006.173.08:20:38.51#ibcon#read 5, iclass 33, count 0 2006.173.08:20:38.51#ibcon#about to read 6, iclass 33, count 0 2006.173.08:20:38.51#ibcon#read 6, iclass 33, count 0 2006.173.08:20:38.51#ibcon#end of sib2, iclass 33, count 0 2006.173.08:20:38.51#ibcon#*mode == 0, iclass 33, count 0 2006.173.08:20:38.51#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.08:20:38.51#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.08:20:38.51#ibcon#*before write, iclass 33, count 0 2006.173.08:20:38.51#ibcon#enter sib2, iclass 33, count 0 2006.173.08:20:38.51#ibcon#flushed, iclass 33, count 0 2006.173.08:20:38.51#ibcon#about to write, iclass 33, count 0 2006.173.08:20:38.51#ibcon#wrote, iclass 33, count 0 2006.173.08:20:38.51#ibcon#about to read 3, iclass 33, count 0 2006.173.08:20:38.55#ibcon#read 3, iclass 33, count 0 2006.173.08:20:38.55#ibcon#about to read 4, iclass 33, count 0 2006.173.08:20:38.55#ibcon#read 4, iclass 33, count 0 2006.173.08:20:38.55#ibcon#about to read 5, iclass 33, count 0 2006.173.08:20:38.55#ibcon#read 5, iclass 33, count 0 2006.173.08:20:38.55#ibcon#about to read 6, iclass 33, count 0 2006.173.08:20:38.55#ibcon#read 6, iclass 33, count 0 2006.173.08:20:38.55#ibcon#end of sib2, iclass 33, count 0 2006.173.08:20:38.55#ibcon#*after write, iclass 33, count 0 2006.173.08:20:38.55#ibcon#*before return 0, iclass 33, count 0 2006.173.08:20:38.55#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.08:20:38.55#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.08:20:38.55#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.08:20:38.55#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.08:20:38.55$vck44/va=2,6 2006.173.08:20:38.55#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.08:20:38.55#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.08:20:38.55#ibcon#ireg 11 cls_cnt 2 2006.173.08:20:38.55#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.08:20:38.61#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.08:20:38.61#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.08:20:38.61#ibcon#enter wrdev, iclass 35, count 2 2006.173.08:20:38.61#ibcon#first serial, iclass 35, count 2 2006.173.08:20:38.61#ibcon#enter sib2, iclass 35, count 2 2006.173.08:20:38.61#ibcon#flushed, iclass 35, count 2 2006.173.08:20:38.61#ibcon#about to write, iclass 35, count 2 2006.173.08:20:38.61#ibcon#wrote, iclass 35, count 2 2006.173.08:20:38.61#ibcon#about to read 3, iclass 35, count 2 2006.173.08:20:38.63#ibcon#read 3, iclass 35, count 2 2006.173.08:20:38.63#ibcon#about to read 4, iclass 35, count 2 2006.173.08:20:38.63#ibcon#read 4, iclass 35, count 2 2006.173.08:20:38.63#ibcon#about to read 5, iclass 35, count 2 2006.173.08:20:38.63#ibcon#read 5, iclass 35, count 2 2006.173.08:20:38.63#ibcon#about to read 6, iclass 35, count 2 2006.173.08:20:38.63#ibcon#read 6, iclass 35, count 2 2006.173.08:20:38.63#ibcon#end of sib2, iclass 35, count 2 2006.173.08:20:38.63#ibcon#*mode == 0, iclass 35, count 2 2006.173.08:20:38.63#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.08:20:38.63#ibcon#[25=AT02-06\r\n] 2006.173.08:20:38.63#ibcon#*before write, iclass 35, count 2 2006.173.08:20:38.63#ibcon#enter sib2, iclass 35, count 2 2006.173.08:20:38.63#ibcon#flushed, iclass 35, count 2 2006.173.08:20:38.63#ibcon#about to write, iclass 35, count 2 2006.173.08:20:38.63#ibcon#wrote, iclass 35, count 2 2006.173.08:20:38.63#ibcon#about to read 3, iclass 35, count 2 2006.173.08:20:38.66#ibcon#read 3, iclass 35, count 2 2006.173.08:20:38.66#ibcon#about to read 4, iclass 35, count 2 2006.173.08:20:38.66#ibcon#read 4, iclass 35, count 2 2006.173.08:20:38.66#ibcon#about to read 5, iclass 35, count 2 2006.173.08:20:38.66#ibcon#read 5, iclass 35, count 2 2006.173.08:20:38.66#ibcon#about to read 6, iclass 35, count 2 2006.173.08:20:38.66#ibcon#read 6, iclass 35, count 2 2006.173.08:20:38.66#ibcon#end of sib2, iclass 35, count 2 2006.173.08:20:38.66#ibcon#*after write, iclass 35, count 2 2006.173.08:20:38.66#ibcon#*before return 0, iclass 35, count 2 2006.173.08:20:38.66#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.08:20:38.66#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.08:20:38.66#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.08:20:38.66#ibcon#ireg 7 cls_cnt 0 2006.173.08:20:38.66#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.08:20:38.78#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.08:20:38.78#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.08:20:38.78#ibcon#enter wrdev, iclass 35, count 0 2006.173.08:20:38.78#ibcon#first serial, iclass 35, count 0 2006.173.08:20:38.78#ibcon#enter sib2, iclass 35, count 0 2006.173.08:20:38.78#ibcon#flushed, iclass 35, count 0 2006.173.08:20:38.78#ibcon#about to write, iclass 35, count 0 2006.173.08:20:38.78#ibcon#wrote, iclass 35, count 0 2006.173.08:20:38.78#ibcon#about to read 3, iclass 35, count 0 2006.173.08:20:38.80#ibcon#read 3, iclass 35, count 0 2006.173.08:20:38.80#ibcon#about to read 4, iclass 35, count 0 2006.173.08:20:38.80#ibcon#read 4, iclass 35, count 0 2006.173.08:20:38.80#ibcon#about to read 5, iclass 35, count 0 2006.173.08:20:38.80#ibcon#read 5, iclass 35, count 0 2006.173.08:20:38.80#ibcon#about to read 6, iclass 35, count 0 2006.173.08:20:38.80#ibcon#read 6, iclass 35, count 0 2006.173.08:20:38.80#ibcon#end of sib2, iclass 35, count 0 2006.173.08:20:38.80#ibcon#*mode == 0, iclass 35, count 0 2006.173.08:20:38.80#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.08:20:38.80#ibcon#[25=USB\r\n] 2006.173.08:20:38.80#ibcon#*before write, iclass 35, count 0 2006.173.08:20:38.80#ibcon#enter sib2, iclass 35, count 0 2006.173.08:20:38.80#ibcon#flushed, iclass 35, count 0 2006.173.08:20:38.80#ibcon#about to write, iclass 35, count 0 2006.173.08:20:38.80#ibcon#wrote, iclass 35, count 0 2006.173.08:20:38.80#ibcon#about to read 3, iclass 35, count 0 2006.173.08:20:38.83#ibcon#read 3, iclass 35, count 0 2006.173.08:20:38.83#ibcon#about to read 4, iclass 35, count 0 2006.173.08:20:38.83#ibcon#read 4, iclass 35, count 0 2006.173.08:20:38.83#ibcon#about to read 5, iclass 35, count 0 2006.173.08:20:38.83#ibcon#read 5, iclass 35, count 0 2006.173.08:20:38.83#ibcon#about to read 6, iclass 35, count 0 2006.173.08:20:38.83#ibcon#read 6, iclass 35, count 0 2006.173.08:20:38.83#ibcon#end of sib2, iclass 35, count 0 2006.173.08:20:38.83#ibcon#*after write, iclass 35, count 0 2006.173.08:20:38.83#ibcon#*before return 0, iclass 35, count 0 2006.173.08:20:38.83#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.08:20:38.83#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.08:20:38.83#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.08:20:38.83#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.08:20:38.83$vck44/valo=3,564.99 2006.173.08:20:38.83#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.08:20:38.83#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.08:20:38.83#ibcon#ireg 17 cls_cnt 0 2006.173.08:20:38.83#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.08:20:38.83#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.08:20:38.83#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.08:20:38.83#ibcon#enter wrdev, iclass 37, count 0 2006.173.08:20:38.83#ibcon#first serial, iclass 37, count 0 2006.173.08:20:38.83#ibcon#enter sib2, iclass 37, count 0 2006.173.08:20:38.83#ibcon#flushed, iclass 37, count 0 2006.173.08:20:38.83#ibcon#about to write, iclass 37, count 0 2006.173.08:20:38.83#ibcon#wrote, iclass 37, count 0 2006.173.08:20:38.83#ibcon#about to read 3, iclass 37, count 0 2006.173.08:20:38.85#ibcon#read 3, iclass 37, count 0 2006.173.08:20:38.85#ibcon#about to read 4, iclass 37, count 0 2006.173.08:20:38.85#ibcon#read 4, iclass 37, count 0 2006.173.08:20:38.85#ibcon#about to read 5, iclass 37, count 0 2006.173.08:20:38.85#ibcon#read 5, iclass 37, count 0 2006.173.08:20:38.85#ibcon#about to read 6, iclass 37, count 0 2006.173.08:20:38.85#ibcon#read 6, iclass 37, count 0 2006.173.08:20:38.85#ibcon#end of sib2, iclass 37, count 0 2006.173.08:20:38.85#ibcon#*mode == 0, iclass 37, count 0 2006.173.08:20:38.85#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.08:20:38.85#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.08:20:38.85#ibcon#*before write, iclass 37, count 0 2006.173.08:20:38.85#ibcon#enter sib2, iclass 37, count 0 2006.173.08:20:38.85#ibcon#flushed, iclass 37, count 0 2006.173.08:20:38.85#ibcon#about to write, iclass 37, count 0 2006.173.08:20:38.85#ibcon#wrote, iclass 37, count 0 2006.173.08:20:38.85#ibcon#about to read 3, iclass 37, count 0 2006.173.08:20:38.89#ibcon#read 3, iclass 37, count 0 2006.173.08:20:38.89#ibcon#about to read 4, iclass 37, count 0 2006.173.08:20:38.89#ibcon#read 4, iclass 37, count 0 2006.173.08:20:38.89#ibcon#about to read 5, iclass 37, count 0 2006.173.08:20:38.89#ibcon#read 5, iclass 37, count 0 2006.173.08:20:38.89#ibcon#about to read 6, iclass 37, count 0 2006.173.08:20:38.89#ibcon#read 6, iclass 37, count 0 2006.173.08:20:38.89#ibcon#end of sib2, iclass 37, count 0 2006.173.08:20:38.89#ibcon#*after write, iclass 37, count 0 2006.173.08:20:38.89#ibcon#*before return 0, iclass 37, count 0 2006.173.08:20:38.89#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.08:20:38.89#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.08:20:38.89#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.08:20:38.89#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.08:20:38.89$vck44/va=3,5 2006.173.08:20:38.89#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.08:20:38.89#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.08:20:38.89#ibcon#ireg 11 cls_cnt 2 2006.173.08:20:38.89#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.08:20:38.95#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.08:20:38.95#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.08:20:38.95#ibcon#enter wrdev, iclass 39, count 2 2006.173.08:20:38.95#ibcon#first serial, iclass 39, count 2 2006.173.08:20:38.95#ibcon#enter sib2, iclass 39, count 2 2006.173.08:20:38.95#ibcon#flushed, iclass 39, count 2 2006.173.08:20:38.95#ibcon#about to write, iclass 39, count 2 2006.173.08:20:38.95#ibcon#wrote, iclass 39, count 2 2006.173.08:20:38.95#ibcon#about to read 3, iclass 39, count 2 2006.173.08:20:38.97#ibcon#read 3, iclass 39, count 2 2006.173.08:20:38.97#ibcon#about to read 4, iclass 39, count 2 2006.173.08:20:38.97#ibcon#read 4, iclass 39, count 2 2006.173.08:20:38.97#ibcon#about to read 5, iclass 39, count 2 2006.173.08:20:38.97#ibcon#read 5, iclass 39, count 2 2006.173.08:20:38.97#ibcon#about to read 6, iclass 39, count 2 2006.173.08:20:38.97#ibcon#read 6, iclass 39, count 2 2006.173.08:20:38.97#ibcon#end of sib2, iclass 39, count 2 2006.173.08:20:38.97#ibcon#*mode == 0, iclass 39, count 2 2006.173.08:20:38.97#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.08:20:38.97#ibcon#[25=AT03-05\r\n] 2006.173.08:20:38.97#ibcon#*before write, iclass 39, count 2 2006.173.08:20:38.97#ibcon#enter sib2, iclass 39, count 2 2006.173.08:20:38.97#ibcon#flushed, iclass 39, count 2 2006.173.08:20:38.97#ibcon#about to write, iclass 39, count 2 2006.173.08:20:38.97#ibcon#wrote, iclass 39, count 2 2006.173.08:20:38.97#ibcon#about to read 3, iclass 39, count 2 2006.173.08:20:39.00#ibcon#read 3, iclass 39, count 2 2006.173.08:20:39.00#ibcon#about to read 4, iclass 39, count 2 2006.173.08:20:39.00#ibcon#read 4, iclass 39, count 2 2006.173.08:20:39.00#ibcon#about to read 5, iclass 39, count 2 2006.173.08:20:39.00#ibcon#read 5, iclass 39, count 2 2006.173.08:20:39.00#ibcon#about to read 6, iclass 39, count 2 2006.173.08:20:39.00#ibcon#read 6, iclass 39, count 2 2006.173.08:20:39.00#ibcon#end of sib2, iclass 39, count 2 2006.173.08:20:39.00#ibcon#*after write, iclass 39, count 2 2006.173.08:20:39.00#ibcon#*before return 0, iclass 39, count 2 2006.173.08:20:39.00#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.08:20:39.00#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.08:20:39.00#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.08:20:39.00#ibcon#ireg 7 cls_cnt 0 2006.173.08:20:39.00#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.08:20:39.12#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.08:20:39.12#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.08:20:39.12#ibcon#enter wrdev, iclass 39, count 0 2006.173.08:20:39.12#ibcon#first serial, iclass 39, count 0 2006.173.08:20:39.12#ibcon#enter sib2, iclass 39, count 0 2006.173.08:20:39.12#ibcon#flushed, iclass 39, count 0 2006.173.08:20:39.12#ibcon#about to write, iclass 39, count 0 2006.173.08:20:39.12#ibcon#wrote, iclass 39, count 0 2006.173.08:20:39.12#ibcon#about to read 3, iclass 39, count 0 2006.173.08:20:39.14#ibcon#read 3, iclass 39, count 0 2006.173.08:20:39.14#ibcon#about to read 4, iclass 39, count 0 2006.173.08:20:39.14#ibcon#read 4, iclass 39, count 0 2006.173.08:20:39.14#ibcon#about to read 5, iclass 39, count 0 2006.173.08:20:39.14#ibcon#read 5, iclass 39, count 0 2006.173.08:20:39.14#ibcon#about to read 6, iclass 39, count 0 2006.173.08:20:39.14#ibcon#read 6, iclass 39, count 0 2006.173.08:20:39.14#ibcon#end of sib2, iclass 39, count 0 2006.173.08:20:39.14#ibcon#*mode == 0, iclass 39, count 0 2006.173.08:20:39.14#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.08:20:39.14#ibcon#[25=USB\r\n] 2006.173.08:20:39.14#ibcon#*before write, iclass 39, count 0 2006.173.08:20:39.14#ibcon#enter sib2, iclass 39, count 0 2006.173.08:20:39.14#ibcon#flushed, iclass 39, count 0 2006.173.08:20:39.14#ibcon#about to write, iclass 39, count 0 2006.173.08:20:39.14#ibcon#wrote, iclass 39, count 0 2006.173.08:20:39.14#ibcon#about to read 3, iclass 39, count 0 2006.173.08:20:39.17#ibcon#read 3, iclass 39, count 0 2006.173.08:20:39.17#ibcon#about to read 4, iclass 39, count 0 2006.173.08:20:39.17#ibcon#read 4, iclass 39, count 0 2006.173.08:20:39.17#ibcon#about to read 5, iclass 39, count 0 2006.173.08:20:39.17#ibcon#read 5, iclass 39, count 0 2006.173.08:20:39.17#ibcon#about to read 6, iclass 39, count 0 2006.173.08:20:39.17#ibcon#read 6, iclass 39, count 0 2006.173.08:20:39.17#ibcon#end of sib2, iclass 39, count 0 2006.173.08:20:39.17#ibcon#*after write, iclass 39, count 0 2006.173.08:20:39.17#ibcon#*before return 0, iclass 39, count 0 2006.173.08:20:39.17#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.08:20:39.17#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.08:20:39.17#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.08:20:39.17#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.08:20:39.17$vck44/valo=4,624.99 2006.173.08:20:39.17#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.08:20:39.17#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.08:20:39.17#ibcon#ireg 17 cls_cnt 0 2006.173.08:20:39.17#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.08:20:39.17#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.08:20:39.17#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.08:20:39.17#ibcon#enter wrdev, iclass 3, count 0 2006.173.08:20:39.17#ibcon#first serial, iclass 3, count 0 2006.173.08:20:39.17#ibcon#enter sib2, iclass 3, count 0 2006.173.08:20:39.17#ibcon#flushed, iclass 3, count 0 2006.173.08:20:39.17#ibcon#about to write, iclass 3, count 0 2006.173.08:20:39.17#ibcon#wrote, iclass 3, count 0 2006.173.08:20:39.17#ibcon#about to read 3, iclass 3, count 0 2006.173.08:20:39.19#ibcon#read 3, iclass 3, count 0 2006.173.08:20:39.19#ibcon#about to read 4, iclass 3, count 0 2006.173.08:20:39.19#ibcon#read 4, iclass 3, count 0 2006.173.08:20:39.19#ibcon#about to read 5, iclass 3, count 0 2006.173.08:20:39.19#ibcon#read 5, iclass 3, count 0 2006.173.08:20:39.19#ibcon#about to read 6, iclass 3, count 0 2006.173.08:20:39.19#ibcon#read 6, iclass 3, count 0 2006.173.08:20:39.19#ibcon#end of sib2, iclass 3, count 0 2006.173.08:20:39.19#ibcon#*mode == 0, iclass 3, count 0 2006.173.08:20:39.19#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.08:20:39.19#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.08:20:39.19#ibcon#*before write, iclass 3, count 0 2006.173.08:20:39.19#ibcon#enter sib2, iclass 3, count 0 2006.173.08:20:39.19#ibcon#flushed, iclass 3, count 0 2006.173.08:20:39.19#ibcon#about to write, iclass 3, count 0 2006.173.08:20:39.19#ibcon#wrote, iclass 3, count 0 2006.173.08:20:39.19#ibcon#about to read 3, iclass 3, count 0 2006.173.08:20:39.23#ibcon#read 3, iclass 3, count 0 2006.173.08:20:39.23#ibcon#about to read 4, iclass 3, count 0 2006.173.08:20:39.23#ibcon#read 4, iclass 3, count 0 2006.173.08:20:39.23#ibcon#about to read 5, iclass 3, count 0 2006.173.08:20:39.23#ibcon#read 5, iclass 3, count 0 2006.173.08:20:39.23#ibcon#about to read 6, iclass 3, count 0 2006.173.08:20:39.23#ibcon#read 6, iclass 3, count 0 2006.173.08:20:39.23#ibcon#end of sib2, iclass 3, count 0 2006.173.08:20:39.23#ibcon#*after write, iclass 3, count 0 2006.173.08:20:39.23#ibcon#*before return 0, iclass 3, count 0 2006.173.08:20:39.23#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.08:20:39.23#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.08:20:39.23#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.08:20:39.23#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.08:20:39.23$vck44/va=4,6 2006.173.08:20:39.23#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.08:20:39.23#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.08:20:39.23#ibcon#ireg 11 cls_cnt 2 2006.173.08:20:39.23#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.08:20:39.29#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.08:20:39.29#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.08:20:39.29#ibcon#enter wrdev, iclass 5, count 2 2006.173.08:20:39.29#ibcon#first serial, iclass 5, count 2 2006.173.08:20:39.29#ibcon#enter sib2, iclass 5, count 2 2006.173.08:20:39.29#ibcon#flushed, iclass 5, count 2 2006.173.08:20:39.29#ibcon#about to write, iclass 5, count 2 2006.173.08:20:39.29#ibcon#wrote, iclass 5, count 2 2006.173.08:20:39.29#ibcon#about to read 3, iclass 5, count 2 2006.173.08:20:39.31#ibcon#read 3, iclass 5, count 2 2006.173.08:20:39.31#ibcon#about to read 4, iclass 5, count 2 2006.173.08:20:39.31#ibcon#read 4, iclass 5, count 2 2006.173.08:20:39.31#ibcon#about to read 5, iclass 5, count 2 2006.173.08:20:39.31#ibcon#read 5, iclass 5, count 2 2006.173.08:20:39.31#ibcon#about to read 6, iclass 5, count 2 2006.173.08:20:39.31#ibcon#read 6, iclass 5, count 2 2006.173.08:20:39.31#ibcon#end of sib2, iclass 5, count 2 2006.173.08:20:39.31#ibcon#*mode == 0, iclass 5, count 2 2006.173.08:20:39.31#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.08:20:39.31#ibcon#[25=AT04-06\r\n] 2006.173.08:20:39.31#ibcon#*before write, iclass 5, count 2 2006.173.08:20:39.31#ibcon#enter sib2, iclass 5, count 2 2006.173.08:20:39.31#ibcon#flushed, iclass 5, count 2 2006.173.08:20:39.31#ibcon#about to write, iclass 5, count 2 2006.173.08:20:39.31#ibcon#wrote, iclass 5, count 2 2006.173.08:20:39.31#ibcon#about to read 3, iclass 5, count 2 2006.173.08:20:39.34#ibcon#read 3, iclass 5, count 2 2006.173.08:20:39.34#ibcon#about to read 4, iclass 5, count 2 2006.173.08:20:39.34#ibcon#read 4, iclass 5, count 2 2006.173.08:20:39.34#ibcon#about to read 5, iclass 5, count 2 2006.173.08:20:39.34#ibcon#read 5, iclass 5, count 2 2006.173.08:20:39.34#ibcon#about to read 6, iclass 5, count 2 2006.173.08:20:39.34#ibcon#read 6, iclass 5, count 2 2006.173.08:20:39.34#ibcon#end of sib2, iclass 5, count 2 2006.173.08:20:39.34#ibcon#*after write, iclass 5, count 2 2006.173.08:20:39.34#ibcon#*before return 0, iclass 5, count 2 2006.173.08:20:39.34#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.08:20:39.34#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.08:20:39.34#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.08:20:39.34#ibcon#ireg 7 cls_cnt 0 2006.173.08:20:39.34#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.08:20:39.46#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.08:20:39.46#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.08:20:39.46#ibcon#enter wrdev, iclass 5, count 0 2006.173.08:20:39.46#ibcon#first serial, iclass 5, count 0 2006.173.08:20:39.46#ibcon#enter sib2, iclass 5, count 0 2006.173.08:20:39.46#ibcon#flushed, iclass 5, count 0 2006.173.08:20:39.46#ibcon#about to write, iclass 5, count 0 2006.173.08:20:39.46#ibcon#wrote, iclass 5, count 0 2006.173.08:20:39.46#ibcon#about to read 3, iclass 5, count 0 2006.173.08:20:39.48#ibcon#read 3, iclass 5, count 0 2006.173.08:20:39.48#ibcon#about to read 4, iclass 5, count 0 2006.173.08:20:39.48#ibcon#read 4, iclass 5, count 0 2006.173.08:20:39.48#ibcon#about to read 5, iclass 5, count 0 2006.173.08:20:39.48#ibcon#read 5, iclass 5, count 0 2006.173.08:20:39.48#ibcon#about to read 6, iclass 5, count 0 2006.173.08:20:39.48#ibcon#read 6, iclass 5, count 0 2006.173.08:20:39.48#ibcon#end of sib2, iclass 5, count 0 2006.173.08:20:39.48#ibcon#*mode == 0, iclass 5, count 0 2006.173.08:20:39.48#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.08:20:39.48#ibcon#[25=USB\r\n] 2006.173.08:20:39.48#ibcon#*before write, iclass 5, count 0 2006.173.08:20:39.48#ibcon#enter sib2, iclass 5, count 0 2006.173.08:20:39.48#ibcon#flushed, iclass 5, count 0 2006.173.08:20:39.48#ibcon#about to write, iclass 5, count 0 2006.173.08:20:39.48#ibcon#wrote, iclass 5, count 0 2006.173.08:20:39.48#ibcon#about to read 3, iclass 5, count 0 2006.173.08:20:39.51#ibcon#read 3, iclass 5, count 0 2006.173.08:20:39.51#ibcon#about to read 4, iclass 5, count 0 2006.173.08:20:39.51#ibcon#read 4, iclass 5, count 0 2006.173.08:20:39.51#ibcon#about to read 5, iclass 5, count 0 2006.173.08:20:39.51#ibcon#read 5, iclass 5, count 0 2006.173.08:20:39.51#ibcon#about to read 6, iclass 5, count 0 2006.173.08:20:39.51#ibcon#read 6, iclass 5, count 0 2006.173.08:20:39.51#ibcon#end of sib2, iclass 5, count 0 2006.173.08:20:39.51#ibcon#*after write, iclass 5, count 0 2006.173.08:20:39.51#ibcon#*before return 0, iclass 5, count 0 2006.173.08:20:39.51#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.08:20:39.51#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.08:20:39.51#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.08:20:39.51#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.08:20:39.51$vck44/valo=5,734.99 2006.173.08:20:39.51#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.08:20:39.51#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.08:20:39.51#ibcon#ireg 17 cls_cnt 0 2006.173.08:20:39.51#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.08:20:39.51#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.08:20:39.51#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.08:20:39.51#ibcon#enter wrdev, iclass 7, count 0 2006.173.08:20:39.51#ibcon#first serial, iclass 7, count 0 2006.173.08:20:39.51#ibcon#enter sib2, iclass 7, count 0 2006.173.08:20:39.51#ibcon#flushed, iclass 7, count 0 2006.173.08:20:39.51#ibcon#about to write, iclass 7, count 0 2006.173.08:20:39.51#ibcon#wrote, iclass 7, count 0 2006.173.08:20:39.51#ibcon#about to read 3, iclass 7, count 0 2006.173.08:20:39.53#ibcon#read 3, iclass 7, count 0 2006.173.08:20:39.53#ibcon#about to read 4, iclass 7, count 0 2006.173.08:20:39.53#ibcon#read 4, iclass 7, count 0 2006.173.08:20:39.53#ibcon#about to read 5, iclass 7, count 0 2006.173.08:20:39.53#ibcon#read 5, iclass 7, count 0 2006.173.08:20:39.53#ibcon#about to read 6, iclass 7, count 0 2006.173.08:20:39.53#ibcon#read 6, iclass 7, count 0 2006.173.08:20:39.53#ibcon#end of sib2, iclass 7, count 0 2006.173.08:20:39.53#ibcon#*mode == 0, iclass 7, count 0 2006.173.08:20:39.53#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.08:20:39.53#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.08:20:39.53#ibcon#*before write, iclass 7, count 0 2006.173.08:20:39.53#ibcon#enter sib2, iclass 7, count 0 2006.173.08:20:39.53#ibcon#flushed, iclass 7, count 0 2006.173.08:20:39.53#ibcon#about to write, iclass 7, count 0 2006.173.08:20:39.53#ibcon#wrote, iclass 7, count 0 2006.173.08:20:39.53#ibcon#about to read 3, iclass 7, count 0 2006.173.08:20:39.57#ibcon#read 3, iclass 7, count 0 2006.173.08:20:39.57#ibcon#about to read 4, iclass 7, count 0 2006.173.08:20:39.57#ibcon#read 4, iclass 7, count 0 2006.173.08:20:39.57#ibcon#about to read 5, iclass 7, count 0 2006.173.08:20:39.57#ibcon#read 5, iclass 7, count 0 2006.173.08:20:39.57#ibcon#about to read 6, iclass 7, count 0 2006.173.08:20:39.57#ibcon#read 6, iclass 7, count 0 2006.173.08:20:39.57#ibcon#end of sib2, iclass 7, count 0 2006.173.08:20:39.57#ibcon#*after write, iclass 7, count 0 2006.173.08:20:39.57#ibcon#*before return 0, iclass 7, count 0 2006.173.08:20:39.57#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.08:20:39.57#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.08:20:39.57#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.08:20:39.57#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.08:20:39.57$vck44/va=5,4 2006.173.08:20:39.57#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.08:20:39.57#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.08:20:39.57#ibcon#ireg 11 cls_cnt 2 2006.173.08:20:39.57#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.08:20:39.63#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.08:20:39.63#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.08:20:39.63#ibcon#enter wrdev, iclass 11, count 2 2006.173.08:20:39.63#ibcon#first serial, iclass 11, count 2 2006.173.08:20:39.63#ibcon#enter sib2, iclass 11, count 2 2006.173.08:20:39.63#ibcon#flushed, iclass 11, count 2 2006.173.08:20:39.63#ibcon#about to write, iclass 11, count 2 2006.173.08:20:39.63#ibcon#wrote, iclass 11, count 2 2006.173.08:20:39.63#ibcon#about to read 3, iclass 11, count 2 2006.173.08:20:39.65#ibcon#read 3, iclass 11, count 2 2006.173.08:20:39.65#ibcon#about to read 4, iclass 11, count 2 2006.173.08:20:39.65#ibcon#read 4, iclass 11, count 2 2006.173.08:20:39.65#ibcon#about to read 5, iclass 11, count 2 2006.173.08:20:39.65#ibcon#read 5, iclass 11, count 2 2006.173.08:20:39.65#ibcon#about to read 6, iclass 11, count 2 2006.173.08:20:39.65#ibcon#read 6, iclass 11, count 2 2006.173.08:20:39.65#ibcon#end of sib2, iclass 11, count 2 2006.173.08:20:39.65#ibcon#*mode == 0, iclass 11, count 2 2006.173.08:20:39.65#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.08:20:39.65#ibcon#[25=AT05-04\r\n] 2006.173.08:20:39.65#ibcon#*before write, iclass 11, count 2 2006.173.08:20:39.65#ibcon#enter sib2, iclass 11, count 2 2006.173.08:20:39.65#ibcon#flushed, iclass 11, count 2 2006.173.08:20:39.65#ibcon#about to write, iclass 11, count 2 2006.173.08:20:39.65#ibcon#wrote, iclass 11, count 2 2006.173.08:20:39.65#ibcon#about to read 3, iclass 11, count 2 2006.173.08:20:39.68#ibcon#read 3, iclass 11, count 2 2006.173.08:20:39.68#ibcon#about to read 4, iclass 11, count 2 2006.173.08:20:39.68#ibcon#read 4, iclass 11, count 2 2006.173.08:20:39.68#ibcon#about to read 5, iclass 11, count 2 2006.173.08:20:39.68#ibcon#read 5, iclass 11, count 2 2006.173.08:20:39.68#ibcon#about to read 6, iclass 11, count 2 2006.173.08:20:39.68#ibcon#read 6, iclass 11, count 2 2006.173.08:20:39.68#ibcon#end of sib2, iclass 11, count 2 2006.173.08:20:39.68#ibcon#*after write, iclass 11, count 2 2006.173.08:20:39.68#ibcon#*before return 0, iclass 11, count 2 2006.173.08:20:39.68#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.08:20:39.68#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.08:20:39.68#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.08:20:39.68#ibcon#ireg 7 cls_cnt 0 2006.173.08:20:39.68#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.08:20:39.80#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.08:20:39.80#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.08:20:39.80#ibcon#enter wrdev, iclass 11, count 0 2006.173.08:20:39.80#ibcon#first serial, iclass 11, count 0 2006.173.08:20:39.80#ibcon#enter sib2, iclass 11, count 0 2006.173.08:20:39.80#ibcon#flushed, iclass 11, count 0 2006.173.08:20:39.80#ibcon#about to write, iclass 11, count 0 2006.173.08:20:39.80#ibcon#wrote, iclass 11, count 0 2006.173.08:20:39.80#ibcon#about to read 3, iclass 11, count 0 2006.173.08:20:39.82#ibcon#read 3, iclass 11, count 0 2006.173.08:20:39.82#ibcon#about to read 4, iclass 11, count 0 2006.173.08:20:39.82#ibcon#read 4, iclass 11, count 0 2006.173.08:20:39.82#ibcon#about to read 5, iclass 11, count 0 2006.173.08:20:39.82#ibcon#read 5, iclass 11, count 0 2006.173.08:20:39.82#ibcon#about to read 6, iclass 11, count 0 2006.173.08:20:39.82#ibcon#read 6, iclass 11, count 0 2006.173.08:20:39.82#ibcon#end of sib2, iclass 11, count 0 2006.173.08:20:39.82#ibcon#*mode == 0, iclass 11, count 0 2006.173.08:20:39.82#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.08:20:39.82#ibcon#[25=USB\r\n] 2006.173.08:20:39.82#ibcon#*before write, iclass 11, count 0 2006.173.08:20:39.82#ibcon#enter sib2, iclass 11, count 0 2006.173.08:20:39.82#ibcon#flushed, iclass 11, count 0 2006.173.08:20:39.82#ibcon#about to write, iclass 11, count 0 2006.173.08:20:39.82#ibcon#wrote, iclass 11, count 0 2006.173.08:20:39.82#ibcon#about to read 3, iclass 11, count 0 2006.173.08:20:39.85#ibcon#read 3, iclass 11, count 0 2006.173.08:20:39.85#ibcon#about to read 4, iclass 11, count 0 2006.173.08:20:39.85#ibcon#read 4, iclass 11, count 0 2006.173.08:20:39.85#ibcon#about to read 5, iclass 11, count 0 2006.173.08:20:39.85#ibcon#read 5, iclass 11, count 0 2006.173.08:20:39.85#ibcon#about to read 6, iclass 11, count 0 2006.173.08:20:39.85#ibcon#read 6, iclass 11, count 0 2006.173.08:20:39.85#ibcon#end of sib2, iclass 11, count 0 2006.173.08:20:39.85#ibcon#*after write, iclass 11, count 0 2006.173.08:20:39.85#ibcon#*before return 0, iclass 11, count 0 2006.173.08:20:39.85#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.08:20:39.85#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.08:20:39.85#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.08:20:39.85#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.08:20:39.85$vck44/valo=6,814.99 2006.173.08:20:39.85#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.08:20:39.85#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.08:20:39.85#ibcon#ireg 17 cls_cnt 0 2006.173.08:20:39.85#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.08:20:39.85#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.08:20:39.85#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.08:20:39.85#ibcon#enter wrdev, iclass 13, count 0 2006.173.08:20:39.85#ibcon#first serial, iclass 13, count 0 2006.173.08:20:39.85#ibcon#enter sib2, iclass 13, count 0 2006.173.08:20:39.85#ibcon#flushed, iclass 13, count 0 2006.173.08:20:39.85#ibcon#about to write, iclass 13, count 0 2006.173.08:20:39.85#ibcon#wrote, iclass 13, count 0 2006.173.08:20:39.85#ibcon#about to read 3, iclass 13, count 0 2006.173.08:20:39.87#ibcon#read 3, iclass 13, count 0 2006.173.08:20:39.87#ibcon#about to read 4, iclass 13, count 0 2006.173.08:20:39.87#ibcon#read 4, iclass 13, count 0 2006.173.08:20:39.87#ibcon#about to read 5, iclass 13, count 0 2006.173.08:20:39.87#ibcon#read 5, iclass 13, count 0 2006.173.08:20:39.87#ibcon#about to read 6, iclass 13, count 0 2006.173.08:20:39.87#ibcon#read 6, iclass 13, count 0 2006.173.08:20:39.87#ibcon#end of sib2, iclass 13, count 0 2006.173.08:20:39.87#ibcon#*mode == 0, iclass 13, count 0 2006.173.08:20:39.87#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.08:20:39.87#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.08:20:39.87#ibcon#*before write, iclass 13, count 0 2006.173.08:20:39.87#ibcon#enter sib2, iclass 13, count 0 2006.173.08:20:39.87#ibcon#flushed, iclass 13, count 0 2006.173.08:20:39.87#ibcon#about to write, iclass 13, count 0 2006.173.08:20:39.87#ibcon#wrote, iclass 13, count 0 2006.173.08:20:39.87#ibcon#about to read 3, iclass 13, count 0 2006.173.08:20:39.91#ibcon#read 3, iclass 13, count 0 2006.173.08:20:39.91#ibcon#about to read 4, iclass 13, count 0 2006.173.08:20:39.91#ibcon#read 4, iclass 13, count 0 2006.173.08:20:39.91#ibcon#about to read 5, iclass 13, count 0 2006.173.08:20:39.91#ibcon#read 5, iclass 13, count 0 2006.173.08:20:39.91#ibcon#about to read 6, iclass 13, count 0 2006.173.08:20:39.91#ibcon#read 6, iclass 13, count 0 2006.173.08:20:39.91#ibcon#end of sib2, iclass 13, count 0 2006.173.08:20:39.91#ibcon#*after write, iclass 13, count 0 2006.173.08:20:39.91#ibcon#*before return 0, iclass 13, count 0 2006.173.08:20:39.91#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.08:20:39.91#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.08:20:39.91#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.08:20:39.91#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.08:20:39.91$vck44/va=6,3 2006.173.08:20:39.91#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.08:20:39.91#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.08:20:39.91#ibcon#ireg 11 cls_cnt 2 2006.173.08:20:39.91#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.08:20:39.97#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.08:20:39.97#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.08:20:39.97#ibcon#enter wrdev, iclass 15, count 2 2006.173.08:20:39.97#ibcon#first serial, iclass 15, count 2 2006.173.08:20:39.97#ibcon#enter sib2, iclass 15, count 2 2006.173.08:20:39.97#ibcon#flushed, iclass 15, count 2 2006.173.08:20:39.97#ibcon#about to write, iclass 15, count 2 2006.173.08:20:39.97#ibcon#wrote, iclass 15, count 2 2006.173.08:20:39.97#ibcon#about to read 3, iclass 15, count 2 2006.173.08:20:39.99#ibcon#read 3, iclass 15, count 2 2006.173.08:20:39.99#ibcon#about to read 4, iclass 15, count 2 2006.173.08:20:39.99#ibcon#read 4, iclass 15, count 2 2006.173.08:20:39.99#ibcon#about to read 5, iclass 15, count 2 2006.173.08:20:39.99#ibcon#read 5, iclass 15, count 2 2006.173.08:20:39.99#ibcon#about to read 6, iclass 15, count 2 2006.173.08:20:39.99#ibcon#read 6, iclass 15, count 2 2006.173.08:20:39.99#ibcon#end of sib2, iclass 15, count 2 2006.173.08:20:39.99#ibcon#*mode == 0, iclass 15, count 2 2006.173.08:20:39.99#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.08:20:39.99#ibcon#[25=AT06-03\r\n] 2006.173.08:20:39.99#ibcon#*before write, iclass 15, count 2 2006.173.08:20:39.99#ibcon#enter sib2, iclass 15, count 2 2006.173.08:20:39.99#ibcon#flushed, iclass 15, count 2 2006.173.08:20:39.99#ibcon#about to write, iclass 15, count 2 2006.173.08:20:39.99#ibcon#wrote, iclass 15, count 2 2006.173.08:20:39.99#ibcon#about to read 3, iclass 15, count 2 2006.173.08:20:40.02#ibcon#read 3, iclass 15, count 2 2006.173.08:20:40.02#ibcon#about to read 4, iclass 15, count 2 2006.173.08:20:40.02#ibcon#read 4, iclass 15, count 2 2006.173.08:20:40.02#ibcon#about to read 5, iclass 15, count 2 2006.173.08:20:40.02#ibcon#read 5, iclass 15, count 2 2006.173.08:20:40.02#ibcon#about to read 6, iclass 15, count 2 2006.173.08:20:40.02#ibcon#read 6, iclass 15, count 2 2006.173.08:20:40.02#ibcon#end of sib2, iclass 15, count 2 2006.173.08:20:40.02#ibcon#*after write, iclass 15, count 2 2006.173.08:20:40.02#ibcon#*before return 0, iclass 15, count 2 2006.173.08:20:40.02#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.08:20:40.02#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.08:20:40.02#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.08:20:40.02#ibcon#ireg 7 cls_cnt 0 2006.173.08:20:40.02#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.08:20:40.14#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.08:20:40.14#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.08:20:40.14#ibcon#enter wrdev, iclass 15, count 0 2006.173.08:20:40.14#ibcon#first serial, iclass 15, count 0 2006.173.08:20:40.14#ibcon#enter sib2, iclass 15, count 0 2006.173.08:20:40.14#ibcon#flushed, iclass 15, count 0 2006.173.08:20:40.14#ibcon#about to write, iclass 15, count 0 2006.173.08:20:40.14#ibcon#wrote, iclass 15, count 0 2006.173.08:20:40.14#ibcon#about to read 3, iclass 15, count 0 2006.173.08:20:40.16#ibcon#read 3, iclass 15, count 0 2006.173.08:20:40.16#ibcon#about to read 4, iclass 15, count 0 2006.173.08:20:40.16#ibcon#read 4, iclass 15, count 0 2006.173.08:20:40.16#ibcon#about to read 5, iclass 15, count 0 2006.173.08:20:40.16#ibcon#read 5, iclass 15, count 0 2006.173.08:20:40.16#ibcon#about to read 6, iclass 15, count 0 2006.173.08:20:40.16#ibcon#read 6, iclass 15, count 0 2006.173.08:20:40.16#ibcon#end of sib2, iclass 15, count 0 2006.173.08:20:40.16#ibcon#*mode == 0, iclass 15, count 0 2006.173.08:20:40.16#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.08:20:40.16#ibcon#[25=USB\r\n] 2006.173.08:20:40.16#ibcon#*before write, iclass 15, count 0 2006.173.08:20:40.16#ibcon#enter sib2, iclass 15, count 0 2006.173.08:20:40.16#ibcon#flushed, iclass 15, count 0 2006.173.08:20:40.16#ibcon#about to write, iclass 15, count 0 2006.173.08:20:40.16#ibcon#wrote, iclass 15, count 0 2006.173.08:20:40.16#ibcon#about to read 3, iclass 15, count 0 2006.173.08:20:40.19#ibcon#read 3, iclass 15, count 0 2006.173.08:20:40.19#ibcon#about to read 4, iclass 15, count 0 2006.173.08:20:40.19#ibcon#read 4, iclass 15, count 0 2006.173.08:20:40.19#ibcon#about to read 5, iclass 15, count 0 2006.173.08:20:40.19#ibcon#read 5, iclass 15, count 0 2006.173.08:20:40.19#ibcon#about to read 6, iclass 15, count 0 2006.173.08:20:40.19#ibcon#read 6, iclass 15, count 0 2006.173.08:20:40.19#ibcon#end of sib2, iclass 15, count 0 2006.173.08:20:40.19#ibcon#*after write, iclass 15, count 0 2006.173.08:20:40.19#ibcon#*before return 0, iclass 15, count 0 2006.173.08:20:40.19#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.08:20:40.19#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.08:20:40.19#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.08:20:40.19#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.08:20:40.19$vck44/valo=7,864.99 2006.173.08:20:40.19#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.08:20:40.19#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.08:20:40.19#ibcon#ireg 17 cls_cnt 0 2006.173.08:20:40.19#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.08:20:40.19#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.08:20:40.19#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.08:20:40.19#ibcon#enter wrdev, iclass 17, count 0 2006.173.08:20:40.19#ibcon#first serial, iclass 17, count 0 2006.173.08:20:40.19#ibcon#enter sib2, iclass 17, count 0 2006.173.08:20:40.19#ibcon#flushed, iclass 17, count 0 2006.173.08:20:40.19#ibcon#about to write, iclass 17, count 0 2006.173.08:20:40.19#ibcon#wrote, iclass 17, count 0 2006.173.08:20:40.19#ibcon#about to read 3, iclass 17, count 0 2006.173.08:20:40.21#ibcon#read 3, iclass 17, count 0 2006.173.08:20:40.21#ibcon#about to read 4, iclass 17, count 0 2006.173.08:20:40.21#ibcon#read 4, iclass 17, count 0 2006.173.08:20:40.21#ibcon#about to read 5, iclass 17, count 0 2006.173.08:20:40.21#ibcon#read 5, iclass 17, count 0 2006.173.08:20:40.21#ibcon#about to read 6, iclass 17, count 0 2006.173.08:20:40.21#ibcon#read 6, iclass 17, count 0 2006.173.08:20:40.21#ibcon#end of sib2, iclass 17, count 0 2006.173.08:20:40.21#ibcon#*mode == 0, iclass 17, count 0 2006.173.08:20:40.21#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.08:20:40.21#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.08:20:40.21#ibcon#*before write, iclass 17, count 0 2006.173.08:20:40.21#ibcon#enter sib2, iclass 17, count 0 2006.173.08:20:40.21#ibcon#flushed, iclass 17, count 0 2006.173.08:20:40.21#ibcon#about to write, iclass 17, count 0 2006.173.08:20:40.21#ibcon#wrote, iclass 17, count 0 2006.173.08:20:40.21#ibcon#about to read 3, iclass 17, count 0 2006.173.08:20:40.25#ibcon#read 3, iclass 17, count 0 2006.173.08:20:40.25#ibcon#about to read 4, iclass 17, count 0 2006.173.08:20:40.25#ibcon#read 4, iclass 17, count 0 2006.173.08:20:40.25#ibcon#about to read 5, iclass 17, count 0 2006.173.08:20:40.25#ibcon#read 5, iclass 17, count 0 2006.173.08:20:40.25#ibcon#about to read 6, iclass 17, count 0 2006.173.08:20:40.25#ibcon#read 6, iclass 17, count 0 2006.173.08:20:40.25#ibcon#end of sib2, iclass 17, count 0 2006.173.08:20:40.25#ibcon#*after write, iclass 17, count 0 2006.173.08:20:40.25#ibcon#*before return 0, iclass 17, count 0 2006.173.08:20:40.25#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.08:20:40.25#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.08:20:40.25#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.08:20:40.25#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.08:20:40.25$vck44/va=7,4 2006.173.08:20:40.25#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.08:20:40.25#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.08:20:40.25#ibcon#ireg 11 cls_cnt 2 2006.173.08:20:40.25#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.08:20:40.31#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.08:20:40.31#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.08:20:40.31#ibcon#enter wrdev, iclass 19, count 2 2006.173.08:20:40.31#ibcon#first serial, iclass 19, count 2 2006.173.08:20:40.31#ibcon#enter sib2, iclass 19, count 2 2006.173.08:20:40.31#ibcon#flushed, iclass 19, count 2 2006.173.08:20:40.31#ibcon#about to write, iclass 19, count 2 2006.173.08:20:40.31#ibcon#wrote, iclass 19, count 2 2006.173.08:20:40.31#ibcon#about to read 3, iclass 19, count 2 2006.173.08:20:40.33#ibcon#read 3, iclass 19, count 2 2006.173.08:20:40.33#ibcon#about to read 4, iclass 19, count 2 2006.173.08:20:40.33#ibcon#read 4, iclass 19, count 2 2006.173.08:20:40.33#ibcon#about to read 5, iclass 19, count 2 2006.173.08:20:40.33#ibcon#read 5, iclass 19, count 2 2006.173.08:20:40.33#ibcon#about to read 6, iclass 19, count 2 2006.173.08:20:40.33#ibcon#read 6, iclass 19, count 2 2006.173.08:20:40.33#ibcon#end of sib2, iclass 19, count 2 2006.173.08:20:40.33#ibcon#*mode == 0, iclass 19, count 2 2006.173.08:20:40.33#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.08:20:40.33#ibcon#[25=AT07-04\r\n] 2006.173.08:20:40.33#ibcon#*before write, iclass 19, count 2 2006.173.08:20:40.33#ibcon#enter sib2, iclass 19, count 2 2006.173.08:20:40.33#ibcon#flushed, iclass 19, count 2 2006.173.08:20:40.33#ibcon#about to write, iclass 19, count 2 2006.173.08:20:40.33#ibcon#wrote, iclass 19, count 2 2006.173.08:20:40.33#ibcon#about to read 3, iclass 19, count 2 2006.173.08:20:40.36#ibcon#read 3, iclass 19, count 2 2006.173.08:20:40.36#ibcon#about to read 4, iclass 19, count 2 2006.173.08:20:40.36#ibcon#read 4, iclass 19, count 2 2006.173.08:20:40.36#ibcon#about to read 5, iclass 19, count 2 2006.173.08:20:40.36#ibcon#read 5, iclass 19, count 2 2006.173.08:20:40.36#ibcon#about to read 6, iclass 19, count 2 2006.173.08:20:40.36#ibcon#read 6, iclass 19, count 2 2006.173.08:20:40.36#ibcon#end of sib2, iclass 19, count 2 2006.173.08:20:40.36#ibcon#*after write, iclass 19, count 2 2006.173.08:20:40.36#ibcon#*before return 0, iclass 19, count 2 2006.173.08:20:40.36#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.08:20:40.36#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.08:20:40.36#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.08:20:40.36#ibcon#ireg 7 cls_cnt 0 2006.173.08:20:40.36#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.08:20:40.48#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.08:20:40.48#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.08:20:40.48#ibcon#enter wrdev, iclass 19, count 0 2006.173.08:20:40.48#ibcon#first serial, iclass 19, count 0 2006.173.08:20:40.48#ibcon#enter sib2, iclass 19, count 0 2006.173.08:20:40.48#ibcon#flushed, iclass 19, count 0 2006.173.08:20:40.48#ibcon#about to write, iclass 19, count 0 2006.173.08:20:40.48#ibcon#wrote, iclass 19, count 0 2006.173.08:20:40.48#ibcon#about to read 3, iclass 19, count 0 2006.173.08:20:40.50#ibcon#read 3, iclass 19, count 0 2006.173.08:20:40.50#ibcon#about to read 4, iclass 19, count 0 2006.173.08:20:40.50#ibcon#read 4, iclass 19, count 0 2006.173.08:20:40.50#ibcon#about to read 5, iclass 19, count 0 2006.173.08:20:40.50#ibcon#read 5, iclass 19, count 0 2006.173.08:20:40.50#ibcon#about to read 6, iclass 19, count 0 2006.173.08:20:40.50#ibcon#read 6, iclass 19, count 0 2006.173.08:20:40.50#ibcon#end of sib2, iclass 19, count 0 2006.173.08:20:40.50#ibcon#*mode == 0, iclass 19, count 0 2006.173.08:20:40.50#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.08:20:40.50#ibcon#[25=USB\r\n] 2006.173.08:20:40.50#ibcon#*before write, iclass 19, count 0 2006.173.08:20:40.50#ibcon#enter sib2, iclass 19, count 0 2006.173.08:20:40.50#ibcon#flushed, iclass 19, count 0 2006.173.08:20:40.50#ibcon#about to write, iclass 19, count 0 2006.173.08:20:40.50#ibcon#wrote, iclass 19, count 0 2006.173.08:20:40.50#ibcon#about to read 3, iclass 19, count 0 2006.173.08:20:40.53#ibcon#read 3, iclass 19, count 0 2006.173.08:20:40.53#ibcon#about to read 4, iclass 19, count 0 2006.173.08:20:40.53#ibcon#read 4, iclass 19, count 0 2006.173.08:20:40.53#ibcon#about to read 5, iclass 19, count 0 2006.173.08:20:40.53#ibcon#read 5, iclass 19, count 0 2006.173.08:20:40.53#ibcon#about to read 6, iclass 19, count 0 2006.173.08:20:40.53#ibcon#read 6, iclass 19, count 0 2006.173.08:20:40.53#ibcon#end of sib2, iclass 19, count 0 2006.173.08:20:40.53#ibcon#*after write, iclass 19, count 0 2006.173.08:20:40.53#ibcon#*before return 0, iclass 19, count 0 2006.173.08:20:40.53#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.08:20:40.53#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.08:20:40.53#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.08:20:40.53#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.08:20:40.53$vck44/valo=8,884.99 2006.173.08:20:40.53#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.08:20:40.53#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.08:20:40.53#ibcon#ireg 17 cls_cnt 0 2006.173.08:20:40.53#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.08:20:40.53#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.08:20:40.53#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.08:20:40.53#ibcon#enter wrdev, iclass 21, count 0 2006.173.08:20:40.53#ibcon#first serial, iclass 21, count 0 2006.173.08:20:40.53#ibcon#enter sib2, iclass 21, count 0 2006.173.08:20:40.53#ibcon#flushed, iclass 21, count 0 2006.173.08:20:40.53#ibcon#about to write, iclass 21, count 0 2006.173.08:20:40.53#ibcon#wrote, iclass 21, count 0 2006.173.08:20:40.53#ibcon#about to read 3, iclass 21, count 0 2006.173.08:20:40.55#ibcon#read 3, iclass 21, count 0 2006.173.08:20:40.55#ibcon#about to read 4, iclass 21, count 0 2006.173.08:20:40.55#ibcon#read 4, iclass 21, count 0 2006.173.08:20:40.55#ibcon#about to read 5, iclass 21, count 0 2006.173.08:20:40.55#ibcon#read 5, iclass 21, count 0 2006.173.08:20:40.55#ibcon#about to read 6, iclass 21, count 0 2006.173.08:20:40.55#ibcon#read 6, iclass 21, count 0 2006.173.08:20:40.55#ibcon#end of sib2, iclass 21, count 0 2006.173.08:20:40.55#ibcon#*mode == 0, iclass 21, count 0 2006.173.08:20:40.55#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.08:20:40.55#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.08:20:40.55#ibcon#*before write, iclass 21, count 0 2006.173.08:20:40.55#ibcon#enter sib2, iclass 21, count 0 2006.173.08:20:40.55#ibcon#flushed, iclass 21, count 0 2006.173.08:20:40.55#ibcon#about to write, iclass 21, count 0 2006.173.08:20:40.55#ibcon#wrote, iclass 21, count 0 2006.173.08:20:40.55#ibcon#about to read 3, iclass 21, count 0 2006.173.08:20:40.59#ibcon#read 3, iclass 21, count 0 2006.173.08:20:40.59#ibcon#about to read 4, iclass 21, count 0 2006.173.08:20:40.59#ibcon#read 4, iclass 21, count 0 2006.173.08:20:40.59#ibcon#about to read 5, iclass 21, count 0 2006.173.08:20:40.59#ibcon#read 5, iclass 21, count 0 2006.173.08:20:40.59#ibcon#about to read 6, iclass 21, count 0 2006.173.08:20:40.59#ibcon#read 6, iclass 21, count 0 2006.173.08:20:40.59#ibcon#end of sib2, iclass 21, count 0 2006.173.08:20:40.59#ibcon#*after write, iclass 21, count 0 2006.173.08:20:40.59#ibcon#*before return 0, iclass 21, count 0 2006.173.08:20:40.59#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.08:20:40.59#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.08:20:40.59#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.08:20:40.59#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.08:20:40.59$vck44/va=8,4 2006.173.08:20:40.59#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.08:20:40.59#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.08:20:40.59#ibcon#ireg 11 cls_cnt 2 2006.173.08:20:40.59#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.08:20:40.65#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.08:20:40.65#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.08:20:40.65#ibcon#enter wrdev, iclass 23, count 2 2006.173.08:20:40.65#ibcon#first serial, iclass 23, count 2 2006.173.08:20:40.65#ibcon#enter sib2, iclass 23, count 2 2006.173.08:20:40.65#ibcon#flushed, iclass 23, count 2 2006.173.08:20:40.65#ibcon#about to write, iclass 23, count 2 2006.173.08:20:40.65#ibcon#wrote, iclass 23, count 2 2006.173.08:20:40.65#ibcon#about to read 3, iclass 23, count 2 2006.173.08:20:40.67#ibcon#read 3, iclass 23, count 2 2006.173.08:20:40.67#ibcon#about to read 4, iclass 23, count 2 2006.173.08:20:40.67#ibcon#read 4, iclass 23, count 2 2006.173.08:20:40.67#ibcon#about to read 5, iclass 23, count 2 2006.173.08:20:40.67#ibcon#read 5, iclass 23, count 2 2006.173.08:20:40.67#ibcon#about to read 6, iclass 23, count 2 2006.173.08:20:40.67#ibcon#read 6, iclass 23, count 2 2006.173.08:20:40.67#ibcon#end of sib2, iclass 23, count 2 2006.173.08:20:40.67#ibcon#*mode == 0, iclass 23, count 2 2006.173.08:20:40.67#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.08:20:40.67#ibcon#[25=AT08-04\r\n] 2006.173.08:20:40.67#ibcon#*before write, iclass 23, count 2 2006.173.08:20:40.67#ibcon#enter sib2, iclass 23, count 2 2006.173.08:20:40.67#ibcon#flushed, iclass 23, count 2 2006.173.08:20:40.67#ibcon#about to write, iclass 23, count 2 2006.173.08:20:40.67#ibcon#wrote, iclass 23, count 2 2006.173.08:20:40.67#ibcon#about to read 3, iclass 23, count 2 2006.173.08:20:40.70#ibcon#read 3, iclass 23, count 2 2006.173.08:20:40.70#ibcon#about to read 4, iclass 23, count 2 2006.173.08:20:40.70#ibcon#read 4, iclass 23, count 2 2006.173.08:20:40.70#ibcon#about to read 5, iclass 23, count 2 2006.173.08:20:40.70#ibcon#read 5, iclass 23, count 2 2006.173.08:20:40.70#ibcon#about to read 6, iclass 23, count 2 2006.173.08:20:40.70#ibcon#read 6, iclass 23, count 2 2006.173.08:20:40.70#ibcon#end of sib2, iclass 23, count 2 2006.173.08:20:40.70#ibcon#*after write, iclass 23, count 2 2006.173.08:20:40.70#ibcon#*before return 0, iclass 23, count 2 2006.173.08:20:40.70#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.08:20:40.70#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.08:20:40.70#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.08:20:40.70#ibcon#ireg 7 cls_cnt 0 2006.173.08:20:40.70#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.08:20:40.82#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.08:20:40.82#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.08:20:40.82#ibcon#enter wrdev, iclass 23, count 0 2006.173.08:20:40.82#ibcon#first serial, iclass 23, count 0 2006.173.08:20:40.82#ibcon#enter sib2, iclass 23, count 0 2006.173.08:20:40.82#ibcon#flushed, iclass 23, count 0 2006.173.08:20:40.82#ibcon#about to write, iclass 23, count 0 2006.173.08:20:40.82#ibcon#wrote, iclass 23, count 0 2006.173.08:20:40.82#ibcon#about to read 3, iclass 23, count 0 2006.173.08:20:40.84#ibcon#read 3, iclass 23, count 0 2006.173.08:20:40.84#ibcon#about to read 4, iclass 23, count 0 2006.173.08:20:40.84#ibcon#read 4, iclass 23, count 0 2006.173.08:20:40.84#ibcon#about to read 5, iclass 23, count 0 2006.173.08:20:40.84#ibcon#read 5, iclass 23, count 0 2006.173.08:20:40.84#ibcon#about to read 6, iclass 23, count 0 2006.173.08:20:40.84#ibcon#read 6, iclass 23, count 0 2006.173.08:20:40.84#ibcon#end of sib2, iclass 23, count 0 2006.173.08:20:40.84#ibcon#*mode == 0, iclass 23, count 0 2006.173.08:20:40.84#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.08:20:40.84#ibcon#[25=USB\r\n] 2006.173.08:20:40.84#ibcon#*before write, iclass 23, count 0 2006.173.08:20:40.84#ibcon#enter sib2, iclass 23, count 0 2006.173.08:20:40.84#ibcon#flushed, iclass 23, count 0 2006.173.08:20:40.84#ibcon#about to write, iclass 23, count 0 2006.173.08:20:40.84#ibcon#wrote, iclass 23, count 0 2006.173.08:20:40.84#ibcon#about to read 3, iclass 23, count 0 2006.173.08:20:40.87#ibcon#read 3, iclass 23, count 0 2006.173.08:20:40.87#ibcon#about to read 4, iclass 23, count 0 2006.173.08:20:40.87#ibcon#read 4, iclass 23, count 0 2006.173.08:20:40.87#ibcon#about to read 5, iclass 23, count 0 2006.173.08:20:40.87#ibcon#read 5, iclass 23, count 0 2006.173.08:20:40.87#ibcon#about to read 6, iclass 23, count 0 2006.173.08:20:40.87#ibcon#read 6, iclass 23, count 0 2006.173.08:20:40.87#ibcon#end of sib2, iclass 23, count 0 2006.173.08:20:40.87#ibcon#*after write, iclass 23, count 0 2006.173.08:20:40.87#ibcon#*before return 0, iclass 23, count 0 2006.173.08:20:40.87#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.08:20:40.87#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.08:20:40.87#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.08:20:40.87#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.08:20:40.87$vck44/vblo=1,629.99 2006.173.08:20:40.87#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.08:20:40.87#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.08:20:40.87#ibcon#ireg 17 cls_cnt 0 2006.173.08:20:40.87#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.08:20:40.87#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.08:20:40.87#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.08:20:40.87#ibcon#enter wrdev, iclass 25, count 0 2006.173.08:20:40.87#ibcon#first serial, iclass 25, count 0 2006.173.08:20:40.87#ibcon#enter sib2, iclass 25, count 0 2006.173.08:20:40.87#ibcon#flushed, iclass 25, count 0 2006.173.08:20:40.87#ibcon#about to write, iclass 25, count 0 2006.173.08:20:40.87#ibcon#wrote, iclass 25, count 0 2006.173.08:20:40.87#ibcon#about to read 3, iclass 25, count 0 2006.173.08:20:40.89#ibcon#read 3, iclass 25, count 0 2006.173.08:20:40.89#ibcon#about to read 4, iclass 25, count 0 2006.173.08:20:40.89#ibcon#read 4, iclass 25, count 0 2006.173.08:20:40.89#ibcon#about to read 5, iclass 25, count 0 2006.173.08:20:40.89#ibcon#read 5, iclass 25, count 0 2006.173.08:20:40.89#ibcon#about to read 6, iclass 25, count 0 2006.173.08:20:40.89#ibcon#read 6, iclass 25, count 0 2006.173.08:20:40.89#ibcon#end of sib2, iclass 25, count 0 2006.173.08:20:40.89#ibcon#*mode == 0, iclass 25, count 0 2006.173.08:20:40.89#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.08:20:40.89#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.08:20:40.89#ibcon#*before write, iclass 25, count 0 2006.173.08:20:40.89#ibcon#enter sib2, iclass 25, count 0 2006.173.08:20:40.89#ibcon#flushed, iclass 25, count 0 2006.173.08:20:40.89#ibcon#about to write, iclass 25, count 0 2006.173.08:20:40.89#ibcon#wrote, iclass 25, count 0 2006.173.08:20:40.89#ibcon#about to read 3, iclass 25, count 0 2006.173.08:20:40.93#ibcon#read 3, iclass 25, count 0 2006.173.08:20:40.93#ibcon#about to read 4, iclass 25, count 0 2006.173.08:20:40.93#ibcon#read 4, iclass 25, count 0 2006.173.08:20:40.93#ibcon#about to read 5, iclass 25, count 0 2006.173.08:20:40.93#ibcon#read 5, iclass 25, count 0 2006.173.08:20:40.93#ibcon#about to read 6, iclass 25, count 0 2006.173.08:20:40.93#ibcon#read 6, iclass 25, count 0 2006.173.08:20:40.93#ibcon#end of sib2, iclass 25, count 0 2006.173.08:20:40.93#ibcon#*after write, iclass 25, count 0 2006.173.08:20:40.93#ibcon#*before return 0, iclass 25, count 0 2006.173.08:20:40.93#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.08:20:40.93#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.08:20:40.93#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.08:20:40.93#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.08:20:40.93$vck44/vb=1,4 2006.173.08:20:40.93#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.08:20:40.93#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.08:20:40.93#ibcon#ireg 11 cls_cnt 2 2006.173.08:20:40.93#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.08:20:40.93#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.08:20:40.93#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.08:20:40.93#ibcon#enter wrdev, iclass 27, count 2 2006.173.08:20:40.93#ibcon#first serial, iclass 27, count 2 2006.173.08:20:40.93#ibcon#enter sib2, iclass 27, count 2 2006.173.08:20:40.93#ibcon#flushed, iclass 27, count 2 2006.173.08:20:40.93#ibcon#about to write, iclass 27, count 2 2006.173.08:20:40.93#ibcon#wrote, iclass 27, count 2 2006.173.08:20:40.93#ibcon#about to read 3, iclass 27, count 2 2006.173.08:20:40.95#ibcon#read 3, iclass 27, count 2 2006.173.08:20:40.95#ibcon#about to read 4, iclass 27, count 2 2006.173.08:20:40.95#ibcon#read 4, iclass 27, count 2 2006.173.08:20:40.95#ibcon#about to read 5, iclass 27, count 2 2006.173.08:20:40.95#ibcon#read 5, iclass 27, count 2 2006.173.08:20:40.95#ibcon#about to read 6, iclass 27, count 2 2006.173.08:20:40.95#ibcon#read 6, iclass 27, count 2 2006.173.08:20:40.95#ibcon#end of sib2, iclass 27, count 2 2006.173.08:20:40.95#ibcon#*mode == 0, iclass 27, count 2 2006.173.08:20:40.95#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.08:20:40.95#ibcon#[27=AT01-04\r\n] 2006.173.08:20:40.95#ibcon#*before write, iclass 27, count 2 2006.173.08:20:40.95#ibcon#enter sib2, iclass 27, count 2 2006.173.08:20:40.95#ibcon#flushed, iclass 27, count 2 2006.173.08:20:40.95#ibcon#about to write, iclass 27, count 2 2006.173.08:20:40.95#ibcon#wrote, iclass 27, count 2 2006.173.08:20:40.95#ibcon#about to read 3, iclass 27, count 2 2006.173.08:20:40.98#ibcon#read 3, iclass 27, count 2 2006.173.08:20:40.98#ibcon#about to read 4, iclass 27, count 2 2006.173.08:20:40.98#ibcon#read 4, iclass 27, count 2 2006.173.08:20:40.98#ibcon#about to read 5, iclass 27, count 2 2006.173.08:20:40.98#ibcon#read 5, iclass 27, count 2 2006.173.08:20:40.98#ibcon#about to read 6, iclass 27, count 2 2006.173.08:20:40.98#ibcon#read 6, iclass 27, count 2 2006.173.08:20:40.98#ibcon#end of sib2, iclass 27, count 2 2006.173.08:20:40.98#ibcon#*after write, iclass 27, count 2 2006.173.08:20:40.98#ibcon#*before return 0, iclass 27, count 2 2006.173.08:20:40.98#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.08:20:40.98#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.08:20:40.98#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.08:20:40.98#ibcon#ireg 7 cls_cnt 0 2006.173.08:20:40.98#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.08:20:41.10#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.08:20:41.10#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.08:20:41.10#ibcon#enter wrdev, iclass 27, count 0 2006.173.08:20:41.10#ibcon#first serial, iclass 27, count 0 2006.173.08:20:41.10#ibcon#enter sib2, iclass 27, count 0 2006.173.08:20:41.10#ibcon#flushed, iclass 27, count 0 2006.173.08:20:41.10#ibcon#about to write, iclass 27, count 0 2006.173.08:20:41.10#ibcon#wrote, iclass 27, count 0 2006.173.08:20:41.10#ibcon#about to read 3, iclass 27, count 0 2006.173.08:20:41.12#ibcon#read 3, iclass 27, count 0 2006.173.08:20:41.12#ibcon#about to read 4, iclass 27, count 0 2006.173.08:20:41.12#ibcon#read 4, iclass 27, count 0 2006.173.08:20:41.12#ibcon#about to read 5, iclass 27, count 0 2006.173.08:20:41.12#ibcon#read 5, iclass 27, count 0 2006.173.08:20:41.12#ibcon#about to read 6, iclass 27, count 0 2006.173.08:20:41.12#ibcon#read 6, iclass 27, count 0 2006.173.08:20:41.12#ibcon#end of sib2, iclass 27, count 0 2006.173.08:20:41.12#ibcon#*mode == 0, iclass 27, count 0 2006.173.08:20:41.12#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.08:20:41.12#ibcon#[27=USB\r\n] 2006.173.08:20:41.12#ibcon#*before write, iclass 27, count 0 2006.173.08:20:41.12#ibcon#enter sib2, iclass 27, count 0 2006.173.08:20:41.12#ibcon#flushed, iclass 27, count 0 2006.173.08:20:41.12#ibcon#about to write, iclass 27, count 0 2006.173.08:20:41.12#ibcon#wrote, iclass 27, count 0 2006.173.08:20:41.12#ibcon#about to read 3, iclass 27, count 0 2006.173.08:20:41.15#ibcon#read 3, iclass 27, count 0 2006.173.08:20:41.15#ibcon#about to read 4, iclass 27, count 0 2006.173.08:20:41.15#ibcon#read 4, iclass 27, count 0 2006.173.08:20:41.15#ibcon#about to read 5, iclass 27, count 0 2006.173.08:20:41.15#ibcon#read 5, iclass 27, count 0 2006.173.08:20:41.15#ibcon#about to read 6, iclass 27, count 0 2006.173.08:20:41.15#ibcon#read 6, iclass 27, count 0 2006.173.08:20:41.15#ibcon#end of sib2, iclass 27, count 0 2006.173.08:20:41.15#ibcon#*after write, iclass 27, count 0 2006.173.08:20:41.15#ibcon#*before return 0, iclass 27, count 0 2006.173.08:20:41.15#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.08:20:41.15#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.08:20:41.15#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.08:20:41.15#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.08:20:41.15$vck44/vblo=2,634.99 2006.173.08:20:41.15#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.08:20:41.15#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.08:20:41.15#ibcon#ireg 17 cls_cnt 0 2006.173.08:20:41.15#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.08:20:41.15#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.08:20:41.15#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.08:20:41.15#ibcon#enter wrdev, iclass 29, count 0 2006.173.08:20:41.15#ibcon#first serial, iclass 29, count 0 2006.173.08:20:41.15#ibcon#enter sib2, iclass 29, count 0 2006.173.08:20:41.15#ibcon#flushed, iclass 29, count 0 2006.173.08:20:41.15#ibcon#about to write, iclass 29, count 0 2006.173.08:20:41.15#ibcon#wrote, iclass 29, count 0 2006.173.08:20:41.15#ibcon#about to read 3, iclass 29, count 0 2006.173.08:20:41.17#ibcon#read 3, iclass 29, count 0 2006.173.08:20:41.17#ibcon#about to read 4, iclass 29, count 0 2006.173.08:20:41.17#ibcon#read 4, iclass 29, count 0 2006.173.08:20:41.17#ibcon#about to read 5, iclass 29, count 0 2006.173.08:20:41.17#ibcon#read 5, iclass 29, count 0 2006.173.08:20:41.17#ibcon#about to read 6, iclass 29, count 0 2006.173.08:20:41.17#ibcon#read 6, iclass 29, count 0 2006.173.08:20:41.17#ibcon#end of sib2, iclass 29, count 0 2006.173.08:20:41.17#ibcon#*mode == 0, iclass 29, count 0 2006.173.08:20:41.17#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.08:20:41.17#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.08:20:41.17#ibcon#*before write, iclass 29, count 0 2006.173.08:20:41.17#ibcon#enter sib2, iclass 29, count 0 2006.173.08:20:41.17#ibcon#flushed, iclass 29, count 0 2006.173.08:20:41.17#ibcon#about to write, iclass 29, count 0 2006.173.08:20:41.17#ibcon#wrote, iclass 29, count 0 2006.173.08:20:41.17#ibcon#about to read 3, iclass 29, count 0 2006.173.08:20:41.21#ibcon#read 3, iclass 29, count 0 2006.173.08:20:41.21#ibcon#about to read 4, iclass 29, count 0 2006.173.08:20:41.21#ibcon#read 4, iclass 29, count 0 2006.173.08:20:41.21#ibcon#about to read 5, iclass 29, count 0 2006.173.08:20:41.21#ibcon#read 5, iclass 29, count 0 2006.173.08:20:41.21#ibcon#about to read 6, iclass 29, count 0 2006.173.08:20:41.21#ibcon#read 6, iclass 29, count 0 2006.173.08:20:41.21#ibcon#end of sib2, iclass 29, count 0 2006.173.08:20:41.21#ibcon#*after write, iclass 29, count 0 2006.173.08:20:41.21#ibcon#*before return 0, iclass 29, count 0 2006.173.08:20:41.21#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.08:20:41.21#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.08:20:41.21#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.08:20:41.21#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.08:20:41.21$vck44/vb=2,4 2006.173.08:20:41.21#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.08:20:41.21#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.08:20:41.21#ibcon#ireg 11 cls_cnt 2 2006.173.08:20:41.21#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.08:20:41.27#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.08:20:41.27#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.08:20:41.27#ibcon#enter wrdev, iclass 31, count 2 2006.173.08:20:41.27#ibcon#first serial, iclass 31, count 2 2006.173.08:20:41.27#ibcon#enter sib2, iclass 31, count 2 2006.173.08:20:41.27#ibcon#flushed, iclass 31, count 2 2006.173.08:20:41.27#ibcon#about to write, iclass 31, count 2 2006.173.08:20:41.27#ibcon#wrote, iclass 31, count 2 2006.173.08:20:41.27#ibcon#about to read 3, iclass 31, count 2 2006.173.08:20:41.29#ibcon#read 3, iclass 31, count 2 2006.173.08:20:41.29#ibcon#about to read 4, iclass 31, count 2 2006.173.08:20:41.29#ibcon#read 4, iclass 31, count 2 2006.173.08:20:41.29#ibcon#about to read 5, iclass 31, count 2 2006.173.08:20:41.29#ibcon#read 5, iclass 31, count 2 2006.173.08:20:41.29#ibcon#about to read 6, iclass 31, count 2 2006.173.08:20:41.29#ibcon#read 6, iclass 31, count 2 2006.173.08:20:41.29#ibcon#end of sib2, iclass 31, count 2 2006.173.08:20:41.29#ibcon#*mode == 0, iclass 31, count 2 2006.173.08:20:41.29#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.08:20:41.29#ibcon#[27=AT02-04\r\n] 2006.173.08:20:41.29#ibcon#*before write, iclass 31, count 2 2006.173.08:20:41.29#ibcon#enter sib2, iclass 31, count 2 2006.173.08:20:41.29#ibcon#flushed, iclass 31, count 2 2006.173.08:20:41.29#ibcon#about to write, iclass 31, count 2 2006.173.08:20:41.29#ibcon#wrote, iclass 31, count 2 2006.173.08:20:41.29#ibcon#about to read 3, iclass 31, count 2 2006.173.08:20:41.32#ibcon#read 3, iclass 31, count 2 2006.173.08:20:41.32#ibcon#about to read 4, iclass 31, count 2 2006.173.08:20:41.32#ibcon#read 4, iclass 31, count 2 2006.173.08:20:41.32#ibcon#about to read 5, iclass 31, count 2 2006.173.08:20:41.32#ibcon#read 5, iclass 31, count 2 2006.173.08:20:41.32#ibcon#about to read 6, iclass 31, count 2 2006.173.08:20:41.32#ibcon#read 6, iclass 31, count 2 2006.173.08:20:41.32#ibcon#end of sib2, iclass 31, count 2 2006.173.08:20:41.32#ibcon#*after write, iclass 31, count 2 2006.173.08:20:41.32#ibcon#*before return 0, iclass 31, count 2 2006.173.08:20:41.32#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.08:20:41.32#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.08:20:41.32#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.08:20:41.32#ibcon#ireg 7 cls_cnt 0 2006.173.08:20:41.32#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.08:20:41.44#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.08:20:41.44#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.08:20:41.44#ibcon#enter wrdev, iclass 31, count 0 2006.173.08:20:41.44#ibcon#first serial, iclass 31, count 0 2006.173.08:20:41.44#ibcon#enter sib2, iclass 31, count 0 2006.173.08:20:41.44#ibcon#flushed, iclass 31, count 0 2006.173.08:20:41.44#ibcon#about to write, iclass 31, count 0 2006.173.08:20:41.44#ibcon#wrote, iclass 31, count 0 2006.173.08:20:41.44#ibcon#about to read 3, iclass 31, count 0 2006.173.08:20:41.46#ibcon#read 3, iclass 31, count 0 2006.173.08:20:41.46#ibcon#about to read 4, iclass 31, count 0 2006.173.08:20:41.46#ibcon#read 4, iclass 31, count 0 2006.173.08:20:41.46#ibcon#about to read 5, iclass 31, count 0 2006.173.08:20:41.46#ibcon#read 5, iclass 31, count 0 2006.173.08:20:41.46#ibcon#about to read 6, iclass 31, count 0 2006.173.08:20:41.46#ibcon#read 6, iclass 31, count 0 2006.173.08:20:41.46#ibcon#end of sib2, iclass 31, count 0 2006.173.08:20:41.46#ibcon#*mode == 0, iclass 31, count 0 2006.173.08:20:41.46#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.08:20:41.46#ibcon#[27=USB\r\n] 2006.173.08:20:41.46#ibcon#*before write, iclass 31, count 0 2006.173.08:20:41.46#ibcon#enter sib2, iclass 31, count 0 2006.173.08:20:41.46#ibcon#flushed, iclass 31, count 0 2006.173.08:20:41.46#ibcon#about to write, iclass 31, count 0 2006.173.08:20:41.46#ibcon#wrote, iclass 31, count 0 2006.173.08:20:41.46#ibcon#about to read 3, iclass 31, count 0 2006.173.08:20:41.49#ibcon#read 3, iclass 31, count 0 2006.173.08:20:41.49#ibcon#about to read 4, iclass 31, count 0 2006.173.08:20:41.49#ibcon#read 4, iclass 31, count 0 2006.173.08:20:41.49#ibcon#about to read 5, iclass 31, count 0 2006.173.08:20:41.49#ibcon#read 5, iclass 31, count 0 2006.173.08:20:41.49#ibcon#about to read 6, iclass 31, count 0 2006.173.08:20:41.49#ibcon#read 6, iclass 31, count 0 2006.173.08:20:41.49#ibcon#end of sib2, iclass 31, count 0 2006.173.08:20:41.49#ibcon#*after write, iclass 31, count 0 2006.173.08:20:41.49#ibcon#*before return 0, iclass 31, count 0 2006.173.08:20:41.49#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.08:20:41.49#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.08:20:41.49#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.08:20:41.49#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.08:20:41.49$vck44/vblo=3,649.99 2006.173.08:20:41.49#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.08:20:41.49#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.08:20:41.49#ibcon#ireg 17 cls_cnt 0 2006.173.08:20:41.49#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.08:20:41.49#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.08:20:41.49#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.08:20:41.49#ibcon#enter wrdev, iclass 33, count 0 2006.173.08:20:41.49#ibcon#first serial, iclass 33, count 0 2006.173.08:20:41.49#ibcon#enter sib2, iclass 33, count 0 2006.173.08:20:41.49#ibcon#flushed, iclass 33, count 0 2006.173.08:20:41.49#ibcon#about to write, iclass 33, count 0 2006.173.08:20:41.49#ibcon#wrote, iclass 33, count 0 2006.173.08:20:41.49#ibcon#about to read 3, iclass 33, count 0 2006.173.08:20:41.51#ibcon#read 3, iclass 33, count 0 2006.173.08:20:41.51#ibcon#about to read 4, iclass 33, count 0 2006.173.08:20:41.51#ibcon#read 4, iclass 33, count 0 2006.173.08:20:41.51#ibcon#about to read 5, iclass 33, count 0 2006.173.08:20:41.51#ibcon#read 5, iclass 33, count 0 2006.173.08:20:41.51#ibcon#about to read 6, iclass 33, count 0 2006.173.08:20:41.51#ibcon#read 6, iclass 33, count 0 2006.173.08:20:41.51#ibcon#end of sib2, iclass 33, count 0 2006.173.08:20:41.51#ibcon#*mode == 0, iclass 33, count 0 2006.173.08:20:41.51#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.08:20:41.51#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.08:20:41.51#ibcon#*before write, iclass 33, count 0 2006.173.08:20:41.51#ibcon#enter sib2, iclass 33, count 0 2006.173.08:20:41.51#ibcon#flushed, iclass 33, count 0 2006.173.08:20:41.51#ibcon#about to write, iclass 33, count 0 2006.173.08:20:41.51#ibcon#wrote, iclass 33, count 0 2006.173.08:20:41.51#ibcon#about to read 3, iclass 33, count 0 2006.173.08:20:41.55#ibcon#read 3, iclass 33, count 0 2006.173.08:20:41.55#ibcon#about to read 4, iclass 33, count 0 2006.173.08:20:41.55#ibcon#read 4, iclass 33, count 0 2006.173.08:20:41.55#ibcon#about to read 5, iclass 33, count 0 2006.173.08:20:41.55#ibcon#read 5, iclass 33, count 0 2006.173.08:20:41.55#ibcon#about to read 6, iclass 33, count 0 2006.173.08:20:41.55#ibcon#read 6, iclass 33, count 0 2006.173.08:20:41.55#ibcon#end of sib2, iclass 33, count 0 2006.173.08:20:41.55#ibcon#*after write, iclass 33, count 0 2006.173.08:20:41.55#ibcon#*before return 0, iclass 33, count 0 2006.173.08:20:41.55#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.08:20:41.55#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.08:20:41.55#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.08:20:41.55#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.08:20:41.55$vck44/vb=3,4 2006.173.08:20:41.55#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.08:20:41.55#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.08:20:41.55#ibcon#ireg 11 cls_cnt 2 2006.173.08:20:41.55#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.08:20:41.61#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.08:20:41.61#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.08:20:41.61#ibcon#enter wrdev, iclass 35, count 2 2006.173.08:20:41.61#ibcon#first serial, iclass 35, count 2 2006.173.08:20:41.61#ibcon#enter sib2, iclass 35, count 2 2006.173.08:20:41.61#ibcon#flushed, iclass 35, count 2 2006.173.08:20:41.61#ibcon#about to write, iclass 35, count 2 2006.173.08:20:41.61#ibcon#wrote, iclass 35, count 2 2006.173.08:20:41.61#ibcon#about to read 3, iclass 35, count 2 2006.173.08:20:41.63#ibcon#read 3, iclass 35, count 2 2006.173.08:20:41.63#ibcon#about to read 4, iclass 35, count 2 2006.173.08:20:41.63#ibcon#read 4, iclass 35, count 2 2006.173.08:20:41.63#ibcon#about to read 5, iclass 35, count 2 2006.173.08:20:41.63#ibcon#read 5, iclass 35, count 2 2006.173.08:20:41.63#ibcon#about to read 6, iclass 35, count 2 2006.173.08:20:41.63#ibcon#read 6, iclass 35, count 2 2006.173.08:20:41.63#ibcon#end of sib2, iclass 35, count 2 2006.173.08:20:41.63#ibcon#*mode == 0, iclass 35, count 2 2006.173.08:20:41.63#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.08:20:41.63#ibcon#[27=AT03-04\r\n] 2006.173.08:20:41.63#ibcon#*before write, iclass 35, count 2 2006.173.08:20:41.63#ibcon#enter sib2, iclass 35, count 2 2006.173.08:20:41.63#ibcon#flushed, iclass 35, count 2 2006.173.08:20:41.63#ibcon#about to write, iclass 35, count 2 2006.173.08:20:41.63#ibcon#wrote, iclass 35, count 2 2006.173.08:20:41.63#ibcon#about to read 3, iclass 35, count 2 2006.173.08:20:41.66#ibcon#read 3, iclass 35, count 2 2006.173.08:20:41.66#ibcon#about to read 4, iclass 35, count 2 2006.173.08:20:41.66#ibcon#read 4, iclass 35, count 2 2006.173.08:20:41.66#ibcon#about to read 5, iclass 35, count 2 2006.173.08:20:41.66#ibcon#read 5, iclass 35, count 2 2006.173.08:20:41.66#ibcon#about to read 6, iclass 35, count 2 2006.173.08:20:41.66#ibcon#read 6, iclass 35, count 2 2006.173.08:20:41.66#ibcon#end of sib2, iclass 35, count 2 2006.173.08:20:41.66#ibcon#*after write, iclass 35, count 2 2006.173.08:20:41.66#ibcon#*before return 0, iclass 35, count 2 2006.173.08:20:41.66#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.08:20:41.66#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.08:20:41.66#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.08:20:41.66#ibcon#ireg 7 cls_cnt 0 2006.173.08:20:41.66#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.08:20:41.78#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.08:20:41.78#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.08:20:41.78#ibcon#enter wrdev, iclass 35, count 0 2006.173.08:20:41.78#ibcon#first serial, iclass 35, count 0 2006.173.08:20:41.78#ibcon#enter sib2, iclass 35, count 0 2006.173.08:20:41.78#ibcon#flushed, iclass 35, count 0 2006.173.08:20:41.78#ibcon#about to write, iclass 35, count 0 2006.173.08:20:41.78#ibcon#wrote, iclass 35, count 0 2006.173.08:20:41.78#ibcon#about to read 3, iclass 35, count 0 2006.173.08:20:41.80#ibcon#read 3, iclass 35, count 0 2006.173.08:20:41.80#ibcon#about to read 4, iclass 35, count 0 2006.173.08:20:41.80#ibcon#read 4, iclass 35, count 0 2006.173.08:20:41.80#ibcon#about to read 5, iclass 35, count 0 2006.173.08:20:41.80#ibcon#read 5, iclass 35, count 0 2006.173.08:20:41.80#ibcon#about to read 6, iclass 35, count 0 2006.173.08:20:41.80#ibcon#read 6, iclass 35, count 0 2006.173.08:20:41.80#ibcon#end of sib2, iclass 35, count 0 2006.173.08:20:41.80#ibcon#*mode == 0, iclass 35, count 0 2006.173.08:20:41.80#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.08:20:41.80#ibcon#[27=USB\r\n] 2006.173.08:20:41.80#ibcon#*before write, iclass 35, count 0 2006.173.08:20:41.80#ibcon#enter sib2, iclass 35, count 0 2006.173.08:20:41.80#ibcon#flushed, iclass 35, count 0 2006.173.08:20:41.80#ibcon#about to write, iclass 35, count 0 2006.173.08:20:41.80#ibcon#wrote, iclass 35, count 0 2006.173.08:20:41.80#ibcon#about to read 3, iclass 35, count 0 2006.173.08:20:41.83#ibcon#read 3, iclass 35, count 0 2006.173.08:20:41.83#ibcon#about to read 4, iclass 35, count 0 2006.173.08:20:41.83#ibcon#read 4, iclass 35, count 0 2006.173.08:20:41.83#ibcon#about to read 5, iclass 35, count 0 2006.173.08:20:41.83#ibcon#read 5, iclass 35, count 0 2006.173.08:20:41.83#ibcon#about to read 6, iclass 35, count 0 2006.173.08:20:41.83#ibcon#read 6, iclass 35, count 0 2006.173.08:20:41.83#ibcon#end of sib2, iclass 35, count 0 2006.173.08:20:41.83#ibcon#*after write, iclass 35, count 0 2006.173.08:20:41.83#ibcon#*before return 0, iclass 35, count 0 2006.173.08:20:41.83#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.08:20:41.83#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.08:20:41.83#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.08:20:41.83#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.08:20:41.83$vck44/vblo=4,679.99 2006.173.08:20:41.83#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.08:20:41.83#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.08:20:41.83#ibcon#ireg 17 cls_cnt 0 2006.173.08:20:41.83#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.08:20:41.83#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.08:20:41.83#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.08:20:41.83#ibcon#enter wrdev, iclass 37, count 0 2006.173.08:20:41.83#ibcon#first serial, iclass 37, count 0 2006.173.08:20:41.83#ibcon#enter sib2, iclass 37, count 0 2006.173.08:20:41.83#ibcon#flushed, iclass 37, count 0 2006.173.08:20:41.83#ibcon#about to write, iclass 37, count 0 2006.173.08:20:41.83#ibcon#wrote, iclass 37, count 0 2006.173.08:20:41.83#ibcon#about to read 3, iclass 37, count 0 2006.173.08:20:41.85#ibcon#read 3, iclass 37, count 0 2006.173.08:20:41.85#ibcon#about to read 4, iclass 37, count 0 2006.173.08:20:41.85#ibcon#read 4, iclass 37, count 0 2006.173.08:20:41.85#ibcon#about to read 5, iclass 37, count 0 2006.173.08:20:41.85#ibcon#read 5, iclass 37, count 0 2006.173.08:20:41.85#ibcon#about to read 6, iclass 37, count 0 2006.173.08:20:41.85#ibcon#read 6, iclass 37, count 0 2006.173.08:20:41.85#ibcon#end of sib2, iclass 37, count 0 2006.173.08:20:41.85#ibcon#*mode == 0, iclass 37, count 0 2006.173.08:20:41.85#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.08:20:41.85#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.08:20:41.85#ibcon#*before write, iclass 37, count 0 2006.173.08:20:41.85#ibcon#enter sib2, iclass 37, count 0 2006.173.08:20:41.85#ibcon#flushed, iclass 37, count 0 2006.173.08:20:41.85#ibcon#about to write, iclass 37, count 0 2006.173.08:20:41.85#ibcon#wrote, iclass 37, count 0 2006.173.08:20:41.85#ibcon#about to read 3, iclass 37, count 0 2006.173.08:20:41.89#ibcon#read 3, iclass 37, count 0 2006.173.08:20:41.89#ibcon#about to read 4, iclass 37, count 0 2006.173.08:20:41.89#ibcon#read 4, iclass 37, count 0 2006.173.08:20:41.89#ibcon#about to read 5, iclass 37, count 0 2006.173.08:20:41.89#ibcon#read 5, iclass 37, count 0 2006.173.08:20:41.89#ibcon#about to read 6, iclass 37, count 0 2006.173.08:20:41.89#ibcon#read 6, iclass 37, count 0 2006.173.08:20:41.89#ibcon#end of sib2, iclass 37, count 0 2006.173.08:20:41.89#ibcon#*after write, iclass 37, count 0 2006.173.08:20:41.89#ibcon#*before return 0, iclass 37, count 0 2006.173.08:20:41.89#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.08:20:41.89#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.08:20:41.89#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.08:20:41.89#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.08:20:41.89$vck44/vb=4,4 2006.173.08:20:41.89#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.08:20:41.89#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.08:20:41.89#ibcon#ireg 11 cls_cnt 2 2006.173.08:20:41.89#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.08:20:41.95#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.08:20:41.95#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.08:20:41.95#ibcon#enter wrdev, iclass 39, count 2 2006.173.08:20:41.95#ibcon#first serial, iclass 39, count 2 2006.173.08:20:41.95#ibcon#enter sib2, iclass 39, count 2 2006.173.08:20:41.95#ibcon#flushed, iclass 39, count 2 2006.173.08:20:41.95#ibcon#about to write, iclass 39, count 2 2006.173.08:20:41.95#ibcon#wrote, iclass 39, count 2 2006.173.08:20:41.95#ibcon#about to read 3, iclass 39, count 2 2006.173.08:20:41.97#ibcon#read 3, iclass 39, count 2 2006.173.08:20:41.97#ibcon#about to read 4, iclass 39, count 2 2006.173.08:20:41.97#ibcon#read 4, iclass 39, count 2 2006.173.08:20:41.97#ibcon#about to read 5, iclass 39, count 2 2006.173.08:20:41.97#ibcon#read 5, iclass 39, count 2 2006.173.08:20:41.97#ibcon#about to read 6, iclass 39, count 2 2006.173.08:20:41.97#ibcon#read 6, iclass 39, count 2 2006.173.08:20:41.97#ibcon#end of sib2, iclass 39, count 2 2006.173.08:20:41.97#ibcon#*mode == 0, iclass 39, count 2 2006.173.08:20:41.97#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.08:20:41.97#ibcon#[27=AT04-04\r\n] 2006.173.08:20:41.97#ibcon#*before write, iclass 39, count 2 2006.173.08:20:41.97#ibcon#enter sib2, iclass 39, count 2 2006.173.08:20:41.97#ibcon#flushed, iclass 39, count 2 2006.173.08:20:41.97#ibcon#about to write, iclass 39, count 2 2006.173.08:20:41.97#ibcon#wrote, iclass 39, count 2 2006.173.08:20:41.97#ibcon#about to read 3, iclass 39, count 2 2006.173.08:20:42.00#ibcon#read 3, iclass 39, count 2 2006.173.08:20:42.00#ibcon#about to read 4, iclass 39, count 2 2006.173.08:20:42.00#ibcon#read 4, iclass 39, count 2 2006.173.08:20:42.00#ibcon#about to read 5, iclass 39, count 2 2006.173.08:20:42.00#ibcon#read 5, iclass 39, count 2 2006.173.08:20:42.00#ibcon#about to read 6, iclass 39, count 2 2006.173.08:20:42.00#ibcon#read 6, iclass 39, count 2 2006.173.08:20:42.00#ibcon#end of sib2, iclass 39, count 2 2006.173.08:20:42.00#ibcon#*after write, iclass 39, count 2 2006.173.08:20:42.00#ibcon#*before return 0, iclass 39, count 2 2006.173.08:20:42.00#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.08:20:42.00#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.08:20:42.00#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.08:20:42.00#ibcon#ireg 7 cls_cnt 0 2006.173.08:20:42.00#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.08:20:42.12#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.08:20:42.12#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.08:20:42.12#ibcon#enter wrdev, iclass 39, count 0 2006.173.08:20:42.12#ibcon#first serial, iclass 39, count 0 2006.173.08:20:42.12#ibcon#enter sib2, iclass 39, count 0 2006.173.08:20:42.12#ibcon#flushed, iclass 39, count 0 2006.173.08:20:42.12#ibcon#about to write, iclass 39, count 0 2006.173.08:20:42.12#ibcon#wrote, iclass 39, count 0 2006.173.08:20:42.12#ibcon#about to read 3, iclass 39, count 0 2006.173.08:20:42.14#ibcon#read 3, iclass 39, count 0 2006.173.08:20:42.14#ibcon#about to read 4, iclass 39, count 0 2006.173.08:20:42.14#ibcon#read 4, iclass 39, count 0 2006.173.08:20:42.14#ibcon#about to read 5, iclass 39, count 0 2006.173.08:20:42.14#ibcon#read 5, iclass 39, count 0 2006.173.08:20:42.14#ibcon#about to read 6, iclass 39, count 0 2006.173.08:20:42.14#ibcon#read 6, iclass 39, count 0 2006.173.08:20:42.14#ibcon#end of sib2, iclass 39, count 0 2006.173.08:20:42.14#ibcon#*mode == 0, iclass 39, count 0 2006.173.08:20:42.14#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.08:20:42.14#ibcon#[27=USB\r\n] 2006.173.08:20:42.14#ibcon#*before write, iclass 39, count 0 2006.173.08:20:42.14#ibcon#enter sib2, iclass 39, count 0 2006.173.08:20:42.14#ibcon#flushed, iclass 39, count 0 2006.173.08:20:42.14#ibcon#about to write, iclass 39, count 0 2006.173.08:20:42.14#ibcon#wrote, iclass 39, count 0 2006.173.08:20:42.14#ibcon#about to read 3, iclass 39, count 0 2006.173.08:20:42.17#ibcon#read 3, iclass 39, count 0 2006.173.08:20:42.17#ibcon#about to read 4, iclass 39, count 0 2006.173.08:20:42.17#ibcon#read 4, iclass 39, count 0 2006.173.08:20:42.17#ibcon#about to read 5, iclass 39, count 0 2006.173.08:20:42.17#ibcon#read 5, iclass 39, count 0 2006.173.08:20:42.17#ibcon#about to read 6, iclass 39, count 0 2006.173.08:20:42.17#ibcon#read 6, iclass 39, count 0 2006.173.08:20:42.17#ibcon#end of sib2, iclass 39, count 0 2006.173.08:20:42.17#ibcon#*after write, iclass 39, count 0 2006.173.08:20:42.17#ibcon#*before return 0, iclass 39, count 0 2006.173.08:20:42.17#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.08:20:42.17#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.08:20:42.17#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.08:20:42.17#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.08:20:42.17$vck44/vblo=5,709.99 2006.173.08:20:42.17#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.08:20:42.17#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.08:20:42.17#ibcon#ireg 17 cls_cnt 0 2006.173.08:20:42.17#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.08:20:42.17#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.08:20:42.17#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.08:20:42.17#ibcon#enter wrdev, iclass 3, count 0 2006.173.08:20:42.17#ibcon#first serial, iclass 3, count 0 2006.173.08:20:42.17#ibcon#enter sib2, iclass 3, count 0 2006.173.08:20:42.17#ibcon#flushed, iclass 3, count 0 2006.173.08:20:42.17#ibcon#about to write, iclass 3, count 0 2006.173.08:20:42.17#ibcon#wrote, iclass 3, count 0 2006.173.08:20:42.17#ibcon#about to read 3, iclass 3, count 0 2006.173.08:20:42.19#ibcon#read 3, iclass 3, count 0 2006.173.08:20:42.19#ibcon#about to read 4, iclass 3, count 0 2006.173.08:20:42.19#ibcon#read 4, iclass 3, count 0 2006.173.08:20:42.19#ibcon#about to read 5, iclass 3, count 0 2006.173.08:20:42.19#ibcon#read 5, iclass 3, count 0 2006.173.08:20:42.19#ibcon#about to read 6, iclass 3, count 0 2006.173.08:20:42.19#ibcon#read 6, iclass 3, count 0 2006.173.08:20:42.19#ibcon#end of sib2, iclass 3, count 0 2006.173.08:20:42.19#ibcon#*mode == 0, iclass 3, count 0 2006.173.08:20:42.19#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.08:20:42.19#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.08:20:42.19#ibcon#*before write, iclass 3, count 0 2006.173.08:20:42.19#ibcon#enter sib2, iclass 3, count 0 2006.173.08:20:42.19#ibcon#flushed, iclass 3, count 0 2006.173.08:20:42.19#ibcon#about to write, iclass 3, count 0 2006.173.08:20:42.19#ibcon#wrote, iclass 3, count 0 2006.173.08:20:42.19#ibcon#about to read 3, iclass 3, count 0 2006.173.08:20:42.23#ibcon#read 3, iclass 3, count 0 2006.173.08:20:42.23#ibcon#about to read 4, iclass 3, count 0 2006.173.08:20:42.23#ibcon#read 4, iclass 3, count 0 2006.173.08:20:42.23#ibcon#about to read 5, iclass 3, count 0 2006.173.08:20:42.23#ibcon#read 5, iclass 3, count 0 2006.173.08:20:42.23#ibcon#about to read 6, iclass 3, count 0 2006.173.08:20:42.23#ibcon#read 6, iclass 3, count 0 2006.173.08:20:42.23#ibcon#end of sib2, iclass 3, count 0 2006.173.08:20:42.23#ibcon#*after write, iclass 3, count 0 2006.173.08:20:42.23#ibcon#*before return 0, iclass 3, count 0 2006.173.08:20:42.23#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.08:20:42.23#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.08:20:42.23#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.08:20:42.23#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.08:20:42.23$vck44/vb=5,4 2006.173.08:20:42.23#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.08:20:42.23#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.08:20:42.23#ibcon#ireg 11 cls_cnt 2 2006.173.08:20:42.23#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.08:20:42.29#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.08:20:42.29#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.08:20:42.29#ibcon#enter wrdev, iclass 5, count 2 2006.173.08:20:42.29#ibcon#first serial, iclass 5, count 2 2006.173.08:20:42.29#ibcon#enter sib2, iclass 5, count 2 2006.173.08:20:42.29#ibcon#flushed, iclass 5, count 2 2006.173.08:20:42.29#ibcon#about to write, iclass 5, count 2 2006.173.08:20:42.29#ibcon#wrote, iclass 5, count 2 2006.173.08:20:42.29#ibcon#about to read 3, iclass 5, count 2 2006.173.08:20:42.31#ibcon#read 3, iclass 5, count 2 2006.173.08:20:42.31#ibcon#about to read 4, iclass 5, count 2 2006.173.08:20:42.31#ibcon#read 4, iclass 5, count 2 2006.173.08:20:42.31#ibcon#about to read 5, iclass 5, count 2 2006.173.08:20:42.31#ibcon#read 5, iclass 5, count 2 2006.173.08:20:42.31#ibcon#about to read 6, iclass 5, count 2 2006.173.08:20:42.31#ibcon#read 6, iclass 5, count 2 2006.173.08:20:42.31#ibcon#end of sib2, iclass 5, count 2 2006.173.08:20:42.31#ibcon#*mode == 0, iclass 5, count 2 2006.173.08:20:42.31#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.08:20:42.31#ibcon#[27=AT05-04\r\n] 2006.173.08:20:42.31#ibcon#*before write, iclass 5, count 2 2006.173.08:20:42.31#ibcon#enter sib2, iclass 5, count 2 2006.173.08:20:42.31#ibcon#flushed, iclass 5, count 2 2006.173.08:20:42.31#ibcon#about to write, iclass 5, count 2 2006.173.08:20:42.31#ibcon#wrote, iclass 5, count 2 2006.173.08:20:42.31#ibcon#about to read 3, iclass 5, count 2 2006.173.08:20:42.34#ibcon#read 3, iclass 5, count 2 2006.173.08:20:42.34#ibcon#about to read 4, iclass 5, count 2 2006.173.08:20:42.34#ibcon#read 4, iclass 5, count 2 2006.173.08:20:42.34#ibcon#about to read 5, iclass 5, count 2 2006.173.08:20:42.34#ibcon#read 5, iclass 5, count 2 2006.173.08:20:42.34#ibcon#about to read 6, iclass 5, count 2 2006.173.08:20:42.34#ibcon#read 6, iclass 5, count 2 2006.173.08:20:42.34#ibcon#end of sib2, iclass 5, count 2 2006.173.08:20:42.34#ibcon#*after write, iclass 5, count 2 2006.173.08:20:42.34#ibcon#*before return 0, iclass 5, count 2 2006.173.08:20:42.34#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.08:20:42.34#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.08:20:42.34#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.08:20:42.34#ibcon#ireg 7 cls_cnt 0 2006.173.08:20:42.34#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.08:20:42.46#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.08:20:42.46#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.08:20:42.46#ibcon#enter wrdev, iclass 5, count 0 2006.173.08:20:42.46#ibcon#first serial, iclass 5, count 0 2006.173.08:20:42.46#ibcon#enter sib2, iclass 5, count 0 2006.173.08:20:42.46#ibcon#flushed, iclass 5, count 0 2006.173.08:20:42.46#ibcon#about to write, iclass 5, count 0 2006.173.08:20:42.46#ibcon#wrote, iclass 5, count 0 2006.173.08:20:42.46#ibcon#about to read 3, iclass 5, count 0 2006.173.08:20:42.48#ibcon#read 3, iclass 5, count 0 2006.173.08:20:42.48#ibcon#about to read 4, iclass 5, count 0 2006.173.08:20:42.48#ibcon#read 4, iclass 5, count 0 2006.173.08:20:42.48#ibcon#about to read 5, iclass 5, count 0 2006.173.08:20:42.48#ibcon#read 5, iclass 5, count 0 2006.173.08:20:42.48#ibcon#about to read 6, iclass 5, count 0 2006.173.08:20:42.48#ibcon#read 6, iclass 5, count 0 2006.173.08:20:42.48#ibcon#end of sib2, iclass 5, count 0 2006.173.08:20:42.48#ibcon#*mode == 0, iclass 5, count 0 2006.173.08:20:42.48#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.08:20:42.48#ibcon#[27=USB\r\n] 2006.173.08:20:42.48#ibcon#*before write, iclass 5, count 0 2006.173.08:20:42.48#ibcon#enter sib2, iclass 5, count 0 2006.173.08:20:42.48#ibcon#flushed, iclass 5, count 0 2006.173.08:20:42.48#ibcon#about to write, iclass 5, count 0 2006.173.08:20:42.48#ibcon#wrote, iclass 5, count 0 2006.173.08:20:42.48#ibcon#about to read 3, iclass 5, count 0 2006.173.08:20:42.51#ibcon#read 3, iclass 5, count 0 2006.173.08:20:42.51#ibcon#about to read 4, iclass 5, count 0 2006.173.08:20:42.51#ibcon#read 4, iclass 5, count 0 2006.173.08:20:42.51#ibcon#about to read 5, iclass 5, count 0 2006.173.08:20:42.51#ibcon#read 5, iclass 5, count 0 2006.173.08:20:42.51#ibcon#about to read 6, iclass 5, count 0 2006.173.08:20:42.51#ibcon#read 6, iclass 5, count 0 2006.173.08:20:42.51#ibcon#end of sib2, iclass 5, count 0 2006.173.08:20:42.51#ibcon#*after write, iclass 5, count 0 2006.173.08:20:42.51#ibcon#*before return 0, iclass 5, count 0 2006.173.08:20:42.51#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.08:20:42.51#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.08:20:42.51#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.08:20:42.51#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.08:20:42.51$vck44/vblo=6,719.99 2006.173.08:20:42.51#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.08:20:42.51#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.08:20:42.51#ibcon#ireg 17 cls_cnt 0 2006.173.08:20:42.51#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.08:20:42.51#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.08:20:42.51#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.08:20:42.51#ibcon#enter wrdev, iclass 7, count 0 2006.173.08:20:42.51#ibcon#first serial, iclass 7, count 0 2006.173.08:20:42.51#ibcon#enter sib2, iclass 7, count 0 2006.173.08:20:42.51#ibcon#flushed, iclass 7, count 0 2006.173.08:20:42.51#ibcon#about to write, iclass 7, count 0 2006.173.08:20:42.51#ibcon#wrote, iclass 7, count 0 2006.173.08:20:42.51#ibcon#about to read 3, iclass 7, count 0 2006.173.08:20:42.53#ibcon#read 3, iclass 7, count 0 2006.173.08:20:42.53#ibcon#about to read 4, iclass 7, count 0 2006.173.08:20:42.53#ibcon#read 4, iclass 7, count 0 2006.173.08:20:42.53#ibcon#about to read 5, iclass 7, count 0 2006.173.08:20:42.53#ibcon#read 5, iclass 7, count 0 2006.173.08:20:42.53#ibcon#about to read 6, iclass 7, count 0 2006.173.08:20:42.53#ibcon#read 6, iclass 7, count 0 2006.173.08:20:42.53#ibcon#end of sib2, iclass 7, count 0 2006.173.08:20:42.53#ibcon#*mode == 0, iclass 7, count 0 2006.173.08:20:42.53#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.08:20:42.53#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.08:20:42.53#ibcon#*before write, iclass 7, count 0 2006.173.08:20:42.53#ibcon#enter sib2, iclass 7, count 0 2006.173.08:20:42.53#ibcon#flushed, iclass 7, count 0 2006.173.08:20:42.53#ibcon#about to write, iclass 7, count 0 2006.173.08:20:42.53#ibcon#wrote, iclass 7, count 0 2006.173.08:20:42.53#ibcon#about to read 3, iclass 7, count 0 2006.173.08:20:42.57#ibcon#read 3, iclass 7, count 0 2006.173.08:20:42.57#ibcon#about to read 4, iclass 7, count 0 2006.173.08:20:42.57#ibcon#read 4, iclass 7, count 0 2006.173.08:20:42.57#ibcon#about to read 5, iclass 7, count 0 2006.173.08:20:42.57#ibcon#read 5, iclass 7, count 0 2006.173.08:20:42.57#ibcon#about to read 6, iclass 7, count 0 2006.173.08:20:42.57#ibcon#read 6, iclass 7, count 0 2006.173.08:20:42.57#ibcon#end of sib2, iclass 7, count 0 2006.173.08:20:42.57#ibcon#*after write, iclass 7, count 0 2006.173.08:20:42.57#ibcon#*before return 0, iclass 7, count 0 2006.173.08:20:42.57#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.08:20:42.57#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.08:20:42.57#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.08:20:42.57#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.08:20:42.57$vck44/vb=6,4 2006.173.08:20:42.57#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.08:20:42.57#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.08:20:42.57#ibcon#ireg 11 cls_cnt 2 2006.173.08:20:42.57#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.08:20:42.63#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.08:20:42.63#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.08:20:42.63#ibcon#enter wrdev, iclass 11, count 2 2006.173.08:20:42.63#ibcon#first serial, iclass 11, count 2 2006.173.08:20:42.63#ibcon#enter sib2, iclass 11, count 2 2006.173.08:20:42.63#ibcon#flushed, iclass 11, count 2 2006.173.08:20:42.63#ibcon#about to write, iclass 11, count 2 2006.173.08:20:42.63#ibcon#wrote, iclass 11, count 2 2006.173.08:20:42.63#ibcon#about to read 3, iclass 11, count 2 2006.173.08:20:42.65#ibcon#read 3, iclass 11, count 2 2006.173.08:20:42.65#ibcon#about to read 4, iclass 11, count 2 2006.173.08:20:42.65#ibcon#read 4, iclass 11, count 2 2006.173.08:20:42.65#ibcon#about to read 5, iclass 11, count 2 2006.173.08:20:42.65#ibcon#read 5, iclass 11, count 2 2006.173.08:20:42.65#ibcon#about to read 6, iclass 11, count 2 2006.173.08:20:42.65#ibcon#read 6, iclass 11, count 2 2006.173.08:20:42.65#ibcon#end of sib2, iclass 11, count 2 2006.173.08:20:42.65#ibcon#*mode == 0, iclass 11, count 2 2006.173.08:20:42.65#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.08:20:42.65#ibcon#[27=AT06-04\r\n] 2006.173.08:20:42.65#ibcon#*before write, iclass 11, count 2 2006.173.08:20:42.65#ibcon#enter sib2, iclass 11, count 2 2006.173.08:20:42.65#ibcon#flushed, iclass 11, count 2 2006.173.08:20:42.65#ibcon#about to write, iclass 11, count 2 2006.173.08:20:42.65#ibcon#wrote, iclass 11, count 2 2006.173.08:20:42.65#ibcon#about to read 3, iclass 11, count 2 2006.173.08:20:42.68#ibcon#read 3, iclass 11, count 2 2006.173.08:20:42.68#ibcon#about to read 4, iclass 11, count 2 2006.173.08:20:42.68#ibcon#read 4, iclass 11, count 2 2006.173.08:20:42.68#ibcon#about to read 5, iclass 11, count 2 2006.173.08:20:42.68#ibcon#read 5, iclass 11, count 2 2006.173.08:20:42.68#ibcon#about to read 6, iclass 11, count 2 2006.173.08:20:42.68#ibcon#read 6, iclass 11, count 2 2006.173.08:20:42.68#ibcon#end of sib2, iclass 11, count 2 2006.173.08:20:42.68#ibcon#*after write, iclass 11, count 2 2006.173.08:20:42.68#ibcon#*before return 0, iclass 11, count 2 2006.173.08:20:42.68#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.08:20:42.68#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.08:20:42.68#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.08:20:42.68#ibcon#ireg 7 cls_cnt 0 2006.173.08:20:42.68#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.08:20:42.80#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.08:20:42.80#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.08:20:42.80#ibcon#enter wrdev, iclass 11, count 0 2006.173.08:20:42.80#ibcon#first serial, iclass 11, count 0 2006.173.08:20:42.80#ibcon#enter sib2, iclass 11, count 0 2006.173.08:20:42.80#ibcon#flushed, iclass 11, count 0 2006.173.08:20:42.80#ibcon#about to write, iclass 11, count 0 2006.173.08:20:42.80#ibcon#wrote, iclass 11, count 0 2006.173.08:20:42.80#ibcon#about to read 3, iclass 11, count 0 2006.173.08:20:42.82#ibcon#read 3, iclass 11, count 0 2006.173.08:20:42.82#ibcon#about to read 4, iclass 11, count 0 2006.173.08:20:42.82#ibcon#read 4, iclass 11, count 0 2006.173.08:20:42.82#ibcon#about to read 5, iclass 11, count 0 2006.173.08:20:42.82#ibcon#read 5, iclass 11, count 0 2006.173.08:20:42.82#ibcon#about to read 6, iclass 11, count 0 2006.173.08:20:42.82#ibcon#read 6, iclass 11, count 0 2006.173.08:20:42.82#ibcon#end of sib2, iclass 11, count 0 2006.173.08:20:42.82#ibcon#*mode == 0, iclass 11, count 0 2006.173.08:20:42.82#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.08:20:42.82#ibcon#[27=USB\r\n] 2006.173.08:20:42.82#ibcon#*before write, iclass 11, count 0 2006.173.08:20:42.82#ibcon#enter sib2, iclass 11, count 0 2006.173.08:20:42.82#ibcon#flushed, iclass 11, count 0 2006.173.08:20:42.82#ibcon#about to write, iclass 11, count 0 2006.173.08:20:42.82#ibcon#wrote, iclass 11, count 0 2006.173.08:20:42.82#ibcon#about to read 3, iclass 11, count 0 2006.173.08:20:42.85#ibcon#read 3, iclass 11, count 0 2006.173.08:20:42.85#ibcon#about to read 4, iclass 11, count 0 2006.173.08:20:42.85#ibcon#read 4, iclass 11, count 0 2006.173.08:20:42.85#ibcon#about to read 5, iclass 11, count 0 2006.173.08:20:42.85#ibcon#read 5, iclass 11, count 0 2006.173.08:20:42.85#ibcon#about to read 6, iclass 11, count 0 2006.173.08:20:42.85#ibcon#read 6, iclass 11, count 0 2006.173.08:20:42.85#ibcon#end of sib2, iclass 11, count 0 2006.173.08:20:42.85#ibcon#*after write, iclass 11, count 0 2006.173.08:20:42.85#ibcon#*before return 0, iclass 11, count 0 2006.173.08:20:42.85#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.08:20:42.85#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.08:20:42.85#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.08:20:42.85#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.08:20:42.85$vck44/vblo=7,734.99 2006.173.08:20:42.85#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.08:20:42.85#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.08:20:42.85#ibcon#ireg 17 cls_cnt 0 2006.173.08:20:42.85#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.08:20:42.85#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.08:20:42.85#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.08:20:42.85#ibcon#enter wrdev, iclass 13, count 0 2006.173.08:20:42.85#ibcon#first serial, iclass 13, count 0 2006.173.08:20:42.85#ibcon#enter sib2, iclass 13, count 0 2006.173.08:20:42.85#ibcon#flushed, iclass 13, count 0 2006.173.08:20:42.85#ibcon#about to write, iclass 13, count 0 2006.173.08:20:42.85#ibcon#wrote, iclass 13, count 0 2006.173.08:20:42.85#ibcon#about to read 3, iclass 13, count 0 2006.173.08:20:42.87#ibcon#read 3, iclass 13, count 0 2006.173.08:20:42.87#ibcon#about to read 4, iclass 13, count 0 2006.173.08:20:42.87#ibcon#read 4, iclass 13, count 0 2006.173.08:20:42.87#ibcon#about to read 5, iclass 13, count 0 2006.173.08:20:42.87#ibcon#read 5, iclass 13, count 0 2006.173.08:20:42.87#ibcon#about to read 6, iclass 13, count 0 2006.173.08:20:42.87#ibcon#read 6, iclass 13, count 0 2006.173.08:20:42.87#ibcon#end of sib2, iclass 13, count 0 2006.173.08:20:42.87#ibcon#*mode == 0, iclass 13, count 0 2006.173.08:20:42.87#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.08:20:42.87#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.08:20:42.87#ibcon#*before write, iclass 13, count 0 2006.173.08:20:42.87#ibcon#enter sib2, iclass 13, count 0 2006.173.08:20:42.87#ibcon#flushed, iclass 13, count 0 2006.173.08:20:42.87#ibcon#about to write, iclass 13, count 0 2006.173.08:20:42.87#ibcon#wrote, iclass 13, count 0 2006.173.08:20:42.87#ibcon#about to read 3, iclass 13, count 0 2006.173.08:20:42.91#ibcon#read 3, iclass 13, count 0 2006.173.08:20:42.91#ibcon#about to read 4, iclass 13, count 0 2006.173.08:20:42.91#ibcon#read 4, iclass 13, count 0 2006.173.08:20:42.91#ibcon#about to read 5, iclass 13, count 0 2006.173.08:20:42.91#ibcon#read 5, iclass 13, count 0 2006.173.08:20:42.91#ibcon#about to read 6, iclass 13, count 0 2006.173.08:20:42.91#ibcon#read 6, iclass 13, count 0 2006.173.08:20:42.91#ibcon#end of sib2, iclass 13, count 0 2006.173.08:20:42.91#ibcon#*after write, iclass 13, count 0 2006.173.08:20:42.91#ibcon#*before return 0, iclass 13, count 0 2006.173.08:20:42.91#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.08:20:42.91#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.08:20:42.91#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.08:20:42.91#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.08:20:42.91$vck44/vb=7,4 2006.173.08:20:42.91#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.08:20:42.91#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.08:20:42.91#ibcon#ireg 11 cls_cnt 2 2006.173.08:20:42.91#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.08:20:42.97#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.08:20:42.97#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.08:20:42.97#ibcon#enter wrdev, iclass 15, count 2 2006.173.08:20:42.97#ibcon#first serial, iclass 15, count 2 2006.173.08:20:42.97#ibcon#enter sib2, iclass 15, count 2 2006.173.08:20:42.97#ibcon#flushed, iclass 15, count 2 2006.173.08:20:42.97#ibcon#about to write, iclass 15, count 2 2006.173.08:20:42.97#ibcon#wrote, iclass 15, count 2 2006.173.08:20:42.97#ibcon#about to read 3, iclass 15, count 2 2006.173.08:20:42.99#ibcon#read 3, iclass 15, count 2 2006.173.08:20:42.99#ibcon#about to read 4, iclass 15, count 2 2006.173.08:20:42.99#ibcon#read 4, iclass 15, count 2 2006.173.08:20:42.99#ibcon#about to read 5, iclass 15, count 2 2006.173.08:20:42.99#ibcon#read 5, iclass 15, count 2 2006.173.08:20:42.99#ibcon#about to read 6, iclass 15, count 2 2006.173.08:20:42.99#ibcon#read 6, iclass 15, count 2 2006.173.08:20:42.99#ibcon#end of sib2, iclass 15, count 2 2006.173.08:20:42.99#ibcon#*mode == 0, iclass 15, count 2 2006.173.08:20:42.99#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.08:20:42.99#ibcon#[27=AT07-04\r\n] 2006.173.08:20:42.99#ibcon#*before write, iclass 15, count 2 2006.173.08:20:42.99#ibcon#enter sib2, iclass 15, count 2 2006.173.08:20:42.99#ibcon#flushed, iclass 15, count 2 2006.173.08:20:42.99#ibcon#about to write, iclass 15, count 2 2006.173.08:20:42.99#ibcon#wrote, iclass 15, count 2 2006.173.08:20:42.99#ibcon#about to read 3, iclass 15, count 2 2006.173.08:20:43.02#ibcon#read 3, iclass 15, count 2 2006.173.08:20:43.02#ibcon#about to read 4, iclass 15, count 2 2006.173.08:20:43.02#ibcon#read 4, iclass 15, count 2 2006.173.08:20:43.02#ibcon#about to read 5, iclass 15, count 2 2006.173.08:20:43.02#ibcon#read 5, iclass 15, count 2 2006.173.08:20:43.02#ibcon#about to read 6, iclass 15, count 2 2006.173.08:20:43.02#ibcon#read 6, iclass 15, count 2 2006.173.08:20:43.02#ibcon#end of sib2, iclass 15, count 2 2006.173.08:20:43.02#ibcon#*after write, iclass 15, count 2 2006.173.08:20:43.02#ibcon#*before return 0, iclass 15, count 2 2006.173.08:20:43.02#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.08:20:43.02#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.08:20:43.02#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.08:20:43.02#ibcon#ireg 7 cls_cnt 0 2006.173.08:20:43.02#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.08:20:43.14#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.08:20:43.14#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.08:20:43.14#ibcon#enter wrdev, iclass 15, count 0 2006.173.08:20:43.14#ibcon#first serial, iclass 15, count 0 2006.173.08:20:43.14#ibcon#enter sib2, iclass 15, count 0 2006.173.08:20:43.14#ibcon#flushed, iclass 15, count 0 2006.173.08:20:43.14#ibcon#about to write, iclass 15, count 0 2006.173.08:20:43.14#ibcon#wrote, iclass 15, count 0 2006.173.08:20:43.14#ibcon#about to read 3, iclass 15, count 0 2006.173.08:20:43.16#ibcon#read 3, iclass 15, count 0 2006.173.08:20:43.16#ibcon#about to read 4, iclass 15, count 0 2006.173.08:20:43.16#ibcon#read 4, iclass 15, count 0 2006.173.08:20:43.16#ibcon#about to read 5, iclass 15, count 0 2006.173.08:20:43.16#ibcon#read 5, iclass 15, count 0 2006.173.08:20:43.16#ibcon#about to read 6, iclass 15, count 0 2006.173.08:20:43.16#ibcon#read 6, iclass 15, count 0 2006.173.08:20:43.16#ibcon#end of sib2, iclass 15, count 0 2006.173.08:20:43.16#ibcon#*mode == 0, iclass 15, count 0 2006.173.08:20:43.16#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.08:20:43.16#ibcon#[27=USB\r\n] 2006.173.08:20:43.16#ibcon#*before write, iclass 15, count 0 2006.173.08:20:43.16#ibcon#enter sib2, iclass 15, count 0 2006.173.08:20:43.16#ibcon#flushed, iclass 15, count 0 2006.173.08:20:43.16#ibcon#about to write, iclass 15, count 0 2006.173.08:20:43.16#ibcon#wrote, iclass 15, count 0 2006.173.08:20:43.16#ibcon#about to read 3, iclass 15, count 0 2006.173.08:20:43.19#ibcon#read 3, iclass 15, count 0 2006.173.08:20:43.19#ibcon#about to read 4, iclass 15, count 0 2006.173.08:20:43.19#ibcon#read 4, iclass 15, count 0 2006.173.08:20:43.19#ibcon#about to read 5, iclass 15, count 0 2006.173.08:20:43.19#ibcon#read 5, iclass 15, count 0 2006.173.08:20:43.19#ibcon#about to read 6, iclass 15, count 0 2006.173.08:20:43.19#ibcon#read 6, iclass 15, count 0 2006.173.08:20:43.19#ibcon#end of sib2, iclass 15, count 0 2006.173.08:20:43.19#ibcon#*after write, iclass 15, count 0 2006.173.08:20:43.19#ibcon#*before return 0, iclass 15, count 0 2006.173.08:20:43.19#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.08:20:43.19#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.08:20:43.19#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.08:20:43.19#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.08:20:43.19$vck44/vblo=8,744.99 2006.173.08:20:43.19#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.08:20:43.19#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.08:20:43.19#ibcon#ireg 17 cls_cnt 0 2006.173.08:20:43.19#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.08:20:43.19#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.08:20:43.19#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.08:20:43.19#ibcon#enter wrdev, iclass 17, count 0 2006.173.08:20:43.19#ibcon#first serial, iclass 17, count 0 2006.173.08:20:43.19#ibcon#enter sib2, iclass 17, count 0 2006.173.08:20:43.19#ibcon#flushed, iclass 17, count 0 2006.173.08:20:43.19#ibcon#about to write, iclass 17, count 0 2006.173.08:20:43.19#ibcon#wrote, iclass 17, count 0 2006.173.08:20:43.19#ibcon#about to read 3, iclass 17, count 0 2006.173.08:20:43.21#ibcon#read 3, iclass 17, count 0 2006.173.08:20:43.21#ibcon#about to read 4, iclass 17, count 0 2006.173.08:20:43.21#ibcon#read 4, iclass 17, count 0 2006.173.08:20:43.21#ibcon#about to read 5, iclass 17, count 0 2006.173.08:20:43.21#ibcon#read 5, iclass 17, count 0 2006.173.08:20:43.21#ibcon#about to read 6, iclass 17, count 0 2006.173.08:20:43.21#ibcon#read 6, iclass 17, count 0 2006.173.08:20:43.21#ibcon#end of sib2, iclass 17, count 0 2006.173.08:20:43.21#ibcon#*mode == 0, iclass 17, count 0 2006.173.08:20:43.21#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.08:20:43.21#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.08:20:43.21#ibcon#*before write, iclass 17, count 0 2006.173.08:20:43.21#ibcon#enter sib2, iclass 17, count 0 2006.173.08:20:43.21#ibcon#flushed, iclass 17, count 0 2006.173.08:20:43.21#ibcon#about to write, iclass 17, count 0 2006.173.08:20:43.21#ibcon#wrote, iclass 17, count 0 2006.173.08:20:43.21#ibcon#about to read 3, iclass 17, count 0 2006.173.08:20:43.25#ibcon#read 3, iclass 17, count 0 2006.173.08:20:43.25#ibcon#about to read 4, iclass 17, count 0 2006.173.08:20:43.25#ibcon#read 4, iclass 17, count 0 2006.173.08:20:43.25#ibcon#about to read 5, iclass 17, count 0 2006.173.08:20:43.25#ibcon#read 5, iclass 17, count 0 2006.173.08:20:43.25#ibcon#about to read 6, iclass 17, count 0 2006.173.08:20:43.25#ibcon#read 6, iclass 17, count 0 2006.173.08:20:43.25#ibcon#end of sib2, iclass 17, count 0 2006.173.08:20:43.25#ibcon#*after write, iclass 17, count 0 2006.173.08:20:43.25#ibcon#*before return 0, iclass 17, count 0 2006.173.08:20:43.25#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.08:20:43.25#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.08:20:43.25#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.08:20:43.25#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.08:20:43.25$vck44/vb=8,4 2006.173.08:20:43.25#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.08:20:43.25#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.08:20:43.25#ibcon#ireg 11 cls_cnt 2 2006.173.08:20:43.25#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.08:20:43.31#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.08:20:43.31#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.08:20:43.31#ibcon#enter wrdev, iclass 19, count 2 2006.173.08:20:43.31#ibcon#first serial, iclass 19, count 2 2006.173.08:20:43.31#ibcon#enter sib2, iclass 19, count 2 2006.173.08:20:43.31#ibcon#flushed, iclass 19, count 2 2006.173.08:20:43.31#ibcon#about to write, iclass 19, count 2 2006.173.08:20:43.31#ibcon#wrote, iclass 19, count 2 2006.173.08:20:43.31#ibcon#about to read 3, iclass 19, count 2 2006.173.08:20:43.33#ibcon#read 3, iclass 19, count 2 2006.173.08:20:43.33#ibcon#about to read 4, iclass 19, count 2 2006.173.08:20:43.33#ibcon#read 4, iclass 19, count 2 2006.173.08:20:43.33#ibcon#about to read 5, iclass 19, count 2 2006.173.08:20:43.33#ibcon#read 5, iclass 19, count 2 2006.173.08:20:43.33#ibcon#about to read 6, iclass 19, count 2 2006.173.08:20:43.33#ibcon#read 6, iclass 19, count 2 2006.173.08:20:43.33#ibcon#end of sib2, iclass 19, count 2 2006.173.08:20:43.33#ibcon#*mode == 0, iclass 19, count 2 2006.173.08:20:43.33#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.08:20:43.33#ibcon#[27=AT08-04\r\n] 2006.173.08:20:43.33#ibcon#*before write, iclass 19, count 2 2006.173.08:20:43.33#ibcon#enter sib2, iclass 19, count 2 2006.173.08:20:43.33#ibcon#flushed, iclass 19, count 2 2006.173.08:20:43.33#ibcon#about to write, iclass 19, count 2 2006.173.08:20:43.33#ibcon#wrote, iclass 19, count 2 2006.173.08:20:43.33#ibcon#about to read 3, iclass 19, count 2 2006.173.08:20:43.36#ibcon#read 3, iclass 19, count 2 2006.173.08:20:43.36#ibcon#about to read 4, iclass 19, count 2 2006.173.08:20:43.36#ibcon#read 4, iclass 19, count 2 2006.173.08:20:43.36#ibcon#about to read 5, iclass 19, count 2 2006.173.08:20:43.36#ibcon#read 5, iclass 19, count 2 2006.173.08:20:43.36#ibcon#about to read 6, iclass 19, count 2 2006.173.08:20:43.36#ibcon#read 6, iclass 19, count 2 2006.173.08:20:43.36#ibcon#end of sib2, iclass 19, count 2 2006.173.08:20:43.36#ibcon#*after write, iclass 19, count 2 2006.173.08:20:43.36#ibcon#*before return 0, iclass 19, count 2 2006.173.08:20:43.36#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.08:20:43.36#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.08:20:43.36#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.08:20:43.36#ibcon#ireg 7 cls_cnt 0 2006.173.08:20:43.36#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.08:20:43.48#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.08:20:43.48#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.08:20:43.48#ibcon#enter wrdev, iclass 19, count 0 2006.173.08:20:43.48#ibcon#first serial, iclass 19, count 0 2006.173.08:20:43.48#ibcon#enter sib2, iclass 19, count 0 2006.173.08:20:43.48#ibcon#flushed, iclass 19, count 0 2006.173.08:20:43.48#ibcon#about to write, iclass 19, count 0 2006.173.08:20:43.48#ibcon#wrote, iclass 19, count 0 2006.173.08:20:43.48#ibcon#about to read 3, iclass 19, count 0 2006.173.08:20:43.50#ibcon#read 3, iclass 19, count 0 2006.173.08:20:43.50#ibcon#about to read 4, iclass 19, count 0 2006.173.08:20:43.50#ibcon#read 4, iclass 19, count 0 2006.173.08:20:43.50#ibcon#about to read 5, iclass 19, count 0 2006.173.08:20:43.50#ibcon#read 5, iclass 19, count 0 2006.173.08:20:43.50#ibcon#about to read 6, iclass 19, count 0 2006.173.08:20:43.50#ibcon#read 6, iclass 19, count 0 2006.173.08:20:43.50#ibcon#end of sib2, iclass 19, count 0 2006.173.08:20:43.50#ibcon#*mode == 0, iclass 19, count 0 2006.173.08:20:43.50#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.08:20:43.50#ibcon#[27=USB\r\n] 2006.173.08:20:43.50#ibcon#*before write, iclass 19, count 0 2006.173.08:20:43.50#ibcon#enter sib2, iclass 19, count 0 2006.173.08:20:43.50#ibcon#flushed, iclass 19, count 0 2006.173.08:20:43.50#ibcon#about to write, iclass 19, count 0 2006.173.08:20:43.50#ibcon#wrote, iclass 19, count 0 2006.173.08:20:43.50#ibcon#about to read 3, iclass 19, count 0 2006.173.08:20:43.53#ibcon#read 3, iclass 19, count 0 2006.173.08:20:43.53#ibcon#about to read 4, iclass 19, count 0 2006.173.08:20:43.53#ibcon#read 4, iclass 19, count 0 2006.173.08:20:43.53#ibcon#about to read 5, iclass 19, count 0 2006.173.08:20:43.53#ibcon#read 5, iclass 19, count 0 2006.173.08:20:43.53#ibcon#about to read 6, iclass 19, count 0 2006.173.08:20:43.53#ibcon#read 6, iclass 19, count 0 2006.173.08:20:43.53#ibcon#end of sib2, iclass 19, count 0 2006.173.08:20:43.53#ibcon#*after write, iclass 19, count 0 2006.173.08:20:43.53#ibcon#*before return 0, iclass 19, count 0 2006.173.08:20:43.53#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.08:20:43.53#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.08:20:43.53#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.08:20:43.53#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.08:20:43.53$vck44/vabw=wide 2006.173.08:20:43.53#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.08:20:43.53#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.08:20:43.53#ibcon#ireg 8 cls_cnt 0 2006.173.08:20:43.53#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.08:20:43.53#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.08:20:43.53#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.08:20:43.53#ibcon#enter wrdev, iclass 21, count 0 2006.173.08:20:43.53#ibcon#first serial, iclass 21, count 0 2006.173.08:20:43.53#ibcon#enter sib2, iclass 21, count 0 2006.173.08:20:43.53#ibcon#flushed, iclass 21, count 0 2006.173.08:20:43.53#ibcon#about to write, iclass 21, count 0 2006.173.08:20:43.53#ibcon#wrote, iclass 21, count 0 2006.173.08:20:43.53#ibcon#about to read 3, iclass 21, count 0 2006.173.08:20:43.55#ibcon#read 3, iclass 21, count 0 2006.173.08:20:43.55#ibcon#about to read 4, iclass 21, count 0 2006.173.08:20:43.55#ibcon#read 4, iclass 21, count 0 2006.173.08:20:43.55#ibcon#about to read 5, iclass 21, count 0 2006.173.08:20:43.55#ibcon#read 5, iclass 21, count 0 2006.173.08:20:43.55#ibcon#about to read 6, iclass 21, count 0 2006.173.08:20:43.55#ibcon#read 6, iclass 21, count 0 2006.173.08:20:43.55#ibcon#end of sib2, iclass 21, count 0 2006.173.08:20:43.55#ibcon#*mode == 0, iclass 21, count 0 2006.173.08:20:43.55#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.08:20:43.55#ibcon#[25=BW32\r\n] 2006.173.08:20:43.55#ibcon#*before write, iclass 21, count 0 2006.173.08:20:43.55#ibcon#enter sib2, iclass 21, count 0 2006.173.08:20:43.55#ibcon#flushed, iclass 21, count 0 2006.173.08:20:43.55#ibcon#about to write, iclass 21, count 0 2006.173.08:20:43.55#ibcon#wrote, iclass 21, count 0 2006.173.08:20:43.55#ibcon#about to read 3, iclass 21, count 0 2006.173.08:20:43.58#ibcon#read 3, iclass 21, count 0 2006.173.08:20:43.58#ibcon#about to read 4, iclass 21, count 0 2006.173.08:20:43.58#ibcon#read 4, iclass 21, count 0 2006.173.08:20:43.58#ibcon#about to read 5, iclass 21, count 0 2006.173.08:20:43.58#ibcon#read 5, iclass 21, count 0 2006.173.08:20:43.58#ibcon#about to read 6, iclass 21, count 0 2006.173.08:20:43.58#ibcon#read 6, iclass 21, count 0 2006.173.08:20:43.58#ibcon#end of sib2, iclass 21, count 0 2006.173.08:20:43.58#ibcon#*after write, iclass 21, count 0 2006.173.08:20:43.58#ibcon#*before return 0, iclass 21, count 0 2006.173.08:20:43.58#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.08:20:43.58#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.08:20:43.58#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.08:20:43.58#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.08:20:43.58$vck44/vbbw=wide 2006.173.08:20:43.58#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.08:20:43.58#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.08:20:43.58#ibcon#ireg 8 cls_cnt 0 2006.173.08:20:43.58#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.08:20:43.65#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.08:20:43.65#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.08:20:43.65#ibcon#enter wrdev, iclass 23, count 0 2006.173.08:20:43.65#ibcon#first serial, iclass 23, count 0 2006.173.08:20:43.65#ibcon#enter sib2, iclass 23, count 0 2006.173.08:20:43.65#ibcon#flushed, iclass 23, count 0 2006.173.08:20:43.65#ibcon#about to write, iclass 23, count 0 2006.173.08:20:43.65#ibcon#wrote, iclass 23, count 0 2006.173.08:20:43.65#ibcon#about to read 3, iclass 23, count 0 2006.173.08:20:43.67#ibcon#read 3, iclass 23, count 0 2006.173.08:20:43.67#ibcon#about to read 4, iclass 23, count 0 2006.173.08:20:43.67#ibcon#read 4, iclass 23, count 0 2006.173.08:20:43.67#ibcon#about to read 5, iclass 23, count 0 2006.173.08:20:43.67#ibcon#read 5, iclass 23, count 0 2006.173.08:20:43.67#ibcon#about to read 6, iclass 23, count 0 2006.173.08:20:43.67#ibcon#read 6, iclass 23, count 0 2006.173.08:20:43.67#ibcon#end of sib2, iclass 23, count 0 2006.173.08:20:43.67#ibcon#*mode == 0, iclass 23, count 0 2006.173.08:20:43.67#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.08:20:43.67#ibcon#[27=BW32\r\n] 2006.173.08:20:43.67#ibcon#*before write, iclass 23, count 0 2006.173.08:20:43.67#ibcon#enter sib2, iclass 23, count 0 2006.173.08:20:43.67#ibcon#flushed, iclass 23, count 0 2006.173.08:20:43.67#ibcon#about to write, iclass 23, count 0 2006.173.08:20:43.67#ibcon#wrote, iclass 23, count 0 2006.173.08:20:43.67#ibcon#about to read 3, iclass 23, count 0 2006.173.08:20:43.70#ibcon#read 3, iclass 23, count 0 2006.173.08:20:43.70#ibcon#about to read 4, iclass 23, count 0 2006.173.08:20:43.70#ibcon#read 4, iclass 23, count 0 2006.173.08:20:43.70#ibcon#about to read 5, iclass 23, count 0 2006.173.08:20:43.70#ibcon#read 5, iclass 23, count 0 2006.173.08:20:43.70#ibcon#about to read 6, iclass 23, count 0 2006.173.08:20:43.70#ibcon#read 6, iclass 23, count 0 2006.173.08:20:43.70#ibcon#end of sib2, iclass 23, count 0 2006.173.08:20:43.70#ibcon#*after write, iclass 23, count 0 2006.173.08:20:43.70#ibcon#*before return 0, iclass 23, count 0 2006.173.08:20:43.70#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.08:20:43.70#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.08:20:43.70#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.08:20:43.70#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.08:20:43.70$setupk4/ifdk4 2006.173.08:20:43.70$ifdk4/lo= 2006.173.08:20:43.70$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.08:20:43.70$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.08:20:43.70$ifdk4/patch= 2006.173.08:20:43.70$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.08:20:43.70$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.08:20:43.70$setupk4/!*+20s 2006.173.08:20:46.66#abcon#<5=/00 0.2 0.8 23.61 851004.0\r\n> 2006.173.08:20:46.68#abcon#{5=INTERFACE CLEAR} 2006.173.08:20:46.74#abcon#[5=S1D000X0/0*\r\n] 2006.173.08:20:56.83#abcon#<5=/00 0.2 0.8 23.61 851004.0\r\n> 2006.173.08:20:56.85#abcon#{5=INTERFACE CLEAR} 2006.173.08:20:56.91#abcon#[5=S1D000X0/0*\r\n] 2006.173.08:20:58.20$setupk4/"tpicd 2006.173.08:20:58.20$setupk4/echo=off 2006.173.08:20:58.20$setupk4/xlog=off 2006.173.08:20:58.20:!2006.173.08:27:36 2006.173.08:21:15.14#trakl#Source acquired 2006.173.08:21:16.14#flagr#flagr/antenna,acquired 2006.173.08:27:36.00:preob 2006.173.08:27:36.13/onsource/TRACKING 2006.173.08:27:36.13:!2006.173.08:27:46 2006.173.08:27:46.00:"tape 2006.173.08:27:46.00:"st=record 2006.173.08:27:46.00:data_valid=on 2006.173.08:27:46.00:midob 2006.173.08:27:46.13/onsource/TRACKING 2006.173.08:27:46.13/wx/23.47,1004.0,86 2006.173.08:27:46.33/cable/+6.5008E-03 2006.173.08:27:47.42/va/01,07,usb,yes,34,37 2006.173.08:27:47.42/va/02,06,usb,yes,34,35 2006.173.08:27:47.42/va/03,05,usb,yes,43,45 2006.173.08:27:47.42/va/04,06,usb,yes,34,36 2006.173.08:27:47.42/va/05,04,usb,yes,27,27 2006.173.08:27:47.42/va/06,03,usb,yes,38,38 2006.173.08:27:47.42/va/07,04,usb,yes,31,32 2006.173.08:27:47.42/va/08,04,usb,yes,26,32 2006.173.08:27:47.65/valo/01,524.99,yes,locked 2006.173.08:27:47.65/valo/02,534.99,yes,locked 2006.173.08:27:47.65/valo/03,564.99,yes,locked 2006.173.08:27:47.65/valo/04,624.99,yes,locked 2006.173.08:27:47.65/valo/05,734.99,yes,locked 2006.173.08:27:47.65/valo/06,814.99,yes,locked 2006.173.08:27:47.65/valo/07,864.99,yes,locked 2006.173.08:27:47.65/valo/08,884.99,yes,locked 2006.173.08:27:48.74/vb/01,04,usb,yes,28,27 2006.173.08:27:48.74/vb/02,04,usb,yes,31,31 2006.173.08:27:48.74/vb/03,04,usb,yes,28,31 2006.173.08:27:48.74/vb/04,04,usb,yes,32,31 2006.173.08:27:48.74/vb/05,04,usb,yes,25,27 2006.173.08:27:48.74/vb/06,04,usb,yes,29,26 2006.173.08:27:48.74/vb/07,04,usb,yes,29,29 2006.173.08:27:48.74/vb/08,04,usb,yes,27,30 2006.173.08:27:48.97/vblo/01,629.99,yes,locked 2006.173.08:27:48.97/vblo/02,634.99,yes,locked 2006.173.08:27:48.97/vblo/03,649.99,yes,locked 2006.173.08:27:48.97/vblo/04,679.99,yes,locked 2006.173.08:27:48.97/vblo/05,709.99,yes,locked 2006.173.08:27:48.97/vblo/06,719.99,yes,locked 2006.173.08:27:48.97/vblo/07,734.99,yes,locked 2006.173.08:27:48.97/vblo/08,744.99,yes,locked 2006.173.08:27:49.12/vabw/8 2006.173.08:27:49.27/vbbw/8 2006.173.08:27:49.36/xfe/off,on,14.5 2006.173.08:27:49.75/ifatt/23,28,28,28 2006.173.08:27:50.08/fmout-gps/S +3.94E-07 2006.173.08:27:50.12:!2006.173.08:34:46 2006.173.08:34:46.00:data_valid=off 2006.173.08:34:46.01:"et 2006.173.08:34:46.01:!+3s 2006.173.08:34:49.02:"tape 2006.173.08:34:49.03:postob 2006.173.08:34:49.12/cable/+6.5002E-03 2006.173.08:34:49.13/wx/23.36,1004.0,86 2006.173.08:34:49.18/fmout-gps/S +3.93E-07 2006.173.08:34:49.19:scan_name=173-0841,jd0606,140 2006.173.08:34:49.19:source=1749+096,175132.82,093900.7,2000.0,ccw 2006.173.08:34:50.13#flagr#flagr/antenna,new-source 2006.173.08:34:50.14:checkk5 2006.173.08:34:50.56/chk_autoobs//k5ts1/ autoobs is running! 2006.173.08:34:50.96/chk_autoobs//k5ts2/ autoobs is running! 2006.173.08:34:51.36/chk_autoobs//k5ts3/ autoobs is running! 2006.173.08:34:51.76/chk_autoobs//k5ts4/ autoobs is running! 2006.173.08:34:52.15/chk_obsdata//k5ts1/T1730827??a.dat file size is correct (nominal:1680MB, actual:1680MB). 2006.173.08:34:52.53/chk_obsdata//k5ts2/T1730827??b.dat file size is correct (nominal:1680MB, actual:1680MB). 2006.173.08:34:52.93/chk_obsdata//k5ts3/T1730827??c.dat file size is correct (nominal:1680MB, actual:1680MB). 2006.173.08:34:53.34/chk_obsdata//k5ts4/T1730827??d.dat file size is correct (nominal:1680MB, actual:1680MB). 2006.173.08:34:54.09/k5log//k5ts1_log_newline 2006.173.08:34:54.80/k5log//k5ts2_log_newline 2006.173.08:34:55.50/k5log//k5ts3_log_newline 2006.173.08:34:56.21/k5log//k5ts4_log_newline 2006.173.08:34:56.23/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.08:34:56.23:setupk4=1 2006.173.08:34:56.23$setupk4/echo=on 2006.173.08:34:56.23$setupk4/pcalon 2006.173.08:34:56.23$pcalon/"no phase cal control is implemented here 2006.173.08:34:56.23$setupk4/"tpicd=stop 2006.173.08:34:56.23$setupk4/"rec=synch_on 2006.173.08:34:56.23$setupk4/"rec_mode=128 2006.173.08:34:56.23$setupk4/!* 2006.173.08:34:56.23$setupk4/recpk4 2006.173.08:34:56.23$recpk4/recpatch= 2006.173.08:34:56.24$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.08:34:56.24$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.08:34:56.24$setupk4/vck44 2006.173.08:34:56.24$vck44/valo=1,524.99 2006.173.08:34:56.24#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.08:34:56.24#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.08:34:56.24#ibcon#ireg 17 cls_cnt 0 2006.173.08:34:56.24#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.08:34:56.24#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.08:34:56.24#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.08:34:56.24#ibcon#enter wrdev, iclass 40, count 0 2006.173.08:34:56.24#ibcon#first serial, iclass 40, count 0 2006.173.08:34:56.24#ibcon#enter sib2, iclass 40, count 0 2006.173.08:34:56.24#ibcon#flushed, iclass 40, count 0 2006.173.08:34:56.24#ibcon#about to write, iclass 40, count 0 2006.173.08:34:56.24#ibcon#wrote, iclass 40, count 0 2006.173.08:34:56.24#ibcon#about to read 3, iclass 40, count 0 2006.173.08:34:56.25#ibcon#read 3, iclass 40, count 0 2006.173.08:34:56.25#ibcon#about to read 4, iclass 40, count 0 2006.173.08:34:56.25#ibcon#read 4, iclass 40, count 0 2006.173.08:34:56.25#ibcon#about to read 5, iclass 40, count 0 2006.173.08:34:56.25#ibcon#read 5, iclass 40, count 0 2006.173.08:34:56.25#ibcon#about to read 6, iclass 40, count 0 2006.173.08:34:56.25#ibcon#read 6, iclass 40, count 0 2006.173.08:34:56.25#ibcon#end of sib2, iclass 40, count 0 2006.173.08:34:56.25#ibcon#*mode == 0, iclass 40, count 0 2006.173.08:34:56.25#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.08:34:56.25#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.08:34:56.25#ibcon#*before write, iclass 40, count 0 2006.173.08:34:56.25#ibcon#enter sib2, iclass 40, count 0 2006.173.08:34:56.25#ibcon#flushed, iclass 40, count 0 2006.173.08:34:56.25#ibcon#about to write, iclass 40, count 0 2006.173.08:34:56.25#ibcon#wrote, iclass 40, count 0 2006.173.08:34:56.25#ibcon#about to read 3, iclass 40, count 0 2006.173.08:34:56.30#ibcon#read 3, iclass 40, count 0 2006.173.08:34:56.30#ibcon#about to read 4, iclass 40, count 0 2006.173.08:34:56.30#ibcon#read 4, iclass 40, count 0 2006.173.08:34:56.30#ibcon#about to read 5, iclass 40, count 0 2006.173.08:34:56.30#ibcon#read 5, iclass 40, count 0 2006.173.08:34:56.30#ibcon#about to read 6, iclass 40, count 0 2006.173.08:34:56.30#ibcon#read 6, iclass 40, count 0 2006.173.08:34:56.30#ibcon#end of sib2, iclass 40, count 0 2006.173.08:34:56.30#ibcon#*after write, iclass 40, count 0 2006.173.08:34:56.30#ibcon#*before return 0, iclass 40, count 0 2006.173.08:34:56.30#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.08:34:56.30#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.08:34:56.30#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.08:34:56.30#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.08:34:56.30$vck44/va=1,7 2006.173.08:34:56.30#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.08:34:56.30#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.08:34:56.30#ibcon#ireg 11 cls_cnt 2 2006.173.08:34:56.30#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.08:34:56.30#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.08:34:56.30#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.08:34:56.30#ibcon#enter wrdev, iclass 4, count 2 2006.173.08:34:56.30#ibcon#first serial, iclass 4, count 2 2006.173.08:34:56.30#ibcon#enter sib2, iclass 4, count 2 2006.173.08:34:56.30#ibcon#flushed, iclass 4, count 2 2006.173.08:34:56.30#ibcon#about to write, iclass 4, count 2 2006.173.08:34:56.30#ibcon#wrote, iclass 4, count 2 2006.173.08:34:56.30#ibcon#about to read 3, iclass 4, count 2 2006.173.08:34:56.32#ibcon#read 3, iclass 4, count 2 2006.173.08:34:56.32#ibcon#about to read 4, iclass 4, count 2 2006.173.08:34:56.32#ibcon#read 4, iclass 4, count 2 2006.173.08:34:56.32#ibcon#about to read 5, iclass 4, count 2 2006.173.08:34:56.32#ibcon#read 5, iclass 4, count 2 2006.173.08:34:56.32#ibcon#about to read 6, iclass 4, count 2 2006.173.08:34:56.32#ibcon#read 6, iclass 4, count 2 2006.173.08:34:56.32#ibcon#end of sib2, iclass 4, count 2 2006.173.08:34:56.32#ibcon#*mode == 0, iclass 4, count 2 2006.173.08:34:56.32#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.08:34:56.32#ibcon#[25=AT01-07\r\n] 2006.173.08:34:56.32#ibcon#*before write, iclass 4, count 2 2006.173.08:34:56.32#ibcon#enter sib2, iclass 4, count 2 2006.173.08:34:56.32#ibcon#flushed, iclass 4, count 2 2006.173.08:34:56.32#ibcon#about to write, iclass 4, count 2 2006.173.08:34:56.32#ibcon#wrote, iclass 4, count 2 2006.173.08:34:56.32#ibcon#about to read 3, iclass 4, count 2 2006.173.08:34:56.35#ibcon#read 3, iclass 4, count 2 2006.173.08:34:56.35#ibcon#about to read 4, iclass 4, count 2 2006.173.08:34:56.35#ibcon#read 4, iclass 4, count 2 2006.173.08:34:56.35#ibcon#about to read 5, iclass 4, count 2 2006.173.08:34:56.35#ibcon#read 5, iclass 4, count 2 2006.173.08:34:56.35#ibcon#about to read 6, iclass 4, count 2 2006.173.08:34:56.35#ibcon#read 6, iclass 4, count 2 2006.173.08:34:56.35#ibcon#end of sib2, iclass 4, count 2 2006.173.08:34:56.35#ibcon#*after write, iclass 4, count 2 2006.173.08:34:56.35#ibcon#*before return 0, iclass 4, count 2 2006.173.08:34:56.35#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.08:34:56.35#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.08:34:56.35#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.08:34:56.35#ibcon#ireg 7 cls_cnt 0 2006.173.08:34:56.35#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.08:34:56.47#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.08:34:56.47#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.08:34:56.47#ibcon#enter wrdev, iclass 4, count 0 2006.173.08:34:56.47#ibcon#first serial, iclass 4, count 0 2006.173.08:34:56.47#ibcon#enter sib2, iclass 4, count 0 2006.173.08:34:56.47#ibcon#flushed, iclass 4, count 0 2006.173.08:34:56.47#ibcon#about to write, iclass 4, count 0 2006.173.08:34:56.47#ibcon#wrote, iclass 4, count 0 2006.173.08:34:56.47#ibcon#about to read 3, iclass 4, count 0 2006.173.08:34:56.49#ibcon#read 3, iclass 4, count 0 2006.173.08:34:56.49#ibcon#about to read 4, iclass 4, count 0 2006.173.08:34:56.49#ibcon#read 4, iclass 4, count 0 2006.173.08:34:56.49#ibcon#about to read 5, iclass 4, count 0 2006.173.08:34:56.49#ibcon#read 5, iclass 4, count 0 2006.173.08:34:56.49#ibcon#about to read 6, iclass 4, count 0 2006.173.08:34:56.49#ibcon#read 6, iclass 4, count 0 2006.173.08:34:56.49#ibcon#end of sib2, iclass 4, count 0 2006.173.08:34:56.49#ibcon#*mode == 0, iclass 4, count 0 2006.173.08:34:56.49#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.08:34:56.49#ibcon#[25=USB\r\n] 2006.173.08:34:56.49#ibcon#*before write, iclass 4, count 0 2006.173.08:34:56.49#ibcon#enter sib2, iclass 4, count 0 2006.173.08:34:56.49#ibcon#flushed, iclass 4, count 0 2006.173.08:34:56.49#ibcon#about to write, iclass 4, count 0 2006.173.08:34:56.49#ibcon#wrote, iclass 4, count 0 2006.173.08:34:56.49#ibcon#about to read 3, iclass 4, count 0 2006.173.08:34:56.52#ibcon#read 3, iclass 4, count 0 2006.173.08:34:56.52#ibcon#about to read 4, iclass 4, count 0 2006.173.08:34:56.52#ibcon#read 4, iclass 4, count 0 2006.173.08:34:56.52#ibcon#about to read 5, iclass 4, count 0 2006.173.08:34:56.52#ibcon#read 5, iclass 4, count 0 2006.173.08:34:56.52#ibcon#about to read 6, iclass 4, count 0 2006.173.08:34:56.52#ibcon#read 6, iclass 4, count 0 2006.173.08:34:56.52#ibcon#end of sib2, iclass 4, count 0 2006.173.08:34:56.52#ibcon#*after write, iclass 4, count 0 2006.173.08:34:56.52#ibcon#*before return 0, iclass 4, count 0 2006.173.08:34:56.52#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.08:34:56.52#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.08:34:56.52#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.08:34:56.52#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.08:34:56.52$vck44/valo=2,534.99 2006.173.08:34:56.52#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.08:34:56.52#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.08:34:56.52#ibcon#ireg 17 cls_cnt 0 2006.173.08:34:56.52#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.08:34:56.52#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.08:34:56.52#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.08:34:56.52#ibcon#enter wrdev, iclass 6, count 0 2006.173.08:34:56.52#ibcon#first serial, iclass 6, count 0 2006.173.08:34:56.52#ibcon#enter sib2, iclass 6, count 0 2006.173.08:34:56.52#ibcon#flushed, iclass 6, count 0 2006.173.08:34:56.52#ibcon#about to write, iclass 6, count 0 2006.173.08:34:56.52#ibcon#wrote, iclass 6, count 0 2006.173.08:34:56.52#ibcon#about to read 3, iclass 6, count 0 2006.173.08:34:56.54#ibcon#read 3, iclass 6, count 0 2006.173.08:34:56.54#ibcon#about to read 4, iclass 6, count 0 2006.173.08:34:56.54#ibcon#read 4, iclass 6, count 0 2006.173.08:34:56.54#ibcon#about to read 5, iclass 6, count 0 2006.173.08:34:56.54#ibcon#read 5, iclass 6, count 0 2006.173.08:34:56.54#ibcon#about to read 6, iclass 6, count 0 2006.173.08:34:56.54#ibcon#read 6, iclass 6, count 0 2006.173.08:34:56.54#ibcon#end of sib2, iclass 6, count 0 2006.173.08:34:56.54#ibcon#*mode == 0, iclass 6, count 0 2006.173.08:34:56.54#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.08:34:56.54#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.08:34:56.54#ibcon#*before write, iclass 6, count 0 2006.173.08:34:56.54#ibcon#enter sib2, iclass 6, count 0 2006.173.08:34:56.54#ibcon#flushed, iclass 6, count 0 2006.173.08:34:56.54#ibcon#about to write, iclass 6, count 0 2006.173.08:34:56.54#ibcon#wrote, iclass 6, count 0 2006.173.08:34:56.54#ibcon#about to read 3, iclass 6, count 0 2006.173.08:34:56.58#ibcon#read 3, iclass 6, count 0 2006.173.08:34:56.58#ibcon#about to read 4, iclass 6, count 0 2006.173.08:34:56.58#ibcon#read 4, iclass 6, count 0 2006.173.08:34:56.58#ibcon#about to read 5, iclass 6, count 0 2006.173.08:34:56.58#ibcon#read 5, iclass 6, count 0 2006.173.08:34:56.58#ibcon#about to read 6, iclass 6, count 0 2006.173.08:34:56.58#ibcon#read 6, iclass 6, count 0 2006.173.08:34:56.58#ibcon#end of sib2, iclass 6, count 0 2006.173.08:34:56.58#ibcon#*after write, iclass 6, count 0 2006.173.08:34:56.58#ibcon#*before return 0, iclass 6, count 0 2006.173.08:34:56.58#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.08:34:56.58#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.08:34:56.58#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.08:34:56.58#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.08:34:56.58$vck44/va=2,6 2006.173.08:34:56.58#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.08:34:56.58#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.08:34:56.58#ibcon#ireg 11 cls_cnt 2 2006.173.08:34:56.58#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.08:34:56.64#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.08:34:56.64#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.08:34:56.64#ibcon#enter wrdev, iclass 10, count 2 2006.173.08:34:56.64#ibcon#first serial, iclass 10, count 2 2006.173.08:34:56.64#ibcon#enter sib2, iclass 10, count 2 2006.173.08:34:56.64#ibcon#flushed, iclass 10, count 2 2006.173.08:34:56.64#ibcon#about to write, iclass 10, count 2 2006.173.08:34:56.64#ibcon#wrote, iclass 10, count 2 2006.173.08:34:56.64#ibcon#about to read 3, iclass 10, count 2 2006.173.08:34:56.66#ibcon#read 3, iclass 10, count 2 2006.173.08:34:56.66#ibcon#about to read 4, iclass 10, count 2 2006.173.08:34:56.66#ibcon#read 4, iclass 10, count 2 2006.173.08:34:56.66#ibcon#about to read 5, iclass 10, count 2 2006.173.08:34:56.66#ibcon#read 5, iclass 10, count 2 2006.173.08:34:56.66#ibcon#about to read 6, iclass 10, count 2 2006.173.08:34:56.66#ibcon#read 6, iclass 10, count 2 2006.173.08:34:56.66#ibcon#end of sib2, iclass 10, count 2 2006.173.08:34:56.66#ibcon#*mode == 0, iclass 10, count 2 2006.173.08:34:56.66#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.08:34:56.66#ibcon#[25=AT02-06\r\n] 2006.173.08:34:56.66#ibcon#*before write, iclass 10, count 2 2006.173.08:34:56.66#ibcon#enter sib2, iclass 10, count 2 2006.173.08:34:56.66#ibcon#flushed, iclass 10, count 2 2006.173.08:34:56.66#ibcon#about to write, iclass 10, count 2 2006.173.08:34:56.66#ibcon#wrote, iclass 10, count 2 2006.173.08:34:56.66#ibcon#about to read 3, iclass 10, count 2 2006.173.08:34:56.69#ibcon#read 3, iclass 10, count 2 2006.173.08:34:56.69#ibcon#about to read 4, iclass 10, count 2 2006.173.08:34:56.69#ibcon#read 4, iclass 10, count 2 2006.173.08:34:56.69#ibcon#about to read 5, iclass 10, count 2 2006.173.08:34:56.69#ibcon#read 5, iclass 10, count 2 2006.173.08:34:56.69#ibcon#about to read 6, iclass 10, count 2 2006.173.08:34:56.69#ibcon#read 6, iclass 10, count 2 2006.173.08:34:56.69#ibcon#end of sib2, iclass 10, count 2 2006.173.08:34:56.69#ibcon#*after write, iclass 10, count 2 2006.173.08:34:56.69#ibcon#*before return 0, iclass 10, count 2 2006.173.08:34:56.69#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.08:34:56.69#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.08:34:56.69#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.08:34:56.69#ibcon#ireg 7 cls_cnt 0 2006.173.08:34:56.69#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.08:34:56.81#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.08:34:56.81#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.08:34:56.81#ibcon#enter wrdev, iclass 10, count 0 2006.173.08:34:56.81#ibcon#first serial, iclass 10, count 0 2006.173.08:34:56.81#ibcon#enter sib2, iclass 10, count 0 2006.173.08:34:56.81#ibcon#flushed, iclass 10, count 0 2006.173.08:34:56.81#ibcon#about to write, iclass 10, count 0 2006.173.08:34:56.81#ibcon#wrote, iclass 10, count 0 2006.173.08:34:56.81#ibcon#about to read 3, iclass 10, count 0 2006.173.08:34:56.83#ibcon#read 3, iclass 10, count 0 2006.173.08:34:56.83#ibcon#about to read 4, iclass 10, count 0 2006.173.08:34:56.83#ibcon#read 4, iclass 10, count 0 2006.173.08:34:56.83#ibcon#about to read 5, iclass 10, count 0 2006.173.08:34:56.83#ibcon#read 5, iclass 10, count 0 2006.173.08:34:56.83#ibcon#about to read 6, iclass 10, count 0 2006.173.08:34:56.83#ibcon#read 6, iclass 10, count 0 2006.173.08:34:56.83#ibcon#end of sib2, iclass 10, count 0 2006.173.08:34:56.83#ibcon#*mode == 0, iclass 10, count 0 2006.173.08:34:56.83#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.08:34:56.83#ibcon#[25=USB\r\n] 2006.173.08:34:56.83#ibcon#*before write, iclass 10, count 0 2006.173.08:34:56.83#ibcon#enter sib2, iclass 10, count 0 2006.173.08:34:56.83#ibcon#flushed, iclass 10, count 0 2006.173.08:34:56.83#ibcon#about to write, iclass 10, count 0 2006.173.08:34:56.83#ibcon#wrote, iclass 10, count 0 2006.173.08:34:56.83#ibcon#about to read 3, iclass 10, count 0 2006.173.08:34:56.86#ibcon#read 3, iclass 10, count 0 2006.173.08:34:56.86#ibcon#about to read 4, iclass 10, count 0 2006.173.08:34:56.86#ibcon#read 4, iclass 10, count 0 2006.173.08:34:56.86#ibcon#about to read 5, iclass 10, count 0 2006.173.08:34:56.86#ibcon#read 5, iclass 10, count 0 2006.173.08:34:56.86#ibcon#about to read 6, iclass 10, count 0 2006.173.08:34:56.86#ibcon#read 6, iclass 10, count 0 2006.173.08:34:56.86#ibcon#end of sib2, iclass 10, count 0 2006.173.08:34:56.86#ibcon#*after write, iclass 10, count 0 2006.173.08:34:56.86#ibcon#*before return 0, iclass 10, count 0 2006.173.08:34:56.86#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.08:34:56.86#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.08:34:56.86#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.08:34:56.86#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.08:34:56.86$vck44/valo=3,564.99 2006.173.08:34:56.86#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.08:34:56.86#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.08:34:56.86#ibcon#ireg 17 cls_cnt 0 2006.173.08:34:56.86#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.08:34:56.86#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.08:34:56.86#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.08:34:56.86#ibcon#enter wrdev, iclass 12, count 0 2006.173.08:34:56.86#ibcon#first serial, iclass 12, count 0 2006.173.08:34:56.86#ibcon#enter sib2, iclass 12, count 0 2006.173.08:34:56.86#ibcon#flushed, iclass 12, count 0 2006.173.08:34:56.86#ibcon#about to write, iclass 12, count 0 2006.173.08:34:56.86#ibcon#wrote, iclass 12, count 0 2006.173.08:34:56.86#ibcon#about to read 3, iclass 12, count 0 2006.173.08:34:56.88#ibcon#read 3, iclass 12, count 0 2006.173.08:34:56.88#ibcon#about to read 4, iclass 12, count 0 2006.173.08:34:56.88#ibcon#read 4, iclass 12, count 0 2006.173.08:34:56.88#ibcon#about to read 5, iclass 12, count 0 2006.173.08:34:56.88#ibcon#read 5, iclass 12, count 0 2006.173.08:34:56.88#ibcon#about to read 6, iclass 12, count 0 2006.173.08:34:56.88#ibcon#read 6, iclass 12, count 0 2006.173.08:34:56.88#ibcon#end of sib2, iclass 12, count 0 2006.173.08:34:56.88#ibcon#*mode == 0, iclass 12, count 0 2006.173.08:34:56.88#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.08:34:56.88#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.08:34:56.88#ibcon#*before write, iclass 12, count 0 2006.173.08:34:56.88#ibcon#enter sib2, iclass 12, count 0 2006.173.08:34:56.88#ibcon#flushed, iclass 12, count 0 2006.173.08:34:56.88#ibcon#about to write, iclass 12, count 0 2006.173.08:34:56.88#ibcon#wrote, iclass 12, count 0 2006.173.08:34:56.88#ibcon#about to read 3, iclass 12, count 0 2006.173.08:34:56.92#ibcon#read 3, iclass 12, count 0 2006.173.08:34:56.92#ibcon#about to read 4, iclass 12, count 0 2006.173.08:34:56.92#ibcon#read 4, iclass 12, count 0 2006.173.08:34:56.92#ibcon#about to read 5, iclass 12, count 0 2006.173.08:34:56.92#ibcon#read 5, iclass 12, count 0 2006.173.08:34:56.92#ibcon#about to read 6, iclass 12, count 0 2006.173.08:34:56.92#ibcon#read 6, iclass 12, count 0 2006.173.08:34:56.92#ibcon#end of sib2, iclass 12, count 0 2006.173.08:34:56.92#ibcon#*after write, iclass 12, count 0 2006.173.08:34:56.92#ibcon#*before return 0, iclass 12, count 0 2006.173.08:34:56.92#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.08:34:56.92#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.08:34:56.92#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.08:34:56.92#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.08:34:56.92$vck44/va=3,5 2006.173.08:34:56.92#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.08:34:56.92#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.08:34:56.92#ibcon#ireg 11 cls_cnt 2 2006.173.08:34:56.92#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.08:34:56.98#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.08:34:56.98#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.08:34:56.98#ibcon#enter wrdev, iclass 14, count 2 2006.173.08:34:56.98#ibcon#first serial, iclass 14, count 2 2006.173.08:34:56.98#ibcon#enter sib2, iclass 14, count 2 2006.173.08:34:56.98#ibcon#flushed, iclass 14, count 2 2006.173.08:34:56.98#ibcon#about to write, iclass 14, count 2 2006.173.08:34:56.98#ibcon#wrote, iclass 14, count 2 2006.173.08:34:56.98#ibcon#about to read 3, iclass 14, count 2 2006.173.08:34:57.00#ibcon#read 3, iclass 14, count 2 2006.173.08:34:57.00#ibcon#about to read 4, iclass 14, count 2 2006.173.08:34:57.00#ibcon#read 4, iclass 14, count 2 2006.173.08:34:57.00#ibcon#about to read 5, iclass 14, count 2 2006.173.08:34:57.00#ibcon#read 5, iclass 14, count 2 2006.173.08:34:57.00#ibcon#about to read 6, iclass 14, count 2 2006.173.08:34:57.00#ibcon#read 6, iclass 14, count 2 2006.173.08:34:57.00#ibcon#end of sib2, iclass 14, count 2 2006.173.08:34:57.00#ibcon#*mode == 0, iclass 14, count 2 2006.173.08:34:57.00#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.08:34:57.00#ibcon#[25=AT03-05\r\n] 2006.173.08:34:57.00#ibcon#*before write, iclass 14, count 2 2006.173.08:34:57.00#ibcon#enter sib2, iclass 14, count 2 2006.173.08:34:57.00#ibcon#flushed, iclass 14, count 2 2006.173.08:34:57.00#ibcon#about to write, iclass 14, count 2 2006.173.08:34:57.00#ibcon#wrote, iclass 14, count 2 2006.173.08:34:57.00#ibcon#about to read 3, iclass 14, count 2 2006.173.08:34:57.03#ibcon#read 3, iclass 14, count 2 2006.173.08:34:57.03#ibcon#about to read 4, iclass 14, count 2 2006.173.08:34:57.03#ibcon#read 4, iclass 14, count 2 2006.173.08:34:57.03#ibcon#about to read 5, iclass 14, count 2 2006.173.08:34:57.03#ibcon#read 5, iclass 14, count 2 2006.173.08:34:57.03#ibcon#about to read 6, iclass 14, count 2 2006.173.08:34:57.03#ibcon#read 6, iclass 14, count 2 2006.173.08:34:57.03#ibcon#end of sib2, iclass 14, count 2 2006.173.08:34:57.03#ibcon#*after write, iclass 14, count 2 2006.173.08:34:57.03#ibcon#*before return 0, iclass 14, count 2 2006.173.08:34:57.03#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.08:34:57.03#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.08:34:57.03#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.08:34:57.03#ibcon#ireg 7 cls_cnt 0 2006.173.08:34:57.03#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.08:34:57.15#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.08:34:57.15#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.08:34:57.15#ibcon#enter wrdev, iclass 14, count 0 2006.173.08:34:57.15#ibcon#first serial, iclass 14, count 0 2006.173.08:34:57.15#ibcon#enter sib2, iclass 14, count 0 2006.173.08:34:57.15#ibcon#flushed, iclass 14, count 0 2006.173.08:34:57.15#ibcon#about to write, iclass 14, count 0 2006.173.08:34:57.15#ibcon#wrote, iclass 14, count 0 2006.173.08:34:57.15#ibcon#about to read 3, iclass 14, count 0 2006.173.08:34:57.17#ibcon#read 3, iclass 14, count 0 2006.173.08:34:57.17#ibcon#about to read 4, iclass 14, count 0 2006.173.08:34:57.17#ibcon#read 4, iclass 14, count 0 2006.173.08:34:57.17#ibcon#about to read 5, iclass 14, count 0 2006.173.08:34:57.17#ibcon#read 5, iclass 14, count 0 2006.173.08:34:57.17#ibcon#about to read 6, iclass 14, count 0 2006.173.08:34:57.17#ibcon#read 6, iclass 14, count 0 2006.173.08:34:57.17#ibcon#end of sib2, iclass 14, count 0 2006.173.08:34:57.17#ibcon#*mode == 0, iclass 14, count 0 2006.173.08:34:57.17#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.08:34:57.17#ibcon#[25=USB\r\n] 2006.173.08:34:57.17#ibcon#*before write, iclass 14, count 0 2006.173.08:34:57.17#ibcon#enter sib2, iclass 14, count 0 2006.173.08:34:57.17#ibcon#flushed, iclass 14, count 0 2006.173.08:34:57.17#ibcon#about to write, iclass 14, count 0 2006.173.08:34:57.17#ibcon#wrote, iclass 14, count 0 2006.173.08:34:57.17#ibcon#about to read 3, iclass 14, count 0 2006.173.08:34:57.20#ibcon#read 3, iclass 14, count 0 2006.173.08:34:57.20#ibcon#about to read 4, iclass 14, count 0 2006.173.08:34:57.20#ibcon#read 4, iclass 14, count 0 2006.173.08:34:57.20#ibcon#about to read 5, iclass 14, count 0 2006.173.08:34:57.20#ibcon#read 5, iclass 14, count 0 2006.173.08:34:57.20#ibcon#about to read 6, iclass 14, count 0 2006.173.08:34:57.20#ibcon#read 6, iclass 14, count 0 2006.173.08:34:57.20#ibcon#end of sib2, iclass 14, count 0 2006.173.08:34:57.20#ibcon#*after write, iclass 14, count 0 2006.173.08:34:57.20#ibcon#*before return 0, iclass 14, count 0 2006.173.08:34:57.20#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.08:34:57.20#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.08:34:57.20#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.08:34:57.20#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.08:34:57.20$vck44/valo=4,624.99 2006.173.08:34:57.20#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.08:34:57.20#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.08:34:57.20#ibcon#ireg 17 cls_cnt 0 2006.173.08:34:57.20#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.08:34:57.20#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.08:34:57.20#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.08:34:57.20#ibcon#enter wrdev, iclass 16, count 0 2006.173.08:34:57.20#ibcon#first serial, iclass 16, count 0 2006.173.08:34:57.20#ibcon#enter sib2, iclass 16, count 0 2006.173.08:34:57.20#ibcon#flushed, iclass 16, count 0 2006.173.08:34:57.20#ibcon#about to write, iclass 16, count 0 2006.173.08:34:57.20#ibcon#wrote, iclass 16, count 0 2006.173.08:34:57.20#ibcon#about to read 3, iclass 16, count 0 2006.173.08:34:57.22#ibcon#read 3, iclass 16, count 0 2006.173.08:34:57.22#ibcon#about to read 4, iclass 16, count 0 2006.173.08:34:57.22#ibcon#read 4, iclass 16, count 0 2006.173.08:34:57.22#ibcon#about to read 5, iclass 16, count 0 2006.173.08:34:57.22#ibcon#read 5, iclass 16, count 0 2006.173.08:34:57.22#ibcon#about to read 6, iclass 16, count 0 2006.173.08:34:57.22#ibcon#read 6, iclass 16, count 0 2006.173.08:34:57.22#ibcon#end of sib2, iclass 16, count 0 2006.173.08:34:57.22#ibcon#*mode == 0, iclass 16, count 0 2006.173.08:34:57.22#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.08:34:57.22#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.08:34:57.22#ibcon#*before write, iclass 16, count 0 2006.173.08:34:57.22#ibcon#enter sib2, iclass 16, count 0 2006.173.08:34:57.22#ibcon#flushed, iclass 16, count 0 2006.173.08:34:57.22#ibcon#about to write, iclass 16, count 0 2006.173.08:34:57.22#ibcon#wrote, iclass 16, count 0 2006.173.08:34:57.22#ibcon#about to read 3, iclass 16, count 0 2006.173.08:34:57.26#ibcon#read 3, iclass 16, count 0 2006.173.08:34:57.26#ibcon#about to read 4, iclass 16, count 0 2006.173.08:34:57.26#ibcon#read 4, iclass 16, count 0 2006.173.08:34:57.26#ibcon#about to read 5, iclass 16, count 0 2006.173.08:34:57.26#ibcon#read 5, iclass 16, count 0 2006.173.08:34:57.26#ibcon#about to read 6, iclass 16, count 0 2006.173.08:34:57.26#ibcon#read 6, iclass 16, count 0 2006.173.08:34:57.26#ibcon#end of sib2, iclass 16, count 0 2006.173.08:34:57.26#ibcon#*after write, iclass 16, count 0 2006.173.08:34:57.26#ibcon#*before return 0, iclass 16, count 0 2006.173.08:34:57.26#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.08:34:57.26#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.08:34:57.26#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.08:34:57.26#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.08:34:57.26$vck44/va=4,6 2006.173.08:34:57.26#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.08:34:57.26#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.08:34:57.26#ibcon#ireg 11 cls_cnt 2 2006.173.08:34:57.26#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.08:34:57.32#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.08:34:57.32#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.08:34:57.32#ibcon#enter wrdev, iclass 18, count 2 2006.173.08:34:57.32#ibcon#first serial, iclass 18, count 2 2006.173.08:34:57.32#ibcon#enter sib2, iclass 18, count 2 2006.173.08:34:57.32#ibcon#flushed, iclass 18, count 2 2006.173.08:34:57.32#ibcon#about to write, iclass 18, count 2 2006.173.08:34:57.32#ibcon#wrote, iclass 18, count 2 2006.173.08:34:57.32#ibcon#about to read 3, iclass 18, count 2 2006.173.08:34:57.34#ibcon#read 3, iclass 18, count 2 2006.173.08:34:57.34#ibcon#about to read 4, iclass 18, count 2 2006.173.08:34:57.34#ibcon#read 4, iclass 18, count 2 2006.173.08:34:57.34#ibcon#about to read 5, iclass 18, count 2 2006.173.08:34:57.34#ibcon#read 5, iclass 18, count 2 2006.173.08:34:57.34#ibcon#about to read 6, iclass 18, count 2 2006.173.08:34:57.34#ibcon#read 6, iclass 18, count 2 2006.173.08:34:57.34#ibcon#end of sib2, iclass 18, count 2 2006.173.08:34:57.34#ibcon#*mode == 0, iclass 18, count 2 2006.173.08:34:57.34#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.08:34:57.34#ibcon#[25=AT04-06\r\n] 2006.173.08:34:57.34#ibcon#*before write, iclass 18, count 2 2006.173.08:34:57.34#ibcon#enter sib2, iclass 18, count 2 2006.173.08:34:57.34#ibcon#flushed, iclass 18, count 2 2006.173.08:34:57.34#ibcon#about to write, iclass 18, count 2 2006.173.08:34:57.34#ibcon#wrote, iclass 18, count 2 2006.173.08:34:57.34#ibcon#about to read 3, iclass 18, count 2 2006.173.08:34:57.37#ibcon#read 3, iclass 18, count 2 2006.173.08:34:57.37#ibcon#about to read 4, iclass 18, count 2 2006.173.08:34:57.37#ibcon#read 4, iclass 18, count 2 2006.173.08:34:57.37#ibcon#about to read 5, iclass 18, count 2 2006.173.08:34:57.37#ibcon#read 5, iclass 18, count 2 2006.173.08:34:57.37#ibcon#about to read 6, iclass 18, count 2 2006.173.08:34:57.37#ibcon#read 6, iclass 18, count 2 2006.173.08:34:57.37#ibcon#end of sib2, iclass 18, count 2 2006.173.08:34:57.37#ibcon#*after write, iclass 18, count 2 2006.173.08:34:57.37#ibcon#*before return 0, iclass 18, count 2 2006.173.08:34:57.37#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.08:34:57.37#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.08:34:57.37#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.08:34:57.37#ibcon#ireg 7 cls_cnt 0 2006.173.08:34:57.37#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.08:34:57.49#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.08:34:57.49#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.08:34:57.49#ibcon#enter wrdev, iclass 18, count 0 2006.173.08:34:57.49#ibcon#first serial, iclass 18, count 0 2006.173.08:34:57.49#ibcon#enter sib2, iclass 18, count 0 2006.173.08:34:57.49#ibcon#flushed, iclass 18, count 0 2006.173.08:34:57.49#ibcon#about to write, iclass 18, count 0 2006.173.08:34:57.49#ibcon#wrote, iclass 18, count 0 2006.173.08:34:57.49#ibcon#about to read 3, iclass 18, count 0 2006.173.08:34:57.51#ibcon#read 3, iclass 18, count 0 2006.173.08:34:57.51#ibcon#about to read 4, iclass 18, count 0 2006.173.08:34:57.51#ibcon#read 4, iclass 18, count 0 2006.173.08:34:57.51#ibcon#about to read 5, iclass 18, count 0 2006.173.08:34:57.51#ibcon#read 5, iclass 18, count 0 2006.173.08:34:57.51#ibcon#about to read 6, iclass 18, count 0 2006.173.08:34:57.51#ibcon#read 6, iclass 18, count 0 2006.173.08:34:57.51#ibcon#end of sib2, iclass 18, count 0 2006.173.08:34:57.51#ibcon#*mode == 0, iclass 18, count 0 2006.173.08:34:57.51#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.08:34:57.51#ibcon#[25=USB\r\n] 2006.173.08:34:57.51#ibcon#*before write, iclass 18, count 0 2006.173.08:34:57.51#ibcon#enter sib2, iclass 18, count 0 2006.173.08:34:57.51#ibcon#flushed, iclass 18, count 0 2006.173.08:34:57.51#ibcon#about to write, iclass 18, count 0 2006.173.08:34:57.51#ibcon#wrote, iclass 18, count 0 2006.173.08:34:57.51#ibcon#about to read 3, iclass 18, count 0 2006.173.08:34:57.54#ibcon#read 3, iclass 18, count 0 2006.173.08:34:57.54#ibcon#about to read 4, iclass 18, count 0 2006.173.08:34:57.54#ibcon#read 4, iclass 18, count 0 2006.173.08:34:57.54#ibcon#about to read 5, iclass 18, count 0 2006.173.08:34:57.54#ibcon#read 5, iclass 18, count 0 2006.173.08:34:57.54#ibcon#about to read 6, iclass 18, count 0 2006.173.08:34:57.54#ibcon#read 6, iclass 18, count 0 2006.173.08:34:57.54#ibcon#end of sib2, iclass 18, count 0 2006.173.08:34:57.54#ibcon#*after write, iclass 18, count 0 2006.173.08:34:57.54#ibcon#*before return 0, iclass 18, count 0 2006.173.08:34:57.54#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.08:34:57.54#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.08:34:57.54#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.08:34:57.54#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.08:34:57.54$vck44/valo=5,734.99 2006.173.08:34:57.54#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.08:34:57.54#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.08:34:57.54#ibcon#ireg 17 cls_cnt 0 2006.173.08:34:57.54#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.08:34:57.54#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.08:34:57.54#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.08:34:57.54#ibcon#enter wrdev, iclass 20, count 0 2006.173.08:34:57.54#ibcon#first serial, iclass 20, count 0 2006.173.08:34:57.54#ibcon#enter sib2, iclass 20, count 0 2006.173.08:34:57.54#ibcon#flushed, iclass 20, count 0 2006.173.08:34:57.54#ibcon#about to write, iclass 20, count 0 2006.173.08:34:57.54#ibcon#wrote, iclass 20, count 0 2006.173.08:34:57.54#ibcon#about to read 3, iclass 20, count 0 2006.173.08:34:57.56#ibcon#read 3, iclass 20, count 0 2006.173.08:34:57.56#ibcon#about to read 4, iclass 20, count 0 2006.173.08:34:57.56#ibcon#read 4, iclass 20, count 0 2006.173.08:34:57.56#ibcon#about to read 5, iclass 20, count 0 2006.173.08:34:57.56#ibcon#read 5, iclass 20, count 0 2006.173.08:34:57.56#ibcon#about to read 6, iclass 20, count 0 2006.173.08:34:57.56#ibcon#read 6, iclass 20, count 0 2006.173.08:34:57.56#ibcon#end of sib2, iclass 20, count 0 2006.173.08:34:57.56#ibcon#*mode == 0, iclass 20, count 0 2006.173.08:34:57.56#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.08:34:57.56#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.08:34:57.56#ibcon#*before write, iclass 20, count 0 2006.173.08:34:57.56#ibcon#enter sib2, iclass 20, count 0 2006.173.08:34:57.56#ibcon#flushed, iclass 20, count 0 2006.173.08:34:57.56#ibcon#about to write, iclass 20, count 0 2006.173.08:34:57.56#ibcon#wrote, iclass 20, count 0 2006.173.08:34:57.56#ibcon#about to read 3, iclass 20, count 0 2006.173.08:34:57.60#ibcon#read 3, iclass 20, count 0 2006.173.08:34:57.60#ibcon#about to read 4, iclass 20, count 0 2006.173.08:34:57.60#ibcon#read 4, iclass 20, count 0 2006.173.08:34:57.60#ibcon#about to read 5, iclass 20, count 0 2006.173.08:34:57.60#ibcon#read 5, iclass 20, count 0 2006.173.08:34:57.60#ibcon#about to read 6, iclass 20, count 0 2006.173.08:34:57.60#ibcon#read 6, iclass 20, count 0 2006.173.08:34:57.60#ibcon#end of sib2, iclass 20, count 0 2006.173.08:34:57.60#ibcon#*after write, iclass 20, count 0 2006.173.08:34:57.60#ibcon#*before return 0, iclass 20, count 0 2006.173.08:34:57.60#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.08:34:57.60#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.08:34:57.60#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.08:34:57.60#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.08:34:57.60$vck44/va=5,4 2006.173.08:34:57.60#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.08:34:57.60#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.08:34:57.60#ibcon#ireg 11 cls_cnt 2 2006.173.08:34:57.60#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.08:34:57.66#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.08:34:57.66#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.08:34:57.66#ibcon#enter wrdev, iclass 22, count 2 2006.173.08:34:57.66#ibcon#first serial, iclass 22, count 2 2006.173.08:34:57.66#ibcon#enter sib2, iclass 22, count 2 2006.173.08:34:57.66#ibcon#flushed, iclass 22, count 2 2006.173.08:34:57.66#ibcon#about to write, iclass 22, count 2 2006.173.08:34:57.66#ibcon#wrote, iclass 22, count 2 2006.173.08:34:57.66#ibcon#about to read 3, iclass 22, count 2 2006.173.08:34:57.68#ibcon#read 3, iclass 22, count 2 2006.173.08:34:57.68#ibcon#about to read 4, iclass 22, count 2 2006.173.08:34:57.68#ibcon#read 4, iclass 22, count 2 2006.173.08:34:57.68#ibcon#about to read 5, iclass 22, count 2 2006.173.08:34:57.68#ibcon#read 5, iclass 22, count 2 2006.173.08:34:57.68#ibcon#about to read 6, iclass 22, count 2 2006.173.08:34:57.68#ibcon#read 6, iclass 22, count 2 2006.173.08:34:57.68#ibcon#end of sib2, iclass 22, count 2 2006.173.08:34:57.68#ibcon#*mode == 0, iclass 22, count 2 2006.173.08:34:57.68#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.08:34:57.68#ibcon#[25=AT05-04\r\n] 2006.173.08:34:57.68#ibcon#*before write, iclass 22, count 2 2006.173.08:34:57.68#ibcon#enter sib2, iclass 22, count 2 2006.173.08:34:57.68#ibcon#flushed, iclass 22, count 2 2006.173.08:34:57.68#ibcon#about to write, iclass 22, count 2 2006.173.08:34:57.68#ibcon#wrote, iclass 22, count 2 2006.173.08:34:57.68#ibcon#about to read 3, iclass 22, count 2 2006.173.08:34:57.71#ibcon#read 3, iclass 22, count 2 2006.173.08:34:57.71#ibcon#about to read 4, iclass 22, count 2 2006.173.08:34:57.71#ibcon#read 4, iclass 22, count 2 2006.173.08:34:57.71#ibcon#about to read 5, iclass 22, count 2 2006.173.08:34:57.71#ibcon#read 5, iclass 22, count 2 2006.173.08:34:57.71#ibcon#about to read 6, iclass 22, count 2 2006.173.08:34:57.71#ibcon#read 6, iclass 22, count 2 2006.173.08:34:57.71#ibcon#end of sib2, iclass 22, count 2 2006.173.08:34:57.71#ibcon#*after write, iclass 22, count 2 2006.173.08:34:57.71#ibcon#*before return 0, iclass 22, count 2 2006.173.08:34:57.71#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.08:34:57.71#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.08:34:57.71#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.08:34:57.71#ibcon#ireg 7 cls_cnt 0 2006.173.08:34:57.71#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.08:34:57.83#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.08:34:57.83#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.08:34:57.83#ibcon#enter wrdev, iclass 22, count 0 2006.173.08:34:57.83#ibcon#first serial, iclass 22, count 0 2006.173.08:34:57.83#ibcon#enter sib2, iclass 22, count 0 2006.173.08:34:57.83#ibcon#flushed, iclass 22, count 0 2006.173.08:34:57.83#ibcon#about to write, iclass 22, count 0 2006.173.08:34:57.83#ibcon#wrote, iclass 22, count 0 2006.173.08:34:57.83#ibcon#about to read 3, iclass 22, count 0 2006.173.08:34:57.85#ibcon#read 3, iclass 22, count 0 2006.173.08:34:57.85#ibcon#about to read 4, iclass 22, count 0 2006.173.08:34:57.85#ibcon#read 4, iclass 22, count 0 2006.173.08:34:57.85#ibcon#about to read 5, iclass 22, count 0 2006.173.08:34:57.85#ibcon#read 5, iclass 22, count 0 2006.173.08:34:57.85#ibcon#about to read 6, iclass 22, count 0 2006.173.08:34:57.85#ibcon#read 6, iclass 22, count 0 2006.173.08:34:57.85#ibcon#end of sib2, iclass 22, count 0 2006.173.08:34:57.85#ibcon#*mode == 0, iclass 22, count 0 2006.173.08:34:57.85#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.08:34:57.85#ibcon#[25=USB\r\n] 2006.173.08:34:57.85#ibcon#*before write, iclass 22, count 0 2006.173.08:34:57.85#ibcon#enter sib2, iclass 22, count 0 2006.173.08:34:57.85#ibcon#flushed, iclass 22, count 0 2006.173.08:34:57.85#ibcon#about to write, iclass 22, count 0 2006.173.08:34:57.85#ibcon#wrote, iclass 22, count 0 2006.173.08:34:57.85#ibcon#about to read 3, iclass 22, count 0 2006.173.08:34:57.88#ibcon#read 3, iclass 22, count 0 2006.173.08:34:57.88#ibcon#about to read 4, iclass 22, count 0 2006.173.08:34:57.88#ibcon#read 4, iclass 22, count 0 2006.173.08:34:57.88#ibcon#about to read 5, iclass 22, count 0 2006.173.08:34:57.88#ibcon#read 5, iclass 22, count 0 2006.173.08:34:57.88#ibcon#about to read 6, iclass 22, count 0 2006.173.08:34:57.88#ibcon#read 6, iclass 22, count 0 2006.173.08:34:57.88#ibcon#end of sib2, iclass 22, count 0 2006.173.08:34:57.88#ibcon#*after write, iclass 22, count 0 2006.173.08:34:57.88#ibcon#*before return 0, iclass 22, count 0 2006.173.08:34:57.88#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.08:34:57.88#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.08:34:57.88#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.08:34:57.88#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.08:34:57.88$vck44/valo=6,814.99 2006.173.08:34:57.88#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.08:34:57.88#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.08:34:57.88#ibcon#ireg 17 cls_cnt 0 2006.173.08:34:57.88#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.08:34:57.88#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.08:34:57.88#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.08:34:57.88#ibcon#enter wrdev, iclass 24, count 0 2006.173.08:34:57.88#ibcon#first serial, iclass 24, count 0 2006.173.08:34:57.88#ibcon#enter sib2, iclass 24, count 0 2006.173.08:34:57.88#ibcon#flushed, iclass 24, count 0 2006.173.08:34:57.88#ibcon#about to write, iclass 24, count 0 2006.173.08:34:57.88#ibcon#wrote, iclass 24, count 0 2006.173.08:34:57.88#ibcon#about to read 3, iclass 24, count 0 2006.173.08:34:57.90#ibcon#read 3, iclass 24, count 0 2006.173.08:34:57.90#ibcon#about to read 4, iclass 24, count 0 2006.173.08:34:57.90#ibcon#read 4, iclass 24, count 0 2006.173.08:34:57.90#ibcon#about to read 5, iclass 24, count 0 2006.173.08:34:57.90#ibcon#read 5, iclass 24, count 0 2006.173.08:34:57.90#ibcon#about to read 6, iclass 24, count 0 2006.173.08:34:57.90#ibcon#read 6, iclass 24, count 0 2006.173.08:34:57.90#ibcon#end of sib2, iclass 24, count 0 2006.173.08:34:57.90#ibcon#*mode == 0, iclass 24, count 0 2006.173.08:34:57.90#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.08:34:57.90#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.08:34:57.90#ibcon#*before write, iclass 24, count 0 2006.173.08:34:57.90#ibcon#enter sib2, iclass 24, count 0 2006.173.08:34:57.90#ibcon#flushed, iclass 24, count 0 2006.173.08:34:57.90#ibcon#about to write, iclass 24, count 0 2006.173.08:34:57.90#ibcon#wrote, iclass 24, count 0 2006.173.08:34:57.90#ibcon#about to read 3, iclass 24, count 0 2006.173.08:34:57.94#ibcon#read 3, iclass 24, count 0 2006.173.08:34:57.94#ibcon#about to read 4, iclass 24, count 0 2006.173.08:34:57.94#ibcon#read 4, iclass 24, count 0 2006.173.08:34:57.94#ibcon#about to read 5, iclass 24, count 0 2006.173.08:34:57.94#ibcon#read 5, iclass 24, count 0 2006.173.08:34:57.94#ibcon#about to read 6, iclass 24, count 0 2006.173.08:34:57.94#ibcon#read 6, iclass 24, count 0 2006.173.08:34:57.94#ibcon#end of sib2, iclass 24, count 0 2006.173.08:34:57.94#ibcon#*after write, iclass 24, count 0 2006.173.08:34:57.94#ibcon#*before return 0, iclass 24, count 0 2006.173.08:34:57.94#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.08:34:57.94#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.08:34:57.94#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.08:34:57.94#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.08:34:57.94$vck44/va=6,3 2006.173.08:34:57.94#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.08:34:57.94#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.08:34:57.94#ibcon#ireg 11 cls_cnt 2 2006.173.08:34:57.94#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.08:34:58.00#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.08:34:58.00#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.08:34:58.00#ibcon#enter wrdev, iclass 26, count 2 2006.173.08:34:58.00#ibcon#first serial, iclass 26, count 2 2006.173.08:34:58.00#ibcon#enter sib2, iclass 26, count 2 2006.173.08:34:58.00#ibcon#flushed, iclass 26, count 2 2006.173.08:34:58.00#ibcon#about to write, iclass 26, count 2 2006.173.08:34:58.00#ibcon#wrote, iclass 26, count 2 2006.173.08:34:58.00#ibcon#about to read 3, iclass 26, count 2 2006.173.08:34:58.02#ibcon#read 3, iclass 26, count 2 2006.173.08:34:58.02#ibcon#about to read 4, iclass 26, count 2 2006.173.08:34:58.02#ibcon#read 4, iclass 26, count 2 2006.173.08:34:58.02#ibcon#about to read 5, iclass 26, count 2 2006.173.08:34:58.02#ibcon#read 5, iclass 26, count 2 2006.173.08:34:58.02#ibcon#about to read 6, iclass 26, count 2 2006.173.08:34:58.02#ibcon#read 6, iclass 26, count 2 2006.173.08:34:58.02#ibcon#end of sib2, iclass 26, count 2 2006.173.08:34:58.02#ibcon#*mode == 0, iclass 26, count 2 2006.173.08:34:58.02#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.08:34:58.02#ibcon#[25=AT06-03\r\n] 2006.173.08:34:58.02#ibcon#*before write, iclass 26, count 2 2006.173.08:34:58.02#ibcon#enter sib2, iclass 26, count 2 2006.173.08:34:58.02#ibcon#flushed, iclass 26, count 2 2006.173.08:34:58.02#ibcon#about to write, iclass 26, count 2 2006.173.08:34:58.02#ibcon#wrote, iclass 26, count 2 2006.173.08:34:58.02#ibcon#about to read 3, iclass 26, count 2 2006.173.08:34:58.05#ibcon#read 3, iclass 26, count 2 2006.173.08:34:58.05#ibcon#about to read 4, iclass 26, count 2 2006.173.08:34:58.05#ibcon#read 4, iclass 26, count 2 2006.173.08:34:58.05#ibcon#about to read 5, iclass 26, count 2 2006.173.08:34:58.05#ibcon#read 5, iclass 26, count 2 2006.173.08:34:58.05#ibcon#about to read 6, iclass 26, count 2 2006.173.08:34:58.05#ibcon#read 6, iclass 26, count 2 2006.173.08:34:58.05#ibcon#end of sib2, iclass 26, count 2 2006.173.08:34:58.05#ibcon#*after write, iclass 26, count 2 2006.173.08:34:58.05#ibcon#*before return 0, iclass 26, count 2 2006.173.08:34:58.05#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.08:34:58.05#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.08:34:58.05#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.08:34:58.05#ibcon#ireg 7 cls_cnt 0 2006.173.08:34:58.05#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.08:34:58.17#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.08:34:58.17#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.08:34:58.17#ibcon#enter wrdev, iclass 26, count 0 2006.173.08:34:58.17#ibcon#first serial, iclass 26, count 0 2006.173.08:34:58.17#ibcon#enter sib2, iclass 26, count 0 2006.173.08:34:58.17#ibcon#flushed, iclass 26, count 0 2006.173.08:34:58.17#ibcon#about to write, iclass 26, count 0 2006.173.08:34:58.17#ibcon#wrote, iclass 26, count 0 2006.173.08:34:58.17#ibcon#about to read 3, iclass 26, count 0 2006.173.08:34:58.19#ibcon#read 3, iclass 26, count 0 2006.173.08:34:58.19#ibcon#about to read 4, iclass 26, count 0 2006.173.08:34:58.19#ibcon#read 4, iclass 26, count 0 2006.173.08:34:58.19#ibcon#about to read 5, iclass 26, count 0 2006.173.08:34:58.19#ibcon#read 5, iclass 26, count 0 2006.173.08:34:58.19#ibcon#about to read 6, iclass 26, count 0 2006.173.08:34:58.19#ibcon#read 6, iclass 26, count 0 2006.173.08:34:58.19#ibcon#end of sib2, iclass 26, count 0 2006.173.08:34:58.19#ibcon#*mode == 0, iclass 26, count 0 2006.173.08:34:58.19#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.08:34:58.19#ibcon#[25=USB\r\n] 2006.173.08:34:58.19#ibcon#*before write, iclass 26, count 0 2006.173.08:34:58.19#ibcon#enter sib2, iclass 26, count 0 2006.173.08:34:58.19#ibcon#flushed, iclass 26, count 0 2006.173.08:34:58.19#ibcon#about to write, iclass 26, count 0 2006.173.08:34:58.19#ibcon#wrote, iclass 26, count 0 2006.173.08:34:58.19#ibcon#about to read 3, iclass 26, count 0 2006.173.08:34:58.22#ibcon#read 3, iclass 26, count 0 2006.173.08:34:58.22#ibcon#about to read 4, iclass 26, count 0 2006.173.08:34:58.22#ibcon#read 4, iclass 26, count 0 2006.173.08:34:58.22#ibcon#about to read 5, iclass 26, count 0 2006.173.08:34:58.22#ibcon#read 5, iclass 26, count 0 2006.173.08:34:58.22#ibcon#about to read 6, iclass 26, count 0 2006.173.08:34:58.22#ibcon#read 6, iclass 26, count 0 2006.173.08:34:58.22#ibcon#end of sib2, iclass 26, count 0 2006.173.08:34:58.22#ibcon#*after write, iclass 26, count 0 2006.173.08:34:58.22#ibcon#*before return 0, iclass 26, count 0 2006.173.08:34:58.22#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.08:34:58.22#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.08:34:58.22#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.08:34:58.22#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.08:34:58.22$vck44/valo=7,864.99 2006.173.08:34:58.22#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.08:34:58.22#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.08:34:58.22#ibcon#ireg 17 cls_cnt 0 2006.173.08:34:58.22#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.08:34:58.22#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.08:34:58.22#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.08:34:58.22#ibcon#enter wrdev, iclass 28, count 0 2006.173.08:34:58.22#ibcon#first serial, iclass 28, count 0 2006.173.08:34:58.22#ibcon#enter sib2, iclass 28, count 0 2006.173.08:34:58.22#ibcon#flushed, iclass 28, count 0 2006.173.08:34:58.22#ibcon#about to write, iclass 28, count 0 2006.173.08:34:58.22#ibcon#wrote, iclass 28, count 0 2006.173.08:34:58.22#ibcon#about to read 3, iclass 28, count 0 2006.173.08:34:58.24#ibcon#read 3, iclass 28, count 0 2006.173.08:34:58.24#ibcon#about to read 4, iclass 28, count 0 2006.173.08:34:58.24#ibcon#read 4, iclass 28, count 0 2006.173.08:34:58.24#ibcon#about to read 5, iclass 28, count 0 2006.173.08:34:58.24#ibcon#read 5, iclass 28, count 0 2006.173.08:34:58.24#ibcon#about to read 6, iclass 28, count 0 2006.173.08:34:58.24#ibcon#read 6, iclass 28, count 0 2006.173.08:34:58.24#ibcon#end of sib2, iclass 28, count 0 2006.173.08:34:58.24#ibcon#*mode == 0, iclass 28, count 0 2006.173.08:34:58.24#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.08:34:58.24#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.08:34:58.24#ibcon#*before write, iclass 28, count 0 2006.173.08:34:58.24#ibcon#enter sib2, iclass 28, count 0 2006.173.08:34:58.24#ibcon#flushed, iclass 28, count 0 2006.173.08:34:58.24#ibcon#about to write, iclass 28, count 0 2006.173.08:34:58.24#ibcon#wrote, iclass 28, count 0 2006.173.08:34:58.24#ibcon#about to read 3, iclass 28, count 0 2006.173.08:34:58.28#ibcon#read 3, iclass 28, count 0 2006.173.08:34:58.28#ibcon#about to read 4, iclass 28, count 0 2006.173.08:34:58.28#ibcon#read 4, iclass 28, count 0 2006.173.08:34:58.28#ibcon#about to read 5, iclass 28, count 0 2006.173.08:34:58.28#ibcon#read 5, iclass 28, count 0 2006.173.08:34:58.28#ibcon#about to read 6, iclass 28, count 0 2006.173.08:34:58.28#ibcon#read 6, iclass 28, count 0 2006.173.08:34:58.28#ibcon#end of sib2, iclass 28, count 0 2006.173.08:34:58.28#ibcon#*after write, iclass 28, count 0 2006.173.08:34:58.28#ibcon#*before return 0, iclass 28, count 0 2006.173.08:34:58.28#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.08:34:58.28#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.08:34:58.28#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.08:34:58.28#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.08:34:58.28$vck44/va=7,4 2006.173.08:34:58.28#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.08:34:58.28#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.08:34:58.28#ibcon#ireg 11 cls_cnt 2 2006.173.08:34:58.28#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.08:34:58.34#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.08:34:58.34#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.08:34:58.34#ibcon#enter wrdev, iclass 30, count 2 2006.173.08:34:58.34#ibcon#first serial, iclass 30, count 2 2006.173.08:34:58.34#ibcon#enter sib2, iclass 30, count 2 2006.173.08:34:58.34#ibcon#flushed, iclass 30, count 2 2006.173.08:34:58.34#ibcon#about to write, iclass 30, count 2 2006.173.08:34:58.34#ibcon#wrote, iclass 30, count 2 2006.173.08:34:58.34#ibcon#about to read 3, iclass 30, count 2 2006.173.08:34:58.36#ibcon#read 3, iclass 30, count 2 2006.173.08:34:58.36#ibcon#about to read 4, iclass 30, count 2 2006.173.08:34:58.36#ibcon#read 4, iclass 30, count 2 2006.173.08:34:58.36#ibcon#about to read 5, iclass 30, count 2 2006.173.08:34:58.36#ibcon#read 5, iclass 30, count 2 2006.173.08:34:58.36#ibcon#about to read 6, iclass 30, count 2 2006.173.08:34:58.36#ibcon#read 6, iclass 30, count 2 2006.173.08:34:58.36#ibcon#end of sib2, iclass 30, count 2 2006.173.08:34:58.36#ibcon#*mode == 0, iclass 30, count 2 2006.173.08:34:58.36#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.08:34:58.36#ibcon#[25=AT07-04\r\n] 2006.173.08:34:58.36#ibcon#*before write, iclass 30, count 2 2006.173.08:34:58.36#ibcon#enter sib2, iclass 30, count 2 2006.173.08:34:58.36#ibcon#flushed, iclass 30, count 2 2006.173.08:34:58.36#ibcon#about to write, iclass 30, count 2 2006.173.08:34:58.36#ibcon#wrote, iclass 30, count 2 2006.173.08:34:58.36#ibcon#about to read 3, iclass 30, count 2 2006.173.08:34:58.39#ibcon#read 3, iclass 30, count 2 2006.173.08:34:58.39#ibcon#about to read 4, iclass 30, count 2 2006.173.08:34:58.39#ibcon#read 4, iclass 30, count 2 2006.173.08:34:58.39#ibcon#about to read 5, iclass 30, count 2 2006.173.08:34:58.39#ibcon#read 5, iclass 30, count 2 2006.173.08:34:58.39#ibcon#about to read 6, iclass 30, count 2 2006.173.08:34:58.39#ibcon#read 6, iclass 30, count 2 2006.173.08:34:58.39#ibcon#end of sib2, iclass 30, count 2 2006.173.08:34:58.39#ibcon#*after write, iclass 30, count 2 2006.173.08:34:58.39#ibcon#*before return 0, iclass 30, count 2 2006.173.08:34:58.39#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.08:34:58.39#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.08:34:58.39#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.08:34:58.39#ibcon#ireg 7 cls_cnt 0 2006.173.08:34:58.39#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.08:34:58.51#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.08:34:58.51#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.08:34:58.51#ibcon#enter wrdev, iclass 30, count 0 2006.173.08:34:58.51#ibcon#first serial, iclass 30, count 0 2006.173.08:34:58.51#ibcon#enter sib2, iclass 30, count 0 2006.173.08:34:58.51#ibcon#flushed, iclass 30, count 0 2006.173.08:34:58.51#ibcon#about to write, iclass 30, count 0 2006.173.08:34:58.51#ibcon#wrote, iclass 30, count 0 2006.173.08:34:58.51#ibcon#about to read 3, iclass 30, count 0 2006.173.08:34:58.53#ibcon#read 3, iclass 30, count 0 2006.173.08:34:58.53#ibcon#about to read 4, iclass 30, count 0 2006.173.08:34:58.53#ibcon#read 4, iclass 30, count 0 2006.173.08:34:58.53#ibcon#about to read 5, iclass 30, count 0 2006.173.08:34:58.53#ibcon#read 5, iclass 30, count 0 2006.173.08:34:58.53#ibcon#about to read 6, iclass 30, count 0 2006.173.08:34:58.53#ibcon#read 6, iclass 30, count 0 2006.173.08:34:58.53#ibcon#end of sib2, iclass 30, count 0 2006.173.08:34:58.53#ibcon#*mode == 0, iclass 30, count 0 2006.173.08:34:58.53#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.08:34:58.53#ibcon#[25=USB\r\n] 2006.173.08:34:58.53#ibcon#*before write, iclass 30, count 0 2006.173.08:34:58.53#ibcon#enter sib2, iclass 30, count 0 2006.173.08:34:58.53#ibcon#flushed, iclass 30, count 0 2006.173.08:34:58.53#ibcon#about to write, iclass 30, count 0 2006.173.08:34:58.53#ibcon#wrote, iclass 30, count 0 2006.173.08:34:58.53#ibcon#about to read 3, iclass 30, count 0 2006.173.08:34:58.56#ibcon#read 3, iclass 30, count 0 2006.173.08:34:58.56#ibcon#about to read 4, iclass 30, count 0 2006.173.08:34:58.56#ibcon#read 4, iclass 30, count 0 2006.173.08:34:58.56#ibcon#about to read 5, iclass 30, count 0 2006.173.08:34:58.56#ibcon#read 5, iclass 30, count 0 2006.173.08:34:58.56#ibcon#about to read 6, iclass 30, count 0 2006.173.08:34:58.56#ibcon#read 6, iclass 30, count 0 2006.173.08:34:58.56#ibcon#end of sib2, iclass 30, count 0 2006.173.08:34:58.56#ibcon#*after write, iclass 30, count 0 2006.173.08:34:58.56#ibcon#*before return 0, iclass 30, count 0 2006.173.08:34:58.56#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.08:34:58.56#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.08:34:58.56#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.08:34:58.56#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.08:34:58.56$vck44/valo=8,884.99 2006.173.08:34:58.56#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.08:34:58.56#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.08:34:58.56#ibcon#ireg 17 cls_cnt 0 2006.173.08:34:58.56#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.08:34:58.56#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.08:34:58.56#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.08:34:58.56#ibcon#enter wrdev, iclass 32, count 0 2006.173.08:34:58.56#ibcon#first serial, iclass 32, count 0 2006.173.08:34:58.56#ibcon#enter sib2, iclass 32, count 0 2006.173.08:34:58.56#ibcon#flushed, iclass 32, count 0 2006.173.08:34:58.56#ibcon#about to write, iclass 32, count 0 2006.173.08:34:58.56#ibcon#wrote, iclass 32, count 0 2006.173.08:34:58.56#ibcon#about to read 3, iclass 32, count 0 2006.173.08:34:58.58#ibcon#read 3, iclass 32, count 0 2006.173.08:34:58.58#ibcon#about to read 4, iclass 32, count 0 2006.173.08:34:58.58#ibcon#read 4, iclass 32, count 0 2006.173.08:34:58.58#ibcon#about to read 5, iclass 32, count 0 2006.173.08:34:58.58#ibcon#read 5, iclass 32, count 0 2006.173.08:34:58.58#ibcon#about to read 6, iclass 32, count 0 2006.173.08:34:58.58#ibcon#read 6, iclass 32, count 0 2006.173.08:34:58.58#ibcon#end of sib2, iclass 32, count 0 2006.173.08:34:58.58#ibcon#*mode == 0, iclass 32, count 0 2006.173.08:34:58.58#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.08:34:58.58#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.08:34:58.58#ibcon#*before write, iclass 32, count 0 2006.173.08:34:58.58#ibcon#enter sib2, iclass 32, count 0 2006.173.08:34:58.58#ibcon#flushed, iclass 32, count 0 2006.173.08:34:58.58#ibcon#about to write, iclass 32, count 0 2006.173.08:34:58.58#ibcon#wrote, iclass 32, count 0 2006.173.08:34:58.58#ibcon#about to read 3, iclass 32, count 0 2006.173.08:34:58.62#ibcon#read 3, iclass 32, count 0 2006.173.08:34:58.62#ibcon#about to read 4, iclass 32, count 0 2006.173.08:34:58.62#ibcon#read 4, iclass 32, count 0 2006.173.08:34:58.62#ibcon#about to read 5, iclass 32, count 0 2006.173.08:34:58.62#ibcon#read 5, iclass 32, count 0 2006.173.08:34:58.62#ibcon#about to read 6, iclass 32, count 0 2006.173.08:34:58.62#ibcon#read 6, iclass 32, count 0 2006.173.08:34:58.62#ibcon#end of sib2, iclass 32, count 0 2006.173.08:34:58.62#ibcon#*after write, iclass 32, count 0 2006.173.08:34:58.62#ibcon#*before return 0, iclass 32, count 0 2006.173.08:34:58.62#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.08:34:58.62#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.08:34:58.62#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.08:34:58.62#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.08:34:58.62$vck44/va=8,4 2006.173.08:34:58.62#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.08:34:58.62#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.08:34:58.62#ibcon#ireg 11 cls_cnt 2 2006.173.08:34:58.62#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.08:34:58.68#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.08:34:58.68#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.08:34:58.68#ibcon#enter wrdev, iclass 34, count 2 2006.173.08:34:58.68#ibcon#first serial, iclass 34, count 2 2006.173.08:34:58.68#ibcon#enter sib2, iclass 34, count 2 2006.173.08:34:58.68#ibcon#flushed, iclass 34, count 2 2006.173.08:34:58.68#ibcon#about to write, iclass 34, count 2 2006.173.08:34:58.68#ibcon#wrote, iclass 34, count 2 2006.173.08:34:58.68#ibcon#about to read 3, iclass 34, count 2 2006.173.08:34:58.70#ibcon#read 3, iclass 34, count 2 2006.173.08:34:58.70#ibcon#about to read 4, iclass 34, count 2 2006.173.08:34:58.70#ibcon#read 4, iclass 34, count 2 2006.173.08:34:58.70#ibcon#about to read 5, iclass 34, count 2 2006.173.08:34:58.70#ibcon#read 5, iclass 34, count 2 2006.173.08:34:58.70#ibcon#about to read 6, iclass 34, count 2 2006.173.08:34:58.70#ibcon#read 6, iclass 34, count 2 2006.173.08:34:58.70#ibcon#end of sib2, iclass 34, count 2 2006.173.08:34:58.70#ibcon#*mode == 0, iclass 34, count 2 2006.173.08:34:58.70#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.08:34:58.70#ibcon#[25=AT08-04\r\n] 2006.173.08:34:58.70#ibcon#*before write, iclass 34, count 2 2006.173.08:34:58.70#ibcon#enter sib2, iclass 34, count 2 2006.173.08:34:58.70#ibcon#flushed, iclass 34, count 2 2006.173.08:34:58.70#ibcon#about to write, iclass 34, count 2 2006.173.08:34:58.70#ibcon#wrote, iclass 34, count 2 2006.173.08:34:58.70#ibcon#about to read 3, iclass 34, count 2 2006.173.08:34:58.73#ibcon#read 3, iclass 34, count 2 2006.173.08:34:58.73#ibcon#about to read 4, iclass 34, count 2 2006.173.08:34:58.73#ibcon#read 4, iclass 34, count 2 2006.173.08:34:58.73#ibcon#about to read 5, iclass 34, count 2 2006.173.08:34:58.73#ibcon#read 5, iclass 34, count 2 2006.173.08:34:58.73#ibcon#about to read 6, iclass 34, count 2 2006.173.08:34:58.73#ibcon#read 6, iclass 34, count 2 2006.173.08:34:58.73#ibcon#end of sib2, iclass 34, count 2 2006.173.08:34:58.73#ibcon#*after write, iclass 34, count 2 2006.173.08:34:58.73#ibcon#*before return 0, iclass 34, count 2 2006.173.08:34:58.73#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.08:34:58.73#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.08:34:58.73#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.08:34:58.73#ibcon#ireg 7 cls_cnt 0 2006.173.08:34:58.73#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.08:34:58.85#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.08:34:58.85#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.08:34:58.85#ibcon#enter wrdev, iclass 34, count 0 2006.173.08:34:58.85#ibcon#first serial, iclass 34, count 0 2006.173.08:34:58.85#ibcon#enter sib2, iclass 34, count 0 2006.173.08:34:58.85#ibcon#flushed, iclass 34, count 0 2006.173.08:34:58.85#ibcon#about to write, iclass 34, count 0 2006.173.08:34:58.85#ibcon#wrote, iclass 34, count 0 2006.173.08:34:58.85#ibcon#about to read 3, iclass 34, count 0 2006.173.08:34:58.87#ibcon#read 3, iclass 34, count 0 2006.173.08:34:58.87#ibcon#about to read 4, iclass 34, count 0 2006.173.08:34:58.87#ibcon#read 4, iclass 34, count 0 2006.173.08:34:58.87#ibcon#about to read 5, iclass 34, count 0 2006.173.08:34:58.87#ibcon#read 5, iclass 34, count 0 2006.173.08:34:58.87#ibcon#about to read 6, iclass 34, count 0 2006.173.08:34:58.87#ibcon#read 6, iclass 34, count 0 2006.173.08:34:58.87#ibcon#end of sib2, iclass 34, count 0 2006.173.08:34:58.87#ibcon#*mode == 0, iclass 34, count 0 2006.173.08:34:58.87#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.08:34:58.87#ibcon#[25=USB\r\n] 2006.173.08:34:58.87#ibcon#*before write, iclass 34, count 0 2006.173.08:34:58.87#ibcon#enter sib2, iclass 34, count 0 2006.173.08:34:58.87#ibcon#flushed, iclass 34, count 0 2006.173.08:34:58.87#ibcon#about to write, iclass 34, count 0 2006.173.08:34:58.87#ibcon#wrote, iclass 34, count 0 2006.173.08:34:58.87#ibcon#about to read 3, iclass 34, count 0 2006.173.08:34:58.90#ibcon#read 3, iclass 34, count 0 2006.173.08:34:58.90#ibcon#about to read 4, iclass 34, count 0 2006.173.08:34:58.90#ibcon#read 4, iclass 34, count 0 2006.173.08:34:58.90#ibcon#about to read 5, iclass 34, count 0 2006.173.08:34:58.90#ibcon#read 5, iclass 34, count 0 2006.173.08:34:58.90#ibcon#about to read 6, iclass 34, count 0 2006.173.08:34:58.90#ibcon#read 6, iclass 34, count 0 2006.173.08:34:58.90#ibcon#end of sib2, iclass 34, count 0 2006.173.08:34:58.90#ibcon#*after write, iclass 34, count 0 2006.173.08:34:58.90#ibcon#*before return 0, iclass 34, count 0 2006.173.08:34:58.90#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.08:34:58.90#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.08:34:58.90#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.08:34:58.90#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.08:34:58.90$vck44/vblo=1,629.99 2006.173.08:34:58.90#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.08:34:58.90#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.08:34:58.90#ibcon#ireg 17 cls_cnt 0 2006.173.08:34:58.90#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.08:34:58.90#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.08:34:58.90#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.08:34:58.90#ibcon#enter wrdev, iclass 36, count 0 2006.173.08:34:58.90#ibcon#first serial, iclass 36, count 0 2006.173.08:34:58.90#ibcon#enter sib2, iclass 36, count 0 2006.173.08:34:58.90#ibcon#flushed, iclass 36, count 0 2006.173.08:34:58.90#ibcon#about to write, iclass 36, count 0 2006.173.08:34:58.90#ibcon#wrote, iclass 36, count 0 2006.173.08:34:58.90#ibcon#about to read 3, iclass 36, count 0 2006.173.08:34:58.92#ibcon#read 3, iclass 36, count 0 2006.173.08:34:58.92#ibcon#about to read 4, iclass 36, count 0 2006.173.08:34:58.92#ibcon#read 4, iclass 36, count 0 2006.173.08:34:58.92#ibcon#about to read 5, iclass 36, count 0 2006.173.08:34:58.92#ibcon#read 5, iclass 36, count 0 2006.173.08:34:58.92#ibcon#about to read 6, iclass 36, count 0 2006.173.08:34:58.92#ibcon#read 6, iclass 36, count 0 2006.173.08:34:58.92#ibcon#end of sib2, iclass 36, count 0 2006.173.08:34:58.92#ibcon#*mode == 0, iclass 36, count 0 2006.173.08:34:58.92#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.08:34:58.92#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.08:34:58.92#ibcon#*before write, iclass 36, count 0 2006.173.08:34:58.92#ibcon#enter sib2, iclass 36, count 0 2006.173.08:34:58.92#ibcon#flushed, iclass 36, count 0 2006.173.08:34:58.92#ibcon#about to write, iclass 36, count 0 2006.173.08:34:58.92#ibcon#wrote, iclass 36, count 0 2006.173.08:34:58.92#ibcon#about to read 3, iclass 36, count 0 2006.173.08:34:58.96#ibcon#read 3, iclass 36, count 0 2006.173.08:34:58.96#ibcon#about to read 4, iclass 36, count 0 2006.173.08:34:58.96#ibcon#read 4, iclass 36, count 0 2006.173.08:34:58.96#ibcon#about to read 5, iclass 36, count 0 2006.173.08:34:58.96#ibcon#read 5, iclass 36, count 0 2006.173.08:34:58.96#ibcon#about to read 6, iclass 36, count 0 2006.173.08:34:58.96#ibcon#read 6, iclass 36, count 0 2006.173.08:34:58.96#ibcon#end of sib2, iclass 36, count 0 2006.173.08:34:58.96#ibcon#*after write, iclass 36, count 0 2006.173.08:34:58.96#ibcon#*before return 0, iclass 36, count 0 2006.173.08:34:58.96#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.08:34:58.96#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.08:34:58.96#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.08:34:58.96#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.08:34:58.96$vck44/vb=1,4 2006.173.08:34:58.96#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.08:34:58.96#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.08:34:58.96#ibcon#ireg 11 cls_cnt 2 2006.173.08:34:58.96#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.08:34:58.96#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.08:34:58.96#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.08:34:58.96#ibcon#enter wrdev, iclass 38, count 2 2006.173.08:34:58.96#ibcon#first serial, iclass 38, count 2 2006.173.08:34:58.96#ibcon#enter sib2, iclass 38, count 2 2006.173.08:34:58.96#ibcon#flushed, iclass 38, count 2 2006.173.08:34:58.96#ibcon#about to write, iclass 38, count 2 2006.173.08:34:58.96#ibcon#wrote, iclass 38, count 2 2006.173.08:34:58.96#ibcon#about to read 3, iclass 38, count 2 2006.173.08:34:58.98#ibcon#read 3, iclass 38, count 2 2006.173.08:34:58.98#ibcon#about to read 4, iclass 38, count 2 2006.173.08:34:58.98#ibcon#read 4, iclass 38, count 2 2006.173.08:34:58.98#ibcon#about to read 5, iclass 38, count 2 2006.173.08:34:58.98#ibcon#read 5, iclass 38, count 2 2006.173.08:34:58.98#ibcon#about to read 6, iclass 38, count 2 2006.173.08:34:58.98#ibcon#read 6, iclass 38, count 2 2006.173.08:34:58.98#ibcon#end of sib2, iclass 38, count 2 2006.173.08:34:58.98#ibcon#*mode == 0, iclass 38, count 2 2006.173.08:34:58.98#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.08:34:58.98#ibcon#[27=AT01-04\r\n] 2006.173.08:34:58.98#ibcon#*before write, iclass 38, count 2 2006.173.08:34:58.98#ibcon#enter sib2, iclass 38, count 2 2006.173.08:34:58.98#ibcon#flushed, iclass 38, count 2 2006.173.08:34:58.98#ibcon#about to write, iclass 38, count 2 2006.173.08:34:58.98#ibcon#wrote, iclass 38, count 2 2006.173.08:34:58.98#ibcon#about to read 3, iclass 38, count 2 2006.173.08:34:59.01#ibcon#read 3, iclass 38, count 2 2006.173.08:34:59.01#ibcon#about to read 4, iclass 38, count 2 2006.173.08:34:59.01#ibcon#read 4, iclass 38, count 2 2006.173.08:34:59.01#ibcon#about to read 5, iclass 38, count 2 2006.173.08:34:59.01#ibcon#read 5, iclass 38, count 2 2006.173.08:34:59.01#ibcon#about to read 6, iclass 38, count 2 2006.173.08:34:59.01#ibcon#read 6, iclass 38, count 2 2006.173.08:34:59.01#ibcon#end of sib2, iclass 38, count 2 2006.173.08:34:59.01#ibcon#*after write, iclass 38, count 2 2006.173.08:34:59.01#ibcon#*before return 0, iclass 38, count 2 2006.173.08:34:59.01#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.08:34:59.01#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.08:34:59.01#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.08:34:59.01#ibcon#ireg 7 cls_cnt 0 2006.173.08:34:59.01#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.08:34:59.13#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.08:34:59.13#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.08:34:59.13#ibcon#enter wrdev, iclass 38, count 0 2006.173.08:34:59.13#ibcon#first serial, iclass 38, count 0 2006.173.08:34:59.13#ibcon#enter sib2, iclass 38, count 0 2006.173.08:34:59.13#ibcon#flushed, iclass 38, count 0 2006.173.08:34:59.13#ibcon#about to write, iclass 38, count 0 2006.173.08:34:59.13#ibcon#wrote, iclass 38, count 0 2006.173.08:34:59.13#ibcon#about to read 3, iclass 38, count 0 2006.173.08:34:59.15#ibcon#read 3, iclass 38, count 0 2006.173.08:34:59.15#ibcon#about to read 4, iclass 38, count 0 2006.173.08:34:59.15#ibcon#read 4, iclass 38, count 0 2006.173.08:34:59.15#ibcon#about to read 5, iclass 38, count 0 2006.173.08:34:59.15#ibcon#read 5, iclass 38, count 0 2006.173.08:34:59.15#ibcon#about to read 6, iclass 38, count 0 2006.173.08:34:59.15#ibcon#read 6, iclass 38, count 0 2006.173.08:34:59.15#ibcon#end of sib2, iclass 38, count 0 2006.173.08:34:59.15#ibcon#*mode == 0, iclass 38, count 0 2006.173.08:34:59.15#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.08:34:59.15#ibcon#[27=USB\r\n] 2006.173.08:34:59.15#ibcon#*before write, iclass 38, count 0 2006.173.08:34:59.15#ibcon#enter sib2, iclass 38, count 0 2006.173.08:34:59.15#ibcon#flushed, iclass 38, count 0 2006.173.08:34:59.15#ibcon#about to write, iclass 38, count 0 2006.173.08:34:59.15#ibcon#wrote, iclass 38, count 0 2006.173.08:34:59.15#ibcon#about to read 3, iclass 38, count 0 2006.173.08:34:59.18#ibcon#read 3, iclass 38, count 0 2006.173.08:34:59.18#ibcon#about to read 4, iclass 38, count 0 2006.173.08:34:59.18#ibcon#read 4, iclass 38, count 0 2006.173.08:34:59.18#ibcon#about to read 5, iclass 38, count 0 2006.173.08:34:59.18#ibcon#read 5, iclass 38, count 0 2006.173.08:34:59.18#ibcon#about to read 6, iclass 38, count 0 2006.173.08:34:59.18#ibcon#read 6, iclass 38, count 0 2006.173.08:34:59.18#ibcon#end of sib2, iclass 38, count 0 2006.173.08:34:59.18#ibcon#*after write, iclass 38, count 0 2006.173.08:34:59.18#ibcon#*before return 0, iclass 38, count 0 2006.173.08:34:59.18#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.08:34:59.18#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.08:34:59.18#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.08:34:59.18#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.08:34:59.18$vck44/vblo=2,634.99 2006.173.08:34:59.18#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.08:34:59.18#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.08:34:59.18#ibcon#ireg 17 cls_cnt 0 2006.173.08:34:59.18#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.08:34:59.18#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.08:34:59.18#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.08:34:59.18#ibcon#enter wrdev, iclass 40, count 0 2006.173.08:34:59.18#ibcon#first serial, iclass 40, count 0 2006.173.08:34:59.18#ibcon#enter sib2, iclass 40, count 0 2006.173.08:34:59.18#ibcon#flushed, iclass 40, count 0 2006.173.08:34:59.18#ibcon#about to write, iclass 40, count 0 2006.173.08:34:59.18#ibcon#wrote, iclass 40, count 0 2006.173.08:34:59.18#ibcon#about to read 3, iclass 40, count 0 2006.173.08:34:59.20#ibcon#read 3, iclass 40, count 0 2006.173.08:34:59.20#ibcon#about to read 4, iclass 40, count 0 2006.173.08:34:59.20#ibcon#read 4, iclass 40, count 0 2006.173.08:34:59.20#ibcon#about to read 5, iclass 40, count 0 2006.173.08:34:59.20#ibcon#read 5, iclass 40, count 0 2006.173.08:34:59.20#ibcon#about to read 6, iclass 40, count 0 2006.173.08:34:59.20#ibcon#read 6, iclass 40, count 0 2006.173.08:34:59.20#ibcon#end of sib2, iclass 40, count 0 2006.173.08:34:59.20#ibcon#*mode == 0, iclass 40, count 0 2006.173.08:34:59.20#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.08:34:59.20#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.08:34:59.20#ibcon#*before write, iclass 40, count 0 2006.173.08:34:59.20#ibcon#enter sib2, iclass 40, count 0 2006.173.08:34:59.20#ibcon#flushed, iclass 40, count 0 2006.173.08:34:59.20#ibcon#about to write, iclass 40, count 0 2006.173.08:34:59.20#ibcon#wrote, iclass 40, count 0 2006.173.08:34:59.20#ibcon#about to read 3, iclass 40, count 0 2006.173.08:34:59.24#ibcon#read 3, iclass 40, count 0 2006.173.08:34:59.24#ibcon#about to read 4, iclass 40, count 0 2006.173.08:34:59.24#ibcon#read 4, iclass 40, count 0 2006.173.08:34:59.24#ibcon#about to read 5, iclass 40, count 0 2006.173.08:34:59.24#ibcon#read 5, iclass 40, count 0 2006.173.08:34:59.24#ibcon#about to read 6, iclass 40, count 0 2006.173.08:34:59.24#ibcon#read 6, iclass 40, count 0 2006.173.08:34:59.24#ibcon#end of sib2, iclass 40, count 0 2006.173.08:34:59.24#ibcon#*after write, iclass 40, count 0 2006.173.08:34:59.24#ibcon#*before return 0, iclass 40, count 0 2006.173.08:34:59.24#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.08:34:59.24#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.08:34:59.24#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.08:34:59.24#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.08:34:59.24$vck44/vb=2,4 2006.173.08:34:59.24#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.08:34:59.24#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.08:34:59.24#ibcon#ireg 11 cls_cnt 2 2006.173.08:34:59.24#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.08:34:59.30#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.08:34:59.30#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.08:34:59.30#ibcon#enter wrdev, iclass 4, count 2 2006.173.08:34:59.30#ibcon#first serial, iclass 4, count 2 2006.173.08:34:59.30#ibcon#enter sib2, iclass 4, count 2 2006.173.08:34:59.30#ibcon#flushed, iclass 4, count 2 2006.173.08:34:59.30#ibcon#about to write, iclass 4, count 2 2006.173.08:34:59.30#ibcon#wrote, iclass 4, count 2 2006.173.08:34:59.30#ibcon#about to read 3, iclass 4, count 2 2006.173.08:34:59.32#ibcon#read 3, iclass 4, count 2 2006.173.08:34:59.32#ibcon#about to read 4, iclass 4, count 2 2006.173.08:34:59.32#ibcon#read 4, iclass 4, count 2 2006.173.08:34:59.32#ibcon#about to read 5, iclass 4, count 2 2006.173.08:34:59.32#ibcon#read 5, iclass 4, count 2 2006.173.08:34:59.32#ibcon#about to read 6, iclass 4, count 2 2006.173.08:34:59.32#ibcon#read 6, iclass 4, count 2 2006.173.08:34:59.32#ibcon#end of sib2, iclass 4, count 2 2006.173.08:34:59.32#ibcon#*mode == 0, iclass 4, count 2 2006.173.08:34:59.32#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.08:34:59.32#ibcon#[27=AT02-04\r\n] 2006.173.08:34:59.32#ibcon#*before write, iclass 4, count 2 2006.173.08:34:59.32#ibcon#enter sib2, iclass 4, count 2 2006.173.08:34:59.32#ibcon#flushed, iclass 4, count 2 2006.173.08:34:59.32#ibcon#about to write, iclass 4, count 2 2006.173.08:34:59.32#ibcon#wrote, iclass 4, count 2 2006.173.08:34:59.32#ibcon#about to read 3, iclass 4, count 2 2006.173.08:34:59.35#ibcon#read 3, iclass 4, count 2 2006.173.08:34:59.35#ibcon#about to read 4, iclass 4, count 2 2006.173.08:34:59.35#ibcon#read 4, iclass 4, count 2 2006.173.08:34:59.35#ibcon#about to read 5, iclass 4, count 2 2006.173.08:34:59.35#ibcon#read 5, iclass 4, count 2 2006.173.08:34:59.35#ibcon#about to read 6, iclass 4, count 2 2006.173.08:34:59.35#ibcon#read 6, iclass 4, count 2 2006.173.08:34:59.35#ibcon#end of sib2, iclass 4, count 2 2006.173.08:34:59.35#ibcon#*after write, iclass 4, count 2 2006.173.08:34:59.35#ibcon#*before return 0, iclass 4, count 2 2006.173.08:34:59.35#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.08:34:59.35#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.08:34:59.35#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.08:34:59.35#ibcon#ireg 7 cls_cnt 0 2006.173.08:34:59.35#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.08:34:59.47#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.08:34:59.47#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.08:34:59.47#ibcon#enter wrdev, iclass 4, count 0 2006.173.08:34:59.47#ibcon#first serial, iclass 4, count 0 2006.173.08:34:59.47#ibcon#enter sib2, iclass 4, count 0 2006.173.08:34:59.47#ibcon#flushed, iclass 4, count 0 2006.173.08:34:59.47#ibcon#about to write, iclass 4, count 0 2006.173.08:34:59.47#ibcon#wrote, iclass 4, count 0 2006.173.08:34:59.47#ibcon#about to read 3, iclass 4, count 0 2006.173.08:34:59.49#ibcon#read 3, iclass 4, count 0 2006.173.08:34:59.49#ibcon#about to read 4, iclass 4, count 0 2006.173.08:34:59.49#ibcon#read 4, iclass 4, count 0 2006.173.08:34:59.49#ibcon#about to read 5, iclass 4, count 0 2006.173.08:34:59.49#ibcon#read 5, iclass 4, count 0 2006.173.08:34:59.49#ibcon#about to read 6, iclass 4, count 0 2006.173.08:34:59.49#ibcon#read 6, iclass 4, count 0 2006.173.08:34:59.49#ibcon#end of sib2, iclass 4, count 0 2006.173.08:34:59.49#ibcon#*mode == 0, iclass 4, count 0 2006.173.08:34:59.49#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.08:34:59.49#ibcon#[27=USB\r\n] 2006.173.08:34:59.49#ibcon#*before write, iclass 4, count 0 2006.173.08:34:59.49#ibcon#enter sib2, iclass 4, count 0 2006.173.08:34:59.49#ibcon#flushed, iclass 4, count 0 2006.173.08:34:59.49#ibcon#about to write, iclass 4, count 0 2006.173.08:34:59.49#ibcon#wrote, iclass 4, count 0 2006.173.08:34:59.49#ibcon#about to read 3, iclass 4, count 0 2006.173.08:34:59.52#ibcon#read 3, iclass 4, count 0 2006.173.08:34:59.52#ibcon#about to read 4, iclass 4, count 0 2006.173.08:34:59.52#ibcon#read 4, iclass 4, count 0 2006.173.08:34:59.52#ibcon#about to read 5, iclass 4, count 0 2006.173.08:34:59.52#ibcon#read 5, iclass 4, count 0 2006.173.08:34:59.52#ibcon#about to read 6, iclass 4, count 0 2006.173.08:34:59.52#ibcon#read 6, iclass 4, count 0 2006.173.08:34:59.52#ibcon#end of sib2, iclass 4, count 0 2006.173.08:34:59.52#ibcon#*after write, iclass 4, count 0 2006.173.08:34:59.52#ibcon#*before return 0, iclass 4, count 0 2006.173.08:34:59.52#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.08:34:59.52#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.08:34:59.52#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.08:34:59.52#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.08:34:59.52$vck44/vblo=3,649.99 2006.173.08:34:59.52#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.08:34:59.52#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.08:34:59.52#ibcon#ireg 17 cls_cnt 0 2006.173.08:34:59.52#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.08:34:59.52#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.08:34:59.52#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.08:34:59.52#ibcon#enter wrdev, iclass 6, count 0 2006.173.08:34:59.52#ibcon#first serial, iclass 6, count 0 2006.173.08:34:59.52#ibcon#enter sib2, iclass 6, count 0 2006.173.08:34:59.52#ibcon#flushed, iclass 6, count 0 2006.173.08:34:59.52#ibcon#about to write, iclass 6, count 0 2006.173.08:34:59.52#ibcon#wrote, iclass 6, count 0 2006.173.08:34:59.52#ibcon#about to read 3, iclass 6, count 0 2006.173.08:34:59.54#ibcon#read 3, iclass 6, count 0 2006.173.08:34:59.54#ibcon#about to read 4, iclass 6, count 0 2006.173.08:34:59.54#ibcon#read 4, iclass 6, count 0 2006.173.08:34:59.54#ibcon#about to read 5, iclass 6, count 0 2006.173.08:34:59.54#ibcon#read 5, iclass 6, count 0 2006.173.08:34:59.54#ibcon#about to read 6, iclass 6, count 0 2006.173.08:34:59.54#ibcon#read 6, iclass 6, count 0 2006.173.08:34:59.54#ibcon#end of sib2, iclass 6, count 0 2006.173.08:34:59.54#ibcon#*mode == 0, iclass 6, count 0 2006.173.08:34:59.54#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.08:34:59.54#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.08:34:59.54#ibcon#*before write, iclass 6, count 0 2006.173.08:34:59.54#ibcon#enter sib2, iclass 6, count 0 2006.173.08:34:59.54#ibcon#flushed, iclass 6, count 0 2006.173.08:34:59.54#ibcon#about to write, iclass 6, count 0 2006.173.08:34:59.54#ibcon#wrote, iclass 6, count 0 2006.173.08:34:59.54#ibcon#about to read 3, iclass 6, count 0 2006.173.08:34:59.58#ibcon#read 3, iclass 6, count 0 2006.173.08:34:59.58#ibcon#about to read 4, iclass 6, count 0 2006.173.08:34:59.58#ibcon#read 4, iclass 6, count 0 2006.173.08:34:59.58#ibcon#about to read 5, iclass 6, count 0 2006.173.08:34:59.58#ibcon#read 5, iclass 6, count 0 2006.173.08:34:59.58#ibcon#about to read 6, iclass 6, count 0 2006.173.08:34:59.58#ibcon#read 6, iclass 6, count 0 2006.173.08:34:59.58#ibcon#end of sib2, iclass 6, count 0 2006.173.08:34:59.58#ibcon#*after write, iclass 6, count 0 2006.173.08:34:59.58#ibcon#*before return 0, iclass 6, count 0 2006.173.08:34:59.58#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.08:34:59.58#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.08:34:59.58#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.08:34:59.58#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.08:34:59.58$vck44/vb=3,4 2006.173.08:34:59.58#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.08:34:59.58#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.08:34:59.58#ibcon#ireg 11 cls_cnt 2 2006.173.08:34:59.58#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.08:34:59.64#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.08:34:59.64#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.08:34:59.64#ibcon#enter wrdev, iclass 10, count 2 2006.173.08:34:59.64#ibcon#first serial, iclass 10, count 2 2006.173.08:34:59.64#ibcon#enter sib2, iclass 10, count 2 2006.173.08:34:59.64#ibcon#flushed, iclass 10, count 2 2006.173.08:34:59.64#ibcon#about to write, iclass 10, count 2 2006.173.08:34:59.64#ibcon#wrote, iclass 10, count 2 2006.173.08:34:59.64#ibcon#about to read 3, iclass 10, count 2 2006.173.08:34:59.66#ibcon#read 3, iclass 10, count 2 2006.173.08:34:59.66#ibcon#about to read 4, iclass 10, count 2 2006.173.08:34:59.66#ibcon#read 4, iclass 10, count 2 2006.173.08:34:59.66#ibcon#about to read 5, iclass 10, count 2 2006.173.08:34:59.66#ibcon#read 5, iclass 10, count 2 2006.173.08:34:59.66#ibcon#about to read 6, iclass 10, count 2 2006.173.08:34:59.66#ibcon#read 6, iclass 10, count 2 2006.173.08:34:59.66#ibcon#end of sib2, iclass 10, count 2 2006.173.08:34:59.66#ibcon#*mode == 0, iclass 10, count 2 2006.173.08:34:59.66#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.08:34:59.66#ibcon#[27=AT03-04\r\n] 2006.173.08:34:59.66#ibcon#*before write, iclass 10, count 2 2006.173.08:34:59.66#ibcon#enter sib2, iclass 10, count 2 2006.173.08:34:59.66#ibcon#flushed, iclass 10, count 2 2006.173.08:34:59.66#ibcon#about to write, iclass 10, count 2 2006.173.08:34:59.66#ibcon#wrote, iclass 10, count 2 2006.173.08:34:59.66#ibcon#about to read 3, iclass 10, count 2 2006.173.08:34:59.69#ibcon#read 3, iclass 10, count 2 2006.173.08:34:59.69#ibcon#about to read 4, iclass 10, count 2 2006.173.08:34:59.69#ibcon#read 4, iclass 10, count 2 2006.173.08:34:59.69#ibcon#about to read 5, iclass 10, count 2 2006.173.08:34:59.69#ibcon#read 5, iclass 10, count 2 2006.173.08:34:59.69#ibcon#about to read 6, iclass 10, count 2 2006.173.08:34:59.69#ibcon#read 6, iclass 10, count 2 2006.173.08:34:59.69#ibcon#end of sib2, iclass 10, count 2 2006.173.08:34:59.69#ibcon#*after write, iclass 10, count 2 2006.173.08:34:59.69#ibcon#*before return 0, iclass 10, count 2 2006.173.08:34:59.69#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.08:34:59.69#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.08:34:59.69#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.08:34:59.69#ibcon#ireg 7 cls_cnt 0 2006.173.08:34:59.69#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.08:34:59.81#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.08:34:59.81#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.08:34:59.81#ibcon#enter wrdev, iclass 10, count 0 2006.173.08:34:59.81#ibcon#first serial, iclass 10, count 0 2006.173.08:34:59.81#ibcon#enter sib2, iclass 10, count 0 2006.173.08:34:59.81#ibcon#flushed, iclass 10, count 0 2006.173.08:34:59.81#ibcon#about to write, iclass 10, count 0 2006.173.08:34:59.81#ibcon#wrote, iclass 10, count 0 2006.173.08:34:59.81#ibcon#about to read 3, iclass 10, count 0 2006.173.08:34:59.83#ibcon#read 3, iclass 10, count 0 2006.173.08:34:59.83#ibcon#about to read 4, iclass 10, count 0 2006.173.08:34:59.83#ibcon#read 4, iclass 10, count 0 2006.173.08:34:59.83#ibcon#about to read 5, iclass 10, count 0 2006.173.08:34:59.83#ibcon#read 5, iclass 10, count 0 2006.173.08:34:59.83#ibcon#about to read 6, iclass 10, count 0 2006.173.08:34:59.83#ibcon#read 6, iclass 10, count 0 2006.173.08:34:59.83#ibcon#end of sib2, iclass 10, count 0 2006.173.08:34:59.83#ibcon#*mode == 0, iclass 10, count 0 2006.173.08:34:59.83#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.08:34:59.83#ibcon#[27=USB\r\n] 2006.173.08:34:59.83#ibcon#*before write, iclass 10, count 0 2006.173.08:34:59.83#ibcon#enter sib2, iclass 10, count 0 2006.173.08:34:59.83#ibcon#flushed, iclass 10, count 0 2006.173.08:34:59.83#ibcon#about to write, iclass 10, count 0 2006.173.08:34:59.83#ibcon#wrote, iclass 10, count 0 2006.173.08:34:59.83#ibcon#about to read 3, iclass 10, count 0 2006.173.08:34:59.86#ibcon#read 3, iclass 10, count 0 2006.173.08:34:59.86#ibcon#about to read 4, iclass 10, count 0 2006.173.08:34:59.86#ibcon#read 4, iclass 10, count 0 2006.173.08:34:59.86#ibcon#about to read 5, iclass 10, count 0 2006.173.08:34:59.86#ibcon#read 5, iclass 10, count 0 2006.173.08:34:59.86#ibcon#about to read 6, iclass 10, count 0 2006.173.08:34:59.86#ibcon#read 6, iclass 10, count 0 2006.173.08:34:59.86#ibcon#end of sib2, iclass 10, count 0 2006.173.08:34:59.86#ibcon#*after write, iclass 10, count 0 2006.173.08:34:59.86#ibcon#*before return 0, iclass 10, count 0 2006.173.08:34:59.86#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.08:34:59.86#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.08:34:59.86#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.08:34:59.86#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.08:34:59.86$vck44/vblo=4,679.99 2006.173.08:34:59.86#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.08:34:59.86#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.08:34:59.86#ibcon#ireg 17 cls_cnt 0 2006.173.08:34:59.86#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.08:34:59.86#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.08:34:59.86#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.08:34:59.86#ibcon#enter wrdev, iclass 12, count 0 2006.173.08:34:59.86#ibcon#first serial, iclass 12, count 0 2006.173.08:34:59.86#ibcon#enter sib2, iclass 12, count 0 2006.173.08:34:59.86#ibcon#flushed, iclass 12, count 0 2006.173.08:34:59.86#ibcon#about to write, iclass 12, count 0 2006.173.08:34:59.86#ibcon#wrote, iclass 12, count 0 2006.173.08:34:59.86#ibcon#about to read 3, iclass 12, count 0 2006.173.08:34:59.88#ibcon#read 3, iclass 12, count 0 2006.173.08:34:59.88#ibcon#about to read 4, iclass 12, count 0 2006.173.08:34:59.88#ibcon#read 4, iclass 12, count 0 2006.173.08:34:59.88#ibcon#about to read 5, iclass 12, count 0 2006.173.08:34:59.88#ibcon#read 5, iclass 12, count 0 2006.173.08:34:59.88#ibcon#about to read 6, iclass 12, count 0 2006.173.08:34:59.88#ibcon#read 6, iclass 12, count 0 2006.173.08:34:59.88#ibcon#end of sib2, iclass 12, count 0 2006.173.08:34:59.88#ibcon#*mode == 0, iclass 12, count 0 2006.173.08:34:59.88#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.08:34:59.88#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.08:34:59.88#ibcon#*before write, iclass 12, count 0 2006.173.08:34:59.88#ibcon#enter sib2, iclass 12, count 0 2006.173.08:34:59.88#ibcon#flushed, iclass 12, count 0 2006.173.08:34:59.88#ibcon#about to write, iclass 12, count 0 2006.173.08:34:59.88#ibcon#wrote, iclass 12, count 0 2006.173.08:34:59.88#ibcon#about to read 3, iclass 12, count 0 2006.173.08:34:59.92#ibcon#read 3, iclass 12, count 0 2006.173.08:34:59.92#ibcon#about to read 4, iclass 12, count 0 2006.173.08:34:59.92#ibcon#read 4, iclass 12, count 0 2006.173.08:34:59.92#ibcon#about to read 5, iclass 12, count 0 2006.173.08:34:59.92#ibcon#read 5, iclass 12, count 0 2006.173.08:34:59.92#ibcon#about to read 6, iclass 12, count 0 2006.173.08:34:59.92#ibcon#read 6, iclass 12, count 0 2006.173.08:34:59.92#ibcon#end of sib2, iclass 12, count 0 2006.173.08:34:59.92#ibcon#*after write, iclass 12, count 0 2006.173.08:34:59.92#ibcon#*before return 0, iclass 12, count 0 2006.173.08:34:59.92#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.08:34:59.92#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.08:34:59.92#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.08:34:59.92#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.08:34:59.92$vck44/vb=4,4 2006.173.08:34:59.92#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.08:34:59.92#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.08:34:59.92#ibcon#ireg 11 cls_cnt 2 2006.173.08:34:59.92#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.08:34:59.98#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.08:34:59.98#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.08:34:59.98#ibcon#enter wrdev, iclass 14, count 2 2006.173.08:34:59.98#ibcon#first serial, iclass 14, count 2 2006.173.08:34:59.98#ibcon#enter sib2, iclass 14, count 2 2006.173.08:34:59.98#ibcon#flushed, iclass 14, count 2 2006.173.08:34:59.98#ibcon#about to write, iclass 14, count 2 2006.173.08:34:59.98#ibcon#wrote, iclass 14, count 2 2006.173.08:34:59.98#ibcon#about to read 3, iclass 14, count 2 2006.173.08:35:00.00#ibcon#read 3, iclass 14, count 2 2006.173.08:35:00.00#ibcon#about to read 4, iclass 14, count 2 2006.173.08:35:00.00#ibcon#read 4, iclass 14, count 2 2006.173.08:35:00.00#ibcon#about to read 5, iclass 14, count 2 2006.173.08:35:00.00#ibcon#read 5, iclass 14, count 2 2006.173.08:35:00.00#ibcon#about to read 6, iclass 14, count 2 2006.173.08:35:00.00#ibcon#read 6, iclass 14, count 2 2006.173.08:35:00.00#ibcon#end of sib2, iclass 14, count 2 2006.173.08:35:00.00#ibcon#*mode == 0, iclass 14, count 2 2006.173.08:35:00.00#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.08:35:00.00#ibcon#[27=AT04-04\r\n] 2006.173.08:35:00.00#ibcon#*before write, iclass 14, count 2 2006.173.08:35:00.00#ibcon#enter sib2, iclass 14, count 2 2006.173.08:35:00.00#ibcon#flushed, iclass 14, count 2 2006.173.08:35:00.00#ibcon#about to write, iclass 14, count 2 2006.173.08:35:00.00#ibcon#wrote, iclass 14, count 2 2006.173.08:35:00.00#ibcon#about to read 3, iclass 14, count 2 2006.173.08:35:00.03#ibcon#read 3, iclass 14, count 2 2006.173.08:35:00.03#ibcon#about to read 4, iclass 14, count 2 2006.173.08:35:00.03#ibcon#read 4, iclass 14, count 2 2006.173.08:35:00.03#ibcon#about to read 5, iclass 14, count 2 2006.173.08:35:00.03#ibcon#read 5, iclass 14, count 2 2006.173.08:35:00.03#ibcon#about to read 6, iclass 14, count 2 2006.173.08:35:00.03#ibcon#read 6, iclass 14, count 2 2006.173.08:35:00.03#ibcon#end of sib2, iclass 14, count 2 2006.173.08:35:00.03#ibcon#*after write, iclass 14, count 2 2006.173.08:35:00.03#ibcon#*before return 0, iclass 14, count 2 2006.173.08:35:00.03#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.08:35:00.03#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.08:35:00.03#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.08:35:00.03#ibcon#ireg 7 cls_cnt 0 2006.173.08:35:00.03#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.08:35:00.15#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.08:35:00.15#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.08:35:00.15#ibcon#enter wrdev, iclass 14, count 0 2006.173.08:35:00.15#ibcon#first serial, iclass 14, count 0 2006.173.08:35:00.15#ibcon#enter sib2, iclass 14, count 0 2006.173.08:35:00.15#ibcon#flushed, iclass 14, count 0 2006.173.08:35:00.15#ibcon#about to write, iclass 14, count 0 2006.173.08:35:00.15#ibcon#wrote, iclass 14, count 0 2006.173.08:35:00.15#ibcon#about to read 3, iclass 14, count 0 2006.173.08:35:00.17#ibcon#read 3, iclass 14, count 0 2006.173.08:35:00.17#ibcon#about to read 4, iclass 14, count 0 2006.173.08:35:00.17#ibcon#read 4, iclass 14, count 0 2006.173.08:35:00.17#ibcon#about to read 5, iclass 14, count 0 2006.173.08:35:00.17#ibcon#read 5, iclass 14, count 0 2006.173.08:35:00.17#ibcon#about to read 6, iclass 14, count 0 2006.173.08:35:00.17#ibcon#read 6, iclass 14, count 0 2006.173.08:35:00.17#ibcon#end of sib2, iclass 14, count 0 2006.173.08:35:00.17#ibcon#*mode == 0, iclass 14, count 0 2006.173.08:35:00.17#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.08:35:00.17#ibcon#[27=USB\r\n] 2006.173.08:35:00.17#ibcon#*before write, iclass 14, count 0 2006.173.08:35:00.17#ibcon#enter sib2, iclass 14, count 0 2006.173.08:35:00.17#ibcon#flushed, iclass 14, count 0 2006.173.08:35:00.17#ibcon#about to write, iclass 14, count 0 2006.173.08:35:00.17#ibcon#wrote, iclass 14, count 0 2006.173.08:35:00.17#ibcon#about to read 3, iclass 14, count 0 2006.173.08:35:00.20#ibcon#read 3, iclass 14, count 0 2006.173.08:35:00.20#ibcon#about to read 4, iclass 14, count 0 2006.173.08:35:00.20#ibcon#read 4, iclass 14, count 0 2006.173.08:35:00.20#ibcon#about to read 5, iclass 14, count 0 2006.173.08:35:00.20#ibcon#read 5, iclass 14, count 0 2006.173.08:35:00.20#ibcon#about to read 6, iclass 14, count 0 2006.173.08:35:00.20#ibcon#read 6, iclass 14, count 0 2006.173.08:35:00.20#ibcon#end of sib2, iclass 14, count 0 2006.173.08:35:00.20#ibcon#*after write, iclass 14, count 0 2006.173.08:35:00.20#ibcon#*before return 0, iclass 14, count 0 2006.173.08:35:00.20#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.08:35:00.20#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.08:35:00.20#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.08:35:00.20#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.08:35:00.20$vck44/vblo=5,709.99 2006.173.08:35:00.20#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.08:35:00.20#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.08:35:00.20#ibcon#ireg 17 cls_cnt 0 2006.173.08:35:00.20#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.08:35:00.20#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.08:35:00.20#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.08:35:00.20#ibcon#enter wrdev, iclass 16, count 0 2006.173.08:35:00.20#ibcon#first serial, iclass 16, count 0 2006.173.08:35:00.20#ibcon#enter sib2, iclass 16, count 0 2006.173.08:35:00.20#ibcon#flushed, iclass 16, count 0 2006.173.08:35:00.20#ibcon#about to write, iclass 16, count 0 2006.173.08:35:00.20#ibcon#wrote, iclass 16, count 0 2006.173.08:35:00.20#ibcon#about to read 3, iclass 16, count 0 2006.173.08:35:00.22#ibcon#read 3, iclass 16, count 0 2006.173.08:35:00.22#ibcon#about to read 4, iclass 16, count 0 2006.173.08:35:00.22#ibcon#read 4, iclass 16, count 0 2006.173.08:35:00.22#ibcon#about to read 5, iclass 16, count 0 2006.173.08:35:00.22#ibcon#read 5, iclass 16, count 0 2006.173.08:35:00.22#ibcon#about to read 6, iclass 16, count 0 2006.173.08:35:00.22#ibcon#read 6, iclass 16, count 0 2006.173.08:35:00.22#ibcon#end of sib2, iclass 16, count 0 2006.173.08:35:00.22#ibcon#*mode == 0, iclass 16, count 0 2006.173.08:35:00.22#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.08:35:00.22#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.08:35:00.22#ibcon#*before write, iclass 16, count 0 2006.173.08:35:00.22#ibcon#enter sib2, iclass 16, count 0 2006.173.08:35:00.22#ibcon#flushed, iclass 16, count 0 2006.173.08:35:00.22#ibcon#about to write, iclass 16, count 0 2006.173.08:35:00.22#ibcon#wrote, iclass 16, count 0 2006.173.08:35:00.22#ibcon#about to read 3, iclass 16, count 0 2006.173.08:35:00.26#ibcon#read 3, iclass 16, count 0 2006.173.08:35:00.26#ibcon#about to read 4, iclass 16, count 0 2006.173.08:35:00.26#ibcon#read 4, iclass 16, count 0 2006.173.08:35:00.26#ibcon#about to read 5, iclass 16, count 0 2006.173.08:35:00.26#ibcon#read 5, iclass 16, count 0 2006.173.08:35:00.26#ibcon#about to read 6, iclass 16, count 0 2006.173.08:35:00.26#ibcon#read 6, iclass 16, count 0 2006.173.08:35:00.26#ibcon#end of sib2, iclass 16, count 0 2006.173.08:35:00.26#ibcon#*after write, iclass 16, count 0 2006.173.08:35:00.26#ibcon#*before return 0, iclass 16, count 0 2006.173.08:35:00.26#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.08:35:00.26#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.08:35:00.26#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.08:35:00.26#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.08:35:00.26$vck44/vb=5,4 2006.173.08:35:00.26#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.08:35:00.26#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.08:35:00.26#ibcon#ireg 11 cls_cnt 2 2006.173.08:35:00.26#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.08:35:00.32#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.08:35:00.32#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.08:35:00.32#ibcon#enter wrdev, iclass 18, count 2 2006.173.08:35:00.32#ibcon#first serial, iclass 18, count 2 2006.173.08:35:00.32#ibcon#enter sib2, iclass 18, count 2 2006.173.08:35:00.32#ibcon#flushed, iclass 18, count 2 2006.173.08:35:00.32#ibcon#about to write, iclass 18, count 2 2006.173.08:35:00.32#ibcon#wrote, iclass 18, count 2 2006.173.08:35:00.32#ibcon#about to read 3, iclass 18, count 2 2006.173.08:35:00.34#ibcon#read 3, iclass 18, count 2 2006.173.08:35:00.34#ibcon#about to read 4, iclass 18, count 2 2006.173.08:35:00.34#ibcon#read 4, iclass 18, count 2 2006.173.08:35:00.34#ibcon#about to read 5, iclass 18, count 2 2006.173.08:35:00.34#ibcon#read 5, iclass 18, count 2 2006.173.08:35:00.34#ibcon#about to read 6, iclass 18, count 2 2006.173.08:35:00.34#ibcon#read 6, iclass 18, count 2 2006.173.08:35:00.34#ibcon#end of sib2, iclass 18, count 2 2006.173.08:35:00.34#ibcon#*mode == 0, iclass 18, count 2 2006.173.08:35:00.34#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.08:35:00.34#ibcon#[27=AT05-04\r\n] 2006.173.08:35:00.34#ibcon#*before write, iclass 18, count 2 2006.173.08:35:00.34#ibcon#enter sib2, iclass 18, count 2 2006.173.08:35:00.34#ibcon#flushed, iclass 18, count 2 2006.173.08:35:00.34#ibcon#about to write, iclass 18, count 2 2006.173.08:35:00.34#ibcon#wrote, iclass 18, count 2 2006.173.08:35:00.34#ibcon#about to read 3, iclass 18, count 2 2006.173.08:35:00.37#ibcon#read 3, iclass 18, count 2 2006.173.08:35:00.37#ibcon#about to read 4, iclass 18, count 2 2006.173.08:35:00.37#ibcon#read 4, iclass 18, count 2 2006.173.08:35:00.37#ibcon#about to read 5, iclass 18, count 2 2006.173.08:35:00.37#ibcon#read 5, iclass 18, count 2 2006.173.08:35:00.37#ibcon#about to read 6, iclass 18, count 2 2006.173.08:35:00.37#ibcon#read 6, iclass 18, count 2 2006.173.08:35:00.37#ibcon#end of sib2, iclass 18, count 2 2006.173.08:35:00.37#ibcon#*after write, iclass 18, count 2 2006.173.08:35:00.37#ibcon#*before return 0, iclass 18, count 2 2006.173.08:35:00.37#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.08:35:00.37#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.08:35:00.37#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.08:35:00.37#ibcon#ireg 7 cls_cnt 0 2006.173.08:35:00.37#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.08:35:00.49#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.08:35:00.49#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.08:35:00.49#ibcon#enter wrdev, iclass 18, count 0 2006.173.08:35:00.49#ibcon#first serial, iclass 18, count 0 2006.173.08:35:00.49#ibcon#enter sib2, iclass 18, count 0 2006.173.08:35:00.49#ibcon#flushed, iclass 18, count 0 2006.173.08:35:00.49#ibcon#about to write, iclass 18, count 0 2006.173.08:35:00.49#ibcon#wrote, iclass 18, count 0 2006.173.08:35:00.49#ibcon#about to read 3, iclass 18, count 0 2006.173.08:35:00.51#ibcon#read 3, iclass 18, count 0 2006.173.08:35:00.51#ibcon#about to read 4, iclass 18, count 0 2006.173.08:35:00.51#ibcon#read 4, iclass 18, count 0 2006.173.08:35:00.51#ibcon#about to read 5, iclass 18, count 0 2006.173.08:35:00.51#ibcon#read 5, iclass 18, count 0 2006.173.08:35:00.51#ibcon#about to read 6, iclass 18, count 0 2006.173.08:35:00.51#ibcon#read 6, iclass 18, count 0 2006.173.08:35:00.51#ibcon#end of sib2, iclass 18, count 0 2006.173.08:35:00.51#ibcon#*mode == 0, iclass 18, count 0 2006.173.08:35:00.51#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.08:35:00.51#ibcon#[27=USB\r\n] 2006.173.08:35:00.51#ibcon#*before write, iclass 18, count 0 2006.173.08:35:00.51#ibcon#enter sib2, iclass 18, count 0 2006.173.08:35:00.51#ibcon#flushed, iclass 18, count 0 2006.173.08:35:00.51#ibcon#about to write, iclass 18, count 0 2006.173.08:35:00.51#ibcon#wrote, iclass 18, count 0 2006.173.08:35:00.51#ibcon#about to read 3, iclass 18, count 0 2006.173.08:35:00.54#ibcon#read 3, iclass 18, count 0 2006.173.08:35:00.54#ibcon#about to read 4, iclass 18, count 0 2006.173.08:35:00.54#ibcon#read 4, iclass 18, count 0 2006.173.08:35:00.54#ibcon#about to read 5, iclass 18, count 0 2006.173.08:35:00.54#ibcon#read 5, iclass 18, count 0 2006.173.08:35:00.54#ibcon#about to read 6, iclass 18, count 0 2006.173.08:35:00.54#ibcon#read 6, iclass 18, count 0 2006.173.08:35:00.54#ibcon#end of sib2, iclass 18, count 0 2006.173.08:35:00.54#ibcon#*after write, iclass 18, count 0 2006.173.08:35:00.54#ibcon#*before return 0, iclass 18, count 0 2006.173.08:35:00.54#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.08:35:00.54#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.08:35:00.54#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.08:35:00.54#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.08:35:00.54$vck44/vblo=6,719.99 2006.173.08:35:00.54#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.08:35:00.54#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.08:35:00.54#ibcon#ireg 17 cls_cnt 0 2006.173.08:35:00.54#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.08:35:00.54#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.08:35:00.54#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.08:35:00.54#ibcon#enter wrdev, iclass 20, count 0 2006.173.08:35:00.54#ibcon#first serial, iclass 20, count 0 2006.173.08:35:00.54#ibcon#enter sib2, iclass 20, count 0 2006.173.08:35:00.54#ibcon#flushed, iclass 20, count 0 2006.173.08:35:00.54#ibcon#about to write, iclass 20, count 0 2006.173.08:35:00.54#ibcon#wrote, iclass 20, count 0 2006.173.08:35:00.54#ibcon#about to read 3, iclass 20, count 0 2006.173.08:35:00.56#ibcon#read 3, iclass 20, count 0 2006.173.08:35:00.56#ibcon#about to read 4, iclass 20, count 0 2006.173.08:35:00.56#ibcon#read 4, iclass 20, count 0 2006.173.08:35:00.56#ibcon#about to read 5, iclass 20, count 0 2006.173.08:35:00.56#ibcon#read 5, iclass 20, count 0 2006.173.08:35:00.56#ibcon#about to read 6, iclass 20, count 0 2006.173.08:35:00.56#ibcon#read 6, iclass 20, count 0 2006.173.08:35:00.56#ibcon#end of sib2, iclass 20, count 0 2006.173.08:35:00.56#ibcon#*mode == 0, iclass 20, count 0 2006.173.08:35:00.56#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.08:35:00.56#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.08:35:00.56#ibcon#*before write, iclass 20, count 0 2006.173.08:35:00.56#ibcon#enter sib2, iclass 20, count 0 2006.173.08:35:00.56#ibcon#flushed, iclass 20, count 0 2006.173.08:35:00.56#ibcon#about to write, iclass 20, count 0 2006.173.08:35:00.56#ibcon#wrote, iclass 20, count 0 2006.173.08:35:00.56#ibcon#about to read 3, iclass 20, count 0 2006.173.08:35:00.60#ibcon#read 3, iclass 20, count 0 2006.173.08:35:00.60#ibcon#about to read 4, iclass 20, count 0 2006.173.08:35:00.60#ibcon#read 4, iclass 20, count 0 2006.173.08:35:00.60#ibcon#about to read 5, iclass 20, count 0 2006.173.08:35:00.60#ibcon#read 5, iclass 20, count 0 2006.173.08:35:00.60#ibcon#about to read 6, iclass 20, count 0 2006.173.08:35:00.60#ibcon#read 6, iclass 20, count 0 2006.173.08:35:00.60#ibcon#end of sib2, iclass 20, count 0 2006.173.08:35:00.60#ibcon#*after write, iclass 20, count 0 2006.173.08:35:00.60#ibcon#*before return 0, iclass 20, count 0 2006.173.08:35:00.60#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.08:35:00.60#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.08:35:00.60#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.08:35:00.60#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.08:35:00.60$vck44/vb=6,4 2006.173.08:35:00.60#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.08:35:00.60#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.08:35:00.60#ibcon#ireg 11 cls_cnt 2 2006.173.08:35:00.60#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.08:35:00.66#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.08:35:00.66#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.08:35:00.66#ibcon#enter wrdev, iclass 22, count 2 2006.173.08:35:00.66#ibcon#first serial, iclass 22, count 2 2006.173.08:35:00.66#ibcon#enter sib2, iclass 22, count 2 2006.173.08:35:00.66#ibcon#flushed, iclass 22, count 2 2006.173.08:35:00.66#ibcon#about to write, iclass 22, count 2 2006.173.08:35:00.66#ibcon#wrote, iclass 22, count 2 2006.173.08:35:00.66#ibcon#about to read 3, iclass 22, count 2 2006.173.08:35:00.68#ibcon#read 3, iclass 22, count 2 2006.173.08:35:00.68#ibcon#about to read 4, iclass 22, count 2 2006.173.08:35:00.68#ibcon#read 4, iclass 22, count 2 2006.173.08:35:00.68#ibcon#about to read 5, iclass 22, count 2 2006.173.08:35:00.68#ibcon#read 5, iclass 22, count 2 2006.173.08:35:00.68#ibcon#about to read 6, iclass 22, count 2 2006.173.08:35:00.68#ibcon#read 6, iclass 22, count 2 2006.173.08:35:00.68#ibcon#end of sib2, iclass 22, count 2 2006.173.08:35:00.68#ibcon#*mode == 0, iclass 22, count 2 2006.173.08:35:00.68#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.08:35:00.68#ibcon#[27=AT06-04\r\n] 2006.173.08:35:00.68#ibcon#*before write, iclass 22, count 2 2006.173.08:35:00.68#ibcon#enter sib2, iclass 22, count 2 2006.173.08:35:00.68#ibcon#flushed, iclass 22, count 2 2006.173.08:35:00.68#ibcon#about to write, iclass 22, count 2 2006.173.08:35:00.68#ibcon#wrote, iclass 22, count 2 2006.173.08:35:00.68#ibcon#about to read 3, iclass 22, count 2 2006.173.08:35:00.71#ibcon#read 3, iclass 22, count 2 2006.173.08:35:00.71#ibcon#about to read 4, iclass 22, count 2 2006.173.08:35:00.71#ibcon#read 4, iclass 22, count 2 2006.173.08:35:00.71#ibcon#about to read 5, iclass 22, count 2 2006.173.08:35:00.71#ibcon#read 5, iclass 22, count 2 2006.173.08:35:00.71#ibcon#about to read 6, iclass 22, count 2 2006.173.08:35:00.71#ibcon#read 6, iclass 22, count 2 2006.173.08:35:00.71#ibcon#end of sib2, iclass 22, count 2 2006.173.08:35:00.71#ibcon#*after write, iclass 22, count 2 2006.173.08:35:00.71#ibcon#*before return 0, iclass 22, count 2 2006.173.08:35:00.71#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.08:35:00.71#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.08:35:00.71#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.08:35:00.71#ibcon#ireg 7 cls_cnt 0 2006.173.08:35:00.71#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.08:35:00.83#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.08:35:00.83#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.08:35:00.83#ibcon#enter wrdev, iclass 22, count 0 2006.173.08:35:00.83#ibcon#first serial, iclass 22, count 0 2006.173.08:35:00.83#ibcon#enter sib2, iclass 22, count 0 2006.173.08:35:00.83#ibcon#flushed, iclass 22, count 0 2006.173.08:35:00.83#ibcon#about to write, iclass 22, count 0 2006.173.08:35:00.83#ibcon#wrote, iclass 22, count 0 2006.173.08:35:00.83#ibcon#about to read 3, iclass 22, count 0 2006.173.08:35:00.85#ibcon#read 3, iclass 22, count 0 2006.173.08:35:00.85#ibcon#about to read 4, iclass 22, count 0 2006.173.08:35:00.85#ibcon#read 4, iclass 22, count 0 2006.173.08:35:00.85#ibcon#about to read 5, iclass 22, count 0 2006.173.08:35:00.85#ibcon#read 5, iclass 22, count 0 2006.173.08:35:00.85#ibcon#about to read 6, iclass 22, count 0 2006.173.08:35:00.85#ibcon#read 6, iclass 22, count 0 2006.173.08:35:00.85#ibcon#end of sib2, iclass 22, count 0 2006.173.08:35:00.85#ibcon#*mode == 0, iclass 22, count 0 2006.173.08:35:00.85#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.08:35:00.85#ibcon#[27=USB\r\n] 2006.173.08:35:00.85#ibcon#*before write, iclass 22, count 0 2006.173.08:35:00.85#ibcon#enter sib2, iclass 22, count 0 2006.173.08:35:00.85#ibcon#flushed, iclass 22, count 0 2006.173.08:35:00.85#ibcon#about to write, iclass 22, count 0 2006.173.08:35:00.85#ibcon#wrote, iclass 22, count 0 2006.173.08:35:00.85#ibcon#about to read 3, iclass 22, count 0 2006.173.08:35:00.88#ibcon#read 3, iclass 22, count 0 2006.173.08:35:00.88#ibcon#about to read 4, iclass 22, count 0 2006.173.08:35:00.88#ibcon#read 4, iclass 22, count 0 2006.173.08:35:00.88#ibcon#about to read 5, iclass 22, count 0 2006.173.08:35:00.88#ibcon#read 5, iclass 22, count 0 2006.173.08:35:00.88#ibcon#about to read 6, iclass 22, count 0 2006.173.08:35:00.88#ibcon#read 6, iclass 22, count 0 2006.173.08:35:00.88#ibcon#end of sib2, iclass 22, count 0 2006.173.08:35:00.88#ibcon#*after write, iclass 22, count 0 2006.173.08:35:00.88#ibcon#*before return 0, iclass 22, count 0 2006.173.08:35:00.88#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.08:35:00.88#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.08:35:00.88#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.08:35:00.88#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.08:35:00.88$vck44/vblo=7,734.99 2006.173.08:35:00.88#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.08:35:00.88#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.08:35:00.88#ibcon#ireg 17 cls_cnt 0 2006.173.08:35:00.88#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.08:35:00.88#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.08:35:00.88#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.08:35:00.88#ibcon#enter wrdev, iclass 24, count 0 2006.173.08:35:00.88#ibcon#first serial, iclass 24, count 0 2006.173.08:35:00.88#ibcon#enter sib2, iclass 24, count 0 2006.173.08:35:00.88#ibcon#flushed, iclass 24, count 0 2006.173.08:35:00.88#ibcon#about to write, iclass 24, count 0 2006.173.08:35:00.88#ibcon#wrote, iclass 24, count 0 2006.173.08:35:00.88#ibcon#about to read 3, iclass 24, count 0 2006.173.08:35:00.90#ibcon#read 3, iclass 24, count 0 2006.173.08:35:00.90#ibcon#about to read 4, iclass 24, count 0 2006.173.08:35:00.90#ibcon#read 4, iclass 24, count 0 2006.173.08:35:00.90#ibcon#about to read 5, iclass 24, count 0 2006.173.08:35:00.90#ibcon#read 5, iclass 24, count 0 2006.173.08:35:00.90#ibcon#about to read 6, iclass 24, count 0 2006.173.08:35:00.90#ibcon#read 6, iclass 24, count 0 2006.173.08:35:00.90#ibcon#end of sib2, iclass 24, count 0 2006.173.08:35:00.90#ibcon#*mode == 0, iclass 24, count 0 2006.173.08:35:00.90#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.08:35:00.90#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.08:35:00.90#ibcon#*before write, iclass 24, count 0 2006.173.08:35:00.90#ibcon#enter sib2, iclass 24, count 0 2006.173.08:35:00.90#ibcon#flushed, iclass 24, count 0 2006.173.08:35:00.90#ibcon#about to write, iclass 24, count 0 2006.173.08:35:00.90#ibcon#wrote, iclass 24, count 0 2006.173.08:35:00.90#ibcon#about to read 3, iclass 24, count 0 2006.173.08:35:00.94#ibcon#read 3, iclass 24, count 0 2006.173.08:35:00.94#ibcon#about to read 4, iclass 24, count 0 2006.173.08:35:00.94#ibcon#read 4, iclass 24, count 0 2006.173.08:35:00.94#ibcon#about to read 5, iclass 24, count 0 2006.173.08:35:00.94#ibcon#read 5, iclass 24, count 0 2006.173.08:35:00.94#ibcon#about to read 6, iclass 24, count 0 2006.173.08:35:00.94#ibcon#read 6, iclass 24, count 0 2006.173.08:35:00.94#ibcon#end of sib2, iclass 24, count 0 2006.173.08:35:00.94#ibcon#*after write, iclass 24, count 0 2006.173.08:35:00.94#ibcon#*before return 0, iclass 24, count 0 2006.173.08:35:00.94#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.08:35:00.94#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.08:35:00.94#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.08:35:00.94#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.08:35:00.94$vck44/vb=7,4 2006.173.08:35:00.94#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.08:35:00.94#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.08:35:00.94#ibcon#ireg 11 cls_cnt 2 2006.173.08:35:00.94#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.08:35:01.00#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.08:35:01.00#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.08:35:01.00#ibcon#enter wrdev, iclass 26, count 2 2006.173.08:35:01.00#ibcon#first serial, iclass 26, count 2 2006.173.08:35:01.00#ibcon#enter sib2, iclass 26, count 2 2006.173.08:35:01.00#ibcon#flushed, iclass 26, count 2 2006.173.08:35:01.00#ibcon#about to write, iclass 26, count 2 2006.173.08:35:01.00#ibcon#wrote, iclass 26, count 2 2006.173.08:35:01.00#ibcon#about to read 3, iclass 26, count 2 2006.173.08:35:01.02#ibcon#read 3, iclass 26, count 2 2006.173.08:35:01.02#ibcon#about to read 4, iclass 26, count 2 2006.173.08:35:01.02#ibcon#read 4, iclass 26, count 2 2006.173.08:35:01.02#ibcon#about to read 5, iclass 26, count 2 2006.173.08:35:01.02#ibcon#read 5, iclass 26, count 2 2006.173.08:35:01.02#ibcon#about to read 6, iclass 26, count 2 2006.173.08:35:01.02#ibcon#read 6, iclass 26, count 2 2006.173.08:35:01.02#ibcon#end of sib2, iclass 26, count 2 2006.173.08:35:01.02#ibcon#*mode == 0, iclass 26, count 2 2006.173.08:35:01.02#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.08:35:01.02#ibcon#[27=AT07-04\r\n] 2006.173.08:35:01.02#ibcon#*before write, iclass 26, count 2 2006.173.08:35:01.02#ibcon#enter sib2, iclass 26, count 2 2006.173.08:35:01.02#ibcon#flushed, iclass 26, count 2 2006.173.08:35:01.02#ibcon#about to write, iclass 26, count 2 2006.173.08:35:01.02#ibcon#wrote, iclass 26, count 2 2006.173.08:35:01.02#ibcon#about to read 3, iclass 26, count 2 2006.173.08:35:01.05#ibcon#read 3, iclass 26, count 2 2006.173.08:35:01.05#ibcon#about to read 4, iclass 26, count 2 2006.173.08:35:01.05#ibcon#read 4, iclass 26, count 2 2006.173.08:35:01.05#ibcon#about to read 5, iclass 26, count 2 2006.173.08:35:01.05#ibcon#read 5, iclass 26, count 2 2006.173.08:35:01.05#ibcon#about to read 6, iclass 26, count 2 2006.173.08:35:01.05#ibcon#read 6, iclass 26, count 2 2006.173.08:35:01.05#ibcon#end of sib2, iclass 26, count 2 2006.173.08:35:01.05#ibcon#*after write, iclass 26, count 2 2006.173.08:35:01.05#ibcon#*before return 0, iclass 26, count 2 2006.173.08:35:01.05#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.08:35:01.05#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.08:35:01.05#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.08:35:01.05#ibcon#ireg 7 cls_cnt 0 2006.173.08:35:01.05#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.08:35:01.17#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.08:35:01.17#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.08:35:01.17#ibcon#enter wrdev, iclass 26, count 0 2006.173.08:35:01.17#ibcon#first serial, iclass 26, count 0 2006.173.08:35:01.17#ibcon#enter sib2, iclass 26, count 0 2006.173.08:35:01.17#ibcon#flushed, iclass 26, count 0 2006.173.08:35:01.17#ibcon#about to write, iclass 26, count 0 2006.173.08:35:01.17#ibcon#wrote, iclass 26, count 0 2006.173.08:35:01.17#ibcon#about to read 3, iclass 26, count 0 2006.173.08:35:01.19#ibcon#read 3, iclass 26, count 0 2006.173.08:35:01.19#ibcon#about to read 4, iclass 26, count 0 2006.173.08:35:01.19#ibcon#read 4, iclass 26, count 0 2006.173.08:35:01.19#ibcon#about to read 5, iclass 26, count 0 2006.173.08:35:01.19#ibcon#read 5, iclass 26, count 0 2006.173.08:35:01.19#ibcon#about to read 6, iclass 26, count 0 2006.173.08:35:01.19#ibcon#read 6, iclass 26, count 0 2006.173.08:35:01.19#ibcon#end of sib2, iclass 26, count 0 2006.173.08:35:01.19#ibcon#*mode == 0, iclass 26, count 0 2006.173.08:35:01.19#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.08:35:01.19#ibcon#[27=USB\r\n] 2006.173.08:35:01.19#ibcon#*before write, iclass 26, count 0 2006.173.08:35:01.19#ibcon#enter sib2, iclass 26, count 0 2006.173.08:35:01.19#ibcon#flushed, iclass 26, count 0 2006.173.08:35:01.19#ibcon#about to write, iclass 26, count 0 2006.173.08:35:01.19#ibcon#wrote, iclass 26, count 0 2006.173.08:35:01.19#ibcon#about to read 3, iclass 26, count 0 2006.173.08:35:01.22#abcon#<5=/00 0.1 0.4 23.35 861003.9\r\n> 2006.173.08:35:01.22#ibcon#read 3, iclass 26, count 0 2006.173.08:35:01.22#ibcon#about to read 4, iclass 26, count 0 2006.173.08:35:01.22#ibcon#read 4, iclass 26, count 0 2006.173.08:35:01.22#ibcon#about to read 5, iclass 26, count 0 2006.173.08:35:01.22#ibcon#read 5, iclass 26, count 0 2006.173.08:35:01.22#ibcon#about to read 6, iclass 26, count 0 2006.173.08:35:01.22#ibcon#read 6, iclass 26, count 0 2006.173.08:35:01.22#ibcon#end of sib2, iclass 26, count 0 2006.173.08:35:01.22#ibcon#*after write, iclass 26, count 0 2006.173.08:35:01.22#ibcon#*before return 0, iclass 26, count 0 2006.173.08:35:01.22#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.08:35:01.22#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.08:35:01.22#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.08:35:01.22#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.08:35:01.22$vck44/vblo=8,744.99 2006.173.08:35:01.22#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.08:35:01.22#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.08:35:01.22#ibcon#ireg 17 cls_cnt 0 2006.173.08:35:01.22#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.08:35:01.22#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.08:35:01.22#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.08:35:01.22#ibcon#enter wrdev, iclass 31, count 0 2006.173.08:35:01.22#ibcon#first serial, iclass 31, count 0 2006.173.08:35:01.22#ibcon#enter sib2, iclass 31, count 0 2006.173.08:35:01.22#ibcon#flushed, iclass 31, count 0 2006.173.08:35:01.22#ibcon#about to write, iclass 31, count 0 2006.173.08:35:01.22#ibcon#wrote, iclass 31, count 0 2006.173.08:35:01.22#ibcon#about to read 3, iclass 31, count 0 2006.173.08:35:01.24#ibcon#read 3, iclass 31, count 0 2006.173.08:35:01.24#ibcon#about to read 4, iclass 31, count 0 2006.173.08:35:01.24#ibcon#read 4, iclass 31, count 0 2006.173.08:35:01.24#ibcon#about to read 5, iclass 31, count 0 2006.173.08:35:01.24#ibcon#read 5, iclass 31, count 0 2006.173.08:35:01.24#ibcon#about to read 6, iclass 31, count 0 2006.173.08:35:01.24#ibcon#read 6, iclass 31, count 0 2006.173.08:35:01.24#ibcon#end of sib2, iclass 31, count 0 2006.173.08:35:01.24#ibcon#*mode == 0, iclass 31, count 0 2006.173.08:35:01.24#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.08:35:01.24#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.08:35:01.24#ibcon#*before write, iclass 31, count 0 2006.173.08:35:01.24#ibcon#enter sib2, iclass 31, count 0 2006.173.08:35:01.24#ibcon#flushed, iclass 31, count 0 2006.173.08:35:01.24#ibcon#about to write, iclass 31, count 0 2006.173.08:35:01.24#ibcon#wrote, iclass 31, count 0 2006.173.08:35:01.24#ibcon#about to read 3, iclass 31, count 0 2006.173.08:35:01.24#abcon#{5=INTERFACE CLEAR} 2006.173.08:35:01.28#ibcon#read 3, iclass 31, count 0 2006.173.08:35:01.28#ibcon#about to read 4, iclass 31, count 0 2006.173.08:35:01.28#ibcon#read 4, iclass 31, count 0 2006.173.08:35:01.28#ibcon#about to read 5, iclass 31, count 0 2006.173.08:35:01.28#ibcon#read 5, iclass 31, count 0 2006.173.08:35:01.28#ibcon#about to read 6, iclass 31, count 0 2006.173.08:35:01.28#ibcon#read 6, iclass 31, count 0 2006.173.08:35:01.28#ibcon#end of sib2, iclass 31, count 0 2006.173.08:35:01.28#ibcon#*after write, iclass 31, count 0 2006.173.08:35:01.28#ibcon#*before return 0, iclass 31, count 0 2006.173.08:35:01.28#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.08:35:01.28#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.08:35:01.28#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.08:35:01.28#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.08:35:01.28$vck44/vb=8,4 2006.173.08:35:01.28#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.173.08:35:01.28#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.173.08:35:01.28#ibcon#ireg 11 cls_cnt 2 2006.173.08:35:01.28#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.08:35:01.30#abcon#[5=S1D000X0/0*\r\n] 2006.173.08:35:01.34#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.08:35:01.34#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.08:35:01.34#ibcon#enter wrdev, iclass 33, count 2 2006.173.08:35:01.34#ibcon#first serial, iclass 33, count 2 2006.173.08:35:01.34#ibcon#enter sib2, iclass 33, count 2 2006.173.08:35:01.34#ibcon#flushed, iclass 33, count 2 2006.173.08:35:01.34#ibcon#about to write, iclass 33, count 2 2006.173.08:35:01.34#ibcon#wrote, iclass 33, count 2 2006.173.08:35:01.34#ibcon#about to read 3, iclass 33, count 2 2006.173.08:35:01.36#ibcon#read 3, iclass 33, count 2 2006.173.08:35:01.36#ibcon#about to read 4, iclass 33, count 2 2006.173.08:35:01.36#ibcon#read 4, iclass 33, count 2 2006.173.08:35:01.36#ibcon#about to read 5, iclass 33, count 2 2006.173.08:35:01.36#ibcon#read 5, iclass 33, count 2 2006.173.08:35:01.36#ibcon#about to read 6, iclass 33, count 2 2006.173.08:35:01.36#ibcon#read 6, iclass 33, count 2 2006.173.08:35:01.36#ibcon#end of sib2, iclass 33, count 2 2006.173.08:35:01.36#ibcon#*mode == 0, iclass 33, count 2 2006.173.08:35:01.36#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.173.08:35:01.36#ibcon#[27=AT08-04\r\n] 2006.173.08:35:01.36#ibcon#*before write, iclass 33, count 2 2006.173.08:35:01.36#ibcon#enter sib2, iclass 33, count 2 2006.173.08:35:01.36#ibcon#flushed, iclass 33, count 2 2006.173.08:35:01.36#ibcon#about to write, iclass 33, count 2 2006.173.08:35:01.36#ibcon#wrote, iclass 33, count 2 2006.173.08:35:01.36#ibcon#about to read 3, iclass 33, count 2 2006.173.08:35:01.39#ibcon#read 3, iclass 33, count 2 2006.173.08:35:01.39#ibcon#about to read 4, iclass 33, count 2 2006.173.08:35:01.39#ibcon#read 4, iclass 33, count 2 2006.173.08:35:01.39#ibcon#about to read 5, iclass 33, count 2 2006.173.08:35:01.39#ibcon#read 5, iclass 33, count 2 2006.173.08:35:01.39#ibcon#about to read 6, iclass 33, count 2 2006.173.08:35:01.39#ibcon#read 6, iclass 33, count 2 2006.173.08:35:01.39#ibcon#end of sib2, iclass 33, count 2 2006.173.08:35:01.39#ibcon#*after write, iclass 33, count 2 2006.173.08:35:01.39#ibcon#*before return 0, iclass 33, count 2 2006.173.08:35:01.39#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.08:35:01.39#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.173.08:35:01.39#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.173.08:35:01.39#ibcon#ireg 7 cls_cnt 0 2006.173.08:35:01.39#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.08:35:01.51#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.08:35:01.51#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.08:35:01.51#ibcon#enter wrdev, iclass 33, count 0 2006.173.08:35:01.51#ibcon#first serial, iclass 33, count 0 2006.173.08:35:01.51#ibcon#enter sib2, iclass 33, count 0 2006.173.08:35:01.51#ibcon#flushed, iclass 33, count 0 2006.173.08:35:01.51#ibcon#about to write, iclass 33, count 0 2006.173.08:35:01.51#ibcon#wrote, iclass 33, count 0 2006.173.08:35:01.51#ibcon#about to read 3, iclass 33, count 0 2006.173.08:35:01.53#ibcon#read 3, iclass 33, count 0 2006.173.08:35:01.53#ibcon#about to read 4, iclass 33, count 0 2006.173.08:35:01.53#ibcon#read 4, iclass 33, count 0 2006.173.08:35:01.53#ibcon#about to read 5, iclass 33, count 0 2006.173.08:35:01.53#ibcon#read 5, iclass 33, count 0 2006.173.08:35:01.53#ibcon#about to read 6, iclass 33, count 0 2006.173.08:35:01.53#ibcon#read 6, iclass 33, count 0 2006.173.08:35:01.53#ibcon#end of sib2, iclass 33, count 0 2006.173.08:35:01.53#ibcon#*mode == 0, iclass 33, count 0 2006.173.08:35:01.53#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.08:35:01.53#ibcon#[27=USB\r\n] 2006.173.08:35:01.53#ibcon#*before write, iclass 33, count 0 2006.173.08:35:01.53#ibcon#enter sib2, iclass 33, count 0 2006.173.08:35:01.53#ibcon#flushed, iclass 33, count 0 2006.173.08:35:01.53#ibcon#about to write, iclass 33, count 0 2006.173.08:35:01.53#ibcon#wrote, iclass 33, count 0 2006.173.08:35:01.53#ibcon#about to read 3, iclass 33, count 0 2006.173.08:35:01.56#ibcon#read 3, iclass 33, count 0 2006.173.08:35:01.56#ibcon#about to read 4, iclass 33, count 0 2006.173.08:35:01.56#ibcon#read 4, iclass 33, count 0 2006.173.08:35:01.56#ibcon#about to read 5, iclass 33, count 0 2006.173.08:35:01.56#ibcon#read 5, iclass 33, count 0 2006.173.08:35:01.56#ibcon#about to read 6, iclass 33, count 0 2006.173.08:35:01.56#ibcon#read 6, iclass 33, count 0 2006.173.08:35:01.56#ibcon#end of sib2, iclass 33, count 0 2006.173.08:35:01.56#ibcon#*after write, iclass 33, count 0 2006.173.08:35:01.56#ibcon#*before return 0, iclass 33, count 0 2006.173.08:35:01.56#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.08:35:01.56#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.173.08:35:01.56#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.08:35:01.56#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.08:35:01.56$vck44/vabw=wide 2006.173.08:35:01.56#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.08:35:01.56#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.08:35:01.56#ibcon#ireg 8 cls_cnt 0 2006.173.08:35:01.56#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.08:35:01.56#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.08:35:01.56#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.08:35:01.56#ibcon#enter wrdev, iclass 36, count 0 2006.173.08:35:01.56#ibcon#first serial, iclass 36, count 0 2006.173.08:35:01.56#ibcon#enter sib2, iclass 36, count 0 2006.173.08:35:01.56#ibcon#flushed, iclass 36, count 0 2006.173.08:35:01.56#ibcon#about to write, iclass 36, count 0 2006.173.08:35:01.56#ibcon#wrote, iclass 36, count 0 2006.173.08:35:01.56#ibcon#about to read 3, iclass 36, count 0 2006.173.08:35:01.58#ibcon#read 3, iclass 36, count 0 2006.173.08:35:01.58#ibcon#about to read 4, iclass 36, count 0 2006.173.08:35:01.58#ibcon#read 4, iclass 36, count 0 2006.173.08:35:01.58#ibcon#about to read 5, iclass 36, count 0 2006.173.08:35:01.58#ibcon#read 5, iclass 36, count 0 2006.173.08:35:01.58#ibcon#about to read 6, iclass 36, count 0 2006.173.08:35:01.58#ibcon#read 6, iclass 36, count 0 2006.173.08:35:01.58#ibcon#end of sib2, iclass 36, count 0 2006.173.08:35:01.58#ibcon#*mode == 0, iclass 36, count 0 2006.173.08:35:01.58#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.08:35:01.58#ibcon#[25=BW32\r\n] 2006.173.08:35:01.58#ibcon#*before write, iclass 36, count 0 2006.173.08:35:01.58#ibcon#enter sib2, iclass 36, count 0 2006.173.08:35:01.58#ibcon#flushed, iclass 36, count 0 2006.173.08:35:01.58#ibcon#about to write, iclass 36, count 0 2006.173.08:35:01.58#ibcon#wrote, iclass 36, count 0 2006.173.08:35:01.58#ibcon#about to read 3, iclass 36, count 0 2006.173.08:35:01.61#ibcon#read 3, iclass 36, count 0 2006.173.08:35:01.61#ibcon#about to read 4, iclass 36, count 0 2006.173.08:35:01.61#ibcon#read 4, iclass 36, count 0 2006.173.08:35:01.61#ibcon#about to read 5, iclass 36, count 0 2006.173.08:35:01.61#ibcon#read 5, iclass 36, count 0 2006.173.08:35:01.61#ibcon#about to read 6, iclass 36, count 0 2006.173.08:35:01.61#ibcon#read 6, iclass 36, count 0 2006.173.08:35:01.61#ibcon#end of sib2, iclass 36, count 0 2006.173.08:35:01.61#ibcon#*after write, iclass 36, count 0 2006.173.08:35:01.61#ibcon#*before return 0, iclass 36, count 0 2006.173.08:35:01.61#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.08:35:01.61#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.08:35:01.61#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.08:35:01.61#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.08:35:01.61$vck44/vbbw=wide 2006.173.08:35:01.61#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.08:35:01.61#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.08:35:01.61#ibcon#ireg 8 cls_cnt 0 2006.173.08:35:01.61#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.08:35:01.68#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.08:35:01.68#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.08:35:01.68#ibcon#enter wrdev, iclass 38, count 0 2006.173.08:35:01.68#ibcon#first serial, iclass 38, count 0 2006.173.08:35:01.68#ibcon#enter sib2, iclass 38, count 0 2006.173.08:35:01.68#ibcon#flushed, iclass 38, count 0 2006.173.08:35:01.68#ibcon#about to write, iclass 38, count 0 2006.173.08:35:01.68#ibcon#wrote, iclass 38, count 0 2006.173.08:35:01.68#ibcon#about to read 3, iclass 38, count 0 2006.173.08:35:01.70#ibcon#read 3, iclass 38, count 0 2006.173.08:35:01.70#ibcon#about to read 4, iclass 38, count 0 2006.173.08:35:01.70#ibcon#read 4, iclass 38, count 0 2006.173.08:35:01.70#ibcon#about to read 5, iclass 38, count 0 2006.173.08:35:01.70#ibcon#read 5, iclass 38, count 0 2006.173.08:35:01.70#ibcon#about to read 6, iclass 38, count 0 2006.173.08:35:01.70#ibcon#read 6, iclass 38, count 0 2006.173.08:35:01.70#ibcon#end of sib2, iclass 38, count 0 2006.173.08:35:01.70#ibcon#*mode == 0, iclass 38, count 0 2006.173.08:35:01.70#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.08:35:01.70#ibcon#[27=BW32\r\n] 2006.173.08:35:01.70#ibcon#*before write, iclass 38, count 0 2006.173.08:35:01.70#ibcon#enter sib2, iclass 38, count 0 2006.173.08:35:01.70#ibcon#flushed, iclass 38, count 0 2006.173.08:35:01.70#ibcon#about to write, iclass 38, count 0 2006.173.08:35:01.70#ibcon#wrote, iclass 38, count 0 2006.173.08:35:01.70#ibcon#about to read 3, iclass 38, count 0 2006.173.08:35:01.73#ibcon#read 3, iclass 38, count 0 2006.173.08:35:01.73#ibcon#about to read 4, iclass 38, count 0 2006.173.08:35:01.73#ibcon#read 4, iclass 38, count 0 2006.173.08:35:01.73#ibcon#about to read 5, iclass 38, count 0 2006.173.08:35:01.73#ibcon#read 5, iclass 38, count 0 2006.173.08:35:01.73#ibcon#about to read 6, iclass 38, count 0 2006.173.08:35:01.73#ibcon#read 6, iclass 38, count 0 2006.173.08:35:01.73#ibcon#end of sib2, iclass 38, count 0 2006.173.08:35:01.73#ibcon#*after write, iclass 38, count 0 2006.173.08:35:01.73#ibcon#*before return 0, iclass 38, count 0 2006.173.08:35:01.73#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.08:35:01.73#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.08:35:01.73#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.08:35:01.73#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.08:35:01.73$setupk4/ifdk4 2006.173.08:35:01.73$ifdk4/lo= 2006.173.08:35:01.73$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.08:35:01.73$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.08:35:01.73$ifdk4/patch= 2006.173.08:35:01.73$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.08:35:01.73$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.08:35:01.74$setupk4/!*+20s 2006.173.08:35:11.39#abcon#<5=/00 0.1 0.4 23.34 861004.0\r\n> 2006.173.08:35:11.41#abcon#{5=INTERFACE CLEAR} 2006.173.08:35:11.47#abcon#[5=S1D000X0/0*\r\n] 2006.173.08:35:16.25$setupk4/"tpicd 2006.173.08:35:16.25$setupk4/echo=off 2006.173.08:35:16.25$setupk4/xlog=off 2006.173.08:35:16.25:!2006.173.08:41:16 2006.173.08:35:20.13#trakl#Source acquired 2006.173.08:35:22.13#flagr#flagr/antenna,acquired 2006.173.08:41:16.00:preob 2006.173.08:41:17.14/onsource/TRACKING 2006.173.08:41:17.14:!2006.173.08:41:26 2006.173.08:41:26.00:"tape 2006.173.08:41:26.00:"st=record 2006.173.08:41:26.00:data_valid=on 2006.173.08:41:26.00:midob 2006.173.08:41:26.14/onsource/TRACKING 2006.173.08:41:26.14/wx/23.21,1003.9,86 2006.173.08:41:26.20/cable/+6.4994E-03 2006.173.08:41:27.29/va/01,07,usb,yes,43,46 2006.173.08:41:27.29/va/02,06,usb,yes,43,44 2006.173.08:41:27.29/va/03,05,usb,yes,54,57 2006.173.08:41:27.29/va/04,06,usb,yes,44,46 2006.173.08:41:27.29/va/05,04,usb,yes,35,36 2006.173.08:41:27.29/va/06,03,usb,yes,48,48 2006.173.08:41:27.29/va/07,04,usb,yes,39,41 2006.173.08:41:27.29/va/08,04,usb,yes,34,40 2006.173.08:41:27.52/valo/01,524.99,yes,locked 2006.173.08:41:27.52/valo/02,534.99,yes,locked 2006.173.08:41:27.52/valo/03,564.99,yes,locked 2006.173.08:41:27.52/valo/04,624.99,yes,locked 2006.173.08:41:27.52/valo/05,734.99,yes,locked 2006.173.08:41:27.52/valo/06,814.99,yes,locked 2006.173.08:41:27.52/valo/07,864.99,yes,locked 2006.173.08:41:27.52/valo/08,884.99,yes,locked 2006.173.08:41:28.61/vb/01,04,usb,yes,32,35 2006.173.08:41:28.61/vb/02,04,usb,yes,34,40 2006.173.08:41:28.61/vb/03,04,usb,yes,31,35 2006.173.08:41:28.61/vb/04,04,usb,yes,36,35 2006.173.08:41:28.61/vb/05,04,usb,yes,28,31 2006.173.08:41:28.61/vb/06,04,usb,yes,33,29 2006.173.08:41:28.61/vb/07,04,usb,yes,33,33 2006.173.08:41:28.61/vb/08,04,usb,yes,30,34 2006.173.08:41:28.84/vblo/01,629.99,yes,locked 2006.173.08:41:28.84/vblo/02,634.99,yes,locked 2006.173.08:41:28.84/vblo/03,649.99,yes,locked 2006.173.08:41:28.84/vblo/04,679.99,yes,locked 2006.173.08:41:28.84/vblo/05,709.99,yes,locked 2006.173.08:41:28.84/vblo/06,719.99,yes,locked 2006.173.08:41:28.84/vblo/07,734.99,yes,locked 2006.173.08:41:28.84/vblo/08,744.99,yes,locked 2006.173.08:41:28.99/vabw/8 2006.173.08:41:29.14/vbbw/8 2006.173.08:41:29.27/xfe/off,on,15.2 2006.173.08:41:29.64/ifatt/23,28,28,28 2006.173.08:41:30.08/fmout-gps/S +3.95E-07 2006.173.08:41:30.12:!2006.173.08:43:46 2006.173.08:43:46.00:data_valid=off 2006.173.08:43:46.00:"et 2006.173.08:43:46.00:!+3s 2006.173.08:43:49.01:"tape 2006.173.08:43:49.01:postob 2006.173.08:43:49.17/cable/+6.4999E-03 2006.173.08:43:49.17/wx/23.18,1004.0,87 2006.173.08:43:50.07/fmout-gps/S +3.96E-07 2006.173.08:43:50.07:scan_name=173-0844,jd0606,360 2006.173.08:43:50.07:source=1308+326,131028.66,322043.8,2000.0,ccw 2006.173.08:43:51.13#flagr#flagr/antenna,new-source 2006.173.08:43:51.13:checkk5 2006.173.08:43:51.54/chk_autoobs//k5ts1/ autoobs is running! 2006.173.08:43:51.93/chk_autoobs//k5ts2/ autoobs is running! 2006.173.08:43:52.33/chk_autoobs//k5ts3/ autoobs is running! 2006.173.08:43:52.72/chk_autoobs//k5ts4/ autoobs is running! 2006.173.08:43:53.11/chk_obsdata//k5ts1/T1730841??a.dat file size is correct (nominal:560MB, actual:556MB). 2006.173.08:43:53.50/chk_obsdata//k5ts2/T1730841??b.dat file size is correct (nominal:560MB, actual:556MB). 2006.173.08:43:53.89/chk_obsdata//k5ts3/T1730841??c.dat file size is correct (nominal:560MB, actual:556MB). 2006.173.08:43:54.30/chk_obsdata//k5ts4/T1730841??d.dat file size is correct (nominal:560MB, actual:556MB). 2006.173.08:43:55.04/k5log//k5ts1_log_newline 2006.173.08:43:55.74/k5log//k5ts2_log_newline 2006.173.08:43:56.46/k5log//k5ts3_log_newline 2006.173.08:43:57.14/k5log//k5ts4_log_newline 2006.173.08:43:57.16/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.08:43:57.16:setupk4=1 2006.173.08:43:57.16$setupk4/echo=on 2006.173.08:43:57.16$setupk4/pcalon 2006.173.08:43:57.16$pcalon/"no phase cal control is implemented here 2006.173.08:43:57.16$setupk4/"tpicd=stop 2006.173.08:43:57.16$setupk4/"rec=synch_on 2006.173.08:43:57.16$setupk4/"rec_mode=128 2006.173.08:43:57.16$setupk4/!* 2006.173.08:43:57.16$setupk4/recpk4 2006.173.08:43:57.16$recpk4/recpatch= 2006.173.08:43:57.17$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.08:43:57.17$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.08:43:57.17$setupk4/vck44 2006.173.08:43:57.17$vck44/valo=1,524.99 2006.173.08:43:57.17#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.08:43:57.17#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.08:43:57.17#ibcon#ireg 17 cls_cnt 0 2006.173.08:43:57.17#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.08:43:57.17#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.08:43:57.17#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.08:43:57.17#ibcon#enter wrdev, iclass 35, count 0 2006.173.08:43:57.17#ibcon#first serial, iclass 35, count 0 2006.173.08:43:57.17#ibcon#enter sib2, iclass 35, count 0 2006.173.08:43:57.17#ibcon#flushed, iclass 35, count 0 2006.173.08:43:57.17#ibcon#about to write, iclass 35, count 0 2006.173.08:43:57.17#ibcon#wrote, iclass 35, count 0 2006.173.08:43:57.17#ibcon#about to read 3, iclass 35, count 0 2006.173.08:43:57.19#ibcon#read 3, iclass 35, count 0 2006.173.08:43:57.19#ibcon#about to read 4, iclass 35, count 0 2006.173.08:43:57.19#ibcon#read 4, iclass 35, count 0 2006.173.08:43:57.19#ibcon#about to read 5, iclass 35, count 0 2006.173.08:43:57.19#ibcon#read 5, iclass 35, count 0 2006.173.08:43:57.19#ibcon#about to read 6, iclass 35, count 0 2006.173.08:43:57.19#ibcon#read 6, iclass 35, count 0 2006.173.08:43:57.19#ibcon#end of sib2, iclass 35, count 0 2006.173.08:43:57.19#ibcon#*mode == 0, iclass 35, count 0 2006.173.08:43:57.19#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.08:43:57.19#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.08:43:57.19#ibcon#*before write, iclass 35, count 0 2006.173.08:43:57.19#ibcon#enter sib2, iclass 35, count 0 2006.173.08:43:57.19#ibcon#flushed, iclass 35, count 0 2006.173.08:43:57.19#ibcon#about to write, iclass 35, count 0 2006.173.08:43:57.19#ibcon#wrote, iclass 35, count 0 2006.173.08:43:57.19#ibcon#about to read 3, iclass 35, count 0 2006.173.08:43:57.24#ibcon#read 3, iclass 35, count 0 2006.173.08:43:57.24#ibcon#about to read 4, iclass 35, count 0 2006.173.08:43:57.24#ibcon#read 4, iclass 35, count 0 2006.173.08:43:57.24#ibcon#about to read 5, iclass 35, count 0 2006.173.08:43:57.24#ibcon#read 5, iclass 35, count 0 2006.173.08:43:57.24#ibcon#about to read 6, iclass 35, count 0 2006.173.08:43:57.24#ibcon#read 6, iclass 35, count 0 2006.173.08:43:57.24#ibcon#end of sib2, iclass 35, count 0 2006.173.08:43:57.24#ibcon#*after write, iclass 35, count 0 2006.173.08:43:57.24#ibcon#*before return 0, iclass 35, count 0 2006.173.08:43:57.24#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.08:43:57.24#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.08:43:57.24#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.08:43:57.24#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.08:43:57.24$vck44/va=1,7 2006.173.08:43:57.24#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.173.08:43:57.24#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.173.08:43:57.24#ibcon#ireg 11 cls_cnt 2 2006.173.08:43:57.24#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.08:43:57.24#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.08:43:57.24#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.08:43:57.24#ibcon#enter wrdev, iclass 37, count 2 2006.173.08:43:57.24#ibcon#first serial, iclass 37, count 2 2006.173.08:43:57.24#ibcon#enter sib2, iclass 37, count 2 2006.173.08:43:57.24#ibcon#flushed, iclass 37, count 2 2006.173.08:43:57.24#ibcon#about to write, iclass 37, count 2 2006.173.08:43:57.24#ibcon#wrote, iclass 37, count 2 2006.173.08:43:57.24#ibcon#about to read 3, iclass 37, count 2 2006.173.08:43:57.26#ibcon#read 3, iclass 37, count 2 2006.173.08:43:57.26#ibcon#about to read 4, iclass 37, count 2 2006.173.08:43:57.26#ibcon#read 4, iclass 37, count 2 2006.173.08:43:57.26#ibcon#about to read 5, iclass 37, count 2 2006.173.08:43:57.26#ibcon#read 5, iclass 37, count 2 2006.173.08:43:57.26#ibcon#about to read 6, iclass 37, count 2 2006.173.08:43:57.26#ibcon#read 6, iclass 37, count 2 2006.173.08:43:57.26#ibcon#end of sib2, iclass 37, count 2 2006.173.08:43:57.26#ibcon#*mode == 0, iclass 37, count 2 2006.173.08:43:57.26#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.173.08:43:57.26#ibcon#[25=AT01-07\r\n] 2006.173.08:43:57.26#ibcon#*before write, iclass 37, count 2 2006.173.08:43:57.26#ibcon#enter sib2, iclass 37, count 2 2006.173.08:43:57.26#ibcon#flushed, iclass 37, count 2 2006.173.08:43:57.26#ibcon#about to write, iclass 37, count 2 2006.173.08:43:57.26#ibcon#wrote, iclass 37, count 2 2006.173.08:43:57.26#ibcon#about to read 3, iclass 37, count 2 2006.173.08:43:57.29#ibcon#read 3, iclass 37, count 2 2006.173.08:43:57.29#ibcon#about to read 4, iclass 37, count 2 2006.173.08:43:57.29#ibcon#read 4, iclass 37, count 2 2006.173.08:43:57.29#ibcon#about to read 5, iclass 37, count 2 2006.173.08:43:57.29#ibcon#read 5, iclass 37, count 2 2006.173.08:43:57.29#ibcon#about to read 6, iclass 37, count 2 2006.173.08:43:57.29#ibcon#read 6, iclass 37, count 2 2006.173.08:43:57.29#ibcon#end of sib2, iclass 37, count 2 2006.173.08:43:57.29#ibcon#*after write, iclass 37, count 2 2006.173.08:43:57.29#ibcon#*before return 0, iclass 37, count 2 2006.173.08:43:57.29#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.08:43:57.29#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.173.08:43:57.29#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.173.08:43:57.29#ibcon#ireg 7 cls_cnt 0 2006.173.08:43:57.29#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.08:43:57.41#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.08:43:57.41#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.08:43:57.41#ibcon#enter wrdev, iclass 37, count 0 2006.173.08:43:57.41#ibcon#first serial, iclass 37, count 0 2006.173.08:43:57.41#ibcon#enter sib2, iclass 37, count 0 2006.173.08:43:57.41#ibcon#flushed, iclass 37, count 0 2006.173.08:43:57.41#ibcon#about to write, iclass 37, count 0 2006.173.08:43:57.41#ibcon#wrote, iclass 37, count 0 2006.173.08:43:57.41#ibcon#about to read 3, iclass 37, count 0 2006.173.08:43:57.43#ibcon#read 3, iclass 37, count 0 2006.173.08:43:57.43#ibcon#about to read 4, iclass 37, count 0 2006.173.08:43:57.43#ibcon#read 4, iclass 37, count 0 2006.173.08:43:57.43#ibcon#about to read 5, iclass 37, count 0 2006.173.08:43:57.43#ibcon#read 5, iclass 37, count 0 2006.173.08:43:57.43#ibcon#about to read 6, iclass 37, count 0 2006.173.08:43:57.43#ibcon#read 6, iclass 37, count 0 2006.173.08:43:57.43#ibcon#end of sib2, iclass 37, count 0 2006.173.08:43:57.43#ibcon#*mode == 0, iclass 37, count 0 2006.173.08:43:57.43#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.08:43:57.43#ibcon#[25=USB\r\n] 2006.173.08:43:57.43#ibcon#*before write, iclass 37, count 0 2006.173.08:43:57.43#ibcon#enter sib2, iclass 37, count 0 2006.173.08:43:57.43#ibcon#flushed, iclass 37, count 0 2006.173.08:43:57.43#ibcon#about to write, iclass 37, count 0 2006.173.08:43:57.43#ibcon#wrote, iclass 37, count 0 2006.173.08:43:57.43#ibcon#about to read 3, iclass 37, count 0 2006.173.08:43:57.46#ibcon#read 3, iclass 37, count 0 2006.173.08:43:57.46#ibcon#about to read 4, iclass 37, count 0 2006.173.08:43:57.46#ibcon#read 4, iclass 37, count 0 2006.173.08:43:57.46#ibcon#about to read 5, iclass 37, count 0 2006.173.08:43:57.46#ibcon#read 5, iclass 37, count 0 2006.173.08:43:57.46#ibcon#about to read 6, iclass 37, count 0 2006.173.08:43:57.46#ibcon#read 6, iclass 37, count 0 2006.173.08:43:57.46#ibcon#end of sib2, iclass 37, count 0 2006.173.08:43:57.46#ibcon#*after write, iclass 37, count 0 2006.173.08:43:57.46#ibcon#*before return 0, iclass 37, count 0 2006.173.08:43:57.46#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.08:43:57.46#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.173.08:43:57.46#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.08:43:57.46#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.08:43:57.46$vck44/valo=2,534.99 2006.173.08:43:57.46#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.08:43:57.46#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.08:43:57.46#ibcon#ireg 17 cls_cnt 0 2006.173.08:43:57.46#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.08:43:57.46#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.08:43:57.46#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.08:43:57.46#ibcon#enter wrdev, iclass 39, count 0 2006.173.08:43:57.46#ibcon#first serial, iclass 39, count 0 2006.173.08:43:57.46#ibcon#enter sib2, iclass 39, count 0 2006.173.08:43:57.46#ibcon#flushed, iclass 39, count 0 2006.173.08:43:57.46#ibcon#about to write, iclass 39, count 0 2006.173.08:43:57.46#ibcon#wrote, iclass 39, count 0 2006.173.08:43:57.46#ibcon#about to read 3, iclass 39, count 0 2006.173.08:43:57.48#ibcon#read 3, iclass 39, count 0 2006.173.08:43:57.48#ibcon#about to read 4, iclass 39, count 0 2006.173.08:43:57.48#ibcon#read 4, iclass 39, count 0 2006.173.08:43:57.48#ibcon#about to read 5, iclass 39, count 0 2006.173.08:43:57.48#ibcon#read 5, iclass 39, count 0 2006.173.08:43:57.48#ibcon#about to read 6, iclass 39, count 0 2006.173.08:43:57.48#ibcon#read 6, iclass 39, count 0 2006.173.08:43:57.48#ibcon#end of sib2, iclass 39, count 0 2006.173.08:43:57.48#ibcon#*mode == 0, iclass 39, count 0 2006.173.08:43:57.48#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.08:43:57.48#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.08:43:57.48#ibcon#*before write, iclass 39, count 0 2006.173.08:43:57.48#ibcon#enter sib2, iclass 39, count 0 2006.173.08:43:57.48#ibcon#flushed, iclass 39, count 0 2006.173.08:43:57.48#ibcon#about to write, iclass 39, count 0 2006.173.08:43:57.48#ibcon#wrote, iclass 39, count 0 2006.173.08:43:57.48#ibcon#about to read 3, iclass 39, count 0 2006.173.08:43:57.52#ibcon#read 3, iclass 39, count 0 2006.173.08:43:57.52#ibcon#about to read 4, iclass 39, count 0 2006.173.08:43:57.52#ibcon#read 4, iclass 39, count 0 2006.173.08:43:57.52#ibcon#about to read 5, iclass 39, count 0 2006.173.08:43:57.52#ibcon#read 5, iclass 39, count 0 2006.173.08:43:57.52#ibcon#about to read 6, iclass 39, count 0 2006.173.08:43:57.52#ibcon#read 6, iclass 39, count 0 2006.173.08:43:57.52#ibcon#end of sib2, iclass 39, count 0 2006.173.08:43:57.52#ibcon#*after write, iclass 39, count 0 2006.173.08:43:57.52#ibcon#*before return 0, iclass 39, count 0 2006.173.08:43:57.52#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.08:43:57.52#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.08:43:57.52#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.08:43:57.52#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.08:43:57.52$vck44/va=2,6 2006.173.08:43:57.52#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.08:43:57.52#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.08:43:57.52#ibcon#ireg 11 cls_cnt 2 2006.173.08:43:57.52#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.08:43:57.58#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.08:43:57.58#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.08:43:57.58#ibcon#enter wrdev, iclass 3, count 2 2006.173.08:43:57.58#ibcon#first serial, iclass 3, count 2 2006.173.08:43:57.58#ibcon#enter sib2, iclass 3, count 2 2006.173.08:43:57.58#ibcon#flushed, iclass 3, count 2 2006.173.08:43:57.58#ibcon#about to write, iclass 3, count 2 2006.173.08:43:57.58#ibcon#wrote, iclass 3, count 2 2006.173.08:43:57.58#ibcon#about to read 3, iclass 3, count 2 2006.173.08:43:57.60#ibcon#read 3, iclass 3, count 2 2006.173.08:43:57.60#ibcon#about to read 4, iclass 3, count 2 2006.173.08:43:57.60#ibcon#read 4, iclass 3, count 2 2006.173.08:43:57.60#ibcon#about to read 5, iclass 3, count 2 2006.173.08:43:57.60#ibcon#read 5, iclass 3, count 2 2006.173.08:43:57.60#ibcon#about to read 6, iclass 3, count 2 2006.173.08:43:57.60#ibcon#read 6, iclass 3, count 2 2006.173.08:43:57.60#ibcon#end of sib2, iclass 3, count 2 2006.173.08:43:57.60#ibcon#*mode == 0, iclass 3, count 2 2006.173.08:43:57.60#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.08:43:57.60#ibcon#[25=AT02-06\r\n] 2006.173.08:43:57.60#ibcon#*before write, iclass 3, count 2 2006.173.08:43:57.60#ibcon#enter sib2, iclass 3, count 2 2006.173.08:43:57.60#ibcon#flushed, iclass 3, count 2 2006.173.08:43:57.60#ibcon#about to write, iclass 3, count 2 2006.173.08:43:57.60#ibcon#wrote, iclass 3, count 2 2006.173.08:43:57.60#ibcon#about to read 3, iclass 3, count 2 2006.173.08:43:57.63#ibcon#read 3, iclass 3, count 2 2006.173.08:43:57.63#ibcon#about to read 4, iclass 3, count 2 2006.173.08:43:57.63#ibcon#read 4, iclass 3, count 2 2006.173.08:43:57.63#ibcon#about to read 5, iclass 3, count 2 2006.173.08:43:57.63#ibcon#read 5, iclass 3, count 2 2006.173.08:43:57.63#ibcon#about to read 6, iclass 3, count 2 2006.173.08:43:57.63#ibcon#read 6, iclass 3, count 2 2006.173.08:43:57.63#ibcon#end of sib2, iclass 3, count 2 2006.173.08:43:57.63#ibcon#*after write, iclass 3, count 2 2006.173.08:43:57.63#ibcon#*before return 0, iclass 3, count 2 2006.173.08:43:57.63#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.08:43:57.63#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.08:43:57.63#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.08:43:57.63#ibcon#ireg 7 cls_cnt 0 2006.173.08:43:57.63#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.08:43:57.75#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.08:43:57.75#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.08:43:57.75#ibcon#enter wrdev, iclass 3, count 0 2006.173.08:43:57.75#ibcon#first serial, iclass 3, count 0 2006.173.08:43:57.75#ibcon#enter sib2, iclass 3, count 0 2006.173.08:43:57.75#ibcon#flushed, iclass 3, count 0 2006.173.08:43:57.75#ibcon#about to write, iclass 3, count 0 2006.173.08:43:57.75#ibcon#wrote, iclass 3, count 0 2006.173.08:43:57.75#ibcon#about to read 3, iclass 3, count 0 2006.173.08:43:57.77#ibcon#read 3, iclass 3, count 0 2006.173.08:43:57.77#ibcon#about to read 4, iclass 3, count 0 2006.173.08:43:57.77#ibcon#read 4, iclass 3, count 0 2006.173.08:43:57.77#ibcon#about to read 5, iclass 3, count 0 2006.173.08:43:57.77#ibcon#read 5, iclass 3, count 0 2006.173.08:43:57.77#ibcon#about to read 6, iclass 3, count 0 2006.173.08:43:57.77#ibcon#read 6, iclass 3, count 0 2006.173.08:43:57.77#ibcon#end of sib2, iclass 3, count 0 2006.173.08:43:57.77#ibcon#*mode == 0, iclass 3, count 0 2006.173.08:43:57.77#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.08:43:57.77#ibcon#[25=USB\r\n] 2006.173.08:43:57.77#ibcon#*before write, iclass 3, count 0 2006.173.08:43:57.77#ibcon#enter sib2, iclass 3, count 0 2006.173.08:43:57.77#ibcon#flushed, iclass 3, count 0 2006.173.08:43:57.77#ibcon#about to write, iclass 3, count 0 2006.173.08:43:57.77#ibcon#wrote, iclass 3, count 0 2006.173.08:43:57.77#ibcon#about to read 3, iclass 3, count 0 2006.173.08:43:57.80#ibcon#read 3, iclass 3, count 0 2006.173.08:43:57.80#ibcon#about to read 4, iclass 3, count 0 2006.173.08:43:57.80#ibcon#read 4, iclass 3, count 0 2006.173.08:43:57.80#ibcon#about to read 5, iclass 3, count 0 2006.173.08:43:57.80#ibcon#read 5, iclass 3, count 0 2006.173.08:43:57.80#ibcon#about to read 6, iclass 3, count 0 2006.173.08:43:57.80#ibcon#read 6, iclass 3, count 0 2006.173.08:43:57.80#ibcon#end of sib2, iclass 3, count 0 2006.173.08:43:57.80#ibcon#*after write, iclass 3, count 0 2006.173.08:43:57.80#ibcon#*before return 0, iclass 3, count 0 2006.173.08:43:57.80#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.08:43:57.80#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.08:43:57.80#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.08:43:57.80#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.08:43:57.80$vck44/valo=3,564.99 2006.173.08:43:57.80#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.08:43:57.80#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.08:43:57.80#ibcon#ireg 17 cls_cnt 0 2006.173.08:43:57.80#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.08:43:57.80#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.08:43:57.80#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.08:43:57.80#ibcon#enter wrdev, iclass 5, count 0 2006.173.08:43:57.80#ibcon#first serial, iclass 5, count 0 2006.173.08:43:57.80#ibcon#enter sib2, iclass 5, count 0 2006.173.08:43:57.80#ibcon#flushed, iclass 5, count 0 2006.173.08:43:57.80#ibcon#about to write, iclass 5, count 0 2006.173.08:43:57.80#ibcon#wrote, iclass 5, count 0 2006.173.08:43:57.80#ibcon#about to read 3, iclass 5, count 0 2006.173.08:43:57.82#ibcon#read 3, iclass 5, count 0 2006.173.08:43:57.82#ibcon#about to read 4, iclass 5, count 0 2006.173.08:43:57.82#ibcon#read 4, iclass 5, count 0 2006.173.08:43:57.82#ibcon#about to read 5, iclass 5, count 0 2006.173.08:43:57.82#ibcon#read 5, iclass 5, count 0 2006.173.08:43:57.82#ibcon#about to read 6, iclass 5, count 0 2006.173.08:43:57.82#ibcon#read 6, iclass 5, count 0 2006.173.08:43:57.82#ibcon#end of sib2, iclass 5, count 0 2006.173.08:43:57.82#ibcon#*mode == 0, iclass 5, count 0 2006.173.08:43:57.82#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.08:43:57.82#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.08:43:57.82#ibcon#*before write, iclass 5, count 0 2006.173.08:43:57.82#ibcon#enter sib2, iclass 5, count 0 2006.173.08:43:57.82#ibcon#flushed, iclass 5, count 0 2006.173.08:43:57.82#ibcon#about to write, iclass 5, count 0 2006.173.08:43:57.82#ibcon#wrote, iclass 5, count 0 2006.173.08:43:57.82#ibcon#about to read 3, iclass 5, count 0 2006.173.08:43:57.86#ibcon#read 3, iclass 5, count 0 2006.173.08:43:57.86#ibcon#about to read 4, iclass 5, count 0 2006.173.08:43:57.86#ibcon#read 4, iclass 5, count 0 2006.173.08:43:57.86#ibcon#about to read 5, iclass 5, count 0 2006.173.08:43:57.86#ibcon#read 5, iclass 5, count 0 2006.173.08:43:57.86#ibcon#about to read 6, iclass 5, count 0 2006.173.08:43:57.86#ibcon#read 6, iclass 5, count 0 2006.173.08:43:57.86#ibcon#end of sib2, iclass 5, count 0 2006.173.08:43:57.86#ibcon#*after write, iclass 5, count 0 2006.173.08:43:57.86#ibcon#*before return 0, iclass 5, count 0 2006.173.08:43:57.86#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.08:43:57.86#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.08:43:57.86#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.08:43:57.86#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.08:43:57.86$vck44/va=3,5 2006.173.08:43:57.86#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.173.08:43:57.86#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.173.08:43:57.86#ibcon#ireg 11 cls_cnt 2 2006.173.08:43:57.86#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.08:43:57.92#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.08:43:57.92#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.08:43:57.92#ibcon#enter wrdev, iclass 7, count 2 2006.173.08:43:57.92#ibcon#first serial, iclass 7, count 2 2006.173.08:43:57.92#ibcon#enter sib2, iclass 7, count 2 2006.173.08:43:57.92#ibcon#flushed, iclass 7, count 2 2006.173.08:43:57.92#ibcon#about to write, iclass 7, count 2 2006.173.08:43:57.92#ibcon#wrote, iclass 7, count 2 2006.173.08:43:57.92#ibcon#about to read 3, iclass 7, count 2 2006.173.08:43:57.94#ibcon#read 3, iclass 7, count 2 2006.173.08:43:57.94#ibcon#about to read 4, iclass 7, count 2 2006.173.08:43:57.94#ibcon#read 4, iclass 7, count 2 2006.173.08:43:57.94#ibcon#about to read 5, iclass 7, count 2 2006.173.08:43:57.94#ibcon#read 5, iclass 7, count 2 2006.173.08:43:57.94#ibcon#about to read 6, iclass 7, count 2 2006.173.08:43:57.94#ibcon#read 6, iclass 7, count 2 2006.173.08:43:57.94#ibcon#end of sib2, iclass 7, count 2 2006.173.08:43:57.94#ibcon#*mode == 0, iclass 7, count 2 2006.173.08:43:57.94#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.173.08:43:57.94#ibcon#[25=AT03-05\r\n] 2006.173.08:43:57.94#ibcon#*before write, iclass 7, count 2 2006.173.08:43:57.94#ibcon#enter sib2, iclass 7, count 2 2006.173.08:43:57.94#ibcon#flushed, iclass 7, count 2 2006.173.08:43:57.94#ibcon#about to write, iclass 7, count 2 2006.173.08:43:57.94#ibcon#wrote, iclass 7, count 2 2006.173.08:43:57.94#ibcon#about to read 3, iclass 7, count 2 2006.173.08:43:57.97#ibcon#read 3, iclass 7, count 2 2006.173.08:43:57.97#ibcon#about to read 4, iclass 7, count 2 2006.173.08:43:57.97#ibcon#read 4, iclass 7, count 2 2006.173.08:43:57.97#ibcon#about to read 5, iclass 7, count 2 2006.173.08:43:57.97#ibcon#read 5, iclass 7, count 2 2006.173.08:43:57.97#ibcon#about to read 6, iclass 7, count 2 2006.173.08:43:57.97#ibcon#read 6, iclass 7, count 2 2006.173.08:43:57.97#ibcon#end of sib2, iclass 7, count 2 2006.173.08:43:57.97#ibcon#*after write, iclass 7, count 2 2006.173.08:43:57.97#ibcon#*before return 0, iclass 7, count 2 2006.173.08:43:57.97#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.08:43:57.97#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.173.08:43:57.97#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.173.08:43:57.97#ibcon#ireg 7 cls_cnt 0 2006.173.08:43:57.97#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.08:43:58.09#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.08:43:58.09#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.08:43:58.09#ibcon#enter wrdev, iclass 7, count 0 2006.173.08:43:58.09#ibcon#first serial, iclass 7, count 0 2006.173.08:43:58.09#ibcon#enter sib2, iclass 7, count 0 2006.173.08:43:58.09#ibcon#flushed, iclass 7, count 0 2006.173.08:43:58.09#ibcon#about to write, iclass 7, count 0 2006.173.08:43:58.09#ibcon#wrote, iclass 7, count 0 2006.173.08:43:58.09#ibcon#about to read 3, iclass 7, count 0 2006.173.08:43:58.11#ibcon#read 3, iclass 7, count 0 2006.173.08:43:58.11#ibcon#about to read 4, iclass 7, count 0 2006.173.08:43:58.11#ibcon#read 4, iclass 7, count 0 2006.173.08:43:58.11#ibcon#about to read 5, iclass 7, count 0 2006.173.08:43:58.11#ibcon#read 5, iclass 7, count 0 2006.173.08:43:58.11#ibcon#about to read 6, iclass 7, count 0 2006.173.08:43:58.11#ibcon#read 6, iclass 7, count 0 2006.173.08:43:58.11#ibcon#end of sib2, iclass 7, count 0 2006.173.08:43:58.11#ibcon#*mode == 0, iclass 7, count 0 2006.173.08:43:58.11#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.08:43:58.11#ibcon#[25=USB\r\n] 2006.173.08:43:58.11#ibcon#*before write, iclass 7, count 0 2006.173.08:43:58.11#ibcon#enter sib2, iclass 7, count 0 2006.173.08:43:58.11#ibcon#flushed, iclass 7, count 0 2006.173.08:43:58.11#ibcon#about to write, iclass 7, count 0 2006.173.08:43:58.11#ibcon#wrote, iclass 7, count 0 2006.173.08:43:58.11#ibcon#about to read 3, iclass 7, count 0 2006.173.08:43:58.14#ibcon#read 3, iclass 7, count 0 2006.173.08:43:58.14#ibcon#about to read 4, iclass 7, count 0 2006.173.08:43:58.14#ibcon#read 4, iclass 7, count 0 2006.173.08:43:58.14#ibcon#about to read 5, iclass 7, count 0 2006.173.08:43:58.14#ibcon#read 5, iclass 7, count 0 2006.173.08:43:58.14#ibcon#about to read 6, iclass 7, count 0 2006.173.08:43:58.14#ibcon#read 6, iclass 7, count 0 2006.173.08:43:58.14#ibcon#end of sib2, iclass 7, count 0 2006.173.08:43:58.14#ibcon#*after write, iclass 7, count 0 2006.173.08:43:58.14#ibcon#*before return 0, iclass 7, count 0 2006.173.08:43:58.14#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.08:43:58.14#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.173.08:43:58.14#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.08:43:58.14#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.08:43:58.14$vck44/valo=4,624.99 2006.173.08:43:58.14#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.08:43:58.14#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.08:43:58.14#ibcon#ireg 17 cls_cnt 0 2006.173.08:43:58.14#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.08:43:58.14#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.08:43:58.14#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.08:43:58.14#ibcon#enter wrdev, iclass 11, count 0 2006.173.08:43:58.14#ibcon#first serial, iclass 11, count 0 2006.173.08:43:58.14#ibcon#enter sib2, iclass 11, count 0 2006.173.08:43:58.14#ibcon#flushed, iclass 11, count 0 2006.173.08:43:58.14#ibcon#about to write, iclass 11, count 0 2006.173.08:43:58.14#ibcon#wrote, iclass 11, count 0 2006.173.08:43:58.14#ibcon#about to read 3, iclass 11, count 0 2006.173.08:43:58.16#ibcon#read 3, iclass 11, count 0 2006.173.08:43:58.16#ibcon#about to read 4, iclass 11, count 0 2006.173.08:43:58.16#ibcon#read 4, iclass 11, count 0 2006.173.08:43:58.16#ibcon#about to read 5, iclass 11, count 0 2006.173.08:43:58.16#ibcon#read 5, iclass 11, count 0 2006.173.08:43:58.16#ibcon#about to read 6, iclass 11, count 0 2006.173.08:43:58.16#ibcon#read 6, iclass 11, count 0 2006.173.08:43:58.16#ibcon#end of sib2, iclass 11, count 0 2006.173.08:43:58.16#ibcon#*mode == 0, iclass 11, count 0 2006.173.08:43:58.16#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.08:43:58.16#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.08:43:58.16#ibcon#*before write, iclass 11, count 0 2006.173.08:43:58.16#ibcon#enter sib2, iclass 11, count 0 2006.173.08:43:58.16#ibcon#flushed, iclass 11, count 0 2006.173.08:43:58.16#ibcon#about to write, iclass 11, count 0 2006.173.08:43:58.16#ibcon#wrote, iclass 11, count 0 2006.173.08:43:58.16#ibcon#about to read 3, iclass 11, count 0 2006.173.08:43:58.20#ibcon#read 3, iclass 11, count 0 2006.173.08:43:58.20#ibcon#about to read 4, iclass 11, count 0 2006.173.08:43:58.20#ibcon#read 4, iclass 11, count 0 2006.173.08:43:58.20#ibcon#about to read 5, iclass 11, count 0 2006.173.08:43:58.20#ibcon#read 5, iclass 11, count 0 2006.173.08:43:58.20#ibcon#about to read 6, iclass 11, count 0 2006.173.08:43:58.20#ibcon#read 6, iclass 11, count 0 2006.173.08:43:58.20#ibcon#end of sib2, iclass 11, count 0 2006.173.08:43:58.20#ibcon#*after write, iclass 11, count 0 2006.173.08:43:58.20#ibcon#*before return 0, iclass 11, count 0 2006.173.08:43:58.20#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.08:43:58.20#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.08:43:58.20#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.08:43:58.20#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.08:43:58.20$vck44/va=4,6 2006.173.08:43:58.20#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.173.08:43:58.20#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.173.08:43:58.20#ibcon#ireg 11 cls_cnt 2 2006.173.08:43:58.20#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.08:43:58.26#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.08:43:58.26#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.08:43:58.26#ibcon#enter wrdev, iclass 13, count 2 2006.173.08:43:58.26#ibcon#first serial, iclass 13, count 2 2006.173.08:43:58.26#ibcon#enter sib2, iclass 13, count 2 2006.173.08:43:58.26#ibcon#flushed, iclass 13, count 2 2006.173.08:43:58.26#ibcon#about to write, iclass 13, count 2 2006.173.08:43:58.26#ibcon#wrote, iclass 13, count 2 2006.173.08:43:58.26#ibcon#about to read 3, iclass 13, count 2 2006.173.08:43:58.28#ibcon#read 3, iclass 13, count 2 2006.173.08:43:58.28#ibcon#about to read 4, iclass 13, count 2 2006.173.08:43:58.28#ibcon#read 4, iclass 13, count 2 2006.173.08:43:58.28#ibcon#about to read 5, iclass 13, count 2 2006.173.08:43:58.28#ibcon#read 5, iclass 13, count 2 2006.173.08:43:58.28#ibcon#about to read 6, iclass 13, count 2 2006.173.08:43:58.28#ibcon#read 6, iclass 13, count 2 2006.173.08:43:58.28#ibcon#end of sib2, iclass 13, count 2 2006.173.08:43:58.28#ibcon#*mode == 0, iclass 13, count 2 2006.173.08:43:58.28#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.173.08:43:58.28#ibcon#[25=AT04-06\r\n] 2006.173.08:43:58.28#ibcon#*before write, iclass 13, count 2 2006.173.08:43:58.28#ibcon#enter sib2, iclass 13, count 2 2006.173.08:43:58.28#ibcon#flushed, iclass 13, count 2 2006.173.08:43:58.28#ibcon#about to write, iclass 13, count 2 2006.173.08:43:58.28#ibcon#wrote, iclass 13, count 2 2006.173.08:43:58.28#ibcon#about to read 3, iclass 13, count 2 2006.173.08:43:58.31#ibcon#read 3, iclass 13, count 2 2006.173.08:43:58.31#ibcon#about to read 4, iclass 13, count 2 2006.173.08:43:58.31#ibcon#read 4, iclass 13, count 2 2006.173.08:43:58.31#ibcon#about to read 5, iclass 13, count 2 2006.173.08:43:58.31#ibcon#read 5, iclass 13, count 2 2006.173.08:43:58.31#ibcon#about to read 6, iclass 13, count 2 2006.173.08:43:58.31#ibcon#read 6, iclass 13, count 2 2006.173.08:43:58.31#ibcon#end of sib2, iclass 13, count 2 2006.173.08:43:58.31#ibcon#*after write, iclass 13, count 2 2006.173.08:43:58.31#ibcon#*before return 0, iclass 13, count 2 2006.173.08:43:58.31#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.08:43:58.31#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.173.08:43:58.31#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.173.08:43:58.31#ibcon#ireg 7 cls_cnt 0 2006.173.08:43:58.31#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.08:43:58.43#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.08:43:58.43#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.08:43:58.43#ibcon#enter wrdev, iclass 13, count 0 2006.173.08:43:58.43#ibcon#first serial, iclass 13, count 0 2006.173.08:43:58.43#ibcon#enter sib2, iclass 13, count 0 2006.173.08:43:58.43#ibcon#flushed, iclass 13, count 0 2006.173.08:43:58.43#ibcon#about to write, iclass 13, count 0 2006.173.08:43:58.43#ibcon#wrote, iclass 13, count 0 2006.173.08:43:58.43#ibcon#about to read 3, iclass 13, count 0 2006.173.08:43:58.45#ibcon#read 3, iclass 13, count 0 2006.173.08:43:58.45#ibcon#about to read 4, iclass 13, count 0 2006.173.08:43:58.45#ibcon#read 4, iclass 13, count 0 2006.173.08:43:58.45#ibcon#about to read 5, iclass 13, count 0 2006.173.08:43:58.45#ibcon#read 5, iclass 13, count 0 2006.173.08:43:58.45#ibcon#about to read 6, iclass 13, count 0 2006.173.08:43:58.45#ibcon#read 6, iclass 13, count 0 2006.173.08:43:58.45#ibcon#end of sib2, iclass 13, count 0 2006.173.08:43:58.45#ibcon#*mode == 0, iclass 13, count 0 2006.173.08:43:58.45#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.08:43:58.45#ibcon#[25=USB\r\n] 2006.173.08:43:58.45#ibcon#*before write, iclass 13, count 0 2006.173.08:43:58.45#ibcon#enter sib2, iclass 13, count 0 2006.173.08:43:58.45#ibcon#flushed, iclass 13, count 0 2006.173.08:43:58.45#ibcon#about to write, iclass 13, count 0 2006.173.08:43:58.45#ibcon#wrote, iclass 13, count 0 2006.173.08:43:58.45#ibcon#about to read 3, iclass 13, count 0 2006.173.08:43:58.48#ibcon#read 3, iclass 13, count 0 2006.173.08:43:58.48#ibcon#about to read 4, iclass 13, count 0 2006.173.08:43:58.48#ibcon#read 4, iclass 13, count 0 2006.173.08:43:58.48#ibcon#about to read 5, iclass 13, count 0 2006.173.08:43:58.48#ibcon#read 5, iclass 13, count 0 2006.173.08:43:58.48#ibcon#about to read 6, iclass 13, count 0 2006.173.08:43:58.48#ibcon#read 6, iclass 13, count 0 2006.173.08:43:58.48#ibcon#end of sib2, iclass 13, count 0 2006.173.08:43:58.48#ibcon#*after write, iclass 13, count 0 2006.173.08:43:58.48#ibcon#*before return 0, iclass 13, count 0 2006.173.08:43:58.48#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.08:43:58.48#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.173.08:43:58.48#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.08:43:58.48#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.08:43:58.48$vck44/valo=5,734.99 2006.173.08:43:58.48#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.08:43:58.48#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.08:43:58.48#ibcon#ireg 17 cls_cnt 0 2006.173.08:43:58.48#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.08:43:58.48#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.08:43:58.48#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.08:43:58.48#ibcon#enter wrdev, iclass 15, count 0 2006.173.08:43:58.48#ibcon#first serial, iclass 15, count 0 2006.173.08:43:58.48#ibcon#enter sib2, iclass 15, count 0 2006.173.08:43:58.48#ibcon#flushed, iclass 15, count 0 2006.173.08:43:58.48#ibcon#about to write, iclass 15, count 0 2006.173.08:43:58.48#ibcon#wrote, iclass 15, count 0 2006.173.08:43:58.48#ibcon#about to read 3, iclass 15, count 0 2006.173.08:43:58.50#ibcon#read 3, iclass 15, count 0 2006.173.08:43:58.50#ibcon#about to read 4, iclass 15, count 0 2006.173.08:43:58.50#ibcon#read 4, iclass 15, count 0 2006.173.08:43:58.50#ibcon#about to read 5, iclass 15, count 0 2006.173.08:43:58.50#ibcon#read 5, iclass 15, count 0 2006.173.08:43:58.50#ibcon#about to read 6, iclass 15, count 0 2006.173.08:43:58.50#ibcon#read 6, iclass 15, count 0 2006.173.08:43:58.50#ibcon#end of sib2, iclass 15, count 0 2006.173.08:43:58.50#ibcon#*mode == 0, iclass 15, count 0 2006.173.08:43:58.50#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.08:43:58.50#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.08:43:58.50#ibcon#*before write, iclass 15, count 0 2006.173.08:43:58.50#ibcon#enter sib2, iclass 15, count 0 2006.173.08:43:58.50#ibcon#flushed, iclass 15, count 0 2006.173.08:43:58.50#ibcon#about to write, iclass 15, count 0 2006.173.08:43:58.50#ibcon#wrote, iclass 15, count 0 2006.173.08:43:58.50#ibcon#about to read 3, iclass 15, count 0 2006.173.08:43:58.54#ibcon#read 3, iclass 15, count 0 2006.173.08:43:58.54#ibcon#about to read 4, iclass 15, count 0 2006.173.08:43:58.54#ibcon#read 4, iclass 15, count 0 2006.173.08:43:58.54#ibcon#about to read 5, iclass 15, count 0 2006.173.08:43:58.54#ibcon#read 5, iclass 15, count 0 2006.173.08:43:58.54#ibcon#about to read 6, iclass 15, count 0 2006.173.08:43:58.54#ibcon#read 6, iclass 15, count 0 2006.173.08:43:58.54#ibcon#end of sib2, iclass 15, count 0 2006.173.08:43:58.54#ibcon#*after write, iclass 15, count 0 2006.173.08:43:58.54#ibcon#*before return 0, iclass 15, count 0 2006.173.08:43:58.54#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.08:43:58.54#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.08:43:58.54#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.08:43:58.54#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.08:43:58.54$vck44/va=5,4 2006.173.08:43:58.54#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.08:43:58.54#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.08:43:58.54#ibcon#ireg 11 cls_cnt 2 2006.173.08:43:58.54#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.08:43:58.60#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.08:43:58.60#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.08:43:58.60#ibcon#enter wrdev, iclass 17, count 2 2006.173.08:43:58.60#ibcon#first serial, iclass 17, count 2 2006.173.08:43:58.60#ibcon#enter sib2, iclass 17, count 2 2006.173.08:43:58.60#ibcon#flushed, iclass 17, count 2 2006.173.08:43:58.60#ibcon#about to write, iclass 17, count 2 2006.173.08:43:58.60#ibcon#wrote, iclass 17, count 2 2006.173.08:43:58.60#ibcon#about to read 3, iclass 17, count 2 2006.173.08:43:58.62#ibcon#read 3, iclass 17, count 2 2006.173.08:43:58.62#ibcon#about to read 4, iclass 17, count 2 2006.173.08:43:58.62#ibcon#read 4, iclass 17, count 2 2006.173.08:43:58.62#ibcon#about to read 5, iclass 17, count 2 2006.173.08:43:58.62#ibcon#read 5, iclass 17, count 2 2006.173.08:43:58.62#ibcon#about to read 6, iclass 17, count 2 2006.173.08:43:58.62#ibcon#read 6, iclass 17, count 2 2006.173.08:43:58.62#ibcon#end of sib2, iclass 17, count 2 2006.173.08:43:58.62#ibcon#*mode == 0, iclass 17, count 2 2006.173.08:43:58.62#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.08:43:58.62#ibcon#[25=AT05-04\r\n] 2006.173.08:43:58.62#ibcon#*before write, iclass 17, count 2 2006.173.08:43:58.62#ibcon#enter sib2, iclass 17, count 2 2006.173.08:43:58.62#ibcon#flushed, iclass 17, count 2 2006.173.08:43:58.62#ibcon#about to write, iclass 17, count 2 2006.173.08:43:58.62#ibcon#wrote, iclass 17, count 2 2006.173.08:43:58.62#ibcon#about to read 3, iclass 17, count 2 2006.173.08:43:58.65#ibcon#read 3, iclass 17, count 2 2006.173.08:43:58.65#ibcon#about to read 4, iclass 17, count 2 2006.173.08:43:58.65#ibcon#read 4, iclass 17, count 2 2006.173.08:43:58.65#ibcon#about to read 5, iclass 17, count 2 2006.173.08:43:58.65#ibcon#read 5, iclass 17, count 2 2006.173.08:43:58.65#ibcon#about to read 6, iclass 17, count 2 2006.173.08:43:58.65#ibcon#read 6, iclass 17, count 2 2006.173.08:43:58.65#ibcon#end of sib2, iclass 17, count 2 2006.173.08:43:58.65#ibcon#*after write, iclass 17, count 2 2006.173.08:43:58.65#ibcon#*before return 0, iclass 17, count 2 2006.173.08:43:58.65#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.08:43:58.65#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.08:43:58.65#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.08:43:58.65#ibcon#ireg 7 cls_cnt 0 2006.173.08:43:58.65#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.08:43:58.77#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.08:43:58.77#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.08:43:58.77#ibcon#enter wrdev, iclass 17, count 0 2006.173.08:43:58.77#ibcon#first serial, iclass 17, count 0 2006.173.08:43:58.77#ibcon#enter sib2, iclass 17, count 0 2006.173.08:43:58.77#ibcon#flushed, iclass 17, count 0 2006.173.08:43:58.77#ibcon#about to write, iclass 17, count 0 2006.173.08:43:58.77#ibcon#wrote, iclass 17, count 0 2006.173.08:43:58.77#ibcon#about to read 3, iclass 17, count 0 2006.173.08:43:58.79#ibcon#read 3, iclass 17, count 0 2006.173.08:43:58.79#ibcon#about to read 4, iclass 17, count 0 2006.173.08:43:58.79#ibcon#read 4, iclass 17, count 0 2006.173.08:43:58.79#ibcon#about to read 5, iclass 17, count 0 2006.173.08:43:58.79#ibcon#read 5, iclass 17, count 0 2006.173.08:43:58.79#ibcon#about to read 6, iclass 17, count 0 2006.173.08:43:58.79#ibcon#read 6, iclass 17, count 0 2006.173.08:43:58.79#ibcon#end of sib2, iclass 17, count 0 2006.173.08:43:58.79#ibcon#*mode == 0, iclass 17, count 0 2006.173.08:43:58.79#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.08:43:58.79#ibcon#[25=USB\r\n] 2006.173.08:43:58.79#ibcon#*before write, iclass 17, count 0 2006.173.08:43:58.79#ibcon#enter sib2, iclass 17, count 0 2006.173.08:43:58.79#ibcon#flushed, iclass 17, count 0 2006.173.08:43:58.79#ibcon#about to write, iclass 17, count 0 2006.173.08:43:58.79#ibcon#wrote, iclass 17, count 0 2006.173.08:43:58.79#ibcon#about to read 3, iclass 17, count 0 2006.173.08:43:58.82#ibcon#read 3, iclass 17, count 0 2006.173.08:43:58.82#ibcon#about to read 4, iclass 17, count 0 2006.173.08:43:58.82#ibcon#read 4, iclass 17, count 0 2006.173.08:43:58.82#ibcon#about to read 5, iclass 17, count 0 2006.173.08:43:58.82#ibcon#read 5, iclass 17, count 0 2006.173.08:43:58.82#ibcon#about to read 6, iclass 17, count 0 2006.173.08:43:58.82#ibcon#read 6, iclass 17, count 0 2006.173.08:43:58.82#ibcon#end of sib2, iclass 17, count 0 2006.173.08:43:58.82#ibcon#*after write, iclass 17, count 0 2006.173.08:43:58.82#ibcon#*before return 0, iclass 17, count 0 2006.173.08:43:58.82#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.08:43:58.82#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.08:43:58.82#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.08:43:58.82#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.08:43:58.82$vck44/valo=6,814.99 2006.173.08:43:58.82#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.08:43:58.82#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.08:43:58.82#ibcon#ireg 17 cls_cnt 0 2006.173.08:43:58.82#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.08:43:58.82#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.08:43:58.82#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.08:43:58.82#ibcon#enter wrdev, iclass 19, count 0 2006.173.08:43:58.82#ibcon#first serial, iclass 19, count 0 2006.173.08:43:58.82#ibcon#enter sib2, iclass 19, count 0 2006.173.08:43:58.82#ibcon#flushed, iclass 19, count 0 2006.173.08:43:58.82#ibcon#about to write, iclass 19, count 0 2006.173.08:43:58.82#ibcon#wrote, iclass 19, count 0 2006.173.08:43:58.82#ibcon#about to read 3, iclass 19, count 0 2006.173.08:43:58.84#ibcon#read 3, iclass 19, count 0 2006.173.08:43:58.84#ibcon#about to read 4, iclass 19, count 0 2006.173.08:43:58.84#ibcon#read 4, iclass 19, count 0 2006.173.08:43:58.84#ibcon#about to read 5, iclass 19, count 0 2006.173.08:43:58.84#ibcon#read 5, iclass 19, count 0 2006.173.08:43:58.84#ibcon#about to read 6, iclass 19, count 0 2006.173.08:43:58.84#ibcon#read 6, iclass 19, count 0 2006.173.08:43:58.84#ibcon#end of sib2, iclass 19, count 0 2006.173.08:43:58.84#ibcon#*mode == 0, iclass 19, count 0 2006.173.08:43:58.84#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.08:43:58.84#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.08:43:58.84#ibcon#*before write, iclass 19, count 0 2006.173.08:43:58.84#ibcon#enter sib2, iclass 19, count 0 2006.173.08:43:58.84#ibcon#flushed, iclass 19, count 0 2006.173.08:43:58.84#ibcon#about to write, iclass 19, count 0 2006.173.08:43:58.84#ibcon#wrote, iclass 19, count 0 2006.173.08:43:58.84#ibcon#about to read 3, iclass 19, count 0 2006.173.08:43:58.88#ibcon#read 3, iclass 19, count 0 2006.173.08:43:58.88#ibcon#about to read 4, iclass 19, count 0 2006.173.08:43:58.88#ibcon#read 4, iclass 19, count 0 2006.173.08:43:58.88#ibcon#about to read 5, iclass 19, count 0 2006.173.08:43:58.88#ibcon#read 5, iclass 19, count 0 2006.173.08:43:58.88#ibcon#about to read 6, iclass 19, count 0 2006.173.08:43:58.88#ibcon#read 6, iclass 19, count 0 2006.173.08:43:58.88#ibcon#end of sib2, iclass 19, count 0 2006.173.08:43:58.88#ibcon#*after write, iclass 19, count 0 2006.173.08:43:58.88#ibcon#*before return 0, iclass 19, count 0 2006.173.08:43:58.88#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.08:43:58.88#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.08:43:58.88#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.08:43:58.88#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.08:43:58.88$vck44/va=6,3 2006.173.08:43:58.88#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.08:43:58.88#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.08:43:58.88#ibcon#ireg 11 cls_cnt 2 2006.173.08:43:58.88#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.08:43:58.94#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.08:43:58.94#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.08:43:58.94#ibcon#enter wrdev, iclass 21, count 2 2006.173.08:43:58.94#ibcon#first serial, iclass 21, count 2 2006.173.08:43:58.94#ibcon#enter sib2, iclass 21, count 2 2006.173.08:43:58.94#ibcon#flushed, iclass 21, count 2 2006.173.08:43:58.94#ibcon#about to write, iclass 21, count 2 2006.173.08:43:58.94#ibcon#wrote, iclass 21, count 2 2006.173.08:43:58.94#ibcon#about to read 3, iclass 21, count 2 2006.173.08:43:58.96#ibcon#read 3, iclass 21, count 2 2006.173.08:43:58.96#ibcon#about to read 4, iclass 21, count 2 2006.173.08:43:58.96#ibcon#read 4, iclass 21, count 2 2006.173.08:43:58.96#ibcon#about to read 5, iclass 21, count 2 2006.173.08:43:58.96#ibcon#read 5, iclass 21, count 2 2006.173.08:43:58.96#ibcon#about to read 6, iclass 21, count 2 2006.173.08:43:58.96#ibcon#read 6, iclass 21, count 2 2006.173.08:43:58.96#ibcon#end of sib2, iclass 21, count 2 2006.173.08:43:58.96#ibcon#*mode == 0, iclass 21, count 2 2006.173.08:43:58.96#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.08:43:58.96#ibcon#[25=AT06-03\r\n] 2006.173.08:43:58.96#ibcon#*before write, iclass 21, count 2 2006.173.08:43:58.96#ibcon#enter sib2, iclass 21, count 2 2006.173.08:43:58.96#ibcon#flushed, iclass 21, count 2 2006.173.08:43:58.96#ibcon#about to write, iclass 21, count 2 2006.173.08:43:58.96#ibcon#wrote, iclass 21, count 2 2006.173.08:43:58.96#ibcon#about to read 3, iclass 21, count 2 2006.173.08:43:58.99#ibcon#read 3, iclass 21, count 2 2006.173.08:43:58.99#ibcon#about to read 4, iclass 21, count 2 2006.173.08:43:58.99#ibcon#read 4, iclass 21, count 2 2006.173.08:43:58.99#ibcon#about to read 5, iclass 21, count 2 2006.173.08:43:58.99#ibcon#read 5, iclass 21, count 2 2006.173.08:43:58.99#ibcon#about to read 6, iclass 21, count 2 2006.173.08:43:58.99#ibcon#read 6, iclass 21, count 2 2006.173.08:43:58.99#ibcon#end of sib2, iclass 21, count 2 2006.173.08:43:58.99#ibcon#*after write, iclass 21, count 2 2006.173.08:43:58.99#ibcon#*before return 0, iclass 21, count 2 2006.173.08:43:58.99#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.08:43:58.99#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.08:43:58.99#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.08:43:58.99#ibcon#ireg 7 cls_cnt 0 2006.173.08:43:58.99#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.08:43:59.11#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.08:43:59.11#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.08:43:59.11#ibcon#enter wrdev, iclass 21, count 0 2006.173.08:43:59.11#ibcon#first serial, iclass 21, count 0 2006.173.08:43:59.11#ibcon#enter sib2, iclass 21, count 0 2006.173.08:43:59.11#ibcon#flushed, iclass 21, count 0 2006.173.08:43:59.11#ibcon#about to write, iclass 21, count 0 2006.173.08:43:59.11#ibcon#wrote, iclass 21, count 0 2006.173.08:43:59.11#ibcon#about to read 3, iclass 21, count 0 2006.173.08:43:59.13#ibcon#read 3, iclass 21, count 0 2006.173.08:43:59.13#ibcon#about to read 4, iclass 21, count 0 2006.173.08:43:59.13#ibcon#read 4, iclass 21, count 0 2006.173.08:43:59.13#ibcon#about to read 5, iclass 21, count 0 2006.173.08:43:59.13#ibcon#read 5, iclass 21, count 0 2006.173.08:43:59.13#ibcon#about to read 6, iclass 21, count 0 2006.173.08:43:59.13#ibcon#read 6, iclass 21, count 0 2006.173.08:43:59.13#ibcon#end of sib2, iclass 21, count 0 2006.173.08:43:59.13#ibcon#*mode == 0, iclass 21, count 0 2006.173.08:43:59.13#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.08:43:59.13#ibcon#[25=USB\r\n] 2006.173.08:43:59.13#ibcon#*before write, iclass 21, count 0 2006.173.08:43:59.13#ibcon#enter sib2, iclass 21, count 0 2006.173.08:43:59.13#ibcon#flushed, iclass 21, count 0 2006.173.08:43:59.13#ibcon#about to write, iclass 21, count 0 2006.173.08:43:59.13#ibcon#wrote, iclass 21, count 0 2006.173.08:43:59.13#ibcon#about to read 3, iclass 21, count 0 2006.173.08:43:59.16#ibcon#read 3, iclass 21, count 0 2006.173.08:43:59.16#ibcon#about to read 4, iclass 21, count 0 2006.173.08:43:59.16#ibcon#read 4, iclass 21, count 0 2006.173.08:43:59.16#ibcon#about to read 5, iclass 21, count 0 2006.173.08:43:59.16#ibcon#read 5, iclass 21, count 0 2006.173.08:43:59.16#ibcon#about to read 6, iclass 21, count 0 2006.173.08:43:59.16#ibcon#read 6, iclass 21, count 0 2006.173.08:43:59.16#ibcon#end of sib2, iclass 21, count 0 2006.173.08:43:59.16#ibcon#*after write, iclass 21, count 0 2006.173.08:43:59.16#ibcon#*before return 0, iclass 21, count 0 2006.173.08:43:59.16#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.08:43:59.16#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.08:43:59.16#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.08:43:59.16#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.08:43:59.16$vck44/valo=7,864.99 2006.173.08:43:59.16#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.08:43:59.16#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.08:43:59.16#ibcon#ireg 17 cls_cnt 0 2006.173.08:43:59.16#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.08:43:59.16#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.08:43:59.16#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.08:43:59.16#ibcon#enter wrdev, iclass 23, count 0 2006.173.08:43:59.16#ibcon#first serial, iclass 23, count 0 2006.173.08:43:59.16#ibcon#enter sib2, iclass 23, count 0 2006.173.08:43:59.16#ibcon#flushed, iclass 23, count 0 2006.173.08:43:59.16#ibcon#about to write, iclass 23, count 0 2006.173.08:43:59.16#ibcon#wrote, iclass 23, count 0 2006.173.08:43:59.16#ibcon#about to read 3, iclass 23, count 0 2006.173.08:43:59.18#ibcon#read 3, iclass 23, count 0 2006.173.08:43:59.18#ibcon#about to read 4, iclass 23, count 0 2006.173.08:43:59.18#ibcon#read 4, iclass 23, count 0 2006.173.08:43:59.18#ibcon#about to read 5, iclass 23, count 0 2006.173.08:43:59.18#ibcon#read 5, iclass 23, count 0 2006.173.08:43:59.18#ibcon#about to read 6, iclass 23, count 0 2006.173.08:43:59.18#ibcon#read 6, iclass 23, count 0 2006.173.08:43:59.18#ibcon#end of sib2, iclass 23, count 0 2006.173.08:43:59.18#ibcon#*mode == 0, iclass 23, count 0 2006.173.08:43:59.18#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.08:43:59.18#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.08:43:59.18#ibcon#*before write, iclass 23, count 0 2006.173.08:43:59.18#ibcon#enter sib2, iclass 23, count 0 2006.173.08:43:59.18#ibcon#flushed, iclass 23, count 0 2006.173.08:43:59.18#ibcon#about to write, iclass 23, count 0 2006.173.08:43:59.18#ibcon#wrote, iclass 23, count 0 2006.173.08:43:59.18#ibcon#about to read 3, iclass 23, count 0 2006.173.08:43:59.22#ibcon#read 3, iclass 23, count 0 2006.173.08:43:59.22#ibcon#about to read 4, iclass 23, count 0 2006.173.08:43:59.22#ibcon#read 4, iclass 23, count 0 2006.173.08:43:59.22#ibcon#about to read 5, iclass 23, count 0 2006.173.08:43:59.22#ibcon#read 5, iclass 23, count 0 2006.173.08:43:59.22#ibcon#about to read 6, iclass 23, count 0 2006.173.08:43:59.22#ibcon#read 6, iclass 23, count 0 2006.173.08:43:59.22#ibcon#end of sib2, iclass 23, count 0 2006.173.08:43:59.22#ibcon#*after write, iclass 23, count 0 2006.173.08:43:59.22#ibcon#*before return 0, iclass 23, count 0 2006.173.08:43:59.22#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.08:43:59.22#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.08:43:59.22#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.08:43:59.22#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.08:43:59.22$vck44/va=7,4 2006.173.08:43:59.22#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.08:43:59.22#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.08:43:59.22#ibcon#ireg 11 cls_cnt 2 2006.173.08:43:59.22#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.08:43:59.28#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.08:43:59.28#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.08:43:59.28#ibcon#enter wrdev, iclass 25, count 2 2006.173.08:43:59.28#ibcon#first serial, iclass 25, count 2 2006.173.08:43:59.28#ibcon#enter sib2, iclass 25, count 2 2006.173.08:43:59.28#ibcon#flushed, iclass 25, count 2 2006.173.08:43:59.28#ibcon#about to write, iclass 25, count 2 2006.173.08:43:59.28#ibcon#wrote, iclass 25, count 2 2006.173.08:43:59.28#ibcon#about to read 3, iclass 25, count 2 2006.173.08:43:59.30#ibcon#read 3, iclass 25, count 2 2006.173.08:43:59.30#ibcon#about to read 4, iclass 25, count 2 2006.173.08:43:59.30#ibcon#read 4, iclass 25, count 2 2006.173.08:43:59.30#ibcon#about to read 5, iclass 25, count 2 2006.173.08:43:59.30#ibcon#read 5, iclass 25, count 2 2006.173.08:43:59.30#ibcon#about to read 6, iclass 25, count 2 2006.173.08:43:59.30#ibcon#read 6, iclass 25, count 2 2006.173.08:43:59.30#ibcon#end of sib2, iclass 25, count 2 2006.173.08:43:59.30#ibcon#*mode == 0, iclass 25, count 2 2006.173.08:43:59.30#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.08:43:59.30#ibcon#[25=AT07-04\r\n] 2006.173.08:43:59.30#ibcon#*before write, iclass 25, count 2 2006.173.08:43:59.30#ibcon#enter sib2, iclass 25, count 2 2006.173.08:43:59.30#ibcon#flushed, iclass 25, count 2 2006.173.08:43:59.30#ibcon#about to write, iclass 25, count 2 2006.173.08:43:59.30#ibcon#wrote, iclass 25, count 2 2006.173.08:43:59.30#ibcon#about to read 3, iclass 25, count 2 2006.173.08:43:59.33#ibcon#read 3, iclass 25, count 2 2006.173.08:43:59.33#ibcon#about to read 4, iclass 25, count 2 2006.173.08:43:59.33#ibcon#read 4, iclass 25, count 2 2006.173.08:43:59.33#ibcon#about to read 5, iclass 25, count 2 2006.173.08:43:59.33#ibcon#read 5, iclass 25, count 2 2006.173.08:43:59.33#ibcon#about to read 6, iclass 25, count 2 2006.173.08:43:59.33#ibcon#read 6, iclass 25, count 2 2006.173.08:43:59.33#ibcon#end of sib2, iclass 25, count 2 2006.173.08:43:59.33#ibcon#*after write, iclass 25, count 2 2006.173.08:43:59.33#ibcon#*before return 0, iclass 25, count 2 2006.173.08:43:59.33#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.08:43:59.33#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.08:43:59.33#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.08:43:59.33#ibcon#ireg 7 cls_cnt 0 2006.173.08:43:59.33#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.08:43:59.45#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.08:43:59.45#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.08:43:59.45#ibcon#enter wrdev, iclass 25, count 0 2006.173.08:43:59.45#ibcon#first serial, iclass 25, count 0 2006.173.08:43:59.45#ibcon#enter sib2, iclass 25, count 0 2006.173.08:43:59.45#ibcon#flushed, iclass 25, count 0 2006.173.08:43:59.45#ibcon#about to write, iclass 25, count 0 2006.173.08:43:59.45#ibcon#wrote, iclass 25, count 0 2006.173.08:43:59.45#ibcon#about to read 3, iclass 25, count 0 2006.173.08:43:59.47#ibcon#read 3, iclass 25, count 0 2006.173.08:43:59.47#ibcon#about to read 4, iclass 25, count 0 2006.173.08:43:59.47#ibcon#read 4, iclass 25, count 0 2006.173.08:43:59.47#ibcon#about to read 5, iclass 25, count 0 2006.173.08:43:59.47#ibcon#read 5, iclass 25, count 0 2006.173.08:43:59.47#ibcon#about to read 6, iclass 25, count 0 2006.173.08:43:59.47#ibcon#read 6, iclass 25, count 0 2006.173.08:43:59.47#ibcon#end of sib2, iclass 25, count 0 2006.173.08:43:59.47#ibcon#*mode == 0, iclass 25, count 0 2006.173.08:43:59.47#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.08:43:59.47#ibcon#[25=USB\r\n] 2006.173.08:43:59.47#ibcon#*before write, iclass 25, count 0 2006.173.08:43:59.47#ibcon#enter sib2, iclass 25, count 0 2006.173.08:43:59.47#ibcon#flushed, iclass 25, count 0 2006.173.08:43:59.47#ibcon#about to write, iclass 25, count 0 2006.173.08:43:59.47#ibcon#wrote, iclass 25, count 0 2006.173.08:43:59.47#ibcon#about to read 3, iclass 25, count 0 2006.173.08:43:59.50#ibcon#read 3, iclass 25, count 0 2006.173.08:43:59.50#ibcon#about to read 4, iclass 25, count 0 2006.173.08:43:59.50#ibcon#read 4, iclass 25, count 0 2006.173.08:43:59.50#ibcon#about to read 5, iclass 25, count 0 2006.173.08:43:59.50#ibcon#read 5, iclass 25, count 0 2006.173.08:43:59.50#ibcon#about to read 6, iclass 25, count 0 2006.173.08:43:59.50#ibcon#read 6, iclass 25, count 0 2006.173.08:43:59.50#ibcon#end of sib2, iclass 25, count 0 2006.173.08:43:59.50#ibcon#*after write, iclass 25, count 0 2006.173.08:43:59.50#ibcon#*before return 0, iclass 25, count 0 2006.173.08:43:59.50#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.08:43:59.50#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.08:43:59.50#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.08:43:59.50#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.08:43:59.50$vck44/valo=8,884.99 2006.173.08:43:59.50#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.08:43:59.50#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.08:43:59.50#ibcon#ireg 17 cls_cnt 0 2006.173.08:43:59.50#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.08:43:59.50#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.08:43:59.50#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.08:43:59.50#ibcon#enter wrdev, iclass 27, count 0 2006.173.08:43:59.50#ibcon#first serial, iclass 27, count 0 2006.173.08:43:59.50#ibcon#enter sib2, iclass 27, count 0 2006.173.08:43:59.50#ibcon#flushed, iclass 27, count 0 2006.173.08:43:59.50#ibcon#about to write, iclass 27, count 0 2006.173.08:43:59.50#ibcon#wrote, iclass 27, count 0 2006.173.08:43:59.50#ibcon#about to read 3, iclass 27, count 0 2006.173.08:43:59.52#ibcon#read 3, iclass 27, count 0 2006.173.08:43:59.52#ibcon#about to read 4, iclass 27, count 0 2006.173.08:43:59.52#ibcon#read 4, iclass 27, count 0 2006.173.08:43:59.52#ibcon#about to read 5, iclass 27, count 0 2006.173.08:43:59.52#ibcon#read 5, iclass 27, count 0 2006.173.08:43:59.52#ibcon#about to read 6, iclass 27, count 0 2006.173.08:43:59.52#ibcon#read 6, iclass 27, count 0 2006.173.08:43:59.52#ibcon#end of sib2, iclass 27, count 0 2006.173.08:43:59.52#ibcon#*mode == 0, iclass 27, count 0 2006.173.08:43:59.52#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.08:43:59.52#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.08:43:59.52#ibcon#*before write, iclass 27, count 0 2006.173.08:43:59.52#ibcon#enter sib2, iclass 27, count 0 2006.173.08:43:59.52#ibcon#flushed, iclass 27, count 0 2006.173.08:43:59.52#ibcon#about to write, iclass 27, count 0 2006.173.08:43:59.52#ibcon#wrote, iclass 27, count 0 2006.173.08:43:59.52#ibcon#about to read 3, iclass 27, count 0 2006.173.08:43:59.56#ibcon#read 3, iclass 27, count 0 2006.173.08:43:59.56#ibcon#about to read 4, iclass 27, count 0 2006.173.08:43:59.56#ibcon#read 4, iclass 27, count 0 2006.173.08:43:59.56#ibcon#about to read 5, iclass 27, count 0 2006.173.08:43:59.56#ibcon#read 5, iclass 27, count 0 2006.173.08:43:59.56#ibcon#about to read 6, iclass 27, count 0 2006.173.08:43:59.56#ibcon#read 6, iclass 27, count 0 2006.173.08:43:59.56#ibcon#end of sib2, iclass 27, count 0 2006.173.08:43:59.56#ibcon#*after write, iclass 27, count 0 2006.173.08:43:59.56#ibcon#*before return 0, iclass 27, count 0 2006.173.08:43:59.56#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.08:43:59.56#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.08:43:59.56#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.08:43:59.56#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.08:43:59.56$vck44/va=8,4 2006.173.08:43:59.56#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.08:43:59.56#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.08:43:59.56#ibcon#ireg 11 cls_cnt 2 2006.173.08:43:59.56#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.08:43:59.62#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.08:43:59.62#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.08:43:59.62#ibcon#enter wrdev, iclass 29, count 2 2006.173.08:43:59.62#ibcon#first serial, iclass 29, count 2 2006.173.08:43:59.62#ibcon#enter sib2, iclass 29, count 2 2006.173.08:43:59.62#ibcon#flushed, iclass 29, count 2 2006.173.08:43:59.62#ibcon#about to write, iclass 29, count 2 2006.173.08:43:59.62#ibcon#wrote, iclass 29, count 2 2006.173.08:43:59.62#ibcon#about to read 3, iclass 29, count 2 2006.173.08:43:59.64#ibcon#read 3, iclass 29, count 2 2006.173.08:43:59.64#ibcon#about to read 4, iclass 29, count 2 2006.173.08:43:59.64#ibcon#read 4, iclass 29, count 2 2006.173.08:43:59.64#ibcon#about to read 5, iclass 29, count 2 2006.173.08:43:59.64#ibcon#read 5, iclass 29, count 2 2006.173.08:43:59.64#ibcon#about to read 6, iclass 29, count 2 2006.173.08:43:59.64#ibcon#read 6, iclass 29, count 2 2006.173.08:43:59.64#ibcon#end of sib2, iclass 29, count 2 2006.173.08:43:59.64#ibcon#*mode == 0, iclass 29, count 2 2006.173.08:43:59.64#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.08:43:59.64#ibcon#[25=AT08-04\r\n] 2006.173.08:43:59.64#ibcon#*before write, iclass 29, count 2 2006.173.08:43:59.64#ibcon#enter sib2, iclass 29, count 2 2006.173.08:43:59.64#ibcon#flushed, iclass 29, count 2 2006.173.08:43:59.64#ibcon#about to write, iclass 29, count 2 2006.173.08:43:59.64#ibcon#wrote, iclass 29, count 2 2006.173.08:43:59.64#ibcon#about to read 3, iclass 29, count 2 2006.173.08:43:59.67#ibcon#read 3, iclass 29, count 2 2006.173.08:43:59.67#ibcon#about to read 4, iclass 29, count 2 2006.173.08:43:59.67#ibcon#read 4, iclass 29, count 2 2006.173.08:43:59.67#ibcon#about to read 5, iclass 29, count 2 2006.173.08:43:59.67#ibcon#read 5, iclass 29, count 2 2006.173.08:43:59.67#ibcon#about to read 6, iclass 29, count 2 2006.173.08:43:59.67#ibcon#read 6, iclass 29, count 2 2006.173.08:43:59.67#ibcon#end of sib2, iclass 29, count 2 2006.173.08:43:59.67#ibcon#*after write, iclass 29, count 2 2006.173.08:43:59.67#ibcon#*before return 0, iclass 29, count 2 2006.173.08:43:59.67#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.08:43:59.67#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.08:43:59.67#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.08:43:59.67#ibcon#ireg 7 cls_cnt 0 2006.173.08:43:59.67#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.08:43:59.79#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.08:43:59.79#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.08:43:59.79#ibcon#enter wrdev, iclass 29, count 0 2006.173.08:43:59.79#ibcon#first serial, iclass 29, count 0 2006.173.08:43:59.79#ibcon#enter sib2, iclass 29, count 0 2006.173.08:43:59.79#ibcon#flushed, iclass 29, count 0 2006.173.08:43:59.79#ibcon#about to write, iclass 29, count 0 2006.173.08:43:59.79#ibcon#wrote, iclass 29, count 0 2006.173.08:43:59.79#ibcon#about to read 3, iclass 29, count 0 2006.173.08:43:59.81#ibcon#read 3, iclass 29, count 0 2006.173.08:43:59.81#ibcon#about to read 4, iclass 29, count 0 2006.173.08:43:59.81#ibcon#read 4, iclass 29, count 0 2006.173.08:43:59.81#ibcon#about to read 5, iclass 29, count 0 2006.173.08:43:59.81#ibcon#read 5, iclass 29, count 0 2006.173.08:43:59.81#ibcon#about to read 6, iclass 29, count 0 2006.173.08:43:59.81#ibcon#read 6, iclass 29, count 0 2006.173.08:43:59.81#ibcon#end of sib2, iclass 29, count 0 2006.173.08:43:59.81#ibcon#*mode == 0, iclass 29, count 0 2006.173.08:43:59.81#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.08:43:59.81#ibcon#[25=USB\r\n] 2006.173.08:43:59.81#ibcon#*before write, iclass 29, count 0 2006.173.08:43:59.81#ibcon#enter sib2, iclass 29, count 0 2006.173.08:43:59.81#ibcon#flushed, iclass 29, count 0 2006.173.08:43:59.81#ibcon#about to write, iclass 29, count 0 2006.173.08:43:59.81#ibcon#wrote, iclass 29, count 0 2006.173.08:43:59.81#ibcon#about to read 3, iclass 29, count 0 2006.173.08:43:59.84#ibcon#read 3, iclass 29, count 0 2006.173.08:43:59.84#ibcon#about to read 4, iclass 29, count 0 2006.173.08:43:59.84#ibcon#read 4, iclass 29, count 0 2006.173.08:43:59.84#ibcon#about to read 5, iclass 29, count 0 2006.173.08:43:59.84#ibcon#read 5, iclass 29, count 0 2006.173.08:43:59.84#ibcon#about to read 6, iclass 29, count 0 2006.173.08:43:59.84#ibcon#read 6, iclass 29, count 0 2006.173.08:43:59.84#ibcon#end of sib2, iclass 29, count 0 2006.173.08:43:59.84#ibcon#*after write, iclass 29, count 0 2006.173.08:43:59.84#ibcon#*before return 0, iclass 29, count 0 2006.173.08:43:59.84#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.08:43:59.84#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.08:43:59.84#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.08:43:59.84#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.08:43:59.84$vck44/vblo=1,629.99 2006.173.08:43:59.84#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.08:43:59.84#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.08:43:59.84#ibcon#ireg 17 cls_cnt 0 2006.173.08:43:59.84#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.08:43:59.84#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.08:43:59.84#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.08:43:59.84#ibcon#enter wrdev, iclass 31, count 0 2006.173.08:43:59.84#ibcon#first serial, iclass 31, count 0 2006.173.08:43:59.84#ibcon#enter sib2, iclass 31, count 0 2006.173.08:43:59.84#ibcon#flushed, iclass 31, count 0 2006.173.08:43:59.84#ibcon#about to write, iclass 31, count 0 2006.173.08:43:59.84#ibcon#wrote, iclass 31, count 0 2006.173.08:43:59.84#ibcon#about to read 3, iclass 31, count 0 2006.173.08:43:59.86#ibcon#read 3, iclass 31, count 0 2006.173.08:43:59.86#ibcon#about to read 4, iclass 31, count 0 2006.173.08:43:59.86#ibcon#read 4, iclass 31, count 0 2006.173.08:43:59.86#ibcon#about to read 5, iclass 31, count 0 2006.173.08:43:59.86#ibcon#read 5, iclass 31, count 0 2006.173.08:43:59.86#ibcon#about to read 6, iclass 31, count 0 2006.173.08:43:59.86#ibcon#read 6, iclass 31, count 0 2006.173.08:43:59.86#ibcon#end of sib2, iclass 31, count 0 2006.173.08:43:59.86#ibcon#*mode == 0, iclass 31, count 0 2006.173.08:43:59.86#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.08:43:59.86#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.08:43:59.86#ibcon#*before write, iclass 31, count 0 2006.173.08:43:59.86#ibcon#enter sib2, iclass 31, count 0 2006.173.08:43:59.86#ibcon#flushed, iclass 31, count 0 2006.173.08:43:59.86#ibcon#about to write, iclass 31, count 0 2006.173.08:43:59.86#ibcon#wrote, iclass 31, count 0 2006.173.08:43:59.86#ibcon#about to read 3, iclass 31, count 0 2006.173.08:43:59.90#ibcon#read 3, iclass 31, count 0 2006.173.08:43:59.90#ibcon#about to read 4, iclass 31, count 0 2006.173.08:43:59.90#ibcon#read 4, iclass 31, count 0 2006.173.08:43:59.90#ibcon#about to read 5, iclass 31, count 0 2006.173.08:43:59.90#ibcon#read 5, iclass 31, count 0 2006.173.08:43:59.90#ibcon#about to read 6, iclass 31, count 0 2006.173.08:43:59.90#ibcon#read 6, iclass 31, count 0 2006.173.08:43:59.90#ibcon#end of sib2, iclass 31, count 0 2006.173.08:43:59.90#ibcon#*after write, iclass 31, count 0 2006.173.08:43:59.90#ibcon#*before return 0, iclass 31, count 0 2006.173.08:43:59.90#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.08:43:59.90#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.08:43:59.90#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.08:43:59.90#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.08:43:59.90$vck44/vb=1,4 2006.173.08:43:59.90#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.173.08:43:59.90#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.173.08:43:59.90#ibcon#ireg 11 cls_cnt 2 2006.173.08:43:59.90#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.08:43:59.90#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.08:43:59.90#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.08:43:59.90#ibcon#enter wrdev, iclass 33, count 2 2006.173.08:43:59.90#ibcon#first serial, iclass 33, count 2 2006.173.08:43:59.90#ibcon#enter sib2, iclass 33, count 2 2006.173.08:43:59.90#ibcon#flushed, iclass 33, count 2 2006.173.08:43:59.90#ibcon#about to write, iclass 33, count 2 2006.173.08:43:59.90#ibcon#wrote, iclass 33, count 2 2006.173.08:43:59.90#ibcon#about to read 3, iclass 33, count 2 2006.173.08:43:59.92#ibcon#read 3, iclass 33, count 2 2006.173.08:43:59.92#ibcon#about to read 4, iclass 33, count 2 2006.173.08:43:59.92#ibcon#read 4, iclass 33, count 2 2006.173.08:43:59.92#ibcon#about to read 5, iclass 33, count 2 2006.173.08:43:59.92#ibcon#read 5, iclass 33, count 2 2006.173.08:43:59.92#ibcon#about to read 6, iclass 33, count 2 2006.173.08:43:59.92#ibcon#read 6, iclass 33, count 2 2006.173.08:43:59.92#ibcon#end of sib2, iclass 33, count 2 2006.173.08:43:59.92#ibcon#*mode == 0, iclass 33, count 2 2006.173.08:43:59.92#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.173.08:43:59.92#ibcon#[27=AT01-04\r\n] 2006.173.08:43:59.92#ibcon#*before write, iclass 33, count 2 2006.173.08:43:59.92#ibcon#enter sib2, iclass 33, count 2 2006.173.08:43:59.92#ibcon#flushed, iclass 33, count 2 2006.173.08:43:59.92#ibcon#about to write, iclass 33, count 2 2006.173.08:43:59.92#ibcon#wrote, iclass 33, count 2 2006.173.08:43:59.92#ibcon#about to read 3, iclass 33, count 2 2006.173.08:43:59.95#ibcon#read 3, iclass 33, count 2 2006.173.08:43:59.95#ibcon#about to read 4, iclass 33, count 2 2006.173.08:43:59.95#ibcon#read 4, iclass 33, count 2 2006.173.08:43:59.95#ibcon#about to read 5, iclass 33, count 2 2006.173.08:43:59.95#ibcon#read 5, iclass 33, count 2 2006.173.08:43:59.95#ibcon#about to read 6, iclass 33, count 2 2006.173.08:43:59.95#ibcon#read 6, iclass 33, count 2 2006.173.08:43:59.95#ibcon#end of sib2, iclass 33, count 2 2006.173.08:43:59.95#ibcon#*after write, iclass 33, count 2 2006.173.08:43:59.95#ibcon#*before return 0, iclass 33, count 2 2006.173.08:43:59.95#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.08:43:59.95#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.173.08:43:59.95#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.173.08:43:59.95#ibcon#ireg 7 cls_cnt 0 2006.173.08:43:59.95#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.08:44:00.07#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.08:44:00.07#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.08:44:00.07#ibcon#enter wrdev, iclass 33, count 0 2006.173.08:44:00.07#ibcon#first serial, iclass 33, count 0 2006.173.08:44:00.07#ibcon#enter sib2, iclass 33, count 0 2006.173.08:44:00.07#ibcon#flushed, iclass 33, count 0 2006.173.08:44:00.07#ibcon#about to write, iclass 33, count 0 2006.173.08:44:00.07#ibcon#wrote, iclass 33, count 0 2006.173.08:44:00.07#ibcon#about to read 3, iclass 33, count 0 2006.173.08:44:00.09#ibcon#read 3, iclass 33, count 0 2006.173.08:44:00.09#ibcon#about to read 4, iclass 33, count 0 2006.173.08:44:00.09#ibcon#read 4, iclass 33, count 0 2006.173.08:44:00.09#ibcon#about to read 5, iclass 33, count 0 2006.173.08:44:00.09#ibcon#read 5, iclass 33, count 0 2006.173.08:44:00.09#ibcon#about to read 6, iclass 33, count 0 2006.173.08:44:00.09#ibcon#read 6, iclass 33, count 0 2006.173.08:44:00.09#ibcon#end of sib2, iclass 33, count 0 2006.173.08:44:00.09#ibcon#*mode == 0, iclass 33, count 0 2006.173.08:44:00.09#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.08:44:00.09#ibcon#[27=USB\r\n] 2006.173.08:44:00.09#ibcon#*before write, iclass 33, count 0 2006.173.08:44:00.09#ibcon#enter sib2, iclass 33, count 0 2006.173.08:44:00.09#ibcon#flushed, iclass 33, count 0 2006.173.08:44:00.09#ibcon#about to write, iclass 33, count 0 2006.173.08:44:00.09#ibcon#wrote, iclass 33, count 0 2006.173.08:44:00.09#ibcon#about to read 3, iclass 33, count 0 2006.173.08:44:00.12#ibcon#read 3, iclass 33, count 0 2006.173.08:44:00.12#ibcon#about to read 4, iclass 33, count 0 2006.173.08:44:00.12#ibcon#read 4, iclass 33, count 0 2006.173.08:44:00.12#ibcon#about to read 5, iclass 33, count 0 2006.173.08:44:00.12#ibcon#read 5, iclass 33, count 0 2006.173.08:44:00.12#ibcon#about to read 6, iclass 33, count 0 2006.173.08:44:00.12#ibcon#read 6, iclass 33, count 0 2006.173.08:44:00.12#ibcon#end of sib2, iclass 33, count 0 2006.173.08:44:00.12#ibcon#*after write, iclass 33, count 0 2006.173.08:44:00.12#ibcon#*before return 0, iclass 33, count 0 2006.173.08:44:00.12#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.08:44:00.12#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.173.08:44:00.12#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.08:44:00.12#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.08:44:00.12$vck44/vblo=2,634.99 2006.173.08:44:00.12#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.08:44:00.12#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.08:44:00.12#ibcon#ireg 17 cls_cnt 0 2006.173.08:44:00.12#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.08:44:00.12#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.08:44:00.12#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.08:44:00.12#ibcon#enter wrdev, iclass 35, count 0 2006.173.08:44:00.12#ibcon#first serial, iclass 35, count 0 2006.173.08:44:00.12#ibcon#enter sib2, iclass 35, count 0 2006.173.08:44:00.12#ibcon#flushed, iclass 35, count 0 2006.173.08:44:00.12#ibcon#about to write, iclass 35, count 0 2006.173.08:44:00.12#ibcon#wrote, iclass 35, count 0 2006.173.08:44:00.12#ibcon#about to read 3, iclass 35, count 0 2006.173.08:44:00.14#ibcon#read 3, iclass 35, count 0 2006.173.08:44:00.14#ibcon#about to read 4, iclass 35, count 0 2006.173.08:44:00.14#ibcon#read 4, iclass 35, count 0 2006.173.08:44:00.14#ibcon#about to read 5, iclass 35, count 0 2006.173.08:44:00.14#ibcon#read 5, iclass 35, count 0 2006.173.08:44:00.14#ibcon#about to read 6, iclass 35, count 0 2006.173.08:44:00.14#ibcon#read 6, iclass 35, count 0 2006.173.08:44:00.14#ibcon#end of sib2, iclass 35, count 0 2006.173.08:44:00.14#ibcon#*mode == 0, iclass 35, count 0 2006.173.08:44:00.14#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.08:44:00.14#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.08:44:00.14#ibcon#*before write, iclass 35, count 0 2006.173.08:44:00.14#ibcon#enter sib2, iclass 35, count 0 2006.173.08:44:00.14#ibcon#flushed, iclass 35, count 0 2006.173.08:44:00.14#ibcon#about to write, iclass 35, count 0 2006.173.08:44:00.14#ibcon#wrote, iclass 35, count 0 2006.173.08:44:00.14#ibcon#about to read 3, iclass 35, count 0 2006.173.08:44:00.18#ibcon#read 3, iclass 35, count 0 2006.173.08:44:00.18#ibcon#about to read 4, iclass 35, count 0 2006.173.08:44:00.18#ibcon#read 4, iclass 35, count 0 2006.173.08:44:00.18#ibcon#about to read 5, iclass 35, count 0 2006.173.08:44:00.18#ibcon#read 5, iclass 35, count 0 2006.173.08:44:00.18#ibcon#about to read 6, iclass 35, count 0 2006.173.08:44:00.18#ibcon#read 6, iclass 35, count 0 2006.173.08:44:00.18#ibcon#end of sib2, iclass 35, count 0 2006.173.08:44:00.18#ibcon#*after write, iclass 35, count 0 2006.173.08:44:00.18#ibcon#*before return 0, iclass 35, count 0 2006.173.08:44:00.18#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.08:44:00.18#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.08:44:00.18#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.08:44:00.18#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.08:44:00.18$vck44/vb=2,4 2006.173.08:44:00.18#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.173.08:44:00.18#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.173.08:44:00.18#ibcon#ireg 11 cls_cnt 2 2006.173.08:44:00.18#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.08:44:00.24#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.08:44:00.24#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.08:44:00.24#ibcon#enter wrdev, iclass 37, count 2 2006.173.08:44:00.24#ibcon#first serial, iclass 37, count 2 2006.173.08:44:00.24#ibcon#enter sib2, iclass 37, count 2 2006.173.08:44:00.24#ibcon#flushed, iclass 37, count 2 2006.173.08:44:00.24#ibcon#about to write, iclass 37, count 2 2006.173.08:44:00.24#ibcon#wrote, iclass 37, count 2 2006.173.08:44:00.24#ibcon#about to read 3, iclass 37, count 2 2006.173.08:44:00.26#ibcon#read 3, iclass 37, count 2 2006.173.08:44:00.26#ibcon#about to read 4, iclass 37, count 2 2006.173.08:44:00.26#ibcon#read 4, iclass 37, count 2 2006.173.08:44:00.26#ibcon#about to read 5, iclass 37, count 2 2006.173.08:44:00.26#ibcon#read 5, iclass 37, count 2 2006.173.08:44:00.26#ibcon#about to read 6, iclass 37, count 2 2006.173.08:44:00.26#ibcon#read 6, iclass 37, count 2 2006.173.08:44:00.26#ibcon#end of sib2, iclass 37, count 2 2006.173.08:44:00.26#ibcon#*mode == 0, iclass 37, count 2 2006.173.08:44:00.26#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.173.08:44:00.26#ibcon#[27=AT02-04\r\n] 2006.173.08:44:00.26#ibcon#*before write, iclass 37, count 2 2006.173.08:44:00.26#ibcon#enter sib2, iclass 37, count 2 2006.173.08:44:00.26#ibcon#flushed, iclass 37, count 2 2006.173.08:44:00.26#ibcon#about to write, iclass 37, count 2 2006.173.08:44:00.26#ibcon#wrote, iclass 37, count 2 2006.173.08:44:00.26#ibcon#about to read 3, iclass 37, count 2 2006.173.08:44:00.29#ibcon#read 3, iclass 37, count 2 2006.173.08:44:00.29#ibcon#about to read 4, iclass 37, count 2 2006.173.08:44:00.29#ibcon#read 4, iclass 37, count 2 2006.173.08:44:00.29#ibcon#about to read 5, iclass 37, count 2 2006.173.08:44:00.29#ibcon#read 5, iclass 37, count 2 2006.173.08:44:00.29#ibcon#about to read 6, iclass 37, count 2 2006.173.08:44:00.29#ibcon#read 6, iclass 37, count 2 2006.173.08:44:00.29#ibcon#end of sib2, iclass 37, count 2 2006.173.08:44:00.29#ibcon#*after write, iclass 37, count 2 2006.173.08:44:00.29#ibcon#*before return 0, iclass 37, count 2 2006.173.08:44:00.29#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.08:44:00.29#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.173.08:44:00.29#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.173.08:44:00.29#ibcon#ireg 7 cls_cnt 0 2006.173.08:44:00.29#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.08:44:00.36#abcon#<5=/00 0.2 0.8 23.17 871004.0\r\n> 2006.173.08:44:00.38#abcon#{5=INTERFACE CLEAR} 2006.173.08:44:00.41#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.08:44:00.41#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.08:44:00.41#ibcon#enter wrdev, iclass 37, count 0 2006.173.08:44:00.41#ibcon#first serial, iclass 37, count 0 2006.173.08:44:00.41#ibcon#enter sib2, iclass 37, count 0 2006.173.08:44:00.41#ibcon#flushed, iclass 37, count 0 2006.173.08:44:00.41#ibcon#about to write, iclass 37, count 0 2006.173.08:44:00.41#ibcon#wrote, iclass 37, count 0 2006.173.08:44:00.41#ibcon#about to read 3, iclass 37, count 0 2006.173.08:44:00.43#ibcon#read 3, iclass 37, count 0 2006.173.08:44:00.43#ibcon#about to read 4, iclass 37, count 0 2006.173.08:44:00.43#ibcon#read 4, iclass 37, count 0 2006.173.08:44:00.43#ibcon#about to read 5, iclass 37, count 0 2006.173.08:44:00.43#ibcon#read 5, iclass 37, count 0 2006.173.08:44:00.43#ibcon#about to read 6, iclass 37, count 0 2006.173.08:44:00.43#ibcon#read 6, iclass 37, count 0 2006.173.08:44:00.43#ibcon#end of sib2, iclass 37, count 0 2006.173.08:44:00.43#ibcon#*mode == 0, iclass 37, count 0 2006.173.08:44:00.43#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.08:44:00.43#ibcon#[27=USB\r\n] 2006.173.08:44:00.43#ibcon#*before write, iclass 37, count 0 2006.173.08:44:00.43#ibcon#enter sib2, iclass 37, count 0 2006.173.08:44:00.43#ibcon#flushed, iclass 37, count 0 2006.173.08:44:00.43#ibcon#about to write, iclass 37, count 0 2006.173.08:44:00.43#ibcon#wrote, iclass 37, count 0 2006.173.08:44:00.43#ibcon#about to read 3, iclass 37, count 0 2006.173.08:44:00.44#abcon#[5=S1D000X0/0*\r\n] 2006.173.08:44:00.46#ibcon#read 3, iclass 37, count 0 2006.173.08:44:00.46#ibcon#about to read 4, iclass 37, count 0 2006.173.08:44:00.46#ibcon#read 4, iclass 37, count 0 2006.173.08:44:00.46#ibcon#about to read 5, iclass 37, count 0 2006.173.08:44:00.46#ibcon#read 5, iclass 37, count 0 2006.173.08:44:00.46#ibcon#about to read 6, iclass 37, count 0 2006.173.08:44:00.46#ibcon#read 6, iclass 37, count 0 2006.173.08:44:00.46#ibcon#end of sib2, iclass 37, count 0 2006.173.08:44:00.46#ibcon#*after write, iclass 37, count 0 2006.173.08:44:00.46#ibcon#*before return 0, iclass 37, count 0 2006.173.08:44:00.46#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.08:44:00.46#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.173.08:44:00.46#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.08:44:00.46#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.08:44:00.46$vck44/vblo=3,649.99 2006.173.08:44:00.46#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.08:44:00.46#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.08:44:00.46#ibcon#ireg 17 cls_cnt 0 2006.173.08:44:00.46#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.08:44:00.46#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.08:44:00.46#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.08:44:00.46#ibcon#enter wrdev, iclass 5, count 0 2006.173.08:44:00.46#ibcon#first serial, iclass 5, count 0 2006.173.08:44:00.46#ibcon#enter sib2, iclass 5, count 0 2006.173.08:44:00.46#ibcon#flushed, iclass 5, count 0 2006.173.08:44:00.46#ibcon#about to write, iclass 5, count 0 2006.173.08:44:00.46#ibcon#wrote, iclass 5, count 0 2006.173.08:44:00.46#ibcon#about to read 3, iclass 5, count 0 2006.173.08:44:00.48#ibcon#read 3, iclass 5, count 0 2006.173.08:44:00.48#ibcon#about to read 4, iclass 5, count 0 2006.173.08:44:00.48#ibcon#read 4, iclass 5, count 0 2006.173.08:44:00.48#ibcon#about to read 5, iclass 5, count 0 2006.173.08:44:00.48#ibcon#read 5, iclass 5, count 0 2006.173.08:44:00.48#ibcon#about to read 6, iclass 5, count 0 2006.173.08:44:00.48#ibcon#read 6, iclass 5, count 0 2006.173.08:44:00.48#ibcon#end of sib2, iclass 5, count 0 2006.173.08:44:00.48#ibcon#*mode == 0, iclass 5, count 0 2006.173.08:44:00.48#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.08:44:00.48#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.08:44:00.48#ibcon#*before write, iclass 5, count 0 2006.173.08:44:00.48#ibcon#enter sib2, iclass 5, count 0 2006.173.08:44:00.48#ibcon#flushed, iclass 5, count 0 2006.173.08:44:00.48#ibcon#about to write, iclass 5, count 0 2006.173.08:44:00.48#ibcon#wrote, iclass 5, count 0 2006.173.08:44:00.48#ibcon#about to read 3, iclass 5, count 0 2006.173.08:44:00.52#ibcon#read 3, iclass 5, count 0 2006.173.08:44:00.52#ibcon#about to read 4, iclass 5, count 0 2006.173.08:44:00.52#ibcon#read 4, iclass 5, count 0 2006.173.08:44:00.52#ibcon#about to read 5, iclass 5, count 0 2006.173.08:44:00.52#ibcon#read 5, iclass 5, count 0 2006.173.08:44:00.52#ibcon#about to read 6, iclass 5, count 0 2006.173.08:44:00.52#ibcon#read 6, iclass 5, count 0 2006.173.08:44:00.52#ibcon#end of sib2, iclass 5, count 0 2006.173.08:44:00.52#ibcon#*after write, iclass 5, count 0 2006.173.08:44:00.52#ibcon#*before return 0, iclass 5, count 0 2006.173.08:44:00.52#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.08:44:00.52#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.08:44:00.52#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.08:44:00.52#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.08:44:00.52$vck44/vb=3,4 2006.173.08:44:00.52#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.173.08:44:00.52#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.173.08:44:00.52#ibcon#ireg 11 cls_cnt 2 2006.173.08:44:00.52#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.08:44:00.58#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.08:44:00.58#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.08:44:00.58#ibcon#enter wrdev, iclass 7, count 2 2006.173.08:44:00.58#ibcon#first serial, iclass 7, count 2 2006.173.08:44:00.58#ibcon#enter sib2, iclass 7, count 2 2006.173.08:44:00.58#ibcon#flushed, iclass 7, count 2 2006.173.08:44:00.58#ibcon#about to write, iclass 7, count 2 2006.173.08:44:00.58#ibcon#wrote, iclass 7, count 2 2006.173.08:44:00.58#ibcon#about to read 3, iclass 7, count 2 2006.173.08:44:00.60#ibcon#read 3, iclass 7, count 2 2006.173.08:44:00.60#ibcon#about to read 4, iclass 7, count 2 2006.173.08:44:00.60#ibcon#read 4, iclass 7, count 2 2006.173.08:44:00.60#ibcon#about to read 5, iclass 7, count 2 2006.173.08:44:00.60#ibcon#read 5, iclass 7, count 2 2006.173.08:44:00.60#ibcon#about to read 6, iclass 7, count 2 2006.173.08:44:00.60#ibcon#read 6, iclass 7, count 2 2006.173.08:44:00.60#ibcon#end of sib2, iclass 7, count 2 2006.173.08:44:00.60#ibcon#*mode == 0, iclass 7, count 2 2006.173.08:44:00.60#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.173.08:44:00.60#ibcon#[27=AT03-04\r\n] 2006.173.08:44:00.60#ibcon#*before write, iclass 7, count 2 2006.173.08:44:00.60#ibcon#enter sib2, iclass 7, count 2 2006.173.08:44:00.60#ibcon#flushed, iclass 7, count 2 2006.173.08:44:00.60#ibcon#about to write, iclass 7, count 2 2006.173.08:44:00.60#ibcon#wrote, iclass 7, count 2 2006.173.08:44:00.60#ibcon#about to read 3, iclass 7, count 2 2006.173.08:44:00.63#ibcon#read 3, iclass 7, count 2 2006.173.08:44:00.63#ibcon#about to read 4, iclass 7, count 2 2006.173.08:44:00.63#ibcon#read 4, iclass 7, count 2 2006.173.08:44:00.63#ibcon#about to read 5, iclass 7, count 2 2006.173.08:44:00.63#ibcon#read 5, iclass 7, count 2 2006.173.08:44:00.63#ibcon#about to read 6, iclass 7, count 2 2006.173.08:44:00.63#ibcon#read 6, iclass 7, count 2 2006.173.08:44:00.63#ibcon#end of sib2, iclass 7, count 2 2006.173.08:44:00.63#ibcon#*after write, iclass 7, count 2 2006.173.08:44:00.63#ibcon#*before return 0, iclass 7, count 2 2006.173.08:44:00.63#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.08:44:00.63#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.173.08:44:00.63#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.173.08:44:00.63#ibcon#ireg 7 cls_cnt 0 2006.173.08:44:00.63#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.08:44:00.75#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.08:44:00.75#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.08:44:00.75#ibcon#enter wrdev, iclass 7, count 0 2006.173.08:44:00.75#ibcon#first serial, iclass 7, count 0 2006.173.08:44:00.75#ibcon#enter sib2, iclass 7, count 0 2006.173.08:44:00.75#ibcon#flushed, iclass 7, count 0 2006.173.08:44:00.75#ibcon#about to write, iclass 7, count 0 2006.173.08:44:00.75#ibcon#wrote, iclass 7, count 0 2006.173.08:44:00.75#ibcon#about to read 3, iclass 7, count 0 2006.173.08:44:00.77#ibcon#read 3, iclass 7, count 0 2006.173.08:44:00.77#ibcon#about to read 4, iclass 7, count 0 2006.173.08:44:00.77#ibcon#read 4, iclass 7, count 0 2006.173.08:44:00.77#ibcon#about to read 5, iclass 7, count 0 2006.173.08:44:00.77#ibcon#read 5, iclass 7, count 0 2006.173.08:44:00.77#ibcon#about to read 6, iclass 7, count 0 2006.173.08:44:00.77#ibcon#read 6, iclass 7, count 0 2006.173.08:44:00.77#ibcon#end of sib2, iclass 7, count 0 2006.173.08:44:00.77#ibcon#*mode == 0, iclass 7, count 0 2006.173.08:44:00.77#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.08:44:00.77#ibcon#[27=USB\r\n] 2006.173.08:44:00.77#ibcon#*before write, iclass 7, count 0 2006.173.08:44:00.77#ibcon#enter sib2, iclass 7, count 0 2006.173.08:44:00.77#ibcon#flushed, iclass 7, count 0 2006.173.08:44:00.77#ibcon#about to write, iclass 7, count 0 2006.173.08:44:00.77#ibcon#wrote, iclass 7, count 0 2006.173.08:44:00.77#ibcon#about to read 3, iclass 7, count 0 2006.173.08:44:00.80#ibcon#read 3, iclass 7, count 0 2006.173.08:44:00.80#ibcon#about to read 4, iclass 7, count 0 2006.173.08:44:00.80#ibcon#read 4, iclass 7, count 0 2006.173.08:44:00.80#ibcon#about to read 5, iclass 7, count 0 2006.173.08:44:00.80#ibcon#read 5, iclass 7, count 0 2006.173.08:44:00.80#ibcon#about to read 6, iclass 7, count 0 2006.173.08:44:00.80#ibcon#read 6, iclass 7, count 0 2006.173.08:44:00.80#ibcon#end of sib2, iclass 7, count 0 2006.173.08:44:00.80#ibcon#*after write, iclass 7, count 0 2006.173.08:44:00.80#ibcon#*before return 0, iclass 7, count 0 2006.173.08:44:00.80#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.08:44:00.80#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.173.08:44:00.80#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.08:44:00.80#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.08:44:00.80$vck44/vblo=4,679.99 2006.173.08:44:00.80#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.08:44:00.80#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.08:44:00.80#ibcon#ireg 17 cls_cnt 0 2006.173.08:44:00.80#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.08:44:00.80#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.08:44:00.80#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.08:44:00.80#ibcon#enter wrdev, iclass 11, count 0 2006.173.08:44:00.80#ibcon#first serial, iclass 11, count 0 2006.173.08:44:00.80#ibcon#enter sib2, iclass 11, count 0 2006.173.08:44:00.80#ibcon#flushed, iclass 11, count 0 2006.173.08:44:00.80#ibcon#about to write, iclass 11, count 0 2006.173.08:44:00.80#ibcon#wrote, iclass 11, count 0 2006.173.08:44:00.80#ibcon#about to read 3, iclass 11, count 0 2006.173.08:44:00.82#ibcon#read 3, iclass 11, count 0 2006.173.08:44:00.82#ibcon#about to read 4, iclass 11, count 0 2006.173.08:44:00.82#ibcon#read 4, iclass 11, count 0 2006.173.08:44:00.82#ibcon#about to read 5, iclass 11, count 0 2006.173.08:44:00.82#ibcon#read 5, iclass 11, count 0 2006.173.08:44:00.82#ibcon#about to read 6, iclass 11, count 0 2006.173.08:44:00.82#ibcon#read 6, iclass 11, count 0 2006.173.08:44:00.82#ibcon#end of sib2, iclass 11, count 0 2006.173.08:44:00.82#ibcon#*mode == 0, iclass 11, count 0 2006.173.08:44:00.82#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.08:44:00.82#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.08:44:00.82#ibcon#*before write, iclass 11, count 0 2006.173.08:44:00.82#ibcon#enter sib2, iclass 11, count 0 2006.173.08:44:00.82#ibcon#flushed, iclass 11, count 0 2006.173.08:44:00.82#ibcon#about to write, iclass 11, count 0 2006.173.08:44:00.82#ibcon#wrote, iclass 11, count 0 2006.173.08:44:00.82#ibcon#about to read 3, iclass 11, count 0 2006.173.08:44:00.86#ibcon#read 3, iclass 11, count 0 2006.173.08:44:00.86#ibcon#about to read 4, iclass 11, count 0 2006.173.08:44:00.86#ibcon#read 4, iclass 11, count 0 2006.173.08:44:00.86#ibcon#about to read 5, iclass 11, count 0 2006.173.08:44:00.86#ibcon#read 5, iclass 11, count 0 2006.173.08:44:00.86#ibcon#about to read 6, iclass 11, count 0 2006.173.08:44:00.86#ibcon#read 6, iclass 11, count 0 2006.173.08:44:00.86#ibcon#end of sib2, iclass 11, count 0 2006.173.08:44:00.86#ibcon#*after write, iclass 11, count 0 2006.173.08:44:00.86#ibcon#*before return 0, iclass 11, count 0 2006.173.08:44:00.86#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.08:44:00.86#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.08:44:00.86#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.08:44:00.86#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.08:44:00.86$vck44/vb=4,4 2006.173.08:44:00.86#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.173.08:44:00.86#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.173.08:44:00.86#ibcon#ireg 11 cls_cnt 2 2006.173.08:44:00.86#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.08:44:00.92#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.08:44:00.92#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.08:44:00.92#ibcon#enter wrdev, iclass 13, count 2 2006.173.08:44:00.92#ibcon#first serial, iclass 13, count 2 2006.173.08:44:00.92#ibcon#enter sib2, iclass 13, count 2 2006.173.08:44:00.92#ibcon#flushed, iclass 13, count 2 2006.173.08:44:00.92#ibcon#about to write, iclass 13, count 2 2006.173.08:44:00.92#ibcon#wrote, iclass 13, count 2 2006.173.08:44:00.92#ibcon#about to read 3, iclass 13, count 2 2006.173.08:44:00.94#ibcon#read 3, iclass 13, count 2 2006.173.08:44:00.94#ibcon#about to read 4, iclass 13, count 2 2006.173.08:44:00.94#ibcon#read 4, iclass 13, count 2 2006.173.08:44:00.94#ibcon#about to read 5, iclass 13, count 2 2006.173.08:44:00.94#ibcon#read 5, iclass 13, count 2 2006.173.08:44:00.94#ibcon#about to read 6, iclass 13, count 2 2006.173.08:44:00.94#ibcon#read 6, iclass 13, count 2 2006.173.08:44:00.94#ibcon#end of sib2, iclass 13, count 2 2006.173.08:44:00.94#ibcon#*mode == 0, iclass 13, count 2 2006.173.08:44:00.94#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.173.08:44:00.94#ibcon#[27=AT04-04\r\n] 2006.173.08:44:00.94#ibcon#*before write, iclass 13, count 2 2006.173.08:44:00.94#ibcon#enter sib2, iclass 13, count 2 2006.173.08:44:00.94#ibcon#flushed, iclass 13, count 2 2006.173.08:44:00.94#ibcon#about to write, iclass 13, count 2 2006.173.08:44:00.94#ibcon#wrote, iclass 13, count 2 2006.173.08:44:00.94#ibcon#about to read 3, iclass 13, count 2 2006.173.08:44:00.97#ibcon#read 3, iclass 13, count 2 2006.173.08:44:00.97#ibcon#about to read 4, iclass 13, count 2 2006.173.08:44:00.97#ibcon#read 4, iclass 13, count 2 2006.173.08:44:00.97#ibcon#about to read 5, iclass 13, count 2 2006.173.08:44:00.97#ibcon#read 5, iclass 13, count 2 2006.173.08:44:00.97#ibcon#about to read 6, iclass 13, count 2 2006.173.08:44:00.97#ibcon#read 6, iclass 13, count 2 2006.173.08:44:00.97#ibcon#end of sib2, iclass 13, count 2 2006.173.08:44:00.97#ibcon#*after write, iclass 13, count 2 2006.173.08:44:00.97#ibcon#*before return 0, iclass 13, count 2 2006.173.08:44:00.97#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.08:44:00.97#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.173.08:44:00.97#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.173.08:44:00.97#ibcon#ireg 7 cls_cnt 0 2006.173.08:44:00.97#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.08:44:01.09#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.08:44:01.09#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.08:44:01.09#ibcon#enter wrdev, iclass 13, count 0 2006.173.08:44:01.09#ibcon#first serial, iclass 13, count 0 2006.173.08:44:01.09#ibcon#enter sib2, iclass 13, count 0 2006.173.08:44:01.09#ibcon#flushed, iclass 13, count 0 2006.173.08:44:01.09#ibcon#about to write, iclass 13, count 0 2006.173.08:44:01.09#ibcon#wrote, iclass 13, count 0 2006.173.08:44:01.09#ibcon#about to read 3, iclass 13, count 0 2006.173.08:44:01.11#ibcon#read 3, iclass 13, count 0 2006.173.08:44:01.11#ibcon#about to read 4, iclass 13, count 0 2006.173.08:44:01.11#ibcon#read 4, iclass 13, count 0 2006.173.08:44:01.11#ibcon#about to read 5, iclass 13, count 0 2006.173.08:44:01.11#ibcon#read 5, iclass 13, count 0 2006.173.08:44:01.11#ibcon#about to read 6, iclass 13, count 0 2006.173.08:44:01.11#ibcon#read 6, iclass 13, count 0 2006.173.08:44:01.11#ibcon#end of sib2, iclass 13, count 0 2006.173.08:44:01.11#ibcon#*mode == 0, iclass 13, count 0 2006.173.08:44:01.11#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.08:44:01.11#ibcon#[27=USB\r\n] 2006.173.08:44:01.11#ibcon#*before write, iclass 13, count 0 2006.173.08:44:01.11#ibcon#enter sib2, iclass 13, count 0 2006.173.08:44:01.11#ibcon#flushed, iclass 13, count 0 2006.173.08:44:01.11#ibcon#about to write, iclass 13, count 0 2006.173.08:44:01.11#ibcon#wrote, iclass 13, count 0 2006.173.08:44:01.11#ibcon#about to read 3, iclass 13, count 0 2006.173.08:44:01.14#ibcon#read 3, iclass 13, count 0 2006.173.08:44:01.14#ibcon#about to read 4, iclass 13, count 0 2006.173.08:44:01.14#ibcon#read 4, iclass 13, count 0 2006.173.08:44:01.14#ibcon#about to read 5, iclass 13, count 0 2006.173.08:44:01.14#ibcon#read 5, iclass 13, count 0 2006.173.08:44:01.14#ibcon#about to read 6, iclass 13, count 0 2006.173.08:44:01.14#ibcon#read 6, iclass 13, count 0 2006.173.08:44:01.14#ibcon#end of sib2, iclass 13, count 0 2006.173.08:44:01.14#ibcon#*after write, iclass 13, count 0 2006.173.08:44:01.14#ibcon#*before return 0, iclass 13, count 0 2006.173.08:44:01.14#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.08:44:01.14#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.173.08:44:01.14#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.08:44:01.14#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.08:44:01.14$vck44/vblo=5,709.99 2006.173.08:44:01.14#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.08:44:01.14#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.08:44:01.14#ibcon#ireg 17 cls_cnt 0 2006.173.08:44:01.14#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.08:44:01.14#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.08:44:01.14#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.08:44:01.14#ibcon#enter wrdev, iclass 15, count 0 2006.173.08:44:01.14#ibcon#first serial, iclass 15, count 0 2006.173.08:44:01.14#ibcon#enter sib2, iclass 15, count 0 2006.173.08:44:01.14#ibcon#flushed, iclass 15, count 0 2006.173.08:44:01.14#ibcon#about to write, iclass 15, count 0 2006.173.08:44:01.14#ibcon#wrote, iclass 15, count 0 2006.173.08:44:01.14#ibcon#about to read 3, iclass 15, count 0 2006.173.08:44:01.16#ibcon#read 3, iclass 15, count 0 2006.173.08:44:01.16#ibcon#about to read 4, iclass 15, count 0 2006.173.08:44:01.16#ibcon#read 4, iclass 15, count 0 2006.173.08:44:01.16#ibcon#about to read 5, iclass 15, count 0 2006.173.08:44:01.16#ibcon#read 5, iclass 15, count 0 2006.173.08:44:01.16#ibcon#about to read 6, iclass 15, count 0 2006.173.08:44:01.16#ibcon#read 6, iclass 15, count 0 2006.173.08:44:01.16#ibcon#end of sib2, iclass 15, count 0 2006.173.08:44:01.16#ibcon#*mode == 0, iclass 15, count 0 2006.173.08:44:01.16#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.08:44:01.16#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.08:44:01.16#ibcon#*before write, iclass 15, count 0 2006.173.08:44:01.16#ibcon#enter sib2, iclass 15, count 0 2006.173.08:44:01.16#ibcon#flushed, iclass 15, count 0 2006.173.08:44:01.16#ibcon#about to write, iclass 15, count 0 2006.173.08:44:01.16#ibcon#wrote, iclass 15, count 0 2006.173.08:44:01.16#ibcon#about to read 3, iclass 15, count 0 2006.173.08:44:01.20#ibcon#read 3, iclass 15, count 0 2006.173.08:44:01.20#ibcon#about to read 4, iclass 15, count 0 2006.173.08:44:01.20#ibcon#read 4, iclass 15, count 0 2006.173.08:44:01.20#ibcon#about to read 5, iclass 15, count 0 2006.173.08:44:01.20#ibcon#read 5, iclass 15, count 0 2006.173.08:44:01.20#ibcon#about to read 6, iclass 15, count 0 2006.173.08:44:01.20#ibcon#read 6, iclass 15, count 0 2006.173.08:44:01.20#ibcon#end of sib2, iclass 15, count 0 2006.173.08:44:01.20#ibcon#*after write, iclass 15, count 0 2006.173.08:44:01.20#ibcon#*before return 0, iclass 15, count 0 2006.173.08:44:01.20#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.08:44:01.20#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.08:44:01.20#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.08:44:01.20#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.08:44:01.20$vck44/vb=5,4 2006.173.08:44:01.20#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.08:44:01.20#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.08:44:01.20#ibcon#ireg 11 cls_cnt 2 2006.173.08:44:01.20#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.08:44:01.26#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.08:44:01.26#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.08:44:01.26#ibcon#enter wrdev, iclass 17, count 2 2006.173.08:44:01.26#ibcon#first serial, iclass 17, count 2 2006.173.08:44:01.26#ibcon#enter sib2, iclass 17, count 2 2006.173.08:44:01.26#ibcon#flushed, iclass 17, count 2 2006.173.08:44:01.26#ibcon#about to write, iclass 17, count 2 2006.173.08:44:01.26#ibcon#wrote, iclass 17, count 2 2006.173.08:44:01.26#ibcon#about to read 3, iclass 17, count 2 2006.173.08:44:01.28#ibcon#read 3, iclass 17, count 2 2006.173.08:44:01.28#ibcon#about to read 4, iclass 17, count 2 2006.173.08:44:01.28#ibcon#read 4, iclass 17, count 2 2006.173.08:44:01.28#ibcon#about to read 5, iclass 17, count 2 2006.173.08:44:01.28#ibcon#read 5, iclass 17, count 2 2006.173.08:44:01.28#ibcon#about to read 6, iclass 17, count 2 2006.173.08:44:01.28#ibcon#read 6, iclass 17, count 2 2006.173.08:44:01.28#ibcon#end of sib2, iclass 17, count 2 2006.173.08:44:01.28#ibcon#*mode == 0, iclass 17, count 2 2006.173.08:44:01.28#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.08:44:01.28#ibcon#[27=AT05-04\r\n] 2006.173.08:44:01.28#ibcon#*before write, iclass 17, count 2 2006.173.08:44:01.28#ibcon#enter sib2, iclass 17, count 2 2006.173.08:44:01.28#ibcon#flushed, iclass 17, count 2 2006.173.08:44:01.28#ibcon#about to write, iclass 17, count 2 2006.173.08:44:01.28#ibcon#wrote, iclass 17, count 2 2006.173.08:44:01.28#ibcon#about to read 3, iclass 17, count 2 2006.173.08:44:01.31#ibcon#read 3, iclass 17, count 2 2006.173.08:44:01.31#ibcon#about to read 4, iclass 17, count 2 2006.173.08:44:01.31#ibcon#read 4, iclass 17, count 2 2006.173.08:44:01.31#ibcon#about to read 5, iclass 17, count 2 2006.173.08:44:01.31#ibcon#read 5, iclass 17, count 2 2006.173.08:44:01.31#ibcon#about to read 6, iclass 17, count 2 2006.173.08:44:01.31#ibcon#read 6, iclass 17, count 2 2006.173.08:44:01.31#ibcon#end of sib2, iclass 17, count 2 2006.173.08:44:01.31#ibcon#*after write, iclass 17, count 2 2006.173.08:44:01.31#ibcon#*before return 0, iclass 17, count 2 2006.173.08:44:01.31#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.08:44:01.31#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.08:44:01.31#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.08:44:01.31#ibcon#ireg 7 cls_cnt 0 2006.173.08:44:01.31#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.08:44:01.43#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.08:44:01.43#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.08:44:01.43#ibcon#enter wrdev, iclass 17, count 0 2006.173.08:44:01.43#ibcon#first serial, iclass 17, count 0 2006.173.08:44:01.43#ibcon#enter sib2, iclass 17, count 0 2006.173.08:44:01.43#ibcon#flushed, iclass 17, count 0 2006.173.08:44:01.43#ibcon#about to write, iclass 17, count 0 2006.173.08:44:01.43#ibcon#wrote, iclass 17, count 0 2006.173.08:44:01.43#ibcon#about to read 3, iclass 17, count 0 2006.173.08:44:01.45#ibcon#read 3, iclass 17, count 0 2006.173.08:44:01.45#ibcon#about to read 4, iclass 17, count 0 2006.173.08:44:01.45#ibcon#read 4, iclass 17, count 0 2006.173.08:44:01.45#ibcon#about to read 5, iclass 17, count 0 2006.173.08:44:01.45#ibcon#read 5, iclass 17, count 0 2006.173.08:44:01.45#ibcon#about to read 6, iclass 17, count 0 2006.173.08:44:01.45#ibcon#read 6, iclass 17, count 0 2006.173.08:44:01.45#ibcon#end of sib2, iclass 17, count 0 2006.173.08:44:01.45#ibcon#*mode == 0, iclass 17, count 0 2006.173.08:44:01.45#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.08:44:01.45#ibcon#[27=USB\r\n] 2006.173.08:44:01.45#ibcon#*before write, iclass 17, count 0 2006.173.08:44:01.45#ibcon#enter sib2, iclass 17, count 0 2006.173.08:44:01.45#ibcon#flushed, iclass 17, count 0 2006.173.08:44:01.45#ibcon#about to write, iclass 17, count 0 2006.173.08:44:01.45#ibcon#wrote, iclass 17, count 0 2006.173.08:44:01.45#ibcon#about to read 3, iclass 17, count 0 2006.173.08:44:01.48#ibcon#read 3, iclass 17, count 0 2006.173.08:44:01.48#ibcon#about to read 4, iclass 17, count 0 2006.173.08:44:01.48#ibcon#read 4, iclass 17, count 0 2006.173.08:44:01.48#ibcon#about to read 5, iclass 17, count 0 2006.173.08:44:01.48#ibcon#read 5, iclass 17, count 0 2006.173.08:44:01.48#ibcon#about to read 6, iclass 17, count 0 2006.173.08:44:01.48#ibcon#read 6, iclass 17, count 0 2006.173.08:44:01.48#ibcon#end of sib2, iclass 17, count 0 2006.173.08:44:01.48#ibcon#*after write, iclass 17, count 0 2006.173.08:44:01.48#ibcon#*before return 0, iclass 17, count 0 2006.173.08:44:01.48#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.08:44:01.48#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.08:44:01.48#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.08:44:01.48#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.08:44:01.48$vck44/vblo=6,719.99 2006.173.08:44:01.48#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.08:44:01.48#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.08:44:01.48#ibcon#ireg 17 cls_cnt 0 2006.173.08:44:01.48#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.08:44:01.48#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.08:44:01.48#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.08:44:01.48#ibcon#enter wrdev, iclass 19, count 0 2006.173.08:44:01.48#ibcon#first serial, iclass 19, count 0 2006.173.08:44:01.48#ibcon#enter sib2, iclass 19, count 0 2006.173.08:44:01.48#ibcon#flushed, iclass 19, count 0 2006.173.08:44:01.48#ibcon#about to write, iclass 19, count 0 2006.173.08:44:01.48#ibcon#wrote, iclass 19, count 0 2006.173.08:44:01.48#ibcon#about to read 3, iclass 19, count 0 2006.173.08:44:01.50#ibcon#read 3, iclass 19, count 0 2006.173.08:44:01.50#ibcon#about to read 4, iclass 19, count 0 2006.173.08:44:01.50#ibcon#read 4, iclass 19, count 0 2006.173.08:44:01.50#ibcon#about to read 5, iclass 19, count 0 2006.173.08:44:01.50#ibcon#read 5, iclass 19, count 0 2006.173.08:44:01.50#ibcon#about to read 6, iclass 19, count 0 2006.173.08:44:01.50#ibcon#read 6, iclass 19, count 0 2006.173.08:44:01.50#ibcon#end of sib2, iclass 19, count 0 2006.173.08:44:01.50#ibcon#*mode == 0, iclass 19, count 0 2006.173.08:44:01.50#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.08:44:01.50#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.08:44:01.50#ibcon#*before write, iclass 19, count 0 2006.173.08:44:01.50#ibcon#enter sib2, iclass 19, count 0 2006.173.08:44:01.50#ibcon#flushed, iclass 19, count 0 2006.173.08:44:01.50#ibcon#about to write, iclass 19, count 0 2006.173.08:44:01.50#ibcon#wrote, iclass 19, count 0 2006.173.08:44:01.50#ibcon#about to read 3, iclass 19, count 0 2006.173.08:44:01.54#ibcon#read 3, iclass 19, count 0 2006.173.08:44:01.54#ibcon#about to read 4, iclass 19, count 0 2006.173.08:44:01.54#ibcon#read 4, iclass 19, count 0 2006.173.08:44:01.54#ibcon#about to read 5, iclass 19, count 0 2006.173.08:44:01.54#ibcon#read 5, iclass 19, count 0 2006.173.08:44:01.54#ibcon#about to read 6, iclass 19, count 0 2006.173.08:44:01.54#ibcon#read 6, iclass 19, count 0 2006.173.08:44:01.54#ibcon#end of sib2, iclass 19, count 0 2006.173.08:44:01.54#ibcon#*after write, iclass 19, count 0 2006.173.08:44:01.54#ibcon#*before return 0, iclass 19, count 0 2006.173.08:44:01.54#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.08:44:01.54#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.08:44:01.54#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.08:44:01.54#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.08:44:01.54$vck44/vb=6,4 2006.173.08:44:01.54#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.08:44:01.54#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.08:44:01.54#ibcon#ireg 11 cls_cnt 2 2006.173.08:44:01.54#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.08:44:01.60#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.08:44:01.60#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.08:44:01.60#ibcon#enter wrdev, iclass 21, count 2 2006.173.08:44:01.60#ibcon#first serial, iclass 21, count 2 2006.173.08:44:01.60#ibcon#enter sib2, iclass 21, count 2 2006.173.08:44:01.60#ibcon#flushed, iclass 21, count 2 2006.173.08:44:01.60#ibcon#about to write, iclass 21, count 2 2006.173.08:44:01.60#ibcon#wrote, iclass 21, count 2 2006.173.08:44:01.60#ibcon#about to read 3, iclass 21, count 2 2006.173.08:44:01.62#ibcon#read 3, iclass 21, count 2 2006.173.08:44:01.62#ibcon#about to read 4, iclass 21, count 2 2006.173.08:44:01.62#ibcon#read 4, iclass 21, count 2 2006.173.08:44:01.62#ibcon#about to read 5, iclass 21, count 2 2006.173.08:44:01.62#ibcon#read 5, iclass 21, count 2 2006.173.08:44:01.62#ibcon#about to read 6, iclass 21, count 2 2006.173.08:44:01.62#ibcon#read 6, iclass 21, count 2 2006.173.08:44:01.62#ibcon#end of sib2, iclass 21, count 2 2006.173.08:44:01.62#ibcon#*mode == 0, iclass 21, count 2 2006.173.08:44:01.62#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.08:44:01.62#ibcon#[27=AT06-04\r\n] 2006.173.08:44:01.62#ibcon#*before write, iclass 21, count 2 2006.173.08:44:01.62#ibcon#enter sib2, iclass 21, count 2 2006.173.08:44:01.62#ibcon#flushed, iclass 21, count 2 2006.173.08:44:01.62#ibcon#about to write, iclass 21, count 2 2006.173.08:44:01.62#ibcon#wrote, iclass 21, count 2 2006.173.08:44:01.62#ibcon#about to read 3, iclass 21, count 2 2006.173.08:44:01.65#ibcon#read 3, iclass 21, count 2 2006.173.08:44:01.65#ibcon#about to read 4, iclass 21, count 2 2006.173.08:44:01.65#ibcon#read 4, iclass 21, count 2 2006.173.08:44:01.65#ibcon#about to read 5, iclass 21, count 2 2006.173.08:44:01.65#ibcon#read 5, iclass 21, count 2 2006.173.08:44:01.65#ibcon#about to read 6, iclass 21, count 2 2006.173.08:44:01.65#ibcon#read 6, iclass 21, count 2 2006.173.08:44:01.65#ibcon#end of sib2, iclass 21, count 2 2006.173.08:44:01.65#ibcon#*after write, iclass 21, count 2 2006.173.08:44:01.65#ibcon#*before return 0, iclass 21, count 2 2006.173.08:44:01.65#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.08:44:01.65#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.08:44:01.65#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.08:44:01.65#ibcon#ireg 7 cls_cnt 0 2006.173.08:44:01.65#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.08:44:01.77#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.08:44:01.77#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.08:44:01.77#ibcon#enter wrdev, iclass 21, count 0 2006.173.08:44:01.77#ibcon#first serial, iclass 21, count 0 2006.173.08:44:01.77#ibcon#enter sib2, iclass 21, count 0 2006.173.08:44:01.77#ibcon#flushed, iclass 21, count 0 2006.173.08:44:01.77#ibcon#about to write, iclass 21, count 0 2006.173.08:44:01.77#ibcon#wrote, iclass 21, count 0 2006.173.08:44:01.77#ibcon#about to read 3, iclass 21, count 0 2006.173.08:44:01.79#ibcon#read 3, iclass 21, count 0 2006.173.08:44:01.79#ibcon#about to read 4, iclass 21, count 0 2006.173.08:44:01.79#ibcon#read 4, iclass 21, count 0 2006.173.08:44:01.79#ibcon#about to read 5, iclass 21, count 0 2006.173.08:44:01.79#ibcon#read 5, iclass 21, count 0 2006.173.08:44:01.79#ibcon#about to read 6, iclass 21, count 0 2006.173.08:44:01.79#ibcon#read 6, iclass 21, count 0 2006.173.08:44:01.79#ibcon#end of sib2, iclass 21, count 0 2006.173.08:44:01.79#ibcon#*mode == 0, iclass 21, count 0 2006.173.08:44:01.79#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.08:44:01.79#ibcon#[27=USB\r\n] 2006.173.08:44:01.79#ibcon#*before write, iclass 21, count 0 2006.173.08:44:01.79#ibcon#enter sib2, iclass 21, count 0 2006.173.08:44:01.79#ibcon#flushed, iclass 21, count 0 2006.173.08:44:01.79#ibcon#about to write, iclass 21, count 0 2006.173.08:44:01.79#ibcon#wrote, iclass 21, count 0 2006.173.08:44:01.79#ibcon#about to read 3, iclass 21, count 0 2006.173.08:44:01.82#ibcon#read 3, iclass 21, count 0 2006.173.08:44:01.82#ibcon#about to read 4, iclass 21, count 0 2006.173.08:44:01.82#ibcon#read 4, iclass 21, count 0 2006.173.08:44:01.82#ibcon#about to read 5, iclass 21, count 0 2006.173.08:44:01.82#ibcon#read 5, iclass 21, count 0 2006.173.08:44:01.82#ibcon#about to read 6, iclass 21, count 0 2006.173.08:44:01.82#ibcon#read 6, iclass 21, count 0 2006.173.08:44:01.82#ibcon#end of sib2, iclass 21, count 0 2006.173.08:44:01.82#ibcon#*after write, iclass 21, count 0 2006.173.08:44:01.82#ibcon#*before return 0, iclass 21, count 0 2006.173.08:44:01.82#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.08:44:01.82#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.08:44:01.82#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.08:44:01.82#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.08:44:01.82$vck44/vblo=7,734.99 2006.173.08:44:01.82#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.08:44:01.82#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.08:44:01.82#ibcon#ireg 17 cls_cnt 0 2006.173.08:44:01.82#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.08:44:01.82#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.08:44:01.82#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.08:44:01.82#ibcon#enter wrdev, iclass 23, count 0 2006.173.08:44:01.82#ibcon#first serial, iclass 23, count 0 2006.173.08:44:01.82#ibcon#enter sib2, iclass 23, count 0 2006.173.08:44:01.82#ibcon#flushed, iclass 23, count 0 2006.173.08:44:01.82#ibcon#about to write, iclass 23, count 0 2006.173.08:44:01.82#ibcon#wrote, iclass 23, count 0 2006.173.08:44:01.82#ibcon#about to read 3, iclass 23, count 0 2006.173.08:44:01.84#ibcon#read 3, iclass 23, count 0 2006.173.08:44:01.84#ibcon#about to read 4, iclass 23, count 0 2006.173.08:44:01.84#ibcon#read 4, iclass 23, count 0 2006.173.08:44:01.84#ibcon#about to read 5, iclass 23, count 0 2006.173.08:44:01.84#ibcon#read 5, iclass 23, count 0 2006.173.08:44:01.84#ibcon#about to read 6, iclass 23, count 0 2006.173.08:44:01.84#ibcon#read 6, iclass 23, count 0 2006.173.08:44:01.84#ibcon#end of sib2, iclass 23, count 0 2006.173.08:44:01.84#ibcon#*mode == 0, iclass 23, count 0 2006.173.08:44:01.84#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.08:44:01.84#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.08:44:01.84#ibcon#*before write, iclass 23, count 0 2006.173.08:44:01.84#ibcon#enter sib2, iclass 23, count 0 2006.173.08:44:01.84#ibcon#flushed, iclass 23, count 0 2006.173.08:44:01.84#ibcon#about to write, iclass 23, count 0 2006.173.08:44:01.84#ibcon#wrote, iclass 23, count 0 2006.173.08:44:01.84#ibcon#about to read 3, iclass 23, count 0 2006.173.08:44:01.88#ibcon#read 3, iclass 23, count 0 2006.173.08:44:01.88#ibcon#about to read 4, iclass 23, count 0 2006.173.08:44:01.88#ibcon#read 4, iclass 23, count 0 2006.173.08:44:01.88#ibcon#about to read 5, iclass 23, count 0 2006.173.08:44:01.88#ibcon#read 5, iclass 23, count 0 2006.173.08:44:01.88#ibcon#about to read 6, iclass 23, count 0 2006.173.08:44:01.88#ibcon#read 6, iclass 23, count 0 2006.173.08:44:01.88#ibcon#end of sib2, iclass 23, count 0 2006.173.08:44:01.88#ibcon#*after write, iclass 23, count 0 2006.173.08:44:01.88#ibcon#*before return 0, iclass 23, count 0 2006.173.08:44:01.88#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.08:44:01.88#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.08:44:01.88#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.08:44:01.88#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.08:44:01.88$vck44/vb=7,4 2006.173.08:44:01.88#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.08:44:01.88#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.08:44:01.88#ibcon#ireg 11 cls_cnt 2 2006.173.08:44:01.88#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.08:44:01.94#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.08:44:01.94#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.08:44:01.94#ibcon#enter wrdev, iclass 25, count 2 2006.173.08:44:01.94#ibcon#first serial, iclass 25, count 2 2006.173.08:44:01.94#ibcon#enter sib2, iclass 25, count 2 2006.173.08:44:01.94#ibcon#flushed, iclass 25, count 2 2006.173.08:44:01.94#ibcon#about to write, iclass 25, count 2 2006.173.08:44:01.94#ibcon#wrote, iclass 25, count 2 2006.173.08:44:01.94#ibcon#about to read 3, iclass 25, count 2 2006.173.08:44:01.96#ibcon#read 3, iclass 25, count 2 2006.173.08:44:01.96#ibcon#about to read 4, iclass 25, count 2 2006.173.08:44:01.96#ibcon#read 4, iclass 25, count 2 2006.173.08:44:01.96#ibcon#about to read 5, iclass 25, count 2 2006.173.08:44:01.96#ibcon#read 5, iclass 25, count 2 2006.173.08:44:01.96#ibcon#about to read 6, iclass 25, count 2 2006.173.08:44:01.96#ibcon#read 6, iclass 25, count 2 2006.173.08:44:01.96#ibcon#end of sib2, iclass 25, count 2 2006.173.08:44:01.96#ibcon#*mode == 0, iclass 25, count 2 2006.173.08:44:01.96#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.08:44:01.96#ibcon#[27=AT07-04\r\n] 2006.173.08:44:01.96#ibcon#*before write, iclass 25, count 2 2006.173.08:44:01.96#ibcon#enter sib2, iclass 25, count 2 2006.173.08:44:01.96#ibcon#flushed, iclass 25, count 2 2006.173.08:44:01.96#ibcon#about to write, iclass 25, count 2 2006.173.08:44:01.96#ibcon#wrote, iclass 25, count 2 2006.173.08:44:01.96#ibcon#about to read 3, iclass 25, count 2 2006.173.08:44:01.99#ibcon#read 3, iclass 25, count 2 2006.173.08:44:01.99#ibcon#about to read 4, iclass 25, count 2 2006.173.08:44:01.99#ibcon#read 4, iclass 25, count 2 2006.173.08:44:01.99#ibcon#about to read 5, iclass 25, count 2 2006.173.08:44:01.99#ibcon#read 5, iclass 25, count 2 2006.173.08:44:01.99#ibcon#about to read 6, iclass 25, count 2 2006.173.08:44:01.99#ibcon#read 6, iclass 25, count 2 2006.173.08:44:01.99#ibcon#end of sib2, iclass 25, count 2 2006.173.08:44:01.99#ibcon#*after write, iclass 25, count 2 2006.173.08:44:01.99#ibcon#*before return 0, iclass 25, count 2 2006.173.08:44:01.99#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.08:44:01.99#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.08:44:01.99#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.08:44:01.99#ibcon#ireg 7 cls_cnt 0 2006.173.08:44:01.99#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.08:44:02.11#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.08:44:02.11#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.08:44:02.11#ibcon#enter wrdev, iclass 25, count 0 2006.173.08:44:02.11#ibcon#first serial, iclass 25, count 0 2006.173.08:44:02.11#ibcon#enter sib2, iclass 25, count 0 2006.173.08:44:02.11#ibcon#flushed, iclass 25, count 0 2006.173.08:44:02.11#ibcon#about to write, iclass 25, count 0 2006.173.08:44:02.11#ibcon#wrote, iclass 25, count 0 2006.173.08:44:02.11#ibcon#about to read 3, iclass 25, count 0 2006.173.08:44:02.13#ibcon#read 3, iclass 25, count 0 2006.173.08:44:02.13#ibcon#about to read 4, iclass 25, count 0 2006.173.08:44:02.13#ibcon#read 4, iclass 25, count 0 2006.173.08:44:02.13#ibcon#about to read 5, iclass 25, count 0 2006.173.08:44:02.13#ibcon#read 5, iclass 25, count 0 2006.173.08:44:02.13#ibcon#about to read 6, iclass 25, count 0 2006.173.08:44:02.13#ibcon#read 6, iclass 25, count 0 2006.173.08:44:02.13#ibcon#end of sib2, iclass 25, count 0 2006.173.08:44:02.13#ibcon#*mode == 0, iclass 25, count 0 2006.173.08:44:02.13#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.08:44:02.13#ibcon#[27=USB\r\n] 2006.173.08:44:02.13#ibcon#*before write, iclass 25, count 0 2006.173.08:44:02.13#ibcon#enter sib2, iclass 25, count 0 2006.173.08:44:02.13#ibcon#flushed, iclass 25, count 0 2006.173.08:44:02.13#ibcon#about to write, iclass 25, count 0 2006.173.08:44:02.13#ibcon#wrote, iclass 25, count 0 2006.173.08:44:02.13#ibcon#about to read 3, iclass 25, count 0 2006.173.08:44:02.16#ibcon#read 3, iclass 25, count 0 2006.173.08:44:02.16#ibcon#about to read 4, iclass 25, count 0 2006.173.08:44:02.16#ibcon#read 4, iclass 25, count 0 2006.173.08:44:02.16#ibcon#about to read 5, iclass 25, count 0 2006.173.08:44:02.16#ibcon#read 5, iclass 25, count 0 2006.173.08:44:02.16#ibcon#about to read 6, iclass 25, count 0 2006.173.08:44:02.16#ibcon#read 6, iclass 25, count 0 2006.173.08:44:02.16#ibcon#end of sib2, iclass 25, count 0 2006.173.08:44:02.16#ibcon#*after write, iclass 25, count 0 2006.173.08:44:02.16#ibcon#*before return 0, iclass 25, count 0 2006.173.08:44:02.16#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.08:44:02.16#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.08:44:02.16#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.08:44:02.16#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.08:44:02.16$vck44/vblo=8,744.99 2006.173.08:44:02.16#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.08:44:02.16#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.08:44:02.16#ibcon#ireg 17 cls_cnt 0 2006.173.08:44:02.16#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.08:44:02.16#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.08:44:02.16#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.08:44:02.16#ibcon#enter wrdev, iclass 27, count 0 2006.173.08:44:02.16#ibcon#first serial, iclass 27, count 0 2006.173.08:44:02.16#ibcon#enter sib2, iclass 27, count 0 2006.173.08:44:02.16#ibcon#flushed, iclass 27, count 0 2006.173.08:44:02.16#ibcon#about to write, iclass 27, count 0 2006.173.08:44:02.16#ibcon#wrote, iclass 27, count 0 2006.173.08:44:02.16#ibcon#about to read 3, iclass 27, count 0 2006.173.08:44:02.18#ibcon#read 3, iclass 27, count 0 2006.173.08:44:02.18#ibcon#about to read 4, iclass 27, count 0 2006.173.08:44:02.18#ibcon#read 4, iclass 27, count 0 2006.173.08:44:02.18#ibcon#about to read 5, iclass 27, count 0 2006.173.08:44:02.18#ibcon#read 5, iclass 27, count 0 2006.173.08:44:02.18#ibcon#about to read 6, iclass 27, count 0 2006.173.08:44:02.18#ibcon#read 6, iclass 27, count 0 2006.173.08:44:02.18#ibcon#end of sib2, iclass 27, count 0 2006.173.08:44:02.18#ibcon#*mode == 0, iclass 27, count 0 2006.173.08:44:02.18#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.08:44:02.18#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.08:44:02.18#ibcon#*before write, iclass 27, count 0 2006.173.08:44:02.18#ibcon#enter sib2, iclass 27, count 0 2006.173.08:44:02.18#ibcon#flushed, iclass 27, count 0 2006.173.08:44:02.18#ibcon#about to write, iclass 27, count 0 2006.173.08:44:02.18#ibcon#wrote, iclass 27, count 0 2006.173.08:44:02.18#ibcon#about to read 3, iclass 27, count 0 2006.173.08:44:02.22#ibcon#read 3, iclass 27, count 0 2006.173.08:44:02.22#ibcon#about to read 4, iclass 27, count 0 2006.173.08:44:02.22#ibcon#read 4, iclass 27, count 0 2006.173.08:44:02.22#ibcon#about to read 5, iclass 27, count 0 2006.173.08:44:02.22#ibcon#read 5, iclass 27, count 0 2006.173.08:44:02.22#ibcon#about to read 6, iclass 27, count 0 2006.173.08:44:02.22#ibcon#read 6, iclass 27, count 0 2006.173.08:44:02.22#ibcon#end of sib2, iclass 27, count 0 2006.173.08:44:02.22#ibcon#*after write, iclass 27, count 0 2006.173.08:44:02.22#ibcon#*before return 0, iclass 27, count 0 2006.173.08:44:02.22#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.08:44:02.22#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.08:44:02.22#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.08:44:02.22#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.08:44:02.22$vck44/vb=8,4 2006.173.08:44:02.22#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.08:44:02.22#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.08:44:02.22#ibcon#ireg 11 cls_cnt 2 2006.173.08:44:02.22#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.08:44:02.28#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.08:44:02.28#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.08:44:02.28#ibcon#enter wrdev, iclass 29, count 2 2006.173.08:44:02.28#ibcon#first serial, iclass 29, count 2 2006.173.08:44:02.28#ibcon#enter sib2, iclass 29, count 2 2006.173.08:44:02.28#ibcon#flushed, iclass 29, count 2 2006.173.08:44:02.28#ibcon#about to write, iclass 29, count 2 2006.173.08:44:02.28#ibcon#wrote, iclass 29, count 2 2006.173.08:44:02.28#ibcon#about to read 3, iclass 29, count 2 2006.173.08:44:02.30#ibcon#read 3, iclass 29, count 2 2006.173.08:44:02.30#ibcon#about to read 4, iclass 29, count 2 2006.173.08:44:02.30#ibcon#read 4, iclass 29, count 2 2006.173.08:44:02.30#ibcon#about to read 5, iclass 29, count 2 2006.173.08:44:02.30#ibcon#read 5, iclass 29, count 2 2006.173.08:44:02.30#ibcon#about to read 6, iclass 29, count 2 2006.173.08:44:02.30#ibcon#read 6, iclass 29, count 2 2006.173.08:44:02.30#ibcon#end of sib2, iclass 29, count 2 2006.173.08:44:02.30#ibcon#*mode == 0, iclass 29, count 2 2006.173.08:44:02.30#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.08:44:02.30#ibcon#[27=AT08-04\r\n] 2006.173.08:44:02.30#ibcon#*before write, iclass 29, count 2 2006.173.08:44:02.30#ibcon#enter sib2, iclass 29, count 2 2006.173.08:44:02.30#ibcon#flushed, iclass 29, count 2 2006.173.08:44:02.30#ibcon#about to write, iclass 29, count 2 2006.173.08:44:02.30#ibcon#wrote, iclass 29, count 2 2006.173.08:44:02.30#ibcon#about to read 3, iclass 29, count 2 2006.173.08:44:02.33#ibcon#read 3, iclass 29, count 2 2006.173.08:44:02.33#ibcon#about to read 4, iclass 29, count 2 2006.173.08:44:02.33#ibcon#read 4, iclass 29, count 2 2006.173.08:44:02.33#ibcon#about to read 5, iclass 29, count 2 2006.173.08:44:02.33#ibcon#read 5, iclass 29, count 2 2006.173.08:44:02.33#ibcon#about to read 6, iclass 29, count 2 2006.173.08:44:02.33#ibcon#read 6, iclass 29, count 2 2006.173.08:44:02.33#ibcon#end of sib2, iclass 29, count 2 2006.173.08:44:02.33#ibcon#*after write, iclass 29, count 2 2006.173.08:44:02.33#ibcon#*before return 0, iclass 29, count 2 2006.173.08:44:02.33#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.08:44:02.33#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.08:44:02.33#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.08:44:02.33#ibcon#ireg 7 cls_cnt 0 2006.173.08:44:02.33#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.08:44:02.45#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.08:44:02.45#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.08:44:02.45#ibcon#enter wrdev, iclass 29, count 0 2006.173.08:44:02.45#ibcon#first serial, iclass 29, count 0 2006.173.08:44:02.45#ibcon#enter sib2, iclass 29, count 0 2006.173.08:44:02.45#ibcon#flushed, iclass 29, count 0 2006.173.08:44:02.45#ibcon#about to write, iclass 29, count 0 2006.173.08:44:02.45#ibcon#wrote, iclass 29, count 0 2006.173.08:44:02.45#ibcon#about to read 3, iclass 29, count 0 2006.173.08:44:02.47#ibcon#read 3, iclass 29, count 0 2006.173.08:44:02.47#ibcon#about to read 4, iclass 29, count 0 2006.173.08:44:02.47#ibcon#read 4, iclass 29, count 0 2006.173.08:44:02.47#ibcon#about to read 5, iclass 29, count 0 2006.173.08:44:02.47#ibcon#read 5, iclass 29, count 0 2006.173.08:44:02.47#ibcon#about to read 6, iclass 29, count 0 2006.173.08:44:02.47#ibcon#read 6, iclass 29, count 0 2006.173.08:44:02.47#ibcon#end of sib2, iclass 29, count 0 2006.173.08:44:02.47#ibcon#*mode == 0, iclass 29, count 0 2006.173.08:44:02.47#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.08:44:02.47#ibcon#[27=USB\r\n] 2006.173.08:44:02.47#ibcon#*before write, iclass 29, count 0 2006.173.08:44:02.47#ibcon#enter sib2, iclass 29, count 0 2006.173.08:44:02.47#ibcon#flushed, iclass 29, count 0 2006.173.08:44:02.47#ibcon#about to write, iclass 29, count 0 2006.173.08:44:02.47#ibcon#wrote, iclass 29, count 0 2006.173.08:44:02.47#ibcon#about to read 3, iclass 29, count 0 2006.173.08:44:02.50#ibcon#read 3, iclass 29, count 0 2006.173.08:44:02.50#ibcon#about to read 4, iclass 29, count 0 2006.173.08:44:02.50#ibcon#read 4, iclass 29, count 0 2006.173.08:44:02.50#ibcon#about to read 5, iclass 29, count 0 2006.173.08:44:02.50#ibcon#read 5, iclass 29, count 0 2006.173.08:44:02.50#ibcon#about to read 6, iclass 29, count 0 2006.173.08:44:02.50#ibcon#read 6, iclass 29, count 0 2006.173.08:44:02.50#ibcon#end of sib2, iclass 29, count 0 2006.173.08:44:02.50#ibcon#*after write, iclass 29, count 0 2006.173.08:44:02.50#ibcon#*before return 0, iclass 29, count 0 2006.173.08:44:02.50#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.08:44:02.50#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.08:44:02.50#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.08:44:02.50#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.08:44:02.50$vck44/vabw=wide 2006.173.08:44:02.50#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.08:44:02.50#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.08:44:02.50#ibcon#ireg 8 cls_cnt 0 2006.173.08:44:02.50#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.08:44:02.50#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.08:44:02.50#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.08:44:02.50#ibcon#enter wrdev, iclass 31, count 0 2006.173.08:44:02.50#ibcon#first serial, iclass 31, count 0 2006.173.08:44:02.50#ibcon#enter sib2, iclass 31, count 0 2006.173.08:44:02.50#ibcon#flushed, iclass 31, count 0 2006.173.08:44:02.50#ibcon#about to write, iclass 31, count 0 2006.173.08:44:02.50#ibcon#wrote, iclass 31, count 0 2006.173.08:44:02.50#ibcon#about to read 3, iclass 31, count 0 2006.173.08:44:02.52#ibcon#read 3, iclass 31, count 0 2006.173.08:44:02.52#ibcon#about to read 4, iclass 31, count 0 2006.173.08:44:02.52#ibcon#read 4, iclass 31, count 0 2006.173.08:44:02.52#ibcon#about to read 5, iclass 31, count 0 2006.173.08:44:02.52#ibcon#read 5, iclass 31, count 0 2006.173.08:44:02.52#ibcon#about to read 6, iclass 31, count 0 2006.173.08:44:02.52#ibcon#read 6, iclass 31, count 0 2006.173.08:44:02.52#ibcon#end of sib2, iclass 31, count 0 2006.173.08:44:02.52#ibcon#*mode == 0, iclass 31, count 0 2006.173.08:44:02.52#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.08:44:02.52#ibcon#[25=BW32\r\n] 2006.173.08:44:02.52#ibcon#*before write, iclass 31, count 0 2006.173.08:44:02.52#ibcon#enter sib2, iclass 31, count 0 2006.173.08:44:02.52#ibcon#flushed, iclass 31, count 0 2006.173.08:44:02.52#ibcon#about to write, iclass 31, count 0 2006.173.08:44:02.52#ibcon#wrote, iclass 31, count 0 2006.173.08:44:02.52#ibcon#about to read 3, iclass 31, count 0 2006.173.08:44:02.55#ibcon#read 3, iclass 31, count 0 2006.173.08:44:02.55#ibcon#about to read 4, iclass 31, count 0 2006.173.08:44:02.55#ibcon#read 4, iclass 31, count 0 2006.173.08:44:02.55#ibcon#about to read 5, iclass 31, count 0 2006.173.08:44:02.55#ibcon#read 5, iclass 31, count 0 2006.173.08:44:02.55#ibcon#about to read 6, iclass 31, count 0 2006.173.08:44:02.55#ibcon#read 6, iclass 31, count 0 2006.173.08:44:02.55#ibcon#end of sib2, iclass 31, count 0 2006.173.08:44:02.55#ibcon#*after write, iclass 31, count 0 2006.173.08:44:02.55#ibcon#*before return 0, iclass 31, count 0 2006.173.08:44:02.55#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.08:44:02.55#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.08:44:02.55#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.08:44:02.55#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.08:44:02.55$vck44/vbbw=wide 2006.173.08:44:02.55#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.08:44:02.55#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.08:44:02.55#ibcon#ireg 8 cls_cnt 0 2006.173.08:44:02.55#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.08:44:02.62#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.08:44:02.62#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.08:44:02.62#ibcon#enter wrdev, iclass 33, count 0 2006.173.08:44:02.62#ibcon#first serial, iclass 33, count 0 2006.173.08:44:02.62#ibcon#enter sib2, iclass 33, count 0 2006.173.08:44:02.62#ibcon#flushed, iclass 33, count 0 2006.173.08:44:02.62#ibcon#about to write, iclass 33, count 0 2006.173.08:44:02.62#ibcon#wrote, iclass 33, count 0 2006.173.08:44:02.62#ibcon#about to read 3, iclass 33, count 0 2006.173.08:44:02.64#ibcon#read 3, iclass 33, count 0 2006.173.08:44:02.64#ibcon#about to read 4, iclass 33, count 0 2006.173.08:44:02.64#ibcon#read 4, iclass 33, count 0 2006.173.08:44:02.64#ibcon#about to read 5, iclass 33, count 0 2006.173.08:44:02.64#ibcon#read 5, iclass 33, count 0 2006.173.08:44:02.64#ibcon#about to read 6, iclass 33, count 0 2006.173.08:44:02.64#ibcon#read 6, iclass 33, count 0 2006.173.08:44:02.64#ibcon#end of sib2, iclass 33, count 0 2006.173.08:44:02.64#ibcon#*mode == 0, iclass 33, count 0 2006.173.08:44:02.64#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.08:44:02.64#ibcon#[27=BW32\r\n] 2006.173.08:44:02.64#ibcon#*before write, iclass 33, count 0 2006.173.08:44:02.64#ibcon#enter sib2, iclass 33, count 0 2006.173.08:44:02.64#ibcon#flushed, iclass 33, count 0 2006.173.08:44:02.64#ibcon#about to write, iclass 33, count 0 2006.173.08:44:02.64#ibcon#wrote, iclass 33, count 0 2006.173.08:44:02.64#ibcon#about to read 3, iclass 33, count 0 2006.173.08:44:02.67#ibcon#read 3, iclass 33, count 0 2006.173.08:44:02.67#ibcon#about to read 4, iclass 33, count 0 2006.173.08:44:02.67#ibcon#read 4, iclass 33, count 0 2006.173.08:44:02.67#ibcon#about to read 5, iclass 33, count 0 2006.173.08:44:02.67#ibcon#read 5, iclass 33, count 0 2006.173.08:44:02.67#ibcon#about to read 6, iclass 33, count 0 2006.173.08:44:02.67#ibcon#read 6, iclass 33, count 0 2006.173.08:44:02.67#ibcon#end of sib2, iclass 33, count 0 2006.173.08:44:02.67#ibcon#*after write, iclass 33, count 0 2006.173.08:44:02.67#ibcon#*before return 0, iclass 33, count 0 2006.173.08:44:02.67#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.08:44:02.67#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.08:44:02.67#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.08:44:02.67#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.08:44:02.67$setupk4/ifdk4 2006.173.08:44:02.67$ifdk4/lo= 2006.173.08:44:02.67$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.08:44:02.67$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.08:44:02.67$ifdk4/patch= 2006.173.08:44:02.67$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.08:44:02.67$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.08:44:02.67$setupk4/!*+20s 2006.173.08:44:10.53#abcon#<5=/00 0.2 0.8 23.17 871004.0\r\n> 2006.173.08:44:10.55#abcon#{5=INTERFACE CLEAR} 2006.173.08:44:10.61#abcon#[5=S1D000X0/0*\r\n] 2006.173.08:44:17.17$setupk4/"tpicd 2006.173.08:44:17.17$setupk4/echo=off 2006.173.08:44:17.17$setupk4/xlog=off 2006.173.08:44:17.17:!2006.173.08:44:23 2006.173.08:44:23.00:preob 2006.173.08:44:23.13#trakl#Source acquired 2006.173.08:44:23.13#flagr#flagr/antenna,acquired 2006.173.08:44:24.13/onsource/TRACKING 2006.173.08:44:24.13:!2006.173.08:44:33 2006.173.08:44:33.00:"tape 2006.173.08:44:33.00:"st=record 2006.173.08:44:33.00:data_valid=on 2006.173.08:44:33.00:midob 2006.173.08:44:33.13/onsource/TRACKING 2006.173.08:44:33.13/wx/23.16,1004.0,87 2006.173.08:44:33.28/cable/+6.5025E-03 2006.173.08:44:34.37/va/01,07,usb,yes,34,37 2006.173.08:44:34.37/va/02,06,usb,yes,34,34 2006.173.08:44:34.37/va/03,05,usb,yes,43,45 2006.173.08:44:34.37/va/04,06,usb,yes,34,36 2006.173.08:44:34.37/va/05,04,usb,yes,27,27 2006.173.08:44:34.37/va/06,03,usb,yes,38,38 2006.173.08:44:34.37/va/07,04,usb,yes,31,32 2006.173.08:44:34.37/va/08,04,usb,yes,26,32 2006.173.08:44:34.60/valo/01,524.99,yes,locked 2006.173.08:44:34.60/valo/02,534.99,yes,locked 2006.173.08:44:34.60/valo/03,564.99,yes,locked 2006.173.08:44:34.60/valo/04,624.99,yes,locked 2006.173.08:44:34.60/valo/05,734.99,yes,locked 2006.173.08:44:34.60/valo/06,814.99,yes,locked 2006.173.08:44:34.60/valo/07,864.99,yes,locked 2006.173.08:44:34.60/valo/08,884.99,yes,locked 2006.173.08:44:35.69/vb/01,04,usb,yes,28,27 2006.173.08:44:35.69/vb/02,04,usb,yes,31,31 2006.173.08:44:35.69/vb/03,04,usb,yes,28,31 2006.173.08:44:35.69/vb/04,04,usb,yes,32,31 2006.173.08:44:35.69/vb/05,04,usb,yes,25,27 2006.173.08:44:35.69/vb/06,04,usb,yes,29,26 2006.173.08:44:35.69/vb/07,04,usb,yes,29,29 2006.173.08:44:35.69/vb/08,04,usb,yes,27,30 2006.173.08:44:35.93/vblo/01,629.99,yes,locked 2006.173.08:44:35.93/vblo/02,634.99,yes,locked 2006.173.08:44:35.93/vblo/03,649.99,yes,locked 2006.173.08:44:35.93/vblo/04,679.99,yes,locked 2006.173.08:44:35.93/vblo/05,709.99,yes,locked 2006.173.08:44:35.93/vblo/06,719.99,yes,locked 2006.173.08:44:35.93/vblo/07,734.99,yes,locked 2006.173.08:44:35.93/vblo/08,744.99,yes,locked 2006.173.08:44:36.08/vabw/8 2006.173.08:44:36.23/vbbw/8 2006.173.08:44:36.32/xfe/off,on,14.7 2006.173.08:44:36.71/ifatt/23,28,28,28 2006.173.08:44:37.07/fmout-gps/S +3.96E-07 2006.173.08:44:37.11:!2006.173.08:50:33 2006.173.08:50:33.00:data_valid=off 2006.173.08:50:33.00:"et 2006.173.08:50:33.01:!+3s 2006.173.08:50:36.02:"tape 2006.173.08:50:36.02:postob 2006.173.08:50:36.17/cable/+6.5004E-03 2006.173.08:50:36.17/wx/23.12,1004.1,86 2006.173.08:50:36.23/fmout-gps/S +3.97E-07 2006.173.08:50:36.23:scan_name=173-0856,jd0606,230 2006.173.08:50:36.23:source=0014+813,001708.47,813508.1,2000.0,neutral 2006.173.08:50:37.14#flagr#flagr/antenna,new-source 2006.173.08:50:37.14:checkk5 2006.173.08:50:37.50/chk_autoobs//k5ts1/ autoobs is running! 2006.173.08:50:37.91/chk_autoobs//k5ts2/ autoobs is running! 2006.173.08:50:38.32/chk_autoobs//k5ts3/ autoobs is running! 2006.173.08:50:38.71/chk_autoobs//k5ts4/ autoobs is running! 2006.173.08:50:39.11/chk_obsdata//k5ts1/T1730844??a.dat file size is correct (nominal:1440MB, actual:1436MB). 2006.173.08:50:39.54/chk_obsdata//k5ts2/T1730844??b.dat file size is correct (nominal:1440MB, actual:1436MB). 2006.173.08:50:39.94/chk_obsdata//k5ts3/T1730844??c.dat file size is correct (nominal:1440MB, actual:1436MB). 2006.173.08:50:40.37/chk_obsdata//k5ts4/T1730844??d.dat file size is correct (nominal:1440MB, actual:1436MB). 2006.173.08:50:41.09/k5log//k5ts1_log_newline 2006.173.08:50:41.80/k5log//k5ts2_log_newline 2006.173.08:50:42.50/k5log//k5ts3_log_newline 2006.173.08:50:43.21/k5log//k5ts4_log_newline 2006.173.08:50:43.23/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.08:50:43.23:setupk4=1 2006.173.08:50:43.23$setupk4/echo=on 2006.173.08:50:43.23$setupk4/pcalon 2006.173.08:50:43.23$pcalon/"no phase cal control is implemented here 2006.173.08:50:43.23$setupk4/"tpicd=stop 2006.173.08:50:43.23$setupk4/"rec=synch_on 2006.173.08:50:43.23$setupk4/"rec_mode=128 2006.173.08:50:43.23$setupk4/!* 2006.173.08:50:43.23$setupk4/recpk4 2006.173.08:50:43.23$recpk4/recpatch= 2006.173.08:50:43.23$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.08:50:43.23$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.08:50:43.24$setupk4/vck44 2006.173.08:50:43.24$vck44/valo=1,524.99 2006.173.08:50:43.24#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.08:50:43.24#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.08:50:43.24#ibcon#ireg 17 cls_cnt 0 2006.173.08:50:43.24#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.08:50:43.24#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.08:50:43.24#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.08:50:43.24#ibcon#enter wrdev, iclass 14, count 0 2006.173.08:50:43.24#ibcon#first serial, iclass 14, count 0 2006.173.08:50:43.24#ibcon#enter sib2, iclass 14, count 0 2006.173.08:50:43.24#ibcon#flushed, iclass 14, count 0 2006.173.08:50:43.24#ibcon#about to write, iclass 14, count 0 2006.173.08:50:43.24#ibcon#wrote, iclass 14, count 0 2006.173.08:50:43.24#ibcon#about to read 3, iclass 14, count 0 2006.173.08:50:43.25#ibcon#read 3, iclass 14, count 0 2006.173.08:50:43.25#ibcon#about to read 4, iclass 14, count 0 2006.173.08:50:43.25#ibcon#read 4, iclass 14, count 0 2006.173.08:50:43.25#ibcon#about to read 5, iclass 14, count 0 2006.173.08:50:43.25#ibcon#read 5, iclass 14, count 0 2006.173.08:50:43.25#ibcon#about to read 6, iclass 14, count 0 2006.173.08:50:43.25#ibcon#read 6, iclass 14, count 0 2006.173.08:50:43.25#ibcon#end of sib2, iclass 14, count 0 2006.173.08:50:43.25#ibcon#*mode == 0, iclass 14, count 0 2006.173.08:50:43.25#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.08:50:43.25#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.08:50:43.25#ibcon#*before write, iclass 14, count 0 2006.173.08:50:43.25#ibcon#enter sib2, iclass 14, count 0 2006.173.08:50:43.25#ibcon#flushed, iclass 14, count 0 2006.173.08:50:43.25#ibcon#about to write, iclass 14, count 0 2006.173.08:50:43.25#ibcon#wrote, iclass 14, count 0 2006.173.08:50:43.25#ibcon#about to read 3, iclass 14, count 0 2006.173.08:50:43.30#ibcon#read 3, iclass 14, count 0 2006.173.08:50:43.30#ibcon#about to read 4, iclass 14, count 0 2006.173.08:50:43.30#ibcon#read 4, iclass 14, count 0 2006.173.08:50:43.30#ibcon#about to read 5, iclass 14, count 0 2006.173.08:50:43.30#ibcon#read 5, iclass 14, count 0 2006.173.08:50:43.30#ibcon#about to read 6, iclass 14, count 0 2006.173.08:50:43.30#ibcon#read 6, iclass 14, count 0 2006.173.08:50:43.30#ibcon#end of sib2, iclass 14, count 0 2006.173.08:50:43.30#ibcon#*after write, iclass 14, count 0 2006.173.08:50:43.30#ibcon#*before return 0, iclass 14, count 0 2006.173.08:50:43.30#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.08:50:43.30#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.08:50:43.30#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.08:50:43.30#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.08:50:43.30$vck44/va=1,7 2006.173.08:50:43.30#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.08:50:43.30#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.08:50:43.30#ibcon#ireg 11 cls_cnt 2 2006.173.08:50:43.30#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.08:50:43.30#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.08:50:43.30#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.08:50:43.30#ibcon#enter wrdev, iclass 16, count 2 2006.173.08:50:43.30#ibcon#first serial, iclass 16, count 2 2006.173.08:50:43.30#ibcon#enter sib2, iclass 16, count 2 2006.173.08:50:43.30#ibcon#flushed, iclass 16, count 2 2006.173.08:50:43.30#ibcon#about to write, iclass 16, count 2 2006.173.08:50:43.30#ibcon#wrote, iclass 16, count 2 2006.173.08:50:43.30#ibcon#about to read 3, iclass 16, count 2 2006.173.08:50:43.32#ibcon#read 3, iclass 16, count 2 2006.173.08:50:43.32#ibcon#about to read 4, iclass 16, count 2 2006.173.08:50:43.32#ibcon#read 4, iclass 16, count 2 2006.173.08:50:43.32#ibcon#about to read 5, iclass 16, count 2 2006.173.08:50:43.32#ibcon#read 5, iclass 16, count 2 2006.173.08:50:43.32#ibcon#about to read 6, iclass 16, count 2 2006.173.08:50:43.32#ibcon#read 6, iclass 16, count 2 2006.173.08:50:43.32#ibcon#end of sib2, iclass 16, count 2 2006.173.08:50:43.32#ibcon#*mode == 0, iclass 16, count 2 2006.173.08:50:43.32#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.08:50:43.32#ibcon#[25=AT01-07\r\n] 2006.173.08:50:43.32#ibcon#*before write, iclass 16, count 2 2006.173.08:50:43.32#ibcon#enter sib2, iclass 16, count 2 2006.173.08:50:43.32#ibcon#flushed, iclass 16, count 2 2006.173.08:50:43.32#ibcon#about to write, iclass 16, count 2 2006.173.08:50:43.32#ibcon#wrote, iclass 16, count 2 2006.173.08:50:43.32#ibcon#about to read 3, iclass 16, count 2 2006.173.08:50:43.35#ibcon#read 3, iclass 16, count 2 2006.173.08:50:43.35#ibcon#about to read 4, iclass 16, count 2 2006.173.08:50:43.35#ibcon#read 4, iclass 16, count 2 2006.173.08:50:43.35#ibcon#about to read 5, iclass 16, count 2 2006.173.08:50:43.35#ibcon#read 5, iclass 16, count 2 2006.173.08:50:43.35#ibcon#about to read 6, iclass 16, count 2 2006.173.08:50:43.35#ibcon#read 6, iclass 16, count 2 2006.173.08:50:43.35#ibcon#end of sib2, iclass 16, count 2 2006.173.08:50:43.35#ibcon#*after write, iclass 16, count 2 2006.173.08:50:43.35#ibcon#*before return 0, iclass 16, count 2 2006.173.08:50:43.35#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.08:50:43.35#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.08:50:43.35#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.08:50:43.35#ibcon#ireg 7 cls_cnt 0 2006.173.08:50:43.35#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.08:50:43.47#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.08:50:43.47#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.08:50:43.47#ibcon#enter wrdev, iclass 16, count 0 2006.173.08:50:43.47#ibcon#first serial, iclass 16, count 0 2006.173.08:50:43.47#ibcon#enter sib2, iclass 16, count 0 2006.173.08:50:43.47#ibcon#flushed, iclass 16, count 0 2006.173.08:50:43.47#ibcon#about to write, iclass 16, count 0 2006.173.08:50:43.47#ibcon#wrote, iclass 16, count 0 2006.173.08:50:43.47#ibcon#about to read 3, iclass 16, count 0 2006.173.08:50:43.49#ibcon#read 3, iclass 16, count 0 2006.173.08:50:43.49#ibcon#about to read 4, iclass 16, count 0 2006.173.08:50:43.49#ibcon#read 4, iclass 16, count 0 2006.173.08:50:43.49#ibcon#about to read 5, iclass 16, count 0 2006.173.08:50:43.49#ibcon#read 5, iclass 16, count 0 2006.173.08:50:43.49#ibcon#about to read 6, iclass 16, count 0 2006.173.08:50:43.49#ibcon#read 6, iclass 16, count 0 2006.173.08:50:43.49#ibcon#end of sib2, iclass 16, count 0 2006.173.08:50:43.49#ibcon#*mode == 0, iclass 16, count 0 2006.173.08:50:43.49#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.08:50:43.49#ibcon#[25=USB\r\n] 2006.173.08:50:43.49#ibcon#*before write, iclass 16, count 0 2006.173.08:50:43.49#ibcon#enter sib2, iclass 16, count 0 2006.173.08:50:43.49#ibcon#flushed, iclass 16, count 0 2006.173.08:50:43.49#ibcon#about to write, iclass 16, count 0 2006.173.08:50:43.49#ibcon#wrote, iclass 16, count 0 2006.173.08:50:43.49#ibcon#about to read 3, iclass 16, count 0 2006.173.08:50:43.52#ibcon#read 3, iclass 16, count 0 2006.173.08:50:43.52#ibcon#about to read 4, iclass 16, count 0 2006.173.08:50:43.52#ibcon#read 4, iclass 16, count 0 2006.173.08:50:43.52#ibcon#about to read 5, iclass 16, count 0 2006.173.08:50:43.52#ibcon#read 5, iclass 16, count 0 2006.173.08:50:43.52#ibcon#about to read 6, iclass 16, count 0 2006.173.08:50:43.52#ibcon#read 6, iclass 16, count 0 2006.173.08:50:43.52#ibcon#end of sib2, iclass 16, count 0 2006.173.08:50:43.52#ibcon#*after write, iclass 16, count 0 2006.173.08:50:43.52#ibcon#*before return 0, iclass 16, count 0 2006.173.08:50:43.52#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.08:50:43.52#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.08:50:43.52#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.08:50:43.52#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.08:50:43.52$vck44/valo=2,534.99 2006.173.08:50:43.52#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.08:50:43.52#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.08:50:43.52#ibcon#ireg 17 cls_cnt 0 2006.173.08:50:43.52#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.08:50:43.52#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.08:50:43.52#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.08:50:43.52#ibcon#enter wrdev, iclass 18, count 0 2006.173.08:50:43.52#ibcon#first serial, iclass 18, count 0 2006.173.08:50:43.52#ibcon#enter sib2, iclass 18, count 0 2006.173.08:50:43.52#ibcon#flushed, iclass 18, count 0 2006.173.08:50:43.52#ibcon#about to write, iclass 18, count 0 2006.173.08:50:43.52#ibcon#wrote, iclass 18, count 0 2006.173.08:50:43.52#ibcon#about to read 3, iclass 18, count 0 2006.173.08:50:43.54#ibcon#read 3, iclass 18, count 0 2006.173.08:50:43.54#ibcon#about to read 4, iclass 18, count 0 2006.173.08:50:43.54#ibcon#read 4, iclass 18, count 0 2006.173.08:50:43.54#ibcon#about to read 5, iclass 18, count 0 2006.173.08:50:43.54#ibcon#read 5, iclass 18, count 0 2006.173.08:50:43.54#ibcon#about to read 6, iclass 18, count 0 2006.173.08:50:43.54#ibcon#read 6, iclass 18, count 0 2006.173.08:50:43.54#ibcon#end of sib2, iclass 18, count 0 2006.173.08:50:43.54#ibcon#*mode == 0, iclass 18, count 0 2006.173.08:50:43.54#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.08:50:43.54#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.08:50:43.54#ibcon#*before write, iclass 18, count 0 2006.173.08:50:43.54#ibcon#enter sib2, iclass 18, count 0 2006.173.08:50:43.54#ibcon#flushed, iclass 18, count 0 2006.173.08:50:43.54#ibcon#about to write, iclass 18, count 0 2006.173.08:50:43.54#ibcon#wrote, iclass 18, count 0 2006.173.08:50:43.54#ibcon#about to read 3, iclass 18, count 0 2006.173.08:50:43.58#ibcon#read 3, iclass 18, count 0 2006.173.08:50:43.58#ibcon#about to read 4, iclass 18, count 0 2006.173.08:50:43.58#ibcon#read 4, iclass 18, count 0 2006.173.08:50:43.58#ibcon#about to read 5, iclass 18, count 0 2006.173.08:50:43.58#ibcon#read 5, iclass 18, count 0 2006.173.08:50:43.58#ibcon#about to read 6, iclass 18, count 0 2006.173.08:50:43.58#ibcon#read 6, iclass 18, count 0 2006.173.08:50:43.58#ibcon#end of sib2, iclass 18, count 0 2006.173.08:50:43.58#ibcon#*after write, iclass 18, count 0 2006.173.08:50:43.58#ibcon#*before return 0, iclass 18, count 0 2006.173.08:50:43.58#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.08:50:43.58#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.08:50:43.58#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.08:50:43.58#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.08:50:43.58$vck44/va=2,6 2006.173.08:50:43.58#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.08:50:43.58#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.08:50:43.58#ibcon#ireg 11 cls_cnt 2 2006.173.08:50:43.58#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.08:50:43.64#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.08:50:43.64#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.08:50:43.64#ibcon#enter wrdev, iclass 20, count 2 2006.173.08:50:43.64#ibcon#first serial, iclass 20, count 2 2006.173.08:50:43.64#ibcon#enter sib2, iclass 20, count 2 2006.173.08:50:43.64#ibcon#flushed, iclass 20, count 2 2006.173.08:50:43.64#ibcon#about to write, iclass 20, count 2 2006.173.08:50:43.64#ibcon#wrote, iclass 20, count 2 2006.173.08:50:43.64#ibcon#about to read 3, iclass 20, count 2 2006.173.08:50:43.66#ibcon#read 3, iclass 20, count 2 2006.173.08:50:43.66#ibcon#about to read 4, iclass 20, count 2 2006.173.08:50:43.66#ibcon#read 4, iclass 20, count 2 2006.173.08:50:43.66#ibcon#about to read 5, iclass 20, count 2 2006.173.08:50:43.66#ibcon#read 5, iclass 20, count 2 2006.173.08:50:43.66#ibcon#about to read 6, iclass 20, count 2 2006.173.08:50:43.66#ibcon#read 6, iclass 20, count 2 2006.173.08:50:43.66#ibcon#end of sib2, iclass 20, count 2 2006.173.08:50:43.66#ibcon#*mode == 0, iclass 20, count 2 2006.173.08:50:43.66#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.08:50:43.66#ibcon#[25=AT02-06\r\n] 2006.173.08:50:43.66#ibcon#*before write, iclass 20, count 2 2006.173.08:50:43.66#ibcon#enter sib2, iclass 20, count 2 2006.173.08:50:43.66#ibcon#flushed, iclass 20, count 2 2006.173.08:50:43.66#ibcon#about to write, iclass 20, count 2 2006.173.08:50:43.66#ibcon#wrote, iclass 20, count 2 2006.173.08:50:43.66#ibcon#about to read 3, iclass 20, count 2 2006.173.08:50:43.69#ibcon#read 3, iclass 20, count 2 2006.173.08:50:43.69#ibcon#about to read 4, iclass 20, count 2 2006.173.08:50:43.69#ibcon#read 4, iclass 20, count 2 2006.173.08:50:43.69#ibcon#about to read 5, iclass 20, count 2 2006.173.08:50:43.69#ibcon#read 5, iclass 20, count 2 2006.173.08:50:43.69#ibcon#about to read 6, iclass 20, count 2 2006.173.08:50:43.69#ibcon#read 6, iclass 20, count 2 2006.173.08:50:43.69#ibcon#end of sib2, iclass 20, count 2 2006.173.08:50:43.69#ibcon#*after write, iclass 20, count 2 2006.173.08:50:43.69#ibcon#*before return 0, iclass 20, count 2 2006.173.08:50:43.69#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.08:50:43.69#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.08:50:43.69#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.08:50:43.69#ibcon#ireg 7 cls_cnt 0 2006.173.08:50:43.69#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.08:50:43.81#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.08:50:43.81#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.08:50:43.81#ibcon#enter wrdev, iclass 20, count 0 2006.173.08:50:43.81#ibcon#first serial, iclass 20, count 0 2006.173.08:50:43.81#ibcon#enter sib2, iclass 20, count 0 2006.173.08:50:43.81#ibcon#flushed, iclass 20, count 0 2006.173.08:50:43.81#ibcon#about to write, iclass 20, count 0 2006.173.08:50:43.81#ibcon#wrote, iclass 20, count 0 2006.173.08:50:43.81#ibcon#about to read 3, iclass 20, count 0 2006.173.08:50:43.83#ibcon#read 3, iclass 20, count 0 2006.173.08:50:43.83#ibcon#about to read 4, iclass 20, count 0 2006.173.08:50:43.83#ibcon#read 4, iclass 20, count 0 2006.173.08:50:43.83#ibcon#about to read 5, iclass 20, count 0 2006.173.08:50:43.83#ibcon#read 5, iclass 20, count 0 2006.173.08:50:43.83#ibcon#about to read 6, iclass 20, count 0 2006.173.08:50:43.83#ibcon#read 6, iclass 20, count 0 2006.173.08:50:43.83#ibcon#end of sib2, iclass 20, count 0 2006.173.08:50:43.83#ibcon#*mode == 0, iclass 20, count 0 2006.173.08:50:43.83#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.08:50:43.83#ibcon#[25=USB\r\n] 2006.173.08:50:43.83#ibcon#*before write, iclass 20, count 0 2006.173.08:50:43.83#ibcon#enter sib2, iclass 20, count 0 2006.173.08:50:43.83#ibcon#flushed, iclass 20, count 0 2006.173.08:50:43.83#ibcon#about to write, iclass 20, count 0 2006.173.08:50:43.83#ibcon#wrote, iclass 20, count 0 2006.173.08:50:43.83#ibcon#about to read 3, iclass 20, count 0 2006.173.08:50:43.86#ibcon#read 3, iclass 20, count 0 2006.173.08:50:43.86#ibcon#about to read 4, iclass 20, count 0 2006.173.08:50:43.86#ibcon#read 4, iclass 20, count 0 2006.173.08:50:43.86#ibcon#about to read 5, iclass 20, count 0 2006.173.08:50:43.86#ibcon#read 5, iclass 20, count 0 2006.173.08:50:43.86#ibcon#about to read 6, iclass 20, count 0 2006.173.08:50:43.86#ibcon#read 6, iclass 20, count 0 2006.173.08:50:43.86#ibcon#end of sib2, iclass 20, count 0 2006.173.08:50:43.86#ibcon#*after write, iclass 20, count 0 2006.173.08:50:43.86#ibcon#*before return 0, iclass 20, count 0 2006.173.08:50:43.86#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.08:50:43.86#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.08:50:43.86#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.08:50:43.86#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.08:50:43.86$vck44/valo=3,564.99 2006.173.08:50:43.86#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.08:50:43.86#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.08:50:43.86#ibcon#ireg 17 cls_cnt 0 2006.173.08:50:43.86#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.08:50:43.86#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.08:50:43.86#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.08:50:43.86#ibcon#enter wrdev, iclass 22, count 0 2006.173.08:50:43.86#ibcon#first serial, iclass 22, count 0 2006.173.08:50:43.86#ibcon#enter sib2, iclass 22, count 0 2006.173.08:50:43.86#ibcon#flushed, iclass 22, count 0 2006.173.08:50:43.86#ibcon#about to write, iclass 22, count 0 2006.173.08:50:43.86#ibcon#wrote, iclass 22, count 0 2006.173.08:50:43.86#ibcon#about to read 3, iclass 22, count 0 2006.173.08:50:43.88#ibcon#read 3, iclass 22, count 0 2006.173.08:50:43.88#ibcon#about to read 4, iclass 22, count 0 2006.173.08:50:43.88#ibcon#read 4, iclass 22, count 0 2006.173.08:50:43.88#ibcon#about to read 5, iclass 22, count 0 2006.173.08:50:43.88#ibcon#read 5, iclass 22, count 0 2006.173.08:50:43.88#ibcon#about to read 6, iclass 22, count 0 2006.173.08:50:43.88#ibcon#read 6, iclass 22, count 0 2006.173.08:50:43.88#ibcon#end of sib2, iclass 22, count 0 2006.173.08:50:43.88#ibcon#*mode == 0, iclass 22, count 0 2006.173.08:50:43.88#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.08:50:43.88#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.08:50:43.88#ibcon#*before write, iclass 22, count 0 2006.173.08:50:43.88#ibcon#enter sib2, iclass 22, count 0 2006.173.08:50:43.88#ibcon#flushed, iclass 22, count 0 2006.173.08:50:43.88#ibcon#about to write, iclass 22, count 0 2006.173.08:50:43.88#ibcon#wrote, iclass 22, count 0 2006.173.08:50:43.88#ibcon#about to read 3, iclass 22, count 0 2006.173.08:50:43.92#ibcon#read 3, iclass 22, count 0 2006.173.08:50:43.92#ibcon#about to read 4, iclass 22, count 0 2006.173.08:50:43.92#ibcon#read 4, iclass 22, count 0 2006.173.08:50:43.92#ibcon#about to read 5, iclass 22, count 0 2006.173.08:50:43.92#ibcon#read 5, iclass 22, count 0 2006.173.08:50:43.92#ibcon#about to read 6, iclass 22, count 0 2006.173.08:50:43.92#ibcon#read 6, iclass 22, count 0 2006.173.08:50:43.92#ibcon#end of sib2, iclass 22, count 0 2006.173.08:50:43.92#ibcon#*after write, iclass 22, count 0 2006.173.08:50:43.92#ibcon#*before return 0, iclass 22, count 0 2006.173.08:50:43.92#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.08:50:43.92#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.08:50:43.92#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.08:50:43.92#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.08:50:43.92$vck44/va=3,5 2006.173.08:50:43.92#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.08:50:43.92#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.08:50:43.92#ibcon#ireg 11 cls_cnt 2 2006.173.08:50:43.92#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.08:50:43.98#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.08:50:43.98#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.08:50:43.98#ibcon#enter wrdev, iclass 24, count 2 2006.173.08:50:43.98#ibcon#first serial, iclass 24, count 2 2006.173.08:50:43.98#ibcon#enter sib2, iclass 24, count 2 2006.173.08:50:43.98#ibcon#flushed, iclass 24, count 2 2006.173.08:50:43.98#ibcon#about to write, iclass 24, count 2 2006.173.08:50:43.98#ibcon#wrote, iclass 24, count 2 2006.173.08:50:43.98#ibcon#about to read 3, iclass 24, count 2 2006.173.08:50:44.00#ibcon#read 3, iclass 24, count 2 2006.173.08:50:44.00#ibcon#about to read 4, iclass 24, count 2 2006.173.08:50:44.00#ibcon#read 4, iclass 24, count 2 2006.173.08:50:44.00#ibcon#about to read 5, iclass 24, count 2 2006.173.08:50:44.00#ibcon#read 5, iclass 24, count 2 2006.173.08:50:44.00#ibcon#about to read 6, iclass 24, count 2 2006.173.08:50:44.00#ibcon#read 6, iclass 24, count 2 2006.173.08:50:44.00#ibcon#end of sib2, iclass 24, count 2 2006.173.08:50:44.00#ibcon#*mode == 0, iclass 24, count 2 2006.173.08:50:44.00#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.08:50:44.00#ibcon#[25=AT03-05\r\n] 2006.173.08:50:44.00#ibcon#*before write, iclass 24, count 2 2006.173.08:50:44.00#ibcon#enter sib2, iclass 24, count 2 2006.173.08:50:44.00#ibcon#flushed, iclass 24, count 2 2006.173.08:50:44.00#ibcon#about to write, iclass 24, count 2 2006.173.08:50:44.00#ibcon#wrote, iclass 24, count 2 2006.173.08:50:44.00#ibcon#about to read 3, iclass 24, count 2 2006.173.08:50:44.03#ibcon#read 3, iclass 24, count 2 2006.173.08:50:44.03#ibcon#about to read 4, iclass 24, count 2 2006.173.08:50:44.03#ibcon#read 4, iclass 24, count 2 2006.173.08:50:44.03#ibcon#about to read 5, iclass 24, count 2 2006.173.08:50:44.03#ibcon#read 5, iclass 24, count 2 2006.173.08:50:44.03#ibcon#about to read 6, iclass 24, count 2 2006.173.08:50:44.03#ibcon#read 6, iclass 24, count 2 2006.173.08:50:44.03#ibcon#end of sib2, iclass 24, count 2 2006.173.08:50:44.03#ibcon#*after write, iclass 24, count 2 2006.173.08:50:44.03#ibcon#*before return 0, iclass 24, count 2 2006.173.08:50:44.03#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.08:50:44.03#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.08:50:44.03#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.08:50:44.03#ibcon#ireg 7 cls_cnt 0 2006.173.08:50:44.03#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.08:50:44.15#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.08:50:44.15#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.08:50:44.15#ibcon#enter wrdev, iclass 24, count 0 2006.173.08:50:44.15#ibcon#first serial, iclass 24, count 0 2006.173.08:50:44.15#ibcon#enter sib2, iclass 24, count 0 2006.173.08:50:44.15#ibcon#flushed, iclass 24, count 0 2006.173.08:50:44.15#ibcon#about to write, iclass 24, count 0 2006.173.08:50:44.15#ibcon#wrote, iclass 24, count 0 2006.173.08:50:44.15#ibcon#about to read 3, iclass 24, count 0 2006.173.08:50:44.17#ibcon#read 3, iclass 24, count 0 2006.173.08:50:44.17#ibcon#about to read 4, iclass 24, count 0 2006.173.08:50:44.17#ibcon#read 4, iclass 24, count 0 2006.173.08:50:44.17#ibcon#about to read 5, iclass 24, count 0 2006.173.08:50:44.17#ibcon#read 5, iclass 24, count 0 2006.173.08:50:44.17#ibcon#about to read 6, iclass 24, count 0 2006.173.08:50:44.17#ibcon#read 6, iclass 24, count 0 2006.173.08:50:44.17#ibcon#end of sib2, iclass 24, count 0 2006.173.08:50:44.17#ibcon#*mode == 0, iclass 24, count 0 2006.173.08:50:44.17#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.08:50:44.17#ibcon#[25=USB\r\n] 2006.173.08:50:44.17#ibcon#*before write, iclass 24, count 0 2006.173.08:50:44.17#ibcon#enter sib2, iclass 24, count 0 2006.173.08:50:44.17#ibcon#flushed, iclass 24, count 0 2006.173.08:50:44.17#ibcon#about to write, iclass 24, count 0 2006.173.08:50:44.17#ibcon#wrote, iclass 24, count 0 2006.173.08:50:44.17#ibcon#about to read 3, iclass 24, count 0 2006.173.08:50:44.20#ibcon#read 3, iclass 24, count 0 2006.173.08:50:44.20#ibcon#about to read 4, iclass 24, count 0 2006.173.08:50:44.20#ibcon#read 4, iclass 24, count 0 2006.173.08:50:44.20#ibcon#about to read 5, iclass 24, count 0 2006.173.08:50:44.20#ibcon#read 5, iclass 24, count 0 2006.173.08:50:44.20#ibcon#about to read 6, iclass 24, count 0 2006.173.08:50:44.20#ibcon#read 6, iclass 24, count 0 2006.173.08:50:44.20#ibcon#end of sib2, iclass 24, count 0 2006.173.08:50:44.20#ibcon#*after write, iclass 24, count 0 2006.173.08:50:44.20#ibcon#*before return 0, iclass 24, count 0 2006.173.08:50:44.20#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.08:50:44.20#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.08:50:44.20#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.08:50:44.20#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.08:50:44.20$vck44/valo=4,624.99 2006.173.08:50:44.20#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.08:50:44.20#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.08:50:44.20#ibcon#ireg 17 cls_cnt 0 2006.173.08:50:44.20#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.08:50:44.20#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.08:50:44.20#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.08:50:44.20#ibcon#enter wrdev, iclass 26, count 0 2006.173.08:50:44.20#ibcon#first serial, iclass 26, count 0 2006.173.08:50:44.20#ibcon#enter sib2, iclass 26, count 0 2006.173.08:50:44.20#ibcon#flushed, iclass 26, count 0 2006.173.08:50:44.20#ibcon#about to write, iclass 26, count 0 2006.173.08:50:44.20#ibcon#wrote, iclass 26, count 0 2006.173.08:50:44.20#ibcon#about to read 3, iclass 26, count 0 2006.173.08:50:44.22#ibcon#read 3, iclass 26, count 0 2006.173.08:50:44.22#ibcon#about to read 4, iclass 26, count 0 2006.173.08:50:44.22#ibcon#read 4, iclass 26, count 0 2006.173.08:50:44.22#ibcon#about to read 5, iclass 26, count 0 2006.173.08:50:44.22#ibcon#read 5, iclass 26, count 0 2006.173.08:50:44.22#ibcon#about to read 6, iclass 26, count 0 2006.173.08:50:44.22#ibcon#read 6, iclass 26, count 0 2006.173.08:50:44.22#ibcon#end of sib2, iclass 26, count 0 2006.173.08:50:44.22#ibcon#*mode == 0, iclass 26, count 0 2006.173.08:50:44.22#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.08:50:44.22#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.08:50:44.22#ibcon#*before write, iclass 26, count 0 2006.173.08:50:44.22#ibcon#enter sib2, iclass 26, count 0 2006.173.08:50:44.22#ibcon#flushed, iclass 26, count 0 2006.173.08:50:44.22#ibcon#about to write, iclass 26, count 0 2006.173.08:50:44.22#ibcon#wrote, iclass 26, count 0 2006.173.08:50:44.22#ibcon#about to read 3, iclass 26, count 0 2006.173.08:50:44.26#ibcon#read 3, iclass 26, count 0 2006.173.08:50:44.26#ibcon#about to read 4, iclass 26, count 0 2006.173.08:50:44.26#ibcon#read 4, iclass 26, count 0 2006.173.08:50:44.26#ibcon#about to read 5, iclass 26, count 0 2006.173.08:50:44.26#ibcon#read 5, iclass 26, count 0 2006.173.08:50:44.26#ibcon#about to read 6, iclass 26, count 0 2006.173.08:50:44.26#ibcon#read 6, iclass 26, count 0 2006.173.08:50:44.26#ibcon#end of sib2, iclass 26, count 0 2006.173.08:50:44.26#ibcon#*after write, iclass 26, count 0 2006.173.08:50:44.26#ibcon#*before return 0, iclass 26, count 0 2006.173.08:50:44.26#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.08:50:44.26#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.08:50:44.26#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.08:50:44.26#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.08:50:44.26$vck44/va=4,6 2006.173.08:50:44.26#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.08:50:44.26#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.08:50:44.26#ibcon#ireg 11 cls_cnt 2 2006.173.08:50:44.26#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.08:50:44.32#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.08:50:44.32#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.08:50:44.32#ibcon#enter wrdev, iclass 28, count 2 2006.173.08:50:44.32#ibcon#first serial, iclass 28, count 2 2006.173.08:50:44.32#ibcon#enter sib2, iclass 28, count 2 2006.173.08:50:44.32#ibcon#flushed, iclass 28, count 2 2006.173.08:50:44.32#ibcon#about to write, iclass 28, count 2 2006.173.08:50:44.32#ibcon#wrote, iclass 28, count 2 2006.173.08:50:44.32#ibcon#about to read 3, iclass 28, count 2 2006.173.08:50:44.34#ibcon#read 3, iclass 28, count 2 2006.173.08:50:44.34#ibcon#about to read 4, iclass 28, count 2 2006.173.08:50:44.34#ibcon#read 4, iclass 28, count 2 2006.173.08:50:44.34#ibcon#about to read 5, iclass 28, count 2 2006.173.08:50:44.34#ibcon#read 5, iclass 28, count 2 2006.173.08:50:44.34#ibcon#about to read 6, iclass 28, count 2 2006.173.08:50:44.34#ibcon#read 6, iclass 28, count 2 2006.173.08:50:44.34#ibcon#end of sib2, iclass 28, count 2 2006.173.08:50:44.34#ibcon#*mode == 0, iclass 28, count 2 2006.173.08:50:44.34#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.08:50:44.34#ibcon#[25=AT04-06\r\n] 2006.173.08:50:44.34#ibcon#*before write, iclass 28, count 2 2006.173.08:50:44.34#ibcon#enter sib2, iclass 28, count 2 2006.173.08:50:44.34#ibcon#flushed, iclass 28, count 2 2006.173.08:50:44.34#ibcon#about to write, iclass 28, count 2 2006.173.08:50:44.34#ibcon#wrote, iclass 28, count 2 2006.173.08:50:44.34#ibcon#about to read 3, iclass 28, count 2 2006.173.08:50:44.37#ibcon#read 3, iclass 28, count 2 2006.173.08:50:44.37#ibcon#about to read 4, iclass 28, count 2 2006.173.08:50:44.37#ibcon#read 4, iclass 28, count 2 2006.173.08:50:44.37#ibcon#about to read 5, iclass 28, count 2 2006.173.08:50:44.37#ibcon#read 5, iclass 28, count 2 2006.173.08:50:44.37#ibcon#about to read 6, iclass 28, count 2 2006.173.08:50:44.37#ibcon#read 6, iclass 28, count 2 2006.173.08:50:44.37#ibcon#end of sib2, iclass 28, count 2 2006.173.08:50:44.37#ibcon#*after write, iclass 28, count 2 2006.173.08:50:44.37#ibcon#*before return 0, iclass 28, count 2 2006.173.08:50:44.37#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.08:50:44.37#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.08:50:44.37#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.08:50:44.37#ibcon#ireg 7 cls_cnt 0 2006.173.08:50:44.37#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.08:50:44.49#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.08:50:44.49#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.08:50:44.49#ibcon#enter wrdev, iclass 28, count 0 2006.173.08:50:44.49#ibcon#first serial, iclass 28, count 0 2006.173.08:50:44.49#ibcon#enter sib2, iclass 28, count 0 2006.173.08:50:44.49#ibcon#flushed, iclass 28, count 0 2006.173.08:50:44.49#ibcon#about to write, iclass 28, count 0 2006.173.08:50:44.49#ibcon#wrote, iclass 28, count 0 2006.173.08:50:44.49#ibcon#about to read 3, iclass 28, count 0 2006.173.08:50:44.51#ibcon#read 3, iclass 28, count 0 2006.173.08:50:44.51#ibcon#about to read 4, iclass 28, count 0 2006.173.08:50:44.51#ibcon#read 4, iclass 28, count 0 2006.173.08:50:44.51#ibcon#about to read 5, iclass 28, count 0 2006.173.08:50:44.51#ibcon#read 5, iclass 28, count 0 2006.173.08:50:44.51#ibcon#about to read 6, iclass 28, count 0 2006.173.08:50:44.51#ibcon#read 6, iclass 28, count 0 2006.173.08:50:44.51#ibcon#end of sib2, iclass 28, count 0 2006.173.08:50:44.51#ibcon#*mode == 0, iclass 28, count 0 2006.173.08:50:44.51#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.08:50:44.51#ibcon#[25=USB\r\n] 2006.173.08:50:44.51#ibcon#*before write, iclass 28, count 0 2006.173.08:50:44.51#ibcon#enter sib2, iclass 28, count 0 2006.173.08:50:44.51#ibcon#flushed, iclass 28, count 0 2006.173.08:50:44.51#ibcon#about to write, iclass 28, count 0 2006.173.08:50:44.51#ibcon#wrote, iclass 28, count 0 2006.173.08:50:44.51#ibcon#about to read 3, iclass 28, count 0 2006.173.08:50:44.54#ibcon#read 3, iclass 28, count 0 2006.173.08:50:44.54#ibcon#about to read 4, iclass 28, count 0 2006.173.08:50:44.54#ibcon#read 4, iclass 28, count 0 2006.173.08:50:44.54#ibcon#about to read 5, iclass 28, count 0 2006.173.08:50:44.54#ibcon#read 5, iclass 28, count 0 2006.173.08:50:44.54#ibcon#about to read 6, iclass 28, count 0 2006.173.08:50:44.54#ibcon#read 6, iclass 28, count 0 2006.173.08:50:44.54#ibcon#end of sib2, iclass 28, count 0 2006.173.08:50:44.54#ibcon#*after write, iclass 28, count 0 2006.173.08:50:44.54#ibcon#*before return 0, iclass 28, count 0 2006.173.08:50:44.54#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.08:50:44.54#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.08:50:44.54#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.08:50:44.54#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.08:50:44.54$vck44/valo=5,734.99 2006.173.08:50:44.54#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.08:50:44.54#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.08:50:44.54#ibcon#ireg 17 cls_cnt 0 2006.173.08:50:44.54#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.08:50:44.54#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.08:50:44.54#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.08:50:44.54#ibcon#enter wrdev, iclass 30, count 0 2006.173.08:50:44.54#ibcon#first serial, iclass 30, count 0 2006.173.08:50:44.54#ibcon#enter sib2, iclass 30, count 0 2006.173.08:50:44.54#ibcon#flushed, iclass 30, count 0 2006.173.08:50:44.54#ibcon#about to write, iclass 30, count 0 2006.173.08:50:44.54#ibcon#wrote, iclass 30, count 0 2006.173.08:50:44.54#ibcon#about to read 3, iclass 30, count 0 2006.173.08:50:44.56#ibcon#read 3, iclass 30, count 0 2006.173.08:50:44.56#ibcon#about to read 4, iclass 30, count 0 2006.173.08:50:44.56#ibcon#read 4, iclass 30, count 0 2006.173.08:50:44.56#ibcon#about to read 5, iclass 30, count 0 2006.173.08:50:44.56#ibcon#read 5, iclass 30, count 0 2006.173.08:50:44.56#ibcon#about to read 6, iclass 30, count 0 2006.173.08:50:44.56#ibcon#read 6, iclass 30, count 0 2006.173.08:50:44.56#ibcon#end of sib2, iclass 30, count 0 2006.173.08:50:44.56#ibcon#*mode == 0, iclass 30, count 0 2006.173.08:50:44.56#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.08:50:44.56#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.08:50:44.56#ibcon#*before write, iclass 30, count 0 2006.173.08:50:44.56#ibcon#enter sib2, iclass 30, count 0 2006.173.08:50:44.56#ibcon#flushed, iclass 30, count 0 2006.173.08:50:44.56#ibcon#about to write, iclass 30, count 0 2006.173.08:50:44.56#ibcon#wrote, iclass 30, count 0 2006.173.08:50:44.56#ibcon#about to read 3, iclass 30, count 0 2006.173.08:50:44.60#ibcon#read 3, iclass 30, count 0 2006.173.08:50:44.60#ibcon#about to read 4, iclass 30, count 0 2006.173.08:50:44.60#ibcon#read 4, iclass 30, count 0 2006.173.08:50:44.60#ibcon#about to read 5, iclass 30, count 0 2006.173.08:50:44.60#ibcon#read 5, iclass 30, count 0 2006.173.08:50:44.60#ibcon#about to read 6, iclass 30, count 0 2006.173.08:50:44.60#ibcon#read 6, iclass 30, count 0 2006.173.08:50:44.60#ibcon#end of sib2, iclass 30, count 0 2006.173.08:50:44.60#ibcon#*after write, iclass 30, count 0 2006.173.08:50:44.60#ibcon#*before return 0, iclass 30, count 0 2006.173.08:50:44.60#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.08:50:44.60#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.08:50:44.60#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.08:50:44.60#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.08:50:44.60$vck44/va=5,4 2006.173.08:50:44.60#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.173.08:50:44.60#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.173.08:50:44.60#ibcon#ireg 11 cls_cnt 2 2006.173.08:50:44.60#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.08:50:44.66#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.08:50:44.66#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.08:50:44.66#ibcon#enter wrdev, iclass 32, count 2 2006.173.08:50:44.66#ibcon#first serial, iclass 32, count 2 2006.173.08:50:44.66#ibcon#enter sib2, iclass 32, count 2 2006.173.08:50:44.66#ibcon#flushed, iclass 32, count 2 2006.173.08:50:44.66#ibcon#about to write, iclass 32, count 2 2006.173.08:50:44.66#ibcon#wrote, iclass 32, count 2 2006.173.08:50:44.66#ibcon#about to read 3, iclass 32, count 2 2006.173.08:50:44.68#ibcon#read 3, iclass 32, count 2 2006.173.08:50:44.68#ibcon#about to read 4, iclass 32, count 2 2006.173.08:50:44.68#ibcon#read 4, iclass 32, count 2 2006.173.08:50:44.68#ibcon#about to read 5, iclass 32, count 2 2006.173.08:50:44.68#ibcon#read 5, iclass 32, count 2 2006.173.08:50:44.68#ibcon#about to read 6, iclass 32, count 2 2006.173.08:50:44.68#ibcon#read 6, iclass 32, count 2 2006.173.08:50:44.68#ibcon#end of sib2, iclass 32, count 2 2006.173.08:50:44.68#ibcon#*mode == 0, iclass 32, count 2 2006.173.08:50:44.68#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.173.08:50:44.68#ibcon#[25=AT05-04\r\n] 2006.173.08:50:44.68#ibcon#*before write, iclass 32, count 2 2006.173.08:50:44.68#ibcon#enter sib2, iclass 32, count 2 2006.173.08:50:44.68#ibcon#flushed, iclass 32, count 2 2006.173.08:50:44.68#ibcon#about to write, iclass 32, count 2 2006.173.08:50:44.68#ibcon#wrote, iclass 32, count 2 2006.173.08:50:44.68#ibcon#about to read 3, iclass 32, count 2 2006.173.08:50:44.71#ibcon#read 3, iclass 32, count 2 2006.173.08:50:44.71#ibcon#about to read 4, iclass 32, count 2 2006.173.08:50:44.71#ibcon#read 4, iclass 32, count 2 2006.173.08:50:44.71#ibcon#about to read 5, iclass 32, count 2 2006.173.08:50:44.71#ibcon#read 5, iclass 32, count 2 2006.173.08:50:44.71#ibcon#about to read 6, iclass 32, count 2 2006.173.08:50:44.71#ibcon#read 6, iclass 32, count 2 2006.173.08:50:44.71#ibcon#end of sib2, iclass 32, count 2 2006.173.08:50:44.71#ibcon#*after write, iclass 32, count 2 2006.173.08:50:44.71#ibcon#*before return 0, iclass 32, count 2 2006.173.08:50:44.71#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.08:50:44.71#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.173.08:50:44.71#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.173.08:50:44.71#ibcon#ireg 7 cls_cnt 0 2006.173.08:50:44.71#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.08:50:44.83#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.08:50:44.83#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.08:50:44.83#ibcon#enter wrdev, iclass 32, count 0 2006.173.08:50:44.83#ibcon#first serial, iclass 32, count 0 2006.173.08:50:44.83#ibcon#enter sib2, iclass 32, count 0 2006.173.08:50:44.83#ibcon#flushed, iclass 32, count 0 2006.173.08:50:44.83#ibcon#about to write, iclass 32, count 0 2006.173.08:50:44.83#ibcon#wrote, iclass 32, count 0 2006.173.08:50:44.83#ibcon#about to read 3, iclass 32, count 0 2006.173.08:50:44.85#ibcon#read 3, iclass 32, count 0 2006.173.08:50:44.85#ibcon#about to read 4, iclass 32, count 0 2006.173.08:50:44.85#ibcon#read 4, iclass 32, count 0 2006.173.08:50:44.85#ibcon#about to read 5, iclass 32, count 0 2006.173.08:50:44.85#ibcon#read 5, iclass 32, count 0 2006.173.08:50:44.85#ibcon#about to read 6, iclass 32, count 0 2006.173.08:50:44.85#ibcon#read 6, iclass 32, count 0 2006.173.08:50:44.85#ibcon#end of sib2, iclass 32, count 0 2006.173.08:50:44.85#ibcon#*mode == 0, iclass 32, count 0 2006.173.08:50:44.85#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.08:50:44.85#ibcon#[25=USB\r\n] 2006.173.08:50:44.85#ibcon#*before write, iclass 32, count 0 2006.173.08:50:44.85#ibcon#enter sib2, iclass 32, count 0 2006.173.08:50:44.85#ibcon#flushed, iclass 32, count 0 2006.173.08:50:44.85#ibcon#about to write, iclass 32, count 0 2006.173.08:50:44.85#ibcon#wrote, iclass 32, count 0 2006.173.08:50:44.85#ibcon#about to read 3, iclass 32, count 0 2006.173.08:50:44.88#ibcon#read 3, iclass 32, count 0 2006.173.08:50:44.88#ibcon#about to read 4, iclass 32, count 0 2006.173.08:50:44.88#ibcon#read 4, iclass 32, count 0 2006.173.08:50:44.88#ibcon#about to read 5, iclass 32, count 0 2006.173.08:50:44.88#ibcon#read 5, iclass 32, count 0 2006.173.08:50:44.88#ibcon#about to read 6, iclass 32, count 0 2006.173.08:50:44.88#ibcon#read 6, iclass 32, count 0 2006.173.08:50:44.88#ibcon#end of sib2, iclass 32, count 0 2006.173.08:50:44.88#ibcon#*after write, iclass 32, count 0 2006.173.08:50:44.88#ibcon#*before return 0, iclass 32, count 0 2006.173.08:50:44.88#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.08:50:44.88#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.173.08:50:44.88#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.08:50:44.88#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.08:50:44.88$vck44/valo=6,814.99 2006.173.08:50:44.88#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.08:50:44.88#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.08:50:44.88#ibcon#ireg 17 cls_cnt 0 2006.173.08:50:44.88#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.08:50:44.88#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.08:50:44.88#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.08:50:44.88#ibcon#enter wrdev, iclass 34, count 0 2006.173.08:50:44.88#ibcon#first serial, iclass 34, count 0 2006.173.08:50:44.88#ibcon#enter sib2, iclass 34, count 0 2006.173.08:50:44.88#ibcon#flushed, iclass 34, count 0 2006.173.08:50:44.88#ibcon#about to write, iclass 34, count 0 2006.173.08:50:44.88#ibcon#wrote, iclass 34, count 0 2006.173.08:50:44.88#ibcon#about to read 3, iclass 34, count 0 2006.173.08:50:44.90#ibcon#read 3, iclass 34, count 0 2006.173.08:50:44.90#ibcon#about to read 4, iclass 34, count 0 2006.173.08:50:44.90#ibcon#read 4, iclass 34, count 0 2006.173.08:50:44.90#ibcon#about to read 5, iclass 34, count 0 2006.173.08:50:44.90#ibcon#read 5, iclass 34, count 0 2006.173.08:50:44.90#ibcon#about to read 6, iclass 34, count 0 2006.173.08:50:44.90#ibcon#read 6, iclass 34, count 0 2006.173.08:50:44.90#ibcon#end of sib2, iclass 34, count 0 2006.173.08:50:44.90#ibcon#*mode == 0, iclass 34, count 0 2006.173.08:50:44.90#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.08:50:44.90#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.08:50:44.90#ibcon#*before write, iclass 34, count 0 2006.173.08:50:44.90#ibcon#enter sib2, iclass 34, count 0 2006.173.08:50:44.90#ibcon#flushed, iclass 34, count 0 2006.173.08:50:44.90#ibcon#about to write, iclass 34, count 0 2006.173.08:50:44.90#ibcon#wrote, iclass 34, count 0 2006.173.08:50:44.90#ibcon#about to read 3, iclass 34, count 0 2006.173.08:50:44.94#ibcon#read 3, iclass 34, count 0 2006.173.08:50:44.94#ibcon#about to read 4, iclass 34, count 0 2006.173.08:50:44.94#ibcon#read 4, iclass 34, count 0 2006.173.08:50:44.94#ibcon#about to read 5, iclass 34, count 0 2006.173.08:50:44.94#ibcon#read 5, iclass 34, count 0 2006.173.08:50:44.94#ibcon#about to read 6, iclass 34, count 0 2006.173.08:50:44.94#ibcon#read 6, iclass 34, count 0 2006.173.08:50:44.94#ibcon#end of sib2, iclass 34, count 0 2006.173.08:50:44.94#ibcon#*after write, iclass 34, count 0 2006.173.08:50:44.94#ibcon#*before return 0, iclass 34, count 0 2006.173.08:50:44.94#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.08:50:44.94#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.08:50:44.94#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.08:50:44.94#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.08:50:44.94$vck44/va=6,3 2006.173.08:50:44.94#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.08:50:44.94#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.08:50:44.94#ibcon#ireg 11 cls_cnt 2 2006.173.08:50:44.94#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.08:50:45.00#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.08:50:45.00#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.08:50:45.00#ibcon#enter wrdev, iclass 36, count 2 2006.173.08:50:45.00#ibcon#first serial, iclass 36, count 2 2006.173.08:50:45.00#ibcon#enter sib2, iclass 36, count 2 2006.173.08:50:45.00#ibcon#flushed, iclass 36, count 2 2006.173.08:50:45.00#ibcon#about to write, iclass 36, count 2 2006.173.08:50:45.00#ibcon#wrote, iclass 36, count 2 2006.173.08:50:45.00#ibcon#about to read 3, iclass 36, count 2 2006.173.08:50:45.02#ibcon#read 3, iclass 36, count 2 2006.173.08:50:45.02#ibcon#about to read 4, iclass 36, count 2 2006.173.08:50:45.02#ibcon#read 4, iclass 36, count 2 2006.173.08:50:45.02#ibcon#about to read 5, iclass 36, count 2 2006.173.08:50:45.02#ibcon#read 5, iclass 36, count 2 2006.173.08:50:45.02#ibcon#about to read 6, iclass 36, count 2 2006.173.08:50:45.02#ibcon#read 6, iclass 36, count 2 2006.173.08:50:45.02#ibcon#end of sib2, iclass 36, count 2 2006.173.08:50:45.02#ibcon#*mode == 0, iclass 36, count 2 2006.173.08:50:45.02#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.08:50:45.02#ibcon#[25=AT06-03\r\n] 2006.173.08:50:45.02#ibcon#*before write, iclass 36, count 2 2006.173.08:50:45.02#ibcon#enter sib2, iclass 36, count 2 2006.173.08:50:45.02#ibcon#flushed, iclass 36, count 2 2006.173.08:50:45.02#ibcon#about to write, iclass 36, count 2 2006.173.08:50:45.02#ibcon#wrote, iclass 36, count 2 2006.173.08:50:45.02#ibcon#about to read 3, iclass 36, count 2 2006.173.08:50:45.05#ibcon#read 3, iclass 36, count 2 2006.173.08:50:45.05#ibcon#about to read 4, iclass 36, count 2 2006.173.08:50:45.05#ibcon#read 4, iclass 36, count 2 2006.173.08:50:45.05#ibcon#about to read 5, iclass 36, count 2 2006.173.08:50:45.05#ibcon#read 5, iclass 36, count 2 2006.173.08:50:45.05#ibcon#about to read 6, iclass 36, count 2 2006.173.08:50:45.05#ibcon#read 6, iclass 36, count 2 2006.173.08:50:45.05#ibcon#end of sib2, iclass 36, count 2 2006.173.08:50:45.05#ibcon#*after write, iclass 36, count 2 2006.173.08:50:45.05#ibcon#*before return 0, iclass 36, count 2 2006.173.08:50:45.05#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.08:50:45.05#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.08:50:45.05#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.08:50:45.05#ibcon#ireg 7 cls_cnt 0 2006.173.08:50:45.05#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.08:50:45.17#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.08:50:45.17#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.08:50:45.17#ibcon#enter wrdev, iclass 36, count 0 2006.173.08:50:45.17#ibcon#first serial, iclass 36, count 0 2006.173.08:50:45.17#ibcon#enter sib2, iclass 36, count 0 2006.173.08:50:45.17#ibcon#flushed, iclass 36, count 0 2006.173.08:50:45.17#ibcon#about to write, iclass 36, count 0 2006.173.08:50:45.17#ibcon#wrote, iclass 36, count 0 2006.173.08:50:45.17#ibcon#about to read 3, iclass 36, count 0 2006.173.08:50:45.19#ibcon#read 3, iclass 36, count 0 2006.173.08:50:45.19#ibcon#about to read 4, iclass 36, count 0 2006.173.08:50:45.19#ibcon#read 4, iclass 36, count 0 2006.173.08:50:45.19#ibcon#about to read 5, iclass 36, count 0 2006.173.08:50:45.19#ibcon#read 5, iclass 36, count 0 2006.173.08:50:45.19#ibcon#about to read 6, iclass 36, count 0 2006.173.08:50:45.19#ibcon#read 6, iclass 36, count 0 2006.173.08:50:45.19#ibcon#end of sib2, iclass 36, count 0 2006.173.08:50:45.19#ibcon#*mode == 0, iclass 36, count 0 2006.173.08:50:45.19#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.08:50:45.19#ibcon#[25=USB\r\n] 2006.173.08:50:45.19#ibcon#*before write, iclass 36, count 0 2006.173.08:50:45.19#ibcon#enter sib2, iclass 36, count 0 2006.173.08:50:45.19#ibcon#flushed, iclass 36, count 0 2006.173.08:50:45.19#ibcon#about to write, iclass 36, count 0 2006.173.08:50:45.19#ibcon#wrote, iclass 36, count 0 2006.173.08:50:45.19#ibcon#about to read 3, iclass 36, count 0 2006.173.08:50:45.22#ibcon#read 3, iclass 36, count 0 2006.173.08:50:45.22#ibcon#about to read 4, iclass 36, count 0 2006.173.08:50:45.22#ibcon#read 4, iclass 36, count 0 2006.173.08:50:45.22#ibcon#about to read 5, iclass 36, count 0 2006.173.08:50:45.22#ibcon#read 5, iclass 36, count 0 2006.173.08:50:45.22#ibcon#about to read 6, iclass 36, count 0 2006.173.08:50:45.22#ibcon#read 6, iclass 36, count 0 2006.173.08:50:45.22#ibcon#end of sib2, iclass 36, count 0 2006.173.08:50:45.22#ibcon#*after write, iclass 36, count 0 2006.173.08:50:45.22#ibcon#*before return 0, iclass 36, count 0 2006.173.08:50:45.22#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.08:50:45.22#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.08:50:45.22#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.08:50:45.22#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.08:50:45.22$vck44/valo=7,864.99 2006.173.08:50:45.22#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.08:50:45.22#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.08:50:45.22#ibcon#ireg 17 cls_cnt 0 2006.173.08:50:45.22#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.08:50:45.22#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.08:50:45.22#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.08:50:45.22#ibcon#enter wrdev, iclass 38, count 0 2006.173.08:50:45.22#ibcon#first serial, iclass 38, count 0 2006.173.08:50:45.22#ibcon#enter sib2, iclass 38, count 0 2006.173.08:50:45.22#ibcon#flushed, iclass 38, count 0 2006.173.08:50:45.22#ibcon#about to write, iclass 38, count 0 2006.173.08:50:45.22#ibcon#wrote, iclass 38, count 0 2006.173.08:50:45.22#ibcon#about to read 3, iclass 38, count 0 2006.173.08:50:45.24#ibcon#read 3, iclass 38, count 0 2006.173.08:50:45.24#ibcon#about to read 4, iclass 38, count 0 2006.173.08:50:45.24#ibcon#read 4, iclass 38, count 0 2006.173.08:50:45.24#ibcon#about to read 5, iclass 38, count 0 2006.173.08:50:45.24#ibcon#read 5, iclass 38, count 0 2006.173.08:50:45.24#ibcon#about to read 6, iclass 38, count 0 2006.173.08:50:45.24#ibcon#read 6, iclass 38, count 0 2006.173.08:50:45.24#ibcon#end of sib2, iclass 38, count 0 2006.173.08:50:45.24#ibcon#*mode == 0, iclass 38, count 0 2006.173.08:50:45.24#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.08:50:45.24#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.08:50:45.24#ibcon#*before write, iclass 38, count 0 2006.173.08:50:45.24#ibcon#enter sib2, iclass 38, count 0 2006.173.08:50:45.24#ibcon#flushed, iclass 38, count 0 2006.173.08:50:45.24#ibcon#about to write, iclass 38, count 0 2006.173.08:50:45.24#ibcon#wrote, iclass 38, count 0 2006.173.08:50:45.24#ibcon#about to read 3, iclass 38, count 0 2006.173.08:50:45.28#ibcon#read 3, iclass 38, count 0 2006.173.08:50:45.28#ibcon#about to read 4, iclass 38, count 0 2006.173.08:50:45.28#ibcon#read 4, iclass 38, count 0 2006.173.08:50:45.28#ibcon#about to read 5, iclass 38, count 0 2006.173.08:50:45.28#ibcon#read 5, iclass 38, count 0 2006.173.08:50:45.28#ibcon#about to read 6, iclass 38, count 0 2006.173.08:50:45.28#ibcon#read 6, iclass 38, count 0 2006.173.08:50:45.28#ibcon#end of sib2, iclass 38, count 0 2006.173.08:50:45.28#ibcon#*after write, iclass 38, count 0 2006.173.08:50:45.28#ibcon#*before return 0, iclass 38, count 0 2006.173.08:50:45.28#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.08:50:45.28#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.08:50:45.28#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.08:50:45.28#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.08:50:45.28$vck44/va=7,4 2006.173.08:50:45.28#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.08:50:45.28#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.08:50:45.28#ibcon#ireg 11 cls_cnt 2 2006.173.08:50:45.28#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.08:50:45.34#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.08:50:45.34#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.08:50:45.34#ibcon#enter wrdev, iclass 40, count 2 2006.173.08:50:45.34#ibcon#first serial, iclass 40, count 2 2006.173.08:50:45.34#ibcon#enter sib2, iclass 40, count 2 2006.173.08:50:45.34#ibcon#flushed, iclass 40, count 2 2006.173.08:50:45.34#ibcon#about to write, iclass 40, count 2 2006.173.08:50:45.34#ibcon#wrote, iclass 40, count 2 2006.173.08:50:45.34#ibcon#about to read 3, iclass 40, count 2 2006.173.08:50:45.36#ibcon#read 3, iclass 40, count 2 2006.173.08:50:45.36#ibcon#about to read 4, iclass 40, count 2 2006.173.08:50:45.36#ibcon#read 4, iclass 40, count 2 2006.173.08:50:45.36#ibcon#about to read 5, iclass 40, count 2 2006.173.08:50:45.36#ibcon#read 5, iclass 40, count 2 2006.173.08:50:45.36#ibcon#about to read 6, iclass 40, count 2 2006.173.08:50:45.36#ibcon#read 6, iclass 40, count 2 2006.173.08:50:45.36#ibcon#end of sib2, iclass 40, count 2 2006.173.08:50:45.36#ibcon#*mode == 0, iclass 40, count 2 2006.173.08:50:45.36#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.08:50:45.36#ibcon#[25=AT07-04\r\n] 2006.173.08:50:45.36#ibcon#*before write, iclass 40, count 2 2006.173.08:50:45.36#ibcon#enter sib2, iclass 40, count 2 2006.173.08:50:45.36#ibcon#flushed, iclass 40, count 2 2006.173.08:50:45.36#ibcon#about to write, iclass 40, count 2 2006.173.08:50:45.36#ibcon#wrote, iclass 40, count 2 2006.173.08:50:45.36#ibcon#about to read 3, iclass 40, count 2 2006.173.08:50:45.39#ibcon#read 3, iclass 40, count 2 2006.173.08:50:45.39#ibcon#about to read 4, iclass 40, count 2 2006.173.08:50:45.39#ibcon#read 4, iclass 40, count 2 2006.173.08:50:45.39#ibcon#about to read 5, iclass 40, count 2 2006.173.08:50:45.39#ibcon#read 5, iclass 40, count 2 2006.173.08:50:45.39#ibcon#about to read 6, iclass 40, count 2 2006.173.08:50:45.39#ibcon#read 6, iclass 40, count 2 2006.173.08:50:45.39#ibcon#end of sib2, iclass 40, count 2 2006.173.08:50:45.39#ibcon#*after write, iclass 40, count 2 2006.173.08:50:45.39#ibcon#*before return 0, iclass 40, count 2 2006.173.08:50:45.39#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.08:50:45.39#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.08:50:45.39#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.08:50:45.39#ibcon#ireg 7 cls_cnt 0 2006.173.08:50:45.39#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.08:50:45.51#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.08:50:45.51#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.08:50:45.51#ibcon#enter wrdev, iclass 40, count 0 2006.173.08:50:45.51#ibcon#first serial, iclass 40, count 0 2006.173.08:50:45.51#ibcon#enter sib2, iclass 40, count 0 2006.173.08:50:45.51#ibcon#flushed, iclass 40, count 0 2006.173.08:50:45.51#ibcon#about to write, iclass 40, count 0 2006.173.08:50:45.51#ibcon#wrote, iclass 40, count 0 2006.173.08:50:45.51#ibcon#about to read 3, iclass 40, count 0 2006.173.08:50:45.53#ibcon#read 3, iclass 40, count 0 2006.173.08:50:45.53#ibcon#about to read 4, iclass 40, count 0 2006.173.08:50:45.53#ibcon#read 4, iclass 40, count 0 2006.173.08:50:45.53#ibcon#about to read 5, iclass 40, count 0 2006.173.08:50:45.53#ibcon#read 5, iclass 40, count 0 2006.173.08:50:45.53#ibcon#about to read 6, iclass 40, count 0 2006.173.08:50:45.53#ibcon#read 6, iclass 40, count 0 2006.173.08:50:45.53#ibcon#end of sib2, iclass 40, count 0 2006.173.08:50:45.53#ibcon#*mode == 0, iclass 40, count 0 2006.173.08:50:45.53#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.08:50:45.53#ibcon#[25=USB\r\n] 2006.173.08:50:45.53#ibcon#*before write, iclass 40, count 0 2006.173.08:50:45.53#ibcon#enter sib2, iclass 40, count 0 2006.173.08:50:45.53#ibcon#flushed, iclass 40, count 0 2006.173.08:50:45.53#ibcon#about to write, iclass 40, count 0 2006.173.08:50:45.53#ibcon#wrote, iclass 40, count 0 2006.173.08:50:45.53#ibcon#about to read 3, iclass 40, count 0 2006.173.08:50:45.56#ibcon#read 3, iclass 40, count 0 2006.173.08:50:45.56#ibcon#about to read 4, iclass 40, count 0 2006.173.08:50:45.56#ibcon#read 4, iclass 40, count 0 2006.173.08:50:45.56#ibcon#about to read 5, iclass 40, count 0 2006.173.08:50:45.56#ibcon#read 5, iclass 40, count 0 2006.173.08:50:45.56#ibcon#about to read 6, iclass 40, count 0 2006.173.08:50:45.56#ibcon#read 6, iclass 40, count 0 2006.173.08:50:45.56#ibcon#end of sib2, iclass 40, count 0 2006.173.08:50:45.56#ibcon#*after write, iclass 40, count 0 2006.173.08:50:45.56#ibcon#*before return 0, iclass 40, count 0 2006.173.08:50:45.56#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.08:50:45.56#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.08:50:45.56#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.08:50:45.56#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.08:50:45.56$vck44/valo=8,884.99 2006.173.08:50:45.56#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.08:50:45.56#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.08:50:45.56#ibcon#ireg 17 cls_cnt 0 2006.173.08:50:45.56#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.08:50:45.56#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.08:50:45.56#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.08:50:45.56#ibcon#enter wrdev, iclass 4, count 0 2006.173.08:50:45.56#ibcon#first serial, iclass 4, count 0 2006.173.08:50:45.56#ibcon#enter sib2, iclass 4, count 0 2006.173.08:50:45.56#ibcon#flushed, iclass 4, count 0 2006.173.08:50:45.56#ibcon#about to write, iclass 4, count 0 2006.173.08:50:45.56#ibcon#wrote, iclass 4, count 0 2006.173.08:50:45.56#ibcon#about to read 3, iclass 4, count 0 2006.173.08:50:45.58#ibcon#read 3, iclass 4, count 0 2006.173.08:50:45.58#ibcon#about to read 4, iclass 4, count 0 2006.173.08:50:45.58#ibcon#read 4, iclass 4, count 0 2006.173.08:50:45.58#ibcon#about to read 5, iclass 4, count 0 2006.173.08:50:45.58#ibcon#read 5, iclass 4, count 0 2006.173.08:50:45.58#ibcon#about to read 6, iclass 4, count 0 2006.173.08:50:45.58#ibcon#read 6, iclass 4, count 0 2006.173.08:50:45.58#ibcon#end of sib2, iclass 4, count 0 2006.173.08:50:45.58#ibcon#*mode == 0, iclass 4, count 0 2006.173.08:50:45.58#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.08:50:45.58#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.08:50:45.58#ibcon#*before write, iclass 4, count 0 2006.173.08:50:45.58#ibcon#enter sib2, iclass 4, count 0 2006.173.08:50:45.58#ibcon#flushed, iclass 4, count 0 2006.173.08:50:45.58#ibcon#about to write, iclass 4, count 0 2006.173.08:50:45.58#ibcon#wrote, iclass 4, count 0 2006.173.08:50:45.58#ibcon#about to read 3, iclass 4, count 0 2006.173.08:50:45.62#ibcon#read 3, iclass 4, count 0 2006.173.08:50:45.62#ibcon#about to read 4, iclass 4, count 0 2006.173.08:50:45.62#ibcon#read 4, iclass 4, count 0 2006.173.08:50:45.62#ibcon#about to read 5, iclass 4, count 0 2006.173.08:50:45.62#ibcon#read 5, iclass 4, count 0 2006.173.08:50:45.62#ibcon#about to read 6, iclass 4, count 0 2006.173.08:50:45.62#ibcon#read 6, iclass 4, count 0 2006.173.08:50:45.62#ibcon#end of sib2, iclass 4, count 0 2006.173.08:50:45.62#ibcon#*after write, iclass 4, count 0 2006.173.08:50:45.62#ibcon#*before return 0, iclass 4, count 0 2006.173.08:50:45.62#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.08:50:45.62#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.08:50:45.62#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.08:50:45.62#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.08:50:45.62$vck44/va=8,4 2006.173.08:50:45.62#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.08:50:45.62#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.08:50:45.62#ibcon#ireg 11 cls_cnt 2 2006.173.08:50:45.62#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.08:50:45.68#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.08:50:45.68#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.08:50:45.68#ibcon#enter wrdev, iclass 6, count 2 2006.173.08:50:45.68#ibcon#first serial, iclass 6, count 2 2006.173.08:50:45.68#ibcon#enter sib2, iclass 6, count 2 2006.173.08:50:45.68#ibcon#flushed, iclass 6, count 2 2006.173.08:50:45.68#ibcon#about to write, iclass 6, count 2 2006.173.08:50:45.68#ibcon#wrote, iclass 6, count 2 2006.173.08:50:45.68#ibcon#about to read 3, iclass 6, count 2 2006.173.08:50:45.70#ibcon#read 3, iclass 6, count 2 2006.173.08:50:45.70#ibcon#about to read 4, iclass 6, count 2 2006.173.08:50:45.70#ibcon#read 4, iclass 6, count 2 2006.173.08:50:45.70#ibcon#about to read 5, iclass 6, count 2 2006.173.08:50:45.70#ibcon#read 5, iclass 6, count 2 2006.173.08:50:45.70#ibcon#about to read 6, iclass 6, count 2 2006.173.08:50:45.70#ibcon#read 6, iclass 6, count 2 2006.173.08:50:45.70#ibcon#end of sib2, iclass 6, count 2 2006.173.08:50:45.70#ibcon#*mode == 0, iclass 6, count 2 2006.173.08:50:45.70#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.08:50:45.70#ibcon#[25=AT08-04\r\n] 2006.173.08:50:45.70#ibcon#*before write, iclass 6, count 2 2006.173.08:50:45.70#ibcon#enter sib2, iclass 6, count 2 2006.173.08:50:45.70#ibcon#flushed, iclass 6, count 2 2006.173.08:50:45.70#ibcon#about to write, iclass 6, count 2 2006.173.08:50:45.70#ibcon#wrote, iclass 6, count 2 2006.173.08:50:45.70#ibcon#about to read 3, iclass 6, count 2 2006.173.08:50:45.73#ibcon#read 3, iclass 6, count 2 2006.173.08:50:45.73#ibcon#about to read 4, iclass 6, count 2 2006.173.08:50:45.73#ibcon#read 4, iclass 6, count 2 2006.173.08:50:45.73#ibcon#about to read 5, iclass 6, count 2 2006.173.08:50:45.73#ibcon#read 5, iclass 6, count 2 2006.173.08:50:45.73#ibcon#about to read 6, iclass 6, count 2 2006.173.08:50:45.73#ibcon#read 6, iclass 6, count 2 2006.173.08:50:45.73#ibcon#end of sib2, iclass 6, count 2 2006.173.08:50:45.73#ibcon#*after write, iclass 6, count 2 2006.173.08:50:45.73#ibcon#*before return 0, iclass 6, count 2 2006.173.08:50:45.73#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.08:50:45.73#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.08:50:45.73#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.08:50:45.73#ibcon#ireg 7 cls_cnt 0 2006.173.08:50:45.73#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.08:50:45.85#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.08:50:45.85#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.08:50:45.85#ibcon#enter wrdev, iclass 6, count 0 2006.173.08:50:45.85#ibcon#first serial, iclass 6, count 0 2006.173.08:50:45.85#ibcon#enter sib2, iclass 6, count 0 2006.173.08:50:45.85#ibcon#flushed, iclass 6, count 0 2006.173.08:50:45.85#ibcon#about to write, iclass 6, count 0 2006.173.08:50:45.85#ibcon#wrote, iclass 6, count 0 2006.173.08:50:45.85#ibcon#about to read 3, iclass 6, count 0 2006.173.08:50:45.87#ibcon#read 3, iclass 6, count 0 2006.173.08:50:45.87#ibcon#about to read 4, iclass 6, count 0 2006.173.08:50:45.87#ibcon#read 4, iclass 6, count 0 2006.173.08:50:45.87#ibcon#about to read 5, iclass 6, count 0 2006.173.08:50:45.87#ibcon#read 5, iclass 6, count 0 2006.173.08:50:45.87#ibcon#about to read 6, iclass 6, count 0 2006.173.08:50:45.87#ibcon#read 6, iclass 6, count 0 2006.173.08:50:45.87#ibcon#end of sib2, iclass 6, count 0 2006.173.08:50:45.87#ibcon#*mode == 0, iclass 6, count 0 2006.173.08:50:45.87#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.08:50:45.87#ibcon#[25=USB\r\n] 2006.173.08:50:45.87#ibcon#*before write, iclass 6, count 0 2006.173.08:50:45.87#ibcon#enter sib2, iclass 6, count 0 2006.173.08:50:45.87#ibcon#flushed, iclass 6, count 0 2006.173.08:50:45.87#ibcon#about to write, iclass 6, count 0 2006.173.08:50:45.87#ibcon#wrote, iclass 6, count 0 2006.173.08:50:45.87#ibcon#about to read 3, iclass 6, count 0 2006.173.08:50:45.90#ibcon#read 3, iclass 6, count 0 2006.173.08:50:45.90#ibcon#about to read 4, iclass 6, count 0 2006.173.08:50:45.90#ibcon#read 4, iclass 6, count 0 2006.173.08:50:45.90#ibcon#about to read 5, iclass 6, count 0 2006.173.08:50:45.90#ibcon#read 5, iclass 6, count 0 2006.173.08:50:45.90#ibcon#about to read 6, iclass 6, count 0 2006.173.08:50:45.90#ibcon#read 6, iclass 6, count 0 2006.173.08:50:45.90#ibcon#end of sib2, iclass 6, count 0 2006.173.08:50:45.90#ibcon#*after write, iclass 6, count 0 2006.173.08:50:45.90#ibcon#*before return 0, iclass 6, count 0 2006.173.08:50:45.90#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.08:50:45.90#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.08:50:45.90#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.08:50:45.90#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.08:50:45.90$vck44/vblo=1,629.99 2006.173.08:50:45.90#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.08:50:45.90#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.08:50:45.90#ibcon#ireg 17 cls_cnt 0 2006.173.08:50:45.90#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.08:50:45.90#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.08:50:45.90#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.08:50:45.90#ibcon#enter wrdev, iclass 10, count 0 2006.173.08:50:45.90#ibcon#first serial, iclass 10, count 0 2006.173.08:50:45.90#ibcon#enter sib2, iclass 10, count 0 2006.173.08:50:45.90#ibcon#flushed, iclass 10, count 0 2006.173.08:50:45.90#ibcon#about to write, iclass 10, count 0 2006.173.08:50:45.90#ibcon#wrote, iclass 10, count 0 2006.173.08:50:45.90#ibcon#about to read 3, iclass 10, count 0 2006.173.08:50:45.92#ibcon#read 3, iclass 10, count 0 2006.173.08:50:45.92#ibcon#about to read 4, iclass 10, count 0 2006.173.08:50:45.92#ibcon#read 4, iclass 10, count 0 2006.173.08:50:45.92#ibcon#about to read 5, iclass 10, count 0 2006.173.08:50:45.92#ibcon#read 5, iclass 10, count 0 2006.173.08:50:45.92#ibcon#about to read 6, iclass 10, count 0 2006.173.08:50:45.92#ibcon#read 6, iclass 10, count 0 2006.173.08:50:45.92#ibcon#end of sib2, iclass 10, count 0 2006.173.08:50:45.92#ibcon#*mode == 0, iclass 10, count 0 2006.173.08:50:45.92#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.08:50:45.92#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.08:50:45.92#ibcon#*before write, iclass 10, count 0 2006.173.08:50:45.92#ibcon#enter sib2, iclass 10, count 0 2006.173.08:50:45.92#ibcon#flushed, iclass 10, count 0 2006.173.08:50:45.92#ibcon#about to write, iclass 10, count 0 2006.173.08:50:45.92#ibcon#wrote, iclass 10, count 0 2006.173.08:50:45.92#ibcon#about to read 3, iclass 10, count 0 2006.173.08:50:45.96#ibcon#read 3, iclass 10, count 0 2006.173.08:50:45.96#ibcon#about to read 4, iclass 10, count 0 2006.173.08:50:45.96#ibcon#read 4, iclass 10, count 0 2006.173.08:50:45.96#ibcon#about to read 5, iclass 10, count 0 2006.173.08:50:45.96#ibcon#read 5, iclass 10, count 0 2006.173.08:50:45.96#ibcon#about to read 6, iclass 10, count 0 2006.173.08:50:45.96#ibcon#read 6, iclass 10, count 0 2006.173.08:50:45.96#ibcon#end of sib2, iclass 10, count 0 2006.173.08:50:45.96#ibcon#*after write, iclass 10, count 0 2006.173.08:50:45.96#ibcon#*before return 0, iclass 10, count 0 2006.173.08:50:45.96#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.08:50:45.96#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.08:50:45.96#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.08:50:45.96#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.08:50:45.96$vck44/vb=1,4 2006.173.08:50:45.96#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.08:50:45.96#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.08:50:45.96#ibcon#ireg 11 cls_cnt 2 2006.173.08:50:45.96#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.08:50:45.96#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.08:50:45.96#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.08:50:45.96#ibcon#enter wrdev, iclass 12, count 2 2006.173.08:50:45.96#ibcon#first serial, iclass 12, count 2 2006.173.08:50:45.96#ibcon#enter sib2, iclass 12, count 2 2006.173.08:50:45.96#ibcon#flushed, iclass 12, count 2 2006.173.08:50:45.96#ibcon#about to write, iclass 12, count 2 2006.173.08:50:45.96#ibcon#wrote, iclass 12, count 2 2006.173.08:50:45.96#ibcon#about to read 3, iclass 12, count 2 2006.173.08:50:45.98#ibcon#read 3, iclass 12, count 2 2006.173.08:50:45.98#ibcon#about to read 4, iclass 12, count 2 2006.173.08:50:45.98#ibcon#read 4, iclass 12, count 2 2006.173.08:50:45.98#ibcon#about to read 5, iclass 12, count 2 2006.173.08:50:45.98#ibcon#read 5, iclass 12, count 2 2006.173.08:50:45.98#ibcon#about to read 6, iclass 12, count 2 2006.173.08:50:45.98#ibcon#read 6, iclass 12, count 2 2006.173.08:50:45.98#ibcon#end of sib2, iclass 12, count 2 2006.173.08:50:45.98#ibcon#*mode == 0, iclass 12, count 2 2006.173.08:50:45.98#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.08:50:45.98#ibcon#[27=AT01-04\r\n] 2006.173.08:50:45.98#ibcon#*before write, iclass 12, count 2 2006.173.08:50:45.98#ibcon#enter sib2, iclass 12, count 2 2006.173.08:50:45.98#ibcon#flushed, iclass 12, count 2 2006.173.08:50:45.98#ibcon#about to write, iclass 12, count 2 2006.173.08:50:45.98#ibcon#wrote, iclass 12, count 2 2006.173.08:50:45.98#ibcon#about to read 3, iclass 12, count 2 2006.173.08:50:46.01#ibcon#read 3, iclass 12, count 2 2006.173.08:50:46.01#ibcon#about to read 4, iclass 12, count 2 2006.173.08:50:46.01#ibcon#read 4, iclass 12, count 2 2006.173.08:50:46.01#ibcon#about to read 5, iclass 12, count 2 2006.173.08:50:46.01#ibcon#read 5, iclass 12, count 2 2006.173.08:50:46.01#ibcon#about to read 6, iclass 12, count 2 2006.173.08:50:46.01#ibcon#read 6, iclass 12, count 2 2006.173.08:50:46.01#ibcon#end of sib2, iclass 12, count 2 2006.173.08:50:46.01#ibcon#*after write, iclass 12, count 2 2006.173.08:50:46.01#ibcon#*before return 0, iclass 12, count 2 2006.173.08:50:46.01#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.08:50:46.01#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.08:50:46.01#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.08:50:46.01#ibcon#ireg 7 cls_cnt 0 2006.173.08:50:46.01#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.08:50:46.13#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.08:50:46.13#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.08:50:46.13#ibcon#enter wrdev, iclass 12, count 0 2006.173.08:50:46.13#ibcon#first serial, iclass 12, count 0 2006.173.08:50:46.13#ibcon#enter sib2, iclass 12, count 0 2006.173.08:50:46.13#ibcon#flushed, iclass 12, count 0 2006.173.08:50:46.13#ibcon#about to write, iclass 12, count 0 2006.173.08:50:46.13#ibcon#wrote, iclass 12, count 0 2006.173.08:50:46.13#ibcon#about to read 3, iclass 12, count 0 2006.173.08:50:46.15#ibcon#read 3, iclass 12, count 0 2006.173.08:50:46.15#ibcon#about to read 4, iclass 12, count 0 2006.173.08:50:46.15#ibcon#read 4, iclass 12, count 0 2006.173.08:50:46.15#ibcon#about to read 5, iclass 12, count 0 2006.173.08:50:46.15#ibcon#read 5, iclass 12, count 0 2006.173.08:50:46.15#ibcon#about to read 6, iclass 12, count 0 2006.173.08:50:46.15#ibcon#read 6, iclass 12, count 0 2006.173.08:50:46.15#ibcon#end of sib2, iclass 12, count 0 2006.173.08:50:46.15#ibcon#*mode == 0, iclass 12, count 0 2006.173.08:50:46.15#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.08:50:46.15#ibcon#[27=USB\r\n] 2006.173.08:50:46.15#ibcon#*before write, iclass 12, count 0 2006.173.08:50:46.15#ibcon#enter sib2, iclass 12, count 0 2006.173.08:50:46.15#ibcon#flushed, iclass 12, count 0 2006.173.08:50:46.15#ibcon#about to write, iclass 12, count 0 2006.173.08:50:46.15#ibcon#wrote, iclass 12, count 0 2006.173.08:50:46.15#ibcon#about to read 3, iclass 12, count 0 2006.173.08:50:46.18#ibcon#read 3, iclass 12, count 0 2006.173.08:50:46.18#ibcon#about to read 4, iclass 12, count 0 2006.173.08:50:46.18#ibcon#read 4, iclass 12, count 0 2006.173.08:50:46.18#ibcon#about to read 5, iclass 12, count 0 2006.173.08:50:46.18#ibcon#read 5, iclass 12, count 0 2006.173.08:50:46.18#ibcon#about to read 6, iclass 12, count 0 2006.173.08:50:46.18#ibcon#read 6, iclass 12, count 0 2006.173.08:50:46.18#ibcon#end of sib2, iclass 12, count 0 2006.173.08:50:46.18#ibcon#*after write, iclass 12, count 0 2006.173.08:50:46.18#ibcon#*before return 0, iclass 12, count 0 2006.173.08:50:46.18#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.08:50:46.18#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.08:50:46.18#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.08:50:46.18#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.08:50:46.18$vck44/vblo=2,634.99 2006.173.08:50:46.18#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.08:50:46.18#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.08:50:46.18#ibcon#ireg 17 cls_cnt 0 2006.173.08:50:46.18#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.08:50:46.18#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.08:50:46.18#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.08:50:46.18#ibcon#enter wrdev, iclass 14, count 0 2006.173.08:50:46.18#ibcon#first serial, iclass 14, count 0 2006.173.08:50:46.18#ibcon#enter sib2, iclass 14, count 0 2006.173.08:50:46.18#ibcon#flushed, iclass 14, count 0 2006.173.08:50:46.18#ibcon#about to write, iclass 14, count 0 2006.173.08:50:46.18#ibcon#wrote, iclass 14, count 0 2006.173.08:50:46.18#ibcon#about to read 3, iclass 14, count 0 2006.173.08:50:46.20#ibcon#read 3, iclass 14, count 0 2006.173.08:50:46.20#ibcon#about to read 4, iclass 14, count 0 2006.173.08:50:46.20#ibcon#read 4, iclass 14, count 0 2006.173.08:50:46.20#ibcon#about to read 5, iclass 14, count 0 2006.173.08:50:46.20#ibcon#read 5, iclass 14, count 0 2006.173.08:50:46.20#ibcon#about to read 6, iclass 14, count 0 2006.173.08:50:46.20#ibcon#read 6, iclass 14, count 0 2006.173.08:50:46.20#ibcon#end of sib2, iclass 14, count 0 2006.173.08:50:46.20#ibcon#*mode == 0, iclass 14, count 0 2006.173.08:50:46.20#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.08:50:46.20#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.08:50:46.20#ibcon#*before write, iclass 14, count 0 2006.173.08:50:46.20#ibcon#enter sib2, iclass 14, count 0 2006.173.08:50:46.20#ibcon#flushed, iclass 14, count 0 2006.173.08:50:46.20#ibcon#about to write, iclass 14, count 0 2006.173.08:50:46.20#ibcon#wrote, iclass 14, count 0 2006.173.08:50:46.20#ibcon#about to read 3, iclass 14, count 0 2006.173.08:50:46.24#ibcon#read 3, iclass 14, count 0 2006.173.08:50:46.24#ibcon#about to read 4, iclass 14, count 0 2006.173.08:50:46.24#ibcon#read 4, iclass 14, count 0 2006.173.08:50:46.24#ibcon#about to read 5, iclass 14, count 0 2006.173.08:50:46.24#ibcon#read 5, iclass 14, count 0 2006.173.08:50:46.24#ibcon#about to read 6, iclass 14, count 0 2006.173.08:50:46.24#ibcon#read 6, iclass 14, count 0 2006.173.08:50:46.24#ibcon#end of sib2, iclass 14, count 0 2006.173.08:50:46.24#ibcon#*after write, iclass 14, count 0 2006.173.08:50:46.24#ibcon#*before return 0, iclass 14, count 0 2006.173.08:50:46.24#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.08:50:46.24#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.08:50:46.24#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.08:50:46.24#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.08:50:46.24$vck44/vb=2,4 2006.173.08:50:46.24#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.08:50:46.24#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.08:50:46.24#ibcon#ireg 11 cls_cnt 2 2006.173.08:50:46.24#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.08:50:46.30#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.08:50:46.30#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.08:50:46.30#ibcon#enter wrdev, iclass 16, count 2 2006.173.08:50:46.30#ibcon#first serial, iclass 16, count 2 2006.173.08:50:46.30#ibcon#enter sib2, iclass 16, count 2 2006.173.08:50:46.30#ibcon#flushed, iclass 16, count 2 2006.173.08:50:46.30#ibcon#about to write, iclass 16, count 2 2006.173.08:50:46.30#ibcon#wrote, iclass 16, count 2 2006.173.08:50:46.30#ibcon#about to read 3, iclass 16, count 2 2006.173.08:50:46.32#ibcon#read 3, iclass 16, count 2 2006.173.08:50:46.32#ibcon#about to read 4, iclass 16, count 2 2006.173.08:50:46.32#ibcon#read 4, iclass 16, count 2 2006.173.08:50:46.32#ibcon#about to read 5, iclass 16, count 2 2006.173.08:50:46.32#ibcon#read 5, iclass 16, count 2 2006.173.08:50:46.32#ibcon#about to read 6, iclass 16, count 2 2006.173.08:50:46.32#ibcon#read 6, iclass 16, count 2 2006.173.08:50:46.32#ibcon#end of sib2, iclass 16, count 2 2006.173.08:50:46.32#ibcon#*mode == 0, iclass 16, count 2 2006.173.08:50:46.32#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.08:50:46.32#ibcon#[27=AT02-04\r\n] 2006.173.08:50:46.32#ibcon#*before write, iclass 16, count 2 2006.173.08:50:46.32#ibcon#enter sib2, iclass 16, count 2 2006.173.08:50:46.32#ibcon#flushed, iclass 16, count 2 2006.173.08:50:46.32#ibcon#about to write, iclass 16, count 2 2006.173.08:50:46.32#ibcon#wrote, iclass 16, count 2 2006.173.08:50:46.32#ibcon#about to read 3, iclass 16, count 2 2006.173.08:50:46.35#ibcon#read 3, iclass 16, count 2 2006.173.08:50:46.35#ibcon#about to read 4, iclass 16, count 2 2006.173.08:50:46.35#ibcon#read 4, iclass 16, count 2 2006.173.08:50:46.35#ibcon#about to read 5, iclass 16, count 2 2006.173.08:50:46.35#ibcon#read 5, iclass 16, count 2 2006.173.08:50:46.35#ibcon#about to read 6, iclass 16, count 2 2006.173.08:50:46.35#ibcon#read 6, iclass 16, count 2 2006.173.08:50:46.35#ibcon#end of sib2, iclass 16, count 2 2006.173.08:50:46.35#ibcon#*after write, iclass 16, count 2 2006.173.08:50:46.35#ibcon#*before return 0, iclass 16, count 2 2006.173.08:50:46.35#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.08:50:46.35#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.08:50:46.35#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.08:50:46.35#ibcon#ireg 7 cls_cnt 0 2006.173.08:50:46.35#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.08:50:46.47#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.08:50:46.47#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.08:50:46.47#ibcon#enter wrdev, iclass 16, count 0 2006.173.08:50:46.47#ibcon#first serial, iclass 16, count 0 2006.173.08:50:46.47#ibcon#enter sib2, iclass 16, count 0 2006.173.08:50:46.47#ibcon#flushed, iclass 16, count 0 2006.173.08:50:46.47#ibcon#about to write, iclass 16, count 0 2006.173.08:50:46.47#ibcon#wrote, iclass 16, count 0 2006.173.08:50:46.47#ibcon#about to read 3, iclass 16, count 0 2006.173.08:50:46.49#ibcon#read 3, iclass 16, count 0 2006.173.08:50:46.49#ibcon#about to read 4, iclass 16, count 0 2006.173.08:50:46.49#ibcon#read 4, iclass 16, count 0 2006.173.08:50:46.49#ibcon#about to read 5, iclass 16, count 0 2006.173.08:50:46.49#ibcon#read 5, iclass 16, count 0 2006.173.08:50:46.49#ibcon#about to read 6, iclass 16, count 0 2006.173.08:50:46.49#ibcon#read 6, iclass 16, count 0 2006.173.08:50:46.49#ibcon#end of sib2, iclass 16, count 0 2006.173.08:50:46.49#ibcon#*mode == 0, iclass 16, count 0 2006.173.08:50:46.49#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.08:50:46.49#ibcon#[27=USB\r\n] 2006.173.08:50:46.49#ibcon#*before write, iclass 16, count 0 2006.173.08:50:46.49#ibcon#enter sib2, iclass 16, count 0 2006.173.08:50:46.49#ibcon#flushed, iclass 16, count 0 2006.173.08:50:46.49#ibcon#about to write, iclass 16, count 0 2006.173.08:50:46.49#ibcon#wrote, iclass 16, count 0 2006.173.08:50:46.49#ibcon#about to read 3, iclass 16, count 0 2006.173.08:50:46.52#ibcon#read 3, iclass 16, count 0 2006.173.08:50:46.52#ibcon#about to read 4, iclass 16, count 0 2006.173.08:50:46.52#ibcon#read 4, iclass 16, count 0 2006.173.08:50:46.52#ibcon#about to read 5, iclass 16, count 0 2006.173.08:50:46.52#ibcon#read 5, iclass 16, count 0 2006.173.08:50:46.52#ibcon#about to read 6, iclass 16, count 0 2006.173.08:50:46.52#ibcon#read 6, iclass 16, count 0 2006.173.08:50:46.52#ibcon#end of sib2, iclass 16, count 0 2006.173.08:50:46.52#ibcon#*after write, iclass 16, count 0 2006.173.08:50:46.52#ibcon#*before return 0, iclass 16, count 0 2006.173.08:50:46.52#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.08:50:46.52#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.08:50:46.52#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.08:50:46.52#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.08:50:46.52$vck44/vblo=3,649.99 2006.173.08:50:46.52#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.08:50:46.52#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.08:50:46.52#ibcon#ireg 17 cls_cnt 0 2006.173.08:50:46.52#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.08:50:46.52#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.08:50:46.52#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.08:50:46.52#ibcon#enter wrdev, iclass 18, count 0 2006.173.08:50:46.52#ibcon#first serial, iclass 18, count 0 2006.173.08:50:46.52#ibcon#enter sib2, iclass 18, count 0 2006.173.08:50:46.52#ibcon#flushed, iclass 18, count 0 2006.173.08:50:46.52#ibcon#about to write, iclass 18, count 0 2006.173.08:50:46.52#ibcon#wrote, iclass 18, count 0 2006.173.08:50:46.52#ibcon#about to read 3, iclass 18, count 0 2006.173.08:50:46.54#ibcon#read 3, iclass 18, count 0 2006.173.08:50:46.54#ibcon#about to read 4, iclass 18, count 0 2006.173.08:50:46.54#ibcon#read 4, iclass 18, count 0 2006.173.08:50:46.54#ibcon#about to read 5, iclass 18, count 0 2006.173.08:50:46.54#ibcon#read 5, iclass 18, count 0 2006.173.08:50:46.54#ibcon#about to read 6, iclass 18, count 0 2006.173.08:50:46.54#ibcon#read 6, iclass 18, count 0 2006.173.08:50:46.54#ibcon#end of sib2, iclass 18, count 0 2006.173.08:50:46.54#ibcon#*mode == 0, iclass 18, count 0 2006.173.08:50:46.54#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.08:50:46.54#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.08:50:46.54#ibcon#*before write, iclass 18, count 0 2006.173.08:50:46.54#ibcon#enter sib2, iclass 18, count 0 2006.173.08:50:46.54#ibcon#flushed, iclass 18, count 0 2006.173.08:50:46.54#ibcon#about to write, iclass 18, count 0 2006.173.08:50:46.54#ibcon#wrote, iclass 18, count 0 2006.173.08:50:46.54#ibcon#about to read 3, iclass 18, count 0 2006.173.08:50:46.58#ibcon#read 3, iclass 18, count 0 2006.173.08:50:46.58#ibcon#about to read 4, iclass 18, count 0 2006.173.08:50:46.58#ibcon#read 4, iclass 18, count 0 2006.173.08:50:46.58#ibcon#about to read 5, iclass 18, count 0 2006.173.08:50:46.58#ibcon#read 5, iclass 18, count 0 2006.173.08:50:46.58#ibcon#about to read 6, iclass 18, count 0 2006.173.08:50:46.58#ibcon#read 6, iclass 18, count 0 2006.173.08:50:46.58#ibcon#end of sib2, iclass 18, count 0 2006.173.08:50:46.58#ibcon#*after write, iclass 18, count 0 2006.173.08:50:46.58#ibcon#*before return 0, iclass 18, count 0 2006.173.08:50:46.58#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.08:50:46.58#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.08:50:46.58#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.08:50:46.58#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.08:50:46.58$vck44/vb=3,4 2006.173.08:50:46.58#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.08:50:46.58#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.08:50:46.58#ibcon#ireg 11 cls_cnt 2 2006.173.08:50:46.58#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.08:50:46.64#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.08:50:46.64#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.08:50:46.64#ibcon#enter wrdev, iclass 20, count 2 2006.173.08:50:46.64#ibcon#first serial, iclass 20, count 2 2006.173.08:50:46.64#ibcon#enter sib2, iclass 20, count 2 2006.173.08:50:46.64#ibcon#flushed, iclass 20, count 2 2006.173.08:50:46.64#ibcon#about to write, iclass 20, count 2 2006.173.08:50:46.64#ibcon#wrote, iclass 20, count 2 2006.173.08:50:46.64#ibcon#about to read 3, iclass 20, count 2 2006.173.08:50:46.66#ibcon#read 3, iclass 20, count 2 2006.173.08:50:46.66#ibcon#about to read 4, iclass 20, count 2 2006.173.08:50:46.66#ibcon#read 4, iclass 20, count 2 2006.173.08:50:46.66#ibcon#about to read 5, iclass 20, count 2 2006.173.08:50:46.66#ibcon#read 5, iclass 20, count 2 2006.173.08:50:46.66#ibcon#about to read 6, iclass 20, count 2 2006.173.08:50:46.66#ibcon#read 6, iclass 20, count 2 2006.173.08:50:46.66#ibcon#end of sib2, iclass 20, count 2 2006.173.08:50:46.66#ibcon#*mode == 0, iclass 20, count 2 2006.173.08:50:46.66#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.08:50:46.66#ibcon#[27=AT03-04\r\n] 2006.173.08:50:46.66#ibcon#*before write, iclass 20, count 2 2006.173.08:50:46.66#ibcon#enter sib2, iclass 20, count 2 2006.173.08:50:46.66#ibcon#flushed, iclass 20, count 2 2006.173.08:50:46.66#ibcon#about to write, iclass 20, count 2 2006.173.08:50:46.66#ibcon#wrote, iclass 20, count 2 2006.173.08:50:46.66#ibcon#about to read 3, iclass 20, count 2 2006.173.08:50:46.69#ibcon#read 3, iclass 20, count 2 2006.173.08:50:46.69#ibcon#about to read 4, iclass 20, count 2 2006.173.08:50:46.69#ibcon#read 4, iclass 20, count 2 2006.173.08:50:46.69#ibcon#about to read 5, iclass 20, count 2 2006.173.08:50:46.69#ibcon#read 5, iclass 20, count 2 2006.173.08:50:46.69#ibcon#about to read 6, iclass 20, count 2 2006.173.08:50:46.69#ibcon#read 6, iclass 20, count 2 2006.173.08:50:46.69#ibcon#end of sib2, iclass 20, count 2 2006.173.08:50:46.69#ibcon#*after write, iclass 20, count 2 2006.173.08:50:46.69#ibcon#*before return 0, iclass 20, count 2 2006.173.08:50:46.69#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.08:50:46.69#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.08:50:46.69#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.08:50:46.69#ibcon#ireg 7 cls_cnt 0 2006.173.08:50:46.69#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.08:50:46.81#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.08:50:46.81#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.08:50:46.81#ibcon#enter wrdev, iclass 20, count 0 2006.173.08:50:46.81#ibcon#first serial, iclass 20, count 0 2006.173.08:50:46.81#ibcon#enter sib2, iclass 20, count 0 2006.173.08:50:46.81#ibcon#flushed, iclass 20, count 0 2006.173.08:50:46.81#ibcon#about to write, iclass 20, count 0 2006.173.08:50:46.81#ibcon#wrote, iclass 20, count 0 2006.173.08:50:46.81#ibcon#about to read 3, iclass 20, count 0 2006.173.08:50:46.83#ibcon#read 3, iclass 20, count 0 2006.173.08:50:46.83#ibcon#about to read 4, iclass 20, count 0 2006.173.08:50:46.83#ibcon#read 4, iclass 20, count 0 2006.173.08:50:46.83#ibcon#about to read 5, iclass 20, count 0 2006.173.08:50:46.83#ibcon#read 5, iclass 20, count 0 2006.173.08:50:46.83#ibcon#about to read 6, iclass 20, count 0 2006.173.08:50:46.83#ibcon#read 6, iclass 20, count 0 2006.173.08:50:46.83#ibcon#end of sib2, iclass 20, count 0 2006.173.08:50:46.83#ibcon#*mode == 0, iclass 20, count 0 2006.173.08:50:46.83#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.08:50:46.83#ibcon#[27=USB\r\n] 2006.173.08:50:46.83#ibcon#*before write, iclass 20, count 0 2006.173.08:50:46.83#ibcon#enter sib2, iclass 20, count 0 2006.173.08:50:46.83#ibcon#flushed, iclass 20, count 0 2006.173.08:50:46.83#ibcon#about to write, iclass 20, count 0 2006.173.08:50:46.83#ibcon#wrote, iclass 20, count 0 2006.173.08:50:46.83#ibcon#about to read 3, iclass 20, count 0 2006.173.08:50:46.86#ibcon#read 3, iclass 20, count 0 2006.173.08:50:46.86#ibcon#about to read 4, iclass 20, count 0 2006.173.08:50:46.86#ibcon#read 4, iclass 20, count 0 2006.173.08:50:46.86#ibcon#about to read 5, iclass 20, count 0 2006.173.08:50:46.86#ibcon#read 5, iclass 20, count 0 2006.173.08:50:46.86#ibcon#about to read 6, iclass 20, count 0 2006.173.08:50:46.86#ibcon#read 6, iclass 20, count 0 2006.173.08:50:46.86#ibcon#end of sib2, iclass 20, count 0 2006.173.08:50:46.86#ibcon#*after write, iclass 20, count 0 2006.173.08:50:46.86#ibcon#*before return 0, iclass 20, count 0 2006.173.08:50:46.86#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.08:50:46.86#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.08:50:46.86#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.08:50:46.86#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.08:50:46.86$vck44/vblo=4,679.99 2006.173.08:50:46.86#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.08:50:46.86#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.08:50:46.86#ibcon#ireg 17 cls_cnt 0 2006.173.08:50:46.86#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.08:50:46.86#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.08:50:46.86#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.08:50:46.86#ibcon#enter wrdev, iclass 22, count 0 2006.173.08:50:46.86#ibcon#first serial, iclass 22, count 0 2006.173.08:50:46.86#ibcon#enter sib2, iclass 22, count 0 2006.173.08:50:46.86#ibcon#flushed, iclass 22, count 0 2006.173.08:50:46.86#ibcon#about to write, iclass 22, count 0 2006.173.08:50:46.86#ibcon#wrote, iclass 22, count 0 2006.173.08:50:46.86#ibcon#about to read 3, iclass 22, count 0 2006.173.08:50:46.88#ibcon#read 3, iclass 22, count 0 2006.173.08:50:46.88#ibcon#about to read 4, iclass 22, count 0 2006.173.08:50:46.88#ibcon#read 4, iclass 22, count 0 2006.173.08:50:46.88#ibcon#about to read 5, iclass 22, count 0 2006.173.08:50:46.88#ibcon#read 5, iclass 22, count 0 2006.173.08:50:46.88#ibcon#about to read 6, iclass 22, count 0 2006.173.08:50:46.88#ibcon#read 6, iclass 22, count 0 2006.173.08:50:46.88#ibcon#end of sib2, iclass 22, count 0 2006.173.08:50:46.88#ibcon#*mode == 0, iclass 22, count 0 2006.173.08:50:46.88#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.08:50:46.88#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.08:50:46.88#ibcon#*before write, iclass 22, count 0 2006.173.08:50:46.88#ibcon#enter sib2, iclass 22, count 0 2006.173.08:50:46.88#ibcon#flushed, iclass 22, count 0 2006.173.08:50:46.88#ibcon#about to write, iclass 22, count 0 2006.173.08:50:46.88#ibcon#wrote, iclass 22, count 0 2006.173.08:50:46.88#ibcon#about to read 3, iclass 22, count 0 2006.173.08:50:46.92#ibcon#read 3, iclass 22, count 0 2006.173.08:50:46.92#ibcon#about to read 4, iclass 22, count 0 2006.173.08:50:46.92#ibcon#read 4, iclass 22, count 0 2006.173.08:50:46.92#ibcon#about to read 5, iclass 22, count 0 2006.173.08:50:46.92#ibcon#read 5, iclass 22, count 0 2006.173.08:50:46.92#ibcon#about to read 6, iclass 22, count 0 2006.173.08:50:46.92#ibcon#read 6, iclass 22, count 0 2006.173.08:50:46.92#ibcon#end of sib2, iclass 22, count 0 2006.173.08:50:46.92#ibcon#*after write, iclass 22, count 0 2006.173.08:50:46.92#ibcon#*before return 0, iclass 22, count 0 2006.173.08:50:46.92#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.08:50:46.92#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.08:50:46.92#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.08:50:46.92#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.08:50:46.92$vck44/vb=4,4 2006.173.08:50:46.92#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.08:50:46.92#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.08:50:46.92#ibcon#ireg 11 cls_cnt 2 2006.173.08:50:46.92#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.08:50:46.98#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.08:50:46.98#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.08:50:46.98#ibcon#enter wrdev, iclass 24, count 2 2006.173.08:50:46.98#ibcon#first serial, iclass 24, count 2 2006.173.08:50:46.98#ibcon#enter sib2, iclass 24, count 2 2006.173.08:50:46.98#ibcon#flushed, iclass 24, count 2 2006.173.08:50:46.98#ibcon#about to write, iclass 24, count 2 2006.173.08:50:46.98#ibcon#wrote, iclass 24, count 2 2006.173.08:50:46.98#ibcon#about to read 3, iclass 24, count 2 2006.173.08:50:47.00#ibcon#read 3, iclass 24, count 2 2006.173.08:50:47.00#ibcon#about to read 4, iclass 24, count 2 2006.173.08:50:47.00#ibcon#read 4, iclass 24, count 2 2006.173.08:50:47.00#ibcon#about to read 5, iclass 24, count 2 2006.173.08:50:47.00#ibcon#read 5, iclass 24, count 2 2006.173.08:50:47.00#ibcon#about to read 6, iclass 24, count 2 2006.173.08:50:47.00#ibcon#read 6, iclass 24, count 2 2006.173.08:50:47.00#ibcon#end of sib2, iclass 24, count 2 2006.173.08:50:47.00#ibcon#*mode == 0, iclass 24, count 2 2006.173.08:50:47.00#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.08:50:47.00#ibcon#[27=AT04-04\r\n] 2006.173.08:50:47.00#ibcon#*before write, iclass 24, count 2 2006.173.08:50:47.00#ibcon#enter sib2, iclass 24, count 2 2006.173.08:50:47.00#ibcon#flushed, iclass 24, count 2 2006.173.08:50:47.00#ibcon#about to write, iclass 24, count 2 2006.173.08:50:47.00#ibcon#wrote, iclass 24, count 2 2006.173.08:50:47.00#ibcon#about to read 3, iclass 24, count 2 2006.173.08:50:47.03#ibcon#read 3, iclass 24, count 2 2006.173.08:50:47.03#ibcon#about to read 4, iclass 24, count 2 2006.173.08:50:47.03#ibcon#read 4, iclass 24, count 2 2006.173.08:50:47.03#ibcon#about to read 5, iclass 24, count 2 2006.173.08:50:47.03#ibcon#read 5, iclass 24, count 2 2006.173.08:50:47.03#ibcon#about to read 6, iclass 24, count 2 2006.173.08:50:47.03#ibcon#read 6, iclass 24, count 2 2006.173.08:50:47.03#ibcon#end of sib2, iclass 24, count 2 2006.173.08:50:47.03#ibcon#*after write, iclass 24, count 2 2006.173.08:50:47.03#ibcon#*before return 0, iclass 24, count 2 2006.173.08:50:47.03#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.08:50:47.03#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.08:50:47.03#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.08:50:47.03#ibcon#ireg 7 cls_cnt 0 2006.173.08:50:47.03#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.08:50:47.15#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.08:50:47.15#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.08:50:47.15#ibcon#enter wrdev, iclass 24, count 0 2006.173.08:50:47.15#ibcon#first serial, iclass 24, count 0 2006.173.08:50:47.15#ibcon#enter sib2, iclass 24, count 0 2006.173.08:50:47.15#ibcon#flushed, iclass 24, count 0 2006.173.08:50:47.15#ibcon#about to write, iclass 24, count 0 2006.173.08:50:47.15#ibcon#wrote, iclass 24, count 0 2006.173.08:50:47.15#ibcon#about to read 3, iclass 24, count 0 2006.173.08:50:47.17#ibcon#read 3, iclass 24, count 0 2006.173.08:50:47.17#ibcon#about to read 4, iclass 24, count 0 2006.173.08:50:47.17#ibcon#read 4, iclass 24, count 0 2006.173.08:50:47.17#ibcon#about to read 5, iclass 24, count 0 2006.173.08:50:47.17#ibcon#read 5, iclass 24, count 0 2006.173.08:50:47.17#ibcon#about to read 6, iclass 24, count 0 2006.173.08:50:47.17#ibcon#read 6, iclass 24, count 0 2006.173.08:50:47.17#ibcon#end of sib2, iclass 24, count 0 2006.173.08:50:47.17#ibcon#*mode == 0, iclass 24, count 0 2006.173.08:50:47.17#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.08:50:47.17#ibcon#[27=USB\r\n] 2006.173.08:50:47.17#ibcon#*before write, iclass 24, count 0 2006.173.08:50:47.17#ibcon#enter sib2, iclass 24, count 0 2006.173.08:50:47.17#ibcon#flushed, iclass 24, count 0 2006.173.08:50:47.17#ibcon#about to write, iclass 24, count 0 2006.173.08:50:47.17#ibcon#wrote, iclass 24, count 0 2006.173.08:50:47.17#ibcon#about to read 3, iclass 24, count 0 2006.173.08:50:47.20#ibcon#read 3, iclass 24, count 0 2006.173.08:50:47.20#ibcon#about to read 4, iclass 24, count 0 2006.173.08:50:47.20#ibcon#read 4, iclass 24, count 0 2006.173.08:50:47.20#ibcon#about to read 5, iclass 24, count 0 2006.173.08:50:47.20#ibcon#read 5, iclass 24, count 0 2006.173.08:50:47.20#ibcon#about to read 6, iclass 24, count 0 2006.173.08:50:47.20#ibcon#read 6, iclass 24, count 0 2006.173.08:50:47.20#ibcon#end of sib2, iclass 24, count 0 2006.173.08:50:47.20#ibcon#*after write, iclass 24, count 0 2006.173.08:50:47.20#ibcon#*before return 0, iclass 24, count 0 2006.173.08:50:47.20#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.08:50:47.20#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.08:50:47.20#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.08:50:47.20#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.08:50:47.20$vck44/vblo=5,709.99 2006.173.08:50:47.20#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.08:50:47.20#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.08:50:47.20#ibcon#ireg 17 cls_cnt 0 2006.173.08:50:47.20#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.08:50:47.20#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.08:50:47.20#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.08:50:47.20#ibcon#enter wrdev, iclass 26, count 0 2006.173.08:50:47.20#ibcon#first serial, iclass 26, count 0 2006.173.08:50:47.20#ibcon#enter sib2, iclass 26, count 0 2006.173.08:50:47.20#ibcon#flushed, iclass 26, count 0 2006.173.08:50:47.20#ibcon#about to write, iclass 26, count 0 2006.173.08:50:47.20#ibcon#wrote, iclass 26, count 0 2006.173.08:50:47.20#ibcon#about to read 3, iclass 26, count 0 2006.173.08:50:47.22#ibcon#read 3, iclass 26, count 0 2006.173.08:50:47.22#ibcon#about to read 4, iclass 26, count 0 2006.173.08:50:47.22#ibcon#read 4, iclass 26, count 0 2006.173.08:50:47.22#ibcon#about to read 5, iclass 26, count 0 2006.173.08:50:47.22#ibcon#read 5, iclass 26, count 0 2006.173.08:50:47.22#ibcon#about to read 6, iclass 26, count 0 2006.173.08:50:47.22#ibcon#read 6, iclass 26, count 0 2006.173.08:50:47.22#ibcon#end of sib2, iclass 26, count 0 2006.173.08:50:47.22#ibcon#*mode == 0, iclass 26, count 0 2006.173.08:50:47.22#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.08:50:47.22#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.08:50:47.22#ibcon#*before write, iclass 26, count 0 2006.173.08:50:47.22#ibcon#enter sib2, iclass 26, count 0 2006.173.08:50:47.22#ibcon#flushed, iclass 26, count 0 2006.173.08:50:47.22#ibcon#about to write, iclass 26, count 0 2006.173.08:50:47.22#ibcon#wrote, iclass 26, count 0 2006.173.08:50:47.22#ibcon#about to read 3, iclass 26, count 0 2006.173.08:50:47.25#abcon#<5=/02 0.4 1.0 23.12 861004.2\r\n> 2006.173.08:50:47.26#ibcon#read 3, iclass 26, count 0 2006.173.08:50:47.26#ibcon#about to read 4, iclass 26, count 0 2006.173.08:50:47.26#ibcon#read 4, iclass 26, count 0 2006.173.08:50:47.26#ibcon#about to read 5, iclass 26, count 0 2006.173.08:50:47.26#ibcon#read 5, iclass 26, count 0 2006.173.08:50:47.26#ibcon#about to read 6, iclass 26, count 0 2006.173.08:50:47.26#ibcon#read 6, iclass 26, count 0 2006.173.08:50:47.26#ibcon#end of sib2, iclass 26, count 0 2006.173.08:50:47.26#ibcon#*after write, iclass 26, count 0 2006.173.08:50:47.26#ibcon#*before return 0, iclass 26, count 0 2006.173.08:50:47.26#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.08:50:47.26#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.08:50:47.26#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.08:50:47.26#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.08:50:47.26$vck44/vb=5,4 2006.173.08:50:47.26#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.08:50:47.26#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.08:50:47.26#ibcon#ireg 11 cls_cnt 2 2006.173.08:50:47.26#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.08:50:47.27#abcon#{5=INTERFACE CLEAR} 2006.173.08:50:47.32#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.08:50:47.32#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.08:50:47.32#ibcon#enter wrdev, iclass 31, count 2 2006.173.08:50:47.32#ibcon#first serial, iclass 31, count 2 2006.173.08:50:47.32#ibcon#enter sib2, iclass 31, count 2 2006.173.08:50:47.32#ibcon#flushed, iclass 31, count 2 2006.173.08:50:47.32#ibcon#about to write, iclass 31, count 2 2006.173.08:50:47.32#ibcon#wrote, iclass 31, count 2 2006.173.08:50:47.32#ibcon#about to read 3, iclass 31, count 2 2006.173.08:50:47.33#abcon#[5=S1D000X0/0*\r\n] 2006.173.08:50:47.34#ibcon#read 3, iclass 31, count 2 2006.173.08:50:47.34#ibcon#about to read 4, iclass 31, count 2 2006.173.08:50:47.34#ibcon#read 4, iclass 31, count 2 2006.173.08:50:47.34#ibcon#about to read 5, iclass 31, count 2 2006.173.08:50:47.34#ibcon#read 5, iclass 31, count 2 2006.173.08:50:47.34#ibcon#about to read 6, iclass 31, count 2 2006.173.08:50:47.34#ibcon#read 6, iclass 31, count 2 2006.173.08:50:47.34#ibcon#end of sib2, iclass 31, count 2 2006.173.08:50:47.34#ibcon#*mode == 0, iclass 31, count 2 2006.173.08:50:47.34#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.08:50:47.34#ibcon#[27=AT05-04\r\n] 2006.173.08:50:47.34#ibcon#*before write, iclass 31, count 2 2006.173.08:50:47.34#ibcon#enter sib2, iclass 31, count 2 2006.173.08:50:47.34#ibcon#flushed, iclass 31, count 2 2006.173.08:50:47.34#ibcon#about to write, iclass 31, count 2 2006.173.08:50:47.34#ibcon#wrote, iclass 31, count 2 2006.173.08:50:47.34#ibcon#about to read 3, iclass 31, count 2 2006.173.08:50:47.37#ibcon#read 3, iclass 31, count 2 2006.173.08:50:47.37#ibcon#about to read 4, iclass 31, count 2 2006.173.08:50:47.37#ibcon#read 4, iclass 31, count 2 2006.173.08:50:47.37#ibcon#about to read 5, iclass 31, count 2 2006.173.08:50:47.37#ibcon#read 5, iclass 31, count 2 2006.173.08:50:47.37#ibcon#about to read 6, iclass 31, count 2 2006.173.08:50:47.37#ibcon#read 6, iclass 31, count 2 2006.173.08:50:47.37#ibcon#end of sib2, iclass 31, count 2 2006.173.08:50:47.37#ibcon#*after write, iclass 31, count 2 2006.173.08:50:47.37#ibcon#*before return 0, iclass 31, count 2 2006.173.08:50:47.37#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.08:50:47.37#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.08:50:47.37#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.08:50:47.37#ibcon#ireg 7 cls_cnt 0 2006.173.08:50:47.37#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.08:50:47.49#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.08:50:47.49#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.08:50:47.49#ibcon#enter wrdev, iclass 31, count 0 2006.173.08:50:47.49#ibcon#first serial, iclass 31, count 0 2006.173.08:50:47.49#ibcon#enter sib2, iclass 31, count 0 2006.173.08:50:47.49#ibcon#flushed, iclass 31, count 0 2006.173.08:50:47.49#ibcon#about to write, iclass 31, count 0 2006.173.08:50:47.49#ibcon#wrote, iclass 31, count 0 2006.173.08:50:47.49#ibcon#about to read 3, iclass 31, count 0 2006.173.08:50:47.51#ibcon#read 3, iclass 31, count 0 2006.173.08:50:47.51#ibcon#about to read 4, iclass 31, count 0 2006.173.08:50:47.51#ibcon#read 4, iclass 31, count 0 2006.173.08:50:47.51#ibcon#about to read 5, iclass 31, count 0 2006.173.08:50:47.51#ibcon#read 5, iclass 31, count 0 2006.173.08:50:47.51#ibcon#about to read 6, iclass 31, count 0 2006.173.08:50:47.51#ibcon#read 6, iclass 31, count 0 2006.173.08:50:47.51#ibcon#end of sib2, iclass 31, count 0 2006.173.08:50:47.51#ibcon#*mode == 0, iclass 31, count 0 2006.173.08:50:47.51#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.08:50:47.51#ibcon#[27=USB\r\n] 2006.173.08:50:47.51#ibcon#*before write, iclass 31, count 0 2006.173.08:50:47.51#ibcon#enter sib2, iclass 31, count 0 2006.173.08:50:47.51#ibcon#flushed, iclass 31, count 0 2006.173.08:50:47.51#ibcon#about to write, iclass 31, count 0 2006.173.08:50:47.51#ibcon#wrote, iclass 31, count 0 2006.173.08:50:47.51#ibcon#about to read 3, iclass 31, count 0 2006.173.08:50:47.54#ibcon#read 3, iclass 31, count 0 2006.173.08:50:47.54#ibcon#about to read 4, iclass 31, count 0 2006.173.08:50:47.54#ibcon#read 4, iclass 31, count 0 2006.173.08:50:47.54#ibcon#about to read 5, iclass 31, count 0 2006.173.08:50:47.54#ibcon#read 5, iclass 31, count 0 2006.173.08:50:47.54#ibcon#about to read 6, iclass 31, count 0 2006.173.08:50:47.54#ibcon#read 6, iclass 31, count 0 2006.173.08:50:47.54#ibcon#end of sib2, iclass 31, count 0 2006.173.08:50:47.54#ibcon#*after write, iclass 31, count 0 2006.173.08:50:47.54#ibcon#*before return 0, iclass 31, count 0 2006.173.08:50:47.54#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.08:50:47.54#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.08:50:47.54#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.08:50:47.54#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.08:50:47.54$vck44/vblo=6,719.99 2006.173.08:50:47.54#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.08:50:47.54#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.08:50:47.54#ibcon#ireg 17 cls_cnt 0 2006.173.08:50:47.54#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.08:50:47.54#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.08:50:47.54#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.08:50:47.54#ibcon#enter wrdev, iclass 34, count 0 2006.173.08:50:47.54#ibcon#first serial, iclass 34, count 0 2006.173.08:50:47.54#ibcon#enter sib2, iclass 34, count 0 2006.173.08:50:47.54#ibcon#flushed, iclass 34, count 0 2006.173.08:50:47.54#ibcon#about to write, iclass 34, count 0 2006.173.08:50:47.54#ibcon#wrote, iclass 34, count 0 2006.173.08:50:47.54#ibcon#about to read 3, iclass 34, count 0 2006.173.08:50:47.56#ibcon#read 3, iclass 34, count 0 2006.173.08:50:47.56#ibcon#about to read 4, iclass 34, count 0 2006.173.08:50:47.56#ibcon#read 4, iclass 34, count 0 2006.173.08:50:47.56#ibcon#about to read 5, iclass 34, count 0 2006.173.08:50:47.56#ibcon#read 5, iclass 34, count 0 2006.173.08:50:47.56#ibcon#about to read 6, iclass 34, count 0 2006.173.08:50:47.56#ibcon#read 6, iclass 34, count 0 2006.173.08:50:47.56#ibcon#end of sib2, iclass 34, count 0 2006.173.08:50:47.56#ibcon#*mode == 0, iclass 34, count 0 2006.173.08:50:47.56#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.08:50:47.56#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.08:50:47.56#ibcon#*before write, iclass 34, count 0 2006.173.08:50:47.56#ibcon#enter sib2, iclass 34, count 0 2006.173.08:50:47.56#ibcon#flushed, iclass 34, count 0 2006.173.08:50:47.56#ibcon#about to write, iclass 34, count 0 2006.173.08:50:47.56#ibcon#wrote, iclass 34, count 0 2006.173.08:50:47.56#ibcon#about to read 3, iclass 34, count 0 2006.173.08:50:47.60#ibcon#read 3, iclass 34, count 0 2006.173.08:50:47.60#ibcon#about to read 4, iclass 34, count 0 2006.173.08:50:47.60#ibcon#read 4, iclass 34, count 0 2006.173.08:50:47.60#ibcon#about to read 5, iclass 34, count 0 2006.173.08:50:47.60#ibcon#read 5, iclass 34, count 0 2006.173.08:50:47.60#ibcon#about to read 6, iclass 34, count 0 2006.173.08:50:47.60#ibcon#read 6, iclass 34, count 0 2006.173.08:50:47.60#ibcon#end of sib2, iclass 34, count 0 2006.173.08:50:47.60#ibcon#*after write, iclass 34, count 0 2006.173.08:50:47.60#ibcon#*before return 0, iclass 34, count 0 2006.173.08:50:47.60#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.08:50:47.60#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.08:50:47.60#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.08:50:47.60#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.08:50:47.60$vck44/vb=6,4 2006.173.08:50:47.60#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.08:50:47.60#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.08:50:47.60#ibcon#ireg 11 cls_cnt 2 2006.173.08:50:47.60#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.08:50:47.66#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.08:50:47.66#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.08:50:47.66#ibcon#enter wrdev, iclass 36, count 2 2006.173.08:50:47.66#ibcon#first serial, iclass 36, count 2 2006.173.08:50:47.66#ibcon#enter sib2, iclass 36, count 2 2006.173.08:50:47.66#ibcon#flushed, iclass 36, count 2 2006.173.08:50:47.66#ibcon#about to write, iclass 36, count 2 2006.173.08:50:47.66#ibcon#wrote, iclass 36, count 2 2006.173.08:50:47.66#ibcon#about to read 3, iclass 36, count 2 2006.173.08:50:47.68#ibcon#read 3, iclass 36, count 2 2006.173.08:50:47.68#ibcon#about to read 4, iclass 36, count 2 2006.173.08:50:47.68#ibcon#read 4, iclass 36, count 2 2006.173.08:50:47.68#ibcon#about to read 5, iclass 36, count 2 2006.173.08:50:47.68#ibcon#read 5, iclass 36, count 2 2006.173.08:50:47.68#ibcon#about to read 6, iclass 36, count 2 2006.173.08:50:47.68#ibcon#read 6, iclass 36, count 2 2006.173.08:50:47.68#ibcon#end of sib2, iclass 36, count 2 2006.173.08:50:47.68#ibcon#*mode == 0, iclass 36, count 2 2006.173.08:50:47.68#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.08:50:47.68#ibcon#[27=AT06-04\r\n] 2006.173.08:50:47.68#ibcon#*before write, iclass 36, count 2 2006.173.08:50:47.68#ibcon#enter sib2, iclass 36, count 2 2006.173.08:50:47.68#ibcon#flushed, iclass 36, count 2 2006.173.08:50:47.68#ibcon#about to write, iclass 36, count 2 2006.173.08:50:47.68#ibcon#wrote, iclass 36, count 2 2006.173.08:50:47.68#ibcon#about to read 3, iclass 36, count 2 2006.173.08:50:47.71#ibcon#read 3, iclass 36, count 2 2006.173.08:50:47.71#ibcon#about to read 4, iclass 36, count 2 2006.173.08:50:47.71#ibcon#read 4, iclass 36, count 2 2006.173.08:50:47.71#ibcon#about to read 5, iclass 36, count 2 2006.173.08:50:47.71#ibcon#read 5, iclass 36, count 2 2006.173.08:50:47.71#ibcon#about to read 6, iclass 36, count 2 2006.173.08:50:47.71#ibcon#read 6, iclass 36, count 2 2006.173.08:50:47.71#ibcon#end of sib2, iclass 36, count 2 2006.173.08:50:47.71#ibcon#*after write, iclass 36, count 2 2006.173.08:50:47.71#ibcon#*before return 0, iclass 36, count 2 2006.173.08:50:47.71#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.08:50:47.71#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.08:50:47.71#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.08:50:47.71#ibcon#ireg 7 cls_cnt 0 2006.173.08:50:47.71#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.08:50:47.83#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.08:50:47.83#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.08:50:47.83#ibcon#enter wrdev, iclass 36, count 0 2006.173.08:50:47.83#ibcon#first serial, iclass 36, count 0 2006.173.08:50:47.83#ibcon#enter sib2, iclass 36, count 0 2006.173.08:50:47.83#ibcon#flushed, iclass 36, count 0 2006.173.08:50:47.83#ibcon#about to write, iclass 36, count 0 2006.173.08:50:47.83#ibcon#wrote, iclass 36, count 0 2006.173.08:50:47.83#ibcon#about to read 3, iclass 36, count 0 2006.173.08:50:47.85#ibcon#read 3, iclass 36, count 0 2006.173.08:50:47.85#ibcon#about to read 4, iclass 36, count 0 2006.173.08:50:47.85#ibcon#read 4, iclass 36, count 0 2006.173.08:50:47.85#ibcon#about to read 5, iclass 36, count 0 2006.173.08:50:47.85#ibcon#read 5, iclass 36, count 0 2006.173.08:50:47.85#ibcon#about to read 6, iclass 36, count 0 2006.173.08:50:47.85#ibcon#read 6, iclass 36, count 0 2006.173.08:50:47.85#ibcon#end of sib2, iclass 36, count 0 2006.173.08:50:47.85#ibcon#*mode == 0, iclass 36, count 0 2006.173.08:50:47.85#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.08:50:47.85#ibcon#[27=USB\r\n] 2006.173.08:50:47.85#ibcon#*before write, iclass 36, count 0 2006.173.08:50:47.85#ibcon#enter sib2, iclass 36, count 0 2006.173.08:50:47.85#ibcon#flushed, iclass 36, count 0 2006.173.08:50:47.85#ibcon#about to write, iclass 36, count 0 2006.173.08:50:47.85#ibcon#wrote, iclass 36, count 0 2006.173.08:50:47.85#ibcon#about to read 3, iclass 36, count 0 2006.173.08:50:47.88#ibcon#read 3, iclass 36, count 0 2006.173.08:50:47.88#ibcon#about to read 4, iclass 36, count 0 2006.173.08:50:47.88#ibcon#read 4, iclass 36, count 0 2006.173.08:50:47.88#ibcon#about to read 5, iclass 36, count 0 2006.173.08:50:47.88#ibcon#read 5, iclass 36, count 0 2006.173.08:50:47.88#ibcon#about to read 6, iclass 36, count 0 2006.173.08:50:47.88#ibcon#read 6, iclass 36, count 0 2006.173.08:50:47.88#ibcon#end of sib2, iclass 36, count 0 2006.173.08:50:47.88#ibcon#*after write, iclass 36, count 0 2006.173.08:50:47.88#ibcon#*before return 0, iclass 36, count 0 2006.173.08:50:47.88#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.08:50:47.88#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.08:50:47.88#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.08:50:47.88#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.08:50:47.88$vck44/vblo=7,734.99 2006.173.08:50:47.88#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.08:50:47.88#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.08:50:47.88#ibcon#ireg 17 cls_cnt 0 2006.173.08:50:47.88#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.08:50:47.88#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.08:50:47.88#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.08:50:47.88#ibcon#enter wrdev, iclass 38, count 0 2006.173.08:50:47.88#ibcon#first serial, iclass 38, count 0 2006.173.08:50:47.88#ibcon#enter sib2, iclass 38, count 0 2006.173.08:50:47.88#ibcon#flushed, iclass 38, count 0 2006.173.08:50:47.88#ibcon#about to write, iclass 38, count 0 2006.173.08:50:47.88#ibcon#wrote, iclass 38, count 0 2006.173.08:50:47.88#ibcon#about to read 3, iclass 38, count 0 2006.173.08:50:47.90#ibcon#read 3, iclass 38, count 0 2006.173.08:50:47.90#ibcon#about to read 4, iclass 38, count 0 2006.173.08:50:47.90#ibcon#read 4, iclass 38, count 0 2006.173.08:50:47.90#ibcon#about to read 5, iclass 38, count 0 2006.173.08:50:47.90#ibcon#read 5, iclass 38, count 0 2006.173.08:50:47.90#ibcon#about to read 6, iclass 38, count 0 2006.173.08:50:47.90#ibcon#read 6, iclass 38, count 0 2006.173.08:50:47.90#ibcon#end of sib2, iclass 38, count 0 2006.173.08:50:47.90#ibcon#*mode == 0, iclass 38, count 0 2006.173.08:50:47.90#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.08:50:47.90#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.08:50:47.90#ibcon#*before write, iclass 38, count 0 2006.173.08:50:47.90#ibcon#enter sib2, iclass 38, count 0 2006.173.08:50:47.90#ibcon#flushed, iclass 38, count 0 2006.173.08:50:47.90#ibcon#about to write, iclass 38, count 0 2006.173.08:50:47.90#ibcon#wrote, iclass 38, count 0 2006.173.08:50:47.90#ibcon#about to read 3, iclass 38, count 0 2006.173.08:50:47.94#ibcon#read 3, iclass 38, count 0 2006.173.08:50:47.94#ibcon#about to read 4, iclass 38, count 0 2006.173.08:50:47.94#ibcon#read 4, iclass 38, count 0 2006.173.08:50:47.94#ibcon#about to read 5, iclass 38, count 0 2006.173.08:50:47.94#ibcon#read 5, iclass 38, count 0 2006.173.08:50:47.94#ibcon#about to read 6, iclass 38, count 0 2006.173.08:50:47.94#ibcon#read 6, iclass 38, count 0 2006.173.08:50:47.94#ibcon#end of sib2, iclass 38, count 0 2006.173.08:50:47.94#ibcon#*after write, iclass 38, count 0 2006.173.08:50:47.94#ibcon#*before return 0, iclass 38, count 0 2006.173.08:50:47.94#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.08:50:47.94#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.08:50:47.94#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.08:50:47.94#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.08:50:47.94$vck44/vb=7,4 2006.173.08:50:47.94#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.08:50:47.94#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.08:50:47.94#ibcon#ireg 11 cls_cnt 2 2006.173.08:50:47.94#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.08:50:48.00#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.08:50:48.00#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.08:50:48.00#ibcon#enter wrdev, iclass 40, count 2 2006.173.08:50:48.00#ibcon#first serial, iclass 40, count 2 2006.173.08:50:48.00#ibcon#enter sib2, iclass 40, count 2 2006.173.08:50:48.00#ibcon#flushed, iclass 40, count 2 2006.173.08:50:48.00#ibcon#about to write, iclass 40, count 2 2006.173.08:50:48.00#ibcon#wrote, iclass 40, count 2 2006.173.08:50:48.00#ibcon#about to read 3, iclass 40, count 2 2006.173.08:50:48.02#ibcon#read 3, iclass 40, count 2 2006.173.08:50:48.02#ibcon#about to read 4, iclass 40, count 2 2006.173.08:50:48.02#ibcon#read 4, iclass 40, count 2 2006.173.08:50:48.02#ibcon#about to read 5, iclass 40, count 2 2006.173.08:50:48.02#ibcon#read 5, iclass 40, count 2 2006.173.08:50:48.02#ibcon#about to read 6, iclass 40, count 2 2006.173.08:50:48.02#ibcon#read 6, iclass 40, count 2 2006.173.08:50:48.02#ibcon#end of sib2, iclass 40, count 2 2006.173.08:50:48.02#ibcon#*mode == 0, iclass 40, count 2 2006.173.08:50:48.02#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.08:50:48.02#ibcon#[27=AT07-04\r\n] 2006.173.08:50:48.02#ibcon#*before write, iclass 40, count 2 2006.173.08:50:48.02#ibcon#enter sib2, iclass 40, count 2 2006.173.08:50:48.02#ibcon#flushed, iclass 40, count 2 2006.173.08:50:48.02#ibcon#about to write, iclass 40, count 2 2006.173.08:50:48.02#ibcon#wrote, iclass 40, count 2 2006.173.08:50:48.02#ibcon#about to read 3, iclass 40, count 2 2006.173.08:50:48.05#ibcon#read 3, iclass 40, count 2 2006.173.08:50:48.05#ibcon#about to read 4, iclass 40, count 2 2006.173.08:50:48.05#ibcon#read 4, iclass 40, count 2 2006.173.08:50:48.05#ibcon#about to read 5, iclass 40, count 2 2006.173.08:50:48.05#ibcon#read 5, iclass 40, count 2 2006.173.08:50:48.05#ibcon#about to read 6, iclass 40, count 2 2006.173.08:50:48.05#ibcon#read 6, iclass 40, count 2 2006.173.08:50:48.05#ibcon#end of sib2, iclass 40, count 2 2006.173.08:50:48.05#ibcon#*after write, iclass 40, count 2 2006.173.08:50:48.05#ibcon#*before return 0, iclass 40, count 2 2006.173.08:50:48.05#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.08:50:48.05#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.08:50:48.05#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.08:50:48.05#ibcon#ireg 7 cls_cnt 0 2006.173.08:50:48.05#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.08:50:48.17#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.08:50:48.17#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.08:50:48.17#ibcon#enter wrdev, iclass 40, count 0 2006.173.08:50:48.17#ibcon#first serial, iclass 40, count 0 2006.173.08:50:48.17#ibcon#enter sib2, iclass 40, count 0 2006.173.08:50:48.17#ibcon#flushed, iclass 40, count 0 2006.173.08:50:48.17#ibcon#about to write, iclass 40, count 0 2006.173.08:50:48.17#ibcon#wrote, iclass 40, count 0 2006.173.08:50:48.17#ibcon#about to read 3, iclass 40, count 0 2006.173.08:50:48.19#ibcon#read 3, iclass 40, count 0 2006.173.08:50:48.19#ibcon#about to read 4, iclass 40, count 0 2006.173.08:50:48.19#ibcon#read 4, iclass 40, count 0 2006.173.08:50:48.19#ibcon#about to read 5, iclass 40, count 0 2006.173.08:50:48.19#ibcon#read 5, iclass 40, count 0 2006.173.08:50:48.19#ibcon#about to read 6, iclass 40, count 0 2006.173.08:50:48.19#ibcon#read 6, iclass 40, count 0 2006.173.08:50:48.19#ibcon#end of sib2, iclass 40, count 0 2006.173.08:50:48.19#ibcon#*mode == 0, iclass 40, count 0 2006.173.08:50:48.19#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.08:50:48.19#ibcon#[27=USB\r\n] 2006.173.08:50:48.19#ibcon#*before write, iclass 40, count 0 2006.173.08:50:48.19#ibcon#enter sib2, iclass 40, count 0 2006.173.08:50:48.19#ibcon#flushed, iclass 40, count 0 2006.173.08:50:48.19#ibcon#about to write, iclass 40, count 0 2006.173.08:50:48.19#ibcon#wrote, iclass 40, count 0 2006.173.08:50:48.19#ibcon#about to read 3, iclass 40, count 0 2006.173.08:50:48.22#ibcon#read 3, iclass 40, count 0 2006.173.08:50:48.22#ibcon#about to read 4, iclass 40, count 0 2006.173.08:50:48.22#ibcon#read 4, iclass 40, count 0 2006.173.08:50:48.22#ibcon#about to read 5, iclass 40, count 0 2006.173.08:50:48.22#ibcon#read 5, iclass 40, count 0 2006.173.08:50:48.22#ibcon#about to read 6, iclass 40, count 0 2006.173.08:50:48.22#ibcon#read 6, iclass 40, count 0 2006.173.08:50:48.22#ibcon#end of sib2, iclass 40, count 0 2006.173.08:50:48.22#ibcon#*after write, iclass 40, count 0 2006.173.08:50:48.22#ibcon#*before return 0, iclass 40, count 0 2006.173.08:50:48.22#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.08:50:48.22#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.08:50:48.22#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.08:50:48.22#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.08:50:48.22$vck44/vblo=8,744.99 2006.173.08:50:48.22#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.08:50:48.22#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.08:50:48.22#ibcon#ireg 17 cls_cnt 0 2006.173.08:50:48.22#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.08:50:48.22#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.08:50:48.22#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.08:50:48.22#ibcon#enter wrdev, iclass 4, count 0 2006.173.08:50:48.22#ibcon#first serial, iclass 4, count 0 2006.173.08:50:48.22#ibcon#enter sib2, iclass 4, count 0 2006.173.08:50:48.22#ibcon#flushed, iclass 4, count 0 2006.173.08:50:48.22#ibcon#about to write, iclass 4, count 0 2006.173.08:50:48.22#ibcon#wrote, iclass 4, count 0 2006.173.08:50:48.22#ibcon#about to read 3, iclass 4, count 0 2006.173.08:50:48.24#ibcon#read 3, iclass 4, count 0 2006.173.08:50:48.24#ibcon#about to read 4, iclass 4, count 0 2006.173.08:50:48.24#ibcon#read 4, iclass 4, count 0 2006.173.08:50:48.24#ibcon#about to read 5, iclass 4, count 0 2006.173.08:50:48.24#ibcon#read 5, iclass 4, count 0 2006.173.08:50:48.24#ibcon#about to read 6, iclass 4, count 0 2006.173.08:50:48.24#ibcon#read 6, iclass 4, count 0 2006.173.08:50:48.24#ibcon#end of sib2, iclass 4, count 0 2006.173.08:50:48.24#ibcon#*mode == 0, iclass 4, count 0 2006.173.08:50:48.24#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.08:50:48.24#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.08:50:48.24#ibcon#*before write, iclass 4, count 0 2006.173.08:50:48.24#ibcon#enter sib2, iclass 4, count 0 2006.173.08:50:48.24#ibcon#flushed, iclass 4, count 0 2006.173.08:50:48.24#ibcon#about to write, iclass 4, count 0 2006.173.08:50:48.24#ibcon#wrote, iclass 4, count 0 2006.173.08:50:48.24#ibcon#about to read 3, iclass 4, count 0 2006.173.08:50:48.28#ibcon#read 3, iclass 4, count 0 2006.173.08:50:48.28#ibcon#about to read 4, iclass 4, count 0 2006.173.08:50:48.28#ibcon#read 4, iclass 4, count 0 2006.173.08:50:48.28#ibcon#about to read 5, iclass 4, count 0 2006.173.08:50:48.28#ibcon#read 5, iclass 4, count 0 2006.173.08:50:48.28#ibcon#about to read 6, iclass 4, count 0 2006.173.08:50:48.28#ibcon#read 6, iclass 4, count 0 2006.173.08:50:48.28#ibcon#end of sib2, iclass 4, count 0 2006.173.08:50:48.28#ibcon#*after write, iclass 4, count 0 2006.173.08:50:48.28#ibcon#*before return 0, iclass 4, count 0 2006.173.08:50:48.28#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.08:50:48.28#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.08:50:48.28#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.08:50:48.28#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.08:50:48.28$vck44/vb=8,4 2006.173.08:50:48.28#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.08:50:48.28#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.08:50:48.28#ibcon#ireg 11 cls_cnt 2 2006.173.08:50:48.28#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.08:50:48.34#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.08:50:48.34#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.08:50:48.34#ibcon#enter wrdev, iclass 6, count 2 2006.173.08:50:48.34#ibcon#first serial, iclass 6, count 2 2006.173.08:50:48.34#ibcon#enter sib2, iclass 6, count 2 2006.173.08:50:48.34#ibcon#flushed, iclass 6, count 2 2006.173.08:50:48.34#ibcon#about to write, iclass 6, count 2 2006.173.08:50:48.34#ibcon#wrote, iclass 6, count 2 2006.173.08:50:48.34#ibcon#about to read 3, iclass 6, count 2 2006.173.08:50:48.36#ibcon#read 3, iclass 6, count 2 2006.173.08:50:48.36#ibcon#about to read 4, iclass 6, count 2 2006.173.08:50:48.36#ibcon#read 4, iclass 6, count 2 2006.173.08:50:48.36#ibcon#about to read 5, iclass 6, count 2 2006.173.08:50:48.36#ibcon#read 5, iclass 6, count 2 2006.173.08:50:48.36#ibcon#about to read 6, iclass 6, count 2 2006.173.08:50:48.36#ibcon#read 6, iclass 6, count 2 2006.173.08:50:48.36#ibcon#end of sib2, iclass 6, count 2 2006.173.08:50:48.36#ibcon#*mode == 0, iclass 6, count 2 2006.173.08:50:48.36#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.08:50:48.36#ibcon#[27=AT08-04\r\n] 2006.173.08:50:48.36#ibcon#*before write, iclass 6, count 2 2006.173.08:50:48.36#ibcon#enter sib2, iclass 6, count 2 2006.173.08:50:48.36#ibcon#flushed, iclass 6, count 2 2006.173.08:50:48.36#ibcon#about to write, iclass 6, count 2 2006.173.08:50:48.36#ibcon#wrote, iclass 6, count 2 2006.173.08:50:48.36#ibcon#about to read 3, iclass 6, count 2 2006.173.08:50:48.39#ibcon#read 3, iclass 6, count 2 2006.173.08:50:48.39#ibcon#about to read 4, iclass 6, count 2 2006.173.08:50:48.39#ibcon#read 4, iclass 6, count 2 2006.173.08:50:48.39#ibcon#about to read 5, iclass 6, count 2 2006.173.08:50:48.39#ibcon#read 5, iclass 6, count 2 2006.173.08:50:48.39#ibcon#about to read 6, iclass 6, count 2 2006.173.08:50:48.39#ibcon#read 6, iclass 6, count 2 2006.173.08:50:48.39#ibcon#end of sib2, iclass 6, count 2 2006.173.08:50:48.39#ibcon#*after write, iclass 6, count 2 2006.173.08:50:48.39#ibcon#*before return 0, iclass 6, count 2 2006.173.08:50:48.39#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.08:50:48.39#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.08:50:48.39#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.08:50:48.39#ibcon#ireg 7 cls_cnt 0 2006.173.08:50:48.39#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.08:50:48.51#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.08:50:48.51#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.08:50:48.51#ibcon#enter wrdev, iclass 6, count 0 2006.173.08:50:48.51#ibcon#first serial, iclass 6, count 0 2006.173.08:50:48.51#ibcon#enter sib2, iclass 6, count 0 2006.173.08:50:48.51#ibcon#flushed, iclass 6, count 0 2006.173.08:50:48.51#ibcon#about to write, iclass 6, count 0 2006.173.08:50:48.51#ibcon#wrote, iclass 6, count 0 2006.173.08:50:48.51#ibcon#about to read 3, iclass 6, count 0 2006.173.08:50:48.53#ibcon#read 3, iclass 6, count 0 2006.173.08:50:48.53#ibcon#about to read 4, iclass 6, count 0 2006.173.08:50:48.53#ibcon#read 4, iclass 6, count 0 2006.173.08:50:48.53#ibcon#about to read 5, iclass 6, count 0 2006.173.08:50:48.53#ibcon#read 5, iclass 6, count 0 2006.173.08:50:48.53#ibcon#about to read 6, iclass 6, count 0 2006.173.08:50:48.53#ibcon#read 6, iclass 6, count 0 2006.173.08:50:48.53#ibcon#end of sib2, iclass 6, count 0 2006.173.08:50:48.53#ibcon#*mode == 0, iclass 6, count 0 2006.173.08:50:48.53#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.08:50:48.53#ibcon#[27=USB\r\n] 2006.173.08:50:48.53#ibcon#*before write, iclass 6, count 0 2006.173.08:50:48.53#ibcon#enter sib2, iclass 6, count 0 2006.173.08:50:48.53#ibcon#flushed, iclass 6, count 0 2006.173.08:50:48.53#ibcon#about to write, iclass 6, count 0 2006.173.08:50:48.53#ibcon#wrote, iclass 6, count 0 2006.173.08:50:48.53#ibcon#about to read 3, iclass 6, count 0 2006.173.08:50:48.56#ibcon#read 3, iclass 6, count 0 2006.173.08:50:48.56#ibcon#about to read 4, iclass 6, count 0 2006.173.08:50:48.56#ibcon#read 4, iclass 6, count 0 2006.173.08:50:48.56#ibcon#about to read 5, iclass 6, count 0 2006.173.08:50:48.56#ibcon#read 5, iclass 6, count 0 2006.173.08:50:48.56#ibcon#about to read 6, iclass 6, count 0 2006.173.08:50:48.56#ibcon#read 6, iclass 6, count 0 2006.173.08:50:48.56#ibcon#end of sib2, iclass 6, count 0 2006.173.08:50:48.56#ibcon#*after write, iclass 6, count 0 2006.173.08:50:48.56#ibcon#*before return 0, iclass 6, count 0 2006.173.08:50:48.56#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.08:50:48.56#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.08:50:48.56#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.08:50:48.56#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.08:50:48.56$vck44/vabw=wide 2006.173.08:50:48.56#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.08:50:48.56#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.08:50:48.56#ibcon#ireg 8 cls_cnt 0 2006.173.08:50:48.56#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.08:50:48.56#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.08:50:48.56#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.08:50:48.56#ibcon#enter wrdev, iclass 10, count 0 2006.173.08:50:48.56#ibcon#first serial, iclass 10, count 0 2006.173.08:50:48.56#ibcon#enter sib2, iclass 10, count 0 2006.173.08:50:48.56#ibcon#flushed, iclass 10, count 0 2006.173.08:50:48.56#ibcon#about to write, iclass 10, count 0 2006.173.08:50:48.56#ibcon#wrote, iclass 10, count 0 2006.173.08:50:48.56#ibcon#about to read 3, iclass 10, count 0 2006.173.08:50:48.58#ibcon#read 3, iclass 10, count 0 2006.173.08:50:48.58#ibcon#about to read 4, iclass 10, count 0 2006.173.08:50:48.58#ibcon#read 4, iclass 10, count 0 2006.173.08:50:48.58#ibcon#about to read 5, iclass 10, count 0 2006.173.08:50:48.58#ibcon#read 5, iclass 10, count 0 2006.173.08:50:48.58#ibcon#about to read 6, iclass 10, count 0 2006.173.08:50:48.58#ibcon#read 6, iclass 10, count 0 2006.173.08:50:48.58#ibcon#end of sib2, iclass 10, count 0 2006.173.08:50:48.58#ibcon#*mode == 0, iclass 10, count 0 2006.173.08:50:48.58#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.08:50:48.58#ibcon#[25=BW32\r\n] 2006.173.08:50:48.58#ibcon#*before write, iclass 10, count 0 2006.173.08:50:48.58#ibcon#enter sib2, iclass 10, count 0 2006.173.08:50:48.58#ibcon#flushed, iclass 10, count 0 2006.173.08:50:48.58#ibcon#about to write, iclass 10, count 0 2006.173.08:50:48.58#ibcon#wrote, iclass 10, count 0 2006.173.08:50:48.58#ibcon#about to read 3, iclass 10, count 0 2006.173.08:50:48.61#ibcon#read 3, iclass 10, count 0 2006.173.08:50:48.61#ibcon#about to read 4, iclass 10, count 0 2006.173.08:50:48.61#ibcon#read 4, iclass 10, count 0 2006.173.08:50:48.61#ibcon#about to read 5, iclass 10, count 0 2006.173.08:50:48.61#ibcon#read 5, iclass 10, count 0 2006.173.08:50:48.61#ibcon#about to read 6, iclass 10, count 0 2006.173.08:50:48.61#ibcon#read 6, iclass 10, count 0 2006.173.08:50:48.61#ibcon#end of sib2, iclass 10, count 0 2006.173.08:50:48.61#ibcon#*after write, iclass 10, count 0 2006.173.08:50:48.61#ibcon#*before return 0, iclass 10, count 0 2006.173.08:50:48.61#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.08:50:48.61#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.08:50:48.61#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.08:50:48.61#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.08:50:48.61$vck44/vbbw=wide 2006.173.08:50:48.61#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.08:50:48.61#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.08:50:48.61#ibcon#ireg 8 cls_cnt 0 2006.173.08:50:48.61#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.08:50:48.68#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.08:50:48.68#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.08:50:48.68#ibcon#enter wrdev, iclass 12, count 0 2006.173.08:50:48.68#ibcon#first serial, iclass 12, count 0 2006.173.08:50:48.68#ibcon#enter sib2, iclass 12, count 0 2006.173.08:50:48.68#ibcon#flushed, iclass 12, count 0 2006.173.08:50:48.68#ibcon#about to write, iclass 12, count 0 2006.173.08:50:48.68#ibcon#wrote, iclass 12, count 0 2006.173.08:50:48.68#ibcon#about to read 3, iclass 12, count 0 2006.173.08:50:48.70#ibcon#read 3, iclass 12, count 0 2006.173.08:50:48.70#ibcon#about to read 4, iclass 12, count 0 2006.173.08:50:48.70#ibcon#read 4, iclass 12, count 0 2006.173.08:50:48.70#ibcon#about to read 5, iclass 12, count 0 2006.173.08:50:48.70#ibcon#read 5, iclass 12, count 0 2006.173.08:50:48.70#ibcon#about to read 6, iclass 12, count 0 2006.173.08:50:48.70#ibcon#read 6, iclass 12, count 0 2006.173.08:50:48.70#ibcon#end of sib2, iclass 12, count 0 2006.173.08:50:48.70#ibcon#*mode == 0, iclass 12, count 0 2006.173.08:50:48.70#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.08:50:48.70#ibcon#[27=BW32\r\n] 2006.173.08:50:48.70#ibcon#*before write, iclass 12, count 0 2006.173.08:50:48.70#ibcon#enter sib2, iclass 12, count 0 2006.173.08:50:48.70#ibcon#flushed, iclass 12, count 0 2006.173.08:50:48.70#ibcon#about to write, iclass 12, count 0 2006.173.08:50:48.70#ibcon#wrote, iclass 12, count 0 2006.173.08:50:48.70#ibcon#about to read 3, iclass 12, count 0 2006.173.08:50:48.73#ibcon#read 3, iclass 12, count 0 2006.173.08:50:48.73#ibcon#about to read 4, iclass 12, count 0 2006.173.08:50:48.73#ibcon#read 4, iclass 12, count 0 2006.173.08:50:48.73#ibcon#about to read 5, iclass 12, count 0 2006.173.08:50:48.73#ibcon#read 5, iclass 12, count 0 2006.173.08:50:48.73#ibcon#about to read 6, iclass 12, count 0 2006.173.08:50:48.73#ibcon#read 6, iclass 12, count 0 2006.173.08:50:48.73#ibcon#end of sib2, iclass 12, count 0 2006.173.08:50:48.73#ibcon#*after write, iclass 12, count 0 2006.173.08:50:48.73#ibcon#*before return 0, iclass 12, count 0 2006.173.08:50:48.73#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.08:50:48.73#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.08:50:48.73#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.08:50:48.73#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.08:50:48.73$setupk4/ifdk4 2006.173.08:50:48.73$ifdk4/lo= 2006.173.08:50:48.73$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.08:50:48.73$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.08:50:48.73$ifdk4/patch= 2006.173.08:50:48.73$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.08:50:48.73$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.08:50:48.73$setupk4/!*+20s 2006.173.08:50:57.42#abcon#<5=/02 0.5 1.0 23.12 861004.1\r\n> 2006.173.08:50:57.44#abcon#{5=INTERFACE CLEAR} 2006.173.08:50:57.50#abcon#[5=S1D000X0/0*\r\n] 2006.173.08:51:03.24$setupk4/"tpicd 2006.173.08:51:03.24$setupk4/echo=off 2006.173.08:51:03.24$setupk4/xlog=off 2006.173.08:51:03.24:!2006.173.08:55:51 2006.173.08:52:06.13#trakl#Source acquired 2006.173.08:52:06.13#flagr#flagr/antenna,acquired 2006.173.08:55:51.00:preob 2006.173.08:55:52.14/onsource/TRACKING 2006.173.08:55:52.14:!2006.173.08:56:01 2006.173.08:56:01.00:"tape 2006.173.08:56:01.00:"st=record 2006.173.08:56:01.00:data_valid=on 2006.173.08:56:01.01:midob 2006.173.08:56:02.14/onsource/TRACKING 2006.173.08:56:02.14/wx/23.10,1004.3,87 2006.173.08:56:02.24/cable/+6.5012E-03 2006.173.08:56:03.33/va/01,07,usb,yes,36,39 2006.173.08:56:03.33/va/02,06,usb,yes,36,36 2006.173.08:56:03.33/va/03,05,usb,yes,45,47 2006.173.08:56:03.33/va/04,06,usb,yes,36,38 2006.173.08:56:03.33/va/05,04,usb,yes,28,29 2006.173.08:56:03.33/va/06,03,usb,yes,40,40 2006.173.08:56:03.33/va/07,04,usb,yes,32,34 2006.173.08:56:03.33/va/08,04,usb,yes,27,33 2006.173.08:56:03.56/valo/01,524.99,yes,locked 2006.173.08:56:03.56/valo/02,534.99,yes,locked 2006.173.08:56:03.56/valo/03,564.99,yes,locked 2006.173.08:56:03.56/valo/04,624.99,yes,locked 2006.173.08:56:03.56/valo/05,734.99,yes,locked 2006.173.08:56:03.56/valo/06,814.99,yes,locked 2006.173.08:56:03.56/valo/07,864.99,yes,locked 2006.173.08:56:03.56/valo/08,884.99,yes,locked 2006.173.08:56:04.65/vb/01,04,usb,yes,29,30 2006.173.08:56:04.65/vb/02,04,usb,yes,31,33 2006.173.08:56:04.65/vb/03,04,usb,yes,28,31 2006.173.08:56:04.65/vb/04,04,usb,yes,32,31 2006.173.08:56:04.65/vb/05,04,usb,yes,26,28 2006.173.08:56:04.65/vb/06,04,usb,yes,30,26 2006.173.08:56:04.65/vb/07,04,usb,yes,30,29 2006.173.08:56:04.65/vb/08,04,usb,yes,27,30 2006.173.08:56:04.88/vblo/01,629.99,yes,locked 2006.173.08:56:04.88/vblo/02,634.99,yes,locked 2006.173.08:56:04.88/vblo/03,649.99,yes,locked 2006.173.08:56:04.88/vblo/04,679.99,yes,locked 2006.173.08:56:04.88/vblo/05,709.99,yes,locked 2006.173.08:56:04.88/vblo/06,719.99,yes,locked 2006.173.08:56:04.88/vblo/07,734.99,yes,locked 2006.173.08:56:04.88/vblo/08,744.99,yes,locked 2006.173.08:56:05.03/vabw/8 2006.173.08:56:05.18/vbbw/8 2006.173.08:56:05.27/xfe/off,on,14.7 2006.173.08:56:05.66/ifatt/23,28,28,28 2006.173.08:56:06.07/fmout-gps/S +4.00E-07 2006.173.08:56:06.11:!2006.173.08:59:51 2006.173.08:59:51.00:data_valid=off 2006.173.08:59:51.00:"et 2006.173.08:59:51.00:!+3s 2006.173.08:59:54.02:"tape 2006.173.08:59:54.02:postob 2006.173.08:59:54.17/cable/+6.5029E-03 2006.173.08:59:54.17/wx/23.06,1004.4,87 2006.173.08:59:55.08/fmout-gps/S +4.01E-07 2006.173.08:59:55.08:scan_name=173-0909,jd0606,60 2006.173.08:59:55.08:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.173.08:59:56.13#flagr#flagr/antenna,new-source 2006.173.08:59:56.13:checkk5 2006.173.08:59:56.53/chk_autoobs//k5ts1/ autoobs is running! 2006.173.08:59:56.91/chk_autoobs//k5ts2/ autoobs is running! 2006.173.08:59:57.34/chk_autoobs//k5ts3/ autoobs is running! 2006.173.08:59:57.75/chk_autoobs//k5ts4/ autoobs is running! 2006.173.08:59:58.13/chk_obsdata//k5ts1/T1730856??a.dat file size is correct (nominal:920MB, actual:920MB). 2006.173.08:59:58.53/chk_obsdata//k5ts2/T1730856??b.dat file size is correct (nominal:920MB, actual:920MB). 2006.173.08:59:58.94/chk_obsdata//k5ts3/T1730856??c.dat file size is correct (nominal:920MB, actual:920MB). 2006.173.08:59:59.33/chk_obsdata//k5ts4/T1730856??d.dat file size is correct (nominal:920MB, actual:920MB). 2006.173.09:00:00.06/k5log//k5ts1_log_newline 2006.173.09:00:00.79/k5log//k5ts2_log_newline 2006.173.09:00:01.50/k5log//k5ts3_log_newline 2006.173.09:00:02.21/k5log//k5ts4_log_newline 2006.173.09:00:02.23/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.09:00:02.23:setupk4=1 2006.173.09:00:02.23$setupk4/echo=on 2006.173.09:00:02.23$setupk4/pcalon 2006.173.09:00:02.24$pcalon/"no phase cal control is implemented here 2006.173.09:00:02.24$setupk4/"tpicd=stop 2006.173.09:00:02.24$setupk4/"rec=synch_on 2006.173.09:00:02.24$setupk4/"rec_mode=128 2006.173.09:00:02.24$setupk4/!* 2006.173.09:00:02.24$setupk4/recpk4 2006.173.09:00:02.24$recpk4/recpatch= 2006.173.09:00:02.24$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.09:00:02.24$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.09:00:02.24$setupk4/vck44 2006.173.09:00:02.24$vck44/valo=1,524.99 2006.173.09:00:02.24#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.09:00:02.24#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.09:00:02.24#ibcon#ireg 17 cls_cnt 0 2006.173.09:00:02.24#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.09:00:02.24#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.09:00:02.24#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.09:00:02.24#ibcon#enter wrdev, iclass 17, count 0 2006.173.09:00:02.24#ibcon#first serial, iclass 17, count 0 2006.173.09:00:02.24#ibcon#enter sib2, iclass 17, count 0 2006.173.09:00:02.24#ibcon#flushed, iclass 17, count 0 2006.173.09:00:02.24#ibcon#about to write, iclass 17, count 0 2006.173.09:00:02.24#ibcon#wrote, iclass 17, count 0 2006.173.09:00:02.24#ibcon#about to read 3, iclass 17, count 0 2006.173.09:00:02.26#ibcon#read 3, iclass 17, count 0 2006.173.09:00:02.26#ibcon#about to read 4, iclass 17, count 0 2006.173.09:00:02.26#ibcon#read 4, iclass 17, count 0 2006.173.09:00:02.26#ibcon#about to read 5, iclass 17, count 0 2006.173.09:00:02.26#ibcon#read 5, iclass 17, count 0 2006.173.09:00:02.26#ibcon#about to read 6, iclass 17, count 0 2006.173.09:00:02.26#ibcon#read 6, iclass 17, count 0 2006.173.09:00:02.26#ibcon#end of sib2, iclass 17, count 0 2006.173.09:00:02.26#ibcon#*mode == 0, iclass 17, count 0 2006.173.09:00:02.26#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.09:00:02.26#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.09:00:02.26#ibcon#*before write, iclass 17, count 0 2006.173.09:00:02.26#ibcon#enter sib2, iclass 17, count 0 2006.173.09:00:02.26#ibcon#flushed, iclass 17, count 0 2006.173.09:00:02.26#ibcon#about to write, iclass 17, count 0 2006.173.09:00:02.26#ibcon#wrote, iclass 17, count 0 2006.173.09:00:02.26#ibcon#about to read 3, iclass 17, count 0 2006.173.09:00:02.31#ibcon#read 3, iclass 17, count 0 2006.173.09:00:02.31#ibcon#about to read 4, iclass 17, count 0 2006.173.09:00:02.31#ibcon#read 4, iclass 17, count 0 2006.173.09:00:02.31#ibcon#about to read 5, iclass 17, count 0 2006.173.09:00:02.31#ibcon#read 5, iclass 17, count 0 2006.173.09:00:02.31#ibcon#about to read 6, iclass 17, count 0 2006.173.09:00:02.31#ibcon#read 6, iclass 17, count 0 2006.173.09:00:02.31#ibcon#end of sib2, iclass 17, count 0 2006.173.09:00:02.31#ibcon#*after write, iclass 17, count 0 2006.173.09:00:02.31#ibcon#*before return 0, iclass 17, count 0 2006.173.09:00:02.31#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.09:00:02.31#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.09:00:02.31#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.09:00:02.31#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.09:00:02.31$vck44/va=1,7 2006.173.09:00:02.31#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.09:00:02.31#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.09:00:02.31#ibcon#ireg 11 cls_cnt 2 2006.173.09:00:02.31#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.09:00:02.31#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.09:00:02.31#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.09:00:02.31#ibcon#enter wrdev, iclass 19, count 2 2006.173.09:00:02.31#ibcon#first serial, iclass 19, count 2 2006.173.09:00:02.31#ibcon#enter sib2, iclass 19, count 2 2006.173.09:00:02.31#ibcon#flushed, iclass 19, count 2 2006.173.09:00:02.31#ibcon#about to write, iclass 19, count 2 2006.173.09:00:02.31#ibcon#wrote, iclass 19, count 2 2006.173.09:00:02.31#ibcon#about to read 3, iclass 19, count 2 2006.173.09:00:02.33#ibcon#read 3, iclass 19, count 2 2006.173.09:00:02.33#ibcon#about to read 4, iclass 19, count 2 2006.173.09:00:02.33#ibcon#read 4, iclass 19, count 2 2006.173.09:00:02.33#ibcon#about to read 5, iclass 19, count 2 2006.173.09:00:02.33#ibcon#read 5, iclass 19, count 2 2006.173.09:00:02.33#ibcon#about to read 6, iclass 19, count 2 2006.173.09:00:02.33#ibcon#read 6, iclass 19, count 2 2006.173.09:00:02.33#ibcon#end of sib2, iclass 19, count 2 2006.173.09:00:02.33#ibcon#*mode == 0, iclass 19, count 2 2006.173.09:00:02.33#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.09:00:02.33#ibcon#[25=AT01-07\r\n] 2006.173.09:00:02.33#ibcon#*before write, iclass 19, count 2 2006.173.09:00:02.33#ibcon#enter sib2, iclass 19, count 2 2006.173.09:00:02.33#ibcon#flushed, iclass 19, count 2 2006.173.09:00:02.33#ibcon#about to write, iclass 19, count 2 2006.173.09:00:02.33#ibcon#wrote, iclass 19, count 2 2006.173.09:00:02.33#ibcon#about to read 3, iclass 19, count 2 2006.173.09:00:02.36#ibcon#read 3, iclass 19, count 2 2006.173.09:00:02.36#ibcon#about to read 4, iclass 19, count 2 2006.173.09:00:02.36#ibcon#read 4, iclass 19, count 2 2006.173.09:00:02.36#ibcon#about to read 5, iclass 19, count 2 2006.173.09:00:02.36#ibcon#read 5, iclass 19, count 2 2006.173.09:00:02.36#ibcon#about to read 6, iclass 19, count 2 2006.173.09:00:02.36#ibcon#read 6, iclass 19, count 2 2006.173.09:00:02.36#ibcon#end of sib2, iclass 19, count 2 2006.173.09:00:02.36#ibcon#*after write, iclass 19, count 2 2006.173.09:00:02.36#ibcon#*before return 0, iclass 19, count 2 2006.173.09:00:02.36#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.09:00:02.36#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.09:00:02.36#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.09:00:02.36#ibcon#ireg 7 cls_cnt 0 2006.173.09:00:02.36#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.09:00:02.48#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.09:00:02.48#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.09:00:02.48#ibcon#enter wrdev, iclass 19, count 0 2006.173.09:00:02.48#ibcon#first serial, iclass 19, count 0 2006.173.09:00:02.48#ibcon#enter sib2, iclass 19, count 0 2006.173.09:00:02.48#ibcon#flushed, iclass 19, count 0 2006.173.09:00:02.48#ibcon#about to write, iclass 19, count 0 2006.173.09:00:02.48#ibcon#wrote, iclass 19, count 0 2006.173.09:00:02.48#ibcon#about to read 3, iclass 19, count 0 2006.173.09:00:02.50#ibcon#read 3, iclass 19, count 0 2006.173.09:00:02.50#ibcon#about to read 4, iclass 19, count 0 2006.173.09:00:02.50#ibcon#read 4, iclass 19, count 0 2006.173.09:00:02.50#ibcon#about to read 5, iclass 19, count 0 2006.173.09:00:02.50#ibcon#read 5, iclass 19, count 0 2006.173.09:00:02.50#ibcon#about to read 6, iclass 19, count 0 2006.173.09:00:02.50#ibcon#read 6, iclass 19, count 0 2006.173.09:00:02.50#ibcon#end of sib2, iclass 19, count 0 2006.173.09:00:02.50#ibcon#*mode == 0, iclass 19, count 0 2006.173.09:00:02.50#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.09:00:02.50#ibcon#[25=USB\r\n] 2006.173.09:00:02.50#ibcon#*before write, iclass 19, count 0 2006.173.09:00:02.50#ibcon#enter sib2, iclass 19, count 0 2006.173.09:00:02.50#ibcon#flushed, iclass 19, count 0 2006.173.09:00:02.50#ibcon#about to write, iclass 19, count 0 2006.173.09:00:02.50#ibcon#wrote, iclass 19, count 0 2006.173.09:00:02.50#ibcon#about to read 3, iclass 19, count 0 2006.173.09:00:02.53#ibcon#read 3, iclass 19, count 0 2006.173.09:00:02.53#ibcon#about to read 4, iclass 19, count 0 2006.173.09:00:02.53#ibcon#read 4, iclass 19, count 0 2006.173.09:00:02.53#ibcon#about to read 5, iclass 19, count 0 2006.173.09:00:02.53#ibcon#read 5, iclass 19, count 0 2006.173.09:00:02.53#ibcon#about to read 6, iclass 19, count 0 2006.173.09:00:02.53#ibcon#read 6, iclass 19, count 0 2006.173.09:00:02.53#ibcon#end of sib2, iclass 19, count 0 2006.173.09:00:02.53#ibcon#*after write, iclass 19, count 0 2006.173.09:00:02.53#ibcon#*before return 0, iclass 19, count 0 2006.173.09:00:02.53#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.09:00:02.53#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.09:00:02.53#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.09:00:02.53#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.09:00:02.53$vck44/valo=2,534.99 2006.173.09:00:02.53#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.09:00:02.53#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.09:00:02.53#ibcon#ireg 17 cls_cnt 0 2006.173.09:00:02.53#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.09:00:02.53#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.09:00:02.53#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.09:00:02.53#ibcon#enter wrdev, iclass 21, count 0 2006.173.09:00:02.53#ibcon#first serial, iclass 21, count 0 2006.173.09:00:02.53#ibcon#enter sib2, iclass 21, count 0 2006.173.09:00:02.53#ibcon#flushed, iclass 21, count 0 2006.173.09:00:02.53#ibcon#about to write, iclass 21, count 0 2006.173.09:00:02.53#ibcon#wrote, iclass 21, count 0 2006.173.09:00:02.53#ibcon#about to read 3, iclass 21, count 0 2006.173.09:00:02.55#ibcon#read 3, iclass 21, count 0 2006.173.09:00:02.55#ibcon#about to read 4, iclass 21, count 0 2006.173.09:00:02.55#ibcon#read 4, iclass 21, count 0 2006.173.09:00:02.55#ibcon#about to read 5, iclass 21, count 0 2006.173.09:00:02.55#ibcon#read 5, iclass 21, count 0 2006.173.09:00:02.55#ibcon#about to read 6, iclass 21, count 0 2006.173.09:00:02.55#ibcon#read 6, iclass 21, count 0 2006.173.09:00:02.55#ibcon#end of sib2, iclass 21, count 0 2006.173.09:00:02.55#ibcon#*mode == 0, iclass 21, count 0 2006.173.09:00:02.55#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.09:00:02.55#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.09:00:02.55#ibcon#*before write, iclass 21, count 0 2006.173.09:00:02.55#ibcon#enter sib2, iclass 21, count 0 2006.173.09:00:02.55#ibcon#flushed, iclass 21, count 0 2006.173.09:00:02.55#ibcon#about to write, iclass 21, count 0 2006.173.09:00:02.55#ibcon#wrote, iclass 21, count 0 2006.173.09:00:02.55#ibcon#about to read 3, iclass 21, count 0 2006.173.09:00:02.59#ibcon#read 3, iclass 21, count 0 2006.173.09:00:02.59#ibcon#about to read 4, iclass 21, count 0 2006.173.09:00:02.59#ibcon#read 4, iclass 21, count 0 2006.173.09:00:02.59#ibcon#about to read 5, iclass 21, count 0 2006.173.09:00:02.59#ibcon#read 5, iclass 21, count 0 2006.173.09:00:02.59#ibcon#about to read 6, iclass 21, count 0 2006.173.09:00:02.59#ibcon#read 6, iclass 21, count 0 2006.173.09:00:02.59#ibcon#end of sib2, iclass 21, count 0 2006.173.09:00:02.59#ibcon#*after write, iclass 21, count 0 2006.173.09:00:02.59#ibcon#*before return 0, iclass 21, count 0 2006.173.09:00:02.59#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.09:00:02.59#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.09:00:02.59#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.09:00:02.59#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.09:00:02.59$vck44/va=2,6 2006.173.09:00:02.59#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.09:00:02.59#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.09:00:02.59#ibcon#ireg 11 cls_cnt 2 2006.173.09:00:02.59#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.09:00:02.65#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.09:00:02.65#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.09:00:02.65#ibcon#enter wrdev, iclass 23, count 2 2006.173.09:00:02.65#ibcon#first serial, iclass 23, count 2 2006.173.09:00:02.65#ibcon#enter sib2, iclass 23, count 2 2006.173.09:00:02.65#ibcon#flushed, iclass 23, count 2 2006.173.09:00:02.65#ibcon#about to write, iclass 23, count 2 2006.173.09:00:02.65#ibcon#wrote, iclass 23, count 2 2006.173.09:00:02.65#ibcon#about to read 3, iclass 23, count 2 2006.173.09:00:02.67#ibcon#read 3, iclass 23, count 2 2006.173.09:00:02.67#ibcon#about to read 4, iclass 23, count 2 2006.173.09:00:02.67#ibcon#read 4, iclass 23, count 2 2006.173.09:00:02.67#ibcon#about to read 5, iclass 23, count 2 2006.173.09:00:02.67#ibcon#read 5, iclass 23, count 2 2006.173.09:00:02.67#ibcon#about to read 6, iclass 23, count 2 2006.173.09:00:02.67#ibcon#read 6, iclass 23, count 2 2006.173.09:00:02.67#ibcon#end of sib2, iclass 23, count 2 2006.173.09:00:02.67#ibcon#*mode == 0, iclass 23, count 2 2006.173.09:00:02.67#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.09:00:02.67#ibcon#[25=AT02-06\r\n] 2006.173.09:00:02.67#ibcon#*before write, iclass 23, count 2 2006.173.09:00:02.67#ibcon#enter sib2, iclass 23, count 2 2006.173.09:00:02.67#ibcon#flushed, iclass 23, count 2 2006.173.09:00:02.67#ibcon#about to write, iclass 23, count 2 2006.173.09:00:02.67#ibcon#wrote, iclass 23, count 2 2006.173.09:00:02.67#ibcon#about to read 3, iclass 23, count 2 2006.173.09:00:02.70#ibcon#read 3, iclass 23, count 2 2006.173.09:00:02.70#ibcon#about to read 4, iclass 23, count 2 2006.173.09:00:02.70#ibcon#read 4, iclass 23, count 2 2006.173.09:00:02.70#ibcon#about to read 5, iclass 23, count 2 2006.173.09:00:02.70#ibcon#read 5, iclass 23, count 2 2006.173.09:00:02.70#ibcon#about to read 6, iclass 23, count 2 2006.173.09:00:02.70#ibcon#read 6, iclass 23, count 2 2006.173.09:00:02.70#ibcon#end of sib2, iclass 23, count 2 2006.173.09:00:02.70#ibcon#*after write, iclass 23, count 2 2006.173.09:00:02.70#ibcon#*before return 0, iclass 23, count 2 2006.173.09:00:02.70#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.09:00:02.70#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.09:00:02.70#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.09:00:02.70#ibcon#ireg 7 cls_cnt 0 2006.173.09:00:02.70#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.09:00:02.82#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.09:00:02.82#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.09:00:02.82#ibcon#enter wrdev, iclass 23, count 0 2006.173.09:00:02.82#ibcon#first serial, iclass 23, count 0 2006.173.09:00:02.82#ibcon#enter sib2, iclass 23, count 0 2006.173.09:00:02.82#ibcon#flushed, iclass 23, count 0 2006.173.09:00:02.82#ibcon#about to write, iclass 23, count 0 2006.173.09:00:02.82#ibcon#wrote, iclass 23, count 0 2006.173.09:00:02.82#ibcon#about to read 3, iclass 23, count 0 2006.173.09:00:02.84#ibcon#read 3, iclass 23, count 0 2006.173.09:00:02.84#ibcon#about to read 4, iclass 23, count 0 2006.173.09:00:02.84#ibcon#read 4, iclass 23, count 0 2006.173.09:00:02.84#ibcon#about to read 5, iclass 23, count 0 2006.173.09:00:02.84#ibcon#read 5, iclass 23, count 0 2006.173.09:00:02.84#ibcon#about to read 6, iclass 23, count 0 2006.173.09:00:02.84#ibcon#read 6, iclass 23, count 0 2006.173.09:00:02.84#ibcon#end of sib2, iclass 23, count 0 2006.173.09:00:02.84#ibcon#*mode == 0, iclass 23, count 0 2006.173.09:00:02.84#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.09:00:02.84#ibcon#[25=USB\r\n] 2006.173.09:00:02.84#ibcon#*before write, iclass 23, count 0 2006.173.09:00:02.84#ibcon#enter sib2, iclass 23, count 0 2006.173.09:00:02.84#ibcon#flushed, iclass 23, count 0 2006.173.09:00:02.84#ibcon#about to write, iclass 23, count 0 2006.173.09:00:02.84#ibcon#wrote, iclass 23, count 0 2006.173.09:00:02.84#ibcon#about to read 3, iclass 23, count 0 2006.173.09:00:02.87#ibcon#read 3, iclass 23, count 0 2006.173.09:00:02.87#ibcon#about to read 4, iclass 23, count 0 2006.173.09:00:02.87#ibcon#read 4, iclass 23, count 0 2006.173.09:00:02.87#ibcon#about to read 5, iclass 23, count 0 2006.173.09:00:02.87#ibcon#read 5, iclass 23, count 0 2006.173.09:00:02.87#ibcon#about to read 6, iclass 23, count 0 2006.173.09:00:02.87#ibcon#read 6, iclass 23, count 0 2006.173.09:00:02.87#ibcon#end of sib2, iclass 23, count 0 2006.173.09:00:02.87#ibcon#*after write, iclass 23, count 0 2006.173.09:00:02.87#ibcon#*before return 0, iclass 23, count 0 2006.173.09:00:02.87#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.09:00:02.87#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.09:00:02.87#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.09:00:02.87#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.09:00:02.87$vck44/valo=3,564.99 2006.173.09:00:02.87#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.09:00:02.87#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.09:00:02.87#ibcon#ireg 17 cls_cnt 0 2006.173.09:00:02.87#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.09:00:02.87#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.09:00:02.87#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.09:00:02.87#ibcon#enter wrdev, iclass 25, count 0 2006.173.09:00:02.87#ibcon#first serial, iclass 25, count 0 2006.173.09:00:02.87#ibcon#enter sib2, iclass 25, count 0 2006.173.09:00:02.87#ibcon#flushed, iclass 25, count 0 2006.173.09:00:02.87#ibcon#about to write, iclass 25, count 0 2006.173.09:00:02.87#ibcon#wrote, iclass 25, count 0 2006.173.09:00:02.87#ibcon#about to read 3, iclass 25, count 0 2006.173.09:00:02.89#ibcon#read 3, iclass 25, count 0 2006.173.09:00:02.89#ibcon#about to read 4, iclass 25, count 0 2006.173.09:00:02.89#ibcon#read 4, iclass 25, count 0 2006.173.09:00:02.89#ibcon#about to read 5, iclass 25, count 0 2006.173.09:00:02.89#ibcon#read 5, iclass 25, count 0 2006.173.09:00:02.89#ibcon#about to read 6, iclass 25, count 0 2006.173.09:00:02.89#ibcon#read 6, iclass 25, count 0 2006.173.09:00:02.89#ibcon#end of sib2, iclass 25, count 0 2006.173.09:00:02.89#ibcon#*mode == 0, iclass 25, count 0 2006.173.09:00:02.89#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.09:00:02.89#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.09:00:02.89#ibcon#*before write, iclass 25, count 0 2006.173.09:00:02.89#ibcon#enter sib2, iclass 25, count 0 2006.173.09:00:02.89#ibcon#flushed, iclass 25, count 0 2006.173.09:00:02.89#ibcon#about to write, iclass 25, count 0 2006.173.09:00:02.89#ibcon#wrote, iclass 25, count 0 2006.173.09:00:02.89#ibcon#about to read 3, iclass 25, count 0 2006.173.09:00:02.93#ibcon#read 3, iclass 25, count 0 2006.173.09:00:02.93#ibcon#about to read 4, iclass 25, count 0 2006.173.09:00:02.93#ibcon#read 4, iclass 25, count 0 2006.173.09:00:02.93#ibcon#about to read 5, iclass 25, count 0 2006.173.09:00:02.93#ibcon#read 5, iclass 25, count 0 2006.173.09:00:02.93#ibcon#about to read 6, iclass 25, count 0 2006.173.09:00:02.93#ibcon#read 6, iclass 25, count 0 2006.173.09:00:02.93#ibcon#end of sib2, iclass 25, count 0 2006.173.09:00:02.93#ibcon#*after write, iclass 25, count 0 2006.173.09:00:02.93#ibcon#*before return 0, iclass 25, count 0 2006.173.09:00:02.93#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.09:00:02.93#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.09:00:02.93#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.09:00:02.93#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.09:00:02.93$vck44/va=3,5 2006.173.09:00:02.93#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.09:00:02.93#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.09:00:02.93#ibcon#ireg 11 cls_cnt 2 2006.173.09:00:02.93#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.09:00:02.99#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.09:00:02.99#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.09:00:02.99#ibcon#enter wrdev, iclass 27, count 2 2006.173.09:00:02.99#ibcon#first serial, iclass 27, count 2 2006.173.09:00:02.99#ibcon#enter sib2, iclass 27, count 2 2006.173.09:00:02.99#ibcon#flushed, iclass 27, count 2 2006.173.09:00:02.99#ibcon#about to write, iclass 27, count 2 2006.173.09:00:02.99#ibcon#wrote, iclass 27, count 2 2006.173.09:00:02.99#ibcon#about to read 3, iclass 27, count 2 2006.173.09:00:03.01#ibcon#read 3, iclass 27, count 2 2006.173.09:00:03.01#ibcon#about to read 4, iclass 27, count 2 2006.173.09:00:03.01#ibcon#read 4, iclass 27, count 2 2006.173.09:00:03.01#ibcon#about to read 5, iclass 27, count 2 2006.173.09:00:03.01#ibcon#read 5, iclass 27, count 2 2006.173.09:00:03.01#ibcon#about to read 6, iclass 27, count 2 2006.173.09:00:03.01#ibcon#read 6, iclass 27, count 2 2006.173.09:00:03.01#ibcon#end of sib2, iclass 27, count 2 2006.173.09:00:03.01#ibcon#*mode == 0, iclass 27, count 2 2006.173.09:00:03.01#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.09:00:03.01#ibcon#[25=AT03-05\r\n] 2006.173.09:00:03.01#ibcon#*before write, iclass 27, count 2 2006.173.09:00:03.01#ibcon#enter sib2, iclass 27, count 2 2006.173.09:00:03.01#ibcon#flushed, iclass 27, count 2 2006.173.09:00:03.01#ibcon#about to write, iclass 27, count 2 2006.173.09:00:03.01#ibcon#wrote, iclass 27, count 2 2006.173.09:00:03.01#ibcon#about to read 3, iclass 27, count 2 2006.173.09:00:03.04#ibcon#read 3, iclass 27, count 2 2006.173.09:00:03.04#ibcon#about to read 4, iclass 27, count 2 2006.173.09:00:03.04#ibcon#read 4, iclass 27, count 2 2006.173.09:00:03.04#ibcon#about to read 5, iclass 27, count 2 2006.173.09:00:03.04#ibcon#read 5, iclass 27, count 2 2006.173.09:00:03.04#ibcon#about to read 6, iclass 27, count 2 2006.173.09:00:03.04#ibcon#read 6, iclass 27, count 2 2006.173.09:00:03.04#ibcon#end of sib2, iclass 27, count 2 2006.173.09:00:03.04#ibcon#*after write, iclass 27, count 2 2006.173.09:00:03.04#ibcon#*before return 0, iclass 27, count 2 2006.173.09:00:03.04#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.09:00:03.04#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.09:00:03.04#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.09:00:03.04#ibcon#ireg 7 cls_cnt 0 2006.173.09:00:03.04#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.09:00:03.16#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.09:00:03.16#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.09:00:03.16#ibcon#enter wrdev, iclass 27, count 0 2006.173.09:00:03.16#ibcon#first serial, iclass 27, count 0 2006.173.09:00:03.16#ibcon#enter sib2, iclass 27, count 0 2006.173.09:00:03.16#ibcon#flushed, iclass 27, count 0 2006.173.09:00:03.16#ibcon#about to write, iclass 27, count 0 2006.173.09:00:03.16#ibcon#wrote, iclass 27, count 0 2006.173.09:00:03.16#ibcon#about to read 3, iclass 27, count 0 2006.173.09:00:03.18#ibcon#read 3, iclass 27, count 0 2006.173.09:00:03.18#ibcon#about to read 4, iclass 27, count 0 2006.173.09:00:03.18#ibcon#read 4, iclass 27, count 0 2006.173.09:00:03.18#ibcon#about to read 5, iclass 27, count 0 2006.173.09:00:03.18#ibcon#read 5, iclass 27, count 0 2006.173.09:00:03.18#ibcon#about to read 6, iclass 27, count 0 2006.173.09:00:03.18#ibcon#read 6, iclass 27, count 0 2006.173.09:00:03.18#ibcon#end of sib2, iclass 27, count 0 2006.173.09:00:03.18#ibcon#*mode == 0, iclass 27, count 0 2006.173.09:00:03.18#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.09:00:03.18#ibcon#[25=USB\r\n] 2006.173.09:00:03.18#ibcon#*before write, iclass 27, count 0 2006.173.09:00:03.18#ibcon#enter sib2, iclass 27, count 0 2006.173.09:00:03.18#ibcon#flushed, iclass 27, count 0 2006.173.09:00:03.18#ibcon#about to write, iclass 27, count 0 2006.173.09:00:03.18#ibcon#wrote, iclass 27, count 0 2006.173.09:00:03.18#ibcon#about to read 3, iclass 27, count 0 2006.173.09:00:03.21#ibcon#read 3, iclass 27, count 0 2006.173.09:00:03.21#ibcon#about to read 4, iclass 27, count 0 2006.173.09:00:03.21#ibcon#read 4, iclass 27, count 0 2006.173.09:00:03.21#ibcon#about to read 5, iclass 27, count 0 2006.173.09:00:03.21#ibcon#read 5, iclass 27, count 0 2006.173.09:00:03.21#ibcon#about to read 6, iclass 27, count 0 2006.173.09:00:03.21#ibcon#read 6, iclass 27, count 0 2006.173.09:00:03.21#ibcon#end of sib2, iclass 27, count 0 2006.173.09:00:03.21#ibcon#*after write, iclass 27, count 0 2006.173.09:00:03.21#ibcon#*before return 0, iclass 27, count 0 2006.173.09:00:03.21#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.09:00:03.21#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.09:00:03.21#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.09:00:03.21#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.09:00:03.21$vck44/valo=4,624.99 2006.173.09:00:03.21#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.09:00:03.21#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.09:00:03.21#ibcon#ireg 17 cls_cnt 0 2006.173.09:00:03.21#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.09:00:03.21#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.09:00:03.21#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.09:00:03.21#ibcon#enter wrdev, iclass 29, count 0 2006.173.09:00:03.21#ibcon#first serial, iclass 29, count 0 2006.173.09:00:03.21#ibcon#enter sib2, iclass 29, count 0 2006.173.09:00:03.21#ibcon#flushed, iclass 29, count 0 2006.173.09:00:03.21#ibcon#about to write, iclass 29, count 0 2006.173.09:00:03.21#ibcon#wrote, iclass 29, count 0 2006.173.09:00:03.21#ibcon#about to read 3, iclass 29, count 0 2006.173.09:00:03.23#ibcon#read 3, iclass 29, count 0 2006.173.09:00:03.23#ibcon#about to read 4, iclass 29, count 0 2006.173.09:00:03.23#ibcon#read 4, iclass 29, count 0 2006.173.09:00:03.23#ibcon#about to read 5, iclass 29, count 0 2006.173.09:00:03.23#ibcon#read 5, iclass 29, count 0 2006.173.09:00:03.23#ibcon#about to read 6, iclass 29, count 0 2006.173.09:00:03.23#ibcon#read 6, iclass 29, count 0 2006.173.09:00:03.23#ibcon#end of sib2, iclass 29, count 0 2006.173.09:00:03.23#ibcon#*mode == 0, iclass 29, count 0 2006.173.09:00:03.23#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.09:00:03.23#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.09:00:03.23#ibcon#*before write, iclass 29, count 0 2006.173.09:00:03.23#ibcon#enter sib2, iclass 29, count 0 2006.173.09:00:03.23#ibcon#flushed, iclass 29, count 0 2006.173.09:00:03.23#ibcon#about to write, iclass 29, count 0 2006.173.09:00:03.23#ibcon#wrote, iclass 29, count 0 2006.173.09:00:03.23#ibcon#about to read 3, iclass 29, count 0 2006.173.09:00:03.27#ibcon#read 3, iclass 29, count 0 2006.173.09:00:03.27#ibcon#about to read 4, iclass 29, count 0 2006.173.09:00:03.27#ibcon#read 4, iclass 29, count 0 2006.173.09:00:03.27#ibcon#about to read 5, iclass 29, count 0 2006.173.09:00:03.27#ibcon#read 5, iclass 29, count 0 2006.173.09:00:03.27#ibcon#about to read 6, iclass 29, count 0 2006.173.09:00:03.27#ibcon#read 6, iclass 29, count 0 2006.173.09:00:03.27#ibcon#end of sib2, iclass 29, count 0 2006.173.09:00:03.27#ibcon#*after write, iclass 29, count 0 2006.173.09:00:03.27#ibcon#*before return 0, iclass 29, count 0 2006.173.09:00:03.27#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.09:00:03.27#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.09:00:03.27#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.09:00:03.27#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.09:00:03.27$vck44/va=4,6 2006.173.09:00:03.27#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.09:00:03.27#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.09:00:03.27#ibcon#ireg 11 cls_cnt 2 2006.173.09:00:03.27#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.09:00:03.33#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.09:00:03.33#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.09:00:03.33#ibcon#enter wrdev, iclass 31, count 2 2006.173.09:00:03.33#ibcon#first serial, iclass 31, count 2 2006.173.09:00:03.33#ibcon#enter sib2, iclass 31, count 2 2006.173.09:00:03.33#ibcon#flushed, iclass 31, count 2 2006.173.09:00:03.33#ibcon#about to write, iclass 31, count 2 2006.173.09:00:03.33#ibcon#wrote, iclass 31, count 2 2006.173.09:00:03.33#ibcon#about to read 3, iclass 31, count 2 2006.173.09:00:03.35#ibcon#read 3, iclass 31, count 2 2006.173.09:00:03.35#ibcon#about to read 4, iclass 31, count 2 2006.173.09:00:03.35#ibcon#read 4, iclass 31, count 2 2006.173.09:00:03.35#ibcon#about to read 5, iclass 31, count 2 2006.173.09:00:03.35#ibcon#read 5, iclass 31, count 2 2006.173.09:00:03.35#ibcon#about to read 6, iclass 31, count 2 2006.173.09:00:03.35#ibcon#read 6, iclass 31, count 2 2006.173.09:00:03.35#ibcon#end of sib2, iclass 31, count 2 2006.173.09:00:03.35#ibcon#*mode == 0, iclass 31, count 2 2006.173.09:00:03.35#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.09:00:03.35#ibcon#[25=AT04-06\r\n] 2006.173.09:00:03.35#ibcon#*before write, iclass 31, count 2 2006.173.09:00:03.35#ibcon#enter sib2, iclass 31, count 2 2006.173.09:00:03.35#ibcon#flushed, iclass 31, count 2 2006.173.09:00:03.35#ibcon#about to write, iclass 31, count 2 2006.173.09:00:03.35#ibcon#wrote, iclass 31, count 2 2006.173.09:00:03.35#ibcon#about to read 3, iclass 31, count 2 2006.173.09:00:03.38#ibcon#read 3, iclass 31, count 2 2006.173.09:00:03.38#ibcon#about to read 4, iclass 31, count 2 2006.173.09:00:03.38#ibcon#read 4, iclass 31, count 2 2006.173.09:00:03.38#ibcon#about to read 5, iclass 31, count 2 2006.173.09:00:03.38#ibcon#read 5, iclass 31, count 2 2006.173.09:00:03.38#ibcon#about to read 6, iclass 31, count 2 2006.173.09:00:03.38#ibcon#read 6, iclass 31, count 2 2006.173.09:00:03.38#ibcon#end of sib2, iclass 31, count 2 2006.173.09:00:03.38#ibcon#*after write, iclass 31, count 2 2006.173.09:00:03.38#ibcon#*before return 0, iclass 31, count 2 2006.173.09:00:03.38#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.09:00:03.38#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.09:00:03.38#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.09:00:03.38#ibcon#ireg 7 cls_cnt 0 2006.173.09:00:03.38#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.09:00:03.50#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.09:00:03.50#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.09:00:03.50#ibcon#enter wrdev, iclass 31, count 0 2006.173.09:00:03.50#ibcon#first serial, iclass 31, count 0 2006.173.09:00:03.50#ibcon#enter sib2, iclass 31, count 0 2006.173.09:00:03.50#ibcon#flushed, iclass 31, count 0 2006.173.09:00:03.50#ibcon#about to write, iclass 31, count 0 2006.173.09:00:03.50#ibcon#wrote, iclass 31, count 0 2006.173.09:00:03.50#ibcon#about to read 3, iclass 31, count 0 2006.173.09:00:03.52#ibcon#read 3, iclass 31, count 0 2006.173.09:00:03.52#ibcon#about to read 4, iclass 31, count 0 2006.173.09:00:03.52#ibcon#read 4, iclass 31, count 0 2006.173.09:00:03.52#ibcon#about to read 5, iclass 31, count 0 2006.173.09:00:03.52#ibcon#read 5, iclass 31, count 0 2006.173.09:00:03.52#ibcon#about to read 6, iclass 31, count 0 2006.173.09:00:03.52#ibcon#read 6, iclass 31, count 0 2006.173.09:00:03.52#ibcon#end of sib2, iclass 31, count 0 2006.173.09:00:03.52#ibcon#*mode == 0, iclass 31, count 0 2006.173.09:00:03.52#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.09:00:03.52#ibcon#[25=USB\r\n] 2006.173.09:00:03.52#ibcon#*before write, iclass 31, count 0 2006.173.09:00:03.52#ibcon#enter sib2, iclass 31, count 0 2006.173.09:00:03.52#ibcon#flushed, iclass 31, count 0 2006.173.09:00:03.52#ibcon#about to write, iclass 31, count 0 2006.173.09:00:03.52#ibcon#wrote, iclass 31, count 0 2006.173.09:00:03.52#ibcon#about to read 3, iclass 31, count 0 2006.173.09:00:03.55#ibcon#read 3, iclass 31, count 0 2006.173.09:00:03.55#ibcon#about to read 4, iclass 31, count 0 2006.173.09:00:03.55#ibcon#read 4, iclass 31, count 0 2006.173.09:00:03.55#ibcon#about to read 5, iclass 31, count 0 2006.173.09:00:03.55#ibcon#read 5, iclass 31, count 0 2006.173.09:00:03.55#ibcon#about to read 6, iclass 31, count 0 2006.173.09:00:03.55#ibcon#read 6, iclass 31, count 0 2006.173.09:00:03.55#ibcon#end of sib2, iclass 31, count 0 2006.173.09:00:03.55#ibcon#*after write, iclass 31, count 0 2006.173.09:00:03.55#ibcon#*before return 0, iclass 31, count 0 2006.173.09:00:03.55#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.09:00:03.55#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.09:00:03.55#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.09:00:03.55#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.09:00:03.55$vck44/valo=5,734.99 2006.173.09:00:03.55#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.09:00:03.55#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.09:00:03.55#ibcon#ireg 17 cls_cnt 0 2006.173.09:00:03.55#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.09:00:03.55#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.09:00:03.55#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.09:00:03.55#ibcon#enter wrdev, iclass 33, count 0 2006.173.09:00:03.55#ibcon#first serial, iclass 33, count 0 2006.173.09:00:03.55#ibcon#enter sib2, iclass 33, count 0 2006.173.09:00:03.55#ibcon#flushed, iclass 33, count 0 2006.173.09:00:03.55#ibcon#about to write, iclass 33, count 0 2006.173.09:00:03.55#ibcon#wrote, iclass 33, count 0 2006.173.09:00:03.55#ibcon#about to read 3, iclass 33, count 0 2006.173.09:00:03.57#ibcon#read 3, iclass 33, count 0 2006.173.09:00:03.57#ibcon#about to read 4, iclass 33, count 0 2006.173.09:00:03.57#ibcon#read 4, iclass 33, count 0 2006.173.09:00:03.57#ibcon#about to read 5, iclass 33, count 0 2006.173.09:00:03.57#ibcon#read 5, iclass 33, count 0 2006.173.09:00:03.57#ibcon#about to read 6, iclass 33, count 0 2006.173.09:00:03.57#ibcon#read 6, iclass 33, count 0 2006.173.09:00:03.57#ibcon#end of sib2, iclass 33, count 0 2006.173.09:00:03.57#ibcon#*mode == 0, iclass 33, count 0 2006.173.09:00:03.57#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.09:00:03.57#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.09:00:03.57#ibcon#*before write, iclass 33, count 0 2006.173.09:00:03.57#ibcon#enter sib2, iclass 33, count 0 2006.173.09:00:03.57#ibcon#flushed, iclass 33, count 0 2006.173.09:00:03.57#ibcon#about to write, iclass 33, count 0 2006.173.09:00:03.57#ibcon#wrote, iclass 33, count 0 2006.173.09:00:03.57#ibcon#about to read 3, iclass 33, count 0 2006.173.09:00:03.61#ibcon#read 3, iclass 33, count 0 2006.173.09:00:03.61#ibcon#about to read 4, iclass 33, count 0 2006.173.09:00:03.61#ibcon#read 4, iclass 33, count 0 2006.173.09:00:03.61#ibcon#about to read 5, iclass 33, count 0 2006.173.09:00:03.61#ibcon#read 5, iclass 33, count 0 2006.173.09:00:03.61#ibcon#about to read 6, iclass 33, count 0 2006.173.09:00:03.61#ibcon#read 6, iclass 33, count 0 2006.173.09:00:03.61#ibcon#end of sib2, iclass 33, count 0 2006.173.09:00:03.61#ibcon#*after write, iclass 33, count 0 2006.173.09:00:03.61#ibcon#*before return 0, iclass 33, count 0 2006.173.09:00:03.61#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.09:00:03.61#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.09:00:03.61#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.09:00:03.61#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.09:00:03.61$vck44/va=5,4 2006.173.09:00:03.61#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.09:00:03.61#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.09:00:03.61#ibcon#ireg 11 cls_cnt 2 2006.173.09:00:03.61#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.09:00:03.67#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.09:00:03.67#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.09:00:03.67#ibcon#enter wrdev, iclass 35, count 2 2006.173.09:00:03.67#ibcon#first serial, iclass 35, count 2 2006.173.09:00:03.67#ibcon#enter sib2, iclass 35, count 2 2006.173.09:00:03.67#ibcon#flushed, iclass 35, count 2 2006.173.09:00:03.67#ibcon#about to write, iclass 35, count 2 2006.173.09:00:03.67#ibcon#wrote, iclass 35, count 2 2006.173.09:00:03.67#ibcon#about to read 3, iclass 35, count 2 2006.173.09:00:03.69#ibcon#read 3, iclass 35, count 2 2006.173.09:00:03.69#ibcon#about to read 4, iclass 35, count 2 2006.173.09:00:03.69#ibcon#read 4, iclass 35, count 2 2006.173.09:00:03.69#ibcon#about to read 5, iclass 35, count 2 2006.173.09:00:03.69#ibcon#read 5, iclass 35, count 2 2006.173.09:00:03.69#ibcon#about to read 6, iclass 35, count 2 2006.173.09:00:03.69#ibcon#read 6, iclass 35, count 2 2006.173.09:00:03.69#ibcon#end of sib2, iclass 35, count 2 2006.173.09:00:03.69#ibcon#*mode == 0, iclass 35, count 2 2006.173.09:00:03.69#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.09:00:03.69#ibcon#[25=AT05-04\r\n] 2006.173.09:00:03.69#ibcon#*before write, iclass 35, count 2 2006.173.09:00:03.69#ibcon#enter sib2, iclass 35, count 2 2006.173.09:00:03.69#ibcon#flushed, iclass 35, count 2 2006.173.09:00:03.69#ibcon#about to write, iclass 35, count 2 2006.173.09:00:03.69#ibcon#wrote, iclass 35, count 2 2006.173.09:00:03.69#ibcon#about to read 3, iclass 35, count 2 2006.173.09:00:03.72#ibcon#read 3, iclass 35, count 2 2006.173.09:00:03.97#ibcon#about to read 4, iclass 35, count 2 2006.173.09:00:03.97#ibcon#read 4, iclass 35, count 2 2006.173.09:00:03.97#ibcon#about to read 5, iclass 35, count 2 2006.173.09:00:03.97#ibcon#read 5, iclass 35, count 2 2006.173.09:00:03.97#ibcon#about to read 6, iclass 35, count 2 2006.173.09:00:03.97#ibcon#read 6, iclass 35, count 2 2006.173.09:00:03.97#ibcon#end of sib2, iclass 35, count 2 2006.173.09:00:03.97#ibcon#*after write, iclass 35, count 2 2006.173.09:00:03.97#ibcon#*before return 0, iclass 35, count 2 2006.173.09:00:03.97#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.09:00:03.97#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.09:00:03.97#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.09:00:03.97#ibcon#ireg 7 cls_cnt 0 2006.173.09:00:03.97#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.09:00:04.09#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.09:00:04.09#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.09:00:04.09#ibcon#enter wrdev, iclass 35, count 0 2006.173.09:00:04.09#ibcon#first serial, iclass 35, count 0 2006.173.09:00:04.09#ibcon#enter sib2, iclass 35, count 0 2006.173.09:00:04.09#ibcon#flushed, iclass 35, count 0 2006.173.09:00:04.09#ibcon#about to write, iclass 35, count 0 2006.173.09:00:04.09#ibcon#wrote, iclass 35, count 0 2006.173.09:00:04.09#ibcon#about to read 3, iclass 35, count 0 2006.173.09:00:04.11#ibcon#read 3, iclass 35, count 0 2006.173.09:00:04.11#ibcon#about to read 4, iclass 35, count 0 2006.173.09:00:04.11#ibcon#read 4, iclass 35, count 0 2006.173.09:00:04.11#ibcon#about to read 5, iclass 35, count 0 2006.173.09:00:04.11#ibcon#read 5, iclass 35, count 0 2006.173.09:00:04.11#ibcon#about to read 6, iclass 35, count 0 2006.173.09:00:04.11#ibcon#read 6, iclass 35, count 0 2006.173.09:00:04.11#ibcon#end of sib2, iclass 35, count 0 2006.173.09:00:04.11#ibcon#*mode == 0, iclass 35, count 0 2006.173.09:00:04.11#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.09:00:04.11#ibcon#[25=USB\r\n] 2006.173.09:00:04.11#ibcon#*before write, iclass 35, count 0 2006.173.09:00:04.11#ibcon#enter sib2, iclass 35, count 0 2006.173.09:00:04.11#ibcon#flushed, iclass 35, count 0 2006.173.09:00:04.11#ibcon#about to write, iclass 35, count 0 2006.173.09:00:04.11#ibcon#wrote, iclass 35, count 0 2006.173.09:00:04.11#ibcon#about to read 3, iclass 35, count 0 2006.173.09:00:04.14#ibcon#read 3, iclass 35, count 0 2006.173.09:00:04.14#ibcon#about to read 4, iclass 35, count 0 2006.173.09:00:04.14#ibcon#read 4, iclass 35, count 0 2006.173.09:00:04.14#ibcon#about to read 5, iclass 35, count 0 2006.173.09:00:04.14#ibcon#read 5, iclass 35, count 0 2006.173.09:00:04.14#ibcon#about to read 6, iclass 35, count 0 2006.173.09:00:04.14#ibcon#read 6, iclass 35, count 0 2006.173.09:00:04.14#ibcon#end of sib2, iclass 35, count 0 2006.173.09:00:04.14#ibcon#*after write, iclass 35, count 0 2006.173.09:00:04.14#ibcon#*before return 0, iclass 35, count 0 2006.173.09:00:04.14#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.09:00:04.14#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.09:00:04.14#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.09:00:04.14#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.09:00:04.14$vck44/valo=6,814.99 2006.173.09:00:04.14#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.09:00:04.14#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.09:00:04.14#ibcon#ireg 17 cls_cnt 0 2006.173.09:00:04.14#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.09:00:04.14#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.09:00:04.14#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.09:00:04.14#ibcon#enter wrdev, iclass 37, count 0 2006.173.09:00:04.14#ibcon#first serial, iclass 37, count 0 2006.173.09:00:04.14#ibcon#enter sib2, iclass 37, count 0 2006.173.09:00:04.14#ibcon#flushed, iclass 37, count 0 2006.173.09:00:04.14#ibcon#about to write, iclass 37, count 0 2006.173.09:00:04.14#ibcon#wrote, iclass 37, count 0 2006.173.09:00:04.14#ibcon#about to read 3, iclass 37, count 0 2006.173.09:00:04.16#ibcon#read 3, iclass 37, count 0 2006.173.09:00:04.16#ibcon#about to read 4, iclass 37, count 0 2006.173.09:00:04.16#ibcon#read 4, iclass 37, count 0 2006.173.09:00:04.16#ibcon#about to read 5, iclass 37, count 0 2006.173.09:00:04.16#ibcon#read 5, iclass 37, count 0 2006.173.09:00:04.16#ibcon#about to read 6, iclass 37, count 0 2006.173.09:00:04.16#ibcon#read 6, iclass 37, count 0 2006.173.09:00:04.16#ibcon#end of sib2, iclass 37, count 0 2006.173.09:00:04.16#ibcon#*mode == 0, iclass 37, count 0 2006.173.09:00:04.16#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.09:00:04.16#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.09:00:04.16#ibcon#*before write, iclass 37, count 0 2006.173.09:00:04.16#ibcon#enter sib2, iclass 37, count 0 2006.173.09:00:04.16#ibcon#flushed, iclass 37, count 0 2006.173.09:00:04.16#ibcon#about to write, iclass 37, count 0 2006.173.09:00:04.16#ibcon#wrote, iclass 37, count 0 2006.173.09:00:04.16#ibcon#about to read 3, iclass 37, count 0 2006.173.09:00:04.20#ibcon#read 3, iclass 37, count 0 2006.173.09:00:04.20#ibcon#about to read 4, iclass 37, count 0 2006.173.09:00:04.20#ibcon#read 4, iclass 37, count 0 2006.173.09:00:04.20#ibcon#about to read 5, iclass 37, count 0 2006.173.09:00:04.20#ibcon#read 5, iclass 37, count 0 2006.173.09:00:04.20#ibcon#about to read 6, iclass 37, count 0 2006.173.09:00:04.20#ibcon#read 6, iclass 37, count 0 2006.173.09:00:04.20#ibcon#end of sib2, iclass 37, count 0 2006.173.09:00:04.20#ibcon#*after write, iclass 37, count 0 2006.173.09:00:04.20#ibcon#*before return 0, iclass 37, count 0 2006.173.09:00:04.20#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.09:00:04.20#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.09:00:04.20#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.09:00:04.20#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.09:00:04.20$vck44/va=6,3 2006.173.09:00:04.20#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.09:00:04.20#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.09:00:04.20#ibcon#ireg 11 cls_cnt 2 2006.173.09:00:04.20#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.09:00:04.26#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.09:00:04.26#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.09:00:04.26#ibcon#enter wrdev, iclass 39, count 2 2006.173.09:00:04.26#ibcon#first serial, iclass 39, count 2 2006.173.09:00:04.26#ibcon#enter sib2, iclass 39, count 2 2006.173.09:00:04.26#ibcon#flushed, iclass 39, count 2 2006.173.09:00:04.26#ibcon#about to write, iclass 39, count 2 2006.173.09:00:04.26#ibcon#wrote, iclass 39, count 2 2006.173.09:00:04.26#ibcon#about to read 3, iclass 39, count 2 2006.173.09:00:04.28#ibcon#read 3, iclass 39, count 2 2006.173.09:00:04.28#ibcon#about to read 4, iclass 39, count 2 2006.173.09:00:04.28#ibcon#read 4, iclass 39, count 2 2006.173.09:00:04.28#ibcon#about to read 5, iclass 39, count 2 2006.173.09:00:04.28#ibcon#read 5, iclass 39, count 2 2006.173.09:00:04.28#ibcon#about to read 6, iclass 39, count 2 2006.173.09:00:04.28#ibcon#read 6, iclass 39, count 2 2006.173.09:00:04.28#ibcon#end of sib2, iclass 39, count 2 2006.173.09:00:04.28#ibcon#*mode == 0, iclass 39, count 2 2006.173.09:00:04.28#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.09:00:04.28#ibcon#[25=AT06-03\r\n] 2006.173.09:00:04.28#ibcon#*before write, iclass 39, count 2 2006.173.09:00:04.28#ibcon#enter sib2, iclass 39, count 2 2006.173.09:00:04.28#ibcon#flushed, iclass 39, count 2 2006.173.09:00:04.28#ibcon#about to write, iclass 39, count 2 2006.173.09:00:04.28#ibcon#wrote, iclass 39, count 2 2006.173.09:00:04.28#ibcon#about to read 3, iclass 39, count 2 2006.173.09:00:04.31#ibcon#read 3, iclass 39, count 2 2006.173.09:00:04.31#ibcon#about to read 4, iclass 39, count 2 2006.173.09:00:04.31#ibcon#read 4, iclass 39, count 2 2006.173.09:00:04.31#ibcon#about to read 5, iclass 39, count 2 2006.173.09:00:04.31#ibcon#read 5, iclass 39, count 2 2006.173.09:00:04.31#ibcon#about to read 6, iclass 39, count 2 2006.173.09:00:04.31#ibcon#read 6, iclass 39, count 2 2006.173.09:00:04.31#ibcon#end of sib2, iclass 39, count 2 2006.173.09:00:04.31#ibcon#*after write, iclass 39, count 2 2006.173.09:00:04.31#ibcon#*before return 0, iclass 39, count 2 2006.173.09:00:04.31#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.09:00:04.31#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.09:00:04.31#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.09:00:04.31#ibcon#ireg 7 cls_cnt 0 2006.173.09:00:04.31#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.09:00:04.43#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.09:00:04.43#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.09:00:04.43#ibcon#enter wrdev, iclass 39, count 0 2006.173.09:00:04.43#ibcon#first serial, iclass 39, count 0 2006.173.09:00:04.43#ibcon#enter sib2, iclass 39, count 0 2006.173.09:00:04.43#ibcon#flushed, iclass 39, count 0 2006.173.09:00:04.43#ibcon#about to write, iclass 39, count 0 2006.173.09:00:04.43#ibcon#wrote, iclass 39, count 0 2006.173.09:00:04.43#ibcon#about to read 3, iclass 39, count 0 2006.173.09:00:04.45#ibcon#read 3, iclass 39, count 0 2006.173.09:00:04.45#ibcon#about to read 4, iclass 39, count 0 2006.173.09:00:04.45#ibcon#read 4, iclass 39, count 0 2006.173.09:00:04.45#ibcon#about to read 5, iclass 39, count 0 2006.173.09:00:04.45#ibcon#read 5, iclass 39, count 0 2006.173.09:00:04.45#ibcon#about to read 6, iclass 39, count 0 2006.173.09:00:04.45#ibcon#read 6, iclass 39, count 0 2006.173.09:00:04.45#ibcon#end of sib2, iclass 39, count 0 2006.173.09:00:04.45#ibcon#*mode == 0, iclass 39, count 0 2006.173.09:00:04.45#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.09:00:04.45#ibcon#[25=USB\r\n] 2006.173.09:00:04.45#ibcon#*before write, iclass 39, count 0 2006.173.09:00:04.45#ibcon#enter sib2, iclass 39, count 0 2006.173.09:00:04.45#ibcon#flushed, iclass 39, count 0 2006.173.09:00:04.45#ibcon#about to write, iclass 39, count 0 2006.173.09:00:04.45#ibcon#wrote, iclass 39, count 0 2006.173.09:00:04.45#ibcon#about to read 3, iclass 39, count 0 2006.173.09:00:04.48#ibcon#read 3, iclass 39, count 0 2006.173.09:00:04.48#ibcon#about to read 4, iclass 39, count 0 2006.173.09:00:04.48#ibcon#read 4, iclass 39, count 0 2006.173.09:00:04.48#ibcon#about to read 5, iclass 39, count 0 2006.173.09:00:04.48#ibcon#read 5, iclass 39, count 0 2006.173.09:00:04.48#ibcon#about to read 6, iclass 39, count 0 2006.173.09:00:04.48#ibcon#read 6, iclass 39, count 0 2006.173.09:00:04.48#ibcon#end of sib2, iclass 39, count 0 2006.173.09:00:04.48#ibcon#*after write, iclass 39, count 0 2006.173.09:00:04.48#ibcon#*before return 0, iclass 39, count 0 2006.173.09:00:04.48#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.09:00:04.48#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.09:00:04.48#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.09:00:04.48#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.09:00:04.48$vck44/valo=7,864.99 2006.173.09:00:04.48#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.09:00:04.48#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.09:00:04.48#ibcon#ireg 17 cls_cnt 0 2006.173.09:00:04.48#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.09:00:04.48#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.09:00:04.48#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.09:00:04.48#ibcon#enter wrdev, iclass 3, count 0 2006.173.09:00:04.48#ibcon#first serial, iclass 3, count 0 2006.173.09:00:04.48#ibcon#enter sib2, iclass 3, count 0 2006.173.09:00:04.48#ibcon#flushed, iclass 3, count 0 2006.173.09:00:04.48#ibcon#about to write, iclass 3, count 0 2006.173.09:00:04.48#ibcon#wrote, iclass 3, count 0 2006.173.09:00:04.48#ibcon#about to read 3, iclass 3, count 0 2006.173.09:00:04.50#ibcon#read 3, iclass 3, count 0 2006.173.09:00:04.50#ibcon#about to read 4, iclass 3, count 0 2006.173.09:00:04.50#ibcon#read 4, iclass 3, count 0 2006.173.09:00:04.50#ibcon#about to read 5, iclass 3, count 0 2006.173.09:00:04.50#ibcon#read 5, iclass 3, count 0 2006.173.09:00:04.50#ibcon#about to read 6, iclass 3, count 0 2006.173.09:00:04.50#ibcon#read 6, iclass 3, count 0 2006.173.09:00:04.50#ibcon#end of sib2, iclass 3, count 0 2006.173.09:00:04.50#ibcon#*mode == 0, iclass 3, count 0 2006.173.09:00:04.50#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.09:00:04.50#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.09:00:04.50#ibcon#*before write, iclass 3, count 0 2006.173.09:00:04.50#ibcon#enter sib2, iclass 3, count 0 2006.173.09:00:04.50#ibcon#flushed, iclass 3, count 0 2006.173.09:00:04.50#ibcon#about to write, iclass 3, count 0 2006.173.09:00:04.50#ibcon#wrote, iclass 3, count 0 2006.173.09:00:04.50#ibcon#about to read 3, iclass 3, count 0 2006.173.09:00:04.54#ibcon#read 3, iclass 3, count 0 2006.173.09:00:04.54#ibcon#about to read 4, iclass 3, count 0 2006.173.09:00:04.54#ibcon#read 4, iclass 3, count 0 2006.173.09:00:04.54#ibcon#about to read 5, iclass 3, count 0 2006.173.09:00:04.54#ibcon#read 5, iclass 3, count 0 2006.173.09:00:04.54#ibcon#about to read 6, iclass 3, count 0 2006.173.09:00:04.54#ibcon#read 6, iclass 3, count 0 2006.173.09:00:04.54#ibcon#end of sib2, iclass 3, count 0 2006.173.09:00:04.54#ibcon#*after write, iclass 3, count 0 2006.173.09:00:04.54#ibcon#*before return 0, iclass 3, count 0 2006.173.09:00:04.54#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.09:00:04.54#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.09:00:04.54#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.09:00:04.54#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.09:00:04.54$vck44/va=7,4 2006.173.09:00:04.54#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.09:00:04.54#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.09:00:04.54#ibcon#ireg 11 cls_cnt 2 2006.173.09:00:04.54#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.09:00:04.60#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.09:00:04.60#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.09:00:04.60#ibcon#enter wrdev, iclass 5, count 2 2006.173.09:00:04.60#ibcon#first serial, iclass 5, count 2 2006.173.09:00:04.60#ibcon#enter sib2, iclass 5, count 2 2006.173.09:00:04.60#ibcon#flushed, iclass 5, count 2 2006.173.09:00:04.60#ibcon#about to write, iclass 5, count 2 2006.173.09:00:04.60#ibcon#wrote, iclass 5, count 2 2006.173.09:00:04.60#ibcon#about to read 3, iclass 5, count 2 2006.173.09:00:04.62#ibcon#read 3, iclass 5, count 2 2006.173.09:00:04.62#ibcon#about to read 4, iclass 5, count 2 2006.173.09:00:04.62#ibcon#read 4, iclass 5, count 2 2006.173.09:00:04.62#ibcon#about to read 5, iclass 5, count 2 2006.173.09:00:04.62#ibcon#read 5, iclass 5, count 2 2006.173.09:00:04.62#ibcon#about to read 6, iclass 5, count 2 2006.173.09:00:04.62#ibcon#read 6, iclass 5, count 2 2006.173.09:00:04.62#ibcon#end of sib2, iclass 5, count 2 2006.173.09:00:04.62#ibcon#*mode == 0, iclass 5, count 2 2006.173.09:00:04.62#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.09:00:04.62#ibcon#[25=AT07-04\r\n] 2006.173.09:00:04.62#ibcon#*before write, iclass 5, count 2 2006.173.09:00:04.62#ibcon#enter sib2, iclass 5, count 2 2006.173.09:00:04.62#ibcon#flushed, iclass 5, count 2 2006.173.09:00:04.62#ibcon#about to write, iclass 5, count 2 2006.173.09:00:04.62#ibcon#wrote, iclass 5, count 2 2006.173.09:00:04.62#ibcon#about to read 3, iclass 5, count 2 2006.173.09:00:04.65#ibcon#read 3, iclass 5, count 2 2006.173.09:00:04.65#ibcon#about to read 4, iclass 5, count 2 2006.173.09:00:04.65#ibcon#read 4, iclass 5, count 2 2006.173.09:00:04.65#ibcon#about to read 5, iclass 5, count 2 2006.173.09:00:04.65#ibcon#read 5, iclass 5, count 2 2006.173.09:00:04.65#ibcon#about to read 6, iclass 5, count 2 2006.173.09:00:04.65#ibcon#read 6, iclass 5, count 2 2006.173.09:00:04.65#ibcon#end of sib2, iclass 5, count 2 2006.173.09:00:04.65#ibcon#*after write, iclass 5, count 2 2006.173.09:00:04.65#ibcon#*before return 0, iclass 5, count 2 2006.173.09:00:04.65#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.09:00:04.65#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.09:00:04.65#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.09:00:04.65#ibcon#ireg 7 cls_cnt 0 2006.173.09:00:04.65#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.09:00:04.77#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.09:00:04.77#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.09:00:04.77#ibcon#enter wrdev, iclass 5, count 0 2006.173.09:00:04.77#ibcon#first serial, iclass 5, count 0 2006.173.09:00:04.77#ibcon#enter sib2, iclass 5, count 0 2006.173.09:00:04.77#ibcon#flushed, iclass 5, count 0 2006.173.09:00:04.77#ibcon#about to write, iclass 5, count 0 2006.173.09:00:04.77#ibcon#wrote, iclass 5, count 0 2006.173.09:00:04.77#ibcon#about to read 3, iclass 5, count 0 2006.173.09:00:04.79#ibcon#read 3, iclass 5, count 0 2006.173.09:00:04.79#ibcon#about to read 4, iclass 5, count 0 2006.173.09:00:04.79#ibcon#read 4, iclass 5, count 0 2006.173.09:00:04.79#ibcon#about to read 5, iclass 5, count 0 2006.173.09:00:04.79#ibcon#read 5, iclass 5, count 0 2006.173.09:00:04.79#ibcon#about to read 6, iclass 5, count 0 2006.173.09:00:04.79#ibcon#read 6, iclass 5, count 0 2006.173.09:00:04.79#ibcon#end of sib2, iclass 5, count 0 2006.173.09:00:04.79#ibcon#*mode == 0, iclass 5, count 0 2006.173.09:00:04.79#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.09:00:04.79#ibcon#[25=USB\r\n] 2006.173.09:00:04.79#ibcon#*before write, iclass 5, count 0 2006.173.09:00:04.79#ibcon#enter sib2, iclass 5, count 0 2006.173.09:00:04.79#ibcon#flushed, iclass 5, count 0 2006.173.09:00:04.79#ibcon#about to write, iclass 5, count 0 2006.173.09:00:04.79#ibcon#wrote, iclass 5, count 0 2006.173.09:00:04.79#ibcon#about to read 3, iclass 5, count 0 2006.173.09:00:04.82#ibcon#read 3, iclass 5, count 0 2006.173.09:00:04.82#ibcon#about to read 4, iclass 5, count 0 2006.173.09:00:04.82#ibcon#read 4, iclass 5, count 0 2006.173.09:00:04.82#ibcon#about to read 5, iclass 5, count 0 2006.173.09:00:04.82#ibcon#read 5, iclass 5, count 0 2006.173.09:00:04.82#ibcon#about to read 6, iclass 5, count 0 2006.173.09:00:04.82#ibcon#read 6, iclass 5, count 0 2006.173.09:00:04.82#ibcon#end of sib2, iclass 5, count 0 2006.173.09:00:04.82#ibcon#*after write, iclass 5, count 0 2006.173.09:00:04.82#ibcon#*before return 0, iclass 5, count 0 2006.173.09:00:04.82#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.09:00:04.82#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.09:00:04.82#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.09:00:04.82#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.09:00:04.82$vck44/valo=8,884.99 2006.173.09:00:04.82#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.09:00:04.82#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.09:00:04.82#ibcon#ireg 17 cls_cnt 0 2006.173.09:00:04.82#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.09:00:04.82#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.09:00:04.82#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.09:00:04.82#ibcon#enter wrdev, iclass 7, count 0 2006.173.09:00:04.82#ibcon#first serial, iclass 7, count 0 2006.173.09:00:04.82#ibcon#enter sib2, iclass 7, count 0 2006.173.09:00:04.82#ibcon#flushed, iclass 7, count 0 2006.173.09:00:04.82#ibcon#about to write, iclass 7, count 0 2006.173.09:00:04.82#ibcon#wrote, iclass 7, count 0 2006.173.09:00:04.82#ibcon#about to read 3, iclass 7, count 0 2006.173.09:00:04.84#ibcon#read 3, iclass 7, count 0 2006.173.09:00:04.84#ibcon#about to read 4, iclass 7, count 0 2006.173.09:00:04.84#ibcon#read 4, iclass 7, count 0 2006.173.09:00:04.84#ibcon#about to read 5, iclass 7, count 0 2006.173.09:00:04.84#ibcon#read 5, iclass 7, count 0 2006.173.09:00:04.84#ibcon#about to read 6, iclass 7, count 0 2006.173.09:00:04.84#ibcon#read 6, iclass 7, count 0 2006.173.09:00:04.84#ibcon#end of sib2, iclass 7, count 0 2006.173.09:00:04.84#ibcon#*mode == 0, iclass 7, count 0 2006.173.09:00:04.84#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.09:00:04.84#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.09:00:04.84#ibcon#*before write, iclass 7, count 0 2006.173.09:00:04.84#ibcon#enter sib2, iclass 7, count 0 2006.173.09:00:04.84#ibcon#flushed, iclass 7, count 0 2006.173.09:00:04.84#ibcon#about to write, iclass 7, count 0 2006.173.09:00:04.84#ibcon#wrote, iclass 7, count 0 2006.173.09:00:04.84#ibcon#about to read 3, iclass 7, count 0 2006.173.09:00:04.88#ibcon#read 3, iclass 7, count 0 2006.173.09:00:04.88#ibcon#about to read 4, iclass 7, count 0 2006.173.09:00:04.88#ibcon#read 4, iclass 7, count 0 2006.173.09:00:04.88#ibcon#about to read 5, iclass 7, count 0 2006.173.09:00:04.88#ibcon#read 5, iclass 7, count 0 2006.173.09:00:04.88#ibcon#about to read 6, iclass 7, count 0 2006.173.09:00:04.88#ibcon#read 6, iclass 7, count 0 2006.173.09:00:04.88#ibcon#end of sib2, iclass 7, count 0 2006.173.09:00:04.88#ibcon#*after write, iclass 7, count 0 2006.173.09:00:04.88#ibcon#*before return 0, iclass 7, count 0 2006.173.09:00:04.88#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.09:00:04.88#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.09:00:04.88#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.09:00:04.88#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.09:00:04.88$vck44/va=8,4 2006.173.09:00:04.88#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.09:00:04.88#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.09:00:04.88#ibcon#ireg 11 cls_cnt 2 2006.173.09:00:04.88#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.09:00:04.94#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.09:00:04.94#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.09:00:04.94#ibcon#enter wrdev, iclass 11, count 2 2006.173.09:00:04.94#ibcon#first serial, iclass 11, count 2 2006.173.09:00:04.94#ibcon#enter sib2, iclass 11, count 2 2006.173.09:00:04.94#ibcon#flushed, iclass 11, count 2 2006.173.09:00:04.94#ibcon#about to write, iclass 11, count 2 2006.173.09:00:04.94#ibcon#wrote, iclass 11, count 2 2006.173.09:00:04.94#ibcon#about to read 3, iclass 11, count 2 2006.173.09:00:04.96#ibcon#read 3, iclass 11, count 2 2006.173.09:00:04.96#ibcon#about to read 4, iclass 11, count 2 2006.173.09:00:04.96#ibcon#read 4, iclass 11, count 2 2006.173.09:00:04.96#ibcon#about to read 5, iclass 11, count 2 2006.173.09:00:04.96#ibcon#read 5, iclass 11, count 2 2006.173.09:00:04.96#ibcon#about to read 6, iclass 11, count 2 2006.173.09:00:04.96#ibcon#read 6, iclass 11, count 2 2006.173.09:00:04.96#ibcon#end of sib2, iclass 11, count 2 2006.173.09:00:04.96#ibcon#*mode == 0, iclass 11, count 2 2006.173.09:00:04.96#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.09:00:04.96#ibcon#[25=AT08-04\r\n] 2006.173.09:00:04.96#ibcon#*before write, iclass 11, count 2 2006.173.09:00:04.96#ibcon#enter sib2, iclass 11, count 2 2006.173.09:00:04.96#ibcon#flushed, iclass 11, count 2 2006.173.09:00:04.96#ibcon#about to write, iclass 11, count 2 2006.173.09:00:04.96#ibcon#wrote, iclass 11, count 2 2006.173.09:00:04.96#ibcon#about to read 3, iclass 11, count 2 2006.173.09:00:04.99#ibcon#read 3, iclass 11, count 2 2006.173.09:00:04.99#ibcon#about to read 4, iclass 11, count 2 2006.173.09:00:04.99#ibcon#read 4, iclass 11, count 2 2006.173.09:00:04.99#ibcon#about to read 5, iclass 11, count 2 2006.173.09:00:04.99#ibcon#read 5, iclass 11, count 2 2006.173.09:00:04.99#ibcon#about to read 6, iclass 11, count 2 2006.173.09:00:04.99#ibcon#read 6, iclass 11, count 2 2006.173.09:00:04.99#ibcon#end of sib2, iclass 11, count 2 2006.173.09:00:04.99#ibcon#*after write, iclass 11, count 2 2006.173.09:00:04.99#ibcon#*before return 0, iclass 11, count 2 2006.173.09:00:04.99#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.09:00:04.99#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.09:00:04.99#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.09:00:04.99#ibcon#ireg 7 cls_cnt 0 2006.173.09:00:04.99#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.09:00:05.11#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.09:00:05.11#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.09:00:05.11#ibcon#enter wrdev, iclass 11, count 0 2006.173.09:00:05.11#ibcon#first serial, iclass 11, count 0 2006.173.09:00:05.11#ibcon#enter sib2, iclass 11, count 0 2006.173.09:00:05.11#ibcon#flushed, iclass 11, count 0 2006.173.09:00:05.11#ibcon#about to write, iclass 11, count 0 2006.173.09:00:05.11#ibcon#wrote, iclass 11, count 0 2006.173.09:00:05.11#ibcon#about to read 3, iclass 11, count 0 2006.173.09:00:05.13#ibcon#read 3, iclass 11, count 0 2006.173.09:00:05.13#ibcon#about to read 4, iclass 11, count 0 2006.173.09:00:05.13#ibcon#read 4, iclass 11, count 0 2006.173.09:00:05.13#ibcon#about to read 5, iclass 11, count 0 2006.173.09:00:05.13#ibcon#read 5, iclass 11, count 0 2006.173.09:00:05.13#ibcon#about to read 6, iclass 11, count 0 2006.173.09:00:05.13#ibcon#read 6, iclass 11, count 0 2006.173.09:00:05.13#ibcon#end of sib2, iclass 11, count 0 2006.173.09:00:05.13#ibcon#*mode == 0, iclass 11, count 0 2006.173.09:00:05.13#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.09:00:05.13#ibcon#[25=USB\r\n] 2006.173.09:00:05.13#ibcon#*before write, iclass 11, count 0 2006.173.09:00:05.13#ibcon#enter sib2, iclass 11, count 0 2006.173.09:00:05.13#ibcon#flushed, iclass 11, count 0 2006.173.09:00:05.13#ibcon#about to write, iclass 11, count 0 2006.173.09:00:05.13#ibcon#wrote, iclass 11, count 0 2006.173.09:00:05.13#ibcon#about to read 3, iclass 11, count 0 2006.173.09:00:05.16#ibcon#read 3, iclass 11, count 0 2006.173.09:00:05.16#ibcon#about to read 4, iclass 11, count 0 2006.173.09:00:05.16#ibcon#read 4, iclass 11, count 0 2006.173.09:00:05.16#ibcon#about to read 5, iclass 11, count 0 2006.173.09:00:05.16#ibcon#read 5, iclass 11, count 0 2006.173.09:00:05.16#ibcon#about to read 6, iclass 11, count 0 2006.173.09:00:05.16#ibcon#read 6, iclass 11, count 0 2006.173.09:00:05.16#ibcon#end of sib2, iclass 11, count 0 2006.173.09:00:05.16#ibcon#*after write, iclass 11, count 0 2006.173.09:00:05.16#ibcon#*before return 0, iclass 11, count 0 2006.173.09:00:05.16#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.09:00:05.16#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.09:00:05.16#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.09:00:05.16#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.09:00:05.16$vck44/vblo=1,629.99 2006.173.09:00:05.16#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.09:00:05.16#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.09:00:05.16#ibcon#ireg 17 cls_cnt 0 2006.173.09:00:05.16#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.09:00:05.16#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.09:00:05.16#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.09:00:05.16#ibcon#enter wrdev, iclass 13, count 0 2006.173.09:00:05.16#ibcon#first serial, iclass 13, count 0 2006.173.09:00:05.16#ibcon#enter sib2, iclass 13, count 0 2006.173.09:00:05.16#ibcon#flushed, iclass 13, count 0 2006.173.09:00:05.16#ibcon#about to write, iclass 13, count 0 2006.173.09:00:05.16#ibcon#wrote, iclass 13, count 0 2006.173.09:00:05.16#ibcon#about to read 3, iclass 13, count 0 2006.173.09:00:05.18#ibcon#read 3, iclass 13, count 0 2006.173.09:00:05.18#ibcon#about to read 4, iclass 13, count 0 2006.173.09:00:05.18#ibcon#read 4, iclass 13, count 0 2006.173.09:00:05.18#ibcon#about to read 5, iclass 13, count 0 2006.173.09:00:05.18#ibcon#read 5, iclass 13, count 0 2006.173.09:00:05.18#ibcon#about to read 6, iclass 13, count 0 2006.173.09:00:05.18#ibcon#read 6, iclass 13, count 0 2006.173.09:00:05.18#ibcon#end of sib2, iclass 13, count 0 2006.173.09:00:05.18#ibcon#*mode == 0, iclass 13, count 0 2006.173.09:00:05.18#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.09:00:05.18#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.09:00:05.18#ibcon#*before write, iclass 13, count 0 2006.173.09:00:05.18#ibcon#enter sib2, iclass 13, count 0 2006.173.09:00:05.18#ibcon#flushed, iclass 13, count 0 2006.173.09:00:05.18#ibcon#about to write, iclass 13, count 0 2006.173.09:00:05.18#ibcon#wrote, iclass 13, count 0 2006.173.09:00:05.18#ibcon#about to read 3, iclass 13, count 0 2006.173.09:00:05.22#ibcon#read 3, iclass 13, count 0 2006.173.09:00:05.22#ibcon#about to read 4, iclass 13, count 0 2006.173.09:00:05.22#ibcon#read 4, iclass 13, count 0 2006.173.09:00:05.22#ibcon#about to read 5, iclass 13, count 0 2006.173.09:00:05.22#ibcon#read 5, iclass 13, count 0 2006.173.09:00:05.22#ibcon#about to read 6, iclass 13, count 0 2006.173.09:00:05.22#ibcon#read 6, iclass 13, count 0 2006.173.09:00:05.22#ibcon#end of sib2, iclass 13, count 0 2006.173.09:00:05.22#ibcon#*after write, iclass 13, count 0 2006.173.09:00:05.22#ibcon#*before return 0, iclass 13, count 0 2006.173.09:00:05.22#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.09:00:05.22#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.09:00:05.22#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.09:00:05.22#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.09:00:05.22$vck44/vb=1,4 2006.173.09:00:05.22#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.09:00:05.22#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.09:00:05.22#ibcon#ireg 11 cls_cnt 2 2006.173.09:00:05.22#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.09:00:05.22#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.09:00:05.22#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.09:00:05.22#ibcon#enter wrdev, iclass 15, count 2 2006.173.09:00:05.22#ibcon#first serial, iclass 15, count 2 2006.173.09:00:05.22#ibcon#enter sib2, iclass 15, count 2 2006.173.09:00:05.22#ibcon#flushed, iclass 15, count 2 2006.173.09:00:05.22#ibcon#about to write, iclass 15, count 2 2006.173.09:00:05.22#ibcon#wrote, iclass 15, count 2 2006.173.09:00:05.22#ibcon#about to read 3, iclass 15, count 2 2006.173.09:00:05.24#ibcon#read 3, iclass 15, count 2 2006.173.09:00:05.24#ibcon#about to read 4, iclass 15, count 2 2006.173.09:00:05.24#ibcon#read 4, iclass 15, count 2 2006.173.09:00:05.24#ibcon#about to read 5, iclass 15, count 2 2006.173.09:00:05.24#ibcon#read 5, iclass 15, count 2 2006.173.09:00:05.24#ibcon#about to read 6, iclass 15, count 2 2006.173.09:00:05.24#ibcon#read 6, iclass 15, count 2 2006.173.09:00:05.24#ibcon#end of sib2, iclass 15, count 2 2006.173.09:00:05.24#ibcon#*mode == 0, iclass 15, count 2 2006.173.09:00:05.24#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.09:00:05.24#ibcon#[27=AT01-04\r\n] 2006.173.09:00:05.24#ibcon#*before write, iclass 15, count 2 2006.173.09:00:05.24#ibcon#enter sib2, iclass 15, count 2 2006.173.09:00:05.24#ibcon#flushed, iclass 15, count 2 2006.173.09:00:05.24#ibcon#about to write, iclass 15, count 2 2006.173.09:00:05.24#ibcon#wrote, iclass 15, count 2 2006.173.09:00:05.24#ibcon#about to read 3, iclass 15, count 2 2006.173.09:00:05.27#ibcon#read 3, iclass 15, count 2 2006.173.09:00:05.27#ibcon#about to read 4, iclass 15, count 2 2006.173.09:00:05.27#ibcon#read 4, iclass 15, count 2 2006.173.09:00:05.27#ibcon#about to read 5, iclass 15, count 2 2006.173.09:00:05.27#ibcon#read 5, iclass 15, count 2 2006.173.09:00:05.27#ibcon#about to read 6, iclass 15, count 2 2006.173.09:00:05.27#ibcon#read 6, iclass 15, count 2 2006.173.09:00:05.27#ibcon#end of sib2, iclass 15, count 2 2006.173.09:00:05.27#ibcon#*after write, iclass 15, count 2 2006.173.09:00:05.27#ibcon#*before return 0, iclass 15, count 2 2006.173.09:00:05.27#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.09:00:05.27#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.09:00:05.27#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.09:00:05.27#ibcon#ireg 7 cls_cnt 0 2006.173.09:00:05.27#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.09:00:05.39#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.09:00:05.39#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.09:00:05.39#ibcon#enter wrdev, iclass 15, count 0 2006.173.09:00:05.39#ibcon#first serial, iclass 15, count 0 2006.173.09:00:05.39#ibcon#enter sib2, iclass 15, count 0 2006.173.09:00:05.39#ibcon#flushed, iclass 15, count 0 2006.173.09:00:05.39#ibcon#about to write, iclass 15, count 0 2006.173.09:00:05.39#ibcon#wrote, iclass 15, count 0 2006.173.09:00:05.39#ibcon#about to read 3, iclass 15, count 0 2006.173.09:00:05.41#ibcon#read 3, iclass 15, count 0 2006.173.09:00:05.41#ibcon#about to read 4, iclass 15, count 0 2006.173.09:00:05.41#ibcon#read 4, iclass 15, count 0 2006.173.09:00:05.41#ibcon#about to read 5, iclass 15, count 0 2006.173.09:00:05.41#ibcon#read 5, iclass 15, count 0 2006.173.09:00:05.41#ibcon#about to read 6, iclass 15, count 0 2006.173.09:00:05.41#ibcon#read 6, iclass 15, count 0 2006.173.09:00:05.41#ibcon#end of sib2, iclass 15, count 0 2006.173.09:00:05.41#ibcon#*mode == 0, iclass 15, count 0 2006.173.09:00:05.41#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.09:00:05.41#ibcon#[27=USB\r\n] 2006.173.09:00:05.41#ibcon#*before write, iclass 15, count 0 2006.173.09:00:05.41#ibcon#enter sib2, iclass 15, count 0 2006.173.09:00:05.41#ibcon#flushed, iclass 15, count 0 2006.173.09:00:05.41#ibcon#about to write, iclass 15, count 0 2006.173.09:00:05.41#ibcon#wrote, iclass 15, count 0 2006.173.09:00:05.41#ibcon#about to read 3, iclass 15, count 0 2006.173.09:00:05.44#ibcon#read 3, iclass 15, count 0 2006.173.09:00:05.44#ibcon#about to read 4, iclass 15, count 0 2006.173.09:00:05.44#ibcon#read 4, iclass 15, count 0 2006.173.09:00:05.44#ibcon#about to read 5, iclass 15, count 0 2006.173.09:00:05.44#ibcon#read 5, iclass 15, count 0 2006.173.09:00:05.44#ibcon#about to read 6, iclass 15, count 0 2006.173.09:00:05.44#ibcon#read 6, iclass 15, count 0 2006.173.09:00:05.44#ibcon#end of sib2, iclass 15, count 0 2006.173.09:00:05.44#ibcon#*after write, iclass 15, count 0 2006.173.09:00:05.44#ibcon#*before return 0, iclass 15, count 0 2006.173.09:00:05.44#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.09:00:05.44#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.09:00:05.44#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.09:00:05.44#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.09:00:05.44$vck44/vblo=2,634.99 2006.173.09:00:05.44#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.09:00:05.44#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.09:00:05.44#ibcon#ireg 17 cls_cnt 0 2006.173.09:00:05.44#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.09:00:05.44#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.09:00:05.44#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.09:00:05.44#ibcon#enter wrdev, iclass 17, count 0 2006.173.09:00:05.44#ibcon#first serial, iclass 17, count 0 2006.173.09:00:05.44#ibcon#enter sib2, iclass 17, count 0 2006.173.09:00:05.44#ibcon#flushed, iclass 17, count 0 2006.173.09:00:05.44#ibcon#about to write, iclass 17, count 0 2006.173.09:00:05.44#ibcon#wrote, iclass 17, count 0 2006.173.09:00:05.44#ibcon#about to read 3, iclass 17, count 0 2006.173.09:00:05.46#ibcon#read 3, iclass 17, count 0 2006.173.09:00:05.46#ibcon#about to read 4, iclass 17, count 0 2006.173.09:00:05.46#ibcon#read 4, iclass 17, count 0 2006.173.09:00:05.46#ibcon#about to read 5, iclass 17, count 0 2006.173.09:00:05.46#ibcon#read 5, iclass 17, count 0 2006.173.09:00:05.46#ibcon#about to read 6, iclass 17, count 0 2006.173.09:00:05.46#ibcon#read 6, iclass 17, count 0 2006.173.09:00:05.46#ibcon#end of sib2, iclass 17, count 0 2006.173.09:00:05.46#ibcon#*mode == 0, iclass 17, count 0 2006.173.09:00:05.46#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.09:00:05.46#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.09:00:05.46#ibcon#*before write, iclass 17, count 0 2006.173.09:00:05.46#ibcon#enter sib2, iclass 17, count 0 2006.173.09:00:05.46#ibcon#flushed, iclass 17, count 0 2006.173.09:00:05.46#ibcon#about to write, iclass 17, count 0 2006.173.09:00:05.46#ibcon#wrote, iclass 17, count 0 2006.173.09:00:05.46#ibcon#about to read 3, iclass 17, count 0 2006.173.09:00:05.50#ibcon#read 3, iclass 17, count 0 2006.173.09:00:05.50#ibcon#about to read 4, iclass 17, count 0 2006.173.09:00:05.50#ibcon#read 4, iclass 17, count 0 2006.173.09:00:05.50#ibcon#about to read 5, iclass 17, count 0 2006.173.09:00:05.50#ibcon#read 5, iclass 17, count 0 2006.173.09:00:05.50#ibcon#about to read 6, iclass 17, count 0 2006.173.09:00:05.50#ibcon#read 6, iclass 17, count 0 2006.173.09:00:05.50#ibcon#end of sib2, iclass 17, count 0 2006.173.09:00:05.50#ibcon#*after write, iclass 17, count 0 2006.173.09:00:05.50#ibcon#*before return 0, iclass 17, count 0 2006.173.09:00:05.50#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.09:00:05.50#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.09:00:05.50#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.09:00:05.50#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.09:00:05.50$vck44/vb=2,4 2006.173.09:00:05.50#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.09:00:05.50#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.09:00:05.50#ibcon#ireg 11 cls_cnt 2 2006.173.09:00:05.50#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.09:00:05.56#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.09:00:05.56#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.09:00:05.56#ibcon#enter wrdev, iclass 19, count 2 2006.173.09:00:05.56#ibcon#first serial, iclass 19, count 2 2006.173.09:00:05.56#ibcon#enter sib2, iclass 19, count 2 2006.173.09:00:05.56#ibcon#flushed, iclass 19, count 2 2006.173.09:00:05.56#ibcon#about to write, iclass 19, count 2 2006.173.09:00:05.56#ibcon#wrote, iclass 19, count 2 2006.173.09:00:05.56#ibcon#about to read 3, iclass 19, count 2 2006.173.09:00:05.58#ibcon#read 3, iclass 19, count 2 2006.173.09:00:06.69#ibcon#about to read 4, iclass 19, count 2 2006.173.09:00:06.69#ibcon#read 4, iclass 19, count 2 2006.173.09:00:06.69#ibcon#about to read 5, iclass 19, count 2 2006.173.09:00:06.69#ibcon#read 5, iclass 19, count 2 2006.173.09:00:06.69#ibcon#about to read 6, iclass 19, count 2 2006.173.09:00:06.69#ibcon#read 6, iclass 19, count 2 2006.173.09:00:06.69#ibcon#end of sib2, iclass 19, count 2 2006.173.09:00:06.69#ibcon#*mode == 0, iclass 19, count 2 2006.173.09:00:06.69#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.09:00:06.69#ibcon#[27=AT02-04\r\n] 2006.173.09:00:06.69#ibcon#*before write, iclass 19, count 2 2006.173.09:00:06.69#ibcon#enter sib2, iclass 19, count 2 2006.173.09:00:06.69#ibcon#flushed, iclass 19, count 2 2006.173.09:00:06.69#ibcon#about to write, iclass 19, count 2 2006.173.09:00:06.69#ibcon#wrote, iclass 19, count 2 2006.173.09:00:06.69#ibcon#about to read 3, iclass 19, count 2 2006.173.09:00:06.72#ibcon#read 3, iclass 19, count 2 2006.173.09:00:06.72#ibcon#about to read 4, iclass 19, count 2 2006.173.09:00:06.72#ibcon#read 4, iclass 19, count 2 2006.173.09:00:06.72#ibcon#about to read 5, iclass 19, count 2 2006.173.09:00:06.72#ibcon#read 5, iclass 19, count 2 2006.173.09:00:06.72#ibcon#about to read 6, iclass 19, count 2 2006.173.09:00:06.72#ibcon#read 6, iclass 19, count 2 2006.173.09:00:06.72#ibcon#end of sib2, iclass 19, count 2 2006.173.09:00:06.72#ibcon#*after write, iclass 19, count 2 2006.173.09:00:06.72#ibcon#*before return 0, iclass 19, count 2 2006.173.09:00:06.72#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.09:00:06.72#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.09:00:06.72#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.09:00:06.72#ibcon#ireg 7 cls_cnt 0 2006.173.09:00:06.72#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.09:00:06.74#abcon#<5=/16 0.6 1.2 23.06 871004.4\r\n> 2006.173.09:00:06.76#abcon#{5=INTERFACE CLEAR} 2006.173.09:00:06.82#abcon#[5=S1D000X0/0*\r\n] 2006.173.09:00:06.84#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.09:00:06.84#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.09:00:06.84#ibcon#enter wrdev, iclass 19, count 0 2006.173.09:00:06.84#ibcon#first serial, iclass 19, count 0 2006.173.09:00:06.84#ibcon#enter sib2, iclass 19, count 0 2006.173.09:00:06.84#ibcon#flushed, iclass 19, count 0 2006.173.09:00:06.84#ibcon#about to write, iclass 19, count 0 2006.173.09:00:06.84#ibcon#wrote, iclass 19, count 0 2006.173.09:00:06.84#ibcon#about to read 3, iclass 19, count 0 2006.173.09:00:06.86#ibcon#read 3, iclass 19, count 0 2006.173.09:00:06.86#ibcon#about to read 4, iclass 19, count 0 2006.173.09:00:06.86#ibcon#read 4, iclass 19, count 0 2006.173.09:00:06.86#ibcon#about to read 5, iclass 19, count 0 2006.173.09:00:06.86#ibcon#read 5, iclass 19, count 0 2006.173.09:00:06.86#ibcon#about to read 6, iclass 19, count 0 2006.173.09:00:06.86#ibcon#read 6, iclass 19, count 0 2006.173.09:00:06.86#ibcon#end of sib2, iclass 19, count 0 2006.173.09:00:06.86#ibcon#*mode == 0, iclass 19, count 0 2006.173.09:00:06.86#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.09:00:06.86#ibcon#[27=USB\r\n] 2006.173.09:00:06.86#ibcon#*before write, iclass 19, count 0 2006.173.09:00:06.86#ibcon#enter sib2, iclass 19, count 0 2006.173.09:00:06.86#ibcon#flushed, iclass 19, count 0 2006.173.09:00:06.86#ibcon#about to write, iclass 19, count 0 2006.173.09:00:06.86#ibcon#wrote, iclass 19, count 0 2006.173.09:00:06.86#ibcon#about to read 3, iclass 19, count 0 2006.173.09:00:06.89#ibcon#read 3, iclass 19, count 0 2006.173.09:00:06.89#ibcon#about to read 4, iclass 19, count 0 2006.173.09:00:06.89#ibcon#read 4, iclass 19, count 0 2006.173.09:00:06.89#ibcon#about to read 5, iclass 19, count 0 2006.173.09:00:06.89#ibcon#read 5, iclass 19, count 0 2006.173.09:00:06.89#ibcon#about to read 6, iclass 19, count 0 2006.173.09:00:06.89#ibcon#read 6, iclass 19, count 0 2006.173.09:00:06.89#ibcon#end of sib2, iclass 19, count 0 2006.173.09:00:06.89#ibcon#*after write, iclass 19, count 0 2006.173.09:00:06.89#ibcon#*before return 0, iclass 19, count 0 2006.173.09:00:06.89#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.09:00:06.89#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.09:00:06.89#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.09:00:06.89#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.09:00:06.89$vck44/vblo=3,649.99 2006.173.09:00:06.89#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.09:00:06.89#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.09:00:06.89#ibcon#ireg 17 cls_cnt 0 2006.173.09:00:06.89#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.09:00:06.89#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.09:00:06.89#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.09:00:06.89#ibcon#enter wrdev, iclass 25, count 0 2006.173.09:00:06.89#ibcon#first serial, iclass 25, count 0 2006.173.09:00:06.89#ibcon#enter sib2, iclass 25, count 0 2006.173.09:00:06.89#ibcon#flushed, iclass 25, count 0 2006.173.09:00:06.89#ibcon#about to write, iclass 25, count 0 2006.173.09:00:06.89#ibcon#wrote, iclass 25, count 0 2006.173.09:00:06.89#ibcon#about to read 3, iclass 25, count 0 2006.173.09:00:06.91#ibcon#read 3, iclass 25, count 0 2006.173.09:00:06.91#ibcon#about to read 4, iclass 25, count 0 2006.173.09:00:06.91#ibcon#read 4, iclass 25, count 0 2006.173.09:00:06.91#ibcon#about to read 5, iclass 25, count 0 2006.173.09:00:06.91#ibcon#read 5, iclass 25, count 0 2006.173.09:00:06.91#ibcon#about to read 6, iclass 25, count 0 2006.173.09:00:06.91#ibcon#read 6, iclass 25, count 0 2006.173.09:00:06.91#ibcon#end of sib2, iclass 25, count 0 2006.173.09:00:06.91#ibcon#*mode == 0, iclass 25, count 0 2006.173.09:00:06.91#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.09:00:06.91#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.09:00:06.91#ibcon#*before write, iclass 25, count 0 2006.173.09:00:06.91#ibcon#enter sib2, iclass 25, count 0 2006.173.09:00:06.91#ibcon#flushed, iclass 25, count 0 2006.173.09:00:06.91#ibcon#about to write, iclass 25, count 0 2006.173.09:00:06.91#ibcon#wrote, iclass 25, count 0 2006.173.09:00:06.91#ibcon#about to read 3, iclass 25, count 0 2006.173.09:00:06.95#ibcon#read 3, iclass 25, count 0 2006.173.09:00:06.95#ibcon#about to read 4, iclass 25, count 0 2006.173.09:00:06.95#ibcon#read 4, iclass 25, count 0 2006.173.09:00:06.95#ibcon#about to read 5, iclass 25, count 0 2006.173.09:00:06.95#ibcon#read 5, iclass 25, count 0 2006.173.09:00:06.95#ibcon#about to read 6, iclass 25, count 0 2006.173.09:00:06.95#ibcon#read 6, iclass 25, count 0 2006.173.09:00:06.95#ibcon#end of sib2, iclass 25, count 0 2006.173.09:00:06.95#ibcon#*after write, iclass 25, count 0 2006.173.09:00:06.95#ibcon#*before return 0, iclass 25, count 0 2006.173.09:00:06.95#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.09:00:06.95#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.09:00:06.95#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.09:00:06.95#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.09:00:06.95$vck44/vb=3,4 2006.173.09:00:06.95#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.09:00:06.95#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.09:00:06.95#ibcon#ireg 11 cls_cnt 2 2006.173.09:00:06.95#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.09:00:07.01#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.09:00:07.01#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.09:00:07.01#ibcon#enter wrdev, iclass 27, count 2 2006.173.09:00:07.01#ibcon#first serial, iclass 27, count 2 2006.173.09:00:07.01#ibcon#enter sib2, iclass 27, count 2 2006.173.09:00:07.01#ibcon#flushed, iclass 27, count 2 2006.173.09:00:07.01#ibcon#about to write, iclass 27, count 2 2006.173.09:00:07.01#ibcon#wrote, iclass 27, count 2 2006.173.09:00:07.01#ibcon#about to read 3, iclass 27, count 2 2006.173.09:00:07.03#ibcon#read 3, iclass 27, count 2 2006.173.09:00:07.03#ibcon#about to read 4, iclass 27, count 2 2006.173.09:00:07.03#ibcon#read 4, iclass 27, count 2 2006.173.09:00:07.03#ibcon#about to read 5, iclass 27, count 2 2006.173.09:00:07.03#ibcon#read 5, iclass 27, count 2 2006.173.09:00:07.03#ibcon#about to read 6, iclass 27, count 2 2006.173.09:00:07.03#ibcon#read 6, iclass 27, count 2 2006.173.09:00:07.03#ibcon#end of sib2, iclass 27, count 2 2006.173.09:00:07.03#ibcon#*mode == 0, iclass 27, count 2 2006.173.09:00:07.03#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.09:00:07.03#ibcon#[27=AT03-04\r\n] 2006.173.09:00:07.03#ibcon#*before write, iclass 27, count 2 2006.173.09:00:07.03#ibcon#enter sib2, iclass 27, count 2 2006.173.09:00:07.03#ibcon#flushed, iclass 27, count 2 2006.173.09:00:07.03#ibcon#about to write, iclass 27, count 2 2006.173.09:00:07.03#ibcon#wrote, iclass 27, count 2 2006.173.09:00:07.03#ibcon#about to read 3, iclass 27, count 2 2006.173.09:00:07.06#ibcon#read 3, iclass 27, count 2 2006.173.09:00:07.06#ibcon#about to read 4, iclass 27, count 2 2006.173.09:00:07.06#ibcon#read 4, iclass 27, count 2 2006.173.09:00:07.06#ibcon#about to read 5, iclass 27, count 2 2006.173.09:00:07.06#ibcon#read 5, iclass 27, count 2 2006.173.09:00:07.06#ibcon#about to read 6, iclass 27, count 2 2006.173.09:00:07.06#ibcon#read 6, iclass 27, count 2 2006.173.09:00:07.06#ibcon#end of sib2, iclass 27, count 2 2006.173.09:00:07.06#ibcon#*after write, iclass 27, count 2 2006.173.09:00:07.06#ibcon#*before return 0, iclass 27, count 2 2006.173.09:00:07.06#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.09:00:07.06#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.09:00:07.06#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.09:00:07.06#ibcon#ireg 7 cls_cnt 0 2006.173.09:00:07.06#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.09:00:07.18#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.09:00:07.18#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.09:00:07.18#ibcon#enter wrdev, iclass 27, count 0 2006.173.09:00:07.18#ibcon#first serial, iclass 27, count 0 2006.173.09:00:07.18#ibcon#enter sib2, iclass 27, count 0 2006.173.09:00:07.18#ibcon#flushed, iclass 27, count 0 2006.173.09:00:07.18#ibcon#about to write, iclass 27, count 0 2006.173.09:00:07.18#ibcon#wrote, iclass 27, count 0 2006.173.09:00:07.18#ibcon#about to read 3, iclass 27, count 0 2006.173.09:00:07.20#ibcon#read 3, iclass 27, count 0 2006.173.09:00:07.20#ibcon#about to read 4, iclass 27, count 0 2006.173.09:00:07.20#ibcon#read 4, iclass 27, count 0 2006.173.09:00:07.20#ibcon#about to read 5, iclass 27, count 0 2006.173.09:00:07.20#ibcon#read 5, iclass 27, count 0 2006.173.09:00:07.20#ibcon#about to read 6, iclass 27, count 0 2006.173.09:00:07.20#ibcon#read 6, iclass 27, count 0 2006.173.09:00:07.20#ibcon#end of sib2, iclass 27, count 0 2006.173.09:00:07.20#ibcon#*mode == 0, iclass 27, count 0 2006.173.09:00:07.20#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.09:00:07.20#ibcon#[27=USB\r\n] 2006.173.09:00:07.20#ibcon#*before write, iclass 27, count 0 2006.173.09:00:07.20#ibcon#enter sib2, iclass 27, count 0 2006.173.09:00:07.20#ibcon#flushed, iclass 27, count 0 2006.173.09:00:07.20#ibcon#about to write, iclass 27, count 0 2006.173.09:00:07.20#ibcon#wrote, iclass 27, count 0 2006.173.09:00:07.20#ibcon#about to read 3, iclass 27, count 0 2006.173.09:00:07.23#ibcon#read 3, iclass 27, count 0 2006.173.09:00:07.23#ibcon#about to read 4, iclass 27, count 0 2006.173.09:00:07.23#ibcon#read 4, iclass 27, count 0 2006.173.09:00:07.23#ibcon#about to read 5, iclass 27, count 0 2006.173.09:00:07.23#ibcon#read 5, iclass 27, count 0 2006.173.09:00:07.23#ibcon#about to read 6, iclass 27, count 0 2006.173.09:00:07.23#ibcon#read 6, iclass 27, count 0 2006.173.09:00:07.23#ibcon#end of sib2, iclass 27, count 0 2006.173.09:00:07.23#ibcon#*after write, iclass 27, count 0 2006.173.09:00:07.23#ibcon#*before return 0, iclass 27, count 0 2006.173.09:00:07.23#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.09:00:07.23#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.09:00:07.23#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.09:00:07.23#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.09:00:07.23$vck44/vblo=4,679.99 2006.173.09:00:07.23#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.09:00:07.23#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.09:00:07.23#ibcon#ireg 17 cls_cnt 0 2006.173.09:00:07.23#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.09:00:07.23#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.09:00:07.23#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.09:00:07.23#ibcon#enter wrdev, iclass 29, count 0 2006.173.09:00:07.23#ibcon#first serial, iclass 29, count 0 2006.173.09:00:07.23#ibcon#enter sib2, iclass 29, count 0 2006.173.09:00:07.23#ibcon#flushed, iclass 29, count 0 2006.173.09:00:07.23#ibcon#about to write, iclass 29, count 0 2006.173.09:00:07.23#ibcon#wrote, iclass 29, count 0 2006.173.09:00:07.23#ibcon#about to read 3, iclass 29, count 0 2006.173.09:00:07.25#ibcon#read 3, iclass 29, count 0 2006.173.09:00:07.25#ibcon#about to read 4, iclass 29, count 0 2006.173.09:00:07.25#ibcon#read 4, iclass 29, count 0 2006.173.09:00:07.25#ibcon#about to read 5, iclass 29, count 0 2006.173.09:00:07.25#ibcon#read 5, iclass 29, count 0 2006.173.09:00:07.25#ibcon#about to read 6, iclass 29, count 0 2006.173.09:00:07.25#ibcon#read 6, iclass 29, count 0 2006.173.09:00:07.25#ibcon#end of sib2, iclass 29, count 0 2006.173.09:00:07.25#ibcon#*mode == 0, iclass 29, count 0 2006.173.09:00:07.25#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.09:00:07.25#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.09:00:07.25#ibcon#*before write, iclass 29, count 0 2006.173.09:00:07.25#ibcon#enter sib2, iclass 29, count 0 2006.173.09:00:07.25#ibcon#flushed, iclass 29, count 0 2006.173.09:00:07.25#ibcon#about to write, iclass 29, count 0 2006.173.09:00:07.25#ibcon#wrote, iclass 29, count 0 2006.173.09:00:07.25#ibcon#about to read 3, iclass 29, count 0 2006.173.09:00:07.29#ibcon#read 3, iclass 29, count 0 2006.173.09:00:07.29#ibcon#about to read 4, iclass 29, count 0 2006.173.09:00:07.29#ibcon#read 4, iclass 29, count 0 2006.173.09:00:07.29#ibcon#about to read 5, iclass 29, count 0 2006.173.09:00:07.29#ibcon#read 5, iclass 29, count 0 2006.173.09:00:07.29#ibcon#about to read 6, iclass 29, count 0 2006.173.09:00:07.29#ibcon#read 6, iclass 29, count 0 2006.173.09:00:07.29#ibcon#end of sib2, iclass 29, count 0 2006.173.09:00:07.29#ibcon#*after write, iclass 29, count 0 2006.173.09:00:07.29#ibcon#*before return 0, iclass 29, count 0 2006.173.09:00:07.29#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.09:00:07.29#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.09:00:07.29#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.09:00:07.29#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.09:00:07.29$vck44/vb=4,4 2006.173.09:00:07.29#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.09:00:07.29#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.09:00:07.29#ibcon#ireg 11 cls_cnt 2 2006.173.09:00:07.29#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.09:00:07.35#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.09:00:07.35#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.09:00:07.35#ibcon#enter wrdev, iclass 31, count 2 2006.173.09:00:07.35#ibcon#first serial, iclass 31, count 2 2006.173.09:00:07.35#ibcon#enter sib2, iclass 31, count 2 2006.173.09:00:07.35#ibcon#flushed, iclass 31, count 2 2006.173.09:00:07.35#ibcon#about to write, iclass 31, count 2 2006.173.09:00:07.35#ibcon#wrote, iclass 31, count 2 2006.173.09:00:07.35#ibcon#about to read 3, iclass 31, count 2 2006.173.09:00:07.37#ibcon#read 3, iclass 31, count 2 2006.173.09:00:07.37#ibcon#about to read 4, iclass 31, count 2 2006.173.09:00:07.37#ibcon#read 4, iclass 31, count 2 2006.173.09:00:07.37#ibcon#about to read 5, iclass 31, count 2 2006.173.09:00:07.37#ibcon#read 5, iclass 31, count 2 2006.173.09:00:07.37#ibcon#about to read 6, iclass 31, count 2 2006.173.09:00:07.37#ibcon#read 6, iclass 31, count 2 2006.173.09:00:07.37#ibcon#end of sib2, iclass 31, count 2 2006.173.09:00:07.37#ibcon#*mode == 0, iclass 31, count 2 2006.173.09:00:07.37#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.09:00:07.37#ibcon#[27=AT04-04\r\n] 2006.173.09:00:07.37#ibcon#*before write, iclass 31, count 2 2006.173.09:00:07.37#ibcon#enter sib2, iclass 31, count 2 2006.173.09:00:07.37#ibcon#flushed, iclass 31, count 2 2006.173.09:00:07.37#ibcon#about to write, iclass 31, count 2 2006.173.09:00:07.37#ibcon#wrote, iclass 31, count 2 2006.173.09:00:07.37#ibcon#about to read 3, iclass 31, count 2 2006.173.09:00:07.40#ibcon#read 3, iclass 31, count 2 2006.173.09:00:07.40#ibcon#about to read 4, iclass 31, count 2 2006.173.09:00:07.40#ibcon#read 4, iclass 31, count 2 2006.173.09:00:07.40#ibcon#about to read 5, iclass 31, count 2 2006.173.09:00:07.40#ibcon#read 5, iclass 31, count 2 2006.173.09:00:07.40#ibcon#about to read 6, iclass 31, count 2 2006.173.09:00:07.40#ibcon#read 6, iclass 31, count 2 2006.173.09:00:07.40#ibcon#end of sib2, iclass 31, count 2 2006.173.09:00:07.40#ibcon#*after write, iclass 31, count 2 2006.173.09:00:07.40#ibcon#*before return 0, iclass 31, count 2 2006.173.09:00:07.40#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.09:00:07.40#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.09:00:07.40#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.09:00:07.40#ibcon#ireg 7 cls_cnt 0 2006.173.09:00:07.40#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.09:00:07.52#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.09:00:07.52#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.09:00:07.52#ibcon#enter wrdev, iclass 31, count 0 2006.173.09:00:07.52#ibcon#first serial, iclass 31, count 0 2006.173.09:00:07.52#ibcon#enter sib2, iclass 31, count 0 2006.173.09:00:07.52#ibcon#flushed, iclass 31, count 0 2006.173.09:00:07.52#ibcon#about to write, iclass 31, count 0 2006.173.09:00:07.52#ibcon#wrote, iclass 31, count 0 2006.173.09:00:07.52#ibcon#about to read 3, iclass 31, count 0 2006.173.09:00:07.54#ibcon#read 3, iclass 31, count 0 2006.173.09:00:07.54#ibcon#about to read 4, iclass 31, count 0 2006.173.09:00:07.54#ibcon#read 4, iclass 31, count 0 2006.173.09:00:07.54#ibcon#about to read 5, iclass 31, count 0 2006.173.09:00:07.54#ibcon#read 5, iclass 31, count 0 2006.173.09:00:07.54#ibcon#about to read 6, iclass 31, count 0 2006.173.09:00:07.54#ibcon#read 6, iclass 31, count 0 2006.173.09:00:07.54#ibcon#end of sib2, iclass 31, count 0 2006.173.09:00:07.54#ibcon#*mode == 0, iclass 31, count 0 2006.173.09:00:07.54#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.09:00:07.54#ibcon#[27=USB\r\n] 2006.173.09:00:07.54#ibcon#*before write, iclass 31, count 0 2006.173.09:00:07.54#ibcon#enter sib2, iclass 31, count 0 2006.173.09:00:07.54#ibcon#flushed, iclass 31, count 0 2006.173.09:00:07.54#ibcon#about to write, iclass 31, count 0 2006.173.09:00:07.54#ibcon#wrote, iclass 31, count 0 2006.173.09:00:07.54#ibcon#about to read 3, iclass 31, count 0 2006.173.09:00:07.57#ibcon#read 3, iclass 31, count 0 2006.173.09:00:07.57#ibcon#about to read 4, iclass 31, count 0 2006.173.09:00:07.57#ibcon#read 4, iclass 31, count 0 2006.173.09:00:07.57#ibcon#about to read 5, iclass 31, count 0 2006.173.09:00:07.57#ibcon#read 5, iclass 31, count 0 2006.173.09:00:07.57#ibcon#about to read 6, iclass 31, count 0 2006.173.09:00:07.57#ibcon#read 6, iclass 31, count 0 2006.173.09:00:07.57#ibcon#end of sib2, iclass 31, count 0 2006.173.09:00:07.57#ibcon#*after write, iclass 31, count 0 2006.173.09:00:07.57#ibcon#*before return 0, iclass 31, count 0 2006.173.09:00:07.57#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.09:00:07.57#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.09:00:07.57#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.09:00:07.57#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.09:00:07.57$vck44/vblo=5,709.99 2006.173.09:00:07.57#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.09:00:07.57#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.09:00:07.57#ibcon#ireg 17 cls_cnt 0 2006.173.09:00:07.57#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.09:00:07.57#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.09:00:07.57#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.09:00:07.57#ibcon#enter wrdev, iclass 33, count 0 2006.173.09:00:07.57#ibcon#first serial, iclass 33, count 0 2006.173.09:00:07.57#ibcon#enter sib2, iclass 33, count 0 2006.173.09:00:07.57#ibcon#flushed, iclass 33, count 0 2006.173.09:00:07.57#ibcon#about to write, iclass 33, count 0 2006.173.09:00:07.57#ibcon#wrote, iclass 33, count 0 2006.173.09:00:07.57#ibcon#about to read 3, iclass 33, count 0 2006.173.09:00:07.59#ibcon#read 3, iclass 33, count 0 2006.173.09:00:07.59#ibcon#about to read 4, iclass 33, count 0 2006.173.09:00:07.59#ibcon#read 4, iclass 33, count 0 2006.173.09:00:07.59#ibcon#about to read 5, iclass 33, count 0 2006.173.09:00:07.59#ibcon#read 5, iclass 33, count 0 2006.173.09:00:07.59#ibcon#about to read 6, iclass 33, count 0 2006.173.09:00:07.59#ibcon#read 6, iclass 33, count 0 2006.173.09:00:07.59#ibcon#end of sib2, iclass 33, count 0 2006.173.09:00:07.59#ibcon#*mode == 0, iclass 33, count 0 2006.173.09:00:07.59#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.09:00:07.59#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.09:00:07.59#ibcon#*before write, iclass 33, count 0 2006.173.09:00:07.59#ibcon#enter sib2, iclass 33, count 0 2006.173.09:00:07.59#ibcon#flushed, iclass 33, count 0 2006.173.09:00:07.59#ibcon#about to write, iclass 33, count 0 2006.173.09:00:07.59#ibcon#wrote, iclass 33, count 0 2006.173.09:00:07.59#ibcon#about to read 3, iclass 33, count 0 2006.173.09:00:07.63#ibcon#read 3, iclass 33, count 0 2006.173.09:00:07.63#ibcon#about to read 4, iclass 33, count 0 2006.173.09:00:07.63#ibcon#read 4, iclass 33, count 0 2006.173.09:00:07.63#ibcon#about to read 5, iclass 33, count 0 2006.173.09:00:07.63#ibcon#read 5, iclass 33, count 0 2006.173.09:00:07.63#ibcon#about to read 6, iclass 33, count 0 2006.173.09:00:07.63#ibcon#read 6, iclass 33, count 0 2006.173.09:00:07.63#ibcon#end of sib2, iclass 33, count 0 2006.173.09:00:07.63#ibcon#*after write, iclass 33, count 0 2006.173.09:00:07.63#ibcon#*before return 0, iclass 33, count 0 2006.173.09:00:07.63#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.09:00:07.63#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.09:00:07.63#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.09:00:07.63#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.09:00:07.63$vck44/vb=5,4 2006.173.09:00:07.63#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.09:00:07.63#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.09:00:07.63#ibcon#ireg 11 cls_cnt 2 2006.173.09:00:07.63#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.09:00:07.69#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.09:00:07.69#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.09:00:07.69#ibcon#enter wrdev, iclass 35, count 2 2006.173.09:00:07.69#ibcon#first serial, iclass 35, count 2 2006.173.09:00:07.69#ibcon#enter sib2, iclass 35, count 2 2006.173.09:00:07.69#ibcon#flushed, iclass 35, count 2 2006.173.09:00:07.69#ibcon#about to write, iclass 35, count 2 2006.173.09:00:07.69#ibcon#wrote, iclass 35, count 2 2006.173.09:00:07.69#ibcon#about to read 3, iclass 35, count 2 2006.173.09:00:07.71#ibcon#read 3, iclass 35, count 2 2006.173.09:00:07.71#ibcon#about to read 4, iclass 35, count 2 2006.173.09:00:07.71#ibcon#read 4, iclass 35, count 2 2006.173.09:00:07.71#ibcon#about to read 5, iclass 35, count 2 2006.173.09:00:07.71#ibcon#read 5, iclass 35, count 2 2006.173.09:00:07.71#ibcon#about to read 6, iclass 35, count 2 2006.173.09:00:07.71#ibcon#read 6, iclass 35, count 2 2006.173.09:00:07.71#ibcon#end of sib2, iclass 35, count 2 2006.173.09:00:07.71#ibcon#*mode == 0, iclass 35, count 2 2006.173.09:00:07.71#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.09:00:07.71#ibcon#[27=AT05-04\r\n] 2006.173.09:00:07.71#ibcon#*before write, iclass 35, count 2 2006.173.09:00:07.71#ibcon#enter sib2, iclass 35, count 2 2006.173.09:00:07.71#ibcon#flushed, iclass 35, count 2 2006.173.09:00:07.71#ibcon#about to write, iclass 35, count 2 2006.173.09:00:07.71#ibcon#wrote, iclass 35, count 2 2006.173.09:00:07.71#ibcon#about to read 3, iclass 35, count 2 2006.173.09:00:07.74#ibcon#read 3, iclass 35, count 2 2006.173.09:00:07.74#ibcon#about to read 4, iclass 35, count 2 2006.173.09:00:07.74#ibcon#read 4, iclass 35, count 2 2006.173.09:00:07.74#ibcon#about to read 5, iclass 35, count 2 2006.173.09:00:07.74#ibcon#read 5, iclass 35, count 2 2006.173.09:00:07.74#ibcon#about to read 6, iclass 35, count 2 2006.173.09:00:07.74#ibcon#read 6, iclass 35, count 2 2006.173.09:00:07.74#ibcon#end of sib2, iclass 35, count 2 2006.173.09:00:07.74#ibcon#*after write, iclass 35, count 2 2006.173.09:00:07.74#ibcon#*before return 0, iclass 35, count 2 2006.173.09:00:07.74#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.09:00:07.74#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.09:00:07.74#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.09:00:07.74#ibcon#ireg 7 cls_cnt 0 2006.173.09:00:07.74#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.09:00:07.86#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.09:00:07.86#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.09:00:07.86#ibcon#enter wrdev, iclass 35, count 0 2006.173.09:00:07.86#ibcon#first serial, iclass 35, count 0 2006.173.09:00:07.86#ibcon#enter sib2, iclass 35, count 0 2006.173.09:00:07.86#ibcon#flushed, iclass 35, count 0 2006.173.09:00:07.86#ibcon#about to write, iclass 35, count 0 2006.173.09:00:07.86#ibcon#wrote, iclass 35, count 0 2006.173.09:00:07.86#ibcon#about to read 3, iclass 35, count 0 2006.173.09:00:07.88#ibcon#read 3, iclass 35, count 0 2006.173.09:00:07.88#ibcon#about to read 4, iclass 35, count 0 2006.173.09:00:07.88#ibcon#read 4, iclass 35, count 0 2006.173.09:00:07.88#ibcon#about to read 5, iclass 35, count 0 2006.173.09:00:07.88#ibcon#read 5, iclass 35, count 0 2006.173.09:00:07.88#ibcon#about to read 6, iclass 35, count 0 2006.173.09:00:07.88#ibcon#read 6, iclass 35, count 0 2006.173.09:00:07.88#ibcon#end of sib2, iclass 35, count 0 2006.173.09:00:07.88#ibcon#*mode == 0, iclass 35, count 0 2006.173.09:00:07.88#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.09:00:07.88#ibcon#[27=USB\r\n] 2006.173.09:00:07.88#ibcon#*before write, iclass 35, count 0 2006.173.09:00:07.88#ibcon#enter sib2, iclass 35, count 0 2006.173.09:00:07.88#ibcon#flushed, iclass 35, count 0 2006.173.09:00:07.88#ibcon#about to write, iclass 35, count 0 2006.173.09:00:07.88#ibcon#wrote, iclass 35, count 0 2006.173.09:00:07.88#ibcon#about to read 3, iclass 35, count 0 2006.173.09:00:07.91#ibcon#read 3, iclass 35, count 0 2006.173.09:00:07.91#ibcon#about to read 4, iclass 35, count 0 2006.173.09:00:07.91#ibcon#read 4, iclass 35, count 0 2006.173.09:00:07.91#ibcon#about to read 5, iclass 35, count 0 2006.173.09:00:07.91#ibcon#read 5, iclass 35, count 0 2006.173.09:00:07.91#ibcon#about to read 6, iclass 35, count 0 2006.173.09:00:07.91#ibcon#read 6, iclass 35, count 0 2006.173.09:00:07.91#ibcon#end of sib2, iclass 35, count 0 2006.173.09:00:07.91#ibcon#*after write, iclass 35, count 0 2006.173.09:00:07.91#ibcon#*before return 0, iclass 35, count 0 2006.173.09:00:07.91#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.09:00:07.91#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.09:00:07.91#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.09:00:07.91#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.09:00:07.91$vck44/vblo=6,719.99 2006.173.09:00:07.91#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.09:00:07.91#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.09:00:07.91#ibcon#ireg 17 cls_cnt 0 2006.173.09:00:07.91#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.09:00:07.91#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.09:00:07.91#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.09:00:07.91#ibcon#enter wrdev, iclass 37, count 0 2006.173.09:00:07.91#ibcon#first serial, iclass 37, count 0 2006.173.09:00:07.91#ibcon#enter sib2, iclass 37, count 0 2006.173.09:00:07.91#ibcon#flushed, iclass 37, count 0 2006.173.09:00:07.91#ibcon#about to write, iclass 37, count 0 2006.173.09:00:07.91#ibcon#wrote, iclass 37, count 0 2006.173.09:00:07.91#ibcon#about to read 3, iclass 37, count 0 2006.173.09:00:07.93#ibcon#read 3, iclass 37, count 0 2006.173.09:00:07.93#ibcon#about to read 4, iclass 37, count 0 2006.173.09:00:07.93#ibcon#read 4, iclass 37, count 0 2006.173.09:00:07.93#ibcon#about to read 5, iclass 37, count 0 2006.173.09:00:07.93#ibcon#read 5, iclass 37, count 0 2006.173.09:00:07.93#ibcon#about to read 6, iclass 37, count 0 2006.173.09:00:07.93#ibcon#read 6, iclass 37, count 0 2006.173.09:00:07.93#ibcon#end of sib2, iclass 37, count 0 2006.173.09:00:07.93#ibcon#*mode == 0, iclass 37, count 0 2006.173.09:00:07.93#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.09:00:07.93#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.09:00:07.93#ibcon#*before write, iclass 37, count 0 2006.173.09:00:07.93#ibcon#enter sib2, iclass 37, count 0 2006.173.09:00:07.93#ibcon#flushed, iclass 37, count 0 2006.173.09:00:07.93#ibcon#about to write, iclass 37, count 0 2006.173.09:00:07.93#ibcon#wrote, iclass 37, count 0 2006.173.09:00:07.93#ibcon#about to read 3, iclass 37, count 0 2006.173.09:00:07.97#ibcon#read 3, iclass 37, count 0 2006.173.09:00:07.97#ibcon#about to read 4, iclass 37, count 0 2006.173.09:00:07.97#ibcon#read 4, iclass 37, count 0 2006.173.09:00:07.97#ibcon#about to read 5, iclass 37, count 0 2006.173.09:00:07.97#ibcon#read 5, iclass 37, count 0 2006.173.09:00:07.97#ibcon#about to read 6, iclass 37, count 0 2006.173.09:00:07.97#ibcon#read 6, iclass 37, count 0 2006.173.09:00:07.97#ibcon#end of sib2, iclass 37, count 0 2006.173.09:00:07.97#ibcon#*after write, iclass 37, count 0 2006.173.09:00:07.97#ibcon#*before return 0, iclass 37, count 0 2006.173.09:00:07.97#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.09:00:07.97#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.09:00:07.97#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.09:00:07.97#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.09:00:07.97$vck44/vb=6,4 2006.173.09:00:07.97#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.09:00:07.97#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.09:00:07.97#ibcon#ireg 11 cls_cnt 2 2006.173.09:00:07.97#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.09:00:08.03#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.09:00:08.03#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.09:00:08.03#ibcon#enter wrdev, iclass 39, count 2 2006.173.09:00:08.03#ibcon#first serial, iclass 39, count 2 2006.173.09:00:08.03#ibcon#enter sib2, iclass 39, count 2 2006.173.09:00:08.03#ibcon#flushed, iclass 39, count 2 2006.173.09:00:08.03#ibcon#about to write, iclass 39, count 2 2006.173.09:00:08.03#ibcon#wrote, iclass 39, count 2 2006.173.09:00:08.03#ibcon#about to read 3, iclass 39, count 2 2006.173.09:00:08.05#ibcon#read 3, iclass 39, count 2 2006.173.09:00:08.05#ibcon#about to read 4, iclass 39, count 2 2006.173.09:00:08.05#ibcon#read 4, iclass 39, count 2 2006.173.09:00:08.05#ibcon#about to read 5, iclass 39, count 2 2006.173.09:00:08.05#ibcon#read 5, iclass 39, count 2 2006.173.09:00:08.05#ibcon#about to read 6, iclass 39, count 2 2006.173.09:00:08.05#ibcon#read 6, iclass 39, count 2 2006.173.09:00:08.05#ibcon#end of sib2, iclass 39, count 2 2006.173.09:00:08.05#ibcon#*mode == 0, iclass 39, count 2 2006.173.09:00:08.05#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.09:00:08.05#ibcon#[27=AT06-04\r\n] 2006.173.09:00:08.05#ibcon#*before write, iclass 39, count 2 2006.173.09:00:08.05#ibcon#enter sib2, iclass 39, count 2 2006.173.09:00:08.05#ibcon#flushed, iclass 39, count 2 2006.173.09:00:08.05#ibcon#about to write, iclass 39, count 2 2006.173.09:00:08.05#ibcon#wrote, iclass 39, count 2 2006.173.09:00:08.05#ibcon#about to read 3, iclass 39, count 2 2006.173.09:00:08.08#ibcon#read 3, iclass 39, count 2 2006.173.09:00:08.79#ibcon#about to read 4, iclass 39, count 2 2006.173.09:00:08.79#ibcon#read 4, iclass 39, count 2 2006.173.09:00:08.79#ibcon#about to read 5, iclass 39, count 2 2006.173.09:00:08.79#ibcon#read 5, iclass 39, count 2 2006.173.09:00:08.79#ibcon#about to read 6, iclass 39, count 2 2006.173.09:00:08.79#ibcon#read 6, iclass 39, count 2 2006.173.09:00:08.79#ibcon#end of sib2, iclass 39, count 2 2006.173.09:00:08.79#ibcon#*after write, iclass 39, count 2 2006.173.09:00:08.79#ibcon#*before return 0, iclass 39, count 2 2006.173.09:00:08.79#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.09:00:08.79#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.09:00:08.79#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.09:00:08.79#ibcon#ireg 7 cls_cnt 0 2006.173.09:00:08.79#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.09:00:08.91#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.09:00:08.91#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.09:00:08.91#ibcon#enter wrdev, iclass 39, count 0 2006.173.09:00:08.91#ibcon#first serial, iclass 39, count 0 2006.173.09:00:08.91#ibcon#enter sib2, iclass 39, count 0 2006.173.09:00:08.91#ibcon#flushed, iclass 39, count 0 2006.173.09:00:08.91#ibcon#about to write, iclass 39, count 0 2006.173.09:00:08.91#ibcon#wrote, iclass 39, count 0 2006.173.09:00:08.91#ibcon#about to read 3, iclass 39, count 0 2006.173.09:00:08.93#ibcon#read 3, iclass 39, count 0 2006.173.09:00:08.93#ibcon#about to read 4, iclass 39, count 0 2006.173.09:00:08.93#ibcon#read 4, iclass 39, count 0 2006.173.09:00:08.93#ibcon#about to read 5, iclass 39, count 0 2006.173.09:00:08.93#ibcon#read 5, iclass 39, count 0 2006.173.09:00:08.93#ibcon#about to read 6, iclass 39, count 0 2006.173.09:00:08.93#ibcon#read 6, iclass 39, count 0 2006.173.09:00:08.93#ibcon#end of sib2, iclass 39, count 0 2006.173.09:00:08.93#ibcon#*mode == 0, iclass 39, count 0 2006.173.09:00:08.93#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.09:00:08.93#ibcon#[27=USB\r\n] 2006.173.09:00:08.93#ibcon#*before write, iclass 39, count 0 2006.173.09:00:08.93#ibcon#enter sib2, iclass 39, count 0 2006.173.09:00:08.93#ibcon#flushed, iclass 39, count 0 2006.173.09:00:08.93#ibcon#about to write, iclass 39, count 0 2006.173.09:00:08.93#ibcon#wrote, iclass 39, count 0 2006.173.09:00:08.93#ibcon#about to read 3, iclass 39, count 0 2006.173.09:00:08.96#ibcon#read 3, iclass 39, count 0 2006.173.09:00:08.96#ibcon#about to read 4, iclass 39, count 0 2006.173.09:00:08.96#ibcon#read 4, iclass 39, count 0 2006.173.09:00:08.96#ibcon#about to read 5, iclass 39, count 0 2006.173.09:00:08.96#ibcon#read 5, iclass 39, count 0 2006.173.09:00:08.96#ibcon#about to read 6, iclass 39, count 0 2006.173.09:00:08.96#ibcon#read 6, iclass 39, count 0 2006.173.09:00:08.96#ibcon#end of sib2, iclass 39, count 0 2006.173.09:00:08.96#ibcon#*after write, iclass 39, count 0 2006.173.09:00:08.96#ibcon#*before return 0, iclass 39, count 0 2006.173.09:00:08.96#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.09:00:08.96#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.09:00:08.96#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.09:00:08.96#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.09:00:08.96$vck44/vblo=7,734.99 2006.173.09:00:08.96#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.09:00:08.96#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.09:00:08.96#ibcon#ireg 17 cls_cnt 0 2006.173.09:00:08.96#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.09:00:08.96#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.09:00:08.96#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.09:00:08.96#ibcon#enter wrdev, iclass 3, count 0 2006.173.09:00:08.96#ibcon#first serial, iclass 3, count 0 2006.173.09:00:08.96#ibcon#enter sib2, iclass 3, count 0 2006.173.09:00:08.96#ibcon#flushed, iclass 3, count 0 2006.173.09:00:08.96#ibcon#about to write, iclass 3, count 0 2006.173.09:00:08.96#ibcon#wrote, iclass 3, count 0 2006.173.09:00:08.96#ibcon#about to read 3, iclass 3, count 0 2006.173.09:00:08.98#ibcon#read 3, iclass 3, count 0 2006.173.09:00:08.98#ibcon#about to read 4, iclass 3, count 0 2006.173.09:00:08.98#ibcon#read 4, iclass 3, count 0 2006.173.09:00:08.98#ibcon#about to read 5, iclass 3, count 0 2006.173.09:00:08.98#ibcon#read 5, iclass 3, count 0 2006.173.09:00:08.98#ibcon#about to read 6, iclass 3, count 0 2006.173.09:00:08.98#ibcon#read 6, iclass 3, count 0 2006.173.09:00:08.98#ibcon#end of sib2, iclass 3, count 0 2006.173.09:00:08.98#ibcon#*mode == 0, iclass 3, count 0 2006.173.09:00:08.98#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.09:00:08.98#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.09:00:08.98#ibcon#*before write, iclass 3, count 0 2006.173.09:00:08.98#ibcon#enter sib2, iclass 3, count 0 2006.173.09:00:08.98#ibcon#flushed, iclass 3, count 0 2006.173.09:00:08.98#ibcon#about to write, iclass 3, count 0 2006.173.09:00:08.98#ibcon#wrote, iclass 3, count 0 2006.173.09:00:08.98#ibcon#about to read 3, iclass 3, count 0 2006.173.09:00:09.02#ibcon#read 3, iclass 3, count 0 2006.173.09:00:09.02#ibcon#about to read 4, iclass 3, count 0 2006.173.09:00:09.02#ibcon#read 4, iclass 3, count 0 2006.173.09:00:09.02#ibcon#about to read 5, iclass 3, count 0 2006.173.09:00:09.02#ibcon#read 5, iclass 3, count 0 2006.173.09:00:09.02#ibcon#about to read 6, iclass 3, count 0 2006.173.09:00:09.02#ibcon#read 6, iclass 3, count 0 2006.173.09:00:09.02#ibcon#end of sib2, iclass 3, count 0 2006.173.09:00:09.02#ibcon#*after write, iclass 3, count 0 2006.173.09:00:09.02#ibcon#*before return 0, iclass 3, count 0 2006.173.09:00:09.02#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.09:00:09.02#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.09:00:09.02#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.09:00:09.02#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.09:00:09.02$vck44/vb=7,4 2006.173.09:00:09.02#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.09:00:09.02#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.09:00:09.02#ibcon#ireg 11 cls_cnt 2 2006.173.09:00:09.02#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.09:00:09.08#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.09:00:09.08#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.09:00:09.08#ibcon#enter wrdev, iclass 5, count 2 2006.173.09:00:09.08#ibcon#first serial, iclass 5, count 2 2006.173.09:00:09.08#ibcon#enter sib2, iclass 5, count 2 2006.173.09:00:09.08#ibcon#flushed, iclass 5, count 2 2006.173.09:00:09.08#ibcon#about to write, iclass 5, count 2 2006.173.09:00:09.08#ibcon#wrote, iclass 5, count 2 2006.173.09:00:09.08#ibcon#about to read 3, iclass 5, count 2 2006.173.09:00:09.10#ibcon#read 3, iclass 5, count 2 2006.173.09:00:09.10#ibcon#about to read 4, iclass 5, count 2 2006.173.09:00:09.10#ibcon#read 4, iclass 5, count 2 2006.173.09:00:09.10#ibcon#about to read 5, iclass 5, count 2 2006.173.09:00:09.10#ibcon#read 5, iclass 5, count 2 2006.173.09:00:09.10#ibcon#about to read 6, iclass 5, count 2 2006.173.09:00:09.10#ibcon#read 6, iclass 5, count 2 2006.173.09:00:09.10#ibcon#end of sib2, iclass 5, count 2 2006.173.09:00:09.10#ibcon#*mode == 0, iclass 5, count 2 2006.173.09:00:09.10#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.09:00:09.10#ibcon#[27=AT07-04\r\n] 2006.173.09:00:09.10#ibcon#*before write, iclass 5, count 2 2006.173.09:00:09.10#ibcon#enter sib2, iclass 5, count 2 2006.173.09:00:09.10#ibcon#flushed, iclass 5, count 2 2006.173.09:00:09.10#ibcon#about to write, iclass 5, count 2 2006.173.09:00:09.10#ibcon#wrote, iclass 5, count 2 2006.173.09:00:09.10#ibcon#about to read 3, iclass 5, count 2 2006.173.09:00:09.13#ibcon#read 3, iclass 5, count 2 2006.173.09:00:09.13#ibcon#about to read 4, iclass 5, count 2 2006.173.09:00:09.13#ibcon#read 4, iclass 5, count 2 2006.173.09:00:09.13#ibcon#about to read 5, iclass 5, count 2 2006.173.09:00:09.13#ibcon#read 5, iclass 5, count 2 2006.173.09:00:09.13#ibcon#about to read 6, iclass 5, count 2 2006.173.09:00:09.13#ibcon#read 6, iclass 5, count 2 2006.173.09:00:09.13#ibcon#end of sib2, iclass 5, count 2 2006.173.09:00:09.13#ibcon#*after write, iclass 5, count 2 2006.173.09:00:09.13#ibcon#*before return 0, iclass 5, count 2 2006.173.09:00:09.13#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.09:00:09.13#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.09:00:09.13#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.09:00:09.13#ibcon#ireg 7 cls_cnt 0 2006.173.09:00:09.13#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.09:00:09.25#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.09:00:09.25#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.09:00:09.25#ibcon#enter wrdev, iclass 5, count 0 2006.173.09:00:09.25#ibcon#first serial, iclass 5, count 0 2006.173.09:00:09.25#ibcon#enter sib2, iclass 5, count 0 2006.173.09:00:09.25#ibcon#flushed, iclass 5, count 0 2006.173.09:00:09.25#ibcon#about to write, iclass 5, count 0 2006.173.09:00:09.25#ibcon#wrote, iclass 5, count 0 2006.173.09:00:09.25#ibcon#about to read 3, iclass 5, count 0 2006.173.09:00:09.27#ibcon#read 3, iclass 5, count 0 2006.173.09:00:09.27#ibcon#about to read 4, iclass 5, count 0 2006.173.09:00:09.27#ibcon#read 4, iclass 5, count 0 2006.173.09:00:09.27#ibcon#about to read 5, iclass 5, count 0 2006.173.09:00:09.27#ibcon#read 5, iclass 5, count 0 2006.173.09:00:09.27#ibcon#about to read 6, iclass 5, count 0 2006.173.09:00:09.27#ibcon#read 6, iclass 5, count 0 2006.173.09:00:09.27#ibcon#end of sib2, iclass 5, count 0 2006.173.09:00:09.27#ibcon#*mode == 0, iclass 5, count 0 2006.173.09:00:09.27#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.09:00:09.27#ibcon#[27=USB\r\n] 2006.173.09:00:09.27#ibcon#*before write, iclass 5, count 0 2006.173.09:00:09.27#ibcon#enter sib2, iclass 5, count 0 2006.173.09:00:09.27#ibcon#flushed, iclass 5, count 0 2006.173.09:00:09.27#ibcon#about to write, iclass 5, count 0 2006.173.09:00:09.27#ibcon#wrote, iclass 5, count 0 2006.173.09:00:09.27#ibcon#about to read 3, iclass 5, count 0 2006.173.09:00:09.30#ibcon#read 3, iclass 5, count 0 2006.173.09:00:09.30#ibcon#about to read 4, iclass 5, count 0 2006.173.09:00:09.30#ibcon#read 4, iclass 5, count 0 2006.173.09:00:09.30#ibcon#about to read 5, iclass 5, count 0 2006.173.09:00:09.30#ibcon#read 5, iclass 5, count 0 2006.173.09:00:09.30#ibcon#about to read 6, iclass 5, count 0 2006.173.09:00:09.30#ibcon#read 6, iclass 5, count 0 2006.173.09:00:09.30#ibcon#end of sib2, iclass 5, count 0 2006.173.09:00:09.30#ibcon#*after write, iclass 5, count 0 2006.173.09:00:09.30#ibcon#*before return 0, iclass 5, count 0 2006.173.09:00:09.30#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.09:00:09.30#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.09:00:09.30#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.09:00:09.30#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.09:00:09.30$vck44/vblo=8,744.99 2006.173.09:00:09.30#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.09:00:09.30#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.09:00:09.30#ibcon#ireg 17 cls_cnt 0 2006.173.09:00:09.30#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.09:00:09.30#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.09:00:09.30#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.09:00:09.30#ibcon#enter wrdev, iclass 7, count 0 2006.173.09:00:09.30#ibcon#first serial, iclass 7, count 0 2006.173.09:00:09.30#ibcon#enter sib2, iclass 7, count 0 2006.173.09:00:09.30#ibcon#flushed, iclass 7, count 0 2006.173.09:00:09.30#ibcon#about to write, iclass 7, count 0 2006.173.09:00:09.30#ibcon#wrote, iclass 7, count 0 2006.173.09:00:09.30#ibcon#about to read 3, iclass 7, count 0 2006.173.09:00:09.32#ibcon#read 3, iclass 7, count 0 2006.173.09:00:09.32#ibcon#about to read 4, iclass 7, count 0 2006.173.09:00:09.32#ibcon#read 4, iclass 7, count 0 2006.173.09:00:09.32#ibcon#about to read 5, iclass 7, count 0 2006.173.09:00:09.32#ibcon#read 5, iclass 7, count 0 2006.173.09:00:09.32#ibcon#about to read 6, iclass 7, count 0 2006.173.09:00:09.32#ibcon#read 6, iclass 7, count 0 2006.173.09:00:09.32#ibcon#end of sib2, iclass 7, count 0 2006.173.09:00:09.32#ibcon#*mode == 0, iclass 7, count 0 2006.173.09:00:09.32#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.09:00:09.32#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.09:00:09.32#ibcon#*before write, iclass 7, count 0 2006.173.09:00:09.32#ibcon#enter sib2, iclass 7, count 0 2006.173.09:00:09.32#ibcon#flushed, iclass 7, count 0 2006.173.09:00:09.32#ibcon#about to write, iclass 7, count 0 2006.173.09:00:09.32#ibcon#wrote, iclass 7, count 0 2006.173.09:00:09.32#ibcon#about to read 3, iclass 7, count 0 2006.173.09:00:09.36#ibcon#read 3, iclass 7, count 0 2006.173.09:00:09.36#ibcon#about to read 4, iclass 7, count 0 2006.173.09:00:09.36#ibcon#read 4, iclass 7, count 0 2006.173.09:00:09.36#ibcon#about to read 5, iclass 7, count 0 2006.173.09:00:09.36#ibcon#read 5, iclass 7, count 0 2006.173.09:00:09.36#ibcon#about to read 6, iclass 7, count 0 2006.173.09:00:09.36#ibcon#read 6, iclass 7, count 0 2006.173.09:00:09.36#ibcon#end of sib2, iclass 7, count 0 2006.173.09:00:09.36#ibcon#*after write, iclass 7, count 0 2006.173.09:00:09.36#ibcon#*before return 0, iclass 7, count 0 2006.173.09:00:09.36#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.09:00:09.36#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.09:00:09.36#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.09:00:09.36#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.09:00:09.36$vck44/vb=8,4 2006.173.09:00:09.36#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.09:00:09.36#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.09:00:09.36#ibcon#ireg 11 cls_cnt 2 2006.173.09:00:09.36#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.09:00:09.42#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.09:00:09.42#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.09:00:09.42#ibcon#enter wrdev, iclass 11, count 2 2006.173.09:00:09.42#ibcon#first serial, iclass 11, count 2 2006.173.09:00:09.42#ibcon#enter sib2, iclass 11, count 2 2006.173.09:00:09.42#ibcon#flushed, iclass 11, count 2 2006.173.09:00:09.42#ibcon#about to write, iclass 11, count 2 2006.173.09:00:09.42#ibcon#wrote, iclass 11, count 2 2006.173.09:00:09.42#ibcon#about to read 3, iclass 11, count 2 2006.173.09:00:09.44#ibcon#read 3, iclass 11, count 2 2006.173.09:00:09.44#ibcon#about to read 4, iclass 11, count 2 2006.173.09:00:09.44#ibcon#read 4, iclass 11, count 2 2006.173.09:00:09.44#ibcon#about to read 5, iclass 11, count 2 2006.173.09:00:09.44#ibcon#read 5, iclass 11, count 2 2006.173.09:00:09.44#ibcon#about to read 6, iclass 11, count 2 2006.173.09:00:09.44#ibcon#read 6, iclass 11, count 2 2006.173.09:00:09.44#ibcon#end of sib2, iclass 11, count 2 2006.173.09:00:09.44#ibcon#*mode == 0, iclass 11, count 2 2006.173.09:00:09.44#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.09:00:09.44#ibcon#[27=AT08-04\r\n] 2006.173.09:00:09.44#ibcon#*before write, iclass 11, count 2 2006.173.09:00:09.44#ibcon#enter sib2, iclass 11, count 2 2006.173.09:00:09.44#ibcon#flushed, iclass 11, count 2 2006.173.09:00:09.44#ibcon#about to write, iclass 11, count 2 2006.173.09:00:09.44#ibcon#wrote, iclass 11, count 2 2006.173.09:00:09.44#ibcon#about to read 3, iclass 11, count 2 2006.173.09:00:09.47#ibcon#read 3, iclass 11, count 2 2006.173.09:00:09.47#ibcon#about to read 4, iclass 11, count 2 2006.173.09:00:09.47#ibcon#read 4, iclass 11, count 2 2006.173.09:00:09.47#ibcon#about to read 5, iclass 11, count 2 2006.173.09:00:09.47#ibcon#read 5, iclass 11, count 2 2006.173.09:00:09.47#ibcon#about to read 6, iclass 11, count 2 2006.173.09:00:09.47#ibcon#read 6, iclass 11, count 2 2006.173.09:00:09.47#ibcon#end of sib2, iclass 11, count 2 2006.173.09:00:09.47#ibcon#*after write, iclass 11, count 2 2006.173.09:00:09.47#ibcon#*before return 0, iclass 11, count 2 2006.173.09:00:09.47#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.09:00:09.47#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.09:00:09.47#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.09:00:09.47#ibcon#ireg 7 cls_cnt 0 2006.173.09:00:09.47#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.09:00:09.59#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.09:00:09.59#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.09:00:09.59#ibcon#enter wrdev, iclass 11, count 0 2006.173.09:00:09.59#ibcon#first serial, iclass 11, count 0 2006.173.09:00:09.59#ibcon#enter sib2, iclass 11, count 0 2006.173.09:00:09.59#ibcon#flushed, iclass 11, count 0 2006.173.09:00:09.59#ibcon#about to write, iclass 11, count 0 2006.173.09:00:09.59#ibcon#wrote, iclass 11, count 0 2006.173.09:00:09.59#ibcon#about to read 3, iclass 11, count 0 2006.173.09:00:09.61#ibcon#read 3, iclass 11, count 0 2006.173.09:00:09.61#ibcon#about to read 4, iclass 11, count 0 2006.173.09:00:09.61#ibcon#read 4, iclass 11, count 0 2006.173.09:00:09.61#ibcon#about to read 5, iclass 11, count 0 2006.173.09:00:09.61#ibcon#read 5, iclass 11, count 0 2006.173.09:00:09.61#ibcon#about to read 6, iclass 11, count 0 2006.173.09:00:09.61#ibcon#read 6, iclass 11, count 0 2006.173.09:00:09.61#ibcon#end of sib2, iclass 11, count 0 2006.173.09:00:09.61#ibcon#*mode == 0, iclass 11, count 0 2006.173.09:00:09.61#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.09:00:09.61#ibcon#[27=USB\r\n] 2006.173.09:00:09.61#ibcon#*before write, iclass 11, count 0 2006.173.09:00:09.61#ibcon#enter sib2, iclass 11, count 0 2006.173.09:00:09.61#ibcon#flushed, iclass 11, count 0 2006.173.09:00:09.61#ibcon#about to write, iclass 11, count 0 2006.173.09:00:09.61#ibcon#wrote, iclass 11, count 0 2006.173.09:00:09.61#ibcon#about to read 3, iclass 11, count 0 2006.173.09:00:09.64#ibcon#read 3, iclass 11, count 0 2006.173.09:00:09.64#ibcon#about to read 4, iclass 11, count 0 2006.173.09:00:09.64#ibcon#read 4, iclass 11, count 0 2006.173.09:00:09.64#ibcon#about to read 5, iclass 11, count 0 2006.173.09:00:09.64#ibcon#read 5, iclass 11, count 0 2006.173.09:00:09.64#ibcon#about to read 6, iclass 11, count 0 2006.173.09:00:09.64#ibcon#read 6, iclass 11, count 0 2006.173.09:00:09.64#ibcon#end of sib2, iclass 11, count 0 2006.173.09:00:09.64#ibcon#*after write, iclass 11, count 0 2006.173.09:00:09.64#ibcon#*before return 0, iclass 11, count 0 2006.173.09:00:09.64#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.09:00:09.64#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.09:00:09.64#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.09:00:09.64#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.09:00:09.64$vck44/vabw=wide 2006.173.09:00:09.64#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.09:00:09.64#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.09:00:09.64#ibcon#ireg 8 cls_cnt 0 2006.173.09:00:09.64#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.09:00:09.64#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.09:00:09.64#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.09:00:09.64#ibcon#enter wrdev, iclass 13, count 0 2006.173.09:00:09.64#ibcon#first serial, iclass 13, count 0 2006.173.09:00:09.64#ibcon#enter sib2, iclass 13, count 0 2006.173.09:00:09.64#ibcon#flushed, iclass 13, count 0 2006.173.09:00:09.64#ibcon#about to write, iclass 13, count 0 2006.173.09:00:09.64#ibcon#wrote, iclass 13, count 0 2006.173.09:00:09.64#ibcon#about to read 3, iclass 13, count 0 2006.173.09:00:09.66#ibcon#read 3, iclass 13, count 0 2006.173.09:00:09.66#ibcon#about to read 4, iclass 13, count 0 2006.173.09:00:09.66#ibcon#read 4, iclass 13, count 0 2006.173.09:00:09.66#ibcon#about to read 5, iclass 13, count 0 2006.173.09:00:09.66#ibcon#read 5, iclass 13, count 0 2006.173.09:00:09.66#ibcon#about to read 6, iclass 13, count 0 2006.173.09:00:09.66#ibcon#read 6, iclass 13, count 0 2006.173.09:00:09.66#ibcon#end of sib2, iclass 13, count 0 2006.173.09:00:09.66#ibcon#*mode == 0, iclass 13, count 0 2006.173.09:00:09.66#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.09:00:09.66#ibcon#[25=BW32\r\n] 2006.173.09:00:09.66#ibcon#*before write, iclass 13, count 0 2006.173.09:00:09.66#ibcon#enter sib2, iclass 13, count 0 2006.173.09:00:09.66#ibcon#flushed, iclass 13, count 0 2006.173.09:00:09.66#ibcon#about to write, iclass 13, count 0 2006.173.09:00:09.66#ibcon#wrote, iclass 13, count 0 2006.173.09:00:09.66#ibcon#about to read 3, iclass 13, count 0 2006.173.09:00:09.69#ibcon#read 3, iclass 13, count 0 2006.173.09:00:09.69#ibcon#about to read 4, iclass 13, count 0 2006.173.09:00:09.69#ibcon#read 4, iclass 13, count 0 2006.173.09:00:09.69#ibcon#about to read 5, iclass 13, count 0 2006.173.09:00:09.69#ibcon#read 5, iclass 13, count 0 2006.173.09:00:09.69#ibcon#about to read 6, iclass 13, count 0 2006.173.09:00:09.69#ibcon#read 6, iclass 13, count 0 2006.173.09:00:09.69#ibcon#end of sib2, iclass 13, count 0 2006.173.09:00:09.69#ibcon#*after write, iclass 13, count 0 2006.173.09:00:09.69#ibcon#*before return 0, iclass 13, count 0 2006.173.09:00:09.69#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.09:00:09.69#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.09:00:09.69#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.09:00:09.69#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.09:00:09.69$vck44/vbbw=wide 2006.173.09:00:09.69#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.09:00:09.69#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.09:00:09.69#ibcon#ireg 8 cls_cnt 0 2006.173.09:00:09.69#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.09:00:09.76#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.09:00:09.76#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.09:00:09.76#ibcon#enter wrdev, iclass 15, count 0 2006.173.09:00:09.76#ibcon#first serial, iclass 15, count 0 2006.173.09:00:09.76#ibcon#enter sib2, iclass 15, count 0 2006.173.09:00:09.76#ibcon#flushed, iclass 15, count 0 2006.173.09:00:09.76#ibcon#about to write, iclass 15, count 0 2006.173.09:00:09.76#ibcon#wrote, iclass 15, count 0 2006.173.09:00:09.76#ibcon#about to read 3, iclass 15, count 0 2006.173.09:00:09.78#ibcon#read 3, iclass 15, count 0 2006.173.09:00:09.78#ibcon#about to read 4, iclass 15, count 0 2006.173.09:00:09.78#ibcon#read 4, iclass 15, count 0 2006.173.09:00:09.78#ibcon#about to read 5, iclass 15, count 0 2006.173.09:00:09.78#ibcon#read 5, iclass 15, count 0 2006.173.09:00:09.78#ibcon#about to read 6, iclass 15, count 0 2006.173.09:00:09.78#ibcon#read 6, iclass 15, count 0 2006.173.09:00:09.78#ibcon#end of sib2, iclass 15, count 0 2006.173.09:00:09.78#ibcon#*mode == 0, iclass 15, count 0 2006.173.09:00:09.78#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.09:00:09.78#ibcon#[27=BW32\r\n] 2006.173.09:00:09.78#ibcon#*before write, iclass 15, count 0 2006.173.09:00:09.78#ibcon#enter sib2, iclass 15, count 0 2006.173.09:00:09.78#ibcon#flushed, iclass 15, count 0 2006.173.09:00:09.78#ibcon#about to write, iclass 15, count 0 2006.173.09:00:09.78#ibcon#wrote, iclass 15, count 0 2006.173.09:00:09.78#ibcon#about to read 3, iclass 15, count 0 2006.173.09:00:09.81#ibcon#read 3, iclass 15, count 0 2006.173.09:00:09.81#ibcon#about to read 4, iclass 15, count 0 2006.173.09:00:09.81#ibcon#read 4, iclass 15, count 0 2006.173.09:00:09.81#ibcon#about to read 5, iclass 15, count 0 2006.173.09:00:09.81#ibcon#read 5, iclass 15, count 0 2006.173.09:00:09.81#ibcon#about to read 6, iclass 15, count 0 2006.173.09:00:09.81#ibcon#read 6, iclass 15, count 0 2006.173.09:00:09.81#ibcon#end of sib2, iclass 15, count 0 2006.173.09:00:09.81#ibcon#*after write, iclass 15, count 0 2006.173.09:00:09.81#ibcon#*before return 0, iclass 15, count 0 2006.173.09:00:09.81#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.09:00:09.81#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.09:00:09.81#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.09:00:09.81#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.09:00:09.81$setupk4/ifdk4 2006.173.09:00:09.81$ifdk4/lo= 2006.173.09:00:09.81$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.09:00:09.81$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.09:00:09.81$ifdk4/patch= 2006.173.09:00:09.81$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.09:00:09.81$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.09:00:09.81$setupk4/!*+20s 2006.173.09:00:16.91#abcon#<5=/16 0.7 1.2 23.06 871004.4\r\n> 2006.173.09:00:16.93#abcon#{5=INTERFACE CLEAR} 2006.173.09:00:16.99#abcon#[5=S1D000X0/0*\r\n] 2006.173.09:00:22.13#trakl#Source acquired 2006.173.09:00:22.25$setupk4/"tpicd 2006.173.09:00:22.25$setupk4/echo=off 2006.173.09:00:22.25$setupk4/xlog=off 2006.173.09:00:22.25:!2006.173.09:09:31 2006.173.09:00:24.13#flagr#flagr/antenna,acquired 2006.173.09:09:31.01:preob 2006.173.09:09:32.13/onsource/TRACKING 2006.173.09:09:32.13:!2006.173.09:09:41 2006.173.09:09:41.01:"tape 2006.173.09:09:41.01:"st=record 2006.173.09:09:41.01:data_valid=on 2006.173.09:09:41.02:midob 2006.173.09:09:42.13/onsource/TRACKING 2006.173.09:09:42.14/wx/22.99,1004.5,88 2006.173.09:09:42.32/cable/+6.5023E-03 2006.173.09:09:43.41/va/01,07,usb,yes,43,46 2006.173.09:09:43.41/va/02,06,usb,yes,43,43 2006.173.09:09:43.41/va/03,05,usb,yes,53,56 2006.173.09:09:43.41/va/04,06,usb,yes,43,45 2006.173.09:09:43.41/va/05,04,usb,yes,34,34 2006.173.09:09:43.41/va/06,03,usb,yes,47,47 2006.173.09:09:43.41/va/07,04,usb,yes,39,40 2006.173.09:09:43.41/va/08,04,usb,yes,33,40 2006.173.09:09:43.64/valo/01,524.99,yes,locked 2006.173.09:09:43.64/valo/02,534.99,yes,locked 2006.173.09:09:43.64/valo/03,564.99,yes,locked 2006.173.09:09:43.64/valo/04,624.99,yes,locked 2006.173.09:09:43.64/valo/05,734.99,yes,locked 2006.173.09:09:43.64/valo/06,814.99,yes,locked 2006.173.09:09:43.64/valo/07,864.99,yes,locked 2006.173.09:09:43.64/valo/08,884.99,yes,locked 2006.173.09:09:44.73/vb/01,04,usb,yes,32,30 2006.173.09:09:44.73/vb/02,04,usb,yes,35,34 2006.173.09:09:44.73/vb/03,04,usb,yes,31,35 2006.173.09:09:44.73/vb/04,04,usb,yes,36,35 2006.173.09:09:44.73/vb/05,04,usb,yes,28,31 2006.173.09:09:44.73/vb/06,04,usb,yes,33,29 2006.173.09:09:44.73/vb/07,04,usb,yes,33,33 2006.173.09:09:44.73/vb/08,04,usb,yes,30,34 2006.173.09:09:44.97/vblo/01,629.99,yes,locked 2006.173.09:09:44.97/vblo/02,634.99,yes,locked 2006.173.09:09:44.97/vblo/03,649.99,yes,locked 2006.173.09:09:44.97/vblo/04,679.99,yes,locked 2006.173.09:09:44.97/vblo/05,709.99,yes,locked 2006.173.09:09:44.97/vblo/06,719.99,yes,locked 2006.173.09:09:44.97/vblo/07,734.99,yes,locked 2006.173.09:09:44.97/vblo/08,744.99,yes,locked 2006.173.09:09:45.12/vabw/8 2006.173.09:09:45.27/vbbw/8 2006.173.09:09:45.36/xfe/off,on,15.0 2006.173.09:09:45.76/ifatt/23,28,28,28 2006.173.09:09:46.07/fmout-gps/S +3.99E-07 2006.173.09:09:46.12:!2006.173.09:10:41 2006.173.09:10:41.01:data_valid=off 2006.173.09:10:41.02:"et 2006.173.09:10:41.02:!+3s 2006.173.09:10:44.05:"tape 2006.173.09:10:44.06:postob 2006.173.09:10:44.24/cable/+6.5006E-03 2006.173.09:10:44.25/wx/22.99,1004.5,88 2006.173.09:10:44.30/fmout-gps/S +4.00E-07 2006.173.09:10:44.31:scan_name=173-0915,jd0606,40 2006.173.09:10:44.31:source=1741-038,174358.86,-035004.6,2000.0,cw 2006.173.09:10:45.14#flagr#flagr/antenna,new-source 2006.173.09:10:45.15:checkk5 2006.173.09:10:45.51/chk_autoobs//k5ts1/ autoobs is running! 2006.173.09:10:45.92/chk_autoobs//k5ts2/ autoobs is running! 2006.173.09:10:46.34/chk_autoobs//k5ts3/ autoobs is running! 2006.173.09:10:46.75/chk_autoobs//k5ts4/ autoobs is running! 2006.173.09:10:47.14/chk_obsdata//k5ts1/T1730909??a.dat file size is correct (nominal:240MB, actual:236MB). 2006.173.09:10:47.54/chk_obsdata//k5ts2/T1730909??b.dat file size is correct (nominal:240MB, actual:236MB). 2006.173.09:10:47.94/chk_obsdata//k5ts3/T1730909??c.dat file size is correct (nominal:240MB, actual:236MB). 2006.173.09:10:48.35/chk_obsdata//k5ts4/T1730909??d.dat file size is correct (nominal:240MB, actual:236MB). 2006.173.09:10:49.07/k5log//k5ts1_log_newline 2006.173.09:10:49.78/k5log//k5ts2_log_newline 2006.173.09:10:50.49/k5log//k5ts3_log_newline 2006.173.09:10:51.22/k5log//k5ts4_log_newline 2006.173.09:10:51.24/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.09:10:51.24:setupk4=1 2006.173.09:10:51.24$setupk4/echo=on 2006.173.09:10:51.24$setupk4/pcalon 2006.173.09:10:51.24$pcalon/"no phase cal control is implemented here 2006.173.09:10:51.24$setupk4/"tpicd=stop 2006.173.09:10:51.24$setupk4/"rec=synch_on 2006.173.09:10:51.24$setupk4/"rec_mode=128 2006.173.09:10:51.24$setupk4/!* 2006.173.09:10:51.24$setupk4/recpk4 2006.173.09:10:51.24$recpk4/recpatch= 2006.173.09:10:51.24$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.09:10:51.24$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.09:10:51.24$setupk4/vck44 2006.173.09:10:51.25$vck44/valo=1,524.99 2006.173.09:10:51.25#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.09:10:51.25#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.09:10:51.25#ibcon#ireg 17 cls_cnt 0 2006.173.09:10:51.25#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.09:10:51.25#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.09:10:51.25#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.09:10:51.25#ibcon#enter wrdev, iclass 20, count 0 2006.173.09:10:51.25#ibcon#first serial, iclass 20, count 0 2006.173.09:10:51.25#ibcon#enter sib2, iclass 20, count 0 2006.173.09:10:51.25#ibcon#flushed, iclass 20, count 0 2006.173.09:10:51.25#ibcon#about to write, iclass 20, count 0 2006.173.09:10:51.25#ibcon#wrote, iclass 20, count 0 2006.173.09:10:51.25#ibcon#about to read 3, iclass 20, count 0 2006.173.09:10:51.26#ibcon#read 3, iclass 20, count 0 2006.173.09:10:51.26#ibcon#about to read 4, iclass 20, count 0 2006.173.09:10:51.26#ibcon#read 4, iclass 20, count 0 2006.173.09:10:51.26#ibcon#about to read 5, iclass 20, count 0 2006.173.09:10:51.26#ibcon#read 5, iclass 20, count 0 2006.173.09:10:51.26#ibcon#about to read 6, iclass 20, count 0 2006.173.09:10:51.26#ibcon#read 6, iclass 20, count 0 2006.173.09:10:51.26#ibcon#end of sib2, iclass 20, count 0 2006.173.09:10:51.26#ibcon#*mode == 0, iclass 20, count 0 2006.173.09:10:51.26#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.09:10:51.26#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.09:10:51.26#ibcon#*before write, iclass 20, count 0 2006.173.09:10:51.26#ibcon#enter sib2, iclass 20, count 0 2006.173.09:10:51.26#ibcon#flushed, iclass 20, count 0 2006.173.09:10:51.26#ibcon#about to write, iclass 20, count 0 2006.173.09:10:51.26#ibcon#wrote, iclass 20, count 0 2006.173.09:10:51.26#ibcon#about to read 3, iclass 20, count 0 2006.173.09:10:51.31#ibcon#read 3, iclass 20, count 0 2006.173.09:10:51.31#ibcon#about to read 4, iclass 20, count 0 2006.173.09:10:51.31#ibcon#read 4, iclass 20, count 0 2006.173.09:10:51.31#ibcon#about to read 5, iclass 20, count 0 2006.173.09:10:51.31#ibcon#read 5, iclass 20, count 0 2006.173.09:10:51.31#ibcon#about to read 6, iclass 20, count 0 2006.173.09:10:51.31#ibcon#read 6, iclass 20, count 0 2006.173.09:10:51.31#ibcon#end of sib2, iclass 20, count 0 2006.173.09:10:51.31#ibcon#*after write, iclass 20, count 0 2006.173.09:10:51.31#ibcon#*before return 0, iclass 20, count 0 2006.173.09:10:51.31#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.09:10:51.31#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.09:10:51.31#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.09:10:51.31#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.09:10:51.31$vck44/va=1,7 2006.173.09:10:51.31#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.09:10:51.31#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.09:10:51.31#ibcon#ireg 11 cls_cnt 2 2006.173.09:10:51.31#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.09:10:51.31#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.09:10:51.31#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.09:10:51.31#ibcon#enter wrdev, iclass 22, count 2 2006.173.09:10:51.31#ibcon#first serial, iclass 22, count 2 2006.173.09:10:51.31#ibcon#enter sib2, iclass 22, count 2 2006.173.09:10:51.31#ibcon#flushed, iclass 22, count 2 2006.173.09:10:51.31#ibcon#about to write, iclass 22, count 2 2006.173.09:10:51.31#ibcon#wrote, iclass 22, count 2 2006.173.09:10:51.31#ibcon#about to read 3, iclass 22, count 2 2006.173.09:10:51.33#ibcon#read 3, iclass 22, count 2 2006.173.09:10:51.33#ibcon#about to read 4, iclass 22, count 2 2006.173.09:10:51.33#ibcon#read 4, iclass 22, count 2 2006.173.09:10:51.33#ibcon#about to read 5, iclass 22, count 2 2006.173.09:10:51.33#ibcon#read 5, iclass 22, count 2 2006.173.09:10:51.33#ibcon#about to read 6, iclass 22, count 2 2006.173.09:10:51.33#ibcon#read 6, iclass 22, count 2 2006.173.09:10:51.33#ibcon#end of sib2, iclass 22, count 2 2006.173.09:10:51.33#ibcon#*mode == 0, iclass 22, count 2 2006.173.09:10:51.33#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.09:10:51.33#ibcon#[25=AT01-07\r\n] 2006.173.09:10:51.33#ibcon#*before write, iclass 22, count 2 2006.173.09:10:51.33#ibcon#enter sib2, iclass 22, count 2 2006.173.09:10:51.33#ibcon#flushed, iclass 22, count 2 2006.173.09:10:51.33#ibcon#about to write, iclass 22, count 2 2006.173.09:10:51.33#ibcon#wrote, iclass 22, count 2 2006.173.09:10:51.33#ibcon#about to read 3, iclass 22, count 2 2006.173.09:10:51.36#ibcon#read 3, iclass 22, count 2 2006.173.09:10:51.36#ibcon#about to read 4, iclass 22, count 2 2006.173.09:10:51.36#ibcon#read 4, iclass 22, count 2 2006.173.09:10:51.36#ibcon#about to read 5, iclass 22, count 2 2006.173.09:10:51.36#ibcon#read 5, iclass 22, count 2 2006.173.09:10:51.36#ibcon#about to read 6, iclass 22, count 2 2006.173.09:10:51.36#ibcon#read 6, iclass 22, count 2 2006.173.09:10:51.36#ibcon#end of sib2, iclass 22, count 2 2006.173.09:10:51.36#ibcon#*after write, iclass 22, count 2 2006.173.09:10:51.36#ibcon#*before return 0, iclass 22, count 2 2006.173.09:10:51.36#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.09:10:51.36#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.09:10:51.36#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.09:10:51.36#ibcon#ireg 7 cls_cnt 0 2006.173.09:10:51.36#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.09:10:51.48#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.09:10:51.48#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.09:10:51.48#ibcon#enter wrdev, iclass 22, count 0 2006.173.09:10:51.48#ibcon#first serial, iclass 22, count 0 2006.173.09:10:51.48#ibcon#enter sib2, iclass 22, count 0 2006.173.09:10:51.48#ibcon#flushed, iclass 22, count 0 2006.173.09:10:51.48#ibcon#about to write, iclass 22, count 0 2006.173.09:10:51.48#ibcon#wrote, iclass 22, count 0 2006.173.09:10:51.48#ibcon#about to read 3, iclass 22, count 0 2006.173.09:10:51.50#ibcon#read 3, iclass 22, count 0 2006.173.09:10:51.50#ibcon#about to read 4, iclass 22, count 0 2006.173.09:10:51.50#ibcon#read 4, iclass 22, count 0 2006.173.09:10:51.50#ibcon#about to read 5, iclass 22, count 0 2006.173.09:10:51.50#ibcon#read 5, iclass 22, count 0 2006.173.09:10:51.50#ibcon#about to read 6, iclass 22, count 0 2006.173.09:10:51.50#ibcon#read 6, iclass 22, count 0 2006.173.09:10:51.50#ibcon#end of sib2, iclass 22, count 0 2006.173.09:10:51.50#ibcon#*mode == 0, iclass 22, count 0 2006.173.09:10:51.50#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.09:10:51.50#ibcon#[25=USB\r\n] 2006.173.09:10:51.50#ibcon#*before write, iclass 22, count 0 2006.173.09:10:51.50#ibcon#enter sib2, iclass 22, count 0 2006.173.09:10:51.50#ibcon#flushed, iclass 22, count 0 2006.173.09:10:51.50#ibcon#about to write, iclass 22, count 0 2006.173.09:10:51.50#ibcon#wrote, iclass 22, count 0 2006.173.09:10:51.50#ibcon#about to read 3, iclass 22, count 0 2006.173.09:10:51.53#ibcon#read 3, iclass 22, count 0 2006.173.09:10:51.53#ibcon#about to read 4, iclass 22, count 0 2006.173.09:10:51.53#ibcon#read 4, iclass 22, count 0 2006.173.09:10:51.53#ibcon#about to read 5, iclass 22, count 0 2006.173.09:10:51.53#ibcon#read 5, iclass 22, count 0 2006.173.09:10:51.53#ibcon#about to read 6, iclass 22, count 0 2006.173.09:10:51.53#ibcon#read 6, iclass 22, count 0 2006.173.09:10:51.53#ibcon#end of sib2, iclass 22, count 0 2006.173.09:10:51.53#ibcon#*after write, iclass 22, count 0 2006.173.09:10:51.53#ibcon#*before return 0, iclass 22, count 0 2006.173.09:10:51.53#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.09:10:51.53#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.09:10:51.53#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.09:10:51.53#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.09:10:51.53$vck44/valo=2,534.99 2006.173.09:10:51.53#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.09:10:51.53#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.09:10:51.53#ibcon#ireg 17 cls_cnt 0 2006.173.09:10:51.53#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.09:10:51.53#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.09:10:51.53#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.09:10:51.53#ibcon#enter wrdev, iclass 24, count 0 2006.173.09:10:51.53#ibcon#first serial, iclass 24, count 0 2006.173.09:10:51.53#ibcon#enter sib2, iclass 24, count 0 2006.173.09:10:51.53#ibcon#flushed, iclass 24, count 0 2006.173.09:10:51.53#ibcon#about to write, iclass 24, count 0 2006.173.09:10:51.53#ibcon#wrote, iclass 24, count 0 2006.173.09:10:51.53#ibcon#about to read 3, iclass 24, count 0 2006.173.09:10:51.55#ibcon#read 3, iclass 24, count 0 2006.173.09:10:51.55#ibcon#about to read 4, iclass 24, count 0 2006.173.09:10:51.55#ibcon#read 4, iclass 24, count 0 2006.173.09:10:51.55#ibcon#about to read 5, iclass 24, count 0 2006.173.09:10:51.55#ibcon#read 5, iclass 24, count 0 2006.173.09:10:51.55#ibcon#about to read 6, iclass 24, count 0 2006.173.09:10:51.55#ibcon#read 6, iclass 24, count 0 2006.173.09:10:51.55#ibcon#end of sib2, iclass 24, count 0 2006.173.09:10:51.55#ibcon#*mode == 0, iclass 24, count 0 2006.173.09:10:51.55#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.09:10:51.55#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.09:10:51.55#ibcon#*before write, iclass 24, count 0 2006.173.09:10:51.55#ibcon#enter sib2, iclass 24, count 0 2006.173.09:10:51.55#ibcon#flushed, iclass 24, count 0 2006.173.09:10:51.55#ibcon#about to write, iclass 24, count 0 2006.173.09:10:51.55#ibcon#wrote, iclass 24, count 0 2006.173.09:10:51.55#ibcon#about to read 3, iclass 24, count 0 2006.173.09:10:51.59#ibcon#read 3, iclass 24, count 0 2006.173.09:10:51.59#ibcon#about to read 4, iclass 24, count 0 2006.173.09:10:51.59#ibcon#read 4, iclass 24, count 0 2006.173.09:10:51.59#ibcon#about to read 5, iclass 24, count 0 2006.173.09:10:51.59#ibcon#read 5, iclass 24, count 0 2006.173.09:10:51.59#ibcon#about to read 6, iclass 24, count 0 2006.173.09:10:51.59#ibcon#read 6, iclass 24, count 0 2006.173.09:10:51.59#ibcon#end of sib2, iclass 24, count 0 2006.173.09:10:51.59#ibcon#*after write, iclass 24, count 0 2006.173.09:10:51.59#ibcon#*before return 0, iclass 24, count 0 2006.173.09:10:51.59#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.09:10:51.59#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.09:10:51.59#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.09:10:51.59#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.09:10:51.59$vck44/va=2,6 2006.173.09:10:51.59#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.09:10:51.59#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.09:10:51.59#ibcon#ireg 11 cls_cnt 2 2006.173.09:10:51.59#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.09:10:51.65#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.09:10:51.65#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.09:10:51.65#ibcon#enter wrdev, iclass 26, count 2 2006.173.09:10:51.65#ibcon#first serial, iclass 26, count 2 2006.173.09:10:51.65#ibcon#enter sib2, iclass 26, count 2 2006.173.09:10:51.65#ibcon#flushed, iclass 26, count 2 2006.173.09:10:51.65#ibcon#about to write, iclass 26, count 2 2006.173.09:10:51.65#ibcon#wrote, iclass 26, count 2 2006.173.09:10:51.65#ibcon#about to read 3, iclass 26, count 2 2006.173.09:10:51.67#ibcon#read 3, iclass 26, count 2 2006.173.09:10:51.67#ibcon#about to read 4, iclass 26, count 2 2006.173.09:10:51.67#ibcon#read 4, iclass 26, count 2 2006.173.09:10:51.67#ibcon#about to read 5, iclass 26, count 2 2006.173.09:10:51.67#ibcon#read 5, iclass 26, count 2 2006.173.09:10:51.67#ibcon#about to read 6, iclass 26, count 2 2006.173.09:10:51.67#ibcon#read 6, iclass 26, count 2 2006.173.09:10:51.67#ibcon#end of sib2, iclass 26, count 2 2006.173.09:10:51.67#ibcon#*mode == 0, iclass 26, count 2 2006.173.09:10:51.67#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.09:10:51.67#ibcon#[25=AT02-06\r\n] 2006.173.09:10:51.67#ibcon#*before write, iclass 26, count 2 2006.173.09:10:51.67#ibcon#enter sib2, iclass 26, count 2 2006.173.09:10:51.67#ibcon#flushed, iclass 26, count 2 2006.173.09:10:51.67#ibcon#about to write, iclass 26, count 2 2006.173.09:10:51.67#ibcon#wrote, iclass 26, count 2 2006.173.09:10:51.67#ibcon#about to read 3, iclass 26, count 2 2006.173.09:10:51.70#ibcon#read 3, iclass 26, count 2 2006.173.09:10:51.70#ibcon#about to read 4, iclass 26, count 2 2006.173.09:10:51.70#ibcon#read 4, iclass 26, count 2 2006.173.09:10:51.70#ibcon#about to read 5, iclass 26, count 2 2006.173.09:10:51.70#ibcon#read 5, iclass 26, count 2 2006.173.09:10:51.70#ibcon#about to read 6, iclass 26, count 2 2006.173.09:10:51.70#ibcon#read 6, iclass 26, count 2 2006.173.09:10:51.70#ibcon#end of sib2, iclass 26, count 2 2006.173.09:10:51.70#ibcon#*after write, iclass 26, count 2 2006.173.09:10:51.70#ibcon#*before return 0, iclass 26, count 2 2006.173.09:10:51.70#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.09:10:51.70#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.09:10:51.70#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.09:10:51.70#ibcon#ireg 7 cls_cnt 0 2006.173.09:10:51.70#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.09:10:51.82#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.09:10:51.82#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.09:10:51.82#ibcon#enter wrdev, iclass 26, count 0 2006.173.09:10:51.82#ibcon#first serial, iclass 26, count 0 2006.173.09:10:51.82#ibcon#enter sib2, iclass 26, count 0 2006.173.09:10:51.82#ibcon#flushed, iclass 26, count 0 2006.173.09:10:51.82#ibcon#about to write, iclass 26, count 0 2006.173.09:10:51.82#ibcon#wrote, iclass 26, count 0 2006.173.09:10:51.82#ibcon#about to read 3, iclass 26, count 0 2006.173.09:10:51.84#ibcon#read 3, iclass 26, count 0 2006.173.09:10:51.84#ibcon#about to read 4, iclass 26, count 0 2006.173.09:10:51.84#ibcon#read 4, iclass 26, count 0 2006.173.09:10:51.84#ibcon#about to read 5, iclass 26, count 0 2006.173.09:10:51.84#ibcon#read 5, iclass 26, count 0 2006.173.09:10:51.84#ibcon#about to read 6, iclass 26, count 0 2006.173.09:10:51.84#ibcon#read 6, iclass 26, count 0 2006.173.09:10:51.84#ibcon#end of sib2, iclass 26, count 0 2006.173.09:10:51.84#ibcon#*mode == 0, iclass 26, count 0 2006.173.09:10:51.84#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.09:10:51.84#ibcon#[25=USB\r\n] 2006.173.09:10:51.84#ibcon#*before write, iclass 26, count 0 2006.173.09:10:51.84#ibcon#enter sib2, iclass 26, count 0 2006.173.09:10:51.84#ibcon#flushed, iclass 26, count 0 2006.173.09:10:51.84#ibcon#about to write, iclass 26, count 0 2006.173.09:10:51.84#ibcon#wrote, iclass 26, count 0 2006.173.09:10:51.84#ibcon#about to read 3, iclass 26, count 0 2006.173.09:10:51.87#ibcon#read 3, iclass 26, count 0 2006.173.09:10:51.87#ibcon#about to read 4, iclass 26, count 0 2006.173.09:10:51.87#ibcon#read 4, iclass 26, count 0 2006.173.09:10:51.87#ibcon#about to read 5, iclass 26, count 0 2006.173.09:10:51.87#ibcon#read 5, iclass 26, count 0 2006.173.09:10:51.87#ibcon#about to read 6, iclass 26, count 0 2006.173.09:10:51.87#ibcon#read 6, iclass 26, count 0 2006.173.09:10:51.87#ibcon#end of sib2, iclass 26, count 0 2006.173.09:10:51.87#ibcon#*after write, iclass 26, count 0 2006.173.09:10:51.87#ibcon#*before return 0, iclass 26, count 0 2006.173.09:10:51.87#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.09:10:51.87#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.09:10:51.87#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.09:10:51.87#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.09:10:51.87$vck44/valo=3,564.99 2006.173.09:10:51.87#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.09:10:51.87#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.09:10:51.87#ibcon#ireg 17 cls_cnt 0 2006.173.09:10:51.87#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.09:10:51.87#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.09:10:51.87#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.09:10:51.87#ibcon#enter wrdev, iclass 28, count 0 2006.173.09:10:51.87#ibcon#first serial, iclass 28, count 0 2006.173.09:10:51.87#ibcon#enter sib2, iclass 28, count 0 2006.173.09:10:51.87#ibcon#flushed, iclass 28, count 0 2006.173.09:10:51.87#ibcon#about to write, iclass 28, count 0 2006.173.09:10:51.87#ibcon#wrote, iclass 28, count 0 2006.173.09:10:51.87#ibcon#about to read 3, iclass 28, count 0 2006.173.09:10:51.89#ibcon#read 3, iclass 28, count 0 2006.173.09:10:51.89#ibcon#about to read 4, iclass 28, count 0 2006.173.09:10:51.89#ibcon#read 4, iclass 28, count 0 2006.173.09:10:51.89#ibcon#about to read 5, iclass 28, count 0 2006.173.09:10:51.89#ibcon#read 5, iclass 28, count 0 2006.173.09:10:51.89#ibcon#about to read 6, iclass 28, count 0 2006.173.09:10:51.89#ibcon#read 6, iclass 28, count 0 2006.173.09:10:51.89#ibcon#end of sib2, iclass 28, count 0 2006.173.09:10:51.89#ibcon#*mode == 0, iclass 28, count 0 2006.173.09:10:51.89#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.09:10:51.89#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.09:10:51.89#ibcon#*before write, iclass 28, count 0 2006.173.09:10:51.89#ibcon#enter sib2, iclass 28, count 0 2006.173.09:10:51.89#ibcon#flushed, iclass 28, count 0 2006.173.09:10:51.89#ibcon#about to write, iclass 28, count 0 2006.173.09:10:51.89#ibcon#wrote, iclass 28, count 0 2006.173.09:10:51.89#ibcon#about to read 3, iclass 28, count 0 2006.173.09:10:51.93#ibcon#read 3, iclass 28, count 0 2006.173.09:10:51.93#ibcon#about to read 4, iclass 28, count 0 2006.173.09:10:51.93#ibcon#read 4, iclass 28, count 0 2006.173.09:10:51.93#ibcon#about to read 5, iclass 28, count 0 2006.173.09:10:51.93#ibcon#read 5, iclass 28, count 0 2006.173.09:10:51.93#ibcon#about to read 6, iclass 28, count 0 2006.173.09:10:51.93#ibcon#read 6, iclass 28, count 0 2006.173.09:10:51.93#ibcon#end of sib2, iclass 28, count 0 2006.173.09:10:51.93#ibcon#*after write, iclass 28, count 0 2006.173.09:10:51.93#ibcon#*before return 0, iclass 28, count 0 2006.173.09:10:51.93#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.09:10:51.93#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.09:10:51.93#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.09:10:51.93#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.09:10:51.93$vck44/va=3,5 2006.173.09:10:51.93#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.09:10:51.93#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.09:10:51.93#ibcon#ireg 11 cls_cnt 2 2006.173.09:10:51.93#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.09:10:51.99#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.09:10:51.99#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.09:10:51.99#ibcon#enter wrdev, iclass 30, count 2 2006.173.09:10:51.99#ibcon#first serial, iclass 30, count 2 2006.173.09:10:51.99#ibcon#enter sib2, iclass 30, count 2 2006.173.09:10:51.99#ibcon#flushed, iclass 30, count 2 2006.173.09:10:51.99#ibcon#about to write, iclass 30, count 2 2006.173.09:10:51.99#ibcon#wrote, iclass 30, count 2 2006.173.09:10:51.99#ibcon#about to read 3, iclass 30, count 2 2006.173.09:10:52.01#ibcon#read 3, iclass 30, count 2 2006.173.09:10:52.01#ibcon#about to read 4, iclass 30, count 2 2006.173.09:10:52.01#ibcon#read 4, iclass 30, count 2 2006.173.09:10:52.01#ibcon#about to read 5, iclass 30, count 2 2006.173.09:10:52.01#ibcon#read 5, iclass 30, count 2 2006.173.09:10:52.01#ibcon#about to read 6, iclass 30, count 2 2006.173.09:10:52.01#ibcon#read 6, iclass 30, count 2 2006.173.09:10:52.01#ibcon#end of sib2, iclass 30, count 2 2006.173.09:10:52.01#ibcon#*mode == 0, iclass 30, count 2 2006.173.09:10:52.01#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.09:10:52.01#ibcon#[25=AT03-05\r\n] 2006.173.09:10:52.01#ibcon#*before write, iclass 30, count 2 2006.173.09:10:52.01#ibcon#enter sib2, iclass 30, count 2 2006.173.09:10:52.01#ibcon#flushed, iclass 30, count 2 2006.173.09:10:52.01#ibcon#about to write, iclass 30, count 2 2006.173.09:10:52.01#ibcon#wrote, iclass 30, count 2 2006.173.09:10:52.01#ibcon#about to read 3, iclass 30, count 2 2006.173.09:10:52.04#ibcon#read 3, iclass 30, count 2 2006.173.09:10:52.04#ibcon#about to read 4, iclass 30, count 2 2006.173.09:10:52.04#ibcon#read 4, iclass 30, count 2 2006.173.09:10:52.04#ibcon#about to read 5, iclass 30, count 2 2006.173.09:10:52.04#ibcon#read 5, iclass 30, count 2 2006.173.09:10:52.04#ibcon#about to read 6, iclass 30, count 2 2006.173.09:10:52.04#ibcon#read 6, iclass 30, count 2 2006.173.09:10:52.04#ibcon#end of sib2, iclass 30, count 2 2006.173.09:10:52.04#ibcon#*after write, iclass 30, count 2 2006.173.09:10:52.04#ibcon#*before return 0, iclass 30, count 2 2006.173.09:10:52.04#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.09:10:52.04#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.09:10:52.04#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.09:10:52.04#ibcon#ireg 7 cls_cnt 0 2006.173.09:10:52.04#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.09:10:52.16#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.09:10:52.16#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.09:10:52.16#ibcon#enter wrdev, iclass 30, count 0 2006.173.09:10:52.16#ibcon#first serial, iclass 30, count 0 2006.173.09:10:52.16#ibcon#enter sib2, iclass 30, count 0 2006.173.09:10:52.16#ibcon#flushed, iclass 30, count 0 2006.173.09:10:52.16#ibcon#about to write, iclass 30, count 0 2006.173.09:10:52.16#ibcon#wrote, iclass 30, count 0 2006.173.09:10:52.16#ibcon#about to read 3, iclass 30, count 0 2006.173.09:10:52.18#ibcon#read 3, iclass 30, count 0 2006.173.09:10:52.18#ibcon#about to read 4, iclass 30, count 0 2006.173.09:10:52.18#ibcon#read 4, iclass 30, count 0 2006.173.09:10:52.18#ibcon#about to read 5, iclass 30, count 0 2006.173.09:10:52.18#ibcon#read 5, iclass 30, count 0 2006.173.09:10:52.18#ibcon#about to read 6, iclass 30, count 0 2006.173.09:10:52.18#ibcon#read 6, iclass 30, count 0 2006.173.09:10:52.18#ibcon#end of sib2, iclass 30, count 0 2006.173.09:10:52.18#ibcon#*mode == 0, iclass 30, count 0 2006.173.09:10:52.18#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.09:10:52.18#ibcon#[25=USB\r\n] 2006.173.09:10:52.18#ibcon#*before write, iclass 30, count 0 2006.173.09:10:52.18#ibcon#enter sib2, iclass 30, count 0 2006.173.09:10:52.18#ibcon#flushed, iclass 30, count 0 2006.173.09:10:52.18#ibcon#about to write, iclass 30, count 0 2006.173.09:10:52.18#ibcon#wrote, iclass 30, count 0 2006.173.09:10:52.18#ibcon#about to read 3, iclass 30, count 0 2006.173.09:10:52.21#ibcon#read 3, iclass 30, count 0 2006.173.09:10:52.21#ibcon#about to read 4, iclass 30, count 0 2006.173.09:10:52.21#ibcon#read 4, iclass 30, count 0 2006.173.09:10:52.21#ibcon#about to read 5, iclass 30, count 0 2006.173.09:10:52.21#ibcon#read 5, iclass 30, count 0 2006.173.09:10:52.21#ibcon#about to read 6, iclass 30, count 0 2006.173.09:10:52.21#ibcon#read 6, iclass 30, count 0 2006.173.09:10:52.21#ibcon#end of sib2, iclass 30, count 0 2006.173.09:10:52.21#ibcon#*after write, iclass 30, count 0 2006.173.09:10:52.21#ibcon#*before return 0, iclass 30, count 0 2006.173.09:10:52.21#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.09:10:52.21#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.09:10:52.21#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.09:10:52.21#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.09:10:52.21$vck44/valo=4,624.99 2006.173.09:10:52.21#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.09:10:52.21#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.09:10:52.21#ibcon#ireg 17 cls_cnt 0 2006.173.09:10:52.21#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.09:10:52.21#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.09:10:52.21#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.09:10:52.21#ibcon#enter wrdev, iclass 32, count 0 2006.173.09:10:52.21#ibcon#first serial, iclass 32, count 0 2006.173.09:10:52.21#ibcon#enter sib2, iclass 32, count 0 2006.173.09:10:52.21#ibcon#flushed, iclass 32, count 0 2006.173.09:10:52.21#ibcon#about to write, iclass 32, count 0 2006.173.09:10:52.21#ibcon#wrote, iclass 32, count 0 2006.173.09:10:52.21#ibcon#about to read 3, iclass 32, count 0 2006.173.09:10:52.23#ibcon#read 3, iclass 32, count 0 2006.173.09:10:52.23#ibcon#about to read 4, iclass 32, count 0 2006.173.09:10:52.23#ibcon#read 4, iclass 32, count 0 2006.173.09:10:52.23#ibcon#about to read 5, iclass 32, count 0 2006.173.09:10:52.23#ibcon#read 5, iclass 32, count 0 2006.173.09:10:52.23#ibcon#about to read 6, iclass 32, count 0 2006.173.09:10:52.23#ibcon#read 6, iclass 32, count 0 2006.173.09:10:52.23#ibcon#end of sib2, iclass 32, count 0 2006.173.09:10:52.23#ibcon#*mode == 0, iclass 32, count 0 2006.173.09:10:52.23#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.09:10:52.23#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.09:10:52.23#ibcon#*before write, iclass 32, count 0 2006.173.09:10:52.23#ibcon#enter sib2, iclass 32, count 0 2006.173.09:10:52.23#ibcon#flushed, iclass 32, count 0 2006.173.09:10:52.23#ibcon#about to write, iclass 32, count 0 2006.173.09:10:52.23#ibcon#wrote, iclass 32, count 0 2006.173.09:10:52.23#ibcon#about to read 3, iclass 32, count 0 2006.173.09:10:52.27#ibcon#read 3, iclass 32, count 0 2006.173.09:10:52.27#ibcon#about to read 4, iclass 32, count 0 2006.173.09:10:52.27#ibcon#read 4, iclass 32, count 0 2006.173.09:10:52.27#ibcon#about to read 5, iclass 32, count 0 2006.173.09:10:52.27#ibcon#read 5, iclass 32, count 0 2006.173.09:10:52.27#ibcon#about to read 6, iclass 32, count 0 2006.173.09:10:52.27#ibcon#read 6, iclass 32, count 0 2006.173.09:10:52.27#ibcon#end of sib2, iclass 32, count 0 2006.173.09:10:52.27#ibcon#*after write, iclass 32, count 0 2006.173.09:10:52.27#ibcon#*before return 0, iclass 32, count 0 2006.173.09:10:52.27#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.09:10:52.27#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.09:10:52.27#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.09:10:52.27#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.09:10:52.27$vck44/va=4,6 2006.173.09:10:52.27#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.09:10:52.27#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.09:10:52.27#ibcon#ireg 11 cls_cnt 2 2006.173.09:10:52.27#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.09:10:52.33#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.09:10:52.33#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.09:10:52.33#ibcon#enter wrdev, iclass 34, count 2 2006.173.09:10:52.33#ibcon#first serial, iclass 34, count 2 2006.173.09:10:52.33#ibcon#enter sib2, iclass 34, count 2 2006.173.09:10:52.33#ibcon#flushed, iclass 34, count 2 2006.173.09:10:52.33#ibcon#about to write, iclass 34, count 2 2006.173.09:10:52.33#ibcon#wrote, iclass 34, count 2 2006.173.09:10:52.33#ibcon#about to read 3, iclass 34, count 2 2006.173.09:10:52.35#ibcon#read 3, iclass 34, count 2 2006.173.09:10:52.35#ibcon#about to read 4, iclass 34, count 2 2006.173.09:10:52.35#ibcon#read 4, iclass 34, count 2 2006.173.09:10:52.35#ibcon#about to read 5, iclass 34, count 2 2006.173.09:10:52.35#ibcon#read 5, iclass 34, count 2 2006.173.09:10:52.35#ibcon#about to read 6, iclass 34, count 2 2006.173.09:10:52.35#ibcon#read 6, iclass 34, count 2 2006.173.09:10:52.35#ibcon#end of sib2, iclass 34, count 2 2006.173.09:10:52.35#ibcon#*mode == 0, iclass 34, count 2 2006.173.09:10:52.35#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.09:10:52.35#ibcon#[25=AT04-06\r\n] 2006.173.09:10:52.35#ibcon#*before write, iclass 34, count 2 2006.173.09:10:52.35#ibcon#enter sib2, iclass 34, count 2 2006.173.09:10:52.35#ibcon#flushed, iclass 34, count 2 2006.173.09:10:52.35#ibcon#about to write, iclass 34, count 2 2006.173.09:10:52.35#ibcon#wrote, iclass 34, count 2 2006.173.09:10:52.35#ibcon#about to read 3, iclass 34, count 2 2006.173.09:10:52.38#ibcon#read 3, iclass 34, count 2 2006.173.09:10:52.38#ibcon#about to read 4, iclass 34, count 2 2006.173.09:10:52.38#ibcon#read 4, iclass 34, count 2 2006.173.09:10:52.38#ibcon#about to read 5, iclass 34, count 2 2006.173.09:10:52.38#ibcon#read 5, iclass 34, count 2 2006.173.09:10:52.38#ibcon#about to read 6, iclass 34, count 2 2006.173.09:10:52.38#ibcon#read 6, iclass 34, count 2 2006.173.09:10:52.38#ibcon#end of sib2, iclass 34, count 2 2006.173.09:10:52.38#ibcon#*after write, iclass 34, count 2 2006.173.09:10:52.38#ibcon#*before return 0, iclass 34, count 2 2006.173.09:10:52.38#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.09:10:52.38#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.09:10:52.38#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.09:10:52.38#ibcon#ireg 7 cls_cnt 0 2006.173.09:10:52.38#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.09:10:52.50#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.09:10:52.50#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.09:10:52.50#ibcon#enter wrdev, iclass 34, count 0 2006.173.09:10:52.50#ibcon#first serial, iclass 34, count 0 2006.173.09:10:52.50#ibcon#enter sib2, iclass 34, count 0 2006.173.09:10:52.50#ibcon#flushed, iclass 34, count 0 2006.173.09:10:52.50#ibcon#about to write, iclass 34, count 0 2006.173.09:10:52.50#ibcon#wrote, iclass 34, count 0 2006.173.09:10:52.50#ibcon#about to read 3, iclass 34, count 0 2006.173.09:10:52.52#ibcon#read 3, iclass 34, count 0 2006.173.09:10:52.52#ibcon#about to read 4, iclass 34, count 0 2006.173.09:10:52.52#ibcon#read 4, iclass 34, count 0 2006.173.09:10:52.52#ibcon#about to read 5, iclass 34, count 0 2006.173.09:10:52.52#ibcon#read 5, iclass 34, count 0 2006.173.09:10:52.52#ibcon#about to read 6, iclass 34, count 0 2006.173.09:10:52.52#ibcon#read 6, iclass 34, count 0 2006.173.09:10:52.52#ibcon#end of sib2, iclass 34, count 0 2006.173.09:10:52.52#ibcon#*mode == 0, iclass 34, count 0 2006.173.09:10:52.52#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.09:10:52.52#ibcon#[25=USB\r\n] 2006.173.09:10:52.52#ibcon#*before write, iclass 34, count 0 2006.173.09:10:52.52#ibcon#enter sib2, iclass 34, count 0 2006.173.09:10:52.52#ibcon#flushed, iclass 34, count 0 2006.173.09:10:52.52#ibcon#about to write, iclass 34, count 0 2006.173.09:10:52.52#ibcon#wrote, iclass 34, count 0 2006.173.09:10:52.52#ibcon#about to read 3, iclass 34, count 0 2006.173.09:10:52.55#ibcon#read 3, iclass 34, count 0 2006.173.09:10:52.55#ibcon#about to read 4, iclass 34, count 0 2006.173.09:10:52.55#ibcon#read 4, iclass 34, count 0 2006.173.09:10:52.55#ibcon#about to read 5, iclass 34, count 0 2006.173.09:10:52.55#ibcon#read 5, iclass 34, count 0 2006.173.09:10:52.55#ibcon#about to read 6, iclass 34, count 0 2006.173.09:10:52.55#ibcon#read 6, iclass 34, count 0 2006.173.09:10:52.55#ibcon#end of sib2, iclass 34, count 0 2006.173.09:10:52.55#ibcon#*after write, iclass 34, count 0 2006.173.09:10:52.55#ibcon#*before return 0, iclass 34, count 0 2006.173.09:10:52.55#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.09:10:52.55#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.09:10:52.55#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.09:10:52.55#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.09:10:52.55$vck44/valo=5,734.99 2006.173.09:10:52.55#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.09:10:52.55#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.09:10:52.55#ibcon#ireg 17 cls_cnt 0 2006.173.09:10:52.55#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.09:10:52.55#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.09:10:52.55#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.09:10:52.55#ibcon#enter wrdev, iclass 36, count 0 2006.173.09:10:52.55#ibcon#first serial, iclass 36, count 0 2006.173.09:10:52.55#ibcon#enter sib2, iclass 36, count 0 2006.173.09:10:52.55#ibcon#flushed, iclass 36, count 0 2006.173.09:10:52.55#ibcon#about to write, iclass 36, count 0 2006.173.09:10:52.55#ibcon#wrote, iclass 36, count 0 2006.173.09:10:52.55#ibcon#about to read 3, iclass 36, count 0 2006.173.09:10:52.57#ibcon#read 3, iclass 36, count 0 2006.173.09:10:52.57#ibcon#about to read 4, iclass 36, count 0 2006.173.09:10:52.57#ibcon#read 4, iclass 36, count 0 2006.173.09:10:52.57#ibcon#about to read 5, iclass 36, count 0 2006.173.09:10:52.57#ibcon#read 5, iclass 36, count 0 2006.173.09:10:52.57#ibcon#about to read 6, iclass 36, count 0 2006.173.09:10:52.57#ibcon#read 6, iclass 36, count 0 2006.173.09:10:52.57#ibcon#end of sib2, iclass 36, count 0 2006.173.09:10:52.57#ibcon#*mode == 0, iclass 36, count 0 2006.173.09:10:52.57#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.09:10:52.57#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.09:10:52.57#ibcon#*before write, iclass 36, count 0 2006.173.09:10:52.57#ibcon#enter sib2, iclass 36, count 0 2006.173.09:10:52.57#ibcon#flushed, iclass 36, count 0 2006.173.09:10:52.57#ibcon#about to write, iclass 36, count 0 2006.173.09:10:52.57#ibcon#wrote, iclass 36, count 0 2006.173.09:10:52.57#ibcon#about to read 3, iclass 36, count 0 2006.173.09:10:52.61#ibcon#read 3, iclass 36, count 0 2006.173.09:10:52.61#ibcon#about to read 4, iclass 36, count 0 2006.173.09:10:52.61#ibcon#read 4, iclass 36, count 0 2006.173.09:10:52.61#ibcon#about to read 5, iclass 36, count 0 2006.173.09:10:52.61#ibcon#read 5, iclass 36, count 0 2006.173.09:10:52.61#ibcon#about to read 6, iclass 36, count 0 2006.173.09:10:52.61#ibcon#read 6, iclass 36, count 0 2006.173.09:10:52.61#ibcon#end of sib2, iclass 36, count 0 2006.173.09:10:52.61#ibcon#*after write, iclass 36, count 0 2006.173.09:10:52.61#ibcon#*before return 0, iclass 36, count 0 2006.173.09:10:52.61#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.09:10:52.61#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.09:10:52.61#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.09:10:52.61#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.09:10:52.61$vck44/va=5,4 2006.173.09:10:52.61#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.09:10:52.61#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.09:10:52.61#ibcon#ireg 11 cls_cnt 2 2006.173.09:10:52.61#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.09:10:52.67#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.09:10:52.67#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.09:10:52.67#ibcon#enter wrdev, iclass 38, count 2 2006.173.09:10:52.67#ibcon#first serial, iclass 38, count 2 2006.173.09:10:52.67#ibcon#enter sib2, iclass 38, count 2 2006.173.09:10:52.67#ibcon#flushed, iclass 38, count 2 2006.173.09:10:52.67#ibcon#about to write, iclass 38, count 2 2006.173.09:10:52.67#ibcon#wrote, iclass 38, count 2 2006.173.09:10:52.67#ibcon#about to read 3, iclass 38, count 2 2006.173.09:10:52.69#ibcon#read 3, iclass 38, count 2 2006.173.09:10:52.69#ibcon#about to read 4, iclass 38, count 2 2006.173.09:10:52.69#ibcon#read 4, iclass 38, count 2 2006.173.09:10:52.69#ibcon#about to read 5, iclass 38, count 2 2006.173.09:10:52.69#ibcon#read 5, iclass 38, count 2 2006.173.09:10:52.69#ibcon#about to read 6, iclass 38, count 2 2006.173.09:10:52.69#ibcon#read 6, iclass 38, count 2 2006.173.09:10:52.69#ibcon#end of sib2, iclass 38, count 2 2006.173.09:10:52.69#ibcon#*mode == 0, iclass 38, count 2 2006.173.09:10:52.69#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.09:10:52.69#ibcon#[25=AT05-04\r\n] 2006.173.09:10:52.69#ibcon#*before write, iclass 38, count 2 2006.173.09:10:52.69#ibcon#enter sib2, iclass 38, count 2 2006.173.09:10:52.69#ibcon#flushed, iclass 38, count 2 2006.173.09:10:52.69#ibcon#about to write, iclass 38, count 2 2006.173.09:10:52.69#ibcon#wrote, iclass 38, count 2 2006.173.09:10:52.69#ibcon#about to read 3, iclass 38, count 2 2006.173.09:10:52.72#ibcon#read 3, iclass 38, count 2 2006.173.09:10:52.72#ibcon#about to read 4, iclass 38, count 2 2006.173.09:10:52.72#ibcon#read 4, iclass 38, count 2 2006.173.09:10:52.72#ibcon#about to read 5, iclass 38, count 2 2006.173.09:10:52.72#ibcon#read 5, iclass 38, count 2 2006.173.09:10:52.72#ibcon#about to read 6, iclass 38, count 2 2006.173.09:10:52.72#ibcon#read 6, iclass 38, count 2 2006.173.09:10:52.72#ibcon#end of sib2, iclass 38, count 2 2006.173.09:10:52.72#ibcon#*after write, iclass 38, count 2 2006.173.09:10:52.72#ibcon#*before return 0, iclass 38, count 2 2006.173.09:10:52.72#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.09:10:52.72#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.09:10:52.72#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.09:10:52.72#ibcon#ireg 7 cls_cnt 0 2006.173.09:10:52.72#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.09:10:52.84#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.09:10:52.84#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.09:10:52.84#ibcon#enter wrdev, iclass 38, count 0 2006.173.09:10:52.84#ibcon#first serial, iclass 38, count 0 2006.173.09:10:52.84#ibcon#enter sib2, iclass 38, count 0 2006.173.09:10:52.84#ibcon#flushed, iclass 38, count 0 2006.173.09:10:52.84#ibcon#about to write, iclass 38, count 0 2006.173.09:10:52.84#ibcon#wrote, iclass 38, count 0 2006.173.09:10:52.84#ibcon#about to read 3, iclass 38, count 0 2006.173.09:10:52.86#ibcon#read 3, iclass 38, count 0 2006.173.09:10:52.86#ibcon#about to read 4, iclass 38, count 0 2006.173.09:10:52.86#ibcon#read 4, iclass 38, count 0 2006.173.09:10:52.86#ibcon#about to read 5, iclass 38, count 0 2006.173.09:10:52.86#ibcon#read 5, iclass 38, count 0 2006.173.09:10:52.86#ibcon#about to read 6, iclass 38, count 0 2006.173.09:10:52.86#ibcon#read 6, iclass 38, count 0 2006.173.09:10:52.86#ibcon#end of sib2, iclass 38, count 0 2006.173.09:10:52.86#ibcon#*mode == 0, iclass 38, count 0 2006.173.09:10:52.86#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.09:10:52.86#ibcon#[25=USB\r\n] 2006.173.09:10:52.86#ibcon#*before write, iclass 38, count 0 2006.173.09:10:52.86#ibcon#enter sib2, iclass 38, count 0 2006.173.09:10:52.86#ibcon#flushed, iclass 38, count 0 2006.173.09:10:52.86#ibcon#about to write, iclass 38, count 0 2006.173.09:10:52.86#ibcon#wrote, iclass 38, count 0 2006.173.09:10:52.86#ibcon#about to read 3, iclass 38, count 0 2006.173.09:10:52.89#ibcon#read 3, iclass 38, count 0 2006.173.09:10:52.89#ibcon#about to read 4, iclass 38, count 0 2006.173.09:10:52.89#ibcon#read 4, iclass 38, count 0 2006.173.09:10:52.89#ibcon#about to read 5, iclass 38, count 0 2006.173.09:10:52.89#ibcon#read 5, iclass 38, count 0 2006.173.09:10:52.89#ibcon#about to read 6, iclass 38, count 0 2006.173.09:10:52.89#ibcon#read 6, iclass 38, count 0 2006.173.09:10:52.89#ibcon#end of sib2, iclass 38, count 0 2006.173.09:10:52.89#ibcon#*after write, iclass 38, count 0 2006.173.09:10:52.89#ibcon#*before return 0, iclass 38, count 0 2006.173.09:10:52.89#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.09:10:52.89#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.09:10:52.89#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.09:10:52.89#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.09:10:52.89$vck44/valo=6,814.99 2006.173.09:10:52.89#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.09:10:52.89#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.09:10:52.89#ibcon#ireg 17 cls_cnt 0 2006.173.09:10:52.89#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.09:10:52.89#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.09:10:52.89#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.09:10:52.89#ibcon#enter wrdev, iclass 40, count 0 2006.173.09:10:52.89#ibcon#first serial, iclass 40, count 0 2006.173.09:10:52.89#ibcon#enter sib2, iclass 40, count 0 2006.173.09:10:52.89#ibcon#flushed, iclass 40, count 0 2006.173.09:10:52.89#ibcon#about to write, iclass 40, count 0 2006.173.09:10:52.89#ibcon#wrote, iclass 40, count 0 2006.173.09:10:52.89#ibcon#about to read 3, iclass 40, count 0 2006.173.09:10:52.91#ibcon#read 3, iclass 40, count 0 2006.173.09:10:52.91#ibcon#about to read 4, iclass 40, count 0 2006.173.09:10:52.91#ibcon#read 4, iclass 40, count 0 2006.173.09:10:52.91#ibcon#about to read 5, iclass 40, count 0 2006.173.09:10:52.91#ibcon#read 5, iclass 40, count 0 2006.173.09:10:52.91#ibcon#about to read 6, iclass 40, count 0 2006.173.09:10:52.91#ibcon#read 6, iclass 40, count 0 2006.173.09:10:52.91#ibcon#end of sib2, iclass 40, count 0 2006.173.09:10:52.91#ibcon#*mode == 0, iclass 40, count 0 2006.173.09:10:52.91#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.09:10:52.91#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.09:10:52.91#ibcon#*before write, iclass 40, count 0 2006.173.09:10:52.91#ibcon#enter sib2, iclass 40, count 0 2006.173.09:10:52.91#ibcon#flushed, iclass 40, count 0 2006.173.09:10:52.91#ibcon#about to write, iclass 40, count 0 2006.173.09:10:52.91#ibcon#wrote, iclass 40, count 0 2006.173.09:10:52.91#ibcon#about to read 3, iclass 40, count 0 2006.173.09:10:52.95#ibcon#read 3, iclass 40, count 0 2006.173.09:10:52.95#ibcon#about to read 4, iclass 40, count 0 2006.173.09:10:52.95#ibcon#read 4, iclass 40, count 0 2006.173.09:10:52.95#ibcon#about to read 5, iclass 40, count 0 2006.173.09:10:52.95#ibcon#read 5, iclass 40, count 0 2006.173.09:10:52.95#ibcon#about to read 6, iclass 40, count 0 2006.173.09:10:52.95#ibcon#read 6, iclass 40, count 0 2006.173.09:10:52.95#ibcon#end of sib2, iclass 40, count 0 2006.173.09:10:52.95#ibcon#*after write, iclass 40, count 0 2006.173.09:10:52.95#ibcon#*before return 0, iclass 40, count 0 2006.173.09:10:52.95#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.09:10:52.95#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.09:10:52.95#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.09:10:52.95#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.09:10:52.95$vck44/va=6,3 2006.173.09:10:52.95#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.09:10:52.95#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.09:10:52.95#ibcon#ireg 11 cls_cnt 2 2006.173.09:10:52.95#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.09:10:53.01#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.09:10:53.01#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.09:10:53.01#ibcon#enter wrdev, iclass 4, count 2 2006.173.09:10:53.01#ibcon#first serial, iclass 4, count 2 2006.173.09:10:53.01#ibcon#enter sib2, iclass 4, count 2 2006.173.09:10:53.01#ibcon#flushed, iclass 4, count 2 2006.173.09:10:53.01#ibcon#about to write, iclass 4, count 2 2006.173.09:10:53.01#ibcon#wrote, iclass 4, count 2 2006.173.09:10:53.01#ibcon#about to read 3, iclass 4, count 2 2006.173.09:10:53.03#ibcon#read 3, iclass 4, count 2 2006.173.09:10:53.03#ibcon#about to read 4, iclass 4, count 2 2006.173.09:10:53.03#ibcon#read 4, iclass 4, count 2 2006.173.09:10:53.03#ibcon#about to read 5, iclass 4, count 2 2006.173.09:10:53.03#ibcon#read 5, iclass 4, count 2 2006.173.09:10:53.03#ibcon#about to read 6, iclass 4, count 2 2006.173.09:10:53.03#ibcon#read 6, iclass 4, count 2 2006.173.09:10:53.03#ibcon#end of sib2, iclass 4, count 2 2006.173.09:10:53.03#ibcon#*mode == 0, iclass 4, count 2 2006.173.09:10:53.03#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.09:10:53.03#ibcon#[25=AT06-03\r\n] 2006.173.09:10:53.03#ibcon#*before write, iclass 4, count 2 2006.173.09:10:53.03#ibcon#enter sib2, iclass 4, count 2 2006.173.09:10:53.03#ibcon#flushed, iclass 4, count 2 2006.173.09:10:53.03#ibcon#about to write, iclass 4, count 2 2006.173.09:10:53.03#ibcon#wrote, iclass 4, count 2 2006.173.09:10:53.03#ibcon#about to read 3, iclass 4, count 2 2006.173.09:10:53.06#ibcon#read 3, iclass 4, count 2 2006.173.09:10:53.06#ibcon#about to read 4, iclass 4, count 2 2006.173.09:10:53.06#ibcon#read 4, iclass 4, count 2 2006.173.09:10:53.06#ibcon#about to read 5, iclass 4, count 2 2006.173.09:10:53.06#ibcon#read 5, iclass 4, count 2 2006.173.09:10:53.06#ibcon#about to read 6, iclass 4, count 2 2006.173.09:10:53.06#ibcon#read 6, iclass 4, count 2 2006.173.09:10:53.06#ibcon#end of sib2, iclass 4, count 2 2006.173.09:10:53.06#ibcon#*after write, iclass 4, count 2 2006.173.09:10:53.06#ibcon#*before return 0, iclass 4, count 2 2006.173.09:10:53.06#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.09:10:53.06#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.09:10:53.06#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.09:10:53.06#ibcon#ireg 7 cls_cnt 0 2006.173.09:10:53.06#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.09:10:53.18#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.09:10:53.18#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.09:10:53.18#ibcon#enter wrdev, iclass 4, count 0 2006.173.09:10:53.18#ibcon#first serial, iclass 4, count 0 2006.173.09:10:53.18#ibcon#enter sib2, iclass 4, count 0 2006.173.09:10:53.18#ibcon#flushed, iclass 4, count 0 2006.173.09:10:53.18#ibcon#about to write, iclass 4, count 0 2006.173.09:10:53.18#ibcon#wrote, iclass 4, count 0 2006.173.09:10:53.18#ibcon#about to read 3, iclass 4, count 0 2006.173.09:10:53.20#ibcon#read 3, iclass 4, count 0 2006.173.09:10:53.20#ibcon#about to read 4, iclass 4, count 0 2006.173.09:10:53.20#ibcon#read 4, iclass 4, count 0 2006.173.09:10:53.20#ibcon#about to read 5, iclass 4, count 0 2006.173.09:10:53.20#ibcon#read 5, iclass 4, count 0 2006.173.09:10:53.20#ibcon#about to read 6, iclass 4, count 0 2006.173.09:10:53.20#ibcon#read 6, iclass 4, count 0 2006.173.09:10:53.20#ibcon#end of sib2, iclass 4, count 0 2006.173.09:10:53.20#ibcon#*mode == 0, iclass 4, count 0 2006.173.09:10:53.20#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.09:10:53.20#ibcon#[25=USB\r\n] 2006.173.09:10:53.20#ibcon#*before write, iclass 4, count 0 2006.173.09:10:53.20#ibcon#enter sib2, iclass 4, count 0 2006.173.09:10:53.20#ibcon#flushed, iclass 4, count 0 2006.173.09:10:53.20#ibcon#about to write, iclass 4, count 0 2006.173.09:10:53.20#ibcon#wrote, iclass 4, count 0 2006.173.09:10:53.20#ibcon#about to read 3, iclass 4, count 0 2006.173.09:10:53.23#ibcon#read 3, iclass 4, count 0 2006.173.09:10:53.23#ibcon#about to read 4, iclass 4, count 0 2006.173.09:10:53.23#ibcon#read 4, iclass 4, count 0 2006.173.09:10:53.23#ibcon#about to read 5, iclass 4, count 0 2006.173.09:10:53.23#ibcon#read 5, iclass 4, count 0 2006.173.09:10:53.23#ibcon#about to read 6, iclass 4, count 0 2006.173.09:10:53.23#ibcon#read 6, iclass 4, count 0 2006.173.09:10:53.23#ibcon#end of sib2, iclass 4, count 0 2006.173.09:10:53.23#ibcon#*after write, iclass 4, count 0 2006.173.09:10:53.23#ibcon#*before return 0, iclass 4, count 0 2006.173.09:10:53.23#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.09:10:53.23#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.09:10:53.23#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.09:10:53.23#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.09:10:53.23$vck44/valo=7,864.99 2006.173.09:10:53.23#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.09:10:53.23#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.09:10:53.23#ibcon#ireg 17 cls_cnt 0 2006.173.09:10:53.23#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.09:10:53.23#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.09:10:53.23#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.09:10:53.23#ibcon#enter wrdev, iclass 6, count 0 2006.173.09:10:53.23#ibcon#first serial, iclass 6, count 0 2006.173.09:10:53.23#ibcon#enter sib2, iclass 6, count 0 2006.173.09:10:53.23#ibcon#flushed, iclass 6, count 0 2006.173.09:10:53.23#ibcon#about to write, iclass 6, count 0 2006.173.09:10:53.23#ibcon#wrote, iclass 6, count 0 2006.173.09:10:53.23#ibcon#about to read 3, iclass 6, count 0 2006.173.09:10:53.25#ibcon#read 3, iclass 6, count 0 2006.173.09:10:53.25#ibcon#about to read 4, iclass 6, count 0 2006.173.09:10:53.25#ibcon#read 4, iclass 6, count 0 2006.173.09:10:53.25#ibcon#about to read 5, iclass 6, count 0 2006.173.09:10:53.25#ibcon#read 5, iclass 6, count 0 2006.173.09:10:53.25#ibcon#about to read 6, iclass 6, count 0 2006.173.09:10:53.25#ibcon#read 6, iclass 6, count 0 2006.173.09:10:53.25#ibcon#end of sib2, iclass 6, count 0 2006.173.09:10:53.25#ibcon#*mode == 0, iclass 6, count 0 2006.173.09:10:53.25#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.09:10:53.25#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.09:10:53.25#ibcon#*before write, iclass 6, count 0 2006.173.09:10:53.25#ibcon#enter sib2, iclass 6, count 0 2006.173.09:10:53.25#ibcon#flushed, iclass 6, count 0 2006.173.09:10:53.25#ibcon#about to write, iclass 6, count 0 2006.173.09:10:53.25#ibcon#wrote, iclass 6, count 0 2006.173.09:10:53.25#ibcon#about to read 3, iclass 6, count 0 2006.173.09:10:53.29#ibcon#read 3, iclass 6, count 0 2006.173.09:10:53.29#ibcon#about to read 4, iclass 6, count 0 2006.173.09:10:53.29#ibcon#read 4, iclass 6, count 0 2006.173.09:10:53.29#ibcon#about to read 5, iclass 6, count 0 2006.173.09:10:53.29#ibcon#read 5, iclass 6, count 0 2006.173.09:10:53.29#ibcon#about to read 6, iclass 6, count 0 2006.173.09:10:53.29#ibcon#read 6, iclass 6, count 0 2006.173.09:10:53.29#ibcon#end of sib2, iclass 6, count 0 2006.173.09:10:53.29#ibcon#*after write, iclass 6, count 0 2006.173.09:10:53.29#ibcon#*before return 0, iclass 6, count 0 2006.173.09:10:53.29#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.09:10:53.29#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.09:10:53.29#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.09:10:53.29#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.09:10:53.29$vck44/va=7,4 2006.173.09:10:53.29#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.09:10:53.29#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.09:10:53.29#ibcon#ireg 11 cls_cnt 2 2006.173.09:10:53.29#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.09:10:53.35#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.09:10:53.35#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.09:10:53.35#ibcon#enter wrdev, iclass 10, count 2 2006.173.09:10:53.35#ibcon#first serial, iclass 10, count 2 2006.173.09:10:53.35#ibcon#enter sib2, iclass 10, count 2 2006.173.09:10:53.35#ibcon#flushed, iclass 10, count 2 2006.173.09:10:53.35#ibcon#about to write, iclass 10, count 2 2006.173.09:10:53.35#ibcon#wrote, iclass 10, count 2 2006.173.09:10:53.35#ibcon#about to read 3, iclass 10, count 2 2006.173.09:10:53.37#ibcon#read 3, iclass 10, count 2 2006.173.09:10:53.37#ibcon#about to read 4, iclass 10, count 2 2006.173.09:10:53.37#ibcon#read 4, iclass 10, count 2 2006.173.09:10:53.37#ibcon#about to read 5, iclass 10, count 2 2006.173.09:10:53.37#ibcon#read 5, iclass 10, count 2 2006.173.09:10:53.37#ibcon#about to read 6, iclass 10, count 2 2006.173.09:10:53.37#ibcon#read 6, iclass 10, count 2 2006.173.09:10:53.37#ibcon#end of sib2, iclass 10, count 2 2006.173.09:10:53.37#ibcon#*mode == 0, iclass 10, count 2 2006.173.09:10:53.37#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.09:10:53.37#ibcon#[25=AT07-04\r\n] 2006.173.09:10:53.37#ibcon#*before write, iclass 10, count 2 2006.173.09:10:53.37#ibcon#enter sib2, iclass 10, count 2 2006.173.09:10:53.37#ibcon#flushed, iclass 10, count 2 2006.173.09:10:53.37#ibcon#about to write, iclass 10, count 2 2006.173.09:10:53.37#ibcon#wrote, iclass 10, count 2 2006.173.09:10:53.37#ibcon#about to read 3, iclass 10, count 2 2006.173.09:10:53.40#ibcon#read 3, iclass 10, count 2 2006.173.09:10:53.40#ibcon#about to read 4, iclass 10, count 2 2006.173.09:10:53.40#ibcon#read 4, iclass 10, count 2 2006.173.09:10:53.40#ibcon#about to read 5, iclass 10, count 2 2006.173.09:10:53.40#ibcon#read 5, iclass 10, count 2 2006.173.09:10:53.40#ibcon#about to read 6, iclass 10, count 2 2006.173.09:10:53.40#ibcon#read 6, iclass 10, count 2 2006.173.09:10:53.40#ibcon#end of sib2, iclass 10, count 2 2006.173.09:10:53.40#ibcon#*after write, iclass 10, count 2 2006.173.09:10:53.40#ibcon#*before return 0, iclass 10, count 2 2006.173.09:10:53.40#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.09:10:53.40#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.09:10:53.40#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.09:10:53.40#ibcon#ireg 7 cls_cnt 0 2006.173.09:10:53.40#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.09:10:53.52#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.09:10:53.52#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.09:10:53.52#ibcon#enter wrdev, iclass 10, count 0 2006.173.09:10:53.52#ibcon#first serial, iclass 10, count 0 2006.173.09:10:53.52#ibcon#enter sib2, iclass 10, count 0 2006.173.09:10:53.52#ibcon#flushed, iclass 10, count 0 2006.173.09:10:53.52#ibcon#about to write, iclass 10, count 0 2006.173.09:10:53.52#ibcon#wrote, iclass 10, count 0 2006.173.09:10:53.52#ibcon#about to read 3, iclass 10, count 0 2006.173.09:10:53.54#ibcon#read 3, iclass 10, count 0 2006.173.09:10:53.54#ibcon#about to read 4, iclass 10, count 0 2006.173.09:10:53.54#ibcon#read 4, iclass 10, count 0 2006.173.09:10:53.54#ibcon#about to read 5, iclass 10, count 0 2006.173.09:10:53.54#ibcon#read 5, iclass 10, count 0 2006.173.09:10:53.54#ibcon#about to read 6, iclass 10, count 0 2006.173.09:10:53.54#ibcon#read 6, iclass 10, count 0 2006.173.09:10:53.54#ibcon#end of sib2, iclass 10, count 0 2006.173.09:10:53.54#ibcon#*mode == 0, iclass 10, count 0 2006.173.09:10:53.54#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.09:10:53.54#ibcon#[25=USB\r\n] 2006.173.09:10:53.54#ibcon#*before write, iclass 10, count 0 2006.173.09:10:53.54#ibcon#enter sib2, iclass 10, count 0 2006.173.09:10:53.54#ibcon#flushed, iclass 10, count 0 2006.173.09:10:53.54#ibcon#about to write, iclass 10, count 0 2006.173.09:10:53.54#ibcon#wrote, iclass 10, count 0 2006.173.09:10:53.54#ibcon#about to read 3, iclass 10, count 0 2006.173.09:10:53.57#ibcon#read 3, iclass 10, count 0 2006.173.09:10:53.57#ibcon#about to read 4, iclass 10, count 0 2006.173.09:10:53.57#ibcon#read 4, iclass 10, count 0 2006.173.09:10:53.57#ibcon#about to read 5, iclass 10, count 0 2006.173.09:10:53.57#ibcon#read 5, iclass 10, count 0 2006.173.09:10:53.57#ibcon#about to read 6, iclass 10, count 0 2006.173.09:10:53.57#ibcon#read 6, iclass 10, count 0 2006.173.09:10:53.57#ibcon#end of sib2, iclass 10, count 0 2006.173.09:10:53.57#ibcon#*after write, iclass 10, count 0 2006.173.09:10:53.57#ibcon#*before return 0, iclass 10, count 0 2006.173.09:10:53.57#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.09:10:53.57#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.09:10:53.57#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.09:10:53.57#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.09:10:53.57$vck44/valo=8,884.99 2006.173.09:10:53.57#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.09:10:53.57#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.09:10:53.57#ibcon#ireg 17 cls_cnt 0 2006.173.09:10:53.57#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.09:10:53.57#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.09:10:53.57#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.09:10:53.57#ibcon#enter wrdev, iclass 12, count 0 2006.173.09:10:53.57#ibcon#first serial, iclass 12, count 0 2006.173.09:10:53.57#ibcon#enter sib2, iclass 12, count 0 2006.173.09:10:53.57#ibcon#flushed, iclass 12, count 0 2006.173.09:10:53.57#ibcon#about to write, iclass 12, count 0 2006.173.09:10:53.57#ibcon#wrote, iclass 12, count 0 2006.173.09:10:53.57#ibcon#about to read 3, iclass 12, count 0 2006.173.09:10:53.59#ibcon#read 3, iclass 12, count 0 2006.173.09:10:53.59#ibcon#about to read 4, iclass 12, count 0 2006.173.09:10:53.59#ibcon#read 4, iclass 12, count 0 2006.173.09:10:53.59#ibcon#about to read 5, iclass 12, count 0 2006.173.09:10:53.59#ibcon#read 5, iclass 12, count 0 2006.173.09:10:53.59#ibcon#about to read 6, iclass 12, count 0 2006.173.09:10:53.59#ibcon#read 6, iclass 12, count 0 2006.173.09:10:53.59#ibcon#end of sib2, iclass 12, count 0 2006.173.09:10:53.59#ibcon#*mode == 0, iclass 12, count 0 2006.173.09:10:53.59#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.09:10:53.59#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.09:10:53.59#ibcon#*before write, iclass 12, count 0 2006.173.09:10:53.59#ibcon#enter sib2, iclass 12, count 0 2006.173.09:10:53.59#ibcon#flushed, iclass 12, count 0 2006.173.09:10:53.59#ibcon#about to write, iclass 12, count 0 2006.173.09:10:53.59#ibcon#wrote, iclass 12, count 0 2006.173.09:10:53.59#ibcon#about to read 3, iclass 12, count 0 2006.173.09:10:53.63#ibcon#read 3, iclass 12, count 0 2006.173.09:10:53.63#ibcon#about to read 4, iclass 12, count 0 2006.173.09:10:53.63#ibcon#read 4, iclass 12, count 0 2006.173.09:10:53.63#ibcon#about to read 5, iclass 12, count 0 2006.173.09:10:53.63#ibcon#read 5, iclass 12, count 0 2006.173.09:10:53.63#ibcon#about to read 6, iclass 12, count 0 2006.173.09:10:53.63#ibcon#read 6, iclass 12, count 0 2006.173.09:10:53.63#ibcon#end of sib2, iclass 12, count 0 2006.173.09:10:53.63#ibcon#*after write, iclass 12, count 0 2006.173.09:10:53.63#ibcon#*before return 0, iclass 12, count 0 2006.173.09:10:53.63#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.09:10:53.63#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.09:10:53.63#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.09:10:53.63#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.09:10:53.63$vck44/va=8,4 2006.173.09:10:53.63#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.09:10:53.63#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.09:10:53.63#ibcon#ireg 11 cls_cnt 2 2006.173.09:10:53.63#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.09:10:53.69#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.09:10:53.69#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.09:10:53.69#ibcon#enter wrdev, iclass 14, count 2 2006.173.09:10:53.69#ibcon#first serial, iclass 14, count 2 2006.173.09:10:53.69#ibcon#enter sib2, iclass 14, count 2 2006.173.09:10:53.69#ibcon#flushed, iclass 14, count 2 2006.173.09:10:53.69#ibcon#about to write, iclass 14, count 2 2006.173.09:10:53.69#ibcon#wrote, iclass 14, count 2 2006.173.09:10:53.69#ibcon#about to read 3, iclass 14, count 2 2006.173.09:10:53.71#ibcon#read 3, iclass 14, count 2 2006.173.09:10:53.71#ibcon#about to read 4, iclass 14, count 2 2006.173.09:10:53.71#ibcon#read 4, iclass 14, count 2 2006.173.09:10:53.71#ibcon#about to read 5, iclass 14, count 2 2006.173.09:10:53.71#ibcon#read 5, iclass 14, count 2 2006.173.09:10:53.71#ibcon#about to read 6, iclass 14, count 2 2006.173.09:10:53.71#ibcon#read 6, iclass 14, count 2 2006.173.09:10:53.71#ibcon#end of sib2, iclass 14, count 2 2006.173.09:10:53.71#ibcon#*mode == 0, iclass 14, count 2 2006.173.09:10:53.71#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.09:10:53.71#ibcon#[25=AT08-04\r\n] 2006.173.09:10:53.71#ibcon#*before write, iclass 14, count 2 2006.173.09:10:53.71#ibcon#enter sib2, iclass 14, count 2 2006.173.09:10:53.71#ibcon#flushed, iclass 14, count 2 2006.173.09:10:53.71#ibcon#about to write, iclass 14, count 2 2006.173.09:10:53.71#ibcon#wrote, iclass 14, count 2 2006.173.09:10:53.71#ibcon#about to read 3, iclass 14, count 2 2006.173.09:10:53.74#ibcon#read 3, iclass 14, count 2 2006.173.09:10:53.74#ibcon#about to read 4, iclass 14, count 2 2006.173.09:10:53.74#ibcon#read 4, iclass 14, count 2 2006.173.09:10:53.74#ibcon#about to read 5, iclass 14, count 2 2006.173.09:10:53.74#ibcon#read 5, iclass 14, count 2 2006.173.09:10:53.74#ibcon#about to read 6, iclass 14, count 2 2006.173.09:10:53.74#ibcon#read 6, iclass 14, count 2 2006.173.09:10:53.74#ibcon#end of sib2, iclass 14, count 2 2006.173.09:10:53.74#ibcon#*after write, iclass 14, count 2 2006.173.09:10:53.74#ibcon#*before return 0, iclass 14, count 2 2006.173.09:10:53.74#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.09:10:53.74#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.09:10:53.74#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.09:10:53.74#ibcon#ireg 7 cls_cnt 0 2006.173.09:10:53.74#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.09:10:53.86#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.09:10:53.86#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.09:10:53.86#ibcon#enter wrdev, iclass 14, count 0 2006.173.09:10:53.86#ibcon#first serial, iclass 14, count 0 2006.173.09:10:53.86#ibcon#enter sib2, iclass 14, count 0 2006.173.09:10:53.86#ibcon#flushed, iclass 14, count 0 2006.173.09:10:53.86#ibcon#about to write, iclass 14, count 0 2006.173.09:10:53.86#ibcon#wrote, iclass 14, count 0 2006.173.09:10:53.86#ibcon#about to read 3, iclass 14, count 0 2006.173.09:10:53.88#ibcon#read 3, iclass 14, count 0 2006.173.09:10:53.88#ibcon#about to read 4, iclass 14, count 0 2006.173.09:10:53.88#ibcon#read 4, iclass 14, count 0 2006.173.09:10:53.88#ibcon#about to read 5, iclass 14, count 0 2006.173.09:10:53.88#ibcon#read 5, iclass 14, count 0 2006.173.09:10:53.88#ibcon#about to read 6, iclass 14, count 0 2006.173.09:10:53.88#ibcon#read 6, iclass 14, count 0 2006.173.09:10:53.88#ibcon#end of sib2, iclass 14, count 0 2006.173.09:10:53.88#ibcon#*mode == 0, iclass 14, count 0 2006.173.09:10:53.88#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.09:10:53.88#ibcon#[25=USB\r\n] 2006.173.09:10:53.88#ibcon#*before write, iclass 14, count 0 2006.173.09:10:53.88#ibcon#enter sib2, iclass 14, count 0 2006.173.09:10:53.88#ibcon#flushed, iclass 14, count 0 2006.173.09:10:53.88#ibcon#about to write, iclass 14, count 0 2006.173.09:10:53.88#ibcon#wrote, iclass 14, count 0 2006.173.09:10:53.88#ibcon#about to read 3, iclass 14, count 0 2006.173.09:10:53.91#ibcon#read 3, iclass 14, count 0 2006.173.09:10:53.91#ibcon#about to read 4, iclass 14, count 0 2006.173.09:10:53.91#ibcon#read 4, iclass 14, count 0 2006.173.09:10:53.91#ibcon#about to read 5, iclass 14, count 0 2006.173.09:10:53.91#ibcon#read 5, iclass 14, count 0 2006.173.09:10:53.91#ibcon#about to read 6, iclass 14, count 0 2006.173.09:10:53.91#ibcon#read 6, iclass 14, count 0 2006.173.09:10:53.91#ibcon#end of sib2, iclass 14, count 0 2006.173.09:10:53.91#ibcon#*after write, iclass 14, count 0 2006.173.09:10:53.91#ibcon#*before return 0, iclass 14, count 0 2006.173.09:10:53.91#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.09:10:53.91#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.09:10:53.91#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.09:10:53.91#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.09:10:53.91$vck44/vblo=1,629.99 2006.173.09:10:53.91#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.09:10:53.91#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.09:10:53.91#ibcon#ireg 17 cls_cnt 0 2006.173.09:10:53.91#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.09:10:53.91#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.09:10:53.91#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.09:10:53.91#ibcon#enter wrdev, iclass 16, count 0 2006.173.09:10:53.91#ibcon#first serial, iclass 16, count 0 2006.173.09:10:53.91#ibcon#enter sib2, iclass 16, count 0 2006.173.09:10:53.91#ibcon#flushed, iclass 16, count 0 2006.173.09:10:53.91#ibcon#about to write, iclass 16, count 0 2006.173.09:10:53.91#ibcon#wrote, iclass 16, count 0 2006.173.09:10:53.91#ibcon#about to read 3, iclass 16, count 0 2006.173.09:10:53.93#ibcon#read 3, iclass 16, count 0 2006.173.09:10:53.93#ibcon#about to read 4, iclass 16, count 0 2006.173.09:10:53.93#ibcon#read 4, iclass 16, count 0 2006.173.09:10:53.93#ibcon#about to read 5, iclass 16, count 0 2006.173.09:10:53.93#ibcon#read 5, iclass 16, count 0 2006.173.09:10:53.93#ibcon#about to read 6, iclass 16, count 0 2006.173.09:10:53.93#ibcon#read 6, iclass 16, count 0 2006.173.09:10:53.93#ibcon#end of sib2, iclass 16, count 0 2006.173.09:10:53.93#ibcon#*mode == 0, iclass 16, count 0 2006.173.09:10:53.93#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.09:10:53.93#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.09:10:53.93#ibcon#*before write, iclass 16, count 0 2006.173.09:10:53.93#ibcon#enter sib2, iclass 16, count 0 2006.173.09:10:53.93#ibcon#flushed, iclass 16, count 0 2006.173.09:10:53.93#ibcon#about to write, iclass 16, count 0 2006.173.09:10:53.93#ibcon#wrote, iclass 16, count 0 2006.173.09:10:53.93#ibcon#about to read 3, iclass 16, count 0 2006.173.09:10:53.97#ibcon#read 3, iclass 16, count 0 2006.173.09:10:53.97#ibcon#about to read 4, iclass 16, count 0 2006.173.09:10:53.97#ibcon#read 4, iclass 16, count 0 2006.173.09:10:53.97#ibcon#about to read 5, iclass 16, count 0 2006.173.09:10:53.97#ibcon#read 5, iclass 16, count 0 2006.173.09:10:53.97#ibcon#about to read 6, iclass 16, count 0 2006.173.09:10:53.97#ibcon#read 6, iclass 16, count 0 2006.173.09:10:53.97#ibcon#end of sib2, iclass 16, count 0 2006.173.09:10:53.97#ibcon#*after write, iclass 16, count 0 2006.173.09:10:53.97#ibcon#*before return 0, iclass 16, count 0 2006.173.09:10:53.97#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.09:10:53.97#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.09:10:53.97#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.09:10:53.97#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.09:10:53.97$vck44/vb=1,4 2006.173.09:10:53.97#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.09:10:53.97#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.09:10:53.97#ibcon#ireg 11 cls_cnt 2 2006.173.09:10:53.97#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.09:10:53.97#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.09:10:53.97#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.09:10:53.97#ibcon#enter wrdev, iclass 18, count 2 2006.173.09:10:53.97#ibcon#first serial, iclass 18, count 2 2006.173.09:10:53.97#ibcon#enter sib2, iclass 18, count 2 2006.173.09:10:53.97#ibcon#flushed, iclass 18, count 2 2006.173.09:10:53.97#ibcon#about to write, iclass 18, count 2 2006.173.09:10:53.97#ibcon#wrote, iclass 18, count 2 2006.173.09:10:53.97#ibcon#about to read 3, iclass 18, count 2 2006.173.09:10:53.99#ibcon#read 3, iclass 18, count 2 2006.173.09:10:53.99#ibcon#about to read 4, iclass 18, count 2 2006.173.09:10:53.99#ibcon#read 4, iclass 18, count 2 2006.173.09:10:53.99#ibcon#about to read 5, iclass 18, count 2 2006.173.09:10:53.99#ibcon#read 5, iclass 18, count 2 2006.173.09:10:53.99#ibcon#about to read 6, iclass 18, count 2 2006.173.09:10:53.99#ibcon#read 6, iclass 18, count 2 2006.173.09:10:53.99#ibcon#end of sib2, iclass 18, count 2 2006.173.09:10:53.99#ibcon#*mode == 0, iclass 18, count 2 2006.173.09:10:53.99#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.09:10:53.99#ibcon#[27=AT01-04\r\n] 2006.173.09:10:53.99#ibcon#*before write, iclass 18, count 2 2006.173.09:10:53.99#ibcon#enter sib2, iclass 18, count 2 2006.173.09:10:53.99#ibcon#flushed, iclass 18, count 2 2006.173.09:10:53.99#ibcon#about to write, iclass 18, count 2 2006.173.09:10:53.99#ibcon#wrote, iclass 18, count 2 2006.173.09:10:53.99#ibcon#about to read 3, iclass 18, count 2 2006.173.09:10:54.02#ibcon#read 3, iclass 18, count 2 2006.173.09:10:54.02#ibcon#about to read 4, iclass 18, count 2 2006.173.09:10:54.02#ibcon#read 4, iclass 18, count 2 2006.173.09:10:54.02#ibcon#about to read 5, iclass 18, count 2 2006.173.09:10:54.02#ibcon#read 5, iclass 18, count 2 2006.173.09:10:54.02#ibcon#about to read 6, iclass 18, count 2 2006.173.09:10:54.02#ibcon#read 6, iclass 18, count 2 2006.173.09:10:54.02#ibcon#end of sib2, iclass 18, count 2 2006.173.09:10:54.02#ibcon#*after write, iclass 18, count 2 2006.173.09:10:54.02#ibcon#*before return 0, iclass 18, count 2 2006.173.09:10:54.02#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.09:10:54.02#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.09:10:54.02#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.09:10:54.02#ibcon#ireg 7 cls_cnt 0 2006.173.09:10:54.02#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.09:10:54.14#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.09:10:54.14#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.09:10:54.14#ibcon#enter wrdev, iclass 18, count 0 2006.173.09:10:54.14#ibcon#first serial, iclass 18, count 0 2006.173.09:10:54.14#ibcon#enter sib2, iclass 18, count 0 2006.173.09:10:54.14#ibcon#flushed, iclass 18, count 0 2006.173.09:10:54.14#ibcon#about to write, iclass 18, count 0 2006.173.09:10:54.14#ibcon#wrote, iclass 18, count 0 2006.173.09:10:54.14#ibcon#about to read 3, iclass 18, count 0 2006.173.09:10:54.16#ibcon#read 3, iclass 18, count 0 2006.173.09:10:54.16#ibcon#about to read 4, iclass 18, count 0 2006.173.09:10:54.16#ibcon#read 4, iclass 18, count 0 2006.173.09:10:54.16#ibcon#about to read 5, iclass 18, count 0 2006.173.09:10:54.16#ibcon#read 5, iclass 18, count 0 2006.173.09:10:54.16#ibcon#about to read 6, iclass 18, count 0 2006.173.09:10:54.16#ibcon#read 6, iclass 18, count 0 2006.173.09:10:54.16#ibcon#end of sib2, iclass 18, count 0 2006.173.09:10:54.16#ibcon#*mode == 0, iclass 18, count 0 2006.173.09:10:54.16#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.09:10:54.16#ibcon#[27=USB\r\n] 2006.173.09:10:54.16#ibcon#*before write, iclass 18, count 0 2006.173.09:10:54.16#ibcon#enter sib2, iclass 18, count 0 2006.173.09:10:54.16#ibcon#flushed, iclass 18, count 0 2006.173.09:10:54.16#ibcon#about to write, iclass 18, count 0 2006.173.09:10:54.16#ibcon#wrote, iclass 18, count 0 2006.173.09:10:54.16#ibcon#about to read 3, iclass 18, count 0 2006.173.09:10:54.19#ibcon#read 3, iclass 18, count 0 2006.173.09:10:54.19#ibcon#about to read 4, iclass 18, count 0 2006.173.09:10:54.19#ibcon#read 4, iclass 18, count 0 2006.173.09:10:54.19#ibcon#about to read 5, iclass 18, count 0 2006.173.09:10:54.19#ibcon#read 5, iclass 18, count 0 2006.173.09:10:54.19#ibcon#about to read 6, iclass 18, count 0 2006.173.09:10:54.19#ibcon#read 6, iclass 18, count 0 2006.173.09:10:54.19#ibcon#end of sib2, iclass 18, count 0 2006.173.09:10:54.19#ibcon#*after write, iclass 18, count 0 2006.173.09:10:54.19#ibcon#*before return 0, iclass 18, count 0 2006.173.09:10:54.19#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.09:10:54.19#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.09:10:54.19#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.09:10:54.19#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.09:10:54.19$vck44/vblo=2,634.99 2006.173.09:10:54.19#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.09:10:54.19#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.09:10:54.19#ibcon#ireg 17 cls_cnt 0 2006.173.09:10:54.19#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.09:10:54.19#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.09:10:54.19#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.09:10:54.19#ibcon#enter wrdev, iclass 20, count 0 2006.173.09:10:54.19#ibcon#first serial, iclass 20, count 0 2006.173.09:10:54.19#ibcon#enter sib2, iclass 20, count 0 2006.173.09:10:54.19#ibcon#flushed, iclass 20, count 0 2006.173.09:10:54.19#ibcon#about to write, iclass 20, count 0 2006.173.09:10:54.19#ibcon#wrote, iclass 20, count 0 2006.173.09:10:54.19#ibcon#about to read 3, iclass 20, count 0 2006.173.09:10:54.21#ibcon#read 3, iclass 20, count 0 2006.173.09:10:54.21#ibcon#about to read 4, iclass 20, count 0 2006.173.09:10:54.21#ibcon#read 4, iclass 20, count 0 2006.173.09:10:54.21#ibcon#about to read 5, iclass 20, count 0 2006.173.09:10:54.21#ibcon#read 5, iclass 20, count 0 2006.173.09:10:54.21#ibcon#about to read 6, iclass 20, count 0 2006.173.09:10:54.21#ibcon#read 6, iclass 20, count 0 2006.173.09:10:54.21#ibcon#end of sib2, iclass 20, count 0 2006.173.09:10:54.21#ibcon#*mode == 0, iclass 20, count 0 2006.173.09:10:54.21#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.09:10:54.21#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.09:10:54.21#ibcon#*before write, iclass 20, count 0 2006.173.09:10:54.21#ibcon#enter sib2, iclass 20, count 0 2006.173.09:10:54.21#ibcon#flushed, iclass 20, count 0 2006.173.09:10:54.21#ibcon#about to write, iclass 20, count 0 2006.173.09:10:54.21#ibcon#wrote, iclass 20, count 0 2006.173.09:10:54.21#ibcon#about to read 3, iclass 20, count 0 2006.173.09:10:54.25#ibcon#read 3, iclass 20, count 0 2006.173.09:10:54.25#ibcon#about to read 4, iclass 20, count 0 2006.173.09:10:54.25#ibcon#read 4, iclass 20, count 0 2006.173.09:10:54.25#ibcon#about to read 5, iclass 20, count 0 2006.173.09:10:54.25#ibcon#read 5, iclass 20, count 0 2006.173.09:10:54.25#ibcon#about to read 6, iclass 20, count 0 2006.173.09:10:54.25#ibcon#read 6, iclass 20, count 0 2006.173.09:10:54.25#ibcon#end of sib2, iclass 20, count 0 2006.173.09:10:54.25#ibcon#*after write, iclass 20, count 0 2006.173.09:10:54.25#ibcon#*before return 0, iclass 20, count 0 2006.173.09:10:54.25#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.09:10:54.25#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.09:10:54.25#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.09:10:54.25#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.09:10:54.25$vck44/vb=2,4 2006.173.09:10:54.25#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.09:10:54.25#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.09:10:54.25#ibcon#ireg 11 cls_cnt 2 2006.173.09:10:54.25#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.09:10:54.31#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.09:10:54.31#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.09:10:54.31#ibcon#enter wrdev, iclass 22, count 2 2006.173.09:10:54.31#ibcon#first serial, iclass 22, count 2 2006.173.09:10:54.31#ibcon#enter sib2, iclass 22, count 2 2006.173.09:10:54.31#ibcon#flushed, iclass 22, count 2 2006.173.09:10:54.31#ibcon#about to write, iclass 22, count 2 2006.173.09:10:54.31#ibcon#wrote, iclass 22, count 2 2006.173.09:10:54.31#ibcon#about to read 3, iclass 22, count 2 2006.173.09:10:54.33#ibcon#read 3, iclass 22, count 2 2006.173.09:10:54.33#ibcon#about to read 4, iclass 22, count 2 2006.173.09:10:54.33#ibcon#read 4, iclass 22, count 2 2006.173.09:10:54.33#ibcon#about to read 5, iclass 22, count 2 2006.173.09:10:54.33#ibcon#read 5, iclass 22, count 2 2006.173.09:10:54.33#ibcon#about to read 6, iclass 22, count 2 2006.173.09:10:54.33#ibcon#read 6, iclass 22, count 2 2006.173.09:10:54.33#ibcon#end of sib2, iclass 22, count 2 2006.173.09:10:54.33#ibcon#*mode == 0, iclass 22, count 2 2006.173.09:10:54.33#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.09:10:54.33#ibcon#[27=AT02-04\r\n] 2006.173.09:10:54.33#ibcon#*before write, iclass 22, count 2 2006.173.09:10:54.33#ibcon#enter sib2, iclass 22, count 2 2006.173.09:10:54.33#ibcon#flushed, iclass 22, count 2 2006.173.09:10:54.33#ibcon#about to write, iclass 22, count 2 2006.173.09:10:54.33#ibcon#wrote, iclass 22, count 2 2006.173.09:10:54.33#ibcon#about to read 3, iclass 22, count 2 2006.173.09:10:54.36#ibcon#read 3, iclass 22, count 2 2006.173.09:10:54.36#ibcon#about to read 4, iclass 22, count 2 2006.173.09:10:54.36#ibcon#read 4, iclass 22, count 2 2006.173.09:10:54.36#ibcon#about to read 5, iclass 22, count 2 2006.173.09:10:54.36#ibcon#read 5, iclass 22, count 2 2006.173.09:10:54.36#ibcon#about to read 6, iclass 22, count 2 2006.173.09:10:54.36#ibcon#read 6, iclass 22, count 2 2006.173.09:10:54.36#ibcon#end of sib2, iclass 22, count 2 2006.173.09:10:54.36#ibcon#*after write, iclass 22, count 2 2006.173.09:10:54.36#ibcon#*before return 0, iclass 22, count 2 2006.173.09:10:54.36#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.09:10:54.36#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.09:10:54.36#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.09:10:54.36#ibcon#ireg 7 cls_cnt 0 2006.173.09:10:54.36#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.09:10:54.48#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.09:10:54.48#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.09:10:54.48#ibcon#enter wrdev, iclass 22, count 0 2006.173.09:10:54.48#ibcon#first serial, iclass 22, count 0 2006.173.09:10:54.48#ibcon#enter sib2, iclass 22, count 0 2006.173.09:10:54.48#ibcon#flushed, iclass 22, count 0 2006.173.09:10:54.48#ibcon#about to write, iclass 22, count 0 2006.173.09:10:54.48#ibcon#wrote, iclass 22, count 0 2006.173.09:10:54.48#ibcon#about to read 3, iclass 22, count 0 2006.173.09:10:54.50#ibcon#read 3, iclass 22, count 0 2006.173.09:10:54.50#ibcon#about to read 4, iclass 22, count 0 2006.173.09:10:54.50#ibcon#read 4, iclass 22, count 0 2006.173.09:10:54.50#ibcon#about to read 5, iclass 22, count 0 2006.173.09:10:54.50#ibcon#read 5, iclass 22, count 0 2006.173.09:10:54.50#ibcon#about to read 6, iclass 22, count 0 2006.173.09:10:54.50#ibcon#read 6, iclass 22, count 0 2006.173.09:10:54.50#ibcon#end of sib2, iclass 22, count 0 2006.173.09:10:54.50#ibcon#*mode == 0, iclass 22, count 0 2006.173.09:10:54.50#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.09:10:54.50#ibcon#[27=USB\r\n] 2006.173.09:10:54.50#ibcon#*before write, iclass 22, count 0 2006.173.09:10:54.50#ibcon#enter sib2, iclass 22, count 0 2006.173.09:10:54.50#ibcon#flushed, iclass 22, count 0 2006.173.09:10:54.50#ibcon#about to write, iclass 22, count 0 2006.173.09:10:54.50#ibcon#wrote, iclass 22, count 0 2006.173.09:10:54.50#ibcon#about to read 3, iclass 22, count 0 2006.173.09:10:54.53#ibcon#read 3, iclass 22, count 0 2006.173.09:10:54.53#ibcon#about to read 4, iclass 22, count 0 2006.173.09:10:54.53#ibcon#read 4, iclass 22, count 0 2006.173.09:10:54.53#ibcon#about to read 5, iclass 22, count 0 2006.173.09:10:54.53#ibcon#read 5, iclass 22, count 0 2006.173.09:10:54.53#ibcon#about to read 6, iclass 22, count 0 2006.173.09:10:54.53#ibcon#read 6, iclass 22, count 0 2006.173.09:10:54.53#ibcon#end of sib2, iclass 22, count 0 2006.173.09:10:54.53#ibcon#*after write, iclass 22, count 0 2006.173.09:10:54.53#ibcon#*before return 0, iclass 22, count 0 2006.173.09:10:54.53#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.09:10:54.53#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.09:10:54.53#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.09:10:54.53#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.09:10:54.53$vck44/vblo=3,649.99 2006.173.09:10:54.53#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.09:10:54.53#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.09:10:54.53#ibcon#ireg 17 cls_cnt 0 2006.173.09:10:54.53#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.09:10:54.53#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.09:10:54.53#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.09:10:54.53#ibcon#enter wrdev, iclass 24, count 0 2006.173.09:10:54.53#ibcon#first serial, iclass 24, count 0 2006.173.09:10:54.53#ibcon#enter sib2, iclass 24, count 0 2006.173.09:10:54.53#ibcon#flushed, iclass 24, count 0 2006.173.09:10:54.53#ibcon#about to write, iclass 24, count 0 2006.173.09:10:54.53#ibcon#wrote, iclass 24, count 0 2006.173.09:10:54.53#ibcon#about to read 3, iclass 24, count 0 2006.173.09:10:54.55#ibcon#read 3, iclass 24, count 0 2006.173.09:10:54.55#ibcon#about to read 4, iclass 24, count 0 2006.173.09:10:54.55#ibcon#read 4, iclass 24, count 0 2006.173.09:10:54.55#ibcon#about to read 5, iclass 24, count 0 2006.173.09:10:54.55#ibcon#read 5, iclass 24, count 0 2006.173.09:10:54.55#ibcon#about to read 6, iclass 24, count 0 2006.173.09:10:54.55#ibcon#read 6, iclass 24, count 0 2006.173.09:10:54.55#ibcon#end of sib2, iclass 24, count 0 2006.173.09:10:54.55#ibcon#*mode == 0, iclass 24, count 0 2006.173.09:10:54.55#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.09:10:54.55#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.09:10:54.55#ibcon#*before write, iclass 24, count 0 2006.173.09:10:54.55#ibcon#enter sib2, iclass 24, count 0 2006.173.09:10:54.55#ibcon#flushed, iclass 24, count 0 2006.173.09:10:54.55#ibcon#about to write, iclass 24, count 0 2006.173.09:10:54.55#ibcon#wrote, iclass 24, count 0 2006.173.09:10:54.55#ibcon#about to read 3, iclass 24, count 0 2006.173.09:10:54.59#ibcon#read 3, iclass 24, count 0 2006.173.09:10:54.59#ibcon#about to read 4, iclass 24, count 0 2006.173.09:10:54.59#ibcon#read 4, iclass 24, count 0 2006.173.09:10:54.59#ibcon#about to read 5, iclass 24, count 0 2006.173.09:10:54.59#ibcon#read 5, iclass 24, count 0 2006.173.09:10:54.59#ibcon#about to read 6, iclass 24, count 0 2006.173.09:10:54.59#ibcon#read 6, iclass 24, count 0 2006.173.09:10:54.59#ibcon#end of sib2, iclass 24, count 0 2006.173.09:10:54.59#ibcon#*after write, iclass 24, count 0 2006.173.09:10:54.59#ibcon#*before return 0, iclass 24, count 0 2006.173.09:10:54.59#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.09:10:54.59#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.09:10:54.59#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.09:10:54.59#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.09:10:54.59$vck44/vb=3,4 2006.173.09:10:54.59#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.09:10:54.59#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.09:10:54.59#ibcon#ireg 11 cls_cnt 2 2006.173.09:10:54.59#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.09:10:54.65#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.09:10:54.65#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.09:10:54.65#ibcon#enter wrdev, iclass 26, count 2 2006.173.09:10:54.65#ibcon#first serial, iclass 26, count 2 2006.173.09:10:54.65#ibcon#enter sib2, iclass 26, count 2 2006.173.09:10:54.65#ibcon#flushed, iclass 26, count 2 2006.173.09:10:54.65#ibcon#about to write, iclass 26, count 2 2006.173.09:10:54.65#ibcon#wrote, iclass 26, count 2 2006.173.09:10:54.65#ibcon#about to read 3, iclass 26, count 2 2006.173.09:10:54.67#ibcon#read 3, iclass 26, count 2 2006.173.09:10:54.67#ibcon#about to read 4, iclass 26, count 2 2006.173.09:10:54.67#ibcon#read 4, iclass 26, count 2 2006.173.09:10:54.67#ibcon#about to read 5, iclass 26, count 2 2006.173.09:10:54.67#ibcon#read 5, iclass 26, count 2 2006.173.09:10:54.67#ibcon#about to read 6, iclass 26, count 2 2006.173.09:10:54.67#ibcon#read 6, iclass 26, count 2 2006.173.09:10:54.67#ibcon#end of sib2, iclass 26, count 2 2006.173.09:10:54.67#ibcon#*mode == 0, iclass 26, count 2 2006.173.09:10:54.67#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.09:10:54.67#ibcon#[27=AT03-04\r\n] 2006.173.09:10:54.67#ibcon#*before write, iclass 26, count 2 2006.173.09:10:54.67#ibcon#enter sib2, iclass 26, count 2 2006.173.09:10:54.67#ibcon#flushed, iclass 26, count 2 2006.173.09:10:54.67#ibcon#about to write, iclass 26, count 2 2006.173.09:10:54.69#ibcon#wrote, iclass 26, count 2 2006.173.09:10:54.69#ibcon#about to read 3, iclass 26, count 2 2006.173.09:10:54.72#ibcon#read 3, iclass 26, count 2 2006.173.09:10:54.72#ibcon#about to read 4, iclass 26, count 2 2006.173.09:10:54.72#ibcon#read 4, iclass 26, count 2 2006.173.09:10:54.72#ibcon#about to read 5, iclass 26, count 2 2006.173.09:10:54.72#ibcon#read 5, iclass 26, count 2 2006.173.09:10:54.72#ibcon#about to read 6, iclass 26, count 2 2006.173.09:10:54.72#ibcon#read 6, iclass 26, count 2 2006.173.09:10:54.72#ibcon#end of sib2, iclass 26, count 2 2006.173.09:10:54.72#ibcon#*after write, iclass 26, count 2 2006.173.09:10:54.72#ibcon#*before return 0, iclass 26, count 2 2006.173.09:10:54.72#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.09:10:54.72#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.09:10:54.72#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.09:10:54.72#ibcon#ireg 7 cls_cnt 0 2006.173.09:10:54.72#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.09:10:54.84#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.09:10:54.84#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.09:10:54.84#ibcon#enter wrdev, iclass 26, count 0 2006.173.09:10:54.84#ibcon#first serial, iclass 26, count 0 2006.173.09:10:54.84#ibcon#enter sib2, iclass 26, count 0 2006.173.09:10:54.84#ibcon#flushed, iclass 26, count 0 2006.173.09:10:54.84#ibcon#about to write, iclass 26, count 0 2006.173.09:10:54.84#ibcon#wrote, iclass 26, count 0 2006.173.09:10:54.84#ibcon#about to read 3, iclass 26, count 0 2006.173.09:10:54.86#ibcon#read 3, iclass 26, count 0 2006.173.09:10:54.86#ibcon#about to read 4, iclass 26, count 0 2006.173.09:10:54.86#ibcon#read 4, iclass 26, count 0 2006.173.09:10:54.86#ibcon#about to read 5, iclass 26, count 0 2006.173.09:10:54.86#ibcon#read 5, iclass 26, count 0 2006.173.09:10:54.86#ibcon#about to read 6, iclass 26, count 0 2006.173.09:10:54.86#ibcon#read 6, iclass 26, count 0 2006.173.09:10:54.86#ibcon#end of sib2, iclass 26, count 0 2006.173.09:10:54.86#ibcon#*mode == 0, iclass 26, count 0 2006.173.09:10:54.86#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.09:10:54.86#ibcon#[27=USB\r\n] 2006.173.09:10:54.86#ibcon#*before write, iclass 26, count 0 2006.173.09:10:54.86#ibcon#enter sib2, iclass 26, count 0 2006.173.09:10:54.86#ibcon#flushed, iclass 26, count 0 2006.173.09:10:54.86#ibcon#about to write, iclass 26, count 0 2006.173.09:10:54.86#ibcon#wrote, iclass 26, count 0 2006.173.09:10:54.86#ibcon#about to read 3, iclass 26, count 0 2006.173.09:10:54.89#ibcon#read 3, iclass 26, count 0 2006.173.09:10:54.89#ibcon#about to read 4, iclass 26, count 0 2006.173.09:10:54.89#ibcon#read 4, iclass 26, count 0 2006.173.09:10:54.89#ibcon#about to read 5, iclass 26, count 0 2006.173.09:10:54.89#ibcon#read 5, iclass 26, count 0 2006.173.09:10:54.89#ibcon#about to read 6, iclass 26, count 0 2006.173.09:10:54.89#ibcon#read 6, iclass 26, count 0 2006.173.09:10:54.89#ibcon#end of sib2, iclass 26, count 0 2006.173.09:10:54.89#ibcon#*after write, iclass 26, count 0 2006.173.09:10:54.89#ibcon#*before return 0, iclass 26, count 0 2006.173.09:10:54.89#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.09:10:54.89#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.09:10:54.89#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.09:10:54.89#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.09:10:54.89$vck44/vblo=4,679.99 2006.173.09:10:54.89#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.09:10:54.89#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.09:10:54.89#ibcon#ireg 17 cls_cnt 0 2006.173.09:10:54.89#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.09:10:54.89#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.09:10:54.89#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.09:10:54.89#ibcon#enter wrdev, iclass 28, count 0 2006.173.09:10:54.89#ibcon#first serial, iclass 28, count 0 2006.173.09:10:54.89#ibcon#enter sib2, iclass 28, count 0 2006.173.09:10:54.89#ibcon#flushed, iclass 28, count 0 2006.173.09:10:54.89#ibcon#about to write, iclass 28, count 0 2006.173.09:10:54.89#ibcon#wrote, iclass 28, count 0 2006.173.09:10:54.89#ibcon#about to read 3, iclass 28, count 0 2006.173.09:10:54.91#ibcon#read 3, iclass 28, count 0 2006.173.09:10:54.91#ibcon#about to read 4, iclass 28, count 0 2006.173.09:10:54.91#ibcon#read 4, iclass 28, count 0 2006.173.09:10:54.91#ibcon#about to read 5, iclass 28, count 0 2006.173.09:10:54.91#ibcon#read 5, iclass 28, count 0 2006.173.09:10:54.91#ibcon#about to read 6, iclass 28, count 0 2006.173.09:10:54.91#ibcon#read 6, iclass 28, count 0 2006.173.09:10:54.91#ibcon#end of sib2, iclass 28, count 0 2006.173.09:10:54.91#ibcon#*mode == 0, iclass 28, count 0 2006.173.09:10:54.91#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.09:10:54.91#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.09:10:54.91#ibcon#*before write, iclass 28, count 0 2006.173.09:10:54.91#ibcon#enter sib2, iclass 28, count 0 2006.173.09:10:54.91#ibcon#flushed, iclass 28, count 0 2006.173.09:10:54.91#ibcon#about to write, iclass 28, count 0 2006.173.09:10:54.91#ibcon#wrote, iclass 28, count 0 2006.173.09:10:54.91#ibcon#about to read 3, iclass 28, count 0 2006.173.09:10:54.95#ibcon#read 3, iclass 28, count 0 2006.173.09:10:54.95#ibcon#about to read 4, iclass 28, count 0 2006.173.09:10:54.95#ibcon#read 4, iclass 28, count 0 2006.173.09:10:54.95#ibcon#about to read 5, iclass 28, count 0 2006.173.09:10:54.95#ibcon#read 5, iclass 28, count 0 2006.173.09:10:54.95#ibcon#about to read 6, iclass 28, count 0 2006.173.09:10:54.95#ibcon#read 6, iclass 28, count 0 2006.173.09:10:54.95#ibcon#end of sib2, iclass 28, count 0 2006.173.09:10:54.95#ibcon#*after write, iclass 28, count 0 2006.173.09:10:54.95#ibcon#*before return 0, iclass 28, count 0 2006.173.09:10:54.95#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.09:10:54.95#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.09:10:54.95#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.09:10:54.95#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.09:10:54.95$vck44/vb=4,4 2006.173.09:10:54.95#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.09:10:54.95#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.09:10:54.95#ibcon#ireg 11 cls_cnt 2 2006.173.09:10:54.95#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.09:10:55.01#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.09:10:55.01#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.09:10:55.01#ibcon#enter wrdev, iclass 30, count 2 2006.173.09:10:55.01#ibcon#first serial, iclass 30, count 2 2006.173.09:10:55.01#ibcon#enter sib2, iclass 30, count 2 2006.173.09:10:55.01#ibcon#flushed, iclass 30, count 2 2006.173.09:10:55.01#ibcon#about to write, iclass 30, count 2 2006.173.09:10:55.01#ibcon#wrote, iclass 30, count 2 2006.173.09:10:55.01#ibcon#about to read 3, iclass 30, count 2 2006.173.09:10:55.03#ibcon#read 3, iclass 30, count 2 2006.173.09:10:55.03#ibcon#about to read 4, iclass 30, count 2 2006.173.09:10:55.03#ibcon#read 4, iclass 30, count 2 2006.173.09:10:55.03#ibcon#about to read 5, iclass 30, count 2 2006.173.09:10:55.03#ibcon#read 5, iclass 30, count 2 2006.173.09:10:55.03#ibcon#about to read 6, iclass 30, count 2 2006.173.09:10:55.03#ibcon#read 6, iclass 30, count 2 2006.173.09:10:55.03#ibcon#end of sib2, iclass 30, count 2 2006.173.09:10:55.03#ibcon#*mode == 0, iclass 30, count 2 2006.173.09:10:55.03#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.09:10:55.03#ibcon#[27=AT04-04\r\n] 2006.173.09:10:55.03#ibcon#*before write, iclass 30, count 2 2006.173.09:10:55.03#ibcon#enter sib2, iclass 30, count 2 2006.173.09:10:55.03#ibcon#flushed, iclass 30, count 2 2006.173.09:10:55.03#ibcon#about to write, iclass 30, count 2 2006.173.09:10:55.03#ibcon#wrote, iclass 30, count 2 2006.173.09:10:55.03#ibcon#about to read 3, iclass 30, count 2 2006.173.09:10:55.06#ibcon#read 3, iclass 30, count 2 2006.173.09:10:55.06#ibcon#about to read 4, iclass 30, count 2 2006.173.09:10:55.06#ibcon#read 4, iclass 30, count 2 2006.173.09:10:55.06#ibcon#about to read 5, iclass 30, count 2 2006.173.09:10:55.06#ibcon#read 5, iclass 30, count 2 2006.173.09:10:55.06#ibcon#about to read 6, iclass 30, count 2 2006.173.09:10:55.06#ibcon#read 6, iclass 30, count 2 2006.173.09:10:55.06#ibcon#end of sib2, iclass 30, count 2 2006.173.09:10:55.06#ibcon#*after write, iclass 30, count 2 2006.173.09:10:55.06#ibcon#*before return 0, iclass 30, count 2 2006.173.09:10:55.06#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.09:10:55.06#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.09:10:55.06#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.09:10:55.06#ibcon#ireg 7 cls_cnt 0 2006.173.09:10:55.06#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.09:10:55.18#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.09:10:55.18#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.09:10:55.18#ibcon#enter wrdev, iclass 30, count 0 2006.173.09:10:55.18#ibcon#first serial, iclass 30, count 0 2006.173.09:10:55.18#ibcon#enter sib2, iclass 30, count 0 2006.173.09:10:55.18#ibcon#flushed, iclass 30, count 0 2006.173.09:10:55.18#ibcon#about to write, iclass 30, count 0 2006.173.09:10:55.18#ibcon#wrote, iclass 30, count 0 2006.173.09:10:55.18#ibcon#about to read 3, iclass 30, count 0 2006.173.09:10:55.20#ibcon#read 3, iclass 30, count 0 2006.173.09:10:55.20#ibcon#about to read 4, iclass 30, count 0 2006.173.09:10:55.20#ibcon#read 4, iclass 30, count 0 2006.173.09:10:55.20#ibcon#about to read 5, iclass 30, count 0 2006.173.09:10:55.20#ibcon#read 5, iclass 30, count 0 2006.173.09:10:55.20#ibcon#about to read 6, iclass 30, count 0 2006.173.09:10:55.20#ibcon#read 6, iclass 30, count 0 2006.173.09:10:55.20#ibcon#end of sib2, iclass 30, count 0 2006.173.09:10:55.20#ibcon#*mode == 0, iclass 30, count 0 2006.173.09:10:55.20#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.09:10:55.20#ibcon#[27=USB\r\n] 2006.173.09:10:55.20#ibcon#*before write, iclass 30, count 0 2006.173.09:10:55.20#ibcon#enter sib2, iclass 30, count 0 2006.173.09:10:55.20#ibcon#flushed, iclass 30, count 0 2006.173.09:10:55.20#ibcon#about to write, iclass 30, count 0 2006.173.09:10:55.20#ibcon#wrote, iclass 30, count 0 2006.173.09:10:55.20#ibcon#about to read 3, iclass 30, count 0 2006.173.09:10:55.23#ibcon#read 3, iclass 30, count 0 2006.173.09:10:55.23#ibcon#about to read 4, iclass 30, count 0 2006.173.09:10:55.23#ibcon#read 4, iclass 30, count 0 2006.173.09:10:55.23#ibcon#about to read 5, iclass 30, count 0 2006.173.09:10:55.23#ibcon#read 5, iclass 30, count 0 2006.173.09:10:55.23#ibcon#about to read 6, iclass 30, count 0 2006.173.09:10:55.23#ibcon#read 6, iclass 30, count 0 2006.173.09:10:55.23#ibcon#end of sib2, iclass 30, count 0 2006.173.09:10:55.23#ibcon#*after write, iclass 30, count 0 2006.173.09:10:55.23#ibcon#*before return 0, iclass 30, count 0 2006.173.09:10:55.23#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.09:10:55.23#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.09:10:55.23#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.09:10:55.23#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.09:10:55.23$vck44/vblo=5,709.99 2006.173.09:10:55.23#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.09:10:55.23#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.09:10:55.23#ibcon#ireg 17 cls_cnt 0 2006.173.09:10:55.23#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.09:10:55.23#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.09:10:55.23#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.09:10:55.23#ibcon#enter wrdev, iclass 32, count 0 2006.173.09:10:55.23#ibcon#first serial, iclass 32, count 0 2006.173.09:10:55.23#ibcon#enter sib2, iclass 32, count 0 2006.173.09:10:55.23#ibcon#flushed, iclass 32, count 0 2006.173.09:10:55.23#ibcon#about to write, iclass 32, count 0 2006.173.09:10:55.23#ibcon#wrote, iclass 32, count 0 2006.173.09:10:55.23#ibcon#about to read 3, iclass 32, count 0 2006.173.09:10:55.25#ibcon#read 3, iclass 32, count 0 2006.173.09:10:55.25#ibcon#about to read 4, iclass 32, count 0 2006.173.09:10:55.25#ibcon#read 4, iclass 32, count 0 2006.173.09:10:55.25#ibcon#about to read 5, iclass 32, count 0 2006.173.09:10:55.25#ibcon#read 5, iclass 32, count 0 2006.173.09:10:55.25#ibcon#about to read 6, iclass 32, count 0 2006.173.09:10:55.25#ibcon#read 6, iclass 32, count 0 2006.173.09:10:55.25#ibcon#end of sib2, iclass 32, count 0 2006.173.09:10:55.25#ibcon#*mode == 0, iclass 32, count 0 2006.173.09:10:55.25#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.09:10:55.25#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.09:10:55.25#ibcon#*before write, iclass 32, count 0 2006.173.09:10:55.25#ibcon#enter sib2, iclass 32, count 0 2006.173.09:10:55.25#ibcon#flushed, iclass 32, count 0 2006.173.09:10:55.25#ibcon#about to write, iclass 32, count 0 2006.173.09:10:55.25#ibcon#wrote, iclass 32, count 0 2006.173.09:10:55.25#ibcon#about to read 3, iclass 32, count 0 2006.173.09:10:55.29#ibcon#read 3, iclass 32, count 0 2006.173.09:10:55.29#ibcon#about to read 4, iclass 32, count 0 2006.173.09:10:55.29#ibcon#read 4, iclass 32, count 0 2006.173.09:10:55.29#ibcon#about to read 5, iclass 32, count 0 2006.173.09:10:55.29#ibcon#read 5, iclass 32, count 0 2006.173.09:10:55.29#ibcon#about to read 6, iclass 32, count 0 2006.173.09:10:55.29#ibcon#read 6, iclass 32, count 0 2006.173.09:10:55.29#ibcon#end of sib2, iclass 32, count 0 2006.173.09:10:55.29#ibcon#*after write, iclass 32, count 0 2006.173.09:10:55.29#ibcon#*before return 0, iclass 32, count 0 2006.173.09:10:55.29#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.09:10:55.29#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.09:10:55.29#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.09:10:55.29#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.09:10:55.29$vck44/vb=5,4 2006.173.09:10:55.29#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.09:10:55.29#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.09:10:55.29#ibcon#ireg 11 cls_cnt 2 2006.173.09:10:55.29#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.09:10:55.35#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.09:10:55.35#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.09:10:55.35#ibcon#enter wrdev, iclass 34, count 2 2006.173.09:10:55.35#ibcon#first serial, iclass 34, count 2 2006.173.09:10:55.35#ibcon#enter sib2, iclass 34, count 2 2006.173.09:10:55.35#ibcon#flushed, iclass 34, count 2 2006.173.09:10:55.35#ibcon#about to write, iclass 34, count 2 2006.173.09:10:55.35#ibcon#wrote, iclass 34, count 2 2006.173.09:10:55.35#ibcon#about to read 3, iclass 34, count 2 2006.173.09:10:55.37#ibcon#read 3, iclass 34, count 2 2006.173.09:10:55.37#ibcon#about to read 4, iclass 34, count 2 2006.173.09:10:55.37#ibcon#read 4, iclass 34, count 2 2006.173.09:10:55.37#ibcon#about to read 5, iclass 34, count 2 2006.173.09:10:55.37#ibcon#read 5, iclass 34, count 2 2006.173.09:10:55.37#ibcon#about to read 6, iclass 34, count 2 2006.173.09:10:55.37#ibcon#read 6, iclass 34, count 2 2006.173.09:10:55.37#ibcon#end of sib2, iclass 34, count 2 2006.173.09:10:55.37#ibcon#*mode == 0, iclass 34, count 2 2006.173.09:10:55.37#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.09:10:55.37#ibcon#[27=AT05-04\r\n] 2006.173.09:10:55.37#ibcon#*before write, iclass 34, count 2 2006.173.09:10:55.37#ibcon#enter sib2, iclass 34, count 2 2006.173.09:10:55.37#ibcon#flushed, iclass 34, count 2 2006.173.09:10:55.37#ibcon#about to write, iclass 34, count 2 2006.173.09:10:55.37#ibcon#wrote, iclass 34, count 2 2006.173.09:10:55.37#ibcon#about to read 3, iclass 34, count 2 2006.173.09:10:55.40#ibcon#read 3, iclass 34, count 2 2006.173.09:10:55.40#ibcon#about to read 4, iclass 34, count 2 2006.173.09:10:55.40#ibcon#read 4, iclass 34, count 2 2006.173.09:10:55.40#ibcon#about to read 5, iclass 34, count 2 2006.173.09:10:55.40#ibcon#read 5, iclass 34, count 2 2006.173.09:10:55.40#ibcon#about to read 6, iclass 34, count 2 2006.173.09:10:55.40#ibcon#read 6, iclass 34, count 2 2006.173.09:10:55.40#ibcon#end of sib2, iclass 34, count 2 2006.173.09:10:55.40#ibcon#*after write, iclass 34, count 2 2006.173.09:10:55.40#ibcon#*before return 0, iclass 34, count 2 2006.173.09:10:55.40#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.09:10:55.40#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.09:10:55.40#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.09:10:55.40#ibcon#ireg 7 cls_cnt 0 2006.173.09:10:55.40#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.09:10:55.52#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.09:10:55.52#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.09:10:55.52#ibcon#enter wrdev, iclass 34, count 0 2006.173.09:10:55.52#ibcon#first serial, iclass 34, count 0 2006.173.09:10:55.52#ibcon#enter sib2, iclass 34, count 0 2006.173.09:10:55.52#ibcon#flushed, iclass 34, count 0 2006.173.09:10:55.52#ibcon#about to write, iclass 34, count 0 2006.173.09:10:55.52#ibcon#wrote, iclass 34, count 0 2006.173.09:10:55.52#ibcon#about to read 3, iclass 34, count 0 2006.173.09:10:55.54#ibcon#read 3, iclass 34, count 0 2006.173.09:10:55.54#ibcon#about to read 4, iclass 34, count 0 2006.173.09:10:55.54#ibcon#read 4, iclass 34, count 0 2006.173.09:10:55.54#ibcon#about to read 5, iclass 34, count 0 2006.173.09:10:55.54#ibcon#read 5, iclass 34, count 0 2006.173.09:10:55.54#ibcon#about to read 6, iclass 34, count 0 2006.173.09:10:55.54#ibcon#read 6, iclass 34, count 0 2006.173.09:10:55.54#ibcon#end of sib2, iclass 34, count 0 2006.173.09:10:55.54#ibcon#*mode == 0, iclass 34, count 0 2006.173.09:10:55.54#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.09:10:55.54#ibcon#[27=USB\r\n] 2006.173.09:10:55.54#ibcon#*before write, iclass 34, count 0 2006.173.09:10:55.54#ibcon#enter sib2, iclass 34, count 0 2006.173.09:10:55.54#ibcon#flushed, iclass 34, count 0 2006.173.09:10:55.54#ibcon#about to write, iclass 34, count 0 2006.173.09:10:55.54#ibcon#wrote, iclass 34, count 0 2006.173.09:10:55.54#ibcon#about to read 3, iclass 34, count 0 2006.173.09:10:55.57#ibcon#read 3, iclass 34, count 0 2006.173.09:10:55.57#ibcon#about to read 4, iclass 34, count 0 2006.173.09:10:55.57#ibcon#read 4, iclass 34, count 0 2006.173.09:10:55.57#ibcon#about to read 5, iclass 34, count 0 2006.173.09:10:55.57#ibcon#read 5, iclass 34, count 0 2006.173.09:10:55.57#ibcon#about to read 6, iclass 34, count 0 2006.173.09:10:55.57#ibcon#read 6, iclass 34, count 0 2006.173.09:10:55.57#ibcon#end of sib2, iclass 34, count 0 2006.173.09:10:55.57#ibcon#*after write, iclass 34, count 0 2006.173.09:10:55.57#ibcon#*before return 0, iclass 34, count 0 2006.173.09:10:55.57#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.09:10:55.57#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.09:10:55.57#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.09:10:55.57#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.09:10:55.57$vck44/vblo=6,719.99 2006.173.09:10:55.57#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.09:10:55.57#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.09:10:55.57#ibcon#ireg 17 cls_cnt 0 2006.173.09:10:55.57#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.09:10:55.57#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.09:10:55.57#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.09:10:55.57#ibcon#enter wrdev, iclass 36, count 0 2006.173.09:10:55.57#ibcon#first serial, iclass 36, count 0 2006.173.09:10:55.57#ibcon#enter sib2, iclass 36, count 0 2006.173.09:10:55.57#ibcon#flushed, iclass 36, count 0 2006.173.09:10:55.57#ibcon#about to write, iclass 36, count 0 2006.173.09:10:55.57#ibcon#wrote, iclass 36, count 0 2006.173.09:10:55.57#ibcon#about to read 3, iclass 36, count 0 2006.173.09:10:55.59#ibcon#read 3, iclass 36, count 0 2006.173.09:10:55.59#ibcon#about to read 4, iclass 36, count 0 2006.173.09:10:55.59#ibcon#read 4, iclass 36, count 0 2006.173.09:10:55.59#ibcon#about to read 5, iclass 36, count 0 2006.173.09:10:55.59#ibcon#read 5, iclass 36, count 0 2006.173.09:10:55.59#ibcon#about to read 6, iclass 36, count 0 2006.173.09:10:55.59#ibcon#read 6, iclass 36, count 0 2006.173.09:10:55.59#ibcon#end of sib2, iclass 36, count 0 2006.173.09:10:55.59#ibcon#*mode == 0, iclass 36, count 0 2006.173.09:10:55.59#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.09:10:55.59#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.09:10:55.59#ibcon#*before write, iclass 36, count 0 2006.173.09:10:55.59#ibcon#enter sib2, iclass 36, count 0 2006.173.09:10:55.59#ibcon#flushed, iclass 36, count 0 2006.173.09:10:55.59#ibcon#about to write, iclass 36, count 0 2006.173.09:10:55.59#ibcon#wrote, iclass 36, count 0 2006.173.09:10:55.59#ibcon#about to read 3, iclass 36, count 0 2006.173.09:10:55.63#ibcon#read 3, iclass 36, count 0 2006.173.09:10:55.63#ibcon#about to read 4, iclass 36, count 0 2006.173.09:10:55.63#ibcon#read 4, iclass 36, count 0 2006.173.09:10:55.63#ibcon#about to read 5, iclass 36, count 0 2006.173.09:10:55.63#ibcon#read 5, iclass 36, count 0 2006.173.09:10:55.63#ibcon#about to read 6, iclass 36, count 0 2006.173.09:10:55.63#ibcon#read 6, iclass 36, count 0 2006.173.09:10:55.63#ibcon#end of sib2, iclass 36, count 0 2006.173.09:10:55.63#ibcon#*after write, iclass 36, count 0 2006.173.09:10:55.63#ibcon#*before return 0, iclass 36, count 0 2006.173.09:10:55.63#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.09:10:55.63#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.09:10:55.63#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.09:10:55.63#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.09:10:55.63$vck44/vb=6,4 2006.173.09:10:55.63#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.09:10:55.63#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.09:10:55.63#ibcon#ireg 11 cls_cnt 2 2006.173.09:10:55.63#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.09:10:55.69#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.09:10:55.69#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.09:10:55.69#ibcon#enter wrdev, iclass 38, count 2 2006.173.09:10:55.69#ibcon#first serial, iclass 38, count 2 2006.173.09:10:55.69#ibcon#enter sib2, iclass 38, count 2 2006.173.09:10:55.69#ibcon#flushed, iclass 38, count 2 2006.173.09:10:55.69#ibcon#about to write, iclass 38, count 2 2006.173.09:10:55.69#ibcon#wrote, iclass 38, count 2 2006.173.09:10:55.69#ibcon#about to read 3, iclass 38, count 2 2006.173.09:10:55.71#ibcon#read 3, iclass 38, count 2 2006.173.09:10:55.71#ibcon#about to read 4, iclass 38, count 2 2006.173.09:10:55.71#ibcon#read 4, iclass 38, count 2 2006.173.09:10:55.71#ibcon#about to read 5, iclass 38, count 2 2006.173.09:10:55.71#ibcon#read 5, iclass 38, count 2 2006.173.09:10:55.71#ibcon#about to read 6, iclass 38, count 2 2006.173.09:10:55.71#ibcon#read 6, iclass 38, count 2 2006.173.09:10:55.71#ibcon#end of sib2, iclass 38, count 2 2006.173.09:10:55.71#ibcon#*mode == 0, iclass 38, count 2 2006.173.09:10:55.71#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.09:10:55.71#ibcon#[27=AT06-04\r\n] 2006.173.09:10:55.71#ibcon#*before write, iclass 38, count 2 2006.173.09:10:55.71#ibcon#enter sib2, iclass 38, count 2 2006.173.09:10:55.71#ibcon#flushed, iclass 38, count 2 2006.173.09:10:55.71#ibcon#about to write, iclass 38, count 2 2006.173.09:10:55.71#ibcon#wrote, iclass 38, count 2 2006.173.09:10:55.71#ibcon#about to read 3, iclass 38, count 2 2006.173.09:10:55.74#ibcon#read 3, iclass 38, count 2 2006.173.09:10:55.74#ibcon#about to read 4, iclass 38, count 2 2006.173.09:10:55.74#ibcon#read 4, iclass 38, count 2 2006.173.09:10:55.74#ibcon#about to read 5, iclass 38, count 2 2006.173.09:10:55.74#ibcon#read 5, iclass 38, count 2 2006.173.09:10:55.74#ibcon#about to read 6, iclass 38, count 2 2006.173.09:10:55.74#ibcon#read 6, iclass 38, count 2 2006.173.09:10:55.74#ibcon#end of sib2, iclass 38, count 2 2006.173.09:10:55.74#ibcon#*after write, iclass 38, count 2 2006.173.09:10:55.74#ibcon#*before return 0, iclass 38, count 2 2006.173.09:10:55.74#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.09:10:55.74#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.09:10:55.74#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.09:10:55.74#ibcon#ireg 7 cls_cnt 0 2006.173.09:10:55.74#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.09:10:55.86#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.09:10:55.86#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.09:10:55.86#ibcon#enter wrdev, iclass 38, count 0 2006.173.09:10:55.86#ibcon#first serial, iclass 38, count 0 2006.173.09:10:55.86#ibcon#enter sib2, iclass 38, count 0 2006.173.09:10:55.86#ibcon#flushed, iclass 38, count 0 2006.173.09:10:55.86#ibcon#about to write, iclass 38, count 0 2006.173.09:10:55.86#ibcon#wrote, iclass 38, count 0 2006.173.09:10:55.86#ibcon#about to read 3, iclass 38, count 0 2006.173.09:10:55.88#ibcon#read 3, iclass 38, count 0 2006.173.09:10:55.88#ibcon#about to read 4, iclass 38, count 0 2006.173.09:10:55.88#ibcon#read 4, iclass 38, count 0 2006.173.09:10:55.88#ibcon#about to read 5, iclass 38, count 0 2006.173.09:10:55.88#ibcon#read 5, iclass 38, count 0 2006.173.09:10:55.88#ibcon#about to read 6, iclass 38, count 0 2006.173.09:10:55.88#ibcon#read 6, iclass 38, count 0 2006.173.09:10:55.88#ibcon#end of sib2, iclass 38, count 0 2006.173.09:10:55.88#ibcon#*mode == 0, iclass 38, count 0 2006.173.09:10:55.88#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.09:10:55.88#ibcon#[27=USB\r\n] 2006.173.09:10:55.88#ibcon#*before write, iclass 38, count 0 2006.173.09:10:55.88#ibcon#enter sib2, iclass 38, count 0 2006.173.09:10:55.88#ibcon#flushed, iclass 38, count 0 2006.173.09:10:55.88#ibcon#about to write, iclass 38, count 0 2006.173.09:10:55.88#ibcon#wrote, iclass 38, count 0 2006.173.09:10:55.88#ibcon#about to read 3, iclass 38, count 0 2006.173.09:10:55.91#ibcon#read 3, iclass 38, count 0 2006.173.09:10:55.91#ibcon#about to read 4, iclass 38, count 0 2006.173.09:10:55.91#ibcon#read 4, iclass 38, count 0 2006.173.09:10:55.91#ibcon#about to read 5, iclass 38, count 0 2006.173.09:10:55.91#ibcon#read 5, iclass 38, count 0 2006.173.09:10:55.91#ibcon#about to read 6, iclass 38, count 0 2006.173.09:10:55.91#ibcon#read 6, iclass 38, count 0 2006.173.09:10:55.91#ibcon#end of sib2, iclass 38, count 0 2006.173.09:10:55.91#ibcon#*after write, iclass 38, count 0 2006.173.09:10:55.91#ibcon#*before return 0, iclass 38, count 0 2006.173.09:10:55.91#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.09:10:55.91#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.09:10:55.91#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.09:10:55.91#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.09:10:55.91$vck44/vblo=7,734.99 2006.173.09:10:55.91#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.09:10:55.91#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.09:10:55.91#ibcon#ireg 17 cls_cnt 0 2006.173.09:10:55.91#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.09:10:55.91#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.09:10:55.91#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.09:10:55.91#ibcon#enter wrdev, iclass 40, count 0 2006.173.09:10:55.91#ibcon#first serial, iclass 40, count 0 2006.173.09:10:55.91#ibcon#enter sib2, iclass 40, count 0 2006.173.09:10:55.91#ibcon#flushed, iclass 40, count 0 2006.173.09:10:55.91#ibcon#about to write, iclass 40, count 0 2006.173.09:10:55.91#ibcon#wrote, iclass 40, count 0 2006.173.09:10:55.91#ibcon#about to read 3, iclass 40, count 0 2006.173.09:10:55.93#ibcon#read 3, iclass 40, count 0 2006.173.09:10:55.93#ibcon#about to read 4, iclass 40, count 0 2006.173.09:10:55.93#ibcon#read 4, iclass 40, count 0 2006.173.09:10:55.93#ibcon#about to read 5, iclass 40, count 0 2006.173.09:10:55.93#ibcon#read 5, iclass 40, count 0 2006.173.09:10:55.93#ibcon#about to read 6, iclass 40, count 0 2006.173.09:10:55.93#ibcon#read 6, iclass 40, count 0 2006.173.09:10:55.93#ibcon#end of sib2, iclass 40, count 0 2006.173.09:10:55.93#ibcon#*mode == 0, iclass 40, count 0 2006.173.09:10:55.93#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.09:10:55.93#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.09:10:55.93#ibcon#*before write, iclass 40, count 0 2006.173.09:10:55.93#ibcon#enter sib2, iclass 40, count 0 2006.173.09:10:55.93#ibcon#flushed, iclass 40, count 0 2006.173.09:10:55.93#ibcon#about to write, iclass 40, count 0 2006.173.09:10:55.93#ibcon#wrote, iclass 40, count 0 2006.173.09:10:55.93#ibcon#about to read 3, iclass 40, count 0 2006.173.09:10:55.97#ibcon#read 3, iclass 40, count 0 2006.173.09:10:55.97#ibcon#about to read 4, iclass 40, count 0 2006.173.09:10:55.97#ibcon#read 4, iclass 40, count 0 2006.173.09:10:55.97#ibcon#about to read 5, iclass 40, count 0 2006.173.09:10:55.97#ibcon#read 5, iclass 40, count 0 2006.173.09:10:55.97#ibcon#about to read 6, iclass 40, count 0 2006.173.09:10:55.97#ibcon#read 6, iclass 40, count 0 2006.173.09:10:55.97#ibcon#end of sib2, iclass 40, count 0 2006.173.09:10:55.97#ibcon#*after write, iclass 40, count 0 2006.173.09:10:55.97#ibcon#*before return 0, iclass 40, count 0 2006.173.09:10:55.97#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.09:10:55.97#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.09:10:55.97#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.09:10:55.97#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.09:10:55.97$vck44/vb=7,4 2006.173.09:10:55.97#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.09:10:55.97#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.09:10:55.97#ibcon#ireg 11 cls_cnt 2 2006.173.09:10:55.97#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.09:10:56.03#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.09:10:56.03#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.09:10:56.03#ibcon#enter wrdev, iclass 4, count 2 2006.173.09:10:56.03#ibcon#first serial, iclass 4, count 2 2006.173.09:10:56.03#ibcon#enter sib2, iclass 4, count 2 2006.173.09:10:56.03#ibcon#flushed, iclass 4, count 2 2006.173.09:10:56.03#ibcon#about to write, iclass 4, count 2 2006.173.09:10:56.03#ibcon#wrote, iclass 4, count 2 2006.173.09:10:56.03#ibcon#about to read 3, iclass 4, count 2 2006.173.09:10:56.05#ibcon#read 3, iclass 4, count 2 2006.173.09:10:56.05#ibcon#about to read 4, iclass 4, count 2 2006.173.09:10:56.05#ibcon#read 4, iclass 4, count 2 2006.173.09:10:56.05#ibcon#about to read 5, iclass 4, count 2 2006.173.09:10:56.05#ibcon#read 5, iclass 4, count 2 2006.173.09:10:56.05#ibcon#about to read 6, iclass 4, count 2 2006.173.09:10:56.05#ibcon#read 6, iclass 4, count 2 2006.173.09:10:56.05#ibcon#end of sib2, iclass 4, count 2 2006.173.09:10:56.05#ibcon#*mode == 0, iclass 4, count 2 2006.173.09:10:56.05#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.09:10:56.05#ibcon#[27=AT07-04\r\n] 2006.173.09:10:56.05#ibcon#*before write, iclass 4, count 2 2006.173.09:10:56.05#ibcon#enter sib2, iclass 4, count 2 2006.173.09:10:56.05#ibcon#flushed, iclass 4, count 2 2006.173.09:10:56.05#ibcon#about to write, iclass 4, count 2 2006.173.09:10:56.05#ibcon#wrote, iclass 4, count 2 2006.173.09:10:56.05#ibcon#about to read 3, iclass 4, count 2 2006.173.09:10:56.08#ibcon#read 3, iclass 4, count 2 2006.173.09:10:56.08#ibcon#about to read 4, iclass 4, count 2 2006.173.09:10:56.08#ibcon#read 4, iclass 4, count 2 2006.173.09:10:56.08#ibcon#about to read 5, iclass 4, count 2 2006.173.09:10:56.08#ibcon#read 5, iclass 4, count 2 2006.173.09:10:56.08#ibcon#about to read 6, iclass 4, count 2 2006.173.09:10:56.08#ibcon#read 6, iclass 4, count 2 2006.173.09:10:56.08#ibcon#end of sib2, iclass 4, count 2 2006.173.09:10:56.08#ibcon#*after write, iclass 4, count 2 2006.173.09:10:56.08#ibcon#*before return 0, iclass 4, count 2 2006.173.09:10:56.08#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.09:10:56.08#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.09:10:56.08#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.09:10:56.08#ibcon#ireg 7 cls_cnt 0 2006.173.09:10:56.08#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.09:10:56.20#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.09:10:56.20#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.09:10:56.20#ibcon#enter wrdev, iclass 4, count 0 2006.173.09:10:56.20#ibcon#first serial, iclass 4, count 0 2006.173.09:10:56.20#ibcon#enter sib2, iclass 4, count 0 2006.173.09:10:56.20#ibcon#flushed, iclass 4, count 0 2006.173.09:10:56.20#ibcon#about to write, iclass 4, count 0 2006.173.09:10:56.20#ibcon#wrote, iclass 4, count 0 2006.173.09:10:56.20#ibcon#about to read 3, iclass 4, count 0 2006.173.09:10:56.22#ibcon#read 3, iclass 4, count 0 2006.173.09:10:56.22#ibcon#about to read 4, iclass 4, count 0 2006.173.09:10:56.22#ibcon#read 4, iclass 4, count 0 2006.173.09:10:56.22#ibcon#about to read 5, iclass 4, count 0 2006.173.09:10:56.22#ibcon#read 5, iclass 4, count 0 2006.173.09:10:56.22#ibcon#about to read 6, iclass 4, count 0 2006.173.09:10:56.22#ibcon#read 6, iclass 4, count 0 2006.173.09:10:56.22#ibcon#end of sib2, iclass 4, count 0 2006.173.09:10:56.22#ibcon#*mode == 0, iclass 4, count 0 2006.173.09:10:56.22#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.09:10:56.22#ibcon#[27=USB\r\n] 2006.173.09:10:56.22#ibcon#*before write, iclass 4, count 0 2006.173.09:10:56.22#ibcon#enter sib2, iclass 4, count 0 2006.173.09:10:56.22#ibcon#flushed, iclass 4, count 0 2006.173.09:10:56.22#ibcon#about to write, iclass 4, count 0 2006.173.09:10:56.22#ibcon#wrote, iclass 4, count 0 2006.173.09:10:56.22#ibcon#about to read 3, iclass 4, count 0 2006.173.09:10:56.25#ibcon#read 3, iclass 4, count 0 2006.173.09:10:56.25#ibcon#about to read 4, iclass 4, count 0 2006.173.09:10:56.25#ibcon#read 4, iclass 4, count 0 2006.173.09:10:56.25#ibcon#about to read 5, iclass 4, count 0 2006.173.09:10:56.25#ibcon#read 5, iclass 4, count 0 2006.173.09:10:56.25#ibcon#about to read 6, iclass 4, count 0 2006.173.09:10:56.25#ibcon#read 6, iclass 4, count 0 2006.173.09:10:56.25#ibcon#end of sib2, iclass 4, count 0 2006.173.09:10:56.25#ibcon#*after write, iclass 4, count 0 2006.173.09:10:56.25#ibcon#*before return 0, iclass 4, count 0 2006.173.09:10:56.25#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.09:10:56.25#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.09:10:56.25#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.09:10:56.25#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.09:10:56.25$vck44/vblo=8,744.99 2006.173.09:10:56.25#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.09:10:56.25#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.09:10:56.25#ibcon#ireg 17 cls_cnt 0 2006.173.09:10:56.25#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.09:10:56.25#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.09:10:56.25#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.09:10:56.25#ibcon#enter wrdev, iclass 6, count 0 2006.173.09:10:56.25#ibcon#first serial, iclass 6, count 0 2006.173.09:10:56.25#ibcon#enter sib2, iclass 6, count 0 2006.173.09:10:56.25#ibcon#flushed, iclass 6, count 0 2006.173.09:10:56.25#ibcon#about to write, iclass 6, count 0 2006.173.09:10:56.25#ibcon#wrote, iclass 6, count 0 2006.173.09:10:56.25#ibcon#about to read 3, iclass 6, count 0 2006.173.09:10:56.27#ibcon#read 3, iclass 6, count 0 2006.173.09:10:56.27#ibcon#about to read 4, iclass 6, count 0 2006.173.09:10:56.27#ibcon#read 4, iclass 6, count 0 2006.173.09:10:56.27#ibcon#about to read 5, iclass 6, count 0 2006.173.09:10:56.27#ibcon#read 5, iclass 6, count 0 2006.173.09:10:56.27#ibcon#about to read 6, iclass 6, count 0 2006.173.09:10:56.27#ibcon#read 6, iclass 6, count 0 2006.173.09:10:56.27#ibcon#end of sib2, iclass 6, count 0 2006.173.09:10:56.27#ibcon#*mode == 0, iclass 6, count 0 2006.173.09:10:56.27#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.09:10:56.27#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.09:10:56.27#ibcon#*before write, iclass 6, count 0 2006.173.09:10:56.27#ibcon#enter sib2, iclass 6, count 0 2006.173.09:10:56.27#ibcon#flushed, iclass 6, count 0 2006.173.09:10:56.27#ibcon#about to write, iclass 6, count 0 2006.173.09:10:56.27#ibcon#wrote, iclass 6, count 0 2006.173.09:10:56.27#ibcon#about to read 3, iclass 6, count 0 2006.173.09:10:56.31#ibcon#read 3, iclass 6, count 0 2006.173.09:10:56.31#ibcon#about to read 4, iclass 6, count 0 2006.173.09:10:56.31#ibcon#read 4, iclass 6, count 0 2006.173.09:10:56.31#ibcon#about to read 5, iclass 6, count 0 2006.173.09:10:56.31#ibcon#read 5, iclass 6, count 0 2006.173.09:10:56.31#ibcon#about to read 6, iclass 6, count 0 2006.173.09:10:56.31#ibcon#read 6, iclass 6, count 0 2006.173.09:10:56.31#ibcon#end of sib2, iclass 6, count 0 2006.173.09:10:56.31#ibcon#*after write, iclass 6, count 0 2006.173.09:10:56.31#ibcon#*before return 0, iclass 6, count 0 2006.173.09:10:56.31#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.09:10:56.31#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.09:10:56.31#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.09:10:56.31#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.09:10:56.31$vck44/vb=8,4 2006.173.09:10:56.31#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.09:10:56.31#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.09:10:56.31#ibcon#ireg 11 cls_cnt 2 2006.173.09:10:56.31#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.09:10:56.37#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.09:10:56.37#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.09:10:56.37#ibcon#enter wrdev, iclass 10, count 2 2006.173.09:10:56.37#ibcon#first serial, iclass 10, count 2 2006.173.09:10:56.37#ibcon#enter sib2, iclass 10, count 2 2006.173.09:10:56.37#ibcon#flushed, iclass 10, count 2 2006.173.09:10:56.37#ibcon#about to write, iclass 10, count 2 2006.173.09:10:56.37#ibcon#wrote, iclass 10, count 2 2006.173.09:10:56.37#ibcon#about to read 3, iclass 10, count 2 2006.173.09:10:56.39#ibcon#read 3, iclass 10, count 2 2006.173.09:10:56.39#ibcon#about to read 4, iclass 10, count 2 2006.173.09:10:56.39#ibcon#read 4, iclass 10, count 2 2006.173.09:10:56.39#ibcon#about to read 5, iclass 10, count 2 2006.173.09:10:56.39#ibcon#read 5, iclass 10, count 2 2006.173.09:10:56.39#ibcon#about to read 6, iclass 10, count 2 2006.173.09:10:56.39#ibcon#read 6, iclass 10, count 2 2006.173.09:10:56.39#ibcon#end of sib2, iclass 10, count 2 2006.173.09:10:56.39#ibcon#*mode == 0, iclass 10, count 2 2006.173.09:10:56.39#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.09:10:56.39#ibcon#[27=AT08-04\r\n] 2006.173.09:10:56.39#ibcon#*before write, iclass 10, count 2 2006.173.09:10:56.39#ibcon#enter sib2, iclass 10, count 2 2006.173.09:10:56.39#ibcon#flushed, iclass 10, count 2 2006.173.09:10:56.39#ibcon#about to write, iclass 10, count 2 2006.173.09:10:56.39#ibcon#wrote, iclass 10, count 2 2006.173.09:10:56.39#ibcon#about to read 3, iclass 10, count 2 2006.173.09:10:56.42#ibcon#read 3, iclass 10, count 2 2006.173.09:10:56.42#ibcon#about to read 4, iclass 10, count 2 2006.173.09:10:56.42#ibcon#read 4, iclass 10, count 2 2006.173.09:10:56.42#ibcon#about to read 5, iclass 10, count 2 2006.173.09:10:56.42#ibcon#read 5, iclass 10, count 2 2006.173.09:10:56.42#ibcon#about to read 6, iclass 10, count 2 2006.173.09:10:56.42#ibcon#read 6, iclass 10, count 2 2006.173.09:10:56.42#ibcon#end of sib2, iclass 10, count 2 2006.173.09:10:56.42#ibcon#*after write, iclass 10, count 2 2006.173.09:10:56.42#ibcon#*before return 0, iclass 10, count 2 2006.173.09:10:56.42#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.09:10:56.42#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.09:10:56.42#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.09:10:56.42#ibcon#ireg 7 cls_cnt 0 2006.173.09:10:56.42#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.09:10:56.54#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.09:10:56.54#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.09:10:56.54#ibcon#enter wrdev, iclass 10, count 0 2006.173.09:10:56.54#ibcon#first serial, iclass 10, count 0 2006.173.09:10:56.54#ibcon#enter sib2, iclass 10, count 0 2006.173.09:10:56.54#ibcon#flushed, iclass 10, count 0 2006.173.09:10:56.54#ibcon#about to write, iclass 10, count 0 2006.173.09:10:56.54#ibcon#wrote, iclass 10, count 0 2006.173.09:10:56.54#ibcon#about to read 3, iclass 10, count 0 2006.173.09:10:56.56#ibcon#read 3, iclass 10, count 0 2006.173.09:10:56.56#ibcon#about to read 4, iclass 10, count 0 2006.173.09:10:56.56#ibcon#read 4, iclass 10, count 0 2006.173.09:10:56.56#ibcon#about to read 5, iclass 10, count 0 2006.173.09:10:56.56#ibcon#read 5, iclass 10, count 0 2006.173.09:10:56.56#ibcon#about to read 6, iclass 10, count 0 2006.173.09:10:56.56#ibcon#read 6, iclass 10, count 0 2006.173.09:10:56.56#ibcon#end of sib2, iclass 10, count 0 2006.173.09:10:56.56#ibcon#*mode == 0, iclass 10, count 0 2006.173.09:10:56.56#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.09:10:56.56#ibcon#[27=USB\r\n] 2006.173.09:10:56.56#ibcon#*before write, iclass 10, count 0 2006.173.09:10:56.56#ibcon#enter sib2, iclass 10, count 0 2006.173.09:10:56.56#ibcon#flushed, iclass 10, count 0 2006.173.09:10:56.56#ibcon#about to write, iclass 10, count 0 2006.173.09:10:56.56#ibcon#wrote, iclass 10, count 0 2006.173.09:10:56.56#ibcon#about to read 3, iclass 10, count 0 2006.173.09:10:56.59#ibcon#read 3, iclass 10, count 0 2006.173.09:10:56.59#ibcon#about to read 4, iclass 10, count 0 2006.173.09:10:56.59#ibcon#read 4, iclass 10, count 0 2006.173.09:10:56.59#ibcon#about to read 5, iclass 10, count 0 2006.173.09:10:56.59#ibcon#read 5, iclass 10, count 0 2006.173.09:10:56.59#ibcon#about to read 6, iclass 10, count 0 2006.173.09:10:56.59#ibcon#read 6, iclass 10, count 0 2006.173.09:10:56.59#ibcon#end of sib2, iclass 10, count 0 2006.173.09:10:56.59#ibcon#*after write, iclass 10, count 0 2006.173.09:10:56.59#ibcon#*before return 0, iclass 10, count 0 2006.173.09:10:56.59#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.09:10:56.59#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.09:10:56.59#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.09:10:56.59#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.09:10:56.59$vck44/vabw=wide 2006.173.09:10:56.59#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.09:10:56.59#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.09:10:56.59#ibcon#ireg 8 cls_cnt 0 2006.173.09:10:56.59#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.09:10:56.59#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.09:10:56.59#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.09:10:56.59#ibcon#enter wrdev, iclass 12, count 0 2006.173.09:10:56.59#ibcon#first serial, iclass 12, count 0 2006.173.09:10:56.59#ibcon#enter sib2, iclass 12, count 0 2006.173.09:10:56.59#ibcon#flushed, iclass 12, count 0 2006.173.09:10:56.59#ibcon#about to write, iclass 12, count 0 2006.173.09:10:56.59#ibcon#wrote, iclass 12, count 0 2006.173.09:10:56.59#ibcon#about to read 3, iclass 12, count 0 2006.173.09:10:56.61#ibcon#read 3, iclass 12, count 0 2006.173.09:10:56.61#ibcon#about to read 4, iclass 12, count 0 2006.173.09:10:56.61#ibcon#read 4, iclass 12, count 0 2006.173.09:10:56.61#ibcon#about to read 5, iclass 12, count 0 2006.173.09:10:56.61#ibcon#read 5, iclass 12, count 0 2006.173.09:10:56.61#ibcon#about to read 6, iclass 12, count 0 2006.173.09:10:56.61#ibcon#read 6, iclass 12, count 0 2006.173.09:10:56.61#ibcon#end of sib2, iclass 12, count 0 2006.173.09:10:56.61#ibcon#*mode == 0, iclass 12, count 0 2006.173.09:10:56.61#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.09:10:56.61#ibcon#[25=BW32\r\n] 2006.173.09:10:56.61#ibcon#*before write, iclass 12, count 0 2006.173.09:10:56.61#ibcon#enter sib2, iclass 12, count 0 2006.173.09:10:56.61#ibcon#flushed, iclass 12, count 0 2006.173.09:10:56.61#ibcon#about to write, iclass 12, count 0 2006.173.09:10:56.61#ibcon#wrote, iclass 12, count 0 2006.173.09:10:56.61#ibcon#about to read 3, iclass 12, count 0 2006.173.09:10:56.64#ibcon#read 3, iclass 12, count 0 2006.173.09:10:56.64#ibcon#about to read 4, iclass 12, count 0 2006.173.09:10:56.64#ibcon#read 4, iclass 12, count 0 2006.173.09:10:56.64#ibcon#about to read 5, iclass 12, count 0 2006.173.09:10:56.64#ibcon#read 5, iclass 12, count 0 2006.173.09:10:56.64#ibcon#about to read 6, iclass 12, count 0 2006.173.09:10:56.64#ibcon#read 6, iclass 12, count 0 2006.173.09:10:56.64#ibcon#end of sib2, iclass 12, count 0 2006.173.09:10:56.64#ibcon#*after write, iclass 12, count 0 2006.173.09:10:56.64#ibcon#*before return 0, iclass 12, count 0 2006.173.09:10:56.64#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.09:10:56.64#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.09:10:56.64#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.09:10:56.64#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.09:10:56.64$vck44/vbbw=wide 2006.173.09:10:56.64#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.09:10:56.64#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.09:10:56.64#ibcon#ireg 8 cls_cnt 0 2006.173.09:10:56.64#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.09:10:56.71#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.09:10:56.71#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.09:10:56.71#ibcon#enter wrdev, iclass 14, count 0 2006.173.09:10:56.71#ibcon#first serial, iclass 14, count 0 2006.173.09:10:56.71#ibcon#enter sib2, iclass 14, count 0 2006.173.09:10:56.71#ibcon#flushed, iclass 14, count 0 2006.173.09:10:56.71#ibcon#about to write, iclass 14, count 0 2006.173.09:10:56.71#ibcon#wrote, iclass 14, count 0 2006.173.09:10:56.71#ibcon#about to read 3, iclass 14, count 0 2006.173.09:10:56.73#ibcon#read 3, iclass 14, count 0 2006.173.09:10:56.73#ibcon#about to read 4, iclass 14, count 0 2006.173.09:10:56.73#ibcon#read 4, iclass 14, count 0 2006.173.09:10:56.73#ibcon#about to read 5, iclass 14, count 0 2006.173.09:10:56.73#ibcon#read 5, iclass 14, count 0 2006.173.09:10:56.73#ibcon#about to read 6, iclass 14, count 0 2006.173.09:10:56.73#ibcon#read 6, iclass 14, count 0 2006.173.09:10:56.73#ibcon#end of sib2, iclass 14, count 0 2006.173.09:10:56.73#ibcon#*mode == 0, iclass 14, count 0 2006.173.09:10:56.73#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.09:10:56.73#ibcon#[27=BW32\r\n] 2006.173.09:10:56.73#ibcon#*before write, iclass 14, count 0 2006.173.09:10:56.73#ibcon#enter sib2, iclass 14, count 0 2006.173.09:10:56.73#ibcon#flushed, iclass 14, count 0 2006.173.09:10:56.73#ibcon#about to write, iclass 14, count 0 2006.173.09:10:56.73#ibcon#wrote, iclass 14, count 0 2006.173.09:10:56.73#ibcon#about to read 3, iclass 14, count 0 2006.173.09:10:56.76#ibcon#read 3, iclass 14, count 0 2006.173.09:10:56.76#ibcon#about to read 4, iclass 14, count 0 2006.173.09:10:56.76#ibcon#read 4, iclass 14, count 0 2006.173.09:10:56.76#ibcon#about to read 5, iclass 14, count 0 2006.173.09:10:56.76#ibcon#read 5, iclass 14, count 0 2006.173.09:10:56.76#ibcon#about to read 6, iclass 14, count 0 2006.173.09:10:56.76#ibcon#read 6, iclass 14, count 0 2006.173.09:10:56.76#ibcon#end of sib2, iclass 14, count 0 2006.173.09:10:56.76#ibcon#*after write, iclass 14, count 0 2006.173.09:10:56.76#ibcon#*before return 0, iclass 14, count 0 2006.173.09:10:56.76#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.09:10:56.76#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.09:10:56.76#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.09:10:56.76#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.09:10:56.76$setupk4/ifdk4 2006.173.09:10:56.76$ifdk4/lo= 2006.173.09:10:56.76$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.09:10:56.76$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.09:10:56.77$ifdk4/patch= 2006.173.09:10:56.77$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.09:10:56.77$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.09:10:56.77$setupk4/!*+20s 2006.173.09:10:57.68#abcon#<5=/15 0.4 1.0 22.99 881004.5\r\n> 2006.173.09:10:57.70#abcon#{5=INTERFACE CLEAR} 2006.173.09:10:57.76#abcon#[5=S1D000X0/0*\r\n] 2006.173.09:11:11.26$setupk4/"tpicd 2006.173.09:11:11.26$setupk4/echo=off 2006.173.09:11:11.26$setupk4/xlog=off 2006.173.09:11:11.26:!2006.173.09:14:51 2006.173.09:11:42.14#trakl#Source acquired 2006.173.09:11:43.14#flagr#flagr/antenna,acquired 2006.173.09:14:51.00:preob 2006.173.09:14:51.14/onsource/TRACKING 2006.173.09:14:51.14:!2006.173.09:15:01 2006.173.09:15:01.00:"tape 2006.173.09:15:01.00:"st=record 2006.173.09:15:01.00:data_valid=on 2006.173.09:15:01.00:midob 2006.173.09:15:01.14/onsource/TRACKING 2006.173.09:15:01.14/wx/22.98,1004.4,88 2006.173.09:15:01.33/cable/+6.5009E-03 2006.173.09:15:02.42/va/01,07,usb,yes,43,47 2006.173.09:15:02.42/va/02,06,usb,yes,43,44 2006.173.09:15:02.42/va/03,05,usb,yes,55,57 2006.173.09:15:02.42/va/04,06,usb,yes,44,47 2006.173.09:15:02.42/va/05,04,usb,yes,35,36 2006.173.09:15:02.42/va/06,03,usb,yes,48,48 2006.173.09:15:02.42/va/07,04,usb,yes,40,41 2006.173.09:15:02.42/va/08,04,usb,yes,34,40 2006.173.09:15:02.65/valo/01,524.99,yes,locked 2006.173.09:15:02.65/valo/02,534.99,yes,locked 2006.173.09:15:02.65/valo/03,564.99,yes,locked 2006.173.09:15:02.65/valo/04,624.99,yes,locked 2006.173.09:15:02.65/valo/05,734.99,yes,locked 2006.173.09:15:02.65/valo/06,814.99,yes,locked 2006.173.09:15:02.65/valo/07,864.99,yes,locked 2006.173.09:15:02.65/valo/08,884.99,yes,locked 2006.173.09:15:03.74/vb/01,04,usb,yes,33,30 2006.173.09:15:03.74/vb/02,04,usb,yes,35,35 2006.173.09:15:03.74/vb/03,04,usb,yes,32,35 2006.173.09:15:03.74/vb/04,04,usb,yes,36,35 2006.173.09:15:03.74/vb/05,04,usb,yes,29,31 2006.173.09:15:03.74/vb/06,04,usb,yes,34,29 2006.173.09:15:03.74/vb/07,04,usb,yes,33,33 2006.173.09:15:03.74/vb/08,04,usb,yes,31,34 2006.173.09:15:03.98/vblo/01,629.99,yes,locked 2006.173.09:15:03.98/vblo/02,634.99,yes,locked 2006.173.09:15:03.98/vblo/03,649.99,yes,locked 2006.173.09:15:03.98/vblo/04,679.99,yes,locked 2006.173.09:15:03.98/vblo/05,709.99,yes,locked 2006.173.09:15:03.98/vblo/06,719.99,yes,locked 2006.173.09:15:03.98/vblo/07,734.99,yes,locked 2006.173.09:15:03.98/vblo/08,744.99,yes,locked 2006.173.09:15:04.13/vabw/8 2006.173.09:15:04.28/vbbw/8 2006.173.09:15:04.37/xfe/off,on,15.2 2006.173.09:15:04.76/ifatt/23,28,28,28 2006.173.09:15:05.07/fmout-gps/S +3.98E-07 2006.173.09:15:05.11:!2006.173.09:15:41 2006.173.09:15:41.01:data_valid=off 2006.173.09:15:41.01:"et 2006.173.09:15:41.01:!+3s 2006.173.09:15:44.02:"tape 2006.173.09:15:44.02:postob 2006.173.09:15:44.21/cable/+6.5019E-03 2006.173.09:15:44.21/wx/22.98,1004.3,88 2006.173.09:15:44.27/fmout-gps/S +3.98E-07 2006.173.09:15:44.27:scan_name=173-0916,jd0606,100 2006.173.09:15:44.27:source=1334-127,133739.78,-125724.7,2000.0,cw 2006.173.09:15:46.14#flagr#flagr/antenna,new-source 2006.173.09:15:46.14:checkk5 2006.173.09:15:46.50/chk_autoobs//k5ts1/ autoobs is running! 2006.173.09:15:46.89/chk_autoobs//k5ts2/ autoobs is running! 2006.173.09:15:47.28/chk_autoobs//k5ts3/ autoobs is running! 2006.173.09:15:47.67/chk_autoobs//k5ts4/ autoobs is running! 2006.173.09:15:48.07/chk_obsdata//k5ts1/T1730915??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.09:15:48.48/chk_obsdata//k5ts2/T1730915??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.09:15:48.87/chk_obsdata//k5ts3/T1730915??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.09:15:49.29/chk_obsdata//k5ts4/T1730915??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.09:15:50.01/k5log//k5ts1_log_newline 2006.173.09:15:50.71/k5log//k5ts2_log_newline 2006.173.09:15:51.43/k5log//k5ts3_log_newline 2006.173.09:15:52.13/k5log//k5ts4_log_newline 2006.173.09:15:52.16/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.09:15:52.16:setupk4=1 2006.173.09:15:52.16$setupk4/echo=on 2006.173.09:15:52.16$setupk4/pcalon 2006.173.09:15:52.16$pcalon/"no phase cal control is implemented here 2006.173.09:15:52.16$setupk4/"tpicd=stop 2006.173.09:15:52.16$setupk4/"rec=synch_on 2006.173.09:15:52.16$setupk4/"rec_mode=128 2006.173.09:15:52.16$setupk4/!* 2006.173.09:15:52.16$setupk4/recpk4 2006.173.09:15:52.16$recpk4/recpatch= 2006.173.09:15:52.16$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.09:15:52.16$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.09:15:52.16$setupk4/vck44 2006.173.09:15:52.16$vck44/valo=1,524.99 2006.173.09:15:52.16#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.09:15:52.16#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.09:15:52.16#ibcon#ireg 17 cls_cnt 0 2006.173.09:15:52.16#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.09:15:52.16#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.09:15:52.16#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.09:15:52.16#ibcon#enter wrdev, iclass 22, count 0 2006.173.09:15:52.16#ibcon#first serial, iclass 22, count 0 2006.173.09:15:52.16#ibcon#enter sib2, iclass 22, count 0 2006.173.09:15:52.16#ibcon#flushed, iclass 22, count 0 2006.173.09:15:52.16#ibcon#about to write, iclass 22, count 0 2006.173.09:15:52.16#ibcon#wrote, iclass 22, count 0 2006.173.09:15:52.16#ibcon#about to read 3, iclass 22, count 0 2006.173.09:15:52.17#ibcon#read 3, iclass 22, count 0 2006.173.09:15:52.17#ibcon#about to read 4, iclass 22, count 0 2006.173.09:15:52.17#ibcon#read 4, iclass 22, count 0 2006.173.09:15:52.17#ibcon#about to read 5, iclass 22, count 0 2006.173.09:15:52.17#ibcon#read 5, iclass 22, count 0 2006.173.09:15:52.17#ibcon#about to read 6, iclass 22, count 0 2006.173.09:15:52.17#ibcon#read 6, iclass 22, count 0 2006.173.09:15:52.17#ibcon#end of sib2, iclass 22, count 0 2006.173.09:15:52.17#ibcon#*mode == 0, iclass 22, count 0 2006.173.09:15:52.17#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.09:15:52.17#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.09:15:52.17#ibcon#*before write, iclass 22, count 0 2006.173.09:15:52.17#ibcon#enter sib2, iclass 22, count 0 2006.173.09:15:52.17#ibcon#flushed, iclass 22, count 0 2006.173.09:15:52.17#ibcon#about to write, iclass 22, count 0 2006.173.09:15:52.17#ibcon#wrote, iclass 22, count 0 2006.173.09:15:52.17#ibcon#about to read 3, iclass 22, count 0 2006.173.09:15:52.22#ibcon#read 3, iclass 22, count 0 2006.173.09:15:52.22#ibcon#about to read 4, iclass 22, count 0 2006.173.09:15:52.22#ibcon#read 4, iclass 22, count 0 2006.173.09:15:52.22#ibcon#about to read 5, iclass 22, count 0 2006.173.09:15:52.22#ibcon#read 5, iclass 22, count 0 2006.173.09:15:52.22#ibcon#about to read 6, iclass 22, count 0 2006.173.09:15:52.22#ibcon#read 6, iclass 22, count 0 2006.173.09:15:52.22#ibcon#end of sib2, iclass 22, count 0 2006.173.09:15:52.22#ibcon#*after write, iclass 22, count 0 2006.173.09:15:52.22#ibcon#*before return 0, iclass 22, count 0 2006.173.09:15:52.22#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.09:15:52.22#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.09:15:52.22#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.09:15:52.22#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.09:15:52.22$vck44/va=1,7 2006.173.09:15:52.22#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.09:15:52.22#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.09:15:52.22#ibcon#ireg 11 cls_cnt 2 2006.173.09:15:52.22#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.09:15:52.22#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.09:15:52.22#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.09:15:52.22#ibcon#enter wrdev, iclass 24, count 2 2006.173.09:15:52.22#ibcon#first serial, iclass 24, count 2 2006.173.09:15:52.22#ibcon#enter sib2, iclass 24, count 2 2006.173.09:15:52.22#ibcon#flushed, iclass 24, count 2 2006.173.09:15:52.22#ibcon#about to write, iclass 24, count 2 2006.173.09:15:52.22#ibcon#wrote, iclass 24, count 2 2006.173.09:15:52.22#ibcon#about to read 3, iclass 24, count 2 2006.173.09:15:52.24#ibcon#read 3, iclass 24, count 2 2006.173.09:15:52.24#ibcon#about to read 4, iclass 24, count 2 2006.173.09:15:52.24#ibcon#read 4, iclass 24, count 2 2006.173.09:15:52.24#ibcon#about to read 5, iclass 24, count 2 2006.173.09:15:52.24#ibcon#read 5, iclass 24, count 2 2006.173.09:15:52.24#ibcon#about to read 6, iclass 24, count 2 2006.173.09:15:52.24#ibcon#read 6, iclass 24, count 2 2006.173.09:15:52.24#ibcon#end of sib2, iclass 24, count 2 2006.173.09:15:52.24#ibcon#*mode == 0, iclass 24, count 2 2006.173.09:15:52.24#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.09:15:52.24#ibcon#[25=AT01-07\r\n] 2006.173.09:15:52.24#ibcon#*before write, iclass 24, count 2 2006.173.09:15:52.24#ibcon#enter sib2, iclass 24, count 2 2006.173.09:15:52.24#ibcon#flushed, iclass 24, count 2 2006.173.09:15:52.24#ibcon#about to write, iclass 24, count 2 2006.173.09:15:52.24#ibcon#wrote, iclass 24, count 2 2006.173.09:15:52.24#ibcon#about to read 3, iclass 24, count 2 2006.173.09:15:52.27#ibcon#read 3, iclass 24, count 2 2006.173.09:15:52.27#ibcon#about to read 4, iclass 24, count 2 2006.173.09:15:52.27#ibcon#read 4, iclass 24, count 2 2006.173.09:15:52.27#ibcon#about to read 5, iclass 24, count 2 2006.173.09:15:52.27#ibcon#read 5, iclass 24, count 2 2006.173.09:15:52.27#ibcon#about to read 6, iclass 24, count 2 2006.173.09:15:52.27#ibcon#read 6, iclass 24, count 2 2006.173.09:15:52.27#ibcon#end of sib2, iclass 24, count 2 2006.173.09:15:52.27#ibcon#*after write, iclass 24, count 2 2006.173.09:15:52.27#ibcon#*before return 0, iclass 24, count 2 2006.173.09:15:52.27#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.09:15:52.27#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.09:15:52.27#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.09:15:52.27#ibcon#ireg 7 cls_cnt 0 2006.173.09:15:52.27#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.09:15:52.39#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.09:15:52.39#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.09:15:52.39#ibcon#enter wrdev, iclass 24, count 0 2006.173.09:15:52.39#ibcon#first serial, iclass 24, count 0 2006.173.09:15:52.39#ibcon#enter sib2, iclass 24, count 0 2006.173.09:15:52.39#ibcon#flushed, iclass 24, count 0 2006.173.09:15:52.39#ibcon#about to write, iclass 24, count 0 2006.173.09:15:52.39#ibcon#wrote, iclass 24, count 0 2006.173.09:15:52.39#ibcon#about to read 3, iclass 24, count 0 2006.173.09:15:52.41#ibcon#read 3, iclass 24, count 0 2006.173.09:15:52.41#ibcon#about to read 4, iclass 24, count 0 2006.173.09:15:52.41#ibcon#read 4, iclass 24, count 0 2006.173.09:15:52.41#ibcon#about to read 5, iclass 24, count 0 2006.173.09:15:52.41#ibcon#read 5, iclass 24, count 0 2006.173.09:15:52.41#ibcon#about to read 6, iclass 24, count 0 2006.173.09:15:52.41#ibcon#read 6, iclass 24, count 0 2006.173.09:15:52.41#ibcon#end of sib2, iclass 24, count 0 2006.173.09:15:52.41#ibcon#*mode == 0, iclass 24, count 0 2006.173.09:15:52.41#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.09:15:52.41#ibcon#[25=USB\r\n] 2006.173.09:15:52.41#ibcon#*before write, iclass 24, count 0 2006.173.09:15:52.41#ibcon#enter sib2, iclass 24, count 0 2006.173.09:15:52.41#ibcon#flushed, iclass 24, count 0 2006.173.09:15:52.41#ibcon#about to write, iclass 24, count 0 2006.173.09:15:52.41#ibcon#wrote, iclass 24, count 0 2006.173.09:15:52.41#ibcon#about to read 3, iclass 24, count 0 2006.173.09:15:52.44#ibcon#read 3, iclass 24, count 0 2006.173.09:15:52.44#ibcon#about to read 4, iclass 24, count 0 2006.173.09:15:52.44#ibcon#read 4, iclass 24, count 0 2006.173.09:15:52.44#ibcon#about to read 5, iclass 24, count 0 2006.173.09:15:52.44#ibcon#read 5, iclass 24, count 0 2006.173.09:15:52.44#ibcon#about to read 6, iclass 24, count 0 2006.173.09:15:52.44#ibcon#read 6, iclass 24, count 0 2006.173.09:15:52.44#ibcon#end of sib2, iclass 24, count 0 2006.173.09:15:52.44#ibcon#*after write, iclass 24, count 0 2006.173.09:15:52.44#ibcon#*before return 0, iclass 24, count 0 2006.173.09:15:52.44#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.09:15:52.44#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.09:15:52.44#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.09:15:52.44#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.09:15:52.44$vck44/valo=2,534.99 2006.173.09:15:52.44#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.09:15:52.44#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.09:15:52.44#ibcon#ireg 17 cls_cnt 0 2006.173.09:15:52.44#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.09:15:52.44#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.09:15:52.44#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.09:15:52.44#ibcon#enter wrdev, iclass 26, count 0 2006.173.09:15:52.44#ibcon#first serial, iclass 26, count 0 2006.173.09:15:52.44#ibcon#enter sib2, iclass 26, count 0 2006.173.09:15:52.44#ibcon#flushed, iclass 26, count 0 2006.173.09:15:52.44#ibcon#about to write, iclass 26, count 0 2006.173.09:15:52.44#ibcon#wrote, iclass 26, count 0 2006.173.09:15:52.44#ibcon#about to read 3, iclass 26, count 0 2006.173.09:15:52.46#ibcon#read 3, iclass 26, count 0 2006.173.09:15:52.46#ibcon#about to read 4, iclass 26, count 0 2006.173.09:15:52.46#ibcon#read 4, iclass 26, count 0 2006.173.09:15:52.46#ibcon#about to read 5, iclass 26, count 0 2006.173.09:15:52.46#ibcon#read 5, iclass 26, count 0 2006.173.09:15:52.46#ibcon#about to read 6, iclass 26, count 0 2006.173.09:15:52.46#ibcon#read 6, iclass 26, count 0 2006.173.09:15:52.46#ibcon#end of sib2, iclass 26, count 0 2006.173.09:15:52.46#ibcon#*mode == 0, iclass 26, count 0 2006.173.09:15:52.46#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.09:15:52.46#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.09:15:52.46#ibcon#*before write, iclass 26, count 0 2006.173.09:15:52.46#ibcon#enter sib2, iclass 26, count 0 2006.173.09:15:52.46#ibcon#flushed, iclass 26, count 0 2006.173.09:15:52.46#ibcon#about to write, iclass 26, count 0 2006.173.09:15:52.46#ibcon#wrote, iclass 26, count 0 2006.173.09:15:52.46#ibcon#about to read 3, iclass 26, count 0 2006.173.09:15:52.50#ibcon#read 3, iclass 26, count 0 2006.173.09:15:52.50#ibcon#about to read 4, iclass 26, count 0 2006.173.09:15:52.50#ibcon#read 4, iclass 26, count 0 2006.173.09:15:52.50#ibcon#about to read 5, iclass 26, count 0 2006.173.09:15:52.50#ibcon#read 5, iclass 26, count 0 2006.173.09:15:52.50#ibcon#about to read 6, iclass 26, count 0 2006.173.09:15:52.50#ibcon#read 6, iclass 26, count 0 2006.173.09:15:52.50#ibcon#end of sib2, iclass 26, count 0 2006.173.09:15:52.50#ibcon#*after write, iclass 26, count 0 2006.173.09:15:52.50#ibcon#*before return 0, iclass 26, count 0 2006.173.09:15:52.50#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.09:15:52.50#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.09:15:52.50#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.09:15:52.50#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.09:15:52.50$vck44/va=2,6 2006.173.09:15:52.50#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.09:15:52.50#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.09:15:52.50#ibcon#ireg 11 cls_cnt 2 2006.173.09:15:52.50#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.09:15:52.56#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.09:15:52.56#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.09:15:52.56#ibcon#enter wrdev, iclass 28, count 2 2006.173.09:15:52.56#ibcon#first serial, iclass 28, count 2 2006.173.09:15:52.56#ibcon#enter sib2, iclass 28, count 2 2006.173.09:15:52.56#ibcon#flushed, iclass 28, count 2 2006.173.09:15:52.56#ibcon#about to write, iclass 28, count 2 2006.173.09:15:52.56#ibcon#wrote, iclass 28, count 2 2006.173.09:15:52.56#ibcon#about to read 3, iclass 28, count 2 2006.173.09:15:52.58#ibcon#read 3, iclass 28, count 2 2006.173.09:15:52.58#ibcon#about to read 4, iclass 28, count 2 2006.173.09:15:52.58#ibcon#read 4, iclass 28, count 2 2006.173.09:15:52.58#ibcon#about to read 5, iclass 28, count 2 2006.173.09:15:52.58#ibcon#read 5, iclass 28, count 2 2006.173.09:15:52.58#ibcon#about to read 6, iclass 28, count 2 2006.173.09:15:52.58#ibcon#read 6, iclass 28, count 2 2006.173.09:15:52.58#ibcon#end of sib2, iclass 28, count 2 2006.173.09:15:52.58#ibcon#*mode == 0, iclass 28, count 2 2006.173.09:15:52.58#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.09:15:52.58#ibcon#[25=AT02-06\r\n] 2006.173.09:15:52.58#ibcon#*before write, iclass 28, count 2 2006.173.09:15:52.58#ibcon#enter sib2, iclass 28, count 2 2006.173.09:15:52.58#ibcon#flushed, iclass 28, count 2 2006.173.09:15:52.58#ibcon#about to write, iclass 28, count 2 2006.173.09:15:52.58#ibcon#wrote, iclass 28, count 2 2006.173.09:15:52.58#ibcon#about to read 3, iclass 28, count 2 2006.173.09:15:52.61#ibcon#read 3, iclass 28, count 2 2006.173.09:15:52.61#ibcon#about to read 4, iclass 28, count 2 2006.173.09:15:52.61#ibcon#read 4, iclass 28, count 2 2006.173.09:15:52.61#ibcon#about to read 5, iclass 28, count 2 2006.173.09:15:52.61#ibcon#read 5, iclass 28, count 2 2006.173.09:15:52.61#ibcon#about to read 6, iclass 28, count 2 2006.173.09:15:52.61#ibcon#read 6, iclass 28, count 2 2006.173.09:15:52.61#ibcon#end of sib2, iclass 28, count 2 2006.173.09:15:52.61#ibcon#*after write, iclass 28, count 2 2006.173.09:15:52.61#ibcon#*before return 0, iclass 28, count 2 2006.173.09:15:52.61#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.09:15:52.61#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.09:15:52.61#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.09:15:52.61#ibcon#ireg 7 cls_cnt 0 2006.173.09:15:52.61#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.09:15:52.73#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.09:15:52.73#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.09:15:52.73#ibcon#enter wrdev, iclass 28, count 0 2006.173.09:15:52.73#ibcon#first serial, iclass 28, count 0 2006.173.09:15:52.73#ibcon#enter sib2, iclass 28, count 0 2006.173.09:15:52.73#ibcon#flushed, iclass 28, count 0 2006.173.09:15:52.73#ibcon#about to write, iclass 28, count 0 2006.173.09:15:52.73#ibcon#wrote, iclass 28, count 0 2006.173.09:15:52.73#ibcon#about to read 3, iclass 28, count 0 2006.173.09:15:52.75#ibcon#read 3, iclass 28, count 0 2006.173.09:15:52.75#ibcon#about to read 4, iclass 28, count 0 2006.173.09:15:52.75#ibcon#read 4, iclass 28, count 0 2006.173.09:15:52.75#ibcon#about to read 5, iclass 28, count 0 2006.173.09:15:52.75#ibcon#read 5, iclass 28, count 0 2006.173.09:15:52.75#ibcon#about to read 6, iclass 28, count 0 2006.173.09:15:52.75#ibcon#read 6, iclass 28, count 0 2006.173.09:15:52.75#ibcon#end of sib2, iclass 28, count 0 2006.173.09:15:52.75#ibcon#*mode == 0, iclass 28, count 0 2006.173.09:15:52.75#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.09:15:52.75#ibcon#[25=USB\r\n] 2006.173.09:15:52.75#ibcon#*before write, iclass 28, count 0 2006.173.09:15:52.75#ibcon#enter sib2, iclass 28, count 0 2006.173.09:15:52.75#ibcon#flushed, iclass 28, count 0 2006.173.09:15:52.75#ibcon#about to write, iclass 28, count 0 2006.173.09:15:52.75#ibcon#wrote, iclass 28, count 0 2006.173.09:15:52.75#ibcon#about to read 3, iclass 28, count 0 2006.173.09:15:52.78#ibcon#read 3, iclass 28, count 0 2006.173.09:15:52.78#ibcon#about to read 4, iclass 28, count 0 2006.173.09:15:52.78#ibcon#read 4, iclass 28, count 0 2006.173.09:15:52.78#ibcon#about to read 5, iclass 28, count 0 2006.173.09:15:52.78#ibcon#read 5, iclass 28, count 0 2006.173.09:15:52.78#ibcon#about to read 6, iclass 28, count 0 2006.173.09:15:52.78#ibcon#read 6, iclass 28, count 0 2006.173.09:15:52.78#ibcon#end of sib2, iclass 28, count 0 2006.173.09:15:52.78#ibcon#*after write, iclass 28, count 0 2006.173.09:15:52.78#ibcon#*before return 0, iclass 28, count 0 2006.173.09:15:52.78#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.09:15:52.78#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.09:15:52.78#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.09:15:52.78#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.09:15:52.78$vck44/valo=3,564.99 2006.173.09:15:52.78#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.09:15:52.78#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.09:15:52.78#ibcon#ireg 17 cls_cnt 0 2006.173.09:15:52.78#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.09:15:52.78#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.09:15:52.78#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.09:15:52.78#ibcon#enter wrdev, iclass 30, count 0 2006.173.09:15:52.78#ibcon#first serial, iclass 30, count 0 2006.173.09:15:52.78#ibcon#enter sib2, iclass 30, count 0 2006.173.09:15:52.78#ibcon#flushed, iclass 30, count 0 2006.173.09:15:52.78#ibcon#about to write, iclass 30, count 0 2006.173.09:15:52.78#ibcon#wrote, iclass 30, count 0 2006.173.09:15:52.78#ibcon#about to read 3, iclass 30, count 0 2006.173.09:15:52.80#ibcon#read 3, iclass 30, count 0 2006.173.09:15:52.80#ibcon#about to read 4, iclass 30, count 0 2006.173.09:15:52.80#ibcon#read 4, iclass 30, count 0 2006.173.09:15:52.80#ibcon#about to read 5, iclass 30, count 0 2006.173.09:15:52.80#ibcon#read 5, iclass 30, count 0 2006.173.09:15:52.80#ibcon#about to read 6, iclass 30, count 0 2006.173.09:15:52.80#ibcon#read 6, iclass 30, count 0 2006.173.09:15:52.80#ibcon#end of sib2, iclass 30, count 0 2006.173.09:15:52.80#ibcon#*mode == 0, iclass 30, count 0 2006.173.09:15:52.80#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.09:15:52.80#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.09:15:52.80#ibcon#*before write, iclass 30, count 0 2006.173.09:15:52.80#ibcon#enter sib2, iclass 30, count 0 2006.173.09:15:52.80#ibcon#flushed, iclass 30, count 0 2006.173.09:15:52.80#ibcon#about to write, iclass 30, count 0 2006.173.09:15:52.80#ibcon#wrote, iclass 30, count 0 2006.173.09:15:52.80#ibcon#about to read 3, iclass 30, count 0 2006.173.09:15:52.84#ibcon#read 3, iclass 30, count 0 2006.173.09:15:52.84#ibcon#about to read 4, iclass 30, count 0 2006.173.09:15:52.84#ibcon#read 4, iclass 30, count 0 2006.173.09:15:52.84#ibcon#about to read 5, iclass 30, count 0 2006.173.09:15:52.84#ibcon#read 5, iclass 30, count 0 2006.173.09:15:52.84#ibcon#about to read 6, iclass 30, count 0 2006.173.09:15:52.84#ibcon#read 6, iclass 30, count 0 2006.173.09:15:52.84#ibcon#end of sib2, iclass 30, count 0 2006.173.09:15:52.84#ibcon#*after write, iclass 30, count 0 2006.173.09:15:52.84#ibcon#*before return 0, iclass 30, count 0 2006.173.09:15:52.84#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.09:15:52.84#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.09:15:52.84#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.09:15:52.84#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.09:15:52.84$vck44/va=3,5 2006.173.09:15:52.84#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.173.09:15:52.84#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.173.09:15:52.84#ibcon#ireg 11 cls_cnt 2 2006.173.09:15:52.84#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.09:15:52.90#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.09:15:52.90#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.09:15:52.90#ibcon#enter wrdev, iclass 32, count 2 2006.173.09:15:52.90#ibcon#first serial, iclass 32, count 2 2006.173.09:15:52.90#ibcon#enter sib2, iclass 32, count 2 2006.173.09:15:52.90#ibcon#flushed, iclass 32, count 2 2006.173.09:15:52.90#ibcon#about to write, iclass 32, count 2 2006.173.09:15:52.90#ibcon#wrote, iclass 32, count 2 2006.173.09:15:52.90#ibcon#about to read 3, iclass 32, count 2 2006.173.09:15:52.92#ibcon#read 3, iclass 32, count 2 2006.173.09:15:52.92#ibcon#about to read 4, iclass 32, count 2 2006.173.09:15:52.92#ibcon#read 4, iclass 32, count 2 2006.173.09:15:52.92#ibcon#about to read 5, iclass 32, count 2 2006.173.09:15:52.92#ibcon#read 5, iclass 32, count 2 2006.173.09:15:52.92#ibcon#about to read 6, iclass 32, count 2 2006.173.09:15:52.92#ibcon#read 6, iclass 32, count 2 2006.173.09:15:52.92#ibcon#end of sib2, iclass 32, count 2 2006.173.09:15:52.92#ibcon#*mode == 0, iclass 32, count 2 2006.173.09:15:52.92#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.173.09:15:52.92#ibcon#[25=AT03-05\r\n] 2006.173.09:15:52.92#ibcon#*before write, iclass 32, count 2 2006.173.09:15:52.92#ibcon#enter sib2, iclass 32, count 2 2006.173.09:15:52.92#ibcon#flushed, iclass 32, count 2 2006.173.09:15:52.92#ibcon#about to write, iclass 32, count 2 2006.173.09:15:52.92#ibcon#wrote, iclass 32, count 2 2006.173.09:15:52.92#ibcon#about to read 3, iclass 32, count 2 2006.173.09:15:52.95#ibcon#read 3, iclass 32, count 2 2006.173.09:15:52.95#ibcon#about to read 4, iclass 32, count 2 2006.173.09:15:52.95#ibcon#read 4, iclass 32, count 2 2006.173.09:15:52.95#ibcon#about to read 5, iclass 32, count 2 2006.173.09:15:52.95#ibcon#read 5, iclass 32, count 2 2006.173.09:15:52.95#ibcon#about to read 6, iclass 32, count 2 2006.173.09:15:52.95#ibcon#read 6, iclass 32, count 2 2006.173.09:15:52.95#ibcon#end of sib2, iclass 32, count 2 2006.173.09:15:52.95#ibcon#*after write, iclass 32, count 2 2006.173.09:15:52.95#ibcon#*before return 0, iclass 32, count 2 2006.173.09:15:52.95#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.09:15:52.95#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.173.09:15:52.95#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.173.09:15:52.95#ibcon#ireg 7 cls_cnt 0 2006.173.09:15:52.95#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.09:15:53.07#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.09:15:53.07#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.09:15:53.07#ibcon#enter wrdev, iclass 32, count 0 2006.173.09:15:53.07#ibcon#first serial, iclass 32, count 0 2006.173.09:15:53.07#ibcon#enter sib2, iclass 32, count 0 2006.173.09:15:53.07#ibcon#flushed, iclass 32, count 0 2006.173.09:15:53.07#ibcon#about to write, iclass 32, count 0 2006.173.09:15:53.07#ibcon#wrote, iclass 32, count 0 2006.173.09:15:53.07#ibcon#about to read 3, iclass 32, count 0 2006.173.09:15:53.09#ibcon#read 3, iclass 32, count 0 2006.173.09:15:53.09#ibcon#about to read 4, iclass 32, count 0 2006.173.09:15:53.09#ibcon#read 4, iclass 32, count 0 2006.173.09:15:53.09#ibcon#about to read 5, iclass 32, count 0 2006.173.09:15:53.09#ibcon#read 5, iclass 32, count 0 2006.173.09:15:53.09#ibcon#about to read 6, iclass 32, count 0 2006.173.09:15:53.09#ibcon#read 6, iclass 32, count 0 2006.173.09:15:53.09#ibcon#end of sib2, iclass 32, count 0 2006.173.09:15:53.09#ibcon#*mode == 0, iclass 32, count 0 2006.173.09:15:53.09#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.09:15:53.09#ibcon#[25=USB\r\n] 2006.173.09:15:53.09#ibcon#*before write, iclass 32, count 0 2006.173.09:15:53.09#ibcon#enter sib2, iclass 32, count 0 2006.173.09:15:53.09#ibcon#flushed, iclass 32, count 0 2006.173.09:15:53.09#ibcon#about to write, iclass 32, count 0 2006.173.09:15:53.09#ibcon#wrote, iclass 32, count 0 2006.173.09:15:53.09#ibcon#about to read 3, iclass 32, count 0 2006.173.09:15:53.12#ibcon#read 3, iclass 32, count 0 2006.173.09:15:53.12#ibcon#about to read 4, iclass 32, count 0 2006.173.09:15:53.12#ibcon#read 4, iclass 32, count 0 2006.173.09:15:53.12#ibcon#about to read 5, iclass 32, count 0 2006.173.09:15:53.12#ibcon#read 5, iclass 32, count 0 2006.173.09:15:53.12#ibcon#about to read 6, iclass 32, count 0 2006.173.09:15:53.12#ibcon#read 6, iclass 32, count 0 2006.173.09:15:53.12#ibcon#end of sib2, iclass 32, count 0 2006.173.09:15:53.12#ibcon#*after write, iclass 32, count 0 2006.173.09:15:53.12#ibcon#*before return 0, iclass 32, count 0 2006.173.09:15:53.12#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.09:15:53.12#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.173.09:15:53.12#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.09:15:53.12#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.09:15:53.12$vck44/valo=4,624.99 2006.173.09:15:53.12#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.09:15:53.12#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.09:15:53.12#ibcon#ireg 17 cls_cnt 0 2006.173.09:15:53.12#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.09:15:53.12#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.09:15:53.12#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.09:15:53.12#ibcon#enter wrdev, iclass 34, count 0 2006.173.09:15:53.12#ibcon#first serial, iclass 34, count 0 2006.173.09:15:53.12#ibcon#enter sib2, iclass 34, count 0 2006.173.09:15:53.12#ibcon#flushed, iclass 34, count 0 2006.173.09:15:53.12#ibcon#about to write, iclass 34, count 0 2006.173.09:15:53.12#ibcon#wrote, iclass 34, count 0 2006.173.09:15:53.12#ibcon#about to read 3, iclass 34, count 0 2006.173.09:15:53.14#ibcon#read 3, iclass 34, count 0 2006.173.09:15:53.14#ibcon#about to read 4, iclass 34, count 0 2006.173.09:15:53.14#ibcon#read 4, iclass 34, count 0 2006.173.09:15:53.14#ibcon#about to read 5, iclass 34, count 0 2006.173.09:15:53.14#ibcon#read 5, iclass 34, count 0 2006.173.09:15:53.14#ibcon#about to read 6, iclass 34, count 0 2006.173.09:15:53.14#ibcon#read 6, iclass 34, count 0 2006.173.09:15:53.14#ibcon#end of sib2, iclass 34, count 0 2006.173.09:15:53.14#ibcon#*mode == 0, iclass 34, count 0 2006.173.09:15:53.14#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.09:15:53.14#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.09:15:53.14#ibcon#*before write, iclass 34, count 0 2006.173.09:15:53.14#ibcon#enter sib2, iclass 34, count 0 2006.173.09:15:53.14#ibcon#flushed, iclass 34, count 0 2006.173.09:15:53.14#ibcon#about to write, iclass 34, count 0 2006.173.09:15:53.14#ibcon#wrote, iclass 34, count 0 2006.173.09:15:53.14#ibcon#about to read 3, iclass 34, count 0 2006.173.09:15:53.18#ibcon#read 3, iclass 34, count 0 2006.173.09:15:53.18#ibcon#about to read 4, iclass 34, count 0 2006.173.09:15:53.18#ibcon#read 4, iclass 34, count 0 2006.173.09:15:53.18#ibcon#about to read 5, iclass 34, count 0 2006.173.09:15:53.18#ibcon#read 5, iclass 34, count 0 2006.173.09:15:53.18#ibcon#about to read 6, iclass 34, count 0 2006.173.09:15:53.18#ibcon#read 6, iclass 34, count 0 2006.173.09:15:53.18#ibcon#end of sib2, iclass 34, count 0 2006.173.09:15:53.18#ibcon#*after write, iclass 34, count 0 2006.173.09:15:53.18#ibcon#*before return 0, iclass 34, count 0 2006.173.09:15:53.18#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.09:15:53.18#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.09:15:53.18#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.09:15:53.18#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.09:15:53.18$vck44/va=4,6 2006.173.09:15:53.18#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.09:15:53.18#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.09:15:53.18#ibcon#ireg 11 cls_cnt 2 2006.173.09:15:53.18#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.09:15:53.24#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.09:15:53.24#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.09:15:53.24#ibcon#enter wrdev, iclass 36, count 2 2006.173.09:15:53.24#ibcon#first serial, iclass 36, count 2 2006.173.09:15:53.24#ibcon#enter sib2, iclass 36, count 2 2006.173.09:15:53.24#ibcon#flushed, iclass 36, count 2 2006.173.09:15:53.24#ibcon#about to write, iclass 36, count 2 2006.173.09:15:53.24#ibcon#wrote, iclass 36, count 2 2006.173.09:15:53.24#ibcon#about to read 3, iclass 36, count 2 2006.173.09:15:53.26#ibcon#read 3, iclass 36, count 2 2006.173.09:15:53.26#ibcon#about to read 4, iclass 36, count 2 2006.173.09:15:53.26#ibcon#read 4, iclass 36, count 2 2006.173.09:15:53.26#ibcon#about to read 5, iclass 36, count 2 2006.173.09:15:53.26#ibcon#read 5, iclass 36, count 2 2006.173.09:15:53.26#ibcon#about to read 6, iclass 36, count 2 2006.173.09:15:53.26#ibcon#read 6, iclass 36, count 2 2006.173.09:15:53.26#ibcon#end of sib2, iclass 36, count 2 2006.173.09:15:53.26#ibcon#*mode == 0, iclass 36, count 2 2006.173.09:15:53.26#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.09:15:53.26#ibcon#[25=AT04-06\r\n] 2006.173.09:15:53.26#ibcon#*before write, iclass 36, count 2 2006.173.09:15:53.26#ibcon#enter sib2, iclass 36, count 2 2006.173.09:15:53.26#ibcon#flushed, iclass 36, count 2 2006.173.09:15:53.26#ibcon#about to write, iclass 36, count 2 2006.173.09:15:53.26#ibcon#wrote, iclass 36, count 2 2006.173.09:15:53.26#ibcon#about to read 3, iclass 36, count 2 2006.173.09:15:53.29#ibcon#read 3, iclass 36, count 2 2006.173.09:15:53.29#ibcon#about to read 4, iclass 36, count 2 2006.173.09:15:53.29#ibcon#read 4, iclass 36, count 2 2006.173.09:15:53.29#ibcon#about to read 5, iclass 36, count 2 2006.173.09:15:53.29#ibcon#read 5, iclass 36, count 2 2006.173.09:15:53.29#ibcon#about to read 6, iclass 36, count 2 2006.173.09:15:53.29#ibcon#read 6, iclass 36, count 2 2006.173.09:15:53.29#ibcon#end of sib2, iclass 36, count 2 2006.173.09:15:53.29#ibcon#*after write, iclass 36, count 2 2006.173.09:15:53.29#ibcon#*before return 0, iclass 36, count 2 2006.173.09:15:53.29#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.09:15:53.29#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.09:15:53.29#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.09:15:53.29#ibcon#ireg 7 cls_cnt 0 2006.173.09:15:53.29#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.09:15:53.41#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.09:15:53.41#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.09:15:53.41#ibcon#enter wrdev, iclass 36, count 0 2006.173.09:15:53.41#ibcon#first serial, iclass 36, count 0 2006.173.09:15:53.41#ibcon#enter sib2, iclass 36, count 0 2006.173.09:15:53.41#ibcon#flushed, iclass 36, count 0 2006.173.09:15:53.41#ibcon#about to write, iclass 36, count 0 2006.173.09:15:53.41#ibcon#wrote, iclass 36, count 0 2006.173.09:15:53.41#ibcon#about to read 3, iclass 36, count 0 2006.173.09:15:53.43#ibcon#read 3, iclass 36, count 0 2006.173.09:15:53.43#ibcon#about to read 4, iclass 36, count 0 2006.173.09:15:53.43#ibcon#read 4, iclass 36, count 0 2006.173.09:15:53.43#ibcon#about to read 5, iclass 36, count 0 2006.173.09:15:53.43#ibcon#read 5, iclass 36, count 0 2006.173.09:15:53.43#ibcon#about to read 6, iclass 36, count 0 2006.173.09:15:53.43#ibcon#read 6, iclass 36, count 0 2006.173.09:15:53.43#ibcon#end of sib2, iclass 36, count 0 2006.173.09:15:53.43#ibcon#*mode == 0, iclass 36, count 0 2006.173.09:15:53.43#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.09:15:53.43#ibcon#[25=USB\r\n] 2006.173.09:15:53.43#ibcon#*before write, iclass 36, count 0 2006.173.09:15:53.43#ibcon#enter sib2, iclass 36, count 0 2006.173.09:15:53.43#ibcon#flushed, iclass 36, count 0 2006.173.09:15:53.43#ibcon#about to write, iclass 36, count 0 2006.173.09:15:53.43#ibcon#wrote, iclass 36, count 0 2006.173.09:15:53.43#ibcon#about to read 3, iclass 36, count 0 2006.173.09:15:53.46#ibcon#read 3, iclass 36, count 0 2006.173.09:15:53.46#ibcon#about to read 4, iclass 36, count 0 2006.173.09:15:53.46#ibcon#read 4, iclass 36, count 0 2006.173.09:15:53.46#ibcon#about to read 5, iclass 36, count 0 2006.173.09:15:53.46#ibcon#read 5, iclass 36, count 0 2006.173.09:15:53.46#ibcon#about to read 6, iclass 36, count 0 2006.173.09:15:53.46#ibcon#read 6, iclass 36, count 0 2006.173.09:15:53.46#ibcon#end of sib2, iclass 36, count 0 2006.173.09:15:53.46#ibcon#*after write, iclass 36, count 0 2006.173.09:15:53.46#ibcon#*before return 0, iclass 36, count 0 2006.173.09:15:53.46#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.09:15:53.46#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.09:15:53.46#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.09:15:53.46#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.09:15:53.46$vck44/valo=5,734.99 2006.173.09:15:53.46#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.09:15:53.46#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.09:15:53.46#ibcon#ireg 17 cls_cnt 0 2006.173.09:15:53.46#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.09:15:53.46#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.09:15:53.46#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.09:15:53.46#ibcon#enter wrdev, iclass 38, count 0 2006.173.09:15:53.46#ibcon#first serial, iclass 38, count 0 2006.173.09:15:53.46#ibcon#enter sib2, iclass 38, count 0 2006.173.09:15:53.46#ibcon#flushed, iclass 38, count 0 2006.173.09:15:53.46#ibcon#about to write, iclass 38, count 0 2006.173.09:15:53.46#ibcon#wrote, iclass 38, count 0 2006.173.09:15:53.46#ibcon#about to read 3, iclass 38, count 0 2006.173.09:15:53.48#ibcon#read 3, iclass 38, count 0 2006.173.09:15:53.48#ibcon#about to read 4, iclass 38, count 0 2006.173.09:15:53.48#ibcon#read 4, iclass 38, count 0 2006.173.09:15:53.48#ibcon#about to read 5, iclass 38, count 0 2006.173.09:15:53.48#ibcon#read 5, iclass 38, count 0 2006.173.09:15:53.48#ibcon#about to read 6, iclass 38, count 0 2006.173.09:15:53.48#ibcon#read 6, iclass 38, count 0 2006.173.09:15:53.48#ibcon#end of sib2, iclass 38, count 0 2006.173.09:15:53.48#ibcon#*mode == 0, iclass 38, count 0 2006.173.09:15:53.48#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.09:15:53.48#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.09:15:53.48#ibcon#*before write, iclass 38, count 0 2006.173.09:15:53.48#ibcon#enter sib2, iclass 38, count 0 2006.173.09:15:53.48#ibcon#flushed, iclass 38, count 0 2006.173.09:15:53.48#ibcon#about to write, iclass 38, count 0 2006.173.09:15:53.48#ibcon#wrote, iclass 38, count 0 2006.173.09:15:53.48#ibcon#about to read 3, iclass 38, count 0 2006.173.09:15:53.52#ibcon#read 3, iclass 38, count 0 2006.173.09:15:53.52#ibcon#about to read 4, iclass 38, count 0 2006.173.09:15:53.52#ibcon#read 4, iclass 38, count 0 2006.173.09:15:53.52#ibcon#about to read 5, iclass 38, count 0 2006.173.09:15:53.52#ibcon#read 5, iclass 38, count 0 2006.173.09:15:53.52#ibcon#about to read 6, iclass 38, count 0 2006.173.09:15:53.52#ibcon#read 6, iclass 38, count 0 2006.173.09:15:53.52#ibcon#end of sib2, iclass 38, count 0 2006.173.09:15:53.52#ibcon#*after write, iclass 38, count 0 2006.173.09:15:53.52#ibcon#*before return 0, iclass 38, count 0 2006.173.09:15:53.52#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.09:15:53.52#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.09:15:53.52#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.09:15:53.52#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.09:15:53.52$vck44/va=5,4 2006.173.09:15:53.52#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.09:15:53.52#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.09:15:53.52#ibcon#ireg 11 cls_cnt 2 2006.173.09:15:53.52#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.09:15:53.58#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.09:15:53.58#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.09:15:53.58#ibcon#enter wrdev, iclass 40, count 2 2006.173.09:15:53.58#ibcon#first serial, iclass 40, count 2 2006.173.09:15:53.58#ibcon#enter sib2, iclass 40, count 2 2006.173.09:15:53.58#ibcon#flushed, iclass 40, count 2 2006.173.09:15:53.58#ibcon#about to write, iclass 40, count 2 2006.173.09:15:53.58#ibcon#wrote, iclass 40, count 2 2006.173.09:15:53.58#ibcon#about to read 3, iclass 40, count 2 2006.173.09:15:53.60#ibcon#read 3, iclass 40, count 2 2006.173.09:15:53.60#ibcon#about to read 4, iclass 40, count 2 2006.173.09:15:53.60#ibcon#read 4, iclass 40, count 2 2006.173.09:15:53.60#ibcon#about to read 5, iclass 40, count 2 2006.173.09:15:53.60#ibcon#read 5, iclass 40, count 2 2006.173.09:15:53.60#ibcon#about to read 6, iclass 40, count 2 2006.173.09:15:53.60#ibcon#read 6, iclass 40, count 2 2006.173.09:15:53.60#ibcon#end of sib2, iclass 40, count 2 2006.173.09:15:53.60#ibcon#*mode == 0, iclass 40, count 2 2006.173.09:15:53.60#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.09:15:53.60#ibcon#[25=AT05-04\r\n] 2006.173.09:15:53.60#ibcon#*before write, iclass 40, count 2 2006.173.09:15:53.60#ibcon#enter sib2, iclass 40, count 2 2006.173.09:15:53.60#ibcon#flushed, iclass 40, count 2 2006.173.09:15:53.60#ibcon#about to write, iclass 40, count 2 2006.173.09:15:53.60#ibcon#wrote, iclass 40, count 2 2006.173.09:15:53.60#ibcon#about to read 3, iclass 40, count 2 2006.173.09:15:53.63#ibcon#read 3, iclass 40, count 2 2006.173.09:15:53.63#ibcon#about to read 4, iclass 40, count 2 2006.173.09:15:53.63#ibcon#read 4, iclass 40, count 2 2006.173.09:15:53.63#ibcon#about to read 5, iclass 40, count 2 2006.173.09:15:53.63#ibcon#read 5, iclass 40, count 2 2006.173.09:15:53.63#ibcon#about to read 6, iclass 40, count 2 2006.173.09:15:53.63#ibcon#read 6, iclass 40, count 2 2006.173.09:15:53.63#ibcon#end of sib2, iclass 40, count 2 2006.173.09:15:53.63#ibcon#*after write, iclass 40, count 2 2006.173.09:15:53.63#ibcon#*before return 0, iclass 40, count 2 2006.173.09:15:53.63#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.09:15:53.63#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.09:15:53.63#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.09:15:53.63#ibcon#ireg 7 cls_cnt 0 2006.173.09:15:53.63#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.09:15:53.75#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.09:15:53.75#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.09:15:53.75#ibcon#enter wrdev, iclass 40, count 0 2006.173.09:15:53.75#ibcon#first serial, iclass 40, count 0 2006.173.09:15:53.75#ibcon#enter sib2, iclass 40, count 0 2006.173.09:15:53.75#ibcon#flushed, iclass 40, count 0 2006.173.09:15:53.75#ibcon#about to write, iclass 40, count 0 2006.173.09:15:53.75#ibcon#wrote, iclass 40, count 0 2006.173.09:15:53.75#ibcon#about to read 3, iclass 40, count 0 2006.173.09:15:53.77#ibcon#read 3, iclass 40, count 0 2006.173.09:15:53.77#ibcon#about to read 4, iclass 40, count 0 2006.173.09:15:53.77#ibcon#read 4, iclass 40, count 0 2006.173.09:15:53.77#ibcon#about to read 5, iclass 40, count 0 2006.173.09:15:53.77#ibcon#read 5, iclass 40, count 0 2006.173.09:15:53.77#ibcon#about to read 6, iclass 40, count 0 2006.173.09:15:53.77#ibcon#read 6, iclass 40, count 0 2006.173.09:15:53.77#ibcon#end of sib2, iclass 40, count 0 2006.173.09:15:53.77#ibcon#*mode == 0, iclass 40, count 0 2006.173.09:15:53.77#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.09:15:53.77#ibcon#[25=USB\r\n] 2006.173.09:15:53.77#ibcon#*before write, iclass 40, count 0 2006.173.09:15:53.77#ibcon#enter sib2, iclass 40, count 0 2006.173.09:15:53.77#ibcon#flushed, iclass 40, count 0 2006.173.09:15:53.77#ibcon#about to write, iclass 40, count 0 2006.173.09:15:53.77#ibcon#wrote, iclass 40, count 0 2006.173.09:15:53.77#ibcon#about to read 3, iclass 40, count 0 2006.173.09:15:53.80#ibcon#read 3, iclass 40, count 0 2006.173.09:15:53.80#ibcon#about to read 4, iclass 40, count 0 2006.173.09:15:53.80#ibcon#read 4, iclass 40, count 0 2006.173.09:15:53.80#ibcon#about to read 5, iclass 40, count 0 2006.173.09:15:53.80#ibcon#read 5, iclass 40, count 0 2006.173.09:15:53.80#ibcon#about to read 6, iclass 40, count 0 2006.173.09:15:53.80#ibcon#read 6, iclass 40, count 0 2006.173.09:15:53.80#ibcon#end of sib2, iclass 40, count 0 2006.173.09:15:53.80#ibcon#*after write, iclass 40, count 0 2006.173.09:15:53.80#ibcon#*before return 0, iclass 40, count 0 2006.173.09:15:53.80#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.09:15:53.80#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.09:15:53.80#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.09:15:53.80#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.09:15:53.80$vck44/valo=6,814.99 2006.173.09:15:53.80#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.09:15:53.80#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.09:15:53.80#ibcon#ireg 17 cls_cnt 0 2006.173.09:15:53.80#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.09:15:53.80#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.09:15:53.80#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.09:15:53.80#ibcon#enter wrdev, iclass 4, count 0 2006.173.09:15:53.80#ibcon#first serial, iclass 4, count 0 2006.173.09:15:53.80#ibcon#enter sib2, iclass 4, count 0 2006.173.09:15:53.80#ibcon#flushed, iclass 4, count 0 2006.173.09:15:53.80#ibcon#about to write, iclass 4, count 0 2006.173.09:15:53.80#ibcon#wrote, iclass 4, count 0 2006.173.09:15:53.80#ibcon#about to read 3, iclass 4, count 0 2006.173.09:15:53.82#ibcon#read 3, iclass 4, count 0 2006.173.09:15:53.82#ibcon#about to read 4, iclass 4, count 0 2006.173.09:15:53.82#ibcon#read 4, iclass 4, count 0 2006.173.09:15:53.82#ibcon#about to read 5, iclass 4, count 0 2006.173.09:15:53.82#ibcon#read 5, iclass 4, count 0 2006.173.09:15:53.82#ibcon#about to read 6, iclass 4, count 0 2006.173.09:15:53.82#ibcon#read 6, iclass 4, count 0 2006.173.09:15:53.82#ibcon#end of sib2, iclass 4, count 0 2006.173.09:15:53.82#ibcon#*mode == 0, iclass 4, count 0 2006.173.09:15:53.82#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.09:15:53.82#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.09:15:53.82#ibcon#*before write, iclass 4, count 0 2006.173.09:15:53.82#ibcon#enter sib2, iclass 4, count 0 2006.173.09:15:53.82#ibcon#flushed, iclass 4, count 0 2006.173.09:15:53.82#ibcon#about to write, iclass 4, count 0 2006.173.09:15:53.82#ibcon#wrote, iclass 4, count 0 2006.173.09:15:53.82#ibcon#about to read 3, iclass 4, count 0 2006.173.09:15:53.86#ibcon#read 3, iclass 4, count 0 2006.173.09:15:53.86#ibcon#about to read 4, iclass 4, count 0 2006.173.09:15:53.86#ibcon#read 4, iclass 4, count 0 2006.173.09:15:53.86#ibcon#about to read 5, iclass 4, count 0 2006.173.09:15:53.86#ibcon#read 5, iclass 4, count 0 2006.173.09:15:53.86#ibcon#about to read 6, iclass 4, count 0 2006.173.09:15:53.86#ibcon#read 6, iclass 4, count 0 2006.173.09:15:53.86#ibcon#end of sib2, iclass 4, count 0 2006.173.09:15:53.86#ibcon#*after write, iclass 4, count 0 2006.173.09:15:53.86#ibcon#*before return 0, iclass 4, count 0 2006.173.09:15:53.86#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.09:15:53.86#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.09:15:53.86#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.09:15:53.86#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.09:15:53.86$vck44/va=6,3 2006.173.09:15:53.86#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.09:15:53.86#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.09:15:53.86#ibcon#ireg 11 cls_cnt 2 2006.173.09:15:53.86#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.09:15:53.92#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.09:15:53.92#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.09:15:53.92#ibcon#enter wrdev, iclass 6, count 2 2006.173.09:15:53.92#ibcon#first serial, iclass 6, count 2 2006.173.09:15:53.92#ibcon#enter sib2, iclass 6, count 2 2006.173.09:15:53.92#ibcon#flushed, iclass 6, count 2 2006.173.09:15:53.92#ibcon#about to write, iclass 6, count 2 2006.173.09:15:53.92#ibcon#wrote, iclass 6, count 2 2006.173.09:15:53.92#ibcon#about to read 3, iclass 6, count 2 2006.173.09:15:53.94#ibcon#read 3, iclass 6, count 2 2006.173.09:15:53.94#ibcon#about to read 4, iclass 6, count 2 2006.173.09:15:53.94#ibcon#read 4, iclass 6, count 2 2006.173.09:15:53.94#ibcon#about to read 5, iclass 6, count 2 2006.173.09:15:53.94#ibcon#read 5, iclass 6, count 2 2006.173.09:15:53.94#ibcon#about to read 6, iclass 6, count 2 2006.173.09:15:53.94#ibcon#read 6, iclass 6, count 2 2006.173.09:15:53.94#ibcon#end of sib2, iclass 6, count 2 2006.173.09:15:53.94#ibcon#*mode == 0, iclass 6, count 2 2006.173.09:15:53.94#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.09:15:53.94#ibcon#[25=AT06-03\r\n] 2006.173.09:15:53.94#ibcon#*before write, iclass 6, count 2 2006.173.09:15:53.94#ibcon#enter sib2, iclass 6, count 2 2006.173.09:15:53.94#ibcon#flushed, iclass 6, count 2 2006.173.09:15:53.94#ibcon#about to write, iclass 6, count 2 2006.173.09:15:53.94#ibcon#wrote, iclass 6, count 2 2006.173.09:15:53.94#ibcon#about to read 3, iclass 6, count 2 2006.173.09:15:53.97#ibcon#read 3, iclass 6, count 2 2006.173.09:15:53.97#ibcon#about to read 4, iclass 6, count 2 2006.173.09:15:53.97#ibcon#read 4, iclass 6, count 2 2006.173.09:15:53.97#ibcon#about to read 5, iclass 6, count 2 2006.173.09:15:53.97#ibcon#read 5, iclass 6, count 2 2006.173.09:15:53.97#ibcon#about to read 6, iclass 6, count 2 2006.173.09:15:53.97#ibcon#read 6, iclass 6, count 2 2006.173.09:15:53.97#ibcon#end of sib2, iclass 6, count 2 2006.173.09:15:53.97#ibcon#*after write, iclass 6, count 2 2006.173.09:15:53.97#ibcon#*before return 0, iclass 6, count 2 2006.173.09:15:53.97#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.09:15:53.97#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.09:15:53.97#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.09:15:53.97#ibcon#ireg 7 cls_cnt 0 2006.173.09:15:53.97#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.09:15:54.09#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.09:15:54.09#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.09:15:54.09#ibcon#enter wrdev, iclass 6, count 0 2006.173.09:15:54.09#ibcon#first serial, iclass 6, count 0 2006.173.09:15:54.09#ibcon#enter sib2, iclass 6, count 0 2006.173.09:15:54.09#ibcon#flushed, iclass 6, count 0 2006.173.09:15:54.09#ibcon#about to write, iclass 6, count 0 2006.173.09:15:54.09#ibcon#wrote, iclass 6, count 0 2006.173.09:15:54.09#ibcon#about to read 3, iclass 6, count 0 2006.173.09:15:54.11#ibcon#read 3, iclass 6, count 0 2006.173.09:15:54.11#ibcon#about to read 4, iclass 6, count 0 2006.173.09:15:54.11#ibcon#read 4, iclass 6, count 0 2006.173.09:15:54.11#ibcon#about to read 5, iclass 6, count 0 2006.173.09:15:54.11#ibcon#read 5, iclass 6, count 0 2006.173.09:15:54.11#ibcon#about to read 6, iclass 6, count 0 2006.173.09:15:54.11#ibcon#read 6, iclass 6, count 0 2006.173.09:15:54.11#ibcon#end of sib2, iclass 6, count 0 2006.173.09:15:54.11#ibcon#*mode == 0, iclass 6, count 0 2006.173.09:15:54.11#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.09:15:54.11#ibcon#[25=USB\r\n] 2006.173.09:15:54.11#ibcon#*before write, iclass 6, count 0 2006.173.09:15:54.11#ibcon#enter sib2, iclass 6, count 0 2006.173.09:15:54.11#ibcon#flushed, iclass 6, count 0 2006.173.09:15:54.11#ibcon#about to write, iclass 6, count 0 2006.173.09:15:54.11#ibcon#wrote, iclass 6, count 0 2006.173.09:15:54.11#ibcon#about to read 3, iclass 6, count 0 2006.173.09:15:54.14#ibcon#read 3, iclass 6, count 0 2006.173.09:15:54.14#ibcon#about to read 4, iclass 6, count 0 2006.173.09:15:54.14#ibcon#read 4, iclass 6, count 0 2006.173.09:15:54.14#ibcon#about to read 5, iclass 6, count 0 2006.173.09:15:54.14#ibcon#read 5, iclass 6, count 0 2006.173.09:15:54.14#ibcon#about to read 6, iclass 6, count 0 2006.173.09:15:54.14#ibcon#read 6, iclass 6, count 0 2006.173.09:15:54.14#ibcon#end of sib2, iclass 6, count 0 2006.173.09:15:54.14#ibcon#*after write, iclass 6, count 0 2006.173.09:15:54.14#ibcon#*before return 0, iclass 6, count 0 2006.173.09:15:54.14#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.09:15:54.14#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.09:15:54.14#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.09:15:54.14#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.09:15:54.14$vck44/valo=7,864.99 2006.173.09:15:54.14#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.09:15:54.14#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.09:15:54.14#ibcon#ireg 17 cls_cnt 0 2006.173.09:15:54.14#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.09:15:54.14#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.09:15:54.14#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.09:15:54.14#ibcon#enter wrdev, iclass 10, count 0 2006.173.09:15:54.14#ibcon#first serial, iclass 10, count 0 2006.173.09:15:54.14#ibcon#enter sib2, iclass 10, count 0 2006.173.09:15:54.14#ibcon#flushed, iclass 10, count 0 2006.173.09:15:54.14#ibcon#about to write, iclass 10, count 0 2006.173.09:15:54.14#ibcon#wrote, iclass 10, count 0 2006.173.09:15:54.14#ibcon#about to read 3, iclass 10, count 0 2006.173.09:15:54.16#ibcon#read 3, iclass 10, count 0 2006.173.09:15:54.16#ibcon#about to read 4, iclass 10, count 0 2006.173.09:15:54.16#ibcon#read 4, iclass 10, count 0 2006.173.09:15:54.16#ibcon#about to read 5, iclass 10, count 0 2006.173.09:15:54.16#ibcon#read 5, iclass 10, count 0 2006.173.09:15:54.16#ibcon#about to read 6, iclass 10, count 0 2006.173.09:15:54.16#ibcon#read 6, iclass 10, count 0 2006.173.09:15:54.16#ibcon#end of sib2, iclass 10, count 0 2006.173.09:15:54.16#ibcon#*mode == 0, iclass 10, count 0 2006.173.09:15:54.16#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.09:15:54.16#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.09:15:54.16#ibcon#*before write, iclass 10, count 0 2006.173.09:15:54.16#ibcon#enter sib2, iclass 10, count 0 2006.173.09:15:54.16#ibcon#flushed, iclass 10, count 0 2006.173.09:15:54.16#ibcon#about to write, iclass 10, count 0 2006.173.09:15:54.16#ibcon#wrote, iclass 10, count 0 2006.173.09:15:54.16#ibcon#about to read 3, iclass 10, count 0 2006.173.09:15:54.20#ibcon#read 3, iclass 10, count 0 2006.173.09:15:54.20#ibcon#about to read 4, iclass 10, count 0 2006.173.09:15:54.20#ibcon#read 4, iclass 10, count 0 2006.173.09:15:54.20#ibcon#about to read 5, iclass 10, count 0 2006.173.09:15:54.20#ibcon#read 5, iclass 10, count 0 2006.173.09:15:54.20#ibcon#about to read 6, iclass 10, count 0 2006.173.09:15:54.20#ibcon#read 6, iclass 10, count 0 2006.173.09:15:54.20#ibcon#end of sib2, iclass 10, count 0 2006.173.09:15:54.20#ibcon#*after write, iclass 10, count 0 2006.173.09:15:54.20#ibcon#*before return 0, iclass 10, count 0 2006.173.09:15:54.20#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.09:15:54.20#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.09:15:54.20#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.09:15:54.20#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.09:15:54.20$vck44/va=7,4 2006.173.09:15:54.20#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.09:15:54.20#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.09:15:54.20#ibcon#ireg 11 cls_cnt 2 2006.173.09:15:54.20#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.09:15:54.26#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.09:15:54.26#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.09:15:54.26#ibcon#enter wrdev, iclass 12, count 2 2006.173.09:15:54.26#ibcon#first serial, iclass 12, count 2 2006.173.09:15:54.26#ibcon#enter sib2, iclass 12, count 2 2006.173.09:15:54.26#ibcon#flushed, iclass 12, count 2 2006.173.09:15:54.26#ibcon#about to write, iclass 12, count 2 2006.173.09:15:54.26#ibcon#wrote, iclass 12, count 2 2006.173.09:15:54.26#ibcon#about to read 3, iclass 12, count 2 2006.173.09:15:54.28#ibcon#read 3, iclass 12, count 2 2006.173.09:15:54.28#ibcon#about to read 4, iclass 12, count 2 2006.173.09:15:54.28#ibcon#read 4, iclass 12, count 2 2006.173.09:15:54.28#ibcon#about to read 5, iclass 12, count 2 2006.173.09:15:54.28#ibcon#read 5, iclass 12, count 2 2006.173.09:15:54.28#ibcon#about to read 6, iclass 12, count 2 2006.173.09:15:54.28#ibcon#read 6, iclass 12, count 2 2006.173.09:15:54.28#ibcon#end of sib2, iclass 12, count 2 2006.173.09:15:54.28#ibcon#*mode == 0, iclass 12, count 2 2006.173.09:15:54.28#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.09:15:54.28#ibcon#[25=AT07-04\r\n] 2006.173.09:15:54.28#ibcon#*before write, iclass 12, count 2 2006.173.09:15:54.28#ibcon#enter sib2, iclass 12, count 2 2006.173.09:15:54.28#ibcon#flushed, iclass 12, count 2 2006.173.09:15:54.28#ibcon#about to write, iclass 12, count 2 2006.173.09:15:54.28#ibcon#wrote, iclass 12, count 2 2006.173.09:15:54.28#ibcon#about to read 3, iclass 12, count 2 2006.173.09:15:54.31#ibcon#read 3, iclass 12, count 2 2006.173.09:15:54.31#ibcon#about to read 4, iclass 12, count 2 2006.173.09:15:54.31#ibcon#read 4, iclass 12, count 2 2006.173.09:15:54.31#ibcon#about to read 5, iclass 12, count 2 2006.173.09:15:54.31#ibcon#read 5, iclass 12, count 2 2006.173.09:15:54.31#ibcon#about to read 6, iclass 12, count 2 2006.173.09:15:54.31#ibcon#read 6, iclass 12, count 2 2006.173.09:15:54.31#ibcon#end of sib2, iclass 12, count 2 2006.173.09:15:54.31#ibcon#*after write, iclass 12, count 2 2006.173.09:15:54.31#ibcon#*before return 0, iclass 12, count 2 2006.173.09:15:54.31#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.09:15:54.31#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.09:15:54.31#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.09:15:54.31#ibcon#ireg 7 cls_cnt 0 2006.173.09:15:54.31#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.09:15:54.43#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.09:15:54.43#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.09:15:54.43#ibcon#enter wrdev, iclass 12, count 0 2006.173.09:15:54.43#ibcon#first serial, iclass 12, count 0 2006.173.09:15:54.43#ibcon#enter sib2, iclass 12, count 0 2006.173.09:15:54.43#ibcon#flushed, iclass 12, count 0 2006.173.09:15:54.43#ibcon#about to write, iclass 12, count 0 2006.173.09:15:54.43#ibcon#wrote, iclass 12, count 0 2006.173.09:15:54.43#ibcon#about to read 3, iclass 12, count 0 2006.173.09:15:54.45#ibcon#read 3, iclass 12, count 0 2006.173.09:15:54.45#ibcon#about to read 4, iclass 12, count 0 2006.173.09:15:54.45#ibcon#read 4, iclass 12, count 0 2006.173.09:15:54.45#ibcon#about to read 5, iclass 12, count 0 2006.173.09:15:54.45#ibcon#read 5, iclass 12, count 0 2006.173.09:15:54.45#ibcon#about to read 6, iclass 12, count 0 2006.173.09:15:54.45#ibcon#read 6, iclass 12, count 0 2006.173.09:15:54.45#ibcon#end of sib2, iclass 12, count 0 2006.173.09:15:54.45#ibcon#*mode == 0, iclass 12, count 0 2006.173.09:15:54.45#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.09:15:54.45#ibcon#[25=USB\r\n] 2006.173.09:15:54.45#ibcon#*before write, iclass 12, count 0 2006.173.09:15:54.45#ibcon#enter sib2, iclass 12, count 0 2006.173.09:15:54.45#ibcon#flushed, iclass 12, count 0 2006.173.09:15:54.45#ibcon#about to write, iclass 12, count 0 2006.173.09:15:54.45#ibcon#wrote, iclass 12, count 0 2006.173.09:15:54.45#ibcon#about to read 3, iclass 12, count 0 2006.173.09:15:54.48#ibcon#read 3, iclass 12, count 0 2006.173.09:15:54.48#ibcon#about to read 4, iclass 12, count 0 2006.173.09:15:54.48#ibcon#read 4, iclass 12, count 0 2006.173.09:15:54.48#ibcon#about to read 5, iclass 12, count 0 2006.173.09:15:54.48#ibcon#read 5, iclass 12, count 0 2006.173.09:15:54.48#ibcon#about to read 6, iclass 12, count 0 2006.173.09:15:54.48#ibcon#read 6, iclass 12, count 0 2006.173.09:15:54.48#ibcon#end of sib2, iclass 12, count 0 2006.173.09:15:54.48#ibcon#*after write, iclass 12, count 0 2006.173.09:15:54.48#ibcon#*before return 0, iclass 12, count 0 2006.173.09:15:54.48#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.09:15:54.48#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.09:15:54.48#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.09:15:54.48#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.09:15:54.48$vck44/valo=8,884.99 2006.173.09:15:54.48#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.09:15:54.48#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.09:15:54.48#ibcon#ireg 17 cls_cnt 0 2006.173.09:15:54.48#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.09:15:54.48#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.09:15:54.48#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.09:15:54.48#ibcon#enter wrdev, iclass 14, count 0 2006.173.09:15:54.48#ibcon#first serial, iclass 14, count 0 2006.173.09:15:54.48#ibcon#enter sib2, iclass 14, count 0 2006.173.09:15:54.48#ibcon#flushed, iclass 14, count 0 2006.173.09:15:54.48#ibcon#about to write, iclass 14, count 0 2006.173.09:15:54.48#ibcon#wrote, iclass 14, count 0 2006.173.09:15:54.48#ibcon#about to read 3, iclass 14, count 0 2006.173.09:15:54.50#ibcon#read 3, iclass 14, count 0 2006.173.09:15:54.50#ibcon#about to read 4, iclass 14, count 0 2006.173.09:15:54.50#ibcon#read 4, iclass 14, count 0 2006.173.09:15:54.50#ibcon#about to read 5, iclass 14, count 0 2006.173.09:15:54.50#ibcon#read 5, iclass 14, count 0 2006.173.09:15:54.50#ibcon#about to read 6, iclass 14, count 0 2006.173.09:15:54.50#ibcon#read 6, iclass 14, count 0 2006.173.09:15:54.50#ibcon#end of sib2, iclass 14, count 0 2006.173.09:15:54.50#ibcon#*mode == 0, iclass 14, count 0 2006.173.09:15:54.50#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.09:15:54.50#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.09:15:54.50#ibcon#*before write, iclass 14, count 0 2006.173.09:15:54.50#ibcon#enter sib2, iclass 14, count 0 2006.173.09:15:54.50#ibcon#flushed, iclass 14, count 0 2006.173.09:15:54.50#ibcon#about to write, iclass 14, count 0 2006.173.09:15:54.50#ibcon#wrote, iclass 14, count 0 2006.173.09:15:54.50#ibcon#about to read 3, iclass 14, count 0 2006.173.09:15:54.54#ibcon#read 3, iclass 14, count 0 2006.173.09:15:54.54#ibcon#about to read 4, iclass 14, count 0 2006.173.09:15:54.54#ibcon#read 4, iclass 14, count 0 2006.173.09:15:54.54#ibcon#about to read 5, iclass 14, count 0 2006.173.09:15:54.54#ibcon#read 5, iclass 14, count 0 2006.173.09:15:54.54#ibcon#about to read 6, iclass 14, count 0 2006.173.09:15:54.54#ibcon#read 6, iclass 14, count 0 2006.173.09:15:54.54#ibcon#end of sib2, iclass 14, count 0 2006.173.09:15:54.54#ibcon#*after write, iclass 14, count 0 2006.173.09:15:54.54#ibcon#*before return 0, iclass 14, count 0 2006.173.09:15:54.54#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.09:15:54.54#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.09:15:54.54#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.09:15:54.54#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.09:15:54.54$vck44/va=8,4 2006.173.09:15:54.54#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.09:15:54.54#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.09:15:54.54#ibcon#ireg 11 cls_cnt 2 2006.173.09:15:54.54#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.09:15:54.60#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.09:15:54.60#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.09:15:54.60#ibcon#enter wrdev, iclass 16, count 2 2006.173.09:15:54.60#ibcon#first serial, iclass 16, count 2 2006.173.09:15:54.60#ibcon#enter sib2, iclass 16, count 2 2006.173.09:15:54.60#ibcon#flushed, iclass 16, count 2 2006.173.09:15:54.60#ibcon#about to write, iclass 16, count 2 2006.173.09:15:54.60#ibcon#wrote, iclass 16, count 2 2006.173.09:15:54.60#ibcon#about to read 3, iclass 16, count 2 2006.173.09:15:54.62#ibcon#read 3, iclass 16, count 2 2006.173.09:15:54.62#ibcon#about to read 4, iclass 16, count 2 2006.173.09:15:54.62#ibcon#read 4, iclass 16, count 2 2006.173.09:15:54.62#ibcon#about to read 5, iclass 16, count 2 2006.173.09:15:54.62#ibcon#read 5, iclass 16, count 2 2006.173.09:15:54.62#ibcon#about to read 6, iclass 16, count 2 2006.173.09:15:54.62#ibcon#read 6, iclass 16, count 2 2006.173.09:15:54.62#ibcon#end of sib2, iclass 16, count 2 2006.173.09:15:54.62#ibcon#*mode == 0, iclass 16, count 2 2006.173.09:15:54.62#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.09:15:54.62#ibcon#[25=AT08-04\r\n] 2006.173.09:15:54.62#ibcon#*before write, iclass 16, count 2 2006.173.09:15:54.62#ibcon#enter sib2, iclass 16, count 2 2006.173.09:15:54.62#ibcon#flushed, iclass 16, count 2 2006.173.09:15:54.62#ibcon#about to write, iclass 16, count 2 2006.173.09:15:54.62#ibcon#wrote, iclass 16, count 2 2006.173.09:15:54.62#ibcon#about to read 3, iclass 16, count 2 2006.173.09:15:54.65#ibcon#read 3, iclass 16, count 2 2006.173.09:15:54.65#ibcon#about to read 4, iclass 16, count 2 2006.173.09:15:54.65#ibcon#read 4, iclass 16, count 2 2006.173.09:15:54.65#ibcon#about to read 5, iclass 16, count 2 2006.173.09:15:54.65#ibcon#read 5, iclass 16, count 2 2006.173.09:15:54.65#ibcon#about to read 6, iclass 16, count 2 2006.173.09:15:54.65#ibcon#read 6, iclass 16, count 2 2006.173.09:15:54.65#ibcon#end of sib2, iclass 16, count 2 2006.173.09:15:54.65#ibcon#*after write, iclass 16, count 2 2006.173.09:15:54.65#ibcon#*before return 0, iclass 16, count 2 2006.173.09:15:54.65#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.09:15:54.65#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.09:15:54.65#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.09:15:54.65#ibcon#ireg 7 cls_cnt 0 2006.173.09:15:54.65#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.09:15:54.77#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.09:15:54.77#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.09:15:54.77#ibcon#enter wrdev, iclass 16, count 0 2006.173.09:15:54.77#ibcon#first serial, iclass 16, count 0 2006.173.09:15:54.77#ibcon#enter sib2, iclass 16, count 0 2006.173.09:15:54.77#ibcon#flushed, iclass 16, count 0 2006.173.09:15:54.77#ibcon#about to write, iclass 16, count 0 2006.173.09:15:54.77#ibcon#wrote, iclass 16, count 0 2006.173.09:15:54.77#ibcon#about to read 3, iclass 16, count 0 2006.173.09:15:54.79#ibcon#read 3, iclass 16, count 0 2006.173.09:15:54.79#ibcon#about to read 4, iclass 16, count 0 2006.173.09:15:54.79#ibcon#read 4, iclass 16, count 0 2006.173.09:15:54.79#ibcon#about to read 5, iclass 16, count 0 2006.173.09:15:54.79#ibcon#read 5, iclass 16, count 0 2006.173.09:15:54.79#ibcon#about to read 6, iclass 16, count 0 2006.173.09:15:54.79#ibcon#read 6, iclass 16, count 0 2006.173.09:15:54.79#ibcon#end of sib2, iclass 16, count 0 2006.173.09:15:54.79#ibcon#*mode == 0, iclass 16, count 0 2006.173.09:15:54.79#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.09:15:54.79#ibcon#[25=USB\r\n] 2006.173.09:15:54.79#ibcon#*before write, iclass 16, count 0 2006.173.09:15:54.79#ibcon#enter sib2, iclass 16, count 0 2006.173.09:15:54.79#ibcon#flushed, iclass 16, count 0 2006.173.09:15:54.79#ibcon#about to write, iclass 16, count 0 2006.173.09:15:54.79#ibcon#wrote, iclass 16, count 0 2006.173.09:15:54.79#ibcon#about to read 3, iclass 16, count 0 2006.173.09:15:54.82#ibcon#read 3, iclass 16, count 0 2006.173.09:15:54.82#ibcon#about to read 4, iclass 16, count 0 2006.173.09:15:54.82#ibcon#read 4, iclass 16, count 0 2006.173.09:15:54.82#ibcon#about to read 5, iclass 16, count 0 2006.173.09:15:54.82#ibcon#read 5, iclass 16, count 0 2006.173.09:15:54.82#ibcon#about to read 6, iclass 16, count 0 2006.173.09:15:54.82#ibcon#read 6, iclass 16, count 0 2006.173.09:15:54.82#ibcon#end of sib2, iclass 16, count 0 2006.173.09:15:54.82#ibcon#*after write, iclass 16, count 0 2006.173.09:15:54.82#ibcon#*before return 0, iclass 16, count 0 2006.173.09:15:54.82#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.09:15:54.82#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.09:15:54.82#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.09:15:54.82#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.09:15:54.82$vck44/vblo=1,629.99 2006.173.09:15:54.82#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.09:15:54.82#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.09:15:54.82#ibcon#ireg 17 cls_cnt 0 2006.173.09:15:54.82#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.09:15:54.82#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.09:15:54.82#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.09:15:54.82#ibcon#enter wrdev, iclass 18, count 0 2006.173.09:15:54.82#ibcon#first serial, iclass 18, count 0 2006.173.09:15:54.82#ibcon#enter sib2, iclass 18, count 0 2006.173.09:15:54.82#ibcon#flushed, iclass 18, count 0 2006.173.09:15:54.82#ibcon#about to write, iclass 18, count 0 2006.173.09:15:54.82#ibcon#wrote, iclass 18, count 0 2006.173.09:15:54.82#ibcon#about to read 3, iclass 18, count 0 2006.173.09:15:54.84#ibcon#read 3, iclass 18, count 0 2006.173.09:15:54.84#ibcon#about to read 4, iclass 18, count 0 2006.173.09:15:54.84#ibcon#read 4, iclass 18, count 0 2006.173.09:15:54.84#ibcon#about to read 5, iclass 18, count 0 2006.173.09:15:54.84#ibcon#read 5, iclass 18, count 0 2006.173.09:15:54.84#ibcon#about to read 6, iclass 18, count 0 2006.173.09:15:54.84#ibcon#read 6, iclass 18, count 0 2006.173.09:15:54.84#ibcon#end of sib2, iclass 18, count 0 2006.173.09:15:54.84#ibcon#*mode == 0, iclass 18, count 0 2006.173.09:15:54.84#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.09:15:54.84#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.09:15:54.84#ibcon#*before write, iclass 18, count 0 2006.173.09:15:54.84#ibcon#enter sib2, iclass 18, count 0 2006.173.09:15:54.84#ibcon#flushed, iclass 18, count 0 2006.173.09:15:54.84#ibcon#about to write, iclass 18, count 0 2006.173.09:15:54.84#ibcon#wrote, iclass 18, count 0 2006.173.09:15:54.84#ibcon#about to read 3, iclass 18, count 0 2006.173.09:15:54.88#ibcon#read 3, iclass 18, count 0 2006.173.09:15:54.88#ibcon#about to read 4, iclass 18, count 0 2006.173.09:15:54.88#ibcon#read 4, iclass 18, count 0 2006.173.09:15:54.88#ibcon#about to read 5, iclass 18, count 0 2006.173.09:15:54.88#ibcon#read 5, iclass 18, count 0 2006.173.09:15:54.88#ibcon#about to read 6, iclass 18, count 0 2006.173.09:15:54.88#ibcon#read 6, iclass 18, count 0 2006.173.09:15:54.88#ibcon#end of sib2, iclass 18, count 0 2006.173.09:15:54.88#ibcon#*after write, iclass 18, count 0 2006.173.09:15:54.88#ibcon#*before return 0, iclass 18, count 0 2006.173.09:15:54.88#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.09:15:54.88#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.09:15:54.88#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.09:15:54.88#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.09:15:54.88$vck44/vb=1,4 2006.173.09:15:54.88#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.09:15:54.88#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.09:15:54.88#ibcon#ireg 11 cls_cnt 2 2006.173.09:15:54.88#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.09:15:54.88#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.09:15:54.88#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.09:15:54.88#ibcon#enter wrdev, iclass 20, count 2 2006.173.09:15:54.88#ibcon#first serial, iclass 20, count 2 2006.173.09:15:54.88#ibcon#enter sib2, iclass 20, count 2 2006.173.09:15:54.88#ibcon#flushed, iclass 20, count 2 2006.173.09:15:54.88#ibcon#about to write, iclass 20, count 2 2006.173.09:15:54.88#ibcon#wrote, iclass 20, count 2 2006.173.09:15:54.88#ibcon#about to read 3, iclass 20, count 2 2006.173.09:15:54.90#ibcon#read 3, iclass 20, count 2 2006.173.09:15:54.90#ibcon#about to read 4, iclass 20, count 2 2006.173.09:15:54.90#ibcon#read 4, iclass 20, count 2 2006.173.09:15:54.90#ibcon#about to read 5, iclass 20, count 2 2006.173.09:15:54.90#ibcon#read 5, iclass 20, count 2 2006.173.09:15:54.90#ibcon#about to read 6, iclass 20, count 2 2006.173.09:15:54.90#ibcon#read 6, iclass 20, count 2 2006.173.09:15:54.90#ibcon#end of sib2, iclass 20, count 2 2006.173.09:15:54.90#ibcon#*mode == 0, iclass 20, count 2 2006.173.09:15:54.90#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.09:15:54.90#ibcon#[27=AT01-04\r\n] 2006.173.09:15:54.90#ibcon#*before write, iclass 20, count 2 2006.173.09:15:54.90#ibcon#enter sib2, iclass 20, count 2 2006.173.09:15:54.90#ibcon#flushed, iclass 20, count 2 2006.173.09:15:54.90#ibcon#about to write, iclass 20, count 2 2006.173.09:15:54.90#ibcon#wrote, iclass 20, count 2 2006.173.09:15:54.90#ibcon#about to read 3, iclass 20, count 2 2006.173.09:15:54.93#ibcon#read 3, iclass 20, count 2 2006.173.09:15:54.93#ibcon#about to read 4, iclass 20, count 2 2006.173.09:15:54.93#ibcon#read 4, iclass 20, count 2 2006.173.09:15:54.93#ibcon#about to read 5, iclass 20, count 2 2006.173.09:15:54.93#ibcon#read 5, iclass 20, count 2 2006.173.09:15:54.93#ibcon#about to read 6, iclass 20, count 2 2006.173.09:15:54.93#ibcon#read 6, iclass 20, count 2 2006.173.09:15:54.93#ibcon#end of sib2, iclass 20, count 2 2006.173.09:15:54.93#ibcon#*after write, iclass 20, count 2 2006.173.09:15:54.93#ibcon#*before return 0, iclass 20, count 2 2006.173.09:15:54.93#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.09:15:54.93#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.09:15:54.93#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.09:15:54.93#ibcon#ireg 7 cls_cnt 0 2006.173.09:15:54.93#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.09:15:55.05#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.09:15:55.05#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.09:15:55.05#ibcon#enter wrdev, iclass 20, count 0 2006.173.09:15:55.05#ibcon#first serial, iclass 20, count 0 2006.173.09:15:55.05#ibcon#enter sib2, iclass 20, count 0 2006.173.09:15:55.05#ibcon#flushed, iclass 20, count 0 2006.173.09:15:55.05#ibcon#about to write, iclass 20, count 0 2006.173.09:15:55.05#ibcon#wrote, iclass 20, count 0 2006.173.09:15:55.05#ibcon#about to read 3, iclass 20, count 0 2006.173.09:15:55.07#ibcon#read 3, iclass 20, count 0 2006.173.09:15:55.07#ibcon#about to read 4, iclass 20, count 0 2006.173.09:15:55.07#ibcon#read 4, iclass 20, count 0 2006.173.09:15:55.07#ibcon#about to read 5, iclass 20, count 0 2006.173.09:15:55.07#ibcon#read 5, iclass 20, count 0 2006.173.09:15:55.07#ibcon#about to read 6, iclass 20, count 0 2006.173.09:15:55.07#ibcon#read 6, iclass 20, count 0 2006.173.09:15:55.07#ibcon#end of sib2, iclass 20, count 0 2006.173.09:15:55.07#ibcon#*mode == 0, iclass 20, count 0 2006.173.09:15:55.07#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.09:15:55.07#ibcon#[27=USB\r\n] 2006.173.09:15:55.07#ibcon#*before write, iclass 20, count 0 2006.173.09:15:55.07#ibcon#enter sib2, iclass 20, count 0 2006.173.09:15:55.07#ibcon#flushed, iclass 20, count 0 2006.173.09:15:55.07#ibcon#about to write, iclass 20, count 0 2006.173.09:15:55.07#ibcon#wrote, iclass 20, count 0 2006.173.09:15:55.07#ibcon#about to read 3, iclass 20, count 0 2006.173.09:15:55.10#ibcon#read 3, iclass 20, count 0 2006.173.09:15:55.10#ibcon#about to read 4, iclass 20, count 0 2006.173.09:15:55.10#ibcon#read 4, iclass 20, count 0 2006.173.09:15:55.10#ibcon#about to read 5, iclass 20, count 0 2006.173.09:15:55.10#ibcon#read 5, iclass 20, count 0 2006.173.09:15:55.10#ibcon#about to read 6, iclass 20, count 0 2006.173.09:15:55.10#ibcon#read 6, iclass 20, count 0 2006.173.09:15:55.10#ibcon#end of sib2, iclass 20, count 0 2006.173.09:15:55.10#ibcon#*after write, iclass 20, count 0 2006.173.09:15:55.10#ibcon#*before return 0, iclass 20, count 0 2006.173.09:15:55.10#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.09:15:55.10#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.09:15:55.10#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.09:15:55.10#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.09:15:55.10$vck44/vblo=2,634.99 2006.173.09:15:55.10#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.09:15:55.10#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.09:15:55.10#ibcon#ireg 17 cls_cnt 0 2006.173.09:15:55.10#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.09:15:55.10#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.09:15:55.10#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.09:15:55.10#ibcon#enter wrdev, iclass 22, count 0 2006.173.09:15:55.10#ibcon#first serial, iclass 22, count 0 2006.173.09:15:55.10#ibcon#enter sib2, iclass 22, count 0 2006.173.09:15:55.10#ibcon#flushed, iclass 22, count 0 2006.173.09:15:55.10#ibcon#about to write, iclass 22, count 0 2006.173.09:15:55.10#ibcon#wrote, iclass 22, count 0 2006.173.09:15:55.10#ibcon#about to read 3, iclass 22, count 0 2006.173.09:15:55.12#ibcon#read 3, iclass 22, count 0 2006.173.09:15:55.12#ibcon#about to read 4, iclass 22, count 0 2006.173.09:15:55.12#ibcon#read 4, iclass 22, count 0 2006.173.09:15:55.12#ibcon#about to read 5, iclass 22, count 0 2006.173.09:15:55.12#ibcon#read 5, iclass 22, count 0 2006.173.09:15:55.12#ibcon#about to read 6, iclass 22, count 0 2006.173.09:15:55.12#ibcon#read 6, iclass 22, count 0 2006.173.09:15:55.12#ibcon#end of sib2, iclass 22, count 0 2006.173.09:15:55.12#ibcon#*mode == 0, iclass 22, count 0 2006.173.09:15:55.12#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.09:15:55.12#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.09:15:55.12#ibcon#*before write, iclass 22, count 0 2006.173.09:15:55.12#ibcon#enter sib2, iclass 22, count 0 2006.173.09:15:55.12#ibcon#flushed, iclass 22, count 0 2006.173.09:15:55.12#ibcon#about to write, iclass 22, count 0 2006.173.09:15:55.12#ibcon#wrote, iclass 22, count 0 2006.173.09:15:55.12#ibcon#about to read 3, iclass 22, count 0 2006.173.09:15:55.16#ibcon#read 3, iclass 22, count 0 2006.173.09:15:55.16#ibcon#about to read 4, iclass 22, count 0 2006.173.09:15:55.16#ibcon#read 4, iclass 22, count 0 2006.173.09:15:55.16#ibcon#about to read 5, iclass 22, count 0 2006.173.09:15:55.16#ibcon#read 5, iclass 22, count 0 2006.173.09:15:55.16#ibcon#about to read 6, iclass 22, count 0 2006.173.09:15:55.16#ibcon#read 6, iclass 22, count 0 2006.173.09:15:55.16#ibcon#end of sib2, iclass 22, count 0 2006.173.09:15:55.16#ibcon#*after write, iclass 22, count 0 2006.173.09:15:55.16#ibcon#*before return 0, iclass 22, count 0 2006.173.09:15:55.16#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.09:15:55.16#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.09:15:55.16#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.09:15:55.16#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.09:15:55.16$vck44/vb=2,4 2006.173.09:15:55.16#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.09:15:55.16#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.09:15:55.16#ibcon#ireg 11 cls_cnt 2 2006.173.09:15:55.16#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.09:15:55.22#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.09:15:55.22#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.09:15:55.22#ibcon#enter wrdev, iclass 24, count 2 2006.173.09:15:55.22#ibcon#first serial, iclass 24, count 2 2006.173.09:15:55.22#ibcon#enter sib2, iclass 24, count 2 2006.173.09:15:55.22#ibcon#flushed, iclass 24, count 2 2006.173.09:15:55.22#ibcon#about to write, iclass 24, count 2 2006.173.09:15:55.22#ibcon#wrote, iclass 24, count 2 2006.173.09:15:55.22#ibcon#about to read 3, iclass 24, count 2 2006.173.09:15:55.24#ibcon#read 3, iclass 24, count 2 2006.173.09:15:55.24#ibcon#about to read 4, iclass 24, count 2 2006.173.09:15:55.24#ibcon#read 4, iclass 24, count 2 2006.173.09:15:55.24#ibcon#about to read 5, iclass 24, count 2 2006.173.09:15:55.24#ibcon#read 5, iclass 24, count 2 2006.173.09:15:55.24#ibcon#about to read 6, iclass 24, count 2 2006.173.09:15:55.24#ibcon#read 6, iclass 24, count 2 2006.173.09:15:55.24#ibcon#end of sib2, iclass 24, count 2 2006.173.09:15:55.24#ibcon#*mode == 0, iclass 24, count 2 2006.173.09:15:55.24#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.09:15:55.24#ibcon#[27=AT02-04\r\n] 2006.173.09:15:55.24#ibcon#*before write, iclass 24, count 2 2006.173.09:15:55.24#ibcon#enter sib2, iclass 24, count 2 2006.173.09:15:55.24#ibcon#flushed, iclass 24, count 2 2006.173.09:15:55.24#ibcon#about to write, iclass 24, count 2 2006.173.09:15:55.24#ibcon#wrote, iclass 24, count 2 2006.173.09:15:55.24#ibcon#about to read 3, iclass 24, count 2 2006.173.09:15:55.27#ibcon#read 3, iclass 24, count 2 2006.173.09:15:55.27#ibcon#about to read 4, iclass 24, count 2 2006.173.09:15:55.27#ibcon#read 4, iclass 24, count 2 2006.173.09:15:55.27#ibcon#about to read 5, iclass 24, count 2 2006.173.09:15:55.27#ibcon#read 5, iclass 24, count 2 2006.173.09:15:55.27#ibcon#about to read 6, iclass 24, count 2 2006.173.09:15:55.27#ibcon#read 6, iclass 24, count 2 2006.173.09:15:55.27#ibcon#end of sib2, iclass 24, count 2 2006.173.09:15:55.27#ibcon#*after write, iclass 24, count 2 2006.173.09:15:55.27#ibcon#*before return 0, iclass 24, count 2 2006.173.09:15:55.27#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.09:15:55.27#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.09:15:55.27#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.09:15:55.27#ibcon#ireg 7 cls_cnt 0 2006.173.09:15:55.27#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.09:15:55.39#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.09:15:55.39#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.09:15:55.39#ibcon#enter wrdev, iclass 24, count 0 2006.173.09:15:55.39#ibcon#first serial, iclass 24, count 0 2006.173.09:15:55.39#ibcon#enter sib2, iclass 24, count 0 2006.173.09:15:55.39#ibcon#flushed, iclass 24, count 0 2006.173.09:15:55.39#ibcon#about to write, iclass 24, count 0 2006.173.09:15:55.39#ibcon#wrote, iclass 24, count 0 2006.173.09:15:55.39#ibcon#about to read 3, iclass 24, count 0 2006.173.09:15:55.41#ibcon#read 3, iclass 24, count 0 2006.173.09:15:55.41#ibcon#about to read 4, iclass 24, count 0 2006.173.09:15:55.41#ibcon#read 4, iclass 24, count 0 2006.173.09:15:55.41#ibcon#about to read 5, iclass 24, count 0 2006.173.09:15:55.41#ibcon#read 5, iclass 24, count 0 2006.173.09:15:55.41#ibcon#about to read 6, iclass 24, count 0 2006.173.09:15:55.41#ibcon#read 6, iclass 24, count 0 2006.173.09:15:55.41#ibcon#end of sib2, iclass 24, count 0 2006.173.09:15:55.41#ibcon#*mode == 0, iclass 24, count 0 2006.173.09:15:55.41#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.09:15:55.41#ibcon#[27=USB\r\n] 2006.173.09:15:55.41#ibcon#*before write, iclass 24, count 0 2006.173.09:15:55.41#ibcon#enter sib2, iclass 24, count 0 2006.173.09:15:55.41#ibcon#flushed, iclass 24, count 0 2006.173.09:15:55.41#ibcon#about to write, iclass 24, count 0 2006.173.09:15:55.41#ibcon#wrote, iclass 24, count 0 2006.173.09:15:55.41#ibcon#about to read 3, iclass 24, count 0 2006.173.09:15:55.44#ibcon#read 3, iclass 24, count 0 2006.173.09:15:55.44#ibcon#about to read 4, iclass 24, count 0 2006.173.09:15:55.44#ibcon#read 4, iclass 24, count 0 2006.173.09:15:55.44#ibcon#about to read 5, iclass 24, count 0 2006.173.09:15:55.44#ibcon#read 5, iclass 24, count 0 2006.173.09:15:55.44#ibcon#about to read 6, iclass 24, count 0 2006.173.09:15:55.44#ibcon#read 6, iclass 24, count 0 2006.173.09:15:55.44#ibcon#end of sib2, iclass 24, count 0 2006.173.09:15:55.44#ibcon#*after write, iclass 24, count 0 2006.173.09:15:55.44#ibcon#*before return 0, iclass 24, count 0 2006.173.09:15:55.44#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.09:15:55.44#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.09:15:55.44#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.09:15:55.44#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.09:15:55.44$vck44/vblo=3,649.99 2006.173.09:15:55.44#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.09:15:55.44#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.09:15:55.44#ibcon#ireg 17 cls_cnt 0 2006.173.09:15:55.44#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.09:15:55.44#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.09:15:55.44#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.09:15:55.44#ibcon#enter wrdev, iclass 26, count 0 2006.173.09:15:55.44#ibcon#first serial, iclass 26, count 0 2006.173.09:15:55.44#ibcon#enter sib2, iclass 26, count 0 2006.173.09:15:55.44#ibcon#flushed, iclass 26, count 0 2006.173.09:15:55.44#ibcon#about to write, iclass 26, count 0 2006.173.09:15:55.44#ibcon#wrote, iclass 26, count 0 2006.173.09:15:55.44#ibcon#about to read 3, iclass 26, count 0 2006.173.09:15:55.46#ibcon#read 3, iclass 26, count 0 2006.173.09:15:55.46#ibcon#about to read 4, iclass 26, count 0 2006.173.09:15:55.46#ibcon#read 4, iclass 26, count 0 2006.173.09:15:55.46#ibcon#about to read 5, iclass 26, count 0 2006.173.09:15:55.46#ibcon#read 5, iclass 26, count 0 2006.173.09:15:55.46#ibcon#about to read 6, iclass 26, count 0 2006.173.09:15:55.46#ibcon#read 6, iclass 26, count 0 2006.173.09:15:55.46#ibcon#end of sib2, iclass 26, count 0 2006.173.09:15:55.46#ibcon#*mode == 0, iclass 26, count 0 2006.173.09:15:55.46#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.09:15:55.46#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.09:15:55.46#ibcon#*before write, iclass 26, count 0 2006.173.09:15:55.46#ibcon#enter sib2, iclass 26, count 0 2006.173.09:15:55.46#ibcon#flushed, iclass 26, count 0 2006.173.09:15:55.46#ibcon#about to write, iclass 26, count 0 2006.173.09:15:55.46#ibcon#wrote, iclass 26, count 0 2006.173.09:15:55.46#ibcon#about to read 3, iclass 26, count 0 2006.173.09:15:55.50#ibcon#read 3, iclass 26, count 0 2006.173.09:15:55.50#ibcon#about to read 4, iclass 26, count 0 2006.173.09:15:55.50#ibcon#read 4, iclass 26, count 0 2006.173.09:15:55.50#ibcon#about to read 5, iclass 26, count 0 2006.173.09:15:55.50#ibcon#read 5, iclass 26, count 0 2006.173.09:15:55.50#ibcon#about to read 6, iclass 26, count 0 2006.173.09:15:55.50#ibcon#read 6, iclass 26, count 0 2006.173.09:15:55.50#ibcon#end of sib2, iclass 26, count 0 2006.173.09:15:55.50#ibcon#*after write, iclass 26, count 0 2006.173.09:15:55.50#ibcon#*before return 0, iclass 26, count 0 2006.173.09:15:55.50#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.09:15:55.50#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.09:15:55.50#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.09:15:55.50#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.09:15:55.50$vck44/vb=3,4 2006.173.09:15:55.50#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.09:15:55.50#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.09:15:55.50#ibcon#ireg 11 cls_cnt 2 2006.173.09:15:55.50#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.09:15:55.56#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.09:15:55.56#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.09:15:55.56#ibcon#enter wrdev, iclass 28, count 2 2006.173.09:15:55.56#ibcon#first serial, iclass 28, count 2 2006.173.09:15:55.56#ibcon#enter sib2, iclass 28, count 2 2006.173.09:15:55.56#ibcon#flushed, iclass 28, count 2 2006.173.09:15:55.56#ibcon#about to write, iclass 28, count 2 2006.173.09:15:55.56#ibcon#wrote, iclass 28, count 2 2006.173.09:15:55.56#ibcon#about to read 3, iclass 28, count 2 2006.173.09:15:55.58#ibcon#read 3, iclass 28, count 2 2006.173.09:15:55.58#ibcon#about to read 4, iclass 28, count 2 2006.173.09:15:55.58#ibcon#read 4, iclass 28, count 2 2006.173.09:15:55.58#ibcon#about to read 5, iclass 28, count 2 2006.173.09:15:55.58#ibcon#read 5, iclass 28, count 2 2006.173.09:15:55.58#ibcon#about to read 6, iclass 28, count 2 2006.173.09:15:55.58#ibcon#read 6, iclass 28, count 2 2006.173.09:15:55.58#ibcon#end of sib2, iclass 28, count 2 2006.173.09:15:55.58#ibcon#*mode == 0, iclass 28, count 2 2006.173.09:15:55.58#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.09:15:55.58#ibcon#[27=AT03-04\r\n] 2006.173.09:15:55.58#ibcon#*before write, iclass 28, count 2 2006.173.09:15:55.58#ibcon#enter sib2, iclass 28, count 2 2006.173.09:15:55.58#ibcon#flushed, iclass 28, count 2 2006.173.09:15:55.58#ibcon#about to write, iclass 28, count 2 2006.173.09:15:55.58#ibcon#wrote, iclass 28, count 2 2006.173.09:15:55.58#ibcon#about to read 3, iclass 28, count 2 2006.173.09:15:55.61#ibcon#read 3, iclass 28, count 2 2006.173.09:15:55.61#ibcon#about to read 4, iclass 28, count 2 2006.173.09:15:55.61#ibcon#read 4, iclass 28, count 2 2006.173.09:15:55.61#ibcon#about to read 5, iclass 28, count 2 2006.173.09:15:55.61#ibcon#read 5, iclass 28, count 2 2006.173.09:15:55.61#ibcon#about to read 6, iclass 28, count 2 2006.173.09:15:55.61#ibcon#read 6, iclass 28, count 2 2006.173.09:15:55.61#ibcon#end of sib2, iclass 28, count 2 2006.173.09:15:55.61#ibcon#*after write, iclass 28, count 2 2006.173.09:15:55.61#ibcon#*before return 0, iclass 28, count 2 2006.173.09:15:55.61#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.09:15:55.61#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.09:15:55.61#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.09:15:55.61#ibcon#ireg 7 cls_cnt 0 2006.173.09:15:55.61#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.09:15:55.66#abcon#<5=/16 0.4 0.8 22.98 881004.4\r\n> 2006.173.09:15:55.68#abcon#{5=INTERFACE CLEAR} 2006.173.09:15:55.73#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.09:15:55.73#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.09:15:55.73#ibcon#enter wrdev, iclass 28, count 0 2006.173.09:15:55.73#ibcon#first serial, iclass 28, count 0 2006.173.09:15:55.73#ibcon#enter sib2, iclass 28, count 0 2006.173.09:15:55.73#ibcon#flushed, iclass 28, count 0 2006.173.09:15:55.73#ibcon#about to write, iclass 28, count 0 2006.173.09:15:55.73#ibcon#wrote, iclass 28, count 0 2006.173.09:15:55.73#ibcon#about to read 3, iclass 28, count 0 2006.173.09:15:55.74#abcon#[5=S1D000X0/0*\r\n] 2006.173.09:15:55.75#ibcon#read 3, iclass 28, count 0 2006.173.09:15:55.75#ibcon#about to read 4, iclass 28, count 0 2006.173.09:15:55.75#ibcon#read 4, iclass 28, count 0 2006.173.09:15:55.75#ibcon#about to read 5, iclass 28, count 0 2006.173.09:15:55.75#ibcon#read 5, iclass 28, count 0 2006.173.09:15:55.75#ibcon#about to read 6, iclass 28, count 0 2006.173.09:15:55.75#ibcon#read 6, iclass 28, count 0 2006.173.09:15:55.75#ibcon#end of sib2, iclass 28, count 0 2006.173.09:15:55.75#ibcon#*mode == 0, iclass 28, count 0 2006.173.09:15:55.75#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.09:15:55.75#ibcon#[27=USB\r\n] 2006.173.09:15:55.75#ibcon#*before write, iclass 28, count 0 2006.173.09:15:55.75#ibcon#enter sib2, iclass 28, count 0 2006.173.09:15:55.75#ibcon#flushed, iclass 28, count 0 2006.173.09:15:55.75#ibcon#about to write, iclass 28, count 0 2006.173.09:15:55.75#ibcon#wrote, iclass 28, count 0 2006.173.09:15:55.75#ibcon#about to read 3, iclass 28, count 0 2006.173.09:15:55.78#ibcon#read 3, iclass 28, count 0 2006.173.09:15:55.78#ibcon#about to read 4, iclass 28, count 0 2006.173.09:15:55.78#ibcon#read 4, iclass 28, count 0 2006.173.09:15:55.78#ibcon#about to read 5, iclass 28, count 0 2006.173.09:15:55.78#ibcon#read 5, iclass 28, count 0 2006.173.09:15:55.78#ibcon#about to read 6, iclass 28, count 0 2006.173.09:15:55.78#ibcon#read 6, iclass 28, count 0 2006.173.09:15:55.78#ibcon#end of sib2, iclass 28, count 0 2006.173.09:15:55.78#ibcon#*after write, iclass 28, count 0 2006.173.09:15:55.78#ibcon#*before return 0, iclass 28, count 0 2006.173.09:15:55.78#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.09:15:55.78#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.09:15:55.78#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.09:15:55.78#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.09:15:55.78$vck44/vblo=4,679.99 2006.173.09:15:55.78#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.09:15:55.78#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.09:15:55.78#ibcon#ireg 17 cls_cnt 0 2006.173.09:15:55.78#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.09:15:55.78#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.09:15:55.78#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.09:15:55.78#ibcon#enter wrdev, iclass 34, count 0 2006.173.09:15:55.78#ibcon#first serial, iclass 34, count 0 2006.173.09:15:55.78#ibcon#enter sib2, iclass 34, count 0 2006.173.09:15:55.78#ibcon#flushed, iclass 34, count 0 2006.173.09:15:55.78#ibcon#about to write, iclass 34, count 0 2006.173.09:15:55.78#ibcon#wrote, iclass 34, count 0 2006.173.09:15:55.78#ibcon#about to read 3, iclass 34, count 0 2006.173.09:15:55.80#ibcon#read 3, iclass 34, count 0 2006.173.09:15:55.80#ibcon#about to read 4, iclass 34, count 0 2006.173.09:15:55.80#ibcon#read 4, iclass 34, count 0 2006.173.09:15:55.80#ibcon#about to read 5, iclass 34, count 0 2006.173.09:15:55.80#ibcon#read 5, iclass 34, count 0 2006.173.09:15:55.80#ibcon#about to read 6, iclass 34, count 0 2006.173.09:15:55.80#ibcon#read 6, iclass 34, count 0 2006.173.09:15:55.80#ibcon#end of sib2, iclass 34, count 0 2006.173.09:15:55.80#ibcon#*mode == 0, iclass 34, count 0 2006.173.09:15:55.80#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.09:15:55.80#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.09:15:55.80#ibcon#*before write, iclass 34, count 0 2006.173.09:15:55.80#ibcon#enter sib2, iclass 34, count 0 2006.173.09:15:55.80#ibcon#flushed, iclass 34, count 0 2006.173.09:15:55.80#ibcon#about to write, iclass 34, count 0 2006.173.09:15:55.80#ibcon#wrote, iclass 34, count 0 2006.173.09:15:55.80#ibcon#about to read 3, iclass 34, count 0 2006.173.09:15:55.84#ibcon#read 3, iclass 34, count 0 2006.173.09:15:55.84#ibcon#about to read 4, iclass 34, count 0 2006.173.09:15:55.84#ibcon#read 4, iclass 34, count 0 2006.173.09:15:55.84#ibcon#about to read 5, iclass 34, count 0 2006.173.09:15:55.84#ibcon#read 5, iclass 34, count 0 2006.173.09:15:55.84#ibcon#about to read 6, iclass 34, count 0 2006.173.09:15:55.84#ibcon#read 6, iclass 34, count 0 2006.173.09:15:55.84#ibcon#end of sib2, iclass 34, count 0 2006.173.09:15:55.84#ibcon#*after write, iclass 34, count 0 2006.173.09:15:55.84#ibcon#*before return 0, iclass 34, count 0 2006.173.09:15:55.84#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.09:15:55.84#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.09:15:55.84#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.09:15:55.84#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.09:15:55.84$vck44/vb=4,4 2006.173.09:15:55.84#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.09:15:55.84#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.09:15:55.84#ibcon#ireg 11 cls_cnt 2 2006.173.09:15:55.84#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.09:15:55.90#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.09:15:55.90#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.09:15:55.90#ibcon#enter wrdev, iclass 36, count 2 2006.173.09:15:55.90#ibcon#first serial, iclass 36, count 2 2006.173.09:15:55.90#ibcon#enter sib2, iclass 36, count 2 2006.173.09:15:55.90#ibcon#flushed, iclass 36, count 2 2006.173.09:15:55.90#ibcon#about to write, iclass 36, count 2 2006.173.09:15:55.90#ibcon#wrote, iclass 36, count 2 2006.173.09:15:55.90#ibcon#about to read 3, iclass 36, count 2 2006.173.09:15:55.92#ibcon#read 3, iclass 36, count 2 2006.173.09:15:55.92#ibcon#about to read 4, iclass 36, count 2 2006.173.09:15:55.92#ibcon#read 4, iclass 36, count 2 2006.173.09:15:55.92#ibcon#about to read 5, iclass 36, count 2 2006.173.09:15:55.92#ibcon#read 5, iclass 36, count 2 2006.173.09:15:55.92#ibcon#about to read 6, iclass 36, count 2 2006.173.09:15:55.92#ibcon#read 6, iclass 36, count 2 2006.173.09:15:55.92#ibcon#end of sib2, iclass 36, count 2 2006.173.09:15:55.92#ibcon#*mode == 0, iclass 36, count 2 2006.173.09:15:55.92#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.09:15:55.92#ibcon#[27=AT04-04\r\n] 2006.173.09:15:55.92#ibcon#*before write, iclass 36, count 2 2006.173.09:15:55.92#ibcon#enter sib2, iclass 36, count 2 2006.173.09:15:55.92#ibcon#flushed, iclass 36, count 2 2006.173.09:15:55.92#ibcon#about to write, iclass 36, count 2 2006.173.09:15:55.92#ibcon#wrote, iclass 36, count 2 2006.173.09:15:55.92#ibcon#about to read 3, iclass 36, count 2 2006.173.09:15:55.95#ibcon#read 3, iclass 36, count 2 2006.173.09:15:55.95#ibcon#about to read 4, iclass 36, count 2 2006.173.09:15:55.95#ibcon#read 4, iclass 36, count 2 2006.173.09:15:55.95#ibcon#about to read 5, iclass 36, count 2 2006.173.09:15:55.95#ibcon#read 5, iclass 36, count 2 2006.173.09:15:55.95#ibcon#about to read 6, iclass 36, count 2 2006.173.09:15:55.95#ibcon#read 6, iclass 36, count 2 2006.173.09:15:55.95#ibcon#end of sib2, iclass 36, count 2 2006.173.09:15:55.95#ibcon#*after write, iclass 36, count 2 2006.173.09:15:55.95#ibcon#*before return 0, iclass 36, count 2 2006.173.09:15:55.95#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.09:15:55.95#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.09:15:55.95#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.09:15:55.95#ibcon#ireg 7 cls_cnt 0 2006.173.09:15:55.95#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.09:15:56.07#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.09:15:56.07#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.09:15:56.07#ibcon#enter wrdev, iclass 36, count 0 2006.173.09:15:56.07#ibcon#first serial, iclass 36, count 0 2006.173.09:15:56.07#ibcon#enter sib2, iclass 36, count 0 2006.173.09:15:56.07#ibcon#flushed, iclass 36, count 0 2006.173.09:15:56.07#ibcon#about to write, iclass 36, count 0 2006.173.09:15:56.07#ibcon#wrote, iclass 36, count 0 2006.173.09:15:56.07#ibcon#about to read 3, iclass 36, count 0 2006.173.09:15:56.09#ibcon#read 3, iclass 36, count 0 2006.173.09:15:56.09#ibcon#about to read 4, iclass 36, count 0 2006.173.09:15:56.09#ibcon#read 4, iclass 36, count 0 2006.173.09:15:56.09#ibcon#about to read 5, iclass 36, count 0 2006.173.09:15:56.09#ibcon#read 5, iclass 36, count 0 2006.173.09:15:56.09#ibcon#about to read 6, iclass 36, count 0 2006.173.09:15:56.09#ibcon#read 6, iclass 36, count 0 2006.173.09:15:56.09#ibcon#end of sib2, iclass 36, count 0 2006.173.09:15:56.09#ibcon#*mode == 0, iclass 36, count 0 2006.173.09:15:56.09#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.09:15:56.09#ibcon#[27=USB\r\n] 2006.173.09:15:56.09#ibcon#*before write, iclass 36, count 0 2006.173.09:15:56.09#ibcon#enter sib2, iclass 36, count 0 2006.173.09:15:56.09#ibcon#flushed, iclass 36, count 0 2006.173.09:15:56.09#ibcon#about to write, iclass 36, count 0 2006.173.09:15:56.09#ibcon#wrote, iclass 36, count 0 2006.173.09:15:56.09#ibcon#about to read 3, iclass 36, count 0 2006.173.09:15:56.12#ibcon#read 3, iclass 36, count 0 2006.173.09:15:56.12#ibcon#about to read 4, iclass 36, count 0 2006.173.09:15:56.12#ibcon#read 4, iclass 36, count 0 2006.173.09:15:56.12#ibcon#about to read 5, iclass 36, count 0 2006.173.09:15:56.12#ibcon#read 5, iclass 36, count 0 2006.173.09:15:56.12#ibcon#about to read 6, iclass 36, count 0 2006.173.09:15:56.12#ibcon#read 6, iclass 36, count 0 2006.173.09:15:56.12#ibcon#end of sib2, iclass 36, count 0 2006.173.09:15:56.12#ibcon#*after write, iclass 36, count 0 2006.173.09:15:56.12#ibcon#*before return 0, iclass 36, count 0 2006.173.09:15:56.12#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.09:15:56.12#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.09:15:56.12#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.09:15:56.12#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.09:15:56.12$vck44/vblo=5,709.99 2006.173.09:15:56.12#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.09:15:56.12#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.09:15:56.12#ibcon#ireg 17 cls_cnt 0 2006.173.09:15:56.12#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.09:15:56.12#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.09:15:56.12#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.09:15:56.12#ibcon#enter wrdev, iclass 38, count 0 2006.173.09:15:56.12#ibcon#first serial, iclass 38, count 0 2006.173.09:15:56.12#ibcon#enter sib2, iclass 38, count 0 2006.173.09:15:56.12#ibcon#flushed, iclass 38, count 0 2006.173.09:15:56.12#ibcon#about to write, iclass 38, count 0 2006.173.09:15:56.12#ibcon#wrote, iclass 38, count 0 2006.173.09:15:56.12#ibcon#about to read 3, iclass 38, count 0 2006.173.09:15:56.14#ibcon#read 3, iclass 38, count 0 2006.173.09:15:56.14#ibcon#about to read 4, iclass 38, count 0 2006.173.09:15:56.14#ibcon#read 4, iclass 38, count 0 2006.173.09:15:56.14#ibcon#about to read 5, iclass 38, count 0 2006.173.09:15:56.14#ibcon#read 5, iclass 38, count 0 2006.173.09:15:56.14#ibcon#about to read 6, iclass 38, count 0 2006.173.09:15:56.14#ibcon#read 6, iclass 38, count 0 2006.173.09:15:56.14#ibcon#end of sib2, iclass 38, count 0 2006.173.09:15:56.14#ibcon#*mode == 0, iclass 38, count 0 2006.173.09:15:56.14#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.09:15:56.14#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.09:15:56.14#ibcon#*before write, iclass 38, count 0 2006.173.09:15:56.14#ibcon#enter sib2, iclass 38, count 0 2006.173.09:15:56.14#ibcon#flushed, iclass 38, count 0 2006.173.09:15:56.14#ibcon#about to write, iclass 38, count 0 2006.173.09:15:56.14#ibcon#wrote, iclass 38, count 0 2006.173.09:15:56.14#ibcon#about to read 3, iclass 38, count 0 2006.173.09:15:56.18#ibcon#read 3, iclass 38, count 0 2006.173.09:15:56.18#ibcon#about to read 4, iclass 38, count 0 2006.173.09:15:56.18#ibcon#read 4, iclass 38, count 0 2006.173.09:15:56.18#ibcon#about to read 5, iclass 38, count 0 2006.173.09:15:56.18#ibcon#read 5, iclass 38, count 0 2006.173.09:15:56.18#ibcon#about to read 6, iclass 38, count 0 2006.173.09:15:56.18#ibcon#read 6, iclass 38, count 0 2006.173.09:15:56.18#ibcon#end of sib2, iclass 38, count 0 2006.173.09:15:56.18#ibcon#*after write, iclass 38, count 0 2006.173.09:15:56.18#ibcon#*before return 0, iclass 38, count 0 2006.173.09:15:56.18#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.09:15:56.18#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.09:15:56.18#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.09:15:56.18#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.09:15:56.18$vck44/vb=5,4 2006.173.09:15:56.18#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.09:15:56.18#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.09:15:56.18#ibcon#ireg 11 cls_cnt 2 2006.173.09:15:56.18#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.09:15:56.24#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.09:15:56.24#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.09:15:56.24#ibcon#enter wrdev, iclass 40, count 2 2006.173.09:15:56.24#ibcon#first serial, iclass 40, count 2 2006.173.09:15:56.24#ibcon#enter sib2, iclass 40, count 2 2006.173.09:15:56.24#ibcon#flushed, iclass 40, count 2 2006.173.09:15:56.24#ibcon#about to write, iclass 40, count 2 2006.173.09:15:56.24#ibcon#wrote, iclass 40, count 2 2006.173.09:15:56.24#ibcon#about to read 3, iclass 40, count 2 2006.173.09:15:56.26#ibcon#read 3, iclass 40, count 2 2006.173.09:15:56.26#ibcon#about to read 4, iclass 40, count 2 2006.173.09:15:56.26#ibcon#read 4, iclass 40, count 2 2006.173.09:15:56.26#ibcon#about to read 5, iclass 40, count 2 2006.173.09:15:56.26#ibcon#read 5, iclass 40, count 2 2006.173.09:15:56.26#ibcon#about to read 6, iclass 40, count 2 2006.173.09:15:56.26#ibcon#read 6, iclass 40, count 2 2006.173.09:15:56.26#ibcon#end of sib2, iclass 40, count 2 2006.173.09:15:56.26#ibcon#*mode == 0, iclass 40, count 2 2006.173.09:15:56.26#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.09:15:56.26#ibcon#[27=AT05-04\r\n] 2006.173.09:15:56.26#ibcon#*before write, iclass 40, count 2 2006.173.09:15:56.26#ibcon#enter sib2, iclass 40, count 2 2006.173.09:15:56.26#ibcon#flushed, iclass 40, count 2 2006.173.09:15:56.26#ibcon#about to write, iclass 40, count 2 2006.173.09:15:56.26#ibcon#wrote, iclass 40, count 2 2006.173.09:15:56.26#ibcon#about to read 3, iclass 40, count 2 2006.173.09:15:56.29#ibcon#read 3, iclass 40, count 2 2006.173.09:15:56.29#ibcon#about to read 4, iclass 40, count 2 2006.173.09:15:56.29#ibcon#read 4, iclass 40, count 2 2006.173.09:15:56.29#ibcon#about to read 5, iclass 40, count 2 2006.173.09:15:56.29#ibcon#read 5, iclass 40, count 2 2006.173.09:15:56.29#ibcon#about to read 6, iclass 40, count 2 2006.173.09:15:56.29#ibcon#read 6, iclass 40, count 2 2006.173.09:15:56.29#ibcon#end of sib2, iclass 40, count 2 2006.173.09:15:56.29#ibcon#*after write, iclass 40, count 2 2006.173.09:15:56.29#ibcon#*before return 0, iclass 40, count 2 2006.173.09:15:56.29#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.09:15:56.29#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.09:15:56.29#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.09:15:56.29#ibcon#ireg 7 cls_cnt 0 2006.173.09:15:56.29#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.09:15:56.41#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.09:15:56.41#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.09:15:56.41#ibcon#enter wrdev, iclass 40, count 0 2006.173.09:15:56.41#ibcon#first serial, iclass 40, count 0 2006.173.09:15:56.41#ibcon#enter sib2, iclass 40, count 0 2006.173.09:15:56.41#ibcon#flushed, iclass 40, count 0 2006.173.09:15:56.41#ibcon#about to write, iclass 40, count 0 2006.173.09:15:56.41#ibcon#wrote, iclass 40, count 0 2006.173.09:15:56.41#ibcon#about to read 3, iclass 40, count 0 2006.173.09:15:56.43#ibcon#read 3, iclass 40, count 0 2006.173.09:15:56.43#ibcon#about to read 4, iclass 40, count 0 2006.173.09:15:56.43#ibcon#read 4, iclass 40, count 0 2006.173.09:15:56.43#ibcon#about to read 5, iclass 40, count 0 2006.173.09:15:56.43#ibcon#read 5, iclass 40, count 0 2006.173.09:15:56.43#ibcon#about to read 6, iclass 40, count 0 2006.173.09:15:56.43#ibcon#read 6, iclass 40, count 0 2006.173.09:15:56.43#ibcon#end of sib2, iclass 40, count 0 2006.173.09:15:56.43#ibcon#*mode == 0, iclass 40, count 0 2006.173.09:15:56.43#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.09:15:56.43#ibcon#[27=USB\r\n] 2006.173.09:15:56.43#ibcon#*before write, iclass 40, count 0 2006.173.09:15:56.43#ibcon#enter sib2, iclass 40, count 0 2006.173.09:15:56.43#ibcon#flushed, iclass 40, count 0 2006.173.09:15:56.43#ibcon#about to write, iclass 40, count 0 2006.173.09:15:56.43#ibcon#wrote, iclass 40, count 0 2006.173.09:15:56.43#ibcon#about to read 3, iclass 40, count 0 2006.173.09:15:56.46#ibcon#read 3, iclass 40, count 0 2006.173.09:15:56.46#ibcon#about to read 4, iclass 40, count 0 2006.173.09:15:56.46#ibcon#read 4, iclass 40, count 0 2006.173.09:15:56.46#ibcon#about to read 5, iclass 40, count 0 2006.173.09:15:56.46#ibcon#read 5, iclass 40, count 0 2006.173.09:15:56.46#ibcon#about to read 6, iclass 40, count 0 2006.173.09:15:56.46#ibcon#read 6, iclass 40, count 0 2006.173.09:15:56.46#ibcon#end of sib2, iclass 40, count 0 2006.173.09:15:56.46#ibcon#*after write, iclass 40, count 0 2006.173.09:15:56.46#ibcon#*before return 0, iclass 40, count 0 2006.173.09:15:56.46#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.09:15:56.46#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.09:15:56.46#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.09:15:56.46#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.09:15:56.46$vck44/vblo=6,719.99 2006.173.09:15:56.46#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.09:15:56.46#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.09:15:56.46#ibcon#ireg 17 cls_cnt 0 2006.173.09:15:56.46#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.09:15:56.46#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.09:15:56.46#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.09:15:56.46#ibcon#enter wrdev, iclass 4, count 0 2006.173.09:15:56.46#ibcon#first serial, iclass 4, count 0 2006.173.09:15:56.46#ibcon#enter sib2, iclass 4, count 0 2006.173.09:15:56.46#ibcon#flushed, iclass 4, count 0 2006.173.09:15:56.46#ibcon#about to write, iclass 4, count 0 2006.173.09:15:56.46#ibcon#wrote, iclass 4, count 0 2006.173.09:15:56.46#ibcon#about to read 3, iclass 4, count 0 2006.173.09:15:56.48#ibcon#read 3, iclass 4, count 0 2006.173.09:15:56.48#ibcon#about to read 4, iclass 4, count 0 2006.173.09:15:56.48#ibcon#read 4, iclass 4, count 0 2006.173.09:15:56.48#ibcon#about to read 5, iclass 4, count 0 2006.173.09:15:56.48#ibcon#read 5, iclass 4, count 0 2006.173.09:15:56.48#ibcon#about to read 6, iclass 4, count 0 2006.173.09:15:56.48#ibcon#read 6, iclass 4, count 0 2006.173.09:15:56.48#ibcon#end of sib2, iclass 4, count 0 2006.173.09:15:56.48#ibcon#*mode == 0, iclass 4, count 0 2006.173.09:15:56.48#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.09:15:56.48#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.09:15:56.48#ibcon#*before write, iclass 4, count 0 2006.173.09:15:56.48#ibcon#enter sib2, iclass 4, count 0 2006.173.09:15:56.48#ibcon#flushed, iclass 4, count 0 2006.173.09:15:56.48#ibcon#about to write, iclass 4, count 0 2006.173.09:15:56.48#ibcon#wrote, iclass 4, count 0 2006.173.09:15:56.48#ibcon#about to read 3, iclass 4, count 0 2006.173.09:15:56.52#ibcon#read 3, iclass 4, count 0 2006.173.09:15:56.52#ibcon#about to read 4, iclass 4, count 0 2006.173.09:15:56.52#ibcon#read 4, iclass 4, count 0 2006.173.09:15:56.52#ibcon#about to read 5, iclass 4, count 0 2006.173.09:15:56.52#ibcon#read 5, iclass 4, count 0 2006.173.09:15:56.52#ibcon#about to read 6, iclass 4, count 0 2006.173.09:15:56.52#ibcon#read 6, iclass 4, count 0 2006.173.09:15:56.52#ibcon#end of sib2, iclass 4, count 0 2006.173.09:15:56.52#ibcon#*after write, iclass 4, count 0 2006.173.09:15:56.52#ibcon#*before return 0, iclass 4, count 0 2006.173.09:15:56.52#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.09:15:56.52#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.09:15:56.52#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.09:15:56.52#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.09:15:56.52$vck44/vb=6,4 2006.173.09:15:56.52#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.09:15:56.52#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.09:15:56.52#ibcon#ireg 11 cls_cnt 2 2006.173.09:15:56.52#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.09:15:56.58#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.09:15:56.58#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.09:15:56.58#ibcon#enter wrdev, iclass 6, count 2 2006.173.09:15:56.58#ibcon#first serial, iclass 6, count 2 2006.173.09:15:56.58#ibcon#enter sib2, iclass 6, count 2 2006.173.09:15:56.58#ibcon#flushed, iclass 6, count 2 2006.173.09:15:56.58#ibcon#about to write, iclass 6, count 2 2006.173.09:15:56.58#ibcon#wrote, iclass 6, count 2 2006.173.09:15:56.58#ibcon#about to read 3, iclass 6, count 2 2006.173.09:15:56.60#ibcon#read 3, iclass 6, count 2 2006.173.09:15:56.60#ibcon#about to read 4, iclass 6, count 2 2006.173.09:15:56.60#ibcon#read 4, iclass 6, count 2 2006.173.09:15:56.60#ibcon#about to read 5, iclass 6, count 2 2006.173.09:15:56.60#ibcon#read 5, iclass 6, count 2 2006.173.09:15:56.60#ibcon#about to read 6, iclass 6, count 2 2006.173.09:15:56.60#ibcon#read 6, iclass 6, count 2 2006.173.09:15:56.60#ibcon#end of sib2, iclass 6, count 2 2006.173.09:15:56.60#ibcon#*mode == 0, iclass 6, count 2 2006.173.09:15:56.60#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.09:15:56.60#ibcon#[27=AT06-04\r\n] 2006.173.09:15:56.60#ibcon#*before write, iclass 6, count 2 2006.173.09:15:56.60#ibcon#enter sib2, iclass 6, count 2 2006.173.09:15:56.60#ibcon#flushed, iclass 6, count 2 2006.173.09:15:56.60#ibcon#about to write, iclass 6, count 2 2006.173.09:15:56.60#ibcon#wrote, iclass 6, count 2 2006.173.09:15:56.60#ibcon#about to read 3, iclass 6, count 2 2006.173.09:15:56.63#ibcon#read 3, iclass 6, count 2 2006.173.09:15:56.63#ibcon#about to read 4, iclass 6, count 2 2006.173.09:15:56.63#ibcon#read 4, iclass 6, count 2 2006.173.09:15:56.63#ibcon#about to read 5, iclass 6, count 2 2006.173.09:15:56.63#ibcon#read 5, iclass 6, count 2 2006.173.09:15:56.63#ibcon#about to read 6, iclass 6, count 2 2006.173.09:15:56.63#ibcon#read 6, iclass 6, count 2 2006.173.09:15:56.63#ibcon#end of sib2, iclass 6, count 2 2006.173.09:15:56.63#ibcon#*after write, iclass 6, count 2 2006.173.09:15:56.63#ibcon#*before return 0, iclass 6, count 2 2006.173.09:15:56.63#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.09:15:56.63#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.09:15:56.63#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.09:15:56.63#ibcon#ireg 7 cls_cnt 0 2006.173.09:15:56.63#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.09:15:56.75#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.09:15:56.75#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.09:15:56.75#ibcon#enter wrdev, iclass 6, count 0 2006.173.09:15:56.75#ibcon#first serial, iclass 6, count 0 2006.173.09:15:56.75#ibcon#enter sib2, iclass 6, count 0 2006.173.09:15:56.75#ibcon#flushed, iclass 6, count 0 2006.173.09:15:56.75#ibcon#about to write, iclass 6, count 0 2006.173.09:15:56.75#ibcon#wrote, iclass 6, count 0 2006.173.09:15:56.75#ibcon#about to read 3, iclass 6, count 0 2006.173.09:15:56.77#ibcon#read 3, iclass 6, count 0 2006.173.09:15:56.77#ibcon#about to read 4, iclass 6, count 0 2006.173.09:15:56.77#ibcon#read 4, iclass 6, count 0 2006.173.09:15:56.77#ibcon#about to read 5, iclass 6, count 0 2006.173.09:15:56.77#ibcon#read 5, iclass 6, count 0 2006.173.09:15:56.77#ibcon#about to read 6, iclass 6, count 0 2006.173.09:15:56.77#ibcon#read 6, iclass 6, count 0 2006.173.09:15:56.77#ibcon#end of sib2, iclass 6, count 0 2006.173.09:15:56.77#ibcon#*mode == 0, iclass 6, count 0 2006.173.09:15:56.77#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.09:15:56.77#ibcon#[27=USB\r\n] 2006.173.09:15:56.77#ibcon#*before write, iclass 6, count 0 2006.173.09:15:56.77#ibcon#enter sib2, iclass 6, count 0 2006.173.09:15:56.77#ibcon#flushed, iclass 6, count 0 2006.173.09:15:56.77#ibcon#about to write, iclass 6, count 0 2006.173.09:15:56.77#ibcon#wrote, iclass 6, count 0 2006.173.09:15:56.77#ibcon#about to read 3, iclass 6, count 0 2006.173.09:15:56.80#ibcon#read 3, iclass 6, count 0 2006.173.09:15:56.80#ibcon#about to read 4, iclass 6, count 0 2006.173.09:15:56.80#ibcon#read 4, iclass 6, count 0 2006.173.09:15:56.80#ibcon#about to read 5, iclass 6, count 0 2006.173.09:15:56.80#ibcon#read 5, iclass 6, count 0 2006.173.09:15:56.80#ibcon#about to read 6, iclass 6, count 0 2006.173.09:15:56.80#ibcon#read 6, iclass 6, count 0 2006.173.09:15:56.80#ibcon#end of sib2, iclass 6, count 0 2006.173.09:15:56.80#ibcon#*after write, iclass 6, count 0 2006.173.09:15:56.80#ibcon#*before return 0, iclass 6, count 0 2006.173.09:15:56.80#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.09:15:56.80#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.09:15:56.80#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.09:15:56.80#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.09:15:56.80$vck44/vblo=7,734.99 2006.173.09:15:56.80#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.09:15:56.80#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.09:15:56.80#ibcon#ireg 17 cls_cnt 0 2006.173.09:15:56.80#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.09:15:56.80#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.09:15:56.80#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.09:15:56.80#ibcon#enter wrdev, iclass 10, count 0 2006.173.09:15:56.80#ibcon#first serial, iclass 10, count 0 2006.173.09:15:56.80#ibcon#enter sib2, iclass 10, count 0 2006.173.09:15:56.80#ibcon#flushed, iclass 10, count 0 2006.173.09:15:56.80#ibcon#about to write, iclass 10, count 0 2006.173.09:15:56.80#ibcon#wrote, iclass 10, count 0 2006.173.09:15:56.80#ibcon#about to read 3, iclass 10, count 0 2006.173.09:15:56.82#ibcon#read 3, iclass 10, count 0 2006.173.09:15:56.82#ibcon#about to read 4, iclass 10, count 0 2006.173.09:15:56.82#ibcon#read 4, iclass 10, count 0 2006.173.09:15:56.82#ibcon#about to read 5, iclass 10, count 0 2006.173.09:15:56.82#ibcon#read 5, iclass 10, count 0 2006.173.09:15:56.82#ibcon#about to read 6, iclass 10, count 0 2006.173.09:15:56.82#ibcon#read 6, iclass 10, count 0 2006.173.09:15:56.82#ibcon#end of sib2, iclass 10, count 0 2006.173.09:15:56.82#ibcon#*mode == 0, iclass 10, count 0 2006.173.09:15:56.82#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.09:15:56.82#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.09:15:56.82#ibcon#*before write, iclass 10, count 0 2006.173.09:15:56.82#ibcon#enter sib2, iclass 10, count 0 2006.173.09:15:56.82#ibcon#flushed, iclass 10, count 0 2006.173.09:15:56.82#ibcon#about to write, iclass 10, count 0 2006.173.09:15:56.82#ibcon#wrote, iclass 10, count 0 2006.173.09:15:56.82#ibcon#about to read 3, iclass 10, count 0 2006.173.09:15:56.86#ibcon#read 3, iclass 10, count 0 2006.173.09:15:56.86#ibcon#about to read 4, iclass 10, count 0 2006.173.09:15:56.86#ibcon#read 4, iclass 10, count 0 2006.173.09:15:56.86#ibcon#about to read 5, iclass 10, count 0 2006.173.09:15:56.86#ibcon#read 5, iclass 10, count 0 2006.173.09:15:56.86#ibcon#about to read 6, iclass 10, count 0 2006.173.09:15:56.86#ibcon#read 6, iclass 10, count 0 2006.173.09:15:56.86#ibcon#end of sib2, iclass 10, count 0 2006.173.09:15:56.86#ibcon#*after write, iclass 10, count 0 2006.173.09:15:56.86#ibcon#*before return 0, iclass 10, count 0 2006.173.09:15:56.86#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.09:15:56.86#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.09:15:56.86#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.09:15:56.86#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.09:15:56.86$vck44/vb=7,4 2006.173.09:15:56.86#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.09:15:56.86#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.09:15:56.86#ibcon#ireg 11 cls_cnt 2 2006.173.09:15:56.86#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.09:15:56.92#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.09:15:56.92#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.09:15:56.92#ibcon#enter wrdev, iclass 12, count 2 2006.173.09:15:56.92#ibcon#first serial, iclass 12, count 2 2006.173.09:15:56.92#ibcon#enter sib2, iclass 12, count 2 2006.173.09:15:56.92#ibcon#flushed, iclass 12, count 2 2006.173.09:15:56.92#ibcon#about to write, iclass 12, count 2 2006.173.09:15:56.92#ibcon#wrote, iclass 12, count 2 2006.173.09:15:56.92#ibcon#about to read 3, iclass 12, count 2 2006.173.09:15:56.94#ibcon#read 3, iclass 12, count 2 2006.173.09:15:56.94#ibcon#about to read 4, iclass 12, count 2 2006.173.09:15:56.94#ibcon#read 4, iclass 12, count 2 2006.173.09:15:56.94#ibcon#about to read 5, iclass 12, count 2 2006.173.09:15:56.94#ibcon#read 5, iclass 12, count 2 2006.173.09:15:56.94#ibcon#about to read 6, iclass 12, count 2 2006.173.09:15:56.94#ibcon#read 6, iclass 12, count 2 2006.173.09:15:56.94#ibcon#end of sib2, iclass 12, count 2 2006.173.09:15:56.94#ibcon#*mode == 0, iclass 12, count 2 2006.173.09:15:56.94#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.09:15:56.94#ibcon#[27=AT07-04\r\n] 2006.173.09:15:56.94#ibcon#*before write, iclass 12, count 2 2006.173.09:15:56.94#ibcon#enter sib2, iclass 12, count 2 2006.173.09:15:56.94#ibcon#flushed, iclass 12, count 2 2006.173.09:15:56.94#ibcon#about to write, iclass 12, count 2 2006.173.09:15:56.94#ibcon#wrote, iclass 12, count 2 2006.173.09:15:56.94#ibcon#about to read 3, iclass 12, count 2 2006.173.09:15:56.97#ibcon#read 3, iclass 12, count 2 2006.173.09:15:56.97#ibcon#about to read 4, iclass 12, count 2 2006.173.09:15:56.97#ibcon#read 4, iclass 12, count 2 2006.173.09:15:56.97#ibcon#about to read 5, iclass 12, count 2 2006.173.09:15:56.97#ibcon#read 5, iclass 12, count 2 2006.173.09:15:56.97#ibcon#about to read 6, iclass 12, count 2 2006.173.09:15:56.97#ibcon#read 6, iclass 12, count 2 2006.173.09:15:56.97#ibcon#end of sib2, iclass 12, count 2 2006.173.09:15:56.97#ibcon#*after write, iclass 12, count 2 2006.173.09:15:56.97#ibcon#*before return 0, iclass 12, count 2 2006.173.09:15:56.97#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.09:15:56.97#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.09:15:56.97#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.09:15:56.97#ibcon#ireg 7 cls_cnt 0 2006.173.09:15:56.97#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.09:15:57.09#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.09:15:57.09#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.09:15:57.09#ibcon#enter wrdev, iclass 12, count 0 2006.173.09:15:57.09#ibcon#first serial, iclass 12, count 0 2006.173.09:15:57.09#ibcon#enter sib2, iclass 12, count 0 2006.173.09:15:57.09#ibcon#flushed, iclass 12, count 0 2006.173.09:15:57.09#ibcon#about to write, iclass 12, count 0 2006.173.09:15:57.09#ibcon#wrote, iclass 12, count 0 2006.173.09:15:57.09#ibcon#about to read 3, iclass 12, count 0 2006.173.09:15:57.11#ibcon#read 3, iclass 12, count 0 2006.173.09:15:57.11#ibcon#about to read 4, iclass 12, count 0 2006.173.09:15:57.11#ibcon#read 4, iclass 12, count 0 2006.173.09:15:57.11#ibcon#about to read 5, iclass 12, count 0 2006.173.09:15:57.11#ibcon#read 5, iclass 12, count 0 2006.173.09:15:57.11#ibcon#about to read 6, iclass 12, count 0 2006.173.09:15:57.11#ibcon#read 6, iclass 12, count 0 2006.173.09:15:57.11#ibcon#end of sib2, iclass 12, count 0 2006.173.09:15:57.11#ibcon#*mode == 0, iclass 12, count 0 2006.173.09:15:57.11#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.09:15:57.11#ibcon#[27=USB\r\n] 2006.173.09:15:57.11#ibcon#*before write, iclass 12, count 0 2006.173.09:15:57.11#ibcon#enter sib2, iclass 12, count 0 2006.173.09:15:57.11#ibcon#flushed, iclass 12, count 0 2006.173.09:15:57.11#ibcon#about to write, iclass 12, count 0 2006.173.09:15:57.11#ibcon#wrote, iclass 12, count 0 2006.173.09:15:57.11#ibcon#about to read 3, iclass 12, count 0 2006.173.09:15:57.14#ibcon#read 3, iclass 12, count 0 2006.173.09:15:57.14#ibcon#about to read 4, iclass 12, count 0 2006.173.09:15:57.14#ibcon#read 4, iclass 12, count 0 2006.173.09:15:57.14#ibcon#about to read 5, iclass 12, count 0 2006.173.09:15:57.14#ibcon#read 5, iclass 12, count 0 2006.173.09:15:57.14#ibcon#about to read 6, iclass 12, count 0 2006.173.09:15:57.14#ibcon#read 6, iclass 12, count 0 2006.173.09:15:57.14#ibcon#end of sib2, iclass 12, count 0 2006.173.09:15:57.14#ibcon#*after write, iclass 12, count 0 2006.173.09:15:57.14#ibcon#*before return 0, iclass 12, count 0 2006.173.09:15:57.14#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.09:15:57.14#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.09:15:57.14#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.09:15:57.14#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.09:15:57.14$vck44/vblo=8,744.99 2006.173.09:15:57.14#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.09:15:57.14#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.09:15:57.14#ibcon#ireg 17 cls_cnt 0 2006.173.09:15:57.14#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.09:15:57.14#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.09:15:57.14#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.09:15:57.14#ibcon#enter wrdev, iclass 14, count 0 2006.173.09:15:57.14#ibcon#first serial, iclass 14, count 0 2006.173.09:15:57.14#ibcon#enter sib2, iclass 14, count 0 2006.173.09:15:57.14#ibcon#flushed, iclass 14, count 0 2006.173.09:15:57.14#ibcon#about to write, iclass 14, count 0 2006.173.09:15:57.14#ibcon#wrote, iclass 14, count 0 2006.173.09:15:57.14#ibcon#about to read 3, iclass 14, count 0 2006.173.09:15:57.16#ibcon#read 3, iclass 14, count 0 2006.173.09:15:57.16#ibcon#about to read 4, iclass 14, count 0 2006.173.09:15:57.16#ibcon#read 4, iclass 14, count 0 2006.173.09:15:57.16#ibcon#about to read 5, iclass 14, count 0 2006.173.09:15:57.16#ibcon#read 5, iclass 14, count 0 2006.173.09:15:57.16#ibcon#about to read 6, iclass 14, count 0 2006.173.09:15:57.16#ibcon#read 6, iclass 14, count 0 2006.173.09:15:57.16#ibcon#end of sib2, iclass 14, count 0 2006.173.09:15:57.16#ibcon#*mode == 0, iclass 14, count 0 2006.173.09:15:57.16#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.09:15:57.16#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.09:15:57.16#ibcon#*before write, iclass 14, count 0 2006.173.09:15:57.16#ibcon#enter sib2, iclass 14, count 0 2006.173.09:15:57.16#ibcon#flushed, iclass 14, count 0 2006.173.09:15:57.16#ibcon#about to write, iclass 14, count 0 2006.173.09:15:57.16#ibcon#wrote, iclass 14, count 0 2006.173.09:15:57.16#ibcon#about to read 3, iclass 14, count 0 2006.173.09:15:57.20#ibcon#read 3, iclass 14, count 0 2006.173.09:15:57.20#ibcon#about to read 4, iclass 14, count 0 2006.173.09:15:57.20#ibcon#read 4, iclass 14, count 0 2006.173.09:15:57.20#ibcon#about to read 5, iclass 14, count 0 2006.173.09:15:57.20#ibcon#read 5, iclass 14, count 0 2006.173.09:15:57.20#ibcon#about to read 6, iclass 14, count 0 2006.173.09:15:57.20#ibcon#read 6, iclass 14, count 0 2006.173.09:15:57.20#ibcon#end of sib2, iclass 14, count 0 2006.173.09:15:57.20#ibcon#*after write, iclass 14, count 0 2006.173.09:15:57.20#ibcon#*before return 0, iclass 14, count 0 2006.173.09:15:57.20#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.09:15:57.20#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.09:15:57.20#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.09:15:57.20#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.09:15:57.20$vck44/vb=8,4 2006.173.09:15:57.20#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.09:15:57.20#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.09:15:57.20#ibcon#ireg 11 cls_cnt 2 2006.173.09:15:57.20#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.09:15:57.26#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.09:15:57.26#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.09:15:57.26#ibcon#enter wrdev, iclass 16, count 2 2006.173.09:15:57.26#ibcon#first serial, iclass 16, count 2 2006.173.09:15:57.26#ibcon#enter sib2, iclass 16, count 2 2006.173.09:15:57.26#ibcon#flushed, iclass 16, count 2 2006.173.09:15:57.26#ibcon#about to write, iclass 16, count 2 2006.173.09:15:57.26#ibcon#wrote, iclass 16, count 2 2006.173.09:15:57.26#ibcon#about to read 3, iclass 16, count 2 2006.173.09:15:57.28#ibcon#read 3, iclass 16, count 2 2006.173.09:15:57.28#ibcon#about to read 4, iclass 16, count 2 2006.173.09:15:57.28#ibcon#read 4, iclass 16, count 2 2006.173.09:15:57.28#ibcon#about to read 5, iclass 16, count 2 2006.173.09:15:57.28#ibcon#read 5, iclass 16, count 2 2006.173.09:15:57.28#ibcon#about to read 6, iclass 16, count 2 2006.173.09:15:57.28#ibcon#read 6, iclass 16, count 2 2006.173.09:15:57.28#ibcon#end of sib2, iclass 16, count 2 2006.173.09:15:57.28#ibcon#*mode == 0, iclass 16, count 2 2006.173.09:15:57.28#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.09:15:57.28#ibcon#[27=AT08-04\r\n] 2006.173.09:15:57.28#ibcon#*before write, iclass 16, count 2 2006.173.09:15:57.28#ibcon#enter sib2, iclass 16, count 2 2006.173.09:15:57.28#ibcon#flushed, iclass 16, count 2 2006.173.09:15:57.28#ibcon#about to write, iclass 16, count 2 2006.173.09:15:57.28#ibcon#wrote, iclass 16, count 2 2006.173.09:15:57.28#ibcon#about to read 3, iclass 16, count 2 2006.173.09:15:57.31#ibcon#read 3, iclass 16, count 2 2006.173.09:15:57.31#ibcon#about to read 4, iclass 16, count 2 2006.173.09:15:57.31#ibcon#read 4, iclass 16, count 2 2006.173.09:15:57.31#ibcon#about to read 5, iclass 16, count 2 2006.173.09:15:57.31#ibcon#read 5, iclass 16, count 2 2006.173.09:15:57.31#ibcon#about to read 6, iclass 16, count 2 2006.173.09:15:57.31#ibcon#read 6, iclass 16, count 2 2006.173.09:15:57.31#ibcon#end of sib2, iclass 16, count 2 2006.173.09:15:57.31#ibcon#*after write, iclass 16, count 2 2006.173.09:15:57.31#ibcon#*before return 0, iclass 16, count 2 2006.173.09:15:57.31#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.09:15:57.31#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.09:15:57.31#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.09:15:57.31#ibcon#ireg 7 cls_cnt 0 2006.173.09:15:57.31#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.09:15:57.43#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.09:15:57.43#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.09:15:57.43#ibcon#enter wrdev, iclass 16, count 0 2006.173.09:15:57.43#ibcon#first serial, iclass 16, count 0 2006.173.09:15:57.43#ibcon#enter sib2, iclass 16, count 0 2006.173.09:15:57.43#ibcon#flushed, iclass 16, count 0 2006.173.09:15:57.43#ibcon#about to write, iclass 16, count 0 2006.173.09:15:57.43#ibcon#wrote, iclass 16, count 0 2006.173.09:15:57.43#ibcon#about to read 3, iclass 16, count 0 2006.173.09:15:57.45#ibcon#read 3, iclass 16, count 0 2006.173.09:15:57.45#ibcon#about to read 4, iclass 16, count 0 2006.173.09:15:57.45#ibcon#read 4, iclass 16, count 0 2006.173.09:15:57.45#ibcon#about to read 5, iclass 16, count 0 2006.173.09:15:57.45#ibcon#read 5, iclass 16, count 0 2006.173.09:15:57.45#ibcon#about to read 6, iclass 16, count 0 2006.173.09:15:57.45#ibcon#read 6, iclass 16, count 0 2006.173.09:15:57.45#ibcon#end of sib2, iclass 16, count 0 2006.173.09:15:57.45#ibcon#*mode == 0, iclass 16, count 0 2006.173.09:15:57.45#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.09:15:57.45#ibcon#[27=USB\r\n] 2006.173.09:15:57.45#ibcon#*before write, iclass 16, count 0 2006.173.09:15:57.45#ibcon#enter sib2, iclass 16, count 0 2006.173.09:15:57.45#ibcon#flushed, iclass 16, count 0 2006.173.09:15:57.45#ibcon#about to write, iclass 16, count 0 2006.173.09:15:57.45#ibcon#wrote, iclass 16, count 0 2006.173.09:15:57.45#ibcon#about to read 3, iclass 16, count 0 2006.173.09:15:57.48#ibcon#read 3, iclass 16, count 0 2006.173.09:15:57.48#ibcon#about to read 4, iclass 16, count 0 2006.173.09:15:57.48#ibcon#read 4, iclass 16, count 0 2006.173.09:15:57.48#ibcon#about to read 5, iclass 16, count 0 2006.173.09:15:57.48#ibcon#read 5, iclass 16, count 0 2006.173.09:15:57.48#ibcon#about to read 6, iclass 16, count 0 2006.173.09:15:57.48#ibcon#read 6, iclass 16, count 0 2006.173.09:15:57.48#ibcon#end of sib2, iclass 16, count 0 2006.173.09:15:57.48#ibcon#*after write, iclass 16, count 0 2006.173.09:15:57.48#ibcon#*before return 0, iclass 16, count 0 2006.173.09:15:57.48#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.09:15:57.48#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.09:15:57.48#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.09:15:57.48#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.09:15:57.48$vck44/vabw=wide 2006.173.09:15:57.48#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.09:15:57.48#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.09:15:57.48#ibcon#ireg 8 cls_cnt 0 2006.173.09:15:57.48#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.09:15:57.48#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.09:15:57.48#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.09:15:57.48#ibcon#enter wrdev, iclass 18, count 0 2006.173.09:15:57.48#ibcon#first serial, iclass 18, count 0 2006.173.09:15:57.48#ibcon#enter sib2, iclass 18, count 0 2006.173.09:15:57.48#ibcon#flushed, iclass 18, count 0 2006.173.09:15:57.48#ibcon#about to write, iclass 18, count 0 2006.173.09:15:57.48#ibcon#wrote, iclass 18, count 0 2006.173.09:15:57.48#ibcon#about to read 3, iclass 18, count 0 2006.173.09:15:57.50#ibcon#read 3, iclass 18, count 0 2006.173.09:15:57.50#ibcon#about to read 4, iclass 18, count 0 2006.173.09:15:57.50#ibcon#read 4, iclass 18, count 0 2006.173.09:15:57.50#ibcon#about to read 5, iclass 18, count 0 2006.173.09:15:57.50#ibcon#read 5, iclass 18, count 0 2006.173.09:15:57.50#ibcon#about to read 6, iclass 18, count 0 2006.173.09:15:57.50#ibcon#read 6, iclass 18, count 0 2006.173.09:15:57.50#ibcon#end of sib2, iclass 18, count 0 2006.173.09:15:57.50#ibcon#*mode == 0, iclass 18, count 0 2006.173.09:15:57.50#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.09:15:57.50#ibcon#[25=BW32\r\n] 2006.173.09:15:57.50#ibcon#*before write, iclass 18, count 0 2006.173.09:15:57.50#ibcon#enter sib2, iclass 18, count 0 2006.173.09:15:57.50#ibcon#flushed, iclass 18, count 0 2006.173.09:15:57.50#ibcon#about to write, iclass 18, count 0 2006.173.09:15:57.50#ibcon#wrote, iclass 18, count 0 2006.173.09:15:57.50#ibcon#about to read 3, iclass 18, count 0 2006.173.09:15:57.53#ibcon#read 3, iclass 18, count 0 2006.173.09:15:57.53#ibcon#about to read 4, iclass 18, count 0 2006.173.09:15:57.53#ibcon#read 4, iclass 18, count 0 2006.173.09:15:57.53#ibcon#about to read 5, iclass 18, count 0 2006.173.09:15:57.53#ibcon#read 5, iclass 18, count 0 2006.173.09:15:57.53#ibcon#about to read 6, iclass 18, count 0 2006.173.09:15:57.53#ibcon#read 6, iclass 18, count 0 2006.173.09:15:57.53#ibcon#end of sib2, iclass 18, count 0 2006.173.09:15:57.53#ibcon#*after write, iclass 18, count 0 2006.173.09:15:57.53#ibcon#*before return 0, iclass 18, count 0 2006.173.09:15:57.53#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.09:15:57.53#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.09:15:57.53#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.09:15:57.53#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.09:15:57.53$vck44/vbbw=wide 2006.173.09:15:57.53#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.09:15:57.53#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.09:15:57.53#ibcon#ireg 8 cls_cnt 0 2006.173.09:15:57.53#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.09:15:57.60#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.09:15:57.60#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.09:15:57.60#ibcon#enter wrdev, iclass 20, count 0 2006.173.09:15:57.60#ibcon#first serial, iclass 20, count 0 2006.173.09:15:57.60#ibcon#enter sib2, iclass 20, count 0 2006.173.09:15:57.60#ibcon#flushed, iclass 20, count 0 2006.173.09:15:57.60#ibcon#about to write, iclass 20, count 0 2006.173.09:15:57.60#ibcon#wrote, iclass 20, count 0 2006.173.09:15:57.60#ibcon#about to read 3, iclass 20, count 0 2006.173.09:15:57.62#ibcon#read 3, iclass 20, count 0 2006.173.09:15:57.62#ibcon#about to read 4, iclass 20, count 0 2006.173.09:15:57.62#ibcon#read 4, iclass 20, count 0 2006.173.09:15:57.62#ibcon#about to read 5, iclass 20, count 0 2006.173.09:15:57.62#ibcon#read 5, iclass 20, count 0 2006.173.09:15:57.62#ibcon#about to read 6, iclass 20, count 0 2006.173.09:15:57.62#ibcon#read 6, iclass 20, count 0 2006.173.09:15:57.62#ibcon#end of sib2, iclass 20, count 0 2006.173.09:15:57.62#ibcon#*mode == 0, iclass 20, count 0 2006.173.09:15:57.62#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.09:15:57.62#ibcon#[27=BW32\r\n] 2006.173.09:15:57.62#ibcon#*before write, iclass 20, count 0 2006.173.09:15:57.62#ibcon#enter sib2, iclass 20, count 0 2006.173.09:15:57.62#ibcon#flushed, iclass 20, count 0 2006.173.09:15:57.62#ibcon#about to write, iclass 20, count 0 2006.173.09:15:57.62#ibcon#wrote, iclass 20, count 0 2006.173.09:15:57.62#ibcon#about to read 3, iclass 20, count 0 2006.173.09:15:57.65#ibcon#read 3, iclass 20, count 0 2006.173.09:15:57.65#ibcon#about to read 4, iclass 20, count 0 2006.173.09:15:57.65#ibcon#read 4, iclass 20, count 0 2006.173.09:15:57.65#ibcon#about to read 5, iclass 20, count 0 2006.173.09:15:57.65#ibcon#read 5, iclass 20, count 0 2006.173.09:15:57.65#ibcon#about to read 6, iclass 20, count 0 2006.173.09:15:57.65#ibcon#read 6, iclass 20, count 0 2006.173.09:15:57.65#ibcon#end of sib2, iclass 20, count 0 2006.173.09:15:57.65#ibcon#*after write, iclass 20, count 0 2006.173.09:15:57.65#ibcon#*before return 0, iclass 20, count 0 2006.173.09:15:57.65#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.09:15:57.65#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.09:15:57.65#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.09:15:57.65#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.09:15:57.65$setupk4/ifdk4 2006.173.09:15:57.65$ifdk4/lo= 2006.173.09:15:57.65$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.09:15:57.65$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.09:15:57.65$ifdk4/patch= 2006.173.09:15:57.65$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.09:15:57.65$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.09:15:57.65$setupk4/!*+20s 2006.173.09:16:05.83#abcon#<5=/16 0.4 0.8 22.98 891004.4\r\n> 2006.173.09:16:05.85#abcon#{5=INTERFACE CLEAR} 2006.173.09:16:05.91#abcon#[5=S1D000X0/0*\r\n] 2006.173.09:16:12.17$setupk4/"tpicd 2006.173.09:16:12.17$setupk4/echo=off 2006.173.09:16:12.17$setupk4/xlog=off 2006.173.09:16:12.17:!2006.173.09:16:16 2006.173.09:16:14.13#trakl#Source acquired 2006.173.09:16:14.13#flagr#flagr/antenna,acquired 2006.173.09:16:16.00:preob 2006.173.09:16:16.14/onsource/TRACKING 2006.173.09:16:16.14:!2006.173.09:16:26 2006.173.09:16:26.00:"tape 2006.173.09:16:26.00:"st=record 2006.173.09:16:26.00:data_valid=on 2006.173.09:16:26.00:midob 2006.173.09:16:26.13/onsource/TRACKING 2006.173.09:16:26.13/wx/22.98,1004.4,89 2006.173.09:16:26.31/cable/+6.5006E-03 2006.173.09:16:27.40/va/01,07,usb,yes,35,38 2006.173.09:16:27.40/va/02,06,usb,yes,35,36 2006.173.09:16:27.40/va/03,05,usb,yes,44,46 2006.173.09:16:27.40/va/04,06,usb,yes,36,38 2006.173.09:16:27.40/va/05,04,usb,yes,28,29 2006.173.09:16:27.40/va/06,03,usb,yes,39,39 2006.173.09:16:27.40/va/07,04,usb,yes,32,33 2006.173.09:16:27.40/va/08,04,usb,yes,27,33 2006.173.09:16:27.63/valo/01,524.99,yes,locked 2006.173.09:16:27.63/valo/02,534.99,yes,locked 2006.173.09:16:27.63/valo/03,564.99,yes,locked 2006.173.09:16:27.63/valo/04,624.99,yes,locked 2006.173.09:16:27.63/valo/05,734.99,yes,locked 2006.173.09:16:27.63/valo/06,814.99,yes,locked 2006.173.09:16:27.63/valo/07,864.99,yes,locked 2006.173.09:16:27.63/valo/08,884.99,yes,locked 2006.173.09:16:28.72/vb/01,04,usb,yes,29,27 2006.173.09:16:28.72/vb/02,04,usb,yes,31,31 2006.173.09:16:28.72/vb/03,04,usb,yes,28,31 2006.173.09:16:28.72/vb/04,04,usb,yes,32,31 2006.173.09:16:28.72/vb/05,04,usb,yes,25,27 2006.173.09:16:28.72/vb/06,04,usb,yes,29,26 2006.173.09:16:28.72/vb/07,04,usb,yes,29,29 2006.173.09:16:28.72/vb/08,04,usb,yes,27,30 2006.173.09:16:28.95/vblo/01,629.99,yes,locked 2006.173.09:16:28.95/vblo/02,634.99,yes,locked 2006.173.09:16:28.95/vblo/03,649.99,yes,locked 2006.173.09:16:28.95/vblo/04,679.99,yes,locked 2006.173.09:16:28.95/vblo/05,709.99,yes,locked 2006.173.09:16:28.95/vblo/06,719.99,yes,locked 2006.173.09:16:28.95/vblo/07,734.99,yes,locked 2006.173.09:16:28.95/vblo/08,744.99,yes,locked 2006.173.09:16:29.10/vabw/8 2006.173.09:16:29.25/vbbw/8 2006.173.09:16:29.34/xfe/off,on,15.0 2006.173.09:16:29.72/ifatt/23,28,28,28 2006.173.09:16:30.06/fmout-gps/S +3.98E-07 2006.173.09:16:30.10:!2006.173.09:18:06 2006.173.09:18:06.01:data_valid=off 2006.173.09:18:06.02:"et 2006.173.09:18:06.02:!+3s 2006.173.09:18:09.03:"tape 2006.173.09:18:09.04:postob 2006.173.09:18:09.24/cable/+6.5013E-03 2006.173.09:18:09.25/wx/23.00,1004.3,89 2006.173.09:18:09.30/fmout-gps/S +3.98E-07 2006.173.09:18:09.31:scan_name=173-0919,jd0606,90 2006.173.09:18:09.31:source=3c274,123049.42,122328.0,2000.0,cw 2006.173.09:18:11.13#flagr#flagr/antenna,new-source 2006.173.09:18:11.13:checkk5 2006.173.09:18:11.54/chk_autoobs//k5ts1/ autoobs is running! 2006.173.09:18:11.94/chk_autoobs//k5ts2/ autoobs is running! 2006.173.09:18:12.33/chk_autoobs//k5ts3/ autoobs is running! 2006.173.09:18:12.73/chk_autoobs//k5ts4/ autoobs is running! 2006.173.09:18:13.11/chk_obsdata//k5ts1/T1730916??a.dat file size is correct (nominal:400MB, actual:396MB). 2006.173.09:18:13.51/chk_obsdata//k5ts2/T1730916??b.dat file size is correct (nominal:400MB, actual:396MB). 2006.173.09:18:13.92/chk_obsdata//k5ts3/T1730916??c.dat file size is correct (nominal:400MB, actual:396MB). 2006.173.09:18:14.33/chk_obsdata//k5ts4/T1730916??d.dat file size is correct (nominal:400MB, actual:396MB). 2006.173.09:18:15.08/k5log//k5ts1_log_newline 2006.173.09:18:15.80/k5log//k5ts2_log_newline 2006.173.09:18:16.52/k5log//k5ts3_log_newline 2006.173.09:18:17.22/k5log//k5ts4_log_newline 2006.173.09:18:17.25/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.09:18:17.25:setupk4=1 2006.173.09:18:17.25$setupk4/echo=on 2006.173.09:18:17.25$setupk4/pcalon 2006.173.09:18:17.25$pcalon/"no phase cal control is implemented here 2006.173.09:18:17.25$setupk4/"tpicd=stop 2006.173.09:18:17.25$setupk4/"rec=synch_on 2006.173.09:18:17.25$setupk4/"rec_mode=128 2006.173.09:18:17.25$setupk4/!* 2006.173.09:18:17.25$setupk4/recpk4 2006.173.09:18:17.25$recpk4/recpatch= 2006.173.09:18:17.25$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.09:18:17.25$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.09:18:17.25$setupk4/vck44 2006.173.09:18:17.25$vck44/valo=1,524.99 2006.173.09:18:17.25#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.09:18:17.25#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.09:18:17.25#ibcon#ireg 17 cls_cnt 0 2006.173.09:18:17.25#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.09:18:17.25#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.09:18:17.25#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.09:18:17.25#ibcon#enter wrdev, iclass 3, count 0 2006.173.09:18:17.25#ibcon#first serial, iclass 3, count 0 2006.173.09:18:17.25#ibcon#enter sib2, iclass 3, count 0 2006.173.09:18:17.25#ibcon#flushed, iclass 3, count 0 2006.173.09:18:17.25#ibcon#about to write, iclass 3, count 0 2006.173.09:18:17.25#ibcon#wrote, iclass 3, count 0 2006.173.09:18:17.25#ibcon#about to read 3, iclass 3, count 0 2006.173.09:18:17.27#ibcon#read 3, iclass 3, count 0 2006.173.09:18:17.27#ibcon#about to read 4, iclass 3, count 0 2006.173.09:18:17.27#ibcon#read 4, iclass 3, count 0 2006.173.09:18:17.27#ibcon#about to read 5, iclass 3, count 0 2006.173.09:18:17.27#ibcon#read 5, iclass 3, count 0 2006.173.09:18:17.27#ibcon#about to read 6, iclass 3, count 0 2006.173.09:18:17.27#ibcon#read 6, iclass 3, count 0 2006.173.09:18:17.27#ibcon#end of sib2, iclass 3, count 0 2006.173.09:18:17.27#ibcon#*mode == 0, iclass 3, count 0 2006.173.09:18:17.27#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.09:18:17.27#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.09:18:17.27#ibcon#*before write, iclass 3, count 0 2006.173.09:18:17.27#ibcon#enter sib2, iclass 3, count 0 2006.173.09:18:17.27#ibcon#flushed, iclass 3, count 0 2006.173.09:18:17.27#ibcon#about to write, iclass 3, count 0 2006.173.09:18:17.27#ibcon#wrote, iclass 3, count 0 2006.173.09:18:17.27#ibcon#about to read 3, iclass 3, count 0 2006.173.09:18:17.32#ibcon#read 3, iclass 3, count 0 2006.173.09:18:17.32#ibcon#about to read 4, iclass 3, count 0 2006.173.09:18:17.32#ibcon#read 4, iclass 3, count 0 2006.173.09:18:17.32#ibcon#about to read 5, iclass 3, count 0 2006.173.09:18:17.32#ibcon#read 5, iclass 3, count 0 2006.173.09:18:17.32#ibcon#about to read 6, iclass 3, count 0 2006.173.09:18:17.32#ibcon#read 6, iclass 3, count 0 2006.173.09:18:17.32#ibcon#end of sib2, iclass 3, count 0 2006.173.09:18:17.32#ibcon#*after write, iclass 3, count 0 2006.173.09:18:17.32#ibcon#*before return 0, iclass 3, count 0 2006.173.09:18:17.32#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.09:18:17.32#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.09:18:17.32#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.09:18:17.32#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.09:18:17.32$vck44/va=1,7 2006.173.09:18:17.32#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.09:18:17.32#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.09:18:17.32#ibcon#ireg 11 cls_cnt 2 2006.173.09:18:17.32#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.09:18:17.32#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.09:18:17.32#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.09:18:17.32#ibcon#enter wrdev, iclass 5, count 2 2006.173.09:18:17.32#ibcon#first serial, iclass 5, count 2 2006.173.09:18:17.32#ibcon#enter sib2, iclass 5, count 2 2006.173.09:18:17.32#ibcon#flushed, iclass 5, count 2 2006.173.09:18:17.32#ibcon#about to write, iclass 5, count 2 2006.173.09:18:17.32#ibcon#wrote, iclass 5, count 2 2006.173.09:18:17.32#ibcon#about to read 3, iclass 5, count 2 2006.173.09:18:17.34#ibcon#read 3, iclass 5, count 2 2006.173.09:18:17.34#ibcon#about to read 4, iclass 5, count 2 2006.173.09:18:17.34#ibcon#read 4, iclass 5, count 2 2006.173.09:18:17.34#ibcon#about to read 5, iclass 5, count 2 2006.173.09:18:17.34#ibcon#read 5, iclass 5, count 2 2006.173.09:18:17.34#ibcon#about to read 6, iclass 5, count 2 2006.173.09:18:17.34#ibcon#read 6, iclass 5, count 2 2006.173.09:18:17.34#ibcon#end of sib2, iclass 5, count 2 2006.173.09:18:17.34#ibcon#*mode == 0, iclass 5, count 2 2006.173.09:18:17.34#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.09:18:17.34#ibcon#[25=AT01-07\r\n] 2006.173.09:18:17.34#ibcon#*before write, iclass 5, count 2 2006.173.09:18:17.34#ibcon#enter sib2, iclass 5, count 2 2006.173.09:18:17.34#ibcon#flushed, iclass 5, count 2 2006.173.09:18:17.34#ibcon#about to write, iclass 5, count 2 2006.173.09:18:17.34#ibcon#wrote, iclass 5, count 2 2006.173.09:18:17.34#ibcon#about to read 3, iclass 5, count 2 2006.173.09:18:17.37#ibcon#read 3, iclass 5, count 2 2006.173.09:18:17.37#ibcon#about to read 4, iclass 5, count 2 2006.173.09:18:17.37#ibcon#read 4, iclass 5, count 2 2006.173.09:18:17.37#ibcon#about to read 5, iclass 5, count 2 2006.173.09:18:17.37#ibcon#read 5, iclass 5, count 2 2006.173.09:18:17.37#ibcon#about to read 6, iclass 5, count 2 2006.173.09:18:17.37#ibcon#read 6, iclass 5, count 2 2006.173.09:18:17.37#ibcon#end of sib2, iclass 5, count 2 2006.173.09:18:17.37#ibcon#*after write, iclass 5, count 2 2006.173.09:18:17.37#ibcon#*before return 0, iclass 5, count 2 2006.173.09:18:17.37#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.09:18:17.37#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.09:18:17.37#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.09:18:17.37#ibcon#ireg 7 cls_cnt 0 2006.173.09:18:17.37#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.09:18:17.49#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.09:18:17.49#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.09:18:17.49#ibcon#enter wrdev, iclass 5, count 0 2006.173.09:18:17.49#ibcon#first serial, iclass 5, count 0 2006.173.09:18:17.49#ibcon#enter sib2, iclass 5, count 0 2006.173.09:18:17.49#ibcon#flushed, iclass 5, count 0 2006.173.09:18:17.49#ibcon#about to write, iclass 5, count 0 2006.173.09:18:17.49#ibcon#wrote, iclass 5, count 0 2006.173.09:18:17.49#ibcon#about to read 3, iclass 5, count 0 2006.173.09:18:17.51#ibcon#read 3, iclass 5, count 0 2006.173.09:18:17.51#ibcon#about to read 4, iclass 5, count 0 2006.173.09:18:17.51#ibcon#read 4, iclass 5, count 0 2006.173.09:18:17.51#ibcon#about to read 5, iclass 5, count 0 2006.173.09:18:17.51#ibcon#read 5, iclass 5, count 0 2006.173.09:18:17.51#ibcon#about to read 6, iclass 5, count 0 2006.173.09:18:17.51#ibcon#read 6, iclass 5, count 0 2006.173.09:18:17.51#ibcon#end of sib2, iclass 5, count 0 2006.173.09:18:17.51#ibcon#*mode == 0, iclass 5, count 0 2006.173.09:18:17.51#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.09:18:17.51#ibcon#[25=USB\r\n] 2006.173.09:18:17.51#ibcon#*before write, iclass 5, count 0 2006.173.09:18:17.51#ibcon#enter sib2, iclass 5, count 0 2006.173.09:18:17.51#ibcon#flushed, iclass 5, count 0 2006.173.09:18:17.51#ibcon#about to write, iclass 5, count 0 2006.173.09:18:17.51#ibcon#wrote, iclass 5, count 0 2006.173.09:18:17.51#ibcon#about to read 3, iclass 5, count 0 2006.173.09:18:17.54#ibcon#read 3, iclass 5, count 0 2006.173.09:18:17.54#ibcon#about to read 4, iclass 5, count 0 2006.173.09:18:17.54#ibcon#read 4, iclass 5, count 0 2006.173.09:18:17.54#ibcon#about to read 5, iclass 5, count 0 2006.173.09:18:17.54#ibcon#read 5, iclass 5, count 0 2006.173.09:18:17.54#ibcon#about to read 6, iclass 5, count 0 2006.173.09:18:17.54#ibcon#read 6, iclass 5, count 0 2006.173.09:18:17.54#ibcon#end of sib2, iclass 5, count 0 2006.173.09:18:17.54#ibcon#*after write, iclass 5, count 0 2006.173.09:18:17.54#ibcon#*before return 0, iclass 5, count 0 2006.173.09:18:17.54#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.09:18:17.54#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.09:18:17.54#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.09:18:17.54#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.09:18:17.54$vck44/valo=2,534.99 2006.173.09:18:17.54#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.09:18:17.54#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.09:18:17.54#ibcon#ireg 17 cls_cnt 0 2006.173.09:18:17.54#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.09:18:17.54#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.09:18:17.54#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.09:18:17.54#ibcon#enter wrdev, iclass 7, count 0 2006.173.09:18:17.54#ibcon#first serial, iclass 7, count 0 2006.173.09:18:17.54#ibcon#enter sib2, iclass 7, count 0 2006.173.09:18:17.54#ibcon#flushed, iclass 7, count 0 2006.173.09:18:17.54#ibcon#about to write, iclass 7, count 0 2006.173.09:18:17.54#ibcon#wrote, iclass 7, count 0 2006.173.09:18:17.54#ibcon#about to read 3, iclass 7, count 0 2006.173.09:18:17.56#ibcon#read 3, iclass 7, count 0 2006.173.09:18:17.56#ibcon#about to read 4, iclass 7, count 0 2006.173.09:18:17.56#ibcon#read 4, iclass 7, count 0 2006.173.09:18:17.56#ibcon#about to read 5, iclass 7, count 0 2006.173.09:18:17.56#ibcon#read 5, iclass 7, count 0 2006.173.09:18:17.56#ibcon#about to read 6, iclass 7, count 0 2006.173.09:18:17.56#ibcon#read 6, iclass 7, count 0 2006.173.09:18:17.56#ibcon#end of sib2, iclass 7, count 0 2006.173.09:18:17.56#ibcon#*mode == 0, iclass 7, count 0 2006.173.09:18:17.56#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.09:18:17.56#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.09:18:17.56#ibcon#*before write, iclass 7, count 0 2006.173.09:18:17.56#ibcon#enter sib2, iclass 7, count 0 2006.173.09:18:17.56#ibcon#flushed, iclass 7, count 0 2006.173.09:18:17.56#ibcon#about to write, iclass 7, count 0 2006.173.09:18:17.56#ibcon#wrote, iclass 7, count 0 2006.173.09:18:17.56#ibcon#about to read 3, iclass 7, count 0 2006.173.09:18:17.60#ibcon#read 3, iclass 7, count 0 2006.173.09:18:17.60#ibcon#about to read 4, iclass 7, count 0 2006.173.09:18:17.60#ibcon#read 4, iclass 7, count 0 2006.173.09:18:17.60#ibcon#about to read 5, iclass 7, count 0 2006.173.09:18:17.60#ibcon#read 5, iclass 7, count 0 2006.173.09:18:17.60#ibcon#about to read 6, iclass 7, count 0 2006.173.09:18:17.60#ibcon#read 6, iclass 7, count 0 2006.173.09:18:17.60#ibcon#end of sib2, iclass 7, count 0 2006.173.09:18:17.60#ibcon#*after write, iclass 7, count 0 2006.173.09:18:17.60#ibcon#*before return 0, iclass 7, count 0 2006.173.09:18:17.60#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.09:18:17.60#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.09:18:17.60#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.09:18:17.60#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.09:18:17.60$vck44/va=2,6 2006.173.09:18:17.60#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.09:18:17.60#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.09:18:17.60#ibcon#ireg 11 cls_cnt 2 2006.173.09:18:17.60#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.09:18:17.66#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.09:18:17.66#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.09:18:17.66#ibcon#enter wrdev, iclass 11, count 2 2006.173.09:18:17.66#ibcon#first serial, iclass 11, count 2 2006.173.09:18:17.66#ibcon#enter sib2, iclass 11, count 2 2006.173.09:18:17.66#ibcon#flushed, iclass 11, count 2 2006.173.09:18:17.66#ibcon#about to write, iclass 11, count 2 2006.173.09:18:17.66#ibcon#wrote, iclass 11, count 2 2006.173.09:18:17.66#ibcon#about to read 3, iclass 11, count 2 2006.173.09:18:17.68#ibcon#read 3, iclass 11, count 2 2006.173.09:18:17.68#ibcon#about to read 4, iclass 11, count 2 2006.173.09:18:17.68#ibcon#read 4, iclass 11, count 2 2006.173.09:18:17.68#ibcon#about to read 5, iclass 11, count 2 2006.173.09:18:17.68#ibcon#read 5, iclass 11, count 2 2006.173.09:18:17.68#ibcon#about to read 6, iclass 11, count 2 2006.173.09:18:17.68#ibcon#read 6, iclass 11, count 2 2006.173.09:18:17.68#ibcon#end of sib2, iclass 11, count 2 2006.173.09:18:17.68#ibcon#*mode == 0, iclass 11, count 2 2006.173.09:18:17.68#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.09:18:17.68#ibcon#[25=AT02-06\r\n] 2006.173.09:18:17.68#ibcon#*before write, iclass 11, count 2 2006.173.09:18:17.68#ibcon#enter sib2, iclass 11, count 2 2006.173.09:18:17.68#ibcon#flushed, iclass 11, count 2 2006.173.09:18:17.68#ibcon#about to write, iclass 11, count 2 2006.173.09:18:17.68#ibcon#wrote, iclass 11, count 2 2006.173.09:18:17.68#ibcon#about to read 3, iclass 11, count 2 2006.173.09:18:17.71#ibcon#read 3, iclass 11, count 2 2006.173.09:18:17.71#ibcon#about to read 4, iclass 11, count 2 2006.173.09:18:17.71#ibcon#read 4, iclass 11, count 2 2006.173.09:18:17.71#ibcon#about to read 5, iclass 11, count 2 2006.173.09:18:17.71#ibcon#read 5, iclass 11, count 2 2006.173.09:18:17.71#ibcon#about to read 6, iclass 11, count 2 2006.173.09:18:17.71#ibcon#read 6, iclass 11, count 2 2006.173.09:18:17.71#ibcon#end of sib2, iclass 11, count 2 2006.173.09:18:17.71#ibcon#*after write, iclass 11, count 2 2006.173.09:18:17.71#ibcon#*before return 0, iclass 11, count 2 2006.173.09:18:17.71#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.09:18:17.71#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.09:18:17.71#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.09:18:17.71#ibcon#ireg 7 cls_cnt 0 2006.173.09:18:17.71#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.09:18:17.83#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.09:18:17.83#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.09:18:17.83#ibcon#enter wrdev, iclass 11, count 0 2006.173.09:18:17.83#ibcon#first serial, iclass 11, count 0 2006.173.09:18:17.83#ibcon#enter sib2, iclass 11, count 0 2006.173.09:18:17.83#ibcon#flushed, iclass 11, count 0 2006.173.09:18:17.83#ibcon#about to write, iclass 11, count 0 2006.173.09:18:17.83#ibcon#wrote, iclass 11, count 0 2006.173.09:18:17.83#ibcon#about to read 3, iclass 11, count 0 2006.173.09:18:17.85#ibcon#read 3, iclass 11, count 0 2006.173.09:18:17.85#ibcon#about to read 4, iclass 11, count 0 2006.173.09:18:17.85#ibcon#read 4, iclass 11, count 0 2006.173.09:18:17.85#ibcon#about to read 5, iclass 11, count 0 2006.173.09:18:17.85#ibcon#read 5, iclass 11, count 0 2006.173.09:18:17.85#ibcon#about to read 6, iclass 11, count 0 2006.173.09:18:17.85#ibcon#read 6, iclass 11, count 0 2006.173.09:18:17.85#ibcon#end of sib2, iclass 11, count 0 2006.173.09:18:17.85#ibcon#*mode == 0, iclass 11, count 0 2006.173.09:18:17.85#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.09:18:17.85#ibcon#[25=USB\r\n] 2006.173.09:18:17.85#ibcon#*before write, iclass 11, count 0 2006.173.09:18:17.85#ibcon#enter sib2, iclass 11, count 0 2006.173.09:18:17.85#ibcon#flushed, iclass 11, count 0 2006.173.09:18:17.85#ibcon#about to write, iclass 11, count 0 2006.173.09:18:17.85#ibcon#wrote, iclass 11, count 0 2006.173.09:18:17.85#ibcon#about to read 3, iclass 11, count 0 2006.173.09:18:17.88#ibcon#read 3, iclass 11, count 0 2006.173.09:18:17.88#ibcon#about to read 4, iclass 11, count 0 2006.173.09:18:17.88#ibcon#read 4, iclass 11, count 0 2006.173.09:18:17.88#ibcon#about to read 5, iclass 11, count 0 2006.173.09:18:17.88#ibcon#read 5, iclass 11, count 0 2006.173.09:18:17.88#ibcon#about to read 6, iclass 11, count 0 2006.173.09:18:17.88#ibcon#read 6, iclass 11, count 0 2006.173.09:18:17.88#ibcon#end of sib2, iclass 11, count 0 2006.173.09:18:17.88#ibcon#*after write, iclass 11, count 0 2006.173.09:18:17.88#ibcon#*before return 0, iclass 11, count 0 2006.173.09:18:17.88#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.09:18:17.88#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.09:18:17.88#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.09:18:17.88#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.09:18:17.88$vck44/valo=3,564.99 2006.173.09:18:17.88#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.09:18:17.88#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.09:18:17.88#ibcon#ireg 17 cls_cnt 0 2006.173.09:18:17.88#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.09:18:17.88#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.09:18:17.88#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.09:18:17.88#ibcon#enter wrdev, iclass 13, count 0 2006.173.09:18:17.88#ibcon#first serial, iclass 13, count 0 2006.173.09:18:17.88#ibcon#enter sib2, iclass 13, count 0 2006.173.09:18:17.88#ibcon#flushed, iclass 13, count 0 2006.173.09:18:17.88#ibcon#about to write, iclass 13, count 0 2006.173.09:18:17.88#ibcon#wrote, iclass 13, count 0 2006.173.09:18:17.88#ibcon#about to read 3, iclass 13, count 0 2006.173.09:18:17.90#ibcon#read 3, iclass 13, count 0 2006.173.09:18:17.90#ibcon#about to read 4, iclass 13, count 0 2006.173.09:18:17.90#ibcon#read 4, iclass 13, count 0 2006.173.09:18:17.90#ibcon#about to read 5, iclass 13, count 0 2006.173.09:18:17.90#ibcon#read 5, iclass 13, count 0 2006.173.09:18:17.90#ibcon#about to read 6, iclass 13, count 0 2006.173.09:18:17.90#ibcon#read 6, iclass 13, count 0 2006.173.09:18:17.90#ibcon#end of sib2, iclass 13, count 0 2006.173.09:18:17.90#ibcon#*mode == 0, iclass 13, count 0 2006.173.09:18:17.90#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.09:18:17.90#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.09:18:17.90#ibcon#*before write, iclass 13, count 0 2006.173.09:18:17.90#ibcon#enter sib2, iclass 13, count 0 2006.173.09:18:17.90#ibcon#flushed, iclass 13, count 0 2006.173.09:18:17.90#ibcon#about to write, iclass 13, count 0 2006.173.09:18:17.90#ibcon#wrote, iclass 13, count 0 2006.173.09:18:17.90#ibcon#about to read 3, iclass 13, count 0 2006.173.09:18:17.94#ibcon#read 3, iclass 13, count 0 2006.173.09:18:17.94#ibcon#about to read 4, iclass 13, count 0 2006.173.09:18:17.94#ibcon#read 4, iclass 13, count 0 2006.173.09:18:17.94#ibcon#about to read 5, iclass 13, count 0 2006.173.09:18:17.94#ibcon#read 5, iclass 13, count 0 2006.173.09:18:17.94#ibcon#about to read 6, iclass 13, count 0 2006.173.09:18:17.94#ibcon#read 6, iclass 13, count 0 2006.173.09:18:17.94#ibcon#end of sib2, iclass 13, count 0 2006.173.09:18:17.94#ibcon#*after write, iclass 13, count 0 2006.173.09:18:17.94#ibcon#*before return 0, iclass 13, count 0 2006.173.09:18:17.94#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.09:18:17.94#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.09:18:17.94#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.09:18:17.94#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.09:18:17.94$vck44/va=3,5 2006.173.09:18:17.94#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.09:18:17.94#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.09:18:17.94#ibcon#ireg 11 cls_cnt 2 2006.173.09:18:17.94#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.09:18:18.00#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.09:18:18.00#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.09:18:18.00#ibcon#enter wrdev, iclass 15, count 2 2006.173.09:18:18.00#ibcon#first serial, iclass 15, count 2 2006.173.09:18:18.00#ibcon#enter sib2, iclass 15, count 2 2006.173.09:18:18.00#ibcon#flushed, iclass 15, count 2 2006.173.09:18:18.00#ibcon#about to write, iclass 15, count 2 2006.173.09:18:18.00#ibcon#wrote, iclass 15, count 2 2006.173.09:18:18.00#ibcon#about to read 3, iclass 15, count 2 2006.173.09:18:18.02#ibcon#read 3, iclass 15, count 2 2006.173.09:18:18.02#ibcon#about to read 4, iclass 15, count 2 2006.173.09:18:18.02#ibcon#read 4, iclass 15, count 2 2006.173.09:18:18.02#ibcon#about to read 5, iclass 15, count 2 2006.173.09:18:18.02#ibcon#read 5, iclass 15, count 2 2006.173.09:18:18.02#ibcon#about to read 6, iclass 15, count 2 2006.173.09:18:18.02#ibcon#read 6, iclass 15, count 2 2006.173.09:18:18.02#ibcon#end of sib2, iclass 15, count 2 2006.173.09:18:18.02#ibcon#*mode == 0, iclass 15, count 2 2006.173.09:18:18.02#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.09:18:18.02#ibcon#[25=AT03-05\r\n] 2006.173.09:18:18.02#ibcon#*before write, iclass 15, count 2 2006.173.09:18:18.02#ibcon#enter sib2, iclass 15, count 2 2006.173.09:18:18.02#ibcon#flushed, iclass 15, count 2 2006.173.09:18:18.02#ibcon#about to write, iclass 15, count 2 2006.173.09:18:18.02#ibcon#wrote, iclass 15, count 2 2006.173.09:18:18.02#ibcon#about to read 3, iclass 15, count 2 2006.173.09:18:18.05#ibcon#read 3, iclass 15, count 2 2006.173.09:18:18.05#ibcon#about to read 4, iclass 15, count 2 2006.173.09:18:18.05#ibcon#read 4, iclass 15, count 2 2006.173.09:18:18.05#ibcon#about to read 5, iclass 15, count 2 2006.173.09:18:18.05#ibcon#read 5, iclass 15, count 2 2006.173.09:18:18.05#ibcon#about to read 6, iclass 15, count 2 2006.173.09:18:18.05#ibcon#read 6, iclass 15, count 2 2006.173.09:18:18.05#ibcon#end of sib2, iclass 15, count 2 2006.173.09:18:18.05#ibcon#*after write, iclass 15, count 2 2006.173.09:18:18.05#ibcon#*before return 0, iclass 15, count 2 2006.173.09:18:18.05#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.09:18:18.05#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.09:18:18.05#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.09:18:18.05#ibcon#ireg 7 cls_cnt 0 2006.173.09:18:18.05#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.09:18:18.16#abcon#<5=/02 0.4 0.8 23.00 901004.3\r\n> 2006.173.09:18:18.17#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.09:18:18.17#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.09:18:18.17#ibcon#enter wrdev, iclass 15, count 0 2006.173.09:18:18.17#ibcon#first serial, iclass 15, count 0 2006.173.09:18:18.17#ibcon#enter sib2, iclass 15, count 0 2006.173.09:18:18.17#ibcon#flushed, iclass 15, count 0 2006.173.09:18:18.17#ibcon#about to write, iclass 15, count 0 2006.173.09:18:18.17#ibcon#wrote, iclass 15, count 0 2006.173.09:18:18.17#ibcon#about to read 3, iclass 15, count 0 2006.173.09:18:18.18#abcon#{5=INTERFACE CLEAR} 2006.173.09:18:18.19#ibcon#read 3, iclass 15, count 0 2006.173.09:18:18.19#ibcon#about to read 4, iclass 15, count 0 2006.173.09:18:18.19#ibcon#read 4, iclass 15, count 0 2006.173.09:18:18.19#ibcon#about to read 5, iclass 15, count 0 2006.173.09:18:18.19#ibcon#read 5, iclass 15, count 0 2006.173.09:18:18.19#ibcon#about to read 6, iclass 15, count 0 2006.173.09:18:18.19#ibcon#read 6, iclass 15, count 0 2006.173.09:18:18.19#ibcon#end of sib2, iclass 15, count 0 2006.173.09:18:18.19#ibcon#*mode == 0, iclass 15, count 0 2006.173.09:18:18.19#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.09:18:18.19#ibcon#[25=USB\r\n] 2006.173.09:18:18.19#ibcon#*before write, iclass 15, count 0 2006.173.09:18:18.19#ibcon#enter sib2, iclass 15, count 0 2006.173.09:18:18.19#ibcon#flushed, iclass 15, count 0 2006.173.09:18:18.19#ibcon#about to write, iclass 15, count 0 2006.173.09:18:18.19#ibcon#wrote, iclass 15, count 0 2006.173.09:18:18.19#ibcon#about to read 3, iclass 15, count 0 2006.173.09:18:18.22#ibcon#read 3, iclass 15, count 0 2006.173.09:18:18.22#ibcon#about to read 4, iclass 15, count 0 2006.173.09:18:18.22#ibcon#read 4, iclass 15, count 0 2006.173.09:18:18.22#ibcon#about to read 5, iclass 15, count 0 2006.173.09:18:18.22#ibcon#read 5, iclass 15, count 0 2006.173.09:18:18.22#ibcon#about to read 6, iclass 15, count 0 2006.173.09:18:18.22#ibcon#read 6, iclass 15, count 0 2006.173.09:18:18.22#ibcon#end of sib2, iclass 15, count 0 2006.173.09:18:18.22#ibcon#*after write, iclass 15, count 0 2006.173.09:18:18.22#ibcon#*before return 0, iclass 15, count 0 2006.173.09:18:18.22#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.09:18:18.22#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.09:18:18.22#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.09:18:18.22#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.09:18:18.22$vck44/valo=4,624.99 2006.173.09:18:18.22#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.09:18:18.22#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.09:18:18.22#ibcon#ireg 17 cls_cnt 0 2006.173.09:18:18.22#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.09:18:18.22#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.09:18:18.22#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.09:18:18.22#ibcon#enter wrdev, iclass 20, count 0 2006.173.09:18:18.22#ibcon#first serial, iclass 20, count 0 2006.173.09:18:18.22#ibcon#enter sib2, iclass 20, count 0 2006.173.09:18:18.22#ibcon#flushed, iclass 20, count 0 2006.173.09:18:18.22#ibcon#about to write, iclass 20, count 0 2006.173.09:18:18.22#ibcon#wrote, iclass 20, count 0 2006.173.09:18:18.22#ibcon#about to read 3, iclass 20, count 0 2006.173.09:18:18.24#ibcon#read 3, iclass 20, count 0 2006.173.09:18:18.24#ibcon#about to read 4, iclass 20, count 0 2006.173.09:18:18.24#ibcon#read 4, iclass 20, count 0 2006.173.09:18:18.24#ibcon#about to read 5, iclass 20, count 0 2006.173.09:18:18.24#ibcon#read 5, iclass 20, count 0 2006.173.09:18:18.24#ibcon#about to read 6, iclass 20, count 0 2006.173.09:18:18.24#ibcon#read 6, iclass 20, count 0 2006.173.09:18:18.24#ibcon#end of sib2, iclass 20, count 0 2006.173.09:18:18.24#ibcon#*mode == 0, iclass 20, count 0 2006.173.09:18:18.24#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.09:18:18.24#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.09:18:18.24#ibcon#*before write, iclass 20, count 0 2006.173.09:18:18.24#ibcon#enter sib2, iclass 20, count 0 2006.173.09:18:18.24#ibcon#flushed, iclass 20, count 0 2006.173.09:18:18.24#ibcon#about to write, iclass 20, count 0 2006.173.09:18:18.24#ibcon#wrote, iclass 20, count 0 2006.173.09:18:18.24#ibcon#about to read 3, iclass 20, count 0 2006.173.09:18:18.24#abcon#[5=S1D000X0/0*\r\n] 2006.173.09:18:18.28#ibcon#read 3, iclass 20, count 0 2006.173.09:18:18.28#ibcon#about to read 4, iclass 20, count 0 2006.173.09:18:18.28#ibcon#read 4, iclass 20, count 0 2006.173.09:18:18.28#ibcon#about to read 5, iclass 20, count 0 2006.173.09:18:18.28#ibcon#read 5, iclass 20, count 0 2006.173.09:18:18.28#ibcon#about to read 6, iclass 20, count 0 2006.173.09:18:18.28#ibcon#read 6, iclass 20, count 0 2006.173.09:18:18.28#ibcon#end of sib2, iclass 20, count 0 2006.173.09:18:18.28#ibcon#*after write, iclass 20, count 0 2006.173.09:18:18.28#ibcon#*before return 0, iclass 20, count 0 2006.173.09:18:18.28#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.09:18:18.28#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.09:18:18.28#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.09:18:18.28#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.09:18:18.28$vck44/va=4,6 2006.173.09:18:18.28#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.09:18:18.28#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.09:18:18.28#ibcon#ireg 11 cls_cnt 2 2006.173.09:18:18.28#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.09:18:18.34#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.09:18:18.34#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.09:18:18.34#ibcon#enter wrdev, iclass 23, count 2 2006.173.09:18:18.34#ibcon#first serial, iclass 23, count 2 2006.173.09:18:18.34#ibcon#enter sib2, iclass 23, count 2 2006.173.09:18:18.34#ibcon#flushed, iclass 23, count 2 2006.173.09:18:18.34#ibcon#about to write, iclass 23, count 2 2006.173.09:18:18.34#ibcon#wrote, iclass 23, count 2 2006.173.09:18:18.34#ibcon#about to read 3, iclass 23, count 2 2006.173.09:18:18.36#ibcon#read 3, iclass 23, count 2 2006.173.09:18:18.36#ibcon#about to read 4, iclass 23, count 2 2006.173.09:18:18.36#ibcon#read 4, iclass 23, count 2 2006.173.09:18:18.36#ibcon#about to read 5, iclass 23, count 2 2006.173.09:18:18.36#ibcon#read 5, iclass 23, count 2 2006.173.09:18:18.36#ibcon#about to read 6, iclass 23, count 2 2006.173.09:18:18.36#ibcon#read 6, iclass 23, count 2 2006.173.09:18:18.36#ibcon#end of sib2, iclass 23, count 2 2006.173.09:18:18.36#ibcon#*mode == 0, iclass 23, count 2 2006.173.09:18:18.36#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.09:18:18.36#ibcon#[25=AT04-06\r\n] 2006.173.09:18:18.36#ibcon#*before write, iclass 23, count 2 2006.173.09:18:18.36#ibcon#enter sib2, iclass 23, count 2 2006.173.09:18:18.36#ibcon#flushed, iclass 23, count 2 2006.173.09:18:18.36#ibcon#about to write, iclass 23, count 2 2006.173.09:18:18.36#ibcon#wrote, iclass 23, count 2 2006.173.09:18:18.36#ibcon#about to read 3, iclass 23, count 2 2006.173.09:18:18.39#ibcon#read 3, iclass 23, count 2 2006.173.09:18:18.39#ibcon#about to read 4, iclass 23, count 2 2006.173.09:18:18.39#ibcon#read 4, iclass 23, count 2 2006.173.09:18:18.39#ibcon#about to read 5, iclass 23, count 2 2006.173.09:18:18.39#ibcon#read 5, iclass 23, count 2 2006.173.09:18:18.39#ibcon#about to read 6, iclass 23, count 2 2006.173.09:18:18.39#ibcon#read 6, iclass 23, count 2 2006.173.09:18:18.39#ibcon#end of sib2, iclass 23, count 2 2006.173.09:18:18.39#ibcon#*after write, iclass 23, count 2 2006.173.09:18:18.39#ibcon#*before return 0, iclass 23, count 2 2006.173.09:18:18.39#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.09:18:18.39#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.09:18:18.39#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.09:18:18.39#ibcon#ireg 7 cls_cnt 0 2006.173.09:18:18.39#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.09:18:18.51#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.09:18:18.51#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.09:18:18.51#ibcon#enter wrdev, iclass 23, count 0 2006.173.09:18:18.51#ibcon#first serial, iclass 23, count 0 2006.173.09:18:18.51#ibcon#enter sib2, iclass 23, count 0 2006.173.09:18:18.51#ibcon#flushed, iclass 23, count 0 2006.173.09:18:18.51#ibcon#about to write, iclass 23, count 0 2006.173.09:18:18.51#ibcon#wrote, iclass 23, count 0 2006.173.09:18:18.51#ibcon#about to read 3, iclass 23, count 0 2006.173.09:18:18.53#ibcon#read 3, iclass 23, count 0 2006.173.09:18:18.53#ibcon#about to read 4, iclass 23, count 0 2006.173.09:18:18.53#ibcon#read 4, iclass 23, count 0 2006.173.09:18:18.53#ibcon#about to read 5, iclass 23, count 0 2006.173.09:18:18.53#ibcon#read 5, iclass 23, count 0 2006.173.09:18:18.53#ibcon#about to read 6, iclass 23, count 0 2006.173.09:18:18.53#ibcon#read 6, iclass 23, count 0 2006.173.09:18:18.53#ibcon#end of sib2, iclass 23, count 0 2006.173.09:18:18.53#ibcon#*mode == 0, iclass 23, count 0 2006.173.09:18:18.53#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.09:18:18.53#ibcon#[25=USB\r\n] 2006.173.09:18:18.53#ibcon#*before write, iclass 23, count 0 2006.173.09:18:18.53#ibcon#enter sib2, iclass 23, count 0 2006.173.09:18:18.53#ibcon#flushed, iclass 23, count 0 2006.173.09:18:18.53#ibcon#about to write, iclass 23, count 0 2006.173.09:18:18.53#ibcon#wrote, iclass 23, count 0 2006.173.09:18:18.53#ibcon#about to read 3, iclass 23, count 0 2006.173.09:18:18.56#ibcon#read 3, iclass 23, count 0 2006.173.09:18:18.56#ibcon#about to read 4, iclass 23, count 0 2006.173.09:18:18.56#ibcon#read 4, iclass 23, count 0 2006.173.09:18:18.56#ibcon#about to read 5, iclass 23, count 0 2006.173.09:18:18.56#ibcon#read 5, iclass 23, count 0 2006.173.09:18:18.56#ibcon#about to read 6, iclass 23, count 0 2006.173.09:18:18.56#ibcon#read 6, iclass 23, count 0 2006.173.09:18:18.56#ibcon#end of sib2, iclass 23, count 0 2006.173.09:18:18.56#ibcon#*after write, iclass 23, count 0 2006.173.09:18:18.56#ibcon#*before return 0, iclass 23, count 0 2006.173.09:18:18.56#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.09:18:18.56#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.09:18:18.56#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.09:18:18.56#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.09:18:18.56$vck44/valo=5,734.99 2006.173.09:18:18.56#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.09:18:18.56#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.09:18:18.56#ibcon#ireg 17 cls_cnt 0 2006.173.09:18:18.56#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.09:18:18.56#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.09:18:18.56#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.09:18:18.56#ibcon#enter wrdev, iclass 25, count 0 2006.173.09:18:18.56#ibcon#first serial, iclass 25, count 0 2006.173.09:18:18.56#ibcon#enter sib2, iclass 25, count 0 2006.173.09:18:18.56#ibcon#flushed, iclass 25, count 0 2006.173.09:18:18.56#ibcon#about to write, iclass 25, count 0 2006.173.09:18:18.56#ibcon#wrote, iclass 25, count 0 2006.173.09:18:18.56#ibcon#about to read 3, iclass 25, count 0 2006.173.09:18:18.58#ibcon#read 3, iclass 25, count 0 2006.173.09:18:18.58#ibcon#about to read 4, iclass 25, count 0 2006.173.09:18:18.58#ibcon#read 4, iclass 25, count 0 2006.173.09:18:18.58#ibcon#about to read 5, iclass 25, count 0 2006.173.09:18:18.58#ibcon#read 5, iclass 25, count 0 2006.173.09:18:18.58#ibcon#about to read 6, iclass 25, count 0 2006.173.09:18:18.58#ibcon#read 6, iclass 25, count 0 2006.173.09:18:18.58#ibcon#end of sib2, iclass 25, count 0 2006.173.09:18:18.58#ibcon#*mode == 0, iclass 25, count 0 2006.173.09:18:18.58#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.09:18:18.58#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.09:18:18.58#ibcon#*before write, iclass 25, count 0 2006.173.09:18:18.58#ibcon#enter sib2, iclass 25, count 0 2006.173.09:18:18.58#ibcon#flushed, iclass 25, count 0 2006.173.09:18:18.58#ibcon#about to write, iclass 25, count 0 2006.173.09:18:18.58#ibcon#wrote, iclass 25, count 0 2006.173.09:18:18.58#ibcon#about to read 3, iclass 25, count 0 2006.173.09:18:18.62#ibcon#read 3, iclass 25, count 0 2006.173.09:18:18.62#ibcon#about to read 4, iclass 25, count 0 2006.173.09:18:18.62#ibcon#read 4, iclass 25, count 0 2006.173.09:18:18.62#ibcon#about to read 5, iclass 25, count 0 2006.173.09:18:18.62#ibcon#read 5, iclass 25, count 0 2006.173.09:18:18.62#ibcon#about to read 6, iclass 25, count 0 2006.173.09:18:18.62#ibcon#read 6, iclass 25, count 0 2006.173.09:18:18.62#ibcon#end of sib2, iclass 25, count 0 2006.173.09:18:18.62#ibcon#*after write, iclass 25, count 0 2006.173.09:18:18.62#ibcon#*before return 0, iclass 25, count 0 2006.173.09:18:18.62#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.09:18:18.62#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.09:18:18.62#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.09:18:18.62#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.09:18:18.62$vck44/va=5,4 2006.173.09:18:18.62#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.09:18:18.62#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.09:18:18.62#ibcon#ireg 11 cls_cnt 2 2006.173.09:18:18.62#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.09:18:18.68#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.09:18:18.68#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.09:18:18.68#ibcon#enter wrdev, iclass 27, count 2 2006.173.09:18:18.68#ibcon#first serial, iclass 27, count 2 2006.173.09:18:18.68#ibcon#enter sib2, iclass 27, count 2 2006.173.09:18:18.68#ibcon#flushed, iclass 27, count 2 2006.173.09:18:18.68#ibcon#about to write, iclass 27, count 2 2006.173.09:18:18.68#ibcon#wrote, iclass 27, count 2 2006.173.09:18:18.68#ibcon#about to read 3, iclass 27, count 2 2006.173.09:18:18.70#ibcon#read 3, iclass 27, count 2 2006.173.09:18:18.70#ibcon#about to read 4, iclass 27, count 2 2006.173.09:18:18.70#ibcon#read 4, iclass 27, count 2 2006.173.09:18:18.70#ibcon#about to read 5, iclass 27, count 2 2006.173.09:18:18.70#ibcon#read 5, iclass 27, count 2 2006.173.09:18:18.70#ibcon#about to read 6, iclass 27, count 2 2006.173.09:18:18.70#ibcon#read 6, iclass 27, count 2 2006.173.09:18:18.70#ibcon#end of sib2, iclass 27, count 2 2006.173.09:18:18.70#ibcon#*mode == 0, iclass 27, count 2 2006.173.09:18:18.70#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.09:18:18.70#ibcon#[25=AT05-04\r\n] 2006.173.09:18:18.70#ibcon#*before write, iclass 27, count 2 2006.173.09:18:18.70#ibcon#enter sib2, iclass 27, count 2 2006.173.09:18:18.70#ibcon#flushed, iclass 27, count 2 2006.173.09:18:18.70#ibcon#about to write, iclass 27, count 2 2006.173.09:18:18.70#ibcon#wrote, iclass 27, count 2 2006.173.09:18:18.70#ibcon#about to read 3, iclass 27, count 2 2006.173.09:18:18.73#ibcon#read 3, iclass 27, count 2 2006.173.09:18:18.73#ibcon#about to read 4, iclass 27, count 2 2006.173.09:18:18.73#ibcon#read 4, iclass 27, count 2 2006.173.09:18:18.73#ibcon#about to read 5, iclass 27, count 2 2006.173.09:18:18.73#ibcon#read 5, iclass 27, count 2 2006.173.09:18:18.73#ibcon#about to read 6, iclass 27, count 2 2006.173.09:18:18.73#ibcon#read 6, iclass 27, count 2 2006.173.09:18:18.73#ibcon#end of sib2, iclass 27, count 2 2006.173.09:18:18.73#ibcon#*after write, iclass 27, count 2 2006.173.09:18:18.73#ibcon#*before return 0, iclass 27, count 2 2006.173.09:18:18.73#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.09:18:18.73#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.09:18:18.73#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.09:18:18.73#ibcon#ireg 7 cls_cnt 0 2006.173.09:18:18.73#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.09:18:18.85#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.09:18:18.85#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.09:18:18.85#ibcon#enter wrdev, iclass 27, count 0 2006.173.09:18:18.85#ibcon#first serial, iclass 27, count 0 2006.173.09:18:18.85#ibcon#enter sib2, iclass 27, count 0 2006.173.09:18:18.85#ibcon#flushed, iclass 27, count 0 2006.173.09:18:18.85#ibcon#about to write, iclass 27, count 0 2006.173.09:18:18.85#ibcon#wrote, iclass 27, count 0 2006.173.09:18:18.85#ibcon#about to read 3, iclass 27, count 0 2006.173.09:18:18.87#ibcon#read 3, iclass 27, count 0 2006.173.09:18:18.87#ibcon#about to read 4, iclass 27, count 0 2006.173.09:18:18.87#ibcon#read 4, iclass 27, count 0 2006.173.09:18:18.87#ibcon#about to read 5, iclass 27, count 0 2006.173.09:18:18.87#ibcon#read 5, iclass 27, count 0 2006.173.09:18:18.87#ibcon#about to read 6, iclass 27, count 0 2006.173.09:18:18.87#ibcon#read 6, iclass 27, count 0 2006.173.09:18:18.87#ibcon#end of sib2, iclass 27, count 0 2006.173.09:18:18.87#ibcon#*mode == 0, iclass 27, count 0 2006.173.09:18:18.87#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.09:18:18.87#ibcon#[25=USB\r\n] 2006.173.09:18:18.87#ibcon#*before write, iclass 27, count 0 2006.173.09:18:18.87#ibcon#enter sib2, iclass 27, count 0 2006.173.09:18:18.87#ibcon#flushed, iclass 27, count 0 2006.173.09:18:18.87#ibcon#about to write, iclass 27, count 0 2006.173.09:18:18.87#ibcon#wrote, iclass 27, count 0 2006.173.09:18:18.87#ibcon#about to read 3, iclass 27, count 0 2006.173.09:18:18.90#ibcon#read 3, iclass 27, count 0 2006.173.09:18:18.90#ibcon#about to read 4, iclass 27, count 0 2006.173.09:18:18.90#ibcon#read 4, iclass 27, count 0 2006.173.09:18:18.90#ibcon#about to read 5, iclass 27, count 0 2006.173.09:18:18.90#ibcon#read 5, iclass 27, count 0 2006.173.09:18:18.90#ibcon#about to read 6, iclass 27, count 0 2006.173.09:18:18.90#ibcon#read 6, iclass 27, count 0 2006.173.09:18:18.90#ibcon#end of sib2, iclass 27, count 0 2006.173.09:18:18.90#ibcon#*after write, iclass 27, count 0 2006.173.09:18:18.90#ibcon#*before return 0, iclass 27, count 0 2006.173.09:18:18.90#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.09:18:18.90#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.09:18:18.90#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.09:18:18.90#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.09:18:18.90$vck44/valo=6,814.99 2006.173.09:18:18.90#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.09:18:18.90#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.09:18:18.90#ibcon#ireg 17 cls_cnt 0 2006.173.09:18:18.90#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.09:18:18.90#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.09:18:18.90#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.09:18:18.90#ibcon#enter wrdev, iclass 29, count 0 2006.173.09:18:18.90#ibcon#first serial, iclass 29, count 0 2006.173.09:18:18.90#ibcon#enter sib2, iclass 29, count 0 2006.173.09:18:18.90#ibcon#flushed, iclass 29, count 0 2006.173.09:18:18.90#ibcon#about to write, iclass 29, count 0 2006.173.09:18:18.90#ibcon#wrote, iclass 29, count 0 2006.173.09:18:18.90#ibcon#about to read 3, iclass 29, count 0 2006.173.09:18:18.92#ibcon#read 3, iclass 29, count 0 2006.173.09:18:18.92#ibcon#about to read 4, iclass 29, count 0 2006.173.09:18:18.92#ibcon#read 4, iclass 29, count 0 2006.173.09:18:18.92#ibcon#about to read 5, iclass 29, count 0 2006.173.09:18:18.92#ibcon#read 5, iclass 29, count 0 2006.173.09:18:18.92#ibcon#about to read 6, iclass 29, count 0 2006.173.09:18:18.92#ibcon#read 6, iclass 29, count 0 2006.173.09:18:18.92#ibcon#end of sib2, iclass 29, count 0 2006.173.09:18:18.92#ibcon#*mode == 0, iclass 29, count 0 2006.173.09:18:18.92#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.09:18:18.92#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.09:18:18.92#ibcon#*before write, iclass 29, count 0 2006.173.09:18:18.92#ibcon#enter sib2, iclass 29, count 0 2006.173.09:18:18.92#ibcon#flushed, iclass 29, count 0 2006.173.09:18:18.92#ibcon#about to write, iclass 29, count 0 2006.173.09:18:18.92#ibcon#wrote, iclass 29, count 0 2006.173.09:18:18.92#ibcon#about to read 3, iclass 29, count 0 2006.173.09:18:18.96#ibcon#read 3, iclass 29, count 0 2006.173.09:18:18.96#ibcon#about to read 4, iclass 29, count 0 2006.173.09:18:18.96#ibcon#read 4, iclass 29, count 0 2006.173.09:18:18.96#ibcon#about to read 5, iclass 29, count 0 2006.173.09:18:18.96#ibcon#read 5, iclass 29, count 0 2006.173.09:18:18.96#ibcon#about to read 6, iclass 29, count 0 2006.173.09:18:18.96#ibcon#read 6, iclass 29, count 0 2006.173.09:18:18.96#ibcon#end of sib2, iclass 29, count 0 2006.173.09:18:18.96#ibcon#*after write, iclass 29, count 0 2006.173.09:18:18.96#ibcon#*before return 0, iclass 29, count 0 2006.173.09:18:18.96#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.09:18:18.96#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.09:18:18.96#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.09:18:18.96#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.09:18:18.96$vck44/va=6,3 2006.173.09:18:18.96#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.09:18:18.96#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.09:18:18.96#ibcon#ireg 11 cls_cnt 2 2006.173.09:18:18.96#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.09:18:19.02#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.09:18:19.02#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.09:18:19.02#ibcon#enter wrdev, iclass 31, count 2 2006.173.09:18:19.02#ibcon#first serial, iclass 31, count 2 2006.173.09:18:19.02#ibcon#enter sib2, iclass 31, count 2 2006.173.09:18:19.02#ibcon#flushed, iclass 31, count 2 2006.173.09:18:19.02#ibcon#about to write, iclass 31, count 2 2006.173.09:18:19.02#ibcon#wrote, iclass 31, count 2 2006.173.09:18:19.02#ibcon#about to read 3, iclass 31, count 2 2006.173.09:18:19.04#ibcon#read 3, iclass 31, count 2 2006.173.09:18:19.04#ibcon#about to read 4, iclass 31, count 2 2006.173.09:18:19.04#ibcon#read 4, iclass 31, count 2 2006.173.09:18:19.04#ibcon#about to read 5, iclass 31, count 2 2006.173.09:18:19.04#ibcon#read 5, iclass 31, count 2 2006.173.09:18:19.04#ibcon#about to read 6, iclass 31, count 2 2006.173.09:18:19.04#ibcon#read 6, iclass 31, count 2 2006.173.09:18:19.04#ibcon#end of sib2, iclass 31, count 2 2006.173.09:18:19.04#ibcon#*mode == 0, iclass 31, count 2 2006.173.09:18:19.04#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.09:18:19.04#ibcon#[25=AT06-03\r\n] 2006.173.09:18:19.04#ibcon#*before write, iclass 31, count 2 2006.173.09:18:19.04#ibcon#enter sib2, iclass 31, count 2 2006.173.09:18:19.04#ibcon#flushed, iclass 31, count 2 2006.173.09:18:19.04#ibcon#about to write, iclass 31, count 2 2006.173.09:18:19.04#ibcon#wrote, iclass 31, count 2 2006.173.09:18:19.04#ibcon#about to read 3, iclass 31, count 2 2006.173.09:18:19.07#ibcon#read 3, iclass 31, count 2 2006.173.09:18:19.07#ibcon#about to read 4, iclass 31, count 2 2006.173.09:18:19.07#ibcon#read 4, iclass 31, count 2 2006.173.09:18:19.07#ibcon#about to read 5, iclass 31, count 2 2006.173.09:18:19.07#ibcon#read 5, iclass 31, count 2 2006.173.09:18:19.07#ibcon#about to read 6, iclass 31, count 2 2006.173.09:18:19.07#ibcon#read 6, iclass 31, count 2 2006.173.09:18:19.07#ibcon#end of sib2, iclass 31, count 2 2006.173.09:18:19.07#ibcon#*after write, iclass 31, count 2 2006.173.09:18:19.07#ibcon#*before return 0, iclass 31, count 2 2006.173.09:18:19.07#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.09:18:19.07#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.09:18:19.07#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.09:18:19.07#ibcon#ireg 7 cls_cnt 0 2006.173.09:18:19.07#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.09:18:19.19#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.09:18:19.19#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.09:18:19.19#ibcon#enter wrdev, iclass 31, count 0 2006.173.09:18:19.19#ibcon#first serial, iclass 31, count 0 2006.173.09:18:19.19#ibcon#enter sib2, iclass 31, count 0 2006.173.09:18:19.19#ibcon#flushed, iclass 31, count 0 2006.173.09:18:19.19#ibcon#about to write, iclass 31, count 0 2006.173.09:18:19.19#ibcon#wrote, iclass 31, count 0 2006.173.09:18:19.19#ibcon#about to read 3, iclass 31, count 0 2006.173.09:18:19.21#ibcon#read 3, iclass 31, count 0 2006.173.09:18:19.21#ibcon#about to read 4, iclass 31, count 0 2006.173.09:18:19.21#ibcon#read 4, iclass 31, count 0 2006.173.09:18:19.21#ibcon#about to read 5, iclass 31, count 0 2006.173.09:18:19.21#ibcon#read 5, iclass 31, count 0 2006.173.09:18:19.21#ibcon#about to read 6, iclass 31, count 0 2006.173.09:18:19.21#ibcon#read 6, iclass 31, count 0 2006.173.09:18:19.21#ibcon#end of sib2, iclass 31, count 0 2006.173.09:18:19.21#ibcon#*mode == 0, iclass 31, count 0 2006.173.09:18:19.21#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.09:18:19.21#ibcon#[25=USB\r\n] 2006.173.09:18:19.21#ibcon#*before write, iclass 31, count 0 2006.173.09:18:19.21#ibcon#enter sib2, iclass 31, count 0 2006.173.09:18:19.21#ibcon#flushed, iclass 31, count 0 2006.173.09:18:19.21#ibcon#about to write, iclass 31, count 0 2006.173.09:18:19.21#ibcon#wrote, iclass 31, count 0 2006.173.09:18:19.21#ibcon#about to read 3, iclass 31, count 0 2006.173.09:18:19.24#ibcon#read 3, iclass 31, count 0 2006.173.09:18:19.24#ibcon#about to read 4, iclass 31, count 0 2006.173.09:18:19.24#ibcon#read 4, iclass 31, count 0 2006.173.09:18:19.24#ibcon#about to read 5, iclass 31, count 0 2006.173.09:18:19.24#ibcon#read 5, iclass 31, count 0 2006.173.09:18:19.24#ibcon#about to read 6, iclass 31, count 0 2006.173.09:18:19.24#ibcon#read 6, iclass 31, count 0 2006.173.09:18:19.24#ibcon#end of sib2, iclass 31, count 0 2006.173.09:18:19.24#ibcon#*after write, iclass 31, count 0 2006.173.09:18:19.24#ibcon#*before return 0, iclass 31, count 0 2006.173.09:18:19.24#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.09:18:19.24#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.09:18:19.24#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.09:18:19.24#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.09:18:19.24$vck44/valo=7,864.99 2006.173.09:18:19.24#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.09:18:19.24#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.09:18:19.24#ibcon#ireg 17 cls_cnt 0 2006.173.09:18:19.24#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.09:18:19.24#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.09:18:19.24#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.09:18:19.24#ibcon#enter wrdev, iclass 33, count 0 2006.173.09:18:19.24#ibcon#first serial, iclass 33, count 0 2006.173.09:18:19.24#ibcon#enter sib2, iclass 33, count 0 2006.173.09:18:19.24#ibcon#flushed, iclass 33, count 0 2006.173.09:18:19.24#ibcon#about to write, iclass 33, count 0 2006.173.09:18:19.24#ibcon#wrote, iclass 33, count 0 2006.173.09:18:19.24#ibcon#about to read 3, iclass 33, count 0 2006.173.09:18:19.26#ibcon#read 3, iclass 33, count 0 2006.173.09:18:19.26#ibcon#about to read 4, iclass 33, count 0 2006.173.09:18:19.26#ibcon#read 4, iclass 33, count 0 2006.173.09:18:19.26#ibcon#about to read 5, iclass 33, count 0 2006.173.09:18:19.26#ibcon#read 5, iclass 33, count 0 2006.173.09:18:19.26#ibcon#about to read 6, iclass 33, count 0 2006.173.09:18:19.26#ibcon#read 6, iclass 33, count 0 2006.173.09:18:19.26#ibcon#end of sib2, iclass 33, count 0 2006.173.09:18:19.26#ibcon#*mode == 0, iclass 33, count 0 2006.173.09:18:19.26#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.09:18:19.26#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.09:18:19.26#ibcon#*before write, iclass 33, count 0 2006.173.09:18:19.26#ibcon#enter sib2, iclass 33, count 0 2006.173.09:18:19.26#ibcon#flushed, iclass 33, count 0 2006.173.09:18:19.26#ibcon#about to write, iclass 33, count 0 2006.173.09:18:19.26#ibcon#wrote, iclass 33, count 0 2006.173.09:18:19.26#ibcon#about to read 3, iclass 33, count 0 2006.173.09:18:19.30#ibcon#read 3, iclass 33, count 0 2006.173.09:18:19.30#ibcon#about to read 4, iclass 33, count 0 2006.173.09:18:19.30#ibcon#read 4, iclass 33, count 0 2006.173.09:18:19.30#ibcon#about to read 5, iclass 33, count 0 2006.173.09:18:19.30#ibcon#read 5, iclass 33, count 0 2006.173.09:18:19.30#ibcon#about to read 6, iclass 33, count 0 2006.173.09:18:19.30#ibcon#read 6, iclass 33, count 0 2006.173.09:18:19.30#ibcon#end of sib2, iclass 33, count 0 2006.173.09:18:19.30#ibcon#*after write, iclass 33, count 0 2006.173.09:18:19.30#ibcon#*before return 0, iclass 33, count 0 2006.173.09:18:19.30#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.09:18:19.30#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.09:18:19.30#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.09:18:19.30#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.09:18:19.30$vck44/va=7,4 2006.173.09:18:19.30#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.09:18:19.30#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.09:18:19.30#ibcon#ireg 11 cls_cnt 2 2006.173.09:18:19.30#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.09:18:19.36#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.09:18:19.36#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.09:18:19.36#ibcon#enter wrdev, iclass 35, count 2 2006.173.09:18:19.36#ibcon#first serial, iclass 35, count 2 2006.173.09:18:19.36#ibcon#enter sib2, iclass 35, count 2 2006.173.09:18:19.36#ibcon#flushed, iclass 35, count 2 2006.173.09:18:19.36#ibcon#about to write, iclass 35, count 2 2006.173.09:18:19.36#ibcon#wrote, iclass 35, count 2 2006.173.09:18:19.36#ibcon#about to read 3, iclass 35, count 2 2006.173.09:18:19.38#ibcon#read 3, iclass 35, count 2 2006.173.09:18:19.38#ibcon#about to read 4, iclass 35, count 2 2006.173.09:18:19.38#ibcon#read 4, iclass 35, count 2 2006.173.09:18:19.38#ibcon#about to read 5, iclass 35, count 2 2006.173.09:18:19.38#ibcon#read 5, iclass 35, count 2 2006.173.09:18:19.38#ibcon#about to read 6, iclass 35, count 2 2006.173.09:18:19.38#ibcon#read 6, iclass 35, count 2 2006.173.09:18:19.38#ibcon#end of sib2, iclass 35, count 2 2006.173.09:18:19.38#ibcon#*mode == 0, iclass 35, count 2 2006.173.09:18:19.38#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.09:18:19.38#ibcon#[25=AT07-04\r\n] 2006.173.09:18:19.38#ibcon#*before write, iclass 35, count 2 2006.173.09:18:19.38#ibcon#enter sib2, iclass 35, count 2 2006.173.09:18:19.38#ibcon#flushed, iclass 35, count 2 2006.173.09:18:19.38#ibcon#about to write, iclass 35, count 2 2006.173.09:18:19.38#ibcon#wrote, iclass 35, count 2 2006.173.09:18:19.38#ibcon#about to read 3, iclass 35, count 2 2006.173.09:18:19.41#ibcon#read 3, iclass 35, count 2 2006.173.09:18:19.41#ibcon#about to read 4, iclass 35, count 2 2006.173.09:18:19.41#ibcon#read 4, iclass 35, count 2 2006.173.09:18:19.41#ibcon#about to read 5, iclass 35, count 2 2006.173.09:18:19.41#ibcon#read 5, iclass 35, count 2 2006.173.09:18:19.41#ibcon#about to read 6, iclass 35, count 2 2006.173.09:18:19.41#ibcon#read 6, iclass 35, count 2 2006.173.09:18:19.41#ibcon#end of sib2, iclass 35, count 2 2006.173.09:18:19.41#ibcon#*after write, iclass 35, count 2 2006.173.09:18:19.41#ibcon#*before return 0, iclass 35, count 2 2006.173.09:18:19.41#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.09:18:19.41#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.09:18:19.41#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.09:18:19.41#ibcon#ireg 7 cls_cnt 0 2006.173.09:18:19.41#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.09:18:19.53#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.09:18:19.53#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.09:18:19.53#ibcon#enter wrdev, iclass 35, count 0 2006.173.09:18:19.53#ibcon#first serial, iclass 35, count 0 2006.173.09:18:19.53#ibcon#enter sib2, iclass 35, count 0 2006.173.09:18:19.53#ibcon#flushed, iclass 35, count 0 2006.173.09:18:19.53#ibcon#about to write, iclass 35, count 0 2006.173.09:18:19.53#ibcon#wrote, iclass 35, count 0 2006.173.09:18:19.53#ibcon#about to read 3, iclass 35, count 0 2006.173.09:18:19.55#ibcon#read 3, iclass 35, count 0 2006.173.09:18:19.55#ibcon#about to read 4, iclass 35, count 0 2006.173.09:18:19.55#ibcon#read 4, iclass 35, count 0 2006.173.09:18:19.55#ibcon#about to read 5, iclass 35, count 0 2006.173.09:18:19.55#ibcon#read 5, iclass 35, count 0 2006.173.09:18:19.55#ibcon#about to read 6, iclass 35, count 0 2006.173.09:18:19.55#ibcon#read 6, iclass 35, count 0 2006.173.09:18:19.55#ibcon#end of sib2, iclass 35, count 0 2006.173.09:18:19.55#ibcon#*mode == 0, iclass 35, count 0 2006.173.09:18:19.55#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.09:18:19.55#ibcon#[25=USB\r\n] 2006.173.09:18:19.55#ibcon#*before write, iclass 35, count 0 2006.173.09:18:19.55#ibcon#enter sib2, iclass 35, count 0 2006.173.09:18:19.55#ibcon#flushed, iclass 35, count 0 2006.173.09:18:19.55#ibcon#about to write, iclass 35, count 0 2006.173.09:18:19.55#ibcon#wrote, iclass 35, count 0 2006.173.09:18:19.55#ibcon#about to read 3, iclass 35, count 0 2006.173.09:18:19.58#ibcon#read 3, iclass 35, count 0 2006.173.09:18:19.58#ibcon#about to read 4, iclass 35, count 0 2006.173.09:18:19.58#ibcon#read 4, iclass 35, count 0 2006.173.09:18:19.58#ibcon#about to read 5, iclass 35, count 0 2006.173.09:18:19.58#ibcon#read 5, iclass 35, count 0 2006.173.09:18:19.58#ibcon#about to read 6, iclass 35, count 0 2006.173.09:18:19.58#ibcon#read 6, iclass 35, count 0 2006.173.09:18:19.58#ibcon#end of sib2, iclass 35, count 0 2006.173.09:18:19.58#ibcon#*after write, iclass 35, count 0 2006.173.09:18:19.58#ibcon#*before return 0, iclass 35, count 0 2006.173.09:18:19.58#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.09:18:19.58#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.09:18:19.58#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.09:18:19.58#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.09:18:19.58$vck44/valo=8,884.99 2006.173.09:18:19.58#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.09:18:19.58#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.09:18:19.58#ibcon#ireg 17 cls_cnt 0 2006.173.09:18:19.58#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.09:18:19.58#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.09:18:19.58#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.09:18:19.58#ibcon#enter wrdev, iclass 37, count 0 2006.173.09:18:19.58#ibcon#first serial, iclass 37, count 0 2006.173.09:18:19.58#ibcon#enter sib2, iclass 37, count 0 2006.173.09:18:19.58#ibcon#flushed, iclass 37, count 0 2006.173.09:18:19.58#ibcon#about to write, iclass 37, count 0 2006.173.09:18:19.58#ibcon#wrote, iclass 37, count 0 2006.173.09:18:19.58#ibcon#about to read 3, iclass 37, count 0 2006.173.09:18:19.60#ibcon#read 3, iclass 37, count 0 2006.173.09:18:19.60#ibcon#about to read 4, iclass 37, count 0 2006.173.09:18:19.60#ibcon#read 4, iclass 37, count 0 2006.173.09:18:19.60#ibcon#about to read 5, iclass 37, count 0 2006.173.09:18:19.60#ibcon#read 5, iclass 37, count 0 2006.173.09:18:19.60#ibcon#about to read 6, iclass 37, count 0 2006.173.09:18:19.60#ibcon#read 6, iclass 37, count 0 2006.173.09:18:19.60#ibcon#end of sib2, iclass 37, count 0 2006.173.09:18:19.60#ibcon#*mode == 0, iclass 37, count 0 2006.173.09:18:19.60#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.09:18:19.60#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.09:18:19.60#ibcon#*before write, iclass 37, count 0 2006.173.09:18:19.60#ibcon#enter sib2, iclass 37, count 0 2006.173.09:18:19.60#ibcon#flushed, iclass 37, count 0 2006.173.09:18:19.60#ibcon#about to write, iclass 37, count 0 2006.173.09:18:19.60#ibcon#wrote, iclass 37, count 0 2006.173.09:18:19.60#ibcon#about to read 3, iclass 37, count 0 2006.173.09:18:19.64#ibcon#read 3, iclass 37, count 0 2006.173.09:18:19.64#ibcon#about to read 4, iclass 37, count 0 2006.173.09:18:19.64#ibcon#read 4, iclass 37, count 0 2006.173.09:18:19.64#ibcon#about to read 5, iclass 37, count 0 2006.173.09:18:19.64#ibcon#read 5, iclass 37, count 0 2006.173.09:18:19.64#ibcon#about to read 6, iclass 37, count 0 2006.173.09:18:19.64#ibcon#read 6, iclass 37, count 0 2006.173.09:18:19.64#ibcon#end of sib2, iclass 37, count 0 2006.173.09:18:19.64#ibcon#*after write, iclass 37, count 0 2006.173.09:18:19.64#ibcon#*before return 0, iclass 37, count 0 2006.173.09:18:19.64#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.09:18:19.64#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.09:18:19.64#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.09:18:19.64#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.09:18:19.64$vck44/va=8,4 2006.173.09:18:19.64#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.09:18:19.64#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.09:18:19.64#ibcon#ireg 11 cls_cnt 2 2006.173.09:18:19.64#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.09:18:19.70#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.09:18:19.70#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.09:18:19.70#ibcon#enter wrdev, iclass 39, count 2 2006.173.09:18:19.70#ibcon#first serial, iclass 39, count 2 2006.173.09:18:19.70#ibcon#enter sib2, iclass 39, count 2 2006.173.09:18:19.70#ibcon#flushed, iclass 39, count 2 2006.173.09:18:19.70#ibcon#about to write, iclass 39, count 2 2006.173.09:18:19.70#ibcon#wrote, iclass 39, count 2 2006.173.09:18:19.70#ibcon#about to read 3, iclass 39, count 2 2006.173.09:18:19.72#ibcon#read 3, iclass 39, count 2 2006.173.09:18:19.72#ibcon#about to read 4, iclass 39, count 2 2006.173.09:18:19.72#ibcon#read 4, iclass 39, count 2 2006.173.09:18:19.72#ibcon#about to read 5, iclass 39, count 2 2006.173.09:18:19.72#ibcon#read 5, iclass 39, count 2 2006.173.09:18:19.72#ibcon#about to read 6, iclass 39, count 2 2006.173.09:18:19.72#ibcon#read 6, iclass 39, count 2 2006.173.09:18:19.72#ibcon#end of sib2, iclass 39, count 2 2006.173.09:18:19.72#ibcon#*mode == 0, iclass 39, count 2 2006.173.09:18:19.72#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.09:18:19.72#ibcon#[25=AT08-04\r\n] 2006.173.09:18:19.72#ibcon#*before write, iclass 39, count 2 2006.173.09:18:19.72#ibcon#enter sib2, iclass 39, count 2 2006.173.09:18:19.72#ibcon#flushed, iclass 39, count 2 2006.173.09:18:19.72#ibcon#about to write, iclass 39, count 2 2006.173.09:18:19.72#ibcon#wrote, iclass 39, count 2 2006.173.09:18:19.72#ibcon#about to read 3, iclass 39, count 2 2006.173.09:18:19.75#ibcon#read 3, iclass 39, count 2 2006.173.09:18:19.75#ibcon#about to read 4, iclass 39, count 2 2006.173.09:18:19.75#ibcon#read 4, iclass 39, count 2 2006.173.09:18:19.75#ibcon#about to read 5, iclass 39, count 2 2006.173.09:18:19.75#ibcon#read 5, iclass 39, count 2 2006.173.09:18:19.75#ibcon#about to read 6, iclass 39, count 2 2006.173.09:18:19.75#ibcon#read 6, iclass 39, count 2 2006.173.09:18:19.75#ibcon#end of sib2, iclass 39, count 2 2006.173.09:18:19.75#ibcon#*after write, iclass 39, count 2 2006.173.09:18:19.75#ibcon#*before return 0, iclass 39, count 2 2006.173.09:18:19.75#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.09:18:19.75#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.09:18:19.75#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.09:18:19.75#ibcon#ireg 7 cls_cnt 0 2006.173.09:18:19.75#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.09:18:19.87#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.09:18:19.87#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.09:18:19.87#ibcon#enter wrdev, iclass 39, count 0 2006.173.09:18:19.87#ibcon#first serial, iclass 39, count 0 2006.173.09:18:19.87#ibcon#enter sib2, iclass 39, count 0 2006.173.09:18:19.87#ibcon#flushed, iclass 39, count 0 2006.173.09:18:19.87#ibcon#about to write, iclass 39, count 0 2006.173.09:18:19.87#ibcon#wrote, iclass 39, count 0 2006.173.09:18:19.87#ibcon#about to read 3, iclass 39, count 0 2006.173.09:18:19.89#ibcon#read 3, iclass 39, count 0 2006.173.09:18:19.89#ibcon#about to read 4, iclass 39, count 0 2006.173.09:18:19.89#ibcon#read 4, iclass 39, count 0 2006.173.09:18:19.89#ibcon#about to read 5, iclass 39, count 0 2006.173.09:18:19.89#ibcon#read 5, iclass 39, count 0 2006.173.09:18:19.89#ibcon#about to read 6, iclass 39, count 0 2006.173.09:18:19.89#ibcon#read 6, iclass 39, count 0 2006.173.09:18:19.89#ibcon#end of sib2, iclass 39, count 0 2006.173.09:18:19.89#ibcon#*mode == 0, iclass 39, count 0 2006.173.09:18:19.89#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.09:18:19.89#ibcon#[25=USB\r\n] 2006.173.09:18:19.89#ibcon#*before write, iclass 39, count 0 2006.173.09:18:19.89#ibcon#enter sib2, iclass 39, count 0 2006.173.09:18:19.89#ibcon#flushed, iclass 39, count 0 2006.173.09:18:19.89#ibcon#about to write, iclass 39, count 0 2006.173.09:18:19.89#ibcon#wrote, iclass 39, count 0 2006.173.09:18:19.89#ibcon#about to read 3, iclass 39, count 0 2006.173.09:18:19.92#ibcon#read 3, iclass 39, count 0 2006.173.09:18:19.92#ibcon#about to read 4, iclass 39, count 0 2006.173.09:18:19.92#ibcon#read 4, iclass 39, count 0 2006.173.09:18:19.92#ibcon#about to read 5, iclass 39, count 0 2006.173.09:18:19.92#ibcon#read 5, iclass 39, count 0 2006.173.09:18:19.92#ibcon#about to read 6, iclass 39, count 0 2006.173.09:18:19.92#ibcon#read 6, iclass 39, count 0 2006.173.09:18:19.92#ibcon#end of sib2, iclass 39, count 0 2006.173.09:18:19.92#ibcon#*after write, iclass 39, count 0 2006.173.09:18:19.92#ibcon#*before return 0, iclass 39, count 0 2006.173.09:18:19.92#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.09:18:19.92#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.09:18:19.92#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.09:18:19.92#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.09:18:19.92$vck44/vblo=1,629.99 2006.173.09:18:19.92#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.09:18:19.92#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.09:18:19.92#ibcon#ireg 17 cls_cnt 0 2006.173.09:18:19.92#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.09:18:19.92#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.09:18:19.92#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.09:18:19.92#ibcon#enter wrdev, iclass 3, count 0 2006.173.09:18:19.92#ibcon#first serial, iclass 3, count 0 2006.173.09:18:19.92#ibcon#enter sib2, iclass 3, count 0 2006.173.09:18:19.92#ibcon#flushed, iclass 3, count 0 2006.173.09:18:19.92#ibcon#about to write, iclass 3, count 0 2006.173.09:18:19.92#ibcon#wrote, iclass 3, count 0 2006.173.09:18:19.92#ibcon#about to read 3, iclass 3, count 0 2006.173.09:18:19.94#ibcon#read 3, iclass 3, count 0 2006.173.09:18:19.94#ibcon#about to read 4, iclass 3, count 0 2006.173.09:18:19.94#ibcon#read 4, iclass 3, count 0 2006.173.09:18:19.94#ibcon#about to read 5, iclass 3, count 0 2006.173.09:18:19.94#ibcon#read 5, iclass 3, count 0 2006.173.09:18:19.94#ibcon#about to read 6, iclass 3, count 0 2006.173.09:18:19.94#ibcon#read 6, iclass 3, count 0 2006.173.09:18:19.94#ibcon#end of sib2, iclass 3, count 0 2006.173.09:18:19.94#ibcon#*mode == 0, iclass 3, count 0 2006.173.09:18:19.94#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.09:18:19.94#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.09:18:19.94#ibcon#*before write, iclass 3, count 0 2006.173.09:18:19.94#ibcon#enter sib2, iclass 3, count 0 2006.173.09:18:19.94#ibcon#flushed, iclass 3, count 0 2006.173.09:18:19.94#ibcon#about to write, iclass 3, count 0 2006.173.09:18:19.94#ibcon#wrote, iclass 3, count 0 2006.173.09:18:19.94#ibcon#about to read 3, iclass 3, count 0 2006.173.09:18:19.98#ibcon#read 3, iclass 3, count 0 2006.173.09:18:19.98#ibcon#about to read 4, iclass 3, count 0 2006.173.09:18:19.98#ibcon#read 4, iclass 3, count 0 2006.173.09:18:19.98#ibcon#about to read 5, iclass 3, count 0 2006.173.09:18:19.98#ibcon#read 5, iclass 3, count 0 2006.173.09:18:19.98#ibcon#about to read 6, iclass 3, count 0 2006.173.09:18:19.98#ibcon#read 6, iclass 3, count 0 2006.173.09:18:19.98#ibcon#end of sib2, iclass 3, count 0 2006.173.09:18:19.98#ibcon#*after write, iclass 3, count 0 2006.173.09:18:19.98#ibcon#*before return 0, iclass 3, count 0 2006.173.09:18:19.98#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.09:18:19.98#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.09:18:19.98#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.09:18:19.98#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.09:18:19.98$vck44/vb=1,4 2006.173.09:18:19.98#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.09:18:19.98#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.09:18:19.98#ibcon#ireg 11 cls_cnt 2 2006.173.09:18:19.98#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.09:18:19.98#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.09:18:19.98#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.09:18:19.98#ibcon#enter wrdev, iclass 5, count 2 2006.173.09:18:19.98#ibcon#first serial, iclass 5, count 2 2006.173.09:18:19.98#ibcon#enter sib2, iclass 5, count 2 2006.173.09:18:19.98#ibcon#flushed, iclass 5, count 2 2006.173.09:18:19.98#ibcon#about to write, iclass 5, count 2 2006.173.09:18:19.98#ibcon#wrote, iclass 5, count 2 2006.173.09:18:19.98#ibcon#about to read 3, iclass 5, count 2 2006.173.09:18:20.00#ibcon#read 3, iclass 5, count 2 2006.173.09:18:20.00#ibcon#about to read 4, iclass 5, count 2 2006.173.09:18:20.00#ibcon#read 4, iclass 5, count 2 2006.173.09:18:20.00#ibcon#about to read 5, iclass 5, count 2 2006.173.09:18:20.00#ibcon#read 5, iclass 5, count 2 2006.173.09:18:20.00#ibcon#about to read 6, iclass 5, count 2 2006.173.09:18:20.00#ibcon#read 6, iclass 5, count 2 2006.173.09:18:20.00#ibcon#end of sib2, iclass 5, count 2 2006.173.09:18:20.00#ibcon#*mode == 0, iclass 5, count 2 2006.173.09:18:20.00#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.09:18:20.00#ibcon#[27=AT01-04\r\n] 2006.173.09:18:20.00#ibcon#*before write, iclass 5, count 2 2006.173.09:18:20.00#ibcon#enter sib2, iclass 5, count 2 2006.173.09:18:20.00#ibcon#flushed, iclass 5, count 2 2006.173.09:18:20.00#ibcon#about to write, iclass 5, count 2 2006.173.09:18:20.00#ibcon#wrote, iclass 5, count 2 2006.173.09:18:20.00#ibcon#about to read 3, iclass 5, count 2 2006.173.09:18:20.03#ibcon#read 3, iclass 5, count 2 2006.173.09:18:20.03#ibcon#about to read 4, iclass 5, count 2 2006.173.09:18:20.03#ibcon#read 4, iclass 5, count 2 2006.173.09:18:20.03#ibcon#about to read 5, iclass 5, count 2 2006.173.09:18:20.03#ibcon#read 5, iclass 5, count 2 2006.173.09:18:20.03#ibcon#about to read 6, iclass 5, count 2 2006.173.09:18:20.03#ibcon#read 6, iclass 5, count 2 2006.173.09:18:20.03#ibcon#end of sib2, iclass 5, count 2 2006.173.09:18:20.03#ibcon#*after write, iclass 5, count 2 2006.173.09:18:20.03#ibcon#*before return 0, iclass 5, count 2 2006.173.09:18:20.03#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.09:18:20.03#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.09:18:20.03#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.09:18:20.03#ibcon#ireg 7 cls_cnt 0 2006.173.09:18:20.03#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.09:18:20.15#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.09:18:20.15#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.09:18:20.15#ibcon#enter wrdev, iclass 5, count 0 2006.173.09:18:20.15#ibcon#first serial, iclass 5, count 0 2006.173.09:18:20.15#ibcon#enter sib2, iclass 5, count 0 2006.173.09:18:20.15#ibcon#flushed, iclass 5, count 0 2006.173.09:18:20.15#ibcon#about to write, iclass 5, count 0 2006.173.09:18:20.15#ibcon#wrote, iclass 5, count 0 2006.173.09:18:20.15#ibcon#about to read 3, iclass 5, count 0 2006.173.09:18:20.17#ibcon#read 3, iclass 5, count 0 2006.173.09:18:20.17#ibcon#about to read 4, iclass 5, count 0 2006.173.09:18:20.17#ibcon#read 4, iclass 5, count 0 2006.173.09:18:20.17#ibcon#about to read 5, iclass 5, count 0 2006.173.09:18:20.17#ibcon#read 5, iclass 5, count 0 2006.173.09:18:20.17#ibcon#about to read 6, iclass 5, count 0 2006.173.09:18:20.17#ibcon#read 6, iclass 5, count 0 2006.173.09:18:20.17#ibcon#end of sib2, iclass 5, count 0 2006.173.09:18:20.17#ibcon#*mode == 0, iclass 5, count 0 2006.173.09:18:20.17#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.09:18:20.17#ibcon#[27=USB\r\n] 2006.173.09:18:20.17#ibcon#*before write, iclass 5, count 0 2006.173.09:18:20.17#ibcon#enter sib2, iclass 5, count 0 2006.173.09:18:20.17#ibcon#flushed, iclass 5, count 0 2006.173.09:18:20.17#ibcon#about to write, iclass 5, count 0 2006.173.09:18:20.17#ibcon#wrote, iclass 5, count 0 2006.173.09:18:20.17#ibcon#about to read 3, iclass 5, count 0 2006.173.09:18:20.20#ibcon#read 3, iclass 5, count 0 2006.173.09:18:20.20#ibcon#about to read 4, iclass 5, count 0 2006.173.09:18:20.20#ibcon#read 4, iclass 5, count 0 2006.173.09:18:20.20#ibcon#about to read 5, iclass 5, count 0 2006.173.09:18:20.20#ibcon#read 5, iclass 5, count 0 2006.173.09:18:20.20#ibcon#about to read 6, iclass 5, count 0 2006.173.09:18:20.20#ibcon#read 6, iclass 5, count 0 2006.173.09:18:20.20#ibcon#end of sib2, iclass 5, count 0 2006.173.09:18:20.20#ibcon#*after write, iclass 5, count 0 2006.173.09:18:20.20#ibcon#*before return 0, iclass 5, count 0 2006.173.09:18:20.20#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.09:18:20.20#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.09:18:20.20#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.09:18:20.20#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.09:18:20.20$vck44/vblo=2,634.99 2006.173.09:18:20.20#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.09:18:20.20#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.09:18:20.20#ibcon#ireg 17 cls_cnt 0 2006.173.09:18:20.20#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.09:18:20.20#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.09:18:20.20#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.09:18:20.20#ibcon#enter wrdev, iclass 7, count 0 2006.173.09:18:20.20#ibcon#first serial, iclass 7, count 0 2006.173.09:18:20.20#ibcon#enter sib2, iclass 7, count 0 2006.173.09:18:20.20#ibcon#flushed, iclass 7, count 0 2006.173.09:18:20.20#ibcon#about to write, iclass 7, count 0 2006.173.09:18:20.20#ibcon#wrote, iclass 7, count 0 2006.173.09:18:20.20#ibcon#about to read 3, iclass 7, count 0 2006.173.09:18:20.22#ibcon#read 3, iclass 7, count 0 2006.173.09:18:20.22#ibcon#about to read 4, iclass 7, count 0 2006.173.09:18:20.22#ibcon#read 4, iclass 7, count 0 2006.173.09:18:20.22#ibcon#about to read 5, iclass 7, count 0 2006.173.09:18:20.22#ibcon#read 5, iclass 7, count 0 2006.173.09:18:20.22#ibcon#about to read 6, iclass 7, count 0 2006.173.09:18:20.22#ibcon#read 6, iclass 7, count 0 2006.173.09:18:20.22#ibcon#end of sib2, iclass 7, count 0 2006.173.09:18:20.22#ibcon#*mode == 0, iclass 7, count 0 2006.173.09:18:20.22#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.09:18:20.22#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.09:18:20.22#ibcon#*before write, iclass 7, count 0 2006.173.09:18:20.22#ibcon#enter sib2, iclass 7, count 0 2006.173.09:18:20.22#ibcon#flushed, iclass 7, count 0 2006.173.09:18:20.22#ibcon#about to write, iclass 7, count 0 2006.173.09:18:20.22#ibcon#wrote, iclass 7, count 0 2006.173.09:18:20.22#ibcon#about to read 3, iclass 7, count 0 2006.173.09:18:20.26#ibcon#read 3, iclass 7, count 0 2006.173.09:18:20.26#ibcon#about to read 4, iclass 7, count 0 2006.173.09:18:20.26#ibcon#read 4, iclass 7, count 0 2006.173.09:18:20.26#ibcon#about to read 5, iclass 7, count 0 2006.173.09:18:20.26#ibcon#read 5, iclass 7, count 0 2006.173.09:18:20.26#ibcon#about to read 6, iclass 7, count 0 2006.173.09:18:20.26#ibcon#read 6, iclass 7, count 0 2006.173.09:18:20.26#ibcon#end of sib2, iclass 7, count 0 2006.173.09:18:20.26#ibcon#*after write, iclass 7, count 0 2006.173.09:18:20.26#ibcon#*before return 0, iclass 7, count 0 2006.173.09:18:20.26#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.09:18:20.26#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.09:18:20.26#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.09:18:20.26#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.09:18:20.26$vck44/vb=2,4 2006.173.09:18:20.26#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.09:18:20.26#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.09:18:20.26#ibcon#ireg 11 cls_cnt 2 2006.173.09:18:20.26#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.09:18:20.32#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.09:18:20.32#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.09:18:20.32#ibcon#enter wrdev, iclass 11, count 2 2006.173.09:18:20.32#ibcon#first serial, iclass 11, count 2 2006.173.09:18:20.32#ibcon#enter sib2, iclass 11, count 2 2006.173.09:18:20.32#ibcon#flushed, iclass 11, count 2 2006.173.09:18:20.32#ibcon#about to write, iclass 11, count 2 2006.173.09:18:20.32#ibcon#wrote, iclass 11, count 2 2006.173.09:18:20.32#ibcon#about to read 3, iclass 11, count 2 2006.173.09:18:20.34#ibcon#read 3, iclass 11, count 2 2006.173.09:18:20.34#ibcon#about to read 4, iclass 11, count 2 2006.173.09:18:20.34#ibcon#read 4, iclass 11, count 2 2006.173.09:18:20.34#ibcon#about to read 5, iclass 11, count 2 2006.173.09:18:20.34#ibcon#read 5, iclass 11, count 2 2006.173.09:18:20.34#ibcon#about to read 6, iclass 11, count 2 2006.173.09:18:20.34#ibcon#read 6, iclass 11, count 2 2006.173.09:18:20.34#ibcon#end of sib2, iclass 11, count 2 2006.173.09:18:20.34#ibcon#*mode == 0, iclass 11, count 2 2006.173.09:18:20.34#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.09:18:20.34#ibcon#[27=AT02-04\r\n] 2006.173.09:18:20.34#ibcon#*before write, iclass 11, count 2 2006.173.09:18:20.34#ibcon#enter sib2, iclass 11, count 2 2006.173.09:18:20.34#ibcon#flushed, iclass 11, count 2 2006.173.09:18:20.34#ibcon#about to write, iclass 11, count 2 2006.173.09:18:20.34#ibcon#wrote, iclass 11, count 2 2006.173.09:18:20.34#ibcon#about to read 3, iclass 11, count 2 2006.173.09:18:20.37#ibcon#read 3, iclass 11, count 2 2006.173.09:18:20.37#ibcon#about to read 4, iclass 11, count 2 2006.173.09:18:20.37#ibcon#read 4, iclass 11, count 2 2006.173.09:18:20.37#ibcon#about to read 5, iclass 11, count 2 2006.173.09:18:20.37#ibcon#read 5, iclass 11, count 2 2006.173.09:18:20.37#ibcon#about to read 6, iclass 11, count 2 2006.173.09:18:20.37#ibcon#read 6, iclass 11, count 2 2006.173.09:18:20.37#ibcon#end of sib2, iclass 11, count 2 2006.173.09:18:20.37#ibcon#*after write, iclass 11, count 2 2006.173.09:18:20.37#ibcon#*before return 0, iclass 11, count 2 2006.173.09:18:20.37#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.09:18:20.37#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.09:18:20.37#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.09:18:20.37#ibcon#ireg 7 cls_cnt 0 2006.173.09:18:20.37#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.09:18:20.49#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.09:18:20.49#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.09:18:20.49#ibcon#enter wrdev, iclass 11, count 0 2006.173.09:18:20.49#ibcon#first serial, iclass 11, count 0 2006.173.09:18:20.49#ibcon#enter sib2, iclass 11, count 0 2006.173.09:18:20.49#ibcon#flushed, iclass 11, count 0 2006.173.09:18:20.49#ibcon#about to write, iclass 11, count 0 2006.173.09:18:20.49#ibcon#wrote, iclass 11, count 0 2006.173.09:18:20.49#ibcon#about to read 3, iclass 11, count 0 2006.173.09:18:20.51#ibcon#read 3, iclass 11, count 0 2006.173.09:18:20.51#ibcon#about to read 4, iclass 11, count 0 2006.173.09:18:20.51#ibcon#read 4, iclass 11, count 0 2006.173.09:18:20.51#ibcon#about to read 5, iclass 11, count 0 2006.173.09:18:20.51#ibcon#read 5, iclass 11, count 0 2006.173.09:18:20.51#ibcon#about to read 6, iclass 11, count 0 2006.173.09:18:20.51#ibcon#read 6, iclass 11, count 0 2006.173.09:18:20.51#ibcon#end of sib2, iclass 11, count 0 2006.173.09:18:20.51#ibcon#*mode == 0, iclass 11, count 0 2006.173.09:18:20.51#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.09:18:20.51#ibcon#[27=USB\r\n] 2006.173.09:18:20.51#ibcon#*before write, iclass 11, count 0 2006.173.09:18:20.51#ibcon#enter sib2, iclass 11, count 0 2006.173.09:18:20.51#ibcon#flushed, iclass 11, count 0 2006.173.09:18:20.51#ibcon#about to write, iclass 11, count 0 2006.173.09:18:20.51#ibcon#wrote, iclass 11, count 0 2006.173.09:18:20.51#ibcon#about to read 3, iclass 11, count 0 2006.173.09:18:20.54#ibcon#read 3, iclass 11, count 0 2006.173.09:18:20.54#ibcon#about to read 4, iclass 11, count 0 2006.173.09:18:20.54#ibcon#read 4, iclass 11, count 0 2006.173.09:18:20.54#ibcon#about to read 5, iclass 11, count 0 2006.173.09:18:20.54#ibcon#read 5, iclass 11, count 0 2006.173.09:18:20.54#ibcon#about to read 6, iclass 11, count 0 2006.173.09:18:20.54#ibcon#read 6, iclass 11, count 0 2006.173.09:18:20.54#ibcon#end of sib2, iclass 11, count 0 2006.173.09:18:20.54#ibcon#*after write, iclass 11, count 0 2006.173.09:18:20.54#ibcon#*before return 0, iclass 11, count 0 2006.173.09:18:20.54#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.09:18:20.54#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.09:18:20.54#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.09:18:20.54#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.09:18:20.54$vck44/vblo=3,649.99 2006.173.09:18:20.54#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.09:18:20.54#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.09:18:20.54#ibcon#ireg 17 cls_cnt 0 2006.173.09:18:20.54#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.09:18:20.54#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.09:18:20.54#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.09:18:20.54#ibcon#enter wrdev, iclass 13, count 0 2006.173.09:18:20.54#ibcon#first serial, iclass 13, count 0 2006.173.09:18:20.54#ibcon#enter sib2, iclass 13, count 0 2006.173.09:18:20.54#ibcon#flushed, iclass 13, count 0 2006.173.09:18:20.54#ibcon#about to write, iclass 13, count 0 2006.173.09:18:20.54#ibcon#wrote, iclass 13, count 0 2006.173.09:18:20.54#ibcon#about to read 3, iclass 13, count 0 2006.173.09:18:20.56#ibcon#read 3, iclass 13, count 0 2006.173.09:18:20.56#ibcon#about to read 4, iclass 13, count 0 2006.173.09:18:20.56#ibcon#read 4, iclass 13, count 0 2006.173.09:18:20.56#ibcon#about to read 5, iclass 13, count 0 2006.173.09:18:20.56#ibcon#read 5, iclass 13, count 0 2006.173.09:18:20.56#ibcon#about to read 6, iclass 13, count 0 2006.173.09:18:20.56#ibcon#read 6, iclass 13, count 0 2006.173.09:18:20.56#ibcon#end of sib2, iclass 13, count 0 2006.173.09:18:20.56#ibcon#*mode == 0, iclass 13, count 0 2006.173.09:18:20.56#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.09:18:20.56#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.09:18:20.56#ibcon#*before write, iclass 13, count 0 2006.173.09:18:20.56#ibcon#enter sib2, iclass 13, count 0 2006.173.09:18:20.56#ibcon#flushed, iclass 13, count 0 2006.173.09:18:20.56#ibcon#about to write, iclass 13, count 0 2006.173.09:18:20.56#ibcon#wrote, iclass 13, count 0 2006.173.09:18:20.56#ibcon#about to read 3, iclass 13, count 0 2006.173.09:18:20.60#ibcon#read 3, iclass 13, count 0 2006.173.09:18:20.60#ibcon#about to read 4, iclass 13, count 0 2006.173.09:18:20.60#ibcon#read 4, iclass 13, count 0 2006.173.09:18:20.60#ibcon#about to read 5, iclass 13, count 0 2006.173.09:18:20.60#ibcon#read 5, iclass 13, count 0 2006.173.09:18:20.60#ibcon#about to read 6, iclass 13, count 0 2006.173.09:18:20.60#ibcon#read 6, iclass 13, count 0 2006.173.09:18:20.60#ibcon#end of sib2, iclass 13, count 0 2006.173.09:18:20.60#ibcon#*after write, iclass 13, count 0 2006.173.09:18:20.60#ibcon#*before return 0, iclass 13, count 0 2006.173.09:18:20.60#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.09:18:20.60#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.09:18:20.60#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.09:18:20.60#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.09:18:20.60$vck44/vb=3,4 2006.173.09:18:20.60#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.09:18:20.60#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.09:18:20.60#ibcon#ireg 11 cls_cnt 2 2006.173.09:18:20.60#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.09:18:20.66#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.09:18:20.66#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.09:18:20.66#ibcon#enter wrdev, iclass 15, count 2 2006.173.09:18:20.66#ibcon#first serial, iclass 15, count 2 2006.173.09:18:20.66#ibcon#enter sib2, iclass 15, count 2 2006.173.09:18:20.66#ibcon#flushed, iclass 15, count 2 2006.173.09:18:20.66#ibcon#about to write, iclass 15, count 2 2006.173.09:18:20.66#ibcon#wrote, iclass 15, count 2 2006.173.09:18:20.66#ibcon#about to read 3, iclass 15, count 2 2006.173.09:18:20.68#ibcon#read 3, iclass 15, count 2 2006.173.09:18:20.68#ibcon#about to read 4, iclass 15, count 2 2006.173.09:18:20.68#ibcon#read 4, iclass 15, count 2 2006.173.09:18:20.68#ibcon#about to read 5, iclass 15, count 2 2006.173.09:18:20.68#ibcon#read 5, iclass 15, count 2 2006.173.09:18:20.68#ibcon#about to read 6, iclass 15, count 2 2006.173.09:18:20.68#ibcon#read 6, iclass 15, count 2 2006.173.09:18:20.68#ibcon#end of sib2, iclass 15, count 2 2006.173.09:18:20.68#ibcon#*mode == 0, iclass 15, count 2 2006.173.09:18:20.68#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.09:18:20.68#ibcon#[27=AT03-04\r\n] 2006.173.09:18:20.68#ibcon#*before write, iclass 15, count 2 2006.173.09:18:20.68#ibcon#enter sib2, iclass 15, count 2 2006.173.09:18:20.68#ibcon#flushed, iclass 15, count 2 2006.173.09:18:20.68#ibcon#about to write, iclass 15, count 2 2006.173.09:18:20.68#ibcon#wrote, iclass 15, count 2 2006.173.09:18:20.68#ibcon#about to read 3, iclass 15, count 2 2006.173.09:18:20.71#ibcon#read 3, iclass 15, count 2 2006.173.09:18:20.71#ibcon#about to read 4, iclass 15, count 2 2006.173.09:18:20.71#ibcon#read 4, iclass 15, count 2 2006.173.09:18:20.71#ibcon#about to read 5, iclass 15, count 2 2006.173.09:18:20.71#ibcon#read 5, iclass 15, count 2 2006.173.09:18:20.71#ibcon#about to read 6, iclass 15, count 2 2006.173.09:18:20.71#ibcon#read 6, iclass 15, count 2 2006.173.09:18:20.71#ibcon#end of sib2, iclass 15, count 2 2006.173.09:18:20.71#ibcon#*after write, iclass 15, count 2 2006.173.09:18:20.71#ibcon#*before return 0, iclass 15, count 2 2006.173.09:18:20.71#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.09:18:20.71#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.09:18:20.71#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.09:18:20.71#ibcon#ireg 7 cls_cnt 0 2006.173.09:18:20.71#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.09:18:20.83#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.09:18:20.83#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.09:18:20.83#ibcon#enter wrdev, iclass 15, count 0 2006.173.09:18:20.83#ibcon#first serial, iclass 15, count 0 2006.173.09:18:20.83#ibcon#enter sib2, iclass 15, count 0 2006.173.09:18:20.83#ibcon#flushed, iclass 15, count 0 2006.173.09:18:20.83#ibcon#about to write, iclass 15, count 0 2006.173.09:18:20.83#ibcon#wrote, iclass 15, count 0 2006.173.09:18:20.83#ibcon#about to read 3, iclass 15, count 0 2006.173.09:18:20.85#ibcon#read 3, iclass 15, count 0 2006.173.09:18:20.85#ibcon#about to read 4, iclass 15, count 0 2006.173.09:18:20.85#ibcon#read 4, iclass 15, count 0 2006.173.09:18:20.85#ibcon#about to read 5, iclass 15, count 0 2006.173.09:18:20.85#ibcon#read 5, iclass 15, count 0 2006.173.09:18:20.85#ibcon#about to read 6, iclass 15, count 0 2006.173.09:18:20.85#ibcon#read 6, iclass 15, count 0 2006.173.09:18:20.85#ibcon#end of sib2, iclass 15, count 0 2006.173.09:18:20.85#ibcon#*mode == 0, iclass 15, count 0 2006.173.09:18:20.85#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.09:18:20.85#ibcon#[27=USB\r\n] 2006.173.09:18:20.85#ibcon#*before write, iclass 15, count 0 2006.173.09:18:20.85#ibcon#enter sib2, iclass 15, count 0 2006.173.09:18:20.85#ibcon#flushed, iclass 15, count 0 2006.173.09:18:20.85#ibcon#about to write, iclass 15, count 0 2006.173.09:18:20.85#ibcon#wrote, iclass 15, count 0 2006.173.09:18:20.85#ibcon#about to read 3, iclass 15, count 0 2006.173.09:18:20.88#ibcon#read 3, iclass 15, count 0 2006.173.09:18:20.88#ibcon#about to read 4, iclass 15, count 0 2006.173.09:18:20.88#ibcon#read 4, iclass 15, count 0 2006.173.09:18:20.88#ibcon#about to read 5, iclass 15, count 0 2006.173.09:18:20.88#ibcon#read 5, iclass 15, count 0 2006.173.09:18:20.88#ibcon#about to read 6, iclass 15, count 0 2006.173.09:18:20.88#ibcon#read 6, iclass 15, count 0 2006.173.09:18:20.88#ibcon#end of sib2, iclass 15, count 0 2006.173.09:18:20.88#ibcon#*after write, iclass 15, count 0 2006.173.09:18:20.88#ibcon#*before return 0, iclass 15, count 0 2006.173.09:18:20.88#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.09:18:20.88#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.09:18:20.88#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.09:18:20.88#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.09:18:20.88$vck44/vblo=4,679.99 2006.173.09:18:20.88#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.09:18:20.88#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.09:18:20.88#ibcon#ireg 17 cls_cnt 0 2006.173.09:18:20.88#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.09:18:20.88#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.09:18:20.88#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.09:18:20.88#ibcon#enter wrdev, iclass 17, count 0 2006.173.09:18:20.88#ibcon#first serial, iclass 17, count 0 2006.173.09:18:20.88#ibcon#enter sib2, iclass 17, count 0 2006.173.09:18:20.88#ibcon#flushed, iclass 17, count 0 2006.173.09:18:20.88#ibcon#about to write, iclass 17, count 0 2006.173.09:18:20.88#ibcon#wrote, iclass 17, count 0 2006.173.09:18:20.88#ibcon#about to read 3, iclass 17, count 0 2006.173.09:18:20.90#ibcon#read 3, iclass 17, count 0 2006.173.09:18:20.90#ibcon#about to read 4, iclass 17, count 0 2006.173.09:18:20.90#ibcon#read 4, iclass 17, count 0 2006.173.09:18:20.90#ibcon#about to read 5, iclass 17, count 0 2006.173.09:18:20.90#ibcon#read 5, iclass 17, count 0 2006.173.09:18:20.90#ibcon#about to read 6, iclass 17, count 0 2006.173.09:18:20.90#ibcon#read 6, iclass 17, count 0 2006.173.09:18:20.90#ibcon#end of sib2, iclass 17, count 0 2006.173.09:18:20.90#ibcon#*mode == 0, iclass 17, count 0 2006.173.09:18:20.90#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.09:18:20.90#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.09:18:20.90#ibcon#*before write, iclass 17, count 0 2006.173.09:18:20.90#ibcon#enter sib2, iclass 17, count 0 2006.173.09:18:20.90#ibcon#flushed, iclass 17, count 0 2006.173.09:18:20.90#ibcon#about to write, iclass 17, count 0 2006.173.09:18:20.90#ibcon#wrote, iclass 17, count 0 2006.173.09:18:20.90#ibcon#about to read 3, iclass 17, count 0 2006.173.09:18:20.94#ibcon#read 3, iclass 17, count 0 2006.173.09:18:20.94#ibcon#about to read 4, iclass 17, count 0 2006.173.09:18:20.94#ibcon#read 4, iclass 17, count 0 2006.173.09:18:20.94#ibcon#about to read 5, iclass 17, count 0 2006.173.09:18:20.94#ibcon#read 5, iclass 17, count 0 2006.173.09:18:20.94#ibcon#about to read 6, iclass 17, count 0 2006.173.09:18:20.94#ibcon#read 6, iclass 17, count 0 2006.173.09:18:20.94#ibcon#end of sib2, iclass 17, count 0 2006.173.09:18:20.94#ibcon#*after write, iclass 17, count 0 2006.173.09:18:20.94#ibcon#*before return 0, iclass 17, count 0 2006.173.09:18:20.94#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.09:18:20.94#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.09:18:20.94#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.09:18:20.94#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.09:18:20.94$vck44/vb=4,4 2006.173.09:18:20.94#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.09:18:20.94#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.09:18:20.94#ibcon#ireg 11 cls_cnt 2 2006.173.09:18:20.94#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.09:18:21.00#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.09:18:21.00#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.09:18:21.00#ibcon#enter wrdev, iclass 19, count 2 2006.173.09:18:21.00#ibcon#first serial, iclass 19, count 2 2006.173.09:18:21.00#ibcon#enter sib2, iclass 19, count 2 2006.173.09:18:21.00#ibcon#flushed, iclass 19, count 2 2006.173.09:18:21.00#ibcon#about to write, iclass 19, count 2 2006.173.09:18:21.00#ibcon#wrote, iclass 19, count 2 2006.173.09:18:21.00#ibcon#about to read 3, iclass 19, count 2 2006.173.09:18:21.02#ibcon#read 3, iclass 19, count 2 2006.173.09:18:21.02#ibcon#about to read 4, iclass 19, count 2 2006.173.09:18:21.02#ibcon#read 4, iclass 19, count 2 2006.173.09:18:21.02#ibcon#about to read 5, iclass 19, count 2 2006.173.09:18:21.02#ibcon#read 5, iclass 19, count 2 2006.173.09:18:21.02#ibcon#about to read 6, iclass 19, count 2 2006.173.09:18:21.02#ibcon#read 6, iclass 19, count 2 2006.173.09:18:21.02#ibcon#end of sib2, iclass 19, count 2 2006.173.09:18:21.02#ibcon#*mode == 0, iclass 19, count 2 2006.173.09:18:21.02#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.09:18:21.02#ibcon#[27=AT04-04\r\n] 2006.173.09:18:21.02#ibcon#*before write, iclass 19, count 2 2006.173.09:18:21.02#ibcon#enter sib2, iclass 19, count 2 2006.173.09:18:21.02#ibcon#flushed, iclass 19, count 2 2006.173.09:18:21.02#ibcon#about to write, iclass 19, count 2 2006.173.09:18:21.02#ibcon#wrote, iclass 19, count 2 2006.173.09:18:21.02#ibcon#about to read 3, iclass 19, count 2 2006.173.09:18:21.05#ibcon#read 3, iclass 19, count 2 2006.173.09:18:21.05#ibcon#about to read 4, iclass 19, count 2 2006.173.09:18:21.05#ibcon#read 4, iclass 19, count 2 2006.173.09:18:21.05#ibcon#about to read 5, iclass 19, count 2 2006.173.09:18:21.05#ibcon#read 5, iclass 19, count 2 2006.173.09:18:21.05#ibcon#about to read 6, iclass 19, count 2 2006.173.09:18:21.05#ibcon#read 6, iclass 19, count 2 2006.173.09:18:21.05#ibcon#end of sib2, iclass 19, count 2 2006.173.09:18:21.05#ibcon#*after write, iclass 19, count 2 2006.173.09:18:21.05#ibcon#*before return 0, iclass 19, count 2 2006.173.09:18:21.05#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.09:18:21.05#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.09:18:21.05#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.09:18:21.05#ibcon#ireg 7 cls_cnt 0 2006.173.09:18:21.05#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.09:18:21.17#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.09:18:21.17#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.09:18:21.17#ibcon#enter wrdev, iclass 19, count 0 2006.173.09:18:21.17#ibcon#first serial, iclass 19, count 0 2006.173.09:18:21.17#ibcon#enter sib2, iclass 19, count 0 2006.173.09:18:21.17#ibcon#flushed, iclass 19, count 0 2006.173.09:18:21.17#ibcon#about to write, iclass 19, count 0 2006.173.09:18:21.17#ibcon#wrote, iclass 19, count 0 2006.173.09:18:21.17#ibcon#about to read 3, iclass 19, count 0 2006.173.09:18:21.19#ibcon#read 3, iclass 19, count 0 2006.173.09:18:21.19#ibcon#about to read 4, iclass 19, count 0 2006.173.09:18:21.19#ibcon#read 4, iclass 19, count 0 2006.173.09:18:21.19#ibcon#about to read 5, iclass 19, count 0 2006.173.09:18:21.19#ibcon#read 5, iclass 19, count 0 2006.173.09:18:21.19#ibcon#about to read 6, iclass 19, count 0 2006.173.09:18:21.19#ibcon#read 6, iclass 19, count 0 2006.173.09:18:21.19#ibcon#end of sib2, iclass 19, count 0 2006.173.09:18:21.19#ibcon#*mode == 0, iclass 19, count 0 2006.173.09:18:21.19#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.09:18:21.19#ibcon#[27=USB\r\n] 2006.173.09:18:21.19#ibcon#*before write, iclass 19, count 0 2006.173.09:18:21.19#ibcon#enter sib2, iclass 19, count 0 2006.173.09:18:21.19#ibcon#flushed, iclass 19, count 0 2006.173.09:18:21.19#ibcon#about to write, iclass 19, count 0 2006.173.09:18:21.19#ibcon#wrote, iclass 19, count 0 2006.173.09:18:21.19#ibcon#about to read 3, iclass 19, count 0 2006.173.09:18:21.22#ibcon#read 3, iclass 19, count 0 2006.173.09:18:21.22#ibcon#about to read 4, iclass 19, count 0 2006.173.09:18:21.22#ibcon#read 4, iclass 19, count 0 2006.173.09:18:21.22#ibcon#about to read 5, iclass 19, count 0 2006.173.09:18:21.22#ibcon#read 5, iclass 19, count 0 2006.173.09:18:21.22#ibcon#about to read 6, iclass 19, count 0 2006.173.09:18:21.22#ibcon#read 6, iclass 19, count 0 2006.173.09:18:21.22#ibcon#end of sib2, iclass 19, count 0 2006.173.09:18:21.22#ibcon#*after write, iclass 19, count 0 2006.173.09:18:21.22#ibcon#*before return 0, iclass 19, count 0 2006.173.09:18:21.22#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.09:18:21.22#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.09:18:21.22#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.09:18:21.22#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.09:18:21.22$vck44/vblo=5,709.99 2006.173.09:18:21.22#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.09:18:21.22#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.09:18:21.22#ibcon#ireg 17 cls_cnt 0 2006.173.09:18:21.22#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.09:18:21.22#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.09:18:21.22#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.09:18:21.22#ibcon#enter wrdev, iclass 21, count 0 2006.173.09:18:21.22#ibcon#first serial, iclass 21, count 0 2006.173.09:18:21.22#ibcon#enter sib2, iclass 21, count 0 2006.173.09:18:21.22#ibcon#flushed, iclass 21, count 0 2006.173.09:18:21.22#ibcon#about to write, iclass 21, count 0 2006.173.09:18:21.22#ibcon#wrote, iclass 21, count 0 2006.173.09:18:21.22#ibcon#about to read 3, iclass 21, count 0 2006.173.09:18:21.24#ibcon#read 3, iclass 21, count 0 2006.173.09:18:21.24#ibcon#about to read 4, iclass 21, count 0 2006.173.09:18:21.24#ibcon#read 4, iclass 21, count 0 2006.173.09:18:21.24#ibcon#about to read 5, iclass 21, count 0 2006.173.09:18:21.24#ibcon#read 5, iclass 21, count 0 2006.173.09:18:21.24#ibcon#about to read 6, iclass 21, count 0 2006.173.09:18:21.24#ibcon#read 6, iclass 21, count 0 2006.173.09:18:21.24#ibcon#end of sib2, iclass 21, count 0 2006.173.09:18:21.24#ibcon#*mode == 0, iclass 21, count 0 2006.173.09:18:21.24#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.09:18:21.24#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.09:18:21.24#ibcon#*before write, iclass 21, count 0 2006.173.09:18:21.24#ibcon#enter sib2, iclass 21, count 0 2006.173.09:18:21.24#ibcon#flushed, iclass 21, count 0 2006.173.09:18:21.24#ibcon#about to write, iclass 21, count 0 2006.173.09:18:21.24#ibcon#wrote, iclass 21, count 0 2006.173.09:18:21.24#ibcon#about to read 3, iclass 21, count 0 2006.173.09:18:21.28#ibcon#read 3, iclass 21, count 0 2006.173.09:18:21.28#ibcon#about to read 4, iclass 21, count 0 2006.173.09:18:21.28#ibcon#read 4, iclass 21, count 0 2006.173.09:18:21.28#ibcon#about to read 5, iclass 21, count 0 2006.173.09:18:21.28#ibcon#read 5, iclass 21, count 0 2006.173.09:18:21.28#ibcon#about to read 6, iclass 21, count 0 2006.173.09:18:21.28#ibcon#read 6, iclass 21, count 0 2006.173.09:18:21.28#ibcon#end of sib2, iclass 21, count 0 2006.173.09:18:21.28#ibcon#*after write, iclass 21, count 0 2006.173.09:18:21.28#ibcon#*before return 0, iclass 21, count 0 2006.173.09:18:21.28#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.09:18:21.28#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.09:18:21.28#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.09:18:21.28#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.09:18:21.28$vck44/vb=5,4 2006.173.09:18:21.28#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.09:18:21.28#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.09:18:21.28#ibcon#ireg 11 cls_cnt 2 2006.173.09:18:21.28#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.09:18:21.34#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.09:18:21.34#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.09:18:21.34#ibcon#enter wrdev, iclass 23, count 2 2006.173.09:18:21.34#ibcon#first serial, iclass 23, count 2 2006.173.09:18:21.34#ibcon#enter sib2, iclass 23, count 2 2006.173.09:18:21.34#ibcon#flushed, iclass 23, count 2 2006.173.09:18:21.34#ibcon#about to write, iclass 23, count 2 2006.173.09:18:21.34#ibcon#wrote, iclass 23, count 2 2006.173.09:18:21.34#ibcon#about to read 3, iclass 23, count 2 2006.173.09:18:21.36#ibcon#read 3, iclass 23, count 2 2006.173.09:18:21.36#ibcon#about to read 4, iclass 23, count 2 2006.173.09:18:21.36#ibcon#read 4, iclass 23, count 2 2006.173.09:18:21.36#ibcon#about to read 5, iclass 23, count 2 2006.173.09:18:21.36#ibcon#read 5, iclass 23, count 2 2006.173.09:18:21.36#ibcon#about to read 6, iclass 23, count 2 2006.173.09:18:21.36#ibcon#read 6, iclass 23, count 2 2006.173.09:18:21.36#ibcon#end of sib2, iclass 23, count 2 2006.173.09:18:21.36#ibcon#*mode == 0, iclass 23, count 2 2006.173.09:18:21.36#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.09:18:21.36#ibcon#[27=AT05-04\r\n] 2006.173.09:18:21.36#ibcon#*before write, iclass 23, count 2 2006.173.09:18:21.36#ibcon#enter sib2, iclass 23, count 2 2006.173.09:18:21.36#ibcon#flushed, iclass 23, count 2 2006.173.09:18:21.36#ibcon#about to write, iclass 23, count 2 2006.173.09:18:21.36#ibcon#wrote, iclass 23, count 2 2006.173.09:18:21.36#ibcon#about to read 3, iclass 23, count 2 2006.173.09:18:21.39#ibcon#read 3, iclass 23, count 2 2006.173.09:18:21.39#ibcon#about to read 4, iclass 23, count 2 2006.173.09:18:21.39#ibcon#read 4, iclass 23, count 2 2006.173.09:18:21.39#ibcon#about to read 5, iclass 23, count 2 2006.173.09:18:21.39#ibcon#read 5, iclass 23, count 2 2006.173.09:18:21.39#ibcon#about to read 6, iclass 23, count 2 2006.173.09:18:21.39#ibcon#read 6, iclass 23, count 2 2006.173.09:18:21.39#ibcon#end of sib2, iclass 23, count 2 2006.173.09:18:21.39#ibcon#*after write, iclass 23, count 2 2006.173.09:18:21.39#ibcon#*before return 0, iclass 23, count 2 2006.173.09:18:21.39#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.09:18:21.39#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.09:18:21.39#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.09:18:21.39#ibcon#ireg 7 cls_cnt 0 2006.173.09:18:21.39#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.09:18:21.51#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.09:18:21.51#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.09:18:21.51#ibcon#enter wrdev, iclass 23, count 0 2006.173.09:18:21.51#ibcon#first serial, iclass 23, count 0 2006.173.09:18:21.51#ibcon#enter sib2, iclass 23, count 0 2006.173.09:18:21.51#ibcon#flushed, iclass 23, count 0 2006.173.09:18:21.51#ibcon#about to write, iclass 23, count 0 2006.173.09:18:21.51#ibcon#wrote, iclass 23, count 0 2006.173.09:18:21.51#ibcon#about to read 3, iclass 23, count 0 2006.173.09:18:21.53#ibcon#read 3, iclass 23, count 0 2006.173.09:18:21.53#ibcon#about to read 4, iclass 23, count 0 2006.173.09:18:21.53#ibcon#read 4, iclass 23, count 0 2006.173.09:18:21.53#ibcon#about to read 5, iclass 23, count 0 2006.173.09:18:21.53#ibcon#read 5, iclass 23, count 0 2006.173.09:18:21.53#ibcon#about to read 6, iclass 23, count 0 2006.173.09:18:21.53#ibcon#read 6, iclass 23, count 0 2006.173.09:18:21.53#ibcon#end of sib2, iclass 23, count 0 2006.173.09:18:21.53#ibcon#*mode == 0, iclass 23, count 0 2006.173.09:18:21.53#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.09:18:21.53#ibcon#[27=USB\r\n] 2006.173.09:18:21.53#ibcon#*before write, iclass 23, count 0 2006.173.09:18:21.53#ibcon#enter sib2, iclass 23, count 0 2006.173.09:18:21.53#ibcon#flushed, iclass 23, count 0 2006.173.09:18:21.53#ibcon#about to write, iclass 23, count 0 2006.173.09:18:21.53#ibcon#wrote, iclass 23, count 0 2006.173.09:18:21.53#ibcon#about to read 3, iclass 23, count 0 2006.173.09:18:21.56#ibcon#read 3, iclass 23, count 0 2006.173.09:18:21.56#ibcon#about to read 4, iclass 23, count 0 2006.173.09:18:21.56#ibcon#read 4, iclass 23, count 0 2006.173.09:18:21.56#ibcon#about to read 5, iclass 23, count 0 2006.173.09:18:21.56#ibcon#read 5, iclass 23, count 0 2006.173.09:18:21.56#ibcon#about to read 6, iclass 23, count 0 2006.173.09:18:21.56#ibcon#read 6, iclass 23, count 0 2006.173.09:18:21.56#ibcon#end of sib2, iclass 23, count 0 2006.173.09:18:21.56#ibcon#*after write, iclass 23, count 0 2006.173.09:18:21.56#ibcon#*before return 0, iclass 23, count 0 2006.173.09:18:21.56#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.09:18:21.56#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.09:18:21.56#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.09:18:21.56#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.09:18:21.56$vck44/vblo=6,719.99 2006.173.09:18:21.56#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.09:18:21.56#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.09:18:21.56#ibcon#ireg 17 cls_cnt 0 2006.173.09:18:21.56#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.09:18:21.56#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.09:18:21.56#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.09:18:21.56#ibcon#enter wrdev, iclass 25, count 0 2006.173.09:18:21.56#ibcon#first serial, iclass 25, count 0 2006.173.09:18:21.56#ibcon#enter sib2, iclass 25, count 0 2006.173.09:18:21.56#ibcon#flushed, iclass 25, count 0 2006.173.09:18:21.56#ibcon#about to write, iclass 25, count 0 2006.173.09:18:21.56#ibcon#wrote, iclass 25, count 0 2006.173.09:18:21.56#ibcon#about to read 3, iclass 25, count 0 2006.173.09:18:21.58#ibcon#read 3, iclass 25, count 0 2006.173.09:18:21.58#ibcon#about to read 4, iclass 25, count 0 2006.173.09:18:21.58#ibcon#read 4, iclass 25, count 0 2006.173.09:18:21.58#ibcon#about to read 5, iclass 25, count 0 2006.173.09:18:21.58#ibcon#read 5, iclass 25, count 0 2006.173.09:18:21.58#ibcon#about to read 6, iclass 25, count 0 2006.173.09:18:21.58#ibcon#read 6, iclass 25, count 0 2006.173.09:18:21.58#ibcon#end of sib2, iclass 25, count 0 2006.173.09:18:21.58#ibcon#*mode == 0, iclass 25, count 0 2006.173.09:18:21.58#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.09:18:21.58#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.09:18:21.58#ibcon#*before write, iclass 25, count 0 2006.173.09:18:21.58#ibcon#enter sib2, iclass 25, count 0 2006.173.09:18:21.58#ibcon#flushed, iclass 25, count 0 2006.173.09:18:21.58#ibcon#about to write, iclass 25, count 0 2006.173.09:18:21.58#ibcon#wrote, iclass 25, count 0 2006.173.09:18:21.58#ibcon#about to read 3, iclass 25, count 0 2006.173.09:18:21.62#ibcon#read 3, iclass 25, count 0 2006.173.09:18:21.62#ibcon#about to read 4, iclass 25, count 0 2006.173.09:18:21.62#ibcon#read 4, iclass 25, count 0 2006.173.09:18:21.62#ibcon#about to read 5, iclass 25, count 0 2006.173.09:18:21.62#ibcon#read 5, iclass 25, count 0 2006.173.09:18:21.62#ibcon#about to read 6, iclass 25, count 0 2006.173.09:18:21.62#ibcon#read 6, iclass 25, count 0 2006.173.09:18:21.62#ibcon#end of sib2, iclass 25, count 0 2006.173.09:18:21.62#ibcon#*after write, iclass 25, count 0 2006.173.09:18:21.62#ibcon#*before return 0, iclass 25, count 0 2006.173.09:18:21.62#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.09:18:21.62#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.09:18:21.62#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.09:18:21.62#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.09:18:21.62$vck44/vb=6,4 2006.173.09:18:21.62#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.09:18:21.62#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.09:18:21.62#ibcon#ireg 11 cls_cnt 2 2006.173.09:18:21.62#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.09:18:21.68#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.09:18:21.68#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.09:18:21.68#ibcon#enter wrdev, iclass 27, count 2 2006.173.09:18:21.68#ibcon#first serial, iclass 27, count 2 2006.173.09:18:21.68#ibcon#enter sib2, iclass 27, count 2 2006.173.09:18:21.68#ibcon#flushed, iclass 27, count 2 2006.173.09:18:21.68#ibcon#about to write, iclass 27, count 2 2006.173.09:18:21.68#ibcon#wrote, iclass 27, count 2 2006.173.09:18:21.68#ibcon#about to read 3, iclass 27, count 2 2006.173.09:18:21.70#ibcon#read 3, iclass 27, count 2 2006.173.09:18:21.70#ibcon#about to read 4, iclass 27, count 2 2006.173.09:18:21.70#ibcon#read 4, iclass 27, count 2 2006.173.09:18:21.70#ibcon#about to read 5, iclass 27, count 2 2006.173.09:18:21.70#ibcon#read 5, iclass 27, count 2 2006.173.09:18:21.70#ibcon#about to read 6, iclass 27, count 2 2006.173.09:18:21.70#ibcon#read 6, iclass 27, count 2 2006.173.09:18:21.70#ibcon#end of sib2, iclass 27, count 2 2006.173.09:18:21.70#ibcon#*mode == 0, iclass 27, count 2 2006.173.09:18:21.70#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.09:18:21.70#ibcon#[27=AT06-04\r\n] 2006.173.09:18:21.70#ibcon#*before write, iclass 27, count 2 2006.173.09:18:21.70#ibcon#enter sib2, iclass 27, count 2 2006.173.09:18:21.70#ibcon#flushed, iclass 27, count 2 2006.173.09:18:21.70#ibcon#about to write, iclass 27, count 2 2006.173.09:18:21.70#ibcon#wrote, iclass 27, count 2 2006.173.09:18:21.70#ibcon#about to read 3, iclass 27, count 2 2006.173.09:18:21.73#ibcon#read 3, iclass 27, count 2 2006.173.09:18:21.73#ibcon#about to read 4, iclass 27, count 2 2006.173.09:18:21.73#ibcon#read 4, iclass 27, count 2 2006.173.09:18:21.73#ibcon#about to read 5, iclass 27, count 2 2006.173.09:18:21.73#ibcon#read 5, iclass 27, count 2 2006.173.09:18:21.73#ibcon#about to read 6, iclass 27, count 2 2006.173.09:18:21.73#ibcon#read 6, iclass 27, count 2 2006.173.09:18:21.73#ibcon#end of sib2, iclass 27, count 2 2006.173.09:18:21.73#ibcon#*after write, iclass 27, count 2 2006.173.09:18:21.73#ibcon#*before return 0, iclass 27, count 2 2006.173.09:18:21.73#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.09:18:21.73#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.09:18:21.73#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.09:18:21.73#ibcon#ireg 7 cls_cnt 0 2006.173.09:18:21.73#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.09:18:21.85#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.09:18:21.85#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.09:18:21.85#ibcon#enter wrdev, iclass 27, count 0 2006.173.09:18:21.85#ibcon#first serial, iclass 27, count 0 2006.173.09:18:21.85#ibcon#enter sib2, iclass 27, count 0 2006.173.09:18:21.85#ibcon#flushed, iclass 27, count 0 2006.173.09:18:21.85#ibcon#about to write, iclass 27, count 0 2006.173.09:18:21.85#ibcon#wrote, iclass 27, count 0 2006.173.09:18:21.85#ibcon#about to read 3, iclass 27, count 0 2006.173.09:18:21.87#ibcon#read 3, iclass 27, count 0 2006.173.09:18:21.87#ibcon#about to read 4, iclass 27, count 0 2006.173.09:18:21.87#ibcon#read 4, iclass 27, count 0 2006.173.09:18:21.87#ibcon#about to read 5, iclass 27, count 0 2006.173.09:18:21.87#ibcon#read 5, iclass 27, count 0 2006.173.09:18:21.87#ibcon#about to read 6, iclass 27, count 0 2006.173.09:18:21.87#ibcon#read 6, iclass 27, count 0 2006.173.09:18:21.87#ibcon#end of sib2, iclass 27, count 0 2006.173.09:18:21.87#ibcon#*mode == 0, iclass 27, count 0 2006.173.09:18:21.87#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.09:18:21.87#ibcon#[27=USB\r\n] 2006.173.09:18:21.87#ibcon#*before write, iclass 27, count 0 2006.173.09:18:21.87#ibcon#enter sib2, iclass 27, count 0 2006.173.09:18:21.87#ibcon#flushed, iclass 27, count 0 2006.173.09:18:21.87#ibcon#about to write, iclass 27, count 0 2006.173.09:18:21.87#ibcon#wrote, iclass 27, count 0 2006.173.09:18:21.87#ibcon#about to read 3, iclass 27, count 0 2006.173.09:18:21.90#ibcon#read 3, iclass 27, count 0 2006.173.09:18:21.90#ibcon#about to read 4, iclass 27, count 0 2006.173.09:18:21.90#ibcon#read 4, iclass 27, count 0 2006.173.09:18:21.90#ibcon#about to read 5, iclass 27, count 0 2006.173.09:18:21.90#ibcon#read 5, iclass 27, count 0 2006.173.09:18:21.90#ibcon#about to read 6, iclass 27, count 0 2006.173.09:18:21.90#ibcon#read 6, iclass 27, count 0 2006.173.09:18:21.90#ibcon#end of sib2, iclass 27, count 0 2006.173.09:18:21.90#ibcon#*after write, iclass 27, count 0 2006.173.09:18:21.90#ibcon#*before return 0, iclass 27, count 0 2006.173.09:18:21.90#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.09:18:21.90#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.09:18:21.90#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.09:18:21.90#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.09:18:21.90$vck44/vblo=7,734.99 2006.173.09:18:21.90#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.09:18:21.90#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.09:18:21.90#ibcon#ireg 17 cls_cnt 0 2006.173.09:18:21.90#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.09:18:21.90#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.09:18:21.90#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.09:18:21.90#ibcon#enter wrdev, iclass 29, count 0 2006.173.09:18:21.90#ibcon#first serial, iclass 29, count 0 2006.173.09:18:21.90#ibcon#enter sib2, iclass 29, count 0 2006.173.09:18:21.90#ibcon#flushed, iclass 29, count 0 2006.173.09:18:21.90#ibcon#about to write, iclass 29, count 0 2006.173.09:18:21.90#ibcon#wrote, iclass 29, count 0 2006.173.09:18:21.90#ibcon#about to read 3, iclass 29, count 0 2006.173.09:18:21.92#ibcon#read 3, iclass 29, count 0 2006.173.09:18:21.92#ibcon#about to read 4, iclass 29, count 0 2006.173.09:18:21.92#ibcon#read 4, iclass 29, count 0 2006.173.09:18:21.92#ibcon#about to read 5, iclass 29, count 0 2006.173.09:18:21.92#ibcon#read 5, iclass 29, count 0 2006.173.09:18:21.92#ibcon#about to read 6, iclass 29, count 0 2006.173.09:18:21.92#ibcon#read 6, iclass 29, count 0 2006.173.09:18:21.92#ibcon#end of sib2, iclass 29, count 0 2006.173.09:18:21.92#ibcon#*mode == 0, iclass 29, count 0 2006.173.09:18:21.92#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.09:18:21.92#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.09:18:21.92#ibcon#*before write, iclass 29, count 0 2006.173.09:18:21.92#ibcon#enter sib2, iclass 29, count 0 2006.173.09:18:21.92#ibcon#flushed, iclass 29, count 0 2006.173.09:18:21.92#ibcon#about to write, iclass 29, count 0 2006.173.09:18:21.92#ibcon#wrote, iclass 29, count 0 2006.173.09:18:21.92#ibcon#about to read 3, iclass 29, count 0 2006.173.09:18:21.96#ibcon#read 3, iclass 29, count 0 2006.173.09:18:21.96#ibcon#about to read 4, iclass 29, count 0 2006.173.09:18:21.96#ibcon#read 4, iclass 29, count 0 2006.173.09:18:21.96#ibcon#about to read 5, iclass 29, count 0 2006.173.09:18:21.96#ibcon#read 5, iclass 29, count 0 2006.173.09:18:21.96#ibcon#about to read 6, iclass 29, count 0 2006.173.09:18:21.96#ibcon#read 6, iclass 29, count 0 2006.173.09:18:21.96#ibcon#end of sib2, iclass 29, count 0 2006.173.09:18:21.96#ibcon#*after write, iclass 29, count 0 2006.173.09:18:21.96#ibcon#*before return 0, iclass 29, count 0 2006.173.09:18:21.96#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.09:18:21.96#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.09:18:21.96#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.09:18:21.96#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.09:18:21.96$vck44/vb=7,4 2006.173.09:18:21.96#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.09:18:21.96#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.09:18:21.96#ibcon#ireg 11 cls_cnt 2 2006.173.09:18:21.96#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.09:18:22.02#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.09:18:22.02#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.09:18:22.02#ibcon#enter wrdev, iclass 31, count 2 2006.173.09:18:22.02#ibcon#first serial, iclass 31, count 2 2006.173.09:18:22.02#ibcon#enter sib2, iclass 31, count 2 2006.173.09:18:22.02#ibcon#flushed, iclass 31, count 2 2006.173.09:18:22.02#ibcon#about to write, iclass 31, count 2 2006.173.09:18:22.02#ibcon#wrote, iclass 31, count 2 2006.173.09:18:22.02#ibcon#about to read 3, iclass 31, count 2 2006.173.09:18:22.04#ibcon#read 3, iclass 31, count 2 2006.173.09:18:22.04#ibcon#about to read 4, iclass 31, count 2 2006.173.09:18:22.04#ibcon#read 4, iclass 31, count 2 2006.173.09:18:22.04#ibcon#about to read 5, iclass 31, count 2 2006.173.09:18:22.04#ibcon#read 5, iclass 31, count 2 2006.173.09:18:22.04#ibcon#about to read 6, iclass 31, count 2 2006.173.09:18:22.04#ibcon#read 6, iclass 31, count 2 2006.173.09:18:22.04#ibcon#end of sib2, iclass 31, count 2 2006.173.09:18:22.04#ibcon#*mode == 0, iclass 31, count 2 2006.173.09:18:22.04#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.09:18:22.04#ibcon#[27=AT07-04\r\n] 2006.173.09:18:22.04#ibcon#*before write, iclass 31, count 2 2006.173.09:18:22.04#ibcon#enter sib2, iclass 31, count 2 2006.173.09:18:22.04#ibcon#flushed, iclass 31, count 2 2006.173.09:18:22.04#ibcon#about to write, iclass 31, count 2 2006.173.09:18:22.04#ibcon#wrote, iclass 31, count 2 2006.173.09:18:22.04#ibcon#about to read 3, iclass 31, count 2 2006.173.09:18:22.07#ibcon#read 3, iclass 31, count 2 2006.173.09:18:22.07#ibcon#about to read 4, iclass 31, count 2 2006.173.09:18:22.07#ibcon#read 4, iclass 31, count 2 2006.173.09:18:22.07#ibcon#about to read 5, iclass 31, count 2 2006.173.09:18:22.07#ibcon#read 5, iclass 31, count 2 2006.173.09:18:22.07#ibcon#about to read 6, iclass 31, count 2 2006.173.09:18:22.07#ibcon#read 6, iclass 31, count 2 2006.173.09:18:22.07#ibcon#end of sib2, iclass 31, count 2 2006.173.09:18:22.07#ibcon#*after write, iclass 31, count 2 2006.173.09:18:22.07#ibcon#*before return 0, iclass 31, count 2 2006.173.09:18:22.07#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.09:18:22.07#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.09:18:22.07#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.09:18:22.07#ibcon#ireg 7 cls_cnt 0 2006.173.09:18:22.07#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.09:18:22.19#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.09:18:22.19#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.09:18:22.19#ibcon#enter wrdev, iclass 31, count 0 2006.173.09:18:22.19#ibcon#first serial, iclass 31, count 0 2006.173.09:18:22.19#ibcon#enter sib2, iclass 31, count 0 2006.173.09:18:22.19#ibcon#flushed, iclass 31, count 0 2006.173.09:18:22.19#ibcon#about to write, iclass 31, count 0 2006.173.09:18:22.19#ibcon#wrote, iclass 31, count 0 2006.173.09:18:22.19#ibcon#about to read 3, iclass 31, count 0 2006.173.09:18:22.21#ibcon#read 3, iclass 31, count 0 2006.173.09:18:22.21#ibcon#about to read 4, iclass 31, count 0 2006.173.09:18:22.21#ibcon#read 4, iclass 31, count 0 2006.173.09:18:22.21#ibcon#about to read 5, iclass 31, count 0 2006.173.09:18:22.21#ibcon#read 5, iclass 31, count 0 2006.173.09:18:22.21#ibcon#about to read 6, iclass 31, count 0 2006.173.09:18:22.21#ibcon#read 6, iclass 31, count 0 2006.173.09:18:22.21#ibcon#end of sib2, iclass 31, count 0 2006.173.09:18:22.21#ibcon#*mode == 0, iclass 31, count 0 2006.173.09:18:22.21#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.09:18:22.21#ibcon#[27=USB\r\n] 2006.173.09:18:22.21#ibcon#*before write, iclass 31, count 0 2006.173.09:18:22.21#ibcon#enter sib2, iclass 31, count 0 2006.173.09:18:22.21#ibcon#flushed, iclass 31, count 0 2006.173.09:18:22.21#ibcon#about to write, iclass 31, count 0 2006.173.09:18:22.21#ibcon#wrote, iclass 31, count 0 2006.173.09:18:22.21#ibcon#about to read 3, iclass 31, count 0 2006.173.09:18:22.24#ibcon#read 3, iclass 31, count 0 2006.173.09:18:22.24#ibcon#about to read 4, iclass 31, count 0 2006.173.09:18:22.24#ibcon#read 4, iclass 31, count 0 2006.173.09:18:22.24#ibcon#about to read 5, iclass 31, count 0 2006.173.09:18:22.24#ibcon#read 5, iclass 31, count 0 2006.173.09:18:22.24#ibcon#about to read 6, iclass 31, count 0 2006.173.09:18:22.24#ibcon#read 6, iclass 31, count 0 2006.173.09:18:22.24#ibcon#end of sib2, iclass 31, count 0 2006.173.09:18:22.24#ibcon#*after write, iclass 31, count 0 2006.173.09:18:22.24#ibcon#*before return 0, iclass 31, count 0 2006.173.09:18:22.24#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.09:18:22.24#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.09:18:22.24#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.09:18:22.24#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.09:18:22.24$vck44/vblo=8,744.99 2006.173.09:18:22.24#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.09:18:22.24#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.09:18:22.24#ibcon#ireg 17 cls_cnt 0 2006.173.09:18:22.24#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.09:18:22.24#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.09:18:22.24#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.09:18:22.24#ibcon#enter wrdev, iclass 33, count 0 2006.173.09:18:22.24#ibcon#first serial, iclass 33, count 0 2006.173.09:18:22.24#ibcon#enter sib2, iclass 33, count 0 2006.173.09:18:22.24#ibcon#flushed, iclass 33, count 0 2006.173.09:18:22.24#ibcon#about to write, iclass 33, count 0 2006.173.09:18:22.24#ibcon#wrote, iclass 33, count 0 2006.173.09:18:22.24#ibcon#about to read 3, iclass 33, count 0 2006.173.09:18:22.26#ibcon#read 3, iclass 33, count 0 2006.173.09:18:22.26#ibcon#about to read 4, iclass 33, count 0 2006.173.09:18:22.26#ibcon#read 4, iclass 33, count 0 2006.173.09:18:22.26#ibcon#about to read 5, iclass 33, count 0 2006.173.09:18:22.26#ibcon#read 5, iclass 33, count 0 2006.173.09:18:22.26#ibcon#about to read 6, iclass 33, count 0 2006.173.09:18:22.26#ibcon#read 6, iclass 33, count 0 2006.173.09:18:22.26#ibcon#end of sib2, iclass 33, count 0 2006.173.09:18:22.26#ibcon#*mode == 0, iclass 33, count 0 2006.173.09:18:22.26#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.09:18:22.26#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.09:18:22.26#ibcon#*before write, iclass 33, count 0 2006.173.09:18:22.26#ibcon#enter sib2, iclass 33, count 0 2006.173.09:18:22.26#ibcon#flushed, iclass 33, count 0 2006.173.09:18:22.26#ibcon#about to write, iclass 33, count 0 2006.173.09:18:22.26#ibcon#wrote, iclass 33, count 0 2006.173.09:18:22.26#ibcon#about to read 3, iclass 33, count 0 2006.173.09:18:22.30#ibcon#read 3, iclass 33, count 0 2006.173.09:18:22.30#ibcon#about to read 4, iclass 33, count 0 2006.173.09:18:22.30#ibcon#read 4, iclass 33, count 0 2006.173.09:18:22.30#ibcon#about to read 5, iclass 33, count 0 2006.173.09:18:22.30#ibcon#read 5, iclass 33, count 0 2006.173.09:18:22.30#ibcon#about to read 6, iclass 33, count 0 2006.173.09:18:22.30#ibcon#read 6, iclass 33, count 0 2006.173.09:18:22.30#ibcon#end of sib2, iclass 33, count 0 2006.173.09:18:22.30#ibcon#*after write, iclass 33, count 0 2006.173.09:18:22.30#ibcon#*before return 0, iclass 33, count 0 2006.173.09:18:22.30#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.09:18:22.30#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.09:18:22.30#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.09:18:22.30#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.09:18:22.30$vck44/vb=8,4 2006.173.09:18:22.30#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.09:18:22.30#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.09:18:22.30#ibcon#ireg 11 cls_cnt 2 2006.173.09:18:22.30#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.09:18:22.36#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.09:18:22.36#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.09:18:22.36#ibcon#enter wrdev, iclass 35, count 2 2006.173.09:18:22.36#ibcon#first serial, iclass 35, count 2 2006.173.09:18:22.36#ibcon#enter sib2, iclass 35, count 2 2006.173.09:18:22.36#ibcon#flushed, iclass 35, count 2 2006.173.09:18:22.36#ibcon#about to write, iclass 35, count 2 2006.173.09:18:22.36#ibcon#wrote, iclass 35, count 2 2006.173.09:18:22.36#ibcon#about to read 3, iclass 35, count 2 2006.173.09:18:22.38#ibcon#read 3, iclass 35, count 2 2006.173.09:18:22.38#ibcon#about to read 4, iclass 35, count 2 2006.173.09:18:22.38#ibcon#read 4, iclass 35, count 2 2006.173.09:18:22.38#ibcon#about to read 5, iclass 35, count 2 2006.173.09:18:22.38#ibcon#read 5, iclass 35, count 2 2006.173.09:18:22.38#ibcon#about to read 6, iclass 35, count 2 2006.173.09:18:22.38#ibcon#read 6, iclass 35, count 2 2006.173.09:18:22.38#ibcon#end of sib2, iclass 35, count 2 2006.173.09:18:22.38#ibcon#*mode == 0, iclass 35, count 2 2006.173.09:18:22.38#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.09:18:22.38#ibcon#[27=AT08-04\r\n] 2006.173.09:18:22.38#ibcon#*before write, iclass 35, count 2 2006.173.09:18:22.38#ibcon#enter sib2, iclass 35, count 2 2006.173.09:18:22.38#ibcon#flushed, iclass 35, count 2 2006.173.09:18:22.38#ibcon#about to write, iclass 35, count 2 2006.173.09:18:22.38#ibcon#wrote, iclass 35, count 2 2006.173.09:18:22.38#ibcon#about to read 3, iclass 35, count 2 2006.173.09:18:22.41#ibcon#read 3, iclass 35, count 2 2006.173.09:18:22.41#ibcon#about to read 4, iclass 35, count 2 2006.173.09:18:22.41#ibcon#read 4, iclass 35, count 2 2006.173.09:18:22.41#ibcon#about to read 5, iclass 35, count 2 2006.173.09:18:22.41#ibcon#read 5, iclass 35, count 2 2006.173.09:18:22.41#ibcon#about to read 6, iclass 35, count 2 2006.173.09:18:22.41#ibcon#read 6, iclass 35, count 2 2006.173.09:18:22.41#ibcon#end of sib2, iclass 35, count 2 2006.173.09:18:22.41#ibcon#*after write, iclass 35, count 2 2006.173.09:18:22.41#ibcon#*before return 0, iclass 35, count 2 2006.173.09:18:22.41#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.09:18:22.41#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.09:18:22.41#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.09:18:22.41#ibcon#ireg 7 cls_cnt 0 2006.173.09:18:22.41#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.09:18:22.53#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.09:18:22.53#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.09:18:22.53#ibcon#enter wrdev, iclass 35, count 0 2006.173.09:18:22.53#ibcon#first serial, iclass 35, count 0 2006.173.09:18:22.53#ibcon#enter sib2, iclass 35, count 0 2006.173.09:18:22.53#ibcon#flushed, iclass 35, count 0 2006.173.09:18:22.53#ibcon#about to write, iclass 35, count 0 2006.173.09:18:22.53#ibcon#wrote, iclass 35, count 0 2006.173.09:18:22.53#ibcon#about to read 3, iclass 35, count 0 2006.173.09:18:22.55#ibcon#read 3, iclass 35, count 0 2006.173.09:18:22.55#ibcon#about to read 4, iclass 35, count 0 2006.173.09:18:22.55#ibcon#read 4, iclass 35, count 0 2006.173.09:18:22.55#ibcon#about to read 5, iclass 35, count 0 2006.173.09:18:22.55#ibcon#read 5, iclass 35, count 0 2006.173.09:18:22.55#ibcon#about to read 6, iclass 35, count 0 2006.173.09:18:22.55#ibcon#read 6, iclass 35, count 0 2006.173.09:18:22.55#ibcon#end of sib2, iclass 35, count 0 2006.173.09:18:22.55#ibcon#*mode == 0, iclass 35, count 0 2006.173.09:18:22.55#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.09:18:22.55#ibcon#[27=USB\r\n] 2006.173.09:18:22.55#ibcon#*before write, iclass 35, count 0 2006.173.09:18:22.55#ibcon#enter sib2, iclass 35, count 0 2006.173.09:18:22.55#ibcon#flushed, iclass 35, count 0 2006.173.09:18:22.55#ibcon#about to write, iclass 35, count 0 2006.173.09:18:22.55#ibcon#wrote, iclass 35, count 0 2006.173.09:18:22.55#ibcon#about to read 3, iclass 35, count 0 2006.173.09:18:22.58#ibcon#read 3, iclass 35, count 0 2006.173.09:18:22.58#ibcon#about to read 4, iclass 35, count 0 2006.173.09:18:22.58#ibcon#read 4, iclass 35, count 0 2006.173.09:18:22.58#ibcon#about to read 5, iclass 35, count 0 2006.173.09:18:22.58#ibcon#read 5, iclass 35, count 0 2006.173.09:18:22.58#ibcon#about to read 6, iclass 35, count 0 2006.173.09:18:22.58#ibcon#read 6, iclass 35, count 0 2006.173.09:18:22.58#ibcon#end of sib2, iclass 35, count 0 2006.173.09:18:22.58#ibcon#*after write, iclass 35, count 0 2006.173.09:18:22.58#ibcon#*before return 0, iclass 35, count 0 2006.173.09:18:22.58#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.09:18:22.58#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.09:18:22.58#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.09:18:22.58#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.09:18:22.58$vck44/vabw=wide 2006.173.09:18:22.58#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.09:18:22.58#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.09:18:22.58#ibcon#ireg 8 cls_cnt 0 2006.173.09:18:22.58#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.09:18:22.58#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.09:18:22.58#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.09:18:22.58#ibcon#enter wrdev, iclass 37, count 0 2006.173.09:18:22.58#ibcon#first serial, iclass 37, count 0 2006.173.09:18:22.58#ibcon#enter sib2, iclass 37, count 0 2006.173.09:18:22.58#ibcon#flushed, iclass 37, count 0 2006.173.09:18:22.58#ibcon#about to write, iclass 37, count 0 2006.173.09:18:22.58#ibcon#wrote, iclass 37, count 0 2006.173.09:18:22.58#ibcon#about to read 3, iclass 37, count 0 2006.173.09:18:22.60#ibcon#read 3, iclass 37, count 0 2006.173.09:18:22.60#ibcon#about to read 4, iclass 37, count 0 2006.173.09:18:22.60#ibcon#read 4, iclass 37, count 0 2006.173.09:18:22.60#ibcon#about to read 5, iclass 37, count 0 2006.173.09:18:22.60#ibcon#read 5, iclass 37, count 0 2006.173.09:18:22.60#ibcon#about to read 6, iclass 37, count 0 2006.173.09:18:22.60#ibcon#read 6, iclass 37, count 0 2006.173.09:18:22.60#ibcon#end of sib2, iclass 37, count 0 2006.173.09:18:22.60#ibcon#*mode == 0, iclass 37, count 0 2006.173.09:18:22.60#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.09:18:22.60#ibcon#[25=BW32\r\n] 2006.173.09:18:22.60#ibcon#*before write, iclass 37, count 0 2006.173.09:18:22.60#ibcon#enter sib2, iclass 37, count 0 2006.173.09:18:22.60#ibcon#flushed, iclass 37, count 0 2006.173.09:18:22.60#ibcon#about to write, iclass 37, count 0 2006.173.09:18:22.60#ibcon#wrote, iclass 37, count 0 2006.173.09:18:22.60#ibcon#about to read 3, iclass 37, count 0 2006.173.09:18:22.63#ibcon#read 3, iclass 37, count 0 2006.173.09:18:22.63#ibcon#about to read 4, iclass 37, count 0 2006.173.09:18:22.63#ibcon#read 4, iclass 37, count 0 2006.173.09:18:22.63#ibcon#about to read 5, iclass 37, count 0 2006.173.09:18:22.63#ibcon#read 5, iclass 37, count 0 2006.173.09:18:22.63#ibcon#about to read 6, iclass 37, count 0 2006.173.09:18:22.63#ibcon#read 6, iclass 37, count 0 2006.173.09:18:22.63#ibcon#end of sib2, iclass 37, count 0 2006.173.09:18:22.63#ibcon#*after write, iclass 37, count 0 2006.173.09:18:22.63#ibcon#*before return 0, iclass 37, count 0 2006.173.09:18:22.63#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.09:18:22.63#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.09:18:22.63#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.09:18:22.63#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.09:18:22.63$vck44/vbbw=wide 2006.173.09:18:22.63#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.09:18:22.63#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.09:18:22.63#ibcon#ireg 8 cls_cnt 0 2006.173.09:18:22.63#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.09:18:22.70#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.09:18:22.70#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.09:18:22.70#ibcon#enter wrdev, iclass 39, count 0 2006.173.09:18:22.70#ibcon#first serial, iclass 39, count 0 2006.173.09:18:22.70#ibcon#enter sib2, iclass 39, count 0 2006.173.09:18:22.70#ibcon#flushed, iclass 39, count 0 2006.173.09:18:22.70#ibcon#about to write, iclass 39, count 0 2006.173.09:18:22.70#ibcon#wrote, iclass 39, count 0 2006.173.09:18:22.70#ibcon#about to read 3, iclass 39, count 0 2006.173.09:18:22.72#ibcon#read 3, iclass 39, count 0 2006.173.09:18:22.72#ibcon#about to read 4, iclass 39, count 0 2006.173.09:18:22.72#ibcon#read 4, iclass 39, count 0 2006.173.09:18:22.72#ibcon#about to read 5, iclass 39, count 0 2006.173.09:18:22.72#ibcon#read 5, iclass 39, count 0 2006.173.09:18:22.72#ibcon#about to read 6, iclass 39, count 0 2006.173.09:18:22.72#ibcon#read 6, iclass 39, count 0 2006.173.09:18:22.72#ibcon#end of sib2, iclass 39, count 0 2006.173.09:18:22.72#ibcon#*mode == 0, iclass 39, count 0 2006.173.09:18:22.72#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.09:18:22.72#ibcon#[27=BW32\r\n] 2006.173.09:18:22.72#ibcon#*before write, iclass 39, count 0 2006.173.09:18:22.72#ibcon#enter sib2, iclass 39, count 0 2006.173.09:18:22.72#ibcon#flushed, iclass 39, count 0 2006.173.09:18:22.72#ibcon#about to write, iclass 39, count 0 2006.173.09:18:22.72#ibcon#wrote, iclass 39, count 0 2006.173.09:18:22.72#ibcon#about to read 3, iclass 39, count 0 2006.173.09:18:22.75#ibcon#read 3, iclass 39, count 0 2006.173.09:18:22.75#ibcon#about to read 4, iclass 39, count 0 2006.173.09:18:22.75#ibcon#read 4, iclass 39, count 0 2006.173.09:18:22.75#ibcon#about to read 5, iclass 39, count 0 2006.173.09:18:22.75#ibcon#read 5, iclass 39, count 0 2006.173.09:18:22.75#ibcon#about to read 6, iclass 39, count 0 2006.173.09:18:22.75#ibcon#read 6, iclass 39, count 0 2006.173.09:18:22.75#ibcon#end of sib2, iclass 39, count 0 2006.173.09:18:22.75#ibcon#*after write, iclass 39, count 0 2006.173.09:18:22.75#ibcon#*before return 0, iclass 39, count 0 2006.173.09:18:22.75#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.09:18:22.75#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.09:18:22.75#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.09:18:22.75#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.09:18:22.75$setupk4/ifdk4 2006.173.09:18:22.75$ifdk4/lo= 2006.173.09:18:22.75$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.09:18:22.75$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.09:18:22.75$ifdk4/patch= 2006.173.09:18:22.75$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.09:18:22.75$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.09:18:22.75$setupk4/!*+20s 2006.173.09:18:28.33#abcon#<5=/02 0.4 0.8 23.00 901004.3\r\n> 2006.173.09:18:28.35#abcon#{5=INTERFACE CLEAR} 2006.173.09:18:28.41#abcon#[5=S1D000X0/0*\r\n] 2006.173.09:18:30.14#trakl#Source acquired 2006.173.09:18:30.14#flagr#flagr/antenna,acquired 2006.173.09:18:37.26$setupk4/"tpicd 2006.173.09:18:37.26$setupk4/echo=off 2006.173.09:18:37.26$setupk4/xlog=off 2006.173.09:18:37.26:!2006.173.09:19:32 2006.173.09:19:32.00:preob 2006.173.09:19:32.14/onsource/TRACKING 2006.173.09:19:32.14:!2006.173.09:19:42 2006.173.09:19:42.00:"tape 2006.173.09:19:42.00:"st=record 2006.173.09:19:42.00:data_valid=on 2006.173.09:19:42.00:midob 2006.173.09:19:42.14/onsource/TRACKING 2006.173.09:19:42.14/wx/23.01,1004.3,89 2006.173.09:19:42.21/cable/+6.5003E-03 2006.173.09:19:43.30/va/01,07,usb,yes,38,41 2006.173.09:19:43.30/va/02,06,usb,yes,37,38 2006.173.09:19:43.30/va/03,05,usb,yes,48,50 2006.173.09:19:43.30/va/04,06,usb,yes,38,40 2006.173.09:19:43.30/va/05,04,usb,yes,30,31 2006.173.09:19:43.30/va/06,03,usb,yes,42,42 2006.173.09:19:43.30/va/07,04,usb,yes,34,35 2006.173.09:19:43.30/va/08,04,usb,yes,29,35 2006.173.09:19:43.53/valo/01,524.99,yes,locked 2006.173.09:19:43.53/valo/02,534.99,yes,locked 2006.173.09:19:43.53/valo/03,564.99,yes,locked 2006.173.09:19:43.53/valo/04,624.99,yes,locked 2006.173.09:19:43.53/valo/05,734.99,yes,locked 2006.173.09:19:43.53/valo/06,814.99,yes,locked 2006.173.09:19:43.53/valo/07,864.99,yes,locked 2006.173.09:19:43.53/valo/08,884.99,yes,locked 2006.173.09:19:44.62/vb/01,04,usb,yes,36,33 2006.173.09:19:44.62/vb/02,04,usb,yes,39,38 2006.173.09:19:44.62/vb/03,04,usb,yes,35,39 2006.173.09:19:44.62/vb/04,04,usb,yes,40,39 2006.173.09:19:44.62/vb/05,04,usb,yes,31,34 2006.173.09:19:44.62/vb/06,04,usb,yes,36,32 2006.173.09:19:44.62/vb/07,04,usb,yes,36,36 2006.173.09:19:44.62/vb/08,04,usb,yes,33,37 2006.173.09:19:44.85/vblo/01,629.99,yes,locked 2006.173.09:19:44.85/vblo/02,634.99,yes,locked 2006.173.09:19:44.85/vblo/03,649.99,yes,locked 2006.173.09:19:44.85/vblo/04,679.99,yes,locked 2006.173.09:19:44.85/vblo/05,709.99,yes,locked 2006.173.09:19:44.85/vblo/06,719.99,yes,locked 2006.173.09:19:44.85/vblo/07,734.99,yes,locked 2006.173.09:19:44.85/vblo/08,744.99,yes,locked 2006.173.09:19:45.00/vabw/8 2006.173.09:19:45.15/vbbw/8 2006.173.09:19:45.24/xfe/off,on,15.2 2006.173.09:19:45.63/ifatt/23,28,28,28 2006.173.09:19:46.07/fmout-gps/S +3.99E-07 2006.173.09:19:46.11:!2006.173.09:21:12 2006.173.09:21:12.01:data_valid=off 2006.173.09:21:12.02:"et 2006.173.09:21:12.02:!+3s 2006.173.09:21:15.03:"tape 2006.173.09:21:15.03:postob 2006.173.09:21:15.17/cable/+6.5028E-03 2006.173.09:21:15.18/wx/23.02,1004.3,89 2006.173.09:21:15.23/fmout-gps/S +3.99E-07 2006.173.09:21:15.24:scan_name=173-0928,jd0606,40 2006.173.09:21:15.24:source=1424-418,142756.30,-420619.4,2000.0,cw 2006.173.09:21:16.14#flagr#flagr/antenna,new-source 2006.173.09:21:16.15:checkk5 2006.173.09:21:16.56/chk_autoobs//k5ts1/ autoobs is running! 2006.173.09:21:16.96/chk_autoobs//k5ts2/ autoobs is running! 2006.173.09:21:17.36/chk_autoobs//k5ts3/ autoobs is running! 2006.173.09:21:17.75/chk_autoobs//k5ts4/ autoobs is running! 2006.173.09:21:18.14/chk_obsdata//k5ts1/T1730919??a.dat file size is correct (nominal:360MB, actual:356MB). 2006.173.09:21:18.54/chk_obsdata//k5ts2/T1730919??b.dat file size is correct (nominal:360MB, actual:356MB). 2006.173.09:21:18.93/chk_obsdata//k5ts3/T1730919??c.dat file size is correct (nominal:360MB, actual:356MB). 2006.173.09:21:19.33/chk_obsdata//k5ts4/T1730919??d.dat file size is correct (nominal:360MB, actual:356MB). 2006.173.09:21:20.06/k5log//k5ts1_log_newline 2006.173.09:21:20.78/k5log//k5ts2_log_newline 2006.173.09:21:21.51/k5log//k5ts3_log_newline 2006.173.09:21:22.21/k5log//k5ts4_log_newline 2006.173.09:21:22.24/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.09:21:22.24:setupk4=1 2006.173.09:21:22.24$setupk4/echo=on 2006.173.09:21:22.24$setupk4/pcalon 2006.173.09:21:22.24$pcalon/"no phase cal control is implemented here 2006.173.09:21:22.24$setupk4/"tpicd=stop 2006.173.09:21:22.24$setupk4/"rec=synch_on 2006.173.09:21:22.24$setupk4/"rec_mode=128 2006.173.09:21:22.24$setupk4/!* 2006.173.09:21:22.24$setupk4/recpk4 2006.173.09:21:22.24$recpk4/recpatch= 2006.173.09:21:22.24$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.09:21:22.24$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.09:21:22.24$setupk4/vck44 2006.173.09:21:22.24$vck44/valo=1,524.99 2006.173.09:21:22.24#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.09:21:22.24#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.09:21:22.24#ibcon#ireg 17 cls_cnt 0 2006.173.09:21:22.24#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.09:21:22.24#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.09:21:22.24#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.09:21:22.24#ibcon#enter wrdev, iclass 6, count 0 2006.173.09:21:22.24#ibcon#first serial, iclass 6, count 0 2006.173.09:21:22.24#ibcon#enter sib2, iclass 6, count 0 2006.173.09:21:22.24#ibcon#flushed, iclass 6, count 0 2006.173.09:21:22.24#ibcon#about to write, iclass 6, count 0 2006.173.09:21:22.24#ibcon#wrote, iclass 6, count 0 2006.173.09:21:22.24#ibcon#about to read 3, iclass 6, count 0 2006.173.09:21:22.26#ibcon#read 3, iclass 6, count 0 2006.173.09:21:22.26#ibcon#about to read 4, iclass 6, count 0 2006.173.09:21:22.26#ibcon#read 4, iclass 6, count 0 2006.173.09:21:22.26#ibcon#about to read 5, iclass 6, count 0 2006.173.09:21:22.26#ibcon#read 5, iclass 6, count 0 2006.173.09:21:22.26#ibcon#about to read 6, iclass 6, count 0 2006.173.09:21:22.26#ibcon#read 6, iclass 6, count 0 2006.173.09:21:22.26#ibcon#end of sib2, iclass 6, count 0 2006.173.09:21:22.26#ibcon#*mode == 0, iclass 6, count 0 2006.173.09:21:22.26#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.09:21:22.26#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.09:21:22.26#ibcon#*before write, iclass 6, count 0 2006.173.09:21:22.26#ibcon#enter sib2, iclass 6, count 0 2006.173.09:21:22.26#ibcon#flushed, iclass 6, count 0 2006.173.09:21:22.26#ibcon#about to write, iclass 6, count 0 2006.173.09:21:22.26#ibcon#wrote, iclass 6, count 0 2006.173.09:21:22.26#ibcon#about to read 3, iclass 6, count 0 2006.173.09:21:22.31#ibcon#read 3, iclass 6, count 0 2006.173.09:21:22.31#ibcon#about to read 4, iclass 6, count 0 2006.173.09:21:22.31#ibcon#read 4, iclass 6, count 0 2006.173.09:21:22.31#ibcon#about to read 5, iclass 6, count 0 2006.173.09:21:22.31#ibcon#read 5, iclass 6, count 0 2006.173.09:21:22.31#ibcon#about to read 6, iclass 6, count 0 2006.173.09:21:22.31#ibcon#read 6, iclass 6, count 0 2006.173.09:21:22.31#ibcon#end of sib2, iclass 6, count 0 2006.173.09:21:22.31#ibcon#*after write, iclass 6, count 0 2006.173.09:21:22.31#ibcon#*before return 0, iclass 6, count 0 2006.173.09:21:22.31#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.09:21:22.31#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.09:21:22.31#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.09:21:22.31#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.09:21:22.31$vck44/va=1,7 2006.173.09:21:22.31#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.09:21:22.31#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.09:21:22.31#ibcon#ireg 11 cls_cnt 2 2006.173.09:21:22.31#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.09:21:22.31#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.09:21:22.31#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.09:21:22.31#ibcon#enter wrdev, iclass 10, count 2 2006.173.09:21:22.31#ibcon#first serial, iclass 10, count 2 2006.173.09:21:22.31#ibcon#enter sib2, iclass 10, count 2 2006.173.09:21:22.31#ibcon#flushed, iclass 10, count 2 2006.173.09:21:22.31#ibcon#about to write, iclass 10, count 2 2006.173.09:21:22.31#ibcon#wrote, iclass 10, count 2 2006.173.09:21:22.31#ibcon#about to read 3, iclass 10, count 2 2006.173.09:21:22.33#ibcon#read 3, iclass 10, count 2 2006.173.09:21:22.33#ibcon#about to read 4, iclass 10, count 2 2006.173.09:21:22.33#ibcon#read 4, iclass 10, count 2 2006.173.09:21:22.33#ibcon#about to read 5, iclass 10, count 2 2006.173.09:21:22.33#ibcon#read 5, iclass 10, count 2 2006.173.09:21:22.33#ibcon#about to read 6, iclass 10, count 2 2006.173.09:21:22.33#ibcon#read 6, iclass 10, count 2 2006.173.09:21:22.33#ibcon#end of sib2, iclass 10, count 2 2006.173.09:21:22.33#ibcon#*mode == 0, iclass 10, count 2 2006.173.09:21:22.33#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.09:21:22.33#ibcon#[25=AT01-07\r\n] 2006.173.09:21:22.33#ibcon#*before write, iclass 10, count 2 2006.173.09:21:22.33#ibcon#enter sib2, iclass 10, count 2 2006.173.09:21:22.33#ibcon#flushed, iclass 10, count 2 2006.173.09:21:22.33#ibcon#about to write, iclass 10, count 2 2006.173.09:21:22.33#ibcon#wrote, iclass 10, count 2 2006.173.09:21:22.33#ibcon#about to read 3, iclass 10, count 2 2006.173.09:21:22.36#ibcon#read 3, iclass 10, count 2 2006.173.09:21:22.36#ibcon#about to read 4, iclass 10, count 2 2006.173.09:21:22.36#ibcon#read 4, iclass 10, count 2 2006.173.09:21:22.36#ibcon#about to read 5, iclass 10, count 2 2006.173.09:21:22.36#ibcon#read 5, iclass 10, count 2 2006.173.09:21:22.36#ibcon#about to read 6, iclass 10, count 2 2006.173.09:21:22.36#ibcon#read 6, iclass 10, count 2 2006.173.09:21:22.36#ibcon#end of sib2, iclass 10, count 2 2006.173.09:21:22.36#ibcon#*after write, iclass 10, count 2 2006.173.09:21:22.36#ibcon#*before return 0, iclass 10, count 2 2006.173.09:21:22.36#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.09:21:22.36#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.09:21:22.36#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.09:21:22.36#ibcon#ireg 7 cls_cnt 0 2006.173.09:21:22.36#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.09:21:22.48#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.09:21:22.48#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.09:21:22.48#ibcon#enter wrdev, iclass 10, count 0 2006.173.09:21:22.48#ibcon#first serial, iclass 10, count 0 2006.173.09:21:22.48#ibcon#enter sib2, iclass 10, count 0 2006.173.09:21:22.48#ibcon#flushed, iclass 10, count 0 2006.173.09:21:22.48#ibcon#about to write, iclass 10, count 0 2006.173.09:21:22.48#ibcon#wrote, iclass 10, count 0 2006.173.09:21:22.48#ibcon#about to read 3, iclass 10, count 0 2006.173.09:21:22.50#ibcon#read 3, iclass 10, count 0 2006.173.09:21:22.50#ibcon#about to read 4, iclass 10, count 0 2006.173.09:21:22.50#ibcon#read 4, iclass 10, count 0 2006.173.09:21:22.50#ibcon#about to read 5, iclass 10, count 0 2006.173.09:21:22.50#ibcon#read 5, iclass 10, count 0 2006.173.09:21:22.50#ibcon#about to read 6, iclass 10, count 0 2006.173.09:21:22.50#ibcon#read 6, iclass 10, count 0 2006.173.09:21:22.50#ibcon#end of sib2, iclass 10, count 0 2006.173.09:21:22.50#ibcon#*mode == 0, iclass 10, count 0 2006.173.09:21:22.50#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.09:21:22.50#ibcon#[25=USB\r\n] 2006.173.09:21:22.50#ibcon#*before write, iclass 10, count 0 2006.173.09:21:22.50#ibcon#enter sib2, iclass 10, count 0 2006.173.09:21:22.50#ibcon#flushed, iclass 10, count 0 2006.173.09:21:22.50#ibcon#about to write, iclass 10, count 0 2006.173.09:21:22.50#ibcon#wrote, iclass 10, count 0 2006.173.09:21:22.50#ibcon#about to read 3, iclass 10, count 0 2006.173.09:21:22.53#ibcon#read 3, iclass 10, count 0 2006.173.09:21:22.53#ibcon#about to read 4, iclass 10, count 0 2006.173.09:21:22.53#ibcon#read 4, iclass 10, count 0 2006.173.09:21:22.53#ibcon#about to read 5, iclass 10, count 0 2006.173.09:21:22.53#ibcon#read 5, iclass 10, count 0 2006.173.09:21:22.53#ibcon#about to read 6, iclass 10, count 0 2006.173.09:21:22.53#ibcon#read 6, iclass 10, count 0 2006.173.09:21:22.53#ibcon#end of sib2, iclass 10, count 0 2006.173.09:21:22.53#ibcon#*after write, iclass 10, count 0 2006.173.09:21:22.53#ibcon#*before return 0, iclass 10, count 0 2006.173.09:21:22.53#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.09:21:22.53#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.09:21:22.53#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.09:21:22.53#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.09:21:22.53$vck44/valo=2,534.99 2006.173.09:21:22.53#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.09:21:22.53#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.09:21:22.53#ibcon#ireg 17 cls_cnt 0 2006.173.09:21:22.53#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.09:21:22.53#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.09:21:22.53#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.09:21:22.53#ibcon#enter wrdev, iclass 12, count 0 2006.173.09:21:22.53#ibcon#first serial, iclass 12, count 0 2006.173.09:21:22.53#ibcon#enter sib2, iclass 12, count 0 2006.173.09:21:22.53#ibcon#flushed, iclass 12, count 0 2006.173.09:21:22.53#ibcon#about to write, iclass 12, count 0 2006.173.09:21:22.53#ibcon#wrote, iclass 12, count 0 2006.173.09:21:22.53#ibcon#about to read 3, iclass 12, count 0 2006.173.09:21:22.55#ibcon#read 3, iclass 12, count 0 2006.173.09:21:22.55#ibcon#about to read 4, iclass 12, count 0 2006.173.09:21:22.55#ibcon#read 4, iclass 12, count 0 2006.173.09:21:22.55#ibcon#about to read 5, iclass 12, count 0 2006.173.09:21:22.55#ibcon#read 5, iclass 12, count 0 2006.173.09:21:22.55#ibcon#about to read 6, iclass 12, count 0 2006.173.09:21:22.55#ibcon#read 6, iclass 12, count 0 2006.173.09:21:22.55#ibcon#end of sib2, iclass 12, count 0 2006.173.09:21:22.55#ibcon#*mode == 0, iclass 12, count 0 2006.173.09:21:22.55#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.09:21:22.55#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.09:21:22.55#ibcon#*before write, iclass 12, count 0 2006.173.09:21:22.55#ibcon#enter sib2, iclass 12, count 0 2006.173.09:21:22.55#ibcon#flushed, iclass 12, count 0 2006.173.09:21:22.55#ibcon#about to write, iclass 12, count 0 2006.173.09:21:22.55#ibcon#wrote, iclass 12, count 0 2006.173.09:21:22.55#ibcon#about to read 3, iclass 12, count 0 2006.173.09:21:22.59#ibcon#read 3, iclass 12, count 0 2006.173.09:21:22.59#ibcon#about to read 4, iclass 12, count 0 2006.173.09:21:22.59#ibcon#read 4, iclass 12, count 0 2006.173.09:21:22.59#ibcon#about to read 5, iclass 12, count 0 2006.173.09:21:22.59#ibcon#read 5, iclass 12, count 0 2006.173.09:21:22.59#ibcon#about to read 6, iclass 12, count 0 2006.173.09:21:22.59#ibcon#read 6, iclass 12, count 0 2006.173.09:21:22.59#ibcon#end of sib2, iclass 12, count 0 2006.173.09:21:22.59#ibcon#*after write, iclass 12, count 0 2006.173.09:21:22.59#ibcon#*before return 0, iclass 12, count 0 2006.173.09:21:22.59#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.09:21:22.59#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.09:21:22.59#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.09:21:22.59#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.09:21:22.59$vck44/va=2,6 2006.173.09:21:22.59#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.09:21:22.59#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.09:21:22.59#ibcon#ireg 11 cls_cnt 2 2006.173.09:21:22.59#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.09:21:22.65#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.09:21:22.65#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.09:21:22.65#ibcon#enter wrdev, iclass 14, count 2 2006.173.09:21:22.65#ibcon#first serial, iclass 14, count 2 2006.173.09:21:22.65#ibcon#enter sib2, iclass 14, count 2 2006.173.09:21:22.65#ibcon#flushed, iclass 14, count 2 2006.173.09:21:22.65#ibcon#about to write, iclass 14, count 2 2006.173.09:21:22.65#ibcon#wrote, iclass 14, count 2 2006.173.09:21:22.65#ibcon#about to read 3, iclass 14, count 2 2006.173.09:21:22.67#ibcon#read 3, iclass 14, count 2 2006.173.09:21:22.67#ibcon#about to read 4, iclass 14, count 2 2006.173.09:21:22.67#ibcon#read 4, iclass 14, count 2 2006.173.09:21:22.67#ibcon#about to read 5, iclass 14, count 2 2006.173.09:21:22.67#ibcon#read 5, iclass 14, count 2 2006.173.09:21:22.67#ibcon#about to read 6, iclass 14, count 2 2006.173.09:21:22.67#ibcon#read 6, iclass 14, count 2 2006.173.09:21:22.67#ibcon#end of sib2, iclass 14, count 2 2006.173.09:21:22.67#ibcon#*mode == 0, iclass 14, count 2 2006.173.09:21:22.67#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.09:21:22.67#ibcon#[25=AT02-06\r\n] 2006.173.09:21:22.67#ibcon#*before write, iclass 14, count 2 2006.173.09:21:22.67#ibcon#enter sib2, iclass 14, count 2 2006.173.09:21:22.67#ibcon#flushed, iclass 14, count 2 2006.173.09:21:22.67#ibcon#about to write, iclass 14, count 2 2006.173.09:21:22.67#ibcon#wrote, iclass 14, count 2 2006.173.09:21:22.67#ibcon#about to read 3, iclass 14, count 2 2006.173.09:21:22.70#ibcon#read 3, iclass 14, count 2 2006.173.09:21:22.70#ibcon#about to read 4, iclass 14, count 2 2006.173.09:21:22.70#ibcon#read 4, iclass 14, count 2 2006.173.09:21:22.70#ibcon#about to read 5, iclass 14, count 2 2006.173.09:21:22.70#ibcon#read 5, iclass 14, count 2 2006.173.09:21:22.70#ibcon#about to read 6, iclass 14, count 2 2006.173.09:21:22.70#ibcon#read 6, iclass 14, count 2 2006.173.09:21:22.70#ibcon#end of sib2, iclass 14, count 2 2006.173.09:21:22.70#ibcon#*after write, iclass 14, count 2 2006.173.09:21:22.70#ibcon#*before return 0, iclass 14, count 2 2006.173.09:21:22.70#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.09:21:22.70#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.09:21:22.70#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.09:21:22.70#ibcon#ireg 7 cls_cnt 0 2006.173.09:21:22.70#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.09:21:22.82#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.09:21:22.82#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.09:21:22.82#ibcon#enter wrdev, iclass 14, count 0 2006.173.09:21:22.82#ibcon#first serial, iclass 14, count 0 2006.173.09:21:22.82#ibcon#enter sib2, iclass 14, count 0 2006.173.09:21:22.82#ibcon#flushed, iclass 14, count 0 2006.173.09:21:22.82#ibcon#about to write, iclass 14, count 0 2006.173.09:21:22.82#ibcon#wrote, iclass 14, count 0 2006.173.09:21:22.82#ibcon#about to read 3, iclass 14, count 0 2006.173.09:21:22.84#ibcon#read 3, iclass 14, count 0 2006.173.09:21:22.84#ibcon#about to read 4, iclass 14, count 0 2006.173.09:21:22.84#ibcon#read 4, iclass 14, count 0 2006.173.09:21:22.84#ibcon#about to read 5, iclass 14, count 0 2006.173.09:21:22.84#ibcon#read 5, iclass 14, count 0 2006.173.09:21:22.84#ibcon#about to read 6, iclass 14, count 0 2006.173.09:21:22.84#ibcon#read 6, iclass 14, count 0 2006.173.09:21:22.84#ibcon#end of sib2, iclass 14, count 0 2006.173.09:21:22.84#ibcon#*mode == 0, iclass 14, count 0 2006.173.09:21:22.84#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.09:21:22.84#ibcon#[25=USB\r\n] 2006.173.09:21:22.84#ibcon#*before write, iclass 14, count 0 2006.173.09:21:22.84#ibcon#enter sib2, iclass 14, count 0 2006.173.09:21:22.84#ibcon#flushed, iclass 14, count 0 2006.173.09:21:22.84#ibcon#about to write, iclass 14, count 0 2006.173.09:21:22.84#ibcon#wrote, iclass 14, count 0 2006.173.09:21:22.84#ibcon#about to read 3, iclass 14, count 0 2006.173.09:21:22.87#ibcon#read 3, iclass 14, count 0 2006.173.09:21:22.87#ibcon#about to read 4, iclass 14, count 0 2006.173.09:21:22.87#ibcon#read 4, iclass 14, count 0 2006.173.09:21:22.87#ibcon#about to read 5, iclass 14, count 0 2006.173.09:21:22.87#ibcon#read 5, iclass 14, count 0 2006.173.09:21:22.87#ibcon#about to read 6, iclass 14, count 0 2006.173.09:21:22.87#ibcon#read 6, iclass 14, count 0 2006.173.09:21:22.87#ibcon#end of sib2, iclass 14, count 0 2006.173.09:21:22.87#ibcon#*after write, iclass 14, count 0 2006.173.09:21:22.87#ibcon#*before return 0, iclass 14, count 0 2006.173.09:21:22.87#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.09:21:22.87#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.09:21:22.87#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.09:21:22.87#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.09:21:22.87$vck44/valo=3,564.99 2006.173.09:21:22.87#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.09:21:22.87#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.09:21:22.87#ibcon#ireg 17 cls_cnt 0 2006.173.09:21:22.87#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.09:21:22.87#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.09:21:22.87#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.09:21:22.87#ibcon#enter wrdev, iclass 16, count 0 2006.173.09:21:22.87#ibcon#first serial, iclass 16, count 0 2006.173.09:21:22.87#ibcon#enter sib2, iclass 16, count 0 2006.173.09:21:22.87#ibcon#flushed, iclass 16, count 0 2006.173.09:21:22.87#ibcon#about to write, iclass 16, count 0 2006.173.09:21:22.87#ibcon#wrote, iclass 16, count 0 2006.173.09:21:22.87#ibcon#about to read 3, iclass 16, count 0 2006.173.09:21:22.89#ibcon#read 3, iclass 16, count 0 2006.173.09:21:22.89#ibcon#about to read 4, iclass 16, count 0 2006.173.09:21:22.89#ibcon#read 4, iclass 16, count 0 2006.173.09:21:22.89#ibcon#about to read 5, iclass 16, count 0 2006.173.09:21:22.89#ibcon#read 5, iclass 16, count 0 2006.173.09:21:22.89#ibcon#about to read 6, iclass 16, count 0 2006.173.09:21:22.89#ibcon#read 6, iclass 16, count 0 2006.173.09:21:22.89#ibcon#end of sib2, iclass 16, count 0 2006.173.09:21:22.89#ibcon#*mode == 0, iclass 16, count 0 2006.173.09:21:22.89#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.09:21:22.89#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.09:21:22.89#ibcon#*before write, iclass 16, count 0 2006.173.09:21:22.89#ibcon#enter sib2, iclass 16, count 0 2006.173.09:21:22.89#ibcon#flushed, iclass 16, count 0 2006.173.09:21:22.89#ibcon#about to write, iclass 16, count 0 2006.173.09:21:22.89#ibcon#wrote, iclass 16, count 0 2006.173.09:21:22.89#ibcon#about to read 3, iclass 16, count 0 2006.173.09:21:22.93#ibcon#read 3, iclass 16, count 0 2006.173.09:21:22.93#ibcon#about to read 4, iclass 16, count 0 2006.173.09:21:22.93#ibcon#read 4, iclass 16, count 0 2006.173.09:21:22.93#ibcon#about to read 5, iclass 16, count 0 2006.173.09:21:22.93#ibcon#read 5, iclass 16, count 0 2006.173.09:21:22.93#ibcon#about to read 6, iclass 16, count 0 2006.173.09:21:22.93#ibcon#read 6, iclass 16, count 0 2006.173.09:21:22.93#ibcon#end of sib2, iclass 16, count 0 2006.173.09:21:22.93#ibcon#*after write, iclass 16, count 0 2006.173.09:21:22.93#ibcon#*before return 0, iclass 16, count 0 2006.173.09:21:22.93#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.09:21:22.93#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.09:21:22.93#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.09:21:22.93#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.09:21:22.93$vck44/va=3,5 2006.173.09:21:22.93#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.09:21:22.93#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.09:21:22.93#ibcon#ireg 11 cls_cnt 2 2006.173.09:21:22.93#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.09:21:22.99#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.09:21:22.99#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.09:21:22.99#ibcon#enter wrdev, iclass 18, count 2 2006.173.09:21:22.99#ibcon#first serial, iclass 18, count 2 2006.173.09:21:22.99#ibcon#enter sib2, iclass 18, count 2 2006.173.09:21:22.99#ibcon#flushed, iclass 18, count 2 2006.173.09:21:22.99#ibcon#about to write, iclass 18, count 2 2006.173.09:21:22.99#ibcon#wrote, iclass 18, count 2 2006.173.09:21:22.99#ibcon#about to read 3, iclass 18, count 2 2006.173.09:21:23.01#ibcon#read 3, iclass 18, count 2 2006.173.09:21:23.01#ibcon#about to read 4, iclass 18, count 2 2006.173.09:21:23.01#ibcon#read 4, iclass 18, count 2 2006.173.09:21:23.01#ibcon#about to read 5, iclass 18, count 2 2006.173.09:21:23.01#ibcon#read 5, iclass 18, count 2 2006.173.09:21:23.01#ibcon#about to read 6, iclass 18, count 2 2006.173.09:21:23.01#ibcon#read 6, iclass 18, count 2 2006.173.09:21:23.01#ibcon#end of sib2, iclass 18, count 2 2006.173.09:21:23.01#ibcon#*mode == 0, iclass 18, count 2 2006.173.09:21:23.01#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.09:21:23.01#ibcon#[25=AT03-05\r\n] 2006.173.09:21:23.01#ibcon#*before write, iclass 18, count 2 2006.173.09:21:23.01#ibcon#enter sib2, iclass 18, count 2 2006.173.09:21:23.01#ibcon#flushed, iclass 18, count 2 2006.173.09:21:23.01#ibcon#about to write, iclass 18, count 2 2006.173.09:21:23.01#ibcon#wrote, iclass 18, count 2 2006.173.09:21:23.01#ibcon#about to read 3, iclass 18, count 2 2006.173.09:21:23.04#ibcon#read 3, iclass 18, count 2 2006.173.09:21:23.04#ibcon#about to read 4, iclass 18, count 2 2006.173.09:21:23.04#ibcon#read 4, iclass 18, count 2 2006.173.09:21:23.04#ibcon#about to read 5, iclass 18, count 2 2006.173.09:21:23.04#ibcon#read 5, iclass 18, count 2 2006.173.09:21:23.04#ibcon#about to read 6, iclass 18, count 2 2006.173.09:21:23.04#ibcon#read 6, iclass 18, count 2 2006.173.09:21:23.04#ibcon#end of sib2, iclass 18, count 2 2006.173.09:21:23.04#ibcon#*after write, iclass 18, count 2 2006.173.09:21:23.04#ibcon#*before return 0, iclass 18, count 2 2006.173.09:21:23.04#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.09:21:23.04#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.09:21:23.04#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.09:21:23.04#ibcon#ireg 7 cls_cnt 0 2006.173.09:21:23.04#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.09:21:23.16#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.09:21:23.16#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.09:21:23.16#ibcon#enter wrdev, iclass 18, count 0 2006.173.09:21:23.16#ibcon#first serial, iclass 18, count 0 2006.173.09:21:23.16#ibcon#enter sib2, iclass 18, count 0 2006.173.09:21:23.16#ibcon#flushed, iclass 18, count 0 2006.173.09:21:23.16#ibcon#about to write, iclass 18, count 0 2006.173.09:21:23.16#ibcon#wrote, iclass 18, count 0 2006.173.09:21:23.16#ibcon#about to read 3, iclass 18, count 0 2006.173.09:21:23.18#ibcon#read 3, iclass 18, count 0 2006.173.09:21:23.18#ibcon#about to read 4, iclass 18, count 0 2006.173.09:21:23.18#ibcon#read 4, iclass 18, count 0 2006.173.09:21:23.18#ibcon#about to read 5, iclass 18, count 0 2006.173.09:21:23.18#ibcon#read 5, iclass 18, count 0 2006.173.09:21:23.18#ibcon#about to read 6, iclass 18, count 0 2006.173.09:21:23.18#ibcon#read 6, iclass 18, count 0 2006.173.09:21:23.18#ibcon#end of sib2, iclass 18, count 0 2006.173.09:21:23.18#ibcon#*mode == 0, iclass 18, count 0 2006.173.09:21:23.18#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.09:21:23.18#ibcon#[25=USB\r\n] 2006.173.09:21:23.18#ibcon#*before write, iclass 18, count 0 2006.173.09:21:23.18#ibcon#enter sib2, iclass 18, count 0 2006.173.09:21:23.18#ibcon#flushed, iclass 18, count 0 2006.173.09:21:23.18#ibcon#about to write, iclass 18, count 0 2006.173.09:21:23.18#ibcon#wrote, iclass 18, count 0 2006.173.09:21:23.18#ibcon#about to read 3, iclass 18, count 0 2006.173.09:21:23.21#ibcon#read 3, iclass 18, count 0 2006.173.09:21:23.21#ibcon#about to read 4, iclass 18, count 0 2006.173.09:21:23.21#ibcon#read 4, iclass 18, count 0 2006.173.09:21:23.21#ibcon#about to read 5, iclass 18, count 0 2006.173.09:21:23.21#ibcon#read 5, iclass 18, count 0 2006.173.09:21:23.21#ibcon#about to read 6, iclass 18, count 0 2006.173.09:21:23.21#ibcon#read 6, iclass 18, count 0 2006.173.09:21:23.21#ibcon#end of sib2, iclass 18, count 0 2006.173.09:21:23.21#ibcon#*after write, iclass 18, count 0 2006.173.09:21:23.21#ibcon#*before return 0, iclass 18, count 0 2006.173.09:21:23.21#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.09:21:23.21#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.09:21:23.21#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.09:21:23.21#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.09:21:23.21$vck44/valo=4,624.99 2006.173.09:21:23.21#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.09:21:23.21#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.09:21:23.21#ibcon#ireg 17 cls_cnt 0 2006.173.09:21:23.21#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.09:21:23.21#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.09:21:23.21#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.09:21:23.21#ibcon#enter wrdev, iclass 20, count 0 2006.173.09:21:23.21#ibcon#first serial, iclass 20, count 0 2006.173.09:21:23.21#ibcon#enter sib2, iclass 20, count 0 2006.173.09:21:23.21#ibcon#flushed, iclass 20, count 0 2006.173.09:21:23.21#ibcon#about to write, iclass 20, count 0 2006.173.09:21:23.21#ibcon#wrote, iclass 20, count 0 2006.173.09:21:23.21#ibcon#about to read 3, iclass 20, count 0 2006.173.09:21:23.23#ibcon#read 3, iclass 20, count 0 2006.173.09:21:23.23#ibcon#about to read 4, iclass 20, count 0 2006.173.09:21:23.23#ibcon#read 4, iclass 20, count 0 2006.173.09:21:23.23#ibcon#about to read 5, iclass 20, count 0 2006.173.09:21:23.23#ibcon#read 5, iclass 20, count 0 2006.173.09:21:23.23#ibcon#about to read 6, iclass 20, count 0 2006.173.09:21:23.23#ibcon#read 6, iclass 20, count 0 2006.173.09:21:23.23#ibcon#end of sib2, iclass 20, count 0 2006.173.09:21:23.23#ibcon#*mode == 0, iclass 20, count 0 2006.173.09:21:23.23#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.09:21:23.23#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.09:21:23.23#ibcon#*before write, iclass 20, count 0 2006.173.09:21:23.23#ibcon#enter sib2, iclass 20, count 0 2006.173.09:21:23.23#ibcon#flushed, iclass 20, count 0 2006.173.09:21:23.23#ibcon#about to write, iclass 20, count 0 2006.173.09:21:23.23#ibcon#wrote, iclass 20, count 0 2006.173.09:21:23.23#ibcon#about to read 3, iclass 20, count 0 2006.173.09:21:23.27#ibcon#read 3, iclass 20, count 0 2006.173.09:21:23.27#ibcon#about to read 4, iclass 20, count 0 2006.173.09:21:23.27#ibcon#read 4, iclass 20, count 0 2006.173.09:21:23.27#ibcon#about to read 5, iclass 20, count 0 2006.173.09:21:23.27#ibcon#read 5, iclass 20, count 0 2006.173.09:21:23.27#ibcon#about to read 6, iclass 20, count 0 2006.173.09:21:23.27#ibcon#read 6, iclass 20, count 0 2006.173.09:21:23.27#ibcon#end of sib2, iclass 20, count 0 2006.173.09:21:23.27#ibcon#*after write, iclass 20, count 0 2006.173.09:21:23.27#ibcon#*before return 0, iclass 20, count 0 2006.173.09:21:23.27#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.09:21:23.27#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.09:21:23.27#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.09:21:23.27#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.09:21:23.27$vck44/va=4,6 2006.173.09:21:23.27#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.09:21:23.27#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.09:21:23.27#ibcon#ireg 11 cls_cnt 2 2006.173.09:21:23.27#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.09:21:23.33#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.09:21:23.33#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.09:21:23.33#ibcon#enter wrdev, iclass 22, count 2 2006.173.09:21:23.33#ibcon#first serial, iclass 22, count 2 2006.173.09:21:23.33#ibcon#enter sib2, iclass 22, count 2 2006.173.09:21:23.33#ibcon#flushed, iclass 22, count 2 2006.173.09:21:23.33#ibcon#about to write, iclass 22, count 2 2006.173.09:21:23.33#ibcon#wrote, iclass 22, count 2 2006.173.09:21:23.33#ibcon#about to read 3, iclass 22, count 2 2006.173.09:21:23.35#ibcon#read 3, iclass 22, count 2 2006.173.09:21:23.35#ibcon#about to read 4, iclass 22, count 2 2006.173.09:21:23.35#ibcon#read 4, iclass 22, count 2 2006.173.09:21:23.35#ibcon#about to read 5, iclass 22, count 2 2006.173.09:21:23.35#ibcon#read 5, iclass 22, count 2 2006.173.09:21:23.35#ibcon#about to read 6, iclass 22, count 2 2006.173.09:21:23.35#ibcon#read 6, iclass 22, count 2 2006.173.09:21:23.35#ibcon#end of sib2, iclass 22, count 2 2006.173.09:21:23.35#ibcon#*mode == 0, iclass 22, count 2 2006.173.09:21:23.35#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.09:21:23.35#ibcon#[25=AT04-06\r\n] 2006.173.09:21:23.35#ibcon#*before write, iclass 22, count 2 2006.173.09:21:23.35#ibcon#enter sib2, iclass 22, count 2 2006.173.09:21:23.35#ibcon#flushed, iclass 22, count 2 2006.173.09:21:23.35#ibcon#about to write, iclass 22, count 2 2006.173.09:21:23.35#ibcon#wrote, iclass 22, count 2 2006.173.09:21:23.35#ibcon#about to read 3, iclass 22, count 2 2006.173.09:21:23.38#ibcon#read 3, iclass 22, count 2 2006.173.09:21:23.38#ibcon#about to read 4, iclass 22, count 2 2006.173.09:21:23.38#ibcon#read 4, iclass 22, count 2 2006.173.09:21:23.38#ibcon#about to read 5, iclass 22, count 2 2006.173.09:21:23.38#ibcon#read 5, iclass 22, count 2 2006.173.09:21:23.38#ibcon#about to read 6, iclass 22, count 2 2006.173.09:21:23.38#ibcon#read 6, iclass 22, count 2 2006.173.09:21:23.38#ibcon#end of sib2, iclass 22, count 2 2006.173.09:21:23.38#ibcon#*after write, iclass 22, count 2 2006.173.09:21:23.38#ibcon#*before return 0, iclass 22, count 2 2006.173.09:21:23.38#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.09:21:23.38#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.09:21:23.38#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.09:21:23.38#ibcon#ireg 7 cls_cnt 0 2006.173.09:21:23.38#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.09:21:23.50#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.09:21:23.50#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.09:21:23.50#ibcon#enter wrdev, iclass 22, count 0 2006.173.09:21:23.50#ibcon#first serial, iclass 22, count 0 2006.173.09:21:23.50#ibcon#enter sib2, iclass 22, count 0 2006.173.09:21:23.50#ibcon#flushed, iclass 22, count 0 2006.173.09:21:23.50#ibcon#about to write, iclass 22, count 0 2006.173.09:21:23.50#ibcon#wrote, iclass 22, count 0 2006.173.09:21:23.50#ibcon#about to read 3, iclass 22, count 0 2006.173.09:21:23.52#ibcon#read 3, iclass 22, count 0 2006.173.09:21:23.52#ibcon#about to read 4, iclass 22, count 0 2006.173.09:21:23.52#ibcon#read 4, iclass 22, count 0 2006.173.09:21:23.52#ibcon#about to read 5, iclass 22, count 0 2006.173.09:21:23.52#ibcon#read 5, iclass 22, count 0 2006.173.09:21:23.52#ibcon#about to read 6, iclass 22, count 0 2006.173.09:21:23.52#ibcon#read 6, iclass 22, count 0 2006.173.09:21:23.52#ibcon#end of sib2, iclass 22, count 0 2006.173.09:21:23.52#ibcon#*mode == 0, iclass 22, count 0 2006.173.09:21:23.52#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.09:21:23.52#ibcon#[25=USB\r\n] 2006.173.09:21:23.52#ibcon#*before write, iclass 22, count 0 2006.173.09:21:23.52#ibcon#enter sib2, iclass 22, count 0 2006.173.09:21:23.52#ibcon#flushed, iclass 22, count 0 2006.173.09:21:23.52#ibcon#about to write, iclass 22, count 0 2006.173.09:21:23.52#ibcon#wrote, iclass 22, count 0 2006.173.09:21:23.52#ibcon#about to read 3, iclass 22, count 0 2006.173.09:21:23.55#ibcon#read 3, iclass 22, count 0 2006.173.09:21:23.55#ibcon#about to read 4, iclass 22, count 0 2006.173.09:21:23.55#ibcon#read 4, iclass 22, count 0 2006.173.09:21:23.55#ibcon#about to read 5, iclass 22, count 0 2006.173.09:21:23.55#ibcon#read 5, iclass 22, count 0 2006.173.09:21:23.55#ibcon#about to read 6, iclass 22, count 0 2006.173.09:21:23.55#ibcon#read 6, iclass 22, count 0 2006.173.09:21:23.55#ibcon#end of sib2, iclass 22, count 0 2006.173.09:21:23.55#ibcon#*after write, iclass 22, count 0 2006.173.09:21:23.55#ibcon#*before return 0, iclass 22, count 0 2006.173.09:21:23.55#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.09:21:23.55#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.09:21:23.55#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.09:21:23.55#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.09:21:23.55$vck44/valo=5,734.99 2006.173.09:21:23.55#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.09:21:23.55#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.09:21:23.55#ibcon#ireg 17 cls_cnt 0 2006.173.09:21:23.55#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.09:21:23.55#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.09:21:23.55#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.09:21:23.55#ibcon#enter wrdev, iclass 24, count 0 2006.173.09:21:23.55#ibcon#first serial, iclass 24, count 0 2006.173.09:21:23.55#ibcon#enter sib2, iclass 24, count 0 2006.173.09:21:23.55#ibcon#flushed, iclass 24, count 0 2006.173.09:21:23.55#ibcon#about to write, iclass 24, count 0 2006.173.09:21:23.55#ibcon#wrote, iclass 24, count 0 2006.173.09:21:23.55#ibcon#about to read 3, iclass 24, count 0 2006.173.09:21:23.57#ibcon#read 3, iclass 24, count 0 2006.173.09:21:23.57#ibcon#about to read 4, iclass 24, count 0 2006.173.09:21:23.57#ibcon#read 4, iclass 24, count 0 2006.173.09:21:23.57#ibcon#about to read 5, iclass 24, count 0 2006.173.09:21:23.57#ibcon#read 5, iclass 24, count 0 2006.173.09:21:23.57#ibcon#about to read 6, iclass 24, count 0 2006.173.09:21:23.57#ibcon#read 6, iclass 24, count 0 2006.173.09:21:23.57#ibcon#end of sib2, iclass 24, count 0 2006.173.09:21:23.57#ibcon#*mode == 0, iclass 24, count 0 2006.173.09:21:23.57#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.09:21:23.57#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.09:21:23.57#ibcon#*before write, iclass 24, count 0 2006.173.09:21:23.57#ibcon#enter sib2, iclass 24, count 0 2006.173.09:21:23.57#ibcon#flushed, iclass 24, count 0 2006.173.09:21:23.57#ibcon#about to write, iclass 24, count 0 2006.173.09:21:23.57#ibcon#wrote, iclass 24, count 0 2006.173.09:21:23.57#ibcon#about to read 3, iclass 24, count 0 2006.173.09:21:23.61#ibcon#read 3, iclass 24, count 0 2006.173.09:21:23.61#ibcon#about to read 4, iclass 24, count 0 2006.173.09:21:23.61#ibcon#read 4, iclass 24, count 0 2006.173.09:21:23.61#ibcon#about to read 5, iclass 24, count 0 2006.173.09:21:23.61#ibcon#read 5, iclass 24, count 0 2006.173.09:21:23.61#ibcon#about to read 6, iclass 24, count 0 2006.173.09:21:23.61#ibcon#read 6, iclass 24, count 0 2006.173.09:21:23.61#ibcon#end of sib2, iclass 24, count 0 2006.173.09:21:23.61#ibcon#*after write, iclass 24, count 0 2006.173.09:21:23.61#ibcon#*before return 0, iclass 24, count 0 2006.173.09:21:23.61#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.09:21:23.61#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.09:21:23.61#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.09:21:23.61#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.09:21:23.61$vck44/va=5,4 2006.173.09:21:23.61#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.09:21:23.61#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.09:21:23.61#ibcon#ireg 11 cls_cnt 2 2006.173.09:21:23.61#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.09:21:23.67#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.09:21:23.67#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.09:21:23.67#ibcon#enter wrdev, iclass 26, count 2 2006.173.09:21:23.67#ibcon#first serial, iclass 26, count 2 2006.173.09:21:23.67#ibcon#enter sib2, iclass 26, count 2 2006.173.09:21:23.67#ibcon#flushed, iclass 26, count 2 2006.173.09:21:23.67#ibcon#about to write, iclass 26, count 2 2006.173.09:21:23.67#ibcon#wrote, iclass 26, count 2 2006.173.09:21:23.67#ibcon#about to read 3, iclass 26, count 2 2006.173.09:21:23.69#ibcon#read 3, iclass 26, count 2 2006.173.09:21:23.69#ibcon#about to read 4, iclass 26, count 2 2006.173.09:21:23.69#ibcon#read 4, iclass 26, count 2 2006.173.09:21:23.69#ibcon#about to read 5, iclass 26, count 2 2006.173.09:21:23.69#ibcon#read 5, iclass 26, count 2 2006.173.09:21:23.69#ibcon#about to read 6, iclass 26, count 2 2006.173.09:21:23.69#ibcon#read 6, iclass 26, count 2 2006.173.09:21:23.69#ibcon#end of sib2, iclass 26, count 2 2006.173.09:21:23.69#ibcon#*mode == 0, iclass 26, count 2 2006.173.09:21:23.69#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.09:21:23.69#ibcon#[25=AT05-04\r\n] 2006.173.09:21:23.69#ibcon#*before write, iclass 26, count 2 2006.173.09:21:23.69#ibcon#enter sib2, iclass 26, count 2 2006.173.09:21:23.69#ibcon#flushed, iclass 26, count 2 2006.173.09:21:23.69#ibcon#about to write, iclass 26, count 2 2006.173.09:21:23.69#ibcon#wrote, iclass 26, count 2 2006.173.09:21:23.69#ibcon#about to read 3, iclass 26, count 2 2006.173.09:21:23.72#ibcon#read 3, iclass 26, count 2 2006.173.09:21:23.72#ibcon#about to read 4, iclass 26, count 2 2006.173.09:21:23.72#ibcon#read 4, iclass 26, count 2 2006.173.09:21:23.72#ibcon#about to read 5, iclass 26, count 2 2006.173.09:21:23.72#ibcon#read 5, iclass 26, count 2 2006.173.09:21:23.72#ibcon#about to read 6, iclass 26, count 2 2006.173.09:21:23.72#ibcon#read 6, iclass 26, count 2 2006.173.09:21:23.72#ibcon#end of sib2, iclass 26, count 2 2006.173.09:21:23.72#ibcon#*after write, iclass 26, count 2 2006.173.09:21:23.72#ibcon#*before return 0, iclass 26, count 2 2006.173.09:21:23.72#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.09:21:23.72#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.09:21:23.72#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.09:21:23.72#ibcon#ireg 7 cls_cnt 0 2006.173.09:21:23.72#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.09:21:23.84#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.09:21:23.84#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.09:21:23.84#ibcon#enter wrdev, iclass 26, count 0 2006.173.09:21:23.84#ibcon#first serial, iclass 26, count 0 2006.173.09:21:23.84#ibcon#enter sib2, iclass 26, count 0 2006.173.09:21:23.84#ibcon#flushed, iclass 26, count 0 2006.173.09:21:23.84#ibcon#about to write, iclass 26, count 0 2006.173.09:21:23.84#ibcon#wrote, iclass 26, count 0 2006.173.09:21:23.84#ibcon#about to read 3, iclass 26, count 0 2006.173.09:21:23.86#ibcon#read 3, iclass 26, count 0 2006.173.09:21:23.86#ibcon#about to read 4, iclass 26, count 0 2006.173.09:21:23.86#ibcon#read 4, iclass 26, count 0 2006.173.09:21:23.86#ibcon#about to read 5, iclass 26, count 0 2006.173.09:21:23.86#ibcon#read 5, iclass 26, count 0 2006.173.09:21:23.86#ibcon#about to read 6, iclass 26, count 0 2006.173.09:21:23.86#ibcon#read 6, iclass 26, count 0 2006.173.09:21:23.86#ibcon#end of sib2, iclass 26, count 0 2006.173.09:21:23.86#ibcon#*mode == 0, iclass 26, count 0 2006.173.09:21:23.86#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.09:21:23.86#ibcon#[25=USB\r\n] 2006.173.09:21:23.86#ibcon#*before write, iclass 26, count 0 2006.173.09:21:23.86#ibcon#enter sib2, iclass 26, count 0 2006.173.09:21:23.86#ibcon#flushed, iclass 26, count 0 2006.173.09:21:23.86#ibcon#about to write, iclass 26, count 0 2006.173.09:21:23.86#ibcon#wrote, iclass 26, count 0 2006.173.09:21:23.86#ibcon#about to read 3, iclass 26, count 0 2006.173.09:21:23.89#ibcon#read 3, iclass 26, count 0 2006.173.09:21:23.89#ibcon#about to read 4, iclass 26, count 0 2006.173.09:21:23.89#ibcon#read 4, iclass 26, count 0 2006.173.09:21:23.89#ibcon#about to read 5, iclass 26, count 0 2006.173.09:21:23.89#ibcon#read 5, iclass 26, count 0 2006.173.09:21:23.89#ibcon#about to read 6, iclass 26, count 0 2006.173.09:21:23.89#ibcon#read 6, iclass 26, count 0 2006.173.09:21:23.89#ibcon#end of sib2, iclass 26, count 0 2006.173.09:21:23.89#ibcon#*after write, iclass 26, count 0 2006.173.09:21:23.89#ibcon#*before return 0, iclass 26, count 0 2006.173.09:21:23.89#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.09:21:23.89#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.09:21:23.89#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.09:21:23.89#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.09:21:23.89$vck44/valo=6,814.99 2006.173.09:21:23.89#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.09:21:23.89#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.09:21:23.89#ibcon#ireg 17 cls_cnt 0 2006.173.09:21:23.89#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.09:21:23.89#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.09:21:23.89#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.09:21:23.89#ibcon#enter wrdev, iclass 28, count 0 2006.173.09:21:23.89#ibcon#first serial, iclass 28, count 0 2006.173.09:21:23.89#ibcon#enter sib2, iclass 28, count 0 2006.173.09:21:23.89#ibcon#flushed, iclass 28, count 0 2006.173.09:21:23.89#ibcon#about to write, iclass 28, count 0 2006.173.09:21:23.89#ibcon#wrote, iclass 28, count 0 2006.173.09:21:23.89#ibcon#about to read 3, iclass 28, count 0 2006.173.09:21:23.91#ibcon#read 3, iclass 28, count 0 2006.173.09:21:23.91#ibcon#about to read 4, iclass 28, count 0 2006.173.09:21:23.91#ibcon#read 4, iclass 28, count 0 2006.173.09:21:23.91#ibcon#about to read 5, iclass 28, count 0 2006.173.09:21:23.91#ibcon#read 5, iclass 28, count 0 2006.173.09:21:23.91#ibcon#about to read 6, iclass 28, count 0 2006.173.09:21:23.91#ibcon#read 6, iclass 28, count 0 2006.173.09:21:23.91#ibcon#end of sib2, iclass 28, count 0 2006.173.09:21:23.91#ibcon#*mode == 0, iclass 28, count 0 2006.173.09:21:23.91#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.09:21:23.91#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.09:21:23.91#ibcon#*before write, iclass 28, count 0 2006.173.09:21:23.91#ibcon#enter sib2, iclass 28, count 0 2006.173.09:21:23.91#ibcon#flushed, iclass 28, count 0 2006.173.09:21:23.91#ibcon#about to write, iclass 28, count 0 2006.173.09:21:23.91#ibcon#wrote, iclass 28, count 0 2006.173.09:21:23.91#ibcon#about to read 3, iclass 28, count 0 2006.173.09:21:23.95#ibcon#read 3, iclass 28, count 0 2006.173.09:21:23.95#ibcon#about to read 4, iclass 28, count 0 2006.173.09:21:23.95#ibcon#read 4, iclass 28, count 0 2006.173.09:21:23.95#ibcon#about to read 5, iclass 28, count 0 2006.173.09:21:23.95#ibcon#read 5, iclass 28, count 0 2006.173.09:21:23.95#ibcon#about to read 6, iclass 28, count 0 2006.173.09:21:23.95#ibcon#read 6, iclass 28, count 0 2006.173.09:21:23.95#ibcon#end of sib2, iclass 28, count 0 2006.173.09:21:23.95#ibcon#*after write, iclass 28, count 0 2006.173.09:21:23.95#ibcon#*before return 0, iclass 28, count 0 2006.173.09:21:23.95#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.09:21:23.95#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.09:21:23.95#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.09:21:23.95#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.09:21:23.95$vck44/va=6,3 2006.173.09:21:23.95#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.09:21:23.95#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.09:21:23.95#ibcon#ireg 11 cls_cnt 2 2006.173.09:21:23.95#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.09:21:24.01#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.09:21:24.01#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.09:21:24.01#ibcon#enter wrdev, iclass 30, count 2 2006.173.09:21:24.01#ibcon#first serial, iclass 30, count 2 2006.173.09:21:24.01#ibcon#enter sib2, iclass 30, count 2 2006.173.09:21:24.01#ibcon#flushed, iclass 30, count 2 2006.173.09:21:24.01#ibcon#about to write, iclass 30, count 2 2006.173.09:21:24.01#ibcon#wrote, iclass 30, count 2 2006.173.09:21:24.01#ibcon#about to read 3, iclass 30, count 2 2006.173.09:21:24.03#ibcon#read 3, iclass 30, count 2 2006.173.09:21:24.03#ibcon#about to read 4, iclass 30, count 2 2006.173.09:21:24.03#ibcon#read 4, iclass 30, count 2 2006.173.09:21:24.03#ibcon#about to read 5, iclass 30, count 2 2006.173.09:21:24.03#ibcon#read 5, iclass 30, count 2 2006.173.09:21:24.03#ibcon#about to read 6, iclass 30, count 2 2006.173.09:21:24.03#ibcon#read 6, iclass 30, count 2 2006.173.09:21:24.03#ibcon#end of sib2, iclass 30, count 2 2006.173.09:21:24.03#ibcon#*mode == 0, iclass 30, count 2 2006.173.09:21:24.03#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.09:21:24.03#ibcon#[25=AT06-03\r\n] 2006.173.09:21:24.03#ibcon#*before write, iclass 30, count 2 2006.173.09:21:24.03#ibcon#enter sib2, iclass 30, count 2 2006.173.09:21:24.03#ibcon#flushed, iclass 30, count 2 2006.173.09:21:24.03#ibcon#about to write, iclass 30, count 2 2006.173.09:21:24.03#ibcon#wrote, iclass 30, count 2 2006.173.09:21:24.03#ibcon#about to read 3, iclass 30, count 2 2006.173.09:21:24.06#ibcon#read 3, iclass 30, count 2 2006.173.09:21:24.06#ibcon#about to read 4, iclass 30, count 2 2006.173.09:21:24.06#ibcon#read 4, iclass 30, count 2 2006.173.09:21:24.06#ibcon#about to read 5, iclass 30, count 2 2006.173.09:21:24.06#ibcon#read 5, iclass 30, count 2 2006.173.09:21:24.06#ibcon#about to read 6, iclass 30, count 2 2006.173.09:21:24.06#ibcon#read 6, iclass 30, count 2 2006.173.09:21:24.06#ibcon#end of sib2, iclass 30, count 2 2006.173.09:21:24.06#ibcon#*after write, iclass 30, count 2 2006.173.09:21:24.06#ibcon#*before return 0, iclass 30, count 2 2006.173.09:21:24.06#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.09:21:24.06#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.09:21:24.06#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.09:21:24.06#ibcon#ireg 7 cls_cnt 0 2006.173.09:21:24.06#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.09:21:24.18#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.09:21:24.18#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.09:21:24.18#ibcon#enter wrdev, iclass 30, count 0 2006.173.09:21:24.18#ibcon#first serial, iclass 30, count 0 2006.173.09:21:24.18#ibcon#enter sib2, iclass 30, count 0 2006.173.09:21:24.18#ibcon#flushed, iclass 30, count 0 2006.173.09:21:24.18#ibcon#about to write, iclass 30, count 0 2006.173.09:21:24.18#ibcon#wrote, iclass 30, count 0 2006.173.09:21:24.18#ibcon#about to read 3, iclass 30, count 0 2006.173.09:21:24.20#ibcon#read 3, iclass 30, count 0 2006.173.09:21:24.20#ibcon#about to read 4, iclass 30, count 0 2006.173.09:21:24.20#ibcon#read 4, iclass 30, count 0 2006.173.09:21:24.20#ibcon#about to read 5, iclass 30, count 0 2006.173.09:21:24.20#ibcon#read 5, iclass 30, count 0 2006.173.09:21:24.20#ibcon#about to read 6, iclass 30, count 0 2006.173.09:21:24.20#ibcon#read 6, iclass 30, count 0 2006.173.09:21:24.20#ibcon#end of sib2, iclass 30, count 0 2006.173.09:21:24.20#ibcon#*mode == 0, iclass 30, count 0 2006.173.09:21:24.20#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.09:21:24.20#ibcon#[25=USB\r\n] 2006.173.09:21:24.20#ibcon#*before write, iclass 30, count 0 2006.173.09:21:24.20#ibcon#enter sib2, iclass 30, count 0 2006.173.09:21:24.20#ibcon#flushed, iclass 30, count 0 2006.173.09:21:24.20#ibcon#about to write, iclass 30, count 0 2006.173.09:21:24.20#ibcon#wrote, iclass 30, count 0 2006.173.09:21:24.20#ibcon#about to read 3, iclass 30, count 0 2006.173.09:21:24.23#ibcon#read 3, iclass 30, count 0 2006.173.09:21:24.23#ibcon#about to read 4, iclass 30, count 0 2006.173.09:21:24.23#ibcon#read 4, iclass 30, count 0 2006.173.09:21:24.23#ibcon#about to read 5, iclass 30, count 0 2006.173.09:21:24.23#ibcon#read 5, iclass 30, count 0 2006.173.09:21:24.23#ibcon#about to read 6, iclass 30, count 0 2006.173.09:21:24.23#ibcon#read 6, iclass 30, count 0 2006.173.09:21:24.23#ibcon#end of sib2, iclass 30, count 0 2006.173.09:21:24.23#ibcon#*after write, iclass 30, count 0 2006.173.09:21:24.23#ibcon#*before return 0, iclass 30, count 0 2006.173.09:21:24.23#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.09:21:24.23#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.09:21:24.23#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.09:21:24.23#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.09:21:24.23$vck44/valo=7,864.99 2006.173.09:21:24.23#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.09:21:24.23#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.09:21:24.23#ibcon#ireg 17 cls_cnt 0 2006.173.09:21:24.23#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.09:21:24.23#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.09:21:24.23#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.09:21:24.23#ibcon#enter wrdev, iclass 32, count 0 2006.173.09:21:24.23#ibcon#first serial, iclass 32, count 0 2006.173.09:21:24.23#ibcon#enter sib2, iclass 32, count 0 2006.173.09:21:24.23#ibcon#flushed, iclass 32, count 0 2006.173.09:21:24.23#ibcon#about to write, iclass 32, count 0 2006.173.09:21:24.23#ibcon#wrote, iclass 32, count 0 2006.173.09:21:24.23#ibcon#about to read 3, iclass 32, count 0 2006.173.09:21:24.25#ibcon#read 3, iclass 32, count 0 2006.173.09:21:24.25#ibcon#about to read 4, iclass 32, count 0 2006.173.09:21:24.25#ibcon#read 4, iclass 32, count 0 2006.173.09:21:24.25#ibcon#about to read 5, iclass 32, count 0 2006.173.09:21:24.25#ibcon#read 5, iclass 32, count 0 2006.173.09:21:24.25#ibcon#about to read 6, iclass 32, count 0 2006.173.09:21:24.25#ibcon#read 6, iclass 32, count 0 2006.173.09:21:24.25#ibcon#end of sib2, iclass 32, count 0 2006.173.09:21:24.25#ibcon#*mode == 0, iclass 32, count 0 2006.173.09:21:24.25#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.09:21:24.25#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.09:21:24.25#ibcon#*before write, iclass 32, count 0 2006.173.09:21:24.25#ibcon#enter sib2, iclass 32, count 0 2006.173.09:21:24.25#ibcon#flushed, iclass 32, count 0 2006.173.09:21:24.25#ibcon#about to write, iclass 32, count 0 2006.173.09:21:24.25#ibcon#wrote, iclass 32, count 0 2006.173.09:21:24.25#ibcon#about to read 3, iclass 32, count 0 2006.173.09:21:24.29#ibcon#read 3, iclass 32, count 0 2006.173.09:21:24.29#ibcon#about to read 4, iclass 32, count 0 2006.173.09:21:24.29#ibcon#read 4, iclass 32, count 0 2006.173.09:21:24.29#ibcon#about to read 5, iclass 32, count 0 2006.173.09:21:24.29#ibcon#read 5, iclass 32, count 0 2006.173.09:21:24.29#ibcon#about to read 6, iclass 32, count 0 2006.173.09:21:24.29#ibcon#read 6, iclass 32, count 0 2006.173.09:21:24.29#ibcon#end of sib2, iclass 32, count 0 2006.173.09:21:24.29#ibcon#*after write, iclass 32, count 0 2006.173.09:21:24.29#ibcon#*before return 0, iclass 32, count 0 2006.173.09:21:24.29#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.09:21:24.29#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.09:21:24.29#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.09:21:24.29#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.09:21:24.29$vck44/va=7,4 2006.173.09:21:24.29#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.09:21:24.29#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.09:21:24.29#ibcon#ireg 11 cls_cnt 2 2006.173.09:21:24.29#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.09:21:24.35#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.09:21:24.35#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.09:21:24.35#ibcon#enter wrdev, iclass 34, count 2 2006.173.09:21:24.35#ibcon#first serial, iclass 34, count 2 2006.173.09:21:24.35#ibcon#enter sib2, iclass 34, count 2 2006.173.09:21:24.35#ibcon#flushed, iclass 34, count 2 2006.173.09:21:24.35#ibcon#about to write, iclass 34, count 2 2006.173.09:21:24.35#ibcon#wrote, iclass 34, count 2 2006.173.09:21:24.35#ibcon#about to read 3, iclass 34, count 2 2006.173.09:21:24.37#ibcon#read 3, iclass 34, count 2 2006.173.09:21:24.37#ibcon#about to read 4, iclass 34, count 2 2006.173.09:21:24.37#ibcon#read 4, iclass 34, count 2 2006.173.09:21:24.37#ibcon#about to read 5, iclass 34, count 2 2006.173.09:21:24.37#ibcon#read 5, iclass 34, count 2 2006.173.09:21:24.37#ibcon#about to read 6, iclass 34, count 2 2006.173.09:21:24.37#ibcon#read 6, iclass 34, count 2 2006.173.09:21:24.37#ibcon#end of sib2, iclass 34, count 2 2006.173.09:21:24.37#ibcon#*mode == 0, iclass 34, count 2 2006.173.09:21:24.37#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.09:21:24.37#ibcon#[25=AT07-04\r\n] 2006.173.09:21:24.37#ibcon#*before write, iclass 34, count 2 2006.173.09:21:24.37#ibcon#enter sib2, iclass 34, count 2 2006.173.09:21:24.37#ibcon#flushed, iclass 34, count 2 2006.173.09:21:24.37#ibcon#about to write, iclass 34, count 2 2006.173.09:21:24.37#ibcon#wrote, iclass 34, count 2 2006.173.09:21:24.37#ibcon#about to read 3, iclass 34, count 2 2006.173.09:21:24.40#ibcon#read 3, iclass 34, count 2 2006.173.09:21:24.40#ibcon#about to read 4, iclass 34, count 2 2006.173.09:21:24.40#ibcon#read 4, iclass 34, count 2 2006.173.09:21:24.40#ibcon#about to read 5, iclass 34, count 2 2006.173.09:21:24.40#ibcon#read 5, iclass 34, count 2 2006.173.09:21:24.40#ibcon#about to read 6, iclass 34, count 2 2006.173.09:21:24.40#ibcon#read 6, iclass 34, count 2 2006.173.09:21:24.40#ibcon#end of sib2, iclass 34, count 2 2006.173.09:21:24.40#ibcon#*after write, iclass 34, count 2 2006.173.09:21:24.40#ibcon#*before return 0, iclass 34, count 2 2006.173.09:21:24.40#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.09:21:24.40#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.09:21:24.40#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.09:21:24.40#ibcon#ireg 7 cls_cnt 0 2006.173.09:21:24.40#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.09:21:24.52#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.09:21:24.52#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.09:21:24.52#ibcon#enter wrdev, iclass 34, count 0 2006.173.09:21:24.52#ibcon#first serial, iclass 34, count 0 2006.173.09:21:24.52#ibcon#enter sib2, iclass 34, count 0 2006.173.09:21:24.52#ibcon#flushed, iclass 34, count 0 2006.173.09:21:24.52#ibcon#about to write, iclass 34, count 0 2006.173.09:21:24.52#ibcon#wrote, iclass 34, count 0 2006.173.09:21:24.52#ibcon#about to read 3, iclass 34, count 0 2006.173.09:21:24.54#ibcon#read 3, iclass 34, count 0 2006.173.09:21:24.54#ibcon#about to read 4, iclass 34, count 0 2006.173.09:21:24.54#ibcon#read 4, iclass 34, count 0 2006.173.09:21:24.54#ibcon#about to read 5, iclass 34, count 0 2006.173.09:21:24.54#ibcon#read 5, iclass 34, count 0 2006.173.09:21:24.54#ibcon#about to read 6, iclass 34, count 0 2006.173.09:21:24.54#ibcon#read 6, iclass 34, count 0 2006.173.09:21:24.54#ibcon#end of sib2, iclass 34, count 0 2006.173.09:21:24.54#ibcon#*mode == 0, iclass 34, count 0 2006.173.09:21:24.54#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.09:21:24.54#ibcon#[25=USB\r\n] 2006.173.09:21:24.54#ibcon#*before write, iclass 34, count 0 2006.173.09:21:24.54#ibcon#enter sib2, iclass 34, count 0 2006.173.09:21:24.54#ibcon#flushed, iclass 34, count 0 2006.173.09:21:24.54#ibcon#about to write, iclass 34, count 0 2006.173.09:21:24.54#ibcon#wrote, iclass 34, count 0 2006.173.09:21:24.54#ibcon#about to read 3, iclass 34, count 0 2006.173.09:21:24.57#ibcon#read 3, iclass 34, count 0 2006.173.09:21:24.57#ibcon#about to read 4, iclass 34, count 0 2006.173.09:21:24.57#ibcon#read 4, iclass 34, count 0 2006.173.09:21:24.57#ibcon#about to read 5, iclass 34, count 0 2006.173.09:21:24.57#ibcon#read 5, iclass 34, count 0 2006.173.09:21:24.57#ibcon#about to read 6, iclass 34, count 0 2006.173.09:21:24.57#ibcon#read 6, iclass 34, count 0 2006.173.09:21:24.57#ibcon#end of sib2, iclass 34, count 0 2006.173.09:21:24.57#ibcon#*after write, iclass 34, count 0 2006.173.09:21:24.57#ibcon#*before return 0, iclass 34, count 0 2006.173.09:21:24.57#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.09:21:24.57#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.09:21:24.57#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.09:21:24.57#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.09:21:24.57$vck44/valo=8,884.99 2006.173.09:21:24.57#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.09:21:24.57#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.09:21:24.57#ibcon#ireg 17 cls_cnt 0 2006.173.09:21:24.57#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.09:21:24.57#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.09:21:24.57#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.09:21:24.57#ibcon#enter wrdev, iclass 36, count 0 2006.173.09:21:24.57#ibcon#first serial, iclass 36, count 0 2006.173.09:21:24.57#ibcon#enter sib2, iclass 36, count 0 2006.173.09:21:24.57#ibcon#flushed, iclass 36, count 0 2006.173.09:21:24.57#ibcon#about to write, iclass 36, count 0 2006.173.09:21:24.57#ibcon#wrote, iclass 36, count 0 2006.173.09:21:24.57#ibcon#about to read 3, iclass 36, count 0 2006.173.09:21:24.59#ibcon#read 3, iclass 36, count 0 2006.173.09:21:24.59#ibcon#about to read 4, iclass 36, count 0 2006.173.09:21:24.59#ibcon#read 4, iclass 36, count 0 2006.173.09:21:24.59#ibcon#about to read 5, iclass 36, count 0 2006.173.09:21:24.59#ibcon#read 5, iclass 36, count 0 2006.173.09:21:24.59#ibcon#about to read 6, iclass 36, count 0 2006.173.09:21:24.59#ibcon#read 6, iclass 36, count 0 2006.173.09:21:24.59#ibcon#end of sib2, iclass 36, count 0 2006.173.09:21:24.59#ibcon#*mode == 0, iclass 36, count 0 2006.173.09:21:24.59#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.09:21:24.59#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.09:21:24.59#ibcon#*before write, iclass 36, count 0 2006.173.09:21:24.59#ibcon#enter sib2, iclass 36, count 0 2006.173.09:21:24.59#ibcon#flushed, iclass 36, count 0 2006.173.09:21:24.59#ibcon#about to write, iclass 36, count 0 2006.173.09:21:24.59#ibcon#wrote, iclass 36, count 0 2006.173.09:21:24.59#ibcon#about to read 3, iclass 36, count 0 2006.173.09:21:24.63#ibcon#read 3, iclass 36, count 0 2006.173.09:21:24.63#ibcon#about to read 4, iclass 36, count 0 2006.173.09:21:24.63#ibcon#read 4, iclass 36, count 0 2006.173.09:21:24.63#ibcon#about to read 5, iclass 36, count 0 2006.173.09:21:24.63#ibcon#read 5, iclass 36, count 0 2006.173.09:21:24.63#ibcon#about to read 6, iclass 36, count 0 2006.173.09:21:24.63#ibcon#read 6, iclass 36, count 0 2006.173.09:21:24.63#ibcon#end of sib2, iclass 36, count 0 2006.173.09:21:24.63#ibcon#*after write, iclass 36, count 0 2006.173.09:21:24.63#ibcon#*before return 0, iclass 36, count 0 2006.173.09:21:24.63#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.09:21:24.63#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.09:21:24.63#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.09:21:24.63#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.09:21:24.63$vck44/va=8,4 2006.173.09:21:24.63#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.09:21:24.63#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.09:21:24.63#ibcon#ireg 11 cls_cnt 2 2006.173.09:21:24.63#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.09:21:24.69#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.09:21:24.69#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.09:21:24.69#ibcon#enter wrdev, iclass 38, count 2 2006.173.09:21:24.69#ibcon#first serial, iclass 38, count 2 2006.173.09:21:24.69#ibcon#enter sib2, iclass 38, count 2 2006.173.09:21:24.69#ibcon#flushed, iclass 38, count 2 2006.173.09:21:24.69#ibcon#about to write, iclass 38, count 2 2006.173.09:21:24.69#ibcon#wrote, iclass 38, count 2 2006.173.09:21:24.69#ibcon#about to read 3, iclass 38, count 2 2006.173.09:21:24.71#ibcon#read 3, iclass 38, count 2 2006.173.09:21:24.71#ibcon#about to read 4, iclass 38, count 2 2006.173.09:21:24.71#ibcon#read 4, iclass 38, count 2 2006.173.09:21:24.71#ibcon#about to read 5, iclass 38, count 2 2006.173.09:21:24.71#ibcon#read 5, iclass 38, count 2 2006.173.09:21:24.71#ibcon#about to read 6, iclass 38, count 2 2006.173.09:21:24.71#ibcon#read 6, iclass 38, count 2 2006.173.09:21:24.71#ibcon#end of sib2, iclass 38, count 2 2006.173.09:21:24.71#ibcon#*mode == 0, iclass 38, count 2 2006.173.09:21:24.71#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.09:21:24.71#ibcon#[25=AT08-04\r\n] 2006.173.09:21:24.71#ibcon#*before write, iclass 38, count 2 2006.173.09:21:24.71#ibcon#enter sib2, iclass 38, count 2 2006.173.09:21:24.71#ibcon#flushed, iclass 38, count 2 2006.173.09:21:24.71#ibcon#about to write, iclass 38, count 2 2006.173.09:21:24.71#ibcon#wrote, iclass 38, count 2 2006.173.09:21:24.71#ibcon#about to read 3, iclass 38, count 2 2006.173.09:21:24.74#ibcon#read 3, iclass 38, count 2 2006.173.09:21:24.74#ibcon#about to read 4, iclass 38, count 2 2006.173.09:21:24.74#ibcon#read 4, iclass 38, count 2 2006.173.09:21:24.74#ibcon#about to read 5, iclass 38, count 2 2006.173.09:21:24.74#ibcon#read 5, iclass 38, count 2 2006.173.09:21:24.74#ibcon#about to read 6, iclass 38, count 2 2006.173.09:21:24.74#ibcon#read 6, iclass 38, count 2 2006.173.09:21:24.74#ibcon#end of sib2, iclass 38, count 2 2006.173.09:21:24.74#ibcon#*after write, iclass 38, count 2 2006.173.09:21:24.74#ibcon#*before return 0, iclass 38, count 2 2006.173.09:21:24.74#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.09:21:24.74#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.09:21:24.74#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.09:21:24.74#ibcon#ireg 7 cls_cnt 0 2006.173.09:21:24.74#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.09:21:24.86#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.09:21:24.86#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.09:21:24.86#ibcon#enter wrdev, iclass 38, count 0 2006.173.09:21:24.86#ibcon#first serial, iclass 38, count 0 2006.173.09:21:24.86#ibcon#enter sib2, iclass 38, count 0 2006.173.09:21:24.86#ibcon#flushed, iclass 38, count 0 2006.173.09:21:24.86#ibcon#about to write, iclass 38, count 0 2006.173.09:21:24.86#ibcon#wrote, iclass 38, count 0 2006.173.09:21:24.86#ibcon#about to read 3, iclass 38, count 0 2006.173.09:21:24.88#ibcon#read 3, iclass 38, count 0 2006.173.09:21:24.88#ibcon#about to read 4, iclass 38, count 0 2006.173.09:21:24.88#ibcon#read 4, iclass 38, count 0 2006.173.09:21:24.88#ibcon#about to read 5, iclass 38, count 0 2006.173.09:21:24.88#ibcon#read 5, iclass 38, count 0 2006.173.09:21:24.88#ibcon#about to read 6, iclass 38, count 0 2006.173.09:21:24.88#ibcon#read 6, iclass 38, count 0 2006.173.09:21:24.88#ibcon#end of sib2, iclass 38, count 0 2006.173.09:21:24.88#ibcon#*mode == 0, iclass 38, count 0 2006.173.09:21:24.88#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.09:21:24.88#ibcon#[25=USB\r\n] 2006.173.09:21:24.88#ibcon#*before write, iclass 38, count 0 2006.173.09:21:24.88#ibcon#enter sib2, iclass 38, count 0 2006.173.09:21:24.88#ibcon#flushed, iclass 38, count 0 2006.173.09:21:24.88#ibcon#about to write, iclass 38, count 0 2006.173.09:21:24.88#ibcon#wrote, iclass 38, count 0 2006.173.09:21:24.88#ibcon#about to read 3, iclass 38, count 0 2006.173.09:21:24.91#ibcon#read 3, iclass 38, count 0 2006.173.09:21:24.91#ibcon#about to read 4, iclass 38, count 0 2006.173.09:21:24.91#ibcon#read 4, iclass 38, count 0 2006.173.09:21:24.91#ibcon#about to read 5, iclass 38, count 0 2006.173.09:21:24.91#ibcon#read 5, iclass 38, count 0 2006.173.09:21:24.91#ibcon#about to read 6, iclass 38, count 0 2006.173.09:21:24.91#ibcon#read 6, iclass 38, count 0 2006.173.09:21:24.91#ibcon#end of sib2, iclass 38, count 0 2006.173.09:21:24.91#ibcon#*after write, iclass 38, count 0 2006.173.09:21:24.91#ibcon#*before return 0, iclass 38, count 0 2006.173.09:21:24.91#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.09:21:24.91#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.09:21:24.91#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.09:21:24.91#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.09:21:24.91$vck44/vblo=1,629.99 2006.173.09:21:24.91#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.09:21:24.91#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.09:21:24.91#ibcon#ireg 17 cls_cnt 0 2006.173.09:21:24.91#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.09:21:24.91#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.09:21:24.91#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.09:21:24.91#ibcon#enter wrdev, iclass 40, count 0 2006.173.09:21:24.91#ibcon#first serial, iclass 40, count 0 2006.173.09:21:24.91#ibcon#enter sib2, iclass 40, count 0 2006.173.09:21:24.91#ibcon#flushed, iclass 40, count 0 2006.173.09:21:24.91#ibcon#about to write, iclass 40, count 0 2006.173.09:21:24.91#ibcon#wrote, iclass 40, count 0 2006.173.09:21:24.91#ibcon#about to read 3, iclass 40, count 0 2006.173.09:21:24.93#ibcon#read 3, iclass 40, count 0 2006.173.09:21:24.93#ibcon#about to read 4, iclass 40, count 0 2006.173.09:21:24.93#ibcon#read 4, iclass 40, count 0 2006.173.09:21:24.93#ibcon#about to read 5, iclass 40, count 0 2006.173.09:21:24.93#ibcon#read 5, iclass 40, count 0 2006.173.09:21:24.93#ibcon#about to read 6, iclass 40, count 0 2006.173.09:21:24.93#ibcon#read 6, iclass 40, count 0 2006.173.09:21:24.93#ibcon#end of sib2, iclass 40, count 0 2006.173.09:21:24.93#ibcon#*mode == 0, iclass 40, count 0 2006.173.09:21:24.93#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.09:21:24.93#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.09:21:24.93#ibcon#*before write, iclass 40, count 0 2006.173.09:21:24.93#ibcon#enter sib2, iclass 40, count 0 2006.173.09:21:24.93#ibcon#flushed, iclass 40, count 0 2006.173.09:21:24.93#ibcon#about to write, iclass 40, count 0 2006.173.09:21:24.93#ibcon#wrote, iclass 40, count 0 2006.173.09:21:24.93#ibcon#about to read 3, iclass 40, count 0 2006.173.09:21:24.97#ibcon#read 3, iclass 40, count 0 2006.173.09:21:24.97#ibcon#about to read 4, iclass 40, count 0 2006.173.09:21:24.97#ibcon#read 4, iclass 40, count 0 2006.173.09:21:24.97#ibcon#about to read 5, iclass 40, count 0 2006.173.09:21:24.97#ibcon#read 5, iclass 40, count 0 2006.173.09:21:24.97#ibcon#about to read 6, iclass 40, count 0 2006.173.09:21:24.97#ibcon#read 6, iclass 40, count 0 2006.173.09:21:24.97#ibcon#end of sib2, iclass 40, count 0 2006.173.09:21:24.97#ibcon#*after write, iclass 40, count 0 2006.173.09:21:24.97#ibcon#*before return 0, iclass 40, count 0 2006.173.09:21:24.97#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.09:21:24.97#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.09:21:24.97#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.09:21:24.97#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.09:21:24.97$vck44/vb=1,4 2006.173.09:21:24.97#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.09:21:24.97#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.09:21:24.97#ibcon#ireg 11 cls_cnt 2 2006.173.09:21:24.97#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.09:21:24.97#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.09:21:24.97#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.09:21:24.97#ibcon#enter wrdev, iclass 4, count 2 2006.173.09:21:24.97#ibcon#first serial, iclass 4, count 2 2006.173.09:21:24.97#ibcon#enter sib2, iclass 4, count 2 2006.173.09:21:24.97#ibcon#flushed, iclass 4, count 2 2006.173.09:21:24.97#ibcon#about to write, iclass 4, count 2 2006.173.09:21:24.97#ibcon#wrote, iclass 4, count 2 2006.173.09:21:24.97#ibcon#about to read 3, iclass 4, count 2 2006.173.09:21:24.99#ibcon#read 3, iclass 4, count 2 2006.173.09:21:24.99#ibcon#about to read 4, iclass 4, count 2 2006.173.09:21:24.99#ibcon#read 4, iclass 4, count 2 2006.173.09:21:24.99#ibcon#about to read 5, iclass 4, count 2 2006.173.09:21:24.99#ibcon#read 5, iclass 4, count 2 2006.173.09:21:24.99#ibcon#about to read 6, iclass 4, count 2 2006.173.09:21:24.99#ibcon#read 6, iclass 4, count 2 2006.173.09:21:24.99#ibcon#end of sib2, iclass 4, count 2 2006.173.09:21:24.99#ibcon#*mode == 0, iclass 4, count 2 2006.173.09:21:24.99#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.09:21:24.99#ibcon#[27=AT01-04\r\n] 2006.173.09:21:24.99#ibcon#*before write, iclass 4, count 2 2006.173.09:21:24.99#ibcon#enter sib2, iclass 4, count 2 2006.173.09:21:24.99#ibcon#flushed, iclass 4, count 2 2006.173.09:21:24.99#ibcon#about to write, iclass 4, count 2 2006.173.09:21:24.99#ibcon#wrote, iclass 4, count 2 2006.173.09:21:24.99#ibcon#about to read 3, iclass 4, count 2 2006.173.09:21:25.02#ibcon#read 3, iclass 4, count 2 2006.173.09:21:25.02#ibcon#about to read 4, iclass 4, count 2 2006.173.09:21:25.02#ibcon#read 4, iclass 4, count 2 2006.173.09:21:25.02#ibcon#about to read 5, iclass 4, count 2 2006.173.09:21:25.02#ibcon#read 5, iclass 4, count 2 2006.173.09:21:25.02#ibcon#about to read 6, iclass 4, count 2 2006.173.09:21:25.02#ibcon#read 6, iclass 4, count 2 2006.173.09:21:25.02#ibcon#end of sib2, iclass 4, count 2 2006.173.09:21:25.02#ibcon#*after write, iclass 4, count 2 2006.173.09:21:25.02#ibcon#*before return 0, iclass 4, count 2 2006.173.09:21:25.02#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.09:21:25.02#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.09:21:25.02#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.09:21:25.02#ibcon#ireg 7 cls_cnt 0 2006.173.09:21:25.02#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.09:21:25.14#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.09:21:25.14#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.09:21:25.14#ibcon#enter wrdev, iclass 4, count 0 2006.173.09:21:25.14#ibcon#first serial, iclass 4, count 0 2006.173.09:21:25.14#ibcon#enter sib2, iclass 4, count 0 2006.173.09:21:25.14#ibcon#flushed, iclass 4, count 0 2006.173.09:21:25.14#ibcon#about to write, iclass 4, count 0 2006.173.09:21:25.14#ibcon#wrote, iclass 4, count 0 2006.173.09:21:25.14#ibcon#about to read 3, iclass 4, count 0 2006.173.09:21:25.16#ibcon#read 3, iclass 4, count 0 2006.173.09:21:25.16#ibcon#about to read 4, iclass 4, count 0 2006.173.09:21:25.16#ibcon#read 4, iclass 4, count 0 2006.173.09:21:25.16#ibcon#about to read 5, iclass 4, count 0 2006.173.09:21:25.16#ibcon#read 5, iclass 4, count 0 2006.173.09:21:25.16#ibcon#about to read 6, iclass 4, count 0 2006.173.09:21:25.16#ibcon#read 6, iclass 4, count 0 2006.173.09:21:25.16#ibcon#end of sib2, iclass 4, count 0 2006.173.09:21:25.16#ibcon#*mode == 0, iclass 4, count 0 2006.173.09:21:25.16#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.09:21:25.16#ibcon#[27=USB\r\n] 2006.173.09:21:25.16#ibcon#*before write, iclass 4, count 0 2006.173.09:21:25.16#ibcon#enter sib2, iclass 4, count 0 2006.173.09:21:25.16#ibcon#flushed, iclass 4, count 0 2006.173.09:21:25.16#ibcon#about to write, iclass 4, count 0 2006.173.09:21:25.16#ibcon#wrote, iclass 4, count 0 2006.173.09:21:25.16#ibcon#about to read 3, iclass 4, count 0 2006.173.09:21:25.19#ibcon#read 3, iclass 4, count 0 2006.173.09:21:25.19#ibcon#about to read 4, iclass 4, count 0 2006.173.09:21:25.19#ibcon#read 4, iclass 4, count 0 2006.173.09:21:25.19#ibcon#about to read 5, iclass 4, count 0 2006.173.09:21:25.19#ibcon#read 5, iclass 4, count 0 2006.173.09:21:25.19#ibcon#about to read 6, iclass 4, count 0 2006.173.09:21:25.19#ibcon#read 6, iclass 4, count 0 2006.173.09:21:25.19#ibcon#end of sib2, iclass 4, count 0 2006.173.09:21:25.19#ibcon#*after write, iclass 4, count 0 2006.173.09:21:25.19#ibcon#*before return 0, iclass 4, count 0 2006.173.09:21:25.19#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.09:21:25.19#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.09:21:25.19#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.09:21:25.19#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.09:21:25.19$vck44/vblo=2,634.99 2006.173.09:21:25.19#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.09:21:25.19#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.09:21:25.19#ibcon#ireg 17 cls_cnt 0 2006.173.09:21:25.19#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.09:21:25.19#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.09:21:25.19#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.09:21:25.19#ibcon#enter wrdev, iclass 6, count 0 2006.173.09:21:25.19#ibcon#first serial, iclass 6, count 0 2006.173.09:21:25.19#ibcon#enter sib2, iclass 6, count 0 2006.173.09:21:25.19#ibcon#flushed, iclass 6, count 0 2006.173.09:21:25.19#ibcon#about to write, iclass 6, count 0 2006.173.09:21:25.19#ibcon#wrote, iclass 6, count 0 2006.173.09:21:25.19#ibcon#about to read 3, iclass 6, count 0 2006.173.09:21:25.21#ibcon#read 3, iclass 6, count 0 2006.173.09:21:25.21#ibcon#about to read 4, iclass 6, count 0 2006.173.09:21:25.21#ibcon#read 4, iclass 6, count 0 2006.173.09:21:25.21#ibcon#about to read 5, iclass 6, count 0 2006.173.09:21:25.21#ibcon#read 5, iclass 6, count 0 2006.173.09:21:25.21#ibcon#about to read 6, iclass 6, count 0 2006.173.09:21:25.21#ibcon#read 6, iclass 6, count 0 2006.173.09:21:25.21#ibcon#end of sib2, iclass 6, count 0 2006.173.09:21:25.21#ibcon#*mode == 0, iclass 6, count 0 2006.173.09:21:25.21#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.09:21:25.21#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.09:21:25.21#ibcon#*before write, iclass 6, count 0 2006.173.09:21:25.21#ibcon#enter sib2, iclass 6, count 0 2006.173.09:21:25.21#ibcon#flushed, iclass 6, count 0 2006.173.09:21:25.21#ibcon#about to write, iclass 6, count 0 2006.173.09:21:25.21#ibcon#wrote, iclass 6, count 0 2006.173.09:21:25.21#ibcon#about to read 3, iclass 6, count 0 2006.173.09:21:25.25#ibcon#read 3, iclass 6, count 0 2006.173.09:21:25.25#ibcon#about to read 4, iclass 6, count 0 2006.173.09:21:25.25#ibcon#read 4, iclass 6, count 0 2006.173.09:21:25.25#ibcon#about to read 5, iclass 6, count 0 2006.173.09:21:25.25#ibcon#read 5, iclass 6, count 0 2006.173.09:21:25.25#ibcon#about to read 6, iclass 6, count 0 2006.173.09:21:25.25#ibcon#read 6, iclass 6, count 0 2006.173.09:21:25.25#ibcon#end of sib2, iclass 6, count 0 2006.173.09:21:25.25#ibcon#*after write, iclass 6, count 0 2006.173.09:21:25.25#ibcon#*before return 0, iclass 6, count 0 2006.173.09:21:25.25#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.09:21:25.25#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.09:21:25.25#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.09:21:25.25#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.09:21:25.25$vck44/vb=2,4 2006.173.09:21:25.25#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.09:21:25.25#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.09:21:25.25#ibcon#ireg 11 cls_cnt 2 2006.173.09:21:25.25#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.09:21:25.31#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.09:21:25.31#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.09:21:25.31#ibcon#enter wrdev, iclass 10, count 2 2006.173.09:21:25.31#ibcon#first serial, iclass 10, count 2 2006.173.09:21:25.31#ibcon#enter sib2, iclass 10, count 2 2006.173.09:21:25.31#ibcon#flushed, iclass 10, count 2 2006.173.09:21:25.31#ibcon#about to write, iclass 10, count 2 2006.173.09:21:25.31#ibcon#wrote, iclass 10, count 2 2006.173.09:21:25.31#ibcon#about to read 3, iclass 10, count 2 2006.173.09:21:25.33#ibcon#read 3, iclass 10, count 2 2006.173.09:21:25.33#ibcon#about to read 4, iclass 10, count 2 2006.173.09:21:25.33#ibcon#read 4, iclass 10, count 2 2006.173.09:21:25.33#ibcon#about to read 5, iclass 10, count 2 2006.173.09:21:25.33#ibcon#read 5, iclass 10, count 2 2006.173.09:21:25.33#ibcon#about to read 6, iclass 10, count 2 2006.173.09:21:25.33#ibcon#read 6, iclass 10, count 2 2006.173.09:21:25.33#ibcon#end of sib2, iclass 10, count 2 2006.173.09:21:25.33#ibcon#*mode == 0, iclass 10, count 2 2006.173.09:21:25.33#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.09:21:25.33#ibcon#[27=AT02-04\r\n] 2006.173.09:21:25.33#ibcon#*before write, iclass 10, count 2 2006.173.09:21:25.33#ibcon#enter sib2, iclass 10, count 2 2006.173.09:21:25.33#ibcon#flushed, iclass 10, count 2 2006.173.09:21:25.33#ibcon#about to write, iclass 10, count 2 2006.173.09:21:25.33#ibcon#wrote, iclass 10, count 2 2006.173.09:21:25.33#ibcon#about to read 3, iclass 10, count 2 2006.173.09:21:25.36#ibcon#read 3, iclass 10, count 2 2006.173.09:21:25.36#ibcon#about to read 4, iclass 10, count 2 2006.173.09:21:25.36#ibcon#read 4, iclass 10, count 2 2006.173.09:21:25.36#ibcon#about to read 5, iclass 10, count 2 2006.173.09:21:25.36#ibcon#read 5, iclass 10, count 2 2006.173.09:21:25.36#ibcon#about to read 6, iclass 10, count 2 2006.173.09:21:25.36#ibcon#read 6, iclass 10, count 2 2006.173.09:21:25.36#ibcon#end of sib2, iclass 10, count 2 2006.173.09:21:25.36#ibcon#*after write, iclass 10, count 2 2006.173.09:21:25.36#ibcon#*before return 0, iclass 10, count 2 2006.173.09:21:25.36#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.09:21:25.36#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.09:21:25.36#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.09:21:25.36#ibcon#ireg 7 cls_cnt 0 2006.173.09:21:25.36#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.09:21:25.48#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.09:21:25.48#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.09:21:25.48#ibcon#enter wrdev, iclass 10, count 0 2006.173.09:21:25.48#ibcon#first serial, iclass 10, count 0 2006.173.09:21:25.48#ibcon#enter sib2, iclass 10, count 0 2006.173.09:21:25.48#ibcon#flushed, iclass 10, count 0 2006.173.09:21:25.48#ibcon#about to write, iclass 10, count 0 2006.173.09:21:25.48#ibcon#wrote, iclass 10, count 0 2006.173.09:21:25.48#ibcon#about to read 3, iclass 10, count 0 2006.173.09:21:25.50#ibcon#read 3, iclass 10, count 0 2006.173.09:21:25.50#ibcon#about to read 4, iclass 10, count 0 2006.173.09:21:25.50#ibcon#read 4, iclass 10, count 0 2006.173.09:21:25.50#ibcon#about to read 5, iclass 10, count 0 2006.173.09:21:25.50#ibcon#read 5, iclass 10, count 0 2006.173.09:21:25.50#ibcon#about to read 6, iclass 10, count 0 2006.173.09:21:25.50#ibcon#read 6, iclass 10, count 0 2006.173.09:21:25.50#ibcon#end of sib2, iclass 10, count 0 2006.173.09:21:25.50#ibcon#*mode == 0, iclass 10, count 0 2006.173.09:21:25.50#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.09:21:25.50#ibcon#[27=USB\r\n] 2006.173.09:21:25.50#ibcon#*before write, iclass 10, count 0 2006.173.09:21:25.50#ibcon#enter sib2, iclass 10, count 0 2006.173.09:21:25.50#ibcon#flushed, iclass 10, count 0 2006.173.09:21:25.50#ibcon#about to write, iclass 10, count 0 2006.173.09:21:25.50#ibcon#wrote, iclass 10, count 0 2006.173.09:21:25.50#ibcon#about to read 3, iclass 10, count 0 2006.173.09:21:25.53#ibcon#read 3, iclass 10, count 0 2006.173.09:21:25.53#ibcon#about to read 4, iclass 10, count 0 2006.173.09:21:25.53#ibcon#read 4, iclass 10, count 0 2006.173.09:21:25.53#ibcon#about to read 5, iclass 10, count 0 2006.173.09:21:25.53#ibcon#read 5, iclass 10, count 0 2006.173.09:21:25.53#ibcon#about to read 6, iclass 10, count 0 2006.173.09:21:25.53#ibcon#read 6, iclass 10, count 0 2006.173.09:21:25.53#ibcon#end of sib2, iclass 10, count 0 2006.173.09:21:25.53#ibcon#*after write, iclass 10, count 0 2006.173.09:21:25.53#ibcon#*before return 0, iclass 10, count 0 2006.173.09:21:25.53#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.09:21:25.53#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.09:21:25.53#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.09:21:25.53#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.09:21:25.53$vck44/vblo=3,649.99 2006.173.09:21:25.53#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.09:21:25.53#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.09:21:25.53#ibcon#ireg 17 cls_cnt 0 2006.173.09:21:25.53#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.09:21:25.53#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.09:21:25.53#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.09:21:25.53#ibcon#enter wrdev, iclass 12, count 0 2006.173.09:21:25.53#ibcon#first serial, iclass 12, count 0 2006.173.09:21:25.53#ibcon#enter sib2, iclass 12, count 0 2006.173.09:21:25.53#ibcon#flushed, iclass 12, count 0 2006.173.09:21:25.53#ibcon#about to write, iclass 12, count 0 2006.173.09:21:25.53#ibcon#wrote, iclass 12, count 0 2006.173.09:21:25.53#ibcon#about to read 3, iclass 12, count 0 2006.173.09:21:25.55#ibcon#read 3, iclass 12, count 0 2006.173.09:21:25.55#ibcon#about to read 4, iclass 12, count 0 2006.173.09:21:25.55#ibcon#read 4, iclass 12, count 0 2006.173.09:21:25.55#ibcon#about to read 5, iclass 12, count 0 2006.173.09:21:25.55#ibcon#read 5, iclass 12, count 0 2006.173.09:21:25.55#ibcon#about to read 6, iclass 12, count 0 2006.173.09:21:25.55#ibcon#read 6, iclass 12, count 0 2006.173.09:21:25.55#ibcon#end of sib2, iclass 12, count 0 2006.173.09:21:25.55#ibcon#*mode == 0, iclass 12, count 0 2006.173.09:21:25.55#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.09:21:25.55#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.09:21:25.55#ibcon#*before write, iclass 12, count 0 2006.173.09:21:25.55#ibcon#enter sib2, iclass 12, count 0 2006.173.09:21:25.55#ibcon#flushed, iclass 12, count 0 2006.173.09:21:25.55#ibcon#about to write, iclass 12, count 0 2006.173.09:21:25.55#ibcon#wrote, iclass 12, count 0 2006.173.09:21:25.55#ibcon#about to read 3, iclass 12, count 0 2006.173.09:21:25.59#ibcon#read 3, iclass 12, count 0 2006.173.09:21:25.59#ibcon#about to read 4, iclass 12, count 0 2006.173.09:21:25.59#ibcon#read 4, iclass 12, count 0 2006.173.09:21:25.59#ibcon#about to read 5, iclass 12, count 0 2006.173.09:21:25.59#ibcon#read 5, iclass 12, count 0 2006.173.09:21:25.59#ibcon#about to read 6, iclass 12, count 0 2006.173.09:21:25.59#ibcon#read 6, iclass 12, count 0 2006.173.09:21:25.59#ibcon#end of sib2, iclass 12, count 0 2006.173.09:21:25.59#ibcon#*after write, iclass 12, count 0 2006.173.09:21:25.59#ibcon#*before return 0, iclass 12, count 0 2006.173.09:21:25.59#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.09:21:25.59#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.09:21:25.59#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.09:21:25.59#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.09:21:25.59$vck44/vb=3,4 2006.173.09:21:25.59#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.09:21:25.59#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.09:21:25.59#ibcon#ireg 11 cls_cnt 2 2006.173.09:21:25.59#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.09:21:25.65#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.09:21:25.65#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.09:21:25.65#ibcon#enter wrdev, iclass 14, count 2 2006.173.09:21:25.65#ibcon#first serial, iclass 14, count 2 2006.173.09:21:25.65#ibcon#enter sib2, iclass 14, count 2 2006.173.09:21:25.65#ibcon#flushed, iclass 14, count 2 2006.173.09:21:25.65#ibcon#about to write, iclass 14, count 2 2006.173.09:21:25.65#ibcon#wrote, iclass 14, count 2 2006.173.09:21:25.65#ibcon#about to read 3, iclass 14, count 2 2006.173.09:21:25.67#ibcon#read 3, iclass 14, count 2 2006.173.09:21:25.67#ibcon#about to read 4, iclass 14, count 2 2006.173.09:21:25.67#ibcon#read 4, iclass 14, count 2 2006.173.09:21:25.67#ibcon#about to read 5, iclass 14, count 2 2006.173.09:21:25.67#ibcon#read 5, iclass 14, count 2 2006.173.09:21:25.67#ibcon#about to read 6, iclass 14, count 2 2006.173.09:21:25.67#ibcon#read 6, iclass 14, count 2 2006.173.09:21:25.67#ibcon#end of sib2, iclass 14, count 2 2006.173.09:21:25.67#ibcon#*mode == 0, iclass 14, count 2 2006.173.09:21:25.67#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.09:21:25.67#ibcon#[27=AT03-04\r\n] 2006.173.09:21:25.67#ibcon#*before write, iclass 14, count 2 2006.173.09:21:25.67#ibcon#enter sib2, iclass 14, count 2 2006.173.09:21:25.67#ibcon#flushed, iclass 14, count 2 2006.173.09:21:25.67#ibcon#about to write, iclass 14, count 2 2006.173.09:21:25.67#ibcon#wrote, iclass 14, count 2 2006.173.09:21:25.67#ibcon#about to read 3, iclass 14, count 2 2006.173.09:21:25.70#ibcon#read 3, iclass 14, count 2 2006.173.09:21:25.70#ibcon#about to read 4, iclass 14, count 2 2006.173.09:21:25.70#ibcon#read 4, iclass 14, count 2 2006.173.09:21:25.70#ibcon#about to read 5, iclass 14, count 2 2006.173.09:21:25.70#ibcon#read 5, iclass 14, count 2 2006.173.09:21:25.70#ibcon#about to read 6, iclass 14, count 2 2006.173.09:21:25.70#ibcon#read 6, iclass 14, count 2 2006.173.09:21:25.70#ibcon#end of sib2, iclass 14, count 2 2006.173.09:21:25.70#ibcon#*after write, iclass 14, count 2 2006.173.09:21:25.70#ibcon#*before return 0, iclass 14, count 2 2006.173.09:21:25.70#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.09:21:25.70#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.09:21:25.70#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.09:21:25.70#ibcon#ireg 7 cls_cnt 0 2006.173.09:21:25.70#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.09:21:25.82#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.09:21:25.82#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.09:21:25.82#ibcon#enter wrdev, iclass 14, count 0 2006.173.09:21:25.82#ibcon#first serial, iclass 14, count 0 2006.173.09:21:25.82#ibcon#enter sib2, iclass 14, count 0 2006.173.09:21:25.82#ibcon#flushed, iclass 14, count 0 2006.173.09:21:25.82#ibcon#about to write, iclass 14, count 0 2006.173.09:21:25.82#ibcon#wrote, iclass 14, count 0 2006.173.09:21:25.82#ibcon#about to read 3, iclass 14, count 0 2006.173.09:21:25.84#ibcon#read 3, iclass 14, count 0 2006.173.09:21:25.84#ibcon#about to read 4, iclass 14, count 0 2006.173.09:21:25.84#ibcon#read 4, iclass 14, count 0 2006.173.09:21:25.84#ibcon#about to read 5, iclass 14, count 0 2006.173.09:21:25.84#ibcon#read 5, iclass 14, count 0 2006.173.09:21:25.84#ibcon#about to read 6, iclass 14, count 0 2006.173.09:21:25.84#ibcon#read 6, iclass 14, count 0 2006.173.09:21:25.84#ibcon#end of sib2, iclass 14, count 0 2006.173.09:21:25.84#ibcon#*mode == 0, iclass 14, count 0 2006.173.09:21:25.84#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.09:21:25.84#ibcon#[27=USB\r\n] 2006.173.09:21:25.84#ibcon#*before write, iclass 14, count 0 2006.173.09:21:25.84#ibcon#enter sib2, iclass 14, count 0 2006.173.09:21:25.84#ibcon#flushed, iclass 14, count 0 2006.173.09:21:25.84#ibcon#about to write, iclass 14, count 0 2006.173.09:21:25.84#ibcon#wrote, iclass 14, count 0 2006.173.09:21:25.84#ibcon#about to read 3, iclass 14, count 0 2006.173.09:21:25.87#ibcon#read 3, iclass 14, count 0 2006.173.09:21:25.87#ibcon#about to read 4, iclass 14, count 0 2006.173.09:21:25.87#ibcon#read 4, iclass 14, count 0 2006.173.09:21:25.87#ibcon#about to read 5, iclass 14, count 0 2006.173.09:21:25.87#ibcon#read 5, iclass 14, count 0 2006.173.09:21:25.87#ibcon#about to read 6, iclass 14, count 0 2006.173.09:21:25.87#ibcon#read 6, iclass 14, count 0 2006.173.09:21:25.87#ibcon#end of sib2, iclass 14, count 0 2006.173.09:21:25.87#ibcon#*after write, iclass 14, count 0 2006.173.09:21:25.87#ibcon#*before return 0, iclass 14, count 0 2006.173.09:21:25.87#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.09:21:25.87#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.09:21:25.87#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.09:21:25.87#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.09:21:25.87$vck44/vblo=4,679.99 2006.173.09:21:25.87#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.09:21:25.87#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.09:21:25.87#ibcon#ireg 17 cls_cnt 0 2006.173.09:21:25.87#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.09:21:25.87#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.09:21:25.87#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.09:21:25.87#ibcon#enter wrdev, iclass 16, count 0 2006.173.09:21:25.87#ibcon#first serial, iclass 16, count 0 2006.173.09:21:25.87#ibcon#enter sib2, iclass 16, count 0 2006.173.09:21:25.87#ibcon#flushed, iclass 16, count 0 2006.173.09:21:25.87#ibcon#about to write, iclass 16, count 0 2006.173.09:21:25.87#ibcon#wrote, iclass 16, count 0 2006.173.09:21:25.87#ibcon#about to read 3, iclass 16, count 0 2006.173.09:21:25.89#ibcon#read 3, iclass 16, count 0 2006.173.09:21:25.89#ibcon#about to read 4, iclass 16, count 0 2006.173.09:21:25.89#ibcon#read 4, iclass 16, count 0 2006.173.09:21:25.89#ibcon#about to read 5, iclass 16, count 0 2006.173.09:21:25.89#ibcon#read 5, iclass 16, count 0 2006.173.09:21:25.89#ibcon#about to read 6, iclass 16, count 0 2006.173.09:21:25.89#ibcon#read 6, iclass 16, count 0 2006.173.09:21:25.89#ibcon#end of sib2, iclass 16, count 0 2006.173.09:21:25.89#ibcon#*mode == 0, iclass 16, count 0 2006.173.09:21:25.89#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.09:21:25.89#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.09:21:25.89#ibcon#*before write, iclass 16, count 0 2006.173.09:21:25.89#ibcon#enter sib2, iclass 16, count 0 2006.173.09:21:25.89#ibcon#flushed, iclass 16, count 0 2006.173.09:21:25.89#ibcon#about to write, iclass 16, count 0 2006.173.09:21:25.89#ibcon#wrote, iclass 16, count 0 2006.173.09:21:25.89#ibcon#about to read 3, iclass 16, count 0 2006.173.09:21:25.93#ibcon#read 3, iclass 16, count 0 2006.173.09:21:25.93#ibcon#about to read 4, iclass 16, count 0 2006.173.09:21:25.93#ibcon#read 4, iclass 16, count 0 2006.173.09:21:25.93#ibcon#about to read 5, iclass 16, count 0 2006.173.09:21:25.93#ibcon#read 5, iclass 16, count 0 2006.173.09:21:25.93#ibcon#about to read 6, iclass 16, count 0 2006.173.09:21:25.93#ibcon#read 6, iclass 16, count 0 2006.173.09:21:25.93#ibcon#end of sib2, iclass 16, count 0 2006.173.09:21:25.93#ibcon#*after write, iclass 16, count 0 2006.173.09:21:25.93#ibcon#*before return 0, iclass 16, count 0 2006.173.09:21:25.93#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.09:21:25.93#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.09:21:25.93#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.09:21:25.93#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.09:21:25.93$vck44/vb=4,4 2006.173.09:21:25.93#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.09:21:25.93#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.09:21:25.93#ibcon#ireg 11 cls_cnt 2 2006.173.09:21:25.93#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.09:21:25.99#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.09:21:25.99#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.09:21:25.99#ibcon#enter wrdev, iclass 18, count 2 2006.173.09:21:25.99#ibcon#first serial, iclass 18, count 2 2006.173.09:21:25.99#ibcon#enter sib2, iclass 18, count 2 2006.173.09:21:25.99#ibcon#flushed, iclass 18, count 2 2006.173.09:21:25.99#ibcon#about to write, iclass 18, count 2 2006.173.09:21:25.99#ibcon#wrote, iclass 18, count 2 2006.173.09:21:25.99#ibcon#about to read 3, iclass 18, count 2 2006.173.09:21:26.01#ibcon#read 3, iclass 18, count 2 2006.173.09:21:26.01#ibcon#about to read 4, iclass 18, count 2 2006.173.09:21:26.01#ibcon#read 4, iclass 18, count 2 2006.173.09:21:26.01#ibcon#about to read 5, iclass 18, count 2 2006.173.09:21:26.01#ibcon#read 5, iclass 18, count 2 2006.173.09:21:26.01#ibcon#about to read 6, iclass 18, count 2 2006.173.09:21:26.01#ibcon#read 6, iclass 18, count 2 2006.173.09:21:26.01#ibcon#end of sib2, iclass 18, count 2 2006.173.09:21:26.01#ibcon#*mode == 0, iclass 18, count 2 2006.173.09:21:26.01#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.09:21:26.01#ibcon#[27=AT04-04\r\n] 2006.173.09:21:26.01#ibcon#*before write, iclass 18, count 2 2006.173.09:21:26.01#ibcon#enter sib2, iclass 18, count 2 2006.173.09:21:26.01#ibcon#flushed, iclass 18, count 2 2006.173.09:21:26.01#ibcon#about to write, iclass 18, count 2 2006.173.09:21:26.01#ibcon#wrote, iclass 18, count 2 2006.173.09:21:26.01#ibcon#about to read 3, iclass 18, count 2 2006.173.09:21:26.04#ibcon#read 3, iclass 18, count 2 2006.173.09:21:26.04#ibcon#about to read 4, iclass 18, count 2 2006.173.09:21:26.04#ibcon#read 4, iclass 18, count 2 2006.173.09:21:26.04#ibcon#about to read 5, iclass 18, count 2 2006.173.09:21:26.04#ibcon#read 5, iclass 18, count 2 2006.173.09:21:26.04#ibcon#about to read 6, iclass 18, count 2 2006.173.09:21:26.04#ibcon#read 6, iclass 18, count 2 2006.173.09:21:26.04#ibcon#end of sib2, iclass 18, count 2 2006.173.09:21:26.04#ibcon#*after write, iclass 18, count 2 2006.173.09:21:26.04#ibcon#*before return 0, iclass 18, count 2 2006.173.09:21:26.04#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.09:21:26.04#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.09:21:26.04#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.09:21:26.04#ibcon#ireg 7 cls_cnt 0 2006.173.09:21:26.04#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.09:21:26.16#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.09:21:26.16#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.09:21:26.16#ibcon#enter wrdev, iclass 18, count 0 2006.173.09:21:26.16#ibcon#first serial, iclass 18, count 0 2006.173.09:21:26.16#ibcon#enter sib2, iclass 18, count 0 2006.173.09:21:26.16#ibcon#flushed, iclass 18, count 0 2006.173.09:21:26.16#ibcon#about to write, iclass 18, count 0 2006.173.09:21:26.16#ibcon#wrote, iclass 18, count 0 2006.173.09:21:26.16#ibcon#about to read 3, iclass 18, count 0 2006.173.09:21:26.18#ibcon#read 3, iclass 18, count 0 2006.173.09:21:26.18#ibcon#about to read 4, iclass 18, count 0 2006.173.09:21:26.18#ibcon#read 4, iclass 18, count 0 2006.173.09:21:26.18#ibcon#about to read 5, iclass 18, count 0 2006.173.09:21:26.18#ibcon#read 5, iclass 18, count 0 2006.173.09:21:26.18#ibcon#about to read 6, iclass 18, count 0 2006.173.09:21:26.18#ibcon#read 6, iclass 18, count 0 2006.173.09:21:26.18#ibcon#end of sib2, iclass 18, count 0 2006.173.09:21:26.18#ibcon#*mode == 0, iclass 18, count 0 2006.173.09:21:26.18#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.09:21:26.18#ibcon#[27=USB\r\n] 2006.173.09:21:26.18#ibcon#*before write, iclass 18, count 0 2006.173.09:21:26.18#ibcon#enter sib2, iclass 18, count 0 2006.173.09:21:26.18#ibcon#flushed, iclass 18, count 0 2006.173.09:21:26.18#ibcon#about to write, iclass 18, count 0 2006.173.09:21:26.18#ibcon#wrote, iclass 18, count 0 2006.173.09:21:26.18#ibcon#about to read 3, iclass 18, count 0 2006.173.09:21:26.21#ibcon#read 3, iclass 18, count 0 2006.173.09:21:26.21#ibcon#about to read 4, iclass 18, count 0 2006.173.09:21:26.21#ibcon#read 4, iclass 18, count 0 2006.173.09:21:26.21#ibcon#about to read 5, iclass 18, count 0 2006.173.09:21:26.21#ibcon#read 5, iclass 18, count 0 2006.173.09:21:26.21#ibcon#about to read 6, iclass 18, count 0 2006.173.09:21:26.21#ibcon#read 6, iclass 18, count 0 2006.173.09:21:26.21#ibcon#end of sib2, iclass 18, count 0 2006.173.09:21:26.21#ibcon#*after write, iclass 18, count 0 2006.173.09:21:26.21#ibcon#*before return 0, iclass 18, count 0 2006.173.09:21:26.21#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.09:21:26.21#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.09:21:26.21#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.09:21:26.21#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.09:21:26.21$vck44/vblo=5,709.99 2006.173.09:21:26.21#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.09:21:26.21#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.09:21:26.21#ibcon#ireg 17 cls_cnt 0 2006.173.09:21:26.21#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.09:21:26.21#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.09:21:26.21#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.09:21:26.21#ibcon#enter wrdev, iclass 20, count 0 2006.173.09:21:26.21#ibcon#first serial, iclass 20, count 0 2006.173.09:21:26.21#ibcon#enter sib2, iclass 20, count 0 2006.173.09:21:26.21#ibcon#flushed, iclass 20, count 0 2006.173.09:21:26.21#ibcon#about to write, iclass 20, count 0 2006.173.09:21:26.21#ibcon#wrote, iclass 20, count 0 2006.173.09:21:26.21#ibcon#about to read 3, iclass 20, count 0 2006.173.09:21:26.23#ibcon#read 3, iclass 20, count 0 2006.173.09:21:26.23#ibcon#about to read 4, iclass 20, count 0 2006.173.09:21:26.23#ibcon#read 4, iclass 20, count 0 2006.173.09:21:26.23#ibcon#about to read 5, iclass 20, count 0 2006.173.09:21:26.23#ibcon#read 5, iclass 20, count 0 2006.173.09:21:26.23#ibcon#about to read 6, iclass 20, count 0 2006.173.09:21:26.23#ibcon#read 6, iclass 20, count 0 2006.173.09:21:26.23#ibcon#end of sib2, iclass 20, count 0 2006.173.09:21:26.23#ibcon#*mode == 0, iclass 20, count 0 2006.173.09:21:26.23#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.09:21:26.23#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.09:21:26.23#ibcon#*before write, iclass 20, count 0 2006.173.09:21:26.23#ibcon#enter sib2, iclass 20, count 0 2006.173.09:21:26.23#ibcon#flushed, iclass 20, count 0 2006.173.09:21:26.23#ibcon#about to write, iclass 20, count 0 2006.173.09:21:26.23#ibcon#wrote, iclass 20, count 0 2006.173.09:21:26.23#ibcon#about to read 3, iclass 20, count 0 2006.173.09:21:26.27#ibcon#read 3, iclass 20, count 0 2006.173.09:21:26.27#ibcon#about to read 4, iclass 20, count 0 2006.173.09:21:26.27#ibcon#read 4, iclass 20, count 0 2006.173.09:21:26.27#ibcon#about to read 5, iclass 20, count 0 2006.173.09:21:26.27#ibcon#read 5, iclass 20, count 0 2006.173.09:21:26.27#ibcon#about to read 6, iclass 20, count 0 2006.173.09:21:26.27#ibcon#read 6, iclass 20, count 0 2006.173.09:21:26.27#ibcon#end of sib2, iclass 20, count 0 2006.173.09:21:26.27#ibcon#*after write, iclass 20, count 0 2006.173.09:21:26.27#ibcon#*before return 0, iclass 20, count 0 2006.173.09:21:26.27#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.09:21:26.27#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.09:21:26.27#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.09:21:26.27#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.09:21:26.27$vck44/vb=5,4 2006.173.09:21:26.27#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.09:21:26.27#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.09:21:26.27#ibcon#ireg 11 cls_cnt 2 2006.173.09:21:26.27#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.09:21:26.33#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.09:21:26.33#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.09:21:26.33#ibcon#enter wrdev, iclass 22, count 2 2006.173.09:21:26.33#ibcon#first serial, iclass 22, count 2 2006.173.09:21:26.33#ibcon#enter sib2, iclass 22, count 2 2006.173.09:21:26.33#ibcon#flushed, iclass 22, count 2 2006.173.09:21:26.33#ibcon#about to write, iclass 22, count 2 2006.173.09:21:26.33#ibcon#wrote, iclass 22, count 2 2006.173.09:21:26.33#ibcon#about to read 3, iclass 22, count 2 2006.173.09:21:26.35#ibcon#read 3, iclass 22, count 2 2006.173.09:21:26.35#ibcon#about to read 4, iclass 22, count 2 2006.173.09:21:26.35#ibcon#read 4, iclass 22, count 2 2006.173.09:21:26.35#ibcon#about to read 5, iclass 22, count 2 2006.173.09:21:26.35#ibcon#read 5, iclass 22, count 2 2006.173.09:21:26.35#ibcon#about to read 6, iclass 22, count 2 2006.173.09:21:26.35#ibcon#read 6, iclass 22, count 2 2006.173.09:21:26.35#ibcon#end of sib2, iclass 22, count 2 2006.173.09:21:26.35#ibcon#*mode == 0, iclass 22, count 2 2006.173.09:21:26.35#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.09:21:26.35#ibcon#[27=AT05-04\r\n] 2006.173.09:21:26.35#ibcon#*before write, iclass 22, count 2 2006.173.09:21:26.35#ibcon#enter sib2, iclass 22, count 2 2006.173.09:21:26.35#ibcon#flushed, iclass 22, count 2 2006.173.09:21:26.35#ibcon#about to write, iclass 22, count 2 2006.173.09:21:26.35#ibcon#wrote, iclass 22, count 2 2006.173.09:21:26.35#ibcon#about to read 3, iclass 22, count 2 2006.173.09:21:26.38#ibcon#read 3, iclass 22, count 2 2006.173.09:21:26.38#ibcon#about to read 4, iclass 22, count 2 2006.173.09:21:26.38#ibcon#read 4, iclass 22, count 2 2006.173.09:21:26.38#ibcon#about to read 5, iclass 22, count 2 2006.173.09:21:26.38#ibcon#read 5, iclass 22, count 2 2006.173.09:21:26.38#ibcon#about to read 6, iclass 22, count 2 2006.173.09:21:26.38#ibcon#read 6, iclass 22, count 2 2006.173.09:21:26.38#ibcon#end of sib2, iclass 22, count 2 2006.173.09:21:26.38#ibcon#*after write, iclass 22, count 2 2006.173.09:21:26.38#ibcon#*before return 0, iclass 22, count 2 2006.173.09:21:26.38#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.09:21:26.38#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.09:21:26.38#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.09:21:26.38#ibcon#ireg 7 cls_cnt 0 2006.173.09:21:26.38#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.09:21:26.50#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.09:21:26.50#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.09:21:26.50#ibcon#enter wrdev, iclass 22, count 0 2006.173.09:21:26.50#ibcon#first serial, iclass 22, count 0 2006.173.09:21:26.50#ibcon#enter sib2, iclass 22, count 0 2006.173.09:21:26.50#ibcon#flushed, iclass 22, count 0 2006.173.09:21:26.50#ibcon#about to write, iclass 22, count 0 2006.173.09:21:26.50#ibcon#wrote, iclass 22, count 0 2006.173.09:21:26.50#ibcon#about to read 3, iclass 22, count 0 2006.173.09:21:26.52#ibcon#read 3, iclass 22, count 0 2006.173.09:21:26.52#ibcon#about to read 4, iclass 22, count 0 2006.173.09:21:26.52#ibcon#read 4, iclass 22, count 0 2006.173.09:21:26.52#ibcon#about to read 5, iclass 22, count 0 2006.173.09:21:26.52#ibcon#read 5, iclass 22, count 0 2006.173.09:21:26.52#ibcon#about to read 6, iclass 22, count 0 2006.173.09:21:26.52#ibcon#read 6, iclass 22, count 0 2006.173.09:21:26.52#ibcon#end of sib2, iclass 22, count 0 2006.173.09:21:26.52#ibcon#*mode == 0, iclass 22, count 0 2006.173.09:21:26.52#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.09:21:26.52#ibcon#[27=USB\r\n] 2006.173.09:21:26.52#ibcon#*before write, iclass 22, count 0 2006.173.09:21:26.52#ibcon#enter sib2, iclass 22, count 0 2006.173.09:21:26.52#ibcon#flushed, iclass 22, count 0 2006.173.09:21:26.52#ibcon#about to write, iclass 22, count 0 2006.173.09:21:26.52#ibcon#wrote, iclass 22, count 0 2006.173.09:21:26.52#ibcon#about to read 3, iclass 22, count 0 2006.173.09:21:26.55#ibcon#read 3, iclass 22, count 0 2006.173.09:21:26.55#ibcon#about to read 4, iclass 22, count 0 2006.173.09:21:26.55#ibcon#read 4, iclass 22, count 0 2006.173.09:21:26.55#ibcon#about to read 5, iclass 22, count 0 2006.173.09:21:26.55#ibcon#read 5, iclass 22, count 0 2006.173.09:21:26.55#ibcon#about to read 6, iclass 22, count 0 2006.173.09:21:26.55#ibcon#read 6, iclass 22, count 0 2006.173.09:21:26.55#ibcon#end of sib2, iclass 22, count 0 2006.173.09:21:26.55#ibcon#*after write, iclass 22, count 0 2006.173.09:21:26.55#ibcon#*before return 0, iclass 22, count 0 2006.173.09:21:26.55#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.09:21:26.55#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.09:21:26.55#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.09:21:26.55#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.09:21:26.55$vck44/vblo=6,719.99 2006.173.09:21:26.55#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.09:21:26.55#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.09:21:26.55#ibcon#ireg 17 cls_cnt 0 2006.173.09:21:26.55#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.09:21:26.55#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.09:21:26.55#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.09:21:26.55#ibcon#enter wrdev, iclass 24, count 0 2006.173.09:21:26.55#ibcon#first serial, iclass 24, count 0 2006.173.09:21:26.55#ibcon#enter sib2, iclass 24, count 0 2006.173.09:21:26.55#ibcon#flushed, iclass 24, count 0 2006.173.09:21:26.55#ibcon#about to write, iclass 24, count 0 2006.173.09:21:26.55#ibcon#wrote, iclass 24, count 0 2006.173.09:21:26.55#ibcon#about to read 3, iclass 24, count 0 2006.173.09:21:26.57#ibcon#read 3, iclass 24, count 0 2006.173.09:21:26.57#ibcon#about to read 4, iclass 24, count 0 2006.173.09:21:26.57#ibcon#read 4, iclass 24, count 0 2006.173.09:21:26.57#ibcon#about to read 5, iclass 24, count 0 2006.173.09:21:26.57#ibcon#read 5, iclass 24, count 0 2006.173.09:21:26.57#ibcon#about to read 6, iclass 24, count 0 2006.173.09:21:26.57#ibcon#read 6, iclass 24, count 0 2006.173.09:21:26.57#ibcon#end of sib2, iclass 24, count 0 2006.173.09:21:26.57#ibcon#*mode == 0, iclass 24, count 0 2006.173.09:21:26.57#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.09:21:26.57#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.09:21:26.57#ibcon#*before write, iclass 24, count 0 2006.173.09:21:26.57#ibcon#enter sib2, iclass 24, count 0 2006.173.09:21:26.57#ibcon#flushed, iclass 24, count 0 2006.173.09:21:26.57#ibcon#about to write, iclass 24, count 0 2006.173.09:21:26.57#ibcon#wrote, iclass 24, count 0 2006.173.09:21:26.57#ibcon#about to read 3, iclass 24, count 0 2006.173.09:21:26.61#ibcon#read 3, iclass 24, count 0 2006.173.09:21:26.61#ibcon#about to read 4, iclass 24, count 0 2006.173.09:21:26.61#ibcon#read 4, iclass 24, count 0 2006.173.09:21:26.61#ibcon#about to read 5, iclass 24, count 0 2006.173.09:21:26.61#ibcon#read 5, iclass 24, count 0 2006.173.09:21:26.61#ibcon#about to read 6, iclass 24, count 0 2006.173.09:21:26.61#ibcon#read 6, iclass 24, count 0 2006.173.09:21:26.61#ibcon#end of sib2, iclass 24, count 0 2006.173.09:21:26.61#ibcon#*after write, iclass 24, count 0 2006.173.09:21:26.61#ibcon#*before return 0, iclass 24, count 0 2006.173.09:21:26.61#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.09:21:26.61#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.09:21:26.61#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.09:21:26.61#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.09:21:26.61$vck44/vb=6,4 2006.173.09:21:26.61#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.09:21:26.61#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.09:21:26.61#ibcon#ireg 11 cls_cnt 2 2006.173.09:21:26.61#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.09:21:26.67#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.09:21:26.67#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.09:21:26.67#ibcon#enter wrdev, iclass 26, count 2 2006.173.09:21:26.67#ibcon#first serial, iclass 26, count 2 2006.173.09:21:26.67#ibcon#enter sib2, iclass 26, count 2 2006.173.09:21:26.67#ibcon#flushed, iclass 26, count 2 2006.173.09:21:26.67#ibcon#about to write, iclass 26, count 2 2006.173.09:21:26.67#ibcon#wrote, iclass 26, count 2 2006.173.09:21:26.67#ibcon#about to read 3, iclass 26, count 2 2006.173.09:21:26.69#ibcon#read 3, iclass 26, count 2 2006.173.09:21:26.69#ibcon#about to read 4, iclass 26, count 2 2006.173.09:21:26.69#ibcon#read 4, iclass 26, count 2 2006.173.09:21:26.69#ibcon#about to read 5, iclass 26, count 2 2006.173.09:21:26.69#ibcon#read 5, iclass 26, count 2 2006.173.09:21:26.69#ibcon#about to read 6, iclass 26, count 2 2006.173.09:21:26.69#ibcon#read 6, iclass 26, count 2 2006.173.09:21:26.69#ibcon#end of sib2, iclass 26, count 2 2006.173.09:21:26.69#ibcon#*mode == 0, iclass 26, count 2 2006.173.09:21:26.69#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.09:21:26.69#ibcon#[27=AT06-04\r\n] 2006.173.09:21:26.69#ibcon#*before write, iclass 26, count 2 2006.173.09:21:26.69#ibcon#enter sib2, iclass 26, count 2 2006.173.09:21:26.69#ibcon#flushed, iclass 26, count 2 2006.173.09:21:26.69#ibcon#about to write, iclass 26, count 2 2006.173.09:21:26.69#ibcon#wrote, iclass 26, count 2 2006.173.09:21:26.69#ibcon#about to read 3, iclass 26, count 2 2006.173.09:21:26.72#ibcon#read 3, iclass 26, count 2 2006.173.09:21:26.72#ibcon#about to read 4, iclass 26, count 2 2006.173.09:21:26.72#ibcon#read 4, iclass 26, count 2 2006.173.09:21:26.72#ibcon#about to read 5, iclass 26, count 2 2006.173.09:21:26.72#ibcon#read 5, iclass 26, count 2 2006.173.09:21:26.72#ibcon#about to read 6, iclass 26, count 2 2006.173.09:21:26.72#ibcon#read 6, iclass 26, count 2 2006.173.09:21:26.72#ibcon#end of sib2, iclass 26, count 2 2006.173.09:21:26.72#ibcon#*after write, iclass 26, count 2 2006.173.09:21:26.72#ibcon#*before return 0, iclass 26, count 2 2006.173.09:21:26.72#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.09:21:26.72#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.09:21:26.72#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.09:21:26.72#ibcon#ireg 7 cls_cnt 0 2006.173.09:21:26.72#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.09:21:26.84#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.09:21:26.84#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.09:21:26.84#ibcon#enter wrdev, iclass 26, count 0 2006.173.09:21:26.84#ibcon#first serial, iclass 26, count 0 2006.173.09:21:26.84#ibcon#enter sib2, iclass 26, count 0 2006.173.09:21:26.84#ibcon#flushed, iclass 26, count 0 2006.173.09:21:26.84#ibcon#about to write, iclass 26, count 0 2006.173.09:21:26.84#ibcon#wrote, iclass 26, count 0 2006.173.09:21:26.84#ibcon#about to read 3, iclass 26, count 0 2006.173.09:21:26.86#ibcon#read 3, iclass 26, count 0 2006.173.09:21:26.86#ibcon#about to read 4, iclass 26, count 0 2006.173.09:21:26.86#ibcon#read 4, iclass 26, count 0 2006.173.09:21:26.86#ibcon#about to read 5, iclass 26, count 0 2006.173.09:21:26.86#ibcon#read 5, iclass 26, count 0 2006.173.09:21:26.86#ibcon#about to read 6, iclass 26, count 0 2006.173.09:21:26.86#ibcon#read 6, iclass 26, count 0 2006.173.09:21:26.86#ibcon#end of sib2, iclass 26, count 0 2006.173.09:21:26.86#ibcon#*mode == 0, iclass 26, count 0 2006.173.09:21:26.86#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.09:21:26.86#ibcon#[27=USB\r\n] 2006.173.09:21:26.86#ibcon#*before write, iclass 26, count 0 2006.173.09:21:26.86#ibcon#enter sib2, iclass 26, count 0 2006.173.09:21:26.86#ibcon#flushed, iclass 26, count 0 2006.173.09:21:26.86#ibcon#about to write, iclass 26, count 0 2006.173.09:21:26.86#ibcon#wrote, iclass 26, count 0 2006.173.09:21:26.86#ibcon#about to read 3, iclass 26, count 0 2006.173.09:21:26.89#ibcon#read 3, iclass 26, count 0 2006.173.09:21:26.89#ibcon#about to read 4, iclass 26, count 0 2006.173.09:21:26.89#ibcon#read 4, iclass 26, count 0 2006.173.09:21:26.89#ibcon#about to read 5, iclass 26, count 0 2006.173.09:21:26.89#ibcon#read 5, iclass 26, count 0 2006.173.09:21:26.89#ibcon#about to read 6, iclass 26, count 0 2006.173.09:21:26.89#ibcon#read 6, iclass 26, count 0 2006.173.09:21:26.89#ibcon#end of sib2, iclass 26, count 0 2006.173.09:21:26.89#ibcon#*after write, iclass 26, count 0 2006.173.09:21:26.89#ibcon#*before return 0, iclass 26, count 0 2006.173.09:21:26.89#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.09:21:26.89#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.09:21:26.89#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.09:21:26.89#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.09:21:26.89$vck44/vblo=7,734.99 2006.173.09:21:26.89#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.09:21:26.89#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.09:21:26.89#ibcon#ireg 17 cls_cnt 0 2006.173.09:21:26.89#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.09:21:26.89#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.09:21:26.89#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.09:21:26.89#ibcon#enter wrdev, iclass 28, count 0 2006.173.09:21:26.89#ibcon#first serial, iclass 28, count 0 2006.173.09:21:26.89#ibcon#enter sib2, iclass 28, count 0 2006.173.09:21:26.89#ibcon#flushed, iclass 28, count 0 2006.173.09:21:26.89#ibcon#about to write, iclass 28, count 0 2006.173.09:21:26.89#ibcon#wrote, iclass 28, count 0 2006.173.09:21:26.89#ibcon#about to read 3, iclass 28, count 0 2006.173.09:21:26.91#ibcon#read 3, iclass 28, count 0 2006.173.09:21:26.91#ibcon#about to read 4, iclass 28, count 0 2006.173.09:21:26.91#ibcon#read 4, iclass 28, count 0 2006.173.09:21:26.91#ibcon#about to read 5, iclass 28, count 0 2006.173.09:21:26.91#ibcon#read 5, iclass 28, count 0 2006.173.09:21:26.91#ibcon#about to read 6, iclass 28, count 0 2006.173.09:21:26.91#ibcon#read 6, iclass 28, count 0 2006.173.09:21:26.91#ibcon#end of sib2, iclass 28, count 0 2006.173.09:21:26.91#ibcon#*mode == 0, iclass 28, count 0 2006.173.09:21:26.91#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.09:21:26.91#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.09:21:26.91#ibcon#*before write, iclass 28, count 0 2006.173.09:21:26.91#ibcon#enter sib2, iclass 28, count 0 2006.173.09:21:26.91#ibcon#flushed, iclass 28, count 0 2006.173.09:21:26.91#ibcon#about to write, iclass 28, count 0 2006.173.09:21:26.91#ibcon#wrote, iclass 28, count 0 2006.173.09:21:26.91#ibcon#about to read 3, iclass 28, count 0 2006.173.09:21:26.95#ibcon#read 3, iclass 28, count 0 2006.173.09:21:26.95#ibcon#about to read 4, iclass 28, count 0 2006.173.09:21:26.95#ibcon#read 4, iclass 28, count 0 2006.173.09:21:26.95#ibcon#about to read 5, iclass 28, count 0 2006.173.09:21:26.95#ibcon#read 5, iclass 28, count 0 2006.173.09:21:26.95#ibcon#about to read 6, iclass 28, count 0 2006.173.09:21:26.95#ibcon#read 6, iclass 28, count 0 2006.173.09:21:26.95#ibcon#end of sib2, iclass 28, count 0 2006.173.09:21:26.95#ibcon#*after write, iclass 28, count 0 2006.173.09:21:26.95#ibcon#*before return 0, iclass 28, count 0 2006.173.09:21:26.95#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.09:21:26.95#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.09:21:26.95#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.09:21:26.95#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.09:21:26.95$vck44/vb=7,4 2006.173.09:21:26.95#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.09:21:26.95#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.09:21:26.95#ibcon#ireg 11 cls_cnt 2 2006.173.09:21:26.95#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.09:21:27.01#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.09:21:27.01#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.09:21:27.01#ibcon#enter wrdev, iclass 30, count 2 2006.173.09:21:27.01#ibcon#first serial, iclass 30, count 2 2006.173.09:21:27.01#ibcon#enter sib2, iclass 30, count 2 2006.173.09:21:27.01#ibcon#flushed, iclass 30, count 2 2006.173.09:21:27.01#ibcon#about to write, iclass 30, count 2 2006.173.09:21:27.01#ibcon#wrote, iclass 30, count 2 2006.173.09:21:27.01#ibcon#about to read 3, iclass 30, count 2 2006.173.09:21:27.03#ibcon#read 3, iclass 30, count 2 2006.173.09:21:27.03#ibcon#about to read 4, iclass 30, count 2 2006.173.09:21:27.03#ibcon#read 4, iclass 30, count 2 2006.173.09:21:27.03#ibcon#about to read 5, iclass 30, count 2 2006.173.09:21:27.03#ibcon#read 5, iclass 30, count 2 2006.173.09:21:27.03#ibcon#about to read 6, iclass 30, count 2 2006.173.09:21:27.03#ibcon#read 6, iclass 30, count 2 2006.173.09:21:27.03#ibcon#end of sib2, iclass 30, count 2 2006.173.09:21:27.03#ibcon#*mode == 0, iclass 30, count 2 2006.173.09:21:27.03#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.09:21:27.03#ibcon#[27=AT07-04\r\n] 2006.173.09:21:27.03#ibcon#*before write, iclass 30, count 2 2006.173.09:21:27.03#ibcon#enter sib2, iclass 30, count 2 2006.173.09:21:27.03#ibcon#flushed, iclass 30, count 2 2006.173.09:21:27.03#ibcon#about to write, iclass 30, count 2 2006.173.09:21:27.03#ibcon#wrote, iclass 30, count 2 2006.173.09:21:27.03#ibcon#about to read 3, iclass 30, count 2 2006.173.09:21:27.06#ibcon#read 3, iclass 30, count 2 2006.173.09:21:27.06#ibcon#about to read 4, iclass 30, count 2 2006.173.09:21:27.06#ibcon#read 4, iclass 30, count 2 2006.173.09:21:27.06#ibcon#about to read 5, iclass 30, count 2 2006.173.09:21:27.06#ibcon#read 5, iclass 30, count 2 2006.173.09:21:27.06#ibcon#about to read 6, iclass 30, count 2 2006.173.09:21:27.06#ibcon#read 6, iclass 30, count 2 2006.173.09:21:27.06#ibcon#end of sib2, iclass 30, count 2 2006.173.09:21:27.06#ibcon#*after write, iclass 30, count 2 2006.173.09:21:27.06#ibcon#*before return 0, iclass 30, count 2 2006.173.09:21:27.06#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.09:21:27.06#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.09:21:27.06#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.09:21:27.06#ibcon#ireg 7 cls_cnt 0 2006.173.09:21:27.06#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.09:21:27.18#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.09:21:27.18#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.09:21:27.18#ibcon#enter wrdev, iclass 30, count 0 2006.173.09:21:27.18#ibcon#first serial, iclass 30, count 0 2006.173.09:21:27.18#ibcon#enter sib2, iclass 30, count 0 2006.173.09:21:27.18#ibcon#flushed, iclass 30, count 0 2006.173.09:21:27.18#ibcon#about to write, iclass 30, count 0 2006.173.09:21:27.18#ibcon#wrote, iclass 30, count 0 2006.173.09:21:27.18#ibcon#about to read 3, iclass 30, count 0 2006.173.09:21:27.20#ibcon#read 3, iclass 30, count 0 2006.173.09:21:27.20#ibcon#about to read 4, iclass 30, count 0 2006.173.09:21:27.20#ibcon#read 4, iclass 30, count 0 2006.173.09:21:27.20#ibcon#about to read 5, iclass 30, count 0 2006.173.09:21:27.20#ibcon#read 5, iclass 30, count 0 2006.173.09:21:27.20#ibcon#about to read 6, iclass 30, count 0 2006.173.09:21:27.20#ibcon#read 6, iclass 30, count 0 2006.173.09:21:27.20#ibcon#end of sib2, iclass 30, count 0 2006.173.09:21:27.20#ibcon#*mode == 0, iclass 30, count 0 2006.173.09:21:27.20#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.09:21:27.20#ibcon#[27=USB\r\n] 2006.173.09:21:27.20#ibcon#*before write, iclass 30, count 0 2006.173.09:21:27.20#ibcon#enter sib2, iclass 30, count 0 2006.173.09:21:27.20#ibcon#flushed, iclass 30, count 0 2006.173.09:21:27.20#ibcon#about to write, iclass 30, count 0 2006.173.09:21:27.20#ibcon#wrote, iclass 30, count 0 2006.173.09:21:27.20#ibcon#about to read 3, iclass 30, count 0 2006.173.09:21:27.23#ibcon#read 3, iclass 30, count 0 2006.173.09:21:27.23#ibcon#about to read 4, iclass 30, count 0 2006.173.09:21:27.23#ibcon#read 4, iclass 30, count 0 2006.173.09:21:27.23#ibcon#about to read 5, iclass 30, count 0 2006.173.09:21:27.23#ibcon#read 5, iclass 30, count 0 2006.173.09:21:27.23#ibcon#about to read 6, iclass 30, count 0 2006.173.09:21:27.23#ibcon#read 6, iclass 30, count 0 2006.173.09:21:27.23#ibcon#end of sib2, iclass 30, count 0 2006.173.09:21:27.23#ibcon#*after write, iclass 30, count 0 2006.173.09:21:27.23#ibcon#*before return 0, iclass 30, count 0 2006.173.09:21:27.23#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.09:21:27.23#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.09:21:27.23#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.09:21:27.23#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.09:21:27.23$vck44/vblo=8,744.99 2006.173.09:21:27.23#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.09:21:27.23#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.09:21:27.23#ibcon#ireg 17 cls_cnt 0 2006.173.09:21:27.23#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.09:21:27.23#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.09:21:27.23#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.09:21:27.23#ibcon#enter wrdev, iclass 32, count 0 2006.173.09:21:27.23#ibcon#first serial, iclass 32, count 0 2006.173.09:21:27.23#ibcon#enter sib2, iclass 32, count 0 2006.173.09:21:27.23#ibcon#flushed, iclass 32, count 0 2006.173.09:21:27.23#ibcon#about to write, iclass 32, count 0 2006.173.09:21:27.23#ibcon#wrote, iclass 32, count 0 2006.173.09:21:27.23#ibcon#about to read 3, iclass 32, count 0 2006.173.09:21:27.25#ibcon#read 3, iclass 32, count 0 2006.173.09:21:27.25#ibcon#about to read 4, iclass 32, count 0 2006.173.09:21:27.25#ibcon#read 4, iclass 32, count 0 2006.173.09:21:27.25#ibcon#about to read 5, iclass 32, count 0 2006.173.09:21:27.25#ibcon#read 5, iclass 32, count 0 2006.173.09:21:27.25#ibcon#about to read 6, iclass 32, count 0 2006.173.09:21:27.25#ibcon#read 6, iclass 32, count 0 2006.173.09:21:27.25#ibcon#end of sib2, iclass 32, count 0 2006.173.09:21:27.25#ibcon#*mode == 0, iclass 32, count 0 2006.173.09:21:27.25#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.09:21:27.25#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.09:21:27.25#ibcon#*before write, iclass 32, count 0 2006.173.09:21:27.25#ibcon#enter sib2, iclass 32, count 0 2006.173.09:21:27.25#ibcon#flushed, iclass 32, count 0 2006.173.09:21:27.25#ibcon#about to write, iclass 32, count 0 2006.173.09:21:27.25#ibcon#wrote, iclass 32, count 0 2006.173.09:21:27.25#ibcon#about to read 3, iclass 32, count 0 2006.173.09:21:27.29#ibcon#read 3, iclass 32, count 0 2006.173.09:21:27.29#ibcon#about to read 4, iclass 32, count 0 2006.173.09:21:27.29#ibcon#read 4, iclass 32, count 0 2006.173.09:21:27.29#ibcon#about to read 5, iclass 32, count 0 2006.173.09:21:27.29#ibcon#read 5, iclass 32, count 0 2006.173.09:21:27.29#ibcon#about to read 6, iclass 32, count 0 2006.173.09:21:27.29#ibcon#read 6, iclass 32, count 0 2006.173.09:21:27.29#ibcon#end of sib2, iclass 32, count 0 2006.173.09:21:27.29#ibcon#*after write, iclass 32, count 0 2006.173.09:21:27.29#ibcon#*before return 0, iclass 32, count 0 2006.173.09:21:27.29#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.09:21:27.29#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.09:21:27.29#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.09:21:27.29#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.09:21:27.29$vck44/vb=8,4 2006.173.09:21:27.29#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.09:21:27.29#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.09:21:27.29#ibcon#ireg 11 cls_cnt 2 2006.173.09:21:27.29#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.09:21:27.35#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.09:21:27.35#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.09:21:27.35#ibcon#enter wrdev, iclass 34, count 2 2006.173.09:21:27.35#ibcon#first serial, iclass 34, count 2 2006.173.09:21:27.35#ibcon#enter sib2, iclass 34, count 2 2006.173.09:21:27.35#ibcon#flushed, iclass 34, count 2 2006.173.09:21:27.35#ibcon#about to write, iclass 34, count 2 2006.173.09:21:27.35#ibcon#wrote, iclass 34, count 2 2006.173.09:21:27.35#ibcon#about to read 3, iclass 34, count 2 2006.173.09:21:27.37#ibcon#read 3, iclass 34, count 2 2006.173.09:21:27.37#ibcon#about to read 4, iclass 34, count 2 2006.173.09:21:27.37#ibcon#read 4, iclass 34, count 2 2006.173.09:21:27.37#ibcon#about to read 5, iclass 34, count 2 2006.173.09:21:27.37#ibcon#read 5, iclass 34, count 2 2006.173.09:21:27.37#ibcon#about to read 6, iclass 34, count 2 2006.173.09:21:27.37#ibcon#read 6, iclass 34, count 2 2006.173.09:21:27.37#ibcon#end of sib2, iclass 34, count 2 2006.173.09:21:27.37#ibcon#*mode == 0, iclass 34, count 2 2006.173.09:21:27.37#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.09:21:27.37#ibcon#[27=AT08-04\r\n] 2006.173.09:21:27.37#ibcon#*before write, iclass 34, count 2 2006.173.09:21:27.37#ibcon#enter sib2, iclass 34, count 2 2006.173.09:21:27.37#ibcon#flushed, iclass 34, count 2 2006.173.09:21:27.37#ibcon#about to write, iclass 34, count 2 2006.173.09:21:27.37#ibcon#wrote, iclass 34, count 2 2006.173.09:21:27.37#ibcon#about to read 3, iclass 34, count 2 2006.173.09:21:27.40#ibcon#read 3, iclass 34, count 2 2006.173.09:21:27.40#ibcon#about to read 4, iclass 34, count 2 2006.173.09:21:27.40#ibcon#read 4, iclass 34, count 2 2006.173.09:21:27.40#ibcon#about to read 5, iclass 34, count 2 2006.173.09:21:27.40#ibcon#read 5, iclass 34, count 2 2006.173.09:21:27.40#ibcon#about to read 6, iclass 34, count 2 2006.173.09:21:27.40#ibcon#read 6, iclass 34, count 2 2006.173.09:21:27.40#ibcon#end of sib2, iclass 34, count 2 2006.173.09:21:27.40#ibcon#*after write, iclass 34, count 2 2006.173.09:21:27.40#ibcon#*before return 0, iclass 34, count 2 2006.173.09:21:27.40#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.09:21:27.40#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.09:21:27.40#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.09:21:27.40#ibcon#ireg 7 cls_cnt 0 2006.173.09:21:27.40#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.09:21:27.52#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.09:21:27.52#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.09:21:27.52#ibcon#enter wrdev, iclass 34, count 0 2006.173.09:21:27.52#ibcon#first serial, iclass 34, count 0 2006.173.09:21:27.52#ibcon#enter sib2, iclass 34, count 0 2006.173.09:21:27.52#ibcon#flushed, iclass 34, count 0 2006.173.09:21:27.52#ibcon#about to write, iclass 34, count 0 2006.173.09:21:27.52#ibcon#wrote, iclass 34, count 0 2006.173.09:21:27.52#ibcon#about to read 3, iclass 34, count 0 2006.173.09:21:27.54#ibcon#read 3, iclass 34, count 0 2006.173.09:21:27.54#ibcon#about to read 4, iclass 34, count 0 2006.173.09:21:27.54#ibcon#read 4, iclass 34, count 0 2006.173.09:21:27.54#ibcon#about to read 5, iclass 34, count 0 2006.173.09:21:27.54#ibcon#read 5, iclass 34, count 0 2006.173.09:21:27.54#ibcon#about to read 6, iclass 34, count 0 2006.173.09:21:27.54#ibcon#read 6, iclass 34, count 0 2006.173.09:21:27.54#ibcon#end of sib2, iclass 34, count 0 2006.173.09:21:27.54#ibcon#*mode == 0, iclass 34, count 0 2006.173.09:21:27.54#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.09:21:27.54#ibcon#[27=USB\r\n] 2006.173.09:21:27.54#ibcon#*before write, iclass 34, count 0 2006.173.09:21:27.54#ibcon#enter sib2, iclass 34, count 0 2006.173.09:21:27.54#ibcon#flushed, iclass 34, count 0 2006.173.09:21:27.54#ibcon#about to write, iclass 34, count 0 2006.173.09:21:27.54#ibcon#wrote, iclass 34, count 0 2006.173.09:21:27.54#ibcon#about to read 3, iclass 34, count 0 2006.173.09:21:27.57#ibcon#read 3, iclass 34, count 0 2006.173.09:21:27.57#ibcon#about to read 4, iclass 34, count 0 2006.173.09:21:27.57#ibcon#read 4, iclass 34, count 0 2006.173.09:21:27.57#ibcon#about to read 5, iclass 34, count 0 2006.173.09:21:27.57#ibcon#read 5, iclass 34, count 0 2006.173.09:21:27.57#ibcon#about to read 6, iclass 34, count 0 2006.173.09:21:27.57#ibcon#read 6, iclass 34, count 0 2006.173.09:21:27.57#ibcon#end of sib2, iclass 34, count 0 2006.173.09:21:27.57#ibcon#*after write, iclass 34, count 0 2006.173.09:21:27.57#ibcon#*before return 0, iclass 34, count 0 2006.173.09:21:27.57#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.09:21:27.57#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.09:21:27.57#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.09:21:27.57#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.09:21:27.57$vck44/vabw=wide 2006.173.09:21:27.57#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.09:21:27.57#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.09:21:27.57#ibcon#ireg 8 cls_cnt 0 2006.173.09:21:27.57#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.09:21:27.57#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.09:21:27.57#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.09:21:27.57#ibcon#enter wrdev, iclass 36, count 0 2006.173.09:21:27.57#ibcon#first serial, iclass 36, count 0 2006.173.09:21:27.57#ibcon#enter sib2, iclass 36, count 0 2006.173.09:21:27.57#ibcon#flushed, iclass 36, count 0 2006.173.09:21:27.57#ibcon#about to write, iclass 36, count 0 2006.173.09:21:27.57#ibcon#wrote, iclass 36, count 0 2006.173.09:21:27.57#ibcon#about to read 3, iclass 36, count 0 2006.173.09:21:27.59#ibcon#read 3, iclass 36, count 0 2006.173.09:21:27.59#ibcon#about to read 4, iclass 36, count 0 2006.173.09:21:27.59#ibcon#read 4, iclass 36, count 0 2006.173.09:21:27.59#ibcon#about to read 5, iclass 36, count 0 2006.173.09:21:27.59#ibcon#read 5, iclass 36, count 0 2006.173.09:21:27.59#ibcon#about to read 6, iclass 36, count 0 2006.173.09:21:27.59#ibcon#read 6, iclass 36, count 0 2006.173.09:21:27.59#ibcon#end of sib2, iclass 36, count 0 2006.173.09:21:27.59#ibcon#*mode == 0, iclass 36, count 0 2006.173.09:21:27.59#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.09:21:27.59#ibcon#[25=BW32\r\n] 2006.173.09:21:27.59#ibcon#*before write, iclass 36, count 0 2006.173.09:21:27.59#ibcon#enter sib2, iclass 36, count 0 2006.173.09:21:27.59#ibcon#flushed, iclass 36, count 0 2006.173.09:21:27.59#ibcon#about to write, iclass 36, count 0 2006.173.09:21:27.59#ibcon#wrote, iclass 36, count 0 2006.173.09:21:27.59#ibcon#about to read 3, iclass 36, count 0 2006.173.09:21:27.62#ibcon#read 3, iclass 36, count 0 2006.173.09:21:27.62#ibcon#about to read 4, iclass 36, count 0 2006.173.09:21:27.62#ibcon#read 4, iclass 36, count 0 2006.173.09:21:27.62#ibcon#about to read 5, iclass 36, count 0 2006.173.09:21:27.62#ibcon#read 5, iclass 36, count 0 2006.173.09:21:27.62#ibcon#about to read 6, iclass 36, count 0 2006.173.09:21:27.62#ibcon#read 6, iclass 36, count 0 2006.173.09:21:27.62#ibcon#end of sib2, iclass 36, count 0 2006.173.09:21:27.62#ibcon#*after write, iclass 36, count 0 2006.173.09:21:27.62#ibcon#*before return 0, iclass 36, count 0 2006.173.09:21:27.62#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.09:21:27.62#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.09:21:27.62#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.09:21:27.62#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.09:21:27.62$vck44/vbbw=wide 2006.173.09:21:27.62#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.09:21:27.62#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.09:21:27.62#ibcon#ireg 8 cls_cnt 0 2006.173.09:21:27.62#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.09:21:27.69#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.09:21:27.69#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.09:21:27.69#ibcon#enter wrdev, iclass 38, count 0 2006.173.09:21:27.69#ibcon#first serial, iclass 38, count 0 2006.173.09:21:27.69#ibcon#enter sib2, iclass 38, count 0 2006.173.09:21:27.69#ibcon#flushed, iclass 38, count 0 2006.173.09:21:27.69#ibcon#about to write, iclass 38, count 0 2006.173.09:21:27.69#ibcon#wrote, iclass 38, count 0 2006.173.09:21:27.69#ibcon#about to read 3, iclass 38, count 0 2006.173.09:21:27.71#ibcon#read 3, iclass 38, count 0 2006.173.09:21:27.71#ibcon#about to read 4, iclass 38, count 0 2006.173.09:21:27.71#ibcon#read 4, iclass 38, count 0 2006.173.09:21:27.71#ibcon#about to read 5, iclass 38, count 0 2006.173.09:21:27.71#ibcon#read 5, iclass 38, count 0 2006.173.09:21:27.71#ibcon#about to read 6, iclass 38, count 0 2006.173.09:21:27.71#ibcon#read 6, iclass 38, count 0 2006.173.09:21:27.71#ibcon#end of sib2, iclass 38, count 0 2006.173.09:21:27.71#ibcon#*mode == 0, iclass 38, count 0 2006.173.09:21:27.71#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.09:21:27.71#ibcon#[27=BW32\r\n] 2006.173.09:21:27.71#ibcon#*before write, iclass 38, count 0 2006.173.09:21:27.71#ibcon#enter sib2, iclass 38, count 0 2006.173.09:21:27.71#ibcon#flushed, iclass 38, count 0 2006.173.09:21:27.71#ibcon#about to write, iclass 38, count 0 2006.173.09:21:27.71#ibcon#wrote, iclass 38, count 0 2006.173.09:21:27.71#ibcon#about to read 3, iclass 38, count 0 2006.173.09:21:27.74#ibcon#read 3, iclass 38, count 0 2006.173.09:21:27.74#ibcon#about to read 4, iclass 38, count 0 2006.173.09:21:27.74#ibcon#read 4, iclass 38, count 0 2006.173.09:21:27.74#ibcon#about to read 5, iclass 38, count 0 2006.173.09:21:27.74#ibcon#read 5, iclass 38, count 0 2006.173.09:21:27.74#ibcon#about to read 6, iclass 38, count 0 2006.173.09:21:27.74#ibcon#read 6, iclass 38, count 0 2006.173.09:21:27.74#ibcon#end of sib2, iclass 38, count 0 2006.173.09:21:27.74#ibcon#*after write, iclass 38, count 0 2006.173.09:21:27.74#ibcon#*before return 0, iclass 38, count 0 2006.173.09:21:27.74#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.09:21:27.74#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.09:21:27.74#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.09:21:27.74#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.09:21:27.74$setupk4/ifdk4 2006.173.09:21:27.74$ifdk4/lo= 2006.173.09:21:27.74$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.09:21:27.74$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.09:21:27.74$ifdk4/patch= 2006.173.09:21:27.74$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.09:21:27.74$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.09:21:27.74$setupk4/!*+20s 2006.173.09:21:31.39#abcon#<5=/03 0.4 1.2 23.03 891004.3\r\n> 2006.173.09:21:31.41#abcon#{5=INTERFACE CLEAR} 2006.173.09:21:31.47#abcon#[5=S1D000X0/0*\r\n] 2006.173.09:21:41.56#abcon#<5=/03 0.5 1.2 23.03 891004.3\r\n> 2006.173.09:21:41.58#abcon#{5=INTERFACE CLEAR} 2006.173.09:21:41.64#abcon#[5=S1D000X0/0*\r\n] 2006.173.09:21:42.25$setupk4/"tpicd 2006.173.09:21:42.25$setupk4/echo=off 2006.173.09:21:42.25$setupk4/xlog=off 2006.173.09:21:42.25:!2006.173.09:27:58 2006.173.09:21:47.14#trakl#Source acquired 2006.173.09:21:48.14#flagr#flagr/antenna,acquired 2006.173.09:27:58.00:preob 2006.173.09:27:58.14/onsource/TRACKING 2006.173.09:27:58.14:!2006.173.09:28:08 2006.173.09:28:08.00:"tape 2006.173.09:28:08.00:"st=record 2006.173.09:28:08.00:data_valid=on 2006.173.09:28:08.00:midob 2006.173.09:28:09.14/onsource/TRACKING 2006.173.09:28:09.14/wx/23.00,1004.3,87 2006.173.09:28:09.33/cable/+6.5033E-03 2006.173.09:28:10.42/va/01,07,usb,yes,43,47 2006.173.09:28:10.42/va/02,06,usb,yes,43,44 2006.173.09:28:10.42/va/03,05,usb,yes,55,57 2006.173.09:28:10.42/va/04,06,usb,yes,44,47 2006.173.09:28:10.42/va/05,04,usb,yes,35,36 2006.173.09:28:10.42/va/06,03,usb,yes,49,49 2006.173.09:28:10.42/va/07,04,usb,yes,40,41 2006.173.09:28:10.42/va/08,04,usb,yes,34,41 2006.173.09:28:10.65/valo/01,524.99,yes,locked 2006.173.09:28:10.65/valo/02,534.99,yes,locked 2006.173.09:28:10.65/valo/03,564.99,yes,locked 2006.173.09:28:10.65/valo/04,624.99,yes,locked 2006.173.09:28:10.65/valo/05,734.99,yes,locked 2006.173.09:28:10.65/valo/06,814.99,yes,locked 2006.173.09:28:10.65/valo/07,864.99,yes,locked 2006.173.09:28:10.65/valo/08,884.99,yes,locked 2006.173.09:28:11.74/vb/01,04,usb,yes,30,31 2006.173.09:28:11.74/vb/02,04,usb,yes,33,36 2006.173.09:28:11.74/vb/03,04,usb,yes,30,33 2006.173.09:28:11.74/vb/04,04,usb,yes,34,33 2006.173.09:28:11.74/vb/05,04,usb,yes,27,29 2006.173.09:28:11.74/vb/06,04,usb,yes,32,28 2006.173.09:28:11.74/vb/07,04,usb,yes,31,31 2006.173.09:28:11.74/vb/08,04,usb,yes,29,32 2006.173.09:28:11.97/vblo/01,629.99,yes,locked 2006.173.09:28:11.97/vblo/02,634.99,yes,locked 2006.173.09:28:11.97/vblo/03,649.99,yes,locked 2006.173.09:28:11.97/vblo/04,679.99,yes,locked 2006.173.09:28:11.97/vblo/05,709.99,yes,locked 2006.173.09:28:11.97/vblo/06,719.99,yes,locked 2006.173.09:28:11.97/vblo/07,734.99,yes,locked 2006.173.09:28:11.97/vblo/08,744.99,yes,locked 2006.173.09:28:12.12/vabw/8 2006.173.09:28:12.27/vbbw/8 2006.173.09:28:12.36/xfe/off,on,14.5 2006.173.09:28:12.76/ifatt/23,28,28,28 2006.173.09:28:13.07/fmout-gps/S +4.00E-07 2006.173.09:28:13.11:!2006.173.09:28:48 2006.173.09:28:48.00:data_valid=off 2006.173.09:28:48.00:"et 2006.173.09:28:48.00:!+3s 2006.173.09:28:51.01:"tape 2006.173.09:28:51.01:postob 2006.173.09:28:51.12/cable/+6.5008E-03 2006.173.09:28:51.12/wx/22.99,1004.3,87 2006.173.09:28:52.07/fmout-gps/S +4.01E-07 2006.173.09:28:52.07:scan_name=173-0934,jd0606,784 2006.173.09:28:52.07:source=1749+096,175132.82,093900.7,2000.0,cw 2006.173.09:28:53.14#flagr#flagr/antenna,new-source 2006.173.09:28:53.14:checkk5 2006.173.09:28:53.51/chk_autoobs//k5ts1/ autoobs is running! 2006.173.09:28:53.90/chk_autoobs//k5ts2/ autoobs is running! 2006.173.09:28:54.32/chk_autoobs//k5ts3/ autoobs is running! 2006.173.09:28:54.72/chk_autoobs//k5ts4/ autoobs is running! 2006.173.09:28:55.10/chk_obsdata//k5ts1/T1730928??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.173.09:28:55.51/chk_obsdata//k5ts2/T1730928??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.173.09:28:55.93/chk_obsdata//k5ts3/T1730928??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.173.09:28:56.33/chk_obsdata//k5ts4/T1730928??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.173.09:28:57.05/k5log//k5ts1_log_newline 2006.173.09:28:57.77/k5log//k5ts2_log_newline 2006.173.09:28:58.49/k5log//k5ts3_log_newline 2006.173.09:28:59.20/k5log//k5ts4_log_newline 2006.173.09:28:59.23/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.09:28:59.23:setupk4=1 2006.173.09:28:59.23$setupk4/echo=on 2006.173.09:28:59.23$setupk4/pcalon 2006.173.09:28:59.23$pcalon/"no phase cal control is implemented here 2006.173.09:28:59.23$setupk4/"tpicd=stop 2006.173.09:28:59.23$setupk4/"rec=synch_on 2006.173.09:28:59.23$setupk4/"rec_mode=128 2006.173.09:28:59.23$setupk4/!* 2006.173.09:28:59.23$setupk4/recpk4 2006.173.09:28:59.23$recpk4/recpatch= 2006.173.09:28:59.24$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.09:28:59.24$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.09:28:59.24$setupk4/vck44 2006.173.09:28:59.24$vck44/valo=1,524.99 2006.173.09:28:59.24#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.09:28:59.24#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.09:28:59.24#ibcon#ireg 17 cls_cnt 0 2006.173.09:28:59.24#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.09:28:59.24#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.09:28:59.24#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.09:28:59.24#ibcon#enter wrdev, iclass 5, count 0 2006.173.09:28:59.24#ibcon#first serial, iclass 5, count 0 2006.173.09:28:59.24#ibcon#enter sib2, iclass 5, count 0 2006.173.09:28:59.24#ibcon#flushed, iclass 5, count 0 2006.173.09:28:59.24#ibcon#about to write, iclass 5, count 0 2006.173.09:28:59.24#ibcon#wrote, iclass 5, count 0 2006.173.09:28:59.24#ibcon#about to read 3, iclass 5, count 0 2006.173.09:28:59.25#ibcon#read 3, iclass 5, count 0 2006.173.09:28:59.25#ibcon#about to read 4, iclass 5, count 0 2006.173.09:28:59.25#ibcon#read 4, iclass 5, count 0 2006.173.09:28:59.25#ibcon#about to read 5, iclass 5, count 0 2006.173.09:28:59.25#ibcon#read 5, iclass 5, count 0 2006.173.09:28:59.25#ibcon#about to read 6, iclass 5, count 0 2006.173.09:28:59.25#ibcon#read 6, iclass 5, count 0 2006.173.09:28:59.25#ibcon#end of sib2, iclass 5, count 0 2006.173.09:28:59.25#ibcon#*mode == 0, iclass 5, count 0 2006.173.09:28:59.25#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.09:28:59.25#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.09:28:59.25#ibcon#*before write, iclass 5, count 0 2006.173.09:28:59.25#ibcon#enter sib2, iclass 5, count 0 2006.173.09:28:59.25#ibcon#flushed, iclass 5, count 0 2006.173.09:28:59.25#ibcon#about to write, iclass 5, count 0 2006.173.09:28:59.25#ibcon#wrote, iclass 5, count 0 2006.173.09:28:59.25#ibcon#about to read 3, iclass 5, count 0 2006.173.09:28:59.30#ibcon#read 3, iclass 5, count 0 2006.173.09:28:59.30#ibcon#about to read 4, iclass 5, count 0 2006.173.09:28:59.30#ibcon#read 4, iclass 5, count 0 2006.173.09:28:59.30#ibcon#about to read 5, iclass 5, count 0 2006.173.09:28:59.30#ibcon#read 5, iclass 5, count 0 2006.173.09:28:59.30#ibcon#about to read 6, iclass 5, count 0 2006.173.09:28:59.30#ibcon#read 6, iclass 5, count 0 2006.173.09:28:59.30#ibcon#end of sib2, iclass 5, count 0 2006.173.09:28:59.30#ibcon#*after write, iclass 5, count 0 2006.173.09:28:59.30#ibcon#*before return 0, iclass 5, count 0 2006.173.09:28:59.30#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.09:28:59.30#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.09:28:59.30#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.09:28:59.30#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.09:28:59.30$vck44/va=1,7 2006.173.09:28:59.30#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.173.09:28:59.30#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.173.09:28:59.30#ibcon#ireg 11 cls_cnt 2 2006.173.09:28:59.30#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.09:28:59.30#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.09:28:59.30#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.09:28:59.30#ibcon#enter wrdev, iclass 7, count 2 2006.173.09:28:59.30#ibcon#first serial, iclass 7, count 2 2006.173.09:28:59.30#ibcon#enter sib2, iclass 7, count 2 2006.173.09:28:59.30#ibcon#flushed, iclass 7, count 2 2006.173.09:28:59.30#ibcon#about to write, iclass 7, count 2 2006.173.09:28:59.30#ibcon#wrote, iclass 7, count 2 2006.173.09:28:59.30#ibcon#about to read 3, iclass 7, count 2 2006.173.09:28:59.32#ibcon#read 3, iclass 7, count 2 2006.173.09:28:59.32#ibcon#about to read 4, iclass 7, count 2 2006.173.09:28:59.32#ibcon#read 4, iclass 7, count 2 2006.173.09:28:59.32#ibcon#about to read 5, iclass 7, count 2 2006.173.09:28:59.32#ibcon#read 5, iclass 7, count 2 2006.173.09:28:59.32#ibcon#about to read 6, iclass 7, count 2 2006.173.09:28:59.32#ibcon#read 6, iclass 7, count 2 2006.173.09:28:59.32#ibcon#end of sib2, iclass 7, count 2 2006.173.09:28:59.32#ibcon#*mode == 0, iclass 7, count 2 2006.173.09:28:59.32#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.173.09:28:59.32#ibcon#[25=AT01-07\r\n] 2006.173.09:28:59.32#ibcon#*before write, iclass 7, count 2 2006.173.09:28:59.32#ibcon#enter sib2, iclass 7, count 2 2006.173.09:28:59.32#ibcon#flushed, iclass 7, count 2 2006.173.09:28:59.32#ibcon#about to write, iclass 7, count 2 2006.173.09:28:59.32#ibcon#wrote, iclass 7, count 2 2006.173.09:28:59.32#ibcon#about to read 3, iclass 7, count 2 2006.173.09:28:59.35#ibcon#read 3, iclass 7, count 2 2006.173.09:28:59.35#ibcon#about to read 4, iclass 7, count 2 2006.173.09:28:59.35#ibcon#read 4, iclass 7, count 2 2006.173.09:28:59.35#ibcon#about to read 5, iclass 7, count 2 2006.173.09:28:59.35#ibcon#read 5, iclass 7, count 2 2006.173.09:28:59.35#ibcon#about to read 6, iclass 7, count 2 2006.173.09:28:59.35#ibcon#read 6, iclass 7, count 2 2006.173.09:28:59.35#ibcon#end of sib2, iclass 7, count 2 2006.173.09:28:59.35#ibcon#*after write, iclass 7, count 2 2006.173.09:28:59.35#ibcon#*before return 0, iclass 7, count 2 2006.173.09:28:59.35#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.09:28:59.35#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.173.09:28:59.35#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.173.09:28:59.35#ibcon#ireg 7 cls_cnt 0 2006.173.09:28:59.35#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.09:28:59.47#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.09:28:59.47#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.09:28:59.47#ibcon#enter wrdev, iclass 7, count 0 2006.173.09:28:59.47#ibcon#first serial, iclass 7, count 0 2006.173.09:28:59.47#ibcon#enter sib2, iclass 7, count 0 2006.173.09:28:59.47#ibcon#flushed, iclass 7, count 0 2006.173.09:28:59.47#ibcon#about to write, iclass 7, count 0 2006.173.09:28:59.47#ibcon#wrote, iclass 7, count 0 2006.173.09:28:59.47#ibcon#about to read 3, iclass 7, count 0 2006.173.09:28:59.49#ibcon#read 3, iclass 7, count 0 2006.173.09:28:59.49#ibcon#about to read 4, iclass 7, count 0 2006.173.09:28:59.49#ibcon#read 4, iclass 7, count 0 2006.173.09:28:59.49#ibcon#about to read 5, iclass 7, count 0 2006.173.09:28:59.49#ibcon#read 5, iclass 7, count 0 2006.173.09:28:59.49#ibcon#about to read 6, iclass 7, count 0 2006.173.09:28:59.49#ibcon#read 6, iclass 7, count 0 2006.173.09:28:59.49#ibcon#end of sib2, iclass 7, count 0 2006.173.09:28:59.49#ibcon#*mode == 0, iclass 7, count 0 2006.173.09:28:59.49#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.09:28:59.49#ibcon#[25=USB\r\n] 2006.173.09:28:59.49#ibcon#*before write, iclass 7, count 0 2006.173.09:28:59.49#ibcon#enter sib2, iclass 7, count 0 2006.173.09:28:59.49#ibcon#flushed, iclass 7, count 0 2006.173.09:28:59.49#ibcon#about to write, iclass 7, count 0 2006.173.09:28:59.49#ibcon#wrote, iclass 7, count 0 2006.173.09:28:59.49#ibcon#about to read 3, iclass 7, count 0 2006.173.09:28:59.52#ibcon#read 3, iclass 7, count 0 2006.173.09:28:59.52#ibcon#about to read 4, iclass 7, count 0 2006.173.09:28:59.52#ibcon#read 4, iclass 7, count 0 2006.173.09:28:59.52#ibcon#about to read 5, iclass 7, count 0 2006.173.09:28:59.52#ibcon#read 5, iclass 7, count 0 2006.173.09:28:59.52#ibcon#about to read 6, iclass 7, count 0 2006.173.09:28:59.52#ibcon#read 6, iclass 7, count 0 2006.173.09:28:59.52#ibcon#end of sib2, iclass 7, count 0 2006.173.09:28:59.52#ibcon#*after write, iclass 7, count 0 2006.173.09:28:59.52#ibcon#*before return 0, iclass 7, count 0 2006.173.09:28:59.52#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.09:28:59.52#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.173.09:28:59.52#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.09:28:59.52#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.09:28:59.52$vck44/valo=2,534.99 2006.173.09:28:59.52#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.09:28:59.52#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.09:28:59.52#ibcon#ireg 17 cls_cnt 0 2006.173.09:28:59.52#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.09:28:59.52#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.09:28:59.52#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.09:28:59.52#ibcon#enter wrdev, iclass 11, count 0 2006.173.09:28:59.52#ibcon#first serial, iclass 11, count 0 2006.173.09:28:59.52#ibcon#enter sib2, iclass 11, count 0 2006.173.09:28:59.52#ibcon#flushed, iclass 11, count 0 2006.173.09:28:59.52#ibcon#about to write, iclass 11, count 0 2006.173.09:28:59.52#ibcon#wrote, iclass 11, count 0 2006.173.09:28:59.52#ibcon#about to read 3, iclass 11, count 0 2006.173.09:28:59.54#ibcon#read 3, iclass 11, count 0 2006.173.09:28:59.54#ibcon#about to read 4, iclass 11, count 0 2006.173.09:28:59.54#ibcon#read 4, iclass 11, count 0 2006.173.09:28:59.54#ibcon#about to read 5, iclass 11, count 0 2006.173.09:28:59.54#ibcon#read 5, iclass 11, count 0 2006.173.09:28:59.54#ibcon#about to read 6, iclass 11, count 0 2006.173.09:28:59.54#ibcon#read 6, iclass 11, count 0 2006.173.09:28:59.54#ibcon#end of sib2, iclass 11, count 0 2006.173.09:28:59.54#ibcon#*mode == 0, iclass 11, count 0 2006.173.09:28:59.54#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.09:28:59.54#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.09:28:59.54#ibcon#*before write, iclass 11, count 0 2006.173.09:28:59.54#ibcon#enter sib2, iclass 11, count 0 2006.173.09:28:59.54#ibcon#flushed, iclass 11, count 0 2006.173.09:28:59.54#ibcon#about to write, iclass 11, count 0 2006.173.09:28:59.54#ibcon#wrote, iclass 11, count 0 2006.173.09:28:59.54#ibcon#about to read 3, iclass 11, count 0 2006.173.09:28:59.58#ibcon#read 3, iclass 11, count 0 2006.173.09:28:59.58#ibcon#about to read 4, iclass 11, count 0 2006.173.09:28:59.58#ibcon#read 4, iclass 11, count 0 2006.173.09:28:59.58#ibcon#about to read 5, iclass 11, count 0 2006.173.09:28:59.58#ibcon#read 5, iclass 11, count 0 2006.173.09:28:59.58#ibcon#about to read 6, iclass 11, count 0 2006.173.09:28:59.58#ibcon#read 6, iclass 11, count 0 2006.173.09:28:59.58#ibcon#end of sib2, iclass 11, count 0 2006.173.09:28:59.58#ibcon#*after write, iclass 11, count 0 2006.173.09:28:59.58#ibcon#*before return 0, iclass 11, count 0 2006.173.09:28:59.58#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.09:28:59.58#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.09:28:59.58#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.09:28:59.58#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.09:28:59.58$vck44/va=2,6 2006.173.09:28:59.58#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.173.09:28:59.58#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.173.09:28:59.58#ibcon#ireg 11 cls_cnt 2 2006.173.09:28:59.58#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.09:28:59.64#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.09:28:59.64#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.09:28:59.64#ibcon#enter wrdev, iclass 13, count 2 2006.173.09:28:59.64#ibcon#first serial, iclass 13, count 2 2006.173.09:28:59.64#ibcon#enter sib2, iclass 13, count 2 2006.173.09:28:59.64#ibcon#flushed, iclass 13, count 2 2006.173.09:28:59.64#ibcon#about to write, iclass 13, count 2 2006.173.09:28:59.64#ibcon#wrote, iclass 13, count 2 2006.173.09:28:59.64#ibcon#about to read 3, iclass 13, count 2 2006.173.09:28:59.66#ibcon#read 3, iclass 13, count 2 2006.173.09:28:59.66#ibcon#about to read 4, iclass 13, count 2 2006.173.09:28:59.66#ibcon#read 4, iclass 13, count 2 2006.173.09:28:59.66#ibcon#about to read 5, iclass 13, count 2 2006.173.09:28:59.66#ibcon#read 5, iclass 13, count 2 2006.173.09:28:59.66#ibcon#about to read 6, iclass 13, count 2 2006.173.09:28:59.66#ibcon#read 6, iclass 13, count 2 2006.173.09:28:59.66#ibcon#end of sib2, iclass 13, count 2 2006.173.09:28:59.66#ibcon#*mode == 0, iclass 13, count 2 2006.173.09:28:59.66#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.173.09:28:59.66#ibcon#[25=AT02-06\r\n] 2006.173.09:28:59.66#ibcon#*before write, iclass 13, count 2 2006.173.09:28:59.66#ibcon#enter sib2, iclass 13, count 2 2006.173.09:28:59.66#ibcon#flushed, iclass 13, count 2 2006.173.09:28:59.66#ibcon#about to write, iclass 13, count 2 2006.173.09:28:59.66#ibcon#wrote, iclass 13, count 2 2006.173.09:28:59.66#ibcon#about to read 3, iclass 13, count 2 2006.173.09:28:59.69#ibcon#read 3, iclass 13, count 2 2006.173.09:28:59.69#ibcon#about to read 4, iclass 13, count 2 2006.173.09:28:59.69#ibcon#read 4, iclass 13, count 2 2006.173.09:28:59.69#ibcon#about to read 5, iclass 13, count 2 2006.173.09:28:59.69#ibcon#read 5, iclass 13, count 2 2006.173.09:28:59.69#ibcon#about to read 6, iclass 13, count 2 2006.173.09:28:59.69#ibcon#read 6, iclass 13, count 2 2006.173.09:28:59.69#ibcon#end of sib2, iclass 13, count 2 2006.173.09:28:59.69#ibcon#*after write, iclass 13, count 2 2006.173.09:28:59.69#ibcon#*before return 0, iclass 13, count 2 2006.173.09:28:59.69#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.09:28:59.69#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.173.09:28:59.69#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.173.09:28:59.69#ibcon#ireg 7 cls_cnt 0 2006.173.09:28:59.69#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.09:28:59.81#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.09:28:59.81#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.09:28:59.81#ibcon#enter wrdev, iclass 13, count 0 2006.173.09:28:59.81#ibcon#first serial, iclass 13, count 0 2006.173.09:28:59.81#ibcon#enter sib2, iclass 13, count 0 2006.173.09:28:59.81#ibcon#flushed, iclass 13, count 0 2006.173.09:28:59.81#ibcon#about to write, iclass 13, count 0 2006.173.09:28:59.81#ibcon#wrote, iclass 13, count 0 2006.173.09:28:59.81#ibcon#about to read 3, iclass 13, count 0 2006.173.09:28:59.83#ibcon#read 3, iclass 13, count 0 2006.173.09:28:59.83#ibcon#about to read 4, iclass 13, count 0 2006.173.09:28:59.83#ibcon#read 4, iclass 13, count 0 2006.173.09:28:59.83#ibcon#about to read 5, iclass 13, count 0 2006.173.09:28:59.83#ibcon#read 5, iclass 13, count 0 2006.173.09:28:59.83#ibcon#about to read 6, iclass 13, count 0 2006.173.09:28:59.83#ibcon#read 6, iclass 13, count 0 2006.173.09:28:59.83#ibcon#end of sib2, iclass 13, count 0 2006.173.09:28:59.83#ibcon#*mode == 0, iclass 13, count 0 2006.173.09:28:59.83#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.09:28:59.83#ibcon#[25=USB\r\n] 2006.173.09:28:59.83#ibcon#*before write, iclass 13, count 0 2006.173.09:28:59.83#ibcon#enter sib2, iclass 13, count 0 2006.173.09:28:59.83#ibcon#flushed, iclass 13, count 0 2006.173.09:28:59.83#ibcon#about to write, iclass 13, count 0 2006.173.09:28:59.83#ibcon#wrote, iclass 13, count 0 2006.173.09:28:59.83#ibcon#about to read 3, iclass 13, count 0 2006.173.09:28:59.86#ibcon#read 3, iclass 13, count 0 2006.173.09:28:59.86#ibcon#about to read 4, iclass 13, count 0 2006.173.09:28:59.86#ibcon#read 4, iclass 13, count 0 2006.173.09:28:59.86#ibcon#about to read 5, iclass 13, count 0 2006.173.09:28:59.86#ibcon#read 5, iclass 13, count 0 2006.173.09:28:59.86#ibcon#about to read 6, iclass 13, count 0 2006.173.09:28:59.86#ibcon#read 6, iclass 13, count 0 2006.173.09:28:59.86#ibcon#end of sib2, iclass 13, count 0 2006.173.09:28:59.86#ibcon#*after write, iclass 13, count 0 2006.173.09:28:59.86#ibcon#*before return 0, iclass 13, count 0 2006.173.09:28:59.86#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.09:28:59.86#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.173.09:28:59.86#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.09:28:59.86#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.09:28:59.86$vck44/valo=3,564.99 2006.173.09:28:59.86#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.09:28:59.86#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.09:28:59.86#ibcon#ireg 17 cls_cnt 0 2006.173.09:28:59.86#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.09:28:59.86#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.09:28:59.86#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.09:28:59.86#ibcon#enter wrdev, iclass 15, count 0 2006.173.09:28:59.86#ibcon#first serial, iclass 15, count 0 2006.173.09:28:59.86#ibcon#enter sib2, iclass 15, count 0 2006.173.09:28:59.86#ibcon#flushed, iclass 15, count 0 2006.173.09:28:59.86#ibcon#about to write, iclass 15, count 0 2006.173.09:28:59.86#ibcon#wrote, iclass 15, count 0 2006.173.09:28:59.86#ibcon#about to read 3, iclass 15, count 0 2006.173.09:28:59.88#ibcon#read 3, iclass 15, count 0 2006.173.09:28:59.88#ibcon#about to read 4, iclass 15, count 0 2006.173.09:28:59.88#ibcon#read 4, iclass 15, count 0 2006.173.09:28:59.88#ibcon#about to read 5, iclass 15, count 0 2006.173.09:28:59.88#ibcon#read 5, iclass 15, count 0 2006.173.09:28:59.88#ibcon#about to read 6, iclass 15, count 0 2006.173.09:28:59.88#ibcon#read 6, iclass 15, count 0 2006.173.09:28:59.88#ibcon#end of sib2, iclass 15, count 0 2006.173.09:28:59.88#ibcon#*mode == 0, iclass 15, count 0 2006.173.09:28:59.88#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.09:28:59.88#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.09:28:59.88#ibcon#*before write, iclass 15, count 0 2006.173.09:28:59.88#ibcon#enter sib2, iclass 15, count 0 2006.173.09:28:59.88#ibcon#flushed, iclass 15, count 0 2006.173.09:28:59.88#ibcon#about to write, iclass 15, count 0 2006.173.09:28:59.88#ibcon#wrote, iclass 15, count 0 2006.173.09:28:59.88#ibcon#about to read 3, iclass 15, count 0 2006.173.09:28:59.92#ibcon#read 3, iclass 15, count 0 2006.173.09:28:59.92#ibcon#about to read 4, iclass 15, count 0 2006.173.09:28:59.92#ibcon#read 4, iclass 15, count 0 2006.173.09:28:59.92#ibcon#about to read 5, iclass 15, count 0 2006.173.09:28:59.92#ibcon#read 5, iclass 15, count 0 2006.173.09:28:59.92#ibcon#about to read 6, iclass 15, count 0 2006.173.09:28:59.92#ibcon#read 6, iclass 15, count 0 2006.173.09:28:59.92#ibcon#end of sib2, iclass 15, count 0 2006.173.09:28:59.92#ibcon#*after write, iclass 15, count 0 2006.173.09:28:59.92#ibcon#*before return 0, iclass 15, count 0 2006.173.09:28:59.92#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.09:28:59.92#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.09:28:59.92#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.09:28:59.92#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.09:28:59.92$vck44/va=3,5 2006.173.09:28:59.92#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.09:28:59.92#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.09:28:59.92#ibcon#ireg 11 cls_cnt 2 2006.173.09:28:59.92#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.09:28:59.98#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.09:28:59.98#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.09:28:59.98#ibcon#enter wrdev, iclass 17, count 2 2006.173.09:28:59.98#ibcon#first serial, iclass 17, count 2 2006.173.09:28:59.98#ibcon#enter sib2, iclass 17, count 2 2006.173.09:28:59.98#ibcon#flushed, iclass 17, count 2 2006.173.09:28:59.98#ibcon#about to write, iclass 17, count 2 2006.173.09:28:59.98#ibcon#wrote, iclass 17, count 2 2006.173.09:28:59.98#ibcon#about to read 3, iclass 17, count 2 2006.173.09:29:00.00#ibcon#read 3, iclass 17, count 2 2006.173.09:29:00.00#ibcon#about to read 4, iclass 17, count 2 2006.173.09:29:00.00#ibcon#read 4, iclass 17, count 2 2006.173.09:29:00.00#ibcon#about to read 5, iclass 17, count 2 2006.173.09:29:00.00#ibcon#read 5, iclass 17, count 2 2006.173.09:29:00.00#ibcon#about to read 6, iclass 17, count 2 2006.173.09:29:00.00#ibcon#read 6, iclass 17, count 2 2006.173.09:29:00.00#ibcon#end of sib2, iclass 17, count 2 2006.173.09:29:00.00#ibcon#*mode == 0, iclass 17, count 2 2006.173.09:29:00.00#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.09:29:00.00#ibcon#[25=AT03-05\r\n] 2006.173.09:29:00.00#ibcon#*before write, iclass 17, count 2 2006.173.09:29:00.00#ibcon#enter sib2, iclass 17, count 2 2006.173.09:29:00.00#ibcon#flushed, iclass 17, count 2 2006.173.09:29:00.00#ibcon#about to write, iclass 17, count 2 2006.173.09:29:00.00#ibcon#wrote, iclass 17, count 2 2006.173.09:29:00.00#ibcon#about to read 3, iclass 17, count 2 2006.173.09:29:00.03#ibcon#read 3, iclass 17, count 2 2006.173.09:29:00.03#ibcon#about to read 4, iclass 17, count 2 2006.173.09:29:00.03#ibcon#read 4, iclass 17, count 2 2006.173.09:29:00.03#ibcon#about to read 5, iclass 17, count 2 2006.173.09:29:00.03#ibcon#read 5, iclass 17, count 2 2006.173.09:29:00.03#ibcon#about to read 6, iclass 17, count 2 2006.173.09:29:00.03#ibcon#read 6, iclass 17, count 2 2006.173.09:29:00.03#ibcon#end of sib2, iclass 17, count 2 2006.173.09:29:00.03#ibcon#*after write, iclass 17, count 2 2006.173.09:29:00.03#ibcon#*before return 0, iclass 17, count 2 2006.173.09:29:00.03#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.09:29:00.03#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.09:29:00.03#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.09:29:00.03#ibcon#ireg 7 cls_cnt 0 2006.173.09:29:00.03#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.09:29:00.15#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.09:29:00.15#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.09:29:00.15#ibcon#enter wrdev, iclass 17, count 0 2006.173.09:29:00.15#ibcon#first serial, iclass 17, count 0 2006.173.09:29:00.15#ibcon#enter sib2, iclass 17, count 0 2006.173.09:29:00.15#ibcon#flushed, iclass 17, count 0 2006.173.09:29:00.15#ibcon#about to write, iclass 17, count 0 2006.173.09:29:00.15#ibcon#wrote, iclass 17, count 0 2006.173.09:29:00.15#ibcon#about to read 3, iclass 17, count 0 2006.173.09:29:00.17#ibcon#read 3, iclass 17, count 0 2006.173.09:29:00.17#ibcon#about to read 4, iclass 17, count 0 2006.173.09:29:00.17#ibcon#read 4, iclass 17, count 0 2006.173.09:29:00.17#ibcon#about to read 5, iclass 17, count 0 2006.173.09:29:00.17#ibcon#read 5, iclass 17, count 0 2006.173.09:29:00.17#ibcon#about to read 6, iclass 17, count 0 2006.173.09:29:00.17#ibcon#read 6, iclass 17, count 0 2006.173.09:29:00.17#ibcon#end of sib2, iclass 17, count 0 2006.173.09:29:00.17#ibcon#*mode == 0, iclass 17, count 0 2006.173.09:29:00.17#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.09:29:00.17#ibcon#[25=USB\r\n] 2006.173.09:29:00.17#ibcon#*before write, iclass 17, count 0 2006.173.09:29:00.17#ibcon#enter sib2, iclass 17, count 0 2006.173.09:29:00.17#ibcon#flushed, iclass 17, count 0 2006.173.09:29:00.17#ibcon#about to write, iclass 17, count 0 2006.173.09:29:00.17#ibcon#wrote, iclass 17, count 0 2006.173.09:29:00.17#ibcon#about to read 3, iclass 17, count 0 2006.173.09:29:00.20#ibcon#read 3, iclass 17, count 0 2006.173.09:29:00.20#ibcon#about to read 4, iclass 17, count 0 2006.173.09:29:00.20#ibcon#read 4, iclass 17, count 0 2006.173.09:29:00.20#ibcon#about to read 5, iclass 17, count 0 2006.173.09:29:00.20#ibcon#read 5, iclass 17, count 0 2006.173.09:29:00.20#ibcon#about to read 6, iclass 17, count 0 2006.173.09:29:00.20#ibcon#read 6, iclass 17, count 0 2006.173.09:29:00.20#ibcon#end of sib2, iclass 17, count 0 2006.173.09:29:00.20#ibcon#*after write, iclass 17, count 0 2006.173.09:29:00.20#ibcon#*before return 0, iclass 17, count 0 2006.173.09:29:00.20#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.09:29:00.20#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.09:29:00.20#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.09:29:00.20#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.09:29:00.20$vck44/valo=4,624.99 2006.173.09:29:00.20#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.09:29:00.20#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.09:29:00.20#ibcon#ireg 17 cls_cnt 0 2006.173.09:29:00.20#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.09:29:00.20#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.09:29:00.20#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.09:29:00.20#ibcon#enter wrdev, iclass 19, count 0 2006.173.09:29:00.20#ibcon#first serial, iclass 19, count 0 2006.173.09:29:00.20#ibcon#enter sib2, iclass 19, count 0 2006.173.09:29:00.20#ibcon#flushed, iclass 19, count 0 2006.173.09:29:00.20#ibcon#about to write, iclass 19, count 0 2006.173.09:29:00.20#ibcon#wrote, iclass 19, count 0 2006.173.09:29:00.20#ibcon#about to read 3, iclass 19, count 0 2006.173.09:29:00.22#ibcon#read 3, iclass 19, count 0 2006.173.09:29:00.22#ibcon#about to read 4, iclass 19, count 0 2006.173.09:29:00.22#ibcon#read 4, iclass 19, count 0 2006.173.09:29:00.22#ibcon#about to read 5, iclass 19, count 0 2006.173.09:29:00.22#ibcon#read 5, iclass 19, count 0 2006.173.09:29:00.22#ibcon#about to read 6, iclass 19, count 0 2006.173.09:29:00.22#ibcon#read 6, iclass 19, count 0 2006.173.09:29:00.22#ibcon#end of sib2, iclass 19, count 0 2006.173.09:29:00.22#ibcon#*mode == 0, iclass 19, count 0 2006.173.09:29:00.22#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.09:29:00.22#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.09:29:00.22#ibcon#*before write, iclass 19, count 0 2006.173.09:29:00.22#ibcon#enter sib2, iclass 19, count 0 2006.173.09:29:00.22#ibcon#flushed, iclass 19, count 0 2006.173.09:29:00.22#ibcon#about to write, iclass 19, count 0 2006.173.09:29:00.22#ibcon#wrote, iclass 19, count 0 2006.173.09:29:00.22#ibcon#about to read 3, iclass 19, count 0 2006.173.09:29:00.26#ibcon#read 3, iclass 19, count 0 2006.173.09:29:00.26#ibcon#about to read 4, iclass 19, count 0 2006.173.09:29:00.26#ibcon#read 4, iclass 19, count 0 2006.173.09:29:00.26#ibcon#about to read 5, iclass 19, count 0 2006.173.09:29:00.26#ibcon#read 5, iclass 19, count 0 2006.173.09:29:00.26#ibcon#about to read 6, iclass 19, count 0 2006.173.09:29:00.26#ibcon#read 6, iclass 19, count 0 2006.173.09:29:00.26#ibcon#end of sib2, iclass 19, count 0 2006.173.09:29:00.26#ibcon#*after write, iclass 19, count 0 2006.173.09:29:00.26#ibcon#*before return 0, iclass 19, count 0 2006.173.09:29:00.26#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.09:29:00.26#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.09:29:00.26#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.09:29:00.26#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.09:29:00.26$vck44/va=4,6 2006.173.09:29:00.26#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.09:29:00.26#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.09:29:00.26#ibcon#ireg 11 cls_cnt 2 2006.173.09:29:00.26#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.09:29:00.32#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.09:29:00.32#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.09:29:00.32#ibcon#enter wrdev, iclass 21, count 2 2006.173.09:29:00.32#ibcon#first serial, iclass 21, count 2 2006.173.09:29:00.32#ibcon#enter sib2, iclass 21, count 2 2006.173.09:29:00.32#ibcon#flushed, iclass 21, count 2 2006.173.09:29:00.32#ibcon#about to write, iclass 21, count 2 2006.173.09:29:00.32#ibcon#wrote, iclass 21, count 2 2006.173.09:29:00.32#ibcon#about to read 3, iclass 21, count 2 2006.173.09:29:00.34#ibcon#read 3, iclass 21, count 2 2006.173.09:29:00.34#ibcon#about to read 4, iclass 21, count 2 2006.173.09:29:00.34#ibcon#read 4, iclass 21, count 2 2006.173.09:29:00.34#ibcon#about to read 5, iclass 21, count 2 2006.173.09:29:00.34#ibcon#read 5, iclass 21, count 2 2006.173.09:29:00.34#ibcon#about to read 6, iclass 21, count 2 2006.173.09:29:00.34#ibcon#read 6, iclass 21, count 2 2006.173.09:29:00.34#ibcon#end of sib2, iclass 21, count 2 2006.173.09:29:00.34#ibcon#*mode == 0, iclass 21, count 2 2006.173.09:29:00.34#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.09:29:00.34#ibcon#[25=AT04-06\r\n] 2006.173.09:29:00.34#ibcon#*before write, iclass 21, count 2 2006.173.09:29:00.34#ibcon#enter sib2, iclass 21, count 2 2006.173.09:29:00.34#ibcon#flushed, iclass 21, count 2 2006.173.09:29:00.34#ibcon#about to write, iclass 21, count 2 2006.173.09:29:00.34#ibcon#wrote, iclass 21, count 2 2006.173.09:29:00.34#ibcon#about to read 3, iclass 21, count 2 2006.173.09:29:00.37#ibcon#read 3, iclass 21, count 2 2006.173.09:29:00.37#ibcon#about to read 4, iclass 21, count 2 2006.173.09:29:00.37#ibcon#read 4, iclass 21, count 2 2006.173.09:29:00.37#ibcon#about to read 5, iclass 21, count 2 2006.173.09:29:00.37#ibcon#read 5, iclass 21, count 2 2006.173.09:29:00.37#ibcon#about to read 6, iclass 21, count 2 2006.173.09:29:00.37#ibcon#read 6, iclass 21, count 2 2006.173.09:29:00.37#ibcon#end of sib2, iclass 21, count 2 2006.173.09:29:00.37#ibcon#*after write, iclass 21, count 2 2006.173.09:29:00.37#ibcon#*before return 0, iclass 21, count 2 2006.173.09:29:00.37#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.09:29:00.37#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.09:29:00.37#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.09:29:00.37#ibcon#ireg 7 cls_cnt 0 2006.173.09:29:00.37#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.09:29:00.49#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.09:29:00.49#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.09:29:00.49#ibcon#enter wrdev, iclass 21, count 0 2006.173.09:29:00.49#ibcon#first serial, iclass 21, count 0 2006.173.09:29:00.49#ibcon#enter sib2, iclass 21, count 0 2006.173.09:29:00.49#ibcon#flushed, iclass 21, count 0 2006.173.09:29:00.49#ibcon#about to write, iclass 21, count 0 2006.173.09:29:00.49#ibcon#wrote, iclass 21, count 0 2006.173.09:29:00.49#ibcon#about to read 3, iclass 21, count 0 2006.173.09:29:00.51#ibcon#read 3, iclass 21, count 0 2006.173.09:29:00.51#ibcon#about to read 4, iclass 21, count 0 2006.173.09:29:00.51#ibcon#read 4, iclass 21, count 0 2006.173.09:29:00.51#ibcon#about to read 5, iclass 21, count 0 2006.173.09:29:00.51#ibcon#read 5, iclass 21, count 0 2006.173.09:29:00.51#ibcon#about to read 6, iclass 21, count 0 2006.173.09:29:00.51#ibcon#read 6, iclass 21, count 0 2006.173.09:29:00.51#ibcon#end of sib2, iclass 21, count 0 2006.173.09:29:00.51#ibcon#*mode == 0, iclass 21, count 0 2006.173.09:29:00.51#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.09:29:00.51#ibcon#[25=USB\r\n] 2006.173.09:29:00.51#ibcon#*before write, iclass 21, count 0 2006.173.09:29:00.51#ibcon#enter sib2, iclass 21, count 0 2006.173.09:29:00.51#ibcon#flushed, iclass 21, count 0 2006.173.09:29:00.51#ibcon#about to write, iclass 21, count 0 2006.173.09:29:00.51#ibcon#wrote, iclass 21, count 0 2006.173.09:29:00.51#ibcon#about to read 3, iclass 21, count 0 2006.173.09:29:00.54#ibcon#read 3, iclass 21, count 0 2006.173.09:29:00.54#ibcon#about to read 4, iclass 21, count 0 2006.173.09:29:00.54#ibcon#read 4, iclass 21, count 0 2006.173.09:29:00.54#ibcon#about to read 5, iclass 21, count 0 2006.173.09:29:00.54#ibcon#read 5, iclass 21, count 0 2006.173.09:29:00.54#ibcon#about to read 6, iclass 21, count 0 2006.173.09:29:00.54#ibcon#read 6, iclass 21, count 0 2006.173.09:29:00.54#ibcon#end of sib2, iclass 21, count 0 2006.173.09:29:00.54#ibcon#*after write, iclass 21, count 0 2006.173.09:29:00.54#ibcon#*before return 0, iclass 21, count 0 2006.173.09:29:00.54#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.09:29:00.54#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.09:29:00.54#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.09:29:00.54#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.09:29:00.54$vck44/valo=5,734.99 2006.173.09:29:00.54#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.09:29:00.54#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.09:29:00.54#ibcon#ireg 17 cls_cnt 0 2006.173.09:29:00.54#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.09:29:00.54#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.09:29:00.54#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.09:29:00.54#ibcon#enter wrdev, iclass 23, count 0 2006.173.09:29:00.54#ibcon#first serial, iclass 23, count 0 2006.173.09:29:00.54#ibcon#enter sib2, iclass 23, count 0 2006.173.09:29:00.54#ibcon#flushed, iclass 23, count 0 2006.173.09:29:00.54#ibcon#about to write, iclass 23, count 0 2006.173.09:29:00.54#ibcon#wrote, iclass 23, count 0 2006.173.09:29:00.54#ibcon#about to read 3, iclass 23, count 0 2006.173.09:29:00.56#ibcon#read 3, iclass 23, count 0 2006.173.09:29:00.56#ibcon#about to read 4, iclass 23, count 0 2006.173.09:29:00.56#ibcon#read 4, iclass 23, count 0 2006.173.09:29:00.56#ibcon#about to read 5, iclass 23, count 0 2006.173.09:29:00.56#ibcon#read 5, iclass 23, count 0 2006.173.09:29:00.56#ibcon#about to read 6, iclass 23, count 0 2006.173.09:29:00.56#ibcon#read 6, iclass 23, count 0 2006.173.09:29:00.56#ibcon#end of sib2, iclass 23, count 0 2006.173.09:29:00.56#ibcon#*mode == 0, iclass 23, count 0 2006.173.09:29:00.56#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.09:29:00.56#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.09:29:00.56#ibcon#*before write, iclass 23, count 0 2006.173.09:29:00.56#ibcon#enter sib2, iclass 23, count 0 2006.173.09:29:00.56#ibcon#flushed, iclass 23, count 0 2006.173.09:29:00.56#ibcon#about to write, iclass 23, count 0 2006.173.09:29:00.56#ibcon#wrote, iclass 23, count 0 2006.173.09:29:00.56#ibcon#about to read 3, iclass 23, count 0 2006.173.09:29:00.60#ibcon#read 3, iclass 23, count 0 2006.173.09:29:00.60#ibcon#about to read 4, iclass 23, count 0 2006.173.09:29:00.60#ibcon#read 4, iclass 23, count 0 2006.173.09:29:00.60#ibcon#about to read 5, iclass 23, count 0 2006.173.09:29:00.60#ibcon#read 5, iclass 23, count 0 2006.173.09:29:00.60#ibcon#about to read 6, iclass 23, count 0 2006.173.09:29:00.60#ibcon#read 6, iclass 23, count 0 2006.173.09:29:00.60#ibcon#end of sib2, iclass 23, count 0 2006.173.09:29:00.60#ibcon#*after write, iclass 23, count 0 2006.173.09:29:00.60#ibcon#*before return 0, iclass 23, count 0 2006.173.09:29:00.60#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.09:29:00.60#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.09:29:00.60#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.09:29:00.60#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.09:29:00.60$vck44/va=5,4 2006.173.09:29:00.60#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.09:29:00.60#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.09:29:00.60#ibcon#ireg 11 cls_cnt 2 2006.173.09:29:00.60#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.09:29:00.66#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.09:29:00.66#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.09:29:00.66#ibcon#enter wrdev, iclass 25, count 2 2006.173.09:29:00.66#ibcon#first serial, iclass 25, count 2 2006.173.09:29:00.66#ibcon#enter sib2, iclass 25, count 2 2006.173.09:29:00.66#ibcon#flushed, iclass 25, count 2 2006.173.09:29:00.66#ibcon#about to write, iclass 25, count 2 2006.173.09:29:00.66#ibcon#wrote, iclass 25, count 2 2006.173.09:29:00.66#ibcon#about to read 3, iclass 25, count 2 2006.173.09:29:00.68#ibcon#read 3, iclass 25, count 2 2006.173.09:29:00.68#ibcon#about to read 4, iclass 25, count 2 2006.173.09:29:00.68#ibcon#read 4, iclass 25, count 2 2006.173.09:29:00.68#ibcon#about to read 5, iclass 25, count 2 2006.173.09:29:00.68#ibcon#read 5, iclass 25, count 2 2006.173.09:29:00.68#ibcon#about to read 6, iclass 25, count 2 2006.173.09:29:00.68#ibcon#read 6, iclass 25, count 2 2006.173.09:29:00.68#ibcon#end of sib2, iclass 25, count 2 2006.173.09:29:00.68#ibcon#*mode == 0, iclass 25, count 2 2006.173.09:29:00.68#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.09:29:00.68#ibcon#[25=AT05-04\r\n] 2006.173.09:29:00.68#ibcon#*before write, iclass 25, count 2 2006.173.09:29:00.68#ibcon#enter sib2, iclass 25, count 2 2006.173.09:29:00.68#ibcon#flushed, iclass 25, count 2 2006.173.09:29:00.68#ibcon#about to write, iclass 25, count 2 2006.173.09:29:00.68#ibcon#wrote, iclass 25, count 2 2006.173.09:29:00.68#ibcon#about to read 3, iclass 25, count 2 2006.173.09:29:00.71#ibcon#read 3, iclass 25, count 2 2006.173.09:29:00.71#ibcon#about to read 4, iclass 25, count 2 2006.173.09:29:00.71#ibcon#read 4, iclass 25, count 2 2006.173.09:29:00.71#ibcon#about to read 5, iclass 25, count 2 2006.173.09:29:00.71#ibcon#read 5, iclass 25, count 2 2006.173.09:29:00.71#ibcon#about to read 6, iclass 25, count 2 2006.173.09:29:00.71#ibcon#read 6, iclass 25, count 2 2006.173.09:29:00.71#ibcon#end of sib2, iclass 25, count 2 2006.173.09:29:00.71#ibcon#*after write, iclass 25, count 2 2006.173.09:29:00.71#ibcon#*before return 0, iclass 25, count 2 2006.173.09:29:00.71#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.09:29:00.71#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.09:29:00.71#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.09:29:00.71#ibcon#ireg 7 cls_cnt 0 2006.173.09:29:00.71#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.09:29:00.83#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.09:29:00.83#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.09:29:00.83#ibcon#enter wrdev, iclass 25, count 0 2006.173.09:29:00.83#ibcon#first serial, iclass 25, count 0 2006.173.09:29:00.83#ibcon#enter sib2, iclass 25, count 0 2006.173.09:29:00.83#ibcon#flushed, iclass 25, count 0 2006.173.09:29:00.83#ibcon#about to write, iclass 25, count 0 2006.173.09:29:00.83#ibcon#wrote, iclass 25, count 0 2006.173.09:29:00.83#ibcon#about to read 3, iclass 25, count 0 2006.173.09:29:00.85#ibcon#read 3, iclass 25, count 0 2006.173.09:29:00.85#ibcon#about to read 4, iclass 25, count 0 2006.173.09:29:00.85#ibcon#read 4, iclass 25, count 0 2006.173.09:29:00.85#ibcon#about to read 5, iclass 25, count 0 2006.173.09:29:00.85#ibcon#read 5, iclass 25, count 0 2006.173.09:29:00.85#ibcon#about to read 6, iclass 25, count 0 2006.173.09:29:00.85#ibcon#read 6, iclass 25, count 0 2006.173.09:29:00.85#ibcon#end of sib2, iclass 25, count 0 2006.173.09:29:00.85#ibcon#*mode == 0, iclass 25, count 0 2006.173.09:29:00.85#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.09:29:00.85#ibcon#[25=USB\r\n] 2006.173.09:29:00.85#ibcon#*before write, iclass 25, count 0 2006.173.09:29:00.85#ibcon#enter sib2, iclass 25, count 0 2006.173.09:29:00.85#ibcon#flushed, iclass 25, count 0 2006.173.09:29:00.85#ibcon#about to write, iclass 25, count 0 2006.173.09:29:00.85#ibcon#wrote, iclass 25, count 0 2006.173.09:29:00.85#ibcon#about to read 3, iclass 25, count 0 2006.173.09:29:00.88#ibcon#read 3, iclass 25, count 0 2006.173.09:29:00.88#ibcon#about to read 4, iclass 25, count 0 2006.173.09:29:00.88#ibcon#read 4, iclass 25, count 0 2006.173.09:29:00.88#ibcon#about to read 5, iclass 25, count 0 2006.173.09:29:00.88#ibcon#read 5, iclass 25, count 0 2006.173.09:29:00.88#ibcon#about to read 6, iclass 25, count 0 2006.173.09:29:00.88#ibcon#read 6, iclass 25, count 0 2006.173.09:29:00.88#ibcon#end of sib2, iclass 25, count 0 2006.173.09:29:00.88#ibcon#*after write, iclass 25, count 0 2006.173.09:29:00.88#ibcon#*before return 0, iclass 25, count 0 2006.173.09:29:00.88#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.09:29:00.88#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.09:29:00.88#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.09:29:00.88#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.09:29:00.88$vck44/valo=6,814.99 2006.173.09:29:00.88#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.09:29:00.88#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.09:29:00.88#ibcon#ireg 17 cls_cnt 0 2006.173.09:29:00.88#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.09:29:00.88#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.09:29:00.88#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.09:29:00.88#ibcon#enter wrdev, iclass 27, count 0 2006.173.09:29:00.88#ibcon#first serial, iclass 27, count 0 2006.173.09:29:00.88#ibcon#enter sib2, iclass 27, count 0 2006.173.09:29:00.88#ibcon#flushed, iclass 27, count 0 2006.173.09:29:00.88#ibcon#about to write, iclass 27, count 0 2006.173.09:29:00.88#ibcon#wrote, iclass 27, count 0 2006.173.09:29:00.88#ibcon#about to read 3, iclass 27, count 0 2006.173.09:29:00.90#ibcon#read 3, iclass 27, count 0 2006.173.09:29:00.90#ibcon#about to read 4, iclass 27, count 0 2006.173.09:29:00.90#ibcon#read 4, iclass 27, count 0 2006.173.09:29:00.90#ibcon#about to read 5, iclass 27, count 0 2006.173.09:29:00.90#ibcon#read 5, iclass 27, count 0 2006.173.09:29:00.90#ibcon#about to read 6, iclass 27, count 0 2006.173.09:29:00.90#ibcon#read 6, iclass 27, count 0 2006.173.09:29:00.90#ibcon#end of sib2, iclass 27, count 0 2006.173.09:29:00.90#ibcon#*mode == 0, iclass 27, count 0 2006.173.09:29:00.90#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.09:29:00.90#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.09:29:00.90#ibcon#*before write, iclass 27, count 0 2006.173.09:29:00.90#ibcon#enter sib2, iclass 27, count 0 2006.173.09:29:00.90#ibcon#flushed, iclass 27, count 0 2006.173.09:29:00.90#ibcon#about to write, iclass 27, count 0 2006.173.09:29:00.90#ibcon#wrote, iclass 27, count 0 2006.173.09:29:00.90#ibcon#about to read 3, iclass 27, count 0 2006.173.09:29:00.94#ibcon#read 3, iclass 27, count 0 2006.173.09:29:00.94#ibcon#about to read 4, iclass 27, count 0 2006.173.09:29:00.94#ibcon#read 4, iclass 27, count 0 2006.173.09:29:00.94#ibcon#about to read 5, iclass 27, count 0 2006.173.09:29:00.94#ibcon#read 5, iclass 27, count 0 2006.173.09:29:00.94#ibcon#about to read 6, iclass 27, count 0 2006.173.09:29:00.94#ibcon#read 6, iclass 27, count 0 2006.173.09:29:00.94#ibcon#end of sib2, iclass 27, count 0 2006.173.09:29:00.94#ibcon#*after write, iclass 27, count 0 2006.173.09:29:00.94#ibcon#*before return 0, iclass 27, count 0 2006.173.09:29:00.94#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.09:29:00.94#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.09:29:00.94#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.09:29:00.94#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.09:29:00.94$vck44/va=6,3 2006.173.09:29:00.94#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.09:29:00.94#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.09:29:00.94#ibcon#ireg 11 cls_cnt 2 2006.173.09:29:00.94#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.09:29:01.00#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.09:29:01.00#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.09:29:01.00#ibcon#enter wrdev, iclass 29, count 2 2006.173.09:29:01.00#ibcon#first serial, iclass 29, count 2 2006.173.09:29:01.00#ibcon#enter sib2, iclass 29, count 2 2006.173.09:29:01.00#ibcon#flushed, iclass 29, count 2 2006.173.09:29:01.00#ibcon#about to write, iclass 29, count 2 2006.173.09:29:01.00#ibcon#wrote, iclass 29, count 2 2006.173.09:29:01.00#ibcon#about to read 3, iclass 29, count 2 2006.173.09:29:01.02#ibcon#read 3, iclass 29, count 2 2006.173.09:29:01.02#ibcon#about to read 4, iclass 29, count 2 2006.173.09:29:01.02#ibcon#read 4, iclass 29, count 2 2006.173.09:29:01.02#ibcon#about to read 5, iclass 29, count 2 2006.173.09:29:01.02#ibcon#read 5, iclass 29, count 2 2006.173.09:29:01.02#ibcon#about to read 6, iclass 29, count 2 2006.173.09:29:01.02#ibcon#read 6, iclass 29, count 2 2006.173.09:29:01.02#ibcon#end of sib2, iclass 29, count 2 2006.173.09:29:01.02#ibcon#*mode == 0, iclass 29, count 2 2006.173.09:29:01.02#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.09:29:01.02#ibcon#[25=AT06-03\r\n] 2006.173.09:29:01.02#ibcon#*before write, iclass 29, count 2 2006.173.09:29:01.02#ibcon#enter sib2, iclass 29, count 2 2006.173.09:29:01.02#ibcon#flushed, iclass 29, count 2 2006.173.09:29:01.02#ibcon#about to write, iclass 29, count 2 2006.173.09:29:01.02#ibcon#wrote, iclass 29, count 2 2006.173.09:29:01.02#ibcon#about to read 3, iclass 29, count 2 2006.173.09:29:01.05#ibcon#read 3, iclass 29, count 2 2006.173.09:29:01.05#ibcon#about to read 4, iclass 29, count 2 2006.173.09:29:01.05#ibcon#read 4, iclass 29, count 2 2006.173.09:29:01.05#ibcon#about to read 5, iclass 29, count 2 2006.173.09:29:01.05#ibcon#read 5, iclass 29, count 2 2006.173.09:29:01.05#ibcon#about to read 6, iclass 29, count 2 2006.173.09:29:01.05#ibcon#read 6, iclass 29, count 2 2006.173.09:29:01.05#ibcon#end of sib2, iclass 29, count 2 2006.173.09:29:01.05#ibcon#*after write, iclass 29, count 2 2006.173.09:29:01.05#ibcon#*before return 0, iclass 29, count 2 2006.173.09:29:01.05#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.09:29:01.05#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.09:29:01.05#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.09:29:01.05#ibcon#ireg 7 cls_cnt 0 2006.173.09:29:01.05#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.09:29:01.17#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.09:29:01.17#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.09:29:01.17#ibcon#enter wrdev, iclass 29, count 0 2006.173.09:29:01.17#ibcon#first serial, iclass 29, count 0 2006.173.09:29:01.17#ibcon#enter sib2, iclass 29, count 0 2006.173.09:29:01.17#ibcon#flushed, iclass 29, count 0 2006.173.09:29:01.17#ibcon#about to write, iclass 29, count 0 2006.173.09:29:01.17#ibcon#wrote, iclass 29, count 0 2006.173.09:29:01.17#ibcon#about to read 3, iclass 29, count 0 2006.173.09:29:01.19#ibcon#read 3, iclass 29, count 0 2006.173.09:29:01.19#ibcon#about to read 4, iclass 29, count 0 2006.173.09:29:01.19#ibcon#read 4, iclass 29, count 0 2006.173.09:29:01.19#ibcon#about to read 5, iclass 29, count 0 2006.173.09:29:01.19#ibcon#read 5, iclass 29, count 0 2006.173.09:29:01.19#ibcon#about to read 6, iclass 29, count 0 2006.173.09:29:01.19#ibcon#read 6, iclass 29, count 0 2006.173.09:29:01.19#ibcon#end of sib2, iclass 29, count 0 2006.173.09:29:01.19#ibcon#*mode == 0, iclass 29, count 0 2006.173.09:29:01.19#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.09:29:01.19#ibcon#[25=USB\r\n] 2006.173.09:29:01.19#ibcon#*before write, iclass 29, count 0 2006.173.09:29:01.19#ibcon#enter sib2, iclass 29, count 0 2006.173.09:29:01.19#ibcon#flushed, iclass 29, count 0 2006.173.09:29:01.19#ibcon#about to write, iclass 29, count 0 2006.173.09:29:01.19#ibcon#wrote, iclass 29, count 0 2006.173.09:29:01.19#ibcon#about to read 3, iclass 29, count 0 2006.173.09:29:01.22#ibcon#read 3, iclass 29, count 0 2006.173.09:29:01.22#ibcon#about to read 4, iclass 29, count 0 2006.173.09:29:01.22#ibcon#read 4, iclass 29, count 0 2006.173.09:29:01.22#ibcon#about to read 5, iclass 29, count 0 2006.173.09:29:01.22#ibcon#read 5, iclass 29, count 0 2006.173.09:29:01.22#ibcon#about to read 6, iclass 29, count 0 2006.173.09:29:01.22#ibcon#read 6, iclass 29, count 0 2006.173.09:29:01.22#ibcon#end of sib2, iclass 29, count 0 2006.173.09:29:01.22#ibcon#*after write, iclass 29, count 0 2006.173.09:29:01.22#ibcon#*before return 0, iclass 29, count 0 2006.173.09:29:01.22#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.09:29:01.22#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.09:29:01.22#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.09:29:01.22#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.09:29:01.22$vck44/valo=7,864.99 2006.173.09:29:01.22#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.09:29:01.22#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.09:29:01.22#ibcon#ireg 17 cls_cnt 0 2006.173.09:29:01.22#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.09:29:01.22#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.09:29:01.22#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.09:29:01.22#ibcon#enter wrdev, iclass 31, count 0 2006.173.09:29:01.22#ibcon#first serial, iclass 31, count 0 2006.173.09:29:01.22#ibcon#enter sib2, iclass 31, count 0 2006.173.09:29:01.22#ibcon#flushed, iclass 31, count 0 2006.173.09:29:01.22#ibcon#about to write, iclass 31, count 0 2006.173.09:29:01.22#ibcon#wrote, iclass 31, count 0 2006.173.09:29:01.22#ibcon#about to read 3, iclass 31, count 0 2006.173.09:29:01.24#ibcon#read 3, iclass 31, count 0 2006.173.09:29:01.24#ibcon#about to read 4, iclass 31, count 0 2006.173.09:29:01.24#ibcon#read 4, iclass 31, count 0 2006.173.09:29:01.24#ibcon#about to read 5, iclass 31, count 0 2006.173.09:29:01.24#ibcon#read 5, iclass 31, count 0 2006.173.09:29:01.24#ibcon#about to read 6, iclass 31, count 0 2006.173.09:29:01.24#ibcon#read 6, iclass 31, count 0 2006.173.09:29:01.24#ibcon#end of sib2, iclass 31, count 0 2006.173.09:29:01.24#ibcon#*mode == 0, iclass 31, count 0 2006.173.09:29:01.24#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.09:29:01.24#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.09:29:01.24#ibcon#*before write, iclass 31, count 0 2006.173.09:29:01.24#ibcon#enter sib2, iclass 31, count 0 2006.173.09:29:01.24#ibcon#flushed, iclass 31, count 0 2006.173.09:29:01.24#ibcon#about to write, iclass 31, count 0 2006.173.09:29:01.24#ibcon#wrote, iclass 31, count 0 2006.173.09:29:01.24#ibcon#about to read 3, iclass 31, count 0 2006.173.09:29:01.28#ibcon#read 3, iclass 31, count 0 2006.173.09:29:01.28#ibcon#about to read 4, iclass 31, count 0 2006.173.09:29:01.28#ibcon#read 4, iclass 31, count 0 2006.173.09:29:01.28#ibcon#about to read 5, iclass 31, count 0 2006.173.09:29:01.28#ibcon#read 5, iclass 31, count 0 2006.173.09:29:01.28#ibcon#about to read 6, iclass 31, count 0 2006.173.09:29:01.28#ibcon#read 6, iclass 31, count 0 2006.173.09:29:01.28#ibcon#end of sib2, iclass 31, count 0 2006.173.09:29:01.28#ibcon#*after write, iclass 31, count 0 2006.173.09:29:01.28#ibcon#*before return 0, iclass 31, count 0 2006.173.09:29:01.28#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.09:29:01.28#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.09:29:01.28#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.09:29:01.28#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.09:29:01.28$vck44/va=7,4 2006.173.09:29:01.28#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.173.09:29:01.28#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.173.09:29:01.28#ibcon#ireg 11 cls_cnt 2 2006.173.09:29:01.28#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.09:29:01.34#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.09:29:01.34#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.09:29:01.34#ibcon#enter wrdev, iclass 33, count 2 2006.173.09:29:01.34#ibcon#first serial, iclass 33, count 2 2006.173.09:29:01.34#ibcon#enter sib2, iclass 33, count 2 2006.173.09:29:01.34#ibcon#flushed, iclass 33, count 2 2006.173.09:29:01.34#ibcon#about to write, iclass 33, count 2 2006.173.09:29:01.34#ibcon#wrote, iclass 33, count 2 2006.173.09:29:01.34#ibcon#about to read 3, iclass 33, count 2 2006.173.09:29:01.36#ibcon#read 3, iclass 33, count 2 2006.173.09:29:01.36#ibcon#about to read 4, iclass 33, count 2 2006.173.09:29:01.36#ibcon#read 4, iclass 33, count 2 2006.173.09:29:01.36#ibcon#about to read 5, iclass 33, count 2 2006.173.09:29:01.36#ibcon#read 5, iclass 33, count 2 2006.173.09:29:01.36#ibcon#about to read 6, iclass 33, count 2 2006.173.09:29:01.36#ibcon#read 6, iclass 33, count 2 2006.173.09:29:01.36#ibcon#end of sib2, iclass 33, count 2 2006.173.09:29:01.36#ibcon#*mode == 0, iclass 33, count 2 2006.173.09:29:01.36#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.173.09:29:01.36#ibcon#[25=AT07-04\r\n] 2006.173.09:29:01.36#ibcon#*before write, iclass 33, count 2 2006.173.09:29:01.36#ibcon#enter sib2, iclass 33, count 2 2006.173.09:29:01.36#ibcon#flushed, iclass 33, count 2 2006.173.09:29:01.36#ibcon#about to write, iclass 33, count 2 2006.173.09:29:01.36#ibcon#wrote, iclass 33, count 2 2006.173.09:29:01.36#ibcon#about to read 3, iclass 33, count 2 2006.173.09:29:01.39#ibcon#read 3, iclass 33, count 2 2006.173.09:29:01.39#ibcon#about to read 4, iclass 33, count 2 2006.173.09:29:01.39#ibcon#read 4, iclass 33, count 2 2006.173.09:29:01.39#ibcon#about to read 5, iclass 33, count 2 2006.173.09:29:01.39#ibcon#read 5, iclass 33, count 2 2006.173.09:29:01.39#ibcon#about to read 6, iclass 33, count 2 2006.173.09:29:01.39#ibcon#read 6, iclass 33, count 2 2006.173.09:29:01.39#ibcon#end of sib2, iclass 33, count 2 2006.173.09:29:01.39#ibcon#*after write, iclass 33, count 2 2006.173.09:29:01.39#ibcon#*before return 0, iclass 33, count 2 2006.173.09:29:01.39#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.09:29:01.39#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.173.09:29:01.39#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.173.09:29:01.39#ibcon#ireg 7 cls_cnt 0 2006.173.09:29:01.39#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.09:29:01.51#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.09:29:01.51#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.09:29:01.51#ibcon#enter wrdev, iclass 33, count 0 2006.173.09:29:01.51#ibcon#first serial, iclass 33, count 0 2006.173.09:29:01.51#ibcon#enter sib2, iclass 33, count 0 2006.173.09:29:01.51#ibcon#flushed, iclass 33, count 0 2006.173.09:29:01.51#ibcon#about to write, iclass 33, count 0 2006.173.09:29:01.51#ibcon#wrote, iclass 33, count 0 2006.173.09:29:01.51#ibcon#about to read 3, iclass 33, count 0 2006.173.09:29:01.53#ibcon#read 3, iclass 33, count 0 2006.173.09:29:01.53#ibcon#about to read 4, iclass 33, count 0 2006.173.09:29:01.53#ibcon#read 4, iclass 33, count 0 2006.173.09:29:01.53#ibcon#about to read 5, iclass 33, count 0 2006.173.09:29:01.53#ibcon#read 5, iclass 33, count 0 2006.173.09:29:01.53#ibcon#about to read 6, iclass 33, count 0 2006.173.09:29:01.53#ibcon#read 6, iclass 33, count 0 2006.173.09:29:01.53#ibcon#end of sib2, iclass 33, count 0 2006.173.09:29:01.53#ibcon#*mode == 0, iclass 33, count 0 2006.173.09:29:01.53#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.09:29:01.53#ibcon#[25=USB\r\n] 2006.173.09:29:01.53#ibcon#*before write, iclass 33, count 0 2006.173.09:29:01.53#ibcon#enter sib2, iclass 33, count 0 2006.173.09:29:01.53#ibcon#flushed, iclass 33, count 0 2006.173.09:29:01.53#ibcon#about to write, iclass 33, count 0 2006.173.09:29:01.53#ibcon#wrote, iclass 33, count 0 2006.173.09:29:01.53#ibcon#about to read 3, iclass 33, count 0 2006.173.09:29:01.56#ibcon#read 3, iclass 33, count 0 2006.173.09:29:01.56#ibcon#about to read 4, iclass 33, count 0 2006.173.09:29:01.56#ibcon#read 4, iclass 33, count 0 2006.173.09:29:01.56#ibcon#about to read 5, iclass 33, count 0 2006.173.09:29:01.56#ibcon#read 5, iclass 33, count 0 2006.173.09:29:01.56#ibcon#about to read 6, iclass 33, count 0 2006.173.09:29:01.56#ibcon#read 6, iclass 33, count 0 2006.173.09:29:01.56#ibcon#end of sib2, iclass 33, count 0 2006.173.09:29:01.56#ibcon#*after write, iclass 33, count 0 2006.173.09:29:01.56#ibcon#*before return 0, iclass 33, count 0 2006.173.09:29:01.56#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.09:29:01.56#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.173.09:29:01.56#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.09:29:01.56#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.09:29:01.56$vck44/valo=8,884.99 2006.173.09:29:01.56#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.09:29:01.56#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.09:29:01.56#ibcon#ireg 17 cls_cnt 0 2006.173.09:29:01.56#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.09:29:01.56#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.09:29:01.56#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.09:29:01.56#ibcon#enter wrdev, iclass 35, count 0 2006.173.09:29:01.56#ibcon#first serial, iclass 35, count 0 2006.173.09:29:01.56#ibcon#enter sib2, iclass 35, count 0 2006.173.09:29:01.56#ibcon#flushed, iclass 35, count 0 2006.173.09:29:01.56#ibcon#about to write, iclass 35, count 0 2006.173.09:29:01.56#ibcon#wrote, iclass 35, count 0 2006.173.09:29:01.56#ibcon#about to read 3, iclass 35, count 0 2006.173.09:29:01.58#ibcon#read 3, iclass 35, count 0 2006.173.09:29:01.58#ibcon#about to read 4, iclass 35, count 0 2006.173.09:29:01.58#ibcon#read 4, iclass 35, count 0 2006.173.09:29:01.58#ibcon#about to read 5, iclass 35, count 0 2006.173.09:29:01.58#ibcon#read 5, iclass 35, count 0 2006.173.09:29:01.58#ibcon#about to read 6, iclass 35, count 0 2006.173.09:29:01.58#ibcon#read 6, iclass 35, count 0 2006.173.09:29:01.58#ibcon#end of sib2, iclass 35, count 0 2006.173.09:29:01.58#ibcon#*mode == 0, iclass 35, count 0 2006.173.09:29:01.58#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.09:29:01.58#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.09:29:01.58#ibcon#*before write, iclass 35, count 0 2006.173.09:29:01.58#ibcon#enter sib2, iclass 35, count 0 2006.173.09:29:01.58#ibcon#flushed, iclass 35, count 0 2006.173.09:29:01.58#ibcon#about to write, iclass 35, count 0 2006.173.09:29:01.58#ibcon#wrote, iclass 35, count 0 2006.173.09:29:01.58#ibcon#about to read 3, iclass 35, count 0 2006.173.09:29:01.62#ibcon#read 3, iclass 35, count 0 2006.173.09:29:01.62#ibcon#about to read 4, iclass 35, count 0 2006.173.09:29:01.62#ibcon#read 4, iclass 35, count 0 2006.173.09:29:01.62#ibcon#about to read 5, iclass 35, count 0 2006.173.09:29:01.62#ibcon#read 5, iclass 35, count 0 2006.173.09:29:01.62#ibcon#about to read 6, iclass 35, count 0 2006.173.09:29:01.62#ibcon#read 6, iclass 35, count 0 2006.173.09:29:01.62#ibcon#end of sib2, iclass 35, count 0 2006.173.09:29:01.62#ibcon#*after write, iclass 35, count 0 2006.173.09:29:01.62#ibcon#*before return 0, iclass 35, count 0 2006.173.09:29:01.62#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.09:29:01.62#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.09:29:01.62#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.09:29:01.62#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.09:29:01.62$vck44/va=8,4 2006.173.09:29:01.62#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.173.09:29:01.62#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.173.09:29:01.62#ibcon#ireg 11 cls_cnt 2 2006.173.09:29:01.62#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.09:29:01.68#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.09:29:01.68#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.09:29:01.68#ibcon#enter wrdev, iclass 37, count 2 2006.173.09:29:01.68#ibcon#first serial, iclass 37, count 2 2006.173.09:29:01.68#ibcon#enter sib2, iclass 37, count 2 2006.173.09:29:01.68#ibcon#flushed, iclass 37, count 2 2006.173.09:29:01.68#ibcon#about to write, iclass 37, count 2 2006.173.09:29:01.68#ibcon#wrote, iclass 37, count 2 2006.173.09:29:01.68#ibcon#about to read 3, iclass 37, count 2 2006.173.09:29:01.70#ibcon#read 3, iclass 37, count 2 2006.173.09:29:01.70#ibcon#about to read 4, iclass 37, count 2 2006.173.09:29:01.70#ibcon#read 4, iclass 37, count 2 2006.173.09:29:01.70#ibcon#about to read 5, iclass 37, count 2 2006.173.09:29:01.70#ibcon#read 5, iclass 37, count 2 2006.173.09:29:01.70#ibcon#about to read 6, iclass 37, count 2 2006.173.09:29:01.70#ibcon#read 6, iclass 37, count 2 2006.173.09:29:01.70#ibcon#end of sib2, iclass 37, count 2 2006.173.09:29:01.70#ibcon#*mode == 0, iclass 37, count 2 2006.173.09:29:01.70#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.173.09:29:01.70#ibcon#[25=AT08-04\r\n] 2006.173.09:29:01.70#ibcon#*before write, iclass 37, count 2 2006.173.09:29:01.70#ibcon#enter sib2, iclass 37, count 2 2006.173.09:29:01.70#ibcon#flushed, iclass 37, count 2 2006.173.09:29:01.70#ibcon#about to write, iclass 37, count 2 2006.173.09:29:01.70#ibcon#wrote, iclass 37, count 2 2006.173.09:29:01.70#ibcon#about to read 3, iclass 37, count 2 2006.173.09:29:01.73#ibcon#read 3, iclass 37, count 2 2006.173.09:29:01.73#ibcon#about to read 4, iclass 37, count 2 2006.173.09:29:01.73#ibcon#read 4, iclass 37, count 2 2006.173.09:29:01.73#ibcon#about to read 5, iclass 37, count 2 2006.173.09:29:01.73#ibcon#read 5, iclass 37, count 2 2006.173.09:29:01.73#ibcon#about to read 6, iclass 37, count 2 2006.173.09:29:01.73#ibcon#read 6, iclass 37, count 2 2006.173.09:29:01.73#ibcon#end of sib2, iclass 37, count 2 2006.173.09:29:01.73#ibcon#*after write, iclass 37, count 2 2006.173.09:29:01.73#ibcon#*before return 0, iclass 37, count 2 2006.173.09:29:01.73#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.09:29:01.73#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.173.09:29:01.73#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.173.09:29:01.73#ibcon#ireg 7 cls_cnt 0 2006.173.09:29:01.73#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.09:29:01.85#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.09:29:01.85#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.09:29:01.85#ibcon#enter wrdev, iclass 37, count 0 2006.173.09:29:01.85#ibcon#first serial, iclass 37, count 0 2006.173.09:29:01.85#ibcon#enter sib2, iclass 37, count 0 2006.173.09:29:01.85#ibcon#flushed, iclass 37, count 0 2006.173.09:29:01.85#ibcon#about to write, iclass 37, count 0 2006.173.09:29:01.85#ibcon#wrote, iclass 37, count 0 2006.173.09:29:01.85#ibcon#about to read 3, iclass 37, count 0 2006.173.09:29:01.87#ibcon#read 3, iclass 37, count 0 2006.173.09:29:01.87#ibcon#about to read 4, iclass 37, count 0 2006.173.09:29:01.87#ibcon#read 4, iclass 37, count 0 2006.173.09:29:01.87#ibcon#about to read 5, iclass 37, count 0 2006.173.09:29:01.87#ibcon#read 5, iclass 37, count 0 2006.173.09:29:01.87#ibcon#about to read 6, iclass 37, count 0 2006.173.09:29:01.87#ibcon#read 6, iclass 37, count 0 2006.173.09:29:01.87#ibcon#end of sib2, iclass 37, count 0 2006.173.09:29:01.87#ibcon#*mode == 0, iclass 37, count 0 2006.173.09:29:01.87#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.09:29:01.87#ibcon#[25=USB\r\n] 2006.173.09:29:01.87#ibcon#*before write, iclass 37, count 0 2006.173.09:29:01.87#ibcon#enter sib2, iclass 37, count 0 2006.173.09:29:01.87#ibcon#flushed, iclass 37, count 0 2006.173.09:29:01.87#ibcon#about to write, iclass 37, count 0 2006.173.09:29:01.87#ibcon#wrote, iclass 37, count 0 2006.173.09:29:01.87#ibcon#about to read 3, iclass 37, count 0 2006.173.09:29:01.90#ibcon#read 3, iclass 37, count 0 2006.173.09:29:01.90#ibcon#about to read 4, iclass 37, count 0 2006.173.09:29:01.90#ibcon#read 4, iclass 37, count 0 2006.173.09:29:01.90#ibcon#about to read 5, iclass 37, count 0 2006.173.09:29:01.90#ibcon#read 5, iclass 37, count 0 2006.173.09:29:01.90#ibcon#about to read 6, iclass 37, count 0 2006.173.09:29:01.90#ibcon#read 6, iclass 37, count 0 2006.173.09:29:01.90#ibcon#end of sib2, iclass 37, count 0 2006.173.09:29:01.90#ibcon#*after write, iclass 37, count 0 2006.173.09:29:01.90#ibcon#*before return 0, iclass 37, count 0 2006.173.09:29:01.90#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.09:29:01.90#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.173.09:29:01.90#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.09:29:01.90#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.09:29:01.90$vck44/vblo=1,629.99 2006.173.09:29:01.90#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.09:29:01.90#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.09:29:01.90#ibcon#ireg 17 cls_cnt 0 2006.173.09:29:01.90#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.09:29:01.90#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.09:29:01.90#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.09:29:01.90#ibcon#enter wrdev, iclass 39, count 0 2006.173.09:29:01.90#ibcon#first serial, iclass 39, count 0 2006.173.09:29:01.90#ibcon#enter sib2, iclass 39, count 0 2006.173.09:29:01.90#ibcon#flushed, iclass 39, count 0 2006.173.09:29:01.90#ibcon#about to write, iclass 39, count 0 2006.173.09:29:01.90#ibcon#wrote, iclass 39, count 0 2006.173.09:29:01.90#ibcon#about to read 3, iclass 39, count 0 2006.173.09:29:01.92#ibcon#read 3, iclass 39, count 0 2006.173.09:29:01.92#ibcon#about to read 4, iclass 39, count 0 2006.173.09:29:01.92#ibcon#read 4, iclass 39, count 0 2006.173.09:29:01.92#ibcon#about to read 5, iclass 39, count 0 2006.173.09:29:01.92#ibcon#read 5, iclass 39, count 0 2006.173.09:29:01.92#ibcon#about to read 6, iclass 39, count 0 2006.173.09:29:01.92#ibcon#read 6, iclass 39, count 0 2006.173.09:29:01.92#ibcon#end of sib2, iclass 39, count 0 2006.173.09:29:01.92#ibcon#*mode == 0, iclass 39, count 0 2006.173.09:29:01.92#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.09:29:01.92#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.09:29:01.92#ibcon#*before write, iclass 39, count 0 2006.173.09:29:01.92#ibcon#enter sib2, iclass 39, count 0 2006.173.09:29:01.92#ibcon#flushed, iclass 39, count 0 2006.173.09:29:01.92#ibcon#about to write, iclass 39, count 0 2006.173.09:29:01.92#ibcon#wrote, iclass 39, count 0 2006.173.09:29:01.92#ibcon#about to read 3, iclass 39, count 0 2006.173.09:29:01.96#ibcon#read 3, iclass 39, count 0 2006.173.09:29:01.96#ibcon#about to read 4, iclass 39, count 0 2006.173.09:29:01.96#ibcon#read 4, iclass 39, count 0 2006.173.09:29:01.96#ibcon#about to read 5, iclass 39, count 0 2006.173.09:29:01.96#ibcon#read 5, iclass 39, count 0 2006.173.09:29:01.96#ibcon#about to read 6, iclass 39, count 0 2006.173.09:29:01.96#ibcon#read 6, iclass 39, count 0 2006.173.09:29:01.96#ibcon#end of sib2, iclass 39, count 0 2006.173.09:29:01.96#ibcon#*after write, iclass 39, count 0 2006.173.09:29:01.96#ibcon#*before return 0, iclass 39, count 0 2006.173.09:29:01.96#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.09:29:01.96#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.09:29:01.96#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.09:29:01.96#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.09:29:01.96$vck44/vb=1,4 2006.173.09:29:01.96#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.09:29:01.96#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.09:29:01.96#ibcon#ireg 11 cls_cnt 2 2006.173.09:29:01.96#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.09:29:01.96#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.09:29:01.96#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.09:29:01.96#ibcon#enter wrdev, iclass 3, count 2 2006.173.09:29:01.96#ibcon#first serial, iclass 3, count 2 2006.173.09:29:01.96#ibcon#enter sib2, iclass 3, count 2 2006.173.09:29:01.96#ibcon#flushed, iclass 3, count 2 2006.173.09:29:01.96#ibcon#about to write, iclass 3, count 2 2006.173.09:29:01.96#ibcon#wrote, iclass 3, count 2 2006.173.09:29:01.96#ibcon#about to read 3, iclass 3, count 2 2006.173.09:29:01.98#ibcon#read 3, iclass 3, count 2 2006.173.09:29:01.98#ibcon#about to read 4, iclass 3, count 2 2006.173.09:29:01.98#ibcon#read 4, iclass 3, count 2 2006.173.09:29:01.98#ibcon#about to read 5, iclass 3, count 2 2006.173.09:29:01.98#ibcon#read 5, iclass 3, count 2 2006.173.09:29:01.98#ibcon#about to read 6, iclass 3, count 2 2006.173.09:29:01.98#ibcon#read 6, iclass 3, count 2 2006.173.09:29:01.98#ibcon#end of sib2, iclass 3, count 2 2006.173.09:29:01.98#ibcon#*mode == 0, iclass 3, count 2 2006.173.09:29:01.98#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.09:29:01.98#ibcon#[27=AT01-04\r\n] 2006.173.09:29:01.98#ibcon#*before write, iclass 3, count 2 2006.173.09:29:01.98#ibcon#enter sib2, iclass 3, count 2 2006.173.09:29:01.98#ibcon#flushed, iclass 3, count 2 2006.173.09:29:01.98#ibcon#about to write, iclass 3, count 2 2006.173.09:29:01.98#ibcon#wrote, iclass 3, count 2 2006.173.09:29:01.98#ibcon#about to read 3, iclass 3, count 2 2006.173.09:29:02.01#ibcon#read 3, iclass 3, count 2 2006.173.09:29:02.01#ibcon#about to read 4, iclass 3, count 2 2006.173.09:29:02.01#ibcon#read 4, iclass 3, count 2 2006.173.09:29:02.01#ibcon#about to read 5, iclass 3, count 2 2006.173.09:29:02.01#ibcon#read 5, iclass 3, count 2 2006.173.09:29:02.01#ibcon#about to read 6, iclass 3, count 2 2006.173.09:29:02.01#ibcon#read 6, iclass 3, count 2 2006.173.09:29:02.01#ibcon#end of sib2, iclass 3, count 2 2006.173.09:29:02.01#ibcon#*after write, iclass 3, count 2 2006.173.09:29:02.01#ibcon#*before return 0, iclass 3, count 2 2006.173.09:29:02.01#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.09:29:02.01#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.09:29:02.01#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.09:29:02.01#ibcon#ireg 7 cls_cnt 0 2006.173.09:29:02.01#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.09:29:02.13#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.09:29:02.13#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.09:29:02.13#ibcon#enter wrdev, iclass 3, count 0 2006.173.09:29:02.13#ibcon#first serial, iclass 3, count 0 2006.173.09:29:02.13#ibcon#enter sib2, iclass 3, count 0 2006.173.09:29:02.13#ibcon#flushed, iclass 3, count 0 2006.173.09:29:02.13#ibcon#about to write, iclass 3, count 0 2006.173.09:29:02.13#ibcon#wrote, iclass 3, count 0 2006.173.09:29:02.13#ibcon#about to read 3, iclass 3, count 0 2006.173.09:29:02.15#ibcon#read 3, iclass 3, count 0 2006.173.09:29:02.15#ibcon#about to read 4, iclass 3, count 0 2006.173.09:29:02.15#ibcon#read 4, iclass 3, count 0 2006.173.09:29:02.15#ibcon#about to read 5, iclass 3, count 0 2006.173.09:29:02.15#ibcon#read 5, iclass 3, count 0 2006.173.09:29:02.15#ibcon#about to read 6, iclass 3, count 0 2006.173.09:29:02.15#ibcon#read 6, iclass 3, count 0 2006.173.09:29:02.15#ibcon#end of sib2, iclass 3, count 0 2006.173.09:29:02.15#ibcon#*mode == 0, iclass 3, count 0 2006.173.09:29:02.15#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.09:29:02.15#ibcon#[27=USB\r\n] 2006.173.09:29:02.15#ibcon#*before write, iclass 3, count 0 2006.173.09:29:02.15#ibcon#enter sib2, iclass 3, count 0 2006.173.09:29:02.15#ibcon#flushed, iclass 3, count 0 2006.173.09:29:02.15#ibcon#about to write, iclass 3, count 0 2006.173.09:29:02.15#ibcon#wrote, iclass 3, count 0 2006.173.09:29:02.15#ibcon#about to read 3, iclass 3, count 0 2006.173.09:29:02.18#ibcon#read 3, iclass 3, count 0 2006.173.09:29:02.18#ibcon#about to read 4, iclass 3, count 0 2006.173.09:29:02.18#ibcon#read 4, iclass 3, count 0 2006.173.09:29:02.18#ibcon#about to read 5, iclass 3, count 0 2006.173.09:29:02.18#ibcon#read 5, iclass 3, count 0 2006.173.09:29:02.18#ibcon#about to read 6, iclass 3, count 0 2006.173.09:29:02.18#ibcon#read 6, iclass 3, count 0 2006.173.09:29:02.18#ibcon#end of sib2, iclass 3, count 0 2006.173.09:29:02.18#ibcon#*after write, iclass 3, count 0 2006.173.09:29:02.18#ibcon#*before return 0, iclass 3, count 0 2006.173.09:29:02.18#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.09:29:02.18#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.09:29:02.18#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.09:29:02.18#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.09:29:02.18$vck44/vblo=2,634.99 2006.173.09:29:02.18#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.09:29:02.18#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.09:29:02.18#ibcon#ireg 17 cls_cnt 0 2006.173.09:29:02.18#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.09:29:02.18#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.09:29:02.18#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.09:29:02.18#ibcon#enter wrdev, iclass 5, count 0 2006.173.09:29:02.18#ibcon#first serial, iclass 5, count 0 2006.173.09:29:02.18#ibcon#enter sib2, iclass 5, count 0 2006.173.09:29:02.18#ibcon#flushed, iclass 5, count 0 2006.173.09:29:02.18#ibcon#about to write, iclass 5, count 0 2006.173.09:29:02.18#ibcon#wrote, iclass 5, count 0 2006.173.09:29:02.18#ibcon#about to read 3, iclass 5, count 0 2006.173.09:29:02.20#ibcon#read 3, iclass 5, count 0 2006.173.09:29:02.20#ibcon#about to read 4, iclass 5, count 0 2006.173.09:29:02.20#ibcon#read 4, iclass 5, count 0 2006.173.09:29:02.20#ibcon#about to read 5, iclass 5, count 0 2006.173.09:29:02.20#ibcon#read 5, iclass 5, count 0 2006.173.09:29:02.20#ibcon#about to read 6, iclass 5, count 0 2006.173.09:29:02.20#ibcon#read 6, iclass 5, count 0 2006.173.09:29:02.20#ibcon#end of sib2, iclass 5, count 0 2006.173.09:29:02.20#ibcon#*mode == 0, iclass 5, count 0 2006.173.09:29:02.20#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.09:29:02.20#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.09:29:02.20#ibcon#*before write, iclass 5, count 0 2006.173.09:29:02.20#ibcon#enter sib2, iclass 5, count 0 2006.173.09:29:02.20#ibcon#flushed, iclass 5, count 0 2006.173.09:29:02.20#ibcon#about to write, iclass 5, count 0 2006.173.09:29:02.20#ibcon#wrote, iclass 5, count 0 2006.173.09:29:02.20#ibcon#about to read 3, iclass 5, count 0 2006.173.09:29:02.24#ibcon#read 3, iclass 5, count 0 2006.173.09:29:02.24#ibcon#about to read 4, iclass 5, count 0 2006.173.09:29:02.24#ibcon#read 4, iclass 5, count 0 2006.173.09:29:02.24#ibcon#about to read 5, iclass 5, count 0 2006.173.09:29:02.24#ibcon#read 5, iclass 5, count 0 2006.173.09:29:02.24#ibcon#about to read 6, iclass 5, count 0 2006.173.09:29:02.24#ibcon#read 6, iclass 5, count 0 2006.173.09:29:02.24#ibcon#end of sib2, iclass 5, count 0 2006.173.09:29:02.24#ibcon#*after write, iclass 5, count 0 2006.173.09:29:02.24#ibcon#*before return 0, iclass 5, count 0 2006.173.09:29:02.24#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.09:29:02.24#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.09:29:02.24#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.09:29:02.24#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.09:29:02.24$vck44/vb=2,4 2006.173.09:29:02.24#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.173.09:29:02.24#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.173.09:29:02.24#ibcon#ireg 11 cls_cnt 2 2006.173.09:29:02.24#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.09:29:02.30#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.09:29:02.30#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.09:29:02.30#ibcon#enter wrdev, iclass 7, count 2 2006.173.09:29:02.30#ibcon#first serial, iclass 7, count 2 2006.173.09:29:02.30#ibcon#enter sib2, iclass 7, count 2 2006.173.09:29:02.30#ibcon#flushed, iclass 7, count 2 2006.173.09:29:02.30#ibcon#about to write, iclass 7, count 2 2006.173.09:29:02.30#ibcon#wrote, iclass 7, count 2 2006.173.09:29:02.30#ibcon#about to read 3, iclass 7, count 2 2006.173.09:29:02.32#ibcon#read 3, iclass 7, count 2 2006.173.09:29:02.32#ibcon#about to read 4, iclass 7, count 2 2006.173.09:29:02.32#ibcon#read 4, iclass 7, count 2 2006.173.09:29:02.32#ibcon#about to read 5, iclass 7, count 2 2006.173.09:29:02.32#ibcon#read 5, iclass 7, count 2 2006.173.09:29:02.32#ibcon#about to read 6, iclass 7, count 2 2006.173.09:29:02.32#ibcon#read 6, iclass 7, count 2 2006.173.09:29:02.32#ibcon#end of sib2, iclass 7, count 2 2006.173.09:29:02.32#ibcon#*mode == 0, iclass 7, count 2 2006.173.09:29:02.32#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.173.09:29:02.32#ibcon#[27=AT02-04\r\n] 2006.173.09:29:02.32#ibcon#*before write, iclass 7, count 2 2006.173.09:29:02.32#ibcon#enter sib2, iclass 7, count 2 2006.173.09:29:02.32#ibcon#flushed, iclass 7, count 2 2006.173.09:29:02.32#ibcon#about to write, iclass 7, count 2 2006.173.09:29:02.32#ibcon#wrote, iclass 7, count 2 2006.173.09:29:02.32#ibcon#about to read 3, iclass 7, count 2 2006.173.09:29:02.35#ibcon#read 3, iclass 7, count 2 2006.173.09:29:02.35#ibcon#about to read 4, iclass 7, count 2 2006.173.09:29:02.35#ibcon#read 4, iclass 7, count 2 2006.173.09:29:02.35#ibcon#about to read 5, iclass 7, count 2 2006.173.09:29:02.35#ibcon#read 5, iclass 7, count 2 2006.173.09:29:02.35#ibcon#about to read 6, iclass 7, count 2 2006.173.09:29:02.35#ibcon#read 6, iclass 7, count 2 2006.173.09:29:02.35#ibcon#end of sib2, iclass 7, count 2 2006.173.09:29:02.35#ibcon#*after write, iclass 7, count 2 2006.173.09:29:02.35#ibcon#*before return 0, iclass 7, count 2 2006.173.09:29:02.35#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.09:29:02.35#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.173.09:29:02.35#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.173.09:29:02.35#ibcon#ireg 7 cls_cnt 0 2006.173.09:29:02.35#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.09:29:02.47#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.09:29:02.47#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.09:29:02.47#ibcon#enter wrdev, iclass 7, count 0 2006.173.09:29:02.47#ibcon#first serial, iclass 7, count 0 2006.173.09:29:02.47#ibcon#enter sib2, iclass 7, count 0 2006.173.09:29:02.47#ibcon#flushed, iclass 7, count 0 2006.173.09:29:02.47#ibcon#about to write, iclass 7, count 0 2006.173.09:29:02.47#ibcon#wrote, iclass 7, count 0 2006.173.09:29:02.47#ibcon#about to read 3, iclass 7, count 0 2006.173.09:29:02.49#ibcon#read 3, iclass 7, count 0 2006.173.09:29:02.49#ibcon#about to read 4, iclass 7, count 0 2006.173.09:29:02.49#ibcon#read 4, iclass 7, count 0 2006.173.09:29:02.49#ibcon#about to read 5, iclass 7, count 0 2006.173.09:29:02.49#ibcon#read 5, iclass 7, count 0 2006.173.09:29:02.49#ibcon#about to read 6, iclass 7, count 0 2006.173.09:29:02.49#ibcon#read 6, iclass 7, count 0 2006.173.09:29:02.49#ibcon#end of sib2, iclass 7, count 0 2006.173.09:29:02.49#ibcon#*mode == 0, iclass 7, count 0 2006.173.09:29:02.49#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.09:29:02.49#ibcon#[27=USB\r\n] 2006.173.09:29:02.49#ibcon#*before write, iclass 7, count 0 2006.173.09:29:02.49#ibcon#enter sib2, iclass 7, count 0 2006.173.09:29:02.49#ibcon#flushed, iclass 7, count 0 2006.173.09:29:02.49#ibcon#about to write, iclass 7, count 0 2006.173.09:29:02.49#ibcon#wrote, iclass 7, count 0 2006.173.09:29:02.49#ibcon#about to read 3, iclass 7, count 0 2006.173.09:29:02.52#ibcon#read 3, iclass 7, count 0 2006.173.09:29:02.52#ibcon#about to read 4, iclass 7, count 0 2006.173.09:29:02.52#ibcon#read 4, iclass 7, count 0 2006.173.09:29:02.52#ibcon#about to read 5, iclass 7, count 0 2006.173.09:29:02.52#ibcon#read 5, iclass 7, count 0 2006.173.09:29:02.52#ibcon#about to read 6, iclass 7, count 0 2006.173.09:29:02.52#ibcon#read 6, iclass 7, count 0 2006.173.09:29:02.52#ibcon#end of sib2, iclass 7, count 0 2006.173.09:29:02.52#ibcon#*after write, iclass 7, count 0 2006.173.09:29:02.52#ibcon#*before return 0, iclass 7, count 0 2006.173.09:29:02.52#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.09:29:02.52#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.173.09:29:02.52#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.09:29:02.52#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.09:29:02.52$vck44/vblo=3,649.99 2006.173.09:29:02.52#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.09:29:02.52#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.09:29:02.52#ibcon#ireg 17 cls_cnt 0 2006.173.09:29:02.52#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.09:29:02.52#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.09:29:02.52#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.09:29:02.52#ibcon#enter wrdev, iclass 11, count 0 2006.173.09:29:02.52#ibcon#first serial, iclass 11, count 0 2006.173.09:29:02.52#ibcon#enter sib2, iclass 11, count 0 2006.173.09:29:02.52#ibcon#flushed, iclass 11, count 0 2006.173.09:29:02.52#ibcon#about to write, iclass 11, count 0 2006.173.09:29:02.52#ibcon#wrote, iclass 11, count 0 2006.173.09:29:02.52#ibcon#about to read 3, iclass 11, count 0 2006.173.09:29:02.54#ibcon#read 3, iclass 11, count 0 2006.173.09:29:02.54#ibcon#about to read 4, iclass 11, count 0 2006.173.09:29:02.54#ibcon#read 4, iclass 11, count 0 2006.173.09:29:02.54#ibcon#about to read 5, iclass 11, count 0 2006.173.09:29:02.54#ibcon#read 5, iclass 11, count 0 2006.173.09:29:02.54#ibcon#about to read 6, iclass 11, count 0 2006.173.09:29:02.54#ibcon#read 6, iclass 11, count 0 2006.173.09:29:02.54#ibcon#end of sib2, iclass 11, count 0 2006.173.09:29:02.54#ibcon#*mode == 0, iclass 11, count 0 2006.173.09:29:02.54#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.09:29:02.54#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.09:29:02.54#ibcon#*before write, iclass 11, count 0 2006.173.09:29:02.54#ibcon#enter sib2, iclass 11, count 0 2006.173.09:29:02.54#ibcon#flushed, iclass 11, count 0 2006.173.09:29:02.54#ibcon#about to write, iclass 11, count 0 2006.173.09:29:02.54#ibcon#wrote, iclass 11, count 0 2006.173.09:29:02.54#ibcon#about to read 3, iclass 11, count 0 2006.173.09:29:02.58#ibcon#read 3, iclass 11, count 0 2006.173.09:29:02.58#ibcon#about to read 4, iclass 11, count 0 2006.173.09:29:02.58#ibcon#read 4, iclass 11, count 0 2006.173.09:29:02.58#ibcon#about to read 5, iclass 11, count 0 2006.173.09:29:02.58#ibcon#read 5, iclass 11, count 0 2006.173.09:29:02.58#ibcon#about to read 6, iclass 11, count 0 2006.173.09:29:02.58#ibcon#read 6, iclass 11, count 0 2006.173.09:29:02.58#ibcon#end of sib2, iclass 11, count 0 2006.173.09:29:02.58#ibcon#*after write, iclass 11, count 0 2006.173.09:29:02.58#ibcon#*before return 0, iclass 11, count 0 2006.173.09:29:02.58#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.09:29:02.58#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.09:29:02.58#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.09:29:02.58#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.09:29:02.58$vck44/vb=3,4 2006.173.09:29:02.58#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.173.09:29:02.58#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.173.09:29:02.58#ibcon#ireg 11 cls_cnt 2 2006.173.09:29:02.58#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.09:29:02.64#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.09:29:02.64#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.09:29:02.64#ibcon#enter wrdev, iclass 13, count 2 2006.173.09:29:02.64#ibcon#first serial, iclass 13, count 2 2006.173.09:29:02.64#ibcon#enter sib2, iclass 13, count 2 2006.173.09:29:02.64#ibcon#flushed, iclass 13, count 2 2006.173.09:29:02.64#ibcon#about to write, iclass 13, count 2 2006.173.09:29:02.64#ibcon#wrote, iclass 13, count 2 2006.173.09:29:02.64#ibcon#about to read 3, iclass 13, count 2 2006.173.09:29:02.66#ibcon#read 3, iclass 13, count 2 2006.173.09:29:02.66#ibcon#about to read 4, iclass 13, count 2 2006.173.09:29:02.66#ibcon#read 4, iclass 13, count 2 2006.173.09:29:02.66#ibcon#about to read 5, iclass 13, count 2 2006.173.09:29:02.66#ibcon#read 5, iclass 13, count 2 2006.173.09:29:02.66#ibcon#about to read 6, iclass 13, count 2 2006.173.09:29:02.66#ibcon#read 6, iclass 13, count 2 2006.173.09:29:02.66#ibcon#end of sib2, iclass 13, count 2 2006.173.09:29:02.66#ibcon#*mode == 0, iclass 13, count 2 2006.173.09:29:02.66#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.173.09:29:02.66#ibcon#[27=AT03-04\r\n] 2006.173.09:29:02.66#ibcon#*before write, iclass 13, count 2 2006.173.09:29:02.66#ibcon#enter sib2, iclass 13, count 2 2006.173.09:29:02.66#ibcon#flushed, iclass 13, count 2 2006.173.09:29:02.66#ibcon#about to write, iclass 13, count 2 2006.173.09:29:02.66#ibcon#wrote, iclass 13, count 2 2006.173.09:29:02.66#ibcon#about to read 3, iclass 13, count 2 2006.173.09:29:02.69#ibcon#read 3, iclass 13, count 2 2006.173.09:29:02.69#ibcon#about to read 4, iclass 13, count 2 2006.173.09:29:02.69#ibcon#read 4, iclass 13, count 2 2006.173.09:29:02.69#ibcon#about to read 5, iclass 13, count 2 2006.173.09:29:02.69#ibcon#read 5, iclass 13, count 2 2006.173.09:29:02.69#ibcon#about to read 6, iclass 13, count 2 2006.173.09:29:02.69#ibcon#read 6, iclass 13, count 2 2006.173.09:29:02.69#ibcon#end of sib2, iclass 13, count 2 2006.173.09:29:02.69#ibcon#*after write, iclass 13, count 2 2006.173.09:29:02.69#ibcon#*before return 0, iclass 13, count 2 2006.173.09:29:02.69#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.09:29:02.69#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.173.09:29:02.69#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.173.09:29:02.69#ibcon#ireg 7 cls_cnt 0 2006.173.09:29:02.69#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.09:29:02.81#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.09:29:02.81#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.09:29:02.81#ibcon#enter wrdev, iclass 13, count 0 2006.173.09:29:02.81#ibcon#first serial, iclass 13, count 0 2006.173.09:29:02.81#ibcon#enter sib2, iclass 13, count 0 2006.173.09:29:02.81#ibcon#flushed, iclass 13, count 0 2006.173.09:29:02.81#ibcon#about to write, iclass 13, count 0 2006.173.09:29:02.81#ibcon#wrote, iclass 13, count 0 2006.173.09:29:02.81#ibcon#about to read 3, iclass 13, count 0 2006.173.09:29:02.83#ibcon#read 3, iclass 13, count 0 2006.173.09:29:02.83#ibcon#about to read 4, iclass 13, count 0 2006.173.09:29:02.83#ibcon#read 4, iclass 13, count 0 2006.173.09:29:02.83#ibcon#about to read 5, iclass 13, count 0 2006.173.09:29:02.83#ibcon#read 5, iclass 13, count 0 2006.173.09:29:02.83#ibcon#about to read 6, iclass 13, count 0 2006.173.09:29:02.83#ibcon#read 6, iclass 13, count 0 2006.173.09:29:02.83#ibcon#end of sib2, iclass 13, count 0 2006.173.09:29:02.83#ibcon#*mode == 0, iclass 13, count 0 2006.173.09:29:02.83#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.09:29:02.83#ibcon#[27=USB\r\n] 2006.173.09:29:02.83#ibcon#*before write, iclass 13, count 0 2006.173.09:29:02.83#ibcon#enter sib2, iclass 13, count 0 2006.173.09:29:02.83#ibcon#flushed, iclass 13, count 0 2006.173.09:29:02.83#ibcon#about to write, iclass 13, count 0 2006.173.09:29:02.83#ibcon#wrote, iclass 13, count 0 2006.173.09:29:02.83#ibcon#about to read 3, iclass 13, count 0 2006.173.09:29:02.86#ibcon#read 3, iclass 13, count 0 2006.173.09:29:02.86#ibcon#about to read 4, iclass 13, count 0 2006.173.09:29:02.86#ibcon#read 4, iclass 13, count 0 2006.173.09:29:02.86#ibcon#about to read 5, iclass 13, count 0 2006.173.09:29:02.86#ibcon#read 5, iclass 13, count 0 2006.173.09:29:02.86#ibcon#about to read 6, iclass 13, count 0 2006.173.09:29:02.86#ibcon#read 6, iclass 13, count 0 2006.173.09:29:02.86#ibcon#end of sib2, iclass 13, count 0 2006.173.09:29:02.86#ibcon#*after write, iclass 13, count 0 2006.173.09:29:02.86#ibcon#*before return 0, iclass 13, count 0 2006.173.09:29:02.86#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.09:29:02.86#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.173.09:29:02.86#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.09:29:02.86#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.09:29:02.86$vck44/vblo=4,679.99 2006.173.09:29:02.86#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.09:29:02.86#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.09:29:02.86#ibcon#ireg 17 cls_cnt 0 2006.173.09:29:02.86#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.09:29:02.86#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.09:29:02.86#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.09:29:02.86#ibcon#enter wrdev, iclass 15, count 0 2006.173.09:29:02.86#ibcon#first serial, iclass 15, count 0 2006.173.09:29:02.86#ibcon#enter sib2, iclass 15, count 0 2006.173.09:29:02.86#ibcon#flushed, iclass 15, count 0 2006.173.09:29:02.86#ibcon#about to write, iclass 15, count 0 2006.173.09:29:02.86#ibcon#wrote, iclass 15, count 0 2006.173.09:29:02.86#ibcon#about to read 3, iclass 15, count 0 2006.173.09:29:02.88#ibcon#read 3, iclass 15, count 0 2006.173.09:29:02.88#ibcon#about to read 4, iclass 15, count 0 2006.173.09:29:02.88#ibcon#read 4, iclass 15, count 0 2006.173.09:29:02.88#ibcon#about to read 5, iclass 15, count 0 2006.173.09:29:02.88#ibcon#read 5, iclass 15, count 0 2006.173.09:29:02.88#ibcon#about to read 6, iclass 15, count 0 2006.173.09:29:02.88#ibcon#read 6, iclass 15, count 0 2006.173.09:29:02.88#ibcon#end of sib2, iclass 15, count 0 2006.173.09:29:02.88#ibcon#*mode == 0, iclass 15, count 0 2006.173.09:29:02.88#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.09:29:02.88#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.09:29:02.88#ibcon#*before write, iclass 15, count 0 2006.173.09:29:02.88#ibcon#enter sib2, iclass 15, count 0 2006.173.09:29:02.88#ibcon#flushed, iclass 15, count 0 2006.173.09:29:02.88#ibcon#about to write, iclass 15, count 0 2006.173.09:29:02.88#ibcon#wrote, iclass 15, count 0 2006.173.09:29:02.88#ibcon#about to read 3, iclass 15, count 0 2006.173.09:29:02.92#ibcon#read 3, iclass 15, count 0 2006.173.09:29:02.92#ibcon#about to read 4, iclass 15, count 0 2006.173.09:29:02.92#ibcon#read 4, iclass 15, count 0 2006.173.09:29:02.92#ibcon#about to read 5, iclass 15, count 0 2006.173.09:29:02.92#ibcon#read 5, iclass 15, count 0 2006.173.09:29:02.92#ibcon#about to read 6, iclass 15, count 0 2006.173.09:29:02.92#ibcon#read 6, iclass 15, count 0 2006.173.09:29:02.92#ibcon#end of sib2, iclass 15, count 0 2006.173.09:29:02.92#ibcon#*after write, iclass 15, count 0 2006.173.09:29:02.92#ibcon#*before return 0, iclass 15, count 0 2006.173.09:29:02.92#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.09:29:02.92#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.09:29:02.92#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.09:29:02.92#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.09:29:02.92$vck44/vb=4,4 2006.173.09:29:02.92#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.09:29:02.92#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.09:29:02.92#ibcon#ireg 11 cls_cnt 2 2006.173.09:29:02.92#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.09:29:02.98#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.09:29:02.98#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.09:29:02.98#ibcon#enter wrdev, iclass 17, count 2 2006.173.09:29:02.98#ibcon#first serial, iclass 17, count 2 2006.173.09:29:02.98#ibcon#enter sib2, iclass 17, count 2 2006.173.09:29:02.98#ibcon#flushed, iclass 17, count 2 2006.173.09:29:02.98#ibcon#about to write, iclass 17, count 2 2006.173.09:29:02.98#ibcon#wrote, iclass 17, count 2 2006.173.09:29:02.98#ibcon#about to read 3, iclass 17, count 2 2006.173.09:29:03.00#ibcon#read 3, iclass 17, count 2 2006.173.09:29:03.00#ibcon#about to read 4, iclass 17, count 2 2006.173.09:29:03.00#ibcon#read 4, iclass 17, count 2 2006.173.09:29:03.00#ibcon#about to read 5, iclass 17, count 2 2006.173.09:29:03.00#ibcon#read 5, iclass 17, count 2 2006.173.09:29:03.00#ibcon#about to read 6, iclass 17, count 2 2006.173.09:29:03.00#ibcon#read 6, iclass 17, count 2 2006.173.09:29:03.00#ibcon#end of sib2, iclass 17, count 2 2006.173.09:29:03.00#ibcon#*mode == 0, iclass 17, count 2 2006.173.09:29:03.00#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.09:29:03.00#ibcon#[27=AT04-04\r\n] 2006.173.09:29:03.00#ibcon#*before write, iclass 17, count 2 2006.173.09:29:03.00#ibcon#enter sib2, iclass 17, count 2 2006.173.09:29:03.00#ibcon#flushed, iclass 17, count 2 2006.173.09:29:03.00#ibcon#about to write, iclass 17, count 2 2006.173.09:29:03.00#ibcon#wrote, iclass 17, count 2 2006.173.09:29:03.00#ibcon#about to read 3, iclass 17, count 2 2006.173.09:29:03.03#ibcon#read 3, iclass 17, count 2 2006.173.09:29:03.03#ibcon#about to read 4, iclass 17, count 2 2006.173.09:29:03.03#ibcon#read 4, iclass 17, count 2 2006.173.09:29:03.03#ibcon#about to read 5, iclass 17, count 2 2006.173.09:29:03.03#ibcon#read 5, iclass 17, count 2 2006.173.09:29:03.03#ibcon#about to read 6, iclass 17, count 2 2006.173.09:29:03.03#ibcon#read 6, iclass 17, count 2 2006.173.09:29:03.03#ibcon#end of sib2, iclass 17, count 2 2006.173.09:29:03.03#ibcon#*after write, iclass 17, count 2 2006.173.09:29:03.03#ibcon#*before return 0, iclass 17, count 2 2006.173.09:29:03.03#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.09:29:03.03#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.09:29:03.03#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.09:29:03.03#ibcon#ireg 7 cls_cnt 0 2006.173.09:29:03.03#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.09:29:03.15#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.09:29:03.15#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.09:29:03.15#ibcon#enter wrdev, iclass 17, count 0 2006.173.09:29:03.15#ibcon#first serial, iclass 17, count 0 2006.173.09:29:03.15#ibcon#enter sib2, iclass 17, count 0 2006.173.09:29:03.15#ibcon#flushed, iclass 17, count 0 2006.173.09:29:03.15#ibcon#about to write, iclass 17, count 0 2006.173.09:29:03.15#ibcon#wrote, iclass 17, count 0 2006.173.09:29:03.15#ibcon#about to read 3, iclass 17, count 0 2006.173.09:29:03.17#ibcon#read 3, iclass 17, count 0 2006.173.09:29:03.17#ibcon#about to read 4, iclass 17, count 0 2006.173.09:29:03.17#ibcon#read 4, iclass 17, count 0 2006.173.09:29:03.17#ibcon#about to read 5, iclass 17, count 0 2006.173.09:29:03.17#ibcon#read 5, iclass 17, count 0 2006.173.09:29:03.17#ibcon#about to read 6, iclass 17, count 0 2006.173.09:29:03.17#ibcon#read 6, iclass 17, count 0 2006.173.09:29:03.17#ibcon#end of sib2, iclass 17, count 0 2006.173.09:29:03.17#ibcon#*mode == 0, iclass 17, count 0 2006.173.09:29:03.17#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.09:29:03.17#ibcon#[27=USB\r\n] 2006.173.09:29:03.17#ibcon#*before write, iclass 17, count 0 2006.173.09:29:03.17#ibcon#enter sib2, iclass 17, count 0 2006.173.09:29:03.17#ibcon#flushed, iclass 17, count 0 2006.173.09:29:03.17#ibcon#about to write, iclass 17, count 0 2006.173.09:29:03.17#ibcon#wrote, iclass 17, count 0 2006.173.09:29:03.17#ibcon#about to read 3, iclass 17, count 0 2006.173.09:29:03.20#ibcon#read 3, iclass 17, count 0 2006.173.09:29:03.20#ibcon#about to read 4, iclass 17, count 0 2006.173.09:29:03.20#ibcon#read 4, iclass 17, count 0 2006.173.09:29:03.20#ibcon#about to read 5, iclass 17, count 0 2006.173.09:29:03.20#ibcon#read 5, iclass 17, count 0 2006.173.09:29:03.20#ibcon#about to read 6, iclass 17, count 0 2006.173.09:29:03.20#ibcon#read 6, iclass 17, count 0 2006.173.09:29:03.20#ibcon#end of sib2, iclass 17, count 0 2006.173.09:29:03.20#ibcon#*after write, iclass 17, count 0 2006.173.09:29:03.20#ibcon#*before return 0, iclass 17, count 0 2006.173.09:29:03.20#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.09:29:03.20#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.09:29:03.20#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.09:29:03.20#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.09:29:03.20$vck44/vblo=5,709.99 2006.173.09:29:03.20#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.09:29:03.20#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.09:29:03.20#ibcon#ireg 17 cls_cnt 0 2006.173.09:29:03.20#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.09:29:03.20#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.09:29:03.20#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.09:29:03.20#ibcon#enter wrdev, iclass 19, count 0 2006.173.09:29:03.20#ibcon#first serial, iclass 19, count 0 2006.173.09:29:03.20#ibcon#enter sib2, iclass 19, count 0 2006.173.09:29:03.20#ibcon#flushed, iclass 19, count 0 2006.173.09:29:03.20#ibcon#about to write, iclass 19, count 0 2006.173.09:29:03.20#ibcon#wrote, iclass 19, count 0 2006.173.09:29:03.20#ibcon#about to read 3, iclass 19, count 0 2006.173.09:29:03.22#ibcon#read 3, iclass 19, count 0 2006.173.09:29:03.22#ibcon#about to read 4, iclass 19, count 0 2006.173.09:29:03.22#ibcon#read 4, iclass 19, count 0 2006.173.09:29:03.22#ibcon#about to read 5, iclass 19, count 0 2006.173.09:29:03.22#ibcon#read 5, iclass 19, count 0 2006.173.09:29:03.22#ibcon#about to read 6, iclass 19, count 0 2006.173.09:29:03.22#ibcon#read 6, iclass 19, count 0 2006.173.09:29:03.22#ibcon#end of sib2, iclass 19, count 0 2006.173.09:29:03.22#ibcon#*mode == 0, iclass 19, count 0 2006.173.09:29:03.22#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.09:29:03.22#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.09:29:03.22#ibcon#*before write, iclass 19, count 0 2006.173.09:29:03.22#ibcon#enter sib2, iclass 19, count 0 2006.173.09:29:03.22#ibcon#flushed, iclass 19, count 0 2006.173.09:29:03.22#ibcon#about to write, iclass 19, count 0 2006.173.09:29:03.22#ibcon#wrote, iclass 19, count 0 2006.173.09:29:03.22#ibcon#about to read 3, iclass 19, count 0 2006.173.09:29:03.26#ibcon#read 3, iclass 19, count 0 2006.173.09:29:03.26#ibcon#about to read 4, iclass 19, count 0 2006.173.09:29:03.26#ibcon#read 4, iclass 19, count 0 2006.173.09:29:03.26#ibcon#about to read 5, iclass 19, count 0 2006.173.09:29:03.26#ibcon#read 5, iclass 19, count 0 2006.173.09:29:03.26#ibcon#about to read 6, iclass 19, count 0 2006.173.09:29:03.26#ibcon#read 6, iclass 19, count 0 2006.173.09:29:03.26#ibcon#end of sib2, iclass 19, count 0 2006.173.09:29:03.26#ibcon#*after write, iclass 19, count 0 2006.173.09:29:03.26#ibcon#*before return 0, iclass 19, count 0 2006.173.09:29:03.26#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.09:29:03.26#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.09:29:03.26#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.09:29:03.26#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.09:29:03.26$vck44/vb=5,4 2006.173.09:29:03.26#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.09:29:03.26#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.09:29:03.26#ibcon#ireg 11 cls_cnt 2 2006.173.09:29:03.26#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.09:29:03.32#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.09:29:03.32#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.09:29:03.32#ibcon#enter wrdev, iclass 21, count 2 2006.173.09:29:03.32#ibcon#first serial, iclass 21, count 2 2006.173.09:29:03.32#ibcon#enter sib2, iclass 21, count 2 2006.173.09:29:03.32#ibcon#flushed, iclass 21, count 2 2006.173.09:29:03.32#ibcon#about to write, iclass 21, count 2 2006.173.09:29:03.32#ibcon#wrote, iclass 21, count 2 2006.173.09:29:03.32#ibcon#about to read 3, iclass 21, count 2 2006.173.09:29:03.34#ibcon#read 3, iclass 21, count 2 2006.173.09:29:03.34#ibcon#about to read 4, iclass 21, count 2 2006.173.09:29:03.34#ibcon#read 4, iclass 21, count 2 2006.173.09:29:03.34#ibcon#about to read 5, iclass 21, count 2 2006.173.09:29:03.34#ibcon#read 5, iclass 21, count 2 2006.173.09:29:03.34#ibcon#about to read 6, iclass 21, count 2 2006.173.09:29:03.34#ibcon#read 6, iclass 21, count 2 2006.173.09:29:03.34#ibcon#end of sib2, iclass 21, count 2 2006.173.09:29:03.34#ibcon#*mode == 0, iclass 21, count 2 2006.173.09:29:03.34#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.09:29:03.34#ibcon#[27=AT05-04\r\n] 2006.173.09:29:03.34#ibcon#*before write, iclass 21, count 2 2006.173.09:29:03.34#ibcon#enter sib2, iclass 21, count 2 2006.173.09:29:03.34#ibcon#flushed, iclass 21, count 2 2006.173.09:29:03.34#ibcon#about to write, iclass 21, count 2 2006.173.09:29:03.34#ibcon#wrote, iclass 21, count 2 2006.173.09:29:03.34#ibcon#about to read 3, iclass 21, count 2 2006.173.09:29:03.37#ibcon#read 3, iclass 21, count 2 2006.173.09:29:03.37#ibcon#about to read 4, iclass 21, count 2 2006.173.09:29:03.37#ibcon#read 4, iclass 21, count 2 2006.173.09:29:03.37#ibcon#about to read 5, iclass 21, count 2 2006.173.09:29:03.37#ibcon#read 5, iclass 21, count 2 2006.173.09:29:03.37#ibcon#about to read 6, iclass 21, count 2 2006.173.09:29:03.37#ibcon#read 6, iclass 21, count 2 2006.173.09:29:03.37#ibcon#end of sib2, iclass 21, count 2 2006.173.09:29:03.37#ibcon#*after write, iclass 21, count 2 2006.173.09:29:03.37#ibcon#*before return 0, iclass 21, count 2 2006.173.09:29:03.37#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.09:29:03.37#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.09:29:03.37#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.09:29:03.37#ibcon#ireg 7 cls_cnt 0 2006.173.09:29:03.37#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.09:29:03.49#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.09:29:03.49#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.09:29:03.49#ibcon#enter wrdev, iclass 21, count 0 2006.173.09:29:03.49#ibcon#first serial, iclass 21, count 0 2006.173.09:29:03.49#ibcon#enter sib2, iclass 21, count 0 2006.173.09:29:03.49#ibcon#flushed, iclass 21, count 0 2006.173.09:29:03.49#ibcon#about to write, iclass 21, count 0 2006.173.09:29:03.49#ibcon#wrote, iclass 21, count 0 2006.173.09:29:03.49#ibcon#about to read 3, iclass 21, count 0 2006.173.09:29:03.51#ibcon#read 3, iclass 21, count 0 2006.173.09:29:03.51#ibcon#about to read 4, iclass 21, count 0 2006.173.09:29:03.51#ibcon#read 4, iclass 21, count 0 2006.173.09:29:03.51#ibcon#about to read 5, iclass 21, count 0 2006.173.09:29:03.51#ibcon#read 5, iclass 21, count 0 2006.173.09:29:03.51#ibcon#about to read 6, iclass 21, count 0 2006.173.09:29:03.51#ibcon#read 6, iclass 21, count 0 2006.173.09:29:03.51#ibcon#end of sib2, iclass 21, count 0 2006.173.09:29:03.51#ibcon#*mode == 0, iclass 21, count 0 2006.173.09:29:03.51#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.09:29:03.51#ibcon#[27=USB\r\n] 2006.173.09:29:03.51#ibcon#*before write, iclass 21, count 0 2006.173.09:29:03.51#ibcon#enter sib2, iclass 21, count 0 2006.173.09:29:03.51#ibcon#flushed, iclass 21, count 0 2006.173.09:29:03.51#ibcon#about to write, iclass 21, count 0 2006.173.09:29:03.51#ibcon#wrote, iclass 21, count 0 2006.173.09:29:03.51#ibcon#about to read 3, iclass 21, count 0 2006.173.09:29:03.54#ibcon#read 3, iclass 21, count 0 2006.173.09:29:03.54#ibcon#about to read 4, iclass 21, count 0 2006.173.09:29:03.54#ibcon#read 4, iclass 21, count 0 2006.173.09:29:03.54#ibcon#about to read 5, iclass 21, count 0 2006.173.09:29:03.54#ibcon#read 5, iclass 21, count 0 2006.173.09:29:03.54#ibcon#about to read 6, iclass 21, count 0 2006.173.09:29:03.54#ibcon#read 6, iclass 21, count 0 2006.173.09:29:03.54#ibcon#end of sib2, iclass 21, count 0 2006.173.09:29:03.54#ibcon#*after write, iclass 21, count 0 2006.173.09:29:03.54#ibcon#*before return 0, iclass 21, count 0 2006.173.09:29:03.54#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.09:29:03.54#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.09:29:03.54#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.09:29:03.54#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.09:29:03.54$vck44/vblo=6,719.99 2006.173.09:29:03.54#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.09:29:03.54#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.09:29:03.54#ibcon#ireg 17 cls_cnt 0 2006.173.09:29:03.54#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.09:29:03.54#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.09:29:03.54#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.09:29:03.54#ibcon#enter wrdev, iclass 23, count 0 2006.173.09:29:03.54#ibcon#first serial, iclass 23, count 0 2006.173.09:29:03.54#ibcon#enter sib2, iclass 23, count 0 2006.173.09:29:03.54#ibcon#flushed, iclass 23, count 0 2006.173.09:29:03.54#ibcon#about to write, iclass 23, count 0 2006.173.09:29:03.54#ibcon#wrote, iclass 23, count 0 2006.173.09:29:03.54#ibcon#about to read 3, iclass 23, count 0 2006.173.09:29:03.56#ibcon#read 3, iclass 23, count 0 2006.173.09:29:03.56#ibcon#about to read 4, iclass 23, count 0 2006.173.09:29:03.56#ibcon#read 4, iclass 23, count 0 2006.173.09:29:03.56#ibcon#about to read 5, iclass 23, count 0 2006.173.09:29:03.56#ibcon#read 5, iclass 23, count 0 2006.173.09:29:03.56#ibcon#about to read 6, iclass 23, count 0 2006.173.09:29:03.56#ibcon#read 6, iclass 23, count 0 2006.173.09:29:03.56#ibcon#end of sib2, iclass 23, count 0 2006.173.09:29:03.56#ibcon#*mode == 0, iclass 23, count 0 2006.173.09:29:03.56#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.09:29:03.56#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.09:29:03.56#ibcon#*before write, iclass 23, count 0 2006.173.09:29:03.56#ibcon#enter sib2, iclass 23, count 0 2006.173.09:29:03.56#ibcon#flushed, iclass 23, count 0 2006.173.09:29:03.56#ibcon#about to write, iclass 23, count 0 2006.173.09:29:03.56#ibcon#wrote, iclass 23, count 0 2006.173.09:29:03.56#ibcon#about to read 3, iclass 23, count 0 2006.173.09:29:03.60#ibcon#read 3, iclass 23, count 0 2006.173.09:29:03.60#ibcon#about to read 4, iclass 23, count 0 2006.173.09:29:03.60#ibcon#read 4, iclass 23, count 0 2006.173.09:29:03.60#ibcon#about to read 5, iclass 23, count 0 2006.173.09:29:03.60#ibcon#read 5, iclass 23, count 0 2006.173.09:29:03.60#ibcon#about to read 6, iclass 23, count 0 2006.173.09:29:03.60#ibcon#read 6, iclass 23, count 0 2006.173.09:29:03.60#ibcon#end of sib2, iclass 23, count 0 2006.173.09:29:03.60#ibcon#*after write, iclass 23, count 0 2006.173.09:29:03.60#ibcon#*before return 0, iclass 23, count 0 2006.173.09:29:03.60#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.09:29:03.60#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.09:29:03.60#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.09:29:03.60#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.09:29:03.60$vck44/vb=6,4 2006.173.09:29:03.60#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.09:29:03.60#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.09:29:03.60#ibcon#ireg 11 cls_cnt 2 2006.173.09:29:03.60#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.09:29:03.66#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.09:29:03.66#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.09:29:03.66#ibcon#enter wrdev, iclass 25, count 2 2006.173.09:29:03.66#ibcon#first serial, iclass 25, count 2 2006.173.09:29:03.66#ibcon#enter sib2, iclass 25, count 2 2006.173.09:29:03.66#ibcon#flushed, iclass 25, count 2 2006.173.09:29:03.66#ibcon#about to write, iclass 25, count 2 2006.173.09:29:03.66#ibcon#wrote, iclass 25, count 2 2006.173.09:29:03.66#ibcon#about to read 3, iclass 25, count 2 2006.173.09:29:03.68#ibcon#read 3, iclass 25, count 2 2006.173.09:29:03.68#ibcon#about to read 4, iclass 25, count 2 2006.173.09:29:03.68#ibcon#read 4, iclass 25, count 2 2006.173.09:29:03.68#ibcon#about to read 5, iclass 25, count 2 2006.173.09:29:03.68#ibcon#read 5, iclass 25, count 2 2006.173.09:29:03.68#ibcon#about to read 6, iclass 25, count 2 2006.173.09:29:03.68#ibcon#read 6, iclass 25, count 2 2006.173.09:29:03.68#ibcon#end of sib2, iclass 25, count 2 2006.173.09:29:03.68#ibcon#*mode == 0, iclass 25, count 2 2006.173.09:29:03.68#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.09:29:03.68#ibcon#[27=AT06-04\r\n] 2006.173.09:29:03.68#ibcon#*before write, iclass 25, count 2 2006.173.09:29:03.68#ibcon#enter sib2, iclass 25, count 2 2006.173.09:29:03.68#ibcon#flushed, iclass 25, count 2 2006.173.09:29:03.68#ibcon#about to write, iclass 25, count 2 2006.173.09:29:03.68#ibcon#wrote, iclass 25, count 2 2006.173.09:29:03.68#ibcon#about to read 3, iclass 25, count 2 2006.173.09:29:03.71#ibcon#read 3, iclass 25, count 2 2006.173.09:29:03.71#ibcon#about to read 4, iclass 25, count 2 2006.173.09:29:03.71#ibcon#read 4, iclass 25, count 2 2006.173.09:29:03.71#ibcon#about to read 5, iclass 25, count 2 2006.173.09:29:03.71#ibcon#read 5, iclass 25, count 2 2006.173.09:29:03.71#ibcon#about to read 6, iclass 25, count 2 2006.173.09:29:03.71#ibcon#read 6, iclass 25, count 2 2006.173.09:29:03.71#ibcon#end of sib2, iclass 25, count 2 2006.173.09:29:03.71#ibcon#*after write, iclass 25, count 2 2006.173.09:29:03.71#ibcon#*before return 0, iclass 25, count 2 2006.173.09:29:03.71#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.09:29:03.71#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.09:29:03.71#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.09:29:03.71#ibcon#ireg 7 cls_cnt 0 2006.173.09:29:03.71#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.09:29:03.83#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.09:29:03.83#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.09:29:03.83#ibcon#enter wrdev, iclass 25, count 0 2006.173.09:29:03.83#ibcon#first serial, iclass 25, count 0 2006.173.09:29:03.83#ibcon#enter sib2, iclass 25, count 0 2006.173.09:29:03.83#ibcon#flushed, iclass 25, count 0 2006.173.09:29:03.83#ibcon#about to write, iclass 25, count 0 2006.173.09:29:03.83#ibcon#wrote, iclass 25, count 0 2006.173.09:29:03.83#ibcon#about to read 3, iclass 25, count 0 2006.173.09:29:03.85#ibcon#read 3, iclass 25, count 0 2006.173.09:29:03.85#ibcon#about to read 4, iclass 25, count 0 2006.173.09:29:03.85#ibcon#read 4, iclass 25, count 0 2006.173.09:29:03.85#ibcon#about to read 5, iclass 25, count 0 2006.173.09:29:03.85#ibcon#read 5, iclass 25, count 0 2006.173.09:29:03.85#ibcon#about to read 6, iclass 25, count 0 2006.173.09:29:03.85#ibcon#read 6, iclass 25, count 0 2006.173.09:29:03.85#ibcon#end of sib2, iclass 25, count 0 2006.173.09:29:03.85#ibcon#*mode == 0, iclass 25, count 0 2006.173.09:29:03.85#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.09:29:03.85#ibcon#[27=USB\r\n] 2006.173.09:29:03.85#ibcon#*before write, iclass 25, count 0 2006.173.09:29:03.85#ibcon#enter sib2, iclass 25, count 0 2006.173.09:29:03.85#ibcon#flushed, iclass 25, count 0 2006.173.09:29:03.85#ibcon#about to write, iclass 25, count 0 2006.173.09:29:03.85#ibcon#wrote, iclass 25, count 0 2006.173.09:29:03.85#ibcon#about to read 3, iclass 25, count 0 2006.173.09:29:03.88#ibcon#read 3, iclass 25, count 0 2006.173.09:29:03.88#ibcon#about to read 4, iclass 25, count 0 2006.173.09:29:03.88#ibcon#read 4, iclass 25, count 0 2006.173.09:29:03.88#ibcon#about to read 5, iclass 25, count 0 2006.173.09:29:03.88#ibcon#read 5, iclass 25, count 0 2006.173.09:29:03.88#ibcon#about to read 6, iclass 25, count 0 2006.173.09:29:03.88#ibcon#read 6, iclass 25, count 0 2006.173.09:29:03.88#ibcon#end of sib2, iclass 25, count 0 2006.173.09:29:03.88#ibcon#*after write, iclass 25, count 0 2006.173.09:29:03.88#ibcon#*before return 0, iclass 25, count 0 2006.173.09:29:03.88#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.09:29:03.88#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.09:29:03.88#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.09:29:03.88#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.09:29:03.88$vck44/vblo=7,734.99 2006.173.09:29:03.88#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.09:29:03.88#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.09:29:03.88#ibcon#ireg 17 cls_cnt 0 2006.173.09:29:03.88#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.09:29:03.88#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.09:29:03.88#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.09:29:03.88#ibcon#enter wrdev, iclass 27, count 0 2006.173.09:29:03.88#ibcon#first serial, iclass 27, count 0 2006.173.09:29:03.88#ibcon#enter sib2, iclass 27, count 0 2006.173.09:29:03.88#ibcon#flushed, iclass 27, count 0 2006.173.09:29:03.88#ibcon#about to write, iclass 27, count 0 2006.173.09:29:03.88#ibcon#wrote, iclass 27, count 0 2006.173.09:29:03.88#ibcon#about to read 3, iclass 27, count 0 2006.173.09:29:03.90#ibcon#read 3, iclass 27, count 0 2006.173.09:29:03.90#ibcon#about to read 4, iclass 27, count 0 2006.173.09:29:03.90#ibcon#read 4, iclass 27, count 0 2006.173.09:29:03.90#ibcon#about to read 5, iclass 27, count 0 2006.173.09:29:03.90#ibcon#read 5, iclass 27, count 0 2006.173.09:29:03.90#ibcon#about to read 6, iclass 27, count 0 2006.173.09:29:03.90#ibcon#read 6, iclass 27, count 0 2006.173.09:29:03.90#ibcon#end of sib2, iclass 27, count 0 2006.173.09:29:03.90#ibcon#*mode == 0, iclass 27, count 0 2006.173.09:29:03.90#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.09:29:03.90#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.09:29:03.90#ibcon#*before write, iclass 27, count 0 2006.173.09:29:03.90#ibcon#enter sib2, iclass 27, count 0 2006.173.09:29:03.90#ibcon#flushed, iclass 27, count 0 2006.173.09:29:03.90#ibcon#about to write, iclass 27, count 0 2006.173.09:29:03.90#ibcon#wrote, iclass 27, count 0 2006.173.09:29:03.90#ibcon#about to read 3, iclass 27, count 0 2006.173.09:29:03.94#ibcon#read 3, iclass 27, count 0 2006.173.09:29:03.94#ibcon#about to read 4, iclass 27, count 0 2006.173.09:29:03.94#ibcon#read 4, iclass 27, count 0 2006.173.09:29:03.94#ibcon#about to read 5, iclass 27, count 0 2006.173.09:29:03.94#ibcon#read 5, iclass 27, count 0 2006.173.09:29:03.94#ibcon#about to read 6, iclass 27, count 0 2006.173.09:29:03.94#ibcon#read 6, iclass 27, count 0 2006.173.09:29:03.94#ibcon#end of sib2, iclass 27, count 0 2006.173.09:29:03.94#ibcon#*after write, iclass 27, count 0 2006.173.09:29:03.94#ibcon#*before return 0, iclass 27, count 0 2006.173.09:29:03.94#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.09:29:03.94#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.09:29:03.94#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.09:29:03.94#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.09:29:03.94$vck44/vb=7,4 2006.173.09:29:03.94#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.09:29:03.94#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.09:29:03.94#ibcon#ireg 11 cls_cnt 2 2006.173.09:29:03.94#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.09:29:04.00#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.09:29:04.00#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.09:29:04.00#ibcon#enter wrdev, iclass 29, count 2 2006.173.09:29:04.00#ibcon#first serial, iclass 29, count 2 2006.173.09:29:04.00#ibcon#enter sib2, iclass 29, count 2 2006.173.09:29:04.00#ibcon#flushed, iclass 29, count 2 2006.173.09:29:04.00#ibcon#about to write, iclass 29, count 2 2006.173.09:29:04.00#ibcon#wrote, iclass 29, count 2 2006.173.09:29:04.00#ibcon#about to read 3, iclass 29, count 2 2006.173.09:29:04.02#ibcon#read 3, iclass 29, count 2 2006.173.09:29:04.02#ibcon#about to read 4, iclass 29, count 2 2006.173.09:29:04.02#ibcon#read 4, iclass 29, count 2 2006.173.09:29:04.02#ibcon#about to read 5, iclass 29, count 2 2006.173.09:29:04.02#ibcon#read 5, iclass 29, count 2 2006.173.09:29:04.02#ibcon#about to read 6, iclass 29, count 2 2006.173.09:29:04.02#ibcon#read 6, iclass 29, count 2 2006.173.09:29:04.02#ibcon#end of sib2, iclass 29, count 2 2006.173.09:29:04.02#ibcon#*mode == 0, iclass 29, count 2 2006.173.09:29:04.02#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.09:29:04.02#ibcon#[27=AT07-04\r\n] 2006.173.09:29:04.02#ibcon#*before write, iclass 29, count 2 2006.173.09:29:04.02#ibcon#enter sib2, iclass 29, count 2 2006.173.09:29:04.02#ibcon#flushed, iclass 29, count 2 2006.173.09:29:04.02#ibcon#about to write, iclass 29, count 2 2006.173.09:29:04.02#ibcon#wrote, iclass 29, count 2 2006.173.09:29:04.02#ibcon#about to read 3, iclass 29, count 2 2006.173.09:29:04.05#ibcon#read 3, iclass 29, count 2 2006.173.09:29:04.05#ibcon#about to read 4, iclass 29, count 2 2006.173.09:29:04.05#ibcon#read 4, iclass 29, count 2 2006.173.09:29:04.05#ibcon#about to read 5, iclass 29, count 2 2006.173.09:29:04.05#ibcon#read 5, iclass 29, count 2 2006.173.09:29:04.05#ibcon#about to read 6, iclass 29, count 2 2006.173.09:29:04.05#ibcon#read 6, iclass 29, count 2 2006.173.09:29:04.05#ibcon#end of sib2, iclass 29, count 2 2006.173.09:29:04.05#ibcon#*after write, iclass 29, count 2 2006.173.09:29:04.05#ibcon#*before return 0, iclass 29, count 2 2006.173.09:29:04.05#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.09:29:04.05#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.09:29:04.05#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.09:29:04.05#ibcon#ireg 7 cls_cnt 0 2006.173.09:29:04.05#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.09:29:04.17#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.09:29:04.17#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.09:29:04.17#ibcon#enter wrdev, iclass 29, count 0 2006.173.09:29:04.17#ibcon#first serial, iclass 29, count 0 2006.173.09:29:04.17#ibcon#enter sib2, iclass 29, count 0 2006.173.09:29:04.17#ibcon#flushed, iclass 29, count 0 2006.173.09:29:04.17#ibcon#about to write, iclass 29, count 0 2006.173.09:29:04.17#ibcon#wrote, iclass 29, count 0 2006.173.09:29:04.17#ibcon#about to read 3, iclass 29, count 0 2006.173.09:29:04.19#ibcon#read 3, iclass 29, count 0 2006.173.09:29:04.19#ibcon#about to read 4, iclass 29, count 0 2006.173.09:29:04.19#ibcon#read 4, iclass 29, count 0 2006.173.09:29:04.19#ibcon#about to read 5, iclass 29, count 0 2006.173.09:29:04.19#ibcon#read 5, iclass 29, count 0 2006.173.09:29:04.19#ibcon#about to read 6, iclass 29, count 0 2006.173.09:29:04.19#ibcon#read 6, iclass 29, count 0 2006.173.09:29:04.19#ibcon#end of sib2, iclass 29, count 0 2006.173.09:29:04.19#ibcon#*mode == 0, iclass 29, count 0 2006.173.09:29:04.19#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.09:29:04.19#ibcon#[27=USB\r\n] 2006.173.09:29:04.19#ibcon#*before write, iclass 29, count 0 2006.173.09:29:04.19#ibcon#enter sib2, iclass 29, count 0 2006.173.09:29:04.19#ibcon#flushed, iclass 29, count 0 2006.173.09:29:04.19#ibcon#about to write, iclass 29, count 0 2006.173.09:29:04.19#ibcon#wrote, iclass 29, count 0 2006.173.09:29:04.19#ibcon#about to read 3, iclass 29, count 0 2006.173.09:29:04.22#ibcon#read 3, iclass 29, count 0 2006.173.09:29:04.22#ibcon#about to read 4, iclass 29, count 0 2006.173.09:29:04.22#ibcon#read 4, iclass 29, count 0 2006.173.09:29:04.22#ibcon#about to read 5, iclass 29, count 0 2006.173.09:29:04.22#ibcon#read 5, iclass 29, count 0 2006.173.09:29:04.22#ibcon#about to read 6, iclass 29, count 0 2006.173.09:29:04.22#ibcon#read 6, iclass 29, count 0 2006.173.09:29:04.22#ibcon#end of sib2, iclass 29, count 0 2006.173.09:29:04.22#ibcon#*after write, iclass 29, count 0 2006.173.09:29:04.22#ibcon#*before return 0, iclass 29, count 0 2006.173.09:29:04.22#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.09:29:04.22#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.09:29:04.22#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.09:29:04.22#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.09:29:04.22$vck44/vblo=8,744.99 2006.173.09:29:04.22#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.09:29:04.22#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.09:29:04.22#ibcon#ireg 17 cls_cnt 0 2006.173.09:29:04.22#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.09:29:04.22#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.09:29:04.22#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.09:29:04.22#ibcon#enter wrdev, iclass 31, count 0 2006.173.09:29:04.22#ibcon#first serial, iclass 31, count 0 2006.173.09:29:04.22#ibcon#enter sib2, iclass 31, count 0 2006.173.09:29:04.22#ibcon#flushed, iclass 31, count 0 2006.173.09:29:04.22#ibcon#about to write, iclass 31, count 0 2006.173.09:29:04.22#ibcon#wrote, iclass 31, count 0 2006.173.09:29:04.22#ibcon#about to read 3, iclass 31, count 0 2006.173.09:29:04.24#ibcon#read 3, iclass 31, count 0 2006.173.09:29:04.24#ibcon#about to read 4, iclass 31, count 0 2006.173.09:29:04.24#ibcon#read 4, iclass 31, count 0 2006.173.09:29:04.24#ibcon#about to read 5, iclass 31, count 0 2006.173.09:29:04.24#ibcon#read 5, iclass 31, count 0 2006.173.09:29:04.24#ibcon#about to read 6, iclass 31, count 0 2006.173.09:29:04.24#ibcon#read 6, iclass 31, count 0 2006.173.09:29:04.24#ibcon#end of sib2, iclass 31, count 0 2006.173.09:29:04.24#ibcon#*mode == 0, iclass 31, count 0 2006.173.09:29:04.24#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.09:29:04.24#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.09:29:04.24#ibcon#*before write, iclass 31, count 0 2006.173.09:29:04.24#ibcon#enter sib2, iclass 31, count 0 2006.173.09:29:04.24#ibcon#flushed, iclass 31, count 0 2006.173.09:29:04.24#ibcon#about to write, iclass 31, count 0 2006.173.09:29:04.24#ibcon#wrote, iclass 31, count 0 2006.173.09:29:04.24#ibcon#about to read 3, iclass 31, count 0 2006.173.09:29:04.28#ibcon#read 3, iclass 31, count 0 2006.173.09:29:04.28#ibcon#about to read 4, iclass 31, count 0 2006.173.09:29:04.28#ibcon#read 4, iclass 31, count 0 2006.173.09:29:04.28#ibcon#about to read 5, iclass 31, count 0 2006.173.09:29:04.28#ibcon#read 5, iclass 31, count 0 2006.173.09:29:04.28#ibcon#about to read 6, iclass 31, count 0 2006.173.09:29:04.28#ibcon#read 6, iclass 31, count 0 2006.173.09:29:04.28#ibcon#end of sib2, iclass 31, count 0 2006.173.09:29:04.28#ibcon#*after write, iclass 31, count 0 2006.173.09:29:04.28#ibcon#*before return 0, iclass 31, count 0 2006.173.09:29:04.28#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.09:29:04.28#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.09:29:04.28#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.09:29:04.28#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.09:29:04.28$vck44/vb=8,4 2006.173.09:29:04.28#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.173.09:29:04.28#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.173.09:29:04.28#ibcon#ireg 11 cls_cnt 2 2006.173.09:29:04.28#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.09:29:04.34#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.09:29:04.34#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.09:29:04.34#ibcon#enter wrdev, iclass 33, count 2 2006.173.09:29:04.34#ibcon#first serial, iclass 33, count 2 2006.173.09:29:04.34#ibcon#enter sib2, iclass 33, count 2 2006.173.09:29:04.34#ibcon#flushed, iclass 33, count 2 2006.173.09:29:04.34#ibcon#about to write, iclass 33, count 2 2006.173.09:29:04.34#ibcon#wrote, iclass 33, count 2 2006.173.09:29:04.34#ibcon#about to read 3, iclass 33, count 2 2006.173.09:29:04.36#ibcon#read 3, iclass 33, count 2 2006.173.09:29:04.36#ibcon#about to read 4, iclass 33, count 2 2006.173.09:29:04.36#ibcon#read 4, iclass 33, count 2 2006.173.09:29:04.36#ibcon#about to read 5, iclass 33, count 2 2006.173.09:29:04.36#ibcon#read 5, iclass 33, count 2 2006.173.09:29:04.36#ibcon#about to read 6, iclass 33, count 2 2006.173.09:29:04.36#ibcon#read 6, iclass 33, count 2 2006.173.09:29:04.36#ibcon#end of sib2, iclass 33, count 2 2006.173.09:29:04.36#ibcon#*mode == 0, iclass 33, count 2 2006.173.09:29:04.36#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.173.09:29:04.36#ibcon#[27=AT08-04\r\n] 2006.173.09:29:04.36#ibcon#*before write, iclass 33, count 2 2006.173.09:29:04.36#ibcon#enter sib2, iclass 33, count 2 2006.173.09:29:04.36#ibcon#flushed, iclass 33, count 2 2006.173.09:29:04.36#ibcon#about to write, iclass 33, count 2 2006.173.09:29:04.36#ibcon#wrote, iclass 33, count 2 2006.173.09:29:04.36#ibcon#about to read 3, iclass 33, count 2 2006.173.09:29:04.39#ibcon#read 3, iclass 33, count 2 2006.173.09:29:04.39#ibcon#about to read 4, iclass 33, count 2 2006.173.09:29:04.39#ibcon#read 4, iclass 33, count 2 2006.173.09:29:04.39#ibcon#about to read 5, iclass 33, count 2 2006.173.09:29:04.39#ibcon#read 5, iclass 33, count 2 2006.173.09:29:04.39#ibcon#about to read 6, iclass 33, count 2 2006.173.09:29:04.39#ibcon#read 6, iclass 33, count 2 2006.173.09:29:04.39#ibcon#end of sib2, iclass 33, count 2 2006.173.09:29:04.39#ibcon#*after write, iclass 33, count 2 2006.173.09:29:04.39#ibcon#*before return 0, iclass 33, count 2 2006.173.09:29:04.39#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.09:29:04.39#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.173.09:29:04.39#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.173.09:29:04.39#ibcon#ireg 7 cls_cnt 0 2006.173.09:29:04.39#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.09:29:04.51#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.09:29:04.51#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.09:29:04.51#ibcon#enter wrdev, iclass 33, count 0 2006.173.09:29:04.51#ibcon#first serial, iclass 33, count 0 2006.173.09:29:04.51#ibcon#enter sib2, iclass 33, count 0 2006.173.09:29:04.51#ibcon#flushed, iclass 33, count 0 2006.173.09:29:04.51#ibcon#about to write, iclass 33, count 0 2006.173.09:29:04.51#ibcon#wrote, iclass 33, count 0 2006.173.09:29:04.51#ibcon#about to read 3, iclass 33, count 0 2006.173.09:29:04.53#ibcon#read 3, iclass 33, count 0 2006.173.09:29:04.53#ibcon#about to read 4, iclass 33, count 0 2006.173.09:29:04.53#ibcon#read 4, iclass 33, count 0 2006.173.09:29:04.53#ibcon#about to read 5, iclass 33, count 0 2006.173.09:29:04.53#ibcon#read 5, iclass 33, count 0 2006.173.09:29:04.53#ibcon#about to read 6, iclass 33, count 0 2006.173.09:29:04.53#ibcon#read 6, iclass 33, count 0 2006.173.09:29:04.53#ibcon#end of sib2, iclass 33, count 0 2006.173.09:29:04.53#ibcon#*mode == 0, iclass 33, count 0 2006.173.09:29:04.53#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.09:29:04.53#ibcon#[27=USB\r\n] 2006.173.09:29:04.53#ibcon#*before write, iclass 33, count 0 2006.173.09:29:04.53#ibcon#enter sib2, iclass 33, count 0 2006.173.09:29:04.53#ibcon#flushed, iclass 33, count 0 2006.173.09:29:04.53#ibcon#about to write, iclass 33, count 0 2006.173.09:29:04.53#ibcon#wrote, iclass 33, count 0 2006.173.09:29:04.53#ibcon#about to read 3, iclass 33, count 0 2006.173.09:29:04.56#ibcon#read 3, iclass 33, count 0 2006.173.09:29:04.56#ibcon#about to read 4, iclass 33, count 0 2006.173.09:29:04.56#ibcon#read 4, iclass 33, count 0 2006.173.09:29:04.56#ibcon#about to read 5, iclass 33, count 0 2006.173.09:29:04.56#ibcon#read 5, iclass 33, count 0 2006.173.09:29:04.56#ibcon#about to read 6, iclass 33, count 0 2006.173.09:29:04.56#ibcon#read 6, iclass 33, count 0 2006.173.09:29:04.56#ibcon#end of sib2, iclass 33, count 0 2006.173.09:29:04.56#ibcon#*after write, iclass 33, count 0 2006.173.09:29:04.56#ibcon#*before return 0, iclass 33, count 0 2006.173.09:29:04.56#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.09:29:04.56#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.173.09:29:04.56#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.09:29:04.56#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.09:29:04.56$vck44/vabw=wide 2006.173.09:29:04.56#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.09:29:04.56#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.09:29:04.56#ibcon#ireg 8 cls_cnt 0 2006.173.09:29:04.56#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.09:29:04.56#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.09:29:04.56#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.09:29:04.56#ibcon#enter wrdev, iclass 35, count 0 2006.173.09:29:04.56#ibcon#first serial, iclass 35, count 0 2006.173.09:29:04.56#ibcon#enter sib2, iclass 35, count 0 2006.173.09:29:04.56#ibcon#flushed, iclass 35, count 0 2006.173.09:29:04.56#ibcon#about to write, iclass 35, count 0 2006.173.09:29:04.56#ibcon#wrote, iclass 35, count 0 2006.173.09:29:04.56#ibcon#about to read 3, iclass 35, count 0 2006.173.09:29:04.58#ibcon#read 3, iclass 35, count 0 2006.173.09:29:04.58#ibcon#about to read 4, iclass 35, count 0 2006.173.09:29:04.58#ibcon#read 4, iclass 35, count 0 2006.173.09:29:04.58#ibcon#about to read 5, iclass 35, count 0 2006.173.09:29:04.58#ibcon#read 5, iclass 35, count 0 2006.173.09:29:04.58#ibcon#about to read 6, iclass 35, count 0 2006.173.09:29:04.58#ibcon#read 6, iclass 35, count 0 2006.173.09:29:04.58#ibcon#end of sib2, iclass 35, count 0 2006.173.09:29:04.58#ibcon#*mode == 0, iclass 35, count 0 2006.173.09:29:04.58#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.09:29:04.58#ibcon#[25=BW32\r\n] 2006.173.09:29:04.58#ibcon#*before write, iclass 35, count 0 2006.173.09:29:04.58#ibcon#enter sib2, iclass 35, count 0 2006.173.09:29:04.58#ibcon#flushed, iclass 35, count 0 2006.173.09:29:04.58#ibcon#about to write, iclass 35, count 0 2006.173.09:29:04.58#ibcon#wrote, iclass 35, count 0 2006.173.09:29:04.58#ibcon#about to read 3, iclass 35, count 0 2006.173.09:29:04.61#ibcon#read 3, iclass 35, count 0 2006.173.09:29:04.61#ibcon#about to read 4, iclass 35, count 0 2006.173.09:29:04.61#ibcon#read 4, iclass 35, count 0 2006.173.09:29:04.61#ibcon#about to read 5, iclass 35, count 0 2006.173.09:29:04.61#ibcon#read 5, iclass 35, count 0 2006.173.09:29:04.61#ibcon#about to read 6, iclass 35, count 0 2006.173.09:29:04.61#ibcon#read 6, iclass 35, count 0 2006.173.09:29:04.61#ibcon#end of sib2, iclass 35, count 0 2006.173.09:29:04.61#ibcon#*after write, iclass 35, count 0 2006.173.09:29:04.61#ibcon#*before return 0, iclass 35, count 0 2006.173.09:29:04.61#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.09:29:04.61#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.09:29:04.61#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.09:29:04.61#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.09:29:04.61$vck44/vbbw=wide 2006.173.09:29:04.61#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.09:29:04.61#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.09:29:04.61#ibcon#ireg 8 cls_cnt 0 2006.173.09:29:04.61#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.09:29:04.68#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.09:29:04.68#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.09:29:04.68#ibcon#enter wrdev, iclass 37, count 0 2006.173.09:29:04.68#ibcon#first serial, iclass 37, count 0 2006.173.09:29:04.68#ibcon#enter sib2, iclass 37, count 0 2006.173.09:29:04.68#ibcon#flushed, iclass 37, count 0 2006.173.09:29:04.68#ibcon#about to write, iclass 37, count 0 2006.173.09:29:04.68#ibcon#wrote, iclass 37, count 0 2006.173.09:29:04.68#ibcon#about to read 3, iclass 37, count 0 2006.173.09:29:04.70#ibcon#read 3, iclass 37, count 0 2006.173.09:29:04.70#ibcon#about to read 4, iclass 37, count 0 2006.173.09:29:04.70#ibcon#read 4, iclass 37, count 0 2006.173.09:29:04.70#ibcon#about to read 5, iclass 37, count 0 2006.173.09:29:04.70#ibcon#read 5, iclass 37, count 0 2006.173.09:29:04.70#ibcon#about to read 6, iclass 37, count 0 2006.173.09:29:04.70#ibcon#read 6, iclass 37, count 0 2006.173.09:29:04.70#ibcon#end of sib2, iclass 37, count 0 2006.173.09:29:04.70#ibcon#*mode == 0, iclass 37, count 0 2006.173.09:29:04.70#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.09:29:04.70#ibcon#[27=BW32\r\n] 2006.173.09:29:04.70#ibcon#*before write, iclass 37, count 0 2006.173.09:29:04.70#ibcon#enter sib2, iclass 37, count 0 2006.173.09:29:04.70#ibcon#flushed, iclass 37, count 0 2006.173.09:29:04.70#ibcon#about to write, iclass 37, count 0 2006.173.09:29:04.70#ibcon#wrote, iclass 37, count 0 2006.173.09:29:04.70#ibcon#about to read 3, iclass 37, count 0 2006.173.09:29:04.73#ibcon#read 3, iclass 37, count 0 2006.173.09:29:04.73#ibcon#about to read 4, iclass 37, count 0 2006.173.09:29:04.73#ibcon#read 4, iclass 37, count 0 2006.173.09:29:04.73#ibcon#about to read 5, iclass 37, count 0 2006.173.09:29:04.73#ibcon#read 5, iclass 37, count 0 2006.173.09:29:04.73#ibcon#about to read 6, iclass 37, count 0 2006.173.09:29:04.73#ibcon#read 6, iclass 37, count 0 2006.173.09:29:04.73#ibcon#end of sib2, iclass 37, count 0 2006.173.09:29:04.73#ibcon#*after write, iclass 37, count 0 2006.173.09:29:04.73#ibcon#*before return 0, iclass 37, count 0 2006.173.09:29:04.73#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.09:29:04.73#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.09:29:04.73#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.09:29:04.73#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.09:29:04.73$setupk4/ifdk4 2006.173.09:29:04.73$ifdk4/lo= 2006.173.09:29:04.73$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.09:29:04.73$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.09:29:04.73$ifdk4/patch= 2006.173.09:29:04.73$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.09:29:04.73$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.09:29:04.73$setupk4/!*+20s 2006.173.09:29:09.17#abcon#<5=/04 0.8 1.5 22.99 871004.3\r\n> 2006.173.09:29:09.19#abcon#{5=INTERFACE CLEAR} 2006.173.09:29:09.25#abcon#[5=S1D000X0/0*\r\n] 2006.173.09:29:19.24$setupk4/"tpicd 2006.173.09:29:19.24$setupk4/echo=off 2006.173.09:29:19.24$setupk4/xlog=off 2006.173.09:29:19.24:!2006.173.09:34:34 2006.173.09:29:25.14#trakl#Source acquired 2006.173.09:29:27.14#flagr#flagr/antenna,acquired 2006.173.09:34:34.00:preob 2006.173.09:34:34.13/onsource/TRACKING 2006.173.09:34:34.13:!2006.173.09:34:44 2006.173.09:34:44.00:"tape 2006.173.09:34:44.00:"st=record 2006.173.09:34:44.00:data_valid=on 2006.173.09:34:44.00:midob 2006.173.09:34:45.13/onsource/TRACKING 2006.173.09:34:45.13/wx/22.89,1004.5,87 2006.173.09:34:45.28/cable/+6.5010E-03 2006.173.09:34:46.37/va/01,07,usb,yes,38,40 2006.173.09:34:46.37/va/02,06,usb,yes,37,38 2006.173.09:34:46.37/va/03,05,usb,yes,48,50 2006.173.09:34:46.37/va/04,06,usb,yes,38,40 2006.173.09:34:46.37/va/05,04,usb,yes,30,31 2006.173.09:34:46.37/va/06,03,usb,yes,42,42 2006.173.09:34:46.37/va/07,04,usb,yes,34,35 2006.173.09:34:46.37/va/08,04,usb,yes,29,35 2006.173.09:34:46.60/valo/01,524.99,yes,locked 2006.173.09:34:46.60/valo/02,534.99,yes,locked 2006.173.09:34:46.60/valo/03,564.99,yes,locked 2006.173.09:34:46.60/valo/04,624.99,yes,locked 2006.173.09:34:46.60/valo/05,734.99,yes,locked 2006.173.09:34:46.60/valo/06,814.99,yes,locked 2006.173.09:34:46.60/valo/07,864.99,yes,locked 2006.173.09:34:46.60/valo/08,884.99,yes,locked 2006.173.09:34:47.69/vb/01,04,usb,yes,30,28 2006.173.09:34:47.69/vb/02,04,usb,yes,33,32 2006.173.09:34:47.69/vb/03,04,usb,yes,30,33 2006.173.09:34:47.69/vb/04,04,usb,yes,34,33 2006.173.09:34:47.69/vb/05,04,usb,yes,27,29 2006.173.09:34:47.69/vb/06,04,usb,yes,31,27 2006.173.09:34:47.69/vb/07,04,usb,yes,31,31 2006.173.09:34:47.69/vb/08,04,usb,yes,28,32 2006.173.09:34:47.92/vblo/01,629.99,yes,locked 2006.173.09:34:47.92/vblo/02,634.99,yes,locked 2006.173.09:34:47.92/vblo/03,649.99,yes,locked 2006.173.09:34:47.92/vblo/04,679.99,yes,locked 2006.173.09:34:47.92/vblo/05,709.99,yes,locked 2006.173.09:34:47.92/vblo/06,719.99,yes,locked 2006.173.09:34:47.92/vblo/07,734.99,yes,locked 2006.173.09:34:47.92/vblo/08,744.99,yes,locked 2006.173.09:34:48.07/vabw/8 2006.173.09:34:48.22/vbbw/8 2006.173.09:34:48.31/xfe/off,on,15.2 2006.173.09:34:48.69/ifatt/23,28,28,28 2006.173.09:34:49.08/fmout-gps/S +4.05E-07 2006.173.09:34:49.12:!2006.173.09:47:48 2006.173.09:47:48.00:data_valid=off 2006.173.09:47:48.00:"et 2006.173.09:47:48.01:!+3s 2006.173.09:47:51.03:"tape 2006.173.09:47:51.03:postob 2006.173.09:47:51.15/cable/+6.5010E-03 2006.173.09:47:51.15/wx/22.69,1004.6,88 2006.173.09:47:51.21/fmout-gps/S +4.03E-07 2006.173.09:47:51.21:scan_name=173-0949,jd0606,360 2006.173.09:47:51.22:source=1308+326,131028.66,322043.8,2000.0,cw 2006.173.09:47:53.14#flagr#flagr/antenna,new-source 2006.173.09:47:53.15:checkk5 2006.173.09:47:53.54/chk_autoobs//k5ts1/ autoobs is running! 2006.173.09:47:53.95/chk_autoobs//k5ts2/ autoobs is running! 2006.173.09:47:54.35/chk_autoobs//k5ts3/ autoobs is running! 2006.173.09:47:54.75/chk_autoobs//k5ts4/ autoobs is running! 2006.173.09:47:55.45/chk_obsdata//k5ts1/T1730934??a.dat file size is correct (nominal:3136MB, actual:3132MB). 2006.173.09:47:56.14/chk_obsdata//k5ts2/T1730934??b.dat file size is correct (nominal:3136MB, actual:3132MB). 2006.173.09:47:56.85/chk_obsdata//k5ts3/T1730934??c.dat file size is correct (nominal:3136MB, actual:3132MB). 2006.173.09:47:57.55/chk_obsdata//k5ts4/T1730934??d.dat file size is correct (nominal:3136MB, actual:3132MB). 2006.173.09:47:58.30/k5log//k5ts1_log_newline 2006.173.09:47:59.01/k5log//k5ts2_log_newline 2006.173.09:47:59.72/k5log//k5ts3_log_newline 2006.173.09:48:00.47/k5log//k5ts4_log_newline 2006.173.09:48:00.49/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.09:48:00.49:setupk4=1 2006.173.09:48:00.49$setupk4/echo=on 2006.173.09:48:00.49$setupk4/pcalon 2006.173.09:48:00.49$pcalon/"no phase cal control is implemented here 2006.173.09:48:00.49$setupk4/"tpicd=stop 2006.173.09:48:00.49$setupk4/"rec=synch_on 2006.173.09:48:00.49$setupk4/"rec_mode=128 2006.173.09:48:00.49$setupk4/!* 2006.173.09:48:00.49$setupk4/recpk4 2006.173.09:48:00.49$recpk4/recpatch= 2006.173.09:48:00.50$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.09:48:00.50$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.09:48:00.50$setupk4/vck44 2006.173.09:48:00.50$vck44/valo=1,524.99 2006.173.09:48:00.50#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.09:48:00.50#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.09:48:00.50#ibcon#ireg 17 cls_cnt 0 2006.173.09:48:00.50#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.09:48:00.50#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.09:48:00.50#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.09:48:00.50#ibcon#enter wrdev, iclass 22, count 0 2006.173.09:48:00.50#ibcon#first serial, iclass 22, count 0 2006.173.09:48:00.50#ibcon#enter sib2, iclass 22, count 0 2006.173.09:48:00.50#ibcon#flushed, iclass 22, count 0 2006.173.09:48:00.50#ibcon#about to write, iclass 22, count 0 2006.173.09:48:00.50#ibcon#wrote, iclass 22, count 0 2006.173.09:48:00.50#ibcon#about to read 3, iclass 22, count 0 2006.173.09:48:00.51#ibcon#read 3, iclass 22, count 0 2006.173.09:48:00.51#ibcon#about to read 4, iclass 22, count 0 2006.173.09:48:00.51#ibcon#read 4, iclass 22, count 0 2006.173.09:48:00.51#ibcon#about to read 5, iclass 22, count 0 2006.173.09:48:00.51#ibcon#read 5, iclass 22, count 0 2006.173.09:48:00.51#ibcon#about to read 6, iclass 22, count 0 2006.173.09:48:00.51#ibcon#read 6, iclass 22, count 0 2006.173.09:48:00.51#ibcon#end of sib2, iclass 22, count 0 2006.173.09:48:00.51#ibcon#*mode == 0, iclass 22, count 0 2006.173.09:48:00.51#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.09:48:00.51#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.09:48:00.51#ibcon#*before write, iclass 22, count 0 2006.173.09:48:00.51#ibcon#enter sib2, iclass 22, count 0 2006.173.09:48:00.51#ibcon#flushed, iclass 22, count 0 2006.173.09:48:00.51#ibcon#about to write, iclass 22, count 0 2006.173.09:48:00.51#ibcon#wrote, iclass 22, count 0 2006.173.09:48:00.51#ibcon#about to read 3, iclass 22, count 0 2006.173.09:48:00.56#ibcon#read 3, iclass 22, count 0 2006.173.09:48:00.56#ibcon#about to read 4, iclass 22, count 0 2006.173.09:48:00.56#ibcon#read 4, iclass 22, count 0 2006.173.09:48:00.56#ibcon#about to read 5, iclass 22, count 0 2006.173.09:48:00.56#ibcon#read 5, iclass 22, count 0 2006.173.09:48:00.56#ibcon#about to read 6, iclass 22, count 0 2006.173.09:48:00.56#ibcon#read 6, iclass 22, count 0 2006.173.09:48:00.56#ibcon#end of sib2, iclass 22, count 0 2006.173.09:48:00.56#ibcon#*after write, iclass 22, count 0 2006.173.09:48:00.56#ibcon#*before return 0, iclass 22, count 0 2006.173.09:48:00.56#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.09:48:00.56#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.09:48:00.56#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.09:48:00.56#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.09:48:00.56$vck44/va=1,7 2006.173.09:48:00.56#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.09:48:00.56#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.09:48:00.56#ibcon#ireg 11 cls_cnt 2 2006.173.09:48:00.56#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.09:48:00.56#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.09:48:00.56#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.09:48:00.56#ibcon#enter wrdev, iclass 24, count 2 2006.173.09:48:00.56#ibcon#first serial, iclass 24, count 2 2006.173.09:48:00.56#ibcon#enter sib2, iclass 24, count 2 2006.173.09:48:00.56#ibcon#flushed, iclass 24, count 2 2006.173.09:48:00.56#ibcon#about to write, iclass 24, count 2 2006.173.09:48:00.56#ibcon#wrote, iclass 24, count 2 2006.173.09:48:00.56#ibcon#about to read 3, iclass 24, count 2 2006.173.09:48:00.58#ibcon#read 3, iclass 24, count 2 2006.173.09:48:00.58#ibcon#about to read 4, iclass 24, count 2 2006.173.09:48:00.58#ibcon#read 4, iclass 24, count 2 2006.173.09:48:00.58#ibcon#about to read 5, iclass 24, count 2 2006.173.09:48:00.58#ibcon#read 5, iclass 24, count 2 2006.173.09:48:00.58#ibcon#about to read 6, iclass 24, count 2 2006.173.09:48:00.58#ibcon#read 6, iclass 24, count 2 2006.173.09:48:00.58#ibcon#end of sib2, iclass 24, count 2 2006.173.09:48:00.58#ibcon#*mode == 0, iclass 24, count 2 2006.173.09:48:00.58#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.09:48:00.58#ibcon#[25=AT01-07\r\n] 2006.173.09:48:00.58#ibcon#*before write, iclass 24, count 2 2006.173.09:48:00.58#ibcon#enter sib2, iclass 24, count 2 2006.173.09:48:00.58#ibcon#flushed, iclass 24, count 2 2006.173.09:48:00.58#ibcon#about to write, iclass 24, count 2 2006.173.09:48:00.58#ibcon#wrote, iclass 24, count 2 2006.173.09:48:00.58#ibcon#about to read 3, iclass 24, count 2 2006.173.09:48:00.61#ibcon#read 3, iclass 24, count 2 2006.173.09:48:00.61#ibcon#about to read 4, iclass 24, count 2 2006.173.09:48:00.61#ibcon#read 4, iclass 24, count 2 2006.173.09:48:00.61#ibcon#about to read 5, iclass 24, count 2 2006.173.09:48:00.61#ibcon#read 5, iclass 24, count 2 2006.173.09:48:00.61#ibcon#about to read 6, iclass 24, count 2 2006.173.09:48:00.61#ibcon#read 6, iclass 24, count 2 2006.173.09:48:00.61#ibcon#end of sib2, iclass 24, count 2 2006.173.09:48:00.61#ibcon#*after write, iclass 24, count 2 2006.173.09:48:00.61#ibcon#*before return 0, iclass 24, count 2 2006.173.09:48:00.61#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.09:48:00.61#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.09:48:00.61#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.09:48:00.61#ibcon#ireg 7 cls_cnt 0 2006.173.09:48:00.61#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.09:48:00.73#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.09:48:00.73#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.09:48:00.73#ibcon#enter wrdev, iclass 24, count 0 2006.173.09:48:00.73#ibcon#first serial, iclass 24, count 0 2006.173.09:48:00.73#ibcon#enter sib2, iclass 24, count 0 2006.173.09:48:00.73#ibcon#flushed, iclass 24, count 0 2006.173.09:48:00.73#ibcon#about to write, iclass 24, count 0 2006.173.09:48:00.73#ibcon#wrote, iclass 24, count 0 2006.173.09:48:00.73#ibcon#about to read 3, iclass 24, count 0 2006.173.09:48:00.75#ibcon#read 3, iclass 24, count 0 2006.173.09:48:00.75#ibcon#about to read 4, iclass 24, count 0 2006.173.09:48:00.75#ibcon#read 4, iclass 24, count 0 2006.173.09:48:00.75#ibcon#about to read 5, iclass 24, count 0 2006.173.09:48:00.75#ibcon#read 5, iclass 24, count 0 2006.173.09:48:00.75#ibcon#about to read 6, iclass 24, count 0 2006.173.09:48:00.75#ibcon#read 6, iclass 24, count 0 2006.173.09:48:00.75#ibcon#end of sib2, iclass 24, count 0 2006.173.09:48:00.75#ibcon#*mode == 0, iclass 24, count 0 2006.173.09:48:00.75#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.09:48:00.75#ibcon#[25=USB\r\n] 2006.173.09:48:00.75#ibcon#*before write, iclass 24, count 0 2006.173.09:48:00.75#ibcon#enter sib2, iclass 24, count 0 2006.173.09:48:00.75#ibcon#flushed, iclass 24, count 0 2006.173.09:48:00.75#ibcon#about to write, iclass 24, count 0 2006.173.09:48:00.75#ibcon#wrote, iclass 24, count 0 2006.173.09:48:00.75#ibcon#about to read 3, iclass 24, count 0 2006.173.09:48:00.78#ibcon#read 3, iclass 24, count 0 2006.173.09:48:00.78#ibcon#about to read 4, iclass 24, count 0 2006.173.09:48:00.78#ibcon#read 4, iclass 24, count 0 2006.173.09:48:00.78#ibcon#about to read 5, iclass 24, count 0 2006.173.09:48:00.78#ibcon#read 5, iclass 24, count 0 2006.173.09:48:00.78#ibcon#about to read 6, iclass 24, count 0 2006.173.09:48:00.78#ibcon#read 6, iclass 24, count 0 2006.173.09:48:00.78#ibcon#end of sib2, iclass 24, count 0 2006.173.09:48:00.78#ibcon#*after write, iclass 24, count 0 2006.173.09:48:00.78#ibcon#*before return 0, iclass 24, count 0 2006.173.09:48:00.78#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.09:48:00.78#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.09:48:00.78#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.09:48:00.78#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.09:48:00.78$vck44/valo=2,534.99 2006.173.09:48:00.78#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.09:48:00.78#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.09:48:00.78#ibcon#ireg 17 cls_cnt 0 2006.173.09:48:00.78#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.09:48:00.78#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.09:48:00.78#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.09:48:00.78#ibcon#enter wrdev, iclass 26, count 0 2006.173.09:48:00.78#ibcon#first serial, iclass 26, count 0 2006.173.09:48:00.78#ibcon#enter sib2, iclass 26, count 0 2006.173.09:48:00.78#ibcon#flushed, iclass 26, count 0 2006.173.09:48:00.78#ibcon#about to write, iclass 26, count 0 2006.173.09:48:00.78#ibcon#wrote, iclass 26, count 0 2006.173.09:48:00.78#ibcon#about to read 3, iclass 26, count 0 2006.173.09:48:00.80#ibcon#read 3, iclass 26, count 0 2006.173.09:48:00.80#ibcon#about to read 4, iclass 26, count 0 2006.173.09:48:00.80#ibcon#read 4, iclass 26, count 0 2006.173.09:48:00.80#ibcon#about to read 5, iclass 26, count 0 2006.173.09:48:00.80#ibcon#read 5, iclass 26, count 0 2006.173.09:48:00.80#ibcon#about to read 6, iclass 26, count 0 2006.173.09:48:00.80#ibcon#read 6, iclass 26, count 0 2006.173.09:48:00.80#ibcon#end of sib2, iclass 26, count 0 2006.173.09:48:00.80#ibcon#*mode == 0, iclass 26, count 0 2006.173.09:48:00.80#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.09:48:00.80#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.09:48:00.80#ibcon#*before write, iclass 26, count 0 2006.173.09:48:00.80#ibcon#enter sib2, iclass 26, count 0 2006.173.09:48:00.80#ibcon#flushed, iclass 26, count 0 2006.173.09:48:00.80#ibcon#about to write, iclass 26, count 0 2006.173.09:48:00.80#ibcon#wrote, iclass 26, count 0 2006.173.09:48:00.80#ibcon#about to read 3, iclass 26, count 0 2006.173.09:48:00.84#ibcon#read 3, iclass 26, count 0 2006.173.09:48:00.84#ibcon#about to read 4, iclass 26, count 0 2006.173.09:48:00.84#ibcon#read 4, iclass 26, count 0 2006.173.09:48:00.84#ibcon#about to read 5, iclass 26, count 0 2006.173.09:48:00.84#ibcon#read 5, iclass 26, count 0 2006.173.09:48:00.84#ibcon#about to read 6, iclass 26, count 0 2006.173.09:48:00.84#ibcon#read 6, iclass 26, count 0 2006.173.09:48:00.84#ibcon#end of sib2, iclass 26, count 0 2006.173.09:48:00.84#ibcon#*after write, iclass 26, count 0 2006.173.09:48:00.84#ibcon#*before return 0, iclass 26, count 0 2006.173.09:48:00.84#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.09:48:00.84#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.09:48:00.84#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.09:48:00.84#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.09:48:00.84$vck44/va=2,6 2006.173.09:48:00.84#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.09:48:00.84#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.09:48:00.84#ibcon#ireg 11 cls_cnt 2 2006.173.09:48:00.84#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.09:48:00.90#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.09:48:00.90#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.09:48:00.90#ibcon#enter wrdev, iclass 28, count 2 2006.173.09:48:00.90#ibcon#first serial, iclass 28, count 2 2006.173.09:48:00.90#ibcon#enter sib2, iclass 28, count 2 2006.173.09:48:00.90#ibcon#flushed, iclass 28, count 2 2006.173.09:48:00.90#ibcon#about to write, iclass 28, count 2 2006.173.09:48:00.90#ibcon#wrote, iclass 28, count 2 2006.173.09:48:00.90#ibcon#about to read 3, iclass 28, count 2 2006.173.09:48:00.92#ibcon#read 3, iclass 28, count 2 2006.173.09:48:00.92#ibcon#about to read 4, iclass 28, count 2 2006.173.09:48:00.92#ibcon#read 4, iclass 28, count 2 2006.173.09:48:00.92#ibcon#about to read 5, iclass 28, count 2 2006.173.09:48:00.92#ibcon#read 5, iclass 28, count 2 2006.173.09:48:00.92#ibcon#about to read 6, iclass 28, count 2 2006.173.09:48:00.92#ibcon#read 6, iclass 28, count 2 2006.173.09:48:00.92#ibcon#end of sib2, iclass 28, count 2 2006.173.09:48:00.92#ibcon#*mode == 0, iclass 28, count 2 2006.173.09:48:00.92#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.09:48:00.92#ibcon#[25=AT02-06\r\n] 2006.173.09:48:00.92#ibcon#*before write, iclass 28, count 2 2006.173.09:48:00.92#ibcon#enter sib2, iclass 28, count 2 2006.173.09:48:00.92#ibcon#flushed, iclass 28, count 2 2006.173.09:48:00.92#ibcon#about to write, iclass 28, count 2 2006.173.09:48:00.92#ibcon#wrote, iclass 28, count 2 2006.173.09:48:00.92#ibcon#about to read 3, iclass 28, count 2 2006.173.09:48:00.95#ibcon#read 3, iclass 28, count 2 2006.173.09:48:00.95#ibcon#about to read 4, iclass 28, count 2 2006.173.09:48:00.95#ibcon#read 4, iclass 28, count 2 2006.173.09:48:00.95#ibcon#about to read 5, iclass 28, count 2 2006.173.09:48:00.95#ibcon#read 5, iclass 28, count 2 2006.173.09:48:00.95#ibcon#about to read 6, iclass 28, count 2 2006.173.09:48:00.95#ibcon#read 6, iclass 28, count 2 2006.173.09:48:00.95#ibcon#end of sib2, iclass 28, count 2 2006.173.09:48:00.95#ibcon#*after write, iclass 28, count 2 2006.173.09:48:00.95#ibcon#*before return 0, iclass 28, count 2 2006.173.09:48:00.95#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.09:48:00.95#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.09:48:00.95#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.09:48:00.95#ibcon#ireg 7 cls_cnt 0 2006.173.09:48:00.95#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.09:48:01.07#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.09:48:01.07#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.09:48:01.07#ibcon#enter wrdev, iclass 28, count 0 2006.173.09:48:01.07#ibcon#first serial, iclass 28, count 0 2006.173.09:48:01.07#ibcon#enter sib2, iclass 28, count 0 2006.173.09:48:01.07#ibcon#flushed, iclass 28, count 0 2006.173.09:48:01.07#ibcon#about to write, iclass 28, count 0 2006.173.09:48:01.07#ibcon#wrote, iclass 28, count 0 2006.173.09:48:01.07#ibcon#about to read 3, iclass 28, count 0 2006.173.09:48:01.09#ibcon#read 3, iclass 28, count 0 2006.173.09:48:01.09#ibcon#about to read 4, iclass 28, count 0 2006.173.09:48:01.09#ibcon#read 4, iclass 28, count 0 2006.173.09:48:01.09#ibcon#about to read 5, iclass 28, count 0 2006.173.09:48:01.09#ibcon#read 5, iclass 28, count 0 2006.173.09:48:01.09#ibcon#about to read 6, iclass 28, count 0 2006.173.09:48:01.09#ibcon#read 6, iclass 28, count 0 2006.173.09:48:01.09#ibcon#end of sib2, iclass 28, count 0 2006.173.09:48:01.09#ibcon#*mode == 0, iclass 28, count 0 2006.173.09:48:01.09#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.09:48:01.09#ibcon#[25=USB\r\n] 2006.173.09:48:01.09#ibcon#*before write, iclass 28, count 0 2006.173.09:48:01.09#ibcon#enter sib2, iclass 28, count 0 2006.173.09:48:01.09#ibcon#flushed, iclass 28, count 0 2006.173.09:48:01.09#ibcon#about to write, iclass 28, count 0 2006.173.09:48:01.09#ibcon#wrote, iclass 28, count 0 2006.173.09:48:01.09#ibcon#about to read 3, iclass 28, count 0 2006.173.09:48:01.12#ibcon#read 3, iclass 28, count 0 2006.173.09:48:01.12#ibcon#about to read 4, iclass 28, count 0 2006.173.09:48:01.12#ibcon#read 4, iclass 28, count 0 2006.173.09:48:01.12#ibcon#about to read 5, iclass 28, count 0 2006.173.09:48:01.12#ibcon#read 5, iclass 28, count 0 2006.173.09:48:01.12#ibcon#about to read 6, iclass 28, count 0 2006.173.09:48:01.12#ibcon#read 6, iclass 28, count 0 2006.173.09:48:01.12#ibcon#end of sib2, iclass 28, count 0 2006.173.09:48:01.12#ibcon#*after write, iclass 28, count 0 2006.173.09:48:01.12#ibcon#*before return 0, iclass 28, count 0 2006.173.09:48:01.12#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.09:48:01.12#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.09:48:01.12#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.09:48:01.12#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.09:48:01.12$vck44/valo=3,564.99 2006.173.09:48:01.12#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.09:48:01.12#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.09:48:01.12#ibcon#ireg 17 cls_cnt 0 2006.173.09:48:01.12#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.09:48:01.12#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.09:48:01.12#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.09:48:01.12#ibcon#enter wrdev, iclass 30, count 0 2006.173.09:48:01.12#ibcon#first serial, iclass 30, count 0 2006.173.09:48:01.12#ibcon#enter sib2, iclass 30, count 0 2006.173.09:48:01.12#ibcon#flushed, iclass 30, count 0 2006.173.09:48:01.12#ibcon#about to write, iclass 30, count 0 2006.173.09:48:01.12#ibcon#wrote, iclass 30, count 0 2006.173.09:48:01.12#ibcon#about to read 3, iclass 30, count 0 2006.173.09:48:01.14#ibcon#read 3, iclass 30, count 0 2006.173.09:48:01.14#ibcon#about to read 4, iclass 30, count 0 2006.173.09:48:01.14#ibcon#read 4, iclass 30, count 0 2006.173.09:48:01.14#ibcon#about to read 5, iclass 30, count 0 2006.173.09:48:01.14#ibcon#read 5, iclass 30, count 0 2006.173.09:48:01.14#ibcon#about to read 6, iclass 30, count 0 2006.173.09:48:01.14#ibcon#read 6, iclass 30, count 0 2006.173.09:48:01.14#ibcon#end of sib2, iclass 30, count 0 2006.173.09:48:01.14#ibcon#*mode == 0, iclass 30, count 0 2006.173.09:48:01.14#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.09:48:01.14#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.09:48:01.14#ibcon#*before write, iclass 30, count 0 2006.173.09:48:01.14#ibcon#enter sib2, iclass 30, count 0 2006.173.09:48:01.14#ibcon#flushed, iclass 30, count 0 2006.173.09:48:01.14#ibcon#about to write, iclass 30, count 0 2006.173.09:48:01.14#ibcon#wrote, iclass 30, count 0 2006.173.09:48:01.14#ibcon#about to read 3, iclass 30, count 0 2006.173.09:48:01.18#ibcon#read 3, iclass 30, count 0 2006.173.09:48:01.18#ibcon#about to read 4, iclass 30, count 0 2006.173.09:48:01.18#ibcon#read 4, iclass 30, count 0 2006.173.09:48:01.18#ibcon#about to read 5, iclass 30, count 0 2006.173.09:48:01.18#ibcon#read 5, iclass 30, count 0 2006.173.09:48:01.18#ibcon#about to read 6, iclass 30, count 0 2006.173.09:48:01.18#ibcon#read 6, iclass 30, count 0 2006.173.09:48:01.18#ibcon#end of sib2, iclass 30, count 0 2006.173.09:48:01.18#ibcon#*after write, iclass 30, count 0 2006.173.09:48:01.18#ibcon#*before return 0, iclass 30, count 0 2006.173.09:48:01.18#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.09:48:01.18#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.09:48:01.18#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.09:48:01.18#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.09:48:01.18$vck44/va=3,5 2006.173.09:48:01.18#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.173.09:48:01.18#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.173.09:48:01.18#ibcon#ireg 11 cls_cnt 2 2006.173.09:48:01.18#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.09:48:01.24#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.09:48:01.24#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.09:48:01.24#ibcon#enter wrdev, iclass 32, count 2 2006.173.09:48:01.24#ibcon#first serial, iclass 32, count 2 2006.173.09:48:01.24#ibcon#enter sib2, iclass 32, count 2 2006.173.09:48:01.24#ibcon#flushed, iclass 32, count 2 2006.173.09:48:01.24#ibcon#about to write, iclass 32, count 2 2006.173.09:48:01.24#ibcon#wrote, iclass 32, count 2 2006.173.09:48:01.24#ibcon#about to read 3, iclass 32, count 2 2006.173.09:48:01.26#ibcon#read 3, iclass 32, count 2 2006.173.09:48:01.26#ibcon#about to read 4, iclass 32, count 2 2006.173.09:48:01.26#ibcon#read 4, iclass 32, count 2 2006.173.09:48:01.26#ibcon#about to read 5, iclass 32, count 2 2006.173.09:48:01.26#ibcon#read 5, iclass 32, count 2 2006.173.09:48:01.26#ibcon#about to read 6, iclass 32, count 2 2006.173.09:48:01.26#ibcon#read 6, iclass 32, count 2 2006.173.09:48:01.26#ibcon#end of sib2, iclass 32, count 2 2006.173.09:48:01.26#ibcon#*mode == 0, iclass 32, count 2 2006.173.09:48:01.26#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.173.09:48:01.26#ibcon#[25=AT03-05\r\n] 2006.173.09:48:01.26#ibcon#*before write, iclass 32, count 2 2006.173.09:48:01.26#ibcon#enter sib2, iclass 32, count 2 2006.173.09:48:01.26#ibcon#flushed, iclass 32, count 2 2006.173.09:48:01.26#ibcon#about to write, iclass 32, count 2 2006.173.09:48:01.26#ibcon#wrote, iclass 32, count 2 2006.173.09:48:01.26#ibcon#about to read 3, iclass 32, count 2 2006.173.09:48:01.29#ibcon#read 3, iclass 32, count 2 2006.173.09:48:01.29#ibcon#about to read 4, iclass 32, count 2 2006.173.09:48:01.29#ibcon#read 4, iclass 32, count 2 2006.173.09:48:01.29#ibcon#about to read 5, iclass 32, count 2 2006.173.09:48:01.29#ibcon#read 5, iclass 32, count 2 2006.173.09:48:01.29#ibcon#about to read 6, iclass 32, count 2 2006.173.09:48:01.29#ibcon#read 6, iclass 32, count 2 2006.173.09:48:01.29#ibcon#end of sib2, iclass 32, count 2 2006.173.09:48:01.29#ibcon#*after write, iclass 32, count 2 2006.173.09:48:01.29#ibcon#*before return 0, iclass 32, count 2 2006.173.09:48:01.29#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.09:48:01.29#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.173.09:48:01.29#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.173.09:48:01.29#ibcon#ireg 7 cls_cnt 0 2006.173.09:48:01.29#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.09:48:01.41#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.09:48:01.41#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.09:48:01.41#ibcon#enter wrdev, iclass 32, count 0 2006.173.09:48:01.41#ibcon#first serial, iclass 32, count 0 2006.173.09:48:01.41#ibcon#enter sib2, iclass 32, count 0 2006.173.09:48:01.41#ibcon#flushed, iclass 32, count 0 2006.173.09:48:01.41#ibcon#about to write, iclass 32, count 0 2006.173.09:48:01.41#ibcon#wrote, iclass 32, count 0 2006.173.09:48:01.41#ibcon#about to read 3, iclass 32, count 0 2006.173.09:48:01.43#ibcon#read 3, iclass 32, count 0 2006.173.09:48:01.43#ibcon#about to read 4, iclass 32, count 0 2006.173.09:48:01.43#ibcon#read 4, iclass 32, count 0 2006.173.09:48:01.43#ibcon#about to read 5, iclass 32, count 0 2006.173.09:48:01.43#ibcon#read 5, iclass 32, count 0 2006.173.09:48:01.43#ibcon#about to read 6, iclass 32, count 0 2006.173.09:48:01.43#ibcon#read 6, iclass 32, count 0 2006.173.09:48:01.43#ibcon#end of sib2, iclass 32, count 0 2006.173.09:48:01.43#ibcon#*mode == 0, iclass 32, count 0 2006.173.09:48:01.43#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.09:48:01.43#ibcon#[25=USB\r\n] 2006.173.09:48:01.43#ibcon#*before write, iclass 32, count 0 2006.173.09:48:01.43#ibcon#enter sib2, iclass 32, count 0 2006.173.09:48:01.43#ibcon#flushed, iclass 32, count 0 2006.173.09:48:01.43#ibcon#about to write, iclass 32, count 0 2006.173.09:48:01.43#ibcon#wrote, iclass 32, count 0 2006.173.09:48:01.43#ibcon#about to read 3, iclass 32, count 0 2006.173.09:48:01.46#ibcon#read 3, iclass 32, count 0 2006.173.09:48:01.46#ibcon#about to read 4, iclass 32, count 0 2006.173.09:48:01.46#ibcon#read 4, iclass 32, count 0 2006.173.09:48:01.46#ibcon#about to read 5, iclass 32, count 0 2006.173.09:48:01.46#ibcon#read 5, iclass 32, count 0 2006.173.09:48:01.46#ibcon#about to read 6, iclass 32, count 0 2006.173.09:48:01.46#ibcon#read 6, iclass 32, count 0 2006.173.09:48:01.46#ibcon#end of sib2, iclass 32, count 0 2006.173.09:48:01.46#ibcon#*after write, iclass 32, count 0 2006.173.09:48:01.46#ibcon#*before return 0, iclass 32, count 0 2006.173.09:48:01.46#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.09:48:01.46#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.173.09:48:01.46#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.09:48:01.46#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.09:48:01.46$vck44/valo=4,624.99 2006.173.09:48:01.46#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.09:48:01.46#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.09:48:01.46#ibcon#ireg 17 cls_cnt 0 2006.173.09:48:01.46#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.09:48:01.46#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.09:48:01.46#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.09:48:01.46#ibcon#enter wrdev, iclass 34, count 0 2006.173.09:48:01.46#ibcon#first serial, iclass 34, count 0 2006.173.09:48:01.46#ibcon#enter sib2, iclass 34, count 0 2006.173.09:48:01.46#ibcon#flushed, iclass 34, count 0 2006.173.09:48:01.46#ibcon#about to write, iclass 34, count 0 2006.173.09:48:01.46#ibcon#wrote, iclass 34, count 0 2006.173.09:48:01.46#ibcon#about to read 3, iclass 34, count 0 2006.173.09:48:01.48#ibcon#read 3, iclass 34, count 0 2006.173.09:48:01.48#ibcon#about to read 4, iclass 34, count 0 2006.173.09:48:01.48#ibcon#read 4, iclass 34, count 0 2006.173.09:48:01.48#ibcon#about to read 5, iclass 34, count 0 2006.173.09:48:01.48#ibcon#read 5, iclass 34, count 0 2006.173.09:48:01.48#ibcon#about to read 6, iclass 34, count 0 2006.173.09:48:01.48#ibcon#read 6, iclass 34, count 0 2006.173.09:48:01.48#ibcon#end of sib2, iclass 34, count 0 2006.173.09:48:01.48#ibcon#*mode == 0, iclass 34, count 0 2006.173.09:48:01.48#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.09:48:01.48#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.09:48:01.48#ibcon#*before write, iclass 34, count 0 2006.173.09:48:01.48#ibcon#enter sib2, iclass 34, count 0 2006.173.09:48:01.48#ibcon#flushed, iclass 34, count 0 2006.173.09:48:01.48#ibcon#about to write, iclass 34, count 0 2006.173.09:48:01.48#ibcon#wrote, iclass 34, count 0 2006.173.09:48:01.48#ibcon#about to read 3, iclass 34, count 0 2006.173.09:48:01.52#ibcon#read 3, iclass 34, count 0 2006.173.09:48:01.52#ibcon#about to read 4, iclass 34, count 0 2006.173.09:48:01.52#ibcon#read 4, iclass 34, count 0 2006.173.09:48:01.52#ibcon#about to read 5, iclass 34, count 0 2006.173.09:48:01.52#ibcon#read 5, iclass 34, count 0 2006.173.09:48:01.52#ibcon#about to read 6, iclass 34, count 0 2006.173.09:48:01.52#ibcon#read 6, iclass 34, count 0 2006.173.09:48:01.52#ibcon#end of sib2, iclass 34, count 0 2006.173.09:48:01.52#ibcon#*after write, iclass 34, count 0 2006.173.09:48:01.52#ibcon#*before return 0, iclass 34, count 0 2006.173.09:48:01.52#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.09:48:01.52#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.09:48:01.52#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.09:48:01.52#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.09:48:01.52$vck44/va=4,6 2006.173.09:48:01.52#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.09:48:01.52#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.09:48:01.52#ibcon#ireg 11 cls_cnt 2 2006.173.09:48:01.52#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.09:48:01.58#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.09:48:01.58#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.09:48:01.58#ibcon#enter wrdev, iclass 36, count 2 2006.173.09:48:01.58#ibcon#first serial, iclass 36, count 2 2006.173.09:48:01.58#ibcon#enter sib2, iclass 36, count 2 2006.173.09:48:01.58#ibcon#flushed, iclass 36, count 2 2006.173.09:48:01.58#ibcon#about to write, iclass 36, count 2 2006.173.09:48:01.58#ibcon#wrote, iclass 36, count 2 2006.173.09:48:01.58#ibcon#about to read 3, iclass 36, count 2 2006.173.09:48:01.60#ibcon#read 3, iclass 36, count 2 2006.173.09:48:01.60#ibcon#about to read 4, iclass 36, count 2 2006.173.09:48:01.60#ibcon#read 4, iclass 36, count 2 2006.173.09:48:01.60#ibcon#about to read 5, iclass 36, count 2 2006.173.09:48:01.60#ibcon#read 5, iclass 36, count 2 2006.173.09:48:01.60#ibcon#about to read 6, iclass 36, count 2 2006.173.09:48:01.60#ibcon#read 6, iclass 36, count 2 2006.173.09:48:01.60#ibcon#end of sib2, iclass 36, count 2 2006.173.09:48:01.60#ibcon#*mode == 0, iclass 36, count 2 2006.173.09:48:01.60#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.09:48:01.60#ibcon#[25=AT04-06\r\n] 2006.173.09:48:01.60#ibcon#*before write, iclass 36, count 2 2006.173.09:48:01.60#ibcon#enter sib2, iclass 36, count 2 2006.173.09:48:01.60#ibcon#flushed, iclass 36, count 2 2006.173.09:48:01.60#ibcon#about to write, iclass 36, count 2 2006.173.09:48:01.60#ibcon#wrote, iclass 36, count 2 2006.173.09:48:01.60#ibcon#about to read 3, iclass 36, count 2 2006.173.09:48:01.63#ibcon#read 3, iclass 36, count 2 2006.173.09:48:01.63#ibcon#about to read 4, iclass 36, count 2 2006.173.09:48:01.63#ibcon#read 4, iclass 36, count 2 2006.173.09:48:01.63#ibcon#about to read 5, iclass 36, count 2 2006.173.09:48:01.63#ibcon#read 5, iclass 36, count 2 2006.173.09:48:01.63#ibcon#about to read 6, iclass 36, count 2 2006.173.09:48:01.63#ibcon#read 6, iclass 36, count 2 2006.173.09:48:01.63#ibcon#end of sib2, iclass 36, count 2 2006.173.09:48:01.63#ibcon#*after write, iclass 36, count 2 2006.173.09:48:01.63#ibcon#*before return 0, iclass 36, count 2 2006.173.09:48:01.63#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.09:48:01.63#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.09:48:01.63#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.09:48:01.63#ibcon#ireg 7 cls_cnt 0 2006.173.09:48:01.63#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.09:48:01.75#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.09:48:01.75#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.09:48:01.75#ibcon#enter wrdev, iclass 36, count 0 2006.173.09:48:01.75#ibcon#first serial, iclass 36, count 0 2006.173.09:48:01.75#ibcon#enter sib2, iclass 36, count 0 2006.173.09:48:01.75#ibcon#flushed, iclass 36, count 0 2006.173.09:48:01.75#ibcon#about to write, iclass 36, count 0 2006.173.09:48:01.75#ibcon#wrote, iclass 36, count 0 2006.173.09:48:01.75#ibcon#about to read 3, iclass 36, count 0 2006.173.09:48:01.77#ibcon#read 3, iclass 36, count 0 2006.173.09:48:01.77#ibcon#about to read 4, iclass 36, count 0 2006.173.09:48:01.77#ibcon#read 4, iclass 36, count 0 2006.173.09:48:01.77#ibcon#about to read 5, iclass 36, count 0 2006.173.09:48:01.77#ibcon#read 5, iclass 36, count 0 2006.173.09:48:01.77#ibcon#about to read 6, iclass 36, count 0 2006.173.09:48:01.77#ibcon#read 6, iclass 36, count 0 2006.173.09:48:01.77#ibcon#end of sib2, iclass 36, count 0 2006.173.09:48:01.77#ibcon#*mode == 0, iclass 36, count 0 2006.173.09:48:01.77#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.09:48:01.77#ibcon#[25=USB\r\n] 2006.173.09:48:01.77#ibcon#*before write, iclass 36, count 0 2006.173.09:48:01.77#ibcon#enter sib2, iclass 36, count 0 2006.173.09:48:01.77#ibcon#flushed, iclass 36, count 0 2006.173.09:48:01.77#ibcon#about to write, iclass 36, count 0 2006.173.09:48:01.77#ibcon#wrote, iclass 36, count 0 2006.173.09:48:01.77#ibcon#about to read 3, iclass 36, count 0 2006.173.09:48:01.80#ibcon#read 3, iclass 36, count 0 2006.173.09:48:01.80#ibcon#about to read 4, iclass 36, count 0 2006.173.09:48:01.80#ibcon#read 4, iclass 36, count 0 2006.173.09:48:01.80#ibcon#about to read 5, iclass 36, count 0 2006.173.09:48:01.80#ibcon#read 5, iclass 36, count 0 2006.173.09:48:01.80#ibcon#about to read 6, iclass 36, count 0 2006.173.09:48:01.80#ibcon#read 6, iclass 36, count 0 2006.173.09:48:01.80#ibcon#end of sib2, iclass 36, count 0 2006.173.09:48:01.80#ibcon#*after write, iclass 36, count 0 2006.173.09:48:01.80#ibcon#*before return 0, iclass 36, count 0 2006.173.09:48:01.80#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.09:48:01.80#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.09:48:01.80#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.09:48:01.80#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.09:48:01.80$vck44/valo=5,734.99 2006.173.09:48:01.80#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.09:48:01.80#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.09:48:01.80#ibcon#ireg 17 cls_cnt 0 2006.173.09:48:01.80#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.09:48:01.80#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.09:48:01.80#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.09:48:01.80#ibcon#enter wrdev, iclass 38, count 0 2006.173.09:48:01.80#ibcon#first serial, iclass 38, count 0 2006.173.09:48:01.80#ibcon#enter sib2, iclass 38, count 0 2006.173.09:48:01.80#ibcon#flushed, iclass 38, count 0 2006.173.09:48:01.80#ibcon#about to write, iclass 38, count 0 2006.173.09:48:01.80#ibcon#wrote, iclass 38, count 0 2006.173.09:48:01.80#ibcon#about to read 3, iclass 38, count 0 2006.173.09:48:01.82#ibcon#read 3, iclass 38, count 0 2006.173.09:48:01.82#ibcon#about to read 4, iclass 38, count 0 2006.173.09:48:01.82#ibcon#read 4, iclass 38, count 0 2006.173.09:48:01.82#ibcon#about to read 5, iclass 38, count 0 2006.173.09:48:01.82#ibcon#read 5, iclass 38, count 0 2006.173.09:48:01.82#ibcon#about to read 6, iclass 38, count 0 2006.173.09:48:01.82#ibcon#read 6, iclass 38, count 0 2006.173.09:48:01.82#ibcon#end of sib2, iclass 38, count 0 2006.173.09:48:01.82#ibcon#*mode == 0, iclass 38, count 0 2006.173.09:48:01.82#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.09:48:01.82#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.09:48:01.82#ibcon#*before write, iclass 38, count 0 2006.173.09:48:01.82#ibcon#enter sib2, iclass 38, count 0 2006.173.09:48:01.82#ibcon#flushed, iclass 38, count 0 2006.173.09:48:01.82#ibcon#about to write, iclass 38, count 0 2006.173.09:48:01.82#ibcon#wrote, iclass 38, count 0 2006.173.09:48:01.82#ibcon#about to read 3, iclass 38, count 0 2006.173.09:48:01.86#ibcon#read 3, iclass 38, count 0 2006.173.09:48:01.86#ibcon#about to read 4, iclass 38, count 0 2006.173.09:48:01.86#ibcon#read 4, iclass 38, count 0 2006.173.09:48:01.86#ibcon#about to read 5, iclass 38, count 0 2006.173.09:48:01.86#ibcon#read 5, iclass 38, count 0 2006.173.09:48:01.86#ibcon#about to read 6, iclass 38, count 0 2006.173.09:48:01.86#ibcon#read 6, iclass 38, count 0 2006.173.09:48:01.86#ibcon#end of sib2, iclass 38, count 0 2006.173.09:48:01.86#ibcon#*after write, iclass 38, count 0 2006.173.09:48:01.86#ibcon#*before return 0, iclass 38, count 0 2006.173.09:48:01.86#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.09:48:01.86#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.09:48:01.86#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.09:48:01.86#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.09:48:01.86$vck44/va=5,4 2006.173.09:48:01.86#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.09:48:01.86#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.09:48:01.86#ibcon#ireg 11 cls_cnt 2 2006.173.09:48:01.86#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.09:48:01.92#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.09:48:01.92#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.09:48:01.92#ibcon#enter wrdev, iclass 40, count 2 2006.173.09:48:01.92#ibcon#first serial, iclass 40, count 2 2006.173.09:48:01.92#ibcon#enter sib2, iclass 40, count 2 2006.173.09:48:01.92#ibcon#flushed, iclass 40, count 2 2006.173.09:48:01.92#ibcon#about to write, iclass 40, count 2 2006.173.09:48:01.92#ibcon#wrote, iclass 40, count 2 2006.173.09:48:01.92#ibcon#about to read 3, iclass 40, count 2 2006.173.09:48:01.94#ibcon#read 3, iclass 40, count 2 2006.173.09:48:01.94#ibcon#about to read 4, iclass 40, count 2 2006.173.09:48:01.94#ibcon#read 4, iclass 40, count 2 2006.173.09:48:01.94#ibcon#about to read 5, iclass 40, count 2 2006.173.09:48:01.94#ibcon#read 5, iclass 40, count 2 2006.173.09:48:01.94#ibcon#about to read 6, iclass 40, count 2 2006.173.09:48:01.94#ibcon#read 6, iclass 40, count 2 2006.173.09:48:01.94#ibcon#end of sib2, iclass 40, count 2 2006.173.09:48:01.94#ibcon#*mode == 0, iclass 40, count 2 2006.173.09:48:01.94#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.09:48:01.94#ibcon#[25=AT05-04\r\n] 2006.173.09:48:01.94#ibcon#*before write, iclass 40, count 2 2006.173.09:48:01.94#ibcon#enter sib2, iclass 40, count 2 2006.173.09:48:01.94#ibcon#flushed, iclass 40, count 2 2006.173.09:48:01.94#ibcon#about to write, iclass 40, count 2 2006.173.09:48:01.94#ibcon#wrote, iclass 40, count 2 2006.173.09:48:01.94#ibcon#about to read 3, iclass 40, count 2 2006.173.09:48:01.97#ibcon#read 3, iclass 40, count 2 2006.173.09:48:01.97#ibcon#about to read 4, iclass 40, count 2 2006.173.09:48:01.97#ibcon#read 4, iclass 40, count 2 2006.173.09:48:01.97#ibcon#about to read 5, iclass 40, count 2 2006.173.09:48:01.97#ibcon#read 5, iclass 40, count 2 2006.173.09:48:01.97#ibcon#about to read 6, iclass 40, count 2 2006.173.09:48:01.97#ibcon#read 6, iclass 40, count 2 2006.173.09:48:01.97#ibcon#end of sib2, iclass 40, count 2 2006.173.09:48:01.97#ibcon#*after write, iclass 40, count 2 2006.173.09:48:01.97#ibcon#*before return 0, iclass 40, count 2 2006.173.09:48:01.97#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.09:48:01.97#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.09:48:01.97#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.09:48:01.97#ibcon#ireg 7 cls_cnt 0 2006.173.09:48:01.97#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.09:48:02.09#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.09:48:02.09#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.09:48:02.09#ibcon#enter wrdev, iclass 40, count 0 2006.173.09:48:02.09#ibcon#first serial, iclass 40, count 0 2006.173.09:48:02.09#ibcon#enter sib2, iclass 40, count 0 2006.173.09:48:02.09#ibcon#flushed, iclass 40, count 0 2006.173.09:48:02.09#ibcon#about to write, iclass 40, count 0 2006.173.09:48:02.09#ibcon#wrote, iclass 40, count 0 2006.173.09:48:02.09#ibcon#about to read 3, iclass 40, count 0 2006.173.09:48:02.11#ibcon#read 3, iclass 40, count 0 2006.173.09:48:02.11#ibcon#about to read 4, iclass 40, count 0 2006.173.09:48:02.11#ibcon#read 4, iclass 40, count 0 2006.173.09:48:02.11#ibcon#about to read 5, iclass 40, count 0 2006.173.09:48:02.11#ibcon#read 5, iclass 40, count 0 2006.173.09:48:02.11#ibcon#about to read 6, iclass 40, count 0 2006.173.09:48:02.11#ibcon#read 6, iclass 40, count 0 2006.173.09:48:02.11#ibcon#end of sib2, iclass 40, count 0 2006.173.09:48:02.11#ibcon#*mode == 0, iclass 40, count 0 2006.173.09:48:02.11#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.09:48:02.11#ibcon#[25=USB\r\n] 2006.173.09:48:02.11#ibcon#*before write, iclass 40, count 0 2006.173.09:48:02.11#ibcon#enter sib2, iclass 40, count 0 2006.173.09:48:02.11#ibcon#flushed, iclass 40, count 0 2006.173.09:48:02.11#ibcon#about to write, iclass 40, count 0 2006.173.09:48:02.11#ibcon#wrote, iclass 40, count 0 2006.173.09:48:02.11#ibcon#about to read 3, iclass 40, count 0 2006.173.09:48:02.14#ibcon#read 3, iclass 40, count 0 2006.173.09:48:02.14#ibcon#about to read 4, iclass 40, count 0 2006.173.09:48:02.14#ibcon#read 4, iclass 40, count 0 2006.173.09:48:02.14#ibcon#about to read 5, iclass 40, count 0 2006.173.09:48:02.14#ibcon#read 5, iclass 40, count 0 2006.173.09:48:02.14#ibcon#about to read 6, iclass 40, count 0 2006.173.09:48:02.14#ibcon#read 6, iclass 40, count 0 2006.173.09:48:02.14#ibcon#end of sib2, iclass 40, count 0 2006.173.09:48:02.14#ibcon#*after write, iclass 40, count 0 2006.173.09:48:02.14#ibcon#*before return 0, iclass 40, count 0 2006.173.09:48:02.14#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.09:48:02.14#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.09:48:02.14#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.09:48:02.14#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.09:48:02.15$vck44/valo=6,814.99 2006.173.09:48:02.15#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.09:48:02.15#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.09:48:02.15#ibcon#ireg 17 cls_cnt 0 2006.173.09:48:02.15#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.09:48:02.15#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.09:48:02.15#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.09:48:02.15#ibcon#enter wrdev, iclass 4, count 0 2006.173.09:48:02.15#ibcon#first serial, iclass 4, count 0 2006.173.09:48:02.15#ibcon#enter sib2, iclass 4, count 0 2006.173.09:48:02.15#ibcon#flushed, iclass 4, count 0 2006.173.09:48:02.15#ibcon#about to write, iclass 4, count 0 2006.173.09:48:02.15#ibcon#wrote, iclass 4, count 0 2006.173.09:48:02.15#ibcon#about to read 3, iclass 4, count 0 2006.173.09:48:02.16#ibcon#read 3, iclass 4, count 0 2006.173.09:48:02.16#ibcon#about to read 4, iclass 4, count 0 2006.173.09:48:02.16#ibcon#read 4, iclass 4, count 0 2006.173.09:48:02.16#ibcon#about to read 5, iclass 4, count 0 2006.173.09:48:02.16#ibcon#read 5, iclass 4, count 0 2006.173.09:48:02.16#ibcon#about to read 6, iclass 4, count 0 2006.173.09:48:02.16#ibcon#read 6, iclass 4, count 0 2006.173.09:48:02.16#ibcon#end of sib2, iclass 4, count 0 2006.173.09:48:02.16#ibcon#*mode == 0, iclass 4, count 0 2006.173.09:48:02.16#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.09:48:02.16#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.09:48:02.16#ibcon#*before write, iclass 4, count 0 2006.173.09:48:02.16#ibcon#enter sib2, iclass 4, count 0 2006.173.09:48:02.16#ibcon#flushed, iclass 4, count 0 2006.173.09:48:02.16#ibcon#about to write, iclass 4, count 0 2006.173.09:48:02.16#ibcon#wrote, iclass 4, count 0 2006.173.09:48:02.16#ibcon#about to read 3, iclass 4, count 0 2006.173.09:48:02.20#ibcon#read 3, iclass 4, count 0 2006.173.09:48:02.20#ibcon#about to read 4, iclass 4, count 0 2006.173.09:48:02.20#ibcon#read 4, iclass 4, count 0 2006.173.09:48:02.20#ibcon#about to read 5, iclass 4, count 0 2006.173.09:48:02.20#ibcon#read 5, iclass 4, count 0 2006.173.09:48:02.20#ibcon#about to read 6, iclass 4, count 0 2006.173.09:48:02.20#ibcon#read 6, iclass 4, count 0 2006.173.09:48:02.20#ibcon#end of sib2, iclass 4, count 0 2006.173.09:48:02.20#ibcon#*after write, iclass 4, count 0 2006.173.09:48:02.20#ibcon#*before return 0, iclass 4, count 0 2006.173.09:48:02.20#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.09:48:02.20#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.09:48:02.20#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.09:48:02.20#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.09:48:02.20$vck44/va=6,3 2006.173.09:48:02.20#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.09:48:02.20#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.09:48:02.20#ibcon#ireg 11 cls_cnt 2 2006.173.09:48:02.20#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.09:48:02.26#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.09:48:02.26#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.09:48:02.26#ibcon#enter wrdev, iclass 6, count 2 2006.173.09:48:02.26#ibcon#first serial, iclass 6, count 2 2006.173.09:48:02.26#ibcon#enter sib2, iclass 6, count 2 2006.173.09:48:02.26#ibcon#flushed, iclass 6, count 2 2006.173.09:48:02.26#ibcon#about to write, iclass 6, count 2 2006.173.09:48:02.26#ibcon#wrote, iclass 6, count 2 2006.173.09:48:02.26#ibcon#about to read 3, iclass 6, count 2 2006.173.09:48:02.28#ibcon#read 3, iclass 6, count 2 2006.173.09:48:02.28#ibcon#about to read 4, iclass 6, count 2 2006.173.09:48:02.28#ibcon#read 4, iclass 6, count 2 2006.173.09:48:02.28#ibcon#about to read 5, iclass 6, count 2 2006.173.09:48:02.28#ibcon#read 5, iclass 6, count 2 2006.173.09:48:02.28#ibcon#about to read 6, iclass 6, count 2 2006.173.09:48:02.28#ibcon#read 6, iclass 6, count 2 2006.173.09:48:02.28#ibcon#end of sib2, iclass 6, count 2 2006.173.09:48:02.28#ibcon#*mode == 0, iclass 6, count 2 2006.173.09:48:02.28#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.09:48:02.28#ibcon#[25=AT06-03\r\n] 2006.173.09:48:02.28#ibcon#*before write, iclass 6, count 2 2006.173.09:48:02.28#ibcon#enter sib2, iclass 6, count 2 2006.173.09:48:02.28#ibcon#flushed, iclass 6, count 2 2006.173.09:48:02.28#ibcon#about to write, iclass 6, count 2 2006.173.09:48:02.28#ibcon#wrote, iclass 6, count 2 2006.173.09:48:02.28#ibcon#about to read 3, iclass 6, count 2 2006.173.09:48:02.31#ibcon#read 3, iclass 6, count 2 2006.173.09:48:02.31#ibcon#about to read 4, iclass 6, count 2 2006.173.09:48:02.31#ibcon#read 4, iclass 6, count 2 2006.173.09:48:02.31#ibcon#about to read 5, iclass 6, count 2 2006.173.09:48:02.31#ibcon#read 5, iclass 6, count 2 2006.173.09:48:02.31#ibcon#about to read 6, iclass 6, count 2 2006.173.09:48:02.31#ibcon#read 6, iclass 6, count 2 2006.173.09:48:02.31#ibcon#end of sib2, iclass 6, count 2 2006.173.09:48:02.31#ibcon#*after write, iclass 6, count 2 2006.173.09:48:02.31#ibcon#*before return 0, iclass 6, count 2 2006.173.09:48:02.31#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.09:48:02.31#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.09:48:02.31#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.09:48:02.31#ibcon#ireg 7 cls_cnt 0 2006.173.09:48:02.31#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.09:48:02.43#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.09:48:02.43#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.09:48:02.43#ibcon#enter wrdev, iclass 6, count 0 2006.173.09:48:02.43#ibcon#first serial, iclass 6, count 0 2006.173.09:48:02.43#ibcon#enter sib2, iclass 6, count 0 2006.173.09:48:02.43#ibcon#flushed, iclass 6, count 0 2006.173.09:48:02.43#ibcon#about to write, iclass 6, count 0 2006.173.09:48:02.43#ibcon#wrote, iclass 6, count 0 2006.173.09:48:02.43#ibcon#about to read 3, iclass 6, count 0 2006.173.09:48:02.45#ibcon#read 3, iclass 6, count 0 2006.173.09:48:02.45#ibcon#about to read 4, iclass 6, count 0 2006.173.09:48:02.45#ibcon#read 4, iclass 6, count 0 2006.173.09:48:02.45#ibcon#about to read 5, iclass 6, count 0 2006.173.09:48:02.45#ibcon#read 5, iclass 6, count 0 2006.173.09:48:02.45#ibcon#about to read 6, iclass 6, count 0 2006.173.09:48:02.45#ibcon#read 6, iclass 6, count 0 2006.173.09:48:02.45#ibcon#end of sib2, iclass 6, count 0 2006.173.09:48:02.45#ibcon#*mode == 0, iclass 6, count 0 2006.173.09:48:02.45#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.09:48:02.45#ibcon#[25=USB\r\n] 2006.173.09:48:02.45#ibcon#*before write, iclass 6, count 0 2006.173.09:48:02.45#ibcon#enter sib2, iclass 6, count 0 2006.173.09:48:02.45#ibcon#flushed, iclass 6, count 0 2006.173.09:48:02.45#ibcon#about to write, iclass 6, count 0 2006.173.09:48:02.45#ibcon#wrote, iclass 6, count 0 2006.173.09:48:02.45#ibcon#about to read 3, iclass 6, count 0 2006.173.09:48:02.48#ibcon#read 3, iclass 6, count 0 2006.173.09:48:02.48#ibcon#about to read 4, iclass 6, count 0 2006.173.09:48:02.48#ibcon#read 4, iclass 6, count 0 2006.173.09:48:02.48#ibcon#about to read 5, iclass 6, count 0 2006.173.09:48:02.48#ibcon#read 5, iclass 6, count 0 2006.173.09:48:02.48#ibcon#about to read 6, iclass 6, count 0 2006.173.09:48:02.48#ibcon#read 6, iclass 6, count 0 2006.173.09:48:02.48#ibcon#end of sib2, iclass 6, count 0 2006.173.09:48:02.48#ibcon#*after write, iclass 6, count 0 2006.173.09:48:02.48#ibcon#*before return 0, iclass 6, count 0 2006.173.09:48:02.48#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.09:48:02.48#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.09:48:02.48#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.09:48:02.48#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.09:48:02.48$vck44/valo=7,864.99 2006.173.09:48:02.48#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.09:48:02.48#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.09:48:02.48#ibcon#ireg 17 cls_cnt 0 2006.173.09:48:02.48#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.09:48:02.48#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.09:48:02.48#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.09:48:02.48#ibcon#enter wrdev, iclass 10, count 0 2006.173.09:48:02.48#ibcon#first serial, iclass 10, count 0 2006.173.09:48:02.48#ibcon#enter sib2, iclass 10, count 0 2006.173.09:48:02.48#ibcon#flushed, iclass 10, count 0 2006.173.09:48:02.48#ibcon#about to write, iclass 10, count 0 2006.173.09:48:02.48#ibcon#wrote, iclass 10, count 0 2006.173.09:48:02.48#ibcon#about to read 3, iclass 10, count 0 2006.173.09:48:02.50#ibcon#read 3, iclass 10, count 0 2006.173.09:48:02.50#ibcon#about to read 4, iclass 10, count 0 2006.173.09:48:02.50#ibcon#read 4, iclass 10, count 0 2006.173.09:48:02.50#ibcon#about to read 5, iclass 10, count 0 2006.173.09:48:02.50#ibcon#read 5, iclass 10, count 0 2006.173.09:48:02.50#ibcon#about to read 6, iclass 10, count 0 2006.173.09:48:02.50#ibcon#read 6, iclass 10, count 0 2006.173.09:48:02.50#ibcon#end of sib2, iclass 10, count 0 2006.173.09:48:02.50#ibcon#*mode == 0, iclass 10, count 0 2006.173.09:48:02.50#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.09:48:02.50#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.09:48:02.50#ibcon#*before write, iclass 10, count 0 2006.173.09:48:02.50#ibcon#enter sib2, iclass 10, count 0 2006.173.09:48:02.50#ibcon#flushed, iclass 10, count 0 2006.173.09:48:02.50#ibcon#about to write, iclass 10, count 0 2006.173.09:48:02.50#ibcon#wrote, iclass 10, count 0 2006.173.09:48:02.50#ibcon#about to read 3, iclass 10, count 0 2006.173.09:48:02.54#ibcon#read 3, iclass 10, count 0 2006.173.09:48:02.54#ibcon#about to read 4, iclass 10, count 0 2006.173.09:48:02.54#ibcon#read 4, iclass 10, count 0 2006.173.09:48:02.54#ibcon#about to read 5, iclass 10, count 0 2006.173.09:48:02.54#ibcon#read 5, iclass 10, count 0 2006.173.09:48:02.54#ibcon#about to read 6, iclass 10, count 0 2006.173.09:48:02.54#ibcon#read 6, iclass 10, count 0 2006.173.09:48:02.54#ibcon#end of sib2, iclass 10, count 0 2006.173.09:48:02.54#ibcon#*after write, iclass 10, count 0 2006.173.09:48:02.54#ibcon#*before return 0, iclass 10, count 0 2006.173.09:48:02.54#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.09:48:02.54#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.09:48:02.54#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.09:48:02.54#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.09:48:02.54$vck44/va=7,4 2006.173.09:48:02.54#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.09:48:02.54#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.09:48:02.54#ibcon#ireg 11 cls_cnt 2 2006.173.09:48:02.54#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.09:48:02.60#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.09:48:02.60#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.09:48:02.60#ibcon#enter wrdev, iclass 12, count 2 2006.173.09:48:02.60#ibcon#first serial, iclass 12, count 2 2006.173.09:48:02.60#ibcon#enter sib2, iclass 12, count 2 2006.173.09:48:02.60#ibcon#flushed, iclass 12, count 2 2006.173.09:48:02.60#ibcon#about to write, iclass 12, count 2 2006.173.09:48:02.60#ibcon#wrote, iclass 12, count 2 2006.173.09:48:02.60#ibcon#about to read 3, iclass 12, count 2 2006.173.09:48:02.62#ibcon#read 3, iclass 12, count 2 2006.173.09:48:02.62#ibcon#about to read 4, iclass 12, count 2 2006.173.09:48:02.62#ibcon#read 4, iclass 12, count 2 2006.173.09:48:02.62#ibcon#about to read 5, iclass 12, count 2 2006.173.09:48:02.62#ibcon#read 5, iclass 12, count 2 2006.173.09:48:02.62#ibcon#about to read 6, iclass 12, count 2 2006.173.09:48:02.62#ibcon#read 6, iclass 12, count 2 2006.173.09:48:02.62#ibcon#end of sib2, iclass 12, count 2 2006.173.09:48:02.62#ibcon#*mode == 0, iclass 12, count 2 2006.173.09:48:02.62#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.09:48:02.62#ibcon#[25=AT07-04\r\n] 2006.173.09:48:02.62#ibcon#*before write, iclass 12, count 2 2006.173.09:48:02.62#ibcon#enter sib2, iclass 12, count 2 2006.173.09:48:02.62#ibcon#flushed, iclass 12, count 2 2006.173.09:48:02.62#ibcon#about to write, iclass 12, count 2 2006.173.09:48:02.62#ibcon#wrote, iclass 12, count 2 2006.173.09:48:02.62#ibcon#about to read 3, iclass 12, count 2 2006.173.09:48:02.65#ibcon#read 3, iclass 12, count 2 2006.173.09:48:02.65#ibcon#about to read 4, iclass 12, count 2 2006.173.09:48:02.65#ibcon#read 4, iclass 12, count 2 2006.173.09:48:02.65#ibcon#about to read 5, iclass 12, count 2 2006.173.09:48:02.65#ibcon#read 5, iclass 12, count 2 2006.173.09:48:02.65#ibcon#about to read 6, iclass 12, count 2 2006.173.09:48:02.65#ibcon#read 6, iclass 12, count 2 2006.173.09:48:02.65#ibcon#end of sib2, iclass 12, count 2 2006.173.09:48:02.65#ibcon#*after write, iclass 12, count 2 2006.173.09:48:02.65#ibcon#*before return 0, iclass 12, count 2 2006.173.09:48:02.65#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.09:48:02.65#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.09:48:02.65#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.09:48:02.65#ibcon#ireg 7 cls_cnt 0 2006.173.09:48:02.65#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.09:48:02.77#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.09:48:02.77#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.09:48:02.77#ibcon#enter wrdev, iclass 12, count 0 2006.173.09:48:02.77#ibcon#first serial, iclass 12, count 0 2006.173.09:48:02.77#ibcon#enter sib2, iclass 12, count 0 2006.173.09:48:02.77#ibcon#flushed, iclass 12, count 0 2006.173.09:48:02.77#ibcon#about to write, iclass 12, count 0 2006.173.09:48:02.77#ibcon#wrote, iclass 12, count 0 2006.173.09:48:02.77#ibcon#about to read 3, iclass 12, count 0 2006.173.09:48:02.79#ibcon#read 3, iclass 12, count 0 2006.173.09:48:02.79#ibcon#about to read 4, iclass 12, count 0 2006.173.09:48:02.79#ibcon#read 4, iclass 12, count 0 2006.173.09:48:02.79#ibcon#about to read 5, iclass 12, count 0 2006.173.09:48:02.79#ibcon#read 5, iclass 12, count 0 2006.173.09:48:02.79#ibcon#about to read 6, iclass 12, count 0 2006.173.09:48:02.79#ibcon#read 6, iclass 12, count 0 2006.173.09:48:02.79#ibcon#end of sib2, iclass 12, count 0 2006.173.09:48:02.79#ibcon#*mode == 0, iclass 12, count 0 2006.173.09:48:02.79#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.09:48:02.79#ibcon#[25=USB\r\n] 2006.173.09:48:02.79#ibcon#*before write, iclass 12, count 0 2006.173.09:48:02.79#ibcon#enter sib2, iclass 12, count 0 2006.173.09:48:02.79#ibcon#flushed, iclass 12, count 0 2006.173.09:48:02.79#ibcon#about to write, iclass 12, count 0 2006.173.09:48:02.79#ibcon#wrote, iclass 12, count 0 2006.173.09:48:02.79#ibcon#about to read 3, iclass 12, count 0 2006.173.09:48:02.82#ibcon#read 3, iclass 12, count 0 2006.173.09:48:02.82#ibcon#about to read 4, iclass 12, count 0 2006.173.09:48:02.82#ibcon#read 4, iclass 12, count 0 2006.173.09:48:02.82#ibcon#about to read 5, iclass 12, count 0 2006.173.09:48:02.82#ibcon#read 5, iclass 12, count 0 2006.173.09:48:02.82#ibcon#about to read 6, iclass 12, count 0 2006.173.09:48:02.82#ibcon#read 6, iclass 12, count 0 2006.173.09:48:02.82#ibcon#end of sib2, iclass 12, count 0 2006.173.09:48:02.82#ibcon#*after write, iclass 12, count 0 2006.173.09:48:02.82#ibcon#*before return 0, iclass 12, count 0 2006.173.09:48:02.82#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.09:48:02.82#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.09:48:02.82#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.09:48:02.82#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.09:48:02.82$vck44/valo=8,884.99 2006.173.09:48:02.82#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.09:48:02.82#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.09:48:02.82#ibcon#ireg 17 cls_cnt 0 2006.173.09:48:02.82#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.09:48:02.82#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.09:48:02.82#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.09:48:02.82#ibcon#enter wrdev, iclass 14, count 0 2006.173.09:48:02.82#ibcon#first serial, iclass 14, count 0 2006.173.09:48:02.82#ibcon#enter sib2, iclass 14, count 0 2006.173.09:48:02.82#ibcon#flushed, iclass 14, count 0 2006.173.09:48:02.82#ibcon#about to write, iclass 14, count 0 2006.173.09:48:02.82#ibcon#wrote, iclass 14, count 0 2006.173.09:48:02.82#ibcon#about to read 3, iclass 14, count 0 2006.173.09:48:02.84#ibcon#read 3, iclass 14, count 0 2006.173.09:48:02.84#ibcon#about to read 4, iclass 14, count 0 2006.173.09:48:02.84#ibcon#read 4, iclass 14, count 0 2006.173.09:48:02.84#ibcon#about to read 5, iclass 14, count 0 2006.173.09:48:02.84#ibcon#read 5, iclass 14, count 0 2006.173.09:48:02.84#ibcon#about to read 6, iclass 14, count 0 2006.173.09:48:02.84#ibcon#read 6, iclass 14, count 0 2006.173.09:48:02.84#ibcon#end of sib2, iclass 14, count 0 2006.173.09:48:02.84#ibcon#*mode == 0, iclass 14, count 0 2006.173.09:48:02.84#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.09:48:02.84#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.09:48:02.84#ibcon#*before write, iclass 14, count 0 2006.173.09:48:02.84#ibcon#enter sib2, iclass 14, count 0 2006.173.09:48:02.84#ibcon#flushed, iclass 14, count 0 2006.173.09:48:02.84#ibcon#about to write, iclass 14, count 0 2006.173.09:48:02.84#ibcon#wrote, iclass 14, count 0 2006.173.09:48:02.84#ibcon#about to read 3, iclass 14, count 0 2006.173.09:48:02.88#ibcon#read 3, iclass 14, count 0 2006.173.09:48:02.88#ibcon#about to read 4, iclass 14, count 0 2006.173.09:48:02.88#ibcon#read 4, iclass 14, count 0 2006.173.09:48:02.88#ibcon#about to read 5, iclass 14, count 0 2006.173.09:48:02.88#ibcon#read 5, iclass 14, count 0 2006.173.09:48:02.88#ibcon#about to read 6, iclass 14, count 0 2006.173.09:48:02.88#ibcon#read 6, iclass 14, count 0 2006.173.09:48:02.88#ibcon#end of sib2, iclass 14, count 0 2006.173.09:48:02.88#ibcon#*after write, iclass 14, count 0 2006.173.09:48:02.88#ibcon#*before return 0, iclass 14, count 0 2006.173.09:48:02.88#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.09:48:02.88#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.09:48:02.88#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.09:48:02.88#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.09:48:02.88$vck44/va=8,4 2006.173.09:48:02.88#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.09:48:02.88#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.09:48:02.88#ibcon#ireg 11 cls_cnt 2 2006.173.09:48:02.88#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.09:48:02.94#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.09:48:02.94#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.09:48:02.94#ibcon#enter wrdev, iclass 16, count 2 2006.173.09:48:02.94#ibcon#first serial, iclass 16, count 2 2006.173.09:48:02.94#ibcon#enter sib2, iclass 16, count 2 2006.173.09:48:02.94#ibcon#flushed, iclass 16, count 2 2006.173.09:48:02.94#ibcon#about to write, iclass 16, count 2 2006.173.09:48:02.94#ibcon#wrote, iclass 16, count 2 2006.173.09:48:02.94#ibcon#about to read 3, iclass 16, count 2 2006.173.09:48:02.96#ibcon#read 3, iclass 16, count 2 2006.173.09:48:02.96#ibcon#about to read 4, iclass 16, count 2 2006.173.09:48:02.96#ibcon#read 4, iclass 16, count 2 2006.173.09:48:02.96#ibcon#about to read 5, iclass 16, count 2 2006.173.09:48:02.96#ibcon#read 5, iclass 16, count 2 2006.173.09:48:02.96#ibcon#about to read 6, iclass 16, count 2 2006.173.09:48:02.96#ibcon#read 6, iclass 16, count 2 2006.173.09:48:02.96#ibcon#end of sib2, iclass 16, count 2 2006.173.09:48:02.96#ibcon#*mode == 0, iclass 16, count 2 2006.173.09:48:02.96#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.09:48:02.96#ibcon#[25=AT08-04\r\n] 2006.173.09:48:02.96#ibcon#*before write, iclass 16, count 2 2006.173.09:48:02.96#ibcon#enter sib2, iclass 16, count 2 2006.173.09:48:02.96#ibcon#flushed, iclass 16, count 2 2006.173.09:48:02.96#ibcon#about to write, iclass 16, count 2 2006.173.09:48:02.96#ibcon#wrote, iclass 16, count 2 2006.173.09:48:02.96#ibcon#about to read 3, iclass 16, count 2 2006.173.09:48:02.99#ibcon#read 3, iclass 16, count 2 2006.173.09:48:02.99#ibcon#about to read 4, iclass 16, count 2 2006.173.09:48:02.99#ibcon#read 4, iclass 16, count 2 2006.173.09:48:02.99#ibcon#about to read 5, iclass 16, count 2 2006.173.09:48:02.99#ibcon#read 5, iclass 16, count 2 2006.173.09:48:02.99#ibcon#about to read 6, iclass 16, count 2 2006.173.09:48:02.99#ibcon#read 6, iclass 16, count 2 2006.173.09:48:02.99#ibcon#end of sib2, iclass 16, count 2 2006.173.09:48:02.99#ibcon#*after write, iclass 16, count 2 2006.173.09:48:02.99#ibcon#*before return 0, iclass 16, count 2 2006.173.09:48:02.99#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.09:48:02.99#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.09:48:02.99#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.09:48:02.99#ibcon#ireg 7 cls_cnt 0 2006.173.09:48:02.99#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.09:48:03.11#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.09:48:03.11#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.09:48:03.11#ibcon#enter wrdev, iclass 16, count 0 2006.173.09:48:03.11#ibcon#first serial, iclass 16, count 0 2006.173.09:48:03.11#ibcon#enter sib2, iclass 16, count 0 2006.173.09:48:03.11#ibcon#flushed, iclass 16, count 0 2006.173.09:48:03.11#ibcon#about to write, iclass 16, count 0 2006.173.09:48:03.11#ibcon#wrote, iclass 16, count 0 2006.173.09:48:03.11#ibcon#about to read 3, iclass 16, count 0 2006.173.09:48:03.13#ibcon#read 3, iclass 16, count 0 2006.173.09:48:03.13#ibcon#about to read 4, iclass 16, count 0 2006.173.09:48:03.13#ibcon#read 4, iclass 16, count 0 2006.173.09:48:03.13#ibcon#about to read 5, iclass 16, count 0 2006.173.09:48:03.13#ibcon#read 5, iclass 16, count 0 2006.173.09:48:03.13#ibcon#about to read 6, iclass 16, count 0 2006.173.09:48:03.13#ibcon#read 6, iclass 16, count 0 2006.173.09:48:03.13#ibcon#end of sib2, iclass 16, count 0 2006.173.09:48:03.13#ibcon#*mode == 0, iclass 16, count 0 2006.173.09:48:03.13#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.09:48:03.13#ibcon#[25=USB\r\n] 2006.173.09:48:03.13#ibcon#*before write, iclass 16, count 0 2006.173.09:48:03.13#ibcon#enter sib2, iclass 16, count 0 2006.173.09:48:03.13#ibcon#flushed, iclass 16, count 0 2006.173.09:48:03.13#ibcon#about to write, iclass 16, count 0 2006.173.09:48:03.13#ibcon#wrote, iclass 16, count 0 2006.173.09:48:03.13#ibcon#about to read 3, iclass 16, count 0 2006.173.09:48:03.16#ibcon#read 3, iclass 16, count 0 2006.173.09:48:03.16#ibcon#about to read 4, iclass 16, count 0 2006.173.09:48:03.16#ibcon#read 4, iclass 16, count 0 2006.173.09:48:03.16#ibcon#about to read 5, iclass 16, count 0 2006.173.09:48:03.16#ibcon#read 5, iclass 16, count 0 2006.173.09:48:03.16#ibcon#about to read 6, iclass 16, count 0 2006.173.09:48:03.16#ibcon#read 6, iclass 16, count 0 2006.173.09:48:03.16#ibcon#end of sib2, iclass 16, count 0 2006.173.09:48:03.16#ibcon#*after write, iclass 16, count 0 2006.173.09:48:03.16#ibcon#*before return 0, iclass 16, count 0 2006.173.09:48:03.16#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.09:48:03.16#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.09:48:03.16#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.09:48:03.16#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.09:48:03.16$vck44/vblo=1,629.99 2006.173.09:48:03.16#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.09:48:03.16#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.09:48:03.16#ibcon#ireg 17 cls_cnt 0 2006.173.09:48:03.16#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.09:48:03.16#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.09:48:03.16#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.09:48:03.16#ibcon#enter wrdev, iclass 18, count 0 2006.173.09:48:03.16#ibcon#first serial, iclass 18, count 0 2006.173.09:48:03.16#ibcon#enter sib2, iclass 18, count 0 2006.173.09:48:03.16#ibcon#flushed, iclass 18, count 0 2006.173.09:48:03.16#ibcon#about to write, iclass 18, count 0 2006.173.09:48:03.16#ibcon#wrote, iclass 18, count 0 2006.173.09:48:03.16#ibcon#about to read 3, iclass 18, count 0 2006.173.09:48:03.18#ibcon#read 3, iclass 18, count 0 2006.173.09:48:03.18#ibcon#about to read 4, iclass 18, count 0 2006.173.09:48:03.18#ibcon#read 4, iclass 18, count 0 2006.173.09:48:03.18#ibcon#about to read 5, iclass 18, count 0 2006.173.09:48:03.18#ibcon#read 5, iclass 18, count 0 2006.173.09:48:03.18#ibcon#about to read 6, iclass 18, count 0 2006.173.09:48:03.18#ibcon#read 6, iclass 18, count 0 2006.173.09:48:03.18#ibcon#end of sib2, iclass 18, count 0 2006.173.09:48:03.18#ibcon#*mode == 0, iclass 18, count 0 2006.173.09:48:03.18#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.09:48:03.18#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.09:48:03.18#ibcon#*before write, iclass 18, count 0 2006.173.09:48:03.18#ibcon#enter sib2, iclass 18, count 0 2006.173.09:48:03.18#ibcon#flushed, iclass 18, count 0 2006.173.09:48:03.18#ibcon#about to write, iclass 18, count 0 2006.173.09:48:03.18#ibcon#wrote, iclass 18, count 0 2006.173.09:48:03.18#ibcon#about to read 3, iclass 18, count 0 2006.173.09:48:03.22#ibcon#read 3, iclass 18, count 0 2006.173.09:48:03.22#ibcon#about to read 4, iclass 18, count 0 2006.173.09:48:03.22#ibcon#read 4, iclass 18, count 0 2006.173.09:48:03.22#ibcon#about to read 5, iclass 18, count 0 2006.173.09:48:03.22#ibcon#read 5, iclass 18, count 0 2006.173.09:48:03.22#ibcon#about to read 6, iclass 18, count 0 2006.173.09:48:03.22#ibcon#read 6, iclass 18, count 0 2006.173.09:48:03.22#ibcon#end of sib2, iclass 18, count 0 2006.173.09:48:03.22#ibcon#*after write, iclass 18, count 0 2006.173.09:48:03.22#ibcon#*before return 0, iclass 18, count 0 2006.173.09:48:03.22#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.09:48:03.22#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.09:48:03.22#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.09:48:03.22#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.09:48:03.22$vck44/vb=1,4 2006.173.09:48:03.22#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.09:48:03.22#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.09:48:03.22#ibcon#ireg 11 cls_cnt 2 2006.173.09:48:03.22#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.09:48:03.22#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.09:48:03.22#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.09:48:03.22#ibcon#enter wrdev, iclass 20, count 2 2006.173.09:48:03.22#ibcon#first serial, iclass 20, count 2 2006.173.09:48:03.22#ibcon#enter sib2, iclass 20, count 2 2006.173.09:48:03.22#ibcon#flushed, iclass 20, count 2 2006.173.09:48:03.22#ibcon#about to write, iclass 20, count 2 2006.173.09:48:03.22#ibcon#wrote, iclass 20, count 2 2006.173.09:48:03.22#ibcon#about to read 3, iclass 20, count 2 2006.173.09:48:03.24#ibcon#read 3, iclass 20, count 2 2006.173.09:48:03.24#ibcon#about to read 4, iclass 20, count 2 2006.173.09:48:03.24#ibcon#read 4, iclass 20, count 2 2006.173.09:48:03.24#ibcon#about to read 5, iclass 20, count 2 2006.173.09:48:03.24#ibcon#read 5, iclass 20, count 2 2006.173.09:48:03.24#ibcon#about to read 6, iclass 20, count 2 2006.173.09:48:03.24#ibcon#read 6, iclass 20, count 2 2006.173.09:48:03.24#ibcon#end of sib2, iclass 20, count 2 2006.173.09:48:03.24#ibcon#*mode == 0, iclass 20, count 2 2006.173.09:48:03.24#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.09:48:03.24#ibcon#[27=AT01-04\r\n] 2006.173.09:48:03.24#ibcon#*before write, iclass 20, count 2 2006.173.09:48:03.24#ibcon#enter sib2, iclass 20, count 2 2006.173.09:48:03.24#ibcon#flushed, iclass 20, count 2 2006.173.09:48:03.24#ibcon#about to write, iclass 20, count 2 2006.173.09:48:03.24#ibcon#wrote, iclass 20, count 2 2006.173.09:48:03.24#ibcon#about to read 3, iclass 20, count 2 2006.173.09:48:03.27#ibcon#read 3, iclass 20, count 2 2006.173.09:48:03.27#ibcon#about to read 4, iclass 20, count 2 2006.173.09:48:03.27#ibcon#read 4, iclass 20, count 2 2006.173.09:48:03.27#ibcon#about to read 5, iclass 20, count 2 2006.173.09:48:03.27#ibcon#read 5, iclass 20, count 2 2006.173.09:48:03.27#ibcon#about to read 6, iclass 20, count 2 2006.173.09:48:03.27#ibcon#read 6, iclass 20, count 2 2006.173.09:48:03.27#ibcon#end of sib2, iclass 20, count 2 2006.173.09:48:03.27#ibcon#*after write, iclass 20, count 2 2006.173.09:48:03.27#ibcon#*before return 0, iclass 20, count 2 2006.173.09:48:03.27#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.09:48:03.27#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.09:48:03.27#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.09:48:03.27#ibcon#ireg 7 cls_cnt 0 2006.173.09:48:03.27#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.09:48:03.39#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.09:48:03.39#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.09:48:03.39#ibcon#enter wrdev, iclass 20, count 0 2006.173.09:48:03.39#ibcon#first serial, iclass 20, count 0 2006.173.09:48:03.39#ibcon#enter sib2, iclass 20, count 0 2006.173.09:48:03.39#ibcon#flushed, iclass 20, count 0 2006.173.09:48:03.39#ibcon#about to write, iclass 20, count 0 2006.173.09:48:03.39#ibcon#wrote, iclass 20, count 0 2006.173.09:48:03.39#ibcon#about to read 3, iclass 20, count 0 2006.173.09:48:03.41#ibcon#read 3, iclass 20, count 0 2006.173.09:48:03.41#ibcon#about to read 4, iclass 20, count 0 2006.173.09:48:03.41#ibcon#read 4, iclass 20, count 0 2006.173.09:48:03.41#ibcon#about to read 5, iclass 20, count 0 2006.173.09:48:03.41#ibcon#read 5, iclass 20, count 0 2006.173.09:48:03.41#ibcon#about to read 6, iclass 20, count 0 2006.173.09:48:03.41#ibcon#read 6, iclass 20, count 0 2006.173.09:48:03.41#ibcon#end of sib2, iclass 20, count 0 2006.173.09:48:03.41#ibcon#*mode == 0, iclass 20, count 0 2006.173.09:48:03.41#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.09:48:03.41#ibcon#[27=USB\r\n] 2006.173.09:48:03.41#ibcon#*before write, iclass 20, count 0 2006.173.09:48:03.41#ibcon#enter sib2, iclass 20, count 0 2006.173.09:48:03.41#ibcon#flushed, iclass 20, count 0 2006.173.09:48:03.41#ibcon#about to write, iclass 20, count 0 2006.173.09:48:03.41#ibcon#wrote, iclass 20, count 0 2006.173.09:48:03.41#ibcon#about to read 3, iclass 20, count 0 2006.173.09:48:03.44#ibcon#read 3, iclass 20, count 0 2006.173.09:48:03.44#ibcon#about to read 4, iclass 20, count 0 2006.173.09:48:03.44#ibcon#read 4, iclass 20, count 0 2006.173.09:48:03.44#ibcon#about to read 5, iclass 20, count 0 2006.173.09:48:03.44#ibcon#read 5, iclass 20, count 0 2006.173.09:48:03.44#ibcon#about to read 6, iclass 20, count 0 2006.173.09:48:03.44#ibcon#read 6, iclass 20, count 0 2006.173.09:48:03.44#ibcon#end of sib2, iclass 20, count 0 2006.173.09:48:03.44#ibcon#*after write, iclass 20, count 0 2006.173.09:48:03.44#ibcon#*before return 0, iclass 20, count 0 2006.173.09:48:03.44#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.09:48:03.44#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.09:48:03.44#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.09:48:03.44#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.09:48:03.44$vck44/vblo=2,634.99 2006.173.09:48:03.44#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.09:48:03.44#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.09:48:03.44#ibcon#ireg 17 cls_cnt 0 2006.173.09:48:03.44#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.09:48:03.44#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.09:48:03.44#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.09:48:03.44#ibcon#enter wrdev, iclass 22, count 0 2006.173.09:48:03.44#ibcon#first serial, iclass 22, count 0 2006.173.09:48:03.44#ibcon#enter sib2, iclass 22, count 0 2006.173.09:48:03.44#ibcon#flushed, iclass 22, count 0 2006.173.09:48:03.44#ibcon#about to write, iclass 22, count 0 2006.173.09:48:03.44#ibcon#wrote, iclass 22, count 0 2006.173.09:48:03.44#ibcon#about to read 3, iclass 22, count 0 2006.173.09:48:03.46#ibcon#read 3, iclass 22, count 0 2006.173.09:48:03.46#ibcon#about to read 4, iclass 22, count 0 2006.173.09:48:03.46#ibcon#read 4, iclass 22, count 0 2006.173.09:48:03.46#ibcon#about to read 5, iclass 22, count 0 2006.173.09:48:03.46#ibcon#read 5, iclass 22, count 0 2006.173.09:48:03.46#ibcon#about to read 6, iclass 22, count 0 2006.173.09:48:03.46#ibcon#read 6, iclass 22, count 0 2006.173.09:48:03.46#ibcon#end of sib2, iclass 22, count 0 2006.173.09:48:03.46#ibcon#*mode == 0, iclass 22, count 0 2006.173.09:48:03.46#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.09:48:03.46#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.09:48:03.46#ibcon#*before write, iclass 22, count 0 2006.173.09:48:03.46#ibcon#enter sib2, iclass 22, count 0 2006.173.09:48:03.46#ibcon#flushed, iclass 22, count 0 2006.173.09:48:03.46#ibcon#about to write, iclass 22, count 0 2006.173.09:48:03.46#ibcon#wrote, iclass 22, count 0 2006.173.09:48:03.46#ibcon#about to read 3, iclass 22, count 0 2006.173.09:48:03.50#ibcon#read 3, iclass 22, count 0 2006.173.09:48:03.50#ibcon#about to read 4, iclass 22, count 0 2006.173.09:48:03.50#ibcon#read 4, iclass 22, count 0 2006.173.09:48:03.50#ibcon#about to read 5, iclass 22, count 0 2006.173.09:48:03.50#ibcon#read 5, iclass 22, count 0 2006.173.09:48:03.50#ibcon#about to read 6, iclass 22, count 0 2006.173.09:48:03.50#ibcon#read 6, iclass 22, count 0 2006.173.09:48:03.50#ibcon#end of sib2, iclass 22, count 0 2006.173.09:48:03.50#ibcon#*after write, iclass 22, count 0 2006.173.09:48:03.50#ibcon#*before return 0, iclass 22, count 0 2006.173.09:48:03.50#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.09:48:03.50#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.09:48:03.50#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.09:48:03.50#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.09:48:03.50$vck44/vb=2,4 2006.173.09:48:03.50#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.09:48:03.50#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.09:48:03.50#ibcon#ireg 11 cls_cnt 2 2006.173.09:48:03.50#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.09:48:03.56#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.09:48:03.56#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.09:48:03.56#ibcon#enter wrdev, iclass 24, count 2 2006.173.09:48:03.56#ibcon#first serial, iclass 24, count 2 2006.173.09:48:03.56#ibcon#enter sib2, iclass 24, count 2 2006.173.09:48:03.56#ibcon#flushed, iclass 24, count 2 2006.173.09:48:03.56#ibcon#about to write, iclass 24, count 2 2006.173.09:48:03.56#ibcon#wrote, iclass 24, count 2 2006.173.09:48:03.56#ibcon#about to read 3, iclass 24, count 2 2006.173.09:48:03.58#ibcon#read 3, iclass 24, count 2 2006.173.09:48:03.58#ibcon#about to read 4, iclass 24, count 2 2006.173.09:48:03.58#ibcon#read 4, iclass 24, count 2 2006.173.09:48:03.58#ibcon#about to read 5, iclass 24, count 2 2006.173.09:48:03.58#ibcon#read 5, iclass 24, count 2 2006.173.09:48:03.58#ibcon#about to read 6, iclass 24, count 2 2006.173.09:48:03.58#ibcon#read 6, iclass 24, count 2 2006.173.09:48:03.58#ibcon#end of sib2, iclass 24, count 2 2006.173.09:48:03.58#ibcon#*mode == 0, iclass 24, count 2 2006.173.09:48:03.58#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.09:48:03.58#ibcon#[27=AT02-04\r\n] 2006.173.09:48:03.58#ibcon#*before write, iclass 24, count 2 2006.173.09:48:03.58#ibcon#enter sib2, iclass 24, count 2 2006.173.09:48:03.58#ibcon#flushed, iclass 24, count 2 2006.173.09:48:03.58#ibcon#about to write, iclass 24, count 2 2006.173.09:48:03.58#ibcon#wrote, iclass 24, count 2 2006.173.09:48:03.58#ibcon#about to read 3, iclass 24, count 2 2006.173.09:48:03.61#ibcon#read 3, iclass 24, count 2 2006.173.09:48:03.61#ibcon#about to read 4, iclass 24, count 2 2006.173.09:48:03.61#ibcon#read 4, iclass 24, count 2 2006.173.09:48:03.61#ibcon#about to read 5, iclass 24, count 2 2006.173.09:48:03.61#ibcon#read 5, iclass 24, count 2 2006.173.09:48:03.61#ibcon#about to read 6, iclass 24, count 2 2006.173.09:48:03.61#ibcon#read 6, iclass 24, count 2 2006.173.09:48:03.61#ibcon#end of sib2, iclass 24, count 2 2006.173.09:48:03.61#ibcon#*after write, iclass 24, count 2 2006.173.09:48:03.61#ibcon#*before return 0, iclass 24, count 2 2006.173.09:48:03.61#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.09:48:03.61#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.09:48:03.61#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.09:48:03.61#ibcon#ireg 7 cls_cnt 0 2006.173.09:48:03.61#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.09:48:03.73#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.09:48:03.73#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.09:48:03.73#ibcon#enter wrdev, iclass 24, count 0 2006.173.09:48:03.73#ibcon#first serial, iclass 24, count 0 2006.173.09:48:03.73#ibcon#enter sib2, iclass 24, count 0 2006.173.09:48:03.73#ibcon#flushed, iclass 24, count 0 2006.173.09:48:03.73#ibcon#about to write, iclass 24, count 0 2006.173.09:48:03.73#ibcon#wrote, iclass 24, count 0 2006.173.09:48:03.73#ibcon#about to read 3, iclass 24, count 0 2006.173.09:48:03.75#ibcon#read 3, iclass 24, count 0 2006.173.09:48:03.75#ibcon#about to read 4, iclass 24, count 0 2006.173.09:48:03.75#ibcon#read 4, iclass 24, count 0 2006.173.09:48:03.75#ibcon#about to read 5, iclass 24, count 0 2006.173.09:48:03.75#ibcon#read 5, iclass 24, count 0 2006.173.09:48:03.75#ibcon#about to read 6, iclass 24, count 0 2006.173.09:48:03.75#ibcon#read 6, iclass 24, count 0 2006.173.09:48:03.75#ibcon#end of sib2, iclass 24, count 0 2006.173.09:48:03.75#ibcon#*mode == 0, iclass 24, count 0 2006.173.09:48:03.75#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.09:48:03.75#ibcon#[27=USB\r\n] 2006.173.09:48:03.75#ibcon#*before write, iclass 24, count 0 2006.173.09:48:03.75#ibcon#enter sib2, iclass 24, count 0 2006.173.09:48:03.75#ibcon#flushed, iclass 24, count 0 2006.173.09:48:03.75#ibcon#about to write, iclass 24, count 0 2006.173.09:48:03.75#ibcon#wrote, iclass 24, count 0 2006.173.09:48:03.75#ibcon#about to read 3, iclass 24, count 0 2006.173.09:48:03.78#ibcon#read 3, iclass 24, count 0 2006.173.09:48:03.78#ibcon#about to read 4, iclass 24, count 0 2006.173.09:48:03.78#ibcon#read 4, iclass 24, count 0 2006.173.09:48:03.78#ibcon#about to read 5, iclass 24, count 0 2006.173.09:48:03.78#ibcon#read 5, iclass 24, count 0 2006.173.09:48:03.78#ibcon#about to read 6, iclass 24, count 0 2006.173.09:48:03.78#ibcon#read 6, iclass 24, count 0 2006.173.09:48:03.78#ibcon#end of sib2, iclass 24, count 0 2006.173.09:48:03.78#ibcon#*after write, iclass 24, count 0 2006.173.09:48:03.78#ibcon#*before return 0, iclass 24, count 0 2006.173.09:48:03.78#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.09:48:03.78#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.09:48:03.78#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.09:48:03.78#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.09:48:03.78$vck44/vblo=3,649.99 2006.173.09:48:03.78#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.09:48:03.78#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.09:48:03.78#ibcon#ireg 17 cls_cnt 0 2006.173.09:48:03.78#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.09:48:03.78#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.09:48:03.78#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.09:48:03.78#ibcon#enter wrdev, iclass 26, count 0 2006.173.09:48:03.78#ibcon#first serial, iclass 26, count 0 2006.173.09:48:03.78#ibcon#enter sib2, iclass 26, count 0 2006.173.09:48:03.78#ibcon#flushed, iclass 26, count 0 2006.173.09:48:03.78#ibcon#about to write, iclass 26, count 0 2006.173.09:48:03.78#ibcon#wrote, iclass 26, count 0 2006.173.09:48:03.78#ibcon#about to read 3, iclass 26, count 0 2006.173.09:48:03.80#ibcon#read 3, iclass 26, count 0 2006.173.09:48:03.80#ibcon#about to read 4, iclass 26, count 0 2006.173.09:48:03.80#ibcon#read 4, iclass 26, count 0 2006.173.09:48:03.80#ibcon#about to read 5, iclass 26, count 0 2006.173.09:48:03.80#ibcon#read 5, iclass 26, count 0 2006.173.09:48:03.80#ibcon#about to read 6, iclass 26, count 0 2006.173.09:48:03.80#ibcon#read 6, iclass 26, count 0 2006.173.09:48:03.80#ibcon#end of sib2, iclass 26, count 0 2006.173.09:48:03.80#ibcon#*mode == 0, iclass 26, count 0 2006.173.09:48:03.80#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.09:48:03.80#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.09:48:03.80#ibcon#*before write, iclass 26, count 0 2006.173.09:48:03.80#ibcon#enter sib2, iclass 26, count 0 2006.173.09:48:03.80#ibcon#flushed, iclass 26, count 0 2006.173.09:48:03.80#ibcon#about to write, iclass 26, count 0 2006.173.09:48:03.80#ibcon#wrote, iclass 26, count 0 2006.173.09:48:03.80#ibcon#about to read 3, iclass 26, count 0 2006.173.09:48:03.84#ibcon#read 3, iclass 26, count 0 2006.173.09:48:03.84#ibcon#about to read 4, iclass 26, count 0 2006.173.09:48:03.84#ibcon#read 4, iclass 26, count 0 2006.173.09:48:03.84#ibcon#about to read 5, iclass 26, count 0 2006.173.09:48:03.84#ibcon#read 5, iclass 26, count 0 2006.173.09:48:03.84#ibcon#about to read 6, iclass 26, count 0 2006.173.09:48:03.84#ibcon#read 6, iclass 26, count 0 2006.173.09:48:03.84#ibcon#end of sib2, iclass 26, count 0 2006.173.09:48:03.84#ibcon#*after write, iclass 26, count 0 2006.173.09:48:03.84#ibcon#*before return 0, iclass 26, count 0 2006.173.09:48:03.84#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.09:48:03.84#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.09:48:03.84#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.09:48:03.84#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.09:48:03.84$vck44/vb=3,4 2006.173.09:48:03.84#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.09:48:03.84#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.09:48:03.84#ibcon#ireg 11 cls_cnt 2 2006.173.09:48:03.84#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.09:48:03.90#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.09:48:03.90#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.09:48:03.90#ibcon#enter wrdev, iclass 28, count 2 2006.173.09:48:03.90#ibcon#first serial, iclass 28, count 2 2006.173.09:48:03.90#ibcon#enter sib2, iclass 28, count 2 2006.173.09:48:03.90#ibcon#flushed, iclass 28, count 2 2006.173.09:48:03.90#ibcon#about to write, iclass 28, count 2 2006.173.09:48:03.90#ibcon#wrote, iclass 28, count 2 2006.173.09:48:03.90#ibcon#about to read 3, iclass 28, count 2 2006.173.09:48:03.92#ibcon#read 3, iclass 28, count 2 2006.173.09:48:03.92#ibcon#about to read 4, iclass 28, count 2 2006.173.09:48:03.92#ibcon#read 4, iclass 28, count 2 2006.173.09:48:03.92#ibcon#about to read 5, iclass 28, count 2 2006.173.09:48:03.92#ibcon#read 5, iclass 28, count 2 2006.173.09:48:03.92#ibcon#about to read 6, iclass 28, count 2 2006.173.09:48:03.92#ibcon#read 6, iclass 28, count 2 2006.173.09:48:03.92#ibcon#end of sib2, iclass 28, count 2 2006.173.09:48:03.92#ibcon#*mode == 0, iclass 28, count 2 2006.173.09:48:03.92#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.09:48:03.92#ibcon#[27=AT03-04\r\n] 2006.173.09:48:03.92#ibcon#*before write, iclass 28, count 2 2006.173.09:48:03.92#ibcon#enter sib2, iclass 28, count 2 2006.173.09:48:03.92#ibcon#flushed, iclass 28, count 2 2006.173.09:48:03.92#ibcon#about to write, iclass 28, count 2 2006.173.09:48:03.92#ibcon#wrote, iclass 28, count 2 2006.173.09:48:03.92#ibcon#about to read 3, iclass 28, count 2 2006.173.09:48:03.95#ibcon#read 3, iclass 28, count 2 2006.173.09:48:03.96#ibcon#about to read 4, iclass 28, count 2 2006.173.09:48:03.96#ibcon#read 4, iclass 28, count 2 2006.173.09:48:03.96#ibcon#about to read 5, iclass 28, count 2 2006.173.09:48:03.96#ibcon#read 5, iclass 28, count 2 2006.173.09:48:03.96#ibcon#about to read 6, iclass 28, count 2 2006.173.09:48:03.96#ibcon#read 6, iclass 28, count 2 2006.173.09:48:03.96#ibcon#end of sib2, iclass 28, count 2 2006.173.09:48:03.96#ibcon#*after write, iclass 28, count 2 2006.173.09:48:03.96#ibcon#*before return 0, iclass 28, count 2 2006.173.09:48:03.96#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.09:48:03.97#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.09:48:03.97#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.09:48:03.97#ibcon#ireg 7 cls_cnt 0 2006.173.09:48:03.97#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.09:48:04.07#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.09:48:04.07#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.09:48:04.07#ibcon#enter wrdev, iclass 28, count 0 2006.173.09:48:04.07#ibcon#first serial, iclass 28, count 0 2006.173.09:48:04.07#ibcon#enter sib2, iclass 28, count 0 2006.173.09:48:04.07#ibcon#flushed, iclass 28, count 0 2006.173.09:48:04.07#ibcon#about to write, iclass 28, count 0 2006.173.09:48:04.07#ibcon#wrote, iclass 28, count 0 2006.173.09:48:04.07#ibcon#about to read 3, iclass 28, count 0 2006.173.09:48:04.09#ibcon#read 3, iclass 28, count 0 2006.173.09:48:04.09#ibcon#about to read 4, iclass 28, count 0 2006.173.09:48:04.09#ibcon#read 4, iclass 28, count 0 2006.173.09:48:04.09#ibcon#about to read 5, iclass 28, count 0 2006.173.09:48:04.09#ibcon#read 5, iclass 28, count 0 2006.173.09:48:04.09#ibcon#about to read 6, iclass 28, count 0 2006.173.09:48:04.09#ibcon#read 6, iclass 28, count 0 2006.173.09:48:04.09#ibcon#end of sib2, iclass 28, count 0 2006.173.09:48:04.09#ibcon#*mode == 0, iclass 28, count 0 2006.173.09:48:04.09#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.09:48:04.09#ibcon#[27=USB\r\n] 2006.173.09:48:04.09#ibcon#*before write, iclass 28, count 0 2006.173.09:48:04.09#ibcon#enter sib2, iclass 28, count 0 2006.173.09:48:04.09#ibcon#flushed, iclass 28, count 0 2006.173.09:48:04.09#ibcon#about to write, iclass 28, count 0 2006.173.09:48:04.09#ibcon#wrote, iclass 28, count 0 2006.173.09:48:04.09#ibcon#about to read 3, iclass 28, count 0 2006.173.09:48:04.12#ibcon#read 3, iclass 28, count 0 2006.173.09:48:04.12#ibcon#about to read 4, iclass 28, count 0 2006.173.09:48:04.12#ibcon#read 4, iclass 28, count 0 2006.173.09:48:04.12#ibcon#about to read 5, iclass 28, count 0 2006.173.09:48:04.12#ibcon#read 5, iclass 28, count 0 2006.173.09:48:04.12#ibcon#about to read 6, iclass 28, count 0 2006.173.09:48:04.12#ibcon#read 6, iclass 28, count 0 2006.173.09:48:04.12#ibcon#end of sib2, iclass 28, count 0 2006.173.09:48:04.12#ibcon#*after write, iclass 28, count 0 2006.173.09:48:04.12#ibcon#*before return 0, iclass 28, count 0 2006.173.09:48:04.12#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.09:48:04.12#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.09:48:04.12#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.09:48:04.12#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.09:48:04.12$vck44/vblo=4,679.99 2006.173.09:48:04.12#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.09:48:04.12#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.09:48:04.12#ibcon#ireg 17 cls_cnt 0 2006.173.09:48:04.12#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.09:48:04.12#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.09:48:04.12#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.09:48:04.12#ibcon#enter wrdev, iclass 30, count 0 2006.173.09:48:04.12#ibcon#first serial, iclass 30, count 0 2006.173.09:48:04.12#ibcon#enter sib2, iclass 30, count 0 2006.173.09:48:04.12#ibcon#flushed, iclass 30, count 0 2006.173.09:48:04.12#ibcon#about to write, iclass 30, count 0 2006.173.09:48:04.12#ibcon#wrote, iclass 30, count 0 2006.173.09:48:04.12#ibcon#about to read 3, iclass 30, count 0 2006.173.09:48:04.14#ibcon#read 3, iclass 30, count 0 2006.173.09:48:04.14#ibcon#about to read 4, iclass 30, count 0 2006.173.09:48:04.14#ibcon#read 4, iclass 30, count 0 2006.173.09:48:04.14#ibcon#about to read 5, iclass 30, count 0 2006.173.09:48:04.14#ibcon#read 5, iclass 30, count 0 2006.173.09:48:04.14#ibcon#about to read 6, iclass 30, count 0 2006.173.09:48:04.14#ibcon#read 6, iclass 30, count 0 2006.173.09:48:04.14#ibcon#end of sib2, iclass 30, count 0 2006.173.09:48:04.14#ibcon#*mode == 0, iclass 30, count 0 2006.173.09:48:04.14#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.09:48:04.14#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.09:48:04.14#ibcon#*before write, iclass 30, count 0 2006.173.09:48:04.14#ibcon#enter sib2, iclass 30, count 0 2006.173.09:48:04.14#ibcon#flushed, iclass 30, count 0 2006.173.09:48:04.14#ibcon#about to write, iclass 30, count 0 2006.173.09:48:04.14#ibcon#wrote, iclass 30, count 0 2006.173.09:48:04.14#ibcon#about to read 3, iclass 30, count 0 2006.173.09:48:04.18#ibcon#read 3, iclass 30, count 0 2006.173.09:48:04.18#ibcon#about to read 4, iclass 30, count 0 2006.173.09:48:04.18#ibcon#read 4, iclass 30, count 0 2006.173.09:48:04.18#ibcon#about to read 5, iclass 30, count 0 2006.173.09:48:04.18#ibcon#read 5, iclass 30, count 0 2006.173.09:48:04.18#ibcon#about to read 6, iclass 30, count 0 2006.173.09:48:04.18#ibcon#read 6, iclass 30, count 0 2006.173.09:48:04.18#ibcon#end of sib2, iclass 30, count 0 2006.173.09:48:04.18#ibcon#*after write, iclass 30, count 0 2006.173.09:48:04.18#ibcon#*before return 0, iclass 30, count 0 2006.173.09:48:04.18#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.09:48:04.18#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.09:48:04.18#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.09:48:04.18#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.09:48:04.18$vck44/vb=4,4 2006.173.09:48:04.18#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.173.09:48:04.18#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.173.09:48:04.18#ibcon#ireg 11 cls_cnt 2 2006.173.09:48:04.18#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.09:48:04.24#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.09:48:04.24#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.09:48:04.24#ibcon#enter wrdev, iclass 32, count 2 2006.173.09:48:04.24#ibcon#first serial, iclass 32, count 2 2006.173.09:48:04.24#ibcon#enter sib2, iclass 32, count 2 2006.173.09:48:04.24#ibcon#flushed, iclass 32, count 2 2006.173.09:48:04.24#ibcon#about to write, iclass 32, count 2 2006.173.09:48:04.24#ibcon#wrote, iclass 32, count 2 2006.173.09:48:04.24#ibcon#about to read 3, iclass 32, count 2 2006.173.09:48:04.26#ibcon#read 3, iclass 32, count 2 2006.173.09:48:04.26#ibcon#about to read 4, iclass 32, count 2 2006.173.09:48:04.26#ibcon#read 4, iclass 32, count 2 2006.173.09:48:04.26#ibcon#about to read 5, iclass 32, count 2 2006.173.09:48:04.26#ibcon#read 5, iclass 32, count 2 2006.173.09:48:04.26#ibcon#about to read 6, iclass 32, count 2 2006.173.09:48:04.26#ibcon#read 6, iclass 32, count 2 2006.173.09:48:04.26#ibcon#end of sib2, iclass 32, count 2 2006.173.09:48:04.26#ibcon#*mode == 0, iclass 32, count 2 2006.173.09:48:04.26#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.173.09:48:04.26#ibcon#[27=AT04-04\r\n] 2006.173.09:48:04.26#ibcon#*before write, iclass 32, count 2 2006.173.09:48:04.26#ibcon#enter sib2, iclass 32, count 2 2006.173.09:48:04.26#ibcon#flushed, iclass 32, count 2 2006.173.09:48:04.26#ibcon#about to write, iclass 32, count 2 2006.173.09:48:04.26#ibcon#wrote, iclass 32, count 2 2006.173.09:48:04.26#ibcon#about to read 3, iclass 32, count 2 2006.173.09:48:04.29#ibcon#read 3, iclass 32, count 2 2006.173.09:48:04.29#ibcon#about to read 4, iclass 32, count 2 2006.173.09:48:04.29#ibcon#read 4, iclass 32, count 2 2006.173.09:48:04.29#ibcon#about to read 5, iclass 32, count 2 2006.173.09:48:04.29#ibcon#read 5, iclass 32, count 2 2006.173.09:48:04.29#ibcon#about to read 6, iclass 32, count 2 2006.173.09:48:04.29#ibcon#read 6, iclass 32, count 2 2006.173.09:48:04.29#ibcon#end of sib2, iclass 32, count 2 2006.173.09:48:04.29#ibcon#*after write, iclass 32, count 2 2006.173.09:48:04.29#ibcon#*before return 0, iclass 32, count 2 2006.173.09:48:04.29#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.09:48:04.29#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.173.09:48:04.29#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.173.09:48:04.29#ibcon#ireg 7 cls_cnt 0 2006.173.09:48:04.29#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.09:48:04.41#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.09:48:04.41#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.09:48:04.41#ibcon#enter wrdev, iclass 32, count 0 2006.173.09:48:04.41#ibcon#first serial, iclass 32, count 0 2006.173.09:48:04.41#ibcon#enter sib2, iclass 32, count 0 2006.173.09:48:04.41#ibcon#flushed, iclass 32, count 0 2006.173.09:48:04.41#ibcon#about to write, iclass 32, count 0 2006.173.09:48:04.41#ibcon#wrote, iclass 32, count 0 2006.173.09:48:04.41#ibcon#about to read 3, iclass 32, count 0 2006.173.09:48:04.43#ibcon#read 3, iclass 32, count 0 2006.173.09:48:04.43#ibcon#about to read 4, iclass 32, count 0 2006.173.09:48:04.43#ibcon#read 4, iclass 32, count 0 2006.173.09:48:04.43#ibcon#about to read 5, iclass 32, count 0 2006.173.09:48:04.43#ibcon#read 5, iclass 32, count 0 2006.173.09:48:04.43#ibcon#about to read 6, iclass 32, count 0 2006.173.09:48:04.43#ibcon#read 6, iclass 32, count 0 2006.173.09:48:04.43#ibcon#end of sib2, iclass 32, count 0 2006.173.09:48:04.43#ibcon#*mode == 0, iclass 32, count 0 2006.173.09:48:04.43#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.09:48:04.43#ibcon#[27=USB\r\n] 2006.173.09:48:04.43#ibcon#*before write, iclass 32, count 0 2006.173.09:48:04.43#ibcon#enter sib2, iclass 32, count 0 2006.173.09:48:04.43#ibcon#flushed, iclass 32, count 0 2006.173.09:48:04.43#ibcon#about to write, iclass 32, count 0 2006.173.09:48:04.43#ibcon#wrote, iclass 32, count 0 2006.173.09:48:04.43#ibcon#about to read 3, iclass 32, count 0 2006.173.09:48:04.46#ibcon#read 3, iclass 32, count 0 2006.173.09:48:04.46#ibcon#about to read 4, iclass 32, count 0 2006.173.09:48:04.46#ibcon#read 4, iclass 32, count 0 2006.173.09:48:04.46#ibcon#about to read 5, iclass 32, count 0 2006.173.09:48:04.46#ibcon#read 5, iclass 32, count 0 2006.173.09:48:04.46#ibcon#about to read 6, iclass 32, count 0 2006.173.09:48:04.46#ibcon#read 6, iclass 32, count 0 2006.173.09:48:04.46#ibcon#end of sib2, iclass 32, count 0 2006.173.09:48:04.46#ibcon#*after write, iclass 32, count 0 2006.173.09:48:04.46#ibcon#*before return 0, iclass 32, count 0 2006.173.09:48:04.46#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.09:48:04.46#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.173.09:48:04.46#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.09:48:04.46#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.09:48:04.46$vck44/vblo=5,709.99 2006.173.09:48:04.46#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.09:48:04.46#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.09:48:04.46#ibcon#ireg 17 cls_cnt 0 2006.173.09:48:04.46#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.09:48:04.46#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.09:48:04.46#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.09:48:04.46#ibcon#enter wrdev, iclass 34, count 0 2006.173.09:48:04.46#ibcon#first serial, iclass 34, count 0 2006.173.09:48:04.46#ibcon#enter sib2, iclass 34, count 0 2006.173.09:48:04.46#ibcon#flushed, iclass 34, count 0 2006.173.09:48:04.46#ibcon#about to write, iclass 34, count 0 2006.173.09:48:04.46#ibcon#wrote, iclass 34, count 0 2006.173.09:48:04.46#ibcon#about to read 3, iclass 34, count 0 2006.173.09:48:04.48#ibcon#read 3, iclass 34, count 0 2006.173.09:48:04.48#ibcon#about to read 4, iclass 34, count 0 2006.173.09:48:04.48#ibcon#read 4, iclass 34, count 0 2006.173.09:48:04.48#ibcon#about to read 5, iclass 34, count 0 2006.173.09:48:04.48#ibcon#read 5, iclass 34, count 0 2006.173.09:48:04.48#ibcon#about to read 6, iclass 34, count 0 2006.173.09:48:04.48#ibcon#read 6, iclass 34, count 0 2006.173.09:48:04.48#ibcon#end of sib2, iclass 34, count 0 2006.173.09:48:04.48#ibcon#*mode == 0, iclass 34, count 0 2006.173.09:48:04.48#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.09:48:04.48#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.09:48:04.48#ibcon#*before write, iclass 34, count 0 2006.173.09:48:04.48#ibcon#enter sib2, iclass 34, count 0 2006.173.09:48:04.48#ibcon#flushed, iclass 34, count 0 2006.173.09:48:04.48#ibcon#about to write, iclass 34, count 0 2006.173.09:48:04.48#ibcon#wrote, iclass 34, count 0 2006.173.09:48:04.48#ibcon#about to read 3, iclass 34, count 0 2006.173.09:48:04.52#ibcon#read 3, iclass 34, count 0 2006.173.09:48:04.52#ibcon#about to read 4, iclass 34, count 0 2006.173.09:48:04.52#ibcon#read 4, iclass 34, count 0 2006.173.09:48:04.52#ibcon#about to read 5, iclass 34, count 0 2006.173.09:48:04.52#ibcon#read 5, iclass 34, count 0 2006.173.09:48:04.52#ibcon#about to read 6, iclass 34, count 0 2006.173.09:48:04.52#ibcon#read 6, iclass 34, count 0 2006.173.09:48:04.52#ibcon#end of sib2, iclass 34, count 0 2006.173.09:48:04.52#ibcon#*after write, iclass 34, count 0 2006.173.09:48:04.52#ibcon#*before return 0, iclass 34, count 0 2006.173.09:48:04.52#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.09:48:04.52#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.09:48:04.52#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.09:48:04.52#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.09:48:04.52$vck44/vb=5,4 2006.173.09:48:04.52#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.09:48:04.52#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.09:48:04.52#ibcon#ireg 11 cls_cnt 2 2006.173.09:48:04.52#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.09:48:04.58#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.09:48:04.58#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.09:48:04.58#ibcon#enter wrdev, iclass 36, count 2 2006.173.09:48:04.58#ibcon#first serial, iclass 36, count 2 2006.173.09:48:04.58#ibcon#enter sib2, iclass 36, count 2 2006.173.09:48:04.58#ibcon#flushed, iclass 36, count 2 2006.173.09:48:04.58#ibcon#about to write, iclass 36, count 2 2006.173.09:48:04.58#ibcon#wrote, iclass 36, count 2 2006.173.09:48:04.58#ibcon#about to read 3, iclass 36, count 2 2006.173.09:48:04.60#ibcon#read 3, iclass 36, count 2 2006.173.09:48:04.60#ibcon#about to read 4, iclass 36, count 2 2006.173.09:48:04.60#ibcon#read 4, iclass 36, count 2 2006.173.09:48:04.60#ibcon#about to read 5, iclass 36, count 2 2006.173.09:48:04.60#ibcon#read 5, iclass 36, count 2 2006.173.09:48:04.60#ibcon#about to read 6, iclass 36, count 2 2006.173.09:48:04.60#ibcon#read 6, iclass 36, count 2 2006.173.09:48:04.60#ibcon#end of sib2, iclass 36, count 2 2006.173.09:48:04.60#ibcon#*mode == 0, iclass 36, count 2 2006.173.09:48:04.60#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.09:48:04.60#ibcon#[27=AT05-04\r\n] 2006.173.09:48:04.60#ibcon#*before write, iclass 36, count 2 2006.173.09:48:04.60#ibcon#enter sib2, iclass 36, count 2 2006.173.09:48:04.60#ibcon#flushed, iclass 36, count 2 2006.173.09:48:04.60#ibcon#about to write, iclass 36, count 2 2006.173.09:48:04.60#ibcon#wrote, iclass 36, count 2 2006.173.09:48:04.60#ibcon#about to read 3, iclass 36, count 2 2006.173.09:48:04.63#ibcon#read 3, iclass 36, count 2 2006.173.09:48:04.63#ibcon#about to read 4, iclass 36, count 2 2006.173.09:48:04.63#ibcon#read 4, iclass 36, count 2 2006.173.09:48:04.63#ibcon#about to read 5, iclass 36, count 2 2006.173.09:48:04.63#ibcon#read 5, iclass 36, count 2 2006.173.09:48:04.63#ibcon#about to read 6, iclass 36, count 2 2006.173.09:48:04.63#ibcon#read 6, iclass 36, count 2 2006.173.09:48:04.63#ibcon#end of sib2, iclass 36, count 2 2006.173.09:48:04.63#ibcon#*after write, iclass 36, count 2 2006.173.09:48:04.63#ibcon#*before return 0, iclass 36, count 2 2006.173.09:48:04.63#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.09:48:04.63#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.09:48:04.63#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.09:48:04.63#ibcon#ireg 7 cls_cnt 0 2006.173.09:48:04.63#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.09:48:04.75#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.09:48:04.75#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.09:48:04.75#ibcon#enter wrdev, iclass 36, count 0 2006.173.09:48:04.75#ibcon#first serial, iclass 36, count 0 2006.173.09:48:04.75#ibcon#enter sib2, iclass 36, count 0 2006.173.09:48:04.75#ibcon#flushed, iclass 36, count 0 2006.173.09:48:04.75#ibcon#about to write, iclass 36, count 0 2006.173.09:48:04.75#ibcon#wrote, iclass 36, count 0 2006.173.09:48:04.75#ibcon#about to read 3, iclass 36, count 0 2006.173.09:48:04.77#ibcon#read 3, iclass 36, count 0 2006.173.09:48:04.77#ibcon#about to read 4, iclass 36, count 0 2006.173.09:48:04.77#ibcon#read 4, iclass 36, count 0 2006.173.09:48:04.77#ibcon#about to read 5, iclass 36, count 0 2006.173.09:48:04.77#ibcon#read 5, iclass 36, count 0 2006.173.09:48:04.77#ibcon#about to read 6, iclass 36, count 0 2006.173.09:48:04.77#ibcon#read 6, iclass 36, count 0 2006.173.09:48:04.77#ibcon#end of sib2, iclass 36, count 0 2006.173.09:48:04.77#ibcon#*mode == 0, iclass 36, count 0 2006.173.09:48:04.77#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.09:48:04.77#ibcon#[27=USB\r\n] 2006.173.09:48:04.77#ibcon#*before write, iclass 36, count 0 2006.173.09:48:04.77#ibcon#enter sib2, iclass 36, count 0 2006.173.09:48:04.77#ibcon#flushed, iclass 36, count 0 2006.173.09:48:04.77#ibcon#about to write, iclass 36, count 0 2006.173.09:48:04.77#ibcon#wrote, iclass 36, count 0 2006.173.09:48:04.77#ibcon#about to read 3, iclass 36, count 0 2006.173.09:48:04.80#ibcon#read 3, iclass 36, count 0 2006.173.09:48:04.80#ibcon#about to read 4, iclass 36, count 0 2006.173.09:48:04.80#ibcon#read 4, iclass 36, count 0 2006.173.09:48:04.80#ibcon#about to read 5, iclass 36, count 0 2006.173.09:48:04.80#ibcon#read 5, iclass 36, count 0 2006.173.09:48:04.80#ibcon#about to read 6, iclass 36, count 0 2006.173.09:48:04.80#ibcon#read 6, iclass 36, count 0 2006.173.09:48:04.80#ibcon#end of sib2, iclass 36, count 0 2006.173.09:48:04.80#ibcon#*after write, iclass 36, count 0 2006.173.09:48:04.80#ibcon#*before return 0, iclass 36, count 0 2006.173.09:48:04.80#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.09:48:04.80#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.09:48:04.80#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.09:48:04.80#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.09:48:04.80$vck44/vblo=6,719.99 2006.173.09:48:04.80#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.09:48:04.80#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.09:48:04.80#ibcon#ireg 17 cls_cnt 0 2006.173.09:48:04.80#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.09:48:04.80#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.09:48:04.80#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.09:48:04.80#ibcon#enter wrdev, iclass 38, count 0 2006.173.09:48:04.80#ibcon#first serial, iclass 38, count 0 2006.173.09:48:04.80#ibcon#enter sib2, iclass 38, count 0 2006.173.09:48:04.80#ibcon#flushed, iclass 38, count 0 2006.173.09:48:04.80#ibcon#about to write, iclass 38, count 0 2006.173.09:48:04.80#ibcon#wrote, iclass 38, count 0 2006.173.09:48:04.80#ibcon#about to read 3, iclass 38, count 0 2006.173.09:48:04.82#ibcon#read 3, iclass 38, count 0 2006.173.09:48:04.82#ibcon#about to read 4, iclass 38, count 0 2006.173.09:48:04.82#ibcon#read 4, iclass 38, count 0 2006.173.09:48:04.82#ibcon#about to read 5, iclass 38, count 0 2006.173.09:48:04.82#ibcon#read 5, iclass 38, count 0 2006.173.09:48:04.82#ibcon#about to read 6, iclass 38, count 0 2006.173.09:48:04.82#ibcon#read 6, iclass 38, count 0 2006.173.09:48:04.82#ibcon#end of sib2, iclass 38, count 0 2006.173.09:48:04.82#ibcon#*mode == 0, iclass 38, count 0 2006.173.09:48:04.82#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.09:48:04.82#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.09:48:04.82#ibcon#*before write, iclass 38, count 0 2006.173.09:48:04.82#ibcon#enter sib2, iclass 38, count 0 2006.173.09:48:04.82#ibcon#flushed, iclass 38, count 0 2006.173.09:48:04.82#ibcon#about to write, iclass 38, count 0 2006.173.09:48:04.82#ibcon#wrote, iclass 38, count 0 2006.173.09:48:04.82#ibcon#about to read 3, iclass 38, count 0 2006.173.09:48:04.86#ibcon#read 3, iclass 38, count 0 2006.173.09:48:04.86#ibcon#about to read 4, iclass 38, count 0 2006.173.09:48:04.86#ibcon#read 4, iclass 38, count 0 2006.173.09:48:04.86#ibcon#about to read 5, iclass 38, count 0 2006.173.09:48:04.86#ibcon#read 5, iclass 38, count 0 2006.173.09:48:04.86#ibcon#about to read 6, iclass 38, count 0 2006.173.09:48:04.86#ibcon#read 6, iclass 38, count 0 2006.173.09:48:04.86#ibcon#end of sib2, iclass 38, count 0 2006.173.09:48:04.86#ibcon#*after write, iclass 38, count 0 2006.173.09:48:04.86#ibcon#*before return 0, iclass 38, count 0 2006.173.09:48:04.86#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.09:48:04.86#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.09:48:04.86#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.09:48:04.86#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.09:48:04.86$vck44/vb=6,4 2006.173.09:48:04.86#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.09:48:04.86#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.09:48:04.86#ibcon#ireg 11 cls_cnt 2 2006.173.09:48:04.86#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.09:48:04.92#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.09:48:04.92#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.09:48:04.92#ibcon#enter wrdev, iclass 40, count 2 2006.173.09:48:04.92#ibcon#first serial, iclass 40, count 2 2006.173.09:48:04.92#ibcon#enter sib2, iclass 40, count 2 2006.173.09:48:04.92#ibcon#flushed, iclass 40, count 2 2006.173.09:48:04.92#ibcon#about to write, iclass 40, count 2 2006.173.09:48:04.92#ibcon#wrote, iclass 40, count 2 2006.173.09:48:04.92#ibcon#about to read 3, iclass 40, count 2 2006.173.09:48:04.94#ibcon#read 3, iclass 40, count 2 2006.173.09:48:04.94#ibcon#about to read 4, iclass 40, count 2 2006.173.09:48:04.94#ibcon#read 4, iclass 40, count 2 2006.173.09:48:04.94#ibcon#about to read 5, iclass 40, count 2 2006.173.09:48:04.94#ibcon#read 5, iclass 40, count 2 2006.173.09:48:04.94#ibcon#about to read 6, iclass 40, count 2 2006.173.09:48:04.94#ibcon#read 6, iclass 40, count 2 2006.173.09:48:04.94#ibcon#end of sib2, iclass 40, count 2 2006.173.09:48:04.94#ibcon#*mode == 0, iclass 40, count 2 2006.173.09:48:04.94#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.09:48:04.94#ibcon#[27=AT06-04\r\n] 2006.173.09:48:04.94#ibcon#*before write, iclass 40, count 2 2006.173.09:48:04.94#ibcon#enter sib2, iclass 40, count 2 2006.173.09:48:04.94#ibcon#flushed, iclass 40, count 2 2006.173.09:48:04.94#ibcon#about to write, iclass 40, count 2 2006.173.09:48:04.94#ibcon#wrote, iclass 40, count 2 2006.173.09:48:04.94#ibcon#about to read 3, iclass 40, count 2 2006.173.09:48:04.97#ibcon#read 3, iclass 40, count 2 2006.173.09:48:04.97#ibcon#about to read 4, iclass 40, count 2 2006.173.09:48:04.97#ibcon#read 4, iclass 40, count 2 2006.173.09:48:04.97#ibcon#about to read 5, iclass 40, count 2 2006.173.09:48:04.97#ibcon#read 5, iclass 40, count 2 2006.173.09:48:04.97#ibcon#about to read 6, iclass 40, count 2 2006.173.09:48:04.97#ibcon#read 6, iclass 40, count 2 2006.173.09:48:04.97#ibcon#end of sib2, iclass 40, count 2 2006.173.09:48:04.97#ibcon#*after write, iclass 40, count 2 2006.173.09:48:04.97#ibcon#*before return 0, iclass 40, count 2 2006.173.09:48:04.97#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.09:48:04.97#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.09:48:04.97#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.09:48:04.97#ibcon#ireg 7 cls_cnt 0 2006.173.09:48:04.97#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.09:48:05.09#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.09:48:05.09#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.09:48:05.09#ibcon#enter wrdev, iclass 40, count 0 2006.173.09:48:05.09#ibcon#first serial, iclass 40, count 0 2006.173.09:48:05.09#ibcon#enter sib2, iclass 40, count 0 2006.173.09:48:05.09#ibcon#flushed, iclass 40, count 0 2006.173.09:48:05.09#ibcon#about to write, iclass 40, count 0 2006.173.09:48:05.09#ibcon#wrote, iclass 40, count 0 2006.173.09:48:05.09#ibcon#about to read 3, iclass 40, count 0 2006.173.09:48:05.11#ibcon#read 3, iclass 40, count 0 2006.173.09:48:05.11#ibcon#about to read 4, iclass 40, count 0 2006.173.09:48:05.11#ibcon#read 4, iclass 40, count 0 2006.173.09:48:05.11#ibcon#about to read 5, iclass 40, count 0 2006.173.09:48:05.11#ibcon#read 5, iclass 40, count 0 2006.173.09:48:05.11#ibcon#about to read 6, iclass 40, count 0 2006.173.09:48:05.11#ibcon#read 6, iclass 40, count 0 2006.173.09:48:05.11#ibcon#end of sib2, iclass 40, count 0 2006.173.09:48:05.11#ibcon#*mode == 0, iclass 40, count 0 2006.173.09:48:05.11#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.09:48:05.11#ibcon#[27=USB\r\n] 2006.173.09:48:05.11#ibcon#*before write, iclass 40, count 0 2006.173.09:48:05.11#ibcon#enter sib2, iclass 40, count 0 2006.173.09:48:05.11#ibcon#flushed, iclass 40, count 0 2006.173.09:48:05.11#ibcon#about to write, iclass 40, count 0 2006.173.09:48:05.11#ibcon#wrote, iclass 40, count 0 2006.173.09:48:05.11#ibcon#about to read 3, iclass 40, count 0 2006.173.09:48:05.14#ibcon#read 3, iclass 40, count 0 2006.173.09:48:05.14#ibcon#about to read 4, iclass 40, count 0 2006.173.09:48:05.14#ibcon#read 4, iclass 40, count 0 2006.173.09:48:05.14#ibcon#about to read 5, iclass 40, count 0 2006.173.09:48:05.14#ibcon#read 5, iclass 40, count 0 2006.173.09:48:05.14#ibcon#about to read 6, iclass 40, count 0 2006.173.09:48:05.14#ibcon#read 6, iclass 40, count 0 2006.173.09:48:05.14#ibcon#end of sib2, iclass 40, count 0 2006.173.09:48:05.14#ibcon#*after write, iclass 40, count 0 2006.173.09:48:05.14#ibcon#*before return 0, iclass 40, count 0 2006.173.09:48:05.14#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.09:48:05.14#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.09:48:05.14#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.09:48:05.14#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.09:48:05.15$vck44/vblo=7,734.99 2006.173.09:48:05.15#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.09:48:05.15#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.09:48:05.15#ibcon#ireg 17 cls_cnt 0 2006.173.09:48:05.15#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.09:48:05.15#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.09:48:05.15#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.09:48:05.15#ibcon#enter wrdev, iclass 4, count 0 2006.173.09:48:05.15#ibcon#first serial, iclass 4, count 0 2006.173.09:48:05.15#ibcon#enter sib2, iclass 4, count 0 2006.173.09:48:05.15#ibcon#flushed, iclass 4, count 0 2006.173.09:48:05.15#ibcon#about to write, iclass 4, count 0 2006.173.09:48:05.15#ibcon#wrote, iclass 4, count 0 2006.173.09:48:05.15#ibcon#about to read 3, iclass 4, count 0 2006.173.09:48:05.16#ibcon#read 3, iclass 4, count 0 2006.173.09:48:05.16#ibcon#about to read 4, iclass 4, count 0 2006.173.09:48:05.16#ibcon#read 4, iclass 4, count 0 2006.173.09:48:05.16#ibcon#about to read 5, iclass 4, count 0 2006.173.09:48:05.16#ibcon#read 5, iclass 4, count 0 2006.173.09:48:05.16#ibcon#about to read 6, iclass 4, count 0 2006.173.09:48:05.16#ibcon#read 6, iclass 4, count 0 2006.173.09:48:05.16#ibcon#end of sib2, iclass 4, count 0 2006.173.09:48:05.16#ibcon#*mode == 0, iclass 4, count 0 2006.173.09:48:05.16#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.09:48:05.16#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.09:48:05.16#ibcon#*before write, iclass 4, count 0 2006.173.09:48:05.16#ibcon#enter sib2, iclass 4, count 0 2006.173.09:48:05.16#ibcon#flushed, iclass 4, count 0 2006.173.09:48:05.16#ibcon#about to write, iclass 4, count 0 2006.173.09:48:05.16#ibcon#wrote, iclass 4, count 0 2006.173.09:48:05.16#ibcon#about to read 3, iclass 4, count 0 2006.173.09:48:05.20#ibcon#read 3, iclass 4, count 0 2006.173.09:48:05.20#ibcon#about to read 4, iclass 4, count 0 2006.173.09:48:05.20#ibcon#read 4, iclass 4, count 0 2006.173.09:48:05.20#ibcon#about to read 5, iclass 4, count 0 2006.173.09:48:05.20#ibcon#read 5, iclass 4, count 0 2006.173.09:48:05.20#ibcon#about to read 6, iclass 4, count 0 2006.173.09:48:05.20#ibcon#read 6, iclass 4, count 0 2006.173.09:48:05.20#ibcon#end of sib2, iclass 4, count 0 2006.173.09:48:05.20#ibcon#*after write, iclass 4, count 0 2006.173.09:48:05.20#ibcon#*before return 0, iclass 4, count 0 2006.173.09:48:05.20#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.09:48:05.20#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.09:48:05.20#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.09:48:05.20#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.09:48:05.20$vck44/vb=7,4 2006.173.09:48:05.20#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.09:48:05.20#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.09:48:05.20#ibcon#ireg 11 cls_cnt 2 2006.173.09:48:05.20#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.09:48:05.26#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.09:48:05.26#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.09:48:05.26#ibcon#enter wrdev, iclass 6, count 2 2006.173.09:48:05.26#ibcon#first serial, iclass 6, count 2 2006.173.09:48:05.26#ibcon#enter sib2, iclass 6, count 2 2006.173.09:48:05.26#ibcon#flushed, iclass 6, count 2 2006.173.09:48:05.26#ibcon#about to write, iclass 6, count 2 2006.173.09:48:05.26#ibcon#wrote, iclass 6, count 2 2006.173.09:48:05.26#ibcon#about to read 3, iclass 6, count 2 2006.173.09:48:05.28#ibcon#read 3, iclass 6, count 2 2006.173.09:48:05.28#ibcon#about to read 4, iclass 6, count 2 2006.173.09:48:05.28#ibcon#read 4, iclass 6, count 2 2006.173.09:48:05.28#ibcon#about to read 5, iclass 6, count 2 2006.173.09:48:05.28#ibcon#read 5, iclass 6, count 2 2006.173.09:48:05.28#ibcon#about to read 6, iclass 6, count 2 2006.173.09:48:05.28#ibcon#read 6, iclass 6, count 2 2006.173.09:48:05.28#ibcon#end of sib2, iclass 6, count 2 2006.173.09:48:05.28#ibcon#*mode == 0, iclass 6, count 2 2006.173.09:48:05.28#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.09:48:05.28#ibcon#[27=AT07-04\r\n] 2006.173.09:48:05.28#ibcon#*before write, iclass 6, count 2 2006.173.09:48:05.28#ibcon#enter sib2, iclass 6, count 2 2006.173.09:48:05.28#ibcon#flushed, iclass 6, count 2 2006.173.09:48:05.28#ibcon#about to write, iclass 6, count 2 2006.173.09:48:05.28#ibcon#wrote, iclass 6, count 2 2006.173.09:48:05.28#ibcon#about to read 3, iclass 6, count 2 2006.173.09:48:05.31#ibcon#read 3, iclass 6, count 2 2006.173.09:48:05.31#ibcon#about to read 4, iclass 6, count 2 2006.173.09:48:05.31#ibcon#read 4, iclass 6, count 2 2006.173.09:48:05.31#ibcon#about to read 5, iclass 6, count 2 2006.173.09:48:05.31#ibcon#read 5, iclass 6, count 2 2006.173.09:48:05.31#ibcon#about to read 6, iclass 6, count 2 2006.173.09:48:05.31#ibcon#read 6, iclass 6, count 2 2006.173.09:48:05.31#ibcon#end of sib2, iclass 6, count 2 2006.173.09:48:05.31#ibcon#*after write, iclass 6, count 2 2006.173.09:48:05.31#ibcon#*before return 0, iclass 6, count 2 2006.173.09:48:05.31#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.09:48:05.31#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.09:48:05.31#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.09:48:05.31#ibcon#ireg 7 cls_cnt 0 2006.173.09:48:05.31#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.09:48:05.43#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.09:48:05.43#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.09:48:05.43#ibcon#enter wrdev, iclass 6, count 0 2006.173.09:48:05.43#ibcon#first serial, iclass 6, count 0 2006.173.09:48:05.43#ibcon#enter sib2, iclass 6, count 0 2006.173.09:48:05.43#ibcon#flushed, iclass 6, count 0 2006.173.09:48:05.43#ibcon#about to write, iclass 6, count 0 2006.173.09:48:05.43#ibcon#wrote, iclass 6, count 0 2006.173.09:48:05.43#ibcon#about to read 3, iclass 6, count 0 2006.173.09:48:05.45#ibcon#read 3, iclass 6, count 0 2006.173.09:48:05.45#ibcon#about to read 4, iclass 6, count 0 2006.173.09:48:05.45#ibcon#read 4, iclass 6, count 0 2006.173.09:48:05.45#ibcon#about to read 5, iclass 6, count 0 2006.173.09:48:05.45#ibcon#read 5, iclass 6, count 0 2006.173.09:48:05.45#ibcon#about to read 6, iclass 6, count 0 2006.173.09:48:05.45#ibcon#read 6, iclass 6, count 0 2006.173.09:48:05.45#ibcon#end of sib2, iclass 6, count 0 2006.173.09:48:05.45#ibcon#*mode == 0, iclass 6, count 0 2006.173.09:48:05.45#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.09:48:05.45#ibcon#[27=USB\r\n] 2006.173.09:48:05.45#ibcon#*before write, iclass 6, count 0 2006.173.09:48:05.45#ibcon#enter sib2, iclass 6, count 0 2006.173.09:48:05.45#ibcon#flushed, iclass 6, count 0 2006.173.09:48:05.45#ibcon#about to write, iclass 6, count 0 2006.173.09:48:05.45#ibcon#wrote, iclass 6, count 0 2006.173.09:48:05.45#ibcon#about to read 3, iclass 6, count 0 2006.173.09:48:05.48#ibcon#read 3, iclass 6, count 0 2006.173.09:48:05.48#ibcon#about to read 4, iclass 6, count 0 2006.173.09:48:05.48#ibcon#read 4, iclass 6, count 0 2006.173.09:48:05.48#ibcon#about to read 5, iclass 6, count 0 2006.173.09:48:05.48#ibcon#read 5, iclass 6, count 0 2006.173.09:48:05.48#ibcon#about to read 6, iclass 6, count 0 2006.173.09:48:05.48#ibcon#read 6, iclass 6, count 0 2006.173.09:48:05.48#ibcon#end of sib2, iclass 6, count 0 2006.173.09:48:05.48#ibcon#*after write, iclass 6, count 0 2006.173.09:48:05.48#ibcon#*before return 0, iclass 6, count 0 2006.173.09:48:05.48#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.09:48:05.48#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.09:48:05.48#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.09:48:05.48#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.09:48:05.48$vck44/vblo=8,744.99 2006.173.09:48:05.48#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.09:48:05.48#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.09:48:05.48#ibcon#ireg 17 cls_cnt 0 2006.173.09:48:05.48#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.09:48:05.48#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.09:48:05.48#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.09:48:05.48#ibcon#enter wrdev, iclass 10, count 0 2006.173.09:48:05.48#ibcon#first serial, iclass 10, count 0 2006.173.09:48:05.48#ibcon#enter sib2, iclass 10, count 0 2006.173.09:48:05.48#ibcon#flushed, iclass 10, count 0 2006.173.09:48:05.48#ibcon#about to write, iclass 10, count 0 2006.173.09:48:05.48#ibcon#wrote, iclass 10, count 0 2006.173.09:48:05.48#ibcon#about to read 3, iclass 10, count 0 2006.173.09:48:05.50#ibcon#read 3, iclass 10, count 0 2006.173.09:48:05.50#ibcon#about to read 4, iclass 10, count 0 2006.173.09:48:05.50#ibcon#read 4, iclass 10, count 0 2006.173.09:48:05.50#ibcon#about to read 5, iclass 10, count 0 2006.173.09:48:05.50#ibcon#read 5, iclass 10, count 0 2006.173.09:48:05.50#ibcon#about to read 6, iclass 10, count 0 2006.173.09:48:05.50#ibcon#read 6, iclass 10, count 0 2006.173.09:48:05.50#ibcon#end of sib2, iclass 10, count 0 2006.173.09:48:05.50#ibcon#*mode == 0, iclass 10, count 0 2006.173.09:48:05.50#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.09:48:05.50#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.09:48:05.50#ibcon#*before write, iclass 10, count 0 2006.173.09:48:05.50#ibcon#enter sib2, iclass 10, count 0 2006.173.09:48:05.50#ibcon#flushed, iclass 10, count 0 2006.173.09:48:05.50#ibcon#about to write, iclass 10, count 0 2006.173.09:48:05.50#ibcon#wrote, iclass 10, count 0 2006.173.09:48:05.50#ibcon#about to read 3, iclass 10, count 0 2006.173.09:48:05.54#ibcon#read 3, iclass 10, count 0 2006.173.09:48:05.54#ibcon#about to read 4, iclass 10, count 0 2006.173.09:48:05.54#ibcon#read 4, iclass 10, count 0 2006.173.09:48:05.54#ibcon#about to read 5, iclass 10, count 0 2006.173.09:48:05.54#ibcon#read 5, iclass 10, count 0 2006.173.09:48:05.54#ibcon#about to read 6, iclass 10, count 0 2006.173.09:48:05.54#ibcon#read 6, iclass 10, count 0 2006.173.09:48:05.54#ibcon#end of sib2, iclass 10, count 0 2006.173.09:48:05.54#ibcon#*after write, iclass 10, count 0 2006.173.09:48:05.54#ibcon#*before return 0, iclass 10, count 0 2006.173.09:48:05.54#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.09:48:05.54#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.09:48:05.54#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.09:48:05.54#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.09:48:05.54$vck44/vb=8,4 2006.173.09:48:05.54#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.09:48:05.54#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.09:48:05.54#ibcon#ireg 11 cls_cnt 2 2006.173.09:48:05.54#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.09:48:05.60#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.09:48:05.60#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.09:48:05.60#ibcon#enter wrdev, iclass 12, count 2 2006.173.09:48:05.60#ibcon#first serial, iclass 12, count 2 2006.173.09:48:05.60#ibcon#enter sib2, iclass 12, count 2 2006.173.09:48:05.60#ibcon#flushed, iclass 12, count 2 2006.173.09:48:05.60#ibcon#about to write, iclass 12, count 2 2006.173.09:48:05.60#ibcon#wrote, iclass 12, count 2 2006.173.09:48:05.60#ibcon#about to read 3, iclass 12, count 2 2006.173.09:48:05.62#ibcon#read 3, iclass 12, count 2 2006.173.09:48:05.62#ibcon#about to read 4, iclass 12, count 2 2006.173.09:48:05.62#ibcon#read 4, iclass 12, count 2 2006.173.09:48:05.62#ibcon#about to read 5, iclass 12, count 2 2006.173.09:48:05.62#ibcon#read 5, iclass 12, count 2 2006.173.09:48:05.62#ibcon#about to read 6, iclass 12, count 2 2006.173.09:48:05.62#ibcon#read 6, iclass 12, count 2 2006.173.09:48:05.62#ibcon#end of sib2, iclass 12, count 2 2006.173.09:48:05.62#ibcon#*mode == 0, iclass 12, count 2 2006.173.09:48:05.62#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.09:48:05.62#ibcon#[27=AT08-04\r\n] 2006.173.09:48:05.62#ibcon#*before write, iclass 12, count 2 2006.173.09:48:05.62#ibcon#enter sib2, iclass 12, count 2 2006.173.09:48:05.62#ibcon#flushed, iclass 12, count 2 2006.173.09:48:05.62#ibcon#about to write, iclass 12, count 2 2006.173.09:48:05.62#ibcon#wrote, iclass 12, count 2 2006.173.09:48:05.62#ibcon#about to read 3, iclass 12, count 2 2006.173.09:48:05.65#ibcon#read 3, iclass 12, count 2 2006.173.09:48:05.65#ibcon#about to read 4, iclass 12, count 2 2006.173.09:48:05.65#ibcon#read 4, iclass 12, count 2 2006.173.09:48:05.65#ibcon#about to read 5, iclass 12, count 2 2006.173.09:48:05.65#ibcon#read 5, iclass 12, count 2 2006.173.09:48:05.65#ibcon#about to read 6, iclass 12, count 2 2006.173.09:48:05.65#ibcon#read 6, iclass 12, count 2 2006.173.09:48:05.65#ibcon#end of sib2, iclass 12, count 2 2006.173.09:48:05.65#ibcon#*after write, iclass 12, count 2 2006.173.09:48:05.65#ibcon#*before return 0, iclass 12, count 2 2006.173.09:48:05.65#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.09:48:05.65#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.09:48:05.65#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.09:48:05.65#ibcon#ireg 7 cls_cnt 0 2006.173.09:48:05.65#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.09:48:05.77#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.09:48:05.77#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.09:48:05.77#ibcon#enter wrdev, iclass 12, count 0 2006.173.09:48:05.77#ibcon#first serial, iclass 12, count 0 2006.173.09:48:05.77#ibcon#enter sib2, iclass 12, count 0 2006.173.09:48:05.77#ibcon#flushed, iclass 12, count 0 2006.173.09:48:05.77#ibcon#about to write, iclass 12, count 0 2006.173.09:48:05.77#ibcon#wrote, iclass 12, count 0 2006.173.09:48:05.77#ibcon#about to read 3, iclass 12, count 0 2006.173.09:48:05.79#ibcon#read 3, iclass 12, count 0 2006.173.09:48:05.79#ibcon#about to read 4, iclass 12, count 0 2006.173.09:48:05.79#ibcon#read 4, iclass 12, count 0 2006.173.09:48:05.79#ibcon#about to read 5, iclass 12, count 0 2006.173.09:48:05.79#ibcon#read 5, iclass 12, count 0 2006.173.09:48:05.79#ibcon#about to read 6, iclass 12, count 0 2006.173.09:48:05.79#ibcon#read 6, iclass 12, count 0 2006.173.09:48:05.79#ibcon#end of sib2, iclass 12, count 0 2006.173.09:48:05.79#ibcon#*mode == 0, iclass 12, count 0 2006.173.09:48:05.79#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.09:48:05.79#ibcon#[27=USB\r\n] 2006.173.09:48:05.79#ibcon#*before write, iclass 12, count 0 2006.173.09:48:05.79#ibcon#enter sib2, iclass 12, count 0 2006.173.09:48:05.79#ibcon#flushed, iclass 12, count 0 2006.173.09:48:05.79#ibcon#about to write, iclass 12, count 0 2006.173.09:48:05.79#ibcon#wrote, iclass 12, count 0 2006.173.09:48:05.79#ibcon#about to read 3, iclass 12, count 0 2006.173.09:48:05.82#ibcon#read 3, iclass 12, count 0 2006.173.09:48:05.82#ibcon#about to read 4, iclass 12, count 0 2006.173.09:48:05.82#ibcon#read 4, iclass 12, count 0 2006.173.09:48:05.82#ibcon#about to read 5, iclass 12, count 0 2006.173.09:48:05.82#ibcon#read 5, iclass 12, count 0 2006.173.09:48:05.82#ibcon#about to read 6, iclass 12, count 0 2006.173.09:48:05.82#ibcon#read 6, iclass 12, count 0 2006.173.09:48:05.82#ibcon#end of sib2, iclass 12, count 0 2006.173.09:48:05.82#ibcon#*after write, iclass 12, count 0 2006.173.09:48:05.82#ibcon#*before return 0, iclass 12, count 0 2006.173.09:48:05.82#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.09:48:05.82#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.09:48:05.82#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.09:48:05.82#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.09:48:05.82$vck44/vabw=wide 2006.173.09:48:05.82#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.09:48:05.82#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.09:48:05.82#ibcon#ireg 8 cls_cnt 0 2006.173.09:48:05.82#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.09:48:05.82#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.09:48:05.82#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.09:48:05.82#ibcon#enter wrdev, iclass 14, count 0 2006.173.09:48:05.82#ibcon#first serial, iclass 14, count 0 2006.173.09:48:05.82#ibcon#enter sib2, iclass 14, count 0 2006.173.09:48:05.82#ibcon#flushed, iclass 14, count 0 2006.173.09:48:05.82#ibcon#about to write, iclass 14, count 0 2006.173.09:48:05.82#ibcon#wrote, iclass 14, count 0 2006.173.09:48:05.82#ibcon#about to read 3, iclass 14, count 0 2006.173.09:48:05.84#ibcon#read 3, iclass 14, count 0 2006.173.09:48:05.84#ibcon#about to read 4, iclass 14, count 0 2006.173.09:48:05.84#ibcon#read 4, iclass 14, count 0 2006.173.09:48:05.84#ibcon#about to read 5, iclass 14, count 0 2006.173.09:48:05.84#ibcon#read 5, iclass 14, count 0 2006.173.09:48:05.84#ibcon#about to read 6, iclass 14, count 0 2006.173.09:48:05.84#ibcon#read 6, iclass 14, count 0 2006.173.09:48:05.84#ibcon#end of sib2, iclass 14, count 0 2006.173.09:48:05.84#ibcon#*mode == 0, iclass 14, count 0 2006.173.09:48:05.84#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.09:48:05.84#ibcon#[25=BW32\r\n] 2006.173.09:48:05.84#ibcon#*before write, iclass 14, count 0 2006.173.09:48:05.84#ibcon#enter sib2, iclass 14, count 0 2006.173.09:48:05.84#ibcon#flushed, iclass 14, count 0 2006.173.09:48:05.84#ibcon#about to write, iclass 14, count 0 2006.173.09:48:05.84#ibcon#wrote, iclass 14, count 0 2006.173.09:48:05.84#ibcon#about to read 3, iclass 14, count 0 2006.173.09:48:05.87#ibcon#read 3, iclass 14, count 0 2006.173.09:48:05.87#ibcon#about to read 4, iclass 14, count 0 2006.173.09:48:05.87#ibcon#read 4, iclass 14, count 0 2006.173.09:48:05.87#ibcon#about to read 5, iclass 14, count 0 2006.173.09:48:05.87#ibcon#read 5, iclass 14, count 0 2006.173.09:48:05.87#ibcon#about to read 6, iclass 14, count 0 2006.173.09:48:05.87#ibcon#read 6, iclass 14, count 0 2006.173.09:48:05.87#ibcon#end of sib2, iclass 14, count 0 2006.173.09:48:05.87#ibcon#*after write, iclass 14, count 0 2006.173.09:48:05.87#ibcon#*before return 0, iclass 14, count 0 2006.173.09:48:05.87#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.09:48:05.87#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.09:48:05.87#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.09:48:05.87#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.09:48:05.87$vck44/vbbw=wide 2006.173.09:48:05.87#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.09:48:05.87#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.09:48:05.87#ibcon#ireg 8 cls_cnt 0 2006.173.09:48:05.87#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.09:48:05.94#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.09:48:05.94#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.09:48:05.94#ibcon#enter wrdev, iclass 16, count 0 2006.173.09:48:05.94#ibcon#first serial, iclass 16, count 0 2006.173.09:48:05.94#ibcon#enter sib2, iclass 16, count 0 2006.173.09:48:05.94#ibcon#flushed, iclass 16, count 0 2006.173.09:48:05.94#ibcon#about to write, iclass 16, count 0 2006.173.09:48:05.94#ibcon#wrote, iclass 16, count 0 2006.173.09:48:05.94#ibcon#about to read 3, iclass 16, count 0 2006.173.09:48:05.96#ibcon#read 3, iclass 16, count 0 2006.173.09:48:05.96#ibcon#about to read 4, iclass 16, count 0 2006.173.09:48:05.96#ibcon#read 4, iclass 16, count 0 2006.173.09:48:05.96#ibcon#about to read 5, iclass 16, count 0 2006.173.09:48:05.96#ibcon#read 5, iclass 16, count 0 2006.173.09:48:05.96#ibcon#about to read 6, iclass 16, count 0 2006.173.09:48:05.96#ibcon#read 6, iclass 16, count 0 2006.173.09:48:05.96#ibcon#end of sib2, iclass 16, count 0 2006.173.09:48:05.96#ibcon#*mode == 0, iclass 16, count 0 2006.173.09:48:05.96#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.09:48:05.96#ibcon#[27=BW32\r\n] 2006.173.09:48:05.96#ibcon#*before write, iclass 16, count 0 2006.173.09:48:05.96#ibcon#enter sib2, iclass 16, count 0 2006.173.09:48:05.96#ibcon#flushed, iclass 16, count 0 2006.173.09:48:05.96#ibcon#about to write, iclass 16, count 0 2006.173.09:48:05.96#ibcon#wrote, iclass 16, count 0 2006.173.09:48:05.96#ibcon#about to read 3, iclass 16, count 0 2006.173.09:48:05.99#ibcon#read 3, iclass 16, count 0 2006.173.09:48:05.99#ibcon#about to read 4, iclass 16, count 0 2006.173.09:48:05.99#ibcon#read 4, iclass 16, count 0 2006.173.09:48:05.99#ibcon#about to read 5, iclass 16, count 0 2006.173.09:48:05.99#ibcon#read 5, iclass 16, count 0 2006.173.09:48:05.99#ibcon#about to read 6, iclass 16, count 0 2006.173.09:48:05.99#ibcon#read 6, iclass 16, count 0 2006.173.09:48:05.99#ibcon#end of sib2, iclass 16, count 0 2006.173.09:48:05.99#ibcon#*after write, iclass 16, count 0 2006.173.09:48:05.99#ibcon#*before return 0, iclass 16, count 0 2006.173.09:48:05.99#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.09:48:05.99#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.09:48:05.99#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.09:48:05.99#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.09:48:05.99$setupk4/ifdk4 2006.173.09:48:05.99$ifdk4/lo= 2006.173.09:48:05.99$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.09:48:06.00$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.09:48:06.00$ifdk4/patch= 2006.173.09:48:06.00$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.09:48:06.00$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.09:48:06.00$setupk4/!*+20s 2006.173.09:48:08.50#abcon#<5=/01 0.4 0.5 22.69 881004.5\r\n> 2006.173.09:48:08.52#abcon#{5=INTERFACE CLEAR} 2006.173.09:48:08.58#abcon#[5=S1D000X0/0*\r\n] 2006.173.09:48:18.67#abcon#<5=/01 0.4 0.5 22.69 881004.5\r\n> 2006.173.09:48:18.69#abcon#{5=INTERFACE CLEAR} 2006.173.09:48:18.75#abcon#[5=S1D000X0/0*\r\n] 2006.173.09:48:20.51$setupk4/"tpicd 2006.173.09:48:20.51$setupk4/echo=off 2006.173.09:48:20.51$setupk4/xlog=off 2006.173.09:48:20.51:!2006.173.09:49:19 2006.173.09:48:28.14#trakl#Source acquired 2006.173.09:48:30.14#flagr#flagr/antenna,acquired 2006.173.09:49:19.00:preob 2006.173.09:49:19.14/onsource/TRACKING 2006.173.09:49:19.14:!2006.173.09:49:29 2006.173.09:49:29.00:"tape 2006.173.09:49:29.00:"st=record 2006.173.09:49:29.00:data_valid=on 2006.173.09:49:29.00:midob 2006.173.09:49:30.14/onsource/TRACKING 2006.173.09:49:30.14/wx/22.70,1004.5,87 2006.173.09:49:30.24/cable/+6.5008E-03 2006.173.09:49:31.33/va/01,07,usb,yes,34,37 2006.173.09:49:31.33/va/02,06,usb,yes,34,35 2006.173.09:49:31.33/va/03,05,usb,yes,43,45 2006.173.09:49:31.33/va/04,06,usb,yes,34,36 2006.173.09:49:31.33/va/05,04,usb,yes,27,28 2006.173.09:49:31.33/va/06,03,usb,yes,38,38 2006.173.09:49:31.33/va/07,04,usb,yes,31,32 2006.173.09:49:31.33/va/08,04,usb,yes,26,32 2006.173.09:49:31.56/valo/01,524.99,yes,locked 2006.173.09:49:31.56/valo/02,534.99,yes,locked 2006.173.09:49:31.56/valo/03,564.99,yes,locked 2006.173.09:49:31.56/valo/04,624.99,yes,locked 2006.173.09:49:31.56/valo/05,734.99,yes,locked 2006.173.09:49:31.56/valo/06,814.99,yes,locked 2006.173.09:49:31.56/valo/07,864.99,yes,locked 2006.173.09:49:31.56/valo/08,884.99,yes,locked 2006.173.09:49:32.65/vb/01,04,usb,yes,28,26 2006.173.09:49:32.65/vb/02,04,usb,yes,31,30 2006.173.09:49:32.65/vb/03,04,usb,yes,28,30 2006.173.09:49:32.65/vb/04,04,usb,yes,32,31 2006.173.09:49:32.65/vb/05,04,usb,yes,25,27 2006.173.09:49:32.65/vb/06,04,usb,yes,29,25 2006.173.09:49:32.65/vb/07,04,usb,yes,29,29 2006.173.09:49:32.65/vb/08,04,usb,yes,26,30 2006.173.09:49:32.88/vblo/01,629.99,yes,locked 2006.173.09:49:32.88/vblo/02,634.99,yes,locked 2006.173.09:49:32.88/vblo/03,649.99,yes,locked 2006.173.09:49:32.88/vblo/04,679.99,yes,locked 2006.173.09:49:32.88/vblo/05,709.99,yes,locked 2006.173.09:49:32.88/vblo/06,719.99,yes,locked 2006.173.09:49:32.88/vblo/07,734.99,yes,locked 2006.173.09:49:32.88/vblo/08,744.99,yes,locked 2006.173.09:49:33.03/vabw/8 2006.173.09:49:33.18/vbbw/8 2006.173.09:49:33.27/xfe/off,on,14.5 2006.173.09:49:33.64/ifatt/23,28,28,28 2006.173.09:49:34.07/fmout-gps/S +4.03E-07 2006.173.09:49:34.12:!2006.173.09:55:29 2006.173.09:55:29.00:data_valid=off 2006.173.09:55:29.00:"et 2006.173.09:55:29.00:!+3s 2006.173.09:55:32.01:"tape 2006.173.09:55:32.01:postob 2006.173.09:55:32.24/cable/+6.5012E-03 2006.173.09:55:32.24/wx/22.84,1004.4,90 2006.173.09:55:33.07/fmout-gps/S +4.00E-07 2006.173.09:55:33.07:scan_name=173-1001,jd0606,100 2006.173.09:55:33.07:source=1334-127,133739.78,-125724.7,2000.0,cw 2006.173.09:55:33.14#flagr#flagr/antenna,new-source 2006.173.09:55:34.14:checkk5 2006.173.09:55:34.54/chk_autoobs//k5ts1/ autoobs is running! 2006.173.09:55:34.93/chk_autoobs//k5ts2/ autoobs is running! 2006.173.09:55:35.35/chk_autoobs//k5ts3/ autoobs is running! 2006.173.09:55:35.75/chk_autoobs//k5ts4/ autoobs is running! 2006.173.09:55:36.14/chk_obsdata//k5ts1/T1730949??a.dat file size is correct (nominal:1440MB, actual:1436MB). 2006.173.09:55:36.54/chk_obsdata//k5ts2/T1730949??b.dat file size is correct (nominal:1440MB, actual:1436MB). 2006.173.09:55:36.96/chk_obsdata//k5ts3/T1730949??c.dat file size is correct (nominal:1440MB, actual:1436MB). 2006.173.09:55:37.37/chk_obsdata//k5ts4/T1730949??d.dat file size is correct (nominal:1440MB, actual:1436MB). 2006.173.09:55:38.09/k5log//k5ts1_log_newline 2006.173.09:55:38.80/k5log//k5ts2_log_newline 2006.173.09:55:39.51/k5log//k5ts3_log_newline 2006.173.09:55:40.21/k5log//k5ts4_log_newline 2006.173.09:55:40.24/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.09:55:40.24:setupk4=1 2006.173.09:55:40.24$setupk4/echo=on 2006.173.09:55:40.24$setupk4/pcalon 2006.173.09:55:40.24$pcalon/"no phase cal control is implemented here 2006.173.09:55:40.24$setupk4/"tpicd=stop 2006.173.09:55:40.24$setupk4/"rec=synch_on 2006.173.09:55:40.24$setupk4/"rec_mode=128 2006.173.09:55:40.24$setupk4/!* 2006.173.09:55:40.24$setupk4/recpk4 2006.173.09:55:40.24$recpk4/recpatch= 2006.173.09:55:40.24$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.09:55:40.24$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.09:55:40.24$setupk4/vck44 2006.173.09:55:40.24$vck44/valo=1,524.99 2006.173.09:55:40.24#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.09:55:40.24#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.09:55:40.24#ibcon#ireg 17 cls_cnt 0 2006.173.09:55:40.24#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.09:55:40.24#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.09:55:40.24#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.09:55:40.24#ibcon#enter wrdev, iclass 21, count 0 2006.173.09:55:40.24#ibcon#first serial, iclass 21, count 0 2006.173.09:55:40.24#ibcon#enter sib2, iclass 21, count 0 2006.173.09:55:40.24#ibcon#flushed, iclass 21, count 0 2006.173.09:55:40.24#ibcon#about to write, iclass 21, count 0 2006.173.09:55:40.24#ibcon#wrote, iclass 21, count 0 2006.173.09:55:40.24#ibcon#about to read 3, iclass 21, count 0 2006.173.09:55:40.26#ibcon#read 3, iclass 21, count 0 2006.173.09:55:40.26#ibcon#about to read 4, iclass 21, count 0 2006.173.09:55:40.26#ibcon#read 4, iclass 21, count 0 2006.173.09:55:40.26#ibcon#about to read 5, iclass 21, count 0 2006.173.09:55:40.26#ibcon#read 5, iclass 21, count 0 2006.173.09:55:40.26#ibcon#about to read 6, iclass 21, count 0 2006.173.09:55:40.26#ibcon#read 6, iclass 21, count 0 2006.173.09:55:40.26#ibcon#end of sib2, iclass 21, count 0 2006.173.09:55:40.26#ibcon#*mode == 0, iclass 21, count 0 2006.173.09:55:40.26#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.09:55:40.26#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.09:55:40.26#ibcon#*before write, iclass 21, count 0 2006.173.09:55:40.26#ibcon#enter sib2, iclass 21, count 0 2006.173.09:55:40.26#ibcon#flushed, iclass 21, count 0 2006.173.09:55:40.26#ibcon#about to write, iclass 21, count 0 2006.173.09:55:40.26#ibcon#wrote, iclass 21, count 0 2006.173.09:55:40.26#ibcon#about to read 3, iclass 21, count 0 2006.173.09:55:40.31#ibcon#read 3, iclass 21, count 0 2006.173.09:55:40.31#ibcon#about to read 4, iclass 21, count 0 2006.173.09:55:40.31#ibcon#read 4, iclass 21, count 0 2006.173.09:55:40.31#ibcon#about to read 5, iclass 21, count 0 2006.173.09:55:40.31#ibcon#read 5, iclass 21, count 0 2006.173.09:55:40.31#ibcon#about to read 6, iclass 21, count 0 2006.173.09:55:40.31#ibcon#read 6, iclass 21, count 0 2006.173.09:55:40.31#ibcon#end of sib2, iclass 21, count 0 2006.173.09:55:40.31#ibcon#*after write, iclass 21, count 0 2006.173.09:55:40.31#ibcon#*before return 0, iclass 21, count 0 2006.173.09:55:40.31#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.09:55:40.31#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.09:55:40.31#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.09:55:40.31#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.09:55:40.31$vck44/va=1,7 2006.173.09:55:40.31#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.09:55:40.31#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.09:55:40.31#ibcon#ireg 11 cls_cnt 2 2006.173.09:55:40.31#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.09:55:40.31#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.09:55:40.31#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.09:55:40.31#ibcon#enter wrdev, iclass 23, count 2 2006.173.09:55:40.31#ibcon#first serial, iclass 23, count 2 2006.173.09:55:40.31#ibcon#enter sib2, iclass 23, count 2 2006.173.09:55:40.31#ibcon#flushed, iclass 23, count 2 2006.173.09:55:40.31#ibcon#about to write, iclass 23, count 2 2006.173.09:55:40.31#ibcon#wrote, iclass 23, count 2 2006.173.09:55:40.31#ibcon#about to read 3, iclass 23, count 2 2006.173.09:55:40.33#ibcon#read 3, iclass 23, count 2 2006.173.09:55:40.33#ibcon#about to read 4, iclass 23, count 2 2006.173.09:55:40.33#ibcon#read 4, iclass 23, count 2 2006.173.09:55:40.33#ibcon#about to read 5, iclass 23, count 2 2006.173.09:55:40.33#ibcon#read 5, iclass 23, count 2 2006.173.09:55:40.33#ibcon#about to read 6, iclass 23, count 2 2006.173.09:55:40.33#ibcon#read 6, iclass 23, count 2 2006.173.09:55:40.33#ibcon#end of sib2, iclass 23, count 2 2006.173.09:55:40.33#ibcon#*mode == 0, iclass 23, count 2 2006.173.09:55:40.33#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.09:55:40.33#ibcon#[25=AT01-07\r\n] 2006.173.09:55:40.33#ibcon#*before write, iclass 23, count 2 2006.173.09:55:40.33#ibcon#enter sib2, iclass 23, count 2 2006.173.09:55:40.33#ibcon#flushed, iclass 23, count 2 2006.173.09:55:40.33#ibcon#about to write, iclass 23, count 2 2006.173.09:55:40.33#ibcon#wrote, iclass 23, count 2 2006.173.09:55:40.33#ibcon#about to read 3, iclass 23, count 2 2006.173.09:55:40.36#ibcon#read 3, iclass 23, count 2 2006.173.09:55:40.36#ibcon#about to read 4, iclass 23, count 2 2006.173.09:55:40.36#ibcon#read 4, iclass 23, count 2 2006.173.09:55:40.36#ibcon#about to read 5, iclass 23, count 2 2006.173.09:55:40.36#ibcon#read 5, iclass 23, count 2 2006.173.09:55:40.36#ibcon#about to read 6, iclass 23, count 2 2006.173.09:55:40.36#ibcon#read 6, iclass 23, count 2 2006.173.09:55:40.36#ibcon#end of sib2, iclass 23, count 2 2006.173.09:55:40.36#ibcon#*after write, iclass 23, count 2 2006.173.09:55:40.36#ibcon#*before return 0, iclass 23, count 2 2006.173.09:55:40.36#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.09:55:40.36#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.09:55:40.36#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.09:55:40.36#ibcon#ireg 7 cls_cnt 0 2006.173.09:55:40.36#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.09:55:40.48#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.09:55:40.48#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.09:55:40.48#ibcon#enter wrdev, iclass 23, count 0 2006.173.09:55:40.48#ibcon#first serial, iclass 23, count 0 2006.173.09:55:40.48#ibcon#enter sib2, iclass 23, count 0 2006.173.09:55:40.48#ibcon#flushed, iclass 23, count 0 2006.173.09:55:40.48#ibcon#about to write, iclass 23, count 0 2006.173.09:55:40.48#ibcon#wrote, iclass 23, count 0 2006.173.09:55:40.48#ibcon#about to read 3, iclass 23, count 0 2006.173.09:55:40.50#ibcon#read 3, iclass 23, count 0 2006.173.09:55:40.50#ibcon#about to read 4, iclass 23, count 0 2006.173.09:55:40.50#ibcon#read 4, iclass 23, count 0 2006.173.09:55:40.50#ibcon#about to read 5, iclass 23, count 0 2006.173.09:55:40.50#ibcon#read 5, iclass 23, count 0 2006.173.09:55:40.50#ibcon#about to read 6, iclass 23, count 0 2006.173.09:55:40.50#ibcon#read 6, iclass 23, count 0 2006.173.09:55:40.50#ibcon#end of sib2, iclass 23, count 0 2006.173.09:55:40.50#ibcon#*mode == 0, iclass 23, count 0 2006.173.09:55:40.50#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.09:55:40.50#ibcon#[25=USB\r\n] 2006.173.09:55:40.50#ibcon#*before write, iclass 23, count 0 2006.173.09:55:40.50#ibcon#enter sib2, iclass 23, count 0 2006.173.09:55:40.50#ibcon#flushed, iclass 23, count 0 2006.173.09:55:40.50#ibcon#about to write, iclass 23, count 0 2006.173.09:55:40.50#ibcon#wrote, iclass 23, count 0 2006.173.09:55:40.50#ibcon#about to read 3, iclass 23, count 0 2006.173.09:55:40.53#ibcon#read 3, iclass 23, count 0 2006.173.09:55:40.53#ibcon#about to read 4, iclass 23, count 0 2006.173.09:55:40.53#ibcon#read 4, iclass 23, count 0 2006.173.09:55:40.53#ibcon#about to read 5, iclass 23, count 0 2006.173.09:55:40.53#ibcon#read 5, iclass 23, count 0 2006.173.09:55:40.53#ibcon#about to read 6, iclass 23, count 0 2006.173.09:55:40.53#ibcon#read 6, iclass 23, count 0 2006.173.09:55:40.53#ibcon#end of sib2, iclass 23, count 0 2006.173.09:55:40.53#ibcon#*after write, iclass 23, count 0 2006.173.09:55:40.53#ibcon#*before return 0, iclass 23, count 0 2006.173.09:55:40.53#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.09:55:40.53#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.09:55:40.53#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.09:55:40.53#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.09:55:40.53$vck44/valo=2,534.99 2006.173.09:55:40.53#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.09:55:40.53#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.09:55:40.53#ibcon#ireg 17 cls_cnt 0 2006.173.09:55:40.53#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.09:55:40.53#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.09:55:40.53#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.09:55:40.53#ibcon#enter wrdev, iclass 25, count 0 2006.173.09:55:40.53#ibcon#first serial, iclass 25, count 0 2006.173.09:55:40.53#ibcon#enter sib2, iclass 25, count 0 2006.173.09:55:40.53#ibcon#flushed, iclass 25, count 0 2006.173.09:55:40.53#ibcon#about to write, iclass 25, count 0 2006.173.09:55:40.53#ibcon#wrote, iclass 25, count 0 2006.173.09:55:40.53#ibcon#about to read 3, iclass 25, count 0 2006.173.09:55:40.55#ibcon#read 3, iclass 25, count 0 2006.173.09:55:40.55#ibcon#about to read 4, iclass 25, count 0 2006.173.09:55:40.55#ibcon#read 4, iclass 25, count 0 2006.173.09:55:40.55#ibcon#about to read 5, iclass 25, count 0 2006.173.09:55:40.55#ibcon#read 5, iclass 25, count 0 2006.173.09:55:40.55#ibcon#about to read 6, iclass 25, count 0 2006.173.09:55:40.55#ibcon#read 6, iclass 25, count 0 2006.173.09:55:40.55#ibcon#end of sib2, iclass 25, count 0 2006.173.09:55:40.55#ibcon#*mode == 0, iclass 25, count 0 2006.173.09:55:40.55#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.09:55:40.55#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.09:55:40.55#ibcon#*before write, iclass 25, count 0 2006.173.09:55:40.55#ibcon#enter sib2, iclass 25, count 0 2006.173.09:55:40.55#ibcon#flushed, iclass 25, count 0 2006.173.09:55:40.55#ibcon#about to write, iclass 25, count 0 2006.173.09:55:40.55#ibcon#wrote, iclass 25, count 0 2006.173.09:55:40.55#ibcon#about to read 3, iclass 25, count 0 2006.173.09:55:40.59#ibcon#read 3, iclass 25, count 0 2006.173.09:55:40.59#ibcon#about to read 4, iclass 25, count 0 2006.173.09:55:40.59#ibcon#read 4, iclass 25, count 0 2006.173.09:55:40.59#ibcon#about to read 5, iclass 25, count 0 2006.173.09:55:40.59#ibcon#read 5, iclass 25, count 0 2006.173.09:55:40.59#ibcon#about to read 6, iclass 25, count 0 2006.173.09:55:40.59#ibcon#read 6, iclass 25, count 0 2006.173.09:55:40.59#ibcon#end of sib2, iclass 25, count 0 2006.173.09:55:40.59#ibcon#*after write, iclass 25, count 0 2006.173.09:55:40.59#ibcon#*before return 0, iclass 25, count 0 2006.173.09:55:40.59#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.09:55:40.59#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.09:55:40.59#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.09:55:40.59#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.09:55:40.59$vck44/va=2,6 2006.173.09:55:40.59#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.09:55:40.59#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.09:55:40.59#ibcon#ireg 11 cls_cnt 2 2006.173.09:55:40.59#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.09:55:40.65#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.09:55:40.65#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.09:55:40.65#ibcon#enter wrdev, iclass 27, count 2 2006.173.09:55:40.65#ibcon#first serial, iclass 27, count 2 2006.173.09:55:40.65#ibcon#enter sib2, iclass 27, count 2 2006.173.09:55:40.65#ibcon#flushed, iclass 27, count 2 2006.173.09:55:40.65#ibcon#about to write, iclass 27, count 2 2006.173.09:55:40.65#ibcon#wrote, iclass 27, count 2 2006.173.09:55:40.65#ibcon#about to read 3, iclass 27, count 2 2006.173.09:55:40.67#ibcon#read 3, iclass 27, count 2 2006.173.09:55:40.67#ibcon#about to read 4, iclass 27, count 2 2006.173.09:55:40.67#ibcon#read 4, iclass 27, count 2 2006.173.09:55:40.67#ibcon#about to read 5, iclass 27, count 2 2006.173.09:55:40.67#ibcon#read 5, iclass 27, count 2 2006.173.09:55:40.67#ibcon#about to read 6, iclass 27, count 2 2006.173.09:55:40.67#ibcon#read 6, iclass 27, count 2 2006.173.09:55:40.67#ibcon#end of sib2, iclass 27, count 2 2006.173.09:55:40.67#ibcon#*mode == 0, iclass 27, count 2 2006.173.09:55:40.67#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.09:55:40.67#ibcon#[25=AT02-06\r\n] 2006.173.09:55:40.67#ibcon#*before write, iclass 27, count 2 2006.173.09:55:40.67#ibcon#enter sib2, iclass 27, count 2 2006.173.09:55:40.67#ibcon#flushed, iclass 27, count 2 2006.173.09:55:40.67#ibcon#about to write, iclass 27, count 2 2006.173.09:55:40.67#ibcon#wrote, iclass 27, count 2 2006.173.09:55:40.67#ibcon#about to read 3, iclass 27, count 2 2006.173.09:55:40.70#ibcon#read 3, iclass 27, count 2 2006.173.09:55:40.70#ibcon#about to read 4, iclass 27, count 2 2006.173.09:55:40.70#ibcon#read 4, iclass 27, count 2 2006.173.09:55:40.70#ibcon#about to read 5, iclass 27, count 2 2006.173.09:55:40.70#ibcon#read 5, iclass 27, count 2 2006.173.09:55:40.70#ibcon#about to read 6, iclass 27, count 2 2006.173.09:55:40.70#ibcon#read 6, iclass 27, count 2 2006.173.09:55:40.70#ibcon#end of sib2, iclass 27, count 2 2006.173.09:55:40.70#ibcon#*after write, iclass 27, count 2 2006.173.09:55:40.70#ibcon#*before return 0, iclass 27, count 2 2006.173.09:55:40.70#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.09:55:40.70#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.09:55:40.70#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.09:55:40.70#ibcon#ireg 7 cls_cnt 0 2006.173.09:55:40.70#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.09:55:40.82#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.09:55:40.82#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.09:55:40.82#ibcon#enter wrdev, iclass 27, count 0 2006.173.09:55:40.82#ibcon#first serial, iclass 27, count 0 2006.173.09:55:40.82#ibcon#enter sib2, iclass 27, count 0 2006.173.09:55:40.82#ibcon#flushed, iclass 27, count 0 2006.173.09:55:40.82#ibcon#about to write, iclass 27, count 0 2006.173.09:55:40.82#ibcon#wrote, iclass 27, count 0 2006.173.09:55:40.82#ibcon#about to read 3, iclass 27, count 0 2006.173.09:55:40.84#ibcon#read 3, iclass 27, count 0 2006.173.09:55:40.84#ibcon#about to read 4, iclass 27, count 0 2006.173.09:55:40.84#ibcon#read 4, iclass 27, count 0 2006.173.09:55:40.84#ibcon#about to read 5, iclass 27, count 0 2006.173.09:55:40.84#ibcon#read 5, iclass 27, count 0 2006.173.09:55:40.84#ibcon#about to read 6, iclass 27, count 0 2006.173.09:55:40.84#ibcon#read 6, iclass 27, count 0 2006.173.09:55:40.84#ibcon#end of sib2, iclass 27, count 0 2006.173.09:55:40.84#ibcon#*mode == 0, iclass 27, count 0 2006.173.09:55:40.84#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.09:55:40.84#ibcon#[25=USB\r\n] 2006.173.09:55:40.84#ibcon#*before write, iclass 27, count 0 2006.173.09:55:40.84#ibcon#enter sib2, iclass 27, count 0 2006.173.09:55:40.84#ibcon#flushed, iclass 27, count 0 2006.173.09:55:40.84#ibcon#about to write, iclass 27, count 0 2006.173.09:55:40.84#ibcon#wrote, iclass 27, count 0 2006.173.09:55:40.84#ibcon#about to read 3, iclass 27, count 0 2006.173.09:55:40.87#ibcon#read 3, iclass 27, count 0 2006.173.09:55:40.87#ibcon#about to read 4, iclass 27, count 0 2006.173.09:55:40.87#ibcon#read 4, iclass 27, count 0 2006.173.09:55:40.87#ibcon#about to read 5, iclass 27, count 0 2006.173.09:55:40.87#ibcon#read 5, iclass 27, count 0 2006.173.09:55:40.87#ibcon#about to read 6, iclass 27, count 0 2006.173.09:55:40.87#ibcon#read 6, iclass 27, count 0 2006.173.09:55:40.87#ibcon#end of sib2, iclass 27, count 0 2006.173.09:55:40.87#ibcon#*after write, iclass 27, count 0 2006.173.09:55:40.87#ibcon#*before return 0, iclass 27, count 0 2006.173.09:55:40.87#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.09:55:40.87#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.09:55:40.87#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.09:55:40.87#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.09:55:40.87$vck44/valo=3,564.99 2006.173.09:55:40.87#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.09:55:40.87#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.09:55:40.87#ibcon#ireg 17 cls_cnt 0 2006.173.09:55:40.87#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.09:55:40.87#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.09:55:40.87#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.09:55:40.87#ibcon#enter wrdev, iclass 29, count 0 2006.173.09:55:40.87#ibcon#first serial, iclass 29, count 0 2006.173.09:55:40.87#ibcon#enter sib2, iclass 29, count 0 2006.173.09:55:40.87#ibcon#flushed, iclass 29, count 0 2006.173.09:55:40.87#ibcon#about to write, iclass 29, count 0 2006.173.09:55:40.87#ibcon#wrote, iclass 29, count 0 2006.173.09:55:40.87#ibcon#about to read 3, iclass 29, count 0 2006.173.09:55:40.89#ibcon#read 3, iclass 29, count 0 2006.173.09:55:40.89#ibcon#about to read 4, iclass 29, count 0 2006.173.09:55:40.89#ibcon#read 4, iclass 29, count 0 2006.173.09:55:40.89#ibcon#about to read 5, iclass 29, count 0 2006.173.09:55:40.89#ibcon#read 5, iclass 29, count 0 2006.173.09:55:40.89#ibcon#about to read 6, iclass 29, count 0 2006.173.09:55:40.89#ibcon#read 6, iclass 29, count 0 2006.173.09:55:40.89#ibcon#end of sib2, iclass 29, count 0 2006.173.09:55:40.89#ibcon#*mode == 0, iclass 29, count 0 2006.173.09:55:40.89#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.09:55:40.89#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.09:55:40.89#ibcon#*before write, iclass 29, count 0 2006.173.09:55:40.89#ibcon#enter sib2, iclass 29, count 0 2006.173.09:55:40.89#ibcon#flushed, iclass 29, count 0 2006.173.09:55:40.89#ibcon#about to write, iclass 29, count 0 2006.173.09:55:40.89#ibcon#wrote, iclass 29, count 0 2006.173.09:55:40.89#ibcon#about to read 3, iclass 29, count 0 2006.173.09:55:40.93#ibcon#read 3, iclass 29, count 0 2006.173.09:55:40.93#ibcon#about to read 4, iclass 29, count 0 2006.173.09:55:40.93#ibcon#read 4, iclass 29, count 0 2006.173.09:55:40.93#ibcon#about to read 5, iclass 29, count 0 2006.173.09:55:40.93#ibcon#read 5, iclass 29, count 0 2006.173.09:55:40.93#ibcon#about to read 6, iclass 29, count 0 2006.173.09:55:40.93#ibcon#read 6, iclass 29, count 0 2006.173.09:55:40.93#ibcon#end of sib2, iclass 29, count 0 2006.173.09:55:40.93#ibcon#*after write, iclass 29, count 0 2006.173.09:55:40.93#ibcon#*before return 0, iclass 29, count 0 2006.173.09:55:40.93#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.09:55:40.93#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.09:55:40.93#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.09:55:40.93#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.09:55:40.93$vck44/va=3,5 2006.173.09:55:40.93#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.09:55:40.93#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.09:55:40.93#ibcon#ireg 11 cls_cnt 2 2006.173.09:55:40.93#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.09:55:40.99#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.09:55:40.99#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.09:55:40.99#ibcon#enter wrdev, iclass 31, count 2 2006.173.09:55:40.99#ibcon#first serial, iclass 31, count 2 2006.173.09:55:40.99#ibcon#enter sib2, iclass 31, count 2 2006.173.09:55:40.99#ibcon#flushed, iclass 31, count 2 2006.173.09:55:40.99#ibcon#about to write, iclass 31, count 2 2006.173.09:55:40.99#ibcon#wrote, iclass 31, count 2 2006.173.09:55:40.99#ibcon#about to read 3, iclass 31, count 2 2006.173.09:55:41.01#ibcon#read 3, iclass 31, count 2 2006.173.09:55:41.01#ibcon#about to read 4, iclass 31, count 2 2006.173.09:55:41.01#ibcon#read 4, iclass 31, count 2 2006.173.09:55:41.01#ibcon#about to read 5, iclass 31, count 2 2006.173.09:55:41.01#ibcon#read 5, iclass 31, count 2 2006.173.09:55:41.01#ibcon#about to read 6, iclass 31, count 2 2006.173.09:55:41.01#ibcon#read 6, iclass 31, count 2 2006.173.09:55:41.01#ibcon#end of sib2, iclass 31, count 2 2006.173.09:55:41.01#ibcon#*mode == 0, iclass 31, count 2 2006.173.09:55:41.01#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.09:55:41.01#ibcon#[25=AT03-05\r\n] 2006.173.09:55:41.01#ibcon#*before write, iclass 31, count 2 2006.173.09:55:41.01#ibcon#enter sib2, iclass 31, count 2 2006.173.09:55:41.01#ibcon#flushed, iclass 31, count 2 2006.173.09:55:41.01#ibcon#about to write, iclass 31, count 2 2006.173.09:55:41.01#ibcon#wrote, iclass 31, count 2 2006.173.09:55:41.01#ibcon#about to read 3, iclass 31, count 2 2006.173.09:55:41.04#ibcon#read 3, iclass 31, count 2 2006.173.09:55:41.04#ibcon#about to read 4, iclass 31, count 2 2006.173.09:55:41.04#ibcon#read 4, iclass 31, count 2 2006.173.09:55:41.04#ibcon#about to read 5, iclass 31, count 2 2006.173.09:55:41.04#ibcon#read 5, iclass 31, count 2 2006.173.09:55:41.04#ibcon#about to read 6, iclass 31, count 2 2006.173.09:55:41.04#ibcon#read 6, iclass 31, count 2 2006.173.09:55:41.04#ibcon#end of sib2, iclass 31, count 2 2006.173.09:55:41.04#ibcon#*after write, iclass 31, count 2 2006.173.09:55:41.04#ibcon#*before return 0, iclass 31, count 2 2006.173.09:55:41.04#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.09:55:41.04#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.09:55:41.04#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.09:55:41.04#ibcon#ireg 7 cls_cnt 0 2006.173.09:55:41.04#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.09:55:41.16#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.09:55:41.16#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.09:55:41.16#ibcon#enter wrdev, iclass 31, count 0 2006.173.09:55:41.16#ibcon#first serial, iclass 31, count 0 2006.173.09:55:41.16#ibcon#enter sib2, iclass 31, count 0 2006.173.09:55:41.16#ibcon#flushed, iclass 31, count 0 2006.173.09:55:41.16#ibcon#about to write, iclass 31, count 0 2006.173.09:55:41.16#ibcon#wrote, iclass 31, count 0 2006.173.09:55:41.16#ibcon#about to read 3, iclass 31, count 0 2006.173.09:55:41.18#ibcon#read 3, iclass 31, count 0 2006.173.09:55:41.18#ibcon#about to read 4, iclass 31, count 0 2006.173.09:55:41.18#ibcon#read 4, iclass 31, count 0 2006.173.09:55:41.18#ibcon#about to read 5, iclass 31, count 0 2006.173.09:55:41.18#ibcon#read 5, iclass 31, count 0 2006.173.09:55:41.18#ibcon#about to read 6, iclass 31, count 0 2006.173.09:55:41.18#ibcon#read 6, iclass 31, count 0 2006.173.09:55:41.18#ibcon#end of sib2, iclass 31, count 0 2006.173.09:55:41.18#ibcon#*mode == 0, iclass 31, count 0 2006.173.09:55:41.18#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.09:55:41.18#ibcon#[25=USB\r\n] 2006.173.09:55:41.18#ibcon#*before write, iclass 31, count 0 2006.173.09:55:41.18#ibcon#enter sib2, iclass 31, count 0 2006.173.09:55:41.18#ibcon#flushed, iclass 31, count 0 2006.173.09:55:41.18#ibcon#about to write, iclass 31, count 0 2006.173.09:55:41.18#ibcon#wrote, iclass 31, count 0 2006.173.09:55:41.18#ibcon#about to read 3, iclass 31, count 0 2006.173.09:55:41.21#ibcon#read 3, iclass 31, count 0 2006.173.09:55:41.21#ibcon#about to read 4, iclass 31, count 0 2006.173.09:55:41.21#ibcon#read 4, iclass 31, count 0 2006.173.09:55:41.21#ibcon#about to read 5, iclass 31, count 0 2006.173.09:55:41.21#ibcon#read 5, iclass 31, count 0 2006.173.09:55:41.21#ibcon#about to read 6, iclass 31, count 0 2006.173.09:55:41.21#ibcon#read 6, iclass 31, count 0 2006.173.09:55:41.21#ibcon#end of sib2, iclass 31, count 0 2006.173.09:55:41.21#ibcon#*after write, iclass 31, count 0 2006.173.09:55:41.21#ibcon#*before return 0, iclass 31, count 0 2006.173.09:55:41.21#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.09:55:41.21#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.09:55:41.21#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.09:55:41.21#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.09:55:41.21$vck44/valo=4,624.99 2006.173.09:55:41.21#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.09:55:41.21#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.09:55:41.21#ibcon#ireg 17 cls_cnt 0 2006.173.09:55:41.21#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.09:55:41.21#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.09:55:41.21#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.09:55:41.21#ibcon#enter wrdev, iclass 33, count 0 2006.173.09:55:41.21#ibcon#first serial, iclass 33, count 0 2006.173.09:55:41.21#ibcon#enter sib2, iclass 33, count 0 2006.173.09:55:41.21#ibcon#flushed, iclass 33, count 0 2006.173.09:55:41.21#ibcon#about to write, iclass 33, count 0 2006.173.09:55:41.21#ibcon#wrote, iclass 33, count 0 2006.173.09:55:41.21#ibcon#about to read 3, iclass 33, count 0 2006.173.09:55:41.23#ibcon#read 3, iclass 33, count 0 2006.173.09:55:41.23#ibcon#about to read 4, iclass 33, count 0 2006.173.09:55:41.23#ibcon#read 4, iclass 33, count 0 2006.173.09:55:41.23#ibcon#about to read 5, iclass 33, count 0 2006.173.09:55:41.23#ibcon#read 5, iclass 33, count 0 2006.173.09:55:41.23#ibcon#about to read 6, iclass 33, count 0 2006.173.09:55:41.23#ibcon#read 6, iclass 33, count 0 2006.173.09:55:41.23#ibcon#end of sib2, iclass 33, count 0 2006.173.09:55:41.23#ibcon#*mode == 0, iclass 33, count 0 2006.173.09:55:41.23#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.09:55:41.23#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.09:55:41.23#ibcon#*before write, iclass 33, count 0 2006.173.09:55:41.23#ibcon#enter sib2, iclass 33, count 0 2006.173.09:55:41.23#ibcon#flushed, iclass 33, count 0 2006.173.09:55:41.23#ibcon#about to write, iclass 33, count 0 2006.173.09:55:41.23#ibcon#wrote, iclass 33, count 0 2006.173.09:55:41.23#ibcon#about to read 3, iclass 33, count 0 2006.173.09:55:41.27#ibcon#read 3, iclass 33, count 0 2006.173.09:55:41.27#ibcon#about to read 4, iclass 33, count 0 2006.173.09:55:41.27#ibcon#read 4, iclass 33, count 0 2006.173.09:55:41.27#ibcon#about to read 5, iclass 33, count 0 2006.173.09:55:41.27#ibcon#read 5, iclass 33, count 0 2006.173.09:55:41.27#ibcon#about to read 6, iclass 33, count 0 2006.173.09:55:41.27#ibcon#read 6, iclass 33, count 0 2006.173.09:55:41.27#ibcon#end of sib2, iclass 33, count 0 2006.173.09:55:41.27#ibcon#*after write, iclass 33, count 0 2006.173.09:55:41.27#ibcon#*before return 0, iclass 33, count 0 2006.173.09:55:41.27#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.09:55:41.27#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.09:55:41.27#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.09:55:41.27#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.09:55:41.27$vck44/va=4,6 2006.173.09:55:41.27#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.09:55:41.27#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.09:55:41.27#ibcon#ireg 11 cls_cnt 2 2006.173.09:55:41.27#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.09:55:41.33#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.09:55:41.33#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.09:55:41.33#ibcon#enter wrdev, iclass 35, count 2 2006.173.09:55:41.33#ibcon#first serial, iclass 35, count 2 2006.173.09:55:41.33#ibcon#enter sib2, iclass 35, count 2 2006.173.09:55:41.33#ibcon#flushed, iclass 35, count 2 2006.173.09:55:41.33#ibcon#about to write, iclass 35, count 2 2006.173.09:55:41.33#ibcon#wrote, iclass 35, count 2 2006.173.09:55:41.33#ibcon#about to read 3, iclass 35, count 2 2006.173.09:55:41.35#ibcon#read 3, iclass 35, count 2 2006.173.09:55:41.35#ibcon#about to read 4, iclass 35, count 2 2006.173.09:55:41.35#ibcon#read 4, iclass 35, count 2 2006.173.09:55:41.35#ibcon#about to read 5, iclass 35, count 2 2006.173.09:55:41.35#ibcon#read 5, iclass 35, count 2 2006.173.09:55:41.35#ibcon#about to read 6, iclass 35, count 2 2006.173.09:55:41.35#ibcon#read 6, iclass 35, count 2 2006.173.09:55:41.35#ibcon#end of sib2, iclass 35, count 2 2006.173.09:55:41.35#ibcon#*mode == 0, iclass 35, count 2 2006.173.09:55:41.35#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.09:55:41.35#ibcon#[25=AT04-06\r\n] 2006.173.09:55:41.35#ibcon#*before write, iclass 35, count 2 2006.173.09:55:41.35#ibcon#enter sib2, iclass 35, count 2 2006.173.09:55:41.35#ibcon#flushed, iclass 35, count 2 2006.173.09:55:41.35#ibcon#about to write, iclass 35, count 2 2006.173.09:55:41.35#ibcon#wrote, iclass 35, count 2 2006.173.09:55:41.35#ibcon#about to read 3, iclass 35, count 2 2006.173.09:55:41.38#ibcon#read 3, iclass 35, count 2 2006.173.09:55:41.38#ibcon#about to read 4, iclass 35, count 2 2006.173.09:55:41.38#ibcon#read 4, iclass 35, count 2 2006.173.09:55:41.38#ibcon#about to read 5, iclass 35, count 2 2006.173.09:55:41.38#ibcon#read 5, iclass 35, count 2 2006.173.09:55:41.38#ibcon#about to read 6, iclass 35, count 2 2006.173.09:55:41.38#ibcon#read 6, iclass 35, count 2 2006.173.09:55:41.38#ibcon#end of sib2, iclass 35, count 2 2006.173.09:55:41.38#ibcon#*after write, iclass 35, count 2 2006.173.09:55:41.38#ibcon#*before return 0, iclass 35, count 2 2006.173.09:55:41.38#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.09:55:41.38#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.09:55:41.38#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.09:55:41.38#ibcon#ireg 7 cls_cnt 0 2006.173.09:55:41.38#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.09:55:41.50#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.09:55:41.50#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.09:55:41.50#ibcon#enter wrdev, iclass 35, count 0 2006.173.09:55:41.50#ibcon#first serial, iclass 35, count 0 2006.173.09:55:41.50#ibcon#enter sib2, iclass 35, count 0 2006.173.09:55:41.50#ibcon#flushed, iclass 35, count 0 2006.173.09:55:41.50#ibcon#about to write, iclass 35, count 0 2006.173.09:55:41.50#ibcon#wrote, iclass 35, count 0 2006.173.09:55:41.50#ibcon#about to read 3, iclass 35, count 0 2006.173.09:55:41.52#ibcon#read 3, iclass 35, count 0 2006.173.09:55:41.52#ibcon#about to read 4, iclass 35, count 0 2006.173.09:55:41.52#ibcon#read 4, iclass 35, count 0 2006.173.09:55:41.52#ibcon#about to read 5, iclass 35, count 0 2006.173.09:55:41.52#ibcon#read 5, iclass 35, count 0 2006.173.09:55:41.52#ibcon#about to read 6, iclass 35, count 0 2006.173.09:55:41.52#ibcon#read 6, iclass 35, count 0 2006.173.09:55:41.52#ibcon#end of sib2, iclass 35, count 0 2006.173.09:55:41.52#ibcon#*mode == 0, iclass 35, count 0 2006.173.09:55:41.52#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.09:55:41.52#ibcon#[25=USB\r\n] 2006.173.09:55:41.52#ibcon#*before write, iclass 35, count 0 2006.173.09:55:41.52#ibcon#enter sib2, iclass 35, count 0 2006.173.09:55:41.52#ibcon#flushed, iclass 35, count 0 2006.173.09:55:41.52#ibcon#about to write, iclass 35, count 0 2006.173.09:55:41.52#ibcon#wrote, iclass 35, count 0 2006.173.09:55:41.52#ibcon#about to read 3, iclass 35, count 0 2006.173.09:55:41.55#ibcon#read 3, iclass 35, count 0 2006.173.09:55:41.55#ibcon#about to read 4, iclass 35, count 0 2006.173.09:55:41.55#ibcon#read 4, iclass 35, count 0 2006.173.09:55:41.55#ibcon#about to read 5, iclass 35, count 0 2006.173.09:55:41.55#ibcon#read 5, iclass 35, count 0 2006.173.09:55:41.55#ibcon#about to read 6, iclass 35, count 0 2006.173.09:55:41.55#ibcon#read 6, iclass 35, count 0 2006.173.09:55:41.55#ibcon#end of sib2, iclass 35, count 0 2006.173.09:55:41.55#ibcon#*after write, iclass 35, count 0 2006.173.09:55:41.55#ibcon#*before return 0, iclass 35, count 0 2006.173.09:55:41.55#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.09:55:41.55#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.09:55:41.55#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.09:55:41.55#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.09:55:41.55$vck44/valo=5,734.99 2006.173.09:55:41.55#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.09:55:41.55#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.09:55:41.55#ibcon#ireg 17 cls_cnt 0 2006.173.09:55:41.55#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.09:55:41.55#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.09:55:41.55#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.09:55:41.55#ibcon#enter wrdev, iclass 37, count 0 2006.173.09:55:41.55#ibcon#first serial, iclass 37, count 0 2006.173.09:55:41.55#ibcon#enter sib2, iclass 37, count 0 2006.173.09:55:41.55#ibcon#flushed, iclass 37, count 0 2006.173.09:55:41.55#ibcon#about to write, iclass 37, count 0 2006.173.09:55:41.55#ibcon#wrote, iclass 37, count 0 2006.173.09:55:41.55#ibcon#about to read 3, iclass 37, count 0 2006.173.09:55:41.57#ibcon#read 3, iclass 37, count 0 2006.173.09:55:41.57#ibcon#about to read 4, iclass 37, count 0 2006.173.09:55:41.57#ibcon#read 4, iclass 37, count 0 2006.173.09:55:41.57#ibcon#about to read 5, iclass 37, count 0 2006.173.09:55:41.57#ibcon#read 5, iclass 37, count 0 2006.173.09:55:41.57#ibcon#about to read 6, iclass 37, count 0 2006.173.09:55:41.57#ibcon#read 6, iclass 37, count 0 2006.173.09:55:41.57#ibcon#end of sib2, iclass 37, count 0 2006.173.09:55:41.57#ibcon#*mode == 0, iclass 37, count 0 2006.173.09:55:41.57#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.09:55:41.57#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.09:55:41.57#ibcon#*before write, iclass 37, count 0 2006.173.09:55:41.57#ibcon#enter sib2, iclass 37, count 0 2006.173.09:55:41.57#ibcon#flushed, iclass 37, count 0 2006.173.09:55:41.57#ibcon#about to write, iclass 37, count 0 2006.173.09:55:41.57#ibcon#wrote, iclass 37, count 0 2006.173.09:55:41.57#ibcon#about to read 3, iclass 37, count 0 2006.173.09:55:41.61#ibcon#read 3, iclass 37, count 0 2006.173.09:55:41.61#ibcon#about to read 4, iclass 37, count 0 2006.173.09:55:41.61#ibcon#read 4, iclass 37, count 0 2006.173.09:55:41.61#ibcon#about to read 5, iclass 37, count 0 2006.173.09:55:41.61#ibcon#read 5, iclass 37, count 0 2006.173.09:55:41.61#ibcon#about to read 6, iclass 37, count 0 2006.173.09:55:41.61#ibcon#read 6, iclass 37, count 0 2006.173.09:55:41.61#ibcon#end of sib2, iclass 37, count 0 2006.173.09:55:41.61#ibcon#*after write, iclass 37, count 0 2006.173.09:55:41.61#ibcon#*before return 0, iclass 37, count 0 2006.173.09:55:41.61#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.09:55:41.61#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.09:55:41.61#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.09:55:41.61#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.09:55:41.61$vck44/va=5,4 2006.173.09:55:41.61#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.09:55:41.61#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.09:55:41.61#ibcon#ireg 11 cls_cnt 2 2006.173.09:55:41.61#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.09:55:41.67#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.09:55:41.67#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.09:55:41.67#ibcon#enter wrdev, iclass 39, count 2 2006.173.09:55:41.67#ibcon#first serial, iclass 39, count 2 2006.173.09:55:41.67#ibcon#enter sib2, iclass 39, count 2 2006.173.09:55:41.67#ibcon#flushed, iclass 39, count 2 2006.173.09:55:41.67#ibcon#about to write, iclass 39, count 2 2006.173.09:55:41.67#ibcon#wrote, iclass 39, count 2 2006.173.09:55:41.67#ibcon#about to read 3, iclass 39, count 2 2006.173.09:55:41.69#ibcon#read 3, iclass 39, count 2 2006.173.09:55:41.69#ibcon#about to read 4, iclass 39, count 2 2006.173.09:55:41.69#ibcon#read 4, iclass 39, count 2 2006.173.09:55:41.69#ibcon#about to read 5, iclass 39, count 2 2006.173.09:55:41.69#ibcon#read 5, iclass 39, count 2 2006.173.09:55:41.69#ibcon#about to read 6, iclass 39, count 2 2006.173.09:55:41.69#ibcon#read 6, iclass 39, count 2 2006.173.09:55:41.69#ibcon#end of sib2, iclass 39, count 2 2006.173.09:55:41.69#ibcon#*mode == 0, iclass 39, count 2 2006.173.09:55:41.69#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.09:55:41.69#ibcon#[25=AT05-04\r\n] 2006.173.09:55:41.69#ibcon#*before write, iclass 39, count 2 2006.173.09:55:41.69#ibcon#enter sib2, iclass 39, count 2 2006.173.09:55:41.69#ibcon#flushed, iclass 39, count 2 2006.173.09:55:41.69#ibcon#about to write, iclass 39, count 2 2006.173.09:55:41.69#ibcon#wrote, iclass 39, count 2 2006.173.09:55:41.69#ibcon#about to read 3, iclass 39, count 2 2006.173.09:55:41.72#ibcon#read 3, iclass 39, count 2 2006.173.09:55:41.72#ibcon#about to read 4, iclass 39, count 2 2006.173.09:55:41.72#ibcon#read 4, iclass 39, count 2 2006.173.09:55:41.72#ibcon#about to read 5, iclass 39, count 2 2006.173.09:55:41.72#ibcon#read 5, iclass 39, count 2 2006.173.09:55:41.72#ibcon#about to read 6, iclass 39, count 2 2006.173.09:55:41.72#ibcon#read 6, iclass 39, count 2 2006.173.09:55:41.72#ibcon#end of sib2, iclass 39, count 2 2006.173.09:55:41.72#ibcon#*after write, iclass 39, count 2 2006.173.09:55:41.72#ibcon#*before return 0, iclass 39, count 2 2006.173.09:55:41.72#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.09:55:41.72#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.09:55:41.72#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.09:55:41.72#ibcon#ireg 7 cls_cnt 0 2006.173.09:55:41.72#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.09:55:41.84#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.09:55:41.84#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.09:55:41.84#ibcon#enter wrdev, iclass 39, count 0 2006.173.09:55:41.84#ibcon#first serial, iclass 39, count 0 2006.173.09:55:41.84#ibcon#enter sib2, iclass 39, count 0 2006.173.09:55:41.84#ibcon#flushed, iclass 39, count 0 2006.173.09:55:41.84#ibcon#about to write, iclass 39, count 0 2006.173.09:55:41.84#ibcon#wrote, iclass 39, count 0 2006.173.09:55:41.84#ibcon#about to read 3, iclass 39, count 0 2006.173.09:55:41.86#ibcon#read 3, iclass 39, count 0 2006.173.09:55:41.86#ibcon#about to read 4, iclass 39, count 0 2006.173.09:55:41.86#ibcon#read 4, iclass 39, count 0 2006.173.09:55:41.86#ibcon#about to read 5, iclass 39, count 0 2006.173.09:55:41.86#ibcon#read 5, iclass 39, count 0 2006.173.09:55:41.86#ibcon#about to read 6, iclass 39, count 0 2006.173.09:55:41.86#ibcon#read 6, iclass 39, count 0 2006.173.09:55:41.86#ibcon#end of sib2, iclass 39, count 0 2006.173.09:55:41.86#ibcon#*mode == 0, iclass 39, count 0 2006.173.09:55:41.86#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.09:55:41.86#ibcon#[25=USB\r\n] 2006.173.09:55:41.86#ibcon#*before write, iclass 39, count 0 2006.173.09:55:41.86#ibcon#enter sib2, iclass 39, count 0 2006.173.09:55:41.86#ibcon#flushed, iclass 39, count 0 2006.173.09:55:41.86#ibcon#about to write, iclass 39, count 0 2006.173.09:55:41.86#ibcon#wrote, iclass 39, count 0 2006.173.09:55:41.86#ibcon#about to read 3, iclass 39, count 0 2006.173.09:55:41.89#ibcon#read 3, iclass 39, count 0 2006.173.09:55:41.89#ibcon#about to read 4, iclass 39, count 0 2006.173.09:55:41.89#ibcon#read 4, iclass 39, count 0 2006.173.09:55:41.89#ibcon#about to read 5, iclass 39, count 0 2006.173.09:55:41.89#ibcon#read 5, iclass 39, count 0 2006.173.09:55:41.89#ibcon#about to read 6, iclass 39, count 0 2006.173.09:55:41.89#ibcon#read 6, iclass 39, count 0 2006.173.09:55:41.89#ibcon#end of sib2, iclass 39, count 0 2006.173.09:55:41.89#ibcon#*after write, iclass 39, count 0 2006.173.09:55:41.89#ibcon#*before return 0, iclass 39, count 0 2006.173.09:55:41.89#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.09:55:41.89#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.09:55:41.89#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.09:55:41.89#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.09:55:41.89$vck44/valo=6,814.99 2006.173.09:55:41.89#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.09:55:41.89#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.09:55:41.89#ibcon#ireg 17 cls_cnt 0 2006.173.09:55:41.89#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.09:55:41.89#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.09:55:41.89#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.09:55:41.89#ibcon#enter wrdev, iclass 3, count 0 2006.173.09:55:41.89#ibcon#first serial, iclass 3, count 0 2006.173.09:55:41.89#ibcon#enter sib2, iclass 3, count 0 2006.173.09:55:41.89#ibcon#flushed, iclass 3, count 0 2006.173.09:55:41.89#ibcon#about to write, iclass 3, count 0 2006.173.09:55:41.89#ibcon#wrote, iclass 3, count 0 2006.173.09:55:41.89#ibcon#about to read 3, iclass 3, count 0 2006.173.09:55:41.91#ibcon#read 3, iclass 3, count 0 2006.173.09:55:41.91#ibcon#about to read 4, iclass 3, count 0 2006.173.09:55:41.91#ibcon#read 4, iclass 3, count 0 2006.173.09:55:41.91#ibcon#about to read 5, iclass 3, count 0 2006.173.09:55:41.91#ibcon#read 5, iclass 3, count 0 2006.173.09:55:41.91#ibcon#about to read 6, iclass 3, count 0 2006.173.09:55:41.91#ibcon#read 6, iclass 3, count 0 2006.173.09:55:41.91#ibcon#end of sib2, iclass 3, count 0 2006.173.09:55:41.91#ibcon#*mode == 0, iclass 3, count 0 2006.173.09:55:41.91#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.09:55:41.91#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.09:55:41.91#ibcon#*before write, iclass 3, count 0 2006.173.09:55:41.91#ibcon#enter sib2, iclass 3, count 0 2006.173.09:55:41.91#ibcon#flushed, iclass 3, count 0 2006.173.09:55:41.91#ibcon#about to write, iclass 3, count 0 2006.173.09:55:41.91#ibcon#wrote, iclass 3, count 0 2006.173.09:55:41.91#ibcon#about to read 3, iclass 3, count 0 2006.173.09:55:41.95#ibcon#read 3, iclass 3, count 0 2006.173.09:55:41.95#ibcon#about to read 4, iclass 3, count 0 2006.173.09:55:41.95#ibcon#read 4, iclass 3, count 0 2006.173.09:55:41.95#ibcon#about to read 5, iclass 3, count 0 2006.173.09:55:41.95#ibcon#read 5, iclass 3, count 0 2006.173.09:55:41.95#ibcon#about to read 6, iclass 3, count 0 2006.173.09:55:41.95#ibcon#read 6, iclass 3, count 0 2006.173.09:55:41.95#ibcon#end of sib2, iclass 3, count 0 2006.173.09:55:41.95#ibcon#*after write, iclass 3, count 0 2006.173.09:55:41.95#ibcon#*before return 0, iclass 3, count 0 2006.173.09:55:41.95#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.09:55:41.95#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.09:55:41.95#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.09:55:41.95#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.09:55:41.95$vck44/va=6,3 2006.173.09:55:41.95#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.09:55:41.95#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.09:55:41.95#ibcon#ireg 11 cls_cnt 2 2006.173.09:55:41.95#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.09:55:42.01#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.09:55:42.01#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.09:55:42.01#ibcon#enter wrdev, iclass 5, count 2 2006.173.09:55:42.01#ibcon#first serial, iclass 5, count 2 2006.173.09:55:42.01#ibcon#enter sib2, iclass 5, count 2 2006.173.09:55:42.01#ibcon#flushed, iclass 5, count 2 2006.173.09:55:42.01#ibcon#about to write, iclass 5, count 2 2006.173.09:55:42.01#ibcon#wrote, iclass 5, count 2 2006.173.09:55:42.01#ibcon#about to read 3, iclass 5, count 2 2006.173.09:55:42.03#ibcon#read 3, iclass 5, count 2 2006.173.09:55:42.03#ibcon#about to read 4, iclass 5, count 2 2006.173.09:55:42.03#ibcon#read 4, iclass 5, count 2 2006.173.09:55:42.03#ibcon#about to read 5, iclass 5, count 2 2006.173.09:55:42.03#ibcon#read 5, iclass 5, count 2 2006.173.09:55:42.03#ibcon#about to read 6, iclass 5, count 2 2006.173.09:55:42.03#ibcon#read 6, iclass 5, count 2 2006.173.09:55:42.03#ibcon#end of sib2, iclass 5, count 2 2006.173.09:55:42.03#ibcon#*mode == 0, iclass 5, count 2 2006.173.09:55:42.03#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.09:55:42.03#ibcon#[25=AT06-03\r\n] 2006.173.09:55:42.03#ibcon#*before write, iclass 5, count 2 2006.173.09:55:42.03#ibcon#enter sib2, iclass 5, count 2 2006.173.09:55:42.03#ibcon#flushed, iclass 5, count 2 2006.173.09:55:42.03#ibcon#about to write, iclass 5, count 2 2006.173.09:55:42.03#ibcon#wrote, iclass 5, count 2 2006.173.09:55:42.03#ibcon#about to read 3, iclass 5, count 2 2006.173.09:55:42.06#ibcon#read 3, iclass 5, count 2 2006.173.09:55:42.06#ibcon#about to read 4, iclass 5, count 2 2006.173.09:55:42.06#ibcon#read 4, iclass 5, count 2 2006.173.09:55:42.06#ibcon#about to read 5, iclass 5, count 2 2006.173.09:55:42.06#ibcon#read 5, iclass 5, count 2 2006.173.09:55:42.06#ibcon#about to read 6, iclass 5, count 2 2006.173.09:55:42.06#ibcon#read 6, iclass 5, count 2 2006.173.09:55:42.06#ibcon#end of sib2, iclass 5, count 2 2006.173.09:55:42.06#ibcon#*after write, iclass 5, count 2 2006.173.09:55:42.06#ibcon#*before return 0, iclass 5, count 2 2006.173.09:55:42.06#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.09:55:42.06#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.09:55:42.06#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.09:55:42.06#ibcon#ireg 7 cls_cnt 0 2006.173.09:55:42.06#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.09:55:42.18#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.09:55:42.18#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.09:55:42.18#ibcon#enter wrdev, iclass 5, count 0 2006.173.09:55:42.18#ibcon#first serial, iclass 5, count 0 2006.173.09:55:42.18#ibcon#enter sib2, iclass 5, count 0 2006.173.09:55:42.18#ibcon#flushed, iclass 5, count 0 2006.173.09:55:42.18#ibcon#about to write, iclass 5, count 0 2006.173.09:55:42.18#ibcon#wrote, iclass 5, count 0 2006.173.09:55:42.18#ibcon#about to read 3, iclass 5, count 0 2006.173.09:55:42.20#ibcon#read 3, iclass 5, count 0 2006.173.09:55:42.20#ibcon#about to read 4, iclass 5, count 0 2006.173.09:55:42.20#ibcon#read 4, iclass 5, count 0 2006.173.09:55:42.20#ibcon#about to read 5, iclass 5, count 0 2006.173.09:55:42.20#ibcon#read 5, iclass 5, count 0 2006.173.09:55:42.20#ibcon#about to read 6, iclass 5, count 0 2006.173.09:55:42.20#ibcon#read 6, iclass 5, count 0 2006.173.09:55:42.20#ibcon#end of sib2, iclass 5, count 0 2006.173.09:55:42.20#ibcon#*mode == 0, iclass 5, count 0 2006.173.09:55:42.20#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.09:55:42.20#ibcon#[25=USB\r\n] 2006.173.09:55:42.20#ibcon#*before write, iclass 5, count 0 2006.173.09:55:42.20#ibcon#enter sib2, iclass 5, count 0 2006.173.09:55:42.20#ibcon#flushed, iclass 5, count 0 2006.173.09:55:42.20#ibcon#about to write, iclass 5, count 0 2006.173.09:55:42.20#ibcon#wrote, iclass 5, count 0 2006.173.09:55:42.20#ibcon#about to read 3, iclass 5, count 0 2006.173.09:55:42.23#ibcon#read 3, iclass 5, count 0 2006.173.09:55:42.23#ibcon#about to read 4, iclass 5, count 0 2006.173.09:55:42.23#ibcon#read 4, iclass 5, count 0 2006.173.09:55:42.23#ibcon#about to read 5, iclass 5, count 0 2006.173.09:55:42.23#ibcon#read 5, iclass 5, count 0 2006.173.09:55:42.23#ibcon#about to read 6, iclass 5, count 0 2006.173.09:55:42.23#ibcon#read 6, iclass 5, count 0 2006.173.09:55:42.23#ibcon#end of sib2, iclass 5, count 0 2006.173.09:55:42.23#ibcon#*after write, iclass 5, count 0 2006.173.09:55:42.23#ibcon#*before return 0, iclass 5, count 0 2006.173.09:55:42.23#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.09:55:42.23#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.09:55:42.23#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.09:55:42.23#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.09:55:42.23$vck44/valo=7,864.99 2006.173.09:55:42.23#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.09:55:42.23#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.09:55:42.23#ibcon#ireg 17 cls_cnt 0 2006.173.09:55:42.23#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.09:55:42.23#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.09:55:42.23#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.09:55:42.23#ibcon#enter wrdev, iclass 7, count 0 2006.173.09:55:42.23#ibcon#first serial, iclass 7, count 0 2006.173.09:55:42.23#ibcon#enter sib2, iclass 7, count 0 2006.173.09:55:42.23#ibcon#flushed, iclass 7, count 0 2006.173.09:55:42.23#ibcon#about to write, iclass 7, count 0 2006.173.09:55:42.23#ibcon#wrote, iclass 7, count 0 2006.173.09:55:42.23#ibcon#about to read 3, iclass 7, count 0 2006.173.09:55:42.25#ibcon#read 3, iclass 7, count 0 2006.173.09:55:42.25#ibcon#about to read 4, iclass 7, count 0 2006.173.09:55:42.25#ibcon#read 4, iclass 7, count 0 2006.173.09:55:42.25#ibcon#about to read 5, iclass 7, count 0 2006.173.09:55:42.25#ibcon#read 5, iclass 7, count 0 2006.173.09:55:42.25#ibcon#about to read 6, iclass 7, count 0 2006.173.09:55:42.25#ibcon#read 6, iclass 7, count 0 2006.173.09:55:42.25#ibcon#end of sib2, iclass 7, count 0 2006.173.09:55:42.25#ibcon#*mode == 0, iclass 7, count 0 2006.173.09:55:42.25#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.09:55:42.25#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.09:55:42.25#ibcon#*before write, iclass 7, count 0 2006.173.09:55:42.25#ibcon#enter sib2, iclass 7, count 0 2006.173.09:55:42.25#ibcon#flushed, iclass 7, count 0 2006.173.09:55:42.25#ibcon#about to write, iclass 7, count 0 2006.173.09:55:42.25#ibcon#wrote, iclass 7, count 0 2006.173.09:55:42.25#ibcon#about to read 3, iclass 7, count 0 2006.173.09:55:42.29#ibcon#read 3, iclass 7, count 0 2006.173.09:55:42.29#ibcon#about to read 4, iclass 7, count 0 2006.173.09:55:42.29#ibcon#read 4, iclass 7, count 0 2006.173.09:55:42.29#ibcon#about to read 5, iclass 7, count 0 2006.173.09:55:42.29#ibcon#read 5, iclass 7, count 0 2006.173.09:55:42.29#ibcon#about to read 6, iclass 7, count 0 2006.173.09:55:42.29#ibcon#read 6, iclass 7, count 0 2006.173.09:55:42.29#ibcon#end of sib2, iclass 7, count 0 2006.173.09:55:42.29#ibcon#*after write, iclass 7, count 0 2006.173.09:55:42.29#ibcon#*before return 0, iclass 7, count 0 2006.173.09:55:42.29#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.09:55:42.29#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.09:55:42.29#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.09:55:42.29#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.09:55:42.29$vck44/va=7,4 2006.173.09:55:42.29#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.09:55:42.29#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.09:55:42.29#ibcon#ireg 11 cls_cnt 2 2006.173.09:55:42.29#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.09:55:42.35#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.09:55:42.35#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.09:55:42.35#ibcon#enter wrdev, iclass 11, count 2 2006.173.09:55:42.35#ibcon#first serial, iclass 11, count 2 2006.173.09:55:42.35#ibcon#enter sib2, iclass 11, count 2 2006.173.09:55:42.35#ibcon#flushed, iclass 11, count 2 2006.173.09:55:42.35#ibcon#about to write, iclass 11, count 2 2006.173.09:55:42.35#ibcon#wrote, iclass 11, count 2 2006.173.09:55:42.35#ibcon#about to read 3, iclass 11, count 2 2006.173.09:55:42.37#ibcon#read 3, iclass 11, count 2 2006.173.09:55:42.37#ibcon#about to read 4, iclass 11, count 2 2006.173.09:55:42.37#ibcon#read 4, iclass 11, count 2 2006.173.09:55:42.37#ibcon#about to read 5, iclass 11, count 2 2006.173.09:55:42.37#ibcon#read 5, iclass 11, count 2 2006.173.09:55:42.37#ibcon#about to read 6, iclass 11, count 2 2006.173.09:55:42.37#ibcon#read 6, iclass 11, count 2 2006.173.09:55:42.37#ibcon#end of sib2, iclass 11, count 2 2006.173.09:55:42.37#ibcon#*mode == 0, iclass 11, count 2 2006.173.09:55:42.37#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.09:55:42.37#ibcon#[25=AT07-04\r\n] 2006.173.09:55:42.37#ibcon#*before write, iclass 11, count 2 2006.173.09:55:42.37#ibcon#enter sib2, iclass 11, count 2 2006.173.09:55:42.37#ibcon#flushed, iclass 11, count 2 2006.173.09:55:42.37#ibcon#about to write, iclass 11, count 2 2006.173.09:55:42.37#ibcon#wrote, iclass 11, count 2 2006.173.09:55:42.37#ibcon#about to read 3, iclass 11, count 2 2006.173.09:55:42.40#ibcon#read 3, iclass 11, count 2 2006.173.09:55:42.40#ibcon#about to read 4, iclass 11, count 2 2006.173.09:55:42.40#ibcon#read 4, iclass 11, count 2 2006.173.09:55:42.40#ibcon#about to read 5, iclass 11, count 2 2006.173.09:55:42.40#ibcon#read 5, iclass 11, count 2 2006.173.09:55:42.40#ibcon#about to read 6, iclass 11, count 2 2006.173.09:55:42.40#ibcon#read 6, iclass 11, count 2 2006.173.09:55:42.40#ibcon#end of sib2, iclass 11, count 2 2006.173.09:55:42.40#ibcon#*after write, iclass 11, count 2 2006.173.09:55:42.40#ibcon#*before return 0, iclass 11, count 2 2006.173.09:55:42.40#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.09:55:42.40#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.09:55:42.40#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.09:55:42.40#ibcon#ireg 7 cls_cnt 0 2006.173.09:55:42.40#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.09:55:42.52#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.09:55:42.52#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.09:55:42.52#ibcon#enter wrdev, iclass 11, count 0 2006.173.09:55:42.52#ibcon#first serial, iclass 11, count 0 2006.173.09:55:42.52#ibcon#enter sib2, iclass 11, count 0 2006.173.09:55:42.52#ibcon#flushed, iclass 11, count 0 2006.173.09:55:42.52#ibcon#about to write, iclass 11, count 0 2006.173.09:55:42.52#ibcon#wrote, iclass 11, count 0 2006.173.09:55:42.52#ibcon#about to read 3, iclass 11, count 0 2006.173.09:55:42.54#ibcon#read 3, iclass 11, count 0 2006.173.09:55:42.54#ibcon#about to read 4, iclass 11, count 0 2006.173.09:55:42.54#ibcon#read 4, iclass 11, count 0 2006.173.09:55:42.54#ibcon#about to read 5, iclass 11, count 0 2006.173.09:55:42.54#ibcon#read 5, iclass 11, count 0 2006.173.09:55:42.54#ibcon#about to read 6, iclass 11, count 0 2006.173.09:55:42.54#ibcon#read 6, iclass 11, count 0 2006.173.09:55:42.54#ibcon#end of sib2, iclass 11, count 0 2006.173.09:55:42.54#ibcon#*mode == 0, iclass 11, count 0 2006.173.09:55:42.54#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.09:55:42.54#ibcon#[25=USB\r\n] 2006.173.09:55:42.54#ibcon#*before write, iclass 11, count 0 2006.173.09:55:42.54#ibcon#enter sib2, iclass 11, count 0 2006.173.09:55:42.54#ibcon#flushed, iclass 11, count 0 2006.173.09:55:42.54#ibcon#about to write, iclass 11, count 0 2006.173.09:55:42.54#ibcon#wrote, iclass 11, count 0 2006.173.09:55:42.54#ibcon#about to read 3, iclass 11, count 0 2006.173.09:55:42.57#ibcon#read 3, iclass 11, count 0 2006.173.09:55:42.57#ibcon#about to read 4, iclass 11, count 0 2006.173.09:55:42.57#ibcon#read 4, iclass 11, count 0 2006.173.09:55:42.57#ibcon#about to read 5, iclass 11, count 0 2006.173.09:55:42.57#ibcon#read 5, iclass 11, count 0 2006.173.09:55:42.57#ibcon#about to read 6, iclass 11, count 0 2006.173.09:55:42.57#ibcon#read 6, iclass 11, count 0 2006.173.09:55:42.57#ibcon#end of sib2, iclass 11, count 0 2006.173.09:55:42.57#ibcon#*after write, iclass 11, count 0 2006.173.09:55:42.57#ibcon#*before return 0, iclass 11, count 0 2006.173.09:55:42.57#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.09:55:42.57#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.09:55:42.57#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.09:55:42.57#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.09:55:42.57$vck44/valo=8,884.99 2006.173.09:55:42.57#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.09:55:42.57#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.09:55:42.57#ibcon#ireg 17 cls_cnt 0 2006.173.09:55:42.57#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.09:55:42.57#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.09:55:42.57#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.09:55:42.57#ibcon#enter wrdev, iclass 13, count 0 2006.173.09:55:42.57#ibcon#first serial, iclass 13, count 0 2006.173.09:55:42.57#ibcon#enter sib2, iclass 13, count 0 2006.173.09:55:42.57#ibcon#flushed, iclass 13, count 0 2006.173.09:55:42.57#ibcon#about to write, iclass 13, count 0 2006.173.09:55:42.57#ibcon#wrote, iclass 13, count 0 2006.173.09:55:42.57#ibcon#about to read 3, iclass 13, count 0 2006.173.09:55:42.59#ibcon#read 3, iclass 13, count 0 2006.173.09:55:42.59#ibcon#about to read 4, iclass 13, count 0 2006.173.09:55:42.59#ibcon#read 4, iclass 13, count 0 2006.173.09:55:42.59#ibcon#about to read 5, iclass 13, count 0 2006.173.09:55:42.59#ibcon#read 5, iclass 13, count 0 2006.173.09:55:42.59#ibcon#about to read 6, iclass 13, count 0 2006.173.09:55:42.59#ibcon#read 6, iclass 13, count 0 2006.173.09:55:42.59#ibcon#end of sib2, iclass 13, count 0 2006.173.09:55:42.59#ibcon#*mode == 0, iclass 13, count 0 2006.173.09:55:42.59#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.09:55:42.59#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.09:55:42.59#ibcon#*before write, iclass 13, count 0 2006.173.09:55:42.59#ibcon#enter sib2, iclass 13, count 0 2006.173.09:55:42.59#ibcon#flushed, iclass 13, count 0 2006.173.09:55:42.59#ibcon#about to write, iclass 13, count 0 2006.173.09:55:42.59#ibcon#wrote, iclass 13, count 0 2006.173.09:55:42.59#ibcon#about to read 3, iclass 13, count 0 2006.173.09:55:42.63#ibcon#read 3, iclass 13, count 0 2006.173.09:55:42.63#ibcon#about to read 4, iclass 13, count 0 2006.173.09:55:42.63#ibcon#read 4, iclass 13, count 0 2006.173.09:55:42.63#ibcon#about to read 5, iclass 13, count 0 2006.173.09:55:42.63#ibcon#read 5, iclass 13, count 0 2006.173.09:55:42.63#ibcon#about to read 6, iclass 13, count 0 2006.173.09:55:42.63#ibcon#read 6, iclass 13, count 0 2006.173.09:55:42.63#ibcon#end of sib2, iclass 13, count 0 2006.173.09:55:42.63#ibcon#*after write, iclass 13, count 0 2006.173.09:55:42.63#ibcon#*before return 0, iclass 13, count 0 2006.173.09:55:42.63#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.09:55:42.63#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.09:55:42.63#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.09:55:42.63#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.09:55:42.63$vck44/va=8,4 2006.173.09:55:42.63#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.09:55:42.63#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.09:55:42.63#ibcon#ireg 11 cls_cnt 2 2006.173.09:55:42.63#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.09:55:42.69#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.09:55:42.69#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.09:55:42.69#ibcon#enter wrdev, iclass 15, count 2 2006.173.09:55:42.69#ibcon#first serial, iclass 15, count 2 2006.173.09:55:42.69#ibcon#enter sib2, iclass 15, count 2 2006.173.09:55:42.69#ibcon#flushed, iclass 15, count 2 2006.173.09:55:42.69#ibcon#about to write, iclass 15, count 2 2006.173.09:55:42.69#ibcon#wrote, iclass 15, count 2 2006.173.09:55:42.69#ibcon#about to read 3, iclass 15, count 2 2006.173.09:55:42.71#ibcon#read 3, iclass 15, count 2 2006.173.09:55:42.71#ibcon#about to read 4, iclass 15, count 2 2006.173.09:55:42.71#ibcon#read 4, iclass 15, count 2 2006.173.09:55:42.71#ibcon#about to read 5, iclass 15, count 2 2006.173.09:55:42.71#ibcon#read 5, iclass 15, count 2 2006.173.09:55:42.71#ibcon#about to read 6, iclass 15, count 2 2006.173.09:55:42.71#ibcon#read 6, iclass 15, count 2 2006.173.09:55:42.71#ibcon#end of sib2, iclass 15, count 2 2006.173.09:55:42.71#ibcon#*mode == 0, iclass 15, count 2 2006.173.09:55:42.71#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.09:55:42.71#ibcon#[25=AT08-04\r\n] 2006.173.09:55:42.71#ibcon#*before write, iclass 15, count 2 2006.173.09:55:42.71#ibcon#enter sib2, iclass 15, count 2 2006.173.09:55:42.71#ibcon#flushed, iclass 15, count 2 2006.173.09:55:42.71#ibcon#about to write, iclass 15, count 2 2006.173.09:55:42.71#ibcon#wrote, iclass 15, count 2 2006.173.09:55:42.71#ibcon#about to read 3, iclass 15, count 2 2006.173.09:55:42.74#ibcon#read 3, iclass 15, count 2 2006.173.09:55:42.74#ibcon#about to read 4, iclass 15, count 2 2006.173.09:55:42.74#ibcon#read 4, iclass 15, count 2 2006.173.09:55:42.74#ibcon#about to read 5, iclass 15, count 2 2006.173.09:55:42.74#ibcon#read 5, iclass 15, count 2 2006.173.09:55:42.74#ibcon#about to read 6, iclass 15, count 2 2006.173.09:55:42.74#ibcon#read 6, iclass 15, count 2 2006.173.09:55:42.74#ibcon#end of sib2, iclass 15, count 2 2006.173.09:55:42.74#ibcon#*after write, iclass 15, count 2 2006.173.09:55:42.74#ibcon#*before return 0, iclass 15, count 2 2006.173.09:55:42.74#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.09:55:42.74#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.09:55:42.74#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.09:55:42.74#ibcon#ireg 7 cls_cnt 0 2006.173.09:55:42.74#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.09:55:42.86#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.09:55:42.86#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.09:55:42.86#ibcon#enter wrdev, iclass 15, count 0 2006.173.09:55:42.86#ibcon#first serial, iclass 15, count 0 2006.173.09:55:42.86#ibcon#enter sib2, iclass 15, count 0 2006.173.09:55:42.86#ibcon#flushed, iclass 15, count 0 2006.173.09:55:42.86#ibcon#about to write, iclass 15, count 0 2006.173.09:55:42.86#ibcon#wrote, iclass 15, count 0 2006.173.09:55:42.86#ibcon#about to read 3, iclass 15, count 0 2006.173.09:55:42.88#ibcon#read 3, iclass 15, count 0 2006.173.09:55:42.88#ibcon#about to read 4, iclass 15, count 0 2006.173.09:55:42.88#ibcon#read 4, iclass 15, count 0 2006.173.09:55:42.88#ibcon#about to read 5, iclass 15, count 0 2006.173.09:55:42.88#ibcon#read 5, iclass 15, count 0 2006.173.09:55:42.88#ibcon#about to read 6, iclass 15, count 0 2006.173.09:55:42.88#ibcon#read 6, iclass 15, count 0 2006.173.09:55:42.88#ibcon#end of sib2, iclass 15, count 0 2006.173.09:55:42.88#ibcon#*mode == 0, iclass 15, count 0 2006.173.09:55:42.88#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.09:55:42.88#ibcon#[25=USB\r\n] 2006.173.09:55:42.88#ibcon#*before write, iclass 15, count 0 2006.173.09:55:42.88#ibcon#enter sib2, iclass 15, count 0 2006.173.09:55:42.88#ibcon#flushed, iclass 15, count 0 2006.173.09:55:42.88#ibcon#about to write, iclass 15, count 0 2006.173.09:55:42.88#ibcon#wrote, iclass 15, count 0 2006.173.09:55:42.88#ibcon#about to read 3, iclass 15, count 0 2006.173.09:55:42.91#ibcon#read 3, iclass 15, count 0 2006.173.09:55:42.91#ibcon#about to read 4, iclass 15, count 0 2006.173.09:55:42.91#ibcon#read 4, iclass 15, count 0 2006.173.09:55:42.91#ibcon#about to read 5, iclass 15, count 0 2006.173.09:55:42.91#ibcon#read 5, iclass 15, count 0 2006.173.09:55:42.91#ibcon#about to read 6, iclass 15, count 0 2006.173.09:55:42.91#ibcon#read 6, iclass 15, count 0 2006.173.09:55:42.91#ibcon#end of sib2, iclass 15, count 0 2006.173.09:55:42.91#ibcon#*after write, iclass 15, count 0 2006.173.09:55:42.91#ibcon#*before return 0, iclass 15, count 0 2006.173.09:55:42.91#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.09:55:42.91#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.09:55:42.91#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.09:55:42.91#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.09:55:42.91$vck44/vblo=1,629.99 2006.173.09:55:42.91#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.09:55:42.91#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.09:55:42.91#ibcon#ireg 17 cls_cnt 0 2006.173.09:55:42.91#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.09:55:42.91#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.09:55:42.91#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.09:55:42.91#ibcon#enter wrdev, iclass 17, count 0 2006.173.09:55:42.91#ibcon#first serial, iclass 17, count 0 2006.173.09:55:42.91#ibcon#enter sib2, iclass 17, count 0 2006.173.09:55:42.91#ibcon#flushed, iclass 17, count 0 2006.173.09:55:42.91#ibcon#about to write, iclass 17, count 0 2006.173.09:55:42.91#ibcon#wrote, iclass 17, count 0 2006.173.09:55:42.91#ibcon#about to read 3, iclass 17, count 0 2006.173.09:55:42.93#ibcon#read 3, iclass 17, count 0 2006.173.09:55:42.93#ibcon#about to read 4, iclass 17, count 0 2006.173.09:55:42.93#ibcon#read 4, iclass 17, count 0 2006.173.09:55:42.93#ibcon#about to read 5, iclass 17, count 0 2006.173.09:55:42.93#ibcon#read 5, iclass 17, count 0 2006.173.09:55:42.93#ibcon#about to read 6, iclass 17, count 0 2006.173.09:55:42.93#ibcon#read 6, iclass 17, count 0 2006.173.09:55:42.93#ibcon#end of sib2, iclass 17, count 0 2006.173.09:55:42.93#ibcon#*mode == 0, iclass 17, count 0 2006.173.09:55:42.93#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.09:55:42.93#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.09:55:42.93#ibcon#*before write, iclass 17, count 0 2006.173.09:55:42.93#ibcon#enter sib2, iclass 17, count 0 2006.173.09:55:42.93#ibcon#flushed, iclass 17, count 0 2006.173.09:55:42.93#ibcon#about to write, iclass 17, count 0 2006.173.09:55:42.93#ibcon#wrote, iclass 17, count 0 2006.173.09:55:42.93#ibcon#about to read 3, iclass 17, count 0 2006.173.09:55:42.97#ibcon#read 3, iclass 17, count 0 2006.173.09:55:42.97#ibcon#about to read 4, iclass 17, count 0 2006.173.09:55:42.97#ibcon#read 4, iclass 17, count 0 2006.173.09:55:42.97#ibcon#about to read 5, iclass 17, count 0 2006.173.09:55:42.97#ibcon#read 5, iclass 17, count 0 2006.173.09:55:42.97#ibcon#about to read 6, iclass 17, count 0 2006.173.09:55:42.97#ibcon#read 6, iclass 17, count 0 2006.173.09:55:42.97#ibcon#end of sib2, iclass 17, count 0 2006.173.09:55:42.97#ibcon#*after write, iclass 17, count 0 2006.173.09:55:42.97#ibcon#*before return 0, iclass 17, count 0 2006.173.09:55:42.97#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.09:55:42.97#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.09:55:42.97#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.09:55:42.97#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.09:55:42.97$vck44/vb=1,4 2006.173.09:55:42.97#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.09:55:42.97#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.09:55:42.97#ibcon#ireg 11 cls_cnt 2 2006.173.09:55:42.97#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.09:55:42.97#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.09:55:42.97#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.09:55:42.97#ibcon#enter wrdev, iclass 19, count 2 2006.173.09:55:42.97#ibcon#first serial, iclass 19, count 2 2006.173.09:55:42.97#ibcon#enter sib2, iclass 19, count 2 2006.173.09:55:42.97#ibcon#flushed, iclass 19, count 2 2006.173.09:55:42.97#ibcon#about to write, iclass 19, count 2 2006.173.09:55:42.97#ibcon#wrote, iclass 19, count 2 2006.173.09:55:42.97#ibcon#about to read 3, iclass 19, count 2 2006.173.09:55:42.99#ibcon#read 3, iclass 19, count 2 2006.173.09:55:42.99#ibcon#about to read 4, iclass 19, count 2 2006.173.09:55:42.99#ibcon#read 4, iclass 19, count 2 2006.173.09:55:42.99#ibcon#about to read 5, iclass 19, count 2 2006.173.09:55:42.99#ibcon#read 5, iclass 19, count 2 2006.173.09:55:42.99#ibcon#about to read 6, iclass 19, count 2 2006.173.09:55:42.99#ibcon#read 6, iclass 19, count 2 2006.173.09:55:42.99#ibcon#end of sib2, iclass 19, count 2 2006.173.09:55:42.99#ibcon#*mode == 0, iclass 19, count 2 2006.173.09:55:42.99#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.09:55:42.99#ibcon#[27=AT01-04\r\n] 2006.173.09:55:42.99#ibcon#*before write, iclass 19, count 2 2006.173.09:55:42.99#ibcon#enter sib2, iclass 19, count 2 2006.173.09:55:42.99#ibcon#flushed, iclass 19, count 2 2006.173.09:55:42.99#ibcon#about to write, iclass 19, count 2 2006.173.09:55:42.99#ibcon#wrote, iclass 19, count 2 2006.173.09:55:42.99#ibcon#about to read 3, iclass 19, count 2 2006.173.09:55:43.02#ibcon#read 3, iclass 19, count 2 2006.173.09:55:43.02#ibcon#about to read 4, iclass 19, count 2 2006.173.09:55:43.02#ibcon#read 4, iclass 19, count 2 2006.173.09:55:43.02#ibcon#about to read 5, iclass 19, count 2 2006.173.09:55:43.02#ibcon#read 5, iclass 19, count 2 2006.173.09:55:43.02#ibcon#about to read 6, iclass 19, count 2 2006.173.09:55:43.02#ibcon#read 6, iclass 19, count 2 2006.173.09:55:43.02#ibcon#end of sib2, iclass 19, count 2 2006.173.09:55:43.02#ibcon#*after write, iclass 19, count 2 2006.173.09:55:43.02#ibcon#*before return 0, iclass 19, count 2 2006.173.09:55:43.02#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.09:55:43.02#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.09:55:43.02#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.09:55:43.02#ibcon#ireg 7 cls_cnt 0 2006.173.09:55:43.02#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.09:55:43.14#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.09:55:43.14#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.09:55:43.14#ibcon#enter wrdev, iclass 19, count 0 2006.173.09:55:43.14#ibcon#first serial, iclass 19, count 0 2006.173.09:55:43.14#ibcon#enter sib2, iclass 19, count 0 2006.173.09:55:43.14#ibcon#flushed, iclass 19, count 0 2006.173.09:55:43.14#ibcon#about to write, iclass 19, count 0 2006.173.09:55:43.14#ibcon#wrote, iclass 19, count 0 2006.173.09:55:43.14#ibcon#about to read 3, iclass 19, count 0 2006.173.09:55:43.16#ibcon#read 3, iclass 19, count 0 2006.173.09:55:43.16#ibcon#about to read 4, iclass 19, count 0 2006.173.09:55:43.16#ibcon#read 4, iclass 19, count 0 2006.173.09:55:43.16#ibcon#about to read 5, iclass 19, count 0 2006.173.09:55:43.16#ibcon#read 5, iclass 19, count 0 2006.173.09:55:43.16#ibcon#about to read 6, iclass 19, count 0 2006.173.09:55:43.16#ibcon#read 6, iclass 19, count 0 2006.173.09:55:43.16#ibcon#end of sib2, iclass 19, count 0 2006.173.09:55:43.16#ibcon#*mode == 0, iclass 19, count 0 2006.173.09:55:43.16#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.09:55:43.16#ibcon#[27=USB\r\n] 2006.173.09:55:43.16#ibcon#*before write, iclass 19, count 0 2006.173.09:55:43.16#ibcon#enter sib2, iclass 19, count 0 2006.173.09:55:43.16#ibcon#flushed, iclass 19, count 0 2006.173.09:55:43.16#ibcon#about to write, iclass 19, count 0 2006.173.09:55:43.16#ibcon#wrote, iclass 19, count 0 2006.173.09:55:43.16#ibcon#about to read 3, iclass 19, count 0 2006.173.09:55:43.19#ibcon#read 3, iclass 19, count 0 2006.173.09:55:43.19#ibcon#about to read 4, iclass 19, count 0 2006.173.09:55:43.19#ibcon#read 4, iclass 19, count 0 2006.173.09:55:43.19#ibcon#about to read 5, iclass 19, count 0 2006.173.09:55:43.19#ibcon#read 5, iclass 19, count 0 2006.173.09:55:43.19#ibcon#about to read 6, iclass 19, count 0 2006.173.09:55:43.19#ibcon#read 6, iclass 19, count 0 2006.173.09:55:43.19#ibcon#end of sib2, iclass 19, count 0 2006.173.09:55:43.19#ibcon#*after write, iclass 19, count 0 2006.173.09:55:43.19#ibcon#*before return 0, iclass 19, count 0 2006.173.09:55:43.19#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.09:55:43.19#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.09:55:43.19#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.09:55:43.19#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.09:55:43.19$vck44/vblo=2,634.99 2006.173.09:55:43.19#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.09:55:43.19#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.09:55:43.19#ibcon#ireg 17 cls_cnt 0 2006.173.09:55:43.19#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.09:55:43.19#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.09:55:43.19#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.09:55:43.19#ibcon#enter wrdev, iclass 21, count 0 2006.173.09:55:43.19#ibcon#first serial, iclass 21, count 0 2006.173.09:55:43.19#ibcon#enter sib2, iclass 21, count 0 2006.173.09:55:43.19#ibcon#flushed, iclass 21, count 0 2006.173.09:55:43.19#ibcon#about to write, iclass 21, count 0 2006.173.09:55:43.19#ibcon#wrote, iclass 21, count 0 2006.173.09:55:43.19#ibcon#about to read 3, iclass 21, count 0 2006.173.09:55:43.21#ibcon#read 3, iclass 21, count 0 2006.173.09:55:43.21#ibcon#about to read 4, iclass 21, count 0 2006.173.09:55:43.21#ibcon#read 4, iclass 21, count 0 2006.173.09:55:43.21#ibcon#about to read 5, iclass 21, count 0 2006.173.09:55:43.21#ibcon#read 5, iclass 21, count 0 2006.173.09:55:43.21#ibcon#about to read 6, iclass 21, count 0 2006.173.09:55:43.21#ibcon#read 6, iclass 21, count 0 2006.173.09:55:43.21#ibcon#end of sib2, iclass 21, count 0 2006.173.09:55:43.21#ibcon#*mode == 0, iclass 21, count 0 2006.173.09:55:43.21#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.09:55:43.21#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.09:55:43.21#ibcon#*before write, iclass 21, count 0 2006.173.09:55:43.21#ibcon#enter sib2, iclass 21, count 0 2006.173.09:55:43.21#ibcon#flushed, iclass 21, count 0 2006.173.09:55:43.21#ibcon#about to write, iclass 21, count 0 2006.173.09:55:43.21#ibcon#wrote, iclass 21, count 0 2006.173.09:55:43.21#ibcon#about to read 3, iclass 21, count 0 2006.173.09:55:43.25#ibcon#read 3, iclass 21, count 0 2006.173.09:55:43.25#ibcon#about to read 4, iclass 21, count 0 2006.173.09:55:43.25#ibcon#read 4, iclass 21, count 0 2006.173.09:55:43.25#ibcon#about to read 5, iclass 21, count 0 2006.173.09:55:43.25#ibcon#read 5, iclass 21, count 0 2006.173.09:55:43.25#ibcon#about to read 6, iclass 21, count 0 2006.173.09:55:43.25#ibcon#read 6, iclass 21, count 0 2006.173.09:55:43.25#ibcon#end of sib2, iclass 21, count 0 2006.173.09:55:43.25#ibcon#*after write, iclass 21, count 0 2006.173.09:55:43.25#ibcon#*before return 0, iclass 21, count 0 2006.173.09:55:43.25#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.09:55:43.25#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.09:55:43.25#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.09:55:43.25#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.09:55:43.25$vck44/vb=2,4 2006.173.09:55:43.25#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.09:55:43.25#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.09:55:43.25#ibcon#ireg 11 cls_cnt 2 2006.173.09:55:43.25#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.09:55:43.31#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.09:55:43.31#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.09:55:43.31#ibcon#enter wrdev, iclass 23, count 2 2006.173.09:55:43.31#ibcon#first serial, iclass 23, count 2 2006.173.09:55:43.31#ibcon#enter sib2, iclass 23, count 2 2006.173.09:55:43.31#ibcon#flushed, iclass 23, count 2 2006.173.09:55:43.31#ibcon#about to write, iclass 23, count 2 2006.173.09:55:43.31#ibcon#wrote, iclass 23, count 2 2006.173.09:55:43.31#ibcon#about to read 3, iclass 23, count 2 2006.173.09:55:43.33#ibcon#read 3, iclass 23, count 2 2006.173.09:55:43.33#ibcon#about to read 4, iclass 23, count 2 2006.173.09:55:43.33#ibcon#read 4, iclass 23, count 2 2006.173.09:55:43.33#ibcon#about to read 5, iclass 23, count 2 2006.173.09:55:43.33#ibcon#read 5, iclass 23, count 2 2006.173.09:55:43.33#ibcon#about to read 6, iclass 23, count 2 2006.173.09:55:43.33#ibcon#read 6, iclass 23, count 2 2006.173.09:55:43.33#ibcon#end of sib2, iclass 23, count 2 2006.173.09:55:43.33#ibcon#*mode == 0, iclass 23, count 2 2006.173.09:55:43.33#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.09:55:43.33#ibcon#[27=AT02-04\r\n] 2006.173.09:55:43.33#ibcon#*before write, iclass 23, count 2 2006.173.09:55:43.33#ibcon#enter sib2, iclass 23, count 2 2006.173.09:55:43.33#ibcon#flushed, iclass 23, count 2 2006.173.09:55:43.33#ibcon#about to write, iclass 23, count 2 2006.173.09:55:43.33#ibcon#wrote, iclass 23, count 2 2006.173.09:55:43.33#ibcon#about to read 3, iclass 23, count 2 2006.173.09:55:43.36#ibcon#read 3, iclass 23, count 2 2006.173.09:55:43.36#ibcon#about to read 4, iclass 23, count 2 2006.173.09:55:43.36#ibcon#read 4, iclass 23, count 2 2006.173.09:55:43.36#ibcon#about to read 5, iclass 23, count 2 2006.173.09:55:43.36#ibcon#read 5, iclass 23, count 2 2006.173.09:55:43.36#ibcon#about to read 6, iclass 23, count 2 2006.173.09:55:43.36#ibcon#read 6, iclass 23, count 2 2006.173.09:55:43.36#ibcon#end of sib2, iclass 23, count 2 2006.173.09:55:43.36#ibcon#*after write, iclass 23, count 2 2006.173.09:55:43.36#ibcon#*before return 0, iclass 23, count 2 2006.173.09:55:43.36#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.09:55:43.36#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.09:55:43.36#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.09:55:43.36#ibcon#ireg 7 cls_cnt 0 2006.173.09:55:43.36#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.09:55:43.48#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.09:55:43.48#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.09:55:43.48#ibcon#enter wrdev, iclass 23, count 0 2006.173.09:55:43.48#ibcon#first serial, iclass 23, count 0 2006.173.09:55:43.48#ibcon#enter sib2, iclass 23, count 0 2006.173.09:55:43.48#ibcon#flushed, iclass 23, count 0 2006.173.09:55:43.48#ibcon#about to write, iclass 23, count 0 2006.173.09:55:43.48#ibcon#wrote, iclass 23, count 0 2006.173.09:55:43.48#ibcon#about to read 3, iclass 23, count 0 2006.173.09:55:43.50#ibcon#read 3, iclass 23, count 0 2006.173.09:55:43.50#ibcon#about to read 4, iclass 23, count 0 2006.173.09:55:43.50#ibcon#read 4, iclass 23, count 0 2006.173.09:55:43.50#ibcon#about to read 5, iclass 23, count 0 2006.173.09:55:43.50#ibcon#read 5, iclass 23, count 0 2006.173.09:55:43.50#ibcon#about to read 6, iclass 23, count 0 2006.173.09:55:43.50#ibcon#read 6, iclass 23, count 0 2006.173.09:55:43.50#ibcon#end of sib2, iclass 23, count 0 2006.173.09:55:43.50#ibcon#*mode == 0, iclass 23, count 0 2006.173.09:55:43.50#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.09:55:43.50#ibcon#[27=USB\r\n] 2006.173.09:55:43.50#ibcon#*before write, iclass 23, count 0 2006.173.09:55:43.50#ibcon#enter sib2, iclass 23, count 0 2006.173.09:55:43.50#ibcon#flushed, iclass 23, count 0 2006.173.09:55:43.50#ibcon#about to write, iclass 23, count 0 2006.173.09:55:43.50#ibcon#wrote, iclass 23, count 0 2006.173.09:55:43.50#ibcon#about to read 3, iclass 23, count 0 2006.173.09:55:43.53#ibcon#read 3, iclass 23, count 0 2006.173.09:55:43.53#ibcon#about to read 4, iclass 23, count 0 2006.173.09:55:43.53#ibcon#read 4, iclass 23, count 0 2006.173.09:55:43.53#ibcon#about to read 5, iclass 23, count 0 2006.173.09:55:43.53#ibcon#read 5, iclass 23, count 0 2006.173.09:55:43.53#ibcon#about to read 6, iclass 23, count 0 2006.173.09:55:43.53#ibcon#read 6, iclass 23, count 0 2006.173.09:55:43.53#ibcon#end of sib2, iclass 23, count 0 2006.173.09:55:43.53#ibcon#*after write, iclass 23, count 0 2006.173.09:55:43.53#ibcon#*before return 0, iclass 23, count 0 2006.173.09:55:43.53#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.09:55:43.53#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.09:55:43.53#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.09:55:43.53#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.09:55:43.53$vck44/vblo=3,649.99 2006.173.09:55:43.53#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.09:55:43.53#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.09:55:43.53#ibcon#ireg 17 cls_cnt 0 2006.173.09:55:43.53#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.09:55:43.53#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.09:55:43.53#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.09:55:43.53#ibcon#enter wrdev, iclass 25, count 0 2006.173.09:55:43.53#ibcon#first serial, iclass 25, count 0 2006.173.09:55:43.53#ibcon#enter sib2, iclass 25, count 0 2006.173.09:55:43.53#ibcon#flushed, iclass 25, count 0 2006.173.09:55:43.53#ibcon#about to write, iclass 25, count 0 2006.173.09:55:43.53#ibcon#wrote, iclass 25, count 0 2006.173.09:55:43.53#ibcon#about to read 3, iclass 25, count 0 2006.173.09:55:43.55#ibcon#read 3, iclass 25, count 0 2006.173.09:55:43.55#ibcon#about to read 4, iclass 25, count 0 2006.173.09:55:43.55#ibcon#read 4, iclass 25, count 0 2006.173.09:55:43.55#ibcon#about to read 5, iclass 25, count 0 2006.173.09:55:43.55#ibcon#read 5, iclass 25, count 0 2006.173.09:55:43.55#ibcon#about to read 6, iclass 25, count 0 2006.173.09:55:43.55#ibcon#read 6, iclass 25, count 0 2006.173.09:55:43.55#ibcon#end of sib2, iclass 25, count 0 2006.173.09:55:43.55#ibcon#*mode == 0, iclass 25, count 0 2006.173.09:55:43.55#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.09:55:43.55#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.09:55:43.55#ibcon#*before write, iclass 25, count 0 2006.173.09:55:43.55#ibcon#enter sib2, iclass 25, count 0 2006.173.09:55:43.55#ibcon#flushed, iclass 25, count 0 2006.173.09:55:43.55#ibcon#about to write, iclass 25, count 0 2006.173.09:55:43.55#ibcon#wrote, iclass 25, count 0 2006.173.09:55:43.55#ibcon#about to read 3, iclass 25, count 0 2006.173.09:55:43.59#ibcon#read 3, iclass 25, count 0 2006.173.09:55:43.59#ibcon#about to read 4, iclass 25, count 0 2006.173.09:55:43.59#ibcon#read 4, iclass 25, count 0 2006.173.09:55:43.59#ibcon#about to read 5, iclass 25, count 0 2006.173.09:55:43.59#ibcon#read 5, iclass 25, count 0 2006.173.09:55:43.59#ibcon#about to read 6, iclass 25, count 0 2006.173.09:55:43.59#ibcon#read 6, iclass 25, count 0 2006.173.09:55:43.59#ibcon#end of sib2, iclass 25, count 0 2006.173.09:55:43.59#ibcon#*after write, iclass 25, count 0 2006.173.09:55:43.59#ibcon#*before return 0, iclass 25, count 0 2006.173.09:55:43.59#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.09:55:43.59#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.09:55:43.59#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.09:55:43.59#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.09:55:43.59$vck44/vb=3,4 2006.173.09:55:43.59#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.09:55:43.59#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.09:55:43.59#ibcon#ireg 11 cls_cnt 2 2006.173.09:55:43.59#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.09:55:43.65#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.09:55:43.65#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.09:55:43.65#ibcon#enter wrdev, iclass 27, count 2 2006.173.09:55:43.65#ibcon#first serial, iclass 27, count 2 2006.173.09:55:43.65#ibcon#enter sib2, iclass 27, count 2 2006.173.09:55:43.65#ibcon#flushed, iclass 27, count 2 2006.173.09:55:43.65#ibcon#about to write, iclass 27, count 2 2006.173.09:55:43.65#ibcon#wrote, iclass 27, count 2 2006.173.09:55:43.65#ibcon#about to read 3, iclass 27, count 2 2006.173.09:55:43.67#ibcon#read 3, iclass 27, count 2 2006.173.09:55:43.67#ibcon#about to read 4, iclass 27, count 2 2006.173.09:55:43.67#ibcon#read 4, iclass 27, count 2 2006.173.09:55:43.67#ibcon#about to read 5, iclass 27, count 2 2006.173.09:55:43.67#ibcon#read 5, iclass 27, count 2 2006.173.09:55:43.67#ibcon#about to read 6, iclass 27, count 2 2006.173.09:55:43.67#ibcon#read 6, iclass 27, count 2 2006.173.09:55:43.67#ibcon#end of sib2, iclass 27, count 2 2006.173.09:55:43.67#ibcon#*mode == 0, iclass 27, count 2 2006.173.09:55:43.67#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.09:55:43.67#ibcon#[27=AT03-04\r\n] 2006.173.09:55:43.67#ibcon#*before write, iclass 27, count 2 2006.173.09:55:43.67#ibcon#enter sib2, iclass 27, count 2 2006.173.09:55:43.67#ibcon#flushed, iclass 27, count 2 2006.173.09:55:43.67#ibcon#about to write, iclass 27, count 2 2006.173.09:55:43.67#ibcon#wrote, iclass 27, count 2 2006.173.09:55:43.67#ibcon#about to read 3, iclass 27, count 2 2006.173.09:55:43.70#ibcon#read 3, iclass 27, count 2 2006.173.09:55:43.70#ibcon#about to read 4, iclass 27, count 2 2006.173.09:55:43.70#ibcon#read 4, iclass 27, count 2 2006.173.09:55:43.70#ibcon#about to read 5, iclass 27, count 2 2006.173.09:55:43.70#ibcon#read 5, iclass 27, count 2 2006.173.09:55:43.70#ibcon#about to read 6, iclass 27, count 2 2006.173.09:55:43.70#ibcon#read 6, iclass 27, count 2 2006.173.09:55:43.70#ibcon#end of sib2, iclass 27, count 2 2006.173.09:55:43.70#ibcon#*after write, iclass 27, count 2 2006.173.09:55:43.70#ibcon#*before return 0, iclass 27, count 2 2006.173.09:55:43.70#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.09:55:43.70#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.09:55:43.70#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.09:55:43.70#ibcon#ireg 7 cls_cnt 0 2006.173.09:55:43.70#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.09:55:43.82#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.09:55:43.82#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.09:55:43.82#ibcon#enter wrdev, iclass 27, count 0 2006.173.09:55:43.82#ibcon#first serial, iclass 27, count 0 2006.173.09:55:43.82#ibcon#enter sib2, iclass 27, count 0 2006.173.09:55:43.82#ibcon#flushed, iclass 27, count 0 2006.173.09:55:43.82#ibcon#about to write, iclass 27, count 0 2006.173.09:55:43.82#ibcon#wrote, iclass 27, count 0 2006.173.09:55:43.82#ibcon#about to read 3, iclass 27, count 0 2006.173.09:55:43.84#ibcon#read 3, iclass 27, count 0 2006.173.09:55:43.84#ibcon#about to read 4, iclass 27, count 0 2006.173.09:55:43.84#ibcon#read 4, iclass 27, count 0 2006.173.09:55:43.84#ibcon#about to read 5, iclass 27, count 0 2006.173.09:55:43.84#ibcon#read 5, iclass 27, count 0 2006.173.09:55:43.84#ibcon#about to read 6, iclass 27, count 0 2006.173.09:55:43.84#ibcon#read 6, iclass 27, count 0 2006.173.09:55:43.84#ibcon#end of sib2, iclass 27, count 0 2006.173.09:55:43.84#ibcon#*mode == 0, iclass 27, count 0 2006.173.09:55:43.84#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.09:55:43.84#ibcon#[27=USB\r\n] 2006.173.09:55:43.84#ibcon#*before write, iclass 27, count 0 2006.173.09:55:43.84#ibcon#enter sib2, iclass 27, count 0 2006.173.09:55:43.84#ibcon#flushed, iclass 27, count 0 2006.173.09:55:43.84#ibcon#about to write, iclass 27, count 0 2006.173.09:55:43.84#ibcon#wrote, iclass 27, count 0 2006.173.09:55:43.84#ibcon#about to read 3, iclass 27, count 0 2006.173.09:55:43.87#ibcon#read 3, iclass 27, count 0 2006.173.09:55:43.87#ibcon#about to read 4, iclass 27, count 0 2006.173.09:55:43.87#ibcon#read 4, iclass 27, count 0 2006.173.09:55:43.87#ibcon#about to read 5, iclass 27, count 0 2006.173.09:55:43.87#ibcon#read 5, iclass 27, count 0 2006.173.09:55:43.87#ibcon#about to read 6, iclass 27, count 0 2006.173.09:55:43.87#ibcon#read 6, iclass 27, count 0 2006.173.09:55:43.87#ibcon#end of sib2, iclass 27, count 0 2006.173.09:55:43.87#ibcon#*after write, iclass 27, count 0 2006.173.09:55:43.87#ibcon#*before return 0, iclass 27, count 0 2006.173.09:55:43.87#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.09:55:43.87#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.09:55:43.87#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.09:55:43.87#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.09:55:43.87$vck44/vblo=4,679.99 2006.173.09:55:43.87#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.09:55:43.87#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.09:55:43.87#ibcon#ireg 17 cls_cnt 0 2006.173.09:55:43.87#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.09:55:43.87#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.09:55:43.87#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.09:55:43.87#ibcon#enter wrdev, iclass 29, count 0 2006.173.09:55:43.87#ibcon#first serial, iclass 29, count 0 2006.173.09:55:43.87#ibcon#enter sib2, iclass 29, count 0 2006.173.09:55:43.87#ibcon#flushed, iclass 29, count 0 2006.173.09:55:43.87#ibcon#about to write, iclass 29, count 0 2006.173.09:55:43.87#ibcon#wrote, iclass 29, count 0 2006.173.09:55:43.87#ibcon#about to read 3, iclass 29, count 0 2006.173.09:55:43.89#ibcon#read 3, iclass 29, count 0 2006.173.09:55:43.89#ibcon#about to read 4, iclass 29, count 0 2006.173.09:55:43.89#ibcon#read 4, iclass 29, count 0 2006.173.09:55:43.89#ibcon#about to read 5, iclass 29, count 0 2006.173.09:55:43.89#ibcon#read 5, iclass 29, count 0 2006.173.09:55:43.89#ibcon#about to read 6, iclass 29, count 0 2006.173.09:55:43.89#ibcon#read 6, iclass 29, count 0 2006.173.09:55:43.89#ibcon#end of sib2, iclass 29, count 0 2006.173.09:55:43.89#ibcon#*mode == 0, iclass 29, count 0 2006.173.09:55:43.89#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.09:55:43.89#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.09:55:43.89#ibcon#*before write, iclass 29, count 0 2006.173.09:55:43.89#ibcon#enter sib2, iclass 29, count 0 2006.173.09:55:43.89#ibcon#flushed, iclass 29, count 0 2006.173.09:55:43.89#ibcon#about to write, iclass 29, count 0 2006.173.09:55:43.89#ibcon#wrote, iclass 29, count 0 2006.173.09:55:43.89#ibcon#about to read 3, iclass 29, count 0 2006.173.09:55:43.93#ibcon#read 3, iclass 29, count 0 2006.173.09:55:43.93#ibcon#about to read 4, iclass 29, count 0 2006.173.09:55:43.93#ibcon#read 4, iclass 29, count 0 2006.173.09:55:43.93#ibcon#about to read 5, iclass 29, count 0 2006.173.09:55:43.93#ibcon#read 5, iclass 29, count 0 2006.173.09:55:43.93#ibcon#about to read 6, iclass 29, count 0 2006.173.09:55:43.93#ibcon#read 6, iclass 29, count 0 2006.173.09:55:43.93#ibcon#end of sib2, iclass 29, count 0 2006.173.09:55:43.93#ibcon#*after write, iclass 29, count 0 2006.173.09:55:43.93#ibcon#*before return 0, iclass 29, count 0 2006.173.09:55:43.93#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.09:55:43.93#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.09:55:43.93#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.09:55:43.93#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.09:55:43.93$vck44/vb=4,4 2006.173.09:55:43.93#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.09:55:43.93#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.09:55:43.93#ibcon#ireg 11 cls_cnt 2 2006.173.09:55:43.93#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.09:55:43.99#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.09:55:43.99#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.09:55:43.99#ibcon#enter wrdev, iclass 31, count 2 2006.173.09:55:43.99#ibcon#first serial, iclass 31, count 2 2006.173.09:55:43.99#ibcon#enter sib2, iclass 31, count 2 2006.173.09:55:43.99#ibcon#flushed, iclass 31, count 2 2006.173.09:55:43.99#ibcon#about to write, iclass 31, count 2 2006.173.09:55:43.99#ibcon#wrote, iclass 31, count 2 2006.173.09:55:43.99#ibcon#about to read 3, iclass 31, count 2 2006.173.09:55:44.01#ibcon#read 3, iclass 31, count 2 2006.173.09:55:44.01#ibcon#about to read 4, iclass 31, count 2 2006.173.09:55:44.01#ibcon#read 4, iclass 31, count 2 2006.173.09:55:44.01#ibcon#about to read 5, iclass 31, count 2 2006.173.09:55:44.01#ibcon#read 5, iclass 31, count 2 2006.173.09:55:44.01#ibcon#about to read 6, iclass 31, count 2 2006.173.09:55:44.01#ibcon#read 6, iclass 31, count 2 2006.173.09:55:44.01#ibcon#end of sib2, iclass 31, count 2 2006.173.09:55:44.01#ibcon#*mode == 0, iclass 31, count 2 2006.173.09:55:44.01#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.09:55:44.01#ibcon#[27=AT04-04\r\n] 2006.173.09:55:44.01#ibcon#*before write, iclass 31, count 2 2006.173.09:55:44.01#ibcon#enter sib2, iclass 31, count 2 2006.173.09:55:44.01#ibcon#flushed, iclass 31, count 2 2006.173.09:55:44.01#ibcon#about to write, iclass 31, count 2 2006.173.09:55:44.01#ibcon#wrote, iclass 31, count 2 2006.173.09:55:44.01#ibcon#about to read 3, iclass 31, count 2 2006.173.09:55:44.04#ibcon#read 3, iclass 31, count 2 2006.173.09:55:44.04#ibcon#about to read 4, iclass 31, count 2 2006.173.09:55:44.04#ibcon#read 4, iclass 31, count 2 2006.173.09:55:44.04#ibcon#about to read 5, iclass 31, count 2 2006.173.09:55:44.04#ibcon#read 5, iclass 31, count 2 2006.173.09:55:44.04#ibcon#about to read 6, iclass 31, count 2 2006.173.09:55:44.04#ibcon#read 6, iclass 31, count 2 2006.173.09:55:44.04#ibcon#end of sib2, iclass 31, count 2 2006.173.09:55:44.04#ibcon#*after write, iclass 31, count 2 2006.173.09:55:44.04#ibcon#*before return 0, iclass 31, count 2 2006.173.09:55:44.04#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.09:55:44.04#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.09:55:44.04#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.09:55:44.04#ibcon#ireg 7 cls_cnt 0 2006.173.09:55:44.04#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.09:55:44.16#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.09:55:44.16#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.09:55:44.16#ibcon#enter wrdev, iclass 31, count 0 2006.173.09:55:44.16#ibcon#first serial, iclass 31, count 0 2006.173.09:55:44.16#ibcon#enter sib2, iclass 31, count 0 2006.173.09:55:44.16#ibcon#flushed, iclass 31, count 0 2006.173.09:55:44.16#ibcon#about to write, iclass 31, count 0 2006.173.09:55:44.16#ibcon#wrote, iclass 31, count 0 2006.173.09:55:44.16#ibcon#about to read 3, iclass 31, count 0 2006.173.09:55:44.18#ibcon#read 3, iclass 31, count 0 2006.173.09:55:44.18#ibcon#about to read 4, iclass 31, count 0 2006.173.09:55:44.18#ibcon#read 4, iclass 31, count 0 2006.173.09:55:44.18#ibcon#about to read 5, iclass 31, count 0 2006.173.09:55:44.18#ibcon#read 5, iclass 31, count 0 2006.173.09:55:44.18#ibcon#about to read 6, iclass 31, count 0 2006.173.09:55:44.18#ibcon#read 6, iclass 31, count 0 2006.173.09:55:44.18#ibcon#end of sib2, iclass 31, count 0 2006.173.09:55:44.18#ibcon#*mode == 0, iclass 31, count 0 2006.173.09:55:44.18#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.09:55:44.18#ibcon#[27=USB\r\n] 2006.173.09:55:44.18#ibcon#*before write, iclass 31, count 0 2006.173.09:55:44.18#ibcon#enter sib2, iclass 31, count 0 2006.173.09:55:44.18#ibcon#flushed, iclass 31, count 0 2006.173.09:55:44.18#ibcon#about to write, iclass 31, count 0 2006.173.09:55:44.18#ibcon#wrote, iclass 31, count 0 2006.173.09:55:44.18#ibcon#about to read 3, iclass 31, count 0 2006.173.09:55:44.21#ibcon#read 3, iclass 31, count 0 2006.173.09:55:44.21#ibcon#about to read 4, iclass 31, count 0 2006.173.09:55:44.21#ibcon#read 4, iclass 31, count 0 2006.173.09:55:44.21#ibcon#about to read 5, iclass 31, count 0 2006.173.09:55:44.21#ibcon#read 5, iclass 31, count 0 2006.173.09:55:44.21#ibcon#about to read 6, iclass 31, count 0 2006.173.09:55:44.21#ibcon#read 6, iclass 31, count 0 2006.173.09:55:44.21#ibcon#end of sib2, iclass 31, count 0 2006.173.09:55:44.21#ibcon#*after write, iclass 31, count 0 2006.173.09:55:44.21#ibcon#*before return 0, iclass 31, count 0 2006.173.09:55:44.21#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.09:55:44.21#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.09:55:44.21#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.09:55:44.21#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.09:55:44.21$vck44/vblo=5,709.99 2006.173.09:55:44.21#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.09:55:44.21#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.09:55:44.21#ibcon#ireg 17 cls_cnt 0 2006.173.09:55:44.21#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.09:55:44.21#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.09:55:44.21#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.09:55:44.21#ibcon#enter wrdev, iclass 33, count 0 2006.173.09:55:44.21#ibcon#first serial, iclass 33, count 0 2006.173.09:55:44.21#ibcon#enter sib2, iclass 33, count 0 2006.173.09:55:44.21#ibcon#flushed, iclass 33, count 0 2006.173.09:55:44.21#ibcon#about to write, iclass 33, count 0 2006.173.09:55:44.21#ibcon#wrote, iclass 33, count 0 2006.173.09:55:44.21#ibcon#about to read 3, iclass 33, count 0 2006.173.09:55:44.23#ibcon#read 3, iclass 33, count 0 2006.173.09:55:44.23#ibcon#about to read 4, iclass 33, count 0 2006.173.09:55:44.23#ibcon#read 4, iclass 33, count 0 2006.173.09:55:44.23#ibcon#about to read 5, iclass 33, count 0 2006.173.09:55:44.23#ibcon#read 5, iclass 33, count 0 2006.173.09:55:44.23#ibcon#about to read 6, iclass 33, count 0 2006.173.09:55:44.23#ibcon#read 6, iclass 33, count 0 2006.173.09:55:44.23#ibcon#end of sib2, iclass 33, count 0 2006.173.09:55:44.23#ibcon#*mode == 0, iclass 33, count 0 2006.173.09:55:44.23#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.09:55:44.23#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.09:55:44.23#ibcon#*before write, iclass 33, count 0 2006.173.09:55:44.23#ibcon#enter sib2, iclass 33, count 0 2006.173.09:55:44.23#ibcon#flushed, iclass 33, count 0 2006.173.09:55:44.23#ibcon#about to write, iclass 33, count 0 2006.173.09:55:44.23#ibcon#wrote, iclass 33, count 0 2006.173.09:55:44.23#ibcon#about to read 3, iclass 33, count 0 2006.173.09:55:44.27#ibcon#read 3, iclass 33, count 0 2006.173.09:55:44.27#ibcon#about to read 4, iclass 33, count 0 2006.173.09:55:44.27#ibcon#read 4, iclass 33, count 0 2006.173.09:55:44.27#ibcon#about to read 5, iclass 33, count 0 2006.173.09:55:44.27#ibcon#read 5, iclass 33, count 0 2006.173.09:55:44.27#ibcon#about to read 6, iclass 33, count 0 2006.173.09:55:44.27#ibcon#read 6, iclass 33, count 0 2006.173.09:55:44.27#ibcon#end of sib2, iclass 33, count 0 2006.173.09:55:44.27#ibcon#*after write, iclass 33, count 0 2006.173.09:55:44.27#ibcon#*before return 0, iclass 33, count 0 2006.173.09:55:44.27#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.09:55:44.27#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.09:55:44.27#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.09:55:44.27#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.09:55:44.27$vck44/vb=5,4 2006.173.09:55:44.27#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.09:55:44.27#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.09:55:44.27#ibcon#ireg 11 cls_cnt 2 2006.173.09:55:44.27#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.09:55:44.33#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.09:55:44.33#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.09:55:44.33#ibcon#enter wrdev, iclass 35, count 2 2006.173.09:55:44.33#ibcon#first serial, iclass 35, count 2 2006.173.09:55:44.33#ibcon#enter sib2, iclass 35, count 2 2006.173.09:55:44.33#ibcon#flushed, iclass 35, count 2 2006.173.09:55:44.33#ibcon#about to write, iclass 35, count 2 2006.173.09:55:44.33#ibcon#wrote, iclass 35, count 2 2006.173.09:55:44.33#ibcon#about to read 3, iclass 35, count 2 2006.173.09:55:44.35#ibcon#read 3, iclass 35, count 2 2006.173.09:55:44.35#ibcon#about to read 4, iclass 35, count 2 2006.173.09:55:44.35#ibcon#read 4, iclass 35, count 2 2006.173.09:55:44.35#ibcon#about to read 5, iclass 35, count 2 2006.173.09:55:44.35#ibcon#read 5, iclass 35, count 2 2006.173.09:55:44.35#ibcon#about to read 6, iclass 35, count 2 2006.173.09:55:44.35#ibcon#read 6, iclass 35, count 2 2006.173.09:55:44.35#ibcon#end of sib2, iclass 35, count 2 2006.173.09:55:44.35#ibcon#*mode == 0, iclass 35, count 2 2006.173.09:55:44.35#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.09:55:44.35#ibcon#[27=AT05-04\r\n] 2006.173.09:55:44.35#ibcon#*before write, iclass 35, count 2 2006.173.09:55:44.35#ibcon#enter sib2, iclass 35, count 2 2006.173.09:55:44.35#ibcon#flushed, iclass 35, count 2 2006.173.09:55:44.35#ibcon#about to write, iclass 35, count 2 2006.173.09:55:44.35#ibcon#wrote, iclass 35, count 2 2006.173.09:55:44.35#ibcon#about to read 3, iclass 35, count 2 2006.173.09:55:44.38#ibcon#read 3, iclass 35, count 2 2006.173.09:55:44.38#ibcon#about to read 4, iclass 35, count 2 2006.173.09:55:44.38#ibcon#read 4, iclass 35, count 2 2006.173.09:55:44.38#ibcon#about to read 5, iclass 35, count 2 2006.173.09:55:44.38#ibcon#read 5, iclass 35, count 2 2006.173.09:55:44.38#ibcon#about to read 6, iclass 35, count 2 2006.173.09:55:44.38#ibcon#read 6, iclass 35, count 2 2006.173.09:55:44.38#ibcon#end of sib2, iclass 35, count 2 2006.173.09:55:44.38#ibcon#*after write, iclass 35, count 2 2006.173.09:55:44.38#ibcon#*before return 0, iclass 35, count 2 2006.173.09:55:44.38#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.09:55:44.38#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.09:55:44.38#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.09:55:44.38#ibcon#ireg 7 cls_cnt 0 2006.173.09:55:44.38#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.09:55:44.50#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.09:55:44.50#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.09:55:44.50#ibcon#enter wrdev, iclass 35, count 0 2006.173.09:55:44.50#ibcon#first serial, iclass 35, count 0 2006.173.09:55:44.50#ibcon#enter sib2, iclass 35, count 0 2006.173.09:55:44.50#ibcon#flushed, iclass 35, count 0 2006.173.09:55:44.50#ibcon#about to write, iclass 35, count 0 2006.173.09:55:44.50#ibcon#wrote, iclass 35, count 0 2006.173.09:55:44.50#ibcon#about to read 3, iclass 35, count 0 2006.173.09:55:44.52#ibcon#read 3, iclass 35, count 0 2006.173.09:55:44.52#ibcon#about to read 4, iclass 35, count 0 2006.173.09:55:44.52#ibcon#read 4, iclass 35, count 0 2006.173.09:55:44.52#ibcon#about to read 5, iclass 35, count 0 2006.173.09:55:44.52#ibcon#read 5, iclass 35, count 0 2006.173.09:55:44.52#ibcon#about to read 6, iclass 35, count 0 2006.173.09:55:44.52#ibcon#read 6, iclass 35, count 0 2006.173.09:55:44.52#ibcon#end of sib2, iclass 35, count 0 2006.173.09:55:44.52#ibcon#*mode == 0, iclass 35, count 0 2006.173.09:55:44.52#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.09:55:44.52#ibcon#[27=USB\r\n] 2006.173.09:55:44.52#ibcon#*before write, iclass 35, count 0 2006.173.09:55:44.52#ibcon#enter sib2, iclass 35, count 0 2006.173.09:55:44.52#ibcon#flushed, iclass 35, count 0 2006.173.09:55:44.52#ibcon#about to write, iclass 35, count 0 2006.173.09:55:44.52#ibcon#wrote, iclass 35, count 0 2006.173.09:55:44.52#ibcon#about to read 3, iclass 35, count 0 2006.173.09:55:44.55#ibcon#read 3, iclass 35, count 0 2006.173.09:55:44.55#ibcon#about to read 4, iclass 35, count 0 2006.173.09:55:44.55#ibcon#read 4, iclass 35, count 0 2006.173.09:55:44.55#ibcon#about to read 5, iclass 35, count 0 2006.173.09:55:44.55#ibcon#read 5, iclass 35, count 0 2006.173.09:55:44.55#ibcon#about to read 6, iclass 35, count 0 2006.173.09:55:44.55#ibcon#read 6, iclass 35, count 0 2006.173.09:55:44.55#ibcon#end of sib2, iclass 35, count 0 2006.173.09:55:44.55#ibcon#*after write, iclass 35, count 0 2006.173.09:55:44.55#ibcon#*before return 0, iclass 35, count 0 2006.173.09:55:44.55#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.09:55:44.55#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.09:55:44.55#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.09:55:44.55#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.09:55:44.55$vck44/vblo=6,719.99 2006.173.09:55:44.55#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.09:55:44.55#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.09:55:44.55#ibcon#ireg 17 cls_cnt 0 2006.173.09:55:44.55#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.09:55:44.55#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.09:55:44.55#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.09:55:44.55#ibcon#enter wrdev, iclass 37, count 0 2006.173.09:55:44.55#ibcon#first serial, iclass 37, count 0 2006.173.09:55:44.55#ibcon#enter sib2, iclass 37, count 0 2006.173.09:55:44.55#ibcon#flushed, iclass 37, count 0 2006.173.09:55:44.55#ibcon#about to write, iclass 37, count 0 2006.173.09:55:44.55#ibcon#wrote, iclass 37, count 0 2006.173.09:55:44.55#ibcon#about to read 3, iclass 37, count 0 2006.173.09:55:44.57#ibcon#read 3, iclass 37, count 0 2006.173.09:55:44.57#ibcon#about to read 4, iclass 37, count 0 2006.173.09:55:44.57#ibcon#read 4, iclass 37, count 0 2006.173.09:55:44.57#ibcon#about to read 5, iclass 37, count 0 2006.173.09:55:44.57#ibcon#read 5, iclass 37, count 0 2006.173.09:55:44.57#ibcon#about to read 6, iclass 37, count 0 2006.173.09:55:44.57#ibcon#read 6, iclass 37, count 0 2006.173.09:55:44.57#ibcon#end of sib2, iclass 37, count 0 2006.173.09:55:44.57#ibcon#*mode == 0, iclass 37, count 0 2006.173.09:55:44.57#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.09:55:44.57#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.09:55:44.57#ibcon#*before write, iclass 37, count 0 2006.173.09:55:44.57#ibcon#enter sib2, iclass 37, count 0 2006.173.09:55:44.57#ibcon#flushed, iclass 37, count 0 2006.173.09:55:44.57#ibcon#about to write, iclass 37, count 0 2006.173.09:55:44.57#ibcon#wrote, iclass 37, count 0 2006.173.09:55:44.57#ibcon#about to read 3, iclass 37, count 0 2006.173.09:55:44.61#ibcon#read 3, iclass 37, count 0 2006.173.09:55:44.61#ibcon#about to read 4, iclass 37, count 0 2006.173.09:55:44.61#ibcon#read 4, iclass 37, count 0 2006.173.09:55:44.61#ibcon#about to read 5, iclass 37, count 0 2006.173.09:55:44.61#ibcon#read 5, iclass 37, count 0 2006.173.09:55:44.61#ibcon#about to read 6, iclass 37, count 0 2006.173.09:55:44.61#ibcon#read 6, iclass 37, count 0 2006.173.09:55:44.61#ibcon#end of sib2, iclass 37, count 0 2006.173.09:55:44.61#ibcon#*after write, iclass 37, count 0 2006.173.09:55:44.61#ibcon#*before return 0, iclass 37, count 0 2006.173.09:55:44.61#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.09:55:44.61#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.09:55:44.61#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.09:55:44.61#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.09:55:44.61$vck44/vb=6,4 2006.173.09:55:44.61#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.09:55:44.61#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.09:55:44.61#ibcon#ireg 11 cls_cnt 2 2006.173.09:55:44.61#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.09:55:44.67#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.09:55:44.67#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.09:55:44.67#ibcon#enter wrdev, iclass 39, count 2 2006.173.09:55:44.67#ibcon#first serial, iclass 39, count 2 2006.173.09:55:44.67#ibcon#enter sib2, iclass 39, count 2 2006.173.09:55:44.67#ibcon#flushed, iclass 39, count 2 2006.173.09:55:44.67#ibcon#about to write, iclass 39, count 2 2006.173.09:55:44.67#ibcon#wrote, iclass 39, count 2 2006.173.09:55:44.67#ibcon#about to read 3, iclass 39, count 2 2006.173.09:55:44.69#ibcon#read 3, iclass 39, count 2 2006.173.09:55:44.69#ibcon#about to read 4, iclass 39, count 2 2006.173.09:55:44.69#ibcon#read 4, iclass 39, count 2 2006.173.09:55:44.69#ibcon#about to read 5, iclass 39, count 2 2006.173.09:55:44.69#ibcon#read 5, iclass 39, count 2 2006.173.09:55:44.69#ibcon#about to read 6, iclass 39, count 2 2006.173.09:55:44.69#ibcon#read 6, iclass 39, count 2 2006.173.09:55:44.69#ibcon#end of sib2, iclass 39, count 2 2006.173.09:55:44.69#ibcon#*mode == 0, iclass 39, count 2 2006.173.09:55:44.69#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.09:55:44.69#ibcon#[27=AT06-04\r\n] 2006.173.09:55:44.69#ibcon#*before write, iclass 39, count 2 2006.173.09:55:44.69#ibcon#enter sib2, iclass 39, count 2 2006.173.09:55:44.69#ibcon#flushed, iclass 39, count 2 2006.173.09:55:44.69#ibcon#about to write, iclass 39, count 2 2006.173.09:55:44.69#ibcon#wrote, iclass 39, count 2 2006.173.09:55:44.69#ibcon#about to read 3, iclass 39, count 2 2006.173.09:55:44.72#ibcon#read 3, iclass 39, count 2 2006.173.09:55:44.72#ibcon#about to read 4, iclass 39, count 2 2006.173.09:55:44.72#ibcon#read 4, iclass 39, count 2 2006.173.09:55:44.72#ibcon#about to read 5, iclass 39, count 2 2006.173.09:55:44.72#ibcon#read 5, iclass 39, count 2 2006.173.09:55:44.72#ibcon#about to read 6, iclass 39, count 2 2006.173.09:55:44.72#ibcon#read 6, iclass 39, count 2 2006.173.09:55:44.72#ibcon#end of sib2, iclass 39, count 2 2006.173.09:55:44.72#ibcon#*after write, iclass 39, count 2 2006.173.09:55:44.72#ibcon#*before return 0, iclass 39, count 2 2006.173.09:55:44.72#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.09:55:44.72#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.09:55:44.72#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.09:55:44.72#ibcon#ireg 7 cls_cnt 0 2006.173.09:55:44.72#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.09:55:44.84#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.09:55:44.84#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.09:55:44.84#ibcon#enter wrdev, iclass 39, count 0 2006.173.09:55:44.84#ibcon#first serial, iclass 39, count 0 2006.173.09:55:44.84#ibcon#enter sib2, iclass 39, count 0 2006.173.09:55:44.84#ibcon#flushed, iclass 39, count 0 2006.173.09:55:44.84#ibcon#about to write, iclass 39, count 0 2006.173.09:55:44.84#ibcon#wrote, iclass 39, count 0 2006.173.09:55:44.84#ibcon#about to read 3, iclass 39, count 0 2006.173.09:55:44.86#ibcon#read 3, iclass 39, count 0 2006.173.09:55:44.86#ibcon#about to read 4, iclass 39, count 0 2006.173.09:55:44.86#ibcon#read 4, iclass 39, count 0 2006.173.09:55:44.86#ibcon#about to read 5, iclass 39, count 0 2006.173.09:55:44.86#ibcon#read 5, iclass 39, count 0 2006.173.09:55:44.86#ibcon#about to read 6, iclass 39, count 0 2006.173.09:55:44.86#ibcon#read 6, iclass 39, count 0 2006.173.09:55:44.86#ibcon#end of sib2, iclass 39, count 0 2006.173.09:55:44.86#ibcon#*mode == 0, iclass 39, count 0 2006.173.09:55:44.86#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.09:55:44.86#ibcon#[27=USB\r\n] 2006.173.09:55:44.86#ibcon#*before write, iclass 39, count 0 2006.173.09:55:44.86#ibcon#enter sib2, iclass 39, count 0 2006.173.09:55:44.86#ibcon#flushed, iclass 39, count 0 2006.173.09:55:44.86#ibcon#about to write, iclass 39, count 0 2006.173.09:55:44.86#ibcon#wrote, iclass 39, count 0 2006.173.09:55:44.86#ibcon#about to read 3, iclass 39, count 0 2006.173.09:55:44.89#ibcon#read 3, iclass 39, count 0 2006.173.09:55:44.89#ibcon#about to read 4, iclass 39, count 0 2006.173.09:55:44.89#ibcon#read 4, iclass 39, count 0 2006.173.09:55:44.89#ibcon#about to read 5, iclass 39, count 0 2006.173.09:55:44.89#ibcon#read 5, iclass 39, count 0 2006.173.09:55:44.89#ibcon#about to read 6, iclass 39, count 0 2006.173.09:55:44.89#ibcon#read 6, iclass 39, count 0 2006.173.09:55:44.89#ibcon#end of sib2, iclass 39, count 0 2006.173.09:55:44.89#ibcon#*after write, iclass 39, count 0 2006.173.09:55:44.89#ibcon#*before return 0, iclass 39, count 0 2006.173.09:55:44.89#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.09:55:44.89#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.09:55:44.89#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.09:55:44.89#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.09:55:44.89$vck44/vblo=7,734.99 2006.173.09:55:44.89#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.09:55:44.89#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.09:55:44.89#ibcon#ireg 17 cls_cnt 0 2006.173.09:55:44.89#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.09:55:44.89#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.09:55:44.89#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.09:55:44.89#ibcon#enter wrdev, iclass 3, count 0 2006.173.09:55:44.89#ibcon#first serial, iclass 3, count 0 2006.173.09:55:44.89#ibcon#enter sib2, iclass 3, count 0 2006.173.09:55:44.89#ibcon#flushed, iclass 3, count 0 2006.173.09:55:44.89#ibcon#about to write, iclass 3, count 0 2006.173.09:55:44.89#ibcon#wrote, iclass 3, count 0 2006.173.09:55:44.89#ibcon#about to read 3, iclass 3, count 0 2006.173.09:55:44.91#ibcon#read 3, iclass 3, count 0 2006.173.09:55:44.91#ibcon#about to read 4, iclass 3, count 0 2006.173.09:55:44.91#ibcon#read 4, iclass 3, count 0 2006.173.09:55:44.91#ibcon#about to read 5, iclass 3, count 0 2006.173.09:55:44.91#ibcon#read 5, iclass 3, count 0 2006.173.09:55:44.91#ibcon#about to read 6, iclass 3, count 0 2006.173.09:55:44.91#ibcon#read 6, iclass 3, count 0 2006.173.09:55:44.91#ibcon#end of sib2, iclass 3, count 0 2006.173.09:55:44.91#ibcon#*mode == 0, iclass 3, count 0 2006.173.09:55:44.91#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.09:55:44.91#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.09:55:44.91#ibcon#*before write, iclass 3, count 0 2006.173.09:55:44.91#ibcon#enter sib2, iclass 3, count 0 2006.173.09:55:44.91#ibcon#flushed, iclass 3, count 0 2006.173.09:55:44.91#ibcon#about to write, iclass 3, count 0 2006.173.09:55:44.91#ibcon#wrote, iclass 3, count 0 2006.173.09:55:44.91#ibcon#about to read 3, iclass 3, count 0 2006.173.09:55:44.95#ibcon#read 3, iclass 3, count 0 2006.173.09:55:44.95#ibcon#about to read 4, iclass 3, count 0 2006.173.09:55:44.95#ibcon#read 4, iclass 3, count 0 2006.173.09:55:44.95#ibcon#about to read 5, iclass 3, count 0 2006.173.09:55:44.95#ibcon#read 5, iclass 3, count 0 2006.173.09:55:44.95#ibcon#about to read 6, iclass 3, count 0 2006.173.09:55:44.95#ibcon#read 6, iclass 3, count 0 2006.173.09:55:44.95#ibcon#end of sib2, iclass 3, count 0 2006.173.09:55:44.95#ibcon#*after write, iclass 3, count 0 2006.173.09:55:44.95#ibcon#*before return 0, iclass 3, count 0 2006.173.09:55:44.95#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.09:55:44.95#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.09:55:44.95#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.09:55:44.95#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.09:55:44.95$vck44/vb=7,4 2006.173.09:55:44.95#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.09:55:44.95#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.09:55:44.95#ibcon#ireg 11 cls_cnt 2 2006.173.09:55:44.95#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.09:55:45.01#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.09:55:45.01#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.09:55:45.01#ibcon#enter wrdev, iclass 5, count 2 2006.173.09:55:45.01#ibcon#first serial, iclass 5, count 2 2006.173.09:55:45.01#ibcon#enter sib2, iclass 5, count 2 2006.173.09:55:45.01#ibcon#flushed, iclass 5, count 2 2006.173.09:55:45.01#ibcon#about to write, iclass 5, count 2 2006.173.09:55:45.01#ibcon#wrote, iclass 5, count 2 2006.173.09:55:45.01#ibcon#about to read 3, iclass 5, count 2 2006.173.09:55:45.03#ibcon#read 3, iclass 5, count 2 2006.173.09:55:45.03#ibcon#about to read 4, iclass 5, count 2 2006.173.09:55:45.03#ibcon#read 4, iclass 5, count 2 2006.173.09:55:45.03#ibcon#about to read 5, iclass 5, count 2 2006.173.09:55:45.03#ibcon#read 5, iclass 5, count 2 2006.173.09:55:45.03#ibcon#about to read 6, iclass 5, count 2 2006.173.09:55:45.03#ibcon#read 6, iclass 5, count 2 2006.173.09:55:45.03#ibcon#end of sib2, iclass 5, count 2 2006.173.09:55:45.03#ibcon#*mode == 0, iclass 5, count 2 2006.173.09:55:45.03#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.09:55:45.03#ibcon#[27=AT07-04\r\n] 2006.173.09:55:45.03#ibcon#*before write, iclass 5, count 2 2006.173.09:55:45.03#ibcon#enter sib2, iclass 5, count 2 2006.173.09:55:45.03#ibcon#flushed, iclass 5, count 2 2006.173.09:55:45.03#ibcon#about to write, iclass 5, count 2 2006.173.09:55:45.03#ibcon#wrote, iclass 5, count 2 2006.173.09:55:45.03#ibcon#about to read 3, iclass 5, count 2 2006.173.09:55:45.06#ibcon#read 3, iclass 5, count 2 2006.173.09:55:45.06#ibcon#about to read 4, iclass 5, count 2 2006.173.09:55:45.06#ibcon#read 4, iclass 5, count 2 2006.173.09:55:45.06#ibcon#about to read 5, iclass 5, count 2 2006.173.09:55:45.06#ibcon#read 5, iclass 5, count 2 2006.173.09:55:45.06#ibcon#about to read 6, iclass 5, count 2 2006.173.09:55:45.06#ibcon#read 6, iclass 5, count 2 2006.173.09:55:45.06#ibcon#end of sib2, iclass 5, count 2 2006.173.09:55:45.06#ibcon#*after write, iclass 5, count 2 2006.173.09:55:45.06#ibcon#*before return 0, iclass 5, count 2 2006.173.09:55:45.06#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.09:55:45.06#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.09:55:45.06#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.09:55:45.06#ibcon#ireg 7 cls_cnt 0 2006.173.09:55:45.06#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.09:55:45.18#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.09:55:45.18#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.09:55:45.18#ibcon#enter wrdev, iclass 5, count 0 2006.173.09:55:45.18#ibcon#first serial, iclass 5, count 0 2006.173.09:55:45.18#ibcon#enter sib2, iclass 5, count 0 2006.173.09:55:45.18#ibcon#flushed, iclass 5, count 0 2006.173.09:55:45.18#ibcon#about to write, iclass 5, count 0 2006.173.09:55:45.18#ibcon#wrote, iclass 5, count 0 2006.173.09:55:45.18#ibcon#about to read 3, iclass 5, count 0 2006.173.09:55:45.20#ibcon#read 3, iclass 5, count 0 2006.173.09:55:45.20#ibcon#about to read 4, iclass 5, count 0 2006.173.09:55:45.20#ibcon#read 4, iclass 5, count 0 2006.173.09:55:45.20#ibcon#about to read 5, iclass 5, count 0 2006.173.09:55:45.20#ibcon#read 5, iclass 5, count 0 2006.173.09:55:45.20#ibcon#about to read 6, iclass 5, count 0 2006.173.09:55:45.20#ibcon#read 6, iclass 5, count 0 2006.173.09:55:45.20#ibcon#end of sib2, iclass 5, count 0 2006.173.09:55:45.20#ibcon#*mode == 0, iclass 5, count 0 2006.173.09:55:45.20#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.09:55:45.20#ibcon#[27=USB\r\n] 2006.173.09:55:45.20#ibcon#*before write, iclass 5, count 0 2006.173.09:55:45.20#ibcon#enter sib2, iclass 5, count 0 2006.173.09:55:45.20#ibcon#flushed, iclass 5, count 0 2006.173.09:55:45.20#ibcon#about to write, iclass 5, count 0 2006.173.09:55:45.20#ibcon#wrote, iclass 5, count 0 2006.173.09:55:45.20#ibcon#about to read 3, iclass 5, count 0 2006.173.09:55:45.23#ibcon#read 3, iclass 5, count 0 2006.173.09:55:45.23#ibcon#about to read 4, iclass 5, count 0 2006.173.09:55:45.23#ibcon#read 4, iclass 5, count 0 2006.173.09:55:45.23#ibcon#about to read 5, iclass 5, count 0 2006.173.09:55:45.23#ibcon#read 5, iclass 5, count 0 2006.173.09:55:45.23#ibcon#about to read 6, iclass 5, count 0 2006.173.09:55:45.23#ibcon#read 6, iclass 5, count 0 2006.173.09:55:45.23#ibcon#end of sib2, iclass 5, count 0 2006.173.09:55:45.23#ibcon#*after write, iclass 5, count 0 2006.173.09:55:45.23#ibcon#*before return 0, iclass 5, count 0 2006.173.09:55:45.23#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.09:55:45.23#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.09:55:45.23#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.09:55:45.23#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.09:55:45.23$vck44/vblo=8,744.99 2006.173.09:55:45.23#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.09:55:45.23#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.09:55:45.23#ibcon#ireg 17 cls_cnt 0 2006.173.09:55:45.23#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.09:55:45.23#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.09:55:45.23#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.09:55:45.23#ibcon#enter wrdev, iclass 7, count 0 2006.173.09:55:45.23#ibcon#first serial, iclass 7, count 0 2006.173.09:55:45.23#ibcon#enter sib2, iclass 7, count 0 2006.173.09:55:45.23#ibcon#flushed, iclass 7, count 0 2006.173.09:55:45.23#ibcon#about to write, iclass 7, count 0 2006.173.09:55:45.23#ibcon#wrote, iclass 7, count 0 2006.173.09:55:45.23#ibcon#about to read 3, iclass 7, count 0 2006.173.09:55:45.25#ibcon#read 3, iclass 7, count 0 2006.173.09:55:45.25#ibcon#about to read 4, iclass 7, count 0 2006.173.09:55:45.25#ibcon#read 4, iclass 7, count 0 2006.173.09:55:45.25#ibcon#about to read 5, iclass 7, count 0 2006.173.09:55:45.25#ibcon#read 5, iclass 7, count 0 2006.173.09:55:45.25#ibcon#about to read 6, iclass 7, count 0 2006.173.09:55:45.25#ibcon#read 6, iclass 7, count 0 2006.173.09:55:45.25#ibcon#end of sib2, iclass 7, count 0 2006.173.09:55:45.25#ibcon#*mode == 0, iclass 7, count 0 2006.173.09:55:45.25#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.09:55:45.25#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.09:55:45.25#ibcon#*before write, iclass 7, count 0 2006.173.09:55:45.25#ibcon#enter sib2, iclass 7, count 0 2006.173.09:55:45.25#ibcon#flushed, iclass 7, count 0 2006.173.09:55:45.25#ibcon#about to write, iclass 7, count 0 2006.173.09:55:45.25#ibcon#wrote, iclass 7, count 0 2006.173.09:55:45.25#ibcon#about to read 3, iclass 7, count 0 2006.173.09:55:45.29#ibcon#read 3, iclass 7, count 0 2006.173.09:55:45.29#ibcon#about to read 4, iclass 7, count 0 2006.173.09:55:45.29#ibcon#read 4, iclass 7, count 0 2006.173.09:55:45.29#ibcon#about to read 5, iclass 7, count 0 2006.173.09:55:45.29#ibcon#read 5, iclass 7, count 0 2006.173.09:55:45.29#ibcon#about to read 6, iclass 7, count 0 2006.173.09:55:45.29#ibcon#read 6, iclass 7, count 0 2006.173.09:55:45.29#ibcon#end of sib2, iclass 7, count 0 2006.173.09:55:45.29#ibcon#*after write, iclass 7, count 0 2006.173.09:55:45.29#ibcon#*before return 0, iclass 7, count 0 2006.173.09:55:45.29#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.09:55:45.29#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.09:55:45.29#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.09:55:45.29#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.09:55:45.29$vck44/vb=8,4 2006.173.09:55:45.29#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.09:55:45.29#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.09:55:45.29#ibcon#ireg 11 cls_cnt 2 2006.173.09:55:45.29#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.09:55:45.35#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.09:55:45.35#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.09:55:45.35#ibcon#enter wrdev, iclass 11, count 2 2006.173.09:55:45.35#ibcon#first serial, iclass 11, count 2 2006.173.09:55:45.35#ibcon#enter sib2, iclass 11, count 2 2006.173.09:55:45.35#ibcon#flushed, iclass 11, count 2 2006.173.09:55:45.35#ibcon#about to write, iclass 11, count 2 2006.173.09:55:45.35#ibcon#wrote, iclass 11, count 2 2006.173.09:55:45.35#ibcon#about to read 3, iclass 11, count 2 2006.173.09:55:45.37#ibcon#read 3, iclass 11, count 2 2006.173.09:55:45.37#ibcon#about to read 4, iclass 11, count 2 2006.173.09:55:45.37#ibcon#read 4, iclass 11, count 2 2006.173.09:55:45.37#ibcon#about to read 5, iclass 11, count 2 2006.173.09:55:45.37#ibcon#read 5, iclass 11, count 2 2006.173.09:55:45.37#ibcon#about to read 6, iclass 11, count 2 2006.173.09:55:45.37#ibcon#read 6, iclass 11, count 2 2006.173.09:55:45.37#ibcon#end of sib2, iclass 11, count 2 2006.173.09:55:45.37#ibcon#*mode == 0, iclass 11, count 2 2006.173.09:55:45.37#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.09:55:45.37#ibcon#[27=AT08-04\r\n] 2006.173.09:55:45.37#ibcon#*before write, iclass 11, count 2 2006.173.09:55:45.37#ibcon#enter sib2, iclass 11, count 2 2006.173.09:55:45.37#ibcon#flushed, iclass 11, count 2 2006.173.09:55:45.37#ibcon#about to write, iclass 11, count 2 2006.173.09:55:45.37#ibcon#wrote, iclass 11, count 2 2006.173.09:55:45.37#ibcon#about to read 3, iclass 11, count 2 2006.173.09:55:45.40#ibcon#read 3, iclass 11, count 2 2006.173.09:55:45.40#ibcon#about to read 4, iclass 11, count 2 2006.173.09:55:45.40#ibcon#read 4, iclass 11, count 2 2006.173.09:55:45.40#ibcon#about to read 5, iclass 11, count 2 2006.173.09:55:45.40#ibcon#read 5, iclass 11, count 2 2006.173.09:55:45.40#ibcon#about to read 6, iclass 11, count 2 2006.173.09:55:45.40#ibcon#read 6, iclass 11, count 2 2006.173.09:55:45.40#ibcon#end of sib2, iclass 11, count 2 2006.173.09:55:45.40#ibcon#*after write, iclass 11, count 2 2006.173.09:55:45.40#ibcon#*before return 0, iclass 11, count 2 2006.173.09:55:45.40#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.09:55:45.40#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.09:55:45.40#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.09:55:45.40#ibcon#ireg 7 cls_cnt 0 2006.173.09:55:45.40#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.09:55:45.52#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.09:55:45.52#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.09:55:45.52#ibcon#enter wrdev, iclass 11, count 0 2006.173.09:55:45.52#ibcon#first serial, iclass 11, count 0 2006.173.09:55:45.52#ibcon#enter sib2, iclass 11, count 0 2006.173.09:55:45.52#ibcon#flushed, iclass 11, count 0 2006.173.09:55:45.52#ibcon#about to write, iclass 11, count 0 2006.173.09:55:45.52#ibcon#wrote, iclass 11, count 0 2006.173.09:55:45.52#ibcon#about to read 3, iclass 11, count 0 2006.173.09:55:45.54#ibcon#read 3, iclass 11, count 0 2006.173.09:55:45.54#ibcon#about to read 4, iclass 11, count 0 2006.173.09:55:45.54#ibcon#read 4, iclass 11, count 0 2006.173.09:55:45.54#ibcon#about to read 5, iclass 11, count 0 2006.173.09:55:45.54#ibcon#read 5, iclass 11, count 0 2006.173.09:55:45.54#ibcon#about to read 6, iclass 11, count 0 2006.173.09:55:45.54#ibcon#read 6, iclass 11, count 0 2006.173.09:55:45.54#ibcon#end of sib2, iclass 11, count 0 2006.173.09:55:45.54#ibcon#*mode == 0, iclass 11, count 0 2006.173.09:55:45.54#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.09:55:45.54#ibcon#[27=USB\r\n] 2006.173.09:55:45.54#ibcon#*before write, iclass 11, count 0 2006.173.09:55:45.54#ibcon#enter sib2, iclass 11, count 0 2006.173.09:55:45.54#ibcon#flushed, iclass 11, count 0 2006.173.09:55:45.54#ibcon#about to write, iclass 11, count 0 2006.173.09:55:45.54#ibcon#wrote, iclass 11, count 0 2006.173.09:55:45.54#ibcon#about to read 3, iclass 11, count 0 2006.173.09:55:45.57#ibcon#read 3, iclass 11, count 0 2006.173.09:55:45.57#ibcon#about to read 4, iclass 11, count 0 2006.173.09:55:45.57#ibcon#read 4, iclass 11, count 0 2006.173.09:55:45.57#ibcon#about to read 5, iclass 11, count 0 2006.173.09:55:45.57#ibcon#read 5, iclass 11, count 0 2006.173.09:55:45.57#ibcon#about to read 6, iclass 11, count 0 2006.173.09:55:45.57#ibcon#read 6, iclass 11, count 0 2006.173.09:55:45.57#ibcon#end of sib2, iclass 11, count 0 2006.173.09:55:45.57#ibcon#*after write, iclass 11, count 0 2006.173.09:55:45.57#ibcon#*before return 0, iclass 11, count 0 2006.173.09:55:45.57#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.09:55:45.57#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.09:55:45.57#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.09:55:45.57#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.09:55:45.57$vck44/vabw=wide 2006.173.09:55:45.57#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.09:55:45.57#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.09:55:45.57#ibcon#ireg 8 cls_cnt 0 2006.173.09:55:45.57#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.09:55:45.57#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.09:55:45.57#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.09:55:45.57#ibcon#enter wrdev, iclass 13, count 0 2006.173.09:55:45.57#ibcon#first serial, iclass 13, count 0 2006.173.09:55:45.57#ibcon#enter sib2, iclass 13, count 0 2006.173.09:55:45.57#ibcon#flushed, iclass 13, count 0 2006.173.09:55:45.57#ibcon#about to write, iclass 13, count 0 2006.173.09:55:45.57#ibcon#wrote, iclass 13, count 0 2006.173.09:55:45.57#ibcon#about to read 3, iclass 13, count 0 2006.173.09:55:45.59#ibcon#read 3, iclass 13, count 0 2006.173.09:55:45.59#ibcon#about to read 4, iclass 13, count 0 2006.173.09:55:45.59#ibcon#read 4, iclass 13, count 0 2006.173.09:55:45.59#ibcon#about to read 5, iclass 13, count 0 2006.173.09:55:45.59#ibcon#read 5, iclass 13, count 0 2006.173.09:55:45.59#ibcon#about to read 6, iclass 13, count 0 2006.173.09:55:45.59#ibcon#read 6, iclass 13, count 0 2006.173.09:55:45.59#ibcon#end of sib2, iclass 13, count 0 2006.173.09:55:45.59#ibcon#*mode == 0, iclass 13, count 0 2006.173.09:55:45.59#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.09:55:45.59#ibcon#[25=BW32\r\n] 2006.173.09:55:45.59#ibcon#*before write, iclass 13, count 0 2006.173.09:55:45.59#ibcon#enter sib2, iclass 13, count 0 2006.173.09:55:45.59#ibcon#flushed, iclass 13, count 0 2006.173.09:55:45.59#ibcon#about to write, iclass 13, count 0 2006.173.09:55:45.59#ibcon#wrote, iclass 13, count 0 2006.173.09:55:45.59#ibcon#about to read 3, iclass 13, count 0 2006.173.09:55:45.62#ibcon#read 3, iclass 13, count 0 2006.173.09:55:45.62#ibcon#about to read 4, iclass 13, count 0 2006.173.09:55:45.62#ibcon#read 4, iclass 13, count 0 2006.173.09:55:45.62#ibcon#about to read 5, iclass 13, count 0 2006.173.09:55:45.62#ibcon#read 5, iclass 13, count 0 2006.173.09:55:45.62#ibcon#about to read 6, iclass 13, count 0 2006.173.09:55:45.62#ibcon#read 6, iclass 13, count 0 2006.173.09:55:45.62#ibcon#end of sib2, iclass 13, count 0 2006.173.09:55:45.62#ibcon#*after write, iclass 13, count 0 2006.173.09:55:45.62#ibcon#*before return 0, iclass 13, count 0 2006.173.09:55:45.62#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.09:55:45.62#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.09:55:45.62#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.09:55:45.62#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.09:55:45.62$vck44/vbbw=wide 2006.173.09:55:45.62#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.09:55:45.62#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.09:55:45.62#ibcon#ireg 8 cls_cnt 0 2006.173.09:55:45.62#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.09:55:45.69#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.09:55:45.69#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.09:55:45.69#ibcon#enter wrdev, iclass 15, count 0 2006.173.09:55:45.69#ibcon#first serial, iclass 15, count 0 2006.173.09:55:45.69#ibcon#enter sib2, iclass 15, count 0 2006.173.09:55:45.69#ibcon#flushed, iclass 15, count 0 2006.173.09:55:45.69#ibcon#about to write, iclass 15, count 0 2006.173.09:55:45.69#ibcon#wrote, iclass 15, count 0 2006.173.09:55:45.69#ibcon#about to read 3, iclass 15, count 0 2006.173.09:55:45.71#ibcon#read 3, iclass 15, count 0 2006.173.09:55:45.71#ibcon#about to read 4, iclass 15, count 0 2006.173.09:55:45.71#ibcon#read 4, iclass 15, count 0 2006.173.09:55:45.71#ibcon#about to read 5, iclass 15, count 0 2006.173.09:55:45.71#ibcon#read 5, iclass 15, count 0 2006.173.09:55:45.71#ibcon#about to read 6, iclass 15, count 0 2006.173.09:55:45.71#ibcon#read 6, iclass 15, count 0 2006.173.09:55:45.71#ibcon#end of sib2, iclass 15, count 0 2006.173.09:55:45.71#ibcon#*mode == 0, iclass 15, count 0 2006.173.09:55:45.71#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.09:55:45.71#ibcon#[27=BW32\r\n] 2006.173.09:55:45.71#ibcon#*before write, iclass 15, count 0 2006.173.09:55:45.71#ibcon#enter sib2, iclass 15, count 0 2006.173.09:55:45.71#ibcon#flushed, iclass 15, count 0 2006.173.09:55:45.71#ibcon#about to write, iclass 15, count 0 2006.173.09:55:45.71#ibcon#wrote, iclass 15, count 0 2006.173.09:55:45.71#ibcon#about to read 3, iclass 15, count 0 2006.173.09:55:45.74#ibcon#read 3, iclass 15, count 0 2006.173.09:55:45.74#ibcon#about to read 4, iclass 15, count 0 2006.173.09:55:45.74#ibcon#read 4, iclass 15, count 0 2006.173.09:55:45.74#ibcon#about to read 5, iclass 15, count 0 2006.173.09:55:45.74#ibcon#read 5, iclass 15, count 0 2006.173.09:55:45.74#ibcon#about to read 6, iclass 15, count 0 2006.173.09:55:45.74#ibcon#read 6, iclass 15, count 0 2006.173.09:55:45.74#ibcon#end of sib2, iclass 15, count 0 2006.173.09:55:45.74#ibcon#*after write, iclass 15, count 0 2006.173.09:55:45.74#ibcon#*before return 0, iclass 15, count 0 2006.173.09:55:45.74#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.09:55:45.74#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.09:55:45.75#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.09:55:45.75#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.09:55:45.75$setupk4/ifdk4 2006.173.09:55:45.75$ifdk4/lo= 2006.173.09:55:45.75$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.09:55:45.75$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.09:55:45.75$ifdk4/patch= 2006.173.09:55:45.76$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.09:55:45.76$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.09:55:45.76$setupk4/!*+20s 2006.173.09:55:46.25#abcon#<5=/04 0.5 1.4 22.85 901004.4\r\n> 2006.173.09:55:46.27#abcon#{5=INTERFACE CLEAR} 2006.173.09:55:46.33#abcon#[5=S1D000X0/0*\r\n] 2006.173.09:55:56.42#abcon#<5=/04 0.5 1.4 22.85 901004.4\r\n> 2006.173.09:55:56.44#abcon#{5=INTERFACE CLEAR} 2006.173.09:55:56.50#abcon#[5=S1D000X0/0*\r\n] 2006.173.09:56:00.26$setupk4/"tpicd 2006.173.09:56:00.26$setupk4/echo=off 2006.173.09:56:00.26$setupk4/xlog=off 2006.173.09:56:00.26:!2006.173.10:01:07 2006.173.09:56:01.14#trakl#Source acquired 2006.173.09:56:03.14#flagr#flagr/antenna,acquired 2006.173.10:01:07.00:preob 2006.173.10:01:07.14/onsource/TRACKING 2006.173.10:01:07.14:!2006.173.10:01:17 2006.173.10:01:17.00:"tape 2006.173.10:01:17.00:"st=record 2006.173.10:01:17.00:data_valid=on 2006.173.10:01:17.00:midob 2006.173.10:01:18.14/onsource/TRACKING 2006.173.10:01:18.14/wx/22.86,1004.1,92 2006.173.10:01:18.29/cable/+6.5016E-03 2006.173.10:01:19.38/va/01,07,usb,yes,35,38 2006.173.10:01:19.38/va/02,06,usb,yes,35,36 2006.173.10:01:19.38/va/03,05,usb,yes,44,46 2006.173.10:01:19.38/va/04,06,usb,yes,35,38 2006.173.10:01:19.38/va/05,04,usb,yes,28,28 2006.173.10:01:19.38/va/06,03,usb,yes,39,39 2006.173.10:01:19.38/va/07,04,usb,yes,32,33 2006.173.10:01:19.38/va/08,04,usb,yes,27,32 2006.173.10:01:19.61/valo/01,524.99,yes,locked 2006.173.10:01:19.61/valo/02,534.99,yes,locked 2006.173.10:01:19.61/valo/03,564.99,yes,locked 2006.173.10:01:19.61/valo/04,624.99,yes,locked 2006.173.10:01:19.61/valo/05,734.99,yes,locked 2006.173.10:01:19.61/valo/06,814.99,yes,locked 2006.173.10:01:19.61/valo/07,864.99,yes,locked 2006.173.10:01:19.61/valo/08,884.99,yes,locked 2006.173.10:01:20.70/vb/01,04,usb,yes,29,27 2006.173.10:01:20.70/vb/02,04,usb,yes,31,31 2006.173.10:01:20.70/vb/03,04,usb,yes,28,31 2006.173.10:01:20.70/vb/04,04,usb,yes,32,31 2006.173.10:01:20.70/vb/05,04,usb,yes,25,27 2006.173.10:01:20.70/vb/06,04,usb,yes,29,26 2006.173.10:01:20.70/vb/07,04,usb,yes,29,29 2006.173.10:01:20.70/vb/08,04,usb,yes,27,30 2006.173.10:01:20.93/vblo/01,629.99,yes,locked 2006.173.10:01:20.93/vblo/02,634.99,yes,locked 2006.173.10:01:20.93/vblo/03,649.99,yes,locked 2006.173.10:01:20.93/vblo/04,679.99,yes,locked 2006.173.10:01:20.93/vblo/05,709.99,yes,locked 2006.173.10:01:20.93/vblo/06,719.99,yes,locked 2006.173.10:01:20.93/vblo/07,734.99,yes,locked 2006.173.10:01:20.93/vblo/08,744.99,yes,locked 2006.173.10:01:21.08/vabw/8 2006.173.10:01:21.23/vbbw/8 2006.173.10:01:21.32/xfe/off,on,15.2 2006.173.10:01:21.71/ifatt/23,28,28,28 2006.173.10:01:22.07/fmout-gps/S +3.99E-07 2006.173.10:01:22.11:!2006.173.10:02:57 2006.173.10:02:57.00:data_valid=off 2006.173.10:02:57.00:"et 2006.173.10:02:57.00:!+3s 2006.173.10:03:00.01:"tape 2006.173.10:03:00.01:postob 2006.173.10:03:00.21/cable/+6.5024E-03 2006.173.10:03:00.21/wx/22.85,1004.1,93 2006.173.10:03:01.07/fmout-gps/S +3.99E-07 2006.173.10:03:01.07:scan_name=173-1004,jd0606,40 2006.173.10:03:01.07:source=1741-038,174358.86,-035004.6,2000.0,cw 2006.173.10:03:02.14#flagr#flagr/antenna,new-source 2006.173.10:03:02.14:checkk5 2006.173.10:03:02.51/chk_autoobs//k5ts1/ autoobs is running! 2006.173.10:03:02.90/chk_autoobs//k5ts2/ autoobs is running! 2006.173.10:03:03.32/chk_autoobs//k5ts3/ autoobs is running! 2006.173.10:03:03.71/chk_autoobs//k5ts4/ autoobs is running! 2006.173.10:03:04.11/chk_obsdata//k5ts1/T1731001??a.dat file size is correct (nominal:400MB, actual:400MB). 2006.173.10:03:04.51/chk_obsdata//k5ts2/T1731001??b.dat file size is correct (nominal:400MB, actual:400MB). 2006.173.10:03:04.93/chk_obsdata//k5ts3/T1731001??c.dat file size is correct (nominal:400MB, actual:400MB). 2006.173.10:03:05.35/chk_obsdata//k5ts4/T1731001??d.dat file size is correct (nominal:400MB, actual:400MB). 2006.173.10:03:06.07/k5log//k5ts1_log_newline 2006.173.10:03:06.79/k5log//k5ts2_log_newline 2006.173.10:03:07.51/k5log//k5ts3_log_newline 2006.173.10:03:08.22/k5log//k5ts4_log_newline 2006.173.10:03:08.25/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.10:03:08.25:setupk4=1 2006.173.10:03:08.25$setupk4/echo=on 2006.173.10:03:08.25$setupk4/pcalon 2006.173.10:03:08.25$pcalon/"no phase cal control is implemented here 2006.173.10:03:08.25$setupk4/"tpicd=stop 2006.173.10:03:08.25$setupk4/"rec=synch_on 2006.173.10:03:08.25$setupk4/"rec_mode=128 2006.173.10:03:08.25$setupk4/!* 2006.173.10:03:08.25$setupk4/recpk4 2006.173.10:03:08.25$recpk4/recpatch= 2006.173.10:03:08.25$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.10:03:08.25$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.10:03:08.25$setupk4/vck44 2006.173.10:03:08.25$vck44/valo=1,524.99 2006.173.10:03:08.25#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.10:03:08.25#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.10:03:08.25#ibcon#ireg 17 cls_cnt 0 2006.173.10:03:08.25#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.10:03:08.25#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.10:03:08.25#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.10:03:08.25#ibcon#enter wrdev, iclass 16, count 0 2006.173.10:03:08.25#ibcon#first serial, iclass 16, count 0 2006.173.10:03:08.25#ibcon#enter sib2, iclass 16, count 0 2006.173.10:03:08.25#ibcon#flushed, iclass 16, count 0 2006.173.10:03:08.25#ibcon#about to write, iclass 16, count 0 2006.173.10:03:08.25#ibcon#wrote, iclass 16, count 0 2006.173.10:03:08.25#ibcon#about to read 3, iclass 16, count 0 2006.173.10:03:08.27#ibcon#read 3, iclass 16, count 0 2006.173.10:03:08.27#ibcon#about to read 4, iclass 16, count 0 2006.173.10:03:08.27#ibcon#read 4, iclass 16, count 0 2006.173.10:03:08.27#ibcon#about to read 5, iclass 16, count 0 2006.173.10:03:08.27#ibcon#read 5, iclass 16, count 0 2006.173.10:03:08.27#ibcon#about to read 6, iclass 16, count 0 2006.173.10:03:08.27#ibcon#read 6, iclass 16, count 0 2006.173.10:03:08.27#ibcon#end of sib2, iclass 16, count 0 2006.173.10:03:08.27#ibcon#*mode == 0, iclass 16, count 0 2006.173.10:03:08.27#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.10:03:08.27#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.10:03:08.27#ibcon#*before write, iclass 16, count 0 2006.173.10:03:08.27#ibcon#enter sib2, iclass 16, count 0 2006.173.10:03:08.27#ibcon#flushed, iclass 16, count 0 2006.173.10:03:08.27#ibcon#about to write, iclass 16, count 0 2006.173.10:03:08.27#ibcon#wrote, iclass 16, count 0 2006.173.10:03:08.27#ibcon#about to read 3, iclass 16, count 0 2006.173.10:03:08.32#ibcon#read 3, iclass 16, count 0 2006.173.10:03:08.32#ibcon#about to read 4, iclass 16, count 0 2006.173.10:03:08.32#ibcon#read 4, iclass 16, count 0 2006.173.10:03:08.32#ibcon#about to read 5, iclass 16, count 0 2006.173.10:03:08.32#ibcon#read 5, iclass 16, count 0 2006.173.10:03:08.32#ibcon#about to read 6, iclass 16, count 0 2006.173.10:03:08.32#ibcon#read 6, iclass 16, count 0 2006.173.10:03:08.32#ibcon#end of sib2, iclass 16, count 0 2006.173.10:03:08.32#ibcon#*after write, iclass 16, count 0 2006.173.10:03:08.32#ibcon#*before return 0, iclass 16, count 0 2006.173.10:03:08.32#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.10:03:08.32#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.10:03:08.32#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.10:03:08.32#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.10:03:08.32$vck44/va=1,7 2006.173.10:03:08.32#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.10:03:08.32#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.10:03:08.32#ibcon#ireg 11 cls_cnt 2 2006.173.10:03:08.32#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.10:03:08.32#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.10:03:08.32#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.10:03:08.32#ibcon#enter wrdev, iclass 18, count 2 2006.173.10:03:08.32#ibcon#first serial, iclass 18, count 2 2006.173.10:03:08.32#ibcon#enter sib2, iclass 18, count 2 2006.173.10:03:08.32#ibcon#flushed, iclass 18, count 2 2006.173.10:03:08.32#ibcon#about to write, iclass 18, count 2 2006.173.10:03:08.32#ibcon#wrote, iclass 18, count 2 2006.173.10:03:08.32#ibcon#about to read 3, iclass 18, count 2 2006.173.10:03:08.34#ibcon#read 3, iclass 18, count 2 2006.173.10:03:08.34#ibcon#about to read 4, iclass 18, count 2 2006.173.10:03:08.34#ibcon#read 4, iclass 18, count 2 2006.173.10:03:08.34#ibcon#about to read 5, iclass 18, count 2 2006.173.10:03:08.34#ibcon#read 5, iclass 18, count 2 2006.173.10:03:08.34#ibcon#about to read 6, iclass 18, count 2 2006.173.10:03:08.34#ibcon#read 6, iclass 18, count 2 2006.173.10:03:08.34#ibcon#end of sib2, iclass 18, count 2 2006.173.10:03:08.34#ibcon#*mode == 0, iclass 18, count 2 2006.173.10:03:08.34#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.10:03:08.34#ibcon#[25=AT01-07\r\n] 2006.173.10:03:08.34#ibcon#*before write, iclass 18, count 2 2006.173.10:03:08.34#ibcon#enter sib2, iclass 18, count 2 2006.173.10:03:08.34#ibcon#flushed, iclass 18, count 2 2006.173.10:03:08.34#ibcon#about to write, iclass 18, count 2 2006.173.10:03:08.34#ibcon#wrote, iclass 18, count 2 2006.173.10:03:08.34#ibcon#about to read 3, iclass 18, count 2 2006.173.10:03:08.37#ibcon#read 3, iclass 18, count 2 2006.173.10:03:08.37#ibcon#about to read 4, iclass 18, count 2 2006.173.10:03:08.37#ibcon#read 4, iclass 18, count 2 2006.173.10:03:08.37#ibcon#about to read 5, iclass 18, count 2 2006.173.10:03:08.37#ibcon#read 5, iclass 18, count 2 2006.173.10:03:08.37#ibcon#about to read 6, iclass 18, count 2 2006.173.10:03:08.37#ibcon#read 6, iclass 18, count 2 2006.173.10:03:08.37#ibcon#end of sib2, iclass 18, count 2 2006.173.10:03:08.37#ibcon#*after write, iclass 18, count 2 2006.173.10:03:08.37#ibcon#*before return 0, iclass 18, count 2 2006.173.10:03:08.37#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.10:03:08.37#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.10:03:08.37#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.10:03:08.37#ibcon#ireg 7 cls_cnt 0 2006.173.10:03:08.37#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.10:03:08.49#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.10:03:08.49#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.10:03:08.49#ibcon#enter wrdev, iclass 18, count 0 2006.173.10:03:08.49#ibcon#first serial, iclass 18, count 0 2006.173.10:03:08.49#ibcon#enter sib2, iclass 18, count 0 2006.173.10:03:08.49#ibcon#flushed, iclass 18, count 0 2006.173.10:03:08.49#ibcon#about to write, iclass 18, count 0 2006.173.10:03:08.49#ibcon#wrote, iclass 18, count 0 2006.173.10:03:08.49#ibcon#about to read 3, iclass 18, count 0 2006.173.10:03:08.51#ibcon#read 3, iclass 18, count 0 2006.173.10:03:08.51#ibcon#about to read 4, iclass 18, count 0 2006.173.10:03:08.51#ibcon#read 4, iclass 18, count 0 2006.173.10:03:08.51#ibcon#about to read 5, iclass 18, count 0 2006.173.10:03:08.51#ibcon#read 5, iclass 18, count 0 2006.173.10:03:08.51#ibcon#about to read 6, iclass 18, count 0 2006.173.10:03:08.51#ibcon#read 6, iclass 18, count 0 2006.173.10:03:08.51#ibcon#end of sib2, iclass 18, count 0 2006.173.10:03:08.51#ibcon#*mode == 0, iclass 18, count 0 2006.173.10:03:08.51#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.10:03:08.51#ibcon#[25=USB\r\n] 2006.173.10:03:08.51#ibcon#*before write, iclass 18, count 0 2006.173.10:03:08.51#ibcon#enter sib2, iclass 18, count 0 2006.173.10:03:08.51#ibcon#flushed, iclass 18, count 0 2006.173.10:03:08.51#ibcon#about to write, iclass 18, count 0 2006.173.10:03:08.51#ibcon#wrote, iclass 18, count 0 2006.173.10:03:08.51#ibcon#about to read 3, iclass 18, count 0 2006.173.10:03:08.54#ibcon#read 3, iclass 18, count 0 2006.173.10:03:08.54#ibcon#about to read 4, iclass 18, count 0 2006.173.10:03:08.54#ibcon#read 4, iclass 18, count 0 2006.173.10:03:08.54#ibcon#about to read 5, iclass 18, count 0 2006.173.10:03:08.54#ibcon#read 5, iclass 18, count 0 2006.173.10:03:08.54#ibcon#about to read 6, iclass 18, count 0 2006.173.10:03:08.54#ibcon#read 6, iclass 18, count 0 2006.173.10:03:08.54#ibcon#end of sib2, iclass 18, count 0 2006.173.10:03:08.54#ibcon#*after write, iclass 18, count 0 2006.173.10:03:08.54#ibcon#*before return 0, iclass 18, count 0 2006.173.10:03:08.54#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.10:03:08.54#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.10:03:08.54#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.10:03:08.54#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.10:03:08.54$vck44/valo=2,534.99 2006.173.10:03:08.54#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.10:03:08.54#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.10:03:08.54#ibcon#ireg 17 cls_cnt 0 2006.173.10:03:08.54#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.10:03:08.54#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.10:03:08.54#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.10:03:08.54#ibcon#enter wrdev, iclass 20, count 0 2006.173.10:03:08.54#ibcon#first serial, iclass 20, count 0 2006.173.10:03:08.54#ibcon#enter sib2, iclass 20, count 0 2006.173.10:03:08.54#ibcon#flushed, iclass 20, count 0 2006.173.10:03:08.54#ibcon#about to write, iclass 20, count 0 2006.173.10:03:08.54#ibcon#wrote, iclass 20, count 0 2006.173.10:03:08.54#ibcon#about to read 3, iclass 20, count 0 2006.173.10:03:08.56#ibcon#read 3, iclass 20, count 0 2006.173.10:03:08.56#ibcon#about to read 4, iclass 20, count 0 2006.173.10:03:08.56#ibcon#read 4, iclass 20, count 0 2006.173.10:03:08.56#ibcon#about to read 5, iclass 20, count 0 2006.173.10:03:08.56#ibcon#read 5, iclass 20, count 0 2006.173.10:03:08.56#ibcon#about to read 6, iclass 20, count 0 2006.173.10:03:08.56#ibcon#read 6, iclass 20, count 0 2006.173.10:03:08.56#ibcon#end of sib2, iclass 20, count 0 2006.173.10:03:08.56#ibcon#*mode == 0, iclass 20, count 0 2006.173.10:03:08.56#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.10:03:08.56#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.10:03:08.56#ibcon#*before write, iclass 20, count 0 2006.173.10:03:08.56#ibcon#enter sib2, iclass 20, count 0 2006.173.10:03:08.56#ibcon#flushed, iclass 20, count 0 2006.173.10:03:08.56#ibcon#about to write, iclass 20, count 0 2006.173.10:03:08.56#ibcon#wrote, iclass 20, count 0 2006.173.10:03:08.56#ibcon#about to read 3, iclass 20, count 0 2006.173.10:03:08.60#ibcon#read 3, iclass 20, count 0 2006.173.10:03:08.60#ibcon#about to read 4, iclass 20, count 0 2006.173.10:03:08.60#ibcon#read 4, iclass 20, count 0 2006.173.10:03:08.60#ibcon#about to read 5, iclass 20, count 0 2006.173.10:03:08.60#ibcon#read 5, iclass 20, count 0 2006.173.10:03:08.60#ibcon#about to read 6, iclass 20, count 0 2006.173.10:03:08.60#ibcon#read 6, iclass 20, count 0 2006.173.10:03:08.60#ibcon#end of sib2, iclass 20, count 0 2006.173.10:03:08.60#ibcon#*after write, iclass 20, count 0 2006.173.10:03:08.60#ibcon#*before return 0, iclass 20, count 0 2006.173.10:03:08.60#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.10:03:08.60#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.10:03:08.60#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.10:03:08.60#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.10:03:08.60$vck44/va=2,6 2006.173.10:03:08.60#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.10:03:08.60#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.10:03:08.60#ibcon#ireg 11 cls_cnt 2 2006.173.10:03:08.60#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.10:03:08.66#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.10:03:08.66#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.10:03:08.66#ibcon#enter wrdev, iclass 22, count 2 2006.173.10:03:08.66#ibcon#first serial, iclass 22, count 2 2006.173.10:03:08.66#ibcon#enter sib2, iclass 22, count 2 2006.173.10:03:08.66#ibcon#flushed, iclass 22, count 2 2006.173.10:03:08.66#ibcon#about to write, iclass 22, count 2 2006.173.10:03:08.66#ibcon#wrote, iclass 22, count 2 2006.173.10:03:08.66#ibcon#about to read 3, iclass 22, count 2 2006.173.10:03:08.68#ibcon#read 3, iclass 22, count 2 2006.173.10:03:08.68#ibcon#about to read 4, iclass 22, count 2 2006.173.10:03:08.68#ibcon#read 4, iclass 22, count 2 2006.173.10:03:08.68#ibcon#about to read 5, iclass 22, count 2 2006.173.10:03:08.68#ibcon#read 5, iclass 22, count 2 2006.173.10:03:08.68#ibcon#about to read 6, iclass 22, count 2 2006.173.10:03:08.68#ibcon#read 6, iclass 22, count 2 2006.173.10:03:08.68#ibcon#end of sib2, iclass 22, count 2 2006.173.10:03:08.68#ibcon#*mode == 0, iclass 22, count 2 2006.173.10:03:08.68#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.10:03:08.68#ibcon#[25=AT02-06\r\n] 2006.173.10:03:08.68#ibcon#*before write, iclass 22, count 2 2006.173.10:03:08.68#ibcon#enter sib2, iclass 22, count 2 2006.173.10:03:08.68#ibcon#flushed, iclass 22, count 2 2006.173.10:03:08.68#ibcon#about to write, iclass 22, count 2 2006.173.10:03:08.68#ibcon#wrote, iclass 22, count 2 2006.173.10:03:08.68#ibcon#about to read 3, iclass 22, count 2 2006.173.10:03:08.71#ibcon#read 3, iclass 22, count 2 2006.173.10:03:08.71#ibcon#about to read 4, iclass 22, count 2 2006.173.10:03:08.71#ibcon#read 4, iclass 22, count 2 2006.173.10:03:08.71#ibcon#about to read 5, iclass 22, count 2 2006.173.10:03:08.71#ibcon#read 5, iclass 22, count 2 2006.173.10:03:08.71#ibcon#about to read 6, iclass 22, count 2 2006.173.10:03:08.71#ibcon#read 6, iclass 22, count 2 2006.173.10:03:08.71#ibcon#end of sib2, iclass 22, count 2 2006.173.10:03:08.71#ibcon#*after write, iclass 22, count 2 2006.173.10:03:08.71#ibcon#*before return 0, iclass 22, count 2 2006.173.10:03:08.71#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.10:03:08.71#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.10:03:08.71#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.10:03:08.71#ibcon#ireg 7 cls_cnt 0 2006.173.10:03:08.71#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.10:03:08.83#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.10:03:08.83#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.10:03:08.83#ibcon#enter wrdev, iclass 22, count 0 2006.173.10:03:08.83#ibcon#first serial, iclass 22, count 0 2006.173.10:03:08.83#ibcon#enter sib2, iclass 22, count 0 2006.173.10:03:08.83#ibcon#flushed, iclass 22, count 0 2006.173.10:03:08.83#ibcon#about to write, iclass 22, count 0 2006.173.10:03:08.83#ibcon#wrote, iclass 22, count 0 2006.173.10:03:08.83#ibcon#about to read 3, iclass 22, count 0 2006.173.10:03:08.85#ibcon#read 3, iclass 22, count 0 2006.173.10:03:08.85#ibcon#about to read 4, iclass 22, count 0 2006.173.10:03:08.85#ibcon#read 4, iclass 22, count 0 2006.173.10:03:08.85#ibcon#about to read 5, iclass 22, count 0 2006.173.10:03:08.85#ibcon#read 5, iclass 22, count 0 2006.173.10:03:08.85#ibcon#about to read 6, iclass 22, count 0 2006.173.10:03:08.85#ibcon#read 6, iclass 22, count 0 2006.173.10:03:08.85#ibcon#end of sib2, iclass 22, count 0 2006.173.10:03:08.85#ibcon#*mode == 0, iclass 22, count 0 2006.173.10:03:08.85#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.10:03:08.85#ibcon#[25=USB\r\n] 2006.173.10:03:08.85#ibcon#*before write, iclass 22, count 0 2006.173.10:03:08.85#ibcon#enter sib2, iclass 22, count 0 2006.173.10:03:08.85#ibcon#flushed, iclass 22, count 0 2006.173.10:03:08.85#ibcon#about to write, iclass 22, count 0 2006.173.10:03:08.85#ibcon#wrote, iclass 22, count 0 2006.173.10:03:08.85#ibcon#about to read 3, iclass 22, count 0 2006.173.10:03:08.88#ibcon#read 3, iclass 22, count 0 2006.173.10:03:08.88#ibcon#about to read 4, iclass 22, count 0 2006.173.10:03:08.88#ibcon#read 4, iclass 22, count 0 2006.173.10:03:08.88#ibcon#about to read 5, iclass 22, count 0 2006.173.10:03:08.88#ibcon#read 5, iclass 22, count 0 2006.173.10:03:08.88#ibcon#about to read 6, iclass 22, count 0 2006.173.10:03:08.88#ibcon#read 6, iclass 22, count 0 2006.173.10:03:08.88#ibcon#end of sib2, iclass 22, count 0 2006.173.10:03:08.88#ibcon#*after write, iclass 22, count 0 2006.173.10:03:08.88#ibcon#*before return 0, iclass 22, count 0 2006.173.10:03:08.88#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.10:03:08.88#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.10:03:08.88#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.10:03:08.88#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.10:03:08.88$vck44/valo=3,564.99 2006.173.10:03:08.88#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.10:03:08.88#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.10:03:08.88#ibcon#ireg 17 cls_cnt 0 2006.173.10:03:08.88#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.10:03:08.88#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.10:03:08.88#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.10:03:08.88#ibcon#enter wrdev, iclass 24, count 0 2006.173.10:03:08.88#ibcon#first serial, iclass 24, count 0 2006.173.10:03:08.88#ibcon#enter sib2, iclass 24, count 0 2006.173.10:03:08.88#ibcon#flushed, iclass 24, count 0 2006.173.10:03:08.88#ibcon#about to write, iclass 24, count 0 2006.173.10:03:08.88#ibcon#wrote, iclass 24, count 0 2006.173.10:03:08.88#ibcon#about to read 3, iclass 24, count 0 2006.173.10:03:08.90#ibcon#read 3, iclass 24, count 0 2006.173.10:03:08.90#ibcon#about to read 4, iclass 24, count 0 2006.173.10:03:08.90#ibcon#read 4, iclass 24, count 0 2006.173.10:03:08.90#ibcon#about to read 5, iclass 24, count 0 2006.173.10:03:08.90#ibcon#read 5, iclass 24, count 0 2006.173.10:03:08.90#ibcon#about to read 6, iclass 24, count 0 2006.173.10:03:08.90#ibcon#read 6, iclass 24, count 0 2006.173.10:03:08.90#ibcon#end of sib2, iclass 24, count 0 2006.173.10:03:08.90#ibcon#*mode == 0, iclass 24, count 0 2006.173.10:03:08.90#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.10:03:08.90#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.10:03:08.90#ibcon#*before write, iclass 24, count 0 2006.173.10:03:08.90#ibcon#enter sib2, iclass 24, count 0 2006.173.10:03:08.90#ibcon#flushed, iclass 24, count 0 2006.173.10:03:08.90#ibcon#about to write, iclass 24, count 0 2006.173.10:03:08.90#ibcon#wrote, iclass 24, count 0 2006.173.10:03:08.90#ibcon#about to read 3, iclass 24, count 0 2006.173.10:03:08.94#ibcon#read 3, iclass 24, count 0 2006.173.10:03:08.94#ibcon#about to read 4, iclass 24, count 0 2006.173.10:03:08.94#ibcon#read 4, iclass 24, count 0 2006.173.10:03:08.94#ibcon#about to read 5, iclass 24, count 0 2006.173.10:03:08.94#ibcon#read 5, iclass 24, count 0 2006.173.10:03:08.94#ibcon#about to read 6, iclass 24, count 0 2006.173.10:03:08.94#ibcon#read 6, iclass 24, count 0 2006.173.10:03:08.94#ibcon#end of sib2, iclass 24, count 0 2006.173.10:03:08.94#ibcon#*after write, iclass 24, count 0 2006.173.10:03:08.94#ibcon#*before return 0, iclass 24, count 0 2006.173.10:03:08.94#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.10:03:08.94#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.10:03:08.94#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.10:03:08.94#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.10:03:08.94$vck44/va=3,5 2006.173.10:03:08.94#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.10:03:08.94#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.10:03:08.94#ibcon#ireg 11 cls_cnt 2 2006.173.10:03:08.94#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.10:03:09.00#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.10:03:09.00#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.10:03:09.00#ibcon#enter wrdev, iclass 26, count 2 2006.173.10:03:09.00#ibcon#first serial, iclass 26, count 2 2006.173.10:03:09.00#ibcon#enter sib2, iclass 26, count 2 2006.173.10:03:09.00#ibcon#flushed, iclass 26, count 2 2006.173.10:03:09.00#ibcon#about to write, iclass 26, count 2 2006.173.10:03:09.00#ibcon#wrote, iclass 26, count 2 2006.173.10:03:09.00#ibcon#about to read 3, iclass 26, count 2 2006.173.10:03:09.02#ibcon#read 3, iclass 26, count 2 2006.173.10:03:09.02#ibcon#about to read 4, iclass 26, count 2 2006.173.10:03:09.02#ibcon#read 4, iclass 26, count 2 2006.173.10:03:09.02#ibcon#about to read 5, iclass 26, count 2 2006.173.10:03:09.02#ibcon#read 5, iclass 26, count 2 2006.173.10:03:09.02#ibcon#about to read 6, iclass 26, count 2 2006.173.10:03:09.02#ibcon#read 6, iclass 26, count 2 2006.173.10:03:09.02#ibcon#end of sib2, iclass 26, count 2 2006.173.10:03:09.02#ibcon#*mode == 0, iclass 26, count 2 2006.173.10:03:09.02#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.10:03:09.02#ibcon#[25=AT03-05\r\n] 2006.173.10:03:09.02#ibcon#*before write, iclass 26, count 2 2006.173.10:03:09.02#ibcon#enter sib2, iclass 26, count 2 2006.173.10:03:09.02#ibcon#flushed, iclass 26, count 2 2006.173.10:03:09.02#ibcon#about to write, iclass 26, count 2 2006.173.10:03:09.02#ibcon#wrote, iclass 26, count 2 2006.173.10:03:09.02#ibcon#about to read 3, iclass 26, count 2 2006.173.10:03:09.05#ibcon#read 3, iclass 26, count 2 2006.173.10:03:09.05#ibcon#about to read 4, iclass 26, count 2 2006.173.10:03:09.05#ibcon#read 4, iclass 26, count 2 2006.173.10:03:09.05#ibcon#about to read 5, iclass 26, count 2 2006.173.10:03:09.05#ibcon#read 5, iclass 26, count 2 2006.173.10:03:09.05#ibcon#about to read 6, iclass 26, count 2 2006.173.10:03:09.05#ibcon#read 6, iclass 26, count 2 2006.173.10:03:09.05#ibcon#end of sib2, iclass 26, count 2 2006.173.10:03:09.05#ibcon#*after write, iclass 26, count 2 2006.173.10:03:09.05#ibcon#*before return 0, iclass 26, count 2 2006.173.10:03:09.05#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.10:03:09.05#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.10:03:09.05#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.10:03:09.05#ibcon#ireg 7 cls_cnt 0 2006.173.10:03:09.05#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.10:03:09.17#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.10:03:09.17#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.10:03:09.17#ibcon#enter wrdev, iclass 26, count 0 2006.173.10:03:09.17#ibcon#first serial, iclass 26, count 0 2006.173.10:03:09.17#ibcon#enter sib2, iclass 26, count 0 2006.173.10:03:09.17#ibcon#flushed, iclass 26, count 0 2006.173.10:03:09.17#ibcon#about to write, iclass 26, count 0 2006.173.10:03:09.17#ibcon#wrote, iclass 26, count 0 2006.173.10:03:09.17#ibcon#about to read 3, iclass 26, count 0 2006.173.10:03:09.19#ibcon#read 3, iclass 26, count 0 2006.173.10:03:09.19#ibcon#about to read 4, iclass 26, count 0 2006.173.10:03:09.19#ibcon#read 4, iclass 26, count 0 2006.173.10:03:09.19#ibcon#about to read 5, iclass 26, count 0 2006.173.10:03:09.19#ibcon#read 5, iclass 26, count 0 2006.173.10:03:09.19#ibcon#about to read 6, iclass 26, count 0 2006.173.10:03:09.19#ibcon#read 6, iclass 26, count 0 2006.173.10:03:09.19#ibcon#end of sib2, iclass 26, count 0 2006.173.10:03:09.19#ibcon#*mode == 0, iclass 26, count 0 2006.173.10:03:09.19#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.10:03:09.19#ibcon#[25=USB\r\n] 2006.173.10:03:09.19#ibcon#*before write, iclass 26, count 0 2006.173.10:03:09.19#ibcon#enter sib2, iclass 26, count 0 2006.173.10:03:09.19#ibcon#flushed, iclass 26, count 0 2006.173.10:03:09.19#ibcon#about to write, iclass 26, count 0 2006.173.10:03:09.19#ibcon#wrote, iclass 26, count 0 2006.173.10:03:09.19#ibcon#about to read 3, iclass 26, count 0 2006.173.10:03:09.22#ibcon#read 3, iclass 26, count 0 2006.173.10:03:09.22#ibcon#about to read 4, iclass 26, count 0 2006.173.10:03:09.22#ibcon#read 4, iclass 26, count 0 2006.173.10:03:09.22#ibcon#about to read 5, iclass 26, count 0 2006.173.10:03:09.22#ibcon#read 5, iclass 26, count 0 2006.173.10:03:09.22#ibcon#about to read 6, iclass 26, count 0 2006.173.10:03:09.22#ibcon#read 6, iclass 26, count 0 2006.173.10:03:09.22#ibcon#end of sib2, iclass 26, count 0 2006.173.10:03:09.22#ibcon#*after write, iclass 26, count 0 2006.173.10:03:09.22#ibcon#*before return 0, iclass 26, count 0 2006.173.10:03:09.22#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.10:03:09.22#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.10:03:09.22#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.10:03:09.22#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.10:03:09.22$vck44/valo=4,624.99 2006.173.10:03:09.22#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.10:03:09.22#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.10:03:09.22#ibcon#ireg 17 cls_cnt 0 2006.173.10:03:09.22#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.10:03:09.22#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.10:03:09.22#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.10:03:09.22#ibcon#enter wrdev, iclass 28, count 0 2006.173.10:03:09.22#ibcon#first serial, iclass 28, count 0 2006.173.10:03:09.22#ibcon#enter sib2, iclass 28, count 0 2006.173.10:03:09.22#ibcon#flushed, iclass 28, count 0 2006.173.10:03:09.22#ibcon#about to write, iclass 28, count 0 2006.173.10:03:09.22#ibcon#wrote, iclass 28, count 0 2006.173.10:03:09.22#ibcon#about to read 3, iclass 28, count 0 2006.173.10:03:09.24#ibcon#read 3, iclass 28, count 0 2006.173.10:03:09.24#ibcon#about to read 4, iclass 28, count 0 2006.173.10:03:09.24#ibcon#read 4, iclass 28, count 0 2006.173.10:03:09.24#ibcon#about to read 5, iclass 28, count 0 2006.173.10:03:09.24#ibcon#read 5, iclass 28, count 0 2006.173.10:03:09.24#ibcon#about to read 6, iclass 28, count 0 2006.173.10:03:09.24#ibcon#read 6, iclass 28, count 0 2006.173.10:03:09.24#ibcon#end of sib2, iclass 28, count 0 2006.173.10:03:09.24#ibcon#*mode == 0, iclass 28, count 0 2006.173.10:03:09.24#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.10:03:09.24#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.10:03:09.24#ibcon#*before write, iclass 28, count 0 2006.173.10:03:09.24#ibcon#enter sib2, iclass 28, count 0 2006.173.10:03:09.24#ibcon#flushed, iclass 28, count 0 2006.173.10:03:09.24#ibcon#about to write, iclass 28, count 0 2006.173.10:03:09.24#ibcon#wrote, iclass 28, count 0 2006.173.10:03:09.24#ibcon#about to read 3, iclass 28, count 0 2006.173.10:03:09.28#ibcon#read 3, iclass 28, count 0 2006.173.10:03:09.28#ibcon#about to read 4, iclass 28, count 0 2006.173.10:03:09.28#ibcon#read 4, iclass 28, count 0 2006.173.10:03:09.28#ibcon#about to read 5, iclass 28, count 0 2006.173.10:03:09.28#ibcon#read 5, iclass 28, count 0 2006.173.10:03:09.28#ibcon#about to read 6, iclass 28, count 0 2006.173.10:03:09.28#ibcon#read 6, iclass 28, count 0 2006.173.10:03:09.28#ibcon#end of sib2, iclass 28, count 0 2006.173.10:03:09.28#ibcon#*after write, iclass 28, count 0 2006.173.10:03:09.28#ibcon#*before return 0, iclass 28, count 0 2006.173.10:03:09.28#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.10:03:09.28#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.10:03:09.28#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.10:03:09.28#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.10:03:09.28$vck44/va=4,6 2006.173.10:03:09.28#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.10:03:09.28#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.10:03:09.28#ibcon#ireg 11 cls_cnt 2 2006.173.10:03:09.28#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.10:03:09.34#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.10:03:09.34#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.10:03:09.34#ibcon#enter wrdev, iclass 30, count 2 2006.173.10:03:09.34#ibcon#first serial, iclass 30, count 2 2006.173.10:03:09.34#ibcon#enter sib2, iclass 30, count 2 2006.173.10:03:09.34#ibcon#flushed, iclass 30, count 2 2006.173.10:03:09.34#ibcon#about to write, iclass 30, count 2 2006.173.10:03:09.34#ibcon#wrote, iclass 30, count 2 2006.173.10:03:09.34#ibcon#about to read 3, iclass 30, count 2 2006.173.10:03:09.36#ibcon#read 3, iclass 30, count 2 2006.173.10:03:09.36#ibcon#about to read 4, iclass 30, count 2 2006.173.10:03:09.36#ibcon#read 4, iclass 30, count 2 2006.173.10:03:09.36#ibcon#about to read 5, iclass 30, count 2 2006.173.10:03:09.36#ibcon#read 5, iclass 30, count 2 2006.173.10:03:09.36#ibcon#about to read 6, iclass 30, count 2 2006.173.10:03:09.36#ibcon#read 6, iclass 30, count 2 2006.173.10:03:09.36#ibcon#end of sib2, iclass 30, count 2 2006.173.10:03:09.36#ibcon#*mode == 0, iclass 30, count 2 2006.173.10:03:09.36#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.10:03:09.36#ibcon#[25=AT04-06\r\n] 2006.173.10:03:09.36#ibcon#*before write, iclass 30, count 2 2006.173.10:03:09.36#ibcon#enter sib2, iclass 30, count 2 2006.173.10:03:09.36#ibcon#flushed, iclass 30, count 2 2006.173.10:03:09.36#ibcon#about to write, iclass 30, count 2 2006.173.10:03:09.36#ibcon#wrote, iclass 30, count 2 2006.173.10:03:09.36#ibcon#about to read 3, iclass 30, count 2 2006.173.10:03:09.39#ibcon#read 3, iclass 30, count 2 2006.173.10:03:09.39#ibcon#about to read 4, iclass 30, count 2 2006.173.10:03:09.39#ibcon#read 4, iclass 30, count 2 2006.173.10:03:09.39#ibcon#about to read 5, iclass 30, count 2 2006.173.10:03:09.39#ibcon#read 5, iclass 30, count 2 2006.173.10:03:09.39#ibcon#about to read 6, iclass 30, count 2 2006.173.10:03:09.39#ibcon#read 6, iclass 30, count 2 2006.173.10:03:09.39#ibcon#end of sib2, iclass 30, count 2 2006.173.10:03:09.39#ibcon#*after write, iclass 30, count 2 2006.173.10:03:09.39#ibcon#*before return 0, iclass 30, count 2 2006.173.10:03:09.39#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.10:03:09.39#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.10:03:09.39#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.10:03:09.39#ibcon#ireg 7 cls_cnt 0 2006.173.10:03:09.39#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.10:03:09.51#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.10:03:09.51#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.10:03:09.51#ibcon#enter wrdev, iclass 30, count 0 2006.173.10:03:09.51#ibcon#first serial, iclass 30, count 0 2006.173.10:03:09.51#ibcon#enter sib2, iclass 30, count 0 2006.173.10:03:09.51#ibcon#flushed, iclass 30, count 0 2006.173.10:03:09.51#ibcon#about to write, iclass 30, count 0 2006.173.10:03:09.51#ibcon#wrote, iclass 30, count 0 2006.173.10:03:09.51#ibcon#about to read 3, iclass 30, count 0 2006.173.10:03:09.53#ibcon#read 3, iclass 30, count 0 2006.173.10:03:09.53#ibcon#about to read 4, iclass 30, count 0 2006.173.10:03:09.53#ibcon#read 4, iclass 30, count 0 2006.173.10:03:09.53#ibcon#about to read 5, iclass 30, count 0 2006.173.10:03:09.53#ibcon#read 5, iclass 30, count 0 2006.173.10:03:09.53#ibcon#about to read 6, iclass 30, count 0 2006.173.10:03:09.53#ibcon#read 6, iclass 30, count 0 2006.173.10:03:09.53#ibcon#end of sib2, iclass 30, count 0 2006.173.10:03:09.53#ibcon#*mode == 0, iclass 30, count 0 2006.173.10:03:09.53#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.10:03:09.53#ibcon#[25=USB\r\n] 2006.173.10:03:09.53#ibcon#*before write, iclass 30, count 0 2006.173.10:03:09.53#ibcon#enter sib2, iclass 30, count 0 2006.173.10:03:09.53#ibcon#flushed, iclass 30, count 0 2006.173.10:03:09.53#ibcon#about to write, iclass 30, count 0 2006.173.10:03:09.53#ibcon#wrote, iclass 30, count 0 2006.173.10:03:09.53#ibcon#about to read 3, iclass 30, count 0 2006.173.10:03:09.56#ibcon#read 3, iclass 30, count 0 2006.173.10:03:09.56#ibcon#about to read 4, iclass 30, count 0 2006.173.10:03:09.56#ibcon#read 4, iclass 30, count 0 2006.173.10:03:09.56#ibcon#about to read 5, iclass 30, count 0 2006.173.10:03:09.56#ibcon#read 5, iclass 30, count 0 2006.173.10:03:09.56#ibcon#about to read 6, iclass 30, count 0 2006.173.10:03:09.56#ibcon#read 6, iclass 30, count 0 2006.173.10:03:09.56#ibcon#end of sib2, iclass 30, count 0 2006.173.10:03:09.56#ibcon#*after write, iclass 30, count 0 2006.173.10:03:09.56#ibcon#*before return 0, iclass 30, count 0 2006.173.10:03:09.56#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.10:03:09.56#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.10:03:09.56#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.10:03:09.56#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.10:03:09.56$vck44/valo=5,734.99 2006.173.10:03:09.56#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.10:03:09.56#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.10:03:09.56#ibcon#ireg 17 cls_cnt 0 2006.173.10:03:09.56#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.10:03:09.56#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.10:03:09.56#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.10:03:09.56#ibcon#enter wrdev, iclass 32, count 0 2006.173.10:03:09.56#ibcon#first serial, iclass 32, count 0 2006.173.10:03:09.56#ibcon#enter sib2, iclass 32, count 0 2006.173.10:03:09.56#ibcon#flushed, iclass 32, count 0 2006.173.10:03:09.56#ibcon#about to write, iclass 32, count 0 2006.173.10:03:09.56#ibcon#wrote, iclass 32, count 0 2006.173.10:03:09.56#ibcon#about to read 3, iclass 32, count 0 2006.173.10:03:09.58#ibcon#read 3, iclass 32, count 0 2006.173.10:03:09.58#ibcon#about to read 4, iclass 32, count 0 2006.173.10:03:09.58#ibcon#read 4, iclass 32, count 0 2006.173.10:03:09.58#ibcon#about to read 5, iclass 32, count 0 2006.173.10:03:09.58#ibcon#read 5, iclass 32, count 0 2006.173.10:03:09.58#ibcon#about to read 6, iclass 32, count 0 2006.173.10:03:09.58#ibcon#read 6, iclass 32, count 0 2006.173.10:03:09.58#ibcon#end of sib2, iclass 32, count 0 2006.173.10:03:09.58#ibcon#*mode == 0, iclass 32, count 0 2006.173.10:03:09.58#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.10:03:09.58#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.10:03:09.58#ibcon#*before write, iclass 32, count 0 2006.173.10:03:09.58#ibcon#enter sib2, iclass 32, count 0 2006.173.10:03:09.58#ibcon#flushed, iclass 32, count 0 2006.173.10:03:09.58#ibcon#about to write, iclass 32, count 0 2006.173.10:03:09.58#ibcon#wrote, iclass 32, count 0 2006.173.10:03:09.58#ibcon#about to read 3, iclass 32, count 0 2006.173.10:03:09.62#ibcon#read 3, iclass 32, count 0 2006.173.10:03:09.62#ibcon#about to read 4, iclass 32, count 0 2006.173.10:03:09.62#ibcon#read 4, iclass 32, count 0 2006.173.10:03:09.62#ibcon#about to read 5, iclass 32, count 0 2006.173.10:03:09.62#ibcon#read 5, iclass 32, count 0 2006.173.10:03:09.62#ibcon#about to read 6, iclass 32, count 0 2006.173.10:03:09.62#ibcon#read 6, iclass 32, count 0 2006.173.10:03:09.62#ibcon#end of sib2, iclass 32, count 0 2006.173.10:03:09.62#ibcon#*after write, iclass 32, count 0 2006.173.10:03:09.62#ibcon#*before return 0, iclass 32, count 0 2006.173.10:03:09.62#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.10:03:09.62#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.10:03:09.62#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.10:03:09.62#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.10:03:09.62$vck44/va=5,4 2006.173.10:03:09.62#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.10:03:09.62#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.10:03:09.62#ibcon#ireg 11 cls_cnt 2 2006.173.10:03:09.62#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.10:03:09.68#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.10:03:09.68#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.10:03:09.68#ibcon#enter wrdev, iclass 34, count 2 2006.173.10:03:09.68#ibcon#first serial, iclass 34, count 2 2006.173.10:03:09.68#ibcon#enter sib2, iclass 34, count 2 2006.173.10:03:09.68#ibcon#flushed, iclass 34, count 2 2006.173.10:03:09.68#ibcon#about to write, iclass 34, count 2 2006.173.10:03:09.68#ibcon#wrote, iclass 34, count 2 2006.173.10:03:09.68#ibcon#about to read 3, iclass 34, count 2 2006.173.10:03:09.70#ibcon#read 3, iclass 34, count 2 2006.173.10:03:09.70#ibcon#about to read 4, iclass 34, count 2 2006.173.10:03:09.70#ibcon#read 4, iclass 34, count 2 2006.173.10:03:09.70#ibcon#about to read 5, iclass 34, count 2 2006.173.10:03:09.70#ibcon#read 5, iclass 34, count 2 2006.173.10:03:09.70#ibcon#about to read 6, iclass 34, count 2 2006.173.10:03:09.70#ibcon#read 6, iclass 34, count 2 2006.173.10:03:09.70#ibcon#end of sib2, iclass 34, count 2 2006.173.10:03:09.70#ibcon#*mode == 0, iclass 34, count 2 2006.173.10:03:09.70#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.10:03:09.70#ibcon#[25=AT05-04\r\n] 2006.173.10:03:09.70#ibcon#*before write, iclass 34, count 2 2006.173.10:03:09.70#ibcon#enter sib2, iclass 34, count 2 2006.173.10:03:09.70#ibcon#flushed, iclass 34, count 2 2006.173.10:03:09.70#ibcon#about to write, iclass 34, count 2 2006.173.10:03:09.70#ibcon#wrote, iclass 34, count 2 2006.173.10:03:09.70#ibcon#about to read 3, iclass 34, count 2 2006.173.10:03:09.73#ibcon#read 3, iclass 34, count 2 2006.173.10:03:09.73#ibcon#about to read 4, iclass 34, count 2 2006.173.10:03:09.73#ibcon#read 4, iclass 34, count 2 2006.173.10:03:09.73#ibcon#about to read 5, iclass 34, count 2 2006.173.10:03:09.73#ibcon#read 5, iclass 34, count 2 2006.173.10:03:09.73#ibcon#about to read 6, iclass 34, count 2 2006.173.10:03:09.73#ibcon#read 6, iclass 34, count 2 2006.173.10:03:09.73#ibcon#end of sib2, iclass 34, count 2 2006.173.10:03:09.73#ibcon#*after write, iclass 34, count 2 2006.173.10:03:09.73#ibcon#*before return 0, iclass 34, count 2 2006.173.10:03:09.73#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.10:03:09.73#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.10:03:09.73#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.10:03:09.73#ibcon#ireg 7 cls_cnt 0 2006.173.10:03:09.73#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.10:03:09.85#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.10:03:09.85#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.10:03:09.85#ibcon#enter wrdev, iclass 34, count 0 2006.173.10:03:09.85#ibcon#first serial, iclass 34, count 0 2006.173.10:03:09.85#ibcon#enter sib2, iclass 34, count 0 2006.173.10:03:09.85#ibcon#flushed, iclass 34, count 0 2006.173.10:03:09.85#ibcon#about to write, iclass 34, count 0 2006.173.10:03:09.85#ibcon#wrote, iclass 34, count 0 2006.173.10:03:09.85#ibcon#about to read 3, iclass 34, count 0 2006.173.10:03:09.87#ibcon#read 3, iclass 34, count 0 2006.173.10:03:09.87#ibcon#about to read 4, iclass 34, count 0 2006.173.10:03:09.87#ibcon#read 4, iclass 34, count 0 2006.173.10:03:09.87#ibcon#about to read 5, iclass 34, count 0 2006.173.10:03:09.87#ibcon#read 5, iclass 34, count 0 2006.173.10:03:09.87#ibcon#about to read 6, iclass 34, count 0 2006.173.10:03:09.87#ibcon#read 6, iclass 34, count 0 2006.173.10:03:09.87#ibcon#end of sib2, iclass 34, count 0 2006.173.10:03:09.87#ibcon#*mode == 0, iclass 34, count 0 2006.173.10:03:09.87#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.10:03:09.87#ibcon#[25=USB\r\n] 2006.173.10:03:09.87#ibcon#*before write, iclass 34, count 0 2006.173.10:03:09.87#ibcon#enter sib2, iclass 34, count 0 2006.173.10:03:09.87#ibcon#flushed, iclass 34, count 0 2006.173.10:03:09.87#ibcon#about to write, iclass 34, count 0 2006.173.10:03:09.87#ibcon#wrote, iclass 34, count 0 2006.173.10:03:09.87#ibcon#about to read 3, iclass 34, count 0 2006.173.10:03:09.90#ibcon#read 3, iclass 34, count 0 2006.173.10:03:09.90#ibcon#about to read 4, iclass 34, count 0 2006.173.10:03:09.90#ibcon#read 4, iclass 34, count 0 2006.173.10:03:09.90#ibcon#about to read 5, iclass 34, count 0 2006.173.10:03:09.90#ibcon#read 5, iclass 34, count 0 2006.173.10:03:09.90#ibcon#about to read 6, iclass 34, count 0 2006.173.10:03:09.90#ibcon#read 6, iclass 34, count 0 2006.173.10:03:09.90#ibcon#end of sib2, iclass 34, count 0 2006.173.10:03:09.90#ibcon#*after write, iclass 34, count 0 2006.173.10:03:09.90#ibcon#*before return 0, iclass 34, count 0 2006.173.10:03:09.90#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.10:03:09.90#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.10:03:09.90#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.10:03:09.90#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.10:03:09.90$vck44/valo=6,814.99 2006.173.10:03:09.90#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.10:03:09.90#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.10:03:09.90#ibcon#ireg 17 cls_cnt 0 2006.173.10:03:09.90#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.10:03:09.90#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.10:03:09.90#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.10:03:09.90#ibcon#enter wrdev, iclass 36, count 0 2006.173.10:03:09.90#ibcon#first serial, iclass 36, count 0 2006.173.10:03:09.90#ibcon#enter sib2, iclass 36, count 0 2006.173.10:03:09.90#ibcon#flushed, iclass 36, count 0 2006.173.10:03:09.90#ibcon#about to write, iclass 36, count 0 2006.173.10:03:09.90#ibcon#wrote, iclass 36, count 0 2006.173.10:03:09.90#ibcon#about to read 3, iclass 36, count 0 2006.173.10:03:09.92#ibcon#read 3, iclass 36, count 0 2006.173.10:03:09.92#ibcon#about to read 4, iclass 36, count 0 2006.173.10:03:09.92#ibcon#read 4, iclass 36, count 0 2006.173.10:03:09.92#ibcon#about to read 5, iclass 36, count 0 2006.173.10:03:09.92#ibcon#read 5, iclass 36, count 0 2006.173.10:03:09.92#ibcon#about to read 6, iclass 36, count 0 2006.173.10:03:09.92#ibcon#read 6, iclass 36, count 0 2006.173.10:03:09.92#ibcon#end of sib2, iclass 36, count 0 2006.173.10:03:09.92#ibcon#*mode == 0, iclass 36, count 0 2006.173.10:03:09.92#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.10:03:09.92#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.10:03:09.92#ibcon#*before write, iclass 36, count 0 2006.173.10:03:09.92#ibcon#enter sib2, iclass 36, count 0 2006.173.10:03:09.92#ibcon#flushed, iclass 36, count 0 2006.173.10:03:09.92#ibcon#about to write, iclass 36, count 0 2006.173.10:03:09.92#ibcon#wrote, iclass 36, count 0 2006.173.10:03:09.92#ibcon#about to read 3, iclass 36, count 0 2006.173.10:03:09.96#ibcon#read 3, iclass 36, count 0 2006.173.10:03:09.96#ibcon#about to read 4, iclass 36, count 0 2006.173.10:03:09.96#ibcon#read 4, iclass 36, count 0 2006.173.10:03:09.96#ibcon#about to read 5, iclass 36, count 0 2006.173.10:03:09.96#ibcon#read 5, iclass 36, count 0 2006.173.10:03:09.96#ibcon#about to read 6, iclass 36, count 0 2006.173.10:03:09.96#ibcon#read 6, iclass 36, count 0 2006.173.10:03:09.96#ibcon#end of sib2, iclass 36, count 0 2006.173.10:03:09.96#ibcon#*after write, iclass 36, count 0 2006.173.10:03:09.96#ibcon#*before return 0, iclass 36, count 0 2006.173.10:03:09.96#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.10:03:09.96#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.10:03:09.96#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.10:03:09.96#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.10:03:09.96$vck44/va=6,3 2006.173.10:03:09.96#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.10:03:09.96#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.10:03:09.96#ibcon#ireg 11 cls_cnt 2 2006.173.10:03:09.96#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.10:03:10.02#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.10:03:10.02#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.10:03:10.02#ibcon#enter wrdev, iclass 38, count 2 2006.173.10:03:10.02#ibcon#first serial, iclass 38, count 2 2006.173.10:03:10.02#ibcon#enter sib2, iclass 38, count 2 2006.173.10:03:10.02#ibcon#flushed, iclass 38, count 2 2006.173.10:03:10.02#ibcon#about to write, iclass 38, count 2 2006.173.10:03:10.02#ibcon#wrote, iclass 38, count 2 2006.173.10:03:10.02#ibcon#about to read 3, iclass 38, count 2 2006.173.10:03:10.04#ibcon#read 3, iclass 38, count 2 2006.173.10:03:10.04#ibcon#about to read 4, iclass 38, count 2 2006.173.10:03:10.04#ibcon#read 4, iclass 38, count 2 2006.173.10:03:10.04#ibcon#about to read 5, iclass 38, count 2 2006.173.10:03:10.04#ibcon#read 5, iclass 38, count 2 2006.173.10:03:10.04#ibcon#about to read 6, iclass 38, count 2 2006.173.10:03:10.04#ibcon#read 6, iclass 38, count 2 2006.173.10:03:10.04#ibcon#end of sib2, iclass 38, count 2 2006.173.10:03:10.04#ibcon#*mode == 0, iclass 38, count 2 2006.173.10:03:10.04#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.10:03:10.04#ibcon#[25=AT06-03\r\n] 2006.173.10:03:10.04#ibcon#*before write, iclass 38, count 2 2006.173.10:03:10.04#ibcon#enter sib2, iclass 38, count 2 2006.173.10:03:10.04#ibcon#flushed, iclass 38, count 2 2006.173.10:03:10.04#ibcon#about to write, iclass 38, count 2 2006.173.10:03:10.04#ibcon#wrote, iclass 38, count 2 2006.173.10:03:10.04#ibcon#about to read 3, iclass 38, count 2 2006.173.10:03:10.07#ibcon#read 3, iclass 38, count 2 2006.173.10:03:10.07#ibcon#about to read 4, iclass 38, count 2 2006.173.10:03:10.07#ibcon#read 4, iclass 38, count 2 2006.173.10:03:10.07#ibcon#about to read 5, iclass 38, count 2 2006.173.10:03:10.07#ibcon#read 5, iclass 38, count 2 2006.173.10:03:10.07#ibcon#about to read 6, iclass 38, count 2 2006.173.10:03:10.07#ibcon#read 6, iclass 38, count 2 2006.173.10:03:10.07#ibcon#end of sib2, iclass 38, count 2 2006.173.10:03:10.07#ibcon#*after write, iclass 38, count 2 2006.173.10:03:10.07#ibcon#*before return 0, iclass 38, count 2 2006.173.10:03:10.07#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.10:03:10.07#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.10:03:10.07#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.10:03:10.07#ibcon#ireg 7 cls_cnt 0 2006.173.10:03:10.07#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.10:03:10.19#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.10:03:10.19#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.10:03:10.19#ibcon#enter wrdev, iclass 38, count 0 2006.173.10:03:10.19#ibcon#first serial, iclass 38, count 0 2006.173.10:03:10.19#ibcon#enter sib2, iclass 38, count 0 2006.173.10:03:10.19#ibcon#flushed, iclass 38, count 0 2006.173.10:03:10.19#ibcon#about to write, iclass 38, count 0 2006.173.10:03:10.19#ibcon#wrote, iclass 38, count 0 2006.173.10:03:10.19#ibcon#about to read 3, iclass 38, count 0 2006.173.10:03:10.21#ibcon#read 3, iclass 38, count 0 2006.173.10:03:10.21#ibcon#about to read 4, iclass 38, count 0 2006.173.10:03:10.21#ibcon#read 4, iclass 38, count 0 2006.173.10:03:10.21#ibcon#about to read 5, iclass 38, count 0 2006.173.10:03:10.21#ibcon#read 5, iclass 38, count 0 2006.173.10:03:10.21#ibcon#about to read 6, iclass 38, count 0 2006.173.10:03:10.21#ibcon#read 6, iclass 38, count 0 2006.173.10:03:10.21#ibcon#end of sib2, iclass 38, count 0 2006.173.10:03:10.21#ibcon#*mode == 0, iclass 38, count 0 2006.173.10:03:10.21#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.10:03:10.21#ibcon#[25=USB\r\n] 2006.173.10:03:10.21#ibcon#*before write, iclass 38, count 0 2006.173.10:03:10.21#ibcon#enter sib2, iclass 38, count 0 2006.173.10:03:10.21#ibcon#flushed, iclass 38, count 0 2006.173.10:03:10.21#ibcon#about to write, iclass 38, count 0 2006.173.10:03:10.21#ibcon#wrote, iclass 38, count 0 2006.173.10:03:10.21#ibcon#about to read 3, iclass 38, count 0 2006.173.10:03:10.24#ibcon#read 3, iclass 38, count 0 2006.173.10:03:10.24#ibcon#about to read 4, iclass 38, count 0 2006.173.10:03:10.24#ibcon#read 4, iclass 38, count 0 2006.173.10:03:10.24#ibcon#about to read 5, iclass 38, count 0 2006.173.10:03:10.24#ibcon#read 5, iclass 38, count 0 2006.173.10:03:10.24#ibcon#about to read 6, iclass 38, count 0 2006.173.10:03:10.24#ibcon#read 6, iclass 38, count 0 2006.173.10:03:10.24#ibcon#end of sib2, iclass 38, count 0 2006.173.10:03:10.24#ibcon#*after write, iclass 38, count 0 2006.173.10:03:10.24#ibcon#*before return 0, iclass 38, count 0 2006.173.10:03:10.24#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.10:03:10.24#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.10:03:10.24#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.10:03:10.24#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.10:03:10.24$vck44/valo=7,864.99 2006.173.10:03:10.24#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.10:03:10.24#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.10:03:10.24#ibcon#ireg 17 cls_cnt 0 2006.173.10:03:10.24#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.10:03:10.24#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.10:03:10.24#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.10:03:10.24#ibcon#enter wrdev, iclass 40, count 0 2006.173.10:03:10.24#ibcon#first serial, iclass 40, count 0 2006.173.10:03:10.24#ibcon#enter sib2, iclass 40, count 0 2006.173.10:03:10.24#ibcon#flushed, iclass 40, count 0 2006.173.10:03:10.24#ibcon#about to write, iclass 40, count 0 2006.173.10:03:10.24#ibcon#wrote, iclass 40, count 0 2006.173.10:03:10.24#ibcon#about to read 3, iclass 40, count 0 2006.173.10:03:10.26#ibcon#read 3, iclass 40, count 0 2006.173.10:03:10.26#ibcon#about to read 4, iclass 40, count 0 2006.173.10:03:10.26#ibcon#read 4, iclass 40, count 0 2006.173.10:03:10.26#ibcon#about to read 5, iclass 40, count 0 2006.173.10:03:10.26#ibcon#read 5, iclass 40, count 0 2006.173.10:03:10.26#ibcon#about to read 6, iclass 40, count 0 2006.173.10:03:10.26#ibcon#read 6, iclass 40, count 0 2006.173.10:03:10.26#ibcon#end of sib2, iclass 40, count 0 2006.173.10:03:10.26#ibcon#*mode == 0, iclass 40, count 0 2006.173.10:03:10.26#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.10:03:10.26#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.10:03:10.26#ibcon#*before write, iclass 40, count 0 2006.173.10:03:10.26#ibcon#enter sib2, iclass 40, count 0 2006.173.10:03:10.26#ibcon#flushed, iclass 40, count 0 2006.173.10:03:10.26#ibcon#about to write, iclass 40, count 0 2006.173.10:03:10.26#ibcon#wrote, iclass 40, count 0 2006.173.10:03:10.26#ibcon#about to read 3, iclass 40, count 0 2006.173.10:03:10.30#ibcon#read 3, iclass 40, count 0 2006.173.10:03:10.30#ibcon#about to read 4, iclass 40, count 0 2006.173.10:03:10.30#ibcon#read 4, iclass 40, count 0 2006.173.10:03:10.30#ibcon#about to read 5, iclass 40, count 0 2006.173.10:03:10.30#ibcon#read 5, iclass 40, count 0 2006.173.10:03:10.30#ibcon#about to read 6, iclass 40, count 0 2006.173.10:03:10.30#ibcon#read 6, iclass 40, count 0 2006.173.10:03:10.30#ibcon#end of sib2, iclass 40, count 0 2006.173.10:03:10.30#ibcon#*after write, iclass 40, count 0 2006.173.10:03:10.30#ibcon#*before return 0, iclass 40, count 0 2006.173.10:03:10.30#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.10:03:10.30#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.10:03:10.30#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.10:03:10.30#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.10:03:10.30$vck44/va=7,4 2006.173.10:03:10.30#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.10:03:10.30#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.10:03:10.30#ibcon#ireg 11 cls_cnt 2 2006.173.10:03:10.30#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.10:03:10.36#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.10:03:10.36#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.10:03:10.36#ibcon#enter wrdev, iclass 4, count 2 2006.173.10:03:10.36#ibcon#first serial, iclass 4, count 2 2006.173.10:03:10.36#ibcon#enter sib2, iclass 4, count 2 2006.173.10:03:10.36#ibcon#flushed, iclass 4, count 2 2006.173.10:03:10.36#ibcon#about to write, iclass 4, count 2 2006.173.10:03:10.36#ibcon#wrote, iclass 4, count 2 2006.173.10:03:10.36#ibcon#about to read 3, iclass 4, count 2 2006.173.10:03:10.38#ibcon#read 3, iclass 4, count 2 2006.173.10:03:10.38#ibcon#about to read 4, iclass 4, count 2 2006.173.10:03:10.38#ibcon#read 4, iclass 4, count 2 2006.173.10:03:10.38#ibcon#about to read 5, iclass 4, count 2 2006.173.10:03:10.38#ibcon#read 5, iclass 4, count 2 2006.173.10:03:10.38#ibcon#about to read 6, iclass 4, count 2 2006.173.10:03:10.38#ibcon#read 6, iclass 4, count 2 2006.173.10:03:10.38#ibcon#end of sib2, iclass 4, count 2 2006.173.10:03:10.38#ibcon#*mode == 0, iclass 4, count 2 2006.173.10:03:10.38#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.10:03:10.38#ibcon#[25=AT07-04\r\n] 2006.173.10:03:10.38#ibcon#*before write, iclass 4, count 2 2006.173.10:03:10.38#ibcon#enter sib2, iclass 4, count 2 2006.173.10:03:10.38#ibcon#flushed, iclass 4, count 2 2006.173.10:03:10.38#ibcon#about to write, iclass 4, count 2 2006.173.10:03:10.38#ibcon#wrote, iclass 4, count 2 2006.173.10:03:10.38#ibcon#about to read 3, iclass 4, count 2 2006.173.10:03:10.41#ibcon#read 3, iclass 4, count 2 2006.173.10:03:10.41#ibcon#about to read 4, iclass 4, count 2 2006.173.10:03:10.41#ibcon#read 4, iclass 4, count 2 2006.173.10:03:10.41#ibcon#about to read 5, iclass 4, count 2 2006.173.10:03:10.41#ibcon#read 5, iclass 4, count 2 2006.173.10:03:10.41#ibcon#about to read 6, iclass 4, count 2 2006.173.10:03:10.41#ibcon#read 6, iclass 4, count 2 2006.173.10:03:10.41#ibcon#end of sib2, iclass 4, count 2 2006.173.10:03:10.41#ibcon#*after write, iclass 4, count 2 2006.173.10:03:10.41#ibcon#*before return 0, iclass 4, count 2 2006.173.10:03:10.41#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.10:03:10.41#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.10:03:10.41#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.10:03:10.41#ibcon#ireg 7 cls_cnt 0 2006.173.10:03:10.41#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.10:03:10.53#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.10:03:10.53#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.10:03:10.53#ibcon#enter wrdev, iclass 4, count 0 2006.173.10:03:10.53#ibcon#first serial, iclass 4, count 0 2006.173.10:03:10.53#ibcon#enter sib2, iclass 4, count 0 2006.173.10:03:10.53#ibcon#flushed, iclass 4, count 0 2006.173.10:03:10.53#ibcon#about to write, iclass 4, count 0 2006.173.10:03:10.53#ibcon#wrote, iclass 4, count 0 2006.173.10:03:10.53#ibcon#about to read 3, iclass 4, count 0 2006.173.10:03:10.55#ibcon#read 3, iclass 4, count 0 2006.173.10:03:10.55#ibcon#about to read 4, iclass 4, count 0 2006.173.10:03:10.55#ibcon#read 4, iclass 4, count 0 2006.173.10:03:10.55#ibcon#about to read 5, iclass 4, count 0 2006.173.10:03:10.55#ibcon#read 5, iclass 4, count 0 2006.173.10:03:10.55#ibcon#about to read 6, iclass 4, count 0 2006.173.10:03:10.55#ibcon#read 6, iclass 4, count 0 2006.173.10:03:10.55#ibcon#end of sib2, iclass 4, count 0 2006.173.10:03:10.55#ibcon#*mode == 0, iclass 4, count 0 2006.173.10:03:10.55#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.10:03:10.55#ibcon#[25=USB\r\n] 2006.173.10:03:10.55#ibcon#*before write, iclass 4, count 0 2006.173.10:03:10.55#ibcon#enter sib2, iclass 4, count 0 2006.173.10:03:10.55#ibcon#flushed, iclass 4, count 0 2006.173.10:03:10.55#ibcon#about to write, iclass 4, count 0 2006.173.10:03:10.55#ibcon#wrote, iclass 4, count 0 2006.173.10:03:10.55#ibcon#about to read 3, iclass 4, count 0 2006.173.10:03:10.58#ibcon#read 3, iclass 4, count 0 2006.173.10:03:10.58#ibcon#about to read 4, iclass 4, count 0 2006.173.10:03:10.58#ibcon#read 4, iclass 4, count 0 2006.173.10:03:10.58#ibcon#about to read 5, iclass 4, count 0 2006.173.10:03:10.58#ibcon#read 5, iclass 4, count 0 2006.173.10:03:10.58#ibcon#about to read 6, iclass 4, count 0 2006.173.10:03:10.58#ibcon#read 6, iclass 4, count 0 2006.173.10:03:10.58#ibcon#end of sib2, iclass 4, count 0 2006.173.10:03:10.58#ibcon#*after write, iclass 4, count 0 2006.173.10:03:10.58#ibcon#*before return 0, iclass 4, count 0 2006.173.10:03:10.58#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.10:03:10.58#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.10:03:10.58#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.10:03:10.58#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.10:03:10.58$vck44/valo=8,884.99 2006.173.10:03:10.58#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.10:03:10.58#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.10:03:10.58#ibcon#ireg 17 cls_cnt 0 2006.173.10:03:10.58#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.10:03:10.58#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.10:03:10.58#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.10:03:10.58#ibcon#enter wrdev, iclass 6, count 0 2006.173.10:03:10.58#ibcon#first serial, iclass 6, count 0 2006.173.10:03:10.58#ibcon#enter sib2, iclass 6, count 0 2006.173.10:03:10.58#ibcon#flushed, iclass 6, count 0 2006.173.10:03:10.58#ibcon#about to write, iclass 6, count 0 2006.173.10:03:10.58#ibcon#wrote, iclass 6, count 0 2006.173.10:03:10.58#ibcon#about to read 3, iclass 6, count 0 2006.173.10:03:10.60#ibcon#read 3, iclass 6, count 0 2006.173.10:03:10.60#ibcon#about to read 4, iclass 6, count 0 2006.173.10:03:10.60#ibcon#read 4, iclass 6, count 0 2006.173.10:03:10.60#ibcon#about to read 5, iclass 6, count 0 2006.173.10:03:10.60#ibcon#read 5, iclass 6, count 0 2006.173.10:03:10.60#ibcon#about to read 6, iclass 6, count 0 2006.173.10:03:10.60#ibcon#read 6, iclass 6, count 0 2006.173.10:03:10.60#ibcon#end of sib2, iclass 6, count 0 2006.173.10:03:10.60#ibcon#*mode == 0, iclass 6, count 0 2006.173.10:03:10.60#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.10:03:10.60#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.10:03:10.60#ibcon#*before write, iclass 6, count 0 2006.173.10:03:10.60#ibcon#enter sib2, iclass 6, count 0 2006.173.10:03:10.60#ibcon#flushed, iclass 6, count 0 2006.173.10:03:10.60#ibcon#about to write, iclass 6, count 0 2006.173.10:03:10.60#ibcon#wrote, iclass 6, count 0 2006.173.10:03:10.60#ibcon#about to read 3, iclass 6, count 0 2006.173.10:03:10.64#ibcon#read 3, iclass 6, count 0 2006.173.10:03:10.64#ibcon#about to read 4, iclass 6, count 0 2006.173.10:03:10.64#ibcon#read 4, iclass 6, count 0 2006.173.10:03:10.64#ibcon#about to read 5, iclass 6, count 0 2006.173.10:03:10.64#ibcon#read 5, iclass 6, count 0 2006.173.10:03:10.64#ibcon#about to read 6, iclass 6, count 0 2006.173.10:03:10.64#ibcon#read 6, iclass 6, count 0 2006.173.10:03:10.64#ibcon#end of sib2, iclass 6, count 0 2006.173.10:03:10.64#ibcon#*after write, iclass 6, count 0 2006.173.10:03:10.64#ibcon#*before return 0, iclass 6, count 0 2006.173.10:03:10.64#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.10:03:10.64#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.10:03:10.64#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.10:03:10.64#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.10:03:10.64$vck44/va=8,4 2006.173.10:03:10.64#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.10:03:10.64#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.10:03:10.64#ibcon#ireg 11 cls_cnt 2 2006.173.10:03:10.64#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.10:03:10.70#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.10:03:10.70#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.10:03:10.70#ibcon#enter wrdev, iclass 10, count 2 2006.173.10:03:10.70#ibcon#first serial, iclass 10, count 2 2006.173.10:03:10.70#ibcon#enter sib2, iclass 10, count 2 2006.173.10:03:10.70#ibcon#flushed, iclass 10, count 2 2006.173.10:03:10.70#ibcon#about to write, iclass 10, count 2 2006.173.10:03:10.70#ibcon#wrote, iclass 10, count 2 2006.173.10:03:10.70#ibcon#about to read 3, iclass 10, count 2 2006.173.10:03:10.72#ibcon#read 3, iclass 10, count 2 2006.173.10:03:10.72#ibcon#about to read 4, iclass 10, count 2 2006.173.10:03:10.72#ibcon#read 4, iclass 10, count 2 2006.173.10:03:10.72#ibcon#about to read 5, iclass 10, count 2 2006.173.10:03:10.72#ibcon#read 5, iclass 10, count 2 2006.173.10:03:10.72#ibcon#about to read 6, iclass 10, count 2 2006.173.10:03:10.72#ibcon#read 6, iclass 10, count 2 2006.173.10:03:10.72#ibcon#end of sib2, iclass 10, count 2 2006.173.10:03:10.72#ibcon#*mode == 0, iclass 10, count 2 2006.173.10:03:10.72#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.10:03:10.72#ibcon#[25=AT08-04\r\n] 2006.173.10:03:10.72#ibcon#*before write, iclass 10, count 2 2006.173.10:03:10.72#ibcon#enter sib2, iclass 10, count 2 2006.173.10:03:10.72#ibcon#flushed, iclass 10, count 2 2006.173.10:03:10.72#ibcon#about to write, iclass 10, count 2 2006.173.10:03:10.72#ibcon#wrote, iclass 10, count 2 2006.173.10:03:10.72#ibcon#about to read 3, iclass 10, count 2 2006.173.10:03:10.75#ibcon#read 3, iclass 10, count 2 2006.173.10:03:10.75#ibcon#about to read 4, iclass 10, count 2 2006.173.10:03:10.75#ibcon#read 4, iclass 10, count 2 2006.173.10:03:10.75#ibcon#about to read 5, iclass 10, count 2 2006.173.10:03:10.75#ibcon#read 5, iclass 10, count 2 2006.173.10:03:10.75#ibcon#about to read 6, iclass 10, count 2 2006.173.10:03:10.75#ibcon#read 6, iclass 10, count 2 2006.173.10:03:10.75#ibcon#end of sib2, iclass 10, count 2 2006.173.10:03:10.75#ibcon#*after write, iclass 10, count 2 2006.173.10:03:10.75#ibcon#*before return 0, iclass 10, count 2 2006.173.10:03:10.75#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.10:03:10.75#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.10:03:10.75#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.10:03:10.75#ibcon#ireg 7 cls_cnt 0 2006.173.10:03:10.75#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.10:03:10.87#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.10:03:10.87#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.10:03:10.87#ibcon#enter wrdev, iclass 10, count 0 2006.173.10:03:10.87#ibcon#first serial, iclass 10, count 0 2006.173.10:03:10.87#ibcon#enter sib2, iclass 10, count 0 2006.173.10:03:10.87#ibcon#flushed, iclass 10, count 0 2006.173.10:03:10.87#ibcon#about to write, iclass 10, count 0 2006.173.10:03:10.87#ibcon#wrote, iclass 10, count 0 2006.173.10:03:10.87#ibcon#about to read 3, iclass 10, count 0 2006.173.10:03:10.89#ibcon#read 3, iclass 10, count 0 2006.173.10:03:10.89#ibcon#about to read 4, iclass 10, count 0 2006.173.10:03:10.89#ibcon#read 4, iclass 10, count 0 2006.173.10:03:10.89#ibcon#about to read 5, iclass 10, count 0 2006.173.10:03:10.89#ibcon#read 5, iclass 10, count 0 2006.173.10:03:10.89#ibcon#about to read 6, iclass 10, count 0 2006.173.10:03:10.89#ibcon#read 6, iclass 10, count 0 2006.173.10:03:10.89#ibcon#end of sib2, iclass 10, count 0 2006.173.10:03:10.89#ibcon#*mode == 0, iclass 10, count 0 2006.173.10:03:10.89#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.10:03:10.89#ibcon#[25=USB\r\n] 2006.173.10:03:10.89#ibcon#*before write, iclass 10, count 0 2006.173.10:03:10.89#ibcon#enter sib2, iclass 10, count 0 2006.173.10:03:10.89#ibcon#flushed, iclass 10, count 0 2006.173.10:03:10.89#ibcon#about to write, iclass 10, count 0 2006.173.10:03:10.89#ibcon#wrote, iclass 10, count 0 2006.173.10:03:10.89#ibcon#about to read 3, iclass 10, count 0 2006.173.10:03:10.92#ibcon#read 3, iclass 10, count 0 2006.173.10:03:10.92#ibcon#about to read 4, iclass 10, count 0 2006.173.10:03:10.92#ibcon#read 4, iclass 10, count 0 2006.173.10:03:10.92#ibcon#about to read 5, iclass 10, count 0 2006.173.10:03:10.92#ibcon#read 5, iclass 10, count 0 2006.173.10:03:10.92#ibcon#about to read 6, iclass 10, count 0 2006.173.10:03:10.92#ibcon#read 6, iclass 10, count 0 2006.173.10:03:10.92#ibcon#end of sib2, iclass 10, count 0 2006.173.10:03:10.92#ibcon#*after write, iclass 10, count 0 2006.173.10:03:10.92#ibcon#*before return 0, iclass 10, count 0 2006.173.10:03:10.92#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.10:03:10.92#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.10:03:10.92#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.10:03:10.92#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.10:03:10.92$vck44/vblo=1,629.99 2006.173.10:03:10.92#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.10:03:10.92#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.10:03:10.92#ibcon#ireg 17 cls_cnt 0 2006.173.10:03:10.92#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.10:03:10.92#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.10:03:10.92#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.10:03:10.92#ibcon#enter wrdev, iclass 12, count 0 2006.173.10:03:10.92#ibcon#first serial, iclass 12, count 0 2006.173.10:03:10.92#ibcon#enter sib2, iclass 12, count 0 2006.173.10:03:10.92#ibcon#flushed, iclass 12, count 0 2006.173.10:03:10.92#ibcon#about to write, iclass 12, count 0 2006.173.10:03:10.92#ibcon#wrote, iclass 12, count 0 2006.173.10:03:10.92#ibcon#about to read 3, iclass 12, count 0 2006.173.10:03:10.94#ibcon#read 3, iclass 12, count 0 2006.173.10:03:10.94#ibcon#about to read 4, iclass 12, count 0 2006.173.10:03:10.94#ibcon#read 4, iclass 12, count 0 2006.173.10:03:10.94#ibcon#about to read 5, iclass 12, count 0 2006.173.10:03:10.94#ibcon#read 5, iclass 12, count 0 2006.173.10:03:10.94#ibcon#about to read 6, iclass 12, count 0 2006.173.10:03:10.94#ibcon#read 6, iclass 12, count 0 2006.173.10:03:10.94#ibcon#end of sib2, iclass 12, count 0 2006.173.10:03:10.94#ibcon#*mode == 0, iclass 12, count 0 2006.173.10:03:10.94#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.10:03:10.94#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.10:03:10.94#ibcon#*before write, iclass 12, count 0 2006.173.10:03:10.94#ibcon#enter sib2, iclass 12, count 0 2006.173.10:03:10.94#ibcon#flushed, iclass 12, count 0 2006.173.10:03:10.94#ibcon#about to write, iclass 12, count 0 2006.173.10:03:10.94#ibcon#wrote, iclass 12, count 0 2006.173.10:03:10.94#ibcon#about to read 3, iclass 12, count 0 2006.173.10:03:10.98#ibcon#read 3, iclass 12, count 0 2006.173.10:03:10.98#ibcon#about to read 4, iclass 12, count 0 2006.173.10:03:10.98#ibcon#read 4, iclass 12, count 0 2006.173.10:03:10.98#ibcon#about to read 5, iclass 12, count 0 2006.173.10:03:10.98#ibcon#read 5, iclass 12, count 0 2006.173.10:03:10.98#ibcon#about to read 6, iclass 12, count 0 2006.173.10:03:10.98#ibcon#read 6, iclass 12, count 0 2006.173.10:03:10.98#ibcon#end of sib2, iclass 12, count 0 2006.173.10:03:10.98#ibcon#*after write, iclass 12, count 0 2006.173.10:03:10.98#ibcon#*before return 0, iclass 12, count 0 2006.173.10:03:10.98#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.10:03:10.98#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.10:03:10.98#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.10:03:10.98#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.10:03:10.98$vck44/vb=1,4 2006.173.10:03:10.98#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.10:03:10.98#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.10:03:10.98#ibcon#ireg 11 cls_cnt 2 2006.173.10:03:10.98#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.10:03:10.98#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.10:03:10.98#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.10:03:10.98#ibcon#enter wrdev, iclass 14, count 2 2006.173.10:03:10.98#ibcon#first serial, iclass 14, count 2 2006.173.10:03:10.98#ibcon#enter sib2, iclass 14, count 2 2006.173.10:03:10.98#ibcon#flushed, iclass 14, count 2 2006.173.10:03:10.98#ibcon#about to write, iclass 14, count 2 2006.173.10:03:10.98#ibcon#wrote, iclass 14, count 2 2006.173.10:03:10.98#ibcon#about to read 3, iclass 14, count 2 2006.173.10:03:11.00#ibcon#read 3, iclass 14, count 2 2006.173.10:03:11.00#ibcon#about to read 4, iclass 14, count 2 2006.173.10:03:11.00#ibcon#read 4, iclass 14, count 2 2006.173.10:03:11.00#ibcon#about to read 5, iclass 14, count 2 2006.173.10:03:11.00#ibcon#read 5, iclass 14, count 2 2006.173.10:03:11.00#ibcon#about to read 6, iclass 14, count 2 2006.173.10:03:11.00#ibcon#read 6, iclass 14, count 2 2006.173.10:03:11.00#ibcon#end of sib2, iclass 14, count 2 2006.173.10:03:11.00#ibcon#*mode == 0, iclass 14, count 2 2006.173.10:03:11.00#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.10:03:11.00#ibcon#[27=AT01-04\r\n] 2006.173.10:03:11.00#ibcon#*before write, iclass 14, count 2 2006.173.10:03:11.00#ibcon#enter sib2, iclass 14, count 2 2006.173.10:03:11.00#ibcon#flushed, iclass 14, count 2 2006.173.10:03:11.00#ibcon#about to write, iclass 14, count 2 2006.173.10:03:11.00#ibcon#wrote, iclass 14, count 2 2006.173.10:03:11.00#ibcon#about to read 3, iclass 14, count 2 2006.173.10:03:11.03#ibcon#read 3, iclass 14, count 2 2006.173.10:03:11.03#ibcon#about to read 4, iclass 14, count 2 2006.173.10:03:11.03#ibcon#read 4, iclass 14, count 2 2006.173.10:03:11.03#ibcon#about to read 5, iclass 14, count 2 2006.173.10:03:11.03#ibcon#read 5, iclass 14, count 2 2006.173.10:03:11.03#ibcon#about to read 6, iclass 14, count 2 2006.173.10:03:11.03#ibcon#read 6, iclass 14, count 2 2006.173.10:03:11.03#ibcon#end of sib2, iclass 14, count 2 2006.173.10:03:11.03#ibcon#*after write, iclass 14, count 2 2006.173.10:03:11.03#ibcon#*before return 0, iclass 14, count 2 2006.173.10:03:11.03#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.10:03:11.03#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.10:03:11.03#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.10:03:11.03#ibcon#ireg 7 cls_cnt 0 2006.173.10:03:11.03#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.10:03:11.15#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.10:03:11.15#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.10:03:11.15#ibcon#enter wrdev, iclass 14, count 0 2006.173.10:03:11.15#ibcon#first serial, iclass 14, count 0 2006.173.10:03:11.15#ibcon#enter sib2, iclass 14, count 0 2006.173.10:03:11.15#ibcon#flushed, iclass 14, count 0 2006.173.10:03:11.15#ibcon#about to write, iclass 14, count 0 2006.173.10:03:11.15#ibcon#wrote, iclass 14, count 0 2006.173.10:03:11.15#ibcon#about to read 3, iclass 14, count 0 2006.173.10:03:11.17#ibcon#read 3, iclass 14, count 0 2006.173.10:03:11.17#ibcon#about to read 4, iclass 14, count 0 2006.173.10:03:11.17#ibcon#read 4, iclass 14, count 0 2006.173.10:03:11.17#ibcon#about to read 5, iclass 14, count 0 2006.173.10:03:11.17#ibcon#read 5, iclass 14, count 0 2006.173.10:03:11.17#ibcon#about to read 6, iclass 14, count 0 2006.173.10:03:11.17#ibcon#read 6, iclass 14, count 0 2006.173.10:03:11.17#ibcon#end of sib2, iclass 14, count 0 2006.173.10:03:11.17#ibcon#*mode == 0, iclass 14, count 0 2006.173.10:03:11.17#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.10:03:11.17#ibcon#[27=USB\r\n] 2006.173.10:03:11.17#ibcon#*before write, iclass 14, count 0 2006.173.10:03:11.17#ibcon#enter sib2, iclass 14, count 0 2006.173.10:03:11.17#ibcon#flushed, iclass 14, count 0 2006.173.10:03:11.17#ibcon#about to write, iclass 14, count 0 2006.173.10:03:11.17#ibcon#wrote, iclass 14, count 0 2006.173.10:03:11.17#ibcon#about to read 3, iclass 14, count 0 2006.173.10:03:11.20#ibcon#read 3, iclass 14, count 0 2006.173.10:03:11.20#ibcon#about to read 4, iclass 14, count 0 2006.173.10:03:11.20#ibcon#read 4, iclass 14, count 0 2006.173.10:03:11.20#ibcon#about to read 5, iclass 14, count 0 2006.173.10:03:11.20#ibcon#read 5, iclass 14, count 0 2006.173.10:03:11.20#ibcon#about to read 6, iclass 14, count 0 2006.173.10:03:11.20#ibcon#read 6, iclass 14, count 0 2006.173.10:03:11.20#ibcon#end of sib2, iclass 14, count 0 2006.173.10:03:11.20#ibcon#*after write, iclass 14, count 0 2006.173.10:03:11.20#ibcon#*before return 0, iclass 14, count 0 2006.173.10:03:11.20#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.10:03:11.20#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.10:03:11.20#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.10:03:11.20#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.10:03:11.20$vck44/vblo=2,634.99 2006.173.10:03:11.20#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.10:03:11.20#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.10:03:11.20#ibcon#ireg 17 cls_cnt 0 2006.173.10:03:11.20#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.10:03:11.20#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.10:03:11.20#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.10:03:11.20#ibcon#enter wrdev, iclass 16, count 0 2006.173.10:03:11.20#ibcon#first serial, iclass 16, count 0 2006.173.10:03:11.20#ibcon#enter sib2, iclass 16, count 0 2006.173.10:03:11.20#ibcon#flushed, iclass 16, count 0 2006.173.10:03:11.20#ibcon#about to write, iclass 16, count 0 2006.173.10:03:11.20#ibcon#wrote, iclass 16, count 0 2006.173.10:03:11.20#ibcon#about to read 3, iclass 16, count 0 2006.173.10:03:11.22#ibcon#read 3, iclass 16, count 0 2006.173.10:03:11.22#ibcon#about to read 4, iclass 16, count 0 2006.173.10:03:11.22#ibcon#read 4, iclass 16, count 0 2006.173.10:03:11.22#ibcon#about to read 5, iclass 16, count 0 2006.173.10:03:11.22#ibcon#read 5, iclass 16, count 0 2006.173.10:03:11.22#ibcon#about to read 6, iclass 16, count 0 2006.173.10:03:11.22#ibcon#read 6, iclass 16, count 0 2006.173.10:03:11.22#ibcon#end of sib2, iclass 16, count 0 2006.173.10:03:11.22#ibcon#*mode == 0, iclass 16, count 0 2006.173.10:03:11.22#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.10:03:11.22#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.10:03:11.22#ibcon#*before write, iclass 16, count 0 2006.173.10:03:11.22#ibcon#enter sib2, iclass 16, count 0 2006.173.10:03:11.22#ibcon#flushed, iclass 16, count 0 2006.173.10:03:11.22#ibcon#about to write, iclass 16, count 0 2006.173.10:03:11.22#ibcon#wrote, iclass 16, count 0 2006.173.10:03:11.22#ibcon#about to read 3, iclass 16, count 0 2006.173.10:03:11.26#ibcon#read 3, iclass 16, count 0 2006.173.10:03:11.26#ibcon#about to read 4, iclass 16, count 0 2006.173.10:03:11.26#ibcon#read 4, iclass 16, count 0 2006.173.10:03:11.26#ibcon#about to read 5, iclass 16, count 0 2006.173.10:03:11.26#ibcon#read 5, iclass 16, count 0 2006.173.10:03:11.26#ibcon#about to read 6, iclass 16, count 0 2006.173.10:03:11.26#ibcon#read 6, iclass 16, count 0 2006.173.10:03:11.26#ibcon#end of sib2, iclass 16, count 0 2006.173.10:03:11.26#ibcon#*after write, iclass 16, count 0 2006.173.10:03:11.26#ibcon#*before return 0, iclass 16, count 0 2006.173.10:03:11.26#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.10:03:11.26#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.10:03:11.26#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.10:03:11.26#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.10:03:11.26$vck44/vb=2,4 2006.173.10:03:11.26#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.10:03:11.26#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.10:03:11.26#ibcon#ireg 11 cls_cnt 2 2006.173.10:03:11.26#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.10:03:11.32#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.10:03:11.32#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.10:03:11.32#ibcon#enter wrdev, iclass 18, count 2 2006.173.10:03:11.32#ibcon#first serial, iclass 18, count 2 2006.173.10:03:11.32#ibcon#enter sib2, iclass 18, count 2 2006.173.10:03:11.32#ibcon#flushed, iclass 18, count 2 2006.173.10:03:11.32#ibcon#about to write, iclass 18, count 2 2006.173.10:03:11.32#ibcon#wrote, iclass 18, count 2 2006.173.10:03:11.32#ibcon#about to read 3, iclass 18, count 2 2006.173.10:03:11.34#ibcon#read 3, iclass 18, count 2 2006.173.10:03:11.34#ibcon#about to read 4, iclass 18, count 2 2006.173.10:03:11.34#ibcon#read 4, iclass 18, count 2 2006.173.10:03:11.34#ibcon#about to read 5, iclass 18, count 2 2006.173.10:03:11.34#ibcon#read 5, iclass 18, count 2 2006.173.10:03:11.34#ibcon#about to read 6, iclass 18, count 2 2006.173.10:03:11.34#ibcon#read 6, iclass 18, count 2 2006.173.10:03:11.34#ibcon#end of sib2, iclass 18, count 2 2006.173.10:03:11.34#ibcon#*mode == 0, iclass 18, count 2 2006.173.10:03:11.34#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.10:03:11.34#ibcon#[27=AT02-04\r\n] 2006.173.10:03:11.34#ibcon#*before write, iclass 18, count 2 2006.173.10:03:11.34#ibcon#enter sib2, iclass 18, count 2 2006.173.10:03:11.34#ibcon#flushed, iclass 18, count 2 2006.173.10:03:11.34#ibcon#about to write, iclass 18, count 2 2006.173.10:03:11.34#ibcon#wrote, iclass 18, count 2 2006.173.10:03:11.34#ibcon#about to read 3, iclass 18, count 2 2006.173.10:03:11.37#ibcon#read 3, iclass 18, count 2 2006.173.10:03:11.37#ibcon#about to read 4, iclass 18, count 2 2006.173.10:03:11.37#ibcon#read 4, iclass 18, count 2 2006.173.10:03:11.37#ibcon#about to read 5, iclass 18, count 2 2006.173.10:03:11.37#ibcon#read 5, iclass 18, count 2 2006.173.10:03:11.37#ibcon#about to read 6, iclass 18, count 2 2006.173.10:03:11.37#ibcon#read 6, iclass 18, count 2 2006.173.10:03:11.37#ibcon#end of sib2, iclass 18, count 2 2006.173.10:03:11.37#ibcon#*after write, iclass 18, count 2 2006.173.10:03:11.37#ibcon#*before return 0, iclass 18, count 2 2006.173.10:03:11.37#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.10:03:11.37#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.10:03:11.37#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.10:03:11.37#ibcon#ireg 7 cls_cnt 0 2006.173.10:03:11.37#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.10:03:11.49#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.10:03:11.49#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.10:03:11.49#ibcon#enter wrdev, iclass 18, count 0 2006.173.10:03:11.49#ibcon#first serial, iclass 18, count 0 2006.173.10:03:11.49#ibcon#enter sib2, iclass 18, count 0 2006.173.10:03:11.49#ibcon#flushed, iclass 18, count 0 2006.173.10:03:11.49#ibcon#about to write, iclass 18, count 0 2006.173.10:03:11.49#ibcon#wrote, iclass 18, count 0 2006.173.10:03:11.49#ibcon#about to read 3, iclass 18, count 0 2006.173.10:03:11.51#ibcon#read 3, iclass 18, count 0 2006.173.10:03:11.51#ibcon#about to read 4, iclass 18, count 0 2006.173.10:03:11.51#ibcon#read 4, iclass 18, count 0 2006.173.10:03:11.51#ibcon#about to read 5, iclass 18, count 0 2006.173.10:03:11.51#ibcon#read 5, iclass 18, count 0 2006.173.10:03:11.51#ibcon#about to read 6, iclass 18, count 0 2006.173.10:03:11.51#ibcon#read 6, iclass 18, count 0 2006.173.10:03:11.51#ibcon#end of sib2, iclass 18, count 0 2006.173.10:03:11.51#ibcon#*mode == 0, iclass 18, count 0 2006.173.10:03:11.51#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.10:03:11.51#ibcon#[27=USB\r\n] 2006.173.10:03:11.51#ibcon#*before write, iclass 18, count 0 2006.173.10:03:11.51#ibcon#enter sib2, iclass 18, count 0 2006.173.10:03:11.51#ibcon#flushed, iclass 18, count 0 2006.173.10:03:11.51#ibcon#about to write, iclass 18, count 0 2006.173.10:03:11.51#ibcon#wrote, iclass 18, count 0 2006.173.10:03:11.51#ibcon#about to read 3, iclass 18, count 0 2006.173.10:03:11.54#ibcon#read 3, iclass 18, count 0 2006.173.10:03:11.54#ibcon#about to read 4, iclass 18, count 0 2006.173.10:03:11.54#ibcon#read 4, iclass 18, count 0 2006.173.10:03:11.54#ibcon#about to read 5, iclass 18, count 0 2006.173.10:03:11.54#ibcon#read 5, iclass 18, count 0 2006.173.10:03:11.54#ibcon#about to read 6, iclass 18, count 0 2006.173.10:03:11.54#ibcon#read 6, iclass 18, count 0 2006.173.10:03:11.54#ibcon#end of sib2, iclass 18, count 0 2006.173.10:03:11.54#ibcon#*after write, iclass 18, count 0 2006.173.10:03:11.54#ibcon#*before return 0, iclass 18, count 0 2006.173.10:03:11.54#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.10:03:11.54#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.10:03:11.54#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.10:03:11.54#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.10:03:11.54$vck44/vblo=3,649.99 2006.173.10:03:11.54#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.10:03:11.54#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.10:03:11.54#ibcon#ireg 17 cls_cnt 0 2006.173.10:03:11.54#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.10:03:11.54#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.10:03:11.54#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.10:03:11.54#ibcon#enter wrdev, iclass 20, count 0 2006.173.10:03:11.54#ibcon#first serial, iclass 20, count 0 2006.173.10:03:11.54#ibcon#enter sib2, iclass 20, count 0 2006.173.10:03:11.54#ibcon#flushed, iclass 20, count 0 2006.173.10:03:11.54#ibcon#about to write, iclass 20, count 0 2006.173.10:03:11.54#ibcon#wrote, iclass 20, count 0 2006.173.10:03:11.54#ibcon#about to read 3, iclass 20, count 0 2006.173.10:03:11.56#ibcon#read 3, iclass 20, count 0 2006.173.10:03:11.56#ibcon#about to read 4, iclass 20, count 0 2006.173.10:03:11.56#ibcon#read 4, iclass 20, count 0 2006.173.10:03:11.56#ibcon#about to read 5, iclass 20, count 0 2006.173.10:03:11.56#ibcon#read 5, iclass 20, count 0 2006.173.10:03:11.56#ibcon#about to read 6, iclass 20, count 0 2006.173.10:03:11.56#ibcon#read 6, iclass 20, count 0 2006.173.10:03:11.56#ibcon#end of sib2, iclass 20, count 0 2006.173.10:03:11.56#ibcon#*mode == 0, iclass 20, count 0 2006.173.10:03:11.56#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.10:03:11.56#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.10:03:11.56#ibcon#*before write, iclass 20, count 0 2006.173.10:03:11.56#ibcon#enter sib2, iclass 20, count 0 2006.173.10:03:11.56#ibcon#flushed, iclass 20, count 0 2006.173.10:03:11.56#ibcon#about to write, iclass 20, count 0 2006.173.10:03:11.56#ibcon#wrote, iclass 20, count 0 2006.173.10:03:11.56#ibcon#about to read 3, iclass 20, count 0 2006.173.10:03:11.60#ibcon#read 3, iclass 20, count 0 2006.173.10:03:11.60#ibcon#about to read 4, iclass 20, count 0 2006.173.10:03:11.60#ibcon#read 4, iclass 20, count 0 2006.173.10:03:11.60#ibcon#about to read 5, iclass 20, count 0 2006.173.10:03:11.60#ibcon#read 5, iclass 20, count 0 2006.173.10:03:11.60#ibcon#about to read 6, iclass 20, count 0 2006.173.10:03:11.60#ibcon#read 6, iclass 20, count 0 2006.173.10:03:11.60#ibcon#end of sib2, iclass 20, count 0 2006.173.10:03:11.60#ibcon#*after write, iclass 20, count 0 2006.173.10:03:11.60#ibcon#*before return 0, iclass 20, count 0 2006.173.10:03:11.60#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.10:03:11.60#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.10:03:11.60#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.10:03:11.60#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.10:03:11.60$vck44/vb=3,4 2006.173.10:03:11.60#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.10:03:11.60#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.10:03:11.60#ibcon#ireg 11 cls_cnt 2 2006.173.10:03:11.60#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.10:03:11.66#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.10:03:11.66#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.10:03:11.66#ibcon#enter wrdev, iclass 22, count 2 2006.173.10:03:11.66#ibcon#first serial, iclass 22, count 2 2006.173.10:03:11.66#ibcon#enter sib2, iclass 22, count 2 2006.173.10:03:11.66#ibcon#flushed, iclass 22, count 2 2006.173.10:03:11.66#ibcon#about to write, iclass 22, count 2 2006.173.10:03:11.66#ibcon#wrote, iclass 22, count 2 2006.173.10:03:11.66#ibcon#about to read 3, iclass 22, count 2 2006.173.10:03:11.68#ibcon#read 3, iclass 22, count 2 2006.173.10:03:11.68#ibcon#about to read 4, iclass 22, count 2 2006.173.10:03:11.68#ibcon#read 4, iclass 22, count 2 2006.173.10:03:11.68#ibcon#about to read 5, iclass 22, count 2 2006.173.10:03:11.68#ibcon#read 5, iclass 22, count 2 2006.173.10:03:11.68#ibcon#about to read 6, iclass 22, count 2 2006.173.10:03:11.68#ibcon#read 6, iclass 22, count 2 2006.173.10:03:11.68#ibcon#end of sib2, iclass 22, count 2 2006.173.10:03:11.68#ibcon#*mode == 0, iclass 22, count 2 2006.173.10:03:11.68#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.10:03:11.68#ibcon#[27=AT03-04\r\n] 2006.173.10:03:11.68#ibcon#*before write, iclass 22, count 2 2006.173.10:03:11.68#ibcon#enter sib2, iclass 22, count 2 2006.173.10:03:11.68#ibcon#flushed, iclass 22, count 2 2006.173.10:03:11.68#ibcon#about to write, iclass 22, count 2 2006.173.10:03:11.68#ibcon#wrote, iclass 22, count 2 2006.173.10:03:11.68#ibcon#about to read 3, iclass 22, count 2 2006.173.10:03:11.71#ibcon#read 3, iclass 22, count 2 2006.173.10:03:11.71#ibcon#about to read 4, iclass 22, count 2 2006.173.10:03:11.71#ibcon#read 4, iclass 22, count 2 2006.173.10:03:11.71#ibcon#about to read 5, iclass 22, count 2 2006.173.10:03:11.71#ibcon#read 5, iclass 22, count 2 2006.173.10:03:11.71#ibcon#about to read 6, iclass 22, count 2 2006.173.10:03:11.71#ibcon#read 6, iclass 22, count 2 2006.173.10:03:11.71#ibcon#end of sib2, iclass 22, count 2 2006.173.10:03:11.71#ibcon#*after write, iclass 22, count 2 2006.173.10:03:11.71#ibcon#*before return 0, iclass 22, count 2 2006.173.10:03:11.71#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.10:03:11.71#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.10:03:11.71#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.10:03:11.71#ibcon#ireg 7 cls_cnt 0 2006.173.10:03:11.71#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.10:03:11.83#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.10:03:11.83#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.10:03:11.83#ibcon#enter wrdev, iclass 22, count 0 2006.173.10:03:11.83#ibcon#first serial, iclass 22, count 0 2006.173.10:03:11.83#ibcon#enter sib2, iclass 22, count 0 2006.173.10:03:11.83#ibcon#flushed, iclass 22, count 0 2006.173.10:03:11.83#ibcon#about to write, iclass 22, count 0 2006.173.10:03:11.83#ibcon#wrote, iclass 22, count 0 2006.173.10:03:11.83#ibcon#about to read 3, iclass 22, count 0 2006.173.10:03:11.85#ibcon#read 3, iclass 22, count 0 2006.173.10:03:11.85#ibcon#about to read 4, iclass 22, count 0 2006.173.10:03:11.85#ibcon#read 4, iclass 22, count 0 2006.173.10:03:11.85#ibcon#about to read 5, iclass 22, count 0 2006.173.10:03:11.85#ibcon#read 5, iclass 22, count 0 2006.173.10:03:11.85#ibcon#about to read 6, iclass 22, count 0 2006.173.10:03:11.85#ibcon#read 6, iclass 22, count 0 2006.173.10:03:11.85#ibcon#end of sib2, iclass 22, count 0 2006.173.10:03:11.85#ibcon#*mode == 0, iclass 22, count 0 2006.173.10:03:11.85#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.10:03:11.85#ibcon#[27=USB\r\n] 2006.173.10:03:11.85#ibcon#*before write, iclass 22, count 0 2006.173.10:03:11.85#ibcon#enter sib2, iclass 22, count 0 2006.173.10:03:11.85#ibcon#flushed, iclass 22, count 0 2006.173.10:03:11.85#ibcon#about to write, iclass 22, count 0 2006.173.10:03:11.85#ibcon#wrote, iclass 22, count 0 2006.173.10:03:11.85#ibcon#about to read 3, iclass 22, count 0 2006.173.10:03:11.88#ibcon#read 3, iclass 22, count 0 2006.173.10:03:11.88#ibcon#about to read 4, iclass 22, count 0 2006.173.10:03:11.88#ibcon#read 4, iclass 22, count 0 2006.173.10:03:11.88#ibcon#about to read 5, iclass 22, count 0 2006.173.10:03:11.88#ibcon#read 5, iclass 22, count 0 2006.173.10:03:11.88#ibcon#about to read 6, iclass 22, count 0 2006.173.10:03:11.88#ibcon#read 6, iclass 22, count 0 2006.173.10:03:11.88#ibcon#end of sib2, iclass 22, count 0 2006.173.10:03:11.88#ibcon#*after write, iclass 22, count 0 2006.173.10:03:11.88#ibcon#*before return 0, iclass 22, count 0 2006.173.10:03:11.88#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.10:03:11.88#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.10:03:11.88#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.10:03:11.88#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.10:03:11.88$vck44/vblo=4,679.99 2006.173.10:03:11.88#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.10:03:11.88#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.10:03:11.88#ibcon#ireg 17 cls_cnt 0 2006.173.10:03:11.88#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.10:03:11.88#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.10:03:11.88#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.10:03:11.88#ibcon#enter wrdev, iclass 24, count 0 2006.173.10:03:11.88#ibcon#first serial, iclass 24, count 0 2006.173.10:03:11.88#ibcon#enter sib2, iclass 24, count 0 2006.173.10:03:11.88#ibcon#flushed, iclass 24, count 0 2006.173.10:03:11.88#ibcon#about to write, iclass 24, count 0 2006.173.10:03:11.88#ibcon#wrote, iclass 24, count 0 2006.173.10:03:11.88#ibcon#about to read 3, iclass 24, count 0 2006.173.10:03:11.90#ibcon#read 3, iclass 24, count 0 2006.173.10:03:11.90#ibcon#about to read 4, iclass 24, count 0 2006.173.10:03:11.90#ibcon#read 4, iclass 24, count 0 2006.173.10:03:11.90#ibcon#about to read 5, iclass 24, count 0 2006.173.10:03:11.90#ibcon#read 5, iclass 24, count 0 2006.173.10:03:11.90#ibcon#about to read 6, iclass 24, count 0 2006.173.10:03:11.90#ibcon#read 6, iclass 24, count 0 2006.173.10:03:11.90#ibcon#end of sib2, iclass 24, count 0 2006.173.10:03:11.90#ibcon#*mode == 0, iclass 24, count 0 2006.173.10:03:11.90#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.10:03:11.90#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.10:03:11.90#ibcon#*before write, iclass 24, count 0 2006.173.10:03:11.90#ibcon#enter sib2, iclass 24, count 0 2006.173.10:03:11.90#ibcon#flushed, iclass 24, count 0 2006.173.10:03:11.90#ibcon#about to write, iclass 24, count 0 2006.173.10:03:11.90#ibcon#wrote, iclass 24, count 0 2006.173.10:03:11.90#ibcon#about to read 3, iclass 24, count 0 2006.173.10:03:11.94#ibcon#read 3, iclass 24, count 0 2006.173.10:03:11.94#ibcon#about to read 4, iclass 24, count 0 2006.173.10:03:11.94#ibcon#read 4, iclass 24, count 0 2006.173.10:03:11.94#ibcon#about to read 5, iclass 24, count 0 2006.173.10:03:11.94#ibcon#read 5, iclass 24, count 0 2006.173.10:03:11.94#ibcon#about to read 6, iclass 24, count 0 2006.173.10:03:11.94#ibcon#read 6, iclass 24, count 0 2006.173.10:03:11.94#ibcon#end of sib2, iclass 24, count 0 2006.173.10:03:11.94#ibcon#*after write, iclass 24, count 0 2006.173.10:03:11.94#ibcon#*before return 0, iclass 24, count 0 2006.173.10:03:11.94#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.10:03:11.94#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.10:03:11.94#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.10:03:11.94#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.10:03:11.94$vck44/vb=4,4 2006.173.10:03:11.94#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.10:03:11.94#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.10:03:11.94#ibcon#ireg 11 cls_cnt 2 2006.173.10:03:11.94#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.10:03:12.00#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.10:03:12.00#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.10:03:12.00#ibcon#enter wrdev, iclass 26, count 2 2006.173.10:03:12.00#ibcon#first serial, iclass 26, count 2 2006.173.10:03:12.00#ibcon#enter sib2, iclass 26, count 2 2006.173.10:03:12.00#ibcon#flushed, iclass 26, count 2 2006.173.10:03:12.00#ibcon#about to write, iclass 26, count 2 2006.173.10:03:12.00#ibcon#wrote, iclass 26, count 2 2006.173.10:03:12.00#ibcon#about to read 3, iclass 26, count 2 2006.173.10:03:12.02#ibcon#read 3, iclass 26, count 2 2006.173.10:03:12.02#ibcon#about to read 4, iclass 26, count 2 2006.173.10:03:12.02#ibcon#read 4, iclass 26, count 2 2006.173.10:03:12.02#ibcon#about to read 5, iclass 26, count 2 2006.173.10:03:12.02#ibcon#read 5, iclass 26, count 2 2006.173.10:03:12.02#ibcon#about to read 6, iclass 26, count 2 2006.173.10:03:12.02#ibcon#read 6, iclass 26, count 2 2006.173.10:03:12.02#ibcon#end of sib2, iclass 26, count 2 2006.173.10:03:12.02#ibcon#*mode == 0, iclass 26, count 2 2006.173.10:03:12.02#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.10:03:12.02#ibcon#[27=AT04-04\r\n] 2006.173.10:03:12.02#ibcon#*before write, iclass 26, count 2 2006.173.10:03:12.02#ibcon#enter sib2, iclass 26, count 2 2006.173.10:03:12.02#ibcon#flushed, iclass 26, count 2 2006.173.10:03:12.02#ibcon#about to write, iclass 26, count 2 2006.173.10:03:12.02#ibcon#wrote, iclass 26, count 2 2006.173.10:03:12.02#ibcon#about to read 3, iclass 26, count 2 2006.173.10:03:12.05#ibcon#read 3, iclass 26, count 2 2006.173.10:03:12.05#ibcon#about to read 4, iclass 26, count 2 2006.173.10:03:12.05#ibcon#read 4, iclass 26, count 2 2006.173.10:03:12.05#ibcon#about to read 5, iclass 26, count 2 2006.173.10:03:12.05#ibcon#read 5, iclass 26, count 2 2006.173.10:03:12.05#ibcon#about to read 6, iclass 26, count 2 2006.173.10:03:12.05#ibcon#read 6, iclass 26, count 2 2006.173.10:03:12.05#ibcon#end of sib2, iclass 26, count 2 2006.173.10:03:12.05#ibcon#*after write, iclass 26, count 2 2006.173.10:03:12.05#ibcon#*before return 0, iclass 26, count 2 2006.173.10:03:12.05#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.10:03:12.05#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.10:03:12.05#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.10:03:12.05#ibcon#ireg 7 cls_cnt 0 2006.173.10:03:12.05#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.10:03:12.17#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.10:03:12.17#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.10:03:12.17#ibcon#enter wrdev, iclass 26, count 0 2006.173.10:03:12.17#ibcon#first serial, iclass 26, count 0 2006.173.10:03:12.17#ibcon#enter sib2, iclass 26, count 0 2006.173.10:03:12.17#ibcon#flushed, iclass 26, count 0 2006.173.10:03:12.17#ibcon#about to write, iclass 26, count 0 2006.173.10:03:12.17#ibcon#wrote, iclass 26, count 0 2006.173.10:03:12.17#ibcon#about to read 3, iclass 26, count 0 2006.173.10:03:12.19#ibcon#read 3, iclass 26, count 0 2006.173.10:03:12.19#ibcon#about to read 4, iclass 26, count 0 2006.173.10:03:12.19#ibcon#read 4, iclass 26, count 0 2006.173.10:03:12.19#ibcon#about to read 5, iclass 26, count 0 2006.173.10:03:12.19#ibcon#read 5, iclass 26, count 0 2006.173.10:03:12.19#ibcon#about to read 6, iclass 26, count 0 2006.173.10:03:12.19#ibcon#read 6, iclass 26, count 0 2006.173.10:03:12.19#ibcon#end of sib2, iclass 26, count 0 2006.173.10:03:12.19#ibcon#*mode == 0, iclass 26, count 0 2006.173.10:03:12.19#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.10:03:12.19#ibcon#[27=USB\r\n] 2006.173.10:03:12.19#ibcon#*before write, iclass 26, count 0 2006.173.10:03:12.19#ibcon#enter sib2, iclass 26, count 0 2006.173.10:03:12.19#ibcon#flushed, iclass 26, count 0 2006.173.10:03:12.19#ibcon#about to write, iclass 26, count 0 2006.173.10:03:12.19#ibcon#wrote, iclass 26, count 0 2006.173.10:03:12.19#ibcon#about to read 3, iclass 26, count 0 2006.173.10:03:12.22#ibcon#read 3, iclass 26, count 0 2006.173.10:03:12.22#ibcon#about to read 4, iclass 26, count 0 2006.173.10:03:12.22#ibcon#read 4, iclass 26, count 0 2006.173.10:03:12.22#ibcon#about to read 5, iclass 26, count 0 2006.173.10:03:12.22#ibcon#read 5, iclass 26, count 0 2006.173.10:03:12.22#ibcon#about to read 6, iclass 26, count 0 2006.173.10:03:12.22#ibcon#read 6, iclass 26, count 0 2006.173.10:03:12.22#ibcon#end of sib2, iclass 26, count 0 2006.173.10:03:12.22#ibcon#*after write, iclass 26, count 0 2006.173.10:03:12.22#ibcon#*before return 0, iclass 26, count 0 2006.173.10:03:12.22#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.10:03:12.22#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.10:03:12.22#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.10:03:12.22#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.10:03:12.22$vck44/vblo=5,709.99 2006.173.10:03:12.22#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.10:03:12.22#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.10:03:12.22#ibcon#ireg 17 cls_cnt 0 2006.173.10:03:12.22#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.10:03:12.22#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.10:03:12.22#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.10:03:12.22#ibcon#enter wrdev, iclass 28, count 0 2006.173.10:03:12.22#ibcon#first serial, iclass 28, count 0 2006.173.10:03:12.22#ibcon#enter sib2, iclass 28, count 0 2006.173.10:03:12.22#ibcon#flushed, iclass 28, count 0 2006.173.10:03:12.22#ibcon#about to write, iclass 28, count 0 2006.173.10:03:12.22#ibcon#wrote, iclass 28, count 0 2006.173.10:03:12.22#ibcon#about to read 3, iclass 28, count 0 2006.173.10:03:12.24#ibcon#read 3, iclass 28, count 0 2006.173.10:03:12.24#ibcon#about to read 4, iclass 28, count 0 2006.173.10:03:12.24#ibcon#read 4, iclass 28, count 0 2006.173.10:03:12.24#ibcon#about to read 5, iclass 28, count 0 2006.173.10:03:12.24#ibcon#read 5, iclass 28, count 0 2006.173.10:03:12.24#ibcon#about to read 6, iclass 28, count 0 2006.173.10:03:12.24#ibcon#read 6, iclass 28, count 0 2006.173.10:03:12.24#ibcon#end of sib2, iclass 28, count 0 2006.173.10:03:12.24#ibcon#*mode == 0, iclass 28, count 0 2006.173.10:03:12.24#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.10:03:12.24#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.10:03:12.24#ibcon#*before write, iclass 28, count 0 2006.173.10:03:12.24#ibcon#enter sib2, iclass 28, count 0 2006.173.10:03:12.24#ibcon#flushed, iclass 28, count 0 2006.173.10:03:12.24#ibcon#about to write, iclass 28, count 0 2006.173.10:03:12.24#ibcon#wrote, iclass 28, count 0 2006.173.10:03:12.24#ibcon#about to read 3, iclass 28, count 0 2006.173.10:03:12.28#ibcon#read 3, iclass 28, count 0 2006.173.10:03:12.28#ibcon#about to read 4, iclass 28, count 0 2006.173.10:03:12.28#ibcon#read 4, iclass 28, count 0 2006.173.10:03:12.28#ibcon#about to read 5, iclass 28, count 0 2006.173.10:03:12.28#ibcon#read 5, iclass 28, count 0 2006.173.10:03:12.28#ibcon#about to read 6, iclass 28, count 0 2006.173.10:03:12.28#ibcon#read 6, iclass 28, count 0 2006.173.10:03:12.28#ibcon#end of sib2, iclass 28, count 0 2006.173.10:03:12.28#ibcon#*after write, iclass 28, count 0 2006.173.10:03:12.28#ibcon#*before return 0, iclass 28, count 0 2006.173.10:03:12.28#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.10:03:12.28#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.10:03:12.28#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.10:03:12.28#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.10:03:12.28$vck44/vb=5,4 2006.173.10:03:12.28#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.10:03:12.28#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.10:03:12.28#ibcon#ireg 11 cls_cnt 2 2006.173.10:03:12.28#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.10:03:12.34#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.10:03:12.34#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.10:03:12.34#ibcon#enter wrdev, iclass 30, count 2 2006.173.10:03:12.34#ibcon#first serial, iclass 30, count 2 2006.173.10:03:12.34#ibcon#enter sib2, iclass 30, count 2 2006.173.10:03:12.34#ibcon#flushed, iclass 30, count 2 2006.173.10:03:12.34#ibcon#about to write, iclass 30, count 2 2006.173.10:03:12.34#ibcon#wrote, iclass 30, count 2 2006.173.10:03:12.34#ibcon#about to read 3, iclass 30, count 2 2006.173.10:03:12.36#ibcon#read 3, iclass 30, count 2 2006.173.10:03:12.36#ibcon#about to read 4, iclass 30, count 2 2006.173.10:03:12.36#ibcon#read 4, iclass 30, count 2 2006.173.10:03:12.36#ibcon#about to read 5, iclass 30, count 2 2006.173.10:03:12.36#ibcon#read 5, iclass 30, count 2 2006.173.10:03:12.36#ibcon#about to read 6, iclass 30, count 2 2006.173.10:03:12.36#ibcon#read 6, iclass 30, count 2 2006.173.10:03:12.36#ibcon#end of sib2, iclass 30, count 2 2006.173.10:03:12.36#ibcon#*mode == 0, iclass 30, count 2 2006.173.10:03:12.36#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.10:03:12.36#ibcon#[27=AT05-04\r\n] 2006.173.10:03:12.36#ibcon#*before write, iclass 30, count 2 2006.173.10:03:12.36#ibcon#enter sib2, iclass 30, count 2 2006.173.10:03:12.36#ibcon#flushed, iclass 30, count 2 2006.173.10:03:12.36#ibcon#about to write, iclass 30, count 2 2006.173.10:03:12.36#ibcon#wrote, iclass 30, count 2 2006.173.10:03:12.36#ibcon#about to read 3, iclass 30, count 2 2006.173.10:03:12.39#ibcon#read 3, iclass 30, count 2 2006.173.10:03:12.39#ibcon#about to read 4, iclass 30, count 2 2006.173.10:03:12.39#ibcon#read 4, iclass 30, count 2 2006.173.10:03:12.39#ibcon#about to read 5, iclass 30, count 2 2006.173.10:03:12.39#ibcon#read 5, iclass 30, count 2 2006.173.10:03:12.39#ibcon#about to read 6, iclass 30, count 2 2006.173.10:03:12.39#ibcon#read 6, iclass 30, count 2 2006.173.10:03:12.39#ibcon#end of sib2, iclass 30, count 2 2006.173.10:03:12.39#ibcon#*after write, iclass 30, count 2 2006.173.10:03:12.39#ibcon#*before return 0, iclass 30, count 2 2006.173.10:03:12.39#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.10:03:12.39#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.10:03:12.39#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.10:03:12.39#ibcon#ireg 7 cls_cnt 0 2006.173.10:03:12.39#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.10:03:12.51#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.10:03:12.51#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.10:03:12.51#ibcon#enter wrdev, iclass 30, count 0 2006.173.10:03:12.51#ibcon#first serial, iclass 30, count 0 2006.173.10:03:12.51#ibcon#enter sib2, iclass 30, count 0 2006.173.10:03:12.51#ibcon#flushed, iclass 30, count 0 2006.173.10:03:12.51#ibcon#about to write, iclass 30, count 0 2006.173.10:03:12.51#ibcon#wrote, iclass 30, count 0 2006.173.10:03:12.51#ibcon#about to read 3, iclass 30, count 0 2006.173.10:03:12.53#ibcon#read 3, iclass 30, count 0 2006.173.10:03:12.53#ibcon#about to read 4, iclass 30, count 0 2006.173.10:03:12.53#ibcon#read 4, iclass 30, count 0 2006.173.10:03:12.53#ibcon#about to read 5, iclass 30, count 0 2006.173.10:03:12.53#ibcon#read 5, iclass 30, count 0 2006.173.10:03:12.53#ibcon#about to read 6, iclass 30, count 0 2006.173.10:03:12.53#ibcon#read 6, iclass 30, count 0 2006.173.10:03:12.53#ibcon#end of sib2, iclass 30, count 0 2006.173.10:03:12.53#ibcon#*mode == 0, iclass 30, count 0 2006.173.10:03:12.53#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.10:03:12.53#ibcon#[27=USB\r\n] 2006.173.10:03:12.53#ibcon#*before write, iclass 30, count 0 2006.173.10:03:12.53#ibcon#enter sib2, iclass 30, count 0 2006.173.10:03:12.53#ibcon#flushed, iclass 30, count 0 2006.173.10:03:12.53#ibcon#about to write, iclass 30, count 0 2006.173.10:03:12.53#ibcon#wrote, iclass 30, count 0 2006.173.10:03:12.53#ibcon#about to read 3, iclass 30, count 0 2006.173.10:03:12.56#ibcon#read 3, iclass 30, count 0 2006.173.10:03:12.56#ibcon#about to read 4, iclass 30, count 0 2006.173.10:03:12.56#ibcon#read 4, iclass 30, count 0 2006.173.10:03:12.56#ibcon#about to read 5, iclass 30, count 0 2006.173.10:03:12.56#ibcon#read 5, iclass 30, count 0 2006.173.10:03:12.56#ibcon#about to read 6, iclass 30, count 0 2006.173.10:03:12.56#ibcon#read 6, iclass 30, count 0 2006.173.10:03:12.56#ibcon#end of sib2, iclass 30, count 0 2006.173.10:03:12.56#ibcon#*after write, iclass 30, count 0 2006.173.10:03:12.56#ibcon#*before return 0, iclass 30, count 0 2006.173.10:03:12.56#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.10:03:12.56#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.10:03:12.56#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.10:03:12.56#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.10:03:12.56$vck44/vblo=6,719.99 2006.173.10:03:12.56#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.10:03:12.56#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.10:03:12.56#ibcon#ireg 17 cls_cnt 0 2006.173.10:03:12.56#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.10:03:12.56#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.10:03:12.56#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.10:03:12.56#ibcon#enter wrdev, iclass 32, count 0 2006.173.10:03:12.56#ibcon#first serial, iclass 32, count 0 2006.173.10:03:12.56#ibcon#enter sib2, iclass 32, count 0 2006.173.10:03:12.56#ibcon#flushed, iclass 32, count 0 2006.173.10:03:12.56#ibcon#about to write, iclass 32, count 0 2006.173.10:03:12.56#ibcon#wrote, iclass 32, count 0 2006.173.10:03:12.56#ibcon#about to read 3, iclass 32, count 0 2006.173.10:03:12.58#ibcon#read 3, iclass 32, count 0 2006.173.10:03:12.58#ibcon#about to read 4, iclass 32, count 0 2006.173.10:03:12.58#ibcon#read 4, iclass 32, count 0 2006.173.10:03:12.58#ibcon#about to read 5, iclass 32, count 0 2006.173.10:03:12.58#ibcon#read 5, iclass 32, count 0 2006.173.10:03:12.58#ibcon#about to read 6, iclass 32, count 0 2006.173.10:03:12.58#ibcon#read 6, iclass 32, count 0 2006.173.10:03:12.58#ibcon#end of sib2, iclass 32, count 0 2006.173.10:03:12.58#ibcon#*mode == 0, iclass 32, count 0 2006.173.10:03:12.58#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.10:03:12.58#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.10:03:12.58#ibcon#*before write, iclass 32, count 0 2006.173.10:03:12.58#ibcon#enter sib2, iclass 32, count 0 2006.173.10:03:12.58#ibcon#flushed, iclass 32, count 0 2006.173.10:03:12.58#ibcon#about to write, iclass 32, count 0 2006.173.10:03:12.58#ibcon#wrote, iclass 32, count 0 2006.173.10:03:12.58#ibcon#about to read 3, iclass 32, count 0 2006.173.10:03:12.62#ibcon#read 3, iclass 32, count 0 2006.173.10:03:12.62#ibcon#about to read 4, iclass 32, count 0 2006.173.10:03:12.62#ibcon#read 4, iclass 32, count 0 2006.173.10:03:12.62#ibcon#about to read 5, iclass 32, count 0 2006.173.10:03:12.62#ibcon#read 5, iclass 32, count 0 2006.173.10:03:12.62#ibcon#about to read 6, iclass 32, count 0 2006.173.10:03:12.62#ibcon#read 6, iclass 32, count 0 2006.173.10:03:12.62#ibcon#end of sib2, iclass 32, count 0 2006.173.10:03:12.62#ibcon#*after write, iclass 32, count 0 2006.173.10:03:12.62#ibcon#*before return 0, iclass 32, count 0 2006.173.10:03:12.62#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.10:03:12.62#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.10:03:12.62#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.10:03:12.62#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.10:03:12.62$vck44/vb=6,4 2006.173.10:03:12.62#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.10:03:12.62#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.10:03:12.62#ibcon#ireg 11 cls_cnt 2 2006.173.10:03:12.62#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.10:03:12.68#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.10:03:12.68#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.10:03:12.68#ibcon#enter wrdev, iclass 34, count 2 2006.173.10:03:12.68#ibcon#first serial, iclass 34, count 2 2006.173.10:03:12.68#ibcon#enter sib2, iclass 34, count 2 2006.173.10:03:12.68#ibcon#flushed, iclass 34, count 2 2006.173.10:03:12.68#ibcon#about to write, iclass 34, count 2 2006.173.10:03:12.68#ibcon#wrote, iclass 34, count 2 2006.173.10:03:12.68#ibcon#about to read 3, iclass 34, count 2 2006.173.10:03:12.70#ibcon#read 3, iclass 34, count 2 2006.173.10:03:12.70#ibcon#about to read 4, iclass 34, count 2 2006.173.10:03:12.70#ibcon#read 4, iclass 34, count 2 2006.173.10:03:12.70#ibcon#about to read 5, iclass 34, count 2 2006.173.10:03:12.70#ibcon#read 5, iclass 34, count 2 2006.173.10:03:12.70#ibcon#about to read 6, iclass 34, count 2 2006.173.10:03:12.70#ibcon#read 6, iclass 34, count 2 2006.173.10:03:12.70#ibcon#end of sib2, iclass 34, count 2 2006.173.10:03:12.70#ibcon#*mode == 0, iclass 34, count 2 2006.173.10:03:12.70#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.10:03:12.70#ibcon#[27=AT06-04\r\n] 2006.173.10:03:12.70#ibcon#*before write, iclass 34, count 2 2006.173.10:03:12.70#ibcon#enter sib2, iclass 34, count 2 2006.173.10:03:12.70#ibcon#flushed, iclass 34, count 2 2006.173.10:03:12.70#ibcon#about to write, iclass 34, count 2 2006.173.10:03:12.70#ibcon#wrote, iclass 34, count 2 2006.173.10:03:12.70#ibcon#about to read 3, iclass 34, count 2 2006.173.10:03:12.73#ibcon#read 3, iclass 34, count 2 2006.173.10:03:12.73#ibcon#about to read 4, iclass 34, count 2 2006.173.10:03:12.73#ibcon#read 4, iclass 34, count 2 2006.173.10:03:12.73#ibcon#about to read 5, iclass 34, count 2 2006.173.10:03:12.73#ibcon#read 5, iclass 34, count 2 2006.173.10:03:12.73#ibcon#about to read 6, iclass 34, count 2 2006.173.10:03:12.73#ibcon#read 6, iclass 34, count 2 2006.173.10:03:12.73#ibcon#end of sib2, iclass 34, count 2 2006.173.10:03:12.73#ibcon#*after write, iclass 34, count 2 2006.173.10:03:12.73#ibcon#*before return 0, iclass 34, count 2 2006.173.10:03:12.73#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.10:03:12.73#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.10:03:12.73#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.10:03:12.73#ibcon#ireg 7 cls_cnt 0 2006.173.10:03:12.73#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.10:03:12.85#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.10:03:12.85#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.10:03:12.85#ibcon#enter wrdev, iclass 34, count 0 2006.173.10:03:12.85#ibcon#first serial, iclass 34, count 0 2006.173.10:03:12.85#ibcon#enter sib2, iclass 34, count 0 2006.173.10:03:12.85#ibcon#flushed, iclass 34, count 0 2006.173.10:03:12.85#ibcon#about to write, iclass 34, count 0 2006.173.10:03:12.85#ibcon#wrote, iclass 34, count 0 2006.173.10:03:12.85#ibcon#about to read 3, iclass 34, count 0 2006.173.10:03:12.87#ibcon#read 3, iclass 34, count 0 2006.173.10:03:12.87#ibcon#about to read 4, iclass 34, count 0 2006.173.10:03:12.87#ibcon#read 4, iclass 34, count 0 2006.173.10:03:12.87#ibcon#about to read 5, iclass 34, count 0 2006.173.10:03:12.87#ibcon#read 5, iclass 34, count 0 2006.173.10:03:12.87#ibcon#about to read 6, iclass 34, count 0 2006.173.10:03:12.87#ibcon#read 6, iclass 34, count 0 2006.173.10:03:12.87#ibcon#end of sib2, iclass 34, count 0 2006.173.10:03:12.87#ibcon#*mode == 0, iclass 34, count 0 2006.173.10:03:12.87#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.10:03:12.87#ibcon#[27=USB\r\n] 2006.173.10:03:12.87#ibcon#*before write, iclass 34, count 0 2006.173.10:03:12.87#ibcon#enter sib2, iclass 34, count 0 2006.173.10:03:12.87#ibcon#flushed, iclass 34, count 0 2006.173.10:03:12.87#ibcon#about to write, iclass 34, count 0 2006.173.10:03:12.87#ibcon#wrote, iclass 34, count 0 2006.173.10:03:12.87#ibcon#about to read 3, iclass 34, count 0 2006.173.10:03:12.90#ibcon#read 3, iclass 34, count 0 2006.173.10:03:12.90#ibcon#about to read 4, iclass 34, count 0 2006.173.10:03:12.90#ibcon#read 4, iclass 34, count 0 2006.173.10:03:12.90#ibcon#about to read 5, iclass 34, count 0 2006.173.10:03:12.90#ibcon#read 5, iclass 34, count 0 2006.173.10:03:12.90#ibcon#about to read 6, iclass 34, count 0 2006.173.10:03:12.90#ibcon#read 6, iclass 34, count 0 2006.173.10:03:12.90#ibcon#end of sib2, iclass 34, count 0 2006.173.10:03:12.90#ibcon#*after write, iclass 34, count 0 2006.173.10:03:12.90#ibcon#*before return 0, iclass 34, count 0 2006.173.10:03:12.90#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.10:03:12.90#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.10:03:12.90#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.10:03:12.90#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.10:03:12.90$vck44/vblo=7,734.99 2006.173.10:03:12.90#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.10:03:12.90#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.10:03:12.90#ibcon#ireg 17 cls_cnt 0 2006.173.10:03:12.90#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.10:03:12.90#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.10:03:12.90#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.10:03:12.90#ibcon#enter wrdev, iclass 36, count 0 2006.173.10:03:12.90#ibcon#first serial, iclass 36, count 0 2006.173.10:03:12.90#ibcon#enter sib2, iclass 36, count 0 2006.173.10:03:12.90#ibcon#flushed, iclass 36, count 0 2006.173.10:03:12.90#ibcon#about to write, iclass 36, count 0 2006.173.10:03:12.90#ibcon#wrote, iclass 36, count 0 2006.173.10:03:12.90#ibcon#about to read 3, iclass 36, count 0 2006.173.10:03:12.92#ibcon#read 3, iclass 36, count 0 2006.173.10:03:12.92#ibcon#about to read 4, iclass 36, count 0 2006.173.10:03:12.92#ibcon#read 4, iclass 36, count 0 2006.173.10:03:12.92#ibcon#about to read 5, iclass 36, count 0 2006.173.10:03:12.92#ibcon#read 5, iclass 36, count 0 2006.173.10:03:12.92#ibcon#about to read 6, iclass 36, count 0 2006.173.10:03:12.92#ibcon#read 6, iclass 36, count 0 2006.173.10:03:12.92#ibcon#end of sib2, iclass 36, count 0 2006.173.10:03:12.92#ibcon#*mode == 0, iclass 36, count 0 2006.173.10:03:12.92#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.10:03:12.92#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.10:03:12.92#ibcon#*before write, iclass 36, count 0 2006.173.10:03:12.92#ibcon#enter sib2, iclass 36, count 0 2006.173.10:03:12.92#ibcon#flushed, iclass 36, count 0 2006.173.10:03:12.92#ibcon#about to write, iclass 36, count 0 2006.173.10:03:12.92#ibcon#wrote, iclass 36, count 0 2006.173.10:03:12.92#ibcon#about to read 3, iclass 36, count 0 2006.173.10:03:12.96#ibcon#read 3, iclass 36, count 0 2006.173.10:03:12.96#ibcon#about to read 4, iclass 36, count 0 2006.173.10:03:12.96#ibcon#read 4, iclass 36, count 0 2006.173.10:03:12.96#ibcon#about to read 5, iclass 36, count 0 2006.173.10:03:12.96#ibcon#read 5, iclass 36, count 0 2006.173.10:03:12.96#ibcon#about to read 6, iclass 36, count 0 2006.173.10:03:12.96#ibcon#read 6, iclass 36, count 0 2006.173.10:03:12.96#ibcon#end of sib2, iclass 36, count 0 2006.173.10:03:12.96#ibcon#*after write, iclass 36, count 0 2006.173.10:03:12.96#ibcon#*before return 0, iclass 36, count 0 2006.173.10:03:12.96#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.10:03:12.96#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.10:03:12.96#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.10:03:12.96#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.10:03:12.96$vck44/vb=7,4 2006.173.10:03:12.96#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.10:03:12.96#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.10:03:12.96#ibcon#ireg 11 cls_cnt 2 2006.173.10:03:12.96#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.10:03:13.02#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.10:03:13.02#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.10:03:13.02#ibcon#enter wrdev, iclass 38, count 2 2006.173.10:03:13.02#ibcon#first serial, iclass 38, count 2 2006.173.10:03:13.02#ibcon#enter sib2, iclass 38, count 2 2006.173.10:03:13.02#ibcon#flushed, iclass 38, count 2 2006.173.10:03:13.02#ibcon#about to write, iclass 38, count 2 2006.173.10:03:13.02#ibcon#wrote, iclass 38, count 2 2006.173.10:03:13.02#ibcon#about to read 3, iclass 38, count 2 2006.173.10:03:13.04#ibcon#read 3, iclass 38, count 2 2006.173.10:03:13.04#ibcon#about to read 4, iclass 38, count 2 2006.173.10:03:13.04#ibcon#read 4, iclass 38, count 2 2006.173.10:03:13.04#ibcon#about to read 5, iclass 38, count 2 2006.173.10:03:13.04#ibcon#read 5, iclass 38, count 2 2006.173.10:03:13.04#ibcon#about to read 6, iclass 38, count 2 2006.173.10:03:13.04#ibcon#read 6, iclass 38, count 2 2006.173.10:03:13.04#ibcon#end of sib2, iclass 38, count 2 2006.173.10:03:13.04#ibcon#*mode == 0, iclass 38, count 2 2006.173.10:03:13.04#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.10:03:13.04#ibcon#[27=AT07-04\r\n] 2006.173.10:03:13.04#ibcon#*before write, iclass 38, count 2 2006.173.10:03:13.04#ibcon#enter sib2, iclass 38, count 2 2006.173.10:03:13.04#ibcon#flushed, iclass 38, count 2 2006.173.10:03:13.04#ibcon#about to write, iclass 38, count 2 2006.173.10:03:13.04#ibcon#wrote, iclass 38, count 2 2006.173.10:03:13.04#ibcon#about to read 3, iclass 38, count 2 2006.173.10:03:13.07#ibcon#read 3, iclass 38, count 2 2006.173.10:03:13.07#ibcon#about to read 4, iclass 38, count 2 2006.173.10:03:13.07#ibcon#read 4, iclass 38, count 2 2006.173.10:03:13.07#ibcon#about to read 5, iclass 38, count 2 2006.173.10:03:13.07#ibcon#read 5, iclass 38, count 2 2006.173.10:03:13.07#ibcon#about to read 6, iclass 38, count 2 2006.173.10:03:13.07#ibcon#read 6, iclass 38, count 2 2006.173.10:03:13.07#ibcon#end of sib2, iclass 38, count 2 2006.173.10:03:13.07#ibcon#*after write, iclass 38, count 2 2006.173.10:03:13.07#ibcon#*before return 0, iclass 38, count 2 2006.173.10:03:13.07#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.10:03:13.07#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.10:03:13.07#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.10:03:13.07#ibcon#ireg 7 cls_cnt 0 2006.173.10:03:13.07#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.10:03:13.19#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.10:03:13.19#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.10:03:13.19#ibcon#enter wrdev, iclass 38, count 0 2006.173.10:03:13.19#ibcon#first serial, iclass 38, count 0 2006.173.10:03:13.19#ibcon#enter sib2, iclass 38, count 0 2006.173.10:03:13.19#ibcon#flushed, iclass 38, count 0 2006.173.10:03:13.19#ibcon#about to write, iclass 38, count 0 2006.173.10:03:13.19#ibcon#wrote, iclass 38, count 0 2006.173.10:03:13.19#ibcon#about to read 3, iclass 38, count 0 2006.173.10:03:13.21#ibcon#read 3, iclass 38, count 0 2006.173.10:03:13.21#ibcon#about to read 4, iclass 38, count 0 2006.173.10:03:13.21#ibcon#read 4, iclass 38, count 0 2006.173.10:03:13.21#ibcon#about to read 5, iclass 38, count 0 2006.173.10:03:13.21#ibcon#read 5, iclass 38, count 0 2006.173.10:03:13.21#ibcon#about to read 6, iclass 38, count 0 2006.173.10:03:13.21#ibcon#read 6, iclass 38, count 0 2006.173.10:03:13.21#ibcon#end of sib2, iclass 38, count 0 2006.173.10:03:13.21#ibcon#*mode == 0, iclass 38, count 0 2006.173.10:03:13.21#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.10:03:13.21#ibcon#[27=USB\r\n] 2006.173.10:03:13.21#ibcon#*before write, iclass 38, count 0 2006.173.10:03:13.21#ibcon#enter sib2, iclass 38, count 0 2006.173.10:03:13.21#ibcon#flushed, iclass 38, count 0 2006.173.10:03:13.21#ibcon#about to write, iclass 38, count 0 2006.173.10:03:13.21#ibcon#wrote, iclass 38, count 0 2006.173.10:03:13.21#ibcon#about to read 3, iclass 38, count 0 2006.173.10:03:13.24#ibcon#read 3, iclass 38, count 0 2006.173.10:03:13.24#ibcon#about to read 4, iclass 38, count 0 2006.173.10:03:13.24#ibcon#read 4, iclass 38, count 0 2006.173.10:03:13.24#ibcon#about to read 5, iclass 38, count 0 2006.173.10:03:13.24#ibcon#read 5, iclass 38, count 0 2006.173.10:03:13.24#ibcon#about to read 6, iclass 38, count 0 2006.173.10:03:13.24#ibcon#read 6, iclass 38, count 0 2006.173.10:03:13.24#ibcon#end of sib2, iclass 38, count 0 2006.173.10:03:13.24#ibcon#*after write, iclass 38, count 0 2006.173.10:03:13.24#ibcon#*before return 0, iclass 38, count 0 2006.173.10:03:13.24#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.10:03:13.24#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.10:03:13.24#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.10:03:13.24#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.10:03:13.24$vck44/vblo=8,744.99 2006.173.10:03:13.24#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.10:03:13.24#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.10:03:13.24#ibcon#ireg 17 cls_cnt 0 2006.173.10:03:13.24#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.10:03:13.24#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.10:03:13.24#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.10:03:13.24#ibcon#enter wrdev, iclass 40, count 0 2006.173.10:03:13.24#ibcon#first serial, iclass 40, count 0 2006.173.10:03:13.24#ibcon#enter sib2, iclass 40, count 0 2006.173.10:03:13.24#ibcon#flushed, iclass 40, count 0 2006.173.10:03:13.24#ibcon#about to write, iclass 40, count 0 2006.173.10:03:13.24#ibcon#wrote, iclass 40, count 0 2006.173.10:03:13.24#ibcon#about to read 3, iclass 40, count 0 2006.173.10:03:13.26#ibcon#read 3, iclass 40, count 0 2006.173.10:03:13.26#ibcon#about to read 4, iclass 40, count 0 2006.173.10:03:13.26#ibcon#read 4, iclass 40, count 0 2006.173.10:03:13.26#ibcon#about to read 5, iclass 40, count 0 2006.173.10:03:13.26#ibcon#read 5, iclass 40, count 0 2006.173.10:03:13.26#ibcon#about to read 6, iclass 40, count 0 2006.173.10:03:13.26#ibcon#read 6, iclass 40, count 0 2006.173.10:03:13.26#ibcon#end of sib2, iclass 40, count 0 2006.173.10:03:13.26#ibcon#*mode == 0, iclass 40, count 0 2006.173.10:03:13.26#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.10:03:13.26#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.10:03:13.26#ibcon#*before write, iclass 40, count 0 2006.173.10:03:13.26#ibcon#enter sib2, iclass 40, count 0 2006.173.10:03:13.26#ibcon#flushed, iclass 40, count 0 2006.173.10:03:13.26#ibcon#about to write, iclass 40, count 0 2006.173.10:03:13.26#ibcon#wrote, iclass 40, count 0 2006.173.10:03:13.26#ibcon#about to read 3, iclass 40, count 0 2006.173.10:03:13.30#ibcon#read 3, iclass 40, count 0 2006.173.10:03:13.30#ibcon#about to read 4, iclass 40, count 0 2006.173.10:03:13.30#ibcon#read 4, iclass 40, count 0 2006.173.10:03:13.30#ibcon#about to read 5, iclass 40, count 0 2006.173.10:03:13.30#ibcon#read 5, iclass 40, count 0 2006.173.10:03:13.30#ibcon#about to read 6, iclass 40, count 0 2006.173.10:03:13.30#ibcon#read 6, iclass 40, count 0 2006.173.10:03:13.30#ibcon#end of sib2, iclass 40, count 0 2006.173.10:03:13.30#ibcon#*after write, iclass 40, count 0 2006.173.10:03:13.30#ibcon#*before return 0, iclass 40, count 0 2006.173.10:03:13.30#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.10:03:13.30#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.10:03:13.30#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.10:03:13.30#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.10:03:13.30$vck44/vb=8,4 2006.173.10:03:13.30#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.10:03:13.30#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.10:03:13.30#ibcon#ireg 11 cls_cnt 2 2006.173.10:03:13.30#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.10:03:13.36#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.10:03:13.36#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.10:03:13.36#ibcon#enter wrdev, iclass 4, count 2 2006.173.10:03:13.36#ibcon#first serial, iclass 4, count 2 2006.173.10:03:13.36#ibcon#enter sib2, iclass 4, count 2 2006.173.10:03:13.36#ibcon#flushed, iclass 4, count 2 2006.173.10:03:13.36#ibcon#about to write, iclass 4, count 2 2006.173.10:03:13.36#ibcon#wrote, iclass 4, count 2 2006.173.10:03:13.36#ibcon#about to read 3, iclass 4, count 2 2006.173.10:03:13.38#ibcon#read 3, iclass 4, count 2 2006.173.10:03:13.38#ibcon#about to read 4, iclass 4, count 2 2006.173.10:03:13.38#ibcon#read 4, iclass 4, count 2 2006.173.10:03:13.38#ibcon#about to read 5, iclass 4, count 2 2006.173.10:03:13.38#ibcon#read 5, iclass 4, count 2 2006.173.10:03:13.38#ibcon#about to read 6, iclass 4, count 2 2006.173.10:03:13.38#ibcon#read 6, iclass 4, count 2 2006.173.10:03:13.38#ibcon#end of sib2, iclass 4, count 2 2006.173.10:03:13.38#ibcon#*mode == 0, iclass 4, count 2 2006.173.10:03:13.38#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.10:03:13.38#ibcon#[27=AT08-04\r\n] 2006.173.10:03:13.38#ibcon#*before write, iclass 4, count 2 2006.173.10:03:13.38#ibcon#enter sib2, iclass 4, count 2 2006.173.10:03:13.38#ibcon#flushed, iclass 4, count 2 2006.173.10:03:13.38#ibcon#about to write, iclass 4, count 2 2006.173.10:03:13.38#ibcon#wrote, iclass 4, count 2 2006.173.10:03:13.38#ibcon#about to read 3, iclass 4, count 2 2006.173.10:03:13.41#ibcon#read 3, iclass 4, count 2 2006.173.10:03:13.41#ibcon#about to read 4, iclass 4, count 2 2006.173.10:03:13.41#ibcon#read 4, iclass 4, count 2 2006.173.10:03:13.41#ibcon#about to read 5, iclass 4, count 2 2006.173.10:03:13.41#ibcon#read 5, iclass 4, count 2 2006.173.10:03:13.41#ibcon#about to read 6, iclass 4, count 2 2006.173.10:03:13.41#ibcon#read 6, iclass 4, count 2 2006.173.10:03:13.41#ibcon#end of sib2, iclass 4, count 2 2006.173.10:03:13.41#ibcon#*after write, iclass 4, count 2 2006.173.10:03:13.41#ibcon#*before return 0, iclass 4, count 2 2006.173.10:03:13.41#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.10:03:13.41#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.10:03:13.41#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.10:03:13.41#ibcon#ireg 7 cls_cnt 0 2006.173.10:03:13.41#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.10:03:13.53#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.10:03:13.53#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.10:03:13.53#ibcon#enter wrdev, iclass 4, count 0 2006.173.10:03:13.53#ibcon#first serial, iclass 4, count 0 2006.173.10:03:13.53#ibcon#enter sib2, iclass 4, count 0 2006.173.10:03:13.53#ibcon#flushed, iclass 4, count 0 2006.173.10:03:13.53#ibcon#about to write, iclass 4, count 0 2006.173.10:03:13.53#ibcon#wrote, iclass 4, count 0 2006.173.10:03:13.53#ibcon#about to read 3, iclass 4, count 0 2006.173.10:03:13.55#ibcon#read 3, iclass 4, count 0 2006.173.10:03:13.55#ibcon#about to read 4, iclass 4, count 0 2006.173.10:03:13.55#ibcon#read 4, iclass 4, count 0 2006.173.10:03:13.55#ibcon#about to read 5, iclass 4, count 0 2006.173.10:03:13.55#ibcon#read 5, iclass 4, count 0 2006.173.10:03:13.55#ibcon#about to read 6, iclass 4, count 0 2006.173.10:03:13.55#ibcon#read 6, iclass 4, count 0 2006.173.10:03:13.55#ibcon#end of sib2, iclass 4, count 0 2006.173.10:03:13.55#ibcon#*mode == 0, iclass 4, count 0 2006.173.10:03:13.55#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.10:03:13.55#ibcon#[27=USB\r\n] 2006.173.10:03:13.55#ibcon#*before write, iclass 4, count 0 2006.173.10:03:13.55#ibcon#enter sib2, iclass 4, count 0 2006.173.10:03:13.55#ibcon#flushed, iclass 4, count 0 2006.173.10:03:13.55#ibcon#about to write, iclass 4, count 0 2006.173.10:03:13.55#ibcon#wrote, iclass 4, count 0 2006.173.10:03:13.55#ibcon#about to read 3, iclass 4, count 0 2006.173.10:03:13.58#ibcon#read 3, iclass 4, count 0 2006.173.10:03:13.58#ibcon#about to read 4, iclass 4, count 0 2006.173.10:03:13.58#ibcon#read 4, iclass 4, count 0 2006.173.10:03:13.58#ibcon#about to read 5, iclass 4, count 0 2006.173.10:03:13.58#ibcon#read 5, iclass 4, count 0 2006.173.10:03:13.58#ibcon#about to read 6, iclass 4, count 0 2006.173.10:03:13.58#ibcon#read 6, iclass 4, count 0 2006.173.10:03:13.58#ibcon#end of sib2, iclass 4, count 0 2006.173.10:03:13.58#ibcon#*after write, iclass 4, count 0 2006.173.10:03:13.58#ibcon#*before return 0, iclass 4, count 0 2006.173.10:03:13.58#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.10:03:13.58#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.10:03:13.58#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.10:03:13.58#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.10:03:13.58$vck44/vabw=wide 2006.173.10:03:13.58#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.10:03:13.58#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.10:03:13.58#ibcon#ireg 8 cls_cnt 0 2006.173.10:03:13.58#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.10:03:13.58#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.10:03:13.58#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.10:03:13.58#ibcon#enter wrdev, iclass 6, count 0 2006.173.10:03:13.58#ibcon#first serial, iclass 6, count 0 2006.173.10:03:13.58#ibcon#enter sib2, iclass 6, count 0 2006.173.10:03:13.58#ibcon#flushed, iclass 6, count 0 2006.173.10:03:13.58#ibcon#about to write, iclass 6, count 0 2006.173.10:03:13.58#ibcon#wrote, iclass 6, count 0 2006.173.10:03:13.58#ibcon#about to read 3, iclass 6, count 0 2006.173.10:03:13.60#ibcon#read 3, iclass 6, count 0 2006.173.10:03:13.60#ibcon#about to read 4, iclass 6, count 0 2006.173.10:03:13.60#ibcon#read 4, iclass 6, count 0 2006.173.10:03:13.60#ibcon#about to read 5, iclass 6, count 0 2006.173.10:03:13.60#ibcon#read 5, iclass 6, count 0 2006.173.10:03:13.60#ibcon#about to read 6, iclass 6, count 0 2006.173.10:03:13.60#ibcon#read 6, iclass 6, count 0 2006.173.10:03:13.60#ibcon#end of sib2, iclass 6, count 0 2006.173.10:03:13.60#ibcon#*mode == 0, iclass 6, count 0 2006.173.10:03:13.60#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.10:03:13.60#ibcon#[25=BW32\r\n] 2006.173.10:03:13.60#ibcon#*before write, iclass 6, count 0 2006.173.10:03:13.60#ibcon#enter sib2, iclass 6, count 0 2006.173.10:03:13.60#ibcon#flushed, iclass 6, count 0 2006.173.10:03:13.60#ibcon#about to write, iclass 6, count 0 2006.173.10:03:13.60#ibcon#wrote, iclass 6, count 0 2006.173.10:03:13.60#ibcon#about to read 3, iclass 6, count 0 2006.173.10:03:13.63#ibcon#read 3, iclass 6, count 0 2006.173.10:03:13.63#ibcon#about to read 4, iclass 6, count 0 2006.173.10:03:13.63#ibcon#read 4, iclass 6, count 0 2006.173.10:03:13.63#ibcon#about to read 5, iclass 6, count 0 2006.173.10:03:13.63#ibcon#read 5, iclass 6, count 0 2006.173.10:03:13.63#ibcon#about to read 6, iclass 6, count 0 2006.173.10:03:13.63#ibcon#read 6, iclass 6, count 0 2006.173.10:03:13.63#ibcon#end of sib2, iclass 6, count 0 2006.173.10:03:13.63#ibcon#*after write, iclass 6, count 0 2006.173.10:03:13.63#ibcon#*before return 0, iclass 6, count 0 2006.173.10:03:13.63#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.10:03:13.63#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.10:03:13.63#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.10:03:13.63#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.10:03:13.63$vck44/vbbw=wide 2006.173.10:03:13.63#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.10:03:13.63#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.10:03:13.63#ibcon#ireg 8 cls_cnt 0 2006.173.10:03:13.63#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.10:03:13.70#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.10:03:13.70#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.10:03:13.70#ibcon#enter wrdev, iclass 10, count 0 2006.173.10:03:13.70#ibcon#first serial, iclass 10, count 0 2006.173.10:03:13.70#ibcon#enter sib2, iclass 10, count 0 2006.173.10:03:13.70#ibcon#flushed, iclass 10, count 0 2006.173.10:03:13.70#ibcon#about to write, iclass 10, count 0 2006.173.10:03:13.70#ibcon#wrote, iclass 10, count 0 2006.173.10:03:13.70#ibcon#about to read 3, iclass 10, count 0 2006.173.10:03:13.72#ibcon#read 3, iclass 10, count 0 2006.173.10:03:13.72#ibcon#about to read 4, iclass 10, count 0 2006.173.10:03:13.72#ibcon#read 4, iclass 10, count 0 2006.173.10:03:13.72#ibcon#about to read 5, iclass 10, count 0 2006.173.10:03:13.72#ibcon#read 5, iclass 10, count 0 2006.173.10:03:13.72#ibcon#about to read 6, iclass 10, count 0 2006.173.10:03:13.72#ibcon#read 6, iclass 10, count 0 2006.173.10:03:13.72#ibcon#end of sib2, iclass 10, count 0 2006.173.10:03:13.72#ibcon#*mode == 0, iclass 10, count 0 2006.173.10:03:13.72#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.10:03:13.72#ibcon#[27=BW32\r\n] 2006.173.10:03:13.72#ibcon#*before write, iclass 10, count 0 2006.173.10:03:13.72#ibcon#enter sib2, iclass 10, count 0 2006.173.10:03:13.72#ibcon#flushed, iclass 10, count 0 2006.173.10:03:13.72#ibcon#about to write, iclass 10, count 0 2006.173.10:03:13.72#ibcon#wrote, iclass 10, count 0 2006.173.10:03:13.72#ibcon#about to read 3, iclass 10, count 0 2006.173.10:03:13.75#ibcon#read 3, iclass 10, count 0 2006.173.10:03:13.75#ibcon#about to read 4, iclass 10, count 0 2006.173.10:03:13.75#ibcon#read 4, iclass 10, count 0 2006.173.10:03:13.75#ibcon#about to read 5, iclass 10, count 0 2006.173.10:03:13.75#ibcon#read 5, iclass 10, count 0 2006.173.10:03:13.75#ibcon#about to read 6, iclass 10, count 0 2006.173.10:03:13.75#ibcon#read 6, iclass 10, count 0 2006.173.10:03:13.75#ibcon#end of sib2, iclass 10, count 0 2006.173.10:03:13.75#ibcon#*after write, iclass 10, count 0 2006.173.10:03:13.75#ibcon#*before return 0, iclass 10, count 0 2006.173.10:03:13.75#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.10:03:13.75#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.10:03:13.75#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.10:03:13.75#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.10:03:13.75$setupk4/ifdk4 2006.173.10:03:13.75$ifdk4/lo= 2006.173.10:03:13.75$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.10:03:13.75$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.10:03:13.75$ifdk4/patch= 2006.173.10:03:13.75$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.10:03:13.75$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.10:03:13.75$setupk4/!*+20s 2006.173.10:03:14.13#abcon#<5=/06 1.1 1.4 22.85 931004.1\r\n> 2006.173.10:03:14.15#abcon#{5=INTERFACE CLEAR} 2006.173.10:03:14.21#abcon#[5=S1D000X0/0*\r\n] 2006.173.10:03:24.30#abcon#<5=/06 1.1 1.4 22.84 931004.1\r\n> 2006.173.10:03:24.32#abcon#{5=INTERFACE CLEAR} 2006.173.10:03:24.38#abcon#[5=S1D000X0/0*\r\n] 2006.173.10:03:28.26$setupk4/"tpicd 2006.173.10:03:28.26$setupk4/echo=off 2006.173.10:03:28.26$setupk4/xlog=off 2006.173.10:03:28.26:!2006.173.10:04:23 2006.173.10:03:32.14#trakl#Source acquired 2006.173.10:03:33.14#flagr#flagr/antenna,acquired 2006.173.10:04:23.00:preob 2006.173.10:04:23.14/onsource/TRACKING 2006.173.10:04:23.14:!2006.173.10:04:33 2006.173.10:04:33.00:"tape 2006.173.10:04:33.00:"st=record 2006.173.10:04:33.00:data_valid=on 2006.173.10:04:33.00:midob 2006.173.10:04:33.14/onsource/TRACKING 2006.173.10:04:33.14/wx/22.84,1004.1,93 2006.173.10:04:33.21/cable/+6.5025E-03 2006.173.10:04:34.30/va/01,07,usb,yes,38,41 2006.173.10:04:34.30/va/02,06,usb,yes,38,38 2006.173.10:04:34.30/va/03,05,usb,yes,48,50 2006.173.10:04:34.30/va/04,06,usb,yes,38,40 2006.173.10:04:34.30/va/05,04,usb,yes,30,31 2006.173.10:04:34.30/va/06,03,usb,yes,42,42 2006.173.10:04:34.30/va/07,04,usb,yes,34,35 2006.173.10:04:34.30/va/08,04,usb,yes,29,35 2006.173.10:04:34.53/valo/01,524.99,yes,locked 2006.173.10:04:34.53/valo/02,534.99,yes,locked 2006.173.10:04:34.53/valo/03,564.99,yes,locked 2006.173.10:04:34.53/valo/04,624.99,yes,locked 2006.173.10:04:34.53/valo/05,734.99,yes,locked 2006.173.10:04:34.53/valo/06,814.99,yes,locked 2006.173.10:04:34.53/valo/07,864.99,yes,locked 2006.173.10:04:34.53/valo/08,884.99,yes,locked 2006.173.10:04:35.62/vb/01,04,usb,yes,30,28 2006.173.10:04:35.62/vb/02,04,usb,yes,32,32 2006.173.10:04:35.62/vb/03,04,usb,yes,29,32 2006.173.10:04:35.62/vb/04,04,usb,yes,33,32 2006.173.10:04:35.62/vb/05,04,usb,yes,26,29 2006.173.10:04:35.62/vb/06,04,usb,yes,31,27 2006.173.10:04:35.62/vb/07,04,usb,yes,30,30 2006.173.10:04:35.62/vb/08,04,usb,yes,28,31 2006.173.10:04:35.86/vblo/01,629.99,yes,locked 2006.173.10:04:35.86/vblo/02,634.99,yes,locked 2006.173.10:04:35.86/vblo/03,649.99,yes,locked 2006.173.10:04:35.86/vblo/04,679.99,yes,locked 2006.173.10:04:35.86/vblo/05,709.99,yes,locked 2006.173.10:04:35.86/vblo/06,719.99,yes,locked 2006.173.10:04:35.86/vblo/07,734.99,yes,locked 2006.173.10:04:35.86/vblo/08,744.99,yes,locked 2006.173.10:04:36.01/vabw/8 2006.173.10:04:36.16/vbbw/8 2006.173.10:04:36.27/xfe/off,on,15.0 2006.173.10:04:36.64/ifatt/23,28,28,28 2006.173.10:04:37.07/fmout-gps/S +3.99E-07 2006.173.10:04:37.11:!2006.173.10:05:13 2006.173.10:05:13.00:data_valid=off 2006.173.10:05:13.00:"et 2006.173.10:05:13.00:!+3s 2006.173.10:05:16.01:"tape 2006.173.10:05:16.01:postob 2006.173.10:05:16.12/cable/+6.5002E-03 2006.173.10:05:16.12/wx/22.83,1004.1,93 2006.173.10:05:17.08/fmout-gps/S +4.00E-07 2006.173.10:05:17.08:scan_name=173-1007,jd0606,90 2006.173.10:05:17.08:source=3c274,123049.42,122328.0,2000.0,cw 2006.173.10:05:18.14#flagr#flagr/antenna,new-source 2006.173.10:05:18.14:checkk5 2006.173.10:05:18.54/chk_autoobs//k5ts1/ autoobs is running! 2006.173.10:05:18.95/chk_autoobs//k5ts2/ autoobs is running! 2006.173.10:05:19.36/chk_autoobs//k5ts3/ autoobs is running! 2006.173.10:05:19.74/chk_autoobs//k5ts4/ autoobs is running! 2006.173.10:05:20.12/chk_obsdata//k5ts1/T1731004??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.173.10:05:20.53/chk_obsdata//k5ts2/T1731004??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.173.10:05:20.94/chk_obsdata//k5ts3/T1731004??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.173.10:05:21.34/chk_obsdata//k5ts4/T1731004??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.173.10:05:22.07/k5log//k5ts1_log_newline 2006.173.10:05:22.81/k5log//k5ts2_log_newline 2006.173.10:05:23.52/k5log//k5ts3_log_newline 2006.173.10:05:24.22/k5log//k5ts4_log_newline 2006.173.10:05:24.24/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.10:05:24.24:setupk4=1 2006.173.10:05:24.24$setupk4/echo=on 2006.173.10:05:24.24$setupk4/pcalon 2006.173.10:05:24.24$pcalon/"no phase cal control is implemented here 2006.173.10:05:24.24$setupk4/"tpicd=stop 2006.173.10:05:24.24$setupk4/"rec=synch_on 2006.173.10:05:24.24$setupk4/"rec_mode=128 2006.173.10:05:24.24$setupk4/!* 2006.173.10:05:24.25$setupk4/recpk4 2006.173.10:05:24.25$recpk4/recpatch= 2006.173.10:05:24.25$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.10:05:24.25$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.10:05:24.25$setupk4/vck44 2006.173.10:05:24.25$vck44/valo=1,524.99 2006.173.10:05:24.25#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.10:05:24.25#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.10:05:24.25#ibcon#ireg 17 cls_cnt 0 2006.173.10:05:24.25#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.10:05:24.25#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.10:05:24.25#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.10:05:24.25#ibcon#enter wrdev, iclass 31, count 0 2006.173.10:05:24.25#ibcon#first serial, iclass 31, count 0 2006.173.10:05:24.25#ibcon#enter sib2, iclass 31, count 0 2006.173.10:05:24.25#ibcon#flushed, iclass 31, count 0 2006.173.10:05:24.25#ibcon#about to write, iclass 31, count 0 2006.173.10:05:24.25#ibcon#wrote, iclass 31, count 0 2006.173.10:05:24.25#ibcon#about to read 3, iclass 31, count 0 2006.173.10:05:24.27#ibcon#read 3, iclass 31, count 0 2006.173.10:05:24.27#ibcon#about to read 4, iclass 31, count 0 2006.173.10:05:24.27#ibcon#read 4, iclass 31, count 0 2006.173.10:05:24.27#ibcon#about to read 5, iclass 31, count 0 2006.173.10:05:24.27#ibcon#read 5, iclass 31, count 0 2006.173.10:05:24.27#ibcon#about to read 6, iclass 31, count 0 2006.173.10:05:24.27#ibcon#read 6, iclass 31, count 0 2006.173.10:05:24.27#ibcon#end of sib2, iclass 31, count 0 2006.173.10:05:24.27#ibcon#*mode == 0, iclass 31, count 0 2006.173.10:05:24.27#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.10:05:24.27#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.10:05:24.27#ibcon#*before write, iclass 31, count 0 2006.173.10:05:24.27#ibcon#enter sib2, iclass 31, count 0 2006.173.10:05:24.27#ibcon#flushed, iclass 31, count 0 2006.173.10:05:24.27#ibcon#about to write, iclass 31, count 0 2006.173.10:05:24.27#ibcon#wrote, iclass 31, count 0 2006.173.10:05:24.27#ibcon#about to read 3, iclass 31, count 0 2006.173.10:05:24.32#ibcon#read 3, iclass 31, count 0 2006.173.10:05:24.32#ibcon#about to read 4, iclass 31, count 0 2006.173.10:05:24.32#ibcon#read 4, iclass 31, count 0 2006.173.10:05:24.32#ibcon#about to read 5, iclass 31, count 0 2006.173.10:05:24.32#ibcon#read 5, iclass 31, count 0 2006.173.10:05:24.32#ibcon#about to read 6, iclass 31, count 0 2006.173.10:05:24.32#ibcon#read 6, iclass 31, count 0 2006.173.10:05:24.32#ibcon#end of sib2, iclass 31, count 0 2006.173.10:05:24.32#ibcon#*after write, iclass 31, count 0 2006.173.10:05:24.32#ibcon#*before return 0, iclass 31, count 0 2006.173.10:05:24.32#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.10:05:24.32#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.10:05:24.32#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.10:05:24.32#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.10:05:24.32$vck44/va=1,7 2006.173.10:05:24.32#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.173.10:05:24.32#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.173.10:05:24.32#ibcon#ireg 11 cls_cnt 2 2006.173.10:05:24.32#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.10:05:24.32#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.10:05:24.32#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.10:05:24.32#ibcon#enter wrdev, iclass 33, count 2 2006.173.10:05:24.32#ibcon#first serial, iclass 33, count 2 2006.173.10:05:24.32#ibcon#enter sib2, iclass 33, count 2 2006.173.10:05:24.32#ibcon#flushed, iclass 33, count 2 2006.173.10:05:24.32#ibcon#about to write, iclass 33, count 2 2006.173.10:05:24.32#ibcon#wrote, iclass 33, count 2 2006.173.10:05:24.32#ibcon#about to read 3, iclass 33, count 2 2006.173.10:05:24.34#ibcon#read 3, iclass 33, count 2 2006.173.10:05:24.34#ibcon#about to read 4, iclass 33, count 2 2006.173.10:05:24.34#ibcon#read 4, iclass 33, count 2 2006.173.10:05:24.34#ibcon#about to read 5, iclass 33, count 2 2006.173.10:05:24.34#ibcon#read 5, iclass 33, count 2 2006.173.10:05:24.34#ibcon#about to read 6, iclass 33, count 2 2006.173.10:05:24.34#ibcon#read 6, iclass 33, count 2 2006.173.10:05:24.34#ibcon#end of sib2, iclass 33, count 2 2006.173.10:05:24.34#ibcon#*mode == 0, iclass 33, count 2 2006.173.10:05:24.34#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.173.10:05:24.34#ibcon#[25=AT01-07\r\n] 2006.173.10:05:24.34#ibcon#*before write, iclass 33, count 2 2006.173.10:05:24.34#ibcon#enter sib2, iclass 33, count 2 2006.173.10:05:24.34#ibcon#flushed, iclass 33, count 2 2006.173.10:05:24.34#ibcon#about to write, iclass 33, count 2 2006.173.10:05:24.34#ibcon#wrote, iclass 33, count 2 2006.173.10:05:24.34#ibcon#about to read 3, iclass 33, count 2 2006.173.10:05:24.37#ibcon#read 3, iclass 33, count 2 2006.173.10:05:24.37#ibcon#about to read 4, iclass 33, count 2 2006.173.10:05:24.37#ibcon#read 4, iclass 33, count 2 2006.173.10:05:24.37#ibcon#about to read 5, iclass 33, count 2 2006.173.10:05:24.37#ibcon#read 5, iclass 33, count 2 2006.173.10:05:24.37#ibcon#about to read 6, iclass 33, count 2 2006.173.10:05:24.37#ibcon#read 6, iclass 33, count 2 2006.173.10:05:24.37#ibcon#end of sib2, iclass 33, count 2 2006.173.10:05:24.37#ibcon#*after write, iclass 33, count 2 2006.173.10:05:24.37#ibcon#*before return 0, iclass 33, count 2 2006.173.10:05:24.37#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.10:05:24.37#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.173.10:05:24.37#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.173.10:05:24.37#ibcon#ireg 7 cls_cnt 0 2006.173.10:05:24.37#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.10:05:24.49#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.10:05:24.49#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.10:05:24.49#ibcon#enter wrdev, iclass 33, count 0 2006.173.10:05:24.49#ibcon#first serial, iclass 33, count 0 2006.173.10:05:24.49#ibcon#enter sib2, iclass 33, count 0 2006.173.10:05:24.49#ibcon#flushed, iclass 33, count 0 2006.173.10:05:24.49#ibcon#about to write, iclass 33, count 0 2006.173.10:05:24.49#ibcon#wrote, iclass 33, count 0 2006.173.10:05:24.49#ibcon#about to read 3, iclass 33, count 0 2006.173.10:05:24.51#ibcon#read 3, iclass 33, count 0 2006.173.10:05:24.51#ibcon#about to read 4, iclass 33, count 0 2006.173.10:05:24.51#ibcon#read 4, iclass 33, count 0 2006.173.10:05:24.51#ibcon#about to read 5, iclass 33, count 0 2006.173.10:05:24.51#ibcon#read 5, iclass 33, count 0 2006.173.10:05:24.51#ibcon#about to read 6, iclass 33, count 0 2006.173.10:05:24.51#ibcon#read 6, iclass 33, count 0 2006.173.10:05:24.51#ibcon#end of sib2, iclass 33, count 0 2006.173.10:05:24.51#ibcon#*mode == 0, iclass 33, count 0 2006.173.10:05:24.51#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.10:05:24.51#ibcon#[25=USB\r\n] 2006.173.10:05:24.51#ibcon#*before write, iclass 33, count 0 2006.173.10:05:24.51#ibcon#enter sib2, iclass 33, count 0 2006.173.10:05:24.51#ibcon#flushed, iclass 33, count 0 2006.173.10:05:24.51#ibcon#about to write, iclass 33, count 0 2006.173.10:05:24.51#ibcon#wrote, iclass 33, count 0 2006.173.10:05:24.51#ibcon#about to read 3, iclass 33, count 0 2006.173.10:05:24.54#ibcon#read 3, iclass 33, count 0 2006.173.10:05:24.54#ibcon#about to read 4, iclass 33, count 0 2006.173.10:05:24.54#ibcon#read 4, iclass 33, count 0 2006.173.10:05:24.54#ibcon#about to read 5, iclass 33, count 0 2006.173.10:05:24.54#ibcon#read 5, iclass 33, count 0 2006.173.10:05:24.54#ibcon#about to read 6, iclass 33, count 0 2006.173.10:05:24.54#ibcon#read 6, iclass 33, count 0 2006.173.10:05:24.54#ibcon#end of sib2, iclass 33, count 0 2006.173.10:05:24.54#ibcon#*after write, iclass 33, count 0 2006.173.10:05:24.54#ibcon#*before return 0, iclass 33, count 0 2006.173.10:05:24.54#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.10:05:24.54#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.173.10:05:24.54#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.10:05:24.54#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.10:05:24.54$vck44/valo=2,534.99 2006.173.10:05:24.54#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.10:05:24.54#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.10:05:24.54#ibcon#ireg 17 cls_cnt 0 2006.173.10:05:24.54#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.10:05:24.54#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.10:05:24.54#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.10:05:24.54#ibcon#enter wrdev, iclass 35, count 0 2006.173.10:05:24.54#ibcon#first serial, iclass 35, count 0 2006.173.10:05:24.54#ibcon#enter sib2, iclass 35, count 0 2006.173.10:05:24.54#ibcon#flushed, iclass 35, count 0 2006.173.10:05:24.54#ibcon#about to write, iclass 35, count 0 2006.173.10:05:24.54#ibcon#wrote, iclass 35, count 0 2006.173.10:05:24.54#ibcon#about to read 3, iclass 35, count 0 2006.173.10:05:24.56#ibcon#read 3, iclass 35, count 0 2006.173.10:05:24.56#ibcon#about to read 4, iclass 35, count 0 2006.173.10:05:24.56#ibcon#read 4, iclass 35, count 0 2006.173.10:05:24.56#ibcon#about to read 5, iclass 35, count 0 2006.173.10:05:24.56#ibcon#read 5, iclass 35, count 0 2006.173.10:05:24.56#ibcon#about to read 6, iclass 35, count 0 2006.173.10:05:24.56#ibcon#read 6, iclass 35, count 0 2006.173.10:05:24.56#ibcon#end of sib2, iclass 35, count 0 2006.173.10:05:24.56#ibcon#*mode == 0, iclass 35, count 0 2006.173.10:05:24.56#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.10:05:24.56#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.10:05:24.56#ibcon#*before write, iclass 35, count 0 2006.173.10:05:24.56#ibcon#enter sib2, iclass 35, count 0 2006.173.10:05:24.56#ibcon#flushed, iclass 35, count 0 2006.173.10:05:24.56#ibcon#about to write, iclass 35, count 0 2006.173.10:05:24.56#ibcon#wrote, iclass 35, count 0 2006.173.10:05:24.56#ibcon#about to read 3, iclass 35, count 0 2006.173.10:05:24.60#ibcon#read 3, iclass 35, count 0 2006.173.10:05:24.60#ibcon#about to read 4, iclass 35, count 0 2006.173.10:05:24.60#ibcon#read 4, iclass 35, count 0 2006.173.10:05:24.60#ibcon#about to read 5, iclass 35, count 0 2006.173.10:05:24.60#ibcon#read 5, iclass 35, count 0 2006.173.10:05:24.60#ibcon#about to read 6, iclass 35, count 0 2006.173.10:05:24.60#ibcon#read 6, iclass 35, count 0 2006.173.10:05:24.60#ibcon#end of sib2, iclass 35, count 0 2006.173.10:05:24.60#ibcon#*after write, iclass 35, count 0 2006.173.10:05:24.60#ibcon#*before return 0, iclass 35, count 0 2006.173.10:05:24.60#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.10:05:24.60#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.10:05:24.60#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.10:05:24.60#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.10:05:24.60$vck44/va=2,6 2006.173.10:05:24.60#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.173.10:05:24.60#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.173.10:05:24.60#ibcon#ireg 11 cls_cnt 2 2006.173.10:05:24.60#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.10:05:24.66#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.10:05:24.66#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.10:05:24.66#ibcon#enter wrdev, iclass 37, count 2 2006.173.10:05:24.66#ibcon#first serial, iclass 37, count 2 2006.173.10:05:24.66#ibcon#enter sib2, iclass 37, count 2 2006.173.10:05:24.66#ibcon#flushed, iclass 37, count 2 2006.173.10:05:24.66#ibcon#about to write, iclass 37, count 2 2006.173.10:05:24.66#ibcon#wrote, iclass 37, count 2 2006.173.10:05:24.66#ibcon#about to read 3, iclass 37, count 2 2006.173.10:05:24.68#ibcon#read 3, iclass 37, count 2 2006.173.10:05:24.68#ibcon#about to read 4, iclass 37, count 2 2006.173.10:05:24.68#ibcon#read 4, iclass 37, count 2 2006.173.10:05:24.68#ibcon#about to read 5, iclass 37, count 2 2006.173.10:05:24.68#ibcon#read 5, iclass 37, count 2 2006.173.10:05:24.68#ibcon#about to read 6, iclass 37, count 2 2006.173.10:05:24.68#ibcon#read 6, iclass 37, count 2 2006.173.10:05:24.68#ibcon#end of sib2, iclass 37, count 2 2006.173.10:05:24.68#ibcon#*mode == 0, iclass 37, count 2 2006.173.10:05:24.68#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.173.10:05:24.68#ibcon#[25=AT02-06\r\n] 2006.173.10:05:24.68#ibcon#*before write, iclass 37, count 2 2006.173.10:05:24.68#ibcon#enter sib2, iclass 37, count 2 2006.173.10:05:24.68#ibcon#flushed, iclass 37, count 2 2006.173.10:05:24.68#ibcon#about to write, iclass 37, count 2 2006.173.10:05:24.68#ibcon#wrote, iclass 37, count 2 2006.173.10:05:24.68#ibcon#about to read 3, iclass 37, count 2 2006.173.10:05:24.71#ibcon#read 3, iclass 37, count 2 2006.173.10:05:24.71#ibcon#about to read 4, iclass 37, count 2 2006.173.10:05:24.71#ibcon#read 4, iclass 37, count 2 2006.173.10:05:24.71#ibcon#about to read 5, iclass 37, count 2 2006.173.10:05:24.71#ibcon#read 5, iclass 37, count 2 2006.173.10:05:24.71#ibcon#about to read 6, iclass 37, count 2 2006.173.10:05:24.71#ibcon#read 6, iclass 37, count 2 2006.173.10:05:24.71#ibcon#end of sib2, iclass 37, count 2 2006.173.10:05:24.71#ibcon#*after write, iclass 37, count 2 2006.173.10:05:24.71#ibcon#*before return 0, iclass 37, count 2 2006.173.10:05:24.71#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.10:05:24.71#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.173.10:05:24.71#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.173.10:05:24.71#ibcon#ireg 7 cls_cnt 0 2006.173.10:05:24.71#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.10:05:24.83#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.10:05:24.83#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.10:05:24.83#ibcon#enter wrdev, iclass 37, count 0 2006.173.10:05:24.83#ibcon#first serial, iclass 37, count 0 2006.173.10:05:24.83#ibcon#enter sib2, iclass 37, count 0 2006.173.10:05:24.83#ibcon#flushed, iclass 37, count 0 2006.173.10:05:24.83#ibcon#about to write, iclass 37, count 0 2006.173.10:05:24.83#ibcon#wrote, iclass 37, count 0 2006.173.10:05:24.83#ibcon#about to read 3, iclass 37, count 0 2006.173.10:05:24.85#ibcon#read 3, iclass 37, count 0 2006.173.10:05:24.85#ibcon#about to read 4, iclass 37, count 0 2006.173.10:05:24.85#ibcon#read 4, iclass 37, count 0 2006.173.10:05:24.85#ibcon#about to read 5, iclass 37, count 0 2006.173.10:05:24.85#ibcon#read 5, iclass 37, count 0 2006.173.10:05:24.85#ibcon#about to read 6, iclass 37, count 0 2006.173.10:05:24.85#ibcon#read 6, iclass 37, count 0 2006.173.10:05:24.85#ibcon#end of sib2, iclass 37, count 0 2006.173.10:05:24.85#ibcon#*mode == 0, iclass 37, count 0 2006.173.10:05:24.85#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.10:05:24.85#ibcon#[25=USB\r\n] 2006.173.10:05:24.85#ibcon#*before write, iclass 37, count 0 2006.173.10:05:24.85#ibcon#enter sib2, iclass 37, count 0 2006.173.10:05:24.85#ibcon#flushed, iclass 37, count 0 2006.173.10:05:24.85#ibcon#about to write, iclass 37, count 0 2006.173.10:05:24.85#ibcon#wrote, iclass 37, count 0 2006.173.10:05:24.85#ibcon#about to read 3, iclass 37, count 0 2006.173.10:05:24.88#ibcon#read 3, iclass 37, count 0 2006.173.10:05:24.88#ibcon#about to read 4, iclass 37, count 0 2006.173.10:05:24.88#ibcon#read 4, iclass 37, count 0 2006.173.10:05:24.88#ibcon#about to read 5, iclass 37, count 0 2006.173.10:05:24.88#ibcon#read 5, iclass 37, count 0 2006.173.10:05:24.88#ibcon#about to read 6, iclass 37, count 0 2006.173.10:05:24.88#ibcon#read 6, iclass 37, count 0 2006.173.10:05:24.88#ibcon#end of sib2, iclass 37, count 0 2006.173.10:05:24.88#ibcon#*after write, iclass 37, count 0 2006.173.10:05:24.88#ibcon#*before return 0, iclass 37, count 0 2006.173.10:05:24.88#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.10:05:24.88#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.173.10:05:24.88#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.10:05:24.88#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.10:05:24.88$vck44/valo=3,564.99 2006.173.10:05:24.88#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.10:05:24.88#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.10:05:24.88#ibcon#ireg 17 cls_cnt 0 2006.173.10:05:24.88#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.10:05:24.88#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.10:05:24.88#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.10:05:24.88#ibcon#enter wrdev, iclass 39, count 0 2006.173.10:05:24.88#ibcon#first serial, iclass 39, count 0 2006.173.10:05:24.88#ibcon#enter sib2, iclass 39, count 0 2006.173.10:05:24.88#ibcon#flushed, iclass 39, count 0 2006.173.10:05:24.88#ibcon#about to write, iclass 39, count 0 2006.173.10:05:24.88#ibcon#wrote, iclass 39, count 0 2006.173.10:05:24.88#ibcon#about to read 3, iclass 39, count 0 2006.173.10:05:24.90#ibcon#read 3, iclass 39, count 0 2006.173.10:05:24.90#ibcon#about to read 4, iclass 39, count 0 2006.173.10:05:24.90#ibcon#read 4, iclass 39, count 0 2006.173.10:05:24.90#ibcon#about to read 5, iclass 39, count 0 2006.173.10:05:24.90#ibcon#read 5, iclass 39, count 0 2006.173.10:05:24.90#ibcon#about to read 6, iclass 39, count 0 2006.173.10:05:24.90#ibcon#read 6, iclass 39, count 0 2006.173.10:05:24.90#ibcon#end of sib2, iclass 39, count 0 2006.173.10:05:24.90#ibcon#*mode == 0, iclass 39, count 0 2006.173.10:05:24.90#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.10:05:24.90#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.10:05:24.90#ibcon#*before write, iclass 39, count 0 2006.173.10:05:24.90#ibcon#enter sib2, iclass 39, count 0 2006.173.10:05:24.90#ibcon#flushed, iclass 39, count 0 2006.173.10:05:24.90#ibcon#about to write, iclass 39, count 0 2006.173.10:05:24.90#ibcon#wrote, iclass 39, count 0 2006.173.10:05:24.90#ibcon#about to read 3, iclass 39, count 0 2006.173.10:05:24.94#ibcon#read 3, iclass 39, count 0 2006.173.10:05:24.94#ibcon#about to read 4, iclass 39, count 0 2006.173.10:05:24.94#ibcon#read 4, iclass 39, count 0 2006.173.10:05:24.94#ibcon#about to read 5, iclass 39, count 0 2006.173.10:05:24.94#ibcon#read 5, iclass 39, count 0 2006.173.10:05:24.94#ibcon#about to read 6, iclass 39, count 0 2006.173.10:05:24.94#ibcon#read 6, iclass 39, count 0 2006.173.10:05:24.94#ibcon#end of sib2, iclass 39, count 0 2006.173.10:05:24.94#ibcon#*after write, iclass 39, count 0 2006.173.10:05:24.94#ibcon#*before return 0, iclass 39, count 0 2006.173.10:05:24.94#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.10:05:24.94#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.10:05:24.94#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.10:05:24.94#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.10:05:24.94$vck44/va=3,5 2006.173.10:05:24.94#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.10:05:24.94#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.10:05:24.94#ibcon#ireg 11 cls_cnt 2 2006.173.10:05:24.94#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.10:05:25.00#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.10:05:25.00#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.10:05:25.00#ibcon#enter wrdev, iclass 3, count 2 2006.173.10:05:25.00#ibcon#first serial, iclass 3, count 2 2006.173.10:05:25.00#ibcon#enter sib2, iclass 3, count 2 2006.173.10:05:25.00#ibcon#flushed, iclass 3, count 2 2006.173.10:05:25.00#ibcon#about to write, iclass 3, count 2 2006.173.10:05:25.00#ibcon#wrote, iclass 3, count 2 2006.173.10:05:25.00#ibcon#about to read 3, iclass 3, count 2 2006.173.10:05:25.02#ibcon#read 3, iclass 3, count 2 2006.173.10:05:25.02#ibcon#about to read 4, iclass 3, count 2 2006.173.10:05:25.02#ibcon#read 4, iclass 3, count 2 2006.173.10:05:25.02#ibcon#about to read 5, iclass 3, count 2 2006.173.10:05:25.02#ibcon#read 5, iclass 3, count 2 2006.173.10:05:25.02#ibcon#about to read 6, iclass 3, count 2 2006.173.10:05:25.02#ibcon#read 6, iclass 3, count 2 2006.173.10:05:25.02#ibcon#end of sib2, iclass 3, count 2 2006.173.10:05:25.02#ibcon#*mode == 0, iclass 3, count 2 2006.173.10:05:25.02#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.10:05:25.02#ibcon#[25=AT03-05\r\n] 2006.173.10:05:25.02#ibcon#*before write, iclass 3, count 2 2006.173.10:05:25.02#ibcon#enter sib2, iclass 3, count 2 2006.173.10:05:25.02#ibcon#flushed, iclass 3, count 2 2006.173.10:05:25.02#ibcon#about to write, iclass 3, count 2 2006.173.10:05:25.02#ibcon#wrote, iclass 3, count 2 2006.173.10:05:25.02#ibcon#about to read 3, iclass 3, count 2 2006.173.10:05:25.05#ibcon#read 3, iclass 3, count 2 2006.173.10:05:25.05#ibcon#about to read 4, iclass 3, count 2 2006.173.10:05:25.05#ibcon#read 4, iclass 3, count 2 2006.173.10:05:25.05#ibcon#about to read 5, iclass 3, count 2 2006.173.10:05:25.05#ibcon#read 5, iclass 3, count 2 2006.173.10:05:25.05#ibcon#about to read 6, iclass 3, count 2 2006.173.10:05:25.05#ibcon#read 6, iclass 3, count 2 2006.173.10:05:25.05#ibcon#end of sib2, iclass 3, count 2 2006.173.10:05:25.05#ibcon#*after write, iclass 3, count 2 2006.173.10:05:25.05#ibcon#*before return 0, iclass 3, count 2 2006.173.10:05:25.05#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.10:05:25.05#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.10:05:25.05#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.10:05:25.05#ibcon#ireg 7 cls_cnt 0 2006.173.10:05:25.05#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.10:05:25.17#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.10:05:25.17#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.10:05:25.17#ibcon#enter wrdev, iclass 3, count 0 2006.173.10:05:25.17#ibcon#first serial, iclass 3, count 0 2006.173.10:05:25.17#ibcon#enter sib2, iclass 3, count 0 2006.173.10:05:25.17#ibcon#flushed, iclass 3, count 0 2006.173.10:05:25.17#ibcon#about to write, iclass 3, count 0 2006.173.10:05:25.17#ibcon#wrote, iclass 3, count 0 2006.173.10:05:25.17#ibcon#about to read 3, iclass 3, count 0 2006.173.10:05:25.19#ibcon#read 3, iclass 3, count 0 2006.173.10:05:25.19#ibcon#about to read 4, iclass 3, count 0 2006.173.10:05:25.19#ibcon#read 4, iclass 3, count 0 2006.173.10:05:25.19#ibcon#about to read 5, iclass 3, count 0 2006.173.10:05:25.19#ibcon#read 5, iclass 3, count 0 2006.173.10:05:25.19#ibcon#about to read 6, iclass 3, count 0 2006.173.10:05:25.19#ibcon#read 6, iclass 3, count 0 2006.173.10:05:25.19#ibcon#end of sib2, iclass 3, count 0 2006.173.10:05:25.19#ibcon#*mode == 0, iclass 3, count 0 2006.173.10:05:25.19#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.10:05:25.19#ibcon#[25=USB\r\n] 2006.173.10:05:25.19#ibcon#*before write, iclass 3, count 0 2006.173.10:05:25.19#ibcon#enter sib2, iclass 3, count 0 2006.173.10:05:25.19#ibcon#flushed, iclass 3, count 0 2006.173.10:05:25.19#ibcon#about to write, iclass 3, count 0 2006.173.10:05:25.19#ibcon#wrote, iclass 3, count 0 2006.173.10:05:25.19#ibcon#about to read 3, iclass 3, count 0 2006.173.10:05:25.22#ibcon#read 3, iclass 3, count 0 2006.173.10:05:25.22#ibcon#about to read 4, iclass 3, count 0 2006.173.10:05:25.22#ibcon#read 4, iclass 3, count 0 2006.173.10:05:25.22#ibcon#about to read 5, iclass 3, count 0 2006.173.10:05:25.22#ibcon#read 5, iclass 3, count 0 2006.173.10:05:25.22#ibcon#about to read 6, iclass 3, count 0 2006.173.10:05:25.22#ibcon#read 6, iclass 3, count 0 2006.173.10:05:25.22#ibcon#end of sib2, iclass 3, count 0 2006.173.10:05:25.22#ibcon#*after write, iclass 3, count 0 2006.173.10:05:25.22#ibcon#*before return 0, iclass 3, count 0 2006.173.10:05:25.22#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.10:05:25.22#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.10:05:25.22#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.10:05:25.22#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.10:05:25.22$vck44/valo=4,624.99 2006.173.10:05:25.22#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.10:05:25.22#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.10:05:25.22#ibcon#ireg 17 cls_cnt 0 2006.173.10:05:25.22#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.10:05:25.22#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.10:05:25.22#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.10:05:25.22#ibcon#enter wrdev, iclass 5, count 0 2006.173.10:05:25.22#ibcon#first serial, iclass 5, count 0 2006.173.10:05:25.22#ibcon#enter sib2, iclass 5, count 0 2006.173.10:05:25.22#ibcon#flushed, iclass 5, count 0 2006.173.10:05:25.22#ibcon#about to write, iclass 5, count 0 2006.173.10:05:25.22#ibcon#wrote, iclass 5, count 0 2006.173.10:05:25.22#ibcon#about to read 3, iclass 5, count 0 2006.173.10:05:25.24#ibcon#read 3, iclass 5, count 0 2006.173.10:05:25.24#ibcon#about to read 4, iclass 5, count 0 2006.173.10:05:25.24#ibcon#read 4, iclass 5, count 0 2006.173.10:05:25.24#ibcon#about to read 5, iclass 5, count 0 2006.173.10:05:25.24#ibcon#read 5, iclass 5, count 0 2006.173.10:05:25.24#ibcon#about to read 6, iclass 5, count 0 2006.173.10:05:25.24#ibcon#read 6, iclass 5, count 0 2006.173.10:05:25.24#ibcon#end of sib2, iclass 5, count 0 2006.173.10:05:25.24#ibcon#*mode == 0, iclass 5, count 0 2006.173.10:05:25.24#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.10:05:25.24#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.10:05:25.24#ibcon#*before write, iclass 5, count 0 2006.173.10:05:25.24#ibcon#enter sib2, iclass 5, count 0 2006.173.10:05:25.24#ibcon#flushed, iclass 5, count 0 2006.173.10:05:25.24#ibcon#about to write, iclass 5, count 0 2006.173.10:05:25.24#ibcon#wrote, iclass 5, count 0 2006.173.10:05:25.24#ibcon#about to read 3, iclass 5, count 0 2006.173.10:05:25.28#ibcon#read 3, iclass 5, count 0 2006.173.10:05:25.28#ibcon#about to read 4, iclass 5, count 0 2006.173.10:05:25.28#ibcon#read 4, iclass 5, count 0 2006.173.10:05:25.28#ibcon#about to read 5, iclass 5, count 0 2006.173.10:05:25.28#ibcon#read 5, iclass 5, count 0 2006.173.10:05:25.28#ibcon#about to read 6, iclass 5, count 0 2006.173.10:05:25.28#ibcon#read 6, iclass 5, count 0 2006.173.10:05:25.28#ibcon#end of sib2, iclass 5, count 0 2006.173.10:05:25.28#ibcon#*after write, iclass 5, count 0 2006.173.10:05:25.28#ibcon#*before return 0, iclass 5, count 0 2006.173.10:05:25.28#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.10:05:25.28#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.10:05:25.28#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.10:05:25.28#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.10:05:25.28$vck44/va=4,6 2006.173.10:05:25.28#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.173.10:05:25.28#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.173.10:05:25.28#ibcon#ireg 11 cls_cnt 2 2006.173.10:05:25.28#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.10:05:25.34#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.10:05:25.34#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.10:05:25.34#ibcon#enter wrdev, iclass 7, count 2 2006.173.10:05:25.34#ibcon#first serial, iclass 7, count 2 2006.173.10:05:25.34#ibcon#enter sib2, iclass 7, count 2 2006.173.10:05:25.34#ibcon#flushed, iclass 7, count 2 2006.173.10:05:25.34#ibcon#about to write, iclass 7, count 2 2006.173.10:05:25.34#ibcon#wrote, iclass 7, count 2 2006.173.10:05:25.34#ibcon#about to read 3, iclass 7, count 2 2006.173.10:05:25.36#ibcon#read 3, iclass 7, count 2 2006.173.10:05:25.36#ibcon#about to read 4, iclass 7, count 2 2006.173.10:05:25.36#ibcon#read 4, iclass 7, count 2 2006.173.10:05:25.36#ibcon#about to read 5, iclass 7, count 2 2006.173.10:05:25.36#ibcon#read 5, iclass 7, count 2 2006.173.10:05:25.36#ibcon#about to read 6, iclass 7, count 2 2006.173.10:05:25.36#ibcon#read 6, iclass 7, count 2 2006.173.10:05:25.36#ibcon#end of sib2, iclass 7, count 2 2006.173.10:05:25.36#ibcon#*mode == 0, iclass 7, count 2 2006.173.10:05:25.36#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.173.10:05:25.36#ibcon#[25=AT04-06\r\n] 2006.173.10:05:25.36#ibcon#*before write, iclass 7, count 2 2006.173.10:05:25.36#ibcon#enter sib2, iclass 7, count 2 2006.173.10:05:25.36#ibcon#flushed, iclass 7, count 2 2006.173.10:05:25.36#ibcon#about to write, iclass 7, count 2 2006.173.10:05:25.36#ibcon#wrote, iclass 7, count 2 2006.173.10:05:25.36#ibcon#about to read 3, iclass 7, count 2 2006.173.10:05:25.39#ibcon#read 3, iclass 7, count 2 2006.173.10:05:25.39#ibcon#about to read 4, iclass 7, count 2 2006.173.10:05:25.39#ibcon#read 4, iclass 7, count 2 2006.173.10:05:25.39#ibcon#about to read 5, iclass 7, count 2 2006.173.10:05:25.39#ibcon#read 5, iclass 7, count 2 2006.173.10:05:25.39#ibcon#about to read 6, iclass 7, count 2 2006.173.10:05:25.39#ibcon#read 6, iclass 7, count 2 2006.173.10:05:25.39#ibcon#end of sib2, iclass 7, count 2 2006.173.10:05:25.39#ibcon#*after write, iclass 7, count 2 2006.173.10:05:25.39#ibcon#*before return 0, iclass 7, count 2 2006.173.10:05:25.39#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.10:05:25.39#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.173.10:05:25.39#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.173.10:05:25.39#ibcon#ireg 7 cls_cnt 0 2006.173.10:05:25.39#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.10:05:25.51#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.10:05:25.51#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.10:05:25.51#ibcon#enter wrdev, iclass 7, count 0 2006.173.10:05:25.51#ibcon#first serial, iclass 7, count 0 2006.173.10:05:25.51#ibcon#enter sib2, iclass 7, count 0 2006.173.10:05:25.51#ibcon#flushed, iclass 7, count 0 2006.173.10:05:25.51#ibcon#about to write, iclass 7, count 0 2006.173.10:05:25.51#ibcon#wrote, iclass 7, count 0 2006.173.10:05:25.51#ibcon#about to read 3, iclass 7, count 0 2006.173.10:05:25.53#ibcon#read 3, iclass 7, count 0 2006.173.10:05:25.53#ibcon#about to read 4, iclass 7, count 0 2006.173.10:05:25.53#ibcon#read 4, iclass 7, count 0 2006.173.10:05:25.53#ibcon#about to read 5, iclass 7, count 0 2006.173.10:05:25.53#ibcon#read 5, iclass 7, count 0 2006.173.10:05:25.53#ibcon#about to read 6, iclass 7, count 0 2006.173.10:05:25.53#ibcon#read 6, iclass 7, count 0 2006.173.10:05:25.53#ibcon#end of sib2, iclass 7, count 0 2006.173.10:05:25.53#ibcon#*mode == 0, iclass 7, count 0 2006.173.10:05:25.53#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.10:05:25.53#ibcon#[25=USB\r\n] 2006.173.10:05:25.53#ibcon#*before write, iclass 7, count 0 2006.173.10:05:25.53#ibcon#enter sib2, iclass 7, count 0 2006.173.10:05:25.53#ibcon#flushed, iclass 7, count 0 2006.173.10:05:25.53#ibcon#about to write, iclass 7, count 0 2006.173.10:05:25.53#ibcon#wrote, iclass 7, count 0 2006.173.10:05:25.53#ibcon#about to read 3, iclass 7, count 0 2006.173.10:05:25.56#ibcon#read 3, iclass 7, count 0 2006.173.10:05:25.56#ibcon#about to read 4, iclass 7, count 0 2006.173.10:05:25.56#ibcon#read 4, iclass 7, count 0 2006.173.10:05:25.56#ibcon#about to read 5, iclass 7, count 0 2006.173.10:05:25.56#ibcon#read 5, iclass 7, count 0 2006.173.10:05:25.56#ibcon#about to read 6, iclass 7, count 0 2006.173.10:05:25.56#ibcon#read 6, iclass 7, count 0 2006.173.10:05:25.56#ibcon#end of sib2, iclass 7, count 0 2006.173.10:05:25.56#ibcon#*after write, iclass 7, count 0 2006.173.10:05:25.56#ibcon#*before return 0, iclass 7, count 0 2006.173.10:05:25.56#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.10:05:25.56#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.173.10:05:25.56#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.10:05:25.56#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.10:05:25.56$vck44/valo=5,734.99 2006.173.10:05:25.56#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.10:05:25.56#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.10:05:25.56#ibcon#ireg 17 cls_cnt 0 2006.173.10:05:25.56#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.10:05:25.56#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.10:05:25.56#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.10:05:25.56#ibcon#enter wrdev, iclass 11, count 0 2006.173.10:05:25.56#ibcon#first serial, iclass 11, count 0 2006.173.10:05:25.56#ibcon#enter sib2, iclass 11, count 0 2006.173.10:05:25.56#ibcon#flushed, iclass 11, count 0 2006.173.10:05:25.56#ibcon#about to write, iclass 11, count 0 2006.173.10:05:25.56#ibcon#wrote, iclass 11, count 0 2006.173.10:05:25.56#ibcon#about to read 3, iclass 11, count 0 2006.173.10:05:25.58#ibcon#read 3, iclass 11, count 0 2006.173.10:05:25.58#ibcon#about to read 4, iclass 11, count 0 2006.173.10:05:25.58#ibcon#read 4, iclass 11, count 0 2006.173.10:05:25.58#ibcon#about to read 5, iclass 11, count 0 2006.173.10:05:25.58#ibcon#read 5, iclass 11, count 0 2006.173.10:05:25.58#ibcon#about to read 6, iclass 11, count 0 2006.173.10:05:25.58#ibcon#read 6, iclass 11, count 0 2006.173.10:05:25.58#ibcon#end of sib2, iclass 11, count 0 2006.173.10:05:25.58#ibcon#*mode == 0, iclass 11, count 0 2006.173.10:05:25.58#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.10:05:25.58#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.10:05:25.58#ibcon#*before write, iclass 11, count 0 2006.173.10:05:25.58#ibcon#enter sib2, iclass 11, count 0 2006.173.10:05:25.58#ibcon#flushed, iclass 11, count 0 2006.173.10:05:25.58#ibcon#about to write, iclass 11, count 0 2006.173.10:05:25.58#ibcon#wrote, iclass 11, count 0 2006.173.10:05:25.58#ibcon#about to read 3, iclass 11, count 0 2006.173.10:05:25.62#ibcon#read 3, iclass 11, count 0 2006.173.10:05:25.62#ibcon#about to read 4, iclass 11, count 0 2006.173.10:05:25.62#ibcon#read 4, iclass 11, count 0 2006.173.10:05:25.62#ibcon#about to read 5, iclass 11, count 0 2006.173.10:05:25.62#ibcon#read 5, iclass 11, count 0 2006.173.10:05:25.62#ibcon#about to read 6, iclass 11, count 0 2006.173.10:05:25.62#ibcon#read 6, iclass 11, count 0 2006.173.10:05:25.62#ibcon#end of sib2, iclass 11, count 0 2006.173.10:05:25.62#ibcon#*after write, iclass 11, count 0 2006.173.10:05:25.62#ibcon#*before return 0, iclass 11, count 0 2006.173.10:05:25.62#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.10:05:25.62#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.10:05:25.62#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.10:05:25.62#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.10:05:25.62$vck44/va=5,4 2006.173.10:05:25.62#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.173.10:05:25.62#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.173.10:05:25.62#ibcon#ireg 11 cls_cnt 2 2006.173.10:05:25.62#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.10:05:25.68#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.10:05:25.68#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.10:05:25.68#ibcon#enter wrdev, iclass 13, count 2 2006.173.10:05:25.68#ibcon#first serial, iclass 13, count 2 2006.173.10:05:25.68#ibcon#enter sib2, iclass 13, count 2 2006.173.10:05:25.68#ibcon#flushed, iclass 13, count 2 2006.173.10:05:25.68#ibcon#about to write, iclass 13, count 2 2006.173.10:05:25.68#ibcon#wrote, iclass 13, count 2 2006.173.10:05:25.68#ibcon#about to read 3, iclass 13, count 2 2006.173.10:05:25.70#ibcon#read 3, iclass 13, count 2 2006.173.10:05:25.70#ibcon#about to read 4, iclass 13, count 2 2006.173.10:05:25.70#ibcon#read 4, iclass 13, count 2 2006.173.10:05:25.70#ibcon#about to read 5, iclass 13, count 2 2006.173.10:05:25.70#ibcon#read 5, iclass 13, count 2 2006.173.10:05:25.70#ibcon#about to read 6, iclass 13, count 2 2006.173.10:05:25.70#ibcon#read 6, iclass 13, count 2 2006.173.10:05:25.70#ibcon#end of sib2, iclass 13, count 2 2006.173.10:05:25.70#ibcon#*mode == 0, iclass 13, count 2 2006.173.10:05:25.70#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.173.10:05:25.70#ibcon#[25=AT05-04\r\n] 2006.173.10:05:25.70#ibcon#*before write, iclass 13, count 2 2006.173.10:05:25.70#ibcon#enter sib2, iclass 13, count 2 2006.173.10:05:25.70#ibcon#flushed, iclass 13, count 2 2006.173.10:05:25.70#ibcon#about to write, iclass 13, count 2 2006.173.10:05:25.70#ibcon#wrote, iclass 13, count 2 2006.173.10:05:25.70#ibcon#about to read 3, iclass 13, count 2 2006.173.10:05:25.73#ibcon#read 3, iclass 13, count 2 2006.173.10:05:25.73#ibcon#about to read 4, iclass 13, count 2 2006.173.10:05:25.73#ibcon#read 4, iclass 13, count 2 2006.173.10:05:25.73#ibcon#about to read 5, iclass 13, count 2 2006.173.10:05:25.73#ibcon#read 5, iclass 13, count 2 2006.173.10:05:25.73#ibcon#about to read 6, iclass 13, count 2 2006.173.10:05:25.73#ibcon#read 6, iclass 13, count 2 2006.173.10:05:25.73#ibcon#end of sib2, iclass 13, count 2 2006.173.10:05:25.73#ibcon#*after write, iclass 13, count 2 2006.173.10:05:25.73#ibcon#*before return 0, iclass 13, count 2 2006.173.10:05:25.73#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.10:05:25.73#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.173.10:05:25.73#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.173.10:05:25.73#ibcon#ireg 7 cls_cnt 0 2006.173.10:05:25.73#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.10:05:25.85#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.10:05:25.85#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.10:05:25.85#ibcon#enter wrdev, iclass 13, count 0 2006.173.10:05:25.85#ibcon#first serial, iclass 13, count 0 2006.173.10:05:25.85#ibcon#enter sib2, iclass 13, count 0 2006.173.10:05:25.85#ibcon#flushed, iclass 13, count 0 2006.173.10:05:25.85#ibcon#about to write, iclass 13, count 0 2006.173.10:05:25.85#ibcon#wrote, iclass 13, count 0 2006.173.10:05:25.85#ibcon#about to read 3, iclass 13, count 0 2006.173.10:05:25.87#ibcon#read 3, iclass 13, count 0 2006.173.10:05:25.87#ibcon#about to read 4, iclass 13, count 0 2006.173.10:05:25.87#ibcon#read 4, iclass 13, count 0 2006.173.10:05:25.87#ibcon#about to read 5, iclass 13, count 0 2006.173.10:05:25.87#ibcon#read 5, iclass 13, count 0 2006.173.10:05:25.87#ibcon#about to read 6, iclass 13, count 0 2006.173.10:05:25.87#ibcon#read 6, iclass 13, count 0 2006.173.10:05:25.87#ibcon#end of sib2, iclass 13, count 0 2006.173.10:05:25.87#ibcon#*mode == 0, iclass 13, count 0 2006.173.10:05:25.87#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.10:05:25.87#ibcon#[25=USB\r\n] 2006.173.10:05:25.87#ibcon#*before write, iclass 13, count 0 2006.173.10:05:25.87#ibcon#enter sib2, iclass 13, count 0 2006.173.10:05:25.87#ibcon#flushed, iclass 13, count 0 2006.173.10:05:25.87#ibcon#about to write, iclass 13, count 0 2006.173.10:05:25.87#ibcon#wrote, iclass 13, count 0 2006.173.10:05:25.87#ibcon#about to read 3, iclass 13, count 0 2006.173.10:05:25.90#ibcon#read 3, iclass 13, count 0 2006.173.10:05:25.90#ibcon#about to read 4, iclass 13, count 0 2006.173.10:05:25.90#ibcon#read 4, iclass 13, count 0 2006.173.10:05:25.90#ibcon#about to read 5, iclass 13, count 0 2006.173.10:05:25.90#ibcon#read 5, iclass 13, count 0 2006.173.10:05:25.90#ibcon#about to read 6, iclass 13, count 0 2006.173.10:05:25.90#ibcon#read 6, iclass 13, count 0 2006.173.10:05:25.90#ibcon#end of sib2, iclass 13, count 0 2006.173.10:05:25.90#ibcon#*after write, iclass 13, count 0 2006.173.10:05:25.90#ibcon#*before return 0, iclass 13, count 0 2006.173.10:05:25.90#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.10:05:25.90#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.173.10:05:25.90#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.10:05:25.90#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.10:05:25.90$vck44/valo=6,814.99 2006.173.10:05:25.90#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.10:05:25.90#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.10:05:25.90#ibcon#ireg 17 cls_cnt 0 2006.173.10:05:25.90#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.10:05:25.90#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.10:05:25.90#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.10:05:25.90#ibcon#enter wrdev, iclass 15, count 0 2006.173.10:05:25.90#ibcon#first serial, iclass 15, count 0 2006.173.10:05:25.90#ibcon#enter sib2, iclass 15, count 0 2006.173.10:05:25.90#ibcon#flushed, iclass 15, count 0 2006.173.10:05:25.90#ibcon#about to write, iclass 15, count 0 2006.173.10:05:25.90#ibcon#wrote, iclass 15, count 0 2006.173.10:05:25.90#ibcon#about to read 3, iclass 15, count 0 2006.173.10:05:25.92#ibcon#read 3, iclass 15, count 0 2006.173.10:05:25.92#ibcon#about to read 4, iclass 15, count 0 2006.173.10:05:25.92#ibcon#read 4, iclass 15, count 0 2006.173.10:05:25.92#ibcon#about to read 5, iclass 15, count 0 2006.173.10:05:25.92#ibcon#read 5, iclass 15, count 0 2006.173.10:05:25.92#ibcon#about to read 6, iclass 15, count 0 2006.173.10:05:25.92#ibcon#read 6, iclass 15, count 0 2006.173.10:05:25.92#ibcon#end of sib2, iclass 15, count 0 2006.173.10:05:25.92#ibcon#*mode == 0, iclass 15, count 0 2006.173.10:05:25.92#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.10:05:25.92#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.10:05:25.92#ibcon#*before write, iclass 15, count 0 2006.173.10:05:25.92#ibcon#enter sib2, iclass 15, count 0 2006.173.10:05:25.92#ibcon#flushed, iclass 15, count 0 2006.173.10:05:25.92#ibcon#about to write, iclass 15, count 0 2006.173.10:05:25.92#ibcon#wrote, iclass 15, count 0 2006.173.10:05:25.92#ibcon#about to read 3, iclass 15, count 0 2006.173.10:05:25.96#ibcon#read 3, iclass 15, count 0 2006.173.10:05:25.96#ibcon#about to read 4, iclass 15, count 0 2006.173.10:05:25.96#ibcon#read 4, iclass 15, count 0 2006.173.10:05:25.96#ibcon#about to read 5, iclass 15, count 0 2006.173.10:05:25.96#ibcon#read 5, iclass 15, count 0 2006.173.10:05:25.96#ibcon#about to read 6, iclass 15, count 0 2006.173.10:05:25.96#ibcon#read 6, iclass 15, count 0 2006.173.10:05:25.96#ibcon#end of sib2, iclass 15, count 0 2006.173.10:05:25.96#ibcon#*after write, iclass 15, count 0 2006.173.10:05:25.96#ibcon#*before return 0, iclass 15, count 0 2006.173.10:05:25.96#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.10:05:25.96#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.10:05:25.96#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.10:05:25.96#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.10:05:25.96$vck44/va=6,3 2006.173.10:05:25.96#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.10:05:25.96#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.10:05:25.96#ibcon#ireg 11 cls_cnt 2 2006.173.10:05:25.96#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.10:05:26.02#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.10:05:26.02#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.10:05:26.02#ibcon#enter wrdev, iclass 17, count 2 2006.173.10:05:26.02#ibcon#first serial, iclass 17, count 2 2006.173.10:05:26.02#ibcon#enter sib2, iclass 17, count 2 2006.173.10:05:26.02#ibcon#flushed, iclass 17, count 2 2006.173.10:05:26.02#ibcon#about to write, iclass 17, count 2 2006.173.10:05:26.02#ibcon#wrote, iclass 17, count 2 2006.173.10:05:26.02#ibcon#about to read 3, iclass 17, count 2 2006.173.10:05:26.04#ibcon#read 3, iclass 17, count 2 2006.173.10:05:26.04#ibcon#about to read 4, iclass 17, count 2 2006.173.10:05:26.04#ibcon#read 4, iclass 17, count 2 2006.173.10:05:26.04#ibcon#about to read 5, iclass 17, count 2 2006.173.10:05:26.04#ibcon#read 5, iclass 17, count 2 2006.173.10:05:26.04#ibcon#about to read 6, iclass 17, count 2 2006.173.10:05:26.04#ibcon#read 6, iclass 17, count 2 2006.173.10:05:26.04#ibcon#end of sib2, iclass 17, count 2 2006.173.10:05:26.04#ibcon#*mode == 0, iclass 17, count 2 2006.173.10:05:26.04#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.10:05:26.04#ibcon#[25=AT06-03\r\n] 2006.173.10:05:26.04#ibcon#*before write, iclass 17, count 2 2006.173.10:05:26.04#ibcon#enter sib2, iclass 17, count 2 2006.173.10:05:26.04#ibcon#flushed, iclass 17, count 2 2006.173.10:05:26.04#ibcon#about to write, iclass 17, count 2 2006.173.10:05:26.04#ibcon#wrote, iclass 17, count 2 2006.173.10:05:26.04#ibcon#about to read 3, iclass 17, count 2 2006.173.10:05:26.07#ibcon#read 3, iclass 17, count 2 2006.173.10:05:26.07#ibcon#about to read 4, iclass 17, count 2 2006.173.10:05:26.07#ibcon#read 4, iclass 17, count 2 2006.173.10:05:26.07#ibcon#about to read 5, iclass 17, count 2 2006.173.10:05:26.07#ibcon#read 5, iclass 17, count 2 2006.173.10:05:26.07#ibcon#about to read 6, iclass 17, count 2 2006.173.10:05:26.07#ibcon#read 6, iclass 17, count 2 2006.173.10:05:26.07#ibcon#end of sib2, iclass 17, count 2 2006.173.10:05:26.07#ibcon#*after write, iclass 17, count 2 2006.173.10:05:26.07#ibcon#*before return 0, iclass 17, count 2 2006.173.10:05:26.07#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.10:05:26.07#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.10:05:26.07#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.10:05:26.07#ibcon#ireg 7 cls_cnt 0 2006.173.10:05:26.07#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.10:05:26.19#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.10:05:26.19#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.10:05:26.19#ibcon#enter wrdev, iclass 17, count 0 2006.173.10:05:26.19#ibcon#first serial, iclass 17, count 0 2006.173.10:05:26.19#ibcon#enter sib2, iclass 17, count 0 2006.173.10:05:26.19#ibcon#flushed, iclass 17, count 0 2006.173.10:05:26.19#ibcon#about to write, iclass 17, count 0 2006.173.10:05:26.19#ibcon#wrote, iclass 17, count 0 2006.173.10:05:26.19#ibcon#about to read 3, iclass 17, count 0 2006.173.10:05:26.21#ibcon#read 3, iclass 17, count 0 2006.173.10:05:26.21#ibcon#about to read 4, iclass 17, count 0 2006.173.10:05:26.21#ibcon#read 4, iclass 17, count 0 2006.173.10:05:26.21#ibcon#about to read 5, iclass 17, count 0 2006.173.10:05:26.21#ibcon#read 5, iclass 17, count 0 2006.173.10:05:26.21#ibcon#about to read 6, iclass 17, count 0 2006.173.10:05:26.21#ibcon#read 6, iclass 17, count 0 2006.173.10:05:26.21#ibcon#end of sib2, iclass 17, count 0 2006.173.10:05:26.21#ibcon#*mode == 0, iclass 17, count 0 2006.173.10:05:26.21#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.10:05:26.21#ibcon#[25=USB\r\n] 2006.173.10:05:26.21#ibcon#*before write, iclass 17, count 0 2006.173.10:05:26.21#ibcon#enter sib2, iclass 17, count 0 2006.173.10:05:26.21#ibcon#flushed, iclass 17, count 0 2006.173.10:05:26.21#ibcon#about to write, iclass 17, count 0 2006.173.10:05:26.21#ibcon#wrote, iclass 17, count 0 2006.173.10:05:26.21#ibcon#about to read 3, iclass 17, count 0 2006.173.10:05:26.24#ibcon#read 3, iclass 17, count 0 2006.173.10:05:26.24#ibcon#about to read 4, iclass 17, count 0 2006.173.10:05:26.24#ibcon#read 4, iclass 17, count 0 2006.173.10:05:26.24#ibcon#about to read 5, iclass 17, count 0 2006.173.10:05:26.24#ibcon#read 5, iclass 17, count 0 2006.173.10:05:26.24#ibcon#about to read 6, iclass 17, count 0 2006.173.10:05:26.24#ibcon#read 6, iclass 17, count 0 2006.173.10:05:26.24#ibcon#end of sib2, iclass 17, count 0 2006.173.10:05:26.24#ibcon#*after write, iclass 17, count 0 2006.173.10:05:26.24#ibcon#*before return 0, iclass 17, count 0 2006.173.10:05:26.24#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.10:05:26.24#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.10:05:26.24#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.10:05:26.24#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.10:05:26.24$vck44/valo=7,864.99 2006.173.10:05:26.24#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.10:05:26.24#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.10:05:26.24#ibcon#ireg 17 cls_cnt 0 2006.173.10:05:26.24#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.10:05:26.24#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.10:05:26.24#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.10:05:26.24#ibcon#enter wrdev, iclass 19, count 0 2006.173.10:05:26.24#ibcon#first serial, iclass 19, count 0 2006.173.10:05:26.24#ibcon#enter sib2, iclass 19, count 0 2006.173.10:05:26.24#ibcon#flushed, iclass 19, count 0 2006.173.10:05:26.24#ibcon#about to write, iclass 19, count 0 2006.173.10:05:26.24#ibcon#wrote, iclass 19, count 0 2006.173.10:05:26.24#ibcon#about to read 3, iclass 19, count 0 2006.173.10:05:26.26#ibcon#read 3, iclass 19, count 0 2006.173.10:05:26.26#ibcon#about to read 4, iclass 19, count 0 2006.173.10:05:26.26#ibcon#read 4, iclass 19, count 0 2006.173.10:05:26.26#ibcon#about to read 5, iclass 19, count 0 2006.173.10:05:26.26#ibcon#read 5, iclass 19, count 0 2006.173.10:05:26.26#ibcon#about to read 6, iclass 19, count 0 2006.173.10:05:26.26#ibcon#read 6, iclass 19, count 0 2006.173.10:05:26.26#ibcon#end of sib2, iclass 19, count 0 2006.173.10:05:26.26#ibcon#*mode == 0, iclass 19, count 0 2006.173.10:05:26.26#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.10:05:26.26#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.10:05:26.26#ibcon#*before write, iclass 19, count 0 2006.173.10:05:26.26#ibcon#enter sib2, iclass 19, count 0 2006.173.10:05:26.26#ibcon#flushed, iclass 19, count 0 2006.173.10:05:26.26#ibcon#about to write, iclass 19, count 0 2006.173.10:05:26.26#ibcon#wrote, iclass 19, count 0 2006.173.10:05:26.26#ibcon#about to read 3, iclass 19, count 0 2006.173.10:05:26.30#ibcon#read 3, iclass 19, count 0 2006.173.10:05:26.30#ibcon#about to read 4, iclass 19, count 0 2006.173.10:05:26.30#ibcon#read 4, iclass 19, count 0 2006.173.10:05:26.30#ibcon#about to read 5, iclass 19, count 0 2006.173.10:05:26.30#ibcon#read 5, iclass 19, count 0 2006.173.10:05:26.30#ibcon#about to read 6, iclass 19, count 0 2006.173.10:05:26.30#ibcon#read 6, iclass 19, count 0 2006.173.10:05:26.30#ibcon#end of sib2, iclass 19, count 0 2006.173.10:05:26.30#ibcon#*after write, iclass 19, count 0 2006.173.10:05:26.30#ibcon#*before return 0, iclass 19, count 0 2006.173.10:05:26.30#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.10:05:26.30#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.10:05:26.30#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.10:05:26.30#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.10:05:26.30$vck44/va=7,4 2006.173.10:05:26.30#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.10:05:26.30#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.10:05:26.30#ibcon#ireg 11 cls_cnt 2 2006.173.10:05:26.30#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.10:05:26.34#abcon#<5=/06 1.2 1.7 22.83 931004.1\r\n> 2006.173.10:05:26.36#abcon#{5=INTERFACE CLEAR} 2006.173.10:05:26.36#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.10:05:26.36#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.10:05:26.36#ibcon#enter wrdev, iclass 22, count 2 2006.173.10:05:26.36#ibcon#first serial, iclass 22, count 2 2006.173.10:05:26.36#ibcon#enter sib2, iclass 22, count 2 2006.173.10:05:26.36#ibcon#flushed, iclass 22, count 2 2006.173.10:05:26.36#ibcon#about to write, iclass 22, count 2 2006.173.10:05:26.36#ibcon#wrote, iclass 22, count 2 2006.173.10:05:26.36#ibcon#about to read 3, iclass 22, count 2 2006.173.10:05:26.38#ibcon#read 3, iclass 22, count 2 2006.173.10:05:26.38#ibcon#about to read 4, iclass 22, count 2 2006.173.10:05:26.38#ibcon#read 4, iclass 22, count 2 2006.173.10:05:26.38#ibcon#about to read 5, iclass 22, count 2 2006.173.10:05:26.38#ibcon#read 5, iclass 22, count 2 2006.173.10:05:26.38#ibcon#about to read 6, iclass 22, count 2 2006.173.10:05:26.38#ibcon#read 6, iclass 22, count 2 2006.173.10:05:26.38#ibcon#end of sib2, iclass 22, count 2 2006.173.10:05:26.38#ibcon#*mode == 0, iclass 22, count 2 2006.173.10:05:26.38#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.10:05:26.38#ibcon#[25=AT07-04\r\n] 2006.173.10:05:26.38#ibcon#*before write, iclass 22, count 2 2006.173.10:05:26.38#ibcon#enter sib2, iclass 22, count 2 2006.173.10:05:26.38#ibcon#flushed, iclass 22, count 2 2006.173.10:05:26.38#ibcon#about to write, iclass 22, count 2 2006.173.10:05:26.38#ibcon#wrote, iclass 22, count 2 2006.173.10:05:26.38#ibcon#about to read 3, iclass 22, count 2 2006.173.10:05:26.41#ibcon#read 3, iclass 22, count 2 2006.173.10:05:26.41#ibcon#about to read 4, iclass 22, count 2 2006.173.10:05:26.41#ibcon#read 4, iclass 22, count 2 2006.173.10:05:26.41#ibcon#about to read 5, iclass 22, count 2 2006.173.10:05:26.41#ibcon#read 5, iclass 22, count 2 2006.173.10:05:26.41#ibcon#about to read 6, iclass 22, count 2 2006.173.10:05:26.41#ibcon#read 6, iclass 22, count 2 2006.173.10:05:26.41#ibcon#end of sib2, iclass 22, count 2 2006.173.10:05:26.41#ibcon#*after write, iclass 22, count 2 2006.173.10:05:26.41#ibcon#*before return 0, iclass 22, count 2 2006.173.10:05:26.41#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.10:05:26.41#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.10:05:26.41#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.10:05:26.41#ibcon#ireg 7 cls_cnt 0 2006.173.10:05:26.41#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.10:05:26.42#abcon#[5=S1D000X0/0*\r\n] 2006.173.10:05:26.53#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.10:05:26.53#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.10:05:26.53#ibcon#enter wrdev, iclass 22, count 0 2006.173.10:05:26.53#ibcon#first serial, iclass 22, count 0 2006.173.10:05:26.53#ibcon#enter sib2, iclass 22, count 0 2006.173.10:05:26.53#ibcon#flushed, iclass 22, count 0 2006.173.10:05:26.53#ibcon#about to write, iclass 22, count 0 2006.173.10:05:26.53#ibcon#wrote, iclass 22, count 0 2006.173.10:05:26.53#ibcon#about to read 3, iclass 22, count 0 2006.173.10:05:26.55#ibcon#read 3, iclass 22, count 0 2006.173.10:05:26.55#ibcon#about to read 4, iclass 22, count 0 2006.173.10:05:26.55#ibcon#read 4, iclass 22, count 0 2006.173.10:05:26.55#ibcon#about to read 5, iclass 22, count 0 2006.173.10:05:26.55#ibcon#read 5, iclass 22, count 0 2006.173.10:05:26.55#ibcon#about to read 6, iclass 22, count 0 2006.173.10:05:26.55#ibcon#read 6, iclass 22, count 0 2006.173.10:05:26.55#ibcon#end of sib2, iclass 22, count 0 2006.173.10:05:26.55#ibcon#*mode == 0, iclass 22, count 0 2006.173.10:05:26.55#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.10:05:26.55#ibcon#[25=USB\r\n] 2006.173.10:05:26.55#ibcon#*before write, iclass 22, count 0 2006.173.10:05:26.55#ibcon#enter sib2, iclass 22, count 0 2006.173.10:05:26.55#ibcon#flushed, iclass 22, count 0 2006.173.10:05:26.55#ibcon#about to write, iclass 22, count 0 2006.173.10:05:26.55#ibcon#wrote, iclass 22, count 0 2006.173.10:05:26.55#ibcon#about to read 3, iclass 22, count 0 2006.173.10:05:26.58#ibcon#read 3, iclass 22, count 0 2006.173.10:05:26.58#ibcon#about to read 4, iclass 22, count 0 2006.173.10:05:26.58#ibcon#read 4, iclass 22, count 0 2006.173.10:05:26.58#ibcon#about to read 5, iclass 22, count 0 2006.173.10:05:26.58#ibcon#read 5, iclass 22, count 0 2006.173.10:05:26.58#ibcon#about to read 6, iclass 22, count 0 2006.173.10:05:26.58#ibcon#read 6, iclass 22, count 0 2006.173.10:05:26.58#ibcon#end of sib2, iclass 22, count 0 2006.173.10:05:26.58#ibcon#*after write, iclass 22, count 0 2006.173.10:05:26.58#ibcon#*before return 0, iclass 22, count 0 2006.173.10:05:26.58#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.10:05:26.58#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.10:05:26.58#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.10:05:26.58#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.10:05:26.58$vck44/valo=8,884.99 2006.173.10:05:26.58#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.10:05:26.58#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.10:05:26.58#ibcon#ireg 17 cls_cnt 0 2006.173.10:05:26.58#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.10:05:26.58#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.10:05:26.58#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.10:05:26.58#ibcon#enter wrdev, iclass 27, count 0 2006.173.10:05:26.58#ibcon#first serial, iclass 27, count 0 2006.173.10:05:26.58#ibcon#enter sib2, iclass 27, count 0 2006.173.10:05:26.58#ibcon#flushed, iclass 27, count 0 2006.173.10:05:26.58#ibcon#about to write, iclass 27, count 0 2006.173.10:05:26.58#ibcon#wrote, iclass 27, count 0 2006.173.10:05:26.58#ibcon#about to read 3, iclass 27, count 0 2006.173.10:05:26.60#ibcon#read 3, iclass 27, count 0 2006.173.10:05:26.60#ibcon#about to read 4, iclass 27, count 0 2006.173.10:05:26.60#ibcon#read 4, iclass 27, count 0 2006.173.10:05:26.60#ibcon#about to read 5, iclass 27, count 0 2006.173.10:05:26.60#ibcon#read 5, iclass 27, count 0 2006.173.10:05:26.60#ibcon#about to read 6, iclass 27, count 0 2006.173.10:05:26.60#ibcon#read 6, iclass 27, count 0 2006.173.10:05:26.60#ibcon#end of sib2, iclass 27, count 0 2006.173.10:05:26.60#ibcon#*mode == 0, iclass 27, count 0 2006.173.10:05:26.60#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.10:05:26.60#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.10:05:26.60#ibcon#*before write, iclass 27, count 0 2006.173.10:05:26.60#ibcon#enter sib2, iclass 27, count 0 2006.173.10:05:26.60#ibcon#flushed, iclass 27, count 0 2006.173.10:05:26.60#ibcon#about to write, iclass 27, count 0 2006.173.10:05:26.60#ibcon#wrote, iclass 27, count 0 2006.173.10:05:26.60#ibcon#about to read 3, iclass 27, count 0 2006.173.10:05:26.64#ibcon#read 3, iclass 27, count 0 2006.173.10:05:26.64#ibcon#about to read 4, iclass 27, count 0 2006.173.10:05:26.64#ibcon#read 4, iclass 27, count 0 2006.173.10:05:26.64#ibcon#about to read 5, iclass 27, count 0 2006.173.10:05:26.64#ibcon#read 5, iclass 27, count 0 2006.173.10:05:26.64#ibcon#about to read 6, iclass 27, count 0 2006.173.10:05:26.64#ibcon#read 6, iclass 27, count 0 2006.173.10:05:26.64#ibcon#end of sib2, iclass 27, count 0 2006.173.10:05:26.64#ibcon#*after write, iclass 27, count 0 2006.173.10:05:26.64#ibcon#*before return 0, iclass 27, count 0 2006.173.10:05:26.64#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.10:05:26.64#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.10:05:26.64#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.10:05:26.64#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.10:05:26.64$vck44/va=8,4 2006.173.10:05:26.64#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.10:05:26.64#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.10:05:26.64#ibcon#ireg 11 cls_cnt 2 2006.173.10:05:26.64#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.10:05:26.70#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.10:05:26.70#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.10:05:26.70#ibcon#enter wrdev, iclass 29, count 2 2006.173.10:05:26.70#ibcon#first serial, iclass 29, count 2 2006.173.10:05:26.70#ibcon#enter sib2, iclass 29, count 2 2006.173.10:05:26.70#ibcon#flushed, iclass 29, count 2 2006.173.10:05:26.70#ibcon#about to write, iclass 29, count 2 2006.173.10:05:26.70#ibcon#wrote, iclass 29, count 2 2006.173.10:05:26.70#ibcon#about to read 3, iclass 29, count 2 2006.173.10:05:26.72#ibcon#read 3, iclass 29, count 2 2006.173.10:05:26.72#ibcon#about to read 4, iclass 29, count 2 2006.173.10:05:26.72#ibcon#read 4, iclass 29, count 2 2006.173.10:05:26.72#ibcon#about to read 5, iclass 29, count 2 2006.173.10:05:26.72#ibcon#read 5, iclass 29, count 2 2006.173.10:05:26.72#ibcon#about to read 6, iclass 29, count 2 2006.173.10:05:26.72#ibcon#read 6, iclass 29, count 2 2006.173.10:05:26.72#ibcon#end of sib2, iclass 29, count 2 2006.173.10:05:26.72#ibcon#*mode == 0, iclass 29, count 2 2006.173.10:05:26.72#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.10:05:26.72#ibcon#[25=AT08-04\r\n] 2006.173.10:05:26.72#ibcon#*before write, iclass 29, count 2 2006.173.10:05:26.72#ibcon#enter sib2, iclass 29, count 2 2006.173.10:05:26.72#ibcon#flushed, iclass 29, count 2 2006.173.10:05:26.72#ibcon#about to write, iclass 29, count 2 2006.173.10:05:26.72#ibcon#wrote, iclass 29, count 2 2006.173.10:05:26.72#ibcon#about to read 3, iclass 29, count 2 2006.173.10:05:26.75#ibcon#read 3, iclass 29, count 2 2006.173.10:05:26.75#ibcon#about to read 4, iclass 29, count 2 2006.173.10:05:26.75#ibcon#read 4, iclass 29, count 2 2006.173.10:05:26.75#ibcon#about to read 5, iclass 29, count 2 2006.173.10:05:26.75#ibcon#read 5, iclass 29, count 2 2006.173.10:05:26.75#ibcon#about to read 6, iclass 29, count 2 2006.173.10:05:26.75#ibcon#read 6, iclass 29, count 2 2006.173.10:05:26.75#ibcon#end of sib2, iclass 29, count 2 2006.173.10:05:26.75#ibcon#*after write, iclass 29, count 2 2006.173.10:05:26.75#ibcon#*before return 0, iclass 29, count 2 2006.173.10:05:26.75#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.10:05:26.75#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.10:05:26.75#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.10:05:26.75#ibcon#ireg 7 cls_cnt 0 2006.173.10:05:26.75#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.10:05:26.87#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.10:05:26.87#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.10:05:26.87#ibcon#enter wrdev, iclass 29, count 0 2006.173.10:05:26.87#ibcon#first serial, iclass 29, count 0 2006.173.10:05:26.87#ibcon#enter sib2, iclass 29, count 0 2006.173.10:05:26.87#ibcon#flushed, iclass 29, count 0 2006.173.10:05:26.87#ibcon#about to write, iclass 29, count 0 2006.173.10:05:26.87#ibcon#wrote, iclass 29, count 0 2006.173.10:05:26.87#ibcon#about to read 3, iclass 29, count 0 2006.173.10:05:26.89#ibcon#read 3, iclass 29, count 0 2006.173.10:05:26.89#ibcon#about to read 4, iclass 29, count 0 2006.173.10:05:26.89#ibcon#read 4, iclass 29, count 0 2006.173.10:05:26.89#ibcon#about to read 5, iclass 29, count 0 2006.173.10:05:26.89#ibcon#read 5, iclass 29, count 0 2006.173.10:05:26.89#ibcon#about to read 6, iclass 29, count 0 2006.173.10:05:26.89#ibcon#read 6, iclass 29, count 0 2006.173.10:05:26.89#ibcon#end of sib2, iclass 29, count 0 2006.173.10:05:26.89#ibcon#*mode == 0, iclass 29, count 0 2006.173.10:05:26.89#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.10:05:26.89#ibcon#[25=USB\r\n] 2006.173.10:05:26.89#ibcon#*before write, iclass 29, count 0 2006.173.10:05:26.89#ibcon#enter sib2, iclass 29, count 0 2006.173.10:05:26.89#ibcon#flushed, iclass 29, count 0 2006.173.10:05:26.89#ibcon#about to write, iclass 29, count 0 2006.173.10:05:26.89#ibcon#wrote, iclass 29, count 0 2006.173.10:05:26.89#ibcon#about to read 3, iclass 29, count 0 2006.173.10:05:26.92#ibcon#read 3, iclass 29, count 0 2006.173.10:05:26.92#ibcon#about to read 4, iclass 29, count 0 2006.173.10:05:26.92#ibcon#read 4, iclass 29, count 0 2006.173.10:05:26.92#ibcon#about to read 5, iclass 29, count 0 2006.173.10:05:26.92#ibcon#read 5, iclass 29, count 0 2006.173.10:05:26.92#ibcon#about to read 6, iclass 29, count 0 2006.173.10:05:26.92#ibcon#read 6, iclass 29, count 0 2006.173.10:05:26.92#ibcon#end of sib2, iclass 29, count 0 2006.173.10:05:26.92#ibcon#*after write, iclass 29, count 0 2006.173.10:05:26.92#ibcon#*before return 0, iclass 29, count 0 2006.173.10:05:26.92#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.10:05:26.92#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.10:05:26.92#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.10:05:26.92#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.10:05:26.92$vck44/vblo=1,629.99 2006.173.10:05:26.92#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.10:05:26.92#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.10:05:26.92#ibcon#ireg 17 cls_cnt 0 2006.173.10:05:26.92#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.10:05:26.92#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.10:05:26.92#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.10:05:26.92#ibcon#enter wrdev, iclass 31, count 0 2006.173.10:05:26.92#ibcon#first serial, iclass 31, count 0 2006.173.10:05:26.92#ibcon#enter sib2, iclass 31, count 0 2006.173.10:05:26.92#ibcon#flushed, iclass 31, count 0 2006.173.10:05:26.92#ibcon#about to write, iclass 31, count 0 2006.173.10:05:26.92#ibcon#wrote, iclass 31, count 0 2006.173.10:05:26.92#ibcon#about to read 3, iclass 31, count 0 2006.173.10:05:26.94#ibcon#read 3, iclass 31, count 0 2006.173.10:05:26.94#ibcon#about to read 4, iclass 31, count 0 2006.173.10:05:26.94#ibcon#read 4, iclass 31, count 0 2006.173.10:05:26.94#ibcon#about to read 5, iclass 31, count 0 2006.173.10:05:26.94#ibcon#read 5, iclass 31, count 0 2006.173.10:05:26.94#ibcon#about to read 6, iclass 31, count 0 2006.173.10:05:26.94#ibcon#read 6, iclass 31, count 0 2006.173.10:05:26.94#ibcon#end of sib2, iclass 31, count 0 2006.173.10:05:26.94#ibcon#*mode == 0, iclass 31, count 0 2006.173.10:05:26.94#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.10:05:26.94#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.10:05:26.94#ibcon#*before write, iclass 31, count 0 2006.173.10:05:26.94#ibcon#enter sib2, iclass 31, count 0 2006.173.10:05:26.94#ibcon#flushed, iclass 31, count 0 2006.173.10:05:26.94#ibcon#about to write, iclass 31, count 0 2006.173.10:05:26.94#ibcon#wrote, iclass 31, count 0 2006.173.10:05:26.94#ibcon#about to read 3, iclass 31, count 0 2006.173.10:05:26.98#ibcon#read 3, iclass 31, count 0 2006.173.10:05:26.98#ibcon#about to read 4, iclass 31, count 0 2006.173.10:05:26.98#ibcon#read 4, iclass 31, count 0 2006.173.10:05:26.98#ibcon#about to read 5, iclass 31, count 0 2006.173.10:05:26.98#ibcon#read 5, iclass 31, count 0 2006.173.10:05:26.98#ibcon#about to read 6, iclass 31, count 0 2006.173.10:05:26.98#ibcon#read 6, iclass 31, count 0 2006.173.10:05:26.98#ibcon#end of sib2, iclass 31, count 0 2006.173.10:05:26.98#ibcon#*after write, iclass 31, count 0 2006.173.10:05:26.98#ibcon#*before return 0, iclass 31, count 0 2006.173.10:05:26.98#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.10:05:26.98#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.10:05:26.98#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.10:05:26.98#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.10:05:26.98$vck44/vb=1,4 2006.173.10:05:26.98#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.173.10:05:26.98#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.173.10:05:26.98#ibcon#ireg 11 cls_cnt 2 2006.173.10:05:26.98#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.10:05:26.98#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.10:05:26.98#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.10:05:26.98#ibcon#enter wrdev, iclass 33, count 2 2006.173.10:05:26.98#ibcon#first serial, iclass 33, count 2 2006.173.10:05:26.98#ibcon#enter sib2, iclass 33, count 2 2006.173.10:05:26.98#ibcon#flushed, iclass 33, count 2 2006.173.10:05:26.98#ibcon#about to write, iclass 33, count 2 2006.173.10:05:26.98#ibcon#wrote, iclass 33, count 2 2006.173.10:05:26.98#ibcon#about to read 3, iclass 33, count 2 2006.173.10:05:27.00#ibcon#read 3, iclass 33, count 2 2006.173.10:05:27.00#ibcon#about to read 4, iclass 33, count 2 2006.173.10:05:27.00#ibcon#read 4, iclass 33, count 2 2006.173.10:05:27.00#ibcon#about to read 5, iclass 33, count 2 2006.173.10:05:27.00#ibcon#read 5, iclass 33, count 2 2006.173.10:05:27.00#ibcon#about to read 6, iclass 33, count 2 2006.173.10:05:27.00#ibcon#read 6, iclass 33, count 2 2006.173.10:05:27.00#ibcon#end of sib2, iclass 33, count 2 2006.173.10:05:27.00#ibcon#*mode == 0, iclass 33, count 2 2006.173.10:05:27.00#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.173.10:05:27.00#ibcon#[27=AT01-04\r\n] 2006.173.10:05:27.00#ibcon#*before write, iclass 33, count 2 2006.173.10:05:27.00#ibcon#enter sib2, iclass 33, count 2 2006.173.10:05:27.00#ibcon#flushed, iclass 33, count 2 2006.173.10:05:27.00#ibcon#about to write, iclass 33, count 2 2006.173.10:05:27.00#ibcon#wrote, iclass 33, count 2 2006.173.10:05:27.00#ibcon#about to read 3, iclass 33, count 2 2006.173.10:05:27.03#ibcon#read 3, iclass 33, count 2 2006.173.10:05:27.03#ibcon#about to read 4, iclass 33, count 2 2006.173.10:05:27.03#ibcon#read 4, iclass 33, count 2 2006.173.10:05:27.03#ibcon#about to read 5, iclass 33, count 2 2006.173.10:05:27.03#ibcon#read 5, iclass 33, count 2 2006.173.10:05:27.03#ibcon#about to read 6, iclass 33, count 2 2006.173.10:05:27.03#ibcon#read 6, iclass 33, count 2 2006.173.10:05:27.03#ibcon#end of sib2, iclass 33, count 2 2006.173.10:05:27.03#ibcon#*after write, iclass 33, count 2 2006.173.10:05:27.03#ibcon#*before return 0, iclass 33, count 2 2006.173.10:05:27.03#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.10:05:27.03#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.173.10:05:27.03#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.173.10:05:27.03#ibcon#ireg 7 cls_cnt 0 2006.173.10:05:27.03#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.10:05:27.15#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.10:05:27.15#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.10:05:27.15#ibcon#enter wrdev, iclass 33, count 0 2006.173.10:05:27.15#ibcon#first serial, iclass 33, count 0 2006.173.10:05:27.15#ibcon#enter sib2, iclass 33, count 0 2006.173.10:05:27.15#ibcon#flushed, iclass 33, count 0 2006.173.10:05:27.15#ibcon#about to write, iclass 33, count 0 2006.173.10:05:27.15#ibcon#wrote, iclass 33, count 0 2006.173.10:05:27.15#ibcon#about to read 3, iclass 33, count 0 2006.173.10:05:27.17#ibcon#read 3, iclass 33, count 0 2006.173.10:05:27.17#ibcon#about to read 4, iclass 33, count 0 2006.173.10:05:27.17#ibcon#read 4, iclass 33, count 0 2006.173.10:05:27.17#ibcon#about to read 5, iclass 33, count 0 2006.173.10:05:27.17#ibcon#read 5, iclass 33, count 0 2006.173.10:05:27.17#ibcon#about to read 6, iclass 33, count 0 2006.173.10:05:27.17#ibcon#read 6, iclass 33, count 0 2006.173.10:05:27.17#ibcon#end of sib2, iclass 33, count 0 2006.173.10:05:27.17#ibcon#*mode == 0, iclass 33, count 0 2006.173.10:05:27.17#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.10:05:27.17#ibcon#[27=USB\r\n] 2006.173.10:05:27.17#ibcon#*before write, iclass 33, count 0 2006.173.10:05:27.17#ibcon#enter sib2, iclass 33, count 0 2006.173.10:05:27.17#ibcon#flushed, iclass 33, count 0 2006.173.10:05:27.17#ibcon#about to write, iclass 33, count 0 2006.173.10:05:27.17#ibcon#wrote, iclass 33, count 0 2006.173.10:05:27.17#ibcon#about to read 3, iclass 33, count 0 2006.173.10:05:27.20#ibcon#read 3, iclass 33, count 0 2006.173.10:05:27.20#ibcon#about to read 4, iclass 33, count 0 2006.173.10:05:27.20#ibcon#read 4, iclass 33, count 0 2006.173.10:05:27.20#ibcon#about to read 5, iclass 33, count 0 2006.173.10:05:27.20#ibcon#read 5, iclass 33, count 0 2006.173.10:05:27.20#ibcon#about to read 6, iclass 33, count 0 2006.173.10:05:27.20#ibcon#read 6, iclass 33, count 0 2006.173.10:05:27.20#ibcon#end of sib2, iclass 33, count 0 2006.173.10:05:27.20#ibcon#*after write, iclass 33, count 0 2006.173.10:05:27.20#ibcon#*before return 0, iclass 33, count 0 2006.173.10:05:27.20#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.10:05:27.20#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.173.10:05:27.20#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.10:05:27.20#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.10:05:27.20$vck44/vblo=2,634.99 2006.173.10:05:27.20#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.10:05:27.20#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.10:05:27.20#ibcon#ireg 17 cls_cnt 0 2006.173.10:05:27.20#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.10:05:27.20#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.10:05:27.20#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.10:05:27.20#ibcon#enter wrdev, iclass 35, count 0 2006.173.10:05:27.20#ibcon#first serial, iclass 35, count 0 2006.173.10:05:27.20#ibcon#enter sib2, iclass 35, count 0 2006.173.10:05:27.20#ibcon#flushed, iclass 35, count 0 2006.173.10:05:27.20#ibcon#about to write, iclass 35, count 0 2006.173.10:05:27.20#ibcon#wrote, iclass 35, count 0 2006.173.10:05:27.20#ibcon#about to read 3, iclass 35, count 0 2006.173.10:05:27.22#ibcon#read 3, iclass 35, count 0 2006.173.10:05:27.22#ibcon#about to read 4, iclass 35, count 0 2006.173.10:05:27.22#ibcon#read 4, iclass 35, count 0 2006.173.10:05:27.22#ibcon#about to read 5, iclass 35, count 0 2006.173.10:05:27.22#ibcon#read 5, iclass 35, count 0 2006.173.10:05:27.22#ibcon#about to read 6, iclass 35, count 0 2006.173.10:05:27.22#ibcon#read 6, iclass 35, count 0 2006.173.10:05:27.22#ibcon#end of sib2, iclass 35, count 0 2006.173.10:05:27.22#ibcon#*mode == 0, iclass 35, count 0 2006.173.10:05:27.22#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.10:05:27.22#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.10:05:27.22#ibcon#*before write, iclass 35, count 0 2006.173.10:05:27.22#ibcon#enter sib2, iclass 35, count 0 2006.173.10:05:27.22#ibcon#flushed, iclass 35, count 0 2006.173.10:05:27.22#ibcon#about to write, iclass 35, count 0 2006.173.10:05:27.22#ibcon#wrote, iclass 35, count 0 2006.173.10:05:27.22#ibcon#about to read 3, iclass 35, count 0 2006.173.10:05:27.26#ibcon#read 3, iclass 35, count 0 2006.173.10:05:27.26#ibcon#about to read 4, iclass 35, count 0 2006.173.10:05:27.26#ibcon#read 4, iclass 35, count 0 2006.173.10:05:27.26#ibcon#about to read 5, iclass 35, count 0 2006.173.10:05:27.26#ibcon#read 5, iclass 35, count 0 2006.173.10:05:27.26#ibcon#about to read 6, iclass 35, count 0 2006.173.10:05:27.26#ibcon#read 6, iclass 35, count 0 2006.173.10:05:27.26#ibcon#end of sib2, iclass 35, count 0 2006.173.10:05:27.26#ibcon#*after write, iclass 35, count 0 2006.173.10:05:27.26#ibcon#*before return 0, iclass 35, count 0 2006.173.10:05:27.26#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.10:05:27.26#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.10:05:27.26#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.10:05:27.26#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.10:05:27.26$vck44/vb=2,4 2006.173.10:05:27.26#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.173.10:05:27.26#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.173.10:05:27.26#ibcon#ireg 11 cls_cnt 2 2006.173.10:05:27.26#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.10:05:27.32#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.10:05:27.32#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.10:05:27.32#ibcon#enter wrdev, iclass 37, count 2 2006.173.10:05:27.32#ibcon#first serial, iclass 37, count 2 2006.173.10:05:27.32#ibcon#enter sib2, iclass 37, count 2 2006.173.10:05:27.32#ibcon#flushed, iclass 37, count 2 2006.173.10:05:27.32#ibcon#about to write, iclass 37, count 2 2006.173.10:05:27.32#ibcon#wrote, iclass 37, count 2 2006.173.10:05:27.32#ibcon#about to read 3, iclass 37, count 2 2006.173.10:05:27.34#ibcon#read 3, iclass 37, count 2 2006.173.10:05:27.34#ibcon#about to read 4, iclass 37, count 2 2006.173.10:05:27.34#ibcon#read 4, iclass 37, count 2 2006.173.10:05:27.34#ibcon#about to read 5, iclass 37, count 2 2006.173.10:05:27.34#ibcon#read 5, iclass 37, count 2 2006.173.10:05:27.34#ibcon#about to read 6, iclass 37, count 2 2006.173.10:05:27.34#ibcon#read 6, iclass 37, count 2 2006.173.10:05:27.34#ibcon#end of sib2, iclass 37, count 2 2006.173.10:05:27.34#ibcon#*mode == 0, iclass 37, count 2 2006.173.10:05:27.34#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.173.10:05:27.34#ibcon#[27=AT02-04\r\n] 2006.173.10:05:27.34#ibcon#*before write, iclass 37, count 2 2006.173.10:05:27.34#ibcon#enter sib2, iclass 37, count 2 2006.173.10:05:27.34#ibcon#flushed, iclass 37, count 2 2006.173.10:05:27.34#ibcon#about to write, iclass 37, count 2 2006.173.10:05:27.34#ibcon#wrote, iclass 37, count 2 2006.173.10:05:27.34#ibcon#about to read 3, iclass 37, count 2 2006.173.10:05:27.37#ibcon#read 3, iclass 37, count 2 2006.173.10:05:27.37#ibcon#about to read 4, iclass 37, count 2 2006.173.10:05:27.37#ibcon#read 4, iclass 37, count 2 2006.173.10:05:27.37#ibcon#about to read 5, iclass 37, count 2 2006.173.10:05:27.37#ibcon#read 5, iclass 37, count 2 2006.173.10:05:27.37#ibcon#about to read 6, iclass 37, count 2 2006.173.10:05:27.37#ibcon#read 6, iclass 37, count 2 2006.173.10:05:27.37#ibcon#end of sib2, iclass 37, count 2 2006.173.10:05:27.37#ibcon#*after write, iclass 37, count 2 2006.173.10:05:27.37#ibcon#*before return 0, iclass 37, count 2 2006.173.10:05:27.37#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.10:05:27.37#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.173.10:05:27.37#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.173.10:05:27.37#ibcon#ireg 7 cls_cnt 0 2006.173.10:05:27.37#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.10:05:27.49#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.10:05:27.49#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.10:05:27.49#ibcon#enter wrdev, iclass 37, count 0 2006.173.10:05:27.49#ibcon#first serial, iclass 37, count 0 2006.173.10:05:27.49#ibcon#enter sib2, iclass 37, count 0 2006.173.10:05:27.49#ibcon#flushed, iclass 37, count 0 2006.173.10:05:27.49#ibcon#about to write, iclass 37, count 0 2006.173.10:05:27.49#ibcon#wrote, iclass 37, count 0 2006.173.10:05:27.49#ibcon#about to read 3, iclass 37, count 0 2006.173.10:05:27.51#ibcon#read 3, iclass 37, count 0 2006.173.10:05:27.51#ibcon#about to read 4, iclass 37, count 0 2006.173.10:05:27.51#ibcon#read 4, iclass 37, count 0 2006.173.10:05:27.51#ibcon#about to read 5, iclass 37, count 0 2006.173.10:05:27.51#ibcon#read 5, iclass 37, count 0 2006.173.10:05:27.51#ibcon#about to read 6, iclass 37, count 0 2006.173.10:05:27.51#ibcon#read 6, iclass 37, count 0 2006.173.10:05:27.51#ibcon#end of sib2, iclass 37, count 0 2006.173.10:05:27.51#ibcon#*mode == 0, iclass 37, count 0 2006.173.10:05:27.51#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.10:05:27.51#ibcon#[27=USB\r\n] 2006.173.10:05:27.51#ibcon#*before write, iclass 37, count 0 2006.173.10:05:27.51#ibcon#enter sib2, iclass 37, count 0 2006.173.10:05:27.51#ibcon#flushed, iclass 37, count 0 2006.173.10:05:27.51#ibcon#about to write, iclass 37, count 0 2006.173.10:05:27.51#ibcon#wrote, iclass 37, count 0 2006.173.10:05:27.51#ibcon#about to read 3, iclass 37, count 0 2006.173.10:05:27.54#ibcon#read 3, iclass 37, count 0 2006.173.10:05:27.54#ibcon#about to read 4, iclass 37, count 0 2006.173.10:05:27.54#ibcon#read 4, iclass 37, count 0 2006.173.10:05:27.54#ibcon#about to read 5, iclass 37, count 0 2006.173.10:05:27.54#ibcon#read 5, iclass 37, count 0 2006.173.10:05:27.54#ibcon#about to read 6, iclass 37, count 0 2006.173.10:05:27.54#ibcon#read 6, iclass 37, count 0 2006.173.10:05:27.54#ibcon#end of sib2, iclass 37, count 0 2006.173.10:05:27.54#ibcon#*after write, iclass 37, count 0 2006.173.10:05:27.54#ibcon#*before return 0, iclass 37, count 0 2006.173.10:05:27.54#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.10:05:27.54#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.173.10:05:27.54#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.10:05:27.54#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.10:05:27.54$vck44/vblo=3,649.99 2006.173.10:05:27.54#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.10:05:27.54#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.10:05:27.54#ibcon#ireg 17 cls_cnt 0 2006.173.10:05:27.54#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.10:05:27.54#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.10:05:27.54#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.10:05:27.54#ibcon#enter wrdev, iclass 39, count 0 2006.173.10:05:27.54#ibcon#first serial, iclass 39, count 0 2006.173.10:05:27.54#ibcon#enter sib2, iclass 39, count 0 2006.173.10:05:27.54#ibcon#flushed, iclass 39, count 0 2006.173.10:05:27.54#ibcon#about to write, iclass 39, count 0 2006.173.10:05:27.54#ibcon#wrote, iclass 39, count 0 2006.173.10:05:27.54#ibcon#about to read 3, iclass 39, count 0 2006.173.10:05:27.56#ibcon#read 3, iclass 39, count 0 2006.173.10:05:27.56#ibcon#about to read 4, iclass 39, count 0 2006.173.10:05:27.56#ibcon#read 4, iclass 39, count 0 2006.173.10:05:27.56#ibcon#about to read 5, iclass 39, count 0 2006.173.10:05:27.56#ibcon#read 5, iclass 39, count 0 2006.173.10:05:27.56#ibcon#about to read 6, iclass 39, count 0 2006.173.10:05:27.56#ibcon#read 6, iclass 39, count 0 2006.173.10:05:27.56#ibcon#end of sib2, iclass 39, count 0 2006.173.10:05:27.56#ibcon#*mode == 0, iclass 39, count 0 2006.173.10:05:27.56#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.10:05:27.56#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.10:05:27.56#ibcon#*before write, iclass 39, count 0 2006.173.10:05:27.56#ibcon#enter sib2, iclass 39, count 0 2006.173.10:05:27.56#ibcon#flushed, iclass 39, count 0 2006.173.10:05:27.56#ibcon#about to write, iclass 39, count 0 2006.173.10:05:27.56#ibcon#wrote, iclass 39, count 0 2006.173.10:05:27.56#ibcon#about to read 3, iclass 39, count 0 2006.173.10:05:27.60#ibcon#read 3, iclass 39, count 0 2006.173.10:05:27.60#ibcon#about to read 4, iclass 39, count 0 2006.173.10:05:27.60#ibcon#read 4, iclass 39, count 0 2006.173.10:05:27.60#ibcon#about to read 5, iclass 39, count 0 2006.173.10:05:27.60#ibcon#read 5, iclass 39, count 0 2006.173.10:05:27.60#ibcon#about to read 6, iclass 39, count 0 2006.173.10:05:27.60#ibcon#read 6, iclass 39, count 0 2006.173.10:05:27.60#ibcon#end of sib2, iclass 39, count 0 2006.173.10:05:27.60#ibcon#*after write, iclass 39, count 0 2006.173.10:05:27.60#ibcon#*before return 0, iclass 39, count 0 2006.173.10:05:27.60#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.10:05:27.60#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.10:05:27.60#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.10:05:27.60#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.10:05:27.60$vck44/vb=3,4 2006.173.10:05:27.60#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.10:05:27.60#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.10:05:27.60#ibcon#ireg 11 cls_cnt 2 2006.173.10:05:27.60#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.10:05:27.66#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.10:05:27.66#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.10:05:27.66#ibcon#enter wrdev, iclass 3, count 2 2006.173.10:05:27.66#ibcon#first serial, iclass 3, count 2 2006.173.10:05:27.66#ibcon#enter sib2, iclass 3, count 2 2006.173.10:05:27.66#ibcon#flushed, iclass 3, count 2 2006.173.10:05:27.66#ibcon#about to write, iclass 3, count 2 2006.173.10:05:27.66#ibcon#wrote, iclass 3, count 2 2006.173.10:05:27.66#ibcon#about to read 3, iclass 3, count 2 2006.173.10:05:27.68#ibcon#read 3, iclass 3, count 2 2006.173.10:05:27.68#ibcon#about to read 4, iclass 3, count 2 2006.173.10:05:27.68#ibcon#read 4, iclass 3, count 2 2006.173.10:05:27.68#ibcon#about to read 5, iclass 3, count 2 2006.173.10:05:27.68#ibcon#read 5, iclass 3, count 2 2006.173.10:05:27.68#ibcon#about to read 6, iclass 3, count 2 2006.173.10:05:27.68#ibcon#read 6, iclass 3, count 2 2006.173.10:05:27.68#ibcon#end of sib2, iclass 3, count 2 2006.173.10:05:27.68#ibcon#*mode == 0, iclass 3, count 2 2006.173.10:05:27.68#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.10:05:27.68#ibcon#[27=AT03-04\r\n] 2006.173.10:05:27.68#ibcon#*before write, iclass 3, count 2 2006.173.10:05:27.68#ibcon#enter sib2, iclass 3, count 2 2006.173.10:05:27.68#ibcon#flushed, iclass 3, count 2 2006.173.10:05:27.68#ibcon#about to write, iclass 3, count 2 2006.173.10:05:27.68#ibcon#wrote, iclass 3, count 2 2006.173.10:05:27.68#ibcon#about to read 3, iclass 3, count 2 2006.173.10:05:27.71#ibcon#read 3, iclass 3, count 2 2006.173.10:05:27.71#ibcon#about to read 4, iclass 3, count 2 2006.173.10:05:27.71#ibcon#read 4, iclass 3, count 2 2006.173.10:05:27.71#ibcon#about to read 5, iclass 3, count 2 2006.173.10:05:27.71#ibcon#read 5, iclass 3, count 2 2006.173.10:05:27.71#ibcon#about to read 6, iclass 3, count 2 2006.173.10:05:27.71#ibcon#read 6, iclass 3, count 2 2006.173.10:05:27.71#ibcon#end of sib2, iclass 3, count 2 2006.173.10:05:27.71#ibcon#*after write, iclass 3, count 2 2006.173.10:05:27.71#ibcon#*before return 0, iclass 3, count 2 2006.173.10:05:27.71#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.10:05:27.71#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.10:05:27.71#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.10:05:27.71#ibcon#ireg 7 cls_cnt 0 2006.173.10:05:27.71#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.10:05:27.83#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.10:05:27.83#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.10:05:27.83#ibcon#enter wrdev, iclass 3, count 0 2006.173.10:05:27.83#ibcon#first serial, iclass 3, count 0 2006.173.10:05:27.83#ibcon#enter sib2, iclass 3, count 0 2006.173.10:05:27.83#ibcon#flushed, iclass 3, count 0 2006.173.10:05:27.83#ibcon#about to write, iclass 3, count 0 2006.173.10:05:27.83#ibcon#wrote, iclass 3, count 0 2006.173.10:05:27.83#ibcon#about to read 3, iclass 3, count 0 2006.173.10:05:27.85#ibcon#read 3, iclass 3, count 0 2006.173.10:05:27.85#ibcon#about to read 4, iclass 3, count 0 2006.173.10:05:27.85#ibcon#read 4, iclass 3, count 0 2006.173.10:05:27.85#ibcon#about to read 5, iclass 3, count 0 2006.173.10:05:27.85#ibcon#read 5, iclass 3, count 0 2006.173.10:05:27.85#ibcon#about to read 6, iclass 3, count 0 2006.173.10:05:27.85#ibcon#read 6, iclass 3, count 0 2006.173.10:05:27.85#ibcon#end of sib2, iclass 3, count 0 2006.173.10:05:27.85#ibcon#*mode == 0, iclass 3, count 0 2006.173.10:05:27.85#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.10:05:27.85#ibcon#[27=USB\r\n] 2006.173.10:05:27.85#ibcon#*before write, iclass 3, count 0 2006.173.10:05:27.85#ibcon#enter sib2, iclass 3, count 0 2006.173.10:05:27.85#ibcon#flushed, iclass 3, count 0 2006.173.10:05:27.85#ibcon#about to write, iclass 3, count 0 2006.173.10:05:27.85#ibcon#wrote, iclass 3, count 0 2006.173.10:05:27.85#ibcon#about to read 3, iclass 3, count 0 2006.173.10:05:27.88#ibcon#read 3, iclass 3, count 0 2006.173.10:05:27.88#ibcon#about to read 4, iclass 3, count 0 2006.173.10:05:27.88#ibcon#read 4, iclass 3, count 0 2006.173.10:05:27.88#ibcon#about to read 5, iclass 3, count 0 2006.173.10:05:27.88#ibcon#read 5, iclass 3, count 0 2006.173.10:05:27.88#ibcon#about to read 6, iclass 3, count 0 2006.173.10:05:27.88#ibcon#read 6, iclass 3, count 0 2006.173.10:05:27.88#ibcon#end of sib2, iclass 3, count 0 2006.173.10:05:27.88#ibcon#*after write, iclass 3, count 0 2006.173.10:05:27.88#ibcon#*before return 0, iclass 3, count 0 2006.173.10:05:27.88#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.10:05:27.88#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.10:05:27.88#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.10:05:27.88#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.10:05:27.88$vck44/vblo=4,679.99 2006.173.10:05:27.88#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.10:05:27.88#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.10:05:27.88#ibcon#ireg 17 cls_cnt 0 2006.173.10:05:27.88#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.10:05:27.88#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.10:05:27.88#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.10:05:27.88#ibcon#enter wrdev, iclass 5, count 0 2006.173.10:05:27.88#ibcon#first serial, iclass 5, count 0 2006.173.10:05:27.88#ibcon#enter sib2, iclass 5, count 0 2006.173.10:05:27.88#ibcon#flushed, iclass 5, count 0 2006.173.10:05:27.88#ibcon#about to write, iclass 5, count 0 2006.173.10:05:27.88#ibcon#wrote, iclass 5, count 0 2006.173.10:05:27.88#ibcon#about to read 3, iclass 5, count 0 2006.173.10:05:27.90#ibcon#read 3, iclass 5, count 0 2006.173.10:05:27.90#ibcon#about to read 4, iclass 5, count 0 2006.173.10:05:27.90#ibcon#read 4, iclass 5, count 0 2006.173.10:05:27.90#ibcon#about to read 5, iclass 5, count 0 2006.173.10:05:27.90#ibcon#read 5, iclass 5, count 0 2006.173.10:05:27.90#ibcon#about to read 6, iclass 5, count 0 2006.173.10:05:27.90#ibcon#read 6, iclass 5, count 0 2006.173.10:05:27.90#ibcon#end of sib2, iclass 5, count 0 2006.173.10:05:27.90#ibcon#*mode == 0, iclass 5, count 0 2006.173.10:05:27.90#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.10:05:27.90#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.10:05:27.90#ibcon#*before write, iclass 5, count 0 2006.173.10:05:27.90#ibcon#enter sib2, iclass 5, count 0 2006.173.10:05:27.90#ibcon#flushed, iclass 5, count 0 2006.173.10:05:27.90#ibcon#about to write, iclass 5, count 0 2006.173.10:05:27.90#ibcon#wrote, iclass 5, count 0 2006.173.10:05:27.90#ibcon#about to read 3, iclass 5, count 0 2006.173.10:05:27.94#ibcon#read 3, iclass 5, count 0 2006.173.10:05:27.94#ibcon#about to read 4, iclass 5, count 0 2006.173.10:05:27.94#ibcon#read 4, iclass 5, count 0 2006.173.10:05:27.94#ibcon#about to read 5, iclass 5, count 0 2006.173.10:05:27.94#ibcon#read 5, iclass 5, count 0 2006.173.10:05:27.94#ibcon#about to read 6, iclass 5, count 0 2006.173.10:05:27.94#ibcon#read 6, iclass 5, count 0 2006.173.10:05:27.94#ibcon#end of sib2, iclass 5, count 0 2006.173.10:05:27.94#ibcon#*after write, iclass 5, count 0 2006.173.10:05:27.94#ibcon#*before return 0, iclass 5, count 0 2006.173.10:05:27.94#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.10:05:27.94#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.10:05:27.94#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.10:05:27.94#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.10:05:27.94$vck44/vb=4,4 2006.173.10:05:27.94#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.173.10:05:27.94#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.173.10:05:27.94#ibcon#ireg 11 cls_cnt 2 2006.173.10:05:27.94#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.10:05:28.00#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.10:05:28.00#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.10:05:28.00#ibcon#enter wrdev, iclass 7, count 2 2006.173.10:05:28.00#ibcon#first serial, iclass 7, count 2 2006.173.10:05:28.00#ibcon#enter sib2, iclass 7, count 2 2006.173.10:05:28.00#ibcon#flushed, iclass 7, count 2 2006.173.10:05:28.00#ibcon#about to write, iclass 7, count 2 2006.173.10:05:28.00#ibcon#wrote, iclass 7, count 2 2006.173.10:05:28.00#ibcon#about to read 3, iclass 7, count 2 2006.173.10:05:28.02#ibcon#read 3, iclass 7, count 2 2006.173.10:05:28.02#ibcon#about to read 4, iclass 7, count 2 2006.173.10:05:28.02#ibcon#read 4, iclass 7, count 2 2006.173.10:05:28.02#ibcon#about to read 5, iclass 7, count 2 2006.173.10:05:28.02#ibcon#read 5, iclass 7, count 2 2006.173.10:05:28.02#ibcon#about to read 6, iclass 7, count 2 2006.173.10:05:28.02#ibcon#read 6, iclass 7, count 2 2006.173.10:05:28.02#ibcon#end of sib2, iclass 7, count 2 2006.173.10:05:28.02#ibcon#*mode == 0, iclass 7, count 2 2006.173.10:05:28.02#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.173.10:05:28.02#ibcon#[27=AT04-04\r\n] 2006.173.10:05:28.02#ibcon#*before write, iclass 7, count 2 2006.173.10:05:28.02#ibcon#enter sib2, iclass 7, count 2 2006.173.10:05:28.02#ibcon#flushed, iclass 7, count 2 2006.173.10:05:28.02#ibcon#about to write, iclass 7, count 2 2006.173.10:05:28.02#ibcon#wrote, iclass 7, count 2 2006.173.10:05:28.02#ibcon#about to read 3, iclass 7, count 2 2006.173.10:05:28.05#ibcon#read 3, iclass 7, count 2 2006.173.10:05:28.05#ibcon#about to read 4, iclass 7, count 2 2006.173.10:05:28.05#ibcon#read 4, iclass 7, count 2 2006.173.10:05:28.05#ibcon#about to read 5, iclass 7, count 2 2006.173.10:05:28.05#ibcon#read 5, iclass 7, count 2 2006.173.10:05:28.05#ibcon#about to read 6, iclass 7, count 2 2006.173.10:05:28.05#ibcon#read 6, iclass 7, count 2 2006.173.10:05:28.05#ibcon#end of sib2, iclass 7, count 2 2006.173.10:05:28.05#ibcon#*after write, iclass 7, count 2 2006.173.10:05:28.05#ibcon#*before return 0, iclass 7, count 2 2006.173.10:05:28.05#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.10:05:28.05#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.173.10:05:28.05#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.173.10:05:28.05#ibcon#ireg 7 cls_cnt 0 2006.173.10:05:28.05#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.10:05:28.17#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.10:05:28.17#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.10:05:28.17#ibcon#enter wrdev, iclass 7, count 0 2006.173.10:05:28.17#ibcon#first serial, iclass 7, count 0 2006.173.10:05:28.17#ibcon#enter sib2, iclass 7, count 0 2006.173.10:05:28.17#ibcon#flushed, iclass 7, count 0 2006.173.10:05:28.17#ibcon#about to write, iclass 7, count 0 2006.173.10:05:28.17#ibcon#wrote, iclass 7, count 0 2006.173.10:05:28.17#ibcon#about to read 3, iclass 7, count 0 2006.173.10:05:28.19#ibcon#read 3, iclass 7, count 0 2006.173.10:05:28.19#ibcon#about to read 4, iclass 7, count 0 2006.173.10:05:28.19#ibcon#read 4, iclass 7, count 0 2006.173.10:05:28.19#ibcon#about to read 5, iclass 7, count 0 2006.173.10:05:28.19#ibcon#read 5, iclass 7, count 0 2006.173.10:05:28.19#ibcon#about to read 6, iclass 7, count 0 2006.173.10:05:28.19#ibcon#read 6, iclass 7, count 0 2006.173.10:05:28.19#ibcon#end of sib2, iclass 7, count 0 2006.173.10:05:28.19#ibcon#*mode == 0, iclass 7, count 0 2006.173.10:05:28.19#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.10:05:28.19#ibcon#[27=USB\r\n] 2006.173.10:05:28.19#ibcon#*before write, iclass 7, count 0 2006.173.10:05:28.19#ibcon#enter sib2, iclass 7, count 0 2006.173.10:05:28.19#ibcon#flushed, iclass 7, count 0 2006.173.10:05:28.19#ibcon#about to write, iclass 7, count 0 2006.173.10:05:28.19#ibcon#wrote, iclass 7, count 0 2006.173.10:05:28.19#ibcon#about to read 3, iclass 7, count 0 2006.173.10:05:28.22#ibcon#read 3, iclass 7, count 0 2006.173.10:05:28.22#ibcon#about to read 4, iclass 7, count 0 2006.173.10:05:28.22#ibcon#read 4, iclass 7, count 0 2006.173.10:05:28.22#ibcon#about to read 5, iclass 7, count 0 2006.173.10:05:28.22#ibcon#read 5, iclass 7, count 0 2006.173.10:05:28.22#ibcon#about to read 6, iclass 7, count 0 2006.173.10:05:28.22#ibcon#read 6, iclass 7, count 0 2006.173.10:05:28.22#ibcon#end of sib2, iclass 7, count 0 2006.173.10:05:28.22#ibcon#*after write, iclass 7, count 0 2006.173.10:05:28.22#ibcon#*before return 0, iclass 7, count 0 2006.173.10:05:28.22#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.10:05:28.22#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.173.10:05:28.22#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.10:05:28.22#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.10:05:28.22$vck44/vblo=5,709.99 2006.173.10:05:28.22#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.10:05:28.22#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.10:05:28.22#ibcon#ireg 17 cls_cnt 0 2006.173.10:05:28.22#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.10:05:28.22#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.10:05:28.22#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.10:05:28.22#ibcon#enter wrdev, iclass 11, count 0 2006.173.10:05:28.22#ibcon#first serial, iclass 11, count 0 2006.173.10:05:28.22#ibcon#enter sib2, iclass 11, count 0 2006.173.10:05:28.22#ibcon#flushed, iclass 11, count 0 2006.173.10:05:28.22#ibcon#about to write, iclass 11, count 0 2006.173.10:05:28.22#ibcon#wrote, iclass 11, count 0 2006.173.10:05:28.22#ibcon#about to read 3, iclass 11, count 0 2006.173.10:05:28.24#ibcon#read 3, iclass 11, count 0 2006.173.10:05:28.24#ibcon#about to read 4, iclass 11, count 0 2006.173.10:05:28.24#ibcon#read 4, iclass 11, count 0 2006.173.10:05:28.24#ibcon#about to read 5, iclass 11, count 0 2006.173.10:05:28.24#ibcon#read 5, iclass 11, count 0 2006.173.10:05:28.24#ibcon#about to read 6, iclass 11, count 0 2006.173.10:05:28.24#ibcon#read 6, iclass 11, count 0 2006.173.10:05:28.24#ibcon#end of sib2, iclass 11, count 0 2006.173.10:05:28.24#ibcon#*mode == 0, iclass 11, count 0 2006.173.10:05:28.24#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.10:05:28.24#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.10:05:28.24#ibcon#*before write, iclass 11, count 0 2006.173.10:05:28.24#ibcon#enter sib2, iclass 11, count 0 2006.173.10:05:28.24#ibcon#flushed, iclass 11, count 0 2006.173.10:05:28.24#ibcon#about to write, iclass 11, count 0 2006.173.10:05:28.24#ibcon#wrote, iclass 11, count 0 2006.173.10:05:28.24#ibcon#about to read 3, iclass 11, count 0 2006.173.10:05:28.28#ibcon#read 3, iclass 11, count 0 2006.173.10:05:28.28#ibcon#about to read 4, iclass 11, count 0 2006.173.10:05:28.28#ibcon#read 4, iclass 11, count 0 2006.173.10:05:28.28#ibcon#about to read 5, iclass 11, count 0 2006.173.10:05:28.28#ibcon#read 5, iclass 11, count 0 2006.173.10:05:28.28#ibcon#about to read 6, iclass 11, count 0 2006.173.10:05:28.28#ibcon#read 6, iclass 11, count 0 2006.173.10:05:28.28#ibcon#end of sib2, iclass 11, count 0 2006.173.10:05:28.28#ibcon#*after write, iclass 11, count 0 2006.173.10:05:28.28#ibcon#*before return 0, iclass 11, count 0 2006.173.10:05:28.28#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.10:05:28.28#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.10:05:28.28#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.10:05:28.28#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.10:05:28.28$vck44/vb=5,4 2006.173.10:05:28.28#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.173.10:05:28.28#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.173.10:05:28.28#ibcon#ireg 11 cls_cnt 2 2006.173.10:05:28.28#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.10:05:28.34#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.10:05:28.34#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.10:05:28.34#ibcon#enter wrdev, iclass 13, count 2 2006.173.10:05:28.34#ibcon#first serial, iclass 13, count 2 2006.173.10:05:28.34#ibcon#enter sib2, iclass 13, count 2 2006.173.10:05:28.34#ibcon#flushed, iclass 13, count 2 2006.173.10:05:28.34#ibcon#about to write, iclass 13, count 2 2006.173.10:05:28.34#ibcon#wrote, iclass 13, count 2 2006.173.10:05:28.34#ibcon#about to read 3, iclass 13, count 2 2006.173.10:05:28.36#ibcon#read 3, iclass 13, count 2 2006.173.10:05:28.36#ibcon#about to read 4, iclass 13, count 2 2006.173.10:05:28.36#ibcon#read 4, iclass 13, count 2 2006.173.10:05:28.36#ibcon#about to read 5, iclass 13, count 2 2006.173.10:05:28.36#ibcon#read 5, iclass 13, count 2 2006.173.10:05:28.36#ibcon#about to read 6, iclass 13, count 2 2006.173.10:05:28.36#ibcon#read 6, iclass 13, count 2 2006.173.10:05:28.36#ibcon#end of sib2, iclass 13, count 2 2006.173.10:05:28.36#ibcon#*mode == 0, iclass 13, count 2 2006.173.10:05:28.36#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.173.10:05:28.36#ibcon#[27=AT05-04\r\n] 2006.173.10:05:28.36#ibcon#*before write, iclass 13, count 2 2006.173.10:05:28.36#ibcon#enter sib2, iclass 13, count 2 2006.173.10:05:28.36#ibcon#flushed, iclass 13, count 2 2006.173.10:05:28.36#ibcon#about to write, iclass 13, count 2 2006.173.10:05:28.36#ibcon#wrote, iclass 13, count 2 2006.173.10:05:28.36#ibcon#about to read 3, iclass 13, count 2 2006.173.10:05:28.39#ibcon#read 3, iclass 13, count 2 2006.173.10:05:28.39#ibcon#about to read 4, iclass 13, count 2 2006.173.10:05:28.39#ibcon#read 4, iclass 13, count 2 2006.173.10:05:28.39#ibcon#about to read 5, iclass 13, count 2 2006.173.10:05:28.39#ibcon#read 5, iclass 13, count 2 2006.173.10:05:28.39#ibcon#about to read 6, iclass 13, count 2 2006.173.10:05:28.39#ibcon#read 6, iclass 13, count 2 2006.173.10:05:28.39#ibcon#end of sib2, iclass 13, count 2 2006.173.10:05:28.39#ibcon#*after write, iclass 13, count 2 2006.173.10:05:28.39#ibcon#*before return 0, iclass 13, count 2 2006.173.10:05:28.39#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.10:05:28.39#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.173.10:05:28.39#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.173.10:05:28.39#ibcon#ireg 7 cls_cnt 0 2006.173.10:05:28.39#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.10:05:28.51#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.10:05:28.51#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.10:05:28.51#ibcon#enter wrdev, iclass 13, count 0 2006.173.10:05:28.51#ibcon#first serial, iclass 13, count 0 2006.173.10:05:28.51#ibcon#enter sib2, iclass 13, count 0 2006.173.10:05:28.51#ibcon#flushed, iclass 13, count 0 2006.173.10:05:28.51#ibcon#about to write, iclass 13, count 0 2006.173.10:05:28.51#ibcon#wrote, iclass 13, count 0 2006.173.10:05:28.51#ibcon#about to read 3, iclass 13, count 0 2006.173.10:05:28.53#ibcon#read 3, iclass 13, count 0 2006.173.10:05:28.53#ibcon#about to read 4, iclass 13, count 0 2006.173.10:05:28.53#ibcon#read 4, iclass 13, count 0 2006.173.10:05:28.53#ibcon#about to read 5, iclass 13, count 0 2006.173.10:05:28.53#ibcon#read 5, iclass 13, count 0 2006.173.10:05:28.53#ibcon#about to read 6, iclass 13, count 0 2006.173.10:05:28.53#ibcon#read 6, iclass 13, count 0 2006.173.10:05:28.53#ibcon#end of sib2, iclass 13, count 0 2006.173.10:05:28.53#ibcon#*mode == 0, iclass 13, count 0 2006.173.10:05:28.53#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.10:05:28.53#ibcon#[27=USB\r\n] 2006.173.10:05:28.53#ibcon#*before write, iclass 13, count 0 2006.173.10:05:28.53#ibcon#enter sib2, iclass 13, count 0 2006.173.10:05:28.53#ibcon#flushed, iclass 13, count 0 2006.173.10:05:28.53#ibcon#about to write, iclass 13, count 0 2006.173.10:05:28.53#ibcon#wrote, iclass 13, count 0 2006.173.10:05:28.53#ibcon#about to read 3, iclass 13, count 0 2006.173.10:05:28.56#ibcon#read 3, iclass 13, count 0 2006.173.10:05:28.56#ibcon#about to read 4, iclass 13, count 0 2006.173.10:05:28.56#ibcon#read 4, iclass 13, count 0 2006.173.10:05:28.56#ibcon#about to read 5, iclass 13, count 0 2006.173.10:05:28.56#ibcon#read 5, iclass 13, count 0 2006.173.10:05:28.56#ibcon#about to read 6, iclass 13, count 0 2006.173.10:05:28.56#ibcon#read 6, iclass 13, count 0 2006.173.10:05:28.56#ibcon#end of sib2, iclass 13, count 0 2006.173.10:05:28.56#ibcon#*after write, iclass 13, count 0 2006.173.10:05:28.56#ibcon#*before return 0, iclass 13, count 0 2006.173.10:05:28.56#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.10:05:28.56#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.173.10:05:28.56#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.10:05:28.56#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.10:05:28.56$vck44/vblo=6,719.99 2006.173.10:05:28.56#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.10:05:28.56#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.10:05:28.56#ibcon#ireg 17 cls_cnt 0 2006.173.10:05:28.56#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.10:05:28.56#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.10:05:28.56#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.10:05:28.56#ibcon#enter wrdev, iclass 15, count 0 2006.173.10:05:28.56#ibcon#first serial, iclass 15, count 0 2006.173.10:05:28.56#ibcon#enter sib2, iclass 15, count 0 2006.173.10:05:28.56#ibcon#flushed, iclass 15, count 0 2006.173.10:05:28.56#ibcon#about to write, iclass 15, count 0 2006.173.10:05:28.56#ibcon#wrote, iclass 15, count 0 2006.173.10:05:28.56#ibcon#about to read 3, iclass 15, count 0 2006.173.10:05:28.58#ibcon#read 3, iclass 15, count 0 2006.173.10:05:28.58#ibcon#about to read 4, iclass 15, count 0 2006.173.10:05:28.58#ibcon#read 4, iclass 15, count 0 2006.173.10:05:28.58#ibcon#about to read 5, iclass 15, count 0 2006.173.10:05:28.58#ibcon#read 5, iclass 15, count 0 2006.173.10:05:28.58#ibcon#about to read 6, iclass 15, count 0 2006.173.10:05:28.58#ibcon#read 6, iclass 15, count 0 2006.173.10:05:28.58#ibcon#end of sib2, iclass 15, count 0 2006.173.10:05:28.58#ibcon#*mode == 0, iclass 15, count 0 2006.173.10:05:28.58#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.10:05:28.58#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.10:05:28.58#ibcon#*before write, iclass 15, count 0 2006.173.10:05:28.58#ibcon#enter sib2, iclass 15, count 0 2006.173.10:05:28.58#ibcon#flushed, iclass 15, count 0 2006.173.10:05:28.58#ibcon#about to write, iclass 15, count 0 2006.173.10:05:28.58#ibcon#wrote, iclass 15, count 0 2006.173.10:05:28.58#ibcon#about to read 3, iclass 15, count 0 2006.173.10:05:28.62#ibcon#read 3, iclass 15, count 0 2006.173.10:05:28.62#ibcon#about to read 4, iclass 15, count 0 2006.173.10:05:28.62#ibcon#read 4, iclass 15, count 0 2006.173.10:05:28.62#ibcon#about to read 5, iclass 15, count 0 2006.173.10:05:28.62#ibcon#read 5, iclass 15, count 0 2006.173.10:05:28.62#ibcon#about to read 6, iclass 15, count 0 2006.173.10:05:28.62#ibcon#read 6, iclass 15, count 0 2006.173.10:05:28.62#ibcon#end of sib2, iclass 15, count 0 2006.173.10:05:28.62#ibcon#*after write, iclass 15, count 0 2006.173.10:05:28.62#ibcon#*before return 0, iclass 15, count 0 2006.173.10:05:28.62#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.10:05:28.62#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.10:05:28.62#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.10:05:28.62#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.10:05:28.62$vck44/vb=6,4 2006.173.10:05:28.62#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.10:05:28.62#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.10:05:28.62#ibcon#ireg 11 cls_cnt 2 2006.173.10:05:28.62#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.10:05:28.68#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.10:05:28.68#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.10:05:28.68#ibcon#enter wrdev, iclass 17, count 2 2006.173.10:05:28.68#ibcon#first serial, iclass 17, count 2 2006.173.10:05:28.68#ibcon#enter sib2, iclass 17, count 2 2006.173.10:05:28.68#ibcon#flushed, iclass 17, count 2 2006.173.10:05:28.68#ibcon#about to write, iclass 17, count 2 2006.173.10:05:28.68#ibcon#wrote, iclass 17, count 2 2006.173.10:05:28.68#ibcon#about to read 3, iclass 17, count 2 2006.173.10:05:28.70#ibcon#read 3, iclass 17, count 2 2006.173.10:05:28.70#ibcon#about to read 4, iclass 17, count 2 2006.173.10:05:28.70#ibcon#read 4, iclass 17, count 2 2006.173.10:05:28.70#ibcon#about to read 5, iclass 17, count 2 2006.173.10:05:28.70#ibcon#read 5, iclass 17, count 2 2006.173.10:05:28.70#ibcon#about to read 6, iclass 17, count 2 2006.173.10:05:28.70#ibcon#read 6, iclass 17, count 2 2006.173.10:05:28.70#ibcon#end of sib2, iclass 17, count 2 2006.173.10:05:28.70#ibcon#*mode == 0, iclass 17, count 2 2006.173.10:05:28.70#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.10:05:28.70#ibcon#[27=AT06-04\r\n] 2006.173.10:05:28.70#ibcon#*before write, iclass 17, count 2 2006.173.10:05:28.70#ibcon#enter sib2, iclass 17, count 2 2006.173.10:05:28.70#ibcon#flushed, iclass 17, count 2 2006.173.10:05:28.70#ibcon#about to write, iclass 17, count 2 2006.173.10:05:28.70#ibcon#wrote, iclass 17, count 2 2006.173.10:05:28.70#ibcon#about to read 3, iclass 17, count 2 2006.173.10:05:28.73#ibcon#read 3, iclass 17, count 2 2006.173.10:05:28.73#ibcon#about to read 4, iclass 17, count 2 2006.173.10:05:28.73#ibcon#read 4, iclass 17, count 2 2006.173.10:05:28.73#ibcon#about to read 5, iclass 17, count 2 2006.173.10:05:28.73#ibcon#read 5, iclass 17, count 2 2006.173.10:05:28.73#ibcon#about to read 6, iclass 17, count 2 2006.173.10:05:28.73#ibcon#read 6, iclass 17, count 2 2006.173.10:05:28.73#ibcon#end of sib2, iclass 17, count 2 2006.173.10:05:28.73#ibcon#*after write, iclass 17, count 2 2006.173.10:05:28.73#ibcon#*before return 0, iclass 17, count 2 2006.173.10:05:28.73#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.10:05:28.73#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.10:05:28.73#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.10:05:28.73#ibcon#ireg 7 cls_cnt 0 2006.173.10:05:28.73#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.10:05:28.85#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.10:05:28.85#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.10:05:28.85#ibcon#enter wrdev, iclass 17, count 0 2006.173.10:05:28.85#ibcon#first serial, iclass 17, count 0 2006.173.10:05:28.85#ibcon#enter sib2, iclass 17, count 0 2006.173.10:05:28.85#ibcon#flushed, iclass 17, count 0 2006.173.10:05:28.85#ibcon#about to write, iclass 17, count 0 2006.173.10:05:28.85#ibcon#wrote, iclass 17, count 0 2006.173.10:05:28.85#ibcon#about to read 3, iclass 17, count 0 2006.173.10:05:28.87#ibcon#read 3, iclass 17, count 0 2006.173.10:05:28.87#ibcon#about to read 4, iclass 17, count 0 2006.173.10:05:28.87#ibcon#read 4, iclass 17, count 0 2006.173.10:05:28.87#ibcon#about to read 5, iclass 17, count 0 2006.173.10:05:28.87#ibcon#read 5, iclass 17, count 0 2006.173.10:05:28.87#ibcon#about to read 6, iclass 17, count 0 2006.173.10:05:28.87#ibcon#read 6, iclass 17, count 0 2006.173.10:05:28.87#ibcon#end of sib2, iclass 17, count 0 2006.173.10:05:28.87#ibcon#*mode == 0, iclass 17, count 0 2006.173.10:05:28.87#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.10:05:28.87#ibcon#[27=USB\r\n] 2006.173.10:05:28.87#ibcon#*before write, iclass 17, count 0 2006.173.10:05:28.87#ibcon#enter sib2, iclass 17, count 0 2006.173.10:05:28.87#ibcon#flushed, iclass 17, count 0 2006.173.10:05:28.87#ibcon#about to write, iclass 17, count 0 2006.173.10:05:28.87#ibcon#wrote, iclass 17, count 0 2006.173.10:05:28.87#ibcon#about to read 3, iclass 17, count 0 2006.173.10:05:28.90#ibcon#read 3, iclass 17, count 0 2006.173.10:05:28.90#ibcon#about to read 4, iclass 17, count 0 2006.173.10:05:28.90#ibcon#read 4, iclass 17, count 0 2006.173.10:05:28.90#ibcon#about to read 5, iclass 17, count 0 2006.173.10:05:28.90#ibcon#read 5, iclass 17, count 0 2006.173.10:05:28.90#ibcon#about to read 6, iclass 17, count 0 2006.173.10:05:28.90#ibcon#read 6, iclass 17, count 0 2006.173.10:05:28.90#ibcon#end of sib2, iclass 17, count 0 2006.173.10:05:28.90#ibcon#*after write, iclass 17, count 0 2006.173.10:05:28.90#ibcon#*before return 0, iclass 17, count 0 2006.173.10:05:28.90#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.10:05:28.90#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.10:05:28.90#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.10:05:28.90#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.10:05:28.90$vck44/vblo=7,734.99 2006.173.10:05:28.90#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.10:05:28.90#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.10:05:28.90#ibcon#ireg 17 cls_cnt 0 2006.173.10:05:28.90#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.10:05:28.90#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.10:05:28.90#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.10:05:28.90#ibcon#enter wrdev, iclass 19, count 0 2006.173.10:05:28.90#ibcon#first serial, iclass 19, count 0 2006.173.10:05:28.90#ibcon#enter sib2, iclass 19, count 0 2006.173.10:05:28.90#ibcon#flushed, iclass 19, count 0 2006.173.10:05:28.90#ibcon#about to write, iclass 19, count 0 2006.173.10:05:28.90#ibcon#wrote, iclass 19, count 0 2006.173.10:05:28.90#ibcon#about to read 3, iclass 19, count 0 2006.173.10:05:28.92#ibcon#read 3, iclass 19, count 0 2006.173.10:05:28.92#ibcon#about to read 4, iclass 19, count 0 2006.173.10:05:28.92#ibcon#read 4, iclass 19, count 0 2006.173.10:05:28.92#ibcon#about to read 5, iclass 19, count 0 2006.173.10:05:28.92#ibcon#read 5, iclass 19, count 0 2006.173.10:05:28.92#ibcon#about to read 6, iclass 19, count 0 2006.173.10:05:28.92#ibcon#read 6, iclass 19, count 0 2006.173.10:05:28.92#ibcon#end of sib2, iclass 19, count 0 2006.173.10:05:28.92#ibcon#*mode == 0, iclass 19, count 0 2006.173.10:05:28.92#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.10:05:28.92#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.10:05:28.92#ibcon#*before write, iclass 19, count 0 2006.173.10:05:28.92#ibcon#enter sib2, iclass 19, count 0 2006.173.10:05:28.92#ibcon#flushed, iclass 19, count 0 2006.173.10:05:28.92#ibcon#about to write, iclass 19, count 0 2006.173.10:05:28.92#ibcon#wrote, iclass 19, count 0 2006.173.10:05:28.92#ibcon#about to read 3, iclass 19, count 0 2006.173.10:05:28.96#ibcon#read 3, iclass 19, count 0 2006.173.10:05:28.96#ibcon#about to read 4, iclass 19, count 0 2006.173.10:05:28.96#ibcon#read 4, iclass 19, count 0 2006.173.10:05:28.96#ibcon#about to read 5, iclass 19, count 0 2006.173.10:05:28.96#ibcon#read 5, iclass 19, count 0 2006.173.10:05:28.96#ibcon#about to read 6, iclass 19, count 0 2006.173.10:05:28.96#ibcon#read 6, iclass 19, count 0 2006.173.10:05:28.96#ibcon#end of sib2, iclass 19, count 0 2006.173.10:05:28.96#ibcon#*after write, iclass 19, count 0 2006.173.10:05:28.96#ibcon#*before return 0, iclass 19, count 0 2006.173.10:05:28.96#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.10:05:28.96#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.10:05:28.96#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.10:05:28.96#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.10:05:28.96$vck44/vb=7,4 2006.173.10:05:28.96#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.10:05:28.96#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.10:05:28.96#ibcon#ireg 11 cls_cnt 2 2006.173.10:05:28.96#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.10:05:29.02#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.10:05:29.02#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.10:05:29.02#ibcon#enter wrdev, iclass 21, count 2 2006.173.10:05:29.02#ibcon#first serial, iclass 21, count 2 2006.173.10:05:29.02#ibcon#enter sib2, iclass 21, count 2 2006.173.10:05:29.02#ibcon#flushed, iclass 21, count 2 2006.173.10:05:29.02#ibcon#about to write, iclass 21, count 2 2006.173.10:05:29.02#ibcon#wrote, iclass 21, count 2 2006.173.10:05:29.02#ibcon#about to read 3, iclass 21, count 2 2006.173.10:05:29.04#ibcon#read 3, iclass 21, count 2 2006.173.10:05:29.04#ibcon#about to read 4, iclass 21, count 2 2006.173.10:05:29.04#ibcon#read 4, iclass 21, count 2 2006.173.10:05:29.04#ibcon#about to read 5, iclass 21, count 2 2006.173.10:05:29.04#ibcon#read 5, iclass 21, count 2 2006.173.10:05:29.04#ibcon#about to read 6, iclass 21, count 2 2006.173.10:05:29.04#ibcon#read 6, iclass 21, count 2 2006.173.10:05:29.04#ibcon#end of sib2, iclass 21, count 2 2006.173.10:05:29.04#ibcon#*mode == 0, iclass 21, count 2 2006.173.10:05:29.04#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.10:05:29.04#ibcon#[27=AT07-04\r\n] 2006.173.10:05:29.04#ibcon#*before write, iclass 21, count 2 2006.173.10:05:29.04#ibcon#enter sib2, iclass 21, count 2 2006.173.10:05:29.04#ibcon#flushed, iclass 21, count 2 2006.173.10:05:29.04#ibcon#about to write, iclass 21, count 2 2006.173.10:05:29.04#ibcon#wrote, iclass 21, count 2 2006.173.10:05:29.04#ibcon#about to read 3, iclass 21, count 2 2006.173.10:05:29.07#ibcon#read 3, iclass 21, count 2 2006.173.10:05:29.07#ibcon#about to read 4, iclass 21, count 2 2006.173.10:05:29.07#ibcon#read 4, iclass 21, count 2 2006.173.10:05:29.07#ibcon#about to read 5, iclass 21, count 2 2006.173.10:05:29.07#ibcon#read 5, iclass 21, count 2 2006.173.10:05:29.07#ibcon#about to read 6, iclass 21, count 2 2006.173.10:05:29.07#ibcon#read 6, iclass 21, count 2 2006.173.10:05:29.07#ibcon#end of sib2, iclass 21, count 2 2006.173.10:05:29.07#ibcon#*after write, iclass 21, count 2 2006.173.10:05:29.07#ibcon#*before return 0, iclass 21, count 2 2006.173.10:05:29.07#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.10:05:29.07#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.10:05:29.07#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.10:05:29.07#ibcon#ireg 7 cls_cnt 0 2006.173.10:05:29.07#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.10:05:29.19#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.10:05:29.19#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.10:05:29.19#ibcon#enter wrdev, iclass 21, count 0 2006.173.10:05:29.19#ibcon#first serial, iclass 21, count 0 2006.173.10:05:29.19#ibcon#enter sib2, iclass 21, count 0 2006.173.10:05:29.19#ibcon#flushed, iclass 21, count 0 2006.173.10:05:29.19#ibcon#about to write, iclass 21, count 0 2006.173.10:05:29.19#ibcon#wrote, iclass 21, count 0 2006.173.10:05:29.19#ibcon#about to read 3, iclass 21, count 0 2006.173.10:05:29.21#ibcon#read 3, iclass 21, count 0 2006.173.10:05:29.21#ibcon#about to read 4, iclass 21, count 0 2006.173.10:05:29.21#ibcon#read 4, iclass 21, count 0 2006.173.10:05:29.21#ibcon#about to read 5, iclass 21, count 0 2006.173.10:05:29.21#ibcon#read 5, iclass 21, count 0 2006.173.10:05:29.21#ibcon#about to read 6, iclass 21, count 0 2006.173.10:05:29.21#ibcon#read 6, iclass 21, count 0 2006.173.10:05:29.21#ibcon#end of sib2, iclass 21, count 0 2006.173.10:05:29.21#ibcon#*mode == 0, iclass 21, count 0 2006.173.10:05:29.21#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.10:05:29.21#ibcon#[27=USB\r\n] 2006.173.10:05:29.21#ibcon#*before write, iclass 21, count 0 2006.173.10:05:29.21#ibcon#enter sib2, iclass 21, count 0 2006.173.10:05:29.21#ibcon#flushed, iclass 21, count 0 2006.173.10:05:29.21#ibcon#about to write, iclass 21, count 0 2006.173.10:05:29.21#ibcon#wrote, iclass 21, count 0 2006.173.10:05:29.21#ibcon#about to read 3, iclass 21, count 0 2006.173.10:05:29.24#ibcon#read 3, iclass 21, count 0 2006.173.10:05:29.24#ibcon#about to read 4, iclass 21, count 0 2006.173.10:05:29.24#ibcon#read 4, iclass 21, count 0 2006.173.10:05:29.24#ibcon#about to read 5, iclass 21, count 0 2006.173.10:05:29.24#ibcon#read 5, iclass 21, count 0 2006.173.10:05:29.24#ibcon#about to read 6, iclass 21, count 0 2006.173.10:05:29.24#ibcon#read 6, iclass 21, count 0 2006.173.10:05:29.24#ibcon#end of sib2, iclass 21, count 0 2006.173.10:05:29.24#ibcon#*after write, iclass 21, count 0 2006.173.10:05:29.24#ibcon#*before return 0, iclass 21, count 0 2006.173.10:05:29.24#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.10:05:29.24#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.10:05:29.24#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.10:05:29.24#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.10:05:29.24$vck44/vblo=8,744.99 2006.173.10:05:29.24#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.10:05:29.24#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.10:05:29.24#ibcon#ireg 17 cls_cnt 0 2006.173.10:05:29.24#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.10:05:29.24#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.10:05:29.24#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.10:05:29.24#ibcon#enter wrdev, iclass 23, count 0 2006.173.10:05:29.24#ibcon#first serial, iclass 23, count 0 2006.173.10:05:29.24#ibcon#enter sib2, iclass 23, count 0 2006.173.10:05:29.24#ibcon#flushed, iclass 23, count 0 2006.173.10:05:29.24#ibcon#about to write, iclass 23, count 0 2006.173.10:05:29.24#ibcon#wrote, iclass 23, count 0 2006.173.10:05:29.24#ibcon#about to read 3, iclass 23, count 0 2006.173.10:05:29.26#ibcon#read 3, iclass 23, count 0 2006.173.10:05:29.26#ibcon#about to read 4, iclass 23, count 0 2006.173.10:05:29.26#ibcon#read 4, iclass 23, count 0 2006.173.10:05:29.26#ibcon#about to read 5, iclass 23, count 0 2006.173.10:05:29.26#ibcon#read 5, iclass 23, count 0 2006.173.10:05:29.26#ibcon#about to read 6, iclass 23, count 0 2006.173.10:05:29.26#ibcon#read 6, iclass 23, count 0 2006.173.10:05:29.26#ibcon#end of sib2, iclass 23, count 0 2006.173.10:05:29.26#ibcon#*mode == 0, iclass 23, count 0 2006.173.10:05:29.26#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.10:05:29.26#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.10:05:29.26#ibcon#*before write, iclass 23, count 0 2006.173.10:05:29.26#ibcon#enter sib2, iclass 23, count 0 2006.173.10:05:29.26#ibcon#flushed, iclass 23, count 0 2006.173.10:05:29.26#ibcon#about to write, iclass 23, count 0 2006.173.10:05:29.26#ibcon#wrote, iclass 23, count 0 2006.173.10:05:29.26#ibcon#about to read 3, iclass 23, count 0 2006.173.10:05:29.30#ibcon#read 3, iclass 23, count 0 2006.173.10:05:29.30#ibcon#about to read 4, iclass 23, count 0 2006.173.10:05:29.30#ibcon#read 4, iclass 23, count 0 2006.173.10:05:29.30#ibcon#about to read 5, iclass 23, count 0 2006.173.10:05:29.30#ibcon#read 5, iclass 23, count 0 2006.173.10:05:29.30#ibcon#about to read 6, iclass 23, count 0 2006.173.10:05:29.30#ibcon#read 6, iclass 23, count 0 2006.173.10:05:29.30#ibcon#end of sib2, iclass 23, count 0 2006.173.10:05:29.30#ibcon#*after write, iclass 23, count 0 2006.173.10:05:29.30#ibcon#*before return 0, iclass 23, count 0 2006.173.10:05:29.30#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.10:05:29.30#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.10:05:29.30#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.10:05:29.30#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.10:05:29.30$vck44/vb=8,4 2006.173.10:05:29.30#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.10:05:29.30#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.10:05:29.30#ibcon#ireg 11 cls_cnt 2 2006.173.10:05:29.30#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.10:05:29.36#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.10:05:29.36#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.10:05:29.36#ibcon#enter wrdev, iclass 25, count 2 2006.173.10:05:29.36#ibcon#first serial, iclass 25, count 2 2006.173.10:05:29.36#ibcon#enter sib2, iclass 25, count 2 2006.173.10:05:29.36#ibcon#flushed, iclass 25, count 2 2006.173.10:05:29.36#ibcon#about to write, iclass 25, count 2 2006.173.10:05:29.36#ibcon#wrote, iclass 25, count 2 2006.173.10:05:29.36#ibcon#about to read 3, iclass 25, count 2 2006.173.10:05:29.38#ibcon#read 3, iclass 25, count 2 2006.173.10:05:29.38#ibcon#about to read 4, iclass 25, count 2 2006.173.10:05:29.38#ibcon#read 4, iclass 25, count 2 2006.173.10:05:29.38#ibcon#about to read 5, iclass 25, count 2 2006.173.10:05:29.38#ibcon#read 5, iclass 25, count 2 2006.173.10:05:29.38#ibcon#about to read 6, iclass 25, count 2 2006.173.10:05:29.38#ibcon#read 6, iclass 25, count 2 2006.173.10:05:29.38#ibcon#end of sib2, iclass 25, count 2 2006.173.10:05:29.38#ibcon#*mode == 0, iclass 25, count 2 2006.173.10:05:29.38#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.10:05:29.38#ibcon#[27=AT08-04\r\n] 2006.173.10:05:29.38#ibcon#*before write, iclass 25, count 2 2006.173.10:05:29.38#ibcon#enter sib2, iclass 25, count 2 2006.173.10:05:29.38#ibcon#flushed, iclass 25, count 2 2006.173.10:05:29.38#ibcon#about to write, iclass 25, count 2 2006.173.10:05:29.38#ibcon#wrote, iclass 25, count 2 2006.173.10:05:29.38#ibcon#about to read 3, iclass 25, count 2 2006.173.10:05:29.41#ibcon#read 3, iclass 25, count 2 2006.173.10:05:29.41#ibcon#about to read 4, iclass 25, count 2 2006.173.10:05:29.41#ibcon#read 4, iclass 25, count 2 2006.173.10:05:29.41#ibcon#about to read 5, iclass 25, count 2 2006.173.10:05:29.41#ibcon#read 5, iclass 25, count 2 2006.173.10:05:29.41#ibcon#about to read 6, iclass 25, count 2 2006.173.10:05:29.41#ibcon#read 6, iclass 25, count 2 2006.173.10:05:29.41#ibcon#end of sib2, iclass 25, count 2 2006.173.10:05:29.41#ibcon#*after write, iclass 25, count 2 2006.173.10:05:29.41#ibcon#*before return 0, iclass 25, count 2 2006.173.10:05:29.41#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.10:05:29.41#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.10:05:29.41#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.10:05:29.41#ibcon#ireg 7 cls_cnt 0 2006.173.10:05:29.41#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.10:05:29.53#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.10:05:29.53#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.10:05:29.53#ibcon#enter wrdev, iclass 25, count 0 2006.173.10:05:29.53#ibcon#first serial, iclass 25, count 0 2006.173.10:05:29.53#ibcon#enter sib2, iclass 25, count 0 2006.173.10:05:29.53#ibcon#flushed, iclass 25, count 0 2006.173.10:05:29.53#ibcon#about to write, iclass 25, count 0 2006.173.10:05:29.53#ibcon#wrote, iclass 25, count 0 2006.173.10:05:29.53#ibcon#about to read 3, iclass 25, count 0 2006.173.10:05:29.55#ibcon#read 3, iclass 25, count 0 2006.173.10:05:29.55#ibcon#about to read 4, iclass 25, count 0 2006.173.10:05:29.55#ibcon#read 4, iclass 25, count 0 2006.173.10:05:29.55#ibcon#about to read 5, iclass 25, count 0 2006.173.10:05:29.55#ibcon#read 5, iclass 25, count 0 2006.173.10:05:29.55#ibcon#about to read 6, iclass 25, count 0 2006.173.10:05:29.55#ibcon#read 6, iclass 25, count 0 2006.173.10:05:29.55#ibcon#end of sib2, iclass 25, count 0 2006.173.10:05:29.55#ibcon#*mode == 0, iclass 25, count 0 2006.173.10:05:29.55#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.10:05:29.55#ibcon#[27=USB\r\n] 2006.173.10:05:29.55#ibcon#*before write, iclass 25, count 0 2006.173.10:05:29.55#ibcon#enter sib2, iclass 25, count 0 2006.173.10:05:29.55#ibcon#flushed, iclass 25, count 0 2006.173.10:05:29.55#ibcon#about to write, iclass 25, count 0 2006.173.10:05:29.55#ibcon#wrote, iclass 25, count 0 2006.173.10:05:29.55#ibcon#about to read 3, iclass 25, count 0 2006.173.10:05:29.58#ibcon#read 3, iclass 25, count 0 2006.173.10:05:29.58#ibcon#about to read 4, iclass 25, count 0 2006.173.10:05:29.58#ibcon#read 4, iclass 25, count 0 2006.173.10:05:29.58#ibcon#about to read 5, iclass 25, count 0 2006.173.10:05:29.58#ibcon#read 5, iclass 25, count 0 2006.173.10:05:29.58#ibcon#about to read 6, iclass 25, count 0 2006.173.10:05:29.58#ibcon#read 6, iclass 25, count 0 2006.173.10:05:29.58#ibcon#end of sib2, iclass 25, count 0 2006.173.10:05:29.58#ibcon#*after write, iclass 25, count 0 2006.173.10:05:29.58#ibcon#*before return 0, iclass 25, count 0 2006.173.10:05:29.58#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.10:05:29.58#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.10:05:29.58#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.10:05:29.58#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.10:05:29.58$vck44/vabw=wide 2006.173.10:05:29.58#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.10:05:29.58#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.10:05:29.58#ibcon#ireg 8 cls_cnt 0 2006.173.10:05:29.58#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.10:05:29.58#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.10:05:29.58#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.10:05:29.58#ibcon#enter wrdev, iclass 27, count 0 2006.173.10:05:29.58#ibcon#first serial, iclass 27, count 0 2006.173.10:05:29.58#ibcon#enter sib2, iclass 27, count 0 2006.173.10:05:29.58#ibcon#flushed, iclass 27, count 0 2006.173.10:05:29.58#ibcon#about to write, iclass 27, count 0 2006.173.10:05:29.58#ibcon#wrote, iclass 27, count 0 2006.173.10:05:29.58#ibcon#about to read 3, iclass 27, count 0 2006.173.10:05:29.60#ibcon#read 3, iclass 27, count 0 2006.173.10:05:29.60#ibcon#about to read 4, iclass 27, count 0 2006.173.10:05:29.60#ibcon#read 4, iclass 27, count 0 2006.173.10:05:29.60#ibcon#about to read 5, iclass 27, count 0 2006.173.10:05:29.60#ibcon#read 5, iclass 27, count 0 2006.173.10:05:29.60#ibcon#about to read 6, iclass 27, count 0 2006.173.10:05:29.60#ibcon#read 6, iclass 27, count 0 2006.173.10:05:29.60#ibcon#end of sib2, iclass 27, count 0 2006.173.10:05:29.60#ibcon#*mode == 0, iclass 27, count 0 2006.173.10:05:29.60#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.10:05:29.60#ibcon#[25=BW32\r\n] 2006.173.10:05:29.60#ibcon#*before write, iclass 27, count 0 2006.173.10:05:29.60#ibcon#enter sib2, iclass 27, count 0 2006.173.10:05:29.60#ibcon#flushed, iclass 27, count 0 2006.173.10:05:29.60#ibcon#about to write, iclass 27, count 0 2006.173.10:05:29.60#ibcon#wrote, iclass 27, count 0 2006.173.10:05:29.60#ibcon#about to read 3, iclass 27, count 0 2006.173.10:05:29.63#ibcon#read 3, iclass 27, count 0 2006.173.10:05:29.63#ibcon#about to read 4, iclass 27, count 0 2006.173.10:05:29.63#ibcon#read 4, iclass 27, count 0 2006.173.10:05:29.63#ibcon#about to read 5, iclass 27, count 0 2006.173.10:05:29.63#ibcon#read 5, iclass 27, count 0 2006.173.10:05:29.63#ibcon#about to read 6, iclass 27, count 0 2006.173.10:05:29.63#ibcon#read 6, iclass 27, count 0 2006.173.10:05:29.63#ibcon#end of sib2, iclass 27, count 0 2006.173.10:05:29.63#ibcon#*after write, iclass 27, count 0 2006.173.10:05:29.63#ibcon#*before return 0, iclass 27, count 0 2006.173.10:05:29.63#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.10:05:29.63#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.10:05:29.63#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.10:05:29.63#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.10:05:29.63$vck44/vbbw=wide 2006.173.10:05:29.63#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.10:05:29.63#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.10:05:29.63#ibcon#ireg 8 cls_cnt 0 2006.173.10:05:29.63#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.10:05:29.70#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.10:05:29.70#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.10:05:29.70#ibcon#enter wrdev, iclass 29, count 0 2006.173.10:05:29.70#ibcon#first serial, iclass 29, count 0 2006.173.10:05:29.70#ibcon#enter sib2, iclass 29, count 0 2006.173.10:05:29.70#ibcon#flushed, iclass 29, count 0 2006.173.10:05:29.70#ibcon#about to write, iclass 29, count 0 2006.173.10:05:29.70#ibcon#wrote, iclass 29, count 0 2006.173.10:05:29.70#ibcon#about to read 3, iclass 29, count 0 2006.173.10:05:29.72#ibcon#read 3, iclass 29, count 0 2006.173.10:05:29.72#ibcon#about to read 4, iclass 29, count 0 2006.173.10:05:29.72#ibcon#read 4, iclass 29, count 0 2006.173.10:05:29.72#ibcon#about to read 5, iclass 29, count 0 2006.173.10:05:29.72#ibcon#read 5, iclass 29, count 0 2006.173.10:05:29.72#ibcon#about to read 6, iclass 29, count 0 2006.173.10:05:29.72#ibcon#read 6, iclass 29, count 0 2006.173.10:05:29.72#ibcon#end of sib2, iclass 29, count 0 2006.173.10:05:29.72#ibcon#*mode == 0, iclass 29, count 0 2006.173.10:05:29.72#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.10:05:29.72#ibcon#[27=BW32\r\n] 2006.173.10:05:29.72#ibcon#*before write, iclass 29, count 0 2006.173.10:05:29.72#ibcon#enter sib2, iclass 29, count 0 2006.173.10:05:29.72#ibcon#flushed, iclass 29, count 0 2006.173.10:05:29.72#ibcon#about to write, iclass 29, count 0 2006.173.10:05:29.72#ibcon#wrote, iclass 29, count 0 2006.173.10:05:29.72#ibcon#about to read 3, iclass 29, count 0 2006.173.10:05:29.75#ibcon#read 3, iclass 29, count 0 2006.173.10:05:29.75#ibcon#about to read 4, iclass 29, count 0 2006.173.10:05:29.75#ibcon#read 4, iclass 29, count 0 2006.173.10:05:29.75#ibcon#about to read 5, iclass 29, count 0 2006.173.10:05:29.75#ibcon#read 5, iclass 29, count 0 2006.173.10:05:29.75#ibcon#about to read 6, iclass 29, count 0 2006.173.10:05:29.75#ibcon#read 6, iclass 29, count 0 2006.173.10:05:29.75#ibcon#end of sib2, iclass 29, count 0 2006.173.10:05:29.75#ibcon#*after write, iclass 29, count 0 2006.173.10:05:29.75#ibcon#*before return 0, iclass 29, count 0 2006.173.10:05:29.75#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.10:05:29.75#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.10:05:29.75#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.10:05:29.75#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.10:05:29.75$setupk4/ifdk4 2006.173.10:05:29.75$ifdk4/lo= 2006.173.10:05:29.75$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.10:05:29.75$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.10:05:29.75$ifdk4/patch= 2006.173.10:05:29.75$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.10:05:29.75$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.10:05:29.75$setupk4/!*+20s 2006.173.10:05:36.51#abcon#<5=/06 1.2 1.7 22.83 931004.1\r\n> 2006.173.10:05:36.53#abcon#{5=INTERFACE CLEAR} 2006.173.10:05:36.59#abcon#[5=S1D000X0/0*\r\n] 2006.173.10:05:44.25$setupk4/"tpicd 2006.173.10:05:44.25$setupk4/echo=off 2006.173.10:05:44.25$setupk4/xlog=off 2006.173.10:05:44.25:!2006.173.10:07:04 2006.173.10:05:59.14#trakl#Source acquired 2006.173.10:06:01.14#flagr#flagr/antenna,acquired 2006.173.10:07:04.00:preob 2006.173.10:07:05.13/onsource/TRACKING 2006.173.10:07:05.13:!2006.173.10:07:14 2006.173.10:07:14.00:"tape 2006.173.10:07:14.00:"st=record 2006.173.10:07:14.00:data_valid=on 2006.173.10:07:14.00:midob 2006.173.10:07:14.13/onsource/TRACKING 2006.173.10:07:14.13/wx/22.82,1004.1,93 2006.173.10:07:14.21/cable/+6.4996E-03 2006.173.10:07:15.30/va/01,07,usb,yes,38,40 2006.173.10:07:15.30/va/02,06,usb,yes,37,38 2006.173.10:07:15.30/va/03,05,usb,yes,47,49 2006.173.10:07:15.30/va/04,06,usb,yes,38,40 2006.173.10:07:15.30/va/05,04,usb,yes,30,30 2006.173.10:07:15.30/va/06,03,usb,yes,42,42 2006.173.10:07:15.30/va/07,04,usb,yes,34,35 2006.173.10:07:15.30/va/08,04,usb,yes,29,35 2006.173.10:07:15.53/valo/01,524.99,yes,locked 2006.173.10:07:15.53/valo/02,534.99,yes,locked 2006.173.10:07:15.53/valo/03,564.99,yes,locked 2006.173.10:07:15.53/valo/04,624.99,yes,locked 2006.173.10:07:15.53/valo/05,734.99,yes,locked 2006.173.10:07:15.53/valo/06,814.99,yes,locked 2006.173.10:07:15.53/valo/07,864.99,yes,locked 2006.173.10:07:15.53/valo/08,884.99,yes,locked 2006.173.10:07:16.62/vb/01,04,usb,yes,36,33 2006.173.10:07:16.62/vb/02,04,usb,yes,38,38 2006.173.10:07:16.62/vb/03,04,usb,yes,35,38 2006.173.10:07:16.62/vb/04,04,usb,yes,40,39 2006.173.10:07:16.62/vb/05,04,usb,yes,31,34 2006.173.10:07:16.62/vb/06,04,usb,yes,36,32 2006.173.10:07:16.62/vb/07,04,usb,yes,36,36 2006.173.10:07:16.62/vb/08,04,usb,yes,33,37 2006.173.10:07:16.86/vblo/01,629.99,yes,locked 2006.173.10:07:16.86/vblo/02,634.99,yes,locked 2006.173.10:07:16.86/vblo/03,649.99,yes,locked 2006.173.10:07:16.86/vblo/04,679.99,yes,locked 2006.173.10:07:16.86/vblo/05,709.99,yes,locked 2006.173.10:07:16.86/vblo/06,719.99,yes,locked 2006.173.10:07:16.86/vblo/07,734.99,yes,locked 2006.173.10:07:16.86/vblo/08,744.99,yes,locked 2006.173.10:07:17.01/vabw/8 2006.173.10:07:17.16/vbbw/8 2006.173.10:07:17.25/xfe/off,on,15.0 2006.173.10:07:17.63/ifatt/23,28,28,28 2006.173.10:07:18.08/fmout-gps/S +4.01E-07 2006.173.10:07:18.12:!2006.173.10:08:44 2006.173.10:08:44.01:data_valid=off 2006.173.10:08:44.01:"et 2006.173.10:08:44.01:!+3s 2006.173.10:08:47.02:"tape 2006.173.10:08:47.02:postob 2006.173.10:08:47.09/cable/+6.5021E-03 2006.173.10:08:47.09/wx/22.81,1004.1,93 2006.173.10:08:47.15/fmout-gps/S +4.01E-07 2006.173.10:08:47.15:scan_name=173-1015,jd0606,110 2006.173.10:08:47.15:source=0552+398,055530.81,394849.2,2000.0,cw 2006.173.10:08:48.14#flagr#flagr/antenna,new-source 2006.173.10:08:48.14:checkk5 2006.173.10:08:48.56/chk_autoobs//k5ts1/ autoobs is running! 2006.173.10:08:48.96/chk_autoobs//k5ts2/ autoobs is running! 2006.173.10:08:49.36/chk_autoobs//k5ts3/ autoobs is running! 2006.173.10:08:49.76/chk_autoobs//k5ts4/ autoobs is running! 2006.173.10:08:50.14/chk_obsdata//k5ts1/T1731007??a.dat file size is correct (nominal:360MB, actual:356MB). 2006.173.10:08:50.56/chk_obsdata//k5ts2/T1731007??b.dat file size is correct (nominal:360MB, actual:356MB). 2006.173.10:08:50.95/chk_obsdata//k5ts3/T1731007??c.dat file size is correct (nominal:360MB, actual:356MB). 2006.173.10:08:51.34/chk_obsdata//k5ts4/T1731007??d.dat file size is correct (nominal:360MB, actual:356MB). 2006.173.10:08:52.06/k5log//k5ts1_log_newline 2006.173.10:08:52.76/k5log//k5ts2_log_newline 2006.173.10:08:53.48/k5log//k5ts3_log_newline 2006.173.10:08:54.19/k5log//k5ts4_log_newline 2006.173.10:08:54.22/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.10:08:54.22:setupk4=1 2006.173.10:08:54.22$setupk4/echo=on 2006.173.10:08:54.22$setupk4/pcalon 2006.173.10:08:54.22$pcalon/"no phase cal control is implemented here 2006.173.10:08:54.22$setupk4/"tpicd=stop 2006.173.10:08:54.22$setupk4/"rec=synch_on 2006.173.10:08:54.22$setupk4/"rec_mode=128 2006.173.10:08:54.22$setupk4/!* 2006.173.10:08:54.22$setupk4/recpk4 2006.173.10:08:54.22$recpk4/recpatch= 2006.173.10:08:54.22$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.10:08:54.22$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.10:08:54.22$setupk4/vck44 2006.173.10:08:54.22$vck44/valo=1,524.99 2006.173.10:08:54.22#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.10:08:54.22#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.10:08:54.22#ibcon#ireg 17 cls_cnt 0 2006.173.10:08:54.22#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.10:08:54.22#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.10:08:54.22#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.10:08:54.22#ibcon#enter wrdev, iclass 4, count 0 2006.173.10:08:54.22#ibcon#first serial, iclass 4, count 0 2006.173.10:08:54.22#ibcon#enter sib2, iclass 4, count 0 2006.173.10:08:54.22#ibcon#flushed, iclass 4, count 0 2006.173.10:08:54.22#ibcon#about to write, iclass 4, count 0 2006.173.10:08:54.22#ibcon#wrote, iclass 4, count 0 2006.173.10:08:54.22#ibcon#about to read 3, iclass 4, count 0 2006.173.10:08:54.24#ibcon#read 3, iclass 4, count 0 2006.173.10:08:54.24#ibcon#about to read 4, iclass 4, count 0 2006.173.10:08:54.24#ibcon#read 4, iclass 4, count 0 2006.173.10:08:54.24#ibcon#about to read 5, iclass 4, count 0 2006.173.10:08:54.24#ibcon#read 5, iclass 4, count 0 2006.173.10:08:54.24#ibcon#about to read 6, iclass 4, count 0 2006.173.10:08:54.24#ibcon#read 6, iclass 4, count 0 2006.173.10:08:54.24#ibcon#end of sib2, iclass 4, count 0 2006.173.10:08:54.24#ibcon#*mode == 0, iclass 4, count 0 2006.173.10:08:54.24#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.10:08:54.24#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.10:08:54.24#ibcon#*before write, iclass 4, count 0 2006.173.10:08:54.24#ibcon#enter sib2, iclass 4, count 0 2006.173.10:08:54.24#ibcon#flushed, iclass 4, count 0 2006.173.10:08:54.24#ibcon#about to write, iclass 4, count 0 2006.173.10:08:54.24#ibcon#wrote, iclass 4, count 0 2006.173.10:08:54.24#ibcon#about to read 3, iclass 4, count 0 2006.173.10:08:54.29#ibcon#read 3, iclass 4, count 0 2006.173.10:08:54.29#ibcon#about to read 4, iclass 4, count 0 2006.173.10:08:54.29#ibcon#read 4, iclass 4, count 0 2006.173.10:08:54.29#ibcon#about to read 5, iclass 4, count 0 2006.173.10:08:54.29#ibcon#read 5, iclass 4, count 0 2006.173.10:08:54.29#ibcon#about to read 6, iclass 4, count 0 2006.173.10:08:54.29#ibcon#read 6, iclass 4, count 0 2006.173.10:08:54.29#ibcon#end of sib2, iclass 4, count 0 2006.173.10:08:54.29#ibcon#*after write, iclass 4, count 0 2006.173.10:08:54.29#ibcon#*before return 0, iclass 4, count 0 2006.173.10:08:54.29#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.10:08:54.29#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.10:08:54.29#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.10:08:54.29#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.10:08:54.29$vck44/va=1,7 2006.173.10:08:54.29#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.10:08:54.29#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.10:08:54.29#ibcon#ireg 11 cls_cnt 2 2006.173.10:08:54.29#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.10:08:54.29#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.10:08:54.29#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.10:08:54.29#ibcon#enter wrdev, iclass 6, count 2 2006.173.10:08:54.29#ibcon#first serial, iclass 6, count 2 2006.173.10:08:54.29#ibcon#enter sib2, iclass 6, count 2 2006.173.10:08:54.29#ibcon#flushed, iclass 6, count 2 2006.173.10:08:54.29#ibcon#about to write, iclass 6, count 2 2006.173.10:08:54.29#ibcon#wrote, iclass 6, count 2 2006.173.10:08:54.29#ibcon#about to read 3, iclass 6, count 2 2006.173.10:08:54.31#ibcon#read 3, iclass 6, count 2 2006.173.10:08:54.31#ibcon#about to read 4, iclass 6, count 2 2006.173.10:08:54.31#ibcon#read 4, iclass 6, count 2 2006.173.10:08:54.31#ibcon#about to read 5, iclass 6, count 2 2006.173.10:08:54.31#ibcon#read 5, iclass 6, count 2 2006.173.10:08:54.31#ibcon#about to read 6, iclass 6, count 2 2006.173.10:08:54.31#ibcon#read 6, iclass 6, count 2 2006.173.10:08:54.31#ibcon#end of sib2, iclass 6, count 2 2006.173.10:08:54.31#ibcon#*mode == 0, iclass 6, count 2 2006.173.10:08:54.31#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.10:08:54.31#ibcon#[25=AT01-07\r\n] 2006.173.10:08:54.31#ibcon#*before write, iclass 6, count 2 2006.173.10:08:54.31#ibcon#enter sib2, iclass 6, count 2 2006.173.10:08:54.31#ibcon#flushed, iclass 6, count 2 2006.173.10:08:54.31#ibcon#about to write, iclass 6, count 2 2006.173.10:08:54.31#ibcon#wrote, iclass 6, count 2 2006.173.10:08:54.31#ibcon#about to read 3, iclass 6, count 2 2006.173.10:08:54.34#ibcon#read 3, iclass 6, count 2 2006.173.10:08:54.34#ibcon#about to read 4, iclass 6, count 2 2006.173.10:08:54.34#ibcon#read 4, iclass 6, count 2 2006.173.10:08:54.34#ibcon#about to read 5, iclass 6, count 2 2006.173.10:08:54.34#ibcon#read 5, iclass 6, count 2 2006.173.10:08:54.34#ibcon#about to read 6, iclass 6, count 2 2006.173.10:08:54.34#ibcon#read 6, iclass 6, count 2 2006.173.10:08:54.34#ibcon#end of sib2, iclass 6, count 2 2006.173.10:08:54.34#ibcon#*after write, iclass 6, count 2 2006.173.10:08:54.34#ibcon#*before return 0, iclass 6, count 2 2006.173.10:08:54.34#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.10:08:54.34#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.10:08:54.34#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.10:08:54.34#ibcon#ireg 7 cls_cnt 0 2006.173.10:08:54.34#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.10:08:54.46#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.10:08:54.46#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.10:08:54.46#ibcon#enter wrdev, iclass 6, count 0 2006.173.10:08:54.46#ibcon#first serial, iclass 6, count 0 2006.173.10:08:54.46#ibcon#enter sib2, iclass 6, count 0 2006.173.10:08:54.46#ibcon#flushed, iclass 6, count 0 2006.173.10:08:54.46#ibcon#about to write, iclass 6, count 0 2006.173.10:08:54.46#ibcon#wrote, iclass 6, count 0 2006.173.10:08:54.46#ibcon#about to read 3, iclass 6, count 0 2006.173.10:08:54.48#ibcon#read 3, iclass 6, count 0 2006.173.10:08:54.48#ibcon#about to read 4, iclass 6, count 0 2006.173.10:08:54.48#ibcon#read 4, iclass 6, count 0 2006.173.10:08:54.48#ibcon#about to read 5, iclass 6, count 0 2006.173.10:08:54.48#ibcon#read 5, iclass 6, count 0 2006.173.10:08:54.48#ibcon#about to read 6, iclass 6, count 0 2006.173.10:08:54.48#ibcon#read 6, iclass 6, count 0 2006.173.10:08:54.48#ibcon#end of sib2, iclass 6, count 0 2006.173.10:08:54.48#ibcon#*mode == 0, iclass 6, count 0 2006.173.10:08:54.48#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.10:08:54.48#ibcon#[25=USB\r\n] 2006.173.10:08:54.48#ibcon#*before write, iclass 6, count 0 2006.173.10:08:54.48#ibcon#enter sib2, iclass 6, count 0 2006.173.10:08:54.48#ibcon#flushed, iclass 6, count 0 2006.173.10:08:54.48#ibcon#about to write, iclass 6, count 0 2006.173.10:08:54.48#ibcon#wrote, iclass 6, count 0 2006.173.10:08:54.48#ibcon#about to read 3, iclass 6, count 0 2006.173.10:08:54.51#ibcon#read 3, iclass 6, count 0 2006.173.10:08:54.51#ibcon#about to read 4, iclass 6, count 0 2006.173.10:08:54.51#ibcon#read 4, iclass 6, count 0 2006.173.10:08:54.51#ibcon#about to read 5, iclass 6, count 0 2006.173.10:08:54.51#ibcon#read 5, iclass 6, count 0 2006.173.10:08:54.51#ibcon#about to read 6, iclass 6, count 0 2006.173.10:08:54.51#ibcon#read 6, iclass 6, count 0 2006.173.10:08:54.51#ibcon#end of sib2, iclass 6, count 0 2006.173.10:08:54.51#ibcon#*after write, iclass 6, count 0 2006.173.10:08:54.51#ibcon#*before return 0, iclass 6, count 0 2006.173.10:08:54.51#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.10:08:54.51#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.10:08:54.51#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.10:08:54.51#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.10:08:54.51$vck44/valo=2,534.99 2006.173.10:08:54.51#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.10:08:54.51#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.10:08:54.51#ibcon#ireg 17 cls_cnt 0 2006.173.10:08:54.51#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.10:08:54.51#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.10:08:54.51#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.10:08:54.51#ibcon#enter wrdev, iclass 10, count 0 2006.173.10:08:54.51#ibcon#first serial, iclass 10, count 0 2006.173.10:08:54.51#ibcon#enter sib2, iclass 10, count 0 2006.173.10:08:54.51#ibcon#flushed, iclass 10, count 0 2006.173.10:08:54.51#ibcon#about to write, iclass 10, count 0 2006.173.10:08:54.51#ibcon#wrote, iclass 10, count 0 2006.173.10:08:54.51#ibcon#about to read 3, iclass 10, count 0 2006.173.10:08:54.53#ibcon#read 3, iclass 10, count 0 2006.173.10:08:54.53#ibcon#about to read 4, iclass 10, count 0 2006.173.10:08:54.53#ibcon#read 4, iclass 10, count 0 2006.173.10:08:54.53#ibcon#about to read 5, iclass 10, count 0 2006.173.10:08:54.53#ibcon#read 5, iclass 10, count 0 2006.173.10:08:54.53#ibcon#about to read 6, iclass 10, count 0 2006.173.10:08:54.53#ibcon#read 6, iclass 10, count 0 2006.173.10:08:54.53#ibcon#end of sib2, iclass 10, count 0 2006.173.10:08:54.53#ibcon#*mode == 0, iclass 10, count 0 2006.173.10:08:54.53#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.10:08:54.53#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.10:08:54.53#ibcon#*before write, iclass 10, count 0 2006.173.10:08:54.53#ibcon#enter sib2, iclass 10, count 0 2006.173.10:08:54.53#ibcon#flushed, iclass 10, count 0 2006.173.10:08:54.53#ibcon#about to write, iclass 10, count 0 2006.173.10:08:54.53#ibcon#wrote, iclass 10, count 0 2006.173.10:08:54.53#ibcon#about to read 3, iclass 10, count 0 2006.173.10:08:54.57#ibcon#read 3, iclass 10, count 0 2006.173.10:08:54.57#ibcon#about to read 4, iclass 10, count 0 2006.173.10:08:54.57#ibcon#read 4, iclass 10, count 0 2006.173.10:08:54.57#ibcon#about to read 5, iclass 10, count 0 2006.173.10:08:54.57#ibcon#read 5, iclass 10, count 0 2006.173.10:08:54.57#ibcon#about to read 6, iclass 10, count 0 2006.173.10:08:54.57#ibcon#read 6, iclass 10, count 0 2006.173.10:08:54.57#ibcon#end of sib2, iclass 10, count 0 2006.173.10:08:54.57#ibcon#*after write, iclass 10, count 0 2006.173.10:08:54.57#ibcon#*before return 0, iclass 10, count 0 2006.173.10:08:54.57#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.10:08:54.57#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.10:08:54.57#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.10:08:54.57#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.10:08:54.57$vck44/va=2,6 2006.173.10:08:54.57#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.10:08:54.57#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.10:08:54.57#ibcon#ireg 11 cls_cnt 2 2006.173.10:08:54.57#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.10:08:54.63#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.10:08:54.63#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.10:08:54.63#ibcon#enter wrdev, iclass 12, count 2 2006.173.10:08:54.63#ibcon#first serial, iclass 12, count 2 2006.173.10:08:54.63#ibcon#enter sib2, iclass 12, count 2 2006.173.10:08:54.63#ibcon#flushed, iclass 12, count 2 2006.173.10:08:54.63#ibcon#about to write, iclass 12, count 2 2006.173.10:08:54.63#ibcon#wrote, iclass 12, count 2 2006.173.10:08:54.63#ibcon#about to read 3, iclass 12, count 2 2006.173.10:08:54.65#ibcon#read 3, iclass 12, count 2 2006.173.10:08:54.65#ibcon#about to read 4, iclass 12, count 2 2006.173.10:08:54.65#ibcon#read 4, iclass 12, count 2 2006.173.10:08:54.65#ibcon#about to read 5, iclass 12, count 2 2006.173.10:08:54.65#ibcon#read 5, iclass 12, count 2 2006.173.10:08:54.65#ibcon#about to read 6, iclass 12, count 2 2006.173.10:08:54.65#ibcon#read 6, iclass 12, count 2 2006.173.10:08:54.65#ibcon#end of sib2, iclass 12, count 2 2006.173.10:08:54.65#ibcon#*mode == 0, iclass 12, count 2 2006.173.10:08:54.65#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.10:08:54.65#ibcon#[25=AT02-06\r\n] 2006.173.10:08:54.65#ibcon#*before write, iclass 12, count 2 2006.173.10:08:54.65#ibcon#enter sib2, iclass 12, count 2 2006.173.10:08:54.65#ibcon#flushed, iclass 12, count 2 2006.173.10:08:54.65#ibcon#about to write, iclass 12, count 2 2006.173.10:08:54.65#ibcon#wrote, iclass 12, count 2 2006.173.10:08:54.65#ibcon#about to read 3, iclass 12, count 2 2006.173.10:08:54.68#ibcon#read 3, iclass 12, count 2 2006.173.10:08:54.68#ibcon#about to read 4, iclass 12, count 2 2006.173.10:08:54.68#ibcon#read 4, iclass 12, count 2 2006.173.10:08:54.68#ibcon#about to read 5, iclass 12, count 2 2006.173.10:08:54.68#ibcon#read 5, iclass 12, count 2 2006.173.10:08:54.68#ibcon#about to read 6, iclass 12, count 2 2006.173.10:08:54.68#ibcon#read 6, iclass 12, count 2 2006.173.10:08:54.68#ibcon#end of sib2, iclass 12, count 2 2006.173.10:08:54.68#ibcon#*after write, iclass 12, count 2 2006.173.10:08:54.68#ibcon#*before return 0, iclass 12, count 2 2006.173.10:08:54.68#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.10:08:54.68#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.10:08:54.68#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.10:08:54.68#ibcon#ireg 7 cls_cnt 0 2006.173.10:08:54.68#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.10:08:54.80#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.10:08:54.80#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.10:08:54.80#ibcon#enter wrdev, iclass 12, count 0 2006.173.10:08:54.80#ibcon#first serial, iclass 12, count 0 2006.173.10:08:54.80#ibcon#enter sib2, iclass 12, count 0 2006.173.10:08:54.80#ibcon#flushed, iclass 12, count 0 2006.173.10:08:54.80#ibcon#about to write, iclass 12, count 0 2006.173.10:08:54.80#ibcon#wrote, iclass 12, count 0 2006.173.10:08:54.80#ibcon#about to read 3, iclass 12, count 0 2006.173.10:08:54.82#ibcon#read 3, iclass 12, count 0 2006.173.10:08:54.82#ibcon#about to read 4, iclass 12, count 0 2006.173.10:08:54.82#ibcon#read 4, iclass 12, count 0 2006.173.10:08:54.82#ibcon#about to read 5, iclass 12, count 0 2006.173.10:08:54.82#ibcon#read 5, iclass 12, count 0 2006.173.10:08:54.82#ibcon#about to read 6, iclass 12, count 0 2006.173.10:08:54.82#ibcon#read 6, iclass 12, count 0 2006.173.10:08:54.82#ibcon#end of sib2, iclass 12, count 0 2006.173.10:08:54.82#ibcon#*mode == 0, iclass 12, count 0 2006.173.10:08:54.82#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.10:08:54.82#ibcon#[25=USB\r\n] 2006.173.10:08:54.82#ibcon#*before write, iclass 12, count 0 2006.173.10:08:54.82#ibcon#enter sib2, iclass 12, count 0 2006.173.10:08:54.82#ibcon#flushed, iclass 12, count 0 2006.173.10:08:54.82#ibcon#about to write, iclass 12, count 0 2006.173.10:08:54.82#ibcon#wrote, iclass 12, count 0 2006.173.10:08:54.82#ibcon#about to read 3, iclass 12, count 0 2006.173.10:08:54.85#ibcon#read 3, iclass 12, count 0 2006.173.10:08:54.85#ibcon#about to read 4, iclass 12, count 0 2006.173.10:08:54.85#ibcon#read 4, iclass 12, count 0 2006.173.10:08:54.85#ibcon#about to read 5, iclass 12, count 0 2006.173.10:08:54.85#ibcon#read 5, iclass 12, count 0 2006.173.10:08:54.85#ibcon#about to read 6, iclass 12, count 0 2006.173.10:08:54.85#ibcon#read 6, iclass 12, count 0 2006.173.10:08:54.85#ibcon#end of sib2, iclass 12, count 0 2006.173.10:08:54.85#ibcon#*after write, iclass 12, count 0 2006.173.10:08:54.85#ibcon#*before return 0, iclass 12, count 0 2006.173.10:08:54.85#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.10:08:54.85#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.10:08:54.85#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.10:08:54.85#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.10:08:54.85$vck44/valo=3,564.99 2006.173.10:08:54.85#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.10:08:54.85#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.10:08:54.85#ibcon#ireg 17 cls_cnt 0 2006.173.10:08:54.85#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.10:08:54.85#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.10:08:54.85#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.10:08:54.85#ibcon#enter wrdev, iclass 14, count 0 2006.173.10:08:54.85#ibcon#first serial, iclass 14, count 0 2006.173.10:08:54.85#ibcon#enter sib2, iclass 14, count 0 2006.173.10:08:54.85#ibcon#flushed, iclass 14, count 0 2006.173.10:08:54.85#ibcon#about to write, iclass 14, count 0 2006.173.10:08:54.85#ibcon#wrote, iclass 14, count 0 2006.173.10:08:54.85#ibcon#about to read 3, iclass 14, count 0 2006.173.10:08:54.87#ibcon#read 3, iclass 14, count 0 2006.173.10:08:54.87#ibcon#about to read 4, iclass 14, count 0 2006.173.10:08:54.87#ibcon#read 4, iclass 14, count 0 2006.173.10:08:54.87#ibcon#about to read 5, iclass 14, count 0 2006.173.10:08:54.87#ibcon#read 5, iclass 14, count 0 2006.173.10:08:54.87#ibcon#about to read 6, iclass 14, count 0 2006.173.10:08:54.87#ibcon#read 6, iclass 14, count 0 2006.173.10:08:54.87#ibcon#end of sib2, iclass 14, count 0 2006.173.10:08:54.87#ibcon#*mode == 0, iclass 14, count 0 2006.173.10:08:54.87#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.10:08:54.87#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.10:08:54.87#ibcon#*before write, iclass 14, count 0 2006.173.10:08:54.87#ibcon#enter sib2, iclass 14, count 0 2006.173.10:08:54.87#ibcon#flushed, iclass 14, count 0 2006.173.10:08:54.87#ibcon#about to write, iclass 14, count 0 2006.173.10:08:54.87#ibcon#wrote, iclass 14, count 0 2006.173.10:08:54.87#ibcon#about to read 3, iclass 14, count 0 2006.173.10:08:54.91#ibcon#read 3, iclass 14, count 0 2006.173.10:08:54.91#ibcon#about to read 4, iclass 14, count 0 2006.173.10:08:54.91#ibcon#read 4, iclass 14, count 0 2006.173.10:08:54.91#ibcon#about to read 5, iclass 14, count 0 2006.173.10:08:54.91#ibcon#read 5, iclass 14, count 0 2006.173.10:08:54.91#ibcon#about to read 6, iclass 14, count 0 2006.173.10:08:54.91#ibcon#read 6, iclass 14, count 0 2006.173.10:08:54.91#ibcon#end of sib2, iclass 14, count 0 2006.173.10:08:54.91#ibcon#*after write, iclass 14, count 0 2006.173.10:08:54.91#ibcon#*before return 0, iclass 14, count 0 2006.173.10:08:54.91#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.10:08:54.91#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.10:08:54.91#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.10:08:54.91#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.10:08:54.91$vck44/va=3,5 2006.173.10:08:54.91#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.10:08:54.91#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.10:08:54.91#ibcon#ireg 11 cls_cnt 2 2006.173.10:08:54.91#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.10:08:54.97#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.10:08:54.97#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.10:08:54.97#ibcon#enter wrdev, iclass 16, count 2 2006.173.10:08:54.97#ibcon#first serial, iclass 16, count 2 2006.173.10:08:54.97#ibcon#enter sib2, iclass 16, count 2 2006.173.10:08:54.97#ibcon#flushed, iclass 16, count 2 2006.173.10:08:54.97#ibcon#about to write, iclass 16, count 2 2006.173.10:08:54.97#ibcon#wrote, iclass 16, count 2 2006.173.10:08:54.97#ibcon#about to read 3, iclass 16, count 2 2006.173.10:08:54.99#ibcon#read 3, iclass 16, count 2 2006.173.10:08:54.99#ibcon#about to read 4, iclass 16, count 2 2006.173.10:08:54.99#ibcon#read 4, iclass 16, count 2 2006.173.10:08:54.99#ibcon#about to read 5, iclass 16, count 2 2006.173.10:08:54.99#ibcon#read 5, iclass 16, count 2 2006.173.10:08:54.99#ibcon#about to read 6, iclass 16, count 2 2006.173.10:08:54.99#ibcon#read 6, iclass 16, count 2 2006.173.10:08:54.99#ibcon#end of sib2, iclass 16, count 2 2006.173.10:08:54.99#ibcon#*mode == 0, iclass 16, count 2 2006.173.10:08:54.99#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.10:08:54.99#ibcon#[25=AT03-05\r\n] 2006.173.10:08:54.99#ibcon#*before write, iclass 16, count 2 2006.173.10:08:54.99#ibcon#enter sib2, iclass 16, count 2 2006.173.10:08:54.99#ibcon#flushed, iclass 16, count 2 2006.173.10:08:54.99#ibcon#about to write, iclass 16, count 2 2006.173.10:08:54.99#ibcon#wrote, iclass 16, count 2 2006.173.10:08:54.99#ibcon#about to read 3, iclass 16, count 2 2006.173.10:08:55.02#ibcon#read 3, iclass 16, count 2 2006.173.10:08:55.02#ibcon#about to read 4, iclass 16, count 2 2006.173.10:08:55.02#ibcon#read 4, iclass 16, count 2 2006.173.10:08:55.02#ibcon#about to read 5, iclass 16, count 2 2006.173.10:08:55.02#ibcon#read 5, iclass 16, count 2 2006.173.10:08:55.02#ibcon#about to read 6, iclass 16, count 2 2006.173.10:08:55.02#ibcon#read 6, iclass 16, count 2 2006.173.10:08:55.02#ibcon#end of sib2, iclass 16, count 2 2006.173.10:08:55.02#ibcon#*after write, iclass 16, count 2 2006.173.10:08:55.02#ibcon#*before return 0, iclass 16, count 2 2006.173.10:08:55.02#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.10:08:55.02#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.10:08:55.02#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.10:08:55.02#ibcon#ireg 7 cls_cnt 0 2006.173.10:08:55.02#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.10:08:55.14#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.10:08:55.14#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.10:08:55.14#ibcon#enter wrdev, iclass 16, count 0 2006.173.10:08:55.14#ibcon#first serial, iclass 16, count 0 2006.173.10:08:55.14#ibcon#enter sib2, iclass 16, count 0 2006.173.10:08:55.14#ibcon#flushed, iclass 16, count 0 2006.173.10:08:55.14#ibcon#about to write, iclass 16, count 0 2006.173.10:08:55.14#ibcon#wrote, iclass 16, count 0 2006.173.10:08:55.14#ibcon#about to read 3, iclass 16, count 0 2006.173.10:08:55.16#ibcon#read 3, iclass 16, count 0 2006.173.10:08:55.16#ibcon#about to read 4, iclass 16, count 0 2006.173.10:08:55.16#ibcon#read 4, iclass 16, count 0 2006.173.10:08:55.16#ibcon#about to read 5, iclass 16, count 0 2006.173.10:08:55.16#ibcon#read 5, iclass 16, count 0 2006.173.10:08:55.16#ibcon#about to read 6, iclass 16, count 0 2006.173.10:08:55.16#ibcon#read 6, iclass 16, count 0 2006.173.10:08:55.16#ibcon#end of sib2, iclass 16, count 0 2006.173.10:08:55.16#ibcon#*mode == 0, iclass 16, count 0 2006.173.10:08:55.16#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.10:08:55.16#ibcon#[25=USB\r\n] 2006.173.10:08:55.16#ibcon#*before write, iclass 16, count 0 2006.173.10:08:55.16#ibcon#enter sib2, iclass 16, count 0 2006.173.10:08:55.16#ibcon#flushed, iclass 16, count 0 2006.173.10:08:55.16#ibcon#about to write, iclass 16, count 0 2006.173.10:08:55.16#ibcon#wrote, iclass 16, count 0 2006.173.10:08:55.16#ibcon#about to read 3, iclass 16, count 0 2006.173.10:08:55.19#ibcon#read 3, iclass 16, count 0 2006.173.10:08:55.19#ibcon#about to read 4, iclass 16, count 0 2006.173.10:08:55.19#ibcon#read 4, iclass 16, count 0 2006.173.10:08:55.19#ibcon#about to read 5, iclass 16, count 0 2006.173.10:08:55.19#ibcon#read 5, iclass 16, count 0 2006.173.10:08:55.19#ibcon#about to read 6, iclass 16, count 0 2006.173.10:08:55.19#ibcon#read 6, iclass 16, count 0 2006.173.10:08:55.19#ibcon#end of sib2, iclass 16, count 0 2006.173.10:08:55.19#ibcon#*after write, iclass 16, count 0 2006.173.10:08:55.19#ibcon#*before return 0, iclass 16, count 0 2006.173.10:08:55.19#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.10:08:55.19#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.10:08:55.19#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.10:08:55.19#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.10:08:55.19$vck44/valo=4,624.99 2006.173.10:08:55.19#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.10:08:55.19#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.10:08:55.19#ibcon#ireg 17 cls_cnt 0 2006.173.10:08:55.19#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.10:08:55.19#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.10:08:55.19#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.10:08:55.19#ibcon#enter wrdev, iclass 18, count 0 2006.173.10:08:55.19#ibcon#first serial, iclass 18, count 0 2006.173.10:08:55.19#ibcon#enter sib2, iclass 18, count 0 2006.173.10:08:55.19#ibcon#flushed, iclass 18, count 0 2006.173.10:08:55.19#ibcon#about to write, iclass 18, count 0 2006.173.10:08:55.19#ibcon#wrote, iclass 18, count 0 2006.173.10:08:55.19#ibcon#about to read 3, iclass 18, count 0 2006.173.10:08:55.21#ibcon#read 3, iclass 18, count 0 2006.173.10:08:55.21#ibcon#about to read 4, iclass 18, count 0 2006.173.10:08:55.21#ibcon#read 4, iclass 18, count 0 2006.173.10:08:55.21#ibcon#about to read 5, iclass 18, count 0 2006.173.10:08:55.21#ibcon#read 5, iclass 18, count 0 2006.173.10:08:55.21#ibcon#about to read 6, iclass 18, count 0 2006.173.10:08:55.21#ibcon#read 6, iclass 18, count 0 2006.173.10:08:55.21#ibcon#end of sib2, iclass 18, count 0 2006.173.10:08:55.21#ibcon#*mode == 0, iclass 18, count 0 2006.173.10:08:55.21#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.10:08:55.21#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.10:08:55.21#ibcon#*before write, iclass 18, count 0 2006.173.10:08:55.21#ibcon#enter sib2, iclass 18, count 0 2006.173.10:08:55.21#ibcon#flushed, iclass 18, count 0 2006.173.10:08:55.21#ibcon#about to write, iclass 18, count 0 2006.173.10:08:55.21#ibcon#wrote, iclass 18, count 0 2006.173.10:08:55.21#ibcon#about to read 3, iclass 18, count 0 2006.173.10:08:55.25#ibcon#read 3, iclass 18, count 0 2006.173.10:08:55.25#ibcon#about to read 4, iclass 18, count 0 2006.173.10:08:55.25#ibcon#read 4, iclass 18, count 0 2006.173.10:08:55.25#ibcon#about to read 5, iclass 18, count 0 2006.173.10:08:55.25#ibcon#read 5, iclass 18, count 0 2006.173.10:08:55.25#ibcon#about to read 6, iclass 18, count 0 2006.173.10:08:55.25#ibcon#read 6, iclass 18, count 0 2006.173.10:08:55.25#ibcon#end of sib2, iclass 18, count 0 2006.173.10:08:55.25#ibcon#*after write, iclass 18, count 0 2006.173.10:08:55.25#ibcon#*before return 0, iclass 18, count 0 2006.173.10:08:55.25#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.10:08:55.25#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.10:08:55.25#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.10:08:55.25#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.10:08:55.25$vck44/va=4,6 2006.173.10:08:55.25#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.10:08:55.25#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.10:08:55.25#ibcon#ireg 11 cls_cnt 2 2006.173.10:08:55.25#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.10:08:55.31#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.10:08:55.31#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.10:08:55.31#ibcon#enter wrdev, iclass 20, count 2 2006.173.10:08:55.31#ibcon#first serial, iclass 20, count 2 2006.173.10:08:55.31#ibcon#enter sib2, iclass 20, count 2 2006.173.10:08:55.31#ibcon#flushed, iclass 20, count 2 2006.173.10:08:55.31#ibcon#about to write, iclass 20, count 2 2006.173.10:08:55.31#ibcon#wrote, iclass 20, count 2 2006.173.10:08:55.31#ibcon#about to read 3, iclass 20, count 2 2006.173.10:08:55.33#ibcon#read 3, iclass 20, count 2 2006.173.10:08:55.33#ibcon#about to read 4, iclass 20, count 2 2006.173.10:08:55.33#ibcon#read 4, iclass 20, count 2 2006.173.10:08:55.33#ibcon#about to read 5, iclass 20, count 2 2006.173.10:08:55.33#ibcon#read 5, iclass 20, count 2 2006.173.10:08:55.33#ibcon#about to read 6, iclass 20, count 2 2006.173.10:08:55.33#ibcon#read 6, iclass 20, count 2 2006.173.10:08:55.33#ibcon#end of sib2, iclass 20, count 2 2006.173.10:08:55.33#ibcon#*mode == 0, iclass 20, count 2 2006.173.10:08:55.33#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.10:08:55.33#ibcon#[25=AT04-06\r\n] 2006.173.10:08:55.33#ibcon#*before write, iclass 20, count 2 2006.173.10:08:55.33#ibcon#enter sib2, iclass 20, count 2 2006.173.10:08:55.33#ibcon#flushed, iclass 20, count 2 2006.173.10:08:55.33#ibcon#about to write, iclass 20, count 2 2006.173.10:08:55.33#ibcon#wrote, iclass 20, count 2 2006.173.10:08:55.33#ibcon#about to read 3, iclass 20, count 2 2006.173.10:08:55.36#ibcon#read 3, iclass 20, count 2 2006.173.10:08:55.36#ibcon#about to read 4, iclass 20, count 2 2006.173.10:08:55.36#ibcon#read 4, iclass 20, count 2 2006.173.10:08:55.36#ibcon#about to read 5, iclass 20, count 2 2006.173.10:08:55.36#ibcon#read 5, iclass 20, count 2 2006.173.10:08:55.36#ibcon#about to read 6, iclass 20, count 2 2006.173.10:08:55.36#ibcon#read 6, iclass 20, count 2 2006.173.10:08:55.36#ibcon#end of sib2, iclass 20, count 2 2006.173.10:08:55.36#ibcon#*after write, iclass 20, count 2 2006.173.10:08:55.36#ibcon#*before return 0, iclass 20, count 2 2006.173.10:08:55.36#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.10:08:55.36#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.10:08:55.36#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.10:08:55.36#ibcon#ireg 7 cls_cnt 0 2006.173.10:08:55.36#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.10:08:55.48#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.10:08:55.48#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.10:08:55.48#ibcon#enter wrdev, iclass 20, count 0 2006.173.10:08:55.48#ibcon#first serial, iclass 20, count 0 2006.173.10:08:55.48#ibcon#enter sib2, iclass 20, count 0 2006.173.10:08:55.48#ibcon#flushed, iclass 20, count 0 2006.173.10:08:55.48#ibcon#about to write, iclass 20, count 0 2006.173.10:08:55.48#ibcon#wrote, iclass 20, count 0 2006.173.10:08:55.48#ibcon#about to read 3, iclass 20, count 0 2006.173.10:08:55.50#ibcon#read 3, iclass 20, count 0 2006.173.10:08:55.50#ibcon#about to read 4, iclass 20, count 0 2006.173.10:08:55.50#ibcon#read 4, iclass 20, count 0 2006.173.10:08:55.50#ibcon#about to read 5, iclass 20, count 0 2006.173.10:08:55.50#ibcon#read 5, iclass 20, count 0 2006.173.10:08:55.50#ibcon#about to read 6, iclass 20, count 0 2006.173.10:08:55.50#ibcon#read 6, iclass 20, count 0 2006.173.10:08:55.50#ibcon#end of sib2, iclass 20, count 0 2006.173.10:08:55.50#ibcon#*mode == 0, iclass 20, count 0 2006.173.10:08:55.50#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.10:08:55.50#ibcon#[25=USB\r\n] 2006.173.10:08:55.50#ibcon#*before write, iclass 20, count 0 2006.173.10:08:55.50#ibcon#enter sib2, iclass 20, count 0 2006.173.10:08:55.50#ibcon#flushed, iclass 20, count 0 2006.173.10:08:55.50#ibcon#about to write, iclass 20, count 0 2006.173.10:08:55.50#ibcon#wrote, iclass 20, count 0 2006.173.10:08:55.50#ibcon#about to read 3, iclass 20, count 0 2006.173.10:08:55.53#ibcon#read 3, iclass 20, count 0 2006.173.10:08:55.53#ibcon#about to read 4, iclass 20, count 0 2006.173.10:08:55.53#ibcon#read 4, iclass 20, count 0 2006.173.10:08:55.53#ibcon#about to read 5, iclass 20, count 0 2006.173.10:08:55.53#ibcon#read 5, iclass 20, count 0 2006.173.10:08:55.53#ibcon#about to read 6, iclass 20, count 0 2006.173.10:08:55.53#ibcon#read 6, iclass 20, count 0 2006.173.10:08:55.53#ibcon#end of sib2, iclass 20, count 0 2006.173.10:08:55.53#ibcon#*after write, iclass 20, count 0 2006.173.10:08:55.53#ibcon#*before return 0, iclass 20, count 0 2006.173.10:08:55.53#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.10:08:55.53#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.10:08:55.53#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.10:08:55.53#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.10:08:55.53$vck44/valo=5,734.99 2006.173.10:08:55.53#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.10:08:55.53#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.10:08:55.53#ibcon#ireg 17 cls_cnt 0 2006.173.10:08:55.53#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.10:08:55.53#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.10:08:55.53#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.10:08:55.53#ibcon#enter wrdev, iclass 22, count 0 2006.173.10:08:55.53#ibcon#first serial, iclass 22, count 0 2006.173.10:08:55.53#ibcon#enter sib2, iclass 22, count 0 2006.173.10:08:55.53#ibcon#flushed, iclass 22, count 0 2006.173.10:08:55.53#ibcon#about to write, iclass 22, count 0 2006.173.10:08:55.53#ibcon#wrote, iclass 22, count 0 2006.173.10:08:55.53#ibcon#about to read 3, iclass 22, count 0 2006.173.10:08:55.55#ibcon#read 3, iclass 22, count 0 2006.173.10:08:55.55#ibcon#about to read 4, iclass 22, count 0 2006.173.10:08:55.55#ibcon#read 4, iclass 22, count 0 2006.173.10:08:55.55#ibcon#about to read 5, iclass 22, count 0 2006.173.10:08:55.55#ibcon#read 5, iclass 22, count 0 2006.173.10:08:55.55#ibcon#about to read 6, iclass 22, count 0 2006.173.10:08:55.55#ibcon#read 6, iclass 22, count 0 2006.173.10:08:55.55#ibcon#end of sib2, iclass 22, count 0 2006.173.10:08:55.55#ibcon#*mode == 0, iclass 22, count 0 2006.173.10:08:55.55#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.10:08:55.55#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.10:08:55.55#ibcon#*before write, iclass 22, count 0 2006.173.10:08:55.55#ibcon#enter sib2, iclass 22, count 0 2006.173.10:08:55.55#ibcon#flushed, iclass 22, count 0 2006.173.10:08:55.55#ibcon#about to write, iclass 22, count 0 2006.173.10:08:55.55#ibcon#wrote, iclass 22, count 0 2006.173.10:08:55.55#ibcon#about to read 3, iclass 22, count 0 2006.173.10:08:55.59#ibcon#read 3, iclass 22, count 0 2006.173.10:08:55.59#ibcon#about to read 4, iclass 22, count 0 2006.173.10:08:55.59#ibcon#read 4, iclass 22, count 0 2006.173.10:08:55.59#ibcon#about to read 5, iclass 22, count 0 2006.173.10:08:55.59#ibcon#read 5, iclass 22, count 0 2006.173.10:08:55.59#ibcon#about to read 6, iclass 22, count 0 2006.173.10:08:55.59#ibcon#read 6, iclass 22, count 0 2006.173.10:08:55.59#ibcon#end of sib2, iclass 22, count 0 2006.173.10:08:55.59#ibcon#*after write, iclass 22, count 0 2006.173.10:08:55.59#ibcon#*before return 0, iclass 22, count 0 2006.173.10:08:55.59#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.10:08:55.59#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.10:08:55.59#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.10:08:55.59#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.10:08:55.59$vck44/va=5,4 2006.173.10:08:55.59#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.10:08:55.59#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.10:08:55.59#ibcon#ireg 11 cls_cnt 2 2006.173.10:08:55.59#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.10:08:55.65#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.10:08:55.65#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.10:08:55.65#ibcon#enter wrdev, iclass 24, count 2 2006.173.10:08:55.65#ibcon#first serial, iclass 24, count 2 2006.173.10:08:55.65#ibcon#enter sib2, iclass 24, count 2 2006.173.10:08:55.65#ibcon#flushed, iclass 24, count 2 2006.173.10:08:55.65#ibcon#about to write, iclass 24, count 2 2006.173.10:08:55.65#ibcon#wrote, iclass 24, count 2 2006.173.10:08:55.65#ibcon#about to read 3, iclass 24, count 2 2006.173.10:08:55.67#ibcon#read 3, iclass 24, count 2 2006.173.10:08:55.67#ibcon#about to read 4, iclass 24, count 2 2006.173.10:08:55.67#ibcon#read 4, iclass 24, count 2 2006.173.10:08:55.67#ibcon#about to read 5, iclass 24, count 2 2006.173.10:08:55.67#ibcon#read 5, iclass 24, count 2 2006.173.10:08:55.67#ibcon#about to read 6, iclass 24, count 2 2006.173.10:08:55.67#ibcon#read 6, iclass 24, count 2 2006.173.10:08:55.67#ibcon#end of sib2, iclass 24, count 2 2006.173.10:08:55.67#ibcon#*mode == 0, iclass 24, count 2 2006.173.10:08:55.67#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.10:08:55.67#ibcon#[25=AT05-04\r\n] 2006.173.10:08:55.67#ibcon#*before write, iclass 24, count 2 2006.173.10:08:55.67#ibcon#enter sib2, iclass 24, count 2 2006.173.10:08:55.67#ibcon#flushed, iclass 24, count 2 2006.173.10:08:55.67#ibcon#about to write, iclass 24, count 2 2006.173.10:08:55.67#ibcon#wrote, iclass 24, count 2 2006.173.10:08:55.67#ibcon#about to read 3, iclass 24, count 2 2006.173.10:08:55.70#ibcon#read 3, iclass 24, count 2 2006.173.10:08:55.70#ibcon#about to read 4, iclass 24, count 2 2006.173.10:08:55.70#ibcon#read 4, iclass 24, count 2 2006.173.10:08:55.70#ibcon#about to read 5, iclass 24, count 2 2006.173.10:08:55.70#ibcon#read 5, iclass 24, count 2 2006.173.10:08:55.70#ibcon#about to read 6, iclass 24, count 2 2006.173.10:08:55.70#ibcon#read 6, iclass 24, count 2 2006.173.10:08:55.70#ibcon#end of sib2, iclass 24, count 2 2006.173.10:08:55.70#ibcon#*after write, iclass 24, count 2 2006.173.10:08:55.70#ibcon#*before return 0, iclass 24, count 2 2006.173.10:08:55.70#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.10:08:55.70#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.10:08:55.70#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.10:08:55.70#ibcon#ireg 7 cls_cnt 0 2006.173.10:08:55.70#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.10:08:55.82#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.10:08:55.82#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.10:08:55.82#ibcon#enter wrdev, iclass 24, count 0 2006.173.10:08:55.82#ibcon#first serial, iclass 24, count 0 2006.173.10:08:55.82#ibcon#enter sib2, iclass 24, count 0 2006.173.10:08:55.82#ibcon#flushed, iclass 24, count 0 2006.173.10:08:55.82#ibcon#about to write, iclass 24, count 0 2006.173.10:08:55.82#ibcon#wrote, iclass 24, count 0 2006.173.10:08:55.82#ibcon#about to read 3, iclass 24, count 0 2006.173.10:08:55.84#ibcon#read 3, iclass 24, count 0 2006.173.10:08:55.84#ibcon#about to read 4, iclass 24, count 0 2006.173.10:08:55.84#ibcon#read 4, iclass 24, count 0 2006.173.10:08:55.84#ibcon#about to read 5, iclass 24, count 0 2006.173.10:08:55.84#ibcon#read 5, iclass 24, count 0 2006.173.10:08:55.84#ibcon#about to read 6, iclass 24, count 0 2006.173.10:08:55.84#ibcon#read 6, iclass 24, count 0 2006.173.10:08:55.84#ibcon#end of sib2, iclass 24, count 0 2006.173.10:08:55.84#ibcon#*mode == 0, iclass 24, count 0 2006.173.10:08:55.84#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.10:08:55.84#ibcon#[25=USB\r\n] 2006.173.10:08:55.84#ibcon#*before write, iclass 24, count 0 2006.173.10:08:55.84#ibcon#enter sib2, iclass 24, count 0 2006.173.10:08:55.84#ibcon#flushed, iclass 24, count 0 2006.173.10:08:55.84#ibcon#about to write, iclass 24, count 0 2006.173.10:08:55.84#ibcon#wrote, iclass 24, count 0 2006.173.10:08:55.84#ibcon#about to read 3, iclass 24, count 0 2006.173.10:08:55.87#ibcon#read 3, iclass 24, count 0 2006.173.10:08:55.87#ibcon#about to read 4, iclass 24, count 0 2006.173.10:08:55.87#ibcon#read 4, iclass 24, count 0 2006.173.10:08:55.87#ibcon#about to read 5, iclass 24, count 0 2006.173.10:08:55.87#ibcon#read 5, iclass 24, count 0 2006.173.10:08:55.87#ibcon#about to read 6, iclass 24, count 0 2006.173.10:08:55.87#ibcon#read 6, iclass 24, count 0 2006.173.10:08:55.87#ibcon#end of sib2, iclass 24, count 0 2006.173.10:08:55.87#ibcon#*after write, iclass 24, count 0 2006.173.10:08:55.87#ibcon#*before return 0, iclass 24, count 0 2006.173.10:08:55.87#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.10:08:55.87#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.10:08:55.87#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.10:08:55.87#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.10:08:55.87$vck44/valo=6,814.99 2006.173.10:08:55.87#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.10:08:55.87#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.10:08:55.87#ibcon#ireg 17 cls_cnt 0 2006.173.10:08:55.87#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.10:08:55.87#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.10:08:55.87#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.10:08:55.87#ibcon#enter wrdev, iclass 26, count 0 2006.173.10:08:55.87#ibcon#first serial, iclass 26, count 0 2006.173.10:08:55.87#ibcon#enter sib2, iclass 26, count 0 2006.173.10:08:55.87#ibcon#flushed, iclass 26, count 0 2006.173.10:08:55.87#ibcon#about to write, iclass 26, count 0 2006.173.10:08:55.87#ibcon#wrote, iclass 26, count 0 2006.173.10:08:55.87#ibcon#about to read 3, iclass 26, count 0 2006.173.10:08:55.89#ibcon#read 3, iclass 26, count 0 2006.173.10:08:55.89#ibcon#about to read 4, iclass 26, count 0 2006.173.10:08:55.89#ibcon#read 4, iclass 26, count 0 2006.173.10:08:55.89#ibcon#about to read 5, iclass 26, count 0 2006.173.10:08:55.89#ibcon#read 5, iclass 26, count 0 2006.173.10:08:55.89#ibcon#about to read 6, iclass 26, count 0 2006.173.10:08:55.89#ibcon#read 6, iclass 26, count 0 2006.173.10:08:55.89#ibcon#end of sib2, iclass 26, count 0 2006.173.10:08:55.89#ibcon#*mode == 0, iclass 26, count 0 2006.173.10:08:55.89#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.10:08:55.89#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.10:08:55.89#ibcon#*before write, iclass 26, count 0 2006.173.10:08:55.89#ibcon#enter sib2, iclass 26, count 0 2006.173.10:08:55.89#ibcon#flushed, iclass 26, count 0 2006.173.10:08:55.89#ibcon#about to write, iclass 26, count 0 2006.173.10:08:55.89#ibcon#wrote, iclass 26, count 0 2006.173.10:08:55.89#ibcon#about to read 3, iclass 26, count 0 2006.173.10:08:55.93#ibcon#read 3, iclass 26, count 0 2006.173.10:08:55.93#ibcon#about to read 4, iclass 26, count 0 2006.173.10:08:55.93#ibcon#read 4, iclass 26, count 0 2006.173.10:08:55.93#ibcon#about to read 5, iclass 26, count 0 2006.173.10:08:55.93#ibcon#read 5, iclass 26, count 0 2006.173.10:08:55.93#ibcon#about to read 6, iclass 26, count 0 2006.173.10:08:55.93#ibcon#read 6, iclass 26, count 0 2006.173.10:08:55.93#ibcon#end of sib2, iclass 26, count 0 2006.173.10:08:55.93#ibcon#*after write, iclass 26, count 0 2006.173.10:08:55.93#ibcon#*before return 0, iclass 26, count 0 2006.173.10:08:55.93#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.10:08:55.93#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.10:08:55.93#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.10:08:55.93#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.10:08:55.93$vck44/va=6,3 2006.173.10:08:55.93#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.10:08:55.93#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.10:08:55.93#ibcon#ireg 11 cls_cnt 2 2006.173.10:08:55.93#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.10:08:55.99#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.10:08:55.99#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.10:08:55.99#ibcon#enter wrdev, iclass 28, count 2 2006.173.10:08:55.99#ibcon#first serial, iclass 28, count 2 2006.173.10:08:55.99#ibcon#enter sib2, iclass 28, count 2 2006.173.10:08:55.99#ibcon#flushed, iclass 28, count 2 2006.173.10:08:55.99#ibcon#about to write, iclass 28, count 2 2006.173.10:08:55.99#ibcon#wrote, iclass 28, count 2 2006.173.10:08:55.99#ibcon#about to read 3, iclass 28, count 2 2006.173.10:08:56.01#ibcon#read 3, iclass 28, count 2 2006.173.10:08:56.01#ibcon#about to read 4, iclass 28, count 2 2006.173.10:08:56.01#ibcon#read 4, iclass 28, count 2 2006.173.10:08:56.01#ibcon#about to read 5, iclass 28, count 2 2006.173.10:08:56.01#ibcon#read 5, iclass 28, count 2 2006.173.10:08:56.01#ibcon#about to read 6, iclass 28, count 2 2006.173.10:08:56.01#ibcon#read 6, iclass 28, count 2 2006.173.10:08:56.01#ibcon#end of sib2, iclass 28, count 2 2006.173.10:08:56.01#ibcon#*mode == 0, iclass 28, count 2 2006.173.10:08:56.01#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.10:08:56.01#ibcon#[25=AT06-03\r\n] 2006.173.10:08:56.01#ibcon#*before write, iclass 28, count 2 2006.173.10:08:56.01#ibcon#enter sib2, iclass 28, count 2 2006.173.10:08:56.01#ibcon#flushed, iclass 28, count 2 2006.173.10:08:56.01#ibcon#about to write, iclass 28, count 2 2006.173.10:08:56.01#ibcon#wrote, iclass 28, count 2 2006.173.10:08:56.01#ibcon#about to read 3, iclass 28, count 2 2006.173.10:08:56.04#ibcon#read 3, iclass 28, count 2 2006.173.10:08:56.04#ibcon#about to read 4, iclass 28, count 2 2006.173.10:08:56.04#ibcon#read 4, iclass 28, count 2 2006.173.10:08:56.04#ibcon#about to read 5, iclass 28, count 2 2006.173.10:08:56.04#ibcon#read 5, iclass 28, count 2 2006.173.10:08:56.04#ibcon#about to read 6, iclass 28, count 2 2006.173.10:08:56.04#ibcon#read 6, iclass 28, count 2 2006.173.10:08:56.04#ibcon#end of sib2, iclass 28, count 2 2006.173.10:08:56.04#ibcon#*after write, iclass 28, count 2 2006.173.10:08:56.04#ibcon#*before return 0, iclass 28, count 2 2006.173.10:08:56.04#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.10:08:56.04#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.10:08:56.04#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.10:08:56.04#ibcon#ireg 7 cls_cnt 0 2006.173.10:08:56.04#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.10:08:56.16#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.10:08:56.16#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.10:08:56.16#ibcon#enter wrdev, iclass 28, count 0 2006.173.10:08:56.16#ibcon#first serial, iclass 28, count 0 2006.173.10:08:56.16#ibcon#enter sib2, iclass 28, count 0 2006.173.10:08:56.16#ibcon#flushed, iclass 28, count 0 2006.173.10:08:56.16#ibcon#about to write, iclass 28, count 0 2006.173.10:08:56.16#ibcon#wrote, iclass 28, count 0 2006.173.10:08:56.16#ibcon#about to read 3, iclass 28, count 0 2006.173.10:08:56.18#ibcon#read 3, iclass 28, count 0 2006.173.10:08:56.18#ibcon#about to read 4, iclass 28, count 0 2006.173.10:08:56.18#ibcon#read 4, iclass 28, count 0 2006.173.10:08:56.18#ibcon#about to read 5, iclass 28, count 0 2006.173.10:08:56.18#ibcon#read 5, iclass 28, count 0 2006.173.10:08:56.18#ibcon#about to read 6, iclass 28, count 0 2006.173.10:08:56.18#ibcon#read 6, iclass 28, count 0 2006.173.10:08:56.18#ibcon#end of sib2, iclass 28, count 0 2006.173.10:08:56.18#ibcon#*mode == 0, iclass 28, count 0 2006.173.10:08:56.18#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.10:08:56.18#ibcon#[25=USB\r\n] 2006.173.10:08:56.18#ibcon#*before write, iclass 28, count 0 2006.173.10:08:56.18#ibcon#enter sib2, iclass 28, count 0 2006.173.10:08:56.18#ibcon#flushed, iclass 28, count 0 2006.173.10:08:56.18#ibcon#about to write, iclass 28, count 0 2006.173.10:08:56.18#ibcon#wrote, iclass 28, count 0 2006.173.10:08:56.18#ibcon#about to read 3, iclass 28, count 0 2006.173.10:08:56.21#ibcon#read 3, iclass 28, count 0 2006.173.10:08:56.21#ibcon#about to read 4, iclass 28, count 0 2006.173.10:08:56.21#ibcon#read 4, iclass 28, count 0 2006.173.10:08:56.21#ibcon#about to read 5, iclass 28, count 0 2006.173.10:08:56.21#ibcon#read 5, iclass 28, count 0 2006.173.10:08:56.21#ibcon#about to read 6, iclass 28, count 0 2006.173.10:08:56.21#ibcon#read 6, iclass 28, count 0 2006.173.10:08:56.21#ibcon#end of sib2, iclass 28, count 0 2006.173.10:08:56.21#ibcon#*after write, iclass 28, count 0 2006.173.10:08:56.21#ibcon#*before return 0, iclass 28, count 0 2006.173.10:08:56.21#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.10:08:56.21#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.10:08:56.21#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.10:08:56.21#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.10:08:56.21$vck44/valo=7,864.99 2006.173.10:08:56.21#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.10:08:56.21#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.10:08:56.21#ibcon#ireg 17 cls_cnt 0 2006.173.10:08:56.21#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.10:08:56.21#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.10:08:56.21#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.10:08:56.21#ibcon#enter wrdev, iclass 30, count 0 2006.173.10:08:56.21#ibcon#first serial, iclass 30, count 0 2006.173.10:08:56.21#ibcon#enter sib2, iclass 30, count 0 2006.173.10:08:56.21#ibcon#flushed, iclass 30, count 0 2006.173.10:08:56.21#ibcon#about to write, iclass 30, count 0 2006.173.10:08:56.21#ibcon#wrote, iclass 30, count 0 2006.173.10:08:56.21#ibcon#about to read 3, iclass 30, count 0 2006.173.10:08:56.23#ibcon#read 3, iclass 30, count 0 2006.173.10:08:56.23#ibcon#about to read 4, iclass 30, count 0 2006.173.10:08:56.23#ibcon#read 4, iclass 30, count 0 2006.173.10:08:56.23#ibcon#about to read 5, iclass 30, count 0 2006.173.10:08:56.23#ibcon#read 5, iclass 30, count 0 2006.173.10:08:56.23#ibcon#about to read 6, iclass 30, count 0 2006.173.10:08:56.23#ibcon#read 6, iclass 30, count 0 2006.173.10:08:56.23#ibcon#end of sib2, iclass 30, count 0 2006.173.10:08:56.23#ibcon#*mode == 0, iclass 30, count 0 2006.173.10:08:56.23#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.10:08:56.23#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.10:08:56.23#ibcon#*before write, iclass 30, count 0 2006.173.10:08:56.23#ibcon#enter sib2, iclass 30, count 0 2006.173.10:08:56.23#ibcon#flushed, iclass 30, count 0 2006.173.10:08:56.23#ibcon#about to write, iclass 30, count 0 2006.173.10:08:56.23#ibcon#wrote, iclass 30, count 0 2006.173.10:08:56.23#ibcon#about to read 3, iclass 30, count 0 2006.173.10:08:56.27#ibcon#read 3, iclass 30, count 0 2006.173.10:08:56.27#ibcon#about to read 4, iclass 30, count 0 2006.173.10:08:56.27#ibcon#read 4, iclass 30, count 0 2006.173.10:08:56.27#ibcon#about to read 5, iclass 30, count 0 2006.173.10:08:56.27#ibcon#read 5, iclass 30, count 0 2006.173.10:08:56.27#ibcon#about to read 6, iclass 30, count 0 2006.173.10:08:56.27#ibcon#read 6, iclass 30, count 0 2006.173.10:08:56.27#ibcon#end of sib2, iclass 30, count 0 2006.173.10:08:56.27#ibcon#*after write, iclass 30, count 0 2006.173.10:08:56.27#ibcon#*before return 0, iclass 30, count 0 2006.173.10:08:56.27#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.10:08:56.27#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.10:08:56.27#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.10:08:56.27#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.10:08:56.27$vck44/va=7,4 2006.173.10:08:56.27#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.173.10:08:56.27#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.173.10:08:56.27#ibcon#ireg 11 cls_cnt 2 2006.173.10:08:56.27#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.10:08:56.33#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.10:08:56.33#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.10:08:56.33#ibcon#enter wrdev, iclass 32, count 2 2006.173.10:08:56.33#ibcon#first serial, iclass 32, count 2 2006.173.10:08:56.33#ibcon#enter sib2, iclass 32, count 2 2006.173.10:08:56.33#ibcon#flushed, iclass 32, count 2 2006.173.10:08:56.33#ibcon#about to write, iclass 32, count 2 2006.173.10:08:56.33#ibcon#wrote, iclass 32, count 2 2006.173.10:08:56.33#ibcon#about to read 3, iclass 32, count 2 2006.173.10:08:56.35#ibcon#read 3, iclass 32, count 2 2006.173.10:08:56.35#ibcon#about to read 4, iclass 32, count 2 2006.173.10:08:56.35#ibcon#read 4, iclass 32, count 2 2006.173.10:08:56.35#ibcon#about to read 5, iclass 32, count 2 2006.173.10:08:56.35#ibcon#read 5, iclass 32, count 2 2006.173.10:08:56.35#ibcon#about to read 6, iclass 32, count 2 2006.173.10:08:56.35#ibcon#read 6, iclass 32, count 2 2006.173.10:08:56.35#ibcon#end of sib2, iclass 32, count 2 2006.173.10:08:56.35#ibcon#*mode == 0, iclass 32, count 2 2006.173.10:08:56.35#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.173.10:08:56.35#ibcon#[25=AT07-04\r\n] 2006.173.10:08:56.35#ibcon#*before write, iclass 32, count 2 2006.173.10:08:56.35#ibcon#enter sib2, iclass 32, count 2 2006.173.10:08:56.35#ibcon#flushed, iclass 32, count 2 2006.173.10:08:56.35#ibcon#about to write, iclass 32, count 2 2006.173.10:08:56.35#ibcon#wrote, iclass 32, count 2 2006.173.10:08:56.35#ibcon#about to read 3, iclass 32, count 2 2006.173.10:08:56.38#ibcon#read 3, iclass 32, count 2 2006.173.10:08:56.38#ibcon#about to read 4, iclass 32, count 2 2006.173.10:08:56.38#ibcon#read 4, iclass 32, count 2 2006.173.10:08:56.38#ibcon#about to read 5, iclass 32, count 2 2006.173.10:08:56.38#ibcon#read 5, iclass 32, count 2 2006.173.10:08:56.38#ibcon#about to read 6, iclass 32, count 2 2006.173.10:08:56.38#ibcon#read 6, iclass 32, count 2 2006.173.10:08:56.38#ibcon#end of sib2, iclass 32, count 2 2006.173.10:08:56.38#ibcon#*after write, iclass 32, count 2 2006.173.10:08:56.38#ibcon#*before return 0, iclass 32, count 2 2006.173.10:08:56.38#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.10:08:56.38#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.173.10:08:56.38#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.173.10:08:56.38#ibcon#ireg 7 cls_cnt 0 2006.173.10:08:56.38#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.10:08:56.50#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.10:08:56.50#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.10:08:56.50#ibcon#enter wrdev, iclass 32, count 0 2006.173.10:08:56.50#ibcon#first serial, iclass 32, count 0 2006.173.10:08:56.50#ibcon#enter sib2, iclass 32, count 0 2006.173.10:08:56.50#ibcon#flushed, iclass 32, count 0 2006.173.10:08:56.50#ibcon#about to write, iclass 32, count 0 2006.173.10:08:56.50#ibcon#wrote, iclass 32, count 0 2006.173.10:08:56.50#ibcon#about to read 3, iclass 32, count 0 2006.173.10:08:56.52#ibcon#read 3, iclass 32, count 0 2006.173.10:08:56.52#ibcon#about to read 4, iclass 32, count 0 2006.173.10:08:56.52#ibcon#read 4, iclass 32, count 0 2006.173.10:08:56.52#ibcon#about to read 5, iclass 32, count 0 2006.173.10:08:56.52#ibcon#read 5, iclass 32, count 0 2006.173.10:08:56.52#ibcon#about to read 6, iclass 32, count 0 2006.173.10:08:56.52#ibcon#read 6, iclass 32, count 0 2006.173.10:08:56.52#ibcon#end of sib2, iclass 32, count 0 2006.173.10:08:56.52#ibcon#*mode == 0, iclass 32, count 0 2006.173.10:08:56.52#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.10:08:56.52#ibcon#[25=USB\r\n] 2006.173.10:08:56.52#ibcon#*before write, iclass 32, count 0 2006.173.10:08:56.52#ibcon#enter sib2, iclass 32, count 0 2006.173.10:08:56.52#ibcon#flushed, iclass 32, count 0 2006.173.10:08:56.52#ibcon#about to write, iclass 32, count 0 2006.173.10:08:56.52#ibcon#wrote, iclass 32, count 0 2006.173.10:08:56.52#ibcon#about to read 3, iclass 32, count 0 2006.173.10:08:56.55#ibcon#read 3, iclass 32, count 0 2006.173.10:08:56.55#ibcon#about to read 4, iclass 32, count 0 2006.173.10:08:56.55#ibcon#read 4, iclass 32, count 0 2006.173.10:08:56.55#ibcon#about to read 5, iclass 32, count 0 2006.173.10:08:56.55#ibcon#read 5, iclass 32, count 0 2006.173.10:08:56.55#ibcon#about to read 6, iclass 32, count 0 2006.173.10:08:56.55#ibcon#read 6, iclass 32, count 0 2006.173.10:08:56.55#ibcon#end of sib2, iclass 32, count 0 2006.173.10:08:56.55#ibcon#*after write, iclass 32, count 0 2006.173.10:08:56.55#ibcon#*before return 0, iclass 32, count 0 2006.173.10:08:56.55#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.10:08:56.55#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.173.10:08:56.55#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.10:08:56.55#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.10:08:56.55$vck44/valo=8,884.99 2006.173.10:08:56.55#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.10:08:56.55#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.10:08:56.55#ibcon#ireg 17 cls_cnt 0 2006.173.10:08:56.55#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.10:08:56.55#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.10:08:56.55#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.10:08:56.55#ibcon#enter wrdev, iclass 34, count 0 2006.173.10:08:56.55#ibcon#first serial, iclass 34, count 0 2006.173.10:08:56.55#ibcon#enter sib2, iclass 34, count 0 2006.173.10:08:56.55#ibcon#flushed, iclass 34, count 0 2006.173.10:08:56.55#ibcon#about to write, iclass 34, count 0 2006.173.10:08:56.55#ibcon#wrote, iclass 34, count 0 2006.173.10:08:56.55#ibcon#about to read 3, iclass 34, count 0 2006.173.10:08:56.57#ibcon#read 3, iclass 34, count 0 2006.173.10:08:56.57#ibcon#about to read 4, iclass 34, count 0 2006.173.10:08:56.57#ibcon#read 4, iclass 34, count 0 2006.173.10:08:56.57#ibcon#about to read 5, iclass 34, count 0 2006.173.10:08:56.57#ibcon#read 5, iclass 34, count 0 2006.173.10:08:56.57#ibcon#about to read 6, iclass 34, count 0 2006.173.10:08:56.57#ibcon#read 6, iclass 34, count 0 2006.173.10:08:56.57#ibcon#end of sib2, iclass 34, count 0 2006.173.10:08:56.57#ibcon#*mode == 0, iclass 34, count 0 2006.173.10:08:56.57#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.10:08:56.57#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.10:08:56.57#ibcon#*before write, iclass 34, count 0 2006.173.10:08:56.57#ibcon#enter sib2, iclass 34, count 0 2006.173.10:08:56.57#ibcon#flushed, iclass 34, count 0 2006.173.10:08:56.57#ibcon#about to write, iclass 34, count 0 2006.173.10:08:56.57#ibcon#wrote, iclass 34, count 0 2006.173.10:08:56.57#ibcon#about to read 3, iclass 34, count 0 2006.173.10:08:56.61#ibcon#read 3, iclass 34, count 0 2006.173.10:08:56.61#ibcon#about to read 4, iclass 34, count 0 2006.173.10:08:56.61#ibcon#read 4, iclass 34, count 0 2006.173.10:08:56.61#ibcon#about to read 5, iclass 34, count 0 2006.173.10:08:56.61#ibcon#read 5, iclass 34, count 0 2006.173.10:08:56.61#ibcon#about to read 6, iclass 34, count 0 2006.173.10:08:56.61#ibcon#read 6, iclass 34, count 0 2006.173.10:08:56.61#ibcon#end of sib2, iclass 34, count 0 2006.173.10:08:56.61#ibcon#*after write, iclass 34, count 0 2006.173.10:08:56.61#ibcon#*before return 0, iclass 34, count 0 2006.173.10:08:56.61#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.10:08:56.61#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.10:08:56.61#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.10:08:56.61#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.10:08:56.61$vck44/va=8,4 2006.173.10:08:56.61#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.10:08:56.61#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.10:08:56.61#ibcon#ireg 11 cls_cnt 2 2006.173.10:08:56.61#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.10:08:56.67#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.10:08:56.67#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.10:08:56.67#ibcon#enter wrdev, iclass 36, count 2 2006.173.10:08:56.67#ibcon#first serial, iclass 36, count 2 2006.173.10:08:56.67#ibcon#enter sib2, iclass 36, count 2 2006.173.10:08:56.67#ibcon#flushed, iclass 36, count 2 2006.173.10:08:56.67#ibcon#about to write, iclass 36, count 2 2006.173.10:08:56.67#ibcon#wrote, iclass 36, count 2 2006.173.10:08:56.67#ibcon#about to read 3, iclass 36, count 2 2006.173.10:08:56.69#ibcon#read 3, iclass 36, count 2 2006.173.10:08:56.69#ibcon#about to read 4, iclass 36, count 2 2006.173.10:08:56.69#ibcon#read 4, iclass 36, count 2 2006.173.10:08:56.69#ibcon#about to read 5, iclass 36, count 2 2006.173.10:08:56.69#ibcon#read 5, iclass 36, count 2 2006.173.10:08:56.69#ibcon#about to read 6, iclass 36, count 2 2006.173.10:08:56.69#ibcon#read 6, iclass 36, count 2 2006.173.10:08:56.69#ibcon#end of sib2, iclass 36, count 2 2006.173.10:08:56.69#ibcon#*mode == 0, iclass 36, count 2 2006.173.10:08:56.69#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.10:08:56.69#ibcon#[25=AT08-04\r\n] 2006.173.10:08:56.69#ibcon#*before write, iclass 36, count 2 2006.173.10:08:56.69#ibcon#enter sib2, iclass 36, count 2 2006.173.10:08:56.69#ibcon#flushed, iclass 36, count 2 2006.173.10:08:56.69#ibcon#about to write, iclass 36, count 2 2006.173.10:08:56.69#ibcon#wrote, iclass 36, count 2 2006.173.10:08:56.69#ibcon#about to read 3, iclass 36, count 2 2006.173.10:08:56.72#ibcon#read 3, iclass 36, count 2 2006.173.10:08:56.72#ibcon#about to read 4, iclass 36, count 2 2006.173.10:08:56.72#ibcon#read 4, iclass 36, count 2 2006.173.10:08:56.72#ibcon#about to read 5, iclass 36, count 2 2006.173.10:08:56.72#ibcon#read 5, iclass 36, count 2 2006.173.10:08:56.72#ibcon#about to read 6, iclass 36, count 2 2006.173.10:08:56.72#ibcon#read 6, iclass 36, count 2 2006.173.10:08:56.72#ibcon#end of sib2, iclass 36, count 2 2006.173.10:08:56.72#ibcon#*after write, iclass 36, count 2 2006.173.10:08:56.72#ibcon#*before return 0, iclass 36, count 2 2006.173.10:08:56.72#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.10:08:56.72#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.10:08:56.72#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.10:08:56.72#ibcon#ireg 7 cls_cnt 0 2006.173.10:08:56.72#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.10:08:56.84#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.10:08:56.84#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.10:08:56.84#ibcon#enter wrdev, iclass 36, count 0 2006.173.10:08:56.84#ibcon#first serial, iclass 36, count 0 2006.173.10:08:56.84#ibcon#enter sib2, iclass 36, count 0 2006.173.10:08:56.84#ibcon#flushed, iclass 36, count 0 2006.173.10:08:56.84#ibcon#about to write, iclass 36, count 0 2006.173.10:08:56.84#ibcon#wrote, iclass 36, count 0 2006.173.10:08:56.84#ibcon#about to read 3, iclass 36, count 0 2006.173.10:08:56.86#ibcon#read 3, iclass 36, count 0 2006.173.10:08:56.86#ibcon#about to read 4, iclass 36, count 0 2006.173.10:08:56.86#ibcon#read 4, iclass 36, count 0 2006.173.10:08:56.86#ibcon#about to read 5, iclass 36, count 0 2006.173.10:08:56.86#ibcon#read 5, iclass 36, count 0 2006.173.10:08:56.86#ibcon#about to read 6, iclass 36, count 0 2006.173.10:08:56.86#ibcon#read 6, iclass 36, count 0 2006.173.10:08:56.86#ibcon#end of sib2, iclass 36, count 0 2006.173.10:08:56.86#ibcon#*mode == 0, iclass 36, count 0 2006.173.10:08:56.86#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.10:08:56.86#ibcon#[25=USB\r\n] 2006.173.10:08:56.86#ibcon#*before write, iclass 36, count 0 2006.173.10:08:56.86#ibcon#enter sib2, iclass 36, count 0 2006.173.10:08:56.86#ibcon#flushed, iclass 36, count 0 2006.173.10:08:56.86#ibcon#about to write, iclass 36, count 0 2006.173.10:08:56.86#ibcon#wrote, iclass 36, count 0 2006.173.10:08:56.86#ibcon#about to read 3, iclass 36, count 0 2006.173.10:08:56.89#ibcon#read 3, iclass 36, count 0 2006.173.10:08:56.89#ibcon#about to read 4, iclass 36, count 0 2006.173.10:08:56.89#ibcon#read 4, iclass 36, count 0 2006.173.10:08:56.89#ibcon#about to read 5, iclass 36, count 0 2006.173.10:08:56.89#ibcon#read 5, iclass 36, count 0 2006.173.10:08:56.89#ibcon#about to read 6, iclass 36, count 0 2006.173.10:08:56.89#ibcon#read 6, iclass 36, count 0 2006.173.10:08:56.89#ibcon#end of sib2, iclass 36, count 0 2006.173.10:08:56.89#ibcon#*after write, iclass 36, count 0 2006.173.10:08:56.89#ibcon#*before return 0, iclass 36, count 0 2006.173.10:08:56.89#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.10:08:56.89#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.10:08:56.89#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.10:08:56.89#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.10:08:56.89$vck44/vblo=1,629.99 2006.173.10:08:56.89#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.10:08:56.89#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.10:08:56.89#ibcon#ireg 17 cls_cnt 0 2006.173.10:08:56.89#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.10:08:56.89#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.10:08:56.89#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.10:08:56.89#ibcon#enter wrdev, iclass 38, count 0 2006.173.10:08:56.89#ibcon#first serial, iclass 38, count 0 2006.173.10:08:56.89#ibcon#enter sib2, iclass 38, count 0 2006.173.10:08:56.89#ibcon#flushed, iclass 38, count 0 2006.173.10:08:56.89#ibcon#about to write, iclass 38, count 0 2006.173.10:08:56.89#ibcon#wrote, iclass 38, count 0 2006.173.10:08:56.89#ibcon#about to read 3, iclass 38, count 0 2006.173.10:08:56.91#ibcon#read 3, iclass 38, count 0 2006.173.10:08:56.91#ibcon#about to read 4, iclass 38, count 0 2006.173.10:08:56.91#ibcon#read 4, iclass 38, count 0 2006.173.10:08:56.91#ibcon#about to read 5, iclass 38, count 0 2006.173.10:08:56.91#ibcon#read 5, iclass 38, count 0 2006.173.10:08:56.91#ibcon#about to read 6, iclass 38, count 0 2006.173.10:08:56.91#ibcon#read 6, iclass 38, count 0 2006.173.10:08:56.91#ibcon#end of sib2, iclass 38, count 0 2006.173.10:08:56.91#ibcon#*mode == 0, iclass 38, count 0 2006.173.10:08:56.91#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.10:08:56.91#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.10:08:56.91#ibcon#*before write, iclass 38, count 0 2006.173.10:08:56.91#ibcon#enter sib2, iclass 38, count 0 2006.173.10:08:56.91#ibcon#flushed, iclass 38, count 0 2006.173.10:08:56.91#ibcon#about to write, iclass 38, count 0 2006.173.10:08:56.91#ibcon#wrote, iclass 38, count 0 2006.173.10:08:56.91#ibcon#about to read 3, iclass 38, count 0 2006.173.10:08:56.95#ibcon#read 3, iclass 38, count 0 2006.173.10:08:56.95#ibcon#about to read 4, iclass 38, count 0 2006.173.10:08:56.95#ibcon#read 4, iclass 38, count 0 2006.173.10:08:56.95#ibcon#about to read 5, iclass 38, count 0 2006.173.10:08:56.95#ibcon#read 5, iclass 38, count 0 2006.173.10:08:56.95#ibcon#about to read 6, iclass 38, count 0 2006.173.10:08:56.95#ibcon#read 6, iclass 38, count 0 2006.173.10:08:56.95#ibcon#end of sib2, iclass 38, count 0 2006.173.10:08:56.95#ibcon#*after write, iclass 38, count 0 2006.173.10:08:56.95#ibcon#*before return 0, iclass 38, count 0 2006.173.10:08:56.95#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.10:08:56.95#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.10:08:56.95#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.10:08:56.95#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.10:08:56.95$vck44/vb=1,4 2006.173.10:08:56.95#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.10:08:56.95#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.10:08:56.95#ibcon#ireg 11 cls_cnt 2 2006.173.10:08:56.95#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.10:08:56.95#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.10:08:56.95#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.10:08:56.95#ibcon#enter wrdev, iclass 40, count 2 2006.173.10:08:56.95#ibcon#first serial, iclass 40, count 2 2006.173.10:08:56.95#ibcon#enter sib2, iclass 40, count 2 2006.173.10:08:56.95#ibcon#flushed, iclass 40, count 2 2006.173.10:08:56.95#ibcon#about to write, iclass 40, count 2 2006.173.10:08:56.95#ibcon#wrote, iclass 40, count 2 2006.173.10:08:56.95#ibcon#about to read 3, iclass 40, count 2 2006.173.10:08:56.97#ibcon#read 3, iclass 40, count 2 2006.173.10:08:56.97#ibcon#about to read 4, iclass 40, count 2 2006.173.10:08:56.97#ibcon#read 4, iclass 40, count 2 2006.173.10:08:56.97#ibcon#about to read 5, iclass 40, count 2 2006.173.10:08:56.97#ibcon#read 5, iclass 40, count 2 2006.173.10:08:56.97#ibcon#about to read 6, iclass 40, count 2 2006.173.10:08:56.97#ibcon#read 6, iclass 40, count 2 2006.173.10:08:56.97#ibcon#end of sib2, iclass 40, count 2 2006.173.10:08:56.97#ibcon#*mode == 0, iclass 40, count 2 2006.173.10:08:56.97#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.10:08:56.97#ibcon#[27=AT01-04\r\n] 2006.173.10:08:56.97#ibcon#*before write, iclass 40, count 2 2006.173.10:08:56.97#ibcon#enter sib2, iclass 40, count 2 2006.173.10:08:56.97#ibcon#flushed, iclass 40, count 2 2006.173.10:08:56.97#ibcon#about to write, iclass 40, count 2 2006.173.10:08:56.97#ibcon#wrote, iclass 40, count 2 2006.173.10:08:56.97#ibcon#about to read 3, iclass 40, count 2 2006.173.10:08:57.00#ibcon#read 3, iclass 40, count 2 2006.173.10:08:57.00#ibcon#about to read 4, iclass 40, count 2 2006.173.10:08:57.00#ibcon#read 4, iclass 40, count 2 2006.173.10:08:57.00#ibcon#about to read 5, iclass 40, count 2 2006.173.10:08:57.00#ibcon#read 5, iclass 40, count 2 2006.173.10:08:57.00#ibcon#about to read 6, iclass 40, count 2 2006.173.10:08:57.00#ibcon#read 6, iclass 40, count 2 2006.173.10:08:57.00#ibcon#end of sib2, iclass 40, count 2 2006.173.10:08:57.00#ibcon#*after write, iclass 40, count 2 2006.173.10:08:57.00#ibcon#*before return 0, iclass 40, count 2 2006.173.10:08:57.00#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.10:08:57.00#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.10:08:57.00#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.10:08:57.00#ibcon#ireg 7 cls_cnt 0 2006.173.10:08:57.00#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.10:08:57.12#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.10:08:57.12#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.10:08:57.12#ibcon#enter wrdev, iclass 40, count 0 2006.173.10:08:57.12#ibcon#first serial, iclass 40, count 0 2006.173.10:08:57.12#ibcon#enter sib2, iclass 40, count 0 2006.173.10:08:57.12#ibcon#flushed, iclass 40, count 0 2006.173.10:08:57.12#ibcon#about to write, iclass 40, count 0 2006.173.10:08:57.12#ibcon#wrote, iclass 40, count 0 2006.173.10:08:57.12#ibcon#about to read 3, iclass 40, count 0 2006.173.10:08:57.14#ibcon#read 3, iclass 40, count 0 2006.173.10:08:57.14#ibcon#about to read 4, iclass 40, count 0 2006.173.10:08:57.14#ibcon#read 4, iclass 40, count 0 2006.173.10:08:57.14#ibcon#about to read 5, iclass 40, count 0 2006.173.10:08:57.14#ibcon#read 5, iclass 40, count 0 2006.173.10:08:57.14#ibcon#about to read 6, iclass 40, count 0 2006.173.10:08:57.14#ibcon#read 6, iclass 40, count 0 2006.173.10:08:57.14#ibcon#end of sib2, iclass 40, count 0 2006.173.10:08:57.14#ibcon#*mode == 0, iclass 40, count 0 2006.173.10:08:57.14#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.10:08:57.14#ibcon#[27=USB\r\n] 2006.173.10:08:57.14#ibcon#*before write, iclass 40, count 0 2006.173.10:08:57.14#ibcon#enter sib2, iclass 40, count 0 2006.173.10:08:57.14#ibcon#flushed, iclass 40, count 0 2006.173.10:08:57.14#ibcon#about to write, iclass 40, count 0 2006.173.10:08:57.14#ibcon#wrote, iclass 40, count 0 2006.173.10:08:57.14#ibcon#about to read 3, iclass 40, count 0 2006.173.10:08:57.17#ibcon#read 3, iclass 40, count 0 2006.173.10:08:57.17#ibcon#about to read 4, iclass 40, count 0 2006.173.10:08:57.17#ibcon#read 4, iclass 40, count 0 2006.173.10:08:57.17#ibcon#about to read 5, iclass 40, count 0 2006.173.10:08:57.17#ibcon#read 5, iclass 40, count 0 2006.173.10:08:57.17#ibcon#about to read 6, iclass 40, count 0 2006.173.10:08:57.17#ibcon#read 6, iclass 40, count 0 2006.173.10:08:57.17#ibcon#end of sib2, iclass 40, count 0 2006.173.10:08:57.17#ibcon#*after write, iclass 40, count 0 2006.173.10:08:57.17#ibcon#*before return 0, iclass 40, count 0 2006.173.10:08:57.17#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.10:08:57.17#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.10:08:57.17#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.10:08:57.17#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.10:08:57.17$vck44/vblo=2,634.99 2006.173.10:08:57.17#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.10:08:57.17#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.10:08:57.17#ibcon#ireg 17 cls_cnt 0 2006.173.10:08:57.17#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.10:08:57.17#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.10:08:57.17#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.10:08:57.17#ibcon#enter wrdev, iclass 4, count 0 2006.173.10:08:57.17#ibcon#first serial, iclass 4, count 0 2006.173.10:08:57.17#ibcon#enter sib2, iclass 4, count 0 2006.173.10:08:57.17#ibcon#flushed, iclass 4, count 0 2006.173.10:08:57.17#ibcon#about to write, iclass 4, count 0 2006.173.10:08:57.17#ibcon#wrote, iclass 4, count 0 2006.173.10:08:57.17#ibcon#about to read 3, iclass 4, count 0 2006.173.10:08:57.19#ibcon#read 3, iclass 4, count 0 2006.173.10:08:57.19#ibcon#about to read 4, iclass 4, count 0 2006.173.10:08:57.19#ibcon#read 4, iclass 4, count 0 2006.173.10:08:57.19#ibcon#about to read 5, iclass 4, count 0 2006.173.10:08:57.19#ibcon#read 5, iclass 4, count 0 2006.173.10:08:57.19#ibcon#about to read 6, iclass 4, count 0 2006.173.10:08:57.19#ibcon#read 6, iclass 4, count 0 2006.173.10:08:57.19#ibcon#end of sib2, iclass 4, count 0 2006.173.10:08:57.19#ibcon#*mode == 0, iclass 4, count 0 2006.173.10:08:57.19#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.10:08:57.19#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.10:08:57.19#ibcon#*before write, iclass 4, count 0 2006.173.10:08:57.19#ibcon#enter sib2, iclass 4, count 0 2006.173.10:08:57.19#ibcon#flushed, iclass 4, count 0 2006.173.10:08:57.19#ibcon#about to write, iclass 4, count 0 2006.173.10:08:57.19#ibcon#wrote, iclass 4, count 0 2006.173.10:08:57.19#ibcon#about to read 3, iclass 4, count 0 2006.173.10:08:57.23#ibcon#read 3, iclass 4, count 0 2006.173.10:08:57.23#ibcon#about to read 4, iclass 4, count 0 2006.173.10:08:57.23#ibcon#read 4, iclass 4, count 0 2006.173.10:08:57.23#ibcon#about to read 5, iclass 4, count 0 2006.173.10:08:57.23#ibcon#read 5, iclass 4, count 0 2006.173.10:08:57.23#ibcon#about to read 6, iclass 4, count 0 2006.173.10:08:57.23#ibcon#read 6, iclass 4, count 0 2006.173.10:08:57.23#ibcon#end of sib2, iclass 4, count 0 2006.173.10:08:57.23#ibcon#*after write, iclass 4, count 0 2006.173.10:08:57.23#ibcon#*before return 0, iclass 4, count 0 2006.173.10:08:57.23#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.10:08:57.23#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.10:08:57.23#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.10:08:57.23#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.10:08:57.23$vck44/vb=2,4 2006.173.10:08:57.23#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.10:08:57.23#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.10:08:57.23#ibcon#ireg 11 cls_cnt 2 2006.173.10:08:57.23#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.10:08:57.29#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.10:08:57.29#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.10:08:57.29#ibcon#enter wrdev, iclass 6, count 2 2006.173.10:08:57.29#ibcon#first serial, iclass 6, count 2 2006.173.10:08:57.29#ibcon#enter sib2, iclass 6, count 2 2006.173.10:08:57.29#ibcon#flushed, iclass 6, count 2 2006.173.10:08:57.29#ibcon#about to write, iclass 6, count 2 2006.173.10:08:57.29#ibcon#wrote, iclass 6, count 2 2006.173.10:08:57.29#ibcon#about to read 3, iclass 6, count 2 2006.173.10:08:57.31#ibcon#read 3, iclass 6, count 2 2006.173.10:08:57.31#ibcon#about to read 4, iclass 6, count 2 2006.173.10:08:57.31#ibcon#read 4, iclass 6, count 2 2006.173.10:08:57.31#ibcon#about to read 5, iclass 6, count 2 2006.173.10:08:57.31#ibcon#read 5, iclass 6, count 2 2006.173.10:08:57.31#ibcon#about to read 6, iclass 6, count 2 2006.173.10:08:57.31#ibcon#read 6, iclass 6, count 2 2006.173.10:08:57.31#ibcon#end of sib2, iclass 6, count 2 2006.173.10:08:57.31#ibcon#*mode == 0, iclass 6, count 2 2006.173.10:08:57.31#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.10:08:57.31#ibcon#[27=AT02-04\r\n] 2006.173.10:08:57.31#ibcon#*before write, iclass 6, count 2 2006.173.10:08:57.31#ibcon#enter sib2, iclass 6, count 2 2006.173.10:08:57.31#ibcon#flushed, iclass 6, count 2 2006.173.10:08:57.31#ibcon#about to write, iclass 6, count 2 2006.173.10:08:57.31#ibcon#wrote, iclass 6, count 2 2006.173.10:08:57.31#ibcon#about to read 3, iclass 6, count 2 2006.173.10:08:57.34#ibcon#read 3, iclass 6, count 2 2006.173.10:08:57.34#ibcon#about to read 4, iclass 6, count 2 2006.173.10:08:57.34#ibcon#read 4, iclass 6, count 2 2006.173.10:08:57.34#ibcon#about to read 5, iclass 6, count 2 2006.173.10:08:57.34#ibcon#read 5, iclass 6, count 2 2006.173.10:08:57.34#ibcon#about to read 6, iclass 6, count 2 2006.173.10:08:57.34#ibcon#read 6, iclass 6, count 2 2006.173.10:08:57.34#ibcon#end of sib2, iclass 6, count 2 2006.173.10:08:57.34#ibcon#*after write, iclass 6, count 2 2006.173.10:08:57.34#ibcon#*before return 0, iclass 6, count 2 2006.173.10:08:57.34#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.10:08:57.34#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.10:08:57.34#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.10:08:57.34#ibcon#ireg 7 cls_cnt 0 2006.173.10:08:57.34#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.10:08:57.46#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.10:08:57.46#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.10:08:57.46#ibcon#enter wrdev, iclass 6, count 0 2006.173.10:08:57.46#ibcon#first serial, iclass 6, count 0 2006.173.10:08:57.46#ibcon#enter sib2, iclass 6, count 0 2006.173.10:08:57.46#ibcon#flushed, iclass 6, count 0 2006.173.10:08:57.46#ibcon#about to write, iclass 6, count 0 2006.173.10:08:57.46#ibcon#wrote, iclass 6, count 0 2006.173.10:08:57.46#ibcon#about to read 3, iclass 6, count 0 2006.173.10:08:57.48#ibcon#read 3, iclass 6, count 0 2006.173.10:08:57.48#ibcon#about to read 4, iclass 6, count 0 2006.173.10:08:57.48#ibcon#read 4, iclass 6, count 0 2006.173.10:08:57.48#ibcon#about to read 5, iclass 6, count 0 2006.173.10:08:57.48#ibcon#read 5, iclass 6, count 0 2006.173.10:08:57.48#ibcon#about to read 6, iclass 6, count 0 2006.173.10:08:57.48#ibcon#read 6, iclass 6, count 0 2006.173.10:08:57.48#ibcon#end of sib2, iclass 6, count 0 2006.173.10:08:57.48#ibcon#*mode == 0, iclass 6, count 0 2006.173.10:08:57.48#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.10:08:57.48#ibcon#[27=USB\r\n] 2006.173.10:08:57.48#ibcon#*before write, iclass 6, count 0 2006.173.10:08:57.48#ibcon#enter sib2, iclass 6, count 0 2006.173.10:08:57.48#ibcon#flushed, iclass 6, count 0 2006.173.10:08:57.48#ibcon#about to write, iclass 6, count 0 2006.173.10:08:57.48#ibcon#wrote, iclass 6, count 0 2006.173.10:08:57.48#ibcon#about to read 3, iclass 6, count 0 2006.173.10:08:57.51#ibcon#read 3, iclass 6, count 0 2006.173.10:08:57.51#ibcon#about to read 4, iclass 6, count 0 2006.173.10:08:57.51#ibcon#read 4, iclass 6, count 0 2006.173.10:08:57.51#ibcon#about to read 5, iclass 6, count 0 2006.173.10:08:57.51#ibcon#read 5, iclass 6, count 0 2006.173.10:08:57.51#ibcon#about to read 6, iclass 6, count 0 2006.173.10:08:57.51#ibcon#read 6, iclass 6, count 0 2006.173.10:08:57.51#ibcon#end of sib2, iclass 6, count 0 2006.173.10:08:57.51#ibcon#*after write, iclass 6, count 0 2006.173.10:08:57.51#ibcon#*before return 0, iclass 6, count 0 2006.173.10:08:57.51#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.10:08:57.51#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.10:08:57.51#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.10:08:57.51#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.10:08:57.51$vck44/vblo=3,649.99 2006.173.10:08:57.51#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.10:08:57.51#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.10:08:57.51#ibcon#ireg 17 cls_cnt 0 2006.173.10:08:57.51#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.10:08:57.51#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.10:08:57.51#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.10:08:57.51#ibcon#enter wrdev, iclass 10, count 0 2006.173.10:08:57.51#ibcon#first serial, iclass 10, count 0 2006.173.10:08:57.51#ibcon#enter sib2, iclass 10, count 0 2006.173.10:08:57.51#ibcon#flushed, iclass 10, count 0 2006.173.10:08:57.51#ibcon#about to write, iclass 10, count 0 2006.173.10:08:57.51#ibcon#wrote, iclass 10, count 0 2006.173.10:08:57.51#ibcon#about to read 3, iclass 10, count 0 2006.173.10:08:57.53#ibcon#read 3, iclass 10, count 0 2006.173.10:08:57.53#ibcon#about to read 4, iclass 10, count 0 2006.173.10:08:57.53#ibcon#read 4, iclass 10, count 0 2006.173.10:08:57.53#ibcon#about to read 5, iclass 10, count 0 2006.173.10:08:57.53#ibcon#read 5, iclass 10, count 0 2006.173.10:08:57.53#ibcon#about to read 6, iclass 10, count 0 2006.173.10:08:57.53#ibcon#read 6, iclass 10, count 0 2006.173.10:08:57.53#ibcon#end of sib2, iclass 10, count 0 2006.173.10:08:57.53#ibcon#*mode == 0, iclass 10, count 0 2006.173.10:08:57.53#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.10:08:57.53#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.10:08:57.53#ibcon#*before write, iclass 10, count 0 2006.173.10:08:57.53#ibcon#enter sib2, iclass 10, count 0 2006.173.10:08:57.53#ibcon#flushed, iclass 10, count 0 2006.173.10:08:57.53#ibcon#about to write, iclass 10, count 0 2006.173.10:08:57.53#ibcon#wrote, iclass 10, count 0 2006.173.10:08:57.53#ibcon#about to read 3, iclass 10, count 0 2006.173.10:08:57.57#ibcon#read 3, iclass 10, count 0 2006.173.10:08:57.57#ibcon#about to read 4, iclass 10, count 0 2006.173.10:08:57.57#ibcon#read 4, iclass 10, count 0 2006.173.10:08:57.57#ibcon#about to read 5, iclass 10, count 0 2006.173.10:08:57.57#ibcon#read 5, iclass 10, count 0 2006.173.10:08:57.57#ibcon#about to read 6, iclass 10, count 0 2006.173.10:08:57.57#ibcon#read 6, iclass 10, count 0 2006.173.10:08:57.57#ibcon#end of sib2, iclass 10, count 0 2006.173.10:08:57.57#ibcon#*after write, iclass 10, count 0 2006.173.10:08:57.57#ibcon#*before return 0, iclass 10, count 0 2006.173.10:08:57.57#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.10:08:57.57#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.10:08:57.57#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.10:08:57.57#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.10:08:57.57$vck44/vb=3,4 2006.173.10:08:57.57#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.10:08:57.57#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.10:08:57.57#ibcon#ireg 11 cls_cnt 2 2006.173.10:08:57.57#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.10:08:57.63#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.10:08:57.63#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.10:08:57.63#ibcon#enter wrdev, iclass 12, count 2 2006.173.10:08:57.63#ibcon#first serial, iclass 12, count 2 2006.173.10:08:57.63#ibcon#enter sib2, iclass 12, count 2 2006.173.10:08:57.63#ibcon#flushed, iclass 12, count 2 2006.173.10:08:57.63#ibcon#about to write, iclass 12, count 2 2006.173.10:08:57.63#ibcon#wrote, iclass 12, count 2 2006.173.10:08:57.63#ibcon#about to read 3, iclass 12, count 2 2006.173.10:08:57.65#ibcon#read 3, iclass 12, count 2 2006.173.10:08:57.65#ibcon#about to read 4, iclass 12, count 2 2006.173.10:08:57.65#ibcon#read 4, iclass 12, count 2 2006.173.10:08:57.65#ibcon#about to read 5, iclass 12, count 2 2006.173.10:08:57.65#ibcon#read 5, iclass 12, count 2 2006.173.10:08:57.65#ibcon#about to read 6, iclass 12, count 2 2006.173.10:08:57.65#ibcon#read 6, iclass 12, count 2 2006.173.10:08:57.65#ibcon#end of sib2, iclass 12, count 2 2006.173.10:08:57.65#ibcon#*mode == 0, iclass 12, count 2 2006.173.10:08:57.65#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.10:08:57.65#ibcon#[27=AT03-04\r\n] 2006.173.10:08:57.65#ibcon#*before write, iclass 12, count 2 2006.173.10:08:57.65#ibcon#enter sib2, iclass 12, count 2 2006.173.10:08:57.65#ibcon#flushed, iclass 12, count 2 2006.173.10:08:57.65#ibcon#about to write, iclass 12, count 2 2006.173.10:08:57.65#ibcon#wrote, iclass 12, count 2 2006.173.10:08:57.65#ibcon#about to read 3, iclass 12, count 2 2006.173.10:08:57.68#ibcon#read 3, iclass 12, count 2 2006.173.10:08:57.68#ibcon#about to read 4, iclass 12, count 2 2006.173.10:08:57.68#ibcon#read 4, iclass 12, count 2 2006.173.10:08:57.68#ibcon#about to read 5, iclass 12, count 2 2006.173.10:08:57.68#ibcon#read 5, iclass 12, count 2 2006.173.10:08:57.68#ibcon#about to read 6, iclass 12, count 2 2006.173.10:08:57.68#ibcon#read 6, iclass 12, count 2 2006.173.10:08:57.68#ibcon#end of sib2, iclass 12, count 2 2006.173.10:08:57.68#ibcon#*after write, iclass 12, count 2 2006.173.10:08:57.68#ibcon#*before return 0, iclass 12, count 2 2006.173.10:08:57.68#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.10:08:57.68#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.10:08:57.68#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.10:08:57.68#ibcon#ireg 7 cls_cnt 0 2006.173.10:08:57.68#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.10:08:57.80#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.10:08:57.80#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.10:08:57.80#ibcon#enter wrdev, iclass 12, count 0 2006.173.10:08:57.80#ibcon#first serial, iclass 12, count 0 2006.173.10:08:57.80#ibcon#enter sib2, iclass 12, count 0 2006.173.10:08:57.80#ibcon#flushed, iclass 12, count 0 2006.173.10:08:57.80#ibcon#about to write, iclass 12, count 0 2006.173.10:08:57.80#ibcon#wrote, iclass 12, count 0 2006.173.10:08:57.80#ibcon#about to read 3, iclass 12, count 0 2006.173.10:08:57.82#ibcon#read 3, iclass 12, count 0 2006.173.10:08:57.82#ibcon#about to read 4, iclass 12, count 0 2006.173.10:08:57.82#ibcon#read 4, iclass 12, count 0 2006.173.10:08:57.82#ibcon#about to read 5, iclass 12, count 0 2006.173.10:08:57.82#ibcon#read 5, iclass 12, count 0 2006.173.10:08:57.82#ibcon#about to read 6, iclass 12, count 0 2006.173.10:08:57.82#ibcon#read 6, iclass 12, count 0 2006.173.10:08:57.82#ibcon#end of sib2, iclass 12, count 0 2006.173.10:08:57.82#ibcon#*mode == 0, iclass 12, count 0 2006.173.10:08:57.82#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.10:08:57.82#ibcon#[27=USB\r\n] 2006.173.10:08:57.82#ibcon#*before write, iclass 12, count 0 2006.173.10:08:57.82#ibcon#enter sib2, iclass 12, count 0 2006.173.10:08:57.82#ibcon#flushed, iclass 12, count 0 2006.173.10:08:57.82#ibcon#about to write, iclass 12, count 0 2006.173.10:08:57.82#ibcon#wrote, iclass 12, count 0 2006.173.10:08:57.82#ibcon#about to read 3, iclass 12, count 0 2006.173.10:08:57.85#ibcon#read 3, iclass 12, count 0 2006.173.10:08:57.85#ibcon#about to read 4, iclass 12, count 0 2006.173.10:08:57.85#ibcon#read 4, iclass 12, count 0 2006.173.10:08:57.85#ibcon#about to read 5, iclass 12, count 0 2006.173.10:08:57.85#ibcon#read 5, iclass 12, count 0 2006.173.10:08:57.85#ibcon#about to read 6, iclass 12, count 0 2006.173.10:08:57.85#ibcon#read 6, iclass 12, count 0 2006.173.10:08:57.85#ibcon#end of sib2, iclass 12, count 0 2006.173.10:08:57.85#ibcon#*after write, iclass 12, count 0 2006.173.10:08:57.85#ibcon#*before return 0, iclass 12, count 0 2006.173.10:08:57.85#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.10:08:57.85#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.10:08:57.85#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.10:08:57.85#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.10:08:57.85$vck44/vblo=4,679.99 2006.173.10:08:57.85#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.10:08:57.85#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.10:08:57.85#ibcon#ireg 17 cls_cnt 0 2006.173.10:08:57.85#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.10:08:57.85#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.10:08:57.85#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.10:08:57.85#ibcon#enter wrdev, iclass 14, count 0 2006.173.10:08:57.85#ibcon#first serial, iclass 14, count 0 2006.173.10:08:57.85#ibcon#enter sib2, iclass 14, count 0 2006.173.10:08:57.85#ibcon#flushed, iclass 14, count 0 2006.173.10:08:57.85#ibcon#about to write, iclass 14, count 0 2006.173.10:08:57.85#ibcon#wrote, iclass 14, count 0 2006.173.10:08:57.85#ibcon#about to read 3, iclass 14, count 0 2006.173.10:08:57.87#ibcon#read 3, iclass 14, count 0 2006.173.10:08:57.87#ibcon#about to read 4, iclass 14, count 0 2006.173.10:08:57.87#ibcon#read 4, iclass 14, count 0 2006.173.10:08:57.87#ibcon#about to read 5, iclass 14, count 0 2006.173.10:08:57.87#ibcon#read 5, iclass 14, count 0 2006.173.10:08:57.87#ibcon#about to read 6, iclass 14, count 0 2006.173.10:08:57.87#ibcon#read 6, iclass 14, count 0 2006.173.10:08:57.87#ibcon#end of sib2, iclass 14, count 0 2006.173.10:08:57.87#ibcon#*mode == 0, iclass 14, count 0 2006.173.10:08:57.87#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.10:08:57.87#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.10:08:57.87#ibcon#*before write, iclass 14, count 0 2006.173.10:08:57.87#ibcon#enter sib2, iclass 14, count 0 2006.173.10:08:57.87#ibcon#flushed, iclass 14, count 0 2006.173.10:08:57.87#ibcon#about to write, iclass 14, count 0 2006.173.10:08:57.87#ibcon#wrote, iclass 14, count 0 2006.173.10:08:57.87#ibcon#about to read 3, iclass 14, count 0 2006.173.10:08:57.91#ibcon#read 3, iclass 14, count 0 2006.173.10:08:57.91#ibcon#about to read 4, iclass 14, count 0 2006.173.10:08:57.91#ibcon#read 4, iclass 14, count 0 2006.173.10:08:57.91#ibcon#about to read 5, iclass 14, count 0 2006.173.10:08:57.91#ibcon#read 5, iclass 14, count 0 2006.173.10:08:57.91#ibcon#about to read 6, iclass 14, count 0 2006.173.10:08:57.91#ibcon#read 6, iclass 14, count 0 2006.173.10:08:57.91#ibcon#end of sib2, iclass 14, count 0 2006.173.10:08:57.91#ibcon#*after write, iclass 14, count 0 2006.173.10:08:57.91#ibcon#*before return 0, iclass 14, count 0 2006.173.10:08:57.91#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.10:08:57.91#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.10:08:57.91#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.10:08:57.91#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.10:08:57.91$vck44/vb=4,4 2006.173.10:08:57.91#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.10:08:57.91#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.10:08:57.91#ibcon#ireg 11 cls_cnt 2 2006.173.10:08:57.91#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.10:08:57.97#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.10:08:57.97#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.10:08:57.97#ibcon#enter wrdev, iclass 16, count 2 2006.173.10:08:57.97#ibcon#first serial, iclass 16, count 2 2006.173.10:08:57.97#ibcon#enter sib2, iclass 16, count 2 2006.173.10:08:57.97#ibcon#flushed, iclass 16, count 2 2006.173.10:08:57.97#ibcon#about to write, iclass 16, count 2 2006.173.10:08:57.97#ibcon#wrote, iclass 16, count 2 2006.173.10:08:57.97#ibcon#about to read 3, iclass 16, count 2 2006.173.10:08:57.99#ibcon#read 3, iclass 16, count 2 2006.173.10:08:57.99#ibcon#about to read 4, iclass 16, count 2 2006.173.10:08:57.99#ibcon#read 4, iclass 16, count 2 2006.173.10:08:57.99#ibcon#about to read 5, iclass 16, count 2 2006.173.10:08:57.99#ibcon#read 5, iclass 16, count 2 2006.173.10:08:57.99#ibcon#about to read 6, iclass 16, count 2 2006.173.10:08:57.99#ibcon#read 6, iclass 16, count 2 2006.173.10:08:57.99#ibcon#end of sib2, iclass 16, count 2 2006.173.10:08:57.99#ibcon#*mode == 0, iclass 16, count 2 2006.173.10:08:57.99#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.10:08:57.99#ibcon#[27=AT04-04\r\n] 2006.173.10:08:57.99#ibcon#*before write, iclass 16, count 2 2006.173.10:08:57.99#ibcon#enter sib2, iclass 16, count 2 2006.173.10:08:57.99#ibcon#flushed, iclass 16, count 2 2006.173.10:08:57.99#ibcon#about to write, iclass 16, count 2 2006.173.10:08:57.99#ibcon#wrote, iclass 16, count 2 2006.173.10:08:57.99#ibcon#about to read 3, iclass 16, count 2 2006.173.10:08:58.02#ibcon#read 3, iclass 16, count 2 2006.173.10:08:58.02#ibcon#about to read 4, iclass 16, count 2 2006.173.10:08:58.02#ibcon#read 4, iclass 16, count 2 2006.173.10:08:58.02#ibcon#about to read 5, iclass 16, count 2 2006.173.10:08:58.02#ibcon#read 5, iclass 16, count 2 2006.173.10:08:58.02#ibcon#about to read 6, iclass 16, count 2 2006.173.10:08:58.02#ibcon#read 6, iclass 16, count 2 2006.173.10:08:58.02#ibcon#end of sib2, iclass 16, count 2 2006.173.10:08:58.02#ibcon#*after write, iclass 16, count 2 2006.173.10:08:58.02#ibcon#*before return 0, iclass 16, count 2 2006.173.10:08:58.02#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.10:08:58.02#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.10:08:58.02#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.10:08:58.02#ibcon#ireg 7 cls_cnt 0 2006.173.10:08:58.02#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.10:08:58.14#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.10:08:58.14#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.10:08:58.14#ibcon#enter wrdev, iclass 16, count 0 2006.173.10:08:58.14#ibcon#first serial, iclass 16, count 0 2006.173.10:08:58.14#ibcon#enter sib2, iclass 16, count 0 2006.173.10:08:58.14#ibcon#flushed, iclass 16, count 0 2006.173.10:08:58.14#ibcon#about to write, iclass 16, count 0 2006.173.10:08:58.14#ibcon#wrote, iclass 16, count 0 2006.173.10:08:58.14#ibcon#about to read 3, iclass 16, count 0 2006.173.10:08:58.16#ibcon#read 3, iclass 16, count 0 2006.173.10:08:58.16#ibcon#about to read 4, iclass 16, count 0 2006.173.10:08:58.16#ibcon#read 4, iclass 16, count 0 2006.173.10:08:58.16#ibcon#about to read 5, iclass 16, count 0 2006.173.10:08:58.16#ibcon#read 5, iclass 16, count 0 2006.173.10:08:58.16#ibcon#about to read 6, iclass 16, count 0 2006.173.10:08:58.16#ibcon#read 6, iclass 16, count 0 2006.173.10:08:58.16#ibcon#end of sib2, iclass 16, count 0 2006.173.10:08:58.16#ibcon#*mode == 0, iclass 16, count 0 2006.173.10:08:58.16#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.10:08:58.16#ibcon#[27=USB\r\n] 2006.173.10:08:58.16#ibcon#*before write, iclass 16, count 0 2006.173.10:08:58.16#ibcon#enter sib2, iclass 16, count 0 2006.173.10:08:58.16#ibcon#flushed, iclass 16, count 0 2006.173.10:08:58.16#ibcon#about to write, iclass 16, count 0 2006.173.10:08:58.16#ibcon#wrote, iclass 16, count 0 2006.173.10:08:58.16#ibcon#about to read 3, iclass 16, count 0 2006.173.10:08:58.19#ibcon#read 3, iclass 16, count 0 2006.173.10:08:58.19#ibcon#about to read 4, iclass 16, count 0 2006.173.10:08:58.19#ibcon#read 4, iclass 16, count 0 2006.173.10:08:58.19#ibcon#about to read 5, iclass 16, count 0 2006.173.10:08:58.19#ibcon#read 5, iclass 16, count 0 2006.173.10:08:58.19#ibcon#about to read 6, iclass 16, count 0 2006.173.10:08:58.19#ibcon#read 6, iclass 16, count 0 2006.173.10:08:58.19#ibcon#end of sib2, iclass 16, count 0 2006.173.10:08:58.19#ibcon#*after write, iclass 16, count 0 2006.173.10:08:58.19#ibcon#*before return 0, iclass 16, count 0 2006.173.10:08:58.19#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.10:08:58.19#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.10:08:58.19#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.10:08:58.19#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.10:08:58.19$vck44/vblo=5,709.99 2006.173.10:08:58.19#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.10:08:58.19#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.10:08:58.19#ibcon#ireg 17 cls_cnt 0 2006.173.10:08:58.19#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.10:08:58.19#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.10:08:58.19#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.10:08:58.19#ibcon#enter wrdev, iclass 18, count 0 2006.173.10:08:58.19#ibcon#first serial, iclass 18, count 0 2006.173.10:08:58.19#ibcon#enter sib2, iclass 18, count 0 2006.173.10:08:58.19#ibcon#flushed, iclass 18, count 0 2006.173.10:08:58.19#ibcon#about to write, iclass 18, count 0 2006.173.10:08:58.19#ibcon#wrote, iclass 18, count 0 2006.173.10:08:58.19#ibcon#about to read 3, iclass 18, count 0 2006.173.10:08:58.21#ibcon#read 3, iclass 18, count 0 2006.173.10:08:58.21#ibcon#about to read 4, iclass 18, count 0 2006.173.10:08:58.21#ibcon#read 4, iclass 18, count 0 2006.173.10:08:58.21#ibcon#about to read 5, iclass 18, count 0 2006.173.10:08:58.21#ibcon#read 5, iclass 18, count 0 2006.173.10:08:58.21#ibcon#about to read 6, iclass 18, count 0 2006.173.10:08:58.21#ibcon#read 6, iclass 18, count 0 2006.173.10:08:58.21#ibcon#end of sib2, iclass 18, count 0 2006.173.10:08:58.21#ibcon#*mode == 0, iclass 18, count 0 2006.173.10:08:58.21#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.10:08:58.21#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.10:08:58.21#ibcon#*before write, iclass 18, count 0 2006.173.10:08:58.21#ibcon#enter sib2, iclass 18, count 0 2006.173.10:08:58.21#ibcon#flushed, iclass 18, count 0 2006.173.10:08:58.21#ibcon#about to write, iclass 18, count 0 2006.173.10:08:58.21#ibcon#wrote, iclass 18, count 0 2006.173.10:08:58.21#ibcon#about to read 3, iclass 18, count 0 2006.173.10:08:58.25#ibcon#read 3, iclass 18, count 0 2006.173.10:08:58.25#ibcon#about to read 4, iclass 18, count 0 2006.173.10:08:58.25#ibcon#read 4, iclass 18, count 0 2006.173.10:08:58.25#ibcon#about to read 5, iclass 18, count 0 2006.173.10:08:58.25#ibcon#read 5, iclass 18, count 0 2006.173.10:08:58.25#ibcon#about to read 6, iclass 18, count 0 2006.173.10:08:58.25#ibcon#read 6, iclass 18, count 0 2006.173.10:08:58.25#ibcon#end of sib2, iclass 18, count 0 2006.173.10:08:58.25#ibcon#*after write, iclass 18, count 0 2006.173.10:08:58.25#ibcon#*before return 0, iclass 18, count 0 2006.173.10:08:58.25#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.10:08:58.25#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.10:08:58.25#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.10:08:58.25#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.10:08:58.25$vck44/vb=5,4 2006.173.10:08:58.25#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.10:08:58.25#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.10:08:58.25#ibcon#ireg 11 cls_cnt 2 2006.173.10:08:58.25#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.10:08:58.31#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.10:08:58.31#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.10:08:58.31#ibcon#enter wrdev, iclass 20, count 2 2006.173.10:08:58.31#ibcon#first serial, iclass 20, count 2 2006.173.10:08:58.31#ibcon#enter sib2, iclass 20, count 2 2006.173.10:08:58.31#ibcon#flushed, iclass 20, count 2 2006.173.10:08:58.31#ibcon#about to write, iclass 20, count 2 2006.173.10:08:58.31#ibcon#wrote, iclass 20, count 2 2006.173.10:08:58.31#ibcon#about to read 3, iclass 20, count 2 2006.173.10:08:58.33#ibcon#read 3, iclass 20, count 2 2006.173.10:08:58.33#ibcon#about to read 4, iclass 20, count 2 2006.173.10:08:58.33#ibcon#read 4, iclass 20, count 2 2006.173.10:08:58.33#ibcon#about to read 5, iclass 20, count 2 2006.173.10:08:58.33#ibcon#read 5, iclass 20, count 2 2006.173.10:08:58.33#ibcon#about to read 6, iclass 20, count 2 2006.173.10:08:58.33#ibcon#read 6, iclass 20, count 2 2006.173.10:08:58.33#ibcon#end of sib2, iclass 20, count 2 2006.173.10:08:58.33#ibcon#*mode == 0, iclass 20, count 2 2006.173.10:08:58.33#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.10:08:58.33#ibcon#[27=AT05-04\r\n] 2006.173.10:08:58.33#ibcon#*before write, iclass 20, count 2 2006.173.10:08:58.33#ibcon#enter sib2, iclass 20, count 2 2006.173.10:08:58.33#ibcon#flushed, iclass 20, count 2 2006.173.10:08:58.33#ibcon#about to write, iclass 20, count 2 2006.173.10:08:58.33#ibcon#wrote, iclass 20, count 2 2006.173.10:08:58.33#ibcon#about to read 3, iclass 20, count 2 2006.173.10:08:58.36#ibcon#read 3, iclass 20, count 2 2006.173.10:08:58.36#ibcon#about to read 4, iclass 20, count 2 2006.173.10:08:58.36#ibcon#read 4, iclass 20, count 2 2006.173.10:08:58.36#ibcon#about to read 5, iclass 20, count 2 2006.173.10:08:58.36#ibcon#read 5, iclass 20, count 2 2006.173.10:08:58.36#ibcon#about to read 6, iclass 20, count 2 2006.173.10:08:58.36#ibcon#read 6, iclass 20, count 2 2006.173.10:08:58.36#ibcon#end of sib2, iclass 20, count 2 2006.173.10:08:58.36#ibcon#*after write, iclass 20, count 2 2006.173.10:08:58.36#ibcon#*before return 0, iclass 20, count 2 2006.173.10:08:58.36#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.10:08:58.36#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.10:08:58.36#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.10:08:58.36#ibcon#ireg 7 cls_cnt 0 2006.173.10:08:58.36#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.10:08:58.48#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.10:08:58.48#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.10:08:58.48#ibcon#enter wrdev, iclass 20, count 0 2006.173.10:08:58.48#ibcon#first serial, iclass 20, count 0 2006.173.10:08:58.48#ibcon#enter sib2, iclass 20, count 0 2006.173.10:08:58.48#ibcon#flushed, iclass 20, count 0 2006.173.10:08:58.48#ibcon#about to write, iclass 20, count 0 2006.173.10:08:58.48#ibcon#wrote, iclass 20, count 0 2006.173.10:08:58.48#ibcon#about to read 3, iclass 20, count 0 2006.173.10:08:58.50#ibcon#read 3, iclass 20, count 0 2006.173.10:08:58.50#ibcon#about to read 4, iclass 20, count 0 2006.173.10:08:58.50#ibcon#read 4, iclass 20, count 0 2006.173.10:08:58.50#ibcon#about to read 5, iclass 20, count 0 2006.173.10:08:58.50#ibcon#read 5, iclass 20, count 0 2006.173.10:08:58.50#ibcon#about to read 6, iclass 20, count 0 2006.173.10:08:58.50#ibcon#read 6, iclass 20, count 0 2006.173.10:08:58.50#ibcon#end of sib2, iclass 20, count 0 2006.173.10:08:58.50#ibcon#*mode == 0, iclass 20, count 0 2006.173.10:08:58.50#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.10:08:58.50#ibcon#[27=USB\r\n] 2006.173.10:08:58.50#ibcon#*before write, iclass 20, count 0 2006.173.10:08:58.50#ibcon#enter sib2, iclass 20, count 0 2006.173.10:08:58.50#ibcon#flushed, iclass 20, count 0 2006.173.10:08:58.50#ibcon#about to write, iclass 20, count 0 2006.173.10:08:58.50#ibcon#wrote, iclass 20, count 0 2006.173.10:08:58.50#ibcon#about to read 3, iclass 20, count 0 2006.173.10:08:58.53#ibcon#read 3, iclass 20, count 0 2006.173.10:08:58.53#ibcon#about to read 4, iclass 20, count 0 2006.173.10:08:58.53#ibcon#read 4, iclass 20, count 0 2006.173.10:08:58.53#ibcon#about to read 5, iclass 20, count 0 2006.173.10:08:58.53#ibcon#read 5, iclass 20, count 0 2006.173.10:08:58.53#ibcon#about to read 6, iclass 20, count 0 2006.173.10:08:58.53#ibcon#read 6, iclass 20, count 0 2006.173.10:08:58.53#ibcon#end of sib2, iclass 20, count 0 2006.173.10:08:58.53#ibcon#*after write, iclass 20, count 0 2006.173.10:08:58.53#ibcon#*before return 0, iclass 20, count 0 2006.173.10:08:58.53#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.10:08:58.53#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.10:08:58.53#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.10:08:58.53#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.10:08:58.53$vck44/vblo=6,719.99 2006.173.10:08:58.53#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.10:08:58.53#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.10:08:58.53#ibcon#ireg 17 cls_cnt 0 2006.173.10:08:58.53#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.10:08:58.53#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.10:08:58.53#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.10:08:58.53#ibcon#enter wrdev, iclass 22, count 0 2006.173.10:08:58.53#ibcon#first serial, iclass 22, count 0 2006.173.10:08:58.53#ibcon#enter sib2, iclass 22, count 0 2006.173.10:08:58.53#ibcon#flushed, iclass 22, count 0 2006.173.10:08:58.53#ibcon#about to write, iclass 22, count 0 2006.173.10:08:58.53#ibcon#wrote, iclass 22, count 0 2006.173.10:08:58.53#ibcon#about to read 3, iclass 22, count 0 2006.173.10:08:58.55#ibcon#read 3, iclass 22, count 0 2006.173.10:08:58.55#ibcon#about to read 4, iclass 22, count 0 2006.173.10:08:58.55#ibcon#read 4, iclass 22, count 0 2006.173.10:08:58.55#ibcon#about to read 5, iclass 22, count 0 2006.173.10:08:58.55#ibcon#read 5, iclass 22, count 0 2006.173.10:08:58.55#ibcon#about to read 6, iclass 22, count 0 2006.173.10:08:58.55#ibcon#read 6, iclass 22, count 0 2006.173.10:08:58.55#ibcon#end of sib2, iclass 22, count 0 2006.173.10:08:58.55#ibcon#*mode == 0, iclass 22, count 0 2006.173.10:08:58.55#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.10:08:58.55#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.10:08:58.55#ibcon#*before write, iclass 22, count 0 2006.173.10:08:58.55#ibcon#enter sib2, iclass 22, count 0 2006.173.10:08:58.55#ibcon#flushed, iclass 22, count 0 2006.173.10:08:58.55#ibcon#about to write, iclass 22, count 0 2006.173.10:08:58.55#ibcon#wrote, iclass 22, count 0 2006.173.10:08:58.55#ibcon#about to read 3, iclass 22, count 0 2006.173.10:08:58.59#ibcon#read 3, iclass 22, count 0 2006.173.10:08:58.59#ibcon#about to read 4, iclass 22, count 0 2006.173.10:08:58.59#ibcon#read 4, iclass 22, count 0 2006.173.10:08:58.59#ibcon#about to read 5, iclass 22, count 0 2006.173.10:08:58.59#ibcon#read 5, iclass 22, count 0 2006.173.10:08:58.59#ibcon#about to read 6, iclass 22, count 0 2006.173.10:08:58.59#ibcon#read 6, iclass 22, count 0 2006.173.10:08:58.59#ibcon#end of sib2, iclass 22, count 0 2006.173.10:08:58.59#ibcon#*after write, iclass 22, count 0 2006.173.10:08:58.59#ibcon#*before return 0, iclass 22, count 0 2006.173.10:08:58.59#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.10:08:58.59#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.10:08:58.59#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.10:08:58.59#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.10:08:58.59$vck44/vb=6,4 2006.173.10:08:58.59#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.10:08:58.59#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.10:08:58.59#ibcon#ireg 11 cls_cnt 2 2006.173.10:08:58.59#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.10:08:58.65#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.10:08:58.65#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.10:08:58.65#ibcon#enter wrdev, iclass 24, count 2 2006.173.10:08:58.65#ibcon#first serial, iclass 24, count 2 2006.173.10:08:58.65#ibcon#enter sib2, iclass 24, count 2 2006.173.10:08:58.65#ibcon#flushed, iclass 24, count 2 2006.173.10:08:58.65#ibcon#about to write, iclass 24, count 2 2006.173.10:08:58.65#ibcon#wrote, iclass 24, count 2 2006.173.10:08:58.65#ibcon#about to read 3, iclass 24, count 2 2006.173.10:08:58.67#ibcon#read 3, iclass 24, count 2 2006.173.10:08:58.67#ibcon#about to read 4, iclass 24, count 2 2006.173.10:08:58.67#ibcon#read 4, iclass 24, count 2 2006.173.10:08:58.67#ibcon#about to read 5, iclass 24, count 2 2006.173.10:08:58.67#ibcon#read 5, iclass 24, count 2 2006.173.10:08:58.67#ibcon#about to read 6, iclass 24, count 2 2006.173.10:08:58.67#ibcon#read 6, iclass 24, count 2 2006.173.10:08:58.67#ibcon#end of sib2, iclass 24, count 2 2006.173.10:08:58.67#ibcon#*mode == 0, iclass 24, count 2 2006.173.10:08:58.67#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.10:08:58.67#ibcon#[27=AT06-04\r\n] 2006.173.10:08:58.67#ibcon#*before write, iclass 24, count 2 2006.173.10:08:58.67#ibcon#enter sib2, iclass 24, count 2 2006.173.10:08:58.67#ibcon#flushed, iclass 24, count 2 2006.173.10:08:58.67#ibcon#about to write, iclass 24, count 2 2006.173.10:08:58.67#ibcon#wrote, iclass 24, count 2 2006.173.10:08:58.67#ibcon#about to read 3, iclass 24, count 2 2006.173.10:08:58.70#ibcon#read 3, iclass 24, count 2 2006.173.10:08:58.70#ibcon#about to read 4, iclass 24, count 2 2006.173.10:08:58.70#ibcon#read 4, iclass 24, count 2 2006.173.10:08:58.70#ibcon#about to read 5, iclass 24, count 2 2006.173.10:08:58.70#ibcon#read 5, iclass 24, count 2 2006.173.10:08:58.70#ibcon#about to read 6, iclass 24, count 2 2006.173.10:08:58.70#ibcon#read 6, iclass 24, count 2 2006.173.10:08:58.70#ibcon#end of sib2, iclass 24, count 2 2006.173.10:08:58.70#ibcon#*after write, iclass 24, count 2 2006.173.10:08:58.71#ibcon#*before return 0, iclass 24, count 2 2006.173.10:08:58.71#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.10:08:58.71#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.10:08:58.71#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.10:08:58.71#ibcon#ireg 7 cls_cnt 0 2006.173.10:08:58.71#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.10:08:58.82#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.10:08:58.82#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.10:08:58.82#ibcon#enter wrdev, iclass 24, count 0 2006.173.10:08:58.82#ibcon#first serial, iclass 24, count 0 2006.173.10:08:58.82#ibcon#enter sib2, iclass 24, count 0 2006.173.10:08:58.82#ibcon#flushed, iclass 24, count 0 2006.173.10:08:58.82#ibcon#about to write, iclass 24, count 0 2006.173.10:08:58.82#ibcon#wrote, iclass 24, count 0 2006.173.10:08:58.82#ibcon#about to read 3, iclass 24, count 0 2006.173.10:08:58.84#ibcon#read 3, iclass 24, count 0 2006.173.10:08:58.84#ibcon#about to read 4, iclass 24, count 0 2006.173.10:08:58.84#ibcon#read 4, iclass 24, count 0 2006.173.10:08:58.84#ibcon#about to read 5, iclass 24, count 0 2006.173.10:08:58.84#ibcon#read 5, iclass 24, count 0 2006.173.10:08:58.84#ibcon#about to read 6, iclass 24, count 0 2006.173.10:08:58.84#ibcon#read 6, iclass 24, count 0 2006.173.10:08:58.84#ibcon#end of sib2, iclass 24, count 0 2006.173.10:08:58.84#ibcon#*mode == 0, iclass 24, count 0 2006.173.10:08:58.84#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.10:08:58.84#ibcon#[27=USB\r\n] 2006.173.10:08:58.84#ibcon#*before write, iclass 24, count 0 2006.173.10:08:58.84#ibcon#enter sib2, iclass 24, count 0 2006.173.10:08:58.84#ibcon#flushed, iclass 24, count 0 2006.173.10:08:58.84#ibcon#about to write, iclass 24, count 0 2006.173.10:08:58.84#ibcon#wrote, iclass 24, count 0 2006.173.10:08:58.84#ibcon#about to read 3, iclass 24, count 0 2006.173.10:08:58.87#ibcon#read 3, iclass 24, count 0 2006.173.10:08:58.87#ibcon#about to read 4, iclass 24, count 0 2006.173.10:08:58.87#ibcon#read 4, iclass 24, count 0 2006.173.10:08:58.87#ibcon#about to read 5, iclass 24, count 0 2006.173.10:08:58.87#ibcon#read 5, iclass 24, count 0 2006.173.10:08:58.87#ibcon#about to read 6, iclass 24, count 0 2006.173.10:08:58.87#ibcon#read 6, iclass 24, count 0 2006.173.10:08:58.87#ibcon#end of sib2, iclass 24, count 0 2006.173.10:08:58.87#ibcon#*after write, iclass 24, count 0 2006.173.10:08:58.87#ibcon#*before return 0, iclass 24, count 0 2006.173.10:08:58.87#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.10:08:58.87#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.10:08:58.87#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.10:08:58.87#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.10:08:58.87$vck44/vblo=7,734.99 2006.173.10:08:58.87#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.10:08:58.87#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.10:08:58.87#ibcon#ireg 17 cls_cnt 0 2006.173.10:08:58.87#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.10:08:58.87#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.10:08:58.87#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.10:08:58.87#ibcon#enter wrdev, iclass 26, count 0 2006.173.10:08:58.87#ibcon#first serial, iclass 26, count 0 2006.173.10:08:58.87#ibcon#enter sib2, iclass 26, count 0 2006.173.10:08:58.87#ibcon#flushed, iclass 26, count 0 2006.173.10:08:58.87#ibcon#about to write, iclass 26, count 0 2006.173.10:08:58.87#ibcon#wrote, iclass 26, count 0 2006.173.10:08:58.87#ibcon#about to read 3, iclass 26, count 0 2006.173.10:08:58.89#ibcon#read 3, iclass 26, count 0 2006.173.10:08:58.89#ibcon#about to read 4, iclass 26, count 0 2006.173.10:08:58.89#ibcon#read 4, iclass 26, count 0 2006.173.10:08:58.89#ibcon#about to read 5, iclass 26, count 0 2006.173.10:08:58.89#ibcon#read 5, iclass 26, count 0 2006.173.10:08:58.89#ibcon#about to read 6, iclass 26, count 0 2006.173.10:08:58.89#ibcon#read 6, iclass 26, count 0 2006.173.10:08:58.89#ibcon#end of sib2, iclass 26, count 0 2006.173.10:08:58.89#ibcon#*mode == 0, iclass 26, count 0 2006.173.10:08:58.89#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.10:08:58.89#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.10:08:58.89#ibcon#*before write, iclass 26, count 0 2006.173.10:08:58.89#ibcon#enter sib2, iclass 26, count 0 2006.173.10:08:58.89#ibcon#flushed, iclass 26, count 0 2006.173.10:08:58.89#ibcon#about to write, iclass 26, count 0 2006.173.10:08:58.89#ibcon#wrote, iclass 26, count 0 2006.173.10:08:58.89#ibcon#about to read 3, iclass 26, count 0 2006.173.10:08:58.93#ibcon#read 3, iclass 26, count 0 2006.173.10:08:58.93#ibcon#about to read 4, iclass 26, count 0 2006.173.10:08:58.93#ibcon#read 4, iclass 26, count 0 2006.173.10:08:58.93#ibcon#about to read 5, iclass 26, count 0 2006.173.10:08:58.93#ibcon#read 5, iclass 26, count 0 2006.173.10:08:58.93#ibcon#about to read 6, iclass 26, count 0 2006.173.10:08:58.93#ibcon#read 6, iclass 26, count 0 2006.173.10:08:58.93#ibcon#end of sib2, iclass 26, count 0 2006.173.10:08:58.93#ibcon#*after write, iclass 26, count 0 2006.173.10:08:58.93#ibcon#*before return 0, iclass 26, count 0 2006.173.10:08:58.93#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.10:08:58.93#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.10:08:58.93#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.10:08:58.93#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.10:08:58.93$vck44/vb=7,4 2006.173.10:08:58.93#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.10:08:58.93#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.10:08:58.93#ibcon#ireg 11 cls_cnt 2 2006.173.10:08:58.93#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.10:08:58.99#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.10:08:58.99#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.10:08:58.99#ibcon#enter wrdev, iclass 28, count 2 2006.173.10:08:58.99#ibcon#first serial, iclass 28, count 2 2006.173.10:08:58.99#ibcon#enter sib2, iclass 28, count 2 2006.173.10:08:58.99#ibcon#flushed, iclass 28, count 2 2006.173.10:08:58.99#ibcon#about to write, iclass 28, count 2 2006.173.10:08:58.99#ibcon#wrote, iclass 28, count 2 2006.173.10:08:58.99#ibcon#about to read 3, iclass 28, count 2 2006.173.10:08:59.01#ibcon#read 3, iclass 28, count 2 2006.173.10:08:59.01#ibcon#about to read 4, iclass 28, count 2 2006.173.10:08:59.01#ibcon#read 4, iclass 28, count 2 2006.173.10:08:59.01#ibcon#about to read 5, iclass 28, count 2 2006.173.10:08:59.01#ibcon#read 5, iclass 28, count 2 2006.173.10:08:59.01#ibcon#about to read 6, iclass 28, count 2 2006.173.10:08:59.01#ibcon#read 6, iclass 28, count 2 2006.173.10:08:59.01#ibcon#end of sib2, iclass 28, count 2 2006.173.10:08:59.01#ibcon#*mode == 0, iclass 28, count 2 2006.173.10:08:59.01#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.10:08:59.01#ibcon#[27=AT07-04\r\n] 2006.173.10:08:59.01#ibcon#*before write, iclass 28, count 2 2006.173.10:08:59.01#ibcon#enter sib2, iclass 28, count 2 2006.173.10:08:59.01#ibcon#flushed, iclass 28, count 2 2006.173.10:08:59.01#ibcon#about to write, iclass 28, count 2 2006.173.10:08:59.01#ibcon#wrote, iclass 28, count 2 2006.173.10:08:59.01#ibcon#about to read 3, iclass 28, count 2 2006.173.10:08:59.04#ibcon#read 3, iclass 28, count 2 2006.173.10:08:59.04#ibcon#about to read 4, iclass 28, count 2 2006.173.10:08:59.04#ibcon#read 4, iclass 28, count 2 2006.173.10:08:59.04#ibcon#about to read 5, iclass 28, count 2 2006.173.10:08:59.04#ibcon#read 5, iclass 28, count 2 2006.173.10:08:59.04#ibcon#about to read 6, iclass 28, count 2 2006.173.10:08:59.04#ibcon#read 6, iclass 28, count 2 2006.173.10:08:59.04#ibcon#end of sib2, iclass 28, count 2 2006.173.10:08:59.04#ibcon#*after write, iclass 28, count 2 2006.173.10:08:59.04#ibcon#*before return 0, iclass 28, count 2 2006.173.10:08:59.04#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.10:08:59.04#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.10:08:59.04#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.10:08:59.04#ibcon#ireg 7 cls_cnt 0 2006.173.10:08:59.04#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.10:08:59.16#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.10:08:59.16#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.10:08:59.16#ibcon#enter wrdev, iclass 28, count 0 2006.173.10:08:59.16#ibcon#first serial, iclass 28, count 0 2006.173.10:08:59.16#ibcon#enter sib2, iclass 28, count 0 2006.173.10:08:59.16#ibcon#flushed, iclass 28, count 0 2006.173.10:08:59.16#ibcon#about to write, iclass 28, count 0 2006.173.10:08:59.16#ibcon#wrote, iclass 28, count 0 2006.173.10:08:59.16#ibcon#about to read 3, iclass 28, count 0 2006.173.10:08:59.18#ibcon#read 3, iclass 28, count 0 2006.173.10:08:59.18#ibcon#about to read 4, iclass 28, count 0 2006.173.10:08:59.18#ibcon#read 4, iclass 28, count 0 2006.173.10:08:59.18#ibcon#about to read 5, iclass 28, count 0 2006.173.10:08:59.18#ibcon#read 5, iclass 28, count 0 2006.173.10:08:59.18#ibcon#about to read 6, iclass 28, count 0 2006.173.10:08:59.18#ibcon#read 6, iclass 28, count 0 2006.173.10:08:59.18#ibcon#end of sib2, iclass 28, count 0 2006.173.10:08:59.18#ibcon#*mode == 0, iclass 28, count 0 2006.173.10:08:59.18#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.10:08:59.18#ibcon#[27=USB\r\n] 2006.173.10:08:59.18#ibcon#*before write, iclass 28, count 0 2006.173.10:08:59.18#ibcon#enter sib2, iclass 28, count 0 2006.173.10:08:59.18#ibcon#flushed, iclass 28, count 0 2006.173.10:08:59.18#ibcon#about to write, iclass 28, count 0 2006.173.10:08:59.18#ibcon#wrote, iclass 28, count 0 2006.173.10:08:59.18#ibcon#about to read 3, iclass 28, count 0 2006.173.10:08:59.21#ibcon#read 3, iclass 28, count 0 2006.173.10:08:59.21#ibcon#about to read 4, iclass 28, count 0 2006.173.10:08:59.21#ibcon#read 4, iclass 28, count 0 2006.173.10:08:59.21#ibcon#about to read 5, iclass 28, count 0 2006.173.10:08:59.21#ibcon#read 5, iclass 28, count 0 2006.173.10:08:59.21#ibcon#about to read 6, iclass 28, count 0 2006.173.10:08:59.21#ibcon#read 6, iclass 28, count 0 2006.173.10:08:59.21#ibcon#end of sib2, iclass 28, count 0 2006.173.10:08:59.21#ibcon#*after write, iclass 28, count 0 2006.173.10:08:59.21#ibcon#*before return 0, iclass 28, count 0 2006.173.10:08:59.21#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.10:08:59.21#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.10:08:59.21#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.10:08:59.21#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.10:08:59.21$vck44/vblo=8,744.99 2006.173.10:08:59.21#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.10:08:59.21#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.10:08:59.21#ibcon#ireg 17 cls_cnt 0 2006.173.10:08:59.21#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.10:08:59.21#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.10:08:59.21#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.10:08:59.21#ibcon#enter wrdev, iclass 30, count 0 2006.173.10:08:59.21#ibcon#first serial, iclass 30, count 0 2006.173.10:08:59.21#ibcon#enter sib2, iclass 30, count 0 2006.173.10:08:59.21#ibcon#flushed, iclass 30, count 0 2006.173.10:08:59.21#ibcon#about to write, iclass 30, count 0 2006.173.10:08:59.21#ibcon#wrote, iclass 30, count 0 2006.173.10:08:59.21#ibcon#about to read 3, iclass 30, count 0 2006.173.10:08:59.23#ibcon#read 3, iclass 30, count 0 2006.173.10:08:59.23#ibcon#about to read 4, iclass 30, count 0 2006.173.10:08:59.23#ibcon#read 4, iclass 30, count 0 2006.173.10:08:59.23#ibcon#about to read 5, iclass 30, count 0 2006.173.10:08:59.23#ibcon#read 5, iclass 30, count 0 2006.173.10:08:59.23#ibcon#about to read 6, iclass 30, count 0 2006.173.10:08:59.23#ibcon#read 6, iclass 30, count 0 2006.173.10:08:59.23#ibcon#end of sib2, iclass 30, count 0 2006.173.10:08:59.23#ibcon#*mode == 0, iclass 30, count 0 2006.173.10:08:59.23#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.10:08:59.23#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.10:08:59.23#ibcon#*before write, iclass 30, count 0 2006.173.10:08:59.23#ibcon#enter sib2, iclass 30, count 0 2006.173.10:08:59.23#ibcon#flushed, iclass 30, count 0 2006.173.10:08:59.23#ibcon#about to write, iclass 30, count 0 2006.173.10:08:59.23#ibcon#wrote, iclass 30, count 0 2006.173.10:08:59.23#ibcon#about to read 3, iclass 30, count 0 2006.173.10:08:59.27#ibcon#read 3, iclass 30, count 0 2006.173.10:08:59.27#ibcon#about to read 4, iclass 30, count 0 2006.173.10:08:59.27#ibcon#read 4, iclass 30, count 0 2006.173.10:08:59.27#ibcon#about to read 5, iclass 30, count 0 2006.173.10:08:59.27#ibcon#read 5, iclass 30, count 0 2006.173.10:08:59.27#ibcon#about to read 6, iclass 30, count 0 2006.173.10:08:59.27#ibcon#read 6, iclass 30, count 0 2006.173.10:08:59.27#ibcon#end of sib2, iclass 30, count 0 2006.173.10:08:59.27#ibcon#*after write, iclass 30, count 0 2006.173.10:08:59.27#ibcon#*before return 0, iclass 30, count 0 2006.173.10:08:59.27#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.10:08:59.27#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.10:08:59.27#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.10:08:59.27#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.10:08:59.27$vck44/vb=8,4 2006.173.10:08:59.27#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.173.10:08:59.27#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.173.10:08:59.27#ibcon#ireg 11 cls_cnt 2 2006.173.10:08:59.27#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.10:08:59.33#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.10:08:59.33#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.10:08:59.33#ibcon#enter wrdev, iclass 32, count 2 2006.173.10:08:59.33#ibcon#first serial, iclass 32, count 2 2006.173.10:08:59.33#ibcon#enter sib2, iclass 32, count 2 2006.173.10:08:59.33#ibcon#flushed, iclass 32, count 2 2006.173.10:08:59.33#ibcon#about to write, iclass 32, count 2 2006.173.10:08:59.33#ibcon#wrote, iclass 32, count 2 2006.173.10:08:59.33#ibcon#about to read 3, iclass 32, count 2 2006.173.10:08:59.35#ibcon#read 3, iclass 32, count 2 2006.173.10:08:59.35#ibcon#about to read 4, iclass 32, count 2 2006.173.10:08:59.35#ibcon#read 4, iclass 32, count 2 2006.173.10:08:59.35#ibcon#about to read 5, iclass 32, count 2 2006.173.10:08:59.35#ibcon#read 5, iclass 32, count 2 2006.173.10:08:59.35#ibcon#about to read 6, iclass 32, count 2 2006.173.10:08:59.35#ibcon#read 6, iclass 32, count 2 2006.173.10:08:59.35#ibcon#end of sib2, iclass 32, count 2 2006.173.10:08:59.35#ibcon#*mode == 0, iclass 32, count 2 2006.173.10:08:59.35#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.173.10:08:59.35#ibcon#[27=AT08-04\r\n] 2006.173.10:08:59.35#ibcon#*before write, iclass 32, count 2 2006.173.10:08:59.35#ibcon#enter sib2, iclass 32, count 2 2006.173.10:08:59.35#ibcon#flushed, iclass 32, count 2 2006.173.10:08:59.35#ibcon#about to write, iclass 32, count 2 2006.173.10:08:59.35#ibcon#wrote, iclass 32, count 2 2006.173.10:08:59.35#ibcon#about to read 3, iclass 32, count 2 2006.173.10:08:59.38#ibcon#read 3, iclass 32, count 2 2006.173.10:08:59.38#ibcon#about to read 4, iclass 32, count 2 2006.173.10:08:59.38#ibcon#read 4, iclass 32, count 2 2006.173.10:08:59.38#ibcon#about to read 5, iclass 32, count 2 2006.173.10:08:59.38#ibcon#read 5, iclass 32, count 2 2006.173.10:08:59.38#ibcon#about to read 6, iclass 32, count 2 2006.173.10:08:59.38#ibcon#read 6, iclass 32, count 2 2006.173.10:08:59.38#ibcon#end of sib2, iclass 32, count 2 2006.173.10:08:59.38#ibcon#*after write, iclass 32, count 2 2006.173.10:08:59.38#ibcon#*before return 0, iclass 32, count 2 2006.173.10:08:59.38#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.10:08:59.38#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.173.10:08:59.38#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.173.10:08:59.38#ibcon#ireg 7 cls_cnt 0 2006.173.10:08:59.38#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.10:08:59.50#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.10:08:59.50#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.10:08:59.50#ibcon#enter wrdev, iclass 32, count 0 2006.173.10:08:59.50#ibcon#first serial, iclass 32, count 0 2006.173.10:08:59.50#ibcon#enter sib2, iclass 32, count 0 2006.173.10:08:59.50#ibcon#flushed, iclass 32, count 0 2006.173.10:08:59.50#ibcon#about to write, iclass 32, count 0 2006.173.10:08:59.50#ibcon#wrote, iclass 32, count 0 2006.173.10:08:59.50#ibcon#about to read 3, iclass 32, count 0 2006.173.10:08:59.52#ibcon#read 3, iclass 32, count 0 2006.173.10:08:59.52#ibcon#about to read 4, iclass 32, count 0 2006.173.10:08:59.52#ibcon#read 4, iclass 32, count 0 2006.173.10:08:59.52#ibcon#about to read 5, iclass 32, count 0 2006.173.10:08:59.52#ibcon#read 5, iclass 32, count 0 2006.173.10:08:59.52#ibcon#about to read 6, iclass 32, count 0 2006.173.10:08:59.52#ibcon#read 6, iclass 32, count 0 2006.173.10:08:59.52#ibcon#end of sib2, iclass 32, count 0 2006.173.10:08:59.52#ibcon#*mode == 0, iclass 32, count 0 2006.173.10:08:59.52#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.10:08:59.52#ibcon#[27=USB\r\n] 2006.173.10:08:59.52#ibcon#*before write, iclass 32, count 0 2006.173.10:08:59.52#ibcon#enter sib2, iclass 32, count 0 2006.173.10:08:59.52#ibcon#flushed, iclass 32, count 0 2006.173.10:08:59.52#ibcon#about to write, iclass 32, count 0 2006.173.10:08:59.52#ibcon#wrote, iclass 32, count 0 2006.173.10:08:59.52#ibcon#about to read 3, iclass 32, count 0 2006.173.10:08:59.55#ibcon#read 3, iclass 32, count 0 2006.173.10:08:59.55#ibcon#about to read 4, iclass 32, count 0 2006.173.10:08:59.55#ibcon#read 4, iclass 32, count 0 2006.173.10:08:59.55#ibcon#about to read 5, iclass 32, count 0 2006.173.10:08:59.55#ibcon#read 5, iclass 32, count 0 2006.173.10:08:59.55#ibcon#about to read 6, iclass 32, count 0 2006.173.10:08:59.55#ibcon#read 6, iclass 32, count 0 2006.173.10:08:59.55#ibcon#end of sib2, iclass 32, count 0 2006.173.10:08:59.55#ibcon#*after write, iclass 32, count 0 2006.173.10:08:59.55#ibcon#*before return 0, iclass 32, count 0 2006.173.10:08:59.55#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.10:08:59.55#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.173.10:08:59.55#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.10:08:59.55#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.10:08:59.55$vck44/vabw=wide 2006.173.10:08:59.55#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.10:08:59.55#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.10:08:59.55#ibcon#ireg 8 cls_cnt 0 2006.173.10:08:59.55#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.10:08:59.55#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.10:08:59.55#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.10:08:59.55#ibcon#enter wrdev, iclass 34, count 0 2006.173.10:08:59.55#ibcon#first serial, iclass 34, count 0 2006.173.10:08:59.55#ibcon#enter sib2, iclass 34, count 0 2006.173.10:08:59.55#ibcon#flushed, iclass 34, count 0 2006.173.10:08:59.55#ibcon#about to write, iclass 34, count 0 2006.173.10:08:59.55#ibcon#wrote, iclass 34, count 0 2006.173.10:08:59.55#ibcon#about to read 3, iclass 34, count 0 2006.173.10:08:59.57#ibcon#read 3, iclass 34, count 0 2006.173.10:08:59.57#ibcon#about to read 4, iclass 34, count 0 2006.173.10:08:59.57#ibcon#read 4, iclass 34, count 0 2006.173.10:08:59.57#ibcon#about to read 5, iclass 34, count 0 2006.173.10:08:59.57#ibcon#read 5, iclass 34, count 0 2006.173.10:08:59.57#ibcon#about to read 6, iclass 34, count 0 2006.173.10:08:59.57#ibcon#read 6, iclass 34, count 0 2006.173.10:08:59.57#ibcon#end of sib2, iclass 34, count 0 2006.173.10:08:59.57#ibcon#*mode == 0, iclass 34, count 0 2006.173.10:08:59.57#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.10:08:59.57#ibcon#[25=BW32\r\n] 2006.173.10:08:59.57#ibcon#*before write, iclass 34, count 0 2006.173.10:08:59.57#ibcon#enter sib2, iclass 34, count 0 2006.173.10:08:59.57#ibcon#flushed, iclass 34, count 0 2006.173.10:08:59.57#ibcon#about to write, iclass 34, count 0 2006.173.10:08:59.57#ibcon#wrote, iclass 34, count 0 2006.173.10:08:59.57#ibcon#about to read 3, iclass 34, count 0 2006.173.10:08:59.60#ibcon#read 3, iclass 34, count 0 2006.173.10:08:59.60#ibcon#about to read 4, iclass 34, count 0 2006.173.10:08:59.60#ibcon#read 4, iclass 34, count 0 2006.173.10:08:59.60#ibcon#about to read 5, iclass 34, count 0 2006.173.10:08:59.60#ibcon#read 5, iclass 34, count 0 2006.173.10:08:59.60#ibcon#about to read 6, iclass 34, count 0 2006.173.10:08:59.60#ibcon#read 6, iclass 34, count 0 2006.173.10:08:59.60#ibcon#end of sib2, iclass 34, count 0 2006.173.10:08:59.60#ibcon#*after write, iclass 34, count 0 2006.173.10:08:59.60#ibcon#*before return 0, iclass 34, count 0 2006.173.10:08:59.60#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.10:08:59.60#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.10:08:59.60#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.10:08:59.60#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.10:08:59.60$vck44/vbbw=wide 2006.173.10:08:59.60#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.10:08:59.60#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.10:08:59.60#ibcon#ireg 8 cls_cnt 0 2006.173.10:08:59.60#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.10:08:59.67#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.10:08:59.67#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.10:08:59.67#ibcon#enter wrdev, iclass 36, count 0 2006.173.10:08:59.67#ibcon#first serial, iclass 36, count 0 2006.173.10:08:59.67#ibcon#enter sib2, iclass 36, count 0 2006.173.10:08:59.67#ibcon#flushed, iclass 36, count 0 2006.173.10:08:59.67#ibcon#about to write, iclass 36, count 0 2006.173.10:08:59.67#ibcon#wrote, iclass 36, count 0 2006.173.10:08:59.67#ibcon#about to read 3, iclass 36, count 0 2006.173.10:08:59.69#ibcon#read 3, iclass 36, count 0 2006.173.10:08:59.69#ibcon#about to read 4, iclass 36, count 0 2006.173.10:08:59.69#ibcon#read 4, iclass 36, count 0 2006.173.10:08:59.69#ibcon#about to read 5, iclass 36, count 0 2006.173.10:08:59.69#ibcon#read 5, iclass 36, count 0 2006.173.10:08:59.69#ibcon#about to read 6, iclass 36, count 0 2006.173.10:08:59.69#ibcon#read 6, iclass 36, count 0 2006.173.10:08:59.69#ibcon#end of sib2, iclass 36, count 0 2006.173.10:08:59.69#ibcon#*mode == 0, iclass 36, count 0 2006.173.10:08:59.69#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.10:08:59.69#ibcon#[27=BW32\r\n] 2006.173.10:08:59.69#ibcon#*before write, iclass 36, count 0 2006.173.10:08:59.69#ibcon#enter sib2, iclass 36, count 0 2006.173.10:08:59.69#ibcon#flushed, iclass 36, count 0 2006.173.10:08:59.69#ibcon#about to write, iclass 36, count 0 2006.173.10:08:59.69#ibcon#wrote, iclass 36, count 0 2006.173.10:08:59.69#ibcon#about to read 3, iclass 36, count 0 2006.173.10:08:59.72#ibcon#read 3, iclass 36, count 0 2006.173.10:08:59.72#ibcon#about to read 4, iclass 36, count 0 2006.173.10:08:59.72#ibcon#read 4, iclass 36, count 0 2006.173.10:08:59.72#ibcon#about to read 5, iclass 36, count 0 2006.173.10:08:59.72#ibcon#read 5, iclass 36, count 0 2006.173.10:08:59.72#ibcon#about to read 6, iclass 36, count 0 2006.173.10:08:59.72#ibcon#read 6, iclass 36, count 0 2006.173.10:08:59.72#ibcon#end of sib2, iclass 36, count 0 2006.173.10:08:59.72#ibcon#*after write, iclass 36, count 0 2006.173.10:08:59.72#ibcon#*before return 0, iclass 36, count 0 2006.173.10:08:59.72#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.10:08:59.72#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.10:08:59.72#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.10:08:59.72#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.10:08:59.72$setupk4/ifdk4 2006.173.10:08:59.72$ifdk4/lo= 2006.173.10:08:59.72$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.10:08:59.72$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.10:08:59.72$ifdk4/patch= 2006.173.10:08:59.72$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.10:08:59.72$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.10:08:59.72$setupk4/!*+20s 2006.173.10:09:00.12#abcon#<5=/06 1.3 1.7 22.81 931004.1\r\n> 2006.173.10:09:00.14#abcon#{5=INTERFACE CLEAR} 2006.173.10:09:00.20#abcon#[5=S1D000X0/0*\r\n] 2006.173.10:09:10.29#abcon#<5=/06 1.3 1.7 22.81 921004.1\r\n> 2006.173.10:09:10.31#abcon#{5=INTERFACE CLEAR} 2006.173.10:09:10.37#abcon#[5=S1D000X0/0*\r\n] 2006.173.10:09:14.23$setupk4/"tpicd 2006.173.10:09:14.23$setupk4/echo=off 2006.173.10:09:14.23$setupk4/xlog=off 2006.173.10:09:14.23:!2006.173.10:15:42 2006.173.10:09:29.14#trakl#Source acquired 2006.173.10:09:29.14#flagr#flagr/antenna,acquired 2006.173.10:15:42.00:preob 2006.173.10:15:42.13/onsource/TRACKING 2006.173.10:15:42.13:!2006.173.10:15:52 2006.173.10:15:52.00:"tape 2006.173.10:15:52.00:"st=record 2006.173.10:15:52.00:data_valid=on 2006.173.10:15:52.00:midob 2006.173.10:15:53.13/onsource/TRACKING 2006.173.10:15:53.13/wx/22.77,1004.1,90 2006.173.10:15:53.26/cable/+6.5021E-03 2006.173.10:15:54.35/va/01,07,usb,yes,60,64 2006.173.10:15:54.35/va/02,06,usb,yes,59,61 2006.173.10:15:54.35/va/03,05,usb,yes,74,77 2006.173.10:15:54.35/va/04,06,usb,yes,61,64 2006.173.10:15:54.35/va/05,04,usb,yes,49,50 2006.173.10:15:54.35/va/06,03,usb,yes,66,66 2006.173.10:15:54.35/va/07,04,usb,yes,54,56 2006.173.10:15:54.35/va/08,04,usb,yes,47,55 2006.173.10:15:54.58/valo/01,524.99,yes,locked 2006.173.10:15:54.58/valo/02,534.99,yes,locked 2006.173.10:15:54.58/valo/03,564.99,yes,locked 2006.173.10:15:54.58/valo/04,624.99,yes,locked 2006.173.10:15:54.58/valo/05,734.99,yes,locked 2006.173.10:15:54.58/valo/06,814.99,yes,locked 2006.173.10:15:54.58/valo/07,864.99,yes,locked 2006.173.10:15:54.58/valo/08,884.99,yes,locked 2006.173.10:15:55.67/vb/01,04,usb,yes,43,42 2006.173.10:15:55.67/vb/02,04,usb,yes,46,48 2006.173.10:15:55.67/vb/03,04,usb,yes,42,47 2006.173.10:15:55.67/vb/04,04,usb,yes,48,47 2006.173.10:15:55.67/vb/05,04,usb,yes,39,42 2006.173.10:15:55.67/vb/06,04,usb,yes,45,40 2006.173.10:15:55.67/vb/07,04,usb,yes,44,44 2006.173.10:15:55.67/vb/08,04,usb,yes,40,45 2006.173.10:15:55.90/vblo/01,629.99,yes,locked 2006.173.10:15:55.90/vblo/02,634.99,yes,locked 2006.173.10:15:55.90/vblo/03,649.99,yes,locked 2006.173.10:15:55.90/vblo/04,679.99,yes,locked 2006.173.10:15:55.90/vblo/05,709.99,yes,locked 2006.173.10:15:55.90/vblo/06,719.99,yes,locked 2006.173.10:15:55.90/vblo/07,734.99,yes,locked 2006.173.10:15:55.90/vblo/08,744.99,yes,locked 2006.173.10:15:56.05/vabw/8 2006.173.10:15:56.20/vbbw/8 2006.173.10:15:56.29/xfe/off,on,14.7 2006.173.10:15:56.69/ifatt/23,28,28,28 2006.173.10:15:57.08/fmout-gps/S +4.01E-07 2006.173.10:15:57.12:!2006.173.10:17:42 2006.173.10:17:42.00:data_valid=off 2006.173.10:17:42.00:"et 2006.173.10:17:42.00:!+3s 2006.173.10:17:45.01:"tape 2006.173.10:17:45.01:postob 2006.173.10:17:45.16/cable/+6.5023E-03 2006.173.10:17:45.16/wx/22.75,1004.1,91 2006.173.10:17:46.08/fmout-gps/S +4.03E-07 2006.173.10:17:46.08:scan_name=173-1018,jd0606,220 2006.173.10:17:46.08:source=1044+719,104827.62,714335.9,2000.0,cw 2006.173.10:17:47.14#flagr#flagr/antenna,new-source 2006.173.10:17:47.14:checkk5 2006.173.10:17:47.55/chk_autoobs//k5ts1/ autoobs is running! 2006.173.10:17:47.94/chk_autoobs//k5ts2/ autoobs is running! 2006.173.10:17:48.34/chk_autoobs//k5ts3/ autoobs is running! 2006.173.10:17:48.73/chk_autoobs//k5ts4/ autoobs is running! 2006.173.10:17:49.12/chk_obsdata//k5ts1/T1731015??a.dat file size is correct (nominal:440MB, actual:436MB). 2006.173.10:17:49.52/chk_obsdata//k5ts2/T1731015??b.dat file size is correct (nominal:440MB, actual:436MB). 2006.173.10:17:49.94/chk_obsdata//k5ts3/T1731015??c.dat file size is correct (nominal:440MB, actual:436MB). 2006.173.10:17:50.35/chk_obsdata//k5ts4/T1731015??d.dat file size is correct (nominal:440MB, actual:436MB). 2006.173.10:17:51.08/k5log//k5ts1_log_newline 2006.173.10:17:51.81/k5log//k5ts2_log_newline 2006.173.10:17:52.52/k5log//k5ts3_log_newline 2006.173.10:17:53.21/k5log//k5ts4_log_newline 2006.173.10:17:53.24/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.10:17:53.24:setupk4=1 2006.173.10:17:53.24$setupk4/echo=on 2006.173.10:17:53.24$setupk4/pcalon 2006.173.10:17:53.24$pcalon/"no phase cal control is implemented here 2006.173.10:17:53.24$setupk4/"tpicd=stop 2006.173.10:17:53.24$setupk4/"rec=synch_on 2006.173.10:17:53.24$setupk4/"rec_mode=128 2006.173.10:17:53.24$setupk4/!* 2006.173.10:17:53.24$setupk4/recpk4 2006.173.10:17:53.24$recpk4/recpatch= 2006.173.10:17:53.24$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.10:17:53.24$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.10:17:53.24$setupk4/vck44 2006.173.10:17:53.24$vck44/valo=1,524.99 2006.173.10:17:53.24#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.10:17:53.24#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.10:17:53.24#ibcon#ireg 17 cls_cnt 0 2006.173.10:17:53.24#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.10:17:53.24#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.10:17:53.24#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.10:17:53.24#ibcon#enter wrdev, iclass 37, count 0 2006.173.10:17:53.24#ibcon#first serial, iclass 37, count 0 2006.173.10:17:53.24#ibcon#enter sib2, iclass 37, count 0 2006.173.10:17:53.24#ibcon#flushed, iclass 37, count 0 2006.173.10:17:53.24#ibcon#about to write, iclass 37, count 0 2006.173.10:17:53.24#ibcon#wrote, iclass 37, count 0 2006.173.10:17:53.24#ibcon#about to read 3, iclass 37, count 0 2006.173.10:17:53.26#ibcon#read 3, iclass 37, count 0 2006.173.10:17:53.26#ibcon#about to read 4, iclass 37, count 0 2006.173.10:17:53.26#ibcon#read 4, iclass 37, count 0 2006.173.10:17:53.26#ibcon#about to read 5, iclass 37, count 0 2006.173.10:17:53.26#ibcon#read 5, iclass 37, count 0 2006.173.10:17:53.26#ibcon#about to read 6, iclass 37, count 0 2006.173.10:17:53.26#ibcon#read 6, iclass 37, count 0 2006.173.10:17:53.26#ibcon#end of sib2, iclass 37, count 0 2006.173.10:17:53.26#ibcon#*mode == 0, iclass 37, count 0 2006.173.10:17:53.26#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.10:17:53.26#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.10:17:53.26#ibcon#*before write, iclass 37, count 0 2006.173.10:17:53.26#ibcon#enter sib2, iclass 37, count 0 2006.173.10:17:53.26#ibcon#flushed, iclass 37, count 0 2006.173.10:17:53.26#ibcon#about to write, iclass 37, count 0 2006.173.10:17:53.26#ibcon#wrote, iclass 37, count 0 2006.173.10:17:53.26#ibcon#about to read 3, iclass 37, count 0 2006.173.10:17:53.31#ibcon#read 3, iclass 37, count 0 2006.173.10:17:53.31#ibcon#about to read 4, iclass 37, count 0 2006.173.10:17:53.31#ibcon#read 4, iclass 37, count 0 2006.173.10:17:53.31#ibcon#about to read 5, iclass 37, count 0 2006.173.10:17:53.31#ibcon#read 5, iclass 37, count 0 2006.173.10:17:53.31#ibcon#about to read 6, iclass 37, count 0 2006.173.10:17:53.31#ibcon#read 6, iclass 37, count 0 2006.173.10:17:53.31#ibcon#end of sib2, iclass 37, count 0 2006.173.10:17:53.31#ibcon#*after write, iclass 37, count 0 2006.173.10:17:53.31#ibcon#*before return 0, iclass 37, count 0 2006.173.10:17:53.31#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.10:17:53.31#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.10:17:53.31#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.10:17:53.31#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.10:17:53.31$vck44/va=1,7 2006.173.10:17:53.31#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.10:17:53.31#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.10:17:53.31#ibcon#ireg 11 cls_cnt 2 2006.173.10:17:53.31#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.10:17:53.31#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.10:17:53.31#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.10:17:53.31#ibcon#enter wrdev, iclass 39, count 2 2006.173.10:17:53.31#ibcon#first serial, iclass 39, count 2 2006.173.10:17:53.31#ibcon#enter sib2, iclass 39, count 2 2006.173.10:17:53.31#ibcon#flushed, iclass 39, count 2 2006.173.10:17:53.31#ibcon#about to write, iclass 39, count 2 2006.173.10:17:53.31#ibcon#wrote, iclass 39, count 2 2006.173.10:17:53.31#ibcon#about to read 3, iclass 39, count 2 2006.173.10:17:53.33#ibcon#read 3, iclass 39, count 2 2006.173.10:17:53.33#ibcon#about to read 4, iclass 39, count 2 2006.173.10:17:53.33#ibcon#read 4, iclass 39, count 2 2006.173.10:17:53.33#ibcon#about to read 5, iclass 39, count 2 2006.173.10:17:53.33#ibcon#read 5, iclass 39, count 2 2006.173.10:17:53.33#ibcon#about to read 6, iclass 39, count 2 2006.173.10:17:53.33#ibcon#read 6, iclass 39, count 2 2006.173.10:17:53.33#ibcon#end of sib2, iclass 39, count 2 2006.173.10:17:53.33#ibcon#*mode == 0, iclass 39, count 2 2006.173.10:17:53.33#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.10:17:53.33#ibcon#[25=AT01-07\r\n] 2006.173.10:17:53.33#ibcon#*before write, iclass 39, count 2 2006.173.10:17:53.33#ibcon#enter sib2, iclass 39, count 2 2006.173.10:17:53.33#ibcon#flushed, iclass 39, count 2 2006.173.10:17:53.33#ibcon#about to write, iclass 39, count 2 2006.173.10:17:53.33#ibcon#wrote, iclass 39, count 2 2006.173.10:17:53.33#ibcon#about to read 3, iclass 39, count 2 2006.173.10:17:53.36#ibcon#read 3, iclass 39, count 2 2006.173.10:17:53.36#ibcon#about to read 4, iclass 39, count 2 2006.173.10:17:53.36#ibcon#read 4, iclass 39, count 2 2006.173.10:17:53.36#ibcon#about to read 5, iclass 39, count 2 2006.173.10:17:53.36#ibcon#read 5, iclass 39, count 2 2006.173.10:17:53.36#ibcon#about to read 6, iclass 39, count 2 2006.173.10:17:53.36#ibcon#read 6, iclass 39, count 2 2006.173.10:17:53.36#ibcon#end of sib2, iclass 39, count 2 2006.173.10:17:53.36#ibcon#*after write, iclass 39, count 2 2006.173.10:17:53.36#ibcon#*before return 0, iclass 39, count 2 2006.173.10:17:53.36#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.10:17:53.36#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.10:17:53.36#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.10:17:53.36#ibcon#ireg 7 cls_cnt 0 2006.173.10:17:53.36#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.10:17:53.48#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.10:17:53.48#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.10:17:53.48#ibcon#enter wrdev, iclass 39, count 0 2006.173.10:17:53.48#ibcon#first serial, iclass 39, count 0 2006.173.10:17:53.48#ibcon#enter sib2, iclass 39, count 0 2006.173.10:17:53.48#ibcon#flushed, iclass 39, count 0 2006.173.10:17:53.48#ibcon#about to write, iclass 39, count 0 2006.173.10:17:53.48#ibcon#wrote, iclass 39, count 0 2006.173.10:17:53.48#ibcon#about to read 3, iclass 39, count 0 2006.173.10:17:53.50#ibcon#read 3, iclass 39, count 0 2006.173.10:17:53.50#ibcon#about to read 4, iclass 39, count 0 2006.173.10:17:53.50#ibcon#read 4, iclass 39, count 0 2006.173.10:17:53.50#ibcon#about to read 5, iclass 39, count 0 2006.173.10:17:53.50#ibcon#read 5, iclass 39, count 0 2006.173.10:17:53.50#ibcon#about to read 6, iclass 39, count 0 2006.173.10:17:53.50#ibcon#read 6, iclass 39, count 0 2006.173.10:17:53.50#ibcon#end of sib2, iclass 39, count 0 2006.173.10:17:53.50#ibcon#*mode == 0, iclass 39, count 0 2006.173.10:17:53.50#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.10:17:53.50#ibcon#[25=USB\r\n] 2006.173.10:17:53.50#ibcon#*before write, iclass 39, count 0 2006.173.10:17:53.50#ibcon#enter sib2, iclass 39, count 0 2006.173.10:17:53.50#ibcon#flushed, iclass 39, count 0 2006.173.10:17:53.50#ibcon#about to write, iclass 39, count 0 2006.173.10:17:53.50#ibcon#wrote, iclass 39, count 0 2006.173.10:17:53.50#ibcon#about to read 3, iclass 39, count 0 2006.173.10:17:53.53#ibcon#read 3, iclass 39, count 0 2006.173.10:17:53.53#ibcon#about to read 4, iclass 39, count 0 2006.173.10:17:53.53#ibcon#read 4, iclass 39, count 0 2006.173.10:17:53.53#ibcon#about to read 5, iclass 39, count 0 2006.173.10:17:53.53#ibcon#read 5, iclass 39, count 0 2006.173.10:17:53.53#ibcon#about to read 6, iclass 39, count 0 2006.173.10:17:53.53#ibcon#read 6, iclass 39, count 0 2006.173.10:17:53.53#ibcon#end of sib2, iclass 39, count 0 2006.173.10:17:53.53#ibcon#*after write, iclass 39, count 0 2006.173.10:17:53.53#ibcon#*before return 0, iclass 39, count 0 2006.173.10:17:53.53#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.10:17:53.53#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.10:17:53.53#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.10:17:53.53#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.10:17:53.53$vck44/valo=2,534.99 2006.173.10:17:53.53#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.10:17:53.53#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.10:17:53.53#ibcon#ireg 17 cls_cnt 0 2006.173.10:17:53.53#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.10:17:53.53#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.10:17:53.53#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.10:17:53.53#ibcon#enter wrdev, iclass 3, count 0 2006.173.10:17:53.53#ibcon#first serial, iclass 3, count 0 2006.173.10:17:53.53#ibcon#enter sib2, iclass 3, count 0 2006.173.10:17:53.53#ibcon#flushed, iclass 3, count 0 2006.173.10:17:53.53#ibcon#about to write, iclass 3, count 0 2006.173.10:17:53.53#ibcon#wrote, iclass 3, count 0 2006.173.10:17:53.53#ibcon#about to read 3, iclass 3, count 0 2006.173.10:17:53.55#ibcon#read 3, iclass 3, count 0 2006.173.10:17:53.55#ibcon#about to read 4, iclass 3, count 0 2006.173.10:17:53.55#ibcon#read 4, iclass 3, count 0 2006.173.10:17:53.55#ibcon#about to read 5, iclass 3, count 0 2006.173.10:17:53.55#ibcon#read 5, iclass 3, count 0 2006.173.10:17:53.55#ibcon#about to read 6, iclass 3, count 0 2006.173.10:17:53.55#ibcon#read 6, iclass 3, count 0 2006.173.10:17:53.55#ibcon#end of sib2, iclass 3, count 0 2006.173.10:17:53.55#ibcon#*mode == 0, iclass 3, count 0 2006.173.10:17:53.55#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.10:17:53.55#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.10:17:53.55#ibcon#*before write, iclass 3, count 0 2006.173.10:17:53.55#ibcon#enter sib2, iclass 3, count 0 2006.173.10:17:53.55#ibcon#flushed, iclass 3, count 0 2006.173.10:17:53.55#ibcon#about to write, iclass 3, count 0 2006.173.10:17:53.55#ibcon#wrote, iclass 3, count 0 2006.173.10:17:53.55#ibcon#about to read 3, iclass 3, count 0 2006.173.10:17:53.59#ibcon#read 3, iclass 3, count 0 2006.173.10:17:53.59#ibcon#about to read 4, iclass 3, count 0 2006.173.10:17:53.59#ibcon#read 4, iclass 3, count 0 2006.173.10:17:53.59#ibcon#about to read 5, iclass 3, count 0 2006.173.10:17:53.59#ibcon#read 5, iclass 3, count 0 2006.173.10:17:53.59#ibcon#about to read 6, iclass 3, count 0 2006.173.10:17:53.59#ibcon#read 6, iclass 3, count 0 2006.173.10:17:53.59#ibcon#end of sib2, iclass 3, count 0 2006.173.10:17:53.59#ibcon#*after write, iclass 3, count 0 2006.173.10:17:53.59#ibcon#*before return 0, iclass 3, count 0 2006.173.10:17:53.59#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.10:17:53.59#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.10:17:53.59#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.10:17:53.59#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.10:17:53.59$vck44/va=2,6 2006.173.10:17:53.59#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.10:17:53.59#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.10:17:53.59#ibcon#ireg 11 cls_cnt 2 2006.173.10:17:53.59#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.10:17:53.65#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.10:17:53.65#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.10:17:53.65#ibcon#enter wrdev, iclass 5, count 2 2006.173.10:17:53.65#ibcon#first serial, iclass 5, count 2 2006.173.10:17:53.65#ibcon#enter sib2, iclass 5, count 2 2006.173.10:17:53.65#ibcon#flushed, iclass 5, count 2 2006.173.10:17:53.65#ibcon#about to write, iclass 5, count 2 2006.173.10:17:53.65#ibcon#wrote, iclass 5, count 2 2006.173.10:17:53.65#ibcon#about to read 3, iclass 5, count 2 2006.173.10:17:53.67#ibcon#read 3, iclass 5, count 2 2006.173.10:17:53.67#ibcon#about to read 4, iclass 5, count 2 2006.173.10:17:53.67#ibcon#read 4, iclass 5, count 2 2006.173.10:17:53.67#ibcon#about to read 5, iclass 5, count 2 2006.173.10:17:53.67#ibcon#read 5, iclass 5, count 2 2006.173.10:17:53.67#ibcon#about to read 6, iclass 5, count 2 2006.173.10:17:53.67#ibcon#read 6, iclass 5, count 2 2006.173.10:17:53.67#ibcon#end of sib2, iclass 5, count 2 2006.173.10:17:53.67#ibcon#*mode == 0, iclass 5, count 2 2006.173.10:17:53.67#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.10:17:53.67#ibcon#[25=AT02-06\r\n] 2006.173.10:17:53.67#ibcon#*before write, iclass 5, count 2 2006.173.10:17:53.67#ibcon#enter sib2, iclass 5, count 2 2006.173.10:17:53.67#ibcon#flushed, iclass 5, count 2 2006.173.10:17:53.67#ibcon#about to write, iclass 5, count 2 2006.173.10:17:53.67#ibcon#wrote, iclass 5, count 2 2006.173.10:17:53.67#ibcon#about to read 3, iclass 5, count 2 2006.173.10:17:53.70#ibcon#read 3, iclass 5, count 2 2006.173.10:17:53.70#ibcon#about to read 4, iclass 5, count 2 2006.173.10:17:53.70#ibcon#read 4, iclass 5, count 2 2006.173.10:17:53.70#ibcon#about to read 5, iclass 5, count 2 2006.173.10:17:53.70#ibcon#read 5, iclass 5, count 2 2006.173.10:17:53.70#ibcon#about to read 6, iclass 5, count 2 2006.173.10:17:53.70#ibcon#read 6, iclass 5, count 2 2006.173.10:17:53.70#ibcon#end of sib2, iclass 5, count 2 2006.173.10:17:53.70#ibcon#*after write, iclass 5, count 2 2006.173.10:17:53.70#ibcon#*before return 0, iclass 5, count 2 2006.173.10:17:53.70#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.10:17:53.70#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.10:17:53.70#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.10:17:53.70#ibcon#ireg 7 cls_cnt 0 2006.173.10:17:53.70#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.10:17:53.82#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.10:17:53.82#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.10:17:53.82#ibcon#enter wrdev, iclass 5, count 0 2006.173.10:17:53.82#ibcon#first serial, iclass 5, count 0 2006.173.10:17:53.82#ibcon#enter sib2, iclass 5, count 0 2006.173.10:17:53.82#ibcon#flushed, iclass 5, count 0 2006.173.10:17:53.82#ibcon#about to write, iclass 5, count 0 2006.173.10:17:53.82#ibcon#wrote, iclass 5, count 0 2006.173.10:17:53.82#ibcon#about to read 3, iclass 5, count 0 2006.173.10:17:53.84#ibcon#read 3, iclass 5, count 0 2006.173.10:17:53.84#ibcon#about to read 4, iclass 5, count 0 2006.173.10:17:53.84#ibcon#read 4, iclass 5, count 0 2006.173.10:17:53.84#ibcon#about to read 5, iclass 5, count 0 2006.173.10:17:53.84#ibcon#read 5, iclass 5, count 0 2006.173.10:17:53.84#ibcon#about to read 6, iclass 5, count 0 2006.173.10:17:53.84#ibcon#read 6, iclass 5, count 0 2006.173.10:17:53.84#ibcon#end of sib2, iclass 5, count 0 2006.173.10:17:53.84#ibcon#*mode == 0, iclass 5, count 0 2006.173.10:17:53.84#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.10:17:53.84#ibcon#[25=USB\r\n] 2006.173.10:17:53.84#ibcon#*before write, iclass 5, count 0 2006.173.10:17:53.84#ibcon#enter sib2, iclass 5, count 0 2006.173.10:17:53.84#ibcon#flushed, iclass 5, count 0 2006.173.10:17:53.84#ibcon#about to write, iclass 5, count 0 2006.173.10:17:53.84#ibcon#wrote, iclass 5, count 0 2006.173.10:17:53.84#ibcon#about to read 3, iclass 5, count 0 2006.173.10:17:53.87#ibcon#read 3, iclass 5, count 0 2006.173.10:17:53.87#ibcon#about to read 4, iclass 5, count 0 2006.173.10:17:53.87#ibcon#read 4, iclass 5, count 0 2006.173.10:17:53.87#ibcon#about to read 5, iclass 5, count 0 2006.173.10:17:53.87#ibcon#read 5, iclass 5, count 0 2006.173.10:17:53.87#ibcon#about to read 6, iclass 5, count 0 2006.173.10:17:53.87#ibcon#read 6, iclass 5, count 0 2006.173.10:17:53.87#ibcon#end of sib2, iclass 5, count 0 2006.173.10:17:53.87#ibcon#*after write, iclass 5, count 0 2006.173.10:17:53.87#ibcon#*before return 0, iclass 5, count 0 2006.173.10:17:53.87#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.10:17:53.87#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.10:17:53.87#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.10:17:53.87#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.10:17:53.87$vck44/valo=3,564.99 2006.173.10:17:53.87#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.10:17:53.87#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.10:17:53.87#ibcon#ireg 17 cls_cnt 0 2006.173.10:17:53.87#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.10:17:53.87#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.10:17:53.87#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.10:17:53.87#ibcon#enter wrdev, iclass 7, count 0 2006.173.10:17:53.87#ibcon#first serial, iclass 7, count 0 2006.173.10:17:53.87#ibcon#enter sib2, iclass 7, count 0 2006.173.10:17:53.87#ibcon#flushed, iclass 7, count 0 2006.173.10:17:53.87#ibcon#about to write, iclass 7, count 0 2006.173.10:17:53.87#ibcon#wrote, iclass 7, count 0 2006.173.10:17:53.87#ibcon#about to read 3, iclass 7, count 0 2006.173.10:17:53.89#ibcon#read 3, iclass 7, count 0 2006.173.10:17:53.89#ibcon#about to read 4, iclass 7, count 0 2006.173.10:17:53.89#ibcon#read 4, iclass 7, count 0 2006.173.10:17:53.89#ibcon#about to read 5, iclass 7, count 0 2006.173.10:17:53.89#ibcon#read 5, iclass 7, count 0 2006.173.10:17:53.89#ibcon#about to read 6, iclass 7, count 0 2006.173.10:17:53.89#ibcon#read 6, iclass 7, count 0 2006.173.10:17:53.89#ibcon#end of sib2, iclass 7, count 0 2006.173.10:17:53.89#ibcon#*mode == 0, iclass 7, count 0 2006.173.10:17:53.89#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.10:17:53.89#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.10:17:53.89#ibcon#*before write, iclass 7, count 0 2006.173.10:17:53.89#ibcon#enter sib2, iclass 7, count 0 2006.173.10:17:53.89#ibcon#flushed, iclass 7, count 0 2006.173.10:17:53.89#ibcon#about to write, iclass 7, count 0 2006.173.10:17:53.89#ibcon#wrote, iclass 7, count 0 2006.173.10:17:53.89#ibcon#about to read 3, iclass 7, count 0 2006.173.10:17:53.93#ibcon#read 3, iclass 7, count 0 2006.173.10:17:53.93#ibcon#about to read 4, iclass 7, count 0 2006.173.10:17:53.93#ibcon#read 4, iclass 7, count 0 2006.173.10:17:53.93#ibcon#about to read 5, iclass 7, count 0 2006.173.10:17:53.93#ibcon#read 5, iclass 7, count 0 2006.173.10:17:53.93#ibcon#about to read 6, iclass 7, count 0 2006.173.10:17:53.93#ibcon#read 6, iclass 7, count 0 2006.173.10:17:53.93#ibcon#end of sib2, iclass 7, count 0 2006.173.10:17:53.93#ibcon#*after write, iclass 7, count 0 2006.173.10:17:53.93#ibcon#*before return 0, iclass 7, count 0 2006.173.10:17:53.93#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.10:17:53.93#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.10:17:53.93#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.10:17:53.93#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.10:17:53.93$vck44/va=3,5 2006.173.10:17:53.93#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.10:17:53.93#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.10:17:53.93#ibcon#ireg 11 cls_cnt 2 2006.173.10:17:53.93#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.10:17:53.99#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.10:17:53.99#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.10:17:53.99#ibcon#enter wrdev, iclass 11, count 2 2006.173.10:17:53.99#ibcon#first serial, iclass 11, count 2 2006.173.10:17:53.99#ibcon#enter sib2, iclass 11, count 2 2006.173.10:17:53.99#ibcon#flushed, iclass 11, count 2 2006.173.10:17:53.99#ibcon#about to write, iclass 11, count 2 2006.173.10:17:53.99#ibcon#wrote, iclass 11, count 2 2006.173.10:17:53.99#ibcon#about to read 3, iclass 11, count 2 2006.173.10:17:54.01#ibcon#read 3, iclass 11, count 2 2006.173.10:17:54.01#ibcon#about to read 4, iclass 11, count 2 2006.173.10:17:54.01#ibcon#read 4, iclass 11, count 2 2006.173.10:17:54.01#ibcon#about to read 5, iclass 11, count 2 2006.173.10:17:54.01#ibcon#read 5, iclass 11, count 2 2006.173.10:17:54.01#ibcon#about to read 6, iclass 11, count 2 2006.173.10:17:54.01#ibcon#read 6, iclass 11, count 2 2006.173.10:17:54.01#ibcon#end of sib2, iclass 11, count 2 2006.173.10:17:54.01#ibcon#*mode == 0, iclass 11, count 2 2006.173.10:17:54.01#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.10:17:54.01#ibcon#[25=AT03-05\r\n] 2006.173.10:17:54.01#ibcon#*before write, iclass 11, count 2 2006.173.10:17:54.01#ibcon#enter sib2, iclass 11, count 2 2006.173.10:17:54.01#ibcon#flushed, iclass 11, count 2 2006.173.10:17:54.01#ibcon#about to write, iclass 11, count 2 2006.173.10:17:54.01#ibcon#wrote, iclass 11, count 2 2006.173.10:17:54.01#ibcon#about to read 3, iclass 11, count 2 2006.173.10:17:54.04#ibcon#read 3, iclass 11, count 2 2006.173.10:17:54.04#ibcon#about to read 4, iclass 11, count 2 2006.173.10:17:54.04#ibcon#read 4, iclass 11, count 2 2006.173.10:17:54.04#ibcon#about to read 5, iclass 11, count 2 2006.173.10:17:54.04#ibcon#read 5, iclass 11, count 2 2006.173.10:17:54.04#ibcon#about to read 6, iclass 11, count 2 2006.173.10:17:54.04#ibcon#read 6, iclass 11, count 2 2006.173.10:17:54.04#ibcon#end of sib2, iclass 11, count 2 2006.173.10:17:54.04#ibcon#*after write, iclass 11, count 2 2006.173.10:17:54.04#ibcon#*before return 0, iclass 11, count 2 2006.173.10:17:54.04#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.10:17:54.04#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.10:17:54.04#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.10:17:54.04#ibcon#ireg 7 cls_cnt 0 2006.173.10:17:54.04#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.10:17:54.16#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.10:17:54.16#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.10:17:54.16#ibcon#enter wrdev, iclass 11, count 0 2006.173.10:17:54.16#ibcon#first serial, iclass 11, count 0 2006.173.10:17:54.16#ibcon#enter sib2, iclass 11, count 0 2006.173.10:17:54.16#ibcon#flushed, iclass 11, count 0 2006.173.10:17:54.16#ibcon#about to write, iclass 11, count 0 2006.173.10:17:54.16#ibcon#wrote, iclass 11, count 0 2006.173.10:17:54.16#ibcon#about to read 3, iclass 11, count 0 2006.173.10:17:54.18#ibcon#read 3, iclass 11, count 0 2006.173.10:17:54.18#ibcon#about to read 4, iclass 11, count 0 2006.173.10:17:54.18#ibcon#read 4, iclass 11, count 0 2006.173.10:17:54.18#ibcon#about to read 5, iclass 11, count 0 2006.173.10:17:54.18#ibcon#read 5, iclass 11, count 0 2006.173.10:17:54.18#ibcon#about to read 6, iclass 11, count 0 2006.173.10:17:54.18#ibcon#read 6, iclass 11, count 0 2006.173.10:17:54.18#ibcon#end of sib2, iclass 11, count 0 2006.173.10:17:54.18#ibcon#*mode == 0, iclass 11, count 0 2006.173.10:17:54.18#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.10:17:54.18#ibcon#[25=USB\r\n] 2006.173.10:17:54.18#ibcon#*before write, iclass 11, count 0 2006.173.10:17:54.18#ibcon#enter sib2, iclass 11, count 0 2006.173.10:17:54.18#ibcon#flushed, iclass 11, count 0 2006.173.10:17:54.18#ibcon#about to write, iclass 11, count 0 2006.173.10:17:54.18#ibcon#wrote, iclass 11, count 0 2006.173.10:17:54.18#ibcon#about to read 3, iclass 11, count 0 2006.173.10:17:54.21#ibcon#read 3, iclass 11, count 0 2006.173.10:17:54.21#ibcon#about to read 4, iclass 11, count 0 2006.173.10:17:54.21#ibcon#read 4, iclass 11, count 0 2006.173.10:17:54.21#ibcon#about to read 5, iclass 11, count 0 2006.173.10:17:54.21#ibcon#read 5, iclass 11, count 0 2006.173.10:17:54.21#ibcon#about to read 6, iclass 11, count 0 2006.173.10:17:54.21#ibcon#read 6, iclass 11, count 0 2006.173.10:17:54.21#ibcon#end of sib2, iclass 11, count 0 2006.173.10:17:54.21#ibcon#*after write, iclass 11, count 0 2006.173.10:17:54.21#ibcon#*before return 0, iclass 11, count 0 2006.173.10:17:54.21#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.10:17:54.21#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.10:17:54.21#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.10:17:54.21#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.10:17:54.21$vck44/valo=4,624.99 2006.173.10:17:54.21#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.10:17:54.21#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.10:17:54.21#ibcon#ireg 17 cls_cnt 0 2006.173.10:17:54.21#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.10:17:54.21#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.10:17:54.21#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.10:17:54.21#ibcon#enter wrdev, iclass 13, count 0 2006.173.10:17:54.21#ibcon#first serial, iclass 13, count 0 2006.173.10:17:54.21#ibcon#enter sib2, iclass 13, count 0 2006.173.10:17:54.21#ibcon#flushed, iclass 13, count 0 2006.173.10:17:54.21#ibcon#about to write, iclass 13, count 0 2006.173.10:17:54.21#ibcon#wrote, iclass 13, count 0 2006.173.10:17:54.21#ibcon#about to read 3, iclass 13, count 0 2006.173.10:17:54.23#ibcon#read 3, iclass 13, count 0 2006.173.10:17:54.23#ibcon#about to read 4, iclass 13, count 0 2006.173.10:17:54.23#ibcon#read 4, iclass 13, count 0 2006.173.10:17:54.23#ibcon#about to read 5, iclass 13, count 0 2006.173.10:17:54.23#ibcon#read 5, iclass 13, count 0 2006.173.10:17:54.23#ibcon#about to read 6, iclass 13, count 0 2006.173.10:17:54.23#ibcon#read 6, iclass 13, count 0 2006.173.10:17:54.23#ibcon#end of sib2, iclass 13, count 0 2006.173.10:17:54.23#ibcon#*mode == 0, iclass 13, count 0 2006.173.10:17:54.23#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.10:17:54.23#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.10:17:54.23#ibcon#*before write, iclass 13, count 0 2006.173.10:17:54.23#ibcon#enter sib2, iclass 13, count 0 2006.173.10:17:54.23#ibcon#flushed, iclass 13, count 0 2006.173.10:17:54.23#ibcon#about to write, iclass 13, count 0 2006.173.10:17:54.23#ibcon#wrote, iclass 13, count 0 2006.173.10:17:54.23#ibcon#about to read 3, iclass 13, count 0 2006.173.10:17:54.27#ibcon#read 3, iclass 13, count 0 2006.173.10:17:54.27#ibcon#about to read 4, iclass 13, count 0 2006.173.10:17:54.27#ibcon#read 4, iclass 13, count 0 2006.173.10:17:54.27#ibcon#about to read 5, iclass 13, count 0 2006.173.10:17:54.27#ibcon#read 5, iclass 13, count 0 2006.173.10:17:54.27#ibcon#about to read 6, iclass 13, count 0 2006.173.10:17:54.27#ibcon#read 6, iclass 13, count 0 2006.173.10:17:54.27#ibcon#end of sib2, iclass 13, count 0 2006.173.10:17:54.27#ibcon#*after write, iclass 13, count 0 2006.173.10:17:54.27#ibcon#*before return 0, iclass 13, count 0 2006.173.10:17:54.27#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.10:17:54.27#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.10:17:54.27#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.10:17:54.27#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.10:17:54.27$vck44/va=4,6 2006.173.10:17:54.27#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.10:17:54.27#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.10:17:54.27#ibcon#ireg 11 cls_cnt 2 2006.173.10:17:54.27#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.10:17:54.33#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.10:17:54.33#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.10:17:54.33#ibcon#enter wrdev, iclass 15, count 2 2006.173.10:17:54.33#ibcon#first serial, iclass 15, count 2 2006.173.10:17:54.33#ibcon#enter sib2, iclass 15, count 2 2006.173.10:17:54.33#ibcon#flushed, iclass 15, count 2 2006.173.10:17:54.33#ibcon#about to write, iclass 15, count 2 2006.173.10:17:54.33#ibcon#wrote, iclass 15, count 2 2006.173.10:17:54.33#ibcon#about to read 3, iclass 15, count 2 2006.173.10:17:54.35#ibcon#read 3, iclass 15, count 2 2006.173.10:17:54.35#ibcon#about to read 4, iclass 15, count 2 2006.173.10:17:54.35#ibcon#read 4, iclass 15, count 2 2006.173.10:17:54.35#ibcon#about to read 5, iclass 15, count 2 2006.173.10:17:54.35#ibcon#read 5, iclass 15, count 2 2006.173.10:17:54.35#ibcon#about to read 6, iclass 15, count 2 2006.173.10:17:54.35#ibcon#read 6, iclass 15, count 2 2006.173.10:17:54.35#ibcon#end of sib2, iclass 15, count 2 2006.173.10:17:54.35#ibcon#*mode == 0, iclass 15, count 2 2006.173.10:17:54.35#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.10:17:54.35#ibcon#[25=AT04-06\r\n] 2006.173.10:17:54.35#ibcon#*before write, iclass 15, count 2 2006.173.10:17:54.35#ibcon#enter sib2, iclass 15, count 2 2006.173.10:17:54.35#ibcon#flushed, iclass 15, count 2 2006.173.10:17:54.35#ibcon#about to write, iclass 15, count 2 2006.173.10:17:54.35#ibcon#wrote, iclass 15, count 2 2006.173.10:17:54.35#ibcon#about to read 3, iclass 15, count 2 2006.173.10:17:54.38#ibcon#read 3, iclass 15, count 2 2006.173.10:17:54.38#ibcon#about to read 4, iclass 15, count 2 2006.173.10:17:54.38#ibcon#read 4, iclass 15, count 2 2006.173.10:17:54.38#ibcon#about to read 5, iclass 15, count 2 2006.173.10:17:54.38#ibcon#read 5, iclass 15, count 2 2006.173.10:17:54.38#ibcon#about to read 6, iclass 15, count 2 2006.173.10:17:54.38#ibcon#read 6, iclass 15, count 2 2006.173.10:17:54.38#ibcon#end of sib2, iclass 15, count 2 2006.173.10:17:54.38#ibcon#*after write, iclass 15, count 2 2006.173.10:17:54.38#ibcon#*before return 0, iclass 15, count 2 2006.173.10:17:54.38#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.10:17:54.38#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.10:17:54.38#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.10:17:54.38#ibcon#ireg 7 cls_cnt 0 2006.173.10:17:54.38#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.10:17:54.50#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.10:17:54.50#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.10:17:54.50#ibcon#enter wrdev, iclass 15, count 0 2006.173.10:17:54.50#ibcon#first serial, iclass 15, count 0 2006.173.10:17:54.50#ibcon#enter sib2, iclass 15, count 0 2006.173.10:17:54.50#ibcon#flushed, iclass 15, count 0 2006.173.10:17:54.50#ibcon#about to write, iclass 15, count 0 2006.173.10:17:54.50#ibcon#wrote, iclass 15, count 0 2006.173.10:17:54.50#ibcon#about to read 3, iclass 15, count 0 2006.173.10:17:54.52#ibcon#read 3, iclass 15, count 0 2006.173.10:17:54.52#ibcon#about to read 4, iclass 15, count 0 2006.173.10:17:54.52#ibcon#read 4, iclass 15, count 0 2006.173.10:17:54.52#ibcon#about to read 5, iclass 15, count 0 2006.173.10:17:54.52#ibcon#read 5, iclass 15, count 0 2006.173.10:17:54.52#ibcon#about to read 6, iclass 15, count 0 2006.173.10:17:54.52#ibcon#read 6, iclass 15, count 0 2006.173.10:17:54.52#ibcon#end of sib2, iclass 15, count 0 2006.173.10:17:54.52#ibcon#*mode == 0, iclass 15, count 0 2006.173.10:17:54.52#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.10:17:54.52#ibcon#[25=USB\r\n] 2006.173.10:17:54.52#ibcon#*before write, iclass 15, count 0 2006.173.10:17:54.52#ibcon#enter sib2, iclass 15, count 0 2006.173.10:17:54.52#ibcon#flushed, iclass 15, count 0 2006.173.10:17:54.52#ibcon#about to write, iclass 15, count 0 2006.173.10:17:54.52#ibcon#wrote, iclass 15, count 0 2006.173.10:17:54.52#ibcon#about to read 3, iclass 15, count 0 2006.173.10:17:54.55#ibcon#read 3, iclass 15, count 0 2006.173.10:17:54.55#ibcon#about to read 4, iclass 15, count 0 2006.173.10:17:54.55#ibcon#read 4, iclass 15, count 0 2006.173.10:17:54.55#ibcon#about to read 5, iclass 15, count 0 2006.173.10:17:54.55#ibcon#read 5, iclass 15, count 0 2006.173.10:17:54.55#ibcon#about to read 6, iclass 15, count 0 2006.173.10:17:54.55#ibcon#read 6, iclass 15, count 0 2006.173.10:17:54.55#ibcon#end of sib2, iclass 15, count 0 2006.173.10:17:54.55#ibcon#*after write, iclass 15, count 0 2006.173.10:17:54.55#ibcon#*before return 0, iclass 15, count 0 2006.173.10:17:54.55#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.10:17:54.55#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.10:17:54.55#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.10:17:54.55#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.10:17:54.55$vck44/valo=5,734.99 2006.173.10:17:54.55#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.10:17:54.55#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.10:17:54.55#ibcon#ireg 17 cls_cnt 0 2006.173.10:17:54.55#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.10:17:54.55#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.10:17:54.55#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.10:17:54.55#ibcon#enter wrdev, iclass 17, count 0 2006.173.10:17:54.55#ibcon#first serial, iclass 17, count 0 2006.173.10:17:54.55#ibcon#enter sib2, iclass 17, count 0 2006.173.10:17:54.55#ibcon#flushed, iclass 17, count 0 2006.173.10:17:54.55#ibcon#about to write, iclass 17, count 0 2006.173.10:17:54.55#ibcon#wrote, iclass 17, count 0 2006.173.10:17:54.55#ibcon#about to read 3, iclass 17, count 0 2006.173.10:17:54.57#ibcon#read 3, iclass 17, count 0 2006.173.10:17:54.57#ibcon#about to read 4, iclass 17, count 0 2006.173.10:17:54.57#ibcon#read 4, iclass 17, count 0 2006.173.10:17:54.57#ibcon#about to read 5, iclass 17, count 0 2006.173.10:17:54.57#ibcon#read 5, iclass 17, count 0 2006.173.10:17:54.57#ibcon#about to read 6, iclass 17, count 0 2006.173.10:17:54.57#ibcon#read 6, iclass 17, count 0 2006.173.10:17:54.57#ibcon#end of sib2, iclass 17, count 0 2006.173.10:17:54.57#ibcon#*mode == 0, iclass 17, count 0 2006.173.10:17:54.57#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.10:17:54.57#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.10:17:54.57#ibcon#*before write, iclass 17, count 0 2006.173.10:17:54.57#ibcon#enter sib2, iclass 17, count 0 2006.173.10:17:54.57#ibcon#flushed, iclass 17, count 0 2006.173.10:17:54.57#ibcon#about to write, iclass 17, count 0 2006.173.10:17:54.57#ibcon#wrote, iclass 17, count 0 2006.173.10:17:54.57#ibcon#about to read 3, iclass 17, count 0 2006.173.10:17:54.61#ibcon#read 3, iclass 17, count 0 2006.173.10:17:54.61#ibcon#about to read 4, iclass 17, count 0 2006.173.10:17:54.61#ibcon#read 4, iclass 17, count 0 2006.173.10:17:54.61#ibcon#about to read 5, iclass 17, count 0 2006.173.10:17:54.61#ibcon#read 5, iclass 17, count 0 2006.173.10:17:54.61#ibcon#about to read 6, iclass 17, count 0 2006.173.10:17:54.61#ibcon#read 6, iclass 17, count 0 2006.173.10:17:54.61#ibcon#end of sib2, iclass 17, count 0 2006.173.10:17:54.61#ibcon#*after write, iclass 17, count 0 2006.173.10:17:54.61#ibcon#*before return 0, iclass 17, count 0 2006.173.10:17:54.61#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.10:17:54.61#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.10:17:54.61#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.10:17:54.61#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.10:17:54.61$vck44/va=5,4 2006.173.10:17:54.61#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.10:17:54.61#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.10:17:54.61#ibcon#ireg 11 cls_cnt 2 2006.173.10:17:54.61#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.10:17:54.67#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.10:17:54.67#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.10:17:54.67#ibcon#enter wrdev, iclass 19, count 2 2006.173.10:17:54.67#ibcon#first serial, iclass 19, count 2 2006.173.10:17:54.67#ibcon#enter sib2, iclass 19, count 2 2006.173.10:17:54.67#ibcon#flushed, iclass 19, count 2 2006.173.10:17:54.67#ibcon#about to write, iclass 19, count 2 2006.173.10:17:54.67#ibcon#wrote, iclass 19, count 2 2006.173.10:17:54.67#ibcon#about to read 3, iclass 19, count 2 2006.173.10:17:54.69#ibcon#read 3, iclass 19, count 2 2006.173.10:17:54.69#ibcon#about to read 4, iclass 19, count 2 2006.173.10:17:54.69#ibcon#read 4, iclass 19, count 2 2006.173.10:17:54.69#ibcon#about to read 5, iclass 19, count 2 2006.173.10:17:54.69#ibcon#read 5, iclass 19, count 2 2006.173.10:17:54.69#ibcon#about to read 6, iclass 19, count 2 2006.173.10:17:54.69#ibcon#read 6, iclass 19, count 2 2006.173.10:17:54.69#ibcon#end of sib2, iclass 19, count 2 2006.173.10:17:54.69#ibcon#*mode == 0, iclass 19, count 2 2006.173.10:17:54.69#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.10:17:54.69#ibcon#[25=AT05-04\r\n] 2006.173.10:17:54.69#ibcon#*before write, iclass 19, count 2 2006.173.10:17:54.69#ibcon#enter sib2, iclass 19, count 2 2006.173.10:17:54.69#ibcon#flushed, iclass 19, count 2 2006.173.10:17:54.69#ibcon#about to write, iclass 19, count 2 2006.173.10:17:54.69#ibcon#wrote, iclass 19, count 2 2006.173.10:17:54.69#ibcon#about to read 3, iclass 19, count 2 2006.173.10:17:54.72#ibcon#read 3, iclass 19, count 2 2006.173.10:17:54.72#ibcon#about to read 4, iclass 19, count 2 2006.173.10:17:54.72#ibcon#read 4, iclass 19, count 2 2006.173.10:17:54.72#ibcon#about to read 5, iclass 19, count 2 2006.173.10:17:54.72#ibcon#read 5, iclass 19, count 2 2006.173.10:17:54.72#ibcon#about to read 6, iclass 19, count 2 2006.173.10:17:54.72#ibcon#read 6, iclass 19, count 2 2006.173.10:17:54.72#ibcon#end of sib2, iclass 19, count 2 2006.173.10:17:54.72#ibcon#*after write, iclass 19, count 2 2006.173.10:17:54.72#ibcon#*before return 0, iclass 19, count 2 2006.173.10:17:54.72#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.10:17:54.72#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.10:17:54.72#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.10:17:54.72#ibcon#ireg 7 cls_cnt 0 2006.173.10:17:54.72#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.10:17:54.84#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.10:17:54.84#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.10:17:54.84#ibcon#enter wrdev, iclass 19, count 0 2006.173.10:17:54.84#ibcon#first serial, iclass 19, count 0 2006.173.10:17:54.84#ibcon#enter sib2, iclass 19, count 0 2006.173.10:17:54.84#ibcon#flushed, iclass 19, count 0 2006.173.10:17:54.84#ibcon#about to write, iclass 19, count 0 2006.173.10:17:54.84#ibcon#wrote, iclass 19, count 0 2006.173.10:17:54.84#ibcon#about to read 3, iclass 19, count 0 2006.173.10:17:54.86#ibcon#read 3, iclass 19, count 0 2006.173.10:17:54.86#ibcon#about to read 4, iclass 19, count 0 2006.173.10:17:54.86#ibcon#read 4, iclass 19, count 0 2006.173.10:17:54.86#ibcon#about to read 5, iclass 19, count 0 2006.173.10:17:54.86#ibcon#read 5, iclass 19, count 0 2006.173.10:17:54.86#ibcon#about to read 6, iclass 19, count 0 2006.173.10:17:54.86#ibcon#read 6, iclass 19, count 0 2006.173.10:17:54.86#ibcon#end of sib2, iclass 19, count 0 2006.173.10:17:54.86#ibcon#*mode == 0, iclass 19, count 0 2006.173.10:17:54.86#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.10:17:54.86#ibcon#[25=USB\r\n] 2006.173.10:17:54.86#ibcon#*before write, iclass 19, count 0 2006.173.10:17:54.86#ibcon#enter sib2, iclass 19, count 0 2006.173.10:17:54.86#ibcon#flushed, iclass 19, count 0 2006.173.10:17:54.86#ibcon#about to write, iclass 19, count 0 2006.173.10:17:54.86#ibcon#wrote, iclass 19, count 0 2006.173.10:17:54.86#ibcon#about to read 3, iclass 19, count 0 2006.173.10:17:54.89#ibcon#read 3, iclass 19, count 0 2006.173.10:17:54.89#ibcon#about to read 4, iclass 19, count 0 2006.173.10:17:54.89#ibcon#read 4, iclass 19, count 0 2006.173.10:17:54.89#ibcon#about to read 5, iclass 19, count 0 2006.173.10:17:54.89#ibcon#read 5, iclass 19, count 0 2006.173.10:17:54.89#ibcon#about to read 6, iclass 19, count 0 2006.173.10:17:54.89#ibcon#read 6, iclass 19, count 0 2006.173.10:17:54.89#ibcon#end of sib2, iclass 19, count 0 2006.173.10:17:54.89#ibcon#*after write, iclass 19, count 0 2006.173.10:17:54.89#ibcon#*before return 0, iclass 19, count 0 2006.173.10:17:54.89#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.10:17:54.89#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.10:17:54.89#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.10:17:54.89#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.10:17:54.89$vck44/valo=6,814.99 2006.173.10:17:54.89#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.10:17:54.89#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.10:17:54.89#ibcon#ireg 17 cls_cnt 0 2006.173.10:17:54.89#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.10:17:54.89#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.10:17:54.89#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.10:17:54.89#ibcon#enter wrdev, iclass 21, count 0 2006.173.10:17:54.89#ibcon#first serial, iclass 21, count 0 2006.173.10:17:54.89#ibcon#enter sib2, iclass 21, count 0 2006.173.10:17:54.89#ibcon#flushed, iclass 21, count 0 2006.173.10:17:54.89#ibcon#about to write, iclass 21, count 0 2006.173.10:17:54.89#ibcon#wrote, iclass 21, count 0 2006.173.10:17:54.89#ibcon#about to read 3, iclass 21, count 0 2006.173.10:17:54.91#ibcon#read 3, iclass 21, count 0 2006.173.10:17:54.91#ibcon#about to read 4, iclass 21, count 0 2006.173.10:17:54.91#ibcon#read 4, iclass 21, count 0 2006.173.10:17:54.91#ibcon#about to read 5, iclass 21, count 0 2006.173.10:17:54.91#ibcon#read 5, iclass 21, count 0 2006.173.10:17:54.91#ibcon#about to read 6, iclass 21, count 0 2006.173.10:17:54.91#ibcon#read 6, iclass 21, count 0 2006.173.10:17:54.91#ibcon#end of sib2, iclass 21, count 0 2006.173.10:17:54.91#ibcon#*mode == 0, iclass 21, count 0 2006.173.10:17:54.91#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.10:17:54.91#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.10:17:54.91#ibcon#*before write, iclass 21, count 0 2006.173.10:17:54.91#ibcon#enter sib2, iclass 21, count 0 2006.173.10:17:54.91#ibcon#flushed, iclass 21, count 0 2006.173.10:17:54.91#ibcon#about to write, iclass 21, count 0 2006.173.10:17:54.91#ibcon#wrote, iclass 21, count 0 2006.173.10:17:54.91#ibcon#about to read 3, iclass 21, count 0 2006.173.10:17:54.95#ibcon#read 3, iclass 21, count 0 2006.173.10:17:54.95#ibcon#about to read 4, iclass 21, count 0 2006.173.10:17:54.95#ibcon#read 4, iclass 21, count 0 2006.173.10:17:54.95#ibcon#about to read 5, iclass 21, count 0 2006.173.10:17:54.95#ibcon#read 5, iclass 21, count 0 2006.173.10:17:54.95#ibcon#about to read 6, iclass 21, count 0 2006.173.10:17:54.95#ibcon#read 6, iclass 21, count 0 2006.173.10:17:54.95#ibcon#end of sib2, iclass 21, count 0 2006.173.10:17:54.95#ibcon#*after write, iclass 21, count 0 2006.173.10:17:54.95#ibcon#*before return 0, iclass 21, count 0 2006.173.10:17:54.95#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.10:17:54.95#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.10:17:54.95#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.10:17:54.95#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.10:17:54.95$vck44/va=6,3 2006.173.10:17:54.95#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.10:17:54.95#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.10:17:54.95#ibcon#ireg 11 cls_cnt 2 2006.173.10:17:54.95#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.10:17:55.01#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.10:17:55.01#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.10:17:55.01#ibcon#enter wrdev, iclass 23, count 2 2006.173.10:17:55.01#ibcon#first serial, iclass 23, count 2 2006.173.10:17:55.01#ibcon#enter sib2, iclass 23, count 2 2006.173.10:17:55.01#ibcon#flushed, iclass 23, count 2 2006.173.10:17:55.01#ibcon#about to write, iclass 23, count 2 2006.173.10:17:55.01#ibcon#wrote, iclass 23, count 2 2006.173.10:17:55.01#ibcon#about to read 3, iclass 23, count 2 2006.173.10:17:55.03#ibcon#read 3, iclass 23, count 2 2006.173.10:17:55.03#ibcon#about to read 4, iclass 23, count 2 2006.173.10:17:55.03#ibcon#read 4, iclass 23, count 2 2006.173.10:17:55.03#ibcon#about to read 5, iclass 23, count 2 2006.173.10:17:55.03#ibcon#read 5, iclass 23, count 2 2006.173.10:17:55.03#ibcon#about to read 6, iclass 23, count 2 2006.173.10:17:55.03#ibcon#read 6, iclass 23, count 2 2006.173.10:17:55.03#ibcon#end of sib2, iclass 23, count 2 2006.173.10:17:55.03#ibcon#*mode == 0, iclass 23, count 2 2006.173.10:17:55.03#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.10:17:55.03#ibcon#[25=AT06-03\r\n] 2006.173.10:17:55.03#ibcon#*before write, iclass 23, count 2 2006.173.10:17:55.03#ibcon#enter sib2, iclass 23, count 2 2006.173.10:17:55.03#ibcon#flushed, iclass 23, count 2 2006.173.10:17:55.03#ibcon#about to write, iclass 23, count 2 2006.173.10:17:55.03#ibcon#wrote, iclass 23, count 2 2006.173.10:17:55.03#ibcon#about to read 3, iclass 23, count 2 2006.173.10:17:55.06#ibcon#read 3, iclass 23, count 2 2006.173.10:17:55.06#ibcon#about to read 4, iclass 23, count 2 2006.173.10:17:55.06#ibcon#read 4, iclass 23, count 2 2006.173.10:17:55.06#ibcon#about to read 5, iclass 23, count 2 2006.173.10:17:55.06#ibcon#read 5, iclass 23, count 2 2006.173.10:17:55.06#ibcon#about to read 6, iclass 23, count 2 2006.173.10:17:55.06#ibcon#read 6, iclass 23, count 2 2006.173.10:17:55.06#ibcon#end of sib2, iclass 23, count 2 2006.173.10:17:55.06#ibcon#*after write, iclass 23, count 2 2006.173.10:17:55.06#ibcon#*before return 0, iclass 23, count 2 2006.173.10:17:55.06#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.10:17:55.06#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.10:17:55.06#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.10:17:55.06#ibcon#ireg 7 cls_cnt 0 2006.173.10:17:55.06#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.10:17:55.18#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.10:17:55.18#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.10:17:55.18#ibcon#enter wrdev, iclass 23, count 0 2006.173.10:17:55.18#ibcon#first serial, iclass 23, count 0 2006.173.10:17:55.18#ibcon#enter sib2, iclass 23, count 0 2006.173.10:17:55.18#ibcon#flushed, iclass 23, count 0 2006.173.10:17:55.18#ibcon#about to write, iclass 23, count 0 2006.173.10:17:55.18#ibcon#wrote, iclass 23, count 0 2006.173.10:17:55.18#ibcon#about to read 3, iclass 23, count 0 2006.173.10:17:55.20#ibcon#read 3, iclass 23, count 0 2006.173.10:17:55.20#ibcon#about to read 4, iclass 23, count 0 2006.173.10:17:55.20#ibcon#read 4, iclass 23, count 0 2006.173.10:17:55.20#ibcon#about to read 5, iclass 23, count 0 2006.173.10:17:55.20#ibcon#read 5, iclass 23, count 0 2006.173.10:17:55.20#ibcon#about to read 6, iclass 23, count 0 2006.173.10:17:55.20#ibcon#read 6, iclass 23, count 0 2006.173.10:17:55.20#ibcon#end of sib2, iclass 23, count 0 2006.173.10:17:55.20#ibcon#*mode == 0, iclass 23, count 0 2006.173.10:17:55.20#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.10:17:55.20#ibcon#[25=USB\r\n] 2006.173.10:17:55.20#ibcon#*before write, iclass 23, count 0 2006.173.10:17:55.20#ibcon#enter sib2, iclass 23, count 0 2006.173.10:17:55.20#ibcon#flushed, iclass 23, count 0 2006.173.10:17:55.20#ibcon#about to write, iclass 23, count 0 2006.173.10:17:55.20#ibcon#wrote, iclass 23, count 0 2006.173.10:17:55.20#ibcon#about to read 3, iclass 23, count 0 2006.173.10:17:55.23#ibcon#read 3, iclass 23, count 0 2006.173.10:17:55.23#ibcon#about to read 4, iclass 23, count 0 2006.173.10:17:55.23#ibcon#read 4, iclass 23, count 0 2006.173.10:17:55.23#ibcon#about to read 5, iclass 23, count 0 2006.173.10:17:55.23#ibcon#read 5, iclass 23, count 0 2006.173.10:17:55.23#ibcon#about to read 6, iclass 23, count 0 2006.173.10:17:55.23#ibcon#read 6, iclass 23, count 0 2006.173.10:17:55.23#ibcon#end of sib2, iclass 23, count 0 2006.173.10:17:55.23#ibcon#*after write, iclass 23, count 0 2006.173.10:17:55.23#ibcon#*before return 0, iclass 23, count 0 2006.173.10:17:55.23#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.10:17:55.23#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.10:17:55.23#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.10:17:55.23#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.10:17:55.23$vck44/valo=7,864.99 2006.173.10:17:55.23#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.10:17:55.23#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.10:17:55.23#ibcon#ireg 17 cls_cnt 0 2006.173.10:17:55.23#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.10:17:55.23#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.10:17:55.23#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.10:17:55.23#ibcon#enter wrdev, iclass 25, count 0 2006.173.10:17:55.23#ibcon#first serial, iclass 25, count 0 2006.173.10:17:55.23#ibcon#enter sib2, iclass 25, count 0 2006.173.10:17:55.23#ibcon#flushed, iclass 25, count 0 2006.173.10:17:55.23#ibcon#about to write, iclass 25, count 0 2006.173.10:17:55.23#ibcon#wrote, iclass 25, count 0 2006.173.10:17:55.23#ibcon#about to read 3, iclass 25, count 0 2006.173.10:17:55.25#ibcon#read 3, iclass 25, count 0 2006.173.10:17:55.25#ibcon#about to read 4, iclass 25, count 0 2006.173.10:17:55.25#ibcon#read 4, iclass 25, count 0 2006.173.10:17:55.25#ibcon#about to read 5, iclass 25, count 0 2006.173.10:17:55.25#ibcon#read 5, iclass 25, count 0 2006.173.10:17:55.25#ibcon#about to read 6, iclass 25, count 0 2006.173.10:17:55.25#ibcon#read 6, iclass 25, count 0 2006.173.10:17:55.25#ibcon#end of sib2, iclass 25, count 0 2006.173.10:17:55.25#ibcon#*mode == 0, iclass 25, count 0 2006.173.10:17:55.25#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.10:17:55.25#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.10:17:55.25#ibcon#*before write, iclass 25, count 0 2006.173.10:17:55.25#ibcon#enter sib2, iclass 25, count 0 2006.173.10:17:55.25#ibcon#flushed, iclass 25, count 0 2006.173.10:17:55.25#ibcon#about to write, iclass 25, count 0 2006.173.10:17:55.25#ibcon#wrote, iclass 25, count 0 2006.173.10:17:55.25#ibcon#about to read 3, iclass 25, count 0 2006.173.10:17:55.29#ibcon#read 3, iclass 25, count 0 2006.173.10:17:55.29#ibcon#about to read 4, iclass 25, count 0 2006.173.10:17:55.29#ibcon#read 4, iclass 25, count 0 2006.173.10:17:55.29#ibcon#about to read 5, iclass 25, count 0 2006.173.10:17:55.29#ibcon#read 5, iclass 25, count 0 2006.173.10:17:55.29#ibcon#about to read 6, iclass 25, count 0 2006.173.10:17:55.29#ibcon#read 6, iclass 25, count 0 2006.173.10:17:55.29#ibcon#end of sib2, iclass 25, count 0 2006.173.10:17:55.29#ibcon#*after write, iclass 25, count 0 2006.173.10:17:55.29#ibcon#*before return 0, iclass 25, count 0 2006.173.10:17:55.29#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.10:17:55.29#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.10:17:55.29#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.10:17:55.29#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.10:17:55.29$vck44/va=7,4 2006.173.10:17:55.29#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.10:17:55.29#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.10:17:55.29#ibcon#ireg 11 cls_cnt 2 2006.173.10:17:55.29#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.10:17:55.35#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.10:17:55.35#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.10:17:55.35#ibcon#enter wrdev, iclass 27, count 2 2006.173.10:17:55.35#ibcon#first serial, iclass 27, count 2 2006.173.10:17:55.35#ibcon#enter sib2, iclass 27, count 2 2006.173.10:17:55.35#ibcon#flushed, iclass 27, count 2 2006.173.10:17:55.35#ibcon#about to write, iclass 27, count 2 2006.173.10:17:55.35#ibcon#wrote, iclass 27, count 2 2006.173.10:17:55.35#ibcon#about to read 3, iclass 27, count 2 2006.173.10:17:55.37#ibcon#read 3, iclass 27, count 2 2006.173.10:17:55.37#ibcon#about to read 4, iclass 27, count 2 2006.173.10:17:55.37#ibcon#read 4, iclass 27, count 2 2006.173.10:17:55.37#ibcon#about to read 5, iclass 27, count 2 2006.173.10:17:55.37#ibcon#read 5, iclass 27, count 2 2006.173.10:17:55.37#ibcon#about to read 6, iclass 27, count 2 2006.173.10:17:55.37#ibcon#read 6, iclass 27, count 2 2006.173.10:17:55.37#ibcon#end of sib2, iclass 27, count 2 2006.173.10:17:55.37#ibcon#*mode == 0, iclass 27, count 2 2006.173.10:17:55.37#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.10:17:55.37#ibcon#[25=AT07-04\r\n] 2006.173.10:17:55.37#ibcon#*before write, iclass 27, count 2 2006.173.10:17:55.37#ibcon#enter sib2, iclass 27, count 2 2006.173.10:17:55.37#ibcon#flushed, iclass 27, count 2 2006.173.10:17:55.37#ibcon#about to write, iclass 27, count 2 2006.173.10:17:55.37#ibcon#wrote, iclass 27, count 2 2006.173.10:17:55.37#ibcon#about to read 3, iclass 27, count 2 2006.173.10:17:55.40#ibcon#read 3, iclass 27, count 2 2006.173.10:17:55.40#ibcon#about to read 4, iclass 27, count 2 2006.173.10:17:55.40#ibcon#read 4, iclass 27, count 2 2006.173.10:17:55.40#ibcon#about to read 5, iclass 27, count 2 2006.173.10:17:55.40#ibcon#read 5, iclass 27, count 2 2006.173.10:17:55.40#ibcon#about to read 6, iclass 27, count 2 2006.173.10:17:55.40#ibcon#read 6, iclass 27, count 2 2006.173.10:17:55.40#ibcon#end of sib2, iclass 27, count 2 2006.173.10:17:55.40#ibcon#*after write, iclass 27, count 2 2006.173.10:17:55.40#ibcon#*before return 0, iclass 27, count 2 2006.173.10:17:55.40#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.10:17:55.40#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.10:17:55.40#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.10:17:55.40#ibcon#ireg 7 cls_cnt 0 2006.173.10:17:55.40#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.10:17:55.52#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.10:17:55.52#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.10:17:55.52#ibcon#enter wrdev, iclass 27, count 0 2006.173.10:17:55.52#ibcon#first serial, iclass 27, count 0 2006.173.10:17:55.52#ibcon#enter sib2, iclass 27, count 0 2006.173.10:17:55.52#ibcon#flushed, iclass 27, count 0 2006.173.10:17:55.52#ibcon#about to write, iclass 27, count 0 2006.173.10:17:55.52#ibcon#wrote, iclass 27, count 0 2006.173.10:17:55.52#ibcon#about to read 3, iclass 27, count 0 2006.173.10:17:55.54#ibcon#read 3, iclass 27, count 0 2006.173.10:17:55.54#ibcon#about to read 4, iclass 27, count 0 2006.173.10:17:55.54#ibcon#read 4, iclass 27, count 0 2006.173.10:17:55.54#ibcon#about to read 5, iclass 27, count 0 2006.173.10:17:55.54#ibcon#read 5, iclass 27, count 0 2006.173.10:17:55.54#ibcon#about to read 6, iclass 27, count 0 2006.173.10:17:55.54#ibcon#read 6, iclass 27, count 0 2006.173.10:17:55.54#ibcon#end of sib2, iclass 27, count 0 2006.173.10:17:55.54#ibcon#*mode == 0, iclass 27, count 0 2006.173.10:17:55.54#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.10:17:55.54#ibcon#[25=USB\r\n] 2006.173.10:17:55.54#ibcon#*before write, iclass 27, count 0 2006.173.10:17:55.54#ibcon#enter sib2, iclass 27, count 0 2006.173.10:17:55.54#ibcon#flushed, iclass 27, count 0 2006.173.10:17:55.54#ibcon#about to write, iclass 27, count 0 2006.173.10:17:55.54#ibcon#wrote, iclass 27, count 0 2006.173.10:17:55.54#ibcon#about to read 3, iclass 27, count 0 2006.173.10:17:55.57#ibcon#read 3, iclass 27, count 0 2006.173.10:17:55.57#ibcon#about to read 4, iclass 27, count 0 2006.173.10:17:55.57#ibcon#read 4, iclass 27, count 0 2006.173.10:17:55.57#ibcon#about to read 5, iclass 27, count 0 2006.173.10:17:55.57#ibcon#read 5, iclass 27, count 0 2006.173.10:17:55.57#ibcon#about to read 6, iclass 27, count 0 2006.173.10:17:55.57#ibcon#read 6, iclass 27, count 0 2006.173.10:17:55.57#ibcon#end of sib2, iclass 27, count 0 2006.173.10:17:55.57#ibcon#*after write, iclass 27, count 0 2006.173.10:17:55.57#ibcon#*before return 0, iclass 27, count 0 2006.173.10:17:55.57#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.10:17:55.57#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.10:17:55.57#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.10:17:55.57#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.10:17:55.57$vck44/valo=8,884.99 2006.173.10:17:55.57#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.10:17:55.57#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.10:17:55.57#ibcon#ireg 17 cls_cnt 0 2006.173.10:17:55.57#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.10:17:55.57#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.10:17:55.57#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.10:17:55.57#ibcon#enter wrdev, iclass 29, count 0 2006.173.10:17:55.57#ibcon#first serial, iclass 29, count 0 2006.173.10:17:55.57#ibcon#enter sib2, iclass 29, count 0 2006.173.10:17:55.57#ibcon#flushed, iclass 29, count 0 2006.173.10:17:55.57#ibcon#about to write, iclass 29, count 0 2006.173.10:17:55.57#ibcon#wrote, iclass 29, count 0 2006.173.10:17:55.57#ibcon#about to read 3, iclass 29, count 0 2006.173.10:17:55.59#ibcon#read 3, iclass 29, count 0 2006.173.10:17:55.59#ibcon#about to read 4, iclass 29, count 0 2006.173.10:17:55.59#ibcon#read 4, iclass 29, count 0 2006.173.10:17:55.59#ibcon#about to read 5, iclass 29, count 0 2006.173.10:17:55.59#ibcon#read 5, iclass 29, count 0 2006.173.10:17:55.59#ibcon#about to read 6, iclass 29, count 0 2006.173.10:17:55.59#ibcon#read 6, iclass 29, count 0 2006.173.10:17:55.59#ibcon#end of sib2, iclass 29, count 0 2006.173.10:17:55.59#ibcon#*mode == 0, iclass 29, count 0 2006.173.10:17:55.59#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.10:17:55.59#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.10:17:55.59#ibcon#*before write, iclass 29, count 0 2006.173.10:17:55.59#ibcon#enter sib2, iclass 29, count 0 2006.173.10:17:55.59#ibcon#flushed, iclass 29, count 0 2006.173.10:17:55.59#ibcon#about to write, iclass 29, count 0 2006.173.10:17:55.59#ibcon#wrote, iclass 29, count 0 2006.173.10:17:55.59#ibcon#about to read 3, iclass 29, count 0 2006.173.10:17:55.63#ibcon#read 3, iclass 29, count 0 2006.173.10:17:55.63#ibcon#about to read 4, iclass 29, count 0 2006.173.10:17:55.63#ibcon#read 4, iclass 29, count 0 2006.173.10:17:55.63#ibcon#about to read 5, iclass 29, count 0 2006.173.10:17:55.63#ibcon#read 5, iclass 29, count 0 2006.173.10:17:55.63#ibcon#about to read 6, iclass 29, count 0 2006.173.10:17:55.63#ibcon#read 6, iclass 29, count 0 2006.173.10:17:55.63#ibcon#end of sib2, iclass 29, count 0 2006.173.10:17:55.63#ibcon#*after write, iclass 29, count 0 2006.173.10:17:55.63#ibcon#*before return 0, iclass 29, count 0 2006.173.10:17:55.63#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.10:17:55.63#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.10:17:55.63#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.10:17:55.63#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.10:17:55.63$vck44/va=8,4 2006.173.10:17:55.63#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.10:17:55.63#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.10:17:55.63#ibcon#ireg 11 cls_cnt 2 2006.173.10:17:55.63#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.10:17:55.69#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.10:17:55.69#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.10:17:55.69#ibcon#enter wrdev, iclass 31, count 2 2006.173.10:17:55.69#ibcon#first serial, iclass 31, count 2 2006.173.10:17:55.69#ibcon#enter sib2, iclass 31, count 2 2006.173.10:17:55.69#ibcon#flushed, iclass 31, count 2 2006.173.10:17:55.69#ibcon#about to write, iclass 31, count 2 2006.173.10:17:55.69#ibcon#wrote, iclass 31, count 2 2006.173.10:17:55.69#ibcon#about to read 3, iclass 31, count 2 2006.173.10:17:55.71#ibcon#read 3, iclass 31, count 2 2006.173.10:17:55.71#ibcon#about to read 4, iclass 31, count 2 2006.173.10:17:55.71#ibcon#read 4, iclass 31, count 2 2006.173.10:17:55.71#ibcon#about to read 5, iclass 31, count 2 2006.173.10:17:55.71#ibcon#read 5, iclass 31, count 2 2006.173.10:17:55.71#ibcon#about to read 6, iclass 31, count 2 2006.173.10:17:55.71#ibcon#read 6, iclass 31, count 2 2006.173.10:17:55.71#ibcon#end of sib2, iclass 31, count 2 2006.173.10:17:55.71#ibcon#*mode == 0, iclass 31, count 2 2006.173.10:17:55.71#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.10:17:55.71#ibcon#[25=AT08-04\r\n] 2006.173.10:17:55.71#ibcon#*before write, iclass 31, count 2 2006.173.10:17:55.71#ibcon#enter sib2, iclass 31, count 2 2006.173.10:17:55.71#ibcon#flushed, iclass 31, count 2 2006.173.10:17:55.71#ibcon#about to write, iclass 31, count 2 2006.173.10:17:55.71#ibcon#wrote, iclass 31, count 2 2006.173.10:17:55.71#ibcon#about to read 3, iclass 31, count 2 2006.173.10:17:55.74#ibcon#read 3, iclass 31, count 2 2006.173.10:17:55.74#ibcon#about to read 4, iclass 31, count 2 2006.173.10:17:55.74#ibcon#read 4, iclass 31, count 2 2006.173.10:17:55.74#ibcon#about to read 5, iclass 31, count 2 2006.173.10:17:55.74#ibcon#read 5, iclass 31, count 2 2006.173.10:17:55.74#ibcon#about to read 6, iclass 31, count 2 2006.173.10:17:55.74#ibcon#read 6, iclass 31, count 2 2006.173.10:17:55.74#ibcon#end of sib2, iclass 31, count 2 2006.173.10:17:55.74#ibcon#*after write, iclass 31, count 2 2006.173.10:17:55.74#ibcon#*before return 0, iclass 31, count 2 2006.173.10:17:55.74#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.10:17:55.74#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.10:17:55.74#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.10:17:55.74#ibcon#ireg 7 cls_cnt 0 2006.173.10:17:55.74#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.10:17:55.86#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.10:17:55.86#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.10:17:55.86#ibcon#enter wrdev, iclass 31, count 0 2006.173.10:17:55.86#ibcon#first serial, iclass 31, count 0 2006.173.10:17:55.86#ibcon#enter sib2, iclass 31, count 0 2006.173.10:17:55.86#ibcon#flushed, iclass 31, count 0 2006.173.10:17:55.86#ibcon#about to write, iclass 31, count 0 2006.173.10:17:55.86#ibcon#wrote, iclass 31, count 0 2006.173.10:17:55.86#ibcon#about to read 3, iclass 31, count 0 2006.173.10:17:55.88#ibcon#read 3, iclass 31, count 0 2006.173.10:17:55.88#ibcon#about to read 4, iclass 31, count 0 2006.173.10:17:55.88#ibcon#read 4, iclass 31, count 0 2006.173.10:17:55.88#ibcon#about to read 5, iclass 31, count 0 2006.173.10:17:55.88#ibcon#read 5, iclass 31, count 0 2006.173.10:17:55.88#ibcon#about to read 6, iclass 31, count 0 2006.173.10:17:55.88#ibcon#read 6, iclass 31, count 0 2006.173.10:17:55.88#ibcon#end of sib2, iclass 31, count 0 2006.173.10:17:55.88#ibcon#*mode == 0, iclass 31, count 0 2006.173.10:17:55.88#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.10:17:55.88#ibcon#[25=USB\r\n] 2006.173.10:17:55.88#ibcon#*before write, iclass 31, count 0 2006.173.10:17:55.88#ibcon#enter sib2, iclass 31, count 0 2006.173.10:17:55.88#ibcon#flushed, iclass 31, count 0 2006.173.10:17:55.88#ibcon#about to write, iclass 31, count 0 2006.173.10:17:55.88#ibcon#wrote, iclass 31, count 0 2006.173.10:17:55.88#ibcon#about to read 3, iclass 31, count 0 2006.173.10:17:55.91#ibcon#read 3, iclass 31, count 0 2006.173.10:17:55.91#ibcon#about to read 4, iclass 31, count 0 2006.173.10:17:55.91#ibcon#read 4, iclass 31, count 0 2006.173.10:17:55.91#ibcon#about to read 5, iclass 31, count 0 2006.173.10:17:55.91#ibcon#read 5, iclass 31, count 0 2006.173.10:17:55.91#ibcon#about to read 6, iclass 31, count 0 2006.173.10:17:55.91#ibcon#read 6, iclass 31, count 0 2006.173.10:17:55.91#ibcon#end of sib2, iclass 31, count 0 2006.173.10:17:55.91#ibcon#*after write, iclass 31, count 0 2006.173.10:17:55.91#ibcon#*before return 0, iclass 31, count 0 2006.173.10:17:55.91#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.10:17:55.91#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.10:17:55.91#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.10:17:55.91#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.10:17:55.91$vck44/vblo=1,629.99 2006.173.10:17:55.91#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.10:17:55.91#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.10:17:55.91#ibcon#ireg 17 cls_cnt 0 2006.173.10:17:55.91#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.10:17:55.91#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.10:17:55.91#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.10:17:55.91#ibcon#enter wrdev, iclass 33, count 0 2006.173.10:17:55.91#ibcon#first serial, iclass 33, count 0 2006.173.10:17:55.91#ibcon#enter sib2, iclass 33, count 0 2006.173.10:17:55.91#ibcon#flushed, iclass 33, count 0 2006.173.10:17:55.91#ibcon#about to write, iclass 33, count 0 2006.173.10:17:55.91#ibcon#wrote, iclass 33, count 0 2006.173.10:17:55.91#ibcon#about to read 3, iclass 33, count 0 2006.173.10:17:55.93#ibcon#read 3, iclass 33, count 0 2006.173.10:17:55.93#ibcon#about to read 4, iclass 33, count 0 2006.173.10:17:55.93#ibcon#read 4, iclass 33, count 0 2006.173.10:17:55.93#ibcon#about to read 5, iclass 33, count 0 2006.173.10:17:55.93#ibcon#read 5, iclass 33, count 0 2006.173.10:17:55.93#ibcon#about to read 6, iclass 33, count 0 2006.173.10:17:55.93#ibcon#read 6, iclass 33, count 0 2006.173.10:17:55.93#ibcon#end of sib2, iclass 33, count 0 2006.173.10:17:55.93#ibcon#*mode == 0, iclass 33, count 0 2006.173.10:17:55.93#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.10:17:55.93#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.10:17:55.93#ibcon#*before write, iclass 33, count 0 2006.173.10:17:55.93#ibcon#enter sib2, iclass 33, count 0 2006.173.10:17:55.93#ibcon#flushed, iclass 33, count 0 2006.173.10:17:55.93#ibcon#about to write, iclass 33, count 0 2006.173.10:17:55.93#ibcon#wrote, iclass 33, count 0 2006.173.10:17:55.93#ibcon#about to read 3, iclass 33, count 0 2006.173.10:17:55.97#ibcon#read 3, iclass 33, count 0 2006.173.10:17:55.97#ibcon#about to read 4, iclass 33, count 0 2006.173.10:17:55.97#ibcon#read 4, iclass 33, count 0 2006.173.10:17:55.97#ibcon#about to read 5, iclass 33, count 0 2006.173.10:17:55.97#ibcon#read 5, iclass 33, count 0 2006.173.10:17:55.97#ibcon#about to read 6, iclass 33, count 0 2006.173.10:17:55.97#ibcon#read 6, iclass 33, count 0 2006.173.10:17:55.97#ibcon#end of sib2, iclass 33, count 0 2006.173.10:17:55.97#ibcon#*after write, iclass 33, count 0 2006.173.10:17:55.97#ibcon#*before return 0, iclass 33, count 0 2006.173.10:17:55.97#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.10:17:55.97#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.10:17:55.97#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.10:17:55.97#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.10:17:55.97$vck44/vb=1,4 2006.173.10:17:55.97#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.10:17:55.97#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.10:17:55.97#ibcon#ireg 11 cls_cnt 2 2006.173.10:17:55.97#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.10:17:55.97#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.10:17:55.97#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.10:17:55.97#ibcon#enter wrdev, iclass 35, count 2 2006.173.10:17:55.97#ibcon#first serial, iclass 35, count 2 2006.173.10:17:55.97#ibcon#enter sib2, iclass 35, count 2 2006.173.10:17:55.97#ibcon#flushed, iclass 35, count 2 2006.173.10:17:55.97#ibcon#about to write, iclass 35, count 2 2006.173.10:17:55.97#ibcon#wrote, iclass 35, count 2 2006.173.10:17:55.97#ibcon#about to read 3, iclass 35, count 2 2006.173.10:17:55.99#ibcon#read 3, iclass 35, count 2 2006.173.10:17:55.99#ibcon#about to read 4, iclass 35, count 2 2006.173.10:17:55.99#ibcon#read 4, iclass 35, count 2 2006.173.10:17:55.99#ibcon#about to read 5, iclass 35, count 2 2006.173.10:17:55.99#ibcon#read 5, iclass 35, count 2 2006.173.10:17:55.99#ibcon#about to read 6, iclass 35, count 2 2006.173.10:17:55.99#ibcon#read 6, iclass 35, count 2 2006.173.10:17:55.99#ibcon#end of sib2, iclass 35, count 2 2006.173.10:17:55.99#ibcon#*mode == 0, iclass 35, count 2 2006.173.10:17:55.99#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.10:17:55.99#ibcon#[27=AT01-04\r\n] 2006.173.10:17:55.99#ibcon#*before write, iclass 35, count 2 2006.173.10:17:55.99#ibcon#enter sib2, iclass 35, count 2 2006.173.10:17:55.99#ibcon#flushed, iclass 35, count 2 2006.173.10:17:55.99#ibcon#about to write, iclass 35, count 2 2006.173.10:17:55.99#ibcon#wrote, iclass 35, count 2 2006.173.10:17:55.99#ibcon#about to read 3, iclass 35, count 2 2006.173.10:17:56.02#ibcon#read 3, iclass 35, count 2 2006.173.10:17:56.02#ibcon#about to read 4, iclass 35, count 2 2006.173.10:17:56.02#ibcon#read 4, iclass 35, count 2 2006.173.10:17:56.02#ibcon#about to read 5, iclass 35, count 2 2006.173.10:17:56.02#ibcon#read 5, iclass 35, count 2 2006.173.10:17:56.02#ibcon#about to read 6, iclass 35, count 2 2006.173.10:17:56.02#ibcon#read 6, iclass 35, count 2 2006.173.10:17:56.02#ibcon#end of sib2, iclass 35, count 2 2006.173.10:17:56.02#ibcon#*after write, iclass 35, count 2 2006.173.10:17:56.02#ibcon#*before return 0, iclass 35, count 2 2006.173.10:17:56.02#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.10:17:56.02#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.10:17:56.02#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.10:17:56.02#ibcon#ireg 7 cls_cnt 0 2006.173.10:17:56.02#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.10:17:56.14#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.10:17:56.14#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.10:17:56.14#ibcon#enter wrdev, iclass 35, count 0 2006.173.10:17:56.14#ibcon#first serial, iclass 35, count 0 2006.173.10:17:56.14#ibcon#enter sib2, iclass 35, count 0 2006.173.10:17:56.14#ibcon#flushed, iclass 35, count 0 2006.173.10:17:56.14#ibcon#about to write, iclass 35, count 0 2006.173.10:17:56.14#ibcon#wrote, iclass 35, count 0 2006.173.10:17:56.14#ibcon#about to read 3, iclass 35, count 0 2006.173.10:17:56.16#ibcon#read 3, iclass 35, count 0 2006.173.10:17:56.16#ibcon#about to read 4, iclass 35, count 0 2006.173.10:17:56.16#ibcon#read 4, iclass 35, count 0 2006.173.10:17:56.16#ibcon#about to read 5, iclass 35, count 0 2006.173.10:17:56.16#ibcon#read 5, iclass 35, count 0 2006.173.10:17:56.16#ibcon#about to read 6, iclass 35, count 0 2006.173.10:17:56.16#ibcon#read 6, iclass 35, count 0 2006.173.10:17:56.16#ibcon#end of sib2, iclass 35, count 0 2006.173.10:17:56.16#ibcon#*mode == 0, iclass 35, count 0 2006.173.10:17:56.16#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.10:17:56.16#ibcon#[27=USB\r\n] 2006.173.10:17:56.16#ibcon#*before write, iclass 35, count 0 2006.173.10:17:56.16#ibcon#enter sib2, iclass 35, count 0 2006.173.10:17:56.16#ibcon#flushed, iclass 35, count 0 2006.173.10:17:56.16#ibcon#about to write, iclass 35, count 0 2006.173.10:17:56.16#ibcon#wrote, iclass 35, count 0 2006.173.10:17:56.16#ibcon#about to read 3, iclass 35, count 0 2006.173.10:17:56.19#ibcon#read 3, iclass 35, count 0 2006.173.10:17:56.19#ibcon#about to read 4, iclass 35, count 0 2006.173.10:17:56.19#ibcon#read 4, iclass 35, count 0 2006.173.10:17:56.19#ibcon#about to read 5, iclass 35, count 0 2006.173.10:17:56.19#ibcon#read 5, iclass 35, count 0 2006.173.10:17:56.19#ibcon#about to read 6, iclass 35, count 0 2006.173.10:17:56.19#ibcon#read 6, iclass 35, count 0 2006.173.10:17:56.19#ibcon#end of sib2, iclass 35, count 0 2006.173.10:17:56.19#ibcon#*after write, iclass 35, count 0 2006.173.10:17:56.19#ibcon#*before return 0, iclass 35, count 0 2006.173.10:17:56.19#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.10:17:56.19#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.10:17:56.19#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.10:17:56.19#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.10:17:56.19$vck44/vblo=2,634.99 2006.173.10:17:56.19#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.10:17:56.19#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.10:17:56.19#ibcon#ireg 17 cls_cnt 0 2006.173.10:17:56.19#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.10:17:56.19#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.10:17:56.19#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.10:17:56.19#ibcon#enter wrdev, iclass 37, count 0 2006.173.10:17:56.19#ibcon#first serial, iclass 37, count 0 2006.173.10:17:56.19#ibcon#enter sib2, iclass 37, count 0 2006.173.10:17:56.19#ibcon#flushed, iclass 37, count 0 2006.173.10:17:56.19#ibcon#about to write, iclass 37, count 0 2006.173.10:17:56.19#ibcon#wrote, iclass 37, count 0 2006.173.10:17:56.19#ibcon#about to read 3, iclass 37, count 0 2006.173.10:17:56.21#ibcon#read 3, iclass 37, count 0 2006.173.10:17:56.21#ibcon#about to read 4, iclass 37, count 0 2006.173.10:17:56.21#ibcon#read 4, iclass 37, count 0 2006.173.10:17:56.21#ibcon#about to read 5, iclass 37, count 0 2006.173.10:17:56.21#ibcon#read 5, iclass 37, count 0 2006.173.10:17:56.21#ibcon#about to read 6, iclass 37, count 0 2006.173.10:17:56.21#ibcon#read 6, iclass 37, count 0 2006.173.10:17:56.21#ibcon#end of sib2, iclass 37, count 0 2006.173.10:17:56.21#ibcon#*mode == 0, iclass 37, count 0 2006.173.10:17:56.21#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.10:17:56.21#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.10:17:56.21#ibcon#*before write, iclass 37, count 0 2006.173.10:17:56.21#ibcon#enter sib2, iclass 37, count 0 2006.173.10:17:56.21#ibcon#flushed, iclass 37, count 0 2006.173.10:17:56.21#ibcon#about to write, iclass 37, count 0 2006.173.10:17:56.21#ibcon#wrote, iclass 37, count 0 2006.173.10:17:56.21#ibcon#about to read 3, iclass 37, count 0 2006.173.10:17:56.25#ibcon#read 3, iclass 37, count 0 2006.173.10:17:56.25#ibcon#about to read 4, iclass 37, count 0 2006.173.10:17:56.25#ibcon#read 4, iclass 37, count 0 2006.173.10:17:56.25#ibcon#about to read 5, iclass 37, count 0 2006.173.10:17:56.25#ibcon#read 5, iclass 37, count 0 2006.173.10:17:56.25#ibcon#about to read 6, iclass 37, count 0 2006.173.10:17:56.25#ibcon#read 6, iclass 37, count 0 2006.173.10:17:56.25#ibcon#end of sib2, iclass 37, count 0 2006.173.10:17:56.25#ibcon#*after write, iclass 37, count 0 2006.173.10:17:56.25#ibcon#*before return 0, iclass 37, count 0 2006.173.10:17:56.25#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.10:17:56.25#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.10:17:56.25#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.10:17:56.25#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.10:17:56.25$vck44/vb=2,4 2006.173.10:17:56.25#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.10:17:56.25#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.10:17:56.25#ibcon#ireg 11 cls_cnt 2 2006.173.10:17:56.25#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.10:17:56.31#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.10:17:56.31#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.10:17:56.31#ibcon#enter wrdev, iclass 39, count 2 2006.173.10:17:56.31#ibcon#first serial, iclass 39, count 2 2006.173.10:17:56.31#ibcon#enter sib2, iclass 39, count 2 2006.173.10:17:56.31#ibcon#flushed, iclass 39, count 2 2006.173.10:17:56.31#ibcon#about to write, iclass 39, count 2 2006.173.10:17:56.31#ibcon#wrote, iclass 39, count 2 2006.173.10:17:56.31#ibcon#about to read 3, iclass 39, count 2 2006.173.10:17:56.33#ibcon#read 3, iclass 39, count 2 2006.173.10:17:56.33#ibcon#about to read 4, iclass 39, count 2 2006.173.10:17:56.33#ibcon#read 4, iclass 39, count 2 2006.173.10:17:56.33#ibcon#about to read 5, iclass 39, count 2 2006.173.10:17:56.33#ibcon#read 5, iclass 39, count 2 2006.173.10:17:56.33#ibcon#about to read 6, iclass 39, count 2 2006.173.10:17:56.33#ibcon#read 6, iclass 39, count 2 2006.173.10:17:56.33#ibcon#end of sib2, iclass 39, count 2 2006.173.10:17:56.33#ibcon#*mode == 0, iclass 39, count 2 2006.173.10:17:56.33#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.10:17:56.33#ibcon#[27=AT02-04\r\n] 2006.173.10:17:56.33#ibcon#*before write, iclass 39, count 2 2006.173.10:17:56.33#ibcon#enter sib2, iclass 39, count 2 2006.173.10:17:56.33#ibcon#flushed, iclass 39, count 2 2006.173.10:17:56.33#ibcon#about to write, iclass 39, count 2 2006.173.10:17:56.33#ibcon#wrote, iclass 39, count 2 2006.173.10:17:56.33#ibcon#about to read 3, iclass 39, count 2 2006.173.10:17:56.36#ibcon#read 3, iclass 39, count 2 2006.173.10:17:56.36#ibcon#about to read 4, iclass 39, count 2 2006.173.10:17:56.36#ibcon#read 4, iclass 39, count 2 2006.173.10:17:56.36#ibcon#about to read 5, iclass 39, count 2 2006.173.10:17:56.36#ibcon#read 5, iclass 39, count 2 2006.173.10:17:56.36#ibcon#about to read 6, iclass 39, count 2 2006.173.10:17:56.36#ibcon#read 6, iclass 39, count 2 2006.173.10:17:56.36#ibcon#end of sib2, iclass 39, count 2 2006.173.10:17:56.36#ibcon#*after write, iclass 39, count 2 2006.173.10:17:56.36#ibcon#*before return 0, iclass 39, count 2 2006.173.10:17:56.36#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.10:17:56.36#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.10:17:56.36#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.10:17:56.36#ibcon#ireg 7 cls_cnt 0 2006.173.10:17:56.36#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.10:17:56.48#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.10:17:56.48#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.10:17:56.48#ibcon#enter wrdev, iclass 39, count 0 2006.173.10:17:56.48#ibcon#first serial, iclass 39, count 0 2006.173.10:17:56.48#ibcon#enter sib2, iclass 39, count 0 2006.173.10:17:56.48#ibcon#flushed, iclass 39, count 0 2006.173.10:17:56.48#ibcon#about to write, iclass 39, count 0 2006.173.10:17:56.48#ibcon#wrote, iclass 39, count 0 2006.173.10:17:56.48#ibcon#about to read 3, iclass 39, count 0 2006.173.10:17:56.50#ibcon#read 3, iclass 39, count 0 2006.173.10:17:56.50#ibcon#about to read 4, iclass 39, count 0 2006.173.10:17:56.50#ibcon#read 4, iclass 39, count 0 2006.173.10:17:56.50#ibcon#about to read 5, iclass 39, count 0 2006.173.10:17:56.50#ibcon#read 5, iclass 39, count 0 2006.173.10:17:56.50#ibcon#about to read 6, iclass 39, count 0 2006.173.10:17:56.50#ibcon#read 6, iclass 39, count 0 2006.173.10:17:56.50#ibcon#end of sib2, iclass 39, count 0 2006.173.10:17:56.50#ibcon#*mode == 0, iclass 39, count 0 2006.173.10:17:56.50#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.10:17:56.50#ibcon#[27=USB\r\n] 2006.173.10:17:56.50#ibcon#*before write, iclass 39, count 0 2006.173.10:17:56.50#ibcon#enter sib2, iclass 39, count 0 2006.173.10:17:56.50#ibcon#flushed, iclass 39, count 0 2006.173.10:17:56.50#ibcon#about to write, iclass 39, count 0 2006.173.10:17:56.50#ibcon#wrote, iclass 39, count 0 2006.173.10:17:56.50#ibcon#about to read 3, iclass 39, count 0 2006.173.10:17:56.53#ibcon#read 3, iclass 39, count 0 2006.173.10:17:56.53#ibcon#about to read 4, iclass 39, count 0 2006.173.10:17:56.53#ibcon#read 4, iclass 39, count 0 2006.173.10:17:56.53#ibcon#about to read 5, iclass 39, count 0 2006.173.10:17:56.53#ibcon#read 5, iclass 39, count 0 2006.173.10:17:56.53#ibcon#about to read 6, iclass 39, count 0 2006.173.10:17:56.53#ibcon#read 6, iclass 39, count 0 2006.173.10:17:56.53#ibcon#end of sib2, iclass 39, count 0 2006.173.10:17:56.53#ibcon#*after write, iclass 39, count 0 2006.173.10:17:56.53#ibcon#*before return 0, iclass 39, count 0 2006.173.10:17:56.53#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.10:17:56.53#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.10:17:56.53#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.10:17:56.53#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.10:17:56.53$vck44/vblo=3,649.99 2006.173.10:17:56.53#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.10:17:56.53#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.10:17:56.53#ibcon#ireg 17 cls_cnt 0 2006.173.10:17:56.53#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.10:17:56.53#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.10:17:56.53#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.10:17:56.53#ibcon#enter wrdev, iclass 3, count 0 2006.173.10:17:56.53#ibcon#first serial, iclass 3, count 0 2006.173.10:17:56.53#ibcon#enter sib2, iclass 3, count 0 2006.173.10:17:56.53#ibcon#flushed, iclass 3, count 0 2006.173.10:17:56.53#ibcon#about to write, iclass 3, count 0 2006.173.10:17:56.53#ibcon#wrote, iclass 3, count 0 2006.173.10:17:56.53#ibcon#about to read 3, iclass 3, count 0 2006.173.10:17:56.55#ibcon#read 3, iclass 3, count 0 2006.173.10:17:56.55#ibcon#about to read 4, iclass 3, count 0 2006.173.10:17:56.55#ibcon#read 4, iclass 3, count 0 2006.173.10:17:56.55#ibcon#about to read 5, iclass 3, count 0 2006.173.10:17:56.55#ibcon#read 5, iclass 3, count 0 2006.173.10:17:56.55#ibcon#about to read 6, iclass 3, count 0 2006.173.10:17:56.55#ibcon#read 6, iclass 3, count 0 2006.173.10:17:56.55#ibcon#end of sib2, iclass 3, count 0 2006.173.10:17:56.55#ibcon#*mode == 0, iclass 3, count 0 2006.173.10:17:56.55#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.10:17:56.55#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.10:17:56.55#ibcon#*before write, iclass 3, count 0 2006.173.10:17:56.55#ibcon#enter sib2, iclass 3, count 0 2006.173.10:17:56.55#ibcon#flushed, iclass 3, count 0 2006.173.10:17:56.55#ibcon#about to write, iclass 3, count 0 2006.173.10:17:56.55#ibcon#wrote, iclass 3, count 0 2006.173.10:17:56.55#ibcon#about to read 3, iclass 3, count 0 2006.173.10:17:56.59#ibcon#read 3, iclass 3, count 0 2006.173.10:17:56.59#ibcon#about to read 4, iclass 3, count 0 2006.173.10:17:56.59#ibcon#read 4, iclass 3, count 0 2006.173.10:17:56.59#ibcon#about to read 5, iclass 3, count 0 2006.173.10:17:56.59#ibcon#read 5, iclass 3, count 0 2006.173.10:17:56.59#ibcon#about to read 6, iclass 3, count 0 2006.173.10:17:56.59#ibcon#read 6, iclass 3, count 0 2006.173.10:17:56.59#ibcon#end of sib2, iclass 3, count 0 2006.173.10:17:56.59#ibcon#*after write, iclass 3, count 0 2006.173.10:17:56.59#ibcon#*before return 0, iclass 3, count 0 2006.173.10:17:56.59#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.10:17:56.59#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.10:17:56.59#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.10:17:56.59#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.10:17:56.59$vck44/vb=3,4 2006.173.10:17:56.59#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.10:17:56.59#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.10:17:56.59#ibcon#ireg 11 cls_cnt 2 2006.173.10:17:56.59#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.10:17:56.65#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.10:17:56.65#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.10:17:56.65#ibcon#enter wrdev, iclass 5, count 2 2006.173.10:17:56.65#ibcon#first serial, iclass 5, count 2 2006.173.10:17:56.65#ibcon#enter sib2, iclass 5, count 2 2006.173.10:17:56.65#ibcon#flushed, iclass 5, count 2 2006.173.10:17:56.65#ibcon#about to write, iclass 5, count 2 2006.173.10:17:56.65#ibcon#wrote, iclass 5, count 2 2006.173.10:17:56.65#ibcon#about to read 3, iclass 5, count 2 2006.173.10:17:56.67#ibcon#read 3, iclass 5, count 2 2006.173.10:17:56.67#ibcon#about to read 4, iclass 5, count 2 2006.173.10:17:56.67#ibcon#read 4, iclass 5, count 2 2006.173.10:17:56.67#ibcon#about to read 5, iclass 5, count 2 2006.173.10:17:56.67#ibcon#read 5, iclass 5, count 2 2006.173.10:17:56.67#ibcon#about to read 6, iclass 5, count 2 2006.173.10:17:56.67#ibcon#read 6, iclass 5, count 2 2006.173.10:17:56.67#ibcon#end of sib2, iclass 5, count 2 2006.173.10:17:56.67#ibcon#*mode == 0, iclass 5, count 2 2006.173.10:17:56.67#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.10:17:56.67#ibcon#[27=AT03-04\r\n] 2006.173.10:17:56.67#ibcon#*before write, iclass 5, count 2 2006.173.10:17:56.67#ibcon#enter sib2, iclass 5, count 2 2006.173.10:17:56.67#ibcon#flushed, iclass 5, count 2 2006.173.10:17:56.67#ibcon#about to write, iclass 5, count 2 2006.173.10:17:56.67#ibcon#wrote, iclass 5, count 2 2006.173.10:17:56.67#ibcon#about to read 3, iclass 5, count 2 2006.173.10:17:56.70#ibcon#read 3, iclass 5, count 2 2006.173.10:17:56.70#ibcon#about to read 4, iclass 5, count 2 2006.173.10:17:56.70#ibcon#read 4, iclass 5, count 2 2006.173.10:17:56.70#ibcon#about to read 5, iclass 5, count 2 2006.173.10:17:56.70#ibcon#read 5, iclass 5, count 2 2006.173.10:17:56.70#ibcon#about to read 6, iclass 5, count 2 2006.173.10:17:56.70#ibcon#read 6, iclass 5, count 2 2006.173.10:17:56.70#ibcon#end of sib2, iclass 5, count 2 2006.173.10:17:56.70#ibcon#*after write, iclass 5, count 2 2006.173.10:17:56.70#ibcon#*before return 0, iclass 5, count 2 2006.173.10:17:56.70#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.10:17:56.70#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.10:17:56.70#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.10:17:56.70#ibcon#ireg 7 cls_cnt 0 2006.173.10:17:56.70#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.10:17:56.82#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.10:17:56.82#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.10:17:56.82#ibcon#enter wrdev, iclass 5, count 0 2006.173.10:17:56.82#ibcon#first serial, iclass 5, count 0 2006.173.10:17:56.82#ibcon#enter sib2, iclass 5, count 0 2006.173.10:17:56.82#ibcon#flushed, iclass 5, count 0 2006.173.10:17:56.82#ibcon#about to write, iclass 5, count 0 2006.173.10:17:56.82#ibcon#wrote, iclass 5, count 0 2006.173.10:17:56.82#ibcon#about to read 3, iclass 5, count 0 2006.173.10:17:56.84#ibcon#read 3, iclass 5, count 0 2006.173.10:17:56.84#ibcon#about to read 4, iclass 5, count 0 2006.173.10:17:56.84#ibcon#read 4, iclass 5, count 0 2006.173.10:17:56.84#ibcon#about to read 5, iclass 5, count 0 2006.173.10:17:56.84#ibcon#read 5, iclass 5, count 0 2006.173.10:17:56.84#ibcon#about to read 6, iclass 5, count 0 2006.173.10:17:56.84#ibcon#read 6, iclass 5, count 0 2006.173.10:17:56.84#ibcon#end of sib2, iclass 5, count 0 2006.173.10:17:56.84#ibcon#*mode == 0, iclass 5, count 0 2006.173.10:17:56.84#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.10:17:56.84#ibcon#[27=USB\r\n] 2006.173.10:17:56.84#ibcon#*before write, iclass 5, count 0 2006.173.10:17:56.84#ibcon#enter sib2, iclass 5, count 0 2006.173.10:17:56.84#ibcon#flushed, iclass 5, count 0 2006.173.10:17:56.84#ibcon#about to write, iclass 5, count 0 2006.173.10:17:56.84#ibcon#wrote, iclass 5, count 0 2006.173.10:17:56.84#ibcon#about to read 3, iclass 5, count 0 2006.173.10:17:56.87#ibcon#read 3, iclass 5, count 0 2006.173.10:17:56.87#ibcon#about to read 4, iclass 5, count 0 2006.173.10:17:56.87#ibcon#read 4, iclass 5, count 0 2006.173.10:17:56.87#ibcon#about to read 5, iclass 5, count 0 2006.173.10:17:56.87#ibcon#read 5, iclass 5, count 0 2006.173.10:17:56.87#ibcon#about to read 6, iclass 5, count 0 2006.173.10:17:56.87#ibcon#read 6, iclass 5, count 0 2006.173.10:17:56.87#ibcon#end of sib2, iclass 5, count 0 2006.173.10:17:56.87#ibcon#*after write, iclass 5, count 0 2006.173.10:17:56.87#ibcon#*before return 0, iclass 5, count 0 2006.173.10:17:56.87#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.10:17:56.87#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.10:17:56.87#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.10:17:56.87#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.10:17:56.87$vck44/vblo=4,679.99 2006.173.10:17:56.87#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.10:17:56.87#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.10:17:56.87#ibcon#ireg 17 cls_cnt 0 2006.173.10:17:56.87#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.10:17:56.87#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.10:17:56.87#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.10:17:56.87#ibcon#enter wrdev, iclass 7, count 0 2006.173.10:17:56.87#ibcon#first serial, iclass 7, count 0 2006.173.10:17:56.87#ibcon#enter sib2, iclass 7, count 0 2006.173.10:17:56.87#ibcon#flushed, iclass 7, count 0 2006.173.10:17:56.87#ibcon#about to write, iclass 7, count 0 2006.173.10:17:56.87#ibcon#wrote, iclass 7, count 0 2006.173.10:17:56.87#ibcon#about to read 3, iclass 7, count 0 2006.173.10:17:56.89#ibcon#read 3, iclass 7, count 0 2006.173.10:17:56.89#ibcon#about to read 4, iclass 7, count 0 2006.173.10:17:56.89#ibcon#read 4, iclass 7, count 0 2006.173.10:17:56.89#ibcon#about to read 5, iclass 7, count 0 2006.173.10:17:56.89#ibcon#read 5, iclass 7, count 0 2006.173.10:17:56.89#ibcon#about to read 6, iclass 7, count 0 2006.173.10:17:56.89#ibcon#read 6, iclass 7, count 0 2006.173.10:17:56.89#ibcon#end of sib2, iclass 7, count 0 2006.173.10:17:56.89#ibcon#*mode == 0, iclass 7, count 0 2006.173.10:17:56.89#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.10:17:56.89#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.10:17:56.89#ibcon#*before write, iclass 7, count 0 2006.173.10:17:56.89#ibcon#enter sib2, iclass 7, count 0 2006.173.10:17:56.89#ibcon#flushed, iclass 7, count 0 2006.173.10:17:56.89#ibcon#about to write, iclass 7, count 0 2006.173.10:17:56.89#ibcon#wrote, iclass 7, count 0 2006.173.10:17:56.89#ibcon#about to read 3, iclass 7, count 0 2006.173.10:17:56.93#ibcon#read 3, iclass 7, count 0 2006.173.10:17:56.93#ibcon#about to read 4, iclass 7, count 0 2006.173.10:17:56.93#ibcon#read 4, iclass 7, count 0 2006.173.10:17:56.93#ibcon#about to read 5, iclass 7, count 0 2006.173.10:17:56.93#ibcon#read 5, iclass 7, count 0 2006.173.10:17:56.93#ibcon#about to read 6, iclass 7, count 0 2006.173.10:17:56.93#ibcon#read 6, iclass 7, count 0 2006.173.10:17:56.93#ibcon#end of sib2, iclass 7, count 0 2006.173.10:17:56.93#ibcon#*after write, iclass 7, count 0 2006.173.10:17:56.93#ibcon#*before return 0, iclass 7, count 0 2006.173.10:17:56.93#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.10:17:56.93#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.10:17:56.93#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.10:17:56.93#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.10:17:56.93$vck44/vb=4,4 2006.173.10:17:56.93#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.10:17:56.93#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.10:17:56.93#ibcon#ireg 11 cls_cnt 2 2006.173.10:17:56.93#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.10:17:56.99#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.10:17:56.99#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.10:17:56.99#ibcon#enter wrdev, iclass 11, count 2 2006.173.10:17:56.99#ibcon#first serial, iclass 11, count 2 2006.173.10:17:56.99#ibcon#enter sib2, iclass 11, count 2 2006.173.10:17:56.99#ibcon#flushed, iclass 11, count 2 2006.173.10:17:56.99#ibcon#about to write, iclass 11, count 2 2006.173.10:17:56.99#ibcon#wrote, iclass 11, count 2 2006.173.10:17:56.99#ibcon#about to read 3, iclass 11, count 2 2006.173.10:17:57.01#ibcon#read 3, iclass 11, count 2 2006.173.10:17:57.01#ibcon#about to read 4, iclass 11, count 2 2006.173.10:17:57.01#ibcon#read 4, iclass 11, count 2 2006.173.10:17:57.01#ibcon#about to read 5, iclass 11, count 2 2006.173.10:17:57.01#ibcon#read 5, iclass 11, count 2 2006.173.10:17:57.01#ibcon#about to read 6, iclass 11, count 2 2006.173.10:17:57.01#ibcon#read 6, iclass 11, count 2 2006.173.10:17:57.01#ibcon#end of sib2, iclass 11, count 2 2006.173.10:17:57.01#ibcon#*mode == 0, iclass 11, count 2 2006.173.10:17:57.01#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.10:17:57.01#ibcon#[27=AT04-04\r\n] 2006.173.10:17:57.01#ibcon#*before write, iclass 11, count 2 2006.173.10:17:57.01#ibcon#enter sib2, iclass 11, count 2 2006.173.10:17:57.01#ibcon#flushed, iclass 11, count 2 2006.173.10:17:57.01#ibcon#about to write, iclass 11, count 2 2006.173.10:17:57.01#ibcon#wrote, iclass 11, count 2 2006.173.10:17:57.01#ibcon#about to read 3, iclass 11, count 2 2006.173.10:17:57.04#ibcon#read 3, iclass 11, count 2 2006.173.10:17:57.04#ibcon#about to read 4, iclass 11, count 2 2006.173.10:17:57.04#ibcon#read 4, iclass 11, count 2 2006.173.10:17:57.04#ibcon#about to read 5, iclass 11, count 2 2006.173.10:17:57.04#ibcon#read 5, iclass 11, count 2 2006.173.10:17:57.04#ibcon#about to read 6, iclass 11, count 2 2006.173.10:17:57.04#ibcon#read 6, iclass 11, count 2 2006.173.10:17:57.04#ibcon#end of sib2, iclass 11, count 2 2006.173.10:17:57.04#ibcon#*after write, iclass 11, count 2 2006.173.10:17:57.04#ibcon#*before return 0, iclass 11, count 2 2006.173.10:17:57.04#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.10:17:57.04#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.10:17:57.04#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.10:17:57.04#ibcon#ireg 7 cls_cnt 0 2006.173.10:17:57.04#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.10:17:57.16#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.10:17:57.16#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.10:17:57.16#ibcon#enter wrdev, iclass 11, count 0 2006.173.10:17:57.16#ibcon#first serial, iclass 11, count 0 2006.173.10:17:57.16#ibcon#enter sib2, iclass 11, count 0 2006.173.10:17:57.16#ibcon#flushed, iclass 11, count 0 2006.173.10:17:57.16#ibcon#about to write, iclass 11, count 0 2006.173.10:17:57.16#ibcon#wrote, iclass 11, count 0 2006.173.10:17:57.16#ibcon#about to read 3, iclass 11, count 0 2006.173.10:17:57.18#ibcon#read 3, iclass 11, count 0 2006.173.10:17:57.18#ibcon#about to read 4, iclass 11, count 0 2006.173.10:17:57.18#ibcon#read 4, iclass 11, count 0 2006.173.10:17:57.18#ibcon#about to read 5, iclass 11, count 0 2006.173.10:17:57.18#ibcon#read 5, iclass 11, count 0 2006.173.10:17:57.18#ibcon#about to read 6, iclass 11, count 0 2006.173.10:17:57.18#ibcon#read 6, iclass 11, count 0 2006.173.10:17:57.18#ibcon#end of sib2, iclass 11, count 0 2006.173.10:17:57.18#ibcon#*mode == 0, iclass 11, count 0 2006.173.10:17:57.18#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.10:17:57.18#ibcon#[27=USB\r\n] 2006.173.10:17:57.18#ibcon#*before write, iclass 11, count 0 2006.173.10:17:57.18#ibcon#enter sib2, iclass 11, count 0 2006.173.10:17:57.18#ibcon#flushed, iclass 11, count 0 2006.173.10:17:57.18#ibcon#about to write, iclass 11, count 0 2006.173.10:17:57.18#ibcon#wrote, iclass 11, count 0 2006.173.10:17:57.18#ibcon#about to read 3, iclass 11, count 0 2006.173.10:17:57.21#ibcon#read 3, iclass 11, count 0 2006.173.10:17:57.21#ibcon#about to read 4, iclass 11, count 0 2006.173.10:17:57.21#ibcon#read 4, iclass 11, count 0 2006.173.10:17:57.21#ibcon#about to read 5, iclass 11, count 0 2006.173.10:17:57.21#ibcon#read 5, iclass 11, count 0 2006.173.10:17:57.21#ibcon#about to read 6, iclass 11, count 0 2006.173.10:17:57.21#ibcon#read 6, iclass 11, count 0 2006.173.10:17:57.21#ibcon#end of sib2, iclass 11, count 0 2006.173.10:17:57.21#ibcon#*after write, iclass 11, count 0 2006.173.10:17:57.21#ibcon#*before return 0, iclass 11, count 0 2006.173.10:17:57.21#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.10:17:57.21#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.10:17:57.21#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.10:17:57.21#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.10:17:57.21$vck44/vblo=5,709.99 2006.173.10:17:57.21#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.10:17:57.21#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.10:17:57.21#ibcon#ireg 17 cls_cnt 0 2006.173.10:17:57.21#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.10:17:57.21#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.10:17:57.21#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.10:17:57.21#ibcon#enter wrdev, iclass 13, count 0 2006.173.10:17:57.21#ibcon#first serial, iclass 13, count 0 2006.173.10:17:57.21#ibcon#enter sib2, iclass 13, count 0 2006.173.10:17:57.21#ibcon#flushed, iclass 13, count 0 2006.173.10:17:57.21#ibcon#about to write, iclass 13, count 0 2006.173.10:17:57.21#ibcon#wrote, iclass 13, count 0 2006.173.10:17:57.21#ibcon#about to read 3, iclass 13, count 0 2006.173.10:17:57.23#ibcon#read 3, iclass 13, count 0 2006.173.10:17:57.23#ibcon#about to read 4, iclass 13, count 0 2006.173.10:17:57.23#ibcon#read 4, iclass 13, count 0 2006.173.10:17:57.23#ibcon#about to read 5, iclass 13, count 0 2006.173.10:17:57.23#ibcon#read 5, iclass 13, count 0 2006.173.10:17:57.23#ibcon#about to read 6, iclass 13, count 0 2006.173.10:17:57.23#ibcon#read 6, iclass 13, count 0 2006.173.10:17:57.23#ibcon#end of sib2, iclass 13, count 0 2006.173.10:17:57.23#ibcon#*mode == 0, iclass 13, count 0 2006.173.10:17:57.23#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.10:17:57.23#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.10:17:57.23#ibcon#*before write, iclass 13, count 0 2006.173.10:17:57.23#ibcon#enter sib2, iclass 13, count 0 2006.173.10:17:57.23#ibcon#flushed, iclass 13, count 0 2006.173.10:17:57.23#ibcon#about to write, iclass 13, count 0 2006.173.10:17:57.23#ibcon#wrote, iclass 13, count 0 2006.173.10:17:57.23#ibcon#about to read 3, iclass 13, count 0 2006.173.10:17:57.27#ibcon#read 3, iclass 13, count 0 2006.173.10:17:57.27#ibcon#about to read 4, iclass 13, count 0 2006.173.10:17:57.27#ibcon#read 4, iclass 13, count 0 2006.173.10:17:57.27#ibcon#about to read 5, iclass 13, count 0 2006.173.10:17:57.27#ibcon#read 5, iclass 13, count 0 2006.173.10:17:57.27#ibcon#about to read 6, iclass 13, count 0 2006.173.10:17:57.27#ibcon#read 6, iclass 13, count 0 2006.173.10:17:57.27#ibcon#end of sib2, iclass 13, count 0 2006.173.10:17:57.27#ibcon#*after write, iclass 13, count 0 2006.173.10:17:57.27#ibcon#*before return 0, iclass 13, count 0 2006.173.10:17:57.27#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.10:17:57.27#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.10:17:57.27#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.10:17:57.27#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.10:17:57.27$vck44/vb=5,4 2006.173.10:17:57.27#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.10:17:57.27#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.10:17:57.27#ibcon#ireg 11 cls_cnt 2 2006.173.10:17:57.27#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.10:17:57.33#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.10:17:57.33#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.10:17:57.33#ibcon#enter wrdev, iclass 15, count 2 2006.173.10:17:57.33#ibcon#first serial, iclass 15, count 2 2006.173.10:17:57.33#ibcon#enter sib2, iclass 15, count 2 2006.173.10:17:57.33#ibcon#flushed, iclass 15, count 2 2006.173.10:17:57.33#ibcon#about to write, iclass 15, count 2 2006.173.10:17:57.33#ibcon#wrote, iclass 15, count 2 2006.173.10:17:57.33#ibcon#about to read 3, iclass 15, count 2 2006.173.10:17:57.35#ibcon#read 3, iclass 15, count 2 2006.173.10:17:57.35#ibcon#about to read 4, iclass 15, count 2 2006.173.10:17:57.35#ibcon#read 4, iclass 15, count 2 2006.173.10:17:57.35#ibcon#about to read 5, iclass 15, count 2 2006.173.10:17:57.35#ibcon#read 5, iclass 15, count 2 2006.173.10:17:57.35#ibcon#about to read 6, iclass 15, count 2 2006.173.10:17:57.35#ibcon#read 6, iclass 15, count 2 2006.173.10:17:57.35#ibcon#end of sib2, iclass 15, count 2 2006.173.10:17:57.35#ibcon#*mode == 0, iclass 15, count 2 2006.173.10:17:57.35#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.10:17:57.35#ibcon#[27=AT05-04\r\n] 2006.173.10:17:57.35#ibcon#*before write, iclass 15, count 2 2006.173.10:17:57.35#ibcon#enter sib2, iclass 15, count 2 2006.173.10:17:57.35#ibcon#flushed, iclass 15, count 2 2006.173.10:17:57.35#ibcon#about to write, iclass 15, count 2 2006.173.10:17:57.35#ibcon#wrote, iclass 15, count 2 2006.173.10:17:57.35#ibcon#about to read 3, iclass 15, count 2 2006.173.10:17:57.38#ibcon#read 3, iclass 15, count 2 2006.173.10:17:57.38#ibcon#about to read 4, iclass 15, count 2 2006.173.10:17:57.38#ibcon#read 4, iclass 15, count 2 2006.173.10:17:57.38#ibcon#about to read 5, iclass 15, count 2 2006.173.10:17:57.38#ibcon#read 5, iclass 15, count 2 2006.173.10:17:57.38#ibcon#about to read 6, iclass 15, count 2 2006.173.10:17:57.38#ibcon#read 6, iclass 15, count 2 2006.173.10:17:57.38#ibcon#end of sib2, iclass 15, count 2 2006.173.10:17:57.38#ibcon#*after write, iclass 15, count 2 2006.173.10:17:57.38#ibcon#*before return 0, iclass 15, count 2 2006.173.10:17:57.38#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.10:17:57.38#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.10:17:57.38#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.10:17:57.38#ibcon#ireg 7 cls_cnt 0 2006.173.10:17:57.38#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.10:17:57.50#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.10:17:57.50#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.10:17:57.50#ibcon#enter wrdev, iclass 15, count 0 2006.173.10:17:57.50#ibcon#first serial, iclass 15, count 0 2006.173.10:17:57.50#ibcon#enter sib2, iclass 15, count 0 2006.173.10:17:57.50#ibcon#flushed, iclass 15, count 0 2006.173.10:17:57.50#ibcon#about to write, iclass 15, count 0 2006.173.10:17:57.50#ibcon#wrote, iclass 15, count 0 2006.173.10:17:57.50#ibcon#about to read 3, iclass 15, count 0 2006.173.10:17:57.52#ibcon#read 3, iclass 15, count 0 2006.173.10:17:57.52#ibcon#about to read 4, iclass 15, count 0 2006.173.10:17:57.52#ibcon#read 4, iclass 15, count 0 2006.173.10:17:57.52#ibcon#about to read 5, iclass 15, count 0 2006.173.10:17:57.52#ibcon#read 5, iclass 15, count 0 2006.173.10:17:57.52#ibcon#about to read 6, iclass 15, count 0 2006.173.10:17:57.52#ibcon#read 6, iclass 15, count 0 2006.173.10:17:57.52#ibcon#end of sib2, iclass 15, count 0 2006.173.10:17:57.52#ibcon#*mode == 0, iclass 15, count 0 2006.173.10:17:57.52#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.10:17:57.52#ibcon#[27=USB\r\n] 2006.173.10:17:57.52#ibcon#*before write, iclass 15, count 0 2006.173.10:17:57.52#ibcon#enter sib2, iclass 15, count 0 2006.173.10:17:57.52#ibcon#flushed, iclass 15, count 0 2006.173.10:17:57.52#ibcon#about to write, iclass 15, count 0 2006.173.10:17:57.52#ibcon#wrote, iclass 15, count 0 2006.173.10:17:57.52#ibcon#about to read 3, iclass 15, count 0 2006.173.10:17:57.55#ibcon#read 3, iclass 15, count 0 2006.173.10:17:57.55#ibcon#about to read 4, iclass 15, count 0 2006.173.10:17:57.55#ibcon#read 4, iclass 15, count 0 2006.173.10:17:57.55#ibcon#about to read 5, iclass 15, count 0 2006.173.10:17:57.55#ibcon#read 5, iclass 15, count 0 2006.173.10:17:57.55#ibcon#about to read 6, iclass 15, count 0 2006.173.10:17:57.55#ibcon#read 6, iclass 15, count 0 2006.173.10:17:57.55#ibcon#end of sib2, iclass 15, count 0 2006.173.10:17:57.55#ibcon#*after write, iclass 15, count 0 2006.173.10:17:57.55#ibcon#*before return 0, iclass 15, count 0 2006.173.10:17:57.55#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.10:17:57.55#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.10:17:57.55#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.10:17:57.55#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.10:17:57.55$vck44/vblo=6,719.99 2006.173.10:17:57.55#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.10:17:57.55#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.10:17:57.55#ibcon#ireg 17 cls_cnt 0 2006.173.10:17:57.55#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.10:17:57.55#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.10:17:57.55#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.10:17:57.55#ibcon#enter wrdev, iclass 17, count 0 2006.173.10:17:57.55#ibcon#first serial, iclass 17, count 0 2006.173.10:17:57.55#ibcon#enter sib2, iclass 17, count 0 2006.173.10:17:57.55#ibcon#flushed, iclass 17, count 0 2006.173.10:17:57.55#ibcon#about to write, iclass 17, count 0 2006.173.10:17:57.55#ibcon#wrote, iclass 17, count 0 2006.173.10:17:57.55#ibcon#about to read 3, iclass 17, count 0 2006.173.10:17:57.57#ibcon#read 3, iclass 17, count 0 2006.173.10:17:57.57#ibcon#about to read 4, iclass 17, count 0 2006.173.10:17:57.57#ibcon#read 4, iclass 17, count 0 2006.173.10:17:57.57#ibcon#about to read 5, iclass 17, count 0 2006.173.10:17:57.57#ibcon#read 5, iclass 17, count 0 2006.173.10:17:57.57#ibcon#about to read 6, iclass 17, count 0 2006.173.10:17:57.57#ibcon#read 6, iclass 17, count 0 2006.173.10:17:57.57#ibcon#end of sib2, iclass 17, count 0 2006.173.10:17:57.57#ibcon#*mode == 0, iclass 17, count 0 2006.173.10:17:57.57#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.10:17:57.57#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.10:17:57.57#ibcon#*before write, iclass 17, count 0 2006.173.10:17:57.57#ibcon#enter sib2, iclass 17, count 0 2006.173.10:17:57.57#ibcon#flushed, iclass 17, count 0 2006.173.10:17:57.57#ibcon#about to write, iclass 17, count 0 2006.173.10:17:57.57#ibcon#wrote, iclass 17, count 0 2006.173.10:17:57.57#ibcon#about to read 3, iclass 17, count 0 2006.173.10:17:57.61#ibcon#read 3, iclass 17, count 0 2006.173.10:17:57.61#ibcon#about to read 4, iclass 17, count 0 2006.173.10:17:57.61#ibcon#read 4, iclass 17, count 0 2006.173.10:17:57.61#ibcon#about to read 5, iclass 17, count 0 2006.173.10:17:57.61#ibcon#read 5, iclass 17, count 0 2006.173.10:17:57.61#ibcon#about to read 6, iclass 17, count 0 2006.173.10:17:57.61#ibcon#read 6, iclass 17, count 0 2006.173.10:17:57.61#ibcon#end of sib2, iclass 17, count 0 2006.173.10:17:57.61#ibcon#*after write, iclass 17, count 0 2006.173.10:17:57.61#ibcon#*before return 0, iclass 17, count 0 2006.173.10:17:57.61#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.10:17:57.61#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.10:17:57.61#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.10:17:57.61#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.10:17:57.61$vck44/vb=6,4 2006.173.10:17:57.61#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.10:17:57.61#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.10:17:57.61#ibcon#ireg 11 cls_cnt 2 2006.173.10:17:57.61#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.10:17:57.67#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.10:17:57.67#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.10:17:57.67#ibcon#enter wrdev, iclass 19, count 2 2006.173.10:17:57.67#ibcon#first serial, iclass 19, count 2 2006.173.10:17:57.67#ibcon#enter sib2, iclass 19, count 2 2006.173.10:17:57.67#ibcon#flushed, iclass 19, count 2 2006.173.10:17:57.67#ibcon#about to write, iclass 19, count 2 2006.173.10:17:57.67#ibcon#wrote, iclass 19, count 2 2006.173.10:17:57.67#ibcon#about to read 3, iclass 19, count 2 2006.173.10:17:57.69#ibcon#read 3, iclass 19, count 2 2006.173.10:17:57.69#ibcon#about to read 4, iclass 19, count 2 2006.173.10:17:57.69#ibcon#read 4, iclass 19, count 2 2006.173.10:17:57.69#ibcon#about to read 5, iclass 19, count 2 2006.173.10:17:57.69#ibcon#read 5, iclass 19, count 2 2006.173.10:17:57.69#ibcon#about to read 6, iclass 19, count 2 2006.173.10:17:57.69#ibcon#read 6, iclass 19, count 2 2006.173.10:17:57.69#ibcon#end of sib2, iclass 19, count 2 2006.173.10:17:57.69#ibcon#*mode == 0, iclass 19, count 2 2006.173.10:17:57.69#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.10:17:57.69#ibcon#[27=AT06-04\r\n] 2006.173.10:17:57.69#ibcon#*before write, iclass 19, count 2 2006.173.10:17:57.69#ibcon#enter sib2, iclass 19, count 2 2006.173.10:17:57.69#ibcon#flushed, iclass 19, count 2 2006.173.10:17:57.69#ibcon#about to write, iclass 19, count 2 2006.173.10:17:57.69#ibcon#wrote, iclass 19, count 2 2006.173.10:17:57.69#ibcon#about to read 3, iclass 19, count 2 2006.173.10:17:57.72#ibcon#read 3, iclass 19, count 2 2006.173.10:17:57.72#ibcon#about to read 4, iclass 19, count 2 2006.173.10:17:57.72#ibcon#read 4, iclass 19, count 2 2006.173.10:17:57.72#ibcon#about to read 5, iclass 19, count 2 2006.173.10:17:57.72#ibcon#read 5, iclass 19, count 2 2006.173.10:17:57.72#ibcon#about to read 6, iclass 19, count 2 2006.173.10:17:57.72#ibcon#read 6, iclass 19, count 2 2006.173.10:17:57.72#ibcon#end of sib2, iclass 19, count 2 2006.173.10:17:57.72#ibcon#*after write, iclass 19, count 2 2006.173.10:17:57.72#ibcon#*before return 0, iclass 19, count 2 2006.173.10:17:57.72#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.10:17:57.72#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.10:17:57.72#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.10:17:57.72#ibcon#ireg 7 cls_cnt 0 2006.173.10:17:57.72#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.10:17:57.84#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.10:17:57.84#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.10:17:57.84#ibcon#enter wrdev, iclass 19, count 0 2006.173.10:17:57.84#ibcon#first serial, iclass 19, count 0 2006.173.10:17:57.84#ibcon#enter sib2, iclass 19, count 0 2006.173.10:17:57.84#ibcon#flushed, iclass 19, count 0 2006.173.10:17:57.84#ibcon#about to write, iclass 19, count 0 2006.173.10:17:57.84#ibcon#wrote, iclass 19, count 0 2006.173.10:17:57.84#ibcon#about to read 3, iclass 19, count 0 2006.173.10:17:57.86#ibcon#read 3, iclass 19, count 0 2006.173.10:17:57.86#ibcon#about to read 4, iclass 19, count 0 2006.173.10:17:57.86#ibcon#read 4, iclass 19, count 0 2006.173.10:17:57.86#ibcon#about to read 5, iclass 19, count 0 2006.173.10:17:57.86#ibcon#read 5, iclass 19, count 0 2006.173.10:17:57.86#ibcon#about to read 6, iclass 19, count 0 2006.173.10:17:57.86#ibcon#read 6, iclass 19, count 0 2006.173.10:17:57.86#ibcon#end of sib2, iclass 19, count 0 2006.173.10:17:57.86#ibcon#*mode == 0, iclass 19, count 0 2006.173.10:17:57.86#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.10:17:57.86#ibcon#[27=USB\r\n] 2006.173.10:17:57.86#ibcon#*before write, iclass 19, count 0 2006.173.10:17:57.86#ibcon#enter sib2, iclass 19, count 0 2006.173.10:17:57.86#ibcon#flushed, iclass 19, count 0 2006.173.10:17:57.86#ibcon#about to write, iclass 19, count 0 2006.173.10:17:57.86#ibcon#wrote, iclass 19, count 0 2006.173.10:17:57.86#ibcon#about to read 3, iclass 19, count 0 2006.173.10:17:57.89#ibcon#read 3, iclass 19, count 0 2006.173.10:17:57.89#ibcon#about to read 4, iclass 19, count 0 2006.173.10:17:57.89#ibcon#read 4, iclass 19, count 0 2006.173.10:17:57.89#ibcon#about to read 5, iclass 19, count 0 2006.173.10:17:57.89#ibcon#read 5, iclass 19, count 0 2006.173.10:17:57.89#ibcon#about to read 6, iclass 19, count 0 2006.173.10:17:57.89#ibcon#read 6, iclass 19, count 0 2006.173.10:17:57.89#ibcon#end of sib2, iclass 19, count 0 2006.173.10:17:57.89#ibcon#*after write, iclass 19, count 0 2006.173.10:17:57.89#ibcon#*before return 0, iclass 19, count 0 2006.173.10:17:57.89#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.10:17:57.89#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.10:17:57.89#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.10:17:57.89#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.10:17:57.89$vck44/vblo=7,734.99 2006.173.10:17:57.89#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.10:17:57.89#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.10:17:57.89#ibcon#ireg 17 cls_cnt 0 2006.173.10:17:57.89#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.10:17:57.89#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.10:17:57.89#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.10:17:57.89#ibcon#enter wrdev, iclass 21, count 0 2006.173.10:17:57.89#ibcon#first serial, iclass 21, count 0 2006.173.10:17:57.89#ibcon#enter sib2, iclass 21, count 0 2006.173.10:17:57.89#ibcon#flushed, iclass 21, count 0 2006.173.10:17:57.89#ibcon#about to write, iclass 21, count 0 2006.173.10:17:57.89#ibcon#wrote, iclass 21, count 0 2006.173.10:17:57.89#ibcon#about to read 3, iclass 21, count 0 2006.173.10:17:57.91#ibcon#read 3, iclass 21, count 0 2006.173.10:17:57.91#ibcon#about to read 4, iclass 21, count 0 2006.173.10:17:57.91#ibcon#read 4, iclass 21, count 0 2006.173.10:17:57.91#ibcon#about to read 5, iclass 21, count 0 2006.173.10:17:57.91#ibcon#read 5, iclass 21, count 0 2006.173.10:17:57.91#ibcon#about to read 6, iclass 21, count 0 2006.173.10:17:57.91#ibcon#read 6, iclass 21, count 0 2006.173.10:17:57.91#ibcon#end of sib2, iclass 21, count 0 2006.173.10:17:57.91#ibcon#*mode == 0, iclass 21, count 0 2006.173.10:17:57.91#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.10:17:57.91#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.10:17:57.91#ibcon#*before write, iclass 21, count 0 2006.173.10:17:57.91#ibcon#enter sib2, iclass 21, count 0 2006.173.10:17:57.91#ibcon#flushed, iclass 21, count 0 2006.173.10:17:57.91#ibcon#about to write, iclass 21, count 0 2006.173.10:17:57.91#ibcon#wrote, iclass 21, count 0 2006.173.10:17:57.91#ibcon#about to read 3, iclass 21, count 0 2006.173.10:17:57.95#ibcon#read 3, iclass 21, count 0 2006.173.10:17:57.95#ibcon#about to read 4, iclass 21, count 0 2006.173.10:17:57.95#ibcon#read 4, iclass 21, count 0 2006.173.10:17:57.95#ibcon#about to read 5, iclass 21, count 0 2006.173.10:17:57.95#ibcon#read 5, iclass 21, count 0 2006.173.10:17:57.95#ibcon#about to read 6, iclass 21, count 0 2006.173.10:17:57.95#ibcon#read 6, iclass 21, count 0 2006.173.10:17:57.95#ibcon#end of sib2, iclass 21, count 0 2006.173.10:17:57.95#ibcon#*after write, iclass 21, count 0 2006.173.10:17:57.95#ibcon#*before return 0, iclass 21, count 0 2006.173.10:17:57.95#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.10:17:57.95#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.10:17:57.95#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.10:17:57.95#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.10:17:57.95$vck44/vb=7,4 2006.173.10:17:57.95#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.10:17:57.95#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.10:17:57.95#ibcon#ireg 11 cls_cnt 2 2006.173.10:17:57.95#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.10:17:58.01#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.10:17:58.01#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.10:17:58.01#ibcon#enter wrdev, iclass 23, count 2 2006.173.10:17:58.01#ibcon#first serial, iclass 23, count 2 2006.173.10:17:58.01#ibcon#enter sib2, iclass 23, count 2 2006.173.10:17:58.01#ibcon#flushed, iclass 23, count 2 2006.173.10:17:58.01#ibcon#about to write, iclass 23, count 2 2006.173.10:17:58.01#ibcon#wrote, iclass 23, count 2 2006.173.10:17:58.01#ibcon#about to read 3, iclass 23, count 2 2006.173.10:17:58.03#ibcon#read 3, iclass 23, count 2 2006.173.10:17:58.03#ibcon#about to read 4, iclass 23, count 2 2006.173.10:17:58.03#ibcon#read 4, iclass 23, count 2 2006.173.10:17:58.03#ibcon#about to read 5, iclass 23, count 2 2006.173.10:17:58.03#ibcon#read 5, iclass 23, count 2 2006.173.10:17:58.03#ibcon#about to read 6, iclass 23, count 2 2006.173.10:17:58.03#ibcon#read 6, iclass 23, count 2 2006.173.10:17:58.03#ibcon#end of sib2, iclass 23, count 2 2006.173.10:17:58.03#ibcon#*mode == 0, iclass 23, count 2 2006.173.10:17:58.03#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.10:17:58.03#ibcon#[27=AT07-04\r\n] 2006.173.10:17:58.03#ibcon#*before write, iclass 23, count 2 2006.173.10:17:58.03#ibcon#enter sib2, iclass 23, count 2 2006.173.10:17:58.03#ibcon#flushed, iclass 23, count 2 2006.173.10:17:58.03#ibcon#about to write, iclass 23, count 2 2006.173.10:17:58.03#ibcon#wrote, iclass 23, count 2 2006.173.10:17:58.03#ibcon#about to read 3, iclass 23, count 2 2006.173.10:17:58.06#ibcon#read 3, iclass 23, count 2 2006.173.10:17:58.06#ibcon#about to read 4, iclass 23, count 2 2006.173.10:17:58.06#ibcon#read 4, iclass 23, count 2 2006.173.10:17:58.06#ibcon#about to read 5, iclass 23, count 2 2006.173.10:17:58.06#ibcon#read 5, iclass 23, count 2 2006.173.10:17:58.06#ibcon#about to read 6, iclass 23, count 2 2006.173.10:17:58.06#ibcon#read 6, iclass 23, count 2 2006.173.10:17:58.06#ibcon#end of sib2, iclass 23, count 2 2006.173.10:17:58.06#ibcon#*after write, iclass 23, count 2 2006.173.10:17:58.06#ibcon#*before return 0, iclass 23, count 2 2006.173.10:17:58.06#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.10:17:58.06#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.10:17:58.06#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.10:17:58.06#ibcon#ireg 7 cls_cnt 0 2006.173.10:17:58.06#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.10:17:58.18#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.10:17:58.18#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.10:17:58.18#ibcon#enter wrdev, iclass 23, count 0 2006.173.10:17:58.18#ibcon#first serial, iclass 23, count 0 2006.173.10:17:58.18#ibcon#enter sib2, iclass 23, count 0 2006.173.10:17:58.18#ibcon#flushed, iclass 23, count 0 2006.173.10:17:58.18#ibcon#about to write, iclass 23, count 0 2006.173.10:17:58.18#ibcon#wrote, iclass 23, count 0 2006.173.10:17:58.18#ibcon#about to read 3, iclass 23, count 0 2006.173.10:17:58.20#ibcon#read 3, iclass 23, count 0 2006.173.10:17:58.20#ibcon#about to read 4, iclass 23, count 0 2006.173.10:17:58.20#ibcon#read 4, iclass 23, count 0 2006.173.10:17:58.20#ibcon#about to read 5, iclass 23, count 0 2006.173.10:17:58.20#ibcon#read 5, iclass 23, count 0 2006.173.10:17:58.20#ibcon#about to read 6, iclass 23, count 0 2006.173.10:17:58.20#ibcon#read 6, iclass 23, count 0 2006.173.10:17:58.20#ibcon#end of sib2, iclass 23, count 0 2006.173.10:17:58.20#ibcon#*mode == 0, iclass 23, count 0 2006.173.10:17:58.20#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.10:17:58.20#ibcon#[27=USB\r\n] 2006.173.10:17:58.20#ibcon#*before write, iclass 23, count 0 2006.173.10:17:58.20#ibcon#enter sib2, iclass 23, count 0 2006.173.10:17:58.20#ibcon#flushed, iclass 23, count 0 2006.173.10:17:58.20#ibcon#about to write, iclass 23, count 0 2006.173.10:17:58.20#ibcon#wrote, iclass 23, count 0 2006.173.10:17:58.20#ibcon#about to read 3, iclass 23, count 0 2006.173.10:17:58.23#ibcon#read 3, iclass 23, count 0 2006.173.10:17:58.23#ibcon#about to read 4, iclass 23, count 0 2006.173.10:17:58.23#ibcon#read 4, iclass 23, count 0 2006.173.10:17:58.23#ibcon#about to read 5, iclass 23, count 0 2006.173.10:17:58.23#ibcon#read 5, iclass 23, count 0 2006.173.10:17:58.23#ibcon#about to read 6, iclass 23, count 0 2006.173.10:17:58.23#ibcon#read 6, iclass 23, count 0 2006.173.10:17:58.23#ibcon#end of sib2, iclass 23, count 0 2006.173.10:17:58.23#ibcon#*after write, iclass 23, count 0 2006.173.10:17:58.23#ibcon#*before return 0, iclass 23, count 0 2006.173.10:17:58.23#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.10:17:58.23#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.10:17:58.23#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.10:17:58.23#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.10:17:58.23$vck44/vblo=8,744.99 2006.173.10:17:58.23#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.10:17:58.23#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.10:17:58.23#ibcon#ireg 17 cls_cnt 0 2006.173.10:17:58.23#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.10:17:58.23#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.10:17:58.23#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.10:17:58.23#ibcon#enter wrdev, iclass 25, count 0 2006.173.10:17:58.23#ibcon#first serial, iclass 25, count 0 2006.173.10:17:58.23#ibcon#enter sib2, iclass 25, count 0 2006.173.10:17:58.23#ibcon#flushed, iclass 25, count 0 2006.173.10:17:58.23#ibcon#about to write, iclass 25, count 0 2006.173.10:17:58.23#ibcon#wrote, iclass 25, count 0 2006.173.10:17:58.23#ibcon#about to read 3, iclass 25, count 0 2006.173.10:17:58.25#ibcon#read 3, iclass 25, count 0 2006.173.10:17:58.25#ibcon#about to read 4, iclass 25, count 0 2006.173.10:17:58.25#ibcon#read 4, iclass 25, count 0 2006.173.10:17:58.25#ibcon#about to read 5, iclass 25, count 0 2006.173.10:17:58.25#ibcon#read 5, iclass 25, count 0 2006.173.10:17:58.25#ibcon#about to read 6, iclass 25, count 0 2006.173.10:17:58.25#ibcon#read 6, iclass 25, count 0 2006.173.10:17:58.25#ibcon#end of sib2, iclass 25, count 0 2006.173.10:17:58.25#ibcon#*mode == 0, iclass 25, count 0 2006.173.10:17:58.25#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.10:17:58.25#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.10:17:58.25#ibcon#*before write, iclass 25, count 0 2006.173.10:17:58.25#ibcon#enter sib2, iclass 25, count 0 2006.173.10:17:58.25#ibcon#flushed, iclass 25, count 0 2006.173.10:17:58.25#ibcon#about to write, iclass 25, count 0 2006.173.10:17:58.25#ibcon#wrote, iclass 25, count 0 2006.173.10:17:58.25#ibcon#about to read 3, iclass 25, count 0 2006.173.10:17:58.29#ibcon#read 3, iclass 25, count 0 2006.173.10:17:58.29#ibcon#about to read 4, iclass 25, count 0 2006.173.10:17:58.29#ibcon#read 4, iclass 25, count 0 2006.173.10:17:58.29#ibcon#about to read 5, iclass 25, count 0 2006.173.10:17:58.29#ibcon#read 5, iclass 25, count 0 2006.173.10:17:58.29#ibcon#about to read 6, iclass 25, count 0 2006.173.10:17:58.29#ibcon#read 6, iclass 25, count 0 2006.173.10:17:58.29#ibcon#end of sib2, iclass 25, count 0 2006.173.10:17:58.29#ibcon#*after write, iclass 25, count 0 2006.173.10:17:58.29#ibcon#*before return 0, iclass 25, count 0 2006.173.10:17:58.29#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.10:17:58.29#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.10:17:58.29#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.10:17:58.29#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.10:17:58.29$vck44/vb=8,4 2006.173.10:17:58.29#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.10:17:58.29#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.10:17:58.29#ibcon#ireg 11 cls_cnt 2 2006.173.10:17:58.29#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.10:17:58.35#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.10:17:58.35#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.10:17:58.35#ibcon#enter wrdev, iclass 27, count 2 2006.173.10:17:58.35#ibcon#first serial, iclass 27, count 2 2006.173.10:17:58.35#ibcon#enter sib2, iclass 27, count 2 2006.173.10:17:58.35#ibcon#flushed, iclass 27, count 2 2006.173.10:17:58.35#ibcon#about to write, iclass 27, count 2 2006.173.10:17:58.35#ibcon#wrote, iclass 27, count 2 2006.173.10:17:58.35#ibcon#about to read 3, iclass 27, count 2 2006.173.10:17:58.37#ibcon#read 3, iclass 27, count 2 2006.173.10:17:58.37#ibcon#about to read 4, iclass 27, count 2 2006.173.10:17:58.37#ibcon#read 4, iclass 27, count 2 2006.173.10:17:58.37#ibcon#about to read 5, iclass 27, count 2 2006.173.10:17:58.37#ibcon#read 5, iclass 27, count 2 2006.173.10:17:58.37#ibcon#about to read 6, iclass 27, count 2 2006.173.10:17:58.37#ibcon#read 6, iclass 27, count 2 2006.173.10:17:58.37#ibcon#end of sib2, iclass 27, count 2 2006.173.10:17:58.37#ibcon#*mode == 0, iclass 27, count 2 2006.173.10:17:58.37#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.10:17:58.37#ibcon#[27=AT08-04\r\n] 2006.173.10:17:58.37#ibcon#*before write, iclass 27, count 2 2006.173.10:17:58.37#ibcon#enter sib2, iclass 27, count 2 2006.173.10:17:58.37#ibcon#flushed, iclass 27, count 2 2006.173.10:17:58.37#ibcon#about to write, iclass 27, count 2 2006.173.10:17:58.37#ibcon#wrote, iclass 27, count 2 2006.173.10:17:58.37#ibcon#about to read 3, iclass 27, count 2 2006.173.10:17:58.40#ibcon#read 3, iclass 27, count 2 2006.173.10:17:58.40#ibcon#about to read 4, iclass 27, count 2 2006.173.10:17:58.40#ibcon#read 4, iclass 27, count 2 2006.173.10:17:58.40#ibcon#about to read 5, iclass 27, count 2 2006.173.10:17:58.40#ibcon#read 5, iclass 27, count 2 2006.173.10:17:58.40#ibcon#about to read 6, iclass 27, count 2 2006.173.10:17:58.40#ibcon#read 6, iclass 27, count 2 2006.173.10:17:58.40#ibcon#end of sib2, iclass 27, count 2 2006.173.10:17:58.40#ibcon#*after write, iclass 27, count 2 2006.173.10:17:58.40#ibcon#*before return 0, iclass 27, count 2 2006.173.10:17:58.40#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.10:17:58.40#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.10:17:58.40#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.10:17:58.40#ibcon#ireg 7 cls_cnt 0 2006.173.10:17:58.40#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.10:17:58.52#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.10:17:58.52#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.10:17:58.52#ibcon#enter wrdev, iclass 27, count 0 2006.173.10:17:58.52#ibcon#first serial, iclass 27, count 0 2006.173.10:17:58.52#ibcon#enter sib2, iclass 27, count 0 2006.173.10:17:58.52#ibcon#flushed, iclass 27, count 0 2006.173.10:17:58.52#ibcon#about to write, iclass 27, count 0 2006.173.10:17:58.52#ibcon#wrote, iclass 27, count 0 2006.173.10:17:58.52#ibcon#about to read 3, iclass 27, count 0 2006.173.10:17:58.54#ibcon#read 3, iclass 27, count 0 2006.173.10:17:58.54#ibcon#about to read 4, iclass 27, count 0 2006.173.10:17:58.54#ibcon#read 4, iclass 27, count 0 2006.173.10:17:58.54#ibcon#about to read 5, iclass 27, count 0 2006.173.10:17:58.54#ibcon#read 5, iclass 27, count 0 2006.173.10:17:58.54#ibcon#about to read 6, iclass 27, count 0 2006.173.10:17:58.54#ibcon#read 6, iclass 27, count 0 2006.173.10:17:58.54#ibcon#end of sib2, iclass 27, count 0 2006.173.10:17:58.54#ibcon#*mode == 0, iclass 27, count 0 2006.173.10:17:58.54#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.10:17:58.54#ibcon#[27=USB\r\n] 2006.173.10:17:58.54#ibcon#*before write, iclass 27, count 0 2006.173.10:17:58.54#ibcon#enter sib2, iclass 27, count 0 2006.173.10:17:58.54#ibcon#flushed, iclass 27, count 0 2006.173.10:17:58.54#ibcon#about to write, iclass 27, count 0 2006.173.10:17:58.54#ibcon#wrote, iclass 27, count 0 2006.173.10:17:58.54#ibcon#about to read 3, iclass 27, count 0 2006.173.10:17:58.57#ibcon#read 3, iclass 27, count 0 2006.173.10:17:58.57#ibcon#about to read 4, iclass 27, count 0 2006.173.10:17:58.57#ibcon#read 4, iclass 27, count 0 2006.173.10:17:58.57#ibcon#about to read 5, iclass 27, count 0 2006.173.10:17:58.57#ibcon#read 5, iclass 27, count 0 2006.173.10:17:58.57#ibcon#about to read 6, iclass 27, count 0 2006.173.10:17:58.57#ibcon#read 6, iclass 27, count 0 2006.173.10:17:58.57#ibcon#end of sib2, iclass 27, count 0 2006.173.10:17:58.57#ibcon#*after write, iclass 27, count 0 2006.173.10:17:58.57#ibcon#*before return 0, iclass 27, count 0 2006.173.10:17:58.57#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.10:17:58.57#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.10:17:58.57#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.10:17:58.57#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.10:17:58.57$vck44/vabw=wide 2006.173.10:17:58.57#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.10:17:58.57#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.10:17:58.57#ibcon#ireg 8 cls_cnt 0 2006.173.10:17:58.57#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.10:17:58.57#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.10:17:58.57#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.10:17:58.57#ibcon#enter wrdev, iclass 29, count 0 2006.173.10:17:58.57#ibcon#first serial, iclass 29, count 0 2006.173.10:17:58.57#ibcon#enter sib2, iclass 29, count 0 2006.173.10:17:58.57#ibcon#flushed, iclass 29, count 0 2006.173.10:17:58.57#ibcon#about to write, iclass 29, count 0 2006.173.10:17:58.57#ibcon#wrote, iclass 29, count 0 2006.173.10:17:58.57#ibcon#about to read 3, iclass 29, count 0 2006.173.10:17:58.59#ibcon#read 3, iclass 29, count 0 2006.173.10:17:58.59#ibcon#about to read 4, iclass 29, count 0 2006.173.10:17:58.59#ibcon#read 4, iclass 29, count 0 2006.173.10:17:58.59#ibcon#about to read 5, iclass 29, count 0 2006.173.10:17:58.59#ibcon#read 5, iclass 29, count 0 2006.173.10:17:58.59#ibcon#about to read 6, iclass 29, count 0 2006.173.10:17:58.59#ibcon#read 6, iclass 29, count 0 2006.173.10:17:58.59#ibcon#end of sib2, iclass 29, count 0 2006.173.10:17:58.59#ibcon#*mode == 0, iclass 29, count 0 2006.173.10:17:58.59#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.10:17:58.59#ibcon#[25=BW32\r\n] 2006.173.10:17:58.59#ibcon#*before write, iclass 29, count 0 2006.173.10:17:58.59#ibcon#enter sib2, iclass 29, count 0 2006.173.10:17:58.59#ibcon#flushed, iclass 29, count 0 2006.173.10:17:58.59#ibcon#about to write, iclass 29, count 0 2006.173.10:17:58.59#ibcon#wrote, iclass 29, count 0 2006.173.10:17:58.59#ibcon#about to read 3, iclass 29, count 0 2006.173.10:17:58.62#ibcon#read 3, iclass 29, count 0 2006.173.10:17:58.62#ibcon#about to read 4, iclass 29, count 0 2006.173.10:17:58.62#ibcon#read 4, iclass 29, count 0 2006.173.10:17:58.62#ibcon#about to read 5, iclass 29, count 0 2006.173.10:17:58.62#ibcon#read 5, iclass 29, count 0 2006.173.10:17:58.62#ibcon#about to read 6, iclass 29, count 0 2006.173.10:17:58.62#ibcon#read 6, iclass 29, count 0 2006.173.10:17:58.62#ibcon#end of sib2, iclass 29, count 0 2006.173.10:17:58.62#ibcon#*after write, iclass 29, count 0 2006.173.10:17:58.62#ibcon#*before return 0, iclass 29, count 0 2006.173.10:17:58.62#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.10:17:58.62#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.10:17:58.62#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.10:17:58.62#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.10:17:58.62$vck44/vbbw=wide 2006.173.10:17:58.62#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.10:17:58.62#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.10:17:58.62#ibcon#ireg 8 cls_cnt 0 2006.173.10:17:58.62#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.10:17:58.69#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.10:17:58.69#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.10:17:58.69#ibcon#enter wrdev, iclass 31, count 0 2006.173.10:17:58.69#ibcon#first serial, iclass 31, count 0 2006.173.10:17:58.69#ibcon#enter sib2, iclass 31, count 0 2006.173.10:17:58.69#ibcon#flushed, iclass 31, count 0 2006.173.10:17:58.69#ibcon#about to write, iclass 31, count 0 2006.173.10:17:58.69#ibcon#wrote, iclass 31, count 0 2006.173.10:17:58.69#ibcon#about to read 3, iclass 31, count 0 2006.173.10:17:58.71#ibcon#read 3, iclass 31, count 0 2006.173.10:17:58.71#ibcon#about to read 4, iclass 31, count 0 2006.173.10:17:58.71#ibcon#read 4, iclass 31, count 0 2006.173.10:17:58.71#ibcon#about to read 5, iclass 31, count 0 2006.173.10:17:58.71#ibcon#read 5, iclass 31, count 0 2006.173.10:17:58.71#ibcon#about to read 6, iclass 31, count 0 2006.173.10:17:58.71#ibcon#read 6, iclass 31, count 0 2006.173.10:17:58.71#ibcon#end of sib2, iclass 31, count 0 2006.173.10:17:58.71#ibcon#*mode == 0, iclass 31, count 0 2006.173.10:17:58.71#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.10:17:58.71#ibcon#[27=BW32\r\n] 2006.173.10:17:58.71#ibcon#*before write, iclass 31, count 0 2006.173.10:17:58.71#ibcon#enter sib2, iclass 31, count 0 2006.173.10:17:58.71#ibcon#flushed, iclass 31, count 0 2006.173.10:17:58.71#ibcon#about to write, iclass 31, count 0 2006.173.10:17:58.71#ibcon#wrote, iclass 31, count 0 2006.173.10:17:58.71#ibcon#about to read 3, iclass 31, count 0 2006.173.10:17:58.74#ibcon#read 3, iclass 31, count 0 2006.173.10:17:58.74#ibcon#about to read 4, iclass 31, count 0 2006.173.10:17:58.74#ibcon#read 4, iclass 31, count 0 2006.173.10:17:58.74#ibcon#about to read 5, iclass 31, count 0 2006.173.10:17:58.74#ibcon#read 5, iclass 31, count 0 2006.173.10:17:58.74#ibcon#about to read 6, iclass 31, count 0 2006.173.10:17:58.74#ibcon#read 6, iclass 31, count 0 2006.173.10:17:58.74#ibcon#end of sib2, iclass 31, count 0 2006.173.10:17:58.74#ibcon#*after write, iclass 31, count 0 2006.173.10:17:58.74#ibcon#*before return 0, iclass 31, count 0 2006.173.10:17:58.74#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.10:17:58.74#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.10:17:58.74#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.10:17:58.74#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.10:17:58.74$setupk4/ifdk4 2006.173.10:17:58.74$ifdk4/lo= 2006.173.10:17:58.74$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.10:17:58.74$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.10:17:58.74$ifdk4/patch= 2006.173.10:17:58.74$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.10:17:58.74$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.10:17:58.74$setupk4/!*+20s 2006.173.10:17:59.35#abcon#<5=/05 0.8 1.4 22.75 901004.1\r\n> 2006.173.10:17:59.37#abcon#{5=INTERFACE CLEAR} 2006.173.10:17:59.43#abcon#[5=S1D000X0/0*\r\n] 2006.173.10:18:09.52#abcon#<5=/05 0.8 1.4 22.75 901004.1\r\n> 2006.173.10:18:09.54#abcon#{5=INTERFACE CLEAR} 2006.173.10:18:09.60#abcon#[5=S1D000X0/0*\r\n] 2006.173.10:18:11.14#trakl#Source acquired 2006.173.10:18:13.14#flagr#flagr/antenna,acquired 2006.173.10:18:13.25$setupk4/"tpicd 2006.173.10:18:13.25$setupk4/echo=off 2006.173.10:18:13.25$setupk4/xlog=off 2006.173.10:18:13.25:!2006.173.10:18:27 2006.173.10:18:27.00:preob 2006.173.10:18:27.14/onsource/TRACKING 2006.173.10:18:27.14:!2006.173.10:18:37 2006.173.10:18:37.00:"tape 2006.173.10:18:37.00:"st=record 2006.173.10:18:37.00:data_valid=on 2006.173.10:18:37.00:midob 2006.173.10:18:37.14/onsource/TRACKING 2006.173.10:18:37.14/wx/22.75,1004.1,90 2006.173.10:18:37.32/cable/+6.5012E-03 2006.173.10:18:38.41/va/01,07,usb,yes,34,37 2006.173.10:18:38.41/va/02,06,usb,yes,34,35 2006.173.10:18:38.41/va/03,05,usb,yes,44,45 2006.173.10:18:38.41/va/04,06,usb,yes,35,37 2006.173.10:18:38.41/va/05,04,usb,yes,27,28 2006.173.10:18:38.41/va/06,03,usb,yes,38,38 2006.173.10:18:38.41/va/07,04,usb,yes,31,32 2006.173.10:18:38.41/va/08,04,usb,yes,26,32 2006.173.10:18:38.64/valo/01,524.99,yes,locked 2006.173.10:18:38.64/valo/02,534.99,yes,locked 2006.173.10:18:38.64/valo/03,564.99,yes,locked 2006.173.10:18:38.64/valo/04,624.99,yes,locked 2006.173.10:18:38.64/valo/05,734.99,yes,locked 2006.173.10:18:38.64/valo/06,814.99,yes,locked 2006.173.10:18:38.64/valo/07,864.99,yes,locked 2006.173.10:18:38.64/valo/08,884.99,yes,locked 2006.173.10:18:39.73/vb/01,04,usb,yes,29,27 2006.173.10:18:39.73/vb/02,04,usb,yes,31,31 2006.173.10:18:39.73/vb/03,04,usb,yes,28,31 2006.173.10:18:39.73/vb/04,04,usb,yes,32,31 2006.173.10:18:39.73/vb/05,04,usb,yes,25,28 2006.173.10:18:39.73/vb/06,04,usb,yes,29,26 2006.173.10:18:39.73/vb/07,04,usb,yes,29,29 2006.173.10:18:39.73/vb/08,04,usb,yes,27,30 2006.173.10:18:39.97/vblo/01,629.99,yes,locked 2006.173.10:18:39.97/vblo/02,634.99,yes,locked 2006.173.10:18:39.97/vblo/03,649.99,yes,locked 2006.173.10:18:39.97/vblo/04,679.99,yes,locked 2006.173.10:18:39.97/vblo/05,709.99,yes,locked 2006.173.10:18:39.97/vblo/06,719.99,yes,locked 2006.173.10:18:39.97/vblo/07,734.99,yes,locked 2006.173.10:18:39.97/vblo/08,744.99,yes,locked 2006.173.10:18:40.12/vabw/8 2006.173.10:18:40.27/vbbw/8 2006.173.10:18:40.36/xfe/off,on,14.7 2006.173.10:18:40.74/ifatt/23,28,28,28 2006.173.10:18:41.08/fmout-gps/S +4.02E-07 2006.173.10:18:41.11:!2006.173.10:22:17 2006.173.10:22:17.02:data_valid=off 2006.173.10:22:17.02:"et 2006.173.10:22:17.02:!+3s 2006.173.10:22:20.04:"tape 2006.173.10:22:20.05:postob 2006.173.10:22:20.24/cable/+6.5020E-03 2006.173.10:22:20.24/wx/22.72,1004.3,90 2006.173.10:22:20.30/fmout-gps/S +4.03E-07 2006.173.10:22:20.30:scan_name=173-1025,jd0606,410 2006.173.10:22:20.30:source=1418+546,141946.60,542314.8,2000.0,cw 2006.173.10:22:22.14#flagr#flagr/antenna,new-source 2006.173.10:22:22.14:checkk5 2006.173.10:22:22.49/chk_autoobs//k5ts1/ autoobs is running! 2006.173.10:22:22.90/chk_autoobs//k5ts2/ autoobs is running! 2006.173.10:22:23.33/chk_autoobs//k5ts3/ autoobs is running! 2006.173.10:22:23.73/chk_autoobs//k5ts4/ autoobs is running! 2006.173.10:22:24.11/chk_obsdata//k5ts1/T1731018??a.dat file size is correct (nominal:880MB, actual:876MB). 2006.173.10:22:24.52/chk_obsdata//k5ts2/T1731018??b.dat file size is correct (nominal:880MB, actual:876MB). 2006.173.10:22:24.93/chk_obsdata//k5ts3/T1731018??c.dat file size is correct (nominal:880MB, actual:876MB). 2006.173.10:22:25.36/chk_obsdata//k5ts4/T1731018??d.dat file size is correct (nominal:880MB, actual:876MB). 2006.173.10:22:26.07/k5log//k5ts1_log_newline 2006.173.10:22:26.79/k5log//k5ts2_log_newline 2006.173.10:22:27.50/k5log//k5ts3_log_newline 2006.173.10:22:28.22/k5log//k5ts4_log_newline 2006.173.10:22:28.25/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.10:22:28.25:setupk4=1 2006.173.10:22:28.25$setupk4/echo=on 2006.173.10:22:28.25$setupk4/pcalon 2006.173.10:22:28.25$pcalon/"no phase cal control is implemented here 2006.173.10:22:28.25$setupk4/"tpicd=stop 2006.173.10:22:28.25$setupk4/"rec=synch_on 2006.173.10:22:28.25$setupk4/"rec_mode=128 2006.173.10:22:28.25$setupk4/!* 2006.173.10:22:28.25$setupk4/recpk4 2006.173.10:22:28.25$recpk4/recpatch= 2006.173.10:22:28.25$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.10:22:28.25$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.10:22:28.25$setupk4/vck44 2006.173.10:22:28.25$vck44/valo=1,524.99 2006.173.10:22:28.25#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.10:22:28.25#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.10:22:28.25#ibcon#ireg 17 cls_cnt 0 2006.173.10:22:28.25#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.10:22:28.25#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.10:22:28.25#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.10:22:28.25#ibcon#enter wrdev, iclass 36, count 0 2006.173.10:22:28.25#ibcon#first serial, iclass 36, count 0 2006.173.10:22:28.25#ibcon#enter sib2, iclass 36, count 0 2006.173.10:22:28.25#ibcon#flushed, iclass 36, count 0 2006.173.10:22:28.25#ibcon#about to write, iclass 36, count 0 2006.173.10:22:28.25#ibcon#wrote, iclass 36, count 0 2006.173.10:22:28.25#ibcon#about to read 3, iclass 36, count 0 2006.173.10:22:28.26#ibcon#read 3, iclass 36, count 0 2006.173.10:22:28.26#ibcon#about to read 4, iclass 36, count 0 2006.173.10:22:28.26#ibcon#read 4, iclass 36, count 0 2006.173.10:22:28.26#ibcon#about to read 5, iclass 36, count 0 2006.173.10:22:28.26#ibcon#read 5, iclass 36, count 0 2006.173.10:22:28.27#ibcon#about to read 6, iclass 36, count 0 2006.173.10:22:28.27#ibcon#read 6, iclass 36, count 0 2006.173.10:22:28.27#ibcon#end of sib2, iclass 36, count 0 2006.173.10:22:28.27#ibcon#*mode == 0, iclass 36, count 0 2006.173.10:22:28.27#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.10:22:28.27#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.10:22:28.27#ibcon#*before write, iclass 36, count 0 2006.173.10:22:28.27#ibcon#enter sib2, iclass 36, count 0 2006.173.10:22:28.27#ibcon#flushed, iclass 36, count 0 2006.173.10:22:28.27#ibcon#about to write, iclass 36, count 0 2006.173.10:22:28.27#ibcon#wrote, iclass 36, count 0 2006.173.10:22:28.27#ibcon#about to read 3, iclass 36, count 0 2006.173.10:22:28.31#ibcon#read 3, iclass 36, count 0 2006.173.10:22:28.31#ibcon#about to read 4, iclass 36, count 0 2006.173.10:22:28.31#ibcon#read 4, iclass 36, count 0 2006.173.10:22:28.31#ibcon#about to read 5, iclass 36, count 0 2006.173.10:22:28.31#ibcon#read 5, iclass 36, count 0 2006.173.10:22:28.31#ibcon#about to read 6, iclass 36, count 0 2006.173.10:22:28.31#ibcon#read 6, iclass 36, count 0 2006.173.10:22:28.32#ibcon#end of sib2, iclass 36, count 0 2006.173.10:22:28.32#ibcon#*after write, iclass 36, count 0 2006.173.10:22:28.32#ibcon#*before return 0, iclass 36, count 0 2006.173.10:22:28.32#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.10:22:28.32#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.10:22:28.32#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.10:22:28.32#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.10:22:28.32$vck44/va=1,7 2006.173.10:22:28.32#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.10:22:28.32#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.10:22:28.32#ibcon#ireg 11 cls_cnt 2 2006.173.10:22:28.32#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.10:22:28.32#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.10:22:28.32#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.10:22:28.32#ibcon#enter wrdev, iclass 38, count 2 2006.173.10:22:28.32#ibcon#first serial, iclass 38, count 2 2006.173.10:22:28.32#ibcon#enter sib2, iclass 38, count 2 2006.173.10:22:28.32#ibcon#flushed, iclass 38, count 2 2006.173.10:22:28.32#ibcon#about to write, iclass 38, count 2 2006.173.10:22:28.32#ibcon#wrote, iclass 38, count 2 2006.173.10:22:28.32#ibcon#about to read 3, iclass 38, count 2 2006.173.10:22:28.33#ibcon#read 3, iclass 38, count 2 2006.173.10:22:28.33#ibcon#about to read 4, iclass 38, count 2 2006.173.10:22:28.33#ibcon#read 4, iclass 38, count 2 2006.173.10:22:28.33#ibcon#about to read 5, iclass 38, count 2 2006.173.10:22:28.33#ibcon#read 5, iclass 38, count 2 2006.173.10:22:28.33#ibcon#about to read 6, iclass 38, count 2 2006.173.10:22:28.34#ibcon#read 6, iclass 38, count 2 2006.173.10:22:28.34#ibcon#end of sib2, iclass 38, count 2 2006.173.10:22:28.34#ibcon#*mode == 0, iclass 38, count 2 2006.173.10:22:28.34#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.10:22:28.34#ibcon#[25=AT01-07\r\n] 2006.173.10:22:28.34#ibcon#*before write, iclass 38, count 2 2006.173.10:22:28.34#ibcon#enter sib2, iclass 38, count 2 2006.173.10:22:28.34#ibcon#flushed, iclass 38, count 2 2006.173.10:22:28.34#ibcon#about to write, iclass 38, count 2 2006.173.10:22:28.34#ibcon#wrote, iclass 38, count 2 2006.173.10:22:28.34#ibcon#about to read 3, iclass 38, count 2 2006.173.10:22:28.36#ibcon#read 3, iclass 38, count 2 2006.173.10:22:28.36#ibcon#about to read 4, iclass 38, count 2 2006.173.10:22:28.36#ibcon#read 4, iclass 38, count 2 2006.173.10:22:28.36#ibcon#about to read 5, iclass 38, count 2 2006.173.10:22:28.36#ibcon#read 5, iclass 38, count 2 2006.173.10:22:28.36#ibcon#about to read 6, iclass 38, count 2 2006.173.10:22:28.36#ibcon#read 6, iclass 38, count 2 2006.173.10:22:28.36#ibcon#end of sib2, iclass 38, count 2 2006.173.10:22:28.36#ibcon#*after write, iclass 38, count 2 2006.173.10:22:28.37#ibcon#*before return 0, iclass 38, count 2 2006.173.10:22:28.37#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.10:22:28.37#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.10:22:28.37#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.10:22:28.37#ibcon#ireg 7 cls_cnt 0 2006.173.10:22:28.37#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.10:22:28.48#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.10:22:28.48#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.10:22:28.48#ibcon#enter wrdev, iclass 38, count 0 2006.173.10:22:28.48#ibcon#first serial, iclass 38, count 0 2006.173.10:22:28.48#ibcon#enter sib2, iclass 38, count 0 2006.173.10:22:28.48#ibcon#flushed, iclass 38, count 0 2006.173.10:22:28.48#ibcon#about to write, iclass 38, count 0 2006.173.10:22:28.49#ibcon#wrote, iclass 38, count 0 2006.173.10:22:28.49#ibcon#about to read 3, iclass 38, count 0 2006.173.10:22:28.50#ibcon#read 3, iclass 38, count 0 2006.173.10:22:28.50#ibcon#about to read 4, iclass 38, count 0 2006.173.10:22:28.50#ibcon#read 4, iclass 38, count 0 2006.173.10:22:28.50#ibcon#about to read 5, iclass 38, count 0 2006.173.10:22:28.51#ibcon#read 5, iclass 38, count 0 2006.173.10:22:28.51#ibcon#about to read 6, iclass 38, count 0 2006.173.10:22:28.51#ibcon#read 6, iclass 38, count 0 2006.173.10:22:28.51#ibcon#end of sib2, iclass 38, count 0 2006.173.10:22:28.51#ibcon#*mode == 0, iclass 38, count 0 2006.173.10:22:28.51#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.10:22:28.51#ibcon#[25=USB\r\n] 2006.173.10:22:28.51#ibcon#*before write, iclass 38, count 0 2006.173.10:22:28.51#ibcon#enter sib2, iclass 38, count 0 2006.173.10:22:28.51#ibcon#flushed, iclass 38, count 0 2006.173.10:22:28.51#ibcon#about to write, iclass 38, count 0 2006.173.10:22:28.51#ibcon#wrote, iclass 38, count 0 2006.173.10:22:28.51#ibcon#about to read 3, iclass 38, count 0 2006.173.10:22:28.53#ibcon#read 3, iclass 38, count 0 2006.173.10:22:28.53#ibcon#about to read 4, iclass 38, count 0 2006.173.10:22:28.53#ibcon#read 4, iclass 38, count 0 2006.173.10:22:28.53#ibcon#about to read 5, iclass 38, count 0 2006.173.10:22:28.53#ibcon#read 5, iclass 38, count 0 2006.173.10:22:28.53#ibcon#about to read 6, iclass 38, count 0 2006.173.10:22:28.54#ibcon#read 6, iclass 38, count 0 2006.173.10:22:28.54#ibcon#end of sib2, iclass 38, count 0 2006.173.10:22:28.54#ibcon#*after write, iclass 38, count 0 2006.173.10:22:28.54#ibcon#*before return 0, iclass 38, count 0 2006.173.10:22:28.54#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.10:22:28.54#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.10:22:28.54#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.10:22:28.54#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.10:22:28.54$vck44/valo=2,534.99 2006.173.10:22:28.54#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.10:22:28.54#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.10:22:28.54#ibcon#ireg 17 cls_cnt 0 2006.173.10:22:28.54#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.10:22:28.54#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.10:22:28.54#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.10:22:28.54#ibcon#enter wrdev, iclass 40, count 0 2006.173.10:22:28.54#ibcon#first serial, iclass 40, count 0 2006.173.10:22:28.54#ibcon#enter sib2, iclass 40, count 0 2006.173.10:22:28.54#ibcon#flushed, iclass 40, count 0 2006.173.10:22:28.54#ibcon#about to write, iclass 40, count 0 2006.173.10:22:28.54#ibcon#wrote, iclass 40, count 0 2006.173.10:22:28.54#ibcon#about to read 3, iclass 40, count 0 2006.173.10:22:28.55#ibcon#read 3, iclass 40, count 0 2006.173.10:22:28.55#ibcon#about to read 4, iclass 40, count 0 2006.173.10:22:28.55#ibcon#read 4, iclass 40, count 0 2006.173.10:22:28.55#ibcon#about to read 5, iclass 40, count 0 2006.173.10:22:28.55#ibcon#read 5, iclass 40, count 0 2006.173.10:22:28.55#ibcon#about to read 6, iclass 40, count 0 2006.173.10:22:28.56#ibcon#read 6, iclass 40, count 0 2006.173.10:22:28.56#ibcon#end of sib2, iclass 40, count 0 2006.173.10:22:28.56#ibcon#*mode == 0, iclass 40, count 0 2006.173.10:22:28.56#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.10:22:28.56#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.10:22:28.56#ibcon#*before write, iclass 40, count 0 2006.173.10:22:28.56#ibcon#enter sib2, iclass 40, count 0 2006.173.10:22:28.56#ibcon#flushed, iclass 40, count 0 2006.173.10:22:28.56#ibcon#about to write, iclass 40, count 0 2006.173.10:22:28.56#ibcon#wrote, iclass 40, count 0 2006.173.10:22:28.56#ibcon#about to read 3, iclass 40, count 0 2006.173.10:22:28.59#ibcon#read 3, iclass 40, count 0 2006.173.10:22:28.59#ibcon#about to read 4, iclass 40, count 0 2006.173.10:22:28.59#ibcon#read 4, iclass 40, count 0 2006.173.10:22:28.59#ibcon#about to read 5, iclass 40, count 0 2006.173.10:22:28.59#ibcon#read 5, iclass 40, count 0 2006.173.10:22:28.59#ibcon#about to read 6, iclass 40, count 0 2006.173.10:22:28.59#ibcon#read 6, iclass 40, count 0 2006.173.10:22:28.60#ibcon#end of sib2, iclass 40, count 0 2006.173.10:22:28.60#ibcon#*after write, iclass 40, count 0 2006.173.10:22:28.60#ibcon#*before return 0, iclass 40, count 0 2006.173.10:22:28.60#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.10:22:28.60#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.10:22:28.60#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.10:22:28.60#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.10:22:28.60$vck44/va=2,6 2006.173.10:22:28.60#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.10:22:28.60#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.10:22:28.60#ibcon#ireg 11 cls_cnt 2 2006.173.10:22:28.60#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.10:22:28.65#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.10:22:28.65#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.10:22:28.65#ibcon#enter wrdev, iclass 4, count 2 2006.173.10:22:28.65#ibcon#first serial, iclass 4, count 2 2006.173.10:22:28.65#ibcon#enter sib2, iclass 4, count 2 2006.173.10:22:28.65#ibcon#flushed, iclass 4, count 2 2006.173.10:22:28.65#ibcon#about to write, iclass 4, count 2 2006.173.10:22:28.66#ibcon#wrote, iclass 4, count 2 2006.173.10:22:28.66#ibcon#about to read 3, iclass 4, count 2 2006.173.10:22:28.67#ibcon#read 3, iclass 4, count 2 2006.173.10:22:28.67#ibcon#about to read 4, iclass 4, count 2 2006.173.10:22:28.67#ibcon#read 4, iclass 4, count 2 2006.173.10:22:28.67#ibcon#about to read 5, iclass 4, count 2 2006.173.10:22:28.67#ibcon#read 5, iclass 4, count 2 2006.173.10:22:28.67#ibcon#about to read 6, iclass 4, count 2 2006.173.10:22:28.67#ibcon#read 6, iclass 4, count 2 2006.173.10:22:28.67#ibcon#end of sib2, iclass 4, count 2 2006.173.10:22:28.67#ibcon#*mode == 0, iclass 4, count 2 2006.173.10:22:28.68#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.10:22:28.68#ibcon#[25=AT02-06\r\n] 2006.173.10:22:28.68#ibcon#*before write, iclass 4, count 2 2006.173.10:22:28.68#ibcon#enter sib2, iclass 4, count 2 2006.173.10:22:28.68#ibcon#flushed, iclass 4, count 2 2006.173.10:22:28.68#ibcon#about to write, iclass 4, count 2 2006.173.10:22:28.68#ibcon#wrote, iclass 4, count 2 2006.173.10:22:28.68#ibcon#about to read 3, iclass 4, count 2 2006.173.10:22:28.70#ibcon#read 3, iclass 4, count 2 2006.173.10:22:28.70#ibcon#about to read 4, iclass 4, count 2 2006.173.10:22:28.70#ibcon#read 4, iclass 4, count 2 2006.173.10:22:28.70#ibcon#about to read 5, iclass 4, count 2 2006.173.10:22:28.70#ibcon#read 5, iclass 4, count 2 2006.173.10:22:28.70#ibcon#about to read 6, iclass 4, count 2 2006.173.10:22:28.70#ibcon#read 6, iclass 4, count 2 2006.173.10:22:28.70#ibcon#end of sib2, iclass 4, count 2 2006.173.10:22:28.70#ibcon#*after write, iclass 4, count 2 2006.173.10:22:28.71#ibcon#*before return 0, iclass 4, count 2 2006.173.10:22:28.71#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.10:22:28.71#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.10:22:28.71#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.10:22:28.71#ibcon#ireg 7 cls_cnt 0 2006.173.10:22:28.71#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.10:22:28.82#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.10:22:28.82#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.10:22:28.82#ibcon#enter wrdev, iclass 4, count 0 2006.173.10:22:28.82#ibcon#first serial, iclass 4, count 0 2006.173.10:22:28.82#ibcon#enter sib2, iclass 4, count 0 2006.173.10:22:28.82#ibcon#flushed, iclass 4, count 0 2006.173.10:22:28.82#ibcon#about to write, iclass 4, count 0 2006.173.10:22:28.83#ibcon#wrote, iclass 4, count 0 2006.173.10:22:28.83#ibcon#about to read 3, iclass 4, count 0 2006.173.10:22:28.84#ibcon#read 3, iclass 4, count 0 2006.173.10:22:28.84#ibcon#about to read 4, iclass 4, count 0 2006.173.10:22:28.84#ibcon#read 4, iclass 4, count 0 2006.173.10:22:28.84#ibcon#about to read 5, iclass 4, count 0 2006.173.10:22:28.84#ibcon#read 5, iclass 4, count 0 2006.173.10:22:28.84#ibcon#about to read 6, iclass 4, count 0 2006.173.10:22:28.84#ibcon#read 6, iclass 4, count 0 2006.173.10:22:28.84#ibcon#end of sib2, iclass 4, count 0 2006.173.10:22:28.85#ibcon#*mode == 0, iclass 4, count 0 2006.173.10:22:28.85#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.10:22:28.85#ibcon#[25=USB\r\n] 2006.173.10:22:28.85#ibcon#*before write, iclass 4, count 0 2006.173.10:22:28.85#ibcon#enter sib2, iclass 4, count 0 2006.173.10:22:28.85#ibcon#flushed, iclass 4, count 0 2006.173.10:22:28.85#ibcon#about to write, iclass 4, count 0 2006.173.10:22:28.85#ibcon#wrote, iclass 4, count 0 2006.173.10:22:28.85#ibcon#about to read 3, iclass 4, count 0 2006.173.10:22:28.87#ibcon#read 3, iclass 4, count 0 2006.173.10:22:28.87#ibcon#about to read 4, iclass 4, count 0 2006.173.10:22:28.87#ibcon#read 4, iclass 4, count 0 2006.173.10:22:28.87#ibcon#about to read 5, iclass 4, count 0 2006.173.10:22:28.87#ibcon#read 5, iclass 4, count 0 2006.173.10:22:28.87#ibcon#about to read 6, iclass 4, count 0 2006.173.10:22:28.87#ibcon#read 6, iclass 4, count 0 2006.173.10:22:28.88#ibcon#end of sib2, iclass 4, count 0 2006.173.10:22:28.88#ibcon#*after write, iclass 4, count 0 2006.173.10:22:28.88#ibcon#*before return 0, iclass 4, count 0 2006.173.10:22:28.88#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.10:22:28.88#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.10:22:28.88#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.10:22:28.88#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.10:22:28.88$vck44/valo=3,564.99 2006.173.10:22:28.88#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.10:22:28.88#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.10:22:28.88#ibcon#ireg 17 cls_cnt 0 2006.173.10:22:28.88#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.10:22:28.88#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.10:22:28.88#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.10:22:28.88#ibcon#enter wrdev, iclass 6, count 0 2006.173.10:22:28.88#ibcon#first serial, iclass 6, count 0 2006.173.10:22:28.88#ibcon#enter sib2, iclass 6, count 0 2006.173.10:22:28.88#ibcon#flushed, iclass 6, count 0 2006.173.10:22:28.88#ibcon#about to write, iclass 6, count 0 2006.173.10:22:28.88#ibcon#wrote, iclass 6, count 0 2006.173.10:22:28.88#ibcon#about to read 3, iclass 6, count 0 2006.173.10:22:28.89#ibcon#read 3, iclass 6, count 0 2006.173.10:22:28.89#ibcon#about to read 4, iclass 6, count 0 2006.173.10:22:28.89#ibcon#read 4, iclass 6, count 0 2006.173.10:22:28.89#ibcon#about to read 5, iclass 6, count 0 2006.173.10:22:28.89#ibcon#read 5, iclass 6, count 0 2006.173.10:22:28.89#ibcon#about to read 6, iclass 6, count 0 2006.173.10:22:28.89#ibcon#read 6, iclass 6, count 0 2006.173.10:22:28.89#ibcon#end of sib2, iclass 6, count 0 2006.173.10:22:28.89#ibcon#*mode == 0, iclass 6, count 0 2006.173.10:22:28.90#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.10:22:28.90#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.10:22:28.90#ibcon#*before write, iclass 6, count 0 2006.173.10:22:28.90#ibcon#enter sib2, iclass 6, count 0 2006.173.10:22:28.90#ibcon#flushed, iclass 6, count 0 2006.173.10:22:28.90#ibcon#about to write, iclass 6, count 0 2006.173.10:22:28.90#ibcon#wrote, iclass 6, count 0 2006.173.10:22:28.90#ibcon#about to read 3, iclass 6, count 0 2006.173.10:22:28.93#ibcon#read 3, iclass 6, count 0 2006.173.10:22:28.93#ibcon#about to read 4, iclass 6, count 0 2006.173.10:22:28.93#ibcon#read 4, iclass 6, count 0 2006.173.10:22:28.93#ibcon#about to read 5, iclass 6, count 0 2006.173.10:22:28.93#ibcon#read 5, iclass 6, count 0 2006.173.10:22:28.93#ibcon#about to read 6, iclass 6, count 0 2006.173.10:22:28.93#ibcon#read 6, iclass 6, count 0 2006.173.10:22:28.93#ibcon#end of sib2, iclass 6, count 0 2006.173.10:22:28.94#ibcon#*after write, iclass 6, count 0 2006.173.10:22:28.94#ibcon#*before return 0, iclass 6, count 0 2006.173.10:22:28.94#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.10:22:28.94#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.10:22:28.94#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.10:22:28.94#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.10:22:28.94$vck44/va=3,5 2006.173.10:22:28.94#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.10:22:28.94#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.10:22:28.94#ibcon#ireg 11 cls_cnt 2 2006.173.10:22:28.94#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.10:22:28.99#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.10:22:28.99#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.10:22:28.99#ibcon#enter wrdev, iclass 10, count 2 2006.173.10:22:28.99#ibcon#first serial, iclass 10, count 2 2006.173.10:22:28.99#ibcon#enter sib2, iclass 10, count 2 2006.173.10:22:28.99#ibcon#flushed, iclass 10, count 2 2006.173.10:22:28.99#ibcon#about to write, iclass 10, count 2 2006.173.10:22:28.99#ibcon#wrote, iclass 10, count 2 2006.173.10:22:29.00#ibcon#about to read 3, iclass 10, count 2 2006.173.10:22:29.01#ibcon#read 3, iclass 10, count 2 2006.173.10:22:29.01#ibcon#about to read 4, iclass 10, count 2 2006.173.10:22:29.01#ibcon#read 4, iclass 10, count 2 2006.173.10:22:29.01#ibcon#about to read 5, iclass 10, count 2 2006.173.10:22:29.01#ibcon#read 5, iclass 10, count 2 2006.173.10:22:29.01#ibcon#about to read 6, iclass 10, count 2 2006.173.10:22:29.01#ibcon#read 6, iclass 10, count 2 2006.173.10:22:29.01#ibcon#end of sib2, iclass 10, count 2 2006.173.10:22:29.02#ibcon#*mode == 0, iclass 10, count 2 2006.173.10:22:29.02#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.10:22:29.02#ibcon#[25=AT03-05\r\n] 2006.173.10:22:29.02#ibcon#*before write, iclass 10, count 2 2006.173.10:22:29.02#ibcon#enter sib2, iclass 10, count 2 2006.173.10:22:29.02#ibcon#flushed, iclass 10, count 2 2006.173.10:22:29.02#ibcon#about to write, iclass 10, count 2 2006.173.10:22:29.02#ibcon#wrote, iclass 10, count 2 2006.173.10:22:29.02#ibcon#about to read 3, iclass 10, count 2 2006.173.10:22:29.04#ibcon#read 3, iclass 10, count 2 2006.173.10:22:29.04#ibcon#about to read 4, iclass 10, count 2 2006.173.10:22:29.04#ibcon#read 4, iclass 10, count 2 2006.173.10:22:29.04#ibcon#about to read 5, iclass 10, count 2 2006.173.10:22:29.04#ibcon#read 5, iclass 10, count 2 2006.173.10:22:29.04#ibcon#about to read 6, iclass 10, count 2 2006.173.10:22:29.04#ibcon#read 6, iclass 10, count 2 2006.173.10:22:29.04#ibcon#end of sib2, iclass 10, count 2 2006.173.10:22:29.05#ibcon#*after write, iclass 10, count 2 2006.173.10:22:29.05#ibcon#*before return 0, iclass 10, count 2 2006.173.10:22:29.05#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.10:22:29.05#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.10:22:29.05#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.10:22:29.05#ibcon#ireg 7 cls_cnt 0 2006.173.10:22:29.05#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.10:22:29.16#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.10:22:29.16#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.10:22:29.16#ibcon#enter wrdev, iclass 10, count 0 2006.173.10:22:29.16#ibcon#first serial, iclass 10, count 0 2006.173.10:22:29.16#ibcon#enter sib2, iclass 10, count 0 2006.173.10:22:29.16#ibcon#flushed, iclass 10, count 0 2006.173.10:22:29.16#ibcon#about to write, iclass 10, count 0 2006.173.10:22:29.17#ibcon#wrote, iclass 10, count 0 2006.173.10:22:29.17#ibcon#about to read 3, iclass 10, count 0 2006.173.10:22:29.18#ibcon#read 3, iclass 10, count 0 2006.173.10:22:29.18#ibcon#about to read 4, iclass 10, count 0 2006.173.10:22:29.18#ibcon#read 4, iclass 10, count 0 2006.173.10:22:29.18#ibcon#about to read 5, iclass 10, count 0 2006.173.10:22:29.18#ibcon#read 5, iclass 10, count 0 2006.173.10:22:29.18#ibcon#about to read 6, iclass 10, count 0 2006.173.10:22:29.18#ibcon#read 6, iclass 10, count 0 2006.173.10:22:29.18#ibcon#end of sib2, iclass 10, count 0 2006.173.10:22:29.18#ibcon#*mode == 0, iclass 10, count 0 2006.173.10:22:29.18#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.10:22:29.19#ibcon#[25=USB\r\n] 2006.173.10:22:29.19#ibcon#*before write, iclass 10, count 0 2006.173.10:22:29.19#ibcon#enter sib2, iclass 10, count 0 2006.173.10:22:29.19#ibcon#flushed, iclass 10, count 0 2006.173.10:22:29.19#ibcon#about to write, iclass 10, count 0 2006.173.10:22:29.19#ibcon#wrote, iclass 10, count 0 2006.173.10:22:29.19#ibcon#about to read 3, iclass 10, count 0 2006.173.10:22:29.21#ibcon#read 3, iclass 10, count 0 2006.173.10:22:29.21#ibcon#about to read 4, iclass 10, count 0 2006.173.10:22:29.21#ibcon#read 4, iclass 10, count 0 2006.173.10:22:29.22#ibcon#about to read 5, iclass 10, count 0 2006.173.10:22:29.22#ibcon#read 5, iclass 10, count 0 2006.173.10:22:29.22#ibcon#about to read 6, iclass 10, count 0 2006.173.10:22:29.22#ibcon#read 6, iclass 10, count 0 2006.173.10:22:29.22#ibcon#end of sib2, iclass 10, count 0 2006.173.10:22:29.22#ibcon#*after write, iclass 10, count 0 2006.173.10:22:29.22#ibcon#*before return 0, iclass 10, count 0 2006.173.10:22:29.22#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.10:22:29.22#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.10:22:29.22#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.10:22:29.22#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.10:22:29.22$vck44/valo=4,624.99 2006.173.10:22:29.22#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.10:22:29.22#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.10:22:29.22#ibcon#ireg 17 cls_cnt 0 2006.173.10:22:29.22#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.10:22:29.22#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.10:22:29.22#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.10:22:29.22#ibcon#enter wrdev, iclass 12, count 0 2006.173.10:22:29.22#ibcon#first serial, iclass 12, count 0 2006.173.10:22:29.22#ibcon#enter sib2, iclass 12, count 0 2006.173.10:22:29.22#ibcon#flushed, iclass 12, count 0 2006.173.10:22:29.22#ibcon#about to write, iclass 12, count 0 2006.173.10:22:29.22#ibcon#wrote, iclass 12, count 0 2006.173.10:22:29.22#ibcon#about to read 3, iclass 12, count 0 2006.173.10:22:29.23#ibcon#read 3, iclass 12, count 0 2006.173.10:22:29.23#ibcon#about to read 4, iclass 12, count 0 2006.173.10:22:29.23#ibcon#read 4, iclass 12, count 0 2006.173.10:22:29.23#ibcon#about to read 5, iclass 12, count 0 2006.173.10:22:29.24#ibcon#read 5, iclass 12, count 0 2006.173.10:22:29.24#ibcon#about to read 6, iclass 12, count 0 2006.173.10:22:29.24#ibcon#read 6, iclass 12, count 0 2006.173.10:22:29.24#ibcon#end of sib2, iclass 12, count 0 2006.173.10:22:29.24#ibcon#*mode == 0, iclass 12, count 0 2006.173.10:22:29.24#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.10:22:29.24#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.10:22:29.24#ibcon#*before write, iclass 12, count 0 2006.173.10:22:29.24#ibcon#enter sib2, iclass 12, count 0 2006.173.10:22:29.24#ibcon#flushed, iclass 12, count 0 2006.173.10:22:29.24#ibcon#about to write, iclass 12, count 0 2006.173.10:22:29.24#ibcon#wrote, iclass 12, count 0 2006.173.10:22:29.24#ibcon#about to read 3, iclass 12, count 0 2006.173.10:22:29.27#ibcon#read 3, iclass 12, count 0 2006.173.10:22:29.27#ibcon#about to read 4, iclass 12, count 0 2006.173.10:22:29.27#ibcon#read 4, iclass 12, count 0 2006.173.10:22:29.27#ibcon#about to read 5, iclass 12, count 0 2006.173.10:22:29.27#ibcon#read 5, iclass 12, count 0 2006.173.10:22:29.27#ibcon#about to read 6, iclass 12, count 0 2006.173.10:22:29.28#ibcon#read 6, iclass 12, count 0 2006.173.10:22:29.28#ibcon#end of sib2, iclass 12, count 0 2006.173.10:22:29.28#ibcon#*after write, iclass 12, count 0 2006.173.10:22:29.28#ibcon#*before return 0, iclass 12, count 0 2006.173.10:22:29.28#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.10:22:29.28#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.10:22:29.28#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.10:22:29.28#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.10:22:29.28$vck44/va=4,6 2006.173.10:22:29.28#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.10:22:29.28#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.10:22:29.28#ibcon#ireg 11 cls_cnt 2 2006.173.10:22:29.28#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.10:22:29.33#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.10:22:29.33#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.10:22:29.33#ibcon#enter wrdev, iclass 14, count 2 2006.173.10:22:29.33#ibcon#first serial, iclass 14, count 2 2006.173.10:22:29.33#ibcon#enter sib2, iclass 14, count 2 2006.173.10:22:29.33#ibcon#flushed, iclass 14, count 2 2006.173.10:22:29.33#ibcon#about to write, iclass 14, count 2 2006.173.10:22:29.34#ibcon#wrote, iclass 14, count 2 2006.173.10:22:29.34#ibcon#about to read 3, iclass 14, count 2 2006.173.10:22:29.35#ibcon#read 3, iclass 14, count 2 2006.173.10:22:29.35#ibcon#about to read 4, iclass 14, count 2 2006.173.10:22:29.35#ibcon#read 4, iclass 14, count 2 2006.173.10:22:29.36#ibcon#about to read 5, iclass 14, count 2 2006.173.10:22:29.36#ibcon#read 5, iclass 14, count 2 2006.173.10:22:29.36#ibcon#about to read 6, iclass 14, count 2 2006.173.10:22:29.36#ibcon#read 6, iclass 14, count 2 2006.173.10:22:29.36#ibcon#end of sib2, iclass 14, count 2 2006.173.10:22:29.36#ibcon#*mode == 0, iclass 14, count 2 2006.173.10:22:29.36#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.10:22:29.36#ibcon#[25=AT04-06\r\n] 2006.173.10:22:29.36#ibcon#*before write, iclass 14, count 2 2006.173.10:22:29.36#ibcon#enter sib2, iclass 14, count 2 2006.173.10:22:29.36#ibcon#flushed, iclass 14, count 2 2006.173.10:22:29.36#ibcon#about to write, iclass 14, count 2 2006.173.10:22:29.36#ibcon#wrote, iclass 14, count 2 2006.173.10:22:29.36#ibcon#about to read 3, iclass 14, count 2 2006.173.10:22:29.38#ibcon#read 3, iclass 14, count 2 2006.173.10:22:29.38#ibcon#about to read 4, iclass 14, count 2 2006.173.10:22:29.38#ibcon#read 4, iclass 14, count 2 2006.173.10:22:29.38#ibcon#about to read 5, iclass 14, count 2 2006.173.10:22:29.38#ibcon#read 5, iclass 14, count 2 2006.173.10:22:29.38#ibcon#about to read 6, iclass 14, count 2 2006.173.10:22:29.38#ibcon#read 6, iclass 14, count 2 2006.173.10:22:29.39#ibcon#end of sib2, iclass 14, count 2 2006.173.10:22:29.39#ibcon#*after write, iclass 14, count 2 2006.173.10:22:29.39#ibcon#*before return 0, iclass 14, count 2 2006.173.10:22:29.39#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.10:22:29.39#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.10:22:29.39#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.10:22:29.39#ibcon#ireg 7 cls_cnt 0 2006.173.10:22:29.39#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.10:22:29.50#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.10:22:29.50#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.10:22:29.50#ibcon#enter wrdev, iclass 14, count 0 2006.173.10:22:29.50#ibcon#first serial, iclass 14, count 0 2006.173.10:22:29.50#ibcon#enter sib2, iclass 14, count 0 2006.173.10:22:29.50#ibcon#flushed, iclass 14, count 0 2006.173.10:22:29.50#ibcon#about to write, iclass 14, count 0 2006.173.10:22:29.51#ibcon#wrote, iclass 14, count 0 2006.173.10:22:29.51#ibcon#about to read 3, iclass 14, count 0 2006.173.10:22:29.52#ibcon#read 3, iclass 14, count 0 2006.173.10:22:29.52#ibcon#about to read 4, iclass 14, count 0 2006.173.10:22:29.52#ibcon#read 4, iclass 14, count 0 2006.173.10:22:29.52#ibcon#about to read 5, iclass 14, count 0 2006.173.10:22:29.52#ibcon#read 5, iclass 14, count 0 2006.173.10:22:29.52#ibcon#about to read 6, iclass 14, count 0 2006.173.10:22:29.53#ibcon#read 6, iclass 14, count 0 2006.173.10:22:29.53#ibcon#end of sib2, iclass 14, count 0 2006.173.10:22:29.53#ibcon#*mode == 0, iclass 14, count 0 2006.173.10:22:29.53#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.10:22:29.53#ibcon#[25=USB\r\n] 2006.173.10:22:29.53#ibcon#*before write, iclass 14, count 0 2006.173.10:22:29.53#ibcon#enter sib2, iclass 14, count 0 2006.173.10:22:29.53#ibcon#flushed, iclass 14, count 0 2006.173.10:22:29.53#ibcon#about to write, iclass 14, count 0 2006.173.10:22:29.53#ibcon#wrote, iclass 14, count 0 2006.173.10:22:29.53#ibcon#about to read 3, iclass 14, count 0 2006.173.10:22:29.55#ibcon#read 3, iclass 14, count 0 2006.173.10:22:29.55#ibcon#about to read 4, iclass 14, count 0 2006.173.10:22:29.55#ibcon#read 4, iclass 14, count 0 2006.173.10:22:29.55#ibcon#about to read 5, iclass 14, count 0 2006.173.10:22:29.55#ibcon#read 5, iclass 14, count 0 2006.173.10:22:29.55#ibcon#about to read 6, iclass 14, count 0 2006.173.10:22:29.56#ibcon#read 6, iclass 14, count 0 2006.173.10:22:29.56#ibcon#end of sib2, iclass 14, count 0 2006.173.10:22:29.56#ibcon#*after write, iclass 14, count 0 2006.173.10:22:29.56#ibcon#*before return 0, iclass 14, count 0 2006.173.10:22:29.56#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.10:22:29.56#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.10:22:29.56#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.10:22:29.56#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.10:22:29.56$vck44/valo=5,734.99 2006.173.10:22:29.56#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.10:22:29.56#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.10:22:29.56#ibcon#ireg 17 cls_cnt 0 2006.173.10:22:29.56#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.10:22:29.56#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.10:22:29.56#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.10:22:29.56#ibcon#enter wrdev, iclass 16, count 0 2006.173.10:22:29.56#ibcon#first serial, iclass 16, count 0 2006.173.10:22:29.56#ibcon#enter sib2, iclass 16, count 0 2006.173.10:22:29.56#ibcon#flushed, iclass 16, count 0 2006.173.10:22:29.56#ibcon#about to write, iclass 16, count 0 2006.173.10:22:29.56#ibcon#wrote, iclass 16, count 0 2006.173.10:22:29.56#ibcon#about to read 3, iclass 16, count 0 2006.173.10:22:29.57#ibcon#read 3, iclass 16, count 0 2006.173.10:22:29.57#ibcon#about to read 4, iclass 16, count 0 2006.173.10:22:29.57#ibcon#read 4, iclass 16, count 0 2006.173.10:22:29.58#ibcon#about to read 5, iclass 16, count 0 2006.173.10:22:29.58#ibcon#read 5, iclass 16, count 0 2006.173.10:22:29.58#ibcon#about to read 6, iclass 16, count 0 2006.173.10:22:29.58#ibcon#read 6, iclass 16, count 0 2006.173.10:22:29.58#ibcon#end of sib2, iclass 16, count 0 2006.173.10:22:29.58#ibcon#*mode == 0, iclass 16, count 0 2006.173.10:22:29.58#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.10:22:29.58#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.10:22:29.58#ibcon#*before write, iclass 16, count 0 2006.173.10:22:29.58#ibcon#enter sib2, iclass 16, count 0 2006.173.10:22:29.58#ibcon#flushed, iclass 16, count 0 2006.173.10:22:29.58#ibcon#about to write, iclass 16, count 0 2006.173.10:22:29.58#ibcon#wrote, iclass 16, count 0 2006.173.10:22:29.58#ibcon#about to read 3, iclass 16, count 0 2006.173.10:22:29.61#ibcon#read 3, iclass 16, count 0 2006.173.10:22:29.61#ibcon#about to read 4, iclass 16, count 0 2006.173.10:22:29.61#ibcon#read 4, iclass 16, count 0 2006.173.10:22:29.61#ibcon#about to read 5, iclass 16, count 0 2006.173.10:22:29.61#ibcon#read 5, iclass 16, count 0 2006.173.10:22:29.61#ibcon#about to read 6, iclass 16, count 0 2006.173.10:22:29.61#ibcon#read 6, iclass 16, count 0 2006.173.10:22:29.62#ibcon#end of sib2, iclass 16, count 0 2006.173.10:22:29.62#ibcon#*after write, iclass 16, count 0 2006.173.10:22:29.62#ibcon#*before return 0, iclass 16, count 0 2006.173.10:22:29.62#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.10:22:29.62#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.10:22:29.62#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.10:22:29.62#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.10:22:29.62$vck44/va=5,4 2006.173.10:22:29.62#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.10:22:29.62#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.10:22:29.62#ibcon#ireg 11 cls_cnt 2 2006.173.10:22:29.62#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.10:22:29.67#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.10:22:29.67#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.10:22:29.67#ibcon#enter wrdev, iclass 18, count 2 2006.173.10:22:29.67#ibcon#first serial, iclass 18, count 2 2006.173.10:22:29.67#ibcon#enter sib2, iclass 18, count 2 2006.173.10:22:29.67#ibcon#flushed, iclass 18, count 2 2006.173.10:22:29.67#ibcon#about to write, iclass 18, count 2 2006.173.10:22:29.68#ibcon#wrote, iclass 18, count 2 2006.173.10:22:29.68#ibcon#about to read 3, iclass 18, count 2 2006.173.10:22:29.69#ibcon#read 3, iclass 18, count 2 2006.173.10:22:29.69#ibcon#about to read 4, iclass 18, count 2 2006.173.10:22:29.69#ibcon#read 4, iclass 18, count 2 2006.173.10:22:29.69#ibcon#about to read 5, iclass 18, count 2 2006.173.10:22:29.69#ibcon#read 5, iclass 18, count 2 2006.173.10:22:29.69#ibcon#about to read 6, iclass 18, count 2 2006.173.10:22:29.69#ibcon#read 6, iclass 18, count 2 2006.173.10:22:29.69#ibcon#end of sib2, iclass 18, count 2 2006.173.10:22:29.70#ibcon#*mode == 0, iclass 18, count 2 2006.173.10:22:29.70#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.10:22:29.70#ibcon#[25=AT05-04\r\n] 2006.173.10:22:29.70#ibcon#*before write, iclass 18, count 2 2006.173.10:22:29.70#ibcon#enter sib2, iclass 18, count 2 2006.173.10:22:29.70#ibcon#flushed, iclass 18, count 2 2006.173.10:22:29.70#ibcon#about to write, iclass 18, count 2 2006.173.10:22:29.70#ibcon#wrote, iclass 18, count 2 2006.173.10:22:29.70#ibcon#about to read 3, iclass 18, count 2 2006.173.10:22:29.72#ibcon#read 3, iclass 18, count 2 2006.173.10:22:29.72#ibcon#about to read 4, iclass 18, count 2 2006.173.10:22:29.72#ibcon#read 4, iclass 18, count 2 2006.173.10:22:29.72#ibcon#about to read 5, iclass 18, count 2 2006.173.10:22:29.72#ibcon#read 5, iclass 18, count 2 2006.173.10:22:29.72#ibcon#about to read 6, iclass 18, count 2 2006.173.10:22:29.72#ibcon#read 6, iclass 18, count 2 2006.173.10:22:29.72#ibcon#end of sib2, iclass 18, count 2 2006.173.10:22:29.72#ibcon#*after write, iclass 18, count 2 2006.173.10:22:29.73#ibcon#*before return 0, iclass 18, count 2 2006.173.10:22:29.73#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.10:22:29.73#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.10:22:29.73#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.10:22:29.73#ibcon#ireg 7 cls_cnt 0 2006.173.10:22:29.73#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.10:22:29.84#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.10:22:29.84#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.10:22:29.84#ibcon#enter wrdev, iclass 18, count 0 2006.173.10:22:29.84#ibcon#first serial, iclass 18, count 0 2006.173.10:22:29.84#ibcon#enter sib2, iclass 18, count 0 2006.173.10:22:29.84#ibcon#flushed, iclass 18, count 0 2006.173.10:22:29.84#ibcon#about to write, iclass 18, count 0 2006.173.10:22:29.85#ibcon#wrote, iclass 18, count 0 2006.173.10:22:29.85#ibcon#about to read 3, iclass 18, count 0 2006.173.10:22:29.86#ibcon#read 3, iclass 18, count 0 2006.173.10:22:29.86#ibcon#about to read 4, iclass 18, count 0 2006.173.10:22:29.86#ibcon#read 4, iclass 18, count 0 2006.173.10:22:29.86#ibcon#about to read 5, iclass 18, count 0 2006.173.10:22:29.86#ibcon#read 5, iclass 18, count 0 2006.173.10:22:29.86#ibcon#about to read 6, iclass 18, count 0 2006.173.10:22:29.86#ibcon#read 6, iclass 18, count 0 2006.173.10:22:29.87#ibcon#end of sib2, iclass 18, count 0 2006.173.10:22:29.87#ibcon#*mode == 0, iclass 18, count 0 2006.173.10:22:29.87#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.10:22:29.87#ibcon#[25=USB\r\n] 2006.173.10:22:29.87#ibcon#*before write, iclass 18, count 0 2006.173.10:22:29.87#ibcon#enter sib2, iclass 18, count 0 2006.173.10:22:29.87#ibcon#flushed, iclass 18, count 0 2006.173.10:22:29.87#ibcon#about to write, iclass 18, count 0 2006.173.10:22:29.87#ibcon#wrote, iclass 18, count 0 2006.173.10:22:29.87#ibcon#about to read 3, iclass 18, count 0 2006.173.10:22:29.89#ibcon#read 3, iclass 18, count 0 2006.173.10:22:29.89#ibcon#about to read 4, iclass 18, count 0 2006.173.10:22:29.89#ibcon#read 4, iclass 18, count 0 2006.173.10:22:29.89#ibcon#about to read 5, iclass 18, count 0 2006.173.10:22:29.89#ibcon#read 5, iclass 18, count 0 2006.173.10:22:29.89#ibcon#about to read 6, iclass 18, count 0 2006.173.10:22:29.89#ibcon#read 6, iclass 18, count 0 2006.173.10:22:29.90#ibcon#end of sib2, iclass 18, count 0 2006.173.10:22:29.90#ibcon#*after write, iclass 18, count 0 2006.173.10:22:29.90#ibcon#*before return 0, iclass 18, count 0 2006.173.10:22:29.90#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.10:22:29.90#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.10:22:29.90#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.10:22:29.90#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.10:22:29.90$vck44/valo=6,814.99 2006.173.10:22:29.90#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.10:22:29.90#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.10:22:29.90#ibcon#ireg 17 cls_cnt 0 2006.173.10:22:29.90#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.10:22:29.90#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.10:22:29.90#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.10:22:29.90#ibcon#enter wrdev, iclass 20, count 0 2006.173.10:22:29.90#ibcon#first serial, iclass 20, count 0 2006.173.10:22:29.90#ibcon#enter sib2, iclass 20, count 0 2006.173.10:22:29.90#ibcon#flushed, iclass 20, count 0 2006.173.10:22:29.90#ibcon#about to write, iclass 20, count 0 2006.173.10:22:29.90#ibcon#wrote, iclass 20, count 0 2006.173.10:22:29.90#ibcon#about to read 3, iclass 20, count 0 2006.173.10:22:29.91#ibcon#read 3, iclass 20, count 0 2006.173.10:22:29.91#ibcon#about to read 4, iclass 20, count 0 2006.173.10:22:29.91#ibcon#read 4, iclass 20, count 0 2006.173.10:22:29.91#ibcon#about to read 5, iclass 20, count 0 2006.173.10:22:29.91#ibcon#read 5, iclass 20, count 0 2006.173.10:22:29.91#ibcon#about to read 6, iclass 20, count 0 2006.173.10:22:29.91#ibcon#read 6, iclass 20, count 0 2006.173.10:22:29.92#ibcon#end of sib2, iclass 20, count 0 2006.173.10:22:29.92#ibcon#*mode == 0, iclass 20, count 0 2006.173.10:22:29.92#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.10:22:29.92#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.10:22:29.92#ibcon#*before write, iclass 20, count 0 2006.173.10:22:29.92#ibcon#enter sib2, iclass 20, count 0 2006.173.10:22:29.92#ibcon#flushed, iclass 20, count 0 2006.173.10:22:29.92#ibcon#about to write, iclass 20, count 0 2006.173.10:22:29.92#ibcon#wrote, iclass 20, count 0 2006.173.10:22:29.92#ibcon#about to read 3, iclass 20, count 0 2006.173.10:22:29.95#ibcon#read 3, iclass 20, count 0 2006.173.10:22:29.95#ibcon#about to read 4, iclass 20, count 0 2006.173.10:22:29.95#ibcon#read 4, iclass 20, count 0 2006.173.10:22:29.95#ibcon#about to read 5, iclass 20, count 0 2006.173.10:22:29.95#ibcon#read 5, iclass 20, count 0 2006.173.10:22:29.95#ibcon#about to read 6, iclass 20, count 0 2006.173.10:22:29.95#ibcon#read 6, iclass 20, count 0 2006.173.10:22:29.96#ibcon#end of sib2, iclass 20, count 0 2006.173.10:22:29.96#ibcon#*after write, iclass 20, count 0 2006.173.10:22:29.96#ibcon#*before return 0, iclass 20, count 0 2006.173.10:22:29.96#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.10:22:29.96#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.10:22:29.96#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.10:22:29.96#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.10:22:29.96$vck44/va=6,3 2006.173.10:22:29.96#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.10:22:29.96#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.10:22:29.96#ibcon#ireg 11 cls_cnt 2 2006.173.10:22:29.96#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.10:22:30.01#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.10:22:30.01#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.10:22:30.01#ibcon#enter wrdev, iclass 22, count 2 2006.173.10:22:30.01#ibcon#first serial, iclass 22, count 2 2006.173.10:22:30.01#ibcon#enter sib2, iclass 22, count 2 2006.173.10:22:30.01#ibcon#flushed, iclass 22, count 2 2006.173.10:22:30.02#ibcon#about to write, iclass 22, count 2 2006.173.10:22:30.02#ibcon#wrote, iclass 22, count 2 2006.173.10:22:30.02#ibcon#about to read 3, iclass 22, count 2 2006.173.10:22:30.03#ibcon#read 3, iclass 22, count 2 2006.173.10:22:30.03#ibcon#about to read 4, iclass 22, count 2 2006.173.10:22:30.03#ibcon#read 4, iclass 22, count 2 2006.173.10:22:30.03#ibcon#about to read 5, iclass 22, count 2 2006.173.10:22:30.03#ibcon#read 5, iclass 22, count 2 2006.173.10:22:30.03#ibcon#about to read 6, iclass 22, count 2 2006.173.10:22:30.03#ibcon#read 6, iclass 22, count 2 2006.173.10:22:30.03#ibcon#end of sib2, iclass 22, count 2 2006.173.10:22:30.03#ibcon#*mode == 0, iclass 22, count 2 2006.173.10:22:30.04#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.10:22:30.04#ibcon#[25=AT06-03\r\n] 2006.173.10:22:30.04#ibcon#*before write, iclass 22, count 2 2006.173.10:22:30.04#ibcon#enter sib2, iclass 22, count 2 2006.173.10:22:30.04#ibcon#flushed, iclass 22, count 2 2006.173.10:22:30.04#ibcon#about to write, iclass 22, count 2 2006.173.10:22:30.04#ibcon#wrote, iclass 22, count 2 2006.173.10:22:30.04#ibcon#about to read 3, iclass 22, count 2 2006.173.10:22:30.06#ibcon#read 3, iclass 22, count 2 2006.173.10:22:30.06#ibcon#about to read 4, iclass 22, count 2 2006.173.10:22:30.06#ibcon#read 4, iclass 22, count 2 2006.173.10:22:30.06#ibcon#about to read 5, iclass 22, count 2 2006.173.10:22:30.06#ibcon#read 5, iclass 22, count 2 2006.173.10:22:30.06#ibcon#about to read 6, iclass 22, count 2 2006.173.10:22:30.06#ibcon#read 6, iclass 22, count 2 2006.173.10:22:30.06#ibcon#end of sib2, iclass 22, count 2 2006.173.10:22:30.06#ibcon#*after write, iclass 22, count 2 2006.173.10:22:30.06#ibcon#*before return 0, iclass 22, count 2 2006.173.10:22:30.06#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.10:22:30.07#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.10:22:30.07#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.10:22:30.07#ibcon#ireg 7 cls_cnt 0 2006.173.10:22:30.07#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.10:22:30.18#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.10:22:30.18#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.10:22:30.18#ibcon#enter wrdev, iclass 22, count 0 2006.173.10:22:30.18#ibcon#first serial, iclass 22, count 0 2006.173.10:22:30.18#ibcon#enter sib2, iclass 22, count 0 2006.173.10:22:30.18#ibcon#flushed, iclass 22, count 0 2006.173.10:22:30.18#ibcon#about to write, iclass 22, count 0 2006.173.10:22:30.19#ibcon#wrote, iclass 22, count 0 2006.173.10:22:30.19#ibcon#about to read 3, iclass 22, count 0 2006.173.10:22:30.20#ibcon#read 3, iclass 22, count 0 2006.173.10:22:30.20#ibcon#about to read 4, iclass 22, count 0 2006.173.10:22:30.20#ibcon#read 4, iclass 22, count 0 2006.173.10:22:30.20#ibcon#about to read 5, iclass 22, count 0 2006.173.10:22:30.20#ibcon#read 5, iclass 22, count 0 2006.173.10:22:30.20#ibcon#about to read 6, iclass 22, count 0 2006.173.10:22:30.20#ibcon#read 6, iclass 22, count 0 2006.173.10:22:30.20#ibcon#end of sib2, iclass 22, count 0 2006.173.10:22:30.20#ibcon#*mode == 0, iclass 22, count 0 2006.173.10:22:30.20#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.10:22:30.20#ibcon#[25=USB\r\n] 2006.173.10:22:30.21#ibcon#*before write, iclass 22, count 0 2006.173.10:22:30.21#ibcon#enter sib2, iclass 22, count 0 2006.173.10:22:30.21#ibcon#flushed, iclass 22, count 0 2006.173.10:22:30.21#ibcon#about to write, iclass 22, count 0 2006.173.10:22:30.21#ibcon#wrote, iclass 22, count 0 2006.173.10:22:30.21#ibcon#about to read 3, iclass 22, count 0 2006.173.10:22:30.23#ibcon#read 3, iclass 22, count 0 2006.173.10:22:30.23#ibcon#about to read 4, iclass 22, count 0 2006.173.10:22:30.23#ibcon#read 4, iclass 22, count 0 2006.173.10:22:30.23#ibcon#about to read 5, iclass 22, count 0 2006.173.10:22:30.23#ibcon#read 5, iclass 22, count 0 2006.173.10:22:30.23#ibcon#about to read 6, iclass 22, count 0 2006.173.10:22:30.23#ibcon#read 6, iclass 22, count 0 2006.173.10:22:30.24#ibcon#end of sib2, iclass 22, count 0 2006.173.10:22:30.24#ibcon#*after write, iclass 22, count 0 2006.173.10:22:30.24#ibcon#*before return 0, iclass 22, count 0 2006.173.10:22:30.24#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.10:22:30.24#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.10:22:30.24#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.10:22:30.24#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.10:22:30.24$vck44/valo=7,864.99 2006.173.10:22:30.24#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.10:22:30.24#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.10:22:30.24#ibcon#ireg 17 cls_cnt 0 2006.173.10:22:30.24#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.10:22:30.24#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.10:22:30.24#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.10:22:30.24#ibcon#enter wrdev, iclass 24, count 0 2006.173.10:22:30.24#ibcon#first serial, iclass 24, count 0 2006.173.10:22:30.24#ibcon#enter sib2, iclass 24, count 0 2006.173.10:22:30.24#ibcon#flushed, iclass 24, count 0 2006.173.10:22:30.24#ibcon#about to write, iclass 24, count 0 2006.173.10:22:30.24#ibcon#wrote, iclass 24, count 0 2006.173.10:22:30.24#ibcon#about to read 3, iclass 24, count 0 2006.173.10:22:30.25#ibcon#read 3, iclass 24, count 0 2006.173.10:22:30.25#ibcon#about to read 4, iclass 24, count 0 2006.173.10:22:30.25#ibcon#read 4, iclass 24, count 0 2006.173.10:22:30.25#ibcon#about to read 5, iclass 24, count 0 2006.173.10:22:30.25#ibcon#read 5, iclass 24, count 0 2006.173.10:22:30.25#ibcon#about to read 6, iclass 24, count 0 2006.173.10:22:30.25#ibcon#read 6, iclass 24, count 0 2006.173.10:22:30.25#ibcon#end of sib2, iclass 24, count 0 2006.173.10:22:30.25#ibcon#*mode == 0, iclass 24, count 0 2006.173.10:22:30.25#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.10:22:30.25#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.10:22:30.26#ibcon#*before write, iclass 24, count 0 2006.173.10:22:30.26#ibcon#enter sib2, iclass 24, count 0 2006.173.10:22:30.26#ibcon#flushed, iclass 24, count 0 2006.173.10:22:30.26#ibcon#about to write, iclass 24, count 0 2006.173.10:22:30.26#ibcon#wrote, iclass 24, count 0 2006.173.10:22:30.26#ibcon#about to read 3, iclass 24, count 0 2006.173.10:22:30.29#ibcon#read 3, iclass 24, count 0 2006.173.10:22:30.29#ibcon#about to read 4, iclass 24, count 0 2006.173.10:22:30.29#ibcon#read 4, iclass 24, count 0 2006.173.10:22:30.29#ibcon#about to read 5, iclass 24, count 0 2006.173.10:22:30.29#ibcon#read 5, iclass 24, count 0 2006.173.10:22:30.29#ibcon#about to read 6, iclass 24, count 0 2006.173.10:22:30.29#ibcon#read 6, iclass 24, count 0 2006.173.10:22:30.29#ibcon#end of sib2, iclass 24, count 0 2006.173.10:22:30.29#ibcon#*after write, iclass 24, count 0 2006.173.10:22:30.30#ibcon#*before return 0, iclass 24, count 0 2006.173.10:22:30.30#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.10:22:30.30#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.10:22:30.30#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.10:22:30.30#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.10:22:30.30$vck44/va=7,4 2006.173.10:22:30.30#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.10:22:30.30#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.10:22:30.30#ibcon#ireg 11 cls_cnt 2 2006.173.10:22:30.30#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.10:22:30.35#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.10:22:30.35#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.10:22:30.35#ibcon#enter wrdev, iclass 26, count 2 2006.173.10:22:30.35#ibcon#first serial, iclass 26, count 2 2006.173.10:22:30.35#ibcon#enter sib2, iclass 26, count 2 2006.173.10:22:30.35#ibcon#flushed, iclass 26, count 2 2006.173.10:22:30.35#ibcon#about to write, iclass 26, count 2 2006.173.10:22:30.35#ibcon#wrote, iclass 26, count 2 2006.173.10:22:30.36#ibcon#about to read 3, iclass 26, count 2 2006.173.10:22:30.37#ibcon#read 3, iclass 26, count 2 2006.173.10:22:30.37#ibcon#about to read 4, iclass 26, count 2 2006.173.10:22:30.37#ibcon#read 4, iclass 26, count 2 2006.173.10:22:30.37#ibcon#about to read 5, iclass 26, count 2 2006.173.10:22:30.37#ibcon#read 5, iclass 26, count 2 2006.173.10:22:30.37#ibcon#about to read 6, iclass 26, count 2 2006.173.10:22:30.37#ibcon#read 6, iclass 26, count 2 2006.173.10:22:30.38#ibcon#end of sib2, iclass 26, count 2 2006.173.10:22:30.38#ibcon#*mode == 0, iclass 26, count 2 2006.173.10:22:30.38#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.10:22:30.38#ibcon#[25=AT07-04\r\n] 2006.173.10:22:30.38#ibcon#*before write, iclass 26, count 2 2006.173.10:22:30.38#ibcon#enter sib2, iclass 26, count 2 2006.173.10:22:30.38#ibcon#flushed, iclass 26, count 2 2006.173.10:22:30.38#ibcon#about to write, iclass 26, count 2 2006.173.10:22:30.38#ibcon#wrote, iclass 26, count 2 2006.173.10:22:30.38#ibcon#about to read 3, iclass 26, count 2 2006.173.10:22:30.40#ibcon#read 3, iclass 26, count 2 2006.173.10:22:30.40#ibcon#about to read 4, iclass 26, count 2 2006.173.10:22:30.40#ibcon#read 4, iclass 26, count 2 2006.173.10:22:30.40#ibcon#about to read 5, iclass 26, count 2 2006.173.10:22:30.40#ibcon#read 5, iclass 26, count 2 2006.173.10:22:30.40#ibcon#about to read 6, iclass 26, count 2 2006.173.10:22:30.40#ibcon#read 6, iclass 26, count 2 2006.173.10:22:30.40#ibcon#end of sib2, iclass 26, count 2 2006.173.10:22:30.40#ibcon#*after write, iclass 26, count 2 2006.173.10:22:30.40#ibcon#*before return 0, iclass 26, count 2 2006.173.10:22:30.40#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.10:22:30.41#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.10:22:30.41#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.10:22:30.41#ibcon#ireg 7 cls_cnt 0 2006.173.10:22:30.41#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.10:22:30.52#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.10:22:30.52#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.10:22:30.52#ibcon#enter wrdev, iclass 26, count 0 2006.173.10:22:30.53#ibcon#first serial, iclass 26, count 0 2006.173.10:22:30.53#ibcon#enter sib2, iclass 26, count 0 2006.173.10:22:30.53#ibcon#flushed, iclass 26, count 0 2006.173.10:22:30.53#ibcon#about to write, iclass 26, count 0 2006.173.10:22:30.53#ibcon#wrote, iclass 26, count 0 2006.173.10:22:30.53#ibcon#about to read 3, iclass 26, count 0 2006.173.10:22:30.54#ibcon#read 3, iclass 26, count 0 2006.173.10:22:30.54#ibcon#about to read 4, iclass 26, count 0 2006.173.10:22:30.54#ibcon#read 4, iclass 26, count 0 2006.173.10:22:30.55#ibcon#about to read 5, iclass 26, count 0 2006.173.10:22:30.55#ibcon#read 5, iclass 26, count 0 2006.173.10:22:30.55#ibcon#about to read 6, iclass 26, count 0 2006.173.10:22:30.55#ibcon#read 6, iclass 26, count 0 2006.173.10:22:30.55#ibcon#end of sib2, iclass 26, count 0 2006.173.10:22:30.55#ibcon#*mode == 0, iclass 26, count 0 2006.173.10:22:30.55#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.10:22:30.55#ibcon#[25=USB\r\n] 2006.173.10:22:30.55#ibcon#*before write, iclass 26, count 0 2006.173.10:22:30.55#ibcon#enter sib2, iclass 26, count 0 2006.173.10:22:30.55#ibcon#flushed, iclass 26, count 0 2006.173.10:22:30.55#ibcon#about to write, iclass 26, count 0 2006.173.10:22:30.55#ibcon#wrote, iclass 26, count 0 2006.173.10:22:30.55#ibcon#about to read 3, iclass 26, count 0 2006.173.10:22:30.57#ibcon#read 3, iclass 26, count 0 2006.173.10:22:30.57#ibcon#about to read 4, iclass 26, count 0 2006.173.10:22:30.57#ibcon#read 4, iclass 26, count 0 2006.173.10:22:30.57#ibcon#about to read 5, iclass 26, count 0 2006.173.10:22:30.57#ibcon#read 5, iclass 26, count 0 2006.173.10:22:30.57#ibcon#about to read 6, iclass 26, count 0 2006.173.10:22:30.57#ibcon#read 6, iclass 26, count 0 2006.173.10:22:30.57#ibcon#end of sib2, iclass 26, count 0 2006.173.10:22:30.58#ibcon#*after write, iclass 26, count 0 2006.173.10:22:30.58#ibcon#*before return 0, iclass 26, count 0 2006.173.10:22:30.58#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.10:22:30.58#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.10:22:30.58#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.10:22:30.58#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.10:22:30.58$vck44/valo=8,884.99 2006.173.10:22:30.58#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.10:22:30.58#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.10:22:30.58#ibcon#ireg 17 cls_cnt 0 2006.173.10:22:30.58#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.10:22:30.58#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.10:22:30.58#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.10:22:30.58#ibcon#enter wrdev, iclass 28, count 0 2006.173.10:22:30.58#ibcon#first serial, iclass 28, count 0 2006.173.10:22:30.58#ibcon#enter sib2, iclass 28, count 0 2006.173.10:22:30.58#ibcon#flushed, iclass 28, count 0 2006.173.10:22:30.58#ibcon#about to write, iclass 28, count 0 2006.173.10:22:30.58#ibcon#wrote, iclass 28, count 0 2006.173.10:22:30.58#ibcon#about to read 3, iclass 28, count 0 2006.173.10:22:30.59#ibcon#read 3, iclass 28, count 0 2006.173.10:22:30.59#ibcon#about to read 4, iclass 28, count 0 2006.173.10:22:30.59#ibcon#read 4, iclass 28, count 0 2006.173.10:22:30.59#ibcon#about to read 5, iclass 28, count 0 2006.173.10:22:30.59#ibcon#read 5, iclass 28, count 0 2006.173.10:22:30.59#ibcon#about to read 6, iclass 28, count 0 2006.173.10:22:30.59#ibcon#read 6, iclass 28, count 0 2006.173.10:22:30.60#ibcon#end of sib2, iclass 28, count 0 2006.173.10:22:30.60#ibcon#*mode == 0, iclass 28, count 0 2006.173.10:22:30.60#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.10:22:30.60#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.10:22:30.60#ibcon#*before write, iclass 28, count 0 2006.173.10:22:30.60#ibcon#enter sib2, iclass 28, count 0 2006.173.10:22:30.60#ibcon#flushed, iclass 28, count 0 2006.173.10:22:30.60#ibcon#about to write, iclass 28, count 0 2006.173.10:22:30.60#ibcon#wrote, iclass 28, count 0 2006.173.10:22:30.60#ibcon#about to read 3, iclass 28, count 0 2006.173.10:22:30.63#ibcon#read 3, iclass 28, count 0 2006.173.10:22:30.63#ibcon#about to read 4, iclass 28, count 0 2006.173.10:22:30.63#ibcon#read 4, iclass 28, count 0 2006.173.10:22:30.63#ibcon#about to read 5, iclass 28, count 0 2006.173.10:22:30.63#ibcon#read 5, iclass 28, count 0 2006.173.10:22:30.63#ibcon#about to read 6, iclass 28, count 0 2006.173.10:22:30.63#ibcon#read 6, iclass 28, count 0 2006.173.10:22:30.64#ibcon#end of sib2, iclass 28, count 0 2006.173.10:22:30.64#ibcon#*after write, iclass 28, count 0 2006.173.10:22:30.64#ibcon#*before return 0, iclass 28, count 0 2006.173.10:22:30.64#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.10:22:30.64#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.10:22:30.64#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.10:22:30.64#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.10:22:30.64$vck44/va=8,4 2006.173.10:22:30.64#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.10:22:30.64#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.10:22:30.64#ibcon#ireg 11 cls_cnt 2 2006.173.10:22:30.64#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.10:22:30.69#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.10:22:30.69#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.10:22:30.69#ibcon#enter wrdev, iclass 30, count 2 2006.173.10:22:30.69#ibcon#first serial, iclass 30, count 2 2006.173.10:22:30.69#ibcon#enter sib2, iclass 30, count 2 2006.173.10:22:30.69#ibcon#flushed, iclass 30, count 2 2006.173.10:22:30.69#ibcon#about to write, iclass 30, count 2 2006.173.10:22:30.70#ibcon#wrote, iclass 30, count 2 2006.173.10:22:30.70#ibcon#about to read 3, iclass 30, count 2 2006.173.10:22:30.71#ibcon#read 3, iclass 30, count 2 2006.173.10:22:30.71#ibcon#about to read 4, iclass 30, count 2 2006.173.10:22:30.71#ibcon#read 4, iclass 30, count 2 2006.173.10:22:30.71#ibcon#about to read 5, iclass 30, count 2 2006.173.10:22:30.71#ibcon#read 5, iclass 30, count 2 2006.173.10:22:30.71#ibcon#about to read 6, iclass 30, count 2 2006.173.10:22:30.71#ibcon#read 6, iclass 30, count 2 2006.173.10:22:30.72#ibcon#end of sib2, iclass 30, count 2 2006.173.10:22:30.72#ibcon#*mode == 0, iclass 30, count 2 2006.173.10:22:30.72#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.10:22:30.72#ibcon#[25=AT08-04\r\n] 2006.173.10:22:30.72#ibcon#*before write, iclass 30, count 2 2006.173.10:22:30.72#ibcon#enter sib2, iclass 30, count 2 2006.173.10:22:30.72#ibcon#flushed, iclass 30, count 2 2006.173.10:22:30.72#ibcon#about to write, iclass 30, count 2 2006.173.10:22:30.72#ibcon#wrote, iclass 30, count 2 2006.173.10:22:30.72#ibcon#about to read 3, iclass 30, count 2 2006.173.10:22:30.74#ibcon#read 3, iclass 30, count 2 2006.173.10:22:30.74#ibcon#about to read 4, iclass 30, count 2 2006.173.10:22:30.74#ibcon#read 4, iclass 30, count 2 2006.173.10:22:30.74#ibcon#about to read 5, iclass 30, count 2 2006.173.10:22:30.74#ibcon#read 5, iclass 30, count 2 2006.173.10:22:30.74#ibcon#about to read 6, iclass 30, count 2 2006.173.10:22:30.74#ibcon#read 6, iclass 30, count 2 2006.173.10:22:30.74#ibcon#end of sib2, iclass 30, count 2 2006.173.10:22:30.74#ibcon#*after write, iclass 30, count 2 2006.173.10:22:30.75#ibcon#*before return 0, iclass 30, count 2 2006.173.10:22:30.75#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.10:22:30.75#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.10:22:30.75#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.10:22:30.75#ibcon#ireg 7 cls_cnt 0 2006.173.10:22:30.75#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.10:22:30.86#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.10:22:30.86#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.10:22:30.86#ibcon#enter wrdev, iclass 30, count 0 2006.173.10:22:30.86#ibcon#first serial, iclass 30, count 0 2006.173.10:22:30.86#ibcon#enter sib2, iclass 30, count 0 2006.173.10:22:30.86#ibcon#flushed, iclass 30, count 0 2006.173.10:22:30.86#ibcon#about to write, iclass 30, count 0 2006.173.10:22:30.87#ibcon#wrote, iclass 30, count 0 2006.173.10:22:30.87#ibcon#about to read 3, iclass 30, count 0 2006.173.10:22:30.88#ibcon#read 3, iclass 30, count 0 2006.173.10:22:30.88#ibcon#about to read 4, iclass 30, count 0 2006.173.10:22:30.88#ibcon#read 4, iclass 30, count 0 2006.173.10:22:30.88#ibcon#about to read 5, iclass 30, count 0 2006.173.10:22:30.88#ibcon#read 5, iclass 30, count 0 2006.173.10:22:30.88#ibcon#about to read 6, iclass 30, count 0 2006.173.10:22:30.88#ibcon#read 6, iclass 30, count 0 2006.173.10:22:30.88#ibcon#end of sib2, iclass 30, count 0 2006.173.10:22:30.89#ibcon#*mode == 0, iclass 30, count 0 2006.173.10:22:30.89#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.10:22:30.89#ibcon#[25=USB\r\n] 2006.173.10:22:30.89#ibcon#*before write, iclass 30, count 0 2006.173.10:22:30.89#ibcon#enter sib2, iclass 30, count 0 2006.173.10:22:30.89#ibcon#flushed, iclass 30, count 0 2006.173.10:22:30.89#ibcon#about to write, iclass 30, count 0 2006.173.10:22:30.89#ibcon#wrote, iclass 30, count 0 2006.173.10:22:30.89#ibcon#about to read 3, iclass 30, count 0 2006.173.10:22:30.91#ibcon#read 3, iclass 30, count 0 2006.173.10:22:30.91#ibcon#about to read 4, iclass 30, count 0 2006.173.10:22:30.91#ibcon#read 4, iclass 30, count 0 2006.173.10:22:30.91#ibcon#about to read 5, iclass 30, count 0 2006.173.10:22:30.91#ibcon#read 5, iclass 30, count 0 2006.173.10:22:30.91#ibcon#about to read 6, iclass 30, count 0 2006.173.10:22:30.92#ibcon#read 6, iclass 30, count 0 2006.173.10:22:30.92#ibcon#end of sib2, iclass 30, count 0 2006.173.10:22:30.92#ibcon#*after write, iclass 30, count 0 2006.173.10:22:30.92#ibcon#*before return 0, iclass 30, count 0 2006.173.10:22:30.92#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.10:22:30.92#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.10:22:30.92#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.10:22:30.92#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.10:22:30.92$vck44/vblo=1,629.99 2006.173.10:22:30.92#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.10:22:30.92#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.10:22:30.92#ibcon#ireg 17 cls_cnt 0 2006.173.10:22:30.92#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.10:22:30.92#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.10:22:30.92#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.10:22:30.92#ibcon#enter wrdev, iclass 32, count 0 2006.173.10:22:30.92#ibcon#first serial, iclass 32, count 0 2006.173.10:22:30.92#ibcon#enter sib2, iclass 32, count 0 2006.173.10:22:30.92#ibcon#flushed, iclass 32, count 0 2006.173.10:22:30.92#ibcon#about to write, iclass 32, count 0 2006.173.10:22:30.92#ibcon#wrote, iclass 32, count 0 2006.173.10:22:30.92#ibcon#about to read 3, iclass 32, count 0 2006.173.10:22:30.93#ibcon#read 3, iclass 32, count 0 2006.173.10:22:30.93#ibcon#about to read 4, iclass 32, count 0 2006.173.10:22:30.93#ibcon#read 4, iclass 32, count 0 2006.173.10:22:30.93#ibcon#about to read 5, iclass 32, count 0 2006.173.10:22:30.93#ibcon#read 5, iclass 32, count 0 2006.173.10:22:30.93#ibcon#about to read 6, iclass 32, count 0 2006.173.10:22:30.93#ibcon#read 6, iclass 32, count 0 2006.173.10:22:30.93#ibcon#end of sib2, iclass 32, count 0 2006.173.10:22:30.93#ibcon#*mode == 0, iclass 32, count 0 2006.173.10:22:30.93#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.10:22:30.94#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.10:22:30.94#ibcon#*before write, iclass 32, count 0 2006.173.10:22:30.94#ibcon#enter sib2, iclass 32, count 0 2006.173.10:22:30.94#ibcon#flushed, iclass 32, count 0 2006.173.10:22:30.94#ibcon#about to write, iclass 32, count 0 2006.173.10:22:30.94#ibcon#wrote, iclass 32, count 0 2006.173.10:22:30.94#ibcon#about to read 3, iclass 32, count 0 2006.173.10:22:30.97#ibcon#read 3, iclass 32, count 0 2006.173.10:22:30.97#ibcon#about to read 4, iclass 32, count 0 2006.173.10:22:30.97#ibcon#read 4, iclass 32, count 0 2006.173.10:22:30.97#ibcon#about to read 5, iclass 32, count 0 2006.173.10:22:30.97#ibcon#read 5, iclass 32, count 0 2006.173.10:22:30.97#ibcon#about to read 6, iclass 32, count 0 2006.173.10:22:30.97#ibcon#read 6, iclass 32, count 0 2006.173.10:22:30.98#ibcon#end of sib2, iclass 32, count 0 2006.173.10:22:30.98#ibcon#*after write, iclass 32, count 0 2006.173.10:22:30.98#ibcon#*before return 0, iclass 32, count 0 2006.173.10:22:30.98#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.10:22:30.98#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.10:22:30.98#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.10:22:30.98#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.10:22:30.98$vck44/vb=1,4 2006.173.10:22:30.98#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.10:22:30.98#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.10:22:30.98#ibcon#ireg 11 cls_cnt 2 2006.173.10:22:30.98#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.10:22:30.98#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.10:22:30.98#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.10:22:30.98#ibcon#enter wrdev, iclass 34, count 2 2006.173.10:22:30.98#ibcon#first serial, iclass 34, count 2 2006.173.10:22:30.98#ibcon#enter sib2, iclass 34, count 2 2006.173.10:22:30.98#ibcon#flushed, iclass 34, count 2 2006.173.10:22:30.98#ibcon#about to write, iclass 34, count 2 2006.173.10:22:30.98#ibcon#wrote, iclass 34, count 2 2006.173.10:22:30.98#ibcon#about to read 3, iclass 34, count 2 2006.173.10:22:30.99#ibcon#read 3, iclass 34, count 2 2006.173.10:22:30.99#ibcon#about to read 4, iclass 34, count 2 2006.173.10:22:30.99#ibcon#read 4, iclass 34, count 2 2006.173.10:22:30.99#ibcon#about to read 5, iclass 34, count 2 2006.173.10:22:30.99#ibcon#read 5, iclass 34, count 2 2006.173.10:22:30.99#ibcon#about to read 6, iclass 34, count 2 2006.173.10:22:30.99#ibcon#read 6, iclass 34, count 2 2006.173.10:22:30.99#ibcon#end of sib2, iclass 34, count 2 2006.173.10:22:30.99#ibcon#*mode == 0, iclass 34, count 2 2006.173.10:22:30.99#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.10:22:31.00#ibcon#[27=AT01-04\r\n] 2006.173.10:22:31.00#ibcon#*before write, iclass 34, count 2 2006.173.10:22:31.00#ibcon#enter sib2, iclass 34, count 2 2006.173.10:22:31.00#ibcon#flushed, iclass 34, count 2 2006.173.10:22:31.00#ibcon#about to write, iclass 34, count 2 2006.173.10:22:31.00#ibcon#wrote, iclass 34, count 2 2006.173.10:22:31.00#ibcon#about to read 3, iclass 34, count 2 2006.173.10:22:31.02#ibcon#read 3, iclass 34, count 2 2006.173.10:22:31.02#ibcon#about to read 4, iclass 34, count 2 2006.173.10:22:31.02#ibcon#read 4, iclass 34, count 2 2006.173.10:22:31.02#ibcon#about to read 5, iclass 34, count 2 2006.173.10:22:31.02#ibcon#read 5, iclass 34, count 2 2006.173.10:22:31.02#ibcon#about to read 6, iclass 34, count 2 2006.173.10:22:31.02#ibcon#read 6, iclass 34, count 2 2006.173.10:22:31.03#ibcon#end of sib2, iclass 34, count 2 2006.173.10:22:31.03#ibcon#*after write, iclass 34, count 2 2006.173.10:22:31.03#ibcon#*before return 0, iclass 34, count 2 2006.173.10:22:31.03#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.10:22:31.03#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.10:22:31.03#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.10:22:31.03#ibcon#ireg 7 cls_cnt 0 2006.173.10:22:31.03#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.10:22:31.15#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.10:22:31.15#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.10:22:31.15#ibcon#enter wrdev, iclass 34, count 0 2006.173.10:22:31.15#ibcon#first serial, iclass 34, count 0 2006.173.10:22:31.15#ibcon#enter sib2, iclass 34, count 0 2006.173.10:22:31.15#ibcon#flushed, iclass 34, count 0 2006.173.10:22:31.15#ibcon#about to write, iclass 34, count 0 2006.173.10:22:31.15#ibcon#wrote, iclass 34, count 0 2006.173.10:22:31.15#ibcon#about to read 3, iclass 34, count 0 2006.173.10:22:31.16#ibcon#read 3, iclass 34, count 0 2006.173.10:22:31.16#ibcon#about to read 4, iclass 34, count 0 2006.173.10:22:31.16#ibcon#read 4, iclass 34, count 0 2006.173.10:22:31.16#ibcon#about to read 5, iclass 34, count 0 2006.173.10:22:31.16#ibcon#read 5, iclass 34, count 0 2006.173.10:22:31.16#ibcon#about to read 6, iclass 34, count 0 2006.173.10:22:31.16#ibcon#read 6, iclass 34, count 0 2006.173.10:22:31.16#ibcon#end of sib2, iclass 34, count 0 2006.173.10:22:31.16#ibcon#*mode == 0, iclass 34, count 0 2006.173.10:22:31.16#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.10:22:31.17#ibcon#[27=USB\r\n] 2006.173.10:22:31.17#ibcon#*before write, iclass 34, count 0 2006.173.10:22:31.17#ibcon#enter sib2, iclass 34, count 0 2006.173.10:22:31.17#ibcon#flushed, iclass 34, count 0 2006.173.10:22:31.17#ibcon#about to write, iclass 34, count 0 2006.173.10:22:31.17#ibcon#wrote, iclass 34, count 0 2006.173.10:22:31.17#ibcon#about to read 3, iclass 34, count 0 2006.173.10:22:31.19#ibcon#read 3, iclass 34, count 0 2006.173.10:22:31.19#ibcon#about to read 4, iclass 34, count 0 2006.173.10:22:31.19#ibcon#read 4, iclass 34, count 0 2006.173.10:22:31.19#ibcon#about to read 5, iclass 34, count 0 2006.173.10:22:31.19#ibcon#read 5, iclass 34, count 0 2006.173.10:22:31.19#ibcon#about to read 6, iclass 34, count 0 2006.173.10:22:31.19#ibcon#read 6, iclass 34, count 0 2006.173.10:22:31.19#ibcon#end of sib2, iclass 34, count 0 2006.173.10:22:31.20#ibcon#*after write, iclass 34, count 0 2006.173.10:22:31.20#ibcon#*before return 0, iclass 34, count 0 2006.173.10:22:31.20#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.10:22:31.20#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.10:22:31.20#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.10:22:31.20#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.10:22:31.20$vck44/vblo=2,634.99 2006.173.10:22:31.20#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.10:22:31.20#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.10:22:31.20#ibcon#ireg 17 cls_cnt 0 2006.173.10:22:31.20#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.10:22:31.20#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.10:22:31.20#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.10:22:31.20#ibcon#enter wrdev, iclass 36, count 0 2006.173.10:22:31.20#ibcon#first serial, iclass 36, count 0 2006.173.10:22:31.20#ibcon#enter sib2, iclass 36, count 0 2006.173.10:22:31.20#ibcon#flushed, iclass 36, count 0 2006.173.10:22:31.20#ibcon#about to write, iclass 36, count 0 2006.173.10:22:31.20#ibcon#wrote, iclass 36, count 0 2006.173.10:22:31.20#ibcon#about to read 3, iclass 36, count 0 2006.173.10:22:31.21#ibcon#read 3, iclass 36, count 0 2006.173.10:22:31.21#ibcon#about to read 4, iclass 36, count 0 2006.173.10:22:31.21#ibcon#read 4, iclass 36, count 0 2006.173.10:22:31.21#ibcon#about to read 5, iclass 36, count 0 2006.173.10:22:31.21#ibcon#read 5, iclass 36, count 0 2006.173.10:22:31.21#ibcon#about to read 6, iclass 36, count 0 2006.173.10:22:31.21#ibcon#read 6, iclass 36, count 0 2006.173.10:22:31.21#ibcon#end of sib2, iclass 36, count 0 2006.173.10:22:31.21#ibcon#*mode == 0, iclass 36, count 0 2006.173.10:22:31.21#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.10:22:31.21#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.10:22:31.22#ibcon#*before write, iclass 36, count 0 2006.173.10:22:31.22#ibcon#enter sib2, iclass 36, count 0 2006.173.10:22:31.22#ibcon#flushed, iclass 36, count 0 2006.173.10:22:31.22#ibcon#about to write, iclass 36, count 0 2006.173.10:22:31.22#ibcon#wrote, iclass 36, count 0 2006.173.10:22:31.22#ibcon#about to read 3, iclass 36, count 0 2006.173.10:22:31.25#ibcon#read 3, iclass 36, count 0 2006.173.10:22:31.25#ibcon#about to read 4, iclass 36, count 0 2006.173.10:22:31.25#ibcon#read 4, iclass 36, count 0 2006.173.10:22:31.25#ibcon#about to read 5, iclass 36, count 0 2006.173.10:22:31.25#ibcon#read 5, iclass 36, count 0 2006.173.10:22:31.25#ibcon#about to read 6, iclass 36, count 0 2006.173.10:22:31.26#ibcon#read 6, iclass 36, count 0 2006.173.10:22:31.26#ibcon#end of sib2, iclass 36, count 0 2006.173.10:22:31.26#ibcon#*after write, iclass 36, count 0 2006.173.10:22:31.26#ibcon#*before return 0, iclass 36, count 0 2006.173.10:22:31.26#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.10:22:31.26#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.10:22:31.26#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.10:22:31.26#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.10:22:31.26$vck44/vb=2,4 2006.173.10:22:31.26#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.10:22:31.26#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.10:22:31.26#ibcon#ireg 11 cls_cnt 2 2006.173.10:22:31.26#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.10:22:31.31#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.10:22:31.31#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.10:22:31.31#ibcon#enter wrdev, iclass 38, count 2 2006.173.10:22:31.31#ibcon#first serial, iclass 38, count 2 2006.173.10:22:31.31#ibcon#enter sib2, iclass 38, count 2 2006.173.10:22:31.31#ibcon#flushed, iclass 38, count 2 2006.173.10:22:31.31#ibcon#about to write, iclass 38, count 2 2006.173.10:22:31.32#ibcon#wrote, iclass 38, count 2 2006.173.10:22:31.32#ibcon#about to read 3, iclass 38, count 2 2006.173.10:22:31.33#ibcon#read 3, iclass 38, count 2 2006.173.10:22:31.33#ibcon#about to read 4, iclass 38, count 2 2006.173.10:22:31.33#ibcon#read 4, iclass 38, count 2 2006.173.10:22:31.33#ibcon#about to read 5, iclass 38, count 2 2006.173.10:22:31.33#ibcon#read 5, iclass 38, count 2 2006.173.10:22:31.33#ibcon#about to read 6, iclass 38, count 2 2006.173.10:22:31.33#ibcon#read 6, iclass 38, count 2 2006.173.10:22:31.33#ibcon#end of sib2, iclass 38, count 2 2006.173.10:22:31.33#ibcon#*mode == 0, iclass 38, count 2 2006.173.10:22:31.33#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.10:22:31.33#ibcon#[27=AT02-04\r\n] 2006.173.10:22:31.34#ibcon#*before write, iclass 38, count 2 2006.173.10:22:31.34#ibcon#enter sib2, iclass 38, count 2 2006.173.10:22:31.34#ibcon#flushed, iclass 38, count 2 2006.173.10:22:31.34#ibcon#about to write, iclass 38, count 2 2006.173.10:22:31.34#ibcon#wrote, iclass 38, count 2 2006.173.10:22:31.34#ibcon#about to read 3, iclass 38, count 2 2006.173.10:22:31.36#ibcon#read 3, iclass 38, count 2 2006.173.10:22:31.36#ibcon#about to read 4, iclass 38, count 2 2006.173.10:22:31.36#ibcon#read 4, iclass 38, count 2 2006.173.10:22:31.36#ibcon#about to read 5, iclass 38, count 2 2006.173.10:22:31.36#ibcon#read 5, iclass 38, count 2 2006.173.10:22:31.36#ibcon#about to read 6, iclass 38, count 2 2006.173.10:22:31.36#ibcon#read 6, iclass 38, count 2 2006.173.10:22:31.36#ibcon#end of sib2, iclass 38, count 2 2006.173.10:22:31.36#ibcon#*after write, iclass 38, count 2 2006.173.10:22:31.36#ibcon#*before return 0, iclass 38, count 2 2006.173.10:22:31.37#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.10:22:31.37#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.10:22:31.37#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.10:22:31.37#ibcon#ireg 7 cls_cnt 0 2006.173.10:22:31.37#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.10:22:31.48#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.10:22:31.48#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.10:22:31.48#ibcon#enter wrdev, iclass 38, count 0 2006.173.10:22:31.48#ibcon#first serial, iclass 38, count 0 2006.173.10:22:31.48#ibcon#enter sib2, iclass 38, count 0 2006.173.10:22:31.48#ibcon#flushed, iclass 38, count 0 2006.173.10:22:31.48#ibcon#about to write, iclass 38, count 0 2006.173.10:22:31.48#ibcon#wrote, iclass 38, count 0 2006.173.10:22:31.49#ibcon#about to read 3, iclass 38, count 0 2006.173.10:22:31.50#ibcon#read 3, iclass 38, count 0 2006.173.10:22:31.50#ibcon#about to read 4, iclass 38, count 0 2006.173.10:22:31.50#ibcon#read 4, iclass 38, count 0 2006.173.10:22:31.50#ibcon#about to read 5, iclass 38, count 0 2006.173.10:22:31.50#ibcon#read 5, iclass 38, count 0 2006.173.10:22:31.50#ibcon#about to read 6, iclass 38, count 0 2006.173.10:22:31.50#ibcon#read 6, iclass 38, count 0 2006.173.10:22:31.51#ibcon#end of sib2, iclass 38, count 0 2006.173.10:22:31.51#ibcon#*mode == 0, iclass 38, count 0 2006.173.10:22:31.51#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.10:22:31.51#ibcon#[27=USB\r\n] 2006.173.10:22:31.51#ibcon#*before write, iclass 38, count 0 2006.173.10:22:31.51#ibcon#enter sib2, iclass 38, count 0 2006.173.10:22:31.51#ibcon#flushed, iclass 38, count 0 2006.173.10:22:31.51#ibcon#about to write, iclass 38, count 0 2006.173.10:22:31.51#ibcon#wrote, iclass 38, count 0 2006.173.10:22:31.51#ibcon#about to read 3, iclass 38, count 0 2006.173.10:22:31.53#ibcon#read 3, iclass 38, count 0 2006.173.10:22:31.53#ibcon#about to read 4, iclass 38, count 0 2006.173.10:22:31.53#ibcon#read 4, iclass 38, count 0 2006.173.10:22:31.53#ibcon#about to read 5, iclass 38, count 0 2006.173.10:22:31.53#ibcon#read 5, iclass 38, count 0 2006.173.10:22:31.53#ibcon#about to read 6, iclass 38, count 0 2006.173.10:22:31.53#ibcon#read 6, iclass 38, count 0 2006.173.10:22:31.53#ibcon#end of sib2, iclass 38, count 0 2006.173.10:22:31.54#ibcon#*after write, iclass 38, count 0 2006.173.10:22:31.54#ibcon#*before return 0, iclass 38, count 0 2006.173.10:22:31.54#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.10:22:31.54#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.10:22:31.54#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.10:22:31.54#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.10:22:31.54$vck44/vblo=3,649.99 2006.173.10:22:31.54#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.10:22:31.54#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.10:22:31.54#ibcon#ireg 17 cls_cnt 0 2006.173.10:22:31.54#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.10:22:31.54#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.10:22:31.54#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.10:22:31.54#ibcon#enter wrdev, iclass 40, count 0 2006.173.10:22:31.54#ibcon#first serial, iclass 40, count 0 2006.173.10:22:31.54#ibcon#enter sib2, iclass 40, count 0 2006.173.10:22:31.54#ibcon#flushed, iclass 40, count 0 2006.173.10:22:31.54#ibcon#about to write, iclass 40, count 0 2006.173.10:22:31.54#ibcon#wrote, iclass 40, count 0 2006.173.10:22:31.54#ibcon#about to read 3, iclass 40, count 0 2006.173.10:22:31.55#ibcon#read 3, iclass 40, count 0 2006.173.10:22:31.55#ibcon#about to read 4, iclass 40, count 0 2006.173.10:22:31.55#ibcon#read 4, iclass 40, count 0 2006.173.10:22:31.56#ibcon#about to read 5, iclass 40, count 0 2006.173.10:22:31.56#ibcon#read 5, iclass 40, count 0 2006.173.10:22:31.56#ibcon#about to read 6, iclass 40, count 0 2006.173.10:22:31.56#ibcon#read 6, iclass 40, count 0 2006.173.10:22:31.56#ibcon#end of sib2, iclass 40, count 0 2006.173.10:22:31.56#ibcon#*mode == 0, iclass 40, count 0 2006.173.10:22:31.56#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.10:22:31.56#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.10:22:31.56#ibcon#*before write, iclass 40, count 0 2006.173.10:22:31.56#ibcon#enter sib2, iclass 40, count 0 2006.173.10:22:31.56#ibcon#flushed, iclass 40, count 0 2006.173.10:22:31.56#ibcon#about to write, iclass 40, count 0 2006.173.10:22:31.56#ibcon#wrote, iclass 40, count 0 2006.173.10:22:31.56#ibcon#about to read 3, iclass 40, count 0 2006.173.10:22:31.59#ibcon#read 3, iclass 40, count 0 2006.173.10:22:31.59#ibcon#about to read 4, iclass 40, count 0 2006.173.10:22:31.59#ibcon#read 4, iclass 40, count 0 2006.173.10:22:31.60#ibcon#about to read 5, iclass 40, count 0 2006.173.10:22:31.60#ibcon#read 5, iclass 40, count 0 2006.173.10:22:31.60#ibcon#about to read 6, iclass 40, count 0 2006.173.10:22:31.60#ibcon#read 6, iclass 40, count 0 2006.173.10:22:31.60#ibcon#end of sib2, iclass 40, count 0 2006.173.10:22:31.60#ibcon#*after write, iclass 40, count 0 2006.173.10:22:31.60#ibcon#*before return 0, iclass 40, count 0 2006.173.10:22:31.60#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.10:22:31.60#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.10:22:31.60#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.10:22:31.60#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.10:22:31.60$vck44/vb=3,4 2006.173.10:22:31.60#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.10:22:31.60#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.10:22:31.60#ibcon#ireg 11 cls_cnt 2 2006.173.10:22:31.60#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.10:22:31.65#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.10:22:31.65#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.10:22:31.65#ibcon#enter wrdev, iclass 4, count 2 2006.173.10:22:31.65#ibcon#first serial, iclass 4, count 2 2006.173.10:22:31.65#ibcon#enter sib2, iclass 4, count 2 2006.173.10:22:31.65#ibcon#flushed, iclass 4, count 2 2006.173.10:22:31.65#ibcon#about to write, iclass 4, count 2 2006.173.10:22:31.66#ibcon#wrote, iclass 4, count 2 2006.173.10:22:31.66#ibcon#about to read 3, iclass 4, count 2 2006.173.10:22:31.67#ibcon#read 3, iclass 4, count 2 2006.173.10:22:31.67#ibcon#about to read 4, iclass 4, count 2 2006.173.10:22:31.67#ibcon#read 4, iclass 4, count 2 2006.173.10:22:31.67#ibcon#about to read 5, iclass 4, count 2 2006.173.10:22:31.67#ibcon#read 5, iclass 4, count 2 2006.173.10:22:31.67#ibcon#about to read 6, iclass 4, count 2 2006.173.10:22:31.67#ibcon#read 6, iclass 4, count 2 2006.173.10:22:31.68#ibcon#end of sib2, iclass 4, count 2 2006.173.10:22:31.68#ibcon#*mode == 0, iclass 4, count 2 2006.173.10:22:31.68#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.10:22:31.68#ibcon#[27=AT03-04\r\n] 2006.173.10:22:31.68#ibcon#*before write, iclass 4, count 2 2006.173.10:22:31.68#ibcon#enter sib2, iclass 4, count 2 2006.173.10:22:31.68#ibcon#flushed, iclass 4, count 2 2006.173.10:22:31.68#ibcon#about to write, iclass 4, count 2 2006.173.10:22:31.68#ibcon#wrote, iclass 4, count 2 2006.173.10:22:31.68#ibcon#about to read 3, iclass 4, count 2 2006.173.10:22:31.70#ibcon#read 3, iclass 4, count 2 2006.173.10:22:31.70#ibcon#about to read 4, iclass 4, count 2 2006.173.10:22:31.70#ibcon#read 4, iclass 4, count 2 2006.173.10:22:31.70#ibcon#about to read 5, iclass 4, count 2 2006.173.10:22:31.70#ibcon#read 5, iclass 4, count 2 2006.173.10:22:31.70#ibcon#about to read 6, iclass 4, count 2 2006.173.10:22:31.70#ibcon#read 6, iclass 4, count 2 2006.173.10:22:31.71#ibcon#end of sib2, iclass 4, count 2 2006.173.10:22:31.71#ibcon#*after write, iclass 4, count 2 2006.173.10:22:31.71#ibcon#*before return 0, iclass 4, count 2 2006.173.10:22:31.71#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.10:22:31.71#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.10:22:31.71#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.10:22:31.71#ibcon#ireg 7 cls_cnt 0 2006.173.10:22:31.71#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.10:22:31.82#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.10:22:31.82#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.10:22:31.82#ibcon#enter wrdev, iclass 4, count 0 2006.173.10:22:31.82#ibcon#first serial, iclass 4, count 0 2006.173.10:22:31.82#ibcon#enter sib2, iclass 4, count 0 2006.173.10:22:31.82#ibcon#flushed, iclass 4, count 0 2006.173.10:22:31.82#ibcon#about to write, iclass 4, count 0 2006.173.10:22:31.82#ibcon#wrote, iclass 4, count 0 2006.173.10:22:31.83#ibcon#about to read 3, iclass 4, count 0 2006.173.10:22:31.84#ibcon#read 3, iclass 4, count 0 2006.173.10:22:31.84#ibcon#about to read 4, iclass 4, count 0 2006.173.10:22:31.84#ibcon#read 4, iclass 4, count 0 2006.173.10:22:31.84#ibcon#about to read 5, iclass 4, count 0 2006.173.10:22:31.84#ibcon#read 5, iclass 4, count 0 2006.173.10:22:31.84#ibcon#about to read 6, iclass 4, count 0 2006.173.10:22:31.84#ibcon#read 6, iclass 4, count 0 2006.173.10:22:31.84#ibcon#end of sib2, iclass 4, count 0 2006.173.10:22:31.84#ibcon#*mode == 0, iclass 4, count 0 2006.173.10:22:31.85#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.10:22:31.85#ibcon#[27=USB\r\n] 2006.173.10:22:31.85#ibcon#*before write, iclass 4, count 0 2006.173.10:22:31.85#ibcon#enter sib2, iclass 4, count 0 2006.173.10:22:31.85#ibcon#flushed, iclass 4, count 0 2006.173.10:22:31.85#ibcon#about to write, iclass 4, count 0 2006.173.10:22:31.85#ibcon#wrote, iclass 4, count 0 2006.173.10:22:31.85#ibcon#about to read 3, iclass 4, count 0 2006.173.10:22:31.87#ibcon#read 3, iclass 4, count 0 2006.173.10:22:31.87#ibcon#about to read 4, iclass 4, count 0 2006.173.10:22:31.87#ibcon#read 4, iclass 4, count 0 2006.173.10:22:31.87#ibcon#about to read 5, iclass 4, count 0 2006.173.10:22:31.87#ibcon#read 5, iclass 4, count 0 2006.173.10:22:31.87#ibcon#about to read 6, iclass 4, count 0 2006.173.10:22:31.87#ibcon#read 6, iclass 4, count 0 2006.173.10:22:31.87#ibcon#end of sib2, iclass 4, count 0 2006.173.10:22:31.87#ibcon#*after write, iclass 4, count 0 2006.173.10:22:31.87#ibcon#*before return 0, iclass 4, count 0 2006.173.10:22:31.88#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.10:22:31.88#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.10:22:31.88#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.10:22:31.88#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.10:22:31.88$vck44/vblo=4,679.99 2006.173.10:22:31.88#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.10:22:31.88#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.10:22:31.88#ibcon#ireg 17 cls_cnt 0 2006.173.10:22:31.88#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.10:22:31.88#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.10:22:31.88#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.10:22:31.88#ibcon#enter wrdev, iclass 6, count 0 2006.173.10:22:31.88#ibcon#first serial, iclass 6, count 0 2006.173.10:22:31.88#ibcon#enter sib2, iclass 6, count 0 2006.173.10:22:31.88#ibcon#flushed, iclass 6, count 0 2006.173.10:22:31.88#ibcon#about to write, iclass 6, count 0 2006.173.10:22:31.88#ibcon#wrote, iclass 6, count 0 2006.173.10:22:31.88#ibcon#about to read 3, iclass 6, count 0 2006.173.10:22:31.89#ibcon#read 3, iclass 6, count 0 2006.173.10:22:31.89#ibcon#about to read 4, iclass 6, count 0 2006.173.10:22:31.89#ibcon#read 4, iclass 6, count 0 2006.173.10:22:31.89#ibcon#about to read 5, iclass 6, count 0 2006.173.10:22:31.89#ibcon#read 5, iclass 6, count 0 2006.173.10:22:31.89#ibcon#about to read 6, iclass 6, count 0 2006.173.10:22:31.89#ibcon#read 6, iclass 6, count 0 2006.173.10:22:31.89#ibcon#end of sib2, iclass 6, count 0 2006.173.10:22:31.89#ibcon#*mode == 0, iclass 6, count 0 2006.173.10:22:31.89#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.10:22:31.90#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.10:22:31.90#ibcon#*before write, iclass 6, count 0 2006.173.10:22:31.90#ibcon#enter sib2, iclass 6, count 0 2006.173.10:22:31.90#ibcon#flushed, iclass 6, count 0 2006.173.10:22:31.90#ibcon#about to write, iclass 6, count 0 2006.173.10:22:31.90#ibcon#wrote, iclass 6, count 0 2006.173.10:22:31.90#ibcon#about to read 3, iclass 6, count 0 2006.173.10:22:31.93#ibcon#read 3, iclass 6, count 0 2006.173.10:22:31.93#ibcon#about to read 4, iclass 6, count 0 2006.173.10:22:31.93#ibcon#read 4, iclass 6, count 0 2006.173.10:22:31.93#ibcon#about to read 5, iclass 6, count 0 2006.173.10:22:31.93#ibcon#read 5, iclass 6, count 0 2006.173.10:22:31.93#ibcon#about to read 6, iclass 6, count 0 2006.173.10:22:31.93#ibcon#read 6, iclass 6, count 0 2006.173.10:22:31.94#ibcon#end of sib2, iclass 6, count 0 2006.173.10:22:31.94#ibcon#*after write, iclass 6, count 0 2006.173.10:22:31.94#ibcon#*before return 0, iclass 6, count 0 2006.173.10:22:31.94#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.10:22:31.94#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.10:22:31.94#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.10:22:31.94#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.10:22:31.94$vck44/vb=4,4 2006.173.10:22:31.94#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.10:22:31.94#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.10:22:31.94#ibcon#ireg 11 cls_cnt 2 2006.173.10:22:31.94#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.10:22:31.99#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.10:22:31.99#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.10:22:31.99#ibcon#enter wrdev, iclass 10, count 2 2006.173.10:22:31.99#ibcon#first serial, iclass 10, count 2 2006.173.10:22:31.99#ibcon#enter sib2, iclass 10, count 2 2006.173.10:22:31.99#ibcon#flushed, iclass 10, count 2 2006.173.10:22:31.99#ibcon#about to write, iclass 10, count 2 2006.173.10:22:32.00#ibcon#wrote, iclass 10, count 2 2006.173.10:22:32.00#ibcon#about to read 3, iclass 10, count 2 2006.173.10:22:32.01#ibcon#read 3, iclass 10, count 2 2006.173.10:22:32.01#ibcon#about to read 4, iclass 10, count 2 2006.173.10:22:32.01#ibcon#read 4, iclass 10, count 2 2006.173.10:22:32.01#ibcon#about to read 5, iclass 10, count 2 2006.173.10:22:32.01#ibcon#read 5, iclass 10, count 2 2006.173.10:22:32.01#ibcon#about to read 6, iclass 10, count 2 2006.173.10:22:32.01#ibcon#read 6, iclass 10, count 2 2006.173.10:22:32.01#ibcon#end of sib2, iclass 10, count 2 2006.173.10:22:32.02#ibcon#*mode == 0, iclass 10, count 2 2006.173.10:22:32.02#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.10:22:32.02#ibcon#[27=AT04-04\r\n] 2006.173.10:22:32.02#ibcon#*before write, iclass 10, count 2 2006.173.10:22:32.02#ibcon#enter sib2, iclass 10, count 2 2006.173.10:22:32.02#ibcon#flushed, iclass 10, count 2 2006.173.10:22:32.02#ibcon#about to write, iclass 10, count 2 2006.173.10:22:32.02#ibcon#wrote, iclass 10, count 2 2006.173.10:22:32.02#ibcon#about to read 3, iclass 10, count 2 2006.173.10:22:32.04#ibcon#read 3, iclass 10, count 2 2006.173.10:22:32.04#ibcon#about to read 4, iclass 10, count 2 2006.173.10:22:32.04#ibcon#read 4, iclass 10, count 2 2006.173.10:22:32.04#ibcon#about to read 5, iclass 10, count 2 2006.173.10:22:32.04#ibcon#read 5, iclass 10, count 2 2006.173.10:22:32.04#ibcon#about to read 6, iclass 10, count 2 2006.173.10:22:32.04#ibcon#read 6, iclass 10, count 2 2006.173.10:22:32.04#ibcon#end of sib2, iclass 10, count 2 2006.173.10:22:32.04#ibcon#*after write, iclass 10, count 2 2006.173.10:22:32.05#ibcon#*before return 0, iclass 10, count 2 2006.173.10:22:32.05#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.10:22:32.05#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.10:22:32.05#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.10:22:32.05#ibcon#ireg 7 cls_cnt 0 2006.173.10:22:32.05#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.10:22:32.16#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.10:22:32.16#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.10:22:32.16#ibcon#enter wrdev, iclass 10, count 0 2006.173.10:22:32.16#ibcon#first serial, iclass 10, count 0 2006.173.10:22:32.16#ibcon#enter sib2, iclass 10, count 0 2006.173.10:22:32.16#ibcon#flushed, iclass 10, count 0 2006.173.10:22:32.16#ibcon#about to write, iclass 10, count 0 2006.173.10:22:32.16#ibcon#wrote, iclass 10, count 0 2006.173.10:22:32.17#ibcon#about to read 3, iclass 10, count 0 2006.173.10:22:32.18#ibcon#read 3, iclass 10, count 0 2006.173.10:22:32.18#ibcon#about to read 4, iclass 10, count 0 2006.173.10:22:32.18#ibcon#read 4, iclass 10, count 0 2006.173.10:22:32.18#ibcon#about to read 5, iclass 10, count 0 2006.173.10:22:32.18#ibcon#read 5, iclass 10, count 0 2006.173.10:22:32.18#ibcon#about to read 6, iclass 10, count 0 2006.173.10:22:32.18#ibcon#read 6, iclass 10, count 0 2006.173.10:22:32.18#ibcon#end of sib2, iclass 10, count 0 2006.173.10:22:32.18#ibcon#*mode == 0, iclass 10, count 0 2006.173.10:22:32.19#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.10:22:32.19#ibcon#[27=USB\r\n] 2006.173.10:22:32.19#ibcon#*before write, iclass 10, count 0 2006.173.10:22:32.19#ibcon#enter sib2, iclass 10, count 0 2006.173.10:22:32.19#ibcon#flushed, iclass 10, count 0 2006.173.10:22:32.19#ibcon#about to write, iclass 10, count 0 2006.173.10:22:32.19#ibcon#wrote, iclass 10, count 0 2006.173.10:22:32.19#ibcon#about to read 3, iclass 10, count 0 2006.173.10:22:32.21#ibcon#read 3, iclass 10, count 0 2006.173.10:22:32.21#ibcon#about to read 4, iclass 10, count 0 2006.173.10:22:32.21#ibcon#read 4, iclass 10, count 0 2006.173.10:22:32.21#ibcon#about to read 5, iclass 10, count 0 2006.173.10:22:32.21#ibcon#read 5, iclass 10, count 0 2006.173.10:22:32.21#ibcon#about to read 6, iclass 10, count 0 2006.173.10:22:32.21#ibcon#read 6, iclass 10, count 0 2006.173.10:22:32.21#ibcon#end of sib2, iclass 10, count 0 2006.173.10:22:32.21#ibcon#*after write, iclass 10, count 0 2006.173.10:22:32.21#ibcon#*before return 0, iclass 10, count 0 2006.173.10:22:32.22#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.10:22:32.22#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.10:22:32.22#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.10:22:32.22#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.10:22:32.22$vck44/vblo=5,709.99 2006.173.10:22:32.22#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.10:22:32.22#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.10:22:32.22#ibcon#ireg 17 cls_cnt 0 2006.173.10:22:32.22#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.10:22:32.22#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.10:22:32.22#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.10:22:32.22#ibcon#enter wrdev, iclass 12, count 0 2006.173.10:22:32.22#ibcon#first serial, iclass 12, count 0 2006.173.10:22:32.22#ibcon#enter sib2, iclass 12, count 0 2006.173.10:22:32.22#ibcon#flushed, iclass 12, count 0 2006.173.10:22:32.22#ibcon#about to write, iclass 12, count 0 2006.173.10:22:32.22#ibcon#wrote, iclass 12, count 0 2006.173.10:22:32.22#ibcon#about to read 3, iclass 12, count 0 2006.173.10:22:32.23#ibcon#read 3, iclass 12, count 0 2006.173.10:22:32.23#ibcon#about to read 4, iclass 12, count 0 2006.173.10:22:32.23#ibcon#read 4, iclass 12, count 0 2006.173.10:22:32.23#ibcon#about to read 5, iclass 12, count 0 2006.173.10:22:32.23#ibcon#read 5, iclass 12, count 0 2006.173.10:22:32.23#ibcon#about to read 6, iclass 12, count 0 2006.173.10:22:32.23#ibcon#read 6, iclass 12, count 0 2006.173.10:22:32.23#ibcon#end of sib2, iclass 12, count 0 2006.173.10:22:32.23#ibcon#*mode == 0, iclass 12, count 0 2006.173.10:22:32.23#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.10:22:32.23#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.10:22:32.24#ibcon#*before write, iclass 12, count 0 2006.173.10:22:32.24#ibcon#enter sib2, iclass 12, count 0 2006.173.10:22:32.24#ibcon#flushed, iclass 12, count 0 2006.173.10:22:32.24#ibcon#about to write, iclass 12, count 0 2006.173.10:22:32.24#ibcon#wrote, iclass 12, count 0 2006.173.10:22:32.24#ibcon#about to read 3, iclass 12, count 0 2006.173.10:22:32.27#ibcon#read 3, iclass 12, count 0 2006.173.10:22:32.27#ibcon#about to read 4, iclass 12, count 0 2006.173.10:22:32.27#ibcon#read 4, iclass 12, count 0 2006.173.10:22:32.27#ibcon#about to read 5, iclass 12, count 0 2006.173.10:22:32.27#ibcon#read 5, iclass 12, count 0 2006.173.10:22:32.27#ibcon#about to read 6, iclass 12, count 0 2006.173.10:22:32.27#ibcon#read 6, iclass 12, count 0 2006.173.10:22:32.27#ibcon#end of sib2, iclass 12, count 0 2006.173.10:22:32.27#ibcon#*after write, iclass 12, count 0 2006.173.10:22:32.27#ibcon#*before return 0, iclass 12, count 0 2006.173.10:22:32.28#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.10:22:32.28#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.10:22:32.28#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.10:22:32.28#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.10:22:32.28$vck44/vb=5,4 2006.173.10:22:32.28#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.10:22:32.28#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.10:22:32.28#ibcon#ireg 11 cls_cnt 2 2006.173.10:22:32.28#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.10:22:32.33#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.10:22:32.33#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.10:22:32.33#ibcon#enter wrdev, iclass 14, count 2 2006.173.10:22:32.33#ibcon#first serial, iclass 14, count 2 2006.173.10:22:32.33#ibcon#enter sib2, iclass 14, count 2 2006.173.10:22:32.33#ibcon#flushed, iclass 14, count 2 2006.173.10:22:32.33#ibcon#about to write, iclass 14, count 2 2006.173.10:22:32.33#ibcon#wrote, iclass 14, count 2 2006.173.10:22:32.34#ibcon#about to read 3, iclass 14, count 2 2006.173.10:22:32.35#ibcon#read 3, iclass 14, count 2 2006.173.10:22:32.35#ibcon#about to read 4, iclass 14, count 2 2006.173.10:22:32.35#ibcon#read 4, iclass 14, count 2 2006.173.10:22:32.35#ibcon#about to read 5, iclass 14, count 2 2006.173.10:22:32.35#ibcon#read 5, iclass 14, count 2 2006.173.10:22:32.35#ibcon#about to read 6, iclass 14, count 2 2006.173.10:22:32.35#ibcon#read 6, iclass 14, count 2 2006.173.10:22:32.35#ibcon#end of sib2, iclass 14, count 2 2006.173.10:22:32.35#ibcon#*mode == 0, iclass 14, count 2 2006.173.10:22:32.35#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.10:22:32.35#ibcon#[27=AT05-04\r\n] 2006.173.10:22:32.36#ibcon#*before write, iclass 14, count 2 2006.173.10:22:32.36#ibcon#enter sib2, iclass 14, count 2 2006.173.10:22:32.36#ibcon#flushed, iclass 14, count 2 2006.173.10:22:32.36#ibcon#about to write, iclass 14, count 2 2006.173.10:22:32.36#ibcon#wrote, iclass 14, count 2 2006.173.10:22:32.36#ibcon#about to read 3, iclass 14, count 2 2006.173.10:22:32.38#ibcon#read 3, iclass 14, count 2 2006.173.10:22:32.38#ibcon#about to read 4, iclass 14, count 2 2006.173.10:22:32.38#ibcon#read 4, iclass 14, count 2 2006.173.10:22:32.38#ibcon#about to read 5, iclass 14, count 2 2006.173.10:22:32.38#ibcon#read 5, iclass 14, count 2 2006.173.10:22:32.38#ibcon#about to read 6, iclass 14, count 2 2006.173.10:22:32.38#ibcon#read 6, iclass 14, count 2 2006.173.10:22:32.38#ibcon#end of sib2, iclass 14, count 2 2006.173.10:22:32.39#ibcon#*after write, iclass 14, count 2 2006.173.10:22:32.39#ibcon#*before return 0, iclass 14, count 2 2006.173.10:22:32.39#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.10:22:32.39#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.10:22:32.39#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.10:22:32.39#ibcon#ireg 7 cls_cnt 0 2006.173.10:22:32.39#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.10:22:32.50#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.10:22:32.50#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.10:22:32.50#ibcon#enter wrdev, iclass 14, count 0 2006.173.10:22:32.50#ibcon#first serial, iclass 14, count 0 2006.173.10:22:32.50#ibcon#enter sib2, iclass 14, count 0 2006.173.10:22:32.50#ibcon#flushed, iclass 14, count 0 2006.173.10:22:32.50#ibcon#about to write, iclass 14, count 0 2006.173.10:22:32.51#ibcon#wrote, iclass 14, count 0 2006.173.10:22:32.51#ibcon#about to read 3, iclass 14, count 0 2006.173.10:22:32.52#ibcon#read 3, iclass 14, count 0 2006.173.10:22:32.52#ibcon#about to read 4, iclass 14, count 0 2006.173.10:22:32.52#ibcon#read 4, iclass 14, count 0 2006.173.10:22:32.52#ibcon#about to read 5, iclass 14, count 0 2006.173.10:22:32.52#ibcon#read 5, iclass 14, count 0 2006.173.10:22:32.52#ibcon#about to read 6, iclass 14, count 0 2006.173.10:22:32.53#ibcon#read 6, iclass 14, count 0 2006.173.10:22:32.53#ibcon#end of sib2, iclass 14, count 0 2006.173.10:22:32.53#ibcon#*mode == 0, iclass 14, count 0 2006.173.10:22:32.53#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.10:22:32.53#ibcon#[27=USB\r\n] 2006.173.10:22:32.53#ibcon#*before write, iclass 14, count 0 2006.173.10:22:32.53#ibcon#enter sib2, iclass 14, count 0 2006.173.10:22:32.53#ibcon#flushed, iclass 14, count 0 2006.173.10:22:32.53#ibcon#about to write, iclass 14, count 0 2006.173.10:22:32.53#ibcon#wrote, iclass 14, count 0 2006.173.10:22:32.53#ibcon#about to read 3, iclass 14, count 0 2006.173.10:22:32.55#ibcon#read 3, iclass 14, count 0 2006.173.10:22:32.55#ibcon#about to read 4, iclass 14, count 0 2006.173.10:22:32.55#ibcon#read 4, iclass 14, count 0 2006.173.10:22:32.55#ibcon#about to read 5, iclass 14, count 0 2006.173.10:22:32.55#ibcon#read 5, iclass 14, count 0 2006.173.10:22:32.55#ibcon#about to read 6, iclass 14, count 0 2006.173.10:22:32.55#ibcon#read 6, iclass 14, count 0 2006.173.10:22:32.55#ibcon#end of sib2, iclass 14, count 0 2006.173.10:22:32.55#ibcon#*after write, iclass 14, count 0 2006.173.10:22:32.55#ibcon#*before return 0, iclass 14, count 0 2006.173.10:22:32.56#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.10:22:32.56#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.10:22:32.56#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.10:22:32.56#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.10:22:32.56$vck44/vblo=6,719.99 2006.173.10:22:32.56#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.10:22:32.56#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.10:22:32.56#ibcon#ireg 17 cls_cnt 0 2006.173.10:22:32.56#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.10:22:32.56#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.10:22:32.56#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.10:22:32.56#ibcon#enter wrdev, iclass 16, count 0 2006.173.10:22:32.56#ibcon#first serial, iclass 16, count 0 2006.173.10:22:32.56#ibcon#enter sib2, iclass 16, count 0 2006.173.10:22:32.56#ibcon#flushed, iclass 16, count 0 2006.173.10:22:32.56#ibcon#about to write, iclass 16, count 0 2006.173.10:22:32.56#ibcon#wrote, iclass 16, count 0 2006.173.10:22:32.56#ibcon#about to read 3, iclass 16, count 0 2006.173.10:22:32.57#ibcon#read 3, iclass 16, count 0 2006.173.10:22:32.57#ibcon#about to read 4, iclass 16, count 0 2006.173.10:22:32.57#ibcon#read 4, iclass 16, count 0 2006.173.10:22:32.57#ibcon#about to read 5, iclass 16, count 0 2006.173.10:22:32.57#ibcon#read 5, iclass 16, count 0 2006.173.10:22:32.57#ibcon#about to read 6, iclass 16, count 0 2006.173.10:22:32.57#ibcon#read 6, iclass 16, count 0 2006.173.10:22:32.57#ibcon#end of sib2, iclass 16, count 0 2006.173.10:22:32.58#ibcon#*mode == 0, iclass 16, count 0 2006.173.10:22:32.58#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.10:22:32.58#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.10:22:32.58#ibcon#*before write, iclass 16, count 0 2006.173.10:22:32.58#ibcon#enter sib2, iclass 16, count 0 2006.173.10:22:32.58#ibcon#flushed, iclass 16, count 0 2006.173.10:22:32.58#ibcon#about to write, iclass 16, count 0 2006.173.10:22:32.58#ibcon#wrote, iclass 16, count 0 2006.173.10:22:32.58#ibcon#about to read 3, iclass 16, count 0 2006.173.10:22:32.61#ibcon#read 3, iclass 16, count 0 2006.173.10:22:32.61#ibcon#about to read 4, iclass 16, count 0 2006.173.10:22:32.61#ibcon#read 4, iclass 16, count 0 2006.173.10:22:32.61#ibcon#about to read 5, iclass 16, count 0 2006.173.10:22:32.61#ibcon#read 5, iclass 16, count 0 2006.173.10:22:32.61#ibcon#about to read 6, iclass 16, count 0 2006.173.10:22:32.61#ibcon#read 6, iclass 16, count 0 2006.173.10:22:32.62#ibcon#end of sib2, iclass 16, count 0 2006.173.10:22:32.62#ibcon#*after write, iclass 16, count 0 2006.173.10:22:32.62#ibcon#*before return 0, iclass 16, count 0 2006.173.10:22:32.62#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.10:22:32.62#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.10:22:32.62#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.10:22:32.62#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.10:22:32.62$vck44/vb=6,4 2006.173.10:22:32.62#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.10:22:32.62#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.10:22:32.62#ibcon#ireg 11 cls_cnt 2 2006.173.10:22:32.62#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.10:22:32.67#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.10:22:32.67#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.10:22:32.67#ibcon#enter wrdev, iclass 18, count 2 2006.173.10:22:32.67#ibcon#first serial, iclass 18, count 2 2006.173.10:22:32.67#ibcon#enter sib2, iclass 18, count 2 2006.173.10:22:32.67#ibcon#flushed, iclass 18, count 2 2006.173.10:22:32.67#ibcon#about to write, iclass 18, count 2 2006.173.10:22:32.68#ibcon#wrote, iclass 18, count 2 2006.173.10:22:32.68#ibcon#about to read 3, iclass 18, count 2 2006.173.10:22:32.69#ibcon#read 3, iclass 18, count 2 2006.173.10:22:32.69#ibcon#about to read 4, iclass 18, count 2 2006.173.10:22:32.69#ibcon#read 4, iclass 18, count 2 2006.173.10:22:32.69#ibcon#about to read 5, iclass 18, count 2 2006.173.10:22:32.69#ibcon#read 5, iclass 18, count 2 2006.173.10:22:32.69#ibcon#about to read 6, iclass 18, count 2 2006.173.10:22:32.70#ibcon#read 6, iclass 18, count 2 2006.173.10:22:32.70#ibcon#end of sib2, iclass 18, count 2 2006.173.10:22:32.70#ibcon#*mode == 0, iclass 18, count 2 2006.173.10:22:32.70#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.10:22:32.70#ibcon#[27=AT06-04\r\n] 2006.173.10:22:32.70#ibcon#*before write, iclass 18, count 2 2006.173.10:22:32.70#ibcon#enter sib2, iclass 18, count 2 2006.173.10:22:32.70#ibcon#flushed, iclass 18, count 2 2006.173.10:22:32.70#ibcon#about to write, iclass 18, count 2 2006.173.10:22:32.70#ibcon#wrote, iclass 18, count 2 2006.173.10:22:32.70#ibcon#about to read 3, iclass 18, count 2 2006.173.10:22:32.72#ibcon#read 3, iclass 18, count 2 2006.173.10:22:32.72#ibcon#about to read 4, iclass 18, count 2 2006.173.10:22:32.72#ibcon#read 4, iclass 18, count 2 2006.173.10:22:32.72#ibcon#about to read 5, iclass 18, count 2 2006.173.10:22:32.72#ibcon#read 5, iclass 18, count 2 2006.173.10:22:32.72#ibcon#about to read 6, iclass 18, count 2 2006.173.10:22:32.72#ibcon#read 6, iclass 18, count 2 2006.173.10:22:32.73#ibcon#end of sib2, iclass 18, count 2 2006.173.10:22:32.73#ibcon#*after write, iclass 18, count 2 2006.173.10:22:32.73#ibcon#*before return 0, iclass 18, count 2 2006.173.10:22:32.73#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.10:22:32.73#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.10:22:32.73#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.10:22:32.73#ibcon#ireg 7 cls_cnt 0 2006.173.10:22:32.73#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.10:22:32.84#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.10:22:32.84#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.10:22:32.84#ibcon#enter wrdev, iclass 18, count 0 2006.173.10:22:32.84#ibcon#first serial, iclass 18, count 0 2006.173.10:22:32.84#ibcon#enter sib2, iclass 18, count 0 2006.173.10:22:32.84#ibcon#flushed, iclass 18, count 0 2006.173.10:22:32.84#ibcon#about to write, iclass 18, count 0 2006.173.10:22:32.84#ibcon#wrote, iclass 18, count 0 2006.173.10:22:32.85#ibcon#about to read 3, iclass 18, count 0 2006.173.10:22:32.86#ibcon#read 3, iclass 18, count 0 2006.173.10:22:32.86#ibcon#about to read 4, iclass 18, count 0 2006.173.10:22:32.86#ibcon#read 4, iclass 18, count 0 2006.173.10:22:32.86#ibcon#about to read 5, iclass 18, count 0 2006.173.10:22:32.86#ibcon#read 5, iclass 18, count 0 2006.173.10:22:32.86#ibcon#about to read 6, iclass 18, count 0 2006.173.10:22:32.86#ibcon#read 6, iclass 18, count 0 2006.173.10:22:32.87#ibcon#end of sib2, iclass 18, count 0 2006.173.10:22:32.87#ibcon#*mode == 0, iclass 18, count 0 2006.173.10:22:32.87#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.10:22:32.87#ibcon#[27=USB\r\n] 2006.173.10:22:32.87#ibcon#*before write, iclass 18, count 0 2006.173.10:22:32.87#ibcon#enter sib2, iclass 18, count 0 2006.173.10:22:32.87#ibcon#flushed, iclass 18, count 0 2006.173.10:22:32.87#ibcon#about to write, iclass 18, count 0 2006.173.10:22:32.87#ibcon#wrote, iclass 18, count 0 2006.173.10:22:32.87#ibcon#about to read 3, iclass 18, count 0 2006.173.10:22:32.89#ibcon#read 3, iclass 18, count 0 2006.173.10:22:32.89#ibcon#about to read 4, iclass 18, count 0 2006.173.10:22:32.89#ibcon#read 4, iclass 18, count 0 2006.173.10:22:32.89#ibcon#about to read 5, iclass 18, count 0 2006.173.10:22:32.89#ibcon#read 5, iclass 18, count 0 2006.173.10:22:32.89#ibcon#about to read 6, iclass 18, count 0 2006.173.10:22:32.89#ibcon#read 6, iclass 18, count 0 2006.173.10:22:32.89#ibcon#end of sib2, iclass 18, count 0 2006.173.10:22:32.89#ibcon#*after write, iclass 18, count 0 2006.173.10:22:32.89#ibcon#*before return 0, iclass 18, count 0 2006.173.10:22:32.90#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.10:22:32.90#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.10:22:32.90#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.10:22:32.90#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.10:22:32.90$vck44/vblo=7,734.99 2006.173.10:22:32.90#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.10:22:32.90#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.10:22:32.90#ibcon#ireg 17 cls_cnt 0 2006.173.10:22:32.90#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.10:22:32.90#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.10:22:32.90#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.10:22:32.90#ibcon#enter wrdev, iclass 20, count 0 2006.173.10:22:32.90#ibcon#first serial, iclass 20, count 0 2006.173.10:22:32.90#ibcon#enter sib2, iclass 20, count 0 2006.173.10:22:32.90#ibcon#flushed, iclass 20, count 0 2006.173.10:22:32.90#ibcon#about to write, iclass 20, count 0 2006.173.10:22:32.90#ibcon#wrote, iclass 20, count 0 2006.173.10:22:32.90#ibcon#about to read 3, iclass 20, count 0 2006.173.10:22:32.91#ibcon#read 3, iclass 20, count 0 2006.173.10:22:32.91#ibcon#about to read 4, iclass 20, count 0 2006.173.10:22:32.91#ibcon#read 4, iclass 20, count 0 2006.173.10:22:32.91#ibcon#about to read 5, iclass 20, count 0 2006.173.10:22:32.91#ibcon#read 5, iclass 20, count 0 2006.173.10:22:32.91#ibcon#about to read 6, iclass 20, count 0 2006.173.10:22:32.91#ibcon#read 6, iclass 20, count 0 2006.173.10:22:32.91#ibcon#end of sib2, iclass 20, count 0 2006.173.10:22:32.91#ibcon#*mode == 0, iclass 20, count 0 2006.173.10:22:32.92#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.10:22:32.92#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.10:22:32.92#ibcon#*before write, iclass 20, count 0 2006.173.10:22:32.92#ibcon#enter sib2, iclass 20, count 0 2006.173.10:22:32.92#ibcon#flushed, iclass 20, count 0 2006.173.10:22:32.92#ibcon#about to write, iclass 20, count 0 2006.173.10:22:32.92#ibcon#wrote, iclass 20, count 0 2006.173.10:22:32.92#ibcon#about to read 3, iclass 20, count 0 2006.173.10:22:32.95#ibcon#read 3, iclass 20, count 0 2006.173.10:22:32.95#ibcon#about to read 4, iclass 20, count 0 2006.173.10:22:32.95#ibcon#read 4, iclass 20, count 0 2006.173.10:22:32.95#ibcon#about to read 5, iclass 20, count 0 2006.173.10:22:32.95#ibcon#read 5, iclass 20, count 0 2006.173.10:22:32.95#ibcon#about to read 6, iclass 20, count 0 2006.173.10:22:32.95#ibcon#read 6, iclass 20, count 0 2006.173.10:22:32.95#ibcon#end of sib2, iclass 20, count 0 2006.173.10:22:32.95#ibcon#*after write, iclass 20, count 0 2006.173.10:22:32.95#ibcon#*before return 0, iclass 20, count 0 2006.173.10:22:32.96#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.10:22:32.96#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.10:22:32.96#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.10:22:32.96#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.10:22:32.96$vck44/vb=7,4 2006.173.10:22:32.96#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.10:22:32.96#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.10:22:32.96#ibcon#ireg 11 cls_cnt 2 2006.173.10:22:32.96#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.10:22:33.01#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.10:22:33.01#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.10:22:33.01#ibcon#enter wrdev, iclass 22, count 2 2006.173.10:22:33.01#ibcon#first serial, iclass 22, count 2 2006.173.10:22:33.01#ibcon#enter sib2, iclass 22, count 2 2006.173.10:22:33.01#ibcon#flushed, iclass 22, count 2 2006.173.10:22:33.02#ibcon#about to write, iclass 22, count 2 2006.173.10:22:33.02#ibcon#wrote, iclass 22, count 2 2006.173.10:22:33.02#ibcon#about to read 3, iclass 22, count 2 2006.173.10:22:33.03#ibcon#read 3, iclass 22, count 2 2006.173.10:22:33.03#ibcon#about to read 4, iclass 22, count 2 2006.173.10:22:33.03#ibcon#read 4, iclass 22, count 2 2006.173.10:22:33.03#ibcon#about to read 5, iclass 22, count 2 2006.173.10:22:33.03#ibcon#read 5, iclass 22, count 2 2006.173.10:22:33.03#ibcon#about to read 6, iclass 22, count 2 2006.173.10:22:33.03#ibcon#read 6, iclass 22, count 2 2006.173.10:22:33.04#ibcon#end of sib2, iclass 22, count 2 2006.173.10:22:33.04#ibcon#*mode == 0, iclass 22, count 2 2006.173.10:22:33.04#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.10:22:33.04#ibcon#[27=AT07-04\r\n] 2006.173.10:22:33.04#ibcon#*before write, iclass 22, count 2 2006.173.10:22:33.04#ibcon#enter sib2, iclass 22, count 2 2006.173.10:22:33.04#ibcon#flushed, iclass 22, count 2 2006.173.10:22:33.04#ibcon#about to write, iclass 22, count 2 2006.173.10:22:33.04#ibcon#wrote, iclass 22, count 2 2006.173.10:22:33.04#ibcon#about to read 3, iclass 22, count 2 2006.173.10:22:33.06#ibcon#read 3, iclass 22, count 2 2006.173.10:22:33.06#ibcon#about to read 4, iclass 22, count 2 2006.173.10:22:33.06#ibcon#read 4, iclass 22, count 2 2006.173.10:22:33.06#ibcon#about to read 5, iclass 22, count 2 2006.173.10:22:33.06#ibcon#read 5, iclass 22, count 2 2006.173.10:22:33.06#ibcon#about to read 6, iclass 22, count 2 2006.173.10:22:33.06#ibcon#read 6, iclass 22, count 2 2006.173.10:22:33.06#ibcon#end of sib2, iclass 22, count 2 2006.173.10:22:33.06#ibcon#*after write, iclass 22, count 2 2006.173.10:22:33.06#ibcon#*before return 0, iclass 22, count 2 2006.173.10:22:33.07#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.10:22:33.07#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.10:22:33.07#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.10:22:33.07#ibcon#ireg 7 cls_cnt 0 2006.173.10:22:33.07#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.10:22:33.19#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.10:22:33.19#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.10:22:33.19#ibcon#enter wrdev, iclass 22, count 0 2006.173.10:22:33.19#ibcon#first serial, iclass 22, count 0 2006.173.10:22:33.19#ibcon#enter sib2, iclass 22, count 0 2006.173.10:22:33.19#ibcon#flushed, iclass 22, count 0 2006.173.10:22:33.19#ibcon#about to write, iclass 22, count 0 2006.173.10:22:33.19#ibcon#wrote, iclass 22, count 0 2006.173.10:22:33.19#ibcon#about to read 3, iclass 22, count 0 2006.173.10:22:33.20#ibcon#read 3, iclass 22, count 0 2006.173.10:22:33.20#ibcon#about to read 4, iclass 22, count 0 2006.173.10:22:33.20#ibcon#read 4, iclass 22, count 0 2006.173.10:22:33.20#ibcon#about to read 5, iclass 22, count 0 2006.173.10:22:33.20#ibcon#read 5, iclass 22, count 0 2006.173.10:22:33.20#ibcon#about to read 6, iclass 22, count 0 2006.173.10:22:33.20#ibcon#read 6, iclass 22, count 0 2006.173.10:22:33.20#ibcon#end of sib2, iclass 22, count 0 2006.173.10:22:33.20#ibcon#*mode == 0, iclass 22, count 0 2006.173.10:22:33.20#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.10:22:33.20#ibcon#[27=USB\r\n] 2006.173.10:22:33.21#ibcon#*before write, iclass 22, count 0 2006.173.10:22:33.21#ibcon#enter sib2, iclass 22, count 0 2006.173.10:22:33.21#ibcon#flushed, iclass 22, count 0 2006.173.10:22:33.21#ibcon#about to write, iclass 22, count 0 2006.173.10:22:33.21#ibcon#wrote, iclass 22, count 0 2006.173.10:22:33.21#ibcon#about to read 3, iclass 22, count 0 2006.173.10:22:33.23#ibcon#read 3, iclass 22, count 0 2006.173.10:22:33.23#ibcon#about to read 4, iclass 22, count 0 2006.173.10:22:33.23#ibcon#read 4, iclass 22, count 0 2006.173.10:22:33.23#ibcon#about to read 5, iclass 22, count 0 2006.173.10:22:33.23#ibcon#read 5, iclass 22, count 0 2006.173.10:22:33.23#ibcon#about to read 6, iclass 22, count 0 2006.173.10:22:33.23#ibcon#read 6, iclass 22, count 0 2006.173.10:22:33.23#ibcon#end of sib2, iclass 22, count 0 2006.173.10:22:33.23#ibcon#*after write, iclass 22, count 0 2006.173.10:22:33.23#ibcon#*before return 0, iclass 22, count 0 2006.173.10:22:33.23#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.10:22:33.24#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.10:22:33.24#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.10:22:33.24#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.10:22:33.24$vck44/vblo=8,744.99 2006.173.10:22:33.24#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.10:22:33.24#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.10:22:33.24#ibcon#ireg 17 cls_cnt 0 2006.173.10:22:33.24#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.10:22:33.24#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.10:22:33.24#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.10:22:33.24#ibcon#enter wrdev, iclass 24, count 0 2006.173.10:22:33.24#ibcon#first serial, iclass 24, count 0 2006.173.10:22:33.24#ibcon#enter sib2, iclass 24, count 0 2006.173.10:22:33.24#ibcon#flushed, iclass 24, count 0 2006.173.10:22:33.24#ibcon#about to write, iclass 24, count 0 2006.173.10:22:33.24#ibcon#wrote, iclass 24, count 0 2006.173.10:22:33.24#ibcon#about to read 3, iclass 24, count 0 2006.173.10:22:33.25#ibcon#read 3, iclass 24, count 0 2006.173.10:22:33.25#ibcon#about to read 4, iclass 24, count 0 2006.173.10:22:33.25#ibcon#read 4, iclass 24, count 0 2006.173.10:22:33.25#ibcon#about to read 5, iclass 24, count 0 2006.173.10:22:33.25#ibcon#read 5, iclass 24, count 0 2006.173.10:22:33.25#ibcon#about to read 6, iclass 24, count 0 2006.173.10:22:33.25#ibcon#read 6, iclass 24, count 0 2006.173.10:22:33.25#ibcon#end of sib2, iclass 24, count 0 2006.173.10:22:33.25#ibcon#*mode == 0, iclass 24, count 0 2006.173.10:22:33.25#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.10:22:33.25#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.10:22:33.26#ibcon#*before write, iclass 24, count 0 2006.173.10:22:33.26#ibcon#enter sib2, iclass 24, count 0 2006.173.10:22:33.26#ibcon#flushed, iclass 24, count 0 2006.173.10:22:33.26#ibcon#about to write, iclass 24, count 0 2006.173.10:22:33.26#ibcon#wrote, iclass 24, count 0 2006.173.10:22:33.26#ibcon#about to read 3, iclass 24, count 0 2006.173.10:22:33.29#ibcon#read 3, iclass 24, count 0 2006.173.10:22:33.29#ibcon#about to read 4, iclass 24, count 0 2006.173.10:22:33.29#ibcon#read 4, iclass 24, count 0 2006.173.10:22:33.29#ibcon#about to read 5, iclass 24, count 0 2006.173.10:22:33.29#ibcon#read 5, iclass 24, count 0 2006.173.10:22:33.29#ibcon#about to read 6, iclass 24, count 0 2006.173.10:22:33.29#ibcon#read 6, iclass 24, count 0 2006.173.10:22:33.29#ibcon#end of sib2, iclass 24, count 0 2006.173.10:22:33.29#ibcon#*after write, iclass 24, count 0 2006.173.10:22:33.29#ibcon#*before return 0, iclass 24, count 0 2006.173.10:22:33.30#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.10:22:33.30#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.10:22:33.30#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.10:22:33.30#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.10:22:33.30$vck44/vb=8,4 2006.173.10:22:33.30#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.10:22:33.30#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.10:22:33.30#ibcon#ireg 11 cls_cnt 2 2006.173.10:22:33.30#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.10:22:33.34#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.10:22:33.34#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.10:22:33.34#ibcon#enter wrdev, iclass 26, count 2 2006.173.10:22:33.34#ibcon#first serial, iclass 26, count 2 2006.173.10:22:33.34#ibcon#enter sib2, iclass 26, count 2 2006.173.10:22:33.34#ibcon#flushed, iclass 26, count 2 2006.173.10:22:33.34#ibcon#about to write, iclass 26, count 2 2006.173.10:22:33.34#ibcon#wrote, iclass 26, count 2 2006.173.10:22:33.34#ibcon#about to read 3, iclass 26, count 2 2006.173.10:22:33.36#ibcon#read 3, iclass 26, count 2 2006.173.10:22:33.36#ibcon#about to read 4, iclass 26, count 2 2006.173.10:22:33.36#ibcon#read 4, iclass 26, count 2 2006.173.10:22:33.36#ibcon#about to read 5, iclass 26, count 2 2006.173.10:22:33.36#ibcon#read 5, iclass 26, count 2 2006.173.10:22:33.36#ibcon#about to read 6, iclass 26, count 2 2006.173.10:22:33.36#ibcon#read 6, iclass 26, count 2 2006.173.10:22:33.36#ibcon#end of sib2, iclass 26, count 2 2006.173.10:22:33.36#ibcon#*mode == 0, iclass 26, count 2 2006.173.10:22:33.36#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.10:22:33.36#ibcon#[27=AT08-04\r\n] 2006.173.10:22:33.36#ibcon#*before write, iclass 26, count 2 2006.173.10:22:33.37#ibcon#enter sib2, iclass 26, count 2 2006.173.10:22:33.37#ibcon#flushed, iclass 26, count 2 2006.173.10:22:33.37#ibcon#about to write, iclass 26, count 2 2006.173.10:22:33.37#ibcon#wrote, iclass 26, count 2 2006.173.10:22:33.37#ibcon#about to read 3, iclass 26, count 2 2006.173.10:22:33.39#ibcon#read 3, iclass 26, count 2 2006.173.10:22:33.39#ibcon#about to read 4, iclass 26, count 2 2006.173.10:22:33.39#ibcon#read 4, iclass 26, count 2 2006.173.10:22:33.39#ibcon#about to read 5, iclass 26, count 2 2006.173.10:22:33.39#ibcon#read 5, iclass 26, count 2 2006.173.10:22:33.39#ibcon#about to read 6, iclass 26, count 2 2006.173.10:22:33.39#ibcon#read 6, iclass 26, count 2 2006.173.10:22:33.39#ibcon#end of sib2, iclass 26, count 2 2006.173.10:22:33.40#ibcon#*after write, iclass 26, count 2 2006.173.10:22:33.40#ibcon#*before return 0, iclass 26, count 2 2006.173.10:22:33.40#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.10:22:33.40#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.10:22:33.40#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.10:22:33.40#ibcon#ireg 7 cls_cnt 0 2006.173.10:22:33.40#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.10:22:33.51#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.10:22:33.51#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.10:22:33.51#ibcon#enter wrdev, iclass 26, count 0 2006.173.10:22:33.51#ibcon#first serial, iclass 26, count 0 2006.173.10:22:33.51#ibcon#enter sib2, iclass 26, count 0 2006.173.10:22:33.51#ibcon#flushed, iclass 26, count 0 2006.173.10:22:33.51#ibcon#about to write, iclass 26, count 0 2006.173.10:22:33.52#ibcon#wrote, iclass 26, count 0 2006.173.10:22:33.52#ibcon#about to read 3, iclass 26, count 0 2006.173.10:22:33.53#ibcon#read 3, iclass 26, count 0 2006.173.10:22:33.53#ibcon#about to read 4, iclass 26, count 0 2006.173.10:22:33.53#ibcon#read 4, iclass 26, count 0 2006.173.10:22:33.53#ibcon#about to read 5, iclass 26, count 0 2006.173.10:22:33.53#ibcon#read 5, iclass 26, count 0 2006.173.10:22:33.53#ibcon#about to read 6, iclass 26, count 0 2006.173.10:22:33.53#ibcon#read 6, iclass 26, count 0 2006.173.10:22:33.53#ibcon#end of sib2, iclass 26, count 0 2006.173.10:22:33.53#ibcon#*mode == 0, iclass 26, count 0 2006.173.10:22:33.53#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.10:22:33.53#ibcon#[27=USB\r\n] 2006.173.10:22:33.53#ibcon#*before write, iclass 26, count 0 2006.173.10:22:33.54#ibcon#enter sib2, iclass 26, count 0 2006.173.10:22:33.54#ibcon#flushed, iclass 26, count 0 2006.173.10:22:33.54#ibcon#about to write, iclass 26, count 0 2006.173.10:22:33.54#ibcon#wrote, iclass 26, count 0 2006.173.10:22:33.54#ibcon#about to read 3, iclass 26, count 0 2006.173.10:22:33.56#ibcon#read 3, iclass 26, count 0 2006.173.10:22:33.56#ibcon#about to read 4, iclass 26, count 0 2006.173.10:22:33.56#ibcon#read 4, iclass 26, count 0 2006.173.10:22:33.56#ibcon#about to read 5, iclass 26, count 0 2006.173.10:22:33.56#ibcon#read 5, iclass 26, count 0 2006.173.10:22:33.56#ibcon#about to read 6, iclass 26, count 0 2006.173.10:22:33.56#ibcon#read 6, iclass 26, count 0 2006.173.10:22:33.56#ibcon#end of sib2, iclass 26, count 0 2006.173.10:22:33.56#ibcon#*after write, iclass 26, count 0 2006.173.10:22:33.56#ibcon#*before return 0, iclass 26, count 0 2006.173.10:22:33.56#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.10:22:33.56#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.10:22:33.57#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.10:22:33.57#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.10:22:33.57$vck44/vabw=wide 2006.173.10:22:33.57#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.10:22:33.57#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.10:22:33.57#ibcon#ireg 8 cls_cnt 0 2006.173.10:22:33.57#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.10:22:33.57#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.10:22:33.57#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.10:22:33.57#ibcon#enter wrdev, iclass 28, count 0 2006.173.10:22:33.57#ibcon#first serial, iclass 28, count 0 2006.173.10:22:33.57#ibcon#enter sib2, iclass 28, count 0 2006.173.10:22:33.57#ibcon#flushed, iclass 28, count 0 2006.173.10:22:33.57#ibcon#about to write, iclass 28, count 0 2006.173.10:22:33.57#ibcon#wrote, iclass 28, count 0 2006.173.10:22:33.57#ibcon#about to read 3, iclass 28, count 0 2006.173.10:22:33.58#ibcon#read 3, iclass 28, count 0 2006.173.10:22:33.58#ibcon#about to read 4, iclass 28, count 0 2006.173.10:22:33.58#ibcon#read 4, iclass 28, count 0 2006.173.10:22:33.58#ibcon#about to read 5, iclass 28, count 0 2006.173.10:22:33.58#ibcon#read 5, iclass 28, count 0 2006.173.10:22:33.58#ibcon#about to read 6, iclass 28, count 0 2006.173.10:22:33.58#ibcon#read 6, iclass 28, count 0 2006.173.10:22:33.58#ibcon#end of sib2, iclass 28, count 0 2006.173.10:22:33.58#ibcon#*mode == 0, iclass 28, count 0 2006.173.10:22:33.58#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.10:22:33.58#ibcon#[25=BW32\r\n] 2006.173.10:22:33.58#ibcon#*before write, iclass 28, count 0 2006.173.10:22:33.59#ibcon#enter sib2, iclass 28, count 0 2006.173.10:22:33.59#ibcon#flushed, iclass 28, count 0 2006.173.10:22:33.59#ibcon#about to write, iclass 28, count 0 2006.173.10:22:33.59#ibcon#wrote, iclass 28, count 0 2006.173.10:22:33.59#ibcon#about to read 3, iclass 28, count 0 2006.173.10:22:33.61#ibcon#read 3, iclass 28, count 0 2006.173.10:22:33.61#ibcon#about to read 4, iclass 28, count 0 2006.173.10:22:33.61#ibcon#read 4, iclass 28, count 0 2006.173.10:22:33.61#ibcon#about to read 5, iclass 28, count 0 2006.173.10:22:33.61#ibcon#read 5, iclass 28, count 0 2006.173.10:22:33.61#ibcon#about to read 6, iclass 28, count 0 2006.173.10:22:33.61#ibcon#read 6, iclass 28, count 0 2006.173.10:22:33.61#ibcon#end of sib2, iclass 28, count 0 2006.173.10:22:33.62#ibcon#*after write, iclass 28, count 0 2006.173.10:22:33.62#ibcon#*before return 0, iclass 28, count 0 2006.173.10:22:33.62#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.10:22:33.62#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.10:22:33.62#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.10:22:33.62#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.10:22:33.62$vck44/vbbw=wide 2006.173.10:22:33.62#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.10:22:33.62#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.10:22:33.62#ibcon#ireg 8 cls_cnt 0 2006.173.10:22:33.62#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.10:22:33.67#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.10:22:33.67#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.10:22:33.67#ibcon#enter wrdev, iclass 30, count 0 2006.173.10:22:33.67#ibcon#first serial, iclass 30, count 0 2006.173.10:22:33.67#ibcon#enter sib2, iclass 30, count 0 2006.173.10:22:33.67#ibcon#flushed, iclass 30, count 0 2006.173.10:22:33.67#ibcon#about to write, iclass 30, count 0 2006.173.10:22:33.67#ibcon#wrote, iclass 30, count 0 2006.173.10:22:33.67#ibcon#about to read 3, iclass 30, count 0 2006.173.10:22:33.69#ibcon#read 3, iclass 30, count 0 2006.173.10:22:33.69#ibcon#about to read 4, iclass 30, count 0 2006.173.10:22:33.69#ibcon#read 4, iclass 30, count 0 2006.173.10:22:33.69#ibcon#about to read 5, iclass 30, count 0 2006.173.10:22:33.69#ibcon#read 5, iclass 30, count 0 2006.173.10:22:33.69#ibcon#about to read 6, iclass 30, count 0 2006.173.10:22:33.69#ibcon#read 6, iclass 30, count 0 2006.173.10:22:33.69#ibcon#end of sib2, iclass 30, count 0 2006.173.10:22:33.70#ibcon#*mode == 0, iclass 30, count 0 2006.173.10:22:33.70#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.10:22:33.70#ibcon#[27=BW32\r\n] 2006.173.10:22:33.70#ibcon#*before write, iclass 30, count 0 2006.173.10:22:33.70#ibcon#enter sib2, iclass 30, count 0 2006.173.10:22:33.70#ibcon#flushed, iclass 30, count 0 2006.173.10:22:33.70#ibcon#about to write, iclass 30, count 0 2006.173.10:22:33.70#ibcon#wrote, iclass 30, count 0 2006.173.10:22:33.70#ibcon#about to read 3, iclass 30, count 0 2006.173.10:22:33.72#ibcon#read 3, iclass 30, count 0 2006.173.10:22:33.72#ibcon#about to read 4, iclass 30, count 0 2006.173.10:22:33.72#ibcon#read 4, iclass 30, count 0 2006.173.10:22:33.72#ibcon#about to read 5, iclass 30, count 0 2006.173.10:22:33.72#ibcon#read 5, iclass 30, count 0 2006.173.10:22:33.72#ibcon#about to read 6, iclass 30, count 0 2006.173.10:22:33.73#ibcon#read 6, iclass 30, count 0 2006.173.10:22:33.73#ibcon#end of sib2, iclass 30, count 0 2006.173.10:22:33.73#ibcon#*after write, iclass 30, count 0 2006.173.10:22:33.73#ibcon#*before return 0, iclass 30, count 0 2006.173.10:22:33.73#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.10:22:33.73#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.10:22:33.73#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.10:22:33.73#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.10:22:33.73$setupk4/ifdk4 2006.173.10:22:33.73$ifdk4/lo= 2006.173.10:22:33.73$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.10:22:33.73$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.10:22:33.73$ifdk4/patch= 2006.173.10:22:33.73$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.10:22:33.73$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.10:22:33.73$setupk4/!*+20s 2006.173.10:22:33.94#abcon#<5=/04 0.6 1.4 22.72 901004.3\r\n> 2006.173.10:22:33.96#abcon#{5=INTERFACE CLEAR} 2006.173.10:22:34.02#abcon#[5=S1D000X0/0*\r\n] 2006.173.10:22:44.11#abcon#<5=/04 0.6 1.4 22.71 901004.3\r\n> 2006.173.10:22:44.13#abcon#{5=INTERFACE CLEAR} 2006.173.10:22:44.19#abcon#[5=S1D000X0/0*\r\n] 2006.173.10:22:48.27$setupk4/"tpicd 2006.173.10:22:48.27$setupk4/echo=off 2006.173.10:22:48.28$setupk4/xlog=off 2006.173.10:22:48.28:!2006.173.10:25:23 2006.173.10:24:11.13#trakl#Source acquired 2006.173.10:24:11.14#flagr#flagr/antenna,acquired 2006.173.10:25:23.01:preob 2006.173.10:25:24.13/onsource/TRACKING 2006.173.10:25:24.13:!2006.173.10:25:33 2006.173.10:25:33.01:"tape 2006.173.10:25:33.01:"st=record 2006.173.10:25:33.01:data_valid=on 2006.173.10:25:33.02:midob 2006.173.10:25:34.14/onsource/TRACKING 2006.173.10:25:34.15/wx/22.67,1004.4,90 2006.173.10:25:34.27/cable/+6.5015E-03 2006.173.10:25:35.36/va/01,07,usb,yes,34,37 2006.173.10:25:35.36/va/02,06,usb,yes,34,34 2006.173.10:25:35.36/va/03,05,usb,yes,43,45 2006.173.10:25:35.36/va/04,06,usb,yes,34,36 2006.173.10:25:35.36/va/05,04,usb,yes,27,27 2006.173.10:25:35.36/va/06,03,usb,yes,38,38 2006.173.10:25:35.36/va/07,04,usb,yes,31,32 2006.173.10:25:35.36/va/08,04,usb,yes,26,31 2006.173.10:25:35.59/valo/01,524.99,yes,locked 2006.173.10:25:35.59/valo/02,534.99,yes,locked 2006.173.10:25:35.59/valo/03,564.99,yes,locked 2006.173.10:25:35.59/valo/04,624.99,yes,locked 2006.173.10:25:35.59/valo/05,734.99,yes,locked 2006.173.10:25:35.59/valo/06,814.99,yes,locked 2006.173.10:25:35.59/valo/07,864.99,yes,locked 2006.173.10:25:35.59/valo/08,884.99,yes,locked 2006.173.10:25:36.68/vb/01,04,usb,yes,29,27 2006.173.10:25:36.68/vb/02,04,usb,yes,31,31 2006.173.10:25:36.68/vb/03,04,usb,yes,28,31 2006.173.10:25:36.68/vb/04,04,usb,yes,32,31 2006.173.10:25:36.68/vb/05,04,usb,yes,25,27 2006.173.10:25:36.68/vb/06,04,usb,yes,29,26 2006.173.10:25:36.68/vb/07,04,usb,yes,29,29 2006.173.10:25:36.68/vb/08,04,usb,yes,27,30 2006.173.10:25:36.92/vblo/01,629.99,yes,locked 2006.173.10:25:36.92/vblo/02,634.99,yes,locked 2006.173.10:25:36.92/vblo/03,649.99,yes,locked 2006.173.10:25:36.92/vblo/04,679.99,yes,locked 2006.173.10:25:36.92/vblo/05,709.99,yes,locked 2006.173.10:25:36.92/vblo/06,719.99,yes,locked 2006.173.10:25:36.92/vblo/07,734.99,yes,locked 2006.173.10:25:36.92/vblo/08,744.99,yes,locked 2006.173.10:25:37.07/vabw/8 2006.173.10:25:37.22/vbbw/8 2006.173.10:25:37.31/xfe/off,on,15.2 2006.173.10:25:37.68/ifatt/23,28,28,28 2006.173.10:25:38.07/fmout-gps/S +4.01E-07 2006.173.10:25:38.12:!2006.173.10:32:23 2006.173.10:32:23.00:data_valid=off 2006.173.10:32:23.01:"et 2006.173.10:32:23.01:!+3s 2006.173.10:32:26.02:"tape 2006.173.10:32:26.03:postob 2006.173.10:32:26.13/cable/+6.5026E-03 2006.173.10:32:26.14/wx/22.59,1004.0,90 2006.173.10:32:26.19/fmout-gps/S +4.01E-07 2006.173.10:32:26.20:scan_name=173-1038,jd0606,410 2006.173.10:32:26.20:source=0059+581,010245.76,582411.1,2000.0,neutral 2006.173.10:32:28.13#flagr#flagr/antenna,new-source 2006.173.10:32:28.14:checkk5 2006.173.10:32:28.54/chk_autoobs//k5ts1/ autoobs is running! 2006.173.10:32:28.94/chk_autoobs//k5ts2/ autoobs is running! 2006.173.10:32:29.35/chk_autoobs//k5ts3/ autoobs is running! 2006.173.10:32:29.75/chk_autoobs//k5ts4/ autoobs is running! 2006.173.10:32:30.15/chk_obsdata//k5ts1/T1731025??a.dat file size is correct (nominal:1640MB, actual:1636MB). 2006.173.10:32:30.54/chk_obsdata//k5ts2/T1731025??b.dat file size is correct (nominal:1640MB, actual:1636MB). 2006.173.10:32:30.94/chk_obsdata//k5ts3/T1731025??c.dat file size is correct (nominal:1640MB, actual:1636MB). 2006.173.10:32:31.34/chk_obsdata//k5ts4/T1731025??d.dat file size is correct (nominal:1640MB, actual:1636MB). 2006.173.10:32:32.06/k5log//k5ts1_log_newline 2006.173.10:32:32.78/k5log//k5ts2_log_newline 2006.173.10:32:33.49/k5log//k5ts3_log_newline 2006.173.10:32:34.20/k5log//k5ts4_log_newline 2006.173.10:32:34.22/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.10:32:34.22:setupk4=1 2006.173.10:32:34.22$setupk4/echo=on 2006.173.10:32:34.22$setupk4/pcalon 2006.173.10:32:34.22$pcalon/"no phase cal control is implemented here 2006.173.10:32:34.22$setupk4/"tpicd=stop 2006.173.10:32:34.22$setupk4/"rec=synch_on 2006.173.10:32:34.22$setupk4/"rec_mode=128 2006.173.10:32:34.22$setupk4/!* 2006.173.10:32:34.22$setupk4/recpk4 2006.173.10:32:34.22$recpk4/recpatch= 2006.173.10:32:34.23$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.10:32:34.23$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.10:32:34.23$setupk4/vck44 2006.173.10:32:34.23$vck44/valo=1,524.99 2006.173.10:32:34.23#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.10:32:34.23#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.10:32:34.23#ibcon#ireg 17 cls_cnt 0 2006.173.10:32:34.23#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.10:32:34.23#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.10:32:34.23#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.10:32:34.23#ibcon#enter wrdev, iclass 23, count 0 2006.173.10:32:34.23#ibcon#first serial, iclass 23, count 0 2006.173.10:32:34.23#ibcon#enter sib2, iclass 23, count 0 2006.173.10:32:34.23#ibcon#flushed, iclass 23, count 0 2006.173.10:32:34.23#ibcon#about to write, iclass 23, count 0 2006.173.10:32:34.23#ibcon#wrote, iclass 23, count 0 2006.173.10:32:34.23#ibcon#about to read 3, iclass 23, count 0 2006.173.10:32:34.24#ibcon#read 3, iclass 23, count 0 2006.173.10:32:34.24#ibcon#about to read 4, iclass 23, count 0 2006.173.10:32:34.24#ibcon#read 4, iclass 23, count 0 2006.173.10:32:34.24#ibcon#about to read 5, iclass 23, count 0 2006.173.10:32:34.24#ibcon#read 5, iclass 23, count 0 2006.173.10:32:34.24#ibcon#about to read 6, iclass 23, count 0 2006.173.10:32:34.24#ibcon#read 6, iclass 23, count 0 2006.173.10:32:34.24#ibcon#end of sib2, iclass 23, count 0 2006.173.10:32:34.24#ibcon#*mode == 0, iclass 23, count 0 2006.173.10:32:34.24#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.10:32:34.24#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.10:32:34.24#ibcon#*before write, iclass 23, count 0 2006.173.10:32:34.24#ibcon#enter sib2, iclass 23, count 0 2006.173.10:32:34.24#ibcon#flushed, iclass 23, count 0 2006.173.10:32:34.24#ibcon#about to write, iclass 23, count 0 2006.173.10:32:34.24#ibcon#wrote, iclass 23, count 0 2006.173.10:32:34.24#ibcon#about to read 3, iclass 23, count 0 2006.173.10:32:34.29#ibcon#read 3, iclass 23, count 0 2006.173.10:32:34.29#ibcon#about to read 4, iclass 23, count 0 2006.173.10:32:34.29#ibcon#read 4, iclass 23, count 0 2006.173.10:32:34.29#ibcon#about to read 5, iclass 23, count 0 2006.173.10:32:34.29#ibcon#read 5, iclass 23, count 0 2006.173.10:32:34.29#ibcon#about to read 6, iclass 23, count 0 2006.173.10:32:34.29#ibcon#read 6, iclass 23, count 0 2006.173.10:32:34.29#ibcon#end of sib2, iclass 23, count 0 2006.173.10:32:34.29#ibcon#*after write, iclass 23, count 0 2006.173.10:32:34.29#ibcon#*before return 0, iclass 23, count 0 2006.173.10:32:34.29#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.10:32:34.29#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.10:32:34.29#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.10:32:34.29#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.10:32:34.29$vck44/va=1,7 2006.173.10:32:34.29#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.10:32:34.29#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.10:32:34.29#ibcon#ireg 11 cls_cnt 2 2006.173.10:32:34.29#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.10:32:34.29#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.10:32:34.29#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.10:32:34.29#ibcon#enter wrdev, iclass 25, count 2 2006.173.10:32:34.29#ibcon#first serial, iclass 25, count 2 2006.173.10:32:34.29#ibcon#enter sib2, iclass 25, count 2 2006.173.10:32:34.29#ibcon#flushed, iclass 25, count 2 2006.173.10:32:34.29#ibcon#about to write, iclass 25, count 2 2006.173.10:32:34.29#ibcon#wrote, iclass 25, count 2 2006.173.10:32:34.29#ibcon#about to read 3, iclass 25, count 2 2006.173.10:32:34.31#ibcon#read 3, iclass 25, count 2 2006.173.10:32:34.31#ibcon#about to read 4, iclass 25, count 2 2006.173.10:32:34.31#ibcon#read 4, iclass 25, count 2 2006.173.10:32:34.31#ibcon#about to read 5, iclass 25, count 2 2006.173.10:32:34.31#ibcon#read 5, iclass 25, count 2 2006.173.10:32:34.31#ibcon#about to read 6, iclass 25, count 2 2006.173.10:32:34.31#ibcon#read 6, iclass 25, count 2 2006.173.10:32:34.31#ibcon#end of sib2, iclass 25, count 2 2006.173.10:32:34.31#ibcon#*mode == 0, iclass 25, count 2 2006.173.10:32:34.31#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.10:32:34.31#ibcon#[25=AT01-07\r\n] 2006.173.10:32:34.31#ibcon#*before write, iclass 25, count 2 2006.173.10:32:34.31#ibcon#enter sib2, iclass 25, count 2 2006.173.10:32:34.31#ibcon#flushed, iclass 25, count 2 2006.173.10:32:34.31#ibcon#about to write, iclass 25, count 2 2006.173.10:32:34.31#ibcon#wrote, iclass 25, count 2 2006.173.10:32:34.31#ibcon#about to read 3, iclass 25, count 2 2006.173.10:32:34.34#ibcon#read 3, iclass 25, count 2 2006.173.10:32:34.34#ibcon#about to read 4, iclass 25, count 2 2006.173.10:32:34.34#ibcon#read 4, iclass 25, count 2 2006.173.10:32:34.34#ibcon#about to read 5, iclass 25, count 2 2006.173.10:32:34.34#ibcon#read 5, iclass 25, count 2 2006.173.10:32:34.34#ibcon#about to read 6, iclass 25, count 2 2006.173.10:32:34.34#ibcon#read 6, iclass 25, count 2 2006.173.10:32:34.34#ibcon#end of sib2, iclass 25, count 2 2006.173.10:32:34.34#ibcon#*after write, iclass 25, count 2 2006.173.10:32:34.34#ibcon#*before return 0, iclass 25, count 2 2006.173.10:32:34.34#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.10:32:34.34#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.10:32:34.34#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.10:32:34.34#ibcon#ireg 7 cls_cnt 0 2006.173.10:32:34.34#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.10:32:34.46#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.10:32:34.46#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.10:32:34.46#ibcon#enter wrdev, iclass 25, count 0 2006.173.10:32:34.46#ibcon#first serial, iclass 25, count 0 2006.173.10:32:34.46#ibcon#enter sib2, iclass 25, count 0 2006.173.10:32:34.46#ibcon#flushed, iclass 25, count 0 2006.173.10:32:34.46#ibcon#about to write, iclass 25, count 0 2006.173.10:32:34.46#ibcon#wrote, iclass 25, count 0 2006.173.10:32:34.46#ibcon#about to read 3, iclass 25, count 0 2006.173.10:32:34.48#ibcon#read 3, iclass 25, count 0 2006.173.10:32:34.48#ibcon#about to read 4, iclass 25, count 0 2006.173.10:32:34.48#ibcon#read 4, iclass 25, count 0 2006.173.10:32:34.48#ibcon#about to read 5, iclass 25, count 0 2006.173.10:32:34.48#ibcon#read 5, iclass 25, count 0 2006.173.10:32:34.48#ibcon#about to read 6, iclass 25, count 0 2006.173.10:32:34.48#ibcon#read 6, iclass 25, count 0 2006.173.10:32:34.48#ibcon#end of sib2, iclass 25, count 0 2006.173.10:32:34.48#ibcon#*mode == 0, iclass 25, count 0 2006.173.10:32:34.48#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.10:32:34.48#ibcon#[25=USB\r\n] 2006.173.10:32:34.48#ibcon#*before write, iclass 25, count 0 2006.173.10:32:34.48#ibcon#enter sib2, iclass 25, count 0 2006.173.10:32:34.48#ibcon#flushed, iclass 25, count 0 2006.173.10:32:34.48#ibcon#about to write, iclass 25, count 0 2006.173.10:32:34.48#ibcon#wrote, iclass 25, count 0 2006.173.10:32:34.48#ibcon#about to read 3, iclass 25, count 0 2006.173.10:32:34.51#ibcon#read 3, iclass 25, count 0 2006.173.10:32:34.51#ibcon#about to read 4, iclass 25, count 0 2006.173.10:32:34.51#ibcon#read 4, iclass 25, count 0 2006.173.10:32:34.51#ibcon#about to read 5, iclass 25, count 0 2006.173.10:32:34.51#ibcon#read 5, iclass 25, count 0 2006.173.10:32:34.51#ibcon#about to read 6, iclass 25, count 0 2006.173.10:32:34.51#ibcon#read 6, iclass 25, count 0 2006.173.10:32:34.51#ibcon#end of sib2, iclass 25, count 0 2006.173.10:32:34.51#ibcon#*after write, iclass 25, count 0 2006.173.10:32:34.51#ibcon#*before return 0, iclass 25, count 0 2006.173.10:32:34.51#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.10:32:34.51#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.10:32:34.51#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.10:32:34.51#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.10:32:34.51$vck44/valo=2,534.99 2006.173.10:32:34.51#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.10:32:34.51#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.10:32:34.51#ibcon#ireg 17 cls_cnt 0 2006.173.10:32:34.51#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.10:32:34.51#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.10:32:34.51#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.10:32:34.51#ibcon#enter wrdev, iclass 27, count 0 2006.173.10:32:34.51#ibcon#first serial, iclass 27, count 0 2006.173.10:32:34.51#ibcon#enter sib2, iclass 27, count 0 2006.173.10:32:34.51#ibcon#flushed, iclass 27, count 0 2006.173.10:32:34.51#ibcon#about to write, iclass 27, count 0 2006.173.10:32:34.51#ibcon#wrote, iclass 27, count 0 2006.173.10:32:34.51#ibcon#about to read 3, iclass 27, count 0 2006.173.10:32:34.53#ibcon#read 3, iclass 27, count 0 2006.173.10:32:34.53#ibcon#about to read 4, iclass 27, count 0 2006.173.10:32:34.53#ibcon#read 4, iclass 27, count 0 2006.173.10:32:34.53#ibcon#about to read 5, iclass 27, count 0 2006.173.10:32:34.53#ibcon#read 5, iclass 27, count 0 2006.173.10:32:34.53#ibcon#about to read 6, iclass 27, count 0 2006.173.10:32:34.53#ibcon#read 6, iclass 27, count 0 2006.173.10:32:34.53#ibcon#end of sib2, iclass 27, count 0 2006.173.10:32:34.53#ibcon#*mode == 0, iclass 27, count 0 2006.173.10:32:34.53#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.10:32:34.53#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.10:32:34.53#ibcon#*before write, iclass 27, count 0 2006.173.10:32:34.53#ibcon#enter sib2, iclass 27, count 0 2006.173.10:32:34.53#ibcon#flushed, iclass 27, count 0 2006.173.10:32:34.53#ibcon#about to write, iclass 27, count 0 2006.173.10:32:34.53#ibcon#wrote, iclass 27, count 0 2006.173.10:32:34.53#ibcon#about to read 3, iclass 27, count 0 2006.173.10:32:34.57#ibcon#read 3, iclass 27, count 0 2006.173.10:32:34.57#ibcon#about to read 4, iclass 27, count 0 2006.173.10:32:34.57#ibcon#read 4, iclass 27, count 0 2006.173.10:32:34.57#ibcon#about to read 5, iclass 27, count 0 2006.173.10:32:34.57#ibcon#read 5, iclass 27, count 0 2006.173.10:32:34.57#ibcon#about to read 6, iclass 27, count 0 2006.173.10:32:34.57#ibcon#read 6, iclass 27, count 0 2006.173.10:32:34.57#ibcon#end of sib2, iclass 27, count 0 2006.173.10:32:34.57#ibcon#*after write, iclass 27, count 0 2006.173.10:32:34.57#ibcon#*before return 0, iclass 27, count 0 2006.173.10:32:34.57#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.10:32:34.57#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.10:32:34.57#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.10:32:34.57#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.10:32:34.57$vck44/va=2,6 2006.173.10:32:34.57#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.10:32:34.57#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.10:32:34.57#ibcon#ireg 11 cls_cnt 2 2006.173.10:32:34.57#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.10:32:34.63#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.10:32:34.63#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.10:32:34.63#ibcon#enter wrdev, iclass 29, count 2 2006.173.10:32:34.63#ibcon#first serial, iclass 29, count 2 2006.173.10:32:34.63#ibcon#enter sib2, iclass 29, count 2 2006.173.10:32:34.63#ibcon#flushed, iclass 29, count 2 2006.173.10:32:34.63#ibcon#about to write, iclass 29, count 2 2006.173.10:32:34.63#ibcon#wrote, iclass 29, count 2 2006.173.10:32:34.63#ibcon#about to read 3, iclass 29, count 2 2006.173.10:32:34.65#ibcon#read 3, iclass 29, count 2 2006.173.10:32:34.65#ibcon#about to read 4, iclass 29, count 2 2006.173.10:32:34.65#ibcon#read 4, iclass 29, count 2 2006.173.10:32:34.65#ibcon#about to read 5, iclass 29, count 2 2006.173.10:32:34.65#ibcon#read 5, iclass 29, count 2 2006.173.10:32:34.65#ibcon#about to read 6, iclass 29, count 2 2006.173.10:32:34.65#ibcon#read 6, iclass 29, count 2 2006.173.10:32:34.65#ibcon#end of sib2, iclass 29, count 2 2006.173.10:32:34.65#ibcon#*mode == 0, iclass 29, count 2 2006.173.10:32:34.65#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.10:32:34.65#ibcon#[25=AT02-06\r\n] 2006.173.10:32:34.65#ibcon#*before write, iclass 29, count 2 2006.173.10:32:34.65#ibcon#enter sib2, iclass 29, count 2 2006.173.10:32:34.65#ibcon#flushed, iclass 29, count 2 2006.173.10:32:34.65#ibcon#about to write, iclass 29, count 2 2006.173.10:32:34.65#ibcon#wrote, iclass 29, count 2 2006.173.10:32:34.65#ibcon#about to read 3, iclass 29, count 2 2006.173.10:32:34.68#ibcon#read 3, iclass 29, count 2 2006.173.10:32:34.68#ibcon#about to read 4, iclass 29, count 2 2006.173.10:32:34.68#ibcon#read 4, iclass 29, count 2 2006.173.10:32:34.68#ibcon#about to read 5, iclass 29, count 2 2006.173.10:32:34.68#ibcon#read 5, iclass 29, count 2 2006.173.10:32:34.68#ibcon#about to read 6, iclass 29, count 2 2006.173.10:32:34.68#ibcon#read 6, iclass 29, count 2 2006.173.10:32:34.68#ibcon#end of sib2, iclass 29, count 2 2006.173.10:32:34.68#ibcon#*after write, iclass 29, count 2 2006.173.10:32:34.68#ibcon#*before return 0, iclass 29, count 2 2006.173.10:32:34.68#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.10:32:34.68#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.10:32:34.68#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.10:32:34.68#ibcon#ireg 7 cls_cnt 0 2006.173.10:32:34.68#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.10:32:34.80#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.10:32:34.80#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.10:32:34.80#ibcon#enter wrdev, iclass 29, count 0 2006.173.10:32:34.80#ibcon#first serial, iclass 29, count 0 2006.173.10:32:34.80#ibcon#enter sib2, iclass 29, count 0 2006.173.10:32:34.80#ibcon#flushed, iclass 29, count 0 2006.173.10:32:34.80#ibcon#about to write, iclass 29, count 0 2006.173.10:32:34.80#ibcon#wrote, iclass 29, count 0 2006.173.10:32:34.80#ibcon#about to read 3, iclass 29, count 0 2006.173.10:32:34.82#ibcon#read 3, iclass 29, count 0 2006.173.10:32:34.82#ibcon#about to read 4, iclass 29, count 0 2006.173.10:32:34.82#ibcon#read 4, iclass 29, count 0 2006.173.10:32:34.82#ibcon#about to read 5, iclass 29, count 0 2006.173.10:32:34.82#ibcon#read 5, iclass 29, count 0 2006.173.10:32:34.82#ibcon#about to read 6, iclass 29, count 0 2006.173.10:32:34.82#ibcon#read 6, iclass 29, count 0 2006.173.10:32:34.82#ibcon#end of sib2, iclass 29, count 0 2006.173.10:32:34.82#ibcon#*mode == 0, iclass 29, count 0 2006.173.10:32:34.82#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.10:32:34.82#ibcon#[25=USB\r\n] 2006.173.10:32:34.82#ibcon#*before write, iclass 29, count 0 2006.173.10:32:34.82#ibcon#enter sib2, iclass 29, count 0 2006.173.10:32:34.82#ibcon#flushed, iclass 29, count 0 2006.173.10:32:34.82#ibcon#about to write, iclass 29, count 0 2006.173.10:32:34.82#ibcon#wrote, iclass 29, count 0 2006.173.10:32:34.82#ibcon#about to read 3, iclass 29, count 0 2006.173.10:32:34.85#ibcon#read 3, iclass 29, count 0 2006.173.10:32:34.85#ibcon#about to read 4, iclass 29, count 0 2006.173.10:32:34.85#ibcon#read 4, iclass 29, count 0 2006.173.10:32:34.85#ibcon#about to read 5, iclass 29, count 0 2006.173.10:32:34.85#ibcon#read 5, iclass 29, count 0 2006.173.10:32:34.85#ibcon#about to read 6, iclass 29, count 0 2006.173.10:32:34.85#ibcon#read 6, iclass 29, count 0 2006.173.10:32:34.85#ibcon#end of sib2, iclass 29, count 0 2006.173.10:32:34.85#ibcon#*after write, iclass 29, count 0 2006.173.10:32:34.85#ibcon#*before return 0, iclass 29, count 0 2006.173.10:32:34.85#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.10:32:34.85#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.10:32:34.85#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.10:32:34.85#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.10:32:34.85$vck44/valo=3,564.99 2006.173.10:32:34.85#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.10:32:34.85#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.10:32:34.85#ibcon#ireg 17 cls_cnt 0 2006.173.10:32:34.85#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.10:32:34.85#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.10:32:34.85#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.10:32:34.85#ibcon#enter wrdev, iclass 31, count 0 2006.173.10:32:34.85#ibcon#first serial, iclass 31, count 0 2006.173.10:32:34.85#ibcon#enter sib2, iclass 31, count 0 2006.173.10:32:34.85#ibcon#flushed, iclass 31, count 0 2006.173.10:32:34.85#ibcon#about to write, iclass 31, count 0 2006.173.10:32:34.85#ibcon#wrote, iclass 31, count 0 2006.173.10:32:34.85#ibcon#about to read 3, iclass 31, count 0 2006.173.10:32:34.87#ibcon#read 3, iclass 31, count 0 2006.173.10:32:34.87#ibcon#about to read 4, iclass 31, count 0 2006.173.10:32:34.87#ibcon#read 4, iclass 31, count 0 2006.173.10:32:34.87#ibcon#about to read 5, iclass 31, count 0 2006.173.10:32:34.87#ibcon#read 5, iclass 31, count 0 2006.173.10:32:34.87#ibcon#about to read 6, iclass 31, count 0 2006.173.10:32:34.87#ibcon#read 6, iclass 31, count 0 2006.173.10:32:34.87#ibcon#end of sib2, iclass 31, count 0 2006.173.10:32:34.87#ibcon#*mode == 0, iclass 31, count 0 2006.173.10:32:34.87#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.10:32:34.87#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.10:32:34.87#ibcon#*before write, iclass 31, count 0 2006.173.10:32:34.87#ibcon#enter sib2, iclass 31, count 0 2006.173.10:32:34.87#ibcon#flushed, iclass 31, count 0 2006.173.10:32:34.87#ibcon#about to write, iclass 31, count 0 2006.173.10:32:34.87#ibcon#wrote, iclass 31, count 0 2006.173.10:32:34.87#ibcon#about to read 3, iclass 31, count 0 2006.173.10:32:34.91#ibcon#read 3, iclass 31, count 0 2006.173.10:32:34.91#ibcon#about to read 4, iclass 31, count 0 2006.173.10:32:34.91#ibcon#read 4, iclass 31, count 0 2006.173.10:32:34.91#ibcon#about to read 5, iclass 31, count 0 2006.173.10:32:34.91#ibcon#read 5, iclass 31, count 0 2006.173.10:32:34.91#ibcon#about to read 6, iclass 31, count 0 2006.173.10:32:34.91#ibcon#read 6, iclass 31, count 0 2006.173.10:32:34.91#ibcon#end of sib2, iclass 31, count 0 2006.173.10:32:34.91#ibcon#*after write, iclass 31, count 0 2006.173.10:32:34.91#ibcon#*before return 0, iclass 31, count 0 2006.173.10:32:34.91#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.10:32:34.91#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.10:32:34.91#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.10:32:34.91#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.10:32:34.91$vck44/va=3,5 2006.173.10:32:34.91#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.173.10:32:34.91#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.173.10:32:34.91#ibcon#ireg 11 cls_cnt 2 2006.173.10:32:34.91#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.10:32:34.97#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.10:32:34.97#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.10:32:34.97#ibcon#enter wrdev, iclass 33, count 2 2006.173.10:32:34.97#ibcon#first serial, iclass 33, count 2 2006.173.10:32:34.97#ibcon#enter sib2, iclass 33, count 2 2006.173.10:32:34.97#ibcon#flushed, iclass 33, count 2 2006.173.10:32:34.97#ibcon#about to write, iclass 33, count 2 2006.173.10:32:34.97#ibcon#wrote, iclass 33, count 2 2006.173.10:32:34.97#ibcon#about to read 3, iclass 33, count 2 2006.173.10:32:34.99#ibcon#read 3, iclass 33, count 2 2006.173.10:32:34.99#ibcon#about to read 4, iclass 33, count 2 2006.173.10:32:34.99#ibcon#read 4, iclass 33, count 2 2006.173.10:32:34.99#ibcon#about to read 5, iclass 33, count 2 2006.173.10:32:34.99#ibcon#read 5, iclass 33, count 2 2006.173.10:32:34.99#ibcon#about to read 6, iclass 33, count 2 2006.173.10:32:34.99#ibcon#read 6, iclass 33, count 2 2006.173.10:32:34.99#ibcon#end of sib2, iclass 33, count 2 2006.173.10:32:34.99#ibcon#*mode == 0, iclass 33, count 2 2006.173.10:32:34.99#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.173.10:32:34.99#ibcon#[25=AT03-05\r\n] 2006.173.10:32:34.99#ibcon#*before write, iclass 33, count 2 2006.173.10:32:34.99#ibcon#enter sib2, iclass 33, count 2 2006.173.10:32:34.99#ibcon#flushed, iclass 33, count 2 2006.173.10:32:34.99#ibcon#about to write, iclass 33, count 2 2006.173.10:32:34.99#ibcon#wrote, iclass 33, count 2 2006.173.10:32:34.99#ibcon#about to read 3, iclass 33, count 2 2006.173.10:32:35.02#ibcon#read 3, iclass 33, count 2 2006.173.10:32:35.02#ibcon#about to read 4, iclass 33, count 2 2006.173.10:32:35.02#ibcon#read 4, iclass 33, count 2 2006.173.10:32:35.02#ibcon#about to read 5, iclass 33, count 2 2006.173.10:32:35.02#ibcon#read 5, iclass 33, count 2 2006.173.10:32:35.02#ibcon#about to read 6, iclass 33, count 2 2006.173.10:32:35.02#ibcon#read 6, iclass 33, count 2 2006.173.10:32:35.02#ibcon#end of sib2, iclass 33, count 2 2006.173.10:32:35.02#ibcon#*after write, iclass 33, count 2 2006.173.10:32:35.02#ibcon#*before return 0, iclass 33, count 2 2006.173.10:32:35.02#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.10:32:35.02#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.173.10:32:35.02#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.173.10:32:35.02#ibcon#ireg 7 cls_cnt 0 2006.173.10:32:35.02#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.10:32:35.14#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.10:32:35.14#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.10:32:35.14#ibcon#enter wrdev, iclass 33, count 0 2006.173.10:32:35.14#ibcon#first serial, iclass 33, count 0 2006.173.10:32:35.14#ibcon#enter sib2, iclass 33, count 0 2006.173.10:32:35.14#ibcon#flushed, iclass 33, count 0 2006.173.10:32:35.14#ibcon#about to write, iclass 33, count 0 2006.173.10:32:35.14#ibcon#wrote, iclass 33, count 0 2006.173.10:32:35.14#ibcon#about to read 3, iclass 33, count 0 2006.173.10:32:35.16#ibcon#read 3, iclass 33, count 0 2006.173.10:32:35.16#ibcon#about to read 4, iclass 33, count 0 2006.173.10:32:35.16#ibcon#read 4, iclass 33, count 0 2006.173.10:32:35.16#ibcon#about to read 5, iclass 33, count 0 2006.173.10:32:35.16#ibcon#read 5, iclass 33, count 0 2006.173.10:32:35.16#ibcon#about to read 6, iclass 33, count 0 2006.173.10:32:35.16#ibcon#read 6, iclass 33, count 0 2006.173.10:32:35.16#ibcon#end of sib2, iclass 33, count 0 2006.173.10:32:35.16#ibcon#*mode == 0, iclass 33, count 0 2006.173.10:32:35.16#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.10:32:35.16#ibcon#[25=USB\r\n] 2006.173.10:32:35.16#ibcon#*before write, iclass 33, count 0 2006.173.10:32:35.16#ibcon#enter sib2, iclass 33, count 0 2006.173.10:32:35.16#ibcon#flushed, iclass 33, count 0 2006.173.10:32:35.16#ibcon#about to write, iclass 33, count 0 2006.173.10:32:35.16#ibcon#wrote, iclass 33, count 0 2006.173.10:32:35.16#ibcon#about to read 3, iclass 33, count 0 2006.173.10:32:35.19#ibcon#read 3, iclass 33, count 0 2006.173.10:32:35.19#ibcon#about to read 4, iclass 33, count 0 2006.173.10:32:35.19#ibcon#read 4, iclass 33, count 0 2006.173.10:32:35.19#ibcon#about to read 5, iclass 33, count 0 2006.173.10:32:35.19#ibcon#read 5, iclass 33, count 0 2006.173.10:32:35.19#ibcon#about to read 6, iclass 33, count 0 2006.173.10:32:35.19#ibcon#read 6, iclass 33, count 0 2006.173.10:32:35.19#ibcon#end of sib2, iclass 33, count 0 2006.173.10:32:35.19#ibcon#*after write, iclass 33, count 0 2006.173.10:32:35.19#ibcon#*before return 0, iclass 33, count 0 2006.173.10:32:35.19#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.10:32:35.19#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.173.10:32:35.19#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.10:32:35.19#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.10:32:35.19$vck44/valo=4,624.99 2006.173.10:32:35.19#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.10:32:35.19#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.10:32:35.19#ibcon#ireg 17 cls_cnt 0 2006.173.10:32:35.19#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.10:32:35.19#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.10:32:35.19#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.10:32:35.19#ibcon#enter wrdev, iclass 35, count 0 2006.173.10:32:35.19#ibcon#first serial, iclass 35, count 0 2006.173.10:32:35.19#ibcon#enter sib2, iclass 35, count 0 2006.173.10:32:35.19#ibcon#flushed, iclass 35, count 0 2006.173.10:32:35.19#ibcon#about to write, iclass 35, count 0 2006.173.10:32:35.19#ibcon#wrote, iclass 35, count 0 2006.173.10:32:35.19#ibcon#about to read 3, iclass 35, count 0 2006.173.10:32:35.21#ibcon#read 3, iclass 35, count 0 2006.173.10:32:35.21#ibcon#about to read 4, iclass 35, count 0 2006.173.10:32:35.21#ibcon#read 4, iclass 35, count 0 2006.173.10:32:35.21#ibcon#about to read 5, iclass 35, count 0 2006.173.10:32:35.21#ibcon#read 5, iclass 35, count 0 2006.173.10:32:35.21#ibcon#about to read 6, iclass 35, count 0 2006.173.10:32:35.21#ibcon#read 6, iclass 35, count 0 2006.173.10:32:35.21#ibcon#end of sib2, iclass 35, count 0 2006.173.10:32:35.21#ibcon#*mode == 0, iclass 35, count 0 2006.173.10:32:35.21#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.10:32:35.21#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.10:32:35.21#ibcon#*before write, iclass 35, count 0 2006.173.10:32:35.21#ibcon#enter sib2, iclass 35, count 0 2006.173.10:32:35.21#ibcon#flushed, iclass 35, count 0 2006.173.10:32:35.21#ibcon#about to write, iclass 35, count 0 2006.173.10:32:35.21#ibcon#wrote, iclass 35, count 0 2006.173.10:32:35.21#ibcon#about to read 3, iclass 35, count 0 2006.173.10:32:35.25#ibcon#read 3, iclass 35, count 0 2006.173.10:32:35.25#ibcon#about to read 4, iclass 35, count 0 2006.173.10:32:35.25#ibcon#read 4, iclass 35, count 0 2006.173.10:32:35.25#ibcon#about to read 5, iclass 35, count 0 2006.173.10:32:35.25#ibcon#read 5, iclass 35, count 0 2006.173.10:32:35.25#ibcon#about to read 6, iclass 35, count 0 2006.173.10:32:35.25#ibcon#read 6, iclass 35, count 0 2006.173.10:32:35.25#ibcon#end of sib2, iclass 35, count 0 2006.173.10:32:35.25#ibcon#*after write, iclass 35, count 0 2006.173.10:32:35.25#ibcon#*before return 0, iclass 35, count 0 2006.173.10:32:35.25#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.10:32:35.25#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.10:32:35.25#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.10:32:35.25#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.10:32:35.25$vck44/va=4,6 2006.173.10:32:35.25#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.173.10:32:35.25#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.173.10:32:35.25#ibcon#ireg 11 cls_cnt 2 2006.173.10:32:35.25#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.10:32:35.31#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.10:32:35.31#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.10:32:35.31#ibcon#enter wrdev, iclass 37, count 2 2006.173.10:32:35.31#ibcon#first serial, iclass 37, count 2 2006.173.10:32:35.31#ibcon#enter sib2, iclass 37, count 2 2006.173.10:32:35.31#ibcon#flushed, iclass 37, count 2 2006.173.10:32:35.31#ibcon#about to write, iclass 37, count 2 2006.173.10:32:35.31#ibcon#wrote, iclass 37, count 2 2006.173.10:32:35.31#ibcon#about to read 3, iclass 37, count 2 2006.173.10:32:35.33#ibcon#read 3, iclass 37, count 2 2006.173.10:32:35.33#ibcon#about to read 4, iclass 37, count 2 2006.173.10:32:35.33#ibcon#read 4, iclass 37, count 2 2006.173.10:32:35.33#ibcon#about to read 5, iclass 37, count 2 2006.173.10:32:35.33#ibcon#read 5, iclass 37, count 2 2006.173.10:32:35.33#ibcon#about to read 6, iclass 37, count 2 2006.173.10:32:35.33#ibcon#read 6, iclass 37, count 2 2006.173.10:32:35.33#ibcon#end of sib2, iclass 37, count 2 2006.173.10:32:35.33#ibcon#*mode == 0, iclass 37, count 2 2006.173.10:32:35.33#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.173.10:32:35.33#ibcon#[25=AT04-06\r\n] 2006.173.10:32:35.33#ibcon#*before write, iclass 37, count 2 2006.173.10:32:35.33#ibcon#enter sib2, iclass 37, count 2 2006.173.10:32:35.33#ibcon#flushed, iclass 37, count 2 2006.173.10:32:35.33#ibcon#about to write, iclass 37, count 2 2006.173.10:32:35.33#ibcon#wrote, iclass 37, count 2 2006.173.10:32:35.33#ibcon#about to read 3, iclass 37, count 2 2006.173.10:32:35.36#ibcon#read 3, iclass 37, count 2 2006.173.10:32:35.36#ibcon#about to read 4, iclass 37, count 2 2006.173.10:32:35.36#ibcon#read 4, iclass 37, count 2 2006.173.10:32:35.36#ibcon#about to read 5, iclass 37, count 2 2006.173.10:32:35.36#ibcon#read 5, iclass 37, count 2 2006.173.10:32:35.36#ibcon#about to read 6, iclass 37, count 2 2006.173.10:32:35.36#ibcon#read 6, iclass 37, count 2 2006.173.10:32:35.36#ibcon#end of sib2, iclass 37, count 2 2006.173.10:32:35.36#ibcon#*after write, iclass 37, count 2 2006.173.10:32:35.36#ibcon#*before return 0, iclass 37, count 2 2006.173.10:32:35.36#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.10:32:35.36#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.173.10:32:35.36#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.173.10:32:35.36#ibcon#ireg 7 cls_cnt 0 2006.173.10:32:35.36#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.10:32:35.48#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.10:32:35.48#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.10:32:35.48#ibcon#enter wrdev, iclass 37, count 0 2006.173.10:32:35.48#ibcon#first serial, iclass 37, count 0 2006.173.10:32:35.48#ibcon#enter sib2, iclass 37, count 0 2006.173.10:32:35.48#ibcon#flushed, iclass 37, count 0 2006.173.10:32:35.48#ibcon#about to write, iclass 37, count 0 2006.173.10:32:35.48#ibcon#wrote, iclass 37, count 0 2006.173.10:32:35.48#ibcon#about to read 3, iclass 37, count 0 2006.173.10:32:35.50#ibcon#read 3, iclass 37, count 0 2006.173.10:32:35.50#ibcon#about to read 4, iclass 37, count 0 2006.173.10:32:35.50#ibcon#read 4, iclass 37, count 0 2006.173.10:32:35.50#ibcon#about to read 5, iclass 37, count 0 2006.173.10:32:35.50#ibcon#read 5, iclass 37, count 0 2006.173.10:32:35.50#ibcon#about to read 6, iclass 37, count 0 2006.173.10:32:35.50#ibcon#read 6, iclass 37, count 0 2006.173.10:32:35.50#ibcon#end of sib2, iclass 37, count 0 2006.173.10:32:35.50#ibcon#*mode == 0, iclass 37, count 0 2006.173.10:32:35.50#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.10:32:35.50#ibcon#[25=USB\r\n] 2006.173.10:32:35.50#ibcon#*before write, iclass 37, count 0 2006.173.10:32:35.50#ibcon#enter sib2, iclass 37, count 0 2006.173.10:32:35.50#ibcon#flushed, iclass 37, count 0 2006.173.10:32:35.50#ibcon#about to write, iclass 37, count 0 2006.173.10:32:35.50#ibcon#wrote, iclass 37, count 0 2006.173.10:32:35.50#ibcon#about to read 3, iclass 37, count 0 2006.173.10:32:35.53#ibcon#read 3, iclass 37, count 0 2006.173.10:32:35.53#ibcon#about to read 4, iclass 37, count 0 2006.173.10:32:35.53#ibcon#read 4, iclass 37, count 0 2006.173.10:32:35.53#ibcon#about to read 5, iclass 37, count 0 2006.173.10:32:35.53#ibcon#read 5, iclass 37, count 0 2006.173.10:32:35.53#ibcon#about to read 6, iclass 37, count 0 2006.173.10:32:35.53#ibcon#read 6, iclass 37, count 0 2006.173.10:32:35.53#ibcon#end of sib2, iclass 37, count 0 2006.173.10:32:35.53#ibcon#*after write, iclass 37, count 0 2006.173.10:32:35.53#ibcon#*before return 0, iclass 37, count 0 2006.173.10:32:35.53#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.10:32:35.53#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.173.10:32:35.53#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.10:32:35.53#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.10:32:35.53$vck44/valo=5,734.99 2006.173.10:32:35.53#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.10:32:35.53#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.10:32:35.53#ibcon#ireg 17 cls_cnt 0 2006.173.10:32:35.53#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.10:32:35.53#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.10:32:35.53#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.10:32:35.53#ibcon#enter wrdev, iclass 39, count 0 2006.173.10:32:35.53#ibcon#first serial, iclass 39, count 0 2006.173.10:32:35.53#ibcon#enter sib2, iclass 39, count 0 2006.173.10:32:35.53#ibcon#flushed, iclass 39, count 0 2006.173.10:32:35.53#ibcon#about to write, iclass 39, count 0 2006.173.10:32:35.53#ibcon#wrote, iclass 39, count 0 2006.173.10:32:35.53#ibcon#about to read 3, iclass 39, count 0 2006.173.10:32:35.55#ibcon#read 3, iclass 39, count 0 2006.173.10:32:35.55#ibcon#about to read 4, iclass 39, count 0 2006.173.10:32:35.55#ibcon#read 4, iclass 39, count 0 2006.173.10:32:35.55#ibcon#about to read 5, iclass 39, count 0 2006.173.10:32:35.55#ibcon#read 5, iclass 39, count 0 2006.173.10:32:35.55#ibcon#about to read 6, iclass 39, count 0 2006.173.10:32:35.55#ibcon#read 6, iclass 39, count 0 2006.173.10:32:35.55#ibcon#end of sib2, iclass 39, count 0 2006.173.10:32:35.55#ibcon#*mode == 0, iclass 39, count 0 2006.173.10:32:35.55#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.10:32:35.55#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.10:32:35.55#ibcon#*before write, iclass 39, count 0 2006.173.10:32:35.55#ibcon#enter sib2, iclass 39, count 0 2006.173.10:32:35.55#ibcon#flushed, iclass 39, count 0 2006.173.10:32:35.55#ibcon#about to write, iclass 39, count 0 2006.173.10:32:35.55#ibcon#wrote, iclass 39, count 0 2006.173.10:32:35.55#ibcon#about to read 3, iclass 39, count 0 2006.173.10:32:35.59#ibcon#read 3, iclass 39, count 0 2006.173.10:32:35.59#ibcon#about to read 4, iclass 39, count 0 2006.173.10:32:35.59#ibcon#read 4, iclass 39, count 0 2006.173.10:32:35.59#ibcon#about to read 5, iclass 39, count 0 2006.173.10:32:35.59#ibcon#read 5, iclass 39, count 0 2006.173.10:32:35.59#ibcon#about to read 6, iclass 39, count 0 2006.173.10:32:35.59#ibcon#read 6, iclass 39, count 0 2006.173.10:32:35.59#ibcon#end of sib2, iclass 39, count 0 2006.173.10:32:35.59#ibcon#*after write, iclass 39, count 0 2006.173.10:32:35.59#ibcon#*before return 0, iclass 39, count 0 2006.173.10:32:35.59#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.10:32:35.59#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.10:32:35.59#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.10:32:35.59#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.10:32:35.59$vck44/va=5,4 2006.173.10:32:35.59#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.10:32:35.59#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.10:32:35.59#ibcon#ireg 11 cls_cnt 2 2006.173.10:32:35.59#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.10:32:35.65#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.10:32:35.65#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.10:32:35.65#ibcon#enter wrdev, iclass 3, count 2 2006.173.10:32:35.65#ibcon#first serial, iclass 3, count 2 2006.173.10:32:35.65#ibcon#enter sib2, iclass 3, count 2 2006.173.10:32:35.65#ibcon#flushed, iclass 3, count 2 2006.173.10:32:35.65#ibcon#about to write, iclass 3, count 2 2006.173.10:32:35.65#ibcon#wrote, iclass 3, count 2 2006.173.10:32:35.65#ibcon#about to read 3, iclass 3, count 2 2006.173.10:32:35.67#ibcon#read 3, iclass 3, count 2 2006.173.10:32:35.67#ibcon#about to read 4, iclass 3, count 2 2006.173.10:32:35.67#ibcon#read 4, iclass 3, count 2 2006.173.10:32:35.67#ibcon#about to read 5, iclass 3, count 2 2006.173.10:32:35.67#ibcon#read 5, iclass 3, count 2 2006.173.10:32:35.67#ibcon#about to read 6, iclass 3, count 2 2006.173.10:32:35.67#ibcon#read 6, iclass 3, count 2 2006.173.10:32:35.67#ibcon#end of sib2, iclass 3, count 2 2006.173.10:32:35.67#ibcon#*mode == 0, iclass 3, count 2 2006.173.10:32:35.67#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.10:32:35.67#ibcon#[25=AT05-04\r\n] 2006.173.10:32:35.67#ibcon#*before write, iclass 3, count 2 2006.173.10:32:35.67#ibcon#enter sib2, iclass 3, count 2 2006.173.10:32:35.67#ibcon#flushed, iclass 3, count 2 2006.173.10:32:35.67#ibcon#about to write, iclass 3, count 2 2006.173.10:32:35.67#ibcon#wrote, iclass 3, count 2 2006.173.10:32:35.67#ibcon#about to read 3, iclass 3, count 2 2006.173.10:32:35.70#ibcon#read 3, iclass 3, count 2 2006.173.10:32:35.70#ibcon#about to read 4, iclass 3, count 2 2006.173.10:32:35.70#ibcon#read 4, iclass 3, count 2 2006.173.10:32:35.70#ibcon#about to read 5, iclass 3, count 2 2006.173.10:32:35.70#ibcon#read 5, iclass 3, count 2 2006.173.10:32:35.70#ibcon#about to read 6, iclass 3, count 2 2006.173.10:32:35.70#ibcon#read 6, iclass 3, count 2 2006.173.10:32:35.70#ibcon#end of sib2, iclass 3, count 2 2006.173.10:32:35.70#ibcon#*after write, iclass 3, count 2 2006.173.10:32:35.70#ibcon#*before return 0, iclass 3, count 2 2006.173.10:32:35.70#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.10:32:35.70#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.10:32:35.70#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.10:32:35.70#ibcon#ireg 7 cls_cnt 0 2006.173.10:32:35.70#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.10:32:35.82#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.10:32:35.82#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.10:32:35.82#ibcon#enter wrdev, iclass 3, count 0 2006.173.10:32:35.82#ibcon#first serial, iclass 3, count 0 2006.173.10:32:35.82#ibcon#enter sib2, iclass 3, count 0 2006.173.10:32:35.82#ibcon#flushed, iclass 3, count 0 2006.173.10:32:35.82#ibcon#about to write, iclass 3, count 0 2006.173.10:32:35.82#ibcon#wrote, iclass 3, count 0 2006.173.10:32:35.82#ibcon#about to read 3, iclass 3, count 0 2006.173.10:32:35.84#ibcon#read 3, iclass 3, count 0 2006.173.10:32:35.84#ibcon#about to read 4, iclass 3, count 0 2006.173.10:32:35.84#ibcon#read 4, iclass 3, count 0 2006.173.10:32:35.84#ibcon#about to read 5, iclass 3, count 0 2006.173.10:32:35.84#ibcon#read 5, iclass 3, count 0 2006.173.10:32:35.84#ibcon#about to read 6, iclass 3, count 0 2006.173.10:32:35.84#ibcon#read 6, iclass 3, count 0 2006.173.10:32:35.84#ibcon#end of sib2, iclass 3, count 0 2006.173.10:32:35.84#ibcon#*mode == 0, iclass 3, count 0 2006.173.10:32:35.84#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.10:32:35.84#ibcon#[25=USB\r\n] 2006.173.10:32:35.84#ibcon#*before write, iclass 3, count 0 2006.173.10:32:35.84#ibcon#enter sib2, iclass 3, count 0 2006.173.10:32:35.84#ibcon#flushed, iclass 3, count 0 2006.173.10:32:35.84#ibcon#about to write, iclass 3, count 0 2006.173.10:32:35.84#ibcon#wrote, iclass 3, count 0 2006.173.10:32:35.84#ibcon#about to read 3, iclass 3, count 0 2006.173.10:32:35.87#ibcon#read 3, iclass 3, count 0 2006.173.10:32:35.87#ibcon#about to read 4, iclass 3, count 0 2006.173.10:32:35.87#ibcon#read 4, iclass 3, count 0 2006.173.10:32:35.87#ibcon#about to read 5, iclass 3, count 0 2006.173.10:32:35.87#ibcon#read 5, iclass 3, count 0 2006.173.10:32:35.87#ibcon#about to read 6, iclass 3, count 0 2006.173.10:32:35.87#ibcon#read 6, iclass 3, count 0 2006.173.10:32:35.87#ibcon#end of sib2, iclass 3, count 0 2006.173.10:32:35.87#ibcon#*after write, iclass 3, count 0 2006.173.10:32:35.87#ibcon#*before return 0, iclass 3, count 0 2006.173.10:32:35.87#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.10:32:35.87#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.10:32:35.87#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.10:32:35.87#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.10:32:35.87$vck44/valo=6,814.99 2006.173.10:32:35.87#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.10:32:35.87#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.10:32:35.87#ibcon#ireg 17 cls_cnt 0 2006.173.10:32:35.87#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.10:32:35.87#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.10:32:35.87#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.10:32:35.87#ibcon#enter wrdev, iclass 5, count 0 2006.173.10:32:35.87#ibcon#first serial, iclass 5, count 0 2006.173.10:32:35.87#ibcon#enter sib2, iclass 5, count 0 2006.173.10:32:35.87#ibcon#flushed, iclass 5, count 0 2006.173.10:32:35.87#ibcon#about to write, iclass 5, count 0 2006.173.10:32:35.87#ibcon#wrote, iclass 5, count 0 2006.173.10:32:35.87#ibcon#about to read 3, iclass 5, count 0 2006.173.10:32:35.89#ibcon#read 3, iclass 5, count 0 2006.173.10:32:35.89#ibcon#about to read 4, iclass 5, count 0 2006.173.10:32:35.89#ibcon#read 4, iclass 5, count 0 2006.173.10:32:35.89#ibcon#about to read 5, iclass 5, count 0 2006.173.10:32:35.89#ibcon#read 5, iclass 5, count 0 2006.173.10:32:35.89#ibcon#about to read 6, iclass 5, count 0 2006.173.10:32:35.89#ibcon#read 6, iclass 5, count 0 2006.173.10:32:35.89#ibcon#end of sib2, iclass 5, count 0 2006.173.10:32:35.89#ibcon#*mode == 0, iclass 5, count 0 2006.173.10:32:35.89#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.10:32:35.89#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.10:32:35.89#ibcon#*before write, iclass 5, count 0 2006.173.10:32:35.89#ibcon#enter sib2, iclass 5, count 0 2006.173.10:32:35.89#ibcon#flushed, iclass 5, count 0 2006.173.10:32:35.89#ibcon#about to write, iclass 5, count 0 2006.173.10:32:35.89#ibcon#wrote, iclass 5, count 0 2006.173.10:32:35.89#ibcon#about to read 3, iclass 5, count 0 2006.173.10:32:35.93#ibcon#read 3, iclass 5, count 0 2006.173.10:32:35.93#ibcon#about to read 4, iclass 5, count 0 2006.173.10:32:35.93#ibcon#read 4, iclass 5, count 0 2006.173.10:32:35.93#ibcon#about to read 5, iclass 5, count 0 2006.173.10:32:35.93#ibcon#read 5, iclass 5, count 0 2006.173.10:32:35.93#ibcon#about to read 6, iclass 5, count 0 2006.173.10:32:35.93#ibcon#read 6, iclass 5, count 0 2006.173.10:32:35.93#ibcon#end of sib2, iclass 5, count 0 2006.173.10:32:35.93#ibcon#*after write, iclass 5, count 0 2006.173.10:32:35.93#ibcon#*before return 0, iclass 5, count 0 2006.173.10:32:35.93#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.10:32:35.93#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.10:32:35.93#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.10:32:35.93#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.10:32:35.93$vck44/va=6,3 2006.173.10:32:35.93#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.173.10:32:35.93#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.173.10:32:35.93#ibcon#ireg 11 cls_cnt 2 2006.173.10:32:35.93#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.10:32:35.99#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.10:32:35.99#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.10:32:35.99#ibcon#enter wrdev, iclass 7, count 2 2006.173.10:32:35.99#ibcon#first serial, iclass 7, count 2 2006.173.10:32:35.99#ibcon#enter sib2, iclass 7, count 2 2006.173.10:32:35.99#ibcon#flushed, iclass 7, count 2 2006.173.10:32:35.99#ibcon#about to write, iclass 7, count 2 2006.173.10:32:35.99#ibcon#wrote, iclass 7, count 2 2006.173.10:32:35.99#ibcon#about to read 3, iclass 7, count 2 2006.173.10:32:36.01#ibcon#read 3, iclass 7, count 2 2006.173.10:32:36.01#ibcon#about to read 4, iclass 7, count 2 2006.173.10:32:36.01#ibcon#read 4, iclass 7, count 2 2006.173.10:32:36.01#ibcon#about to read 5, iclass 7, count 2 2006.173.10:32:36.01#ibcon#read 5, iclass 7, count 2 2006.173.10:32:36.01#ibcon#about to read 6, iclass 7, count 2 2006.173.10:32:36.01#ibcon#read 6, iclass 7, count 2 2006.173.10:32:36.01#ibcon#end of sib2, iclass 7, count 2 2006.173.10:32:36.01#ibcon#*mode == 0, iclass 7, count 2 2006.173.10:32:36.01#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.173.10:32:36.01#ibcon#[25=AT06-03\r\n] 2006.173.10:32:36.01#ibcon#*before write, iclass 7, count 2 2006.173.10:32:36.01#ibcon#enter sib2, iclass 7, count 2 2006.173.10:32:36.01#ibcon#flushed, iclass 7, count 2 2006.173.10:32:36.01#ibcon#about to write, iclass 7, count 2 2006.173.10:32:36.01#ibcon#wrote, iclass 7, count 2 2006.173.10:32:36.01#ibcon#about to read 3, iclass 7, count 2 2006.173.10:32:36.04#ibcon#read 3, iclass 7, count 2 2006.173.10:32:36.04#ibcon#about to read 4, iclass 7, count 2 2006.173.10:32:36.04#ibcon#read 4, iclass 7, count 2 2006.173.10:32:36.04#ibcon#about to read 5, iclass 7, count 2 2006.173.10:32:36.04#ibcon#read 5, iclass 7, count 2 2006.173.10:32:36.04#ibcon#about to read 6, iclass 7, count 2 2006.173.10:32:36.04#ibcon#read 6, iclass 7, count 2 2006.173.10:32:36.04#ibcon#end of sib2, iclass 7, count 2 2006.173.10:32:36.04#ibcon#*after write, iclass 7, count 2 2006.173.10:32:36.04#ibcon#*before return 0, iclass 7, count 2 2006.173.10:32:36.04#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.10:32:36.04#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.173.10:32:36.04#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.173.10:32:36.04#ibcon#ireg 7 cls_cnt 0 2006.173.10:32:36.04#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.10:32:36.16#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.10:32:36.16#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.10:32:36.16#ibcon#enter wrdev, iclass 7, count 0 2006.173.10:32:36.16#ibcon#first serial, iclass 7, count 0 2006.173.10:32:36.16#ibcon#enter sib2, iclass 7, count 0 2006.173.10:32:36.16#ibcon#flushed, iclass 7, count 0 2006.173.10:32:36.16#ibcon#about to write, iclass 7, count 0 2006.173.10:32:36.16#ibcon#wrote, iclass 7, count 0 2006.173.10:32:36.16#ibcon#about to read 3, iclass 7, count 0 2006.173.10:32:36.18#ibcon#read 3, iclass 7, count 0 2006.173.10:32:36.18#ibcon#about to read 4, iclass 7, count 0 2006.173.10:32:36.18#ibcon#read 4, iclass 7, count 0 2006.173.10:32:36.18#ibcon#about to read 5, iclass 7, count 0 2006.173.10:32:36.18#ibcon#read 5, iclass 7, count 0 2006.173.10:32:36.18#ibcon#about to read 6, iclass 7, count 0 2006.173.10:32:36.18#ibcon#read 6, iclass 7, count 0 2006.173.10:32:36.18#ibcon#end of sib2, iclass 7, count 0 2006.173.10:32:36.18#ibcon#*mode == 0, iclass 7, count 0 2006.173.10:32:36.18#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.10:32:36.18#ibcon#[25=USB\r\n] 2006.173.10:32:36.18#ibcon#*before write, iclass 7, count 0 2006.173.10:32:36.18#ibcon#enter sib2, iclass 7, count 0 2006.173.10:32:36.18#ibcon#flushed, iclass 7, count 0 2006.173.10:32:36.18#ibcon#about to write, iclass 7, count 0 2006.173.10:32:36.18#ibcon#wrote, iclass 7, count 0 2006.173.10:32:36.18#ibcon#about to read 3, iclass 7, count 0 2006.173.10:32:36.21#ibcon#read 3, iclass 7, count 0 2006.173.10:32:36.21#ibcon#about to read 4, iclass 7, count 0 2006.173.10:32:36.21#ibcon#read 4, iclass 7, count 0 2006.173.10:32:36.21#ibcon#about to read 5, iclass 7, count 0 2006.173.10:32:36.21#ibcon#read 5, iclass 7, count 0 2006.173.10:32:36.21#ibcon#about to read 6, iclass 7, count 0 2006.173.10:32:36.21#ibcon#read 6, iclass 7, count 0 2006.173.10:32:36.21#ibcon#end of sib2, iclass 7, count 0 2006.173.10:32:36.21#ibcon#*after write, iclass 7, count 0 2006.173.10:32:36.21#ibcon#*before return 0, iclass 7, count 0 2006.173.10:32:36.21#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.10:32:36.21#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.173.10:32:36.21#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.10:32:36.21#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.10:32:36.21$vck44/valo=7,864.99 2006.173.10:32:36.21#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.10:32:36.21#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.10:32:36.21#ibcon#ireg 17 cls_cnt 0 2006.173.10:32:36.21#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.10:32:36.21#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.10:32:36.21#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.10:32:36.21#ibcon#enter wrdev, iclass 11, count 0 2006.173.10:32:36.21#ibcon#first serial, iclass 11, count 0 2006.173.10:32:36.21#ibcon#enter sib2, iclass 11, count 0 2006.173.10:32:36.21#ibcon#flushed, iclass 11, count 0 2006.173.10:32:36.21#ibcon#about to write, iclass 11, count 0 2006.173.10:32:36.21#ibcon#wrote, iclass 11, count 0 2006.173.10:32:36.21#ibcon#about to read 3, iclass 11, count 0 2006.173.10:32:36.23#ibcon#read 3, iclass 11, count 0 2006.173.10:32:36.23#ibcon#about to read 4, iclass 11, count 0 2006.173.10:32:36.23#ibcon#read 4, iclass 11, count 0 2006.173.10:32:36.23#ibcon#about to read 5, iclass 11, count 0 2006.173.10:32:36.23#ibcon#read 5, iclass 11, count 0 2006.173.10:32:36.23#ibcon#about to read 6, iclass 11, count 0 2006.173.10:32:36.23#ibcon#read 6, iclass 11, count 0 2006.173.10:32:36.23#ibcon#end of sib2, iclass 11, count 0 2006.173.10:32:36.23#ibcon#*mode == 0, iclass 11, count 0 2006.173.10:32:36.23#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.10:32:36.23#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.10:32:36.23#ibcon#*before write, iclass 11, count 0 2006.173.10:32:36.23#ibcon#enter sib2, iclass 11, count 0 2006.173.10:32:36.23#ibcon#flushed, iclass 11, count 0 2006.173.10:32:36.23#ibcon#about to write, iclass 11, count 0 2006.173.10:32:36.23#ibcon#wrote, iclass 11, count 0 2006.173.10:32:36.23#ibcon#about to read 3, iclass 11, count 0 2006.173.10:32:36.27#ibcon#read 3, iclass 11, count 0 2006.173.10:32:36.27#ibcon#about to read 4, iclass 11, count 0 2006.173.10:32:36.27#ibcon#read 4, iclass 11, count 0 2006.173.10:32:36.27#ibcon#about to read 5, iclass 11, count 0 2006.173.10:32:36.27#ibcon#read 5, iclass 11, count 0 2006.173.10:32:36.27#ibcon#about to read 6, iclass 11, count 0 2006.173.10:32:36.27#ibcon#read 6, iclass 11, count 0 2006.173.10:32:36.27#ibcon#end of sib2, iclass 11, count 0 2006.173.10:32:36.27#ibcon#*after write, iclass 11, count 0 2006.173.10:32:36.27#ibcon#*before return 0, iclass 11, count 0 2006.173.10:32:36.27#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.10:32:36.27#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.10:32:36.27#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.10:32:36.27#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.10:32:36.27$vck44/va=7,4 2006.173.10:32:36.27#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.173.10:32:36.27#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.173.10:32:36.27#ibcon#ireg 11 cls_cnt 2 2006.173.10:32:36.27#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.10:32:36.33#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.10:32:36.33#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.10:32:36.33#ibcon#enter wrdev, iclass 13, count 2 2006.173.10:32:36.33#ibcon#first serial, iclass 13, count 2 2006.173.10:32:36.33#ibcon#enter sib2, iclass 13, count 2 2006.173.10:32:36.33#ibcon#flushed, iclass 13, count 2 2006.173.10:32:36.33#ibcon#about to write, iclass 13, count 2 2006.173.10:32:36.33#ibcon#wrote, iclass 13, count 2 2006.173.10:32:36.33#ibcon#about to read 3, iclass 13, count 2 2006.173.10:32:36.35#ibcon#read 3, iclass 13, count 2 2006.173.10:32:36.35#ibcon#about to read 4, iclass 13, count 2 2006.173.10:32:36.35#ibcon#read 4, iclass 13, count 2 2006.173.10:32:36.35#ibcon#about to read 5, iclass 13, count 2 2006.173.10:32:36.35#ibcon#read 5, iclass 13, count 2 2006.173.10:32:36.35#ibcon#about to read 6, iclass 13, count 2 2006.173.10:32:36.35#ibcon#read 6, iclass 13, count 2 2006.173.10:32:36.35#ibcon#end of sib2, iclass 13, count 2 2006.173.10:32:36.35#ibcon#*mode == 0, iclass 13, count 2 2006.173.10:32:36.35#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.173.10:32:36.35#ibcon#[25=AT07-04\r\n] 2006.173.10:32:36.35#ibcon#*before write, iclass 13, count 2 2006.173.10:32:36.35#ibcon#enter sib2, iclass 13, count 2 2006.173.10:32:36.35#ibcon#flushed, iclass 13, count 2 2006.173.10:32:36.35#ibcon#about to write, iclass 13, count 2 2006.173.10:32:36.35#ibcon#wrote, iclass 13, count 2 2006.173.10:32:36.35#ibcon#about to read 3, iclass 13, count 2 2006.173.10:32:36.38#ibcon#read 3, iclass 13, count 2 2006.173.10:32:36.38#ibcon#about to read 4, iclass 13, count 2 2006.173.10:32:36.38#ibcon#read 4, iclass 13, count 2 2006.173.10:32:36.38#ibcon#about to read 5, iclass 13, count 2 2006.173.10:32:36.38#ibcon#read 5, iclass 13, count 2 2006.173.10:32:36.38#ibcon#about to read 6, iclass 13, count 2 2006.173.10:32:36.38#ibcon#read 6, iclass 13, count 2 2006.173.10:32:36.38#ibcon#end of sib2, iclass 13, count 2 2006.173.10:32:36.38#ibcon#*after write, iclass 13, count 2 2006.173.10:32:36.38#ibcon#*before return 0, iclass 13, count 2 2006.173.10:32:36.38#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.10:32:36.38#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.173.10:32:36.38#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.173.10:32:36.38#ibcon#ireg 7 cls_cnt 0 2006.173.10:32:36.38#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.10:32:36.50#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.10:32:36.50#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.10:32:36.50#ibcon#enter wrdev, iclass 13, count 0 2006.173.10:32:36.50#ibcon#first serial, iclass 13, count 0 2006.173.10:32:36.50#ibcon#enter sib2, iclass 13, count 0 2006.173.10:32:36.50#ibcon#flushed, iclass 13, count 0 2006.173.10:32:36.50#ibcon#about to write, iclass 13, count 0 2006.173.10:32:36.50#ibcon#wrote, iclass 13, count 0 2006.173.10:32:36.50#ibcon#about to read 3, iclass 13, count 0 2006.173.10:32:36.52#ibcon#read 3, iclass 13, count 0 2006.173.10:32:36.52#ibcon#about to read 4, iclass 13, count 0 2006.173.10:32:36.52#ibcon#read 4, iclass 13, count 0 2006.173.10:32:36.52#ibcon#about to read 5, iclass 13, count 0 2006.173.10:32:36.52#ibcon#read 5, iclass 13, count 0 2006.173.10:32:36.52#ibcon#about to read 6, iclass 13, count 0 2006.173.10:32:36.52#ibcon#read 6, iclass 13, count 0 2006.173.10:32:36.52#ibcon#end of sib2, iclass 13, count 0 2006.173.10:32:36.52#ibcon#*mode == 0, iclass 13, count 0 2006.173.10:32:36.52#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.10:32:36.52#ibcon#[25=USB\r\n] 2006.173.10:32:36.52#ibcon#*before write, iclass 13, count 0 2006.173.10:32:36.52#ibcon#enter sib2, iclass 13, count 0 2006.173.10:32:36.52#ibcon#flushed, iclass 13, count 0 2006.173.10:32:36.52#ibcon#about to write, iclass 13, count 0 2006.173.10:32:36.52#ibcon#wrote, iclass 13, count 0 2006.173.10:32:36.52#ibcon#about to read 3, iclass 13, count 0 2006.173.10:32:36.55#ibcon#read 3, iclass 13, count 0 2006.173.10:32:36.55#ibcon#about to read 4, iclass 13, count 0 2006.173.10:32:36.55#ibcon#read 4, iclass 13, count 0 2006.173.10:32:36.55#ibcon#about to read 5, iclass 13, count 0 2006.173.10:32:36.55#ibcon#read 5, iclass 13, count 0 2006.173.10:32:36.55#ibcon#about to read 6, iclass 13, count 0 2006.173.10:32:36.55#ibcon#read 6, iclass 13, count 0 2006.173.10:32:36.55#ibcon#end of sib2, iclass 13, count 0 2006.173.10:32:36.55#ibcon#*after write, iclass 13, count 0 2006.173.10:32:36.55#ibcon#*before return 0, iclass 13, count 0 2006.173.10:32:36.55#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.10:32:36.55#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.173.10:32:36.55#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.10:32:36.55#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.10:32:36.55$vck44/valo=8,884.99 2006.173.10:32:36.55#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.10:32:36.55#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.10:32:36.55#ibcon#ireg 17 cls_cnt 0 2006.173.10:32:36.55#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.10:32:36.55#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.10:32:36.55#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.10:32:36.55#ibcon#enter wrdev, iclass 15, count 0 2006.173.10:32:36.55#ibcon#first serial, iclass 15, count 0 2006.173.10:32:36.55#ibcon#enter sib2, iclass 15, count 0 2006.173.10:32:36.55#ibcon#flushed, iclass 15, count 0 2006.173.10:32:36.55#ibcon#about to write, iclass 15, count 0 2006.173.10:32:36.55#ibcon#wrote, iclass 15, count 0 2006.173.10:32:36.55#ibcon#about to read 3, iclass 15, count 0 2006.173.10:32:36.57#ibcon#read 3, iclass 15, count 0 2006.173.10:32:36.57#ibcon#about to read 4, iclass 15, count 0 2006.173.10:32:36.57#ibcon#read 4, iclass 15, count 0 2006.173.10:32:36.57#ibcon#about to read 5, iclass 15, count 0 2006.173.10:32:36.57#ibcon#read 5, iclass 15, count 0 2006.173.10:32:36.57#ibcon#about to read 6, iclass 15, count 0 2006.173.10:32:36.57#ibcon#read 6, iclass 15, count 0 2006.173.10:32:36.57#ibcon#end of sib2, iclass 15, count 0 2006.173.10:32:36.57#ibcon#*mode == 0, iclass 15, count 0 2006.173.10:32:36.57#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.10:32:36.57#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.10:32:36.57#ibcon#*before write, iclass 15, count 0 2006.173.10:32:36.57#ibcon#enter sib2, iclass 15, count 0 2006.173.10:32:36.57#ibcon#flushed, iclass 15, count 0 2006.173.10:32:36.57#ibcon#about to write, iclass 15, count 0 2006.173.10:32:36.57#ibcon#wrote, iclass 15, count 0 2006.173.10:32:36.57#ibcon#about to read 3, iclass 15, count 0 2006.173.10:32:36.61#ibcon#read 3, iclass 15, count 0 2006.173.10:32:36.61#ibcon#about to read 4, iclass 15, count 0 2006.173.10:32:36.61#ibcon#read 4, iclass 15, count 0 2006.173.10:32:36.61#ibcon#about to read 5, iclass 15, count 0 2006.173.10:32:36.61#ibcon#read 5, iclass 15, count 0 2006.173.10:32:36.61#ibcon#about to read 6, iclass 15, count 0 2006.173.10:32:36.61#ibcon#read 6, iclass 15, count 0 2006.173.10:32:36.61#ibcon#end of sib2, iclass 15, count 0 2006.173.10:32:36.61#ibcon#*after write, iclass 15, count 0 2006.173.10:32:36.61#ibcon#*before return 0, iclass 15, count 0 2006.173.10:32:36.61#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.10:32:36.61#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.10:32:36.61#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.10:32:36.61#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.10:32:36.61$vck44/va=8,4 2006.173.10:32:36.61#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.10:32:36.61#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.10:32:36.61#ibcon#ireg 11 cls_cnt 2 2006.173.10:32:36.61#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.10:32:36.67#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.10:32:36.67#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.10:32:36.67#ibcon#enter wrdev, iclass 17, count 2 2006.173.10:32:36.67#ibcon#first serial, iclass 17, count 2 2006.173.10:32:36.67#ibcon#enter sib2, iclass 17, count 2 2006.173.10:32:36.67#ibcon#flushed, iclass 17, count 2 2006.173.10:32:36.67#ibcon#about to write, iclass 17, count 2 2006.173.10:32:36.67#ibcon#wrote, iclass 17, count 2 2006.173.10:32:36.67#ibcon#about to read 3, iclass 17, count 2 2006.173.10:32:36.69#ibcon#read 3, iclass 17, count 2 2006.173.10:32:36.69#ibcon#about to read 4, iclass 17, count 2 2006.173.10:32:36.69#ibcon#read 4, iclass 17, count 2 2006.173.10:32:36.69#ibcon#about to read 5, iclass 17, count 2 2006.173.10:32:36.69#ibcon#read 5, iclass 17, count 2 2006.173.10:32:36.69#ibcon#about to read 6, iclass 17, count 2 2006.173.10:32:36.69#ibcon#read 6, iclass 17, count 2 2006.173.10:32:36.69#ibcon#end of sib2, iclass 17, count 2 2006.173.10:32:36.69#ibcon#*mode == 0, iclass 17, count 2 2006.173.10:32:36.69#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.10:32:36.69#ibcon#[25=AT08-04\r\n] 2006.173.10:32:36.69#ibcon#*before write, iclass 17, count 2 2006.173.10:32:36.69#ibcon#enter sib2, iclass 17, count 2 2006.173.10:32:36.69#ibcon#flushed, iclass 17, count 2 2006.173.10:32:36.69#ibcon#about to write, iclass 17, count 2 2006.173.10:32:36.69#ibcon#wrote, iclass 17, count 2 2006.173.10:32:36.69#ibcon#about to read 3, iclass 17, count 2 2006.173.10:32:36.72#ibcon#read 3, iclass 17, count 2 2006.173.10:32:36.72#ibcon#about to read 4, iclass 17, count 2 2006.173.10:32:36.72#ibcon#read 4, iclass 17, count 2 2006.173.10:32:36.72#ibcon#about to read 5, iclass 17, count 2 2006.173.10:32:36.72#ibcon#read 5, iclass 17, count 2 2006.173.10:32:36.72#ibcon#about to read 6, iclass 17, count 2 2006.173.10:32:36.72#ibcon#read 6, iclass 17, count 2 2006.173.10:32:36.72#ibcon#end of sib2, iclass 17, count 2 2006.173.10:32:36.72#ibcon#*after write, iclass 17, count 2 2006.173.10:32:36.72#ibcon#*before return 0, iclass 17, count 2 2006.173.10:32:36.72#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.10:32:36.72#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.10:32:36.72#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.10:32:36.72#ibcon#ireg 7 cls_cnt 0 2006.173.10:32:36.72#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.10:32:36.84#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.10:32:36.84#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.10:32:36.84#ibcon#enter wrdev, iclass 17, count 0 2006.173.10:32:36.84#ibcon#first serial, iclass 17, count 0 2006.173.10:32:36.84#ibcon#enter sib2, iclass 17, count 0 2006.173.10:32:36.84#ibcon#flushed, iclass 17, count 0 2006.173.10:32:36.84#ibcon#about to write, iclass 17, count 0 2006.173.10:32:36.84#ibcon#wrote, iclass 17, count 0 2006.173.10:32:36.84#ibcon#about to read 3, iclass 17, count 0 2006.173.10:32:36.86#ibcon#read 3, iclass 17, count 0 2006.173.10:32:36.86#ibcon#about to read 4, iclass 17, count 0 2006.173.10:32:36.86#ibcon#read 4, iclass 17, count 0 2006.173.10:32:36.86#ibcon#about to read 5, iclass 17, count 0 2006.173.10:32:36.86#ibcon#read 5, iclass 17, count 0 2006.173.10:32:36.86#ibcon#about to read 6, iclass 17, count 0 2006.173.10:32:36.86#ibcon#read 6, iclass 17, count 0 2006.173.10:32:36.86#ibcon#end of sib2, iclass 17, count 0 2006.173.10:32:36.86#ibcon#*mode == 0, iclass 17, count 0 2006.173.10:32:36.86#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.10:32:36.86#ibcon#[25=USB\r\n] 2006.173.10:32:36.86#ibcon#*before write, iclass 17, count 0 2006.173.10:32:36.86#ibcon#enter sib2, iclass 17, count 0 2006.173.10:32:36.86#ibcon#flushed, iclass 17, count 0 2006.173.10:32:36.86#ibcon#about to write, iclass 17, count 0 2006.173.10:32:36.86#ibcon#wrote, iclass 17, count 0 2006.173.10:32:36.86#ibcon#about to read 3, iclass 17, count 0 2006.173.10:32:36.89#ibcon#read 3, iclass 17, count 0 2006.173.10:32:36.89#ibcon#about to read 4, iclass 17, count 0 2006.173.10:32:36.89#ibcon#read 4, iclass 17, count 0 2006.173.10:32:36.89#ibcon#about to read 5, iclass 17, count 0 2006.173.10:32:36.89#ibcon#read 5, iclass 17, count 0 2006.173.10:32:36.89#ibcon#about to read 6, iclass 17, count 0 2006.173.10:32:36.89#ibcon#read 6, iclass 17, count 0 2006.173.10:32:36.89#ibcon#end of sib2, iclass 17, count 0 2006.173.10:32:36.89#ibcon#*after write, iclass 17, count 0 2006.173.10:32:36.89#ibcon#*before return 0, iclass 17, count 0 2006.173.10:32:36.89#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.10:32:36.89#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.10:32:36.89#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.10:32:36.89#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.10:32:36.89$vck44/vblo=1,629.99 2006.173.10:32:36.89#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.10:32:36.89#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.10:32:36.89#ibcon#ireg 17 cls_cnt 0 2006.173.10:32:36.89#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.10:32:36.89#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.10:32:36.89#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.10:32:36.89#ibcon#enter wrdev, iclass 19, count 0 2006.173.10:32:36.89#ibcon#first serial, iclass 19, count 0 2006.173.10:32:36.89#ibcon#enter sib2, iclass 19, count 0 2006.173.10:32:36.89#ibcon#flushed, iclass 19, count 0 2006.173.10:32:36.89#ibcon#about to write, iclass 19, count 0 2006.173.10:32:36.89#ibcon#wrote, iclass 19, count 0 2006.173.10:32:36.89#ibcon#about to read 3, iclass 19, count 0 2006.173.10:32:36.91#ibcon#read 3, iclass 19, count 0 2006.173.10:32:36.91#ibcon#about to read 4, iclass 19, count 0 2006.173.10:32:36.91#ibcon#read 4, iclass 19, count 0 2006.173.10:32:36.91#ibcon#about to read 5, iclass 19, count 0 2006.173.10:32:36.91#ibcon#read 5, iclass 19, count 0 2006.173.10:32:36.91#ibcon#about to read 6, iclass 19, count 0 2006.173.10:32:36.91#ibcon#read 6, iclass 19, count 0 2006.173.10:32:36.91#ibcon#end of sib2, iclass 19, count 0 2006.173.10:32:36.91#ibcon#*mode == 0, iclass 19, count 0 2006.173.10:32:36.91#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.10:32:36.91#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.10:32:36.91#ibcon#*before write, iclass 19, count 0 2006.173.10:32:36.91#ibcon#enter sib2, iclass 19, count 0 2006.173.10:32:36.91#ibcon#flushed, iclass 19, count 0 2006.173.10:32:36.91#ibcon#about to write, iclass 19, count 0 2006.173.10:32:36.91#ibcon#wrote, iclass 19, count 0 2006.173.10:32:36.91#ibcon#about to read 3, iclass 19, count 0 2006.173.10:32:36.95#ibcon#read 3, iclass 19, count 0 2006.173.10:32:36.95#ibcon#about to read 4, iclass 19, count 0 2006.173.10:32:36.95#ibcon#read 4, iclass 19, count 0 2006.173.10:32:36.95#ibcon#about to read 5, iclass 19, count 0 2006.173.10:32:36.95#ibcon#read 5, iclass 19, count 0 2006.173.10:32:36.95#ibcon#about to read 6, iclass 19, count 0 2006.173.10:32:36.95#ibcon#read 6, iclass 19, count 0 2006.173.10:32:36.95#ibcon#end of sib2, iclass 19, count 0 2006.173.10:32:36.95#ibcon#*after write, iclass 19, count 0 2006.173.10:32:36.95#ibcon#*before return 0, iclass 19, count 0 2006.173.10:32:36.95#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.10:32:36.95#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.10:32:36.95#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.10:32:36.95#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.10:32:36.95$vck44/vb=1,4 2006.173.10:32:36.95#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.10:32:36.95#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.10:32:36.95#ibcon#ireg 11 cls_cnt 2 2006.173.10:32:36.95#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.10:32:36.95#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.10:32:36.95#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.10:32:36.95#ibcon#enter wrdev, iclass 21, count 2 2006.173.10:32:36.95#ibcon#first serial, iclass 21, count 2 2006.173.10:32:36.95#ibcon#enter sib2, iclass 21, count 2 2006.173.10:32:36.95#ibcon#flushed, iclass 21, count 2 2006.173.10:32:36.95#ibcon#about to write, iclass 21, count 2 2006.173.10:32:36.95#ibcon#wrote, iclass 21, count 2 2006.173.10:32:36.95#ibcon#about to read 3, iclass 21, count 2 2006.173.10:32:36.97#ibcon#read 3, iclass 21, count 2 2006.173.10:32:36.97#ibcon#about to read 4, iclass 21, count 2 2006.173.10:32:36.97#ibcon#read 4, iclass 21, count 2 2006.173.10:32:36.97#ibcon#about to read 5, iclass 21, count 2 2006.173.10:32:36.97#ibcon#read 5, iclass 21, count 2 2006.173.10:32:36.97#ibcon#about to read 6, iclass 21, count 2 2006.173.10:32:36.97#ibcon#read 6, iclass 21, count 2 2006.173.10:32:36.97#ibcon#end of sib2, iclass 21, count 2 2006.173.10:32:36.97#ibcon#*mode == 0, iclass 21, count 2 2006.173.10:32:36.97#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.10:32:36.97#ibcon#[27=AT01-04\r\n] 2006.173.10:32:36.97#ibcon#*before write, iclass 21, count 2 2006.173.10:32:36.97#ibcon#enter sib2, iclass 21, count 2 2006.173.10:32:36.97#ibcon#flushed, iclass 21, count 2 2006.173.10:32:36.97#ibcon#about to write, iclass 21, count 2 2006.173.10:32:36.97#ibcon#wrote, iclass 21, count 2 2006.173.10:32:36.97#ibcon#about to read 3, iclass 21, count 2 2006.173.10:32:37.00#ibcon#read 3, iclass 21, count 2 2006.173.10:32:37.00#ibcon#about to read 4, iclass 21, count 2 2006.173.10:32:37.00#ibcon#read 4, iclass 21, count 2 2006.173.10:32:37.00#ibcon#about to read 5, iclass 21, count 2 2006.173.10:32:37.00#ibcon#read 5, iclass 21, count 2 2006.173.10:32:37.00#ibcon#about to read 6, iclass 21, count 2 2006.173.10:32:37.00#ibcon#read 6, iclass 21, count 2 2006.173.10:32:37.00#ibcon#end of sib2, iclass 21, count 2 2006.173.10:32:37.00#ibcon#*after write, iclass 21, count 2 2006.173.10:32:37.00#ibcon#*before return 0, iclass 21, count 2 2006.173.10:32:37.00#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.10:32:37.00#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.10:32:37.00#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.10:32:37.00#ibcon#ireg 7 cls_cnt 0 2006.173.10:32:37.00#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.10:32:37.12#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.10:32:37.12#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.10:32:37.12#ibcon#enter wrdev, iclass 21, count 0 2006.173.10:32:37.12#ibcon#first serial, iclass 21, count 0 2006.173.10:32:37.12#ibcon#enter sib2, iclass 21, count 0 2006.173.10:32:37.12#ibcon#flushed, iclass 21, count 0 2006.173.10:32:37.12#ibcon#about to write, iclass 21, count 0 2006.173.10:32:37.12#ibcon#wrote, iclass 21, count 0 2006.173.10:32:37.12#ibcon#about to read 3, iclass 21, count 0 2006.173.10:32:37.14#ibcon#read 3, iclass 21, count 0 2006.173.10:32:37.14#ibcon#about to read 4, iclass 21, count 0 2006.173.10:32:37.14#ibcon#read 4, iclass 21, count 0 2006.173.10:32:37.14#ibcon#about to read 5, iclass 21, count 0 2006.173.10:32:37.14#ibcon#read 5, iclass 21, count 0 2006.173.10:32:37.14#ibcon#about to read 6, iclass 21, count 0 2006.173.10:32:37.14#ibcon#read 6, iclass 21, count 0 2006.173.10:32:37.14#ibcon#end of sib2, iclass 21, count 0 2006.173.10:32:37.14#ibcon#*mode == 0, iclass 21, count 0 2006.173.10:32:37.14#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.10:32:37.14#ibcon#[27=USB\r\n] 2006.173.10:32:37.14#ibcon#*before write, iclass 21, count 0 2006.173.10:32:37.14#ibcon#enter sib2, iclass 21, count 0 2006.173.10:32:37.14#ibcon#flushed, iclass 21, count 0 2006.173.10:32:37.14#ibcon#about to write, iclass 21, count 0 2006.173.10:32:37.14#ibcon#wrote, iclass 21, count 0 2006.173.10:32:37.14#ibcon#about to read 3, iclass 21, count 0 2006.173.10:32:37.17#ibcon#read 3, iclass 21, count 0 2006.173.10:32:37.17#ibcon#about to read 4, iclass 21, count 0 2006.173.10:32:37.17#ibcon#read 4, iclass 21, count 0 2006.173.10:32:37.17#ibcon#about to read 5, iclass 21, count 0 2006.173.10:32:37.17#ibcon#read 5, iclass 21, count 0 2006.173.10:32:37.17#ibcon#about to read 6, iclass 21, count 0 2006.173.10:32:37.17#ibcon#read 6, iclass 21, count 0 2006.173.10:32:37.17#ibcon#end of sib2, iclass 21, count 0 2006.173.10:32:37.17#ibcon#*after write, iclass 21, count 0 2006.173.10:32:37.17#ibcon#*before return 0, iclass 21, count 0 2006.173.10:32:37.17#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.10:32:37.17#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.10:32:37.17#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.10:32:37.17#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.10:32:37.17$vck44/vblo=2,634.99 2006.173.10:32:37.17#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.10:32:37.17#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.10:32:37.17#ibcon#ireg 17 cls_cnt 0 2006.173.10:32:37.17#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.10:32:37.17#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.10:32:37.17#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.10:32:37.17#ibcon#enter wrdev, iclass 23, count 0 2006.173.10:32:37.17#ibcon#first serial, iclass 23, count 0 2006.173.10:32:37.17#ibcon#enter sib2, iclass 23, count 0 2006.173.10:32:37.17#ibcon#flushed, iclass 23, count 0 2006.173.10:32:37.17#ibcon#about to write, iclass 23, count 0 2006.173.10:32:37.17#ibcon#wrote, iclass 23, count 0 2006.173.10:32:37.17#ibcon#about to read 3, iclass 23, count 0 2006.173.10:32:37.19#ibcon#read 3, iclass 23, count 0 2006.173.10:32:37.19#ibcon#about to read 4, iclass 23, count 0 2006.173.10:32:37.19#ibcon#read 4, iclass 23, count 0 2006.173.10:32:37.19#ibcon#about to read 5, iclass 23, count 0 2006.173.10:32:37.19#ibcon#read 5, iclass 23, count 0 2006.173.10:32:37.19#ibcon#about to read 6, iclass 23, count 0 2006.173.10:32:37.19#ibcon#read 6, iclass 23, count 0 2006.173.10:32:37.19#ibcon#end of sib2, iclass 23, count 0 2006.173.10:32:37.19#ibcon#*mode == 0, iclass 23, count 0 2006.173.10:32:37.19#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.10:32:37.19#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.10:32:37.19#ibcon#*before write, iclass 23, count 0 2006.173.10:32:37.19#ibcon#enter sib2, iclass 23, count 0 2006.173.10:32:37.19#ibcon#flushed, iclass 23, count 0 2006.173.10:32:37.19#ibcon#about to write, iclass 23, count 0 2006.173.10:32:37.19#ibcon#wrote, iclass 23, count 0 2006.173.10:32:37.19#ibcon#about to read 3, iclass 23, count 0 2006.173.10:32:37.23#ibcon#read 3, iclass 23, count 0 2006.173.10:32:37.23#ibcon#about to read 4, iclass 23, count 0 2006.173.10:32:37.23#ibcon#read 4, iclass 23, count 0 2006.173.10:32:37.23#ibcon#about to read 5, iclass 23, count 0 2006.173.10:32:37.23#ibcon#read 5, iclass 23, count 0 2006.173.10:32:37.23#ibcon#about to read 6, iclass 23, count 0 2006.173.10:32:37.23#ibcon#read 6, iclass 23, count 0 2006.173.10:32:37.23#ibcon#end of sib2, iclass 23, count 0 2006.173.10:32:37.23#ibcon#*after write, iclass 23, count 0 2006.173.10:32:37.23#ibcon#*before return 0, iclass 23, count 0 2006.173.10:32:37.23#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.10:32:37.23#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.10:32:37.23#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.10:32:37.23#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.10:32:37.23$vck44/vb=2,4 2006.173.10:32:37.23#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.10:32:37.23#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.10:32:37.23#ibcon#ireg 11 cls_cnt 2 2006.173.10:32:37.23#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.10:32:37.29#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.10:32:37.29#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.10:32:37.29#ibcon#enter wrdev, iclass 25, count 2 2006.173.10:32:37.29#ibcon#first serial, iclass 25, count 2 2006.173.10:32:37.29#ibcon#enter sib2, iclass 25, count 2 2006.173.10:32:37.29#ibcon#flushed, iclass 25, count 2 2006.173.10:32:37.29#ibcon#about to write, iclass 25, count 2 2006.173.10:32:37.29#ibcon#wrote, iclass 25, count 2 2006.173.10:32:37.29#ibcon#about to read 3, iclass 25, count 2 2006.173.10:32:37.31#ibcon#read 3, iclass 25, count 2 2006.173.10:32:37.31#ibcon#about to read 4, iclass 25, count 2 2006.173.10:32:37.31#ibcon#read 4, iclass 25, count 2 2006.173.10:32:37.31#ibcon#about to read 5, iclass 25, count 2 2006.173.10:32:37.31#ibcon#read 5, iclass 25, count 2 2006.173.10:32:37.31#ibcon#about to read 6, iclass 25, count 2 2006.173.10:32:37.31#ibcon#read 6, iclass 25, count 2 2006.173.10:32:37.31#ibcon#end of sib2, iclass 25, count 2 2006.173.10:32:37.31#ibcon#*mode == 0, iclass 25, count 2 2006.173.10:32:37.31#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.10:32:37.31#ibcon#[27=AT02-04\r\n] 2006.173.10:32:37.31#ibcon#*before write, iclass 25, count 2 2006.173.10:32:37.31#ibcon#enter sib2, iclass 25, count 2 2006.173.10:32:37.31#ibcon#flushed, iclass 25, count 2 2006.173.10:32:37.31#ibcon#about to write, iclass 25, count 2 2006.173.10:32:37.31#ibcon#wrote, iclass 25, count 2 2006.173.10:32:37.31#ibcon#about to read 3, iclass 25, count 2 2006.173.10:32:37.34#ibcon#read 3, iclass 25, count 2 2006.173.10:32:37.34#ibcon#about to read 4, iclass 25, count 2 2006.173.10:32:37.34#ibcon#read 4, iclass 25, count 2 2006.173.10:32:37.34#ibcon#about to read 5, iclass 25, count 2 2006.173.10:32:37.34#ibcon#read 5, iclass 25, count 2 2006.173.10:32:37.34#ibcon#about to read 6, iclass 25, count 2 2006.173.10:32:37.34#ibcon#read 6, iclass 25, count 2 2006.173.10:32:37.34#ibcon#end of sib2, iclass 25, count 2 2006.173.10:32:37.34#ibcon#*after write, iclass 25, count 2 2006.173.10:32:37.34#ibcon#*before return 0, iclass 25, count 2 2006.173.10:32:37.34#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.10:32:37.34#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.10:32:37.34#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.10:32:37.34#ibcon#ireg 7 cls_cnt 0 2006.173.10:32:37.34#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.10:32:37.46#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.10:32:37.46#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.10:32:37.46#ibcon#enter wrdev, iclass 25, count 0 2006.173.10:32:37.46#ibcon#first serial, iclass 25, count 0 2006.173.10:32:37.46#ibcon#enter sib2, iclass 25, count 0 2006.173.10:32:37.46#ibcon#flushed, iclass 25, count 0 2006.173.10:32:37.46#ibcon#about to write, iclass 25, count 0 2006.173.10:32:37.46#ibcon#wrote, iclass 25, count 0 2006.173.10:32:37.46#ibcon#about to read 3, iclass 25, count 0 2006.173.10:32:37.48#ibcon#read 3, iclass 25, count 0 2006.173.10:32:37.48#ibcon#about to read 4, iclass 25, count 0 2006.173.10:32:37.48#ibcon#read 4, iclass 25, count 0 2006.173.10:32:37.48#ibcon#about to read 5, iclass 25, count 0 2006.173.10:32:37.48#ibcon#read 5, iclass 25, count 0 2006.173.10:32:37.48#ibcon#about to read 6, iclass 25, count 0 2006.173.10:32:37.48#ibcon#read 6, iclass 25, count 0 2006.173.10:32:37.48#ibcon#end of sib2, iclass 25, count 0 2006.173.10:32:37.48#ibcon#*mode == 0, iclass 25, count 0 2006.173.10:32:37.48#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.10:32:37.48#ibcon#[27=USB\r\n] 2006.173.10:32:37.48#ibcon#*before write, iclass 25, count 0 2006.173.10:32:37.48#ibcon#enter sib2, iclass 25, count 0 2006.173.10:32:37.48#ibcon#flushed, iclass 25, count 0 2006.173.10:32:37.48#ibcon#about to write, iclass 25, count 0 2006.173.10:32:37.48#ibcon#wrote, iclass 25, count 0 2006.173.10:32:37.48#ibcon#about to read 3, iclass 25, count 0 2006.173.10:32:37.51#ibcon#read 3, iclass 25, count 0 2006.173.10:32:37.51#ibcon#about to read 4, iclass 25, count 0 2006.173.10:32:37.51#ibcon#read 4, iclass 25, count 0 2006.173.10:32:37.51#ibcon#about to read 5, iclass 25, count 0 2006.173.10:32:37.51#ibcon#read 5, iclass 25, count 0 2006.173.10:32:37.51#ibcon#about to read 6, iclass 25, count 0 2006.173.10:32:37.51#ibcon#read 6, iclass 25, count 0 2006.173.10:32:37.51#ibcon#end of sib2, iclass 25, count 0 2006.173.10:32:37.51#ibcon#*after write, iclass 25, count 0 2006.173.10:32:37.51#ibcon#*before return 0, iclass 25, count 0 2006.173.10:32:37.51#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.10:32:37.51#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.10:32:37.51#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.10:32:37.51#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.10:32:37.51$vck44/vblo=3,649.99 2006.173.10:32:37.51#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.10:32:37.51#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.10:32:37.51#ibcon#ireg 17 cls_cnt 0 2006.173.10:32:37.51#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.10:32:37.51#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.10:32:37.51#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.10:32:37.51#ibcon#enter wrdev, iclass 27, count 0 2006.173.10:32:37.51#ibcon#first serial, iclass 27, count 0 2006.173.10:32:37.51#ibcon#enter sib2, iclass 27, count 0 2006.173.10:32:37.51#ibcon#flushed, iclass 27, count 0 2006.173.10:32:37.51#ibcon#about to write, iclass 27, count 0 2006.173.10:32:37.51#ibcon#wrote, iclass 27, count 0 2006.173.10:32:37.51#ibcon#about to read 3, iclass 27, count 0 2006.173.10:32:37.53#ibcon#read 3, iclass 27, count 0 2006.173.10:32:37.53#ibcon#about to read 4, iclass 27, count 0 2006.173.10:32:37.53#ibcon#read 4, iclass 27, count 0 2006.173.10:32:37.53#ibcon#about to read 5, iclass 27, count 0 2006.173.10:32:37.53#ibcon#read 5, iclass 27, count 0 2006.173.10:32:37.53#ibcon#about to read 6, iclass 27, count 0 2006.173.10:32:37.53#ibcon#read 6, iclass 27, count 0 2006.173.10:32:37.53#ibcon#end of sib2, iclass 27, count 0 2006.173.10:32:37.53#ibcon#*mode == 0, iclass 27, count 0 2006.173.10:32:37.53#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.10:32:37.53#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.10:32:37.53#ibcon#*before write, iclass 27, count 0 2006.173.10:32:37.53#ibcon#enter sib2, iclass 27, count 0 2006.173.10:32:37.53#ibcon#flushed, iclass 27, count 0 2006.173.10:32:37.53#ibcon#about to write, iclass 27, count 0 2006.173.10:32:37.53#ibcon#wrote, iclass 27, count 0 2006.173.10:32:37.53#ibcon#about to read 3, iclass 27, count 0 2006.173.10:32:37.57#ibcon#read 3, iclass 27, count 0 2006.173.10:32:37.57#ibcon#about to read 4, iclass 27, count 0 2006.173.10:32:37.57#ibcon#read 4, iclass 27, count 0 2006.173.10:32:37.57#ibcon#about to read 5, iclass 27, count 0 2006.173.10:32:37.57#ibcon#read 5, iclass 27, count 0 2006.173.10:32:37.57#ibcon#about to read 6, iclass 27, count 0 2006.173.10:32:37.57#ibcon#read 6, iclass 27, count 0 2006.173.10:32:37.57#ibcon#end of sib2, iclass 27, count 0 2006.173.10:32:37.57#ibcon#*after write, iclass 27, count 0 2006.173.10:32:37.57#ibcon#*before return 0, iclass 27, count 0 2006.173.10:32:37.57#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.10:32:37.57#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.10:32:37.57#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.10:32:37.57#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.10:32:37.57$vck44/vb=3,4 2006.173.10:32:37.57#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.10:32:37.57#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.10:32:37.57#ibcon#ireg 11 cls_cnt 2 2006.173.10:32:37.57#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.10:32:37.63#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.10:32:37.63#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.10:32:37.63#ibcon#enter wrdev, iclass 29, count 2 2006.173.10:32:37.63#ibcon#first serial, iclass 29, count 2 2006.173.10:32:37.63#ibcon#enter sib2, iclass 29, count 2 2006.173.10:32:37.63#ibcon#flushed, iclass 29, count 2 2006.173.10:32:37.63#ibcon#about to write, iclass 29, count 2 2006.173.10:32:37.63#ibcon#wrote, iclass 29, count 2 2006.173.10:32:37.63#ibcon#about to read 3, iclass 29, count 2 2006.173.10:32:37.65#ibcon#read 3, iclass 29, count 2 2006.173.10:32:37.65#ibcon#about to read 4, iclass 29, count 2 2006.173.10:32:37.65#ibcon#read 4, iclass 29, count 2 2006.173.10:32:37.65#ibcon#about to read 5, iclass 29, count 2 2006.173.10:32:37.65#ibcon#read 5, iclass 29, count 2 2006.173.10:32:37.65#ibcon#about to read 6, iclass 29, count 2 2006.173.10:32:37.65#ibcon#read 6, iclass 29, count 2 2006.173.10:32:37.65#ibcon#end of sib2, iclass 29, count 2 2006.173.10:32:37.65#ibcon#*mode == 0, iclass 29, count 2 2006.173.10:32:37.65#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.10:32:37.65#ibcon#[27=AT03-04\r\n] 2006.173.10:32:37.65#ibcon#*before write, iclass 29, count 2 2006.173.10:32:37.65#ibcon#enter sib2, iclass 29, count 2 2006.173.10:32:37.65#ibcon#flushed, iclass 29, count 2 2006.173.10:32:37.65#ibcon#about to write, iclass 29, count 2 2006.173.10:32:37.65#ibcon#wrote, iclass 29, count 2 2006.173.10:32:37.65#ibcon#about to read 3, iclass 29, count 2 2006.173.10:32:37.68#ibcon#read 3, iclass 29, count 2 2006.173.10:32:37.68#ibcon#about to read 4, iclass 29, count 2 2006.173.10:32:37.68#ibcon#read 4, iclass 29, count 2 2006.173.10:32:37.68#ibcon#about to read 5, iclass 29, count 2 2006.173.10:32:37.68#ibcon#read 5, iclass 29, count 2 2006.173.10:32:37.68#ibcon#about to read 6, iclass 29, count 2 2006.173.10:32:37.68#ibcon#read 6, iclass 29, count 2 2006.173.10:32:37.68#ibcon#end of sib2, iclass 29, count 2 2006.173.10:32:37.68#ibcon#*after write, iclass 29, count 2 2006.173.10:32:37.68#ibcon#*before return 0, iclass 29, count 2 2006.173.10:32:37.68#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.10:32:37.68#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.10:32:37.68#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.10:32:37.68#ibcon#ireg 7 cls_cnt 0 2006.173.10:32:37.68#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.10:32:37.80#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.10:32:37.80#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.10:32:37.80#ibcon#enter wrdev, iclass 29, count 0 2006.173.10:32:37.80#ibcon#first serial, iclass 29, count 0 2006.173.10:32:37.80#ibcon#enter sib2, iclass 29, count 0 2006.173.10:32:37.80#ibcon#flushed, iclass 29, count 0 2006.173.10:32:37.80#ibcon#about to write, iclass 29, count 0 2006.173.10:32:37.80#ibcon#wrote, iclass 29, count 0 2006.173.10:32:37.80#ibcon#about to read 3, iclass 29, count 0 2006.173.10:32:37.82#ibcon#read 3, iclass 29, count 0 2006.173.10:32:37.82#ibcon#about to read 4, iclass 29, count 0 2006.173.10:32:37.82#ibcon#read 4, iclass 29, count 0 2006.173.10:32:37.82#ibcon#about to read 5, iclass 29, count 0 2006.173.10:32:37.82#ibcon#read 5, iclass 29, count 0 2006.173.10:32:37.82#ibcon#about to read 6, iclass 29, count 0 2006.173.10:32:37.82#ibcon#read 6, iclass 29, count 0 2006.173.10:32:37.82#ibcon#end of sib2, iclass 29, count 0 2006.173.10:32:37.82#ibcon#*mode == 0, iclass 29, count 0 2006.173.10:32:37.82#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.10:32:37.82#ibcon#[27=USB\r\n] 2006.173.10:32:37.82#ibcon#*before write, iclass 29, count 0 2006.173.10:32:37.82#ibcon#enter sib2, iclass 29, count 0 2006.173.10:32:37.82#ibcon#flushed, iclass 29, count 0 2006.173.10:32:37.82#ibcon#about to write, iclass 29, count 0 2006.173.10:32:37.82#ibcon#wrote, iclass 29, count 0 2006.173.10:32:37.82#ibcon#about to read 3, iclass 29, count 0 2006.173.10:32:37.85#ibcon#read 3, iclass 29, count 0 2006.173.10:32:37.85#ibcon#about to read 4, iclass 29, count 0 2006.173.10:32:37.85#ibcon#read 4, iclass 29, count 0 2006.173.10:32:37.85#ibcon#about to read 5, iclass 29, count 0 2006.173.10:32:37.85#ibcon#read 5, iclass 29, count 0 2006.173.10:32:37.85#ibcon#about to read 6, iclass 29, count 0 2006.173.10:32:37.85#ibcon#read 6, iclass 29, count 0 2006.173.10:32:37.85#ibcon#end of sib2, iclass 29, count 0 2006.173.10:32:37.85#ibcon#*after write, iclass 29, count 0 2006.173.10:32:37.85#ibcon#*before return 0, iclass 29, count 0 2006.173.10:32:37.85#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.10:32:37.85#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.10:32:37.85#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.10:32:37.85#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.10:32:37.85$vck44/vblo=4,679.99 2006.173.10:32:37.85#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.10:32:37.85#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.10:32:37.85#ibcon#ireg 17 cls_cnt 0 2006.173.10:32:37.85#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.10:32:37.85#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.10:32:37.85#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.10:32:37.85#ibcon#enter wrdev, iclass 31, count 0 2006.173.10:32:37.85#ibcon#first serial, iclass 31, count 0 2006.173.10:32:37.85#ibcon#enter sib2, iclass 31, count 0 2006.173.10:32:37.85#ibcon#flushed, iclass 31, count 0 2006.173.10:32:37.85#ibcon#about to write, iclass 31, count 0 2006.173.10:32:37.85#ibcon#wrote, iclass 31, count 0 2006.173.10:32:37.85#ibcon#about to read 3, iclass 31, count 0 2006.173.10:32:37.87#ibcon#read 3, iclass 31, count 0 2006.173.10:32:37.87#ibcon#about to read 4, iclass 31, count 0 2006.173.10:32:37.87#ibcon#read 4, iclass 31, count 0 2006.173.10:32:37.87#ibcon#about to read 5, iclass 31, count 0 2006.173.10:32:37.87#ibcon#read 5, iclass 31, count 0 2006.173.10:32:37.87#ibcon#about to read 6, iclass 31, count 0 2006.173.10:32:37.87#ibcon#read 6, iclass 31, count 0 2006.173.10:32:37.87#ibcon#end of sib2, iclass 31, count 0 2006.173.10:32:37.87#ibcon#*mode == 0, iclass 31, count 0 2006.173.10:32:37.87#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.10:32:37.87#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.10:32:37.87#ibcon#*before write, iclass 31, count 0 2006.173.10:32:37.87#ibcon#enter sib2, iclass 31, count 0 2006.173.10:32:37.87#ibcon#flushed, iclass 31, count 0 2006.173.10:32:37.87#ibcon#about to write, iclass 31, count 0 2006.173.10:32:37.87#ibcon#wrote, iclass 31, count 0 2006.173.10:32:37.87#ibcon#about to read 3, iclass 31, count 0 2006.173.10:32:37.91#ibcon#read 3, iclass 31, count 0 2006.173.10:32:37.91#ibcon#about to read 4, iclass 31, count 0 2006.173.10:32:37.91#ibcon#read 4, iclass 31, count 0 2006.173.10:32:37.91#ibcon#about to read 5, iclass 31, count 0 2006.173.10:32:37.91#ibcon#read 5, iclass 31, count 0 2006.173.10:32:37.91#ibcon#about to read 6, iclass 31, count 0 2006.173.10:32:37.91#ibcon#read 6, iclass 31, count 0 2006.173.10:32:37.91#ibcon#end of sib2, iclass 31, count 0 2006.173.10:32:37.91#ibcon#*after write, iclass 31, count 0 2006.173.10:32:37.91#ibcon#*before return 0, iclass 31, count 0 2006.173.10:32:37.91#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.10:32:37.91#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.10:32:37.91#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.10:32:37.91#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.10:32:37.91$vck44/vb=4,4 2006.173.10:32:37.91#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.173.10:32:37.91#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.173.10:32:37.91#ibcon#ireg 11 cls_cnt 2 2006.173.10:32:37.91#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.10:32:37.97#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.10:32:37.97#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.10:32:37.97#ibcon#enter wrdev, iclass 33, count 2 2006.173.10:32:37.97#ibcon#first serial, iclass 33, count 2 2006.173.10:32:37.97#ibcon#enter sib2, iclass 33, count 2 2006.173.10:32:37.97#ibcon#flushed, iclass 33, count 2 2006.173.10:32:37.97#ibcon#about to write, iclass 33, count 2 2006.173.10:32:37.97#ibcon#wrote, iclass 33, count 2 2006.173.10:32:37.97#ibcon#about to read 3, iclass 33, count 2 2006.173.10:32:37.99#ibcon#read 3, iclass 33, count 2 2006.173.10:32:37.99#ibcon#about to read 4, iclass 33, count 2 2006.173.10:32:37.99#ibcon#read 4, iclass 33, count 2 2006.173.10:32:37.99#ibcon#about to read 5, iclass 33, count 2 2006.173.10:32:37.99#ibcon#read 5, iclass 33, count 2 2006.173.10:32:37.99#ibcon#about to read 6, iclass 33, count 2 2006.173.10:32:37.99#ibcon#read 6, iclass 33, count 2 2006.173.10:32:37.99#ibcon#end of sib2, iclass 33, count 2 2006.173.10:32:37.99#ibcon#*mode == 0, iclass 33, count 2 2006.173.10:32:37.99#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.173.10:32:37.99#ibcon#[27=AT04-04\r\n] 2006.173.10:32:37.99#ibcon#*before write, iclass 33, count 2 2006.173.10:32:37.99#ibcon#enter sib2, iclass 33, count 2 2006.173.10:32:37.99#ibcon#flushed, iclass 33, count 2 2006.173.10:32:37.99#ibcon#about to write, iclass 33, count 2 2006.173.10:32:37.99#ibcon#wrote, iclass 33, count 2 2006.173.10:32:37.99#ibcon#about to read 3, iclass 33, count 2 2006.173.10:32:38.02#ibcon#read 3, iclass 33, count 2 2006.173.10:32:38.02#ibcon#about to read 4, iclass 33, count 2 2006.173.10:32:38.02#ibcon#read 4, iclass 33, count 2 2006.173.10:32:38.02#ibcon#about to read 5, iclass 33, count 2 2006.173.10:32:38.02#ibcon#read 5, iclass 33, count 2 2006.173.10:32:38.02#ibcon#about to read 6, iclass 33, count 2 2006.173.10:32:38.02#ibcon#read 6, iclass 33, count 2 2006.173.10:32:38.02#ibcon#end of sib2, iclass 33, count 2 2006.173.10:32:38.02#ibcon#*after write, iclass 33, count 2 2006.173.10:32:38.02#ibcon#*before return 0, iclass 33, count 2 2006.173.10:32:38.02#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.10:32:38.02#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.173.10:32:38.02#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.173.10:32:38.02#ibcon#ireg 7 cls_cnt 0 2006.173.10:32:38.02#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.10:32:38.14#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.10:32:38.14#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.10:32:38.14#ibcon#enter wrdev, iclass 33, count 0 2006.173.10:32:38.14#ibcon#first serial, iclass 33, count 0 2006.173.10:32:38.14#ibcon#enter sib2, iclass 33, count 0 2006.173.10:32:38.14#ibcon#flushed, iclass 33, count 0 2006.173.10:32:38.14#ibcon#about to write, iclass 33, count 0 2006.173.10:32:38.14#ibcon#wrote, iclass 33, count 0 2006.173.10:32:38.14#ibcon#about to read 3, iclass 33, count 0 2006.173.10:32:38.16#ibcon#read 3, iclass 33, count 0 2006.173.10:32:38.16#ibcon#about to read 4, iclass 33, count 0 2006.173.10:32:38.16#ibcon#read 4, iclass 33, count 0 2006.173.10:32:38.16#ibcon#about to read 5, iclass 33, count 0 2006.173.10:32:38.16#ibcon#read 5, iclass 33, count 0 2006.173.10:32:38.16#ibcon#about to read 6, iclass 33, count 0 2006.173.10:32:38.16#ibcon#read 6, iclass 33, count 0 2006.173.10:32:38.16#ibcon#end of sib2, iclass 33, count 0 2006.173.10:32:38.16#ibcon#*mode == 0, iclass 33, count 0 2006.173.10:32:38.16#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.10:32:38.16#ibcon#[27=USB\r\n] 2006.173.10:32:38.16#ibcon#*before write, iclass 33, count 0 2006.173.10:32:38.16#ibcon#enter sib2, iclass 33, count 0 2006.173.10:32:38.16#ibcon#flushed, iclass 33, count 0 2006.173.10:32:38.16#ibcon#about to write, iclass 33, count 0 2006.173.10:32:38.16#ibcon#wrote, iclass 33, count 0 2006.173.10:32:38.16#ibcon#about to read 3, iclass 33, count 0 2006.173.10:32:38.19#ibcon#read 3, iclass 33, count 0 2006.173.10:32:38.19#ibcon#about to read 4, iclass 33, count 0 2006.173.10:32:38.19#ibcon#read 4, iclass 33, count 0 2006.173.10:32:38.19#ibcon#about to read 5, iclass 33, count 0 2006.173.10:32:38.19#ibcon#read 5, iclass 33, count 0 2006.173.10:32:38.19#ibcon#about to read 6, iclass 33, count 0 2006.173.10:32:38.19#ibcon#read 6, iclass 33, count 0 2006.173.10:32:38.19#ibcon#end of sib2, iclass 33, count 0 2006.173.10:32:38.19#ibcon#*after write, iclass 33, count 0 2006.173.10:32:38.19#ibcon#*before return 0, iclass 33, count 0 2006.173.10:32:38.19#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.10:32:38.19#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.173.10:32:38.19#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.10:32:38.19#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.10:32:38.19$vck44/vblo=5,709.99 2006.173.10:32:38.19#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.10:32:38.19#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.10:32:38.19#ibcon#ireg 17 cls_cnt 0 2006.173.10:32:38.19#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.10:32:38.19#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.10:32:38.19#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.10:32:38.19#ibcon#enter wrdev, iclass 35, count 0 2006.173.10:32:38.19#ibcon#first serial, iclass 35, count 0 2006.173.10:32:38.19#ibcon#enter sib2, iclass 35, count 0 2006.173.10:32:38.19#ibcon#flushed, iclass 35, count 0 2006.173.10:32:38.19#ibcon#about to write, iclass 35, count 0 2006.173.10:32:38.19#ibcon#wrote, iclass 35, count 0 2006.173.10:32:38.19#ibcon#about to read 3, iclass 35, count 0 2006.173.10:32:38.21#ibcon#read 3, iclass 35, count 0 2006.173.10:32:38.21#ibcon#about to read 4, iclass 35, count 0 2006.173.10:32:38.21#ibcon#read 4, iclass 35, count 0 2006.173.10:32:38.21#ibcon#about to read 5, iclass 35, count 0 2006.173.10:32:38.21#ibcon#read 5, iclass 35, count 0 2006.173.10:32:38.21#ibcon#about to read 6, iclass 35, count 0 2006.173.10:32:38.21#ibcon#read 6, iclass 35, count 0 2006.173.10:32:38.21#ibcon#end of sib2, iclass 35, count 0 2006.173.10:32:38.21#ibcon#*mode == 0, iclass 35, count 0 2006.173.10:32:38.21#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.10:32:38.21#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.10:32:38.21#ibcon#*before write, iclass 35, count 0 2006.173.10:32:38.21#ibcon#enter sib2, iclass 35, count 0 2006.173.10:32:38.21#ibcon#flushed, iclass 35, count 0 2006.173.10:32:38.21#ibcon#about to write, iclass 35, count 0 2006.173.10:32:38.21#ibcon#wrote, iclass 35, count 0 2006.173.10:32:38.21#ibcon#about to read 3, iclass 35, count 0 2006.173.10:32:38.25#ibcon#read 3, iclass 35, count 0 2006.173.10:32:38.25#ibcon#about to read 4, iclass 35, count 0 2006.173.10:32:38.25#ibcon#read 4, iclass 35, count 0 2006.173.10:32:38.25#ibcon#about to read 5, iclass 35, count 0 2006.173.10:32:38.25#ibcon#read 5, iclass 35, count 0 2006.173.10:32:38.25#ibcon#about to read 6, iclass 35, count 0 2006.173.10:32:38.25#ibcon#read 6, iclass 35, count 0 2006.173.10:32:38.25#ibcon#end of sib2, iclass 35, count 0 2006.173.10:32:38.25#ibcon#*after write, iclass 35, count 0 2006.173.10:32:38.25#ibcon#*before return 0, iclass 35, count 0 2006.173.10:32:38.25#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.10:32:38.25#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.10:32:38.25#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.10:32:38.25#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.10:32:38.25$vck44/vb=5,4 2006.173.10:32:38.25#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.173.10:32:38.25#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.173.10:32:38.25#ibcon#ireg 11 cls_cnt 2 2006.173.10:32:38.25#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.10:32:38.31#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.10:32:38.31#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.10:32:38.31#ibcon#enter wrdev, iclass 37, count 2 2006.173.10:32:38.31#ibcon#first serial, iclass 37, count 2 2006.173.10:32:38.31#ibcon#enter sib2, iclass 37, count 2 2006.173.10:32:38.31#ibcon#flushed, iclass 37, count 2 2006.173.10:32:38.31#ibcon#about to write, iclass 37, count 2 2006.173.10:32:38.31#ibcon#wrote, iclass 37, count 2 2006.173.10:32:38.31#ibcon#about to read 3, iclass 37, count 2 2006.173.10:32:38.33#ibcon#read 3, iclass 37, count 2 2006.173.10:32:38.33#ibcon#about to read 4, iclass 37, count 2 2006.173.10:32:38.33#ibcon#read 4, iclass 37, count 2 2006.173.10:32:38.33#ibcon#about to read 5, iclass 37, count 2 2006.173.10:32:38.33#ibcon#read 5, iclass 37, count 2 2006.173.10:32:38.33#ibcon#about to read 6, iclass 37, count 2 2006.173.10:32:38.33#ibcon#read 6, iclass 37, count 2 2006.173.10:32:38.33#ibcon#end of sib2, iclass 37, count 2 2006.173.10:32:38.33#ibcon#*mode == 0, iclass 37, count 2 2006.173.10:32:38.33#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.173.10:32:38.33#ibcon#[27=AT05-04\r\n] 2006.173.10:32:38.33#ibcon#*before write, iclass 37, count 2 2006.173.10:32:38.33#ibcon#enter sib2, iclass 37, count 2 2006.173.10:32:38.33#ibcon#flushed, iclass 37, count 2 2006.173.10:32:38.33#ibcon#about to write, iclass 37, count 2 2006.173.10:32:38.33#ibcon#wrote, iclass 37, count 2 2006.173.10:32:38.33#ibcon#about to read 3, iclass 37, count 2 2006.173.10:32:38.36#ibcon#read 3, iclass 37, count 2 2006.173.10:32:38.36#ibcon#about to read 4, iclass 37, count 2 2006.173.10:32:38.36#ibcon#read 4, iclass 37, count 2 2006.173.10:32:38.36#ibcon#about to read 5, iclass 37, count 2 2006.173.10:32:38.36#ibcon#read 5, iclass 37, count 2 2006.173.10:32:38.36#ibcon#about to read 6, iclass 37, count 2 2006.173.10:32:38.36#ibcon#read 6, iclass 37, count 2 2006.173.10:32:38.36#ibcon#end of sib2, iclass 37, count 2 2006.173.10:32:38.36#ibcon#*after write, iclass 37, count 2 2006.173.10:32:38.36#ibcon#*before return 0, iclass 37, count 2 2006.173.10:32:38.36#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.10:32:38.36#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.173.10:32:38.36#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.173.10:32:38.36#ibcon#ireg 7 cls_cnt 0 2006.173.10:32:38.36#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.10:32:38.48#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.10:32:38.48#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.10:32:38.48#ibcon#enter wrdev, iclass 37, count 0 2006.173.10:32:38.48#ibcon#first serial, iclass 37, count 0 2006.173.10:32:38.48#ibcon#enter sib2, iclass 37, count 0 2006.173.10:32:38.48#ibcon#flushed, iclass 37, count 0 2006.173.10:32:38.48#ibcon#about to write, iclass 37, count 0 2006.173.10:32:38.48#ibcon#wrote, iclass 37, count 0 2006.173.10:32:38.48#ibcon#about to read 3, iclass 37, count 0 2006.173.10:32:38.50#ibcon#read 3, iclass 37, count 0 2006.173.10:32:38.50#ibcon#about to read 4, iclass 37, count 0 2006.173.10:32:38.50#ibcon#read 4, iclass 37, count 0 2006.173.10:32:38.50#ibcon#about to read 5, iclass 37, count 0 2006.173.10:32:38.50#ibcon#read 5, iclass 37, count 0 2006.173.10:32:38.50#ibcon#about to read 6, iclass 37, count 0 2006.173.10:32:38.50#ibcon#read 6, iclass 37, count 0 2006.173.10:32:38.50#ibcon#end of sib2, iclass 37, count 0 2006.173.10:32:38.50#ibcon#*mode == 0, iclass 37, count 0 2006.173.10:32:38.50#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.10:32:38.50#ibcon#[27=USB\r\n] 2006.173.10:32:38.50#ibcon#*before write, iclass 37, count 0 2006.173.10:32:38.50#ibcon#enter sib2, iclass 37, count 0 2006.173.10:32:38.50#ibcon#flushed, iclass 37, count 0 2006.173.10:32:38.50#ibcon#about to write, iclass 37, count 0 2006.173.10:32:38.50#ibcon#wrote, iclass 37, count 0 2006.173.10:32:38.50#ibcon#about to read 3, iclass 37, count 0 2006.173.10:32:38.53#ibcon#read 3, iclass 37, count 0 2006.173.10:32:38.53#ibcon#about to read 4, iclass 37, count 0 2006.173.10:32:38.53#ibcon#read 4, iclass 37, count 0 2006.173.10:32:38.53#ibcon#about to read 5, iclass 37, count 0 2006.173.10:32:38.53#ibcon#read 5, iclass 37, count 0 2006.173.10:32:38.53#ibcon#about to read 6, iclass 37, count 0 2006.173.10:32:38.53#ibcon#read 6, iclass 37, count 0 2006.173.10:32:38.53#ibcon#end of sib2, iclass 37, count 0 2006.173.10:32:38.53#ibcon#*after write, iclass 37, count 0 2006.173.10:32:38.53#ibcon#*before return 0, iclass 37, count 0 2006.173.10:32:38.53#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.10:32:38.53#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.173.10:32:38.53#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.10:32:38.53#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.10:32:38.53$vck44/vblo=6,719.99 2006.173.10:32:38.53#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.10:32:38.53#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.10:32:38.53#ibcon#ireg 17 cls_cnt 0 2006.173.10:32:38.53#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.10:32:38.53#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.10:32:38.53#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.10:32:38.53#ibcon#enter wrdev, iclass 39, count 0 2006.173.10:32:38.53#ibcon#first serial, iclass 39, count 0 2006.173.10:32:38.53#ibcon#enter sib2, iclass 39, count 0 2006.173.10:32:38.53#ibcon#flushed, iclass 39, count 0 2006.173.10:32:38.53#ibcon#about to write, iclass 39, count 0 2006.173.10:32:38.53#ibcon#wrote, iclass 39, count 0 2006.173.10:32:38.53#ibcon#about to read 3, iclass 39, count 0 2006.173.10:32:38.55#ibcon#read 3, iclass 39, count 0 2006.173.10:32:38.55#ibcon#about to read 4, iclass 39, count 0 2006.173.10:32:38.55#ibcon#read 4, iclass 39, count 0 2006.173.10:32:38.55#ibcon#about to read 5, iclass 39, count 0 2006.173.10:32:38.55#ibcon#read 5, iclass 39, count 0 2006.173.10:32:38.55#ibcon#about to read 6, iclass 39, count 0 2006.173.10:32:38.55#ibcon#read 6, iclass 39, count 0 2006.173.10:32:38.55#ibcon#end of sib2, iclass 39, count 0 2006.173.10:32:38.55#ibcon#*mode == 0, iclass 39, count 0 2006.173.10:32:38.55#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.10:32:38.55#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.10:32:38.55#ibcon#*before write, iclass 39, count 0 2006.173.10:32:38.55#ibcon#enter sib2, iclass 39, count 0 2006.173.10:32:38.55#ibcon#flushed, iclass 39, count 0 2006.173.10:32:38.55#ibcon#about to write, iclass 39, count 0 2006.173.10:32:38.55#ibcon#wrote, iclass 39, count 0 2006.173.10:32:38.55#ibcon#about to read 3, iclass 39, count 0 2006.173.10:32:38.59#ibcon#read 3, iclass 39, count 0 2006.173.10:32:38.59#ibcon#about to read 4, iclass 39, count 0 2006.173.10:32:38.59#ibcon#read 4, iclass 39, count 0 2006.173.10:32:38.59#ibcon#about to read 5, iclass 39, count 0 2006.173.10:32:38.59#ibcon#read 5, iclass 39, count 0 2006.173.10:32:38.59#ibcon#about to read 6, iclass 39, count 0 2006.173.10:32:38.59#ibcon#read 6, iclass 39, count 0 2006.173.10:32:38.59#ibcon#end of sib2, iclass 39, count 0 2006.173.10:32:38.59#ibcon#*after write, iclass 39, count 0 2006.173.10:32:38.59#ibcon#*before return 0, iclass 39, count 0 2006.173.10:32:38.59#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.10:32:38.59#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.10:32:38.59#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.10:32:38.59#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.10:32:38.59$vck44/vb=6,4 2006.173.10:32:38.59#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.10:32:38.59#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.10:32:38.59#ibcon#ireg 11 cls_cnt 2 2006.173.10:32:38.59#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.10:32:38.65#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.10:32:38.65#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.10:32:38.65#ibcon#enter wrdev, iclass 3, count 2 2006.173.10:32:38.65#ibcon#first serial, iclass 3, count 2 2006.173.10:32:38.65#ibcon#enter sib2, iclass 3, count 2 2006.173.10:32:38.65#ibcon#flushed, iclass 3, count 2 2006.173.10:32:38.65#ibcon#about to write, iclass 3, count 2 2006.173.10:32:38.65#ibcon#wrote, iclass 3, count 2 2006.173.10:32:38.65#ibcon#about to read 3, iclass 3, count 2 2006.173.10:32:38.67#ibcon#read 3, iclass 3, count 2 2006.173.10:32:38.67#ibcon#about to read 4, iclass 3, count 2 2006.173.10:32:38.67#ibcon#read 4, iclass 3, count 2 2006.173.10:32:38.67#ibcon#about to read 5, iclass 3, count 2 2006.173.10:32:38.67#ibcon#read 5, iclass 3, count 2 2006.173.10:32:38.67#ibcon#about to read 6, iclass 3, count 2 2006.173.10:32:38.67#ibcon#read 6, iclass 3, count 2 2006.173.10:32:38.67#ibcon#end of sib2, iclass 3, count 2 2006.173.10:32:38.67#ibcon#*mode == 0, iclass 3, count 2 2006.173.10:32:38.67#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.10:32:38.67#ibcon#[27=AT06-04\r\n] 2006.173.10:32:38.67#ibcon#*before write, iclass 3, count 2 2006.173.10:32:38.67#ibcon#enter sib2, iclass 3, count 2 2006.173.10:32:38.67#ibcon#flushed, iclass 3, count 2 2006.173.10:32:38.67#ibcon#about to write, iclass 3, count 2 2006.173.10:32:38.67#ibcon#wrote, iclass 3, count 2 2006.173.10:32:38.67#ibcon#about to read 3, iclass 3, count 2 2006.173.10:32:38.70#ibcon#read 3, iclass 3, count 2 2006.173.10:32:38.70#ibcon#about to read 4, iclass 3, count 2 2006.173.10:32:38.70#ibcon#read 4, iclass 3, count 2 2006.173.10:32:38.70#ibcon#about to read 5, iclass 3, count 2 2006.173.10:32:38.70#ibcon#read 5, iclass 3, count 2 2006.173.10:32:38.70#ibcon#about to read 6, iclass 3, count 2 2006.173.10:32:38.70#ibcon#read 6, iclass 3, count 2 2006.173.10:32:38.70#ibcon#end of sib2, iclass 3, count 2 2006.173.10:32:38.70#ibcon#*after write, iclass 3, count 2 2006.173.10:32:38.70#ibcon#*before return 0, iclass 3, count 2 2006.173.10:32:38.70#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.10:32:38.70#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.10:32:38.70#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.10:32:38.70#ibcon#ireg 7 cls_cnt 0 2006.173.10:32:38.70#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.10:32:38.82#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.10:32:38.82#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.10:32:38.82#ibcon#enter wrdev, iclass 3, count 0 2006.173.10:32:38.82#ibcon#first serial, iclass 3, count 0 2006.173.10:32:38.82#ibcon#enter sib2, iclass 3, count 0 2006.173.10:32:38.82#ibcon#flushed, iclass 3, count 0 2006.173.10:32:38.82#ibcon#about to write, iclass 3, count 0 2006.173.10:32:38.82#ibcon#wrote, iclass 3, count 0 2006.173.10:32:38.82#ibcon#about to read 3, iclass 3, count 0 2006.173.10:32:38.84#ibcon#read 3, iclass 3, count 0 2006.173.10:32:38.84#ibcon#about to read 4, iclass 3, count 0 2006.173.10:32:38.84#ibcon#read 4, iclass 3, count 0 2006.173.10:32:38.84#ibcon#about to read 5, iclass 3, count 0 2006.173.10:32:38.84#ibcon#read 5, iclass 3, count 0 2006.173.10:32:38.84#ibcon#about to read 6, iclass 3, count 0 2006.173.10:32:38.84#ibcon#read 6, iclass 3, count 0 2006.173.10:32:38.84#ibcon#end of sib2, iclass 3, count 0 2006.173.10:32:38.84#ibcon#*mode == 0, iclass 3, count 0 2006.173.10:32:38.84#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.10:32:38.84#ibcon#[27=USB\r\n] 2006.173.10:32:38.84#ibcon#*before write, iclass 3, count 0 2006.173.10:32:38.84#ibcon#enter sib2, iclass 3, count 0 2006.173.10:32:38.84#ibcon#flushed, iclass 3, count 0 2006.173.10:32:38.84#ibcon#about to write, iclass 3, count 0 2006.173.10:32:38.84#ibcon#wrote, iclass 3, count 0 2006.173.10:32:38.84#ibcon#about to read 3, iclass 3, count 0 2006.173.10:32:38.87#ibcon#read 3, iclass 3, count 0 2006.173.10:32:38.87#ibcon#about to read 4, iclass 3, count 0 2006.173.10:32:38.87#ibcon#read 4, iclass 3, count 0 2006.173.10:32:38.87#ibcon#about to read 5, iclass 3, count 0 2006.173.10:32:38.87#ibcon#read 5, iclass 3, count 0 2006.173.10:32:38.87#ibcon#about to read 6, iclass 3, count 0 2006.173.10:32:38.87#ibcon#read 6, iclass 3, count 0 2006.173.10:32:38.87#ibcon#end of sib2, iclass 3, count 0 2006.173.10:32:38.87#ibcon#*after write, iclass 3, count 0 2006.173.10:32:38.87#ibcon#*before return 0, iclass 3, count 0 2006.173.10:32:38.87#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.10:32:38.87#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.10:32:38.87#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.10:32:38.87#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.10:32:38.87$vck44/vblo=7,734.99 2006.173.10:32:38.87#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.10:32:38.87#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.10:32:38.87#ibcon#ireg 17 cls_cnt 0 2006.173.10:32:38.87#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.10:32:38.87#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.10:32:38.87#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.10:32:38.87#ibcon#enter wrdev, iclass 5, count 0 2006.173.10:32:38.87#ibcon#first serial, iclass 5, count 0 2006.173.10:32:38.87#ibcon#enter sib2, iclass 5, count 0 2006.173.10:32:38.87#ibcon#flushed, iclass 5, count 0 2006.173.10:32:38.87#ibcon#about to write, iclass 5, count 0 2006.173.10:32:38.87#ibcon#wrote, iclass 5, count 0 2006.173.10:32:38.87#ibcon#about to read 3, iclass 5, count 0 2006.173.10:32:38.89#ibcon#read 3, iclass 5, count 0 2006.173.10:32:38.89#ibcon#about to read 4, iclass 5, count 0 2006.173.10:32:38.89#ibcon#read 4, iclass 5, count 0 2006.173.10:32:38.89#ibcon#about to read 5, iclass 5, count 0 2006.173.10:32:38.89#ibcon#read 5, iclass 5, count 0 2006.173.10:32:38.89#ibcon#about to read 6, iclass 5, count 0 2006.173.10:32:38.89#ibcon#read 6, iclass 5, count 0 2006.173.10:32:38.89#ibcon#end of sib2, iclass 5, count 0 2006.173.10:32:38.89#ibcon#*mode == 0, iclass 5, count 0 2006.173.10:32:38.89#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.10:32:38.89#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.10:32:38.89#ibcon#*before write, iclass 5, count 0 2006.173.10:32:38.89#ibcon#enter sib2, iclass 5, count 0 2006.173.10:32:38.89#ibcon#flushed, iclass 5, count 0 2006.173.10:32:38.89#ibcon#about to write, iclass 5, count 0 2006.173.10:32:38.89#ibcon#wrote, iclass 5, count 0 2006.173.10:32:38.89#ibcon#about to read 3, iclass 5, count 0 2006.173.10:32:38.93#ibcon#read 3, iclass 5, count 0 2006.173.10:32:38.93#ibcon#about to read 4, iclass 5, count 0 2006.173.10:32:38.93#ibcon#read 4, iclass 5, count 0 2006.173.10:32:38.93#ibcon#about to read 5, iclass 5, count 0 2006.173.10:32:38.93#ibcon#read 5, iclass 5, count 0 2006.173.10:32:38.93#ibcon#about to read 6, iclass 5, count 0 2006.173.10:32:38.93#ibcon#read 6, iclass 5, count 0 2006.173.10:32:38.93#ibcon#end of sib2, iclass 5, count 0 2006.173.10:32:38.93#ibcon#*after write, iclass 5, count 0 2006.173.10:32:38.93#ibcon#*before return 0, iclass 5, count 0 2006.173.10:32:38.93#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.10:32:38.93#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.10:32:38.93#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.10:32:38.93#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.10:32:38.93$vck44/vb=7,4 2006.173.10:32:38.93#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.173.10:32:38.93#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.173.10:32:38.93#ibcon#ireg 11 cls_cnt 2 2006.173.10:32:38.93#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.10:32:38.99#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.10:32:38.99#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.10:32:38.99#ibcon#enter wrdev, iclass 7, count 2 2006.173.10:32:38.99#ibcon#first serial, iclass 7, count 2 2006.173.10:32:38.99#ibcon#enter sib2, iclass 7, count 2 2006.173.10:32:38.99#ibcon#flushed, iclass 7, count 2 2006.173.10:32:38.99#ibcon#about to write, iclass 7, count 2 2006.173.10:32:38.99#ibcon#wrote, iclass 7, count 2 2006.173.10:32:38.99#ibcon#about to read 3, iclass 7, count 2 2006.173.10:32:39.01#ibcon#read 3, iclass 7, count 2 2006.173.10:32:39.01#ibcon#about to read 4, iclass 7, count 2 2006.173.10:32:39.01#ibcon#read 4, iclass 7, count 2 2006.173.10:32:39.01#ibcon#about to read 5, iclass 7, count 2 2006.173.10:32:39.01#ibcon#read 5, iclass 7, count 2 2006.173.10:32:39.01#ibcon#about to read 6, iclass 7, count 2 2006.173.10:32:39.01#ibcon#read 6, iclass 7, count 2 2006.173.10:32:39.01#ibcon#end of sib2, iclass 7, count 2 2006.173.10:32:39.01#ibcon#*mode == 0, iclass 7, count 2 2006.173.10:32:39.01#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.173.10:32:39.01#ibcon#[27=AT07-04\r\n] 2006.173.10:32:39.01#ibcon#*before write, iclass 7, count 2 2006.173.10:32:39.01#ibcon#enter sib2, iclass 7, count 2 2006.173.10:32:39.01#ibcon#flushed, iclass 7, count 2 2006.173.10:32:39.01#ibcon#about to write, iclass 7, count 2 2006.173.10:32:39.01#ibcon#wrote, iclass 7, count 2 2006.173.10:32:39.01#ibcon#about to read 3, iclass 7, count 2 2006.173.10:32:39.04#ibcon#read 3, iclass 7, count 2 2006.173.10:32:39.04#ibcon#about to read 4, iclass 7, count 2 2006.173.10:32:39.04#ibcon#read 4, iclass 7, count 2 2006.173.10:32:39.04#ibcon#about to read 5, iclass 7, count 2 2006.173.10:32:39.04#ibcon#read 5, iclass 7, count 2 2006.173.10:32:39.04#ibcon#about to read 6, iclass 7, count 2 2006.173.10:32:39.04#ibcon#read 6, iclass 7, count 2 2006.173.10:32:39.04#ibcon#end of sib2, iclass 7, count 2 2006.173.10:32:39.04#ibcon#*after write, iclass 7, count 2 2006.173.10:32:39.04#ibcon#*before return 0, iclass 7, count 2 2006.173.10:32:39.04#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.10:32:39.04#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.173.10:32:39.04#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.173.10:32:39.04#ibcon#ireg 7 cls_cnt 0 2006.173.10:32:39.04#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.10:32:39.16#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.10:32:39.16#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.10:32:39.16#ibcon#enter wrdev, iclass 7, count 0 2006.173.10:32:39.16#ibcon#first serial, iclass 7, count 0 2006.173.10:32:39.16#ibcon#enter sib2, iclass 7, count 0 2006.173.10:32:39.16#ibcon#flushed, iclass 7, count 0 2006.173.10:32:39.16#ibcon#about to write, iclass 7, count 0 2006.173.10:32:39.16#ibcon#wrote, iclass 7, count 0 2006.173.10:32:39.16#ibcon#about to read 3, iclass 7, count 0 2006.173.10:32:39.18#ibcon#read 3, iclass 7, count 0 2006.173.10:32:39.18#ibcon#about to read 4, iclass 7, count 0 2006.173.10:32:39.18#ibcon#read 4, iclass 7, count 0 2006.173.10:32:39.18#ibcon#about to read 5, iclass 7, count 0 2006.173.10:32:39.18#ibcon#read 5, iclass 7, count 0 2006.173.10:32:39.18#ibcon#about to read 6, iclass 7, count 0 2006.173.10:32:39.18#ibcon#read 6, iclass 7, count 0 2006.173.10:32:39.18#ibcon#end of sib2, iclass 7, count 0 2006.173.10:32:39.18#ibcon#*mode == 0, iclass 7, count 0 2006.173.10:32:39.18#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.10:32:39.18#ibcon#[27=USB\r\n] 2006.173.10:32:39.18#ibcon#*before write, iclass 7, count 0 2006.173.10:32:39.18#ibcon#enter sib2, iclass 7, count 0 2006.173.10:32:39.18#ibcon#flushed, iclass 7, count 0 2006.173.10:32:39.18#ibcon#about to write, iclass 7, count 0 2006.173.10:32:39.18#ibcon#wrote, iclass 7, count 0 2006.173.10:32:39.18#ibcon#about to read 3, iclass 7, count 0 2006.173.10:32:39.21#ibcon#read 3, iclass 7, count 0 2006.173.10:32:39.21#ibcon#about to read 4, iclass 7, count 0 2006.173.10:32:39.21#ibcon#read 4, iclass 7, count 0 2006.173.10:32:39.21#ibcon#about to read 5, iclass 7, count 0 2006.173.10:32:39.21#ibcon#read 5, iclass 7, count 0 2006.173.10:32:39.21#ibcon#about to read 6, iclass 7, count 0 2006.173.10:32:39.21#ibcon#read 6, iclass 7, count 0 2006.173.10:32:39.21#ibcon#end of sib2, iclass 7, count 0 2006.173.10:32:39.21#ibcon#*after write, iclass 7, count 0 2006.173.10:32:39.21#ibcon#*before return 0, iclass 7, count 0 2006.173.10:32:39.21#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.10:32:39.21#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.173.10:32:39.21#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.10:32:39.21#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.10:32:39.21$vck44/vblo=8,744.99 2006.173.10:32:39.21#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.10:32:39.21#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.10:32:39.21#ibcon#ireg 17 cls_cnt 0 2006.173.10:32:39.21#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.10:32:39.21#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.10:32:39.21#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.10:32:39.21#ibcon#enter wrdev, iclass 11, count 0 2006.173.10:32:39.21#ibcon#first serial, iclass 11, count 0 2006.173.10:32:39.21#ibcon#enter sib2, iclass 11, count 0 2006.173.10:32:39.21#ibcon#flushed, iclass 11, count 0 2006.173.10:32:39.21#ibcon#about to write, iclass 11, count 0 2006.173.10:32:39.21#ibcon#wrote, iclass 11, count 0 2006.173.10:32:39.21#ibcon#about to read 3, iclass 11, count 0 2006.173.10:32:39.23#ibcon#read 3, iclass 11, count 0 2006.173.10:32:39.23#ibcon#about to read 4, iclass 11, count 0 2006.173.10:32:39.23#ibcon#read 4, iclass 11, count 0 2006.173.10:32:39.23#ibcon#about to read 5, iclass 11, count 0 2006.173.10:32:39.23#ibcon#read 5, iclass 11, count 0 2006.173.10:32:39.23#ibcon#about to read 6, iclass 11, count 0 2006.173.10:32:39.23#ibcon#read 6, iclass 11, count 0 2006.173.10:32:39.23#ibcon#end of sib2, iclass 11, count 0 2006.173.10:32:39.23#ibcon#*mode == 0, iclass 11, count 0 2006.173.10:32:39.23#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.10:32:39.23#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.10:32:39.23#ibcon#*before write, iclass 11, count 0 2006.173.10:32:39.23#ibcon#enter sib2, iclass 11, count 0 2006.173.10:32:39.23#ibcon#flushed, iclass 11, count 0 2006.173.10:32:39.23#ibcon#about to write, iclass 11, count 0 2006.173.10:32:39.23#ibcon#wrote, iclass 11, count 0 2006.173.10:32:39.23#ibcon#about to read 3, iclass 11, count 0 2006.173.10:32:39.27#ibcon#read 3, iclass 11, count 0 2006.173.10:32:39.27#ibcon#about to read 4, iclass 11, count 0 2006.173.10:32:39.27#ibcon#read 4, iclass 11, count 0 2006.173.10:32:39.27#ibcon#about to read 5, iclass 11, count 0 2006.173.10:32:39.27#ibcon#read 5, iclass 11, count 0 2006.173.10:32:39.27#ibcon#about to read 6, iclass 11, count 0 2006.173.10:32:39.27#ibcon#read 6, iclass 11, count 0 2006.173.10:32:39.27#ibcon#end of sib2, iclass 11, count 0 2006.173.10:32:39.27#ibcon#*after write, iclass 11, count 0 2006.173.10:32:39.27#ibcon#*before return 0, iclass 11, count 0 2006.173.10:32:39.27#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.10:32:39.27#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.10:32:39.27#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.10:32:39.27#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.10:32:39.27$vck44/vb=8,4 2006.173.10:32:39.27#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.173.10:32:39.27#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.173.10:32:39.27#ibcon#ireg 11 cls_cnt 2 2006.173.10:32:39.27#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.10:32:39.33#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.10:32:39.33#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.10:32:39.33#ibcon#enter wrdev, iclass 13, count 2 2006.173.10:32:39.33#ibcon#first serial, iclass 13, count 2 2006.173.10:32:39.33#ibcon#enter sib2, iclass 13, count 2 2006.173.10:32:39.33#ibcon#flushed, iclass 13, count 2 2006.173.10:32:39.33#ibcon#about to write, iclass 13, count 2 2006.173.10:32:39.33#ibcon#wrote, iclass 13, count 2 2006.173.10:32:39.33#ibcon#about to read 3, iclass 13, count 2 2006.173.10:32:39.35#ibcon#read 3, iclass 13, count 2 2006.173.10:32:39.35#ibcon#about to read 4, iclass 13, count 2 2006.173.10:32:39.35#ibcon#read 4, iclass 13, count 2 2006.173.10:32:39.35#ibcon#about to read 5, iclass 13, count 2 2006.173.10:32:39.35#ibcon#read 5, iclass 13, count 2 2006.173.10:32:39.35#ibcon#about to read 6, iclass 13, count 2 2006.173.10:32:39.35#ibcon#read 6, iclass 13, count 2 2006.173.10:32:39.35#ibcon#end of sib2, iclass 13, count 2 2006.173.10:32:39.35#ibcon#*mode == 0, iclass 13, count 2 2006.173.10:32:39.35#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.173.10:32:39.35#ibcon#[27=AT08-04\r\n] 2006.173.10:32:39.35#ibcon#*before write, iclass 13, count 2 2006.173.10:32:39.35#ibcon#enter sib2, iclass 13, count 2 2006.173.10:32:39.35#ibcon#flushed, iclass 13, count 2 2006.173.10:32:39.35#ibcon#about to write, iclass 13, count 2 2006.173.10:32:39.35#ibcon#wrote, iclass 13, count 2 2006.173.10:32:39.35#ibcon#about to read 3, iclass 13, count 2 2006.173.10:32:39.38#ibcon#read 3, iclass 13, count 2 2006.173.10:32:39.38#ibcon#about to read 4, iclass 13, count 2 2006.173.10:32:39.38#ibcon#read 4, iclass 13, count 2 2006.173.10:32:39.38#ibcon#about to read 5, iclass 13, count 2 2006.173.10:32:39.38#ibcon#read 5, iclass 13, count 2 2006.173.10:32:39.38#ibcon#about to read 6, iclass 13, count 2 2006.173.10:32:39.38#ibcon#read 6, iclass 13, count 2 2006.173.10:32:39.38#ibcon#end of sib2, iclass 13, count 2 2006.173.10:32:39.38#ibcon#*after write, iclass 13, count 2 2006.173.10:32:39.38#ibcon#*before return 0, iclass 13, count 2 2006.173.10:32:39.38#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.10:32:39.38#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.173.10:32:39.38#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.173.10:32:39.38#ibcon#ireg 7 cls_cnt 0 2006.173.10:32:39.38#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.10:32:39.50#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.10:32:39.50#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.10:32:39.50#ibcon#enter wrdev, iclass 13, count 0 2006.173.10:32:39.50#ibcon#first serial, iclass 13, count 0 2006.173.10:32:39.50#ibcon#enter sib2, iclass 13, count 0 2006.173.10:32:39.50#ibcon#flushed, iclass 13, count 0 2006.173.10:32:39.50#ibcon#about to write, iclass 13, count 0 2006.173.10:32:39.50#ibcon#wrote, iclass 13, count 0 2006.173.10:32:39.50#ibcon#about to read 3, iclass 13, count 0 2006.173.10:32:39.52#ibcon#read 3, iclass 13, count 0 2006.173.10:32:39.52#ibcon#about to read 4, iclass 13, count 0 2006.173.10:32:39.52#ibcon#read 4, iclass 13, count 0 2006.173.10:32:39.52#ibcon#about to read 5, iclass 13, count 0 2006.173.10:32:39.52#ibcon#read 5, iclass 13, count 0 2006.173.10:32:39.52#ibcon#about to read 6, iclass 13, count 0 2006.173.10:32:39.52#ibcon#read 6, iclass 13, count 0 2006.173.10:32:39.52#ibcon#end of sib2, iclass 13, count 0 2006.173.10:32:39.52#ibcon#*mode == 0, iclass 13, count 0 2006.173.10:32:39.52#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.10:32:39.52#ibcon#[27=USB\r\n] 2006.173.10:32:39.52#ibcon#*before write, iclass 13, count 0 2006.173.10:32:39.52#ibcon#enter sib2, iclass 13, count 0 2006.173.10:32:39.52#ibcon#flushed, iclass 13, count 0 2006.173.10:32:39.52#ibcon#about to write, iclass 13, count 0 2006.173.10:32:39.52#ibcon#wrote, iclass 13, count 0 2006.173.10:32:39.52#ibcon#about to read 3, iclass 13, count 0 2006.173.10:32:39.55#ibcon#read 3, iclass 13, count 0 2006.173.10:32:39.55#ibcon#about to read 4, iclass 13, count 0 2006.173.10:32:39.55#ibcon#read 4, iclass 13, count 0 2006.173.10:32:39.55#ibcon#about to read 5, iclass 13, count 0 2006.173.10:32:39.55#ibcon#read 5, iclass 13, count 0 2006.173.10:32:39.55#ibcon#about to read 6, iclass 13, count 0 2006.173.10:32:39.55#ibcon#read 6, iclass 13, count 0 2006.173.10:32:39.55#ibcon#end of sib2, iclass 13, count 0 2006.173.10:32:39.55#ibcon#*after write, iclass 13, count 0 2006.173.10:32:39.55#ibcon#*before return 0, iclass 13, count 0 2006.173.10:32:39.55#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.10:32:39.55#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.173.10:32:39.55#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.10:32:39.55#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.10:32:39.55$vck44/vabw=wide 2006.173.10:32:39.55#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.10:32:39.55#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.10:32:39.55#ibcon#ireg 8 cls_cnt 0 2006.173.10:32:39.55#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.10:32:39.55#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.10:32:39.55#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.10:32:39.55#ibcon#enter wrdev, iclass 15, count 0 2006.173.10:32:39.55#ibcon#first serial, iclass 15, count 0 2006.173.10:32:39.55#ibcon#enter sib2, iclass 15, count 0 2006.173.10:32:39.55#ibcon#flushed, iclass 15, count 0 2006.173.10:32:39.55#ibcon#about to write, iclass 15, count 0 2006.173.10:32:39.55#ibcon#wrote, iclass 15, count 0 2006.173.10:32:39.55#ibcon#about to read 3, iclass 15, count 0 2006.173.10:32:39.57#ibcon#read 3, iclass 15, count 0 2006.173.10:32:39.57#ibcon#about to read 4, iclass 15, count 0 2006.173.10:32:39.57#ibcon#read 4, iclass 15, count 0 2006.173.10:32:39.57#ibcon#about to read 5, iclass 15, count 0 2006.173.10:32:39.57#ibcon#read 5, iclass 15, count 0 2006.173.10:32:39.57#ibcon#about to read 6, iclass 15, count 0 2006.173.10:32:39.57#ibcon#read 6, iclass 15, count 0 2006.173.10:32:39.57#ibcon#end of sib2, iclass 15, count 0 2006.173.10:32:39.57#ibcon#*mode == 0, iclass 15, count 0 2006.173.10:32:39.57#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.10:32:39.57#ibcon#[25=BW32\r\n] 2006.173.10:32:39.57#ibcon#*before write, iclass 15, count 0 2006.173.10:32:39.57#ibcon#enter sib2, iclass 15, count 0 2006.173.10:32:39.57#ibcon#flushed, iclass 15, count 0 2006.173.10:32:39.57#ibcon#about to write, iclass 15, count 0 2006.173.10:32:39.57#ibcon#wrote, iclass 15, count 0 2006.173.10:32:39.57#ibcon#about to read 3, iclass 15, count 0 2006.173.10:32:39.60#ibcon#read 3, iclass 15, count 0 2006.173.10:32:39.60#ibcon#about to read 4, iclass 15, count 0 2006.173.10:32:39.60#ibcon#read 4, iclass 15, count 0 2006.173.10:32:39.60#ibcon#about to read 5, iclass 15, count 0 2006.173.10:32:39.60#ibcon#read 5, iclass 15, count 0 2006.173.10:32:39.60#ibcon#about to read 6, iclass 15, count 0 2006.173.10:32:39.60#ibcon#read 6, iclass 15, count 0 2006.173.10:32:39.60#ibcon#end of sib2, iclass 15, count 0 2006.173.10:32:39.60#ibcon#*after write, iclass 15, count 0 2006.173.10:32:39.60#ibcon#*before return 0, iclass 15, count 0 2006.173.10:32:39.60#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.10:32:39.60#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.10:32:39.60#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.10:32:39.60#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.10:32:39.60$vck44/vbbw=wide 2006.173.10:32:39.60#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.10:32:39.60#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.10:32:39.60#ibcon#ireg 8 cls_cnt 0 2006.173.10:32:39.60#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.10:32:39.67#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.10:32:39.67#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.10:32:39.67#ibcon#enter wrdev, iclass 17, count 0 2006.173.10:32:39.67#ibcon#first serial, iclass 17, count 0 2006.173.10:32:39.67#ibcon#enter sib2, iclass 17, count 0 2006.173.10:32:39.67#ibcon#flushed, iclass 17, count 0 2006.173.10:32:39.67#ibcon#about to write, iclass 17, count 0 2006.173.10:32:39.67#ibcon#wrote, iclass 17, count 0 2006.173.10:32:39.67#ibcon#about to read 3, iclass 17, count 0 2006.173.10:32:39.69#ibcon#read 3, iclass 17, count 0 2006.173.10:32:39.69#ibcon#about to read 4, iclass 17, count 0 2006.173.10:32:39.69#ibcon#read 4, iclass 17, count 0 2006.173.10:32:39.69#ibcon#about to read 5, iclass 17, count 0 2006.173.10:32:39.69#ibcon#read 5, iclass 17, count 0 2006.173.10:32:39.69#ibcon#about to read 6, iclass 17, count 0 2006.173.10:32:39.69#ibcon#read 6, iclass 17, count 0 2006.173.10:32:39.69#ibcon#end of sib2, iclass 17, count 0 2006.173.10:32:39.69#ibcon#*mode == 0, iclass 17, count 0 2006.173.10:32:39.69#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.10:32:39.69#ibcon#[27=BW32\r\n] 2006.173.10:32:39.69#ibcon#*before write, iclass 17, count 0 2006.173.10:32:39.69#ibcon#enter sib2, iclass 17, count 0 2006.173.10:32:39.69#ibcon#flushed, iclass 17, count 0 2006.173.10:32:39.69#ibcon#about to write, iclass 17, count 0 2006.173.10:32:39.69#ibcon#wrote, iclass 17, count 0 2006.173.10:32:39.69#ibcon#about to read 3, iclass 17, count 0 2006.173.10:32:39.72#ibcon#read 3, iclass 17, count 0 2006.173.10:32:39.72#ibcon#about to read 4, iclass 17, count 0 2006.173.10:32:39.72#ibcon#read 4, iclass 17, count 0 2006.173.10:32:39.72#ibcon#about to read 5, iclass 17, count 0 2006.173.10:32:39.72#ibcon#read 5, iclass 17, count 0 2006.173.10:32:39.72#ibcon#about to read 6, iclass 17, count 0 2006.173.10:32:39.72#ibcon#read 6, iclass 17, count 0 2006.173.10:32:39.72#ibcon#end of sib2, iclass 17, count 0 2006.173.10:32:39.72#ibcon#*after write, iclass 17, count 0 2006.173.10:32:39.72#ibcon#*before return 0, iclass 17, count 0 2006.173.10:32:39.72#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.10:32:39.72#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.10:32:39.72#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.10:32:39.72#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.10:32:39.72$setupk4/ifdk4 2006.173.10:32:39.72$ifdk4/lo= 2006.173.10:32:39.72$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.10:32:39.72$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.10:32:39.72$ifdk4/patch= 2006.173.10:32:39.72$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.10:32:39.72$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.10:32:39.72$setupk4/!*+20s 2006.173.10:32:44.28#abcon#<5=/03 0.9 1.6 22.59 901004.0\r\n> 2006.173.10:32:44.30#abcon#{5=INTERFACE CLEAR} 2006.173.10:32:44.36#abcon#[5=S1D000X0/0*\r\n] 2006.173.10:32:54.23$setupk4/"tpicd 2006.173.10:32:54.23$setupk4/echo=off 2006.173.10:32:54.23$setupk4/xlog=off 2006.173.10:32:54.23:!2006.173.10:38:29 2006.173.10:33:01.13#trakl#Source acquired 2006.173.10:33:02.13#flagr#flagr/antenna,acquired 2006.173.10:38:29.00:preob 2006.173.10:38:30.14/onsource/TRACKING 2006.173.10:38:30.14:!2006.173.10:38:39 2006.173.10:38:39.00:"tape 2006.173.10:38:39.00:"st=record 2006.173.10:38:39.00:data_valid=on 2006.173.10:38:39.00:midob 2006.173.10:38:39.14/onsource/TRACKING 2006.173.10:38:39.14/wx/22.63,1003.8,90 2006.173.10:38:39.29/cable/+6.5032E-03 2006.173.10:38:40.38/va/01,07,usb,yes,53,57 2006.173.10:38:40.38/va/02,06,usb,yes,53,54 2006.173.10:38:40.38/va/03,05,usb,yes,66,69 2006.173.10:38:40.38/va/04,06,usb,yes,54,57 2006.173.10:38:40.38/va/05,04,usb,yes,43,44 2006.173.10:38:40.38/va/06,03,usb,yes,59,59 2006.173.10:38:40.38/va/07,04,usb,yes,49,50 2006.173.10:38:40.38/va/08,04,usb,yes,42,50 2006.173.10:38:40.61/valo/01,524.99,yes,locked 2006.173.10:38:40.61/valo/02,534.99,yes,locked 2006.173.10:38:40.61/valo/03,564.99,yes,locked 2006.173.10:38:40.61/valo/04,624.99,yes,locked 2006.173.10:38:40.61/valo/05,734.99,yes,locked 2006.173.10:38:40.61/valo/06,814.99,yes,locked 2006.173.10:38:40.61/valo/07,864.99,yes,locked 2006.173.10:38:40.61/valo/08,884.99,yes,locked 2006.173.10:38:41.70/vb/01,04,usb,yes,37,83 2006.173.10:38:41.70/vb/02,04,usb,yes,37,89 2006.173.10:38:41.70/vb/03,04,usb,yes,34,58 2006.173.10:38:41.70/vb/04,04,usb,yes,39,37 2006.173.10:38:41.70/vb/05,04,usb,yes,32,34 2006.173.10:38:41.70/vb/06,04,usb,yes,37,33 2006.173.10:38:41.70/vb/07,04,usb,yes,36,36 2006.173.10:38:41.70/vb/08,04,usb,yes,33,37 2006.173.10:38:41.94/vblo/01,629.99,yes,locked 2006.173.10:38:41.94/vblo/02,634.99,yes,locked 2006.173.10:38:41.94/vblo/03,649.99,yes,locked 2006.173.10:38:41.94/vblo/04,679.99,yes,locked 2006.173.10:38:41.94/vblo/05,709.99,yes,locked 2006.173.10:38:41.94/vblo/06,719.99,yes,locked 2006.173.10:38:41.94/vblo/07,734.99,yes,locked 2006.173.10:38:41.94/vblo/08,744.99,yes,locked 2006.173.10:38:42.09/vabw/8 2006.173.10:38:42.24/vbbw/8 2006.173.10:38:42.33/xfe/off,on,14.7 2006.173.10:38:42.71/ifatt/23,28,28,28 2006.173.10:38:43.07/fmout-gps/S +4.00E-07 2006.173.10:38:43.11:!2006.173.10:45:29 2006.173.10:45:29.00:data_valid=off 2006.173.10:45:29.00:"et 2006.173.10:45:29.01:!+3s 2006.173.10:45:32.02:"tape 2006.173.10:45:32.02:postob 2006.173.10:45:32.21/cable/+6.5014E-03 2006.173.10:45:32.21/wx/22.65,1003.8,91 2006.173.10:45:32.27/fmout-gps/S +3.99E-07 2006.173.10:45:32.27:scan_name=173-1046,jd0606,40 2006.173.10:45:32.28:source=1424-418,142756.30,-420619.4,2000.0,cw 2006.173.10:45:33.14#flagr#flagr/antenna,new-source 2006.173.10:45:33.14:checkk5 2006.173.10:45:33.57/chk_autoobs//k5ts1/ autoobs is running! 2006.173.10:45:33.97/chk_autoobs//k5ts2/ autoobs is running! 2006.173.10:45:34.39/chk_autoobs//k5ts3/ autoobs is running! 2006.173.10:45:34.77/chk_autoobs//k5ts4/ autoobs is running! 2006.173.10:45:35.16/chk_obsdata//k5ts1/T1731038??a.dat file size is correct (nominal:1640MB, actual:1636MB). 2006.173.10:45:35.59/chk_obsdata//k5ts2/T1731038??b.dat file size is correct (nominal:1640MB, actual:1636MB). 2006.173.10:45:35.99/chk_obsdata//k5ts3/T1731038??c.dat file size is correct (nominal:1640MB, actual:1636MB). 2006.173.10:45:36.39/chk_obsdata//k5ts4/T1731038??d.dat file size is correct (nominal:1640MB, actual:1636MB). 2006.173.10:45:37.13/k5log//k5ts1_log_newline 2006.173.10:45:37.85/k5log//k5ts2_log_newline 2006.173.10:45:38.57/k5log//k5ts3_log_newline 2006.173.10:45:39.28/k5log//k5ts4_log_newline 2006.173.10:45:39.31/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.10:45:39.31:setupk4=1 2006.173.10:45:39.31$setupk4/echo=on 2006.173.10:45:39.31$setupk4/pcalon 2006.173.10:45:39.31$pcalon/"no phase cal control is implemented here 2006.173.10:45:39.31$setupk4/"tpicd=stop 2006.173.10:45:39.31$setupk4/"rec=synch_on 2006.173.10:45:39.31$setupk4/"rec_mode=128 2006.173.10:45:39.31$setupk4/!* 2006.173.10:45:39.31$setupk4/recpk4 2006.173.10:45:39.31$recpk4/recpatch= 2006.173.10:45:39.31$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.10:45:39.31$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.10:45:39.31$setupk4/vck44 2006.173.10:45:39.31$vck44/valo=1,524.99 2006.173.10:45:39.31#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.10:45:39.31#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.10:45:39.31#ibcon#ireg 17 cls_cnt 0 2006.173.10:45:39.31#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.10:45:39.31#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.10:45:39.31#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.10:45:39.31#ibcon#enter wrdev, iclass 33, count 0 2006.173.10:45:39.31#ibcon#first serial, iclass 33, count 0 2006.173.10:45:39.31#ibcon#enter sib2, iclass 33, count 0 2006.173.10:45:39.31#ibcon#flushed, iclass 33, count 0 2006.173.10:45:39.31#ibcon#about to write, iclass 33, count 0 2006.173.10:45:39.31#ibcon#wrote, iclass 33, count 0 2006.173.10:45:39.31#ibcon#about to read 3, iclass 33, count 0 2006.173.10:45:39.33#ibcon#read 3, iclass 33, count 0 2006.173.10:45:39.33#ibcon#about to read 4, iclass 33, count 0 2006.173.10:45:39.33#ibcon#read 4, iclass 33, count 0 2006.173.10:45:39.33#ibcon#about to read 5, iclass 33, count 0 2006.173.10:45:39.33#ibcon#read 5, iclass 33, count 0 2006.173.10:45:39.33#ibcon#about to read 6, iclass 33, count 0 2006.173.10:45:39.33#ibcon#read 6, iclass 33, count 0 2006.173.10:45:39.33#ibcon#end of sib2, iclass 33, count 0 2006.173.10:45:39.33#ibcon#*mode == 0, iclass 33, count 0 2006.173.10:45:39.33#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.10:45:39.33#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.10:45:39.33#ibcon#*before write, iclass 33, count 0 2006.173.10:45:39.33#ibcon#enter sib2, iclass 33, count 0 2006.173.10:45:39.33#ibcon#flushed, iclass 33, count 0 2006.173.10:45:39.33#ibcon#about to write, iclass 33, count 0 2006.173.10:45:39.33#ibcon#wrote, iclass 33, count 0 2006.173.10:45:39.33#ibcon#about to read 3, iclass 33, count 0 2006.173.10:45:39.38#ibcon#read 3, iclass 33, count 0 2006.173.10:45:39.38#ibcon#about to read 4, iclass 33, count 0 2006.173.10:45:39.38#ibcon#read 4, iclass 33, count 0 2006.173.10:45:39.38#ibcon#about to read 5, iclass 33, count 0 2006.173.10:45:39.38#ibcon#read 5, iclass 33, count 0 2006.173.10:45:39.38#ibcon#about to read 6, iclass 33, count 0 2006.173.10:45:39.38#ibcon#read 6, iclass 33, count 0 2006.173.10:45:39.38#ibcon#end of sib2, iclass 33, count 0 2006.173.10:45:39.38#ibcon#*after write, iclass 33, count 0 2006.173.10:45:39.38#ibcon#*before return 0, iclass 33, count 0 2006.173.10:45:39.38#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.10:45:39.38#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.10:45:39.38#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.10:45:39.38#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.10:45:39.38$vck44/va=1,7 2006.173.10:45:39.38#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.10:45:39.38#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.10:45:39.38#ibcon#ireg 11 cls_cnt 2 2006.173.10:45:39.38#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.10:45:39.38#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.10:45:39.38#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.10:45:39.38#ibcon#enter wrdev, iclass 35, count 2 2006.173.10:45:39.38#ibcon#first serial, iclass 35, count 2 2006.173.10:45:39.38#ibcon#enter sib2, iclass 35, count 2 2006.173.10:45:39.38#ibcon#flushed, iclass 35, count 2 2006.173.10:45:39.38#ibcon#about to write, iclass 35, count 2 2006.173.10:45:39.38#ibcon#wrote, iclass 35, count 2 2006.173.10:45:39.38#ibcon#about to read 3, iclass 35, count 2 2006.173.10:45:39.40#ibcon#read 3, iclass 35, count 2 2006.173.10:45:39.40#ibcon#about to read 4, iclass 35, count 2 2006.173.10:45:39.40#ibcon#read 4, iclass 35, count 2 2006.173.10:45:39.40#ibcon#about to read 5, iclass 35, count 2 2006.173.10:45:39.40#ibcon#read 5, iclass 35, count 2 2006.173.10:45:39.40#ibcon#about to read 6, iclass 35, count 2 2006.173.10:45:39.40#ibcon#read 6, iclass 35, count 2 2006.173.10:45:39.40#ibcon#end of sib2, iclass 35, count 2 2006.173.10:45:39.40#ibcon#*mode == 0, iclass 35, count 2 2006.173.10:45:39.40#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.10:45:39.40#ibcon#[25=AT01-07\r\n] 2006.173.10:45:39.40#ibcon#*before write, iclass 35, count 2 2006.173.10:45:39.40#ibcon#enter sib2, iclass 35, count 2 2006.173.10:45:39.40#ibcon#flushed, iclass 35, count 2 2006.173.10:45:39.40#ibcon#about to write, iclass 35, count 2 2006.173.10:45:39.40#ibcon#wrote, iclass 35, count 2 2006.173.10:45:39.40#ibcon#about to read 3, iclass 35, count 2 2006.173.10:45:39.43#ibcon#read 3, iclass 35, count 2 2006.173.10:45:39.43#ibcon#about to read 4, iclass 35, count 2 2006.173.10:45:39.43#ibcon#read 4, iclass 35, count 2 2006.173.10:45:39.43#ibcon#about to read 5, iclass 35, count 2 2006.173.10:45:39.43#ibcon#read 5, iclass 35, count 2 2006.173.10:45:39.43#ibcon#about to read 6, iclass 35, count 2 2006.173.10:45:39.43#ibcon#read 6, iclass 35, count 2 2006.173.10:45:39.43#ibcon#end of sib2, iclass 35, count 2 2006.173.10:45:39.43#ibcon#*after write, iclass 35, count 2 2006.173.10:45:39.43#ibcon#*before return 0, iclass 35, count 2 2006.173.10:45:39.43#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.10:45:39.43#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.10:45:39.43#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.10:45:39.43#ibcon#ireg 7 cls_cnt 0 2006.173.10:45:39.43#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.10:45:39.55#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.10:45:39.55#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.10:45:39.55#ibcon#enter wrdev, iclass 35, count 0 2006.173.10:45:39.55#ibcon#first serial, iclass 35, count 0 2006.173.10:45:39.55#ibcon#enter sib2, iclass 35, count 0 2006.173.10:45:39.55#ibcon#flushed, iclass 35, count 0 2006.173.10:45:39.55#ibcon#about to write, iclass 35, count 0 2006.173.10:45:39.55#ibcon#wrote, iclass 35, count 0 2006.173.10:45:39.55#ibcon#about to read 3, iclass 35, count 0 2006.173.10:45:39.57#ibcon#read 3, iclass 35, count 0 2006.173.10:45:39.57#ibcon#about to read 4, iclass 35, count 0 2006.173.10:45:39.57#ibcon#read 4, iclass 35, count 0 2006.173.10:45:39.57#ibcon#about to read 5, iclass 35, count 0 2006.173.10:45:39.57#ibcon#read 5, iclass 35, count 0 2006.173.10:45:39.57#ibcon#about to read 6, iclass 35, count 0 2006.173.10:45:39.57#ibcon#read 6, iclass 35, count 0 2006.173.10:45:39.57#ibcon#end of sib2, iclass 35, count 0 2006.173.10:45:39.57#ibcon#*mode == 0, iclass 35, count 0 2006.173.10:45:39.57#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.10:45:39.57#ibcon#[25=USB\r\n] 2006.173.10:45:39.57#ibcon#*before write, iclass 35, count 0 2006.173.10:45:39.57#ibcon#enter sib2, iclass 35, count 0 2006.173.10:45:39.57#ibcon#flushed, iclass 35, count 0 2006.173.10:45:39.57#ibcon#about to write, iclass 35, count 0 2006.173.10:45:39.57#ibcon#wrote, iclass 35, count 0 2006.173.10:45:39.57#ibcon#about to read 3, iclass 35, count 0 2006.173.10:45:39.60#ibcon#read 3, iclass 35, count 0 2006.173.10:45:39.60#ibcon#about to read 4, iclass 35, count 0 2006.173.10:45:39.60#ibcon#read 4, iclass 35, count 0 2006.173.10:45:39.60#ibcon#about to read 5, iclass 35, count 0 2006.173.10:45:39.60#ibcon#read 5, iclass 35, count 0 2006.173.10:45:39.60#ibcon#about to read 6, iclass 35, count 0 2006.173.10:45:39.60#ibcon#read 6, iclass 35, count 0 2006.173.10:45:39.60#ibcon#end of sib2, iclass 35, count 0 2006.173.10:45:39.60#ibcon#*after write, iclass 35, count 0 2006.173.10:45:39.60#ibcon#*before return 0, iclass 35, count 0 2006.173.10:45:39.60#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.10:45:39.60#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.10:45:39.60#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.10:45:39.60#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.10:45:39.60$vck44/valo=2,534.99 2006.173.10:45:39.60#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.10:45:39.60#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.10:45:39.60#ibcon#ireg 17 cls_cnt 0 2006.173.10:45:39.60#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.10:45:39.60#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.10:45:39.60#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.10:45:39.60#ibcon#enter wrdev, iclass 37, count 0 2006.173.10:45:39.60#ibcon#first serial, iclass 37, count 0 2006.173.10:45:39.60#ibcon#enter sib2, iclass 37, count 0 2006.173.10:45:39.60#ibcon#flushed, iclass 37, count 0 2006.173.10:45:39.60#ibcon#about to write, iclass 37, count 0 2006.173.10:45:39.60#ibcon#wrote, iclass 37, count 0 2006.173.10:45:39.60#ibcon#about to read 3, iclass 37, count 0 2006.173.10:45:39.62#ibcon#read 3, iclass 37, count 0 2006.173.10:45:39.62#ibcon#about to read 4, iclass 37, count 0 2006.173.10:45:39.62#ibcon#read 4, iclass 37, count 0 2006.173.10:45:39.62#ibcon#about to read 5, iclass 37, count 0 2006.173.10:45:39.62#ibcon#read 5, iclass 37, count 0 2006.173.10:45:39.62#ibcon#about to read 6, iclass 37, count 0 2006.173.10:45:39.62#ibcon#read 6, iclass 37, count 0 2006.173.10:45:39.62#ibcon#end of sib2, iclass 37, count 0 2006.173.10:45:39.62#ibcon#*mode == 0, iclass 37, count 0 2006.173.10:45:39.62#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.10:45:39.62#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.10:45:39.62#ibcon#*before write, iclass 37, count 0 2006.173.10:45:39.62#ibcon#enter sib2, iclass 37, count 0 2006.173.10:45:39.62#ibcon#flushed, iclass 37, count 0 2006.173.10:45:39.62#ibcon#about to write, iclass 37, count 0 2006.173.10:45:39.62#ibcon#wrote, iclass 37, count 0 2006.173.10:45:39.62#ibcon#about to read 3, iclass 37, count 0 2006.173.10:45:39.66#ibcon#read 3, iclass 37, count 0 2006.173.10:45:39.66#ibcon#about to read 4, iclass 37, count 0 2006.173.10:45:39.66#ibcon#read 4, iclass 37, count 0 2006.173.10:45:39.66#ibcon#about to read 5, iclass 37, count 0 2006.173.10:45:39.66#ibcon#read 5, iclass 37, count 0 2006.173.10:45:39.66#ibcon#about to read 6, iclass 37, count 0 2006.173.10:45:39.66#ibcon#read 6, iclass 37, count 0 2006.173.10:45:39.66#ibcon#end of sib2, iclass 37, count 0 2006.173.10:45:39.66#ibcon#*after write, iclass 37, count 0 2006.173.10:45:39.66#ibcon#*before return 0, iclass 37, count 0 2006.173.10:45:39.66#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.10:45:39.66#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.10:45:39.66#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.10:45:39.66#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.10:45:39.66$vck44/va=2,6 2006.173.10:45:39.66#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.10:45:39.66#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.10:45:39.66#ibcon#ireg 11 cls_cnt 2 2006.173.10:45:39.66#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.10:45:39.72#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.10:45:39.72#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.10:45:39.72#ibcon#enter wrdev, iclass 39, count 2 2006.173.10:45:39.72#ibcon#first serial, iclass 39, count 2 2006.173.10:45:39.72#ibcon#enter sib2, iclass 39, count 2 2006.173.10:45:39.72#ibcon#flushed, iclass 39, count 2 2006.173.10:45:39.72#ibcon#about to write, iclass 39, count 2 2006.173.10:45:39.72#ibcon#wrote, iclass 39, count 2 2006.173.10:45:39.72#ibcon#about to read 3, iclass 39, count 2 2006.173.10:45:39.74#ibcon#read 3, iclass 39, count 2 2006.173.10:45:39.74#ibcon#about to read 4, iclass 39, count 2 2006.173.10:45:39.74#ibcon#read 4, iclass 39, count 2 2006.173.10:45:39.74#ibcon#about to read 5, iclass 39, count 2 2006.173.10:45:39.74#ibcon#read 5, iclass 39, count 2 2006.173.10:45:39.74#ibcon#about to read 6, iclass 39, count 2 2006.173.10:45:39.74#ibcon#read 6, iclass 39, count 2 2006.173.10:45:39.74#ibcon#end of sib2, iclass 39, count 2 2006.173.10:45:39.74#ibcon#*mode == 0, iclass 39, count 2 2006.173.10:45:39.74#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.10:45:39.74#ibcon#[25=AT02-06\r\n] 2006.173.10:45:39.74#ibcon#*before write, iclass 39, count 2 2006.173.10:45:39.74#ibcon#enter sib2, iclass 39, count 2 2006.173.10:45:39.74#ibcon#flushed, iclass 39, count 2 2006.173.10:45:39.74#ibcon#about to write, iclass 39, count 2 2006.173.10:45:39.74#ibcon#wrote, iclass 39, count 2 2006.173.10:45:39.74#ibcon#about to read 3, iclass 39, count 2 2006.173.10:45:39.77#ibcon#read 3, iclass 39, count 2 2006.173.10:45:39.77#ibcon#about to read 4, iclass 39, count 2 2006.173.10:45:39.77#ibcon#read 4, iclass 39, count 2 2006.173.10:45:39.77#ibcon#about to read 5, iclass 39, count 2 2006.173.10:45:39.77#ibcon#read 5, iclass 39, count 2 2006.173.10:45:39.77#ibcon#about to read 6, iclass 39, count 2 2006.173.10:45:39.77#ibcon#read 6, iclass 39, count 2 2006.173.10:45:39.77#ibcon#end of sib2, iclass 39, count 2 2006.173.10:45:39.77#ibcon#*after write, iclass 39, count 2 2006.173.10:45:39.77#ibcon#*before return 0, iclass 39, count 2 2006.173.10:45:39.77#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.10:45:39.77#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.10:45:39.77#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.10:45:39.77#ibcon#ireg 7 cls_cnt 0 2006.173.10:45:39.77#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.10:45:39.89#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.10:45:39.89#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.10:45:39.89#ibcon#enter wrdev, iclass 39, count 0 2006.173.10:45:39.89#ibcon#first serial, iclass 39, count 0 2006.173.10:45:39.89#ibcon#enter sib2, iclass 39, count 0 2006.173.10:45:39.89#ibcon#flushed, iclass 39, count 0 2006.173.10:45:39.89#ibcon#about to write, iclass 39, count 0 2006.173.10:45:39.89#ibcon#wrote, iclass 39, count 0 2006.173.10:45:39.89#ibcon#about to read 3, iclass 39, count 0 2006.173.10:45:39.91#ibcon#read 3, iclass 39, count 0 2006.173.10:45:39.91#ibcon#about to read 4, iclass 39, count 0 2006.173.10:45:39.91#ibcon#read 4, iclass 39, count 0 2006.173.10:45:39.91#ibcon#about to read 5, iclass 39, count 0 2006.173.10:45:39.91#ibcon#read 5, iclass 39, count 0 2006.173.10:45:39.91#ibcon#about to read 6, iclass 39, count 0 2006.173.10:45:39.91#ibcon#read 6, iclass 39, count 0 2006.173.10:45:39.91#ibcon#end of sib2, iclass 39, count 0 2006.173.10:45:39.91#ibcon#*mode == 0, iclass 39, count 0 2006.173.10:45:39.91#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.10:45:39.91#ibcon#[25=USB\r\n] 2006.173.10:45:39.91#ibcon#*before write, iclass 39, count 0 2006.173.10:45:39.91#ibcon#enter sib2, iclass 39, count 0 2006.173.10:45:39.91#ibcon#flushed, iclass 39, count 0 2006.173.10:45:39.91#ibcon#about to write, iclass 39, count 0 2006.173.10:45:39.91#ibcon#wrote, iclass 39, count 0 2006.173.10:45:39.91#ibcon#about to read 3, iclass 39, count 0 2006.173.10:45:39.94#ibcon#read 3, iclass 39, count 0 2006.173.10:45:39.94#ibcon#about to read 4, iclass 39, count 0 2006.173.10:45:39.94#ibcon#read 4, iclass 39, count 0 2006.173.10:45:39.94#ibcon#about to read 5, iclass 39, count 0 2006.173.10:45:39.94#ibcon#read 5, iclass 39, count 0 2006.173.10:45:39.94#ibcon#about to read 6, iclass 39, count 0 2006.173.10:45:39.94#ibcon#read 6, iclass 39, count 0 2006.173.10:45:39.94#ibcon#end of sib2, iclass 39, count 0 2006.173.10:45:39.94#ibcon#*after write, iclass 39, count 0 2006.173.10:45:39.94#ibcon#*before return 0, iclass 39, count 0 2006.173.10:45:39.94#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.10:45:39.94#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.10:45:39.94#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.10:45:39.94#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.10:45:39.94$vck44/valo=3,564.99 2006.173.10:45:39.94#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.10:45:39.94#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.10:45:39.94#ibcon#ireg 17 cls_cnt 0 2006.173.10:45:39.94#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.10:45:39.94#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.10:45:39.94#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.10:45:39.94#ibcon#enter wrdev, iclass 3, count 0 2006.173.10:45:39.94#ibcon#first serial, iclass 3, count 0 2006.173.10:45:39.94#ibcon#enter sib2, iclass 3, count 0 2006.173.10:45:39.94#ibcon#flushed, iclass 3, count 0 2006.173.10:45:39.94#ibcon#about to write, iclass 3, count 0 2006.173.10:45:39.94#ibcon#wrote, iclass 3, count 0 2006.173.10:45:39.94#ibcon#about to read 3, iclass 3, count 0 2006.173.10:45:39.96#ibcon#read 3, iclass 3, count 0 2006.173.10:45:39.96#ibcon#about to read 4, iclass 3, count 0 2006.173.10:45:39.96#ibcon#read 4, iclass 3, count 0 2006.173.10:45:39.96#ibcon#about to read 5, iclass 3, count 0 2006.173.10:45:39.96#ibcon#read 5, iclass 3, count 0 2006.173.10:45:39.96#ibcon#about to read 6, iclass 3, count 0 2006.173.10:45:39.96#ibcon#read 6, iclass 3, count 0 2006.173.10:45:39.96#ibcon#end of sib2, iclass 3, count 0 2006.173.10:45:39.96#ibcon#*mode == 0, iclass 3, count 0 2006.173.10:45:39.96#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.10:45:39.96#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.10:45:39.96#ibcon#*before write, iclass 3, count 0 2006.173.10:45:39.96#ibcon#enter sib2, iclass 3, count 0 2006.173.10:45:39.96#ibcon#flushed, iclass 3, count 0 2006.173.10:45:39.96#ibcon#about to write, iclass 3, count 0 2006.173.10:45:39.96#ibcon#wrote, iclass 3, count 0 2006.173.10:45:39.96#ibcon#about to read 3, iclass 3, count 0 2006.173.10:45:40.00#ibcon#read 3, iclass 3, count 0 2006.173.10:45:40.00#ibcon#about to read 4, iclass 3, count 0 2006.173.10:45:40.00#ibcon#read 4, iclass 3, count 0 2006.173.10:45:40.00#ibcon#about to read 5, iclass 3, count 0 2006.173.10:45:40.00#ibcon#read 5, iclass 3, count 0 2006.173.10:45:40.00#ibcon#about to read 6, iclass 3, count 0 2006.173.10:45:40.00#ibcon#read 6, iclass 3, count 0 2006.173.10:45:40.00#ibcon#end of sib2, iclass 3, count 0 2006.173.10:45:40.00#ibcon#*after write, iclass 3, count 0 2006.173.10:45:40.00#ibcon#*before return 0, iclass 3, count 0 2006.173.10:45:40.00#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.10:45:40.00#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.10:45:40.00#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.10:45:40.00#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.10:45:40.00$vck44/va=3,5 2006.173.10:45:40.00#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.10:45:40.00#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.10:45:40.00#ibcon#ireg 11 cls_cnt 2 2006.173.10:45:40.00#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.10:45:40.06#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.10:45:40.06#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.10:45:40.06#ibcon#enter wrdev, iclass 5, count 2 2006.173.10:45:40.06#ibcon#first serial, iclass 5, count 2 2006.173.10:45:40.06#ibcon#enter sib2, iclass 5, count 2 2006.173.10:45:40.06#ibcon#flushed, iclass 5, count 2 2006.173.10:45:40.06#ibcon#about to write, iclass 5, count 2 2006.173.10:45:40.06#ibcon#wrote, iclass 5, count 2 2006.173.10:45:40.06#ibcon#about to read 3, iclass 5, count 2 2006.173.10:45:40.08#ibcon#read 3, iclass 5, count 2 2006.173.10:45:40.08#ibcon#about to read 4, iclass 5, count 2 2006.173.10:45:40.08#ibcon#read 4, iclass 5, count 2 2006.173.10:45:40.08#ibcon#about to read 5, iclass 5, count 2 2006.173.10:45:40.08#ibcon#read 5, iclass 5, count 2 2006.173.10:45:40.08#ibcon#about to read 6, iclass 5, count 2 2006.173.10:45:40.08#ibcon#read 6, iclass 5, count 2 2006.173.10:45:40.08#ibcon#end of sib2, iclass 5, count 2 2006.173.10:45:40.08#ibcon#*mode == 0, iclass 5, count 2 2006.173.10:45:40.08#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.10:45:40.08#ibcon#[25=AT03-05\r\n] 2006.173.10:45:40.08#ibcon#*before write, iclass 5, count 2 2006.173.10:45:40.08#ibcon#enter sib2, iclass 5, count 2 2006.173.10:45:40.08#ibcon#flushed, iclass 5, count 2 2006.173.10:45:40.08#ibcon#about to write, iclass 5, count 2 2006.173.10:45:40.08#ibcon#wrote, iclass 5, count 2 2006.173.10:45:40.08#ibcon#about to read 3, iclass 5, count 2 2006.173.10:45:40.11#ibcon#read 3, iclass 5, count 2 2006.173.10:45:40.11#ibcon#about to read 4, iclass 5, count 2 2006.173.10:45:40.11#ibcon#read 4, iclass 5, count 2 2006.173.10:45:40.11#ibcon#about to read 5, iclass 5, count 2 2006.173.10:45:40.11#ibcon#read 5, iclass 5, count 2 2006.173.10:45:40.11#ibcon#about to read 6, iclass 5, count 2 2006.173.10:45:40.11#ibcon#read 6, iclass 5, count 2 2006.173.10:45:40.11#ibcon#end of sib2, iclass 5, count 2 2006.173.10:45:40.11#ibcon#*after write, iclass 5, count 2 2006.173.10:45:40.11#ibcon#*before return 0, iclass 5, count 2 2006.173.10:45:40.11#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.10:45:40.11#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.10:45:40.11#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.10:45:40.11#ibcon#ireg 7 cls_cnt 0 2006.173.10:45:40.11#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.10:45:40.19#abcon#<5=/05 1.0 1.8 22.65 911003.9\r\n> 2006.173.10:45:40.21#abcon#{5=INTERFACE CLEAR} 2006.173.10:45:40.23#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.10:45:40.23#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.10:45:40.23#ibcon#enter wrdev, iclass 5, count 0 2006.173.10:45:40.23#ibcon#first serial, iclass 5, count 0 2006.173.10:45:40.23#ibcon#enter sib2, iclass 5, count 0 2006.173.10:45:40.23#ibcon#flushed, iclass 5, count 0 2006.173.10:45:40.23#ibcon#about to write, iclass 5, count 0 2006.173.10:45:40.23#ibcon#wrote, iclass 5, count 0 2006.173.10:45:40.23#ibcon#about to read 3, iclass 5, count 0 2006.173.10:45:40.25#ibcon#read 3, iclass 5, count 0 2006.173.10:45:40.25#ibcon#about to read 4, iclass 5, count 0 2006.173.10:45:40.25#ibcon#read 4, iclass 5, count 0 2006.173.10:45:40.25#ibcon#about to read 5, iclass 5, count 0 2006.173.10:45:40.25#ibcon#read 5, iclass 5, count 0 2006.173.10:45:40.25#ibcon#about to read 6, iclass 5, count 0 2006.173.10:45:40.25#ibcon#read 6, iclass 5, count 0 2006.173.10:45:40.25#ibcon#end of sib2, iclass 5, count 0 2006.173.10:45:40.25#ibcon#*mode == 0, iclass 5, count 0 2006.173.10:45:40.25#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.10:45:40.25#ibcon#[25=USB\r\n] 2006.173.10:45:40.25#ibcon#*before write, iclass 5, count 0 2006.173.10:45:40.25#ibcon#enter sib2, iclass 5, count 0 2006.173.10:45:40.25#ibcon#flushed, iclass 5, count 0 2006.173.10:45:40.25#ibcon#about to write, iclass 5, count 0 2006.173.10:45:40.25#ibcon#wrote, iclass 5, count 0 2006.173.10:45:40.25#ibcon#about to read 3, iclass 5, count 0 2006.173.10:45:40.27#abcon#[5=S1D000X0/0*\r\n] 2006.173.10:45:40.28#ibcon#read 3, iclass 5, count 0 2006.173.10:45:40.28#ibcon#about to read 4, iclass 5, count 0 2006.173.10:45:40.28#ibcon#read 4, iclass 5, count 0 2006.173.10:45:40.28#ibcon#about to read 5, iclass 5, count 0 2006.173.10:45:40.28#ibcon#read 5, iclass 5, count 0 2006.173.10:45:40.28#ibcon#about to read 6, iclass 5, count 0 2006.173.10:45:40.28#ibcon#read 6, iclass 5, count 0 2006.173.10:45:40.28#ibcon#end of sib2, iclass 5, count 0 2006.173.10:45:40.28#ibcon#*after write, iclass 5, count 0 2006.173.10:45:40.28#ibcon#*before return 0, iclass 5, count 0 2006.173.10:45:40.28#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.10:45:40.28#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.10:45:40.28#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.10:45:40.28#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.10:45:40.28$vck44/valo=4,624.99 2006.173.10:45:40.28#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.10:45:40.28#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.10:45:40.28#ibcon#ireg 17 cls_cnt 0 2006.173.10:45:40.28#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.10:45:40.28#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.10:45:40.28#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.10:45:40.28#ibcon#enter wrdev, iclass 13, count 0 2006.173.10:45:40.28#ibcon#first serial, iclass 13, count 0 2006.173.10:45:40.28#ibcon#enter sib2, iclass 13, count 0 2006.173.10:45:40.28#ibcon#flushed, iclass 13, count 0 2006.173.10:45:40.28#ibcon#about to write, iclass 13, count 0 2006.173.10:45:40.28#ibcon#wrote, iclass 13, count 0 2006.173.10:45:40.28#ibcon#about to read 3, iclass 13, count 0 2006.173.10:45:40.30#ibcon#read 3, iclass 13, count 0 2006.173.10:45:40.30#ibcon#about to read 4, iclass 13, count 0 2006.173.10:45:40.30#ibcon#read 4, iclass 13, count 0 2006.173.10:45:40.30#ibcon#about to read 5, iclass 13, count 0 2006.173.10:45:40.30#ibcon#read 5, iclass 13, count 0 2006.173.10:45:40.30#ibcon#about to read 6, iclass 13, count 0 2006.173.10:45:40.30#ibcon#read 6, iclass 13, count 0 2006.173.10:45:40.30#ibcon#end of sib2, iclass 13, count 0 2006.173.10:45:40.30#ibcon#*mode == 0, iclass 13, count 0 2006.173.10:45:40.30#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.10:45:40.30#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.10:45:40.30#ibcon#*before write, iclass 13, count 0 2006.173.10:45:40.30#ibcon#enter sib2, iclass 13, count 0 2006.173.10:45:40.30#ibcon#flushed, iclass 13, count 0 2006.173.10:45:40.30#ibcon#about to write, iclass 13, count 0 2006.173.10:45:40.30#ibcon#wrote, iclass 13, count 0 2006.173.10:45:40.30#ibcon#about to read 3, iclass 13, count 0 2006.173.10:45:40.34#ibcon#read 3, iclass 13, count 0 2006.173.10:45:40.34#ibcon#about to read 4, iclass 13, count 0 2006.173.10:45:40.34#ibcon#read 4, iclass 13, count 0 2006.173.10:45:40.34#ibcon#about to read 5, iclass 13, count 0 2006.173.10:45:40.34#ibcon#read 5, iclass 13, count 0 2006.173.10:45:40.34#ibcon#about to read 6, iclass 13, count 0 2006.173.10:45:40.34#ibcon#read 6, iclass 13, count 0 2006.173.10:45:40.34#ibcon#end of sib2, iclass 13, count 0 2006.173.10:45:40.34#ibcon#*after write, iclass 13, count 0 2006.173.10:45:40.34#ibcon#*before return 0, iclass 13, count 0 2006.173.10:45:40.34#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.10:45:40.34#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.10:45:40.34#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.10:45:40.34#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.10:45:40.34$vck44/va=4,6 2006.173.10:45:40.34#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.10:45:40.34#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.10:45:40.34#ibcon#ireg 11 cls_cnt 2 2006.173.10:45:40.34#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.10:45:40.40#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.10:45:40.40#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.10:45:40.40#ibcon#enter wrdev, iclass 15, count 2 2006.173.10:45:40.40#ibcon#first serial, iclass 15, count 2 2006.173.10:45:40.40#ibcon#enter sib2, iclass 15, count 2 2006.173.10:45:40.40#ibcon#flushed, iclass 15, count 2 2006.173.10:45:40.40#ibcon#about to write, iclass 15, count 2 2006.173.10:45:40.40#ibcon#wrote, iclass 15, count 2 2006.173.10:45:40.40#ibcon#about to read 3, iclass 15, count 2 2006.173.10:45:40.42#ibcon#read 3, iclass 15, count 2 2006.173.10:45:40.42#ibcon#about to read 4, iclass 15, count 2 2006.173.10:45:40.42#ibcon#read 4, iclass 15, count 2 2006.173.10:45:40.42#ibcon#about to read 5, iclass 15, count 2 2006.173.10:45:40.42#ibcon#read 5, iclass 15, count 2 2006.173.10:45:40.42#ibcon#about to read 6, iclass 15, count 2 2006.173.10:45:40.42#ibcon#read 6, iclass 15, count 2 2006.173.10:45:40.42#ibcon#end of sib2, iclass 15, count 2 2006.173.10:45:40.42#ibcon#*mode == 0, iclass 15, count 2 2006.173.10:45:40.42#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.10:45:40.42#ibcon#[25=AT04-06\r\n] 2006.173.10:45:40.42#ibcon#*before write, iclass 15, count 2 2006.173.10:45:40.42#ibcon#enter sib2, iclass 15, count 2 2006.173.10:45:40.42#ibcon#flushed, iclass 15, count 2 2006.173.10:45:40.42#ibcon#about to write, iclass 15, count 2 2006.173.10:45:40.42#ibcon#wrote, iclass 15, count 2 2006.173.10:45:40.42#ibcon#about to read 3, iclass 15, count 2 2006.173.10:45:40.45#ibcon#read 3, iclass 15, count 2 2006.173.10:45:40.45#ibcon#about to read 4, iclass 15, count 2 2006.173.10:45:40.45#ibcon#read 4, iclass 15, count 2 2006.173.10:45:40.45#ibcon#about to read 5, iclass 15, count 2 2006.173.10:45:40.45#ibcon#read 5, iclass 15, count 2 2006.173.10:45:40.45#ibcon#about to read 6, iclass 15, count 2 2006.173.10:45:40.45#ibcon#read 6, iclass 15, count 2 2006.173.10:45:40.45#ibcon#end of sib2, iclass 15, count 2 2006.173.10:45:40.45#ibcon#*after write, iclass 15, count 2 2006.173.10:45:40.45#ibcon#*before return 0, iclass 15, count 2 2006.173.10:45:40.45#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.10:45:40.45#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.10:45:40.45#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.10:45:40.45#ibcon#ireg 7 cls_cnt 0 2006.173.10:45:40.45#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.10:45:40.57#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.10:45:40.57#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.10:45:40.57#ibcon#enter wrdev, iclass 15, count 0 2006.173.10:45:40.57#ibcon#first serial, iclass 15, count 0 2006.173.10:45:40.57#ibcon#enter sib2, iclass 15, count 0 2006.173.10:45:40.57#ibcon#flushed, iclass 15, count 0 2006.173.10:45:40.57#ibcon#about to write, iclass 15, count 0 2006.173.10:45:40.57#ibcon#wrote, iclass 15, count 0 2006.173.10:45:40.57#ibcon#about to read 3, iclass 15, count 0 2006.173.10:45:40.59#ibcon#read 3, iclass 15, count 0 2006.173.10:45:40.59#ibcon#about to read 4, iclass 15, count 0 2006.173.10:45:40.59#ibcon#read 4, iclass 15, count 0 2006.173.10:45:40.59#ibcon#about to read 5, iclass 15, count 0 2006.173.10:45:40.59#ibcon#read 5, iclass 15, count 0 2006.173.10:45:40.59#ibcon#about to read 6, iclass 15, count 0 2006.173.10:45:40.59#ibcon#read 6, iclass 15, count 0 2006.173.10:45:40.59#ibcon#end of sib2, iclass 15, count 0 2006.173.10:45:40.59#ibcon#*mode == 0, iclass 15, count 0 2006.173.10:45:40.59#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.10:45:40.59#ibcon#[25=USB\r\n] 2006.173.10:45:40.59#ibcon#*before write, iclass 15, count 0 2006.173.10:45:40.59#ibcon#enter sib2, iclass 15, count 0 2006.173.10:45:40.59#ibcon#flushed, iclass 15, count 0 2006.173.10:45:40.59#ibcon#about to write, iclass 15, count 0 2006.173.10:45:40.59#ibcon#wrote, iclass 15, count 0 2006.173.10:45:40.59#ibcon#about to read 3, iclass 15, count 0 2006.173.10:45:40.62#ibcon#read 3, iclass 15, count 0 2006.173.10:45:40.62#ibcon#about to read 4, iclass 15, count 0 2006.173.10:45:40.62#ibcon#read 4, iclass 15, count 0 2006.173.10:45:40.62#ibcon#about to read 5, iclass 15, count 0 2006.173.10:45:40.62#ibcon#read 5, iclass 15, count 0 2006.173.10:45:40.62#ibcon#about to read 6, iclass 15, count 0 2006.173.10:45:40.62#ibcon#read 6, iclass 15, count 0 2006.173.10:45:40.62#ibcon#end of sib2, iclass 15, count 0 2006.173.10:45:40.62#ibcon#*after write, iclass 15, count 0 2006.173.10:45:40.62#ibcon#*before return 0, iclass 15, count 0 2006.173.10:45:40.62#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.10:45:40.62#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.10:45:40.62#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.10:45:40.62#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.10:45:40.62$vck44/valo=5,734.99 2006.173.10:45:40.62#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.10:45:40.62#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.10:45:40.62#ibcon#ireg 17 cls_cnt 0 2006.173.10:45:40.62#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.10:45:40.62#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.10:45:40.62#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.10:45:40.62#ibcon#enter wrdev, iclass 17, count 0 2006.173.10:45:40.62#ibcon#first serial, iclass 17, count 0 2006.173.10:45:40.62#ibcon#enter sib2, iclass 17, count 0 2006.173.10:45:40.62#ibcon#flushed, iclass 17, count 0 2006.173.10:45:40.62#ibcon#about to write, iclass 17, count 0 2006.173.10:45:40.62#ibcon#wrote, iclass 17, count 0 2006.173.10:45:40.62#ibcon#about to read 3, iclass 17, count 0 2006.173.10:45:40.64#ibcon#read 3, iclass 17, count 0 2006.173.10:45:40.64#ibcon#about to read 4, iclass 17, count 0 2006.173.10:45:40.64#ibcon#read 4, iclass 17, count 0 2006.173.10:45:40.64#ibcon#about to read 5, iclass 17, count 0 2006.173.10:45:40.64#ibcon#read 5, iclass 17, count 0 2006.173.10:45:40.64#ibcon#about to read 6, iclass 17, count 0 2006.173.10:45:40.64#ibcon#read 6, iclass 17, count 0 2006.173.10:45:40.64#ibcon#end of sib2, iclass 17, count 0 2006.173.10:45:40.64#ibcon#*mode == 0, iclass 17, count 0 2006.173.10:45:40.64#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.10:45:40.64#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.10:45:40.64#ibcon#*before write, iclass 17, count 0 2006.173.10:45:40.64#ibcon#enter sib2, iclass 17, count 0 2006.173.10:45:40.64#ibcon#flushed, iclass 17, count 0 2006.173.10:45:40.64#ibcon#about to write, iclass 17, count 0 2006.173.10:45:40.64#ibcon#wrote, iclass 17, count 0 2006.173.10:45:40.64#ibcon#about to read 3, iclass 17, count 0 2006.173.10:45:40.68#ibcon#read 3, iclass 17, count 0 2006.173.10:45:40.68#ibcon#about to read 4, iclass 17, count 0 2006.173.10:45:40.68#ibcon#read 4, iclass 17, count 0 2006.173.10:45:40.68#ibcon#about to read 5, iclass 17, count 0 2006.173.10:45:40.68#ibcon#read 5, iclass 17, count 0 2006.173.10:45:40.68#ibcon#about to read 6, iclass 17, count 0 2006.173.10:45:40.68#ibcon#read 6, iclass 17, count 0 2006.173.10:45:40.68#ibcon#end of sib2, iclass 17, count 0 2006.173.10:45:40.68#ibcon#*after write, iclass 17, count 0 2006.173.10:45:40.68#ibcon#*before return 0, iclass 17, count 0 2006.173.10:45:40.68#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.10:45:40.68#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.10:45:40.68#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.10:45:40.68#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.10:45:40.68$vck44/va=5,4 2006.173.10:45:40.68#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.10:45:40.68#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.10:45:40.68#ibcon#ireg 11 cls_cnt 2 2006.173.10:45:40.68#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.10:45:40.74#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.10:45:40.74#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.10:45:40.74#ibcon#enter wrdev, iclass 19, count 2 2006.173.10:45:40.74#ibcon#first serial, iclass 19, count 2 2006.173.10:45:40.74#ibcon#enter sib2, iclass 19, count 2 2006.173.10:45:40.74#ibcon#flushed, iclass 19, count 2 2006.173.10:45:40.74#ibcon#about to write, iclass 19, count 2 2006.173.10:45:40.74#ibcon#wrote, iclass 19, count 2 2006.173.10:45:40.74#ibcon#about to read 3, iclass 19, count 2 2006.173.10:45:40.76#ibcon#read 3, iclass 19, count 2 2006.173.10:45:40.76#ibcon#about to read 4, iclass 19, count 2 2006.173.10:45:40.76#ibcon#read 4, iclass 19, count 2 2006.173.10:45:40.76#ibcon#about to read 5, iclass 19, count 2 2006.173.10:45:40.76#ibcon#read 5, iclass 19, count 2 2006.173.10:45:40.76#ibcon#about to read 6, iclass 19, count 2 2006.173.10:45:40.76#ibcon#read 6, iclass 19, count 2 2006.173.10:45:40.76#ibcon#end of sib2, iclass 19, count 2 2006.173.10:45:40.76#ibcon#*mode == 0, iclass 19, count 2 2006.173.10:45:40.76#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.10:45:40.76#ibcon#[25=AT05-04\r\n] 2006.173.10:45:40.76#ibcon#*before write, iclass 19, count 2 2006.173.10:45:40.76#ibcon#enter sib2, iclass 19, count 2 2006.173.10:45:40.76#ibcon#flushed, iclass 19, count 2 2006.173.10:45:40.76#ibcon#about to write, iclass 19, count 2 2006.173.10:45:40.76#ibcon#wrote, iclass 19, count 2 2006.173.10:45:40.76#ibcon#about to read 3, iclass 19, count 2 2006.173.10:45:40.79#ibcon#read 3, iclass 19, count 2 2006.173.10:45:40.79#ibcon#about to read 4, iclass 19, count 2 2006.173.10:45:40.79#ibcon#read 4, iclass 19, count 2 2006.173.10:45:40.79#ibcon#about to read 5, iclass 19, count 2 2006.173.10:45:40.79#ibcon#read 5, iclass 19, count 2 2006.173.10:45:40.79#ibcon#about to read 6, iclass 19, count 2 2006.173.10:45:40.79#ibcon#read 6, iclass 19, count 2 2006.173.10:45:40.79#ibcon#end of sib2, iclass 19, count 2 2006.173.10:45:40.79#ibcon#*after write, iclass 19, count 2 2006.173.10:45:40.79#ibcon#*before return 0, iclass 19, count 2 2006.173.10:45:40.79#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.10:45:40.79#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.10:45:40.79#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.10:45:40.79#ibcon#ireg 7 cls_cnt 0 2006.173.10:45:40.79#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.10:45:40.91#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.10:45:40.91#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.10:45:40.91#ibcon#enter wrdev, iclass 19, count 0 2006.173.10:45:40.91#ibcon#first serial, iclass 19, count 0 2006.173.10:45:40.91#ibcon#enter sib2, iclass 19, count 0 2006.173.10:45:40.91#ibcon#flushed, iclass 19, count 0 2006.173.10:45:40.91#ibcon#about to write, iclass 19, count 0 2006.173.10:45:40.91#ibcon#wrote, iclass 19, count 0 2006.173.10:45:40.91#ibcon#about to read 3, iclass 19, count 0 2006.173.10:45:40.93#ibcon#read 3, iclass 19, count 0 2006.173.10:45:40.93#ibcon#about to read 4, iclass 19, count 0 2006.173.10:45:40.93#ibcon#read 4, iclass 19, count 0 2006.173.10:45:40.93#ibcon#about to read 5, iclass 19, count 0 2006.173.10:45:40.93#ibcon#read 5, iclass 19, count 0 2006.173.10:45:40.93#ibcon#about to read 6, iclass 19, count 0 2006.173.10:45:40.93#ibcon#read 6, iclass 19, count 0 2006.173.10:45:40.93#ibcon#end of sib2, iclass 19, count 0 2006.173.10:45:40.93#ibcon#*mode == 0, iclass 19, count 0 2006.173.10:45:40.93#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.10:45:40.93#ibcon#[25=USB\r\n] 2006.173.10:45:40.93#ibcon#*before write, iclass 19, count 0 2006.173.10:45:40.93#ibcon#enter sib2, iclass 19, count 0 2006.173.10:45:40.93#ibcon#flushed, iclass 19, count 0 2006.173.10:45:40.93#ibcon#about to write, iclass 19, count 0 2006.173.10:45:40.93#ibcon#wrote, iclass 19, count 0 2006.173.10:45:40.93#ibcon#about to read 3, iclass 19, count 0 2006.173.10:45:40.96#ibcon#read 3, iclass 19, count 0 2006.173.10:45:40.96#ibcon#about to read 4, iclass 19, count 0 2006.173.10:45:40.96#ibcon#read 4, iclass 19, count 0 2006.173.10:45:40.96#ibcon#about to read 5, iclass 19, count 0 2006.173.10:45:40.96#ibcon#read 5, iclass 19, count 0 2006.173.10:45:40.96#ibcon#about to read 6, iclass 19, count 0 2006.173.10:45:40.96#ibcon#read 6, iclass 19, count 0 2006.173.10:45:40.96#ibcon#end of sib2, iclass 19, count 0 2006.173.10:45:40.96#ibcon#*after write, iclass 19, count 0 2006.173.10:45:40.96#ibcon#*before return 0, iclass 19, count 0 2006.173.10:45:40.96#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.10:45:40.96#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.10:45:40.96#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.10:45:40.96#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.10:45:40.96$vck44/valo=6,814.99 2006.173.10:45:40.96#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.10:45:40.96#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.10:45:40.96#ibcon#ireg 17 cls_cnt 0 2006.173.10:45:40.96#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.10:45:40.96#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.10:45:40.96#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.10:45:40.96#ibcon#enter wrdev, iclass 21, count 0 2006.173.10:45:40.96#ibcon#first serial, iclass 21, count 0 2006.173.10:45:40.96#ibcon#enter sib2, iclass 21, count 0 2006.173.10:45:40.96#ibcon#flushed, iclass 21, count 0 2006.173.10:45:40.96#ibcon#about to write, iclass 21, count 0 2006.173.10:45:40.96#ibcon#wrote, iclass 21, count 0 2006.173.10:45:40.96#ibcon#about to read 3, iclass 21, count 0 2006.173.10:45:40.98#ibcon#read 3, iclass 21, count 0 2006.173.10:45:40.98#ibcon#about to read 4, iclass 21, count 0 2006.173.10:45:40.98#ibcon#read 4, iclass 21, count 0 2006.173.10:45:40.98#ibcon#about to read 5, iclass 21, count 0 2006.173.10:45:40.98#ibcon#read 5, iclass 21, count 0 2006.173.10:45:40.98#ibcon#about to read 6, iclass 21, count 0 2006.173.10:45:40.98#ibcon#read 6, iclass 21, count 0 2006.173.10:45:40.98#ibcon#end of sib2, iclass 21, count 0 2006.173.10:45:40.98#ibcon#*mode == 0, iclass 21, count 0 2006.173.10:45:40.98#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.10:45:40.98#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.10:45:40.98#ibcon#*before write, iclass 21, count 0 2006.173.10:45:40.98#ibcon#enter sib2, iclass 21, count 0 2006.173.10:45:40.98#ibcon#flushed, iclass 21, count 0 2006.173.10:45:40.98#ibcon#about to write, iclass 21, count 0 2006.173.10:45:40.98#ibcon#wrote, iclass 21, count 0 2006.173.10:45:40.98#ibcon#about to read 3, iclass 21, count 0 2006.173.10:45:41.02#ibcon#read 3, iclass 21, count 0 2006.173.10:45:41.02#ibcon#about to read 4, iclass 21, count 0 2006.173.10:45:41.02#ibcon#read 4, iclass 21, count 0 2006.173.10:45:41.02#ibcon#about to read 5, iclass 21, count 0 2006.173.10:45:41.02#ibcon#read 5, iclass 21, count 0 2006.173.10:45:41.02#ibcon#about to read 6, iclass 21, count 0 2006.173.10:45:41.02#ibcon#read 6, iclass 21, count 0 2006.173.10:45:41.02#ibcon#end of sib2, iclass 21, count 0 2006.173.10:45:41.02#ibcon#*after write, iclass 21, count 0 2006.173.10:45:41.02#ibcon#*before return 0, iclass 21, count 0 2006.173.10:45:41.02#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.10:45:41.02#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.10:45:41.02#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.10:45:41.02#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.10:45:41.02$vck44/va=6,3 2006.173.10:45:41.02#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.10:45:41.02#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.10:45:41.02#ibcon#ireg 11 cls_cnt 2 2006.173.10:45:41.02#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.10:45:41.08#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.10:45:41.08#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.10:45:41.08#ibcon#enter wrdev, iclass 23, count 2 2006.173.10:45:41.08#ibcon#first serial, iclass 23, count 2 2006.173.10:45:41.08#ibcon#enter sib2, iclass 23, count 2 2006.173.10:45:41.08#ibcon#flushed, iclass 23, count 2 2006.173.10:45:41.08#ibcon#about to write, iclass 23, count 2 2006.173.10:45:41.08#ibcon#wrote, iclass 23, count 2 2006.173.10:45:41.08#ibcon#about to read 3, iclass 23, count 2 2006.173.10:45:41.10#ibcon#read 3, iclass 23, count 2 2006.173.10:45:41.10#ibcon#about to read 4, iclass 23, count 2 2006.173.10:45:41.10#ibcon#read 4, iclass 23, count 2 2006.173.10:45:41.10#ibcon#about to read 5, iclass 23, count 2 2006.173.10:45:41.10#ibcon#read 5, iclass 23, count 2 2006.173.10:45:41.10#ibcon#about to read 6, iclass 23, count 2 2006.173.10:45:41.10#ibcon#read 6, iclass 23, count 2 2006.173.10:45:41.10#ibcon#end of sib2, iclass 23, count 2 2006.173.10:45:41.10#ibcon#*mode == 0, iclass 23, count 2 2006.173.10:45:41.10#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.10:45:41.10#ibcon#[25=AT06-03\r\n] 2006.173.10:45:41.10#ibcon#*before write, iclass 23, count 2 2006.173.10:45:41.10#ibcon#enter sib2, iclass 23, count 2 2006.173.10:45:41.10#ibcon#flushed, iclass 23, count 2 2006.173.10:45:41.10#ibcon#about to write, iclass 23, count 2 2006.173.10:45:41.10#ibcon#wrote, iclass 23, count 2 2006.173.10:45:41.10#ibcon#about to read 3, iclass 23, count 2 2006.173.10:45:41.13#ibcon#read 3, iclass 23, count 2 2006.173.10:45:41.13#ibcon#about to read 4, iclass 23, count 2 2006.173.10:45:41.13#ibcon#read 4, iclass 23, count 2 2006.173.10:45:41.13#ibcon#about to read 5, iclass 23, count 2 2006.173.10:45:41.13#ibcon#read 5, iclass 23, count 2 2006.173.10:45:41.13#ibcon#about to read 6, iclass 23, count 2 2006.173.10:45:41.13#ibcon#read 6, iclass 23, count 2 2006.173.10:45:41.13#ibcon#end of sib2, iclass 23, count 2 2006.173.10:45:41.13#ibcon#*after write, iclass 23, count 2 2006.173.10:45:41.13#ibcon#*before return 0, iclass 23, count 2 2006.173.10:45:41.13#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.10:45:41.13#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.10:45:41.13#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.10:45:41.13#ibcon#ireg 7 cls_cnt 0 2006.173.10:45:41.13#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.10:45:41.25#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.10:45:41.25#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.10:45:41.25#ibcon#enter wrdev, iclass 23, count 0 2006.173.10:45:41.25#ibcon#first serial, iclass 23, count 0 2006.173.10:45:41.25#ibcon#enter sib2, iclass 23, count 0 2006.173.10:45:41.25#ibcon#flushed, iclass 23, count 0 2006.173.10:45:41.25#ibcon#about to write, iclass 23, count 0 2006.173.10:45:41.25#ibcon#wrote, iclass 23, count 0 2006.173.10:45:41.25#ibcon#about to read 3, iclass 23, count 0 2006.173.10:45:41.27#ibcon#read 3, iclass 23, count 0 2006.173.10:45:41.27#ibcon#about to read 4, iclass 23, count 0 2006.173.10:45:41.27#ibcon#read 4, iclass 23, count 0 2006.173.10:45:41.27#ibcon#about to read 5, iclass 23, count 0 2006.173.10:45:41.27#ibcon#read 5, iclass 23, count 0 2006.173.10:45:41.27#ibcon#about to read 6, iclass 23, count 0 2006.173.10:45:41.27#ibcon#read 6, iclass 23, count 0 2006.173.10:45:41.27#ibcon#end of sib2, iclass 23, count 0 2006.173.10:45:41.27#ibcon#*mode == 0, iclass 23, count 0 2006.173.10:45:41.27#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.10:45:41.27#ibcon#[25=USB\r\n] 2006.173.10:45:41.27#ibcon#*before write, iclass 23, count 0 2006.173.10:45:41.27#ibcon#enter sib2, iclass 23, count 0 2006.173.10:45:41.27#ibcon#flushed, iclass 23, count 0 2006.173.10:45:41.27#ibcon#about to write, iclass 23, count 0 2006.173.10:45:41.27#ibcon#wrote, iclass 23, count 0 2006.173.10:45:41.27#ibcon#about to read 3, iclass 23, count 0 2006.173.10:45:41.30#ibcon#read 3, iclass 23, count 0 2006.173.10:45:41.30#ibcon#about to read 4, iclass 23, count 0 2006.173.10:45:41.30#ibcon#read 4, iclass 23, count 0 2006.173.10:45:41.30#ibcon#about to read 5, iclass 23, count 0 2006.173.10:45:41.30#ibcon#read 5, iclass 23, count 0 2006.173.10:45:41.30#ibcon#about to read 6, iclass 23, count 0 2006.173.10:45:41.30#ibcon#read 6, iclass 23, count 0 2006.173.10:45:41.30#ibcon#end of sib2, iclass 23, count 0 2006.173.10:45:41.30#ibcon#*after write, iclass 23, count 0 2006.173.10:45:41.30#ibcon#*before return 0, iclass 23, count 0 2006.173.10:45:41.30#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.10:45:41.30#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.10:45:41.30#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.10:45:41.30#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.10:45:41.30$vck44/valo=7,864.99 2006.173.10:45:41.30#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.10:45:41.30#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.10:45:41.30#ibcon#ireg 17 cls_cnt 0 2006.173.10:45:41.30#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.10:45:41.30#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.10:45:41.30#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.10:45:41.30#ibcon#enter wrdev, iclass 25, count 0 2006.173.10:45:41.30#ibcon#first serial, iclass 25, count 0 2006.173.10:45:41.30#ibcon#enter sib2, iclass 25, count 0 2006.173.10:45:41.30#ibcon#flushed, iclass 25, count 0 2006.173.10:45:41.30#ibcon#about to write, iclass 25, count 0 2006.173.10:45:41.30#ibcon#wrote, iclass 25, count 0 2006.173.10:45:41.30#ibcon#about to read 3, iclass 25, count 0 2006.173.10:45:41.32#ibcon#read 3, iclass 25, count 0 2006.173.10:45:41.32#ibcon#about to read 4, iclass 25, count 0 2006.173.10:45:41.32#ibcon#read 4, iclass 25, count 0 2006.173.10:45:41.32#ibcon#about to read 5, iclass 25, count 0 2006.173.10:45:41.32#ibcon#read 5, iclass 25, count 0 2006.173.10:45:41.32#ibcon#about to read 6, iclass 25, count 0 2006.173.10:45:41.32#ibcon#read 6, iclass 25, count 0 2006.173.10:45:41.32#ibcon#end of sib2, iclass 25, count 0 2006.173.10:45:41.32#ibcon#*mode == 0, iclass 25, count 0 2006.173.10:45:41.32#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.10:45:41.32#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.10:45:41.32#ibcon#*before write, iclass 25, count 0 2006.173.10:45:41.32#ibcon#enter sib2, iclass 25, count 0 2006.173.10:45:41.32#ibcon#flushed, iclass 25, count 0 2006.173.10:45:41.32#ibcon#about to write, iclass 25, count 0 2006.173.10:45:41.32#ibcon#wrote, iclass 25, count 0 2006.173.10:45:41.32#ibcon#about to read 3, iclass 25, count 0 2006.173.10:45:41.36#ibcon#read 3, iclass 25, count 0 2006.173.10:45:41.36#ibcon#about to read 4, iclass 25, count 0 2006.173.10:45:41.36#ibcon#read 4, iclass 25, count 0 2006.173.10:45:41.36#ibcon#about to read 5, iclass 25, count 0 2006.173.10:45:41.36#ibcon#read 5, iclass 25, count 0 2006.173.10:45:41.36#ibcon#about to read 6, iclass 25, count 0 2006.173.10:45:41.36#ibcon#read 6, iclass 25, count 0 2006.173.10:45:41.36#ibcon#end of sib2, iclass 25, count 0 2006.173.10:45:41.36#ibcon#*after write, iclass 25, count 0 2006.173.10:45:41.36#ibcon#*before return 0, iclass 25, count 0 2006.173.10:45:41.36#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.10:45:41.36#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.10:45:41.36#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.10:45:41.36#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.10:45:41.36$vck44/va=7,4 2006.173.10:45:41.36#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.10:45:41.36#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.10:45:41.36#ibcon#ireg 11 cls_cnt 2 2006.173.10:45:41.36#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.10:45:41.42#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.10:45:41.42#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.10:45:41.42#ibcon#enter wrdev, iclass 27, count 2 2006.173.10:45:41.42#ibcon#first serial, iclass 27, count 2 2006.173.10:45:41.42#ibcon#enter sib2, iclass 27, count 2 2006.173.10:45:41.42#ibcon#flushed, iclass 27, count 2 2006.173.10:45:41.42#ibcon#about to write, iclass 27, count 2 2006.173.10:45:41.42#ibcon#wrote, iclass 27, count 2 2006.173.10:45:41.42#ibcon#about to read 3, iclass 27, count 2 2006.173.10:45:41.44#ibcon#read 3, iclass 27, count 2 2006.173.10:45:41.44#ibcon#about to read 4, iclass 27, count 2 2006.173.10:45:41.44#ibcon#read 4, iclass 27, count 2 2006.173.10:45:41.44#ibcon#about to read 5, iclass 27, count 2 2006.173.10:45:41.44#ibcon#read 5, iclass 27, count 2 2006.173.10:45:41.44#ibcon#about to read 6, iclass 27, count 2 2006.173.10:45:41.44#ibcon#read 6, iclass 27, count 2 2006.173.10:45:41.44#ibcon#end of sib2, iclass 27, count 2 2006.173.10:45:41.44#ibcon#*mode == 0, iclass 27, count 2 2006.173.10:45:41.44#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.10:45:41.44#ibcon#[25=AT07-04\r\n] 2006.173.10:45:41.44#ibcon#*before write, iclass 27, count 2 2006.173.10:45:41.44#ibcon#enter sib2, iclass 27, count 2 2006.173.10:45:41.44#ibcon#flushed, iclass 27, count 2 2006.173.10:45:41.44#ibcon#about to write, iclass 27, count 2 2006.173.10:45:41.44#ibcon#wrote, iclass 27, count 2 2006.173.10:45:41.44#ibcon#about to read 3, iclass 27, count 2 2006.173.10:45:41.47#ibcon#read 3, iclass 27, count 2 2006.173.10:45:41.47#ibcon#about to read 4, iclass 27, count 2 2006.173.10:45:41.47#ibcon#read 4, iclass 27, count 2 2006.173.10:45:41.47#ibcon#about to read 5, iclass 27, count 2 2006.173.10:45:41.47#ibcon#read 5, iclass 27, count 2 2006.173.10:45:41.47#ibcon#about to read 6, iclass 27, count 2 2006.173.10:45:41.47#ibcon#read 6, iclass 27, count 2 2006.173.10:45:41.47#ibcon#end of sib2, iclass 27, count 2 2006.173.10:45:41.47#ibcon#*after write, iclass 27, count 2 2006.173.10:45:41.47#ibcon#*before return 0, iclass 27, count 2 2006.173.10:45:41.47#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.10:45:41.47#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.10:45:41.47#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.10:45:41.47#ibcon#ireg 7 cls_cnt 0 2006.173.10:45:41.47#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.10:45:41.59#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.10:45:41.59#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.10:45:41.59#ibcon#enter wrdev, iclass 27, count 0 2006.173.10:45:41.59#ibcon#first serial, iclass 27, count 0 2006.173.10:45:41.59#ibcon#enter sib2, iclass 27, count 0 2006.173.10:45:41.59#ibcon#flushed, iclass 27, count 0 2006.173.10:45:41.59#ibcon#about to write, iclass 27, count 0 2006.173.10:45:41.59#ibcon#wrote, iclass 27, count 0 2006.173.10:45:41.59#ibcon#about to read 3, iclass 27, count 0 2006.173.10:45:41.61#ibcon#read 3, iclass 27, count 0 2006.173.10:45:41.61#ibcon#about to read 4, iclass 27, count 0 2006.173.10:45:41.61#ibcon#read 4, iclass 27, count 0 2006.173.10:45:41.61#ibcon#about to read 5, iclass 27, count 0 2006.173.10:45:41.61#ibcon#read 5, iclass 27, count 0 2006.173.10:45:41.61#ibcon#about to read 6, iclass 27, count 0 2006.173.10:45:41.61#ibcon#read 6, iclass 27, count 0 2006.173.10:45:41.61#ibcon#end of sib2, iclass 27, count 0 2006.173.10:45:41.61#ibcon#*mode == 0, iclass 27, count 0 2006.173.10:45:41.61#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.10:45:41.61#ibcon#[25=USB\r\n] 2006.173.10:45:41.61#ibcon#*before write, iclass 27, count 0 2006.173.10:45:41.61#ibcon#enter sib2, iclass 27, count 0 2006.173.10:45:41.61#ibcon#flushed, iclass 27, count 0 2006.173.10:45:41.61#ibcon#about to write, iclass 27, count 0 2006.173.10:45:41.61#ibcon#wrote, iclass 27, count 0 2006.173.10:45:41.61#ibcon#about to read 3, iclass 27, count 0 2006.173.10:45:41.64#ibcon#read 3, iclass 27, count 0 2006.173.10:45:41.64#ibcon#about to read 4, iclass 27, count 0 2006.173.10:45:41.64#ibcon#read 4, iclass 27, count 0 2006.173.10:45:41.64#ibcon#about to read 5, iclass 27, count 0 2006.173.10:45:41.64#ibcon#read 5, iclass 27, count 0 2006.173.10:45:41.64#ibcon#about to read 6, iclass 27, count 0 2006.173.10:45:41.64#ibcon#read 6, iclass 27, count 0 2006.173.10:45:41.64#ibcon#end of sib2, iclass 27, count 0 2006.173.10:45:41.64#ibcon#*after write, iclass 27, count 0 2006.173.10:45:41.64#ibcon#*before return 0, iclass 27, count 0 2006.173.10:45:41.64#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.10:45:41.64#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.10:45:41.64#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.10:45:41.64#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.10:45:41.64$vck44/valo=8,884.99 2006.173.10:45:41.64#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.10:45:41.64#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.10:45:41.64#ibcon#ireg 17 cls_cnt 0 2006.173.10:45:41.64#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.10:45:41.64#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.10:45:41.64#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.10:45:41.64#ibcon#enter wrdev, iclass 29, count 0 2006.173.10:45:41.64#ibcon#first serial, iclass 29, count 0 2006.173.10:45:41.64#ibcon#enter sib2, iclass 29, count 0 2006.173.10:45:41.64#ibcon#flushed, iclass 29, count 0 2006.173.10:45:41.64#ibcon#about to write, iclass 29, count 0 2006.173.10:45:41.64#ibcon#wrote, iclass 29, count 0 2006.173.10:45:41.64#ibcon#about to read 3, iclass 29, count 0 2006.173.10:45:41.66#ibcon#read 3, iclass 29, count 0 2006.173.10:45:41.66#ibcon#about to read 4, iclass 29, count 0 2006.173.10:45:41.66#ibcon#read 4, iclass 29, count 0 2006.173.10:45:41.66#ibcon#about to read 5, iclass 29, count 0 2006.173.10:45:41.66#ibcon#read 5, iclass 29, count 0 2006.173.10:45:41.66#ibcon#about to read 6, iclass 29, count 0 2006.173.10:45:41.66#ibcon#read 6, iclass 29, count 0 2006.173.10:45:41.66#ibcon#end of sib2, iclass 29, count 0 2006.173.10:45:41.66#ibcon#*mode == 0, iclass 29, count 0 2006.173.10:45:41.66#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.10:45:41.66#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.10:45:41.66#ibcon#*before write, iclass 29, count 0 2006.173.10:45:41.66#ibcon#enter sib2, iclass 29, count 0 2006.173.10:45:41.66#ibcon#flushed, iclass 29, count 0 2006.173.10:45:41.66#ibcon#about to write, iclass 29, count 0 2006.173.10:45:41.66#ibcon#wrote, iclass 29, count 0 2006.173.10:45:41.66#ibcon#about to read 3, iclass 29, count 0 2006.173.10:45:41.70#ibcon#read 3, iclass 29, count 0 2006.173.10:45:41.70#ibcon#about to read 4, iclass 29, count 0 2006.173.10:45:41.70#ibcon#read 4, iclass 29, count 0 2006.173.10:45:41.70#ibcon#about to read 5, iclass 29, count 0 2006.173.10:45:41.70#ibcon#read 5, iclass 29, count 0 2006.173.10:45:41.70#ibcon#about to read 6, iclass 29, count 0 2006.173.10:45:41.70#ibcon#read 6, iclass 29, count 0 2006.173.10:45:41.70#ibcon#end of sib2, iclass 29, count 0 2006.173.10:45:41.70#ibcon#*after write, iclass 29, count 0 2006.173.10:45:41.70#ibcon#*before return 0, iclass 29, count 0 2006.173.10:45:41.70#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.10:45:41.70#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.10:45:41.70#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.10:45:41.70#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.10:45:41.70$vck44/va=8,4 2006.173.10:45:41.70#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.10:45:41.70#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.10:45:41.70#ibcon#ireg 11 cls_cnt 2 2006.173.10:45:41.70#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.10:45:41.76#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.10:45:41.76#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.10:45:41.76#ibcon#enter wrdev, iclass 31, count 2 2006.173.10:45:41.76#ibcon#first serial, iclass 31, count 2 2006.173.10:45:41.76#ibcon#enter sib2, iclass 31, count 2 2006.173.10:45:41.76#ibcon#flushed, iclass 31, count 2 2006.173.10:45:41.76#ibcon#about to write, iclass 31, count 2 2006.173.10:45:41.76#ibcon#wrote, iclass 31, count 2 2006.173.10:45:41.76#ibcon#about to read 3, iclass 31, count 2 2006.173.10:45:41.78#ibcon#read 3, iclass 31, count 2 2006.173.10:45:41.78#ibcon#about to read 4, iclass 31, count 2 2006.173.10:45:41.78#ibcon#read 4, iclass 31, count 2 2006.173.10:45:41.78#ibcon#about to read 5, iclass 31, count 2 2006.173.10:45:41.78#ibcon#read 5, iclass 31, count 2 2006.173.10:45:41.78#ibcon#about to read 6, iclass 31, count 2 2006.173.10:45:41.78#ibcon#read 6, iclass 31, count 2 2006.173.10:45:41.78#ibcon#end of sib2, iclass 31, count 2 2006.173.10:45:41.78#ibcon#*mode == 0, iclass 31, count 2 2006.173.10:45:41.78#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.10:45:41.78#ibcon#[25=AT08-04\r\n] 2006.173.10:45:41.78#ibcon#*before write, iclass 31, count 2 2006.173.10:45:41.78#ibcon#enter sib2, iclass 31, count 2 2006.173.10:45:41.78#ibcon#flushed, iclass 31, count 2 2006.173.10:45:41.78#ibcon#about to write, iclass 31, count 2 2006.173.10:45:41.78#ibcon#wrote, iclass 31, count 2 2006.173.10:45:41.78#ibcon#about to read 3, iclass 31, count 2 2006.173.10:45:41.81#ibcon#read 3, iclass 31, count 2 2006.173.10:45:41.81#ibcon#about to read 4, iclass 31, count 2 2006.173.10:45:41.81#ibcon#read 4, iclass 31, count 2 2006.173.10:45:41.81#ibcon#about to read 5, iclass 31, count 2 2006.173.10:45:41.81#ibcon#read 5, iclass 31, count 2 2006.173.10:45:41.81#ibcon#about to read 6, iclass 31, count 2 2006.173.10:45:41.81#ibcon#read 6, iclass 31, count 2 2006.173.10:45:41.81#ibcon#end of sib2, iclass 31, count 2 2006.173.10:45:41.81#ibcon#*after write, iclass 31, count 2 2006.173.10:45:41.81#ibcon#*before return 0, iclass 31, count 2 2006.173.10:45:41.81#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.10:45:41.81#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.10:45:41.81#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.10:45:41.81#ibcon#ireg 7 cls_cnt 0 2006.173.10:45:41.81#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.10:45:41.93#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.10:45:41.93#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.10:45:41.93#ibcon#enter wrdev, iclass 31, count 0 2006.173.10:45:41.93#ibcon#first serial, iclass 31, count 0 2006.173.10:45:41.93#ibcon#enter sib2, iclass 31, count 0 2006.173.10:45:41.93#ibcon#flushed, iclass 31, count 0 2006.173.10:45:41.93#ibcon#about to write, iclass 31, count 0 2006.173.10:45:41.93#ibcon#wrote, iclass 31, count 0 2006.173.10:45:41.93#ibcon#about to read 3, iclass 31, count 0 2006.173.10:45:41.95#ibcon#read 3, iclass 31, count 0 2006.173.10:45:41.95#ibcon#about to read 4, iclass 31, count 0 2006.173.10:45:41.95#ibcon#read 4, iclass 31, count 0 2006.173.10:45:41.95#ibcon#about to read 5, iclass 31, count 0 2006.173.10:45:41.95#ibcon#read 5, iclass 31, count 0 2006.173.10:45:41.95#ibcon#about to read 6, iclass 31, count 0 2006.173.10:45:41.95#ibcon#read 6, iclass 31, count 0 2006.173.10:45:41.95#ibcon#end of sib2, iclass 31, count 0 2006.173.10:45:41.95#ibcon#*mode == 0, iclass 31, count 0 2006.173.10:45:41.95#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.10:45:41.95#ibcon#[25=USB\r\n] 2006.173.10:45:41.95#ibcon#*before write, iclass 31, count 0 2006.173.10:45:41.95#ibcon#enter sib2, iclass 31, count 0 2006.173.10:45:41.95#ibcon#flushed, iclass 31, count 0 2006.173.10:45:41.95#ibcon#about to write, iclass 31, count 0 2006.173.10:45:41.95#ibcon#wrote, iclass 31, count 0 2006.173.10:45:41.95#ibcon#about to read 3, iclass 31, count 0 2006.173.10:45:41.98#ibcon#read 3, iclass 31, count 0 2006.173.10:45:41.98#ibcon#about to read 4, iclass 31, count 0 2006.173.10:45:41.98#ibcon#read 4, iclass 31, count 0 2006.173.10:45:41.98#ibcon#about to read 5, iclass 31, count 0 2006.173.10:45:41.98#ibcon#read 5, iclass 31, count 0 2006.173.10:45:41.98#ibcon#about to read 6, iclass 31, count 0 2006.173.10:45:41.98#ibcon#read 6, iclass 31, count 0 2006.173.10:45:41.98#ibcon#end of sib2, iclass 31, count 0 2006.173.10:45:41.98#ibcon#*after write, iclass 31, count 0 2006.173.10:45:41.98#ibcon#*before return 0, iclass 31, count 0 2006.173.10:45:41.98#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.10:45:41.98#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.10:45:41.98#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.10:45:41.98#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.10:45:41.98$vck44/vblo=1,629.99 2006.173.10:45:41.98#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.10:45:41.98#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.10:45:41.98#ibcon#ireg 17 cls_cnt 0 2006.173.10:45:41.98#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.10:45:41.98#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.10:45:41.98#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.10:45:41.98#ibcon#enter wrdev, iclass 33, count 0 2006.173.10:45:41.98#ibcon#first serial, iclass 33, count 0 2006.173.10:45:41.98#ibcon#enter sib2, iclass 33, count 0 2006.173.10:45:41.98#ibcon#flushed, iclass 33, count 0 2006.173.10:45:41.98#ibcon#about to write, iclass 33, count 0 2006.173.10:45:41.98#ibcon#wrote, iclass 33, count 0 2006.173.10:45:41.98#ibcon#about to read 3, iclass 33, count 0 2006.173.10:45:42.00#ibcon#read 3, iclass 33, count 0 2006.173.10:45:42.00#ibcon#about to read 4, iclass 33, count 0 2006.173.10:45:42.00#ibcon#read 4, iclass 33, count 0 2006.173.10:45:42.00#ibcon#about to read 5, iclass 33, count 0 2006.173.10:45:42.00#ibcon#read 5, iclass 33, count 0 2006.173.10:45:42.00#ibcon#about to read 6, iclass 33, count 0 2006.173.10:45:42.00#ibcon#read 6, iclass 33, count 0 2006.173.10:45:42.00#ibcon#end of sib2, iclass 33, count 0 2006.173.10:45:42.00#ibcon#*mode == 0, iclass 33, count 0 2006.173.10:45:42.00#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.10:45:42.00#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.10:45:42.00#ibcon#*before write, iclass 33, count 0 2006.173.10:45:42.00#ibcon#enter sib2, iclass 33, count 0 2006.173.10:45:42.00#ibcon#flushed, iclass 33, count 0 2006.173.10:45:42.00#ibcon#about to write, iclass 33, count 0 2006.173.10:45:42.00#ibcon#wrote, iclass 33, count 0 2006.173.10:45:42.00#ibcon#about to read 3, iclass 33, count 0 2006.173.10:45:42.04#ibcon#read 3, iclass 33, count 0 2006.173.10:45:42.04#ibcon#about to read 4, iclass 33, count 0 2006.173.10:45:42.04#ibcon#read 4, iclass 33, count 0 2006.173.10:45:42.04#ibcon#about to read 5, iclass 33, count 0 2006.173.10:45:42.04#ibcon#read 5, iclass 33, count 0 2006.173.10:45:42.04#ibcon#about to read 6, iclass 33, count 0 2006.173.10:45:42.04#ibcon#read 6, iclass 33, count 0 2006.173.10:45:42.04#ibcon#end of sib2, iclass 33, count 0 2006.173.10:45:42.04#ibcon#*after write, iclass 33, count 0 2006.173.10:45:42.04#ibcon#*before return 0, iclass 33, count 0 2006.173.10:45:42.04#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.10:45:42.04#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.10:45:42.04#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.10:45:42.04#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.10:45:42.04$vck44/vb=1,4 2006.173.10:45:42.04#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.10:45:42.04#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.10:45:42.04#ibcon#ireg 11 cls_cnt 2 2006.173.10:45:42.04#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.10:45:42.04#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.10:45:42.04#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.10:45:42.04#ibcon#enter wrdev, iclass 35, count 2 2006.173.10:45:42.04#ibcon#first serial, iclass 35, count 2 2006.173.10:45:42.04#ibcon#enter sib2, iclass 35, count 2 2006.173.10:45:42.04#ibcon#flushed, iclass 35, count 2 2006.173.10:45:42.04#ibcon#about to write, iclass 35, count 2 2006.173.10:45:42.04#ibcon#wrote, iclass 35, count 2 2006.173.10:45:42.04#ibcon#about to read 3, iclass 35, count 2 2006.173.10:45:42.06#ibcon#read 3, iclass 35, count 2 2006.173.10:45:42.06#ibcon#about to read 4, iclass 35, count 2 2006.173.10:45:42.06#ibcon#read 4, iclass 35, count 2 2006.173.10:45:42.06#ibcon#about to read 5, iclass 35, count 2 2006.173.10:45:42.06#ibcon#read 5, iclass 35, count 2 2006.173.10:45:42.06#ibcon#about to read 6, iclass 35, count 2 2006.173.10:45:42.06#ibcon#read 6, iclass 35, count 2 2006.173.10:45:42.06#ibcon#end of sib2, iclass 35, count 2 2006.173.10:45:42.06#ibcon#*mode == 0, iclass 35, count 2 2006.173.10:45:42.06#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.10:45:42.06#ibcon#[27=AT01-04\r\n] 2006.173.10:45:42.06#ibcon#*before write, iclass 35, count 2 2006.173.10:45:42.06#ibcon#enter sib2, iclass 35, count 2 2006.173.10:45:42.06#ibcon#flushed, iclass 35, count 2 2006.173.10:45:42.06#ibcon#about to write, iclass 35, count 2 2006.173.10:45:42.06#ibcon#wrote, iclass 35, count 2 2006.173.10:45:42.06#ibcon#about to read 3, iclass 35, count 2 2006.173.10:45:42.09#ibcon#read 3, iclass 35, count 2 2006.173.10:45:42.09#ibcon#about to read 4, iclass 35, count 2 2006.173.10:45:42.09#ibcon#read 4, iclass 35, count 2 2006.173.10:45:42.09#ibcon#about to read 5, iclass 35, count 2 2006.173.10:45:42.09#ibcon#read 5, iclass 35, count 2 2006.173.10:45:42.09#ibcon#about to read 6, iclass 35, count 2 2006.173.10:45:42.09#ibcon#read 6, iclass 35, count 2 2006.173.10:45:42.09#ibcon#end of sib2, iclass 35, count 2 2006.173.10:45:42.09#ibcon#*after write, iclass 35, count 2 2006.173.10:45:42.09#ibcon#*before return 0, iclass 35, count 2 2006.173.10:45:42.09#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.10:45:42.09#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.10:45:42.09#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.10:45:42.09#ibcon#ireg 7 cls_cnt 0 2006.173.10:45:42.09#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.10:45:42.21#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.10:45:42.21#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.10:45:42.21#ibcon#enter wrdev, iclass 35, count 0 2006.173.10:45:42.21#ibcon#first serial, iclass 35, count 0 2006.173.10:45:42.21#ibcon#enter sib2, iclass 35, count 0 2006.173.10:45:42.21#ibcon#flushed, iclass 35, count 0 2006.173.10:45:42.21#ibcon#about to write, iclass 35, count 0 2006.173.10:45:42.21#ibcon#wrote, iclass 35, count 0 2006.173.10:45:42.21#ibcon#about to read 3, iclass 35, count 0 2006.173.10:45:42.23#ibcon#read 3, iclass 35, count 0 2006.173.10:45:42.23#ibcon#about to read 4, iclass 35, count 0 2006.173.10:45:42.23#ibcon#read 4, iclass 35, count 0 2006.173.10:45:42.23#ibcon#about to read 5, iclass 35, count 0 2006.173.10:45:42.23#ibcon#read 5, iclass 35, count 0 2006.173.10:45:42.23#ibcon#about to read 6, iclass 35, count 0 2006.173.10:45:42.23#ibcon#read 6, iclass 35, count 0 2006.173.10:45:42.23#ibcon#end of sib2, iclass 35, count 0 2006.173.10:45:42.23#ibcon#*mode == 0, iclass 35, count 0 2006.173.10:45:42.23#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.10:45:42.23#ibcon#[27=USB\r\n] 2006.173.10:45:42.23#ibcon#*before write, iclass 35, count 0 2006.173.10:45:42.23#ibcon#enter sib2, iclass 35, count 0 2006.173.10:45:42.23#ibcon#flushed, iclass 35, count 0 2006.173.10:45:42.23#ibcon#about to write, iclass 35, count 0 2006.173.10:45:42.23#ibcon#wrote, iclass 35, count 0 2006.173.10:45:42.23#ibcon#about to read 3, iclass 35, count 0 2006.173.10:45:42.26#ibcon#read 3, iclass 35, count 0 2006.173.10:45:42.26#ibcon#about to read 4, iclass 35, count 0 2006.173.10:45:42.26#ibcon#read 4, iclass 35, count 0 2006.173.10:45:42.26#ibcon#about to read 5, iclass 35, count 0 2006.173.10:45:42.26#ibcon#read 5, iclass 35, count 0 2006.173.10:45:42.26#ibcon#about to read 6, iclass 35, count 0 2006.173.10:45:42.26#ibcon#read 6, iclass 35, count 0 2006.173.10:45:42.26#ibcon#end of sib2, iclass 35, count 0 2006.173.10:45:42.26#ibcon#*after write, iclass 35, count 0 2006.173.10:45:42.26#ibcon#*before return 0, iclass 35, count 0 2006.173.10:45:42.26#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.10:45:42.26#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.10:45:42.26#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.10:45:42.26#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.10:45:42.26$vck44/vblo=2,634.99 2006.173.10:45:42.26#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.10:45:42.26#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.10:45:42.26#ibcon#ireg 17 cls_cnt 0 2006.173.10:45:42.26#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.10:45:42.26#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.10:45:42.26#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.10:45:42.26#ibcon#enter wrdev, iclass 37, count 0 2006.173.10:45:42.26#ibcon#first serial, iclass 37, count 0 2006.173.10:45:42.26#ibcon#enter sib2, iclass 37, count 0 2006.173.10:45:42.26#ibcon#flushed, iclass 37, count 0 2006.173.10:45:42.26#ibcon#about to write, iclass 37, count 0 2006.173.10:45:42.26#ibcon#wrote, iclass 37, count 0 2006.173.10:45:42.26#ibcon#about to read 3, iclass 37, count 0 2006.173.10:45:42.28#ibcon#read 3, iclass 37, count 0 2006.173.10:45:42.28#ibcon#about to read 4, iclass 37, count 0 2006.173.10:45:42.28#ibcon#read 4, iclass 37, count 0 2006.173.10:45:42.28#ibcon#about to read 5, iclass 37, count 0 2006.173.10:45:42.28#ibcon#read 5, iclass 37, count 0 2006.173.10:45:42.28#ibcon#about to read 6, iclass 37, count 0 2006.173.10:45:42.28#ibcon#read 6, iclass 37, count 0 2006.173.10:45:42.28#ibcon#end of sib2, iclass 37, count 0 2006.173.10:45:42.28#ibcon#*mode == 0, iclass 37, count 0 2006.173.10:45:42.28#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.10:45:42.28#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.10:45:42.28#ibcon#*before write, iclass 37, count 0 2006.173.10:45:42.28#ibcon#enter sib2, iclass 37, count 0 2006.173.10:45:42.28#ibcon#flushed, iclass 37, count 0 2006.173.10:45:42.28#ibcon#about to write, iclass 37, count 0 2006.173.10:45:42.28#ibcon#wrote, iclass 37, count 0 2006.173.10:45:42.28#ibcon#about to read 3, iclass 37, count 0 2006.173.10:45:42.32#ibcon#read 3, iclass 37, count 0 2006.173.10:45:42.32#ibcon#about to read 4, iclass 37, count 0 2006.173.10:45:42.32#ibcon#read 4, iclass 37, count 0 2006.173.10:45:42.32#ibcon#about to read 5, iclass 37, count 0 2006.173.10:45:42.32#ibcon#read 5, iclass 37, count 0 2006.173.10:45:42.32#ibcon#about to read 6, iclass 37, count 0 2006.173.10:45:42.32#ibcon#read 6, iclass 37, count 0 2006.173.10:45:42.32#ibcon#end of sib2, iclass 37, count 0 2006.173.10:45:42.32#ibcon#*after write, iclass 37, count 0 2006.173.10:45:42.32#ibcon#*before return 0, iclass 37, count 0 2006.173.10:45:42.32#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.10:45:42.32#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.10:45:42.32#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.10:45:42.32#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.10:45:42.32$vck44/vb=2,4 2006.173.10:45:42.32#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.10:45:42.32#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.10:45:42.32#ibcon#ireg 11 cls_cnt 2 2006.173.10:45:42.32#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.10:45:42.38#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.10:45:42.38#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.10:45:42.38#ibcon#enter wrdev, iclass 39, count 2 2006.173.10:45:42.38#ibcon#first serial, iclass 39, count 2 2006.173.10:45:42.38#ibcon#enter sib2, iclass 39, count 2 2006.173.10:45:42.38#ibcon#flushed, iclass 39, count 2 2006.173.10:45:42.38#ibcon#about to write, iclass 39, count 2 2006.173.10:45:42.38#ibcon#wrote, iclass 39, count 2 2006.173.10:45:42.38#ibcon#about to read 3, iclass 39, count 2 2006.173.10:45:42.40#ibcon#read 3, iclass 39, count 2 2006.173.10:45:42.40#ibcon#about to read 4, iclass 39, count 2 2006.173.10:45:42.40#ibcon#read 4, iclass 39, count 2 2006.173.10:45:42.40#ibcon#about to read 5, iclass 39, count 2 2006.173.10:45:42.40#ibcon#read 5, iclass 39, count 2 2006.173.10:45:42.40#ibcon#about to read 6, iclass 39, count 2 2006.173.10:45:42.40#ibcon#read 6, iclass 39, count 2 2006.173.10:45:42.40#ibcon#end of sib2, iclass 39, count 2 2006.173.10:45:42.40#ibcon#*mode == 0, iclass 39, count 2 2006.173.10:45:42.40#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.10:45:42.40#ibcon#[27=AT02-04\r\n] 2006.173.10:45:42.40#ibcon#*before write, iclass 39, count 2 2006.173.10:45:42.40#ibcon#enter sib2, iclass 39, count 2 2006.173.10:45:42.40#ibcon#flushed, iclass 39, count 2 2006.173.10:45:42.40#ibcon#about to write, iclass 39, count 2 2006.173.10:45:42.40#ibcon#wrote, iclass 39, count 2 2006.173.10:45:42.40#ibcon#about to read 3, iclass 39, count 2 2006.173.10:45:42.43#ibcon#read 3, iclass 39, count 2 2006.173.10:45:42.43#ibcon#about to read 4, iclass 39, count 2 2006.173.10:45:42.43#ibcon#read 4, iclass 39, count 2 2006.173.10:45:42.43#ibcon#about to read 5, iclass 39, count 2 2006.173.10:45:42.43#ibcon#read 5, iclass 39, count 2 2006.173.10:45:42.43#ibcon#about to read 6, iclass 39, count 2 2006.173.10:45:42.43#ibcon#read 6, iclass 39, count 2 2006.173.10:45:42.43#ibcon#end of sib2, iclass 39, count 2 2006.173.10:45:42.43#ibcon#*after write, iclass 39, count 2 2006.173.10:45:42.43#ibcon#*before return 0, iclass 39, count 2 2006.173.10:45:42.43#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.10:45:42.43#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.10:45:42.43#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.10:45:42.43#ibcon#ireg 7 cls_cnt 0 2006.173.10:45:42.43#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.10:45:42.55#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.10:45:42.55#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.10:45:42.55#ibcon#enter wrdev, iclass 39, count 0 2006.173.10:45:42.55#ibcon#first serial, iclass 39, count 0 2006.173.10:45:42.55#ibcon#enter sib2, iclass 39, count 0 2006.173.10:45:42.55#ibcon#flushed, iclass 39, count 0 2006.173.10:45:42.55#ibcon#about to write, iclass 39, count 0 2006.173.10:45:42.55#ibcon#wrote, iclass 39, count 0 2006.173.10:45:42.55#ibcon#about to read 3, iclass 39, count 0 2006.173.10:45:42.57#ibcon#read 3, iclass 39, count 0 2006.173.10:45:42.57#ibcon#about to read 4, iclass 39, count 0 2006.173.10:45:42.57#ibcon#read 4, iclass 39, count 0 2006.173.10:45:42.57#ibcon#about to read 5, iclass 39, count 0 2006.173.10:45:42.57#ibcon#read 5, iclass 39, count 0 2006.173.10:45:42.57#ibcon#about to read 6, iclass 39, count 0 2006.173.10:45:42.57#ibcon#read 6, iclass 39, count 0 2006.173.10:45:42.57#ibcon#end of sib2, iclass 39, count 0 2006.173.10:45:42.57#ibcon#*mode == 0, iclass 39, count 0 2006.173.10:45:42.57#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.10:45:42.57#ibcon#[27=USB\r\n] 2006.173.10:45:42.57#ibcon#*before write, iclass 39, count 0 2006.173.10:45:42.57#ibcon#enter sib2, iclass 39, count 0 2006.173.10:45:42.57#ibcon#flushed, iclass 39, count 0 2006.173.10:45:42.57#ibcon#about to write, iclass 39, count 0 2006.173.10:45:42.57#ibcon#wrote, iclass 39, count 0 2006.173.10:45:42.57#ibcon#about to read 3, iclass 39, count 0 2006.173.10:45:42.60#ibcon#read 3, iclass 39, count 0 2006.173.10:45:42.60#ibcon#about to read 4, iclass 39, count 0 2006.173.10:45:42.60#ibcon#read 4, iclass 39, count 0 2006.173.10:45:42.60#ibcon#about to read 5, iclass 39, count 0 2006.173.10:45:42.60#ibcon#read 5, iclass 39, count 0 2006.173.10:45:42.60#ibcon#about to read 6, iclass 39, count 0 2006.173.10:45:42.60#ibcon#read 6, iclass 39, count 0 2006.173.10:45:42.60#ibcon#end of sib2, iclass 39, count 0 2006.173.10:45:42.60#ibcon#*after write, iclass 39, count 0 2006.173.10:45:42.60#ibcon#*before return 0, iclass 39, count 0 2006.173.10:45:42.60#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.10:45:42.60#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.10:45:42.60#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.10:45:42.60#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.10:45:42.60$vck44/vblo=3,649.99 2006.173.10:45:42.60#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.10:45:42.60#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.10:45:42.60#ibcon#ireg 17 cls_cnt 0 2006.173.10:45:42.60#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.10:45:42.60#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.10:45:42.60#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.10:45:42.60#ibcon#enter wrdev, iclass 3, count 0 2006.173.10:45:42.60#ibcon#first serial, iclass 3, count 0 2006.173.10:45:42.60#ibcon#enter sib2, iclass 3, count 0 2006.173.10:45:42.60#ibcon#flushed, iclass 3, count 0 2006.173.10:45:42.60#ibcon#about to write, iclass 3, count 0 2006.173.10:45:42.60#ibcon#wrote, iclass 3, count 0 2006.173.10:45:42.60#ibcon#about to read 3, iclass 3, count 0 2006.173.10:45:42.62#ibcon#read 3, iclass 3, count 0 2006.173.10:45:42.62#ibcon#about to read 4, iclass 3, count 0 2006.173.10:45:42.62#ibcon#read 4, iclass 3, count 0 2006.173.10:45:42.62#ibcon#about to read 5, iclass 3, count 0 2006.173.10:45:42.62#ibcon#read 5, iclass 3, count 0 2006.173.10:45:42.62#ibcon#about to read 6, iclass 3, count 0 2006.173.10:45:42.62#ibcon#read 6, iclass 3, count 0 2006.173.10:45:42.62#ibcon#end of sib2, iclass 3, count 0 2006.173.10:45:42.62#ibcon#*mode == 0, iclass 3, count 0 2006.173.10:45:42.62#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.10:45:42.62#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.10:45:42.62#ibcon#*before write, iclass 3, count 0 2006.173.10:45:42.62#ibcon#enter sib2, iclass 3, count 0 2006.173.10:45:42.62#ibcon#flushed, iclass 3, count 0 2006.173.10:45:42.62#ibcon#about to write, iclass 3, count 0 2006.173.10:45:42.62#ibcon#wrote, iclass 3, count 0 2006.173.10:45:42.62#ibcon#about to read 3, iclass 3, count 0 2006.173.10:45:42.66#ibcon#read 3, iclass 3, count 0 2006.173.10:45:42.66#ibcon#about to read 4, iclass 3, count 0 2006.173.10:45:42.66#ibcon#read 4, iclass 3, count 0 2006.173.10:45:42.66#ibcon#about to read 5, iclass 3, count 0 2006.173.10:45:42.66#ibcon#read 5, iclass 3, count 0 2006.173.10:45:42.66#ibcon#about to read 6, iclass 3, count 0 2006.173.10:45:42.66#ibcon#read 6, iclass 3, count 0 2006.173.10:45:42.66#ibcon#end of sib2, iclass 3, count 0 2006.173.10:45:42.66#ibcon#*after write, iclass 3, count 0 2006.173.10:45:42.66#ibcon#*before return 0, iclass 3, count 0 2006.173.10:45:42.66#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.10:45:42.66#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.10:45:42.66#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.10:45:42.66#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.10:45:42.66$vck44/vb=3,4 2006.173.10:45:42.66#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.10:45:42.66#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.10:45:42.66#ibcon#ireg 11 cls_cnt 2 2006.173.10:45:42.66#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.10:45:42.72#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.10:45:42.72#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.10:45:42.72#ibcon#enter wrdev, iclass 5, count 2 2006.173.10:45:42.72#ibcon#first serial, iclass 5, count 2 2006.173.10:45:42.72#ibcon#enter sib2, iclass 5, count 2 2006.173.10:45:42.72#ibcon#flushed, iclass 5, count 2 2006.173.10:45:42.72#ibcon#about to write, iclass 5, count 2 2006.173.10:45:42.72#ibcon#wrote, iclass 5, count 2 2006.173.10:45:42.72#ibcon#about to read 3, iclass 5, count 2 2006.173.10:45:42.74#ibcon#read 3, iclass 5, count 2 2006.173.10:45:42.74#ibcon#about to read 4, iclass 5, count 2 2006.173.10:45:42.74#ibcon#read 4, iclass 5, count 2 2006.173.10:45:42.74#ibcon#about to read 5, iclass 5, count 2 2006.173.10:45:42.74#ibcon#read 5, iclass 5, count 2 2006.173.10:45:42.74#ibcon#about to read 6, iclass 5, count 2 2006.173.10:45:42.74#ibcon#read 6, iclass 5, count 2 2006.173.10:45:42.74#ibcon#end of sib2, iclass 5, count 2 2006.173.10:45:42.74#ibcon#*mode == 0, iclass 5, count 2 2006.173.10:45:42.74#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.10:45:42.74#ibcon#[27=AT03-04\r\n] 2006.173.10:45:42.74#ibcon#*before write, iclass 5, count 2 2006.173.10:45:42.74#ibcon#enter sib2, iclass 5, count 2 2006.173.10:45:42.74#ibcon#flushed, iclass 5, count 2 2006.173.10:45:42.74#ibcon#about to write, iclass 5, count 2 2006.173.10:45:42.74#ibcon#wrote, iclass 5, count 2 2006.173.10:45:42.74#ibcon#about to read 3, iclass 5, count 2 2006.173.10:45:42.77#ibcon#read 3, iclass 5, count 2 2006.173.10:45:42.77#ibcon#about to read 4, iclass 5, count 2 2006.173.10:45:42.77#ibcon#read 4, iclass 5, count 2 2006.173.10:45:42.77#ibcon#about to read 5, iclass 5, count 2 2006.173.10:45:42.77#ibcon#read 5, iclass 5, count 2 2006.173.10:45:42.77#ibcon#about to read 6, iclass 5, count 2 2006.173.10:45:42.77#ibcon#read 6, iclass 5, count 2 2006.173.10:45:42.77#ibcon#end of sib2, iclass 5, count 2 2006.173.10:45:42.77#ibcon#*after write, iclass 5, count 2 2006.173.10:45:42.77#ibcon#*before return 0, iclass 5, count 2 2006.173.10:45:42.77#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.10:45:42.77#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.10:45:42.77#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.10:45:42.77#ibcon#ireg 7 cls_cnt 0 2006.173.10:45:42.77#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.10:45:42.89#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.10:45:42.89#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.10:45:42.89#ibcon#enter wrdev, iclass 5, count 0 2006.173.10:45:42.89#ibcon#first serial, iclass 5, count 0 2006.173.10:45:42.89#ibcon#enter sib2, iclass 5, count 0 2006.173.10:45:42.89#ibcon#flushed, iclass 5, count 0 2006.173.10:45:42.89#ibcon#about to write, iclass 5, count 0 2006.173.10:45:42.89#ibcon#wrote, iclass 5, count 0 2006.173.10:45:42.89#ibcon#about to read 3, iclass 5, count 0 2006.173.10:45:42.91#ibcon#read 3, iclass 5, count 0 2006.173.10:45:42.91#ibcon#about to read 4, iclass 5, count 0 2006.173.10:45:42.91#ibcon#read 4, iclass 5, count 0 2006.173.10:45:42.91#ibcon#about to read 5, iclass 5, count 0 2006.173.10:45:42.91#ibcon#read 5, iclass 5, count 0 2006.173.10:45:42.91#ibcon#about to read 6, iclass 5, count 0 2006.173.10:45:42.91#ibcon#read 6, iclass 5, count 0 2006.173.10:45:42.91#ibcon#end of sib2, iclass 5, count 0 2006.173.10:45:42.91#ibcon#*mode == 0, iclass 5, count 0 2006.173.10:45:42.91#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.10:45:42.91#ibcon#[27=USB\r\n] 2006.173.10:45:42.91#ibcon#*before write, iclass 5, count 0 2006.173.10:45:42.91#ibcon#enter sib2, iclass 5, count 0 2006.173.10:45:42.91#ibcon#flushed, iclass 5, count 0 2006.173.10:45:42.91#ibcon#about to write, iclass 5, count 0 2006.173.10:45:42.91#ibcon#wrote, iclass 5, count 0 2006.173.10:45:42.91#ibcon#about to read 3, iclass 5, count 0 2006.173.10:45:42.94#ibcon#read 3, iclass 5, count 0 2006.173.10:45:42.94#ibcon#about to read 4, iclass 5, count 0 2006.173.10:45:42.94#ibcon#read 4, iclass 5, count 0 2006.173.10:45:42.94#ibcon#about to read 5, iclass 5, count 0 2006.173.10:45:42.94#ibcon#read 5, iclass 5, count 0 2006.173.10:45:42.94#ibcon#about to read 6, iclass 5, count 0 2006.173.10:45:42.94#ibcon#read 6, iclass 5, count 0 2006.173.10:45:42.94#ibcon#end of sib2, iclass 5, count 0 2006.173.10:45:42.94#ibcon#*after write, iclass 5, count 0 2006.173.10:45:42.94#ibcon#*before return 0, iclass 5, count 0 2006.173.10:45:42.94#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.10:45:42.94#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.10:45:42.94#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.10:45:42.94#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.10:45:42.94$vck44/vblo=4,679.99 2006.173.10:45:42.94#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.10:45:42.94#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.10:45:42.94#ibcon#ireg 17 cls_cnt 0 2006.173.10:45:42.94#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.10:45:42.94#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.10:45:42.94#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.10:45:42.94#ibcon#enter wrdev, iclass 7, count 0 2006.173.10:45:42.94#ibcon#first serial, iclass 7, count 0 2006.173.10:45:42.94#ibcon#enter sib2, iclass 7, count 0 2006.173.10:45:42.94#ibcon#flushed, iclass 7, count 0 2006.173.10:45:42.94#ibcon#about to write, iclass 7, count 0 2006.173.10:45:42.94#ibcon#wrote, iclass 7, count 0 2006.173.10:45:42.94#ibcon#about to read 3, iclass 7, count 0 2006.173.10:45:42.96#ibcon#read 3, iclass 7, count 0 2006.173.10:45:42.96#ibcon#about to read 4, iclass 7, count 0 2006.173.10:45:42.96#ibcon#read 4, iclass 7, count 0 2006.173.10:45:42.96#ibcon#about to read 5, iclass 7, count 0 2006.173.10:45:42.96#ibcon#read 5, iclass 7, count 0 2006.173.10:45:42.96#ibcon#about to read 6, iclass 7, count 0 2006.173.10:45:42.96#ibcon#read 6, iclass 7, count 0 2006.173.10:45:42.96#ibcon#end of sib2, iclass 7, count 0 2006.173.10:45:42.96#ibcon#*mode == 0, iclass 7, count 0 2006.173.10:45:42.96#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.10:45:42.96#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.10:45:42.96#ibcon#*before write, iclass 7, count 0 2006.173.10:45:42.96#ibcon#enter sib2, iclass 7, count 0 2006.173.10:45:42.96#ibcon#flushed, iclass 7, count 0 2006.173.10:45:42.96#ibcon#about to write, iclass 7, count 0 2006.173.10:45:42.96#ibcon#wrote, iclass 7, count 0 2006.173.10:45:42.96#ibcon#about to read 3, iclass 7, count 0 2006.173.10:45:43.00#ibcon#read 3, iclass 7, count 0 2006.173.10:45:43.00#ibcon#about to read 4, iclass 7, count 0 2006.173.10:45:43.00#ibcon#read 4, iclass 7, count 0 2006.173.10:45:43.00#ibcon#about to read 5, iclass 7, count 0 2006.173.10:45:43.00#ibcon#read 5, iclass 7, count 0 2006.173.10:45:43.00#ibcon#about to read 6, iclass 7, count 0 2006.173.10:45:43.00#ibcon#read 6, iclass 7, count 0 2006.173.10:45:43.00#ibcon#end of sib2, iclass 7, count 0 2006.173.10:45:43.00#ibcon#*after write, iclass 7, count 0 2006.173.10:45:43.00#ibcon#*before return 0, iclass 7, count 0 2006.173.10:45:43.00#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.10:45:43.00#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.10:45:43.00#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.10:45:43.00#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.10:45:43.00$vck44/vb=4,4 2006.173.10:45:43.00#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.10:45:43.00#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.10:45:43.00#ibcon#ireg 11 cls_cnt 2 2006.173.10:45:43.00#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.10:45:43.06#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.10:45:43.06#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.10:45:43.06#ibcon#enter wrdev, iclass 11, count 2 2006.173.10:45:43.06#ibcon#first serial, iclass 11, count 2 2006.173.10:45:43.06#ibcon#enter sib2, iclass 11, count 2 2006.173.10:45:43.06#ibcon#flushed, iclass 11, count 2 2006.173.10:45:43.06#ibcon#about to write, iclass 11, count 2 2006.173.10:45:43.06#ibcon#wrote, iclass 11, count 2 2006.173.10:45:43.06#ibcon#about to read 3, iclass 11, count 2 2006.173.10:45:43.08#ibcon#read 3, iclass 11, count 2 2006.173.10:45:43.08#ibcon#about to read 4, iclass 11, count 2 2006.173.10:45:43.08#ibcon#read 4, iclass 11, count 2 2006.173.10:45:43.08#ibcon#about to read 5, iclass 11, count 2 2006.173.10:45:43.08#ibcon#read 5, iclass 11, count 2 2006.173.10:45:43.08#ibcon#about to read 6, iclass 11, count 2 2006.173.10:45:43.08#ibcon#read 6, iclass 11, count 2 2006.173.10:45:43.08#ibcon#end of sib2, iclass 11, count 2 2006.173.10:45:43.08#ibcon#*mode == 0, iclass 11, count 2 2006.173.10:45:43.08#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.10:45:43.08#ibcon#[27=AT04-04\r\n] 2006.173.10:45:43.08#ibcon#*before write, iclass 11, count 2 2006.173.10:45:43.08#ibcon#enter sib2, iclass 11, count 2 2006.173.10:45:43.08#ibcon#flushed, iclass 11, count 2 2006.173.10:45:43.08#ibcon#about to write, iclass 11, count 2 2006.173.10:45:43.08#ibcon#wrote, iclass 11, count 2 2006.173.10:45:43.08#ibcon#about to read 3, iclass 11, count 2 2006.173.10:45:43.11#ibcon#read 3, iclass 11, count 2 2006.173.10:45:43.11#ibcon#about to read 4, iclass 11, count 2 2006.173.10:45:43.11#ibcon#read 4, iclass 11, count 2 2006.173.10:45:43.11#ibcon#about to read 5, iclass 11, count 2 2006.173.10:45:43.11#ibcon#read 5, iclass 11, count 2 2006.173.10:45:43.11#ibcon#about to read 6, iclass 11, count 2 2006.173.10:45:43.11#ibcon#read 6, iclass 11, count 2 2006.173.10:45:43.11#ibcon#end of sib2, iclass 11, count 2 2006.173.10:45:43.11#ibcon#*after write, iclass 11, count 2 2006.173.10:45:43.11#ibcon#*before return 0, iclass 11, count 2 2006.173.10:45:43.11#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.10:45:43.11#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.10:45:43.11#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.10:45:43.11#ibcon#ireg 7 cls_cnt 0 2006.173.10:45:43.11#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.10:45:43.23#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.10:45:43.23#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.10:45:43.23#ibcon#enter wrdev, iclass 11, count 0 2006.173.10:45:43.23#ibcon#first serial, iclass 11, count 0 2006.173.10:45:43.23#ibcon#enter sib2, iclass 11, count 0 2006.173.10:45:43.23#ibcon#flushed, iclass 11, count 0 2006.173.10:45:43.23#ibcon#about to write, iclass 11, count 0 2006.173.10:45:43.23#ibcon#wrote, iclass 11, count 0 2006.173.10:45:43.23#ibcon#about to read 3, iclass 11, count 0 2006.173.10:45:43.25#ibcon#read 3, iclass 11, count 0 2006.173.10:45:43.25#ibcon#about to read 4, iclass 11, count 0 2006.173.10:45:43.25#ibcon#read 4, iclass 11, count 0 2006.173.10:45:43.25#ibcon#about to read 5, iclass 11, count 0 2006.173.10:45:43.25#ibcon#read 5, iclass 11, count 0 2006.173.10:45:43.25#ibcon#about to read 6, iclass 11, count 0 2006.173.10:45:43.25#ibcon#read 6, iclass 11, count 0 2006.173.10:45:43.25#ibcon#end of sib2, iclass 11, count 0 2006.173.10:45:43.25#ibcon#*mode == 0, iclass 11, count 0 2006.173.10:45:43.25#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.10:45:43.25#ibcon#[27=USB\r\n] 2006.173.10:45:43.25#ibcon#*before write, iclass 11, count 0 2006.173.10:45:43.25#ibcon#enter sib2, iclass 11, count 0 2006.173.10:45:43.25#ibcon#flushed, iclass 11, count 0 2006.173.10:45:43.25#ibcon#about to write, iclass 11, count 0 2006.173.10:45:43.25#ibcon#wrote, iclass 11, count 0 2006.173.10:45:43.25#ibcon#about to read 3, iclass 11, count 0 2006.173.10:45:43.28#ibcon#read 3, iclass 11, count 0 2006.173.10:45:43.28#ibcon#about to read 4, iclass 11, count 0 2006.173.10:45:43.28#ibcon#read 4, iclass 11, count 0 2006.173.10:45:43.28#ibcon#about to read 5, iclass 11, count 0 2006.173.10:45:43.28#ibcon#read 5, iclass 11, count 0 2006.173.10:45:43.28#ibcon#about to read 6, iclass 11, count 0 2006.173.10:45:43.28#ibcon#read 6, iclass 11, count 0 2006.173.10:45:43.28#ibcon#end of sib2, iclass 11, count 0 2006.173.10:45:43.28#ibcon#*after write, iclass 11, count 0 2006.173.10:45:43.28#ibcon#*before return 0, iclass 11, count 0 2006.173.10:45:43.28#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.10:45:43.28#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.10:45:43.28#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.10:45:43.28#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.10:45:43.28$vck44/vblo=5,709.99 2006.173.10:45:43.28#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.10:45:43.28#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.10:45:43.28#ibcon#ireg 17 cls_cnt 0 2006.173.10:45:43.28#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.10:45:43.28#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.10:45:43.28#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.10:45:43.28#ibcon#enter wrdev, iclass 13, count 0 2006.173.10:45:43.28#ibcon#first serial, iclass 13, count 0 2006.173.10:45:43.28#ibcon#enter sib2, iclass 13, count 0 2006.173.10:45:43.28#ibcon#flushed, iclass 13, count 0 2006.173.10:45:43.28#ibcon#about to write, iclass 13, count 0 2006.173.10:45:43.28#ibcon#wrote, iclass 13, count 0 2006.173.10:45:43.28#ibcon#about to read 3, iclass 13, count 0 2006.173.10:45:43.30#ibcon#read 3, iclass 13, count 0 2006.173.10:45:43.30#ibcon#about to read 4, iclass 13, count 0 2006.173.10:45:43.30#ibcon#read 4, iclass 13, count 0 2006.173.10:45:43.30#ibcon#about to read 5, iclass 13, count 0 2006.173.10:45:43.30#ibcon#read 5, iclass 13, count 0 2006.173.10:45:43.30#ibcon#about to read 6, iclass 13, count 0 2006.173.10:45:43.30#ibcon#read 6, iclass 13, count 0 2006.173.10:45:43.30#ibcon#end of sib2, iclass 13, count 0 2006.173.10:45:43.30#ibcon#*mode == 0, iclass 13, count 0 2006.173.10:45:43.30#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.10:45:43.30#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.10:45:43.30#ibcon#*before write, iclass 13, count 0 2006.173.10:45:43.30#ibcon#enter sib2, iclass 13, count 0 2006.173.10:45:43.30#ibcon#flushed, iclass 13, count 0 2006.173.10:45:43.30#ibcon#about to write, iclass 13, count 0 2006.173.10:45:43.30#ibcon#wrote, iclass 13, count 0 2006.173.10:45:43.30#ibcon#about to read 3, iclass 13, count 0 2006.173.10:45:43.34#ibcon#read 3, iclass 13, count 0 2006.173.10:45:43.34#ibcon#about to read 4, iclass 13, count 0 2006.173.10:45:43.34#ibcon#read 4, iclass 13, count 0 2006.173.10:45:43.34#ibcon#about to read 5, iclass 13, count 0 2006.173.10:45:43.34#ibcon#read 5, iclass 13, count 0 2006.173.10:45:43.34#ibcon#about to read 6, iclass 13, count 0 2006.173.10:45:43.34#ibcon#read 6, iclass 13, count 0 2006.173.10:45:43.34#ibcon#end of sib2, iclass 13, count 0 2006.173.10:45:43.34#ibcon#*after write, iclass 13, count 0 2006.173.10:45:43.34#ibcon#*before return 0, iclass 13, count 0 2006.173.10:45:43.34#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.10:45:43.34#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.10:45:43.34#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.10:45:43.34#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.10:45:43.34$vck44/vb=5,4 2006.173.10:45:43.34#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.10:45:43.34#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.10:45:43.34#ibcon#ireg 11 cls_cnt 2 2006.173.10:45:43.34#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.10:45:43.40#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.10:45:43.40#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.10:45:43.40#ibcon#enter wrdev, iclass 15, count 2 2006.173.10:45:43.40#ibcon#first serial, iclass 15, count 2 2006.173.10:45:43.40#ibcon#enter sib2, iclass 15, count 2 2006.173.10:45:43.40#ibcon#flushed, iclass 15, count 2 2006.173.10:45:43.40#ibcon#about to write, iclass 15, count 2 2006.173.10:45:43.40#ibcon#wrote, iclass 15, count 2 2006.173.10:45:43.40#ibcon#about to read 3, iclass 15, count 2 2006.173.10:45:43.42#ibcon#read 3, iclass 15, count 2 2006.173.10:45:43.42#ibcon#about to read 4, iclass 15, count 2 2006.173.10:45:43.42#ibcon#read 4, iclass 15, count 2 2006.173.10:45:43.42#ibcon#about to read 5, iclass 15, count 2 2006.173.10:45:43.42#ibcon#read 5, iclass 15, count 2 2006.173.10:45:43.42#ibcon#about to read 6, iclass 15, count 2 2006.173.10:45:43.42#ibcon#read 6, iclass 15, count 2 2006.173.10:45:43.42#ibcon#end of sib2, iclass 15, count 2 2006.173.10:45:43.42#ibcon#*mode == 0, iclass 15, count 2 2006.173.10:45:43.42#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.10:45:43.42#ibcon#[27=AT05-04\r\n] 2006.173.10:45:43.42#ibcon#*before write, iclass 15, count 2 2006.173.10:45:43.42#ibcon#enter sib2, iclass 15, count 2 2006.173.10:45:43.42#ibcon#flushed, iclass 15, count 2 2006.173.10:45:43.42#ibcon#about to write, iclass 15, count 2 2006.173.10:45:43.42#ibcon#wrote, iclass 15, count 2 2006.173.10:45:43.42#ibcon#about to read 3, iclass 15, count 2 2006.173.10:45:43.45#ibcon#read 3, iclass 15, count 2 2006.173.10:45:43.45#ibcon#about to read 4, iclass 15, count 2 2006.173.10:45:43.45#ibcon#read 4, iclass 15, count 2 2006.173.10:45:43.45#ibcon#about to read 5, iclass 15, count 2 2006.173.10:45:43.45#ibcon#read 5, iclass 15, count 2 2006.173.10:45:43.45#ibcon#about to read 6, iclass 15, count 2 2006.173.10:45:43.45#ibcon#read 6, iclass 15, count 2 2006.173.10:45:43.45#ibcon#end of sib2, iclass 15, count 2 2006.173.10:45:43.45#ibcon#*after write, iclass 15, count 2 2006.173.10:45:43.45#ibcon#*before return 0, iclass 15, count 2 2006.173.10:45:43.45#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.10:45:43.45#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.10:45:43.45#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.10:45:43.45#ibcon#ireg 7 cls_cnt 0 2006.173.10:45:43.45#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.10:45:43.57#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.10:45:43.57#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.10:45:43.57#ibcon#enter wrdev, iclass 15, count 0 2006.173.10:45:43.57#ibcon#first serial, iclass 15, count 0 2006.173.10:45:43.57#ibcon#enter sib2, iclass 15, count 0 2006.173.10:45:43.57#ibcon#flushed, iclass 15, count 0 2006.173.10:45:43.57#ibcon#about to write, iclass 15, count 0 2006.173.10:45:43.57#ibcon#wrote, iclass 15, count 0 2006.173.10:45:43.57#ibcon#about to read 3, iclass 15, count 0 2006.173.10:45:43.59#ibcon#read 3, iclass 15, count 0 2006.173.10:45:43.59#ibcon#about to read 4, iclass 15, count 0 2006.173.10:45:43.59#ibcon#read 4, iclass 15, count 0 2006.173.10:45:43.59#ibcon#about to read 5, iclass 15, count 0 2006.173.10:45:43.59#ibcon#read 5, iclass 15, count 0 2006.173.10:45:43.59#ibcon#about to read 6, iclass 15, count 0 2006.173.10:45:43.59#ibcon#read 6, iclass 15, count 0 2006.173.10:45:43.59#ibcon#end of sib2, iclass 15, count 0 2006.173.10:45:43.59#ibcon#*mode == 0, iclass 15, count 0 2006.173.10:45:43.59#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.10:45:43.59#ibcon#[27=USB\r\n] 2006.173.10:45:43.59#ibcon#*before write, iclass 15, count 0 2006.173.10:45:43.59#ibcon#enter sib2, iclass 15, count 0 2006.173.10:45:43.59#ibcon#flushed, iclass 15, count 0 2006.173.10:45:43.59#ibcon#about to write, iclass 15, count 0 2006.173.10:45:43.59#ibcon#wrote, iclass 15, count 0 2006.173.10:45:43.59#ibcon#about to read 3, iclass 15, count 0 2006.173.10:45:43.62#ibcon#read 3, iclass 15, count 0 2006.173.10:45:43.62#ibcon#about to read 4, iclass 15, count 0 2006.173.10:45:43.62#ibcon#read 4, iclass 15, count 0 2006.173.10:45:43.62#ibcon#about to read 5, iclass 15, count 0 2006.173.10:45:43.62#ibcon#read 5, iclass 15, count 0 2006.173.10:45:43.62#ibcon#about to read 6, iclass 15, count 0 2006.173.10:45:43.62#ibcon#read 6, iclass 15, count 0 2006.173.10:45:43.62#ibcon#end of sib2, iclass 15, count 0 2006.173.10:45:43.62#ibcon#*after write, iclass 15, count 0 2006.173.10:45:43.62#ibcon#*before return 0, iclass 15, count 0 2006.173.10:45:43.62#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.10:45:43.62#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.10:45:43.62#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.10:45:43.62#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.10:45:43.62$vck44/vblo=6,719.99 2006.173.10:45:43.62#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.10:45:43.62#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.10:45:43.62#ibcon#ireg 17 cls_cnt 0 2006.173.10:45:43.62#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.10:45:43.62#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.10:45:43.62#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.10:45:43.62#ibcon#enter wrdev, iclass 17, count 0 2006.173.10:45:43.62#ibcon#first serial, iclass 17, count 0 2006.173.10:45:43.62#ibcon#enter sib2, iclass 17, count 0 2006.173.10:45:43.62#ibcon#flushed, iclass 17, count 0 2006.173.10:45:43.62#ibcon#about to write, iclass 17, count 0 2006.173.10:45:43.62#ibcon#wrote, iclass 17, count 0 2006.173.10:45:43.62#ibcon#about to read 3, iclass 17, count 0 2006.173.10:45:43.64#ibcon#read 3, iclass 17, count 0 2006.173.10:45:43.64#ibcon#about to read 4, iclass 17, count 0 2006.173.10:45:43.64#ibcon#read 4, iclass 17, count 0 2006.173.10:45:43.64#ibcon#about to read 5, iclass 17, count 0 2006.173.10:45:43.64#ibcon#read 5, iclass 17, count 0 2006.173.10:45:43.64#ibcon#about to read 6, iclass 17, count 0 2006.173.10:45:43.64#ibcon#read 6, iclass 17, count 0 2006.173.10:45:43.64#ibcon#end of sib2, iclass 17, count 0 2006.173.10:45:43.64#ibcon#*mode == 0, iclass 17, count 0 2006.173.10:45:43.64#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.10:45:43.64#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.10:45:43.64#ibcon#*before write, iclass 17, count 0 2006.173.10:45:43.64#ibcon#enter sib2, iclass 17, count 0 2006.173.10:45:43.64#ibcon#flushed, iclass 17, count 0 2006.173.10:45:43.64#ibcon#about to write, iclass 17, count 0 2006.173.10:45:43.64#ibcon#wrote, iclass 17, count 0 2006.173.10:45:43.64#ibcon#about to read 3, iclass 17, count 0 2006.173.10:45:43.68#ibcon#read 3, iclass 17, count 0 2006.173.10:45:43.68#ibcon#about to read 4, iclass 17, count 0 2006.173.10:45:43.68#ibcon#read 4, iclass 17, count 0 2006.173.10:45:43.68#ibcon#about to read 5, iclass 17, count 0 2006.173.10:45:43.68#ibcon#read 5, iclass 17, count 0 2006.173.10:45:43.68#ibcon#about to read 6, iclass 17, count 0 2006.173.10:45:43.68#ibcon#read 6, iclass 17, count 0 2006.173.10:45:43.68#ibcon#end of sib2, iclass 17, count 0 2006.173.10:45:43.68#ibcon#*after write, iclass 17, count 0 2006.173.10:45:43.68#ibcon#*before return 0, iclass 17, count 0 2006.173.10:45:43.68#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.10:45:43.68#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.10:45:43.68#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.10:45:43.68#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.10:45:43.68$vck44/vb=6,4 2006.173.10:45:43.68#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.10:45:43.68#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.10:45:43.68#ibcon#ireg 11 cls_cnt 2 2006.173.10:45:43.68#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.10:45:43.74#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.10:45:43.74#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.10:45:43.74#ibcon#enter wrdev, iclass 19, count 2 2006.173.10:45:43.74#ibcon#first serial, iclass 19, count 2 2006.173.10:45:43.74#ibcon#enter sib2, iclass 19, count 2 2006.173.10:45:43.74#ibcon#flushed, iclass 19, count 2 2006.173.10:45:43.74#ibcon#about to write, iclass 19, count 2 2006.173.10:45:43.74#ibcon#wrote, iclass 19, count 2 2006.173.10:45:43.74#ibcon#about to read 3, iclass 19, count 2 2006.173.10:45:43.76#ibcon#read 3, iclass 19, count 2 2006.173.10:45:43.76#ibcon#about to read 4, iclass 19, count 2 2006.173.10:45:43.76#ibcon#read 4, iclass 19, count 2 2006.173.10:45:43.76#ibcon#about to read 5, iclass 19, count 2 2006.173.10:45:43.76#ibcon#read 5, iclass 19, count 2 2006.173.10:45:43.76#ibcon#about to read 6, iclass 19, count 2 2006.173.10:45:43.76#ibcon#read 6, iclass 19, count 2 2006.173.10:45:43.76#ibcon#end of sib2, iclass 19, count 2 2006.173.10:45:43.76#ibcon#*mode == 0, iclass 19, count 2 2006.173.10:45:43.76#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.10:45:43.76#ibcon#[27=AT06-04\r\n] 2006.173.10:45:43.76#ibcon#*before write, iclass 19, count 2 2006.173.10:45:43.76#ibcon#enter sib2, iclass 19, count 2 2006.173.10:45:43.76#ibcon#flushed, iclass 19, count 2 2006.173.10:45:43.76#ibcon#about to write, iclass 19, count 2 2006.173.10:45:43.76#ibcon#wrote, iclass 19, count 2 2006.173.10:45:43.76#ibcon#about to read 3, iclass 19, count 2 2006.173.10:45:43.79#ibcon#read 3, iclass 19, count 2 2006.173.10:45:43.79#ibcon#about to read 4, iclass 19, count 2 2006.173.10:45:43.79#ibcon#read 4, iclass 19, count 2 2006.173.10:45:43.79#ibcon#about to read 5, iclass 19, count 2 2006.173.10:45:43.79#ibcon#read 5, iclass 19, count 2 2006.173.10:45:43.79#ibcon#about to read 6, iclass 19, count 2 2006.173.10:45:43.79#ibcon#read 6, iclass 19, count 2 2006.173.10:45:43.79#ibcon#end of sib2, iclass 19, count 2 2006.173.10:45:43.79#ibcon#*after write, iclass 19, count 2 2006.173.10:45:43.79#ibcon#*before return 0, iclass 19, count 2 2006.173.10:45:43.79#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.10:45:43.79#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.10:45:43.79#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.10:45:43.79#ibcon#ireg 7 cls_cnt 0 2006.173.10:45:43.79#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.10:45:43.91#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.10:45:43.91#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.10:45:43.91#ibcon#enter wrdev, iclass 19, count 0 2006.173.10:45:43.91#ibcon#first serial, iclass 19, count 0 2006.173.10:45:43.91#ibcon#enter sib2, iclass 19, count 0 2006.173.10:45:43.91#ibcon#flushed, iclass 19, count 0 2006.173.10:45:43.91#ibcon#about to write, iclass 19, count 0 2006.173.10:45:43.91#ibcon#wrote, iclass 19, count 0 2006.173.10:45:43.91#ibcon#about to read 3, iclass 19, count 0 2006.173.10:45:43.93#ibcon#read 3, iclass 19, count 0 2006.173.10:45:43.93#ibcon#about to read 4, iclass 19, count 0 2006.173.10:45:43.93#ibcon#read 4, iclass 19, count 0 2006.173.10:45:43.93#ibcon#about to read 5, iclass 19, count 0 2006.173.10:45:43.93#ibcon#read 5, iclass 19, count 0 2006.173.10:45:43.93#ibcon#about to read 6, iclass 19, count 0 2006.173.10:45:43.93#ibcon#read 6, iclass 19, count 0 2006.173.10:45:43.93#ibcon#end of sib2, iclass 19, count 0 2006.173.10:45:43.93#ibcon#*mode == 0, iclass 19, count 0 2006.173.10:45:43.93#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.10:45:43.93#ibcon#[27=USB\r\n] 2006.173.10:45:43.93#ibcon#*before write, iclass 19, count 0 2006.173.10:45:43.93#ibcon#enter sib2, iclass 19, count 0 2006.173.10:45:43.93#ibcon#flushed, iclass 19, count 0 2006.173.10:45:43.93#ibcon#about to write, iclass 19, count 0 2006.173.10:45:43.93#ibcon#wrote, iclass 19, count 0 2006.173.10:45:43.93#ibcon#about to read 3, iclass 19, count 0 2006.173.10:45:43.96#ibcon#read 3, iclass 19, count 0 2006.173.10:45:43.96#ibcon#about to read 4, iclass 19, count 0 2006.173.10:45:43.96#ibcon#read 4, iclass 19, count 0 2006.173.10:45:43.96#ibcon#about to read 5, iclass 19, count 0 2006.173.10:45:43.96#ibcon#read 5, iclass 19, count 0 2006.173.10:45:43.96#ibcon#about to read 6, iclass 19, count 0 2006.173.10:45:43.96#ibcon#read 6, iclass 19, count 0 2006.173.10:45:43.96#ibcon#end of sib2, iclass 19, count 0 2006.173.10:45:43.96#ibcon#*after write, iclass 19, count 0 2006.173.10:45:43.96#ibcon#*before return 0, iclass 19, count 0 2006.173.10:45:43.96#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.10:45:43.96#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.10:45:43.96#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.10:45:43.96#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.10:45:43.96$vck44/vblo=7,734.99 2006.173.10:45:43.96#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.10:45:43.96#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.10:45:43.96#ibcon#ireg 17 cls_cnt 0 2006.173.10:45:43.96#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.10:45:43.96#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.10:45:43.96#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.10:45:43.96#ibcon#enter wrdev, iclass 21, count 0 2006.173.10:45:43.96#ibcon#first serial, iclass 21, count 0 2006.173.10:45:43.96#ibcon#enter sib2, iclass 21, count 0 2006.173.10:45:43.96#ibcon#flushed, iclass 21, count 0 2006.173.10:45:43.96#ibcon#about to write, iclass 21, count 0 2006.173.10:45:43.96#ibcon#wrote, iclass 21, count 0 2006.173.10:45:43.96#ibcon#about to read 3, iclass 21, count 0 2006.173.10:45:43.98#ibcon#read 3, iclass 21, count 0 2006.173.10:45:43.98#ibcon#about to read 4, iclass 21, count 0 2006.173.10:45:43.98#ibcon#read 4, iclass 21, count 0 2006.173.10:45:43.98#ibcon#about to read 5, iclass 21, count 0 2006.173.10:45:43.98#ibcon#read 5, iclass 21, count 0 2006.173.10:45:43.98#ibcon#about to read 6, iclass 21, count 0 2006.173.10:45:43.98#ibcon#read 6, iclass 21, count 0 2006.173.10:45:43.98#ibcon#end of sib2, iclass 21, count 0 2006.173.10:45:43.98#ibcon#*mode == 0, iclass 21, count 0 2006.173.10:45:43.98#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.10:45:43.98#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.10:45:43.98#ibcon#*before write, iclass 21, count 0 2006.173.10:45:43.98#ibcon#enter sib2, iclass 21, count 0 2006.173.10:45:43.98#ibcon#flushed, iclass 21, count 0 2006.173.10:45:43.98#ibcon#about to write, iclass 21, count 0 2006.173.10:45:43.98#ibcon#wrote, iclass 21, count 0 2006.173.10:45:43.98#ibcon#about to read 3, iclass 21, count 0 2006.173.10:45:44.02#ibcon#read 3, iclass 21, count 0 2006.173.10:45:44.02#ibcon#about to read 4, iclass 21, count 0 2006.173.10:45:44.02#ibcon#read 4, iclass 21, count 0 2006.173.10:45:44.02#ibcon#about to read 5, iclass 21, count 0 2006.173.10:45:44.02#ibcon#read 5, iclass 21, count 0 2006.173.10:45:44.02#ibcon#about to read 6, iclass 21, count 0 2006.173.10:45:44.02#ibcon#read 6, iclass 21, count 0 2006.173.10:45:44.02#ibcon#end of sib2, iclass 21, count 0 2006.173.10:45:44.02#ibcon#*after write, iclass 21, count 0 2006.173.10:45:44.02#ibcon#*before return 0, iclass 21, count 0 2006.173.10:45:44.02#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.10:45:44.02#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.10:45:44.02#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.10:45:44.02#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.10:45:44.02$vck44/vb=7,4 2006.173.10:45:44.02#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.10:45:44.02#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.10:45:44.02#ibcon#ireg 11 cls_cnt 2 2006.173.10:45:44.02#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.10:45:44.08#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.10:45:44.08#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.10:45:44.08#ibcon#enter wrdev, iclass 23, count 2 2006.173.10:45:44.08#ibcon#first serial, iclass 23, count 2 2006.173.10:45:44.08#ibcon#enter sib2, iclass 23, count 2 2006.173.10:45:44.08#ibcon#flushed, iclass 23, count 2 2006.173.10:45:44.08#ibcon#about to write, iclass 23, count 2 2006.173.10:45:44.08#ibcon#wrote, iclass 23, count 2 2006.173.10:45:44.08#ibcon#about to read 3, iclass 23, count 2 2006.173.10:45:44.10#ibcon#read 3, iclass 23, count 2 2006.173.10:45:44.10#ibcon#about to read 4, iclass 23, count 2 2006.173.10:45:44.10#ibcon#read 4, iclass 23, count 2 2006.173.10:45:44.10#ibcon#about to read 5, iclass 23, count 2 2006.173.10:45:44.10#ibcon#read 5, iclass 23, count 2 2006.173.10:45:44.10#ibcon#about to read 6, iclass 23, count 2 2006.173.10:45:44.10#ibcon#read 6, iclass 23, count 2 2006.173.10:45:44.10#ibcon#end of sib2, iclass 23, count 2 2006.173.10:45:44.10#ibcon#*mode == 0, iclass 23, count 2 2006.173.10:45:44.10#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.10:45:44.10#ibcon#[27=AT07-04\r\n] 2006.173.10:45:44.10#ibcon#*before write, iclass 23, count 2 2006.173.10:45:44.10#ibcon#enter sib2, iclass 23, count 2 2006.173.10:45:44.10#ibcon#flushed, iclass 23, count 2 2006.173.10:45:44.10#ibcon#about to write, iclass 23, count 2 2006.173.10:45:44.10#ibcon#wrote, iclass 23, count 2 2006.173.10:45:44.10#ibcon#about to read 3, iclass 23, count 2 2006.173.10:45:44.13#ibcon#read 3, iclass 23, count 2 2006.173.10:45:44.13#ibcon#about to read 4, iclass 23, count 2 2006.173.10:45:44.13#ibcon#read 4, iclass 23, count 2 2006.173.10:45:44.13#ibcon#about to read 5, iclass 23, count 2 2006.173.10:45:44.13#ibcon#read 5, iclass 23, count 2 2006.173.10:45:44.13#ibcon#about to read 6, iclass 23, count 2 2006.173.10:45:44.13#ibcon#read 6, iclass 23, count 2 2006.173.10:45:44.13#ibcon#end of sib2, iclass 23, count 2 2006.173.10:45:44.13#ibcon#*after write, iclass 23, count 2 2006.173.10:45:44.13#ibcon#*before return 0, iclass 23, count 2 2006.173.10:45:44.13#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.10:45:44.13#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.10:45:44.13#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.10:45:44.13#ibcon#ireg 7 cls_cnt 0 2006.173.10:45:44.13#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.10:45:44.25#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.10:45:44.25#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.10:45:44.25#ibcon#enter wrdev, iclass 23, count 0 2006.173.10:45:44.25#ibcon#first serial, iclass 23, count 0 2006.173.10:45:44.25#ibcon#enter sib2, iclass 23, count 0 2006.173.10:45:44.25#ibcon#flushed, iclass 23, count 0 2006.173.10:45:44.25#ibcon#about to write, iclass 23, count 0 2006.173.10:45:44.25#ibcon#wrote, iclass 23, count 0 2006.173.10:45:44.25#ibcon#about to read 3, iclass 23, count 0 2006.173.10:45:44.27#ibcon#read 3, iclass 23, count 0 2006.173.10:45:44.27#ibcon#about to read 4, iclass 23, count 0 2006.173.10:45:44.27#ibcon#read 4, iclass 23, count 0 2006.173.10:45:44.27#ibcon#about to read 5, iclass 23, count 0 2006.173.10:45:44.27#ibcon#read 5, iclass 23, count 0 2006.173.10:45:44.27#ibcon#about to read 6, iclass 23, count 0 2006.173.10:45:44.27#ibcon#read 6, iclass 23, count 0 2006.173.10:45:44.27#ibcon#end of sib2, iclass 23, count 0 2006.173.10:45:44.27#ibcon#*mode == 0, iclass 23, count 0 2006.173.10:45:44.27#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.10:45:44.27#ibcon#[27=USB\r\n] 2006.173.10:45:44.27#ibcon#*before write, iclass 23, count 0 2006.173.10:45:44.27#ibcon#enter sib2, iclass 23, count 0 2006.173.10:45:44.27#ibcon#flushed, iclass 23, count 0 2006.173.10:45:44.27#ibcon#about to write, iclass 23, count 0 2006.173.10:45:44.27#ibcon#wrote, iclass 23, count 0 2006.173.10:45:44.27#ibcon#about to read 3, iclass 23, count 0 2006.173.10:45:44.30#ibcon#read 3, iclass 23, count 0 2006.173.10:45:44.30#ibcon#about to read 4, iclass 23, count 0 2006.173.10:45:44.30#ibcon#read 4, iclass 23, count 0 2006.173.10:45:44.30#ibcon#about to read 5, iclass 23, count 0 2006.173.10:45:44.30#ibcon#read 5, iclass 23, count 0 2006.173.10:45:44.30#ibcon#about to read 6, iclass 23, count 0 2006.173.10:45:44.30#ibcon#read 6, iclass 23, count 0 2006.173.10:45:44.30#ibcon#end of sib2, iclass 23, count 0 2006.173.10:45:44.30#ibcon#*after write, iclass 23, count 0 2006.173.10:45:44.30#ibcon#*before return 0, iclass 23, count 0 2006.173.10:45:44.30#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.10:45:44.30#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.10:45:44.30#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.10:45:44.30#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.10:45:44.30$vck44/vblo=8,744.99 2006.173.10:45:44.30#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.10:45:44.30#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.10:45:44.30#ibcon#ireg 17 cls_cnt 0 2006.173.10:45:44.30#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.10:45:44.30#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.10:45:44.30#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.10:45:44.30#ibcon#enter wrdev, iclass 25, count 0 2006.173.10:45:44.30#ibcon#first serial, iclass 25, count 0 2006.173.10:45:44.30#ibcon#enter sib2, iclass 25, count 0 2006.173.10:45:44.30#ibcon#flushed, iclass 25, count 0 2006.173.10:45:44.30#ibcon#about to write, iclass 25, count 0 2006.173.10:45:44.30#ibcon#wrote, iclass 25, count 0 2006.173.10:45:44.30#ibcon#about to read 3, iclass 25, count 0 2006.173.10:45:44.32#ibcon#read 3, iclass 25, count 0 2006.173.10:45:44.32#ibcon#about to read 4, iclass 25, count 0 2006.173.10:45:44.32#ibcon#read 4, iclass 25, count 0 2006.173.10:45:44.32#ibcon#about to read 5, iclass 25, count 0 2006.173.10:45:44.32#ibcon#read 5, iclass 25, count 0 2006.173.10:45:44.32#ibcon#about to read 6, iclass 25, count 0 2006.173.10:45:44.32#ibcon#read 6, iclass 25, count 0 2006.173.10:45:44.32#ibcon#end of sib2, iclass 25, count 0 2006.173.10:45:44.32#ibcon#*mode == 0, iclass 25, count 0 2006.173.10:45:44.32#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.10:45:44.32#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.10:45:44.32#ibcon#*before write, iclass 25, count 0 2006.173.10:45:44.32#ibcon#enter sib2, iclass 25, count 0 2006.173.10:45:44.32#ibcon#flushed, iclass 25, count 0 2006.173.10:45:44.32#ibcon#about to write, iclass 25, count 0 2006.173.10:45:44.32#ibcon#wrote, iclass 25, count 0 2006.173.10:45:44.32#ibcon#about to read 3, iclass 25, count 0 2006.173.10:45:44.36#ibcon#read 3, iclass 25, count 0 2006.173.10:45:44.36#ibcon#about to read 4, iclass 25, count 0 2006.173.10:45:44.36#ibcon#read 4, iclass 25, count 0 2006.173.10:45:44.36#ibcon#about to read 5, iclass 25, count 0 2006.173.10:45:44.36#ibcon#read 5, iclass 25, count 0 2006.173.10:45:44.36#ibcon#about to read 6, iclass 25, count 0 2006.173.10:45:44.36#ibcon#read 6, iclass 25, count 0 2006.173.10:45:44.36#ibcon#end of sib2, iclass 25, count 0 2006.173.10:45:44.36#ibcon#*after write, iclass 25, count 0 2006.173.10:45:44.36#ibcon#*before return 0, iclass 25, count 0 2006.173.10:45:44.36#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.10:45:44.36#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.10:45:44.36#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.10:45:44.36#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.10:45:44.36$vck44/vb=8,4 2006.173.10:45:44.36#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.10:45:44.36#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.10:45:44.36#ibcon#ireg 11 cls_cnt 2 2006.173.10:45:44.36#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.10:45:44.42#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.10:45:44.42#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.10:45:44.42#ibcon#enter wrdev, iclass 27, count 2 2006.173.10:45:44.42#ibcon#first serial, iclass 27, count 2 2006.173.10:45:44.42#ibcon#enter sib2, iclass 27, count 2 2006.173.10:45:44.42#ibcon#flushed, iclass 27, count 2 2006.173.10:45:44.42#ibcon#about to write, iclass 27, count 2 2006.173.10:45:44.42#ibcon#wrote, iclass 27, count 2 2006.173.10:45:44.42#ibcon#about to read 3, iclass 27, count 2 2006.173.10:45:44.44#ibcon#read 3, iclass 27, count 2 2006.173.10:45:44.44#ibcon#about to read 4, iclass 27, count 2 2006.173.10:45:44.44#ibcon#read 4, iclass 27, count 2 2006.173.10:45:44.44#ibcon#about to read 5, iclass 27, count 2 2006.173.10:45:44.44#ibcon#read 5, iclass 27, count 2 2006.173.10:45:44.44#ibcon#about to read 6, iclass 27, count 2 2006.173.10:45:44.44#ibcon#read 6, iclass 27, count 2 2006.173.10:45:44.44#ibcon#end of sib2, iclass 27, count 2 2006.173.10:45:44.44#ibcon#*mode == 0, iclass 27, count 2 2006.173.10:45:44.44#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.10:45:44.44#ibcon#[27=AT08-04\r\n] 2006.173.10:45:44.44#ibcon#*before write, iclass 27, count 2 2006.173.10:45:44.44#ibcon#enter sib2, iclass 27, count 2 2006.173.10:45:44.44#ibcon#flushed, iclass 27, count 2 2006.173.10:45:44.44#ibcon#about to write, iclass 27, count 2 2006.173.10:45:44.44#ibcon#wrote, iclass 27, count 2 2006.173.10:45:44.44#ibcon#about to read 3, iclass 27, count 2 2006.173.10:45:44.47#ibcon#read 3, iclass 27, count 2 2006.173.10:45:44.47#ibcon#about to read 4, iclass 27, count 2 2006.173.10:45:44.47#ibcon#read 4, iclass 27, count 2 2006.173.10:45:44.47#ibcon#about to read 5, iclass 27, count 2 2006.173.10:45:44.47#ibcon#read 5, iclass 27, count 2 2006.173.10:45:44.47#ibcon#about to read 6, iclass 27, count 2 2006.173.10:45:44.47#ibcon#read 6, iclass 27, count 2 2006.173.10:45:44.47#ibcon#end of sib2, iclass 27, count 2 2006.173.10:45:44.47#ibcon#*after write, iclass 27, count 2 2006.173.10:45:44.47#ibcon#*before return 0, iclass 27, count 2 2006.173.10:45:44.47#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.10:45:44.47#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.10:45:44.47#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.10:45:44.47#ibcon#ireg 7 cls_cnt 0 2006.173.10:45:44.47#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.10:45:44.59#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.10:45:44.59#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.10:45:44.59#ibcon#enter wrdev, iclass 27, count 0 2006.173.10:45:44.59#ibcon#first serial, iclass 27, count 0 2006.173.10:45:44.59#ibcon#enter sib2, iclass 27, count 0 2006.173.10:45:44.59#ibcon#flushed, iclass 27, count 0 2006.173.10:45:44.59#ibcon#about to write, iclass 27, count 0 2006.173.10:45:44.59#ibcon#wrote, iclass 27, count 0 2006.173.10:45:44.59#ibcon#about to read 3, iclass 27, count 0 2006.173.10:45:44.61#ibcon#read 3, iclass 27, count 0 2006.173.10:45:44.61#ibcon#about to read 4, iclass 27, count 0 2006.173.10:45:44.61#ibcon#read 4, iclass 27, count 0 2006.173.10:45:44.61#ibcon#about to read 5, iclass 27, count 0 2006.173.10:45:44.61#ibcon#read 5, iclass 27, count 0 2006.173.10:45:44.61#ibcon#about to read 6, iclass 27, count 0 2006.173.10:45:44.61#ibcon#read 6, iclass 27, count 0 2006.173.10:45:44.61#ibcon#end of sib2, iclass 27, count 0 2006.173.10:45:44.61#ibcon#*mode == 0, iclass 27, count 0 2006.173.10:45:44.61#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.10:45:44.61#ibcon#[27=USB\r\n] 2006.173.10:45:44.61#ibcon#*before write, iclass 27, count 0 2006.173.10:45:44.61#ibcon#enter sib2, iclass 27, count 0 2006.173.10:45:44.61#ibcon#flushed, iclass 27, count 0 2006.173.10:45:44.61#ibcon#about to write, iclass 27, count 0 2006.173.10:45:44.61#ibcon#wrote, iclass 27, count 0 2006.173.10:45:44.61#ibcon#about to read 3, iclass 27, count 0 2006.173.10:45:44.64#ibcon#read 3, iclass 27, count 0 2006.173.10:45:44.64#ibcon#about to read 4, iclass 27, count 0 2006.173.10:45:44.64#ibcon#read 4, iclass 27, count 0 2006.173.10:45:44.64#ibcon#about to read 5, iclass 27, count 0 2006.173.10:45:44.64#ibcon#read 5, iclass 27, count 0 2006.173.10:45:44.64#ibcon#about to read 6, iclass 27, count 0 2006.173.10:45:44.64#ibcon#read 6, iclass 27, count 0 2006.173.10:45:44.64#ibcon#end of sib2, iclass 27, count 0 2006.173.10:45:44.64#ibcon#*after write, iclass 27, count 0 2006.173.10:45:44.64#ibcon#*before return 0, iclass 27, count 0 2006.173.10:45:44.64#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.10:45:44.64#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.10:45:44.64#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.10:45:44.64#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.10:45:44.64$vck44/vabw=wide 2006.173.10:45:44.64#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.10:45:44.64#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.10:45:44.64#ibcon#ireg 8 cls_cnt 0 2006.173.10:45:44.64#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.10:45:44.64#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.10:45:44.64#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.10:45:44.64#ibcon#enter wrdev, iclass 29, count 0 2006.173.10:45:44.64#ibcon#first serial, iclass 29, count 0 2006.173.10:45:44.64#ibcon#enter sib2, iclass 29, count 0 2006.173.10:45:44.64#ibcon#flushed, iclass 29, count 0 2006.173.10:45:44.64#ibcon#about to write, iclass 29, count 0 2006.173.10:45:44.64#ibcon#wrote, iclass 29, count 0 2006.173.10:45:44.64#ibcon#about to read 3, iclass 29, count 0 2006.173.10:45:44.66#ibcon#read 3, iclass 29, count 0 2006.173.10:45:44.66#ibcon#about to read 4, iclass 29, count 0 2006.173.10:45:44.66#ibcon#read 4, iclass 29, count 0 2006.173.10:45:44.66#ibcon#about to read 5, iclass 29, count 0 2006.173.10:45:44.66#ibcon#read 5, iclass 29, count 0 2006.173.10:45:44.66#ibcon#about to read 6, iclass 29, count 0 2006.173.10:45:44.66#ibcon#read 6, iclass 29, count 0 2006.173.10:45:44.66#ibcon#end of sib2, iclass 29, count 0 2006.173.10:45:44.66#ibcon#*mode == 0, iclass 29, count 0 2006.173.10:45:44.66#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.10:45:44.66#ibcon#[25=BW32\r\n] 2006.173.10:45:44.66#ibcon#*before write, iclass 29, count 0 2006.173.10:45:44.66#ibcon#enter sib2, iclass 29, count 0 2006.173.10:45:44.66#ibcon#flushed, iclass 29, count 0 2006.173.10:45:44.66#ibcon#about to write, iclass 29, count 0 2006.173.10:45:44.66#ibcon#wrote, iclass 29, count 0 2006.173.10:45:44.66#ibcon#about to read 3, iclass 29, count 0 2006.173.10:45:44.69#ibcon#read 3, iclass 29, count 0 2006.173.10:45:44.69#ibcon#about to read 4, iclass 29, count 0 2006.173.10:45:44.69#ibcon#read 4, iclass 29, count 0 2006.173.10:45:44.69#ibcon#about to read 5, iclass 29, count 0 2006.173.10:45:44.69#ibcon#read 5, iclass 29, count 0 2006.173.10:45:44.69#ibcon#about to read 6, iclass 29, count 0 2006.173.10:45:44.69#ibcon#read 6, iclass 29, count 0 2006.173.10:45:44.69#ibcon#end of sib2, iclass 29, count 0 2006.173.10:45:44.69#ibcon#*after write, iclass 29, count 0 2006.173.10:45:44.69#ibcon#*before return 0, iclass 29, count 0 2006.173.10:45:44.69#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.10:45:44.69#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.10:45:44.69#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.10:45:44.69#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.10:45:44.69$vck44/vbbw=wide 2006.173.10:45:44.69#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.10:45:44.69#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.10:45:44.69#ibcon#ireg 8 cls_cnt 0 2006.173.10:45:44.69#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.10:45:44.76#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.10:45:44.76#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.10:45:44.76#ibcon#enter wrdev, iclass 31, count 0 2006.173.10:45:44.76#ibcon#first serial, iclass 31, count 0 2006.173.10:45:44.76#ibcon#enter sib2, iclass 31, count 0 2006.173.10:45:44.76#ibcon#flushed, iclass 31, count 0 2006.173.10:45:44.76#ibcon#about to write, iclass 31, count 0 2006.173.10:45:44.76#ibcon#wrote, iclass 31, count 0 2006.173.10:45:44.76#ibcon#about to read 3, iclass 31, count 0 2006.173.10:45:44.78#ibcon#read 3, iclass 31, count 0 2006.173.10:45:44.78#ibcon#about to read 4, iclass 31, count 0 2006.173.10:45:44.78#ibcon#read 4, iclass 31, count 0 2006.173.10:45:44.78#ibcon#about to read 5, iclass 31, count 0 2006.173.10:45:44.78#ibcon#read 5, iclass 31, count 0 2006.173.10:45:44.78#ibcon#about to read 6, iclass 31, count 0 2006.173.10:45:44.78#ibcon#read 6, iclass 31, count 0 2006.173.10:45:44.78#ibcon#end of sib2, iclass 31, count 0 2006.173.10:45:44.78#ibcon#*mode == 0, iclass 31, count 0 2006.173.10:45:44.78#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.10:45:44.78#ibcon#[27=BW32\r\n] 2006.173.10:45:44.78#ibcon#*before write, iclass 31, count 0 2006.173.10:45:44.78#ibcon#enter sib2, iclass 31, count 0 2006.173.10:45:44.78#ibcon#flushed, iclass 31, count 0 2006.173.10:45:44.78#ibcon#about to write, iclass 31, count 0 2006.173.10:45:44.78#ibcon#wrote, iclass 31, count 0 2006.173.10:45:44.78#ibcon#about to read 3, iclass 31, count 0 2006.173.10:45:44.81#ibcon#read 3, iclass 31, count 0 2006.173.10:45:44.81#ibcon#about to read 4, iclass 31, count 0 2006.173.10:45:44.81#ibcon#read 4, iclass 31, count 0 2006.173.10:45:44.81#ibcon#about to read 5, iclass 31, count 0 2006.173.10:45:44.81#ibcon#read 5, iclass 31, count 0 2006.173.10:45:44.81#ibcon#about to read 6, iclass 31, count 0 2006.173.10:45:44.81#ibcon#read 6, iclass 31, count 0 2006.173.10:45:44.81#ibcon#end of sib2, iclass 31, count 0 2006.173.10:45:44.81#ibcon#*after write, iclass 31, count 0 2006.173.10:45:44.81#ibcon#*before return 0, iclass 31, count 0 2006.173.10:45:44.81#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.10:45:44.81#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.10:45:44.81#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.10:45:44.81#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.10:45:44.81$setupk4/ifdk4 2006.173.10:45:44.81$ifdk4/lo= 2006.173.10:45:44.81$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.10:45:44.81$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.10:45:44.81$ifdk4/patch= 2006.173.10:45:44.81$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.10:45:44.81$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.10:45:44.81$setupk4/!*+20s 2006.173.10:45:50.36#abcon#<5=/05 1.0 1.8 22.65 911003.9\r\n> 2006.173.10:45:50.38#abcon#{5=INTERFACE CLEAR} 2006.173.10:45:50.44#abcon#[5=S1D000X0/0*\r\n] 2006.173.10:45:59.32$setupk4/"tpicd 2006.173.10:45:59.32$setupk4/echo=off 2006.173.10:45:59.32$setupk4/xlog=off 2006.173.10:45:59.32:!2006.173.10:46:39 2006.173.10:46:34.14#trakl#Source acquired 2006.173.10:46:34.14#flagr#flagr/antenna,acquired 2006.173.10:46:39.00:preob 2006.173.10:46:39.14/onsource/TRACKING 2006.173.10:46:39.14:!2006.173.10:46:49 2006.173.10:46:49.00:"tape 2006.173.10:46:49.00:"st=record 2006.173.10:46:49.00:data_valid=on 2006.173.10:46:49.00:midob 2006.173.10:46:49.14/onsource/TRACKING 2006.173.10:46:49.14/wx/22.66,1003.9,92 2006.173.10:46:49.20/cable/+6.5032E-03 2006.173.10:46:50.29/va/01,07,usb,yes,41,44 2006.173.10:46:50.29/va/02,06,usb,yes,40,41 2006.173.10:46:50.29/va/03,05,usb,yes,51,53 2006.173.10:46:50.29/va/04,06,usb,yes,41,43 2006.173.10:46:50.29/va/05,04,usb,yes,33,33 2006.173.10:46:50.29/va/06,03,usb,yes,45,45 2006.173.10:46:50.29/va/07,04,usb,yes,37,38 2006.173.10:46:50.29/va/08,04,usb,yes,32,38 2006.173.10:46:50.52/valo/01,524.99,yes,locked 2006.173.10:46:50.52/valo/02,534.99,yes,locked 2006.173.10:46:50.52/valo/03,564.99,yes,locked 2006.173.10:46:50.52/valo/04,624.99,yes,locked 2006.173.10:46:50.52/valo/05,734.99,yes,locked 2006.173.10:46:50.52/valo/06,814.99,yes,locked 2006.173.10:46:50.52/valo/07,864.99,yes,locked 2006.173.10:46:50.52/valo/08,884.99,yes,locked 2006.173.10:46:51.61/vb/01,04,usb,yes,31,29 2006.173.10:46:51.61/vb/02,04,usb,yes,34,33 2006.173.10:46:51.61/vb/03,04,usb,yes,30,33 2006.173.10:46:51.61/vb/04,04,usb,yes,35,34 2006.173.10:46:51.61/vb/05,04,usb,yes,27,30 2006.173.10:46:51.61/vb/06,04,usb,yes,32,28 2006.173.10:46:51.61/vb/07,04,usb,yes,32,31 2006.173.10:46:51.61/vb/08,04,usb,yes,29,33 2006.173.10:46:51.84/vblo/01,629.99,yes,locked 2006.173.10:46:51.84/vblo/02,634.99,yes,locked 2006.173.10:46:51.84/vblo/03,649.99,yes,locked 2006.173.10:46:51.84/vblo/04,679.99,yes,locked 2006.173.10:46:51.84/vblo/05,709.99,yes,locked 2006.173.10:46:51.84/vblo/06,719.99,yes,locked 2006.173.10:46:51.84/vblo/07,734.99,yes,locked 2006.173.10:46:51.84/vblo/08,744.99,yes,locked 2006.173.10:46:51.99/vabw/8 2006.173.10:46:52.14/vbbw/8 2006.173.10:46:52.23/xfe/off,on,15.0 2006.173.10:46:52.62/ifatt/23,28,28,28 2006.173.10:46:53.07/fmout-gps/S +3.99E-07 2006.173.10:46:53.11:!2006.173.10:47:29 2006.173.10:47:29.00:data_valid=off 2006.173.10:47:29.00:"et 2006.173.10:47:29.00:!+3s 2006.173.10:47:32.01:"tape 2006.173.10:47:32.01:postob 2006.173.10:47:32.13/cable/+6.5009E-03 2006.173.10:47:32.13/wx/22.66,1003.9,92 2006.173.10:47:33.07/fmout-gps/S +4.00E-07 2006.173.10:47:33.07:scan_name=173-1052,jd0606,100 2006.173.10:47:33.07:source=1334-127,133739.78,-125724.7,2000.0,cw 2006.173.10:47:34.14#flagr#flagr/antenna,new-source 2006.173.10:47:34.14:checkk5 2006.173.10:47:34.50/chk_autoobs//k5ts1/ autoobs is running! 2006.173.10:47:34.87/chk_autoobs//k5ts2/ autoobs is running! 2006.173.10:47:35.28/chk_autoobs//k5ts3/ autoobs is running! 2006.173.10:47:35.68/chk_autoobs//k5ts4/ autoobs is running! 2006.173.10:47:36.07/chk_obsdata//k5ts1/T1731046??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.10:47:36.47/chk_obsdata//k5ts2/T1731046??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.10:47:36.88/chk_obsdata//k5ts3/T1731046??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.10:47:37.29/chk_obsdata//k5ts4/T1731046??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.10:47:38.02/k5log//k5ts1_log_newline 2006.173.10:47:38.73/k5log//k5ts2_log_newline 2006.173.10:47:39.43/k5log//k5ts3_log_newline 2006.173.10:47:40.15/k5log//k5ts4_log_newline 2006.173.10:47:40.17/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.10:47:40.17:setupk4=1 2006.173.10:47:40.17$setupk4/echo=on 2006.173.10:47:40.17$setupk4/pcalon 2006.173.10:47:40.17$pcalon/"no phase cal control is implemented here 2006.173.10:47:40.17$setupk4/"tpicd=stop 2006.173.10:47:40.17$setupk4/"rec=synch_on 2006.173.10:47:40.17$setupk4/"rec_mode=128 2006.173.10:47:40.17$setupk4/!* 2006.173.10:47:40.17$setupk4/recpk4 2006.173.10:47:40.17$recpk4/recpatch= 2006.173.10:47:40.17$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.10:47:40.17$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.10:47:40.17$setupk4/vck44 2006.173.10:47:40.17$vck44/valo=1,524.99 2006.173.10:47:40.17#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.10:47:40.17#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.10:47:40.17#ibcon#ireg 17 cls_cnt 0 2006.173.10:47:40.17#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.10:47:40.17#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.10:47:40.17#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.10:47:40.17#ibcon#enter wrdev, iclass 6, count 0 2006.173.10:47:40.17#ibcon#first serial, iclass 6, count 0 2006.173.10:47:40.17#ibcon#enter sib2, iclass 6, count 0 2006.173.10:47:40.17#ibcon#flushed, iclass 6, count 0 2006.173.10:47:40.17#ibcon#about to write, iclass 6, count 0 2006.173.10:47:40.17#ibcon#wrote, iclass 6, count 0 2006.173.10:47:40.17#ibcon#about to read 3, iclass 6, count 0 2006.173.10:47:40.19#ibcon#read 3, iclass 6, count 0 2006.173.10:47:40.19#ibcon#about to read 4, iclass 6, count 0 2006.173.10:47:40.19#ibcon#read 4, iclass 6, count 0 2006.173.10:47:40.19#ibcon#about to read 5, iclass 6, count 0 2006.173.10:47:40.19#ibcon#read 5, iclass 6, count 0 2006.173.10:47:40.19#ibcon#about to read 6, iclass 6, count 0 2006.173.10:47:40.19#ibcon#read 6, iclass 6, count 0 2006.173.10:47:40.19#ibcon#end of sib2, iclass 6, count 0 2006.173.10:47:40.19#ibcon#*mode == 0, iclass 6, count 0 2006.173.10:47:40.19#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.10:47:40.19#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.10:47:40.19#ibcon#*before write, iclass 6, count 0 2006.173.10:47:40.19#ibcon#enter sib2, iclass 6, count 0 2006.173.10:47:40.19#ibcon#flushed, iclass 6, count 0 2006.173.10:47:40.19#ibcon#about to write, iclass 6, count 0 2006.173.10:47:40.19#ibcon#wrote, iclass 6, count 0 2006.173.10:47:40.19#ibcon#about to read 3, iclass 6, count 0 2006.173.10:47:40.24#ibcon#read 3, iclass 6, count 0 2006.173.10:47:40.24#ibcon#about to read 4, iclass 6, count 0 2006.173.10:47:40.24#ibcon#read 4, iclass 6, count 0 2006.173.10:47:40.24#ibcon#about to read 5, iclass 6, count 0 2006.173.10:47:40.24#ibcon#read 5, iclass 6, count 0 2006.173.10:47:40.24#ibcon#about to read 6, iclass 6, count 0 2006.173.10:47:40.24#ibcon#read 6, iclass 6, count 0 2006.173.10:47:40.24#ibcon#end of sib2, iclass 6, count 0 2006.173.10:47:40.24#ibcon#*after write, iclass 6, count 0 2006.173.10:47:40.24#ibcon#*before return 0, iclass 6, count 0 2006.173.10:47:40.24#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.10:47:40.24#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.10:47:40.24#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.10:47:40.24#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.10:47:40.24$vck44/va=1,7 2006.173.10:47:40.24#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.10:47:40.24#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.10:47:40.24#ibcon#ireg 11 cls_cnt 2 2006.173.10:47:40.24#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.10:47:40.24#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.10:47:40.24#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.10:47:40.24#ibcon#enter wrdev, iclass 10, count 2 2006.173.10:47:40.24#ibcon#first serial, iclass 10, count 2 2006.173.10:47:40.24#ibcon#enter sib2, iclass 10, count 2 2006.173.10:47:40.24#ibcon#flushed, iclass 10, count 2 2006.173.10:47:40.24#ibcon#about to write, iclass 10, count 2 2006.173.10:47:40.24#ibcon#wrote, iclass 10, count 2 2006.173.10:47:40.24#ibcon#about to read 3, iclass 10, count 2 2006.173.10:47:40.26#ibcon#read 3, iclass 10, count 2 2006.173.10:47:40.26#ibcon#about to read 4, iclass 10, count 2 2006.173.10:47:40.26#ibcon#read 4, iclass 10, count 2 2006.173.10:47:40.26#ibcon#about to read 5, iclass 10, count 2 2006.173.10:47:40.26#ibcon#read 5, iclass 10, count 2 2006.173.10:47:40.26#ibcon#about to read 6, iclass 10, count 2 2006.173.10:47:40.26#ibcon#read 6, iclass 10, count 2 2006.173.10:47:40.26#ibcon#end of sib2, iclass 10, count 2 2006.173.10:47:40.26#ibcon#*mode == 0, iclass 10, count 2 2006.173.10:47:40.26#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.10:47:40.26#ibcon#[25=AT01-07\r\n] 2006.173.10:47:40.26#ibcon#*before write, iclass 10, count 2 2006.173.10:47:40.26#ibcon#enter sib2, iclass 10, count 2 2006.173.10:47:40.26#ibcon#flushed, iclass 10, count 2 2006.173.10:47:40.26#ibcon#about to write, iclass 10, count 2 2006.173.10:47:40.26#ibcon#wrote, iclass 10, count 2 2006.173.10:47:40.26#ibcon#about to read 3, iclass 10, count 2 2006.173.10:47:40.29#ibcon#read 3, iclass 10, count 2 2006.173.10:47:40.29#ibcon#about to read 4, iclass 10, count 2 2006.173.10:47:40.29#ibcon#read 4, iclass 10, count 2 2006.173.10:47:40.29#ibcon#about to read 5, iclass 10, count 2 2006.173.10:47:40.29#ibcon#read 5, iclass 10, count 2 2006.173.10:47:40.29#ibcon#about to read 6, iclass 10, count 2 2006.173.10:47:40.29#ibcon#read 6, iclass 10, count 2 2006.173.10:47:40.29#ibcon#end of sib2, iclass 10, count 2 2006.173.10:47:40.29#ibcon#*after write, iclass 10, count 2 2006.173.10:47:40.29#ibcon#*before return 0, iclass 10, count 2 2006.173.10:47:40.29#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.10:47:40.29#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.10:47:40.29#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.10:47:40.29#ibcon#ireg 7 cls_cnt 0 2006.173.10:47:40.29#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.10:47:40.41#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.10:47:40.41#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.10:47:40.41#ibcon#enter wrdev, iclass 10, count 0 2006.173.10:47:40.41#ibcon#first serial, iclass 10, count 0 2006.173.10:47:40.41#ibcon#enter sib2, iclass 10, count 0 2006.173.10:47:40.41#ibcon#flushed, iclass 10, count 0 2006.173.10:47:40.41#ibcon#about to write, iclass 10, count 0 2006.173.10:47:40.41#ibcon#wrote, iclass 10, count 0 2006.173.10:47:40.41#ibcon#about to read 3, iclass 10, count 0 2006.173.10:47:40.43#ibcon#read 3, iclass 10, count 0 2006.173.10:47:40.43#ibcon#about to read 4, iclass 10, count 0 2006.173.10:47:40.43#ibcon#read 4, iclass 10, count 0 2006.173.10:47:40.43#ibcon#about to read 5, iclass 10, count 0 2006.173.10:47:40.43#ibcon#read 5, iclass 10, count 0 2006.173.10:47:40.43#ibcon#about to read 6, iclass 10, count 0 2006.173.10:47:40.43#ibcon#read 6, iclass 10, count 0 2006.173.10:47:40.43#ibcon#end of sib2, iclass 10, count 0 2006.173.10:47:40.43#ibcon#*mode == 0, iclass 10, count 0 2006.173.10:47:40.43#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.10:47:40.43#ibcon#[25=USB\r\n] 2006.173.10:47:40.43#ibcon#*before write, iclass 10, count 0 2006.173.10:47:40.43#ibcon#enter sib2, iclass 10, count 0 2006.173.10:47:40.43#ibcon#flushed, iclass 10, count 0 2006.173.10:47:40.43#ibcon#about to write, iclass 10, count 0 2006.173.10:47:40.43#ibcon#wrote, iclass 10, count 0 2006.173.10:47:40.43#ibcon#about to read 3, iclass 10, count 0 2006.173.10:47:40.46#ibcon#read 3, iclass 10, count 0 2006.173.10:47:40.46#ibcon#about to read 4, iclass 10, count 0 2006.173.10:47:40.46#ibcon#read 4, iclass 10, count 0 2006.173.10:47:40.46#ibcon#about to read 5, iclass 10, count 0 2006.173.10:47:40.46#ibcon#read 5, iclass 10, count 0 2006.173.10:47:40.46#ibcon#about to read 6, iclass 10, count 0 2006.173.10:47:40.46#ibcon#read 6, iclass 10, count 0 2006.173.10:47:40.46#ibcon#end of sib2, iclass 10, count 0 2006.173.10:47:40.46#ibcon#*after write, iclass 10, count 0 2006.173.10:47:40.46#ibcon#*before return 0, iclass 10, count 0 2006.173.10:47:40.46#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.10:47:40.46#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.10:47:40.46#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.10:47:40.46#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.10:47:40.46$vck44/valo=2,534.99 2006.173.10:47:40.46#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.10:47:40.46#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.10:47:40.46#ibcon#ireg 17 cls_cnt 0 2006.173.10:47:40.46#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.10:47:40.46#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.10:47:40.46#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.10:47:40.46#ibcon#enter wrdev, iclass 12, count 0 2006.173.10:47:40.46#ibcon#first serial, iclass 12, count 0 2006.173.10:47:40.46#ibcon#enter sib2, iclass 12, count 0 2006.173.10:47:40.46#ibcon#flushed, iclass 12, count 0 2006.173.10:47:40.46#ibcon#about to write, iclass 12, count 0 2006.173.10:47:40.46#ibcon#wrote, iclass 12, count 0 2006.173.10:47:40.46#ibcon#about to read 3, iclass 12, count 0 2006.173.10:47:40.48#ibcon#read 3, iclass 12, count 0 2006.173.10:47:40.48#ibcon#about to read 4, iclass 12, count 0 2006.173.10:47:40.48#ibcon#read 4, iclass 12, count 0 2006.173.10:47:40.48#ibcon#about to read 5, iclass 12, count 0 2006.173.10:47:40.48#ibcon#read 5, iclass 12, count 0 2006.173.10:47:40.48#ibcon#about to read 6, iclass 12, count 0 2006.173.10:47:40.48#ibcon#read 6, iclass 12, count 0 2006.173.10:47:40.48#ibcon#end of sib2, iclass 12, count 0 2006.173.10:47:40.48#ibcon#*mode == 0, iclass 12, count 0 2006.173.10:47:40.48#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.10:47:40.48#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.10:47:40.48#ibcon#*before write, iclass 12, count 0 2006.173.10:47:40.48#ibcon#enter sib2, iclass 12, count 0 2006.173.10:47:40.48#ibcon#flushed, iclass 12, count 0 2006.173.10:47:40.48#ibcon#about to write, iclass 12, count 0 2006.173.10:47:40.48#ibcon#wrote, iclass 12, count 0 2006.173.10:47:40.48#ibcon#about to read 3, iclass 12, count 0 2006.173.10:47:40.52#ibcon#read 3, iclass 12, count 0 2006.173.10:47:40.52#ibcon#about to read 4, iclass 12, count 0 2006.173.10:47:40.52#ibcon#read 4, iclass 12, count 0 2006.173.10:47:40.52#ibcon#about to read 5, iclass 12, count 0 2006.173.10:47:40.52#ibcon#read 5, iclass 12, count 0 2006.173.10:47:40.52#ibcon#about to read 6, iclass 12, count 0 2006.173.10:47:40.52#ibcon#read 6, iclass 12, count 0 2006.173.10:47:40.52#ibcon#end of sib2, iclass 12, count 0 2006.173.10:47:40.52#ibcon#*after write, iclass 12, count 0 2006.173.10:47:40.52#ibcon#*before return 0, iclass 12, count 0 2006.173.10:47:40.52#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.10:47:40.52#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.10:47:40.52#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.10:47:40.52#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.10:47:40.52$vck44/va=2,6 2006.173.10:47:40.52#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.10:47:40.52#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.10:47:40.52#ibcon#ireg 11 cls_cnt 2 2006.173.10:47:40.52#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.10:47:40.58#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.10:47:40.58#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.10:47:40.58#ibcon#enter wrdev, iclass 14, count 2 2006.173.10:47:40.58#ibcon#first serial, iclass 14, count 2 2006.173.10:47:40.58#ibcon#enter sib2, iclass 14, count 2 2006.173.10:47:40.58#ibcon#flushed, iclass 14, count 2 2006.173.10:47:40.58#ibcon#about to write, iclass 14, count 2 2006.173.10:47:40.58#ibcon#wrote, iclass 14, count 2 2006.173.10:47:40.58#ibcon#about to read 3, iclass 14, count 2 2006.173.10:47:40.60#ibcon#read 3, iclass 14, count 2 2006.173.10:47:40.60#ibcon#about to read 4, iclass 14, count 2 2006.173.10:47:40.60#ibcon#read 4, iclass 14, count 2 2006.173.10:47:40.60#ibcon#about to read 5, iclass 14, count 2 2006.173.10:47:40.60#ibcon#read 5, iclass 14, count 2 2006.173.10:47:40.60#ibcon#about to read 6, iclass 14, count 2 2006.173.10:47:40.60#ibcon#read 6, iclass 14, count 2 2006.173.10:47:40.60#ibcon#end of sib2, iclass 14, count 2 2006.173.10:47:40.60#ibcon#*mode == 0, iclass 14, count 2 2006.173.10:47:40.60#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.10:47:40.60#ibcon#[25=AT02-06\r\n] 2006.173.10:47:40.60#ibcon#*before write, iclass 14, count 2 2006.173.10:47:40.60#ibcon#enter sib2, iclass 14, count 2 2006.173.10:47:40.60#ibcon#flushed, iclass 14, count 2 2006.173.10:47:40.60#ibcon#about to write, iclass 14, count 2 2006.173.10:47:40.60#ibcon#wrote, iclass 14, count 2 2006.173.10:47:40.60#ibcon#about to read 3, iclass 14, count 2 2006.173.10:47:40.63#ibcon#read 3, iclass 14, count 2 2006.173.10:47:40.63#ibcon#about to read 4, iclass 14, count 2 2006.173.10:47:40.63#ibcon#read 4, iclass 14, count 2 2006.173.10:47:40.63#ibcon#about to read 5, iclass 14, count 2 2006.173.10:47:40.63#ibcon#read 5, iclass 14, count 2 2006.173.10:47:40.63#ibcon#about to read 6, iclass 14, count 2 2006.173.10:47:40.63#ibcon#read 6, iclass 14, count 2 2006.173.10:47:40.63#ibcon#end of sib2, iclass 14, count 2 2006.173.10:47:40.63#ibcon#*after write, iclass 14, count 2 2006.173.10:47:40.63#ibcon#*before return 0, iclass 14, count 2 2006.173.10:47:40.63#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.10:47:40.63#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.10:47:40.63#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.10:47:40.63#ibcon#ireg 7 cls_cnt 0 2006.173.10:47:40.63#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.10:47:40.75#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.10:47:40.75#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.10:47:40.75#ibcon#enter wrdev, iclass 14, count 0 2006.173.10:47:40.75#ibcon#first serial, iclass 14, count 0 2006.173.10:47:40.75#ibcon#enter sib2, iclass 14, count 0 2006.173.10:47:40.75#ibcon#flushed, iclass 14, count 0 2006.173.10:47:40.75#ibcon#about to write, iclass 14, count 0 2006.173.10:47:40.75#ibcon#wrote, iclass 14, count 0 2006.173.10:47:40.75#ibcon#about to read 3, iclass 14, count 0 2006.173.10:47:40.77#ibcon#read 3, iclass 14, count 0 2006.173.10:47:40.77#ibcon#about to read 4, iclass 14, count 0 2006.173.10:47:40.77#ibcon#read 4, iclass 14, count 0 2006.173.10:47:40.77#ibcon#about to read 5, iclass 14, count 0 2006.173.10:47:40.77#ibcon#read 5, iclass 14, count 0 2006.173.10:47:40.77#ibcon#about to read 6, iclass 14, count 0 2006.173.10:47:40.77#ibcon#read 6, iclass 14, count 0 2006.173.10:47:40.77#ibcon#end of sib2, iclass 14, count 0 2006.173.10:47:40.77#ibcon#*mode == 0, iclass 14, count 0 2006.173.10:47:40.77#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.10:47:40.77#ibcon#[25=USB\r\n] 2006.173.10:47:40.77#ibcon#*before write, iclass 14, count 0 2006.173.10:47:40.77#ibcon#enter sib2, iclass 14, count 0 2006.173.10:47:40.77#ibcon#flushed, iclass 14, count 0 2006.173.10:47:40.77#ibcon#about to write, iclass 14, count 0 2006.173.10:47:40.77#ibcon#wrote, iclass 14, count 0 2006.173.10:47:40.77#ibcon#about to read 3, iclass 14, count 0 2006.173.10:47:40.80#ibcon#read 3, iclass 14, count 0 2006.173.10:47:40.80#ibcon#about to read 4, iclass 14, count 0 2006.173.10:47:40.80#ibcon#read 4, iclass 14, count 0 2006.173.10:47:40.80#ibcon#about to read 5, iclass 14, count 0 2006.173.10:47:40.80#ibcon#read 5, iclass 14, count 0 2006.173.10:47:40.80#ibcon#about to read 6, iclass 14, count 0 2006.173.10:47:40.80#ibcon#read 6, iclass 14, count 0 2006.173.10:47:40.80#ibcon#end of sib2, iclass 14, count 0 2006.173.10:47:40.80#ibcon#*after write, iclass 14, count 0 2006.173.10:47:40.80#ibcon#*before return 0, iclass 14, count 0 2006.173.10:47:40.80#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.10:47:40.80#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.10:47:40.80#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.10:47:40.80#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.10:47:40.80$vck44/valo=3,564.99 2006.173.10:47:40.80#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.10:47:40.80#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.10:47:40.80#ibcon#ireg 17 cls_cnt 0 2006.173.10:47:40.80#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.10:47:40.80#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.10:47:40.80#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.10:47:40.80#ibcon#enter wrdev, iclass 16, count 0 2006.173.10:47:40.80#ibcon#first serial, iclass 16, count 0 2006.173.10:47:40.80#ibcon#enter sib2, iclass 16, count 0 2006.173.10:47:40.80#ibcon#flushed, iclass 16, count 0 2006.173.10:47:40.80#ibcon#about to write, iclass 16, count 0 2006.173.10:47:40.80#ibcon#wrote, iclass 16, count 0 2006.173.10:47:40.80#ibcon#about to read 3, iclass 16, count 0 2006.173.10:47:40.82#ibcon#read 3, iclass 16, count 0 2006.173.10:47:40.82#ibcon#about to read 4, iclass 16, count 0 2006.173.10:47:40.82#ibcon#read 4, iclass 16, count 0 2006.173.10:47:40.82#ibcon#about to read 5, iclass 16, count 0 2006.173.10:47:40.82#ibcon#read 5, iclass 16, count 0 2006.173.10:47:40.82#ibcon#about to read 6, iclass 16, count 0 2006.173.10:47:40.82#ibcon#read 6, iclass 16, count 0 2006.173.10:47:40.82#ibcon#end of sib2, iclass 16, count 0 2006.173.10:47:40.82#ibcon#*mode == 0, iclass 16, count 0 2006.173.10:47:40.82#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.10:47:40.82#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.10:47:40.82#ibcon#*before write, iclass 16, count 0 2006.173.10:47:40.82#ibcon#enter sib2, iclass 16, count 0 2006.173.10:47:40.82#ibcon#flushed, iclass 16, count 0 2006.173.10:47:40.82#ibcon#about to write, iclass 16, count 0 2006.173.10:47:40.82#ibcon#wrote, iclass 16, count 0 2006.173.10:47:40.82#ibcon#about to read 3, iclass 16, count 0 2006.173.10:47:40.86#ibcon#read 3, iclass 16, count 0 2006.173.10:47:40.86#ibcon#about to read 4, iclass 16, count 0 2006.173.10:47:40.86#ibcon#read 4, iclass 16, count 0 2006.173.10:47:40.86#ibcon#about to read 5, iclass 16, count 0 2006.173.10:47:40.86#ibcon#read 5, iclass 16, count 0 2006.173.10:47:40.86#ibcon#about to read 6, iclass 16, count 0 2006.173.10:47:40.86#ibcon#read 6, iclass 16, count 0 2006.173.10:47:40.86#ibcon#end of sib2, iclass 16, count 0 2006.173.10:47:40.86#ibcon#*after write, iclass 16, count 0 2006.173.10:47:40.86#ibcon#*before return 0, iclass 16, count 0 2006.173.10:47:40.86#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.10:47:40.86#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.10:47:40.86#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.10:47:40.86#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.10:47:40.86$vck44/va=3,5 2006.173.10:47:40.86#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.10:47:40.86#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.10:47:40.86#ibcon#ireg 11 cls_cnt 2 2006.173.10:47:40.86#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.10:47:40.92#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.10:47:40.92#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.10:47:40.92#ibcon#enter wrdev, iclass 18, count 2 2006.173.10:47:40.92#ibcon#first serial, iclass 18, count 2 2006.173.10:47:40.92#ibcon#enter sib2, iclass 18, count 2 2006.173.10:47:40.92#ibcon#flushed, iclass 18, count 2 2006.173.10:47:40.92#ibcon#about to write, iclass 18, count 2 2006.173.10:47:40.92#ibcon#wrote, iclass 18, count 2 2006.173.10:47:40.92#ibcon#about to read 3, iclass 18, count 2 2006.173.10:47:40.94#ibcon#read 3, iclass 18, count 2 2006.173.10:47:40.94#ibcon#about to read 4, iclass 18, count 2 2006.173.10:47:40.94#ibcon#read 4, iclass 18, count 2 2006.173.10:47:40.94#ibcon#about to read 5, iclass 18, count 2 2006.173.10:47:40.94#ibcon#read 5, iclass 18, count 2 2006.173.10:47:40.94#ibcon#about to read 6, iclass 18, count 2 2006.173.10:47:40.94#ibcon#read 6, iclass 18, count 2 2006.173.10:47:40.94#ibcon#end of sib2, iclass 18, count 2 2006.173.10:47:40.94#ibcon#*mode == 0, iclass 18, count 2 2006.173.10:47:40.94#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.10:47:40.94#ibcon#[25=AT03-05\r\n] 2006.173.10:47:40.94#ibcon#*before write, iclass 18, count 2 2006.173.10:47:40.94#ibcon#enter sib2, iclass 18, count 2 2006.173.10:47:40.94#ibcon#flushed, iclass 18, count 2 2006.173.10:47:40.94#ibcon#about to write, iclass 18, count 2 2006.173.10:47:40.94#ibcon#wrote, iclass 18, count 2 2006.173.10:47:40.94#ibcon#about to read 3, iclass 18, count 2 2006.173.10:47:40.97#ibcon#read 3, iclass 18, count 2 2006.173.10:47:40.97#ibcon#about to read 4, iclass 18, count 2 2006.173.10:47:40.97#ibcon#read 4, iclass 18, count 2 2006.173.10:47:40.97#ibcon#about to read 5, iclass 18, count 2 2006.173.10:47:40.97#ibcon#read 5, iclass 18, count 2 2006.173.10:47:40.97#ibcon#about to read 6, iclass 18, count 2 2006.173.10:47:40.97#ibcon#read 6, iclass 18, count 2 2006.173.10:47:40.97#ibcon#end of sib2, iclass 18, count 2 2006.173.10:47:40.97#ibcon#*after write, iclass 18, count 2 2006.173.10:47:40.97#ibcon#*before return 0, iclass 18, count 2 2006.173.10:47:40.97#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.10:47:40.97#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.10:47:40.97#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.10:47:40.97#ibcon#ireg 7 cls_cnt 0 2006.173.10:47:40.97#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.10:47:41.09#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.10:47:41.09#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.10:47:41.09#ibcon#enter wrdev, iclass 18, count 0 2006.173.10:47:41.09#ibcon#first serial, iclass 18, count 0 2006.173.10:47:41.09#ibcon#enter sib2, iclass 18, count 0 2006.173.10:47:41.09#ibcon#flushed, iclass 18, count 0 2006.173.10:47:41.09#ibcon#about to write, iclass 18, count 0 2006.173.10:47:41.09#ibcon#wrote, iclass 18, count 0 2006.173.10:47:41.09#ibcon#about to read 3, iclass 18, count 0 2006.173.10:47:41.11#ibcon#read 3, iclass 18, count 0 2006.173.10:47:41.11#ibcon#about to read 4, iclass 18, count 0 2006.173.10:47:41.11#ibcon#read 4, iclass 18, count 0 2006.173.10:47:41.11#ibcon#about to read 5, iclass 18, count 0 2006.173.10:47:41.11#ibcon#read 5, iclass 18, count 0 2006.173.10:47:41.11#ibcon#about to read 6, iclass 18, count 0 2006.173.10:47:41.11#ibcon#read 6, iclass 18, count 0 2006.173.10:47:41.11#ibcon#end of sib2, iclass 18, count 0 2006.173.10:47:41.11#ibcon#*mode == 0, iclass 18, count 0 2006.173.10:47:41.11#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.10:47:41.11#ibcon#[25=USB\r\n] 2006.173.10:47:41.11#ibcon#*before write, iclass 18, count 0 2006.173.10:47:41.11#ibcon#enter sib2, iclass 18, count 0 2006.173.10:47:41.11#ibcon#flushed, iclass 18, count 0 2006.173.10:47:41.11#ibcon#about to write, iclass 18, count 0 2006.173.10:47:41.11#ibcon#wrote, iclass 18, count 0 2006.173.10:47:41.11#ibcon#about to read 3, iclass 18, count 0 2006.173.10:47:41.14#ibcon#read 3, iclass 18, count 0 2006.173.10:47:41.14#ibcon#about to read 4, iclass 18, count 0 2006.173.10:47:41.14#ibcon#read 4, iclass 18, count 0 2006.173.10:47:41.14#ibcon#about to read 5, iclass 18, count 0 2006.173.10:47:41.14#ibcon#read 5, iclass 18, count 0 2006.173.10:47:41.14#ibcon#about to read 6, iclass 18, count 0 2006.173.10:47:41.14#ibcon#read 6, iclass 18, count 0 2006.173.10:47:41.14#ibcon#end of sib2, iclass 18, count 0 2006.173.10:47:41.14#ibcon#*after write, iclass 18, count 0 2006.173.10:47:41.14#ibcon#*before return 0, iclass 18, count 0 2006.173.10:47:41.14#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.10:47:41.14#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.10:47:41.14#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.10:47:41.14#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.10:47:41.14$vck44/valo=4,624.99 2006.173.10:47:41.14#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.10:47:41.14#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.10:47:41.14#ibcon#ireg 17 cls_cnt 0 2006.173.10:47:41.14#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.10:47:41.14#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.10:47:41.14#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.10:47:41.14#ibcon#enter wrdev, iclass 20, count 0 2006.173.10:47:41.14#ibcon#first serial, iclass 20, count 0 2006.173.10:47:41.14#ibcon#enter sib2, iclass 20, count 0 2006.173.10:47:41.14#ibcon#flushed, iclass 20, count 0 2006.173.10:47:41.14#ibcon#about to write, iclass 20, count 0 2006.173.10:47:41.14#ibcon#wrote, iclass 20, count 0 2006.173.10:47:41.14#ibcon#about to read 3, iclass 20, count 0 2006.173.10:47:41.16#ibcon#read 3, iclass 20, count 0 2006.173.10:47:41.16#ibcon#about to read 4, iclass 20, count 0 2006.173.10:47:41.16#ibcon#read 4, iclass 20, count 0 2006.173.10:47:41.16#ibcon#about to read 5, iclass 20, count 0 2006.173.10:47:41.16#ibcon#read 5, iclass 20, count 0 2006.173.10:47:41.16#ibcon#about to read 6, iclass 20, count 0 2006.173.10:47:41.16#ibcon#read 6, iclass 20, count 0 2006.173.10:47:41.16#ibcon#end of sib2, iclass 20, count 0 2006.173.10:47:41.16#ibcon#*mode == 0, iclass 20, count 0 2006.173.10:47:41.16#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.10:47:41.16#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.10:47:41.16#ibcon#*before write, iclass 20, count 0 2006.173.10:47:41.16#ibcon#enter sib2, iclass 20, count 0 2006.173.10:47:41.16#ibcon#flushed, iclass 20, count 0 2006.173.10:47:41.16#ibcon#about to write, iclass 20, count 0 2006.173.10:47:41.16#ibcon#wrote, iclass 20, count 0 2006.173.10:47:41.16#ibcon#about to read 3, iclass 20, count 0 2006.173.10:47:41.20#ibcon#read 3, iclass 20, count 0 2006.173.10:47:41.20#ibcon#about to read 4, iclass 20, count 0 2006.173.10:47:41.20#ibcon#read 4, iclass 20, count 0 2006.173.10:47:41.20#ibcon#about to read 5, iclass 20, count 0 2006.173.10:47:41.20#ibcon#read 5, iclass 20, count 0 2006.173.10:47:41.20#ibcon#about to read 6, iclass 20, count 0 2006.173.10:47:41.20#ibcon#read 6, iclass 20, count 0 2006.173.10:47:41.20#ibcon#end of sib2, iclass 20, count 0 2006.173.10:47:41.20#ibcon#*after write, iclass 20, count 0 2006.173.10:47:41.20#ibcon#*before return 0, iclass 20, count 0 2006.173.10:47:41.20#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.10:47:41.20#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.10:47:41.20#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.10:47:41.20#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.10:47:41.20$vck44/va=4,6 2006.173.10:47:41.20#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.10:47:41.20#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.10:47:41.20#ibcon#ireg 11 cls_cnt 2 2006.173.10:47:41.20#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.10:47:41.26#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.10:47:41.26#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.10:47:41.26#ibcon#enter wrdev, iclass 22, count 2 2006.173.10:47:41.26#ibcon#first serial, iclass 22, count 2 2006.173.10:47:41.26#ibcon#enter sib2, iclass 22, count 2 2006.173.10:47:41.26#ibcon#flushed, iclass 22, count 2 2006.173.10:47:41.26#ibcon#about to write, iclass 22, count 2 2006.173.10:47:41.26#ibcon#wrote, iclass 22, count 2 2006.173.10:47:41.26#ibcon#about to read 3, iclass 22, count 2 2006.173.10:47:41.28#ibcon#read 3, iclass 22, count 2 2006.173.10:47:41.28#ibcon#about to read 4, iclass 22, count 2 2006.173.10:47:41.28#ibcon#read 4, iclass 22, count 2 2006.173.10:47:41.28#ibcon#about to read 5, iclass 22, count 2 2006.173.10:47:41.28#ibcon#read 5, iclass 22, count 2 2006.173.10:47:41.28#ibcon#about to read 6, iclass 22, count 2 2006.173.10:47:41.28#ibcon#read 6, iclass 22, count 2 2006.173.10:47:41.28#ibcon#end of sib2, iclass 22, count 2 2006.173.10:47:41.28#ibcon#*mode == 0, iclass 22, count 2 2006.173.10:47:41.28#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.10:47:41.28#ibcon#[25=AT04-06\r\n] 2006.173.10:47:41.28#ibcon#*before write, iclass 22, count 2 2006.173.10:47:41.28#ibcon#enter sib2, iclass 22, count 2 2006.173.10:47:41.28#ibcon#flushed, iclass 22, count 2 2006.173.10:47:41.28#ibcon#about to write, iclass 22, count 2 2006.173.10:47:41.28#ibcon#wrote, iclass 22, count 2 2006.173.10:47:41.28#ibcon#about to read 3, iclass 22, count 2 2006.173.10:47:41.31#ibcon#read 3, iclass 22, count 2 2006.173.10:47:41.31#ibcon#about to read 4, iclass 22, count 2 2006.173.10:47:41.31#ibcon#read 4, iclass 22, count 2 2006.173.10:47:41.31#ibcon#about to read 5, iclass 22, count 2 2006.173.10:47:41.31#ibcon#read 5, iclass 22, count 2 2006.173.10:47:41.31#ibcon#about to read 6, iclass 22, count 2 2006.173.10:47:41.31#ibcon#read 6, iclass 22, count 2 2006.173.10:47:41.31#ibcon#end of sib2, iclass 22, count 2 2006.173.10:47:41.31#ibcon#*after write, iclass 22, count 2 2006.173.10:47:41.31#ibcon#*before return 0, iclass 22, count 2 2006.173.10:47:41.31#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.10:47:41.31#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.10:47:41.31#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.10:47:41.31#ibcon#ireg 7 cls_cnt 0 2006.173.10:47:41.31#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.10:47:41.43#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.10:47:41.43#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.10:47:41.43#ibcon#enter wrdev, iclass 22, count 0 2006.173.10:47:41.43#ibcon#first serial, iclass 22, count 0 2006.173.10:47:41.43#ibcon#enter sib2, iclass 22, count 0 2006.173.10:47:41.43#ibcon#flushed, iclass 22, count 0 2006.173.10:47:41.43#ibcon#about to write, iclass 22, count 0 2006.173.10:47:41.43#ibcon#wrote, iclass 22, count 0 2006.173.10:47:41.43#ibcon#about to read 3, iclass 22, count 0 2006.173.10:47:41.45#ibcon#read 3, iclass 22, count 0 2006.173.10:47:41.45#ibcon#about to read 4, iclass 22, count 0 2006.173.10:47:41.45#ibcon#read 4, iclass 22, count 0 2006.173.10:47:41.45#ibcon#about to read 5, iclass 22, count 0 2006.173.10:47:41.45#ibcon#read 5, iclass 22, count 0 2006.173.10:47:41.45#ibcon#about to read 6, iclass 22, count 0 2006.173.10:47:41.45#ibcon#read 6, iclass 22, count 0 2006.173.10:47:41.45#ibcon#end of sib2, iclass 22, count 0 2006.173.10:47:41.45#ibcon#*mode == 0, iclass 22, count 0 2006.173.10:47:41.45#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.10:47:41.45#ibcon#[25=USB\r\n] 2006.173.10:47:41.45#ibcon#*before write, iclass 22, count 0 2006.173.10:47:41.45#ibcon#enter sib2, iclass 22, count 0 2006.173.10:47:41.45#ibcon#flushed, iclass 22, count 0 2006.173.10:47:41.45#ibcon#about to write, iclass 22, count 0 2006.173.10:47:41.45#ibcon#wrote, iclass 22, count 0 2006.173.10:47:41.45#ibcon#about to read 3, iclass 22, count 0 2006.173.10:47:41.48#ibcon#read 3, iclass 22, count 0 2006.173.10:47:41.48#ibcon#about to read 4, iclass 22, count 0 2006.173.10:47:41.48#ibcon#read 4, iclass 22, count 0 2006.173.10:47:41.48#ibcon#about to read 5, iclass 22, count 0 2006.173.10:47:41.48#ibcon#read 5, iclass 22, count 0 2006.173.10:47:41.48#ibcon#about to read 6, iclass 22, count 0 2006.173.10:47:41.48#ibcon#read 6, iclass 22, count 0 2006.173.10:47:41.48#ibcon#end of sib2, iclass 22, count 0 2006.173.10:47:41.48#ibcon#*after write, iclass 22, count 0 2006.173.10:47:41.48#ibcon#*before return 0, iclass 22, count 0 2006.173.10:47:41.48#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.10:47:41.48#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.10:47:41.48#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.10:47:41.48#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.10:47:41.48$vck44/valo=5,734.99 2006.173.10:47:41.48#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.10:47:41.48#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.10:47:41.48#ibcon#ireg 17 cls_cnt 0 2006.173.10:47:41.48#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.10:47:41.48#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.10:47:41.48#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.10:47:41.48#ibcon#enter wrdev, iclass 24, count 0 2006.173.10:47:41.48#ibcon#first serial, iclass 24, count 0 2006.173.10:47:41.48#ibcon#enter sib2, iclass 24, count 0 2006.173.10:47:41.48#ibcon#flushed, iclass 24, count 0 2006.173.10:47:41.48#ibcon#about to write, iclass 24, count 0 2006.173.10:47:41.48#ibcon#wrote, iclass 24, count 0 2006.173.10:47:41.48#ibcon#about to read 3, iclass 24, count 0 2006.173.10:47:41.50#ibcon#read 3, iclass 24, count 0 2006.173.10:47:41.50#ibcon#about to read 4, iclass 24, count 0 2006.173.10:47:41.50#ibcon#read 4, iclass 24, count 0 2006.173.10:47:41.50#ibcon#about to read 5, iclass 24, count 0 2006.173.10:47:41.50#ibcon#read 5, iclass 24, count 0 2006.173.10:47:41.50#ibcon#about to read 6, iclass 24, count 0 2006.173.10:47:41.50#ibcon#read 6, iclass 24, count 0 2006.173.10:47:41.50#ibcon#end of sib2, iclass 24, count 0 2006.173.10:47:41.50#ibcon#*mode == 0, iclass 24, count 0 2006.173.10:47:41.50#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.10:47:41.50#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.10:47:41.50#ibcon#*before write, iclass 24, count 0 2006.173.10:47:41.50#ibcon#enter sib2, iclass 24, count 0 2006.173.10:47:41.50#ibcon#flushed, iclass 24, count 0 2006.173.10:47:41.50#ibcon#about to write, iclass 24, count 0 2006.173.10:47:41.50#ibcon#wrote, iclass 24, count 0 2006.173.10:47:41.50#ibcon#about to read 3, iclass 24, count 0 2006.173.10:47:41.54#ibcon#read 3, iclass 24, count 0 2006.173.10:47:41.54#ibcon#about to read 4, iclass 24, count 0 2006.173.10:47:41.54#ibcon#read 4, iclass 24, count 0 2006.173.10:47:41.54#ibcon#about to read 5, iclass 24, count 0 2006.173.10:47:41.54#ibcon#read 5, iclass 24, count 0 2006.173.10:47:41.54#ibcon#about to read 6, iclass 24, count 0 2006.173.10:47:41.54#ibcon#read 6, iclass 24, count 0 2006.173.10:47:41.54#ibcon#end of sib2, iclass 24, count 0 2006.173.10:47:41.54#ibcon#*after write, iclass 24, count 0 2006.173.10:47:41.54#ibcon#*before return 0, iclass 24, count 0 2006.173.10:47:41.54#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.10:47:41.54#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.10:47:41.54#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.10:47:41.54#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.10:47:41.54$vck44/va=5,4 2006.173.10:47:41.54#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.10:47:41.54#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.10:47:41.54#ibcon#ireg 11 cls_cnt 2 2006.173.10:47:41.54#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.10:47:41.60#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.10:47:41.60#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.10:47:41.60#ibcon#enter wrdev, iclass 26, count 2 2006.173.10:47:41.60#ibcon#first serial, iclass 26, count 2 2006.173.10:47:41.60#ibcon#enter sib2, iclass 26, count 2 2006.173.10:47:41.60#ibcon#flushed, iclass 26, count 2 2006.173.10:47:41.60#ibcon#about to write, iclass 26, count 2 2006.173.10:47:41.60#ibcon#wrote, iclass 26, count 2 2006.173.10:47:41.60#ibcon#about to read 3, iclass 26, count 2 2006.173.10:47:41.62#ibcon#read 3, iclass 26, count 2 2006.173.10:47:41.62#ibcon#about to read 4, iclass 26, count 2 2006.173.10:47:41.62#ibcon#read 4, iclass 26, count 2 2006.173.10:47:41.62#ibcon#about to read 5, iclass 26, count 2 2006.173.10:47:41.62#ibcon#read 5, iclass 26, count 2 2006.173.10:47:41.62#ibcon#about to read 6, iclass 26, count 2 2006.173.10:47:41.62#ibcon#read 6, iclass 26, count 2 2006.173.10:47:41.62#ibcon#end of sib2, iclass 26, count 2 2006.173.10:47:41.62#ibcon#*mode == 0, iclass 26, count 2 2006.173.10:47:41.62#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.10:47:41.62#ibcon#[25=AT05-04\r\n] 2006.173.10:47:41.62#ibcon#*before write, iclass 26, count 2 2006.173.10:47:41.62#ibcon#enter sib2, iclass 26, count 2 2006.173.10:47:41.62#ibcon#flushed, iclass 26, count 2 2006.173.10:47:41.62#ibcon#about to write, iclass 26, count 2 2006.173.10:47:41.62#ibcon#wrote, iclass 26, count 2 2006.173.10:47:41.62#ibcon#about to read 3, iclass 26, count 2 2006.173.10:47:41.65#ibcon#read 3, iclass 26, count 2 2006.173.10:47:41.65#ibcon#about to read 4, iclass 26, count 2 2006.173.10:47:41.65#ibcon#read 4, iclass 26, count 2 2006.173.10:47:41.65#ibcon#about to read 5, iclass 26, count 2 2006.173.10:47:41.65#ibcon#read 5, iclass 26, count 2 2006.173.10:47:41.65#ibcon#about to read 6, iclass 26, count 2 2006.173.10:47:41.65#ibcon#read 6, iclass 26, count 2 2006.173.10:47:41.65#ibcon#end of sib2, iclass 26, count 2 2006.173.10:47:41.65#ibcon#*after write, iclass 26, count 2 2006.173.10:47:41.65#ibcon#*before return 0, iclass 26, count 2 2006.173.10:47:41.65#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.10:47:41.65#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.10:47:41.65#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.10:47:41.65#ibcon#ireg 7 cls_cnt 0 2006.173.10:47:41.65#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.10:47:41.77#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.10:47:41.77#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.10:47:41.77#ibcon#enter wrdev, iclass 26, count 0 2006.173.10:47:41.77#ibcon#first serial, iclass 26, count 0 2006.173.10:47:41.77#ibcon#enter sib2, iclass 26, count 0 2006.173.10:47:41.77#ibcon#flushed, iclass 26, count 0 2006.173.10:47:41.77#ibcon#about to write, iclass 26, count 0 2006.173.10:47:41.77#ibcon#wrote, iclass 26, count 0 2006.173.10:47:41.77#ibcon#about to read 3, iclass 26, count 0 2006.173.10:47:41.79#ibcon#read 3, iclass 26, count 0 2006.173.10:47:41.79#ibcon#about to read 4, iclass 26, count 0 2006.173.10:47:41.79#ibcon#read 4, iclass 26, count 0 2006.173.10:47:41.79#ibcon#about to read 5, iclass 26, count 0 2006.173.10:47:41.79#ibcon#read 5, iclass 26, count 0 2006.173.10:47:41.79#ibcon#about to read 6, iclass 26, count 0 2006.173.10:47:41.79#ibcon#read 6, iclass 26, count 0 2006.173.10:47:41.79#ibcon#end of sib2, iclass 26, count 0 2006.173.10:47:41.79#ibcon#*mode == 0, iclass 26, count 0 2006.173.10:47:41.79#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.10:47:41.79#ibcon#[25=USB\r\n] 2006.173.10:47:41.79#ibcon#*before write, iclass 26, count 0 2006.173.10:47:41.79#ibcon#enter sib2, iclass 26, count 0 2006.173.10:47:41.79#ibcon#flushed, iclass 26, count 0 2006.173.10:47:41.79#ibcon#about to write, iclass 26, count 0 2006.173.10:47:41.79#ibcon#wrote, iclass 26, count 0 2006.173.10:47:41.79#ibcon#about to read 3, iclass 26, count 0 2006.173.10:47:41.82#ibcon#read 3, iclass 26, count 0 2006.173.10:47:41.82#ibcon#about to read 4, iclass 26, count 0 2006.173.10:47:41.82#ibcon#read 4, iclass 26, count 0 2006.173.10:47:41.82#ibcon#about to read 5, iclass 26, count 0 2006.173.10:47:41.82#ibcon#read 5, iclass 26, count 0 2006.173.10:47:41.82#ibcon#about to read 6, iclass 26, count 0 2006.173.10:47:41.82#ibcon#read 6, iclass 26, count 0 2006.173.10:47:41.82#ibcon#end of sib2, iclass 26, count 0 2006.173.10:47:41.82#ibcon#*after write, iclass 26, count 0 2006.173.10:47:41.82#ibcon#*before return 0, iclass 26, count 0 2006.173.10:47:41.82#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.10:47:41.82#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.10:47:41.82#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.10:47:41.82#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.10:47:41.82$vck44/valo=6,814.99 2006.173.10:47:41.82#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.10:47:41.82#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.10:47:41.82#ibcon#ireg 17 cls_cnt 0 2006.173.10:47:41.82#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.10:47:41.82#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.10:47:41.82#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.10:47:41.82#ibcon#enter wrdev, iclass 28, count 0 2006.173.10:47:41.82#ibcon#first serial, iclass 28, count 0 2006.173.10:47:41.82#ibcon#enter sib2, iclass 28, count 0 2006.173.10:47:41.82#ibcon#flushed, iclass 28, count 0 2006.173.10:47:41.82#ibcon#about to write, iclass 28, count 0 2006.173.10:47:41.82#ibcon#wrote, iclass 28, count 0 2006.173.10:47:41.82#ibcon#about to read 3, iclass 28, count 0 2006.173.10:47:41.84#ibcon#read 3, iclass 28, count 0 2006.173.10:47:41.84#ibcon#about to read 4, iclass 28, count 0 2006.173.10:47:41.84#ibcon#read 4, iclass 28, count 0 2006.173.10:47:41.84#ibcon#about to read 5, iclass 28, count 0 2006.173.10:47:41.84#ibcon#read 5, iclass 28, count 0 2006.173.10:47:41.84#ibcon#about to read 6, iclass 28, count 0 2006.173.10:47:41.84#ibcon#read 6, iclass 28, count 0 2006.173.10:47:41.84#ibcon#end of sib2, iclass 28, count 0 2006.173.10:47:41.84#ibcon#*mode == 0, iclass 28, count 0 2006.173.10:47:41.84#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.10:47:41.84#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.10:47:41.84#ibcon#*before write, iclass 28, count 0 2006.173.10:47:41.84#ibcon#enter sib2, iclass 28, count 0 2006.173.10:47:41.84#ibcon#flushed, iclass 28, count 0 2006.173.10:47:41.84#ibcon#about to write, iclass 28, count 0 2006.173.10:47:41.84#ibcon#wrote, iclass 28, count 0 2006.173.10:47:41.84#ibcon#about to read 3, iclass 28, count 0 2006.173.10:47:41.88#ibcon#read 3, iclass 28, count 0 2006.173.10:47:41.88#ibcon#about to read 4, iclass 28, count 0 2006.173.10:47:41.88#ibcon#read 4, iclass 28, count 0 2006.173.10:47:41.88#ibcon#about to read 5, iclass 28, count 0 2006.173.10:47:41.88#ibcon#read 5, iclass 28, count 0 2006.173.10:47:41.88#ibcon#about to read 6, iclass 28, count 0 2006.173.10:47:41.88#ibcon#read 6, iclass 28, count 0 2006.173.10:47:41.88#ibcon#end of sib2, iclass 28, count 0 2006.173.10:47:41.88#ibcon#*after write, iclass 28, count 0 2006.173.10:47:41.88#ibcon#*before return 0, iclass 28, count 0 2006.173.10:47:41.88#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.10:47:41.88#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.10:47:41.88#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.10:47:41.88#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.10:47:41.88$vck44/va=6,3 2006.173.10:47:41.88#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.10:47:41.88#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.10:47:41.88#ibcon#ireg 11 cls_cnt 2 2006.173.10:47:41.88#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.10:47:41.94#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.10:47:41.94#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.10:47:41.94#ibcon#enter wrdev, iclass 30, count 2 2006.173.10:47:41.94#ibcon#first serial, iclass 30, count 2 2006.173.10:47:41.94#ibcon#enter sib2, iclass 30, count 2 2006.173.10:47:41.94#ibcon#flushed, iclass 30, count 2 2006.173.10:47:41.94#ibcon#about to write, iclass 30, count 2 2006.173.10:47:41.94#ibcon#wrote, iclass 30, count 2 2006.173.10:47:41.94#ibcon#about to read 3, iclass 30, count 2 2006.173.10:47:41.96#ibcon#read 3, iclass 30, count 2 2006.173.10:47:41.96#ibcon#about to read 4, iclass 30, count 2 2006.173.10:47:41.96#ibcon#read 4, iclass 30, count 2 2006.173.10:47:41.96#ibcon#about to read 5, iclass 30, count 2 2006.173.10:47:41.96#ibcon#read 5, iclass 30, count 2 2006.173.10:47:41.96#ibcon#about to read 6, iclass 30, count 2 2006.173.10:47:41.96#ibcon#read 6, iclass 30, count 2 2006.173.10:47:41.96#ibcon#end of sib2, iclass 30, count 2 2006.173.10:47:41.96#ibcon#*mode == 0, iclass 30, count 2 2006.173.10:47:41.96#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.10:47:41.96#ibcon#[25=AT06-03\r\n] 2006.173.10:47:41.96#ibcon#*before write, iclass 30, count 2 2006.173.10:47:41.96#ibcon#enter sib2, iclass 30, count 2 2006.173.10:47:41.96#ibcon#flushed, iclass 30, count 2 2006.173.10:47:41.96#ibcon#about to write, iclass 30, count 2 2006.173.10:47:41.96#ibcon#wrote, iclass 30, count 2 2006.173.10:47:41.96#ibcon#about to read 3, iclass 30, count 2 2006.173.10:47:41.99#ibcon#read 3, iclass 30, count 2 2006.173.10:47:41.99#ibcon#about to read 4, iclass 30, count 2 2006.173.10:47:41.99#ibcon#read 4, iclass 30, count 2 2006.173.10:47:41.99#ibcon#about to read 5, iclass 30, count 2 2006.173.10:47:41.99#ibcon#read 5, iclass 30, count 2 2006.173.10:47:41.99#ibcon#about to read 6, iclass 30, count 2 2006.173.10:47:41.99#ibcon#read 6, iclass 30, count 2 2006.173.10:47:41.99#ibcon#end of sib2, iclass 30, count 2 2006.173.10:47:41.99#ibcon#*after write, iclass 30, count 2 2006.173.10:47:41.99#ibcon#*before return 0, iclass 30, count 2 2006.173.10:47:41.99#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.10:47:41.99#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.10:47:41.99#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.10:47:41.99#ibcon#ireg 7 cls_cnt 0 2006.173.10:47:41.99#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.10:47:42.11#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.10:47:42.11#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.10:47:42.11#ibcon#enter wrdev, iclass 30, count 0 2006.173.10:47:42.11#ibcon#first serial, iclass 30, count 0 2006.173.10:47:42.11#ibcon#enter sib2, iclass 30, count 0 2006.173.10:47:42.11#ibcon#flushed, iclass 30, count 0 2006.173.10:47:42.11#ibcon#about to write, iclass 30, count 0 2006.173.10:47:42.11#ibcon#wrote, iclass 30, count 0 2006.173.10:47:42.11#ibcon#about to read 3, iclass 30, count 0 2006.173.10:47:42.13#ibcon#read 3, iclass 30, count 0 2006.173.10:47:42.13#ibcon#about to read 4, iclass 30, count 0 2006.173.10:47:42.13#ibcon#read 4, iclass 30, count 0 2006.173.10:47:42.13#ibcon#about to read 5, iclass 30, count 0 2006.173.10:47:42.13#ibcon#read 5, iclass 30, count 0 2006.173.10:47:42.13#ibcon#about to read 6, iclass 30, count 0 2006.173.10:47:42.13#ibcon#read 6, iclass 30, count 0 2006.173.10:47:42.13#ibcon#end of sib2, iclass 30, count 0 2006.173.10:47:42.13#ibcon#*mode == 0, iclass 30, count 0 2006.173.10:47:42.13#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.10:47:42.13#ibcon#[25=USB\r\n] 2006.173.10:47:42.13#ibcon#*before write, iclass 30, count 0 2006.173.10:47:42.13#ibcon#enter sib2, iclass 30, count 0 2006.173.10:47:42.13#ibcon#flushed, iclass 30, count 0 2006.173.10:47:42.13#ibcon#about to write, iclass 30, count 0 2006.173.10:47:42.13#ibcon#wrote, iclass 30, count 0 2006.173.10:47:42.13#ibcon#about to read 3, iclass 30, count 0 2006.173.10:47:42.16#ibcon#read 3, iclass 30, count 0 2006.173.10:47:42.16#ibcon#about to read 4, iclass 30, count 0 2006.173.10:47:42.16#ibcon#read 4, iclass 30, count 0 2006.173.10:47:42.16#ibcon#about to read 5, iclass 30, count 0 2006.173.10:47:42.16#ibcon#read 5, iclass 30, count 0 2006.173.10:47:42.16#ibcon#about to read 6, iclass 30, count 0 2006.173.10:47:42.16#ibcon#read 6, iclass 30, count 0 2006.173.10:47:42.16#ibcon#end of sib2, iclass 30, count 0 2006.173.10:47:42.16#ibcon#*after write, iclass 30, count 0 2006.173.10:47:42.16#ibcon#*before return 0, iclass 30, count 0 2006.173.10:47:42.16#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.10:47:42.16#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.10:47:42.16#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.10:47:42.16#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.10:47:42.16$vck44/valo=7,864.99 2006.173.10:47:42.16#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.10:47:42.16#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.10:47:42.16#ibcon#ireg 17 cls_cnt 0 2006.173.10:47:42.16#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.10:47:42.16#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.10:47:42.16#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.10:47:42.16#ibcon#enter wrdev, iclass 32, count 0 2006.173.10:47:42.16#ibcon#first serial, iclass 32, count 0 2006.173.10:47:42.16#ibcon#enter sib2, iclass 32, count 0 2006.173.10:47:42.16#ibcon#flushed, iclass 32, count 0 2006.173.10:47:42.16#ibcon#about to write, iclass 32, count 0 2006.173.10:47:42.16#ibcon#wrote, iclass 32, count 0 2006.173.10:47:42.16#ibcon#about to read 3, iclass 32, count 0 2006.173.10:47:42.18#ibcon#read 3, iclass 32, count 0 2006.173.10:47:42.18#ibcon#about to read 4, iclass 32, count 0 2006.173.10:47:42.18#ibcon#read 4, iclass 32, count 0 2006.173.10:47:42.18#ibcon#about to read 5, iclass 32, count 0 2006.173.10:47:42.18#ibcon#read 5, iclass 32, count 0 2006.173.10:47:42.18#ibcon#about to read 6, iclass 32, count 0 2006.173.10:47:42.18#ibcon#read 6, iclass 32, count 0 2006.173.10:47:42.18#ibcon#end of sib2, iclass 32, count 0 2006.173.10:47:42.18#ibcon#*mode == 0, iclass 32, count 0 2006.173.10:47:42.18#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.10:47:42.18#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.10:47:42.18#ibcon#*before write, iclass 32, count 0 2006.173.10:47:42.18#ibcon#enter sib2, iclass 32, count 0 2006.173.10:47:42.18#ibcon#flushed, iclass 32, count 0 2006.173.10:47:42.18#ibcon#about to write, iclass 32, count 0 2006.173.10:47:42.18#ibcon#wrote, iclass 32, count 0 2006.173.10:47:42.18#ibcon#about to read 3, iclass 32, count 0 2006.173.10:47:42.22#ibcon#read 3, iclass 32, count 0 2006.173.10:47:42.22#ibcon#about to read 4, iclass 32, count 0 2006.173.10:47:42.22#ibcon#read 4, iclass 32, count 0 2006.173.10:47:42.22#ibcon#about to read 5, iclass 32, count 0 2006.173.10:47:42.22#ibcon#read 5, iclass 32, count 0 2006.173.10:47:42.22#ibcon#about to read 6, iclass 32, count 0 2006.173.10:47:42.22#ibcon#read 6, iclass 32, count 0 2006.173.10:47:42.22#ibcon#end of sib2, iclass 32, count 0 2006.173.10:47:42.22#ibcon#*after write, iclass 32, count 0 2006.173.10:47:42.22#ibcon#*before return 0, iclass 32, count 0 2006.173.10:47:42.22#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.10:47:42.22#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.10:47:42.22#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.10:47:42.22#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.10:47:42.22$vck44/va=7,4 2006.173.10:47:42.22#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.10:47:42.22#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.10:47:42.22#ibcon#ireg 11 cls_cnt 2 2006.173.10:47:42.22#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.10:47:42.23#abcon#<5=/05 0.9 1.8 22.66 921003.9\r\n> 2006.173.10:47:42.25#abcon#{5=INTERFACE CLEAR} 2006.173.10:47:42.28#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.10:47:42.28#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.10:47:42.28#ibcon#enter wrdev, iclass 35, count 2 2006.173.10:47:42.28#ibcon#first serial, iclass 35, count 2 2006.173.10:47:42.28#ibcon#enter sib2, iclass 35, count 2 2006.173.10:47:42.28#ibcon#flushed, iclass 35, count 2 2006.173.10:47:42.28#ibcon#about to write, iclass 35, count 2 2006.173.10:47:42.28#ibcon#wrote, iclass 35, count 2 2006.173.10:47:42.28#ibcon#about to read 3, iclass 35, count 2 2006.173.10:47:42.30#ibcon#read 3, iclass 35, count 2 2006.173.10:47:42.30#ibcon#about to read 4, iclass 35, count 2 2006.173.10:47:42.30#ibcon#read 4, iclass 35, count 2 2006.173.10:47:42.30#ibcon#about to read 5, iclass 35, count 2 2006.173.10:47:42.30#ibcon#read 5, iclass 35, count 2 2006.173.10:47:42.30#ibcon#about to read 6, iclass 35, count 2 2006.173.10:47:42.30#ibcon#read 6, iclass 35, count 2 2006.173.10:47:42.30#ibcon#end of sib2, iclass 35, count 2 2006.173.10:47:42.30#ibcon#*mode == 0, iclass 35, count 2 2006.173.10:47:42.30#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.10:47:42.30#ibcon#[25=AT07-04\r\n] 2006.173.10:47:42.30#ibcon#*before write, iclass 35, count 2 2006.173.10:47:42.30#ibcon#enter sib2, iclass 35, count 2 2006.173.10:47:42.30#ibcon#flushed, iclass 35, count 2 2006.173.10:47:42.30#ibcon#about to write, iclass 35, count 2 2006.173.10:47:42.30#ibcon#wrote, iclass 35, count 2 2006.173.10:47:42.30#ibcon#about to read 3, iclass 35, count 2 2006.173.10:47:42.31#abcon#[5=S1D000X0/0*\r\n] 2006.173.10:47:42.33#ibcon#read 3, iclass 35, count 2 2006.173.10:47:42.33#ibcon#about to read 4, iclass 35, count 2 2006.173.10:47:42.33#ibcon#read 4, iclass 35, count 2 2006.173.10:47:42.33#ibcon#about to read 5, iclass 35, count 2 2006.173.10:47:42.33#ibcon#read 5, iclass 35, count 2 2006.173.10:47:42.33#ibcon#about to read 6, iclass 35, count 2 2006.173.10:47:42.33#ibcon#read 6, iclass 35, count 2 2006.173.10:47:42.33#ibcon#end of sib2, iclass 35, count 2 2006.173.10:47:42.33#ibcon#*after write, iclass 35, count 2 2006.173.10:47:42.33#ibcon#*before return 0, iclass 35, count 2 2006.173.10:47:42.33#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.10:47:42.33#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.10:47:42.33#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.10:47:42.33#ibcon#ireg 7 cls_cnt 0 2006.173.10:47:42.33#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.10:47:42.45#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.10:47:42.45#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.10:47:42.45#ibcon#enter wrdev, iclass 35, count 0 2006.173.10:47:42.45#ibcon#first serial, iclass 35, count 0 2006.173.10:47:42.45#ibcon#enter sib2, iclass 35, count 0 2006.173.10:47:42.45#ibcon#flushed, iclass 35, count 0 2006.173.10:47:42.45#ibcon#about to write, iclass 35, count 0 2006.173.10:47:42.45#ibcon#wrote, iclass 35, count 0 2006.173.10:47:42.45#ibcon#about to read 3, iclass 35, count 0 2006.173.10:47:42.47#ibcon#read 3, iclass 35, count 0 2006.173.10:47:42.47#ibcon#about to read 4, iclass 35, count 0 2006.173.10:47:42.47#ibcon#read 4, iclass 35, count 0 2006.173.10:47:42.47#ibcon#about to read 5, iclass 35, count 0 2006.173.10:47:42.47#ibcon#read 5, iclass 35, count 0 2006.173.10:47:42.47#ibcon#about to read 6, iclass 35, count 0 2006.173.10:47:42.47#ibcon#read 6, iclass 35, count 0 2006.173.10:47:42.47#ibcon#end of sib2, iclass 35, count 0 2006.173.10:47:42.47#ibcon#*mode == 0, iclass 35, count 0 2006.173.10:47:42.47#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.10:47:42.47#ibcon#[25=USB\r\n] 2006.173.10:47:42.47#ibcon#*before write, iclass 35, count 0 2006.173.10:47:42.47#ibcon#enter sib2, iclass 35, count 0 2006.173.10:47:42.47#ibcon#flushed, iclass 35, count 0 2006.173.10:47:42.47#ibcon#about to write, iclass 35, count 0 2006.173.10:47:42.47#ibcon#wrote, iclass 35, count 0 2006.173.10:47:42.47#ibcon#about to read 3, iclass 35, count 0 2006.173.10:47:42.50#ibcon#read 3, iclass 35, count 0 2006.173.10:47:42.50#ibcon#about to read 4, iclass 35, count 0 2006.173.10:47:42.50#ibcon#read 4, iclass 35, count 0 2006.173.10:47:42.50#ibcon#about to read 5, iclass 35, count 0 2006.173.10:47:42.50#ibcon#read 5, iclass 35, count 0 2006.173.10:47:42.50#ibcon#about to read 6, iclass 35, count 0 2006.173.10:47:42.50#ibcon#read 6, iclass 35, count 0 2006.173.10:47:42.50#ibcon#end of sib2, iclass 35, count 0 2006.173.10:47:42.50#ibcon#*after write, iclass 35, count 0 2006.173.10:47:42.50#ibcon#*before return 0, iclass 35, count 0 2006.173.10:47:42.50#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.10:47:42.50#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.10:47:42.50#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.10:47:42.50#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.10:47:42.50$vck44/valo=8,884.99 2006.173.10:47:42.50#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.10:47:42.50#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.10:47:42.50#ibcon#ireg 17 cls_cnt 0 2006.173.10:47:42.50#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.10:47:42.50#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.10:47:42.50#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.10:47:42.50#ibcon#enter wrdev, iclass 40, count 0 2006.173.10:47:42.50#ibcon#first serial, iclass 40, count 0 2006.173.10:47:42.50#ibcon#enter sib2, iclass 40, count 0 2006.173.10:47:42.50#ibcon#flushed, iclass 40, count 0 2006.173.10:47:42.50#ibcon#about to write, iclass 40, count 0 2006.173.10:47:42.50#ibcon#wrote, iclass 40, count 0 2006.173.10:47:42.50#ibcon#about to read 3, iclass 40, count 0 2006.173.10:47:42.52#ibcon#read 3, iclass 40, count 0 2006.173.10:47:42.52#ibcon#about to read 4, iclass 40, count 0 2006.173.10:47:42.52#ibcon#read 4, iclass 40, count 0 2006.173.10:47:42.52#ibcon#about to read 5, iclass 40, count 0 2006.173.10:47:42.52#ibcon#read 5, iclass 40, count 0 2006.173.10:47:42.52#ibcon#about to read 6, iclass 40, count 0 2006.173.10:47:42.52#ibcon#read 6, iclass 40, count 0 2006.173.10:47:42.52#ibcon#end of sib2, iclass 40, count 0 2006.173.10:47:42.52#ibcon#*mode == 0, iclass 40, count 0 2006.173.10:47:42.52#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.10:47:42.52#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.10:47:42.52#ibcon#*before write, iclass 40, count 0 2006.173.10:47:42.52#ibcon#enter sib2, iclass 40, count 0 2006.173.10:47:42.52#ibcon#flushed, iclass 40, count 0 2006.173.10:47:42.52#ibcon#about to write, iclass 40, count 0 2006.173.10:47:42.52#ibcon#wrote, iclass 40, count 0 2006.173.10:47:42.52#ibcon#about to read 3, iclass 40, count 0 2006.173.10:47:42.56#ibcon#read 3, iclass 40, count 0 2006.173.10:47:42.56#ibcon#about to read 4, iclass 40, count 0 2006.173.10:47:42.56#ibcon#read 4, iclass 40, count 0 2006.173.10:47:42.56#ibcon#about to read 5, iclass 40, count 0 2006.173.10:47:42.56#ibcon#read 5, iclass 40, count 0 2006.173.10:47:42.56#ibcon#about to read 6, iclass 40, count 0 2006.173.10:47:42.56#ibcon#read 6, iclass 40, count 0 2006.173.10:47:42.56#ibcon#end of sib2, iclass 40, count 0 2006.173.10:47:42.56#ibcon#*after write, iclass 40, count 0 2006.173.10:47:42.56#ibcon#*before return 0, iclass 40, count 0 2006.173.10:47:42.56#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.10:47:42.56#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.10:47:42.56#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.10:47:42.56#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.10:47:42.56$vck44/va=8,4 2006.173.10:47:42.56#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.10:47:42.56#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.10:47:42.56#ibcon#ireg 11 cls_cnt 2 2006.173.10:47:42.56#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.10:47:42.62#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.10:47:42.62#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.10:47:42.62#ibcon#enter wrdev, iclass 4, count 2 2006.173.10:47:42.62#ibcon#first serial, iclass 4, count 2 2006.173.10:47:42.62#ibcon#enter sib2, iclass 4, count 2 2006.173.10:47:42.62#ibcon#flushed, iclass 4, count 2 2006.173.10:47:42.62#ibcon#about to write, iclass 4, count 2 2006.173.10:47:42.62#ibcon#wrote, iclass 4, count 2 2006.173.10:47:42.62#ibcon#about to read 3, iclass 4, count 2 2006.173.10:47:42.64#ibcon#read 3, iclass 4, count 2 2006.173.10:47:42.64#ibcon#about to read 4, iclass 4, count 2 2006.173.10:47:42.64#ibcon#read 4, iclass 4, count 2 2006.173.10:47:42.64#ibcon#about to read 5, iclass 4, count 2 2006.173.10:47:42.64#ibcon#read 5, iclass 4, count 2 2006.173.10:47:42.64#ibcon#about to read 6, iclass 4, count 2 2006.173.10:47:42.64#ibcon#read 6, iclass 4, count 2 2006.173.10:47:42.64#ibcon#end of sib2, iclass 4, count 2 2006.173.10:47:42.64#ibcon#*mode == 0, iclass 4, count 2 2006.173.10:47:42.64#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.10:47:42.64#ibcon#[25=AT08-04\r\n] 2006.173.10:47:42.64#ibcon#*before write, iclass 4, count 2 2006.173.10:47:42.64#ibcon#enter sib2, iclass 4, count 2 2006.173.10:47:42.64#ibcon#flushed, iclass 4, count 2 2006.173.10:47:42.64#ibcon#about to write, iclass 4, count 2 2006.173.10:47:42.64#ibcon#wrote, iclass 4, count 2 2006.173.10:47:42.64#ibcon#about to read 3, iclass 4, count 2 2006.173.10:47:42.67#ibcon#read 3, iclass 4, count 2 2006.173.10:47:42.67#ibcon#about to read 4, iclass 4, count 2 2006.173.10:47:42.67#ibcon#read 4, iclass 4, count 2 2006.173.10:47:42.67#ibcon#about to read 5, iclass 4, count 2 2006.173.10:47:42.67#ibcon#read 5, iclass 4, count 2 2006.173.10:47:42.67#ibcon#about to read 6, iclass 4, count 2 2006.173.10:47:42.67#ibcon#read 6, iclass 4, count 2 2006.173.10:47:42.67#ibcon#end of sib2, iclass 4, count 2 2006.173.10:47:42.67#ibcon#*after write, iclass 4, count 2 2006.173.10:47:42.67#ibcon#*before return 0, iclass 4, count 2 2006.173.10:47:42.67#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.10:47:42.67#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.10:47:42.67#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.10:47:42.67#ibcon#ireg 7 cls_cnt 0 2006.173.10:47:42.67#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.10:47:42.79#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.10:47:42.79#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.10:47:42.79#ibcon#enter wrdev, iclass 4, count 0 2006.173.10:47:42.79#ibcon#first serial, iclass 4, count 0 2006.173.10:47:42.79#ibcon#enter sib2, iclass 4, count 0 2006.173.10:47:42.79#ibcon#flushed, iclass 4, count 0 2006.173.10:47:42.79#ibcon#about to write, iclass 4, count 0 2006.173.10:47:42.79#ibcon#wrote, iclass 4, count 0 2006.173.10:47:42.79#ibcon#about to read 3, iclass 4, count 0 2006.173.10:47:42.81#ibcon#read 3, iclass 4, count 0 2006.173.10:47:42.81#ibcon#about to read 4, iclass 4, count 0 2006.173.10:47:42.81#ibcon#read 4, iclass 4, count 0 2006.173.10:47:42.81#ibcon#about to read 5, iclass 4, count 0 2006.173.10:47:42.81#ibcon#read 5, iclass 4, count 0 2006.173.10:47:42.81#ibcon#about to read 6, iclass 4, count 0 2006.173.10:47:42.81#ibcon#read 6, iclass 4, count 0 2006.173.10:47:42.81#ibcon#end of sib2, iclass 4, count 0 2006.173.10:47:42.81#ibcon#*mode == 0, iclass 4, count 0 2006.173.10:47:42.81#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.10:47:42.81#ibcon#[25=USB\r\n] 2006.173.10:47:42.81#ibcon#*before write, iclass 4, count 0 2006.173.10:47:42.81#ibcon#enter sib2, iclass 4, count 0 2006.173.10:47:42.81#ibcon#flushed, iclass 4, count 0 2006.173.10:47:42.81#ibcon#about to write, iclass 4, count 0 2006.173.10:47:42.81#ibcon#wrote, iclass 4, count 0 2006.173.10:47:42.81#ibcon#about to read 3, iclass 4, count 0 2006.173.10:47:42.84#ibcon#read 3, iclass 4, count 0 2006.173.10:47:42.84#ibcon#about to read 4, iclass 4, count 0 2006.173.10:47:42.84#ibcon#read 4, iclass 4, count 0 2006.173.10:47:42.84#ibcon#about to read 5, iclass 4, count 0 2006.173.10:47:42.84#ibcon#read 5, iclass 4, count 0 2006.173.10:47:42.84#ibcon#about to read 6, iclass 4, count 0 2006.173.10:47:42.84#ibcon#read 6, iclass 4, count 0 2006.173.10:47:42.84#ibcon#end of sib2, iclass 4, count 0 2006.173.10:47:42.84#ibcon#*after write, iclass 4, count 0 2006.173.10:47:42.84#ibcon#*before return 0, iclass 4, count 0 2006.173.10:47:42.84#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.10:47:42.84#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.10:47:42.84#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.10:47:42.84#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.10:47:42.84$vck44/vblo=1,629.99 2006.173.10:47:42.84#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.10:47:42.84#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.10:47:42.84#ibcon#ireg 17 cls_cnt 0 2006.173.10:47:42.84#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.10:47:42.84#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.10:47:42.84#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.10:47:42.84#ibcon#enter wrdev, iclass 6, count 0 2006.173.10:47:42.84#ibcon#first serial, iclass 6, count 0 2006.173.10:47:42.84#ibcon#enter sib2, iclass 6, count 0 2006.173.10:47:42.84#ibcon#flushed, iclass 6, count 0 2006.173.10:47:42.84#ibcon#about to write, iclass 6, count 0 2006.173.10:47:42.84#ibcon#wrote, iclass 6, count 0 2006.173.10:47:42.84#ibcon#about to read 3, iclass 6, count 0 2006.173.10:47:42.86#ibcon#read 3, iclass 6, count 0 2006.173.10:47:42.86#ibcon#about to read 4, iclass 6, count 0 2006.173.10:47:42.86#ibcon#read 4, iclass 6, count 0 2006.173.10:47:42.86#ibcon#about to read 5, iclass 6, count 0 2006.173.10:47:42.86#ibcon#read 5, iclass 6, count 0 2006.173.10:47:42.86#ibcon#about to read 6, iclass 6, count 0 2006.173.10:47:42.86#ibcon#read 6, iclass 6, count 0 2006.173.10:47:42.86#ibcon#end of sib2, iclass 6, count 0 2006.173.10:47:42.86#ibcon#*mode == 0, iclass 6, count 0 2006.173.10:47:42.86#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.10:47:42.86#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.10:47:42.86#ibcon#*before write, iclass 6, count 0 2006.173.10:47:42.86#ibcon#enter sib2, iclass 6, count 0 2006.173.10:47:42.86#ibcon#flushed, iclass 6, count 0 2006.173.10:47:42.86#ibcon#about to write, iclass 6, count 0 2006.173.10:47:42.86#ibcon#wrote, iclass 6, count 0 2006.173.10:47:42.86#ibcon#about to read 3, iclass 6, count 0 2006.173.10:47:42.90#ibcon#read 3, iclass 6, count 0 2006.173.10:47:42.90#ibcon#about to read 4, iclass 6, count 0 2006.173.10:47:42.90#ibcon#read 4, iclass 6, count 0 2006.173.10:47:42.90#ibcon#about to read 5, iclass 6, count 0 2006.173.10:47:42.90#ibcon#read 5, iclass 6, count 0 2006.173.10:47:42.90#ibcon#about to read 6, iclass 6, count 0 2006.173.10:47:42.90#ibcon#read 6, iclass 6, count 0 2006.173.10:47:42.90#ibcon#end of sib2, iclass 6, count 0 2006.173.10:47:42.90#ibcon#*after write, iclass 6, count 0 2006.173.10:47:42.90#ibcon#*before return 0, iclass 6, count 0 2006.173.10:47:42.90#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.10:47:42.90#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.10:47:42.90#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.10:47:42.90#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.10:47:42.90$vck44/vb=1,4 2006.173.10:47:42.90#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.10:47:42.90#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.10:47:42.90#ibcon#ireg 11 cls_cnt 2 2006.173.10:47:42.90#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.10:47:42.90#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.10:47:42.90#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.10:47:42.90#ibcon#enter wrdev, iclass 10, count 2 2006.173.10:47:42.90#ibcon#first serial, iclass 10, count 2 2006.173.10:47:42.90#ibcon#enter sib2, iclass 10, count 2 2006.173.10:47:42.90#ibcon#flushed, iclass 10, count 2 2006.173.10:47:42.90#ibcon#about to write, iclass 10, count 2 2006.173.10:47:42.90#ibcon#wrote, iclass 10, count 2 2006.173.10:47:42.90#ibcon#about to read 3, iclass 10, count 2 2006.173.10:47:42.92#ibcon#read 3, iclass 10, count 2 2006.173.10:47:42.92#ibcon#about to read 4, iclass 10, count 2 2006.173.10:47:42.92#ibcon#read 4, iclass 10, count 2 2006.173.10:47:42.92#ibcon#about to read 5, iclass 10, count 2 2006.173.10:47:42.92#ibcon#read 5, iclass 10, count 2 2006.173.10:47:42.92#ibcon#about to read 6, iclass 10, count 2 2006.173.10:47:42.92#ibcon#read 6, iclass 10, count 2 2006.173.10:47:42.92#ibcon#end of sib2, iclass 10, count 2 2006.173.10:47:42.92#ibcon#*mode == 0, iclass 10, count 2 2006.173.10:47:42.92#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.10:47:42.92#ibcon#[27=AT01-04\r\n] 2006.173.10:47:42.92#ibcon#*before write, iclass 10, count 2 2006.173.10:47:42.92#ibcon#enter sib2, iclass 10, count 2 2006.173.10:47:42.92#ibcon#flushed, iclass 10, count 2 2006.173.10:47:42.92#ibcon#about to write, iclass 10, count 2 2006.173.10:47:42.92#ibcon#wrote, iclass 10, count 2 2006.173.10:47:42.92#ibcon#about to read 3, iclass 10, count 2 2006.173.10:47:42.95#ibcon#read 3, iclass 10, count 2 2006.173.10:47:42.95#ibcon#about to read 4, iclass 10, count 2 2006.173.10:47:42.95#ibcon#read 4, iclass 10, count 2 2006.173.10:47:42.95#ibcon#about to read 5, iclass 10, count 2 2006.173.10:47:42.95#ibcon#read 5, iclass 10, count 2 2006.173.10:47:42.95#ibcon#about to read 6, iclass 10, count 2 2006.173.10:47:42.95#ibcon#read 6, iclass 10, count 2 2006.173.10:47:42.95#ibcon#end of sib2, iclass 10, count 2 2006.173.10:47:42.95#ibcon#*after write, iclass 10, count 2 2006.173.10:47:42.95#ibcon#*before return 0, iclass 10, count 2 2006.173.10:47:42.95#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.10:47:42.95#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.10:47:42.95#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.10:47:42.95#ibcon#ireg 7 cls_cnt 0 2006.173.10:47:42.95#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.10:47:43.07#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.10:47:43.07#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.10:47:43.07#ibcon#enter wrdev, iclass 10, count 0 2006.173.10:47:43.07#ibcon#first serial, iclass 10, count 0 2006.173.10:47:43.07#ibcon#enter sib2, iclass 10, count 0 2006.173.10:47:43.07#ibcon#flushed, iclass 10, count 0 2006.173.10:47:43.07#ibcon#about to write, iclass 10, count 0 2006.173.10:47:43.07#ibcon#wrote, iclass 10, count 0 2006.173.10:47:43.07#ibcon#about to read 3, iclass 10, count 0 2006.173.10:47:43.09#ibcon#read 3, iclass 10, count 0 2006.173.10:47:43.09#ibcon#about to read 4, iclass 10, count 0 2006.173.10:47:43.09#ibcon#read 4, iclass 10, count 0 2006.173.10:47:43.09#ibcon#about to read 5, iclass 10, count 0 2006.173.10:47:43.09#ibcon#read 5, iclass 10, count 0 2006.173.10:47:43.09#ibcon#about to read 6, iclass 10, count 0 2006.173.10:47:43.09#ibcon#read 6, iclass 10, count 0 2006.173.10:47:43.09#ibcon#end of sib2, iclass 10, count 0 2006.173.10:47:43.09#ibcon#*mode == 0, iclass 10, count 0 2006.173.10:47:43.09#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.10:47:43.09#ibcon#[27=USB\r\n] 2006.173.10:47:43.09#ibcon#*before write, iclass 10, count 0 2006.173.10:47:43.09#ibcon#enter sib2, iclass 10, count 0 2006.173.10:47:43.09#ibcon#flushed, iclass 10, count 0 2006.173.10:47:43.09#ibcon#about to write, iclass 10, count 0 2006.173.10:47:43.09#ibcon#wrote, iclass 10, count 0 2006.173.10:47:43.09#ibcon#about to read 3, iclass 10, count 0 2006.173.10:47:43.12#ibcon#read 3, iclass 10, count 0 2006.173.10:47:43.12#ibcon#about to read 4, iclass 10, count 0 2006.173.10:47:43.12#ibcon#read 4, iclass 10, count 0 2006.173.10:47:43.12#ibcon#about to read 5, iclass 10, count 0 2006.173.10:47:43.12#ibcon#read 5, iclass 10, count 0 2006.173.10:47:43.12#ibcon#about to read 6, iclass 10, count 0 2006.173.10:47:43.12#ibcon#read 6, iclass 10, count 0 2006.173.10:47:43.12#ibcon#end of sib2, iclass 10, count 0 2006.173.10:47:43.12#ibcon#*after write, iclass 10, count 0 2006.173.10:47:43.12#ibcon#*before return 0, iclass 10, count 0 2006.173.10:47:43.12#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.10:47:43.12#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.10:47:43.12#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.10:47:43.12#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.10:47:43.12$vck44/vblo=2,634.99 2006.173.10:47:43.12#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.10:47:43.12#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.10:47:43.12#ibcon#ireg 17 cls_cnt 0 2006.173.10:47:43.12#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.10:47:43.12#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.10:47:43.12#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.10:47:43.12#ibcon#enter wrdev, iclass 12, count 0 2006.173.10:47:43.12#ibcon#first serial, iclass 12, count 0 2006.173.10:47:43.12#ibcon#enter sib2, iclass 12, count 0 2006.173.10:47:43.12#ibcon#flushed, iclass 12, count 0 2006.173.10:47:43.12#ibcon#about to write, iclass 12, count 0 2006.173.10:47:43.12#ibcon#wrote, iclass 12, count 0 2006.173.10:47:43.12#ibcon#about to read 3, iclass 12, count 0 2006.173.10:47:43.14#ibcon#read 3, iclass 12, count 0 2006.173.10:47:43.14#ibcon#about to read 4, iclass 12, count 0 2006.173.10:47:43.14#ibcon#read 4, iclass 12, count 0 2006.173.10:47:43.14#ibcon#about to read 5, iclass 12, count 0 2006.173.10:47:43.14#ibcon#read 5, iclass 12, count 0 2006.173.10:47:43.14#ibcon#about to read 6, iclass 12, count 0 2006.173.10:47:43.14#ibcon#read 6, iclass 12, count 0 2006.173.10:47:43.14#ibcon#end of sib2, iclass 12, count 0 2006.173.10:47:43.14#ibcon#*mode == 0, iclass 12, count 0 2006.173.10:47:43.14#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.10:47:43.14#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.10:47:43.14#ibcon#*before write, iclass 12, count 0 2006.173.10:47:43.14#ibcon#enter sib2, iclass 12, count 0 2006.173.10:47:43.14#ibcon#flushed, iclass 12, count 0 2006.173.10:47:43.14#ibcon#about to write, iclass 12, count 0 2006.173.10:47:43.14#ibcon#wrote, iclass 12, count 0 2006.173.10:47:43.14#ibcon#about to read 3, iclass 12, count 0 2006.173.10:47:43.18#ibcon#read 3, iclass 12, count 0 2006.173.10:47:43.18#ibcon#about to read 4, iclass 12, count 0 2006.173.10:47:43.18#ibcon#read 4, iclass 12, count 0 2006.173.10:47:43.18#ibcon#about to read 5, iclass 12, count 0 2006.173.10:47:43.18#ibcon#read 5, iclass 12, count 0 2006.173.10:47:43.18#ibcon#about to read 6, iclass 12, count 0 2006.173.10:47:43.18#ibcon#read 6, iclass 12, count 0 2006.173.10:47:43.18#ibcon#end of sib2, iclass 12, count 0 2006.173.10:47:43.18#ibcon#*after write, iclass 12, count 0 2006.173.10:47:43.18#ibcon#*before return 0, iclass 12, count 0 2006.173.10:47:43.18#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.10:47:43.18#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.10:47:43.18#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.10:47:43.18#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.10:47:43.18$vck44/vb=2,4 2006.173.10:47:43.18#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.10:47:43.18#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.10:47:43.18#ibcon#ireg 11 cls_cnt 2 2006.173.10:47:43.18#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.10:47:43.24#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.10:47:43.24#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.10:47:43.24#ibcon#enter wrdev, iclass 14, count 2 2006.173.10:47:43.24#ibcon#first serial, iclass 14, count 2 2006.173.10:47:43.24#ibcon#enter sib2, iclass 14, count 2 2006.173.10:47:43.24#ibcon#flushed, iclass 14, count 2 2006.173.10:47:43.24#ibcon#about to write, iclass 14, count 2 2006.173.10:47:43.24#ibcon#wrote, iclass 14, count 2 2006.173.10:47:43.24#ibcon#about to read 3, iclass 14, count 2 2006.173.10:47:43.26#ibcon#read 3, iclass 14, count 2 2006.173.10:47:43.26#ibcon#about to read 4, iclass 14, count 2 2006.173.10:47:43.26#ibcon#read 4, iclass 14, count 2 2006.173.10:47:43.26#ibcon#about to read 5, iclass 14, count 2 2006.173.10:47:43.26#ibcon#read 5, iclass 14, count 2 2006.173.10:47:43.26#ibcon#about to read 6, iclass 14, count 2 2006.173.10:47:43.26#ibcon#read 6, iclass 14, count 2 2006.173.10:47:43.26#ibcon#end of sib2, iclass 14, count 2 2006.173.10:47:43.26#ibcon#*mode == 0, iclass 14, count 2 2006.173.10:47:43.26#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.10:47:43.26#ibcon#[27=AT02-04\r\n] 2006.173.10:47:43.26#ibcon#*before write, iclass 14, count 2 2006.173.10:47:43.26#ibcon#enter sib2, iclass 14, count 2 2006.173.10:47:43.26#ibcon#flushed, iclass 14, count 2 2006.173.10:47:43.26#ibcon#about to write, iclass 14, count 2 2006.173.10:47:43.26#ibcon#wrote, iclass 14, count 2 2006.173.10:47:43.26#ibcon#about to read 3, iclass 14, count 2 2006.173.10:47:43.29#ibcon#read 3, iclass 14, count 2 2006.173.10:47:43.29#ibcon#about to read 4, iclass 14, count 2 2006.173.10:47:43.29#ibcon#read 4, iclass 14, count 2 2006.173.10:47:43.29#ibcon#about to read 5, iclass 14, count 2 2006.173.10:47:43.29#ibcon#read 5, iclass 14, count 2 2006.173.10:47:43.29#ibcon#about to read 6, iclass 14, count 2 2006.173.10:47:43.29#ibcon#read 6, iclass 14, count 2 2006.173.10:47:43.29#ibcon#end of sib2, iclass 14, count 2 2006.173.10:47:43.29#ibcon#*after write, iclass 14, count 2 2006.173.10:47:43.29#ibcon#*before return 0, iclass 14, count 2 2006.173.10:47:43.29#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.10:47:43.29#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.10:47:43.29#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.10:47:43.29#ibcon#ireg 7 cls_cnt 0 2006.173.10:47:43.29#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.10:47:43.41#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.10:47:43.41#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.10:47:43.41#ibcon#enter wrdev, iclass 14, count 0 2006.173.10:47:43.41#ibcon#first serial, iclass 14, count 0 2006.173.10:47:43.41#ibcon#enter sib2, iclass 14, count 0 2006.173.10:47:43.41#ibcon#flushed, iclass 14, count 0 2006.173.10:47:43.41#ibcon#about to write, iclass 14, count 0 2006.173.10:47:43.41#ibcon#wrote, iclass 14, count 0 2006.173.10:47:43.41#ibcon#about to read 3, iclass 14, count 0 2006.173.10:47:43.43#ibcon#read 3, iclass 14, count 0 2006.173.10:47:43.43#ibcon#about to read 4, iclass 14, count 0 2006.173.10:47:43.43#ibcon#read 4, iclass 14, count 0 2006.173.10:47:43.43#ibcon#about to read 5, iclass 14, count 0 2006.173.10:47:43.43#ibcon#read 5, iclass 14, count 0 2006.173.10:47:43.43#ibcon#about to read 6, iclass 14, count 0 2006.173.10:47:43.43#ibcon#read 6, iclass 14, count 0 2006.173.10:47:43.43#ibcon#end of sib2, iclass 14, count 0 2006.173.10:47:43.43#ibcon#*mode == 0, iclass 14, count 0 2006.173.10:47:43.43#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.10:47:43.43#ibcon#[27=USB\r\n] 2006.173.10:47:43.43#ibcon#*before write, iclass 14, count 0 2006.173.10:47:43.43#ibcon#enter sib2, iclass 14, count 0 2006.173.10:47:43.43#ibcon#flushed, iclass 14, count 0 2006.173.10:47:43.43#ibcon#about to write, iclass 14, count 0 2006.173.10:47:43.43#ibcon#wrote, iclass 14, count 0 2006.173.10:47:43.43#ibcon#about to read 3, iclass 14, count 0 2006.173.10:47:43.46#ibcon#read 3, iclass 14, count 0 2006.173.10:47:43.46#ibcon#about to read 4, iclass 14, count 0 2006.173.10:47:43.46#ibcon#read 4, iclass 14, count 0 2006.173.10:47:43.46#ibcon#about to read 5, iclass 14, count 0 2006.173.10:47:43.46#ibcon#read 5, iclass 14, count 0 2006.173.10:47:43.46#ibcon#about to read 6, iclass 14, count 0 2006.173.10:47:43.46#ibcon#read 6, iclass 14, count 0 2006.173.10:47:43.46#ibcon#end of sib2, iclass 14, count 0 2006.173.10:47:43.46#ibcon#*after write, iclass 14, count 0 2006.173.10:47:43.46#ibcon#*before return 0, iclass 14, count 0 2006.173.10:47:43.46#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.10:47:43.46#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.10:47:43.46#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.10:47:43.46#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.10:47:43.46$vck44/vblo=3,649.99 2006.173.10:47:43.46#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.10:47:43.46#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.10:47:43.46#ibcon#ireg 17 cls_cnt 0 2006.173.10:47:43.46#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.10:47:43.46#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.10:47:43.46#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.10:47:43.46#ibcon#enter wrdev, iclass 16, count 0 2006.173.10:47:43.46#ibcon#first serial, iclass 16, count 0 2006.173.10:47:43.46#ibcon#enter sib2, iclass 16, count 0 2006.173.10:47:43.46#ibcon#flushed, iclass 16, count 0 2006.173.10:47:43.46#ibcon#about to write, iclass 16, count 0 2006.173.10:47:43.46#ibcon#wrote, iclass 16, count 0 2006.173.10:47:43.46#ibcon#about to read 3, iclass 16, count 0 2006.173.10:47:43.48#ibcon#read 3, iclass 16, count 0 2006.173.10:47:43.48#ibcon#about to read 4, iclass 16, count 0 2006.173.10:47:43.48#ibcon#read 4, iclass 16, count 0 2006.173.10:47:43.48#ibcon#about to read 5, iclass 16, count 0 2006.173.10:47:43.48#ibcon#read 5, iclass 16, count 0 2006.173.10:47:43.48#ibcon#about to read 6, iclass 16, count 0 2006.173.10:47:43.48#ibcon#read 6, iclass 16, count 0 2006.173.10:47:43.48#ibcon#end of sib2, iclass 16, count 0 2006.173.10:47:43.48#ibcon#*mode == 0, iclass 16, count 0 2006.173.10:47:43.48#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.10:47:43.48#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.10:47:43.48#ibcon#*before write, iclass 16, count 0 2006.173.10:47:43.48#ibcon#enter sib2, iclass 16, count 0 2006.173.10:47:43.48#ibcon#flushed, iclass 16, count 0 2006.173.10:47:43.48#ibcon#about to write, iclass 16, count 0 2006.173.10:47:43.48#ibcon#wrote, iclass 16, count 0 2006.173.10:47:43.48#ibcon#about to read 3, iclass 16, count 0 2006.173.10:47:43.52#ibcon#read 3, iclass 16, count 0 2006.173.10:47:43.52#ibcon#about to read 4, iclass 16, count 0 2006.173.10:47:43.52#ibcon#read 4, iclass 16, count 0 2006.173.10:47:43.52#ibcon#about to read 5, iclass 16, count 0 2006.173.10:47:43.52#ibcon#read 5, iclass 16, count 0 2006.173.10:47:43.52#ibcon#about to read 6, iclass 16, count 0 2006.173.10:47:43.52#ibcon#read 6, iclass 16, count 0 2006.173.10:47:43.52#ibcon#end of sib2, iclass 16, count 0 2006.173.10:47:43.52#ibcon#*after write, iclass 16, count 0 2006.173.10:47:43.52#ibcon#*before return 0, iclass 16, count 0 2006.173.10:47:43.52#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.10:47:43.52#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.10:47:43.52#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.10:47:43.52#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.10:47:43.52$vck44/vb=3,4 2006.173.10:47:43.52#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.10:47:43.52#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.10:47:43.52#ibcon#ireg 11 cls_cnt 2 2006.173.10:47:43.52#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.10:47:43.58#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.10:47:43.58#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.10:47:43.58#ibcon#enter wrdev, iclass 18, count 2 2006.173.10:47:43.58#ibcon#first serial, iclass 18, count 2 2006.173.10:47:43.58#ibcon#enter sib2, iclass 18, count 2 2006.173.10:47:43.58#ibcon#flushed, iclass 18, count 2 2006.173.10:47:43.58#ibcon#about to write, iclass 18, count 2 2006.173.10:47:43.58#ibcon#wrote, iclass 18, count 2 2006.173.10:47:43.58#ibcon#about to read 3, iclass 18, count 2 2006.173.10:47:43.60#ibcon#read 3, iclass 18, count 2 2006.173.10:47:43.60#ibcon#about to read 4, iclass 18, count 2 2006.173.10:47:43.60#ibcon#read 4, iclass 18, count 2 2006.173.10:47:43.60#ibcon#about to read 5, iclass 18, count 2 2006.173.10:47:43.60#ibcon#read 5, iclass 18, count 2 2006.173.10:47:43.60#ibcon#about to read 6, iclass 18, count 2 2006.173.10:47:43.60#ibcon#read 6, iclass 18, count 2 2006.173.10:47:43.60#ibcon#end of sib2, iclass 18, count 2 2006.173.10:47:43.60#ibcon#*mode == 0, iclass 18, count 2 2006.173.10:47:43.60#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.10:47:43.60#ibcon#[27=AT03-04\r\n] 2006.173.10:47:43.60#ibcon#*before write, iclass 18, count 2 2006.173.10:47:43.60#ibcon#enter sib2, iclass 18, count 2 2006.173.10:47:43.60#ibcon#flushed, iclass 18, count 2 2006.173.10:47:43.60#ibcon#about to write, iclass 18, count 2 2006.173.10:47:43.60#ibcon#wrote, iclass 18, count 2 2006.173.10:47:43.60#ibcon#about to read 3, iclass 18, count 2 2006.173.10:47:43.63#ibcon#read 3, iclass 18, count 2 2006.173.10:47:43.63#ibcon#about to read 4, iclass 18, count 2 2006.173.10:47:43.63#ibcon#read 4, iclass 18, count 2 2006.173.10:47:43.63#ibcon#about to read 5, iclass 18, count 2 2006.173.10:47:43.63#ibcon#read 5, iclass 18, count 2 2006.173.10:47:43.63#ibcon#about to read 6, iclass 18, count 2 2006.173.10:47:43.63#ibcon#read 6, iclass 18, count 2 2006.173.10:47:43.63#ibcon#end of sib2, iclass 18, count 2 2006.173.10:47:43.63#ibcon#*after write, iclass 18, count 2 2006.173.10:47:43.63#ibcon#*before return 0, iclass 18, count 2 2006.173.10:47:43.63#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.10:47:43.63#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.10:47:43.63#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.10:47:43.63#ibcon#ireg 7 cls_cnt 0 2006.173.10:47:43.63#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.10:47:43.75#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.10:47:43.75#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.10:47:43.75#ibcon#enter wrdev, iclass 18, count 0 2006.173.10:47:43.75#ibcon#first serial, iclass 18, count 0 2006.173.10:47:43.75#ibcon#enter sib2, iclass 18, count 0 2006.173.10:47:43.75#ibcon#flushed, iclass 18, count 0 2006.173.10:47:43.75#ibcon#about to write, iclass 18, count 0 2006.173.10:47:43.75#ibcon#wrote, iclass 18, count 0 2006.173.10:47:43.75#ibcon#about to read 3, iclass 18, count 0 2006.173.10:47:43.77#ibcon#read 3, iclass 18, count 0 2006.173.10:47:43.77#ibcon#about to read 4, iclass 18, count 0 2006.173.10:47:43.77#ibcon#read 4, iclass 18, count 0 2006.173.10:47:43.77#ibcon#about to read 5, iclass 18, count 0 2006.173.10:47:43.77#ibcon#read 5, iclass 18, count 0 2006.173.10:47:43.77#ibcon#about to read 6, iclass 18, count 0 2006.173.10:47:43.77#ibcon#read 6, iclass 18, count 0 2006.173.10:47:43.77#ibcon#end of sib2, iclass 18, count 0 2006.173.10:47:43.77#ibcon#*mode == 0, iclass 18, count 0 2006.173.10:47:43.77#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.10:47:43.77#ibcon#[27=USB\r\n] 2006.173.10:47:43.77#ibcon#*before write, iclass 18, count 0 2006.173.10:47:43.77#ibcon#enter sib2, iclass 18, count 0 2006.173.10:47:43.77#ibcon#flushed, iclass 18, count 0 2006.173.10:47:43.77#ibcon#about to write, iclass 18, count 0 2006.173.10:47:43.77#ibcon#wrote, iclass 18, count 0 2006.173.10:47:43.77#ibcon#about to read 3, iclass 18, count 0 2006.173.10:47:43.80#ibcon#read 3, iclass 18, count 0 2006.173.10:47:43.80#ibcon#about to read 4, iclass 18, count 0 2006.173.10:47:43.80#ibcon#read 4, iclass 18, count 0 2006.173.10:47:43.80#ibcon#about to read 5, iclass 18, count 0 2006.173.10:47:43.80#ibcon#read 5, iclass 18, count 0 2006.173.10:47:43.80#ibcon#about to read 6, iclass 18, count 0 2006.173.10:47:43.80#ibcon#read 6, iclass 18, count 0 2006.173.10:47:43.80#ibcon#end of sib2, iclass 18, count 0 2006.173.10:47:43.80#ibcon#*after write, iclass 18, count 0 2006.173.10:47:43.80#ibcon#*before return 0, iclass 18, count 0 2006.173.10:47:43.80#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.10:47:43.80#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.10:47:43.80#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.10:47:43.80#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.10:47:43.80$vck44/vblo=4,679.99 2006.173.10:47:43.80#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.10:47:43.80#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.10:47:43.80#ibcon#ireg 17 cls_cnt 0 2006.173.10:47:43.80#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.10:47:43.80#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.10:47:43.80#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.10:47:43.80#ibcon#enter wrdev, iclass 20, count 0 2006.173.10:47:43.80#ibcon#first serial, iclass 20, count 0 2006.173.10:47:43.80#ibcon#enter sib2, iclass 20, count 0 2006.173.10:47:43.80#ibcon#flushed, iclass 20, count 0 2006.173.10:47:43.80#ibcon#about to write, iclass 20, count 0 2006.173.10:47:43.80#ibcon#wrote, iclass 20, count 0 2006.173.10:47:43.80#ibcon#about to read 3, iclass 20, count 0 2006.173.10:47:43.82#ibcon#read 3, iclass 20, count 0 2006.173.10:47:43.82#ibcon#about to read 4, iclass 20, count 0 2006.173.10:47:43.82#ibcon#read 4, iclass 20, count 0 2006.173.10:47:43.82#ibcon#about to read 5, iclass 20, count 0 2006.173.10:47:43.82#ibcon#read 5, iclass 20, count 0 2006.173.10:47:43.82#ibcon#about to read 6, iclass 20, count 0 2006.173.10:47:43.82#ibcon#read 6, iclass 20, count 0 2006.173.10:47:43.82#ibcon#end of sib2, iclass 20, count 0 2006.173.10:47:43.82#ibcon#*mode == 0, iclass 20, count 0 2006.173.10:47:43.82#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.10:47:43.82#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.10:47:43.82#ibcon#*before write, iclass 20, count 0 2006.173.10:47:43.82#ibcon#enter sib2, iclass 20, count 0 2006.173.10:47:43.82#ibcon#flushed, iclass 20, count 0 2006.173.10:47:43.82#ibcon#about to write, iclass 20, count 0 2006.173.10:47:43.82#ibcon#wrote, iclass 20, count 0 2006.173.10:47:43.82#ibcon#about to read 3, iclass 20, count 0 2006.173.10:47:43.86#ibcon#read 3, iclass 20, count 0 2006.173.10:47:43.86#ibcon#about to read 4, iclass 20, count 0 2006.173.10:47:43.86#ibcon#read 4, iclass 20, count 0 2006.173.10:47:43.86#ibcon#about to read 5, iclass 20, count 0 2006.173.10:47:43.86#ibcon#read 5, iclass 20, count 0 2006.173.10:47:43.86#ibcon#about to read 6, iclass 20, count 0 2006.173.10:47:43.86#ibcon#read 6, iclass 20, count 0 2006.173.10:47:43.86#ibcon#end of sib2, iclass 20, count 0 2006.173.10:47:43.86#ibcon#*after write, iclass 20, count 0 2006.173.10:47:43.86#ibcon#*before return 0, iclass 20, count 0 2006.173.10:47:43.86#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.10:47:43.86#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.10:47:43.86#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.10:47:43.86#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.10:47:43.86$vck44/vb=4,4 2006.173.10:47:43.86#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.10:47:43.86#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.10:47:43.86#ibcon#ireg 11 cls_cnt 2 2006.173.10:47:43.86#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.10:47:43.92#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.10:47:43.92#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.10:47:43.92#ibcon#enter wrdev, iclass 22, count 2 2006.173.10:47:43.92#ibcon#first serial, iclass 22, count 2 2006.173.10:47:43.92#ibcon#enter sib2, iclass 22, count 2 2006.173.10:47:43.92#ibcon#flushed, iclass 22, count 2 2006.173.10:47:43.92#ibcon#about to write, iclass 22, count 2 2006.173.10:47:43.92#ibcon#wrote, iclass 22, count 2 2006.173.10:47:43.92#ibcon#about to read 3, iclass 22, count 2 2006.173.10:47:43.94#ibcon#read 3, iclass 22, count 2 2006.173.10:47:43.94#ibcon#about to read 4, iclass 22, count 2 2006.173.10:47:43.94#ibcon#read 4, iclass 22, count 2 2006.173.10:47:43.94#ibcon#about to read 5, iclass 22, count 2 2006.173.10:47:43.94#ibcon#read 5, iclass 22, count 2 2006.173.10:47:43.94#ibcon#about to read 6, iclass 22, count 2 2006.173.10:47:43.94#ibcon#read 6, iclass 22, count 2 2006.173.10:47:43.94#ibcon#end of sib2, iclass 22, count 2 2006.173.10:47:43.94#ibcon#*mode == 0, iclass 22, count 2 2006.173.10:47:43.94#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.10:47:43.94#ibcon#[27=AT04-04\r\n] 2006.173.10:47:43.94#ibcon#*before write, iclass 22, count 2 2006.173.10:47:43.94#ibcon#enter sib2, iclass 22, count 2 2006.173.10:47:43.94#ibcon#flushed, iclass 22, count 2 2006.173.10:47:43.94#ibcon#about to write, iclass 22, count 2 2006.173.10:47:43.94#ibcon#wrote, iclass 22, count 2 2006.173.10:47:43.94#ibcon#about to read 3, iclass 22, count 2 2006.173.10:47:43.97#ibcon#read 3, iclass 22, count 2 2006.173.10:47:43.97#ibcon#about to read 4, iclass 22, count 2 2006.173.10:47:43.97#ibcon#read 4, iclass 22, count 2 2006.173.10:47:43.97#ibcon#about to read 5, iclass 22, count 2 2006.173.10:47:43.97#ibcon#read 5, iclass 22, count 2 2006.173.10:47:43.97#ibcon#about to read 6, iclass 22, count 2 2006.173.10:47:43.97#ibcon#read 6, iclass 22, count 2 2006.173.10:47:43.97#ibcon#end of sib2, iclass 22, count 2 2006.173.10:47:43.97#ibcon#*after write, iclass 22, count 2 2006.173.10:47:43.97#ibcon#*before return 0, iclass 22, count 2 2006.173.10:47:43.97#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.10:47:43.97#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.10:47:43.97#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.10:47:43.97#ibcon#ireg 7 cls_cnt 0 2006.173.10:47:43.97#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.10:47:44.09#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.10:47:44.09#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.10:47:44.09#ibcon#enter wrdev, iclass 22, count 0 2006.173.10:47:44.09#ibcon#first serial, iclass 22, count 0 2006.173.10:47:44.09#ibcon#enter sib2, iclass 22, count 0 2006.173.10:47:44.09#ibcon#flushed, iclass 22, count 0 2006.173.10:47:44.09#ibcon#about to write, iclass 22, count 0 2006.173.10:47:44.09#ibcon#wrote, iclass 22, count 0 2006.173.10:47:44.09#ibcon#about to read 3, iclass 22, count 0 2006.173.10:47:44.11#ibcon#read 3, iclass 22, count 0 2006.173.10:47:44.11#ibcon#about to read 4, iclass 22, count 0 2006.173.10:47:44.11#ibcon#read 4, iclass 22, count 0 2006.173.10:47:44.11#ibcon#about to read 5, iclass 22, count 0 2006.173.10:47:44.11#ibcon#read 5, iclass 22, count 0 2006.173.10:47:44.11#ibcon#about to read 6, iclass 22, count 0 2006.173.10:47:44.11#ibcon#read 6, iclass 22, count 0 2006.173.10:47:44.11#ibcon#end of sib2, iclass 22, count 0 2006.173.10:47:44.11#ibcon#*mode == 0, iclass 22, count 0 2006.173.10:47:44.11#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.10:47:44.11#ibcon#[27=USB\r\n] 2006.173.10:47:44.11#ibcon#*before write, iclass 22, count 0 2006.173.10:47:44.11#ibcon#enter sib2, iclass 22, count 0 2006.173.10:47:44.11#ibcon#flushed, iclass 22, count 0 2006.173.10:47:44.11#ibcon#about to write, iclass 22, count 0 2006.173.10:47:44.11#ibcon#wrote, iclass 22, count 0 2006.173.10:47:44.11#ibcon#about to read 3, iclass 22, count 0 2006.173.10:47:44.14#ibcon#read 3, iclass 22, count 0 2006.173.10:47:44.14#ibcon#about to read 4, iclass 22, count 0 2006.173.10:47:44.14#ibcon#read 4, iclass 22, count 0 2006.173.10:47:44.14#ibcon#about to read 5, iclass 22, count 0 2006.173.10:47:44.14#ibcon#read 5, iclass 22, count 0 2006.173.10:47:44.14#ibcon#about to read 6, iclass 22, count 0 2006.173.10:47:44.14#ibcon#read 6, iclass 22, count 0 2006.173.10:47:44.14#ibcon#end of sib2, iclass 22, count 0 2006.173.10:47:44.14#ibcon#*after write, iclass 22, count 0 2006.173.10:47:44.14#ibcon#*before return 0, iclass 22, count 0 2006.173.10:47:44.14#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.10:47:44.14#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.10:47:44.14#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.10:47:44.14#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.10:47:44.14$vck44/vblo=5,709.99 2006.173.10:47:44.14#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.10:47:44.14#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.10:47:44.14#ibcon#ireg 17 cls_cnt 0 2006.173.10:47:44.14#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.10:47:44.14#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.10:47:44.14#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.10:47:44.14#ibcon#enter wrdev, iclass 24, count 0 2006.173.10:47:44.14#ibcon#first serial, iclass 24, count 0 2006.173.10:47:44.14#ibcon#enter sib2, iclass 24, count 0 2006.173.10:47:44.14#ibcon#flushed, iclass 24, count 0 2006.173.10:47:44.14#ibcon#about to write, iclass 24, count 0 2006.173.10:47:44.14#ibcon#wrote, iclass 24, count 0 2006.173.10:47:44.14#ibcon#about to read 3, iclass 24, count 0 2006.173.10:47:44.16#ibcon#read 3, iclass 24, count 0 2006.173.10:47:44.16#ibcon#about to read 4, iclass 24, count 0 2006.173.10:47:44.16#ibcon#read 4, iclass 24, count 0 2006.173.10:47:44.16#ibcon#about to read 5, iclass 24, count 0 2006.173.10:47:44.16#ibcon#read 5, iclass 24, count 0 2006.173.10:47:44.16#ibcon#about to read 6, iclass 24, count 0 2006.173.10:47:44.16#ibcon#read 6, iclass 24, count 0 2006.173.10:47:44.16#ibcon#end of sib2, iclass 24, count 0 2006.173.10:47:44.16#ibcon#*mode == 0, iclass 24, count 0 2006.173.10:47:44.16#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.10:47:44.16#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.10:47:44.16#ibcon#*before write, iclass 24, count 0 2006.173.10:47:44.16#ibcon#enter sib2, iclass 24, count 0 2006.173.10:47:44.16#ibcon#flushed, iclass 24, count 0 2006.173.10:47:44.16#ibcon#about to write, iclass 24, count 0 2006.173.10:47:44.16#ibcon#wrote, iclass 24, count 0 2006.173.10:47:44.16#ibcon#about to read 3, iclass 24, count 0 2006.173.10:47:44.20#ibcon#read 3, iclass 24, count 0 2006.173.10:47:44.20#ibcon#about to read 4, iclass 24, count 0 2006.173.10:47:44.20#ibcon#read 4, iclass 24, count 0 2006.173.10:47:44.20#ibcon#about to read 5, iclass 24, count 0 2006.173.10:47:44.20#ibcon#read 5, iclass 24, count 0 2006.173.10:47:44.20#ibcon#about to read 6, iclass 24, count 0 2006.173.10:47:44.20#ibcon#read 6, iclass 24, count 0 2006.173.10:47:44.20#ibcon#end of sib2, iclass 24, count 0 2006.173.10:47:44.20#ibcon#*after write, iclass 24, count 0 2006.173.10:47:44.20#ibcon#*before return 0, iclass 24, count 0 2006.173.10:47:44.20#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.10:47:44.20#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.10:47:44.20#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.10:47:44.20#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.10:47:44.20$vck44/vb=5,4 2006.173.10:47:44.20#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.10:47:44.20#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.10:47:44.20#ibcon#ireg 11 cls_cnt 2 2006.173.10:47:44.20#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.10:47:44.26#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.10:47:44.26#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.10:47:44.26#ibcon#enter wrdev, iclass 26, count 2 2006.173.10:47:44.26#ibcon#first serial, iclass 26, count 2 2006.173.10:47:44.26#ibcon#enter sib2, iclass 26, count 2 2006.173.10:47:44.26#ibcon#flushed, iclass 26, count 2 2006.173.10:47:44.26#ibcon#about to write, iclass 26, count 2 2006.173.10:47:44.26#ibcon#wrote, iclass 26, count 2 2006.173.10:47:44.26#ibcon#about to read 3, iclass 26, count 2 2006.173.10:47:44.28#ibcon#read 3, iclass 26, count 2 2006.173.10:47:44.28#ibcon#about to read 4, iclass 26, count 2 2006.173.10:47:44.28#ibcon#read 4, iclass 26, count 2 2006.173.10:47:44.28#ibcon#about to read 5, iclass 26, count 2 2006.173.10:47:44.28#ibcon#read 5, iclass 26, count 2 2006.173.10:47:44.28#ibcon#about to read 6, iclass 26, count 2 2006.173.10:47:44.28#ibcon#read 6, iclass 26, count 2 2006.173.10:47:44.28#ibcon#end of sib2, iclass 26, count 2 2006.173.10:47:44.28#ibcon#*mode == 0, iclass 26, count 2 2006.173.10:47:44.28#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.10:47:44.28#ibcon#[27=AT05-04\r\n] 2006.173.10:47:44.28#ibcon#*before write, iclass 26, count 2 2006.173.10:47:44.28#ibcon#enter sib2, iclass 26, count 2 2006.173.10:47:44.28#ibcon#flushed, iclass 26, count 2 2006.173.10:47:44.28#ibcon#about to write, iclass 26, count 2 2006.173.10:47:44.28#ibcon#wrote, iclass 26, count 2 2006.173.10:47:44.28#ibcon#about to read 3, iclass 26, count 2 2006.173.10:47:44.31#ibcon#read 3, iclass 26, count 2 2006.173.10:47:44.31#ibcon#about to read 4, iclass 26, count 2 2006.173.10:47:44.31#ibcon#read 4, iclass 26, count 2 2006.173.10:47:44.31#ibcon#about to read 5, iclass 26, count 2 2006.173.10:47:44.31#ibcon#read 5, iclass 26, count 2 2006.173.10:47:44.31#ibcon#about to read 6, iclass 26, count 2 2006.173.10:47:44.31#ibcon#read 6, iclass 26, count 2 2006.173.10:47:44.31#ibcon#end of sib2, iclass 26, count 2 2006.173.10:47:44.31#ibcon#*after write, iclass 26, count 2 2006.173.10:47:44.31#ibcon#*before return 0, iclass 26, count 2 2006.173.10:47:44.31#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.10:47:44.31#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.10:47:44.31#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.10:47:44.31#ibcon#ireg 7 cls_cnt 0 2006.173.10:47:44.31#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.10:47:44.43#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.10:47:44.43#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.10:47:44.43#ibcon#enter wrdev, iclass 26, count 0 2006.173.10:47:44.43#ibcon#first serial, iclass 26, count 0 2006.173.10:47:44.43#ibcon#enter sib2, iclass 26, count 0 2006.173.10:47:44.43#ibcon#flushed, iclass 26, count 0 2006.173.10:47:44.43#ibcon#about to write, iclass 26, count 0 2006.173.10:47:44.43#ibcon#wrote, iclass 26, count 0 2006.173.10:47:44.43#ibcon#about to read 3, iclass 26, count 0 2006.173.10:47:44.45#ibcon#read 3, iclass 26, count 0 2006.173.10:47:44.45#ibcon#about to read 4, iclass 26, count 0 2006.173.10:47:44.45#ibcon#read 4, iclass 26, count 0 2006.173.10:47:44.45#ibcon#about to read 5, iclass 26, count 0 2006.173.10:47:44.45#ibcon#read 5, iclass 26, count 0 2006.173.10:47:44.45#ibcon#about to read 6, iclass 26, count 0 2006.173.10:47:44.45#ibcon#read 6, iclass 26, count 0 2006.173.10:47:44.45#ibcon#end of sib2, iclass 26, count 0 2006.173.10:47:44.45#ibcon#*mode == 0, iclass 26, count 0 2006.173.10:47:44.45#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.10:47:44.45#ibcon#[27=USB\r\n] 2006.173.10:47:44.45#ibcon#*before write, iclass 26, count 0 2006.173.10:47:44.45#ibcon#enter sib2, iclass 26, count 0 2006.173.10:47:44.45#ibcon#flushed, iclass 26, count 0 2006.173.10:47:44.45#ibcon#about to write, iclass 26, count 0 2006.173.10:47:44.45#ibcon#wrote, iclass 26, count 0 2006.173.10:47:44.45#ibcon#about to read 3, iclass 26, count 0 2006.173.10:47:44.48#ibcon#read 3, iclass 26, count 0 2006.173.10:47:44.48#ibcon#about to read 4, iclass 26, count 0 2006.173.10:47:44.48#ibcon#read 4, iclass 26, count 0 2006.173.10:47:44.48#ibcon#about to read 5, iclass 26, count 0 2006.173.10:47:44.48#ibcon#read 5, iclass 26, count 0 2006.173.10:47:44.48#ibcon#about to read 6, iclass 26, count 0 2006.173.10:47:44.48#ibcon#read 6, iclass 26, count 0 2006.173.10:47:44.48#ibcon#end of sib2, iclass 26, count 0 2006.173.10:47:44.48#ibcon#*after write, iclass 26, count 0 2006.173.10:47:44.48#ibcon#*before return 0, iclass 26, count 0 2006.173.10:47:44.48#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.10:47:44.48#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.10:47:44.48#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.10:47:44.48#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.10:47:44.48$vck44/vblo=6,719.99 2006.173.10:47:44.48#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.10:47:44.48#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.10:47:44.48#ibcon#ireg 17 cls_cnt 0 2006.173.10:47:44.48#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.10:47:44.48#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.10:47:44.48#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.10:47:44.48#ibcon#enter wrdev, iclass 28, count 0 2006.173.10:47:44.48#ibcon#first serial, iclass 28, count 0 2006.173.10:47:44.48#ibcon#enter sib2, iclass 28, count 0 2006.173.10:47:44.48#ibcon#flushed, iclass 28, count 0 2006.173.10:47:44.48#ibcon#about to write, iclass 28, count 0 2006.173.10:47:44.48#ibcon#wrote, iclass 28, count 0 2006.173.10:47:44.48#ibcon#about to read 3, iclass 28, count 0 2006.173.10:47:44.50#ibcon#read 3, iclass 28, count 0 2006.173.10:47:44.50#ibcon#about to read 4, iclass 28, count 0 2006.173.10:47:44.50#ibcon#read 4, iclass 28, count 0 2006.173.10:47:44.50#ibcon#about to read 5, iclass 28, count 0 2006.173.10:47:44.50#ibcon#read 5, iclass 28, count 0 2006.173.10:47:44.50#ibcon#about to read 6, iclass 28, count 0 2006.173.10:47:44.50#ibcon#read 6, iclass 28, count 0 2006.173.10:47:44.50#ibcon#end of sib2, iclass 28, count 0 2006.173.10:47:44.50#ibcon#*mode == 0, iclass 28, count 0 2006.173.10:47:44.50#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.10:47:44.50#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.10:47:44.50#ibcon#*before write, iclass 28, count 0 2006.173.10:47:44.50#ibcon#enter sib2, iclass 28, count 0 2006.173.10:47:44.50#ibcon#flushed, iclass 28, count 0 2006.173.10:47:44.50#ibcon#about to write, iclass 28, count 0 2006.173.10:47:44.50#ibcon#wrote, iclass 28, count 0 2006.173.10:47:44.50#ibcon#about to read 3, iclass 28, count 0 2006.173.10:47:44.54#ibcon#read 3, iclass 28, count 0 2006.173.10:47:44.54#ibcon#about to read 4, iclass 28, count 0 2006.173.10:47:44.54#ibcon#read 4, iclass 28, count 0 2006.173.10:47:44.54#ibcon#about to read 5, iclass 28, count 0 2006.173.10:47:44.54#ibcon#read 5, iclass 28, count 0 2006.173.10:47:44.54#ibcon#about to read 6, iclass 28, count 0 2006.173.10:47:44.54#ibcon#read 6, iclass 28, count 0 2006.173.10:47:44.54#ibcon#end of sib2, iclass 28, count 0 2006.173.10:47:44.54#ibcon#*after write, iclass 28, count 0 2006.173.10:47:44.54#ibcon#*before return 0, iclass 28, count 0 2006.173.10:47:44.54#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.10:47:44.54#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.10:47:44.54#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.10:47:44.54#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.10:47:44.54$vck44/vb=6,4 2006.173.10:47:44.54#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.10:47:44.54#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.10:47:44.54#ibcon#ireg 11 cls_cnt 2 2006.173.10:47:44.54#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.10:47:44.60#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.10:47:44.60#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.10:47:44.60#ibcon#enter wrdev, iclass 30, count 2 2006.173.10:47:44.60#ibcon#first serial, iclass 30, count 2 2006.173.10:47:44.60#ibcon#enter sib2, iclass 30, count 2 2006.173.10:47:44.60#ibcon#flushed, iclass 30, count 2 2006.173.10:47:44.60#ibcon#about to write, iclass 30, count 2 2006.173.10:47:44.60#ibcon#wrote, iclass 30, count 2 2006.173.10:47:44.60#ibcon#about to read 3, iclass 30, count 2 2006.173.10:47:44.62#ibcon#read 3, iclass 30, count 2 2006.173.10:47:44.62#ibcon#about to read 4, iclass 30, count 2 2006.173.10:47:44.62#ibcon#read 4, iclass 30, count 2 2006.173.10:47:44.62#ibcon#about to read 5, iclass 30, count 2 2006.173.10:47:44.62#ibcon#read 5, iclass 30, count 2 2006.173.10:47:44.62#ibcon#about to read 6, iclass 30, count 2 2006.173.10:47:44.62#ibcon#read 6, iclass 30, count 2 2006.173.10:47:44.62#ibcon#end of sib2, iclass 30, count 2 2006.173.10:47:44.62#ibcon#*mode == 0, iclass 30, count 2 2006.173.10:47:44.62#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.10:47:44.62#ibcon#[27=AT06-04\r\n] 2006.173.10:47:44.62#ibcon#*before write, iclass 30, count 2 2006.173.10:47:44.62#ibcon#enter sib2, iclass 30, count 2 2006.173.10:47:44.62#ibcon#flushed, iclass 30, count 2 2006.173.10:47:44.62#ibcon#about to write, iclass 30, count 2 2006.173.10:47:44.62#ibcon#wrote, iclass 30, count 2 2006.173.10:47:44.62#ibcon#about to read 3, iclass 30, count 2 2006.173.10:47:44.65#ibcon#read 3, iclass 30, count 2 2006.173.10:47:44.65#ibcon#about to read 4, iclass 30, count 2 2006.173.10:47:44.65#ibcon#read 4, iclass 30, count 2 2006.173.10:47:44.65#ibcon#about to read 5, iclass 30, count 2 2006.173.10:47:44.65#ibcon#read 5, iclass 30, count 2 2006.173.10:47:44.65#ibcon#about to read 6, iclass 30, count 2 2006.173.10:47:44.65#ibcon#read 6, iclass 30, count 2 2006.173.10:47:44.65#ibcon#end of sib2, iclass 30, count 2 2006.173.10:47:44.65#ibcon#*after write, iclass 30, count 2 2006.173.10:47:44.65#ibcon#*before return 0, iclass 30, count 2 2006.173.10:47:44.65#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.10:47:44.65#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.10:47:44.65#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.10:47:44.65#ibcon#ireg 7 cls_cnt 0 2006.173.10:47:44.65#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.10:47:44.77#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.10:47:44.77#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.10:47:44.77#ibcon#enter wrdev, iclass 30, count 0 2006.173.10:47:44.77#ibcon#first serial, iclass 30, count 0 2006.173.10:47:44.77#ibcon#enter sib2, iclass 30, count 0 2006.173.10:47:44.77#ibcon#flushed, iclass 30, count 0 2006.173.10:47:44.77#ibcon#about to write, iclass 30, count 0 2006.173.10:47:44.77#ibcon#wrote, iclass 30, count 0 2006.173.10:47:44.77#ibcon#about to read 3, iclass 30, count 0 2006.173.10:47:44.79#ibcon#read 3, iclass 30, count 0 2006.173.10:47:44.79#ibcon#about to read 4, iclass 30, count 0 2006.173.10:47:44.79#ibcon#read 4, iclass 30, count 0 2006.173.10:47:44.79#ibcon#about to read 5, iclass 30, count 0 2006.173.10:47:44.79#ibcon#read 5, iclass 30, count 0 2006.173.10:47:44.79#ibcon#about to read 6, iclass 30, count 0 2006.173.10:47:44.79#ibcon#read 6, iclass 30, count 0 2006.173.10:47:44.79#ibcon#end of sib2, iclass 30, count 0 2006.173.10:47:44.79#ibcon#*mode == 0, iclass 30, count 0 2006.173.10:47:44.79#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.10:47:44.79#ibcon#[27=USB\r\n] 2006.173.10:47:44.79#ibcon#*before write, iclass 30, count 0 2006.173.10:47:44.79#ibcon#enter sib2, iclass 30, count 0 2006.173.10:47:44.79#ibcon#flushed, iclass 30, count 0 2006.173.10:47:44.79#ibcon#about to write, iclass 30, count 0 2006.173.10:47:44.79#ibcon#wrote, iclass 30, count 0 2006.173.10:47:44.79#ibcon#about to read 3, iclass 30, count 0 2006.173.10:47:44.82#ibcon#read 3, iclass 30, count 0 2006.173.10:47:44.82#ibcon#about to read 4, iclass 30, count 0 2006.173.10:47:44.82#ibcon#read 4, iclass 30, count 0 2006.173.10:47:44.82#ibcon#about to read 5, iclass 30, count 0 2006.173.10:47:44.82#ibcon#read 5, iclass 30, count 0 2006.173.10:47:44.82#ibcon#about to read 6, iclass 30, count 0 2006.173.10:47:44.82#ibcon#read 6, iclass 30, count 0 2006.173.10:47:44.82#ibcon#end of sib2, iclass 30, count 0 2006.173.10:47:44.82#ibcon#*after write, iclass 30, count 0 2006.173.10:47:44.82#ibcon#*before return 0, iclass 30, count 0 2006.173.10:47:44.82#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.10:47:44.82#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.10:47:44.82#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.10:47:44.82#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.10:47:44.82$vck44/vblo=7,734.99 2006.173.10:47:44.82#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.10:47:44.82#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.10:47:44.82#ibcon#ireg 17 cls_cnt 0 2006.173.10:47:44.82#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.10:47:44.82#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.10:47:44.82#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.10:47:44.82#ibcon#enter wrdev, iclass 32, count 0 2006.173.10:47:44.82#ibcon#first serial, iclass 32, count 0 2006.173.10:47:44.82#ibcon#enter sib2, iclass 32, count 0 2006.173.10:47:44.82#ibcon#flushed, iclass 32, count 0 2006.173.10:47:44.82#ibcon#about to write, iclass 32, count 0 2006.173.10:47:44.82#ibcon#wrote, iclass 32, count 0 2006.173.10:47:44.82#ibcon#about to read 3, iclass 32, count 0 2006.173.10:47:44.84#ibcon#read 3, iclass 32, count 0 2006.173.10:47:44.84#ibcon#about to read 4, iclass 32, count 0 2006.173.10:47:44.84#ibcon#read 4, iclass 32, count 0 2006.173.10:47:44.84#ibcon#about to read 5, iclass 32, count 0 2006.173.10:47:44.84#ibcon#read 5, iclass 32, count 0 2006.173.10:47:44.84#ibcon#about to read 6, iclass 32, count 0 2006.173.10:47:44.84#ibcon#read 6, iclass 32, count 0 2006.173.10:47:44.84#ibcon#end of sib2, iclass 32, count 0 2006.173.10:47:44.84#ibcon#*mode == 0, iclass 32, count 0 2006.173.10:47:44.84#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.10:47:44.84#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.10:47:44.84#ibcon#*before write, iclass 32, count 0 2006.173.10:47:44.84#ibcon#enter sib2, iclass 32, count 0 2006.173.10:47:44.84#ibcon#flushed, iclass 32, count 0 2006.173.10:47:44.84#ibcon#about to write, iclass 32, count 0 2006.173.10:47:44.84#ibcon#wrote, iclass 32, count 0 2006.173.10:47:44.84#ibcon#about to read 3, iclass 32, count 0 2006.173.10:47:44.88#ibcon#read 3, iclass 32, count 0 2006.173.10:47:44.88#ibcon#about to read 4, iclass 32, count 0 2006.173.10:47:44.88#ibcon#read 4, iclass 32, count 0 2006.173.10:47:44.88#ibcon#about to read 5, iclass 32, count 0 2006.173.10:47:44.88#ibcon#read 5, iclass 32, count 0 2006.173.10:47:44.88#ibcon#about to read 6, iclass 32, count 0 2006.173.10:47:44.88#ibcon#read 6, iclass 32, count 0 2006.173.10:47:44.88#ibcon#end of sib2, iclass 32, count 0 2006.173.10:47:44.88#ibcon#*after write, iclass 32, count 0 2006.173.10:47:44.88#ibcon#*before return 0, iclass 32, count 0 2006.173.10:47:44.88#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.10:47:44.88#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.10:47:44.88#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.10:47:44.88#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.10:47:44.88$vck44/vb=7,4 2006.173.10:47:44.88#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.10:47:44.88#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.10:47:44.88#ibcon#ireg 11 cls_cnt 2 2006.173.10:47:44.88#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.10:47:44.94#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.10:47:44.94#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.10:47:44.94#ibcon#enter wrdev, iclass 34, count 2 2006.173.10:47:44.94#ibcon#first serial, iclass 34, count 2 2006.173.10:47:44.94#ibcon#enter sib2, iclass 34, count 2 2006.173.10:47:44.94#ibcon#flushed, iclass 34, count 2 2006.173.10:47:44.94#ibcon#about to write, iclass 34, count 2 2006.173.10:47:44.94#ibcon#wrote, iclass 34, count 2 2006.173.10:47:44.94#ibcon#about to read 3, iclass 34, count 2 2006.173.10:47:44.96#ibcon#read 3, iclass 34, count 2 2006.173.10:47:44.96#ibcon#about to read 4, iclass 34, count 2 2006.173.10:47:44.96#ibcon#read 4, iclass 34, count 2 2006.173.10:47:44.96#ibcon#about to read 5, iclass 34, count 2 2006.173.10:47:44.96#ibcon#read 5, iclass 34, count 2 2006.173.10:47:44.96#ibcon#about to read 6, iclass 34, count 2 2006.173.10:47:44.96#ibcon#read 6, iclass 34, count 2 2006.173.10:47:44.96#ibcon#end of sib2, iclass 34, count 2 2006.173.10:47:44.96#ibcon#*mode == 0, iclass 34, count 2 2006.173.10:47:44.96#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.10:47:44.96#ibcon#[27=AT07-04\r\n] 2006.173.10:47:44.96#ibcon#*before write, iclass 34, count 2 2006.173.10:47:44.96#ibcon#enter sib2, iclass 34, count 2 2006.173.10:47:44.96#ibcon#flushed, iclass 34, count 2 2006.173.10:47:44.96#ibcon#about to write, iclass 34, count 2 2006.173.10:47:44.96#ibcon#wrote, iclass 34, count 2 2006.173.10:47:44.96#ibcon#about to read 3, iclass 34, count 2 2006.173.10:47:44.99#ibcon#read 3, iclass 34, count 2 2006.173.10:47:44.99#ibcon#about to read 4, iclass 34, count 2 2006.173.10:47:44.99#ibcon#read 4, iclass 34, count 2 2006.173.10:47:44.99#ibcon#about to read 5, iclass 34, count 2 2006.173.10:47:44.99#ibcon#read 5, iclass 34, count 2 2006.173.10:47:44.99#ibcon#about to read 6, iclass 34, count 2 2006.173.10:47:44.99#ibcon#read 6, iclass 34, count 2 2006.173.10:47:44.99#ibcon#end of sib2, iclass 34, count 2 2006.173.10:47:44.99#ibcon#*after write, iclass 34, count 2 2006.173.10:47:44.99#ibcon#*before return 0, iclass 34, count 2 2006.173.10:47:44.99#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.10:47:44.99#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.10:47:44.99#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.10:47:44.99#ibcon#ireg 7 cls_cnt 0 2006.173.10:47:44.99#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.10:47:45.11#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.10:47:45.11#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.10:47:45.11#ibcon#enter wrdev, iclass 34, count 0 2006.173.10:47:45.11#ibcon#first serial, iclass 34, count 0 2006.173.10:47:45.11#ibcon#enter sib2, iclass 34, count 0 2006.173.10:47:45.11#ibcon#flushed, iclass 34, count 0 2006.173.10:47:45.11#ibcon#about to write, iclass 34, count 0 2006.173.10:47:45.11#ibcon#wrote, iclass 34, count 0 2006.173.10:47:45.11#ibcon#about to read 3, iclass 34, count 0 2006.173.10:47:45.13#ibcon#read 3, iclass 34, count 0 2006.173.10:47:45.13#ibcon#about to read 4, iclass 34, count 0 2006.173.10:47:45.13#ibcon#read 4, iclass 34, count 0 2006.173.10:47:45.13#ibcon#about to read 5, iclass 34, count 0 2006.173.10:47:45.13#ibcon#read 5, iclass 34, count 0 2006.173.10:47:45.13#ibcon#about to read 6, iclass 34, count 0 2006.173.10:47:45.13#ibcon#read 6, iclass 34, count 0 2006.173.10:47:45.13#ibcon#end of sib2, iclass 34, count 0 2006.173.10:47:45.13#ibcon#*mode == 0, iclass 34, count 0 2006.173.10:47:45.13#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.10:47:45.13#ibcon#[27=USB\r\n] 2006.173.10:47:45.13#ibcon#*before write, iclass 34, count 0 2006.173.10:47:45.13#ibcon#enter sib2, iclass 34, count 0 2006.173.10:47:45.13#ibcon#flushed, iclass 34, count 0 2006.173.10:47:45.13#ibcon#about to write, iclass 34, count 0 2006.173.10:47:45.13#ibcon#wrote, iclass 34, count 0 2006.173.10:47:45.13#ibcon#about to read 3, iclass 34, count 0 2006.173.10:47:45.16#ibcon#read 3, iclass 34, count 0 2006.173.10:47:45.16#ibcon#about to read 4, iclass 34, count 0 2006.173.10:47:45.16#ibcon#read 4, iclass 34, count 0 2006.173.10:47:45.16#ibcon#about to read 5, iclass 34, count 0 2006.173.10:47:45.16#ibcon#read 5, iclass 34, count 0 2006.173.10:47:45.16#ibcon#about to read 6, iclass 34, count 0 2006.173.10:47:45.16#ibcon#read 6, iclass 34, count 0 2006.173.10:47:45.16#ibcon#end of sib2, iclass 34, count 0 2006.173.10:47:45.16#ibcon#*after write, iclass 34, count 0 2006.173.10:47:45.16#ibcon#*before return 0, iclass 34, count 0 2006.173.10:47:45.16#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.10:47:45.16#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.10:47:45.16#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.10:47:45.16#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.10:47:45.16$vck44/vblo=8,744.99 2006.173.10:47:45.16#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.10:47:45.16#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.10:47:45.16#ibcon#ireg 17 cls_cnt 0 2006.173.10:47:45.16#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.10:47:45.16#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.10:47:45.16#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.10:47:45.16#ibcon#enter wrdev, iclass 36, count 0 2006.173.10:47:45.16#ibcon#first serial, iclass 36, count 0 2006.173.10:47:45.16#ibcon#enter sib2, iclass 36, count 0 2006.173.10:47:45.16#ibcon#flushed, iclass 36, count 0 2006.173.10:47:45.16#ibcon#about to write, iclass 36, count 0 2006.173.10:47:45.16#ibcon#wrote, iclass 36, count 0 2006.173.10:47:45.16#ibcon#about to read 3, iclass 36, count 0 2006.173.10:47:45.18#ibcon#read 3, iclass 36, count 0 2006.173.10:47:45.18#ibcon#about to read 4, iclass 36, count 0 2006.173.10:47:45.18#ibcon#read 4, iclass 36, count 0 2006.173.10:47:45.18#ibcon#about to read 5, iclass 36, count 0 2006.173.10:47:45.18#ibcon#read 5, iclass 36, count 0 2006.173.10:47:45.18#ibcon#about to read 6, iclass 36, count 0 2006.173.10:47:45.18#ibcon#read 6, iclass 36, count 0 2006.173.10:47:45.18#ibcon#end of sib2, iclass 36, count 0 2006.173.10:47:45.18#ibcon#*mode == 0, iclass 36, count 0 2006.173.10:47:45.18#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.10:47:45.18#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.10:47:45.18#ibcon#*before write, iclass 36, count 0 2006.173.10:47:45.18#ibcon#enter sib2, iclass 36, count 0 2006.173.10:47:45.18#ibcon#flushed, iclass 36, count 0 2006.173.10:47:45.18#ibcon#about to write, iclass 36, count 0 2006.173.10:47:45.18#ibcon#wrote, iclass 36, count 0 2006.173.10:47:45.18#ibcon#about to read 3, iclass 36, count 0 2006.173.10:47:45.22#ibcon#read 3, iclass 36, count 0 2006.173.10:47:45.22#ibcon#about to read 4, iclass 36, count 0 2006.173.10:47:45.22#ibcon#read 4, iclass 36, count 0 2006.173.10:47:45.22#ibcon#about to read 5, iclass 36, count 0 2006.173.10:47:45.22#ibcon#read 5, iclass 36, count 0 2006.173.10:47:45.22#ibcon#about to read 6, iclass 36, count 0 2006.173.10:47:45.22#ibcon#read 6, iclass 36, count 0 2006.173.10:47:45.22#ibcon#end of sib2, iclass 36, count 0 2006.173.10:47:45.22#ibcon#*after write, iclass 36, count 0 2006.173.10:47:45.22#ibcon#*before return 0, iclass 36, count 0 2006.173.10:47:45.22#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.10:47:45.22#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.10:47:45.22#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.10:47:45.22#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.10:47:45.22$vck44/vb=8,4 2006.173.10:47:45.22#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.10:47:45.22#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.10:47:45.22#ibcon#ireg 11 cls_cnt 2 2006.173.10:47:45.22#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.10:47:45.28#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.10:47:45.28#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.10:47:45.28#ibcon#enter wrdev, iclass 38, count 2 2006.173.10:47:45.28#ibcon#first serial, iclass 38, count 2 2006.173.10:47:45.28#ibcon#enter sib2, iclass 38, count 2 2006.173.10:47:45.28#ibcon#flushed, iclass 38, count 2 2006.173.10:47:45.28#ibcon#about to write, iclass 38, count 2 2006.173.10:47:45.28#ibcon#wrote, iclass 38, count 2 2006.173.10:47:45.28#ibcon#about to read 3, iclass 38, count 2 2006.173.10:47:45.30#ibcon#read 3, iclass 38, count 2 2006.173.10:47:45.30#ibcon#about to read 4, iclass 38, count 2 2006.173.10:47:45.30#ibcon#read 4, iclass 38, count 2 2006.173.10:47:45.30#ibcon#about to read 5, iclass 38, count 2 2006.173.10:47:45.30#ibcon#read 5, iclass 38, count 2 2006.173.10:47:45.30#ibcon#about to read 6, iclass 38, count 2 2006.173.10:47:45.30#ibcon#read 6, iclass 38, count 2 2006.173.10:47:45.30#ibcon#end of sib2, iclass 38, count 2 2006.173.10:47:45.30#ibcon#*mode == 0, iclass 38, count 2 2006.173.10:47:45.30#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.10:47:45.30#ibcon#[27=AT08-04\r\n] 2006.173.10:47:45.30#ibcon#*before write, iclass 38, count 2 2006.173.10:47:45.30#ibcon#enter sib2, iclass 38, count 2 2006.173.10:47:45.30#ibcon#flushed, iclass 38, count 2 2006.173.10:47:45.30#ibcon#about to write, iclass 38, count 2 2006.173.10:47:45.30#ibcon#wrote, iclass 38, count 2 2006.173.10:47:45.30#ibcon#about to read 3, iclass 38, count 2 2006.173.10:47:45.33#ibcon#read 3, iclass 38, count 2 2006.173.10:47:45.33#ibcon#about to read 4, iclass 38, count 2 2006.173.10:47:45.33#ibcon#read 4, iclass 38, count 2 2006.173.10:47:45.33#ibcon#about to read 5, iclass 38, count 2 2006.173.10:47:45.33#ibcon#read 5, iclass 38, count 2 2006.173.10:47:45.33#ibcon#about to read 6, iclass 38, count 2 2006.173.10:47:45.33#ibcon#read 6, iclass 38, count 2 2006.173.10:47:45.33#ibcon#end of sib2, iclass 38, count 2 2006.173.10:47:45.33#ibcon#*after write, iclass 38, count 2 2006.173.10:47:45.33#ibcon#*before return 0, iclass 38, count 2 2006.173.10:47:45.33#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.10:47:45.33#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.10:47:45.33#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.10:47:45.33#ibcon#ireg 7 cls_cnt 0 2006.173.10:47:45.33#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.10:47:45.45#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.10:47:45.45#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.10:47:45.45#ibcon#enter wrdev, iclass 38, count 0 2006.173.10:47:45.45#ibcon#first serial, iclass 38, count 0 2006.173.10:47:45.45#ibcon#enter sib2, iclass 38, count 0 2006.173.10:47:45.45#ibcon#flushed, iclass 38, count 0 2006.173.10:47:45.45#ibcon#about to write, iclass 38, count 0 2006.173.10:47:45.45#ibcon#wrote, iclass 38, count 0 2006.173.10:47:45.45#ibcon#about to read 3, iclass 38, count 0 2006.173.10:47:45.47#ibcon#read 3, iclass 38, count 0 2006.173.10:47:45.47#ibcon#about to read 4, iclass 38, count 0 2006.173.10:47:45.47#ibcon#read 4, iclass 38, count 0 2006.173.10:47:45.47#ibcon#about to read 5, iclass 38, count 0 2006.173.10:47:45.47#ibcon#read 5, iclass 38, count 0 2006.173.10:47:45.47#ibcon#about to read 6, iclass 38, count 0 2006.173.10:47:45.47#ibcon#read 6, iclass 38, count 0 2006.173.10:47:45.47#ibcon#end of sib2, iclass 38, count 0 2006.173.10:47:45.47#ibcon#*mode == 0, iclass 38, count 0 2006.173.10:47:45.47#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.10:47:45.47#ibcon#[27=USB\r\n] 2006.173.10:47:45.47#ibcon#*before write, iclass 38, count 0 2006.173.10:47:45.47#ibcon#enter sib2, iclass 38, count 0 2006.173.10:47:45.47#ibcon#flushed, iclass 38, count 0 2006.173.10:47:45.47#ibcon#about to write, iclass 38, count 0 2006.173.10:47:45.47#ibcon#wrote, iclass 38, count 0 2006.173.10:47:45.47#ibcon#about to read 3, iclass 38, count 0 2006.173.10:47:45.50#ibcon#read 3, iclass 38, count 0 2006.173.10:47:45.50#ibcon#about to read 4, iclass 38, count 0 2006.173.10:47:45.50#ibcon#read 4, iclass 38, count 0 2006.173.10:47:45.50#ibcon#about to read 5, iclass 38, count 0 2006.173.10:47:45.50#ibcon#read 5, iclass 38, count 0 2006.173.10:47:45.50#ibcon#about to read 6, iclass 38, count 0 2006.173.10:47:45.50#ibcon#read 6, iclass 38, count 0 2006.173.10:47:45.50#ibcon#end of sib2, iclass 38, count 0 2006.173.10:47:45.50#ibcon#*after write, iclass 38, count 0 2006.173.10:47:45.50#ibcon#*before return 0, iclass 38, count 0 2006.173.10:47:45.50#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.10:47:45.50#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.10:47:45.50#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.10:47:45.50#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.10:47:45.50$vck44/vabw=wide 2006.173.10:47:45.50#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.10:47:45.50#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.10:47:45.50#ibcon#ireg 8 cls_cnt 0 2006.173.10:47:45.50#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.10:47:45.50#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.10:47:45.50#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.10:47:45.50#ibcon#enter wrdev, iclass 40, count 0 2006.173.10:47:45.50#ibcon#first serial, iclass 40, count 0 2006.173.10:47:45.50#ibcon#enter sib2, iclass 40, count 0 2006.173.10:47:45.50#ibcon#flushed, iclass 40, count 0 2006.173.10:47:45.50#ibcon#about to write, iclass 40, count 0 2006.173.10:47:45.50#ibcon#wrote, iclass 40, count 0 2006.173.10:47:45.50#ibcon#about to read 3, iclass 40, count 0 2006.173.10:47:45.52#ibcon#read 3, iclass 40, count 0 2006.173.10:47:45.52#ibcon#about to read 4, iclass 40, count 0 2006.173.10:47:45.52#ibcon#read 4, iclass 40, count 0 2006.173.10:47:45.52#ibcon#about to read 5, iclass 40, count 0 2006.173.10:47:45.52#ibcon#read 5, iclass 40, count 0 2006.173.10:47:45.52#ibcon#about to read 6, iclass 40, count 0 2006.173.10:47:45.52#ibcon#read 6, iclass 40, count 0 2006.173.10:47:45.52#ibcon#end of sib2, iclass 40, count 0 2006.173.10:47:45.52#ibcon#*mode == 0, iclass 40, count 0 2006.173.10:47:45.52#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.10:47:45.52#ibcon#[25=BW32\r\n] 2006.173.10:47:45.52#ibcon#*before write, iclass 40, count 0 2006.173.10:47:45.52#ibcon#enter sib2, iclass 40, count 0 2006.173.10:47:45.52#ibcon#flushed, iclass 40, count 0 2006.173.10:47:45.52#ibcon#about to write, iclass 40, count 0 2006.173.10:47:45.52#ibcon#wrote, iclass 40, count 0 2006.173.10:47:45.52#ibcon#about to read 3, iclass 40, count 0 2006.173.10:47:45.55#ibcon#read 3, iclass 40, count 0 2006.173.10:47:45.55#ibcon#about to read 4, iclass 40, count 0 2006.173.10:47:45.55#ibcon#read 4, iclass 40, count 0 2006.173.10:47:45.55#ibcon#about to read 5, iclass 40, count 0 2006.173.10:47:45.55#ibcon#read 5, iclass 40, count 0 2006.173.10:47:45.55#ibcon#about to read 6, iclass 40, count 0 2006.173.10:47:45.55#ibcon#read 6, iclass 40, count 0 2006.173.10:47:45.55#ibcon#end of sib2, iclass 40, count 0 2006.173.10:47:45.55#ibcon#*after write, iclass 40, count 0 2006.173.10:47:45.55#ibcon#*before return 0, iclass 40, count 0 2006.173.10:47:45.55#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.10:47:45.55#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.10:47:45.55#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.10:47:45.55#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.10:47:45.55$vck44/vbbw=wide 2006.173.10:47:45.55#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.10:47:45.55#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.10:47:45.55#ibcon#ireg 8 cls_cnt 0 2006.173.10:47:45.55#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.10:47:45.62#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.10:47:45.62#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.10:47:45.62#ibcon#enter wrdev, iclass 4, count 0 2006.173.10:47:45.62#ibcon#first serial, iclass 4, count 0 2006.173.10:47:45.62#ibcon#enter sib2, iclass 4, count 0 2006.173.10:47:45.62#ibcon#flushed, iclass 4, count 0 2006.173.10:47:45.62#ibcon#about to write, iclass 4, count 0 2006.173.10:47:45.62#ibcon#wrote, iclass 4, count 0 2006.173.10:47:45.62#ibcon#about to read 3, iclass 4, count 0 2006.173.10:47:45.64#ibcon#read 3, iclass 4, count 0 2006.173.10:47:45.64#ibcon#about to read 4, iclass 4, count 0 2006.173.10:47:45.64#ibcon#read 4, iclass 4, count 0 2006.173.10:47:45.64#ibcon#about to read 5, iclass 4, count 0 2006.173.10:47:45.64#ibcon#read 5, iclass 4, count 0 2006.173.10:47:45.64#ibcon#about to read 6, iclass 4, count 0 2006.173.10:47:45.64#ibcon#read 6, iclass 4, count 0 2006.173.10:47:45.64#ibcon#end of sib2, iclass 4, count 0 2006.173.10:47:45.64#ibcon#*mode == 0, iclass 4, count 0 2006.173.10:47:45.64#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.10:47:45.64#ibcon#[27=BW32\r\n] 2006.173.10:47:45.64#ibcon#*before write, iclass 4, count 0 2006.173.10:47:45.64#ibcon#enter sib2, iclass 4, count 0 2006.173.10:47:45.64#ibcon#flushed, iclass 4, count 0 2006.173.10:47:45.64#ibcon#about to write, iclass 4, count 0 2006.173.10:47:45.64#ibcon#wrote, iclass 4, count 0 2006.173.10:47:45.64#ibcon#about to read 3, iclass 4, count 0 2006.173.10:47:45.67#ibcon#read 3, iclass 4, count 0 2006.173.10:47:45.67#ibcon#about to read 4, iclass 4, count 0 2006.173.10:47:45.67#ibcon#read 4, iclass 4, count 0 2006.173.10:47:45.67#ibcon#about to read 5, iclass 4, count 0 2006.173.10:47:45.67#ibcon#read 5, iclass 4, count 0 2006.173.10:47:45.67#ibcon#about to read 6, iclass 4, count 0 2006.173.10:47:45.67#ibcon#read 6, iclass 4, count 0 2006.173.10:47:45.67#ibcon#end of sib2, iclass 4, count 0 2006.173.10:47:45.67#ibcon#*after write, iclass 4, count 0 2006.173.10:47:45.67#ibcon#*before return 0, iclass 4, count 0 2006.173.10:47:45.67#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.10:47:45.67#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.10:47:45.67#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.10:47:45.67#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.10:47:45.67$setupk4/ifdk4 2006.173.10:47:45.67$ifdk4/lo= 2006.173.10:47:45.67$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.10:47:45.67$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.10:47:45.67$ifdk4/patch= 2006.173.10:47:45.67$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.10:47:45.67$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.10:47:45.67$setupk4/!*+20s 2006.173.10:47:52.40#abcon#<5=/05 0.8 1.8 22.66 921003.9\r\n> 2006.173.10:47:52.42#abcon#{5=INTERFACE CLEAR} 2006.173.10:47:52.48#abcon#[5=S1D000X0/0*\r\n] 2006.173.10:47:54.14#trakl#Source acquired 2006.173.10:47:56.14#flagr#flagr/antenna,acquired 2006.173.10:48:00.18$setupk4/"tpicd 2006.173.10:48:00.18$setupk4/echo=off 2006.173.10:48:00.18$setupk4/xlog=off 2006.173.10:48:00.18:!2006.173.10:52:05 2006.173.10:52:05.00:preob 2006.173.10:52:06.14/onsource/TRACKING 2006.173.10:52:06.14:!2006.173.10:52:15 2006.173.10:52:15.00:"tape 2006.173.10:52:15.00:"st=record 2006.173.10:52:15.00:data_valid=on 2006.173.10:52:15.00:midob 2006.173.10:52:15.14/onsource/TRACKING 2006.173.10:52:15.14/wx/22.62,1003.9,92 2006.173.10:52:15.28/cable/+6.5021E-03 2006.173.10:52:16.37/va/01,07,usb,yes,35,38 2006.173.10:52:16.37/va/02,06,usb,yes,35,36 2006.173.10:52:16.37/va/03,05,usb,yes,44,46 2006.173.10:52:16.37/va/04,06,usb,yes,36,38 2006.173.10:52:16.37/va/05,04,usb,yes,28,28 2006.173.10:52:16.37/va/06,03,usb,yes,39,39 2006.173.10:52:16.37/va/07,04,usb,yes,32,33 2006.173.10:52:16.37/va/08,04,usb,yes,27,33 2006.173.10:52:16.60/valo/01,524.99,yes,locked 2006.173.10:52:16.60/valo/02,534.99,yes,locked 2006.173.10:52:16.60/valo/03,564.99,yes,locked 2006.173.10:52:16.60/valo/04,624.99,yes,locked 2006.173.10:52:16.60/valo/05,734.99,yes,locked 2006.173.10:52:16.60/valo/06,814.99,yes,locked 2006.173.10:52:16.60/valo/07,864.99,yes,locked 2006.173.10:52:16.60/valo/08,884.99,yes,locked 2006.173.10:52:17.69/vb/01,04,usb,yes,29,27 2006.173.10:52:17.69/vb/02,04,usb,yes,31,31 2006.173.10:52:17.69/vb/03,04,usb,yes,28,31 2006.173.10:52:17.69/vb/04,04,usb,yes,32,31 2006.173.10:52:17.69/vb/05,04,usb,yes,25,27 2006.173.10:52:17.69/vb/06,04,usb,yes,29,26 2006.173.10:52:17.69/vb/07,04,usb,yes,29,29 2006.173.10:52:17.69/vb/08,04,usb,yes,27,30 2006.173.10:52:17.93/vblo/01,629.99,yes,locked 2006.173.10:52:17.93/vblo/02,634.99,yes,locked 2006.173.10:52:17.93/vblo/03,649.99,yes,locked 2006.173.10:52:17.93/vblo/04,679.99,yes,locked 2006.173.10:52:17.93/vblo/05,709.99,yes,locked 2006.173.10:52:17.93/vblo/06,719.99,yes,locked 2006.173.10:52:17.93/vblo/07,734.99,yes,locked 2006.173.10:52:17.93/vblo/08,744.99,yes,locked 2006.173.10:52:18.08/vabw/8 2006.173.10:52:18.23/vbbw/8 2006.173.10:52:18.32/xfe/off,on,14.5 2006.173.10:52:18.69/ifatt/23,28,28,28 2006.173.10:52:19.08/fmout-gps/S +4.02E-07 2006.173.10:52:19.12:!2006.173.10:53:55 2006.173.10:53:55.00:data_valid=off 2006.173.10:53:55.00:"et 2006.173.10:53:55.00:!+3s 2006.173.10:53:58.01:"tape 2006.173.10:53:58.01:postob 2006.173.10:53:58.12/cable/+6.5022E-03 2006.173.10:53:58.12/wx/22.59,1003.9,92 2006.173.10:53:59.08/fmout-gps/S +4.03E-07 2006.173.10:53:59.08:scan_name=173-1055,jd0606,40 2006.173.10:53:59.08:source=1741-038,174358.86,-035004.6,2000.0,cw 2006.173.10:54:00.14#flagr#flagr/antenna,new-source 2006.173.10:54:00.14:checkk5 2006.173.10:54:00.56/chk_autoobs//k5ts1/ autoobs is running! 2006.173.10:54:00.95/chk_autoobs//k5ts2/ autoobs is running! 2006.173.10:54:01.36/chk_autoobs//k5ts3/ autoobs is running! 2006.173.10:54:01.75/chk_autoobs//k5ts4/ autoobs is running! 2006.173.10:54:02.13/chk_obsdata//k5ts1/T1731052??a.dat file size is correct (nominal:400MB, actual:396MB). 2006.173.10:54:02.52/chk_obsdata//k5ts2/T1731052??b.dat file size is correct (nominal:400MB, actual:396MB). 2006.173.10:54:02.92/chk_obsdata//k5ts3/T1731052??c.dat file size is correct (nominal:400MB, actual:396MB). 2006.173.10:54:03.32/chk_obsdata//k5ts4/T1731052??d.dat file size is correct (nominal:400MB, actual:396MB). 2006.173.10:54:04.04/k5log//k5ts1_log_newline 2006.173.10:54:04.75/k5log//k5ts2_log_newline 2006.173.10:54:05.46/k5log//k5ts3_log_newline 2006.173.10:54:06.16/k5log//k5ts4_log_newline 2006.173.10:54:06.19/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.10:54:06.19:setupk4=1 2006.173.10:54:06.19$setupk4/echo=on 2006.173.10:54:06.19$setupk4/pcalon 2006.173.10:54:06.19$pcalon/"no phase cal control is implemented here 2006.173.10:54:06.19$setupk4/"tpicd=stop 2006.173.10:54:06.19$setupk4/"rec=synch_on 2006.173.10:54:06.19$setupk4/"rec_mode=128 2006.173.10:54:06.19$setupk4/!* 2006.173.10:54:06.19$setupk4/recpk4 2006.173.10:54:06.19$recpk4/recpatch= 2006.173.10:54:06.20$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.10:54:06.20$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.10:54:06.20$setupk4/vck44 2006.173.10:54:06.20$vck44/valo=1,524.99 2006.173.10:54:06.20#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.10:54:06.20#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.10:54:06.20#ibcon#ireg 17 cls_cnt 0 2006.173.10:54:06.20#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.10:54:06.20#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.10:54:06.20#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.10:54:06.20#ibcon#enter wrdev, iclass 15, count 0 2006.173.10:54:06.20#ibcon#first serial, iclass 15, count 0 2006.173.10:54:06.20#ibcon#enter sib2, iclass 15, count 0 2006.173.10:54:06.20#ibcon#flushed, iclass 15, count 0 2006.173.10:54:06.20#ibcon#about to write, iclass 15, count 0 2006.173.10:54:06.20#ibcon#wrote, iclass 15, count 0 2006.173.10:54:06.20#ibcon#about to read 3, iclass 15, count 0 2006.173.10:54:06.22#ibcon#read 3, iclass 15, count 0 2006.173.10:54:06.22#ibcon#about to read 4, iclass 15, count 0 2006.173.10:54:06.22#ibcon#read 4, iclass 15, count 0 2006.173.10:54:06.22#ibcon#about to read 5, iclass 15, count 0 2006.173.10:54:06.22#ibcon#read 5, iclass 15, count 0 2006.173.10:54:06.22#ibcon#about to read 6, iclass 15, count 0 2006.173.10:54:06.22#ibcon#read 6, iclass 15, count 0 2006.173.10:54:06.22#ibcon#end of sib2, iclass 15, count 0 2006.173.10:54:06.22#ibcon#*mode == 0, iclass 15, count 0 2006.173.10:54:06.22#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.10:54:06.22#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.10:54:06.22#ibcon#*before write, iclass 15, count 0 2006.173.10:54:06.22#ibcon#enter sib2, iclass 15, count 0 2006.173.10:54:06.22#ibcon#flushed, iclass 15, count 0 2006.173.10:54:06.22#ibcon#about to write, iclass 15, count 0 2006.173.10:54:06.22#ibcon#wrote, iclass 15, count 0 2006.173.10:54:06.22#ibcon#about to read 3, iclass 15, count 0 2006.173.10:54:06.27#ibcon#read 3, iclass 15, count 0 2006.173.10:54:06.27#ibcon#about to read 4, iclass 15, count 0 2006.173.10:54:06.27#ibcon#read 4, iclass 15, count 0 2006.173.10:54:06.27#ibcon#about to read 5, iclass 15, count 0 2006.173.10:54:06.27#ibcon#read 5, iclass 15, count 0 2006.173.10:54:06.27#ibcon#about to read 6, iclass 15, count 0 2006.173.10:54:06.27#ibcon#read 6, iclass 15, count 0 2006.173.10:54:06.27#ibcon#end of sib2, iclass 15, count 0 2006.173.10:54:06.27#ibcon#*after write, iclass 15, count 0 2006.173.10:54:06.27#ibcon#*before return 0, iclass 15, count 0 2006.173.10:54:06.27#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.10:54:06.27#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.10:54:06.27#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.10:54:06.27#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.10:54:06.27$vck44/va=1,7 2006.173.10:54:06.27#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.10:54:06.27#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.10:54:06.27#ibcon#ireg 11 cls_cnt 2 2006.173.10:54:06.27#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.10:54:06.27#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.10:54:06.27#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.10:54:06.27#ibcon#enter wrdev, iclass 17, count 2 2006.173.10:54:06.27#ibcon#first serial, iclass 17, count 2 2006.173.10:54:06.27#ibcon#enter sib2, iclass 17, count 2 2006.173.10:54:06.27#ibcon#flushed, iclass 17, count 2 2006.173.10:54:06.27#ibcon#about to write, iclass 17, count 2 2006.173.10:54:06.27#ibcon#wrote, iclass 17, count 2 2006.173.10:54:06.27#ibcon#about to read 3, iclass 17, count 2 2006.173.10:54:06.29#ibcon#read 3, iclass 17, count 2 2006.173.10:54:06.29#ibcon#about to read 4, iclass 17, count 2 2006.173.10:54:06.29#ibcon#read 4, iclass 17, count 2 2006.173.10:54:06.29#ibcon#about to read 5, iclass 17, count 2 2006.173.10:54:06.29#ibcon#read 5, iclass 17, count 2 2006.173.10:54:06.29#ibcon#about to read 6, iclass 17, count 2 2006.173.10:54:06.29#ibcon#read 6, iclass 17, count 2 2006.173.10:54:06.29#ibcon#end of sib2, iclass 17, count 2 2006.173.10:54:06.29#ibcon#*mode == 0, iclass 17, count 2 2006.173.10:54:06.29#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.10:54:06.29#ibcon#[25=AT01-07\r\n] 2006.173.10:54:06.29#ibcon#*before write, iclass 17, count 2 2006.173.10:54:06.29#ibcon#enter sib2, iclass 17, count 2 2006.173.10:54:06.29#ibcon#flushed, iclass 17, count 2 2006.173.10:54:06.29#ibcon#about to write, iclass 17, count 2 2006.173.10:54:06.29#ibcon#wrote, iclass 17, count 2 2006.173.10:54:06.29#ibcon#about to read 3, iclass 17, count 2 2006.173.10:54:06.32#ibcon#read 3, iclass 17, count 2 2006.173.10:54:06.32#ibcon#about to read 4, iclass 17, count 2 2006.173.10:54:06.32#ibcon#read 4, iclass 17, count 2 2006.173.10:54:06.32#ibcon#about to read 5, iclass 17, count 2 2006.173.10:54:06.32#ibcon#read 5, iclass 17, count 2 2006.173.10:54:06.32#ibcon#about to read 6, iclass 17, count 2 2006.173.10:54:06.32#ibcon#read 6, iclass 17, count 2 2006.173.10:54:06.32#ibcon#end of sib2, iclass 17, count 2 2006.173.10:54:06.32#ibcon#*after write, iclass 17, count 2 2006.173.10:54:06.32#ibcon#*before return 0, iclass 17, count 2 2006.173.10:54:06.32#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.10:54:06.32#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.10:54:06.32#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.10:54:06.32#ibcon#ireg 7 cls_cnt 0 2006.173.10:54:06.32#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.10:54:06.44#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.10:54:06.44#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.10:54:06.44#ibcon#enter wrdev, iclass 17, count 0 2006.173.10:54:06.44#ibcon#first serial, iclass 17, count 0 2006.173.10:54:06.44#ibcon#enter sib2, iclass 17, count 0 2006.173.10:54:06.44#ibcon#flushed, iclass 17, count 0 2006.173.10:54:06.44#ibcon#about to write, iclass 17, count 0 2006.173.10:54:06.44#ibcon#wrote, iclass 17, count 0 2006.173.10:54:06.44#ibcon#about to read 3, iclass 17, count 0 2006.173.10:54:06.46#ibcon#read 3, iclass 17, count 0 2006.173.10:54:06.46#ibcon#about to read 4, iclass 17, count 0 2006.173.10:54:06.46#ibcon#read 4, iclass 17, count 0 2006.173.10:54:06.46#ibcon#about to read 5, iclass 17, count 0 2006.173.10:54:06.46#ibcon#read 5, iclass 17, count 0 2006.173.10:54:06.46#ibcon#about to read 6, iclass 17, count 0 2006.173.10:54:06.46#ibcon#read 6, iclass 17, count 0 2006.173.10:54:06.46#ibcon#end of sib2, iclass 17, count 0 2006.173.10:54:06.46#ibcon#*mode == 0, iclass 17, count 0 2006.173.10:54:06.46#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.10:54:06.46#ibcon#[25=USB\r\n] 2006.173.10:54:06.46#ibcon#*before write, iclass 17, count 0 2006.173.10:54:06.46#ibcon#enter sib2, iclass 17, count 0 2006.173.10:54:06.46#ibcon#flushed, iclass 17, count 0 2006.173.10:54:06.46#ibcon#about to write, iclass 17, count 0 2006.173.10:54:06.46#ibcon#wrote, iclass 17, count 0 2006.173.10:54:06.46#ibcon#about to read 3, iclass 17, count 0 2006.173.10:54:06.49#ibcon#read 3, iclass 17, count 0 2006.173.10:54:06.49#ibcon#about to read 4, iclass 17, count 0 2006.173.10:54:06.49#ibcon#read 4, iclass 17, count 0 2006.173.10:54:06.49#ibcon#about to read 5, iclass 17, count 0 2006.173.10:54:06.49#ibcon#read 5, iclass 17, count 0 2006.173.10:54:06.49#ibcon#about to read 6, iclass 17, count 0 2006.173.10:54:06.49#ibcon#read 6, iclass 17, count 0 2006.173.10:54:06.49#ibcon#end of sib2, iclass 17, count 0 2006.173.10:54:06.49#ibcon#*after write, iclass 17, count 0 2006.173.10:54:06.49#ibcon#*before return 0, iclass 17, count 0 2006.173.10:54:06.49#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.10:54:06.49#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.10:54:06.49#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.10:54:06.49#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.10:54:06.49$vck44/valo=2,534.99 2006.173.10:54:06.49#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.10:54:06.49#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.10:54:06.49#ibcon#ireg 17 cls_cnt 0 2006.173.10:54:06.49#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.10:54:06.49#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.10:54:06.49#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.10:54:06.49#ibcon#enter wrdev, iclass 19, count 0 2006.173.10:54:06.49#ibcon#first serial, iclass 19, count 0 2006.173.10:54:06.49#ibcon#enter sib2, iclass 19, count 0 2006.173.10:54:06.49#ibcon#flushed, iclass 19, count 0 2006.173.10:54:06.49#ibcon#about to write, iclass 19, count 0 2006.173.10:54:06.49#ibcon#wrote, iclass 19, count 0 2006.173.10:54:06.49#ibcon#about to read 3, iclass 19, count 0 2006.173.10:54:06.51#ibcon#read 3, iclass 19, count 0 2006.173.10:54:06.51#ibcon#about to read 4, iclass 19, count 0 2006.173.10:54:06.51#ibcon#read 4, iclass 19, count 0 2006.173.10:54:06.51#ibcon#about to read 5, iclass 19, count 0 2006.173.10:54:06.51#ibcon#read 5, iclass 19, count 0 2006.173.10:54:06.51#ibcon#about to read 6, iclass 19, count 0 2006.173.10:54:06.51#ibcon#read 6, iclass 19, count 0 2006.173.10:54:06.51#ibcon#end of sib2, iclass 19, count 0 2006.173.10:54:06.51#ibcon#*mode == 0, iclass 19, count 0 2006.173.10:54:06.51#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.10:54:06.51#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.10:54:06.51#ibcon#*before write, iclass 19, count 0 2006.173.10:54:06.51#ibcon#enter sib2, iclass 19, count 0 2006.173.10:54:06.51#ibcon#flushed, iclass 19, count 0 2006.173.10:54:06.51#ibcon#about to write, iclass 19, count 0 2006.173.10:54:06.51#ibcon#wrote, iclass 19, count 0 2006.173.10:54:06.51#ibcon#about to read 3, iclass 19, count 0 2006.173.10:54:06.55#ibcon#read 3, iclass 19, count 0 2006.173.10:54:06.55#ibcon#about to read 4, iclass 19, count 0 2006.173.10:54:06.55#ibcon#read 4, iclass 19, count 0 2006.173.10:54:06.55#ibcon#about to read 5, iclass 19, count 0 2006.173.10:54:06.55#ibcon#read 5, iclass 19, count 0 2006.173.10:54:06.55#ibcon#about to read 6, iclass 19, count 0 2006.173.10:54:06.55#ibcon#read 6, iclass 19, count 0 2006.173.10:54:06.55#ibcon#end of sib2, iclass 19, count 0 2006.173.10:54:06.55#ibcon#*after write, iclass 19, count 0 2006.173.10:54:06.55#ibcon#*before return 0, iclass 19, count 0 2006.173.10:54:06.55#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.10:54:06.55#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.10:54:06.55#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.10:54:06.55#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.10:54:06.55$vck44/va=2,6 2006.173.10:54:06.55#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.10:54:06.55#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.10:54:06.55#ibcon#ireg 11 cls_cnt 2 2006.173.10:54:06.55#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.10:54:06.61#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.10:54:06.61#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.10:54:06.61#ibcon#enter wrdev, iclass 21, count 2 2006.173.10:54:06.61#ibcon#first serial, iclass 21, count 2 2006.173.10:54:06.61#ibcon#enter sib2, iclass 21, count 2 2006.173.10:54:06.61#ibcon#flushed, iclass 21, count 2 2006.173.10:54:06.61#ibcon#about to write, iclass 21, count 2 2006.173.10:54:06.61#ibcon#wrote, iclass 21, count 2 2006.173.10:54:06.61#ibcon#about to read 3, iclass 21, count 2 2006.173.10:54:06.63#ibcon#read 3, iclass 21, count 2 2006.173.10:54:06.63#ibcon#about to read 4, iclass 21, count 2 2006.173.10:54:06.63#ibcon#read 4, iclass 21, count 2 2006.173.10:54:06.63#ibcon#about to read 5, iclass 21, count 2 2006.173.10:54:06.63#ibcon#read 5, iclass 21, count 2 2006.173.10:54:06.63#ibcon#about to read 6, iclass 21, count 2 2006.173.10:54:06.63#ibcon#read 6, iclass 21, count 2 2006.173.10:54:06.63#ibcon#end of sib2, iclass 21, count 2 2006.173.10:54:06.63#ibcon#*mode == 0, iclass 21, count 2 2006.173.10:54:06.63#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.10:54:06.63#ibcon#[25=AT02-06\r\n] 2006.173.10:54:06.63#ibcon#*before write, iclass 21, count 2 2006.173.10:54:06.63#ibcon#enter sib2, iclass 21, count 2 2006.173.10:54:06.63#ibcon#flushed, iclass 21, count 2 2006.173.10:54:06.63#ibcon#about to write, iclass 21, count 2 2006.173.10:54:06.63#ibcon#wrote, iclass 21, count 2 2006.173.10:54:06.63#ibcon#about to read 3, iclass 21, count 2 2006.173.10:54:06.66#ibcon#read 3, iclass 21, count 2 2006.173.10:54:06.66#ibcon#about to read 4, iclass 21, count 2 2006.173.10:54:06.66#ibcon#read 4, iclass 21, count 2 2006.173.10:54:06.66#ibcon#about to read 5, iclass 21, count 2 2006.173.10:54:06.66#ibcon#read 5, iclass 21, count 2 2006.173.10:54:06.66#ibcon#about to read 6, iclass 21, count 2 2006.173.10:54:06.66#ibcon#read 6, iclass 21, count 2 2006.173.10:54:06.66#ibcon#end of sib2, iclass 21, count 2 2006.173.10:54:06.66#ibcon#*after write, iclass 21, count 2 2006.173.10:54:06.66#ibcon#*before return 0, iclass 21, count 2 2006.173.10:54:06.66#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.10:54:06.66#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.10:54:06.66#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.10:54:06.66#ibcon#ireg 7 cls_cnt 0 2006.173.10:54:06.66#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.10:54:06.78#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.10:54:06.78#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.10:54:06.78#ibcon#enter wrdev, iclass 21, count 0 2006.173.10:54:06.78#ibcon#first serial, iclass 21, count 0 2006.173.10:54:06.78#ibcon#enter sib2, iclass 21, count 0 2006.173.10:54:06.78#ibcon#flushed, iclass 21, count 0 2006.173.10:54:06.78#ibcon#about to write, iclass 21, count 0 2006.173.10:54:06.78#ibcon#wrote, iclass 21, count 0 2006.173.10:54:06.78#ibcon#about to read 3, iclass 21, count 0 2006.173.10:54:06.80#ibcon#read 3, iclass 21, count 0 2006.173.10:54:06.80#ibcon#about to read 4, iclass 21, count 0 2006.173.10:54:06.80#ibcon#read 4, iclass 21, count 0 2006.173.10:54:06.80#ibcon#about to read 5, iclass 21, count 0 2006.173.10:54:06.80#ibcon#read 5, iclass 21, count 0 2006.173.10:54:06.80#ibcon#about to read 6, iclass 21, count 0 2006.173.10:54:06.80#ibcon#read 6, iclass 21, count 0 2006.173.10:54:06.80#ibcon#end of sib2, iclass 21, count 0 2006.173.10:54:06.80#ibcon#*mode == 0, iclass 21, count 0 2006.173.10:54:06.80#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.10:54:06.80#ibcon#[25=USB\r\n] 2006.173.10:54:06.80#ibcon#*before write, iclass 21, count 0 2006.173.10:54:06.80#ibcon#enter sib2, iclass 21, count 0 2006.173.10:54:06.80#ibcon#flushed, iclass 21, count 0 2006.173.10:54:06.80#ibcon#about to write, iclass 21, count 0 2006.173.10:54:06.80#ibcon#wrote, iclass 21, count 0 2006.173.10:54:06.80#ibcon#about to read 3, iclass 21, count 0 2006.173.10:54:06.83#ibcon#read 3, iclass 21, count 0 2006.173.10:54:06.83#ibcon#about to read 4, iclass 21, count 0 2006.173.10:54:06.83#ibcon#read 4, iclass 21, count 0 2006.173.10:54:06.83#ibcon#about to read 5, iclass 21, count 0 2006.173.10:54:06.83#ibcon#read 5, iclass 21, count 0 2006.173.10:54:06.83#ibcon#about to read 6, iclass 21, count 0 2006.173.10:54:06.83#ibcon#read 6, iclass 21, count 0 2006.173.10:54:06.83#ibcon#end of sib2, iclass 21, count 0 2006.173.10:54:06.83#ibcon#*after write, iclass 21, count 0 2006.173.10:54:06.83#ibcon#*before return 0, iclass 21, count 0 2006.173.10:54:06.83#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.10:54:06.83#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.10:54:06.83#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.10:54:06.83#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.10:54:06.83$vck44/valo=3,564.99 2006.173.10:54:06.83#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.10:54:06.83#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.10:54:06.83#ibcon#ireg 17 cls_cnt 0 2006.173.10:54:06.83#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.10:54:06.83#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.10:54:06.83#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.10:54:06.83#ibcon#enter wrdev, iclass 23, count 0 2006.173.10:54:06.83#ibcon#first serial, iclass 23, count 0 2006.173.10:54:06.83#ibcon#enter sib2, iclass 23, count 0 2006.173.10:54:06.83#ibcon#flushed, iclass 23, count 0 2006.173.10:54:06.83#ibcon#about to write, iclass 23, count 0 2006.173.10:54:06.83#ibcon#wrote, iclass 23, count 0 2006.173.10:54:06.83#ibcon#about to read 3, iclass 23, count 0 2006.173.10:54:06.85#ibcon#read 3, iclass 23, count 0 2006.173.10:54:06.85#ibcon#about to read 4, iclass 23, count 0 2006.173.10:54:06.85#ibcon#read 4, iclass 23, count 0 2006.173.10:54:06.85#ibcon#about to read 5, iclass 23, count 0 2006.173.10:54:06.85#ibcon#read 5, iclass 23, count 0 2006.173.10:54:06.85#ibcon#about to read 6, iclass 23, count 0 2006.173.10:54:06.85#ibcon#read 6, iclass 23, count 0 2006.173.10:54:06.85#ibcon#end of sib2, iclass 23, count 0 2006.173.10:54:06.85#ibcon#*mode == 0, iclass 23, count 0 2006.173.10:54:06.85#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.10:54:06.85#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.10:54:06.85#ibcon#*before write, iclass 23, count 0 2006.173.10:54:06.85#ibcon#enter sib2, iclass 23, count 0 2006.173.10:54:06.85#ibcon#flushed, iclass 23, count 0 2006.173.10:54:06.85#ibcon#about to write, iclass 23, count 0 2006.173.10:54:06.85#ibcon#wrote, iclass 23, count 0 2006.173.10:54:06.85#ibcon#about to read 3, iclass 23, count 0 2006.173.10:54:06.89#ibcon#read 3, iclass 23, count 0 2006.173.10:54:06.89#ibcon#about to read 4, iclass 23, count 0 2006.173.10:54:06.89#ibcon#read 4, iclass 23, count 0 2006.173.10:54:06.89#ibcon#about to read 5, iclass 23, count 0 2006.173.10:54:06.89#ibcon#read 5, iclass 23, count 0 2006.173.10:54:06.89#ibcon#about to read 6, iclass 23, count 0 2006.173.10:54:06.89#ibcon#read 6, iclass 23, count 0 2006.173.10:54:06.89#ibcon#end of sib2, iclass 23, count 0 2006.173.10:54:06.89#ibcon#*after write, iclass 23, count 0 2006.173.10:54:06.89#ibcon#*before return 0, iclass 23, count 0 2006.173.10:54:06.89#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.10:54:06.89#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.10:54:06.89#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.10:54:06.89#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.10:54:06.89$vck44/va=3,5 2006.173.10:54:06.89#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.10:54:06.89#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.10:54:06.89#ibcon#ireg 11 cls_cnt 2 2006.173.10:54:06.89#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.10:54:06.95#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.10:54:06.95#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.10:54:06.95#ibcon#enter wrdev, iclass 25, count 2 2006.173.10:54:06.95#ibcon#first serial, iclass 25, count 2 2006.173.10:54:06.95#ibcon#enter sib2, iclass 25, count 2 2006.173.10:54:06.95#ibcon#flushed, iclass 25, count 2 2006.173.10:54:06.95#ibcon#about to write, iclass 25, count 2 2006.173.10:54:06.95#ibcon#wrote, iclass 25, count 2 2006.173.10:54:06.95#ibcon#about to read 3, iclass 25, count 2 2006.173.10:54:06.97#ibcon#read 3, iclass 25, count 2 2006.173.10:54:06.97#ibcon#about to read 4, iclass 25, count 2 2006.173.10:54:06.97#ibcon#read 4, iclass 25, count 2 2006.173.10:54:06.97#ibcon#about to read 5, iclass 25, count 2 2006.173.10:54:06.97#ibcon#read 5, iclass 25, count 2 2006.173.10:54:06.97#ibcon#about to read 6, iclass 25, count 2 2006.173.10:54:06.97#ibcon#read 6, iclass 25, count 2 2006.173.10:54:06.97#ibcon#end of sib2, iclass 25, count 2 2006.173.10:54:06.97#ibcon#*mode == 0, iclass 25, count 2 2006.173.10:54:06.97#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.10:54:06.97#ibcon#[25=AT03-05\r\n] 2006.173.10:54:06.97#ibcon#*before write, iclass 25, count 2 2006.173.10:54:06.97#ibcon#enter sib2, iclass 25, count 2 2006.173.10:54:06.97#ibcon#flushed, iclass 25, count 2 2006.173.10:54:06.97#ibcon#about to write, iclass 25, count 2 2006.173.10:54:06.97#ibcon#wrote, iclass 25, count 2 2006.173.10:54:06.97#ibcon#about to read 3, iclass 25, count 2 2006.173.10:54:07.00#ibcon#read 3, iclass 25, count 2 2006.173.10:54:07.00#ibcon#about to read 4, iclass 25, count 2 2006.173.10:54:07.00#ibcon#read 4, iclass 25, count 2 2006.173.10:54:07.00#ibcon#about to read 5, iclass 25, count 2 2006.173.10:54:07.00#ibcon#read 5, iclass 25, count 2 2006.173.10:54:07.00#ibcon#about to read 6, iclass 25, count 2 2006.173.10:54:07.00#ibcon#read 6, iclass 25, count 2 2006.173.10:54:07.00#ibcon#end of sib2, iclass 25, count 2 2006.173.10:54:07.00#ibcon#*after write, iclass 25, count 2 2006.173.10:54:07.00#ibcon#*before return 0, iclass 25, count 2 2006.173.10:54:07.00#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.10:54:07.00#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.10:54:07.00#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.10:54:07.00#ibcon#ireg 7 cls_cnt 0 2006.173.10:54:07.00#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.10:54:07.12#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.10:54:07.12#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.10:54:07.12#ibcon#enter wrdev, iclass 25, count 0 2006.173.10:54:07.12#ibcon#first serial, iclass 25, count 0 2006.173.10:54:07.12#ibcon#enter sib2, iclass 25, count 0 2006.173.10:54:07.12#ibcon#flushed, iclass 25, count 0 2006.173.10:54:07.12#ibcon#about to write, iclass 25, count 0 2006.173.10:54:07.12#ibcon#wrote, iclass 25, count 0 2006.173.10:54:07.12#ibcon#about to read 3, iclass 25, count 0 2006.173.10:54:07.14#ibcon#read 3, iclass 25, count 0 2006.173.10:54:07.14#ibcon#about to read 4, iclass 25, count 0 2006.173.10:54:07.14#ibcon#read 4, iclass 25, count 0 2006.173.10:54:07.14#ibcon#about to read 5, iclass 25, count 0 2006.173.10:54:07.14#ibcon#read 5, iclass 25, count 0 2006.173.10:54:07.14#ibcon#about to read 6, iclass 25, count 0 2006.173.10:54:07.14#ibcon#read 6, iclass 25, count 0 2006.173.10:54:07.14#ibcon#end of sib2, iclass 25, count 0 2006.173.10:54:07.14#ibcon#*mode == 0, iclass 25, count 0 2006.173.10:54:07.14#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.10:54:07.14#ibcon#[25=USB\r\n] 2006.173.10:54:07.14#ibcon#*before write, iclass 25, count 0 2006.173.10:54:07.14#ibcon#enter sib2, iclass 25, count 0 2006.173.10:54:07.14#ibcon#flushed, iclass 25, count 0 2006.173.10:54:07.14#ibcon#about to write, iclass 25, count 0 2006.173.10:54:07.14#ibcon#wrote, iclass 25, count 0 2006.173.10:54:07.14#ibcon#about to read 3, iclass 25, count 0 2006.173.10:54:07.17#ibcon#read 3, iclass 25, count 0 2006.173.10:54:07.17#ibcon#about to read 4, iclass 25, count 0 2006.173.10:54:07.17#ibcon#read 4, iclass 25, count 0 2006.173.10:54:07.17#ibcon#about to read 5, iclass 25, count 0 2006.173.10:54:07.17#ibcon#read 5, iclass 25, count 0 2006.173.10:54:07.17#ibcon#about to read 6, iclass 25, count 0 2006.173.10:54:07.17#ibcon#read 6, iclass 25, count 0 2006.173.10:54:07.17#ibcon#end of sib2, iclass 25, count 0 2006.173.10:54:07.17#ibcon#*after write, iclass 25, count 0 2006.173.10:54:07.17#ibcon#*before return 0, iclass 25, count 0 2006.173.10:54:07.17#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.10:54:07.17#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.10:54:07.17#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.10:54:07.17#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.10:54:07.17$vck44/valo=4,624.99 2006.173.10:54:07.17#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.10:54:07.17#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.10:54:07.17#ibcon#ireg 17 cls_cnt 0 2006.173.10:54:07.17#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.10:54:07.17#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.10:54:07.17#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.10:54:07.17#ibcon#enter wrdev, iclass 27, count 0 2006.173.10:54:07.17#ibcon#first serial, iclass 27, count 0 2006.173.10:54:07.17#ibcon#enter sib2, iclass 27, count 0 2006.173.10:54:07.17#ibcon#flushed, iclass 27, count 0 2006.173.10:54:07.17#ibcon#about to write, iclass 27, count 0 2006.173.10:54:07.17#ibcon#wrote, iclass 27, count 0 2006.173.10:54:07.17#ibcon#about to read 3, iclass 27, count 0 2006.173.10:54:07.19#ibcon#read 3, iclass 27, count 0 2006.173.10:54:07.19#ibcon#about to read 4, iclass 27, count 0 2006.173.10:54:07.19#ibcon#read 4, iclass 27, count 0 2006.173.10:54:07.19#ibcon#about to read 5, iclass 27, count 0 2006.173.10:54:07.19#ibcon#read 5, iclass 27, count 0 2006.173.10:54:07.19#ibcon#about to read 6, iclass 27, count 0 2006.173.10:54:07.19#ibcon#read 6, iclass 27, count 0 2006.173.10:54:07.19#ibcon#end of sib2, iclass 27, count 0 2006.173.10:54:07.19#ibcon#*mode == 0, iclass 27, count 0 2006.173.10:54:07.19#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.10:54:07.19#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.10:54:07.19#ibcon#*before write, iclass 27, count 0 2006.173.10:54:07.19#ibcon#enter sib2, iclass 27, count 0 2006.173.10:54:07.19#ibcon#flushed, iclass 27, count 0 2006.173.10:54:07.19#ibcon#about to write, iclass 27, count 0 2006.173.10:54:07.19#ibcon#wrote, iclass 27, count 0 2006.173.10:54:07.19#ibcon#about to read 3, iclass 27, count 0 2006.173.10:54:07.23#ibcon#read 3, iclass 27, count 0 2006.173.10:54:07.23#ibcon#about to read 4, iclass 27, count 0 2006.173.10:54:07.23#ibcon#read 4, iclass 27, count 0 2006.173.10:54:07.23#ibcon#about to read 5, iclass 27, count 0 2006.173.10:54:07.23#ibcon#read 5, iclass 27, count 0 2006.173.10:54:07.23#ibcon#about to read 6, iclass 27, count 0 2006.173.10:54:07.23#ibcon#read 6, iclass 27, count 0 2006.173.10:54:07.23#ibcon#end of sib2, iclass 27, count 0 2006.173.10:54:07.23#ibcon#*after write, iclass 27, count 0 2006.173.10:54:07.23#ibcon#*before return 0, iclass 27, count 0 2006.173.10:54:07.23#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.10:54:07.23#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.10:54:07.23#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.10:54:07.23#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.10:54:07.23$vck44/va=4,6 2006.173.10:54:07.23#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.10:54:07.23#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.10:54:07.23#ibcon#ireg 11 cls_cnt 2 2006.173.10:54:07.23#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.10:54:07.29#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.10:54:07.29#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.10:54:07.29#ibcon#enter wrdev, iclass 29, count 2 2006.173.10:54:07.29#ibcon#first serial, iclass 29, count 2 2006.173.10:54:07.29#ibcon#enter sib2, iclass 29, count 2 2006.173.10:54:07.29#ibcon#flushed, iclass 29, count 2 2006.173.10:54:07.29#ibcon#about to write, iclass 29, count 2 2006.173.10:54:07.29#ibcon#wrote, iclass 29, count 2 2006.173.10:54:07.29#ibcon#about to read 3, iclass 29, count 2 2006.173.10:54:07.31#ibcon#read 3, iclass 29, count 2 2006.173.10:54:07.31#ibcon#about to read 4, iclass 29, count 2 2006.173.10:54:07.31#ibcon#read 4, iclass 29, count 2 2006.173.10:54:07.31#ibcon#about to read 5, iclass 29, count 2 2006.173.10:54:07.31#ibcon#read 5, iclass 29, count 2 2006.173.10:54:07.31#ibcon#about to read 6, iclass 29, count 2 2006.173.10:54:07.31#ibcon#read 6, iclass 29, count 2 2006.173.10:54:07.31#ibcon#end of sib2, iclass 29, count 2 2006.173.10:54:07.31#ibcon#*mode == 0, iclass 29, count 2 2006.173.10:54:07.31#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.10:54:07.31#ibcon#[25=AT04-06\r\n] 2006.173.10:54:07.31#ibcon#*before write, iclass 29, count 2 2006.173.10:54:07.31#ibcon#enter sib2, iclass 29, count 2 2006.173.10:54:07.31#ibcon#flushed, iclass 29, count 2 2006.173.10:54:07.31#ibcon#about to write, iclass 29, count 2 2006.173.10:54:07.31#ibcon#wrote, iclass 29, count 2 2006.173.10:54:07.31#ibcon#about to read 3, iclass 29, count 2 2006.173.10:54:07.34#ibcon#read 3, iclass 29, count 2 2006.173.10:54:07.34#ibcon#about to read 4, iclass 29, count 2 2006.173.10:54:07.34#ibcon#read 4, iclass 29, count 2 2006.173.10:54:07.34#ibcon#about to read 5, iclass 29, count 2 2006.173.10:54:07.34#ibcon#read 5, iclass 29, count 2 2006.173.10:54:07.34#ibcon#about to read 6, iclass 29, count 2 2006.173.10:54:07.34#ibcon#read 6, iclass 29, count 2 2006.173.10:54:07.34#ibcon#end of sib2, iclass 29, count 2 2006.173.10:54:07.34#ibcon#*after write, iclass 29, count 2 2006.173.10:54:07.34#ibcon#*before return 0, iclass 29, count 2 2006.173.10:54:07.34#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.10:54:07.34#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.10:54:07.34#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.10:54:07.34#ibcon#ireg 7 cls_cnt 0 2006.173.10:54:07.34#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.10:54:07.46#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.10:54:07.46#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.10:54:07.46#ibcon#enter wrdev, iclass 29, count 0 2006.173.10:54:07.46#ibcon#first serial, iclass 29, count 0 2006.173.10:54:07.46#ibcon#enter sib2, iclass 29, count 0 2006.173.10:54:07.46#ibcon#flushed, iclass 29, count 0 2006.173.10:54:07.46#ibcon#about to write, iclass 29, count 0 2006.173.10:54:07.46#ibcon#wrote, iclass 29, count 0 2006.173.10:54:07.46#ibcon#about to read 3, iclass 29, count 0 2006.173.10:54:07.48#ibcon#read 3, iclass 29, count 0 2006.173.10:54:07.48#ibcon#about to read 4, iclass 29, count 0 2006.173.10:54:07.48#ibcon#read 4, iclass 29, count 0 2006.173.10:54:07.48#ibcon#about to read 5, iclass 29, count 0 2006.173.10:54:07.48#ibcon#read 5, iclass 29, count 0 2006.173.10:54:07.48#ibcon#about to read 6, iclass 29, count 0 2006.173.10:54:07.48#ibcon#read 6, iclass 29, count 0 2006.173.10:54:07.48#ibcon#end of sib2, iclass 29, count 0 2006.173.10:54:07.48#ibcon#*mode == 0, iclass 29, count 0 2006.173.10:54:07.48#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.10:54:07.48#ibcon#[25=USB\r\n] 2006.173.10:54:07.48#ibcon#*before write, iclass 29, count 0 2006.173.10:54:07.48#ibcon#enter sib2, iclass 29, count 0 2006.173.10:54:07.48#ibcon#flushed, iclass 29, count 0 2006.173.10:54:07.48#ibcon#about to write, iclass 29, count 0 2006.173.10:54:07.48#ibcon#wrote, iclass 29, count 0 2006.173.10:54:07.48#ibcon#about to read 3, iclass 29, count 0 2006.173.10:54:07.51#ibcon#read 3, iclass 29, count 0 2006.173.10:54:07.51#ibcon#about to read 4, iclass 29, count 0 2006.173.10:54:07.51#ibcon#read 4, iclass 29, count 0 2006.173.10:54:07.51#ibcon#about to read 5, iclass 29, count 0 2006.173.10:54:07.51#ibcon#read 5, iclass 29, count 0 2006.173.10:54:07.51#ibcon#about to read 6, iclass 29, count 0 2006.173.10:54:07.51#ibcon#read 6, iclass 29, count 0 2006.173.10:54:07.51#ibcon#end of sib2, iclass 29, count 0 2006.173.10:54:07.51#ibcon#*after write, iclass 29, count 0 2006.173.10:54:07.51#ibcon#*before return 0, iclass 29, count 0 2006.173.10:54:07.51#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.10:54:07.51#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.10:54:07.51#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.10:54:07.51#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.10:54:07.51$vck44/valo=5,734.99 2006.173.10:54:07.51#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.10:54:07.51#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.10:54:07.51#ibcon#ireg 17 cls_cnt 0 2006.173.10:54:07.51#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.10:54:07.51#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.10:54:07.51#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.10:54:07.51#ibcon#enter wrdev, iclass 31, count 0 2006.173.10:54:07.51#ibcon#first serial, iclass 31, count 0 2006.173.10:54:07.51#ibcon#enter sib2, iclass 31, count 0 2006.173.10:54:07.51#ibcon#flushed, iclass 31, count 0 2006.173.10:54:07.51#ibcon#about to write, iclass 31, count 0 2006.173.10:54:07.51#ibcon#wrote, iclass 31, count 0 2006.173.10:54:07.51#ibcon#about to read 3, iclass 31, count 0 2006.173.10:54:07.53#ibcon#read 3, iclass 31, count 0 2006.173.10:54:07.53#ibcon#about to read 4, iclass 31, count 0 2006.173.10:54:07.53#ibcon#read 4, iclass 31, count 0 2006.173.10:54:07.53#ibcon#about to read 5, iclass 31, count 0 2006.173.10:54:07.53#ibcon#read 5, iclass 31, count 0 2006.173.10:54:07.53#ibcon#about to read 6, iclass 31, count 0 2006.173.10:54:07.53#ibcon#read 6, iclass 31, count 0 2006.173.10:54:07.53#ibcon#end of sib2, iclass 31, count 0 2006.173.10:54:07.53#ibcon#*mode == 0, iclass 31, count 0 2006.173.10:54:07.53#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.10:54:07.53#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.10:54:07.53#ibcon#*before write, iclass 31, count 0 2006.173.10:54:07.53#ibcon#enter sib2, iclass 31, count 0 2006.173.10:54:07.53#ibcon#flushed, iclass 31, count 0 2006.173.10:54:07.53#ibcon#about to write, iclass 31, count 0 2006.173.10:54:07.53#ibcon#wrote, iclass 31, count 0 2006.173.10:54:07.53#ibcon#about to read 3, iclass 31, count 0 2006.173.10:54:07.57#ibcon#read 3, iclass 31, count 0 2006.173.10:54:07.57#ibcon#about to read 4, iclass 31, count 0 2006.173.10:54:07.57#ibcon#read 4, iclass 31, count 0 2006.173.10:54:07.57#ibcon#about to read 5, iclass 31, count 0 2006.173.10:54:07.57#ibcon#read 5, iclass 31, count 0 2006.173.10:54:07.57#ibcon#about to read 6, iclass 31, count 0 2006.173.10:54:07.57#ibcon#read 6, iclass 31, count 0 2006.173.10:54:07.57#ibcon#end of sib2, iclass 31, count 0 2006.173.10:54:07.57#ibcon#*after write, iclass 31, count 0 2006.173.10:54:07.57#ibcon#*before return 0, iclass 31, count 0 2006.173.10:54:07.57#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.10:54:07.57#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.10:54:07.57#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.10:54:07.57#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.10:54:07.57$vck44/va=5,4 2006.173.10:54:07.57#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.173.10:54:07.57#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.173.10:54:07.57#ibcon#ireg 11 cls_cnt 2 2006.173.10:54:07.57#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.10:54:07.63#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.10:54:07.63#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.10:54:07.63#ibcon#enter wrdev, iclass 33, count 2 2006.173.10:54:07.63#ibcon#first serial, iclass 33, count 2 2006.173.10:54:07.63#ibcon#enter sib2, iclass 33, count 2 2006.173.10:54:07.63#ibcon#flushed, iclass 33, count 2 2006.173.10:54:07.63#ibcon#about to write, iclass 33, count 2 2006.173.10:54:07.63#ibcon#wrote, iclass 33, count 2 2006.173.10:54:07.63#ibcon#about to read 3, iclass 33, count 2 2006.173.10:54:07.65#ibcon#read 3, iclass 33, count 2 2006.173.10:54:07.65#ibcon#about to read 4, iclass 33, count 2 2006.173.10:54:07.65#ibcon#read 4, iclass 33, count 2 2006.173.10:54:07.65#ibcon#about to read 5, iclass 33, count 2 2006.173.10:54:07.65#ibcon#read 5, iclass 33, count 2 2006.173.10:54:07.65#ibcon#about to read 6, iclass 33, count 2 2006.173.10:54:07.65#ibcon#read 6, iclass 33, count 2 2006.173.10:54:07.65#ibcon#end of sib2, iclass 33, count 2 2006.173.10:54:07.65#ibcon#*mode == 0, iclass 33, count 2 2006.173.10:54:07.65#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.173.10:54:07.65#ibcon#[25=AT05-04\r\n] 2006.173.10:54:07.65#ibcon#*before write, iclass 33, count 2 2006.173.10:54:07.65#ibcon#enter sib2, iclass 33, count 2 2006.173.10:54:07.65#ibcon#flushed, iclass 33, count 2 2006.173.10:54:07.65#ibcon#about to write, iclass 33, count 2 2006.173.10:54:07.65#ibcon#wrote, iclass 33, count 2 2006.173.10:54:07.65#ibcon#about to read 3, iclass 33, count 2 2006.173.10:54:07.68#ibcon#read 3, iclass 33, count 2 2006.173.10:54:07.68#ibcon#about to read 4, iclass 33, count 2 2006.173.10:54:07.68#ibcon#read 4, iclass 33, count 2 2006.173.10:54:07.68#ibcon#about to read 5, iclass 33, count 2 2006.173.10:54:07.68#ibcon#read 5, iclass 33, count 2 2006.173.10:54:07.68#ibcon#about to read 6, iclass 33, count 2 2006.173.10:54:07.68#ibcon#read 6, iclass 33, count 2 2006.173.10:54:07.68#ibcon#end of sib2, iclass 33, count 2 2006.173.10:54:07.68#ibcon#*after write, iclass 33, count 2 2006.173.10:54:07.68#ibcon#*before return 0, iclass 33, count 2 2006.173.10:54:07.68#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.10:54:07.68#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.173.10:54:07.68#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.173.10:54:07.68#ibcon#ireg 7 cls_cnt 0 2006.173.10:54:07.68#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.10:54:07.80#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.10:54:07.80#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.10:54:07.80#ibcon#enter wrdev, iclass 33, count 0 2006.173.10:54:07.80#ibcon#first serial, iclass 33, count 0 2006.173.10:54:07.80#ibcon#enter sib2, iclass 33, count 0 2006.173.10:54:07.80#ibcon#flushed, iclass 33, count 0 2006.173.10:54:07.80#ibcon#about to write, iclass 33, count 0 2006.173.10:54:07.80#ibcon#wrote, iclass 33, count 0 2006.173.10:54:07.80#ibcon#about to read 3, iclass 33, count 0 2006.173.10:54:07.82#ibcon#read 3, iclass 33, count 0 2006.173.10:54:07.82#ibcon#about to read 4, iclass 33, count 0 2006.173.10:54:07.82#ibcon#read 4, iclass 33, count 0 2006.173.10:54:07.82#ibcon#about to read 5, iclass 33, count 0 2006.173.10:54:07.82#ibcon#read 5, iclass 33, count 0 2006.173.10:54:07.82#ibcon#about to read 6, iclass 33, count 0 2006.173.10:54:07.82#ibcon#read 6, iclass 33, count 0 2006.173.10:54:07.82#ibcon#end of sib2, iclass 33, count 0 2006.173.10:54:07.82#ibcon#*mode == 0, iclass 33, count 0 2006.173.10:54:07.82#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.10:54:07.82#ibcon#[25=USB\r\n] 2006.173.10:54:07.82#ibcon#*before write, iclass 33, count 0 2006.173.10:54:07.82#ibcon#enter sib2, iclass 33, count 0 2006.173.10:54:07.82#ibcon#flushed, iclass 33, count 0 2006.173.10:54:07.82#ibcon#about to write, iclass 33, count 0 2006.173.10:54:07.82#ibcon#wrote, iclass 33, count 0 2006.173.10:54:07.82#ibcon#about to read 3, iclass 33, count 0 2006.173.10:54:07.85#ibcon#read 3, iclass 33, count 0 2006.173.10:54:07.85#ibcon#about to read 4, iclass 33, count 0 2006.173.10:54:07.85#ibcon#read 4, iclass 33, count 0 2006.173.10:54:07.85#ibcon#about to read 5, iclass 33, count 0 2006.173.10:54:07.85#ibcon#read 5, iclass 33, count 0 2006.173.10:54:07.85#ibcon#about to read 6, iclass 33, count 0 2006.173.10:54:07.85#ibcon#read 6, iclass 33, count 0 2006.173.10:54:07.85#ibcon#end of sib2, iclass 33, count 0 2006.173.10:54:07.85#ibcon#*after write, iclass 33, count 0 2006.173.10:54:07.85#ibcon#*before return 0, iclass 33, count 0 2006.173.10:54:07.85#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.10:54:07.85#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.173.10:54:07.85#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.10:54:07.85#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.10:54:07.85$vck44/valo=6,814.99 2006.173.10:54:07.85#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.10:54:07.85#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.10:54:07.85#ibcon#ireg 17 cls_cnt 0 2006.173.10:54:07.85#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.10:54:07.85#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.10:54:07.85#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.10:54:07.85#ibcon#enter wrdev, iclass 35, count 0 2006.173.10:54:07.85#ibcon#first serial, iclass 35, count 0 2006.173.10:54:07.85#ibcon#enter sib2, iclass 35, count 0 2006.173.10:54:07.85#ibcon#flushed, iclass 35, count 0 2006.173.10:54:07.85#ibcon#about to write, iclass 35, count 0 2006.173.10:54:07.85#ibcon#wrote, iclass 35, count 0 2006.173.10:54:07.85#ibcon#about to read 3, iclass 35, count 0 2006.173.10:54:07.87#ibcon#read 3, iclass 35, count 0 2006.173.10:54:07.87#ibcon#about to read 4, iclass 35, count 0 2006.173.10:54:07.87#ibcon#read 4, iclass 35, count 0 2006.173.10:54:07.87#ibcon#about to read 5, iclass 35, count 0 2006.173.10:54:07.87#ibcon#read 5, iclass 35, count 0 2006.173.10:54:07.87#ibcon#about to read 6, iclass 35, count 0 2006.173.10:54:07.87#ibcon#read 6, iclass 35, count 0 2006.173.10:54:07.87#ibcon#end of sib2, iclass 35, count 0 2006.173.10:54:07.87#ibcon#*mode == 0, iclass 35, count 0 2006.173.10:54:07.87#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.10:54:07.87#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.10:54:07.87#ibcon#*before write, iclass 35, count 0 2006.173.10:54:07.87#ibcon#enter sib2, iclass 35, count 0 2006.173.10:54:07.87#ibcon#flushed, iclass 35, count 0 2006.173.10:54:07.87#ibcon#about to write, iclass 35, count 0 2006.173.10:54:07.87#ibcon#wrote, iclass 35, count 0 2006.173.10:54:07.87#ibcon#about to read 3, iclass 35, count 0 2006.173.10:54:07.91#ibcon#read 3, iclass 35, count 0 2006.173.10:54:07.91#ibcon#about to read 4, iclass 35, count 0 2006.173.10:54:07.91#ibcon#read 4, iclass 35, count 0 2006.173.10:54:07.91#ibcon#about to read 5, iclass 35, count 0 2006.173.10:54:07.91#ibcon#read 5, iclass 35, count 0 2006.173.10:54:07.91#ibcon#about to read 6, iclass 35, count 0 2006.173.10:54:07.91#ibcon#read 6, iclass 35, count 0 2006.173.10:54:07.91#ibcon#end of sib2, iclass 35, count 0 2006.173.10:54:07.91#ibcon#*after write, iclass 35, count 0 2006.173.10:54:07.91#ibcon#*before return 0, iclass 35, count 0 2006.173.10:54:07.91#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.10:54:07.91#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.10:54:07.91#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.10:54:07.91#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.10:54:07.91$vck44/va=6,3 2006.173.10:54:07.91#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.173.10:54:07.91#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.173.10:54:07.91#ibcon#ireg 11 cls_cnt 2 2006.173.10:54:07.91#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.10:54:07.97#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.10:54:07.97#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.10:54:07.97#ibcon#enter wrdev, iclass 37, count 2 2006.173.10:54:07.97#ibcon#first serial, iclass 37, count 2 2006.173.10:54:07.97#ibcon#enter sib2, iclass 37, count 2 2006.173.10:54:07.97#ibcon#flushed, iclass 37, count 2 2006.173.10:54:07.97#ibcon#about to write, iclass 37, count 2 2006.173.10:54:07.97#ibcon#wrote, iclass 37, count 2 2006.173.10:54:07.97#ibcon#about to read 3, iclass 37, count 2 2006.173.10:54:07.99#ibcon#read 3, iclass 37, count 2 2006.173.10:54:07.99#ibcon#about to read 4, iclass 37, count 2 2006.173.10:54:07.99#ibcon#read 4, iclass 37, count 2 2006.173.10:54:07.99#ibcon#about to read 5, iclass 37, count 2 2006.173.10:54:07.99#ibcon#read 5, iclass 37, count 2 2006.173.10:54:07.99#ibcon#about to read 6, iclass 37, count 2 2006.173.10:54:07.99#ibcon#read 6, iclass 37, count 2 2006.173.10:54:07.99#ibcon#end of sib2, iclass 37, count 2 2006.173.10:54:07.99#ibcon#*mode == 0, iclass 37, count 2 2006.173.10:54:07.99#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.173.10:54:07.99#ibcon#[25=AT06-03\r\n] 2006.173.10:54:07.99#ibcon#*before write, iclass 37, count 2 2006.173.10:54:07.99#ibcon#enter sib2, iclass 37, count 2 2006.173.10:54:07.99#ibcon#flushed, iclass 37, count 2 2006.173.10:54:07.99#ibcon#about to write, iclass 37, count 2 2006.173.10:54:07.99#ibcon#wrote, iclass 37, count 2 2006.173.10:54:07.99#ibcon#about to read 3, iclass 37, count 2 2006.173.10:54:08.02#ibcon#read 3, iclass 37, count 2 2006.173.10:54:08.02#ibcon#about to read 4, iclass 37, count 2 2006.173.10:54:08.02#ibcon#read 4, iclass 37, count 2 2006.173.10:54:08.02#ibcon#about to read 5, iclass 37, count 2 2006.173.10:54:08.02#ibcon#read 5, iclass 37, count 2 2006.173.10:54:08.02#ibcon#about to read 6, iclass 37, count 2 2006.173.10:54:08.02#ibcon#read 6, iclass 37, count 2 2006.173.10:54:08.02#ibcon#end of sib2, iclass 37, count 2 2006.173.10:54:08.02#ibcon#*after write, iclass 37, count 2 2006.173.10:54:08.02#ibcon#*before return 0, iclass 37, count 2 2006.173.10:54:08.02#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.10:54:08.02#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.173.10:54:08.02#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.173.10:54:08.02#ibcon#ireg 7 cls_cnt 0 2006.173.10:54:08.02#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.10:54:08.14#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.10:54:08.14#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.10:54:08.14#ibcon#enter wrdev, iclass 37, count 0 2006.173.10:54:08.14#ibcon#first serial, iclass 37, count 0 2006.173.10:54:08.14#ibcon#enter sib2, iclass 37, count 0 2006.173.10:54:08.14#ibcon#flushed, iclass 37, count 0 2006.173.10:54:08.14#ibcon#about to write, iclass 37, count 0 2006.173.10:54:08.14#ibcon#wrote, iclass 37, count 0 2006.173.10:54:08.14#ibcon#about to read 3, iclass 37, count 0 2006.173.10:54:08.16#ibcon#read 3, iclass 37, count 0 2006.173.10:54:08.16#ibcon#about to read 4, iclass 37, count 0 2006.173.10:54:08.16#ibcon#read 4, iclass 37, count 0 2006.173.10:54:08.16#ibcon#about to read 5, iclass 37, count 0 2006.173.10:54:08.16#ibcon#read 5, iclass 37, count 0 2006.173.10:54:08.16#ibcon#about to read 6, iclass 37, count 0 2006.173.10:54:08.16#ibcon#read 6, iclass 37, count 0 2006.173.10:54:08.16#ibcon#end of sib2, iclass 37, count 0 2006.173.10:54:08.16#ibcon#*mode == 0, iclass 37, count 0 2006.173.10:54:08.16#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.10:54:08.16#ibcon#[25=USB\r\n] 2006.173.10:54:08.16#ibcon#*before write, iclass 37, count 0 2006.173.10:54:08.16#ibcon#enter sib2, iclass 37, count 0 2006.173.10:54:08.16#ibcon#flushed, iclass 37, count 0 2006.173.10:54:08.16#ibcon#about to write, iclass 37, count 0 2006.173.10:54:08.16#ibcon#wrote, iclass 37, count 0 2006.173.10:54:08.16#ibcon#about to read 3, iclass 37, count 0 2006.173.10:54:08.19#ibcon#read 3, iclass 37, count 0 2006.173.10:54:08.19#ibcon#about to read 4, iclass 37, count 0 2006.173.10:54:08.19#ibcon#read 4, iclass 37, count 0 2006.173.10:54:08.19#ibcon#about to read 5, iclass 37, count 0 2006.173.10:54:08.19#ibcon#read 5, iclass 37, count 0 2006.173.10:54:08.19#ibcon#about to read 6, iclass 37, count 0 2006.173.10:54:08.19#ibcon#read 6, iclass 37, count 0 2006.173.10:54:08.19#ibcon#end of sib2, iclass 37, count 0 2006.173.10:54:08.19#ibcon#*after write, iclass 37, count 0 2006.173.10:54:08.19#ibcon#*before return 0, iclass 37, count 0 2006.173.10:54:08.19#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.10:54:08.19#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.173.10:54:08.19#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.10:54:08.19#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.10:54:08.19$vck44/valo=7,864.99 2006.173.10:54:08.19#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.10:54:08.19#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.10:54:08.19#ibcon#ireg 17 cls_cnt 0 2006.173.10:54:08.19#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.10:54:08.19#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.10:54:08.19#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.10:54:08.19#ibcon#enter wrdev, iclass 39, count 0 2006.173.10:54:08.19#ibcon#first serial, iclass 39, count 0 2006.173.10:54:08.19#ibcon#enter sib2, iclass 39, count 0 2006.173.10:54:08.19#ibcon#flushed, iclass 39, count 0 2006.173.10:54:08.19#ibcon#about to write, iclass 39, count 0 2006.173.10:54:08.19#ibcon#wrote, iclass 39, count 0 2006.173.10:54:08.19#ibcon#about to read 3, iclass 39, count 0 2006.173.10:54:08.21#ibcon#read 3, iclass 39, count 0 2006.173.10:54:08.21#ibcon#about to read 4, iclass 39, count 0 2006.173.10:54:08.21#ibcon#read 4, iclass 39, count 0 2006.173.10:54:08.21#ibcon#about to read 5, iclass 39, count 0 2006.173.10:54:08.21#ibcon#read 5, iclass 39, count 0 2006.173.10:54:08.21#ibcon#about to read 6, iclass 39, count 0 2006.173.10:54:08.21#ibcon#read 6, iclass 39, count 0 2006.173.10:54:08.21#ibcon#end of sib2, iclass 39, count 0 2006.173.10:54:08.21#ibcon#*mode == 0, iclass 39, count 0 2006.173.10:54:08.21#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.10:54:08.21#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.10:54:08.21#ibcon#*before write, iclass 39, count 0 2006.173.10:54:08.21#ibcon#enter sib2, iclass 39, count 0 2006.173.10:54:08.21#ibcon#flushed, iclass 39, count 0 2006.173.10:54:08.21#ibcon#about to write, iclass 39, count 0 2006.173.10:54:08.21#ibcon#wrote, iclass 39, count 0 2006.173.10:54:08.21#ibcon#about to read 3, iclass 39, count 0 2006.173.10:54:08.25#ibcon#read 3, iclass 39, count 0 2006.173.10:54:08.25#ibcon#about to read 4, iclass 39, count 0 2006.173.10:54:08.25#ibcon#read 4, iclass 39, count 0 2006.173.10:54:08.25#ibcon#about to read 5, iclass 39, count 0 2006.173.10:54:08.25#ibcon#read 5, iclass 39, count 0 2006.173.10:54:08.25#ibcon#about to read 6, iclass 39, count 0 2006.173.10:54:08.25#ibcon#read 6, iclass 39, count 0 2006.173.10:54:08.25#ibcon#end of sib2, iclass 39, count 0 2006.173.10:54:08.25#ibcon#*after write, iclass 39, count 0 2006.173.10:54:08.25#ibcon#*before return 0, iclass 39, count 0 2006.173.10:54:08.25#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.10:54:08.25#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.10:54:08.25#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.10:54:08.25#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.10:54:08.25$vck44/va=7,4 2006.173.10:54:08.25#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.10:54:08.25#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.10:54:08.25#ibcon#ireg 11 cls_cnt 2 2006.173.10:54:08.25#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.10:54:08.31#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.10:54:08.31#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.10:54:08.31#ibcon#enter wrdev, iclass 3, count 2 2006.173.10:54:08.31#ibcon#first serial, iclass 3, count 2 2006.173.10:54:08.31#ibcon#enter sib2, iclass 3, count 2 2006.173.10:54:08.31#ibcon#flushed, iclass 3, count 2 2006.173.10:54:08.31#ibcon#about to write, iclass 3, count 2 2006.173.10:54:08.31#ibcon#wrote, iclass 3, count 2 2006.173.10:54:08.31#ibcon#about to read 3, iclass 3, count 2 2006.173.10:54:08.33#ibcon#read 3, iclass 3, count 2 2006.173.10:54:08.33#ibcon#about to read 4, iclass 3, count 2 2006.173.10:54:08.33#ibcon#read 4, iclass 3, count 2 2006.173.10:54:08.33#ibcon#about to read 5, iclass 3, count 2 2006.173.10:54:08.33#ibcon#read 5, iclass 3, count 2 2006.173.10:54:08.33#ibcon#about to read 6, iclass 3, count 2 2006.173.10:54:08.33#ibcon#read 6, iclass 3, count 2 2006.173.10:54:08.33#ibcon#end of sib2, iclass 3, count 2 2006.173.10:54:08.33#ibcon#*mode == 0, iclass 3, count 2 2006.173.10:54:08.33#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.10:54:08.33#ibcon#[25=AT07-04\r\n] 2006.173.10:54:08.33#ibcon#*before write, iclass 3, count 2 2006.173.10:54:08.33#ibcon#enter sib2, iclass 3, count 2 2006.173.10:54:08.33#ibcon#flushed, iclass 3, count 2 2006.173.10:54:08.33#ibcon#about to write, iclass 3, count 2 2006.173.10:54:08.33#ibcon#wrote, iclass 3, count 2 2006.173.10:54:08.33#ibcon#about to read 3, iclass 3, count 2 2006.173.10:54:08.36#ibcon#read 3, iclass 3, count 2 2006.173.10:54:08.36#ibcon#about to read 4, iclass 3, count 2 2006.173.10:54:08.36#ibcon#read 4, iclass 3, count 2 2006.173.10:54:08.36#ibcon#about to read 5, iclass 3, count 2 2006.173.10:54:08.36#ibcon#read 5, iclass 3, count 2 2006.173.10:54:08.36#ibcon#about to read 6, iclass 3, count 2 2006.173.10:54:08.36#ibcon#read 6, iclass 3, count 2 2006.173.10:54:08.36#ibcon#end of sib2, iclass 3, count 2 2006.173.10:54:08.36#ibcon#*after write, iclass 3, count 2 2006.173.10:54:08.36#ibcon#*before return 0, iclass 3, count 2 2006.173.10:54:08.36#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.10:54:08.36#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.10:54:08.36#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.10:54:08.36#ibcon#ireg 7 cls_cnt 0 2006.173.10:54:08.36#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.10:54:08.48#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.10:54:08.48#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.10:54:08.48#ibcon#enter wrdev, iclass 3, count 0 2006.173.10:54:08.48#ibcon#first serial, iclass 3, count 0 2006.173.10:54:08.48#ibcon#enter sib2, iclass 3, count 0 2006.173.10:54:08.48#ibcon#flushed, iclass 3, count 0 2006.173.10:54:08.48#ibcon#about to write, iclass 3, count 0 2006.173.10:54:08.48#ibcon#wrote, iclass 3, count 0 2006.173.10:54:08.48#ibcon#about to read 3, iclass 3, count 0 2006.173.10:54:08.50#ibcon#read 3, iclass 3, count 0 2006.173.10:54:08.50#ibcon#about to read 4, iclass 3, count 0 2006.173.10:54:08.50#ibcon#read 4, iclass 3, count 0 2006.173.10:54:08.50#ibcon#about to read 5, iclass 3, count 0 2006.173.10:54:08.50#ibcon#read 5, iclass 3, count 0 2006.173.10:54:08.50#ibcon#about to read 6, iclass 3, count 0 2006.173.10:54:08.50#ibcon#read 6, iclass 3, count 0 2006.173.10:54:08.50#ibcon#end of sib2, iclass 3, count 0 2006.173.10:54:08.50#ibcon#*mode == 0, iclass 3, count 0 2006.173.10:54:08.50#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.10:54:08.50#ibcon#[25=USB\r\n] 2006.173.10:54:08.50#ibcon#*before write, iclass 3, count 0 2006.173.10:54:08.50#ibcon#enter sib2, iclass 3, count 0 2006.173.10:54:08.50#ibcon#flushed, iclass 3, count 0 2006.173.10:54:08.50#ibcon#about to write, iclass 3, count 0 2006.173.10:54:08.50#ibcon#wrote, iclass 3, count 0 2006.173.10:54:08.50#ibcon#about to read 3, iclass 3, count 0 2006.173.10:54:08.53#ibcon#read 3, iclass 3, count 0 2006.173.10:54:08.53#ibcon#about to read 4, iclass 3, count 0 2006.173.10:54:08.53#ibcon#read 4, iclass 3, count 0 2006.173.10:54:08.53#ibcon#about to read 5, iclass 3, count 0 2006.173.10:54:08.53#ibcon#read 5, iclass 3, count 0 2006.173.10:54:08.53#ibcon#about to read 6, iclass 3, count 0 2006.173.10:54:08.53#ibcon#read 6, iclass 3, count 0 2006.173.10:54:08.53#ibcon#end of sib2, iclass 3, count 0 2006.173.10:54:08.53#ibcon#*after write, iclass 3, count 0 2006.173.10:54:08.53#ibcon#*before return 0, iclass 3, count 0 2006.173.10:54:08.53#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.10:54:08.53#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.10:54:08.53#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.10:54:08.53#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.10:54:08.53$vck44/valo=8,884.99 2006.173.10:54:08.53#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.10:54:08.53#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.10:54:08.53#ibcon#ireg 17 cls_cnt 0 2006.173.10:54:08.53#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.10:54:08.53#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.10:54:08.53#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.10:54:08.53#ibcon#enter wrdev, iclass 5, count 0 2006.173.10:54:08.53#ibcon#first serial, iclass 5, count 0 2006.173.10:54:08.53#ibcon#enter sib2, iclass 5, count 0 2006.173.10:54:08.53#ibcon#flushed, iclass 5, count 0 2006.173.10:54:08.53#ibcon#about to write, iclass 5, count 0 2006.173.10:54:08.53#ibcon#wrote, iclass 5, count 0 2006.173.10:54:08.53#ibcon#about to read 3, iclass 5, count 0 2006.173.10:54:08.55#ibcon#read 3, iclass 5, count 0 2006.173.10:54:08.55#ibcon#about to read 4, iclass 5, count 0 2006.173.10:54:08.55#ibcon#read 4, iclass 5, count 0 2006.173.10:54:08.55#ibcon#about to read 5, iclass 5, count 0 2006.173.10:54:08.55#ibcon#read 5, iclass 5, count 0 2006.173.10:54:08.55#ibcon#about to read 6, iclass 5, count 0 2006.173.10:54:08.55#ibcon#read 6, iclass 5, count 0 2006.173.10:54:08.55#ibcon#end of sib2, iclass 5, count 0 2006.173.10:54:08.55#ibcon#*mode == 0, iclass 5, count 0 2006.173.10:54:08.55#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.10:54:08.55#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.10:54:08.55#ibcon#*before write, iclass 5, count 0 2006.173.10:54:08.55#ibcon#enter sib2, iclass 5, count 0 2006.173.10:54:08.55#ibcon#flushed, iclass 5, count 0 2006.173.10:54:08.55#ibcon#about to write, iclass 5, count 0 2006.173.10:54:08.55#ibcon#wrote, iclass 5, count 0 2006.173.10:54:08.55#ibcon#about to read 3, iclass 5, count 0 2006.173.10:54:08.59#ibcon#read 3, iclass 5, count 0 2006.173.10:54:08.59#ibcon#about to read 4, iclass 5, count 0 2006.173.10:54:08.59#ibcon#read 4, iclass 5, count 0 2006.173.10:54:08.59#ibcon#about to read 5, iclass 5, count 0 2006.173.10:54:08.59#ibcon#read 5, iclass 5, count 0 2006.173.10:54:08.59#ibcon#about to read 6, iclass 5, count 0 2006.173.10:54:08.59#ibcon#read 6, iclass 5, count 0 2006.173.10:54:08.59#ibcon#end of sib2, iclass 5, count 0 2006.173.10:54:08.59#ibcon#*after write, iclass 5, count 0 2006.173.10:54:08.59#ibcon#*before return 0, iclass 5, count 0 2006.173.10:54:08.59#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.10:54:08.59#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.10:54:08.59#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.10:54:08.59#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.10:54:08.59$vck44/va=8,4 2006.173.10:54:08.59#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.173.10:54:08.59#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.173.10:54:08.59#ibcon#ireg 11 cls_cnt 2 2006.173.10:54:08.59#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.10:54:08.65#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.10:54:08.65#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.10:54:08.65#ibcon#enter wrdev, iclass 7, count 2 2006.173.10:54:08.65#ibcon#first serial, iclass 7, count 2 2006.173.10:54:08.65#ibcon#enter sib2, iclass 7, count 2 2006.173.10:54:08.65#ibcon#flushed, iclass 7, count 2 2006.173.10:54:08.65#ibcon#about to write, iclass 7, count 2 2006.173.10:54:08.65#ibcon#wrote, iclass 7, count 2 2006.173.10:54:08.65#ibcon#about to read 3, iclass 7, count 2 2006.173.10:54:08.67#ibcon#read 3, iclass 7, count 2 2006.173.10:54:08.67#ibcon#about to read 4, iclass 7, count 2 2006.173.10:54:08.67#ibcon#read 4, iclass 7, count 2 2006.173.10:54:08.67#ibcon#about to read 5, iclass 7, count 2 2006.173.10:54:08.67#ibcon#read 5, iclass 7, count 2 2006.173.10:54:08.67#ibcon#about to read 6, iclass 7, count 2 2006.173.10:54:08.67#ibcon#read 6, iclass 7, count 2 2006.173.10:54:08.67#ibcon#end of sib2, iclass 7, count 2 2006.173.10:54:08.67#ibcon#*mode == 0, iclass 7, count 2 2006.173.10:54:08.67#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.173.10:54:08.67#ibcon#[25=AT08-04\r\n] 2006.173.10:54:08.67#ibcon#*before write, iclass 7, count 2 2006.173.10:54:08.67#ibcon#enter sib2, iclass 7, count 2 2006.173.10:54:08.67#ibcon#flushed, iclass 7, count 2 2006.173.10:54:08.67#ibcon#about to write, iclass 7, count 2 2006.173.10:54:08.67#ibcon#wrote, iclass 7, count 2 2006.173.10:54:08.67#ibcon#about to read 3, iclass 7, count 2 2006.173.10:54:08.70#ibcon#read 3, iclass 7, count 2 2006.173.10:54:08.70#ibcon#about to read 4, iclass 7, count 2 2006.173.10:54:08.70#ibcon#read 4, iclass 7, count 2 2006.173.10:54:08.70#ibcon#about to read 5, iclass 7, count 2 2006.173.10:54:08.70#ibcon#read 5, iclass 7, count 2 2006.173.10:54:08.70#ibcon#about to read 6, iclass 7, count 2 2006.173.10:54:08.70#ibcon#read 6, iclass 7, count 2 2006.173.10:54:08.70#ibcon#end of sib2, iclass 7, count 2 2006.173.10:54:08.70#ibcon#*after write, iclass 7, count 2 2006.173.10:54:08.70#ibcon#*before return 0, iclass 7, count 2 2006.173.10:54:08.70#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.10:54:08.70#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.173.10:54:08.70#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.173.10:54:08.70#ibcon#ireg 7 cls_cnt 0 2006.173.10:54:08.70#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.10:54:08.82#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.10:54:08.82#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.10:54:08.82#ibcon#enter wrdev, iclass 7, count 0 2006.173.10:54:08.82#ibcon#first serial, iclass 7, count 0 2006.173.10:54:08.82#ibcon#enter sib2, iclass 7, count 0 2006.173.10:54:08.82#ibcon#flushed, iclass 7, count 0 2006.173.10:54:08.82#ibcon#about to write, iclass 7, count 0 2006.173.10:54:08.82#ibcon#wrote, iclass 7, count 0 2006.173.10:54:08.82#ibcon#about to read 3, iclass 7, count 0 2006.173.10:54:08.84#ibcon#read 3, iclass 7, count 0 2006.173.10:54:08.84#ibcon#about to read 4, iclass 7, count 0 2006.173.10:54:08.84#ibcon#read 4, iclass 7, count 0 2006.173.10:54:08.84#ibcon#about to read 5, iclass 7, count 0 2006.173.10:54:08.84#ibcon#read 5, iclass 7, count 0 2006.173.10:54:08.84#ibcon#about to read 6, iclass 7, count 0 2006.173.10:54:08.84#ibcon#read 6, iclass 7, count 0 2006.173.10:54:08.84#ibcon#end of sib2, iclass 7, count 0 2006.173.10:54:08.84#ibcon#*mode == 0, iclass 7, count 0 2006.173.10:54:08.84#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.10:54:08.84#ibcon#[25=USB\r\n] 2006.173.10:54:08.84#ibcon#*before write, iclass 7, count 0 2006.173.10:54:08.84#ibcon#enter sib2, iclass 7, count 0 2006.173.10:54:08.84#ibcon#flushed, iclass 7, count 0 2006.173.10:54:08.84#ibcon#about to write, iclass 7, count 0 2006.173.10:54:08.84#ibcon#wrote, iclass 7, count 0 2006.173.10:54:08.84#ibcon#about to read 3, iclass 7, count 0 2006.173.10:54:08.87#ibcon#read 3, iclass 7, count 0 2006.173.10:54:08.87#ibcon#about to read 4, iclass 7, count 0 2006.173.10:54:08.87#ibcon#read 4, iclass 7, count 0 2006.173.10:54:08.87#ibcon#about to read 5, iclass 7, count 0 2006.173.10:54:08.87#ibcon#read 5, iclass 7, count 0 2006.173.10:54:08.87#ibcon#about to read 6, iclass 7, count 0 2006.173.10:54:08.87#ibcon#read 6, iclass 7, count 0 2006.173.10:54:08.87#ibcon#end of sib2, iclass 7, count 0 2006.173.10:54:08.87#ibcon#*after write, iclass 7, count 0 2006.173.10:54:08.87#ibcon#*before return 0, iclass 7, count 0 2006.173.10:54:08.87#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.10:54:08.87#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.173.10:54:08.87#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.10:54:08.87#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.10:54:08.87$vck44/vblo=1,629.99 2006.173.10:54:08.87#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.10:54:08.87#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.10:54:08.87#ibcon#ireg 17 cls_cnt 0 2006.173.10:54:08.87#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.10:54:08.87#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.10:54:08.87#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.10:54:08.87#ibcon#enter wrdev, iclass 11, count 0 2006.173.10:54:08.87#ibcon#first serial, iclass 11, count 0 2006.173.10:54:08.87#ibcon#enter sib2, iclass 11, count 0 2006.173.10:54:08.87#ibcon#flushed, iclass 11, count 0 2006.173.10:54:08.87#ibcon#about to write, iclass 11, count 0 2006.173.10:54:08.87#ibcon#wrote, iclass 11, count 0 2006.173.10:54:08.87#ibcon#about to read 3, iclass 11, count 0 2006.173.10:54:08.89#ibcon#read 3, iclass 11, count 0 2006.173.10:54:08.89#ibcon#about to read 4, iclass 11, count 0 2006.173.10:54:08.89#ibcon#read 4, iclass 11, count 0 2006.173.10:54:08.89#ibcon#about to read 5, iclass 11, count 0 2006.173.10:54:08.89#ibcon#read 5, iclass 11, count 0 2006.173.10:54:08.89#ibcon#about to read 6, iclass 11, count 0 2006.173.10:54:08.89#ibcon#read 6, iclass 11, count 0 2006.173.10:54:08.89#ibcon#end of sib2, iclass 11, count 0 2006.173.10:54:08.89#ibcon#*mode == 0, iclass 11, count 0 2006.173.10:54:08.89#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.10:54:08.89#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.10:54:08.89#ibcon#*before write, iclass 11, count 0 2006.173.10:54:08.89#ibcon#enter sib2, iclass 11, count 0 2006.173.10:54:08.89#ibcon#flushed, iclass 11, count 0 2006.173.10:54:08.89#ibcon#about to write, iclass 11, count 0 2006.173.10:54:08.89#ibcon#wrote, iclass 11, count 0 2006.173.10:54:08.89#ibcon#about to read 3, iclass 11, count 0 2006.173.10:54:08.93#ibcon#read 3, iclass 11, count 0 2006.173.10:54:08.93#ibcon#about to read 4, iclass 11, count 0 2006.173.10:54:08.93#ibcon#read 4, iclass 11, count 0 2006.173.10:54:08.93#ibcon#about to read 5, iclass 11, count 0 2006.173.10:54:08.93#ibcon#read 5, iclass 11, count 0 2006.173.10:54:08.93#ibcon#about to read 6, iclass 11, count 0 2006.173.10:54:08.93#ibcon#read 6, iclass 11, count 0 2006.173.10:54:08.93#ibcon#end of sib2, iclass 11, count 0 2006.173.10:54:08.93#ibcon#*after write, iclass 11, count 0 2006.173.10:54:08.93#ibcon#*before return 0, iclass 11, count 0 2006.173.10:54:08.93#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.10:54:08.93#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.10:54:08.93#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.10:54:08.93#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.10:54:08.93$vck44/vb=1,4 2006.173.10:54:08.93#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.173.10:54:08.93#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.173.10:54:08.93#ibcon#ireg 11 cls_cnt 2 2006.173.10:54:08.93#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.10:54:08.93#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.10:54:08.93#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.10:54:08.93#ibcon#enter wrdev, iclass 13, count 2 2006.173.10:54:08.93#ibcon#first serial, iclass 13, count 2 2006.173.10:54:08.93#ibcon#enter sib2, iclass 13, count 2 2006.173.10:54:08.93#ibcon#flushed, iclass 13, count 2 2006.173.10:54:08.93#ibcon#about to write, iclass 13, count 2 2006.173.10:54:08.93#ibcon#wrote, iclass 13, count 2 2006.173.10:54:08.93#ibcon#about to read 3, iclass 13, count 2 2006.173.10:54:08.95#ibcon#read 3, iclass 13, count 2 2006.173.10:54:08.95#ibcon#about to read 4, iclass 13, count 2 2006.173.10:54:08.95#ibcon#read 4, iclass 13, count 2 2006.173.10:54:08.95#ibcon#about to read 5, iclass 13, count 2 2006.173.10:54:08.95#ibcon#read 5, iclass 13, count 2 2006.173.10:54:08.95#ibcon#about to read 6, iclass 13, count 2 2006.173.10:54:08.95#ibcon#read 6, iclass 13, count 2 2006.173.10:54:08.95#ibcon#end of sib2, iclass 13, count 2 2006.173.10:54:08.95#ibcon#*mode == 0, iclass 13, count 2 2006.173.10:54:08.95#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.173.10:54:08.95#ibcon#[27=AT01-04\r\n] 2006.173.10:54:08.95#ibcon#*before write, iclass 13, count 2 2006.173.10:54:08.95#ibcon#enter sib2, iclass 13, count 2 2006.173.10:54:08.95#ibcon#flushed, iclass 13, count 2 2006.173.10:54:08.95#ibcon#about to write, iclass 13, count 2 2006.173.10:54:08.95#ibcon#wrote, iclass 13, count 2 2006.173.10:54:08.95#ibcon#about to read 3, iclass 13, count 2 2006.173.10:54:08.98#ibcon#read 3, iclass 13, count 2 2006.173.10:54:08.98#ibcon#about to read 4, iclass 13, count 2 2006.173.10:54:08.98#ibcon#read 4, iclass 13, count 2 2006.173.10:54:08.98#ibcon#about to read 5, iclass 13, count 2 2006.173.10:54:08.98#ibcon#read 5, iclass 13, count 2 2006.173.10:54:08.98#ibcon#about to read 6, iclass 13, count 2 2006.173.10:54:08.98#ibcon#read 6, iclass 13, count 2 2006.173.10:54:08.98#ibcon#end of sib2, iclass 13, count 2 2006.173.10:54:08.98#ibcon#*after write, iclass 13, count 2 2006.173.10:54:08.98#ibcon#*before return 0, iclass 13, count 2 2006.173.10:54:08.98#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.10:54:08.98#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.173.10:54:08.98#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.173.10:54:08.98#ibcon#ireg 7 cls_cnt 0 2006.173.10:54:08.98#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.10:54:09.01#abcon#<5=/04 0.7 1.8 22.59 921003.9\r\n> 2006.173.10:54:09.03#abcon#{5=INTERFACE CLEAR} 2006.173.10:54:09.09#abcon#[5=S1D000X0/0*\r\n] 2006.173.10:54:09.10#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.10:54:09.10#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.10:54:09.10#ibcon#enter wrdev, iclass 13, count 0 2006.173.10:54:09.10#ibcon#first serial, iclass 13, count 0 2006.173.10:54:09.10#ibcon#enter sib2, iclass 13, count 0 2006.173.10:54:09.10#ibcon#flushed, iclass 13, count 0 2006.173.10:54:09.10#ibcon#about to write, iclass 13, count 0 2006.173.10:54:09.10#ibcon#wrote, iclass 13, count 0 2006.173.10:54:09.10#ibcon#about to read 3, iclass 13, count 0 2006.173.10:54:09.12#ibcon#read 3, iclass 13, count 0 2006.173.10:54:09.12#ibcon#about to read 4, iclass 13, count 0 2006.173.10:54:09.12#ibcon#read 4, iclass 13, count 0 2006.173.10:54:09.12#ibcon#about to read 5, iclass 13, count 0 2006.173.10:54:09.12#ibcon#read 5, iclass 13, count 0 2006.173.10:54:09.12#ibcon#about to read 6, iclass 13, count 0 2006.173.10:54:09.12#ibcon#read 6, iclass 13, count 0 2006.173.10:54:09.12#ibcon#end of sib2, iclass 13, count 0 2006.173.10:54:09.12#ibcon#*mode == 0, iclass 13, count 0 2006.173.10:54:09.12#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.10:54:09.12#ibcon#[27=USB\r\n] 2006.173.10:54:09.12#ibcon#*before write, iclass 13, count 0 2006.173.10:54:09.12#ibcon#enter sib2, iclass 13, count 0 2006.173.10:54:09.12#ibcon#flushed, iclass 13, count 0 2006.173.10:54:09.12#ibcon#about to write, iclass 13, count 0 2006.173.10:54:09.12#ibcon#wrote, iclass 13, count 0 2006.173.10:54:09.12#ibcon#about to read 3, iclass 13, count 0 2006.173.10:54:09.15#ibcon#read 3, iclass 13, count 0 2006.173.10:54:09.15#ibcon#about to read 4, iclass 13, count 0 2006.173.10:54:09.15#ibcon#read 4, iclass 13, count 0 2006.173.10:54:09.15#ibcon#about to read 5, iclass 13, count 0 2006.173.10:54:09.15#ibcon#read 5, iclass 13, count 0 2006.173.10:54:09.15#ibcon#about to read 6, iclass 13, count 0 2006.173.10:54:09.15#ibcon#read 6, iclass 13, count 0 2006.173.10:54:09.15#ibcon#end of sib2, iclass 13, count 0 2006.173.10:54:09.15#ibcon#*after write, iclass 13, count 0 2006.173.10:54:09.15#ibcon#*before return 0, iclass 13, count 0 2006.173.10:54:09.15#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.10:54:09.15#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.173.10:54:09.15#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.10:54:09.15#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.10:54:09.15$vck44/vblo=2,634.99 2006.173.10:54:09.15#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.10:54:09.15#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.10:54:09.15#ibcon#ireg 17 cls_cnt 0 2006.173.10:54:09.15#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.10:54:09.15#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.10:54:09.15#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.10:54:09.15#ibcon#enter wrdev, iclass 19, count 0 2006.173.10:54:09.15#ibcon#first serial, iclass 19, count 0 2006.173.10:54:09.15#ibcon#enter sib2, iclass 19, count 0 2006.173.10:54:09.15#ibcon#flushed, iclass 19, count 0 2006.173.10:54:09.15#ibcon#about to write, iclass 19, count 0 2006.173.10:54:09.15#ibcon#wrote, iclass 19, count 0 2006.173.10:54:09.15#ibcon#about to read 3, iclass 19, count 0 2006.173.10:54:09.17#ibcon#read 3, iclass 19, count 0 2006.173.10:54:09.17#ibcon#about to read 4, iclass 19, count 0 2006.173.10:54:09.17#ibcon#read 4, iclass 19, count 0 2006.173.10:54:09.17#ibcon#about to read 5, iclass 19, count 0 2006.173.10:54:09.17#ibcon#read 5, iclass 19, count 0 2006.173.10:54:09.17#ibcon#about to read 6, iclass 19, count 0 2006.173.10:54:09.17#ibcon#read 6, iclass 19, count 0 2006.173.10:54:09.17#ibcon#end of sib2, iclass 19, count 0 2006.173.10:54:09.17#ibcon#*mode == 0, iclass 19, count 0 2006.173.10:54:09.17#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.10:54:09.17#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.10:54:09.17#ibcon#*before write, iclass 19, count 0 2006.173.10:54:09.17#ibcon#enter sib2, iclass 19, count 0 2006.173.10:54:09.17#ibcon#flushed, iclass 19, count 0 2006.173.10:54:09.17#ibcon#about to write, iclass 19, count 0 2006.173.10:54:09.17#ibcon#wrote, iclass 19, count 0 2006.173.10:54:09.17#ibcon#about to read 3, iclass 19, count 0 2006.173.10:54:09.21#ibcon#read 3, iclass 19, count 0 2006.173.10:54:09.21#ibcon#about to read 4, iclass 19, count 0 2006.173.10:54:09.21#ibcon#read 4, iclass 19, count 0 2006.173.10:54:09.21#ibcon#about to read 5, iclass 19, count 0 2006.173.10:54:09.21#ibcon#read 5, iclass 19, count 0 2006.173.10:54:09.21#ibcon#about to read 6, iclass 19, count 0 2006.173.10:54:09.21#ibcon#read 6, iclass 19, count 0 2006.173.10:54:09.21#ibcon#end of sib2, iclass 19, count 0 2006.173.10:54:09.21#ibcon#*after write, iclass 19, count 0 2006.173.10:54:09.21#ibcon#*before return 0, iclass 19, count 0 2006.173.10:54:09.21#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.10:54:09.21#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.10:54:09.21#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.10:54:09.21#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.10:54:09.21$vck44/vb=2,4 2006.173.10:54:09.21#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.10:54:09.21#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.10:54:09.21#ibcon#ireg 11 cls_cnt 2 2006.173.10:54:09.21#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.10:54:09.27#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.10:54:09.27#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.10:54:09.27#ibcon#enter wrdev, iclass 21, count 2 2006.173.10:54:09.27#ibcon#first serial, iclass 21, count 2 2006.173.10:54:09.27#ibcon#enter sib2, iclass 21, count 2 2006.173.10:54:09.27#ibcon#flushed, iclass 21, count 2 2006.173.10:54:09.27#ibcon#about to write, iclass 21, count 2 2006.173.10:54:09.27#ibcon#wrote, iclass 21, count 2 2006.173.10:54:09.27#ibcon#about to read 3, iclass 21, count 2 2006.173.10:54:09.29#ibcon#read 3, iclass 21, count 2 2006.173.10:54:09.29#ibcon#about to read 4, iclass 21, count 2 2006.173.10:54:09.29#ibcon#read 4, iclass 21, count 2 2006.173.10:54:09.29#ibcon#about to read 5, iclass 21, count 2 2006.173.10:54:09.29#ibcon#read 5, iclass 21, count 2 2006.173.10:54:09.29#ibcon#about to read 6, iclass 21, count 2 2006.173.10:54:09.29#ibcon#read 6, iclass 21, count 2 2006.173.10:54:09.29#ibcon#end of sib2, iclass 21, count 2 2006.173.10:54:09.29#ibcon#*mode == 0, iclass 21, count 2 2006.173.10:54:09.29#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.10:54:09.29#ibcon#[27=AT02-04\r\n] 2006.173.10:54:09.29#ibcon#*before write, iclass 21, count 2 2006.173.10:54:09.29#ibcon#enter sib2, iclass 21, count 2 2006.173.10:54:09.29#ibcon#flushed, iclass 21, count 2 2006.173.10:54:09.29#ibcon#about to write, iclass 21, count 2 2006.173.10:54:09.29#ibcon#wrote, iclass 21, count 2 2006.173.10:54:09.29#ibcon#about to read 3, iclass 21, count 2 2006.173.10:54:09.32#ibcon#read 3, iclass 21, count 2 2006.173.10:54:09.32#ibcon#about to read 4, iclass 21, count 2 2006.173.10:54:09.32#ibcon#read 4, iclass 21, count 2 2006.173.10:54:09.32#ibcon#about to read 5, iclass 21, count 2 2006.173.10:54:09.32#ibcon#read 5, iclass 21, count 2 2006.173.10:54:09.32#ibcon#about to read 6, iclass 21, count 2 2006.173.10:54:09.32#ibcon#read 6, iclass 21, count 2 2006.173.10:54:09.32#ibcon#end of sib2, iclass 21, count 2 2006.173.10:54:09.32#ibcon#*after write, iclass 21, count 2 2006.173.10:54:09.32#ibcon#*before return 0, iclass 21, count 2 2006.173.10:54:09.32#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.10:54:09.32#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.10:54:09.32#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.10:54:09.32#ibcon#ireg 7 cls_cnt 0 2006.173.10:54:09.32#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.10:54:09.44#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.10:54:09.44#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.10:54:09.44#ibcon#enter wrdev, iclass 21, count 0 2006.173.10:54:09.44#ibcon#first serial, iclass 21, count 0 2006.173.10:54:09.44#ibcon#enter sib2, iclass 21, count 0 2006.173.10:54:09.44#ibcon#flushed, iclass 21, count 0 2006.173.10:54:09.44#ibcon#about to write, iclass 21, count 0 2006.173.10:54:09.44#ibcon#wrote, iclass 21, count 0 2006.173.10:54:09.44#ibcon#about to read 3, iclass 21, count 0 2006.173.10:54:09.46#ibcon#read 3, iclass 21, count 0 2006.173.10:54:09.46#ibcon#about to read 4, iclass 21, count 0 2006.173.10:54:09.46#ibcon#read 4, iclass 21, count 0 2006.173.10:54:09.46#ibcon#about to read 5, iclass 21, count 0 2006.173.10:54:09.46#ibcon#read 5, iclass 21, count 0 2006.173.10:54:09.46#ibcon#about to read 6, iclass 21, count 0 2006.173.10:54:09.46#ibcon#read 6, iclass 21, count 0 2006.173.10:54:09.46#ibcon#end of sib2, iclass 21, count 0 2006.173.10:54:09.46#ibcon#*mode == 0, iclass 21, count 0 2006.173.10:54:09.46#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.10:54:09.46#ibcon#[27=USB\r\n] 2006.173.10:54:09.46#ibcon#*before write, iclass 21, count 0 2006.173.10:54:09.46#ibcon#enter sib2, iclass 21, count 0 2006.173.10:54:09.46#ibcon#flushed, iclass 21, count 0 2006.173.10:54:09.46#ibcon#about to write, iclass 21, count 0 2006.173.10:54:09.46#ibcon#wrote, iclass 21, count 0 2006.173.10:54:09.46#ibcon#about to read 3, iclass 21, count 0 2006.173.10:54:09.49#ibcon#read 3, iclass 21, count 0 2006.173.10:54:09.49#ibcon#about to read 4, iclass 21, count 0 2006.173.10:54:09.49#ibcon#read 4, iclass 21, count 0 2006.173.10:54:09.49#ibcon#about to read 5, iclass 21, count 0 2006.173.10:54:09.49#ibcon#read 5, iclass 21, count 0 2006.173.10:54:09.49#ibcon#about to read 6, iclass 21, count 0 2006.173.10:54:09.49#ibcon#read 6, iclass 21, count 0 2006.173.10:54:09.49#ibcon#end of sib2, iclass 21, count 0 2006.173.10:54:09.49#ibcon#*after write, iclass 21, count 0 2006.173.10:54:09.49#ibcon#*before return 0, iclass 21, count 0 2006.173.10:54:09.49#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.10:54:09.49#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.10:54:09.49#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.10:54:09.49#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.10:54:09.49$vck44/vblo=3,649.99 2006.173.10:54:09.49#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.10:54:09.49#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.10:54:09.49#ibcon#ireg 17 cls_cnt 0 2006.173.10:54:09.49#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.10:54:09.49#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.10:54:09.49#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.10:54:09.49#ibcon#enter wrdev, iclass 23, count 0 2006.173.10:54:09.49#ibcon#first serial, iclass 23, count 0 2006.173.10:54:09.49#ibcon#enter sib2, iclass 23, count 0 2006.173.10:54:09.49#ibcon#flushed, iclass 23, count 0 2006.173.10:54:09.49#ibcon#about to write, iclass 23, count 0 2006.173.10:54:09.49#ibcon#wrote, iclass 23, count 0 2006.173.10:54:09.49#ibcon#about to read 3, iclass 23, count 0 2006.173.10:54:09.51#ibcon#read 3, iclass 23, count 0 2006.173.10:54:09.51#ibcon#about to read 4, iclass 23, count 0 2006.173.10:54:09.51#ibcon#read 4, iclass 23, count 0 2006.173.10:54:09.51#ibcon#about to read 5, iclass 23, count 0 2006.173.10:54:09.51#ibcon#read 5, iclass 23, count 0 2006.173.10:54:09.51#ibcon#about to read 6, iclass 23, count 0 2006.173.10:54:09.51#ibcon#read 6, iclass 23, count 0 2006.173.10:54:09.51#ibcon#end of sib2, iclass 23, count 0 2006.173.10:54:09.51#ibcon#*mode == 0, iclass 23, count 0 2006.173.10:54:09.51#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.10:54:09.51#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.10:54:09.51#ibcon#*before write, iclass 23, count 0 2006.173.10:54:09.51#ibcon#enter sib2, iclass 23, count 0 2006.173.10:54:09.51#ibcon#flushed, iclass 23, count 0 2006.173.10:54:09.51#ibcon#about to write, iclass 23, count 0 2006.173.10:54:09.51#ibcon#wrote, iclass 23, count 0 2006.173.10:54:09.51#ibcon#about to read 3, iclass 23, count 0 2006.173.10:54:09.55#ibcon#read 3, iclass 23, count 0 2006.173.10:54:09.55#ibcon#about to read 4, iclass 23, count 0 2006.173.10:54:09.55#ibcon#read 4, iclass 23, count 0 2006.173.10:54:09.55#ibcon#about to read 5, iclass 23, count 0 2006.173.10:54:09.55#ibcon#read 5, iclass 23, count 0 2006.173.10:54:09.55#ibcon#about to read 6, iclass 23, count 0 2006.173.10:54:09.55#ibcon#read 6, iclass 23, count 0 2006.173.10:54:09.55#ibcon#end of sib2, iclass 23, count 0 2006.173.10:54:09.55#ibcon#*after write, iclass 23, count 0 2006.173.10:54:09.55#ibcon#*before return 0, iclass 23, count 0 2006.173.10:54:09.55#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.10:54:09.55#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.10:54:09.55#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.10:54:09.55#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.10:54:09.55$vck44/vb=3,4 2006.173.10:54:09.55#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.10:54:09.55#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.10:54:09.55#ibcon#ireg 11 cls_cnt 2 2006.173.10:54:09.55#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.10:54:09.61#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.10:54:09.61#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.10:54:09.61#ibcon#enter wrdev, iclass 25, count 2 2006.173.10:54:09.61#ibcon#first serial, iclass 25, count 2 2006.173.10:54:09.61#ibcon#enter sib2, iclass 25, count 2 2006.173.10:54:09.61#ibcon#flushed, iclass 25, count 2 2006.173.10:54:09.61#ibcon#about to write, iclass 25, count 2 2006.173.10:54:09.61#ibcon#wrote, iclass 25, count 2 2006.173.10:54:09.61#ibcon#about to read 3, iclass 25, count 2 2006.173.10:54:09.63#ibcon#read 3, iclass 25, count 2 2006.173.10:54:09.63#ibcon#about to read 4, iclass 25, count 2 2006.173.10:54:09.63#ibcon#read 4, iclass 25, count 2 2006.173.10:54:09.63#ibcon#about to read 5, iclass 25, count 2 2006.173.10:54:09.63#ibcon#read 5, iclass 25, count 2 2006.173.10:54:09.63#ibcon#about to read 6, iclass 25, count 2 2006.173.10:54:09.63#ibcon#read 6, iclass 25, count 2 2006.173.10:54:09.63#ibcon#end of sib2, iclass 25, count 2 2006.173.10:54:09.63#ibcon#*mode == 0, iclass 25, count 2 2006.173.10:54:09.63#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.10:54:09.63#ibcon#[27=AT03-04\r\n] 2006.173.10:54:09.63#ibcon#*before write, iclass 25, count 2 2006.173.10:54:09.63#ibcon#enter sib2, iclass 25, count 2 2006.173.10:54:09.63#ibcon#flushed, iclass 25, count 2 2006.173.10:54:09.63#ibcon#about to write, iclass 25, count 2 2006.173.10:54:09.63#ibcon#wrote, iclass 25, count 2 2006.173.10:54:09.63#ibcon#about to read 3, iclass 25, count 2 2006.173.10:54:09.66#ibcon#read 3, iclass 25, count 2 2006.173.10:54:09.66#ibcon#about to read 4, iclass 25, count 2 2006.173.10:54:09.66#ibcon#read 4, iclass 25, count 2 2006.173.10:54:09.66#ibcon#about to read 5, iclass 25, count 2 2006.173.10:54:09.66#ibcon#read 5, iclass 25, count 2 2006.173.10:54:09.66#ibcon#about to read 6, iclass 25, count 2 2006.173.10:54:09.66#ibcon#read 6, iclass 25, count 2 2006.173.10:54:09.66#ibcon#end of sib2, iclass 25, count 2 2006.173.10:54:09.66#ibcon#*after write, iclass 25, count 2 2006.173.10:54:09.66#ibcon#*before return 0, iclass 25, count 2 2006.173.10:54:09.66#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.10:54:09.66#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.10:54:09.66#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.10:54:09.66#ibcon#ireg 7 cls_cnt 0 2006.173.10:54:09.66#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.10:54:09.78#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.10:54:09.78#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.10:54:09.78#ibcon#enter wrdev, iclass 25, count 0 2006.173.10:54:09.78#ibcon#first serial, iclass 25, count 0 2006.173.10:54:09.78#ibcon#enter sib2, iclass 25, count 0 2006.173.10:54:09.78#ibcon#flushed, iclass 25, count 0 2006.173.10:54:09.78#ibcon#about to write, iclass 25, count 0 2006.173.10:54:09.78#ibcon#wrote, iclass 25, count 0 2006.173.10:54:09.78#ibcon#about to read 3, iclass 25, count 0 2006.173.10:54:09.80#ibcon#read 3, iclass 25, count 0 2006.173.10:54:09.80#ibcon#about to read 4, iclass 25, count 0 2006.173.10:54:09.80#ibcon#read 4, iclass 25, count 0 2006.173.10:54:09.80#ibcon#about to read 5, iclass 25, count 0 2006.173.10:54:09.80#ibcon#read 5, iclass 25, count 0 2006.173.10:54:09.80#ibcon#about to read 6, iclass 25, count 0 2006.173.10:54:09.80#ibcon#read 6, iclass 25, count 0 2006.173.10:54:09.80#ibcon#end of sib2, iclass 25, count 0 2006.173.10:54:09.80#ibcon#*mode == 0, iclass 25, count 0 2006.173.10:54:09.80#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.10:54:09.80#ibcon#[27=USB\r\n] 2006.173.10:54:09.80#ibcon#*before write, iclass 25, count 0 2006.173.10:54:09.80#ibcon#enter sib2, iclass 25, count 0 2006.173.10:54:09.80#ibcon#flushed, iclass 25, count 0 2006.173.10:54:09.80#ibcon#about to write, iclass 25, count 0 2006.173.10:54:09.80#ibcon#wrote, iclass 25, count 0 2006.173.10:54:09.80#ibcon#about to read 3, iclass 25, count 0 2006.173.10:54:09.83#ibcon#read 3, iclass 25, count 0 2006.173.10:54:09.83#ibcon#about to read 4, iclass 25, count 0 2006.173.10:54:09.83#ibcon#read 4, iclass 25, count 0 2006.173.10:54:09.83#ibcon#about to read 5, iclass 25, count 0 2006.173.10:54:09.83#ibcon#read 5, iclass 25, count 0 2006.173.10:54:09.83#ibcon#about to read 6, iclass 25, count 0 2006.173.10:54:09.83#ibcon#read 6, iclass 25, count 0 2006.173.10:54:09.83#ibcon#end of sib2, iclass 25, count 0 2006.173.10:54:09.83#ibcon#*after write, iclass 25, count 0 2006.173.10:54:09.83#ibcon#*before return 0, iclass 25, count 0 2006.173.10:54:09.83#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.10:54:09.83#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.10:54:09.83#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.10:54:09.83#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.10:54:09.83$vck44/vblo=4,679.99 2006.173.10:54:09.83#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.10:54:09.83#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.10:54:09.83#ibcon#ireg 17 cls_cnt 0 2006.173.10:54:09.83#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.10:54:09.83#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.10:54:09.83#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.10:54:09.83#ibcon#enter wrdev, iclass 27, count 0 2006.173.10:54:09.83#ibcon#first serial, iclass 27, count 0 2006.173.10:54:09.83#ibcon#enter sib2, iclass 27, count 0 2006.173.10:54:09.83#ibcon#flushed, iclass 27, count 0 2006.173.10:54:09.83#ibcon#about to write, iclass 27, count 0 2006.173.10:54:09.83#ibcon#wrote, iclass 27, count 0 2006.173.10:54:09.83#ibcon#about to read 3, iclass 27, count 0 2006.173.10:54:09.85#ibcon#read 3, iclass 27, count 0 2006.173.10:54:09.85#ibcon#about to read 4, iclass 27, count 0 2006.173.10:54:09.85#ibcon#read 4, iclass 27, count 0 2006.173.10:54:09.85#ibcon#about to read 5, iclass 27, count 0 2006.173.10:54:09.85#ibcon#read 5, iclass 27, count 0 2006.173.10:54:09.85#ibcon#about to read 6, iclass 27, count 0 2006.173.10:54:09.85#ibcon#read 6, iclass 27, count 0 2006.173.10:54:09.85#ibcon#end of sib2, iclass 27, count 0 2006.173.10:54:09.85#ibcon#*mode == 0, iclass 27, count 0 2006.173.10:54:09.85#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.10:54:09.85#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.10:54:09.85#ibcon#*before write, iclass 27, count 0 2006.173.10:54:09.85#ibcon#enter sib2, iclass 27, count 0 2006.173.10:54:09.85#ibcon#flushed, iclass 27, count 0 2006.173.10:54:09.85#ibcon#about to write, iclass 27, count 0 2006.173.10:54:09.85#ibcon#wrote, iclass 27, count 0 2006.173.10:54:09.85#ibcon#about to read 3, iclass 27, count 0 2006.173.10:54:09.89#ibcon#read 3, iclass 27, count 0 2006.173.10:54:09.89#ibcon#about to read 4, iclass 27, count 0 2006.173.10:54:09.89#ibcon#read 4, iclass 27, count 0 2006.173.10:54:09.89#ibcon#about to read 5, iclass 27, count 0 2006.173.10:54:09.89#ibcon#read 5, iclass 27, count 0 2006.173.10:54:09.89#ibcon#about to read 6, iclass 27, count 0 2006.173.10:54:09.89#ibcon#read 6, iclass 27, count 0 2006.173.10:54:09.89#ibcon#end of sib2, iclass 27, count 0 2006.173.10:54:09.89#ibcon#*after write, iclass 27, count 0 2006.173.10:54:09.89#ibcon#*before return 0, iclass 27, count 0 2006.173.10:54:09.89#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.10:54:09.89#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.10:54:09.89#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.10:54:09.89#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.10:54:09.89$vck44/vb=4,4 2006.173.10:54:09.89#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.10:54:09.89#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.10:54:09.89#ibcon#ireg 11 cls_cnt 2 2006.173.10:54:09.89#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.10:54:09.95#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.10:54:09.95#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.10:54:09.95#ibcon#enter wrdev, iclass 29, count 2 2006.173.10:54:09.95#ibcon#first serial, iclass 29, count 2 2006.173.10:54:09.95#ibcon#enter sib2, iclass 29, count 2 2006.173.10:54:09.95#ibcon#flushed, iclass 29, count 2 2006.173.10:54:09.95#ibcon#about to write, iclass 29, count 2 2006.173.10:54:09.95#ibcon#wrote, iclass 29, count 2 2006.173.10:54:09.95#ibcon#about to read 3, iclass 29, count 2 2006.173.10:54:09.97#ibcon#read 3, iclass 29, count 2 2006.173.10:54:09.97#ibcon#about to read 4, iclass 29, count 2 2006.173.10:54:09.97#ibcon#read 4, iclass 29, count 2 2006.173.10:54:09.97#ibcon#about to read 5, iclass 29, count 2 2006.173.10:54:09.97#ibcon#read 5, iclass 29, count 2 2006.173.10:54:09.97#ibcon#about to read 6, iclass 29, count 2 2006.173.10:54:09.97#ibcon#read 6, iclass 29, count 2 2006.173.10:54:09.97#ibcon#end of sib2, iclass 29, count 2 2006.173.10:54:09.97#ibcon#*mode == 0, iclass 29, count 2 2006.173.10:54:09.97#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.10:54:09.97#ibcon#[27=AT04-04\r\n] 2006.173.10:54:09.97#ibcon#*before write, iclass 29, count 2 2006.173.10:54:09.97#ibcon#enter sib2, iclass 29, count 2 2006.173.10:54:09.97#ibcon#flushed, iclass 29, count 2 2006.173.10:54:09.97#ibcon#about to write, iclass 29, count 2 2006.173.10:54:09.97#ibcon#wrote, iclass 29, count 2 2006.173.10:54:09.97#ibcon#about to read 3, iclass 29, count 2 2006.173.10:54:10.00#ibcon#read 3, iclass 29, count 2 2006.173.10:54:10.00#ibcon#about to read 4, iclass 29, count 2 2006.173.10:54:10.00#ibcon#read 4, iclass 29, count 2 2006.173.10:54:10.00#ibcon#about to read 5, iclass 29, count 2 2006.173.10:54:10.00#ibcon#read 5, iclass 29, count 2 2006.173.10:54:10.00#ibcon#about to read 6, iclass 29, count 2 2006.173.10:54:10.00#ibcon#read 6, iclass 29, count 2 2006.173.10:54:10.00#ibcon#end of sib2, iclass 29, count 2 2006.173.10:54:10.00#ibcon#*after write, iclass 29, count 2 2006.173.10:54:10.00#ibcon#*before return 0, iclass 29, count 2 2006.173.10:54:10.00#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.10:54:10.00#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.10:54:10.00#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.10:54:10.00#ibcon#ireg 7 cls_cnt 0 2006.173.10:54:10.00#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.10:54:10.12#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.10:54:10.12#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.10:54:10.12#ibcon#enter wrdev, iclass 29, count 0 2006.173.10:54:10.12#ibcon#first serial, iclass 29, count 0 2006.173.10:54:10.12#ibcon#enter sib2, iclass 29, count 0 2006.173.10:54:10.12#ibcon#flushed, iclass 29, count 0 2006.173.10:54:10.12#ibcon#about to write, iclass 29, count 0 2006.173.10:54:10.12#ibcon#wrote, iclass 29, count 0 2006.173.10:54:10.12#ibcon#about to read 3, iclass 29, count 0 2006.173.10:54:10.14#ibcon#read 3, iclass 29, count 0 2006.173.10:54:10.14#ibcon#about to read 4, iclass 29, count 0 2006.173.10:54:10.14#ibcon#read 4, iclass 29, count 0 2006.173.10:54:10.14#ibcon#about to read 5, iclass 29, count 0 2006.173.10:54:10.14#ibcon#read 5, iclass 29, count 0 2006.173.10:54:10.14#ibcon#about to read 6, iclass 29, count 0 2006.173.10:54:10.14#ibcon#read 6, iclass 29, count 0 2006.173.10:54:10.14#ibcon#end of sib2, iclass 29, count 0 2006.173.10:54:10.14#ibcon#*mode == 0, iclass 29, count 0 2006.173.10:54:10.14#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.10:54:10.14#ibcon#[27=USB\r\n] 2006.173.10:54:10.14#ibcon#*before write, iclass 29, count 0 2006.173.10:54:10.14#ibcon#enter sib2, iclass 29, count 0 2006.173.10:54:10.14#ibcon#flushed, iclass 29, count 0 2006.173.10:54:10.14#ibcon#about to write, iclass 29, count 0 2006.173.10:54:10.14#ibcon#wrote, iclass 29, count 0 2006.173.10:54:10.14#ibcon#about to read 3, iclass 29, count 0 2006.173.10:54:10.17#ibcon#read 3, iclass 29, count 0 2006.173.10:54:10.17#ibcon#about to read 4, iclass 29, count 0 2006.173.10:54:10.17#ibcon#read 4, iclass 29, count 0 2006.173.10:54:10.17#ibcon#about to read 5, iclass 29, count 0 2006.173.10:54:10.17#ibcon#read 5, iclass 29, count 0 2006.173.10:54:10.17#ibcon#about to read 6, iclass 29, count 0 2006.173.10:54:10.17#ibcon#read 6, iclass 29, count 0 2006.173.10:54:10.17#ibcon#end of sib2, iclass 29, count 0 2006.173.10:54:10.17#ibcon#*after write, iclass 29, count 0 2006.173.10:54:10.17#ibcon#*before return 0, iclass 29, count 0 2006.173.10:54:10.17#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.10:54:10.17#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.10:54:10.17#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.10:54:10.17#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.10:54:10.17$vck44/vblo=5,709.99 2006.173.10:54:10.17#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.10:54:10.17#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.10:54:10.17#ibcon#ireg 17 cls_cnt 0 2006.173.10:54:10.17#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.10:54:10.17#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.10:54:10.17#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.10:54:10.17#ibcon#enter wrdev, iclass 31, count 0 2006.173.10:54:10.17#ibcon#first serial, iclass 31, count 0 2006.173.10:54:10.17#ibcon#enter sib2, iclass 31, count 0 2006.173.10:54:10.17#ibcon#flushed, iclass 31, count 0 2006.173.10:54:10.17#ibcon#about to write, iclass 31, count 0 2006.173.10:54:10.17#ibcon#wrote, iclass 31, count 0 2006.173.10:54:10.17#ibcon#about to read 3, iclass 31, count 0 2006.173.10:54:10.19#ibcon#read 3, iclass 31, count 0 2006.173.10:54:10.19#ibcon#about to read 4, iclass 31, count 0 2006.173.10:54:10.19#ibcon#read 4, iclass 31, count 0 2006.173.10:54:10.19#ibcon#about to read 5, iclass 31, count 0 2006.173.10:54:10.19#ibcon#read 5, iclass 31, count 0 2006.173.10:54:10.19#ibcon#about to read 6, iclass 31, count 0 2006.173.10:54:10.19#ibcon#read 6, iclass 31, count 0 2006.173.10:54:10.19#ibcon#end of sib2, iclass 31, count 0 2006.173.10:54:10.19#ibcon#*mode == 0, iclass 31, count 0 2006.173.10:54:10.19#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.10:54:10.19#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.10:54:10.19#ibcon#*before write, iclass 31, count 0 2006.173.10:54:10.19#ibcon#enter sib2, iclass 31, count 0 2006.173.10:54:10.19#ibcon#flushed, iclass 31, count 0 2006.173.10:54:10.19#ibcon#about to write, iclass 31, count 0 2006.173.10:54:10.19#ibcon#wrote, iclass 31, count 0 2006.173.10:54:10.19#ibcon#about to read 3, iclass 31, count 0 2006.173.10:54:10.23#ibcon#read 3, iclass 31, count 0 2006.173.10:54:10.23#ibcon#about to read 4, iclass 31, count 0 2006.173.10:54:10.23#ibcon#read 4, iclass 31, count 0 2006.173.10:54:10.23#ibcon#about to read 5, iclass 31, count 0 2006.173.10:54:10.23#ibcon#read 5, iclass 31, count 0 2006.173.10:54:10.23#ibcon#about to read 6, iclass 31, count 0 2006.173.10:54:10.23#ibcon#read 6, iclass 31, count 0 2006.173.10:54:10.23#ibcon#end of sib2, iclass 31, count 0 2006.173.10:54:10.23#ibcon#*after write, iclass 31, count 0 2006.173.10:54:10.23#ibcon#*before return 0, iclass 31, count 0 2006.173.10:54:10.23#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.10:54:10.23#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.10:54:10.23#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.10:54:10.23#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.10:54:10.23$vck44/vb=5,4 2006.173.10:54:10.23#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.173.10:54:10.23#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.173.10:54:10.23#ibcon#ireg 11 cls_cnt 2 2006.173.10:54:10.23#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.10:54:10.29#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.10:54:10.29#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.10:54:10.29#ibcon#enter wrdev, iclass 33, count 2 2006.173.10:54:10.29#ibcon#first serial, iclass 33, count 2 2006.173.10:54:10.29#ibcon#enter sib2, iclass 33, count 2 2006.173.10:54:10.29#ibcon#flushed, iclass 33, count 2 2006.173.10:54:10.29#ibcon#about to write, iclass 33, count 2 2006.173.10:54:10.29#ibcon#wrote, iclass 33, count 2 2006.173.10:54:10.29#ibcon#about to read 3, iclass 33, count 2 2006.173.10:54:10.31#ibcon#read 3, iclass 33, count 2 2006.173.10:54:10.31#ibcon#about to read 4, iclass 33, count 2 2006.173.10:54:10.31#ibcon#read 4, iclass 33, count 2 2006.173.10:54:10.31#ibcon#about to read 5, iclass 33, count 2 2006.173.10:54:10.31#ibcon#read 5, iclass 33, count 2 2006.173.10:54:10.31#ibcon#about to read 6, iclass 33, count 2 2006.173.10:54:10.31#ibcon#read 6, iclass 33, count 2 2006.173.10:54:10.31#ibcon#end of sib2, iclass 33, count 2 2006.173.10:54:10.31#ibcon#*mode == 0, iclass 33, count 2 2006.173.10:54:10.31#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.173.10:54:10.31#ibcon#[27=AT05-04\r\n] 2006.173.10:54:10.31#ibcon#*before write, iclass 33, count 2 2006.173.10:54:10.31#ibcon#enter sib2, iclass 33, count 2 2006.173.10:54:10.31#ibcon#flushed, iclass 33, count 2 2006.173.10:54:10.31#ibcon#about to write, iclass 33, count 2 2006.173.10:54:10.31#ibcon#wrote, iclass 33, count 2 2006.173.10:54:10.31#ibcon#about to read 3, iclass 33, count 2 2006.173.10:54:10.34#ibcon#read 3, iclass 33, count 2 2006.173.10:54:10.34#ibcon#about to read 4, iclass 33, count 2 2006.173.10:54:10.34#ibcon#read 4, iclass 33, count 2 2006.173.10:54:10.34#ibcon#about to read 5, iclass 33, count 2 2006.173.10:54:10.34#ibcon#read 5, iclass 33, count 2 2006.173.10:54:10.34#ibcon#about to read 6, iclass 33, count 2 2006.173.10:54:10.34#ibcon#read 6, iclass 33, count 2 2006.173.10:54:10.34#ibcon#end of sib2, iclass 33, count 2 2006.173.10:54:10.34#ibcon#*after write, iclass 33, count 2 2006.173.10:54:10.34#ibcon#*before return 0, iclass 33, count 2 2006.173.10:54:10.34#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.10:54:10.34#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.173.10:54:10.34#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.173.10:54:10.34#ibcon#ireg 7 cls_cnt 0 2006.173.10:54:10.34#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.10:54:10.46#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.10:54:10.46#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.10:54:10.46#ibcon#enter wrdev, iclass 33, count 0 2006.173.10:54:10.46#ibcon#first serial, iclass 33, count 0 2006.173.10:54:10.46#ibcon#enter sib2, iclass 33, count 0 2006.173.10:54:10.46#ibcon#flushed, iclass 33, count 0 2006.173.10:54:10.46#ibcon#about to write, iclass 33, count 0 2006.173.10:54:10.46#ibcon#wrote, iclass 33, count 0 2006.173.10:54:10.46#ibcon#about to read 3, iclass 33, count 0 2006.173.10:54:10.48#ibcon#read 3, iclass 33, count 0 2006.173.10:54:10.48#ibcon#about to read 4, iclass 33, count 0 2006.173.10:54:10.48#ibcon#read 4, iclass 33, count 0 2006.173.10:54:10.48#ibcon#about to read 5, iclass 33, count 0 2006.173.10:54:10.48#ibcon#read 5, iclass 33, count 0 2006.173.10:54:10.48#ibcon#about to read 6, iclass 33, count 0 2006.173.10:54:10.48#ibcon#read 6, iclass 33, count 0 2006.173.10:54:10.48#ibcon#end of sib2, iclass 33, count 0 2006.173.10:54:10.48#ibcon#*mode == 0, iclass 33, count 0 2006.173.10:54:10.48#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.10:54:10.48#ibcon#[27=USB\r\n] 2006.173.10:54:10.48#ibcon#*before write, iclass 33, count 0 2006.173.10:54:10.48#ibcon#enter sib2, iclass 33, count 0 2006.173.10:54:10.48#ibcon#flushed, iclass 33, count 0 2006.173.10:54:10.48#ibcon#about to write, iclass 33, count 0 2006.173.10:54:10.48#ibcon#wrote, iclass 33, count 0 2006.173.10:54:10.48#ibcon#about to read 3, iclass 33, count 0 2006.173.10:54:10.51#ibcon#read 3, iclass 33, count 0 2006.173.10:54:10.51#ibcon#about to read 4, iclass 33, count 0 2006.173.10:54:10.51#ibcon#read 4, iclass 33, count 0 2006.173.10:54:10.51#ibcon#about to read 5, iclass 33, count 0 2006.173.10:54:10.51#ibcon#read 5, iclass 33, count 0 2006.173.10:54:10.51#ibcon#about to read 6, iclass 33, count 0 2006.173.10:54:10.51#ibcon#read 6, iclass 33, count 0 2006.173.10:54:10.51#ibcon#end of sib2, iclass 33, count 0 2006.173.10:54:10.51#ibcon#*after write, iclass 33, count 0 2006.173.10:54:10.51#ibcon#*before return 0, iclass 33, count 0 2006.173.10:54:10.51#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.10:54:10.51#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.173.10:54:10.51#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.10:54:10.51#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.10:54:10.51$vck44/vblo=6,719.99 2006.173.10:54:10.51#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.10:54:10.51#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.10:54:10.51#ibcon#ireg 17 cls_cnt 0 2006.173.10:54:10.51#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.10:54:10.51#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.10:54:10.51#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.10:54:10.51#ibcon#enter wrdev, iclass 35, count 0 2006.173.10:54:10.51#ibcon#first serial, iclass 35, count 0 2006.173.10:54:10.51#ibcon#enter sib2, iclass 35, count 0 2006.173.10:54:10.51#ibcon#flushed, iclass 35, count 0 2006.173.10:54:10.51#ibcon#about to write, iclass 35, count 0 2006.173.10:54:10.51#ibcon#wrote, iclass 35, count 0 2006.173.10:54:10.51#ibcon#about to read 3, iclass 35, count 0 2006.173.10:54:10.53#ibcon#read 3, iclass 35, count 0 2006.173.10:54:10.53#ibcon#about to read 4, iclass 35, count 0 2006.173.10:54:10.53#ibcon#read 4, iclass 35, count 0 2006.173.10:54:10.53#ibcon#about to read 5, iclass 35, count 0 2006.173.10:54:10.53#ibcon#read 5, iclass 35, count 0 2006.173.10:54:10.53#ibcon#about to read 6, iclass 35, count 0 2006.173.10:54:10.53#ibcon#read 6, iclass 35, count 0 2006.173.10:54:10.53#ibcon#end of sib2, iclass 35, count 0 2006.173.10:54:10.53#ibcon#*mode == 0, iclass 35, count 0 2006.173.10:54:10.53#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.10:54:10.53#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.10:54:10.53#ibcon#*before write, iclass 35, count 0 2006.173.10:54:10.53#ibcon#enter sib2, iclass 35, count 0 2006.173.10:54:10.53#ibcon#flushed, iclass 35, count 0 2006.173.10:54:10.53#ibcon#about to write, iclass 35, count 0 2006.173.10:54:10.53#ibcon#wrote, iclass 35, count 0 2006.173.10:54:10.53#ibcon#about to read 3, iclass 35, count 0 2006.173.10:54:10.57#ibcon#read 3, iclass 35, count 0 2006.173.10:54:10.57#ibcon#about to read 4, iclass 35, count 0 2006.173.10:54:10.57#ibcon#read 4, iclass 35, count 0 2006.173.10:54:10.57#ibcon#about to read 5, iclass 35, count 0 2006.173.10:54:10.57#ibcon#read 5, iclass 35, count 0 2006.173.10:54:10.57#ibcon#about to read 6, iclass 35, count 0 2006.173.10:54:10.57#ibcon#read 6, iclass 35, count 0 2006.173.10:54:10.57#ibcon#end of sib2, iclass 35, count 0 2006.173.10:54:10.57#ibcon#*after write, iclass 35, count 0 2006.173.10:54:10.57#ibcon#*before return 0, iclass 35, count 0 2006.173.10:54:10.57#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.10:54:10.57#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.10:54:10.57#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.10:54:10.57#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.10:54:10.57$vck44/vb=6,4 2006.173.10:54:10.57#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.173.10:54:10.57#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.173.10:54:10.57#ibcon#ireg 11 cls_cnt 2 2006.173.10:54:10.57#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.10:54:10.63#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.10:54:10.63#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.10:54:10.63#ibcon#enter wrdev, iclass 37, count 2 2006.173.10:54:10.63#ibcon#first serial, iclass 37, count 2 2006.173.10:54:10.63#ibcon#enter sib2, iclass 37, count 2 2006.173.10:54:10.63#ibcon#flushed, iclass 37, count 2 2006.173.10:54:10.63#ibcon#about to write, iclass 37, count 2 2006.173.10:54:10.63#ibcon#wrote, iclass 37, count 2 2006.173.10:54:10.63#ibcon#about to read 3, iclass 37, count 2 2006.173.10:54:10.65#ibcon#read 3, iclass 37, count 2 2006.173.10:54:10.65#ibcon#about to read 4, iclass 37, count 2 2006.173.10:54:10.65#ibcon#read 4, iclass 37, count 2 2006.173.10:54:10.65#ibcon#about to read 5, iclass 37, count 2 2006.173.10:54:10.65#ibcon#read 5, iclass 37, count 2 2006.173.10:54:10.65#ibcon#about to read 6, iclass 37, count 2 2006.173.10:54:10.65#ibcon#read 6, iclass 37, count 2 2006.173.10:54:10.65#ibcon#end of sib2, iclass 37, count 2 2006.173.10:54:10.65#ibcon#*mode == 0, iclass 37, count 2 2006.173.10:54:10.65#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.173.10:54:10.65#ibcon#[27=AT06-04\r\n] 2006.173.10:54:10.65#ibcon#*before write, iclass 37, count 2 2006.173.10:54:10.65#ibcon#enter sib2, iclass 37, count 2 2006.173.10:54:10.65#ibcon#flushed, iclass 37, count 2 2006.173.10:54:10.65#ibcon#about to write, iclass 37, count 2 2006.173.10:54:10.65#ibcon#wrote, iclass 37, count 2 2006.173.10:54:10.65#ibcon#about to read 3, iclass 37, count 2 2006.173.10:54:10.68#ibcon#read 3, iclass 37, count 2 2006.173.10:54:10.68#ibcon#about to read 4, iclass 37, count 2 2006.173.10:54:10.68#ibcon#read 4, iclass 37, count 2 2006.173.10:54:10.68#ibcon#about to read 5, iclass 37, count 2 2006.173.10:54:10.68#ibcon#read 5, iclass 37, count 2 2006.173.10:54:10.68#ibcon#about to read 6, iclass 37, count 2 2006.173.10:54:10.68#ibcon#read 6, iclass 37, count 2 2006.173.10:54:10.68#ibcon#end of sib2, iclass 37, count 2 2006.173.10:54:10.68#ibcon#*after write, iclass 37, count 2 2006.173.10:54:10.68#ibcon#*before return 0, iclass 37, count 2 2006.173.10:54:10.68#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.10:54:10.68#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.173.10:54:10.68#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.173.10:54:10.68#ibcon#ireg 7 cls_cnt 0 2006.173.10:54:10.68#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.10:54:10.80#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.10:54:10.80#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.10:54:10.80#ibcon#enter wrdev, iclass 37, count 0 2006.173.10:54:10.80#ibcon#first serial, iclass 37, count 0 2006.173.10:54:10.80#ibcon#enter sib2, iclass 37, count 0 2006.173.10:54:10.80#ibcon#flushed, iclass 37, count 0 2006.173.10:54:10.80#ibcon#about to write, iclass 37, count 0 2006.173.10:54:10.80#ibcon#wrote, iclass 37, count 0 2006.173.10:54:10.80#ibcon#about to read 3, iclass 37, count 0 2006.173.10:54:10.82#ibcon#read 3, iclass 37, count 0 2006.173.10:54:10.82#ibcon#about to read 4, iclass 37, count 0 2006.173.10:54:10.82#ibcon#read 4, iclass 37, count 0 2006.173.10:54:10.82#ibcon#about to read 5, iclass 37, count 0 2006.173.10:54:10.82#ibcon#read 5, iclass 37, count 0 2006.173.10:54:10.82#ibcon#about to read 6, iclass 37, count 0 2006.173.10:54:10.82#ibcon#read 6, iclass 37, count 0 2006.173.10:54:10.82#ibcon#end of sib2, iclass 37, count 0 2006.173.10:54:10.82#ibcon#*mode == 0, iclass 37, count 0 2006.173.10:54:10.82#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.10:54:10.82#ibcon#[27=USB\r\n] 2006.173.10:54:10.82#ibcon#*before write, iclass 37, count 0 2006.173.10:54:10.82#ibcon#enter sib2, iclass 37, count 0 2006.173.10:54:10.82#ibcon#flushed, iclass 37, count 0 2006.173.10:54:10.82#ibcon#about to write, iclass 37, count 0 2006.173.10:54:10.82#ibcon#wrote, iclass 37, count 0 2006.173.10:54:10.82#ibcon#about to read 3, iclass 37, count 0 2006.173.10:54:10.85#ibcon#read 3, iclass 37, count 0 2006.173.10:54:10.85#ibcon#about to read 4, iclass 37, count 0 2006.173.10:54:10.85#ibcon#read 4, iclass 37, count 0 2006.173.10:54:10.85#ibcon#about to read 5, iclass 37, count 0 2006.173.10:54:10.85#ibcon#read 5, iclass 37, count 0 2006.173.10:54:10.85#ibcon#about to read 6, iclass 37, count 0 2006.173.10:54:10.85#ibcon#read 6, iclass 37, count 0 2006.173.10:54:10.85#ibcon#end of sib2, iclass 37, count 0 2006.173.10:54:10.85#ibcon#*after write, iclass 37, count 0 2006.173.10:54:10.85#ibcon#*before return 0, iclass 37, count 0 2006.173.10:54:10.85#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.10:54:10.85#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.173.10:54:10.85#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.10:54:10.85#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.10:54:10.85$vck44/vblo=7,734.99 2006.173.10:54:10.85#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.10:54:10.85#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.10:54:10.85#ibcon#ireg 17 cls_cnt 0 2006.173.10:54:10.85#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.10:54:10.85#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.10:54:10.85#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.10:54:10.85#ibcon#enter wrdev, iclass 39, count 0 2006.173.10:54:10.85#ibcon#first serial, iclass 39, count 0 2006.173.10:54:10.85#ibcon#enter sib2, iclass 39, count 0 2006.173.10:54:10.85#ibcon#flushed, iclass 39, count 0 2006.173.10:54:10.85#ibcon#about to write, iclass 39, count 0 2006.173.10:54:10.85#ibcon#wrote, iclass 39, count 0 2006.173.10:54:10.85#ibcon#about to read 3, iclass 39, count 0 2006.173.10:54:10.87#ibcon#read 3, iclass 39, count 0 2006.173.10:54:10.87#ibcon#about to read 4, iclass 39, count 0 2006.173.10:54:10.87#ibcon#read 4, iclass 39, count 0 2006.173.10:54:10.87#ibcon#about to read 5, iclass 39, count 0 2006.173.10:54:10.87#ibcon#read 5, iclass 39, count 0 2006.173.10:54:10.87#ibcon#about to read 6, iclass 39, count 0 2006.173.10:54:10.87#ibcon#read 6, iclass 39, count 0 2006.173.10:54:10.87#ibcon#end of sib2, iclass 39, count 0 2006.173.10:54:10.87#ibcon#*mode == 0, iclass 39, count 0 2006.173.10:54:10.87#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.10:54:10.87#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.10:54:10.87#ibcon#*before write, iclass 39, count 0 2006.173.10:54:10.87#ibcon#enter sib2, iclass 39, count 0 2006.173.10:54:10.87#ibcon#flushed, iclass 39, count 0 2006.173.10:54:10.87#ibcon#about to write, iclass 39, count 0 2006.173.10:54:10.87#ibcon#wrote, iclass 39, count 0 2006.173.10:54:10.87#ibcon#about to read 3, iclass 39, count 0 2006.173.10:54:10.91#ibcon#read 3, iclass 39, count 0 2006.173.10:54:10.91#ibcon#about to read 4, iclass 39, count 0 2006.173.10:54:10.91#ibcon#read 4, iclass 39, count 0 2006.173.10:54:10.91#ibcon#about to read 5, iclass 39, count 0 2006.173.10:54:10.91#ibcon#read 5, iclass 39, count 0 2006.173.10:54:10.91#ibcon#about to read 6, iclass 39, count 0 2006.173.10:54:10.91#ibcon#read 6, iclass 39, count 0 2006.173.10:54:10.91#ibcon#end of sib2, iclass 39, count 0 2006.173.10:54:10.91#ibcon#*after write, iclass 39, count 0 2006.173.10:54:10.91#ibcon#*before return 0, iclass 39, count 0 2006.173.10:54:10.91#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.10:54:10.91#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.10:54:10.91#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.10:54:10.91#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.10:54:10.91$vck44/vb=7,4 2006.173.10:54:10.91#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.10:54:10.91#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.10:54:10.91#ibcon#ireg 11 cls_cnt 2 2006.173.10:54:10.91#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.10:54:10.97#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.10:54:10.97#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.10:54:10.97#ibcon#enter wrdev, iclass 3, count 2 2006.173.10:54:10.97#ibcon#first serial, iclass 3, count 2 2006.173.10:54:10.97#ibcon#enter sib2, iclass 3, count 2 2006.173.10:54:10.97#ibcon#flushed, iclass 3, count 2 2006.173.10:54:10.97#ibcon#about to write, iclass 3, count 2 2006.173.10:54:10.97#ibcon#wrote, iclass 3, count 2 2006.173.10:54:10.97#ibcon#about to read 3, iclass 3, count 2 2006.173.10:54:10.99#ibcon#read 3, iclass 3, count 2 2006.173.10:54:10.99#ibcon#about to read 4, iclass 3, count 2 2006.173.10:54:10.99#ibcon#read 4, iclass 3, count 2 2006.173.10:54:10.99#ibcon#about to read 5, iclass 3, count 2 2006.173.10:54:10.99#ibcon#read 5, iclass 3, count 2 2006.173.10:54:10.99#ibcon#about to read 6, iclass 3, count 2 2006.173.10:54:10.99#ibcon#read 6, iclass 3, count 2 2006.173.10:54:10.99#ibcon#end of sib2, iclass 3, count 2 2006.173.10:54:10.99#ibcon#*mode == 0, iclass 3, count 2 2006.173.10:54:10.99#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.10:54:10.99#ibcon#[27=AT07-04\r\n] 2006.173.10:54:10.99#ibcon#*before write, iclass 3, count 2 2006.173.10:54:10.99#ibcon#enter sib2, iclass 3, count 2 2006.173.10:54:10.99#ibcon#flushed, iclass 3, count 2 2006.173.10:54:10.99#ibcon#about to write, iclass 3, count 2 2006.173.10:54:10.99#ibcon#wrote, iclass 3, count 2 2006.173.10:54:10.99#ibcon#about to read 3, iclass 3, count 2 2006.173.10:54:11.02#ibcon#read 3, iclass 3, count 2 2006.173.10:54:11.02#ibcon#about to read 4, iclass 3, count 2 2006.173.10:54:11.02#ibcon#read 4, iclass 3, count 2 2006.173.10:54:11.02#ibcon#about to read 5, iclass 3, count 2 2006.173.10:54:11.02#ibcon#read 5, iclass 3, count 2 2006.173.10:54:11.02#ibcon#about to read 6, iclass 3, count 2 2006.173.10:54:11.02#ibcon#read 6, iclass 3, count 2 2006.173.10:54:11.02#ibcon#end of sib2, iclass 3, count 2 2006.173.10:54:11.02#ibcon#*after write, iclass 3, count 2 2006.173.10:54:11.02#ibcon#*before return 0, iclass 3, count 2 2006.173.10:54:11.02#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.10:54:11.02#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.10:54:11.02#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.10:54:11.02#ibcon#ireg 7 cls_cnt 0 2006.173.10:54:11.02#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.10:54:11.14#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.10:54:11.14#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.10:54:11.14#ibcon#enter wrdev, iclass 3, count 0 2006.173.10:54:11.14#ibcon#first serial, iclass 3, count 0 2006.173.10:54:11.14#ibcon#enter sib2, iclass 3, count 0 2006.173.10:54:11.14#ibcon#flushed, iclass 3, count 0 2006.173.10:54:11.14#ibcon#about to write, iclass 3, count 0 2006.173.10:54:11.14#ibcon#wrote, iclass 3, count 0 2006.173.10:54:11.14#ibcon#about to read 3, iclass 3, count 0 2006.173.10:54:11.16#ibcon#read 3, iclass 3, count 0 2006.173.10:54:11.16#ibcon#about to read 4, iclass 3, count 0 2006.173.10:54:11.16#ibcon#read 4, iclass 3, count 0 2006.173.10:54:11.16#ibcon#about to read 5, iclass 3, count 0 2006.173.10:54:11.16#ibcon#read 5, iclass 3, count 0 2006.173.10:54:11.16#ibcon#about to read 6, iclass 3, count 0 2006.173.10:54:11.16#ibcon#read 6, iclass 3, count 0 2006.173.10:54:11.16#ibcon#end of sib2, iclass 3, count 0 2006.173.10:54:11.16#ibcon#*mode == 0, iclass 3, count 0 2006.173.10:54:11.16#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.10:54:11.16#ibcon#[27=USB\r\n] 2006.173.10:54:11.16#ibcon#*before write, iclass 3, count 0 2006.173.10:54:11.16#ibcon#enter sib2, iclass 3, count 0 2006.173.10:54:11.16#ibcon#flushed, iclass 3, count 0 2006.173.10:54:11.16#ibcon#about to write, iclass 3, count 0 2006.173.10:54:11.16#ibcon#wrote, iclass 3, count 0 2006.173.10:54:11.16#ibcon#about to read 3, iclass 3, count 0 2006.173.10:54:11.19#ibcon#read 3, iclass 3, count 0 2006.173.10:54:11.19#ibcon#about to read 4, iclass 3, count 0 2006.173.10:54:11.19#ibcon#read 4, iclass 3, count 0 2006.173.10:54:11.19#ibcon#about to read 5, iclass 3, count 0 2006.173.10:54:11.19#ibcon#read 5, iclass 3, count 0 2006.173.10:54:11.19#ibcon#about to read 6, iclass 3, count 0 2006.173.10:54:11.19#ibcon#read 6, iclass 3, count 0 2006.173.10:54:11.19#ibcon#end of sib2, iclass 3, count 0 2006.173.10:54:11.19#ibcon#*after write, iclass 3, count 0 2006.173.10:54:11.19#ibcon#*before return 0, iclass 3, count 0 2006.173.10:54:11.19#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.10:54:11.19#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.10:54:11.19#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.10:54:11.19#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.10:54:11.19$vck44/vblo=8,744.99 2006.173.10:54:11.19#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.10:54:11.19#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.10:54:11.19#ibcon#ireg 17 cls_cnt 0 2006.173.10:54:11.19#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.10:54:11.19#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.10:54:11.19#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.10:54:11.19#ibcon#enter wrdev, iclass 5, count 0 2006.173.10:54:11.19#ibcon#first serial, iclass 5, count 0 2006.173.10:54:11.19#ibcon#enter sib2, iclass 5, count 0 2006.173.10:54:11.19#ibcon#flushed, iclass 5, count 0 2006.173.10:54:11.19#ibcon#about to write, iclass 5, count 0 2006.173.10:54:11.19#ibcon#wrote, iclass 5, count 0 2006.173.10:54:11.19#ibcon#about to read 3, iclass 5, count 0 2006.173.10:54:11.21#ibcon#read 3, iclass 5, count 0 2006.173.10:54:11.21#ibcon#about to read 4, iclass 5, count 0 2006.173.10:54:11.21#ibcon#read 4, iclass 5, count 0 2006.173.10:54:11.21#ibcon#about to read 5, iclass 5, count 0 2006.173.10:54:11.21#ibcon#read 5, iclass 5, count 0 2006.173.10:54:11.21#ibcon#about to read 6, iclass 5, count 0 2006.173.10:54:11.21#ibcon#read 6, iclass 5, count 0 2006.173.10:54:11.21#ibcon#end of sib2, iclass 5, count 0 2006.173.10:54:11.21#ibcon#*mode == 0, iclass 5, count 0 2006.173.10:54:11.21#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.10:54:11.21#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.10:54:11.21#ibcon#*before write, iclass 5, count 0 2006.173.10:54:11.21#ibcon#enter sib2, iclass 5, count 0 2006.173.10:54:11.21#ibcon#flushed, iclass 5, count 0 2006.173.10:54:11.21#ibcon#about to write, iclass 5, count 0 2006.173.10:54:11.21#ibcon#wrote, iclass 5, count 0 2006.173.10:54:11.21#ibcon#about to read 3, iclass 5, count 0 2006.173.10:54:11.25#ibcon#read 3, iclass 5, count 0 2006.173.10:54:11.25#ibcon#about to read 4, iclass 5, count 0 2006.173.10:54:11.25#ibcon#read 4, iclass 5, count 0 2006.173.10:54:11.25#ibcon#about to read 5, iclass 5, count 0 2006.173.10:54:11.25#ibcon#read 5, iclass 5, count 0 2006.173.10:54:11.25#ibcon#about to read 6, iclass 5, count 0 2006.173.10:54:11.25#ibcon#read 6, iclass 5, count 0 2006.173.10:54:11.25#ibcon#end of sib2, iclass 5, count 0 2006.173.10:54:11.25#ibcon#*after write, iclass 5, count 0 2006.173.10:54:11.25#ibcon#*before return 0, iclass 5, count 0 2006.173.10:54:11.25#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.10:54:11.25#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.10:54:11.25#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.10:54:11.25#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.10:54:11.25$vck44/vb=8,4 2006.173.10:54:11.25#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.173.10:54:11.25#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.173.10:54:11.25#ibcon#ireg 11 cls_cnt 2 2006.173.10:54:11.25#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.10:54:11.31#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.10:54:11.31#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.10:54:11.31#ibcon#enter wrdev, iclass 7, count 2 2006.173.10:54:11.31#ibcon#first serial, iclass 7, count 2 2006.173.10:54:11.31#ibcon#enter sib2, iclass 7, count 2 2006.173.10:54:11.31#ibcon#flushed, iclass 7, count 2 2006.173.10:54:11.31#ibcon#about to write, iclass 7, count 2 2006.173.10:54:11.31#ibcon#wrote, iclass 7, count 2 2006.173.10:54:11.31#ibcon#about to read 3, iclass 7, count 2 2006.173.10:54:11.33#ibcon#read 3, iclass 7, count 2 2006.173.10:54:11.33#ibcon#about to read 4, iclass 7, count 2 2006.173.10:54:11.33#ibcon#read 4, iclass 7, count 2 2006.173.10:54:11.33#ibcon#about to read 5, iclass 7, count 2 2006.173.10:54:11.33#ibcon#read 5, iclass 7, count 2 2006.173.10:54:11.33#ibcon#about to read 6, iclass 7, count 2 2006.173.10:54:11.33#ibcon#read 6, iclass 7, count 2 2006.173.10:54:11.33#ibcon#end of sib2, iclass 7, count 2 2006.173.10:54:11.33#ibcon#*mode == 0, iclass 7, count 2 2006.173.10:54:11.33#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.173.10:54:11.33#ibcon#[27=AT08-04\r\n] 2006.173.10:54:11.33#ibcon#*before write, iclass 7, count 2 2006.173.10:54:11.33#ibcon#enter sib2, iclass 7, count 2 2006.173.10:54:11.33#ibcon#flushed, iclass 7, count 2 2006.173.10:54:11.33#ibcon#about to write, iclass 7, count 2 2006.173.10:54:11.33#ibcon#wrote, iclass 7, count 2 2006.173.10:54:11.33#ibcon#about to read 3, iclass 7, count 2 2006.173.10:54:11.36#ibcon#read 3, iclass 7, count 2 2006.173.10:54:11.36#ibcon#about to read 4, iclass 7, count 2 2006.173.10:54:11.36#ibcon#read 4, iclass 7, count 2 2006.173.10:54:11.36#ibcon#about to read 5, iclass 7, count 2 2006.173.10:54:11.36#ibcon#read 5, iclass 7, count 2 2006.173.10:54:11.36#ibcon#about to read 6, iclass 7, count 2 2006.173.10:54:11.36#ibcon#read 6, iclass 7, count 2 2006.173.10:54:11.36#ibcon#end of sib2, iclass 7, count 2 2006.173.10:54:11.36#ibcon#*after write, iclass 7, count 2 2006.173.10:54:11.36#ibcon#*before return 0, iclass 7, count 2 2006.173.10:54:11.36#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.10:54:11.36#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.173.10:54:11.36#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.173.10:54:11.36#ibcon#ireg 7 cls_cnt 0 2006.173.10:54:11.36#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.10:54:11.48#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.10:54:11.48#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.10:54:11.48#ibcon#enter wrdev, iclass 7, count 0 2006.173.10:54:11.48#ibcon#first serial, iclass 7, count 0 2006.173.10:54:11.48#ibcon#enter sib2, iclass 7, count 0 2006.173.10:54:11.48#ibcon#flushed, iclass 7, count 0 2006.173.10:54:11.48#ibcon#about to write, iclass 7, count 0 2006.173.10:54:11.48#ibcon#wrote, iclass 7, count 0 2006.173.10:54:11.48#ibcon#about to read 3, iclass 7, count 0 2006.173.10:54:11.50#ibcon#read 3, iclass 7, count 0 2006.173.10:54:11.50#ibcon#about to read 4, iclass 7, count 0 2006.173.10:54:11.50#ibcon#read 4, iclass 7, count 0 2006.173.10:54:11.50#ibcon#about to read 5, iclass 7, count 0 2006.173.10:54:11.50#ibcon#read 5, iclass 7, count 0 2006.173.10:54:11.50#ibcon#about to read 6, iclass 7, count 0 2006.173.10:54:11.50#ibcon#read 6, iclass 7, count 0 2006.173.10:54:11.50#ibcon#end of sib2, iclass 7, count 0 2006.173.10:54:11.50#ibcon#*mode == 0, iclass 7, count 0 2006.173.10:54:11.50#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.10:54:11.50#ibcon#[27=USB\r\n] 2006.173.10:54:11.50#ibcon#*before write, iclass 7, count 0 2006.173.10:54:11.50#ibcon#enter sib2, iclass 7, count 0 2006.173.10:54:11.50#ibcon#flushed, iclass 7, count 0 2006.173.10:54:11.50#ibcon#about to write, iclass 7, count 0 2006.173.10:54:11.50#ibcon#wrote, iclass 7, count 0 2006.173.10:54:11.50#ibcon#about to read 3, iclass 7, count 0 2006.173.10:54:11.53#ibcon#read 3, iclass 7, count 0 2006.173.10:54:11.53#ibcon#about to read 4, iclass 7, count 0 2006.173.10:54:11.53#ibcon#read 4, iclass 7, count 0 2006.173.10:54:11.53#ibcon#about to read 5, iclass 7, count 0 2006.173.10:54:11.53#ibcon#read 5, iclass 7, count 0 2006.173.10:54:11.53#ibcon#about to read 6, iclass 7, count 0 2006.173.10:54:11.53#ibcon#read 6, iclass 7, count 0 2006.173.10:54:11.53#ibcon#end of sib2, iclass 7, count 0 2006.173.10:54:11.53#ibcon#*after write, iclass 7, count 0 2006.173.10:54:11.53#ibcon#*before return 0, iclass 7, count 0 2006.173.10:54:11.53#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.10:54:11.53#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.173.10:54:11.53#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.10:54:11.53#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.10:54:11.53$vck44/vabw=wide 2006.173.10:54:11.53#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.10:54:11.53#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.10:54:11.53#ibcon#ireg 8 cls_cnt 0 2006.173.10:54:11.53#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.10:54:11.53#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.10:54:11.53#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.10:54:11.53#ibcon#enter wrdev, iclass 11, count 0 2006.173.10:54:11.53#ibcon#first serial, iclass 11, count 0 2006.173.10:54:11.53#ibcon#enter sib2, iclass 11, count 0 2006.173.10:54:11.53#ibcon#flushed, iclass 11, count 0 2006.173.10:54:11.53#ibcon#about to write, iclass 11, count 0 2006.173.10:54:11.53#ibcon#wrote, iclass 11, count 0 2006.173.10:54:11.53#ibcon#about to read 3, iclass 11, count 0 2006.173.10:54:11.55#ibcon#read 3, iclass 11, count 0 2006.173.10:54:11.55#ibcon#about to read 4, iclass 11, count 0 2006.173.10:54:11.55#ibcon#read 4, iclass 11, count 0 2006.173.10:54:11.55#ibcon#about to read 5, iclass 11, count 0 2006.173.10:54:11.55#ibcon#read 5, iclass 11, count 0 2006.173.10:54:11.55#ibcon#about to read 6, iclass 11, count 0 2006.173.10:54:11.55#ibcon#read 6, iclass 11, count 0 2006.173.10:54:11.55#ibcon#end of sib2, iclass 11, count 0 2006.173.10:54:11.55#ibcon#*mode == 0, iclass 11, count 0 2006.173.10:54:11.55#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.10:54:11.55#ibcon#[25=BW32\r\n] 2006.173.10:54:11.55#ibcon#*before write, iclass 11, count 0 2006.173.10:54:11.55#ibcon#enter sib2, iclass 11, count 0 2006.173.10:54:11.55#ibcon#flushed, iclass 11, count 0 2006.173.10:54:11.55#ibcon#about to write, iclass 11, count 0 2006.173.10:54:11.55#ibcon#wrote, iclass 11, count 0 2006.173.10:54:11.55#ibcon#about to read 3, iclass 11, count 0 2006.173.10:54:11.58#ibcon#read 3, iclass 11, count 0 2006.173.10:54:11.58#ibcon#about to read 4, iclass 11, count 0 2006.173.10:54:11.58#ibcon#read 4, iclass 11, count 0 2006.173.10:54:11.58#ibcon#about to read 5, iclass 11, count 0 2006.173.10:54:11.58#ibcon#read 5, iclass 11, count 0 2006.173.10:54:11.58#ibcon#about to read 6, iclass 11, count 0 2006.173.10:54:11.58#ibcon#read 6, iclass 11, count 0 2006.173.10:54:11.58#ibcon#end of sib2, iclass 11, count 0 2006.173.10:54:11.58#ibcon#*after write, iclass 11, count 0 2006.173.10:54:11.58#ibcon#*before return 0, iclass 11, count 0 2006.173.10:54:11.58#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.10:54:11.58#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.10:54:11.58#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.10:54:11.58#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.10:54:11.58$vck44/vbbw=wide 2006.173.10:54:11.58#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.10:54:11.58#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.10:54:11.58#ibcon#ireg 8 cls_cnt 0 2006.173.10:54:11.58#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.10:54:11.65#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.10:54:11.65#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.10:54:11.65#ibcon#enter wrdev, iclass 13, count 0 2006.173.10:54:11.65#ibcon#first serial, iclass 13, count 0 2006.173.10:54:11.65#ibcon#enter sib2, iclass 13, count 0 2006.173.10:54:11.65#ibcon#flushed, iclass 13, count 0 2006.173.10:54:11.65#ibcon#about to write, iclass 13, count 0 2006.173.10:54:11.65#ibcon#wrote, iclass 13, count 0 2006.173.10:54:11.65#ibcon#about to read 3, iclass 13, count 0 2006.173.10:54:11.67#ibcon#read 3, iclass 13, count 0 2006.173.10:54:11.67#ibcon#about to read 4, iclass 13, count 0 2006.173.10:54:11.67#ibcon#read 4, iclass 13, count 0 2006.173.10:54:11.67#ibcon#about to read 5, iclass 13, count 0 2006.173.10:54:11.67#ibcon#read 5, iclass 13, count 0 2006.173.10:54:11.67#ibcon#about to read 6, iclass 13, count 0 2006.173.10:54:11.67#ibcon#read 6, iclass 13, count 0 2006.173.10:54:11.67#ibcon#end of sib2, iclass 13, count 0 2006.173.10:54:11.67#ibcon#*mode == 0, iclass 13, count 0 2006.173.10:54:11.67#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.10:54:11.67#ibcon#[27=BW32\r\n] 2006.173.10:54:11.67#ibcon#*before write, iclass 13, count 0 2006.173.10:54:11.67#ibcon#enter sib2, iclass 13, count 0 2006.173.10:54:11.67#ibcon#flushed, iclass 13, count 0 2006.173.10:54:11.67#ibcon#about to write, iclass 13, count 0 2006.173.10:54:11.67#ibcon#wrote, iclass 13, count 0 2006.173.10:54:11.67#ibcon#about to read 3, iclass 13, count 0 2006.173.10:54:11.70#ibcon#read 3, iclass 13, count 0 2006.173.10:54:11.70#ibcon#about to read 4, iclass 13, count 0 2006.173.10:54:11.70#ibcon#read 4, iclass 13, count 0 2006.173.10:54:11.70#ibcon#about to read 5, iclass 13, count 0 2006.173.10:54:11.70#ibcon#read 5, iclass 13, count 0 2006.173.10:54:11.70#ibcon#about to read 6, iclass 13, count 0 2006.173.10:54:11.70#ibcon#read 6, iclass 13, count 0 2006.173.10:54:11.70#ibcon#end of sib2, iclass 13, count 0 2006.173.10:54:11.70#ibcon#*after write, iclass 13, count 0 2006.173.10:54:11.70#ibcon#*before return 0, iclass 13, count 0 2006.173.10:54:11.70#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.10:54:11.70#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.10:54:11.70#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.10:54:11.70#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.10:54:11.70$setupk4/ifdk4 2006.173.10:54:11.70$ifdk4/lo= 2006.173.10:54:11.70$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.10:54:11.70$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.10:54:11.70$ifdk4/patch= 2006.173.10:54:11.70$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.10:54:11.70$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.10:54:11.70$setupk4/!*+20s 2006.173.10:54:19.18#abcon#<5=/04 0.7 1.8 22.59 921003.9\r\n> 2006.173.10:54:19.20#abcon#{5=INTERFACE CLEAR} 2006.173.10:54:19.26#abcon#[5=S1D000X0/0*\r\n] 2006.173.10:54:26.20$setupk4/"tpicd 2006.173.10:54:26.20$setupk4/echo=off 2006.173.10:54:26.20$setupk4/xlog=off 2006.173.10:54:26.20:!2006.173.10:55:23 2006.173.10:54:33.14#trakl#Source acquired 2006.173.10:54:34.14#flagr#flagr/antenna,acquired 2006.173.10:55:23.00:preob 2006.173.10:55:23.14/onsource/TRACKING 2006.173.10:55:23.14:!2006.173.10:55:33 2006.173.10:55:33.00:"tape 2006.173.10:55:33.00:"st=record 2006.173.10:55:33.00:data_valid=on 2006.173.10:55:33.00:midob 2006.173.10:55:34.14/onsource/TRACKING 2006.173.10:55:34.14/wx/22.58,1003.9,92 2006.173.10:55:34.32/cable/+6.5028E-03 2006.173.10:55:35.41/va/01,07,usb,yes,36,39 2006.173.10:55:35.41/va/02,06,usb,yes,36,37 2006.173.10:55:35.41/va/03,05,usb,yes,46,48 2006.173.10:55:35.41/va/04,06,usb,yes,37,39 2006.173.10:55:35.41/va/05,04,usb,yes,29,29 2006.173.10:55:35.41/va/06,03,usb,yes,40,40 2006.173.10:55:35.41/va/07,04,usb,yes,33,34 2006.173.10:55:35.41/va/08,04,usb,yes,28,34 2006.173.10:55:35.64/valo/01,524.99,yes,locked 2006.173.10:55:35.64/valo/02,534.99,yes,locked 2006.173.10:55:35.64/valo/03,564.99,yes,locked 2006.173.10:55:35.64/valo/04,624.99,yes,locked 2006.173.10:55:35.64/valo/05,734.99,yes,locked 2006.173.10:55:35.64/valo/06,814.99,yes,locked 2006.173.10:55:35.64/valo/07,864.99,yes,locked 2006.173.10:55:35.64/valo/08,884.99,yes,locked 2006.173.10:55:36.73/vb/01,04,usb,yes,29,27 2006.173.10:55:36.73/vb/02,04,usb,yes,32,32 2006.173.10:55:36.73/vb/03,04,usb,yes,29,32 2006.173.10:55:36.73/vb/04,04,usb,yes,33,32 2006.173.10:55:36.73/vb/05,04,usb,yes,26,28 2006.173.10:55:36.73/vb/06,04,usb,yes,30,26 2006.173.10:55:36.73/vb/07,04,usb,yes,30,30 2006.173.10:55:36.73/vb/08,04,usb,yes,28,31 2006.173.10:55:36.96/vblo/01,629.99,yes,locked 2006.173.10:55:36.96/vblo/02,634.99,yes,locked 2006.173.10:55:36.96/vblo/03,649.99,yes,locked 2006.173.10:55:36.96/vblo/04,679.99,yes,locked 2006.173.10:55:36.96/vblo/05,709.99,yes,locked 2006.173.10:55:36.96/vblo/06,719.99,yes,locked 2006.173.10:55:36.96/vblo/07,734.99,yes,locked 2006.173.10:55:36.96/vblo/08,744.99,yes,locked 2006.173.10:55:37.11/vabw/8 2006.173.10:55:37.26/vbbw/8 2006.173.10:55:37.35/xfe/off,on,15.2 2006.173.10:55:37.73/ifatt/23,28,28,28 2006.173.10:55:38.08/fmout-gps/S +4.02E-07 2006.173.10:55:38.12:!2006.173.10:56:13 2006.173.10:56:13.00:data_valid=off 2006.173.10:56:13.00:"et 2006.173.10:56:13.00:!+3s 2006.173.10:56:16.01:"tape 2006.173.10:56:16.01:postob 2006.173.10:56:16.12/cable/+6.5012E-03 2006.173.10:56:16.12/wx/22.57,1004.0,92 2006.173.10:56:17.08/fmout-gps/S +4.01E-07 2006.173.10:56:17.08:scan_name=173-1058,jd0606,90 2006.173.10:56:17.08:source=3c274,123049.42,122328.0,2000.0,cw 2006.173.10:56:18.14#flagr#flagr/antenna,new-source 2006.173.10:56:18.14:checkk5 2006.173.10:56:18.56/chk_autoobs//k5ts1/ autoobs is running! 2006.173.10:56:18.95/chk_autoobs//k5ts2/ autoobs is running! 2006.173.10:56:19.36/chk_autoobs//k5ts3/ autoobs is running! 2006.173.10:56:19.74/chk_autoobs//k5ts4/ autoobs is running! 2006.173.10:56:20.14/chk_obsdata//k5ts1/T1731055??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.173.10:56:20.56/chk_obsdata//k5ts2/T1731055??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.173.10:56:20.95/chk_obsdata//k5ts3/T1731055??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.173.10:56:21.34/chk_obsdata//k5ts4/T1731055??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.173.10:56:22.05/k5log//k5ts1_log_newline 2006.173.10:56:22.76/k5log//k5ts2_log_newline 2006.173.10:56:23.46/k5log//k5ts3_log_newline 2006.173.10:56:24.16/k5log//k5ts4_log_newline 2006.173.10:56:24.19/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.10:56:24.19:setupk4=1 2006.173.10:56:24.19$setupk4/echo=on 2006.173.10:56:24.19$setupk4/pcalon 2006.173.10:56:24.19$pcalon/"no phase cal control is implemented here 2006.173.10:56:24.19$setupk4/"tpicd=stop 2006.173.10:56:24.19$setupk4/"rec=synch_on 2006.173.10:56:24.19$setupk4/"rec_mode=128 2006.173.10:56:24.19$setupk4/!* 2006.173.10:56:24.19$setupk4/recpk4 2006.173.10:56:24.19$recpk4/recpatch= 2006.173.10:56:24.19$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.10:56:24.19$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.10:56:24.20$setupk4/vck44 2006.173.10:56:24.20$vck44/valo=1,524.99 2006.173.10:56:24.20#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.10:56:24.20#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.10:56:24.20#ibcon#ireg 17 cls_cnt 0 2006.173.10:56:24.20#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.10:56:24.20#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.10:56:24.20#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.10:56:24.20#ibcon#enter wrdev, iclass 34, count 0 2006.173.10:56:24.20#ibcon#first serial, iclass 34, count 0 2006.173.10:56:24.20#ibcon#enter sib2, iclass 34, count 0 2006.173.10:56:24.20#ibcon#flushed, iclass 34, count 0 2006.173.10:56:24.20#ibcon#about to write, iclass 34, count 0 2006.173.10:56:24.20#ibcon#wrote, iclass 34, count 0 2006.173.10:56:24.20#ibcon#about to read 3, iclass 34, count 0 2006.173.10:56:24.22#ibcon#read 3, iclass 34, count 0 2006.173.10:56:24.22#ibcon#about to read 4, iclass 34, count 0 2006.173.10:56:24.22#ibcon#read 4, iclass 34, count 0 2006.173.10:56:24.22#ibcon#about to read 5, iclass 34, count 0 2006.173.10:56:24.22#ibcon#read 5, iclass 34, count 0 2006.173.10:56:24.22#ibcon#about to read 6, iclass 34, count 0 2006.173.10:56:24.22#ibcon#read 6, iclass 34, count 0 2006.173.10:56:24.22#ibcon#end of sib2, iclass 34, count 0 2006.173.10:56:24.22#ibcon#*mode == 0, iclass 34, count 0 2006.173.10:56:24.22#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.10:56:24.22#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.10:56:24.22#ibcon#*before write, iclass 34, count 0 2006.173.10:56:24.22#ibcon#enter sib2, iclass 34, count 0 2006.173.10:56:24.22#ibcon#flushed, iclass 34, count 0 2006.173.10:56:24.22#ibcon#about to write, iclass 34, count 0 2006.173.10:56:24.22#ibcon#wrote, iclass 34, count 0 2006.173.10:56:24.22#ibcon#about to read 3, iclass 34, count 0 2006.173.10:56:24.27#ibcon#read 3, iclass 34, count 0 2006.173.10:56:24.27#ibcon#about to read 4, iclass 34, count 0 2006.173.10:56:24.27#ibcon#read 4, iclass 34, count 0 2006.173.10:56:24.27#ibcon#about to read 5, iclass 34, count 0 2006.173.10:56:24.27#ibcon#read 5, iclass 34, count 0 2006.173.10:56:24.27#ibcon#about to read 6, iclass 34, count 0 2006.173.10:56:24.27#ibcon#read 6, iclass 34, count 0 2006.173.10:56:24.27#ibcon#end of sib2, iclass 34, count 0 2006.173.10:56:24.27#ibcon#*after write, iclass 34, count 0 2006.173.10:56:24.27#ibcon#*before return 0, iclass 34, count 0 2006.173.10:56:24.27#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.10:56:24.27#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.10:56:24.27#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.10:56:24.27#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.10:56:24.27$vck44/va=1,7 2006.173.10:56:24.27#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.10:56:24.27#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.10:56:24.27#ibcon#ireg 11 cls_cnt 2 2006.173.10:56:24.27#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.10:56:24.27#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.10:56:24.27#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.10:56:24.27#ibcon#enter wrdev, iclass 36, count 2 2006.173.10:56:24.27#ibcon#first serial, iclass 36, count 2 2006.173.10:56:24.27#ibcon#enter sib2, iclass 36, count 2 2006.173.10:56:24.27#ibcon#flushed, iclass 36, count 2 2006.173.10:56:24.27#ibcon#about to write, iclass 36, count 2 2006.173.10:56:24.27#ibcon#wrote, iclass 36, count 2 2006.173.10:56:24.27#ibcon#about to read 3, iclass 36, count 2 2006.173.10:56:24.29#ibcon#read 3, iclass 36, count 2 2006.173.10:56:24.29#ibcon#about to read 4, iclass 36, count 2 2006.173.10:56:24.29#ibcon#read 4, iclass 36, count 2 2006.173.10:56:24.29#ibcon#about to read 5, iclass 36, count 2 2006.173.10:56:24.29#ibcon#read 5, iclass 36, count 2 2006.173.10:56:24.29#ibcon#about to read 6, iclass 36, count 2 2006.173.10:56:24.29#ibcon#read 6, iclass 36, count 2 2006.173.10:56:24.29#ibcon#end of sib2, iclass 36, count 2 2006.173.10:56:24.29#ibcon#*mode == 0, iclass 36, count 2 2006.173.10:56:24.29#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.10:56:24.29#ibcon#[25=AT01-07\r\n] 2006.173.10:56:24.29#ibcon#*before write, iclass 36, count 2 2006.173.10:56:24.29#ibcon#enter sib2, iclass 36, count 2 2006.173.10:56:24.29#ibcon#flushed, iclass 36, count 2 2006.173.10:56:24.29#ibcon#about to write, iclass 36, count 2 2006.173.10:56:24.29#ibcon#wrote, iclass 36, count 2 2006.173.10:56:24.29#ibcon#about to read 3, iclass 36, count 2 2006.173.10:56:24.32#ibcon#read 3, iclass 36, count 2 2006.173.10:56:24.32#ibcon#about to read 4, iclass 36, count 2 2006.173.10:56:24.32#ibcon#read 4, iclass 36, count 2 2006.173.10:56:24.32#ibcon#about to read 5, iclass 36, count 2 2006.173.10:56:24.32#ibcon#read 5, iclass 36, count 2 2006.173.10:56:24.32#ibcon#about to read 6, iclass 36, count 2 2006.173.10:56:24.32#ibcon#read 6, iclass 36, count 2 2006.173.10:56:24.32#ibcon#end of sib2, iclass 36, count 2 2006.173.10:56:24.32#ibcon#*after write, iclass 36, count 2 2006.173.10:56:24.32#ibcon#*before return 0, iclass 36, count 2 2006.173.10:56:24.32#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.10:56:24.32#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.10:56:24.32#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.10:56:24.32#ibcon#ireg 7 cls_cnt 0 2006.173.10:56:24.32#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.10:56:24.44#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.10:56:24.44#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.10:56:24.44#ibcon#enter wrdev, iclass 36, count 0 2006.173.10:56:24.44#ibcon#first serial, iclass 36, count 0 2006.173.10:56:24.44#ibcon#enter sib2, iclass 36, count 0 2006.173.10:56:24.44#ibcon#flushed, iclass 36, count 0 2006.173.10:56:24.44#ibcon#about to write, iclass 36, count 0 2006.173.10:56:24.44#ibcon#wrote, iclass 36, count 0 2006.173.10:56:24.44#ibcon#about to read 3, iclass 36, count 0 2006.173.10:56:24.46#ibcon#read 3, iclass 36, count 0 2006.173.10:56:24.46#ibcon#about to read 4, iclass 36, count 0 2006.173.10:56:24.46#ibcon#read 4, iclass 36, count 0 2006.173.10:56:24.46#ibcon#about to read 5, iclass 36, count 0 2006.173.10:56:24.46#ibcon#read 5, iclass 36, count 0 2006.173.10:56:24.46#ibcon#about to read 6, iclass 36, count 0 2006.173.10:56:24.46#ibcon#read 6, iclass 36, count 0 2006.173.10:56:24.46#ibcon#end of sib2, iclass 36, count 0 2006.173.10:56:24.46#ibcon#*mode == 0, iclass 36, count 0 2006.173.10:56:24.46#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.10:56:24.46#ibcon#[25=USB\r\n] 2006.173.10:56:24.46#ibcon#*before write, iclass 36, count 0 2006.173.10:56:24.46#ibcon#enter sib2, iclass 36, count 0 2006.173.10:56:24.46#ibcon#flushed, iclass 36, count 0 2006.173.10:56:24.46#ibcon#about to write, iclass 36, count 0 2006.173.10:56:24.46#ibcon#wrote, iclass 36, count 0 2006.173.10:56:24.46#ibcon#about to read 3, iclass 36, count 0 2006.173.10:56:24.49#ibcon#read 3, iclass 36, count 0 2006.173.10:56:24.49#ibcon#about to read 4, iclass 36, count 0 2006.173.10:56:24.49#ibcon#read 4, iclass 36, count 0 2006.173.10:56:24.49#ibcon#about to read 5, iclass 36, count 0 2006.173.10:56:24.49#ibcon#read 5, iclass 36, count 0 2006.173.10:56:24.49#ibcon#about to read 6, iclass 36, count 0 2006.173.10:56:24.49#ibcon#read 6, iclass 36, count 0 2006.173.10:56:24.49#ibcon#end of sib2, iclass 36, count 0 2006.173.10:56:24.49#ibcon#*after write, iclass 36, count 0 2006.173.10:56:24.49#ibcon#*before return 0, iclass 36, count 0 2006.173.10:56:24.49#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.10:56:24.49#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.10:56:24.49#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.10:56:24.49#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.10:56:24.49$vck44/valo=2,534.99 2006.173.10:56:24.49#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.10:56:24.49#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.10:56:24.49#ibcon#ireg 17 cls_cnt 0 2006.173.10:56:24.49#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.10:56:24.49#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.10:56:24.49#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.10:56:24.49#ibcon#enter wrdev, iclass 38, count 0 2006.173.10:56:24.49#ibcon#first serial, iclass 38, count 0 2006.173.10:56:24.49#ibcon#enter sib2, iclass 38, count 0 2006.173.10:56:24.49#ibcon#flushed, iclass 38, count 0 2006.173.10:56:24.49#ibcon#about to write, iclass 38, count 0 2006.173.10:56:24.49#ibcon#wrote, iclass 38, count 0 2006.173.10:56:24.49#ibcon#about to read 3, iclass 38, count 0 2006.173.10:56:24.51#ibcon#read 3, iclass 38, count 0 2006.173.10:56:24.51#ibcon#about to read 4, iclass 38, count 0 2006.173.10:56:24.51#ibcon#read 4, iclass 38, count 0 2006.173.10:56:24.51#ibcon#about to read 5, iclass 38, count 0 2006.173.10:56:24.51#ibcon#read 5, iclass 38, count 0 2006.173.10:56:24.51#ibcon#about to read 6, iclass 38, count 0 2006.173.10:56:24.51#ibcon#read 6, iclass 38, count 0 2006.173.10:56:24.51#ibcon#end of sib2, iclass 38, count 0 2006.173.10:56:24.51#ibcon#*mode == 0, iclass 38, count 0 2006.173.10:56:24.51#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.10:56:24.51#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.10:56:24.51#ibcon#*before write, iclass 38, count 0 2006.173.10:56:24.51#ibcon#enter sib2, iclass 38, count 0 2006.173.10:56:24.51#ibcon#flushed, iclass 38, count 0 2006.173.10:56:24.51#ibcon#about to write, iclass 38, count 0 2006.173.10:56:24.51#ibcon#wrote, iclass 38, count 0 2006.173.10:56:24.51#ibcon#about to read 3, iclass 38, count 0 2006.173.10:56:24.55#ibcon#read 3, iclass 38, count 0 2006.173.10:56:24.55#ibcon#about to read 4, iclass 38, count 0 2006.173.10:56:24.55#ibcon#read 4, iclass 38, count 0 2006.173.10:56:24.55#ibcon#about to read 5, iclass 38, count 0 2006.173.10:56:24.55#ibcon#read 5, iclass 38, count 0 2006.173.10:56:24.55#ibcon#about to read 6, iclass 38, count 0 2006.173.10:56:24.55#ibcon#read 6, iclass 38, count 0 2006.173.10:56:24.55#ibcon#end of sib2, iclass 38, count 0 2006.173.10:56:24.55#ibcon#*after write, iclass 38, count 0 2006.173.10:56:24.55#ibcon#*before return 0, iclass 38, count 0 2006.173.10:56:24.55#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.10:56:24.55#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.10:56:24.55#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.10:56:24.55#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.10:56:24.55$vck44/va=2,6 2006.173.10:56:24.55#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.10:56:24.55#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.10:56:24.55#ibcon#ireg 11 cls_cnt 2 2006.173.10:56:24.55#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.10:56:24.61#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.10:56:24.61#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.10:56:24.61#ibcon#enter wrdev, iclass 40, count 2 2006.173.10:56:24.61#ibcon#first serial, iclass 40, count 2 2006.173.10:56:24.61#ibcon#enter sib2, iclass 40, count 2 2006.173.10:56:24.61#ibcon#flushed, iclass 40, count 2 2006.173.10:56:24.61#ibcon#about to write, iclass 40, count 2 2006.173.10:56:24.61#ibcon#wrote, iclass 40, count 2 2006.173.10:56:24.61#ibcon#about to read 3, iclass 40, count 2 2006.173.10:56:24.63#ibcon#read 3, iclass 40, count 2 2006.173.10:56:24.63#ibcon#about to read 4, iclass 40, count 2 2006.173.10:56:24.63#ibcon#read 4, iclass 40, count 2 2006.173.10:56:24.63#ibcon#about to read 5, iclass 40, count 2 2006.173.10:56:24.63#ibcon#read 5, iclass 40, count 2 2006.173.10:56:24.63#ibcon#about to read 6, iclass 40, count 2 2006.173.10:56:24.63#ibcon#read 6, iclass 40, count 2 2006.173.10:56:24.63#ibcon#end of sib2, iclass 40, count 2 2006.173.10:56:24.63#ibcon#*mode == 0, iclass 40, count 2 2006.173.10:56:24.63#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.10:56:24.63#ibcon#[25=AT02-06\r\n] 2006.173.10:56:24.63#ibcon#*before write, iclass 40, count 2 2006.173.10:56:24.63#ibcon#enter sib2, iclass 40, count 2 2006.173.10:56:24.63#ibcon#flushed, iclass 40, count 2 2006.173.10:56:24.63#ibcon#about to write, iclass 40, count 2 2006.173.10:56:24.63#ibcon#wrote, iclass 40, count 2 2006.173.10:56:24.63#ibcon#about to read 3, iclass 40, count 2 2006.173.10:56:24.66#ibcon#read 3, iclass 40, count 2 2006.173.10:56:24.66#ibcon#about to read 4, iclass 40, count 2 2006.173.10:56:24.66#ibcon#read 4, iclass 40, count 2 2006.173.10:56:24.66#ibcon#about to read 5, iclass 40, count 2 2006.173.10:56:24.66#ibcon#read 5, iclass 40, count 2 2006.173.10:56:24.66#ibcon#about to read 6, iclass 40, count 2 2006.173.10:56:24.66#ibcon#read 6, iclass 40, count 2 2006.173.10:56:24.66#ibcon#end of sib2, iclass 40, count 2 2006.173.10:56:24.66#ibcon#*after write, iclass 40, count 2 2006.173.10:56:24.66#ibcon#*before return 0, iclass 40, count 2 2006.173.10:56:24.66#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.10:56:24.66#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.10:56:24.66#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.10:56:24.66#ibcon#ireg 7 cls_cnt 0 2006.173.10:56:24.66#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.10:56:24.78#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.10:56:24.78#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.10:56:24.78#ibcon#enter wrdev, iclass 40, count 0 2006.173.10:56:24.78#ibcon#first serial, iclass 40, count 0 2006.173.10:56:24.78#ibcon#enter sib2, iclass 40, count 0 2006.173.10:56:24.78#ibcon#flushed, iclass 40, count 0 2006.173.10:56:24.78#ibcon#about to write, iclass 40, count 0 2006.173.10:56:24.78#ibcon#wrote, iclass 40, count 0 2006.173.10:56:24.78#ibcon#about to read 3, iclass 40, count 0 2006.173.10:56:24.80#ibcon#read 3, iclass 40, count 0 2006.173.10:56:24.80#ibcon#about to read 4, iclass 40, count 0 2006.173.10:56:24.80#ibcon#read 4, iclass 40, count 0 2006.173.10:56:24.80#ibcon#about to read 5, iclass 40, count 0 2006.173.10:56:24.80#ibcon#read 5, iclass 40, count 0 2006.173.10:56:24.80#ibcon#about to read 6, iclass 40, count 0 2006.173.10:56:24.80#ibcon#read 6, iclass 40, count 0 2006.173.10:56:24.80#ibcon#end of sib2, iclass 40, count 0 2006.173.10:56:24.80#ibcon#*mode == 0, iclass 40, count 0 2006.173.10:56:24.80#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.10:56:24.80#ibcon#[25=USB\r\n] 2006.173.10:56:24.80#ibcon#*before write, iclass 40, count 0 2006.173.10:56:24.80#ibcon#enter sib2, iclass 40, count 0 2006.173.10:56:24.80#ibcon#flushed, iclass 40, count 0 2006.173.10:56:24.80#ibcon#about to write, iclass 40, count 0 2006.173.10:56:24.80#ibcon#wrote, iclass 40, count 0 2006.173.10:56:24.80#ibcon#about to read 3, iclass 40, count 0 2006.173.10:56:24.83#ibcon#read 3, iclass 40, count 0 2006.173.10:56:24.83#ibcon#about to read 4, iclass 40, count 0 2006.173.10:56:24.83#ibcon#read 4, iclass 40, count 0 2006.173.10:56:24.83#ibcon#about to read 5, iclass 40, count 0 2006.173.10:56:24.83#ibcon#read 5, iclass 40, count 0 2006.173.10:56:24.83#ibcon#about to read 6, iclass 40, count 0 2006.173.10:56:24.83#ibcon#read 6, iclass 40, count 0 2006.173.10:56:24.83#ibcon#end of sib2, iclass 40, count 0 2006.173.10:56:24.83#ibcon#*after write, iclass 40, count 0 2006.173.10:56:24.83#ibcon#*before return 0, iclass 40, count 0 2006.173.10:56:24.83#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.10:56:24.83#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.10:56:24.83#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.10:56:24.83#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.10:56:24.83$vck44/valo=3,564.99 2006.173.10:56:24.83#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.10:56:24.83#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.10:56:24.83#ibcon#ireg 17 cls_cnt 0 2006.173.10:56:24.83#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.10:56:24.83#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.10:56:24.83#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.10:56:24.83#ibcon#enter wrdev, iclass 4, count 0 2006.173.10:56:24.83#ibcon#first serial, iclass 4, count 0 2006.173.10:56:24.83#ibcon#enter sib2, iclass 4, count 0 2006.173.10:56:24.83#ibcon#flushed, iclass 4, count 0 2006.173.10:56:24.83#ibcon#about to write, iclass 4, count 0 2006.173.10:56:24.83#ibcon#wrote, iclass 4, count 0 2006.173.10:56:24.83#ibcon#about to read 3, iclass 4, count 0 2006.173.10:56:24.85#ibcon#read 3, iclass 4, count 0 2006.173.10:56:24.85#ibcon#about to read 4, iclass 4, count 0 2006.173.10:56:24.85#ibcon#read 4, iclass 4, count 0 2006.173.10:56:24.85#ibcon#about to read 5, iclass 4, count 0 2006.173.10:56:24.85#ibcon#read 5, iclass 4, count 0 2006.173.10:56:24.85#ibcon#about to read 6, iclass 4, count 0 2006.173.10:56:24.85#ibcon#read 6, iclass 4, count 0 2006.173.10:56:24.85#ibcon#end of sib2, iclass 4, count 0 2006.173.10:56:24.85#ibcon#*mode == 0, iclass 4, count 0 2006.173.10:56:24.85#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.10:56:24.85#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.10:56:24.85#ibcon#*before write, iclass 4, count 0 2006.173.10:56:24.85#ibcon#enter sib2, iclass 4, count 0 2006.173.10:56:24.85#ibcon#flushed, iclass 4, count 0 2006.173.10:56:24.85#ibcon#about to write, iclass 4, count 0 2006.173.10:56:24.85#ibcon#wrote, iclass 4, count 0 2006.173.10:56:24.85#ibcon#about to read 3, iclass 4, count 0 2006.173.10:56:24.89#ibcon#read 3, iclass 4, count 0 2006.173.10:56:24.89#ibcon#about to read 4, iclass 4, count 0 2006.173.10:56:24.89#ibcon#read 4, iclass 4, count 0 2006.173.10:56:24.89#ibcon#about to read 5, iclass 4, count 0 2006.173.10:56:24.89#ibcon#read 5, iclass 4, count 0 2006.173.10:56:24.89#ibcon#about to read 6, iclass 4, count 0 2006.173.10:56:24.89#ibcon#read 6, iclass 4, count 0 2006.173.10:56:24.89#ibcon#end of sib2, iclass 4, count 0 2006.173.10:56:24.89#ibcon#*after write, iclass 4, count 0 2006.173.10:56:24.89#ibcon#*before return 0, iclass 4, count 0 2006.173.10:56:24.89#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.10:56:24.89#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.10:56:24.89#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.10:56:24.89#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.10:56:24.89$vck44/va=3,5 2006.173.10:56:24.89#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.10:56:24.89#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.10:56:24.89#ibcon#ireg 11 cls_cnt 2 2006.173.10:56:24.89#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.10:56:24.95#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.10:56:24.95#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.10:56:24.95#ibcon#enter wrdev, iclass 6, count 2 2006.173.10:56:24.95#ibcon#first serial, iclass 6, count 2 2006.173.10:56:24.95#ibcon#enter sib2, iclass 6, count 2 2006.173.10:56:24.95#ibcon#flushed, iclass 6, count 2 2006.173.10:56:24.95#ibcon#about to write, iclass 6, count 2 2006.173.10:56:24.95#ibcon#wrote, iclass 6, count 2 2006.173.10:56:24.95#ibcon#about to read 3, iclass 6, count 2 2006.173.10:56:24.97#ibcon#read 3, iclass 6, count 2 2006.173.10:56:24.97#ibcon#about to read 4, iclass 6, count 2 2006.173.10:56:24.97#ibcon#read 4, iclass 6, count 2 2006.173.10:56:24.97#ibcon#about to read 5, iclass 6, count 2 2006.173.10:56:24.97#ibcon#read 5, iclass 6, count 2 2006.173.10:56:24.97#ibcon#about to read 6, iclass 6, count 2 2006.173.10:56:24.97#ibcon#read 6, iclass 6, count 2 2006.173.10:56:24.97#ibcon#end of sib2, iclass 6, count 2 2006.173.10:56:24.97#ibcon#*mode == 0, iclass 6, count 2 2006.173.10:56:24.97#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.10:56:24.97#ibcon#[25=AT03-05\r\n] 2006.173.10:56:24.97#ibcon#*before write, iclass 6, count 2 2006.173.10:56:24.97#ibcon#enter sib2, iclass 6, count 2 2006.173.10:56:24.97#ibcon#flushed, iclass 6, count 2 2006.173.10:56:24.97#ibcon#about to write, iclass 6, count 2 2006.173.10:56:24.97#ibcon#wrote, iclass 6, count 2 2006.173.10:56:24.97#ibcon#about to read 3, iclass 6, count 2 2006.173.10:56:25.00#ibcon#read 3, iclass 6, count 2 2006.173.10:56:25.00#ibcon#about to read 4, iclass 6, count 2 2006.173.10:56:25.00#ibcon#read 4, iclass 6, count 2 2006.173.10:56:25.00#ibcon#about to read 5, iclass 6, count 2 2006.173.10:56:25.00#ibcon#read 5, iclass 6, count 2 2006.173.10:56:25.00#ibcon#about to read 6, iclass 6, count 2 2006.173.10:56:25.00#ibcon#read 6, iclass 6, count 2 2006.173.10:56:25.00#ibcon#end of sib2, iclass 6, count 2 2006.173.10:56:25.00#ibcon#*after write, iclass 6, count 2 2006.173.10:56:25.00#ibcon#*before return 0, iclass 6, count 2 2006.173.10:56:25.00#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.10:56:25.00#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.10:56:25.00#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.10:56:25.00#ibcon#ireg 7 cls_cnt 0 2006.173.10:56:25.00#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.10:56:25.12#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.10:56:25.12#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.10:56:25.12#ibcon#enter wrdev, iclass 6, count 0 2006.173.10:56:25.12#ibcon#first serial, iclass 6, count 0 2006.173.10:56:25.12#ibcon#enter sib2, iclass 6, count 0 2006.173.10:56:25.12#ibcon#flushed, iclass 6, count 0 2006.173.10:56:25.12#ibcon#about to write, iclass 6, count 0 2006.173.10:56:25.12#ibcon#wrote, iclass 6, count 0 2006.173.10:56:25.12#ibcon#about to read 3, iclass 6, count 0 2006.173.10:56:25.14#ibcon#read 3, iclass 6, count 0 2006.173.10:56:25.14#ibcon#about to read 4, iclass 6, count 0 2006.173.10:56:25.14#ibcon#read 4, iclass 6, count 0 2006.173.10:56:25.14#ibcon#about to read 5, iclass 6, count 0 2006.173.10:56:25.14#ibcon#read 5, iclass 6, count 0 2006.173.10:56:25.14#ibcon#about to read 6, iclass 6, count 0 2006.173.10:56:25.14#ibcon#read 6, iclass 6, count 0 2006.173.10:56:25.14#ibcon#end of sib2, iclass 6, count 0 2006.173.10:56:25.14#ibcon#*mode == 0, iclass 6, count 0 2006.173.10:56:25.14#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.10:56:25.14#ibcon#[25=USB\r\n] 2006.173.10:56:25.14#ibcon#*before write, iclass 6, count 0 2006.173.10:56:25.14#ibcon#enter sib2, iclass 6, count 0 2006.173.10:56:25.14#ibcon#flushed, iclass 6, count 0 2006.173.10:56:25.14#ibcon#about to write, iclass 6, count 0 2006.173.10:56:25.14#ibcon#wrote, iclass 6, count 0 2006.173.10:56:25.14#ibcon#about to read 3, iclass 6, count 0 2006.173.10:56:25.17#ibcon#read 3, iclass 6, count 0 2006.173.10:56:25.17#ibcon#about to read 4, iclass 6, count 0 2006.173.10:56:25.17#ibcon#read 4, iclass 6, count 0 2006.173.10:56:25.17#ibcon#about to read 5, iclass 6, count 0 2006.173.10:56:25.17#ibcon#read 5, iclass 6, count 0 2006.173.10:56:25.17#ibcon#about to read 6, iclass 6, count 0 2006.173.10:56:25.17#ibcon#read 6, iclass 6, count 0 2006.173.10:56:25.17#ibcon#end of sib2, iclass 6, count 0 2006.173.10:56:25.17#ibcon#*after write, iclass 6, count 0 2006.173.10:56:25.17#ibcon#*before return 0, iclass 6, count 0 2006.173.10:56:25.17#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.10:56:25.17#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.10:56:25.17#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.10:56:25.17#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.10:56:25.17$vck44/valo=4,624.99 2006.173.10:56:25.17#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.10:56:25.17#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.10:56:25.17#ibcon#ireg 17 cls_cnt 0 2006.173.10:56:25.17#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.10:56:25.17#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.10:56:25.17#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.10:56:25.17#ibcon#enter wrdev, iclass 10, count 0 2006.173.10:56:25.17#ibcon#first serial, iclass 10, count 0 2006.173.10:56:25.17#ibcon#enter sib2, iclass 10, count 0 2006.173.10:56:25.17#ibcon#flushed, iclass 10, count 0 2006.173.10:56:25.17#ibcon#about to write, iclass 10, count 0 2006.173.10:56:25.17#ibcon#wrote, iclass 10, count 0 2006.173.10:56:25.17#ibcon#about to read 3, iclass 10, count 0 2006.173.10:56:25.19#ibcon#read 3, iclass 10, count 0 2006.173.10:56:25.19#ibcon#about to read 4, iclass 10, count 0 2006.173.10:56:25.19#ibcon#read 4, iclass 10, count 0 2006.173.10:56:25.19#ibcon#about to read 5, iclass 10, count 0 2006.173.10:56:25.19#ibcon#read 5, iclass 10, count 0 2006.173.10:56:25.19#ibcon#about to read 6, iclass 10, count 0 2006.173.10:56:25.19#ibcon#read 6, iclass 10, count 0 2006.173.10:56:25.19#ibcon#end of sib2, iclass 10, count 0 2006.173.10:56:25.19#ibcon#*mode == 0, iclass 10, count 0 2006.173.10:56:25.19#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.10:56:25.19#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.10:56:25.19#ibcon#*before write, iclass 10, count 0 2006.173.10:56:25.19#ibcon#enter sib2, iclass 10, count 0 2006.173.10:56:25.19#ibcon#flushed, iclass 10, count 0 2006.173.10:56:25.19#ibcon#about to write, iclass 10, count 0 2006.173.10:56:25.19#ibcon#wrote, iclass 10, count 0 2006.173.10:56:25.19#ibcon#about to read 3, iclass 10, count 0 2006.173.10:56:25.23#ibcon#read 3, iclass 10, count 0 2006.173.10:56:25.23#ibcon#about to read 4, iclass 10, count 0 2006.173.10:56:25.23#ibcon#read 4, iclass 10, count 0 2006.173.10:56:25.23#ibcon#about to read 5, iclass 10, count 0 2006.173.10:56:25.23#ibcon#read 5, iclass 10, count 0 2006.173.10:56:25.23#ibcon#about to read 6, iclass 10, count 0 2006.173.10:56:25.23#ibcon#read 6, iclass 10, count 0 2006.173.10:56:25.23#ibcon#end of sib2, iclass 10, count 0 2006.173.10:56:25.23#ibcon#*after write, iclass 10, count 0 2006.173.10:56:25.23#ibcon#*before return 0, iclass 10, count 0 2006.173.10:56:25.23#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.10:56:25.23#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.10:56:25.23#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.10:56:25.23#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.10:56:25.23$vck44/va=4,6 2006.173.10:56:25.23#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.10:56:25.23#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.10:56:25.23#ibcon#ireg 11 cls_cnt 2 2006.173.10:56:25.23#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.10:56:25.29#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.10:56:25.29#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.10:56:25.29#ibcon#enter wrdev, iclass 12, count 2 2006.173.10:56:25.29#ibcon#first serial, iclass 12, count 2 2006.173.10:56:25.29#ibcon#enter sib2, iclass 12, count 2 2006.173.10:56:25.29#ibcon#flushed, iclass 12, count 2 2006.173.10:56:25.29#ibcon#about to write, iclass 12, count 2 2006.173.10:56:25.29#ibcon#wrote, iclass 12, count 2 2006.173.10:56:25.29#ibcon#about to read 3, iclass 12, count 2 2006.173.10:56:25.31#ibcon#read 3, iclass 12, count 2 2006.173.10:56:25.31#ibcon#about to read 4, iclass 12, count 2 2006.173.10:56:25.31#ibcon#read 4, iclass 12, count 2 2006.173.10:56:25.31#ibcon#about to read 5, iclass 12, count 2 2006.173.10:56:25.31#ibcon#read 5, iclass 12, count 2 2006.173.10:56:25.31#ibcon#about to read 6, iclass 12, count 2 2006.173.10:56:25.31#ibcon#read 6, iclass 12, count 2 2006.173.10:56:25.31#ibcon#end of sib2, iclass 12, count 2 2006.173.10:56:25.31#ibcon#*mode == 0, iclass 12, count 2 2006.173.10:56:25.31#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.10:56:25.31#ibcon#[25=AT04-06\r\n] 2006.173.10:56:25.31#ibcon#*before write, iclass 12, count 2 2006.173.10:56:25.31#ibcon#enter sib2, iclass 12, count 2 2006.173.10:56:25.31#ibcon#flushed, iclass 12, count 2 2006.173.10:56:25.31#ibcon#about to write, iclass 12, count 2 2006.173.10:56:25.31#ibcon#wrote, iclass 12, count 2 2006.173.10:56:25.31#ibcon#about to read 3, iclass 12, count 2 2006.173.10:56:25.34#ibcon#read 3, iclass 12, count 2 2006.173.10:56:25.34#ibcon#about to read 4, iclass 12, count 2 2006.173.10:56:25.34#ibcon#read 4, iclass 12, count 2 2006.173.10:56:25.34#ibcon#about to read 5, iclass 12, count 2 2006.173.10:56:25.34#ibcon#read 5, iclass 12, count 2 2006.173.10:56:25.34#ibcon#about to read 6, iclass 12, count 2 2006.173.10:56:25.34#ibcon#read 6, iclass 12, count 2 2006.173.10:56:25.34#ibcon#end of sib2, iclass 12, count 2 2006.173.10:56:25.34#ibcon#*after write, iclass 12, count 2 2006.173.10:56:25.34#ibcon#*before return 0, iclass 12, count 2 2006.173.10:56:25.34#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.10:56:25.34#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.10:56:25.34#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.10:56:25.34#ibcon#ireg 7 cls_cnt 0 2006.173.10:56:25.34#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.10:56:25.46#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.10:56:25.46#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.10:56:25.46#ibcon#enter wrdev, iclass 12, count 0 2006.173.10:56:25.46#ibcon#first serial, iclass 12, count 0 2006.173.10:56:25.46#ibcon#enter sib2, iclass 12, count 0 2006.173.10:56:25.46#ibcon#flushed, iclass 12, count 0 2006.173.10:56:25.46#ibcon#about to write, iclass 12, count 0 2006.173.10:56:25.46#ibcon#wrote, iclass 12, count 0 2006.173.10:56:25.46#ibcon#about to read 3, iclass 12, count 0 2006.173.10:56:25.48#ibcon#read 3, iclass 12, count 0 2006.173.10:56:25.48#ibcon#about to read 4, iclass 12, count 0 2006.173.10:56:25.48#ibcon#read 4, iclass 12, count 0 2006.173.10:56:25.48#ibcon#about to read 5, iclass 12, count 0 2006.173.10:56:25.48#ibcon#read 5, iclass 12, count 0 2006.173.10:56:25.48#ibcon#about to read 6, iclass 12, count 0 2006.173.10:56:25.48#ibcon#read 6, iclass 12, count 0 2006.173.10:56:25.48#ibcon#end of sib2, iclass 12, count 0 2006.173.10:56:25.48#ibcon#*mode == 0, iclass 12, count 0 2006.173.10:56:25.48#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.10:56:25.48#ibcon#[25=USB\r\n] 2006.173.10:56:25.48#ibcon#*before write, iclass 12, count 0 2006.173.10:56:25.48#ibcon#enter sib2, iclass 12, count 0 2006.173.10:56:25.48#ibcon#flushed, iclass 12, count 0 2006.173.10:56:25.48#ibcon#about to write, iclass 12, count 0 2006.173.10:56:25.48#ibcon#wrote, iclass 12, count 0 2006.173.10:56:25.48#ibcon#about to read 3, iclass 12, count 0 2006.173.10:56:25.51#ibcon#read 3, iclass 12, count 0 2006.173.10:56:25.51#ibcon#about to read 4, iclass 12, count 0 2006.173.10:56:25.51#ibcon#read 4, iclass 12, count 0 2006.173.10:56:25.51#ibcon#about to read 5, iclass 12, count 0 2006.173.10:56:25.51#ibcon#read 5, iclass 12, count 0 2006.173.10:56:25.51#ibcon#about to read 6, iclass 12, count 0 2006.173.10:56:25.51#ibcon#read 6, iclass 12, count 0 2006.173.10:56:25.51#ibcon#end of sib2, iclass 12, count 0 2006.173.10:56:25.51#ibcon#*after write, iclass 12, count 0 2006.173.10:56:25.51#ibcon#*before return 0, iclass 12, count 0 2006.173.10:56:25.51#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.10:56:25.51#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.10:56:25.51#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.10:56:25.51#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.10:56:25.51$vck44/valo=5,734.99 2006.173.10:56:25.51#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.10:56:25.51#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.10:56:25.51#ibcon#ireg 17 cls_cnt 0 2006.173.10:56:25.51#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.10:56:25.51#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.10:56:25.51#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.10:56:25.51#ibcon#enter wrdev, iclass 14, count 0 2006.173.10:56:25.51#ibcon#first serial, iclass 14, count 0 2006.173.10:56:25.51#ibcon#enter sib2, iclass 14, count 0 2006.173.10:56:25.51#ibcon#flushed, iclass 14, count 0 2006.173.10:56:25.51#ibcon#about to write, iclass 14, count 0 2006.173.10:56:25.51#ibcon#wrote, iclass 14, count 0 2006.173.10:56:25.51#ibcon#about to read 3, iclass 14, count 0 2006.173.10:56:25.53#ibcon#read 3, iclass 14, count 0 2006.173.10:56:25.53#ibcon#about to read 4, iclass 14, count 0 2006.173.10:56:25.53#ibcon#read 4, iclass 14, count 0 2006.173.10:56:25.53#ibcon#about to read 5, iclass 14, count 0 2006.173.10:56:25.53#ibcon#read 5, iclass 14, count 0 2006.173.10:56:25.53#ibcon#about to read 6, iclass 14, count 0 2006.173.10:56:25.53#ibcon#read 6, iclass 14, count 0 2006.173.10:56:25.53#ibcon#end of sib2, iclass 14, count 0 2006.173.10:56:25.53#ibcon#*mode == 0, iclass 14, count 0 2006.173.10:56:25.53#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.10:56:25.53#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.10:56:25.53#ibcon#*before write, iclass 14, count 0 2006.173.10:56:25.53#ibcon#enter sib2, iclass 14, count 0 2006.173.10:56:25.53#ibcon#flushed, iclass 14, count 0 2006.173.10:56:25.53#ibcon#about to write, iclass 14, count 0 2006.173.10:56:25.53#ibcon#wrote, iclass 14, count 0 2006.173.10:56:25.53#ibcon#about to read 3, iclass 14, count 0 2006.173.10:56:25.57#ibcon#read 3, iclass 14, count 0 2006.173.10:56:25.57#ibcon#about to read 4, iclass 14, count 0 2006.173.10:56:25.57#ibcon#read 4, iclass 14, count 0 2006.173.10:56:25.57#ibcon#about to read 5, iclass 14, count 0 2006.173.10:56:25.57#ibcon#read 5, iclass 14, count 0 2006.173.10:56:25.57#ibcon#about to read 6, iclass 14, count 0 2006.173.10:56:25.57#ibcon#read 6, iclass 14, count 0 2006.173.10:56:25.57#ibcon#end of sib2, iclass 14, count 0 2006.173.10:56:25.57#ibcon#*after write, iclass 14, count 0 2006.173.10:56:25.57#ibcon#*before return 0, iclass 14, count 0 2006.173.10:56:25.57#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.10:56:25.57#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.10:56:25.57#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.10:56:25.57#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.10:56:25.57$vck44/va=5,4 2006.173.10:56:25.57#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.10:56:25.57#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.10:56:25.57#ibcon#ireg 11 cls_cnt 2 2006.173.10:56:25.57#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.10:56:25.63#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.10:56:25.63#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.10:56:25.63#ibcon#enter wrdev, iclass 16, count 2 2006.173.10:56:25.63#ibcon#first serial, iclass 16, count 2 2006.173.10:56:25.63#ibcon#enter sib2, iclass 16, count 2 2006.173.10:56:25.63#ibcon#flushed, iclass 16, count 2 2006.173.10:56:25.63#ibcon#about to write, iclass 16, count 2 2006.173.10:56:25.63#ibcon#wrote, iclass 16, count 2 2006.173.10:56:25.63#ibcon#about to read 3, iclass 16, count 2 2006.173.10:56:25.65#ibcon#read 3, iclass 16, count 2 2006.173.10:56:25.65#ibcon#about to read 4, iclass 16, count 2 2006.173.10:56:25.65#ibcon#read 4, iclass 16, count 2 2006.173.10:56:25.65#ibcon#about to read 5, iclass 16, count 2 2006.173.10:56:25.65#ibcon#read 5, iclass 16, count 2 2006.173.10:56:25.65#ibcon#about to read 6, iclass 16, count 2 2006.173.10:56:25.65#ibcon#read 6, iclass 16, count 2 2006.173.10:56:25.65#ibcon#end of sib2, iclass 16, count 2 2006.173.10:56:25.65#ibcon#*mode == 0, iclass 16, count 2 2006.173.10:56:25.65#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.10:56:25.65#ibcon#[25=AT05-04\r\n] 2006.173.10:56:25.65#ibcon#*before write, iclass 16, count 2 2006.173.10:56:25.65#ibcon#enter sib2, iclass 16, count 2 2006.173.10:56:25.65#ibcon#flushed, iclass 16, count 2 2006.173.10:56:25.65#ibcon#about to write, iclass 16, count 2 2006.173.10:56:25.65#ibcon#wrote, iclass 16, count 2 2006.173.10:56:25.65#ibcon#about to read 3, iclass 16, count 2 2006.173.10:56:25.68#ibcon#read 3, iclass 16, count 2 2006.173.10:56:25.68#ibcon#about to read 4, iclass 16, count 2 2006.173.10:56:25.68#ibcon#read 4, iclass 16, count 2 2006.173.10:56:25.68#ibcon#about to read 5, iclass 16, count 2 2006.173.10:56:25.68#ibcon#read 5, iclass 16, count 2 2006.173.10:56:25.68#ibcon#about to read 6, iclass 16, count 2 2006.173.10:56:25.68#ibcon#read 6, iclass 16, count 2 2006.173.10:56:25.68#ibcon#end of sib2, iclass 16, count 2 2006.173.10:56:25.68#ibcon#*after write, iclass 16, count 2 2006.173.10:56:25.68#ibcon#*before return 0, iclass 16, count 2 2006.173.10:56:25.68#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.10:56:25.68#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.10:56:25.68#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.10:56:25.68#ibcon#ireg 7 cls_cnt 0 2006.173.10:56:25.68#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.10:56:25.80#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.10:56:25.80#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.10:56:25.80#ibcon#enter wrdev, iclass 16, count 0 2006.173.10:56:25.80#ibcon#first serial, iclass 16, count 0 2006.173.10:56:25.80#ibcon#enter sib2, iclass 16, count 0 2006.173.10:56:25.80#ibcon#flushed, iclass 16, count 0 2006.173.10:56:25.80#ibcon#about to write, iclass 16, count 0 2006.173.10:56:25.80#ibcon#wrote, iclass 16, count 0 2006.173.10:56:25.80#ibcon#about to read 3, iclass 16, count 0 2006.173.10:56:25.82#ibcon#read 3, iclass 16, count 0 2006.173.10:56:25.82#ibcon#about to read 4, iclass 16, count 0 2006.173.10:56:25.82#ibcon#read 4, iclass 16, count 0 2006.173.10:56:25.82#ibcon#about to read 5, iclass 16, count 0 2006.173.10:56:25.82#ibcon#read 5, iclass 16, count 0 2006.173.10:56:25.82#ibcon#about to read 6, iclass 16, count 0 2006.173.10:56:25.82#ibcon#read 6, iclass 16, count 0 2006.173.10:56:25.82#ibcon#end of sib2, iclass 16, count 0 2006.173.10:56:25.82#ibcon#*mode == 0, iclass 16, count 0 2006.173.10:56:25.82#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.10:56:25.82#ibcon#[25=USB\r\n] 2006.173.10:56:25.82#ibcon#*before write, iclass 16, count 0 2006.173.10:56:25.82#ibcon#enter sib2, iclass 16, count 0 2006.173.10:56:25.82#ibcon#flushed, iclass 16, count 0 2006.173.10:56:25.82#ibcon#about to write, iclass 16, count 0 2006.173.10:56:25.82#ibcon#wrote, iclass 16, count 0 2006.173.10:56:25.82#ibcon#about to read 3, iclass 16, count 0 2006.173.10:56:25.85#ibcon#read 3, iclass 16, count 0 2006.173.10:56:25.85#ibcon#about to read 4, iclass 16, count 0 2006.173.10:56:25.85#ibcon#read 4, iclass 16, count 0 2006.173.10:56:25.85#ibcon#about to read 5, iclass 16, count 0 2006.173.10:56:25.85#ibcon#read 5, iclass 16, count 0 2006.173.10:56:25.85#ibcon#about to read 6, iclass 16, count 0 2006.173.10:56:25.85#ibcon#read 6, iclass 16, count 0 2006.173.10:56:25.85#ibcon#end of sib2, iclass 16, count 0 2006.173.10:56:25.85#ibcon#*after write, iclass 16, count 0 2006.173.10:56:25.85#ibcon#*before return 0, iclass 16, count 0 2006.173.10:56:25.85#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.10:56:25.85#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.10:56:25.85#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.10:56:25.85#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.10:56:25.85$vck44/valo=6,814.99 2006.173.10:56:25.85#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.10:56:25.85#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.10:56:25.85#ibcon#ireg 17 cls_cnt 0 2006.173.10:56:25.85#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.10:56:25.85#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.10:56:25.85#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.10:56:25.85#ibcon#enter wrdev, iclass 18, count 0 2006.173.10:56:25.85#ibcon#first serial, iclass 18, count 0 2006.173.10:56:25.85#ibcon#enter sib2, iclass 18, count 0 2006.173.10:56:25.85#ibcon#flushed, iclass 18, count 0 2006.173.10:56:25.85#ibcon#about to write, iclass 18, count 0 2006.173.10:56:25.85#ibcon#wrote, iclass 18, count 0 2006.173.10:56:25.85#ibcon#about to read 3, iclass 18, count 0 2006.173.10:56:25.87#ibcon#read 3, iclass 18, count 0 2006.173.10:56:25.87#ibcon#about to read 4, iclass 18, count 0 2006.173.10:56:25.87#ibcon#read 4, iclass 18, count 0 2006.173.10:56:25.87#ibcon#about to read 5, iclass 18, count 0 2006.173.10:56:25.87#ibcon#read 5, iclass 18, count 0 2006.173.10:56:25.87#ibcon#about to read 6, iclass 18, count 0 2006.173.10:56:25.87#ibcon#read 6, iclass 18, count 0 2006.173.10:56:25.87#ibcon#end of sib2, iclass 18, count 0 2006.173.10:56:25.87#ibcon#*mode == 0, iclass 18, count 0 2006.173.10:56:25.87#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.10:56:25.87#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.10:56:25.87#ibcon#*before write, iclass 18, count 0 2006.173.10:56:25.87#ibcon#enter sib2, iclass 18, count 0 2006.173.10:56:25.87#ibcon#flushed, iclass 18, count 0 2006.173.10:56:25.87#ibcon#about to write, iclass 18, count 0 2006.173.10:56:25.87#ibcon#wrote, iclass 18, count 0 2006.173.10:56:25.87#ibcon#about to read 3, iclass 18, count 0 2006.173.10:56:25.91#ibcon#read 3, iclass 18, count 0 2006.173.10:56:25.91#ibcon#about to read 4, iclass 18, count 0 2006.173.10:56:25.91#ibcon#read 4, iclass 18, count 0 2006.173.10:56:25.91#ibcon#about to read 5, iclass 18, count 0 2006.173.10:56:25.91#ibcon#read 5, iclass 18, count 0 2006.173.10:56:25.91#ibcon#about to read 6, iclass 18, count 0 2006.173.10:56:25.91#ibcon#read 6, iclass 18, count 0 2006.173.10:56:25.91#ibcon#end of sib2, iclass 18, count 0 2006.173.10:56:25.91#ibcon#*after write, iclass 18, count 0 2006.173.10:56:25.91#ibcon#*before return 0, iclass 18, count 0 2006.173.10:56:25.91#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.10:56:25.91#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.10:56:25.91#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.10:56:25.91#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.10:56:25.91$vck44/va=6,3 2006.173.10:56:25.91#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.10:56:25.91#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.10:56:25.91#ibcon#ireg 11 cls_cnt 2 2006.173.10:56:25.91#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.10:56:25.97#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.10:56:25.97#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.10:56:25.97#ibcon#enter wrdev, iclass 20, count 2 2006.173.10:56:25.97#ibcon#first serial, iclass 20, count 2 2006.173.10:56:25.97#ibcon#enter sib2, iclass 20, count 2 2006.173.10:56:25.97#ibcon#flushed, iclass 20, count 2 2006.173.10:56:25.97#ibcon#about to write, iclass 20, count 2 2006.173.10:56:25.97#ibcon#wrote, iclass 20, count 2 2006.173.10:56:25.97#ibcon#about to read 3, iclass 20, count 2 2006.173.10:56:25.99#ibcon#read 3, iclass 20, count 2 2006.173.10:56:25.99#ibcon#about to read 4, iclass 20, count 2 2006.173.10:56:25.99#ibcon#read 4, iclass 20, count 2 2006.173.10:56:25.99#ibcon#about to read 5, iclass 20, count 2 2006.173.10:56:25.99#ibcon#read 5, iclass 20, count 2 2006.173.10:56:25.99#ibcon#about to read 6, iclass 20, count 2 2006.173.10:56:25.99#ibcon#read 6, iclass 20, count 2 2006.173.10:56:25.99#ibcon#end of sib2, iclass 20, count 2 2006.173.10:56:25.99#ibcon#*mode == 0, iclass 20, count 2 2006.173.10:56:25.99#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.10:56:25.99#ibcon#[25=AT06-03\r\n] 2006.173.10:56:25.99#ibcon#*before write, iclass 20, count 2 2006.173.10:56:25.99#ibcon#enter sib2, iclass 20, count 2 2006.173.10:56:25.99#ibcon#flushed, iclass 20, count 2 2006.173.10:56:25.99#ibcon#about to write, iclass 20, count 2 2006.173.10:56:25.99#ibcon#wrote, iclass 20, count 2 2006.173.10:56:25.99#ibcon#about to read 3, iclass 20, count 2 2006.173.10:56:26.02#ibcon#read 3, iclass 20, count 2 2006.173.10:56:26.02#ibcon#about to read 4, iclass 20, count 2 2006.173.10:56:26.02#ibcon#read 4, iclass 20, count 2 2006.173.10:56:26.02#ibcon#about to read 5, iclass 20, count 2 2006.173.10:56:26.02#ibcon#read 5, iclass 20, count 2 2006.173.10:56:26.02#ibcon#about to read 6, iclass 20, count 2 2006.173.10:56:26.02#ibcon#read 6, iclass 20, count 2 2006.173.10:56:26.02#ibcon#end of sib2, iclass 20, count 2 2006.173.10:56:26.02#ibcon#*after write, iclass 20, count 2 2006.173.10:56:26.02#ibcon#*before return 0, iclass 20, count 2 2006.173.10:56:26.02#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.10:56:26.02#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.10:56:26.02#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.10:56:26.02#ibcon#ireg 7 cls_cnt 0 2006.173.10:56:26.02#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.10:56:26.14#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.10:56:26.14#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.10:56:26.14#ibcon#enter wrdev, iclass 20, count 0 2006.173.10:56:26.14#ibcon#first serial, iclass 20, count 0 2006.173.10:56:26.14#ibcon#enter sib2, iclass 20, count 0 2006.173.10:56:26.14#ibcon#flushed, iclass 20, count 0 2006.173.10:56:26.14#ibcon#about to write, iclass 20, count 0 2006.173.10:56:26.14#ibcon#wrote, iclass 20, count 0 2006.173.10:56:26.14#ibcon#about to read 3, iclass 20, count 0 2006.173.10:56:26.16#ibcon#read 3, iclass 20, count 0 2006.173.10:56:26.16#ibcon#about to read 4, iclass 20, count 0 2006.173.10:56:26.16#ibcon#read 4, iclass 20, count 0 2006.173.10:56:26.16#ibcon#about to read 5, iclass 20, count 0 2006.173.10:56:26.16#ibcon#read 5, iclass 20, count 0 2006.173.10:56:26.16#ibcon#about to read 6, iclass 20, count 0 2006.173.10:56:26.16#ibcon#read 6, iclass 20, count 0 2006.173.10:56:26.16#ibcon#end of sib2, iclass 20, count 0 2006.173.10:56:26.16#ibcon#*mode == 0, iclass 20, count 0 2006.173.10:56:26.16#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.10:56:26.16#ibcon#[25=USB\r\n] 2006.173.10:56:26.16#ibcon#*before write, iclass 20, count 0 2006.173.10:56:26.16#ibcon#enter sib2, iclass 20, count 0 2006.173.10:56:26.16#ibcon#flushed, iclass 20, count 0 2006.173.10:56:26.16#ibcon#about to write, iclass 20, count 0 2006.173.10:56:26.16#ibcon#wrote, iclass 20, count 0 2006.173.10:56:26.16#ibcon#about to read 3, iclass 20, count 0 2006.173.10:56:26.19#ibcon#read 3, iclass 20, count 0 2006.173.10:56:26.19#ibcon#about to read 4, iclass 20, count 0 2006.173.10:56:26.19#ibcon#read 4, iclass 20, count 0 2006.173.10:56:26.19#ibcon#about to read 5, iclass 20, count 0 2006.173.10:56:26.19#ibcon#read 5, iclass 20, count 0 2006.173.10:56:26.19#ibcon#about to read 6, iclass 20, count 0 2006.173.10:56:26.19#ibcon#read 6, iclass 20, count 0 2006.173.10:56:26.19#ibcon#end of sib2, iclass 20, count 0 2006.173.10:56:26.19#ibcon#*after write, iclass 20, count 0 2006.173.10:56:26.19#ibcon#*before return 0, iclass 20, count 0 2006.173.10:56:26.19#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.10:56:26.19#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.10:56:26.19#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.10:56:26.19#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.10:56:26.19$vck44/valo=7,864.99 2006.173.10:56:26.19#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.10:56:26.19#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.10:56:26.19#ibcon#ireg 17 cls_cnt 0 2006.173.10:56:26.19#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.10:56:26.19#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.10:56:26.19#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.10:56:26.19#ibcon#enter wrdev, iclass 22, count 0 2006.173.10:56:26.19#ibcon#first serial, iclass 22, count 0 2006.173.10:56:26.19#ibcon#enter sib2, iclass 22, count 0 2006.173.10:56:26.19#ibcon#flushed, iclass 22, count 0 2006.173.10:56:26.19#ibcon#about to write, iclass 22, count 0 2006.173.10:56:26.19#ibcon#wrote, iclass 22, count 0 2006.173.10:56:26.19#ibcon#about to read 3, iclass 22, count 0 2006.173.10:56:26.21#ibcon#read 3, iclass 22, count 0 2006.173.10:56:26.21#ibcon#about to read 4, iclass 22, count 0 2006.173.10:56:26.21#ibcon#read 4, iclass 22, count 0 2006.173.10:56:26.21#ibcon#about to read 5, iclass 22, count 0 2006.173.10:56:26.21#ibcon#read 5, iclass 22, count 0 2006.173.10:56:26.21#ibcon#about to read 6, iclass 22, count 0 2006.173.10:56:26.21#ibcon#read 6, iclass 22, count 0 2006.173.10:56:26.21#ibcon#end of sib2, iclass 22, count 0 2006.173.10:56:26.21#ibcon#*mode == 0, iclass 22, count 0 2006.173.10:56:26.21#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.10:56:26.21#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.10:56:26.21#ibcon#*before write, iclass 22, count 0 2006.173.10:56:26.21#ibcon#enter sib2, iclass 22, count 0 2006.173.10:56:26.21#ibcon#flushed, iclass 22, count 0 2006.173.10:56:26.21#ibcon#about to write, iclass 22, count 0 2006.173.10:56:26.21#ibcon#wrote, iclass 22, count 0 2006.173.10:56:26.21#ibcon#about to read 3, iclass 22, count 0 2006.173.10:56:26.25#ibcon#read 3, iclass 22, count 0 2006.173.10:56:26.25#ibcon#about to read 4, iclass 22, count 0 2006.173.10:56:26.25#ibcon#read 4, iclass 22, count 0 2006.173.10:56:26.25#ibcon#about to read 5, iclass 22, count 0 2006.173.10:56:26.25#ibcon#read 5, iclass 22, count 0 2006.173.10:56:26.25#ibcon#about to read 6, iclass 22, count 0 2006.173.10:56:26.25#ibcon#read 6, iclass 22, count 0 2006.173.10:56:26.25#ibcon#end of sib2, iclass 22, count 0 2006.173.10:56:26.25#ibcon#*after write, iclass 22, count 0 2006.173.10:56:26.25#ibcon#*before return 0, iclass 22, count 0 2006.173.10:56:26.25#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.10:56:26.25#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.10:56:26.25#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.10:56:26.25#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.10:56:26.25$vck44/va=7,4 2006.173.10:56:26.25#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.10:56:26.25#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.10:56:26.25#ibcon#ireg 11 cls_cnt 2 2006.173.10:56:26.25#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.10:56:26.31#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.10:56:26.31#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.10:56:26.31#ibcon#enter wrdev, iclass 24, count 2 2006.173.10:56:26.31#ibcon#first serial, iclass 24, count 2 2006.173.10:56:26.31#ibcon#enter sib2, iclass 24, count 2 2006.173.10:56:26.31#ibcon#flushed, iclass 24, count 2 2006.173.10:56:26.31#ibcon#about to write, iclass 24, count 2 2006.173.10:56:26.31#ibcon#wrote, iclass 24, count 2 2006.173.10:56:26.31#ibcon#about to read 3, iclass 24, count 2 2006.173.10:56:26.33#ibcon#read 3, iclass 24, count 2 2006.173.10:56:26.33#ibcon#about to read 4, iclass 24, count 2 2006.173.10:56:26.33#ibcon#read 4, iclass 24, count 2 2006.173.10:56:26.33#ibcon#about to read 5, iclass 24, count 2 2006.173.10:56:26.33#ibcon#read 5, iclass 24, count 2 2006.173.10:56:26.33#ibcon#about to read 6, iclass 24, count 2 2006.173.10:56:26.33#ibcon#read 6, iclass 24, count 2 2006.173.10:56:26.33#ibcon#end of sib2, iclass 24, count 2 2006.173.10:56:26.33#ibcon#*mode == 0, iclass 24, count 2 2006.173.10:56:26.33#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.10:56:26.33#ibcon#[25=AT07-04\r\n] 2006.173.10:56:26.33#ibcon#*before write, iclass 24, count 2 2006.173.10:56:26.33#ibcon#enter sib2, iclass 24, count 2 2006.173.10:56:26.33#ibcon#flushed, iclass 24, count 2 2006.173.10:56:26.33#ibcon#about to write, iclass 24, count 2 2006.173.10:56:26.33#ibcon#wrote, iclass 24, count 2 2006.173.10:56:26.33#ibcon#about to read 3, iclass 24, count 2 2006.173.10:56:26.36#ibcon#read 3, iclass 24, count 2 2006.173.10:56:26.36#ibcon#about to read 4, iclass 24, count 2 2006.173.10:56:26.36#ibcon#read 4, iclass 24, count 2 2006.173.10:56:26.36#ibcon#about to read 5, iclass 24, count 2 2006.173.10:56:26.36#ibcon#read 5, iclass 24, count 2 2006.173.10:56:26.36#ibcon#about to read 6, iclass 24, count 2 2006.173.10:56:26.36#ibcon#read 6, iclass 24, count 2 2006.173.10:56:26.36#ibcon#end of sib2, iclass 24, count 2 2006.173.10:56:26.36#ibcon#*after write, iclass 24, count 2 2006.173.10:56:26.36#ibcon#*before return 0, iclass 24, count 2 2006.173.10:56:26.36#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.10:56:26.36#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.10:56:26.36#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.10:56:26.36#ibcon#ireg 7 cls_cnt 0 2006.173.10:56:26.36#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.10:56:26.48#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.10:56:26.48#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.10:56:26.48#ibcon#enter wrdev, iclass 24, count 0 2006.173.10:56:26.48#ibcon#first serial, iclass 24, count 0 2006.173.10:56:26.48#ibcon#enter sib2, iclass 24, count 0 2006.173.10:56:26.48#ibcon#flushed, iclass 24, count 0 2006.173.10:56:26.48#ibcon#about to write, iclass 24, count 0 2006.173.10:56:26.48#ibcon#wrote, iclass 24, count 0 2006.173.10:56:26.48#ibcon#about to read 3, iclass 24, count 0 2006.173.10:56:26.50#ibcon#read 3, iclass 24, count 0 2006.173.10:56:26.50#ibcon#about to read 4, iclass 24, count 0 2006.173.10:56:26.50#ibcon#read 4, iclass 24, count 0 2006.173.10:56:26.50#ibcon#about to read 5, iclass 24, count 0 2006.173.10:56:26.50#ibcon#read 5, iclass 24, count 0 2006.173.10:56:26.50#ibcon#about to read 6, iclass 24, count 0 2006.173.10:56:26.50#ibcon#read 6, iclass 24, count 0 2006.173.10:56:26.50#ibcon#end of sib2, iclass 24, count 0 2006.173.10:56:26.50#ibcon#*mode == 0, iclass 24, count 0 2006.173.10:56:26.50#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.10:56:26.50#ibcon#[25=USB\r\n] 2006.173.10:56:26.50#ibcon#*before write, iclass 24, count 0 2006.173.10:56:26.50#ibcon#enter sib2, iclass 24, count 0 2006.173.10:56:26.50#ibcon#flushed, iclass 24, count 0 2006.173.10:56:26.50#ibcon#about to write, iclass 24, count 0 2006.173.10:56:26.50#ibcon#wrote, iclass 24, count 0 2006.173.10:56:26.50#ibcon#about to read 3, iclass 24, count 0 2006.173.10:56:26.53#ibcon#read 3, iclass 24, count 0 2006.173.10:56:26.53#ibcon#about to read 4, iclass 24, count 0 2006.173.10:56:26.53#ibcon#read 4, iclass 24, count 0 2006.173.10:56:26.53#ibcon#about to read 5, iclass 24, count 0 2006.173.10:56:26.53#ibcon#read 5, iclass 24, count 0 2006.173.10:56:26.53#ibcon#about to read 6, iclass 24, count 0 2006.173.10:56:26.53#ibcon#read 6, iclass 24, count 0 2006.173.10:56:26.53#ibcon#end of sib2, iclass 24, count 0 2006.173.10:56:26.53#ibcon#*after write, iclass 24, count 0 2006.173.10:56:26.53#ibcon#*before return 0, iclass 24, count 0 2006.173.10:56:26.53#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.10:56:26.53#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.10:56:26.53#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.10:56:26.53#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.10:56:26.53$vck44/valo=8,884.99 2006.173.10:56:26.53#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.10:56:26.53#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.10:56:26.53#ibcon#ireg 17 cls_cnt 0 2006.173.10:56:26.53#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.10:56:26.53#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.10:56:26.53#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.10:56:26.53#ibcon#enter wrdev, iclass 26, count 0 2006.173.10:56:26.53#ibcon#first serial, iclass 26, count 0 2006.173.10:56:26.53#ibcon#enter sib2, iclass 26, count 0 2006.173.10:56:26.53#ibcon#flushed, iclass 26, count 0 2006.173.10:56:26.53#ibcon#about to write, iclass 26, count 0 2006.173.10:56:26.53#ibcon#wrote, iclass 26, count 0 2006.173.10:56:26.53#ibcon#about to read 3, iclass 26, count 0 2006.173.10:56:26.55#ibcon#read 3, iclass 26, count 0 2006.173.10:56:26.55#ibcon#about to read 4, iclass 26, count 0 2006.173.10:56:26.55#ibcon#read 4, iclass 26, count 0 2006.173.10:56:26.55#ibcon#about to read 5, iclass 26, count 0 2006.173.10:56:26.55#ibcon#read 5, iclass 26, count 0 2006.173.10:56:26.55#ibcon#about to read 6, iclass 26, count 0 2006.173.10:56:26.55#ibcon#read 6, iclass 26, count 0 2006.173.10:56:26.55#ibcon#end of sib2, iclass 26, count 0 2006.173.10:56:26.55#ibcon#*mode == 0, iclass 26, count 0 2006.173.10:56:26.55#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.10:56:26.55#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.10:56:26.55#ibcon#*before write, iclass 26, count 0 2006.173.10:56:26.55#ibcon#enter sib2, iclass 26, count 0 2006.173.10:56:26.55#ibcon#flushed, iclass 26, count 0 2006.173.10:56:26.55#ibcon#about to write, iclass 26, count 0 2006.173.10:56:26.55#ibcon#wrote, iclass 26, count 0 2006.173.10:56:26.55#ibcon#about to read 3, iclass 26, count 0 2006.173.10:56:26.59#ibcon#read 3, iclass 26, count 0 2006.173.10:56:26.59#ibcon#about to read 4, iclass 26, count 0 2006.173.10:56:26.59#ibcon#read 4, iclass 26, count 0 2006.173.10:56:26.59#ibcon#about to read 5, iclass 26, count 0 2006.173.10:56:26.59#ibcon#read 5, iclass 26, count 0 2006.173.10:56:26.59#ibcon#about to read 6, iclass 26, count 0 2006.173.10:56:26.59#ibcon#read 6, iclass 26, count 0 2006.173.10:56:26.59#ibcon#end of sib2, iclass 26, count 0 2006.173.10:56:26.59#ibcon#*after write, iclass 26, count 0 2006.173.10:56:26.59#ibcon#*before return 0, iclass 26, count 0 2006.173.10:56:26.59#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.10:56:26.59#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.10:56:26.59#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.10:56:26.59#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.10:56:26.59$vck44/va=8,4 2006.173.10:56:26.59#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.10:56:26.59#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.10:56:26.59#ibcon#ireg 11 cls_cnt 2 2006.173.10:56:26.59#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.10:56:26.65#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.10:56:26.65#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.10:56:26.65#ibcon#enter wrdev, iclass 28, count 2 2006.173.10:56:26.65#ibcon#first serial, iclass 28, count 2 2006.173.10:56:26.65#ibcon#enter sib2, iclass 28, count 2 2006.173.10:56:26.65#ibcon#flushed, iclass 28, count 2 2006.173.10:56:26.65#ibcon#about to write, iclass 28, count 2 2006.173.10:56:26.65#ibcon#wrote, iclass 28, count 2 2006.173.10:56:26.65#ibcon#about to read 3, iclass 28, count 2 2006.173.10:56:26.67#ibcon#read 3, iclass 28, count 2 2006.173.10:56:26.67#ibcon#about to read 4, iclass 28, count 2 2006.173.10:56:26.67#ibcon#read 4, iclass 28, count 2 2006.173.10:56:26.67#ibcon#about to read 5, iclass 28, count 2 2006.173.10:56:26.67#ibcon#read 5, iclass 28, count 2 2006.173.10:56:26.67#ibcon#about to read 6, iclass 28, count 2 2006.173.10:56:26.67#ibcon#read 6, iclass 28, count 2 2006.173.10:56:26.67#ibcon#end of sib2, iclass 28, count 2 2006.173.10:56:26.67#ibcon#*mode == 0, iclass 28, count 2 2006.173.10:56:26.67#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.10:56:26.67#ibcon#[25=AT08-04\r\n] 2006.173.10:56:26.67#ibcon#*before write, iclass 28, count 2 2006.173.10:56:26.67#ibcon#enter sib2, iclass 28, count 2 2006.173.10:56:26.67#ibcon#flushed, iclass 28, count 2 2006.173.10:56:26.67#ibcon#about to write, iclass 28, count 2 2006.173.10:56:26.67#ibcon#wrote, iclass 28, count 2 2006.173.10:56:26.67#ibcon#about to read 3, iclass 28, count 2 2006.173.10:56:26.70#ibcon#read 3, iclass 28, count 2 2006.173.10:56:26.70#ibcon#about to read 4, iclass 28, count 2 2006.173.10:56:26.70#ibcon#read 4, iclass 28, count 2 2006.173.10:56:26.70#ibcon#about to read 5, iclass 28, count 2 2006.173.10:56:26.70#ibcon#read 5, iclass 28, count 2 2006.173.10:56:26.70#ibcon#about to read 6, iclass 28, count 2 2006.173.10:56:26.70#ibcon#read 6, iclass 28, count 2 2006.173.10:56:26.70#ibcon#end of sib2, iclass 28, count 2 2006.173.10:56:26.70#ibcon#*after write, iclass 28, count 2 2006.173.10:56:26.70#ibcon#*before return 0, iclass 28, count 2 2006.173.10:56:26.70#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.10:56:26.70#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.10:56:26.70#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.10:56:26.70#ibcon#ireg 7 cls_cnt 0 2006.173.10:56:26.70#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.10:56:26.82#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.10:56:26.82#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.10:56:26.82#ibcon#enter wrdev, iclass 28, count 0 2006.173.10:56:26.82#ibcon#first serial, iclass 28, count 0 2006.173.10:56:26.82#ibcon#enter sib2, iclass 28, count 0 2006.173.10:56:26.82#ibcon#flushed, iclass 28, count 0 2006.173.10:56:26.82#ibcon#about to write, iclass 28, count 0 2006.173.10:56:26.82#ibcon#wrote, iclass 28, count 0 2006.173.10:56:26.82#ibcon#about to read 3, iclass 28, count 0 2006.173.10:56:26.84#ibcon#read 3, iclass 28, count 0 2006.173.10:56:26.84#ibcon#about to read 4, iclass 28, count 0 2006.173.10:56:26.84#ibcon#read 4, iclass 28, count 0 2006.173.10:56:26.84#ibcon#about to read 5, iclass 28, count 0 2006.173.10:56:26.84#ibcon#read 5, iclass 28, count 0 2006.173.10:56:26.84#ibcon#about to read 6, iclass 28, count 0 2006.173.10:56:26.84#ibcon#read 6, iclass 28, count 0 2006.173.10:56:26.84#ibcon#end of sib2, iclass 28, count 0 2006.173.10:56:26.84#ibcon#*mode == 0, iclass 28, count 0 2006.173.10:56:26.84#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.10:56:26.84#ibcon#[25=USB\r\n] 2006.173.10:56:26.84#ibcon#*before write, iclass 28, count 0 2006.173.10:56:26.84#ibcon#enter sib2, iclass 28, count 0 2006.173.10:56:26.84#ibcon#flushed, iclass 28, count 0 2006.173.10:56:26.84#ibcon#about to write, iclass 28, count 0 2006.173.10:56:26.84#ibcon#wrote, iclass 28, count 0 2006.173.10:56:26.84#ibcon#about to read 3, iclass 28, count 0 2006.173.10:56:26.87#ibcon#read 3, iclass 28, count 0 2006.173.10:56:26.87#ibcon#about to read 4, iclass 28, count 0 2006.173.10:56:26.87#ibcon#read 4, iclass 28, count 0 2006.173.10:56:26.87#ibcon#about to read 5, iclass 28, count 0 2006.173.10:56:26.87#ibcon#read 5, iclass 28, count 0 2006.173.10:56:26.87#ibcon#about to read 6, iclass 28, count 0 2006.173.10:56:26.87#ibcon#read 6, iclass 28, count 0 2006.173.10:56:26.87#ibcon#end of sib2, iclass 28, count 0 2006.173.10:56:26.87#ibcon#*after write, iclass 28, count 0 2006.173.10:56:26.87#ibcon#*before return 0, iclass 28, count 0 2006.173.10:56:26.87#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.10:56:26.87#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.10:56:26.87#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.10:56:26.87#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.10:56:26.87$vck44/vblo=1,629.99 2006.173.10:56:26.87#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.10:56:26.87#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.10:56:26.87#ibcon#ireg 17 cls_cnt 0 2006.173.10:56:26.87#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.10:56:26.87#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.10:56:26.87#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.10:56:26.87#ibcon#enter wrdev, iclass 30, count 0 2006.173.10:56:26.87#ibcon#first serial, iclass 30, count 0 2006.173.10:56:26.87#ibcon#enter sib2, iclass 30, count 0 2006.173.10:56:26.87#ibcon#flushed, iclass 30, count 0 2006.173.10:56:26.87#ibcon#about to write, iclass 30, count 0 2006.173.10:56:26.87#ibcon#wrote, iclass 30, count 0 2006.173.10:56:26.87#ibcon#about to read 3, iclass 30, count 0 2006.173.10:56:26.89#ibcon#read 3, iclass 30, count 0 2006.173.10:56:26.89#ibcon#about to read 4, iclass 30, count 0 2006.173.10:56:26.89#ibcon#read 4, iclass 30, count 0 2006.173.10:56:26.89#ibcon#about to read 5, iclass 30, count 0 2006.173.10:56:26.89#ibcon#read 5, iclass 30, count 0 2006.173.10:56:26.89#ibcon#about to read 6, iclass 30, count 0 2006.173.10:56:26.89#ibcon#read 6, iclass 30, count 0 2006.173.10:56:26.89#ibcon#end of sib2, iclass 30, count 0 2006.173.10:56:26.89#ibcon#*mode == 0, iclass 30, count 0 2006.173.10:56:26.89#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.10:56:26.89#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.10:56:26.89#ibcon#*before write, iclass 30, count 0 2006.173.10:56:26.89#ibcon#enter sib2, iclass 30, count 0 2006.173.10:56:26.89#ibcon#flushed, iclass 30, count 0 2006.173.10:56:26.89#ibcon#about to write, iclass 30, count 0 2006.173.10:56:26.89#ibcon#wrote, iclass 30, count 0 2006.173.10:56:26.89#ibcon#about to read 3, iclass 30, count 0 2006.173.10:56:26.93#ibcon#read 3, iclass 30, count 0 2006.173.10:56:26.93#ibcon#about to read 4, iclass 30, count 0 2006.173.10:56:26.93#ibcon#read 4, iclass 30, count 0 2006.173.10:56:26.93#ibcon#about to read 5, iclass 30, count 0 2006.173.10:56:26.93#ibcon#read 5, iclass 30, count 0 2006.173.10:56:26.93#ibcon#about to read 6, iclass 30, count 0 2006.173.10:56:26.93#ibcon#read 6, iclass 30, count 0 2006.173.10:56:26.93#ibcon#end of sib2, iclass 30, count 0 2006.173.10:56:26.93#ibcon#*after write, iclass 30, count 0 2006.173.10:56:26.93#ibcon#*before return 0, iclass 30, count 0 2006.173.10:56:26.93#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.10:56:26.93#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.10:56:26.93#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.10:56:26.93#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.10:56:26.93$vck44/vb=1,4 2006.173.10:56:26.93#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.173.10:56:26.93#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.173.10:56:26.93#ibcon#ireg 11 cls_cnt 2 2006.173.10:56:26.93#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.10:56:26.93#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.10:56:26.93#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.10:56:26.93#ibcon#enter wrdev, iclass 32, count 2 2006.173.10:56:26.93#ibcon#first serial, iclass 32, count 2 2006.173.10:56:26.93#ibcon#enter sib2, iclass 32, count 2 2006.173.10:56:26.93#ibcon#flushed, iclass 32, count 2 2006.173.10:56:26.93#ibcon#about to write, iclass 32, count 2 2006.173.10:56:26.93#ibcon#wrote, iclass 32, count 2 2006.173.10:56:26.93#ibcon#about to read 3, iclass 32, count 2 2006.173.10:56:26.95#ibcon#read 3, iclass 32, count 2 2006.173.10:56:26.95#ibcon#about to read 4, iclass 32, count 2 2006.173.10:56:26.95#ibcon#read 4, iclass 32, count 2 2006.173.10:56:26.95#ibcon#about to read 5, iclass 32, count 2 2006.173.10:56:26.95#ibcon#read 5, iclass 32, count 2 2006.173.10:56:26.95#ibcon#about to read 6, iclass 32, count 2 2006.173.10:56:26.95#ibcon#read 6, iclass 32, count 2 2006.173.10:56:26.95#ibcon#end of sib2, iclass 32, count 2 2006.173.10:56:26.95#ibcon#*mode == 0, iclass 32, count 2 2006.173.10:56:26.95#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.173.10:56:26.95#ibcon#[27=AT01-04\r\n] 2006.173.10:56:26.95#ibcon#*before write, iclass 32, count 2 2006.173.10:56:26.95#ibcon#enter sib2, iclass 32, count 2 2006.173.10:56:26.95#ibcon#flushed, iclass 32, count 2 2006.173.10:56:26.95#ibcon#about to write, iclass 32, count 2 2006.173.10:56:26.95#ibcon#wrote, iclass 32, count 2 2006.173.10:56:26.95#ibcon#about to read 3, iclass 32, count 2 2006.173.10:56:26.98#ibcon#read 3, iclass 32, count 2 2006.173.10:56:26.98#ibcon#about to read 4, iclass 32, count 2 2006.173.10:56:26.98#ibcon#read 4, iclass 32, count 2 2006.173.10:56:26.98#ibcon#about to read 5, iclass 32, count 2 2006.173.10:56:26.98#ibcon#read 5, iclass 32, count 2 2006.173.10:56:26.98#ibcon#about to read 6, iclass 32, count 2 2006.173.10:56:26.98#ibcon#read 6, iclass 32, count 2 2006.173.10:56:26.98#ibcon#end of sib2, iclass 32, count 2 2006.173.10:56:26.98#ibcon#*after write, iclass 32, count 2 2006.173.10:56:26.98#ibcon#*before return 0, iclass 32, count 2 2006.173.10:56:26.98#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.10:56:26.98#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.173.10:56:26.98#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.173.10:56:26.98#ibcon#ireg 7 cls_cnt 0 2006.173.10:56:26.98#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.10:56:27.10#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.10:56:27.10#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.10:56:27.10#ibcon#enter wrdev, iclass 32, count 0 2006.173.10:56:27.10#ibcon#first serial, iclass 32, count 0 2006.173.10:56:27.10#ibcon#enter sib2, iclass 32, count 0 2006.173.10:56:27.10#ibcon#flushed, iclass 32, count 0 2006.173.10:56:27.10#ibcon#about to write, iclass 32, count 0 2006.173.10:56:27.10#ibcon#wrote, iclass 32, count 0 2006.173.10:56:27.10#ibcon#about to read 3, iclass 32, count 0 2006.173.10:56:27.12#ibcon#read 3, iclass 32, count 0 2006.173.10:56:27.12#ibcon#about to read 4, iclass 32, count 0 2006.173.10:56:27.12#ibcon#read 4, iclass 32, count 0 2006.173.10:56:27.12#ibcon#about to read 5, iclass 32, count 0 2006.173.10:56:27.12#ibcon#read 5, iclass 32, count 0 2006.173.10:56:27.12#ibcon#about to read 6, iclass 32, count 0 2006.173.10:56:27.12#ibcon#read 6, iclass 32, count 0 2006.173.10:56:27.12#ibcon#end of sib2, iclass 32, count 0 2006.173.10:56:27.12#ibcon#*mode == 0, iclass 32, count 0 2006.173.10:56:27.12#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.10:56:27.12#ibcon#[27=USB\r\n] 2006.173.10:56:27.12#ibcon#*before write, iclass 32, count 0 2006.173.10:56:27.12#ibcon#enter sib2, iclass 32, count 0 2006.173.10:56:27.12#ibcon#flushed, iclass 32, count 0 2006.173.10:56:27.12#ibcon#about to write, iclass 32, count 0 2006.173.10:56:27.12#ibcon#wrote, iclass 32, count 0 2006.173.10:56:27.12#ibcon#about to read 3, iclass 32, count 0 2006.173.10:56:27.15#ibcon#read 3, iclass 32, count 0 2006.173.10:56:27.15#ibcon#about to read 4, iclass 32, count 0 2006.173.10:56:27.15#ibcon#read 4, iclass 32, count 0 2006.173.10:56:27.15#ibcon#about to read 5, iclass 32, count 0 2006.173.10:56:27.15#ibcon#read 5, iclass 32, count 0 2006.173.10:56:27.15#ibcon#about to read 6, iclass 32, count 0 2006.173.10:56:27.15#ibcon#read 6, iclass 32, count 0 2006.173.10:56:27.15#ibcon#end of sib2, iclass 32, count 0 2006.173.10:56:27.15#ibcon#*after write, iclass 32, count 0 2006.173.10:56:27.15#ibcon#*before return 0, iclass 32, count 0 2006.173.10:56:27.15#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.10:56:27.15#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.173.10:56:27.15#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.10:56:27.15#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.10:56:27.15$vck44/vblo=2,634.99 2006.173.10:56:27.15#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.10:56:27.15#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.10:56:27.15#ibcon#ireg 17 cls_cnt 0 2006.173.10:56:27.15#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.10:56:27.15#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.10:56:27.15#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.10:56:27.15#ibcon#enter wrdev, iclass 34, count 0 2006.173.10:56:27.15#ibcon#first serial, iclass 34, count 0 2006.173.10:56:27.15#ibcon#enter sib2, iclass 34, count 0 2006.173.10:56:27.15#ibcon#flushed, iclass 34, count 0 2006.173.10:56:27.15#ibcon#about to write, iclass 34, count 0 2006.173.10:56:27.15#ibcon#wrote, iclass 34, count 0 2006.173.10:56:27.15#ibcon#about to read 3, iclass 34, count 0 2006.173.10:56:27.17#ibcon#read 3, iclass 34, count 0 2006.173.10:56:27.17#ibcon#about to read 4, iclass 34, count 0 2006.173.10:56:27.17#ibcon#read 4, iclass 34, count 0 2006.173.10:56:27.17#ibcon#about to read 5, iclass 34, count 0 2006.173.10:56:27.17#ibcon#read 5, iclass 34, count 0 2006.173.10:56:27.17#ibcon#about to read 6, iclass 34, count 0 2006.173.10:56:27.17#ibcon#read 6, iclass 34, count 0 2006.173.10:56:27.17#ibcon#end of sib2, iclass 34, count 0 2006.173.10:56:27.17#ibcon#*mode == 0, iclass 34, count 0 2006.173.10:56:27.17#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.10:56:27.17#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.10:56:27.17#ibcon#*before write, iclass 34, count 0 2006.173.10:56:27.17#ibcon#enter sib2, iclass 34, count 0 2006.173.10:56:27.17#ibcon#flushed, iclass 34, count 0 2006.173.10:56:27.17#ibcon#about to write, iclass 34, count 0 2006.173.10:56:27.17#ibcon#wrote, iclass 34, count 0 2006.173.10:56:27.17#ibcon#about to read 3, iclass 34, count 0 2006.173.10:56:27.21#ibcon#read 3, iclass 34, count 0 2006.173.10:56:27.21#ibcon#about to read 4, iclass 34, count 0 2006.173.10:56:27.21#ibcon#read 4, iclass 34, count 0 2006.173.10:56:27.21#ibcon#about to read 5, iclass 34, count 0 2006.173.10:56:27.21#ibcon#read 5, iclass 34, count 0 2006.173.10:56:27.21#ibcon#about to read 6, iclass 34, count 0 2006.173.10:56:27.21#ibcon#read 6, iclass 34, count 0 2006.173.10:56:27.21#ibcon#end of sib2, iclass 34, count 0 2006.173.10:56:27.21#ibcon#*after write, iclass 34, count 0 2006.173.10:56:27.21#ibcon#*before return 0, iclass 34, count 0 2006.173.10:56:27.21#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.10:56:27.21#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.10:56:27.21#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.10:56:27.21#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.10:56:27.21$vck44/vb=2,4 2006.173.10:56:27.21#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.10:56:27.21#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.10:56:27.21#ibcon#ireg 11 cls_cnt 2 2006.173.10:56:27.21#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.10:56:27.27#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.10:56:27.27#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.10:56:27.27#ibcon#enter wrdev, iclass 36, count 2 2006.173.10:56:27.27#ibcon#first serial, iclass 36, count 2 2006.173.10:56:27.27#ibcon#enter sib2, iclass 36, count 2 2006.173.10:56:27.27#ibcon#flushed, iclass 36, count 2 2006.173.10:56:27.27#ibcon#about to write, iclass 36, count 2 2006.173.10:56:27.27#ibcon#wrote, iclass 36, count 2 2006.173.10:56:27.27#ibcon#about to read 3, iclass 36, count 2 2006.173.10:56:27.29#ibcon#read 3, iclass 36, count 2 2006.173.10:56:27.29#ibcon#about to read 4, iclass 36, count 2 2006.173.10:56:27.29#ibcon#read 4, iclass 36, count 2 2006.173.10:56:27.29#ibcon#about to read 5, iclass 36, count 2 2006.173.10:56:27.29#ibcon#read 5, iclass 36, count 2 2006.173.10:56:27.29#ibcon#about to read 6, iclass 36, count 2 2006.173.10:56:27.29#ibcon#read 6, iclass 36, count 2 2006.173.10:56:27.29#ibcon#end of sib2, iclass 36, count 2 2006.173.10:56:27.29#ibcon#*mode == 0, iclass 36, count 2 2006.173.10:56:27.29#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.10:56:27.29#ibcon#[27=AT02-04\r\n] 2006.173.10:56:27.29#ibcon#*before write, iclass 36, count 2 2006.173.10:56:27.29#ibcon#enter sib2, iclass 36, count 2 2006.173.10:56:27.29#ibcon#flushed, iclass 36, count 2 2006.173.10:56:27.29#ibcon#about to write, iclass 36, count 2 2006.173.10:56:27.29#ibcon#wrote, iclass 36, count 2 2006.173.10:56:27.29#ibcon#about to read 3, iclass 36, count 2 2006.173.10:56:27.32#ibcon#read 3, iclass 36, count 2 2006.173.10:56:27.32#ibcon#about to read 4, iclass 36, count 2 2006.173.10:56:27.32#ibcon#read 4, iclass 36, count 2 2006.173.10:56:27.32#ibcon#about to read 5, iclass 36, count 2 2006.173.10:56:27.32#ibcon#read 5, iclass 36, count 2 2006.173.10:56:27.32#ibcon#about to read 6, iclass 36, count 2 2006.173.10:56:27.32#ibcon#read 6, iclass 36, count 2 2006.173.10:56:27.32#ibcon#end of sib2, iclass 36, count 2 2006.173.10:56:27.32#ibcon#*after write, iclass 36, count 2 2006.173.10:56:27.32#ibcon#*before return 0, iclass 36, count 2 2006.173.10:56:27.32#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.10:56:27.32#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.10:56:27.32#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.10:56:27.32#ibcon#ireg 7 cls_cnt 0 2006.173.10:56:27.32#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.10:56:27.44#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.10:56:27.44#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.10:56:27.44#ibcon#enter wrdev, iclass 36, count 0 2006.173.10:56:27.44#ibcon#first serial, iclass 36, count 0 2006.173.10:56:27.44#ibcon#enter sib2, iclass 36, count 0 2006.173.10:56:27.44#ibcon#flushed, iclass 36, count 0 2006.173.10:56:27.44#ibcon#about to write, iclass 36, count 0 2006.173.10:56:27.44#ibcon#wrote, iclass 36, count 0 2006.173.10:56:27.44#ibcon#about to read 3, iclass 36, count 0 2006.173.10:56:27.46#ibcon#read 3, iclass 36, count 0 2006.173.10:56:27.46#ibcon#about to read 4, iclass 36, count 0 2006.173.10:56:27.46#ibcon#read 4, iclass 36, count 0 2006.173.10:56:27.46#ibcon#about to read 5, iclass 36, count 0 2006.173.10:56:27.46#ibcon#read 5, iclass 36, count 0 2006.173.10:56:27.46#ibcon#about to read 6, iclass 36, count 0 2006.173.10:56:27.46#ibcon#read 6, iclass 36, count 0 2006.173.10:56:27.46#ibcon#end of sib2, iclass 36, count 0 2006.173.10:56:27.46#ibcon#*mode == 0, iclass 36, count 0 2006.173.10:56:27.46#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.10:56:27.46#ibcon#[27=USB\r\n] 2006.173.10:56:27.46#ibcon#*before write, iclass 36, count 0 2006.173.10:56:27.46#ibcon#enter sib2, iclass 36, count 0 2006.173.10:56:27.46#ibcon#flushed, iclass 36, count 0 2006.173.10:56:27.46#ibcon#about to write, iclass 36, count 0 2006.173.10:56:27.46#ibcon#wrote, iclass 36, count 0 2006.173.10:56:27.46#ibcon#about to read 3, iclass 36, count 0 2006.173.10:56:27.49#ibcon#read 3, iclass 36, count 0 2006.173.10:56:27.49#ibcon#about to read 4, iclass 36, count 0 2006.173.10:56:27.49#ibcon#read 4, iclass 36, count 0 2006.173.10:56:27.49#ibcon#about to read 5, iclass 36, count 0 2006.173.10:56:27.49#ibcon#read 5, iclass 36, count 0 2006.173.10:56:27.49#ibcon#about to read 6, iclass 36, count 0 2006.173.10:56:27.49#ibcon#read 6, iclass 36, count 0 2006.173.10:56:27.49#ibcon#end of sib2, iclass 36, count 0 2006.173.10:56:27.49#ibcon#*after write, iclass 36, count 0 2006.173.10:56:27.49#ibcon#*before return 0, iclass 36, count 0 2006.173.10:56:27.49#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.10:56:27.49#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.10:56:27.49#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.10:56:27.49#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.10:56:27.49$vck44/vblo=3,649.99 2006.173.10:56:27.49#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.10:56:27.49#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.10:56:27.49#ibcon#ireg 17 cls_cnt 0 2006.173.10:56:27.49#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.10:56:27.49#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.10:56:27.49#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.10:56:27.49#ibcon#enter wrdev, iclass 38, count 0 2006.173.10:56:27.49#ibcon#first serial, iclass 38, count 0 2006.173.10:56:27.49#ibcon#enter sib2, iclass 38, count 0 2006.173.10:56:27.49#ibcon#flushed, iclass 38, count 0 2006.173.10:56:27.49#ibcon#about to write, iclass 38, count 0 2006.173.10:56:27.49#ibcon#wrote, iclass 38, count 0 2006.173.10:56:27.49#ibcon#about to read 3, iclass 38, count 0 2006.173.10:56:27.51#ibcon#read 3, iclass 38, count 0 2006.173.10:56:27.51#ibcon#about to read 4, iclass 38, count 0 2006.173.10:56:27.51#ibcon#read 4, iclass 38, count 0 2006.173.10:56:27.51#ibcon#about to read 5, iclass 38, count 0 2006.173.10:56:27.51#ibcon#read 5, iclass 38, count 0 2006.173.10:56:27.51#ibcon#about to read 6, iclass 38, count 0 2006.173.10:56:27.51#ibcon#read 6, iclass 38, count 0 2006.173.10:56:27.51#ibcon#end of sib2, iclass 38, count 0 2006.173.10:56:27.51#ibcon#*mode == 0, iclass 38, count 0 2006.173.10:56:27.51#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.10:56:27.51#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.10:56:27.51#ibcon#*before write, iclass 38, count 0 2006.173.10:56:27.51#ibcon#enter sib2, iclass 38, count 0 2006.173.10:56:27.51#ibcon#flushed, iclass 38, count 0 2006.173.10:56:27.51#ibcon#about to write, iclass 38, count 0 2006.173.10:56:27.51#ibcon#wrote, iclass 38, count 0 2006.173.10:56:27.51#ibcon#about to read 3, iclass 38, count 0 2006.173.10:56:27.55#ibcon#read 3, iclass 38, count 0 2006.173.10:56:27.55#ibcon#about to read 4, iclass 38, count 0 2006.173.10:56:27.55#ibcon#read 4, iclass 38, count 0 2006.173.10:56:27.55#ibcon#about to read 5, iclass 38, count 0 2006.173.10:56:27.55#ibcon#read 5, iclass 38, count 0 2006.173.10:56:27.55#ibcon#about to read 6, iclass 38, count 0 2006.173.10:56:27.55#ibcon#read 6, iclass 38, count 0 2006.173.10:56:27.55#ibcon#end of sib2, iclass 38, count 0 2006.173.10:56:27.55#ibcon#*after write, iclass 38, count 0 2006.173.10:56:27.55#ibcon#*before return 0, iclass 38, count 0 2006.173.10:56:27.55#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.10:56:27.55#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.10:56:27.55#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.10:56:27.55#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.10:56:27.55$vck44/vb=3,4 2006.173.10:56:27.55#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.10:56:27.55#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.10:56:27.55#ibcon#ireg 11 cls_cnt 2 2006.173.10:56:27.55#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.10:56:27.61#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.10:56:27.61#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.10:56:27.61#ibcon#enter wrdev, iclass 40, count 2 2006.173.10:56:27.61#ibcon#first serial, iclass 40, count 2 2006.173.10:56:27.61#ibcon#enter sib2, iclass 40, count 2 2006.173.10:56:27.61#ibcon#flushed, iclass 40, count 2 2006.173.10:56:27.61#ibcon#about to write, iclass 40, count 2 2006.173.10:56:27.61#ibcon#wrote, iclass 40, count 2 2006.173.10:56:27.61#ibcon#about to read 3, iclass 40, count 2 2006.173.10:56:27.63#ibcon#read 3, iclass 40, count 2 2006.173.10:56:27.63#ibcon#about to read 4, iclass 40, count 2 2006.173.10:56:27.63#ibcon#read 4, iclass 40, count 2 2006.173.10:56:27.63#ibcon#about to read 5, iclass 40, count 2 2006.173.10:56:27.63#ibcon#read 5, iclass 40, count 2 2006.173.10:56:27.63#ibcon#about to read 6, iclass 40, count 2 2006.173.10:56:27.63#ibcon#read 6, iclass 40, count 2 2006.173.10:56:27.63#ibcon#end of sib2, iclass 40, count 2 2006.173.10:56:27.63#ibcon#*mode == 0, iclass 40, count 2 2006.173.10:56:27.63#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.10:56:27.63#ibcon#[27=AT03-04\r\n] 2006.173.10:56:27.63#ibcon#*before write, iclass 40, count 2 2006.173.10:56:27.63#ibcon#enter sib2, iclass 40, count 2 2006.173.10:56:27.63#ibcon#flushed, iclass 40, count 2 2006.173.10:56:27.63#ibcon#about to write, iclass 40, count 2 2006.173.10:56:27.63#ibcon#wrote, iclass 40, count 2 2006.173.10:56:27.63#ibcon#about to read 3, iclass 40, count 2 2006.173.10:56:27.66#ibcon#read 3, iclass 40, count 2 2006.173.10:56:27.66#ibcon#about to read 4, iclass 40, count 2 2006.173.10:56:27.66#ibcon#read 4, iclass 40, count 2 2006.173.10:56:27.66#ibcon#about to read 5, iclass 40, count 2 2006.173.10:56:27.66#ibcon#read 5, iclass 40, count 2 2006.173.10:56:27.66#ibcon#about to read 6, iclass 40, count 2 2006.173.10:56:27.66#ibcon#read 6, iclass 40, count 2 2006.173.10:56:27.66#ibcon#end of sib2, iclass 40, count 2 2006.173.10:56:27.66#ibcon#*after write, iclass 40, count 2 2006.173.10:56:27.66#ibcon#*before return 0, iclass 40, count 2 2006.173.10:56:27.66#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.10:56:27.66#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.10:56:27.66#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.10:56:27.66#ibcon#ireg 7 cls_cnt 0 2006.173.10:56:27.66#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.10:56:27.78#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.10:56:27.78#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.10:56:27.78#ibcon#enter wrdev, iclass 40, count 0 2006.173.10:56:27.78#ibcon#first serial, iclass 40, count 0 2006.173.10:56:27.78#ibcon#enter sib2, iclass 40, count 0 2006.173.10:56:27.78#ibcon#flushed, iclass 40, count 0 2006.173.10:56:27.78#ibcon#about to write, iclass 40, count 0 2006.173.10:56:27.78#ibcon#wrote, iclass 40, count 0 2006.173.10:56:27.78#ibcon#about to read 3, iclass 40, count 0 2006.173.10:56:27.80#ibcon#read 3, iclass 40, count 0 2006.173.10:56:27.80#ibcon#about to read 4, iclass 40, count 0 2006.173.10:56:27.80#ibcon#read 4, iclass 40, count 0 2006.173.10:56:27.80#ibcon#about to read 5, iclass 40, count 0 2006.173.10:56:27.80#ibcon#read 5, iclass 40, count 0 2006.173.10:56:27.80#ibcon#about to read 6, iclass 40, count 0 2006.173.10:56:27.80#ibcon#read 6, iclass 40, count 0 2006.173.10:56:27.80#ibcon#end of sib2, iclass 40, count 0 2006.173.10:56:27.80#ibcon#*mode == 0, iclass 40, count 0 2006.173.10:56:27.80#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.10:56:27.80#ibcon#[27=USB\r\n] 2006.173.10:56:27.80#ibcon#*before write, iclass 40, count 0 2006.173.10:56:27.80#ibcon#enter sib2, iclass 40, count 0 2006.173.10:56:27.80#ibcon#flushed, iclass 40, count 0 2006.173.10:56:27.80#ibcon#about to write, iclass 40, count 0 2006.173.10:56:27.80#ibcon#wrote, iclass 40, count 0 2006.173.10:56:27.80#ibcon#about to read 3, iclass 40, count 0 2006.173.10:56:27.83#ibcon#read 3, iclass 40, count 0 2006.173.10:56:27.83#ibcon#about to read 4, iclass 40, count 0 2006.173.10:56:27.83#ibcon#read 4, iclass 40, count 0 2006.173.10:56:27.83#ibcon#about to read 5, iclass 40, count 0 2006.173.10:56:27.83#ibcon#read 5, iclass 40, count 0 2006.173.10:56:27.83#ibcon#about to read 6, iclass 40, count 0 2006.173.10:56:27.83#ibcon#read 6, iclass 40, count 0 2006.173.10:56:27.83#ibcon#end of sib2, iclass 40, count 0 2006.173.10:56:27.83#ibcon#*after write, iclass 40, count 0 2006.173.10:56:27.83#ibcon#*before return 0, iclass 40, count 0 2006.173.10:56:27.83#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.10:56:27.83#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.10:56:27.83#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.10:56:27.83#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.10:56:27.83$vck44/vblo=4,679.99 2006.173.10:56:27.83#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.10:56:27.83#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.10:56:27.83#ibcon#ireg 17 cls_cnt 0 2006.173.10:56:27.83#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.10:56:27.83#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.10:56:27.83#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.10:56:27.83#ibcon#enter wrdev, iclass 4, count 0 2006.173.10:56:27.83#ibcon#first serial, iclass 4, count 0 2006.173.10:56:27.83#ibcon#enter sib2, iclass 4, count 0 2006.173.10:56:27.83#ibcon#flushed, iclass 4, count 0 2006.173.10:56:27.83#ibcon#about to write, iclass 4, count 0 2006.173.10:56:27.83#ibcon#wrote, iclass 4, count 0 2006.173.10:56:27.83#ibcon#about to read 3, iclass 4, count 0 2006.173.10:56:27.85#ibcon#read 3, iclass 4, count 0 2006.173.10:56:27.85#ibcon#about to read 4, iclass 4, count 0 2006.173.10:56:27.85#ibcon#read 4, iclass 4, count 0 2006.173.10:56:27.85#ibcon#about to read 5, iclass 4, count 0 2006.173.10:56:27.85#ibcon#read 5, iclass 4, count 0 2006.173.10:56:27.85#ibcon#about to read 6, iclass 4, count 0 2006.173.10:56:27.85#ibcon#read 6, iclass 4, count 0 2006.173.10:56:27.85#ibcon#end of sib2, iclass 4, count 0 2006.173.10:56:27.85#ibcon#*mode == 0, iclass 4, count 0 2006.173.10:56:27.85#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.10:56:27.85#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.10:56:27.85#ibcon#*before write, iclass 4, count 0 2006.173.10:56:27.85#ibcon#enter sib2, iclass 4, count 0 2006.173.10:56:27.85#ibcon#flushed, iclass 4, count 0 2006.173.10:56:27.85#ibcon#about to write, iclass 4, count 0 2006.173.10:56:27.85#ibcon#wrote, iclass 4, count 0 2006.173.10:56:27.85#ibcon#about to read 3, iclass 4, count 0 2006.173.10:56:27.89#ibcon#read 3, iclass 4, count 0 2006.173.10:56:27.89#ibcon#about to read 4, iclass 4, count 0 2006.173.10:56:27.89#ibcon#read 4, iclass 4, count 0 2006.173.10:56:27.89#ibcon#about to read 5, iclass 4, count 0 2006.173.10:56:27.89#ibcon#read 5, iclass 4, count 0 2006.173.10:56:27.89#ibcon#about to read 6, iclass 4, count 0 2006.173.10:56:27.89#ibcon#read 6, iclass 4, count 0 2006.173.10:56:27.89#ibcon#end of sib2, iclass 4, count 0 2006.173.10:56:27.89#ibcon#*after write, iclass 4, count 0 2006.173.10:56:27.89#ibcon#*before return 0, iclass 4, count 0 2006.173.10:56:27.89#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.10:56:27.89#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.10:56:27.89#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.10:56:27.89#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.10:56:27.89$vck44/vb=4,4 2006.173.10:56:27.89#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.10:56:27.89#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.10:56:27.89#ibcon#ireg 11 cls_cnt 2 2006.173.10:56:27.89#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.10:56:27.95#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.10:56:27.95#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.10:56:27.95#ibcon#enter wrdev, iclass 6, count 2 2006.173.10:56:27.95#ibcon#first serial, iclass 6, count 2 2006.173.10:56:27.95#ibcon#enter sib2, iclass 6, count 2 2006.173.10:56:27.95#ibcon#flushed, iclass 6, count 2 2006.173.10:56:27.95#ibcon#about to write, iclass 6, count 2 2006.173.10:56:27.95#ibcon#wrote, iclass 6, count 2 2006.173.10:56:27.95#ibcon#about to read 3, iclass 6, count 2 2006.173.10:56:27.97#ibcon#read 3, iclass 6, count 2 2006.173.10:56:27.97#ibcon#about to read 4, iclass 6, count 2 2006.173.10:56:27.97#ibcon#read 4, iclass 6, count 2 2006.173.10:56:27.97#ibcon#about to read 5, iclass 6, count 2 2006.173.10:56:27.97#ibcon#read 5, iclass 6, count 2 2006.173.10:56:27.97#ibcon#about to read 6, iclass 6, count 2 2006.173.10:56:27.97#ibcon#read 6, iclass 6, count 2 2006.173.10:56:27.97#ibcon#end of sib2, iclass 6, count 2 2006.173.10:56:27.97#ibcon#*mode == 0, iclass 6, count 2 2006.173.10:56:27.97#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.10:56:27.97#ibcon#[27=AT04-04\r\n] 2006.173.10:56:27.97#ibcon#*before write, iclass 6, count 2 2006.173.10:56:27.97#ibcon#enter sib2, iclass 6, count 2 2006.173.10:56:27.97#ibcon#flushed, iclass 6, count 2 2006.173.10:56:27.97#ibcon#about to write, iclass 6, count 2 2006.173.10:56:27.97#ibcon#wrote, iclass 6, count 2 2006.173.10:56:27.97#ibcon#about to read 3, iclass 6, count 2 2006.173.10:56:28.00#ibcon#read 3, iclass 6, count 2 2006.173.10:56:28.00#ibcon#about to read 4, iclass 6, count 2 2006.173.10:56:28.00#ibcon#read 4, iclass 6, count 2 2006.173.10:56:28.00#ibcon#about to read 5, iclass 6, count 2 2006.173.10:56:28.00#ibcon#read 5, iclass 6, count 2 2006.173.10:56:28.00#ibcon#about to read 6, iclass 6, count 2 2006.173.10:56:28.00#ibcon#read 6, iclass 6, count 2 2006.173.10:56:28.00#ibcon#end of sib2, iclass 6, count 2 2006.173.10:56:28.00#ibcon#*after write, iclass 6, count 2 2006.173.10:56:28.00#ibcon#*before return 0, iclass 6, count 2 2006.173.10:56:28.00#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.10:56:28.00#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.10:56:28.00#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.10:56:28.00#ibcon#ireg 7 cls_cnt 0 2006.173.10:56:28.00#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.10:56:28.12#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.10:56:28.12#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.10:56:28.12#ibcon#enter wrdev, iclass 6, count 0 2006.173.10:56:28.12#ibcon#first serial, iclass 6, count 0 2006.173.10:56:28.12#ibcon#enter sib2, iclass 6, count 0 2006.173.10:56:28.12#ibcon#flushed, iclass 6, count 0 2006.173.10:56:28.12#ibcon#about to write, iclass 6, count 0 2006.173.10:56:28.12#ibcon#wrote, iclass 6, count 0 2006.173.10:56:28.12#ibcon#about to read 3, iclass 6, count 0 2006.173.10:56:28.14#ibcon#read 3, iclass 6, count 0 2006.173.10:56:28.14#ibcon#about to read 4, iclass 6, count 0 2006.173.10:56:28.14#ibcon#read 4, iclass 6, count 0 2006.173.10:56:28.14#ibcon#about to read 5, iclass 6, count 0 2006.173.10:56:28.14#ibcon#read 5, iclass 6, count 0 2006.173.10:56:28.14#ibcon#about to read 6, iclass 6, count 0 2006.173.10:56:28.14#ibcon#read 6, iclass 6, count 0 2006.173.10:56:28.14#ibcon#end of sib2, iclass 6, count 0 2006.173.10:56:28.14#ibcon#*mode == 0, iclass 6, count 0 2006.173.10:56:28.14#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.10:56:28.14#ibcon#[27=USB\r\n] 2006.173.10:56:28.14#ibcon#*before write, iclass 6, count 0 2006.173.10:56:28.14#ibcon#enter sib2, iclass 6, count 0 2006.173.10:56:28.14#ibcon#flushed, iclass 6, count 0 2006.173.10:56:28.14#ibcon#about to write, iclass 6, count 0 2006.173.10:56:28.14#ibcon#wrote, iclass 6, count 0 2006.173.10:56:28.14#ibcon#about to read 3, iclass 6, count 0 2006.173.10:56:28.17#ibcon#read 3, iclass 6, count 0 2006.173.10:56:28.17#ibcon#about to read 4, iclass 6, count 0 2006.173.10:56:28.17#ibcon#read 4, iclass 6, count 0 2006.173.10:56:28.17#ibcon#about to read 5, iclass 6, count 0 2006.173.10:56:28.17#ibcon#read 5, iclass 6, count 0 2006.173.10:56:28.17#ibcon#about to read 6, iclass 6, count 0 2006.173.10:56:28.17#ibcon#read 6, iclass 6, count 0 2006.173.10:56:28.17#ibcon#end of sib2, iclass 6, count 0 2006.173.10:56:28.17#ibcon#*after write, iclass 6, count 0 2006.173.10:56:28.17#ibcon#*before return 0, iclass 6, count 0 2006.173.10:56:28.17#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.10:56:28.17#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.10:56:28.17#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.10:56:28.17#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.10:56:28.17$vck44/vblo=5,709.99 2006.173.10:56:28.17#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.10:56:28.17#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.10:56:28.17#ibcon#ireg 17 cls_cnt 0 2006.173.10:56:28.17#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.10:56:28.17#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.10:56:28.17#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.10:56:28.17#ibcon#enter wrdev, iclass 10, count 0 2006.173.10:56:28.17#ibcon#first serial, iclass 10, count 0 2006.173.10:56:28.17#ibcon#enter sib2, iclass 10, count 0 2006.173.10:56:28.17#ibcon#flushed, iclass 10, count 0 2006.173.10:56:28.17#ibcon#about to write, iclass 10, count 0 2006.173.10:56:28.17#ibcon#wrote, iclass 10, count 0 2006.173.10:56:28.17#ibcon#about to read 3, iclass 10, count 0 2006.173.10:56:28.19#ibcon#read 3, iclass 10, count 0 2006.173.10:56:28.19#ibcon#about to read 4, iclass 10, count 0 2006.173.10:56:28.19#ibcon#read 4, iclass 10, count 0 2006.173.10:56:28.19#ibcon#about to read 5, iclass 10, count 0 2006.173.10:56:28.19#ibcon#read 5, iclass 10, count 0 2006.173.10:56:28.19#ibcon#about to read 6, iclass 10, count 0 2006.173.10:56:28.19#ibcon#read 6, iclass 10, count 0 2006.173.10:56:28.19#ibcon#end of sib2, iclass 10, count 0 2006.173.10:56:28.19#ibcon#*mode == 0, iclass 10, count 0 2006.173.10:56:28.19#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.10:56:28.19#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.10:56:28.19#ibcon#*before write, iclass 10, count 0 2006.173.10:56:28.19#ibcon#enter sib2, iclass 10, count 0 2006.173.10:56:28.19#ibcon#flushed, iclass 10, count 0 2006.173.10:56:28.19#ibcon#about to write, iclass 10, count 0 2006.173.10:56:28.19#ibcon#wrote, iclass 10, count 0 2006.173.10:56:28.19#ibcon#about to read 3, iclass 10, count 0 2006.173.10:56:28.23#ibcon#read 3, iclass 10, count 0 2006.173.10:56:28.23#ibcon#about to read 4, iclass 10, count 0 2006.173.10:56:28.23#ibcon#read 4, iclass 10, count 0 2006.173.10:56:28.23#ibcon#about to read 5, iclass 10, count 0 2006.173.10:56:28.23#ibcon#read 5, iclass 10, count 0 2006.173.10:56:28.23#ibcon#about to read 6, iclass 10, count 0 2006.173.10:56:28.23#ibcon#read 6, iclass 10, count 0 2006.173.10:56:28.23#ibcon#end of sib2, iclass 10, count 0 2006.173.10:56:28.23#ibcon#*after write, iclass 10, count 0 2006.173.10:56:28.23#ibcon#*before return 0, iclass 10, count 0 2006.173.10:56:28.23#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.10:56:28.23#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.10:56:28.23#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.10:56:28.23#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.10:56:28.23$vck44/vb=5,4 2006.173.10:56:28.23#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.10:56:28.23#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.10:56:28.23#ibcon#ireg 11 cls_cnt 2 2006.173.10:56:28.23#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.10:56:28.29#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.10:56:28.29#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.10:56:28.29#ibcon#enter wrdev, iclass 12, count 2 2006.173.10:56:28.29#ibcon#first serial, iclass 12, count 2 2006.173.10:56:28.29#ibcon#enter sib2, iclass 12, count 2 2006.173.10:56:28.29#ibcon#flushed, iclass 12, count 2 2006.173.10:56:28.29#ibcon#about to write, iclass 12, count 2 2006.173.10:56:28.29#ibcon#wrote, iclass 12, count 2 2006.173.10:56:28.29#ibcon#about to read 3, iclass 12, count 2 2006.173.10:56:28.31#ibcon#read 3, iclass 12, count 2 2006.173.10:56:28.31#ibcon#about to read 4, iclass 12, count 2 2006.173.10:56:28.31#ibcon#read 4, iclass 12, count 2 2006.173.10:56:28.31#ibcon#about to read 5, iclass 12, count 2 2006.173.10:56:28.31#ibcon#read 5, iclass 12, count 2 2006.173.10:56:28.31#ibcon#about to read 6, iclass 12, count 2 2006.173.10:56:28.31#ibcon#read 6, iclass 12, count 2 2006.173.10:56:28.31#ibcon#end of sib2, iclass 12, count 2 2006.173.10:56:28.31#ibcon#*mode == 0, iclass 12, count 2 2006.173.10:56:28.31#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.10:56:28.31#ibcon#[27=AT05-04\r\n] 2006.173.10:56:28.31#ibcon#*before write, iclass 12, count 2 2006.173.10:56:28.31#ibcon#enter sib2, iclass 12, count 2 2006.173.10:56:28.31#ibcon#flushed, iclass 12, count 2 2006.173.10:56:28.31#ibcon#about to write, iclass 12, count 2 2006.173.10:56:28.31#ibcon#wrote, iclass 12, count 2 2006.173.10:56:28.31#ibcon#about to read 3, iclass 12, count 2 2006.173.10:56:28.34#ibcon#read 3, iclass 12, count 2 2006.173.10:56:28.34#ibcon#about to read 4, iclass 12, count 2 2006.173.10:56:28.34#ibcon#read 4, iclass 12, count 2 2006.173.10:56:28.34#ibcon#about to read 5, iclass 12, count 2 2006.173.10:56:28.34#ibcon#read 5, iclass 12, count 2 2006.173.10:56:28.34#ibcon#about to read 6, iclass 12, count 2 2006.173.10:56:28.34#ibcon#read 6, iclass 12, count 2 2006.173.10:56:28.34#ibcon#end of sib2, iclass 12, count 2 2006.173.10:56:28.34#ibcon#*after write, iclass 12, count 2 2006.173.10:56:28.34#ibcon#*before return 0, iclass 12, count 2 2006.173.10:56:28.34#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.10:56:28.34#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.10:56:28.34#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.10:56:28.34#ibcon#ireg 7 cls_cnt 0 2006.173.10:56:28.34#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.10:56:28.46#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.10:56:28.46#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.10:56:28.46#ibcon#enter wrdev, iclass 12, count 0 2006.173.10:56:28.46#ibcon#first serial, iclass 12, count 0 2006.173.10:56:28.46#ibcon#enter sib2, iclass 12, count 0 2006.173.10:56:28.46#ibcon#flushed, iclass 12, count 0 2006.173.10:56:28.46#ibcon#about to write, iclass 12, count 0 2006.173.10:56:28.46#ibcon#wrote, iclass 12, count 0 2006.173.10:56:28.46#ibcon#about to read 3, iclass 12, count 0 2006.173.10:56:28.48#ibcon#read 3, iclass 12, count 0 2006.173.10:56:28.48#ibcon#about to read 4, iclass 12, count 0 2006.173.10:56:28.48#ibcon#read 4, iclass 12, count 0 2006.173.10:56:28.48#ibcon#about to read 5, iclass 12, count 0 2006.173.10:56:28.48#ibcon#read 5, iclass 12, count 0 2006.173.10:56:28.48#ibcon#about to read 6, iclass 12, count 0 2006.173.10:56:28.48#ibcon#read 6, iclass 12, count 0 2006.173.10:56:28.48#ibcon#end of sib2, iclass 12, count 0 2006.173.10:56:28.48#ibcon#*mode == 0, iclass 12, count 0 2006.173.10:56:28.48#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.10:56:28.48#ibcon#[27=USB\r\n] 2006.173.10:56:28.48#ibcon#*before write, iclass 12, count 0 2006.173.10:56:28.48#ibcon#enter sib2, iclass 12, count 0 2006.173.10:56:28.48#ibcon#flushed, iclass 12, count 0 2006.173.10:56:28.48#ibcon#about to write, iclass 12, count 0 2006.173.10:56:28.48#ibcon#wrote, iclass 12, count 0 2006.173.10:56:28.48#ibcon#about to read 3, iclass 12, count 0 2006.173.10:56:28.51#ibcon#read 3, iclass 12, count 0 2006.173.10:56:28.51#ibcon#about to read 4, iclass 12, count 0 2006.173.10:56:28.51#ibcon#read 4, iclass 12, count 0 2006.173.10:56:28.51#ibcon#about to read 5, iclass 12, count 0 2006.173.10:56:28.51#ibcon#read 5, iclass 12, count 0 2006.173.10:56:28.51#ibcon#about to read 6, iclass 12, count 0 2006.173.10:56:28.51#ibcon#read 6, iclass 12, count 0 2006.173.10:56:28.51#ibcon#end of sib2, iclass 12, count 0 2006.173.10:56:28.51#ibcon#*after write, iclass 12, count 0 2006.173.10:56:28.51#ibcon#*before return 0, iclass 12, count 0 2006.173.10:56:28.51#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.10:56:28.51#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.10:56:28.51#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.10:56:28.51#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.10:56:28.51$vck44/vblo=6,719.99 2006.173.10:56:28.51#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.10:56:28.51#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.10:56:28.51#ibcon#ireg 17 cls_cnt 0 2006.173.10:56:28.51#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.10:56:28.51#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.10:56:28.51#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.10:56:28.51#ibcon#enter wrdev, iclass 14, count 0 2006.173.10:56:28.51#ibcon#first serial, iclass 14, count 0 2006.173.10:56:28.51#ibcon#enter sib2, iclass 14, count 0 2006.173.10:56:28.51#ibcon#flushed, iclass 14, count 0 2006.173.10:56:28.51#ibcon#about to write, iclass 14, count 0 2006.173.10:56:28.51#ibcon#wrote, iclass 14, count 0 2006.173.10:56:28.51#ibcon#about to read 3, iclass 14, count 0 2006.173.10:56:28.53#ibcon#read 3, iclass 14, count 0 2006.173.10:56:28.53#ibcon#about to read 4, iclass 14, count 0 2006.173.10:56:28.53#ibcon#read 4, iclass 14, count 0 2006.173.10:56:28.53#ibcon#about to read 5, iclass 14, count 0 2006.173.10:56:28.53#ibcon#read 5, iclass 14, count 0 2006.173.10:56:28.53#ibcon#about to read 6, iclass 14, count 0 2006.173.10:56:28.53#ibcon#read 6, iclass 14, count 0 2006.173.10:56:28.53#ibcon#end of sib2, iclass 14, count 0 2006.173.10:56:28.53#ibcon#*mode == 0, iclass 14, count 0 2006.173.10:56:28.53#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.10:56:28.53#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.10:56:28.53#ibcon#*before write, iclass 14, count 0 2006.173.10:56:28.53#ibcon#enter sib2, iclass 14, count 0 2006.173.10:56:28.53#ibcon#flushed, iclass 14, count 0 2006.173.10:56:28.53#ibcon#about to write, iclass 14, count 0 2006.173.10:56:28.53#ibcon#wrote, iclass 14, count 0 2006.173.10:56:28.53#ibcon#about to read 3, iclass 14, count 0 2006.173.10:56:28.57#ibcon#read 3, iclass 14, count 0 2006.173.10:56:28.57#ibcon#about to read 4, iclass 14, count 0 2006.173.10:56:28.57#ibcon#read 4, iclass 14, count 0 2006.173.10:56:28.57#ibcon#about to read 5, iclass 14, count 0 2006.173.10:56:28.57#ibcon#read 5, iclass 14, count 0 2006.173.10:56:28.57#ibcon#about to read 6, iclass 14, count 0 2006.173.10:56:28.57#ibcon#read 6, iclass 14, count 0 2006.173.10:56:28.57#ibcon#end of sib2, iclass 14, count 0 2006.173.10:56:28.57#ibcon#*after write, iclass 14, count 0 2006.173.10:56:28.57#ibcon#*before return 0, iclass 14, count 0 2006.173.10:56:28.57#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.10:56:28.57#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.10:56:28.57#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.10:56:28.57#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.10:56:28.57$vck44/vb=6,4 2006.173.10:56:28.57#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.10:56:28.57#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.10:56:28.57#ibcon#ireg 11 cls_cnt 2 2006.173.10:56:28.57#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.10:56:28.63#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.10:56:28.63#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.10:56:28.63#ibcon#enter wrdev, iclass 16, count 2 2006.173.10:56:28.63#ibcon#first serial, iclass 16, count 2 2006.173.10:56:28.63#ibcon#enter sib2, iclass 16, count 2 2006.173.10:56:28.63#ibcon#flushed, iclass 16, count 2 2006.173.10:56:28.63#ibcon#about to write, iclass 16, count 2 2006.173.10:56:28.63#ibcon#wrote, iclass 16, count 2 2006.173.10:56:28.63#ibcon#about to read 3, iclass 16, count 2 2006.173.10:56:28.65#ibcon#read 3, iclass 16, count 2 2006.173.10:56:28.65#ibcon#about to read 4, iclass 16, count 2 2006.173.10:56:28.65#ibcon#read 4, iclass 16, count 2 2006.173.10:56:28.65#ibcon#about to read 5, iclass 16, count 2 2006.173.10:56:28.65#ibcon#read 5, iclass 16, count 2 2006.173.10:56:28.65#ibcon#about to read 6, iclass 16, count 2 2006.173.10:56:28.65#ibcon#read 6, iclass 16, count 2 2006.173.10:56:28.65#ibcon#end of sib2, iclass 16, count 2 2006.173.10:56:28.65#ibcon#*mode == 0, iclass 16, count 2 2006.173.10:56:28.65#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.10:56:28.65#ibcon#[27=AT06-04\r\n] 2006.173.10:56:28.65#ibcon#*before write, iclass 16, count 2 2006.173.10:56:28.65#ibcon#enter sib2, iclass 16, count 2 2006.173.10:56:28.65#ibcon#flushed, iclass 16, count 2 2006.173.10:56:28.65#ibcon#about to write, iclass 16, count 2 2006.173.10:56:28.65#ibcon#wrote, iclass 16, count 2 2006.173.10:56:28.65#ibcon#about to read 3, iclass 16, count 2 2006.173.10:56:28.68#ibcon#read 3, iclass 16, count 2 2006.173.10:56:28.68#ibcon#about to read 4, iclass 16, count 2 2006.173.10:56:28.68#ibcon#read 4, iclass 16, count 2 2006.173.10:56:28.68#ibcon#about to read 5, iclass 16, count 2 2006.173.10:56:28.68#ibcon#read 5, iclass 16, count 2 2006.173.10:56:28.68#ibcon#about to read 6, iclass 16, count 2 2006.173.10:56:28.68#ibcon#read 6, iclass 16, count 2 2006.173.10:56:28.68#ibcon#end of sib2, iclass 16, count 2 2006.173.10:56:28.68#ibcon#*after write, iclass 16, count 2 2006.173.10:56:28.68#ibcon#*before return 0, iclass 16, count 2 2006.173.10:56:28.68#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.10:56:28.68#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.10:56:28.68#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.10:56:28.68#ibcon#ireg 7 cls_cnt 0 2006.173.10:56:28.68#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.10:56:28.80#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.10:56:28.80#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.10:56:28.80#ibcon#enter wrdev, iclass 16, count 0 2006.173.10:56:28.80#ibcon#first serial, iclass 16, count 0 2006.173.10:56:28.80#ibcon#enter sib2, iclass 16, count 0 2006.173.10:56:28.80#ibcon#flushed, iclass 16, count 0 2006.173.10:56:28.80#ibcon#about to write, iclass 16, count 0 2006.173.10:56:28.80#ibcon#wrote, iclass 16, count 0 2006.173.10:56:28.80#ibcon#about to read 3, iclass 16, count 0 2006.173.10:56:28.82#ibcon#read 3, iclass 16, count 0 2006.173.10:56:28.82#ibcon#about to read 4, iclass 16, count 0 2006.173.10:56:28.82#ibcon#read 4, iclass 16, count 0 2006.173.10:56:28.82#ibcon#about to read 5, iclass 16, count 0 2006.173.10:56:28.82#ibcon#read 5, iclass 16, count 0 2006.173.10:56:28.82#ibcon#about to read 6, iclass 16, count 0 2006.173.10:56:28.82#ibcon#read 6, iclass 16, count 0 2006.173.10:56:28.82#ibcon#end of sib2, iclass 16, count 0 2006.173.10:56:28.82#ibcon#*mode == 0, iclass 16, count 0 2006.173.10:56:28.82#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.10:56:28.82#ibcon#[27=USB\r\n] 2006.173.10:56:28.82#ibcon#*before write, iclass 16, count 0 2006.173.10:56:28.82#ibcon#enter sib2, iclass 16, count 0 2006.173.10:56:28.82#ibcon#flushed, iclass 16, count 0 2006.173.10:56:28.82#ibcon#about to write, iclass 16, count 0 2006.173.10:56:28.82#ibcon#wrote, iclass 16, count 0 2006.173.10:56:28.82#ibcon#about to read 3, iclass 16, count 0 2006.173.10:56:28.85#ibcon#read 3, iclass 16, count 0 2006.173.10:56:28.85#ibcon#about to read 4, iclass 16, count 0 2006.173.10:56:28.85#ibcon#read 4, iclass 16, count 0 2006.173.10:56:28.85#ibcon#about to read 5, iclass 16, count 0 2006.173.10:56:28.85#ibcon#read 5, iclass 16, count 0 2006.173.10:56:28.85#ibcon#about to read 6, iclass 16, count 0 2006.173.10:56:28.85#ibcon#read 6, iclass 16, count 0 2006.173.10:56:28.85#ibcon#end of sib2, iclass 16, count 0 2006.173.10:56:28.85#ibcon#*after write, iclass 16, count 0 2006.173.10:56:28.85#ibcon#*before return 0, iclass 16, count 0 2006.173.10:56:28.85#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.10:56:28.85#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.10:56:28.85#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.10:56:28.85#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.10:56:28.85$vck44/vblo=7,734.99 2006.173.10:56:28.85#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.10:56:28.85#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.10:56:28.85#ibcon#ireg 17 cls_cnt 0 2006.173.10:56:28.85#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.10:56:28.85#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.10:56:28.85#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.10:56:28.85#ibcon#enter wrdev, iclass 18, count 0 2006.173.10:56:28.85#ibcon#first serial, iclass 18, count 0 2006.173.10:56:28.85#ibcon#enter sib2, iclass 18, count 0 2006.173.10:56:28.85#ibcon#flushed, iclass 18, count 0 2006.173.10:56:28.85#ibcon#about to write, iclass 18, count 0 2006.173.10:56:28.85#ibcon#wrote, iclass 18, count 0 2006.173.10:56:28.85#ibcon#about to read 3, iclass 18, count 0 2006.173.10:56:28.87#ibcon#read 3, iclass 18, count 0 2006.173.10:56:28.87#ibcon#about to read 4, iclass 18, count 0 2006.173.10:56:28.87#ibcon#read 4, iclass 18, count 0 2006.173.10:56:28.87#ibcon#about to read 5, iclass 18, count 0 2006.173.10:56:28.87#ibcon#read 5, iclass 18, count 0 2006.173.10:56:28.87#ibcon#about to read 6, iclass 18, count 0 2006.173.10:56:28.87#ibcon#read 6, iclass 18, count 0 2006.173.10:56:28.87#ibcon#end of sib2, iclass 18, count 0 2006.173.10:56:28.87#ibcon#*mode == 0, iclass 18, count 0 2006.173.10:56:28.87#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.10:56:28.87#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.10:56:28.87#ibcon#*before write, iclass 18, count 0 2006.173.10:56:28.87#ibcon#enter sib2, iclass 18, count 0 2006.173.10:56:28.87#ibcon#flushed, iclass 18, count 0 2006.173.10:56:28.87#ibcon#about to write, iclass 18, count 0 2006.173.10:56:28.87#ibcon#wrote, iclass 18, count 0 2006.173.10:56:28.87#ibcon#about to read 3, iclass 18, count 0 2006.173.10:56:28.91#ibcon#read 3, iclass 18, count 0 2006.173.10:56:28.91#ibcon#about to read 4, iclass 18, count 0 2006.173.10:56:28.91#ibcon#read 4, iclass 18, count 0 2006.173.10:56:28.91#ibcon#about to read 5, iclass 18, count 0 2006.173.10:56:28.91#ibcon#read 5, iclass 18, count 0 2006.173.10:56:28.91#ibcon#about to read 6, iclass 18, count 0 2006.173.10:56:28.91#ibcon#read 6, iclass 18, count 0 2006.173.10:56:28.91#ibcon#end of sib2, iclass 18, count 0 2006.173.10:56:28.91#ibcon#*after write, iclass 18, count 0 2006.173.10:56:28.91#ibcon#*before return 0, iclass 18, count 0 2006.173.10:56:28.91#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.10:56:28.91#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.10:56:28.91#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.10:56:28.91#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.10:56:28.91$vck44/vb=7,4 2006.173.10:56:28.91#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.10:56:28.91#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.10:56:28.91#ibcon#ireg 11 cls_cnt 2 2006.173.10:56:28.91#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.10:56:28.97#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.10:56:28.97#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.10:56:28.97#ibcon#enter wrdev, iclass 20, count 2 2006.173.10:56:28.97#ibcon#first serial, iclass 20, count 2 2006.173.10:56:28.97#ibcon#enter sib2, iclass 20, count 2 2006.173.10:56:28.97#ibcon#flushed, iclass 20, count 2 2006.173.10:56:28.97#ibcon#about to write, iclass 20, count 2 2006.173.10:56:28.97#ibcon#wrote, iclass 20, count 2 2006.173.10:56:28.97#ibcon#about to read 3, iclass 20, count 2 2006.173.10:56:28.99#ibcon#read 3, iclass 20, count 2 2006.173.10:56:28.99#ibcon#about to read 4, iclass 20, count 2 2006.173.10:56:28.99#ibcon#read 4, iclass 20, count 2 2006.173.10:56:28.99#ibcon#about to read 5, iclass 20, count 2 2006.173.10:56:28.99#ibcon#read 5, iclass 20, count 2 2006.173.10:56:28.99#ibcon#about to read 6, iclass 20, count 2 2006.173.10:56:28.99#ibcon#read 6, iclass 20, count 2 2006.173.10:56:28.99#ibcon#end of sib2, iclass 20, count 2 2006.173.10:56:28.99#ibcon#*mode == 0, iclass 20, count 2 2006.173.10:56:28.99#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.10:56:28.99#ibcon#[27=AT07-04\r\n] 2006.173.10:56:28.99#ibcon#*before write, iclass 20, count 2 2006.173.10:56:28.99#ibcon#enter sib2, iclass 20, count 2 2006.173.10:56:28.99#ibcon#flushed, iclass 20, count 2 2006.173.10:56:28.99#ibcon#about to write, iclass 20, count 2 2006.173.10:56:28.99#ibcon#wrote, iclass 20, count 2 2006.173.10:56:28.99#ibcon#about to read 3, iclass 20, count 2 2006.173.10:56:29.02#ibcon#read 3, iclass 20, count 2 2006.173.10:56:29.02#ibcon#about to read 4, iclass 20, count 2 2006.173.10:56:29.02#ibcon#read 4, iclass 20, count 2 2006.173.10:56:29.02#ibcon#about to read 5, iclass 20, count 2 2006.173.10:56:29.02#ibcon#read 5, iclass 20, count 2 2006.173.10:56:29.02#ibcon#about to read 6, iclass 20, count 2 2006.173.10:56:29.02#ibcon#read 6, iclass 20, count 2 2006.173.10:56:29.02#ibcon#end of sib2, iclass 20, count 2 2006.173.10:56:29.02#ibcon#*after write, iclass 20, count 2 2006.173.10:56:29.02#ibcon#*before return 0, iclass 20, count 2 2006.173.10:56:29.02#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.10:56:29.02#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.10:56:29.02#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.10:56:29.02#ibcon#ireg 7 cls_cnt 0 2006.173.10:56:29.02#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.10:56:29.14#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.10:56:29.14#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.10:56:29.14#ibcon#enter wrdev, iclass 20, count 0 2006.173.10:56:29.14#ibcon#first serial, iclass 20, count 0 2006.173.10:56:29.14#ibcon#enter sib2, iclass 20, count 0 2006.173.10:56:29.14#ibcon#flushed, iclass 20, count 0 2006.173.10:56:29.14#ibcon#about to write, iclass 20, count 0 2006.173.10:56:29.14#ibcon#wrote, iclass 20, count 0 2006.173.10:56:29.14#ibcon#about to read 3, iclass 20, count 0 2006.173.10:56:29.16#ibcon#read 3, iclass 20, count 0 2006.173.10:56:29.16#ibcon#about to read 4, iclass 20, count 0 2006.173.10:56:29.16#ibcon#read 4, iclass 20, count 0 2006.173.10:56:29.16#ibcon#about to read 5, iclass 20, count 0 2006.173.10:56:29.16#ibcon#read 5, iclass 20, count 0 2006.173.10:56:29.16#ibcon#about to read 6, iclass 20, count 0 2006.173.10:56:29.16#ibcon#read 6, iclass 20, count 0 2006.173.10:56:29.16#ibcon#end of sib2, iclass 20, count 0 2006.173.10:56:29.16#ibcon#*mode == 0, iclass 20, count 0 2006.173.10:56:29.16#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.10:56:29.16#ibcon#[27=USB\r\n] 2006.173.10:56:29.16#ibcon#*before write, iclass 20, count 0 2006.173.10:56:29.16#ibcon#enter sib2, iclass 20, count 0 2006.173.10:56:29.16#ibcon#flushed, iclass 20, count 0 2006.173.10:56:29.16#ibcon#about to write, iclass 20, count 0 2006.173.10:56:29.16#ibcon#wrote, iclass 20, count 0 2006.173.10:56:29.16#ibcon#about to read 3, iclass 20, count 0 2006.173.10:56:29.19#ibcon#read 3, iclass 20, count 0 2006.173.10:56:29.19#ibcon#about to read 4, iclass 20, count 0 2006.173.10:56:29.19#ibcon#read 4, iclass 20, count 0 2006.173.10:56:29.19#ibcon#about to read 5, iclass 20, count 0 2006.173.10:56:29.19#ibcon#read 5, iclass 20, count 0 2006.173.10:56:29.19#ibcon#about to read 6, iclass 20, count 0 2006.173.10:56:29.19#ibcon#read 6, iclass 20, count 0 2006.173.10:56:29.19#ibcon#end of sib2, iclass 20, count 0 2006.173.10:56:29.19#ibcon#*after write, iclass 20, count 0 2006.173.10:56:29.19#ibcon#*before return 0, iclass 20, count 0 2006.173.10:56:29.19#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.10:56:29.19#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.10:56:29.19#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.10:56:29.19#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.10:56:29.19$vck44/vblo=8,744.99 2006.173.10:56:29.19#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.10:56:29.19#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.10:56:29.19#ibcon#ireg 17 cls_cnt 0 2006.173.10:56:29.19#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.10:56:29.19#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.10:56:29.19#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.10:56:29.19#ibcon#enter wrdev, iclass 22, count 0 2006.173.10:56:29.19#ibcon#first serial, iclass 22, count 0 2006.173.10:56:29.19#ibcon#enter sib2, iclass 22, count 0 2006.173.10:56:29.19#ibcon#flushed, iclass 22, count 0 2006.173.10:56:29.19#ibcon#about to write, iclass 22, count 0 2006.173.10:56:29.19#ibcon#wrote, iclass 22, count 0 2006.173.10:56:29.19#ibcon#about to read 3, iclass 22, count 0 2006.173.10:56:29.21#ibcon#read 3, iclass 22, count 0 2006.173.10:56:29.21#ibcon#about to read 4, iclass 22, count 0 2006.173.10:56:29.21#ibcon#read 4, iclass 22, count 0 2006.173.10:56:29.21#ibcon#about to read 5, iclass 22, count 0 2006.173.10:56:29.21#ibcon#read 5, iclass 22, count 0 2006.173.10:56:29.21#ibcon#about to read 6, iclass 22, count 0 2006.173.10:56:29.21#ibcon#read 6, iclass 22, count 0 2006.173.10:56:29.21#ibcon#end of sib2, iclass 22, count 0 2006.173.10:56:29.21#ibcon#*mode == 0, iclass 22, count 0 2006.173.10:56:29.21#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.10:56:29.21#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.10:56:29.21#ibcon#*before write, iclass 22, count 0 2006.173.10:56:29.21#ibcon#enter sib2, iclass 22, count 0 2006.173.10:56:29.21#ibcon#flushed, iclass 22, count 0 2006.173.10:56:29.21#ibcon#about to write, iclass 22, count 0 2006.173.10:56:29.21#ibcon#wrote, iclass 22, count 0 2006.173.10:56:29.21#ibcon#about to read 3, iclass 22, count 0 2006.173.10:56:29.25#ibcon#read 3, iclass 22, count 0 2006.173.10:56:29.25#ibcon#about to read 4, iclass 22, count 0 2006.173.10:56:29.25#ibcon#read 4, iclass 22, count 0 2006.173.10:56:29.25#ibcon#about to read 5, iclass 22, count 0 2006.173.10:56:29.25#ibcon#read 5, iclass 22, count 0 2006.173.10:56:29.25#ibcon#about to read 6, iclass 22, count 0 2006.173.10:56:29.25#ibcon#read 6, iclass 22, count 0 2006.173.10:56:29.25#ibcon#end of sib2, iclass 22, count 0 2006.173.10:56:29.25#ibcon#*after write, iclass 22, count 0 2006.173.10:56:29.25#ibcon#*before return 0, iclass 22, count 0 2006.173.10:56:29.25#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.10:56:29.25#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.10:56:29.25#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.10:56:29.25#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.10:56:29.25$vck44/vb=8,4 2006.173.10:56:29.25#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.10:56:29.25#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.10:56:29.25#ibcon#ireg 11 cls_cnt 2 2006.173.10:56:29.25#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.10:56:29.31#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.10:56:29.31#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.10:56:29.31#ibcon#enter wrdev, iclass 24, count 2 2006.173.10:56:29.31#ibcon#first serial, iclass 24, count 2 2006.173.10:56:29.31#ibcon#enter sib2, iclass 24, count 2 2006.173.10:56:29.31#ibcon#flushed, iclass 24, count 2 2006.173.10:56:29.31#ibcon#about to write, iclass 24, count 2 2006.173.10:56:29.31#ibcon#wrote, iclass 24, count 2 2006.173.10:56:29.31#ibcon#about to read 3, iclass 24, count 2 2006.173.10:56:29.33#ibcon#read 3, iclass 24, count 2 2006.173.10:56:29.33#ibcon#about to read 4, iclass 24, count 2 2006.173.10:56:29.33#ibcon#read 4, iclass 24, count 2 2006.173.10:56:29.33#ibcon#about to read 5, iclass 24, count 2 2006.173.10:56:29.33#ibcon#read 5, iclass 24, count 2 2006.173.10:56:29.33#ibcon#about to read 6, iclass 24, count 2 2006.173.10:56:29.33#ibcon#read 6, iclass 24, count 2 2006.173.10:56:29.33#ibcon#end of sib2, iclass 24, count 2 2006.173.10:56:29.33#ibcon#*mode == 0, iclass 24, count 2 2006.173.10:56:29.33#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.10:56:29.33#ibcon#[27=AT08-04\r\n] 2006.173.10:56:29.33#ibcon#*before write, iclass 24, count 2 2006.173.10:56:29.33#ibcon#enter sib2, iclass 24, count 2 2006.173.10:56:29.33#ibcon#flushed, iclass 24, count 2 2006.173.10:56:29.33#ibcon#about to write, iclass 24, count 2 2006.173.10:56:29.33#ibcon#wrote, iclass 24, count 2 2006.173.10:56:29.33#ibcon#about to read 3, iclass 24, count 2 2006.173.10:56:29.36#ibcon#read 3, iclass 24, count 2 2006.173.10:56:29.36#ibcon#about to read 4, iclass 24, count 2 2006.173.10:56:29.36#ibcon#read 4, iclass 24, count 2 2006.173.10:56:29.36#ibcon#about to read 5, iclass 24, count 2 2006.173.10:56:29.36#ibcon#read 5, iclass 24, count 2 2006.173.10:56:29.36#ibcon#about to read 6, iclass 24, count 2 2006.173.10:56:29.36#ibcon#read 6, iclass 24, count 2 2006.173.10:56:29.36#ibcon#end of sib2, iclass 24, count 2 2006.173.10:56:29.36#ibcon#*after write, iclass 24, count 2 2006.173.10:56:29.36#ibcon#*before return 0, iclass 24, count 2 2006.173.10:56:29.36#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.10:56:29.36#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.10:56:29.36#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.10:56:29.36#ibcon#ireg 7 cls_cnt 0 2006.173.10:56:29.36#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.10:56:29.48#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.10:56:29.48#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.10:56:29.48#ibcon#enter wrdev, iclass 24, count 0 2006.173.10:56:29.48#ibcon#first serial, iclass 24, count 0 2006.173.10:56:29.48#ibcon#enter sib2, iclass 24, count 0 2006.173.10:56:29.48#ibcon#flushed, iclass 24, count 0 2006.173.10:56:29.48#ibcon#about to write, iclass 24, count 0 2006.173.10:56:29.48#ibcon#wrote, iclass 24, count 0 2006.173.10:56:29.48#ibcon#about to read 3, iclass 24, count 0 2006.173.10:56:29.50#ibcon#read 3, iclass 24, count 0 2006.173.10:56:29.50#ibcon#about to read 4, iclass 24, count 0 2006.173.10:56:29.50#ibcon#read 4, iclass 24, count 0 2006.173.10:56:29.50#ibcon#about to read 5, iclass 24, count 0 2006.173.10:56:29.50#ibcon#read 5, iclass 24, count 0 2006.173.10:56:29.50#ibcon#about to read 6, iclass 24, count 0 2006.173.10:56:29.50#ibcon#read 6, iclass 24, count 0 2006.173.10:56:29.50#ibcon#end of sib2, iclass 24, count 0 2006.173.10:56:29.50#ibcon#*mode == 0, iclass 24, count 0 2006.173.10:56:29.50#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.10:56:29.50#ibcon#[27=USB\r\n] 2006.173.10:56:29.50#ibcon#*before write, iclass 24, count 0 2006.173.10:56:29.50#ibcon#enter sib2, iclass 24, count 0 2006.173.10:56:29.50#ibcon#flushed, iclass 24, count 0 2006.173.10:56:29.50#ibcon#about to write, iclass 24, count 0 2006.173.10:56:29.50#ibcon#wrote, iclass 24, count 0 2006.173.10:56:29.50#ibcon#about to read 3, iclass 24, count 0 2006.173.10:56:29.53#ibcon#read 3, iclass 24, count 0 2006.173.10:56:29.53#ibcon#about to read 4, iclass 24, count 0 2006.173.10:56:29.53#ibcon#read 4, iclass 24, count 0 2006.173.10:56:29.53#ibcon#about to read 5, iclass 24, count 0 2006.173.10:56:29.53#ibcon#read 5, iclass 24, count 0 2006.173.10:56:29.53#ibcon#about to read 6, iclass 24, count 0 2006.173.10:56:29.53#ibcon#read 6, iclass 24, count 0 2006.173.10:56:29.53#ibcon#end of sib2, iclass 24, count 0 2006.173.10:56:29.53#ibcon#*after write, iclass 24, count 0 2006.173.10:56:29.53#ibcon#*before return 0, iclass 24, count 0 2006.173.10:56:29.53#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.10:56:29.53#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.10:56:29.53#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.10:56:29.53#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.10:56:29.53$vck44/vabw=wide 2006.173.10:56:29.53#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.10:56:29.53#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.10:56:29.53#ibcon#ireg 8 cls_cnt 0 2006.173.10:56:29.53#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.10:56:29.53#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.10:56:29.53#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.10:56:29.53#ibcon#enter wrdev, iclass 26, count 0 2006.173.10:56:29.53#ibcon#first serial, iclass 26, count 0 2006.173.10:56:29.53#ibcon#enter sib2, iclass 26, count 0 2006.173.10:56:29.53#ibcon#flushed, iclass 26, count 0 2006.173.10:56:29.53#ibcon#about to write, iclass 26, count 0 2006.173.10:56:29.53#ibcon#wrote, iclass 26, count 0 2006.173.10:56:29.53#ibcon#about to read 3, iclass 26, count 0 2006.173.10:56:29.55#ibcon#read 3, iclass 26, count 0 2006.173.10:56:29.55#ibcon#about to read 4, iclass 26, count 0 2006.173.10:56:29.55#ibcon#read 4, iclass 26, count 0 2006.173.10:56:29.55#ibcon#about to read 5, iclass 26, count 0 2006.173.10:56:29.55#ibcon#read 5, iclass 26, count 0 2006.173.10:56:29.55#ibcon#about to read 6, iclass 26, count 0 2006.173.10:56:29.55#ibcon#read 6, iclass 26, count 0 2006.173.10:56:29.55#ibcon#end of sib2, iclass 26, count 0 2006.173.10:56:29.55#ibcon#*mode == 0, iclass 26, count 0 2006.173.10:56:29.55#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.10:56:29.55#ibcon#[25=BW32\r\n] 2006.173.10:56:29.55#ibcon#*before write, iclass 26, count 0 2006.173.10:56:29.55#ibcon#enter sib2, iclass 26, count 0 2006.173.10:56:29.55#ibcon#flushed, iclass 26, count 0 2006.173.10:56:29.55#ibcon#about to write, iclass 26, count 0 2006.173.10:56:29.55#ibcon#wrote, iclass 26, count 0 2006.173.10:56:29.55#ibcon#about to read 3, iclass 26, count 0 2006.173.10:56:29.58#ibcon#read 3, iclass 26, count 0 2006.173.10:56:29.58#ibcon#about to read 4, iclass 26, count 0 2006.173.10:56:29.58#ibcon#read 4, iclass 26, count 0 2006.173.10:56:29.58#ibcon#about to read 5, iclass 26, count 0 2006.173.10:56:29.58#ibcon#read 5, iclass 26, count 0 2006.173.10:56:29.58#ibcon#about to read 6, iclass 26, count 0 2006.173.10:56:29.58#ibcon#read 6, iclass 26, count 0 2006.173.10:56:29.58#ibcon#end of sib2, iclass 26, count 0 2006.173.10:56:29.58#ibcon#*after write, iclass 26, count 0 2006.173.10:56:29.58#ibcon#*before return 0, iclass 26, count 0 2006.173.10:56:29.58#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.10:56:29.58#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.10:56:29.58#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.10:56:29.58#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.10:56:29.58$vck44/vbbw=wide 2006.173.10:56:29.58#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.10:56:29.58#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.10:56:29.58#ibcon#ireg 8 cls_cnt 0 2006.173.10:56:29.58#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.10:56:29.65#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.10:56:29.65#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.10:56:29.65#ibcon#enter wrdev, iclass 28, count 0 2006.173.10:56:29.65#ibcon#first serial, iclass 28, count 0 2006.173.10:56:29.65#ibcon#enter sib2, iclass 28, count 0 2006.173.10:56:29.65#ibcon#flushed, iclass 28, count 0 2006.173.10:56:29.65#ibcon#about to write, iclass 28, count 0 2006.173.10:56:29.65#ibcon#wrote, iclass 28, count 0 2006.173.10:56:29.65#ibcon#about to read 3, iclass 28, count 0 2006.173.10:56:29.67#ibcon#read 3, iclass 28, count 0 2006.173.10:56:29.67#ibcon#about to read 4, iclass 28, count 0 2006.173.10:56:29.67#ibcon#read 4, iclass 28, count 0 2006.173.10:56:29.67#ibcon#about to read 5, iclass 28, count 0 2006.173.10:56:29.67#ibcon#read 5, iclass 28, count 0 2006.173.10:56:29.67#ibcon#about to read 6, iclass 28, count 0 2006.173.10:56:29.67#ibcon#read 6, iclass 28, count 0 2006.173.10:56:29.67#ibcon#end of sib2, iclass 28, count 0 2006.173.10:56:29.67#ibcon#*mode == 0, iclass 28, count 0 2006.173.10:56:29.67#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.10:56:29.67#ibcon#[27=BW32\r\n] 2006.173.10:56:29.67#ibcon#*before write, iclass 28, count 0 2006.173.10:56:29.67#ibcon#enter sib2, iclass 28, count 0 2006.173.10:56:29.67#ibcon#flushed, iclass 28, count 0 2006.173.10:56:29.67#ibcon#about to write, iclass 28, count 0 2006.173.10:56:29.67#ibcon#wrote, iclass 28, count 0 2006.173.10:56:29.67#ibcon#about to read 3, iclass 28, count 0 2006.173.10:56:29.70#ibcon#read 3, iclass 28, count 0 2006.173.10:56:29.70#ibcon#about to read 4, iclass 28, count 0 2006.173.10:56:29.70#ibcon#read 4, iclass 28, count 0 2006.173.10:56:29.70#ibcon#about to read 5, iclass 28, count 0 2006.173.10:56:29.70#ibcon#read 5, iclass 28, count 0 2006.173.10:56:29.70#ibcon#about to read 6, iclass 28, count 0 2006.173.10:56:29.70#ibcon#read 6, iclass 28, count 0 2006.173.10:56:29.70#ibcon#end of sib2, iclass 28, count 0 2006.173.10:56:29.70#ibcon#*after write, iclass 28, count 0 2006.173.10:56:29.70#ibcon#*before return 0, iclass 28, count 0 2006.173.10:56:29.70#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.10:56:29.70#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.10:56:29.70#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.10:56:29.70#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.10:56:29.70$setupk4/ifdk4 2006.173.10:56:29.70$ifdk4/lo= 2006.173.10:56:29.70$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.10:56:29.70$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.10:56:29.70$ifdk4/patch= 2006.173.10:56:29.70$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.10:56:29.70$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.10:56:29.70$setupk4/!*+20s 2006.173.10:56:31.39#abcon#<5=/04 0.7 1.8 22.57 921004.0\r\n> 2006.173.10:56:31.41#abcon#{5=INTERFACE CLEAR} 2006.173.10:56:31.47#abcon#[5=S1D000X0/0*\r\n] 2006.173.10:56:41.56#abcon#<5=/04 0.7 1.8 22.57 921004.0\r\n> 2006.173.10:56:41.58#abcon#{5=INTERFACE CLEAR} 2006.173.10:56:41.64#abcon#[5=S1D000X0/0*\r\n] 2006.173.10:56:44.20$setupk4/"tpicd 2006.173.10:56:44.20$setupk4/echo=off 2006.173.10:56:44.20$setupk4/xlog=off 2006.173.10:56:44.20:!2006.173.10:57:58 2006.173.10:57:03.13#trakl#Source acquired 2006.173.10:57:04.13#flagr#flagr/antenna,acquired 2006.173.10:57:58.00:preob 2006.173.10:57:59.13/onsource/TRACKING 2006.173.10:57:59.13:!2006.173.10:58:08 2006.173.10:58:08.00:"tape 2006.173.10:58:08.00:"st=record 2006.173.10:58:08.00:data_valid=on 2006.173.10:58:08.00:midob 2006.173.10:58:08.13/onsource/TRACKING 2006.173.10:58:08.13/wx/22.57,1004.0,92 2006.173.10:58:08.34/cable/+6.5044E-03 2006.173.10:58:09.43/va/01,07,usb,yes,38,41 2006.173.10:58:09.43/va/02,06,usb,yes,38,38 2006.173.10:58:09.43/va/03,05,usb,yes,48,50 2006.173.10:58:09.43/va/04,06,usb,yes,38,40 2006.173.10:58:09.43/va/05,04,usb,yes,30,31 2006.173.10:58:09.43/va/06,03,usb,yes,42,42 2006.173.10:58:09.43/va/07,04,usb,yes,34,35 2006.173.10:58:09.43/va/08,04,usb,yes,29,35 2006.173.10:58:09.66/valo/01,524.99,yes,locked 2006.173.10:58:09.66/valo/02,534.99,yes,locked 2006.173.10:58:09.66/valo/03,564.99,yes,locked 2006.173.10:58:09.66/valo/04,624.99,yes,locked 2006.173.10:58:09.66/valo/05,734.99,yes,locked 2006.173.10:58:09.66/valo/06,814.99,yes,locked 2006.173.10:58:09.66/valo/07,864.99,yes,locked 2006.173.10:58:09.66/valo/08,884.99,yes,locked 2006.173.10:58:10.75/vb/01,04,usb,yes,36,33 2006.173.10:58:10.75/vb/02,04,usb,yes,38,38 2006.173.10:58:10.75/vb/03,04,usb,yes,35,38 2006.173.10:58:10.75/vb/04,04,usb,yes,40,39 2006.173.10:58:10.75/vb/05,04,usb,yes,31,34 2006.173.10:58:10.75/vb/06,04,usb,yes,36,32 2006.173.10:58:10.75/vb/07,04,usb,yes,36,36 2006.173.10:58:10.75/vb/08,04,usb,yes,33,37 2006.173.10:58:10.99/vblo/01,629.99,yes,locked 2006.173.10:58:10.99/vblo/02,634.99,yes,locked 2006.173.10:58:10.99/vblo/03,649.99,yes,locked 2006.173.10:58:10.99/vblo/04,679.99,yes,locked 2006.173.10:58:10.99/vblo/05,709.99,yes,locked 2006.173.10:58:10.99/vblo/06,719.99,yes,locked 2006.173.10:58:10.99/vblo/07,734.99,yes,locked 2006.173.10:58:10.99/vblo/08,744.99,yes,locked 2006.173.10:58:11.14/vabw/8 2006.173.10:58:11.29/vbbw/8 2006.173.10:58:11.38/xfe/off,on,15.2 2006.173.10:58:11.76/ifatt/23,28,28,28 2006.173.10:58:12.08/fmout-gps/S +4.01E-07 2006.173.10:58:12.12:!2006.173.10:59:38 2006.173.10:59:38.00:data_valid=off 2006.173.10:59:38.00:"et 2006.173.10:59:38.00:!+3s 2006.173.10:59:41.01:"tape 2006.173.10:59:41.01:postob 2006.173.10:59:41.18/cable/+6.5032E-03 2006.173.10:59:41.18/wx/22.57,1004.0,92 2006.173.10:59:42.08/fmout-gps/S +4.00E-07 2006.173.10:59:42.08:scan_name=173-1106,jd0606,360 2006.173.10:59:42.08:source=1308+326,131028.66,322043.8,2000.0,cw 2006.173.10:59:42.14#flagr#flagr/antenna,new-source 2006.173.10:59:43.14:checkk5 2006.173.10:59:43.49/chk_autoobs//k5ts1/ autoobs is running! 2006.173.10:59:43.90/chk_autoobs//k5ts2/ autoobs is running! 2006.173.10:59:44.32/chk_autoobs//k5ts3/ autoobs is running! 2006.173.10:59:44.71/chk_autoobs//k5ts4/ autoobs is running! 2006.173.10:59:45.10/chk_obsdata//k5ts1/T1731058??a.dat file size is correct (nominal:360MB, actual:360MB). 2006.173.10:59:45.52/chk_obsdata//k5ts2/T1731058??b.dat file size is correct (nominal:360MB, actual:360MB). 2006.173.10:59:45.93/chk_obsdata//k5ts3/T1731058??c.dat file size is correct (nominal:360MB, actual:360MB). 2006.173.10:59:46.33/chk_obsdata//k5ts4/T1731058??d.dat file size is correct (nominal:360MB, actual:360MB). 2006.173.10:59:47.05/k5log//k5ts1_log_newline 2006.173.10:59:47.78/k5log//k5ts2_log_newline 2006.173.10:59:48.50/k5log//k5ts3_log_newline 2006.173.10:59:49.21/k5log//k5ts4_log_newline 2006.173.10:59:49.23/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.10:59:49.23:setupk4=1 2006.173.10:59:49.23$setupk4/echo=on 2006.173.10:59:49.23$setupk4/pcalon 2006.173.10:59:49.23$pcalon/"no phase cal control is implemented here 2006.173.10:59:49.23$setupk4/"tpicd=stop 2006.173.10:59:49.23$setupk4/"rec=synch_on 2006.173.10:59:49.23$setupk4/"rec_mode=128 2006.173.10:59:49.23$setupk4/!* 2006.173.10:59:49.23$setupk4/recpk4 2006.173.10:59:49.23$recpk4/recpatch= 2006.173.10:59:49.24$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.10:59:49.24$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.10:59:49.24$setupk4/vck44 2006.173.10:59:49.24$vck44/valo=1,524.99 2006.173.10:59:49.24#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.10:59:49.24#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.10:59:49.24#ibcon#ireg 17 cls_cnt 0 2006.173.10:59:49.24#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.10:59:49.24#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.10:59:49.24#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.10:59:49.24#ibcon#enter wrdev, iclass 3, count 0 2006.173.10:59:49.24#ibcon#first serial, iclass 3, count 0 2006.173.10:59:49.24#ibcon#enter sib2, iclass 3, count 0 2006.173.10:59:49.24#ibcon#flushed, iclass 3, count 0 2006.173.10:59:49.24#ibcon#about to write, iclass 3, count 0 2006.173.10:59:49.24#ibcon#wrote, iclass 3, count 0 2006.173.10:59:49.24#ibcon#about to read 3, iclass 3, count 0 2006.173.10:59:49.25#ibcon#read 3, iclass 3, count 0 2006.173.10:59:49.26#ibcon#about to read 4, iclass 3, count 0 2006.173.10:59:49.26#ibcon#read 4, iclass 3, count 0 2006.173.10:59:49.26#ibcon#about to read 5, iclass 3, count 0 2006.173.10:59:49.26#ibcon#read 5, iclass 3, count 0 2006.173.10:59:49.26#ibcon#about to read 6, iclass 3, count 0 2006.173.10:59:49.26#ibcon#read 6, iclass 3, count 0 2006.173.10:59:49.26#ibcon#end of sib2, iclass 3, count 0 2006.173.10:59:49.26#ibcon#*mode == 0, iclass 3, count 0 2006.173.10:59:49.26#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.10:59:49.26#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.10:59:49.26#ibcon#*before write, iclass 3, count 0 2006.173.10:59:49.26#ibcon#enter sib2, iclass 3, count 0 2006.173.10:59:49.26#ibcon#flushed, iclass 3, count 0 2006.173.10:59:49.26#ibcon#about to write, iclass 3, count 0 2006.173.10:59:49.26#ibcon#wrote, iclass 3, count 0 2006.173.10:59:49.26#ibcon#about to read 3, iclass 3, count 0 2006.173.10:59:49.30#ibcon#read 3, iclass 3, count 0 2006.173.10:59:49.31#ibcon#about to read 4, iclass 3, count 0 2006.173.10:59:49.31#ibcon#read 4, iclass 3, count 0 2006.173.10:59:49.31#ibcon#about to read 5, iclass 3, count 0 2006.173.10:59:49.31#ibcon#read 5, iclass 3, count 0 2006.173.10:59:49.31#ibcon#about to read 6, iclass 3, count 0 2006.173.10:59:49.31#ibcon#read 6, iclass 3, count 0 2006.173.10:59:49.31#ibcon#end of sib2, iclass 3, count 0 2006.173.10:59:49.31#ibcon#*after write, iclass 3, count 0 2006.173.10:59:49.31#ibcon#*before return 0, iclass 3, count 0 2006.173.10:59:49.31#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.10:59:49.31#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.10:59:49.31#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.10:59:49.31#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.10:59:49.31$vck44/va=1,7 2006.173.10:59:49.31#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.10:59:49.31#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.10:59:49.31#ibcon#ireg 11 cls_cnt 2 2006.173.10:59:49.31#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.10:59:49.31#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.10:59:49.31#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.10:59:49.31#ibcon#enter wrdev, iclass 5, count 2 2006.173.10:59:49.31#ibcon#first serial, iclass 5, count 2 2006.173.10:59:49.31#ibcon#enter sib2, iclass 5, count 2 2006.173.10:59:49.31#ibcon#flushed, iclass 5, count 2 2006.173.10:59:49.31#ibcon#about to write, iclass 5, count 2 2006.173.10:59:49.31#ibcon#wrote, iclass 5, count 2 2006.173.10:59:49.31#ibcon#about to read 3, iclass 5, count 2 2006.173.10:59:49.32#ibcon#read 3, iclass 5, count 2 2006.173.10:59:49.33#ibcon#about to read 4, iclass 5, count 2 2006.173.10:59:49.33#ibcon#read 4, iclass 5, count 2 2006.173.10:59:49.33#ibcon#about to read 5, iclass 5, count 2 2006.173.10:59:49.33#ibcon#read 5, iclass 5, count 2 2006.173.10:59:49.33#ibcon#about to read 6, iclass 5, count 2 2006.173.10:59:49.33#ibcon#read 6, iclass 5, count 2 2006.173.10:59:49.33#ibcon#end of sib2, iclass 5, count 2 2006.173.10:59:49.33#ibcon#*mode == 0, iclass 5, count 2 2006.173.10:59:49.33#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.10:59:49.33#ibcon#[25=AT01-07\r\n] 2006.173.10:59:49.33#ibcon#*before write, iclass 5, count 2 2006.173.10:59:49.33#ibcon#enter sib2, iclass 5, count 2 2006.173.10:59:49.33#ibcon#flushed, iclass 5, count 2 2006.173.10:59:49.33#ibcon#about to write, iclass 5, count 2 2006.173.10:59:49.33#ibcon#wrote, iclass 5, count 2 2006.173.10:59:49.33#ibcon#about to read 3, iclass 5, count 2 2006.173.10:59:49.35#ibcon#read 3, iclass 5, count 2 2006.173.10:59:49.36#ibcon#about to read 4, iclass 5, count 2 2006.173.10:59:49.36#ibcon#read 4, iclass 5, count 2 2006.173.10:59:49.36#ibcon#about to read 5, iclass 5, count 2 2006.173.10:59:49.36#ibcon#read 5, iclass 5, count 2 2006.173.10:59:49.36#ibcon#about to read 6, iclass 5, count 2 2006.173.10:59:49.36#ibcon#read 6, iclass 5, count 2 2006.173.10:59:49.36#ibcon#end of sib2, iclass 5, count 2 2006.173.10:59:49.36#ibcon#*after write, iclass 5, count 2 2006.173.10:59:49.36#ibcon#*before return 0, iclass 5, count 2 2006.173.10:59:49.36#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.10:59:49.36#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.10:59:49.36#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.10:59:49.36#ibcon#ireg 7 cls_cnt 0 2006.173.10:59:49.36#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.10:59:49.47#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.10:59:49.48#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.10:59:49.48#ibcon#enter wrdev, iclass 5, count 0 2006.173.10:59:49.48#ibcon#first serial, iclass 5, count 0 2006.173.10:59:49.48#ibcon#enter sib2, iclass 5, count 0 2006.173.10:59:49.48#ibcon#flushed, iclass 5, count 0 2006.173.10:59:49.48#ibcon#about to write, iclass 5, count 0 2006.173.10:59:49.48#ibcon#wrote, iclass 5, count 0 2006.173.10:59:49.48#ibcon#about to read 3, iclass 5, count 0 2006.173.10:59:49.50#ibcon#read 3, iclass 5, count 0 2006.173.10:59:49.50#ibcon#about to read 4, iclass 5, count 0 2006.173.10:59:49.50#ibcon#read 4, iclass 5, count 0 2006.173.10:59:49.50#ibcon#about to read 5, iclass 5, count 0 2006.173.10:59:49.50#ibcon#read 5, iclass 5, count 0 2006.173.10:59:49.50#ibcon#about to read 6, iclass 5, count 0 2006.173.10:59:49.50#ibcon#read 6, iclass 5, count 0 2006.173.10:59:49.50#ibcon#end of sib2, iclass 5, count 0 2006.173.10:59:49.50#ibcon#*mode == 0, iclass 5, count 0 2006.173.10:59:49.50#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.10:59:49.50#ibcon#[25=USB\r\n] 2006.173.10:59:49.50#ibcon#*before write, iclass 5, count 0 2006.173.10:59:49.50#ibcon#enter sib2, iclass 5, count 0 2006.173.10:59:49.50#ibcon#flushed, iclass 5, count 0 2006.173.10:59:49.50#ibcon#about to write, iclass 5, count 0 2006.173.10:59:49.50#ibcon#wrote, iclass 5, count 0 2006.173.10:59:49.50#ibcon#about to read 3, iclass 5, count 0 2006.173.10:59:49.52#ibcon#read 3, iclass 5, count 0 2006.173.10:59:49.53#ibcon#about to read 4, iclass 5, count 0 2006.173.10:59:49.53#ibcon#read 4, iclass 5, count 0 2006.173.10:59:49.53#ibcon#about to read 5, iclass 5, count 0 2006.173.10:59:49.53#ibcon#read 5, iclass 5, count 0 2006.173.10:59:49.53#ibcon#about to read 6, iclass 5, count 0 2006.173.10:59:49.53#ibcon#read 6, iclass 5, count 0 2006.173.10:59:49.53#ibcon#end of sib2, iclass 5, count 0 2006.173.10:59:49.53#ibcon#*after write, iclass 5, count 0 2006.173.10:59:49.53#ibcon#*before return 0, iclass 5, count 0 2006.173.10:59:49.53#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.10:59:49.53#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.10:59:49.53#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.10:59:49.53#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.10:59:49.53$vck44/valo=2,534.99 2006.173.10:59:49.53#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.10:59:49.53#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.10:59:49.53#ibcon#ireg 17 cls_cnt 0 2006.173.10:59:49.53#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.10:59:49.53#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.10:59:49.53#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.10:59:49.53#ibcon#enter wrdev, iclass 7, count 0 2006.173.10:59:49.53#ibcon#first serial, iclass 7, count 0 2006.173.10:59:49.53#ibcon#enter sib2, iclass 7, count 0 2006.173.10:59:49.53#ibcon#flushed, iclass 7, count 0 2006.173.10:59:49.53#ibcon#about to write, iclass 7, count 0 2006.173.10:59:49.53#ibcon#wrote, iclass 7, count 0 2006.173.10:59:49.53#ibcon#about to read 3, iclass 7, count 0 2006.173.10:59:49.54#ibcon#read 3, iclass 7, count 0 2006.173.10:59:49.55#ibcon#about to read 4, iclass 7, count 0 2006.173.10:59:49.55#ibcon#read 4, iclass 7, count 0 2006.173.10:59:49.55#ibcon#about to read 5, iclass 7, count 0 2006.173.10:59:49.55#ibcon#read 5, iclass 7, count 0 2006.173.10:59:49.55#ibcon#about to read 6, iclass 7, count 0 2006.173.10:59:49.55#ibcon#read 6, iclass 7, count 0 2006.173.10:59:49.55#ibcon#end of sib2, iclass 7, count 0 2006.173.10:59:49.55#ibcon#*mode == 0, iclass 7, count 0 2006.173.10:59:49.55#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.10:59:49.55#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.10:59:49.55#ibcon#*before write, iclass 7, count 0 2006.173.10:59:49.55#ibcon#enter sib2, iclass 7, count 0 2006.173.10:59:49.55#ibcon#flushed, iclass 7, count 0 2006.173.10:59:49.55#ibcon#about to write, iclass 7, count 0 2006.173.10:59:49.55#ibcon#wrote, iclass 7, count 0 2006.173.10:59:49.55#ibcon#about to read 3, iclass 7, count 0 2006.173.10:59:49.58#ibcon#read 3, iclass 7, count 0 2006.173.10:59:49.59#ibcon#about to read 4, iclass 7, count 0 2006.173.10:59:49.59#ibcon#read 4, iclass 7, count 0 2006.173.10:59:49.59#ibcon#about to read 5, iclass 7, count 0 2006.173.10:59:49.59#ibcon#read 5, iclass 7, count 0 2006.173.10:59:49.59#ibcon#about to read 6, iclass 7, count 0 2006.173.10:59:49.59#ibcon#read 6, iclass 7, count 0 2006.173.10:59:49.59#ibcon#end of sib2, iclass 7, count 0 2006.173.10:59:49.59#ibcon#*after write, iclass 7, count 0 2006.173.10:59:49.59#ibcon#*before return 0, iclass 7, count 0 2006.173.10:59:49.59#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.10:59:49.59#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.10:59:49.59#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.10:59:49.59#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.10:59:49.59$vck44/va=2,6 2006.173.10:59:49.59#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.10:59:49.59#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.10:59:49.59#ibcon#ireg 11 cls_cnt 2 2006.173.10:59:49.59#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.10:59:49.64#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.10:59:49.65#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.10:59:49.65#ibcon#enter wrdev, iclass 11, count 2 2006.173.10:59:49.65#ibcon#first serial, iclass 11, count 2 2006.173.10:59:49.65#ibcon#enter sib2, iclass 11, count 2 2006.173.10:59:49.65#ibcon#flushed, iclass 11, count 2 2006.173.10:59:49.65#ibcon#about to write, iclass 11, count 2 2006.173.10:59:49.65#ibcon#wrote, iclass 11, count 2 2006.173.10:59:49.65#ibcon#about to read 3, iclass 11, count 2 2006.173.10:59:49.66#ibcon#read 3, iclass 11, count 2 2006.173.10:59:49.67#ibcon#about to read 4, iclass 11, count 2 2006.173.10:59:49.67#ibcon#read 4, iclass 11, count 2 2006.173.10:59:49.67#ibcon#about to read 5, iclass 11, count 2 2006.173.10:59:49.67#ibcon#read 5, iclass 11, count 2 2006.173.10:59:49.67#ibcon#about to read 6, iclass 11, count 2 2006.173.10:59:49.67#ibcon#read 6, iclass 11, count 2 2006.173.10:59:49.67#ibcon#end of sib2, iclass 11, count 2 2006.173.10:59:49.67#ibcon#*mode == 0, iclass 11, count 2 2006.173.10:59:49.67#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.10:59:49.67#ibcon#[25=AT02-06\r\n] 2006.173.10:59:49.67#ibcon#*before write, iclass 11, count 2 2006.173.10:59:49.67#ibcon#enter sib2, iclass 11, count 2 2006.173.10:59:49.67#ibcon#flushed, iclass 11, count 2 2006.173.10:59:49.67#ibcon#about to write, iclass 11, count 2 2006.173.10:59:49.67#ibcon#wrote, iclass 11, count 2 2006.173.10:59:49.67#ibcon#about to read 3, iclass 11, count 2 2006.173.10:59:49.69#ibcon#read 3, iclass 11, count 2 2006.173.10:59:49.70#ibcon#about to read 4, iclass 11, count 2 2006.173.10:59:49.70#ibcon#read 4, iclass 11, count 2 2006.173.10:59:49.70#ibcon#about to read 5, iclass 11, count 2 2006.173.10:59:49.70#ibcon#read 5, iclass 11, count 2 2006.173.10:59:49.70#ibcon#about to read 6, iclass 11, count 2 2006.173.10:59:49.70#ibcon#read 6, iclass 11, count 2 2006.173.10:59:49.70#ibcon#end of sib2, iclass 11, count 2 2006.173.10:59:49.70#ibcon#*after write, iclass 11, count 2 2006.173.10:59:49.70#ibcon#*before return 0, iclass 11, count 2 2006.173.10:59:49.70#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.10:59:49.70#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.10:59:49.70#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.10:59:49.70#ibcon#ireg 7 cls_cnt 0 2006.173.10:59:49.70#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.10:59:49.81#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.10:59:49.82#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.10:59:49.82#ibcon#enter wrdev, iclass 11, count 0 2006.173.10:59:49.82#ibcon#first serial, iclass 11, count 0 2006.173.10:59:49.82#ibcon#enter sib2, iclass 11, count 0 2006.173.10:59:49.82#ibcon#flushed, iclass 11, count 0 2006.173.10:59:49.82#ibcon#about to write, iclass 11, count 0 2006.173.10:59:49.82#ibcon#wrote, iclass 11, count 0 2006.173.10:59:49.82#ibcon#about to read 3, iclass 11, count 0 2006.173.10:59:49.83#ibcon#read 3, iclass 11, count 0 2006.173.10:59:49.84#ibcon#about to read 4, iclass 11, count 0 2006.173.10:59:49.84#ibcon#read 4, iclass 11, count 0 2006.173.10:59:49.84#ibcon#about to read 5, iclass 11, count 0 2006.173.10:59:49.84#ibcon#read 5, iclass 11, count 0 2006.173.10:59:49.84#ibcon#about to read 6, iclass 11, count 0 2006.173.10:59:49.84#ibcon#read 6, iclass 11, count 0 2006.173.10:59:49.84#ibcon#end of sib2, iclass 11, count 0 2006.173.10:59:49.84#ibcon#*mode == 0, iclass 11, count 0 2006.173.10:59:49.84#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.10:59:49.84#ibcon#[25=USB\r\n] 2006.173.10:59:49.84#ibcon#*before write, iclass 11, count 0 2006.173.10:59:49.84#ibcon#enter sib2, iclass 11, count 0 2006.173.10:59:49.84#ibcon#flushed, iclass 11, count 0 2006.173.10:59:49.84#ibcon#about to write, iclass 11, count 0 2006.173.10:59:49.84#ibcon#wrote, iclass 11, count 0 2006.173.10:59:49.84#ibcon#about to read 3, iclass 11, count 0 2006.173.10:59:49.86#ibcon#read 3, iclass 11, count 0 2006.173.10:59:49.86#ibcon#about to read 4, iclass 11, count 0 2006.173.10:59:49.87#ibcon#read 4, iclass 11, count 0 2006.173.10:59:49.87#ibcon#about to read 5, iclass 11, count 0 2006.173.10:59:49.87#ibcon#read 5, iclass 11, count 0 2006.173.10:59:49.87#ibcon#about to read 6, iclass 11, count 0 2006.173.10:59:49.87#ibcon#read 6, iclass 11, count 0 2006.173.10:59:49.87#ibcon#end of sib2, iclass 11, count 0 2006.173.10:59:49.87#ibcon#*after write, iclass 11, count 0 2006.173.10:59:49.87#ibcon#*before return 0, iclass 11, count 0 2006.173.10:59:49.87#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.10:59:49.87#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.10:59:49.87#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.10:59:49.87#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.10:59:49.87$vck44/valo=3,564.99 2006.173.10:59:49.87#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.10:59:49.87#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.10:59:49.87#ibcon#ireg 17 cls_cnt 0 2006.173.10:59:49.87#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.10:59:49.87#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.10:59:49.87#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.10:59:49.87#ibcon#enter wrdev, iclass 13, count 0 2006.173.10:59:49.87#ibcon#first serial, iclass 13, count 0 2006.173.10:59:49.87#ibcon#enter sib2, iclass 13, count 0 2006.173.10:59:49.87#ibcon#flushed, iclass 13, count 0 2006.173.10:59:49.87#ibcon#about to write, iclass 13, count 0 2006.173.10:59:49.87#ibcon#wrote, iclass 13, count 0 2006.173.10:59:49.87#ibcon#about to read 3, iclass 13, count 0 2006.173.10:59:49.88#ibcon#read 3, iclass 13, count 0 2006.173.10:59:49.89#ibcon#about to read 4, iclass 13, count 0 2006.173.10:59:49.89#ibcon#read 4, iclass 13, count 0 2006.173.10:59:49.89#ibcon#about to read 5, iclass 13, count 0 2006.173.10:59:49.89#ibcon#read 5, iclass 13, count 0 2006.173.10:59:49.89#ibcon#about to read 6, iclass 13, count 0 2006.173.10:59:49.89#ibcon#read 6, iclass 13, count 0 2006.173.10:59:49.89#ibcon#end of sib2, iclass 13, count 0 2006.173.10:59:49.89#ibcon#*mode == 0, iclass 13, count 0 2006.173.10:59:49.89#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.10:59:49.89#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.10:59:49.89#ibcon#*before write, iclass 13, count 0 2006.173.10:59:49.89#ibcon#enter sib2, iclass 13, count 0 2006.173.10:59:49.89#ibcon#flushed, iclass 13, count 0 2006.173.10:59:49.89#ibcon#about to write, iclass 13, count 0 2006.173.10:59:49.89#ibcon#wrote, iclass 13, count 0 2006.173.10:59:49.89#ibcon#about to read 3, iclass 13, count 0 2006.173.10:59:49.92#ibcon#read 3, iclass 13, count 0 2006.173.10:59:49.93#ibcon#about to read 4, iclass 13, count 0 2006.173.10:59:49.93#ibcon#read 4, iclass 13, count 0 2006.173.10:59:49.93#ibcon#about to read 5, iclass 13, count 0 2006.173.10:59:49.93#ibcon#read 5, iclass 13, count 0 2006.173.10:59:49.93#ibcon#about to read 6, iclass 13, count 0 2006.173.10:59:49.93#ibcon#read 6, iclass 13, count 0 2006.173.10:59:49.93#ibcon#end of sib2, iclass 13, count 0 2006.173.10:59:49.93#ibcon#*after write, iclass 13, count 0 2006.173.10:59:49.93#ibcon#*before return 0, iclass 13, count 0 2006.173.10:59:49.93#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.10:59:49.93#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.10:59:49.93#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.10:59:49.93#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.10:59:49.93$vck44/va=3,5 2006.173.10:59:49.93#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.10:59:49.93#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.10:59:49.93#ibcon#ireg 11 cls_cnt 2 2006.173.10:59:49.93#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.10:59:49.98#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.10:59:49.99#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.10:59:49.99#ibcon#enter wrdev, iclass 15, count 2 2006.173.10:59:49.99#ibcon#first serial, iclass 15, count 2 2006.173.10:59:49.99#ibcon#enter sib2, iclass 15, count 2 2006.173.10:59:49.99#ibcon#flushed, iclass 15, count 2 2006.173.10:59:49.99#ibcon#about to write, iclass 15, count 2 2006.173.10:59:49.99#ibcon#wrote, iclass 15, count 2 2006.173.10:59:49.99#ibcon#about to read 3, iclass 15, count 2 2006.173.10:59:50.00#ibcon#read 3, iclass 15, count 2 2006.173.10:59:50.01#ibcon#about to read 4, iclass 15, count 2 2006.173.10:59:50.01#ibcon#read 4, iclass 15, count 2 2006.173.10:59:50.01#ibcon#about to read 5, iclass 15, count 2 2006.173.10:59:50.01#ibcon#read 5, iclass 15, count 2 2006.173.10:59:50.01#ibcon#about to read 6, iclass 15, count 2 2006.173.10:59:50.01#ibcon#read 6, iclass 15, count 2 2006.173.10:59:50.01#ibcon#end of sib2, iclass 15, count 2 2006.173.10:59:50.01#ibcon#*mode == 0, iclass 15, count 2 2006.173.10:59:50.01#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.10:59:50.01#ibcon#[25=AT03-05\r\n] 2006.173.10:59:50.01#ibcon#*before write, iclass 15, count 2 2006.173.10:59:50.01#ibcon#enter sib2, iclass 15, count 2 2006.173.10:59:50.01#ibcon#flushed, iclass 15, count 2 2006.173.10:59:50.01#ibcon#about to write, iclass 15, count 2 2006.173.10:59:50.01#ibcon#wrote, iclass 15, count 2 2006.173.10:59:50.01#ibcon#about to read 3, iclass 15, count 2 2006.173.10:59:50.03#ibcon#read 3, iclass 15, count 2 2006.173.10:59:50.04#ibcon#about to read 4, iclass 15, count 2 2006.173.10:59:50.04#ibcon#read 4, iclass 15, count 2 2006.173.10:59:50.04#ibcon#about to read 5, iclass 15, count 2 2006.173.10:59:50.04#ibcon#read 5, iclass 15, count 2 2006.173.10:59:50.04#ibcon#about to read 6, iclass 15, count 2 2006.173.10:59:50.04#ibcon#read 6, iclass 15, count 2 2006.173.10:59:50.04#ibcon#end of sib2, iclass 15, count 2 2006.173.10:59:50.04#ibcon#*after write, iclass 15, count 2 2006.173.10:59:50.04#ibcon#*before return 0, iclass 15, count 2 2006.173.10:59:50.04#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.10:59:50.04#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.10:59:50.04#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.10:59:50.04#ibcon#ireg 7 cls_cnt 0 2006.173.10:59:50.04#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.10:59:50.15#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.10:59:50.16#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.10:59:50.16#ibcon#enter wrdev, iclass 15, count 0 2006.173.10:59:50.16#ibcon#first serial, iclass 15, count 0 2006.173.10:59:50.16#ibcon#enter sib2, iclass 15, count 0 2006.173.10:59:50.16#ibcon#flushed, iclass 15, count 0 2006.173.10:59:50.16#ibcon#about to write, iclass 15, count 0 2006.173.10:59:50.16#ibcon#wrote, iclass 15, count 0 2006.173.10:59:50.16#ibcon#about to read 3, iclass 15, count 0 2006.173.10:59:50.18#ibcon#read 3, iclass 15, count 0 2006.173.10:59:50.18#ibcon#about to read 4, iclass 15, count 0 2006.173.10:59:50.18#ibcon#read 4, iclass 15, count 0 2006.173.10:59:50.18#ibcon#about to read 5, iclass 15, count 0 2006.173.10:59:50.18#ibcon#read 5, iclass 15, count 0 2006.173.10:59:50.18#ibcon#about to read 6, iclass 15, count 0 2006.173.10:59:50.18#ibcon#read 6, iclass 15, count 0 2006.173.10:59:50.18#ibcon#end of sib2, iclass 15, count 0 2006.173.10:59:50.18#ibcon#*mode == 0, iclass 15, count 0 2006.173.10:59:50.18#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.10:59:50.18#ibcon#[25=USB\r\n] 2006.173.10:59:50.18#ibcon#*before write, iclass 15, count 0 2006.173.10:59:50.18#ibcon#enter sib2, iclass 15, count 0 2006.173.10:59:50.18#ibcon#flushed, iclass 15, count 0 2006.173.10:59:50.18#ibcon#about to write, iclass 15, count 0 2006.173.10:59:50.18#ibcon#wrote, iclass 15, count 0 2006.173.10:59:50.18#ibcon#about to read 3, iclass 15, count 0 2006.173.10:59:50.20#ibcon#read 3, iclass 15, count 0 2006.173.10:59:50.21#ibcon#about to read 4, iclass 15, count 0 2006.173.10:59:50.21#ibcon#read 4, iclass 15, count 0 2006.173.10:59:50.21#ibcon#about to read 5, iclass 15, count 0 2006.173.10:59:50.21#ibcon#read 5, iclass 15, count 0 2006.173.10:59:50.21#ibcon#about to read 6, iclass 15, count 0 2006.173.10:59:50.21#ibcon#read 6, iclass 15, count 0 2006.173.10:59:50.21#ibcon#end of sib2, iclass 15, count 0 2006.173.10:59:50.21#ibcon#*after write, iclass 15, count 0 2006.173.10:59:50.21#ibcon#*before return 0, iclass 15, count 0 2006.173.10:59:50.21#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.10:59:50.21#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.10:59:50.21#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.10:59:50.21#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.10:59:50.21$vck44/valo=4,624.99 2006.173.10:59:50.21#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.10:59:50.21#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.10:59:50.21#ibcon#ireg 17 cls_cnt 0 2006.173.10:59:50.21#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.10:59:50.21#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.10:59:50.21#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.10:59:50.21#ibcon#enter wrdev, iclass 17, count 0 2006.173.10:59:50.21#ibcon#first serial, iclass 17, count 0 2006.173.10:59:50.21#ibcon#enter sib2, iclass 17, count 0 2006.173.10:59:50.21#ibcon#flushed, iclass 17, count 0 2006.173.10:59:50.21#ibcon#about to write, iclass 17, count 0 2006.173.10:59:50.21#ibcon#wrote, iclass 17, count 0 2006.173.10:59:50.21#ibcon#about to read 3, iclass 17, count 0 2006.173.10:59:50.23#ibcon#read 3, iclass 17, count 0 2006.173.10:59:50.23#ibcon#about to read 4, iclass 17, count 0 2006.173.10:59:50.23#ibcon#read 4, iclass 17, count 0 2006.173.10:59:50.23#ibcon#about to read 5, iclass 17, count 0 2006.173.10:59:50.23#ibcon#read 5, iclass 17, count 0 2006.173.10:59:50.23#ibcon#about to read 6, iclass 17, count 0 2006.173.10:59:50.23#ibcon#read 6, iclass 17, count 0 2006.173.10:59:50.23#ibcon#end of sib2, iclass 17, count 0 2006.173.10:59:50.23#ibcon#*mode == 0, iclass 17, count 0 2006.173.10:59:50.23#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.10:59:50.23#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.10:59:50.23#ibcon#*before write, iclass 17, count 0 2006.173.10:59:50.23#ibcon#enter sib2, iclass 17, count 0 2006.173.10:59:50.23#ibcon#flushed, iclass 17, count 0 2006.173.10:59:50.23#ibcon#about to write, iclass 17, count 0 2006.173.10:59:50.23#ibcon#wrote, iclass 17, count 0 2006.173.10:59:50.23#ibcon#about to read 3, iclass 17, count 0 2006.173.10:59:50.26#ibcon#read 3, iclass 17, count 0 2006.173.10:59:50.27#ibcon#about to read 4, iclass 17, count 0 2006.173.10:59:50.27#ibcon#read 4, iclass 17, count 0 2006.173.10:59:50.27#ibcon#about to read 5, iclass 17, count 0 2006.173.10:59:50.27#ibcon#read 5, iclass 17, count 0 2006.173.10:59:50.27#ibcon#about to read 6, iclass 17, count 0 2006.173.10:59:50.27#ibcon#read 6, iclass 17, count 0 2006.173.10:59:50.27#ibcon#end of sib2, iclass 17, count 0 2006.173.10:59:50.27#ibcon#*after write, iclass 17, count 0 2006.173.10:59:50.27#ibcon#*before return 0, iclass 17, count 0 2006.173.10:59:50.27#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.10:59:50.27#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.10:59:50.27#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.10:59:50.27#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.10:59:50.27$vck44/va=4,6 2006.173.10:59:50.27#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.10:59:50.27#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.10:59:50.27#ibcon#ireg 11 cls_cnt 2 2006.173.10:59:50.27#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.10:59:50.32#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.10:59:50.33#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.10:59:50.33#ibcon#enter wrdev, iclass 19, count 2 2006.173.10:59:50.33#ibcon#first serial, iclass 19, count 2 2006.173.10:59:50.33#ibcon#enter sib2, iclass 19, count 2 2006.173.10:59:50.33#ibcon#flushed, iclass 19, count 2 2006.173.10:59:50.33#ibcon#about to write, iclass 19, count 2 2006.173.10:59:50.33#ibcon#wrote, iclass 19, count 2 2006.173.10:59:50.33#ibcon#about to read 3, iclass 19, count 2 2006.173.10:59:50.34#ibcon#read 3, iclass 19, count 2 2006.173.10:59:50.35#ibcon#about to read 4, iclass 19, count 2 2006.173.10:59:50.35#ibcon#read 4, iclass 19, count 2 2006.173.10:59:50.35#ibcon#about to read 5, iclass 19, count 2 2006.173.10:59:50.35#ibcon#read 5, iclass 19, count 2 2006.173.10:59:50.35#ibcon#about to read 6, iclass 19, count 2 2006.173.10:59:50.35#ibcon#read 6, iclass 19, count 2 2006.173.10:59:50.35#ibcon#end of sib2, iclass 19, count 2 2006.173.10:59:50.35#ibcon#*mode == 0, iclass 19, count 2 2006.173.10:59:50.35#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.10:59:50.35#ibcon#[25=AT04-06\r\n] 2006.173.10:59:50.35#ibcon#*before write, iclass 19, count 2 2006.173.10:59:50.35#ibcon#enter sib2, iclass 19, count 2 2006.173.10:59:50.35#ibcon#flushed, iclass 19, count 2 2006.173.10:59:50.35#ibcon#about to write, iclass 19, count 2 2006.173.10:59:50.35#ibcon#wrote, iclass 19, count 2 2006.173.10:59:50.35#ibcon#about to read 3, iclass 19, count 2 2006.173.10:59:50.37#ibcon#read 3, iclass 19, count 2 2006.173.10:59:50.38#ibcon#about to read 4, iclass 19, count 2 2006.173.10:59:50.38#ibcon#read 4, iclass 19, count 2 2006.173.10:59:50.38#ibcon#about to read 5, iclass 19, count 2 2006.173.10:59:50.38#ibcon#read 5, iclass 19, count 2 2006.173.10:59:50.38#ibcon#about to read 6, iclass 19, count 2 2006.173.10:59:50.38#ibcon#read 6, iclass 19, count 2 2006.173.10:59:50.38#ibcon#end of sib2, iclass 19, count 2 2006.173.10:59:50.38#ibcon#*after write, iclass 19, count 2 2006.173.10:59:50.38#ibcon#*before return 0, iclass 19, count 2 2006.173.10:59:50.38#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.10:59:50.38#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.10:59:50.38#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.10:59:50.38#ibcon#ireg 7 cls_cnt 0 2006.173.10:59:50.38#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.10:59:50.49#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.10:59:50.50#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.10:59:50.50#ibcon#enter wrdev, iclass 19, count 0 2006.173.10:59:50.50#ibcon#first serial, iclass 19, count 0 2006.173.10:59:50.50#ibcon#enter sib2, iclass 19, count 0 2006.173.10:59:50.50#ibcon#flushed, iclass 19, count 0 2006.173.10:59:50.50#ibcon#about to write, iclass 19, count 0 2006.173.10:59:50.50#ibcon#wrote, iclass 19, count 0 2006.173.10:59:50.50#ibcon#about to read 3, iclass 19, count 0 2006.173.10:59:50.51#ibcon#read 3, iclass 19, count 0 2006.173.10:59:50.52#ibcon#about to read 4, iclass 19, count 0 2006.173.10:59:50.52#ibcon#read 4, iclass 19, count 0 2006.173.10:59:50.52#ibcon#about to read 5, iclass 19, count 0 2006.173.10:59:50.52#ibcon#read 5, iclass 19, count 0 2006.173.10:59:50.52#ibcon#about to read 6, iclass 19, count 0 2006.173.10:59:50.52#ibcon#read 6, iclass 19, count 0 2006.173.10:59:50.52#ibcon#end of sib2, iclass 19, count 0 2006.173.10:59:50.52#ibcon#*mode == 0, iclass 19, count 0 2006.173.10:59:50.52#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.10:59:50.52#ibcon#[25=USB\r\n] 2006.173.10:59:50.52#ibcon#*before write, iclass 19, count 0 2006.173.10:59:50.52#ibcon#enter sib2, iclass 19, count 0 2006.173.10:59:50.52#ibcon#flushed, iclass 19, count 0 2006.173.10:59:50.52#ibcon#about to write, iclass 19, count 0 2006.173.10:59:50.52#ibcon#wrote, iclass 19, count 0 2006.173.10:59:50.52#ibcon#about to read 3, iclass 19, count 0 2006.173.10:59:50.54#ibcon#read 3, iclass 19, count 0 2006.173.10:59:50.55#ibcon#about to read 4, iclass 19, count 0 2006.173.10:59:50.55#ibcon#read 4, iclass 19, count 0 2006.173.10:59:50.55#ibcon#about to read 5, iclass 19, count 0 2006.173.10:59:50.55#ibcon#read 5, iclass 19, count 0 2006.173.10:59:50.55#ibcon#about to read 6, iclass 19, count 0 2006.173.10:59:50.55#ibcon#read 6, iclass 19, count 0 2006.173.10:59:50.55#ibcon#end of sib2, iclass 19, count 0 2006.173.10:59:50.55#ibcon#*after write, iclass 19, count 0 2006.173.10:59:50.55#ibcon#*before return 0, iclass 19, count 0 2006.173.10:59:50.55#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.10:59:50.55#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.10:59:50.55#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.10:59:50.55#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.10:59:50.55$vck44/valo=5,734.99 2006.173.10:59:50.55#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.10:59:50.55#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.10:59:50.55#ibcon#ireg 17 cls_cnt 0 2006.173.10:59:50.55#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.10:59:50.55#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.10:59:50.55#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.10:59:50.55#ibcon#enter wrdev, iclass 21, count 0 2006.173.10:59:50.55#ibcon#first serial, iclass 21, count 0 2006.173.10:59:50.55#ibcon#enter sib2, iclass 21, count 0 2006.173.10:59:50.55#ibcon#flushed, iclass 21, count 0 2006.173.10:59:50.55#ibcon#about to write, iclass 21, count 0 2006.173.10:59:50.55#ibcon#wrote, iclass 21, count 0 2006.173.10:59:50.55#ibcon#about to read 3, iclass 21, count 0 2006.173.10:59:50.56#ibcon#read 3, iclass 21, count 0 2006.173.10:59:50.57#ibcon#about to read 4, iclass 21, count 0 2006.173.10:59:50.57#ibcon#read 4, iclass 21, count 0 2006.173.10:59:50.57#ibcon#about to read 5, iclass 21, count 0 2006.173.10:59:50.57#ibcon#read 5, iclass 21, count 0 2006.173.10:59:50.57#ibcon#about to read 6, iclass 21, count 0 2006.173.10:59:50.57#ibcon#read 6, iclass 21, count 0 2006.173.10:59:50.57#ibcon#end of sib2, iclass 21, count 0 2006.173.10:59:50.57#ibcon#*mode == 0, iclass 21, count 0 2006.173.10:59:50.57#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.10:59:50.57#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.10:59:50.57#ibcon#*before write, iclass 21, count 0 2006.173.10:59:50.57#ibcon#enter sib2, iclass 21, count 0 2006.173.10:59:50.57#ibcon#flushed, iclass 21, count 0 2006.173.10:59:50.57#ibcon#about to write, iclass 21, count 0 2006.173.10:59:50.57#ibcon#wrote, iclass 21, count 0 2006.173.10:59:50.57#ibcon#about to read 3, iclass 21, count 0 2006.173.10:59:50.60#ibcon#read 3, iclass 21, count 0 2006.173.10:59:50.61#ibcon#about to read 4, iclass 21, count 0 2006.173.10:59:50.61#ibcon#read 4, iclass 21, count 0 2006.173.10:59:50.61#ibcon#about to read 5, iclass 21, count 0 2006.173.10:59:50.61#ibcon#read 5, iclass 21, count 0 2006.173.10:59:50.61#ibcon#about to read 6, iclass 21, count 0 2006.173.10:59:50.61#ibcon#read 6, iclass 21, count 0 2006.173.10:59:50.61#ibcon#end of sib2, iclass 21, count 0 2006.173.10:59:50.61#ibcon#*after write, iclass 21, count 0 2006.173.10:59:50.61#ibcon#*before return 0, iclass 21, count 0 2006.173.10:59:50.61#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.10:59:50.61#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.10:59:50.61#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.10:59:50.61#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.10:59:50.61$vck44/va=5,4 2006.173.10:59:50.61#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.10:59:50.61#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.10:59:50.61#ibcon#ireg 11 cls_cnt 2 2006.173.10:59:50.61#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.10:59:50.66#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.10:59:50.67#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.10:59:50.67#ibcon#enter wrdev, iclass 23, count 2 2006.173.10:59:50.67#ibcon#first serial, iclass 23, count 2 2006.173.10:59:50.67#ibcon#enter sib2, iclass 23, count 2 2006.173.10:59:50.67#ibcon#flushed, iclass 23, count 2 2006.173.10:59:50.67#ibcon#about to write, iclass 23, count 2 2006.173.10:59:50.67#ibcon#wrote, iclass 23, count 2 2006.173.10:59:50.67#ibcon#about to read 3, iclass 23, count 2 2006.173.10:59:50.68#ibcon#read 3, iclass 23, count 2 2006.173.10:59:50.69#ibcon#about to read 4, iclass 23, count 2 2006.173.10:59:50.69#ibcon#read 4, iclass 23, count 2 2006.173.10:59:50.69#ibcon#about to read 5, iclass 23, count 2 2006.173.10:59:50.69#ibcon#read 5, iclass 23, count 2 2006.173.10:59:50.69#ibcon#about to read 6, iclass 23, count 2 2006.173.10:59:50.69#ibcon#read 6, iclass 23, count 2 2006.173.10:59:50.69#ibcon#end of sib2, iclass 23, count 2 2006.173.10:59:50.69#ibcon#*mode == 0, iclass 23, count 2 2006.173.10:59:50.69#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.10:59:50.69#ibcon#[25=AT05-04\r\n] 2006.173.10:59:50.69#ibcon#*before write, iclass 23, count 2 2006.173.10:59:50.69#ibcon#enter sib2, iclass 23, count 2 2006.173.10:59:50.69#ibcon#flushed, iclass 23, count 2 2006.173.10:59:50.69#ibcon#about to write, iclass 23, count 2 2006.173.10:59:50.69#ibcon#wrote, iclass 23, count 2 2006.173.10:59:50.69#ibcon#about to read 3, iclass 23, count 2 2006.173.10:59:50.71#ibcon#read 3, iclass 23, count 2 2006.173.10:59:50.72#ibcon#about to read 4, iclass 23, count 2 2006.173.10:59:50.72#ibcon#read 4, iclass 23, count 2 2006.173.10:59:50.72#ibcon#about to read 5, iclass 23, count 2 2006.173.10:59:50.72#ibcon#read 5, iclass 23, count 2 2006.173.10:59:50.72#ibcon#about to read 6, iclass 23, count 2 2006.173.10:59:50.72#ibcon#read 6, iclass 23, count 2 2006.173.10:59:50.72#ibcon#end of sib2, iclass 23, count 2 2006.173.10:59:50.72#ibcon#*after write, iclass 23, count 2 2006.173.10:59:50.72#ibcon#*before return 0, iclass 23, count 2 2006.173.10:59:50.72#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.10:59:50.72#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.10:59:50.72#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.10:59:50.72#ibcon#ireg 7 cls_cnt 0 2006.173.10:59:50.72#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.10:59:50.83#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.10:59:50.84#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.10:59:50.84#ibcon#enter wrdev, iclass 23, count 0 2006.173.10:59:50.84#ibcon#first serial, iclass 23, count 0 2006.173.10:59:50.84#ibcon#enter sib2, iclass 23, count 0 2006.173.10:59:50.84#ibcon#flushed, iclass 23, count 0 2006.173.10:59:50.84#ibcon#about to write, iclass 23, count 0 2006.173.10:59:50.84#ibcon#wrote, iclass 23, count 0 2006.173.10:59:50.84#ibcon#about to read 3, iclass 23, count 0 2006.173.10:59:50.85#ibcon#read 3, iclass 23, count 0 2006.173.10:59:50.86#ibcon#about to read 4, iclass 23, count 0 2006.173.10:59:50.86#ibcon#read 4, iclass 23, count 0 2006.173.10:59:50.86#ibcon#about to read 5, iclass 23, count 0 2006.173.10:59:50.86#ibcon#read 5, iclass 23, count 0 2006.173.10:59:50.86#ibcon#about to read 6, iclass 23, count 0 2006.173.10:59:50.86#ibcon#read 6, iclass 23, count 0 2006.173.10:59:50.86#ibcon#end of sib2, iclass 23, count 0 2006.173.10:59:50.86#ibcon#*mode == 0, iclass 23, count 0 2006.173.10:59:50.86#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.10:59:50.86#ibcon#[25=USB\r\n] 2006.173.10:59:50.86#ibcon#*before write, iclass 23, count 0 2006.173.10:59:50.86#ibcon#enter sib2, iclass 23, count 0 2006.173.10:59:50.86#ibcon#flushed, iclass 23, count 0 2006.173.10:59:50.86#ibcon#about to write, iclass 23, count 0 2006.173.10:59:50.86#ibcon#wrote, iclass 23, count 0 2006.173.10:59:50.86#ibcon#about to read 3, iclass 23, count 0 2006.173.10:59:50.88#ibcon#read 3, iclass 23, count 0 2006.173.10:59:50.89#ibcon#about to read 4, iclass 23, count 0 2006.173.10:59:50.89#ibcon#read 4, iclass 23, count 0 2006.173.10:59:50.89#ibcon#about to read 5, iclass 23, count 0 2006.173.10:59:50.89#ibcon#read 5, iclass 23, count 0 2006.173.10:59:50.89#ibcon#about to read 6, iclass 23, count 0 2006.173.10:59:50.89#ibcon#read 6, iclass 23, count 0 2006.173.10:59:50.89#ibcon#end of sib2, iclass 23, count 0 2006.173.10:59:50.89#ibcon#*after write, iclass 23, count 0 2006.173.10:59:50.89#ibcon#*before return 0, iclass 23, count 0 2006.173.10:59:50.89#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.10:59:50.89#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.10:59:50.89#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.10:59:50.89#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.10:59:50.89$vck44/valo=6,814.99 2006.173.10:59:50.89#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.10:59:50.89#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.10:59:50.89#ibcon#ireg 17 cls_cnt 0 2006.173.10:59:50.89#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.10:59:50.89#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.10:59:50.89#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.10:59:50.89#ibcon#enter wrdev, iclass 25, count 0 2006.173.10:59:50.89#ibcon#first serial, iclass 25, count 0 2006.173.10:59:50.89#ibcon#enter sib2, iclass 25, count 0 2006.173.10:59:50.89#ibcon#flushed, iclass 25, count 0 2006.173.10:59:50.89#ibcon#about to write, iclass 25, count 0 2006.173.10:59:50.89#ibcon#wrote, iclass 25, count 0 2006.173.10:59:50.89#ibcon#about to read 3, iclass 25, count 0 2006.173.10:59:50.90#ibcon#read 3, iclass 25, count 0 2006.173.10:59:50.91#ibcon#about to read 4, iclass 25, count 0 2006.173.10:59:50.91#ibcon#read 4, iclass 25, count 0 2006.173.10:59:50.91#ibcon#about to read 5, iclass 25, count 0 2006.173.10:59:50.91#ibcon#read 5, iclass 25, count 0 2006.173.10:59:50.91#ibcon#about to read 6, iclass 25, count 0 2006.173.10:59:50.91#ibcon#read 6, iclass 25, count 0 2006.173.10:59:50.91#ibcon#end of sib2, iclass 25, count 0 2006.173.10:59:50.91#ibcon#*mode == 0, iclass 25, count 0 2006.173.10:59:50.91#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.10:59:50.91#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.10:59:50.91#ibcon#*before write, iclass 25, count 0 2006.173.10:59:50.91#ibcon#enter sib2, iclass 25, count 0 2006.173.10:59:50.91#ibcon#flushed, iclass 25, count 0 2006.173.10:59:50.91#ibcon#about to write, iclass 25, count 0 2006.173.10:59:50.91#ibcon#wrote, iclass 25, count 0 2006.173.10:59:50.91#ibcon#about to read 3, iclass 25, count 0 2006.173.10:59:50.94#ibcon#read 3, iclass 25, count 0 2006.173.10:59:50.95#ibcon#about to read 4, iclass 25, count 0 2006.173.10:59:50.95#ibcon#read 4, iclass 25, count 0 2006.173.10:59:50.95#ibcon#about to read 5, iclass 25, count 0 2006.173.10:59:50.95#ibcon#read 5, iclass 25, count 0 2006.173.10:59:50.95#ibcon#about to read 6, iclass 25, count 0 2006.173.10:59:50.95#ibcon#read 6, iclass 25, count 0 2006.173.10:59:50.95#ibcon#end of sib2, iclass 25, count 0 2006.173.10:59:50.95#ibcon#*after write, iclass 25, count 0 2006.173.10:59:50.95#ibcon#*before return 0, iclass 25, count 0 2006.173.10:59:50.95#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.10:59:50.95#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.10:59:50.95#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.10:59:50.95#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.10:59:50.95$vck44/va=6,3 2006.173.10:59:50.95#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.10:59:50.95#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.10:59:50.95#ibcon#ireg 11 cls_cnt 2 2006.173.10:59:50.95#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.10:59:51.01#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.10:59:51.01#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.10:59:51.01#ibcon#enter wrdev, iclass 27, count 2 2006.173.10:59:51.01#ibcon#first serial, iclass 27, count 2 2006.173.10:59:51.01#ibcon#enter sib2, iclass 27, count 2 2006.173.10:59:51.01#ibcon#flushed, iclass 27, count 2 2006.173.10:59:51.01#ibcon#about to write, iclass 27, count 2 2006.173.10:59:51.01#ibcon#wrote, iclass 27, count 2 2006.173.10:59:51.01#ibcon#about to read 3, iclass 27, count 2 2006.173.10:59:51.02#ibcon#read 3, iclass 27, count 2 2006.173.10:59:51.02#ibcon#about to read 4, iclass 27, count 2 2006.173.10:59:51.03#ibcon#read 4, iclass 27, count 2 2006.173.10:59:51.03#ibcon#about to read 5, iclass 27, count 2 2006.173.10:59:51.03#ibcon#read 5, iclass 27, count 2 2006.173.10:59:51.03#ibcon#about to read 6, iclass 27, count 2 2006.173.10:59:51.03#ibcon#read 6, iclass 27, count 2 2006.173.10:59:51.03#ibcon#end of sib2, iclass 27, count 2 2006.173.10:59:51.03#ibcon#*mode == 0, iclass 27, count 2 2006.173.10:59:51.03#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.10:59:51.03#ibcon#[25=AT06-03\r\n] 2006.173.10:59:51.03#ibcon#*before write, iclass 27, count 2 2006.173.10:59:51.03#ibcon#enter sib2, iclass 27, count 2 2006.173.10:59:51.03#ibcon#flushed, iclass 27, count 2 2006.173.10:59:51.03#ibcon#about to write, iclass 27, count 2 2006.173.10:59:51.03#ibcon#wrote, iclass 27, count 2 2006.173.10:59:51.03#ibcon#about to read 3, iclass 27, count 2 2006.173.10:59:51.05#ibcon#read 3, iclass 27, count 2 2006.173.10:59:51.06#ibcon#about to read 4, iclass 27, count 2 2006.173.10:59:51.06#ibcon#read 4, iclass 27, count 2 2006.173.10:59:51.06#ibcon#about to read 5, iclass 27, count 2 2006.173.10:59:51.06#ibcon#read 5, iclass 27, count 2 2006.173.10:59:51.06#ibcon#about to read 6, iclass 27, count 2 2006.173.10:59:51.06#ibcon#read 6, iclass 27, count 2 2006.173.10:59:51.06#ibcon#end of sib2, iclass 27, count 2 2006.173.10:59:51.06#ibcon#*after write, iclass 27, count 2 2006.173.10:59:51.06#ibcon#*before return 0, iclass 27, count 2 2006.173.10:59:51.06#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.10:59:51.06#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.10:59:51.06#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.10:59:51.06#ibcon#ireg 7 cls_cnt 0 2006.173.10:59:51.06#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.10:59:51.18#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.10:59:51.18#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.10:59:51.18#ibcon#enter wrdev, iclass 27, count 0 2006.173.10:59:51.18#ibcon#first serial, iclass 27, count 0 2006.173.10:59:51.18#ibcon#enter sib2, iclass 27, count 0 2006.173.10:59:51.18#ibcon#flushed, iclass 27, count 0 2006.173.10:59:51.18#ibcon#about to write, iclass 27, count 0 2006.173.10:59:51.18#ibcon#wrote, iclass 27, count 0 2006.173.10:59:51.18#ibcon#about to read 3, iclass 27, count 0 2006.173.10:59:51.19#ibcon#read 3, iclass 27, count 0 2006.173.10:59:51.20#ibcon#about to read 4, iclass 27, count 0 2006.173.10:59:51.20#ibcon#read 4, iclass 27, count 0 2006.173.10:59:51.20#ibcon#about to read 5, iclass 27, count 0 2006.173.10:59:51.20#ibcon#read 5, iclass 27, count 0 2006.173.10:59:51.20#ibcon#about to read 6, iclass 27, count 0 2006.173.10:59:51.20#ibcon#read 6, iclass 27, count 0 2006.173.10:59:51.20#ibcon#end of sib2, iclass 27, count 0 2006.173.10:59:51.20#ibcon#*mode == 0, iclass 27, count 0 2006.173.10:59:51.20#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.10:59:51.20#ibcon#[25=USB\r\n] 2006.173.10:59:51.20#ibcon#*before write, iclass 27, count 0 2006.173.10:59:51.20#ibcon#enter sib2, iclass 27, count 0 2006.173.10:59:51.20#ibcon#flushed, iclass 27, count 0 2006.173.10:59:51.20#ibcon#about to write, iclass 27, count 0 2006.173.10:59:51.20#ibcon#wrote, iclass 27, count 0 2006.173.10:59:51.20#ibcon#about to read 3, iclass 27, count 0 2006.173.10:59:51.22#ibcon#read 3, iclass 27, count 0 2006.173.10:59:51.22#ibcon#about to read 4, iclass 27, count 0 2006.173.10:59:51.23#ibcon#read 4, iclass 27, count 0 2006.173.10:59:51.23#ibcon#about to read 5, iclass 27, count 0 2006.173.10:59:51.23#ibcon#read 5, iclass 27, count 0 2006.173.10:59:51.23#ibcon#about to read 6, iclass 27, count 0 2006.173.10:59:51.23#ibcon#read 6, iclass 27, count 0 2006.173.10:59:51.23#ibcon#end of sib2, iclass 27, count 0 2006.173.10:59:51.23#ibcon#*after write, iclass 27, count 0 2006.173.10:59:51.23#ibcon#*before return 0, iclass 27, count 0 2006.173.10:59:51.23#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.10:59:51.23#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.10:59:51.23#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.10:59:51.23#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.10:59:51.23$vck44/valo=7,864.99 2006.173.10:59:51.23#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.10:59:51.23#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.10:59:51.23#ibcon#ireg 17 cls_cnt 0 2006.173.10:59:51.23#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.10:59:51.23#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.10:59:51.23#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.10:59:51.23#ibcon#enter wrdev, iclass 29, count 0 2006.173.10:59:51.23#ibcon#first serial, iclass 29, count 0 2006.173.10:59:51.23#ibcon#enter sib2, iclass 29, count 0 2006.173.10:59:51.23#ibcon#flushed, iclass 29, count 0 2006.173.10:59:51.23#ibcon#about to write, iclass 29, count 0 2006.173.10:59:51.23#ibcon#wrote, iclass 29, count 0 2006.173.10:59:51.23#ibcon#about to read 3, iclass 29, count 0 2006.173.10:59:51.24#ibcon#read 3, iclass 29, count 0 2006.173.10:59:51.25#ibcon#about to read 4, iclass 29, count 0 2006.173.10:59:51.25#ibcon#read 4, iclass 29, count 0 2006.173.10:59:51.25#ibcon#about to read 5, iclass 29, count 0 2006.173.10:59:51.25#ibcon#read 5, iclass 29, count 0 2006.173.10:59:51.25#ibcon#about to read 6, iclass 29, count 0 2006.173.10:59:51.25#ibcon#read 6, iclass 29, count 0 2006.173.10:59:51.25#ibcon#end of sib2, iclass 29, count 0 2006.173.10:59:51.25#ibcon#*mode == 0, iclass 29, count 0 2006.173.10:59:51.25#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.10:59:51.25#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.10:59:51.25#ibcon#*before write, iclass 29, count 0 2006.173.10:59:51.25#ibcon#enter sib2, iclass 29, count 0 2006.173.10:59:51.25#ibcon#flushed, iclass 29, count 0 2006.173.10:59:51.25#ibcon#about to write, iclass 29, count 0 2006.173.10:59:51.25#ibcon#wrote, iclass 29, count 0 2006.173.10:59:51.25#ibcon#about to read 3, iclass 29, count 0 2006.173.10:59:51.28#ibcon#read 3, iclass 29, count 0 2006.173.10:59:51.28#ibcon#about to read 4, iclass 29, count 0 2006.173.10:59:51.28#ibcon#read 4, iclass 29, count 0 2006.173.10:59:51.29#ibcon#about to read 5, iclass 29, count 0 2006.173.10:59:51.29#ibcon#read 5, iclass 29, count 0 2006.173.10:59:51.29#ibcon#about to read 6, iclass 29, count 0 2006.173.10:59:51.29#ibcon#read 6, iclass 29, count 0 2006.173.10:59:51.29#ibcon#end of sib2, iclass 29, count 0 2006.173.10:59:51.29#ibcon#*after write, iclass 29, count 0 2006.173.10:59:51.29#ibcon#*before return 0, iclass 29, count 0 2006.173.10:59:51.29#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.10:59:51.29#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.10:59:51.29#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.10:59:51.29#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.10:59:51.29$vck44/va=7,4 2006.173.10:59:51.29#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.10:59:51.29#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.10:59:51.29#ibcon#ireg 11 cls_cnt 2 2006.173.10:59:51.29#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.10:59:51.35#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.10:59:51.35#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.10:59:51.35#ibcon#enter wrdev, iclass 31, count 2 2006.173.10:59:51.35#ibcon#first serial, iclass 31, count 2 2006.173.10:59:51.35#ibcon#enter sib2, iclass 31, count 2 2006.173.10:59:51.35#ibcon#flushed, iclass 31, count 2 2006.173.10:59:51.35#ibcon#about to write, iclass 31, count 2 2006.173.10:59:51.35#ibcon#wrote, iclass 31, count 2 2006.173.10:59:51.35#ibcon#about to read 3, iclass 31, count 2 2006.173.10:59:51.36#ibcon#read 3, iclass 31, count 2 2006.173.10:59:51.36#ibcon#about to read 4, iclass 31, count 2 2006.173.10:59:51.37#ibcon#read 4, iclass 31, count 2 2006.173.10:59:51.37#ibcon#about to read 5, iclass 31, count 2 2006.173.10:59:51.37#ibcon#read 5, iclass 31, count 2 2006.173.10:59:51.37#ibcon#about to read 6, iclass 31, count 2 2006.173.10:59:51.37#ibcon#read 6, iclass 31, count 2 2006.173.10:59:51.37#ibcon#end of sib2, iclass 31, count 2 2006.173.10:59:51.37#ibcon#*mode == 0, iclass 31, count 2 2006.173.10:59:51.37#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.10:59:51.37#ibcon#[25=AT07-04\r\n] 2006.173.10:59:51.37#ibcon#*before write, iclass 31, count 2 2006.173.10:59:51.37#ibcon#enter sib2, iclass 31, count 2 2006.173.10:59:51.37#ibcon#flushed, iclass 31, count 2 2006.173.10:59:51.37#ibcon#about to write, iclass 31, count 2 2006.173.10:59:51.37#ibcon#wrote, iclass 31, count 2 2006.173.10:59:51.37#ibcon#about to read 3, iclass 31, count 2 2006.173.10:59:51.39#ibcon#read 3, iclass 31, count 2 2006.173.10:59:51.40#ibcon#about to read 4, iclass 31, count 2 2006.173.10:59:51.40#ibcon#read 4, iclass 31, count 2 2006.173.10:59:51.40#ibcon#about to read 5, iclass 31, count 2 2006.173.10:59:51.40#ibcon#read 5, iclass 31, count 2 2006.173.10:59:51.40#ibcon#about to read 6, iclass 31, count 2 2006.173.10:59:51.40#ibcon#read 6, iclass 31, count 2 2006.173.10:59:51.40#ibcon#end of sib2, iclass 31, count 2 2006.173.10:59:51.40#ibcon#*after write, iclass 31, count 2 2006.173.10:59:51.40#ibcon#*before return 0, iclass 31, count 2 2006.173.10:59:51.40#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.10:59:51.40#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.10:59:51.40#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.10:59:51.40#ibcon#ireg 7 cls_cnt 0 2006.173.10:59:51.40#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.10:59:51.51#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.10:59:51.52#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.10:59:51.52#ibcon#enter wrdev, iclass 31, count 0 2006.173.10:59:51.52#ibcon#first serial, iclass 31, count 0 2006.173.10:59:51.52#ibcon#enter sib2, iclass 31, count 0 2006.173.10:59:51.52#ibcon#flushed, iclass 31, count 0 2006.173.10:59:51.52#ibcon#about to write, iclass 31, count 0 2006.173.10:59:51.52#ibcon#wrote, iclass 31, count 0 2006.173.10:59:51.52#ibcon#about to read 3, iclass 31, count 0 2006.173.10:59:51.53#ibcon#read 3, iclass 31, count 0 2006.173.10:59:51.54#ibcon#about to read 4, iclass 31, count 0 2006.173.10:59:51.54#ibcon#read 4, iclass 31, count 0 2006.173.10:59:51.54#ibcon#about to read 5, iclass 31, count 0 2006.173.10:59:51.54#ibcon#read 5, iclass 31, count 0 2006.173.10:59:51.54#ibcon#about to read 6, iclass 31, count 0 2006.173.10:59:51.54#ibcon#read 6, iclass 31, count 0 2006.173.10:59:51.54#ibcon#end of sib2, iclass 31, count 0 2006.173.10:59:51.54#ibcon#*mode == 0, iclass 31, count 0 2006.173.10:59:51.54#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.10:59:51.54#ibcon#[25=USB\r\n] 2006.173.10:59:51.54#ibcon#*before write, iclass 31, count 0 2006.173.10:59:51.54#ibcon#enter sib2, iclass 31, count 0 2006.173.10:59:51.54#ibcon#flushed, iclass 31, count 0 2006.173.10:59:51.54#ibcon#about to write, iclass 31, count 0 2006.173.10:59:51.54#ibcon#wrote, iclass 31, count 0 2006.173.10:59:51.54#ibcon#about to read 3, iclass 31, count 0 2006.173.10:59:51.56#ibcon#read 3, iclass 31, count 0 2006.173.10:59:51.57#ibcon#about to read 4, iclass 31, count 0 2006.173.10:59:51.57#ibcon#read 4, iclass 31, count 0 2006.173.10:59:51.57#ibcon#about to read 5, iclass 31, count 0 2006.173.10:59:51.57#ibcon#read 5, iclass 31, count 0 2006.173.10:59:51.57#ibcon#about to read 6, iclass 31, count 0 2006.173.10:59:51.57#ibcon#read 6, iclass 31, count 0 2006.173.10:59:51.57#ibcon#end of sib2, iclass 31, count 0 2006.173.10:59:51.57#ibcon#*after write, iclass 31, count 0 2006.173.10:59:51.57#ibcon#*before return 0, iclass 31, count 0 2006.173.10:59:51.57#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.10:59:51.57#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.10:59:51.57#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.10:59:51.57#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.10:59:51.57$vck44/valo=8,884.99 2006.173.10:59:51.57#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.10:59:51.57#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.10:59:51.57#ibcon#ireg 17 cls_cnt 0 2006.173.10:59:51.57#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.10:59:51.57#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.10:59:51.57#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.10:59:51.57#ibcon#enter wrdev, iclass 33, count 0 2006.173.10:59:51.57#ibcon#first serial, iclass 33, count 0 2006.173.10:59:51.57#ibcon#enter sib2, iclass 33, count 0 2006.173.10:59:51.57#ibcon#flushed, iclass 33, count 0 2006.173.10:59:51.57#ibcon#about to write, iclass 33, count 0 2006.173.10:59:51.57#ibcon#wrote, iclass 33, count 0 2006.173.10:59:51.57#ibcon#about to read 3, iclass 33, count 0 2006.173.10:59:51.58#ibcon#read 3, iclass 33, count 0 2006.173.10:59:51.59#ibcon#about to read 4, iclass 33, count 0 2006.173.10:59:51.59#ibcon#read 4, iclass 33, count 0 2006.173.10:59:51.59#ibcon#about to read 5, iclass 33, count 0 2006.173.10:59:51.59#ibcon#read 5, iclass 33, count 0 2006.173.10:59:51.59#ibcon#about to read 6, iclass 33, count 0 2006.173.10:59:51.59#ibcon#read 6, iclass 33, count 0 2006.173.10:59:51.59#ibcon#end of sib2, iclass 33, count 0 2006.173.10:59:51.59#ibcon#*mode == 0, iclass 33, count 0 2006.173.10:59:51.59#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.10:59:51.59#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.10:59:51.59#ibcon#*before write, iclass 33, count 0 2006.173.10:59:51.59#ibcon#enter sib2, iclass 33, count 0 2006.173.10:59:51.59#ibcon#flushed, iclass 33, count 0 2006.173.10:59:51.59#ibcon#about to write, iclass 33, count 0 2006.173.10:59:51.59#ibcon#wrote, iclass 33, count 0 2006.173.10:59:51.59#ibcon#about to read 3, iclass 33, count 0 2006.173.10:59:51.62#ibcon#read 3, iclass 33, count 0 2006.173.10:59:51.63#ibcon#about to read 4, iclass 33, count 0 2006.173.10:59:51.63#ibcon#read 4, iclass 33, count 0 2006.173.10:59:51.63#ibcon#about to read 5, iclass 33, count 0 2006.173.10:59:51.63#ibcon#read 5, iclass 33, count 0 2006.173.10:59:51.63#ibcon#about to read 6, iclass 33, count 0 2006.173.10:59:51.63#ibcon#read 6, iclass 33, count 0 2006.173.10:59:51.63#ibcon#end of sib2, iclass 33, count 0 2006.173.10:59:51.63#ibcon#*after write, iclass 33, count 0 2006.173.10:59:51.63#ibcon#*before return 0, iclass 33, count 0 2006.173.10:59:51.63#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.10:59:51.63#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.10:59:51.63#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.10:59:51.63#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.10:59:51.63$vck44/va=8,4 2006.173.10:59:51.63#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.10:59:51.63#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.10:59:51.63#ibcon#ireg 11 cls_cnt 2 2006.173.10:59:51.63#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.10:59:51.68#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.10:59:51.69#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.10:59:51.69#ibcon#enter wrdev, iclass 35, count 2 2006.173.10:59:51.69#ibcon#first serial, iclass 35, count 2 2006.173.10:59:51.69#ibcon#enter sib2, iclass 35, count 2 2006.173.10:59:51.69#ibcon#flushed, iclass 35, count 2 2006.173.10:59:51.69#ibcon#about to write, iclass 35, count 2 2006.173.10:59:51.69#ibcon#wrote, iclass 35, count 2 2006.173.10:59:51.69#ibcon#about to read 3, iclass 35, count 2 2006.173.10:59:51.70#ibcon#read 3, iclass 35, count 2 2006.173.10:59:51.71#ibcon#about to read 4, iclass 35, count 2 2006.173.10:59:51.71#ibcon#read 4, iclass 35, count 2 2006.173.10:59:51.71#ibcon#about to read 5, iclass 35, count 2 2006.173.10:59:51.71#ibcon#read 5, iclass 35, count 2 2006.173.10:59:51.71#ibcon#about to read 6, iclass 35, count 2 2006.173.10:59:51.71#ibcon#read 6, iclass 35, count 2 2006.173.10:59:51.71#ibcon#end of sib2, iclass 35, count 2 2006.173.10:59:51.71#ibcon#*mode == 0, iclass 35, count 2 2006.173.10:59:51.71#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.10:59:51.71#ibcon#[25=AT08-04\r\n] 2006.173.10:59:51.71#ibcon#*before write, iclass 35, count 2 2006.173.10:59:51.71#ibcon#enter sib2, iclass 35, count 2 2006.173.10:59:51.71#ibcon#flushed, iclass 35, count 2 2006.173.10:59:51.71#ibcon#about to write, iclass 35, count 2 2006.173.10:59:51.71#ibcon#wrote, iclass 35, count 2 2006.173.10:59:51.71#ibcon#about to read 3, iclass 35, count 2 2006.173.10:59:51.73#ibcon#read 3, iclass 35, count 2 2006.173.10:59:51.74#ibcon#about to read 4, iclass 35, count 2 2006.173.10:59:51.74#ibcon#read 4, iclass 35, count 2 2006.173.10:59:51.74#ibcon#about to read 5, iclass 35, count 2 2006.173.10:59:51.74#ibcon#read 5, iclass 35, count 2 2006.173.10:59:51.74#ibcon#about to read 6, iclass 35, count 2 2006.173.10:59:51.74#ibcon#read 6, iclass 35, count 2 2006.173.10:59:51.74#ibcon#end of sib2, iclass 35, count 2 2006.173.10:59:51.74#ibcon#*after write, iclass 35, count 2 2006.173.10:59:51.74#ibcon#*before return 0, iclass 35, count 2 2006.173.10:59:51.74#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.10:59:51.74#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.10:59:51.74#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.10:59:51.74#ibcon#ireg 7 cls_cnt 0 2006.173.10:59:51.74#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.10:59:51.85#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.10:59:51.86#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.10:59:51.86#ibcon#enter wrdev, iclass 35, count 0 2006.173.10:59:51.86#ibcon#first serial, iclass 35, count 0 2006.173.10:59:51.86#ibcon#enter sib2, iclass 35, count 0 2006.173.10:59:51.86#ibcon#flushed, iclass 35, count 0 2006.173.10:59:51.86#ibcon#about to write, iclass 35, count 0 2006.173.10:59:51.86#ibcon#wrote, iclass 35, count 0 2006.173.10:59:51.86#ibcon#about to read 3, iclass 35, count 0 2006.173.10:59:51.87#ibcon#read 3, iclass 35, count 0 2006.173.10:59:51.88#ibcon#about to read 4, iclass 35, count 0 2006.173.10:59:51.88#ibcon#read 4, iclass 35, count 0 2006.173.10:59:51.88#ibcon#about to read 5, iclass 35, count 0 2006.173.10:59:51.88#ibcon#read 5, iclass 35, count 0 2006.173.10:59:51.88#ibcon#about to read 6, iclass 35, count 0 2006.173.10:59:51.88#ibcon#read 6, iclass 35, count 0 2006.173.10:59:51.88#ibcon#end of sib2, iclass 35, count 0 2006.173.10:59:51.88#ibcon#*mode == 0, iclass 35, count 0 2006.173.10:59:51.88#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.10:59:51.88#ibcon#[25=USB\r\n] 2006.173.10:59:51.88#ibcon#*before write, iclass 35, count 0 2006.173.10:59:51.88#ibcon#enter sib2, iclass 35, count 0 2006.173.10:59:51.88#ibcon#flushed, iclass 35, count 0 2006.173.10:59:51.88#ibcon#about to write, iclass 35, count 0 2006.173.10:59:51.88#ibcon#wrote, iclass 35, count 0 2006.173.10:59:51.88#ibcon#about to read 3, iclass 35, count 0 2006.173.10:59:51.90#ibcon#read 3, iclass 35, count 0 2006.173.10:59:51.91#ibcon#about to read 4, iclass 35, count 0 2006.173.10:59:51.91#ibcon#read 4, iclass 35, count 0 2006.173.10:59:51.91#ibcon#about to read 5, iclass 35, count 0 2006.173.10:59:51.91#ibcon#read 5, iclass 35, count 0 2006.173.10:59:51.91#ibcon#about to read 6, iclass 35, count 0 2006.173.10:59:51.91#ibcon#read 6, iclass 35, count 0 2006.173.10:59:51.91#ibcon#end of sib2, iclass 35, count 0 2006.173.10:59:51.91#ibcon#*after write, iclass 35, count 0 2006.173.10:59:51.91#ibcon#*before return 0, iclass 35, count 0 2006.173.10:59:51.91#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.10:59:51.91#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.10:59:51.91#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.10:59:51.91#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.10:59:51.91$vck44/vblo=1,629.99 2006.173.10:59:51.91#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.10:59:51.91#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.10:59:51.91#ibcon#ireg 17 cls_cnt 0 2006.173.10:59:51.91#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.10:59:51.91#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.10:59:51.91#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.10:59:51.91#ibcon#enter wrdev, iclass 37, count 0 2006.173.10:59:51.91#ibcon#first serial, iclass 37, count 0 2006.173.10:59:51.91#ibcon#enter sib2, iclass 37, count 0 2006.173.10:59:51.91#ibcon#flushed, iclass 37, count 0 2006.173.10:59:51.91#ibcon#about to write, iclass 37, count 0 2006.173.10:59:51.91#ibcon#wrote, iclass 37, count 0 2006.173.10:59:51.91#ibcon#about to read 3, iclass 37, count 0 2006.173.10:59:51.92#ibcon#read 3, iclass 37, count 0 2006.173.10:59:51.93#ibcon#about to read 4, iclass 37, count 0 2006.173.10:59:51.93#ibcon#read 4, iclass 37, count 0 2006.173.10:59:51.93#ibcon#about to read 5, iclass 37, count 0 2006.173.10:59:51.93#ibcon#read 5, iclass 37, count 0 2006.173.10:59:51.93#ibcon#about to read 6, iclass 37, count 0 2006.173.10:59:51.93#ibcon#read 6, iclass 37, count 0 2006.173.10:59:51.93#ibcon#end of sib2, iclass 37, count 0 2006.173.10:59:51.93#ibcon#*mode == 0, iclass 37, count 0 2006.173.10:59:51.93#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.10:59:51.93#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.10:59:51.93#ibcon#*before write, iclass 37, count 0 2006.173.10:59:51.93#ibcon#enter sib2, iclass 37, count 0 2006.173.10:59:51.93#ibcon#flushed, iclass 37, count 0 2006.173.10:59:51.93#ibcon#about to write, iclass 37, count 0 2006.173.10:59:51.93#ibcon#wrote, iclass 37, count 0 2006.173.10:59:51.93#ibcon#about to read 3, iclass 37, count 0 2006.173.10:59:51.96#ibcon#read 3, iclass 37, count 0 2006.173.10:59:51.97#ibcon#about to read 4, iclass 37, count 0 2006.173.10:59:51.97#ibcon#read 4, iclass 37, count 0 2006.173.10:59:51.97#ibcon#about to read 5, iclass 37, count 0 2006.173.10:59:51.97#ibcon#read 5, iclass 37, count 0 2006.173.10:59:51.97#ibcon#about to read 6, iclass 37, count 0 2006.173.10:59:51.97#ibcon#read 6, iclass 37, count 0 2006.173.10:59:51.97#ibcon#end of sib2, iclass 37, count 0 2006.173.10:59:51.97#ibcon#*after write, iclass 37, count 0 2006.173.10:59:51.97#ibcon#*before return 0, iclass 37, count 0 2006.173.10:59:51.97#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.10:59:51.97#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.10:59:51.97#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.10:59:51.97#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.10:59:51.97$vck44/vb=1,4 2006.173.10:59:51.97#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.10:59:51.97#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.10:59:51.97#ibcon#ireg 11 cls_cnt 2 2006.173.10:59:51.97#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.10:59:51.97#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.10:59:51.97#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.10:59:51.97#ibcon#enter wrdev, iclass 39, count 2 2006.173.10:59:51.97#ibcon#first serial, iclass 39, count 2 2006.173.10:59:51.97#ibcon#enter sib2, iclass 39, count 2 2006.173.10:59:51.97#ibcon#flushed, iclass 39, count 2 2006.173.10:59:51.97#ibcon#about to write, iclass 39, count 2 2006.173.10:59:51.97#ibcon#wrote, iclass 39, count 2 2006.173.10:59:51.97#ibcon#about to read 3, iclass 39, count 2 2006.173.10:59:51.98#ibcon#read 3, iclass 39, count 2 2006.173.10:59:51.98#ibcon#about to read 4, iclass 39, count 2 2006.173.10:59:51.99#ibcon#read 4, iclass 39, count 2 2006.173.10:59:51.99#ibcon#about to read 5, iclass 39, count 2 2006.173.10:59:51.99#ibcon#read 5, iclass 39, count 2 2006.173.10:59:51.99#ibcon#about to read 6, iclass 39, count 2 2006.173.10:59:51.99#ibcon#read 6, iclass 39, count 2 2006.173.10:59:51.99#ibcon#end of sib2, iclass 39, count 2 2006.173.10:59:51.99#ibcon#*mode == 0, iclass 39, count 2 2006.173.10:59:51.99#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.10:59:51.99#ibcon#[27=AT01-04\r\n] 2006.173.10:59:51.99#ibcon#*before write, iclass 39, count 2 2006.173.10:59:51.99#ibcon#enter sib2, iclass 39, count 2 2006.173.10:59:51.99#ibcon#flushed, iclass 39, count 2 2006.173.10:59:51.99#ibcon#about to write, iclass 39, count 2 2006.173.10:59:51.99#ibcon#wrote, iclass 39, count 2 2006.173.10:59:51.99#ibcon#about to read 3, iclass 39, count 2 2006.173.10:59:52.01#ibcon#read 3, iclass 39, count 2 2006.173.10:59:52.02#ibcon#about to read 4, iclass 39, count 2 2006.173.10:59:52.02#ibcon#read 4, iclass 39, count 2 2006.173.10:59:52.02#ibcon#about to read 5, iclass 39, count 2 2006.173.10:59:52.02#ibcon#read 5, iclass 39, count 2 2006.173.10:59:52.02#ibcon#about to read 6, iclass 39, count 2 2006.173.10:59:52.02#ibcon#read 6, iclass 39, count 2 2006.173.10:59:52.02#ibcon#end of sib2, iclass 39, count 2 2006.173.10:59:52.02#ibcon#*after write, iclass 39, count 2 2006.173.10:59:52.02#ibcon#*before return 0, iclass 39, count 2 2006.173.10:59:52.02#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.10:59:52.02#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.10:59:52.02#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.10:59:52.02#ibcon#ireg 7 cls_cnt 0 2006.173.10:59:52.02#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.10:59:52.14#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.10:59:52.14#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.10:59:52.14#ibcon#enter wrdev, iclass 39, count 0 2006.173.10:59:52.14#ibcon#first serial, iclass 39, count 0 2006.173.10:59:52.14#ibcon#enter sib2, iclass 39, count 0 2006.173.10:59:52.14#ibcon#flushed, iclass 39, count 0 2006.173.10:59:52.14#ibcon#about to write, iclass 39, count 0 2006.173.10:59:52.14#ibcon#wrote, iclass 39, count 0 2006.173.10:59:52.14#ibcon#about to read 3, iclass 39, count 0 2006.173.10:59:52.15#ibcon#read 3, iclass 39, count 0 2006.173.10:59:52.16#ibcon#about to read 4, iclass 39, count 0 2006.173.10:59:52.16#ibcon#read 4, iclass 39, count 0 2006.173.10:59:52.16#ibcon#about to read 5, iclass 39, count 0 2006.173.10:59:52.16#ibcon#read 5, iclass 39, count 0 2006.173.10:59:52.16#ibcon#about to read 6, iclass 39, count 0 2006.173.10:59:52.16#ibcon#read 6, iclass 39, count 0 2006.173.10:59:52.16#ibcon#end of sib2, iclass 39, count 0 2006.173.10:59:52.16#ibcon#*mode == 0, iclass 39, count 0 2006.173.10:59:52.16#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.10:59:52.16#ibcon#[27=USB\r\n] 2006.173.10:59:52.16#ibcon#*before write, iclass 39, count 0 2006.173.10:59:52.16#ibcon#enter sib2, iclass 39, count 0 2006.173.10:59:52.16#ibcon#flushed, iclass 39, count 0 2006.173.10:59:52.16#ibcon#about to write, iclass 39, count 0 2006.173.10:59:52.16#ibcon#wrote, iclass 39, count 0 2006.173.10:59:52.16#ibcon#about to read 3, iclass 39, count 0 2006.173.10:59:52.18#ibcon#read 3, iclass 39, count 0 2006.173.10:59:52.19#ibcon#about to read 4, iclass 39, count 0 2006.173.10:59:52.19#ibcon#read 4, iclass 39, count 0 2006.173.10:59:52.19#ibcon#about to read 5, iclass 39, count 0 2006.173.10:59:52.19#ibcon#read 5, iclass 39, count 0 2006.173.10:59:52.19#ibcon#about to read 6, iclass 39, count 0 2006.173.10:59:52.19#ibcon#read 6, iclass 39, count 0 2006.173.10:59:52.19#ibcon#end of sib2, iclass 39, count 0 2006.173.10:59:52.19#ibcon#*after write, iclass 39, count 0 2006.173.10:59:52.19#ibcon#*before return 0, iclass 39, count 0 2006.173.10:59:52.19#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.10:59:52.19#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.10:59:52.19#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.10:59:52.19#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.10:59:52.19$vck44/vblo=2,634.99 2006.173.10:59:52.19#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.10:59:52.19#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.10:59:52.19#ibcon#ireg 17 cls_cnt 0 2006.173.10:59:52.19#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.10:59:52.19#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.10:59:52.19#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.10:59:52.19#ibcon#enter wrdev, iclass 3, count 0 2006.173.10:59:52.19#ibcon#first serial, iclass 3, count 0 2006.173.10:59:52.19#ibcon#enter sib2, iclass 3, count 0 2006.173.10:59:52.19#ibcon#flushed, iclass 3, count 0 2006.173.10:59:52.19#ibcon#about to write, iclass 3, count 0 2006.173.10:59:52.19#ibcon#wrote, iclass 3, count 0 2006.173.10:59:52.19#ibcon#about to read 3, iclass 3, count 0 2006.173.10:59:52.20#ibcon#read 3, iclass 3, count 0 2006.173.10:59:52.20#ibcon#about to read 4, iclass 3, count 0 2006.173.10:59:52.21#ibcon#read 4, iclass 3, count 0 2006.173.10:59:52.21#ibcon#about to read 5, iclass 3, count 0 2006.173.10:59:52.21#ibcon#read 5, iclass 3, count 0 2006.173.10:59:52.21#ibcon#about to read 6, iclass 3, count 0 2006.173.10:59:52.21#ibcon#read 6, iclass 3, count 0 2006.173.10:59:52.21#ibcon#end of sib2, iclass 3, count 0 2006.173.10:59:52.21#ibcon#*mode == 0, iclass 3, count 0 2006.173.10:59:52.21#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.10:59:52.21#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.10:59:52.21#ibcon#*before write, iclass 3, count 0 2006.173.10:59:52.21#ibcon#enter sib2, iclass 3, count 0 2006.173.10:59:52.21#ibcon#flushed, iclass 3, count 0 2006.173.10:59:52.21#ibcon#about to write, iclass 3, count 0 2006.173.10:59:52.21#ibcon#wrote, iclass 3, count 0 2006.173.10:59:52.21#ibcon#about to read 3, iclass 3, count 0 2006.173.10:59:52.24#ibcon#read 3, iclass 3, count 0 2006.173.10:59:52.25#ibcon#about to read 4, iclass 3, count 0 2006.173.10:59:52.25#ibcon#read 4, iclass 3, count 0 2006.173.10:59:52.25#ibcon#about to read 5, iclass 3, count 0 2006.173.10:59:52.25#ibcon#read 5, iclass 3, count 0 2006.173.10:59:52.25#ibcon#about to read 6, iclass 3, count 0 2006.173.10:59:52.25#ibcon#read 6, iclass 3, count 0 2006.173.10:59:52.25#ibcon#end of sib2, iclass 3, count 0 2006.173.10:59:52.25#ibcon#*after write, iclass 3, count 0 2006.173.10:59:52.25#ibcon#*before return 0, iclass 3, count 0 2006.173.10:59:52.25#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.10:59:52.25#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.10:59:52.25#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.10:59:52.25#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.10:59:52.25$vck44/vb=2,4 2006.173.10:59:52.25#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.10:59:52.25#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.10:59:52.25#ibcon#ireg 11 cls_cnt 2 2006.173.10:59:52.25#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.10:59:52.30#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.10:59:52.31#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.10:59:52.31#ibcon#enter wrdev, iclass 5, count 2 2006.173.10:59:52.31#ibcon#first serial, iclass 5, count 2 2006.173.10:59:52.31#ibcon#enter sib2, iclass 5, count 2 2006.173.10:59:52.31#ibcon#flushed, iclass 5, count 2 2006.173.10:59:52.31#ibcon#about to write, iclass 5, count 2 2006.173.10:59:52.31#ibcon#wrote, iclass 5, count 2 2006.173.10:59:52.31#ibcon#about to read 3, iclass 5, count 2 2006.173.10:59:52.32#ibcon#read 3, iclass 5, count 2 2006.173.10:59:52.33#ibcon#about to read 4, iclass 5, count 2 2006.173.10:59:52.33#ibcon#read 4, iclass 5, count 2 2006.173.10:59:52.33#ibcon#about to read 5, iclass 5, count 2 2006.173.10:59:52.33#ibcon#read 5, iclass 5, count 2 2006.173.10:59:52.33#ibcon#about to read 6, iclass 5, count 2 2006.173.10:59:52.33#ibcon#read 6, iclass 5, count 2 2006.173.10:59:52.33#ibcon#end of sib2, iclass 5, count 2 2006.173.10:59:52.33#ibcon#*mode == 0, iclass 5, count 2 2006.173.10:59:52.33#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.10:59:52.33#ibcon#[27=AT02-04\r\n] 2006.173.10:59:52.33#ibcon#*before write, iclass 5, count 2 2006.173.10:59:52.33#ibcon#enter sib2, iclass 5, count 2 2006.173.10:59:52.33#ibcon#flushed, iclass 5, count 2 2006.173.10:59:52.33#ibcon#about to write, iclass 5, count 2 2006.173.10:59:52.33#ibcon#wrote, iclass 5, count 2 2006.173.10:59:52.33#ibcon#about to read 3, iclass 5, count 2 2006.173.10:59:52.35#ibcon#read 3, iclass 5, count 2 2006.173.10:59:52.36#ibcon#about to read 4, iclass 5, count 2 2006.173.10:59:52.36#ibcon#read 4, iclass 5, count 2 2006.173.10:59:52.36#ibcon#about to read 5, iclass 5, count 2 2006.173.10:59:52.36#ibcon#read 5, iclass 5, count 2 2006.173.10:59:52.36#ibcon#about to read 6, iclass 5, count 2 2006.173.10:59:52.36#ibcon#read 6, iclass 5, count 2 2006.173.10:59:52.36#ibcon#end of sib2, iclass 5, count 2 2006.173.10:59:52.36#ibcon#*after write, iclass 5, count 2 2006.173.10:59:52.36#ibcon#*before return 0, iclass 5, count 2 2006.173.10:59:52.36#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.10:59:52.36#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.10:59:52.36#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.10:59:52.36#ibcon#ireg 7 cls_cnt 0 2006.173.10:59:52.36#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.10:59:52.47#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.10:59:52.48#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.10:59:52.48#ibcon#enter wrdev, iclass 5, count 0 2006.173.10:59:52.48#ibcon#first serial, iclass 5, count 0 2006.173.10:59:52.48#ibcon#enter sib2, iclass 5, count 0 2006.173.10:59:52.48#ibcon#flushed, iclass 5, count 0 2006.173.10:59:52.48#ibcon#about to write, iclass 5, count 0 2006.173.10:59:52.48#ibcon#wrote, iclass 5, count 0 2006.173.10:59:52.48#ibcon#about to read 3, iclass 5, count 0 2006.173.10:59:52.49#ibcon#read 3, iclass 5, count 0 2006.173.10:59:52.50#ibcon#about to read 4, iclass 5, count 0 2006.173.10:59:52.50#ibcon#read 4, iclass 5, count 0 2006.173.10:59:52.50#ibcon#about to read 5, iclass 5, count 0 2006.173.10:59:52.50#ibcon#read 5, iclass 5, count 0 2006.173.10:59:52.50#ibcon#about to read 6, iclass 5, count 0 2006.173.10:59:52.50#ibcon#read 6, iclass 5, count 0 2006.173.10:59:52.50#ibcon#end of sib2, iclass 5, count 0 2006.173.10:59:52.50#ibcon#*mode == 0, iclass 5, count 0 2006.173.10:59:52.50#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.10:59:52.50#ibcon#[27=USB\r\n] 2006.173.10:59:52.50#ibcon#*before write, iclass 5, count 0 2006.173.10:59:52.50#ibcon#enter sib2, iclass 5, count 0 2006.173.10:59:52.50#ibcon#flushed, iclass 5, count 0 2006.173.10:59:52.50#ibcon#about to write, iclass 5, count 0 2006.173.10:59:52.50#ibcon#wrote, iclass 5, count 0 2006.173.10:59:52.50#ibcon#about to read 3, iclass 5, count 0 2006.173.10:59:52.52#ibcon#read 3, iclass 5, count 0 2006.173.10:59:52.53#ibcon#about to read 4, iclass 5, count 0 2006.173.10:59:52.53#ibcon#read 4, iclass 5, count 0 2006.173.10:59:52.53#ibcon#about to read 5, iclass 5, count 0 2006.173.10:59:52.53#ibcon#read 5, iclass 5, count 0 2006.173.10:59:52.53#ibcon#about to read 6, iclass 5, count 0 2006.173.10:59:52.53#ibcon#read 6, iclass 5, count 0 2006.173.10:59:52.53#ibcon#end of sib2, iclass 5, count 0 2006.173.10:59:52.53#ibcon#*after write, iclass 5, count 0 2006.173.10:59:52.53#ibcon#*before return 0, iclass 5, count 0 2006.173.10:59:52.53#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.10:59:52.53#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.10:59:52.53#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.10:59:52.53#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.10:59:52.53$vck44/vblo=3,649.99 2006.173.10:59:52.53#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.10:59:52.53#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.10:59:52.53#ibcon#ireg 17 cls_cnt 0 2006.173.10:59:52.53#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.10:59:52.53#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.10:59:52.53#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.10:59:52.53#ibcon#enter wrdev, iclass 7, count 0 2006.173.10:59:52.53#ibcon#first serial, iclass 7, count 0 2006.173.10:59:52.53#ibcon#enter sib2, iclass 7, count 0 2006.173.10:59:52.53#ibcon#flushed, iclass 7, count 0 2006.173.10:59:52.53#ibcon#about to write, iclass 7, count 0 2006.173.10:59:52.53#ibcon#wrote, iclass 7, count 0 2006.173.10:59:52.53#ibcon#about to read 3, iclass 7, count 0 2006.173.10:59:52.54#ibcon#read 3, iclass 7, count 0 2006.173.10:59:52.54#ibcon#about to read 4, iclass 7, count 0 2006.173.10:59:52.54#ibcon#read 4, iclass 7, count 0 2006.173.10:59:52.55#ibcon#about to read 5, iclass 7, count 0 2006.173.10:59:52.55#ibcon#read 5, iclass 7, count 0 2006.173.10:59:52.55#ibcon#about to read 6, iclass 7, count 0 2006.173.10:59:52.55#ibcon#read 6, iclass 7, count 0 2006.173.10:59:52.55#ibcon#end of sib2, iclass 7, count 0 2006.173.10:59:52.55#ibcon#*mode == 0, iclass 7, count 0 2006.173.10:59:52.55#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.10:59:52.55#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.10:59:52.55#ibcon#*before write, iclass 7, count 0 2006.173.10:59:52.55#ibcon#enter sib2, iclass 7, count 0 2006.173.10:59:52.55#ibcon#flushed, iclass 7, count 0 2006.173.10:59:52.55#ibcon#about to write, iclass 7, count 0 2006.173.10:59:52.55#ibcon#wrote, iclass 7, count 0 2006.173.10:59:52.55#ibcon#about to read 3, iclass 7, count 0 2006.173.10:59:52.58#ibcon#read 3, iclass 7, count 0 2006.173.10:59:52.59#ibcon#about to read 4, iclass 7, count 0 2006.173.10:59:52.59#ibcon#read 4, iclass 7, count 0 2006.173.10:59:52.59#ibcon#about to read 5, iclass 7, count 0 2006.173.10:59:52.59#ibcon#read 5, iclass 7, count 0 2006.173.10:59:52.59#ibcon#about to read 6, iclass 7, count 0 2006.173.10:59:52.59#ibcon#read 6, iclass 7, count 0 2006.173.10:59:52.59#ibcon#end of sib2, iclass 7, count 0 2006.173.10:59:52.59#ibcon#*after write, iclass 7, count 0 2006.173.10:59:52.59#ibcon#*before return 0, iclass 7, count 0 2006.173.10:59:52.59#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.10:59:52.59#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.10:59:52.59#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.10:59:52.59#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.10:59:52.59$vck44/vb=3,4 2006.173.10:59:52.59#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.10:59:52.59#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.10:59:52.59#ibcon#ireg 11 cls_cnt 2 2006.173.10:59:52.59#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.10:59:52.64#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.10:59:52.65#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.10:59:52.65#ibcon#enter wrdev, iclass 11, count 2 2006.173.10:59:52.65#ibcon#first serial, iclass 11, count 2 2006.173.10:59:52.65#ibcon#enter sib2, iclass 11, count 2 2006.173.10:59:52.65#ibcon#flushed, iclass 11, count 2 2006.173.10:59:52.65#ibcon#about to write, iclass 11, count 2 2006.173.10:59:52.65#ibcon#wrote, iclass 11, count 2 2006.173.10:59:52.65#ibcon#about to read 3, iclass 11, count 2 2006.173.10:59:52.66#ibcon#read 3, iclass 11, count 2 2006.173.10:59:52.67#ibcon#about to read 4, iclass 11, count 2 2006.173.10:59:52.67#ibcon#read 4, iclass 11, count 2 2006.173.10:59:52.67#ibcon#about to read 5, iclass 11, count 2 2006.173.10:59:52.67#ibcon#read 5, iclass 11, count 2 2006.173.10:59:52.67#ibcon#about to read 6, iclass 11, count 2 2006.173.10:59:52.67#ibcon#read 6, iclass 11, count 2 2006.173.10:59:52.67#ibcon#end of sib2, iclass 11, count 2 2006.173.10:59:52.67#ibcon#*mode == 0, iclass 11, count 2 2006.173.10:59:52.67#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.10:59:52.67#ibcon#[27=AT03-04\r\n] 2006.173.10:59:52.67#ibcon#*before write, iclass 11, count 2 2006.173.10:59:52.67#ibcon#enter sib2, iclass 11, count 2 2006.173.10:59:52.67#ibcon#flushed, iclass 11, count 2 2006.173.10:59:52.67#ibcon#about to write, iclass 11, count 2 2006.173.10:59:52.67#ibcon#wrote, iclass 11, count 2 2006.173.10:59:52.67#ibcon#about to read 3, iclass 11, count 2 2006.173.10:59:52.69#ibcon#read 3, iclass 11, count 2 2006.173.10:59:52.70#ibcon#about to read 4, iclass 11, count 2 2006.173.10:59:52.70#ibcon#read 4, iclass 11, count 2 2006.173.10:59:52.70#ibcon#about to read 5, iclass 11, count 2 2006.173.10:59:52.70#ibcon#read 5, iclass 11, count 2 2006.173.10:59:52.70#ibcon#about to read 6, iclass 11, count 2 2006.173.10:59:52.70#ibcon#read 6, iclass 11, count 2 2006.173.10:59:52.70#ibcon#end of sib2, iclass 11, count 2 2006.173.10:59:52.70#ibcon#*after write, iclass 11, count 2 2006.173.10:59:52.70#ibcon#*before return 0, iclass 11, count 2 2006.173.10:59:52.70#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.10:59:52.70#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.10:59:52.70#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.10:59:52.70#ibcon#ireg 7 cls_cnt 0 2006.173.10:59:52.70#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.10:59:52.81#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.10:59:52.82#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.10:59:52.82#ibcon#enter wrdev, iclass 11, count 0 2006.173.10:59:52.82#ibcon#first serial, iclass 11, count 0 2006.173.10:59:52.82#ibcon#enter sib2, iclass 11, count 0 2006.173.10:59:52.82#ibcon#flushed, iclass 11, count 0 2006.173.10:59:52.82#ibcon#about to write, iclass 11, count 0 2006.173.10:59:52.82#ibcon#wrote, iclass 11, count 0 2006.173.10:59:52.82#ibcon#about to read 3, iclass 11, count 0 2006.173.10:59:52.83#ibcon#read 3, iclass 11, count 0 2006.173.10:59:52.84#ibcon#about to read 4, iclass 11, count 0 2006.173.10:59:52.84#ibcon#read 4, iclass 11, count 0 2006.173.10:59:52.84#ibcon#about to read 5, iclass 11, count 0 2006.173.10:59:52.84#ibcon#read 5, iclass 11, count 0 2006.173.10:59:52.84#ibcon#about to read 6, iclass 11, count 0 2006.173.10:59:52.84#ibcon#read 6, iclass 11, count 0 2006.173.10:59:52.84#ibcon#end of sib2, iclass 11, count 0 2006.173.10:59:52.84#ibcon#*mode == 0, iclass 11, count 0 2006.173.10:59:52.84#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.10:59:52.84#ibcon#[27=USB\r\n] 2006.173.10:59:52.84#ibcon#*before write, iclass 11, count 0 2006.173.10:59:52.84#ibcon#enter sib2, iclass 11, count 0 2006.173.10:59:52.84#ibcon#flushed, iclass 11, count 0 2006.173.10:59:52.84#ibcon#about to write, iclass 11, count 0 2006.173.10:59:52.84#ibcon#wrote, iclass 11, count 0 2006.173.10:59:52.84#ibcon#about to read 3, iclass 11, count 0 2006.173.10:59:52.86#ibcon#read 3, iclass 11, count 0 2006.173.10:59:52.87#ibcon#about to read 4, iclass 11, count 0 2006.173.10:59:52.87#ibcon#read 4, iclass 11, count 0 2006.173.10:59:52.87#ibcon#about to read 5, iclass 11, count 0 2006.173.10:59:52.87#ibcon#read 5, iclass 11, count 0 2006.173.10:59:52.87#ibcon#about to read 6, iclass 11, count 0 2006.173.10:59:52.87#ibcon#read 6, iclass 11, count 0 2006.173.10:59:52.87#ibcon#end of sib2, iclass 11, count 0 2006.173.10:59:52.87#ibcon#*after write, iclass 11, count 0 2006.173.10:59:52.87#ibcon#*before return 0, iclass 11, count 0 2006.173.10:59:52.87#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.10:59:52.87#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.10:59:52.87#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.10:59:52.87#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.10:59:52.87$vck44/vblo=4,679.99 2006.173.10:59:52.87#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.10:59:52.87#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.10:59:52.87#ibcon#ireg 17 cls_cnt 0 2006.173.10:59:52.87#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.10:59:52.87#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.10:59:52.87#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.10:59:52.87#ibcon#enter wrdev, iclass 13, count 0 2006.173.10:59:52.87#ibcon#first serial, iclass 13, count 0 2006.173.10:59:52.87#ibcon#enter sib2, iclass 13, count 0 2006.173.10:59:52.87#ibcon#flushed, iclass 13, count 0 2006.173.10:59:52.87#ibcon#about to write, iclass 13, count 0 2006.173.10:59:52.87#ibcon#wrote, iclass 13, count 0 2006.173.10:59:52.87#ibcon#about to read 3, iclass 13, count 0 2006.173.10:59:52.88#ibcon#read 3, iclass 13, count 0 2006.173.10:59:52.88#ibcon#about to read 4, iclass 13, count 0 2006.173.10:59:52.89#ibcon#read 4, iclass 13, count 0 2006.173.10:59:52.89#ibcon#about to read 5, iclass 13, count 0 2006.173.10:59:52.89#ibcon#read 5, iclass 13, count 0 2006.173.10:59:52.89#ibcon#about to read 6, iclass 13, count 0 2006.173.10:59:52.89#ibcon#read 6, iclass 13, count 0 2006.173.10:59:52.89#ibcon#end of sib2, iclass 13, count 0 2006.173.10:59:52.89#ibcon#*mode == 0, iclass 13, count 0 2006.173.10:59:52.89#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.10:59:52.89#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.10:59:52.89#ibcon#*before write, iclass 13, count 0 2006.173.10:59:52.89#ibcon#enter sib2, iclass 13, count 0 2006.173.10:59:52.89#ibcon#flushed, iclass 13, count 0 2006.173.10:59:52.89#ibcon#about to write, iclass 13, count 0 2006.173.10:59:52.89#ibcon#wrote, iclass 13, count 0 2006.173.10:59:52.89#ibcon#about to read 3, iclass 13, count 0 2006.173.10:59:52.92#ibcon#read 3, iclass 13, count 0 2006.173.10:59:52.93#ibcon#about to read 4, iclass 13, count 0 2006.173.10:59:52.93#ibcon#read 4, iclass 13, count 0 2006.173.10:59:52.93#ibcon#about to read 5, iclass 13, count 0 2006.173.10:59:52.93#ibcon#read 5, iclass 13, count 0 2006.173.10:59:52.93#ibcon#about to read 6, iclass 13, count 0 2006.173.10:59:52.93#ibcon#read 6, iclass 13, count 0 2006.173.10:59:52.93#ibcon#end of sib2, iclass 13, count 0 2006.173.10:59:52.93#ibcon#*after write, iclass 13, count 0 2006.173.10:59:52.93#ibcon#*before return 0, iclass 13, count 0 2006.173.10:59:52.93#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.10:59:52.93#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.10:59:52.93#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.10:59:52.93#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.10:59:52.93$vck44/vb=4,4 2006.173.10:59:52.93#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.10:59:52.93#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.10:59:52.93#ibcon#ireg 11 cls_cnt 2 2006.173.10:59:52.93#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.10:59:52.98#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.10:59:52.99#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.10:59:52.99#ibcon#enter wrdev, iclass 15, count 2 2006.173.10:59:52.99#ibcon#first serial, iclass 15, count 2 2006.173.10:59:52.99#ibcon#enter sib2, iclass 15, count 2 2006.173.10:59:52.99#ibcon#flushed, iclass 15, count 2 2006.173.10:59:52.99#ibcon#about to write, iclass 15, count 2 2006.173.10:59:52.99#ibcon#wrote, iclass 15, count 2 2006.173.10:59:52.99#ibcon#about to read 3, iclass 15, count 2 2006.173.10:59:53.00#ibcon#read 3, iclass 15, count 2 2006.173.10:59:53.00#ibcon#about to read 4, iclass 15, count 2 2006.173.10:59:53.01#ibcon#read 4, iclass 15, count 2 2006.173.10:59:53.01#ibcon#about to read 5, iclass 15, count 2 2006.173.10:59:53.01#ibcon#read 5, iclass 15, count 2 2006.173.10:59:53.01#ibcon#about to read 6, iclass 15, count 2 2006.173.10:59:53.01#ibcon#read 6, iclass 15, count 2 2006.173.10:59:53.01#ibcon#end of sib2, iclass 15, count 2 2006.173.10:59:53.01#ibcon#*mode == 0, iclass 15, count 2 2006.173.10:59:53.01#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.10:59:53.01#ibcon#[27=AT04-04\r\n] 2006.173.10:59:53.01#ibcon#*before write, iclass 15, count 2 2006.173.10:59:53.01#ibcon#enter sib2, iclass 15, count 2 2006.173.10:59:53.01#ibcon#flushed, iclass 15, count 2 2006.173.10:59:53.01#ibcon#about to write, iclass 15, count 2 2006.173.10:59:53.01#ibcon#wrote, iclass 15, count 2 2006.173.10:59:53.01#ibcon#about to read 3, iclass 15, count 2 2006.173.10:59:53.03#ibcon#read 3, iclass 15, count 2 2006.173.10:59:53.04#ibcon#about to read 4, iclass 15, count 2 2006.173.10:59:53.04#ibcon#read 4, iclass 15, count 2 2006.173.10:59:53.04#ibcon#about to read 5, iclass 15, count 2 2006.173.10:59:53.04#ibcon#read 5, iclass 15, count 2 2006.173.10:59:53.04#ibcon#about to read 6, iclass 15, count 2 2006.173.10:59:53.04#ibcon#read 6, iclass 15, count 2 2006.173.10:59:53.04#ibcon#end of sib2, iclass 15, count 2 2006.173.10:59:53.04#ibcon#*after write, iclass 15, count 2 2006.173.10:59:53.04#ibcon#*before return 0, iclass 15, count 2 2006.173.10:59:53.04#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.10:59:53.04#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.10:59:53.04#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.10:59:53.04#ibcon#ireg 7 cls_cnt 0 2006.173.10:59:53.04#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.10:59:53.15#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.10:59:53.16#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.10:59:53.16#ibcon#enter wrdev, iclass 15, count 0 2006.173.10:59:53.16#ibcon#first serial, iclass 15, count 0 2006.173.10:59:53.16#ibcon#enter sib2, iclass 15, count 0 2006.173.10:59:53.16#ibcon#flushed, iclass 15, count 0 2006.173.10:59:53.16#ibcon#about to write, iclass 15, count 0 2006.173.10:59:53.16#ibcon#wrote, iclass 15, count 0 2006.173.10:59:53.16#ibcon#about to read 3, iclass 15, count 0 2006.173.10:59:53.17#ibcon#read 3, iclass 15, count 0 2006.173.10:59:53.18#ibcon#about to read 4, iclass 15, count 0 2006.173.10:59:53.18#ibcon#read 4, iclass 15, count 0 2006.173.10:59:53.18#ibcon#about to read 5, iclass 15, count 0 2006.173.10:59:53.18#ibcon#read 5, iclass 15, count 0 2006.173.10:59:53.18#ibcon#about to read 6, iclass 15, count 0 2006.173.10:59:53.18#ibcon#read 6, iclass 15, count 0 2006.173.10:59:53.18#ibcon#end of sib2, iclass 15, count 0 2006.173.10:59:53.18#ibcon#*mode == 0, iclass 15, count 0 2006.173.10:59:53.18#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.10:59:53.18#ibcon#[27=USB\r\n] 2006.173.10:59:53.18#ibcon#*before write, iclass 15, count 0 2006.173.10:59:53.18#ibcon#enter sib2, iclass 15, count 0 2006.173.10:59:53.18#ibcon#flushed, iclass 15, count 0 2006.173.10:59:53.18#ibcon#about to write, iclass 15, count 0 2006.173.10:59:53.18#ibcon#wrote, iclass 15, count 0 2006.173.10:59:53.18#ibcon#about to read 3, iclass 15, count 0 2006.173.10:59:53.20#ibcon#read 3, iclass 15, count 0 2006.173.10:59:53.20#ibcon#about to read 4, iclass 15, count 0 2006.173.10:59:53.21#ibcon#read 4, iclass 15, count 0 2006.173.10:59:53.21#ibcon#about to read 5, iclass 15, count 0 2006.173.10:59:53.21#ibcon#read 5, iclass 15, count 0 2006.173.10:59:53.21#ibcon#about to read 6, iclass 15, count 0 2006.173.10:59:53.21#ibcon#read 6, iclass 15, count 0 2006.173.10:59:53.21#ibcon#end of sib2, iclass 15, count 0 2006.173.10:59:53.21#ibcon#*after write, iclass 15, count 0 2006.173.10:59:53.21#ibcon#*before return 0, iclass 15, count 0 2006.173.10:59:53.21#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.10:59:53.21#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.10:59:53.21#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.10:59:53.21#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.10:59:53.21$vck44/vblo=5,709.99 2006.173.10:59:53.21#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.10:59:53.21#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.10:59:53.21#ibcon#ireg 17 cls_cnt 0 2006.173.10:59:53.21#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.10:59:53.21#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.10:59:53.21#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.10:59:53.21#ibcon#enter wrdev, iclass 17, count 0 2006.173.10:59:53.21#ibcon#first serial, iclass 17, count 0 2006.173.10:59:53.21#ibcon#enter sib2, iclass 17, count 0 2006.173.10:59:53.21#ibcon#flushed, iclass 17, count 0 2006.173.10:59:53.21#ibcon#about to write, iclass 17, count 0 2006.173.10:59:53.21#ibcon#wrote, iclass 17, count 0 2006.173.10:59:53.21#ibcon#about to read 3, iclass 17, count 0 2006.173.10:59:53.22#ibcon#read 3, iclass 17, count 0 2006.173.10:59:53.22#ibcon#about to read 4, iclass 17, count 0 2006.173.10:59:53.23#ibcon#read 4, iclass 17, count 0 2006.173.10:59:53.23#ibcon#about to read 5, iclass 17, count 0 2006.173.10:59:53.23#ibcon#read 5, iclass 17, count 0 2006.173.10:59:53.23#ibcon#about to read 6, iclass 17, count 0 2006.173.10:59:53.23#ibcon#read 6, iclass 17, count 0 2006.173.10:59:53.23#ibcon#end of sib2, iclass 17, count 0 2006.173.10:59:53.23#ibcon#*mode == 0, iclass 17, count 0 2006.173.10:59:53.23#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.10:59:53.23#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.10:59:53.23#ibcon#*before write, iclass 17, count 0 2006.173.10:59:53.23#ibcon#enter sib2, iclass 17, count 0 2006.173.10:59:53.23#ibcon#flushed, iclass 17, count 0 2006.173.10:59:53.23#ibcon#about to write, iclass 17, count 0 2006.173.10:59:53.23#ibcon#wrote, iclass 17, count 0 2006.173.10:59:53.23#ibcon#about to read 3, iclass 17, count 0 2006.173.10:59:53.26#ibcon#read 3, iclass 17, count 0 2006.173.10:59:53.26#ibcon#about to read 4, iclass 17, count 0 2006.173.10:59:53.27#ibcon#read 4, iclass 17, count 0 2006.173.10:59:53.27#ibcon#about to read 5, iclass 17, count 0 2006.173.10:59:53.27#ibcon#read 5, iclass 17, count 0 2006.173.10:59:53.27#ibcon#about to read 6, iclass 17, count 0 2006.173.10:59:53.27#ibcon#read 6, iclass 17, count 0 2006.173.10:59:53.27#ibcon#end of sib2, iclass 17, count 0 2006.173.10:59:53.27#ibcon#*after write, iclass 17, count 0 2006.173.10:59:53.27#ibcon#*before return 0, iclass 17, count 0 2006.173.10:59:53.27#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.10:59:53.27#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.10:59:53.27#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.10:59:53.27#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.10:59:53.27$vck44/vb=5,4 2006.173.10:59:53.27#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.10:59:53.27#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.10:59:53.27#ibcon#ireg 11 cls_cnt 2 2006.173.10:59:53.27#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.10:59:53.32#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.10:59:53.32#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.10:59:53.33#ibcon#enter wrdev, iclass 19, count 2 2006.173.10:59:53.33#ibcon#first serial, iclass 19, count 2 2006.173.10:59:53.33#ibcon#enter sib2, iclass 19, count 2 2006.173.10:59:53.33#ibcon#flushed, iclass 19, count 2 2006.173.10:59:53.33#ibcon#about to write, iclass 19, count 2 2006.173.10:59:53.33#ibcon#wrote, iclass 19, count 2 2006.173.10:59:53.33#ibcon#about to read 3, iclass 19, count 2 2006.173.10:59:53.34#ibcon#read 3, iclass 19, count 2 2006.173.10:59:53.35#ibcon#about to read 4, iclass 19, count 2 2006.173.10:59:53.35#ibcon#read 4, iclass 19, count 2 2006.173.10:59:53.35#ibcon#about to read 5, iclass 19, count 2 2006.173.10:59:53.35#ibcon#read 5, iclass 19, count 2 2006.173.10:59:53.35#ibcon#about to read 6, iclass 19, count 2 2006.173.10:59:53.35#ibcon#read 6, iclass 19, count 2 2006.173.10:59:53.35#ibcon#end of sib2, iclass 19, count 2 2006.173.10:59:53.35#ibcon#*mode == 0, iclass 19, count 2 2006.173.10:59:53.35#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.10:59:53.35#ibcon#[27=AT05-04\r\n] 2006.173.10:59:53.35#ibcon#*before write, iclass 19, count 2 2006.173.10:59:53.35#ibcon#enter sib2, iclass 19, count 2 2006.173.10:59:53.35#ibcon#flushed, iclass 19, count 2 2006.173.10:59:53.35#ibcon#about to write, iclass 19, count 2 2006.173.10:59:53.35#ibcon#wrote, iclass 19, count 2 2006.173.10:59:53.35#ibcon#about to read 3, iclass 19, count 2 2006.173.10:59:53.37#ibcon#read 3, iclass 19, count 2 2006.173.10:59:53.38#ibcon#about to read 4, iclass 19, count 2 2006.173.10:59:53.38#ibcon#read 4, iclass 19, count 2 2006.173.10:59:53.38#ibcon#about to read 5, iclass 19, count 2 2006.173.10:59:53.38#ibcon#read 5, iclass 19, count 2 2006.173.10:59:53.38#ibcon#about to read 6, iclass 19, count 2 2006.173.10:59:53.38#ibcon#read 6, iclass 19, count 2 2006.173.10:59:53.38#ibcon#end of sib2, iclass 19, count 2 2006.173.10:59:53.38#ibcon#*after write, iclass 19, count 2 2006.173.10:59:53.38#ibcon#*before return 0, iclass 19, count 2 2006.173.10:59:53.38#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.10:59:53.38#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.10:59:53.38#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.10:59:53.38#ibcon#ireg 7 cls_cnt 0 2006.173.10:59:53.38#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.10:59:53.49#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.10:59:53.49#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.10:59:53.50#ibcon#enter wrdev, iclass 19, count 0 2006.173.10:59:53.50#ibcon#first serial, iclass 19, count 0 2006.173.10:59:53.50#ibcon#enter sib2, iclass 19, count 0 2006.173.10:59:53.50#ibcon#flushed, iclass 19, count 0 2006.173.10:59:53.50#ibcon#about to write, iclass 19, count 0 2006.173.10:59:53.50#ibcon#wrote, iclass 19, count 0 2006.173.10:59:53.50#ibcon#about to read 3, iclass 19, count 0 2006.173.10:59:53.51#ibcon#read 3, iclass 19, count 0 2006.173.10:59:53.52#ibcon#about to read 4, iclass 19, count 0 2006.173.10:59:53.52#ibcon#read 4, iclass 19, count 0 2006.173.10:59:53.52#ibcon#about to read 5, iclass 19, count 0 2006.173.10:59:53.52#ibcon#read 5, iclass 19, count 0 2006.173.10:59:53.52#ibcon#about to read 6, iclass 19, count 0 2006.173.10:59:53.52#ibcon#read 6, iclass 19, count 0 2006.173.10:59:53.52#ibcon#end of sib2, iclass 19, count 0 2006.173.10:59:53.52#ibcon#*mode == 0, iclass 19, count 0 2006.173.10:59:53.52#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.10:59:53.52#ibcon#[27=USB\r\n] 2006.173.10:59:53.52#ibcon#*before write, iclass 19, count 0 2006.173.10:59:53.52#ibcon#enter sib2, iclass 19, count 0 2006.173.10:59:53.52#ibcon#flushed, iclass 19, count 0 2006.173.10:59:53.52#ibcon#about to write, iclass 19, count 0 2006.173.10:59:53.52#ibcon#wrote, iclass 19, count 0 2006.173.10:59:53.52#ibcon#about to read 3, iclass 19, count 0 2006.173.10:59:53.54#ibcon#read 3, iclass 19, count 0 2006.173.10:59:53.55#ibcon#about to read 4, iclass 19, count 0 2006.173.10:59:53.55#ibcon#read 4, iclass 19, count 0 2006.173.10:59:53.55#ibcon#about to read 5, iclass 19, count 0 2006.173.10:59:53.55#ibcon#read 5, iclass 19, count 0 2006.173.10:59:53.55#ibcon#about to read 6, iclass 19, count 0 2006.173.10:59:53.55#ibcon#read 6, iclass 19, count 0 2006.173.10:59:53.55#ibcon#end of sib2, iclass 19, count 0 2006.173.10:59:53.55#ibcon#*after write, iclass 19, count 0 2006.173.10:59:53.55#ibcon#*before return 0, iclass 19, count 0 2006.173.10:59:53.55#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.10:59:53.55#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.10:59:53.55#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.10:59:53.55#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.10:59:53.55$vck44/vblo=6,719.99 2006.173.10:59:53.55#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.10:59:53.55#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.10:59:53.55#ibcon#ireg 17 cls_cnt 0 2006.173.10:59:53.55#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.10:59:53.55#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.10:59:53.55#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.10:59:53.55#ibcon#enter wrdev, iclass 21, count 0 2006.173.10:59:53.55#ibcon#first serial, iclass 21, count 0 2006.173.10:59:53.55#ibcon#enter sib2, iclass 21, count 0 2006.173.10:59:53.55#ibcon#flushed, iclass 21, count 0 2006.173.10:59:53.55#ibcon#about to write, iclass 21, count 0 2006.173.10:59:53.55#ibcon#wrote, iclass 21, count 0 2006.173.10:59:53.55#ibcon#about to read 3, iclass 21, count 0 2006.173.10:59:53.56#ibcon#read 3, iclass 21, count 0 2006.173.10:59:53.57#ibcon#about to read 4, iclass 21, count 0 2006.173.10:59:53.57#ibcon#read 4, iclass 21, count 0 2006.173.10:59:53.57#ibcon#about to read 5, iclass 21, count 0 2006.173.10:59:53.57#ibcon#read 5, iclass 21, count 0 2006.173.10:59:53.57#ibcon#about to read 6, iclass 21, count 0 2006.173.10:59:53.57#ibcon#read 6, iclass 21, count 0 2006.173.10:59:53.57#ibcon#end of sib2, iclass 21, count 0 2006.173.10:59:53.57#ibcon#*mode == 0, iclass 21, count 0 2006.173.10:59:53.57#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.10:59:53.57#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.10:59:53.57#ibcon#*before write, iclass 21, count 0 2006.173.10:59:53.57#ibcon#enter sib2, iclass 21, count 0 2006.173.10:59:53.57#ibcon#flushed, iclass 21, count 0 2006.173.10:59:53.57#ibcon#about to write, iclass 21, count 0 2006.173.10:59:53.57#ibcon#wrote, iclass 21, count 0 2006.173.10:59:53.57#ibcon#about to read 3, iclass 21, count 0 2006.173.10:59:53.60#ibcon#read 3, iclass 21, count 0 2006.173.10:59:53.60#ibcon#about to read 4, iclass 21, count 0 2006.173.10:59:53.61#ibcon#read 4, iclass 21, count 0 2006.173.10:59:53.61#ibcon#about to read 5, iclass 21, count 0 2006.173.10:59:53.61#ibcon#read 5, iclass 21, count 0 2006.173.10:59:53.61#ibcon#about to read 6, iclass 21, count 0 2006.173.10:59:53.61#ibcon#read 6, iclass 21, count 0 2006.173.10:59:53.61#ibcon#end of sib2, iclass 21, count 0 2006.173.10:59:53.61#ibcon#*after write, iclass 21, count 0 2006.173.10:59:53.61#ibcon#*before return 0, iclass 21, count 0 2006.173.10:59:53.61#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.10:59:53.61#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.10:59:53.61#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.10:59:53.61#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.10:59:53.61$vck44/vb=6,4 2006.173.10:59:53.61#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.10:59:53.61#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.10:59:53.61#ibcon#ireg 11 cls_cnt 2 2006.173.10:59:53.61#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.10:59:53.66#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.10:59:53.67#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.10:59:53.67#ibcon#enter wrdev, iclass 23, count 2 2006.173.10:59:53.67#ibcon#first serial, iclass 23, count 2 2006.173.10:59:53.67#ibcon#enter sib2, iclass 23, count 2 2006.173.10:59:53.67#ibcon#flushed, iclass 23, count 2 2006.173.10:59:53.67#ibcon#about to write, iclass 23, count 2 2006.173.10:59:53.67#ibcon#wrote, iclass 23, count 2 2006.173.10:59:53.67#ibcon#about to read 3, iclass 23, count 2 2006.173.10:59:53.68#ibcon#read 3, iclass 23, count 2 2006.173.10:59:53.69#ibcon#about to read 4, iclass 23, count 2 2006.173.10:59:53.69#ibcon#read 4, iclass 23, count 2 2006.173.10:59:53.69#ibcon#about to read 5, iclass 23, count 2 2006.173.10:59:53.69#ibcon#read 5, iclass 23, count 2 2006.173.10:59:53.69#ibcon#about to read 6, iclass 23, count 2 2006.173.10:59:53.69#ibcon#read 6, iclass 23, count 2 2006.173.10:59:53.69#ibcon#end of sib2, iclass 23, count 2 2006.173.10:59:53.69#ibcon#*mode == 0, iclass 23, count 2 2006.173.10:59:53.69#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.10:59:53.69#ibcon#[27=AT06-04\r\n] 2006.173.10:59:53.69#ibcon#*before write, iclass 23, count 2 2006.173.10:59:53.69#ibcon#enter sib2, iclass 23, count 2 2006.173.10:59:53.69#ibcon#flushed, iclass 23, count 2 2006.173.10:59:53.69#ibcon#about to write, iclass 23, count 2 2006.173.10:59:53.69#ibcon#wrote, iclass 23, count 2 2006.173.10:59:53.69#ibcon#about to read 3, iclass 23, count 2 2006.173.10:59:53.72#ibcon#read 3, iclass 23, count 2 2006.173.10:59:53.72#ibcon#about to read 4, iclass 23, count 2 2006.173.10:59:53.72#ibcon#read 4, iclass 23, count 2 2006.173.10:59:53.72#ibcon#about to read 5, iclass 23, count 2 2006.173.10:59:53.72#ibcon#read 5, iclass 23, count 2 2006.173.10:59:53.72#ibcon#about to read 6, iclass 23, count 2 2006.173.10:59:53.72#ibcon#read 6, iclass 23, count 2 2006.173.10:59:53.72#ibcon#end of sib2, iclass 23, count 2 2006.173.10:59:53.72#ibcon#*after write, iclass 23, count 2 2006.173.10:59:53.72#ibcon#*before return 0, iclass 23, count 2 2006.173.10:59:53.72#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.10:59:53.72#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.10:59:53.72#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.10:59:53.72#ibcon#ireg 7 cls_cnt 0 2006.173.10:59:53.72#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.10:59:53.83#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.10:59:53.84#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.10:59:53.84#ibcon#enter wrdev, iclass 23, count 0 2006.173.10:59:53.84#ibcon#first serial, iclass 23, count 0 2006.173.10:59:53.84#ibcon#enter sib2, iclass 23, count 0 2006.173.10:59:53.84#ibcon#flushed, iclass 23, count 0 2006.173.10:59:53.84#ibcon#about to write, iclass 23, count 0 2006.173.10:59:53.84#ibcon#wrote, iclass 23, count 0 2006.173.10:59:53.84#ibcon#about to read 3, iclass 23, count 0 2006.173.10:59:53.85#ibcon#read 3, iclass 23, count 0 2006.173.10:59:53.86#ibcon#about to read 4, iclass 23, count 0 2006.173.10:59:53.86#ibcon#read 4, iclass 23, count 0 2006.173.10:59:53.86#ibcon#about to read 5, iclass 23, count 0 2006.173.10:59:53.86#ibcon#read 5, iclass 23, count 0 2006.173.10:59:53.86#ibcon#about to read 6, iclass 23, count 0 2006.173.10:59:53.86#ibcon#read 6, iclass 23, count 0 2006.173.10:59:53.86#ibcon#end of sib2, iclass 23, count 0 2006.173.10:59:53.86#ibcon#*mode == 0, iclass 23, count 0 2006.173.10:59:53.86#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.10:59:53.86#ibcon#[27=USB\r\n] 2006.173.10:59:53.86#ibcon#*before write, iclass 23, count 0 2006.173.10:59:53.86#ibcon#enter sib2, iclass 23, count 0 2006.173.10:59:53.86#ibcon#flushed, iclass 23, count 0 2006.173.10:59:53.86#ibcon#about to write, iclass 23, count 0 2006.173.10:59:53.86#ibcon#wrote, iclass 23, count 0 2006.173.10:59:53.86#ibcon#about to read 3, iclass 23, count 0 2006.173.10:59:53.88#ibcon#read 3, iclass 23, count 0 2006.173.10:59:53.89#ibcon#about to read 4, iclass 23, count 0 2006.173.10:59:53.89#ibcon#read 4, iclass 23, count 0 2006.173.10:59:53.89#ibcon#about to read 5, iclass 23, count 0 2006.173.10:59:53.89#ibcon#read 5, iclass 23, count 0 2006.173.10:59:53.89#ibcon#about to read 6, iclass 23, count 0 2006.173.10:59:53.89#ibcon#read 6, iclass 23, count 0 2006.173.10:59:53.89#ibcon#end of sib2, iclass 23, count 0 2006.173.10:59:53.89#ibcon#*after write, iclass 23, count 0 2006.173.10:59:53.89#ibcon#*before return 0, iclass 23, count 0 2006.173.10:59:53.89#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.10:59:53.89#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.10:59:53.89#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.10:59:53.89#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.10:59:53.89$vck44/vblo=7,734.99 2006.173.10:59:53.89#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.10:59:53.89#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.10:59:53.89#ibcon#ireg 17 cls_cnt 0 2006.173.10:59:53.89#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.10:59:53.89#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.10:59:53.89#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.10:59:53.89#ibcon#enter wrdev, iclass 25, count 0 2006.173.10:59:53.89#ibcon#first serial, iclass 25, count 0 2006.173.10:59:53.89#ibcon#enter sib2, iclass 25, count 0 2006.173.10:59:53.89#ibcon#flushed, iclass 25, count 0 2006.173.10:59:53.89#ibcon#about to write, iclass 25, count 0 2006.173.10:59:53.89#ibcon#wrote, iclass 25, count 0 2006.173.10:59:53.89#ibcon#about to read 3, iclass 25, count 0 2006.173.10:59:53.90#ibcon#read 3, iclass 25, count 0 2006.173.10:59:53.91#ibcon#about to read 4, iclass 25, count 0 2006.173.10:59:53.91#ibcon#read 4, iclass 25, count 0 2006.173.10:59:53.91#ibcon#about to read 5, iclass 25, count 0 2006.173.10:59:53.91#ibcon#read 5, iclass 25, count 0 2006.173.10:59:53.91#ibcon#about to read 6, iclass 25, count 0 2006.173.10:59:53.91#ibcon#read 6, iclass 25, count 0 2006.173.10:59:53.91#ibcon#end of sib2, iclass 25, count 0 2006.173.10:59:53.91#ibcon#*mode == 0, iclass 25, count 0 2006.173.10:59:53.91#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.10:59:53.91#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.10:59:53.91#ibcon#*before write, iclass 25, count 0 2006.173.10:59:53.91#ibcon#enter sib2, iclass 25, count 0 2006.173.10:59:53.91#ibcon#flushed, iclass 25, count 0 2006.173.10:59:53.91#ibcon#about to write, iclass 25, count 0 2006.173.10:59:53.91#ibcon#wrote, iclass 25, count 0 2006.173.10:59:53.91#ibcon#about to read 3, iclass 25, count 0 2006.173.10:59:53.94#ibcon#read 3, iclass 25, count 0 2006.173.10:59:53.94#ibcon#about to read 4, iclass 25, count 0 2006.173.10:59:53.95#ibcon#read 4, iclass 25, count 0 2006.173.10:59:53.95#ibcon#about to read 5, iclass 25, count 0 2006.173.10:59:53.95#ibcon#read 5, iclass 25, count 0 2006.173.10:59:53.95#ibcon#about to read 6, iclass 25, count 0 2006.173.10:59:53.95#ibcon#read 6, iclass 25, count 0 2006.173.10:59:53.95#ibcon#end of sib2, iclass 25, count 0 2006.173.10:59:53.95#ibcon#*after write, iclass 25, count 0 2006.173.10:59:53.95#ibcon#*before return 0, iclass 25, count 0 2006.173.10:59:53.95#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.10:59:53.95#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.10:59:53.95#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.10:59:53.95#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.10:59:53.95$vck44/vb=7,4 2006.173.10:59:53.95#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.10:59:53.95#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.10:59:53.95#ibcon#ireg 11 cls_cnt 2 2006.173.10:59:53.95#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.10:59:54.01#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.10:59:54.01#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.10:59:54.01#ibcon#enter wrdev, iclass 27, count 2 2006.173.10:59:54.01#ibcon#first serial, iclass 27, count 2 2006.173.10:59:54.01#ibcon#enter sib2, iclass 27, count 2 2006.173.10:59:54.01#ibcon#flushed, iclass 27, count 2 2006.173.10:59:54.01#ibcon#about to write, iclass 27, count 2 2006.173.10:59:54.01#ibcon#wrote, iclass 27, count 2 2006.173.10:59:54.01#ibcon#about to read 3, iclass 27, count 2 2006.173.10:59:54.02#ibcon#read 3, iclass 27, count 2 2006.173.10:59:54.03#ibcon#about to read 4, iclass 27, count 2 2006.173.10:59:54.03#ibcon#read 4, iclass 27, count 2 2006.173.10:59:54.03#ibcon#about to read 5, iclass 27, count 2 2006.173.10:59:54.03#ibcon#read 5, iclass 27, count 2 2006.173.10:59:54.03#ibcon#about to read 6, iclass 27, count 2 2006.173.10:59:54.03#ibcon#read 6, iclass 27, count 2 2006.173.10:59:54.03#ibcon#end of sib2, iclass 27, count 2 2006.173.10:59:54.03#ibcon#*mode == 0, iclass 27, count 2 2006.173.10:59:54.03#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.10:59:54.03#ibcon#[27=AT07-04\r\n] 2006.173.10:59:54.03#ibcon#*before write, iclass 27, count 2 2006.173.10:59:54.03#ibcon#enter sib2, iclass 27, count 2 2006.173.10:59:54.03#ibcon#flushed, iclass 27, count 2 2006.173.10:59:54.03#ibcon#about to write, iclass 27, count 2 2006.173.10:59:54.03#ibcon#wrote, iclass 27, count 2 2006.173.10:59:54.03#ibcon#about to read 3, iclass 27, count 2 2006.173.10:59:54.05#ibcon#read 3, iclass 27, count 2 2006.173.10:59:54.06#ibcon#about to read 4, iclass 27, count 2 2006.173.10:59:54.06#ibcon#read 4, iclass 27, count 2 2006.173.10:59:54.06#ibcon#about to read 5, iclass 27, count 2 2006.173.10:59:54.06#ibcon#read 5, iclass 27, count 2 2006.173.10:59:54.06#ibcon#about to read 6, iclass 27, count 2 2006.173.10:59:54.06#ibcon#read 6, iclass 27, count 2 2006.173.10:59:54.06#ibcon#end of sib2, iclass 27, count 2 2006.173.10:59:54.06#ibcon#*after write, iclass 27, count 2 2006.173.10:59:54.06#ibcon#*before return 0, iclass 27, count 2 2006.173.10:59:54.06#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.10:59:54.06#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.10:59:54.06#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.10:59:54.06#ibcon#ireg 7 cls_cnt 0 2006.173.10:59:54.06#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.10:59:54.17#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.10:59:54.17#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.10:59:54.18#ibcon#enter wrdev, iclass 27, count 0 2006.173.10:59:54.18#ibcon#first serial, iclass 27, count 0 2006.173.10:59:54.18#ibcon#enter sib2, iclass 27, count 0 2006.173.10:59:54.18#ibcon#flushed, iclass 27, count 0 2006.173.10:59:54.18#ibcon#about to write, iclass 27, count 0 2006.173.10:59:54.18#ibcon#wrote, iclass 27, count 0 2006.173.10:59:54.18#ibcon#about to read 3, iclass 27, count 0 2006.173.10:59:54.19#ibcon#read 3, iclass 27, count 0 2006.173.10:59:54.20#ibcon#about to read 4, iclass 27, count 0 2006.173.10:59:54.20#ibcon#read 4, iclass 27, count 0 2006.173.10:59:54.20#ibcon#about to read 5, iclass 27, count 0 2006.173.10:59:54.20#ibcon#read 5, iclass 27, count 0 2006.173.10:59:54.20#ibcon#about to read 6, iclass 27, count 0 2006.173.10:59:54.20#ibcon#read 6, iclass 27, count 0 2006.173.10:59:54.20#ibcon#end of sib2, iclass 27, count 0 2006.173.10:59:54.20#ibcon#*mode == 0, iclass 27, count 0 2006.173.10:59:54.20#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.10:59:54.20#ibcon#[27=USB\r\n] 2006.173.10:59:54.20#ibcon#*before write, iclass 27, count 0 2006.173.10:59:54.20#ibcon#enter sib2, iclass 27, count 0 2006.173.10:59:54.20#ibcon#flushed, iclass 27, count 0 2006.173.10:59:54.20#ibcon#about to write, iclass 27, count 0 2006.173.10:59:54.20#ibcon#wrote, iclass 27, count 0 2006.173.10:59:54.20#ibcon#about to read 3, iclass 27, count 0 2006.173.10:59:54.22#ibcon#read 3, iclass 27, count 0 2006.173.10:59:54.22#ibcon#about to read 4, iclass 27, count 0 2006.173.10:59:54.23#ibcon#read 4, iclass 27, count 0 2006.173.10:59:54.23#ibcon#about to read 5, iclass 27, count 0 2006.173.10:59:54.23#ibcon#read 5, iclass 27, count 0 2006.173.10:59:54.23#ibcon#about to read 6, iclass 27, count 0 2006.173.10:59:54.23#ibcon#read 6, iclass 27, count 0 2006.173.10:59:54.23#ibcon#end of sib2, iclass 27, count 0 2006.173.10:59:54.23#ibcon#*after write, iclass 27, count 0 2006.173.10:59:54.23#ibcon#*before return 0, iclass 27, count 0 2006.173.10:59:54.23#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.10:59:54.23#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.10:59:54.23#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.10:59:54.23#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.10:59:54.23$vck44/vblo=8,744.99 2006.173.10:59:54.23#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.10:59:54.23#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.10:59:54.23#ibcon#ireg 17 cls_cnt 0 2006.173.10:59:54.23#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.10:59:54.23#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.10:59:54.23#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.10:59:54.23#ibcon#enter wrdev, iclass 29, count 0 2006.173.10:59:54.23#ibcon#first serial, iclass 29, count 0 2006.173.10:59:54.23#ibcon#enter sib2, iclass 29, count 0 2006.173.10:59:54.23#ibcon#flushed, iclass 29, count 0 2006.173.10:59:54.23#ibcon#about to write, iclass 29, count 0 2006.173.10:59:54.23#ibcon#wrote, iclass 29, count 0 2006.173.10:59:54.23#ibcon#about to read 3, iclass 29, count 0 2006.173.10:59:54.24#ibcon#read 3, iclass 29, count 0 2006.173.10:59:54.24#ibcon#about to read 4, iclass 29, count 0 2006.173.10:59:54.25#ibcon#read 4, iclass 29, count 0 2006.173.10:59:54.25#ibcon#about to read 5, iclass 29, count 0 2006.173.10:59:54.25#ibcon#read 5, iclass 29, count 0 2006.173.10:59:54.25#ibcon#about to read 6, iclass 29, count 0 2006.173.10:59:54.25#ibcon#read 6, iclass 29, count 0 2006.173.10:59:54.25#ibcon#end of sib2, iclass 29, count 0 2006.173.10:59:54.25#ibcon#*mode == 0, iclass 29, count 0 2006.173.10:59:54.25#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.10:59:54.25#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.10:59:54.25#ibcon#*before write, iclass 29, count 0 2006.173.10:59:54.25#ibcon#enter sib2, iclass 29, count 0 2006.173.10:59:54.25#ibcon#flushed, iclass 29, count 0 2006.173.10:59:54.25#ibcon#about to write, iclass 29, count 0 2006.173.10:59:54.25#ibcon#wrote, iclass 29, count 0 2006.173.10:59:54.25#ibcon#about to read 3, iclass 29, count 0 2006.173.10:59:54.28#ibcon#read 3, iclass 29, count 0 2006.173.10:59:54.29#ibcon#about to read 4, iclass 29, count 0 2006.173.10:59:54.29#ibcon#read 4, iclass 29, count 0 2006.173.10:59:54.29#ibcon#about to read 5, iclass 29, count 0 2006.173.10:59:54.29#ibcon#read 5, iclass 29, count 0 2006.173.10:59:54.29#ibcon#about to read 6, iclass 29, count 0 2006.173.10:59:54.29#ibcon#read 6, iclass 29, count 0 2006.173.10:59:54.29#ibcon#end of sib2, iclass 29, count 0 2006.173.10:59:54.29#ibcon#*after write, iclass 29, count 0 2006.173.10:59:54.29#ibcon#*before return 0, iclass 29, count 0 2006.173.10:59:54.29#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.10:59:54.29#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.10:59:54.29#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.10:59:54.29#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.10:59:54.29$vck44/vb=8,4 2006.173.10:59:54.29#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.10:59:54.29#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.10:59:54.29#ibcon#ireg 11 cls_cnt 2 2006.173.10:59:54.29#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.10:59:54.34#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.10:59:54.35#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.10:59:54.35#ibcon#enter wrdev, iclass 31, count 2 2006.173.10:59:54.35#ibcon#first serial, iclass 31, count 2 2006.173.10:59:54.35#ibcon#enter sib2, iclass 31, count 2 2006.173.10:59:54.35#ibcon#flushed, iclass 31, count 2 2006.173.10:59:54.35#ibcon#about to write, iclass 31, count 2 2006.173.10:59:54.35#ibcon#wrote, iclass 31, count 2 2006.173.10:59:54.35#ibcon#about to read 3, iclass 31, count 2 2006.173.10:59:54.36#ibcon#read 3, iclass 31, count 2 2006.173.10:59:54.36#ibcon#about to read 4, iclass 31, count 2 2006.173.10:59:54.37#ibcon#read 4, iclass 31, count 2 2006.173.10:59:54.37#ibcon#about to read 5, iclass 31, count 2 2006.173.10:59:54.37#ibcon#read 5, iclass 31, count 2 2006.173.10:59:54.37#ibcon#about to read 6, iclass 31, count 2 2006.173.10:59:54.37#ibcon#read 6, iclass 31, count 2 2006.173.10:59:54.37#ibcon#end of sib2, iclass 31, count 2 2006.173.10:59:54.37#ibcon#*mode == 0, iclass 31, count 2 2006.173.10:59:54.37#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.10:59:54.37#ibcon#[27=AT08-04\r\n] 2006.173.10:59:54.37#ibcon#*before write, iclass 31, count 2 2006.173.10:59:54.37#ibcon#enter sib2, iclass 31, count 2 2006.173.10:59:54.37#ibcon#flushed, iclass 31, count 2 2006.173.10:59:54.37#ibcon#about to write, iclass 31, count 2 2006.173.10:59:54.37#ibcon#wrote, iclass 31, count 2 2006.173.10:59:54.37#ibcon#about to read 3, iclass 31, count 2 2006.173.10:59:54.39#ibcon#read 3, iclass 31, count 2 2006.173.10:59:54.40#ibcon#about to read 4, iclass 31, count 2 2006.173.10:59:54.40#ibcon#read 4, iclass 31, count 2 2006.173.10:59:54.40#ibcon#about to read 5, iclass 31, count 2 2006.173.10:59:54.40#ibcon#read 5, iclass 31, count 2 2006.173.10:59:54.40#ibcon#about to read 6, iclass 31, count 2 2006.173.10:59:54.40#ibcon#read 6, iclass 31, count 2 2006.173.10:59:54.40#ibcon#end of sib2, iclass 31, count 2 2006.173.10:59:54.40#ibcon#*after write, iclass 31, count 2 2006.173.10:59:54.40#ibcon#*before return 0, iclass 31, count 2 2006.173.10:59:54.40#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.10:59:54.40#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.10:59:54.40#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.10:59:54.40#ibcon#ireg 7 cls_cnt 0 2006.173.10:59:54.40#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.10:59:54.51#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.10:59:54.51#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.10:59:54.52#ibcon#enter wrdev, iclass 31, count 0 2006.173.10:59:54.52#ibcon#first serial, iclass 31, count 0 2006.173.10:59:54.52#ibcon#enter sib2, iclass 31, count 0 2006.173.10:59:54.52#ibcon#flushed, iclass 31, count 0 2006.173.10:59:54.52#ibcon#about to write, iclass 31, count 0 2006.173.10:59:54.52#ibcon#wrote, iclass 31, count 0 2006.173.10:59:54.52#ibcon#about to read 3, iclass 31, count 0 2006.173.10:59:54.53#ibcon#read 3, iclass 31, count 0 2006.173.10:59:54.53#ibcon#about to read 4, iclass 31, count 0 2006.173.10:59:54.54#ibcon#read 4, iclass 31, count 0 2006.173.10:59:54.54#ibcon#about to read 5, iclass 31, count 0 2006.173.10:59:54.54#ibcon#read 5, iclass 31, count 0 2006.173.10:59:54.54#ibcon#about to read 6, iclass 31, count 0 2006.173.10:59:54.54#ibcon#read 6, iclass 31, count 0 2006.173.10:59:54.54#ibcon#end of sib2, iclass 31, count 0 2006.173.10:59:54.54#ibcon#*mode == 0, iclass 31, count 0 2006.173.10:59:54.54#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.10:59:54.54#ibcon#[27=USB\r\n] 2006.173.10:59:54.54#ibcon#*before write, iclass 31, count 0 2006.173.10:59:54.54#ibcon#enter sib2, iclass 31, count 0 2006.173.10:59:54.54#ibcon#flushed, iclass 31, count 0 2006.173.10:59:54.54#ibcon#about to write, iclass 31, count 0 2006.173.10:59:54.54#ibcon#wrote, iclass 31, count 0 2006.173.10:59:54.54#ibcon#about to read 3, iclass 31, count 0 2006.173.10:59:54.56#ibcon#read 3, iclass 31, count 0 2006.173.10:59:54.56#ibcon#about to read 4, iclass 31, count 0 2006.173.10:59:54.56#ibcon#read 4, iclass 31, count 0 2006.173.10:59:54.57#ibcon#about to read 5, iclass 31, count 0 2006.173.10:59:54.57#ibcon#read 5, iclass 31, count 0 2006.173.10:59:54.57#ibcon#about to read 6, iclass 31, count 0 2006.173.10:59:54.57#ibcon#read 6, iclass 31, count 0 2006.173.10:59:54.57#ibcon#end of sib2, iclass 31, count 0 2006.173.10:59:54.57#ibcon#*after write, iclass 31, count 0 2006.173.10:59:54.57#ibcon#*before return 0, iclass 31, count 0 2006.173.10:59:54.57#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.10:59:54.57#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.10:59:54.57#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.10:59:54.57#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.10:59:54.57$vck44/vabw=wide 2006.173.10:59:54.57#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.10:59:54.57#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.10:59:54.57#ibcon#ireg 8 cls_cnt 0 2006.173.10:59:54.57#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.10:59:54.57#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.10:59:54.57#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.10:59:54.57#ibcon#enter wrdev, iclass 33, count 0 2006.173.10:59:54.57#ibcon#first serial, iclass 33, count 0 2006.173.10:59:54.57#ibcon#enter sib2, iclass 33, count 0 2006.173.10:59:54.57#ibcon#flushed, iclass 33, count 0 2006.173.10:59:54.57#ibcon#about to write, iclass 33, count 0 2006.173.10:59:54.57#ibcon#wrote, iclass 33, count 0 2006.173.10:59:54.57#ibcon#about to read 3, iclass 33, count 0 2006.173.10:59:54.58#ibcon#read 3, iclass 33, count 0 2006.173.10:59:54.58#ibcon#about to read 4, iclass 33, count 0 2006.173.10:59:54.59#ibcon#read 4, iclass 33, count 0 2006.173.10:59:54.59#ibcon#about to read 5, iclass 33, count 0 2006.173.10:59:54.59#ibcon#read 5, iclass 33, count 0 2006.173.10:59:54.59#ibcon#about to read 6, iclass 33, count 0 2006.173.10:59:54.59#ibcon#read 6, iclass 33, count 0 2006.173.10:59:54.59#ibcon#end of sib2, iclass 33, count 0 2006.173.10:59:54.59#ibcon#*mode == 0, iclass 33, count 0 2006.173.10:59:54.59#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.10:59:54.59#ibcon#[25=BW32\r\n] 2006.173.10:59:54.59#ibcon#*before write, iclass 33, count 0 2006.173.10:59:54.59#ibcon#enter sib2, iclass 33, count 0 2006.173.10:59:54.59#ibcon#flushed, iclass 33, count 0 2006.173.10:59:54.59#ibcon#about to write, iclass 33, count 0 2006.173.10:59:54.59#ibcon#wrote, iclass 33, count 0 2006.173.10:59:54.59#ibcon#about to read 3, iclass 33, count 0 2006.173.10:59:54.61#ibcon#read 3, iclass 33, count 0 2006.173.10:59:54.62#ibcon#about to read 4, iclass 33, count 0 2006.173.10:59:54.62#ibcon#read 4, iclass 33, count 0 2006.173.10:59:54.62#ibcon#about to read 5, iclass 33, count 0 2006.173.10:59:54.62#ibcon#read 5, iclass 33, count 0 2006.173.10:59:54.62#ibcon#about to read 6, iclass 33, count 0 2006.173.10:59:54.62#ibcon#read 6, iclass 33, count 0 2006.173.10:59:54.62#ibcon#end of sib2, iclass 33, count 0 2006.173.10:59:54.62#ibcon#*after write, iclass 33, count 0 2006.173.10:59:54.62#ibcon#*before return 0, iclass 33, count 0 2006.173.10:59:54.62#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.10:59:54.62#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.10:59:54.62#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.10:59:54.62#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.10:59:54.62$vck44/vbbw=wide 2006.173.10:59:54.62#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.10:59:54.62#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.10:59:54.62#ibcon#ireg 8 cls_cnt 0 2006.173.10:59:54.62#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.10:59:54.68#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.10:59:54.69#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.10:59:54.69#ibcon#enter wrdev, iclass 35, count 0 2006.173.10:59:54.69#ibcon#first serial, iclass 35, count 0 2006.173.10:59:54.69#ibcon#enter sib2, iclass 35, count 0 2006.173.10:59:54.69#ibcon#flushed, iclass 35, count 0 2006.173.10:59:54.69#ibcon#about to write, iclass 35, count 0 2006.173.10:59:54.69#ibcon#wrote, iclass 35, count 0 2006.173.10:59:54.69#ibcon#about to read 3, iclass 35, count 0 2006.173.10:59:54.70#ibcon#read 3, iclass 35, count 0 2006.173.10:59:54.70#ibcon#about to read 4, iclass 35, count 0 2006.173.10:59:54.71#ibcon#read 4, iclass 35, count 0 2006.173.10:59:54.71#ibcon#about to read 5, iclass 35, count 0 2006.173.10:59:54.71#ibcon#read 5, iclass 35, count 0 2006.173.10:59:54.71#ibcon#about to read 6, iclass 35, count 0 2006.173.10:59:54.71#ibcon#read 6, iclass 35, count 0 2006.173.10:59:54.71#ibcon#end of sib2, iclass 35, count 0 2006.173.10:59:54.71#ibcon#*mode == 0, iclass 35, count 0 2006.173.10:59:54.71#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.10:59:54.71#ibcon#[27=BW32\r\n] 2006.173.10:59:54.71#ibcon#*before write, iclass 35, count 0 2006.173.10:59:54.71#ibcon#enter sib2, iclass 35, count 0 2006.173.10:59:54.71#ibcon#flushed, iclass 35, count 0 2006.173.10:59:54.71#ibcon#about to write, iclass 35, count 0 2006.173.10:59:54.71#ibcon#wrote, iclass 35, count 0 2006.173.10:59:54.71#ibcon#about to read 3, iclass 35, count 0 2006.173.10:59:54.73#ibcon#read 3, iclass 35, count 0 2006.173.10:59:54.74#ibcon#about to read 4, iclass 35, count 0 2006.173.10:59:54.74#ibcon#read 4, iclass 35, count 0 2006.173.10:59:54.74#ibcon#about to read 5, iclass 35, count 0 2006.173.10:59:54.74#ibcon#read 5, iclass 35, count 0 2006.173.10:59:54.74#ibcon#about to read 6, iclass 35, count 0 2006.173.10:59:54.74#ibcon#read 6, iclass 35, count 0 2006.173.10:59:54.74#ibcon#end of sib2, iclass 35, count 0 2006.173.10:59:54.74#ibcon#*after write, iclass 35, count 0 2006.173.10:59:54.74#ibcon#*before return 0, iclass 35, count 0 2006.173.10:59:54.74#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.10:59:54.74#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.10:59:54.74#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.10:59:54.74#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.10:59:54.74$setupk4/ifdk4 2006.173.10:59:54.74$ifdk4/lo= 2006.173.10:59:54.74$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.10:59:54.74$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.10:59:54.74$ifdk4/patch= 2006.173.10:59:54.74$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.10:59:54.74$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.10:59:54.74$setupk4/!*+20s 2006.173.10:59:54.79#abcon#<5=/03 0.8 1.8 22.57 921004.0\r\n> 2006.173.10:59:54.81#abcon#{5=INTERFACE CLEAR} 2006.173.10:59:54.86#abcon#[5=S1D000X0/0*\r\n] 2006.173.11:00:03.13#trakl#Source acquired 2006.173.11:00:03.14#flagr#flagr/antenna,acquired 2006.173.11:00:04.95#abcon#<5=/03 0.8 1.8 22.57 921004.0\r\n> 2006.173.11:00:04.97#abcon#{5=INTERFACE CLEAR} 2006.173.11:00:05.03#abcon#[5=S1D000X0/0*\r\n] 2006.173.11:00:09.25$setupk4/"tpicd 2006.173.11:00:09.26$setupk4/echo=off 2006.173.11:00:09.26$setupk4/xlog=off 2006.173.11:00:09.26:!2006.173.11:06:34 2006.173.11:06:34.00:preob 2006.173.11:06:34.13/onsource/TRACKING 2006.173.11:06:34.13:!2006.173.11:06:44 2006.173.11:06:44.00:"tape 2006.173.11:06:44.00:"st=record 2006.173.11:06:44.00:data_valid=on 2006.173.11:06:44.00:midob 2006.173.11:06:45.13/onsource/TRACKING 2006.173.11:06:45.13/wx/22.49,1004.1,92 2006.173.11:06:45.28/cable/+6.5025E-03 2006.173.11:06:46.37/va/01,07,usb,yes,34,37 2006.173.11:06:46.37/va/02,06,usb,yes,34,35 2006.173.11:06:46.37/va/03,05,usb,yes,43,45 2006.173.11:06:46.37/va/04,06,usb,yes,34,36 2006.173.11:06:46.37/va/05,04,usb,yes,27,27 2006.173.11:06:46.37/va/06,03,usb,yes,38,38 2006.173.11:06:46.37/va/07,04,usb,yes,31,32 2006.173.11:06:46.37/va/08,04,usb,yes,26,32 2006.173.11:06:46.60/valo/01,524.99,yes,locked 2006.173.11:06:46.60/valo/02,534.99,yes,locked 2006.173.11:06:46.60/valo/03,564.99,yes,locked 2006.173.11:06:46.60/valo/04,624.99,yes,locked 2006.173.11:06:46.60/valo/05,734.99,yes,locked 2006.173.11:06:46.60/valo/06,814.99,yes,locked 2006.173.11:06:46.60/valo/07,864.99,yes,locked 2006.173.11:06:46.60/valo/08,884.99,yes,locked 2006.173.11:06:47.69/vb/01,04,usb,yes,28,26 2006.173.11:06:47.69/vb/02,04,usb,yes,31,31 2006.173.11:06:47.69/vb/03,04,usb,yes,28,31 2006.173.11:06:47.69/vb/04,04,usb,yes,32,31 2006.173.11:06:47.69/vb/05,04,usb,yes,25,27 2006.173.11:06:47.69/vb/06,04,usb,yes,29,25 2006.173.11:06:47.69/vb/07,04,usb,yes,29,29 2006.173.11:06:47.69/vb/08,04,usb,yes,26,30 2006.173.11:06:47.92/vblo/01,629.99,yes,locked 2006.173.11:06:47.92/vblo/02,634.99,yes,locked 2006.173.11:06:47.92/vblo/03,649.99,yes,locked 2006.173.11:06:47.92/vblo/04,679.99,yes,locked 2006.173.11:06:47.92/vblo/05,709.99,yes,locked 2006.173.11:06:47.92/vblo/06,719.99,yes,locked 2006.173.11:06:47.92/vblo/07,734.99,yes,locked 2006.173.11:06:47.92/vblo/08,744.99,yes,locked 2006.173.11:06:48.07/vabw/8 2006.173.11:06:48.22/vbbw/8 2006.173.11:06:48.31/xfe/off,on,14.7 2006.173.11:06:48.69/ifatt/23,28,28,28 2006.173.11:06:49.07/fmout-gps/S +4.00E-07 2006.173.11:06:49.12:!2006.173.11:12:44 2006.173.11:12:44.00:data_valid=off 2006.173.11:12:44.00:"et 2006.173.11:12:44.00:!+3s 2006.173.11:12:47.01:"tape 2006.173.11:12:47.01:postob 2006.173.11:12:47.20/cable/+6.5026E-03 2006.173.11:12:47.20/wx/22.47,1004.3,92 2006.173.11:12:48.08/fmout-gps/S +4.01E-07 2006.173.11:12:48.08:scan_name=173-1118,jd0606,340 2006.173.11:12:48.08:source=oq208,140700.39,282714.7,2000.0,cw 2006.173.11:12:48.14#flagr#flagr/antenna,new-source 2006.173.11:12:49.14:checkk5 2006.173.11:12:49.55/chk_autoobs//k5ts1/ autoobs is running! 2006.173.11:12:49.96/chk_autoobs//k5ts2/ autoobs is running! 2006.173.11:12:50.37/chk_autoobs//k5ts3/ autoobs is running! 2006.173.11:12:50.77/chk_autoobs//k5ts4/ autoobs is running! 2006.173.11:12:51.15/chk_obsdata//k5ts1/T1731106??a.dat file size is correct (nominal:1440MB, actual:1436MB). 2006.173.11:12:51.55/chk_obsdata//k5ts2/T1731106??b.dat file size is correct (nominal:1440MB, actual:1436MB). 2006.173.11:12:51.93/chk_obsdata//k5ts3/T1731106??c.dat file size is correct (nominal:1440MB, actual:1436MB). 2006.173.11:12:52.35/chk_obsdata//k5ts4/T1731106??d.dat file size is correct (nominal:1440MB, actual:1436MB). 2006.173.11:12:53.09/k5log//k5ts1_log_newline 2006.173.11:12:53.82/k5log//k5ts2_log_newline 2006.173.11:12:54.53/k5log//k5ts3_log_newline 2006.173.11:12:55.24/k5log//k5ts4_log_newline 2006.173.11:12:55.26/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.11:12:55.26:setupk4=1 2006.173.11:12:55.26$setupk4/echo=on 2006.173.11:12:55.26$setupk4/pcalon 2006.173.11:12:55.26$pcalon/"no phase cal control is implemented here 2006.173.11:12:55.26$setupk4/"tpicd=stop 2006.173.11:12:55.26$setupk4/"rec=synch_on 2006.173.11:12:55.26$setupk4/"rec_mode=128 2006.173.11:12:55.26$setupk4/!* 2006.173.11:12:55.26$setupk4/recpk4 2006.173.11:12:55.26$recpk4/recpatch= 2006.173.11:12:55.27$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.11:12:55.27$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.11:12:55.27$setupk4/vck44 2006.173.11:12:55.27$vck44/valo=1,524.99 2006.173.11:12:55.27#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.11:12:55.27#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.11:12:55.27#ibcon#ireg 17 cls_cnt 0 2006.173.11:12:55.27#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.11:12:55.27#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.11:12:55.27#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.11:12:55.27#ibcon#enter wrdev, iclass 24, count 0 2006.173.11:12:55.27#ibcon#first serial, iclass 24, count 0 2006.173.11:12:55.27#ibcon#enter sib2, iclass 24, count 0 2006.173.11:12:55.27#ibcon#flushed, iclass 24, count 0 2006.173.11:12:55.27#ibcon#about to write, iclass 24, count 0 2006.173.11:12:55.27#ibcon#wrote, iclass 24, count 0 2006.173.11:12:55.27#ibcon#about to read 3, iclass 24, count 0 2006.173.11:12:55.28#ibcon#read 3, iclass 24, count 0 2006.173.11:12:55.28#ibcon#about to read 4, iclass 24, count 0 2006.173.11:12:55.28#ibcon#read 4, iclass 24, count 0 2006.173.11:12:55.28#ibcon#about to read 5, iclass 24, count 0 2006.173.11:12:55.28#ibcon#read 5, iclass 24, count 0 2006.173.11:12:55.28#ibcon#about to read 6, iclass 24, count 0 2006.173.11:12:55.28#ibcon#read 6, iclass 24, count 0 2006.173.11:12:55.28#ibcon#end of sib2, iclass 24, count 0 2006.173.11:12:55.28#ibcon#*mode == 0, iclass 24, count 0 2006.173.11:12:55.28#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.11:12:55.28#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.11:12:55.28#ibcon#*before write, iclass 24, count 0 2006.173.11:12:55.28#ibcon#enter sib2, iclass 24, count 0 2006.173.11:12:55.28#ibcon#flushed, iclass 24, count 0 2006.173.11:12:55.28#ibcon#about to write, iclass 24, count 0 2006.173.11:12:55.28#ibcon#wrote, iclass 24, count 0 2006.173.11:12:55.28#ibcon#about to read 3, iclass 24, count 0 2006.173.11:12:55.33#ibcon#read 3, iclass 24, count 0 2006.173.11:12:55.33#ibcon#about to read 4, iclass 24, count 0 2006.173.11:12:55.33#ibcon#read 4, iclass 24, count 0 2006.173.11:12:55.33#ibcon#about to read 5, iclass 24, count 0 2006.173.11:12:55.33#ibcon#read 5, iclass 24, count 0 2006.173.11:12:55.33#ibcon#about to read 6, iclass 24, count 0 2006.173.11:12:55.33#ibcon#read 6, iclass 24, count 0 2006.173.11:12:55.33#ibcon#end of sib2, iclass 24, count 0 2006.173.11:12:55.33#ibcon#*after write, iclass 24, count 0 2006.173.11:12:55.33#ibcon#*before return 0, iclass 24, count 0 2006.173.11:12:55.33#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.11:12:55.33#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.11:12:55.33#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.11:12:55.33#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.11:12:55.33$vck44/va=1,7 2006.173.11:12:55.33#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.11:12:55.33#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.11:12:55.33#ibcon#ireg 11 cls_cnt 2 2006.173.11:12:55.33#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.11:12:55.33#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.11:12:55.33#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.11:12:55.33#ibcon#enter wrdev, iclass 26, count 2 2006.173.11:12:55.33#ibcon#first serial, iclass 26, count 2 2006.173.11:12:55.33#ibcon#enter sib2, iclass 26, count 2 2006.173.11:12:55.33#ibcon#flushed, iclass 26, count 2 2006.173.11:12:55.33#ibcon#about to write, iclass 26, count 2 2006.173.11:12:55.33#ibcon#wrote, iclass 26, count 2 2006.173.11:12:55.33#ibcon#about to read 3, iclass 26, count 2 2006.173.11:12:55.35#ibcon#read 3, iclass 26, count 2 2006.173.11:12:55.35#ibcon#about to read 4, iclass 26, count 2 2006.173.11:12:55.35#ibcon#read 4, iclass 26, count 2 2006.173.11:12:55.35#ibcon#about to read 5, iclass 26, count 2 2006.173.11:12:55.35#ibcon#read 5, iclass 26, count 2 2006.173.11:12:55.35#ibcon#about to read 6, iclass 26, count 2 2006.173.11:12:55.35#ibcon#read 6, iclass 26, count 2 2006.173.11:12:55.35#ibcon#end of sib2, iclass 26, count 2 2006.173.11:12:55.35#ibcon#*mode == 0, iclass 26, count 2 2006.173.11:12:55.35#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.11:12:55.35#ibcon#[25=AT01-07\r\n] 2006.173.11:12:55.35#ibcon#*before write, iclass 26, count 2 2006.173.11:12:55.35#ibcon#enter sib2, iclass 26, count 2 2006.173.11:12:55.35#ibcon#flushed, iclass 26, count 2 2006.173.11:12:55.35#ibcon#about to write, iclass 26, count 2 2006.173.11:12:55.35#ibcon#wrote, iclass 26, count 2 2006.173.11:12:55.35#ibcon#about to read 3, iclass 26, count 2 2006.173.11:12:55.38#ibcon#read 3, iclass 26, count 2 2006.173.11:12:55.38#ibcon#about to read 4, iclass 26, count 2 2006.173.11:12:55.38#ibcon#read 4, iclass 26, count 2 2006.173.11:12:55.38#ibcon#about to read 5, iclass 26, count 2 2006.173.11:12:55.38#ibcon#read 5, iclass 26, count 2 2006.173.11:12:55.38#ibcon#about to read 6, iclass 26, count 2 2006.173.11:12:55.38#ibcon#read 6, iclass 26, count 2 2006.173.11:12:55.38#ibcon#end of sib2, iclass 26, count 2 2006.173.11:12:55.38#ibcon#*after write, iclass 26, count 2 2006.173.11:12:55.38#ibcon#*before return 0, iclass 26, count 2 2006.173.11:12:55.38#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.11:12:55.38#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.11:12:55.38#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.11:12:55.38#ibcon#ireg 7 cls_cnt 0 2006.173.11:12:55.38#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.11:12:55.50#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.11:12:55.50#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.11:12:55.50#ibcon#enter wrdev, iclass 26, count 0 2006.173.11:12:55.50#ibcon#first serial, iclass 26, count 0 2006.173.11:12:55.50#ibcon#enter sib2, iclass 26, count 0 2006.173.11:12:55.50#ibcon#flushed, iclass 26, count 0 2006.173.11:12:55.50#ibcon#about to write, iclass 26, count 0 2006.173.11:12:55.50#ibcon#wrote, iclass 26, count 0 2006.173.11:12:55.50#ibcon#about to read 3, iclass 26, count 0 2006.173.11:12:55.52#ibcon#read 3, iclass 26, count 0 2006.173.11:12:55.52#ibcon#about to read 4, iclass 26, count 0 2006.173.11:12:55.52#ibcon#read 4, iclass 26, count 0 2006.173.11:12:55.52#ibcon#about to read 5, iclass 26, count 0 2006.173.11:12:55.52#ibcon#read 5, iclass 26, count 0 2006.173.11:12:55.52#ibcon#about to read 6, iclass 26, count 0 2006.173.11:12:55.52#ibcon#read 6, iclass 26, count 0 2006.173.11:12:55.52#ibcon#end of sib2, iclass 26, count 0 2006.173.11:12:55.52#ibcon#*mode == 0, iclass 26, count 0 2006.173.11:12:55.52#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.11:12:55.52#ibcon#[25=USB\r\n] 2006.173.11:12:55.52#ibcon#*before write, iclass 26, count 0 2006.173.11:12:55.52#ibcon#enter sib2, iclass 26, count 0 2006.173.11:12:55.52#ibcon#flushed, iclass 26, count 0 2006.173.11:12:55.52#ibcon#about to write, iclass 26, count 0 2006.173.11:12:55.52#ibcon#wrote, iclass 26, count 0 2006.173.11:12:55.52#ibcon#about to read 3, iclass 26, count 0 2006.173.11:12:55.55#ibcon#read 3, iclass 26, count 0 2006.173.11:12:55.55#ibcon#about to read 4, iclass 26, count 0 2006.173.11:12:55.55#ibcon#read 4, iclass 26, count 0 2006.173.11:12:55.55#ibcon#about to read 5, iclass 26, count 0 2006.173.11:12:55.55#ibcon#read 5, iclass 26, count 0 2006.173.11:12:55.55#ibcon#about to read 6, iclass 26, count 0 2006.173.11:12:55.55#ibcon#read 6, iclass 26, count 0 2006.173.11:12:55.55#ibcon#end of sib2, iclass 26, count 0 2006.173.11:12:55.55#ibcon#*after write, iclass 26, count 0 2006.173.11:12:55.55#ibcon#*before return 0, iclass 26, count 0 2006.173.11:12:55.55#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.11:12:55.55#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.11:12:55.55#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.11:12:55.55#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.11:12:55.55$vck44/valo=2,534.99 2006.173.11:12:55.55#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.11:12:55.55#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.11:12:55.55#ibcon#ireg 17 cls_cnt 0 2006.173.11:12:55.55#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.11:12:55.55#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.11:12:55.55#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.11:12:55.55#ibcon#enter wrdev, iclass 28, count 0 2006.173.11:12:55.55#ibcon#first serial, iclass 28, count 0 2006.173.11:12:55.55#ibcon#enter sib2, iclass 28, count 0 2006.173.11:12:55.55#ibcon#flushed, iclass 28, count 0 2006.173.11:12:55.55#ibcon#about to write, iclass 28, count 0 2006.173.11:12:55.55#ibcon#wrote, iclass 28, count 0 2006.173.11:12:55.55#ibcon#about to read 3, iclass 28, count 0 2006.173.11:12:55.57#ibcon#read 3, iclass 28, count 0 2006.173.11:12:55.57#ibcon#about to read 4, iclass 28, count 0 2006.173.11:12:55.57#ibcon#read 4, iclass 28, count 0 2006.173.11:12:55.57#ibcon#about to read 5, iclass 28, count 0 2006.173.11:12:55.57#ibcon#read 5, iclass 28, count 0 2006.173.11:12:55.57#ibcon#about to read 6, iclass 28, count 0 2006.173.11:12:55.57#ibcon#read 6, iclass 28, count 0 2006.173.11:12:55.57#ibcon#end of sib2, iclass 28, count 0 2006.173.11:12:55.57#ibcon#*mode == 0, iclass 28, count 0 2006.173.11:12:55.57#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.11:12:55.57#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.11:12:55.57#ibcon#*before write, iclass 28, count 0 2006.173.11:12:55.57#ibcon#enter sib2, iclass 28, count 0 2006.173.11:12:55.57#ibcon#flushed, iclass 28, count 0 2006.173.11:12:55.57#ibcon#about to write, iclass 28, count 0 2006.173.11:12:55.57#ibcon#wrote, iclass 28, count 0 2006.173.11:12:55.57#ibcon#about to read 3, iclass 28, count 0 2006.173.11:12:55.61#ibcon#read 3, iclass 28, count 0 2006.173.11:12:55.61#ibcon#about to read 4, iclass 28, count 0 2006.173.11:12:55.61#ibcon#read 4, iclass 28, count 0 2006.173.11:12:55.61#ibcon#about to read 5, iclass 28, count 0 2006.173.11:12:55.61#ibcon#read 5, iclass 28, count 0 2006.173.11:12:55.61#ibcon#about to read 6, iclass 28, count 0 2006.173.11:12:55.61#ibcon#read 6, iclass 28, count 0 2006.173.11:12:55.61#ibcon#end of sib2, iclass 28, count 0 2006.173.11:12:55.61#ibcon#*after write, iclass 28, count 0 2006.173.11:12:55.61#ibcon#*before return 0, iclass 28, count 0 2006.173.11:12:55.61#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.11:12:55.61#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.11:12:55.61#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.11:12:55.61#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.11:12:55.61$vck44/va=2,6 2006.173.11:12:55.61#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.11:12:55.61#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.11:12:55.61#ibcon#ireg 11 cls_cnt 2 2006.173.11:12:55.61#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.11:12:55.67#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.11:12:55.67#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.11:12:55.67#ibcon#enter wrdev, iclass 30, count 2 2006.173.11:12:55.67#ibcon#first serial, iclass 30, count 2 2006.173.11:12:55.67#ibcon#enter sib2, iclass 30, count 2 2006.173.11:12:55.67#ibcon#flushed, iclass 30, count 2 2006.173.11:12:55.67#ibcon#about to write, iclass 30, count 2 2006.173.11:12:55.67#ibcon#wrote, iclass 30, count 2 2006.173.11:12:55.67#ibcon#about to read 3, iclass 30, count 2 2006.173.11:12:55.69#ibcon#read 3, iclass 30, count 2 2006.173.11:12:55.69#ibcon#about to read 4, iclass 30, count 2 2006.173.11:12:55.69#ibcon#read 4, iclass 30, count 2 2006.173.11:12:55.69#ibcon#about to read 5, iclass 30, count 2 2006.173.11:12:55.69#ibcon#read 5, iclass 30, count 2 2006.173.11:12:55.69#ibcon#about to read 6, iclass 30, count 2 2006.173.11:12:55.69#ibcon#read 6, iclass 30, count 2 2006.173.11:12:55.69#ibcon#end of sib2, iclass 30, count 2 2006.173.11:12:55.69#ibcon#*mode == 0, iclass 30, count 2 2006.173.11:12:55.69#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.11:12:55.69#ibcon#[25=AT02-06\r\n] 2006.173.11:12:55.69#ibcon#*before write, iclass 30, count 2 2006.173.11:12:55.69#ibcon#enter sib2, iclass 30, count 2 2006.173.11:12:55.69#ibcon#flushed, iclass 30, count 2 2006.173.11:12:55.69#ibcon#about to write, iclass 30, count 2 2006.173.11:12:55.69#ibcon#wrote, iclass 30, count 2 2006.173.11:12:55.69#ibcon#about to read 3, iclass 30, count 2 2006.173.11:12:55.72#ibcon#read 3, iclass 30, count 2 2006.173.11:12:55.72#ibcon#about to read 4, iclass 30, count 2 2006.173.11:12:55.72#ibcon#read 4, iclass 30, count 2 2006.173.11:12:55.72#ibcon#about to read 5, iclass 30, count 2 2006.173.11:12:55.72#ibcon#read 5, iclass 30, count 2 2006.173.11:12:55.72#ibcon#about to read 6, iclass 30, count 2 2006.173.11:12:55.72#ibcon#read 6, iclass 30, count 2 2006.173.11:12:55.72#ibcon#end of sib2, iclass 30, count 2 2006.173.11:12:55.72#ibcon#*after write, iclass 30, count 2 2006.173.11:12:55.72#ibcon#*before return 0, iclass 30, count 2 2006.173.11:12:55.72#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.11:12:55.72#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.11:12:55.72#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.11:12:55.72#ibcon#ireg 7 cls_cnt 0 2006.173.11:12:55.72#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.11:12:55.84#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.11:12:55.84#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.11:12:55.84#ibcon#enter wrdev, iclass 30, count 0 2006.173.11:12:55.84#ibcon#first serial, iclass 30, count 0 2006.173.11:12:55.84#ibcon#enter sib2, iclass 30, count 0 2006.173.11:12:55.84#ibcon#flushed, iclass 30, count 0 2006.173.11:12:55.84#ibcon#about to write, iclass 30, count 0 2006.173.11:12:55.84#ibcon#wrote, iclass 30, count 0 2006.173.11:12:55.84#ibcon#about to read 3, iclass 30, count 0 2006.173.11:12:55.86#ibcon#read 3, iclass 30, count 0 2006.173.11:12:55.86#ibcon#about to read 4, iclass 30, count 0 2006.173.11:12:55.86#ibcon#read 4, iclass 30, count 0 2006.173.11:12:55.86#ibcon#about to read 5, iclass 30, count 0 2006.173.11:12:55.86#ibcon#read 5, iclass 30, count 0 2006.173.11:12:55.86#ibcon#about to read 6, iclass 30, count 0 2006.173.11:12:55.86#ibcon#read 6, iclass 30, count 0 2006.173.11:12:55.86#ibcon#end of sib2, iclass 30, count 0 2006.173.11:12:55.86#ibcon#*mode == 0, iclass 30, count 0 2006.173.11:12:55.86#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.11:12:55.86#ibcon#[25=USB\r\n] 2006.173.11:12:55.86#ibcon#*before write, iclass 30, count 0 2006.173.11:12:55.86#ibcon#enter sib2, iclass 30, count 0 2006.173.11:12:55.86#ibcon#flushed, iclass 30, count 0 2006.173.11:12:55.86#ibcon#about to write, iclass 30, count 0 2006.173.11:12:55.86#ibcon#wrote, iclass 30, count 0 2006.173.11:12:55.86#ibcon#about to read 3, iclass 30, count 0 2006.173.11:12:55.89#ibcon#read 3, iclass 30, count 0 2006.173.11:12:55.89#ibcon#about to read 4, iclass 30, count 0 2006.173.11:12:55.89#ibcon#read 4, iclass 30, count 0 2006.173.11:12:55.89#ibcon#about to read 5, iclass 30, count 0 2006.173.11:12:55.89#ibcon#read 5, iclass 30, count 0 2006.173.11:12:55.89#ibcon#about to read 6, iclass 30, count 0 2006.173.11:12:55.89#ibcon#read 6, iclass 30, count 0 2006.173.11:12:55.89#ibcon#end of sib2, iclass 30, count 0 2006.173.11:12:55.89#ibcon#*after write, iclass 30, count 0 2006.173.11:12:55.89#ibcon#*before return 0, iclass 30, count 0 2006.173.11:12:55.89#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.11:12:55.89#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.11:12:55.89#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.11:12:55.89#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.11:12:55.89$vck44/valo=3,564.99 2006.173.11:12:55.89#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.11:12:55.89#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.11:12:55.89#ibcon#ireg 17 cls_cnt 0 2006.173.11:12:55.89#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.11:12:55.89#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.11:12:55.89#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.11:12:55.89#ibcon#enter wrdev, iclass 32, count 0 2006.173.11:12:55.89#ibcon#first serial, iclass 32, count 0 2006.173.11:12:55.89#ibcon#enter sib2, iclass 32, count 0 2006.173.11:12:55.89#ibcon#flushed, iclass 32, count 0 2006.173.11:12:55.89#ibcon#about to write, iclass 32, count 0 2006.173.11:12:55.89#ibcon#wrote, iclass 32, count 0 2006.173.11:12:55.89#ibcon#about to read 3, iclass 32, count 0 2006.173.11:12:55.91#ibcon#read 3, iclass 32, count 0 2006.173.11:12:55.91#ibcon#about to read 4, iclass 32, count 0 2006.173.11:12:55.91#ibcon#read 4, iclass 32, count 0 2006.173.11:12:55.91#ibcon#about to read 5, iclass 32, count 0 2006.173.11:12:55.91#ibcon#read 5, iclass 32, count 0 2006.173.11:12:55.91#ibcon#about to read 6, iclass 32, count 0 2006.173.11:12:55.91#ibcon#read 6, iclass 32, count 0 2006.173.11:12:55.91#ibcon#end of sib2, iclass 32, count 0 2006.173.11:12:55.91#ibcon#*mode == 0, iclass 32, count 0 2006.173.11:12:55.91#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.11:12:55.91#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.11:12:55.91#ibcon#*before write, iclass 32, count 0 2006.173.11:12:55.91#ibcon#enter sib2, iclass 32, count 0 2006.173.11:12:55.91#ibcon#flushed, iclass 32, count 0 2006.173.11:12:55.91#ibcon#about to write, iclass 32, count 0 2006.173.11:12:55.91#ibcon#wrote, iclass 32, count 0 2006.173.11:12:55.91#ibcon#about to read 3, iclass 32, count 0 2006.173.11:12:55.95#ibcon#read 3, iclass 32, count 0 2006.173.11:12:55.95#ibcon#about to read 4, iclass 32, count 0 2006.173.11:12:55.95#ibcon#read 4, iclass 32, count 0 2006.173.11:12:55.95#ibcon#about to read 5, iclass 32, count 0 2006.173.11:12:55.95#ibcon#read 5, iclass 32, count 0 2006.173.11:12:55.95#ibcon#about to read 6, iclass 32, count 0 2006.173.11:12:55.95#ibcon#read 6, iclass 32, count 0 2006.173.11:12:55.95#ibcon#end of sib2, iclass 32, count 0 2006.173.11:12:55.95#ibcon#*after write, iclass 32, count 0 2006.173.11:12:55.95#ibcon#*before return 0, iclass 32, count 0 2006.173.11:12:55.95#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.11:12:55.95#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.11:12:55.95#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.11:12:55.95#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.11:12:55.95$vck44/va=3,5 2006.173.11:12:55.95#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.11:12:55.95#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.11:12:55.95#ibcon#ireg 11 cls_cnt 2 2006.173.11:12:55.95#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.11:12:56.01#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.11:12:56.01#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.11:12:56.01#ibcon#enter wrdev, iclass 34, count 2 2006.173.11:12:56.01#ibcon#first serial, iclass 34, count 2 2006.173.11:12:56.01#ibcon#enter sib2, iclass 34, count 2 2006.173.11:12:56.01#ibcon#flushed, iclass 34, count 2 2006.173.11:12:56.01#ibcon#about to write, iclass 34, count 2 2006.173.11:12:56.01#ibcon#wrote, iclass 34, count 2 2006.173.11:12:56.01#ibcon#about to read 3, iclass 34, count 2 2006.173.11:12:56.03#ibcon#read 3, iclass 34, count 2 2006.173.11:12:56.03#ibcon#about to read 4, iclass 34, count 2 2006.173.11:12:56.03#ibcon#read 4, iclass 34, count 2 2006.173.11:12:56.03#ibcon#about to read 5, iclass 34, count 2 2006.173.11:12:56.03#ibcon#read 5, iclass 34, count 2 2006.173.11:12:56.03#ibcon#about to read 6, iclass 34, count 2 2006.173.11:12:56.03#ibcon#read 6, iclass 34, count 2 2006.173.11:12:56.03#ibcon#end of sib2, iclass 34, count 2 2006.173.11:12:56.03#ibcon#*mode == 0, iclass 34, count 2 2006.173.11:12:56.03#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.11:12:56.03#ibcon#[25=AT03-05\r\n] 2006.173.11:12:56.03#ibcon#*before write, iclass 34, count 2 2006.173.11:12:56.03#ibcon#enter sib2, iclass 34, count 2 2006.173.11:12:56.03#ibcon#flushed, iclass 34, count 2 2006.173.11:12:56.03#ibcon#about to write, iclass 34, count 2 2006.173.11:12:56.03#ibcon#wrote, iclass 34, count 2 2006.173.11:12:56.03#ibcon#about to read 3, iclass 34, count 2 2006.173.11:12:56.06#ibcon#read 3, iclass 34, count 2 2006.173.11:12:56.06#ibcon#about to read 4, iclass 34, count 2 2006.173.11:12:56.06#ibcon#read 4, iclass 34, count 2 2006.173.11:12:56.06#ibcon#about to read 5, iclass 34, count 2 2006.173.11:12:56.06#ibcon#read 5, iclass 34, count 2 2006.173.11:12:56.06#ibcon#about to read 6, iclass 34, count 2 2006.173.11:12:56.06#ibcon#read 6, iclass 34, count 2 2006.173.11:12:56.06#ibcon#end of sib2, iclass 34, count 2 2006.173.11:12:56.06#ibcon#*after write, iclass 34, count 2 2006.173.11:12:56.06#ibcon#*before return 0, iclass 34, count 2 2006.173.11:12:56.06#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.11:12:56.06#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.11:12:56.06#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.11:12:56.06#ibcon#ireg 7 cls_cnt 0 2006.173.11:12:56.06#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.11:12:56.18#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.11:12:56.18#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.11:12:56.18#ibcon#enter wrdev, iclass 34, count 0 2006.173.11:12:56.18#ibcon#first serial, iclass 34, count 0 2006.173.11:12:56.18#ibcon#enter sib2, iclass 34, count 0 2006.173.11:12:56.18#ibcon#flushed, iclass 34, count 0 2006.173.11:12:56.18#ibcon#about to write, iclass 34, count 0 2006.173.11:12:56.18#ibcon#wrote, iclass 34, count 0 2006.173.11:12:56.18#ibcon#about to read 3, iclass 34, count 0 2006.173.11:12:56.20#ibcon#read 3, iclass 34, count 0 2006.173.11:12:56.20#ibcon#about to read 4, iclass 34, count 0 2006.173.11:12:56.20#ibcon#read 4, iclass 34, count 0 2006.173.11:12:56.20#ibcon#about to read 5, iclass 34, count 0 2006.173.11:12:56.20#ibcon#read 5, iclass 34, count 0 2006.173.11:12:56.20#ibcon#about to read 6, iclass 34, count 0 2006.173.11:12:56.20#ibcon#read 6, iclass 34, count 0 2006.173.11:12:56.20#ibcon#end of sib2, iclass 34, count 0 2006.173.11:12:56.20#ibcon#*mode == 0, iclass 34, count 0 2006.173.11:12:56.20#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.11:12:56.20#ibcon#[25=USB\r\n] 2006.173.11:12:56.20#ibcon#*before write, iclass 34, count 0 2006.173.11:12:56.20#ibcon#enter sib2, iclass 34, count 0 2006.173.11:12:56.20#ibcon#flushed, iclass 34, count 0 2006.173.11:12:56.20#ibcon#about to write, iclass 34, count 0 2006.173.11:12:56.20#ibcon#wrote, iclass 34, count 0 2006.173.11:12:56.20#ibcon#about to read 3, iclass 34, count 0 2006.173.11:12:56.23#ibcon#read 3, iclass 34, count 0 2006.173.11:12:56.23#ibcon#about to read 4, iclass 34, count 0 2006.173.11:12:56.23#ibcon#read 4, iclass 34, count 0 2006.173.11:12:56.23#ibcon#about to read 5, iclass 34, count 0 2006.173.11:12:56.23#ibcon#read 5, iclass 34, count 0 2006.173.11:12:56.23#ibcon#about to read 6, iclass 34, count 0 2006.173.11:12:56.23#ibcon#read 6, iclass 34, count 0 2006.173.11:12:56.23#ibcon#end of sib2, iclass 34, count 0 2006.173.11:12:56.23#ibcon#*after write, iclass 34, count 0 2006.173.11:12:56.23#ibcon#*before return 0, iclass 34, count 0 2006.173.11:12:56.23#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.11:12:56.23#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.11:12:56.23#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.11:12:56.23#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.11:12:56.23$vck44/valo=4,624.99 2006.173.11:12:56.23#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.11:12:56.23#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.11:12:56.23#ibcon#ireg 17 cls_cnt 0 2006.173.11:12:56.23#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.11:12:56.23#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.11:12:56.23#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.11:12:56.23#ibcon#enter wrdev, iclass 36, count 0 2006.173.11:12:56.23#ibcon#first serial, iclass 36, count 0 2006.173.11:12:56.23#ibcon#enter sib2, iclass 36, count 0 2006.173.11:12:56.23#ibcon#flushed, iclass 36, count 0 2006.173.11:12:56.23#ibcon#about to write, iclass 36, count 0 2006.173.11:12:56.23#ibcon#wrote, iclass 36, count 0 2006.173.11:12:56.23#ibcon#about to read 3, iclass 36, count 0 2006.173.11:12:56.25#ibcon#read 3, iclass 36, count 0 2006.173.11:12:56.25#ibcon#about to read 4, iclass 36, count 0 2006.173.11:12:56.25#ibcon#read 4, iclass 36, count 0 2006.173.11:12:56.25#ibcon#about to read 5, iclass 36, count 0 2006.173.11:12:56.25#ibcon#read 5, iclass 36, count 0 2006.173.11:12:56.25#ibcon#about to read 6, iclass 36, count 0 2006.173.11:12:56.25#ibcon#read 6, iclass 36, count 0 2006.173.11:12:56.25#ibcon#end of sib2, iclass 36, count 0 2006.173.11:12:56.25#ibcon#*mode == 0, iclass 36, count 0 2006.173.11:12:56.25#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.11:12:56.25#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.11:12:56.25#ibcon#*before write, iclass 36, count 0 2006.173.11:12:56.25#ibcon#enter sib2, iclass 36, count 0 2006.173.11:12:56.25#ibcon#flushed, iclass 36, count 0 2006.173.11:12:56.25#ibcon#about to write, iclass 36, count 0 2006.173.11:12:56.25#ibcon#wrote, iclass 36, count 0 2006.173.11:12:56.25#ibcon#about to read 3, iclass 36, count 0 2006.173.11:12:56.29#ibcon#read 3, iclass 36, count 0 2006.173.11:12:56.29#ibcon#about to read 4, iclass 36, count 0 2006.173.11:12:56.29#ibcon#read 4, iclass 36, count 0 2006.173.11:12:56.29#ibcon#about to read 5, iclass 36, count 0 2006.173.11:12:56.29#ibcon#read 5, iclass 36, count 0 2006.173.11:12:56.29#ibcon#about to read 6, iclass 36, count 0 2006.173.11:12:56.29#ibcon#read 6, iclass 36, count 0 2006.173.11:12:56.29#ibcon#end of sib2, iclass 36, count 0 2006.173.11:12:56.29#ibcon#*after write, iclass 36, count 0 2006.173.11:12:56.29#ibcon#*before return 0, iclass 36, count 0 2006.173.11:12:56.29#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.11:12:56.29#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.11:12:56.29#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.11:12:56.29#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.11:12:56.29$vck44/va=4,6 2006.173.11:12:56.29#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.11:12:56.29#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.11:12:56.29#ibcon#ireg 11 cls_cnt 2 2006.173.11:12:56.29#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.11:12:56.35#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.11:12:56.35#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.11:12:56.35#ibcon#enter wrdev, iclass 38, count 2 2006.173.11:12:56.35#ibcon#first serial, iclass 38, count 2 2006.173.11:12:56.35#ibcon#enter sib2, iclass 38, count 2 2006.173.11:12:56.35#ibcon#flushed, iclass 38, count 2 2006.173.11:12:56.35#ibcon#about to write, iclass 38, count 2 2006.173.11:12:56.35#ibcon#wrote, iclass 38, count 2 2006.173.11:12:56.35#ibcon#about to read 3, iclass 38, count 2 2006.173.11:12:56.37#ibcon#read 3, iclass 38, count 2 2006.173.11:12:56.37#ibcon#about to read 4, iclass 38, count 2 2006.173.11:12:56.37#ibcon#read 4, iclass 38, count 2 2006.173.11:12:56.37#ibcon#about to read 5, iclass 38, count 2 2006.173.11:12:56.37#ibcon#read 5, iclass 38, count 2 2006.173.11:12:56.37#ibcon#about to read 6, iclass 38, count 2 2006.173.11:12:56.37#ibcon#read 6, iclass 38, count 2 2006.173.11:12:56.37#ibcon#end of sib2, iclass 38, count 2 2006.173.11:12:56.37#ibcon#*mode == 0, iclass 38, count 2 2006.173.11:12:56.37#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.11:12:56.37#ibcon#[25=AT04-06\r\n] 2006.173.11:12:56.37#ibcon#*before write, iclass 38, count 2 2006.173.11:12:56.37#ibcon#enter sib2, iclass 38, count 2 2006.173.11:12:56.37#ibcon#flushed, iclass 38, count 2 2006.173.11:12:56.37#ibcon#about to write, iclass 38, count 2 2006.173.11:12:56.37#ibcon#wrote, iclass 38, count 2 2006.173.11:12:56.37#ibcon#about to read 3, iclass 38, count 2 2006.173.11:12:56.40#ibcon#read 3, iclass 38, count 2 2006.173.11:12:56.40#ibcon#about to read 4, iclass 38, count 2 2006.173.11:12:56.40#ibcon#read 4, iclass 38, count 2 2006.173.11:12:56.40#ibcon#about to read 5, iclass 38, count 2 2006.173.11:12:56.40#ibcon#read 5, iclass 38, count 2 2006.173.11:12:56.40#ibcon#about to read 6, iclass 38, count 2 2006.173.11:12:56.40#ibcon#read 6, iclass 38, count 2 2006.173.11:12:56.40#ibcon#end of sib2, iclass 38, count 2 2006.173.11:12:56.40#ibcon#*after write, iclass 38, count 2 2006.173.11:12:56.40#ibcon#*before return 0, iclass 38, count 2 2006.173.11:12:56.40#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.11:12:56.40#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.11:12:56.40#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.11:12:56.40#ibcon#ireg 7 cls_cnt 0 2006.173.11:12:56.40#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.11:12:56.52#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.11:12:56.52#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.11:12:56.52#ibcon#enter wrdev, iclass 38, count 0 2006.173.11:12:56.52#ibcon#first serial, iclass 38, count 0 2006.173.11:12:56.52#ibcon#enter sib2, iclass 38, count 0 2006.173.11:12:56.52#ibcon#flushed, iclass 38, count 0 2006.173.11:12:56.52#ibcon#about to write, iclass 38, count 0 2006.173.11:12:56.52#ibcon#wrote, iclass 38, count 0 2006.173.11:12:56.52#ibcon#about to read 3, iclass 38, count 0 2006.173.11:12:56.54#ibcon#read 3, iclass 38, count 0 2006.173.11:12:56.54#ibcon#about to read 4, iclass 38, count 0 2006.173.11:12:56.54#ibcon#read 4, iclass 38, count 0 2006.173.11:12:56.54#ibcon#about to read 5, iclass 38, count 0 2006.173.11:12:56.54#ibcon#read 5, iclass 38, count 0 2006.173.11:12:56.54#ibcon#about to read 6, iclass 38, count 0 2006.173.11:12:56.54#ibcon#read 6, iclass 38, count 0 2006.173.11:12:56.54#ibcon#end of sib2, iclass 38, count 0 2006.173.11:12:56.54#ibcon#*mode == 0, iclass 38, count 0 2006.173.11:12:56.54#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.11:12:56.54#ibcon#[25=USB\r\n] 2006.173.11:12:56.54#ibcon#*before write, iclass 38, count 0 2006.173.11:12:56.54#ibcon#enter sib2, iclass 38, count 0 2006.173.11:12:56.54#ibcon#flushed, iclass 38, count 0 2006.173.11:12:56.54#ibcon#about to write, iclass 38, count 0 2006.173.11:12:56.54#ibcon#wrote, iclass 38, count 0 2006.173.11:12:56.54#ibcon#about to read 3, iclass 38, count 0 2006.173.11:12:56.57#ibcon#read 3, iclass 38, count 0 2006.173.11:12:56.57#ibcon#about to read 4, iclass 38, count 0 2006.173.11:12:56.57#ibcon#read 4, iclass 38, count 0 2006.173.11:12:56.57#ibcon#about to read 5, iclass 38, count 0 2006.173.11:12:56.57#ibcon#read 5, iclass 38, count 0 2006.173.11:12:56.57#ibcon#about to read 6, iclass 38, count 0 2006.173.11:12:56.57#ibcon#read 6, iclass 38, count 0 2006.173.11:12:56.57#ibcon#end of sib2, iclass 38, count 0 2006.173.11:12:56.57#ibcon#*after write, iclass 38, count 0 2006.173.11:12:56.57#ibcon#*before return 0, iclass 38, count 0 2006.173.11:12:56.57#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.11:12:56.57#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.11:12:56.57#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.11:12:56.57#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.11:12:56.57$vck44/valo=5,734.99 2006.173.11:12:56.57#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.11:12:56.57#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.11:12:56.57#ibcon#ireg 17 cls_cnt 0 2006.173.11:12:56.57#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.11:12:56.57#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.11:12:56.57#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.11:12:56.57#ibcon#enter wrdev, iclass 40, count 0 2006.173.11:12:56.57#ibcon#first serial, iclass 40, count 0 2006.173.11:12:56.57#ibcon#enter sib2, iclass 40, count 0 2006.173.11:12:56.57#ibcon#flushed, iclass 40, count 0 2006.173.11:12:56.57#ibcon#about to write, iclass 40, count 0 2006.173.11:12:56.57#ibcon#wrote, iclass 40, count 0 2006.173.11:12:56.57#ibcon#about to read 3, iclass 40, count 0 2006.173.11:12:56.59#ibcon#read 3, iclass 40, count 0 2006.173.11:12:56.59#ibcon#about to read 4, iclass 40, count 0 2006.173.11:12:56.59#ibcon#read 4, iclass 40, count 0 2006.173.11:12:56.59#ibcon#about to read 5, iclass 40, count 0 2006.173.11:12:56.59#ibcon#read 5, iclass 40, count 0 2006.173.11:12:56.59#ibcon#about to read 6, iclass 40, count 0 2006.173.11:12:56.59#ibcon#read 6, iclass 40, count 0 2006.173.11:12:56.59#ibcon#end of sib2, iclass 40, count 0 2006.173.11:12:56.59#ibcon#*mode == 0, iclass 40, count 0 2006.173.11:12:56.59#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.11:12:56.59#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.11:12:56.59#ibcon#*before write, iclass 40, count 0 2006.173.11:12:56.59#ibcon#enter sib2, iclass 40, count 0 2006.173.11:12:56.59#ibcon#flushed, iclass 40, count 0 2006.173.11:12:56.59#ibcon#about to write, iclass 40, count 0 2006.173.11:12:56.59#ibcon#wrote, iclass 40, count 0 2006.173.11:12:56.59#ibcon#about to read 3, iclass 40, count 0 2006.173.11:12:56.63#ibcon#read 3, iclass 40, count 0 2006.173.11:12:56.63#ibcon#about to read 4, iclass 40, count 0 2006.173.11:12:56.63#ibcon#read 4, iclass 40, count 0 2006.173.11:12:56.63#ibcon#about to read 5, iclass 40, count 0 2006.173.11:12:56.63#ibcon#read 5, iclass 40, count 0 2006.173.11:12:56.63#ibcon#about to read 6, iclass 40, count 0 2006.173.11:12:56.63#ibcon#read 6, iclass 40, count 0 2006.173.11:12:56.63#ibcon#end of sib2, iclass 40, count 0 2006.173.11:12:56.63#ibcon#*after write, iclass 40, count 0 2006.173.11:12:56.63#ibcon#*before return 0, iclass 40, count 0 2006.173.11:12:56.63#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.11:12:56.63#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.11:12:56.63#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.11:12:56.63#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.11:12:56.63$vck44/va=5,4 2006.173.11:12:56.63#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.11:12:56.63#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.11:12:56.63#ibcon#ireg 11 cls_cnt 2 2006.173.11:12:56.63#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.11:12:56.69#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.11:12:56.69#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.11:12:56.69#ibcon#enter wrdev, iclass 4, count 2 2006.173.11:12:56.69#ibcon#first serial, iclass 4, count 2 2006.173.11:12:56.69#ibcon#enter sib2, iclass 4, count 2 2006.173.11:12:56.69#ibcon#flushed, iclass 4, count 2 2006.173.11:12:56.69#ibcon#about to write, iclass 4, count 2 2006.173.11:12:56.69#ibcon#wrote, iclass 4, count 2 2006.173.11:12:56.69#ibcon#about to read 3, iclass 4, count 2 2006.173.11:12:56.71#ibcon#read 3, iclass 4, count 2 2006.173.11:12:56.71#ibcon#about to read 4, iclass 4, count 2 2006.173.11:12:56.71#ibcon#read 4, iclass 4, count 2 2006.173.11:12:56.71#ibcon#about to read 5, iclass 4, count 2 2006.173.11:12:56.71#ibcon#read 5, iclass 4, count 2 2006.173.11:12:56.71#ibcon#about to read 6, iclass 4, count 2 2006.173.11:12:56.71#ibcon#read 6, iclass 4, count 2 2006.173.11:12:56.71#ibcon#end of sib2, iclass 4, count 2 2006.173.11:12:56.71#ibcon#*mode == 0, iclass 4, count 2 2006.173.11:12:56.71#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.11:12:56.71#ibcon#[25=AT05-04\r\n] 2006.173.11:12:56.71#ibcon#*before write, iclass 4, count 2 2006.173.11:12:56.71#ibcon#enter sib2, iclass 4, count 2 2006.173.11:12:56.71#ibcon#flushed, iclass 4, count 2 2006.173.11:12:56.71#ibcon#about to write, iclass 4, count 2 2006.173.11:12:56.71#ibcon#wrote, iclass 4, count 2 2006.173.11:12:56.71#ibcon#about to read 3, iclass 4, count 2 2006.173.11:12:56.74#ibcon#read 3, iclass 4, count 2 2006.173.11:12:56.74#ibcon#about to read 4, iclass 4, count 2 2006.173.11:12:56.74#ibcon#read 4, iclass 4, count 2 2006.173.11:12:56.74#ibcon#about to read 5, iclass 4, count 2 2006.173.11:12:56.74#ibcon#read 5, iclass 4, count 2 2006.173.11:12:56.74#ibcon#about to read 6, iclass 4, count 2 2006.173.11:12:56.74#ibcon#read 6, iclass 4, count 2 2006.173.11:12:56.74#ibcon#end of sib2, iclass 4, count 2 2006.173.11:12:56.74#ibcon#*after write, iclass 4, count 2 2006.173.11:12:56.74#ibcon#*before return 0, iclass 4, count 2 2006.173.11:12:56.74#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.11:12:56.74#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.11:12:56.74#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.11:12:56.74#ibcon#ireg 7 cls_cnt 0 2006.173.11:12:56.74#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.11:12:56.86#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.11:12:56.86#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.11:12:56.86#ibcon#enter wrdev, iclass 4, count 0 2006.173.11:12:56.86#ibcon#first serial, iclass 4, count 0 2006.173.11:12:56.86#ibcon#enter sib2, iclass 4, count 0 2006.173.11:12:56.86#ibcon#flushed, iclass 4, count 0 2006.173.11:12:56.86#ibcon#about to write, iclass 4, count 0 2006.173.11:12:56.86#ibcon#wrote, iclass 4, count 0 2006.173.11:12:56.86#ibcon#about to read 3, iclass 4, count 0 2006.173.11:12:56.88#ibcon#read 3, iclass 4, count 0 2006.173.11:12:56.88#ibcon#about to read 4, iclass 4, count 0 2006.173.11:12:56.88#ibcon#read 4, iclass 4, count 0 2006.173.11:12:56.88#ibcon#about to read 5, iclass 4, count 0 2006.173.11:12:56.88#ibcon#read 5, iclass 4, count 0 2006.173.11:12:56.88#ibcon#about to read 6, iclass 4, count 0 2006.173.11:12:56.88#ibcon#read 6, iclass 4, count 0 2006.173.11:12:56.88#ibcon#end of sib2, iclass 4, count 0 2006.173.11:12:56.88#ibcon#*mode == 0, iclass 4, count 0 2006.173.11:12:56.88#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.11:12:56.88#ibcon#[25=USB\r\n] 2006.173.11:12:56.88#ibcon#*before write, iclass 4, count 0 2006.173.11:12:56.88#ibcon#enter sib2, iclass 4, count 0 2006.173.11:12:56.88#ibcon#flushed, iclass 4, count 0 2006.173.11:12:56.88#ibcon#about to write, iclass 4, count 0 2006.173.11:12:56.88#ibcon#wrote, iclass 4, count 0 2006.173.11:12:56.88#ibcon#about to read 3, iclass 4, count 0 2006.173.11:12:56.91#ibcon#read 3, iclass 4, count 0 2006.173.11:12:56.91#ibcon#about to read 4, iclass 4, count 0 2006.173.11:12:56.91#ibcon#read 4, iclass 4, count 0 2006.173.11:12:56.91#ibcon#about to read 5, iclass 4, count 0 2006.173.11:12:56.91#ibcon#read 5, iclass 4, count 0 2006.173.11:12:56.91#ibcon#about to read 6, iclass 4, count 0 2006.173.11:12:56.91#ibcon#read 6, iclass 4, count 0 2006.173.11:12:56.91#ibcon#end of sib2, iclass 4, count 0 2006.173.11:12:56.91#ibcon#*after write, iclass 4, count 0 2006.173.11:12:56.91#ibcon#*before return 0, iclass 4, count 0 2006.173.11:12:56.91#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.11:12:56.91#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.11:12:56.91#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.11:12:56.91#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.11:12:56.91$vck44/valo=6,814.99 2006.173.11:12:56.91#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.11:12:56.91#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.11:12:56.91#ibcon#ireg 17 cls_cnt 0 2006.173.11:12:56.91#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.11:12:56.91#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.11:12:56.91#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.11:12:56.91#ibcon#enter wrdev, iclass 6, count 0 2006.173.11:12:56.91#ibcon#first serial, iclass 6, count 0 2006.173.11:12:56.91#ibcon#enter sib2, iclass 6, count 0 2006.173.11:12:56.91#ibcon#flushed, iclass 6, count 0 2006.173.11:12:56.91#ibcon#about to write, iclass 6, count 0 2006.173.11:12:56.91#ibcon#wrote, iclass 6, count 0 2006.173.11:12:56.91#ibcon#about to read 3, iclass 6, count 0 2006.173.11:12:56.93#ibcon#read 3, iclass 6, count 0 2006.173.11:12:56.93#ibcon#about to read 4, iclass 6, count 0 2006.173.11:12:56.93#ibcon#read 4, iclass 6, count 0 2006.173.11:12:56.93#ibcon#about to read 5, iclass 6, count 0 2006.173.11:12:56.93#ibcon#read 5, iclass 6, count 0 2006.173.11:12:56.93#ibcon#about to read 6, iclass 6, count 0 2006.173.11:12:56.93#ibcon#read 6, iclass 6, count 0 2006.173.11:12:56.93#ibcon#end of sib2, iclass 6, count 0 2006.173.11:12:56.93#ibcon#*mode == 0, iclass 6, count 0 2006.173.11:12:56.93#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.11:12:56.93#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.11:12:56.93#ibcon#*before write, iclass 6, count 0 2006.173.11:12:56.93#ibcon#enter sib2, iclass 6, count 0 2006.173.11:12:56.93#ibcon#flushed, iclass 6, count 0 2006.173.11:12:56.93#ibcon#about to write, iclass 6, count 0 2006.173.11:12:56.93#ibcon#wrote, iclass 6, count 0 2006.173.11:12:56.93#ibcon#about to read 3, iclass 6, count 0 2006.173.11:12:56.97#ibcon#read 3, iclass 6, count 0 2006.173.11:12:56.97#ibcon#about to read 4, iclass 6, count 0 2006.173.11:12:56.97#ibcon#read 4, iclass 6, count 0 2006.173.11:12:56.97#ibcon#about to read 5, iclass 6, count 0 2006.173.11:12:56.97#ibcon#read 5, iclass 6, count 0 2006.173.11:12:56.97#ibcon#about to read 6, iclass 6, count 0 2006.173.11:12:56.97#ibcon#read 6, iclass 6, count 0 2006.173.11:12:56.97#ibcon#end of sib2, iclass 6, count 0 2006.173.11:12:56.97#ibcon#*after write, iclass 6, count 0 2006.173.11:12:56.97#ibcon#*before return 0, iclass 6, count 0 2006.173.11:12:56.97#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.11:12:56.97#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.11:12:56.97#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.11:12:56.97#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.11:12:56.97$vck44/va=6,3 2006.173.11:12:56.97#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.11:12:56.97#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.11:12:56.97#ibcon#ireg 11 cls_cnt 2 2006.173.11:12:56.97#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.11:12:57.03#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.11:12:57.03#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.11:12:57.03#ibcon#enter wrdev, iclass 10, count 2 2006.173.11:12:57.03#ibcon#first serial, iclass 10, count 2 2006.173.11:12:57.03#ibcon#enter sib2, iclass 10, count 2 2006.173.11:12:57.03#ibcon#flushed, iclass 10, count 2 2006.173.11:12:57.03#ibcon#about to write, iclass 10, count 2 2006.173.11:12:57.03#ibcon#wrote, iclass 10, count 2 2006.173.11:12:57.03#ibcon#about to read 3, iclass 10, count 2 2006.173.11:12:57.05#ibcon#read 3, iclass 10, count 2 2006.173.11:12:57.05#ibcon#about to read 4, iclass 10, count 2 2006.173.11:12:57.05#ibcon#read 4, iclass 10, count 2 2006.173.11:12:57.05#ibcon#about to read 5, iclass 10, count 2 2006.173.11:12:57.05#ibcon#read 5, iclass 10, count 2 2006.173.11:12:57.05#ibcon#about to read 6, iclass 10, count 2 2006.173.11:12:57.05#ibcon#read 6, iclass 10, count 2 2006.173.11:12:57.05#ibcon#end of sib2, iclass 10, count 2 2006.173.11:12:57.05#ibcon#*mode == 0, iclass 10, count 2 2006.173.11:12:57.05#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.11:12:57.05#ibcon#[25=AT06-03\r\n] 2006.173.11:12:57.05#ibcon#*before write, iclass 10, count 2 2006.173.11:12:57.05#ibcon#enter sib2, iclass 10, count 2 2006.173.11:12:57.05#ibcon#flushed, iclass 10, count 2 2006.173.11:12:57.05#ibcon#about to write, iclass 10, count 2 2006.173.11:12:57.05#ibcon#wrote, iclass 10, count 2 2006.173.11:12:57.05#ibcon#about to read 3, iclass 10, count 2 2006.173.11:12:57.08#ibcon#read 3, iclass 10, count 2 2006.173.11:12:57.08#ibcon#about to read 4, iclass 10, count 2 2006.173.11:12:57.08#ibcon#read 4, iclass 10, count 2 2006.173.11:12:57.08#ibcon#about to read 5, iclass 10, count 2 2006.173.11:12:57.08#ibcon#read 5, iclass 10, count 2 2006.173.11:12:57.08#ibcon#about to read 6, iclass 10, count 2 2006.173.11:12:57.08#ibcon#read 6, iclass 10, count 2 2006.173.11:12:57.08#ibcon#end of sib2, iclass 10, count 2 2006.173.11:12:57.08#ibcon#*after write, iclass 10, count 2 2006.173.11:12:57.08#ibcon#*before return 0, iclass 10, count 2 2006.173.11:12:57.08#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.11:12:57.08#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.11:12:57.08#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.11:12:57.08#ibcon#ireg 7 cls_cnt 0 2006.173.11:12:57.08#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.11:12:57.20#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.11:12:57.20#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.11:12:57.20#ibcon#enter wrdev, iclass 10, count 0 2006.173.11:12:57.20#ibcon#first serial, iclass 10, count 0 2006.173.11:12:57.20#ibcon#enter sib2, iclass 10, count 0 2006.173.11:12:57.20#ibcon#flushed, iclass 10, count 0 2006.173.11:12:57.20#ibcon#about to write, iclass 10, count 0 2006.173.11:12:57.20#ibcon#wrote, iclass 10, count 0 2006.173.11:12:57.20#ibcon#about to read 3, iclass 10, count 0 2006.173.11:12:57.22#ibcon#read 3, iclass 10, count 0 2006.173.11:12:57.22#ibcon#about to read 4, iclass 10, count 0 2006.173.11:12:57.22#ibcon#read 4, iclass 10, count 0 2006.173.11:12:57.22#ibcon#about to read 5, iclass 10, count 0 2006.173.11:12:57.22#ibcon#read 5, iclass 10, count 0 2006.173.11:12:57.22#ibcon#about to read 6, iclass 10, count 0 2006.173.11:12:57.22#ibcon#read 6, iclass 10, count 0 2006.173.11:12:57.22#ibcon#end of sib2, iclass 10, count 0 2006.173.11:12:57.22#ibcon#*mode == 0, iclass 10, count 0 2006.173.11:12:57.22#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.11:12:57.22#ibcon#[25=USB\r\n] 2006.173.11:12:57.22#ibcon#*before write, iclass 10, count 0 2006.173.11:12:57.22#ibcon#enter sib2, iclass 10, count 0 2006.173.11:12:57.22#ibcon#flushed, iclass 10, count 0 2006.173.11:12:57.22#ibcon#about to write, iclass 10, count 0 2006.173.11:12:57.22#ibcon#wrote, iclass 10, count 0 2006.173.11:12:57.22#ibcon#about to read 3, iclass 10, count 0 2006.173.11:12:57.25#ibcon#read 3, iclass 10, count 0 2006.173.11:12:57.25#ibcon#about to read 4, iclass 10, count 0 2006.173.11:12:57.25#ibcon#read 4, iclass 10, count 0 2006.173.11:12:57.25#ibcon#about to read 5, iclass 10, count 0 2006.173.11:12:57.25#ibcon#read 5, iclass 10, count 0 2006.173.11:12:57.25#ibcon#about to read 6, iclass 10, count 0 2006.173.11:12:57.25#ibcon#read 6, iclass 10, count 0 2006.173.11:12:57.25#ibcon#end of sib2, iclass 10, count 0 2006.173.11:12:57.25#ibcon#*after write, iclass 10, count 0 2006.173.11:12:57.25#ibcon#*before return 0, iclass 10, count 0 2006.173.11:12:57.25#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.11:12:57.25#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.11:12:57.25#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.11:12:57.25#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.11:12:57.25$vck44/valo=7,864.99 2006.173.11:12:57.25#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.11:12:57.25#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.11:12:57.25#ibcon#ireg 17 cls_cnt 0 2006.173.11:12:57.25#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.11:12:57.25#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.11:12:57.25#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.11:12:57.25#ibcon#enter wrdev, iclass 12, count 0 2006.173.11:12:57.25#ibcon#first serial, iclass 12, count 0 2006.173.11:12:57.25#ibcon#enter sib2, iclass 12, count 0 2006.173.11:12:57.25#ibcon#flushed, iclass 12, count 0 2006.173.11:12:57.25#ibcon#about to write, iclass 12, count 0 2006.173.11:12:57.25#ibcon#wrote, iclass 12, count 0 2006.173.11:12:57.25#ibcon#about to read 3, iclass 12, count 0 2006.173.11:12:57.27#ibcon#read 3, iclass 12, count 0 2006.173.11:12:57.27#ibcon#about to read 4, iclass 12, count 0 2006.173.11:12:57.27#ibcon#read 4, iclass 12, count 0 2006.173.11:12:57.27#ibcon#about to read 5, iclass 12, count 0 2006.173.11:12:57.27#ibcon#read 5, iclass 12, count 0 2006.173.11:12:57.27#ibcon#about to read 6, iclass 12, count 0 2006.173.11:12:57.27#ibcon#read 6, iclass 12, count 0 2006.173.11:12:57.27#ibcon#end of sib2, iclass 12, count 0 2006.173.11:12:57.27#ibcon#*mode == 0, iclass 12, count 0 2006.173.11:12:57.27#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.11:12:57.27#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.11:12:57.27#ibcon#*before write, iclass 12, count 0 2006.173.11:12:57.27#ibcon#enter sib2, iclass 12, count 0 2006.173.11:12:57.27#ibcon#flushed, iclass 12, count 0 2006.173.11:12:57.27#ibcon#about to write, iclass 12, count 0 2006.173.11:12:57.27#ibcon#wrote, iclass 12, count 0 2006.173.11:12:57.27#ibcon#about to read 3, iclass 12, count 0 2006.173.11:12:57.31#ibcon#read 3, iclass 12, count 0 2006.173.11:12:57.31#ibcon#about to read 4, iclass 12, count 0 2006.173.11:12:57.31#ibcon#read 4, iclass 12, count 0 2006.173.11:12:57.31#ibcon#about to read 5, iclass 12, count 0 2006.173.11:12:57.31#ibcon#read 5, iclass 12, count 0 2006.173.11:12:57.31#ibcon#about to read 6, iclass 12, count 0 2006.173.11:12:57.31#ibcon#read 6, iclass 12, count 0 2006.173.11:12:57.31#ibcon#end of sib2, iclass 12, count 0 2006.173.11:12:57.31#ibcon#*after write, iclass 12, count 0 2006.173.11:12:57.31#ibcon#*before return 0, iclass 12, count 0 2006.173.11:12:57.31#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.11:12:57.31#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.11:12:57.31#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.11:12:57.31#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.11:12:57.31$vck44/va=7,4 2006.173.11:12:57.31#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.11:12:57.31#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.11:12:57.31#ibcon#ireg 11 cls_cnt 2 2006.173.11:12:57.31#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.11:12:57.37#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.11:12:57.37#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.11:12:57.37#ibcon#enter wrdev, iclass 14, count 2 2006.173.11:12:57.37#ibcon#first serial, iclass 14, count 2 2006.173.11:12:57.37#ibcon#enter sib2, iclass 14, count 2 2006.173.11:12:57.37#ibcon#flushed, iclass 14, count 2 2006.173.11:12:57.37#ibcon#about to write, iclass 14, count 2 2006.173.11:12:57.37#ibcon#wrote, iclass 14, count 2 2006.173.11:12:57.37#ibcon#about to read 3, iclass 14, count 2 2006.173.11:12:57.39#ibcon#read 3, iclass 14, count 2 2006.173.11:12:57.39#ibcon#about to read 4, iclass 14, count 2 2006.173.11:12:57.39#ibcon#read 4, iclass 14, count 2 2006.173.11:12:57.39#ibcon#about to read 5, iclass 14, count 2 2006.173.11:12:57.39#ibcon#read 5, iclass 14, count 2 2006.173.11:12:57.39#ibcon#about to read 6, iclass 14, count 2 2006.173.11:12:57.39#ibcon#read 6, iclass 14, count 2 2006.173.11:12:57.39#ibcon#end of sib2, iclass 14, count 2 2006.173.11:12:57.39#ibcon#*mode == 0, iclass 14, count 2 2006.173.11:12:57.39#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.11:12:57.39#ibcon#[25=AT07-04\r\n] 2006.173.11:12:57.39#ibcon#*before write, iclass 14, count 2 2006.173.11:12:57.39#ibcon#enter sib2, iclass 14, count 2 2006.173.11:12:57.39#ibcon#flushed, iclass 14, count 2 2006.173.11:12:57.39#ibcon#about to write, iclass 14, count 2 2006.173.11:12:57.39#ibcon#wrote, iclass 14, count 2 2006.173.11:12:57.39#ibcon#about to read 3, iclass 14, count 2 2006.173.11:12:57.42#ibcon#read 3, iclass 14, count 2 2006.173.11:12:57.42#ibcon#about to read 4, iclass 14, count 2 2006.173.11:12:57.42#ibcon#read 4, iclass 14, count 2 2006.173.11:12:57.42#ibcon#about to read 5, iclass 14, count 2 2006.173.11:12:57.42#ibcon#read 5, iclass 14, count 2 2006.173.11:12:57.42#ibcon#about to read 6, iclass 14, count 2 2006.173.11:12:57.42#ibcon#read 6, iclass 14, count 2 2006.173.11:12:57.42#ibcon#end of sib2, iclass 14, count 2 2006.173.11:12:57.42#ibcon#*after write, iclass 14, count 2 2006.173.11:12:57.42#ibcon#*before return 0, iclass 14, count 2 2006.173.11:12:57.42#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.11:12:57.42#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.11:12:57.42#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.11:12:57.42#ibcon#ireg 7 cls_cnt 0 2006.173.11:12:57.42#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.11:12:57.54#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.11:12:57.54#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.11:12:57.54#ibcon#enter wrdev, iclass 14, count 0 2006.173.11:12:57.54#ibcon#first serial, iclass 14, count 0 2006.173.11:12:57.54#ibcon#enter sib2, iclass 14, count 0 2006.173.11:12:57.54#ibcon#flushed, iclass 14, count 0 2006.173.11:12:57.54#ibcon#about to write, iclass 14, count 0 2006.173.11:12:57.54#ibcon#wrote, iclass 14, count 0 2006.173.11:12:57.54#ibcon#about to read 3, iclass 14, count 0 2006.173.11:12:57.56#ibcon#read 3, iclass 14, count 0 2006.173.11:12:57.56#ibcon#about to read 4, iclass 14, count 0 2006.173.11:12:57.56#ibcon#read 4, iclass 14, count 0 2006.173.11:12:57.56#ibcon#about to read 5, iclass 14, count 0 2006.173.11:12:57.56#ibcon#read 5, iclass 14, count 0 2006.173.11:12:57.56#ibcon#about to read 6, iclass 14, count 0 2006.173.11:12:57.56#ibcon#read 6, iclass 14, count 0 2006.173.11:12:57.56#ibcon#end of sib2, iclass 14, count 0 2006.173.11:12:57.56#ibcon#*mode == 0, iclass 14, count 0 2006.173.11:12:57.56#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.11:12:57.56#ibcon#[25=USB\r\n] 2006.173.11:12:57.56#ibcon#*before write, iclass 14, count 0 2006.173.11:12:57.56#ibcon#enter sib2, iclass 14, count 0 2006.173.11:12:57.56#ibcon#flushed, iclass 14, count 0 2006.173.11:12:57.56#ibcon#about to write, iclass 14, count 0 2006.173.11:12:57.56#ibcon#wrote, iclass 14, count 0 2006.173.11:12:57.56#ibcon#about to read 3, iclass 14, count 0 2006.173.11:12:57.59#ibcon#read 3, iclass 14, count 0 2006.173.11:12:57.59#ibcon#about to read 4, iclass 14, count 0 2006.173.11:12:57.59#ibcon#read 4, iclass 14, count 0 2006.173.11:12:57.59#ibcon#about to read 5, iclass 14, count 0 2006.173.11:12:57.59#ibcon#read 5, iclass 14, count 0 2006.173.11:12:57.59#ibcon#about to read 6, iclass 14, count 0 2006.173.11:12:57.59#ibcon#read 6, iclass 14, count 0 2006.173.11:12:57.59#ibcon#end of sib2, iclass 14, count 0 2006.173.11:12:57.59#ibcon#*after write, iclass 14, count 0 2006.173.11:12:57.59#ibcon#*before return 0, iclass 14, count 0 2006.173.11:12:57.59#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.11:12:57.59#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.11:12:57.59#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.11:12:57.59#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.11:12:57.59$vck44/valo=8,884.99 2006.173.11:12:57.59#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.11:12:57.59#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.11:12:57.59#ibcon#ireg 17 cls_cnt 0 2006.173.11:12:57.59#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.11:12:57.59#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.11:12:57.59#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.11:12:57.59#ibcon#enter wrdev, iclass 16, count 0 2006.173.11:12:57.59#ibcon#first serial, iclass 16, count 0 2006.173.11:12:57.59#ibcon#enter sib2, iclass 16, count 0 2006.173.11:12:57.59#ibcon#flushed, iclass 16, count 0 2006.173.11:12:57.59#ibcon#about to write, iclass 16, count 0 2006.173.11:12:57.59#ibcon#wrote, iclass 16, count 0 2006.173.11:12:57.59#ibcon#about to read 3, iclass 16, count 0 2006.173.11:12:57.61#ibcon#read 3, iclass 16, count 0 2006.173.11:12:57.61#ibcon#about to read 4, iclass 16, count 0 2006.173.11:12:57.61#ibcon#read 4, iclass 16, count 0 2006.173.11:12:57.61#ibcon#about to read 5, iclass 16, count 0 2006.173.11:12:57.61#ibcon#read 5, iclass 16, count 0 2006.173.11:12:57.61#ibcon#about to read 6, iclass 16, count 0 2006.173.11:12:57.61#ibcon#read 6, iclass 16, count 0 2006.173.11:12:57.61#ibcon#end of sib2, iclass 16, count 0 2006.173.11:12:57.61#ibcon#*mode == 0, iclass 16, count 0 2006.173.11:12:57.61#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.11:12:57.61#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.11:12:57.61#ibcon#*before write, iclass 16, count 0 2006.173.11:12:57.61#ibcon#enter sib2, iclass 16, count 0 2006.173.11:12:57.61#ibcon#flushed, iclass 16, count 0 2006.173.11:12:57.61#ibcon#about to write, iclass 16, count 0 2006.173.11:12:57.61#ibcon#wrote, iclass 16, count 0 2006.173.11:12:57.61#ibcon#about to read 3, iclass 16, count 0 2006.173.11:12:57.65#ibcon#read 3, iclass 16, count 0 2006.173.11:12:57.65#ibcon#about to read 4, iclass 16, count 0 2006.173.11:12:57.65#ibcon#read 4, iclass 16, count 0 2006.173.11:12:57.65#ibcon#about to read 5, iclass 16, count 0 2006.173.11:12:57.65#ibcon#read 5, iclass 16, count 0 2006.173.11:12:57.65#ibcon#about to read 6, iclass 16, count 0 2006.173.11:12:57.65#ibcon#read 6, iclass 16, count 0 2006.173.11:12:57.65#ibcon#end of sib2, iclass 16, count 0 2006.173.11:12:57.65#ibcon#*after write, iclass 16, count 0 2006.173.11:12:57.65#ibcon#*before return 0, iclass 16, count 0 2006.173.11:12:57.65#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.11:12:57.65#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.11:12:57.65#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.11:12:57.65#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.11:12:57.65$vck44/va=8,4 2006.173.11:12:57.65#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.11:12:57.65#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.11:12:57.65#ibcon#ireg 11 cls_cnt 2 2006.173.11:12:57.65#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.11:12:57.71#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.11:12:57.71#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.11:12:57.71#ibcon#enter wrdev, iclass 18, count 2 2006.173.11:12:57.71#ibcon#first serial, iclass 18, count 2 2006.173.11:12:57.71#ibcon#enter sib2, iclass 18, count 2 2006.173.11:12:57.71#ibcon#flushed, iclass 18, count 2 2006.173.11:12:57.71#ibcon#about to write, iclass 18, count 2 2006.173.11:12:57.71#ibcon#wrote, iclass 18, count 2 2006.173.11:12:57.71#ibcon#about to read 3, iclass 18, count 2 2006.173.11:12:57.73#ibcon#read 3, iclass 18, count 2 2006.173.11:12:57.73#ibcon#about to read 4, iclass 18, count 2 2006.173.11:12:57.73#ibcon#read 4, iclass 18, count 2 2006.173.11:12:57.73#ibcon#about to read 5, iclass 18, count 2 2006.173.11:12:57.73#ibcon#read 5, iclass 18, count 2 2006.173.11:12:57.73#ibcon#about to read 6, iclass 18, count 2 2006.173.11:12:57.73#ibcon#read 6, iclass 18, count 2 2006.173.11:12:57.73#ibcon#end of sib2, iclass 18, count 2 2006.173.11:12:57.73#ibcon#*mode == 0, iclass 18, count 2 2006.173.11:12:57.73#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.11:12:57.73#ibcon#[25=AT08-04\r\n] 2006.173.11:12:57.73#ibcon#*before write, iclass 18, count 2 2006.173.11:12:57.73#ibcon#enter sib2, iclass 18, count 2 2006.173.11:12:57.73#ibcon#flushed, iclass 18, count 2 2006.173.11:12:57.73#ibcon#about to write, iclass 18, count 2 2006.173.11:12:57.73#ibcon#wrote, iclass 18, count 2 2006.173.11:12:57.73#ibcon#about to read 3, iclass 18, count 2 2006.173.11:12:57.76#ibcon#read 3, iclass 18, count 2 2006.173.11:12:57.76#ibcon#about to read 4, iclass 18, count 2 2006.173.11:12:57.76#ibcon#read 4, iclass 18, count 2 2006.173.11:12:57.76#ibcon#about to read 5, iclass 18, count 2 2006.173.11:12:57.76#ibcon#read 5, iclass 18, count 2 2006.173.11:12:57.76#ibcon#about to read 6, iclass 18, count 2 2006.173.11:12:57.76#ibcon#read 6, iclass 18, count 2 2006.173.11:12:57.76#ibcon#end of sib2, iclass 18, count 2 2006.173.11:12:57.76#ibcon#*after write, iclass 18, count 2 2006.173.11:12:57.76#ibcon#*before return 0, iclass 18, count 2 2006.173.11:12:57.76#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.11:12:57.76#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.11:12:57.76#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.11:12:57.76#ibcon#ireg 7 cls_cnt 0 2006.173.11:12:57.76#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.11:12:57.88#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.11:12:57.88#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.11:12:57.88#ibcon#enter wrdev, iclass 18, count 0 2006.173.11:12:57.88#ibcon#first serial, iclass 18, count 0 2006.173.11:12:57.88#ibcon#enter sib2, iclass 18, count 0 2006.173.11:12:57.88#ibcon#flushed, iclass 18, count 0 2006.173.11:12:57.88#ibcon#about to write, iclass 18, count 0 2006.173.11:12:57.88#ibcon#wrote, iclass 18, count 0 2006.173.11:12:57.88#ibcon#about to read 3, iclass 18, count 0 2006.173.11:12:57.90#ibcon#read 3, iclass 18, count 0 2006.173.11:12:57.90#ibcon#about to read 4, iclass 18, count 0 2006.173.11:12:57.90#ibcon#read 4, iclass 18, count 0 2006.173.11:12:57.90#ibcon#about to read 5, iclass 18, count 0 2006.173.11:12:57.90#ibcon#read 5, iclass 18, count 0 2006.173.11:12:57.90#ibcon#about to read 6, iclass 18, count 0 2006.173.11:12:57.90#ibcon#read 6, iclass 18, count 0 2006.173.11:12:57.90#ibcon#end of sib2, iclass 18, count 0 2006.173.11:12:57.90#ibcon#*mode == 0, iclass 18, count 0 2006.173.11:12:57.90#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.11:12:57.90#ibcon#[25=USB\r\n] 2006.173.11:12:57.90#ibcon#*before write, iclass 18, count 0 2006.173.11:12:57.90#ibcon#enter sib2, iclass 18, count 0 2006.173.11:12:57.90#ibcon#flushed, iclass 18, count 0 2006.173.11:12:57.90#ibcon#about to write, iclass 18, count 0 2006.173.11:12:57.90#ibcon#wrote, iclass 18, count 0 2006.173.11:12:57.90#ibcon#about to read 3, iclass 18, count 0 2006.173.11:12:57.93#ibcon#read 3, iclass 18, count 0 2006.173.11:12:57.93#ibcon#about to read 4, iclass 18, count 0 2006.173.11:12:57.93#ibcon#read 4, iclass 18, count 0 2006.173.11:12:57.93#ibcon#about to read 5, iclass 18, count 0 2006.173.11:12:57.93#ibcon#read 5, iclass 18, count 0 2006.173.11:12:57.93#ibcon#about to read 6, iclass 18, count 0 2006.173.11:12:57.93#ibcon#read 6, iclass 18, count 0 2006.173.11:12:57.93#ibcon#end of sib2, iclass 18, count 0 2006.173.11:12:57.93#ibcon#*after write, iclass 18, count 0 2006.173.11:12:57.93#ibcon#*before return 0, iclass 18, count 0 2006.173.11:12:57.93#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.11:12:57.93#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.11:12:57.93#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.11:12:57.93#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.11:12:57.93$vck44/vblo=1,629.99 2006.173.11:12:57.93#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.11:12:57.93#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.11:12:57.93#ibcon#ireg 17 cls_cnt 0 2006.173.11:12:57.93#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.11:12:57.93#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.11:12:57.93#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.11:12:57.93#ibcon#enter wrdev, iclass 20, count 0 2006.173.11:12:57.93#ibcon#first serial, iclass 20, count 0 2006.173.11:12:57.93#ibcon#enter sib2, iclass 20, count 0 2006.173.11:12:57.93#ibcon#flushed, iclass 20, count 0 2006.173.11:12:57.93#ibcon#about to write, iclass 20, count 0 2006.173.11:12:57.93#ibcon#wrote, iclass 20, count 0 2006.173.11:12:57.93#ibcon#about to read 3, iclass 20, count 0 2006.173.11:12:57.95#ibcon#read 3, iclass 20, count 0 2006.173.11:12:57.95#ibcon#about to read 4, iclass 20, count 0 2006.173.11:12:57.95#ibcon#read 4, iclass 20, count 0 2006.173.11:12:57.95#ibcon#about to read 5, iclass 20, count 0 2006.173.11:12:57.95#ibcon#read 5, iclass 20, count 0 2006.173.11:12:57.95#ibcon#about to read 6, iclass 20, count 0 2006.173.11:12:57.95#ibcon#read 6, iclass 20, count 0 2006.173.11:12:57.95#ibcon#end of sib2, iclass 20, count 0 2006.173.11:12:57.95#ibcon#*mode == 0, iclass 20, count 0 2006.173.11:12:57.95#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.11:12:57.95#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.11:12:57.95#ibcon#*before write, iclass 20, count 0 2006.173.11:12:57.95#ibcon#enter sib2, iclass 20, count 0 2006.173.11:12:57.95#ibcon#flushed, iclass 20, count 0 2006.173.11:12:57.95#ibcon#about to write, iclass 20, count 0 2006.173.11:12:57.95#ibcon#wrote, iclass 20, count 0 2006.173.11:12:57.95#ibcon#about to read 3, iclass 20, count 0 2006.173.11:12:57.99#ibcon#read 3, iclass 20, count 0 2006.173.11:12:57.99#ibcon#about to read 4, iclass 20, count 0 2006.173.11:12:57.99#ibcon#read 4, iclass 20, count 0 2006.173.11:12:57.99#ibcon#about to read 5, iclass 20, count 0 2006.173.11:12:57.99#ibcon#read 5, iclass 20, count 0 2006.173.11:12:57.99#ibcon#about to read 6, iclass 20, count 0 2006.173.11:12:57.99#ibcon#read 6, iclass 20, count 0 2006.173.11:12:57.99#ibcon#end of sib2, iclass 20, count 0 2006.173.11:12:57.99#ibcon#*after write, iclass 20, count 0 2006.173.11:12:57.99#ibcon#*before return 0, iclass 20, count 0 2006.173.11:12:57.99#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.11:12:57.99#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.11:12:57.99#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.11:12:57.99#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.11:12:57.99$vck44/vb=1,4 2006.173.11:12:57.99#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.11:12:57.99#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.11:12:57.99#ibcon#ireg 11 cls_cnt 2 2006.173.11:12:57.99#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.11:12:57.99#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.11:12:57.99#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.11:12:57.99#ibcon#enter wrdev, iclass 22, count 2 2006.173.11:12:57.99#ibcon#first serial, iclass 22, count 2 2006.173.11:12:57.99#ibcon#enter sib2, iclass 22, count 2 2006.173.11:12:57.99#ibcon#flushed, iclass 22, count 2 2006.173.11:12:57.99#ibcon#about to write, iclass 22, count 2 2006.173.11:12:57.99#ibcon#wrote, iclass 22, count 2 2006.173.11:12:57.99#ibcon#about to read 3, iclass 22, count 2 2006.173.11:12:58.01#ibcon#read 3, iclass 22, count 2 2006.173.11:12:58.01#ibcon#about to read 4, iclass 22, count 2 2006.173.11:12:58.01#ibcon#read 4, iclass 22, count 2 2006.173.11:12:58.01#ibcon#about to read 5, iclass 22, count 2 2006.173.11:12:58.01#ibcon#read 5, iclass 22, count 2 2006.173.11:12:58.01#ibcon#about to read 6, iclass 22, count 2 2006.173.11:12:58.01#ibcon#read 6, iclass 22, count 2 2006.173.11:12:58.01#ibcon#end of sib2, iclass 22, count 2 2006.173.11:12:58.01#ibcon#*mode == 0, iclass 22, count 2 2006.173.11:12:58.01#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.11:12:58.01#ibcon#[27=AT01-04\r\n] 2006.173.11:12:58.01#ibcon#*before write, iclass 22, count 2 2006.173.11:12:58.01#ibcon#enter sib2, iclass 22, count 2 2006.173.11:12:58.01#ibcon#flushed, iclass 22, count 2 2006.173.11:12:58.01#ibcon#about to write, iclass 22, count 2 2006.173.11:12:58.01#ibcon#wrote, iclass 22, count 2 2006.173.11:12:58.01#ibcon#about to read 3, iclass 22, count 2 2006.173.11:12:58.04#ibcon#read 3, iclass 22, count 2 2006.173.11:12:58.04#ibcon#about to read 4, iclass 22, count 2 2006.173.11:12:58.04#ibcon#read 4, iclass 22, count 2 2006.173.11:12:58.04#ibcon#about to read 5, iclass 22, count 2 2006.173.11:12:58.04#ibcon#read 5, iclass 22, count 2 2006.173.11:12:58.04#ibcon#about to read 6, iclass 22, count 2 2006.173.11:12:58.04#ibcon#read 6, iclass 22, count 2 2006.173.11:12:58.04#ibcon#end of sib2, iclass 22, count 2 2006.173.11:12:58.04#ibcon#*after write, iclass 22, count 2 2006.173.11:12:58.04#ibcon#*before return 0, iclass 22, count 2 2006.173.11:12:58.04#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.11:12:58.04#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.11:12:58.04#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.11:12:58.04#ibcon#ireg 7 cls_cnt 0 2006.173.11:12:58.04#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.11:12:58.15#abcon#<5=/03 0.5 1.4 22.48 921004.3\r\n> 2006.173.11:12:58.16#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.11:12:58.16#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.11:12:58.16#ibcon#enter wrdev, iclass 22, count 0 2006.173.11:12:58.16#ibcon#first serial, iclass 22, count 0 2006.173.11:12:58.16#ibcon#enter sib2, iclass 22, count 0 2006.173.11:12:58.16#ibcon#flushed, iclass 22, count 0 2006.173.11:12:58.16#ibcon#about to write, iclass 22, count 0 2006.173.11:12:58.16#ibcon#wrote, iclass 22, count 0 2006.173.11:12:58.16#ibcon#about to read 3, iclass 22, count 0 2006.173.11:12:58.17#abcon#{5=INTERFACE CLEAR} 2006.173.11:12:58.18#ibcon#read 3, iclass 22, count 0 2006.173.11:12:58.18#ibcon#about to read 4, iclass 22, count 0 2006.173.11:12:58.18#ibcon#read 4, iclass 22, count 0 2006.173.11:12:58.18#ibcon#about to read 5, iclass 22, count 0 2006.173.11:12:58.18#ibcon#read 5, iclass 22, count 0 2006.173.11:12:58.18#ibcon#about to read 6, iclass 22, count 0 2006.173.11:12:58.18#ibcon#read 6, iclass 22, count 0 2006.173.11:12:58.18#ibcon#end of sib2, iclass 22, count 0 2006.173.11:12:58.18#ibcon#*mode == 0, iclass 22, count 0 2006.173.11:12:58.18#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.11:12:58.18#ibcon#[27=USB\r\n] 2006.173.11:12:58.18#ibcon#*before write, iclass 22, count 0 2006.173.11:12:58.18#ibcon#enter sib2, iclass 22, count 0 2006.173.11:12:58.18#ibcon#flushed, iclass 22, count 0 2006.173.11:12:58.18#ibcon#about to write, iclass 22, count 0 2006.173.11:12:58.18#ibcon#wrote, iclass 22, count 0 2006.173.11:12:58.18#ibcon#about to read 3, iclass 22, count 0 2006.173.11:12:58.21#ibcon#read 3, iclass 22, count 0 2006.173.11:12:58.21#ibcon#about to read 4, iclass 22, count 0 2006.173.11:12:58.21#ibcon#read 4, iclass 22, count 0 2006.173.11:12:58.21#ibcon#about to read 5, iclass 22, count 0 2006.173.11:12:58.21#ibcon#read 5, iclass 22, count 0 2006.173.11:12:58.21#ibcon#about to read 6, iclass 22, count 0 2006.173.11:12:58.21#ibcon#read 6, iclass 22, count 0 2006.173.11:12:58.21#ibcon#end of sib2, iclass 22, count 0 2006.173.11:12:58.21#ibcon#*after write, iclass 22, count 0 2006.173.11:12:58.21#ibcon#*before return 0, iclass 22, count 0 2006.173.11:12:58.21#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.11:12:58.21#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.11:12:58.21#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.11:12:58.21#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.11:12:58.21$vck44/vblo=2,634.99 2006.173.11:12:58.21#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.11:12:58.21#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.11:12:58.21#ibcon#ireg 17 cls_cnt 0 2006.173.11:12:58.21#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.11:12:58.21#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.11:12:58.21#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.11:12:58.21#ibcon#enter wrdev, iclass 27, count 0 2006.173.11:12:58.21#ibcon#first serial, iclass 27, count 0 2006.173.11:12:58.21#ibcon#enter sib2, iclass 27, count 0 2006.173.11:12:58.21#ibcon#flushed, iclass 27, count 0 2006.173.11:12:58.21#ibcon#about to write, iclass 27, count 0 2006.173.11:12:58.21#ibcon#wrote, iclass 27, count 0 2006.173.11:12:58.21#ibcon#about to read 3, iclass 27, count 0 2006.173.11:12:58.23#ibcon#read 3, iclass 27, count 0 2006.173.11:12:58.23#ibcon#about to read 4, iclass 27, count 0 2006.173.11:12:58.23#ibcon#read 4, iclass 27, count 0 2006.173.11:12:58.23#ibcon#about to read 5, iclass 27, count 0 2006.173.11:12:58.23#ibcon#read 5, iclass 27, count 0 2006.173.11:12:58.23#ibcon#about to read 6, iclass 27, count 0 2006.173.11:12:58.23#ibcon#read 6, iclass 27, count 0 2006.173.11:12:58.23#ibcon#end of sib2, iclass 27, count 0 2006.173.11:12:58.23#ibcon#*mode == 0, iclass 27, count 0 2006.173.11:12:58.23#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.11:12:58.23#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.11:12:58.23#ibcon#*before write, iclass 27, count 0 2006.173.11:12:58.23#ibcon#enter sib2, iclass 27, count 0 2006.173.11:12:58.23#ibcon#flushed, iclass 27, count 0 2006.173.11:12:58.23#ibcon#about to write, iclass 27, count 0 2006.173.11:12:58.23#ibcon#wrote, iclass 27, count 0 2006.173.11:12:58.23#ibcon#about to read 3, iclass 27, count 0 2006.173.11:12:58.23#abcon#[5=S1D000X0/0*\r\n] 2006.173.11:12:58.27#ibcon#read 3, iclass 27, count 0 2006.173.11:12:58.27#ibcon#about to read 4, iclass 27, count 0 2006.173.11:12:58.27#ibcon#read 4, iclass 27, count 0 2006.173.11:12:58.27#ibcon#about to read 5, iclass 27, count 0 2006.173.11:12:58.27#ibcon#read 5, iclass 27, count 0 2006.173.11:12:58.27#ibcon#about to read 6, iclass 27, count 0 2006.173.11:12:58.27#ibcon#read 6, iclass 27, count 0 2006.173.11:12:58.27#ibcon#end of sib2, iclass 27, count 0 2006.173.11:12:58.27#ibcon#*after write, iclass 27, count 0 2006.173.11:12:58.27#ibcon#*before return 0, iclass 27, count 0 2006.173.11:12:58.27#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.11:12:58.27#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.11:12:58.27#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.11:12:58.27#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.11:12:58.27$vck44/vb=2,4 2006.173.11:12:58.27#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.11:12:58.27#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.11:12:58.27#ibcon#ireg 11 cls_cnt 2 2006.173.11:12:58.27#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.11:12:58.33#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.11:12:58.33#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.11:12:58.33#ibcon#enter wrdev, iclass 30, count 2 2006.173.11:12:58.33#ibcon#first serial, iclass 30, count 2 2006.173.11:12:58.33#ibcon#enter sib2, iclass 30, count 2 2006.173.11:12:58.33#ibcon#flushed, iclass 30, count 2 2006.173.11:12:58.33#ibcon#about to write, iclass 30, count 2 2006.173.11:12:58.33#ibcon#wrote, iclass 30, count 2 2006.173.11:12:58.33#ibcon#about to read 3, iclass 30, count 2 2006.173.11:12:58.35#ibcon#read 3, iclass 30, count 2 2006.173.11:12:58.35#ibcon#about to read 4, iclass 30, count 2 2006.173.11:12:58.35#ibcon#read 4, iclass 30, count 2 2006.173.11:12:58.35#ibcon#about to read 5, iclass 30, count 2 2006.173.11:12:58.35#ibcon#read 5, iclass 30, count 2 2006.173.11:12:58.35#ibcon#about to read 6, iclass 30, count 2 2006.173.11:12:58.35#ibcon#read 6, iclass 30, count 2 2006.173.11:12:58.35#ibcon#end of sib2, iclass 30, count 2 2006.173.11:12:58.35#ibcon#*mode == 0, iclass 30, count 2 2006.173.11:12:58.35#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.11:12:58.35#ibcon#[27=AT02-04\r\n] 2006.173.11:12:58.35#ibcon#*before write, iclass 30, count 2 2006.173.11:12:58.35#ibcon#enter sib2, iclass 30, count 2 2006.173.11:12:58.35#ibcon#flushed, iclass 30, count 2 2006.173.11:12:58.35#ibcon#about to write, iclass 30, count 2 2006.173.11:12:58.35#ibcon#wrote, iclass 30, count 2 2006.173.11:12:58.35#ibcon#about to read 3, iclass 30, count 2 2006.173.11:12:58.38#ibcon#read 3, iclass 30, count 2 2006.173.11:12:58.38#ibcon#about to read 4, iclass 30, count 2 2006.173.11:12:58.38#ibcon#read 4, iclass 30, count 2 2006.173.11:12:58.38#ibcon#about to read 5, iclass 30, count 2 2006.173.11:12:58.38#ibcon#read 5, iclass 30, count 2 2006.173.11:12:58.38#ibcon#about to read 6, iclass 30, count 2 2006.173.11:12:58.38#ibcon#read 6, iclass 30, count 2 2006.173.11:12:58.38#ibcon#end of sib2, iclass 30, count 2 2006.173.11:12:58.38#ibcon#*after write, iclass 30, count 2 2006.173.11:12:58.38#ibcon#*before return 0, iclass 30, count 2 2006.173.11:12:58.38#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.11:12:58.38#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.11:12:58.38#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.11:12:58.38#ibcon#ireg 7 cls_cnt 0 2006.173.11:12:58.38#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.11:12:58.50#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.11:12:58.50#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.11:12:58.50#ibcon#enter wrdev, iclass 30, count 0 2006.173.11:12:58.50#ibcon#first serial, iclass 30, count 0 2006.173.11:12:58.50#ibcon#enter sib2, iclass 30, count 0 2006.173.11:12:58.50#ibcon#flushed, iclass 30, count 0 2006.173.11:12:58.50#ibcon#about to write, iclass 30, count 0 2006.173.11:12:58.50#ibcon#wrote, iclass 30, count 0 2006.173.11:12:58.50#ibcon#about to read 3, iclass 30, count 0 2006.173.11:12:58.52#ibcon#read 3, iclass 30, count 0 2006.173.11:12:58.52#ibcon#about to read 4, iclass 30, count 0 2006.173.11:12:58.52#ibcon#read 4, iclass 30, count 0 2006.173.11:12:58.52#ibcon#about to read 5, iclass 30, count 0 2006.173.11:12:58.52#ibcon#read 5, iclass 30, count 0 2006.173.11:12:58.52#ibcon#about to read 6, iclass 30, count 0 2006.173.11:12:58.52#ibcon#read 6, iclass 30, count 0 2006.173.11:12:58.52#ibcon#end of sib2, iclass 30, count 0 2006.173.11:12:58.52#ibcon#*mode == 0, iclass 30, count 0 2006.173.11:12:58.52#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.11:12:58.52#ibcon#[27=USB\r\n] 2006.173.11:12:58.52#ibcon#*before write, iclass 30, count 0 2006.173.11:12:58.52#ibcon#enter sib2, iclass 30, count 0 2006.173.11:12:58.52#ibcon#flushed, iclass 30, count 0 2006.173.11:12:58.52#ibcon#about to write, iclass 30, count 0 2006.173.11:12:58.52#ibcon#wrote, iclass 30, count 0 2006.173.11:12:58.52#ibcon#about to read 3, iclass 30, count 0 2006.173.11:12:58.55#ibcon#read 3, iclass 30, count 0 2006.173.11:12:58.55#ibcon#about to read 4, iclass 30, count 0 2006.173.11:12:58.55#ibcon#read 4, iclass 30, count 0 2006.173.11:12:58.55#ibcon#about to read 5, iclass 30, count 0 2006.173.11:12:58.55#ibcon#read 5, iclass 30, count 0 2006.173.11:12:58.55#ibcon#about to read 6, iclass 30, count 0 2006.173.11:12:58.55#ibcon#read 6, iclass 30, count 0 2006.173.11:12:58.55#ibcon#end of sib2, iclass 30, count 0 2006.173.11:12:58.55#ibcon#*after write, iclass 30, count 0 2006.173.11:12:58.55#ibcon#*before return 0, iclass 30, count 0 2006.173.11:12:58.55#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.11:12:58.55#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.11:12:58.55#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.11:12:58.55#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.11:12:58.55$vck44/vblo=3,649.99 2006.173.11:12:58.55#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.11:12:58.55#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.11:12:58.55#ibcon#ireg 17 cls_cnt 0 2006.173.11:12:58.55#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.11:12:58.55#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.11:12:58.55#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.11:12:58.55#ibcon#enter wrdev, iclass 32, count 0 2006.173.11:12:58.55#ibcon#first serial, iclass 32, count 0 2006.173.11:12:58.55#ibcon#enter sib2, iclass 32, count 0 2006.173.11:12:58.55#ibcon#flushed, iclass 32, count 0 2006.173.11:12:58.55#ibcon#about to write, iclass 32, count 0 2006.173.11:12:58.55#ibcon#wrote, iclass 32, count 0 2006.173.11:12:58.55#ibcon#about to read 3, iclass 32, count 0 2006.173.11:12:58.57#ibcon#read 3, iclass 32, count 0 2006.173.11:12:58.57#ibcon#about to read 4, iclass 32, count 0 2006.173.11:12:58.57#ibcon#read 4, iclass 32, count 0 2006.173.11:12:58.57#ibcon#about to read 5, iclass 32, count 0 2006.173.11:12:58.57#ibcon#read 5, iclass 32, count 0 2006.173.11:12:58.57#ibcon#about to read 6, iclass 32, count 0 2006.173.11:12:58.57#ibcon#read 6, iclass 32, count 0 2006.173.11:12:58.57#ibcon#end of sib2, iclass 32, count 0 2006.173.11:12:58.57#ibcon#*mode == 0, iclass 32, count 0 2006.173.11:12:58.57#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.11:12:58.57#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.11:12:58.57#ibcon#*before write, iclass 32, count 0 2006.173.11:12:58.57#ibcon#enter sib2, iclass 32, count 0 2006.173.11:12:58.57#ibcon#flushed, iclass 32, count 0 2006.173.11:12:58.57#ibcon#about to write, iclass 32, count 0 2006.173.11:12:58.57#ibcon#wrote, iclass 32, count 0 2006.173.11:12:58.57#ibcon#about to read 3, iclass 32, count 0 2006.173.11:12:58.61#ibcon#read 3, iclass 32, count 0 2006.173.11:12:58.61#ibcon#about to read 4, iclass 32, count 0 2006.173.11:12:58.61#ibcon#read 4, iclass 32, count 0 2006.173.11:12:58.61#ibcon#about to read 5, iclass 32, count 0 2006.173.11:12:58.61#ibcon#read 5, iclass 32, count 0 2006.173.11:12:58.61#ibcon#about to read 6, iclass 32, count 0 2006.173.11:12:58.61#ibcon#read 6, iclass 32, count 0 2006.173.11:12:58.61#ibcon#end of sib2, iclass 32, count 0 2006.173.11:12:58.61#ibcon#*after write, iclass 32, count 0 2006.173.11:12:58.61#ibcon#*before return 0, iclass 32, count 0 2006.173.11:12:58.61#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.11:12:58.61#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.11:12:58.61#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.11:12:58.61#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.11:12:58.61$vck44/vb=3,4 2006.173.11:12:58.61#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.11:12:58.61#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.11:12:58.61#ibcon#ireg 11 cls_cnt 2 2006.173.11:12:58.61#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.11:12:58.67#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.11:12:58.67#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.11:12:58.67#ibcon#enter wrdev, iclass 34, count 2 2006.173.11:12:58.67#ibcon#first serial, iclass 34, count 2 2006.173.11:12:58.67#ibcon#enter sib2, iclass 34, count 2 2006.173.11:12:58.67#ibcon#flushed, iclass 34, count 2 2006.173.11:12:58.67#ibcon#about to write, iclass 34, count 2 2006.173.11:12:58.67#ibcon#wrote, iclass 34, count 2 2006.173.11:12:58.67#ibcon#about to read 3, iclass 34, count 2 2006.173.11:12:58.69#ibcon#read 3, iclass 34, count 2 2006.173.11:12:58.69#ibcon#about to read 4, iclass 34, count 2 2006.173.11:12:58.69#ibcon#read 4, iclass 34, count 2 2006.173.11:12:58.69#ibcon#about to read 5, iclass 34, count 2 2006.173.11:12:58.69#ibcon#read 5, iclass 34, count 2 2006.173.11:12:58.69#ibcon#about to read 6, iclass 34, count 2 2006.173.11:12:58.69#ibcon#read 6, iclass 34, count 2 2006.173.11:12:58.69#ibcon#end of sib2, iclass 34, count 2 2006.173.11:12:58.69#ibcon#*mode == 0, iclass 34, count 2 2006.173.11:12:58.69#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.11:12:58.69#ibcon#[27=AT03-04\r\n] 2006.173.11:12:58.69#ibcon#*before write, iclass 34, count 2 2006.173.11:12:58.69#ibcon#enter sib2, iclass 34, count 2 2006.173.11:12:58.69#ibcon#flushed, iclass 34, count 2 2006.173.11:12:58.69#ibcon#about to write, iclass 34, count 2 2006.173.11:12:58.69#ibcon#wrote, iclass 34, count 2 2006.173.11:12:58.69#ibcon#about to read 3, iclass 34, count 2 2006.173.11:12:58.72#ibcon#read 3, iclass 34, count 2 2006.173.11:12:58.72#ibcon#about to read 4, iclass 34, count 2 2006.173.11:12:58.72#ibcon#read 4, iclass 34, count 2 2006.173.11:12:58.72#ibcon#about to read 5, iclass 34, count 2 2006.173.11:12:58.72#ibcon#read 5, iclass 34, count 2 2006.173.11:12:58.72#ibcon#about to read 6, iclass 34, count 2 2006.173.11:12:58.72#ibcon#read 6, iclass 34, count 2 2006.173.11:12:58.72#ibcon#end of sib2, iclass 34, count 2 2006.173.11:12:58.72#ibcon#*after write, iclass 34, count 2 2006.173.11:12:58.72#ibcon#*before return 0, iclass 34, count 2 2006.173.11:12:58.72#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.11:12:58.72#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.11:12:58.72#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.11:12:58.72#ibcon#ireg 7 cls_cnt 0 2006.173.11:12:58.72#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.11:12:58.84#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.11:12:58.84#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.11:12:58.84#ibcon#enter wrdev, iclass 34, count 0 2006.173.11:12:58.84#ibcon#first serial, iclass 34, count 0 2006.173.11:12:58.84#ibcon#enter sib2, iclass 34, count 0 2006.173.11:12:58.84#ibcon#flushed, iclass 34, count 0 2006.173.11:12:58.84#ibcon#about to write, iclass 34, count 0 2006.173.11:12:58.84#ibcon#wrote, iclass 34, count 0 2006.173.11:12:58.84#ibcon#about to read 3, iclass 34, count 0 2006.173.11:12:58.86#ibcon#read 3, iclass 34, count 0 2006.173.11:12:58.86#ibcon#about to read 4, iclass 34, count 0 2006.173.11:12:58.86#ibcon#read 4, iclass 34, count 0 2006.173.11:12:58.86#ibcon#about to read 5, iclass 34, count 0 2006.173.11:12:58.86#ibcon#read 5, iclass 34, count 0 2006.173.11:12:58.86#ibcon#about to read 6, iclass 34, count 0 2006.173.11:12:58.86#ibcon#read 6, iclass 34, count 0 2006.173.11:12:58.86#ibcon#end of sib2, iclass 34, count 0 2006.173.11:12:58.86#ibcon#*mode == 0, iclass 34, count 0 2006.173.11:12:58.86#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.11:12:58.86#ibcon#[27=USB\r\n] 2006.173.11:12:58.86#ibcon#*before write, iclass 34, count 0 2006.173.11:12:58.86#ibcon#enter sib2, iclass 34, count 0 2006.173.11:12:58.86#ibcon#flushed, iclass 34, count 0 2006.173.11:12:58.86#ibcon#about to write, iclass 34, count 0 2006.173.11:12:58.86#ibcon#wrote, iclass 34, count 0 2006.173.11:12:58.86#ibcon#about to read 3, iclass 34, count 0 2006.173.11:12:58.89#ibcon#read 3, iclass 34, count 0 2006.173.11:12:58.89#ibcon#about to read 4, iclass 34, count 0 2006.173.11:12:58.89#ibcon#read 4, iclass 34, count 0 2006.173.11:12:58.89#ibcon#about to read 5, iclass 34, count 0 2006.173.11:12:58.89#ibcon#read 5, iclass 34, count 0 2006.173.11:12:58.89#ibcon#about to read 6, iclass 34, count 0 2006.173.11:12:58.89#ibcon#read 6, iclass 34, count 0 2006.173.11:12:58.89#ibcon#end of sib2, iclass 34, count 0 2006.173.11:12:58.89#ibcon#*after write, iclass 34, count 0 2006.173.11:12:58.89#ibcon#*before return 0, iclass 34, count 0 2006.173.11:12:58.89#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.11:12:58.89#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.11:12:58.89#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.11:12:58.89#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.11:12:58.89$vck44/vblo=4,679.99 2006.173.11:12:58.89#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.11:12:58.89#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.11:12:58.89#ibcon#ireg 17 cls_cnt 0 2006.173.11:12:58.89#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.11:12:58.89#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.11:12:58.89#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.11:12:58.89#ibcon#enter wrdev, iclass 36, count 0 2006.173.11:12:58.89#ibcon#first serial, iclass 36, count 0 2006.173.11:12:58.89#ibcon#enter sib2, iclass 36, count 0 2006.173.11:12:58.89#ibcon#flushed, iclass 36, count 0 2006.173.11:12:58.89#ibcon#about to write, iclass 36, count 0 2006.173.11:12:58.89#ibcon#wrote, iclass 36, count 0 2006.173.11:12:58.89#ibcon#about to read 3, iclass 36, count 0 2006.173.11:12:58.91#ibcon#read 3, iclass 36, count 0 2006.173.11:12:58.91#ibcon#about to read 4, iclass 36, count 0 2006.173.11:12:58.91#ibcon#read 4, iclass 36, count 0 2006.173.11:12:58.91#ibcon#about to read 5, iclass 36, count 0 2006.173.11:12:58.91#ibcon#read 5, iclass 36, count 0 2006.173.11:12:58.91#ibcon#about to read 6, iclass 36, count 0 2006.173.11:12:58.91#ibcon#read 6, iclass 36, count 0 2006.173.11:12:58.91#ibcon#end of sib2, iclass 36, count 0 2006.173.11:12:58.91#ibcon#*mode == 0, iclass 36, count 0 2006.173.11:12:58.91#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.11:12:58.91#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.11:12:58.91#ibcon#*before write, iclass 36, count 0 2006.173.11:12:58.91#ibcon#enter sib2, iclass 36, count 0 2006.173.11:12:58.91#ibcon#flushed, iclass 36, count 0 2006.173.11:12:58.91#ibcon#about to write, iclass 36, count 0 2006.173.11:12:58.91#ibcon#wrote, iclass 36, count 0 2006.173.11:12:58.91#ibcon#about to read 3, iclass 36, count 0 2006.173.11:12:58.95#ibcon#read 3, iclass 36, count 0 2006.173.11:12:58.95#ibcon#about to read 4, iclass 36, count 0 2006.173.11:12:58.95#ibcon#read 4, iclass 36, count 0 2006.173.11:12:58.95#ibcon#about to read 5, iclass 36, count 0 2006.173.11:12:58.95#ibcon#read 5, iclass 36, count 0 2006.173.11:12:58.95#ibcon#about to read 6, iclass 36, count 0 2006.173.11:12:58.95#ibcon#read 6, iclass 36, count 0 2006.173.11:12:58.95#ibcon#end of sib2, iclass 36, count 0 2006.173.11:12:58.95#ibcon#*after write, iclass 36, count 0 2006.173.11:12:58.95#ibcon#*before return 0, iclass 36, count 0 2006.173.11:12:58.95#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.11:12:58.95#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.11:12:58.95#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.11:12:58.95#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.11:12:58.95$vck44/vb=4,4 2006.173.11:12:58.95#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.11:12:58.95#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.11:12:58.95#ibcon#ireg 11 cls_cnt 2 2006.173.11:12:58.95#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.11:12:59.01#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.11:12:59.01#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.11:12:59.01#ibcon#enter wrdev, iclass 38, count 2 2006.173.11:12:59.01#ibcon#first serial, iclass 38, count 2 2006.173.11:12:59.01#ibcon#enter sib2, iclass 38, count 2 2006.173.11:12:59.01#ibcon#flushed, iclass 38, count 2 2006.173.11:12:59.01#ibcon#about to write, iclass 38, count 2 2006.173.11:12:59.01#ibcon#wrote, iclass 38, count 2 2006.173.11:12:59.01#ibcon#about to read 3, iclass 38, count 2 2006.173.11:12:59.03#ibcon#read 3, iclass 38, count 2 2006.173.11:12:59.03#ibcon#about to read 4, iclass 38, count 2 2006.173.11:12:59.03#ibcon#read 4, iclass 38, count 2 2006.173.11:12:59.03#ibcon#about to read 5, iclass 38, count 2 2006.173.11:12:59.03#ibcon#read 5, iclass 38, count 2 2006.173.11:12:59.03#ibcon#about to read 6, iclass 38, count 2 2006.173.11:12:59.03#ibcon#read 6, iclass 38, count 2 2006.173.11:12:59.03#ibcon#end of sib2, iclass 38, count 2 2006.173.11:12:59.03#ibcon#*mode == 0, iclass 38, count 2 2006.173.11:12:59.03#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.11:12:59.03#ibcon#[27=AT04-04\r\n] 2006.173.11:12:59.03#ibcon#*before write, iclass 38, count 2 2006.173.11:12:59.03#ibcon#enter sib2, iclass 38, count 2 2006.173.11:12:59.03#ibcon#flushed, iclass 38, count 2 2006.173.11:12:59.03#ibcon#about to write, iclass 38, count 2 2006.173.11:12:59.03#ibcon#wrote, iclass 38, count 2 2006.173.11:12:59.03#ibcon#about to read 3, iclass 38, count 2 2006.173.11:12:59.06#ibcon#read 3, iclass 38, count 2 2006.173.11:12:59.06#ibcon#about to read 4, iclass 38, count 2 2006.173.11:12:59.06#ibcon#read 4, iclass 38, count 2 2006.173.11:12:59.06#ibcon#about to read 5, iclass 38, count 2 2006.173.11:12:59.06#ibcon#read 5, iclass 38, count 2 2006.173.11:12:59.06#ibcon#about to read 6, iclass 38, count 2 2006.173.11:12:59.06#ibcon#read 6, iclass 38, count 2 2006.173.11:12:59.06#ibcon#end of sib2, iclass 38, count 2 2006.173.11:12:59.06#ibcon#*after write, iclass 38, count 2 2006.173.11:12:59.06#ibcon#*before return 0, iclass 38, count 2 2006.173.11:12:59.06#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.11:12:59.06#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.11:12:59.06#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.11:12:59.06#ibcon#ireg 7 cls_cnt 0 2006.173.11:12:59.06#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.11:12:59.18#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.11:12:59.18#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.11:12:59.18#ibcon#enter wrdev, iclass 38, count 0 2006.173.11:12:59.18#ibcon#first serial, iclass 38, count 0 2006.173.11:12:59.18#ibcon#enter sib2, iclass 38, count 0 2006.173.11:12:59.18#ibcon#flushed, iclass 38, count 0 2006.173.11:12:59.18#ibcon#about to write, iclass 38, count 0 2006.173.11:12:59.18#ibcon#wrote, iclass 38, count 0 2006.173.11:12:59.18#ibcon#about to read 3, iclass 38, count 0 2006.173.11:12:59.20#ibcon#read 3, iclass 38, count 0 2006.173.11:12:59.20#ibcon#about to read 4, iclass 38, count 0 2006.173.11:12:59.20#ibcon#read 4, iclass 38, count 0 2006.173.11:12:59.20#ibcon#about to read 5, iclass 38, count 0 2006.173.11:12:59.20#ibcon#read 5, iclass 38, count 0 2006.173.11:12:59.20#ibcon#about to read 6, iclass 38, count 0 2006.173.11:12:59.20#ibcon#read 6, iclass 38, count 0 2006.173.11:12:59.20#ibcon#end of sib2, iclass 38, count 0 2006.173.11:12:59.20#ibcon#*mode == 0, iclass 38, count 0 2006.173.11:12:59.20#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.11:12:59.20#ibcon#[27=USB\r\n] 2006.173.11:12:59.20#ibcon#*before write, iclass 38, count 0 2006.173.11:12:59.20#ibcon#enter sib2, iclass 38, count 0 2006.173.11:12:59.20#ibcon#flushed, iclass 38, count 0 2006.173.11:12:59.20#ibcon#about to write, iclass 38, count 0 2006.173.11:12:59.20#ibcon#wrote, iclass 38, count 0 2006.173.11:12:59.20#ibcon#about to read 3, iclass 38, count 0 2006.173.11:12:59.23#ibcon#read 3, iclass 38, count 0 2006.173.11:12:59.23#ibcon#about to read 4, iclass 38, count 0 2006.173.11:12:59.23#ibcon#read 4, iclass 38, count 0 2006.173.11:12:59.23#ibcon#about to read 5, iclass 38, count 0 2006.173.11:12:59.23#ibcon#read 5, iclass 38, count 0 2006.173.11:12:59.23#ibcon#about to read 6, iclass 38, count 0 2006.173.11:12:59.23#ibcon#read 6, iclass 38, count 0 2006.173.11:12:59.23#ibcon#end of sib2, iclass 38, count 0 2006.173.11:12:59.23#ibcon#*after write, iclass 38, count 0 2006.173.11:12:59.23#ibcon#*before return 0, iclass 38, count 0 2006.173.11:12:59.23#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.11:12:59.23#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.11:12:59.23#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.11:12:59.23#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.11:12:59.23$vck44/vblo=5,709.99 2006.173.11:12:59.23#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.11:12:59.23#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.11:12:59.23#ibcon#ireg 17 cls_cnt 0 2006.173.11:12:59.23#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.11:12:59.23#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.11:12:59.23#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.11:12:59.23#ibcon#enter wrdev, iclass 40, count 0 2006.173.11:12:59.23#ibcon#first serial, iclass 40, count 0 2006.173.11:12:59.23#ibcon#enter sib2, iclass 40, count 0 2006.173.11:12:59.23#ibcon#flushed, iclass 40, count 0 2006.173.11:12:59.23#ibcon#about to write, iclass 40, count 0 2006.173.11:12:59.23#ibcon#wrote, iclass 40, count 0 2006.173.11:12:59.23#ibcon#about to read 3, iclass 40, count 0 2006.173.11:12:59.25#ibcon#read 3, iclass 40, count 0 2006.173.11:12:59.25#ibcon#about to read 4, iclass 40, count 0 2006.173.11:12:59.25#ibcon#read 4, iclass 40, count 0 2006.173.11:12:59.25#ibcon#about to read 5, iclass 40, count 0 2006.173.11:12:59.25#ibcon#read 5, iclass 40, count 0 2006.173.11:12:59.25#ibcon#about to read 6, iclass 40, count 0 2006.173.11:12:59.25#ibcon#read 6, iclass 40, count 0 2006.173.11:12:59.25#ibcon#end of sib2, iclass 40, count 0 2006.173.11:12:59.25#ibcon#*mode == 0, iclass 40, count 0 2006.173.11:12:59.25#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.11:12:59.25#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.11:12:59.25#ibcon#*before write, iclass 40, count 0 2006.173.11:12:59.25#ibcon#enter sib2, iclass 40, count 0 2006.173.11:12:59.25#ibcon#flushed, iclass 40, count 0 2006.173.11:12:59.25#ibcon#about to write, iclass 40, count 0 2006.173.11:12:59.25#ibcon#wrote, iclass 40, count 0 2006.173.11:12:59.25#ibcon#about to read 3, iclass 40, count 0 2006.173.11:12:59.29#ibcon#read 3, iclass 40, count 0 2006.173.11:12:59.29#ibcon#about to read 4, iclass 40, count 0 2006.173.11:12:59.29#ibcon#read 4, iclass 40, count 0 2006.173.11:12:59.29#ibcon#about to read 5, iclass 40, count 0 2006.173.11:12:59.29#ibcon#read 5, iclass 40, count 0 2006.173.11:12:59.29#ibcon#about to read 6, iclass 40, count 0 2006.173.11:12:59.29#ibcon#read 6, iclass 40, count 0 2006.173.11:12:59.29#ibcon#end of sib2, iclass 40, count 0 2006.173.11:12:59.29#ibcon#*after write, iclass 40, count 0 2006.173.11:12:59.29#ibcon#*before return 0, iclass 40, count 0 2006.173.11:12:59.29#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.11:12:59.29#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.11:12:59.29#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.11:12:59.29#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.11:12:59.29$vck44/vb=5,4 2006.173.11:12:59.29#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.11:12:59.29#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.11:12:59.29#ibcon#ireg 11 cls_cnt 2 2006.173.11:12:59.29#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.11:12:59.35#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.11:12:59.35#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.11:12:59.35#ibcon#enter wrdev, iclass 4, count 2 2006.173.11:12:59.35#ibcon#first serial, iclass 4, count 2 2006.173.11:12:59.35#ibcon#enter sib2, iclass 4, count 2 2006.173.11:12:59.35#ibcon#flushed, iclass 4, count 2 2006.173.11:12:59.35#ibcon#about to write, iclass 4, count 2 2006.173.11:12:59.35#ibcon#wrote, iclass 4, count 2 2006.173.11:12:59.35#ibcon#about to read 3, iclass 4, count 2 2006.173.11:12:59.37#ibcon#read 3, iclass 4, count 2 2006.173.11:12:59.37#ibcon#about to read 4, iclass 4, count 2 2006.173.11:12:59.37#ibcon#read 4, iclass 4, count 2 2006.173.11:12:59.37#ibcon#about to read 5, iclass 4, count 2 2006.173.11:12:59.37#ibcon#read 5, iclass 4, count 2 2006.173.11:12:59.37#ibcon#about to read 6, iclass 4, count 2 2006.173.11:12:59.37#ibcon#read 6, iclass 4, count 2 2006.173.11:12:59.37#ibcon#end of sib2, iclass 4, count 2 2006.173.11:12:59.37#ibcon#*mode == 0, iclass 4, count 2 2006.173.11:12:59.37#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.11:12:59.37#ibcon#[27=AT05-04\r\n] 2006.173.11:12:59.37#ibcon#*before write, iclass 4, count 2 2006.173.11:12:59.37#ibcon#enter sib2, iclass 4, count 2 2006.173.11:12:59.37#ibcon#flushed, iclass 4, count 2 2006.173.11:12:59.37#ibcon#about to write, iclass 4, count 2 2006.173.11:12:59.37#ibcon#wrote, iclass 4, count 2 2006.173.11:12:59.37#ibcon#about to read 3, iclass 4, count 2 2006.173.11:12:59.40#ibcon#read 3, iclass 4, count 2 2006.173.11:12:59.40#ibcon#about to read 4, iclass 4, count 2 2006.173.11:12:59.40#ibcon#read 4, iclass 4, count 2 2006.173.11:12:59.40#ibcon#about to read 5, iclass 4, count 2 2006.173.11:12:59.40#ibcon#read 5, iclass 4, count 2 2006.173.11:12:59.40#ibcon#about to read 6, iclass 4, count 2 2006.173.11:12:59.40#ibcon#read 6, iclass 4, count 2 2006.173.11:12:59.40#ibcon#end of sib2, iclass 4, count 2 2006.173.11:12:59.40#ibcon#*after write, iclass 4, count 2 2006.173.11:12:59.40#ibcon#*before return 0, iclass 4, count 2 2006.173.11:12:59.40#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.11:12:59.40#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.11:12:59.40#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.11:12:59.40#ibcon#ireg 7 cls_cnt 0 2006.173.11:12:59.40#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.11:12:59.52#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.11:12:59.52#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.11:12:59.52#ibcon#enter wrdev, iclass 4, count 0 2006.173.11:12:59.52#ibcon#first serial, iclass 4, count 0 2006.173.11:12:59.52#ibcon#enter sib2, iclass 4, count 0 2006.173.11:12:59.52#ibcon#flushed, iclass 4, count 0 2006.173.11:12:59.52#ibcon#about to write, iclass 4, count 0 2006.173.11:12:59.52#ibcon#wrote, iclass 4, count 0 2006.173.11:12:59.52#ibcon#about to read 3, iclass 4, count 0 2006.173.11:12:59.54#ibcon#read 3, iclass 4, count 0 2006.173.11:12:59.54#ibcon#about to read 4, iclass 4, count 0 2006.173.11:12:59.54#ibcon#read 4, iclass 4, count 0 2006.173.11:12:59.54#ibcon#about to read 5, iclass 4, count 0 2006.173.11:12:59.54#ibcon#read 5, iclass 4, count 0 2006.173.11:12:59.54#ibcon#about to read 6, iclass 4, count 0 2006.173.11:12:59.54#ibcon#read 6, iclass 4, count 0 2006.173.11:12:59.54#ibcon#end of sib2, iclass 4, count 0 2006.173.11:12:59.54#ibcon#*mode == 0, iclass 4, count 0 2006.173.11:12:59.54#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.11:12:59.54#ibcon#[27=USB\r\n] 2006.173.11:12:59.54#ibcon#*before write, iclass 4, count 0 2006.173.11:12:59.54#ibcon#enter sib2, iclass 4, count 0 2006.173.11:12:59.54#ibcon#flushed, iclass 4, count 0 2006.173.11:12:59.54#ibcon#about to write, iclass 4, count 0 2006.173.11:12:59.54#ibcon#wrote, iclass 4, count 0 2006.173.11:12:59.54#ibcon#about to read 3, iclass 4, count 0 2006.173.11:12:59.57#ibcon#read 3, iclass 4, count 0 2006.173.11:12:59.57#ibcon#about to read 4, iclass 4, count 0 2006.173.11:12:59.57#ibcon#read 4, iclass 4, count 0 2006.173.11:12:59.57#ibcon#about to read 5, iclass 4, count 0 2006.173.11:12:59.57#ibcon#read 5, iclass 4, count 0 2006.173.11:12:59.57#ibcon#about to read 6, iclass 4, count 0 2006.173.11:12:59.57#ibcon#read 6, iclass 4, count 0 2006.173.11:12:59.57#ibcon#end of sib2, iclass 4, count 0 2006.173.11:12:59.57#ibcon#*after write, iclass 4, count 0 2006.173.11:12:59.57#ibcon#*before return 0, iclass 4, count 0 2006.173.11:12:59.57#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.11:12:59.57#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.11:12:59.57#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.11:12:59.57#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.11:12:59.57$vck44/vblo=6,719.99 2006.173.11:12:59.57#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.11:12:59.57#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.11:12:59.57#ibcon#ireg 17 cls_cnt 0 2006.173.11:12:59.57#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.11:12:59.57#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.11:12:59.57#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.11:12:59.57#ibcon#enter wrdev, iclass 6, count 0 2006.173.11:12:59.57#ibcon#first serial, iclass 6, count 0 2006.173.11:12:59.57#ibcon#enter sib2, iclass 6, count 0 2006.173.11:12:59.57#ibcon#flushed, iclass 6, count 0 2006.173.11:12:59.57#ibcon#about to write, iclass 6, count 0 2006.173.11:12:59.57#ibcon#wrote, iclass 6, count 0 2006.173.11:12:59.57#ibcon#about to read 3, iclass 6, count 0 2006.173.11:12:59.59#ibcon#read 3, iclass 6, count 0 2006.173.11:12:59.59#ibcon#about to read 4, iclass 6, count 0 2006.173.11:12:59.59#ibcon#read 4, iclass 6, count 0 2006.173.11:12:59.59#ibcon#about to read 5, iclass 6, count 0 2006.173.11:12:59.59#ibcon#read 5, iclass 6, count 0 2006.173.11:12:59.59#ibcon#about to read 6, iclass 6, count 0 2006.173.11:12:59.59#ibcon#read 6, iclass 6, count 0 2006.173.11:12:59.59#ibcon#end of sib2, iclass 6, count 0 2006.173.11:12:59.59#ibcon#*mode == 0, iclass 6, count 0 2006.173.11:12:59.59#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.11:12:59.59#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.11:12:59.59#ibcon#*before write, iclass 6, count 0 2006.173.11:12:59.59#ibcon#enter sib2, iclass 6, count 0 2006.173.11:12:59.59#ibcon#flushed, iclass 6, count 0 2006.173.11:12:59.59#ibcon#about to write, iclass 6, count 0 2006.173.11:12:59.59#ibcon#wrote, iclass 6, count 0 2006.173.11:12:59.59#ibcon#about to read 3, iclass 6, count 0 2006.173.11:12:59.63#ibcon#read 3, iclass 6, count 0 2006.173.11:12:59.63#ibcon#about to read 4, iclass 6, count 0 2006.173.11:12:59.63#ibcon#read 4, iclass 6, count 0 2006.173.11:12:59.63#ibcon#about to read 5, iclass 6, count 0 2006.173.11:12:59.63#ibcon#read 5, iclass 6, count 0 2006.173.11:12:59.63#ibcon#about to read 6, iclass 6, count 0 2006.173.11:12:59.63#ibcon#read 6, iclass 6, count 0 2006.173.11:12:59.63#ibcon#end of sib2, iclass 6, count 0 2006.173.11:12:59.63#ibcon#*after write, iclass 6, count 0 2006.173.11:12:59.63#ibcon#*before return 0, iclass 6, count 0 2006.173.11:12:59.63#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.11:12:59.63#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.11:12:59.63#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.11:12:59.63#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.11:12:59.63$vck44/vb=6,4 2006.173.11:12:59.63#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.11:12:59.63#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.11:12:59.63#ibcon#ireg 11 cls_cnt 2 2006.173.11:12:59.63#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.11:12:59.69#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.11:12:59.69#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.11:12:59.69#ibcon#enter wrdev, iclass 10, count 2 2006.173.11:12:59.69#ibcon#first serial, iclass 10, count 2 2006.173.11:12:59.69#ibcon#enter sib2, iclass 10, count 2 2006.173.11:12:59.69#ibcon#flushed, iclass 10, count 2 2006.173.11:12:59.69#ibcon#about to write, iclass 10, count 2 2006.173.11:12:59.69#ibcon#wrote, iclass 10, count 2 2006.173.11:12:59.69#ibcon#about to read 3, iclass 10, count 2 2006.173.11:12:59.71#ibcon#read 3, iclass 10, count 2 2006.173.11:12:59.71#ibcon#about to read 4, iclass 10, count 2 2006.173.11:12:59.71#ibcon#read 4, iclass 10, count 2 2006.173.11:12:59.71#ibcon#about to read 5, iclass 10, count 2 2006.173.11:12:59.71#ibcon#read 5, iclass 10, count 2 2006.173.11:12:59.71#ibcon#about to read 6, iclass 10, count 2 2006.173.11:12:59.71#ibcon#read 6, iclass 10, count 2 2006.173.11:12:59.71#ibcon#end of sib2, iclass 10, count 2 2006.173.11:12:59.71#ibcon#*mode == 0, iclass 10, count 2 2006.173.11:12:59.71#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.11:12:59.71#ibcon#[27=AT06-04\r\n] 2006.173.11:12:59.71#ibcon#*before write, iclass 10, count 2 2006.173.11:12:59.71#ibcon#enter sib2, iclass 10, count 2 2006.173.11:12:59.71#ibcon#flushed, iclass 10, count 2 2006.173.11:12:59.71#ibcon#about to write, iclass 10, count 2 2006.173.11:12:59.71#ibcon#wrote, iclass 10, count 2 2006.173.11:12:59.71#ibcon#about to read 3, iclass 10, count 2 2006.173.11:12:59.74#ibcon#read 3, iclass 10, count 2 2006.173.11:12:59.74#ibcon#about to read 4, iclass 10, count 2 2006.173.11:12:59.74#ibcon#read 4, iclass 10, count 2 2006.173.11:12:59.74#ibcon#about to read 5, iclass 10, count 2 2006.173.11:12:59.74#ibcon#read 5, iclass 10, count 2 2006.173.11:12:59.74#ibcon#about to read 6, iclass 10, count 2 2006.173.11:12:59.74#ibcon#read 6, iclass 10, count 2 2006.173.11:12:59.74#ibcon#end of sib2, iclass 10, count 2 2006.173.11:12:59.74#ibcon#*after write, iclass 10, count 2 2006.173.11:12:59.74#ibcon#*before return 0, iclass 10, count 2 2006.173.11:12:59.74#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.11:12:59.74#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.11:12:59.74#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.11:12:59.74#ibcon#ireg 7 cls_cnt 0 2006.173.11:12:59.74#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.11:12:59.86#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.11:12:59.86#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.11:12:59.86#ibcon#enter wrdev, iclass 10, count 0 2006.173.11:12:59.86#ibcon#first serial, iclass 10, count 0 2006.173.11:12:59.86#ibcon#enter sib2, iclass 10, count 0 2006.173.11:12:59.86#ibcon#flushed, iclass 10, count 0 2006.173.11:12:59.86#ibcon#about to write, iclass 10, count 0 2006.173.11:12:59.86#ibcon#wrote, iclass 10, count 0 2006.173.11:12:59.86#ibcon#about to read 3, iclass 10, count 0 2006.173.11:12:59.88#ibcon#read 3, iclass 10, count 0 2006.173.11:12:59.88#ibcon#about to read 4, iclass 10, count 0 2006.173.11:12:59.88#ibcon#read 4, iclass 10, count 0 2006.173.11:12:59.88#ibcon#about to read 5, iclass 10, count 0 2006.173.11:12:59.88#ibcon#read 5, iclass 10, count 0 2006.173.11:12:59.88#ibcon#about to read 6, iclass 10, count 0 2006.173.11:12:59.88#ibcon#read 6, iclass 10, count 0 2006.173.11:12:59.88#ibcon#end of sib2, iclass 10, count 0 2006.173.11:12:59.88#ibcon#*mode == 0, iclass 10, count 0 2006.173.11:12:59.88#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.11:12:59.88#ibcon#[27=USB\r\n] 2006.173.11:12:59.88#ibcon#*before write, iclass 10, count 0 2006.173.11:12:59.88#ibcon#enter sib2, iclass 10, count 0 2006.173.11:12:59.88#ibcon#flushed, iclass 10, count 0 2006.173.11:12:59.88#ibcon#about to write, iclass 10, count 0 2006.173.11:12:59.88#ibcon#wrote, iclass 10, count 0 2006.173.11:12:59.88#ibcon#about to read 3, iclass 10, count 0 2006.173.11:12:59.91#ibcon#read 3, iclass 10, count 0 2006.173.11:12:59.91#ibcon#about to read 4, iclass 10, count 0 2006.173.11:12:59.91#ibcon#read 4, iclass 10, count 0 2006.173.11:12:59.91#ibcon#about to read 5, iclass 10, count 0 2006.173.11:12:59.91#ibcon#read 5, iclass 10, count 0 2006.173.11:12:59.91#ibcon#about to read 6, iclass 10, count 0 2006.173.11:12:59.91#ibcon#read 6, iclass 10, count 0 2006.173.11:12:59.91#ibcon#end of sib2, iclass 10, count 0 2006.173.11:12:59.91#ibcon#*after write, iclass 10, count 0 2006.173.11:12:59.91#ibcon#*before return 0, iclass 10, count 0 2006.173.11:12:59.91#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.11:12:59.91#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.11:12:59.91#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.11:12:59.91#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.11:12:59.91$vck44/vblo=7,734.99 2006.173.11:12:59.91#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.11:12:59.91#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.11:12:59.91#ibcon#ireg 17 cls_cnt 0 2006.173.11:12:59.91#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.11:12:59.91#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.11:12:59.91#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.11:12:59.91#ibcon#enter wrdev, iclass 12, count 0 2006.173.11:12:59.91#ibcon#first serial, iclass 12, count 0 2006.173.11:12:59.91#ibcon#enter sib2, iclass 12, count 0 2006.173.11:12:59.91#ibcon#flushed, iclass 12, count 0 2006.173.11:12:59.91#ibcon#about to write, iclass 12, count 0 2006.173.11:12:59.91#ibcon#wrote, iclass 12, count 0 2006.173.11:12:59.91#ibcon#about to read 3, iclass 12, count 0 2006.173.11:12:59.93#ibcon#read 3, iclass 12, count 0 2006.173.11:12:59.93#ibcon#about to read 4, iclass 12, count 0 2006.173.11:12:59.93#ibcon#read 4, iclass 12, count 0 2006.173.11:12:59.93#ibcon#about to read 5, iclass 12, count 0 2006.173.11:12:59.93#ibcon#read 5, iclass 12, count 0 2006.173.11:12:59.93#ibcon#about to read 6, iclass 12, count 0 2006.173.11:12:59.93#ibcon#read 6, iclass 12, count 0 2006.173.11:12:59.93#ibcon#end of sib2, iclass 12, count 0 2006.173.11:12:59.93#ibcon#*mode == 0, iclass 12, count 0 2006.173.11:12:59.93#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.11:12:59.93#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.11:12:59.93#ibcon#*before write, iclass 12, count 0 2006.173.11:12:59.93#ibcon#enter sib2, iclass 12, count 0 2006.173.11:12:59.93#ibcon#flushed, iclass 12, count 0 2006.173.11:12:59.93#ibcon#about to write, iclass 12, count 0 2006.173.11:12:59.93#ibcon#wrote, iclass 12, count 0 2006.173.11:12:59.93#ibcon#about to read 3, iclass 12, count 0 2006.173.11:12:59.97#ibcon#read 3, iclass 12, count 0 2006.173.11:12:59.97#ibcon#about to read 4, iclass 12, count 0 2006.173.11:12:59.97#ibcon#read 4, iclass 12, count 0 2006.173.11:12:59.97#ibcon#about to read 5, iclass 12, count 0 2006.173.11:12:59.97#ibcon#read 5, iclass 12, count 0 2006.173.11:12:59.97#ibcon#about to read 6, iclass 12, count 0 2006.173.11:12:59.97#ibcon#read 6, iclass 12, count 0 2006.173.11:12:59.97#ibcon#end of sib2, iclass 12, count 0 2006.173.11:12:59.97#ibcon#*after write, iclass 12, count 0 2006.173.11:12:59.97#ibcon#*before return 0, iclass 12, count 0 2006.173.11:12:59.97#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.11:12:59.97#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.11:12:59.97#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.11:12:59.97#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.11:12:59.97$vck44/vb=7,4 2006.173.11:12:59.97#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.11:12:59.97#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.11:12:59.97#ibcon#ireg 11 cls_cnt 2 2006.173.11:12:59.97#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.11:13:00.03#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.11:13:00.03#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.11:13:00.03#ibcon#enter wrdev, iclass 14, count 2 2006.173.11:13:00.03#ibcon#first serial, iclass 14, count 2 2006.173.11:13:00.03#ibcon#enter sib2, iclass 14, count 2 2006.173.11:13:00.03#ibcon#flushed, iclass 14, count 2 2006.173.11:13:00.03#ibcon#about to write, iclass 14, count 2 2006.173.11:13:00.03#ibcon#wrote, iclass 14, count 2 2006.173.11:13:00.03#ibcon#about to read 3, iclass 14, count 2 2006.173.11:13:00.05#ibcon#read 3, iclass 14, count 2 2006.173.11:13:00.05#ibcon#about to read 4, iclass 14, count 2 2006.173.11:13:00.05#ibcon#read 4, iclass 14, count 2 2006.173.11:13:00.05#ibcon#about to read 5, iclass 14, count 2 2006.173.11:13:00.05#ibcon#read 5, iclass 14, count 2 2006.173.11:13:00.05#ibcon#about to read 6, iclass 14, count 2 2006.173.11:13:00.05#ibcon#read 6, iclass 14, count 2 2006.173.11:13:00.05#ibcon#end of sib2, iclass 14, count 2 2006.173.11:13:00.05#ibcon#*mode == 0, iclass 14, count 2 2006.173.11:13:00.05#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.11:13:00.05#ibcon#[27=AT07-04\r\n] 2006.173.11:13:00.05#ibcon#*before write, iclass 14, count 2 2006.173.11:13:00.05#ibcon#enter sib2, iclass 14, count 2 2006.173.11:13:00.05#ibcon#flushed, iclass 14, count 2 2006.173.11:13:00.05#ibcon#about to write, iclass 14, count 2 2006.173.11:13:00.05#ibcon#wrote, iclass 14, count 2 2006.173.11:13:00.05#ibcon#about to read 3, iclass 14, count 2 2006.173.11:13:00.08#ibcon#read 3, iclass 14, count 2 2006.173.11:13:00.08#ibcon#about to read 4, iclass 14, count 2 2006.173.11:13:00.08#ibcon#read 4, iclass 14, count 2 2006.173.11:13:00.08#ibcon#about to read 5, iclass 14, count 2 2006.173.11:13:00.08#ibcon#read 5, iclass 14, count 2 2006.173.11:13:00.08#ibcon#about to read 6, iclass 14, count 2 2006.173.11:13:00.08#ibcon#read 6, iclass 14, count 2 2006.173.11:13:00.08#ibcon#end of sib2, iclass 14, count 2 2006.173.11:13:00.08#ibcon#*after write, iclass 14, count 2 2006.173.11:13:00.08#ibcon#*before return 0, iclass 14, count 2 2006.173.11:13:00.08#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.11:13:00.08#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.11:13:00.08#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.11:13:00.08#ibcon#ireg 7 cls_cnt 0 2006.173.11:13:00.08#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.11:13:00.20#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.11:13:00.20#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.11:13:00.20#ibcon#enter wrdev, iclass 14, count 0 2006.173.11:13:00.20#ibcon#first serial, iclass 14, count 0 2006.173.11:13:00.20#ibcon#enter sib2, iclass 14, count 0 2006.173.11:13:00.20#ibcon#flushed, iclass 14, count 0 2006.173.11:13:00.20#ibcon#about to write, iclass 14, count 0 2006.173.11:13:00.20#ibcon#wrote, iclass 14, count 0 2006.173.11:13:00.20#ibcon#about to read 3, iclass 14, count 0 2006.173.11:13:00.22#ibcon#read 3, iclass 14, count 0 2006.173.11:13:00.22#ibcon#about to read 4, iclass 14, count 0 2006.173.11:13:00.22#ibcon#read 4, iclass 14, count 0 2006.173.11:13:00.22#ibcon#about to read 5, iclass 14, count 0 2006.173.11:13:00.22#ibcon#read 5, iclass 14, count 0 2006.173.11:13:00.22#ibcon#about to read 6, iclass 14, count 0 2006.173.11:13:00.22#ibcon#read 6, iclass 14, count 0 2006.173.11:13:00.22#ibcon#end of sib2, iclass 14, count 0 2006.173.11:13:00.22#ibcon#*mode == 0, iclass 14, count 0 2006.173.11:13:00.22#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.11:13:00.22#ibcon#[27=USB\r\n] 2006.173.11:13:00.22#ibcon#*before write, iclass 14, count 0 2006.173.11:13:00.22#ibcon#enter sib2, iclass 14, count 0 2006.173.11:13:00.22#ibcon#flushed, iclass 14, count 0 2006.173.11:13:00.22#ibcon#about to write, iclass 14, count 0 2006.173.11:13:00.22#ibcon#wrote, iclass 14, count 0 2006.173.11:13:00.22#ibcon#about to read 3, iclass 14, count 0 2006.173.11:13:00.25#ibcon#read 3, iclass 14, count 0 2006.173.11:13:00.25#ibcon#about to read 4, iclass 14, count 0 2006.173.11:13:00.25#ibcon#read 4, iclass 14, count 0 2006.173.11:13:00.25#ibcon#about to read 5, iclass 14, count 0 2006.173.11:13:00.25#ibcon#read 5, iclass 14, count 0 2006.173.11:13:00.25#ibcon#about to read 6, iclass 14, count 0 2006.173.11:13:00.25#ibcon#read 6, iclass 14, count 0 2006.173.11:13:00.25#ibcon#end of sib2, iclass 14, count 0 2006.173.11:13:00.25#ibcon#*after write, iclass 14, count 0 2006.173.11:13:00.25#ibcon#*before return 0, iclass 14, count 0 2006.173.11:13:00.25#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.11:13:00.25#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.11:13:00.25#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.11:13:00.25#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.11:13:00.25$vck44/vblo=8,744.99 2006.173.11:13:00.25#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.11:13:00.25#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.11:13:00.25#ibcon#ireg 17 cls_cnt 0 2006.173.11:13:00.25#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.11:13:00.25#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.11:13:00.25#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.11:13:00.25#ibcon#enter wrdev, iclass 16, count 0 2006.173.11:13:00.25#ibcon#first serial, iclass 16, count 0 2006.173.11:13:00.25#ibcon#enter sib2, iclass 16, count 0 2006.173.11:13:00.25#ibcon#flushed, iclass 16, count 0 2006.173.11:13:00.25#ibcon#about to write, iclass 16, count 0 2006.173.11:13:00.25#ibcon#wrote, iclass 16, count 0 2006.173.11:13:00.25#ibcon#about to read 3, iclass 16, count 0 2006.173.11:13:00.27#ibcon#read 3, iclass 16, count 0 2006.173.11:13:00.27#ibcon#about to read 4, iclass 16, count 0 2006.173.11:13:00.27#ibcon#read 4, iclass 16, count 0 2006.173.11:13:00.27#ibcon#about to read 5, iclass 16, count 0 2006.173.11:13:00.27#ibcon#read 5, iclass 16, count 0 2006.173.11:13:00.27#ibcon#about to read 6, iclass 16, count 0 2006.173.11:13:00.27#ibcon#read 6, iclass 16, count 0 2006.173.11:13:00.27#ibcon#end of sib2, iclass 16, count 0 2006.173.11:13:00.27#ibcon#*mode == 0, iclass 16, count 0 2006.173.11:13:00.27#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.11:13:00.27#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.11:13:00.27#ibcon#*before write, iclass 16, count 0 2006.173.11:13:00.27#ibcon#enter sib2, iclass 16, count 0 2006.173.11:13:00.27#ibcon#flushed, iclass 16, count 0 2006.173.11:13:00.27#ibcon#about to write, iclass 16, count 0 2006.173.11:13:00.27#ibcon#wrote, iclass 16, count 0 2006.173.11:13:00.27#ibcon#about to read 3, iclass 16, count 0 2006.173.11:13:00.31#ibcon#read 3, iclass 16, count 0 2006.173.11:13:00.31#ibcon#about to read 4, iclass 16, count 0 2006.173.11:13:00.31#ibcon#read 4, iclass 16, count 0 2006.173.11:13:00.31#ibcon#about to read 5, iclass 16, count 0 2006.173.11:13:00.31#ibcon#read 5, iclass 16, count 0 2006.173.11:13:00.31#ibcon#about to read 6, iclass 16, count 0 2006.173.11:13:00.31#ibcon#read 6, iclass 16, count 0 2006.173.11:13:00.31#ibcon#end of sib2, iclass 16, count 0 2006.173.11:13:00.31#ibcon#*after write, iclass 16, count 0 2006.173.11:13:00.31#ibcon#*before return 0, iclass 16, count 0 2006.173.11:13:00.31#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.11:13:00.31#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.11:13:00.31#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.11:13:00.31#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.11:13:00.31$vck44/vb=8,4 2006.173.11:13:00.31#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.11:13:00.31#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.11:13:00.31#ibcon#ireg 11 cls_cnt 2 2006.173.11:13:00.31#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.11:13:00.37#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.11:13:00.37#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.11:13:00.37#ibcon#enter wrdev, iclass 18, count 2 2006.173.11:13:00.37#ibcon#first serial, iclass 18, count 2 2006.173.11:13:00.37#ibcon#enter sib2, iclass 18, count 2 2006.173.11:13:00.37#ibcon#flushed, iclass 18, count 2 2006.173.11:13:00.37#ibcon#about to write, iclass 18, count 2 2006.173.11:13:00.37#ibcon#wrote, iclass 18, count 2 2006.173.11:13:00.37#ibcon#about to read 3, iclass 18, count 2 2006.173.11:13:00.39#ibcon#read 3, iclass 18, count 2 2006.173.11:13:00.39#ibcon#about to read 4, iclass 18, count 2 2006.173.11:13:00.39#ibcon#read 4, iclass 18, count 2 2006.173.11:13:00.39#ibcon#about to read 5, iclass 18, count 2 2006.173.11:13:00.39#ibcon#read 5, iclass 18, count 2 2006.173.11:13:00.39#ibcon#about to read 6, iclass 18, count 2 2006.173.11:13:00.39#ibcon#read 6, iclass 18, count 2 2006.173.11:13:00.39#ibcon#end of sib2, iclass 18, count 2 2006.173.11:13:00.39#ibcon#*mode == 0, iclass 18, count 2 2006.173.11:13:00.39#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.11:13:00.39#ibcon#[27=AT08-04\r\n] 2006.173.11:13:00.39#ibcon#*before write, iclass 18, count 2 2006.173.11:13:00.39#ibcon#enter sib2, iclass 18, count 2 2006.173.11:13:00.39#ibcon#flushed, iclass 18, count 2 2006.173.11:13:00.39#ibcon#about to write, iclass 18, count 2 2006.173.11:13:00.39#ibcon#wrote, iclass 18, count 2 2006.173.11:13:00.39#ibcon#about to read 3, iclass 18, count 2 2006.173.11:13:00.42#ibcon#read 3, iclass 18, count 2 2006.173.11:13:00.42#ibcon#about to read 4, iclass 18, count 2 2006.173.11:13:00.42#ibcon#read 4, iclass 18, count 2 2006.173.11:13:00.42#ibcon#about to read 5, iclass 18, count 2 2006.173.11:13:00.42#ibcon#read 5, iclass 18, count 2 2006.173.11:13:00.42#ibcon#about to read 6, iclass 18, count 2 2006.173.11:13:00.42#ibcon#read 6, iclass 18, count 2 2006.173.11:13:00.42#ibcon#end of sib2, iclass 18, count 2 2006.173.11:13:00.42#ibcon#*after write, iclass 18, count 2 2006.173.11:13:00.42#ibcon#*before return 0, iclass 18, count 2 2006.173.11:13:00.42#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.11:13:00.42#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.11:13:00.42#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.11:13:00.42#ibcon#ireg 7 cls_cnt 0 2006.173.11:13:00.42#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.11:13:00.54#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.11:13:00.54#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.11:13:00.54#ibcon#enter wrdev, iclass 18, count 0 2006.173.11:13:00.54#ibcon#first serial, iclass 18, count 0 2006.173.11:13:00.54#ibcon#enter sib2, iclass 18, count 0 2006.173.11:13:00.54#ibcon#flushed, iclass 18, count 0 2006.173.11:13:00.54#ibcon#about to write, iclass 18, count 0 2006.173.11:13:00.54#ibcon#wrote, iclass 18, count 0 2006.173.11:13:00.54#ibcon#about to read 3, iclass 18, count 0 2006.173.11:13:00.56#ibcon#read 3, iclass 18, count 0 2006.173.11:13:00.56#ibcon#about to read 4, iclass 18, count 0 2006.173.11:13:00.56#ibcon#read 4, iclass 18, count 0 2006.173.11:13:00.56#ibcon#about to read 5, iclass 18, count 0 2006.173.11:13:00.56#ibcon#read 5, iclass 18, count 0 2006.173.11:13:00.56#ibcon#about to read 6, iclass 18, count 0 2006.173.11:13:00.56#ibcon#read 6, iclass 18, count 0 2006.173.11:13:00.56#ibcon#end of sib2, iclass 18, count 0 2006.173.11:13:00.56#ibcon#*mode == 0, iclass 18, count 0 2006.173.11:13:00.56#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.11:13:00.56#ibcon#[27=USB\r\n] 2006.173.11:13:00.56#ibcon#*before write, iclass 18, count 0 2006.173.11:13:00.56#ibcon#enter sib2, iclass 18, count 0 2006.173.11:13:00.56#ibcon#flushed, iclass 18, count 0 2006.173.11:13:00.56#ibcon#about to write, iclass 18, count 0 2006.173.11:13:00.56#ibcon#wrote, iclass 18, count 0 2006.173.11:13:00.56#ibcon#about to read 3, iclass 18, count 0 2006.173.11:13:00.59#ibcon#read 3, iclass 18, count 0 2006.173.11:13:00.59#ibcon#about to read 4, iclass 18, count 0 2006.173.11:13:00.59#ibcon#read 4, iclass 18, count 0 2006.173.11:13:00.59#ibcon#about to read 5, iclass 18, count 0 2006.173.11:13:00.59#ibcon#read 5, iclass 18, count 0 2006.173.11:13:00.59#ibcon#about to read 6, iclass 18, count 0 2006.173.11:13:00.59#ibcon#read 6, iclass 18, count 0 2006.173.11:13:00.59#ibcon#end of sib2, iclass 18, count 0 2006.173.11:13:00.59#ibcon#*after write, iclass 18, count 0 2006.173.11:13:00.59#ibcon#*before return 0, iclass 18, count 0 2006.173.11:13:00.59#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.11:13:00.59#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.11:13:00.59#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.11:13:00.59#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.11:13:00.59$vck44/vabw=wide 2006.173.11:13:00.59#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.11:13:00.59#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.11:13:00.59#ibcon#ireg 8 cls_cnt 0 2006.173.11:13:00.59#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.11:13:00.59#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.11:13:00.59#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.11:13:00.59#ibcon#enter wrdev, iclass 20, count 0 2006.173.11:13:00.59#ibcon#first serial, iclass 20, count 0 2006.173.11:13:00.59#ibcon#enter sib2, iclass 20, count 0 2006.173.11:13:00.59#ibcon#flushed, iclass 20, count 0 2006.173.11:13:00.59#ibcon#about to write, iclass 20, count 0 2006.173.11:13:00.59#ibcon#wrote, iclass 20, count 0 2006.173.11:13:00.59#ibcon#about to read 3, iclass 20, count 0 2006.173.11:13:00.61#ibcon#read 3, iclass 20, count 0 2006.173.11:13:00.61#ibcon#about to read 4, iclass 20, count 0 2006.173.11:13:00.61#ibcon#read 4, iclass 20, count 0 2006.173.11:13:00.61#ibcon#about to read 5, iclass 20, count 0 2006.173.11:13:00.61#ibcon#read 5, iclass 20, count 0 2006.173.11:13:00.61#ibcon#about to read 6, iclass 20, count 0 2006.173.11:13:00.61#ibcon#read 6, iclass 20, count 0 2006.173.11:13:00.61#ibcon#end of sib2, iclass 20, count 0 2006.173.11:13:00.61#ibcon#*mode == 0, iclass 20, count 0 2006.173.11:13:00.61#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.11:13:00.61#ibcon#[25=BW32\r\n] 2006.173.11:13:00.61#ibcon#*before write, iclass 20, count 0 2006.173.11:13:00.61#ibcon#enter sib2, iclass 20, count 0 2006.173.11:13:00.61#ibcon#flushed, iclass 20, count 0 2006.173.11:13:00.61#ibcon#about to write, iclass 20, count 0 2006.173.11:13:00.61#ibcon#wrote, iclass 20, count 0 2006.173.11:13:00.61#ibcon#about to read 3, iclass 20, count 0 2006.173.11:13:00.64#ibcon#read 3, iclass 20, count 0 2006.173.11:13:00.64#ibcon#about to read 4, iclass 20, count 0 2006.173.11:13:00.64#ibcon#read 4, iclass 20, count 0 2006.173.11:13:00.64#ibcon#about to read 5, iclass 20, count 0 2006.173.11:13:00.64#ibcon#read 5, iclass 20, count 0 2006.173.11:13:00.64#ibcon#about to read 6, iclass 20, count 0 2006.173.11:13:00.64#ibcon#read 6, iclass 20, count 0 2006.173.11:13:00.64#ibcon#end of sib2, iclass 20, count 0 2006.173.11:13:00.64#ibcon#*after write, iclass 20, count 0 2006.173.11:13:00.64#ibcon#*before return 0, iclass 20, count 0 2006.173.11:13:00.64#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.11:13:00.64#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.11:13:00.64#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.11:13:00.64#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.11:13:00.64$vck44/vbbw=wide 2006.173.11:13:00.64#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.11:13:00.64#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.11:13:00.64#ibcon#ireg 8 cls_cnt 0 2006.173.11:13:00.64#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.11:13:00.71#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.11:13:00.71#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.11:13:00.71#ibcon#enter wrdev, iclass 22, count 0 2006.173.11:13:00.71#ibcon#first serial, iclass 22, count 0 2006.173.11:13:00.71#ibcon#enter sib2, iclass 22, count 0 2006.173.11:13:00.71#ibcon#flushed, iclass 22, count 0 2006.173.11:13:00.71#ibcon#about to write, iclass 22, count 0 2006.173.11:13:00.71#ibcon#wrote, iclass 22, count 0 2006.173.11:13:00.71#ibcon#about to read 3, iclass 22, count 0 2006.173.11:13:00.73#ibcon#read 3, iclass 22, count 0 2006.173.11:13:00.73#ibcon#about to read 4, iclass 22, count 0 2006.173.11:13:00.73#ibcon#read 4, iclass 22, count 0 2006.173.11:13:00.73#ibcon#about to read 5, iclass 22, count 0 2006.173.11:13:00.73#ibcon#read 5, iclass 22, count 0 2006.173.11:13:00.73#ibcon#about to read 6, iclass 22, count 0 2006.173.11:13:00.73#ibcon#read 6, iclass 22, count 0 2006.173.11:13:00.73#ibcon#end of sib2, iclass 22, count 0 2006.173.11:13:00.73#ibcon#*mode == 0, iclass 22, count 0 2006.173.11:13:00.73#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.11:13:00.73#ibcon#[27=BW32\r\n] 2006.173.11:13:00.73#ibcon#*before write, iclass 22, count 0 2006.173.11:13:00.73#ibcon#enter sib2, iclass 22, count 0 2006.173.11:13:00.73#ibcon#flushed, iclass 22, count 0 2006.173.11:13:00.73#ibcon#about to write, iclass 22, count 0 2006.173.11:13:00.73#ibcon#wrote, iclass 22, count 0 2006.173.11:13:00.73#ibcon#about to read 3, iclass 22, count 0 2006.173.11:13:00.76#ibcon#read 3, iclass 22, count 0 2006.173.11:13:00.76#ibcon#about to read 4, iclass 22, count 0 2006.173.11:13:00.76#ibcon#read 4, iclass 22, count 0 2006.173.11:13:00.76#ibcon#about to read 5, iclass 22, count 0 2006.173.11:13:00.76#ibcon#read 5, iclass 22, count 0 2006.173.11:13:00.76#ibcon#about to read 6, iclass 22, count 0 2006.173.11:13:00.76#ibcon#read 6, iclass 22, count 0 2006.173.11:13:00.76#ibcon#end of sib2, iclass 22, count 0 2006.173.11:13:00.76#ibcon#*after write, iclass 22, count 0 2006.173.11:13:00.76#ibcon#*before return 0, iclass 22, count 0 2006.173.11:13:00.76#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.11:13:00.76#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.11:13:00.76#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.11:13:00.76#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.11:13:00.76$setupk4/ifdk4 2006.173.11:13:00.76$ifdk4/lo= 2006.173.11:13:00.76$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.11:13:00.76$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.11:13:00.76$ifdk4/patch= 2006.173.11:13:00.76$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.11:13:00.76$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.11:13:00.76$setupk4/!*+20s 2006.173.11:13:08.32#abcon#<5=/03 0.5 1.4 22.48 921004.3\r\n> 2006.173.11:13:08.34#abcon#{5=INTERFACE CLEAR} 2006.173.11:13:08.40#abcon#[5=S1D000X0/0*\r\n] 2006.173.11:13:12.14#trakl#Source acquired 2006.173.11:13:12.14#flagr#flagr/antenna,acquired 2006.173.11:13:15.27$setupk4/"tpicd 2006.173.11:13:15.27$setupk4/echo=off 2006.173.11:13:15.27$setupk4/xlog=off 2006.173.11:13:15.27:!2006.173.11:18:12 2006.173.11:18:12.00:preob 2006.173.11:18:13.14/onsource/TRACKING 2006.173.11:18:13.14:!2006.173.11:18:22 2006.173.11:18:22.00:"tape 2006.173.11:18:22.00:"st=record 2006.173.11:18:22.00:data_valid=on 2006.173.11:18:22.00:midob 2006.173.11:18:22.14/onsource/TRACKING 2006.173.11:18:22.14/wx/22.51,1004.1,93 2006.173.11:18:22.29/cable/+6.5010E-03 2006.173.11:18:23.38/va/01,07,usb,yes,34,37 2006.173.11:18:23.38/va/02,06,usb,yes,34,35 2006.173.11:18:23.38/va/03,05,usb,yes,43,45 2006.173.11:18:23.38/va/04,06,usb,yes,35,36 2006.173.11:18:23.38/va/05,04,usb,yes,27,28 2006.173.11:18:23.38/va/06,03,usb,yes,38,38 2006.173.11:18:23.38/va/07,04,usb,yes,31,32 2006.173.11:18:23.38/va/08,04,usb,yes,26,32 2006.173.11:18:23.61/valo/01,524.99,yes,locked 2006.173.11:18:23.61/valo/02,534.99,yes,locked 2006.173.11:18:23.61/valo/03,564.99,yes,locked 2006.173.11:18:23.61/valo/04,624.99,yes,locked 2006.173.11:18:23.61/valo/05,734.99,yes,locked 2006.173.11:18:23.61/valo/06,814.99,yes,locked 2006.173.11:18:23.61/valo/07,864.99,yes,locked 2006.173.11:18:23.61/valo/08,884.99,yes,locked 2006.173.11:18:24.70/vb/01,04,usb,yes,28,26 2006.173.11:18:24.70/vb/02,04,usb,yes,31,31 2006.173.11:18:24.70/vb/03,04,usb,yes,28,31 2006.173.11:18:24.70/vb/04,04,usb,yes,32,31 2006.173.11:18:24.70/vb/05,04,usb,yes,25,27 2006.173.11:18:24.70/vb/06,04,usb,yes,29,25 2006.173.11:18:24.70/vb/07,04,usb,yes,29,29 2006.173.11:18:24.70/vb/08,04,usb,yes,26,30 2006.173.11:18:24.93/vblo/01,629.99,yes,locked 2006.173.11:18:24.93/vblo/02,634.99,yes,locked 2006.173.11:18:24.93/vblo/03,649.99,yes,locked 2006.173.11:18:24.93/vblo/04,679.99,yes,locked 2006.173.11:18:24.93/vblo/05,709.99,yes,locked 2006.173.11:18:24.93/vblo/06,719.99,yes,locked 2006.173.11:18:24.93/vblo/07,734.99,yes,locked 2006.173.11:18:24.93/vblo/08,744.99,yes,locked 2006.173.11:18:25.08/vabw/8 2006.173.11:18:25.23/vbbw/8 2006.173.11:18:25.32/xfe/off,on,15.0 2006.173.11:18:25.69/ifatt/23,28,28,28 2006.173.11:18:26.07/fmout-gps/S +3.98E-07 2006.173.11:18:26.11:!2006.173.11:24:02 2006.173.11:24:02.00:data_valid=off 2006.173.11:24:02.00:"et 2006.173.11:24:02.00:!+3s 2006.173.11:24:05.01:"tape 2006.173.11:24:05.01:postob 2006.173.11:24:05.20/cable/+6.5022E-03 2006.173.11:24:05.20/wx/22.51,1003.7,93 2006.173.11:24:06.07/fmout-gps/S +3.97E-07 2006.173.11:24:06.07:scan_name=173-1132,jd0606,40 2006.173.11:24:06.07:source=1908-201,191109.65,-200655.1,2000.0,cw 2006.173.11:24:07.14#flagr#flagr/antenna,new-source 2006.173.11:24:07.14:checkk5 2006.173.11:24:07.55/chk_autoobs//k5ts1/ autoobs is running! 2006.173.11:24:07.94/chk_autoobs//k5ts2/ autoobs is running! 2006.173.11:24:08.35/chk_autoobs//k5ts3/ autoobs is running! 2006.173.11:24:08.74/chk_autoobs//k5ts4/ autoobs is running! 2006.173.11:24:09.12/chk_obsdata//k5ts1/T1731118??a.dat file size is correct (nominal:1360MB, actual:1356MB). 2006.173.11:24:09.51/chk_obsdata//k5ts2/T1731118??b.dat file size is correct (nominal:1360MB, actual:1356MB). 2006.173.11:24:09.93/chk_obsdata//k5ts3/T1731118??c.dat file size is correct (nominal:1360MB, actual:1356MB). 2006.173.11:24:10.33/chk_obsdata//k5ts4/T1731118??d.dat file size is correct (nominal:1360MB, actual:1356MB). 2006.173.11:24:11.07/k5log//k5ts1_log_newline 2006.173.11:24:11.78/k5log//k5ts2_log_newline 2006.173.11:24:12.51/k5log//k5ts3_log_newline 2006.173.11:24:13.22/k5log//k5ts4_log_newline 2006.173.11:24:13.24/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.11:24:13.24:setupk4=1 2006.173.11:24:13.24$setupk4/echo=on 2006.173.11:24:13.25$setupk4/pcalon 2006.173.11:24:13.25$pcalon/"no phase cal control is implemented here 2006.173.11:24:13.25$setupk4/"tpicd=stop 2006.173.11:24:13.25$setupk4/"rec=synch_on 2006.173.11:24:13.25$setupk4/"rec_mode=128 2006.173.11:24:13.25$setupk4/!* 2006.173.11:24:13.25$setupk4/recpk4 2006.173.11:24:13.25$recpk4/recpatch= 2006.173.11:24:13.25$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.11:24:13.25$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.11:24:13.25$setupk4/vck44 2006.173.11:24:13.25$vck44/valo=1,524.99 2006.173.11:24:13.25#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.11:24:13.25#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.11:24:13.25#ibcon#ireg 17 cls_cnt 0 2006.173.11:24:13.25#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.11:24:13.25#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.11:24:13.25#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.11:24:13.25#ibcon#enter wrdev, iclass 39, count 0 2006.173.11:24:13.25#ibcon#first serial, iclass 39, count 0 2006.173.11:24:13.25#ibcon#enter sib2, iclass 39, count 0 2006.173.11:24:13.25#ibcon#flushed, iclass 39, count 0 2006.173.11:24:13.25#ibcon#about to write, iclass 39, count 0 2006.173.11:24:13.25#ibcon#wrote, iclass 39, count 0 2006.173.11:24:13.25#ibcon#about to read 3, iclass 39, count 0 2006.173.11:24:13.27#ibcon#read 3, iclass 39, count 0 2006.173.11:24:13.27#ibcon#about to read 4, iclass 39, count 0 2006.173.11:24:13.27#ibcon#read 4, iclass 39, count 0 2006.173.11:24:13.27#ibcon#about to read 5, iclass 39, count 0 2006.173.11:24:13.27#ibcon#read 5, iclass 39, count 0 2006.173.11:24:13.27#ibcon#about to read 6, iclass 39, count 0 2006.173.11:24:13.27#ibcon#read 6, iclass 39, count 0 2006.173.11:24:13.27#ibcon#end of sib2, iclass 39, count 0 2006.173.11:24:13.27#ibcon#*mode == 0, iclass 39, count 0 2006.173.11:24:13.27#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.11:24:13.27#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.11:24:13.27#ibcon#*before write, iclass 39, count 0 2006.173.11:24:13.27#ibcon#enter sib2, iclass 39, count 0 2006.173.11:24:13.27#ibcon#flushed, iclass 39, count 0 2006.173.11:24:13.27#ibcon#about to write, iclass 39, count 0 2006.173.11:24:13.27#ibcon#wrote, iclass 39, count 0 2006.173.11:24:13.27#ibcon#about to read 3, iclass 39, count 0 2006.173.11:24:13.32#ibcon#read 3, iclass 39, count 0 2006.173.11:24:13.32#ibcon#about to read 4, iclass 39, count 0 2006.173.11:24:13.32#ibcon#read 4, iclass 39, count 0 2006.173.11:24:13.32#ibcon#about to read 5, iclass 39, count 0 2006.173.11:24:13.32#ibcon#read 5, iclass 39, count 0 2006.173.11:24:13.32#ibcon#about to read 6, iclass 39, count 0 2006.173.11:24:13.32#ibcon#read 6, iclass 39, count 0 2006.173.11:24:13.32#ibcon#end of sib2, iclass 39, count 0 2006.173.11:24:13.32#ibcon#*after write, iclass 39, count 0 2006.173.11:24:13.32#ibcon#*before return 0, iclass 39, count 0 2006.173.11:24:13.32#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.11:24:13.32#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.11:24:13.32#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.11:24:13.32#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.11:24:13.32$vck44/va=1,7 2006.173.11:24:13.32#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.11:24:13.32#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.11:24:13.32#ibcon#ireg 11 cls_cnt 2 2006.173.11:24:13.32#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.11:24:13.32#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.11:24:13.32#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.11:24:13.32#ibcon#enter wrdev, iclass 3, count 2 2006.173.11:24:13.32#ibcon#first serial, iclass 3, count 2 2006.173.11:24:13.32#ibcon#enter sib2, iclass 3, count 2 2006.173.11:24:13.32#ibcon#flushed, iclass 3, count 2 2006.173.11:24:13.32#ibcon#about to write, iclass 3, count 2 2006.173.11:24:13.32#ibcon#wrote, iclass 3, count 2 2006.173.11:24:13.32#ibcon#about to read 3, iclass 3, count 2 2006.173.11:24:13.34#ibcon#read 3, iclass 3, count 2 2006.173.11:24:13.34#ibcon#about to read 4, iclass 3, count 2 2006.173.11:24:13.34#ibcon#read 4, iclass 3, count 2 2006.173.11:24:13.34#ibcon#about to read 5, iclass 3, count 2 2006.173.11:24:13.34#ibcon#read 5, iclass 3, count 2 2006.173.11:24:13.34#ibcon#about to read 6, iclass 3, count 2 2006.173.11:24:13.34#ibcon#read 6, iclass 3, count 2 2006.173.11:24:13.34#ibcon#end of sib2, iclass 3, count 2 2006.173.11:24:13.34#ibcon#*mode == 0, iclass 3, count 2 2006.173.11:24:13.34#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.11:24:13.34#ibcon#[25=AT01-07\r\n] 2006.173.11:24:13.34#ibcon#*before write, iclass 3, count 2 2006.173.11:24:13.34#ibcon#enter sib2, iclass 3, count 2 2006.173.11:24:13.34#ibcon#flushed, iclass 3, count 2 2006.173.11:24:13.34#ibcon#about to write, iclass 3, count 2 2006.173.11:24:13.34#ibcon#wrote, iclass 3, count 2 2006.173.11:24:13.34#ibcon#about to read 3, iclass 3, count 2 2006.173.11:24:13.37#ibcon#read 3, iclass 3, count 2 2006.173.11:24:13.37#ibcon#about to read 4, iclass 3, count 2 2006.173.11:24:13.37#ibcon#read 4, iclass 3, count 2 2006.173.11:24:13.37#ibcon#about to read 5, iclass 3, count 2 2006.173.11:24:13.37#ibcon#read 5, iclass 3, count 2 2006.173.11:24:13.37#ibcon#about to read 6, iclass 3, count 2 2006.173.11:24:13.37#ibcon#read 6, iclass 3, count 2 2006.173.11:24:13.37#ibcon#end of sib2, iclass 3, count 2 2006.173.11:24:13.37#ibcon#*after write, iclass 3, count 2 2006.173.11:24:13.37#ibcon#*before return 0, iclass 3, count 2 2006.173.11:24:13.37#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.11:24:13.37#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.11:24:13.37#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.11:24:13.37#ibcon#ireg 7 cls_cnt 0 2006.173.11:24:13.37#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.11:24:13.49#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.11:24:13.49#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.11:24:13.49#ibcon#enter wrdev, iclass 3, count 0 2006.173.11:24:13.49#ibcon#first serial, iclass 3, count 0 2006.173.11:24:13.49#ibcon#enter sib2, iclass 3, count 0 2006.173.11:24:13.49#ibcon#flushed, iclass 3, count 0 2006.173.11:24:13.49#ibcon#about to write, iclass 3, count 0 2006.173.11:24:13.49#ibcon#wrote, iclass 3, count 0 2006.173.11:24:13.49#ibcon#about to read 3, iclass 3, count 0 2006.173.11:24:13.51#ibcon#read 3, iclass 3, count 0 2006.173.11:24:13.51#ibcon#about to read 4, iclass 3, count 0 2006.173.11:24:13.51#ibcon#read 4, iclass 3, count 0 2006.173.11:24:13.51#ibcon#about to read 5, iclass 3, count 0 2006.173.11:24:13.51#ibcon#read 5, iclass 3, count 0 2006.173.11:24:13.51#ibcon#about to read 6, iclass 3, count 0 2006.173.11:24:13.51#ibcon#read 6, iclass 3, count 0 2006.173.11:24:13.51#ibcon#end of sib2, iclass 3, count 0 2006.173.11:24:13.51#ibcon#*mode == 0, iclass 3, count 0 2006.173.11:24:13.51#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.11:24:13.51#ibcon#[25=USB\r\n] 2006.173.11:24:13.51#ibcon#*before write, iclass 3, count 0 2006.173.11:24:13.51#ibcon#enter sib2, iclass 3, count 0 2006.173.11:24:13.51#ibcon#flushed, iclass 3, count 0 2006.173.11:24:13.51#ibcon#about to write, iclass 3, count 0 2006.173.11:24:13.51#ibcon#wrote, iclass 3, count 0 2006.173.11:24:13.51#ibcon#about to read 3, iclass 3, count 0 2006.173.11:24:13.54#ibcon#read 3, iclass 3, count 0 2006.173.11:24:13.54#ibcon#about to read 4, iclass 3, count 0 2006.173.11:24:13.54#ibcon#read 4, iclass 3, count 0 2006.173.11:24:13.54#ibcon#about to read 5, iclass 3, count 0 2006.173.11:24:13.54#ibcon#read 5, iclass 3, count 0 2006.173.11:24:13.54#ibcon#about to read 6, iclass 3, count 0 2006.173.11:24:13.54#ibcon#read 6, iclass 3, count 0 2006.173.11:24:13.54#ibcon#end of sib2, iclass 3, count 0 2006.173.11:24:13.54#ibcon#*after write, iclass 3, count 0 2006.173.11:24:13.54#ibcon#*before return 0, iclass 3, count 0 2006.173.11:24:13.54#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.11:24:13.54#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.11:24:13.54#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.11:24:13.54#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.11:24:13.54$vck44/valo=2,534.99 2006.173.11:24:13.54#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.11:24:13.54#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.11:24:13.54#ibcon#ireg 17 cls_cnt 0 2006.173.11:24:13.54#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.11:24:13.54#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.11:24:13.54#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.11:24:13.54#ibcon#enter wrdev, iclass 5, count 0 2006.173.11:24:13.54#ibcon#first serial, iclass 5, count 0 2006.173.11:24:13.54#ibcon#enter sib2, iclass 5, count 0 2006.173.11:24:13.54#ibcon#flushed, iclass 5, count 0 2006.173.11:24:13.54#ibcon#about to write, iclass 5, count 0 2006.173.11:24:13.54#ibcon#wrote, iclass 5, count 0 2006.173.11:24:13.54#ibcon#about to read 3, iclass 5, count 0 2006.173.11:24:13.56#ibcon#read 3, iclass 5, count 0 2006.173.11:24:13.56#ibcon#about to read 4, iclass 5, count 0 2006.173.11:24:13.56#ibcon#read 4, iclass 5, count 0 2006.173.11:24:13.56#ibcon#about to read 5, iclass 5, count 0 2006.173.11:24:13.56#ibcon#read 5, iclass 5, count 0 2006.173.11:24:13.56#ibcon#about to read 6, iclass 5, count 0 2006.173.11:24:13.56#ibcon#read 6, iclass 5, count 0 2006.173.11:24:13.56#ibcon#end of sib2, iclass 5, count 0 2006.173.11:24:13.56#ibcon#*mode == 0, iclass 5, count 0 2006.173.11:24:13.56#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.11:24:13.56#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.11:24:13.56#ibcon#*before write, iclass 5, count 0 2006.173.11:24:13.56#ibcon#enter sib2, iclass 5, count 0 2006.173.11:24:13.56#ibcon#flushed, iclass 5, count 0 2006.173.11:24:13.56#ibcon#about to write, iclass 5, count 0 2006.173.11:24:13.56#ibcon#wrote, iclass 5, count 0 2006.173.11:24:13.56#ibcon#about to read 3, iclass 5, count 0 2006.173.11:24:13.60#ibcon#read 3, iclass 5, count 0 2006.173.11:24:13.60#ibcon#about to read 4, iclass 5, count 0 2006.173.11:24:13.60#ibcon#read 4, iclass 5, count 0 2006.173.11:24:13.60#ibcon#about to read 5, iclass 5, count 0 2006.173.11:24:13.60#ibcon#read 5, iclass 5, count 0 2006.173.11:24:13.60#ibcon#about to read 6, iclass 5, count 0 2006.173.11:24:13.60#ibcon#read 6, iclass 5, count 0 2006.173.11:24:13.60#ibcon#end of sib2, iclass 5, count 0 2006.173.11:24:13.60#ibcon#*after write, iclass 5, count 0 2006.173.11:24:13.60#ibcon#*before return 0, iclass 5, count 0 2006.173.11:24:13.60#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.11:24:13.60#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.11:24:13.60#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.11:24:13.60#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.11:24:13.60$vck44/va=2,6 2006.173.11:24:13.60#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.173.11:24:13.60#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.173.11:24:13.60#ibcon#ireg 11 cls_cnt 2 2006.173.11:24:13.60#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.11:24:13.66#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.11:24:13.66#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.11:24:13.66#ibcon#enter wrdev, iclass 7, count 2 2006.173.11:24:13.66#ibcon#first serial, iclass 7, count 2 2006.173.11:24:13.66#ibcon#enter sib2, iclass 7, count 2 2006.173.11:24:13.66#ibcon#flushed, iclass 7, count 2 2006.173.11:24:13.66#ibcon#about to write, iclass 7, count 2 2006.173.11:24:13.66#ibcon#wrote, iclass 7, count 2 2006.173.11:24:13.66#ibcon#about to read 3, iclass 7, count 2 2006.173.11:24:13.68#ibcon#read 3, iclass 7, count 2 2006.173.11:24:13.68#ibcon#about to read 4, iclass 7, count 2 2006.173.11:24:13.68#ibcon#read 4, iclass 7, count 2 2006.173.11:24:13.68#ibcon#about to read 5, iclass 7, count 2 2006.173.11:24:13.68#ibcon#read 5, iclass 7, count 2 2006.173.11:24:13.68#ibcon#about to read 6, iclass 7, count 2 2006.173.11:24:13.68#ibcon#read 6, iclass 7, count 2 2006.173.11:24:13.68#ibcon#end of sib2, iclass 7, count 2 2006.173.11:24:13.68#ibcon#*mode == 0, iclass 7, count 2 2006.173.11:24:13.68#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.173.11:24:13.68#ibcon#[25=AT02-06\r\n] 2006.173.11:24:13.68#ibcon#*before write, iclass 7, count 2 2006.173.11:24:13.68#ibcon#enter sib2, iclass 7, count 2 2006.173.11:24:13.68#ibcon#flushed, iclass 7, count 2 2006.173.11:24:13.68#ibcon#about to write, iclass 7, count 2 2006.173.11:24:13.68#ibcon#wrote, iclass 7, count 2 2006.173.11:24:13.68#ibcon#about to read 3, iclass 7, count 2 2006.173.11:24:13.71#ibcon#read 3, iclass 7, count 2 2006.173.11:24:13.71#ibcon#about to read 4, iclass 7, count 2 2006.173.11:24:13.71#ibcon#read 4, iclass 7, count 2 2006.173.11:24:13.71#ibcon#about to read 5, iclass 7, count 2 2006.173.11:24:13.71#ibcon#read 5, iclass 7, count 2 2006.173.11:24:13.71#ibcon#about to read 6, iclass 7, count 2 2006.173.11:24:13.71#ibcon#read 6, iclass 7, count 2 2006.173.11:24:13.71#ibcon#end of sib2, iclass 7, count 2 2006.173.11:24:13.71#ibcon#*after write, iclass 7, count 2 2006.173.11:24:13.71#ibcon#*before return 0, iclass 7, count 2 2006.173.11:24:13.71#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.11:24:13.71#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.173.11:24:13.71#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.173.11:24:13.71#ibcon#ireg 7 cls_cnt 0 2006.173.11:24:13.71#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.11:24:13.83#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.11:24:13.83#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.11:24:13.83#ibcon#enter wrdev, iclass 7, count 0 2006.173.11:24:13.83#ibcon#first serial, iclass 7, count 0 2006.173.11:24:13.83#ibcon#enter sib2, iclass 7, count 0 2006.173.11:24:13.83#ibcon#flushed, iclass 7, count 0 2006.173.11:24:13.83#ibcon#about to write, iclass 7, count 0 2006.173.11:24:13.83#ibcon#wrote, iclass 7, count 0 2006.173.11:24:13.83#ibcon#about to read 3, iclass 7, count 0 2006.173.11:24:13.85#ibcon#read 3, iclass 7, count 0 2006.173.11:24:13.85#ibcon#about to read 4, iclass 7, count 0 2006.173.11:24:13.85#ibcon#read 4, iclass 7, count 0 2006.173.11:24:13.85#ibcon#about to read 5, iclass 7, count 0 2006.173.11:24:13.85#ibcon#read 5, iclass 7, count 0 2006.173.11:24:13.85#ibcon#about to read 6, iclass 7, count 0 2006.173.11:24:13.85#ibcon#read 6, iclass 7, count 0 2006.173.11:24:13.85#ibcon#end of sib2, iclass 7, count 0 2006.173.11:24:13.85#ibcon#*mode == 0, iclass 7, count 0 2006.173.11:24:13.85#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.11:24:13.85#ibcon#[25=USB\r\n] 2006.173.11:24:13.85#ibcon#*before write, iclass 7, count 0 2006.173.11:24:13.85#ibcon#enter sib2, iclass 7, count 0 2006.173.11:24:13.85#ibcon#flushed, iclass 7, count 0 2006.173.11:24:13.85#ibcon#about to write, iclass 7, count 0 2006.173.11:24:13.85#ibcon#wrote, iclass 7, count 0 2006.173.11:24:13.85#ibcon#about to read 3, iclass 7, count 0 2006.173.11:24:13.88#ibcon#read 3, iclass 7, count 0 2006.173.11:24:13.88#ibcon#about to read 4, iclass 7, count 0 2006.173.11:24:13.88#ibcon#read 4, iclass 7, count 0 2006.173.11:24:13.88#ibcon#about to read 5, iclass 7, count 0 2006.173.11:24:13.88#ibcon#read 5, iclass 7, count 0 2006.173.11:24:13.88#ibcon#about to read 6, iclass 7, count 0 2006.173.11:24:13.88#ibcon#read 6, iclass 7, count 0 2006.173.11:24:13.88#ibcon#end of sib2, iclass 7, count 0 2006.173.11:24:13.88#ibcon#*after write, iclass 7, count 0 2006.173.11:24:13.88#ibcon#*before return 0, iclass 7, count 0 2006.173.11:24:13.88#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.11:24:13.88#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.173.11:24:13.88#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.11:24:13.88#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.11:24:13.88$vck44/valo=3,564.99 2006.173.11:24:13.88#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.11:24:13.88#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.11:24:13.88#ibcon#ireg 17 cls_cnt 0 2006.173.11:24:13.88#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.11:24:13.88#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.11:24:13.88#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.11:24:13.88#ibcon#enter wrdev, iclass 11, count 0 2006.173.11:24:13.88#ibcon#first serial, iclass 11, count 0 2006.173.11:24:13.88#ibcon#enter sib2, iclass 11, count 0 2006.173.11:24:13.88#ibcon#flushed, iclass 11, count 0 2006.173.11:24:13.88#ibcon#about to write, iclass 11, count 0 2006.173.11:24:13.88#ibcon#wrote, iclass 11, count 0 2006.173.11:24:13.88#ibcon#about to read 3, iclass 11, count 0 2006.173.11:24:13.90#ibcon#read 3, iclass 11, count 0 2006.173.11:24:13.90#ibcon#about to read 4, iclass 11, count 0 2006.173.11:24:13.90#ibcon#read 4, iclass 11, count 0 2006.173.11:24:13.90#ibcon#about to read 5, iclass 11, count 0 2006.173.11:24:13.90#ibcon#read 5, iclass 11, count 0 2006.173.11:24:13.90#ibcon#about to read 6, iclass 11, count 0 2006.173.11:24:13.90#ibcon#read 6, iclass 11, count 0 2006.173.11:24:13.90#ibcon#end of sib2, iclass 11, count 0 2006.173.11:24:13.90#ibcon#*mode == 0, iclass 11, count 0 2006.173.11:24:13.90#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.11:24:13.90#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.11:24:13.90#ibcon#*before write, iclass 11, count 0 2006.173.11:24:13.90#ibcon#enter sib2, iclass 11, count 0 2006.173.11:24:13.90#ibcon#flushed, iclass 11, count 0 2006.173.11:24:13.90#ibcon#about to write, iclass 11, count 0 2006.173.11:24:13.90#ibcon#wrote, iclass 11, count 0 2006.173.11:24:13.90#ibcon#about to read 3, iclass 11, count 0 2006.173.11:24:13.94#ibcon#read 3, iclass 11, count 0 2006.173.11:24:13.94#ibcon#about to read 4, iclass 11, count 0 2006.173.11:24:13.94#ibcon#read 4, iclass 11, count 0 2006.173.11:24:13.94#ibcon#about to read 5, iclass 11, count 0 2006.173.11:24:13.94#ibcon#read 5, iclass 11, count 0 2006.173.11:24:13.94#ibcon#about to read 6, iclass 11, count 0 2006.173.11:24:13.94#ibcon#read 6, iclass 11, count 0 2006.173.11:24:13.94#ibcon#end of sib2, iclass 11, count 0 2006.173.11:24:13.94#ibcon#*after write, iclass 11, count 0 2006.173.11:24:13.94#ibcon#*before return 0, iclass 11, count 0 2006.173.11:24:13.94#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.11:24:13.94#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.11:24:13.94#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.11:24:13.94#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.11:24:13.94$vck44/va=3,5 2006.173.11:24:13.94#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.173.11:24:13.94#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.173.11:24:13.94#ibcon#ireg 11 cls_cnt 2 2006.173.11:24:13.94#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.11:24:14.00#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.11:24:14.00#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.11:24:14.00#ibcon#enter wrdev, iclass 13, count 2 2006.173.11:24:14.00#ibcon#first serial, iclass 13, count 2 2006.173.11:24:14.00#ibcon#enter sib2, iclass 13, count 2 2006.173.11:24:14.00#ibcon#flushed, iclass 13, count 2 2006.173.11:24:14.00#ibcon#about to write, iclass 13, count 2 2006.173.11:24:14.00#ibcon#wrote, iclass 13, count 2 2006.173.11:24:14.00#ibcon#about to read 3, iclass 13, count 2 2006.173.11:24:14.02#ibcon#read 3, iclass 13, count 2 2006.173.11:24:14.02#ibcon#about to read 4, iclass 13, count 2 2006.173.11:24:14.02#ibcon#read 4, iclass 13, count 2 2006.173.11:24:14.02#ibcon#about to read 5, iclass 13, count 2 2006.173.11:24:14.02#ibcon#read 5, iclass 13, count 2 2006.173.11:24:14.02#ibcon#about to read 6, iclass 13, count 2 2006.173.11:24:14.02#ibcon#read 6, iclass 13, count 2 2006.173.11:24:14.02#ibcon#end of sib2, iclass 13, count 2 2006.173.11:24:14.02#ibcon#*mode == 0, iclass 13, count 2 2006.173.11:24:14.02#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.173.11:24:14.02#ibcon#[25=AT03-05\r\n] 2006.173.11:24:14.02#ibcon#*before write, iclass 13, count 2 2006.173.11:24:14.02#ibcon#enter sib2, iclass 13, count 2 2006.173.11:24:14.02#ibcon#flushed, iclass 13, count 2 2006.173.11:24:14.02#ibcon#about to write, iclass 13, count 2 2006.173.11:24:14.02#ibcon#wrote, iclass 13, count 2 2006.173.11:24:14.02#ibcon#about to read 3, iclass 13, count 2 2006.173.11:24:14.05#ibcon#read 3, iclass 13, count 2 2006.173.11:24:14.05#ibcon#about to read 4, iclass 13, count 2 2006.173.11:24:14.05#ibcon#read 4, iclass 13, count 2 2006.173.11:24:14.05#ibcon#about to read 5, iclass 13, count 2 2006.173.11:24:14.05#ibcon#read 5, iclass 13, count 2 2006.173.11:24:14.05#ibcon#about to read 6, iclass 13, count 2 2006.173.11:24:14.05#ibcon#read 6, iclass 13, count 2 2006.173.11:24:14.05#ibcon#end of sib2, iclass 13, count 2 2006.173.11:24:14.05#ibcon#*after write, iclass 13, count 2 2006.173.11:24:14.05#ibcon#*before return 0, iclass 13, count 2 2006.173.11:24:14.05#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.11:24:14.05#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.173.11:24:14.05#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.173.11:24:14.05#ibcon#ireg 7 cls_cnt 0 2006.173.11:24:14.05#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.11:24:14.17#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.11:24:14.17#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.11:24:14.17#ibcon#enter wrdev, iclass 13, count 0 2006.173.11:24:14.17#ibcon#first serial, iclass 13, count 0 2006.173.11:24:14.17#ibcon#enter sib2, iclass 13, count 0 2006.173.11:24:14.17#ibcon#flushed, iclass 13, count 0 2006.173.11:24:14.17#ibcon#about to write, iclass 13, count 0 2006.173.11:24:14.17#ibcon#wrote, iclass 13, count 0 2006.173.11:24:14.17#ibcon#about to read 3, iclass 13, count 0 2006.173.11:24:14.19#ibcon#read 3, iclass 13, count 0 2006.173.11:24:14.19#ibcon#about to read 4, iclass 13, count 0 2006.173.11:24:14.19#ibcon#read 4, iclass 13, count 0 2006.173.11:24:14.19#ibcon#about to read 5, iclass 13, count 0 2006.173.11:24:14.19#ibcon#read 5, iclass 13, count 0 2006.173.11:24:14.19#ibcon#about to read 6, iclass 13, count 0 2006.173.11:24:14.19#ibcon#read 6, iclass 13, count 0 2006.173.11:24:14.19#ibcon#end of sib2, iclass 13, count 0 2006.173.11:24:14.19#ibcon#*mode == 0, iclass 13, count 0 2006.173.11:24:14.19#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.11:24:14.19#ibcon#[25=USB\r\n] 2006.173.11:24:14.19#ibcon#*before write, iclass 13, count 0 2006.173.11:24:14.19#ibcon#enter sib2, iclass 13, count 0 2006.173.11:24:14.19#ibcon#flushed, iclass 13, count 0 2006.173.11:24:14.19#ibcon#about to write, iclass 13, count 0 2006.173.11:24:14.19#ibcon#wrote, iclass 13, count 0 2006.173.11:24:14.19#ibcon#about to read 3, iclass 13, count 0 2006.173.11:24:14.22#ibcon#read 3, iclass 13, count 0 2006.173.11:24:14.22#ibcon#about to read 4, iclass 13, count 0 2006.173.11:24:14.22#ibcon#read 4, iclass 13, count 0 2006.173.11:24:14.22#ibcon#about to read 5, iclass 13, count 0 2006.173.11:24:14.22#ibcon#read 5, iclass 13, count 0 2006.173.11:24:14.22#ibcon#about to read 6, iclass 13, count 0 2006.173.11:24:14.22#ibcon#read 6, iclass 13, count 0 2006.173.11:24:14.22#ibcon#end of sib2, iclass 13, count 0 2006.173.11:24:14.22#ibcon#*after write, iclass 13, count 0 2006.173.11:24:14.22#ibcon#*before return 0, iclass 13, count 0 2006.173.11:24:14.22#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.11:24:14.22#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.173.11:24:14.22#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.11:24:14.22#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.11:24:14.22$vck44/valo=4,624.99 2006.173.11:24:14.22#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.11:24:14.22#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.11:24:14.22#ibcon#ireg 17 cls_cnt 0 2006.173.11:24:14.22#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.11:24:14.22#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.11:24:14.22#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.11:24:14.22#ibcon#enter wrdev, iclass 15, count 0 2006.173.11:24:14.22#ibcon#first serial, iclass 15, count 0 2006.173.11:24:14.22#ibcon#enter sib2, iclass 15, count 0 2006.173.11:24:14.22#ibcon#flushed, iclass 15, count 0 2006.173.11:24:14.22#ibcon#about to write, iclass 15, count 0 2006.173.11:24:14.22#ibcon#wrote, iclass 15, count 0 2006.173.11:24:14.22#ibcon#about to read 3, iclass 15, count 0 2006.173.11:24:14.24#ibcon#read 3, iclass 15, count 0 2006.173.11:24:14.24#ibcon#about to read 4, iclass 15, count 0 2006.173.11:24:14.24#ibcon#read 4, iclass 15, count 0 2006.173.11:24:14.24#ibcon#about to read 5, iclass 15, count 0 2006.173.11:24:14.24#ibcon#read 5, iclass 15, count 0 2006.173.11:24:14.24#ibcon#about to read 6, iclass 15, count 0 2006.173.11:24:14.24#ibcon#read 6, iclass 15, count 0 2006.173.11:24:14.24#ibcon#end of sib2, iclass 15, count 0 2006.173.11:24:14.24#ibcon#*mode == 0, iclass 15, count 0 2006.173.11:24:14.24#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.11:24:14.24#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.11:24:14.24#ibcon#*before write, iclass 15, count 0 2006.173.11:24:14.24#ibcon#enter sib2, iclass 15, count 0 2006.173.11:24:14.24#ibcon#flushed, iclass 15, count 0 2006.173.11:24:14.24#ibcon#about to write, iclass 15, count 0 2006.173.11:24:14.24#ibcon#wrote, iclass 15, count 0 2006.173.11:24:14.24#ibcon#about to read 3, iclass 15, count 0 2006.173.11:24:14.28#ibcon#read 3, iclass 15, count 0 2006.173.11:24:14.28#ibcon#about to read 4, iclass 15, count 0 2006.173.11:24:14.28#ibcon#read 4, iclass 15, count 0 2006.173.11:24:14.28#ibcon#about to read 5, iclass 15, count 0 2006.173.11:24:14.28#ibcon#read 5, iclass 15, count 0 2006.173.11:24:14.28#ibcon#about to read 6, iclass 15, count 0 2006.173.11:24:14.28#ibcon#read 6, iclass 15, count 0 2006.173.11:24:14.28#ibcon#end of sib2, iclass 15, count 0 2006.173.11:24:14.28#ibcon#*after write, iclass 15, count 0 2006.173.11:24:14.28#ibcon#*before return 0, iclass 15, count 0 2006.173.11:24:14.28#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.11:24:14.28#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.11:24:14.28#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.11:24:14.28#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.11:24:14.28$vck44/va=4,6 2006.173.11:24:14.28#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.11:24:14.28#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.11:24:14.28#ibcon#ireg 11 cls_cnt 2 2006.173.11:24:14.28#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.11:24:14.34#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.11:24:14.34#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.11:24:14.34#ibcon#enter wrdev, iclass 17, count 2 2006.173.11:24:14.34#ibcon#first serial, iclass 17, count 2 2006.173.11:24:14.34#ibcon#enter sib2, iclass 17, count 2 2006.173.11:24:14.34#ibcon#flushed, iclass 17, count 2 2006.173.11:24:14.34#ibcon#about to write, iclass 17, count 2 2006.173.11:24:14.34#ibcon#wrote, iclass 17, count 2 2006.173.11:24:14.34#ibcon#about to read 3, iclass 17, count 2 2006.173.11:24:14.36#ibcon#read 3, iclass 17, count 2 2006.173.11:24:14.36#ibcon#about to read 4, iclass 17, count 2 2006.173.11:24:14.36#ibcon#read 4, iclass 17, count 2 2006.173.11:24:14.36#ibcon#about to read 5, iclass 17, count 2 2006.173.11:24:14.36#ibcon#read 5, iclass 17, count 2 2006.173.11:24:14.36#ibcon#about to read 6, iclass 17, count 2 2006.173.11:24:14.36#ibcon#read 6, iclass 17, count 2 2006.173.11:24:14.36#ibcon#end of sib2, iclass 17, count 2 2006.173.11:24:14.36#ibcon#*mode == 0, iclass 17, count 2 2006.173.11:24:14.36#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.11:24:14.36#ibcon#[25=AT04-06\r\n] 2006.173.11:24:14.36#ibcon#*before write, iclass 17, count 2 2006.173.11:24:14.36#ibcon#enter sib2, iclass 17, count 2 2006.173.11:24:14.36#ibcon#flushed, iclass 17, count 2 2006.173.11:24:14.36#ibcon#about to write, iclass 17, count 2 2006.173.11:24:14.36#ibcon#wrote, iclass 17, count 2 2006.173.11:24:14.36#ibcon#about to read 3, iclass 17, count 2 2006.173.11:24:14.39#ibcon#read 3, iclass 17, count 2 2006.173.11:24:14.39#ibcon#about to read 4, iclass 17, count 2 2006.173.11:24:14.39#ibcon#read 4, iclass 17, count 2 2006.173.11:24:14.39#ibcon#about to read 5, iclass 17, count 2 2006.173.11:24:14.39#ibcon#read 5, iclass 17, count 2 2006.173.11:24:14.39#ibcon#about to read 6, iclass 17, count 2 2006.173.11:24:14.39#ibcon#read 6, iclass 17, count 2 2006.173.11:24:14.39#ibcon#end of sib2, iclass 17, count 2 2006.173.11:24:14.39#ibcon#*after write, iclass 17, count 2 2006.173.11:24:14.39#ibcon#*before return 0, iclass 17, count 2 2006.173.11:24:14.39#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.11:24:14.39#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.11:24:14.39#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.11:24:14.39#ibcon#ireg 7 cls_cnt 0 2006.173.11:24:14.39#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.11:24:14.51#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.11:24:14.51#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.11:24:14.51#ibcon#enter wrdev, iclass 17, count 0 2006.173.11:24:14.51#ibcon#first serial, iclass 17, count 0 2006.173.11:24:14.51#ibcon#enter sib2, iclass 17, count 0 2006.173.11:24:14.51#ibcon#flushed, iclass 17, count 0 2006.173.11:24:14.51#ibcon#about to write, iclass 17, count 0 2006.173.11:24:14.51#ibcon#wrote, iclass 17, count 0 2006.173.11:24:14.51#ibcon#about to read 3, iclass 17, count 0 2006.173.11:24:14.53#ibcon#read 3, iclass 17, count 0 2006.173.11:24:14.53#ibcon#about to read 4, iclass 17, count 0 2006.173.11:24:14.53#ibcon#read 4, iclass 17, count 0 2006.173.11:24:14.53#ibcon#about to read 5, iclass 17, count 0 2006.173.11:24:14.53#ibcon#read 5, iclass 17, count 0 2006.173.11:24:14.53#ibcon#about to read 6, iclass 17, count 0 2006.173.11:24:14.53#ibcon#read 6, iclass 17, count 0 2006.173.11:24:14.53#ibcon#end of sib2, iclass 17, count 0 2006.173.11:24:14.53#ibcon#*mode == 0, iclass 17, count 0 2006.173.11:24:14.53#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.11:24:14.53#ibcon#[25=USB\r\n] 2006.173.11:24:14.53#ibcon#*before write, iclass 17, count 0 2006.173.11:24:14.53#ibcon#enter sib2, iclass 17, count 0 2006.173.11:24:14.53#ibcon#flushed, iclass 17, count 0 2006.173.11:24:14.53#ibcon#about to write, iclass 17, count 0 2006.173.11:24:14.53#ibcon#wrote, iclass 17, count 0 2006.173.11:24:14.53#ibcon#about to read 3, iclass 17, count 0 2006.173.11:24:14.56#ibcon#read 3, iclass 17, count 0 2006.173.11:24:14.56#ibcon#about to read 4, iclass 17, count 0 2006.173.11:24:14.56#ibcon#read 4, iclass 17, count 0 2006.173.11:24:14.56#ibcon#about to read 5, iclass 17, count 0 2006.173.11:24:14.56#ibcon#read 5, iclass 17, count 0 2006.173.11:24:14.56#ibcon#about to read 6, iclass 17, count 0 2006.173.11:24:14.56#ibcon#read 6, iclass 17, count 0 2006.173.11:24:14.56#ibcon#end of sib2, iclass 17, count 0 2006.173.11:24:14.56#ibcon#*after write, iclass 17, count 0 2006.173.11:24:14.56#ibcon#*before return 0, iclass 17, count 0 2006.173.11:24:14.56#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.11:24:14.56#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.11:24:14.56#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.11:24:14.56#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.11:24:14.56$vck44/valo=5,734.99 2006.173.11:24:14.56#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.11:24:14.56#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.11:24:14.56#ibcon#ireg 17 cls_cnt 0 2006.173.11:24:14.56#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.11:24:14.56#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.11:24:14.56#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.11:24:14.56#ibcon#enter wrdev, iclass 19, count 0 2006.173.11:24:14.56#ibcon#first serial, iclass 19, count 0 2006.173.11:24:14.56#ibcon#enter sib2, iclass 19, count 0 2006.173.11:24:14.56#ibcon#flushed, iclass 19, count 0 2006.173.11:24:14.56#ibcon#about to write, iclass 19, count 0 2006.173.11:24:14.56#ibcon#wrote, iclass 19, count 0 2006.173.11:24:14.56#ibcon#about to read 3, iclass 19, count 0 2006.173.11:24:14.58#ibcon#read 3, iclass 19, count 0 2006.173.11:24:14.58#ibcon#about to read 4, iclass 19, count 0 2006.173.11:24:14.58#ibcon#read 4, iclass 19, count 0 2006.173.11:24:14.58#ibcon#about to read 5, iclass 19, count 0 2006.173.11:24:14.58#ibcon#read 5, iclass 19, count 0 2006.173.11:24:14.58#ibcon#about to read 6, iclass 19, count 0 2006.173.11:24:14.58#ibcon#read 6, iclass 19, count 0 2006.173.11:24:14.58#ibcon#end of sib2, iclass 19, count 0 2006.173.11:24:14.58#ibcon#*mode == 0, iclass 19, count 0 2006.173.11:24:14.58#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.11:24:14.58#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.11:24:14.58#ibcon#*before write, iclass 19, count 0 2006.173.11:24:14.58#ibcon#enter sib2, iclass 19, count 0 2006.173.11:24:14.58#ibcon#flushed, iclass 19, count 0 2006.173.11:24:14.58#ibcon#about to write, iclass 19, count 0 2006.173.11:24:14.58#ibcon#wrote, iclass 19, count 0 2006.173.11:24:14.58#ibcon#about to read 3, iclass 19, count 0 2006.173.11:24:14.62#ibcon#read 3, iclass 19, count 0 2006.173.11:24:14.62#ibcon#about to read 4, iclass 19, count 0 2006.173.11:24:14.62#ibcon#read 4, iclass 19, count 0 2006.173.11:24:14.62#ibcon#about to read 5, iclass 19, count 0 2006.173.11:24:14.62#ibcon#read 5, iclass 19, count 0 2006.173.11:24:14.62#ibcon#about to read 6, iclass 19, count 0 2006.173.11:24:14.62#ibcon#read 6, iclass 19, count 0 2006.173.11:24:14.62#ibcon#end of sib2, iclass 19, count 0 2006.173.11:24:14.62#ibcon#*after write, iclass 19, count 0 2006.173.11:24:14.62#ibcon#*before return 0, iclass 19, count 0 2006.173.11:24:14.62#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.11:24:14.62#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.11:24:14.62#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.11:24:14.62#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.11:24:14.62$vck44/va=5,4 2006.173.11:24:14.62#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.11:24:14.62#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.11:24:14.62#ibcon#ireg 11 cls_cnt 2 2006.173.11:24:14.62#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.11:24:14.68#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.11:24:14.68#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.11:24:14.68#ibcon#enter wrdev, iclass 21, count 2 2006.173.11:24:14.68#ibcon#first serial, iclass 21, count 2 2006.173.11:24:14.68#ibcon#enter sib2, iclass 21, count 2 2006.173.11:24:14.68#ibcon#flushed, iclass 21, count 2 2006.173.11:24:14.68#ibcon#about to write, iclass 21, count 2 2006.173.11:24:14.68#ibcon#wrote, iclass 21, count 2 2006.173.11:24:14.68#ibcon#about to read 3, iclass 21, count 2 2006.173.11:24:14.70#ibcon#read 3, iclass 21, count 2 2006.173.11:24:14.70#ibcon#about to read 4, iclass 21, count 2 2006.173.11:24:14.70#ibcon#read 4, iclass 21, count 2 2006.173.11:24:14.70#ibcon#about to read 5, iclass 21, count 2 2006.173.11:24:14.70#ibcon#read 5, iclass 21, count 2 2006.173.11:24:14.70#ibcon#about to read 6, iclass 21, count 2 2006.173.11:24:14.70#ibcon#read 6, iclass 21, count 2 2006.173.11:24:14.70#ibcon#end of sib2, iclass 21, count 2 2006.173.11:24:14.70#ibcon#*mode == 0, iclass 21, count 2 2006.173.11:24:14.70#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.11:24:14.70#ibcon#[25=AT05-04\r\n] 2006.173.11:24:14.70#ibcon#*before write, iclass 21, count 2 2006.173.11:24:14.70#ibcon#enter sib2, iclass 21, count 2 2006.173.11:24:14.70#ibcon#flushed, iclass 21, count 2 2006.173.11:24:14.70#ibcon#about to write, iclass 21, count 2 2006.173.11:24:14.70#ibcon#wrote, iclass 21, count 2 2006.173.11:24:14.70#ibcon#about to read 3, iclass 21, count 2 2006.173.11:24:14.73#ibcon#read 3, iclass 21, count 2 2006.173.11:24:14.73#ibcon#about to read 4, iclass 21, count 2 2006.173.11:24:14.73#ibcon#read 4, iclass 21, count 2 2006.173.11:24:14.73#ibcon#about to read 5, iclass 21, count 2 2006.173.11:24:14.73#ibcon#read 5, iclass 21, count 2 2006.173.11:24:14.73#ibcon#about to read 6, iclass 21, count 2 2006.173.11:24:14.73#ibcon#read 6, iclass 21, count 2 2006.173.11:24:14.73#ibcon#end of sib2, iclass 21, count 2 2006.173.11:24:14.73#ibcon#*after write, iclass 21, count 2 2006.173.11:24:14.73#ibcon#*before return 0, iclass 21, count 2 2006.173.11:24:14.73#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.11:24:14.73#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.11:24:14.73#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.11:24:14.73#ibcon#ireg 7 cls_cnt 0 2006.173.11:24:14.73#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.11:24:14.85#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.11:24:14.85#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.11:24:14.85#ibcon#enter wrdev, iclass 21, count 0 2006.173.11:24:14.85#ibcon#first serial, iclass 21, count 0 2006.173.11:24:14.85#ibcon#enter sib2, iclass 21, count 0 2006.173.11:24:14.85#ibcon#flushed, iclass 21, count 0 2006.173.11:24:14.85#ibcon#about to write, iclass 21, count 0 2006.173.11:24:14.85#ibcon#wrote, iclass 21, count 0 2006.173.11:24:14.85#ibcon#about to read 3, iclass 21, count 0 2006.173.11:24:14.87#ibcon#read 3, iclass 21, count 0 2006.173.11:24:14.87#ibcon#about to read 4, iclass 21, count 0 2006.173.11:24:14.87#ibcon#read 4, iclass 21, count 0 2006.173.11:24:14.87#ibcon#about to read 5, iclass 21, count 0 2006.173.11:24:14.87#ibcon#read 5, iclass 21, count 0 2006.173.11:24:14.87#ibcon#about to read 6, iclass 21, count 0 2006.173.11:24:14.87#ibcon#read 6, iclass 21, count 0 2006.173.11:24:14.87#ibcon#end of sib2, iclass 21, count 0 2006.173.11:24:14.87#ibcon#*mode == 0, iclass 21, count 0 2006.173.11:24:14.87#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.11:24:14.87#ibcon#[25=USB\r\n] 2006.173.11:24:14.87#ibcon#*before write, iclass 21, count 0 2006.173.11:24:14.87#ibcon#enter sib2, iclass 21, count 0 2006.173.11:24:14.87#ibcon#flushed, iclass 21, count 0 2006.173.11:24:14.87#ibcon#about to write, iclass 21, count 0 2006.173.11:24:14.87#ibcon#wrote, iclass 21, count 0 2006.173.11:24:14.87#ibcon#about to read 3, iclass 21, count 0 2006.173.11:24:14.90#ibcon#read 3, iclass 21, count 0 2006.173.11:24:14.90#ibcon#about to read 4, iclass 21, count 0 2006.173.11:24:14.90#ibcon#read 4, iclass 21, count 0 2006.173.11:24:14.90#ibcon#about to read 5, iclass 21, count 0 2006.173.11:24:14.90#ibcon#read 5, iclass 21, count 0 2006.173.11:24:14.90#ibcon#about to read 6, iclass 21, count 0 2006.173.11:24:14.90#ibcon#read 6, iclass 21, count 0 2006.173.11:24:14.90#ibcon#end of sib2, iclass 21, count 0 2006.173.11:24:14.90#ibcon#*after write, iclass 21, count 0 2006.173.11:24:14.90#ibcon#*before return 0, iclass 21, count 0 2006.173.11:24:14.90#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.11:24:14.90#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.11:24:14.90#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.11:24:14.90#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.11:24:14.90$vck44/valo=6,814.99 2006.173.11:24:14.90#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.11:24:14.90#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.11:24:14.90#ibcon#ireg 17 cls_cnt 0 2006.173.11:24:14.90#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.11:24:14.90#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.11:24:14.90#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.11:24:14.90#ibcon#enter wrdev, iclass 23, count 0 2006.173.11:24:14.90#ibcon#first serial, iclass 23, count 0 2006.173.11:24:14.90#ibcon#enter sib2, iclass 23, count 0 2006.173.11:24:14.90#ibcon#flushed, iclass 23, count 0 2006.173.11:24:14.90#ibcon#about to write, iclass 23, count 0 2006.173.11:24:14.90#ibcon#wrote, iclass 23, count 0 2006.173.11:24:14.90#ibcon#about to read 3, iclass 23, count 0 2006.173.11:24:14.92#ibcon#read 3, iclass 23, count 0 2006.173.11:24:14.92#ibcon#about to read 4, iclass 23, count 0 2006.173.11:24:14.92#ibcon#read 4, iclass 23, count 0 2006.173.11:24:14.92#ibcon#about to read 5, iclass 23, count 0 2006.173.11:24:14.92#ibcon#read 5, iclass 23, count 0 2006.173.11:24:14.92#ibcon#about to read 6, iclass 23, count 0 2006.173.11:24:14.92#ibcon#read 6, iclass 23, count 0 2006.173.11:24:14.92#ibcon#end of sib2, iclass 23, count 0 2006.173.11:24:14.92#ibcon#*mode == 0, iclass 23, count 0 2006.173.11:24:14.92#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.11:24:14.92#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.11:24:14.92#ibcon#*before write, iclass 23, count 0 2006.173.11:24:14.92#ibcon#enter sib2, iclass 23, count 0 2006.173.11:24:14.92#ibcon#flushed, iclass 23, count 0 2006.173.11:24:14.92#ibcon#about to write, iclass 23, count 0 2006.173.11:24:14.92#ibcon#wrote, iclass 23, count 0 2006.173.11:24:14.92#ibcon#about to read 3, iclass 23, count 0 2006.173.11:24:14.96#ibcon#read 3, iclass 23, count 0 2006.173.11:24:14.96#ibcon#about to read 4, iclass 23, count 0 2006.173.11:24:14.96#ibcon#read 4, iclass 23, count 0 2006.173.11:24:14.96#ibcon#about to read 5, iclass 23, count 0 2006.173.11:24:14.96#ibcon#read 5, iclass 23, count 0 2006.173.11:24:14.96#ibcon#about to read 6, iclass 23, count 0 2006.173.11:24:14.96#ibcon#read 6, iclass 23, count 0 2006.173.11:24:14.96#ibcon#end of sib2, iclass 23, count 0 2006.173.11:24:14.96#ibcon#*after write, iclass 23, count 0 2006.173.11:24:14.96#ibcon#*before return 0, iclass 23, count 0 2006.173.11:24:14.96#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.11:24:14.96#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.11:24:14.96#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.11:24:14.96#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.11:24:14.96$vck44/va=6,3 2006.173.11:24:14.96#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.11:24:14.96#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.11:24:14.96#ibcon#ireg 11 cls_cnt 2 2006.173.11:24:14.96#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.11:24:15.02#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.11:24:15.02#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.11:24:15.02#ibcon#enter wrdev, iclass 25, count 2 2006.173.11:24:15.02#ibcon#first serial, iclass 25, count 2 2006.173.11:24:15.02#ibcon#enter sib2, iclass 25, count 2 2006.173.11:24:15.02#ibcon#flushed, iclass 25, count 2 2006.173.11:24:15.02#ibcon#about to write, iclass 25, count 2 2006.173.11:24:15.02#ibcon#wrote, iclass 25, count 2 2006.173.11:24:15.02#ibcon#about to read 3, iclass 25, count 2 2006.173.11:24:15.04#ibcon#read 3, iclass 25, count 2 2006.173.11:24:15.04#ibcon#about to read 4, iclass 25, count 2 2006.173.11:24:15.04#ibcon#read 4, iclass 25, count 2 2006.173.11:24:15.04#ibcon#about to read 5, iclass 25, count 2 2006.173.11:24:15.04#ibcon#read 5, iclass 25, count 2 2006.173.11:24:15.04#ibcon#about to read 6, iclass 25, count 2 2006.173.11:24:15.04#ibcon#read 6, iclass 25, count 2 2006.173.11:24:15.04#ibcon#end of sib2, iclass 25, count 2 2006.173.11:24:15.04#ibcon#*mode == 0, iclass 25, count 2 2006.173.11:24:15.04#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.11:24:15.04#ibcon#[25=AT06-03\r\n] 2006.173.11:24:15.04#ibcon#*before write, iclass 25, count 2 2006.173.11:24:15.04#ibcon#enter sib2, iclass 25, count 2 2006.173.11:24:15.04#ibcon#flushed, iclass 25, count 2 2006.173.11:24:15.04#ibcon#about to write, iclass 25, count 2 2006.173.11:24:15.04#ibcon#wrote, iclass 25, count 2 2006.173.11:24:15.04#ibcon#about to read 3, iclass 25, count 2 2006.173.11:24:15.07#ibcon#read 3, iclass 25, count 2 2006.173.11:24:15.07#ibcon#about to read 4, iclass 25, count 2 2006.173.11:24:15.07#ibcon#read 4, iclass 25, count 2 2006.173.11:24:15.07#ibcon#about to read 5, iclass 25, count 2 2006.173.11:24:15.07#ibcon#read 5, iclass 25, count 2 2006.173.11:24:15.07#ibcon#about to read 6, iclass 25, count 2 2006.173.11:24:15.07#ibcon#read 6, iclass 25, count 2 2006.173.11:24:15.07#ibcon#end of sib2, iclass 25, count 2 2006.173.11:24:15.07#ibcon#*after write, iclass 25, count 2 2006.173.11:24:15.07#ibcon#*before return 0, iclass 25, count 2 2006.173.11:24:15.07#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.11:24:15.07#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.11:24:15.07#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.11:24:15.07#ibcon#ireg 7 cls_cnt 0 2006.173.11:24:15.07#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.11:24:15.19#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.11:24:15.19#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.11:24:15.19#ibcon#enter wrdev, iclass 25, count 0 2006.173.11:24:15.19#ibcon#first serial, iclass 25, count 0 2006.173.11:24:15.19#ibcon#enter sib2, iclass 25, count 0 2006.173.11:24:15.19#ibcon#flushed, iclass 25, count 0 2006.173.11:24:15.19#ibcon#about to write, iclass 25, count 0 2006.173.11:24:15.19#ibcon#wrote, iclass 25, count 0 2006.173.11:24:15.19#ibcon#about to read 3, iclass 25, count 0 2006.173.11:24:15.21#ibcon#read 3, iclass 25, count 0 2006.173.11:24:15.21#ibcon#about to read 4, iclass 25, count 0 2006.173.11:24:15.21#ibcon#read 4, iclass 25, count 0 2006.173.11:24:15.21#ibcon#about to read 5, iclass 25, count 0 2006.173.11:24:15.21#ibcon#read 5, iclass 25, count 0 2006.173.11:24:15.21#ibcon#about to read 6, iclass 25, count 0 2006.173.11:24:15.21#ibcon#read 6, iclass 25, count 0 2006.173.11:24:15.21#ibcon#end of sib2, iclass 25, count 0 2006.173.11:24:15.21#ibcon#*mode == 0, iclass 25, count 0 2006.173.11:24:15.21#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.11:24:15.21#ibcon#[25=USB\r\n] 2006.173.11:24:15.21#ibcon#*before write, iclass 25, count 0 2006.173.11:24:15.21#ibcon#enter sib2, iclass 25, count 0 2006.173.11:24:15.21#ibcon#flushed, iclass 25, count 0 2006.173.11:24:15.21#ibcon#about to write, iclass 25, count 0 2006.173.11:24:15.21#ibcon#wrote, iclass 25, count 0 2006.173.11:24:15.21#ibcon#about to read 3, iclass 25, count 0 2006.173.11:24:15.24#ibcon#read 3, iclass 25, count 0 2006.173.11:24:15.24#ibcon#about to read 4, iclass 25, count 0 2006.173.11:24:15.24#ibcon#read 4, iclass 25, count 0 2006.173.11:24:15.24#ibcon#about to read 5, iclass 25, count 0 2006.173.11:24:15.24#ibcon#read 5, iclass 25, count 0 2006.173.11:24:15.24#ibcon#about to read 6, iclass 25, count 0 2006.173.11:24:15.24#ibcon#read 6, iclass 25, count 0 2006.173.11:24:15.24#ibcon#end of sib2, iclass 25, count 0 2006.173.11:24:15.24#ibcon#*after write, iclass 25, count 0 2006.173.11:24:15.24#ibcon#*before return 0, iclass 25, count 0 2006.173.11:24:15.24#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.11:24:15.24#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.11:24:15.24#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.11:24:15.24#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.11:24:15.24$vck44/valo=7,864.99 2006.173.11:24:15.24#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.11:24:15.24#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.11:24:15.24#ibcon#ireg 17 cls_cnt 0 2006.173.11:24:15.24#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.11:24:15.24#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.11:24:15.24#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.11:24:15.24#ibcon#enter wrdev, iclass 27, count 0 2006.173.11:24:15.24#ibcon#first serial, iclass 27, count 0 2006.173.11:24:15.24#ibcon#enter sib2, iclass 27, count 0 2006.173.11:24:15.24#ibcon#flushed, iclass 27, count 0 2006.173.11:24:15.24#ibcon#about to write, iclass 27, count 0 2006.173.11:24:15.24#ibcon#wrote, iclass 27, count 0 2006.173.11:24:15.24#ibcon#about to read 3, iclass 27, count 0 2006.173.11:24:15.26#ibcon#read 3, iclass 27, count 0 2006.173.11:24:15.26#ibcon#about to read 4, iclass 27, count 0 2006.173.11:24:15.26#ibcon#read 4, iclass 27, count 0 2006.173.11:24:15.26#ibcon#about to read 5, iclass 27, count 0 2006.173.11:24:15.26#ibcon#read 5, iclass 27, count 0 2006.173.11:24:15.26#ibcon#about to read 6, iclass 27, count 0 2006.173.11:24:15.26#ibcon#read 6, iclass 27, count 0 2006.173.11:24:15.26#ibcon#end of sib2, iclass 27, count 0 2006.173.11:24:15.26#ibcon#*mode == 0, iclass 27, count 0 2006.173.11:24:15.26#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.11:24:15.26#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.11:24:15.26#ibcon#*before write, iclass 27, count 0 2006.173.11:24:15.26#ibcon#enter sib2, iclass 27, count 0 2006.173.11:24:15.26#ibcon#flushed, iclass 27, count 0 2006.173.11:24:15.26#ibcon#about to write, iclass 27, count 0 2006.173.11:24:15.26#ibcon#wrote, iclass 27, count 0 2006.173.11:24:15.26#ibcon#about to read 3, iclass 27, count 0 2006.173.11:24:15.30#ibcon#read 3, iclass 27, count 0 2006.173.11:24:15.30#ibcon#about to read 4, iclass 27, count 0 2006.173.11:24:15.30#ibcon#read 4, iclass 27, count 0 2006.173.11:24:15.30#ibcon#about to read 5, iclass 27, count 0 2006.173.11:24:15.30#ibcon#read 5, iclass 27, count 0 2006.173.11:24:15.30#ibcon#about to read 6, iclass 27, count 0 2006.173.11:24:15.30#ibcon#read 6, iclass 27, count 0 2006.173.11:24:15.30#ibcon#end of sib2, iclass 27, count 0 2006.173.11:24:15.30#ibcon#*after write, iclass 27, count 0 2006.173.11:24:15.30#ibcon#*before return 0, iclass 27, count 0 2006.173.11:24:15.30#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.11:24:15.30#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.11:24:15.30#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.11:24:15.30#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.11:24:15.30$vck44/va=7,4 2006.173.11:24:15.30#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.11:24:15.30#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.11:24:15.30#ibcon#ireg 11 cls_cnt 2 2006.173.11:24:15.30#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.11:24:15.36#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.11:24:15.36#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.11:24:15.36#ibcon#enter wrdev, iclass 29, count 2 2006.173.11:24:15.36#ibcon#first serial, iclass 29, count 2 2006.173.11:24:15.36#ibcon#enter sib2, iclass 29, count 2 2006.173.11:24:15.36#ibcon#flushed, iclass 29, count 2 2006.173.11:24:15.36#ibcon#about to write, iclass 29, count 2 2006.173.11:24:15.36#ibcon#wrote, iclass 29, count 2 2006.173.11:24:15.36#ibcon#about to read 3, iclass 29, count 2 2006.173.11:24:15.38#ibcon#read 3, iclass 29, count 2 2006.173.11:24:15.38#ibcon#about to read 4, iclass 29, count 2 2006.173.11:24:15.38#ibcon#read 4, iclass 29, count 2 2006.173.11:24:15.38#ibcon#about to read 5, iclass 29, count 2 2006.173.11:24:15.38#ibcon#read 5, iclass 29, count 2 2006.173.11:24:15.38#ibcon#about to read 6, iclass 29, count 2 2006.173.11:24:15.38#ibcon#read 6, iclass 29, count 2 2006.173.11:24:15.38#ibcon#end of sib2, iclass 29, count 2 2006.173.11:24:15.38#ibcon#*mode == 0, iclass 29, count 2 2006.173.11:24:15.38#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.11:24:15.38#ibcon#[25=AT07-04\r\n] 2006.173.11:24:15.38#ibcon#*before write, iclass 29, count 2 2006.173.11:24:15.38#ibcon#enter sib2, iclass 29, count 2 2006.173.11:24:15.38#ibcon#flushed, iclass 29, count 2 2006.173.11:24:15.38#ibcon#about to write, iclass 29, count 2 2006.173.11:24:15.38#ibcon#wrote, iclass 29, count 2 2006.173.11:24:15.38#ibcon#about to read 3, iclass 29, count 2 2006.173.11:24:15.41#ibcon#read 3, iclass 29, count 2 2006.173.11:24:15.41#ibcon#about to read 4, iclass 29, count 2 2006.173.11:24:15.41#ibcon#read 4, iclass 29, count 2 2006.173.11:24:15.41#ibcon#about to read 5, iclass 29, count 2 2006.173.11:24:15.41#ibcon#read 5, iclass 29, count 2 2006.173.11:24:15.41#ibcon#about to read 6, iclass 29, count 2 2006.173.11:24:15.41#ibcon#read 6, iclass 29, count 2 2006.173.11:24:15.41#ibcon#end of sib2, iclass 29, count 2 2006.173.11:24:15.41#ibcon#*after write, iclass 29, count 2 2006.173.11:24:15.41#ibcon#*before return 0, iclass 29, count 2 2006.173.11:24:15.41#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.11:24:15.41#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.11:24:15.41#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.11:24:15.41#ibcon#ireg 7 cls_cnt 0 2006.173.11:24:15.41#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.11:24:15.53#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.11:24:15.53#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.11:24:15.53#ibcon#enter wrdev, iclass 29, count 0 2006.173.11:24:15.53#ibcon#first serial, iclass 29, count 0 2006.173.11:24:15.53#ibcon#enter sib2, iclass 29, count 0 2006.173.11:24:15.53#ibcon#flushed, iclass 29, count 0 2006.173.11:24:15.53#ibcon#about to write, iclass 29, count 0 2006.173.11:24:15.53#ibcon#wrote, iclass 29, count 0 2006.173.11:24:15.53#ibcon#about to read 3, iclass 29, count 0 2006.173.11:24:15.55#ibcon#read 3, iclass 29, count 0 2006.173.11:24:15.55#ibcon#about to read 4, iclass 29, count 0 2006.173.11:24:15.55#ibcon#read 4, iclass 29, count 0 2006.173.11:24:15.55#ibcon#about to read 5, iclass 29, count 0 2006.173.11:24:15.55#ibcon#read 5, iclass 29, count 0 2006.173.11:24:15.55#ibcon#about to read 6, iclass 29, count 0 2006.173.11:24:15.55#ibcon#read 6, iclass 29, count 0 2006.173.11:24:15.55#ibcon#end of sib2, iclass 29, count 0 2006.173.11:24:15.55#ibcon#*mode == 0, iclass 29, count 0 2006.173.11:24:15.55#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.11:24:15.55#ibcon#[25=USB\r\n] 2006.173.11:24:15.55#ibcon#*before write, iclass 29, count 0 2006.173.11:24:15.55#ibcon#enter sib2, iclass 29, count 0 2006.173.11:24:15.55#ibcon#flushed, iclass 29, count 0 2006.173.11:24:15.55#ibcon#about to write, iclass 29, count 0 2006.173.11:24:15.55#ibcon#wrote, iclass 29, count 0 2006.173.11:24:15.55#ibcon#about to read 3, iclass 29, count 0 2006.173.11:24:15.58#ibcon#read 3, iclass 29, count 0 2006.173.11:24:15.58#ibcon#about to read 4, iclass 29, count 0 2006.173.11:24:15.58#ibcon#read 4, iclass 29, count 0 2006.173.11:24:15.58#ibcon#about to read 5, iclass 29, count 0 2006.173.11:24:15.58#ibcon#read 5, iclass 29, count 0 2006.173.11:24:15.58#ibcon#about to read 6, iclass 29, count 0 2006.173.11:24:15.58#ibcon#read 6, iclass 29, count 0 2006.173.11:24:15.58#ibcon#end of sib2, iclass 29, count 0 2006.173.11:24:15.58#ibcon#*after write, iclass 29, count 0 2006.173.11:24:15.58#ibcon#*before return 0, iclass 29, count 0 2006.173.11:24:15.58#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.11:24:15.58#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.11:24:15.58#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.11:24:15.58#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.11:24:15.58$vck44/valo=8,884.99 2006.173.11:24:15.58#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.11:24:15.58#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.11:24:15.58#ibcon#ireg 17 cls_cnt 0 2006.173.11:24:15.58#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.11:24:15.58#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.11:24:15.58#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.11:24:15.58#ibcon#enter wrdev, iclass 31, count 0 2006.173.11:24:15.58#ibcon#first serial, iclass 31, count 0 2006.173.11:24:15.58#ibcon#enter sib2, iclass 31, count 0 2006.173.11:24:15.58#ibcon#flushed, iclass 31, count 0 2006.173.11:24:15.58#ibcon#about to write, iclass 31, count 0 2006.173.11:24:15.58#ibcon#wrote, iclass 31, count 0 2006.173.11:24:15.58#ibcon#about to read 3, iclass 31, count 0 2006.173.11:24:15.60#ibcon#read 3, iclass 31, count 0 2006.173.11:24:15.60#ibcon#about to read 4, iclass 31, count 0 2006.173.11:24:15.60#ibcon#read 4, iclass 31, count 0 2006.173.11:24:15.60#ibcon#about to read 5, iclass 31, count 0 2006.173.11:24:15.60#ibcon#read 5, iclass 31, count 0 2006.173.11:24:15.60#ibcon#about to read 6, iclass 31, count 0 2006.173.11:24:15.60#ibcon#read 6, iclass 31, count 0 2006.173.11:24:15.60#ibcon#end of sib2, iclass 31, count 0 2006.173.11:24:15.60#ibcon#*mode == 0, iclass 31, count 0 2006.173.11:24:15.60#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.11:24:15.60#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.11:24:15.60#ibcon#*before write, iclass 31, count 0 2006.173.11:24:15.60#ibcon#enter sib2, iclass 31, count 0 2006.173.11:24:15.60#ibcon#flushed, iclass 31, count 0 2006.173.11:24:15.60#ibcon#about to write, iclass 31, count 0 2006.173.11:24:15.60#ibcon#wrote, iclass 31, count 0 2006.173.11:24:15.60#ibcon#about to read 3, iclass 31, count 0 2006.173.11:24:15.64#ibcon#read 3, iclass 31, count 0 2006.173.11:24:15.64#ibcon#about to read 4, iclass 31, count 0 2006.173.11:24:15.64#ibcon#read 4, iclass 31, count 0 2006.173.11:24:15.64#ibcon#about to read 5, iclass 31, count 0 2006.173.11:24:15.64#ibcon#read 5, iclass 31, count 0 2006.173.11:24:15.64#ibcon#about to read 6, iclass 31, count 0 2006.173.11:24:15.64#ibcon#read 6, iclass 31, count 0 2006.173.11:24:15.64#ibcon#end of sib2, iclass 31, count 0 2006.173.11:24:15.64#ibcon#*after write, iclass 31, count 0 2006.173.11:24:15.64#ibcon#*before return 0, iclass 31, count 0 2006.173.11:24:15.64#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.11:24:15.64#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.11:24:15.64#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.11:24:15.64#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.11:24:15.64$vck44/va=8,4 2006.173.11:24:15.64#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.173.11:24:15.64#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.173.11:24:15.64#ibcon#ireg 11 cls_cnt 2 2006.173.11:24:15.64#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.11:24:15.70#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.11:24:15.70#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.11:24:15.70#ibcon#enter wrdev, iclass 33, count 2 2006.173.11:24:15.70#ibcon#first serial, iclass 33, count 2 2006.173.11:24:15.70#ibcon#enter sib2, iclass 33, count 2 2006.173.11:24:15.70#ibcon#flushed, iclass 33, count 2 2006.173.11:24:15.70#ibcon#about to write, iclass 33, count 2 2006.173.11:24:15.70#ibcon#wrote, iclass 33, count 2 2006.173.11:24:15.70#ibcon#about to read 3, iclass 33, count 2 2006.173.11:24:15.72#ibcon#read 3, iclass 33, count 2 2006.173.11:24:15.72#ibcon#about to read 4, iclass 33, count 2 2006.173.11:24:15.72#ibcon#read 4, iclass 33, count 2 2006.173.11:24:15.72#ibcon#about to read 5, iclass 33, count 2 2006.173.11:24:15.72#ibcon#read 5, iclass 33, count 2 2006.173.11:24:15.72#ibcon#about to read 6, iclass 33, count 2 2006.173.11:24:15.72#ibcon#read 6, iclass 33, count 2 2006.173.11:24:15.72#ibcon#end of sib2, iclass 33, count 2 2006.173.11:24:15.72#ibcon#*mode == 0, iclass 33, count 2 2006.173.11:24:15.72#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.173.11:24:15.72#ibcon#[25=AT08-04\r\n] 2006.173.11:24:15.72#ibcon#*before write, iclass 33, count 2 2006.173.11:24:15.72#ibcon#enter sib2, iclass 33, count 2 2006.173.11:24:15.72#ibcon#flushed, iclass 33, count 2 2006.173.11:24:15.72#ibcon#about to write, iclass 33, count 2 2006.173.11:24:15.72#ibcon#wrote, iclass 33, count 2 2006.173.11:24:15.72#ibcon#about to read 3, iclass 33, count 2 2006.173.11:24:15.75#ibcon#read 3, iclass 33, count 2 2006.173.11:24:15.75#ibcon#about to read 4, iclass 33, count 2 2006.173.11:24:15.75#ibcon#read 4, iclass 33, count 2 2006.173.11:24:15.75#ibcon#about to read 5, iclass 33, count 2 2006.173.11:24:15.75#ibcon#read 5, iclass 33, count 2 2006.173.11:24:15.75#ibcon#about to read 6, iclass 33, count 2 2006.173.11:24:15.75#ibcon#read 6, iclass 33, count 2 2006.173.11:24:15.75#ibcon#end of sib2, iclass 33, count 2 2006.173.11:24:15.75#ibcon#*after write, iclass 33, count 2 2006.173.11:24:15.75#ibcon#*before return 0, iclass 33, count 2 2006.173.11:24:15.75#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.11:24:15.75#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.173.11:24:15.75#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.173.11:24:15.75#ibcon#ireg 7 cls_cnt 0 2006.173.11:24:15.75#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.11:24:15.87#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.11:24:15.87#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.11:24:15.87#ibcon#enter wrdev, iclass 33, count 0 2006.173.11:24:15.87#ibcon#first serial, iclass 33, count 0 2006.173.11:24:15.87#ibcon#enter sib2, iclass 33, count 0 2006.173.11:24:15.87#ibcon#flushed, iclass 33, count 0 2006.173.11:24:15.87#ibcon#about to write, iclass 33, count 0 2006.173.11:24:15.87#ibcon#wrote, iclass 33, count 0 2006.173.11:24:15.87#ibcon#about to read 3, iclass 33, count 0 2006.173.11:24:15.89#ibcon#read 3, iclass 33, count 0 2006.173.11:24:15.89#ibcon#about to read 4, iclass 33, count 0 2006.173.11:24:15.89#ibcon#read 4, iclass 33, count 0 2006.173.11:24:15.89#ibcon#about to read 5, iclass 33, count 0 2006.173.11:24:15.89#ibcon#read 5, iclass 33, count 0 2006.173.11:24:15.89#ibcon#about to read 6, iclass 33, count 0 2006.173.11:24:15.89#ibcon#read 6, iclass 33, count 0 2006.173.11:24:15.89#ibcon#end of sib2, iclass 33, count 0 2006.173.11:24:15.89#ibcon#*mode == 0, iclass 33, count 0 2006.173.11:24:15.89#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.11:24:15.89#ibcon#[25=USB\r\n] 2006.173.11:24:15.89#ibcon#*before write, iclass 33, count 0 2006.173.11:24:15.89#ibcon#enter sib2, iclass 33, count 0 2006.173.11:24:15.89#ibcon#flushed, iclass 33, count 0 2006.173.11:24:15.89#ibcon#about to write, iclass 33, count 0 2006.173.11:24:15.89#ibcon#wrote, iclass 33, count 0 2006.173.11:24:15.89#ibcon#about to read 3, iclass 33, count 0 2006.173.11:24:15.92#ibcon#read 3, iclass 33, count 0 2006.173.11:24:15.92#ibcon#about to read 4, iclass 33, count 0 2006.173.11:24:15.92#ibcon#read 4, iclass 33, count 0 2006.173.11:24:15.92#ibcon#about to read 5, iclass 33, count 0 2006.173.11:24:15.92#ibcon#read 5, iclass 33, count 0 2006.173.11:24:15.92#ibcon#about to read 6, iclass 33, count 0 2006.173.11:24:15.92#ibcon#read 6, iclass 33, count 0 2006.173.11:24:15.92#ibcon#end of sib2, iclass 33, count 0 2006.173.11:24:15.92#ibcon#*after write, iclass 33, count 0 2006.173.11:24:15.92#ibcon#*before return 0, iclass 33, count 0 2006.173.11:24:15.92#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.11:24:15.92#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.173.11:24:15.92#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.11:24:15.92#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.11:24:15.92$vck44/vblo=1,629.99 2006.173.11:24:15.92#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.11:24:15.92#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.11:24:15.92#ibcon#ireg 17 cls_cnt 0 2006.173.11:24:15.92#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.11:24:15.92#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.11:24:15.92#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.11:24:15.92#ibcon#enter wrdev, iclass 35, count 0 2006.173.11:24:15.92#ibcon#first serial, iclass 35, count 0 2006.173.11:24:15.92#ibcon#enter sib2, iclass 35, count 0 2006.173.11:24:15.92#ibcon#flushed, iclass 35, count 0 2006.173.11:24:15.92#ibcon#about to write, iclass 35, count 0 2006.173.11:24:15.92#ibcon#wrote, iclass 35, count 0 2006.173.11:24:15.92#ibcon#about to read 3, iclass 35, count 0 2006.173.11:24:15.94#ibcon#read 3, iclass 35, count 0 2006.173.11:24:15.94#ibcon#about to read 4, iclass 35, count 0 2006.173.11:24:15.94#ibcon#read 4, iclass 35, count 0 2006.173.11:24:15.94#ibcon#about to read 5, iclass 35, count 0 2006.173.11:24:15.94#ibcon#read 5, iclass 35, count 0 2006.173.11:24:15.94#ibcon#about to read 6, iclass 35, count 0 2006.173.11:24:15.94#ibcon#read 6, iclass 35, count 0 2006.173.11:24:15.94#ibcon#end of sib2, iclass 35, count 0 2006.173.11:24:15.94#ibcon#*mode == 0, iclass 35, count 0 2006.173.11:24:15.94#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.11:24:15.94#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.11:24:15.94#ibcon#*before write, iclass 35, count 0 2006.173.11:24:15.94#ibcon#enter sib2, iclass 35, count 0 2006.173.11:24:15.94#ibcon#flushed, iclass 35, count 0 2006.173.11:24:15.94#ibcon#about to write, iclass 35, count 0 2006.173.11:24:15.94#ibcon#wrote, iclass 35, count 0 2006.173.11:24:15.94#ibcon#about to read 3, iclass 35, count 0 2006.173.11:24:15.98#ibcon#read 3, iclass 35, count 0 2006.173.11:24:15.98#ibcon#about to read 4, iclass 35, count 0 2006.173.11:24:15.98#ibcon#read 4, iclass 35, count 0 2006.173.11:24:15.98#ibcon#about to read 5, iclass 35, count 0 2006.173.11:24:15.98#ibcon#read 5, iclass 35, count 0 2006.173.11:24:15.98#ibcon#about to read 6, iclass 35, count 0 2006.173.11:24:15.98#ibcon#read 6, iclass 35, count 0 2006.173.11:24:15.98#ibcon#end of sib2, iclass 35, count 0 2006.173.11:24:15.98#ibcon#*after write, iclass 35, count 0 2006.173.11:24:15.98#ibcon#*before return 0, iclass 35, count 0 2006.173.11:24:15.98#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.11:24:15.98#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.11:24:15.98#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.11:24:15.98#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.11:24:15.98$vck44/vb=1,4 2006.173.11:24:15.98#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.173.11:24:15.98#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.173.11:24:15.98#ibcon#ireg 11 cls_cnt 2 2006.173.11:24:15.98#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.11:24:15.98#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.11:24:15.98#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.11:24:15.98#ibcon#enter wrdev, iclass 37, count 2 2006.173.11:24:15.98#ibcon#first serial, iclass 37, count 2 2006.173.11:24:15.98#ibcon#enter sib2, iclass 37, count 2 2006.173.11:24:15.98#ibcon#flushed, iclass 37, count 2 2006.173.11:24:15.98#ibcon#about to write, iclass 37, count 2 2006.173.11:24:15.98#ibcon#wrote, iclass 37, count 2 2006.173.11:24:15.98#ibcon#about to read 3, iclass 37, count 2 2006.173.11:24:16.00#ibcon#read 3, iclass 37, count 2 2006.173.11:24:16.00#ibcon#about to read 4, iclass 37, count 2 2006.173.11:24:16.00#ibcon#read 4, iclass 37, count 2 2006.173.11:24:16.00#ibcon#about to read 5, iclass 37, count 2 2006.173.11:24:16.00#ibcon#read 5, iclass 37, count 2 2006.173.11:24:16.00#ibcon#about to read 6, iclass 37, count 2 2006.173.11:24:16.00#ibcon#read 6, iclass 37, count 2 2006.173.11:24:16.00#ibcon#end of sib2, iclass 37, count 2 2006.173.11:24:16.00#ibcon#*mode == 0, iclass 37, count 2 2006.173.11:24:16.00#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.173.11:24:16.00#ibcon#[27=AT01-04\r\n] 2006.173.11:24:16.00#ibcon#*before write, iclass 37, count 2 2006.173.11:24:16.00#ibcon#enter sib2, iclass 37, count 2 2006.173.11:24:16.00#ibcon#flushed, iclass 37, count 2 2006.173.11:24:16.00#ibcon#about to write, iclass 37, count 2 2006.173.11:24:16.00#ibcon#wrote, iclass 37, count 2 2006.173.11:24:16.00#ibcon#about to read 3, iclass 37, count 2 2006.173.11:24:16.03#ibcon#read 3, iclass 37, count 2 2006.173.11:24:16.03#ibcon#about to read 4, iclass 37, count 2 2006.173.11:24:16.03#ibcon#read 4, iclass 37, count 2 2006.173.11:24:16.03#ibcon#about to read 5, iclass 37, count 2 2006.173.11:24:16.03#ibcon#read 5, iclass 37, count 2 2006.173.11:24:16.03#ibcon#about to read 6, iclass 37, count 2 2006.173.11:24:16.03#ibcon#read 6, iclass 37, count 2 2006.173.11:24:16.03#ibcon#end of sib2, iclass 37, count 2 2006.173.11:24:16.03#ibcon#*after write, iclass 37, count 2 2006.173.11:24:16.03#ibcon#*before return 0, iclass 37, count 2 2006.173.11:24:16.03#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.11:24:16.03#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.173.11:24:16.03#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.173.11:24:16.03#ibcon#ireg 7 cls_cnt 0 2006.173.11:24:16.03#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.11:24:16.15#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.11:24:16.15#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.11:24:16.15#ibcon#enter wrdev, iclass 37, count 0 2006.173.11:24:16.15#ibcon#first serial, iclass 37, count 0 2006.173.11:24:16.15#ibcon#enter sib2, iclass 37, count 0 2006.173.11:24:16.15#ibcon#flushed, iclass 37, count 0 2006.173.11:24:16.15#ibcon#about to write, iclass 37, count 0 2006.173.11:24:16.15#ibcon#wrote, iclass 37, count 0 2006.173.11:24:16.15#ibcon#about to read 3, iclass 37, count 0 2006.173.11:24:16.17#ibcon#read 3, iclass 37, count 0 2006.173.11:24:16.17#ibcon#about to read 4, iclass 37, count 0 2006.173.11:24:16.17#ibcon#read 4, iclass 37, count 0 2006.173.11:24:16.17#ibcon#about to read 5, iclass 37, count 0 2006.173.11:24:16.17#ibcon#read 5, iclass 37, count 0 2006.173.11:24:16.17#ibcon#about to read 6, iclass 37, count 0 2006.173.11:24:16.17#ibcon#read 6, iclass 37, count 0 2006.173.11:24:16.17#ibcon#end of sib2, iclass 37, count 0 2006.173.11:24:16.17#ibcon#*mode == 0, iclass 37, count 0 2006.173.11:24:16.17#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.11:24:16.17#ibcon#[27=USB\r\n] 2006.173.11:24:16.17#ibcon#*before write, iclass 37, count 0 2006.173.11:24:16.17#ibcon#enter sib2, iclass 37, count 0 2006.173.11:24:16.17#ibcon#flushed, iclass 37, count 0 2006.173.11:24:16.17#ibcon#about to write, iclass 37, count 0 2006.173.11:24:16.17#ibcon#wrote, iclass 37, count 0 2006.173.11:24:16.17#ibcon#about to read 3, iclass 37, count 0 2006.173.11:24:16.20#ibcon#read 3, iclass 37, count 0 2006.173.11:24:16.20#ibcon#about to read 4, iclass 37, count 0 2006.173.11:24:16.20#ibcon#read 4, iclass 37, count 0 2006.173.11:24:16.20#ibcon#about to read 5, iclass 37, count 0 2006.173.11:24:16.20#ibcon#read 5, iclass 37, count 0 2006.173.11:24:16.20#ibcon#about to read 6, iclass 37, count 0 2006.173.11:24:16.20#ibcon#read 6, iclass 37, count 0 2006.173.11:24:16.20#ibcon#end of sib2, iclass 37, count 0 2006.173.11:24:16.20#ibcon#*after write, iclass 37, count 0 2006.173.11:24:16.20#ibcon#*before return 0, iclass 37, count 0 2006.173.11:24:16.20#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.11:24:16.20#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.173.11:24:16.20#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.11:24:16.20#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.11:24:16.20$vck44/vblo=2,634.99 2006.173.11:24:16.20#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.11:24:16.20#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.11:24:16.20#ibcon#ireg 17 cls_cnt 0 2006.173.11:24:16.20#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.11:24:16.20#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.11:24:16.20#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.11:24:16.20#ibcon#enter wrdev, iclass 39, count 0 2006.173.11:24:16.20#ibcon#first serial, iclass 39, count 0 2006.173.11:24:16.20#ibcon#enter sib2, iclass 39, count 0 2006.173.11:24:16.20#ibcon#flushed, iclass 39, count 0 2006.173.11:24:16.20#ibcon#about to write, iclass 39, count 0 2006.173.11:24:16.20#ibcon#wrote, iclass 39, count 0 2006.173.11:24:16.20#ibcon#about to read 3, iclass 39, count 0 2006.173.11:24:16.22#ibcon#read 3, iclass 39, count 0 2006.173.11:24:16.22#ibcon#about to read 4, iclass 39, count 0 2006.173.11:24:16.22#ibcon#read 4, iclass 39, count 0 2006.173.11:24:16.22#ibcon#about to read 5, iclass 39, count 0 2006.173.11:24:16.22#ibcon#read 5, iclass 39, count 0 2006.173.11:24:16.22#ibcon#about to read 6, iclass 39, count 0 2006.173.11:24:16.22#ibcon#read 6, iclass 39, count 0 2006.173.11:24:16.22#ibcon#end of sib2, iclass 39, count 0 2006.173.11:24:16.22#ibcon#*mode == 0, iclass 39, count 0 2006.173.11:24:16.22#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.11:24:16.22#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.11:24:16.22#ibcon#*before write, iclass 39, count 0 2006.173.11:24:16.22#ibcon#enter sib2, iclass 39, count 0 2006.173.11:24:16.22#ibcon#flushed, iclass 39, count 0 2006.173.11:24:16.22#ibcon#about to write, iclass 39, count 0 2006.173.11:24:16.22#ibcon#wrote, iclass 39, count 0 2006.173.11:24:16.22#ibcon#about to read 3, iclass 39, count 0 2006.173.11:24:16.26#ibcon#read 3, iclass 39, count 0 2006.173.11:24:16.26#ibcon#about to read 4, iclass 39, count 0 2006.173.11:24:16.26#ibcon#read 4, iclass 39, count 0 2006.173.11:24:16.26#ibcon#about to read 5, iclass 39, count 0 2006.173.11:24:16.26#ibcon#read 5, iclass 39, count 0 2006.173.11:24:16.26#ibcon#about to read 6, iclass 39, count 0 2006.173.11:24:16.26#ibcon#read 6, iclass 39, count 0 2006.173.11:24:16.26#ibcon#end of sib2, iclass 39, count 0 2006.173.11:24:16.26#ibcon#*after write, iclass 39, count 0 2006.173.11:24:16.26#ibcon#*before return 0, iclass 39, count 0 2006.173.11:24:16.26#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.11:24:16.26#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.11:24:16.26#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.11:24:16.26#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.11:24:16.26$vck44/vb=2,4 2006.173.11:24:16.26#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.11:24:16.26#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.11:24:16.26#ibcon#ireg 11 cls_cnt 2 2006.173.11:24:16.26#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.11:24:16.32#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.11:24:16.32#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.11:24:16.32#ibcon#enter wrdev, iclass 3, count 2 2006.173.11:24:16.32#ibcon#first serial, iclass 3, count 2 2006.173.11:24:16.32#ibcon#enter sib2, iclass 3, count 2 2006.173.11:24:16.32#ibcon#flushed, iclass 3, count 2 2006.173.11:24:16.32#ibcon#about to write, iclass 3, count 2 2006.173.11:24:16.32#ibcon#wrote, iclass 3, count 2 2006.173.11:24:16.32#ibcon#about to read 3, iclass 3, count 2 2006.173.11:24:16.34#ibcon#read 3, iclass 3, count 2 2006.173.11:24:16.34#ibcon#about to read 4, iclass 3, count 2 2006.173.11:24:16.34#ibcon#read 4, iclass 3, count 2 2006.173.11:24:16.34#ibcon#about to read 5, iclass 3, count 2 2006.173.11:24:16.34#ibcon#read 5, iclass 3, count 2 2006.173.11:24:16.34#ibcon#about to read 6, iclass 3, count 2 2006.173.11:24:16.34#ibcon#read 6, iclass 3, count 2 2006.173.11:24:16.34#ibcon#end of sib2, iclass 3, count 2 2006.173.11:24:16.34#ibcon#*mode == 0, iclass 3, count 2 2006.173.11:24:16.34#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.11:24:16.34#ibcon#[27=AT02-04\r\n] 2006.173.11:24:16.34#ibcon#*before write, iclass 3, count 2 2006.173.11:24:16.34#ibcon#enter sib2, iclass 3, count 2 2006.173.11:24:16.34#ibcon#flushed, iclass 3, count 2 2006.173.11:24:16.34#ibcon#about to write, iclass 3, count 2 2006.173.11:24:16.34#ibcon#wrote, iclass 3, count 2 2006.173.11:24:16.34#ibcon#about to read 3, iclass 3, count 2 2006.173.11:24:16.37#ibcon#read 3, iclass 3, count 2 2006.173.11:24:16.37#ibcon#about to read 4, iclass 3, count 2 2006.173.11:24:16.37#ibcon#read 4, iclass 3, count 2 2006.173.11:24:16.37#ibcon#about to read 5, iclass 3, count 2 2006.173.11:24:16.37#ibcon#read 5, iclass 3, count 2 2006.173.11:24:16.37#ibcon#about to read 6, iclass 3, count 2 2006.173.11:24:16.37#ibcon#read 6, iclass 3, count 2 2006.173.11:24:16.37#ibcon#end of sib2, iclass 3, count 2 2006.173.11:24:16.37#ibcon#*after write, iclass 3, count 2 2006.173.11:24:16.37#ibcon#*before return 0, iclass 3, count 2 2006.173.11:24:16.37#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.11:24:16.37#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.11:24:16.37#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.11:24:16.37#ibcon#ireg 7 cls_cnt 0 2006.173.11:24:16.37#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.11:24:16.49#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.11:24:16.49#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.11:24:16.49#ibcon#enter wrdev, iclass 3, count 0 2006.173.11:24:16.49#ibcon#first serial, iclass 3, count 0 2006.173.11:24:16.49#ibcon#enter sib2, iclass 3, count 0 2006.173.11:24:16.49#ibcon#flushed, iclass 3, count 0 2006.173.11:24:16.49#ibcon#about to write, iclass 3, count 0 2006.173.11:24:16.49#ibcon#wrote, iclass 3, count 0 2006.173.11:24:16.49#ibcon#about to read 3, iclass 3, count 0 2006.173.11:24:16.51#ibcon#read 3, iclass 3, count 0 2006.173.11:24:16.51#ibcon#about to read 4, iclass 3, count 0 2006.173.11:24:16.51#ibcon#read 4, iclass 3, count 0 2006.173.11:24:16.51#ibcon#about to read 5, iclass 3, count 0 2006.173.11:24:16.51#ibcon#read 5, iclass 3, count 0 2006.173.11:24:16.51#ibcon#about to read 6, iclass 3, count 0 2006.173.11:24:16.51#ibcon#read 6, iclass 3, count 0 2006.173.11:24:16.51#ibcon#end of sib2, iclass 3, count 0 2006.173.11:24:16.51#ibcon#*mode == 0, iclass 3, count 0 2006.173.11:24:16.51#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.11:24:16.51#ibcon#[27=USB\r\n] 2006.173.11:24:16.51#ibcon#*before write, iclass 3, count 0 2006.173.11:24:16.51#ibcon#enter sib2, iclass 3, count 0 2006.173.11:24:16.51#ibcon#flushed, iclass 3, count 0 2006.173.11:24:16.51#ibcon#about to write, iclass 3, count 0 2006.173.11:24:16.51#ibcon#wrote, iclass 3, count 0 2006.173.11:24:16.51#ibcon#about to read 3, iclass 3, count 0 2006.173.11:24:16.54#ibcon#read 3, iclass 3, count 0 2006.173.11:24:16.54#ibcon#about to read 4, iclass 3, count 0 2006.173.11:24:16.54#ibcon#read 4, iclass 3, count 0 2006.173.11:24:16.54#ibcon#about to read 5, iclass 3, count 0 2006.173.11:24:16.54#ibcon#read 5, iclass 3, count 0 2006.173.11:24:16.54#ibcon#about to read 6, iclass 3, count 0 2006.173.11:24:16.54#ibcon#read 6, iclass 3, count 0 2006.173.11:24:16.54#ibcon#end of sib2, iclass 3, count 0 2006.173.11:24:16.54#ibcon#*after write, iclass 3, count 0 2006.173.11:24:16.54#ibcon#*before return 0, iclass 3, count 0 2006.173.11:24:16.54#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.11:24:16.54#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.11:24:16.54#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.11:24:16.54#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.11:24:16.54$vck44/vblo=3,649.99 2006.173.11:24:16.54#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.11:24:16.54#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.11:24:16.54#ibcon#ireg 17 cls_cnt 0 2006.173.11:24:16.54#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.11:24:16.54#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.11:24:16.54#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.11:24:16.54#ibcon#enter wrdev, iclass 5, count 0 2006.173.11:24:16.54#ibcon#first serial, iclass 5, count 0 2006.173.11:24:16.54#ibcon#enter sib2, iclass 5, count 0 2006.173.11:24:16.54#ibcon#flushed, iclass 5, count 0 2006.173.11:24:16.54#ibcon#about to write, iclass 5, count 0 2006.173.11:24:16.54#ibcon#wrote, iclass 5, count 0 2006.173.11:24:16.54#ibcon#about to read 3, iclass 5, count 0 2006.173.11:24:16.56#ibcon#read 3, iclass 5, count 0 2006.173.11:24:16.56#ibcon#about to read 4, iclass 5, count 0 2006.173.11:24:16.56#ibcon#read 4, iclass 5, count 0 2006.173.11:24:16.56#ibcon#about to read 5, iclass 5, count 0 2006.173.11:24:16.56#ibcon#read 5, iclass 5, count 0 2006.173.11:24:16.56#ibcon#about to read 6, iclass 5, count 0 2006.173.11:24:16.56#ibcon#read 6, iclass 5, count 0 2006.173.11:24:16.56#ibcon#end of sib2, iclass 5, count 0 2006.173.11:24:16.56#ibcon#*mode == 0, iclass 5, count 0 2006.173.11:24:16.56#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.11:24:16.56#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.11:24:16.56#ibcon#*before write, iclass 5, count 0 2006.173.11:24:16.56#ibcon#enter sib2, iclass 5, count 0 2006.173.11:24:16.56#ibcon#flushed, iclass 5, count 0 2006.173.11:24:16.56#ibcon#about to write, iclass 5, count 0 2006.173.11:24:16.56#ibcon#wrote, iclass 5, count 0 2006.173.11:24:16.56#ibcon#about to read 3, iclass 5, count 0 2006.173.11:24:16.60#ibcon#read 3, iclass 5, count 0 2006.173.11:24:16.60#ibcon#about to read 4, iclass 5, count 0 2006.173.11:24:16.60#ibcon#read 4, iclass 5, count 0 2006.173.11:24:16.60#ibcon#about to read 5, iclass 5, count 0 2006.173.11:24:16.60#ibcon#read 5, iclass 5, count 0 2006.173.11:24:16.60#ibcon#about to read 6, iclass 5, count 0 2006.173.11:24:16.60#ibcon#read 6, iclass 5, count 0 2006.173.11:24:16.60#ibcon#end of sib2, iclass 5, count 0 2006.173.11:24:16.60#ibcon#*after write, iclass 5, count 0 2006.173.11:24:16.60#ibcon#*before return 0, iclass 5, count 0 2006.173.11:24:16.60#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.11:24:16.60#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.11:24:16.60#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.11:24:16.60#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.11:24:16.60$vck44/vb=3,4 2006.173.11:24:16.60#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.173.11:24:16.60#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.173.11:24:16.60#ibcon#ireg 11 cls_cnt 2 2006.173.11:24:16.60#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.11:24:16.66#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.11:24:16.66#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.11:24:16.66#ibcon#enter wrdev, iclass 7, count 2 2006.173.11:24:16.66#ibcon#first serial, iclass 7, count 2 2006.173.11:24:16.66#ibcon#enter sib2, iclass 7, count 2 2006.173.11:24:16.66#ibcon#flushed, iclass 7, count 2 2006.173.11:24:16.66#ibcon#about to write, iclass 7, count 2 2006.173.11:24:16.66#ibcon#wrote, iclass 7, count 2 2006.173.11:24:16.66#ibcon#about to read 3, iclass 7, count 2 2006.173.11:24:16.68#ibcon#read 3, iclass 7, count 2 2006.173.11:24:16.68#ibcon#about to read 4, iclass 7, count 2 2006.173.11:24:16.68#ibcon#read 4, iclass 7, count 2 2006.173.11:24:16.68#ibcon#about to read 5, iclass 7, count 2 2006.173.11:24:16.68#ibcon#read 5, iclass 7, count 2 2006.173.11:24:16.68#ibcon#about to read 6, iclass 7, count 2 2006.173.11:24:16.68#ibcon#read 6, iclass 7, count 2 2006.173.11:24:16.68#ibcon#end of sib2, iclass 7, count 2 2006.173.11:24:16.68#ibcon#*mode == 0, iclass 7, count 2 2006.173.11:24:16.68#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.173.11:24:16.68#ibcon#[27=AT03-04\r\n] 2006.173.11:24:16.68#ibcon#*before write, iclass 7, count 2 2006.173.11:24:16.68#ibcon#enter sib2, iclass 7, count 2 2006.173.11:24:16.68#ibcon#flushed, iclass 7, count 2 2006.173.11:24:16.68#ibcon#about to write, iclass 7, count 2 2006.173.11:24:16.68#ibcon#wrote, iclass 7, count 2 2006.173.11:24:16.68#ibcon#about to read 3, iclass 7, count 2 2006.173.11:24:16.71#ibcon#read 3, iclass 7, count 2 2006.173.11:24:16.71#ibcon#about to read 4, iclass 7, count 2 2006.173.11:24:16.71#ibcon#read 4, iclass 7, count 2 2006.173.11:24:16.71#ibcon#about to read 5, iclass 7, count 2 2006.173.11:24:16.71#ibcon#read 5, iclass 7, count 2 2006.173.11:24:16.71#ibcon#about to read 6, iclass 7, count 2 2006.173.11:24:16.71#ibcon#read 6, iclass 7, count 2 2006.173.11:24:16.71#ibcon#end of sib2, iclass 7, count 2 2006.173.11:24:16.71#ibcon#*after write, iclass 7, count 2 2006.173.11:24:16.71#ibcon#*before return 0, iclass 7, count 2 2006.173.11:24:16.71#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.11:24:16.71#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.173.11:24:16.71#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.173.11:24:16.71#ibcon#ireg 7 cls_cnt 0 2006.173.11:24:16.71#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.11:24:16.83#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.11:24:16.83#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.11:24:16.83#ibcon#enter wrdev, iclass 7, count 0 2006.173.11:24:16.83#ibcon#first serial, iclass 7, count 0 2006.173.11:24:16.83#ibcon#enter sib2, iclass 7, count 0 2006.173.11:24:16.83#ibcon#flushed, iclass 7, count 0 2006.173.11:24:16.83#ibcon#about to write, iclass 7, count 0 2006.173.11:24:16.83#ibcon#wrote, iclass 7, count 0 2006.173.11:24:16.83#ibcon#about to read 3, iclass 7, count 0 2006.173.11:24:16.85#ibcon#read 3, iclass 7, count 0 2006.173.11:24:16.85#ibcon#about to read 4, iclass 7, count 0 2006.173.11:24:16.85#ibcon#read 4, iclass 7, count 0 2006.173.11:24:16.85#ibcon#about to read 5, iclass 7, count 0 2006.173.11:24:16.85#ibcon#read 5, iclass 7, count 0 2006.173.11:24:16.85#ibcon#about to read 6, iclass 7, count 0 2006.173.11:24:16.85#ibcon#read 6, iclass 7, count 0 2006.173.11:24:16.85#ibcon#end of sib2, iclass 7, count 0 2006.173.11:24:16.85#ibcon#*mode == 0, iclass 7, count 0 2006.173.11:24:16.85#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.11:24:16.85#ibcon#[27=USB\r\n] 2006.173.11:24:16.85#ibcon#*before write, iclass 7, count 0 2006.173.11:24:16.85#ibcon#enter sib2, iclass 7, count 0 2006.173.11:24:16.85#ibcon#flushed, iclass 7, count 0 2006.173.11:24:16.85#ibcon#about to write, iclass 7, count 0 2006.173.11:24:16.85#ibcon#wrote, iclass 7, count 0 2006.173.11:24:16.85#ibcon#about to read 3, iclass 7, count 0 2006.173.11:24:16.88#ibcon#read 3, iclass 7, count 0 2006.173.11:24:16.88#ibcon#about to read 4, iclass 7, count 0 2006.173.11:24:16.88#ibcon#read 4, iclass 7, count 0 2006.173.11:24:16.88#ibcon#about to read 5, iclass 7, count 0 2006.173.11:24:16.88#ibcon#read 5, iclass 7, count 0 2006.173.11:24:16.88#ibcon#about to read 6, iclass 7, count 0 2006.173.11:24:16.88#ibcon#read 6, iclass 7, count 0 2006.173.11:24:16.88#ibcon#end of sib2, iclass 7, count 0 2006.173.11:24:16.88#ibcon#*after write, iclass 7, count 0 2006.173.11:24:16.88#ibcon#*before return 0, iclass 7, count 0 2006.173.11:24:16.88#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.11:24:16.88#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.173.11:24:16.88#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.11:24:16.88#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.11:24:16.88$vck44/vblo=4,679.99 2006.173.11:24:16.88#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.11:24:16.88#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.11:24:16.88#ibcon#ireg 17 cls_cnt 0 2006.173.11:24:16.88#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.11:24:16.88#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.11:24:16.88#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.11:24:16.88#ibcon#enter wrdev, iclass 11, count 0 2006.173.11:24:16.88#ibcon#first serial, iclass 11, count 0 2006.173.11:24:16.88#ibcon#enter sib2, iclass 11, count 0 2006.173.11:24:16.88#ibcon#flushed, iclass 11, count 0 2006.173.11:24:16.88#ibcon#about to write, iclass 11, count 0 2006.173.11:24:16.88#ibcon#wrote, iclass 11, count 0 2006.173.11:24:16.88#ibcon#about to read 3, iclass 11, count 0 2006.173.11:24:16.90#ibcon#read 3, iclass 11, count 0 2006.173.11:24:16.90#ibcon#about to read 4, iclass 11, count 0 2006.173.11:24:16.90#ibcon#read 4, iclass 11, count 0 2006.173.11:24:16.90#ibcon#about to read 5, iclass 11, count 0 2006.173.11:24:16.90#ibcon#read 5, iclass 11, count 0 2006.173.11:24:16.90#ibcon#about to read 6, iclass 11, count 0 2006.173.11:24:16.90#ibcon#read 6, iclass 11, count 0 2006.173.11:24:16.90#ibcon#end of sib2, iclass 11, count 0 2006.173.11:24:16.90#ibcon#*mode == 0, iclass 11, count 0 2006.173.11:24:16.90#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.11:24:16.90#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.11:24:16.90#ibcon#*before write, iclass 11, count 0 2006.173.11:24:16.90#ibcon#enter sib2, iclass 11, count 0 2006.173.11:24:16.90#ibcon#flushed, iclass 11, count 0 2006.173.11:24:16.90#ibcon#about to write, iclass 11, count 0 2006.173.11:24:16.90#ibcon#wrote, iclass 11, count 0 2006.173.11:24:16.90#ibcon#about to read 3, iclass 11, count 0 2006.173.11:24:16.94#ibcon#read 3, iclass 11, count 0 2006.173.11:24:16.94#ibcon#about to read 4, iclass 11, count 0 2006.173.11:24:16.94#ibcon#read 4, iclass 11, count 0 2006.173.11:24:16.94#ibcon#about to read 5, iclass 11, count 0 2006.173.11:24:16.94#ibcon#read 5, iclass 11, count 0 2006.173.11:24:16.94#ibcon#about to read 6, iclass 11, count 0 2006.173.11:24:16.94#ibcon#read 6, iclass 11, count 0 2006.173.11:24:16.94#ibcon#end of sib2, iclass 11, count 0 2006.173.11:24:16.94#ibcon#*after write, iclass 11, count 0 2006.173.11:24:16.94#ibcon#*before return 0, iclass 11, count 0 2006.173.11:24:16.94#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.11:24:16.94#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.11:24:16.94#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.11:24:16.94#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.11:24:16.94$vck44/vb=4,4 2006.173.11:24:16.94#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.173.11:24:16.94#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.173.11:24:16.94#ibcon#ireg 11 cls_cnt 2 2006.173.11:24:16.94#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.11:24:17.00#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.11:24:17.00#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.11:24:17.00#ibcon#enter wrdev, iclass 13, count 2 2006.173.11:24:17.00#ibcon#first serial, iclass 13, count 2 2006.173.11:24:17.00#ibcon#enter sib2, iclass 13, count 2 2006.173.11:24:17.00#ibcon#flushed, iclass 13, count 2 2006.173.11:24:17.00#ibcon#about to write, iclass 13, count 2 2006.173.11:24:17.00#ibcon#wrote, iclass 13, count 2 2006.173.11:24:17.00#ibcon#about to read 3, iclass 13, count 2 2006.173.11:24:17.02#ibcon#read 3, iclass 13, count 2 2006.173.11:24:17.02#ibcon#about to read 4, iclass 13, count 2 2006.173.11:24:17.02#ibcon#read 4, iclass 13, count 2 2006.173.11:24:17.02#ibcon#about to read 5, iclass 13, count 2 2006.173.11:24:17.02#ibcon#read 5, iclass 13, count 2 2006.173.11:24:17.02#ibcon#about to read 6, iclass 13, count 2 2006.173.11:24:17.02#ibcon#read 6, iclass 13, count 2 2006.173.11:24:17.02#ibcon#end of sib2, iclass 13, count 2 2006.173.11:24:17.02#ibcon#*mode == 0, iclass 13, count 2 2006.173.11:24:17.02#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.173.11:24:17.02#ibcon#[27=AT04-04\r\n] 2006.173.11:24:17.02#ibcon#*before write, iclass 13, count 2 2006.173.11:24:17.02#ibcon#enter sib2, iclass 13, count 2 2006.173.11:24:17.02#ibcon#flushed, iclass 13, count 2 2006.173.11:24:17.02#ibcon#about to write, iclass 13, count 2 2006.173.11:24:17.02#ibcon#wrote, iclass 13, count 2 2006.173.11:24:17.02#ibcon#about to read 3, iclass 13, count 2 2006.173.11:24:17.05#ibcon#read 3, iclass 13, count 2 2006.173.11:24:17.05#ibcon#about to read 4, iclass 13, count 2 2006.173.11:24:17.05#ibcon#read 4, iclass 13, count 2 2006.173.11:24:17.05#ibcon#about to read 5, iclass 13, count 2 2006.173.11:24:17.05#ibcon#read 5, iclass 13, count 2 2006.173.11:24:17.05#ibcon#about to read 6, iclass 13, count 2 2006.173.11:24:17.05#ibcon#read 6, iclass 13, count 2 2006.173.11:24:17.05#ibcon#end of sib2, iclass 13, count 2 2006.173.11:24:17.05#ibcon#*after write, iclass 13, count 2 2006.173.11:24:17.05#ibcon#*before return 0, iclass 13, count 2 2006.173.11:24:17.05#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.11:24:17.05#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.173.11:24:17.05#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.173.11:24:17.05#ibcon#ireg 7 cls_cnt 0 2006.173.11:24:17.05#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.11:24:17.17#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.11:24:17.17#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.11:24:17.17#ibcon#enter wrdev, iclass 13, count 0 2006.173.11:24:17.17#ibcon#first serial, iclass 13, count 0 2006.173.11:24:17.17#ibcon#enter sib2, iclass 13, count 0 2006.173.11:24:17.17#ibcon#flushed, iclass 13, count 0 2006.173.11:24:17.17#ibcon#about to write, iclass 13, count 0 2006.173.11:24:17.17#ibcon#wrote, iclass 13, count 0 2006.173.11:24:17.17#ibcon#about to read 3, iclass 13, count 0 2006.173.11:24:17.19#ibcon#read 3, iclass 13, count 0 2006.173.11:24:17.19#ibcon#about to read 4, iclass 13, count 0 2006.173.11:24:17.19#ibcon#read 4, iclass 13, count 0 2006.173.11:24:17.19#ibcon#about to read 5, iclass 13, count 0 2006.173.11:24:17.19#ibcon#read 5, iclass 13, count 0 2006.173.11:24:17.19#ibcon#about to read 6, iclass 13, count 0 2006.173.11:24:17.19#ibcon#read 6, iclass 13, count 0 2006.173.11:24:17.19#ibcon#end of sib2, iclass 13, count 0 2006.173.11:24:17.19#ibcon#*mode == 0, iclass 13, count 0 2006.173.11:24:17.19#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.11:24:17.19#ibcon#[27=USB\r\n] 2006.173.11:24:17.19#ibcon#*before write, iclass 13, count 0 2006.173.11:24:17.19#ibcon#enter sib2, iclass 13, count 0 2006.173.11:24:17.19#ibcon#flushed, iclass 13, count 0 2006.173.11:24:17.19#ibcon#about to write, iclass 13, count 0 2006.173.11:24:17.19#ibcon#wrote, iclass 13, count 0 2006.173.11:24:17.19#ibcon#about to read 3, iclass 13, count 0 2006.173.11:24:17.22#ibcon#read 3, iclass 13, count 0 2006.173.11:24:17.22#ibcon#about to read 4, iclass 13, count 0 2006.173.11:24:17.22#ibcon#read 4, iclass 13, count 0 2006.173.11:24:17.22#ibcon#about to read 5, iclass 13, count 0 2006.173.11:24:17.22#ibcon#read 5, iclass 13, count 0 2006.173.11:24:17.22#ibcon#about to read 6, iclass 13, count 0 2006.173.11:24:17.22#ibcon#read 6, iclass 13, count 0 2006.173.11:24:17.22#ibcon#end of sib2, iclass 13, count 0 2006.173.11:24:17.22#ibcon#*after write, iclass 13, count 0 2006.173.11:24:17.22#ibcon#*before return 0, iclass 13, count 0 2006.173.11:24:17.22#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.11:24:17.22#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.173.11:24:17.22#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.11:24:17.22#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.11:24:17.22$vck44/vblo=5,709.99 2006.173.11:24:17.22#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.11:24:17.22#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.11:24:17.22#ibcon#ireg 17 cls_cnt 0 2006.173.11:24:17.22#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.11:24:17.22#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.11:24:17.22#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.11:24:17.22#ibcon#enter wrdev, iclass 15, count 0 2006.173.11:24:17.22#ibcon#first serial, iclass 15, count 0 2006.173.11:24:17.22#ibcon#enter sib2, iclass 15, count 0 2006.173.11:24:17.22#ibcon#flushed, iclass 15, count 0 2006.173.11:24:17.22#ibcon#about to write, iclass 15, count 0 2006.173.11:24:17.22#ibcon#wrote, iclass 15, count 0 2006.173.11:24:17.22#ibcon#about to read 3, iclass 15, count 0 2006.173.11:24:17.24#ibcon#read 3, iclass 15, count 0 2006.173.11:24:17.24#ibcon#about to read 4, iclass 15, count 0 2006.173.11:24:17.24#ibcon#read 4, iclass 15, count 0 2006.173.11:24:17.24#ibcon#about to read 5, iclass 15, count 0 2006.173.11:24:17.24#ibcon#read 5, iclass 15, count 0 2006.173.11:24:17.24#ibcon#about to read 6, iclass 15, count 0 2006.173.11:24:17.24#ibcon#read 6, iclass 15, count 0 2006.173.11:24:17.24#ibcon#end of sib2, iclass 15, count 0 2006.173.11:24:17.24#ibcon#*mode == 0, iclass 15, count 0 2006.173.11:24:17.24#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.11:24:17.24#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.11:24:17.24#ibcon#*before write, iclass 15, count 0 2006.173.11:24:17.24#ibcon#enter sib2, iclass 15, count 0 2006.173.11:24:17.24#ibcon#flushed, iclass 15, count 0 2006.173.11:24:17.24#ibcon#about to write, iclass 15, count 0 2006.173.11:24:17.24#ibcon#wrote, iclass 15, count 0 2006.173.11:24:17.24#ibcon#about to read 3, iclass 15, count 0 2006.173.11:24:17.28#ibcon#read 3, iclass 15, count 0 2006.173.11:24:17.28#ibcon#about to read 4, iclass 15, count 0 2006.173.11:24:17.28#ibcon#read 4, iclass 15, count 0 2006.173.11:24:17.28#ibcon#about to read 5, iclass 15, count 0 2006.173.11:24:17.28#ibcon#read 5, iclass 15, count 0 2006.173.11:24:17.28#ibcon#about to read 6, iclass 15, count 0 2006.173.11:24:17.28#ibcon#read 6, iclass 15, count 0 2006.173.11:24:17.28#ibcon#end of sib2, iclass 15, count 0 2006.173.11:24:17.28#ibcon#*after write, iclass 15, count 0 2006.173.11:24:17.28#ibcon#*before return 0, iclass 15, count 0 2006.173.11:24:17.28#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.11:24:17.28#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.11:24:17.28#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.11:24:17.28#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.11:24:17.28$vck44/vb=5,4 2006.173.11:24:17.28#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.11:24:17.28#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.11:24:17.28#ibcon#ireg 11 cls_cnt 2 2006.173.11:24:17.28#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.11:24:17.34#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.11:24:17.34#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.11:24:17.34#ibcon#enter wrdev, iclass 17, count 2 2006.173.11:24:17.34#ibcon#first serial, iclass 17, count 2 2006.173.11:24:17.34#ibcon#enter sib2, iclass 17, count 2 2006.173.11:24:17.34#ibcon#flushed, iclass 17, count 2 2006.173.11:24:17.34#ibcon#about to write, iclass 17, count 2 2006.173.11:24:17.34#ibcon#wrote, iclass 17, count 2 2006.173.11:24:17.34#ibcon#about to read 3, iclass 17, count 2 2006.173.11:24:17.36#ibcon#read 3, iclass 17, count 2 2006.173.11:24:17.36#ibcon#about to read 4, iclass 17, count 2 2006.173.11:24:17.36#ibcon#read 4, iclass 17, count 2 2006.173.11:24:17.36#ibcon#about to read 5, iclass 17, count 2 2006.173.11:24:17.36#ibcon#read 5, iclass 17, count 2 2006.173.11:24:17.36#ibcon#about to read 6, iclass 17, count 2 2006.173.11:24:17.36#ibcon#read 6, iclass 17, count 2 2006.173.11:24:17.36#ibcon#end of sib2, iclass 17, count 2 2006.173.11:24:17.36#ibcon#*mode == 0, iclass 17, count 2 2006.173.11:24:17.36#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.11:24:17.36#ibcon#[27=AT05-04\r\n] 2006.173.11:24:17.36#ibcon#*before write, iclass 17, count 2 2006.173.11:24:17.36#ibcon#enter sib2, iclass 17, count 2 2006.173.11:24:17.36#ibcon#flushed, iclass 17, count 2 2006.173.11:24:17.36#ibcon#about to write, iclass 17, count 2 2006.173.11:24:17.36#ibcon#wrote, iclass 17, count 2 2006.173.11:24:17.36#ibcon#about to read 3, iclass 17, count 2 2006.173.11:24:17.39#ibcon#read 3, iclass 17, count 2 2006.173.11:24:17.39#ibcon#about to read 4, iclass 17, count 2 2006.173.11:24:17.39#ibcon#read 4, iclass 17, count 2 2006.173.11:24:17.39#ibcon#about to read 5, iclass 17, count 2 2006.173.11:24:17.39#ibcon#read 5, iclass 17, count 2 2006.173.11:24:17.39#ibcon#about to read 6, iclass 17, count 2 2006.173.11:24:17.39#ibcon#read 6, iclass 17, count 2 2006.173.11:24:17.39#ibcon#end of sib2, iclass 17, count 2 2006.173.11:24:17.39#ibcon#*after write, iclass 17, count 2 2006.173.11:24:17.39#ibcon#*before return 0, iclass 17, count 2 2006.173.11:24:17.39#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.11:24:17.39#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.11:24:17.39#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.11:24:17.39#ibcon#ireg 7 cls_cnt 0 2006.173.11:24:17.39#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.11:24:17.51#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.11:24:17.51#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.11:24:17.51#ibcon#enter wrdev, iclass 17, count 0 2006.173.11:24:17.51#ibcon#first serial, iclass 17, count 0 2006.173.11:24:17.51#ibcon#enter sib2, iclass 17, count 0 2006.173.11:24:17.51#ibcon#flushed, iclass 17, count 0 2006.173.11:24:17.51#ibcon#about to write, iclass 17, count 0 2006.173.11:24:17.51#ibcon#wrote, iclass 17, count 0 2006.173.11:24:17.51#ibcon#about to read 3, iclass 17, count 0 2006.173.11:24:17.53#ibcon#read 3, iclass 17, count 0 2006.173.11:24:17.53#ibcon#about to read 4, iclass 17, count 0 2006.173.11:24:17.53#ibcon#read 4, iclass 17, count 0 2006.173.11:24:17.53#ibcon#about to read 5, iclass 17, count 0 2006.173.11:24:17.53#ibcon#read 5, iclass 17, count 0 2006.173.11:24:17.53#ibcon#about to read 6, iclass 17, count 0 2006.173.11:24:17.53#ibcon#read 6, iclass 17, count 0 2006.173.11:24:17.53#ibcon#end of sib2, iclass 17, count 0 2006.173.11:24:17.53#ibcon#*mode == 0, iclass 17, count 0 2006.173.11:24:17.53#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.11:24:17.53#ibcon#[27=USB\r\n] 2006.173.11:24:17.53#ibcon#*before write, iclass 17, count 0 2006.173.11:24:17.53#ibcon#enter sib2, iclass 17, count 0 2006.173.11:24:17.53#ibcon#flushed, iclass 17, count 0 2006.173.11:24:17.53#ibcon#about to write, iclass 17, count 0 2006.173.11:24:17.53#ibcon#wrote, iclass 17, count 0 2006.173.11:24:17.53#ibcon#about to read 3, iclass 17, count 0 2006.173.11:24:17.56#ibcon#read 3, iclass 17, count 0 2006.173.11:24:17.56#ibcon#about to read 4, iclass 17, count 0 2006.173.11:24:17.56#ibcon#read 4, iclass 17, count 0 2006.173.11:24:17.56#ibcon#about to read 5, iclass 17, count 0 2006.173.11:24:17.56#ibcon#read 5, iclass 17, count 0 2006.173.11:24:17.56#ibcon#about to read 6, iclass 17, count 0 2006.173.11:24:17.56#ibcon#read 6, iclass 17, count 0 2006.173.11:24:17.56#ibcon#end of sib2, iclass 17, count 0 2006.173.11:24:17.56#ibcon#*after write, iclass 17, count 0 2006.173.11:24:17.56#ibcon#*before return 0, iclass 17, count 0 2006.173.11:24:17.56#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.11:24:17.56#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.11:24:17.56#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.11:24:17.56#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.11:24:17.56$vck44/vblo=6,719.99 2006.173.11:24:17.56#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.11:24:17.56#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.11:24:17.56#ibcon#ireg 17 cls_cnt 0 2006.173.11:24:17.56#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.11:24:17.56#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.11:24:17.56#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.11:24:17.56#ibcon#enter wrdev, iclass 19, count 0 2006.173.11:24:17.56#ibcon#first serial, iclass 19, count 0 2006.173.11:24:17.56#ibcon#enter sib2, iclass 19, count 0 2006.173.11:24:17.56#ibcon#flushed, iclass 19, count 0 2006.173.11:24:17.56#ibcon#about to write, iclass 19, count 0 2006.173.11:24:17.56#ibcon#wrote, iclass 19, count 0 2006.173.11:24:17.56#ibcon#about to read 3, iclass 19, count 0 2006.173.11:24:17.58#ibcon#read 3, iclass 19, count 0 2006.173.11:24:17.58#ibcon#about to read 4, iclass 19, count 0 2006.173.11:24:17.58#ibcon#read 4, iclass 19, count 0 2006.173.11:24:17.58#ibcon#about to read 5, iclass 19, count 0 2006.173.11:24:17.58#ibcon#read 5, iclass 19, count 0 2006.173.11:24:17.58#ibcon#about to read 6, iclass 19, count 0 2006.173.11:24:17.58#ibcon#read 6, iclass 19, count 0 2006.173.11:24:17.58#ibcon#end of sib2, iclass 19, count 0 2006.173.11:24:17.58#ibcon#*mode == 0, iclass 19, count 0 2006.173.11:24:17.58#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.11:24:17.58#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.11:24:17.58#ibcon#*before write, iclass 19, count 0 2006.173.11:24:17.58#ibcon#enter sib2, iclass 19, count 0 2006.173.11:24:17.58#ibcon#flushed, iclass 19, count 0 2006.173.11:24:17.58#ibcon#about to write, iclass 19, count 0 2006.173.11:24:17.58#ibcon#wrote, iclass 19, count 0 2006.173.11:24:17.58#ibcon#about to read 3, iclass 19, count 0 2006.173.11:24:17.62#ibcon#read 3, iclass 19, count 0 2006.173.11:24:17.62#ibcon#about to read 4, iclass 19, count 0 2006.173.11:24:17.62#ibcon#read 4, iclass 19, count 0 2006.173.11:24:17.62#ibcon#about to read 5, iclass 19, count 0 2006.173.11:24:17.62#ibcon#read 5, iclass 19, count 0 2006.173.11:24:17.62#ibcon#about to read 6, iclass 19, count 0 2006.173.11:24:17.62#ibcon#read 6, iclass 19, count 0 2006.173.11:24:17.62#ibcon#end of sib2, iclass 19, count 0 2006.173.11:24:17.62#ibcon#*after write, iclass 19, count 0 2006.173.11:24:17.62#ibcon#*before return 0, iclass 19, count 0 2006.173.11:24:17.62#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.11:24:17.62#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.11:24:17.62#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.11:24:17.62#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.11:24:17.62$vck44/vb=6,4 2006.173.11:24:17.62#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.11:24:17.62#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.11:24:17.62#ibcon#ireg 11 cls_cnt 2 2006.173.11:24:17.62#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.11:24:17.68#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.11:24:17.68#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.11:24:17.68#ibcon#enter wrdev, iclass 21, count 2 2006.173.11:24:17.68#ibcon#first serial, iclass 21, count 2 2006.173.11:24:17.68#ibcon#enter sib2, iclass 21, count 2 2006.173.11:24:17.68#ibcon#flushed, iclass 21, count 2 2006.173.11:24:17.68#ibcon#about to write, iclass 21, count 2 2006.173.11:24:17.68#ibcon#wrote, iclass 21, count 2 2006.173.11:24:17.68#ibcon#about to read 3, iclass 21, count 2 2006.173.11:24:17.70#ibcon#read 3, iclass 21, count 2 2006.173.11:24:17.70#ibcon#about to read 4, iclass 21, count 2 2006.173.11:24:17.70#ibcon#read 4, iclass 21, count 2 2006.173.11:24:17.70#ibcon#about to read 5, iclass 21, count 2 2006.173.11:24:17.70#ibcon#read 5, iclass 21, count 2 2006.173.11:24:17.70#ibcon#about to read 6, iclass 21, count 2 2006.173.11:24:17.70#ibcon#read 6, iclass 21, count 2 2006.173.11:24:17.70#ibcon#end of sib2, iclass 21, count 2 2006.173.11:24:17.70#ibcon#*mode == 0, iclass 21, count 2 2006.173.11:24:17.70#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.11:24:17.70#ibcon#[27=AT06-04\r\n] 2006.173.11:24:17.70#ibcon#*before write, iclass 21, count 2 2006.173.11:24:17.70#ibcon#enter sib2, iclass 21, count 2 2006.173.11:24:17.70#ibcon#flushed, iclass 21, count 2 2006.173.11:24:17.70#ibcon#about to write, iclass 21, count 2 2006.173.11:24:17.70#ibcon#wrote, iclass 21, count 2 2006.173.11:24:17.70#ibcon#about to read 3, iclass 21, count 2 2006.173.11:24:17.73#ibcon#read 3, iclass 21, count 2 2006.173.11:24:17.73#ibcon#about to read 4, iclass 21, count 2 2006.173.11:24:17.73#ibcon#read 4, iclass 21, count 2 2006.173.11:24:17.73#ibcon#about to read 5, iclass 21, count 2 2006.173.11:24:17.73#ibcon#read 5, iclass 21, count 2 2006.173.11:24:17.73#ibcon#about to read 6, iclass 21, count 2 2006.173.11:24:17.73#ibcon#read 6, iclass 21, count 2 2006.173.11:24:17.73#ibcon#end of sib2, iclass 21, count 2 2006.173.11:24:17.73#ibcon#*after write, iclass 21, count 2 2006.173.11:24:17.73#ibcon#*before return 0, iclass 21, count 2 2006.173.11:24:17.73#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.11:24:17.73#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.11:24:17.73#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.11:24:17.73#ibcon#ireg 7 cls_cnt 0 2006.173.11:24:17.73#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.11:24:17.85#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.11:24:17.85#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.11:24:17.85#ibcon#enter wrdev, iclass 21, count 0 2006.173.11:24:17.85#ibcon#first serial, iclass 21, count 0 2006.173.11:24:17.85#ibcon#enter sib2, iclass 21, count 0 2006.173.11:24:17.85#ibcon#flushed, iclass 21, count 0 2006.173.11:24:17.85#ibcon#about to write, iclass 21, count 0 2006.173.11:24:17.85#ibcon#wrote, iclass 21, count 0 2006.173.11:24:17.85#ibcon#about to read 3, iclass 21, count 0 2006.173.11:24:17.87#ibcon#read 3, iclass 21, count 0 2006.173.11:24:17.87#ibcon#about to read 4, iclass 21, count 0 2006.173.11:24:17.87#ibcon#read 4, iclass 21, count 0 2006.173.11:24:17.87#ibcon#about to read 5, iclass 21, count 0 2006.173.11:24:17.87#ibcon#read 5, iclass 21, count 0 2006.173.11:24:17.87#ibcon#about to read 6, iclass 21, count 0 2006.173.11:24:17.87#ibcon#read 6, iclass 21, count 0 2006.173.11:24:17.87#ibcon#end of sib2, iclass 21, count 0 2006.173.11:24:17.87#ibcon#*mode == 0, iclass 21, count 0 2006.173.11:24:17.87#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.11:24:17.87#ibcon#[27=USB\r\n] 2006.173.11:24:17.87#ibcon#*before write, iclass 21, count 0 2006.173.11:24:17.87#ibcon#enter sib2, iclass 21, count 0 2006.173.11:24:17.87#ibcon#flushed, iclass 21, count 0 2006.173.11:24:17.87#ibcon#about to write, iclass 21, count 0 2006.173.11:24:17.87#ibcon#wrote, iclass 21, count 0 2006.173.11:24:17.87#ibcon#about to read 3, iclass 21, count 0 2006.173.11:24:17.90#ibcon#read 3, iclass 21, count 0 2006.173.11:24:17.90#ibcon#about to read 4, iclass 21, count 0 2006.173.11:24:17.90#ibcon#read 4, iclass 21, count 0 2006.173.11:24:17.90#ibcon#about to read 5, iclass 21, count 0 2006.173.11:24:17.90#ibcon#read 5, iclass 21, count 0 2006.173.11:24:17.90#ibcon#about to read 6, iclass 21, count 0 2006.173.11:24:17.90#ibcon#read 6, iclass 21, count 0 2006.173.11:24:17.90#ibcon#end of sib2, iclass 21, count 0 2006.173.11:24:17.90#ibcon#*after write, iclass 21, count 0 2006.173.11:24:17.90#ibcon#*before return 0, iclass 21, count 0 2006.173.11:24:17.90#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.11:24:17.90#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.11:24:17.90#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.11:24:17.90#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.11:24:17.90$vck44/vblo=7,734.99 2006.173.11:24:17.90#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.11:24:17.90#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.11:24:17.90#ibcon#ireg 17 cls_cnt 0 2006.173.11:24:17.90#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.11:24:17.90#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.11:24:17.90#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.11:24:17.90#ibcon#enter wrdev, iclass 23, count 0 2006.173.11:24:17.90#ibcon#first serial, iclass 23, count 0 2006.173.11:24:17.90#ibcon#enter sib2, iclass 23, count 0 2006.173.11:24:17.90#ibcon#flushed, iclass 23, count 0 2006.173.11:24:17.90#ibcon#about to write, iclass 23, count 0 2006.173.11:24:17.90#ibcon#wrote, iclass 23, count 0 2006.173.11:24:17.90#ibcon#about to read 3, iclass 23, count 0 2006.173.11:24:17.92#ibcon#read 3, iclass 23, count 0 2006.173.11:24:17.92#ibcon#about to read 4, iclass 23, count 0 2006.173.11:24:17.92#ibcon#read 4, iclass 23, count 0 2006.173.11:24:17.92#ibcon#about to read 5, iclass 23, count 0 2006.173.11:24:17.92#ibcon#read 5, iclass 23, count 0 2006.173.11:24:17.92#ibcon#about to read 6, iclass 23, count 0 2006.173.11:24:17.92#ibcon#read 6, iclass 23, count 0 2006.173.11:24:17.92#ibcon#end of sib2, iclass 23, count 0 2006.173.11:24:17.92#ibcon#*mode == 0, iclass 23, count 0 2006.173.11:24:17.92#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.11:24:17.92#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.11:24:17.92#ibcon#*before write, iclass 23, count 0 2006.173.11:24:17.92#ibcon#enter sib2, iclass 23, count 0 2006.173.11:24:17.92#ibcon#flushed, iclass 23, count 0 2006.173.11:24:17.92#ibcon#about to write, iclass 23, count 0 2006.173.11:24:17.92#ibcon#wrote, iclass 23, count 0 2006.173.11:24:17.92#ibcon#about to read 3, iclass 23, count 0 2006.173.11:24:17.96#ibcon#read 3, iclass 23, count 0 2006.173.11:24:17.96#ibcon#about to read 4, iclass 23, count 0 2006.173.11:24:17.96#ibcon#read 4, iclass 23, count 0 2006.173.11:24:17.96#ibcon#about to read 5, iclass 23, count 0 2006.173.11:24:17.96#ibcon#read 5, iclass 23, count 0 2006.173.11:24:17.96#ibcon#about to read 6, iclass 23, count 0 2006.173.11:24:17.96#ibcon#read 6, iclass 23, count 0 2006.173.11:24:17.96#ibcon#end of sib2, iclass 23, count 0 2006.173.11:24:17.96#ibcon#*after write, iclass 23, count 0 2006.173.11:24:17.96#ibcon#*before return 0, iclass 23, count 0 2006.173.11:24:17.96#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.11:24:17.96#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.11:24:17.96#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.11:24:17.96#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.11:24:17.96$vck44/vb=7,4 2006.173.11:24:17.96#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.11:24:17.96#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.11:24:17.96#ibcon#ireg 11 cls_cnt 2 2006.173.11:24:17.96#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.11:24:18.02#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.11:24:18.02#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.11:24:18.02#ibcon#enter wrdev, iclass 25, count 2 2006.173.11:24:18.02#ibcon#first serial, iclass 25, count 2 2006.173.11:24:18.02#ibcon#enter sib2, iclass 25, count 2 2006.173.11:24:18.02#ibcon#flushed, iclass 25, count 2 2006.173.11:24:18.02#ibcon#about to write, iclass 25, count 2 2006.173.11:24:18.02#ibcon#wrote, iclass 25, count 2 2006.173.11:24:18.02#ibcon#about to read 3, iclass 25, count 2 2006.173.11:24:18.04#ibcon#read 3, iclass 25, count 2 2006.173.11:24:18.04#ibcon#about to read 4, iclass 25, count 2 2006.173.11:24:18.04#ibcon#read 4, iclass 25, count 2 2006.173.11:24:18.04#ibcon#about to read 5, iclass 25, count 2 2006.173.11:24:18.04#ibcon#read 5, iclass 25, count 2 2006.173.11:24:18.04#ibcon#about to read 6, iclass 25, count 2 2006.173.11:24:18.04#ibcon#read 6, iclass 25, count 2 2006.173.11:24:18.04#ibcon#end of sib2, iclass 25, count 2 2006.173.11:24:18.04#ibcon#*mode == 0, iclass 25, count 2 2006.173.11:24:18.04#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.11:24:18.04#ibcon#[27=AT07-04\r\n] 2006.173.11:24:18.04#ibcon#*before write, iclass 25, count 2 2006.173.11:24:18.04#ibcon#enter sib2, iclass 25, count 2 2006.173.11:24:18.04#ibcon#flushed, iclass 25, count 2 2006.173.11:24:18.04#ibcon#about to write, iclass 25, count 2 2006.173.11:24:18.04#ibcon#wrote, iclass 25, count 2 2006.173.11:24:18.04#ibcon#about to read 3, iclass 25, count 2 2006.173.11:24:18.07#ibcon#read 3, iclass 25, count 2 2006.173.11:24:18.07#ibcon#about to read 4, iclass 25, count 2 2006.173.11:24:18.07#ibcon#read 4, iclass 25, count 2 2006.173.11:24:18.07#ibcon#about to read 5, iclass 25, count 2 2006.173.11:24:18.07#ibcon#read 5, iclass 25, count 2 2006.173.11:24:18.07#ibcon#about to read 6, iclass 25, count 2 2006.173.11:24:18.07#ibcon#read 6, iclass 25, count 2 2006.173.11:24:18.07#ibcon#end of sib2, iclass 25, count 2 2006.173.11:24:18.07#ibcon#*after write, iclass 25, count 2 2006.173.11:24:18.07#ibcon#*before return 0, iclass 25, count 2 2006.173.11:24:18.07#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.11:24:18.07#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.11:24:18.07#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.11:24:18.07#ibcon#ireg 7 cls_cnt 0 2006.173.11:24:18.07#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.11:24:18.19#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.11:24:18.19#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.11:24:18.19#ibcon#enter wrdev, iclass 25, count 0 2006.173.11:24:18.19#ibcon#first serial, iclass 25, count 0 2006.173.11:24:18.19#ibcon#enter sib2, iclass 25, count 0 2006.173.11:24:18.19#ibcon#flushed, iclass 25, count 0 2006.173.11:24:18.19#ibcon#about to write, iclass 25, count 0 2006.173.11:24:18.19#ibcon#wrote, iclass 25, count 0 2006.173.11:24:18.19#ibcon#about to read 3, iclass 25, count 0 2006.173.11:24:18.21#ibcon#read 3, iclass 25, count 0 2006.173.11:24:18.21#ibcon#about to read 4, iclass 25, count 0 2006.173.11:24:18.21#ibcon#read 4, iclass 25, count 0 2006.173.11:24:18.21#ibcon#about to read 5, iclass 25, count 0 2006.173.11:24:18.21#ibcon#read 5, iclass 25, count 0 2006.173.11:24:18.21#ibcon#about to read 6, iclass 25, count 0 2006.173.11:24:18.21#ibcon#read 6, iclass 25, count 0 2006.173.11:24:18.21#ibcon#end of sib2, iclass 25, count 0 2006.173.11:24:18.21#ibcon#*mode == 0, iclass 25, count 0 2006.173.11:24:18.21#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.11:24:18.21#ibcon#[27=USB\r\n] 2006.173.11:24:18.21#ibcon#*before write, iclass 25, count 0 2006.173.11:24:18.21#ibcon#enter sib2, iclass 25, count 0 2006.173.11:24:18.21#ibcon#flushed, iclass 25, count 0 2006.173.11:24:18.21#ibcon#about to write, iclass 25, count 0 2006.173.11:24:18.21#ibcon#wrote, iclass 25, count 0 2006.173.11:24:18.21#ibcon#about to read 3, iclass 25, count 0 2006.173.11:24:18.24#ibcon#read 3, iclass 25, count 0 2006.173.11:24:18.24#ibcon#about to read 4, iclass 25, count 0 2006.173.11:24:18.24#ibcon#read 4, iclass 25, count 0 2006.173.11:24:18.24#ibcon#about to read 5, iclass 25, count 0 2006.173.11:24:18.24#ibcon#read 5, iclass 25, count 0 2006.173.11:24:18.24#ibcon#about to read 6, iclass 25, count 0 2006.173.11:24:18.24#ibcon#read 6, iclass 25, count 0 2006.173.11:24:18.24#ibcon#end of sib2, iclass 25, count 0 2006.173.11:24:18.24#ibcon#*after write, iclass 25, count 0 2006.173.11:24:18.24#ibcon#*before return 0, iclass 25, count 0 2006.173.11:24:18.24#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.11:24:18.24#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.11:24:18.24#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.11:24:18.24#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.11:24:18.24$vck44/vblo=8,744.99 2006.173.11:24:18.24#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.11:24:18.24#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.11:24:18.24#ibcon#ireg 17 cls_cnt 0 2006.173.11:24:18.24#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.11:24:18.24#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.11:24:18.24#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.11:24:18.24#ibcon#enter wrdev, iclass 27, count 0 2006.173.11:24:18.24#ibcon#first serial, iclass 27, count 0 2006.173.11:24:18.24#ibcon#enter sib2, iclass 27, count 0 2006.173.11:24:18.24#ibcon#flushed, iclass 27, count 0 2006.173.11:24:18.24#ibcon#about to write, iclass 27, count 0 2006.173.11:24:18.24#ibcon#wrote, iclass 27, count 0 2006.173.11:24:18.24#ibcon#about to read 3, iclass 27, count 0 2006.173.11:24:18.26#ibcon#read 3, iclass 27, count 0 2006.173.11:24:18.26#ibcon#about to read 4, iclass 27, count 0 2006.173.11:24:18.26#ibcon#read 4, iclass 27, count 0 2006.173.11:24:18.26#ibcon#about to read 5, iclass 27, count 0 2006.173.11:24:18.26#ibcon#read 5, iclass 27, count 0 2006.173.11:24:18.26#ibcon#about to read 6, iclass 27, count 0 2006.173.11:24:18.26#ibcon#read 6, iclass 27, count 0 2006.173.11:24:18.26#ibcon#end of sib2, iclass 27, count 0 2006.173.11:24:18.26#ibcon#*mode == 0, iclass 27, count 0 2006.173.11:24:18.26#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.11:24:18.26#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.11:24:18.26#ibcon#*before write, iclass 27, count 0 2006.173.11:24:18.26#ibcon#enter sib2, iclass 27, count 0 2006.173.11:24:18.26#ibcon#flushed, iclass 27, count 0 2006.173.11:24:18.26#ibcon#about to write, iclass 27, count 0 2006.173.11:24:18.26#ibcon#wrote, iclass 27, count 0 2006.173.11:24:18.26#ibcon#about to read 3, iclass 27, count 0 2006.173.11:24:18.30#ibcon#read 3, iclass 27, count 0 2006.173.11:24:18.30#ibcon#about to read 4, iclass 27, count 0 2006.173.11:24:18.30#ibcon#read 4, iclass 27, count 0 2006.173.11:24:18.30#ibcon#about to read 5, iclass 27, count 0 2006.173.11:24:18.30#ibcon#read 5, iclass 27, count 0 2006.173.11:24:18.30#ibcon#about to read 6, iclass 27, count 0 2006.173.11:24:18.30#ibcon#read 6, iclass 27, count 0 2006.173.11:24:18.30#ibcon#end of sib2, iclass 27, count 0 2006.173.11:24:18.30#ibcon#*after write, iclass 27, count 0 2006.173.11:24:18.30#ibcon#*before return 0, iclass 27, count 0 2006.173.11:24:18.30#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.11:24:18.30#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.11:24:18.30#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.11:24:18.30#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.11:24:18.30$vck44/vb=8,4 2006.173.11:24:18.30#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.11:24:18.30#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.11:24:18.30#ibcon#ireg 11 cls_cnt 2 2006.173.11:24:18.30#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.11:24:18.36#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.11:24:18.36#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.11:24:18.36#ibcon#enter wrdev, iclass 29, count 2 2006.173.11:24:18.36#ibcon#first serial, iclass 29, count 2 2006.173.11:24:18.36#ibcon#enter sib2, iclass 29, count 2 2006.173.11:24:18.36#ibcon#flushed, iclass 29, count 2 2006.173.11:24:18.36#ibcon#about to write, iclass 29, count 2 2006.173.11:24:18.36#ibcon#wrote, iclass 29, count 2 2006.173.11:24:18.36#ibcon#about to read 3, iclass 29, count 2 2006.173.11:24:18.38#ibcon#read 3, iclass 29, count 2 2006.173.11:24:18.38#ibcon#about to read 4, iclass 29, count 2 2006.173.11:24:18.38#ibcon#read 4, iclass 29, count 2 2006.173.11:24:18.38#ibcon#about to read 5, iclass 29, count 2 2006.173.11:24:18.38#ibcon#read 5, iclass 29, count 2 2006.173.11:24:18.38#ibcon#about to read 6, iclass 29, count 2 2006.173.11:24:18.38#ibcon#read 6, iclass 29, count 2 2006.173.11:24:18.38#ibcon#end of sib2, iclass 29, count 2 2006.173.11:24:18.38#ibcon#*mode == 0, iclass 29, count 2 2006.173.11:24:18.38#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.11:24:18.38#ibcon#[27=AT08-04\r\n] 2006.173.11:24:18.38#ibcon#*before write, iclass 29, count 2 2006.173.11:24:18.38#ibcon#enter sib2, iclass 29, count 2 2006.173.11:24:18.38#ibcon#flushed, iclass 29, count 2 2006.173.11:24:18.38#ibcon#about to write, iclass 29, count 2 2006.173.11:24:18.38#ibcon#wrote, iclass 29, count 2 2006.173.11:24:18.38#ibcon#about to read 3, iclass 29, count 2 2006.173.11:24:18.41#ibcon#read 3, iclass 29, count 2 2006.173.11:24:18.41#ibcon#about to read 4, iclass 29, count 2 2006.173.11:24:18.41#ibcon#read 4, iclass 29, count 2 2006.173.11:24:18.41#ibcon#about to read 5, iclass 29, count 2 2006.173.11:24:18.41#ibcon#read 5, iclass 29, count 2 2006.173.11:24:18.41#ibcon#about to read 6, iclass 29, count 2 2006.173.11:24:18.41#ibcon#read 6, iclass 29, count 2 2006.173.11:24:18.41#ibcon#end of sib2, iclass 29, count 2 2006.173.11:24:18.41#ibcon#*after write, iclass 29, count 2 2006.173.11:24:18.41#ibcon#*before return 0, iclass 29, count 2 2006.173.11:24:18.41#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.11:24:18.41#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.11:24:18.41#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.11:24:18.41#ibcon#ireg 7 cls_cnt 0 2006.173.11:24:18.41#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.11:24:18.53#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.11:24:18.53#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.11:24:18.53#ibcon#enter wrdev, iclass 29, count 0 2006.173.11:24:18.53#ibcon#first serial, iclass 29, count 0 2006.173.11:24:18.53#ibcon#enter sib2, iclass 29, count 0 2006.173.11:24:18.53#ibcon#flushed, iclass 29, count 0 2006.173.11:24:18.53#ibcon#about to write, iclass 29, count 0 2006.173.11:24:18.53#ibcon#wrote, iclass 29, count 0 2006.173.11:24:18.53#ibcon#about to read 3, iclass 29, count 0 2006.173.11:24:18.55#ibcon#read 3, iclass 29, count 0 2006.173.11:24:18.55#ibcon#about to read 4, iclass 29, count 0 2006.173.11:24:18.55#ibcon#read 4, iclass 29, count 0 2006.173.11:24:18.55#ibcon#about to read 5, iclass 29, count 0 2006.173.11:24:18.55#ibcon#read 5, iclass 29, count 0 2006.173.11:24:18.55#ibcon#about to read 6, iclass 29, count 0 2006.173.11:24:18.55#ibcon#read 6, iclass 29, count 0 2006.173.11:24:18.55#ibcon#end of sib2, iclass 29, count 0 2006.173.11:24:18.55#ibcon#*mode == 0, iclass 29, count 0 2006.173.11:24:18.55#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.11:24:18.55#ibcon#[27=USB\r\n] 2006.173.11:24:18.55#ibcon#*before write, iclass 29, count 0 2006.173.11:24:18.55#ibcon#enter sib2, iclass 29, count 0 2006.173.11:24:18.55#ibcon#flushed, iclass 29, count 0 2006.173.11:24:18.55#ibcon#about to write, iclass 29, count 0 2006.173.11:24:18.55#ibcon#wrote, iclass 29, count 0 2006.173.11:24:18.55#ibcon#about to read 3, iclass 29, count 0 2006.173.11:24:18.58#ibcon#read 3, iclass 29, count 0 2006.173.11:24:18.58#ibcon#about to read 4, iclass 29, count 0 2006.173.11:24:18.58#ibcon#read 4, iclass 29, count 0 2006.173.11:24:18.58#ibcon#about to read 5, iclass 29, count 0 2006.173.11:24:18.58#ibcon#read 5, iclass 29, count 0 2006.173.11:24:18.58#ibcon#about to read 6, iclass 29, count 0 2006.173.11:24:18.58#ibcon#read 6, iclass 29, count 0 2006.173.11:24:18.58#ibcon#end of sib2, iclass 29, count 0 2006.173.11:24:18.58#ibcon#*after write, iclass 29, count 0 2006.173.11:24:18.58#ibcon#*before return 0, iclass 29, count 0 2006.173.11:24:18.58#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.11:24:18.58#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.11:24:18.58#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.11:24:18.58#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.11:24:18.58$vck44/vabw=wide 2006.173.11:24:18.58#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.11:24:18.58#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.11:24:18.58#ibcon#ireg 8 cls_cnt 0 2006.173.11:24:18.58#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.11:24:18.58#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.11:24:18.58#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.11:24:18.58#ibcon#enter wrdev, iclass 31, count 0 2006.173.11:24:18.58#ibcon#first serial, iclass 31, count 0 2006.173.11:24:18.58#ibcon#enter sib2, iclass 31, count 0 2006.173.11:24:18.58#ibcon#flushed, iclass 31, count 0 2006.173.11:24:18.58#ibcon#about to write, iclass 31, count 0 2006.173.11:24:18.58#ibcon#wrote, iclass 31, count 0 2006.173.11:24:18.58#ibcon#about to read 3, iclass 31, count 0 2006.173.11:24:18.60#ibcon#read 3, iclass 31, count 0 2006.173.11:24:18.60#ibcon#about to read 4, iclass 31, count 0 2006.173.11:24:18.60#ibcon#read 4, iclass 31, count 0 2006.173.11:24:18.60#ibcon#about to read 5, iclass 31, count 0 2006.173.11:24:18.60#ibcon#read 5, iclass 31, count 0 2006.173.11:24:18.60#ibcon#about to read 6, iclass 31, count 0 2006.173.11:24:18.60#ibcon#read 6, iclass 31, count 0 2006.173.11:24:18.60#ibcon#end of sib2, iclass 31, count 0 2006.173.11:24:18.60#ibcon#*mode == 0, iclass 31, count 0 2006.173.11:24:18.60#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.11:24:18.60#ibcon#[25=BW32\r\n] 2006.173.11:24:18.60#ibcon#*before write, iclass 31, count 0 2006.173.11:24:18.60#ibcon#enter sib2, iclass 31, count 0 2006.173.11:24:18.60#ibcon#flushed, iclass 31, count 0 2006.173.11:24:18.60#ibcon#about to write, iclass 31, count 0 2006.173.11:24:18.60#ibcon#wrote, iclass 31, count 0 2006.173.11:24:18.60#ibcon#about to read 3, iclass 31, count 0 2006.173.11:24:18.63#ibcon#read 3, iclass 31, count 0 2006.173.11:24:18.63#ibcon#about to read 4, iclass 31, count 0 2006.173.11:24:18.63#ibcon#read 4, iclass 31, count 0 2006.173.11:24:18.63#ibcon#about to read 5, iclass 31, count 0 2006.173.11:24:18.63#ibcon#read 5, iclass 31, count 0 2006.173.11:24:18.63#ibcon#about to read 6, iclass 31, count 0 2006.173.11:24:18.63#ibcon#read 6, iclass 31, count 0 2006.173.11:24:18.63#ibcon#end of sib2, iclass 31, count 0 2006.173.11:24:18.63#ibcon#*after write, iclass 31, count 0 2006.173.11:24:18.63#ibcon#*before return 0, iclass 31, count 0 2006.173.11:24:18.63#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.11:24:18.63#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.11:24:18.63#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.11:24:18.63#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.11:24:18.63$vck44/vbbw=wide 2006.173.11:24:18.63#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.11:24:18.63#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.11:24:18.63#ibcon#ireg 8 cls_cnt 0 2006.173.11:24:18.63#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.11:24:18.70#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.11:24:18.70#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.11:24:18.70#ibcon#enter wrdev, iclass 33, count 0 2006.173.11:24:18.70#ibcon#first serial, iclass 33, count 0 2006.173.11:24:18.70#ibcon#enter sib2, iclass 33, count 0 2006.173.11:24:18.70#ibcon#flushed, iclass 33, count 0 2006.173.11:24:18.70#ibcon#about to write, iclass 33, count 0 2006.173.11:24:18.70#ibcon#wrote, iclass 33, count 0 2006.173.11:24:18.70#ibcon#about to read 3, iclass 33, count 0 2006.173.11:24:18.72#ibcon#read 3, iclass 33, count 0 2006.173.11:24:18.72#ibcon#about to read 4, iclass 33, count 0 2006.173.11:24:18.72#ibcon#read 4, iclass 33, count 0 2006.173.11:24:18.72#ibcon#about to read 5, iclass 33, count 0 2006.173.11:24:18.72#ibcon#read 5, iclass 33, count 0 2006.173.11:24:18.72#ibcon#about to read 6, iclass 33, count 0 2006.173.11:24:18.72#ibcon#read 6, iclass 33, count 0 2006.173.11:24:18.72#ibcon#end of sib2, iclass 33, count 0 2006.173.11:24:18.72#ibcon#*mode == 0, iclass 33, count 0 2006.173.11:24:18.72#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.11:24:18.72#ibcon#[27=BW32\r\n] 2006.173.11:24:18.72#ibcon#*before write, iclass 33, count 0 2006.173.11:24:18.72#ibcon#enter sib2, iclass 33, count 0 2006.173.11:24:18.72#ibcon#flushed, iclass 33, count 0 2006.173.11:24:18.72#ibcon#about to write, iclass 33, count 0 2006.173.11:24:18.72#ibcon#wrote, iclass 33, count 0 2006.173.11:24:18.72#ibcon#about to read 3, iclass 33, count 0 2006.173.11:24:18.75#ibcon#read 3, iclass 33, count 0 2006.173.11:24:18.75#ibcon#about to read 4, iclass 33, count 0 2006.173.11:24:18.75#ibcon#read 4, iclass 33, count 0 2006.173.11:24:18.75#ibcon#about to read 5, iclass 33, count 0 2006.173.11:24:18.75#ibcon#read 5, iclass 33, count 0 2006.173.11:24:18.75#ibcon#about to read 6, iclass 33, count 0 2006.173.11:24:18.75#ibcon#read 6, iclass 33, count 0 2006.173.11:24:18.75#ibcon#end of sib2, iclass 33, count 0 2006.173.11:24:18.75#ibcon#*after write, iclass 33, count 0 2006.173.11:24:18.75#ibcon#*before return 0, iclass 33, count 0 2006.173.11:24:18.75#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.11:24:18.75#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.11:24:18.75#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.11:24:18.75#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.11:24:18.75$setupk4/ifdk4 2006.173.11:24:18.75$ifdk4/lo= 2006.173.11:24:18.75$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.11:24:18.75$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.11:24:18.75$ifdk4/patch= 2006.173.11:24:18.75$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.11:24:18.75$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.11:24:18.75$setupk4/!*+20s 2006.173.11:24:19.68#abcon#<5=/05 1.2 2.4 22.50 931003.8\r\n> 2006.173.11:24:19.70#abcon#{5=INTERFACE CLEAR} 2006.173.11:24:19.76#abcon#[5=S1D000X0/0*\r\n] 2006.173.11:24:29.85#abcon#<5=/05 1.3 3.1 22.50 931003.7\r\n> 2006.173.11:24:29.87#abcon#{5=INTERFACE CLEAR} 2006.173.11:24:29.93#abcon#[5=S1D000X0/0*\r\n] 2006.173.11:24:33.26$setupk4/"tpicd 2006.173.11:24:33.26$setupk4/echo=off 2006.173.11:24:33.26$setupk4/xlog=off 2006.173.11:24:33.26:!2006.173.11:32:19 2006.173.11:24:53.14#trakl#Source acquired 2006.173.11:24:53.14#flagr#flagr/antenna,acquired 2006.173.11:32:19.00:preob 2006.173.11:32:19.13/onsource/TRACKING 2006.173.11:32:19.13:!2006.173.11:32:29 2006.173.11:32:29.00:"tape 2006.173.11:32:29.00:"st=record 2006.173.11:32:29.00:data_valid=on 2006.173.11:32:29.00:midob 2006.173.11:32:29.13/onsource/TRACKING 2006.173.11:32:29.13/wx/22.40,1004.0,93 2006.173.11:32:29.29/cable/+6.5023E-03 2006.173.11:32:30.38/va/01,07,usb,yes,44,47 2006.173.11:32:30.38/va/02,06,usb,yes,44,44 2006.173.11:32:30.38/va/03,05,usb,yes,55,57 2006.173.11:32:30.38/va/04,06,usb,yes,45,47 2006.173.11:32:30.38/va/05,04,usb,yes,35,36 2006.173.11:32:30.38/va/06,03,usb,yes,49,49 2006.173.11:32:30.38/va/07,04,usb,yes,40,41 2006.173.11:32:30.38/va/08,04,usb,yes,34,41 2006.173.11:32:30.61/valo/01,524.99,yes,locked 2006.173.11:32:30.61/valo/02,534.99,yes,locked 2006.173.11:32:30.61/valo/03,564.99,yes,locked 2006.173.11:32:30.61/valo/04,624.99,yes,locked 2006.173.11:32:30.61/valo/05,734.99,yes,locked 2006.173.11:32:30.61/valo/06,814.99,yes,locked 2006.173.11:32:30.61/valo/07,864.99,yes,locked 2006.173.11:32:30.61/valo/08,884.99,yes,locked 2006.173.11:32:31.70/vb/01,04,usb,yes,32,30 2006.173.11:32:31.70/vb/02,04,usb,yes,35,34 2006.173.11:32:31.70/vb/03,04,usb,yes,31,35 2006.173.11:32:31.70/vb/04,04,usb,yes,36,35 2006.173.11:32:31.70/vb/05,04,usb,yes,28,31 2006.173.11:32:31.70/vb/06,04,usb,yes,33,29 2006.173.11:32:31.70/vb/07,04,usb,yes,33,33 2006.173.11:32:31.70/vb/08,04,usb,yes,30,34 2006.173.11:32:31.94/vblo/01,629.99,yes,locked 2006.173.11:32:31.94/vblo/02,634.99,yes,locked 2006.173.11:32:31.94/vblo/03,649.99,yes,locked 2006.173.11:32:31.94/vblo/04,679.99,yes,locked 2006.173.11:32:31.94/vblo/05,709.99,yes,locked 2006.173.11:32:31.94/vblo/06,719.99,yes,locked 2006.173.11:32:31.94/vblo/07,734.99,yes,locked 2006.173.11:32:31.94/vblo/08,744.99,yes,locked 2006.173.11:32:32.09/vabw/8 2006.173.11:32:32.24/vbbw/8 2006.173.11:32:32.40/xfe/off,on,14.7 2006.173.11:32:32.79/ifatt/23,28,28,28 2006.173.11:32:33.08/fmout-gps/S +3.97E-07 2006.173.11:32:33.12:!2006.173.11:33:09 2006.173.11:33:09.00:data_valid=off 2006.173.11:33:09.00:"et 2006.173.11:33:09.00:!+3s 2006.173.11:33:12.01:"tape 2006.173.11:33:12.01:postob 2006.173.11:33:12.20/cable/+6.5029E-03 2006.173.11:33:12.20/wx/22.39,1004.1,93 2006.173.11:33:13.08/fmout-gps/S +3.97E-07 2006.173.11:33:13.08:scan_name=173-1134,jd0606,100 2006.173.11:33:13.08:source=1334-127,133739.78,-125724.7,2000.0,cw 2006.173.11:33:14.14#flagr#flagr/antenna,new-source 2006.173.11:33:14.14:checkk5 2006.173.11:33:14.51/chk_autoobs//k5ts1/ autoobs is running! 2006.173.11:33:14.90/chk_autoobs//k5ts2/ autoobs is running! 2006.173.11:33:15.32/chk_autoobs//k5ts3/ autoobs is running! 2006.173.11:33:15.73/chk_autoobs//k5ts4/ autoobs is running! 2006.173.11:33:16.12/chk_obsdata//k5ts1/T1731132??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.173.11:33:16.54/chk_obsdata//k5ts2/T1731132??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.173.11:33:16.95/chk_obsdata//k5ts3/T1731132??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.173.11:33:17.35/chk_obsdata//k5ts4/T1731132??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.173.11:33:18.09/k5log//k5ts1_log_newline 2006.173.11:33:18.81/k5log//k5ts2_log_newline 2006.173.11:33:19.53/k5log//k5ts3_log_newline 2006.173.11:33:20.25/k5log//k5ts4_log_newline 2006.173.11:33:20.28/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.11:33:20.28:setupk4=1 2006.173.11:33:20.28$setupk4/echo=on 2006.173.11:33:20.28$setupk4/pcalon 2006.173.11:33:20.28$pcalon/"no phase cal control is implemented here 2006.173.11:33:20.28$setupk4/"tpicd=stop 2006.173.11:33:20.28$setupk4/"rec=synch_on 2006.173.11:33:20.28$setupk4/"rec_mode=128 2006.173.11:33:20.28$setupk4/!* 2006.173.11:33:20.28$setupk4/recpk4 2006.173.11:33:20.28$recpk4/recpatch= 2006.173.11:33:20.28$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.11:33:20.28$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.11:33:20.28$setupk4/vck44 2006.173.11:33:20.28$vck44/valo=1,524.99 2006.173.11:33:20.28#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.11:33:20.28#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.11:33:20.28#ibcon#ireg 17 cls_cnt 0 2006.173.11:33:20.28#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.11:33:20.28#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.11:33:20.28#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.11:33:20.28#ibcon#enter wrdev, iclass 38, count 0 2006.173.11:33:20.28#ibcon#first serial, iclass 38, count 0 2006.173.11:33:20.28#ibcon#enter sib2, iclass 38, count 0 2006.173.11:33:20.28#ibcon#flushed, iclass 38, count 0 2006.173.11:33:20.28#ibcon#about to write, iclass 38, count 0 2006.173.11:33:20.28#ibcon#wrote, iclass 38, count 0 2006.173.11:33:20.28#ibcon#about to read 3, iclass 38, count 0 2006.173.11:33:20.30#ibcon#read 3, iclass 38, count 0 2006.173.11:33:20.30#ibcon#about to read 4, iclass 38, count 0 2006.173.11:33:20.30#ibcon#read 4, iclass 38, count 0 2006.173.11:33:20.30#ibcon#about to read 5, iclass 38, count 0 2006.173.11:33:20.30#ibcon#read 5, iclass 38, count 0 2006.173.11:33:20.30#ibcon#about to read 6, iclass 38, count 0 2006.173.11:33:20.30#ibcon#read 6, iclass 38, count 0 2006.173.11:33:20.30#ibcon#end of sib2, iclass 38, count 0 2006.173.11:33:20.30#ibcon#*mode == 0, iclass 38, count 0 2006.173.11:33:20.30#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.11:33:20.30#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.11:33:20.30#ibcon#*before write, iclass 38, count 0 2006.173.11:33:20.30#ibcon#enter sib2, iclass 38, count 0 2006.173.11:33:20.30#ibcon#flushed, iclass 38, count 0 2006.173.11:33:20.30#ibcon#about to write, iclass 38, count 0 2006.173.11:33:20.30#ibcon#wrote, iclass 38, count 0 2006.173.11:33:20.30#ibcon#about to read 3, iclass 38, count 0 2006.173.11:33:20.35#ibcon#read 3, iclass 38, count 0 2006.173.11:33:20.35#ibcon#about to read 4, iclass 38, count 0 2006.173.11:33:20.35#ibcon#read 4, iclass 38, count 0 2006.173.11:33:20.35#ibcon#about to read 5, iclass 38, count 0 2006.173.11:33:20.35#ibcon#read 5, iclass 38, count 0 2006.173.11:33:20.35#ibcon#about to read 6, iclass 38, count 0 2006.173.11:33:20.35#ibcon#read 6, iclass 38, count 0 2006.173.11:33:20.35#ibcon#end of sib2, iclass 38, count 0 2006.173.11:33:20.35#ibcon#*after write, iclass 38, count 0 2006.173.11:33:20.35#ibcon#*before return 0, iclass 38, count 0 2006.173.11:33:20.35#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.11:33:20.35#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.11:33:20.35#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.11:33:20.35#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.11:33:20.35$vck44/va=1,7 2006.173.11:33:20.35#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.11:33:20.35#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.11:33:20.35#ibcon#ireg 11 cls_cnt 2 2006.173.11:33:20.35#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.11:33:20.35#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.11:33:20.35#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.11:33:20.35#ibcon#enter wrdev, iclass 40, count 2 2006.173.11:33:20.35#ibcon#first serial, iclass 40, count 2 2006.173.11:33:20.35#ibcon#enter sib2, iclass 40, count 2 2006.173.11:33:20.35#ibcon#flushed, iclass 40, count 2 2006.173.11:33:20.35#ibcon#about to write, iclass 40, count 2 2006.173.11:33:20.35#ibcon#wrote, iclass 40, count 2 2006.173.11:33:20.35#ibcon#about to read 3, iclass 40, count 2 2006.173.11:33:20.37#ibcon#read 3, iclass 40, count 2 2006.173.11:33:20.37#ibcon#about to read 4, iclass 40, count 2 2006.173.11:33:20.37#ibcon#read 4, iclass 40, count 2 2006.173.11:33:20.37#ibcon#about to read 5, iclass 40, count 2 2006.173.11:33:20.37#ibcon#read 5, iclass 40, count 2 2006.173.11:33:20.37#ibcon#about to read 6, iclass 40, count 2 2006.173.11:33:20.37#ibcon#read 6, iclass 40, count 2 2006.173.11:33:20.37#ibcon#end of sib2, iclass 40, count 2 2006.173.11:33:20.37#ibcon#*mode == 0, iclass 40, count 2 2006.173.11:33:20.37#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.11:33:20.37#ibcon#[25=AT01-07\r\n] 2006.173.11:33:20.37#ibcon#*before write, iclass 40, count 2 2006.173.11:33:20.37#ibcon#enter sib2, iclass 40, count 2 2006.173.11:33:20.37#ibcon#flushed, iclass 40, count 2 2006.173.11:33:20.37#ibcon#about to write, iclass 40, count 2 2006.173.11:33:20.37#ibcon#wrote, iclass 40, count 2 2006.173.11:33:20.37#ibcon#about to read 3, iclass 40, count 2 2006.173.11:33:20.40#ibcon#read 3, iclass 40, count 2 2006.173.11:33:20.40#ibcon#about to read 4, iclass 40, count 2 2006.173.11:33:20.40#ibcon#read 4, iclass 40, count 2 2006.173.11:33:20.40#ibcon#about to read 5, iclass 40, count 2 2006.173.11:33:20.40#ibcon#read 5, iclass 40, count 2 2006.173.11:33:20.40#ibcon#about to read 6, iclass 40, count 2 2006.173.11:33:20.40#ibcon#read 6, iclass 40, count 2 2006.173.11:33:20.40#ibcon#end of sib2, iclass 40, count 2 2006.173.11:33:20.40#ibcon#*after write, iclass 40, count 2 2006.173.11:33:20.40#ibcon#*before return 0, iclass 40, count 2 2006.173.11:33:20.40#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.11:33:20.40#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.11:33:20.40#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.11:33:20.40#ibcon#ireg 7 cls_cnt 0 2006.173.11:33:20.40#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.11:33:20.52#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.11:33:20.52#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.11:33:20.52#ibcon#enter wrdev, iclass 40, count 0 2006.173.11:33:20.52#ibcon#first serial, iclass 40, count 0 2006.173.11:33:20.52#ibcon#enter sib2, iclass 40, count 0 2006.173.11:33:20.52#ibcon#flushed, iclass 40, count 0 2006.173.11:33:20.52#ibcon#about to write, iclass 40, count 0 2006.173.11:33:20.52#ibcon#wrote, iclass 40, count 0 2006.173.11:33:20.52#ibcon#about to read 3, iclass 40, count 0 2006.173.11:33:20.54#ibcon#read 3, iclass 40, count 0 2006.173.11:33:20.54#ibcon#about to read 4, iclass 40, count 0 2006.173.11:33:20.54#ibcon#read 4, iclass 40, count 0 2006.173.11:33:20.54#ibcon#about to read 5, iclass 40, count 0 2006.173.11:33:20.54#ibcon#read 5, iclass 40, count 0 2006.173.11:33:20.54#ibcon#about to read 6, iclass 40, count 0 2006.173.11:33:20.54#ibcon#read 6, iclass 40, count 0 2006.173.11:33:20.54#ibcon#end of sib2, iclass 40, count 0 2006.173.11:33:20.54#ibcon#*mode == 0, iclass 40, count 0 2006.173.11:33:20.54#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.11:33:20.54#ibcon#[25=USB\r\n] 2006.173.11:33:20.54#ibcon#*before write, iclass 40, count 0 2006.173.11:33:20.54#ibcon#enter sib2, iclass 40, count 0 2006.173.11:33:20.54#ibcon#flushed, iclass 40, count 0 2006.173.11:33:20.54#ibcon#about to write, iclass 40, count 0 2006.173.11:33:20.54#ibcon#wrote, iclass 40, count 0 2006.173.11:33:20.54#ibcon#about to read 3, iclass 40, count 0 2006.173.11:33:20.57#ibcon#read 3, iclass 40, count 0 2006.173.11:33:20.57#ibcon#about to read 4, iclass 40, count 0 2006.173.11:33:20.57#ibcon#read 4, iclass 40, count 0 2006.173.11:33:20.57#ibcon#about to read 5, iclass 40, count 0 2006.173.11:33:20.57#ibcon#read 5, iclass 40, count 0 2006.173.11:33:20.57#ibcon#about to read 6, iclass 40, count 0 2006.173.11:33:20.57#ibcon#read 6, iclass 40, count 0 2006.173.11:33:20.57#ibcon#end of sib2, iclass 40, count 0 2006.173.11:33:20.57#ibcon#*after write, iclass 40, count 0 2006.173.11:33:20.57#ibcon#*before return 0, iclass 40, count 0 2006.173.11:33:20.57#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.11:33:20.57#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.11:33:20.57#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.11:33:20.57#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.11:33:20.57$vck44/valo=2,534.99 2006.173.11:33:20.57#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.11:33:20.57#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.11:33:20.57#ibcon#ireg 17 cls_cnt 0 2006.173.11:33:20.57#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.11:33:20.57#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.11:33:20.57#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.11:33:20.57#ibcon#enter wrdev, iclass 4, count 0 2006.173.11:33:20.57#ibcon#first serial, iclass 4, count 0 2006.173.11:33:20.57#ibcon#enter sib2, iclass 4, count 0 2006.173.11:33:20.57#ibcon#flushed, iclass 4, count 0 2006.173.11:33:20.57#ibcon#about to write, iclass 4, count 0 2006.173.11:33:20.57#ibcon#wrote, iclass 4, count 0 2006.173.11:33:20.57#ibcon#about to read 3, iclass 4, count 0 2006.173.11:33:20.59#ibcon#read 3, iclass 4, count 0 2006.173.11:33:20.59#ibcon#about to read 4, iclass 4, count 0 2006.173.11:33:20.59#ibcon#read 4, iclass 4, count 0 2006.173.11:33:20.59#ibcon#about to read 5, iclass 4, count 0 2006.173.11:33:20.59#ibcon#read 5, iclass 4, count 0 2006.173.11:33:20.59#ibcon#about to read 6, iclass 4, count 0 2006.173.11:33:20.59#ibcon#read 6, iclass 4, count 0 2006.173.11:33:20.59#ibcon#end of sib2, iclass 4, count 0 2006.173.11:33:20.59#ibcon#*mode == 0, iclass 4, count 0 2006.173.11:33:20.59#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.11:33:20.59#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.11:33:20.59#ibcon#*before write, iclass 4, count 0 2006.173.11:33:20.59#ibcon#enter sib2, iclass 4, count 0 2006.173.11:33:20.59#ibcon#flushed, iclass 4, count 0 2006.173.11:33:20.59#ibcon#about to write, iclass 4, count 0 2006.173.11:33:20.59#ibcon#wrote, iclass 4, count 0 2006.173.11:33:20.59#ibcon#about to read 3, iclass 4, count 0 2006.173.11:33:20.63#ibcon#read 3, iclass 4, count 0 2006.173.11:33:20.63#ibcon#about to read 4, iclass 4, count 0 2006.173.11:33:20.63#ibcon#read 4, iclass 4, count 0 2006.173.11:33:20.63#ibcon#about to read 5, iclass 4, count 0 2006.173.11:33:20.63#ibcon#read 5, iclass 4, count 0 2006.173.11:33:20.63#ibcon#about to read 6, iclass 4, count 0 2006.173.11:33:20.63#ibcon#read 6, iclass 4, count 0 2006.173.11:33:20.63#ibcon#end of sib2, iclass 4, count 0 2006.173.11:33:20.63#ibcon#*after write, iclass 4, count 0 2006.173.11:33:20.63#ibcon#*before return 0, iclass 4, count 0 2006.173.11:33:20.63#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.11:33:20.63#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.11:33:20.63#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.11:33:20.63#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.11:33:20.63$vck44/va=2,6 2006.173.11:33:20.63#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.11:33:20.63#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.11:33:20.63#ibcon#ireg 11 cls_cnt 2 2006.173.11:33:20.63#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.11:33:20.69#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.11:33:20.69#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.11:33:20.69#ibcon#enter wrdev, iclass 6, count 2 2006.173.11:33:20.69#ibcon#first serial, iclass 6, count 2 2006.173.11:33:20.69#ibcon#enter sib2, iclass 6, count 2 2006.173.11:33:20.69#ibcon#flushed, iclass 6, count 2 2006.173.11:33:20.69#ibcon#about to write, iclass 6, count 2 2006.173.11:33:20.69#ibcon#wrote, iclass 6, count 2 2006.173.11:33:20.69#ibcon#about to read 3, iclass 6, count 2 2006.173.11:33:20.71#ibcon#read 3, iclass 6, count 2 2006.173.11:33:20.71#ibcon#about to read 4, iclass 6, count 2 2006.173.11:33:20.71#ibcon#read 4, iclass 6, count 2 2006.173.11:33:20.71#ibcon#about to read 5, iclass 6, count 2 2006.173.11:33:20.71#ibcon#read 5, iclass 6, count 2 2006.173.11:33:20.71#ibcon#about to read 6, iclass 6, count 2 2006.173.11:33:20.71#ibcon#read 6, iclass 6, count 2 2006.173.11:33:20.71#ibcon#end of sib2, iclass 6, count 2 2006.173.11:33:20.71#ibcon#*mode == 0, iclass 6, count 2 2006.173.11:33:20.71#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.11:33:20.71#ibcon#[25=AT02-06\r\n] 2006.173.11:33:20.71#ibcon#*before write, iclass 6, count 2 2006.173.11:33:20.71#ibcon#enter sib2, iclass 6, count 2 2006.173.11:33:20.71#ibcon#flushed, iclass 6, count 2 2006.173.11:33:20.71#ibcon#about to write, iclass 6, count 2 2006.173.11:33:20.71#ibcon#wrote, iclass 6, count 2 2006.173.11:33:20.71#ibcon#about to read 3, iclass 6, count 2 2006.173.11:33:20.74#ibcon#read 3, iclass 6, count 2 2006.173.11:33:20.74#ibcon#about to read 4, iclass 6, count 2 2006.173.11:33:20.74#ibcon#read 4, iclass 6, count 2 2006.173.11:33:20.74#ibcon#about to read 5, iclass 6, count 2 2006.173.11:33:20.74#ibcon#read 5, iclass 6, count 2 2006.173.11:33:20.74#ibcon#about to read 6, iclass 6, count 2 2006.173.11:33:20.74#ibcon#read 6, iclass 6, count 2 2006.173.11:33:20.74#ibcon#end of sib2, iclass 6, count 2 2006.173.11:33:20.74#ibcon#*after write, iclass 6, count 2 2006.173.11:33:20.74#ibcon#*before return 0, iclass 6, count 2 2006.173.11:33:20.74#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.11:33:20.74#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.11:33:20.74#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.11:33:20.74#ibcon#ireg 7 cls_cnt 0 2006.173.11:33:20.74#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.11:33:20.86#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.11:33:20.86#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.11:33:20.86#ibcon#enter wrdev, iclass 6, count 0 2006.173.11:33:20.86#ibcon#first serial, iclass 6, count 0 2006.173.11:33:20.86#ibcon#enter sib2, iclass 6, count 0 2006.173.11:33:20.86#ibcon#flushed, iclass 6, count 0 2006.173.11:33:20.86#ibcon#about to write, iclass 6, count 0 2006.173.11:33:20.86#ibcon#wrote, iclass 6, count 0 2006.173.11:33:20.86#ibcon#about to read 3, iclass 6, count 0 2006.173.11:33:20.88#ibcon#read 3, iclass 6, count 0 2006.173.11:33:20.88#ibcon#about to read 4, iclass 6, count 0 2006.173.11:33:20.88#ibcon#read 4, iclass 6, count 0 2006.173.11:33:20.88#ibcon#about to read 5, iclass 6, count 0 2006.173.11:33:20.88#ibcon#read 5, iclass 6, count 0 2006.173.11:33:20.88#ibcon#about to read 6, iclass 6, count 0 2006.173.11:33:20.88#ibcon#read 6, iclass 6, count 0 2006.173.11:33:20.88#ibcon#end of sib2, iclass 6, count 0 2006.173.11:33:20.88#ibcon#*mode == 0, iclass 6, count 0 2006.173.11:33:20.88#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.11:33:20.88#ibcon#[25=USB\r\n] 2006.173.11:33:20.88#ibcon#*before write, iclass 6, count 0 2006.173.11:33:20.88#ibcon#enter sib2, iclass 6, count 0 2006.173.11:33:20.88#ibcon#flushed, iclass 6, count 0 2006.173.11:33:20.88#ibcon#about to write, iclass 6, count 0 2006.173.11:33:20.88#ibcon#wrote, iclass 6, count 0 2006.173.11:33:20.88#ibcon#about to read 3, iclass 6, count 0 2006.173.11:33:20.91#ibcon#read 3, iclass 6, count 0 2006.173.11:33:20.91#ibcon#about to read 4, iclass 6, count 0 2006.173.11:33:20.91#ibcon#read 4, iclass 6, count 0 2006.173.11:33:20.91#ibcon#about to read 5, iclass 6, count 0 2006.173.11:33:20.91#ibcon#read 5, iclass 6, count 0 2006.173.11:33:20.91#ibcon#about to read 6, iclass 6, count 0 2006.173.11:33:20.91#ibcon#read 6, iclass 6, count 0 2006.173.11:33:20.91#ibcon#end of sib2, iclass 6, count 0 2006.173.11:33:20.91#ibcon#*after write, iclass 6, count 0 2006.173.11:33:20.91#ibcon#*before return 0, iclass 6, count 0 2006.173.11:33:20.91#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.11:33:20.91#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.11:33:20.91#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.11:33:20.91#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.11:33:20.91$vck44/valo=3,564.99 2006.173.11:33:20.91#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.11:33:20.91#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.11:33:20.91#ibcon#ireg 17 cls_cnt 0 2006.173.11:33:20.91#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.11:33:20.91#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.11:33:20.91#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.11:33:20.91#ibcon#enter wrdev, iclass 10, count 0 2006.173.11:33:20.91#ibcon#first serial, iclass 10, count 0 2006.173.11:33:20.91#ibcon#enter sib2, iclass 10, count 0 2006.173.11:33:20.91#ibcon#flushed, iclass 10, count 0 2006.173.11:33:20.91#ibcon#about to write, iclass 10, count 0 2006.173.11:33:20.91#ibcon#wrote, iclass 10, count 0 2006.173.11:33:20.91#ibcon#about to read 3, iclass 10, count 0 2006.173.11:33:20.93#ibcon#read 3, iclass 10, count 0 2006.173.11:33:20.93#ibcon#about to read 4, iclass 10, count 0 2006.173.11:33:20.93#ibcon#read 4, iclass 10, count 0 2006.173.11:33:20.93#ibcon#about to read 5, iclass 10, count 0 2006.173.11:33:20.93#ibcon#read 5, iclass 10, count 0 2006.173.11:33:20.93#ibcon#about to read 6, iclass 10, count 0 2006.173.11:33:20.93#ibcon#read 6, iclass 10, count 0 2006.173.11:33:20.93#ibcon#end of sib2, iclass 10, count 0 2006.173.11:33:20.93#ibcon#*mode == 0, iclass 10, count 0 2006.173.11:33:20.93#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.11:33:20.93#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.11:33:20.93#ibcon#*before write, iclass 10, count 0 2006.173.11:33:20.93#ibcon#enter sib2, iclass 10, count 0 2006.173.11:33:20.93#ibcon#flushed, iclass 10, count 0 2006.173.11:33:20.93#ibcon#about to write, iclass 10, count 0 2006.173.11:33:20.93#ibcon#wrote, iclass 10, count 0 2006.173.11:33:20.93#ibcon#about to read 3, iclass 10, count 0 2006.173.11:33:20.97#ibcon#read 3, iclass 10, count 0 2006.173.11:33:20.97#ibcon#about to read 4, iclass 10, count 0 2006.173.11:33:20.97#ibcon#read 4, iclass 10, count 0 2006.173.11:33:20.97#ibcon#about to read 5, iclass 10, count 0 2006.173.11:33:20.97#ibcon#read 5, iclass 10, count 0 2006.173.11:33:20.97#ibcon#about to read 6, iclass 10, count 0 2006.173.11:33:20.97#ibcon#read 6, iclass 10, count 0 2006.173.11:33:20.97#ibcon#end of sib2, iclass 10, count 0 2006.173.11:33:20.97#ibcon#*after write, iclass 10, count 0 2006.173.11:33:20.97#ibcon#*before return 0, iclass 10, count 0 2006.173.11:33:20.97#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.11:33:20.97#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.11:33:20.97#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.11:33:20.97#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.11:33:20.97$vck44/va=3,5 2006.173.11:33:20.97#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.11:33:20.97#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.11:33:20.97#ibcon#ireg 11 cls_cnt 2 2006.173.11:33:20.97#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.11:33:21.03#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.11:33:21.03#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.11:33:21.03#ibcon#enter wrdev, iclass 12, count 2 2006.173.11:33:21.03#ibcon#first serial, iclass 12, count 2 2006.173.11:33:21.03#ibcon#enter sib2, iclass 12, count 2 2006.173.11:33:21.03#ibcon#flushed, iclass 12, count 2 2006.173.11:33:21.03#ibcon#about to write, iclass 12, count 2 2006.173.11:33:21.03#ibcon#wrote, iclass 12, count 2 2006.173.11:33:21.03#ibcon#about to read 3, iclass 12, count 2 2006.173.11:33:21.05#ibcon#read 3, iclass 12, count 2 2006.173.11:33:21.05#ibcon#about to read 4, iclass 12, count 2 2006.173.11:33:21.05#ibcon#read 4, iclass 12, count 2 2006.173.11:33:21.05#ibcon#about to read 5, iclass 12, count 2 2006.173.11:33:21.05#ibcon#read 5, iclass 12, count 2 2006.173.11:33:21.05#ibcon#about to read 6, iclass 12, count 2 2006.173.11:33:21.05#ibcon#read 6, iclass 12, count 2 2006.173.11:33:21.05#ibcon#end of sib2, iclass 12, count 2 2006.173.11:33:21.05#ibcon#*mode == 0, iclass 12, count 2 2006.173.11:33:21.05#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.11:33:21.05#ibcon#[25=AT03-05\r\n] 2006.173.11:33:21.05#ibcon#*before write, iclass 12, count 2 2006.173.11:33:21.05#ibcon#enter sib2, iclass 12, count 2 2006.173.11:33:21.05#ibcon#flushed, iclass 12, count 2 2006.173.11:33:21.05#ibcon#about to write, iclass 12, count 2 2006.173.11:33:21.05#ibcon#wrote, iclass 12, count 2 2006.173.11:33:21.05#ibcon#about to read 3, iclass 12, count 2 2006.173.11:33:21.08#ibcon#read 3, iclass 12, count 2 2006.173.11:33:21.08#ibcon#about to read 4, iclass 12, count 2 2006.173.11:33:21.08#ibcon#read 4, iclass 12, count 2 2006.173.11:33:21.08#ibcon#about to read 5, iclass 12, count 2 2006.173.11:33:21.08#ibcon#read 5, iclass 12, count 2 2006.173.11:33:21.08#ibcon#about to read 6, iclass 12, count 2 2006.173.11:33:21.08#ibcon#read 6, iclass 12, count 2 2006.173.11:33:21.08#ibcon#end of sib2, iclass 12, count 2 2006.173.11:33:21.08#ibcon#*after write, iclass 12, count 2 2006.173.11:33:21.08#ibcon#*before return 0, iclass 12, count 2 2006.173.11:33:21.08#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.11:33:21.08#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.11:33:21.08#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.11:33:21.08#ibcon#ireg 7 cls_cnt 0 2006.173.11:33:21.08#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.11:33:21.20#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.11:33:21.20#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.11:33:21.20#ibcon#enter wrdev, iclass 12, count 0 2006.173.11:33:21.20#ibcon#first serial, iclass 12, count 0 2006.173.11:33:21.20#ibcon#enter sib2, iclass 12, count 0 2006.173.11:33:21.20#ibcon#flushed, iclass 12, count 0 2006.173.11:33:21.20#ibcon#about to write, iclass 12, count 0 2006.173.11:33:21.20#ibcon#wrote, iclass 12, count 0 2006.173.11:33:21.20#ibcon#about to read 3, iclass 12, count 0 2006.173.11:33:21.22#ibcon#read 3, iclass 12, count 0 2006.173.11:33:21.22#ibcon#about to read 4, iclass 12, count 0 2006.173.11:33:21.22#ibcon#read 4, iclass 12, count 0 2006.173.11:33:21.22#ibcon#about to read 5, iclass 12, count 0 2006.173.11:33:21.22#ibcon#read 5, iclass 12, count 0 2006.173.11:33:21.22#ibcon#about to read 6, iclass 12, count 0 2006.173.11:33:21.22#ibcon#read 6, iclass 12, count 0 2006.173.11:33:21.22#ibcon#end of sib2, iclass 12, count 0 2006.173.11:33:21.22#ibcon#*mode == 0, iclass 12, count 0 2006.173.11:33:21.22#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.11:33:21.22#ibcon#[25=USB\r\n] 2006.173.11:33:21.22#ibcon#*before write, iclass 12, count 0 2006.173.11:33:21.22#ibcon#enter sib2, iclass 12, count 0 2006.173.11:33:21.22#ibcon#flushed, iclass 12, count 0 2006.173.11:33:21.22#ibcon#about to write, iclass 12, count 0 2006.173.11:33:21.22#ibcon#wrote, iclass 12, count 0 2006.173.11:33:21.22#ibcon#about to read 3, iclass 12, count 0 2006.173.11:33:21.25#ibcon#read 3, iclass 12, count 0 2006.173.11:33:21.25#ibcon#about to read 4, iclass 12, count 0 2006.173.11:33:21.25#ibcon#read 4, iclass 12, count 0 2006.173.11:33:21.25#ibcon#about to read 5, iclass 12, count 0 2006.173.11:33:21.25#ibcon#read 5, iclass 12, count 0 2006.173.11:33:21.25#ibcon#about to read 6, iclass 12, count 0 2006.173.11:33:21.25#ibcon#read 6, iclass 12, count 0 2006.173.11:33:21.25#ibcon#end of sib2, iclass 12, count 0 2006.173.11:33:21.25#ibcon#*after write, iclass 12, count 0 2006.173.11:33:21.25#ibcon#*before return 0, iclass 12, count 0 2006.173.11:33:21.25#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.11:33:21.25#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.11:33:21.25#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.11:33:21.25#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.11:33:21.25$vck44/valo=4,624.99 2006.173.11:33:21.25#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.11:33:21.25#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.11:33:21.25#ibcon#ireg 17 cls_cnt 0 2006.173.11:33:21.25#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.11:33:21.25#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.11:33:21.25#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.11:33:21.25#ibcon#enter wrdev, iclass 14, count 0 2006.173.11:33:21.25#ibcon#first serial, iclass 14, count 0 2006.173.11:33:21.25#ibcon#enter sib2, iclass 14, count 0 2006.173.11:33:21.25#ibcon#flushed, iclass 14, count 0 2006.173.11:33:21.25#ibcon#about to write, iclass 14, count 0 2006.173.11:33:21.25#ibcon#wrote, iclass 14, count 0 2006.173.11:33:21.25#ibcon#about to read 3, iclass 14, count 0 2006.173.11:33:21.27#ibcon#read 3, iclass 14, count 0 2006.173.11:33:21.27#ibcon#about to read 4, iclass 14, count 0 2006.173.11:33:21.27#ibcon#read 4, iclass 14, count 0 2006.173.11:33:21.27#ibcon#about to read 5, iclass 14, count 0 2006.173.11:33:21.27#ibcon#read 5, iclass 14, count 0 2006.173.11:33:21.27#ibcon#about to read 6, iclass 14, count 0 2006.173.11:33:21.27#ibcon#read 6, iclass 14, count 0 2006.173.11:33:21.27#ibcon#end of sib2, iclass 14, count 0 2006.173.11:33:21.27#ibcon#*mode == 0, iclass 14, count 0 2006.173.11:33:21.27#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.11:33:21.27#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.11:33:21.27#ibcon#*before write, iclass 14, count 0 2006.173.11:33:21.27#ibcon#enter sib2, iclass 14, count 0 2006.173.11:33:21.27#ibcon#flushed, iclass 14, count 0 2006.173.11:33:21.27#ibcon#about to write, iclass 14, count 0 2006.173.11:33:21.27#ibcon#wrote, iclass 14, count 0 2006.173.11:33:21.27#ibcon#about to read 3, iclass 14, count 0 2006.173.11:33:21.31#ibcon#read 3, iclass 14, count 0 2006.173.11:33:21.31#ibcon#about to read 4, iclass 14, count 0 2006.173.11:33:21.31#ibcon#read 4, iclass 14, count 0 2006.173.11:33:21.31#ibcon#about to read 5, iclass 14, count 0 2006.173.11:33:21.31#ibcon#read 5, iclass 14, count 0 2006.173.11:33:21.31#ibcon#about to read 6, iclass 14, count 0 2006.173.11:33:21.31#ibcon#read 6, iclass 14, count 0 2006.173.11:33:21.31#ibcon#end of sib2, iclass 14, count 0 2006.173.11:33:21.31#ibcon#*after write, iclass 14, count 0 2006.173.11:33:21.31#ibcon#*before return 0, iclass 14, count 0 2006.173.11:33:21.31#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.11:33:21.31#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.11:33:21.31#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.11:33:21.31#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.11:33:21.31$vck44/va=4,6 2006.173.11:33:21.31#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.11:33:21.31#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.11:33:21.31#ibcon#ireg 11 cls_cnt 2 2006.173.11:33:21.31#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.11:33:21.37#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.11:33:21.37#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.11:33:21.37#ibcon#enter wrdev, iclass 16, count 2 2006.173.11:33:21.37#ibcon#first serial, iclass 16, count 2 2006.173.11:33:21.37#ibcon#enter sib2, iclass 16, count 2 2006.173.11:33:21.37#ibcon#flushed, iclass 16, count 2 2006.173.11:33:21.37#ibcon#about to write, iclass 16, count 2 2006.173.11:33:21.37#ibcon#wrote, iclass 16, count 2 2006.173.11:33:21.37#ibcon#about to read 3, iclass 16, count 2 2006.173.11:33:21.39#ibcon#read 3, iclass 16, count 2 2006.173.11:33:21.39#ibcon#about to read 4, iclass 16, count 2 2006.173.11:33:21.39#ibcon#read 4, iclass 16, count 2 2006.173.11:33:21.39#ibcon#about to read 5, iclass 16, count 2 2006.173.11:33:21.39#ibcon#read 5, iclass 16, count 2 2006.173.11:33:21.39#ibcon#about to read 6, iclass 16, count 2 2006.173.11:33:21.39#ibcon#read 6, iclass 16, count 2 2006.173.11:33:21.39#ibcon#end of sib2, iclass 16, count 2 2006.173.11:33:21.39#ibcon#*mode == 0, iclass 16, count 2 2006.173.11:33:21.39#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.11:33:21.39#ibcon#[25=AT04-06\r\n] 2006.173.11:33:21.39#ibcon#*before write, iclass 16, count 2 2006.173.11:33:21.39#ibcon#enter sib2, iclass 16, count 2 2006.173.11:33:21.39#ibcon#flushed, iclass 16, count 2 2006.173.11:33:21.39#ibcon#about to write, iclass 16, count 2 2006.173.11:33:21.39#ibcon#wrote, iclass 16, count 2 2006.173.11:33:21.39#ibcon#about to read 3, iclass 16, count 2 2006.173.11:33:21.42#ibcon#read 3, iclass 16, count 2 2006.173.11:33:21.42#ibcon#about to read 4, iclass 16, count 2 2006.173.11:33:21.42#ibcon#read 4, iclass 16, count 2 2006.173.11:33:21.42#ibcon#about to read 5, iclass 16, count 2 2006.173.11:33:21.42#ibcon#read 5, iclass 16, count 2 2006.173.11:33:21.42#ibcon#about to read 6, iclass 16, count 2 2006.173.11:33:21.42#ibcon#read 6, iclass 16, count 2 2006.173.11:33:21.42#ibcon#end of sib2, iclass 16, count 2 2006.173.11:33:21.42#ibcon#*after write, iclass 16, count 2 2006.173.11:33:21.42#ibcon#*before return 0, iclass 16, count 2 2006.173.11:33:21.42#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.11:33:21.42#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.11:33:21.42#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.11:33:21.42#ibcon#ireg 7 cls_cnt 0 2006.173.11:33:21.42#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.11:33:21.54#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.11:33:21.54#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.11:33:21.54#ibcon#enter wrdev, iclass 16, count 0 2006.173.11:33:21.54#ibcon#first serial, iclass 16, count 0 2006.173.11:33:21.54#ibcon#enter sib2, iclass 16, count 0 2006.173.11:33:21.54#ibcon#flushed, iclass 16, count 0 2006.173.11:33:21.54#ibcon#about to write, iclass 16, count 0 2006.173.11:33:21.54#ibcon#wrote, iclass 16, count 0 2006.173.11:33:21.54#ibcon#about to read 3, iclass 16, count 0 2006.173.11:33:21.56#ibcon#read 3, iclass 16, count 0 2006.173.11:33:21.56#ibcon#about to read 4, iclass 16, count 0 2006.173.11:33:21.56#ibcon#read 4, iclass 16, count 0 2006.173.11:33:21.56#ibcon#about to read 5, iclass 16, count 0 2006.173.11:33:21.56#ibcon#read 5, iclass 16, count 0 2006.173.11:33:21.56#ibcon#about to read 6, iclass 16, count 0 2006.173.11:33:21.56#ibcon#read 6, iclass 16, count 0 2006.173.11:33:21.56#ibcon#end of sib2, iclass 16, count 0 2006.173.11:33:21.56#ibcon#*mode == 0, iclass 16, count 0 2006.173.11:33:21.56#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.11:33:21.56#ibcon#[25=USB\r\n] 2006.173.11:33:21.56#ibcon#*before write, iclass 16, count 0 2006.173.11:33:21.56#ibcon#enter sib2, iclass 16, count 0 2006.173.11:33:21.56#ibcon#flushed, iclass 16, count 0 2006.173.11:33:21.56#ibcon#about to write, iclass 16, count 0 2006.173.11:33:21.56#ibcon#wrote, iclass 16, count 0 2006.173.11:33:21.56#ibcon#about to read 3, iclass 16, count 0 2006.173.11:33:21.59#ibcon#read 3, iclass 16, count 0 2006.173.11:33:21.59#ibcon#about to read 4, iclass 16, count 0 2006.173.11:33:21.59#ibcon#read 4, iclass 16, count 0 2006.173.11:33:21.59#ibcon#about to read 5, iclass 16, count 0 2006.173.11:33:21.59#ibcon#read 5, iclass 16, count 0 2006.173.11:33:21.59#ibcon#about to read 6, iclass 16, count 0 2006.173.11:33:21.59#ibcon#read 6, iclass 16, count 0 2006.173.11:33:21.59#ibcon#end of sib2, iclass 16, count 0 2006.173.11:33:21.59#ibcon#*after write, iclass 16, count 0 2006.173.11:33:21.59#ibcon#*before return 0, iclass 16, count 0 2006.173.11:33:21.59#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.11:33:21.59#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.11:33:21.59#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.11:33:21.59#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.11:33:21.59$vck44/valo=5,734.99 2006.173.11:33:21.59#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.11:33:21.59#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.11:33:21.59#ibcon#ireg 17 cls_cnt 0 2006.173.11:33:21.59#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.11:33:21.59#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.11:33:21.59#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.11:33:21.59#ibcon#enter wrdev, iclass 18, count 0 2006.173.11:33:21.59#ibcon#first serial, iclass 18, count 0 2006.173.11:33:21.59#ibcon#enter sib2, iclass 18, count 0 2006.173.11:33:21.59#ibcon#flushed, iclass 18, count 0 2006.173.11:33:21.59#ibcon#about to write, iclass 18, count 0 2006.173.11:33:21.59#ibcon#wrote, iclass 18, count 0 2006.173.11:33:21.59#ibcon#about to read 3, iclass 18, count 0 2006.173.11:33:21.61#ibcon#read 3, iclass 18, count 0 2006.173.11:33:21.61#ibcon#about to read 4, iclass 18, count 0 2006.173.11:33:21.61#ibcon#read 4, iclass 18, count 0 2006.173.11:33:21.61#ibcon#about to read 5, iclass 18, count 0 2006.173.11:33:21.61#ibcon#read 5, iclass 18, count 0 2006.173.11:33:21.61#ibcon#about to read 6, iclass 18, count 0 2006.173.11:33:21.61#ibcon#read 6, iclass 18, count 0 2006.173.11:33:21.61#ibcon#end of sib2, iclass 18, count 0 2006.173.11:33:21.61#ibcon#*mode == 0, iclass 18, count 0 2006.173.11:33:21.61#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.11:33:21.61#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.11:33:21.61#ibcon#*before write, iclass 18, count 0 2006.173.11:33:21.61#ibcon#enter sib2, iclass 18, count 0 2006.173.11:33:21.61#ibcon#flushed, iclass 18, count 0 2006.173.11:33:21.61#ibcon#about to write, iclass 18, count 0 2006.173.11:33:21.61#ibcon#wrote, iclass 18, count 0 2006.173.11:33:21.61#ibcon#about to read 3, iclass 18, count 0 2006.173.11:33:21.65#ibcon#read 3, iclass 18, count 0 2006.173.11:33:21.65#ibcon#about to read 4, iclass 18, count 0 2006.173.11:33:21.65#ibcon#read 4, iclass 18, count 0 2006.173.11:33:21.65#ibcon#about to read 5, iclass 18, count 0 2006.173.11:33:21.65#ibcon#read 5, iclass 18, count 0 2006.173.11:33:21.65#ibcon#about to read 6, iclass 18, count 0 2006.173.11:33:21.65#ibcon#read 6, iclass 18, count 0 2006.173.11:33:21.65#ibcon#end of sib2, iclass 18, count 0 2006.173.11:33:21.65#ibcon#*after write, iclass 18, count 0 2006.173.11:33:21.65#ibcon#*before return 0, iclass 18, count 0 2006.173.11:33:21.65#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.11:33:21.65#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.11:33:21.65#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.11:33:21.65#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.11:33:21.65$vck44/va=5,4 2006.173.11:33:21.65#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.11:33:21.65#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.11:33:21.65#ibcon#ireg 11 cls_cnt 2 2006.173.11:33:21.65#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.11:33:21.71#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.11:33:21.71#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.11:33:21.71#ibcon#enter wrdev, iclass 20, count 2 2006.173.11:33:21.71#ibcon#first serial, iclass 20, count 2 2006.173.11:33:21.71#ibcon#enter sib2, iclass 20, count 2 2006.173.11:33:21.71#ibcon#flushed, iclass 20, count 2 2006.173.11:33:21.71#ibcon#about to write, iclass 20, count 2 2006.173.11:33:21.71#ibcon#wrote, iclass 20, count 2 2006.173.11:33:21.71#ibcon#about to read 3, iclass 20, count 2 2006.173.11:33:21.73#ibcon#read 3, iclass 20, count 2 2006.173.11:33:21.73#ibcon#about to read 4, iclass 20, count 2 2006.173.11:33:21.73#ibcon#read 4, iclass 20, count 2 2006.173.11:33:21.73#ibcon#about to read 5, iclass 20, count 2 2006.173.11:33:21.73#ibcon#read 5, iclass 20, count 2 2006.173.11:33:21.73#ibcon#about to read 6, iclass 20, count 2 2006.173.11:33:21.73#ibcon#read 6, iclass 20, count 2 2006.173.11:33:21.73#ibcon#end of sib2, iclass 20, count 2 2006.173.11:33:21.73#ibcon#*mode == 0, iclass 20, count 2 2006.173.11:33:21.73#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.11:33:21.73#ibcon#[25=AT05-04\r\n] 2006.173.11:33:21.73#ibcon#*before write, iclass 20, count 2 2006.173.11:33:21.73#ibcon#enter sib2, iclass 20, count 2 2006.173.11:33:21.73#ibcon#flushed, iclass 20, count 2 2006.173.11:33:21.73#ibcon#about to write, iclass 20, count 2 2006.173.11:33:21.73#ibcon#wrote, iclass 20, count 2 2006.173.11:33:21.73#ibcon#about to read 3, iclass 20, count 2 2006.173.11:33:21.76#ibcon#read 3, iclass 20, count 2 2006.173.11:33:21.76#ibcon#about to read 4, iclass 20, count 2 2006.173.11:33:21.76#ibcon#read 4, iclass 20, count 2 2006.173.11:33:21.76#ibcon#about to read 5, iclass 20, count 2 2006.173.11:33:21.76#ibcon#read 5, iclass 20, count 2 2006.173.11:33:21.76#ibcon#about to read 6, iclass 20, count 2 2006.173.11:33:21.76#ibcon#read 6, iclass 20, count 2 2006.173.11:33:21.76#ibcon#end of sib2, iclass 20, count 2 2006.173.11:33:21.76#ibcon#*after write, iclass 20, count 2 2006.173.11:33:21.76#ibcon#*before return 0, iclass 20, count 2 2006.173.11:33:21.76#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.11:33:21.76#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.11:33:21.76#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.11:33:21.76#ibcon#ireg 7 cls_cnt 0 2006.173.11:33:21.76#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.11:33:21.88#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.11:33:21.88#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.11:33:21.88#ibcon#enter wrdev, iclass 20, count 0 2006.173.11:33:21.88#ibcon#first serial, iclass 20, count 0 2006.173.11:33:21.88#ibcon#enter sib2, iclass 20, count 0 2006.173.11:33:21.88#ibcon#flushed, iclass 20, count 0 2006.173.11:33:21.88#ibcon#about to write, iclass 20, count 0 2006.173.11:33:21.88#ibcon#wrote, iclass 20, count 0 2006.173.11:33:21.88#ibcon#about to read 3, iclass 20, count 0 2006.173.11:33:21.90#ibcon#read 3, iclass 20, count 0 2006.173.11:33:21.90#ibcon#about to read 4, iclass 20, count 0 2006.173.11:33:21.90#ibcon#read 4, iclass 20, count 0 2006.173.11:33:21.90#ibcon#about to read 5, iclass 20, count 0 2006.173.11:33:21.90#ibcon#read 5, iclass 20, count 0 2006.173.11:33:21.90#ibcon#about to read 6, iclass 20, count 0 2006.173.11:33:21.90#ibcon#read 6, iclass 20, count 0 2006.173.11:33:21.90#ibcon#end of sib2, iclass 20, count 0 2006.173.11:33:21.90#ibcon#*mode == 0, iclass 20, count 0 2006.173.11:33:21.90#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.11:33:21.90#ibcon#[25=USB\r\n] 2006.173.11:33:21.90#ibcon#*before write, iclass 20, count 0 2006.173.11:33:21.90#ibcon#enter sib2, iclass 20, count 0 2006.173.11:33:21.90#ibcon#flushed, iclass 20, count 0 2006.173.11:33:21.90#ibcon#about to write, iclass 20, count 0 2006.173.11:33:21.90#ibcon#wrote, iclass 20, count 0 2006.173.11:33:21.90#ibcon#about to read 3, iclass 20, count 0 2006.173.11:33:21.93#ibcon#read 3, iclass 20, count 0 2006.173.11:33:21.93#ibcon#about to read 4, iclass 20, count 0 2006.173.11:33:21.93#ibcon#read 4, iclass 20, count 0 2006.173.11:33:21.93#ibcon#about to read 5, iclass 20, count 0 2006.173.11:33:21.93#ibcon#read 5, iclass 20, count 0 2006.173.11:33:21.93#ibcon#about to read 6, iclass 20, count 0 2006.173.11:33:21.93#ibcon#read 6, iclass 20, count 0 2006.173.11:33:21.93#ibcon#end of sib2, iclass 20, count 0 2006.173.11:33:21.93#ibcon#*after write, iclass 20, count 0 2006.173.11:33:21.93#ibcon#*before return 0, iclass 20, count 0 2006.173.11:33:21.93#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.11:33:21.93#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.11:33:21.93#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.11:33:21.93#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.11:33:21.93$vck44/valo=6,814.99 2006.173.11:33:21.93#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.11:33:21.93#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.11:33:21.93#ibcon#ireg 17 cls_cnt 0 2006.173.11:33:21.93#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.11:33:21.93#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.11:33:21.93#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.11:33:21.93#ibcon#enter wrdev, iclass 22, count 0 2006.173.11:33:21.93#ibcon#first serial, iclass 22, count 0 2006.173.11:33:21.93#ibcon#enter sib2, iclass 22, count 0 2006.173.11:33:21.93#ibcon#flushed, iclass 22, count 0 2006.173.11:33:21.93#ibcon#about to write, iclass 22, count 0 2006.173.11:33:21.93#ibcon#wrote, iclass 22, count 0 2006.173.11:33:21.93#ibcon#about to read 3, iclass 22, count 0 2006.173.11:33:21.95#ibcon#read 3, iclass 22, count 0 2006.173.11:33:21.95#ibcon#about to read 4, iclass 22, count 0 2006.173.11:33:21.95#ibcon#read 4, iclass 22, count 0 2006.173.11:33:21.95#ibcon#about to read 5, iclass 22, count 0 2006.173.11:33:21.95#ibcon#read 5, iclass 22, count 0 2006.173.11:33:21.95#ibcon#about to read 6, iclass 22, count 0 2006.173.11:33:21.95#ibcon#read 6, iclass 22, count 0 2006.173.11:33:21.95#ibcon#end of sib2, iclass 22, count 0 2006.173.11:33:21.95#ibcon#*mode == 0, iclass 22, count 0 2006.173.11:33:21.95#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.11:33:21.95#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.11:33:21.95#ibcon#*before write, iclass 22, count 0 2006.173.11:33:21.95#ibcon#enter sib2, iclass 22, count 0 2006.173.11:33:21.95#ibcon#flushed, iclass 22, count 0 2006.173.11:33:21.95#ibcon#about to write, iclass 22, count 0 2006.173.11:33:21.95#ibcon#wrote, iclass 22, count 0 2006.173.11:33:21.95#ibcon#about to read 3, iclass 22, count 0 2006.173.11:33:21.99#ibcon#read 3, iclass 22, count 0 2006.173.11:33:21.99#ibcon#about to read 4, iclass 22, count 0 2006.173.11:33:21.99#ibcon#read 4, iclass 22, count 0 2006.173.11:33:21.99#ibcon#about to read 5, iclass 22, count 0 2006.173.11:33:21.99#ibcon#read 5, iclass 22, count 0 2006.173.11:33:21.99#ibcon#about to read 6, iclass 22, count 0 2006.173.11:33:21.99#ibcon#read 6, iclass 22, count 0 2006.173.11:33:21.99#ibcon#end of sib2, iclass 22, count 0 2006.173.11:33:21.99#ibcon#*after write, iclass 22, count 0 2006.173.11:33:21.99#ibcon#*before return 0, iclass 22, count 0 2006.173.11:33:21.99#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.11:33:21.99#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.11:33:21.99#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.11:33:21.99#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.11:33:21.99$vck44/va=6,3 2006.173.11:33:21.99#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.11:33:21.99#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.11:33:21.99#ibcon#ireg 11 cls_cnt 2 2006.173.11:33:21.99#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.11:33:22.05#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.11:33:22.05#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.11:33:22.05#ibcon#enter wrdev, iclass 24, count 2 2006.173.11:33:22.05#ibcon#first serial, iclass 24, count 2 2006.173.11:33:22.05#ibcon#enter sib2, iclass 24, count 2 2006.173.11:33:22.05#ibcon#flushed, iclass 24, count 2 2006.173.11:33:22.05#ibcon#about to write, iclass 24, count 2 2006.173.11:33:22.05#ibcon#wrote, iclass 24, count 2 2006.173.11:33:22.05#ibcon#about to read 3, iclass 24, count 2 2006.173.11:33:22.07#ibcon#read 3, iclass 24, count 2 2006.173.11:33:22.07#ibcon#about to read 4, iclass 24, count 2 2006.173.11:33:22.07#ibcon#read 4, iclass 24, count 2 2006.173.11:33:22.07#ibcon#about to read 5, iclass 24, count 2 2006.173.11:33:22.07#ibcon#read 5, iclass 24, count 2 2006.173.11:33:22.07#ibcon#about to read 6, iclass 24, count 2 2006.173.11:33:22.07#ibcon#read 6, iclass 24, count 2 2006.173.11:33:22.07#ibcon#end of sib2, iclass 24, count 2 2006.173.11:33:22.07#ibcon#*mode == 0, iclass 24, count 2 2006.173.11:33:22.07#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.11:33:22.07#ibcon#[25=AT06-03\r\n] 2006.173.11:33:22.07#ibcon#*before write, iclass 24, count 2 2006.173.11:33:22.07#ibcon#enter sib2, iclass 24, count 2 2006.173.11:33:22.07#ibcon#flushed, iclass 24, count 2 2006.173.11:33:22.07#ibcon#about to write, iclass 24, count 2 2006.173.11:33:22.07#ibcon#wrote, iclass 24, count 2 2006.173.11:33:22.07#ibcon#about to read 3, iclass 24, count 2 2006.173.11:33:22.10#ibcon#read 3, iclass 24, count 2 2006.173.11:33:22.10#ibcon#about to read 4, iclass 24, count 2 2006.173.11:33:22.10#ibcon#read 4, iclass 24, count 2 2006.173.11:33:22.10#ibcon#about to read 5, iclass 24, count 2 2006.173.11:33:22.10#ibcon#read 5, iclass 24, count 2 2006.173.11:33:22.10#ibcon#about to read 6, iclass 24, count 2 2006.173.11:33:22.10#ibcon#read 6, iclass 24, count 2 2006.173.11:33:22.10#ibcon#end of sib2, iclass 24, count 2 2006.173.11:33:22.10#ibcon#*after write, iclass 24, count 2 2006.173.11:33:22.10#ibcon#*before return 0, iclass 24, count 2 2006.173.11:33:22.10#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.11:33:22.10#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.11:33:22.10#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.11:33:22.10#ibcon#ireg 7 cls_cnt 0 2006.173.11:33:22.10#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.11:33:22.22#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.11:33:22.22#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.11:33:22.22#ibcon#enter wrdev, iclass 24, count 0 2006.173.11:33:22.22#ibcon#first serial, iclass 24, count 0 2006.173.11:33:22.22#ibcon#enter sib2, iclass 24, count 0 2006.173.11:33:22.22#ibcon#flushed, iclass 24, count 0 2006.173.11:33:22.22#ibcon#about to write, iclass 24, count 0 2006.173.11:33:22.22#ibcon#wrote, iclass 24, count 0 2006.173.11:33:22.22#ibcon#about to read 3, iclass 24, count 0 2006.173.11:33:22.24#ibcon#read 3, iclass 24, count 0 2006.173.11:33:22.24#ibcon#about to read 4, iclass 24, count 0 2006.173.11:33:22.24#ibcon#read 4, iclass 24, count 0 2006.173.11:33:22.24#ibcon#about to read 5, iclass 24, count 0 2006.173.11:33:22.24#ibcon#read 5, iclass 24, count 0 2006.173.11:33:22.24#ibcon#about to read 6, iclass 24, count 0 2006.173.11:33:22.24#ibcon#read 6, iclass 24, count 0 2006.173.11:33:22.24#ibcon#end of sib2, iclass 24, count 0 2006.173.11:33:22.24#ibcon#*mode == 0, iclass 24, count 0 2006.173.11:33:22.24#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.11:33:22.24#ibcon#[25=USB\r\n] 2006.173.11:33:22.24#ibcon#*before write, iclass 24, count 0 2006.173.11:33:22.24#ibcon#enter sib2, iclass 24, count 0 2006.173.11:33:22.24#ibcon#flushed, iclass 24, count 0 2006.173.11:33:22.24#ibcon#about to write, iclass 24, count 0 2006.173.11:33:22.24#ibcon#wrote, iclass 24, count 0 2006.173.11:33:22.24#ibcon#about to read 3, iclass 24, count 0 2006.173.11:33:22.27#ibcon#read 3, iclass 24, count 0 2006.173.11:33:22.27#ibcon#about to read 4, iclass 24, count 0 2006.173.11:33:22.27#ibcon#read 4, iclass 24, count 0 2006.173.11:33:22.27#ibcon#about to read 5, iclass 24, count 0 2006.173.11:33:22.27#ibcon#read 5, iclass 24, count 0 2006.173.11:33:22.27#ibcon#about to read 6, iclass 24, count 0 2006.173.11:33:22.27#ibcon#read 6, iclass 24, count 0 2006.173.11:33:22.27#ibcon#end of sib2, iclass 24, count 0 2006.173.11:33:22.27#ibcon#*after write, iclass 24, count 0 2006.173.11:33:22.27#ibcon#*before return 0, iclass 24, count 0 2006.173.11:33:22.27#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.11:33:22.27#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.11:33:22.27#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.11:33:22.27#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.11:33:22.27$vck44/valo=7,864.99 2006.173.11:33:22.27#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.11:33:22.27#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.11:33:22.27#ibcon#ireg 17 cls_cnt 0 2006.173.11:33:22.27#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.11:33:22.27#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.11:33:22.27#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.11:33:22.27#ibcon#enter wrdev, iclass 26, count 0 2006.173.11:33:22.27#ibcon#first serial, iclass 26, count 0 2006.173.11:33:22.27#ibcon#enter sib2, iclass 26, count 0 2006.173.11:33:22.27#ibcon#flushed, iclass 26, count 0 2006.173.11:33:22.27#ibcon#about to write, iclass 26, count 0 2006.173.11:33:22.27#ibcon#wrote, iclass 26, count 0 2006.173.11:33:22.27#ibcon#about to read 3, iclass 26, count 0 2006.173.11:33:22.29#ibcon#read 3, iclass 26, count 0 2006.173.11:33:22.29#ibcon#about to read 4, iclass 26, count 0 2006.173.11:33:22.29#ibcon#read 4, iclass 26, count 0 2006.173.11:33:22.29#ibcon#about to read 5, iclass 26, count 0 2006.173.11:33:22.29#ibcon#read 5, iclass 26, count 0 2006.173.11:33:22.29#ibcon#about to read 6, iclass 26, count 0 2006.173.11:33:22.29#ibcon#read 6, iclass 26, count 0 2006.173.11:33:22.29#ibcon#end of sib2, iclass 26, count 0 2006.173.11:33:22.29#ibcon#*mode == 0, iclass 26, count 0 2006.173.11:33:22.29#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.11:33:22.29#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.11:33:22.29#ibcon#*before write, iclass 26, count 0 2006.173.11:33:22.29#ibcon#enter sib2, iclass 26, count 0 2006.173.11:33:22.29#ibcon#flushed, iclass 26, count 0 2006.173.11:33:22.29#ibcon#about to write, iclass 26, count 0 2006.173.11:33:22.29#ibcon#wrote, iclass 26, count 0 2006.173.11:33:22.29#ibcon#about to read 3, iclass 26, count 0 2006.173.11:33:22.33#ibcon#read 3, iclass 26, count 0 2006.173.11:33:22.33#ibcon#about to read 4, iclass 26, count 0 2006.173.11:33:22.33#ibcon#read 4, iclass 26, count 0 2006.173.11:33:22.33#ibcon#about to read 5, iclass 26, count 0 2006.173.11:33:22.33#ibcon#read 5, iclass 26, count 0 2006.173.11:33:22.33#ibcon#about to read 6, iclass 26, count 0 2006.173.11:33:22.33#ibcon#read 6, iclass 26, count 0 2006.173.11:33:22.33#ibcon#end of sib2, iclass 26, count 0 2006.173.11:33:22.33#ibcon#*after write, iclass 26, count 0 2006.173.11:33:22.33#ibcon#*before return 0, iclass 26, count 0 2006.173.11:33:22.33#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.11:33:22.33#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.11:33:22.33#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.11:33:22.33#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.11:33:22.33$vck44/va=7,4 2006.173.11:33:22.33#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.11:33:22.33#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.11:33:22.33#ibcon#ireg 11 cls_cnt 2 2006.173.11:33:22.33#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.11:33:22.39#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.11:33:22.39#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.11:33:22.39#ibcon#enter wrdev, iclass 28, count 2 2006.173.11:33:22.39#ibcon#first serial, iclass 28, count 2 2006.173.11:33:22.39#ibcon#enter sib2, iclass 28, count 2 2006.173.11:33:22.39#ibcon#flushed, iclass 28, count 2 2006.173.11:33:22.39#ibcon#about to write, iclass 28, count 2 2006.173.11:33:22.39#ibcon#wrote, iclass 28, count 2 2006.173.11:33:22.39#ibcon#about to read 3, iclass 28, count 2 2006.173.11:33:22.41#ibcon#read 3, iclass 28, count 2 2006.173.11:33:22.41#ibcon#about to read 4, iclass 28, count 2 2006.173.11:33:22.41#ibcon#read 4, iclass 28, count 2 2006.173.11:33:22.41#ibcon#about to read 5, iclass 28, count 2 2006.173.11:33:22.41#ibcon#read 5, iclass 28, count 2 2006.173.11:33:22.41#ibcon#about to read 6, iclass 28, count 2 2006.173.11:33:22.41#ibcon#read 6, iclass 28, count 2 2006.173.11:33:22.41#ibcon#end of sib2, iclass 28, count 2 2006.173.11:33:22.41#ibcon#*mode == 0, iclass 28, count 2 2006.173.11:33:22.41#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.11:33:22.41#ibcon#[25=AT07-04\r\n] 2006.173.11:33:22.41#ibcon#*before write, iclass 28, count 2 2006.173.11:33:22.41#ibcon#enter sib2, iclass 28, count 2 2006.173.11:33:22.41#ibcon#flushed, iclass 28, count 2 2006.173.11:33:22.41#ibcon#about to write, iclass 28, count 2 2006.173.11:33:22.41#ibcon#wrote, iclass 28, count 2 2006.173.11:33:22.41#ibcon#about to read 3, iclass 28, count 2 2006.173.11:33:22.44#ibcon#read 3, iclass 28, count 2 2006.173.11:33:22.44#ibcon#about to read 4, iclass 28, count 2 2006.173.11:33:22.44#ibcon#read 4, iclass 28, count 2 2006.173.11:33:22.44#ibcon#about to read 5, iclass 28, count 2 2006.173.11:33:22.44#ibcon#read 5, iclass 28, count 2 2006.173.11:33:22.44#ibcon#about to read 6, iclass 28, count 2 2006.173.11:33:22.44#ibcon#read 6, iclass 28, count 2 2006.173.11:33:22.44#ibcon#end of sib2, iclass 28, count 2 2006.173.11:33:22.44#ibcon#*after write, iclass 28, count 2 2006.173.11:33:22.44#ibcon#*before return 0, iclass 28, count 2 2006.173.11:33:22.44#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.11:33:22.44#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.11:33:22.44#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.11:33:22.44#ibcon#ireg 7 cls_cnt 0 2006.173.11:33:22.44#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.11:33:22.56#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.11:33:22.56#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.11:33:22.56#ibcon#enter wrdev, iclass 28, count 0 2006.173.11:33:22.56#ibcon#first serial, iclass 28, count 0 2006.173.11:33:22.56#ibcon#enter sib2, iclass 28, count 0 2006.173.11:33:22.56#ibcon#flushed, iclass 28, count 0 2006.173.11:33:22.56#ibcon#about to write, iclass 28, count 0 2006.173.11:33:22.56#ibcon#wrote, iclass 28, count 0 2006.173.11:33:22.56#ibcon#about to read 3, iclass 28, count 0 2006.173.11:33:22.58#ibcon#read 3, iclass 28, count 0 2006.173.11:33:22.58#ibcon#about to read 4, iclass 28, count 0 2006.173.11:33:22.58#ibcon#read 4, iclass 28, count 0 2006.173.11:33:22.58#ibcon#about to read 5, iclass 28, count 0 2006.173.11:33:22.58#ibcon#read 5, iclass 28, count 0 2006.173.11:33:22.58#ibcon#about to read 6, iclass 28, count 0 2006.173.11:33:22.58#ibcon#read 6, iclass 28, count 0 2006.173.11:33:22.58#ibcon#end of sib2, iclass 28, count 0 2006.173.11:33:22.58#ibcon#*mode == 0, iclass 28, count 0 2006.173.11:33:22.58#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.11:33:22.58#ibcon#[25=USB\r\n] 2006.173.11:33:22.58#ibcon#*before write, iclass 28, count 0 2006.173.11:33:22.58#ibcon#enter sib2, iclass 28, count 0 2006.173.11:33:22.58#ibcon#flushed, iclass 28, count 0 2006.173.11:33:22.58#ibcon#about to write, iclass 28, count 0 2006.173.11:33:22.58#ibcon#wrote, iclass 28, count 0 2006.173.11:33:22.58#ibcon#about to read 3, iclass 28, count 0 2006.173.11:33:22.61#ibcon#read 3, iclass 28, count 0 2006.173.11:33:22.61#ibcon#about to read 4, iclass 28, count 0 2006.173.11:33:22.61#ibcon#read 4, iclass 28, count 0 2006.173.11:33:22.61#ibcon#about to read 5, iclass 28, count 0 2006.173.11:33:22.61#ibcon#read 5, iclass 28, count 0 2006.173.11:33:22.61#ibcon#about to read 6, iclass 28, count 0 2006.173.11:33:22.61#ibcon#read 6, iclass 28, count 0 2006.173.11:33:22.61#ibcon#end of sib2, iclass 28, count 0 2006.173.11:33:22.61#ibcon#*after write, iclass 28, count 0 2006.173.11:33:22.61#ibcon#*before return 0, iclass 28, count 0 2006.173.11:33:22.61#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.11:33:22.61#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.11:33:22.61#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.11:33:22.61#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.11:33:22.61$vck44/valo=8,884.99 2006.173.11:33:22.61#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.11:33:22.61#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.11:33:22.61#ibcon#ireg 17 cls_cnt 0 2006.173.11:33:22.61#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.11:33:22.61#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.11:33:22.61#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.11:33:22.61#ibcon#enter wrdev, iclass 30, count 0 2006.173.11:33:22.61#ibcon#first serial, iclass 30, count 0 2006.173.11:33:22.61#ibcon#enter sib2, iclass 30, count 0 2006.173.11:33:22.61#ibcon#flushed, iclass 30, count 0 2006.173.11:33:22.61#ibcon#about to write, iclass 30, count 0 2006.173.11:33:22.61#ibcon#wrote, iclass 30, count 0 2006.173.11:33:22.61#ibcon#about to read 3, iclass 30, count 0 2006.173.11:33:22.63#ibcon#read 3, iclass 30, count 0 2006.173.11:33:22.63#ibcon#about to read 4, iclass 30, count 0 2006.173.11:33:22.63#ibcon#read 4, iclass 30, count 0 2006.173.11:33:22.63#ibcon#about to read 5, iclass 30, count 0 2006.173.11:33:22.63#ibcon#read 5, iclass 30, count 0 2006.173.11:33:22.63#ibcon#about to read 6, iclass 30, count 0 2006.173.11:33:22.63#ibcon#read 6, iclass 30, count 0 2006.173.11:33:22.63#ibcon#end of sib2, iclass 30, count 0 2006.173.11:33:22.63#ibcon#*mode == 0, iclass 30, count 0 2006.173.11:33:22.63#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.11:33:22.63#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.11:33:22.63#ibcon#*before write, iclass 30, count 0 2006.173.11:33:22.63#ibcon#enter sib2, iclass 30, count 0 2006.173.11:33:22.63#ibcon#flushed, iclass 30, count 0 2006.173.11:33:22.63#ibcon#about to write, iclass 30, count 0 2006.173.11:33:22.63#ibcon#wrote, iclass 30, count 0 2006.173.11:33:22.63#ibcon#about to read 3, iclass 30, count 0 2006.173.11:33:22.67#ibcon#read 3, iclass 30, count 0 2006.173.11:33:22.67#ibcon#about to read 4, iclass 30, count 0 2006.173.11:33:22.67#ibcon#read 4, iclass 30, count 0 2006.173.11:33:22.67#ibcon#about to read 5, iclass 30, count 0 2006.173.11:33:22.67#ibcon#read 5, iclass 30, count 0 2006.173.11:33:22.67#ibcon#about to read 6, iclass 30, count 0 2006.173.11:33:22.67#ibcon#read 6, iclass 30, count 0 2006.173.11:33:22.67#ibcon#end of sib2, iclass 30, count 0 2006.173.11:33:22.67#ibcon#*after write, iclass 30, count 0 2006.173.11:33:22.67#ibcon#*before return 0, iclass 30, count 0 2006.173.11:33:22.67#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.11:33:22.67#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.11:33:22.67#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.11:33:22.67#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.11:33:22.67$vck44/va=8,4 2006.173.11:33:22.67#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.173.11:33:22.67#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.173.11:33:22.67#ibcon#ireg 11 cls_cnt 2 2006.173.11:33:22.67#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.11:33:22.73#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.11:33:22.73#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.11:33:22.73#ibcon#enter wrdev, iclass 32, count 2 2006.173.11:33:22.73#ibcon#first serial, iclass 32, count 2 2006.173.11:33:22.73#ibcon#enter sib2, iclass 32, count 2 2006.173.11:33:22.73#ibcon#flushed, iclass 32, count 2 2006.173.11:33:22.73#ibcon#about to write, iclass 32, count 2 2006.173.11:33:22.73#ibcon#wrote, iclass 32, count 2 2006.173.11:33:22.73#ibcon#about to read 3, iclass 32, count 2 2006.173.11:33:22.75#ibcon#read 3, iclass 32, count 2 2006.173.11:33:22.75#ibcon#about to read 4, iclass 32, count 2 2006.173.11:33:22.75#ibcon#read 4, iclass 32, count 2 2006.173.11:33:22.75#ibcon#about to read 5, iclass 32, count 2 2006.173.11:33:22.75#ibcon#read 5, iclass 32, count 2 2006.173.11:33:22.75#ibcon#about to read 6, iclass 32, count 2 2006.173.11:33:22.75#ibcon#read 6, iclass 32, count 2 2006.173.11:33:22.75#ibcon#end of sib2, iclass 32, count 2 2006.173.11:33:22.75#ibcon#*mode == 0, iclass 32, count 2 2006.173.11:33:22.75#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.173.11:33:22.75#ibcon#[25=AT08-04\r\n] 2006.173.11:33:22.75#ibcon#*before write, iclass 32, count 2 2006.173.11:33:22.75#ibcon#enter sib2, iclass 32, count 2 2006.173.11:33:22.75#ibcon#flushed, iclass 32, count 2 2006.173.11:33:22.75#ibcon#about to write, iclass 32, count 2 2006.173.11:33:22.75#ibcon#wrote, iclass 32, count 2 2006.173.11:33:22.75#ibcon#about to read 3, iclass 32, count 2 2006.173.11:33:22.78#ibcon#read 3, iclass 32, count 2 2006.173.11:33:22.78#ibcon#about to read 4, iclass 32, count 2 2006.173.11:33:22.78#ibcon#read 4, iclass 32, count 2 2006.173.11:33:22.78#ibcon#about to read 5, iclass 32, count 2 2006.173.11:33:22.78#ibcon#read 5, iclass 32, count 2 2006.173.11:33:22.78#ibcon#about to read 6, iclass 32, count 2 2006.173.11:33:22.78#ibcon#read 6, iclass 32, count 2 2006.173.11:33:22.78#ibcon#end of sib2, iclass 32, count 2 2006.173.11:33:22.78#ibcon#*after write, iclass 32, count 2 2006.173.11:33:22.78#ibcon#*before return 0, iclass 32, count 2 2006.173.11:33:22.78#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.11:33:22.78#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.173.11:33:22.78#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.173.11:33:22.78#ibcon#ireg 7 cls_cnt 0 2006.173.11:33:22.78#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.11:33:22.90#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.11:33:22.90#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.11:33:22.90#ibcon#enter wrdev, iclass 32, count 0 2006.173.11:33:22.90#ibcon#first serial, iclass 32, count 0 2006.173.11:33:22.90#ibcon#enter sib2, iclass 32, count 0 2006.173.11:33:22.90#ibcon#flushed, iclass 32, count 0 2006.173.11:33:22.90#ibcon#about to write, iclass 32, count 0 2006.173.11:33:22.90#ibcon#wrote, iclass 32, count 0 2006.173.11:33:22.90#ibcon#about to read 3, iclass 32, count 0 2006.173.11:33:22.92#ibcon#read 3, iclass 32, count 0 2006.173.11:33:22.92#ibcon#about to read 4, iclass 32, count 0 2006.173.11:33:22.92#ibcon#read 4, iclass 32, count 0 2006.173.11:33:22.92#ibcon#about to read 5, iclass 32, count 0 2006.173.11:33:22.92#ibcon#read 5, iclass 32, count 0 2006.173.11:33:22.92#ibcon#about to read 6, iclass 32, count 0 2006.173.11:33:22.92#ibcon#read 6, iclass 32, count 0 2006.173.11:33:22.92#ibcon#end of sib2, iclass 32, count 0 2006.173.11:33:22.92#ibcon#*mode == 0, iclass 32, count 0 2006.173.11:33:22.92#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.11:33:22.92#ibcon#[25=USB\r\n] 2006.173.11:33:22.92#ibcon#*before write, iclass 32, count 0 2006.173.11:33:22.92#ibcon#enter sib2, iclass 32, count 0 2006.173.11:33:22.92#ibcon#flushed, iclass 32, count 0 2006.173.11:33:22.92#ibcon#about to write, iclass 32, count 0 2006.173.11:33:22.92#ibcon#wrote, iclass 32, count 0 2006.173.11:33:22.92#ibcon#about to read 3, iclass 32, count 0 2006.173.11:33:22.95#ibcon#read 3, iclass 32, count 0 2006.173.11:33:22.95#ibcon#about to read 4, iclass 32, count 0 2006.173.11:33:22.95#ibcon#read 4, iclass 32, count 0 2006.173.11:33:22.95#ibcon#about to read 5, iclass 32, count 0 2006.173.11:33:22.95#ibcon#read 5, iclass 32, count 0 2006.173.11:33:22.95#ibcon#about to read 6, iclass 32, count 0 2006.173.11:33:22.95#ibcon#read 6, iclass 32, count 0 2006.173.11:33:22.95#ibcon#end of sib2, iclass 32, count 0 2006.173.11:33:22.95#ibcon#*after write, iclass 32, count 0 2006.173.11:33:22.95#ibcon#*before return 0, iclass 32, count 0 2006.173.11:33:22.95#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.11:33:22.95#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.173.11:33:22.95#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.11:33:22.95#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.11:33:22.95$vck44/vblo=1,629.99 2006.173.11:33:22.95#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.11:33:22.95#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.11:33:22.95#ibcon#ireg 17 cls_cnt 0 2006.173.11:33:22.95#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.11:33:22.95#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.11:33:22.95#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.11:33:22.95#ibcon#enter wrdev, iclass 34, count 0 2006.173.11:33:22.95#ibcon#first serial, iclass 34, count 0 2006.173.11:33:22.95#ibcon#enter sib2, iclass 34, count 0 2006.173.11:33:22.95#ibcon#flushed, iclass 34, count 0 2006.173.11:33:22.95#ibcon#about to write, iclass 34, count 0 2006.173.11:33:22.95#ibcon#wrote, iclass 34, count 0 2006.173.11:33:22.95#ibcon#about to read 3, iclass 34, count 0 2006.173.11:33:22.97#ibcon#read 3, iclass 34, count 0 2006.173.11:33:22.97#ibcon#about to read 4, iclass 34, count 0 2006.173.11:33:22.97#ibcon#read 4, iclass 34, count 0 2006.173.11:33:22.97#ibcon#about to read 5, iclass 34, count 0 2006.173.11:33:22.97#ibcon#read 5, iclass 34, count 0 2006.173.11:33:22.97#ibcon#about to read 6, iclass 34, count 0 2006.173.11:33:22.97#ibcon#read 6, iclass 34, count 0 2006.173.11:33:22.97#ibcon#end of sib2, iclass 34, count 0 2006.173.11:33:22.97#ibcon#*mode == 0, iclass 34, count 0 2006.173.11:33:22.97#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.11:33:22.97#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.11:33:22.97#ibcon#*before write, iclass 34, count 0 2006.173.11:33:22.97#ibcon#enter sib2, iclass 34, count 0 2006.173.11:33:22.97#ibcon#flushed, iclass 34, count 0 2006.173.11:33:22.97#ibcon#about to write, iclass 34, count 0 2006.173.11:33:22.97#ibcon#wrote, iclass 34, count 0 2006.173.11:33:22.97#ibcon#about to read 3, iclass 34, count 0 2006.173.11:33:23.01#ibcon#read 3, iclass 34, count 0 2006.173.11:33:23.01#ibcon#about to read 4, iclass 34, count 0 2006.173.11:33:23.01#ibcon#read 4, iclass 34, count 0 2006.173.11:33:23.01#ibcon#about to read 5, iclass 34, count 0 2006.173.11:33:23.01#ibcon#read 5, iclass 34, count 0 2006.173.11:33:23.01#ibcon#about to read 6, iclass 34, count 0 2006.173.11:33:23.01#ibcon#read 6, iclass 34, count 0 2006.173.11:33:23.01#ibcon#end of sib2, iclass 34, count 0 2006.173.11:33:23.01#ibcon#*after write, iclass 34, count 0 2006.173.11:33:23.01#ibcon#*before return 0, iclass 34, count 0 2006.173.11:33:23.01#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.11:33:23.01#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.11:33:23.01#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.11:33:23.01#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.11:33:23.01$vck44/vb=1,4 2006.173.11:33:23.01#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.11:33:23.01#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.11:33:23.01#ibcon#ireg 11 cls_cnt 2 2006.173.11:33:23.01#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.11:33:23.01#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.11:33:23.01#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.11:33:23.01#ibcon#enter wrdev, iclass 36, count 2 2006.173.11:33:23.01#ibcon#first serial, iclass 36, count 2 2006.173.11:33:23.01#ibcon#enter sib2, iclass 36, count 2 2006.173.11:33:23.01#ibcon#flushed, iclass 36, count 2 2006.173.11:33:23.01#ibcon#about to write, iclass 36, count 2 2006.173.11:33:23.01#ibcon#wrote, iclass 36, count 2 2006.173.11:33:23.01#ibcon#about to read 3, iclass 36, count 2 2006.173.11:33:23.03#ibcon#read 3, iclass 36, count 2 2006.173.11:33:23.03#ibcon#about to read 4, iclass 36, count 2 2006.173.11:33:23.03#ibcon#read 4, iclass 36, count 2 2006.173.11:33:23.03#ibcon#about to read 5, iclass 36, count 2 2006.173.11:33:23.03#ibcon#read 5, iclass 36, count 2 2006.173.11:33:23.03#ibcon#about to read 6, iclass 36, count 2 2006.173.11:33:23.03#ibcon#read 6, iclass 36, count 2 2006.173.11:33:23.03#ibcon#end of sib2, iclass 36, count 2 2006.173.11:33:23.03#ibcon#*mode == 0, iclass 36, count 2 2006.173.11:33:23.03#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.11:33:23.03#ibcon#[27=AT01-04\r\n] 2006.173.11:33:23.03#ibcon#*before write, iclass 36, count 2 2006.173.11:33:23.03#ibcon#enter sib2, iclass 36, count 2 2006.173.11:33:23.03#ibcon#flushed, iclass 36, count 2 2006.173.11:33:23.03#ibcon#about to write, iclass 36, count 2 2006.173.11:33:23.03#ibcon#wrote, iclass 36, count 2 2006.173.11:33:23.03#ibcon#about to read 3, iclass 36, count 2 2006.173.11:33:23.06#ibcon#read 3, iclass 36, count 2 2006.173.11:33:23.06#ibcon#about to read 4, iclass 36, count 2 2006.173.11:33:23.06#ibcon#read 4, iclass 36, count 2 2006.173.11:33:23.06#ibcon#about to read 5, iclass 36, count 2 2006.173.11:33:23.06#ibcon#read 5, iclass 36, count 2 2006.173.11:33:23.06#ibcon#about to read 6, iclass 36, count 2 2006.173.11:33:23.06#ibcon#read 6, iclass 36, count 2 2006.173.11:33:23.06#ibcon#end of sib2, iclass 36, count 2 2006.173.11:33:23.06#ibcon#*after write, iclass 36, count 2 2006.173.11:33:23.06#ibcon#*before return 0, iclass 36, count 2 2006.173.11:33:23.06#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.11:33:23.06#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.11:33:23.06#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.11:33:23.06#ibcon#ireg 7 cls_cnt 0 2006.173.11:33:23.06#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.11:33:23.18#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.11:33:23.18#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.11:33:23.18#ibcon#enter wrdev, iclass 36, count 0 2006.173.11:33:23.18#ibcon#first serial, iclass 36, count 0 2006.173.11:33:23.18#ibcon#enter sib2, iclass 36, count 0 2006.173.11:33:23.18#ibcon#flushed, iclass 36, count 0 2006.173.11:33:23.18#ibcon#about to write, iclass 36, count 0 2006.173.11:33:23.18#ibcon#wrote, iclass 36, count 0 2006.173.11:33:23.18#ibcon#about to read 3, iclass 36, count 0 2006.173.11:33:23.20#ibcon#read 3, iclass 36, count 0 2006.173.11:33:23.20#ibcon#about to read 4, iclass 36, count 0 2006.173.11:33:23.20#ibcon#read 4, iclass 36, count 0 2006.173.11:33:23.20#ibcon#about to read 5, iclass 36, count 0 2006.173.11:33:23.20#ibcon#read 5, iclass 36, count 0 2006.173.11:33:23.20#ibcon#about to read 6, iclass 36, count 0 2006.173.11:33:23.20#ibcon#read 6, iclass 36, count 0 2006.173.11:33:23.20#ibcon#end of sib2, iclass 36, count 0 2006.173.11:33:23.20#ibcon#*mode == 0, iclass 36, count 0 2006.173.11:33:23.20#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.11:33:23.20#ibcon#[27=USB\r\n] 2006.173.11:33:23.20#ibcon#*before write, iclass 36, count 0 2006.173.11:33:23.20#ibcon#enter sib2, iclass 36, count 0 2006.173.11:33:23.20#ibcon#flushed, iclass 36, count 0 2006.173.11:33:23.20#ibcon#about to write, iclass 36, count 0 2006.173.11:33:23.20#ibcon#wrote, iclass 36, count 0 2006.173.11:33:23.20#ibcon#about to read 3, iclass 36, count 0 2006.173.11:33:23.23#ibcon#read 3, iclass 36, count 0 2006.173.11:33:23.23#ibcon#about to read 4, iclass 36, count 0 2006.173.11:33:23.23#ibcon#read 4, iclass 36, count 0 2006.173.11:33:23.23#ibcon#about to read 5, iclass 36, count 0 2006.173.11:33:23.23#ibcon#read 5, iclass 36, count 0 2006.173.11:33:23.23#ibcon#about to read 6, iclass 36, count 0 2006.173.11:33:23.23#ibcon#read 6, iclass 36, count 0 2006.173.11:33:23.23#ibcon#end of sib2, iclass 36, count 0 2006.173.11:33:23.23#ibcon#*after write, iclass 36, count 0 2006.173.11:33:23.23#ibcon#*before return 0, iclass 36, count 0 2006.173.11:33:23.23#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.11:33:23.23#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.11:33:23.23#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.11:33:23.23#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.11:33:23.23$vck44/vblo=2,634.99 2006.173.11:33:23.23#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.11:33:23.23#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.11:33:23.23#ibcon#ireg 17 cls_cnt 0 2006.173.11:33:23.23#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.11:33:23.23#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.11:33:23.23#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.11:33:23.23#ibcon#enter wrdev, iclass 38, count 0 2006.173.11:33:23.23#ibcon#first serial, iclass 38, count 0 2006.173.11:33:23.23#ibcon#enter sib2, iclass 38, count 0 2006.173.11:33:23.23#ibcon#flushed, iclass 38, count 0 2006.173.11:33:23.23#ibcon#about to write, iclass 38, count 0 2006.173.11:33:23.23#ibcon#wrote, iclass 38, count 0 2006.173.11:33:23.23#ibcon#about to read 3, iclass 38, count 0 2006.173.11:33:23.25#ibcon#read 3, iclass 38, count 0 2006.173.11:33:23.25#ibcon#about to read 4, iclass 38, count 0 2006.173.11:33:23.25#ibcon#read 4, iclass 38, count 0 2006.173.11:33:23.25#ibcon#about to read 5, iclass 38, count 0 2006.173.11:33:23.25#ibcon#read 5, iclass 38, count 0 2006.173.11:33:23.25#ibcon#about to read 6, iclass 38, count 0 2006.173.11:33:23.25#ibcon#read 6, iclass 38, count 0 2006.173.11:33:23.25#ibcon#end of sib2, iclass 38, count 0 2006.173.11:33:23.25#ibcon#*mode == 0, iclass 38, count 0 2006.173.11:33:23.25#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.11:33:23.25#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.11:33:23.25#ibcon#*before write, iclass 38, count 0 2006.173.11:33:23.25#ibcon#enter sib2, iclass 38, count 0 2006.173.11:33:23.25#ibcon#flushed, iclass 38, count 0 2006.173.11:33:23.25#ibcon#about to write, iclass 38, count 0 2006.173.11:33:23.25#ibcon#wrote, iclass 38, count 0 2006.173.11:33:23.25#ibcon#about to read 3, iclass 38, count 0 2006.173.11:33:23.29#ibcon#read 3, iclass 38, count 0 2006.173.11:33:23.29#ibcon#about to read 4, iclass 38, count 0 2006.173.11:33:23.29#ibcon#read 4, iclass 38, count 0 2006.173.11:33:23.29#ibcon#about to read 5, iclass 38, count 0 2006.173.11:33:23.29#ibcon#read 5, iclass 38, count 0 2006.173.11:33:23.29#ibcon#about to read 6, iclass 38, count 0 2006.173.11:33:23.29#ibcon#read 6, iclass 38, count 0 2006.173.11:33:23.29#ibcon#end of sib2, iclass 38, count 0 2006.173.11:33:23.29#ibcon#*after write, iclass 38, count 0 2006.173.11:33:23.29#ibcon#*before return 0, iclass 38, count 0 2006.173.11:33:23.29#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.11:33:23.29#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.11:33:23.29#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.11:33:23.29#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.11:33:23.29$vck44/vb=2,4 2006.173.11:33:23.29#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.11:33:23.29#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.11:33:23.29#ibcon#ireg 11 cls_cnt 2 2006.173.11:33:23.29#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.11:33:23.35#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.11:33:23.35#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.11:33:23.35#ibcon#enter wrdev, iclass 40, count 2 2006.173.11:33:23.35#ibcon#first serial, iclass 40, count 2 2006.173.11:33:23.35#ibcon#enter sib2, iclass 40, count 2 2006.173.11:33:23.35#ibcon#flushed, iclass 40, count 2 2006.173.11:33:23.35#ibcon#about to write, iclass 40, count 2 2006.173.11:33:23.35#ibcon#wrote, iclass 40, count 2 2006.173.11:33:23.35#ibcon#about to read 3, iclass 40, count 2 2006.173.11:33:23.37#ibcon#read 3, iclass 40, count 2 2006.173.11:33:23.37#ibcon#about to read 4, iclass 40, count 2 2006.173.11:33:23.37#ibcon#read 4, iclass 40, count 2 2006.173.11:33:23.37#ibcon#about to read 5, iclass 40, count 2 2006.173.11:33:23.37#ibcon#read 5, iclass 40, count 2 2006.173.11:33:23.37#ibcon#about to read 6, iclass 40, count 2 2006.173.11:33:23.37#ibcon#read 6, iclass 40, count 2 2006.173.11:33:23.37#ibcon#end of sib2, iclass 40, count 2 2006.173.11:33:23.37#ibcon#*mode == 0, iclass 40, count 2 2006.173.11:33:23.37#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.11:33:23.37#ibcon#[27=AT02-04\r\n] 2006.173.11:33:23.37#ibcon#*before write, iclass 40, count 2 2006.173.11:33:23.37#ibcon#enter sib2, iclass 40, count 2 2006.173.11:33:23.37#ibcon#flushed, iclass 40, count 2 2006.173.11:33:23.37#ibcon#about to write, iclass 40, count 2 2006.173.11:33:23.37#ibcon#wrote, iclass 40, count 2 2006.173.11:33:23.37#ibcon#about to read 3, iclass 40, count 2 2006.173.11:33:23.40#ibcon#read 3, iclass 40, count 2 2006.173.11:33:23.40#ibcon#about to read 4, iclass 40, count 2 2006.173.11:33:23.40#ibcon#read 4, iclass 40, count 2 2006.173.11:33:23.40#ibcon#about to read 5, iclass 40, count 2 2006.173.11:33:23.40#ibcon#read 5, iclass 40, count 2 2006.173.11:33:23.40#ibcon#about to read 6, iclass 40, count 2 2006.173.11:33:23.40#ibcon#read 6, iclass 40, count 2 2006.173.11:33:23.40#ibcon#end of sib2, iclass 40, count 2 2006.173.11:33:23.40#ibcon#*after write, iclass 40, count 2 2006.173.11:33:23.40#ibcon#*before return 0, iclass 40, count 2 2006.173.11:33:23.40#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.11:33:23.40#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.11:33:23.40#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.11:33:23.40#ibcon#ireg 7 cls_cnt 0 2006.173.11:33:23.40#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.11:33:23.52#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.11:33:23.52#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.11:33:23.52#ibcon#enter wrdev, iclass 40, count 0 2006.173.11:33:23.52#ibcon#first serial, iclass 40, count 0 2006.173.11:33:23.52#ibcon#enter sib2, iclass 40, count 0 2006.173.11:33:23.52#ibcon#flushed, iclass 40, count 0 2006.173.11:33:23.52#ibcon#about to write, iclass 40, count 0 2006.173.11:33:23.52#ibcon#wrote, iclass 40, count 0 2006.173.11:33:23.52#ibcon#about to read 3, iclass 40, count 0 2006.173.11:33:23.54#ibcon#read 3, iclass 40, count 0 2006.173.11:33:23.54#ibcon#about to read 4, iclass 40, count 0 2006.173.11:33:23.54#ibcon#read 4, iclass 40, count 0 2006.173.11:33:23.54#ibcon#about to read 5, iclass 40, count 0 2006.173.11:33:23.54#ibcon#read 5, iclass 40, count 0 2006.173.11:33:23.54#ibcon#about to read 6, iclass 40, count 0 2006.173.11:33:23.54#ibcon#read 6, iclass 40, count 0 2006.173.11:33:23.54#ibcon#end of sib2, iclass 40, count 0 2006.173.11:33:23.54#ibcon#*mode == 0, iclass 40, count 0 2006.173.11:33:23.54#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.11:33:23.54#ibcon#[27=USB\r\n] 2006.173.11:33:23.54#ibcon#*before write, iclass 40, count 0 2006.173.11:33:23.54#ibcon#enter sib2, iclass 40, count 0 2006.173.11:33:23.54#ibcon#flushed, iclass 40, count 0 2006.173.11:33:23.54#ibcon#about to write, iclass 40, count 0 2006.173.11:33:23.54#ibcon#wrote, iclass 40, count 0 2006.173.11:33:23.54#ibcon#about to read 3, iclass 40, count 0 2006.173.11:33:23.57#ibcon#read 3, iclass 40, count 0 2006.173.11:33:23.57#ibcon#about to read 4, iclass 40, count 0 2006.173.11:33:23.57#ibcon#read 4, iclass 40, count 0 2006.173.11:33:23.57#ibcon#about to read 5, iclass 40, count 0 2006.173.11:33:23.57#ibcon#read 5, iclass 40, count 0 2006.173.11:33:23.57#ibcon#about to read 6, iclass 40, count 0 2006.173.11:33:23.57#ibcon#read 6, iclass 40, count 0 2006.173.11:33:23.57#ibcon#end of sib2, iclass 40, count 0 2006.173.11:33:23.57#ibcon#*after write, iclass 40, count 0 2006.173.11:33:23.57#ibcon#*before return 0, iclass 40, count 0 2006.173.11:33:23.57#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.11:33:23.57#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.11:33:23.57#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.11:33:23.57#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.11:33:23.57$vck44/vblo=3,649.99 2006.173.11:33:23.57#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.11:33:23.57#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.11:33:23.57#ibcon#ireg 17 cls_cnt 0 2006.173.11:33:23.57#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.11:33:23.57#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.11:33:23.57#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.11:33:23.57#ibcon#enter wrdev, iclass 4, count 0 2006.173.11:33:23.57#ibcon#first serial, iclass 4, count 0 2006.173.11:33:23.57#ibcon#enter sib2, iclass 4, count 0 2006.173.11:33:23.57#ibcon#flushed, iclass 4, count 0 2006.173.11:33:23.57#ibcon#about to write, iclass 4, count 0 2006.173.11:33:23.57#ibcon#wrote, iclass 4, count 0 2006.173.11:33:23.57#ibcon#about to read 3, iclass 4, count 0 2006.173.11:33:23.59#ibcon#read 3, iclass 4, count 0 2006.173.11:33:23.59#ibcon#about to read 4, iclass 4, count 0 2006.173.11:33:23.59#ibcon#read 4, iclass 4, count 0 2006.173.11:33:23.59#ibcon#about to read 5, iclass 4, count 0 2006.173.11:33:23.59#ibcon#read 5, iclass 4, count 0 2006.173.11:33:23.59#ibcon#about to read 6, iclass 4, count 0 2006.173.11:33:23.59#ibcon#read 6, iclass 4, count 0 2006.173.11:33:23.59#ibcon#end of sib2, iclass 4, count 0 2006.173.11:33:23.59#ibcon#*mode == 0, iclass 4, count 0 2006.173.11:33:23.59#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.11:33:23.59#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.11:33:23.59#ibcon#*before write, iclass 4, count 0 2006.173.11:33:23.59#ibcon#enter sib2, iclass 4, count 0 2006.173.11:33:23.59#ibcon#flushed, iclass 4, count 0 2006.173.11:33:23.59#ibcon#about to write, iclass 4, count 0 2006.173.11:33:23.59#ibcon#wrote, iclass 4, count 0 2006.173.11:33:23.59#ibcon#about to read 3, iclass 4, count 0 2006.173.11:33:23.63#ibcon#read 3, iclass 4, count 0 2006.173.11:33:23.63#ibcon#about to read 4, iclass 4, count 0 2006.173.11:33:23.63#ibcon#read 4, iclass 4, count 0 2006.173.11:33:23.63#ibcon#about to read 5, iclass 4, count 0 2006.173.11:33:23.63#ibcon#read 5, iclass 4, count 0 2006.173.11:33:23.63#ibcon#about to read 6, iclass 4, count 0 2006.173.11:33:23.63#ibcon#read 6, iclass 4, count 0 2006.173.11:33:23.63#ibcon#end of sib2, iclass 4, count 0 2006.173.11:33:23.63#ibcon#*after write, iclass 4, count 0 2006.173.11:33:23.63#ibcon#*before return 0, iclass 4, count 0 2006.173.11:33:23.63#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.11:33:23.63#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.11:33:23.63#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.11:33:23.63#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.11:33:23.63$vck44/vb=3,4 2006.173.11:33:23.63#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.11:33:23.63#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.11:33:23.63#ibcon#ireg 11 cls_cnt 2 2006.173.11:33:23.63#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.11:33:23.69#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.11:33:23.69#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.11:33:23.69#ibcon#enter wrdev, iclass 6, count 2 2006.173.11:33:23.69#ibcon#first serial, iclass 6, count 2 2006.173.11:33:23.69#ibcon#enter sib2, iclass 6, count 2 2006.173.11:33:23.69#ibcon#flushed, iclass 6, count 2 2006.173.11:33:23.69#ibcon#about to write, iclass 6, count 2 2006.173.11:33:23.69#ibcon#wrote, iclass 6, count 2 2006.173.11:33:23.69#ibcon#about to read 3, iclass 6, count 2 2006.173.11:33:23.71#ibcon#read 3, iclass 6, count 2 2006.173.11:33:23.71#ibcon#about to read 4, iclass 6, count 2 2006.173.11:33:23.71#ibcon#read 4, iclass 6, count 2 2006.173.11:33:23.71#ibcon#about to read 5, iclass 6, count 2 2006.173.11:33:23.71#ibcon#read 5, iclass 6, count 2 2006.173.11:33:23.71#ibcon#about to read 6, iclass 6, count 2 2006.173.11:33:23.71#ibcon#read 6, iclass 6, count 2 2006.173.11:33:23.71#ibcon#end of sib2, iclass 6, count 2 2006.173.11:33:23.71#ibcon#*mode == 0, iclass 6, count 2 2006.173.11:33:23.71#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.11:33:23.71#ibcon#[27=AT03-04\r\n] 2006.173.11:33:23.71#ibcon#*before write, iclass 6, count 2 2006.173.11:33:23.71#ibcon#enter sib2, iclass 6, count 2 2006.173.11:33:23.71#ibcon#flushed, iclass 6, count 2 2006.173.11:33:23.71#ibcon#about to write, iclass 6, count 2 2006.173.11:33:23.71#ibcon#wrote, iclass 6, count 2 2006.173.11:33:23.71#ibcon#about to read 3, iclass 6, count 2 2006.173.11:33:23.74#ibcon#read 3, iclass 6, count 2 2006.173.11:33:23.74#ibcon#about to read 4, iclass 6, count 2 2006.173.11:33:23.74#ibcon#read 4, iclass 6, count 2 2006.173.11:33:23.74#ibcon#about to read 5, iclass 6, count 2 2006.173.11:33:23.74#ibcon#read 5, iclass 6, count 2 2006.173.11:33:23.74#ibcon#about to read 6, iclass 6, count 2 2006.173.11:33:23.74#ibcon#read 6, iclass 6, count 2 2006.173.11:33:23.74#ibcon#end of sib2, iclass 6, count 2 2006.173.11:33:23.74#ibcon#*after write, iclass 6, count 2 2006.173.11:33:23.74#ibcon#*before return 0, iclass 6, count 2 2006.173.11:33:23.74#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.11:33:23.74#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.11:33:23.74#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.11:33:23.74#ibcon#ireg 7 cls_cnt 0 2006.173.11:33:23.74#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.11:33:23.86#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.11:33:23.86#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.11:33:23.86#ibcon#enter wrdev, iclass 6, count 0 2006.173.11:33:23.86#ibcon#first serial, iclass 6, count 0 2006.173.11:33:23.86#ibcon#enter sib2, iclass 6, count 0 2006.173.11:33:23.86#ibcon#flushed, iclass 6, count 0 2006.173.11:33:23.86#ibcon#about to write, iclass 6, count 0 2006.173.11:33:23.86#ibcon#wrote, iclass 6, count 0 2006.173.11:33:23.86#ibcon#about to read 3, iclass 6, count 0 2006.173.11:33:23.88#ibcon#read 3, iclass 6, count 0 2006.173.11:33:23.88#ibcon#about to read 4, iclass 6, count 0 2006.173.11:33:23.88#ibcon#read 4, iclass 6, count 0 2006.173.11:33:23.88#ibcon#about to read 5, iclass 6, count 0 2006.173.11:33:23.88#ibcon#read 5, iclass 6, count 0 2006.173.11:33:23.88#ibcon#about to read 6, iclass 6, count 0 2006.173.11:33:23.88#ibcon#read 6, iclass 6, count 0 2006.173.11:33:23.88#ibcon#end of sib2, iclass 6, count 0 2006.173.11:33:23.88#ibcon#*mode == 0, iclass 6, count 0 2006.173.11:33:23.88#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.11:33:23.88#ibcon#[27=USB\r\n] 2006.173.11:33:23.88#ibcon#*before write, iclass 6, count 0 2006.173.11:33:23.88#ibcon#enter sib2, iclass 6, count 0 2006.173.11:33:23.88#ibcon#flushed, iclass 6, count 0 2006.173.11:33:23.88#ibcon#about to write, iclass 6, count 0 2006.173.11:33:23.88#ibcon#wrote, iclass 6, count 0 2006.173.11:33:23.88#ibcon#about to read 3, iclass 6, count 0 2006.173.11:33:23.91#ibcon#read 3, iclass 6, count 0 2006.173.11:33:23.91#ibcon#about to read 4, iclass 6, count 0 2006.173.11:33:23.91#ibcon#read 4, iclass 6, count 0 2006.173.11:33:23.91#ibcon#about to read 5, iclass 6, count 0 2006.173.11:33:23.91#ibcon#read 5, iclass 6, count 0 2006.173.11:33:23.91#ibcon#about to read 6, iclass 6, count 0 2006.173.11:33:23.91#ibcon#read 6, iclass 6, count 0 2006.173.11:33:23.91#ibcon#end of sib2, iclass 6, count 0 2006.173.11:33:23.91#ibcon#*after write, iclass 6, count 0 2006.173.11:33:23.91#ibcon#*before return 0, iclass 6, count 0 2006.173.11:33:23.91#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.11:33:23.91#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.11:33:23.91#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.11:33:23.91#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.11:33:23.91$vck44/vblo=4,679.99 2006.173.11:33:23.91#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.11:33:23.91#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.11:33:23.91#ibcon#ireg 17 cls_cnt 0 2006.173.11:33:23.91#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.11:33:23.91#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.11:33:23.91#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.11:33:23.91#ibcon#enter wrdev, iclass 10, count 0 2006.173.11:33:23.91#ibcon#first serial, iclass 10, count 0 2006.173.11:33:23.91#ibcon#enter sib2, iclass 10, count 0 2006.173.11:33:23.91#ibcon#flushed, iclass 10, count 0 2006.173.11:33:23.91#ibcon#about to write, iclass 10, count 0 2006.173.11:33:23.91#ibcon#wrote, iclass 10, count 0 2006.173.11:33:23.91#ibcon#about to read 3, iclass 10, count 0 2006.173.11:33:23.93#ibcon#read 3, iclass 10, count 0 2006.173.11:33:23.93#ibcon#about to read 4, iclass 10, count 0 2006.173.11:33:23.93#ibcon#read 4, iclass 10, count 0 2006.173.11:33:23.93#ibcon#about to read 5, iclass 10, count 0 2006.173.11:33:23.93#ibcon#read 5, iclass 10, count 0 2006.173.11:33:23.93#ibcon#about to read 6, iclass 10, count 0 2006.173.11:33:23.93#ibcon#read 6, iclass 10, count 0 2006.173.11:33:23.93#ibcon#end of sib2, iclass 10, count 0 2006.173.11:33:23.93#ibcon#*mode == 0, iclass 10, count 0 2006.173.11:33:23.93#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.11:33:23.93#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.11:33:23.93#ibcon#*before write, iclass 10, count 0 2006.173.11:33:23.93#ibcon#enter sib2, iclass 10, count 0 2006.173.11:33:23.93#ibcon#flushed, iclass 10, count 0 2006.173.11:33:23.93#ibcon#about to write, iclass 10, count 0 2006.173.11:33:23.93#ibcon#wrote, iclass 10, count 0 2006.173.11:33:23.93#ibcon#about to read 3, iclass 10, count 0 2006.173.11:33:23.97#ibcon#read 3, iclass 10, count 0 2006.173.11:33:23.97#ibcon#about to read 4, iclass 10, count 0 2006.173.11:33:23.97#ibcon#read 4, iclass 10, count 0 2006.173.11:33:23.97#ibcon#about to read 5, iclass 10, count 0 2006.173.11:33:23.97#ibcon#read 5, iclass 10, count 0 2006.173.11:33:23.97#ibcon#about to read 6, iclass 10, count 0 2006.173.11:33:23.97#ibcon#read 6, iclass 10, count 0 2006.173.11:33:23.97#ibcon#end of sib2, iclass 10, count 0 2006.173.11:33:23.97#ibcon#*after write, iclass 10, count 0 2006.173.11:33:23.97#ibcon#*before return 0, iclass 10, count 0 2006.173.11:33:23.97#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.11:33:23.97#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.11:33:23.97#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.11:33:23.97#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.11:33:23.97$vck44/vb=4,4 2006.173.11:33:23.97#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.11:33:23.97#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.11:33:23.97#ibcon#ireg 11 cls_cnt 2 2006.173.11:33:23.97#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.11:33:24.03#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.11:33:24.03#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.11:33:24.03#ibcon#enter wrdev, iclass 12, count 2 2006.173.11:33:24.03#ibcon#first serial, iclass 12, count 2 2006.173.11:33:24.03#ibcon#enter sib2, iclass 12, count 2 2006.173.11:33:24.03#ibcon#flushed, iclass 12, count 2 2006.173.11:33:24.03#ibcon#about to write, iclass 12, count 2 2006.173.11:33:24.03#ibcon#wrote, iclass 12, count 2 2006.173.11:33:24.03#ibcon#about to read 3, iclass 12, count 2 2006.173.11:33:24.05#ibcon#read 3, iclass 12, count 2 2006.173.11:33:24.05#ibcon#about to read 4, iclass 12, count 2 2006.173.11:33:24.05#ibcon#read 4, iclass 12, count 2 2006.173.11:33:24.05#ibcon#about to read 5, iclass 12, count 2 2006.173.11:33:24.05#ibcon#read 5, iclass 12, count 2 2006.173.11:33:24.05#ibcon#about to read 6, iclass 12, count 2 2006.173.11:33:24.05#ibcon#read 6, iclass 12, count 2 2006.173.11:33:24.05#ibcon#end of sib2, iclass 12, count 2 2006.173.11:33:24.05#ibcon#*mode == 0, iclass 12, count 2 2006.173.11:33:24.05#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.11:33:24.05#ibcon#[27=AT04-04\r\n] 2006.173.11:33:24.05#ibcon#*before write, iclass 12, count 2 2006.173.11:33:24.05#ibcon#enter sib2, iclass 12, count 2 2006.173.11:33:24.05#ibcon#flushed, iclass 12, count 2 2006.173.11:33:24.05#ibcon#about to write, iclass 12, count 2 2006.173.11:33:24.05#ibcon#wrote, iclass 12, count 2 2006.173.11:33:24.05#ibcon#about to read 3, iclass 12, count 2 2006.173.11:33:24.08#ibcon#read 3, iclass 12, count 2 2006.173.11:33:24.08#ibcon#about to read 4, iclass 12, count 2 2006.173.11:33:24.08#ibcon#read 4, iclass 12, count 2 2006.173.11:33:24.08#ibcon#about to read 5, iclass 12, count 2 2006.173.11:33:24.08#ibcon#read 5, iclass 12, count 2 2006.173.11:33:24.08#ibcon#about to read 6, iclass 12, count 2 2006.173.11:33:24.08#ibcon#read 6, iclass 12, count 2 2006.173.11:33:24.08#ibcon#end of sib2, iclass 12, count 2 2006.173.11:33:24.08#ibcon#*after write, iclass 12, count 2 2006.173.11:33:24.08#ibcon#*before return 0, iclass 12, count 2 2006.173.11:33:24.08#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.11:33:24.08#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.11:33:24.08#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.11:33:24.08#ibcon#ireg 7 cls_cnt 0 2006.173.11:33:24.08#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.11:33:24.20#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.11:33:24.20#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.11:33:24.20#ibcon#enter wrdev, iclass 12, count 0 2006.173.11:33:24.20#ibcon#first serial, iclass 12, count 0 2006.173.11:33:24.20#ibcon#enter sib2, iclass 12, count 0 2006.173.11:33:24.20#ibcon#flushed, iclass 12, count 0 2006.173.11:33:24.20#ibcon#about to write, iclass 12, count 0 2006.173.11:33:24.20#ibcon#wrote, iclass 12, count 0 2006.173.11:33:24.20#ibcon#about to read 3, iclass 12, count 0 2006.173.11:33:24.22#ibcon#read 3, iclass 12, count 0 2006.173.11:33:24.22#ibcon#about to read 4, iclass 12, count 0 2006.173.11:33:24.22#ibcon#read 4, iclass 12, count 0 2006.173.11:33:24.22#ibcon#about to read 5, iclass 12, count 0 2006.173.11:33:24.22#ibcon#read 5, iclass 12, count 0 2006.173.11:33:24.22#ibcon#about to read 6, iclass 12, count 0 2006.173.11:33:24.22#ibcon#read 6, iclass 12, count 0 2006.173.11:33:24.22#ibcon#end of sib2, iclass 12, count 0 2006.173.11:33:24.22#ibcon#*mode == 0, iclass 12, count 0 2006.173.11:33:24.22#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.11:33:24.22#ibcon#[27=USB\r\n] 2006.173.11:33:24.22#ibcon#*before write, iclass 12, count 0 2006.173.11:33:24.22#ibcon#enter sib2, iclass 12, count 0 2006.173.11:33:24.22#ibcon#flushed, iclass 12, count 0 2006.173.11:33:24.22#ibcon#about to write, iclass 12, count 0 2006.173.11:33:24.22#ibcon#wrote, iclass 12, count 0 2006.173.11:33:24.22#ibcon#about to read 3, iclass 12, count 0 2006.173.11:33:24.25#ibcon#read 3, iclass 12, count 0 2006.173.11:33:24.25#ibcon#about to read 4, iclass 12, count 0 2006.173.11:33:24.25#ibcon#read 4, iclass 12, count 0 2006.173.11:33:24.25#ibcon#about to read 5, iclass 12, count 0 2006.173.11:33:24.25#ibcon#read 5, iclass 12, count 0 2006.173.11:33:24.25#ibcon#about to read 6, iclass 12, count 0 2006.173.11:33:24.25#ibcon#read 6, iclass 12, count 0 2006.173.11:33:24.25#ibcon#end of sib2, iclass 12, count 0 2006.173.11:33:24.25#ibcon#*after write, iclass 12, count 0 2006.173.11:33:24.25#ibcon#*before return 0, iclass 12, count 0 2006.173.11:33:24.25#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.11:33:24.25#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.11:33:24.25#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.11:33:24.25#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.11:33:24.25$vck44/vblo=5,709.99 2006.173.11:33:24.25#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.11:33:24.25#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.11:33:24.25#ibcon#ireg 17 cls_cnt 0 2006.173.11:33:24.25#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.11:33:24.25#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.11:33:24.25#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.11:33:24.25#ibcon#enter wrdev, iclass 14, count 0 2006.173.11:33:24.25#ibcon#first serial, iclass 14, count 0 2006.173.11:33:24.25#ibcon#enter sib2, iclass 14, count 0 2006.173.11:33:24.25#ibcon#flushed, iclass 14, count 0 2006.173.11:33:24.25#ibcon#about to write, iclass 14, count 0 2006.173.11:33:24.25#ibcon#wrote, iclass 14, count 0 2006.173.11:33:24.25#ibcon#about to read 3, iclass 14, count 0 2006.173.11:33:24.27#ibcon#read 3, iclass 14, count 0 2006.173.11:33:24.27#ibcon#about to read 4, iclass 14, count 0 2006.173.11:33:24.27#ibcon#read 4, iclass 14, count 0 2006.173.11:33:24.27#ibcon#about to read 5, iclass 14, count 0 2006.173.11:33:24.27#ibcon#read 5, iclass 14, count 0 2006.173.11:33:24.27#ibcon#about to read 6, iclass 14, count 0 2006.173.11:33:24.27#ibcon#read 6, iclass 14, count 0 2006.173.11:33:24.27#ibcon#end of sib2, iclass 14, count 0 2006.173.11:33:24.27#ibcon#*mode == 0, iclass 14, count 0 2006.173.11:33:24.27#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.11:33:24.27#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.11:33:24.27#ibcon#*before write, iclass 14, count 0 2006.173.11:33:24.27#ibcon#enter sib2, iclass 14, count 0 2006.173.11:33:24.27#ibcon#flushed, iclass 14, count 0 2006.173.11:33:24.27#ibcon#about to write, iclass 14, count 0 2006.173.11:33:24.27#ibcon#wrote, iclass 14, count 0 2006.173.11:33:24.27#ibcon#about to read 3, iclass 14, count 0 2006.173.11:33:24.31#ibcon#read 3, iclass 14, count 0 2006.173.11:33:24.31#ibcon#about to read 4, iclass 14, count 0 2006.173.11:33:24.31#ibcon#read 4, iclass 14, count 0 2006.173.11:33:24.31#ibcon#about to read 5, iclass 14, count 0 2006.173.11:33:24.31#ibcon#read 5, iclass 14, count 0 2006.173.11:33:24.31#ibcon#about to read 6, iclass 14, count 0 2006.173.11:33:24.31#ibcon#read 6, iclass 14, count 0 2006.173.11:33:24.31#ibcon#end of sib2, iclass 14, count 0 2006.173.11:33:24.31#ibcon#*after write, iclass 14, count 0 2006.173.11:33:24.31#ibcon#*before return 0, iclass 14, count 0 2006.173.11:33:24.31#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.11:33:24.31#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.11:33:24.31#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.11:33:24.31#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.11:33:24.31$vck44/vb=5,4 2006.173.11:33:24.31#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.11:33:24.31#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.11:33:24.31#ibcon#ireg 11 cls_cnt 2 2006.173.11:33:24.31#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.11:33:24.37#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.11:33:24.37#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.11:33:24.37#ibcon#enter wrdev, iclass 16, count 2 2006.173.11:33:24.37#ibcon#first serial, iclass 16, count 2 2006.173.11:33:24.37#ibcon#enter sib2, iclass 16, count 2 2006.173.11:33:24.37#ibcon#flushed, iclass 16, count 2 2006.173.11:33:24.37#ibcon#about to write, iclass 16, count 2 2006.173.11:33:24.37#ibcon#wrote, iclass 16, count 2 2006.173.11:33:24.37#ibcon#about to read 3, iclass 16, count 2 2006.173.11:33:24.39#ibcon#read 3, iclass 16, count 2 2006.173.11:33:24.39#ibcon#about to read 4, iclass 16, count 2 2006.173.11:33:24.39#ibcon#read 4, iclass 16, count 2 2006.173.11:33:24.39#ibcon#about to read 5, iclass 16, count 2 2006.173.11:33:24.39#ibcon#read 5, iclass 16, count 2 2006.173.11:33:24.39#ibcon#about to read 6, iclass 16, count 2 2006.173.11:33:24.39#ibcon#read 6, iclass 16, count 2 2006.173.11:33:24.39#ibcon#end of sib2, iclass 16, count 2 2006.173.11:33:24.39#ibcon#*mode == 0, iclass 16, count 2 2006.173.11:33:24.39#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.11:33:24.39#ibcon#[27=AT05-04\r\n] 2006.173.11:33:24.39#ibcon#*before write, iclass 16, count 2 2006.173.11:33:24.39#ibcon#enter sib2, iclass 16, count 2 2006.173.11:33:24.39#ibcon#flushed, iclass 16, count 2 2006.173.11:33:24.39#ibcon#about to write, iclass 16, count 2 2006.173.11:33:24.39#ibcon#wrote, iclass 16, count 2 2006.173.11:33:24.39#ibcon#about to read 3, iclass 16, count 2 2006.173.11:33:24.42#ibcon#read 3, iclass 16, count 2 2006.173.11:33:24.42#ibcon#about to read 4, iclass 16, count 2 2006.173.11:33:24.42#ibcon#read 4, iclass 16, count 2 2006.173.11:33:24.42#ibcon#about to read 5, iclass 16, count 2 2006.173.11:33:24.42#ibcon#read 5, iclass 16, count 2 2006.173.11:33:24.42#ibcon#about to read 6, iclass 16, count 2 2006.173.11:33:24.42#ibcon#read 6, iclass 16, count 2 2006.173.11:33:24.42#ibcon#end of sib2, iclass 16, count 2 2006.173.11:33:24.42#ibcon#*after write, iclass 16, count 2 2006.173.11:33:24.42#ibcon#*before return 0, iclass 16, count 2 2006.173.11:33:24.42#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.11:33:24.42#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.11:33:24.42#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.11:33:24.42#ibcon#ireg 7 cls_cnt 0 2006.173.11:33:24.42#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.11:33:24.54#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.11:33:24.54#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.11:33:24.54#ibcon#enter wrdev, iclass 16, count 0 2006.173.11:33:24.54#ibcon#first serial, iclass 16, count 0 2006.173.11:33:24.54#ibcon#enter sib2, iclass 16, count 0 2006.173.11:33:24.54#ibcon#flushed, iclass 16, count 0 2006.173.11:33:24.54#ibcon#about to write, iclass 16, count 0 2006.173.11:33:24.54#ibcon#wrote, iclass 16, count 0 2006.173.11:33:24.54#ibcon#about to read 3, iclass 16, count 0 2006.173.11:33:24.56#ibcon#read 3, iclass 16, count 0 2006.173.11:33:24.56#ibcon#about to read 4, iclass 16, count 0 2006.173.11:33:24.56#ibcon#read 4, iclass 16, count 0 2006.173.11:33:24.56#ibcon#about to read 5, iclass 16, count 0 2006.173.11:33:24.56#ibcon#read 5, iclass 16, count 0 2006.173.11:33:24.56#ibcon#about to read 6, iclass 16, count 0 2006.173.11:33:24.56#ibcon#read 6, iclass 16, count 0 2006.173.11:33:24.56#ibcon#end of sib2, iclass 16, count 0 2006.173.11:33:24.56#ibcon#*mode == 0, iclass 16, count 0 2006.173.11:33:24.56#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.11:33:24.56#ibcon#[27=USB\r\n] 2006.173.11:33:24.56#ibcon#*before write, iclass 16, count 0 2006.173.11:33:24.56#ibcon#enter sib2, iclass 16, count 0 2006.173.11:33:24.56#ibcon#flushed, iclass 16, count 0 2006.173.11:33:24.56#ibcon#about to write, iclass 16, count 0 2006.173.11:33:24.56#ibcon#wrote, iclass 16, count 0 2006.173.11:33:24.56#ibcon#about to read 3, iclass 16, count 0 2006.173.11:33:24.59#ibcon#read 3, iclass 16, count 0 2006.173.11:33:24.59#ibcon#about to read 4, iclass 16, count 0 2006.173.11:33:24.59#ibcon#read 4, iclass 16, count 0 2006.173.11:33:24.59#ibcon#about to read 5, iclass 16, count 0 2006.173.11:33:24.59#ibcon#read 5, iclass 16, count 0 2006.173.11:33:24.59#ibcon#about to read 6, iclass 16, count 0 2006.173.11:33:24.59#ibcon#read 6, iclass 16, count 0 2006.173.11:33:24.59#ibcon#end of sib2, iclass 16, count 0 2006.173.11:33:24.59#ibcon#*after write, iclass 16, count 0 2006.173.11:33:24.59#ibcon#*before return 0, iclass 16, count 0 2006.173.11:33:24.59#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.11:33:24.59#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.11:33:24.59#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.11:33:24.59#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.11:33:24.59$vck44/vblo=6,719.99 2006.173.11:33:24.59#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.11:33:24.59#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.11:33:24.59#ibcon#ireg 17 cls_cnt 0 2006.173.11:33:24.59#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.11:33:24.59#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.11:33:24.59#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.11:33:24.59#ibcon#enter wrdev, iclass 18, count 0 2006.173.11:33:24.59#ibcon#first serial, iclass 18, count 0 2006.173.11:33:24.59#ibcon#enter sib2, iclass 18, count 0 2006.173.11:33:24.59#ibcon#flushed, iclass 18, count 0 2006.173.11:33:24.59#ibcon#about to write, iclass 18, count 0 2006.173.11:33:24.59#ibcon#wrote, iclass 18, count 0 2006.173.11:33:24.59#ibcon#about to read 3, iclass 18, count 0 2006.173.11:33:24.61#ibcon#read 3, iclass 18, count 0 2006.173.11:33:24.61#ibcon#about to read 4, iclass 18, count 0 2006.173.11:33:24.61#ibcon#read 4, iclass 18, count 0 2006.173.11:33:24.61#ibcon#about to read 5, iclass 18, count 0 2006.173.11:33:24.61#ibcon#read 5, iclass 18, count 0 2006.173.11:33:24.61#ibcon#about to read 6, iclass 18, count 0 2006.173.11:33:24.61#ibcon#read 6, iclass 18, count 0 2006.173.11:33:24.61#ibcon#end of sib2, iclass 18, count 0 2006.173.11:33:24.61#ibcon#*mode == 0, iclass 18, count 0 2006.173.11:33:24.61#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.11:33:24.61#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.11:33:24.61#ibcon#*before write, iclass 18, count 0 2006.173.11:33:24.61#ibcon#enter sib2, iclass 18, count 0 2006.173.11:33:24.61#ibcon#flushed, iclass 18, count 0 2006.173.11:33:24.61#ibcon#about to write, iclass 18, count 0 2006.173.11:33:24.61#ibcon#wrote, iclass 18, count 0 2006.173.11:33:24.61#ibcon#about to read 3, iclass 18, count 0 2006.173.11:33:24.65#ibcon#read 3, iclass 18, count 0 2006.173.11:33:24.65#ibcon#about to read 4, iclass 18, count 0 2006.173.11:33:24.65#ibcon#read 4, iclass 18, count 0 2006.173.11:33:24.65#ibcon#about to read 5, iclass 18, count 0 2006.173.11:33:24.65#ibcon#read 5, iclass 18, count 0 2006.173.11:33:24.65#ibcon#about to read 6, iclass 18, count 0 2006.173.11:33:24.65#ibcon#read 6, iclass 18, count 0 2006.173.11:33:24.65#ibcon#end of sib2, iclass 18, count 0 2006.173.11:33:24.65#ibcon#*after write, iclass 18, count 0 2006.173.11:33:24.65#ibcon#*before return 0, iclass 18, count 0 2006.173.11:33:24.65#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.11:33:24.65#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.11:33:24.65#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.11:33:24.65#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.11:33:24.65$vck44/vb=6,4 2006.173.11:33:24.65#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.11:33:24.65#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.11:33:24.65#ibcon#ireg 11 cls_cnt 2 2006.173.11:33:24.65#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.11:33:24.71#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.11:33:24.71#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.11:33:24.71#ibcon#enter wrdev, iclass 20, count 2 2006.173.11:33:24.71#ibcon#first serial, iclass 20, count 2 2006.173.11:33:24.71#ibcon#enter sib2, iclass 20, count 2 2006.173.11:33:24.71#ibcon#flushed, iclass 20, count 2 2006.173.11:33:24.71#ibcon#about to write, iclass 20, count 2 2006.173.11:33:24.71#ibcon#wrote, iclass 20, count 2 2006.173.11:33:24.71#ibcon#about to read 3, iclass 20, count 2 2006.173.11:33:24.73#ibcon#read 3, iclass 20, count 2 2006.173.11:33:24.73#ibcon#about to read 4, iclass 20, count 2 2006.173.11:33:24.73#ibcon#read 4, iclass 20, count 2 2006.173.11:33:24.73#ibcon#about to read 5, iclass 20, count 2 2006.173.11:33:24.73#ibcon#read 5, iclass 20, count 2 2006.173.11:33:24.73#ibcon#about to read 6, iclass 20, count 2 2006.173.11:33:24.73#ibcon#read 6, iclass 20, count 2 2006.173.11:33:24.73#ibcon#end of sib2, iclass 20, count 2 2006.173.11:33:24.73#ibcon#*mode == 0, iclass 20, count 2 2006.173.11:33:24.73#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.11:33:24.73#ibcon#[27=AT06-04\r\n] 2006.173.11:33:24.73#ibcon#*before write, iclass 20, count 2 2006.173.11:33:24.73#ibcon#enter sib2, iclass 20, count 2 2006.173.11:33:24.73#ibcon#flushed, iclass 20, count 2 2006.173.11:33:24.73#ibcon#about to write, iclass 20, count 2 2006.173.11:33:24.73#ibcon#wrote, iclass 20, count 2 2006.173.11:33:24.73#ibcon#about to read 3, iclass 20, count 2 2006.173.11:33:24.76#ibcon#read 3, iclass 20, count 2 2006.173.11:33:24.76#ibcon#about to read 4, iclass 20, count 2 2006.173.11:33:24.76#ibcon#read 4, iclass 20, count 2 2006.173.11:33:24.76#ibcon#about to read 5, iclass 20, count 2 2006.173.11:33:24.76#ibcon#read 5, iclass 20, count 2 2006.173.11:33:24.76#ibcon#about to read 6, iclass 20, count 2 2006.173.11:33:24.76#ibcon#read 6, iclass 20, count 2 2006.173.11:33:24.76#ibcon#end of sib2, iclass 20, count 2 2006.173.11:33:24.76#ibcon#*after write, iclass 20, count 2 2006.173.11:33:24.76#ibcon#*before return 0, iclass 20, count 2 2006.173.11:33:24.76#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.11:33:24.76#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.11:33:24.76#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.11:33:24.76#ibcon#ireg 7 cls_cnt 0 2006.173.11:33:24.76#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.11:33:24.88#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.11:33:24.88#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.11:33:24.88#ibcon#enter wrdev, iclass 20, count 0 2006.173.11:33:24.88#ibcon#first serial, iclass 20, count 0 2006.173.11:33:24.88#ibcon#enter sib2, iclass 20, count 0 2006.173.11:33:24.88#ibcon#flushed, iclass 20, count 0 2006.173.11:33:24.88#ibcon#about to write, iclass 20, count 0 2006.173.11:33:24.88#ibcon#wrote, iclass 20, count 0 2006.173.11:33:24.88#ibcon#about to read 3, iclass 20, count 0 2006.173.11:33:24.90#ibcon#read 3, iclass 20, count 0 2006.173.11:33:24.90#ibcon#about to read 4, iclass 20, count 0 2006.173.11:33:24.90#ibcon#read 4, iclass 20, count 0 2006.173.11:33:24.90#ibcon#about to read 5, iclass 20, count 0 2006.173.11:33:24.90#ibcon#read 5, iclass 20, count 0 2006.173.11:33:24.90#ibcon#about to read 6, iclass 20, count 0 2006.173.11:33:24.90#ibcon#read 6, iclass 20, count 0 2006.173.11:33:24.90#ibcon#end of sib2, iclass 20, count 0 2006.173.11:33:24.90#ibcon#*mode == 0, iclass 20, count 0 2006.173.11:33:24.90#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.11:33:24.90#ibcon#[27=USB\r\n] 2006.173.11:33:24.90#ibcon#*before write, iclass 20, count 0 2006.173.11:33:24.90#ibcon#enter sib2, iclass 20, count 0 2006.173.11:33:24.90#ibcon#flushed, iclass 20, count 0 2006.173.11:33:24.90#ibcon#about to write, iclass 20, count 0 2006.173.11:33:24.90#ibcon#wrote, iclass 20, count 0 2006.173.11:33:24.90#ibcon#about to read 3, iclass 20, count 0 2006.173.11:33:24.93#ibcon#read 3, iclass 20, count 0 2006.173.11:33:24.93#ibcon#about to read 4, iclass 20, count 0 2006.173.11:33:24.93#ibcon#read 4, iclass 20, count 0 2006.173.11:33:24.93#ibcon#about to read 5, iclass 20, count 0 2006.173.11:33:24.93#ibcon#read 5, iclass 20, count 0 2006.173.11:33:24.93#ibcon#about to read 6, iclass 20, count 0 2006.173.11:33:24.93#ibcon#read 6, iclass 20, count 0 2006.173.11:33:24.93#ibcon#end of sib2, iclass 20, count 0 2006.173.11:33:24.93#ibcon#*after write, iclass 20, count 0 2006.173.11:33:24.93#ibcon#*before return 0, iclass 20, count 0 2006.173.11:33:24.93#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.11:33:24.93#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.11:33:24.93#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.11:33:24.93#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.11:33:24.93$vck44/vblo=7,734.99 2006.173.11:33:24.93#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.11:33:24.93#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.11:33:24.93#ibcon#ireg 17 cls_cnt 0 2006.173.11:33:24.93#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.11:33:24.93#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.11:33:24.93#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.11:33:24.93#ibcon#enter wrdev, iclass 22, count 0 2006.173.11:33:24.93#ibcon#first serial, iclass 22, count 0 2006.173.11:33:24.93#ibcon#enter sib2, iclass 22, count 0 2006.173.11:33:24.93#ibcon#flushed, iclass 22, count 0 2006.173.11:33:24.93#ibcon#about to write, iclass 22, count 0 2006.173.11:33:24.93#ibcon#wrote, iclass 22, count 0 2006.173.11:33:24.93#ibcon#about to read 3, iclass 22, count 0 2006.173.11:33:24.95#ibcon#read 3, iclass 22, count 0 2006.173.11:33:24.95#ibcon#about to read 4, iclass 22, count 0 2006.173.11:33:24.95#ibcon#read 4, iclass 22, count 0 2006.173.11:33:24.95#ibcon#about to read 5, iclass 22, count 0 2006.173.11:33:24.95#ibcon#read 5, iclass 22, count 0 2006.173.11:33:24.95#ibcon#about to read 6, iclass 22, count 0 2006.173.11:33:24.95#ibcon#read 6, iclass 22, count 0 2006.173.11:33:24.95#ibcon#end of sib2, iclass 22, count 0 2006.173.11:33:24.95#ibcon#*mode == 0, iclass 22, count 0 2006.173.11:33:24.95#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.11:33:24.95#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.11:33:24.95#ibcon#*before write, iclass 22, count 0 2006.173.11:33:24.95#ibcon#enter sib2, iclass 22, count 0 2006.173.11:33:24.95#ibcon#flushed, iclass 22, count 0 2006.173.11:33:24.95#ibcon#about to write, iclass 22, count 0 2006.173.11:33:24.95#ibcon#wrote, iclass 22, count 0 2006.173.11:33:24.95#ibcon#about to read 3, iclass 22, count 0 2006.173.11:33:24.99#ibcon#read 3, iclass 22, count 0 2006.173.11:33:24.99#ibcon#about to read 4, iclass 22, count 0 2006.173.11:33:24.99#ibcon#read 4, iclass 22, count 0 2006.173.11:33:24.99#ibcon#about to read 5, iclass 22, count 0 2006.173.11:33:24.99#ibcon#read 5, iclass 22, count 0 2006.173.11:33:24.99#ibcon#about to read 6, iclass 22, count 0 2006.173.11:33:24.99#ibcon#read 6, iclass 22, count 0 2006.173.11:33:24.99#ibcon#end of sib2, iclass 22, count 0 2006.173.11:33:24.99#ibcon#*after write, iclass 22, count 0 2006.173.11:33:24.99#ibcon#*before return 0, iclass 22, count 0 2006.173.11:33:24.99#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.11:33:24.99#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.11:33:24.99#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.11:33:24.99#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.11:33:24.99$vck44/vb=7,4 2006.173.11:33:24.99#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.11:33:24.99#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.11:33:24.99#ibcon#ireg 11 cls_cnt 2 2006.173.11:33:24.99#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.11:33:25.05#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.11:33:25.05#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.11:33:25.05#ibcon#enter wrdev, iclass 24, count 2 2006.173.11:33:25.05#ibcon#first serial, iclass 24, count 2 2006.173.11:33:25.05#ibcon#enter sib2, iclass 24, count 2 2006.173.11:33:25.05#ibcon#flushed, iclass 24, count 2 2006.173.11:33:25.05#ibcon#about to write, iclass 24, count 2 2006.173.11:33:25.05#ibcon#wrote, iclass 24, count 2 2006.173.11:33:25.05#ibcon#about to read 3, iclass 24, count 2 2006.173.11:33:25.07#ibcon#read 3, iclass 24, count 2 2006.173.11:33:25.07#ibcon#about to read 4, iclass 24, count 2 2006.173.11:33:25.07#ibcon#read 4, iclass 24, count 2 2006.173.11:33:25.07#ibcon#about to read 5, iclass 24, count 2 2006.173.11:33:25.07#ibcon#read 5, iclass 24, count 2 2006.173.11:33:25.07#ibcon#about to read 6, iclass 24, count 2 2006.173.11:33:25.07#ibcon#read 6, iclass 24, count 2 2006.173.11:33:25.07#ibcon#end of sib2, iclass 24, count 2 2006.173.11:33:25.07#ibcon#*mode == 0, iclass 24, count 2 2006.173.11:33:25.07#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.11:33:25.07#ibcon#[27=AT07-04\r\n] 2006.173.11:33:25.07#ibcon#*before write, iclass 24, count 2 2006.173.11:33:25.07#ibcon#enter sib2, iclass 24, count 2 2006.173.11:33:25.07#ibcon#flushed, iclass 24, count 2 2006.173.11:33:25.07#ibcon#about to write, iclass 24, count 2 2006.173.11:33:25.07#ibcon#wrote, iclass 24, count 2 2006.173.11:33:25.07#ibcon#about to read 3, iclass 24, count 2 2006.173.11:33:25.10#ibcon#read 3, iclass 24, count 2 2006.173.11:33:25.10#ibcon#about to read 4, iclass 24, count 2 2006.173.11:33:25.10#ibcon#read 4, iclass 24, count 2 2006.173.11:33:25.10#ibcon#about to read 5, iclass 24, count 2 2006.173.11:33:25.10#ibcon#read 5, iclass 24, count 2 2006.173.11:33:25.10#ibcon#about to read 6, iclass 24, count 2 2006.173.11:33:25.10#ibcon#read 6, iclass 24, count 2 2006.173.11:33:25.10#ibcon#end of sib2, iclass 24, count 2 2006.173.11:33:25.10#ibcon#*after write, iclass 24, count 2 2006.173.11:33:25.10#ibcon#*before return 0, iclass 24, count 2 2006.173.11:33:25.10#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.11:33:25.10#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.11:33:25.10#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.11:33:25.10#ibcon#ireg 7 cls_cnt 0 2006.173.11:33:25.10#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.11:33:25.22#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.11:33:25.22#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.11:33:25.22#ibcon#enter wrdev, iclass 24, count 0 2006.173.11:33:25.22#ibcon#first serial, iclass 24, count 0 2006.173.11:33:25.22#ibcon#enter sib2, iclass 24, count 0 2006.173.11:33:25.22#ibcon#flushed, iclass 24, count 0 2006.173.11:33:25.22#ibcon#about to write, iclass 24, count 0 2006.173.11:33:25.22#ibcon#wrote, iclass 24, count 0 2006.173.11:33:25.22#ibcon#about to read 3, iclass 24, count 0 2006.173.11:33:25.24#ibcon#read 3, iclass 24, count 0 2006.173.11:33:25.24#ibcon#about to read 4, iclass 24, count 0 2006.173.11:33:25.24#ibcon#read 4, iclass 24, count 0 2006.173.11:33:25.24#ibcon#about to read 5, iclass 24, count 0 2006.173.11:33:25.24#ibcon#read 5, iclass 24, count 0 2006.173.11:33:25.24#ibcon#about to read 6, iclass 24, count 0 2006.173.11:33:25.24#ibcon#read 6, iclass 24, count 0 2006.173.11:33:25.24#ibcon#end of sib2, iclass 24, count 0 2006.173.11:33:25.24#ibcon#*mode == 0, iclass 24, count 0 2006.173.11:33:25.24#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.11:33:25.24#ibcon#[27=USB\r\n] 2006.173.11:33:25.24#ibcon#*before write, iclass 24, count 0 2006.173.11:33:25.24#ibcon#enter sib2, iclass 24, count 0 2006.173.11:33:25.24#ibcon#flushed, iclass 24, count 0 2006.173.11:33:25.24#ibcon#about to write, iclass 24, count 0 2006.173.11:33:25.24#ibcon#wrote, iclass 24, count 0 2006.173.11:33:25.24#ibcon#about to read 3, iclass 24, count 0 2006.173.11:33:25.27#ibcon#read 3, iclass 24, count 0 2006.173.11:33:25.27#ibcon#about to read 4, iclass 24, count 0 2006.173.11:33:25.27#ibcon#read 4, iclass 24, count 0 2006.173.11:33:25.27#ibcon#about to read 5, iclass 24, count 0 2006.173.11:33:25.27#ibcon#read 5, iclass 24, count 0 2006.173.11:33:25.27#ibcon#about to read 6, iclass 24, count 0 2006.173.11:33:25.27#ibcon#read 6, iclass 24, count 0 2006.173.11:33:25.27#ibcon#end of sib2, iclass 24, count 0 2006.173.11:33:25.27#ibcon#*after write, iclass 24, count 0 2006.173.11:33:25.27#ibcon#*before return 0, iclass 24, count 0 2006.173.11:33:25.27#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.11:33:25.27#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.11:33:25.27#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.11:33:25.27#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.11:33:25.27$vck44/vblo=8,744.99 2006.173.11:33:25.27#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.11:33:25.27#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.11:33:25.27#ibcon#ireg 17 cls_cnt 0 2006.173.11:33:25.27#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.11:33:25.27#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.11:33:25.27#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.11:33:25.27#ibcon#enter wrdev, iclass 26, count 0 2006.173.11:33:25.27#ibcon#first serial, iclass 26, count 0 2006.173.11:33:25.27#ibcon#enter sib2, iclass 26, count 0 2006.173.11:33:25.27#ibcon#flushed, iclass 26, count 0 2006.173.11:33:25.27#ibcon#about to write, iclass 26, count 0 2006.173.11:33:25.27#ibcon#wrote, iclass 26, count 0 2006.173.11:33:25.27#ibcon#about to read 3, iclass 26, count 0 2006.173.11:33:25.29#ibcon#read 3, iclass 26, count 0 2006.173.11:33:25.29#ibcon#about to read 4, iclass 26, count 0 2006.173.11:33:25.29#ibcon#read 4, iclass 26, count 0 2006.173.11:33:25.29#ibcon#about to read 5, iclass 26, count 0 2006.173.11:33:25.29#ibcon#read 5, iclass 26, count 0 2006.173.11:33:25.29#ibcon#about to read 6, iclass 26, count 0 2006.173.11:33:25.29#ibcon#read 6, iclass 26, count 0 2006.173.11:33:25.29#ibcon#end of sib2, iclass 26, count 0 2006.173.11:33:25.29#ibcon#*mode == 0, iclass 26, count 0 2006.173.11:33:25.29#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.11:33:25.29#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.11:33:25.29#ibcon#*before write, iclass 26, count 0 2006.173.11:33:25.29#ibcon#enter sib2, iclass 26, count 0 2006.173.11:33:25.29#ibcon#flushed, iclass 26, count 0 2006.173.11:33:25.29#ibcon#about to write, iclass 26, count 0 2006.173.11:33:25.29#ibcon#wrote, iclass 26, count 0 2006.173.11:33:25.29#ibcon#about to read 3, iclass 26, count 0 2006.173.11:33:25.33#ibcon#read 3, iclass 26, count 0 2006.173.11:33:25.33#ibcon#about to read 4, iclass 26, count 0 2006.173.11:33:25.33#ibcon#read 4, iclass 26, count 0 2006.173.11:33:25.33#ibcon#about to read 5, iclass 26, count 0 2006.173.11:33:25.33#ibcon#read 5, iclass 26, count 0 2006.173.11:33:25.33#ibcon#about to read 6, iclass 26, count 0 2006.173.11:33:25.33#ibcon#read 6, iclass 26, count 0 2006.173.11:33:25.33#ibcon#end of sib2, iclass 26, count 0 2006.173.11:33:25.33#ibcon#*after write, iclass 26, count 0 2006.173.11:33:25.33#ibcon#*before return 0, iclass 26, count 0 2006.173.11:33:25.33#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.11:33:25.33#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.11:33:25.33#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.11:33:25.33#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.11:33:25.33$vck44/vb=8,4 2006.173.11:33:25.33#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.11:33:25.33#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.11:33:25.33#ibcon#ireg 11 cls_cnt 2 2006.173.11:33:25.33#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.11:33:25.39#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.11:33:25.39#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.11:33:25.39#ibcon#enter wrdev, iclass 28, count 2 2006.173.11:33:25.39#ibcon#first serial, iclass 28, count 2 2006.173.11:33:25.39#ibcon#enter sib2, iclass 28, count 2 2006.173.11:33:25.39#ibcon#flushed, iclass 28, count 2 2006.173.11:33:25.39#ibcon#about to write, iclass 28, count 2 2006.173.11:33:25.39#ibcon#wrote, iclass 28, count 2 2006.173.11:33:25.39#ibcon#about to read 3, iclass 28, count 2 2006.173.11:33:25.41#ibcon#read 3, iclass 28, count 2 2006.173.11:33:25.41#ibcon#about to read 4, iclass 28, count 2 2006.173.11:33:25.41#ibcon#read 4, iclass 28, count 2 2006.173.11:33:25.41#ibcon#about to read 5, iclass 28, count 2 2006.173.11:33:25.41#ibcon#read 5, iclass 28, count 2 2006.173.11:33:25.41#ibcon#about to read 6, iclass 28, count 2 2006.173.11:33:25.41#ibcon#read 6, iclass 28, count 2 2006.173.11:33:25.41#ibcon#end of sib2, iclass 28, count 2 2006.173.11:33:25.41#ibcon#*mode == 0, iclass 28, count 2 2006.173.11:33:25.41#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.11:33:25.41#ibcon#[27=AT08-04\r\n] 2006.173.11:33:25.41#ibcon#*before write, iclass 28, count 2 2006.173.11:33:25.41#ibcon#enter sib2, iclass 28, count 2 2006.173.11:33:25.41#ibcon#flushed, iclass 28, count 2 2006.173.11:33:25.41#ibcon#about to write, iclass 28, count 2 2006.173.11:33:25.41#ibcon#wrote, iclass 28, count 2 2006.173.11:33:25.41#ibcon#about to read 3, iclass 28, count 2 2006.173.11:33:25.44#ibcon#read 3, iclass 28, count 2 2006.173.11:33:25.44#ibcon#about to read 4, iclass 28, count 2 2006.173.11:33:25.44#ibcon#read 4, iclass 28, count 2 2006.173.11:33:25.44#ibcon#about to read 5, iclass 28, count 2 2006.173.11:33:25.44#ibcon#read 5, iclass 28, count 2 2006.173.11:33:25.44#ibcon#about to read 6, iclass 28, count 2 2006.173.11:33:25.44#ibcon#read 6, iclass 28, count 2 2006.173.11:33:25.44#ibcon#end of sib2, iclass 28, count 2 2006.173.11:33:25.44#ibcon#*after write, iclass 28, count 2 2006.173.11:33:25.44#ibcon#*before return 0, iclass 28, count 2 2006.173.11:33:25.44#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.11:33:25.44#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.11:33:25.44#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.11:33:25.44#ibcon#ireg 7 cls_cnt 0 2006.173.11:33:25.44#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.11:33:25.56#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.11:33:25.56#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.11:33:25.56#ibcon#enter wrdev, iclass 28, count 0 2006.173.11:33:25.56#ibcon#first serial, iclass 28, count 0 2006.173.11:33:25.56#ibcon#enter sib2, iclass 28, count 0 2006.173.11:33:25.56#ibcon#flushed, iclass 28, count 0 2006.173.11:33:25.56#ibcon#about to write, iclass 28, count 0 2006.173.11:33:25.56#ibcon#wrote, iclass 28, count 0 2006.173.11:33:25.56#ibcon#about to read 3, iclass 28, count 0 2006.173.11:33:25.58#ibcon#read 3, iclass 28, count 0 2006.173.11:33:25.58#ibcon#about to read 4, iclass 28, count 0 2006.173.11:33:25.58#ibcon#read 4, iclass 28, count 0 2006.173.11:33:25.58#ibcon#about to read 5, iclass 28, count 0 2006.173.11:33:25.58#ibcon#read 5, iclass 28, count 0 2006.173.11:33:25.58#ibcon#about to read 6, iclass 28, count 0 2006.173.11:33:25.58#ibcon#read 6, iclass 28, count 0 2006.173.11:33:25.58#ibcon#end of sib2, iclass 28, count 0 2006.173.11:33:25.58#ibcon#*mode == 0, iclass 28, count 0 2006.173.11:33:25.58#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.11:33:25.58#ibcon#[27=USB\r\n] 2006.173.11:33:25.58#ibcon#*before write, iclass 28, count 0 2006.173.11:33:25.58#ibcon#enter sib2, iclass 28, count 0 2006.173.11:33:25.58#ibcon#flushed, iclass 28, count 0 2006.173.11:33:25.58#ibcon#about to write, iclass 28, count 0 2006.173.11:33:25.58#ibcon#wrote, iclass 28, count 0 2006.173.11:33:25.58#ibcon#about to read 3, iclass 28, count 0 2006.173.11:33:25.61#ibcon#read 3, iclass 28, count 0 2006.173.11:33:25.61#ibcon#about to read 4, iclass 28, count 0 2006.173.11:33:25.61#ibcon#read 4, iclass 28, count 0 2006.173.11:33:25.61#ibcon#about to read 5, iclass 28, count 0 2006.173.11:33:25.61#ibcon#read 5, iclass 28, count 0 2006.173.11:33:25.61#ibcon#about to read 6, iclass 28, count 0 2006.173.11:33:25.61#ibcon#read 6, iclass 28, count 0 2006.173.11:33:25.61#ibcon#end of sib2, iclass 28, count 0 2006.173.11:33:25.61#ibcon#*after write, iclass 28, count 0 2006.173.11:33:25.61#ibcon#*before return 0, iclass 28, count 0 2006.173.11:33:25.61#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.11:33:25.61#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.11:33:25.61#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.11:33:25.61#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.11:33:25.61$vck44/vabw=wide 2006.173.11:33:25.61#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.11:33:25.61#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.11:33:25.61#ibcon#ireg 8 cls_cnt 0 2006.173.11:33:25.61#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.11:33:25.61#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.11:33:25.61#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.11:33:25.61#ibcon#enter wrdev, iclass 30, count 0 2006.173.11:33:25.61#ibcon#first serial, iclass 30, count 0 2006.173.11:33:25.61#ibcon#enter sib2, iclass 30, count 0 2006.173.11:33:25.61#ibcon#flushed, iclass 30, count 0 2006.173.11:33:25.61#ibcon#about to write, iclass 30, count 0 2006.173.11:33:25.61#ibcon#wrote, iclass 30, count 0 2006.173.11:33:25.61#ibcon#about to read 3, iclass 30, count 0 2006.173.11:33:25.63#ibcon#read 3, iclass 30, count 0 2006.173.11:33:25.63#ibcon#about to read 4, iclass 30, count 0 2006.173.11:33:25.63#ibcon#read 4, iclass 30, count 0 2006.173.11:33:25.63#ibcon#about to read 5, iclass 30, count 0 2006.173.11:33:25.63#ibcon#read 5, iclass 30, count 0 2006.173.11:33:25.63#ibcon#about to read 6, iclass 30, count 0 2006.173.11:33:25.63#ibcon#read 6, iclass 30, count 0 2006.173.11:33:25.63#ibcon#end of sib2, iclass 30, count 0 2006.173.11:33:25.63#ibcon#*mode == 0, iclass 30, count 0 2006.173.11:33:25.63#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.11:33:25.63#ibcon#[25=BW32\r\n] 2006.173.11:33:25.63#ibcon#*before write, iclass 30, count 0 2006.173.11:33:25.63#ibcon#enter sib2, iclass 30, count 0 2006.173.11:33:25.63#ibcon#flushed, iclass 30, count 0 2006.173.11:33:25.63#ibcon#about to write, iclass 30, count 0 2006.173.11:33:25.63#ibcon#wrote, iclass 30, count 0 2006.173.11:33:25.63#ibcon#about to read 3, iclass 30, count 0 2006.173.11:33:25.66#ibcon#read 3, iclass 30, count 0 2006.173.11:33:25.66#ibcon#about to read 4, iclass 30, count 0 2006.173.11:33:25.66#ibcon#read 4, iclass 30, count 0 2006.173.11:33:25.66#ibcon#about to read 5, iclass 30, count 0 2006.173.11:33:25.66#ibcon#read 5, iclass 30, count 0 2006.173.11:33:25.66#ibcon#about to read 6, iclass 30, count 0 2006.173.11:33:25.66#ibcon#read 6, iclass 30, count 0 2006.173.11:33:25.66#ibcon#end of sib2, iclass 30, count 0 2006.173.11:33:25.66#ibcon#*after write, iclass 30, count 0 2006.173.11:33:25.66#ibcon#*before return 0, iclass 30, count 0 2006.173.11:33:25.66#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.11:33:25.66#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.11:33:25.66#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.11:33:25.66#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.11:33:25.66$vck44/vbbw=wide 2006.173.11:33:25.66#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.11:33:25.66#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.11:33:25.66#ibcon#ireg 8 cls_cnt 0 2006.173.11:33:25.66#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.11:33:25.73#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.11:33:25.73#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.11:33:25.73#ibcon#enter wrdev, iclass 32, count 0 2006.173.11:33:25.73#ibcon#first serial, iclass 32, count 0 2006.173.11:33:25.73#ibcon#enter sib2, iclass 32, count 0 2006.173.11:33:25.73#ibcon#flushed, iclass 32, count 0 2006.173.11:33:25.73#ibcon#about to write, iclass 32, count 0 2006.173.11:33:25.73#ibcon#wrote, iclass 32, count 0 2006.173.11:33:25.73#ibcon#about to read 3, iclass 32, count 0 2006.173.11:33:25.75#ibcon#read 3, iclass 32, count 0 2006.173.11:33:25.75#ibcon#about to read 4, iclass 32, count 0 2006.173.11:33:25.75#ibcon#read 4, iclass 32, count 0 2006.173.11:33:25.75#ibcon#about to read 5, iclass 32, count 0 2006.173.11:33:25.75#ibcon#read 5, iclass 32, count 0 2006.173.11:33:25.75#ibcon#about to read 6, iclass 32, count 0 2006.173.11:33:25.75#ibcon#read 6, iclass 32, count 0 2006.173.11:33:25.75#ibcon#end of sib2, iclass 32, count 0 2006.173.11:33:25.75#ibcon#*mode == 0, iclass 32, count 0 2006.173.11:33:25.75#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.11:33:25.75#ibcon#[27=BW32\r\n] 2006.173.11:33:25.75#ibcon#*before write, iclass 32, count 0 2006.173.11:33:25.75#ibcon#enter sib2, iclass 32, count 0 2006.173.11:33:25.75#ibcon#flushed, iclass 32, count 0 2006.173.11:33:25.75#ibcon#about to write, iclass 32, count 0 2006.173.11:33:25.75#ibcon#wrote, iclass 32, count 0 2006.173.11:33:25.75#ibcon#about to read 3, iclass 32, count 0 2006.173.11:33:25.78#ibcon#read 3, iclass 32, count 0 2006.173.11:33:25.78#ibcon#about to read 4, iclass 32, count 0 2006.173.11:33:25.78#ibcon#read 4, iclass 32, count 0 2006.173.11:33:25.78#ibcon#about to read 5, iclass 32, count 0 2006.173.11:33:25.78#ibcon#read 5, iclass 32, count 0 2006.173.11:33:25.78#ibcon#about to read 6, iclass 32, count 0 2006.173.11:33:25.78#ibcon#read 6, iclass 32, count 0 2006.173.11:33:25.78#ibcon#end of sib2, iclass 32, count 0 2006.173.11:33:25.78#ibcon#*after write, iclass 32, count 0 2006.173.11:33:25.78#ibcon#*before return 0, iclass 32, count 0 2006.173.11:33:25.78#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.11:33:25.78#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.11:33:25.78#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.11:33:25.78#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.11:33:25.78$setupk4/ifdk4 2006.173.11:33:25.78$ifdk4/lo= 2006.173.11:33:25.78$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.11:33:25.78$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.11:33:25.78$ifdk4/patch= 2006.173.11:33:25.78$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.11:33:25.78$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.11:33:25.78$setupk4/!*+20s 2006.173.11:33:29.00#abcon#<5=/04 1.2 3.1 22.39 931004.1\r\n> 2006.173.11:33:29.02#abcon#{5=INTERFACE CLEAR} 2006.173.11:33:29.08#abcon#[5=S1D000X0/0*\r\n] 2006.173.11:33:39.17#abcon#<5=/04 1.2 3.1 22.39 931004.1\r\n> 2006.173.11:33:39.19#abcon#{5=INTERFACE CLEAR} 2006.173.11:33:39.25#abcon#[5=S1D000X0/0*\r\n] 2006.173.11:33:40.29$setupk4/"tpicd 2006.173.11:33:40.29$setupk4/echo=off 2006.173.11:33:40.29$setupk4/xlog=off 2006.173.11:33:40.29:!2006.173.11:33:51 2006.173.11:33:49.14#trakl#Source acquired 2006.173.11:33:51.00:preob 2006.173.11:33:51.14#flagr#flagr/antenna,acquired 2006.173.11:33:52.14/onsource/TRACKING 2006.173.11:33:52.14:!2006.173.11:34:01 2006.173.11:34:01.00:"tape 2006.173.11:34:01.00:"st=record 2006.173.11:34:01.00:data_valid=on 2006.173.11:34:01.00:midob 2006.173.11:34:01.14/onsource/TRACKING 2006.173.11:34:01.14/wx/22.39,1004.1,93 2006.173.11:34:01.24/cable/+6.5022E-03 2006.173.11:34:02.33/va/01,07,usb,yes,35,38 2006.173.11:34:02.33/va/02,06,usb,yes,35,36 2006.173.11:34:02.33/va/03,05,usb,yes,45,46 2006.173.11:34:02.33/va/04,06,usb,yes,36,38 2006.173.11:34:02.33/va/05,04,usb,yes,28,29 2006.173.11:34:02.33/va/06,03,usb,yes,39,39 2006.173.11:34:02.33/va/07,04,usb,yes,32,33 2006.173.11:34:02.33/va/08,04,usb,yes,27,33 2006.173.11:34:02.56/valo/01,524.99,yes,locked 2006.173.11:34:02.56/valo/02,534.99,yes,locked 2006.173.11:34:02.56/valo/03,564.99,yes,locked 2006.173.11:34:02.56/valo/04,624.99,yes,locked 2006.173.11:34:02.56/valo/05,734.99,yes,locked 2006.173.11:34:02.56/valo/06,814.99,yes,locked 2006.173.11:34:02.56/valo/07,864.99,yes,locked 2006.173.11:34:02.56/valo/08,884.99,yes,locked 2006.173.11:34:03.65/vb/01,04,usb,yes,29,27 2006.173.11:34:03.65/vb/02,04,usb,yes,31,31 2006.173.11:34:03.65/vb/03,04,usb,yes,28,31 2006.173.11:34:03.65/vb/04,04,usb,yes,33,32 2006.173.11:34:03.65/vb/05,04,usb,yes,25,28 2006.173.11:34:03.65/vb/06,04,usb,yes,30,26 2006.173.11:34:03.65/vb/07,04,usb,yes,29,29 2006.173.11:34:03.65/vb/08,04,usb,yes,27,30 2006.173.11:34:03.89/vblo/01,629.99,yes,locked 2006.173.11:34:03.89/vblo/02,634.99,yes,locked 2006.173.11:34:03.89/vblo/03,649.99,yes,locked 2006.173.11:34:03.89/vblo/04,679.99,yes,locked 2006.173.11:34:03.89/vblo/05,709.99,yes,locked 2006.173.11:34:03.89/vblo/06,719.99,yes,locked 2006.173.11:34:03.89/vblo/07,734.99,yes,locked 2006.173.11:34:03.89/vblo/08,744.99,yes,locked 2006.173.11:34:04.04/vabw/8 2006.173.11:34:04.19/vbbw/8 2006.173.11:34:04.28/xfe/off,on,15.5 2006.173.11:34:04.65/ifatt/23,28,28,28 2006.173.11:34:05.08/fmout-gps/S +3.98E-07 2006.173.11:34:05.12:!2006.173.11:35:41 2006.173.11:35:41.00:data_valid=off 2006.173.11:35:41.00:"et 2006.173.11:35:41.00:!+3s 2006.173.11:35:44.01:"tape 2006.173.11:35:44.01:postob 2006.173.11:35:44.09/cable/+6.5035E-03 2006.173.11:35:44.09/wx/22.38,1004.3,93 2006.173.11:35:45.08/fmout-gps/S +3.98E-07 2006.173.11:35:45.08:scan_name=173-1137,jd0606,40 2006.173.11:35:45.08:source=1741-038,174358.86,-035004.6,2000.0,cw 2006.173.11:35:46.14#flagr#flagr/antenna,new-source 2006.173.11:35:46.14:checkk5 2006.173.11:35:46.50/chk_autoobs//k5ts1/ autoobs is running! 2006.173.11:35:46.90/chk_autoobs//k5ts2/ autoobs is running! 2006.173.11:35:47.31/chk_autoobs//k5ts3/ autoobs is running! 2006.173.11:35:47.71/chk_autoobs//k5ts4/ autoobs is running! 2006.173.11:35:48.11/chk_obsdata//k5ts1/T1731134??a.dat file size is correct (nominal:400MB, actual:396MB). 2006.173.11:35:48.52/chk_obsdata//k5ts2/T1731134??b.dat file size is correct (nominal:400MB, actual:396MB). 2006.173.11:35:48.91/chk_obsdata//k5ts3/T1731134??c.dat file size is correct (nominal:400MB, actual:396MB). 2006.173.11:35:49.31/chk_obsdata//k5ts4/T1731134??d.dat file size is correct (nominal:400MB, actual:396MB). 2006.173.11:35:50.04/k5log//k5ts1_log_newline 2006.173.11:35:50.73/k5log//k5ts2_log_newline 2006.173.11:35:51.45/k5log//k5ts3_log_newline 2006.173.11:35:52.15/k5log//k5ts4_log_newline 2006.173.11:35:52.17/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.11:35:52.17:setupk4=1 2006.173.11:35:52.17$setupk4/echo=on 2006.173.11:35:52.17$setupk4/pcalon 2006.173.11:35:52.17$pcalon/"no phase cal control is implemented here 2006.173.11:35:52.17$setupk4/"tpicd=stop 2006.173.11:35:52.17$setupk4/"rec=synch_on 2006.173.11:35:52.17$setupk4/"rec_mode=128 2006.173.11:35:52.17$setupk4/!* 2006.173.11:35:52.17$setupk4/recpk4 2006.173.11:35:52.17$recpk4/recpatch= 2006.173.11:35:52.18$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.11:35:52.18$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.11:35:52.18$setupk4/vck44 2006.173.11:35:52.18$vck44/valo=1,524.99 2006.173.11:35:52.18#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.11:35:52.18#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.11:35:52.18#ibcon#ireg 17 cls_cnt 0 2006.173.11:35:52.18#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.11:35:52.18#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.11:35:52.18#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.11:35:52.18#ibcon#enter wrdev, iclass 25, count 0 2006.173.11:35:52.18#ibcon#first serial, iclass 25, count 0 2006.173.11:35:52.18#ibcon#enter sib2, iclass 25, count 0 2006.173.11:35:52.18#ibcon#flushed, iclass 25, count 0 2006.173.11:35:52.18#ibcon#about to write, iclass 25, count 0 2006.173.11:35:52.18#ibcon#wrote, iclass 25, count 0 2006.173.11:35:52.18#ibcon#about to read 3, iclass 25, count 0 2006.173.11:35:52.20#ibcon#read 3, iclass 25, count 0 2006.173.11:35:52.20#ibcon#about to read 4, iclass 25, count 0 2006.173.11:35:52.20#ibcon#read 4, iclass 25, count 0 2006.173.11:35:52.20#ibcon#about to read 5, iclass 25, count 0 2006.173.11:35:52.20#ibcon#read 5, iclass 25, count 0 2006.173.11:35:52.20#ibcon#about to read 6, iclass 25, count 0 2006.173.11:35:52.20#ibcon#read 6, iclass 25, count 0 2006.173.11:35:52.20#ibcon#end of sib2, iclass 25, count 0 2006.173.11:35:52.20#ibcon#*mode == 0, iclass 25, count 0 2006.173.11:35:52.20#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.11:35:52.20#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.11:35:52.20#ibcon#*before write, iclass 25, count 0 2006.173.11:35:52.20#ibcon#enter sib2, iclass 25, count 0 2006.173.11:35:52.20#ibcon#flushed, iclass 25, count 0 2006.173.11:35:52.20#ibcon#about to write, iclass 25, count 0 2006.173.11:35:52.20#ibcon#wrote, iclass 25, count 0 2006.173.11:35:52.20#ibcon#about to read 3, iclass 25, count 0 2006.173.11:35:52.25#ibcon#read 3, iclass 25, count 0 2006.173.11:35:52.25#ibcon#about to read 4, iclass 25, count 0 2006.173.11:35:52.25#ibcon#read 4, iclass 25, count 0 2006.173.11:35:52.25#ibcon#about to read 5, iclass 25, count 0 2006.173.11:35:52.25#ibcon#read 5, iclass 25, count 0 2006.173.11:35:52.25#ibcon#about to read 6, iclass 25, count 0 2006.173.11:35:52.25#ibcon#read 6, iclass 25, count 0 2006.173.11:35:52.25#ibcon#end of sib2, iclass 25, count 0 2006.173.11:35:52.25#ibcon#*after write, iclass 25, count 0 2006.173.11:35:52.25#ibcon#*before return 0, iclass 25, count 0 2006.173.11:35:52.25#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.11:35:52.25#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.11:35:52.25#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.11:35:52.25#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.11:35:52.25$vck44/va=1,7 2006.173.11:35:52.25#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.11:35:52.25#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.11:35:52.25#ibcon#ireg 11 cls_cnt 2 2006.173.11:35:52.25#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.11:35:52.25#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.11:35:52.25#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.11:35:52.25#ibcon#enter wrdev, iclass 27, count 2 2006.173.11:35:52.25#ibcon#first serial, iclass 27, count 2 2006.173.11:35:52.25#ibcon#enter sib2, iclass 27, count 2 2006.173.11:35:52.25#ibcon#flushed, iclass 27, count 2 2006.173.11:35:52.25#ibcon#about to write, iclass 27, count 2 2006.173.11:35:52.25#ibcon#wrote, iclass 27, count 2 2006.173.11:35:52.25#ibcon#about to read 3, iclass 27, count 2 2006.173.11:35:52.27#ibcon#read 3, iclass 27, count 2 2006.173.11:35:52.27#ibcon#about to read 4, iclass 27, count 2 2006.173.11:35:52.27#ibcon#read 4, iclass 27, count 2 2006.173.11:35:52.27#ibcon#about to read 5, iclass 27, count 2 2006.173.11:35:52.27#ibcon#read 5, iclass 27, count 2 2006.173.11:35:52.27#ibcon#about to read 6, iclass 27, count 2 2006.173.11:35:52.27#ibcon#read 6, iclass 27, count 2 2006.173.11:35:52.27#ibcon#end of sib2, iclass 27, count 2 2006.173.11:35:52.27#ibcon#*mode == 0, iclass 27, count 2 2006.173.11:35:52.27#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.11:35:52.27#ibcon#[25=AT01-07\r\n] 2006.173.11:35:52.27#ibcon#*before write, iclass 27, count 2 2006.173.11:35:52.27#ibcon#enter sib2, iclass 27, count 2 2006.173.11:35:52.27#ibcon#flushed, iclass 27, count 2 2006.173.11:35:52.27#ibcon#about to write, iclass 27, count 2 2006.173.11:35:52.27#ibcon#wrote, iclass 27, count 2 2006.173.11:35:52.27#ibcon#about to read 3, iclass 27, count 2 2006.173.11:35:52.30#ibcon#read 3, iclass 27, count 2 2006.173.11:35:52.30#ibcon#about to read 4, iclass 27, count 2 2006.173.11:35:52.30#ibcon#read 4, iclass 27, count 2 2006.173.11:35:52.30#ibcon#about to read 5, iclass 27, count 2 2006.173.11:35:52.30#ibcon#read 5, iclass 27, count 2 2006.173.11:35:52.30#ibcon#about to read 6, iclass 27, count 2 2006.173.11:35:52.30#ibcon#read 6, iclass 27, count 2 2006.173.11:35:52.30#ibcon#end of sib2, iclass 27, count 2 2006.173.11:35:52.30#ibcon#*after write, iclass 27, count 2 2006.173.11:35:52.30#ibcon#*before return 0, iclass 27, count 2 2006.173.11:35:52.30#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.11:35:52.30#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.11:35:52.30#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.11:35:52.30#ibcon#ireg 7 cls_cnt 0 2006.173.11:35:52.30#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.11:35:52.42#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.11:35:52.42#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.11:35:52.42#ibcon#enter wrdev, iclass 27, count 0 2006.173.11:35:52.42#ibcon#first serial, iclass 27, count 0 2006.173.11:35:52.42#ibcon#enter sib2, iclass 27, count 0 2006.173.11:35:52.42#ibcon#flushed, iclass 27, count 0 2006.173.11:35:52.42#ibcon#about to write, iclass 27, count 0 2006.173.11:35:52.42#ibcon#wrote, iclass 27, count 0 2006.173.11:35:52.42#ibcon#about to read 3, iclass 27, count 0 2006.173.11:35:52.44#ibcon#read 3, iclass 27, count 0 2006.173.11:35:52.44#ibcon#about to read 4, iclass 27, count 0 2006.173.11:35:52.44#ibcon#read 4, iclass 27, count 0 2006.173.11:35:52.44#ibcon#about to read 5, iclass 27, count 0 2006.173.11:35:52.44#ibcon#read 5, iclass 27, count 0 2006.173.11:35:52.44#ibcon#about to read 6, iclass 27, count 0 2006.173.11:35:52.44#ibcon#read 6, iclass 27, count 0 2006.173.11:35:52.44#ibcon#end of sib2, iclass 27, count 0 2006.173.11:35:52.44#ibcon#*mode == 0, iclass 27, count 0 2006.173.11:35:52.44#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.11:35:52.44#ibcon#[25=USB\r\n] 2006.173.11:35:52.44#ibcon#*before write, iclass 27, count 0 2006.173.11:35:52.44#ibcon#enter sib2, iclass 27, count 0 2006.173.11:35:52.44#ibcon#flushed, iclass 27, count 0 2006.173.11:35:52.44#ibcon#about to write, iclass 27, count 0 2006.173.11:35:52.44#ibcon#wrote, iclass 27, count 0 2006.173.11:35:52.44#ibcon#about to read 3, iclass 27, count 0 2006.173.11:35:52.47#ibcon#read 3, iclass 27, count 0 2006.173.11:35:52.47#ibcon#about to read 4, iclass 27, count 0 2006.173.11:35:52.47#ibcon#read 4, iclass 27, count 0 2006.173.11:35:52.47#ibcon#about to read 5, iclass 27, count 0 2006.173.11:35:52.47#ibcon#read 5, iclass 27, count 0 2006.173.11:35:52.47#ibcon#about to read 6, iclass 27, count 0 2006.173.11:35:52.47#ibcon#read 6, iclass 27, count 0 2006.173.11:35:52.47#ibcon#end of sib2, iclass 27, count 0 2006.173.11:35:52.47#ibcon#*after write, iclass 27, count 0 2006.173.11:35:52.47#ibcon#*before return 0, iclass 27, count 0 2006.173.11:35:52.47#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.11:35:52.47#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.11:35:52.47#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.11:35:52.47#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.11:35:52.47$vck44/valo=2,534.99 2006.173.11:35:52.47#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.11:35:52.47#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.11:35:52.47#ibcon#ireg 17 cls_cnt 0 2006.173.11:35:52.47#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.11:35:52.47#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.11:35:52.47#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.11:35:52.47#ibcon#enter wrdev, iclass 29, count 0 2006.173.11:35:52.47#ibcon#first serial, iclass 29, count 0 2006.173.11:35:52.47#ibcon#enter sib2, iclass 29, count 0 2006.173.11:35:52.47#ibcon#flushed, iclass 29, count 0 2006.173.11:35:52.47#ibcon#about to write, iclass 29, count 0 2006.173.11:35:52.47#ibcon#wrote, iclass 29, count 0 2006.173.11:35:52.47#ibcon#about to read 3, iclass 29, count 0 2006.173.11:35:52.49#ibcon#read 3, iclass 29, count 0 2006.173.11:35:52.49#ibcon#about to read 4, iclass 29, count 0 2006.173.11:35:52.49#ibcon#read 4, iclass 29, count 0 2006.173.11:35:52.49#ibcon#about to read 5, iclass 29, count 0 2006.173.11:35:52.49#ibcon#read 5, iclass 29, count 0 2006.173.11:35:52.49#ibcon#about to read 6, iclass 29, count 0 2006.173.11:35:52.49#ibcon#read 6, iclass 29, count 0 2006.173.11:35:52.49#ibcon#end of sib2, iclass 29, count 0 2006.173.11:35:52.49#ibcon#*mode == 0, iclass 29, count 0 2006.173.11:35:52.49#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.11:35:52.49#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.11:35:52.49#ibcon#*before write, iclass 29, count 0 2006.173.11:35:52.49#ibcon#enter sib2, iclass 29, count 0 2006.173.11:35:52.49#ibcon#flushed, iclass 29, count 0 2006.173.11:35:52.49#ibcon#about to write, iclass 29, count 0 2006.173.11:35:52.49#ibcon#wrote, iclass 29, count 0 2006.173.11:35:52.49#ibcon#about to read 3, iclass 29, count 0 2006.173.11:35:52.53#ibcon#read 3, iclass 29, count 0 2006.173.11:35:52.53#ibcon#about to read 4, iclass 29, count 0 2006.173.11:35:52.53#ibcon#read 4, iclass 29, count 0 2006.173.11:35:52.53#ibcon#about to read 5, iclass 29, count 0 2006.173.11:35:52.53#ibcon#read 5, iclass 29, count 0 2006.173.11:35:52.53#ibcon#about to read 6, iclass 29, count 0 2006.173.11:35:52.53#ibcon#read 6, iclass 29, count 0 2006.173.11:35:52.53#ibcon#end of sib2, iclass 29, count 0 2006.173.11:35:52.53#ibcon#*after write, iclass 29, count 0 2006.173.11:35:52.53#ibcon#*before return 0, iclass 29, count 0 2006.173.11:35:52.53#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.11:35:52.53#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.11:35:52.53#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.11:35:52.53#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.11:35:52.53$vck44/va=2,6 2006.173.11:35:52.53#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.11:35:52.53#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.11:35:52.53#ibcon#ireg 11 cls_cnt 2 2006.173.11:35:52.53#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.11:35:52.59#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.11:35:52.59#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.11:35:52.59#ibcon#enter wrdev, iclass 31, count 2 2006.173.11:35:52.59#ibcon#first serial, iclass 31, count 2 2006.173.11:35:52.59#ibcon#enter sib2, iclass 31, count 2 2006.173.11:35:52.59#ibcon#flushed, iclass 31, count 2 2006.173.11:35:52.59#ibcon#about to write, iclass 31, count 2 2006.173.11:35:52.59#ibcon#wrote, iclass 31, count 2 2006.173.11:35:52.59#ibcon#about to read 3, iclass 31, count 2 2006.173.11:35:52.61#ibcon#read 3, iclass 31, count 2 2006.173.11:35:52.61#ibcon#about to read 4, iclass 31, count 2 2006.173.11:35:52.61#ibcon#read 4, iclass 31, count 2 2006.173.11:35:52.61#ibcon#about to read 5, iclass 31, count 2 2006.173.11:35:52.61#ibcon#read 5, iclass 31, count 2 2006.173.11:35:52.61#ibcon#about to read 6, iclass 31, count 2 2006.173.11:35:52.61#ibcon#read 6, iclass 31, count 2 2006.173.11:35:52.61#ibcon#end of sib2, iclass 31, count 2 2006.173.11:35:52.61#ibcon#*mode == 0, iclass 31, count 2 2006.173.11:35:52.61#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.11:35:52.61#ibcon#[25=AT02-06\r\n] 2006.173.11:35:52.61#ibcon#*before write, iclass 31, count 2 2006.173.11:35:52.61#ibcon#enter sib2, iclass 31, count 2 2006.173.11:35:52.61#ibcon#flushed, iclass 31, count 2 2006.173.11:35:52.61#ibcon#about to write, iclass 31, count 2 2006.173.11:35:52.61#ibcon#wrote, iclass 31, count 2 2006.173.11:35:52.61#ibcon#about to read 3, iclass 31, count 2 2006.173.11:35:52.64#ibcon#read 3, iclass 31, count 2 2006.173.11:35:52.64#ibcon#about to read 4, iclass 31, count 2 2006.173.11:35:52.64#ibcon#read 4, iclass 31, count 2 2006.173.11:35:52.64#ibcon#about to read 5, iclass 31, count 2 2006.173.11:35:52.64#ibcon#read 5, iclass 31, count 2 2006.173.11:35:52.64#ibcon#about to read 6, iclass 31, count 2 2006.173.11:35:52.64#ibcon#read 6, iclass 31, count 2 2006.173.11:35:52.64#ibcon#end of sib2, iclass 31, count 2 2006.173.11:35:52.64#ibcon#*after write, iclass 31, count 2 2006.173.11:35:52.64#ibcon#*before return 0, iclass 31, count 2 2006.173.11:35:52.64#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.11:35:52.64#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.11:35:52.64#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.11:35:52.64#ibcon#ireg 7 cls_cnt 0 2006.173.11:35:52.64#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.11:35:52.76#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.11:35:52.76#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.11:35:52.76#ibcon#enter wrdev, iclass 31, count 0 2006.173.11:35:52.76#ibcon#first serial, iclass 31, count 0 2006.173.11:35:52.76#ibcon#enter sib2, iclass 31, count 0 2006.173.11:35:52.76#ibcon#flushed, iclass 31, count 0 2006.173.11:35:52.76#ibcon#about to write, iclass 31, count 0 2006.173.11:35:52.76#ibcon#wrote, iclass 31, count 0 2006.173.11:35:52.76#ibcon#about to read 3, iclass 31, count 0 2006.173.11:35:52.78#ibcon#read 3, iclass 31, count 0 2006.173.11:35:52.78#ibcon#about to read 4, iclass 31, count 0 2006.173.11:35:52.78#ibcon#read 4, iclass 31, count 0 2006.173.11:35:52.78#ibcon#about to read 5, iclass 31, count 0 2006.173.11:35:52.78#ibcon#read 5, iclass 31, count 0 2006.173.11:35:52.78#ibcon#about to read 6, iclass 31, count 0 2006.173.11:35:52.78#ibcon#read 6, iclass 31, count 0 2006.173.11:35:52.78#ibcon#end of sib2, iclass 31, count 0 2006.173.11:35:52.78#ibcon#*mode == 0, iclass 31, count 0 2006.173.11:35:52.78#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.11:35:52.78#ibcon#[25=USB\r\n] 2006.173.11:35:52.78#ibcon#*before write, iclass 31, count 0 2006.173.11:35:52.78#ibcon#enter sib2, iclass 31, count 0 2006.173.11:35:52.78#ibcon#flushed, iclass 31, count 0 2006.173.11:35:52.78#ibcon#about to write, iclass 31, count 0 2006.173.11:35:52.78#ibcon#wrote, iclass 31, count 0 2006.173.11:35:52.78#ibcon#about to read 3, iclass 31, count 0 2006.173.11:35:52.81#ibcon#read 3, iclass 31, count 0 2006.173.11:35:52.81#ibcon#about to read 4, iclass 31, count 0 2006.173.11:35:52.81#ibcon#read 4, iclass 31, count 0 2006.173.11:35:52.81#ibcon#about to read 5, iclass 31, count 0 2006.173.11:35:52.81#ibcon#read 5, iclass 31, count 0 2006.173.11:35:52.81#ibcon#about to read 6, iclass 31, count 0 2006.173.11:35:52.81#ibcon#read 6, iclass 31, count 0 2006.173.11:35:52.81#ibcon#end of sib2, iclass 31, count 0 2006.173.11:35:52.81#ibcon#*after write, iclass 31, count 0 2006.173.11:35:52.81#ibcon#*before return 0, iclass 31, count 0 2006.173.11:35:52.81#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.11:35:52.81#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.11:35:52.81#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.11:35:52.81#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.11:35:52.81$vck44/valo=3,564.99 2006.173.11:35:52.81#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.11:35:52.81#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.11:35:52.81#ibcon#ireg 17 cls_cnt 0 2006.173.11:35:52.81#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.11:35:52.81#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.11:35:52.81#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.11:35:52.81#ibcon#enter wrdev, iclass 33, count 0 2006.173.11:35:52.81#ibcon#first serial, iclass 33, count 0 2006.173.11:35:52.81#ibcon#enter sib2, iclass 33, count 0 2006.173.11:35:52.81#ibcon#flushed, iclass 33, count 0 2006.173.11:35:52.81#ibcon#about to write, iclass 33, count 0 2006.173.11:35:52.81#ibcon#wrote, iclass 33, count 0 2006.173.11:35:52.81#ibcon#about to read 3, iclass 33, count 0 2006.173.11:35:52.83#ibcon#read 3, iclass 33, count 0 2006.173.11:35:52.83#ibcon#about to read 4, iclass 33, count 0 2006.173.11:35:52.83#ibcon#read 4, iclass 33, count 0 2006.173.11:35:52.83#ibcon#about to read 5, iclass 33, count 0 2006.173.11:35:52.83#ibcon#read 5, iclass 33, count 0 2006.173.11:35:52.83#ibcon#about to read 6, iclass 33, count 0 2006.173.11:35:52.83#ibcon#read 6, iclass 33, count 0 2006.173.11:35:52.83#ibcon#end of sib2, iclass 33, count 0 2006.173.11:35:52.83#ibcon#*mode == 0, iclass 33, count 0 2006.173.11:35:52.83#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.11:35:52.83#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.11:35:52.83#ibcon#*before write, iclass 33, count 0 2006.173.11:35:52.83#ibcon#enter sib2, iclass 33, count 0 2006.173.11:35:52.83#ibcon#flushed, iclass 33, count 0 2006.173.11:35:52.83#ibcon#about to write, iclass 33, count 0 2006.173.11:35:52.83#ibcon#wrote, iclass 33, count 0 2006.173.11:35:52.83#ibcon#about to read 3, iclass 33, count 0 2006.173.11:35:52.87#ibcon#read 3, iclass 33, count 0 2006.173.11:35:52.87#ibcon#about to read 4, iclass 33, count 0 2006.173.11:35:52.87#ibcon#read 4, iclass 33, count 0 2006.173.11:35:52.87#ibcon#about to read 5, iclass 33, count 0 2006.173.11:35:52.87#ibcon#read 5, iclass 33, count 0 2006.173.11:35:52.87#ibcon#about to read 6, iclass 33, count 0 2006.173.11:35:52.87#ibcon#read 6, iclass 33, count 0 2006.173.11:35:52.87#ibcon#end of sib2, iclass 33, count 0 2006.173.11:35:52.87#ibcon#*after write, iclass 33, count 0 2006.173.11:35:52.87#ibcon#*before return 0, iclass 33, count 0 2006.173.11:35:52.87#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.11:35:52.87#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.11:35:52.87#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.11:35:52.87#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.11:35:52.87$vck44/va=3,5 2006.173.11:35:52.87#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.11:35:52.87#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.11:35:52.87#ibcon#ireg 11 cls_cnt 2 2006.173.11:35:52.87#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.11:35:52.93#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.11:35:52.93#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.11:35:52.93#ibcon#enter wrdev, iclass 35, count 2 2006.173.11:35:52.93#ibcon#first serial, iclass 35, count 2 2006.173.11:35:52.93#ibcon#enter sib2, iclass 35, count 2 2006.173.11:35:52.93#ibcon#flushed, iclass 35, count 2 2006.173.11:35:52.93#ibcon#about to write, iclass 35, count 2 2006.173.11:35:52.93#ibcon#wrote, iclass 35, count 2 2006.173.11:35:52.93#ibcon#about to read 3, iclass 35, count 2 2006.173.11:35:52.95#ibcon#read 3, iclass 35, count 2 2006.173.11:35:52.95#ibcon#about to read 4, iclass 35, count 2 2006.173.11:35:52.95#ibcon#read 4, iclass 35, count 2 2006.173.11:35:52.95#ibcon#about to read 5, iclass 35, count 2 2006.173.11:35:52.95#ibcon#read 5, iclass 35, count 2 2006.173.11:35:52.95#ibcon#about to read 6, iclass 35, count 2 2006.173.11:35:52.95#ibcon#read 6, iclass 35, count 2 2006.173.11:35:52.95#ibcon#end of sib2, iclass 35, count 2 2006.173.11:35:52.95#ibcon#*mode == 0, iclass 35, count 2 2006.173.11:35:52.95#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.11:35:52.95#ibcon#[25=AT03-05\r\n] 2006.173.11:35:52.95#ibcon#*before write, iclass 35, count 2 2006.173.11:35:52.95#ibcon#enter sib2, iclass 35, count 2 2006.173.11:35:52.95#ibcon#flushed, iclass 35, count 2 2006.173.11:35:52.95#ibcon#about to write, iclass 35, count 2 2006.173.11:35:52.95#ibcon#wrote, iclass 35, count 2 2006.173.11:35:52.95#ibcon#about to read 3, iclass 35, count 2 2006.173.11:35:52.98#ibcon#read 3, iclass 35, count 2 2006.173.11:35:52.98#ibcon#about to read 4, iclass 35, count 2 2006.173.11:35:52.98#ibcon#read 4, iclass 35, count 2 2006.173.11:35:52.98#ibcon#about to read 5, iclass 35, count 2 2006.173.11:35:52.98#ibcon#read 5, iclass 35, count 2 2006.173.11:35:52.98#ibcon#about to read 6, iclass 35, count 2 2006.173.11:35:52.98#ibcon#read 6, iclass 35, count 2 2006.173.11:35:52.98#ibcon#end of sib2, iclass 35, count 2 2006.173.11:35:52.98#ibcon#*after write, iclass 35, count 2 2006.173.11:35:52.98#ibcon#*before return 0, iclass 35, count 2 2006.173.11:35:52.98#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.11:35:52.98#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.11:35:52.98#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.11:35:52.98#ibcon#ireg 7 cls_cnt 0 2006.173.11:35:52.98#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.11:35:53.10#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.11:35:53.10#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.11:35:53.10#ibcon#enter wrdev, iclass 35, count 0 2006.173.11:35:53.10#ibcon#first serial, iclass 35, count 0 2006.173.11:35:53.10#ibcon#enter sib2, iclass 35, count 0 2006.173.11:35:53.10#ibcon#flushed, iclass 35, count 0 2006.173.11:35:53.10#ibcon#about to write, iclass 35, count 0 2006.173.11:35:53.10#ibcon#wrote, iclass 35, count 0 2006.173.11:35:53.10#ibcon#about to read 3, iclass 35, count 0 2006.173.11:35:53.12#ibcon#read 3, iclass 35, count 0 2006.173.11:35:53.12#ibcon#about to read 4, iclass 35, count 0 2006.173.11:35:53.12#ibcon#read 4, iclass 35, count 0 2006.173.11:35:53.12#ibcon#about to read 5, iclass 35, count 0 2006.173.11:35:53.12#ibcon#read 5, iclass 35, count 0 2006.173.11:35:53.12#ibcon#about to read 6, iclass 35, count 0 2006.173.11:35:53.12#ibcon#read 6, iclass 35, count 0 2006.173.11:35:53.12#ibcon#end of sib2, iclass 35, count 0 2006.173.11:35:53.12#ibcon#*mode == 0, iclass 35, count 0 2006.173.11:35:53.12#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.11:35:53.12#ibcon#[25=USB\r\n] 2006.173.11:35:53.12#ibcon#*before write, iclass 35, count 0 2006.173.11:35:53.12#ibcon#enter sib2, iclass 35, count 0 2006.173.11:35:53.12#ibcon#flushed, iclass 35, count 0 2006.173.11:35:53.12#ibcon#about to write, iclass 35, count 0 2006.173.11:35:53.12#ibcon#wrote, iclass 35, count 0 2006.173.11:35:53.12#ibcon#about to read 3, iclass 35, count 0 2006.173.11:35:53.15#ibcon#read 3, iclass 35, count 0 2006.173.11:35:53.15#ibcon#about to read 4, iclass 35, count 0 2006.173.11:35:53.15#ibcon#read 4, iclass 35, count 0 2006.173.11:35:53.15#ibcon#about to read 5, iclass 35, count 0 2006.173.11:35:53.15#ibcon#read 5, iclass 35, count 0 2006.173.11:35:53.15#ibcon#about to read 6, iclass 35, count 0 2006.173.11:35:53.15#ibcon#read 6, iclass 35, count 0 2006.173.11:35:53.15#ibcon#end of sib2, iclass 35, count 0 2006.173.11:35:53.15#ibcon#*after write, iclass 35, count 0 2006.173.11:35:53.15#ibcon#*before return 0, iclass 35, count 0 2006.173.11:35:53.15#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.11:35:53.15#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.11:35:53.15#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.11:35:53.15#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.11:35:53.15$vck44/valo=4,624.99 2006.173.11:35:53.15#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.11:35:53.15#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.11:35:53.15#ibcon#ireg 17 cls_cnt 0 2006.173.11:35:53.15#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.11:35:53.15#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.11:35:53.15#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.11:35:53.15#ibcon#enter wrdev, iclass 37, count 0 2006.173.11:35:53.15#ibcon#first serial, iclass 37, count 0 2006.173.11:35:53.15#ibcon#enter sib2, iclass 37, count 0 2006.173.11:35:53.15#ibcon#flushed, iclass 37, count 0 2006.173.11:35:53.15#ibcon#about to write, iclass 37, count 0 2006.173.11:35:53.15#ibcon#wrote, iclass 37, count 0 2006.173.11:35:53.15#ibcon#about to read 3, iclass 37, count 0 2006.173.11:35:53.17#ibcon#read 3, iclass 37, count 0 2006.173.11:35:53.17#ibcon#about to read 4, iclass 37, count 0 2006.173.11:35:53.17#ibcon#read 4, iclass 37, count 0 2006.173.11:35:53.17#ibcon#about to read 5, iclass 37, count 0 2006.173.11:35:53.17#ibcon#read 5, iclass 37, count 0 2006.173.11:35:53.17#ibcon#about to read 6, iclass 37, count 0 2006.173.11:35:53.17#ibcon#read 6, iclass 37, count 0 2006.173.11:35:53.17#ibcon#end of sib2, iclass 37, count 0 2006.173.11:35:53.17#ibcon#*mode == 0, iclass 37, count 0 2006.173.11:35:53.17#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.11:35:53.17#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.11:35:53.17#ibcon#*before write, iclass 37, count 0 2006.173.11:35:53.17#ibcon#enter sib2, iclass 37, count 0 2006.173.11:35:53.17#ibcon#flushed, iclass 37, count 0 2006.173.11:35:53.17#ibcon#about to write, iclass 37, count 0 2006.173.11:35:53.17#ibcon#wrote, iclass 37, count 0 2006.173.11:35:53.17#ibcon#about to read 3, iclass 37, count 0 2006.173.11:35:53.21#ibcon#read 3, iclass 37, count 0 2006.173.11:35:53.21#ibcon#about to read 4, iclass 37, count 0 2006.173.11:35:53.21#ibcon#read 4, iclass 37, count 0 2006.173.11:35:53.21#ibcon#about to read 5, iclass 37, count 0 2006.173.11:35:53.21#ibcon#read 5, iclass 37, count 0 2006.173.11:35:53.21#ibcon#about to read 6, iclass 37, count 0 2006.173.11:35:53.21#ibcon#read 6, iclass 37, count 0 2006.173.11:35:53.21#ibcon#end of sib2, iclass 37, count 0 2006.173.11:35:53.21#ibcon#*after write, iclass 37, count 0 2006.173.11:35:53.21#ibcon#*before return 0, iclass 37, count 0 2006.173.11:35:53.21#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.11:35:53.21#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.11:35:53.21#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.11:35:53.21#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.11:35:53.21$vck44/va=4,6 2006.173.11:35:53.21#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.11:35:53.21#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.11:35:53.21#ibcon#ireg 11 cls_cnt 2 2006.173.11:35:53.21#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.11:35:53.27#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.11:35:53.27#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.11:35:53.27#ibcon#enter wrdev, iclass 39, count 2 2006.173.11:35:53.27#ibcon#first serial, iclass 39, count 2 2006.173.11:35:53.27#ibcon#enter sib2, iclass 39, count 2 2006.173.11:35:53.27#ibcon#flushed, iclass 39, count 2 2006.173.11:35:53.27#ibcon#about to write, iclass 39, count 2 2006.173.11:35:53.27#ibcon#wrote, iclass 39, count 2 2006.173.11:35:53.27#ibcon#about to read 3, iclass 39, count 2 2006.173.11:35:53.29#ibcon#read 3, iclass 39, count 2 2006.173.11:35:53.29#ibcon#about to read 4, iclass 39, count 2 2006.173.11:35:53.29#ibcon#read 4, iclass 39, count 2 2006.173.11:35:53.29#ibcon#about to read 5, iclass 39, count 2 2006.173.11:35:53.29#ibcon#read 5, iclass 39, count 2 2006.173.11:35:53.29#ibcon#about to read 6, iclass 39, count 2 2006.173.11:35:53.29#ibcon#read 6, iclass 39, count 2 2006.173.11:35:53.29#ibcon#end of sib2, iclass 39, count 2 2006.173.11:35:53.29#ibcon#*mode == 0, iclass 39, count 2 2006.173.11:35:53.29#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.11:35:53.29#ibcon#[25=AT04-06\r\n] 2006.173.11:35:53.29#ibcon#*before write, iclass 39, count 2 2006.173.11:35:53.29#ibcon#enter sib2, iclass 39, count 2 2006.173.11:35:53.29#ibcon#flushed, iclass 39, count 2 2006.173.11:35:53.29#ibcon#about to write, iclass 39, count 2 2006.173.11:35:53.29#ibcon#wrote, iclass 39, count 2 2006.173.11:35:53.29#ibcon#about to read 3, iclass 39, count 2 2006.173.11:35:53.32#ibcon#read 3, iclass 39, count 2 2006.173.11:35:53.32#ibcon#about to read 4, iclass 39, count 2 2006.173.11:35:53.32#ibcon#read 4, iclass 39, count 2 2006.173.11:35:53.32#ibcon#about to read 5, iclass 39, count 2 2006.173.11:35:53.32#ibcon#read 5, iclass 39, count 2 2006.173.11:35:53.32#ibcon#about to read 6, iclass 39, count 2 2006.173.11:35:53.32#ibcon#read 6, iclass 39, count 2 2006.173.11:35:53.32#ibcon#end of sib2, iclass 39, count 2 2006.173.11:35:53.32#ibcon#*after write, iclass 39, count 2 2006.173.11:35:53.32#ibcon#*before return 0, iclass 39, count 2 2006.173.11:35:53.32#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.11:35:53.32#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.11:35:53.32#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.11:35:53.32#ibcon#ireg 7 cls_cnt 0 2006.173.11:35:53.32#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.11:35:53.44#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.11:35:53.44#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.11:35:53.44#ibcon#enter wrdev, iclass 39, count 0 2006.173.11:35:53.44#ibcon#first serial, iclass 39, count 0 2006.173.11:35:53.44#ibcon#enter sib2, iclass 39, count 0 2006.173.11:35:53.44#ibcon#flushed, iclass 39, count 0 2006.173.11:35:53.44#ibcon#about to write, iclass 39, count 0 2006.173.11:35:53.44#ibcon#wrote, iclass 39, count 0 2006.173.11:35:53.44#ibcon#about to read 3, iclass 39, count 0 2006.173.11:35:53.46#ibcon#read 3, iclass 39, count 0 2006.173.11:35:53.46#ibcon#about to read 4, iclass 39, count 0 2006.173.11:35:53.46#ibcon#read 4, iclass 39, count 0 2006.173.11:35:53.46#ibcon#about to read 5, iclass 39, count 0 2006.173.11:35:53.46#ibcon#read 5, iclass 39, count 0 2006.173.11:35:53.46#ibcon#about to read 6, iclass 39, count 0 2006.173.11:35:53.46#ibcon#read 6, iclass 39, count 0 2006.173.11:35:53.46#ibcon#end of sib2, iclass 39, count 0 2006.173.11:35:53.46#ibcon#*mode == 0, iclass 39, count 0 2006.173.11:35:53.46#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.11:35:53.46#ibcon#[25=USB\r\n] 2006.173.11:35:53.46#ibcon#*before write, iclass 39, count 0 2006.173.11:35:53.46#ibcon#enter sib2, iclass 39, count 0 2006.173.11:35:53.46#ibcon#flushed, iclass 39, count 0 2006.173.11:35:53.46#ibcon#about to write, iclass 39, count 0 2006.173.11:35:53.46#ibcon#wrote, iclass 39, count 0 2006.173.11:35:53.46#ibcon#about to read 3, iclass 39, count 0 2006.173.11:35:53.49#ibcon#read 3, iclass 39, count 0 2006.173.11:35:53.49#ibcon#about to read 4, iclass 39, count 0 2006.173.11:35:53.49#ibcon#read 4, iclass 39, count 0 2006.173.11:35:53.49#ibcon#about to read 5, iclass 39, count 0 2006.173.11:35:53.49#ibcon#read 5, iclass 39, count 0 2006.173.11:35:53.49#ibcon#about to read 6, iclass 39, count 0 2006.173.11:35:53.49#ibcon#read 6, iclass 39, count 0 2006.173.11:35:53.49#ibcon#end of sib2, iclass 39, count 0 2006.173.11:35:53.49#ibcon#*after write, iclass 39, count 0 2006.173.11:35:53.49#ibcon#*before return 0, iclass 39, count 0 2006.173.11:35:53.49#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.11:35:53.49#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.11:35:53.49#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.11:35:53.49#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.11:35:53.49$vck44/valo=5,734.99 2006.173.11:35:53.49#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.11:35:53.49#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.11:35:53.49#ibcon#ireg 17 cls_cnt 0 2006.173.11:35:53.49#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.11:35:53.49#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.11:35:53.49#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.11:35:53.49#ibcon#enter wrdev, iclass 3, count 0 2006.173.11:35:53.49#ibcon#first serial, iclass 3, count 0 2006.173.11:35:53.49#ibcon#enter sib2, iclass 3, count 0 2006.173.11:35:53.49#ibcon#flushed, iclass 3, count 0 2006.173.11:35:53.49#ibcon#about to write, iclass 3, count 0 2006.173.11:35:53.49#ibcon#wrote, iclass 3, count 0 2006.173.11:35:53.49#ibcon#about to read 3, iclass 3, count 0 2006.173.11:35:53.51#ibcon#read 3, iclass 3, count 0 2006.173.11:35:53.51#ibcon#about to read 4, iclass 3, count 0 2006.173.11:35:53.51#ibcon#read 4, iclass 3, count 0 2006.173.11:35:53.51#ibcon#about to read 5, iclass 3, count 0 2006.173.11:35:53.51#ibcon#read 5, iclass 3, count 0 2006.173.11:35:53.51#ibcon#about to read 6, iclass 3, count 0 2006.173.11:35:53.51#ibcon#read 6, iclass 3, count 0 2006.173.11:35:53.51#ibcon#end of sib2, iclass 3, count 0 2006.173.11:35:53.51#ibcon#*mode == 0, iclass 3, count 0 2006.173.11:35:53.51#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.11:35:53.51#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.11:35:53.51#ibcon#*before write, iclass 3, count 0 2006.173.11:35:53.51#ibcon#enter sib2, iclass 3, count 0 2006.173.11:35:53.51#ibcon#flushed, iclass 3, count 0 2006.173.11:35:53.51#ibcon#about to write, iclass 3, count 0 2006.173.11:35:53.51#ibcon#wrote, iclass 3, count 0 2006.173.11:35:53.51#ibcon#about to read 3, iclass 3, count 0 2006.173.11:35:53.55#ibcon#read 3, iclass 3, count 0 2006.173.11:35:53.55#ibcon#about to read 4, iclass 3, count 0 2006.173.11:35:53.55#ibcon#read 4, iclass 3, count 0 2006.173.11:35:53.55#ibcon#about to read 5, iclass 3, count 0 2006.173.11:35:53.55#ibcon#read 5, iclass 3, count 0 2006.173.11:35:53.55#ibcon#about to read 6, iclass 3, count 0 2006.173.11:35:53.55#ibcon#read 6, iclass 3, count 0 2006.173.11:35:53.55#ibcon#end of sib2, iclass 3, count 0 2006.173.11:35:53.55#ibcon#*after write, iclass 3, count 0 2006.173.11:35:53.55#ibcon#*before return 0, iclass 3, count 0 2006.173.11:35:53.55#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.11:35:53.55#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.11:35:53.55#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.11:35:53.55#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.11:35:53.55$vck44/va=5,4 2006.173.11:35:53.55#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.11:35:53.55#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.11:35:53.55#ibcon#ireg 11 cls_cnt 2 2006.173.11:35:53.55#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.11:35:53.61#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.11:35:53.61#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.11:35:53.61#ibcon#enter wrdev, iclass 5, count 2 2006.173.11:35:53.61#ibcon#first serial, iclass 5, count 2 2006.173.11:35:53.61#ibcon#enter sib2, iclass 5, count 2 2006.173.11:35:53.61#ibcon#flushed, iclass 5, count 2 2006.173.11:35:53.61#ibcon#about to write, iclass 5, count 2 2006.173.11:35:53.61#ibcon#wrote, iclass 5, count 2 2006.173.11:35:53.61#ibcon#about to read 3, iclass 5, count 2 2006.173.11:35:53.63#ibcon#read 3, iclass 5, count 2 2006.173.11:35:53.63#ibcon#about to read 4, iclass 5, count 2 2006.173.11:35:53.63#ibcon#read 4, iclass 5, count 2 2006.173.11:35:53.63#ibcon#about to read 5, iclass 5, count 2 2006.173.11:35:53.63#ibcon#read 5, iclass 5, count 2 2006.173.11:35:53.63#ibcon#about to read 6, iclass 5, count 2 2006.173.11:35:53.63#ibcon#read 6, iclass 5, count 2 2006.173.11:35:53.63#ibcon#end of sib2, iclass 5, count 2 2006.173.11:35:53.63#ibcon#*mode == 0, iclass 5, count 2 2006.173.11:35:53.63#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.11:35:53.63#ibcon#[25=AT05-04\r\n] 2006.173.11:35:53.63#ibcon#*before write, iclass 5, count 2 2006.173.11:35:53.63#ibcon#enter sib2, iclass 5, count 2 2006.173.11:35:53.63#ibcon#flushed, iclass 5, count 2 2006.173.11:35:53.63#ibcon#about to write, iclass 5, count 2 2006.173.11:35:53.63#ibcon#wrote, iclass 5, count 2 2006.173.11:35:53.63#ibcon#about to read 3, iclass 5, count 2 2006.173.11:35:53.66#ibcon#read 3, iclass 5, count 2 2006.173.11:35:53.66#ibcon#about to read 4, iclass 5, count 2 2006.173.11:35:53.66#ibcon#read 4, iclass 5, count 2 2006.173.11:35:53.66#ibcon#about to read 5, iclass 5, count 2 2006.173.11:35:53.66#ibcon#read 5, iclass 5, count 2 2006.173.11:35:53.66#ibcon#about to read 6, iclass 5, count 2 2006.173.11:35:53.66#ibcon#read 6, iclass 5, count 2 2006.173.11:35:53.66#ibcon#end of sib2, iclass 5, count 2 2006.173.11:35:53.66#ibcon#*after write, iclass 5, count 2 2006.173.11:35:53.66#ibcon#*before return 0, iclass 5, count 2 2006.173.11:35:53.66#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.11:35:53.66#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.11:35:53.66#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.11:35:53.66#ibcon#ireg 7 cls_cnt 0 2006.173.11:35:53.66#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.11:35:53.78#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.11:35:53.78#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.11:35:53.78#ibcon#enter wrdev, iclass 5, count 0 2006.173.11:35:53.78#ibcon#first serial, iclass 5, count 0 2006.173.11:35:53.78#ibcon#enter sib2, iclass 5, count 0 2006.173.11:35:53.78#ibcon#flushed, iclass 5, count 0 2006.173.11:35:53.78#ibcon#about to write, iclass 5, count 0 2006.173.11:35:53.78#ibcon#wrote, iclass 5, count 0 2006.173.11:35:53.78#ibcon#about to read 3, iclass 5, count 0 2006.173.11:35:53.80#ibcon#read 3, iclass 5, count 0 2006.173.11:35:53.80#ibcon#about to read 4, iclass 5, count 0 2006.173.11:35:53.80#ibcon#read 4, iclass 5, count 0 2006.173.11:35:53.80#ibcon#about to read 5, iclass 5, count 0 2006.173.11:35:53.80#ibcon#read 5, iclass 5, count 0 2006.173.11:35:53.80#ibcon#about to read 6, iclass 5, count 0 2006.173.11:35:53.80#ibcon#read 6, iclass 5, count 0 2006.173.11:35:53.80#ibcon#end of sib2, iclass 5, count 0 2006.173.11:35:53.80#ibcon#*mode == 0, iclass 5, count 0 2006.173.11:35:53.80#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.11:35:53.80#ibcon#[25=USB\r\n] 2006.173.11:35:53.80#ibcon#*before write, iclass 5, count 0 2006.173.11:35:53.80#ibcon#enter sib2, iclass 5, count 0 2006.173.11:35:53.80#ibcon#flushed, iclass 5, count 0 2006.173.11:35:53.80#ibcon#about to write, iclass 5, count 0 2006.173.11:35:53.80#ibcon#wrote, iclass 5, count 0 2006.173.11:35:53.80#ibcon#about to read 3, iclass 5, count 0 2006.173.11:35:53.83#ibcon#read 3, iclass 5, count 0 2006.173.11:35:53.83#ibcon#about to read 4, iclass 5, count 0 2006.173.11:35:53.83#ibcon#read 4, iclass 5, count 0 2006.173.11:35:53.83#ibcon#about to read 5, iclass 5, count 0 2006.173.11:35:53.83#ibcon#read 5, iclass 5, count 0 2006.173.11:35:53.83#ibcon#about to read 6, iclass 5, count 0 2006.173.11:35:53.83#ibcon#read 6, iclass 5, count 0 2006.173.11:35:53.83#ibcon#end of sib2, iclass 5, count 0 2006.173.11:35:53.83#ibcon#*after write, iclass 5, count 0 2006.173.11:35:53.83#ibcon#*before return 0, iclass 5, count 0 2006.173.11:35:53.83#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.11:35:53.83#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.11:35:53.83#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.11:35:53.83#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.11:35:53.83$vck44/valo=6,814.99 2006.173.11:35:53.83#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.11:35:53.83#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.11:35:53.83#ibcon#ireg 17 cls_cnt 0 2006.173.11:35:53.83#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.11:35:53.83#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.11:35:53.83#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.11:35:53.83#ibcon#enter wrdev, iclass 7, count 0 2006.173.11:35:53.83#ibcon#first serial, iclass 7, count 0 2006.173.11:35:53.83#ibcon#enter sib2, iclass 7, count 0 2006.173.11:35:53.83#ibcon#flushed, iclass 7, count 0 2006.173.11:35:53.83#ibcon#about to write, iclass 7, count 0 2006.173.11:35:53.83#ibcon#wrote, iclass 7, count 0 2006.173.11:35:53.83#ibcon#about to read 3, iclass 7, count 0 2006.173.11:35:53.85#ibcon#read 3, iclass 7, count 0 2006.173.11:35:53.85#ibcon#about to read 4, iclass 7, count 0 2006.173.11:35:53.85#ibcon#read 4, iclass 7, count 0 2006.173.11:35:53.85#ibcon#about to read 5, iclass 7, count 0 2006.173.11:35:53.85#ibcon#read 5, iclass 7, count 0 2006.173.11:35:53.85#ibcon#about to read 6, iclass 7, count 0 2006.173.11:35:53.85#ibcon#read 6, iclass 7, count 0 2006.173.11:35:53.85#ibcon#end of sib2, iclass 7, count 0 2006.173.11:35:53.85#ibcon#*mode == 0, iclass 7, count 0 2006.173.11:35:53.85#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.11:35:53.85#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.11:35:53.85#ibcon#*before write, iclass 7, count 0 2006.173.11:35:53.85#ibcon#enter sib2, iclass 7, count 0 2006.173.11:35:53.85#ibcon#flushed, iclass 7, count 0 2006.173.11:35:53.85#ibcon#about to write, iclass 7, count 0 2006.173.11:35:53.85#ibcon#wrote, iclass 7, count 0 2006.173.11:35:53.85#ibcon#about to read 3, iclass 7, count 0 2006.173.11:35:53.89#ibcon#read 3, iclass 7, count 0 2006.173.11:35:53.89#ibcon#about to read 4, iclass 7, count 0 2006.173.11:35:53.89#ibcon#read 4, iclass 7, count 0 2006.173.11:35:53.89#ibcon#about to read 5, iclass 7, count 0 2006.173.11:35:53.89#ibcon#read 5, iclass 7, count 0 2006.173.11:35:53.89#ibcon#about to read 6, iclass 7, count 0 2006.173.11:35:53.89#ibcon#read 6, iclass 7, count 0 2006.173.11:35:53.89#ibcon#end of sib2, iclass 7, count 0 2006.173.11:35:53.89#ibcon#*after write, iclass 7, count 0 2006.173.11:35:53.89#ibcon#*before return 0, iclass 7, count 0 2006.173.11:35:53.89#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.11:35:53.89#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.11:35:53.89#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.11:35:53.89#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.11:35:53.89$vck44/va=6,3 2006.173.11:35:53.89#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.11:35:53.89#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.11:35:53.89#ibcon#ireg 11 cls_cnt 2 2006.173.11:35:53.89#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.11:35:53.95#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.11:35:53.95#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.11:35:53.95#ibcon#enter wrdev, iclass 11, count 2 2006.173.11:35:53.95#ibcon#first serial, iclass 11, count 2 2006.173.11:35:53.95#ibcon#enter sib2, iclass 11, count 2 2006.173.11:35:53.95#ibcon#flushed, iclass 11, count 2 2006.173.11:35:53.95#ibcon#about to write, iclass 11, count 2 2006.173.11:35:53.95#ibcon#wrote, iclass 11, count 2 2006.173.11:35:53.95#ibcon#about to read 3, iclass 11, count 2 2006.173.11:35:53.97#ibcon#read 3, iclass 11, count 2 2006.173.11:35:53.97#ibcon#about to read 4, iclass 11, count 2 2006.173.11:35:53.97#ibcon#read 4, iclass 11, count 2 2006.173.11:35:53.97#ibcon#about to read 5, iclass 11, count 2 2006.173.11:35:53.97#ibcon#read 5, iclass 11, count 2 2006.173.11:35:53.97#ibcon#about to read 6, iclass 11, count 2 2006.173.11:35:53.97#ibcon#read 6, iclass 11, count 2 2006.173.11:35:53.97#ibcon#end of sib2, iclass 11, count 2 2006.173.11:35:53.97#ibcon#*mode == 0, iclass 11, count 2 2006.173.11:35:53.97#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.11:35:53.97#ibcon#[25=AT06-03\r\n] 2006.173.11:35:53.97#ibcon#*before write, iclass 11, count 2 2006.173.11:35:53.97#ibcon#enter sib2, iclass 11, count 2 2006.173.11:35:53.97#ibcon#flushed, iclass 11, count 2 2006.173.11:35:53.97#ibcon#about to write, iclass 11, count 2 2006.173.11:35:53.97#ibcon#wrote, iclass 11, count 2 2006.173.11:35:53.97#ibcon#about to read 3, iclass 11, count 2 2006.173.11:35:54.00#ibcon#read 3, iclass 11, count 2 2006.173.11:35:54.00#ibcon#about to read 4, iclass 11, count 2 2006.173.11:35:54.00#ibcon#read 4, iclass 11, count 2 2006.173.11:35:54.00#ibcon#about to read 5, iclass 11, count 2 2006.173.11:35:54.00#ibcon#read 5, iclass 11, count 2 2006.173.11:35:54.00#ibcon#about to read 6, iclass 11, count 2 2006.173.11:35:54.00#ibcon#read 6, iclass 11, count 2 2006.173.11:35:54.00#ibcon#end of sib2, iclass 11, count 2 2006.173.11:35:54.00#ibcon#*after write, iclass 11, count 2 2006.173.11:35:54.00#ibcon#*before return 0, iclass 11, count 2 2006.173.11:35:54.00#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.11:35:54.00#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.11:35:54.00#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.11:35:54.00#ibcon#ireg 7 cls_cnt 0 2006.173.11:35:54.00#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.11:35:54.12#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.11:35:54.12#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.11:35:54.12#ibcon#enter wrdev, iclass 11, count 0 2006.173.11:35:54.12#ibcon#first serial, iclass 11, count 0 2006.173.11:35:54.12#ibcon#enter sib2, iclass 11, count 0 2006.173.11:35:54.12#ibcon#flushed, iclass 11, count 0 2006.173.11:35:54.12#ibcon#about to write, iclass 11, count 0 2006.173.11:35:54.12#ibcon#wrote, iclass 11, count 0 2006.173.11:35:54.12#ibcon#about to read 3, iclass 11, count 0 2006.173.11:35:54.14#ibcon#read 3, iclass 11, count 0 2006.173.11:35:54.14#ibcon#about to read 4, iclass 11, count 0 2006.173.11:35:54.14#ibcon#read 4, iclass 11, count 0 2006.173.11:35:54.14#ibcon#about to read 5, iclass 11, count 0 2006.173.11:35:54.14#ibcon#read 5, iclass 11, count 0 2006.173.11:35:54.14#ibcon#about to read 6, iclass 11, count 0 2006.173.11:35:54.14#ibcon#read 6, iclass 11, count 0 2006.173.11:35:54.14#ibcon#end of sib2, iclass 11, count 0 2006.173.11:35:54.14#ibcon#*mode == 0, iclass 11, count 0 2006.173.11:35:54.14#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.11:35:54.14#ibcon#[25=USB\r\n] 2006.173.11:35:54.14#ibcon#*before write, iclass 11, count 0 2006.173.11:35:54.14#ibcon#enter sib2, iclass 11, count 0 2006.173.11:35:54.14#ibcon#flushed, iclass 11, count 0 2006.173.11:35:54.14#ibcon#about to write, iclass 11, count 0 2006.173.11:35:54.14#ibcon#wrote, iclass 11, count 0 2006.173.11:35:54.14#ibcon#about to read 3, iclass 11, count 0 2006.173.11:35:54.17#ibcon#read 3, iclass 11, count 0 2006.173.11:35:54.17#ibcon#about to read 4, iclass 11, count 0 2006.173.11:35:54.17#ibcon#read 4, iclass 11, count 0 2006.173.11:35:54.17#ibcon#about to read 5, iclass 11, count 0 2006.173.11:35:54.17#ibcon#read 5, iclass 11, count 0 2006.173.11:35:54.17#ibcon#about to read 6, iclass 11, count 0 2006.173.11:35:54.17#ibcon#read 6, iclass 11, count 0 2006.173.11:35:54.17#ibcon#end of sib2, iclass 11, count 0 2006.173.11:35:54.17#ibcon#*after write, iclass 11, count 0 2006.173.11:35:54.17#ibcon#*before return 0, iclass 11, count 0 2006.173.11:35:54.17#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.11:35:54.17#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.11:35:54.17#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.11:35:54.17#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.11:35:54.17$vck44/valo=7,864.99 2006.173.11:35:54.17#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.11:35:54.17#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.11:35:54.17#ibcon#ireg 17 cls_cnt 0 2006.173.11:35:54.17#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.11:35:54.17#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.11:35:54.17#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.11:35:54.17#ibcon#enter wrdev, iclass 13, count 0 2006.173.11:35:54.17#ibcon#first serial, iclass 13, count 0 2006.173.11:35:54.17#ibcon#enter sib2, iclass 13, count 0 2006.173.11:35:54.17#ibcon#flushed, iclass 13, count 0 2006.173.11:35:54.17#ibcon#about to write, iclass 13, count 0 2006.173.11:35:54.17#ibcon#wrote, iclass 13, count 0 2006.173.11:35:54.17#ibcon#about to read 3, iclass 13, count 0 2006.173.11:35:54.19#ibcon#read 3, iclass 13, count 0 2006.173.11:35:54.19#ibcon#about to read 4, iclass 13, count 0 2006.173.11:35:54.19#ibcon#read 4, iclass 13, count 0 2006.173.11:35:54.19#ibcon#about to read 5, iclass 13, count 0 2006.173.11:35:54.19#ibcon#read 5, iclass 13, count 0 2006.173.11:35:54.19#ibcon#about to read 6, iclass 13, count 0 2006.173.11:35:54.19#ibcon#read 6, iclass 13, count 0 2006.173.11:35:54.19#ibcon#end of sib2, iclass 13, count 0 2006.173.11:35:54.19#ibcon#*mode == 0, iclass 13, count 0 2006.173.11:35:54.19#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.11:35:54.19#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.11:35:54.19#ibcon#*before write, iclass 13, count 0 2006.173.11:35:54.19#ibcon#enter sib2, iclass 13, count 0 2006.173.11:35:54.19#ibcon#flushed, iclass 13, count 0 2006.173.11:35:54.19#ibcon#about to write, iclass 13, count 0 2006.173.11:35:54.19#ibcon#wrote, iclass 13, count 0 2006.173.11:35:54.19#ibcon#about to read 3, iclass 13, count 0 2006.173.11:35:54.23#ibcon#read 3, iclass 13, count 0 2006.173.11:35:54.23#ibcon#about to read 4, iclass 13, count 0 2006.173.11:35:54.23#ibcon#read 4, iclass 13, count 0 2006.173.11:35:54.23#ibcon#about to read 5, iclass 13, count 0 2006.173.11:35:54.23#ibcon#read 5, iclass 13, count 0 2006.173.11:35:54.23#ibcon#about to read 6, iclass 13, count 0 2006.173.11:35:54.23#ibcon#read 6, iclass 13, count 0 2006.173.11:35:54.23#ibcon#end of sib2, iclass 13, count 0 2006.173.11:35:54.23#ibcon#*after write, iclass 13, count 0 2006.173.11:35:54.23#ibcon#*before return 0, iclass 13, count 0 2006.173.11:35:54.23#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.11:35:54.23#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.11:35:54.23#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.11:35:54.23#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.11:35:54.23$vck44/va=7,4 2006.173.11:35:54.23#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.11:35:54.23#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.11:35:54.23#ibcon#ireg 11 cls_cnt 2 2006.173.11:35:54.23#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.11:35:54.29#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.11:35:54.29#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.11:35:54.29#ibcon#enter wrdev, iclass 15, count 2 2006.173.11:35:54.29#ibcon#first serial, iclass 15, count 2 2006.173.11:35:54.29#ibcon#enter sib2, iclass 15, count 2 2006.173.11:35:54.29#ibcon#flushed, iclass 15, count 2 2006.173.11:35:54.29#ibcon#about to write, iclass 15, count 2 2006.173.11:35:54.29#ibcon#wrote, iclass 15, count 2 2006.173.11:35:54.29#ibcon#about to read 3, iclass 15, count 2 2006.173.11:35:54.31#ibcon#read 3, iclass 15, count 2 2006.173.11:35:54.31#ibcon#about to read 4, iclass 15, count 2 2006.173.11:35:54.31#ibcon#read 4, iclass 15, count 2 2006.173.11:35:54.31#ibcon#about to read 5, iclass 15, count 2 2006.173.11:35:54.31#ibcon#read 5, iclass 15, count 2 2006.173.11:35:54.31#ibcon#about to read 6, iclass 15, count 2 2006.173.11:35:54.31#ibcon#read 6, iclass 15, count 2 2006.173.11:35:54.31#ibcon#end of sib2, iclass 15, count 2 2006.173.11:35:54.31#ibcon#*mode == 0, iclass 15, count 2 2006.173.11:35:54.31#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.11:35:54.31#ibcon#[25=AT07-04\r\n] 2006.173.11:35:54.31#ibcon#*before write, iclass 15, count 2 2006.173.11:35:54.31#ibcon#enter sib2, iclass 15, count 2 2006.173.11:35:54.31#ibcon#flushed, iclass 15, count 2 2006.173.11:35:54.31#ibcon#about to write, iclass 15, count 2 2006.173.11:35:54.31#ibcon#wrote, iclass 15, count 2 2006.173.11:35:54.31#ibcon#about to read 3, iclass 15, count 2 2006.173.11:35:54.34#ibcon#read 3, iclass 15, count 2 2006.173.11:35:54.34#ibcon#about to read 4, iclass 15, count 2 2006.173.11:35:54.34#ibcon#read 4, iclass 15, count 2 2006.173.11:35:54.34#ibcon#about to read 5, iclass 15, count 2 2006.173.11:35:54.34#ibcon#read 5, iclass 15, count 2 2006.173.11:35:54.34#ibcon#about to read 6, iclass 15, count 2 2006.173.11:35:54.34#ibcon#read 6, iclass 15, count 2 2006.173.11:35:54.34#ibcon#end of sib2, iclass 15, count 2 2006.173.11:35:54.34#ibcon#*after write, iclass 15, count 2 2006.173.11:35:54.34#ibcon#*before return 0, iclass 15, count 2 2006.173.11:35:54.34#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.11:35:54.34#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.11:35:54.34#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.11:35:54.34#ibcon#ireg 7 cls_cnt 0 2006.173.11:35:54.34#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.11:35:54.46#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.11:35:54.46#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.11:35:54.46#ibcon#enter wrdev, iclass 15, count 0 2006.173.11:35:54.46#ibcon#first serial, iclass 15, count 0 2006.173.11:35:54.46#ibcon#enter sib2, iclass 15, count 0 2006.173.11:35:54.46#ibcon#flushed, iclass 15, count 0 2006.173.11:35:54.46#ibcon#about to write, iclass 15, count 0 2006.173.11:35:54.46#ibcon#wrote, iclass 15, count 0 2006.173.11:35:54.46#ibcon#about to read 3, iclass 15, count 0 2006.173.11:35:54.48#ibcon#read 3, iclass 15, count 0 2006.173.11:35:54.48#ibcon#about to read 4, iclass 15, count 0 2006.173.11:35:54.48#ibcon#read 4, iclass 15, count 0 2006.173.11:35:54.48#ibcon#about to read 5, iclass 15, count 0 2006.173.11:35:54.48#ibcon#read 5, iclass 15, count 0 2006.173.11:35:54.48#ibcon#about to read 6, iclass 15, count 0 2006.173.11:35:54.48#ibcon#read 6, iclass 15, count 0 2006.173.11:35:54.48#ibcon#end of sib2, iclass 15, count 0 2006.173.11:35:54.48#ibcon#*mode == 0, iclass 15, count 0 2006.173.11:35:54.48#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.11:35:54.48#ibcon#[25=USB\r\n] 2006.173.11:35:54.48#ibcon#*before write, iclass 15, count 0 2006.173.11:35:54.48#ibcon#enter sib2, iclass 15, count 0 2006.173.11:35:54.48#ibcon#flushed, iclass 15, count 0 2006.173.11:35:54.48#ibcon#about to write, iclass 15, count 0 2006.173.11:35:54.48#ibcon#wrote, iclass 15, count 0 2006.173.11:35:54.48#ibcon#about to read 3, iclass 15, count 0 2006.173.11:35:54.51#ibcon#read 3, iclass 15, count 0 2006.173.11:35:54.51#ibcon#about to read 4, iclass 15, count 0 2006.173.11:35:54.51#ibcon#read 4, iclass 15, count 0 2006.173.11:35:54.51#ibcon#about to read 5, iclass 15, count 0 2006.173.11:35:54.51#ibcon#read 5, iclass 15, count 0 2006.173.11:35:54.51#ibcon#about to read 6, iclass 15, count 0 2006.173.11:35:54.51#ibcon#read 6, iclass 15, count 0 2006.173.11:35:54.51#ibcon#end of sib2, iclass 15, count 0 2006.173.11:35:54.51#ibcon#*after write, iclass 15, count 0 2006.173.11:35:54.51#ibcon#*before return 0, iclass 15, count 0 2006.173.11:35:54.51#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.11:35:54.51#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.11:35:54.51#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.11:35:54.51#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.11:35:54.51$vck44/valo=8,884.99 2006.173.11:35:54.51#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.11:35:54.51#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.11:35:54.51#ibcon#ireg 17 cls_cnt 0 2006.173.11:35:54.51#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.11:35:54.51#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.11:35:54.51#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.11:35:54.51#ibcon#enter wrdev, iclass 17, count 0 2006.173.11:35:54.51#ibcon#first serial, iclass 17, count 0 2006.173.11:35:54.51#ibcon#enter sib2, iclass 17, count 0 2006.173.11:35:54.51#ibcon#flushed, iclass 17, count 0 2006.173.11:35:54.51#ibcon#about to write, iclass 17, count 0 2006.173.11:35:54.51#ibcon#wrote, iclass 17, count 0 2006.173.11:35:54.51#ibcon#about to read 3, iclass 17, count 0 2006.173.11:35:54.53#ibcon#read 3, iclass 17, count 0 2006.173.11:35:54.53#ibcon#about to read 4, iclass 17, count 0 2006.173.11:35:54.53#ibcon#read 4, iclass 17, count 0 2006.173.11:35:54.53#ibcon#about to read 5, iclass 17, count 0 2006.173.11:35:54.53#ibcon#read 5, iclass 17, count 0 2006.173.11:35:54.53#ibcon#about to read 6, iclass 17, count 0 2006.173.11:35:54.53#ibcon#read 6, iclass 17, count 0 2006.173.11:35:54.53#ibcon#end of sib2, iclass 17, count 0 2006.173.11:35:54.53#ibcon#*mode == 0, iclass 17, count 0 2006.173.11:35:54.53#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.11:35:54.53#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.11:35:54.53#ibcon#*before write, iclass 17, count 0 2006.173.11:35:54.53#ibcon#enter sib2, iclass 17, count 0 2006.173.11:35:54.53#ibcon#flushed, iclass 17, count 0 2006.173.11:35:54.53#ibcon#about to write, iclass 17, count 0 2006.173.11:35:54.53#ibcon#wrote, iclass 17, count 0 2006.173.11:35:54.53#ibcon#about to read 3, iclass 17, count 0 2006.173.11:35:54.57#ibcon#read 3, iclass 17, count 0 2006.173.11:35:54.57#ibcon#about to read 4, iclass 17, count 0 2006.173.11:35:54.57#ibcon#read 4, iclass 17, count 0 2006.173.11:35:54.57#ibcon#about to read 5, iclass 17, count 0 2006.173.11:35:54.57#ibcon#read 5, iclass 17, count 0 2006.173.11:35:54.57#ibcon#about to read 6, iclass 17, count 0 2006.173.11:35:54.57#ibcon#read 6, iclass 17, count 0 2006.173.11:35:54.57#ibcon#end of sib2, iclass 17, count 0 2006.173.11:35:54.57#ibcon#*after write, iclass 17, count 0 2006.173.11:35:54.57#ibcon#*before return 0, iclass 17, count 0 2006.173.11:35:54.57#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.11:35:54.57#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.11:35:54.57#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.11:35:54.57#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.11:35:54.57$vck44/va=8,4 2006.173.11:35:54.57#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.11:35:54.57#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.11:35:54.57#ibcon#ireg 11 cls_cnt 2 2006.173.11:35:54.57#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.11:35:54.63#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.11:35:54.63#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.11:35:54.63#ibcon#enter wrdev, iclass 19, count 2 2006.173.11:35:54.63#ibcon#first serial, iclass 19, count 2 2006.173.11:35:54.63#ibcon#enter sib2, iclass 19, count 2 2006.173.11:35:54.63#ibcon#flushed, iclass 19, count 2 2006.173.11:35:54.63#ibcon#about to write, iclass 19, count 2 2006.173.11:35:54.63#ibcon#wrote, iclass 19, count 2 2006.173.11:35:54.63#ibcon#about to read 3, iclass 19, count 2 2006.173.11:35:54.65#ibcon#read 3, iclass 19, count 2 2006.173.11:35:54.65#ibcon#about to read 4, iclass 19, count 2 2006.173.11:35:54.65#ibcon#read 4, iclass 19, count 2 2006.173.11:35:54.65#ibcon#about to read 5, iclass 19, count 2 2006.173.11:35:54.65#ibcon#read 5, iclass 19, count 2 2006.173.11:35:54.65#ibcon#about to read 6, iclass 19, count 2 2006.173.11:35:54.65#ibcon#read 6, iclass 19, count 2 2006.173.11:35:54.65#ibcon#end of sib2, iclass 19, count 2 2006.173.11:35:54.65#ibcon#*mode == 0, iclass 19, count 2 2006.173.11:35:54.65#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.11:35:54.65#ibcon#[25=AT08-04\r\n] 2006.173.11:35:54.65#ibcon#*before write, iclass 19, count 2 2006.173.11:35:54.65#ibcon#enter sib2, iclass 19, count 2 2006.173.11:35:54.65#ibcon#flushed, iclass 19, count 2 2006.173.11:35:54.65#ibcon#about to write, iclass 19, count 2 2006.173.11:35:54.65#ibcon#wrote, iclass 19, count 2 2006.173.11:35:54.65#ibcon#about to read 3, iclass 19, count 2 2006.173.11:35:54.68#ibcon#read 3, iclass 19, count 2 2006.173.11:35:54.68#ibcon#about to read 4, iclass 19, count 2 2006.173.11:35:54.68#ibcon#read 4, iclass 19, count 2 2006.173.11:35:54.68#ibcon#about to read 5, iclass 19, count 2 2006.173.11:35:54.68#ibcon#read 5, iclass 19, count 2 2006.173.11:35:54.68#ibcon#about to read 6, iclass 19, count 2 2006.173.11:35:54.68#ibcon#read 6, iclass 19, count 2 2006.173.11:35:54.68#ibcon#end of sib2, iclass 19, count 2 2006.173.11:35:54.68#ibcon#*after write, iclass 19, count 2 2006.173.11:35:54.68#ibcon#*before return 0, iclass 19, count 2 2006.173.11:35:54.68#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.11:35:54.68#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.11:35:54.68#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.11:35:54.68#ibcon#ireg 7 cls_cnt 0 2006.173.11:35:54.68#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.11:35:54.80#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.11:35:54.80#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.11:35:54.80#ibcon#enter wrdev, iclass 19, count 0 2006.173.11:35:54.80#ibcon#first serial, iclass 19, count 0 2006.173.11:35:54.80#ibcon#enter sib2, iclass 19, count 0 2006.173.11:35:54.80#ibcon#flushed, iclass 19, count 0 2006.173.11:35:54.80#ibcon#about to write, iclass 19, count 0 2006.173.11:35:54.80#ibcon#wrote, iclass 19, count 0 2006.173.11:35:54.80#ibcon#about to read 3, iclass 19, count 0 2006.173.11:35:54.82#ibcon#read 3, iclass 19, count 0 2006.173.11:35:54.82#ibcon#about to read 4, iclass 19, count 0 2006.173.11:35:54.82#ibcon#read 4, iclass 19, count 0 2006.173.11:35:54.82#ibcon#about to read 5, iclass 19, count 0 2006.173.11:35:54.82#ibcon#read 5, iclass 19, count 0 2006.173.11:35:54.82#ibcon#about to read 6, iclass 19, count 0 2006.173.11:35:54.82#ibcon#read 6, iclass 19, count 0 2006.173.11:35:54.82#ibcon#end of sib2, iclass 19, count 0 2006.173.11:35:54.82#ibcon#*mode == 0, iclass 19, count 0 2006.173.11:35:54.82#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.11:35:54.82#ibcon#[25=USB\r\n] 2006.173.11:35:54.82#ibcon#*before write, iclass 19, count 0 2006.173.11:35:54.82#ibcon#enter sib2, iclass 19, count 0 2006.173.11:35:54.82#ibcon#flushed, iclass 19, count 0 2006.173.11:35:54.82#ibcon#about to write, iclass 19, count 0 2006.173.11:35:54.82#ibcon#wrote, iclass 19, count 0 2006.173.11:35:54.82#ibcon#about to read 3, iclass 19, count 0 2006.173.11:35:54.85#ibcon#read 3, iclass 19, count 0 2006.173.11:35:54.85#ibcon#about to read 4, iclass 19, count 0 2006.173.11:35:54.85#ibcon#read 4, iclass 19, count 0 2006.173.11:35:54.85#ibcon#about to read 5, iclass 19, count 0 2006.173.11:35:54.85#ibcon#read 5, iclass 19, count 0 2006.173.11:35:54.85#ibcon#about to read 6, iclass 19, count 0 2006.173.11:35:54.85#ibcon#read 6, iclass 19, count 0 2006.173.11:35:54.85#ibcon#end of sib2, iclass 19, count 0 2006.173.11:35:54.85#ibcon#*after write, iclass 19, count 0 2006.173.11:35:54.85#ibcon#*before return 0, iclass 19, count 0 2006.173.11:35:54.85#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.11:35:54.85#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.11:35:54.85#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.11:35:54.85#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.11:35:54.85$vck44/vblo=1,629.99 2006.173.11:35:54.85#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.11:35:54.85#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.11:35:54.85#ibcon#ireg 17 cls_cnt 0 2006.173.11:35:54.85#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.11:35:54.85#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.11:35:54.85#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.11:35:54.85#ibcon#enter wrdev, iclass 21, count 0 2006.173.11:35:54.85#ibcon#first serial, iclass 21, count 0 2006.173.11:35:54.85#ibcon#enter sib2, iclass 21, count 0 2006.173.11:35:54.85#ibcon#flushed, iclass 21, count 0 2006.173.11:35:54.85#ibcon#about to write, iclass 21, count 0 2006.173.11:35:54.85#ibcon#wrote, iclass 21, count 0 2006.173.11:35:54.85#ibcon#about to read 3, iclass 21, count 0 2006.173.11:35:54.87#ibcon#read 3, iclass 21, count 0 2006.173.11:35:54.87#ibcon#about to read 4, iclass 21, count 0 2006.173.11:35:54.87#ibcon#read 4, iclass 21, count 0 2006.173.11:35:54.87#ibcon#about to read 5, iclass 21, count 0 2006.173.11:35:54.87#ibcon#read 5, iclass 21, count 0 2006.173.11:35:54.87#ibcon#about to read 6, iclass 21, count 0 2006.173.11:35:54.87#ibcon#read 6, iclass 21, count 0 2006.173.11:35:54.87#ibcon#end of sib2, iclass 21, count 0 2006.173.11:35:54.87#ibcon#*mode == 0, iclass 21, count 0 2006.173.11:35:54.87#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.11:35:54.87#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.11:35:54.87#ibcon#*before write, iclass 21, count 0 2006.173.11:35:54.87#ibcon#enter sib2, iclass 21, count 0 2006.173.11:35:54.87#ibcon#flushed, iclass 21, count 0 2006.173.11:35:54.87#ibcon#about to write, iclass 21, count 0 2006.173.11:35:54.87#ibcon#wrote, iclass 21, count 0 2006.173.11:35:54.87#ibcon#about to read 3, iclass 21, count 0 2006.173.11:35:54.91#ibcon#read 3, iclass 21, count 0 2006.173.11:35:54.91#ibcon#about to read 4, iclass 21, count 0 2006.173.11:35:54.91#ibcon#read 4, iclass 21, count 0 2006.173.11:35:54.91#ibcon#about to read 5, iclass 21, count 0 2006.173.11:35:54.91#ibcon#read 5, iclass 21, count 0 2006.173.11:35:54.91#ibcon#about to read 6, iclass 21, count 0 2006.173.11:35:54.91#ibcon#read 6, iclass 21, count 0 2006.173.11:35:54.91#ibcon#end of sib2, iclass 21, count 0 2006.173.11:35:54.91#ibcon#*after write, iclass 21, count 0 2006.173.11:35:54.91#ibcon#*before return 0, iclass 21, count 0 2006.173.11:35:54.91#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.11:35:54.91#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.11:35:54.91#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.11:35:54.91#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.11:35:54.91$vck44/vb=1,4 2006.173.11:35:54.91#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.11:35:54.91#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.11:35:54.91#ibcon#ireg 11 cls_cnt 2 2006.173.11:35:54.91#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.11:35:54.91#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.11:35:54.91#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.11:35:54.91#ibcon#enter wrdev, iclass 23, count 2 2006.173.11:35:54.91#ibcon#first serial, iclass 23, count 2 2006.173.11:35:54.91#ibcon#enter sib2, iclass 23, count 2 2006.173.11:35:54.91#ibcon#flushed, iclass 23, count 2 2006.173.11:35:54.91#ibcon#about to write, iclass 23, count 2 2006.173.11:35:54.91#ibcon#wrote, iclass 23, count 2 2006.173.11:35:54.91#ibcon#about to read 3, iclass 23, count 2 2006.173.11:35:54.93#ibcon#read 3, iclass 23, count 2 2006.173.11:35:54.93#ibcon#about to read 4, iclass 23, count 2 2006.173.11:35:54.93#ibcon#read 4, iclass 23, count 2 2006.173.11:35:54.93#ibcon#about to read 5, iclass 23, count 2 2006.173.11:35:54.93#ibcon#read 5, iclass 23, count 2 2006.173.11:35:54.93#ibcon#about to read 6, iclass 23, count 2 2006.173.11:35:54.93#ibcon#read 6, iclass 23, count 2 2006.173.11:35:54.93#ibcon#end of sib2, iclass 23, count 2 2006.173.11:35:54.93#ibcon#*mode == 0, iclass 23, count 2 2006.173.11:35:54.93#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.11:35:54.93#ibcon#[27=AT01-04\r\n] 2006.173.11:35:54.93#ibcon#*before write, iclass 23, count 2 2006.173.11:35:54.93#ibcon#enter sib2, iclass 23, count 2 2006.173.11:35:54.93#ibcon#flushed, iclass 23, count 2 2006.173.11:35:54.93#ibcon#about to write, iclass 23, count 2 2006.173.11:35:54.93#ibcon#wrote, iclass 23, count 2 2006.173.11:35:54.93#ibcon#about to read 3, iclass 23, count 2 2006.173.11:35:54.96#ibcon#read 3, iclass 23, count 2 2006.173.11:35:54.96#ibcon#about to read 4, iclass 23, count 2 2006.173.11:35:54.96#ibcon#read 4, iclass 23, count 2 2006.173.11:35:54.96#ibcon#about to read 5, iclass 23, count 2 2006.173.11:35:54.96#ibcon#read 5, iclass 23, count 2 2006.173.11:35:54.96#ibcon#about to read 6, iclass 23, count 2 2006.173.11:35:54.96#ibcon#read 6, iclass 23, count 2 2006.173.11:35:54.96#ibcon#end of sib2, iclass 23, count 2 2006.173.11:35:54.96#ibcon#*after write, iclass 23, count 2 2006.173.11:35:54.96#ibcon#*before return 0, iclass 23, count 2 2006.173.11:35:54.96#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.11:35:54.96#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.11:35:54.96#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.11:35:54.96#ibcon#ireg 7 cls_cnt 0 2006.173.11:35:54.96#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.11:35:55.08#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.11:35:55.08#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.11:35:55.08#ibcon#enter wrdev, iclass 23, count 0 2006.173.11:35:55.08#ibcon#first serial, iclass 23, count 0 2006.173.11:35:55.08#ibcon#enter sib2, iclass 23, count 0 2006.173.11:35:55.08#ibcon#flushed, iclass 23, count 0 2006.173.11:35:55.08#ibcon#about to write, iclass 23, count 0 2006.173.11:35:55.08#ibcon#wrote, iclass 23, count 0 2006.173.11:35:55.08#ibcon#about to read 3, iclass 23, count 0 2006.173.11:35:55.10#ibcon#read 3, iclass 23, count 0 2006.173.11:35:55.10#ibcon#about to read 4, iclass 23, count 0 2006.173.11:35:55.10#ibcon#read 4, iclass 23, count 0 2006.173.11:35:55.10#ibcon#about to read 5, iclass 23, count 0 2006.173.11:35:55.10#ibcon#read 5, iclass 23, count 0 2006.173.11:35:55.10#ibcon#about to read 6, iclass 23, count 0 2006.173.11:35:55.10#ibcon#read 6, iclass 23, count 0 2006.173.11:35:55.10#ibcon#end of sib2, iclass 23, count 0 2006.173.11:35:55.10#ibcon#*mode == 0, iclass 23, count 0 2006.173.11:35:55.10#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.11:35:55.10#ibcon#[27=USB\r\n] 2006.173.11:35:55.10#ibcon#*before write, iclass 23, count 0 2006.173.11:35:55.10#ibcon#enter sib2, iclass 23, count 0 2006.173.11:35:55.10#ibcon#flushed, iclass 23, count 0 2006.173.11:35:55.10#ibcon#about to write, iclass 23, count 0 2006.173.11:35:55.10#ibcon#wrote, iclass 23, count 0 2006.173.11:35:55.10#ibcon#about to read 3, iclass 23, count 0 2006.173.11:35:55.13#ibcon#read 3, iclass 23, count 0 2006.173.11:35:55.13#ibcon#about to read 4, iclass 23, count 0 2006.173.11:35:55.13#ibcon#read 4, iclass 23, count 0 2006.173.11:35:55.13#ibcon#about to read 5, iclass 23, count 0 2006.173.11:35:55.13#ibcon#read 5, iclass 23, count 0 2006.173.11:35:55.13#ibcon#about to read 6, iclass 23, count 0 2006.173.11:35:55.13#ibcon#read 6, iclass 23, count 0 2006.173.11:35:55.13#ibcon#end of sib2, iclass 23, count 0 2006.173.11:35:55.13#ibcon#*after write, iclass 23, count 0 2006.173.11:35:55.13#ibcon#*before return 0, iclass 23, count 0 2006.173.11:35:55.13#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.11:35:55.13#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.11:35:55.13#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.11:35:55.13#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.11:35:55.13$vck44/vblo=2,634.99 2006.173.11:35:55.13#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.11:35:55.13#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.11:35:55.13#ibcon#ireg 17 cls_cnt 0 2006.173.11:35:55.13#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.11:35:55.13#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.11:35:55.13#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.11:35:55.13#ibcon#enter wrdev, iclass 25, count 0 2006.173.11:35:55.13#ibcon#first serial, iclass 25, count 0 2006.173.11:35:55.13#ibcon#enter sib2, iclass 25, count 0 2006.173.11:35:55.13#ibcon#flushed, iclass 25, count 0 2006.173.11:35:55.13#ibcon#about to write, iclass 25, count 0 2006.173.11:35:55.13#ibcon#wrote, iclass 25, count 0 2006.173.11:35:55.13#ibcon#about to read 3, iclass 25, count 0 2006.173.11:35:55.15#ibcon#read 3, iclass 25, count 0 2006.173.11:35:55.15#ibcon#about to read 4, iclass 25, count 0 2006.173.11:35:55.15#ibcon#read 4, iclass 25, count 0 2006.173.11:35:55.15#ibcon#about to read 5, iclass 25, count 0 2006.173.11:35:55.15#ibcon#read 5, iclass 25, count 0 2006.173.11:35:55.15#ibcon#about to read 6, iclass 25, count 0 2006.173.11:35:55.15#ibcon#read 6, iclass 25, count 0 2006.173.11:35:55.15#ibcon#end of sib2, iclass 25, count 0 2006.173.11:35:55.15#ibcon#*mode == 0, iclass 25, count 0 2006.173.11:35:55.15#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.11:35:55.15#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.11:35:55.15#ibcon#*before write, iclass 25, count 0 2006.173.11:35:55.15#ibcon#enter sib2, iclass 25, count 0 2006.173.11:35:55.15#ibcon#flushed, iclass 25, count 0 2006.173.11:35:55.15#ibcon#about to write, iclass 25, count 0 2006.173.11:35:55.15#ibcon#wrote, iclass 25, count 0 2006.173.11:35:55.15#ibcon#about to read 3, iclass 25, count 0 2006.173.11:35:55.19#ibcon#read 3, iclass 25, count 0 2006.173.11:35:55.19#ibcon#about to read 4, iclass 25, count 0 2006.173.11:35:55.19#ibcon#read 4, iclass 25, count 0 2006.173.11:35:55.19#ibcon#about to read 5, iclass 25, count 0 2006.173.11:35:55.19#ibcon#read 5, iclass 25, count 0 2006.173.11:35:55.19#ibcon#about to read 6, iclass 25, count 0 2006.173.11:35:55.19#ibcon#read 6, iclass 25, count 0 2006.173.11:35:55.19#ibcon#end of sib2, iclass 25, count 0 2006.173.11:35:55.19#ibcon#*after write, iclass 25, count 0 2006.173.11:35:55.19#ibcon#*before return 0, iclass 25, count 0 2006.173.11:35:55.19#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.11:35:55.19#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.11:35:55.19#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.11:35:55.19#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.11:35:55.19$vck44/vb=2,4 2006.173.11:35:55.19#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.11:35:55.19#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.11:35:55.19#ibcon#ireg 11 cls_cnt 2 2006.173.11:35:55.19#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.11:35:55.25#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.11:35:55.25#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.11:35:55.25#ibcon#enter wrdev, iclass 27, count 2 2006.173.11:35:55.25#ibcon#first serial, iclass 27, count 2 2006.173.11:35:55.25#ibcon#enter sib2, iclass 27, count 2 2006.173.11:35:55.25#ibcon#flushed, iclass 27, count 2 2006.173.11:35:55.25#ibcon#about to write, iclass 27, count 2 2006.173.11:35:55.25#ibcon#wrote, iclass 27, count 2 2006.173.11:35:55.25#ibcon#about to read 3, iclass 27, count 2 2006.173.11:35:55.27#ibcon#read 3, iclass 27, count 2 2006.173.11:35:55.27#ibcon#about to read 4, iclass 27, count 2 2006.173.11:35:55.27#ibcon#read 4, iclass 27, count 2 2006.173.11:35:55.27#ibcon#about to read 5, iclass 27, count 2 2006.173.11:35:55.27#ibcon#read 5, iclass 27, count 2 2006.173.11:35:55.27#ibcon#about to read 6, iclass 27, count 2 2006.173.11:35:55.27#ibcon#read 6, iclass 27, count 2 2006.173.11:35:55.27#ibcon#end of sib2, iclass 27, count 2 2006.173.11:35:55.27#ibcon#*mode == 0, iclass 27, count 2 2006.173.11:35:55.27#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.11:35:55.27#ibcon#[27=AT02-04\r\n] 2006.173.11:35:55.27#ibcon#*before write, iclass 27, count 2 2006.173.11:35:55.27#ibcon#enter sib2, iclass 27, count 2 2006.173.11:35:55.27#ibcon#flushed, iclass 27, count 2 2006.173.11:35:55.27#ibcon#about to write, iclass 27, count 2 2006.173.11:35:55.27#ibcon#wrote, iclass 27, count 2 2006.173.11:35:55.27#ibcon#about to read 3, iclass 27, count 2 2006.173.11:35:55.30#ibcon#read 3, iclass 27, count 2 2006.173.11:35:55.30#ibcon#about to read 4, iclass 27, count 2 2006.173.11:35:55.30#ibcon#read 4, iclass 27, count 2 2006.173.11:35:55.30#ibcon#about to read 5, iclass 27, count 2 2006.173.11:35:55.30#ibcon#read 5, iclass 27, count 2 2006.173.11:35:55.30#ibcon#about to read 6, iclass 27, count 2 2006.173.11:35:55.30#ibcon#read 6, iclass 27, count 2 2006.173.11:35:55.30#ibcon#end of sib2, iclass 27, count 2 2006.173.11:35:55.30#ibcon#*after write, iclass 27, count 2 2006.173.11:35:55.30#ibcon#*before return 0, iclass 27, count 2 2006.173.11:35:55.30#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.11:35:55.30#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.11:35:55.30#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.11:35:55.30#ibcon#ireg 7 cls_cnt 0 2006.173.11:35:55.30#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.11:35:55.42#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.11:35:55.42#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.11:35:55.42#ibcon#enter wrdev, iclass 27, count 0 2006.173.11:35:55.42#ibcon#first serial, iclass 27, count 0 2006.173.11:35:55.42#ibcon#enter sib2, iclass 27, count 0 2006.173.11:35:55.42#ibcon#flushed, iclass 27, count 0 2006.173.11:35:55.42#ibcon#about to write, iclass 27, count 0 2006.173.11:35:55.42#ibcon#wrote, iclass 27, count 0 2006.173.11:35:55.42#ibcon#about to read 3, iclass 27, count 0 2006.173.11:35:55.44#ibcon#read 3, iclass 27, count 0 2006.173.11:35:55.44#ibcon#about to read 4, iclass 27, count 0 2006.173.11:35:55.44#ibcon#read 4, iclass 27, count 0 2006.173.11:35:55.44#ibcon#about to read 5, iclass 27, count 0 2006.173.11:35:55.44#ibcon#read 5, iclass 27, count 0 2006.173.11:35:55.44#ibcon#about to read 6, iclass 27, count 0 2006.173.11:35:55.44#ibcon#read 6, iclass 27, count 0 2006.173.11:35:55.44#ibcon#end of sib2, iclass 27, count 0 2006.173.11:35:55.44#ibcon#*mode == 0, iclass 27, count 0 2006.173.11:35:55.44#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.11:35:55.44#ibcon#[27=USB\r\n] 2006.173.11:35:55.44#ibcon#*before write, iclass 27, count 0 2006.173.11:35:55.44#ibcon#enter sib2, iclass 27, count 0 2006.173.11:35:55.44#ibcon#flushed, iclass 27, count 0 2006.173.11:35:55.44#ibcon#about to write, iclass 27, count 0 2006.173.11:35:55.44#ibcon#wrote, iclass 27, count 0 2006.173.11:35:55.44#ibcon#about to read 3, iclass 27, count 0 2006.173.11:35:55.47#ibcon#read 3, iclass 27, count 0 2006.173.11:35:55.47#ibcon#about to read 4, iclass 27, count 0 2006.173.11:35:55.47#ibcon#read 4, iclass 27, count 0 2006.173.11:35:55.47#ibcon#about to read 5, iclass 27, count 0 2006.173.11:35:55.47#ibcon#read 5, iclass 27, count 0 2006.173.11:35:55.47#ibcon#about to read 6, iclass 27, count 0 2006.173.11:35:55.47#ibcon#read 6, iclass 27, count 0 2006.173.11:35:55.47#ibcon#end of sib2, iclass 27, count 0 2006.173.11:35:55.47#ibcon#*after write, iclass 27, count 0 2006.173.11:35:55.47#ibcon#*before return 0, iclass 27, count 0 2006.173.11:35:55.47#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.11:35:55.47#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.11:35:55.47#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.11:35:55.47#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.11:35:55.47$vck44/vblo=3,649.99 2006.173.11:35:55.47#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.11:35:55.47#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.11:35:55.47#ibcon#ireg 17 cls_cnt 0 2006.173.11:35:55.47#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.11:35:55.47#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.11:35:55.47#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.11:35:55.47#ibcon#enter wrdev, iclass 29, count 0 2006.173.11:35:55.47#ibcon#first serial, iclass 29, count 0 2006.173.11:35:55.47#ibcon#enter sib2, iclass 29, count 0 2006.173.11:35:55.47#ibcon#flushed, iclass 29, count 0 2006.173.11:35:55.47#ibcon#about to write, iclass 29, count 0 2006.173.11:35:55.47#ibcon#wrote, iclass 29, count 0 2006.173.11:35:55.47#ibcon#about to read 3, iclass 29, count 0 2006.173.11:35:55.49#ibcon#read 3, iclass 29, count 0 2006.173.11:35:55.49#ibcon#about to read 4, iclass 29, count 0 2006.173.11:35:55.49#ibcon#read 4, iclass 29, count 0 2006.173.11:35:55.49#ibcon#about to read 5, iclass 29, count 0 2006.173.11:35:55.49#ibcon#read 5, iclass 29, count 0 2006.173.11:35:55.49#ibcon#about to read 6, iclass 29, count 0 2006.173.11:35:55.49#ibcon#read 6, iclass 29, count 0 2006.173.11:35:55.49#ibcon#end of sib2, iclass 29, count 0 2006.173.11:35:55.49#ibcon#*mode == 0, iclass 29, count 0 2006.173.11:35:55.49#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.11:35:55.49#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.11:35:55.49#ibcon#*before write, iclass 29, count 0 2006.173.11:35:55.49#ibcon#enter sib2, iclass 29, count 0 2006.173.11:35:55.49#ibcon#flushed, iclass 29, count 0 2006.173.11:35:55.49#ibcon#about to write, iclass 29, count 0 2006.173.11:35:55.49#ibcon#wrote, iclass 29, count 0 2006.173.11:35:55.49#ibcon#about to read 3, iclass 29, count 0 2006.173.11:35:55.53#ibcon#read 3, iclass 29, count 0 2006.173.11:35:55.53#ibcon#about to read 4, iclass 29, count 0 2006.173.11:35:55.53#ibcon#read 4, iclass 29, count 0 2006.173.11:35:55.53#ibcon#about to read 5, iclass 29, count 0 2006.173.11:35:55.53#ibcon#read 5, iclass 29, count 0 2006.173.11:35:55.53#ibcon#about to read 6, iclass 29, count 0 2006.173.11:35:55.53#ibcon#read 6, iclass 29, count 0 2006.173.11:35:55.53#ibcon#end of sib2, iclass 29, count 0 2006.173.11:35:55.53#ibcon#*after write, iclass 29, count 0 2006.173.11:35:55.53#ibcon#*before return 0, iclass 29, count 0 2006.173.11:35:55.53#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.11:35:55.53#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.11:35:55.53#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.11:35:55.53#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.11:35:55.53$vck44/vb=3,4 2006.173.11:35:55.53#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.11:35:55.53#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.11:35:55.53#ibcon#ireg 11 cls_cnt 2 2006.173.11:35:55.53#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.11:35:55.59#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.11:35:55.59#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.11:35:55.59#ibcon#enter wrdev, iclass 31, count 2 2006.173.11:35:55.59#ibcon#first serial, iclass 31, count 2 2006.173.11:35:55.59#ibcon#enter sib2, iclass 31, count 2 2006.173.11:35:55.59#ibcon#flushed, iclass 31, count 2 2006.173.11:35:55.59#ibcon#about to write, iclass 31, count 2 2006.173.11:35:55.59#ibcon#wrote, iclass 31, count 2 2006.173.11:35:55.59#ibcon#about to read 3, iclass 31, count 2 2006.173.11:35:55.61#ibcon#read 3, iclass 31, count 2 2006.173.11:35:55.61#ibcon#about to read 4, iclass 31, count 2 2006.173.11:35:55.61#ibcon#read 4, iclass 31, count 2 2006.173.11:35:55.61#ibcon#about to read 5, iclass 31, count 2 2006.173.11:35:55.61#ibcon#read 5, iclass 31, count 2 2006.173.11:35:55.61#ibcon#about to read 6, iclass 31, count 2 2006.173.11:35:55.61#ibcon#read 6, iclass 31, count 2 2006.173.11:35:55.61#ibcon#end of sib2, iclass 31, count 2 2006.173.11:35:55.61#ibcon#*mode == 0, iclass 31, count 2 2006.173.11:35:55.61#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.11:35:55.61#ibcon#[27=AT03-04\r\n] 2006.173.11:35:55.61#ibcon#*before write, iclass 31, count 2 2006.173.11:35:55.61#ibcon#enter sib2, iclass 31, count 2 2006.173.11:35:55.61#ibcon#flushed, iclass 31, count 2 2006.173.11:35:55.61#ibcon#about to write, iclass 31, count 2 2006.173.11:35:55.61#ibcon#wrote, iclass 31, count 2 2006.173.11:35:55.61#ibcon#about to read 3, iclass 31, count 2 2006.173.11:35:55.64#ibcon#read 3, iclass 31, count 2 2006.173.11:35:55.64#ibcon#about to read 4, iclass 31, count 2 2006.173.11:35:55.64#ibcon#read 4, iclass 31, count 2 2006.173.11:35:55.64#ibcon#about to read 5, iclass 31, count 2 2006.173.11:35:55.64#ibcon#read 5, iclass 31, count 2 2006.173.11:35:55.64#ibcon#about to read 6, iclass 31, count 2 2006.173.11:35:55.64#ibcon#read 6, iclass 31, count 2 2006.173.11:35:55.64#ibcon#end of sib2, iclass 31, count 2 2006.173.11:35:55.64#ibcon#*after write, iclass 31, count 2 2006.173.11:35:55.64#ibcon#*before return 0, iclass 31, count 2 2006.173.11:35:55.64#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.11:35:55.64#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.11:35:55.64#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.11:35:55.64#ibcon#ireg 7 cls_cnt 0 2006.173.11:35:55.64#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.11:35:55.76#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.11:35:55.76#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.11:35:55.76#ibcon#enter wrdev, iclass 31, count 0 2006.173.11:35:55.76#ibcon#first serial, iclass 31, count 0 2006.173.11:35:55.76#ibcon#enter sib2, iclass 31, count 0 2006.173.11:35:55.76#ibcon#flushed, iclass 31, count 0 2006.173.11:35:55.76#ibcon#about to write, iclass 31, count 0 2006.173.11:35:55.76#ibcon#wrote, iclass 31, count 0 2006.173.11:35:55.76#ibcon#about to read 3, iclass 31, count 0 2006.173.11:35:55.78#ibcon#read 3, iclass 31, count 0 2006.173.11:35:55.78#ibcon#about to read 4, iclass 31, count 0 2006.173.11:35:55.78#ibcon#read 4, iclass 31, count 0 2006.173.11:35:55.78#ibcon#about to read 5, iclass 31, count 0 2006.173.11:35:55.78#ibcon#read 5, iclass 31, count 0 2006.173.11:35:55.78#ibcon#about to read 6, iclass 31, count 0 2006.173.11:35:55.78#ibcon#read 6, iclass 31, count 0 2006.173.11:35:55.78#ibcon#end of sib2, iclass 31, count 0 2006.173.11:35:55.78#ibcon#*mode == 0, iclass 31, count 0 2006.173.11:35:55.78#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.11:35:55.78#ibcon#[27=USB\r\n] 2006.173.11:35:55.78#ibcon#*before write, iclass 31, count 0 2006.173.11:35:55.78#ibcon#enter sib2, iclass 31, count 0 2006.173.11:35:55.78#ibcon#flushed, iclass 31, count 0 2006.173.11:35:55.78#ibcon#about to write, iclass 31, count 0 2006.173.11:35:55.78#ibcon#wrote, iclass 31, count 0 2006.173.11:35:55.78#ibcon#about to read 3, iclass 31, count 0 2006.173.11:35:55.81#ibcon#read 3, iclass 31, count 0 2006.173.11:35:55.81#ibcon#about to read 4, iclass 31, count 0 2006.173.11:35:55.81#ibcon#read 4, iclass 31, count 0 2006.173.11:35:55.81#ibcon#about to read 5, iclass 31, count 0 2006.173.11:35:55.81#ibcon#read 5, iclass 31, count 0 2006.173.11:35:55.81#ibcon#about to read 6, iclass 31, count 0 2006.173.11:35:55.81#ibcon#read 6, iclass 31, count 0 2006.173.11:35:55.81#ibcon#end of sib2, iclass 31, count 0 2006.173.11:35:55.81#ibcon#*after write, iclass 31, count 0 2006.173.11:35:55.81#ibcon#*before return 0, iclass 31, count 0 2006.173.11:35:55.81#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.11:35:55.81#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.11:35:55.81#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.11:35:55.81#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.11:35:55.81$vck44/vblo=4,679.99 2006.173.11:35:55.81#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.11:35:55.81#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.11:35:55.81#ibcon#ireg 17 cls_cnt 0 2006.173.11:35:55.81#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.11:35:55.81#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.11:35:55.81#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.11:35:55.81#ibcon#enter wrdev, iclass 33, count 0 2006.173.11:35:55.81#ibcon#first serial, iclass 33, count 0 2006.173.11:35:55.81#ibcon#enter sib2, iclass 33, count 0 2006.173.11:35:55.81#ibcon#flushed, iclass 33, count 0 2006.173.11:35:55.81#ibcon#about to write, iclass 33, count 0 2006.173.11:35:55.81#ibcon#wrote, iclass 33, count 0 2006.173.11:35:55.81#ibcon#about to read 3, iclass 33, count 0 2006.173.11:35:55.83#ibcon#read 3, iclass 33, count 0 2006.173.11:35:55.83#ibcon#about to read 4, iclass 33, count 0 2006.173.11:35:55.83#ibcon#read 4, iclass 33, count 0 2006.173.11:35:55.83#ibcon#about to read 5, iclass 33, count 0 2006.173.11:35:55.83#ibcon#read 5, iclass 33, count 0 2006.173.11:35:55.83#ibcon#about to read 6, iclass 33, count 0 2006.173.11:35:55.83#ibcon#read 6, iclass 33, count 0 2006.173.11:35:55.83#ibcon#end of sib2, iclass 33, count 0 2006.173.11:35:55.83#ibcon#*mode == 0, iclass 33, count 0 2006.173.11:35:55.83#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.11:35:55.83#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.11:35:55.83#ibcon#*before write, iclass 33, count 0 2006.173.11:35:55.83#ibcon#enter sib2, iclass 33, count 0 2006.173.11:35:55.83#ibcon#flushed, iclass 33, count 0 2006.173.11:35:55.83#ibcon#about to write, iclass 33, count 0 2006.173.11:35:55.83#ibcon#wrote, iclass 33, count 0 2006.173.11:35:55.83#ibcon#about to read 3, iclass 33, count 0 2006.173.11:35:55.87#ibcon#read 3, iclass 33, count 0 2006.173.11:35:55.87#ibcon#about to read 4, iclass 33, count 0 2006.173.11:35:55.87#ibcon#read 4, iclass 33, count 0 2006.173.11:35:55.87#ibcon#about to read 5, iclass 33, count 0 2006.173.11:35:55.87#ibcon#read 5, iclass 33, count 0 2006.173.11:35:55.87#ibcon#about to read 6, iclass 33, count 0 2006.173.11:35:55.87#ibcon#read 6, iclass 33, count 0 2006.173.11:35:55.87#ibcon#end of sib2, iclass 33, count 0 2006.173.11:35:55.87#ibcon#*after write, iclass 33, count 0 2006.173.11:35:55.87#ibcon#*before return 0, iclass 33, count 0 2006.173.11:35:55.87#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.11:35:55.87#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.11:35:55.87#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.11:35:55.87#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.11:35:55.87$vck44/vb=4,4 2006.173.11:35:55.87#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.11:35:55.87#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.11:35:55.87#ibcon#ireg 11 cls_cnt 2 2006.173.11:35:55.87#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.11:35:55.93#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.11:35:55.93#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.11:35:55.93#ibcon#enter wrdev, iclass 35, count 2 2006.173.11:35:55.93#ibcon#first serial, iclass 35, count 2 2006.173.11:35:55.93#ibcon#enter sib2, iclass 35, count 2 2006.173.11:35:55.93#ibcon#flushed, iclass 35, count 2 2006.173.11:35:55.93#ibcon#about to write, iclass 35, count 2 2006.173.11:35:55.93#ibcon#wrote, iclass 35, count 2 2006.173.11:35:55.93#ibcon#about to read 3, iclass 35, count 2 2006.173.11:35:55.95#ibcon#read 3, iclass 35, count 2 2006.173.11:35:55.95#ibcon#about to read 4, iclass 35, count 2 2006.173.11:35:55.95#ibcon#read 4, iclass 35, count 2 2006.173.11:35:55.95#ibcon#about to read 5, iclass 35, count 2 2006.173.11:35:55.95#ibcon#read 5, iclass 35, count 2 2006.173.11:35:55.95#ibcon#about to read 6, iclass 35, count 2 2006.173.11:35:55.95#ibcon#read 6, iclass 35, count 2 2006.173.11:35:55.95#ibcon#end of sib2, iclass 35, count 2 2006.173.11:35:55.95#ibcon#*mode == 0, iclass 35, count 2 2006.173.11:35:55.95#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.11:35:55.95#ibcon#[27=AT04-04\r\n] 2006.173.11:35:55.95#ibcon#*before write, iclass 35, count 2 2006.173.11:35:55.95#ibcon#enter sib2, iclass 35, count 2 2006.173.11:35:55.95#ibcon#flushed, iclass 35, count 2 2006.173.11:35:55.95#ibcon#about to write, iclass 35, count 2 2006.173.11:35:55.95#ibcon#wrote, iclass 35, count 2 2006.173.11:35:55.95#ibcon#about to read 3, iclass 35, count 2 2006.173.11:35:55.98#ibcon#read 3, iclass 35, count 2 2006.173.11:35:55.98#ibcon#about to read 4, iclass 35, count 2 2006.173.11:35:55.98#ibcon#read 4, iclass 35, count 2 2006.173.11:35:55.98#ibcon#about to read 5, iclass 35, count 2 2006.173.11:35:55.98#ibcon#read 5, iclass 35, count 2 2006.173.11:35:55.98#ibcon#about to read 6, iclass 35, count 2 2006.173.11:35:55.98#ibcon#read 6, iclass 35, count 2 2006.173.11:35:55.98#ibcon#end of sib2, iclass 35, count 2 2006.173.11:35:55.98#ibcon#*after write, iclass 35, count 2 2006.173.11:35:55.98#ibcon#*before return 0, iclass 35, count 2 2006.173.11:35:55.98#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.11:35:55.98#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.11:35:55.98#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.11:35:55.98#ibcon#ireg 7 cls_cnt 0 2006.173.11:35:55.98#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.11:35:56.10#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.11:35:56.10#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.11:35:56.10#ibcon#enter wrdev, iclass 35, count 0 2006.173.11:35:56.10#ibcon#first serial, iclass 35, count 0 2006.173.11:35:56.10#ibcon#enter sib2, iclass 35, count 0 2006.173.11:35:56.10#ibcon#flushed, iclass 35, count 0 2006.173.11:35:56.10#ibcon#about to write, iclass 35, count 0 2006.173.11:35:56.10#ibcon#wrote, iclass 35, count 0 2006.173.11:35:56.10#ibcon#about to read 3, iclass 35, count 0 2006.173.11:35:56.12#ibcon#read 3, iclass 35, count 0 2006.173.11:35:56.12#ibcon#about to read 4, iclass 35, count 0 2006.173.11:35:56.12#ibcon#read 4, iclass 35, count 0 2006.173.11:35:56.12#ibcon#about to read 5, iclass 35, count 0 2006.173.11:35:56.12#ibcon#read 5, iclass 35, count 0 2006.173.11:35:56.12#ibcon#about to read 6, iclass 35, count 0 2006.173.11:35:56.12#ibcon#read 6, iclass 35, count 0 2006.173.11:35:56.12#ibcon#end of sib2, iclass 35, count 0 2006.173.11:35:56.12#ibcon#*mode == 0, iclass 35, count 0 2006.173.11:35:56.12#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.11:35:56.12#ibcon#[27=USB\r\n] 2006.173.11:35:56.12#ibcon#*before write, iclass 35, count 0 2006.173.11:35:56.12#ibcon#enter sib2, iclass 35, count 0 2006.173.11:35:56.12#ibcon#flushed, iclass 35, count 0 2006.173.11:35:56.12#ibcon#about to write, iclass 35, count 0 2006.173.11:35:56.12#ibcon#wrote, iclass 35, count 0 2006.173.11:35:56.12#ibcon#about to read 3, iclass 35, count 0 2006.173.11:35:56.15#ibcon#read 3, iclass 35, count 0 2006.173.11:35:56.15#ibcon#about to read 4, iclass 35, count 0 2006.173.11:35:56.15#ibcon#read 4, iclass 35, count 0 2006.173.11:35:56.15#ibcon#about to read 5, iclass 35, count 0 2006.173.11:35:56.15#ibcon#read 5, iclass 35, count 0 2006.173.11:35:56.15#ibcon#about to read 6, iclass 35, count 0 2006.173.11:35:56.15#ibcon#read 6, iclass 35, count 0 2006.173.11:35:56.15#ibcon#end of sib2, iclass 35, count 0 2006.173.11:35:56.15#ibcon#*after write, iclass 35, count 0 2006.173.11:35:56.15#ibcon#*before return 0, iclass 35, count 0 2006.173.11:35:56.15#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.11:35:56.15#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.11:35:56.15#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.11:35:56.15#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.11:35:56.15$vck44/vblo=5,709.99 2006.173.11:35:56.15#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.11:35:56.15#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.11:35:56.15#ibcon#ireg 17 cls_cnt 0 2006.173.11:35:56.15#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.11:35:56.15#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.11:35:56.15#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.11:35:56.15#ibcon#enter wrdev, iclass 37, count 0 2006.173.11:35:56.15#ibcon#first serial, iclass 37, count 0 2006.173.11:35:56.15#ibcon#enter sib2, iclass 37, count 0 2006.173.11:35:56.15#ibcon#flushed, iclass 37, count 0 2006.173.11:35:56.15#ibcon#about to write, iclass 37, count 0 2006.173.11:35:56.15#ibcon#wrote, iclass 37, count 0 2006.173.11:35:56.15#ibcon#about to read 3, iclass 37, count 0 2006.173.11:35:56.17#ibcon#read 3, iclass 37, count 0 2006.173.11:35:56.17#ibcon#about to read 4, iclass 37, count 0 2006.173.11:35:56.17#ibcon#read 4, iclass 37, count 0 2006.173.11:35:56.17#ibcon#about to read 5, iclass 37, count 0 2006.173.11:35:56.17#ibcon#read 5, iclass 37, count 0 2006.173.11:35:56.17#ibcon#about to read 6, iclass 37, count 0 2006.173.11:35:56.17#ibcon#read 6, iclass 37, count 0 2006.173.11:35:56.17#ibcon#end of sib2, iclass 37, count 0 2006.173.11:35:56.17#ibcon#*mode == 0, iclass 37, count 0 2006.173.11:35:56.17#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.11:35:56.17#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.11:35:56.17#ibcon#*before write, iclass 37, count 0 2006.173.11:35:56.17#ibcon#enter sib2, iclass 37, count 0 2006.173.11:35:56.17#ibcon#flushed, iclass 37, count 0 2006.173.11:35:56.17#ibcon#about to write, iclass 37, count 0 2006.173.11:35:56.17#ibcon#wrote, iclass 37, count 0 2006.173.11:35:56.17#ibcon#about to read 3, iclass 37, count 0 2006.173.11:35:56.21#ibcon#read 3, iclass 37, count 0 2006.173.11:35:56.21#ibcon#about to read 4, iclass 37, count 0 2006.173.11:35:56.21#ibcon#read 4, iclass 37, count 0 2006.173.11:35:56.21#ibcon#about to read 5, iclass 37, count 0 2006.173.11:35:56.21#ibcon#read 5, iclass 37, count 0 2006.173.11:35:56.21#ibcon#about to read 6, iclass 37, count 0 2006.173.11:35:56.21#ibcon#read 6, iclass 37, count 0 2006.173.11:35:56.21#ibcon#end of sib2, iclass 37, count 0 2006.173.11:35:56.21#ibcon#*after write, iclass 37, count 0 2006.173.11:35:56.21#ibcon#*before return 0, iclass 37, count 0 2006.173.11:35:56.21#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.11:35:56.21#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.11:35:56.21#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.11:35:56.21#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.11:35:56.21$vck44/vb=5,4 2006.173.11:35:56.21#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.11:35:56.21#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.11:35:56.21#ibcon#ireg 11 cls_cnt 2 2006.173.11:35:56.21#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.11:35:56.27#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.11:35:56.27#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.11:35:56.27#ibcon#enter wrdev, iclass 39, count 2 2006.173.11:35:56.27#ibcon#first serial, iclass 39, count 2 2006.173.11:35:56.27#ibcon#enter sib2, iclass 39, count 2 2006.173.11:35:56.27#ibcon#flushed, iclass 39, count 2 2006.173.11:35:56.27#ibcon#about to write, iclass 39, count 2 2006.173.11:35:56.27#ibcon#wrote, iclass 39, count 2 2006.173.11:35:56.27#ibcon#about to read 3, iclass 39, count 2 2006.173.11:35:56.29#ibcon#read 3, iclass 39, count 2 2006.173.11:35:56.29#ibcon#about to read 4, iclass 39, count 2 2006.173.11:35:56.29#ibcon#read 4, iclass 39, count 2 2006.173.11:35:56.29#ibcon#about to read 5, iclass 39, count 2 2006.173.11:35:56.29#ibcon#read 5, iclass 39, count 2 2006.173.11:35:56.29#ibcon#about to read 6, iclass 39, count 2 2006.173.11:35:56.29#ibcon#read 6, iclass 39, count 2 2006.173.11:35:56.29#ibcon#end of sib2, iclass 39, count 2 2006.173.11:35:56.29#ibcon#*mode == 0, iclass 39, count 2 2006.173.11:35:56.29#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.11:35:56.29#ibcon#[27=AT05-04\r\n] 2006.173.11:35:56.29#ibcon#*before write, iclass 39, count 2 2006.173.11:35:56.29#ibcon#enter sib2, iclass 39, count 2 2006.173.11:35:56.29#ibcon#flushed, iclass 39, count 2 2006.173.11:35:56.29#ibcon#about to write, iclass 39, count 2 2006.173.11:35:56.29#ibcon#wrote, iclass 39, count 2 2006.173.11:35:56.29#ibcon#about to read 3, iclass 39, count 2 2006.173.11:35:56.32#ibcon#read 3, iclass 39, count 2 2006.173.11:35:56.32#ibcon#about to read 4, iclass 39, count 2 2006.173.11:35:56.32#ibcon#read 4, iclass 39, count 2 2006.173.11:35:56.32#ibcon#about to read 5, iclass 39, count 2 2006.173.11:35:56.32#ibcon#read 5, iclass 39, count 2 2006.173.11:35:56.32#ibcon#about to read 6, iclass 39, count 2 2006.173.11:35:56.32#ibcon#read 6, iclass 39, count 2 2006.173.11:35:56.32#ibcon#end of sib2, iclass 39, count 2 2006.173.11:35:56.32#ibcon#*after write, iclass 39, count 2 2006.173.11:35:56.32#ibcon#*before return 0, iclass 39, count 2 2006.173.11:35:56.32#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.11:35:56.32#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.11:35:56.32#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.11:35:56.32#ibcon#ireg 7 cls_cnt 0 2006.173.11:35:56.32#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.11:35:56.44#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.11:35:56.44#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.11:35:56.44#ibcon#enter wrdev, iclass 39, count 0 2006.173.11:35:56.44#ibcon#first serial, iclass 39, count 0 2006.173.11:35:56.44#ibcon#enter sib2, iclass 39, count 0 2006.173.11:35:56.44#ibcon#flushed, iclass 39, count 0 2006.173.11:35:56.44#ibcon#about to write, iclass 39, count 0 2006.173.11:35:56.44#ibcon#wrote, iclass 39, count 0 2006.173.11:35:56.44#ibcon#about to read 3, iclass 39, count 0 2006.173.11:35:56.46#ibcon#read 3, iclass 39, count 0 2006.173.11:35:56.46#ibcon#about to read 4, iclass 39, count 0 2006.173.11:35:56.46#ibcon#read 4, iclass 39, count 0 2006.173.11:35:56.46#ibcon#about to read 5, iclass 39, count 0 2006.173.11:35:56.46#ibcon#read 5, iclass 39, count 0 2006.173.11:35:56.46#ibcon#about to read 6, iclass 39, count 0 2006.173.11:35:56.46#ibcon#read 6, iclass 39, count 0 2006.173.11:35:56.46#ibcon#end of sib2, iclass 39, count 0 2006.173.11:35:56.46#ibcon#*mode == 0, iclass 39, count 0 2006.173.11:35:56.46#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.11:35:56.46#ibcon#[27=USB\r\n] 2006.173.11:35:56.46#ibcon#*before write, iclass 39, count 0 2006.173.11:35:56.46#ibcon#enter sib2, iclass 39, count 0 2006.173.11:35:56.46#ibcon#flushed, iclass 39, count 0 2006.173.11:35:56.46#ibcon#about to write, iclass 39, count 0 2006.173.11:35:56.46#ibcon#wrote, iclass 39, count 0 2006.173.11:35:56.46#ibcon#about to read 3, iclass 39, count 0 2006.173.11:35:56.49#ibcon#read 3, iclass 39, count 0 2006.173.11:35:56.49#ibcon#about to read 4, iclass 39, count 0 2006.173.11:35:56.49#ibcon#read 4, iclass 39, count 0 2006.173.11:35:56.49#ibcon#about to read 5, iclass 39, count 0 2006.173.11:35:56.49#ibcon#read 5, iclass 39, count 0 2006.173.11:35:56.49#ibcon#about to read 6, iclass 39, count 0 2006.173.11:35:56.49#ibcon#read 6, iclass 39, count 0 2006.173.11:35:56.49#ibcon#end of sib2, iclass 39, count 0 2006.173.11:35:56.49#ibcon#*after write, iclass 39, count 0 2006.173.11:35:56.49#ibcon#*before return 0, iclass 39, count 0 2006.173.11:35:56.49#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.11:35:56.49#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.11:35:56.49#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.11:35:56.49#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.11:35:56.49$vck44/vblo=6,719.99 2006.173.11:35:56.49#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.11:35:56.49#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.11:35:56.49#ibcon#ireg 17 cls_cnt 0 2006.173.11:35:56.49#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.11:35:56.49#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.11:35:56.49#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.11:35:56.49#ibcon#enter wrdev, iclass 3, count 0 2006.173.11:35:56.49#ibcon#first serial, iclass 3, count 0 2006.173.11:35:56.49#ibcon#enter sib2, iclass 3, count 0 2006.173.11:35:56.49#ibcon#flushed, iclass 3, count 0 2006.173.11:35:56.49#ibcon#about to write, iclass 3, count 0 2006.173.11:35:56.49#ibcon#wrote, iclass 3, count 0 2006.173.11:35:56.49#ibcon#about to read 3, iclass 3, count 0 2006.173.11:35:56.51#ibcon#read 3, iclass 3, count 0 2006.173.11:35:56.51#ibcon#about to read 4, iclass 3, count 0 2006.173.11:35:56.51#ibcon#read 4, iclass 3, count 0 2006.173.11:35:56.51#ibcon#about to read 5, iclass 3, count 0 2006.173.11:35:56.51#ibcon#read 5, iclass 3, count 0 2006.173.11:35:56.51#ibcon#about to read 6, iclass 3, count 0 2006.173.11:35:56.51#ibcon#read 6, iclass 3, count 0 2006.173.11:35:56.51#ibcon#end of sib2, iclass 3, count 0 2006.173.11:35:56.51#ibcon#*mode == 0, iclass 3, count 0 2006.173.11:35:56.51#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.11:35:56.51#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.11:35:56.51#ibcon#*before write, iclass 3, count 0 2006.173.11:35:56.51#ibcon#enter sib2, iclass 3, count 0 2006.173.11:35:56.51#ibcon#flushed, iclass 3, count 0 2006.173.11:35:56.51#ibcon#about to write, iclass 3, count 0 2006.173.11:35:56.51#ibcon#wrote, iclass 3, count 0 2006.173.11:35:56.51#ibcon#about to read 3, iclass 3, count 0 2006.173.11:35:56.55#ibcon#read 3, iclass 3, count 0 2006.173.11:35:56.55#ibcon#about to read 4, iclass 3, count 0 2006.173.11:35:56.55#ibcon#read 4, iclass 3, count 0 2006.173.11:35:56.55#ibcon#about to read 5, iclass 3, count 0 2006.173.11:35:56.55#ibcon#read 5, iclass 3, count 0 2006.173.11:35:56.55#ibcon#about to read 6, iclass 3, count 0 2006.173.11:35:56.55#ibcon#read 6, iclass 3, count 0 2006.173.11:35:56.55#ibcon#end of sib2, iclass 3, count 0 2006.173.11:35:56.55#ibcon#*after write, iclass 3, count 0 2006.173.11:35:56.55#ibcon#*before return 0, iclass 3, count 0 2006.173.11:35:56.55#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.11:35:56.55#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.11:35:56.55#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.11:35:56.55#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.11:35:56.55$vck44/vb=6,4 2006.173.11:35:56.55#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.11:35:56.55#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.11:35:56.55#ibcon#ireg 11 cls_cnt 2 2006.173.11:35:56.55#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.11:35:56.61#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.11:35:56.61#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.11:35:56.61#ibcon#enter wrdev, iclass 5, count 2 2006.173.11:35:56.61#ibcon#first serial, iclass 5, count 2 2006.173.11:35:56.61#ibcon#enter sib2, iclass 5, count 2 2006.173.11:35:56.61#ibcon#flushed, iclass 5, count 2 2006.173.11:35:56.61#ibcon#about to write, iclass 5, count 2 2006.173.11:35:56.61#ibcon#wrote, iclass 5, count 2 2006.173.11:35:56.61#ibcon#about to read 3, iclass 5, count 2 2006.173.11:35:56.63#ibcon#read 3, iclass 5, count 2 2006.173.11:35:56.63#ibcon#about to read 4, iclass 5, count 2 2006.173.11:35:56.63#ibcon#read 4, iclass 5, count 2 2006.173.11:35:56.63#ibcon#about to read 5, iclass 5, count 2 2006.173.11:35:56.63#ibcon#read 5, iclass 5, count 2 2006.173.11:35:56.63#ibcon#about to read 6, iclass 5, count 2 2006.173.11:35:56.63#ibcon#read 6, iclass 5, count 2 2006.173.11:35:56.63#ibcon#end of sib2, iclass 5, count 2 2006.173.11:35:56.63#ibcon#*mode == 0, iclass 5, count 2 2006.173.11:35:56.63#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.11:35:56.63#ibcon#[27=AT06-04\r\n] 2006.173.11:35:56.63#ibcon#*before write, iclass 5, count 2 2006.173.11:35:56.63#ibcon#enter sib2, iclass 5, count 2 2006.173.11:35:56.63#ibcon#flushed, iclass 5, count 2 2006.173.11:35:56.63#ibcon#about to write, iclass 5, count 2 2006.173.11:35:56.63#ibcon#wrote, iclass 5, count 2 2006.173.11:35:56.63#ibcon#about to read 3, iclass 5, count 2 2006.173.11:35:56.66#ibcon#read 3, iclass 5, count 2 2006.173.11:35:56.66#ibcon#about to read 4, iclass 5, count 2 2006.173.11:35:56.66#ibcon#read 4, iclass 5, count 2 2006.173.11:35:56.66#ibcon#about to read 5, iclass 5, count 2 2006.173.11:35:56.66#ibcon#read 5, iclass 5, count 2 2006.173.11:35:56.66#ibcon#about to read 6, iclass 5, count 2 2006.173.11:35:56.66#ibcon#read 6, iclass 5, count 2 2006.173.11:35:56.66#ibcon#end of sib2, iclass 5, count 2 2006.173.11:35:56.66#ibcon#*after write, iclass 5, count 2 2006.173.11:35:56.66#ibcon#*before return 0, iclass 5, count 2 2006.173.11:35:56.66#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.11:35:56.66#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.11:35:56.66#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.11:35:56.66#ibcon#ireg 7 cls_cnt 0 2006.173.11:35:56.66#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.11:35:56.78#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.11:35:56.78#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.11:35:56.78#ibcon#enter wrdev, iclass 5, count 0 2006.173.11:35:56.78#ibcon#first serial, iclass 5, count 0 2006.173.11:35:56.78#ibcon#enter sib2, iclass 5, count 0 2006.173.11:35:56.78#ibcon#flushed, iclass 5, count 0 2006.173.11:35:56.78#ibcon#about to write, iclass 5, count 0 2006.173.11:35:56.78#ibcon#wrote, iclass 5, count 0 2006.173.11:35:56.78#ibcon#about to read 3, iclass 5, count 0 2006.173.11:35:56.80#ibcon#read 3, iclass 5, count 0 2006.173.11:35:56.80#ibcon#about to read 4, iclass 5, count 0 2006.173.11:35:56.80#ibcon#read 4, iclass 5, count 0 2006.173.11:35:56.80#ibcon#about to read 5, iclass 5, count 0 2006.173.11:35:56.80#ibcon#read 5, iclass 5, count 0 2006.173.11:35:56.80#ibcon#about to read 6, iclass 5, count 0 2006.173.11:35:56.80#ibcon#read 6, iclass 5, count 0 2006.173.11:35:56.80#ibcon#end of sib2, iclass 5, count 0 2006.173.11:35:56.80#ibcon#*mode == 0, iclass 5, count 0 2006.173.11:35:56.80#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.11:35:56.80#ibcon#[27=USB\r\n] 2006.173.11:35:56.80#ibcon#*before write, iclass 5, count 0 2006.173.11:35:56.80#ibcon#enter sib2, iclass 5, count 0 2006.173.11:35:56.80#ibcon#flushed, iclass 5, count 0 2006.173.11:35:56.80#ibcon#about to write, iclass 5, count 0 2006.173.11:35:56.80#ibcon#wrote, iclass 5, count 0 2006.173.11:35:56.80#ibcon#about to read 3, iclass 5, count 0 2006.173.11:35:56.83#ibcon#read 3, iclass 5, count 0 2006.173.11:35:56.83#ibcon#about to read 4, iclass 5, count 0 2006.173.11:35:56.83#ibcon#read 4, iclass 5, count 0 2006.173.11:35:56.83#ibcon#about to read 5, iclass 5, count 0 2006.173.11:35:56.83#ibcon#read 5, iclass 5, count 0 2006.173.11:35:56.83#ibcon#about to read 6, iclass 5, count 0 2006.173.11:35:56.83#ibcon#read 6, iclass 5, count 0 2006.173.11:35:56.83#ibcon#end of sib2, iclass 5, count 0 2006.173.11:35:56.83#ibcon#*after write, iclass 5, count 0 2006.173.11:35:56.83#ibcon#*before return 0, iclass 5, count 0 2006.173.11:35:56.83#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.11:35:56.83#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.11:35:56.83#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.11:35:56.83#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.11:35:56.83$vck44/vblo=7,734.99 2006.173.11:35:56.83#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.11:35:56.83#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.11:35:56.83#ibcon#ireg 17 cls_cnt 0 2006.173.11:35:56.83#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.11:35:56.83#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.11:35:56.83#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.11:35:56.83#ibcon#enter wrdev, iclass 7, count 0 2006.173.11:35:56.83#ibcon#first serial, iclass 7, count 0 2006.173.11:35:56.83#ibcon#enter sib2, iclass 7, count 0 2006.173.11:35:56.83#ibcon#flushed, iclass 7, count 0 2006.173.11:35:56.83#ibcon#about to write, iclass 7, count 0 2006.173.11:35:56.83#ibcon#wrote, iclass 7, count 0 2006.173.11:35:56.83#ibcon#about to read 3, iclass 7, count 0 2006.173.11:35:56.85#ibcon#read 3, iclass 7, count 0 2006.173.11:35:56.85#ibcon#about to read 4, iclass 7, count 0 2006.173.11:35:56.85#ibcon#read 4, iclass 7, count 0 2006.173.11:35:56.85#ibcon#about to read 5, iclass 7, count 0 2006.173.11:35:56.85#ibcon#read 5, iclass 7, count 0 2006.173.11:35:56.85#ibcon#about to read 6, iclass 7, count 0 2006.173.11:35:56.85#ibcon#read 6, iclass 7, count 0 2006.173.11:35:56.85#ibcon#end of sib2, iclass 7, count 0 2006.173.11:35:56.85#ibcon#*mode == 0, iclass 7, count 0 2006.173.11:35:56.85#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.11:35:56.85#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.11:35:56.85#ibcon#*before write, iclass 7, count 0 2006.173.11:35:56.85#ibcon#enter sib2, iclass 7, count 0 2006.173.11:35:56.85#ibcon#flushed, iclass 7, count 0 2006.173.11:35:56.85#ibcon#about to write, iclass 7, count 0 2006.173.11:35:56.85#ibcon#wrote, iclass 7, count 0 2006.173.11:35:56.85#ibcon#about to read 3, iclass 7, count 0 2006.173.11:35:56.89#ibcon#read 3, iclass 7, count 0 2006.173.11:35:56.89#ibcon#about to read 4, iclass 7, count 0 2006.173.11:35:56.89#ibcon#read 4, iclass 7, count 0 2006.173.11:35:56.89#ibcon#about to read 5, iclass 7, count 0 2006.173.11:35:56.89#ibcon#read 5, iclass 7, count 0 2006.173.11:35:56.89#ibcon#about to read 6, iclass 7, count 0 2006.173.11:35:56.89#ibcon#read 6, iclass 7, count 0 2006.173.11:35:56.89#ibcon#end of sib2, iclass 7, count 0 2006.173.11:35:56.89#ibcon#*after write, iclass 7, count 0 2006.173.11:35:56.89#ibcon#*before return 0, iclass 7, count 0 2006.173.11:35:56.89#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.11:35:56.89#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.11:35:56.89#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.11:35:56.89#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.11:35:56.89$vck44/vb=7,4 2006.173.11:35:56.89#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.11:35:56.89#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.11:35:56.89#ibcon#ireg 11 cls_cnt 2 2006.173.11:35:56.89#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.11:35:56.95#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.11:35:56.95#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.11:35:56.95#ibcon#enter wrdev, iclass 11, count 2 2006.173.11:35:56.95#ibcon#first serial, iclass 11, count 2 2006.173.11:35:56.95#ibcon#enter sib2, iclass 11, count 2 2006.173.11:35:56.95#ibcon#flushed, iclass 11, count 2 2006.173.11:35:56.95#ibcon#about to write, iclass 11, count 2 2006.173.11:35:56.95#ibcon#wrote, iclass 11, count 2 2006.173.11:35:56.95#ibcon#about to read 3, iclass 11, count 2 2006.173.11:35:56.97#ibcon#read 3, iclass 11, count 2 2006.173.11:35:56.97#ibcon#about to read 4, iclass 11, count 2 2006.173.11:35:56.97#ibcon#read 4, iclass 11, count 2 2006.173.11:35:56.97#ibcon#about to read 5, iclass 11, count 2 2006.173.11:35:56.97#ibcon#read 5, iclass 11, count 2 2006.173.11:35:56.97#ibcon#about to read 6, iclass 11, count 2 2006.173.11:35:56.97#ibcon#read 6, iclass 11, count 2 2006.173.11:35:56.97#ibcon#end of sib2, iclass 11, count 2 2006.173.11:35:56.97#ibcon#*mode == 0, iclass 11, count 2 2006.173.11:35:56.97#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.11:35:56.97#ibcon#[27=AT07-04\r\n] 2006.173.11:35:56.97#ibcon#*before write, iclass 11, count 2 2006.173.11:35:56.97#ibcon#enter sib2, iclass 11, count 2 2006.173.11:35:56.97#ibcon#flushed, iclass 11, count 2 2006.173.11:35:56.97#ibcon#about to write, iclass 11, count 2 2006.173.11:35:56.97#ibcon#wrote, iclass 11, count 2 2006.173.11:35:56.97#ibcon#about to read 3, iclass 11, count 2 2006.173.11:35:57.00#ibcon#read 3, iclass 11, count 2 2006.173.11:35:57.00#ibcon#about to read 4, iclass 11, count 2 2006.173.11:35:57.00#ibcon#read 4, iclass 11, count 2 2006.173.11:35:57.00#ibcon#about to read 5, iclass 11, count 2 2006.173.11:35:57.00#ibcon#read 5, iclass 11, count 2 2006.173.11:35:57.00#ibcon#about to read 6, iclass 11, count 2 2006.173.11:35:57.00#ibcon#read 6, iclass 11, count 2 2006.173.11:35:57.00#ibcon#end of sib2, iclass 11, count 2 2006.173.11:35:57.00#ibcon#*after write, iclass 11, count 2 2006.173.11:35:57.00#ibcon#*before return 0, iclass 11, count 2 2006.173.11:35:57.00#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.11:35:57.00#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.11:35:57.00#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.11:35:57.00#ibcon#ireg 7 cls_cnt 0 2006.173.11:35:57.00#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.11:35:57.12#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.11:35:57.12#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.11:35:57.12#ibcon#enter wrdev, iclass 11, count 0 2006.173.11:35:57.12#ibcon#first serial, iclass 11, count 0 2006.173.11:35:57.12#ibcon#enter sib2, iclass 11, count 0 2006.173.11:35:57.12#ibcon#flushed, iclass 11, count 0 2006.173.11:35:57.12#ibcon#about to write, iclass 11, count 0 2006.173.11:35:57.12#ibcon#wrote, iclass 11, count 0 2006.173.11:35:57.12#ibcon#about to read 3, iclass 11, count 0 2006.173.11:35:57.14#ibcon#read 3, iclass 11, count 0 2006.173.11:35:57.14#ibcon#about to read 4, iclass 11, count 0 2006.173.11:35:57.14#ibcon#read 4, iclass 11, count 0 2006.173.11:35:57.14#ibcon#about to read 5, iclass 11, count 0 2006.173.11:35:57.14#ibcon#read 5, iclass 11, count 0 2006.173.11:35:57.14#ibcon#about to read 6, iclass 11, count 0 2006.173.11:35:57.14#ibcon#read 6, iclass 11, count 0 2006.173.11:35:57.14#ibcon#end of sib2, iclass 11, count 0 2006.173.11:35:57.14#ibcon#*mode == 0, iclass 11, count 0 2006.173.11:35:57.14#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.11:35:57.14#ibcon#[27=USB\r\n] 2006.173.11:35:57.14#ibcon#*before write, iclass 11, count 0 2006.173.11:35:57.14#ibcon#enter sib2, iclass 11, count 0 2006.173.11:35:57.14#ibcon#flushed, iclass 11, count 0 2006.173.11:35:57.14#ibcon#about to write, iclass 11, count 0 2006.173.11:35:57.14#ibcon#wrote, iclass 11, count 0 2006.173.11:35:57.14#ibcon#about to read 3, iclass 11, count 0 2006.173.11:35:57.17#ibcon#read 3, iclass 11, count 0 2006.173.11:35:57.17#ibcon#about to read 4, iclass 11, count 0 2006.173.11:35:57.17#ibcon#read 4, iclass 11, count 0 2006.173.11:35:57.17#ibcon#about to read 5, iclass 11, count 0 2006.173.11:35:57.17#ibcon#read 5, iclass 11, count 0 2006.173.11:35:57.17#ibcon#about to read 6, iclass 11, count 0 2006.173.11:35:57.17#ibcon#read 6, iclass 11, count 0 2006.173.11:35:57.17#ibcon#end of sib2, iclass 11, count 0 2006.173.11:35:57.17#ibcon#*after write, iclass 11, count 0 2006.173.11:35:57.17#ibcon#*before return 0, iclass 11, count 0 2006.173.11:35:57.17#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.11:35:57.17#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.11:35:57.17#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.11:35:57.17#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.11:35:57.17$vck44/vblo=8,744.99 2006.173.11:35:57.17#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.11:35:57.17#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.11:35:57.17#ibcon#ireg 17 cls_cnt 0 2006.173.11:35:57.17#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.11:35:57.17#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.11:35:57.17#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.11:35:57.17#ibcon#enter wrdev, iclass 13, count 0 2006.173.11:35:57.17#ibcon#first serial, iclass 13, count 0 2006.173.11:35:57.17#ibcon#enter sib2, iclass 13, count 0 2006.173.11:35:57.17#ibcon#flushed, iclass 13, count 0 2006.173.11:35:57.17#ibcon#about to write, iclass 13, count 0 2006.173.11:35:57.17#ibcon#wrote, iclass 13, count 0 2006.173.11:35:57.17#ibcon#about to read 3, iclass 13, count 0 2006.173.11:35:57.19#ibcon#read 3, iclass 13, count 0 2006.173.11:35:57.19#ibcon#about to read 4, iclass 13, count 0 2006.173.11:35:57.19#ibcon#read 4, iclass 13, count 0 2006.173.11:35:57.19#ibcon#about to read 5, iclass 13, count 0 2006.173.11:35:57.19#ibcon#read 5, iclass 13, count 0 2006.173.11:35:57.19#ibcon#about to read 6, iclass 13, count 0 2006.173.11:35:57.19#ibcon#read 6, iclass 13, count 0 2006.173.11:35:57.19#ibcon#end of sib2, iclass 13, count 0 2006.173.11:35:57.19#ibcon#*mode == 0, iclass 13, count 0 2006.173.11:35:57.19#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.11:35:57.19#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.11:35:57.19#ibcon#*before write, iclass 13, count 0 2006.173.11:35:57.19#ibcon#enter sib2, iclass 13, count 0 2006.173.11:35:57.19#ibcon#flushed, iclass 13, count 0 2006.173.11:35:57.19#ibcon#about to write, iclass 13, count 0 2006.173.11:35:57.19#ibcon#wrote, iclass 13, count 0 2006.173.11:35:57.19#ibcon#about to read 3, iclass 13, count 0 2006.173.11:35:57.23#ibcon#read 3, iclass 13, count 0 2006.173.11:35:57.23#ibcon#about to read 4, iclass 13, count 0 2006.173.11:35:57.23#ibcon#read 4, iclass 13, count 0 2006.173.11:35:57.23#ibcon#about to read 5, iclass 13, count 0 2006.173.11:35:57.23#ibcon#read 5, iclass 13, count 0 2006.173.11:35:57.23#ibcon#about to read 6, iclass 13, count 0 2006.173.11:35:57.23#ibcon#read 6, iclass 13, count 0 2006.173.11:35:57.23#ibcon#end of sib2, iclass 13, count 0 2006.173.11:35:57.23#ibcon#*after write, iclass 13, count 0 2006.173.11:35:57.23#ibcon#*before return 0, iclass 13, count 0 2006.173.11:35:57.23#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.11:35:57.23#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.11:35:57.23#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.11:35:57.23#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.11:35:57.23$vck44/vb=8,4 2006.173.11:35:57.23#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.11:35:57.23#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.11:35:57.23#ibcon#ireg 11 cls_cnt 2 2006.173.11:35:57.23#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.11:35:57.29#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.11:35:57.29#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.11:35:57.29#ibcon#enter wrdev, iclass 15, count 2 2006.173.11:35:57.29#ibcon#first serial, iclass 15, count 2 2006.173.11:35:57.29#ibcon#enter sib2, iclass 15, count 2 2006.173.11:35:57.29#ibcon#flushed, iclass 15, count 2 2006.173.11:35:57.29#ibcon#about to write, iclass 15, count 2 2006.173.11:35:57.29#ibcon#wrote, iclass 15, count 2 2006.173.11:35:57.29#ibcon#about to read 3, iclass 15, count 2 2006.173.11:35:57.31#ibcon#read 3, iclass 15, count 2 2006.173.11:35:57.31#ibcon#about to read 4, iclass 15, count 2 2006.173.11:35:57.31#ibcon#read 4, iclass 15, count 2 2006.173.11:35:57.31#ibcon#about to read 5, iclass 15, count 2 2006.173.11:35:57.31#ibcon#read 5, iclass 15, count 2 2006.173.11:35:57.31#ibcon#about to read 6, iclass 15, count 2 2006.173.11:35:57.31#ibcon#read 6, iclass 15, count 2 2006.173.11:35:57.31#ibcon#end of sib2, iclass 15, count 2 2006.173.11:35:57.31#ibcon#*mode == 0, iclass 15, count 2 2006.173.11:35:57.31#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.11:35:57.31#ibcon#[27=AT08-04\r\n] 2006.173.11:35:57.31#ibcon#*before write, iclass 15, count 2 2006.173.11:35:57.31#ibcon#enter sib2, iclass 15, count 2 2006.173.11:35:57.31#ibcon#flushed, iclass 15, count 2 2006.173.11:35:57.31#ibcon#about to write, iclass 15, count 2 2006.173.11:35:57.31#ibcon#wrote, iclass 15, count 2 2006.173.11:35:57.31#ibcon#about to read 3, iclass 15, count 2 2006.173.11:35:57.34#ibcon#read 3, iclass 15, count 2 2006.173.11:35:57.34#ibcon#about to read 4, iclass 15, count 2 2006.173.11:35:57.34#ibcon#read 4, iclass 15, count 2 2006.173.11:35:57.34#ibcon#about to read 5, iclass 15, count 2 2006.173.11:35:57.34#ibcon#read 5, iclass 15, count 2 2006.173.11:35:57.34#ibcon#about to read 6, iclass 15, count 2 2006.173.11:35:57.34#ibcon#read 6, iclass 15, count 2 2006.173.11:35:57.34#ibcon#end of sib2, iclass 15, count 2 2006.173.11:35:57.34#ibcon#*after write, iclass 15, count 2 2006.173.11:35:57.34#ibcon#*before return 0, iclass 15, count 2 2006.173.11:35:57.34#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.11:35:57.34#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.11:35:57.34#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.11:35:57.34#ibcon#ireg 7 cls_cnt 0 2006.173.11:35:57.34#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.11:35:57.46#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.11:35:57.46#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.11:35:57.46#ibcon#enter wrdev, iclass 15, count 0 2006.173.11:35:57.46#ibcon#first serial, iclass 15, count 0 2006.173.11:35:57.46#ibcon#enter sib2, iclass 15, count 0 2006.173.11:35:57.46#ibcon#flushed, iclass 15, count 0 2006.173.11:35:57.46#ibcon#about to write, iclass 15, count 0 2006.173.11:35:57.46#ibcon#wrote, iclass 15, count 0 2006.173.11:35:57.46#ibcon#about to read 3, iclass 15, count 0 2006.173.11:35:57.48#ibcon#read 3, iclass 15, count 0 2006.173.11:35:57.48#ibcon#about to read 4, iclass 15, count 0 2006.173.11:35:57.48#ibcon#read 4, iclass 15, count 0 2006.173.11:35:57.48#ibcon#about to read 5, iclass 15, count 0 2006.173.11:35:57.48#ibcon#read 5, iclass 15, count 0 2006.173.11:35:57.48#ibcon#about to read 6, iclass 15, count 0 2006.173.11:35:57.48#ibcon#read 6, iclass 15, count 0 2006.173.11:35:57.48#ibcon#end of sib2, iclass 15, count 0 2006.173.11:35:57.48#ibcon#*mode == 0, iclass 15, count 0 2006.173.11:35:57.48#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.11:35:57.48#ibcon#[27=USB\r\n] 2006.173.11:35:57.48#ibcon#*before write, iclass 15, count 0 2006.173.11:35:57.48#ibcon#enter sib2, iclass 15, count 0 2006.173.11:35:57.48#ibcon#flushed, iclass 15, count 0 2006.173.11:35:57.48#ibcon#about to write, iclass 15, count 0 2006.173.11:35:57.48#ibcon#wrote, iclass 15, count 0 2006.173.11:35:57.48#ibcon#about to read 3, iclass 15, count 0 2006.173.11:35:57.51#ibcon#read 3, iclass 15, count 0 2006.173.11:35:57.51#ibcon#about to read 4, iclass 15, count 0 2006.173.11:35:57.51#ibcon#read 4, iclass 15, count 0 2006.173.11:35:57.51#ibcon#about to read 5, iclass 15, count 0 2006.173.11:35:57.51#ibcon#read 5, iclass 15, count 0 2006.173.11:35:57.51#ibcon#about to read 6, iclass 15, count 0 2006.173.11:35:57.51#ibcon#read 6, iclass 15, count 0 2006.173.11:35:57.51#ibcon#end of sib2, iclass 15, count 0 2006.173.11:35:57.51#ibcon#*after write, iclass 15, count 0 2006.173.11:35:57.51#ibcon#*before return 0, iclass 15, count 0 2006.173.11:35:57.51#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.11:35:57.51#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.11:35:57.51#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.11:35:57.51#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.11:35:57.51$vck44/vabw=wide 2006.173.11:35:57.51#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.11:35:57.51#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.11:35:57.51#ibcon#ireg 8 cls_cnt 0 2006.173.11:35:57.51#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.11:35:57.51#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.11:35:57.51#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.11:35:57.51#ibcon#enter wrdev, iclass 17, count 0 2006.173.11:35:57.51#ibcon#first serial, iclass 17, count 0 2006.173.11:35:57.51#ibcon#enter sib2, iclass 17, count 0 2006.173.11:35:57.51#ibcon#flushed, iclass 17, count 0 2006.173.11:35:57.51#ibcon#about to write, iclass 17, count 0 2006.173.11:35:57.51#ibcon#wrote, iclass 17, count 0 2006.173.11:35:57.51#ibcon#about to read 3, iclass 17, count 0 2006.173.11:35:57.53#ibcon#read 3, iclass 17, count 0 2006.173.11:35:57.53#ibcon#about to read 4, iclass 17, count 0 2006.173.11:35:57.53#ibcon#read 4, iclass 17, count 0 2006.173.11:35:57.53#ibcon#about to read 5, iclass 17, count 0 2006.173.11:35:57.53#ibcon#read 5, iclass 17, count 0 2006.173.11:35:57.53#ibcon#about to read 6, iclass 17, count 0 2006.173.11:35:57.53#ibcon#read 6, iclass 17, count 0 2006.173.11:35:57.53#ibcon#end of sib2, iclass 17, count 0 2006.173.11:35:57.53#ibcon#*mode == 0, iclass 17, count 0 2006.173.11:35:57.53#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.11:35:57.53#ibcon#[25=BW32\r\n] 2006.173.11:35:57.53#ibcon#*before write, iclass 17, count 0 2006.173.11:35:57.53#ibcon#enter sib2, iclass 17, count 0 2006.173.11:35:57.53#ibcon#flushed, iclass 17, count 0 2006.173.11:35:57.53#ibcon#about to write, iclass 17, count 0 2006.173.11:35:57.53#ibcon#wrote, iclass 17, count 0 2006.173.11:35:57.53#ibcon#about to read 3, iclass 17, count 0 2006.173.11:35:57.56#ibcon#read 3, iclass 17, count 0 2006.173.11:35:57.56#ibcon#about to read 4, iclass 17, count 0 2006.173.11:35:57.56#ibcon#read 4, iclass 17, count 0 2006.173.11:35:57.56#ibcon#about to read 5, iclass 17, count 0 2006.173.11:35:57.56#ibcon#read 5, iclass 17, count 0 2006.173.11:35:57.56#ibcon#about to read 6, iclass 17, count 0 2006.173.11:35:57.56#ibcon#read 6, iclass 17, count 0 2006.173.11:35:57.56#ibcon#end of sib2, iclass 17, count 0 2006.173.11:35:57.56#ibcon#*after write, iclass 17, count 0 2006.173.11:35:57.56#ibcon#*before return 0, iclass 17, count 0 2006.173.11:35:57.56#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.11:35:57.56#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.11:35:57.56#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.11:35:57.56#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.11:35:57.56$vck44/vbbw=wide 2006.173.11:35:57.56#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.11:35:57.56#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.11:35:57.56#ibcon#ireg 8 cls_cnt 0 2006.173.11:35:57.56#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.11:35:57.63#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.11:35:57.63#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.11:35:57.63#ibcon#enter wrdev, iclass 19, count 0 2006.173.11:35:57.63#ibcon#first serial, iclass 19, count 0 2006.173.11:35:57.63#ibcon#enter sib2, iclass 19, count 0 2006.173.11:35:57.63#ibcon#flushed, iclass 19, count 0 2006.173.11:35:57.63#ibcon#about to write, iclass 19, count 0 2006.173.11:35:57.63#ibcon#wrote, iclass 19, count 0 2006.173.11:35:57.63#ibcon#about to read 3, iclass 19, count 0 2006.173.11:35:57.65#ibcon#read 3, iclass 19, count 0 2006.173.11:35:57.65#ibcon#about to read 4, iclass 19, count 0 2006.173.11:35:57.65#ibcon#read 4, iclass 19, count 0 2006.173.11:35:57.65#ibcon#about to read 5, iclass 19, count 0 2006.173.11:35:57.65#ibcon#read 5, iclass 19, count 0 2006.173.11:35:57.65#ibcon#about to read 6, iclass 19, count 0 2006.173.11:35:57.65#ibcon#read 6, iclass 19, count 0 2006.173.11:35:57.65#ibcon#end of sib2, iclass 19, count 0 2006.173.11:35:57.65#ibcon#*mode == 0, iclass 19, count 0 2006.173.11:35:57.65#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.11:35:57.65#ibcon#[27=BW32\r\n] 2006.173.11:35:57.65#ibcon#*before write, iclass 19, count 0 2006.173.11:35:57.65#ibcon#enter sib2, iclass 19, count 0 2006.173.11:35:57.65#ibcon#flushed, iclass 19, count 0 2006.173.11:35:57.65#ibcon#about to write, iclass 19, count 0 2006.173.11:35:57.65#ibcon#wrote, iclass 19, count 0 2006.173.11:35:57.65#ibcon#about to read 3, iclass 19, count 0 2006.173.11:35:57.68#ibcon#read 3, iclass 19, count 0 2006.173.11:35:57.68#ibcon#about to read 4, iclass 19, count 0 2006.173.11:35:57.68#ibcon#read 4, iclass 19, count 0 2006.173.11:35:57.68#ibcon#about to read 5, iclass 19, count 0 2006.173.11:35:57.68#ibcon#read 5, iclass 19, count 0 2006.173.11:35:57.68#ibcon#about to read 6, iclass 19, count 0 2006.173.11:35:57.68#ibcon#read 6, iclass 19, count 0 2006.173.11:35:57.68#ibcon#end of sib2, iclass 19, count 0 2006.173.11:35:57.68#ibcon#*after write, iclass 19, count 0 2006.173.11:35:57.68#ibcon#*before return 0, iclass 19, count 0 2006.173.11:35:57.68#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.11:35:57.68#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.11:35:57.68#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.11:35:57.68#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.11:35:57.68$setupk4/ifdk4 2006.173.11:35:57.68$ifdk4/lo= 2006.173.11:35:57.68$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.11:35:57.68$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.11:35:57.68$ifdk4/patch= 2006.173.11:35:57.68$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.11:35:57.68$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.11:35:57.68$setupk4/!*+20s 2006.173.11:36:01.56#abcon#<5=/04 0.9 2.6 22.37 931004.3\r\n> 2006.173.11:36:01.58#abcon#{5=INTERFACE CLEAR} 2006.173.11:36:01.64#abcon#[5=S1D000X0/0*\r\n] 2006.173.11:36:11.73#abcon#<5=/04 0.9 2.6 22.37 931004.3\r\n> 2006.173.11:36:11.75#abcon#{5=INTERFACE CLEAR} 2006.173.11:36:11.81#abcon#[5=S1D000X0/0*\r\n] 2006.173.11:36:12.18$setupk4/"tpicd 2006.173.11:36:12.18$setupk4/echo=off 2006.173.11:36:12.18$setupk4/xlog=off 2006.173.11:36:12.18:!2006.173.11:37:11 2006.173.11:36:20.14#trakl#Source acquired 2006.173.11:36:20.14#flagr#flagr/antenna,acquired 2006.173.11:37:11.00:preob 2006.173.11:37:12.14/onsource/TRACKING 2006.173.11:37:12.14:!2006.173.11:37:21 2006.173.11:37:21.00:"tape 2006.173.11:37:21.00:"st=record 2006.173.11:37:21.00:data_valid=on 2006.173.11:37:21.00:midob 2006.173.11:37:21.14/onsource/TRACKING 2006.173.11:37:21.14/wx/22.36,1004.4,93 2006.173.11:37:21.37/cable/+6.5049E-03 2006.173.11:37:22.46/va/01,07,usb,yes,35,38 2006.173.11:37:22.46/va/02,06,usb,yes,35,36 2006.173.11:37:22.46/va/03,05,usb,yes,45,47 2006.173.11:37:22.46/va/04,06,usb,yes,36,38 2006.173.11:37:22.46/va/05,04,usb,yes,28,29 2006.173.11:37:22.46/va/06,03,usb,yes,40,39 2006.173.11:37:22.46/va/07,04,usb,yes,32,33 2006.173.11:37:22.46/va/08,04,usb,yes,27,33 2006.173.11:37:22.69/valo/01,524.99,yes,locked 2006.173.11:37:22.69/valo/02,534.99,yes,locked 2006.173.11:37:22.69/valo/03,564.99,yes,locked 2006.173.11:37:22.69/valo/04,624.99,yes,locked 2006.173.11:37:22.69/valo/05,734.99,yes,locked 2006.173.11:37:22.69/valo/06,814.99,yes,locked 2006.173.11:37:22.69/valo/07,864.99,yes,locked 2006.173.11:37:22.69/valo/08,884.99,yes,locked 2006.173.11:37:23.78/vb/01,04,usb,yes,29,27 2006.173.11:37:23.78/vb/02,04,usb,yes,32,31 2006.173.11:37:23.78/vb/03,04,usb,yes,29,32 2006.173.11:37:23.78/vb/04,04,usb,yes,33,32 2006.173.11:37:23.78/vb/05,04,usb,yes,26,28 2006.173.11:37:23.78/vb/06,04,usb,yes,30,26 2006.173.11:37:23.78/vb/07,04,usb,yes,30,30 2006.173.11:37:23.78/vb/08,04,usb,yes,27,31 2006.173.11:37:24.01/vblo/01,629.99,yes,locked 2006.173.11:37:24.01/vblo/02,634.99,yes,locked 2006.173.11:37:24.01/vblo/03,649.99,yes,locked 2006.173.11:37:24.01/vblo/04,679.99,yes,locked 2006.173.11:37:24.01/vblo/05,709.99,yes,locked 2006.173.11:37:24.01/vblo/06,719.99,yes,locked 2006.173.11:37:24.01/vblo/07,734.99,yes,locked 2006.173.11:37:24.01/vblo/08,744.99,yes,locked 2006.173.11:37:24.16/vabw/8 2006.173.11:37:24.31/vbbw/8 2006.173.11:37:24.40/xfe/off,on,15.0 2006.173.11:37:24.77/ifatt/23,28,28,28 2006.173.11:37:25.08/fmout-gps/S +3.97E-07 2006.173.11:37:25.12:!2006.173.11:38:01 2006.173.11:38:01.02:data_valid=off 2006.173.11:38:01.02:"et 2006.173.11:38:01.02:!+3s 2006.173.11:38:04.04:"tape 2006.173.11:38:04.05:postob 2006.173.11:38:04.17/cable/+6.5027E-03 2006.173.11:38:04.17/wx/22.35,1004.4,93 2006.173.11:38:04.23/fmout-gps/S +3.97E-07 2006.173.11:38:04.23:scan_name=173-1139,jd0606,90 2006.173.11:38:04.23:source=3c274,123049.42,122328.0,2000.0,cw 2006.173.11:38:06.14#flagr#flagr/antenna,new-source 2006.173.11:38:06.14:checkk5 2006.173.11:38:06.54/chk_autoobs//k5ts1/ autoobs is running! 2006.173.11:38:06.92/chk_autoobs//k5ts2/ autoobs is running! 2006.173.11:38:07.34/chk_autoobs//k5ts3/ autoobs is running! 2006.173.11:38:07.73/chk_autoobs//k5ts4/ autoobs is running! 2006.173.11:38:08.12/chk_obsdata//k5ts1/T1731137??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.11:38:08.54/chk_obsdata//k5ts2/T1731137??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.11:38:08.95/chk_obsdata//k5ts3/T1731137??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.11:38:09.35/chk_obsdata//k5ts4/T1731137??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.11:38:10.08/k5log//k5ts1_log_newline 2006.173.11:38:10.77/k5log//k5ts2_log_newline 2006.173.11:38:11.51/k5log//k5ts3_log_newline 2006.173.11:38:12.21/k5log//k5ts4_log_newline 2006.173.11:38:12.24/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.11:38:12.24:setupk4=1 2006.173.11:38:12.24$setupk4/echo=on 2006.173.11:38:12.24$setupk4/pcalon 2006.173.11:38:12.24$pcalon/"no phase cal control is implemented here 2006.173.11:38:12.24$setupk4/"tpicd=stop 2006.173.11:38:12.24$setupk4/"rec=synch_on 2006.173.11:38:12.24$setupk4/"rec_mode=128 2006.173.11:38:12.24$setupk4/!* 2006.173.11:38:12.24$setupk4/recpk4 2006.173.11:38:12.24$recpk4/recpatch= 2006.173.11:38:12.24$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.11:38:12.24$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.11:38:12.24$setupk4/vck44 2006.173.11:38:12.24$vck44/valo=1,524.99 2006.173.11:38:12.24#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.11:38:12.24#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.11:38:12.24#ibcon#ireg 17 cls_cnt 0 2006.173.11:38:12.24#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.11:38:12.24#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.11:38:12.24#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.11:38:12.24#ibcon#enter wrdev, iclass 40, count 0 2006.173.11:38:12.24#ibcon#first serial, iclass 40, count 0 2006.173.11:38:12.24#ibcon#enter sib2, iclass 40, count 0 2006.173.11:38:12.24#ibcon#flushed, iclass 40, count 0 2006.173.11:38:12.24#ibcon#about to write, iclass 40, count 0 2006.173.11:38:12.24#ibcon#wrote, iclass 40, count 0 2006.173.11:38:12.24#ibcon#about to read 3, iclass 40, count 0 2006.173.11:38:12.25#ibcon#read 3, iclass 40, count 0 2006.173.11:38:12.25#ibcon#about to read 4, iclass 40, count 0 2006.173.11:38:12.25#ibcon#read 4, iclass 40, count 0 2006.173.11:38:12.25#ibcon#about to read 5, iclass 40, count 0 2006.173.11:38:12.25#ibcon#read 5, iclass 40, count 0 2006.173.11:38:12.26#ibcon#about to read 6, iclass 40, count 0 2006.173.11:38:12.26#ibcon#read 6, iclass 40, count 0 2006.173.11:38:12.26#ibcon#end of sib2, iclass 40, count 0 2006.173.11:38:12.26#ibcon#*mode == 0, iclass 40, count 0 2006.173.11:38:12.26#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.11:38:12.26#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.11:38:12.26#ibcon#*before write, iclass 40, count 0 2006.173.11:38:12.26#ibcon#enter sib2, iclass 40, count 0 2006.173.11:38:12.26#ibcon#flushed, iclass 40, count 0 2006.173.11:38:12.26#ibcon#about to write, iclass 40, count 0 2006.173.11:38:12.26#ibcon#wrote, iclass 40, count 0 2006.173.11:38:12.26#ibcon#about to read 3, iclass 40, count 0 2006.173.11:38:12.30#ibcon#read 3, iclass 40, count 0 2006.173.11:38:12.30#ibcon#about to read 4, iclass 40, count 0 2006.173.11:38:12.30#ibcon#read 4, iclass 40, count 0 2006.173.11:38:12.30#ibcon#about to read 5, iclass 40, count 0 2006.173.11:38:12.30#ibcon#read 5, iclass 40, count 0 2006.173.11:38:12.30#ibcon#about to read 6, iclass 40, count 0 2006.173.11:38:12.31#ibcon#read 6, iclass 40, count 0 2006.173.11:38:12.31#ibcon#end of sib2, iclass 40, count 0 2006.173.11:38:12.31#ibcon#*after write, iclass 40, count 0 2006.173.11:38:12.31#ibcon#*before return 0, iclass 40, count 0 2006.173.11:38:12.31#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.11:38:12.31#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.11:38:12.31#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.11:38:12.31#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.11:38:12.31$vck44/va=1,7 2006.173.11:38:12.31#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.11:38:12.31#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.11:38:12.31#ibcon#ireg 11 cls_cnt 2 2006.173.11:38:12.31#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.11:38:12.31#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.11:38:12.31#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.11:38:12.31#ibcon#enter wrdev, iclass 4, count 2 2006.173.11:38:12.31#ibcon#first serial, iclass 4, count 2 2006.173.11:38:12.31#ibcon#enter sib2, iclass 4, count 2 2006.173.11:38:12.31#ibcon#flushed, iclass 4, count 2 2006.173.11:38:12.31#ibcon#about to write, iclass 4, count 2 2006.173.11:38:12.31#ibcon#wrote, iclass 4, count 2 2006.173.11:38:12.31#ibcon#about to read 3, iclass 4, count 2 2006.173.11:38:12.32#ibcon#read 3, iclass 4, count 2 2006.173.11:38:12.32#ibcon#about to read 4, iclass 4, count 2 2006.173.11:38:12.32#ibcon#read 4, iclass 4, count 2 2006.173.11:38:12.32#ibcon#about to read 5, iclass 4, count 2 2006.173.11:38:12.32#ibcon#read 5, iclass 4, count 2 2006.173.11:38:12.32#ibcon#about to read 6, iclass 4, count 2 2006.173.11:38:12.33#ibcon#read 6, iclass 4, count 2 2006.173.11:38:12.33#ibcon#end of sib2, iclass 4, count 2 2006.173.11:38:12.33#ibcon#*mode == 0, iclass 4, count 2 2006.173.11:38:12.33#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.11:38:12.33#ibcon#[25=AT01-07\r\n] 2006.173.11:38:12.33#ibcon#*before write, iclass 4, count 2 2006.173.11:38:12.33#ibcon#enter sib2, iclass 4, count 2 2006.173.11:38:12.33#ibcon#flushed, iclass 4, count 2 2006.173.11:38:12.33#ibcon#about to write, iclass 4, count 2 2006.173.11:38:12.33#ibcon#wrote, iclass 4, count 2 2006.173.11:38:12.33#ibcon#about to read 3, iclass 4, count 2 2006.173.11:38:12.35#ibcon#read 3, iclass 4, count 2 2006.173.11:38:12.35#ibcon#about to read 4, iclass 4, count 2 2006.173.11:38:12.35#ibcon#read 4, iclass 4, count 2 2006.173.11:38:12.35#ibcon#about to read 5, iclass 4, count 2 2006.173.11:38:12.35#ibcon#read 5, iclass 4, count 2 2006.173.11:38:12.35#ibcon#about to read 6, iclass 4, count 2 2006.173.11:38:12.35#ibcon#read 6, iclass 4, count 2 2006.173.11:38:12.35#ibcon#end of sib2, iclass 4, count 2 2006.173.11:38:12.35#ibcon#*after write, iclass 4, count 2 2006.173.11:38:12.36#ibcon#*before return 0, iclass 4, count 2 2006.173.11:38:12.36#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.11:38:12.36#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.11:38:12.36#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.11:38:12.36#ibcon#ireg 7 cls_cnt 0 2006.173.11:38:12.36#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.11:38:12.47#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.11:38:12.47#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.11:38:12.47#ibcon#enter wrdev, iclass 4, count 0 2006.173.11:38:12.47#ibcon#first serial, iclass 4, count 0 2006.173.11:38:12.47#ibcon#enter sib2, iclass 4, count 0 2006.173.11:38:12.47#ibcon#flushed, iclass 4, count 0 2006.173.11:38:12.47#ibcon#about to write, iclass 4, count 0 2006.173.11:38:12.48#ibcon#wrote, iclass 4, count 0 2006.173.11:38:12.48#ibcon#about to read 3, iclass 4, count 0 2006.173.11:38:12.49#ibcon#read 3, iclass 4, count 0 2006.173.11:38:12.49#ibcon#about to read 4, iclass 4, count 0 2006.173.11:38:12.49#ibcon#read 4, iclass 4, count 0 2006.173.11:38:12.49#ibcon#about to read 5, iclass 4, count 0 2006.173.11:38:12.50#ibcon#read 5, iclass 4, count 0 2006.173.11:38:12.50#ibcon#about to read 6, iclass 4, count 0 2006.173.11:38:12.50#ibcon#read 6, iclass 4, count 0 2006.173.11:38:12.50#ibcon#end of sib2, iclass 4, count 0 2006.173.11:38:12.50#ibcon#*mode == 0, iclass 4, count 0 2006.173.11:38:12.50#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.11:38:12.50#ibcon#[25=USB\r\n] 2006.173.11:38:12.50#ibcon#*before write, iclass 4, count 0 2006.173.11:38:12.50#ibcon#enter sib2, iclass 4, count 0 2006.173.11:38:12.50#ibcon#flushed, iclass 4, count 0 2006.173.11:38:12.50#ibcon#about to write, iclass 4, count 0 2006.173.11:38:12.50#ibcon#wrote, iclass 4, count 0 2006.173.11:38:12.50#ibcon#about to read 3, iclass 4, count 0 2006.173.11:38:12.52#ibcon#read 3, iclass 4, count 0 2006.173.11:38:12.52#ibcon#about to read 4, iclass 4, count 0 2006.173.11:38:12.52#ibcon#read 4, iclass 4, count 0 2006.173.11:38:12.52#ibcon#about to read 5, iclass 4, count 0 2006.173.11:38:12.52#ibcon#read 5, iclass 4, count 0 2006.173.11:38:12.52#ibcon#about to read 6, iclass 4, count 0 2006.173.11:38:12.53#ibcon#read 6, iclass 4, count 0 2006.173.11:38:12.53#ibcon#end of sib2, iclass 4, count 0 2006.173.11:38:12.53#ibcon#*after write, iclass 4, count 0 2006.173.11:38:12.53#ibcon#*before return 0, iclass 4, count 0 2006.173.11:38:12.53#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.11:38:12.53#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.11:38:12.53#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.11:38:12.53#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.11:38:12.53$vck44/valo=2,534.99 2006.173.11:38:12.53#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.11:38:12.53#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.11:38:12.53#ibcon#ireg 17 cls_cnt 0 2006.173.11:38:12.53#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.11:38:12.53#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.11:38:12.53#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.11:38:12.53#ibcon#enter wrdev, iclass 6, count 0 2006.173.11:38:12.53#ibcon#first serial, iclass 6, count 0 2006.173.11:38:12.53#ibcon#enter sib2, iclass 6, count 0 2006.173.11:38:12.53#ibcon#flushed, iclass 6, count 0 2006.173.11:38:12.53#ibcon#about to write, iclass 6, count 0 2006.173.11:38:12.53#ibcon#wrote, iclass 6, count 0 2006.173.11:38:12.53#ibcon#about to read 3, iclass 6, count 0 2006.173.11:38:12.54#ibcon#read 3, iclass 6, count 0 2006.173.11:38:12.54#ibcon#about to read 4, iclass 6, count 0 2006.173.11:38:12.54#ibcon#read 4, iclass 6, count 0 2006.173.11:38:12.54#ibcon#about to read 5, iclass 6, count 0 2006.173.11:38:12.54#ibcon#read 5, iclass 6, count 0 2006.173.11:38:12.54#ibcon#about to read 6, iclass 6, count 0 2006.173.11:38:12.55#ibcon#read 6, iclass 6, count 0 2006.173.11:38:12.55#ibcon#end of sib2, iclass 6, count 0 2006.173.11:38:12.55#ibcon#*mode == 0, iclass 6, count 0 2006.173.11:38:12.55#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.11:38:12.55#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.11:38:12.55#ibcon#*before write, iclass 6, count 0 2006.173.11:38:12.55#ibcon#enter sib2, iclass 6, count 0 2006.173.11:38:12.55#ibcon#flushed, iclass 6, count 0 2006.173.11:38:12.55#ibcon#about to write, iclass 6, count 0 2006.173.11:38:12.55#ibcon#wrote, iclass 6, count 0 2006.173.11:38:12.55#ibcon#about to read 3, iclass 6, count 0 2006.173.11:38:12.58#ibcon#read 3, iclass 6, count 0 2006.173.11:38:12.58#ibcon#about to read 4, iclass 6, count 0 2006.173.11:38:12.58#ibcon#read 4, iclass 6, count 0 2006.173.11:38:12.58#ibcon#about to read 5, iclass 6, count 0 2006.173.11:38:12.58#ibcon#read 5, iclass 6, count 0 2006.173.11:38:12.58#ibcon#about to read 6, iclass 6, count 0 2006.173.11:38:12.59#ibcon#read 6, iclass 6, count 0 2006.173.11:38:12.59#ibcon#end of sib2, iclass 6, count 0 2006.173.11:38:12.59#ibcon#*after write, iclass 6, count 0 2006.173.11:38:12.59#ibcon#*before return 0, iclass 6, count 0 2006.173.11:38:12.59#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.11:38:12.59#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.11:38:12.59#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.11:38:12.59#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.11:38:12.59$vck44/va=2,6 2006.173.11:38:12.59#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.11:38:12.59#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.11:38:12.59#ibcon#ireg 11 cls_cnt 2 2006.173.11:38:12.59#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.11:38:12.64#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.11:38:12.64#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.11:38:12.64#ibcon#enter wrdev, iclass 10, count 2 2006.173.11:38:12.64#ibcon#first serial, iclass 10, count 2 2006.173.11:38:12.64#ibcon#enter sib2, iclass 10, count 2 2006.173.11:38:12.64#ibcon#flushed, iclass 10, count 2 2006.173.11:38:12.65#ibcon#about to write, iclass 10, count 2 2006.173.11:38:12.65#ibcon#wrote, iclass 10, count 2 2006.173.11:38:12.65#ibcon#about to read 3, iclass 10, count 2 2006.173.11:38:12.66#ibcon#read 3, iclass 10, count 2 2006.173.11:38:12.66#ibcon#about to read 4, iclass 10, count 2 2006.173.11:38:12.66#ibcon#read 4, iclass 10, count 2 2006.173.11:38:12.66#ibcon#about to read 5, iclass 10, count 2 2006.173.11:38:12.66#ibcon#read 5, iclass 10, count 2 2006.173.11:38:12.66#ibcon#about to read 6, iclass 10, count 2 2006.173.11:38:12.66#ibcon#read 6, iclass 10, count 2 2006.173.11:38:12.66#ibcon#end of sib2, iclass 10, count 2 2006.173.11:38:12.66#ibcon#*mode == 0, iclass 10, count 2 2006.173.11:38:12.67#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.11:38:12.67#ibcon#[25=AT02-06\r\n] 2006.173.11:38:12.67#ibcon#*before write, iclass 10, count 2 2006.173.11:38:12.67#ibcon#enter sib2, iclass 10, count 2 2006.173.11:38:12.67#ibcon#flushed, iclass 10, count 2 2006.173.11:38:12.67#ibcon#about to write, iclass 10, count 2 2006.173.11:38:12.67#ibcon#wrote, iclass 10, count 2 2006.173.11:38:12.67#ibcon#about to read 3, iclass 10, count 2 2006.173.11:38:12.69#ibcon#read 3, iclass 10, count 2 2006.173.11:38:12.69#ibcon#about to read 4, iclass 10, count 2 2006.173.11:38:12.69#ibcon#read 4, iclass 10, count 2 2006.173.11:38:12.69#ibcon#about to read 5, iclass 10, count 2 2006.173.11:38:12.69#ibcon#read 5, iclass 10, count 2 2006.173.11:38:12.69#ibcon#about to read 6, iclass 10, count 2 2006.173.11:38:12.69#ibcon#read 6, iclass 10, count 2 2006.173.11:38:12.69#ibcon#end of sib2, iclass 10, count 2 2006.173.11:38:12.70#ibcon#*after write, iclass 10, count 2 2006.173.11:38:12.70#ibcon#*before return 0, iclass 10, count 2 2006.173.11:38:12.70#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.11:38:12.70#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.11:38:12.70#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.11:38:12.70#ibcon#ireg 7 cls_cnt 0 2006.173.11:38:12.70#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.11:38:12.81#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.11:38:12.81#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.11:38:12.81#ibcon#enter wrdev, iclass 10, count 0 2006.173.11:38:12.81#ibcon#first serial, iclass 10, count 0 2006.173.11:38:12.81#ibcon#enter sib2, iclass 10, count 0 2006.173.11:38:12.81#ibcon#flushed, iclass 10, count 0 2006.173.11:38:12.81#ibcon#about to write, iclass 10, count 0 2006.173.11:38:12.82#ibcon#wrote, iclass 10, count 0 2006.173.11:38:12.82#ibcon#about to read 3, iclass 10, count 0 2006.173.11:38:12.83#ibcon#read 3, iclass 10, count 0 2006.173.11:38:12.83#ibcon#about to read 4, iclass 10, count 0 2006.173.11:38:12.83#ibcon#read 4, iclass 10, count 0 2006.173.11:38:12.83#ibcon#about to read 5, iclass 10, count 0 2006.173.11:38:12.83#ibcon#read 5, iclass 10, count 0 2006.173.11:38:12.83#ibcon#about to read 6, iclass 10, count 0 2006.173.11:38:12.84#ibcon#read 6, iclass 10, count 0 2006.173.11:38:12.84#ibcon#end of sib2, iclass 10, count 0 2006.173.11:38:12.84#ibcon#*mode == 0, iclass 10, count 0 2006.173.11:38:12.84#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.11:38:12.84#ibcon#[25=USB\r\n] 2006.173.11:38:12.84#ibcon#*before write, iclass 10, count 0 2006.173.11:38:12.84#ibcon#enter sib2, iclass 10, count 0 2006.173.11:38:12.84#ibcon#flushed, iclass 10, count 0 2006.173.11:38:12.84#ibcon#about to write, iclass 10, count 0 2006.173.11:38:12.84#ibcon#wrote, iclass 10, count 0 2006.173.11:38:12.84#ibcon#about to read 3, iclass 10, count 0 2006.173.11:38:12.86#ibcon#read 3, iclass 10, count 0 2006.173.11:38:12.86#ibcon#about to read 4, iclass 10, count 0 2006.173.11:38:12.86#ibcon#read 4, iclass 10, count 0 2006.173.11:38:12.86#ibcon#about to read 5, iclass 10, count 0 2006.173.11:38:12.86#ibcon#read 5, iclass 10, count 0 2006.173.11:38:12.86#ibcon#about to read 6, iclass 10, count 0 2006.173.11:38:12.86#ibcon#read 6, iclass 10, count 0 2006.173.11:38:12.86#ibcon#end of sib2, iclass 10, count 0 2006.173.11:38:12.86#ibcon#*after write, iclass 10, count 0 2006.173.11:38:12.87#ibcon#*before return 0, iclass 10, count 0 2006.173.11:38:12.87#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.11:38:12.87#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.11:38:12.87#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.11:38:12.87#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.11:38:12.87$vck44/valo=3,564.99 2006.173.11:38:12.87#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.11:38:12.87#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.11:38:12.87#ibcon#ireg 17 cls_cnt 0 2006.173.11:38:12.87#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.11:38:12.87#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.11:38:12.87#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.11:38:12.87#ibcon#enter wrdev, iclass 12, count 0 2006.173.11:38:12.87#ibcon#first serial, iclass 12, count 0 2006.173.11:38:12.87#ibcon#enter sib2, iclass 12, count 0 2006.173.11:38:12.87#ibcon#flushed, iclass 12, count 0 2006.173.11:38:12.87#ibcon#about to write, iclass 12, count 0 2006.173.11:38:12.87#ibcon#wrote, iclass 12, count 0 2006.173.11:38:12.87#ibcon#about to read 3, iclass 12, count 0 2006.173.11:38:12.88#ibcon#read 3, iclass 12, count 0 2006.173.11:38:12.88#ibcon#about to read 4, iclass 12, count 0 2006.173.11:38:12.88#ibcon#read 4, iclass 12, count 0 2006.173.11:38:12.88#ibcon#about to read 5, iclass 12, count 0 2006.173.11:38:12.88#ibcon#read 5, iclass 12, count 0 2006.173.11:38:12.88#ibcon#about to read 6, iclass 12, count 0 2006.173.11:38:12.88#ibcon#read 6, iclass 12, count 0 2006.173.11:38:12.88#ibcon#end of sib2, iclass 12, count 0 2006.173.11:38:12.88#ibcon#*mode == 0, iclass 12, count 0 2006.173.11:38:12.88#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.11:38:12.89#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.11:38:12.89#ibcon#*before write, iclass 12, count 0 2006.173.11:38:12.89#ibcon#enter sib2, iclass 12, count 0 2006.173.11:38:12.89#ibcon#flushed, iclass 12, count 0 2006.173.11:38:12.89#ibcon#about to write, iclass 12, count 0 2006.173.11:38:12.89#ibcon#wrote, iclass 12, count 0 2006.173.11:38:12.89#ibcon#about to read 3, iclass 12, count 0 2006.173.11:38:12.92#ibcon#read 3, iclass 12, count 0 2006.173.11:38:12.92#ibcon#about to read 4, iclass 12, count 0 2006.173.11:38:12.92#ibcon#read 4, iclass 12, count 0 2006.173.11:38:12.92#ibcon#about to read 5, iclass 12, count 0 2006.173.11:38:12.92#ibcon#read 5, iclass 12, count 0 2006.173.11:38:12.92#ibcon#about to read 6, iclass 12, count 0 2006.173.11:38:12.92#ibcon#read 6, iclass 12, count 0 2006.173.11:38:12.93#ibcon#end of sib2, iclass 12, count 0 2006.173.11:38:12.93#ibcon#*after write, iclass 12, count 0 2006.173.11:38:12.93#ibcon#*before return 0, iclass 12, count 0 2006.173.11:38:12.93#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.11:38:12.93#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.11:38:12.93#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.11:38:12.93#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.11:38:12.93$vck44/va=3,5 2006.173.11:38:12.93#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.11:38:12.93#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.11:38:12.93#ibcon#ireg 11 cls_cnt 2 2006.173.11:38:12.93#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.11:38:12.98#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.11:38:12.98#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.11:38:12.98#ibcon#enter wrdev, iclass 14, count 2 2006.173.11:38:12.98#ibcon#first serial, iclass 14, count 2 2006.173.11:38:12.98#ibcon#enter sib2, iclass 14, count 2 2006.173.11:38:12.98#ibcon#flushed, iclass 14, count 2 2006.173.11:38:12.98#ibcon#about to write, iclass 14, count 2 2006.173.11:38:12.99#ibcon#wrote, iclass 14, count 2 2006.173.11:38:12.99#ibcon#about to read 3, iclass 14, count 2 2006.173.11:38:13.00#ibcon#read 3, iclass 14, count 2 2006.173.11:38:13.00#ibcon#about to read 4, iclass 14, count 2 2006.173.11:38:13.00#ibcon#read 4, iclass 14, count 2 2006.173.11:38:13.00#ibcon#about to read 5, iclass 14, count 2 2006.173.11:38:13.00#ibcon#read 5, iclass 14, count 2 2006.173.11:38:13.00#ibcon#about to read 6, iclass 14, count 2 2006.173.11:38:13.00#ibcon#read 6, iclass 14, count 2 2006.173.11:38:13.00#ibcon#end of sib2, iclass 14, count 2 2006.173.11:38:13.01#ibcon#*mode == 0, iclass 14, count 2 2006.173.11:38:13.01#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.11:38:13.01#ibcon#[25=AT03-05\r\n] 2006.173.11:38:13.01#ibcon#*before write, iclass 14, count 2 2006.173.11:38:13.01#ibcon#enter sib2, iclass 14, count 2 2006.173.11:38:13.01#ibcon#flushed, iclass 14, count 2 2006.173.11:38:13.01#ibcon#about to write, iclass 14, count 2 2006.173.11:38:13.01#ibcon#wrote, iclass 14, count 2 2006.173.11:38:13.01#ibcon#about to read 3, iclass 14, count 2 2006.173.11:38:13.03#ibcon#read 3, iclass 14, count 2 2006.173.11:38:13.03#ibcon#about to read 4, iclass 14, count 2 2006.173.11:38:13.03#ibcon#read 4, iclass 14, count 2 2006.173.11:38:13.03#ibcon#about to read 5, iclass 14, count 2 2006.173.11:38:13.03#ibcon#read 5, iclass 14, count 2 2006.173.11:38:13.03#ibcon#about to read 6, iclass 14, count 2 2006.173.11:38:13.03#ibcon#read 6, iclass 14, count 2 2006.173.11:38:13.03#ibcon#end of sib2, iclass 14, count 2 2006.173.11:38:13.04#ibcon#*after write, iclass 14, count 2 2006.173.11:38:13.04#ibcon#*before return 0, iclass 14, count 2 2006.173.11:38:13.04#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.11:38:13.04#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.11:38:13.04#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.11:38:13.04#ibcon#ireg 7 cls_cnt 0 2006.173.11:38:13.04#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.11:38:13.15#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.11:38:13.16#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.11:38:13.16#ibcon#enter wrdev, iclass 14, count 0 2006.173.11:38:13.16#ibcon#first serial, iclass 14, count 0 2006.173.11:38:13.16#ibcon#enter sib2, iclass 14, count 0 2006.173.11:38:13.16#ibcon#flushed, iclass 14, count 0 2006.173.11:38:13.16#ibcon#about to write, iclass 14, count 0 2006.173.11:38:13.16#ibcon#wrote, iclass 14, count 0 2006.173.11:38:13.16#ibcon#about to read 3, iclass 14, count 0 2006.173.11:38:13.17#ibcon#read 3, iclass 14, count 0 2006.173.11:38:13.17#ibcon#about to read 4, iclass 14, count 0 2006.173.11:38:13.17#ibcon#read 4, iclass 14, count 0 2006.173.11:38:13.17#ibcon#about to read 5, iclass 14, count 0 2006.173.11:38:13.17#ibcon#read 5, iclass 14, count 0 2006.173.11:38:13.17#ibcon#about to read 6, iclass 14, count 0 2006.173.11:38:13.17#ibcon#read 6, iclass 14, count 0 2006.173.11:38:13.17#ibcon#end of sib2, iclass 14, count 0 2006.173.11:38:13.17#ibcon#*mode == 0, iclass 14, count 0 2006.173.11:38:13.17#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.11:38:13.17#ibcon#[25=USB\r\n] 2006.173.11:38:13.18#ibcon#*before write, iclass 14, count 0 2006.173.11:38:13.18#ibcon#enter sib2, iclass 14, count 0 2006.173.11:38:13.18#ibcon#flushed, iclass 14, count 0 2006.173.11:38:13.18#ibcon#about to write, iclass 14, count 0 2006.173.11:38:13.18#ibcon#wrote, iclass 14, count 0 2006.173.11:38:13.18#ibcon#about to read 3, iclass 14, count 0 2006.173.11:38:13.20#ibcon#read 3, iclass 14, count 0 2006.173.11:38:13.20#ibcon#about to read 4, iclass 14, count 0 2006.173.11:38:13.20#ibcon#read 4, iclass 14, count 0 2006.173.11:38:13.20#ibcon#about to read 5, iclass 14, count 0 2006.173.11:38:13.20#ibcon#read 5, iclass 14, count 0 2006.173.11:38:13.20#ibcon#about to read 6, iclass 14, count 0 2006.173.11:38:13.20#ibcon#read 6, iclass 14, count 0 2006.173.11:38:13.20#ibcon#end of sib2, iclass 14, count 0 2006.173.11:38:13.21#ibcon#*after write, iclass 14, count 0 2006.173.11:38:13.21#ibcon#*before return 0, iclass 14, count 0 2006.173.11:38:13.21#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.11:38:13.21#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.11:38:13.21#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.11:38:13.21#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.11:38:13.21$vck44/valo=4,624.99 2006.173.11:38:13.21#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.11:38:13.21#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.11:38:13.21#ibcon#ireg 17 cls_cnt 0 2006.173.11:38:13.21#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.11:38:13.21#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.11:38:13.21#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.11:38:13.21#ibcon#enter wrdev, iclass 16, count 0 2006.173.11:38:13.21#ibcon#first serial, iclass 16, count 0 2006.173.11:38:13.21#ibcon#enter sib2, iclass 16, count 0 2006.173.11:38:13.21#ibcon#flushed, iclass 16, count 0 2006.173.11:38:13.21#ibcon#about to write, iclass 16, count 0 2006.173.11:38:13.21#ibcon#wrote, iclass 16, count 0 2006.173.11:38:13.21#ibcon#about to read 3, iclass 16, count 0 2006.173.11:38:13.22#ibcon#read 3, iclass 16, count 0 2006.173.11:38:13.22#ibcon#about to read 4, iclass 16, count 0 2006.173.11:38:13.22#ibcon#read 4, iclass 16, count 0 2006.173.11:38:13.22#ibcon#about to read 5, iclass 16, count 0 2006.173.11:38:13.22#ibcon#read 5, iclass 16, count 0 2006.173.11:38:13.22#ibcon#about to read 6, iclass 16, count 0 2006.173.11:38:13.22#ibcon#read 6, iclass 16, count 0 2006.173.11:38:13.22#ibcon#end of sib2, iclass 16, count 0 2006.173.11:38:13.22#ibcon#*mode == 0, iclass 16, count 0 2006.173.11:38:13.22#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.11:38:13.23#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.11:38:13.23#ibcon#*before write, iclass 16, count 0 2006.173.11:38:13.23#ibcon#enter sib2, iclass 16, count 0 2006.173.11:38:13.23#ibcon#flushed, iclass 16, count 0 2006.173.11:38:13.23#ibcon#about to write, iclass 16, count 0 2006.173.11:38:13.23#ibcon#wrote, iclass 16, count 0 2006.173.11:38:13.23#ibcon#about to read 3, iclass 16, count 0 2006.173.11:38:13.26#ibcon#read 3, iclass 16, count 0 2006.173.11:38:13.26#ibcon#about to read 4, iclass 16, count 0 2006.173.11:38:13.27#ibcon#read 4, iclass 16, count 0 2006.173.11:38:13.27#ibcon#about to read 5, iclass 16, count 0 2006.173.11:38:13.27#ibcon#read 5, iclass 16, count 0 2006.173.11:38:13.27#ibcon#about to read 6, iclass 16, count 0 2006.173.11:38:13.27#ibcon#read 6, iclass 16, count 0 2006.173.11:38:13.27#ibcon#end of sib2, iclass 16, count 0 2006.173.11:38:13.27#ibcon#*after write, iclass 16, count 0 2006.173.11:38:13.27#ibcon#*before return 0, iclass 16, count 0 2006.173.11:38:13.27#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.11:38:13.27#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.11:38:13.27#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.11:38:13.27#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.11:38:13.27$vck44/va=4,6 2006.173.11:38:13.27#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.11:38:13.27#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.11:38:13.27#ibcon#ireg 11 cls_cnt 2 2006.173.11:38:13.27#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.11:38:13.32#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.11:38:13.32#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.11:38:13.32#ibcon#enter wrdev, iclass 18, count 2 2006.173.11:38:13.32#ibcon#first serial, iclass 18, count 2 2006.173.11:38:13.32#ibcon#enter sib2, iclass 18, count 2 2006.173.11:38:13.32#ibcon#flushed, iclass 18, count 2 2006.173.11:38:13.32#ibcon#about to write, iclass 18, count 2 2006.173.11:38:13.33#ibcon#wrote, iclass 18, count 2 2006.173.11:38:13.33#ibcon#about to read 3, iclass 18, count 2 2006.173.11:38:13.34#ibcon#read 3, iclass 18, count 2 2006.173.11:38:13.34#ibcon#about to read 4, iclass 18, count 2 2006.173.11:38:13.34#ibcon#read 4, iclass 18, count 2 2006.173.11:38:13.34#ibcon#about to read 5, iclass 18, count 2 2006.173.11:38:13.34#ibcon#read 5, iclass 18, count 2 2006.173.11:38:13.34#ibcon#about to read 6, iclass 18, count 2 2006.173.11:38:13.35#ibcon#read 6, iclass 18, count 2 2006.173.11:38:13.35#ibcon#end of sib2, iclass 18, count 2 2006.173.11:38:13.35#ibcon#*mode == 0, iclass 18, count 2 2006.173.11:38:13.35#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.11:38:13.35#ibcon#[25=AT04-06\r\n] 2006.173.11:38:13.35#ibcon#*before write, iclass 18, count 2 2006.173.11:38:13.35#ibcon#enter sib2, iclass 18, count 2 2006.173.11:38:13.35#ibcon#flushed, iclass 18, count 2 2006.173.11:38:13.35#ibcon#about to write, iclass 18, count 2 2006.173.11:38:13.35#ibcon#wrote, iclass 18, count 2 2006.173.11:38:13.35#ibcon#about to read 3, iclass 18, count 2 2006.173.11:38:13.37#ibcon#read 3, iclass 18, count 2 2006.173.11:38:13.37#ibcon#about to read 4, iclass 18, count 2 2006.173.11:38:13.37#ibcon#read 4, iclass 18, count 2 2006.173.11:38:13.37#ibcon#about to read 5, iclass 18, count 2 2006.173.11:38:13.37#ibcon#read 5, iclass 18, count 2 2006.173.11:38:13.38#ibcon#about to read 6, iclass 18, count 2 2006.173.11:38:13.38#ibcon#read 6, iclass 18, count 2 2006.173.11:38:13.38#ibcon#end of sib2, iclass 18, count 2 2006.173.11:38:13.38#ibcon#*after write, iclass 18, count 2 2006.173.11:38:13.38#ibcon#*before return 0, iclass 18, count 2 2006.173.11:38:13.38#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.11:38:13.38#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.11:38:13.38#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.11:38:13.38#ibcon#ireg 7 cls_cnt 0 2006.173.11:38:13.38#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.11:38:13.49#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.11:38:13.49#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.11:38:13.49#ibcon#enter wrdev, iclass 18, count 0 2006.173.11:38:13.49#ibcon#first serial, iclass 18, count 0 2006.173.11:38:13.49#ibcon#enter sib2, iclass 18, count 0 2006.173.11:38:13.49#ibcon#flushed, iclass 18, count 0 2006.173.11:38:13.49#ibcon#about to write, iclass 18, count 0 2006.173.11:38:13.50#ibcon#wrote, iclass 18, count 0 2006.173.11:38:13.50#ibcon#about to read 3, iclass 18, count 0 2006.173.11:38:13.51#ibcon#read 3, iclass 18, count 0 2006.173.11:38:13.51#ibcon#about to read 4, iclass 18, count 0 2006.173.11:38:13.51#ibcon#read 4, iclass 18, count 0 2006.173.11:38:13.51#ibcon#about to read 5, iclass 18, count 0 2006.173.11:38:13.51#ibcon#read 5, iclass 18, count 0 2006.173.11:38:13.52#ibcon#about to read 6, iclass 18, count 0 2006.173.11:38:13.52#ibcon#read 6, iclass 18, count 0 2006.173.11:38:13.52#ibcon#end of sib2, iclass 18, count 0 2006.173.11:38:13.52#ibcon#*mode == 0, iclass 18, count 0 2006.173.11:38:13.52#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.11:38:13.52#ibcon#[25=USB\r\n] 2006.173.11:38:13.52#ibcon#*before write, iclass 18, count 0 2006.173.11:38:13.52#ibcon#enter sib2, iclass 18, count 0 2006.173.11:38:13.52#ibcon#flushed, iclass 18, count 0 2006.173.11:38:13.52#ibcon#about to write, iclass 18, count 0 2006.173.11:38:13.52#ibcon#wrote, iclass 18, count 0 2006.173.11:38:13.52#ibcon#about to read 3, iclass 18, count 0 2006.173.11:38:13.54#ibcon#read 3, iclass 18, count 0 2006.173.11:38:13.54#ibcon#about to read 4, iclass 18, count 0 2006.173.11:38:13.54#ibcon#read 4, iclass 18, count 0 2006.173.11:38:13.54#ibcon#about to read 5, iclass 18, count 0 2006.173.11:38:13.54#ibcon#read 5, iclass 18, count 0 2006.173.11:38:13.54#ibcon#about to read 6, iclass 18, count 0 2006.173.11:38:13.54#ibcon#read 6, iclass 18, count 0 2006.173.11:38:13.55#ibcon#end of sib2, iclass 18, count 0 2006.173.11:38:13.55#ibcon#*after write, iclass 18, count 0 2006.173.11:38:13.55#ibcon#*before return 0, iclass 18, count 0 2006.173.11:38:13.55#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.11:38:13.55#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.11:38:13.55#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.11:38:13.55#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.11:38:13.55$vck44/valo=5,734.99 2006.173.11:38:13.55#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.11:38:13.55#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.11:38:13.55#ibcon#ireg 17 cls_cnt 0 2006.173.11:38:13.55#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.11:38:13.55#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.11:38:13.55#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.11:38:13.55#ibcon#enter wrdev, iclass 20, count 0 2006.173.11:38:13.55#ibcon#first serial, iclass 20, count 0 2006.173.11:38:13.55#ibcon#enter sib2, iclass 20, count 0 2006.173.11:38:13.55#ibcon#flushed, iclass 20, count 0 2006.173.11:38:13.55#ibcon#about to write, iclass 20, count 0 2006.173.11:38:13.55#ibcon#wrote, iclass 20, count 0 2006.173.11:38:13.55#ibcon#about to read 3, iclass 20, count 0 2006.173.11:38:13.56#ibcon#read 3, iclass 20, count 0 2006.173.11:38:13.56#ibcon#about to read 4, iclass 20, count 0 2006.173.11:38:13.56#ibcon#read 4, iclass 20, count 0 2006.173.11:38:13.56#ibcon#about to read 5, iclass 20, count 0 2006.173.11:38:13.56#ibcon#read 5, iclass 20, count 0 2006.173.11:38:13.56#ibcon#about to read 6, iclass 20, count 0 2006.173.11:38:13.57#ibcon#read 6, iclass 20, count 0 2006.173.11:38:13.57#ibcon#end of sib2, iclass 20, count 0 2006.173.11:38:13.57#ibcon#*mode == 0, iclass 20, count 0 2006.173.11:38:13.57#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.11:38:13.57#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.11:38:13.57#ibcon#*before write, iclass 20, count 0 2006.173.11:38:13.57#ibcon#enter sib2, iclass 20, count 0 2006.173.11:38:13.57#ibcon#flushed, iclass 20, count 0 2006.173.11:38:13.57#ibcon#about to write, iclass 20, count 0 2006.173.11:38:13.57#ibcon#wrote, iclass 20, count 0 2006.173.11:38:13.57#ibcon#about to read 3, iclass 20, count 0 2006.173.11:38:13.60#ibcon#read 3, iclass 20, count 0 2006.173.11:38:13.60#ibcon#about to read 4, iclass 20, count 0 2006.173.11:38:13.60#ibcon#read 4, iclass 20, count 0 2006.173.11:38:13.60#ibcon#about to read 5, iclass 20, count 0 2006.173.11:38:13.60#ibcon#read 5, iclass 20, count 0 2006.173.11:38:13.60#ibcon#about to read 6, iclass 20, count 0 2006.173.11:38:13.61#ibcon#read 6, iclass 20, count 0 2006.173.11:38:13.61#ibcon#end of sib2, iclass 20, count 0 2006.173.11:38:13.61#ibcon#*after write, iclass 20, count 0 2006.173.11:38:13.61#ibcon#*before return 0, iclass 20, count 0 2006.173.11:38:13.61#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.11:38:13.61#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.11:38:13.61#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.11:38:13.61#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.11:38:13.61$vck44/va=5,4 2006.173.11:38:13.61#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.11:38:13.61#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.11:38:13.61#ibcon#ireg 11 cls_cnt 2 2006.173.11:38:13.61#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.11:38:13.66#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.11:38:13.66#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.11:38:13.66#ibcon#enter wrdev, iclass 22, count 2 2006.173.11:38:13.66#ibcon#first serial, iclass 22, count 2 2006.173.11:38:13.66#ibcon#enter sib2, iclass 22, count 2 2006.173.11:38:13.66#ibcon#flushed, iclass 22, count 2 2006.173.11:38:13.66#ibcon#about to write, iclass 22, count 2 2006.173.11:38:13.67#ibcon#wrote, iclass 22, count 2 2006.173.11:38:13.67#ibcon#about to read 3, iclass 22, count 2 2006.173.11:38:13.68#ibcon#read 3, iclass 22, count 2 2006.173.11:38:13.68#ibcon#about to read 4, iclass 22, count 2 2006.173.11:38:13.68#ibcon#read 4, iclass 22, count 2 2006.173.11:38:13.68#ibcon#about to read 5, iclass 22, count 2 2006.173.11:38:13.68#ibcon#read 5, iclass 22, count 2 2006.173.11:38:13.68#ibcon#about to read 6, iclass 22, count 2 2006.173.11:38:13.68#ibcon#read 6, iclass 22, count 2 2006.173.11:38:13.68#ibcon#end of sib2, iclass 22, count 2 2006.173.11:38:13.69#ibcon#*mode == 0, iclass 22, count 2 2006.173.11:38:13.69#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.11:38:13.69#ibcon#[25=AT05-04\r\n] 2006.173.11:38:13.69#ibcon#*before write, iclass 22, count 2 2006.173.11:38:13.69#ibcon#enter sib2, iclass 22, count 2 2006.173.11:38:13.69#ibcon#flushed, iclass 22, count 2 2006.173.11:38:13.69#ibcon#about to write, iclass 22, count 2 2006.173.11:38:13.69#ibcon#wrote, iclass 22, count 2 2006.173.11:38:13.69#ibcon#about to read 3, iclass 22, count 2 2006.173.11:38:13.71#ibcon#read 3, iclass 22, count 2 2006.173.11:38:13.71#ibcon#about to read 4, iclass 22, count 2 2006.173.11:38:13.71#ibcon#read 4, iclass 22, count 2 2006.173.11:38:13.71#ibcon#about to read 5, iclass 22, count 2 2006.173.11:38:13.71#ibcon#read 5, iclass 22, count 2 2006.173.11:38:13.71#ibcon#about to read 6, iclass 22, count 2 2006.173.11:38:13.71#ibcon#read 6, iclass 22, count 2 2006.173.11:38:13.71#ibcon#end of sib2, iclass 22, count 2 2006.173.11:38:13.71#ibcon#*after write, iclass 22, count 2 2006.173.11:38:13.72#ibcon#*before return 0, iclass 22, count 2 2006.173.11:38:13.72#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.11:38:13.72#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.11:38:13.72#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.11:38:13.72#ibcon#ireg 7 cls_cnt 0 2006.173.11:38:13.72#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.11:38:13.76#abcon#<5=/03 0.9 1.7 22.35 931004.4\r\n> 2006.173.11:38:13.78#abcon#{5=INTERFACE CLEAR} 2006.173.11:38:13.83#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.11:38:13.83#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.11:38:13.83#ibcon#enter wrdev, iclass 22, count 0 2006.173.11:38:13.83#ibcon#first serial, iclass 22, count 0 2006.173.11:38:13.83#ibcon#enter sib2, iclass 22, count 0 2006.173.11:38:13.83#ibcon#flushed, iclass 22, count 0 2006.173.11:38:13.83#ibcon#about to write, iclass 22, count 0 2006.173.11:38:13.84#ibcon#wrote, iclass 22, count 0 2006.173.11:38:13.84#ibcon#about to read 3, iclass 22, count 0 2006.173.11:38:13.84#abcon#[5=S1D000X0/0*\r\n] 2006.173.11:38:13.85#ibcon#read 3, iclass 22, count 0 2006.173.11:38:13.85#ibcon#about to read 4, iclass 22, count 0 2006.173.11:38:13.85#ibcon#read 4, iclass 22, count 0 2006.173.11:38:13.85#ibcon#about to read 5, iclass 22, count 0 2006.173.11:38:13.85#ibcon#read 5, iclass 22, count 0 2006.173.11:38:13.85#ibcon#about to read 6, iclass 22, count 0 2006.173.11:38:13.86#ibcon#read 6, iclass 22, count 0 2006.173.11:38:13.86#ibcon#end of sib2, iclass 22, count 0 2006.173.11:38:13.86#ibcon#*mode == 0, iclass 22, count 0 2006.173.11:38:13.86#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.11:38:13.86#ibcon#[25=USB\r\n] 2006.173.11:38:13.86#ibcon#*before write, iclass 22, count 0 2006.173.11:38:13.86#ibcon#enter sib2, iclass 22, count 0 2006.173.11:38:13.86#ibcon#flushed, iclass 22, count 0 2006.173.11:38:13.86#ibcon#about to write, iclass 22, count 0 2006.173.11:38:13.86#ibcon#wrote, iclass 22, count 0 2006.173.11:38:13.86#ibcon#about to read 3, iclass 22, count 0 2006.173.11:38:13.88#ibcon#read 3, iclass 22, count 0 2006.173.11:38:13.88#ibcon#about to read 4, iclass 22, count 0 2006.173.11:38:13.88#ibcon#read 4, iclass 22, count 0 2006.173.11:38:13.88#ibcon#about to read 5, iclass 22, count 0 2006.173.11:38:13.88#ibcon#read 5, iclass 22, count 0 2006.173.11:38:13.88#ibcon#about to read 6, iclass 22, count 0 2006.173.11:38:13.88#ibcon#read 6, iclass 22, count 0 2006.173.11:38:13.88#ibcon#end of sib2, iclass 22, count 0 2006.173.11:38:13.88#ibcon#*after write, iclass 22, count 0 2006.173.11:38:13.88#ibcon#*before return 0, iclass 22, count 0 2006.173.11:38:13.89#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.11:38:13.89#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.11:38:13.89#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.11:38:13.89#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.11:38:13.89$vck44/valo=6,814.99 2006.173.11:38:13.89#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.11:38:13.89#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.11:38:13.89#ibcon#ireg 17 cls_cnt 0 2006.173.11:38:13.89#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.11:38:13.89#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.11:38:13.89#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.11:38:13.89#ibcon#enter wrdev, iclass 28, count 0 2006.173.11:38:13.89#ibcon#first serial, iclass 28, count 0 2006.173.11:38:13.89#ibcon#enter sib2, iclass 28, count 0 2006.173.11:38:13.89#ibcon#flushed, iclass 28, count 0 2006.173.11:38:13.89#ibcon#about to write, iclass 28, count 0 2006.173.11:38:13.89#ibcon#wrote, iclass 28, count 0 2006.173.11:38:13.89#ibcon#about to read 3, iclass 28, count 0 2006.173.11:38:13.90#ibcon#read 3, iclass 28, count 0 2006.173.11:38:13.90#ibcon#about to read 4, iclass 28, count 0 2006.173.11:38:13.90#ibcon#read 4, iclass 28, count 0 2006.173.11:38:13.90#ibcon#about to read 5, iclass 28, count 0 2006.173.11:38:13.90#ibcon#read 5, iclass 28, count 0 2006.173.11:38:13.90#ibcon#about to read 6, iclass 28, count 0 2006.173.11:38:13.91#ibcon#read 6, iclass 28, count 0 2006.173.11:38:13.91#ibcon#end of sib2, iclass 28, count 0 2006.173.11:38:13.91#ibcon#*mode == 0, iclass 28, count 0 2006.173.11:38:13.91#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.11:38:13.91#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.11:38:13.91#ibcon#*before write, iclass 28, count 0 2006.173.11:38:13.91#ibcon#enter sib2, iclass 28, count 0 2006.173.11:38:13.91#ibcon#flushed, iclass 28, count 0 2006.173.11:38:13.91#ibcon#about to write, iclass 28, count 0 2006.173.11:38:13.91#ibcon#wrote, iclass 28, count 0 2006.173.11:38:13.91#ibcon#about to read 3, iclass 28, count 0 2006.173.11:38:13.94#ibcon#read 3, iclass 28, count 0 2006.173.11:38:13.94#ibcon#about to read 4, iclass 28, count 0 2006.173.11:38:13.94#ibcon#read 4, iclass 28, count 0 2006.173.11:38:13.94#ibcon#about to read 5, iclass 28, count 0 2006.173.11:38:13.94#ibcon#read 5, iclass 28, count 0 2006.173.11:38:13.94#ibcon#about to read 6, iclass 28, count 0 2006.173.11:38:13.94#ibcon#read 6, iclass 28, count 0 2006.173.11:38:13.95#ibcon#end of sib2, iclass 28, count 0 2006.173.11:38:13.95#ibcon#*after write, iclass 28, count 0 2006.173.11:38:13.95#ibcon#*before return 0, iclass 28, count 0 2006.173.11:38:13.95#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.11:38:13.95#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.11:38:13.95#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.11:38:13.95#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.11:38:13.95$vck44/va=6,3 2006.173.11:38:13.95#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.11:38:13.95#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.11:38:13.95#ibcon#ireg 11 cls_cnt 2 2006.173.11:38:13.95#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.11:38:14.01#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.11:38:14.01#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.11:38:14.01#ibcon#enter wrdev, iclass 30, count 2 2006.173.11:38:14.01#ibcon#first serial, iclass 30, count 2 2006.173.11:38:14.01#ibcon#enter sib2, iclass 30, count 2 2006.173.11:38:14.01#ibcon#flushed, iclass 30, count 2 2006.173.11:38:14.01#ibcon#about to write, iclass 30, count 2 2006.173.11:38:14.01#ibcon#wrote, iclass 30, count 2 2006.173.11:38:14.01#ibcon#about to read 3, iclass 30, count 2 2006.173.11:38:14.02#ibcon#read 3, iclass 30, count 2 2006.173.11:38:14.02#ibcon#about to read 4, iclass 30, count 2 2006.173.11:38:14.02#ibcon#read 4, iclass 30, count 2 2006.173.11:38:14.02#ibcon#about to read 5, iclass 30, count 2 2006.173.11:38:14.02#ibcon#read 5, iclass 30, count 2 2006.173.11:38:14.02#ibcon#about to read 6, iclass 30, count 2 2006.173.11:38:14.02#ibcon#read 6, iclass 30, count 2 2006.173.11:38:14.02#ibcon#end of sib2, iclass 30, count 2 2006.173.11:38:14.02#ibcon#*mode == 0, iclass 30, count 2 2006.173.11:38:14.03#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.11:38:14.03#ibcon#[25=AT06-03\r\n] 2006.173.11:38:14.03#ibcon#*before write, iclass 30, count 2 2006.173.11:38:14.03#ibcon#enter sib2, iclass 30, count 2 2006.173.11:38:14.03#ibcon#flushed, iclass 30, count 2 2006.173.11:38:14.03#ibcon#about to write, iclass 30, count 2 2006.173.11:38:14.03#ibcon#wrote, iclass 30, count 2 2006.173.11:38:14.03#ibcon#about to read 3, iclass 30, count 2 2006.173.11:38:14.05#ibcon#read 3, iclass 30, count 2 2006.173.11:38:14.05#ibcon#about to read 4, iclass 30, count 2 2006.173.11:38:14.05#ibcon#read 4, iclass 30, count 2 2006.173.11:38:14.05#ibcon#about to read 5, iclass 30, count 2 2006.173.11:38:14.05#ibcon#read 5, iclass 30, count 2 2006.173.11:38:14.05#ibcon#about to read 6, iclass 30, count 2 2006.173.11:38:14.05#ibcon#read 6, iclass 30, count 2 2006.173.11:38:14.05#ibcon#end of sib2, iclass 30, count 2 2006.173.11:38:14.05#ibcon#*after write, iclass 30, count 2 2006.173.11:38:14.05#ibcon#*before return 0, iclass 30, count 2 2006.173.11:38:14.06#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.11:38:14.06#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.11:38:14.06#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.11:38:14.06#ibcon#ireg 7 cls_cnt 0 2006.173.11:38:14.06#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.11:38:14.17#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.11:38:14.17#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.11:38:14.17#ibcon#enter wrdev, iclass 30, count 0 2006.173.11:38:14.17#ibcon#first serial, iclass 30, count 0 2006.173.11:38:14.17#ibcon#enter sib2, iclass 30, count 0 2006.173.11:38:14.17#ibcon#flushed, iclass 30, count 0 2006.173.11:38:14.17#ibcon#about to write, iclass 30, count 0 2006.173.11:38:14.18#ibcon#wrote, iclass 30, count 0 2006.173.11:38:14.18#ibcon#about to read 3, iclass 30, count 0 2006.173.11:38:14.19#ibcon#read 3, iclass 30, count 0 2006.173.11:38:14.19#ibcon#about to read 4, iclass 30, count 0 2006.173.11:38:14.19#ibcon#read 4, iclass 30, count 0 2006.173.11:38:14.19#ibcon#about to read 5, iclass 30, count 0 2006.173.11:38:14.19#ibcon#read 5, iclass 30, count 0 2006.173.11:38:14.19#ibcon#about to read 6, iclass 30, count 0 2006.173.11:38:14.19#ibcon#read 6, iclass 30, count 0 2006.173.11:38:14.19#ibcon#end of sib2, iclass 30, count 0 2006.173.11:38:14.19#ibcon#*mode == 0, iclass 30, count 0 2006.173.11:38:14.20#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.11:38:14.20#ibcon#[25=USB\r\n] 2006.173.11:38:14.20#ibcon#*before write, iclass 30, count 0 2006.173.11:38:14.20#ibcon#enter sib2, iclass 30, count 0 2006.173.11:38:14.20#ibcon#flushed, iclass 30, count 0 2006.173.11:38:14.20#ibcon#about to write, iclass 30, count 0 2006.173.11:38:14.20#ibcon#wrote, iclass 30, count 0 2006.173.11:38:14.20#ibcon#about to read 3, iclass 30, count 0 2006.173.11:38:14.22#ibcon#read 3, iclass 30, count 0 2006.173.11:38:14.22#ibcon#about to read 4, iclass 30, count 0 2006.173.11:38:14.22#ibcon#read 4, iclass 30, count 0 2006.173.11:38:14.22#ibcon#about to read 5, iclass 30, count 0 2006.173.11:38:14.22#ibcon#read 5, iclass 30, count 0 2006.173.11:38:14.22#ibcon#about to read 6, iclass 30, count 0 2006.173.11:38:14.22#ibcon#read 6, iclass 30, count 0 2006.173.11:38:14.22#ibcon#end of sib2, iclass 30, count 0 2006.173.11:38:14.22#ibcon#*after write, iclass 30, count 0 2006.173.11:38:14.22#ibcon#*before return 0, iclass 30, count 0 2006.173.11:38:14.23#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.11:38:14.23#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.11:38:14.23#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.11:38:14.23#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.11:38:14.23$vck44/valo=7,864.99 2006.173.11:38:14.23#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.11:38:14.23#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.11:38:14.23#ibcon#ireg 17 cls_cnt 0 2006.173.11:38:14.23#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.11:38:14.23#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.11:38:14.23#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.11:38:14.23#ibcon#enter wrdev, iclass 32, count 0 2006.173.11:38:14.23#ibcon#first serial, iclass 32, count 0 2006.173.11:38:14.23#ibcon#enter sib2, iclass 32, count 0 2006.173.11:38:14.23#ibcon#flushed, iclass 32, count 0 2006.173.11:38:14.23#ibcon#about to write, iclass 32, count 0 2006.173.11:38:14.23#ibcon#wrote, iclass 32, count 0 2006.173.11:38:14.23#ibcon#about to read 3, iclass 32, count 0 2006.173.11:38:14.24#ibcon#read 3, iclass 32, count 0 2006.173.11:38:14.24#ibcon#about to read 4, iclass 32, count 0 2006.173.11:38:14.24#ibcon#read 4, iclass 32, count 0 2006.173.11:38:14.24#ibcon#about to read 5, iclass 32, count 0 2006.173.11:38:14.24#ibcon#read 5, iclass 32, count 0 2006.173.11:38:14.24#ibcon#about to read 6, iclass 32, count 0 2006.173.11:38:14.25#ibcon#read 6, iclass 32, count 0 2006.173.11:38:14.25#ibcon#end of sib2, iclass 32, count 0 2006.173.11:38:14.25#ibcon#*mode == 0, iclass 32, count 0 2006.173.11:38:14.25#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.11:38:14.25#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.11:38:14.25#ibcon#*before write, iclass 32, count 0 2006.173.11:38:14.25#ibcon#enter sib2, iclass 32, count 0 2006.173.11:38:14.25#ibcon#flushed, iclass 32, count 0 2006.173.11:38:14.25#ibcon#about to write, iclass 32, count 0 2006.173.11:38:14.25#ibcon#wrote, iclass 32, count 0 2006.173.11:38:14.25#ibcon#about to read 3, iclass 32, count 0 2006.173.11:38:14.28#ibcon#read 3, iclass 32, count 0 2006.173.11:38:14.28#ibcon#about to read 4, iclass 32, count 0 2006.173.11:38:14.28#ibcon#read 4, iclass 32, count 0 2006.173.11:38:14.28#ibcon#about to read 5, iclass 32, count 0 2006.173.11:38:14.28#ibcon#read 5, iclass 32, count 0 2006.173.11:38:14.28#ibcon#about to read 6, iclass 32, count 0 2006.173.11:38:14.28#ibcon#read 6, iclass 32, count 0 2006.173.11:38:14.28#ibcon#end of sib2, iclass 32, count 0 2006.173.11:38:14.28#ibcon#*after write, iclass 32, count 0 2006.173.11:38:14.29#ibcon#*before return 0, iclass 32, count 0 2006.173.11:38:14.29#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.11:38:14.29#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.11:38:14.29#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.11:38:14.29#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.11:38:14.29$vck44/va=7,4 2006.173.11:38:14.29#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.11:38:14.29#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.11:38:14.29#ibcon#ireg 11 cls_cnt 2 2006.173.11:38:14.29#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.11:38:14.34#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.11:38:14.34#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.11:38:14.34#ibcon#enter wrdev, iclass 34, count 2 2006.173.11:38:14.34#ibcon#first serial, iclass 34, count 2 2006.173.11:38:14.34#ibcon#enter sib2, iclass 34, count 2 2006.173.11:38:14.34#ibcon#flushed, iclass 34, count 2 2006.173.11:38:14.34#ibcon#about to write, iclass 34, count 2 2006.173.11:38:14.35#ibcon#wrote, iclass 34, count 2 2006.173.11:38:14.35#ibcon#about to read 3, iclass 34, count 2 2006.173.11:38:14.36#ibcon#read 3, iclass 34, count 2 2006.173.11:38:14.36#ibcon#about to read 4, iclass 34, count 2 2006.173.11:38:14.36#ibcon#read 4, iclass 34, count 2 2006.173.11:38:14.36#ibcon#about to read 5, iclass 34, count 2 2006.173.11:38:14.36#ibcon#read 5, iclass 34, count 2 2006.173.11:38:14.36#ibcon#about to read 6, iclass 34, count 2 2006.173.11:38:14.36#ibcon#read 6, iclass 34, count 2 2006.173.11:38:14.37#ibcon#end of sib2, iclass 34, count 2 2006.173.11:38:14.37#ibcon#*mode == 0, iclass 34, count 2 2006.173.11:38:14.37#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.11:38:14.37#ibcon#[25=AT07-04\r\n] 2006.173.11:38:14.37#ibcon#*before write, iclass 34, count 2 2006.173.11:38:14.37#ibcon#enter sib2, iclass 34, count 2 2006.173.11:38:14.37#ibcon#flushed, iclass 34, count 2 2006.173.11:38:14.37#ibcon#about to write, iclass 34, count 2 2006.173.11:38:14.37#ibcon#wrote, iclass 34, count 2 2006.173.11:38:14.37#ibcon#about to read 3, iclass 34, count 2 2006.173.11:38:14.39#ibcon#read 3, iclass 34, count 2 2006.173.11:38:14.39#ibcon#about to read 4, iclass 34, count 2 2006.173.11:38:14.39#ibcon#read 4, iclass 34, count 2 2006.173.11:38:14.39#ibcon#about to read 5, iclass 34, count 2 2006.173.11:38:14.39#ibcon#read 5, iclass 34, count 2 2006.173.11:38:14.39#ibcon#about to read 6, iclass 34, count 2 2006.173.11:38:14.39#ibcon#read 6, iclass 34, count 2 2006.173.11:38:14.40#ibcon#end of sib2, iclass 34, count 2 2006.173.11:38:14.40#ibcon#*after write, iclass 34, count 2 2006.173.11:38:14.40#ibcon#*before return 0, iclass 34, count 2 2006.173.11:38:14.40#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.11:38:14.40#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.11:38:14.40#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.11:38:14.40#ibcon#ireg 7 cls_cnt 0 2006.173.11:38:14.40#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.11:38:14.51#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.11:38:14.51#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.11:38:14.52#ibcon#enter wrdev, iclass 34, count 0 2006.173.11:38:14.52#ibcon#first serial, iclass 34, count 0 2006.173.11:38:14.52#ibcon#enter sib2, iclass 34, count 0 2006.173.11:38:14.52#ibcon#flushed, iclass 34, count 0 2006.173.11:38:14.52#ibcon#about to write, iclass 34, count 0 2006.173.11:38:14.52#ibcon#wrote, iclass 34, count 0 2006.173.11:38:14.52#ibcon#about to read 3, iclass 34, count 0 2006.173.11:38:14.53#ibcon#read 3, iclass 34, count 0 2006.173.11:38:14.53#ibcon#about to read 4, iclass 34, count 0 2006.173.11:38:14.53#ibcon#read 4, iclass 34, count 0 2006.173.11:38:14.53#ibcon#about to read 5, iclass 34, count 0 2006.173.11:38:14.54#ibcon#read 5, iclass 34, count 0 2006.173.11:38:14.54#ibcon#about to read 6, iclass 34, count 0 2006.173.11:38:14.54#ibcon#read 6, iclass 34, count 0 2006.173.11:38:14.54#ibcon#end of sib2, iclass 34, count 0 2006.173.11:38:14.54#ibcon#*mode == 0, iclass 34, count 0 2006.173.11:38:14.54#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.11:38:14.54#ibcon#[25=USB\r\n] 2006.173.11:38:14.54#ibcon#*before write, iclass 34, count 0 2006.173.11:38:14.54#ibcon#enter sib2, iclass 34, count 0 2006.173.11:38:14.54#ibcon#flushed, iclass 34, count 0 2006.173.11:38:14.54#ibcon#about to write, iclass 34, count 0 2006.173.11:38:14.54#ibcon#wrote, iclass 34, count 0 2006.173.11:38:14.54#ibcon#about to read 3, iclass 34, count 0 2006.173.11:38:14.56#ibcon#read 3, iclass 34, count 0 2006.173.11:38:14.56#ibcon#about to read 4, iclass 34, count 0 2006.173.11:38:14.56#ibcon#read 4, iclass 34, count 0 2006.173.11:38:14.56#ibcon#about to read 5, iclass 34, count 0 2006.173.11:38:14.56#ibcon#read 5, iclass 34, count 0 2006.173.11:38:14.56#ibcon#about to read 6, iclass 34, count 0 2006.173.11:38:14.57#ibcon#read 6, iclass 34, count 0 2006.173.11:38:14.57#ibcon#end of sib2, iclass 34, count 0 2006.173.11:38:14.57#ibcon#*after write, iclass 34, count 0 2006.173.11:38:14.57#ibcon#*before return 0, iclass 34, count 0 2006.173.11:38:14.57#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.11:38:14.57#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.11:38:14.57#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.11:38:14.57#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.11:38:14.57$vck44/valo=8,884.99 2006.173.11:38:14.57#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.11:38:14.57#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.11:38:14.57#ibcon#ireg 17 cls_cnt 0 2006.173.11:38:14.57#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.11:38:14.57#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.11:38:14.57#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.11:38:14.57#ibcon#enter wrdev, iclass 36, count 0 2006.173.11:38:14.57#ibcon#first serial, iclass 36, count 0 2006.173.11:38:14.57#ibcon#enter sib2, iclass 36, count 0 2006.173.11:38:14.57#ibcon#flushed, iclass 36, count 0 2006.173.11:38:14.57#ibcon#about to write, iclass 36, count 0 2006.173.11:38:14.57#ibcon#wrote, iclass 36, count 0 2006.173.11:38:14.57#ibcon#about to read 3, iclass 36, count 0 2006.173.11:38:14.58#ibcon#read 3, iclass 36, count 0 2006.173.11:38:14.58#ibcon#about to read 4, iclass 36, count 0 2006.173.11:38:14.58#ibcon#read 4, iclass 36, count 0 2006.173.11:38:14.58#ibcon#about to read 5, iclass 36, count 0 2006.173.11:38:14.58#ibcon#read 5, iclass 36, count 0 2006.173.11:38:14.59#ibcon#about to read 6, iclass 36, count 0 2006.173.11:38:14.59#ibcon#read 6, iclass 36, count 0 2006.173.11:38:14.59#ibcon#end of sib2, iclass 36, count 0 2006.173.11:38:14.59#ibcon#*mode == 0, iclass 36, count 0 2006.173.11:38:14.59#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.11:38:14.59#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.11:38:14.59#ibcon#*before write, iclass 36, count 0 2006.173.11:38:14.59#ibcon#enter sib2, iclass 36, count 0 2006.173.11:38:14.59#ibcon#flushed, iclass 36, count 0 2006.173.11:38:14.59#ibcon#about to write, iclass 36, count 0 2006.173.11:38:14.59#ibcon#wrote, iclass 36, count 0 2006.173.11:38:14.59#ibcon#about to read 3, iclass 36, count 0 2006.173.11:38:14.62#ibcon#read 3, iclass 36, count 0 2006.173.11:38:14.62#ibcon#about to read 4, iclass 36, count 0 2006.173.11:38:14.62#ibcon#read 4, iclass 36, count 0 2006.173.11:38:14.62#ibcon#about to read 5, iclass 36, count 0 2006.173.11:38:14.62#ibcon#read 5, iclass 36, count 0 2006.173.11:38:14.62#ibcon#about to read 6, iclass 36, count 0 2006.173.11:38:14.62#ibcon#read 6, iclass 36, count 0 2006.173.11:38:14.63#ibcon#end of sib2, iclass 36, count 0 2006.173.11:38:14.63#ibcon#*after write, iclass 36, count 0 2006.173.11:38:14.63#ibcon#*before return 0, iclass 36, count 0 2006.173.11:38:14.63#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.11:38:14.63#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.11:38:14.63#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.11:38:14.63#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.11:38:14.63$vck44/va=8,4 2006.173.11:38:14.63#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.11:38:14.63#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.11:38:14.63#ibcon#ireg 11 cls_cnt 2 2006.173.11:38:14.63#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.11:38:14.68#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.11:38:14.68#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.11:38:14.68#ibcon#enter wrdev, iclass 38, count 2 2006.173.11:38:14.68#ibcon#first serial, iclass 38, count 2 2006.173.11:38:14.68#ibcon#enter sib2, iclass 38, count 2 2006.173.11:38:14.68#ibcon#flushed, iclass 38, count 2 2006.173.11:38:14.68#ibcon#about to write, iclass 38, count 2 2006.173.11:38:14.69#ibcon#wrote, iclass 38, count 2 2006.173.11:38:14.69#ibcon#about to read 3, iclass 38, count 2 2006.173.11:38:14.70#ibcon#read 3, iclass 38, count 2 2006.173.11:38:14.70#ibcon#about to read 4, iclass 38, count 2 2006.173.11:38:14.70#ibcon#read 4, iclass 38, count 2 2006.173.11:38:14.70#ibcon#about to read 5, iclass 38, count 2 2006.173.11:38:14.71#ibcon#read 5, iclass 38, count 2 2006.173.11:38:14.71#ibcon#about to read 6, iclass 38, count 2 2006.173.11:38:14.71#ibcon#read 6, iclass 38, count 2 2006.173.11:38:14.71#ibcon#end of sib2, iclass 38, count 2 2006.173.11:38:14.71#ibcon#*mode == 0, iclass 38, count 2 2006.173.11:38:14.71#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.11:38:14.71#ibcon#[25=AT08-04\r\n] 2006.173.11:38:14.71#ibcon#*before write, iclass 38, count 2 2006.173.11:38:14.71#ibcon#enter sib2, iclass 38, count 2 2006.173.11:38:14.71#ibcon#flushed, iclass 38, count 2 2006.173.11:38:14.71#ibcon#about to write, iclass 38, count 2 2006.173.11:38:14.71#ibcon#wrote, iclass 38, count 2 2006.173.11:38:14.71#ibcon#about to read 3, iclass 38, count 2 2006.173.11:38:14.73#ibcon#read 3, iclass 38, count 2 2006.173.11:38:14.73#ibcon#about to read 4, iclass 38, count 2 2006.173.11:38:14.73#ibcon#read 4, iclass 38, count 2 2006.173.11:38:14.73#ibcon#about to read 5, iclass 38, count 2 2006.173.11:38:14.73#ibcon#read 5, iclass 38, count 2 2006.173.11:38:14.73#ibcon#about to read 6, iclass 38, count 2 2006.173.11:38:14.73#ibcon#read 6, iclass 38, count 2 2006.173.11:38:14.74#ibcon#end of sib2, iclass 38, count 2 2006.173.11:38:14.74#ibcon#*after write, iclass 38, count 2 2006.173.11:38:14.74#ibcon#*before return 0, iclass 38, count 2 2006.173.11:38:14.74#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.11:38:14.74#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.11:38:14.74#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.11:38:14.74#ibcon#ireg 7 cls_cnt 0 2006.173.11:38:14.74#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.11:38:14.85#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.11:38:14.85#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.11:38:14.85#ibcon#enter wrdev, iclass 38, count 0 2006.173.11:38:14.85#ibcon#first serial, iclass 38, count 0 2006.173.11:38:14.85#ibcon#enter sib2, iclass 38, count 0 2006.173.11:38:14.85#ibcon#flushed, iclass 38, count 0 2006.173.11:38:14.85#ibcon#about to write, iclass 38, count 0 2006.173.11:38:14.86#ibcon#wrote, iclass 38, count 0 2006.173.11:38:14.86#ibcon#about to read 3, iclass 38, count 0 2006.173.11:38:14.87#ibcon#read 3, iclass 38, count 0 2006.173.11:38:14.87#ibcon#about to read 4, iclass 38, count 0 2006.173.11:38:14.87#ibcon#read 4, iclass 38, count 0 2006.173.11:38:14.87#ibcon#about to read 5, iclass 38, count 0 2006.173.11:38:14.87#ibcon#read 5, iclass 38, count 0 2006.173.11:38:14.87#ibcon#about to read 6, iclass 38, count 0 2006.173.11:38:14.87#ibcon#read 6, iclass 38, count 0 2006.173.11:38:14.87#ibcon#end of sib2, iclass 38, count 0 2006.173.11:38:14.87#ibcon#*mode == 0, iclass 38, count 0 2006.173.11:38:14.88#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.11:38:14.88#ibcon#[25=USB\r\n] 2006.173.11:38:14.88#ibcon#*before write, iclass 38, count 0 2006.173.11:38:14.88#ibcon#enter sib2, iclass 38, count 0 2006.173.11:38:14.88#ibcon#flushed, iclass 38, count 0 2006.173.11:38:14.88#ibcon#about to write, iclass 38, count 0 2006.173.11:38:14.88#ibcon#wrote, iclass 38, count 0 2006.173.11:38:14.88#ibcon#about to read 3, iclass 38, count 0 2006.173.11:38:14.90#ibcon#read 3, iclass 38, count 0 2006.173.11:38:14.90#ibcon#about to read 4, iclass 38, count 0 2006.173.11:38:14.90#ibcon#read 4, iclass 38, count 0 2006.173.11:38:14.90#ibcon#about to read 5, iclass 38, count 0 2006.173.11:38:14.90#ibcon#read 5, iclass 38, count 0 2006.173.11:38:14.90#ibcon#about to read 6, iclass 38, count 0 2006.173.11:38:14.91#ibcon#read 6, iclass 38, count 0 2006.173.11:38:14.91#ibcon#end of sib2, iclass 38, count 0 2006.173.11:38:14.91#ibcon#*after write, iclass 38, count 0 2006.173.11:38:14.91#ibcon#*before return 0, iclass 38, count 0 2006.173.11:38:14.91#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.11:38:14.91#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.11:38:14.91#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.11:38:14.91#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.11:38:14.91$vck44/vblo=1,629.99 2006.173.11:38:14.91#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.11:38:14.91#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.11:38:14.91#ibcon#ireg 17 cls_cnt 0 2006.173.11:38:14.91#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.11:38:14.91#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.11:38:14.91#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.11:38:14.91#ibcon#enter wrdev, iclass 40, count 0 2006.173.11:38:14.91#ibcon#first serial, iclass 40, count 0 2006.173.11:38:14.91#ibcon#enter sib2, iclass 40, count 0 2006.173.11:38:14.91#ibcon#flushed, iclass 40, count 0 2006.173.11:38:14.91#ibcon#about to write, iclass 40, count 0 2006.173.11:38:14.91#ibcon#wrote, iclass 40, count 0 2006.173.11:38:14.91#ibcon#about to read 3, iclass 40, count 0 2006.173.11:38:14.92#ibcon#read 3, iclass 40, count 0 2006.173.11:38:14.92#ibcon#about to read 4, iclass 40, count 0 2006.173.11:38:14.92#ibcon#read 4, iclass 40, count 0 2006.173.11:38:14.92#ibcon#about to read 5, iclass 40, count 0 2006.173.11:38:14.92#ibcon#read 5, iclass 40, count 0 2006.173.11:38:14.92#ibcon#about to read 6, iclass 40, count 0 2006.173.11:38:14.92#ibcon#read 6, iclass 40, count 0 2006.173.11:38:14.92#ibcon#end of sib2, iclass 40, count 0 2006.173.11:38:14.92#ibcon#*mode == 0, iclass 40, count 0 2006.173.11:38:14.93#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.11:38:14.93#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.11:38:14.93#ibcon#*before write, iclass 40, count 0 2006.173.11:38:14.93#ibcon#enter sib2, iclass 40, count 0 2006.173.11:38:14.93#ibcon#flushed, iclass 40, count 0 2006.173.11:38:14.93#ibcon#about to write, iclass 40, count 0 2006.173.11:38:14.93#ibcon#wrote, iclass 40, count 0 2006.173.11:38:14.93#ibcon#about to read 3, iclass 40, count 0 2006.173.11:38:14.96#ibcon#read 3, iclass 40, count 0 2006.173.11:38:14.96#ibcon#about to read 4, iclass 40, count 0 2006.173.11:38:14.96#ibcon#read 4, iclass 40, count 0 2006.173.11:38:14.96#ibcon#about to read 5, iclass 40, count 0 2006.173.11:38:14.96#ibcon#read 5, iclass 40, count 0 2006.173.11:38:14.96#ibcon#about to read 6, iclass 40, count 0 2006.173.11:38:14.97#ibcon#read 6, iclass 40, count 0 2006.173.11:38:14.97#ibcon#end of sib2, iclass 40, count 0 2006.173.11:38:14.97#ibcon#*after write, iclass 40, count 0 2006.173.11:38:14.97#ibcon#*before return 0, iclass 40, count 0 2006.173.11:38:14.97#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.11:38:14.97#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.11:38:14.97#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.11:38:14.97#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.11:38:14.97$vck44/vb=1,4 2006.173.11:38:14.97#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.11:38:14.97#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.11:38:14.97#ibcon#ireg 11 cls_cnt 2 2006.173.11:38:14.97#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.11:38:14.97#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.11:38:14.97#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.11:38:14.97#ibcon#enter wrdev, iclass 4, count 2 2006.173.11:38:14.97#ibcon#first serial, iclass 4, count 2 2006.173.11:38:14.97#ibcon#enter sib2, iclass 4, count 2 2006.173.11:38:14.97#ibcon#flushed, iclass 4, count 2 2006.173.11:38:14.97#ibcon#about to write, iclass 4, count 2 2006.173.11:38:14.97#ibcon#wrote, iclass 4, count 2 2006.173.11:38:14.97#ibcon#about to read 3, iclass 4, count 2 2006.173.11:38:14.98#ibcon#read 3, iclass 4, count 2 2006.173.11:38:14.98#ibcon#about to read 4, iclass 4, count 2 2006.173.11:38:14.98#ibcon#read 4, iclass 4, count 2 2006.173.11:38:14.98#ibcon#about to read 5, iclass 4, count 2 2006.173.11:38:14.98#ibcon#read 5, iclass 4, count 2 2006.173.11:38:14.98#ibcon#about to read 6, iclass 4, count 2 2006.173.11:38:14.98#ibcon#read 6, iclass 4, count 2 2006.173.11:38:14.98#ibcon#end of sib2, iclass 4, count 2 2006.173.11:38:14.98#ibcon#*mode == 0, iclass 4, count 2 2006.173.11:38:14.99#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.11:38:14.99#ibcon#[27=AT01-04\r\n] 2006.173.11:38:14.99#ibcon#*before write, iclass 4, count 2 2006.173.11:38:14.99#ibcon#enter sib2, iclass 4, count 2 2006.173.11:38:14.99#ibcon#flushed, iclass 4, count 2 2006.173.11:38:14.99#ibcon#about to write, iclass 4, count 2 2006.173.11:38:14.99#ibcon#wrote, iclass 4, count 2 2006.173.11:38:14.99#ibcon#about to read 3, iclass 4, count 2 2006.173.11:38:15.01#ibcon#read 3, iclass 4, count 2 2006.173.11:38:15.01#ibcon#about to read 4, iclass 4, count 2 2006.173.11:38:15.01#ibcon#read 4, iclass 4, count 2 2006.173.11:38:15.01#ibcon#about to read 5, iclass 4, count 2 2006.173.11:38:15.01#ibcon#read 5, iclass 4, count 2 2006.173.11:38:15.01#ibcon#about to read 6, iclass 4, count 2 2006.173.11:38:15.01#ibcon#read 6, iclass 4, count 2 2006.173.11:38:15.01#ibcon#end of sib2, iclass 4, count 2 2006.173.11:38:15.01#ibcon#*after write, iclass 4, count 2 2006.173.11:38:15.02#ibcon#*before return 0, iclass 4, count 2 2006.173.11:38:15.02#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.11:38:15.02#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.11:38:15.02#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.11:38:15.02#ibcon#ireg 7 cls_cnt 0 2006.173.11:38:15.02#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.11:38:15.13#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.11:38:15.13#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.11:38:15.13#ibcon#enter wrdev, iclass 4, count 0 2006.173.11:38:15.13#ibcon#first serial, iclass 4, count 0 2006.173.11:38:15.13#ibcon#enter sib2, iclass 4, count 0 2006.173.11:38:15.13#ibcon#flushed, iclass 4, count 0 2006.173.11:38:15.13#ibcon#about to write, iclass 4, count 0 2006.173.11:38:15.14#ibcon#wrote, iclass 4, count 0 2006.173.11:38:15.14#ibcon#about to read 3, iclass 4, count 0 2006.173.11:38:15.15#ibcon#read 3, iclass 4, count 0 2006.173.11:38:15.15#ibcon#about to read 4, iclass 4, count 0 2006.173.11:38:15.15#ibcon#read 4, iclass 4, count 0 2006.173.11:38:15.15#ibcon#about to read 5, iclass 4, count 0 2006.173.11:38:15.15#ibcon#read 5, iclass 4, count 0 2006.173.11:38:15.15#ibcon#about to read 6, iclass 4, count 0 2006.173.11:38:15.15#ibcon#read 6, iclass 4, count 0 2006.173.11:38:15.15#ibcon#end of sib2, iclass 4, count 0 2006.173.11:38:15.15#ibcon#*mode == 0, iclass 4, count 0 2006.173.11:38:15.15#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.11:38:15.15#ibcon#[27=USB\r\n] 2006.173.11:38:15.15#ibcon#*before write, iclass 4, count 0 2006.173.11:38:15.15#ibcon#enter sib2, iclass 4, count 0 2006.173.11:38:15.15#ibcon#flushed, iclass 4, count 0 2006.173.11:38:15.15#ibcon#about to write, iclass 4, count 0 2006.173.11:38:15.15#ibcon#wrote, iclass 4, count 0 2006.173.11:38:15.15#ibcon#about to read 3, iclass 4, count 0 2006.173.11:38:15.17#ibcon#read 3, iclass 4, count 0 2006.173.11:38:15.17#ibcon#about to read 4, iclass 4, count 0 2006.173.11:38:15.17#ibcon#read 4, iclass 4, count 0 2006.173.11:38:15.17#ibcon#about to read 5, iclass 4, count 0 2006.173.11:38:15.17#ibcon#read 5, iclass 4, count 0 2006.173.11:38:15.17#ibcon#about to read 6, iclass 4, count 0 2006.173.11:38:15.17#ibcon#read 6, iclass 4, count 0 2006.173.11:38:15.17#ibcon#end of sib2, iclass 4, count 0 2006.173.11:38:15.17#ibcon#*after write, iclass 4, count 0 2006.173.11:38:15.18#ibcon#*before return 0, iclass 4, count 0 2006.173.11:38:15.18#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.11:38:15.18#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.11:38:15.18#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.11:38:15.18#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.11:38:15.18$vck44/vblo=2,634.99 2006.173.11:38:15.18#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.11:38:15.18#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.11:38:15.18#ibcon#ireg 17 cls_cnt 0 2006.173.11:38:15.18#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.11:38:15.18#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.11:38:15.18#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.11:38:15.18#ibcon#enter wrdev, iclass 6, count 0 2006.173.11:38:15.18#ibcon#first serial, iclass 6, count 0 2006.173.11:38:15.18#ibcon#enter sib2, iclass 6, count 0 2006.173.11:38:15.18#ibcon#flushed, iclass 6, count 0 2006.173.11:38:15.18#ibcon#about to write, iclass 6, count 0 2006.173.11:38:15.18#ibcon#wrote, iclass 6, count 0 2006.173.11:38:15.18#ibcon#about to read 3, iclass 6, count 0 2006.173.11:38:15.19#ibcon#read 3, iclass 6, count 0 2006.173.11:38:15.19#ibcon#about to read 4, iclass 6, count 0 2006.173.11:38:15.19#ibcon#read 4, iclass 6, count 0 2006.173.11:38:15.19#ibcon#about to read 5, iclass 6, count 0 2006.173.11:38:15.19#ibcon#read 5, iclass 6, count 0 2006.173.11:38:15.19#ibcon#about to read 6, iclass 6, count 0 2006.173.11:38:15.19#ibcon#read 6, iclass 6, count 0 2006.173.11:38:15.19#ibcon#end of sib2, iclass 6, count 0 2006.173.11:38:15.19#ibcon#*mode == 0, iclass 6, count 0 2006.173.11:38:15.19#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.11:38:15.20#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.11:38:15.20#ibcon#*before write, iclass 6, count 0 2006.173.11:38:15.20#ibcon#enter sib2, iclass 6, count 0 2006.173.11:38:15.20#ibcon#flushed, iclass 6, count 0 2006.173.11:38:15.20#ibcon#about to write, iclass 6, count 0 2006.173.11:38:15.20#ibcon#wrote, iclass 6, count 0 2006.173.11:38:15.20#ibcon#about to read 3, iclass 6, count 0 2006.173.11:38:15.23#ibcon#read 3, iclass 6, count 0 2006.173.11:38:15.23#ibcon#about to read 4, iclass 6, count 0 2006.173.11:38:15.23#ibcon#read 4, iclass 6, count 0 2006.173.11:38:15.23#ibcon#about to read 5, iclass 6, count 0 2006.173.11:38:15.23#ibcon#read 5, iclass 6, count 0 2006.173.11:38:15.23#ibcon#about to read 6, iclass 6, count 0 2006.173.11:38:15.23#ibcon#read 6, iclass 6, count 0 2006.173.11:38:15.23#ibcon#end of sib2, iclass 6, count 0 2006.173.11:38:15.24#ibcon#*after write, iclass 6, count 0 2006.173.11:38:15.24#ibcon#*before return 0, iclass 6, count 0 2006.173.11:38:15.24#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.11:38:15.24#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.11:38:15.24#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.11:38:15.24#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.11:38:15.24$vck44/vb=2,4 2006.173.11:38:15.24#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.11:38:15.24#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.11:38:15.24#ibcon#ireg 11 cls_cnt 2 2006.173.11:38:15.24#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.11:38:15.29#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.11:38:15.29#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.11:38:15.29#ibcon#enter wrdev, iclass 10, count 2 2006.173.11:38:15.29#ibcon#first serial, iclass 10, count 2 2006.173.11:38:15.29#ibcon#enter sib2, iclass 10, count 2 2006.173.11:38:15.29#ibcon#flushed, iclass 10, count 2 2006.173.11:38:15.29#ibcon#about to write, iclass 10, count 2 2006.173.11:38:15.30#ibcon#wrote, iclass 10, count 2 2006.173.11:38:15.30#ibcon#about to read 3, iclass 10, count 2 2006.173.11:38:15.31#ibcon#read 3, iclass 10, count 2 2006.173.11:38:15.31#ibcon#about to read 4, iclass 10, count 2 2006.173.11:38:15.31#ibcon#read 4, iclass 10, count 2 2006.173.11:38:15.31#ibcon#about to read 5, iclass 10, count 2 2006.173.11:38:15.31#ibcon#read 5, iclass 10, count 2 2006.173.11:38:15.31#ibcon#about to read 6, iclass 10, count 2 2006.173.11:38:15.31#ibcon#read 6, iclass 10, count 2 2006.173.11:38:15.31#ibcon#end of sib2, iclass 10, count 2 2006.173.11:38:15.31#ibcon#*mode == 0, iclass 10, count 2 2006.173.11:38:15.31#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.11:38:15.32#ibcon#[27=AT02-04\r\n] 2006.173.11:38:15.32#ibcon#*before write, iclass 10, count 2 2006.173.11:38:15.32#ibcon#enter sib2, iclass 10, count 2 2006.173.11:38:15.32#ibcon#flushed, iclass 10, count 2 2006.173.11:38:15.32#ibcon#about to write, iclass 10, count 2 2006.173.11:38:15.32#ibcon#wrote, iclass 10, count 2 2006.173.11:38:15.32#ibcon#about to read 3, iclass 10, count 2 2006.173.11:38:15.34#ibcon#read 3, iclass 10, count 2 2006.173.11:38:15.34#ibcon#about to read 4, iclass 10, count 2 2006.173.11:38:15.34#ibcon#read 4, iclass 10, count 2 2006.173.11:38:15.34#ibcon#about to read 5, iclass 10, count 2 2006.173.11:38:15.34#ibcon#read 5, iclass 10, count 2 2006.173.11:38:15.34#ibcon#about to read 6, iclass 10, count 2 2006.173.11:38:15.34#ibcon#read 6, iclass 10, count 2 2006.173.11:38:15.35#ibcon#end of sib2, iclass 10, count 2 2006.173.11:38:15.35#ibcon#*after write, iclass 10, count 2 2006.173.11:38:15.35#ibcon#*before return 0, iclass 10, count 2 2006.173.11:38:15.35#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.11:38:15.35#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.11:38:15.35#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.11:38:15.35#ibcon#ireg 7 cls_cnt 0 2006.173.11:38:15.35#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.11:38:15.46#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.11:38:15.46#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.11:38:15.46#ibcon#enter wrdev, iclass 10, count 0 2006.173.11:38:15.46#ibcon#first serial, iclass 10, count 0 2006.173.11:38:15.46#ibcon#enter sib2, iclass 10, count 0 2006.173.11:38:15.46#ibcon#flushed, iclass 10, count 0 2006.173.11:38:15.46#ibcon#about to write, iclass 10, count 0 2006.173.11:38:15.47#ibcon#wrote, iclass 10, count 0 2006.173.11:38:15.47#ibcon#about to read 3, iclass 10, count 0 2006.173.11:38:15.48#ibcon#read 3, iclass 10, count 0 2006.173.11:38:15.48#ibcon#about to read 4, iclass 10, count 0 2006.173.11:38:15.48#ibcon#read 4, iclass 10, count 0 2006.173.11:38:15.48#ibcon#about to read 5, iclass 10, count 0 2006.173.11:38:15.48#ibcon#read 5, iclass 10, count 0 2006.173.11:38:15.48#ibcon#about to read 6, iclass 10, count 0 2006.173.11:38:15.48#ibcon#read 6, iclass 10, count 0 2006.173.11:38:15.49#ibcon#end of sib2, iclass 10, count 0 2006.173.11:38:15.49#ibcon#*mode == 0, iclass 10, count 0 2006.173.11:38:15.49#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.11:38:15.49#ibcon#[27=USB\r\n] 2006.173.11:38:15.49#ibcon#*before write, iclass 10, count 0 2006.173.11:38:15.49#ibcon#enter sib2, iclass 10, count 0 2006.173.11:38:15.49#ibcon#flushed, iclass 10, count 0 2006.173.11:38:15.49#ibcon#about to write, iclass 10, count 0 2006.173.11:38:15.49#ibcon#wrote, iclass 10, count 0 2006.173.11:38:15.49#ibcon#about to read 3, iclass 10, count 0 2006.173.11:38:15.51#ibcon#read 3, iclass 10, count 0 2006.173.11:38:15.51#ibcon#about to read 4, iclass 10, count 0 2006.173.11:38:15.51#ibcon#read 4, iclass 10, count 0 2006.173.11:38:15.51#ibcon#about to read 5, iclass 10, count 0 2006.173.11:38:15.51#ibcon#read 5, iclass 10, count 0 2006.173.11:38:15.51#ibcon#about to read 6, iclass 10, count 0 2006.173.11:38:15.51#ibcon#read 6, iclass 10, count 0 2006.173.11:38:15.51#ibcon#end of sib2, iclass 10, count 0 2006.173.11:38:15.51#ibcon#*after write, iclass 10, count 0 2006.173.11:38:15.52#ibcon#*before return 0, iclass 10, count 0 2006.173.11:38:15.52#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.11:38:15.52#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.11:38:15.52#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.11:38:15.52#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.11:38:15.52$vck44/vblo=3,649.99 2006.173.11:38:15.52#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.11:38:15.52#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.11:38:15.52#ibcon#ireg 17 cls_cnt 0 2006.173.11:38:15.52#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.11:38:15.52#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.11:38:15.52#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.11:38:15.52#ibcon#enter wrdev, iclass 12, count 0 2006.173.11:38:15.52#ibcon#first serial, iclass 12, count 0 2006.173.11:38:15.52#ibcon#enter sib2, iclass 12, count 0 2006.173.11:38:15.52#ibcon#flushed, iclass 12, count 0 2006.173.11:38:15.52#ibcon#about to write, iclass 12, count 0 2006.173.11:38:15.52#ibcon#wrote, iclass 12, count 0 2006.173.11:38:15.52#ibcon#about to read 3, iclass 12, count 0 2006.173.11:38:15.53#ibcon#read 3, iclass 12, count 0 2006.173.11:38:15.53#ibcon#about to read 4, iclass 12, count 0 2006.173.11:38:15.53#ibcon#read 4, iclass 12, count 0 2006.173.11:38:15.53#ibcon#about to read 5, iclass 12, count 0 2006.173.11:38:15.53#ibcon#read 5, iclass 12, count 0 2006.173.11:38:15.53#ibcon#about to read 6, iclass 12, count 0 2006.173.11:38:15.53#ibcon#read 6, iclass 12, count 0 2006.173.11:38:15.53#ibcon#end of sib2, iclass 12, count 0 2006.173.11:38:15.53#ibcon#*mode == 0, iclass 12, count 0 2006.173.11:38:15.53#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.11:38:15.54#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.11:38:15.54#ibcon#*before write, iclass 12, count 0 2006.173.11:38:15.54#ibcon#enter sib2, iclass 12, count 0 2006.173.11:38:15.54#ibcon#flushed, iclass 12, count 0 2006.173.11:38:15.54#ibcon#about to write, iclass 12, count 0 2006.173.11:38:15.54#ibcon#wrote, iclass 12, count 0 2006.173.11:38:15.54#ibcon#about to read 3, iclass 12, count 0 2006.173.11:38:15.57#ibcon#read 3, iclass 12, count 0 2006.173.11:38:15.57#ibcon#about to read 4, iclass 12, count 0 2006.173.11:38:15.57#ibcon#read 4, iclass 12, count 0 2006.173.11:38:15.58#ibcon#about to read 5, iclass 12, count 0 2006.173.11:38:15.58#ibcon#read 5, iclass 12, count 0 2006.173.11:38:15.58#ibcon#about to read 6, iclass 12, count 0 2006.173.11:38:15.58#ibcon#read 6, iclass 12, count 0 2006.173.11:38:15.58#ibcon#end of sib2, iclass 12, count 0 2006.173.11:38:15.58#ibcon#*after write, iclass 12, count 0 2006.173.11:38:15.58#ibcon#*before return 0, iclass 12, count 0 2006.173.11:38:15.58#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.11:38:15.58#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.11:38:15.58#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.11:38:15.58#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.11:38:15.58$vck44/vb=3,4 2006.173.11:38:15.58#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.11:38:15.58#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.11:38:15.58#ibcon#ireg 11 cls_cnt 2 2006.173.11:38:15.58#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.11:38:15.63#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.11:38:15.63#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.11:38:15.63#ibcon#enter wrdev, iclass 14, count 2 2006.173.11:38:15.63#ibcon#first serial, iclass 14, count 2 2006.173.11:38:15.63#ibcon#enter sib2, iclass 14, count 2 2006.173.11:38:15.63#ibcon#flushed, iclass 14, count 2 2006.173.11:38:15.63#ibcon#about to write, iclass 14, count 2 2006.173.11:38:15.64#ibcon#wrote, iclass 14, count 2 2006.173.11:38:15.64#ibcon#about to read 3, iclass 14, count 2 2006.173.11:38:15.65#ibcon#read 3, iclass 14, count 2 2006.173.11:38:15.65#ibcon#about to read 4, iclass 14, count 2 2006.173.11:38:15.65#ibcon#read 4, iclass 14, count 2 2006.173.11:38:15.65#ibcon#about to read 5, iclass 14, count 2 2006.173.11:38:15.65#ibcon#read 5, iclass 14, count 2 2006.173.11:38:15.65#ibcon#about to read 6, iclass 14, count 2 2006.173.11:38:15.65#ibcon#read 6, iclass 14, count 2 2006.173.11:38:15.66#ibcon#end of sib2, iclass 14, count 2 2006.173.11:38:15.66#ibcon#*mode == 0, iclass 14, count 2 2006.173.11:38:15.66#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.11:38:15.66#ibcon#[27=AT03-04\r\n] 2006.173.11:38:15.66#ibcon#*before write, iclass 14, count 2 2006.173.11:38:15.66#ibcon#enter sib2, iclass 14, count 2 2006.173.11:38:15.66#ibcon#flushed, iclass 14, count 2 2006.173.11:38:15.66#ibcon#about to write, iclass 14, count 2 2006.173.11:38:15.66#ibcon#wrote, iclass 14, count 2 2006.173.11:38:15.66#ibcon#about to read 3, iclass 14, count 2 2006.173.11:38:15.68#ibcon#read 3, iclass 14, count 2 2006.173.11:38:15.68#ibcon#about to read 4, iclass 14, count 2 2006.173.11:38:15.68#ibcon#read 4, iclass 14, count 2 2006.173.11:38:15.68#ibcon#about to read 5, iclass 14, count 2 2006.173.11:38:15.68#ibcon#read 5, iclass 14, count 2 2006.173.11:38:15.68#ibcon#about to read 6, iclass 14, count 2 2006.173.11:38:15.69#ibcon#read 6, iclass 14, count 2 2006.173.11:38:15.69#ibcon#end of sib2, iclass 14, count 2 2006.173.11:38:15.69#ibcon#*after write, iclass 14, count 2 2006.173.11:38:15.69#ibcon#*before return 0, iclass 14, count 2 2006.173.11:38:15.69#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.11:38:15.69#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.11:38:15.69#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.11:38:15.69#ibcon#ireg 7 cls_cnt 0 2006.173.11:38:15.69#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.11:38:15.80#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.11:38:15.80#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.11:38:15.80#ibcon#enter wrdev, iclass 14, count 0 2006.173.11:38:15.80#ibcon#first serial, iclass 14, count 0 2006.173.11:38:15.80#ibcon#enter sib2, iclass 14, count 0 2006.173.11:38:15.80#ibcon#flushed, iclass 14, count 0 2006.173.11:38:15.80#ibcon#about to write, iclass 14, count 0 2006.173.11:38:15.81#ibcon#wrote, iclass 14, count 0 2006.173.11:38:15.81#ibcon#about to read 3, iclass 14, count 0 2006.173.11:38:15.82#ibcon#read 3, iclass 14, count 0 2006.173.11:38:15.82#ibcon#about to read 4, iclass 14, count 0 2006.173.11:38:15.82#ibcon#read 4, iclass 14, count 0 2006.173.11:38:15.82#ibcon#about to read 5, iclass 14, count 0 2006.173.11:38:15.82#ibcon#read 5, iclass 14, count 0 2006.173.11:38:15.82#ibcon#about to read 6, iclass 14, count 0 2006.173.11:38:15.82#ibcon#read 6, iclass 14, count 0 2006.173.11:38:15.82#ibcon#end of sib2, iclass 14, count 0 2006.173.11:38:15.83#ibcon#*mode == 0, iclass 14, count 0 2006.173.11:38:15.83#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.11:38:15.83#ibcon#[27=USB\r\n] 2006.173.11:38:15.83#ibcon#*before write, iclass 14, count 0 2006.173.11:38:15.83#ibcon#enter sib2, iclass 14, count 0 2006.173.11:38:15.83#ibcon#flushed, iclass 14, count 0 2006.173.11:38:15.83#ibcon#about to write, iclass 14, count 0 2006.173.11:38:15.83#ibcon#wrote, iclass 14, count 0 2006.173.11:38:15.83#ibcon#about to read 3, iclass 14, count 0 2006.173.11:38:15.85#ibcon#read 3, iclass 14, count 0 2006.173.11:38:15.85#ibcon#about to read 4, iclass 14, count 0 2006.173.11:38:15.85#ibcon#read 4, iclass 14, count 0 2006.173.11:38:15.85#ibcon#about to read 5, iclass 14, count 0 2006.173.11:38:15.85#ibcon#read 5, iclass 14, count 0 2006.173.11:38:15.85#ibcon#about to read 6, iclass 14, count 0 2006.173.11:38:15.85#ibcon#read 6, iclass 14, count 0 2006.173.11:38:15.85#ibcon#end of sib2, iclass 14, count 0 2006.173.11:38:15.85#ibcon#*after write, iclass 14, count 0 2006.173.11:38:15.85#ibcon#*before return 0, iclass 14, count 0 2006.173.11:38:15.86#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.11:38:15.86#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.11:38:15.86#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.11:38:15.86#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.11:38:15.86$vck44/vblo=4,679.99 2006.173.11:38:15.86#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.11:38:15.86#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.11:38:15.86#ibcon#ireg 17 cls_cnt 0 2006.173.11:38:15.86#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.11:38:15.86#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.11:38:15.86#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.11:38:15.86#ibcon#enter wrdev, iclass 16, count 0 2006.173.11:38:15.86#ibcon#first serial, iclass 16, count 0 2006.173.11:38:15.86#ibcon#enter sib2, iclass 16, count 0 2006.173.11:38:15.86#ibcon#flushed, iclass 16, count 0 2006.173.11:38:15.86#ibcon#about to write, iclass 16, count 0 2006.173.11:38:15.86#ibcon#wrote, iclass 16, count 0 2006.173.11:38:15.86#ibcon#about to read 3, iclass 16, count 0 2006.173.11:38:15.87#ibcon#read 3, iclass 16, count 0 2006.173.11:38:15.87#ibcon#about to read 4, iclass 16, count 0 2006.173.11:38:15.87#ibcon#read 4, iclass 16, count 0 2006.173.11:38:15.87#ibcon#about to read 5, iclass 16, count 0 2006.173.11:38:15.87#ibcon#read 5, iclass 16, count 0 2006.173.11:38:15.87#ibcon#about to read 6, iclass 16, count 0 2006.173.11:38:15.87#ibcon#read 6, iclass 16, count 0 2006.173.11:38:15.87#ibcon#end of sib2, iclass 16, count 0 2006.173.11:38:15.87#ibcon#*mode == 0, iclass 16, count 0 2006.173.11:38:15.88#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.11:38:15.88#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.11:38:15.88#ibcon#*before write, iclass 16, count 0 2006.173.11:38:15.88#ibcon#enter sib2, iclass 16, count 0 2006.173.11:38:15.88#ibcon#flushed, iclass 16, count 0 2006.173.11:38:15.88#ibcon#about to write, iclass 16, count 0 2006.173.11:38:15.88#ibcon#wrote, iclass 16, count 0 2006.173.11:38:15.88#ibcon#about to read 3, iclass 16, count 0 2006.173.11:38:15.91#ibcon#read 3, iclass 16, count 0 2006.173.11:38:15.91#ibcon#about to read 4, iclass 16, count 0 2006.173.11:38:15.91#ibcon#read 4, iclass 16, count 0 2006.173.11:38:15.91#ibcon#about to read 5, iclass 16, count 0 2006.173.11:38:15.91#ibcon#read 5, iclass 16, count 0 2006.173.11:38:15.91#ibcon#about to read 6, iclass 16, count 0 2006.173.11:38:15.91#ibcon#read 6, iclass 16, count 0 2006.173.11:38:15.91#ibcon#end of sib2, iclass 16, count 0 2006.173.11:38:15.91#ibcon#*after write, iclass 16, count 0 2006.173.11:38:15.92#ibcon#*before return 0, iclass 16, count 0 2006.173.11:38:15.92#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.11:38:15.92#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.11:38:15.92#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.11:38:15.92#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.11:38:15.92$vck44/vb=4,4 2006.173.11:38:15.92#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.11:38:15.92#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.11:38:15.92#ibcon#ireg 11 cls_cnt 2 2006.173.11:38:15.92#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.11:38:15.97#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.11:38:15.97#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.11:38:15.97#ibcon#enter wrdev, iclass 18, count 2 2006.173.11:38:15.97#ibcon#first serial, iclass 18, count 2 2006.173.11:38:15.97#ibcon#enter sib2, iclass 18, count 2 2006.173.11:38:15.97#ibcon#flushed, iclass 18, count 2 2006.173.11:38:15.97#ibcon#about to write, iclass 18, count 2 2006.173.11:38:15.98#ibcon#wrote, iclass 18, count 2 2006.173.11:38:15.98#ibcon#about to read 3, iclass 18, count 2 2006.173.11:38:15.99#ibcon#read 3, iclass 18, count 2 2006.173.11:38:15.99#ibcon#about to read 4, iclass 18, count 2 2006.173.11:38:15.99#ibcon#read 4, iclass 18, count 2 2006.173.11:38:15.99#ibcon#about to read 5, iclass 18, count 2 2006.173.11:38:15.99#ibcon#read 5, iclass 18, count 2 2006.173.11:38:15.99#ibcon#about to read 6, iclass 18, count 2 2006.173.11:38:15.99#ibcon#read 6, iclass 18, count 2 2006.173.11:38:16.00#ibcon#end of sib2, iclass 18, count 2 2006.173.11:38:16.00#ibcon#*mode == 0, iclass 18, count 2 2006.173.11:38:16.00#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.11:38:16.00#ibcon#[27=AT04-04\r\n] 2006.173.11:38:16.00#ibcon#*before write, iclass 18, count 2 2006.173.11:38:16.00#ibcon#enter sib2, iclass 18, count 2 2006.173.11:38:16.00#ibcon#flushed, iclass 18, count 2 2006.173.11:38:16.00#ibcon#about to write, iclass 18, count 2 2006.173.11:38:16.00#ibcon#wrote, iclass 18, count 2 2006.173.11:38:16.00#ibcon#about to read 3, iclass 18, count 2 2006.173.11:38:16.02#ibcon#read 3, iclass 18, count 2 2006.173.11:38:16.02#ibcon#about to read 4, iclass 18, count 2 2006.173.11:38:16.02#ibcon#read 4, iclass 18, count 2 2006.173.11:38:16.02#ibcon#about to read 5, iclass 18, count 2 2006.173.11:38:16.02#ibcon#read 5, iclass 18, count 2 2006.173.11:38:16.02#ibcon#about to read 6, iclass 18, count 2 2006.173.11:38:16.02#ibcon#read 6, iclass 18, count 2 2006.173.11:38:16.02#ibcon#end of sib2, iclass 18, count 2 2006.173.11:38:16.02#ibcon#*after write, iclass 18, count 2 2006.173.11:38:16.02#ibcon#*before return 0, iclass 18, count 2 2006.173.11:38:16.03#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.11:38:16.03#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.11:38:16.03#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.11:38:16.03#ibcon#ireg 7 cls_cnt 0 2006.173.11:38:16.03#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.11:38:16.14#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.11:38:16.14#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.11:38:16.14#ibcon#enter wrdev, iclass 18, count 0 2006.173.11:38:16.14#ibcon#first serial, iclass 18, count 0 2006.173.11:38:16.14#ibcon#enter sib2, iclass 18, count 0 2006.173.11:38:16.14#ibcon#flushed, iclass 18, count 0 2006.173.11:38:16.14#ibcon#about to write, iclass 18, count 0 2006.173.11:38:16.14#ibcon#wrote, iclass 18, count 0 2006.173.11:38:16.15#ibcon#about to read 3, iclass 18, count 0 2006.173.11:38:16.16#ibcon#read 3, iclass 18, count 0 2006.173.11:38:16.17#ibcon#about to read 4, iclass 18, count 0 2006.173.11:38:16.17#ibcon#read 4, iclass 18, count 0 2006.173.11:38:16.17#ibcon#about to read 5, iclass 18, count 0 2006.173.11:38:16.17#ibcon#read 5, iclass 18, count 0 2006.173.11:38:16.17#ibcon#about to read 6, iclass 18, count 0 2006.173.11:38:16.17#ibcon#read 6, iclass 18, count 0 2006.173.11:38:16.17#ibcon#end of sib2, iclass 18, count 0 2006.173.11:38:16.17#ibcon#*mode == 0, iclass 18, count 0 2006.173.11:38:16.17#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.11:38:16.17#ibcon#[27=USB\r\n] 2006.173.11:38:16.17#ibcon#*before write, iclass 18, count 0 2006.173.11:38:16.17#ibcon#enter sib2, iclass 18, count 0 2006.173.11:38:16.17#ibcon#flushed, iclass 18, count 0 2006.173.11:38:16.17#ibcon#about to write, iclass 18, count 0 2006.173.11:38:16.17#ibcon#wrote, iclass 18, count 0 2006.173.11:38:16.17#ibcon#about to read 3, iclass 18, count 0 2006.173.11:38:16.19#ibcon#read 3, iclass 18, count 0 2006.173.11:38:16.19#ibcon#about to read 4, iclass 18, count 0 2006.173.11:38:16.19#ibcon#read 4, iclass 18, count 0 2006.173.11:38:16.19#ibcon#about to read 5, iclass 18, count 0 2006.173.11:38:16.19#ibcon#read 5, iclass 18, count 0 2006.173.11:38:16.19#ibcon#about to read 6, iclass 18, count 0 2006.173.11:38:16.19#ibcon#read 6, iclass 18, count 0 2006.173.11:38:16.19#ibcon#end of sib2, iclass 18, count 0 2006.173.11:38:16.20#ibcon#*after write, iclass 18, count 0 2006.173.11:38:16.20#ibcon#*before return 0, iclass 18, count 0 2006.173.11:38:16.20#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.11:38:16.20#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.11:38:16.20#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.11:38:16.20#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.11:38:16.20$vck44/vblo=5,709.99 2006.173.11:38:16.20#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.11:38:16.20#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.11:38:16.20#ibcon#ireg 17 cls_cnt 0 2006.173.11:38:16.20#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.11:38:16.20#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.11:38:16.20#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.11:38:16.20#ibcon#enter wrdev, iclass 20, count 0 2006.173.11:38:16.20#ibcon#first serial, iclass 20, count 0 2006.173.11:38:16.20#ibcon#enter sib2, iclass 20, count 0 2006.173.11:38:16.20#ibcon#flushed, iclass 20, count 0 2006.173.11:38:16.20#ibcon#about to write, iclass 20, count 0 2006.173.11:38:16.20#ibcon#wrote, iclass 20, count 0 2006.173.11:38:16.20#ibcon#about to read 3, iclass 20, count 0 2006.173.11:38:16.21#ibcon#read 3, iclass 20, count 0 2006.173.11:38:16.21#ibcon#about to read 4, iclass 20, count 0 2006.173.11:38:16.21#ibcon#read 4, iclass 20, count 0 2006.173.11:38:16.21#ibcon#about to read 5, iclass 20, count 0 2006.173.11:38:16.21#ibcon#read 5, iclass 20, count 0 2006.173.11:38:16.21#ibcon#about to read 6, iclass 20, count 0 2006.173.11:38:16.21#ibcon#read 6, iclass 20, count 0 2006.173.11:38:16.21#ibcon#end of sib2, iclass 20, count 0 2006.173.11:38:16.21#ibcon#*mode == 0, iclass 20, count 0 2006.173.11:38:16.21#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.11:38:16.22#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.11:38:16.22#ibcon#*before write, iclass 20, count 0 2006.173.11:38:16.22#ibcon#enter sib2, iclass 20, count 0 2006.173.11:38:16.22#ibcon#flushed, iclass 20, count 0 2006.173.11:38:16.22#ibcon#about to write, iclass 20, count 0 2006.173.11:38:16.22#ibcon#wrote, iclass 20, count 0 2006.173.11:38:16.22#ibcon#about to read 3, iclass 20, count 0 2006.173.11:38:16.25#ibcon#read 3, iclass 20, count 0 2006.173.11:38:16.25#ibcon#about to read 4, iclass 20, count 0 2006.173.11:38:16.25#ibcon#read 4, iclass 20, count 0 2006.173.11:38:16.25#ibcon#about to read 5, iclass 20, count 0 2006.173.11:38:16.25#ibcon#read 5, iclass 20, count 0 2006.173.11:38:16.25#ibcon#about to read 6, iclass 20, count 0 2006.173.11:38:16.25#ibcon#read 6, iclass 20, count 0 2006.173.11:38:16.25#ibcon#end of sib2, iclass 20, count 0 2006.173.11:38:16.25#ibcon#*after write, iclass 20, count 0 2006.173.11:38:16.25#ibcon#*before return 0, iclass 20, count 0 2006.173.11:38:16.26#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.11:38:16.26#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.11:38:16.26#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.11:38:16.26#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.11:38:16.26$vck44/vb=5,4 2006.173.11:38:16.26#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.11:38:16.26#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.11:38:16.26#ibcon#ireg 11 cls_cnt 2 2006.173.11:38:16.26#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.11:38:16.31#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.11:38:16.31#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.11:38:16.31#ibcon#enter wrdev, iclass 22, count 2 2006.173.11:38:16.31#ibcon#first serial, iclass 22, count 2 2006.173.11:38:16.31#ibcon#enter sib2, iclass 22, count 2 2006.173.11:38:16.31#ibcon#flushed, iclass 22, count 2 2006.173.11:38:16.31#ibcon#about to write, iclass 22, count 2 2006.173.11:38:16.31#ibcon#wrote, iclass 22, count 2 2006.173.11:38:16.32#ibcon#about to read 3, iclass 22, count 2 2006.173.11:38:16.33#ibcon#read 3, iclass 22, count 2 2006.173.11:38:16.33#ibcon#about to read 4, iclass 22, count 2 2006.173.11:38:16.33#ibcon#read 4, iclass 22, count 2 2006.173.11:38:16.33#ibcon#about to read 5, iclass 22, count 2 2006.173.11:38:16.33#ibcon#read 5, iclass 22, count 2 2006.173.11:38:16.33#ibcon#about to read 6, iclass 22, count 2 2006.173.11:38:16.33#ibcon#read 6, iclass 22, count 2 2006.173.11:38:16.34#ibcon#end of sib2, iclass 22, count 2 2006.173.11:38:16.34#ibcon#*mode == 0, iclass 22, count 2 2006.173.11:38:16.34#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.11:38:16.34#ibcon#[27=AT05-04\r\n] 2006.173.11:38:16.34#ibcon#*before write, iclass 22, count 2 2006.173.11:38:16.34#ibcon#enter sib2, iclass 22, count 2 2006.173.11:38:16.34#ibcon#flushed, iclass 22, count 2 2006.173.11:38:16.34#ibcon#about to write, iclass 22, count 2 2006.173.11:38:16.34#ibcon#wrote, iclass 22, count 2 2006.173.11:38:16.34#ibcon#about to read 3, iclass 22, count 2 2006.173.11:38:16.36#ibcon#read 3, iclass 22, count 2 2006.173.11:38:16.36#ibcon#about to read 4, iclass 22, count 2 2006.173.11:38:16.36#ibcon#read 4, iclass 22, count 2 2006.173.11:38:16.36#ibcon#about to read 5, iclass 22, count 2 2006.173.11:38:16.36#ibcon#read 5, iclass 22, count 2 2006.173.11:38:16.36#ibcon#about to read 6, iclass 22, count 2 2006.173.11:38:16.36#ibcon#read 6, iclass 22, count 2 2006.173.11:38:16.36#ibcon#end of sib2, iclass 22, count 2 2006.173.11:38:16.36#ibcon#*after write, iclass 22, count 2 2006.173.11:38:16.36#ibcon#*before return 0, iclass 22, count 2 2006.173.11:38:16.36#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.11:38:16.36#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.11:38:16.37#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.11:38:16.37#ibcon#ireg 7 cls_cnt 0 2006.173.11:38:16.37#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.11:38:16.47#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.11:38:16.47#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.11:38:16.47#ibcon#enter wrdev, iclass 22, count 0 2006.173.11:38:16.47#ibcon#first serial, iclass 22, count 0 2006.173.11:38:16.47#ibcon#enter sib2, iclass 22, count 0 2006.173.11:38:16.47#ibcon#flushed, iclass 22, count 0 2006.173.11:38:16.47#ibcon#about to write, iclass 22, count 0 2006.173.11:38:16.47#ibcon#wrote, iclass 22, count 0 2006.173.11:38:16.48#ibcon#about to read 3, iclass 22, count 0 2006.173.11:38:16.49#ibcon#read 3, iclass 22, count 0 2006.173.11:38:16.49#ibcon#about to read 4, iclass 22, count 0 2006.173.11:38:16.49#ibcon#read 4, iclass 22, count 0 2006.173.11:38:16.49#ibcon#about to read 5, iclass 22, count 0 2006.173.11:38:16.49#ibcon#read 5, iclass 22, count 0 2006.173.11:38:16.49#ibcon#about to read 6, iclass 22, count 0 2006.173.11:38:16.49#ibcon#read 6, iclass 22, count 0 2006.173.11:38:16.49#ibcon#end of sib2, iclass 22, count 0 2006.173.11:38:16.49#ibcon#*mode == 0, iclass 22, count 0 2006.173.11:38:16.49#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.11:38:16.49#ibcon#[27=USB\r\n] 2006.173.11:38:16.50#ibcon#*before write, iclass 22, count 0 2006.173.11:38:16.50#ibcon#enter sib2, iclass 22, count 0 2006.173.11:38:16.50#ibcon#flushed, iclass 22, count 0 2006.173.11:38:16.50#ibcon#about to write, iclass 22, count 0 2006.173.11:38:16.50#ibcon#wrote, iclass 22, count 0 2006.173.11:38:16.50#ibcon#about to read 3, iclass 22, count 0 2006.173.11:38:16.52#ibcon#read 3, iclass 22, count 0 2006.173.11:38:16.52#ibcon#about to read 4, iclass 22, count 0 2006.173.11:38:16.52#ibcon#read 4, iclass 22, count 0 2006.173.11:38:16.52#ibcon#about to read 5, iclass 22, count 0 2006.173.11:38:16.52#ibcon#read 5, iclass 22, count 0 2006.173.11:38:16.52#ibcon#about to read 6, iclass 22, count 0 2006.173.11:38:16.52#ibcon#read 6, iclass 22, count 0 2006.173.11:38:16.52#ibcon#end of sib2, iclass 22, count 0 2006.173.11:38:16.52#ibcon#*after write, iclass 22, count 0 2006.173.11:38:16.52#ibcon#*before return 0, iclass 22, count 0 2006.173.11:38:16.53#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.11:38:16.53#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.11:38:16.53#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.11:38:16.53#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.11:38:16.53$vck44/vblo=6,719.99 2006.173.11:38:16.53#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.11:38:16.53#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.11:38:16.53#ibcon#ireg 17 cls_cnt 0 2006.173.11:38:16.53#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.11:38:16.53#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.11:38:16.53#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.11:38:16.53#ibcon#enter wrdev, iclass 24, count 0 2006.173.11:38:16.53#ibcon#first serial, iclass 24, count 0 2006.173.11:38:16.53#ibcon#enter sib2, iclass 24, count 0 2006.173.11:38:16.53#ibcon#flushed, iclass 24, count 0 2006.173.11:38:16.53#ibcon#about to write, iclass 24, count 0 2006.173.11:38:16.53#ibcon#wrote, iclass 24, count 0 2006.173.11:38:16.53#ibcon#about to read 3, iclass 24, count 0 2006.173.11:38:16.54#ibcon#read 3, iclass 24, count 0 2006.173.11:38:16.54#ibcon#about to read 4, iclass 24, count 0 2006.173.11:38:16.54#ibcon#read 4, iclass 24, count 0 2006.173.11:38:16.54#ibcon#about to read 5, iclass 24, count 0 2006.173.11:38:16.54#ibcon#read 5, iclass 24, count 0 2006.173.11:38:16.54#ibcon#about to read 6, iclass 24, count 0 2006.173.11:38:16.54#ibcon#read 6, iclass 24, count 0 2006.173.11:38:16.55#ibcon#end of sib2, iclass 24, count 0 2006.173.11:38:16.55#ibcon#*mode == 0, iclass 24, count 0 2006.173.11:38:16.55#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.11:38:16.55#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.11:38:16.55#ibcon#*before write, iclass 24, count 0 2006.173.11:38:16.55#ibcon#enter sib2, iclass 24, count 0 2006.173.11:38:16.55#ibcon#flushed, iclass 24, count 0 2006.173.11:38:16.55#ibcon#about to write, iclass 24, count 0 2006.173.11:38:16.55#ibcon#wrote, iclass 24, count 0 2006.173.11:38:16.55#ibcon#about to read 3, iclass 24, count 0 2006.173.11:38:16.58#ibcon#read 3, iclass 24, count 0 2006.173.11:38:16.58#ibcon#about to read 4, iclass 24, count 0 2006.173.11:38:16.58#ibcon#read 4, iclass 24, count 0 2006.173.11:38:16.58#ibcon#about to read 5, iclass 24, count 0 2006.173.11:38:16.58#ibcon#read 5, iclass 24, count 0 2006.173.11:38:16.58#ibcon#about to read 6, iclass 24, count 0 2006.173.11:38:16.58#ibcon#read 6, iclass 24, count 0 2006.173.11:38:16.59#ibcon#end of sib2, iclass 24, count 0 2006.173.11:38:16.59#ibcon#*after write, iclass 24, count 0 2006.173.11:38:16.59#ibcon#*before return 0, iclass 24, count 0 2006.173.11:38:16.59#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.11:38:16.59#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.11:38:16.59#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.11:38:16.59#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.11:38:16.59$vck44/vb=6,4 2006.173.11:38:16.59#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.11:38:16.59#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.11:38:16.59#ibcon#ireg 11 cls_cnt 2 2006.173.11:38:16.59#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.11:38:16.64#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.11:38:16.64#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.11:38:16.64#ibcon#enter wrdev, iclass 26, count 2 2006.173.11:38:16.64#ibcon#first serial, iclass 26, count 2 2006.173.11:38:16.64#ibcon#enter sib2, iclass 26, count 2 2006.173.11:38:16.64#ibcon#flushed, iclass 26, count 2 2006.173.11:38:16.64#ibcon#about to write, iclass 26, count 2 2006.173.11:38:16.64#ibcon#wrote, iclass 26, count 2 2006.173.11:38:16.65#ibcon#about to read 3, iclass 26, count 2 2006.173.11:38:16.66#ibcon#read 3, iclass 26, count 2 2006.173.11:38:16.66#ibcon#about to read 4, iclass 26, count 2 2006.173.11:38:16.66#ibcon#read 4, iclass 26, count 2 2006.173.11:38:16.66#ibcon#about to read 5, iclass 26, count 2 2006.173.11:38:16.66#ibcon#read 5, iclass 26, count 2 2006.173.11:38:16.66#ibcon#about to read 6, iclass 26, count 2 2006.173.11:38:16.66#ibcon#read 6, iclass 26, count 2 2006.173.11:38:16.66#ibcon#end of sib2, iclass 26, count 2 2006.173.11:38:16.66#ibcon#*mode == 0, iclass 26, count 2 2006.173.11:38:16.66#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.11:38:16.66#ibcon#[27=AT06-04\r\n] 2006.173.11:38:16.66#ibcon#*before write, iclass 26, count 2 2006.173.11:38:16.67#ibcon#enter sib2, iclass 26, count 2 2006.173.11:38:16.67#ibcon#flushed, iclass 26, count 2 2006.173.11:38:16.67#ibcon#about to write, iclass 26, count 2 2006.173.11:38:16.67#ibcon#wrote, iclass 26, count 2 2006.173.11:38:16.67#ibcon#about to read 3, iclass 26, count 2 2006.173.11:38:16.69#ibcon#read 3, iclass 26, count 2 2006.173.11:38:16.69#ibcon#about to read 4, iclass 26, count 2 2006.173.11:38:16.69#ibcon#read 4, iclass 26, count 2 2006.173.11:38:16.69#ibcon#about to read 5, iclass 26, count 2 2006.173.11:38:16.70#ibcon#read 5, iclass 26, count 2 2006.173.11:38:16.70#ibcon#about to read 6, iclass 26, count 2 2006.173.11:38:16.70#ibcon#read 6, iclass 26, count 2 2006.173.11:38:16.70#ibcon#end of sib2, iclass 26, count 2 2006.173.11:38:16.70#ibcon#*after write, iclass 26, count 2 2006.173.11:38:16.70#ibcon#*before return 0, iclass 26, count 2 2006.173.11:38:16.70#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.11:38:16.70#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.11:38:16.70#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.11:38:16.70#ibcon#ireg 7 cls_cnt 0 2006.173.11:38:16.70#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.11:38:16.81#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.11:38:16.81#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.11:38:16.81#ibcon#enter wrdev, iclass 26, count 0 2006.173.11:38:16.81#ibcon#first serial, iclass 26, count 0 2006.173.11:38:16.81#ibcon#enter sib2, iclass 26, count 0 2006.173.11:38:16.81#ibcon#flushed, iclass 26, count 0 2006.173.11:38:16.81#ibcon#about to write, iclass 26, count 0 2006.173.11:38:16.82#ibcon#wrote, iclass 26, count 0 2006.173.11:38:16.82#ibcon#about to read 3, iclass 26, count 0 2006.173.11:38:16.83#ibcon#read 3, iclass 26, count 0 2006.173.11:38:16.83#ibcon#about to read 4, iclass 26, count 0 2006.173.11:38:16.83#ibcon#read 4, iclass 26, count 0 2006.173.11:38:16.83#ibcon#about to read 5, iclass 26, count 0 2006.173.11:38:16.83#ibcon#read 5, iclass 26, count 0 2006.173.11:38:16.83#ibcon#about to read 6, iclass 26, count 0 2006.173.11:38:16.83#ibcon#read 6, iclass 26, count 0 2006.173.11:38:16.84#ibcon#end of sib2, iclass 26, count 0 2006.173.11:38:16.84#ibcon#*mode == 0, iclass 26, count 0 2006.173.11:38:16.84#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.11:38:16.84#ibcon#[27=USB\r\n] 2006.173.11:38:16.84#ibcon#*before write, iclass 26, count 0 2006.173.11:38:16.84#ibcon#enter sib2, iclass 26, count 0 2006.173.11:38:16.84#ibcon#flushed, iclass 26, count 0 2006.173.11:38:16.84#ibcon#about to write, iclass 26, count 0 2006.173.11:38:16.84#ibcon#wrote, iclass 26, count 0 2006.173.11:38:16.84#ibcon#about to read 3, iclass 26, count 0 2006.173.11:38:16.86#ibcon#read 3, iclass 26, count 0 2006.173.11:38:16.86#ibcon#about to read 4, iclass 26, count 0 2006.173.11:38:16.86#ibcon#read 4, iclass 26, count 0 2006.173.11:38:16.86#ibcon#about to read 5, iclass 26, count 0 2006.173.11:38:16.86#ibcon#read 5, iclass 26, count 0 2006.173.11:38:16.86#ibcon#about to read 6, iclass 26, count 0 2006.173.11:38:16.86#ibcon#read 6, iclass 26, count 0 2006.173.11:38:16.87#ibcon#end of sib2, iclass 26, count 0 2006.173.11:38:16.87#ibcon#*after write, iclass 26, count 0 2006.173.11:38:16.87#ibcon#*before return 0, iclass 26, count 0 2006.173.11:38:16.87#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.11:38:16.87#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.11:38:16.87#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.11:38:16.87#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.11:38:16.87$vck44/vblo=7,734.99 2006.173.11:38:16.87#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.11:38:16.87#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.11:38:16.87#ibcon#ireg 17 cls_cnt 0 2006.173.11:38:16.87#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.11:38:16.87#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.11:38:16.87#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.11:38:16.87#ibcon#enter wrdev, iclass 28, count 0 2006.173.11:38:16.87#ibcon#first serial, iclass 28, count 0 2006.173.11:38:16.87#ibcon#enter sib2, iclass 28, count 0 2006.173.11:38:16.87#ibcon#flushed, iclass 28, count 0 2006.173.11:38:16.87#ibcon#about to write, iclass 28, count 0 2006.173.11:38:16.87#ibcon#wrote, iclass 28, count 0 2006.173.11:38:16.87#ibcon#about to read 3, iclass 28, count 0 2006.173.11:38:16.88#ibcon#read 3, iclass 28, count 0 2006.173.11:38:16.88#ibcon#about to read 4, iclass 28, count 0 2006.173.11:38:16.88#ibcon#read 4, iclass 28, count 0 2006.173.11:38:16.88#ibcon#about to read 5, iclass 28, count 0 2006.173.11:38:16.88#ibcon#read 5, iclass 28, count 0 2006.173.11:38:16.88#ibcon#about to read 6, iclass 28, count 0 2006.173.11:38:16.88#ibcon#read 6, iclass 28, count 0 2006.173.11:38:16.89#ibcon#end of sib2, iclass 28, count 0 2006.173.11:38:16.89#ibcon#*mode == 0, iclass 28, count 0 2006.173.11:38:16.89#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.11:38:16.89#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.11:38:16.89#ibcon#*before write, iclass 28, count 0 2006.173.11:38:16.89#ibcon#enter sib2, iclass 28, count 0 2006.173.11:38:16.89#ibcon#flushed, iclass 28, count 0 2006.173.11:38:16.89#ibcon#about to write, iclass 28, count 0 2006.173.11:38:16.89#ibcon#wrote, iclass 28, count 0 2006.173.11:38:16.89#ibcon#about to read 3, iclass 28, count 0 2006.173.11:38:16.92#ibcon#read 3, iclass 28, count 0 2006.173.11:38:16.92#ibcon#about to read 4, iclass 28, count 0 2006.173.11:38:16.92#ibcon#read 4, iclass 28, count 0 2006.173.11:38:16.92#ibcon#about to read 5, iclass 28, count 0 2006.173.11:38:16.92#ibcon#read 5, iclass 28, count 0 2006.173.11:38:16.92#ibcon#about to read 6, iclass 28, count 0 2006.173.11:38:16.92#ibcon#read 6, iclass 28, count 0 2006.173.11:38:16.92#ibcon#end of sib2, iclass 28, count 0 2006.173.11:38:16.93#ibcon#*after write, iclass 28, count 0 2006.173.11:38:16.93#ibcon#*before return 0, iclass 28, count 0 2006.173.11:38:16.93#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.11:38:16.93#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.11:38:16.93#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.11:38:16.93#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.11:38:16.93$vck44/vb=7,4 2006.173.11:38:16.93#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.11:38:16.93#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.11:38:16.93#ibcon#ireg 11 cls_cnt 2 2006.173.11:38:16.93#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.11:38:16.98#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.11:38:16.98#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.11:38:16.98#ibcon#enter wrdev, iclass 30, count 2 2006.173.11:38:16.98#ibcon#first serial, iclass 30, count 2 2006.173.11:38:16.98#ibcon#enter sib2, iclass 30, count 2 2006.173.11:38:16.98#ibcon#flushed, iclass 30, count 2 2006.173.11:38:16.98#ibcon#about to write, iclass 30, count 2 2006.173.11:38:16.98#ibcon#wrote, iclass 30, count 2 2006.173.11:38:16.99#ibcon#about to read 3, iclass 30, count 2 2006.173.11:38:17.00#ibcon#read 3, iclass 30, count 2 2006.173.11:38:17.00#ibcon#about to read 4, iclass 30, count 2 2006.173.11:38:17.00#ibcon#read 4, iclass 30, count 2 2006.173.11:38:17.00#ibcon#about to read 5, iclass 30, count 2 2006.173.11:38:17.00#ibcon#read 5, iclass 30, count 2 2006.173.11:38:17.00#ibcon#about to read 6, iclass 30, count 2 2006.173.11:38:17.00#ibcon#read 6, iclass 30, count 2 2006.173.11:38:17.00#ibcon#end of sib2, iclass 30, count 2 2006.173.11:38:17.01#ibcon#*mode == 0, iclass 30, count 2 2006.173.11:38:17.01#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.11:38:17.01#ibcon#[27=AT07-04\r\n] 2006.173.11:38:17.01#ibcon#*before write, iclass 30, count 2 2006.173.11:38:17.01#ibcon#enter sib2, iclass 30, count 2 2006.173.11:38:17.01#ibcon#flushed, iclass 30, count 2 2006.173.11:38:17.01#ibcon#about to write, iclass 30, count 2 2006.173.11:38:17.01#ibcon#wrote, iclass 30, count 2 2006.173.11:38:17.01#ibcon#about to read 3, iclass 30, count 2 2006.173.11:38:17.03#ibcon#read 3, iclass 30, count 2 2006.173.11:38:17.03#ibcon#about to read 4, iclass 30, count 2 2006.173.11:38:17.03#ibcon#read 4, iclass 30, count 2 2006.173.11:38:17.03#ibcon#about to read 5, iclass 30, count 2 2006.173.11:38:17.03#ibcon#read 5, iclass 30, count 2 2006.173.11:38:17.03#ibcon#about to read 6, iclass 30, count 2 2006.173.11:38:17.03#ibcon#read 6, iclass 30, count 2 2006.173.11:38:17.03#ibcon#end of sib2, iclass 30, count 2 2006.173.11:38:17.03#ibcon#*after write, iclass 30, count 2 2006.173.11:38:17.04#ibcon#*before return 0, iclass 30, count 2 2006.173.11:38:17.04#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.11:38:17.04#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.11:38:17.04#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.11:38:17.04#ibcon#ireg 7 cls_cnt 0 2006.173.11:38:17.04#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.11:38:17.15#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.11:38:17.15#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.11:38:17.15#ibcon#enter wrdev, iclass 30, count 0 2006.173.11:38:17.15#ibcon#first serial, iclass 30, count 0 2006.173.11:38:17.15#ibcon#enter sib2, iclass 30, count 0 2006.173.11:38:17.15#ibcon#flushed, iclass 30, count 0 2006.173.11:38:17.15#ibcon#about to write, iclass 30, count 0 2006.173.11:38:17.16#ibcon#wrote, iclass 30, count 0 2006.173.11:38:17.16#ibcon#about to read 3, iclass 30, count 0 2006.173.11:38:17.17#ibcon#read 3, iclass 30, count 0 2006.173.11:38:17.17#ibcon#about to read 4, iclass 30, count 0 2006.173.11:38:17.17#ibcon#read 4, iclass 30, count 0 2006.173.11:38:17.17#ibcon#about to read 5, iclass 30, count 0 2006.173.11:38:17.17#ibcon#read 5, iclass 30, count 0 2006.173.11:38:17.17#ibcon#about to read 6, iclass 30, count 0 2006.173.11:38:17.17#ibcon#read 6, iclass 30, count 0 2006.173.11:38:17.18#ibcon#end of sib2, iclass 30, count 0 2006.173.11:38:17.18#ibcon#*mode == 0, iclass 30, count 0 2006.173.11:38:17.18#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.11:38:17.18#ibcon#[27=USB\r\n] 2006.173.11:38:17.18#ibcon#*before write, iclass 30, count 0 2006.173.11:38:17.18#ibcon#enter sib2, iclass 30, count 0 2006.173.11:38:17.18#ibcon#flushed, iclass 30, count 0 2006.173.11:38:17.18#ibcon#about to write, iclass 30, count 0 2006.173.11:38:17.18#ibcon#wrote, iclass 30, count 0 2006.173.11:38:17.18#ibcon#about to read 3, iclass 30, count 0 2006.173.11:38:17.20#ibcon#read 3, iclass 30, count 0 2006.173.11:38:17.20#ibcon#about to read 4, iclass 30, count 0 2006.173.11:38:17.20#ibcon#read 4, iclass 30, count 0 2006.173.11:38:17.20#ibcon#about to read 5, iclass 30, count 0 2006.173.11:38:17.20#ibcon#read 5, iclass 30, count 0 2006.173.11:38:17.20#ibcon#about to read 6, iclass 30, count 0 2006.173.11:38:17.20#ibcon#read 6, iclass 30, count 0 2006.173.11:38:17.21#ibcon#end of sib2, iclass 30, count 0 2006.173.11:38:17.21#ibcon#*after write, iclass 30, count 0 2006.173.11:38:17.21#ibcon#*before return 0, iclass 30, count 0 2006.173.11:38:17.21#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.11:38:17.21#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.11:38:17.21#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.11:38:17.21#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.11:38:17.21$vck44/vblo=8,744.99 2006.173.11:38:17.21#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.11:38:17.21#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.11:38:17.21#ibcon#ireg 17 cls_cnt 0 2006.173.11:38:17.21#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.11:38:17.21#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.11:38:17.21#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.11:38:17.21#ibcon#enter wrdev, iclass 32, count 0 2006.173.11:38:17.21#ibcon#first serial, iclass 32, count 0 2006.173.11:38:17.21#ibcon#enter sib2, iclass 32, count 0 2006.173.11:38:17.21#ibcon#flushed, iclass 32, count 0 2006.173.11:38:17.21#ibcon#about to write, iclass 32, count 0 2006.173.11:38:17.21#ibcon#wrote, iclass 32, count 0 2006.173.11:38:17.21#ibcon#about to read 3, iclass 32, count 0 2006.173.11:38:17.22#ibcon#read 3, iclass 32, count 0 2006.173.11:38:17.22#ibcon#about to read 4, iclass 32, count 0 2006.173.11:38:17.22#ibcon#read 4, iclass 32, count 0 2006.173.11:38:17.22#ibcon#about to read 5, iclass 32, count 0 2006.173.11:38:17.22#ibcon#read 5, iclass 32, count 0 2006.173.11:38:17.23#ibcon#about to read 6, iclass 32, count 0 2006.173.11:38:17.23#ibcon#read 6, iclass 32, count 0 2006.173.11:38:17.23#ibcon#end of sib2, iclass 32, count 0 2006.173.11:38:17.23#ibcon#*mode == 0, iclass 32, count 0 2006.173.11:38:17.23#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.11:38:17.23#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.11:38:17.23#ibcon#*before write, iclass 32, count 0 2006.173.11:38:17.23#ibcon#enter sib2, iclass 32, count 0 2006.173.11:38:17.23#ibcon#flushed, iclass 32, count 0 2006.173.11:38:17.23#ibcon#about to write, iclass 32, count 0 2006.173.11:38:17.23#ibcon#wrote, iclass 32, count 0 2006.173.11:38:17.23#ibcon#about to read 3, iclass 32, count 0 2006.173.11:38:17.26#ibcon#read 3, iclass 32, count 0 2006.173.11:38:17.26#ibcon#about to read 4, iclass 32, count 0 2006.173.11:38:17.26#ibcon#read 4, iclass 32, count 0 2006.173.11:38:17.26#ibcon#about to read 5, iclass 32, count 0 2006.173.11:38:17.26#ibcon#read 5, iclass 32, count 0 2006.173.11:38:17.26#ibcon#about to read 6, iclass 32, count 0 2006.173.11:38:17.26#ibcon#read 6, iclass 32, count 0 2006.173.11:38:17.27#ibcon#end of sib2, iclass 32, count 0 2006.173.11:38:17.27#ibcon#*after write, iclass 32, count 0 2006.173.11:38:17.27#ibcon#*before return 0, iclass 32, count 0 2006.173.11:38:17.27#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.11:38:17.27#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.11:38:17.27#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.11:38:17.27#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.11:38:17.27$vck44/vb=8,4 2006.173.11:38:17.27#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.11:38:17.27#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.11:38:17.27#ibcon#ireg 11 cls_cnt 2 2006.173.11:38:17.27#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.11:38:17.32#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.11:38:17.32#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.11:38:17.32#ibcon#enter wrdev, iclass 34, count 2 2006.173.11:38:17.32#ibcon#first serial, iclass 34, count 2 2006.173.11:38:17.32#ibcon#enter sib2, iclass 34, count 2 2006.173.11:38:17.32#ibcon#flushed, iclass 34, count 2 2006.173.11:38:17.32#ibcon#about to write, iclass 34, count 2 2006.173.11:38:17.32#ibcon#wrote, iclass 34, count 2 2006.173.11:38:17.33#ibcon#about to read 3, iclass 34, count 2 2006.173.11:38:17.34#ibcon#read 3, iclass 34, count 2 2006.173.11:38:17.34#ibcon#about to read 4, iclass 34, count 2 2006.173.11:38:17.34#ibcon#read 4, iclass 34, count 2 2006.173.11:38:17.34#ibcon#about to read 5, iclass 34, count 2 2006.173.11:38:17.34#ibcon#read 5, iclass 34, count 2 2006.173.11:38:17.34#ibcon#about to read 6, iclass 34, count 2 2006.173.11:38:17.34#ibcon#read 6, iclass 34, count 2 2006.173.11:38:17.34#ibcon#end of sib2, iclass 34, count 2 2006.173.11:38:17.34#ibcon#*mode == 0, iclass 34, count 2 2006.173.11:38:17.34#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.11:38:17.34#ibcon#[27=AT08-04\r\n] 2006.173.11:38:17.35#ibcon#*before write, iclass 34, count 2 2006.173.11:38:17.35#ibcon#enter sib2, iclass 34, count 2 2006.173.11:38:17.35#ibcon#flushed, iclass 34, count 2 2006.173.11:38:17.35#ibcon#about to write, iclass 34, count 2 2006.173.11:38:17.35#ibcon#wrote, iclass 34, count 2 2006.173.11:38:17.35#ibcon#about to read 3, iclass 34, count 2 2006.173.11:38:17.37#ibcon#read 3, iclass 34, count 2 2006.173.11:38:17.37#ibcon#about to read 4, iclass 34, count 2 2006.173.11:38:17.37#ibcon#read 4, iclass 34, count 2 2006.173.11:38:17.37#ibcon#about to read 5, iclass 34, count 2 2006.173.11:38:17.37#ibcon#read 5, iclass 34, count 2 2006.173.11:38:17.37#ibcon#about to read 6, iclass 34, count 2 2006.173.11:38:17.37#ibcon#read 6, iclass 34, count 2 2006.173.11:38:17.37#ibcon#end of sib2, iclass 34, count 2 2006.173.11:38:17.37#ibcon#*after write, iclass 34, count 2 2006.173.11:38:17.37#ibcon#*before return 0, iclass 34, count 2 2006.173.11:38:17.38#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.11:38:17.38#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.11:38:17.38#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.11:38:17.38#ibcon#ireg 7 cls_cnt 0 2006.173.11:38:17.38#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.11:38:17.49#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.11:38:17.49#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.11:38:17.49#ibcon#enter wrdev, iclass 34, count 0 2006.173.11:38:17.49#ibcon#first serial, iclass 34, count 0 2006.173.11:38:17.49#ibcon#enter sib2, iclass 34, count 0 2006.173.11:38:17.49#ibcon#flushed, iclass 34, count 0 2006.173.11:38:17.49#ibcon#about to write, iclass 34, count 0 2006.173.11:38:17.50#ibcon#wrote, iclass 34, count 0 2006.173.11:38:17.50#ibcon#about to read 3, iclass 34, count 0 2006.173.11:38:17.51#ibcon#read 3, iclass 34, count 0 2006.173.11:38:17.51#ibcon#about to read 4, iclass 34, count 0 2006.173.11:38:17.51#ibcon#read 4, iclass 34, count 0 2006.173.11:38:17.51#ibcon#about to read 5, iclass 34, count 0 2006.173.11:38:17.51#ibcon#read 5, iclass 34, count 0 2006.173.11:38:17.51#ibcon#about to read 6, iclass 34, count 0 2006.173.11:38:17.51#ibcon#read 6, iclass 34, count 0 2006.173.11:38:17.51#ibcon#end of sib2, iclass 34, count 0 2006.173.11:38:17.51#ibcon#*mode == 0, iclass 34, count 0 2006.173.11:38:17.51#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.11:38:17.51#ibcon#[27=USB\r\n] 2006.173.11:38:17.52#ibcon#*before write, iclass 34, count 0 2006.173.11:38:17.52#ibcon#enter sib2, iclass 34, count 0 2006.173.11:38:17.52#ibcon#flushed, iclass 34, count 0 2006.173.11:38:17.52#ibcon#about to write, iclass 34, count 0 2006.173.11:38:17.52#ibcon#wrote, iclass 34, count 0 2006.173.11:38:17.52#ibcon#about to read 3, iclass 34, count 0 2006.173.11:38:17.54#ibcon#read 3, iclass 34, count 0 2006.173.11:38:17.54#ibcon#about to read 4, iclass 34, count 0 2006.173.11:38:17.54#ibcon#read 4, iclass 34, count 0 2006.173.11:38:17.54#ibcon#about to read 5, iclass 34, count 0 2006.173.11:38:17.54#ibcon#read 5, iclass 34, count 0 2006.173.11:38:17.54#ibcon#about to read 6, iclass 34, count 0 2006.173.11:38:17.54#ibcon#read 6, iclass 34, count 0 2006.173.11:38:17.54#ibcon#end of sib2, iclass 34, count 0 2006.173.11:38:17.55#ibcon#*after write, iclass 34, count 0 2006.173.11:38:17.55#ibcon#*before return 0, iclass 34, count 0 2006.173.11:38:17.55#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.11:38:17.55#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.11:38:17.55#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.11:38:17.55#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.11:38:17.55$vck44/vabw=wide 2006.173.11:38:17.55#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.11:38:17.55#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.11:38:17.55#ibcon#ireg 8 cls_cnt 0 2006.173.11:38:17.55#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.11:38:17.55#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.11:38:17.55#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.11:38:17.55#ibcon#enter wrdev, iclass 36, count 0 2006.173.11:38:17.55#ibcon#first serial, iclass 36, count 0 2006.173.11:38:17.55#ibcon#enter sib2, iclass 36, count 0 2006.173.11:38:17.55#ibcon#flushed, iclass 36, count 0 2006.173.11:38:17.55#ibcon#about to write, iclass 36, count 0 2006.173.11:38:17.55#ibcon#wrote, iclass 36, count 0 2006.173.11:38:17.55#ibcon#about to read 3, iclass 36, count 0 2006.173.11:38:17.56#ibcon#read 3, iclass 36, count 0 2006.173.11:38:17.56#ibcon#about to read 4, iclass 36, count 0 2006.173.11:38:17.56#ibcon#read 4, iclass 36, count 0 2006.173.11:38:17.56#ibcon#about to read 5, iclass 36, count 0 2006.173.11:38:17.56#ibcon#read 5, iclass 36, count 0 2006.173.11:38:17.56#ibcon#about to read 6, iclass 36, count 0 2006.173.11:38:17.56#ibcon#read 6, iclass 36, count 0 2006.173.11:38:17.56#ibcon#end of sib2, iclass 36, count 0 2006.173.11:38:17.56#ibcon#*mode == 0, iclass 36, count 0 2006.173.11:38:17.56#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.11:38:17.56#ibcon#[25=BW32\r\n] 2006.173.11:38:17.57#ibcon#*before write, iclass 36, count 0 2006.173.11:38:17.57#ibcon#enter sib2, iclass 36, count 0 2006.173.11:38:17.57#ibcon#flushed, iclass 36, count 0 2006.173.11:38:17.57#ibcon#about to write, iclass 36, count 0 2006.173.11:38:17.57#ibcon#wrote, iclass 36, count 0 2006.173.11:38:17.57#ibcon#about to read 3, iclass 36, count 0 2006.173.11:38:17.59#ibcon#read 3, iclass 36, count 0 2006.173.11:38:17.59#ibcon#about to read 4, iclass 36, count 0 2006.173.11:38:17.59#ibcon#read 4, iclass 36, count 0 2006.173.11:38:17.59#ibcon#about to read 5, iclass 36, count 0 2006.173.11:38:17.59#ibcon#read 5, iclass 36, count 0 2006.173.11:38:17.59#ibcon#about to read 6, iclass 36, count 0 2006.173.11:38:17.59#ibcon#read 6, iclass 36, count 0 2006.173.11:38:17.59#ibcon#end of sib2, iclass 36, count 0 2006.173.11:38:17.59#ibcon#*after write, iclass 36, count 0 2006.173.11:38:17.60#ibcon#*before return 0, iclass 36, count 0 2006.173.11:38:17.60#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.11:38:17.60#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.11:38:17.60#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.11:38:17.60#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.11:38:17.60$vck44/vbbw=wide 2006.173.11:38:17.60#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.11:38:17.60#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.11:38:17.60#ibcon#ireg 8 cls_cnt 0 2006.173.11:38:17.60#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.11:38:17.66#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.11:38:17.66#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.11:38:17.66#ibcon#enter wrdev, iclass 38, count 0 2006.173.11:38:17.66#ibcon#first serial, iclass 38, count 0 2006.173.11:38:17.66#ibcon#enter sib2, iclass 38, count 0 2006.173.11:38:17.66#ibcon#flushed, iclass 38, count 0 2006.173.11:38:17.66#ibcon#about to write, iclass 38, count 0 2006.173.11:38:17.66#ibcon#wrote, iclass 38, count 0 2006.173.11:38:17.67#ibcon#about to read 3, iclass 38, count 0 2006.173.11:38:17.68#ibcon#read 3, iclass 38, count 0 2006.173.11:38:17.68#ibcon#about to read 4, iclass 38, count 0 2006.173.11:38:17.68#ibcon#read 4, iclass 38, count 0 2006.173.11:38:17.68#ibcon#about to read 5, iclass 38, count 0 2006.173.11:38:17.68#ibcon#read 5, iclass 38, count 0 2006.173.11:38:17.68#ibcon#about to read 6, iclass 38, count 0 2006.173.11:38:17.68#ibcon#read 6, iclass 38, count 0 2006.173.11:38:17.68#ibcon#end of sib2, iclass 38, count 0 2006.173.11:38:17.69#ibcon#*mode == 0, iclass 38, count 0 2006.173.11:38:17.69#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.11:38:17.69#ibcon#[27=BW32\r\n] 2006.173.11:38:17.69#ibcon#*before write, iclass 38, count 0 2006.173.11:38:17.69#ibcon#enter sib2, iclass 38, count 0 2006.173.11:38:17.69#ibcon#flushed, iclass 38, count 0 2006.173.11:38:17.69#ibcon#about to write, iclass 38, count 0 2006.173.11:38:17.69#ibcon#wrote, iclass 38, count 0 2006.173.11:38:17.69#ibcon#about to read 3, iclass 38, count 0 2006.173.11:38:17.71#ibcon#read 3, iclass 38, count 0 2006.173.11:38:17.71#ibcon#about to read 4, iclass 38, count 0 2006.173.11:38:17.71#ibcon#read 4, iclass 38, count 0 2006.173.11:38:17.71#ibcon#about to read 5, iclass 38, count 0 2006.173.11:38:17.71#ibcon#read 5, iclass 38, count 0 2006.173.11:38:17.71#ibcon#about to read 6, iclass 38, count 0 2006.173.11:38:17.71#ibcon#read 6, iclass 38, count 0 2006.173.11:38:17.71#ibcon#end of sib2, iclass 38, count 0 2006.173.11:38:17.71#ibcon#*after write, iclass 38, count 0 2006.173.11:38:17.71#ibcon#*before return 0, iclass 38, count 0 2006.173.11:38:17.71#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.11:38:17.72#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.11:38:17.72#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.11:38:17.72#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.11:38:17.72$setupk4/ifdk4 2006.173.11:38:17.72$ifdk4/lo= 2006.173.11:38:17.72$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.11:38:17.72$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.11:38:17.72$ifdk4/patch= 2006.173.11:38:17.72$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.11:38:17.72$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.11:38:17.72$setupk4/!*+20s 2006.173.11:38:23.93#abcon#<5=/03 0.8 1.7 22.34 931004.4\r\n> 2006.173.11:38:23.95#abcon#{5=INTERFACE CLEAR} 2006.173.11:38:24.01#abcon#[5=S1D000X0/0*\r\n] 2006.173.11:38:32.26$setupk4/"tpicd 2006.173.11:38:32.26$setupk4/echo=off 2006.173.11:38:32.27$setupk4/xlog=off 2006.173.11:38:32.27:!2006.173.11:39:49 2006.173.11:38:52.14#trakl#Source acquired 2006.173.11:38:52.15#flagr#flagr/antenna,acquired 2006.173.11:39:49.02:preob 2006.173.11:39:50.14/onsource/TRACKING 2006.173.11:39:50.14:!2006.173.11:39:59 2006.173.11:39:59.02:"tape 2006.173.11:39:59.02:"st=record 2006.173.11:39:59.02:data_valid=on 2006.173.11:39:59.02:midob 2006.173.11:40:00.14/onsource/TRACKING 2006.173.11:40:00.14/wx/22.31,1004.5,94 2006.173.11:40:00.24/cable/+6.5055E-03 2006.173.11:40:01.33/va/01,07,usb,yes,38,41 2006.173.11:40:01.33/va/02,06,usb,yes,38,39 2006.173.11:40:01.33/va/03,05,usb,yes,48,50 2006.173.11:40:01.33/va/04,06,usb,yes,38,41 2006.173.11:40:01.33/va/05,04,usb,yes,30,31 2006.173.11:40:01.33/va/06,03,usb,yes,42,42 2006.173.11:40:01.33/va/07,04,usb,yes,34,35 2006.173.11:40:01.33/va/08,04,usb,yes,29,35 2006.173.11:40:01.56/valo/01,524.99,yes,locked 2006.173.11:40:01.56/valo/02,534.99,yes,locked 2006.173.11:40:01.56/valo/03,564.99,yes,locked 2006.173.11:40:01.56/valo/04,624.99,yes,locked 2006.173.11:40:01.56/valo/05,734.99,yes,locked 2006.173.11:40:01.56/valo/06,814.99,yes,locked 2006.173.11:40:01.56/valo/07,864.99,yes,locked 2006.173.11:40:01.56/valo/08,884.99,yes,locked 2006.173.11:40:02.65/vb/01,04,usb,yes,36,34 2006.173.11:40:02.65/vb/02,04,usb,yes,39,39 2006.173.11:40:02.65/vb/03,04,usb,yes,35,39 2006.173.11:40:02.65/vb/04,04,usb,yes,40,39 2006.173.11:40:02.65/vb/05,04,usb,yes,32,35 2006.173.11:40:02.65/vb/06,04,usb,yes,37,32 2006.173.11:40:02.65/vb/07,04,usb,yes,36,36 2006.173.11:40:02.65/vb/08,04,usb,yes,33,37 2006.173.11:40:02.89/vblo/01,629.99,yes,locked 2006.173.11:40:02.89/vblo/02,634.99,yes,locked 2006.173.11:40:02.89/vblo/03,649.99,yes,locked 2006.173.11:40:02.89/vblo/04,679.99,yes,locked 2006.173.11:40:02.89/vblo/05,709.99,yes,locked 2006.173.11:40:02.89/vblo/06,719.99,yes,locked 2006.173.11:40:02.89/vblo/07,734.99,yes,locked 2006.173.11:40:02.89/vblo/08,744.99,yes,locked 2006.173.11:40:03.04/vabw/8 2006.173.11:40:03.19/vbbw/8 2006.173.11:40:03.28/xfe/off,on,14.7 2006.173.11:40:03.65/ifatt/23,28,28,28 2006.173.11:40:04.07/fmout-gps/S +3.97E-07 2006.173.11:40:04.12:!2006.173.11:41:29 2006.173.11:41:29.01:data_valid=off 2006.173.11:41:29.02:"et 2006.173.11:41:29.02:!+3s 2006.173.11:41:32.05:"tape 2006.173.11:41:32.06:postob 2006.173.11:41:32.25/cable/+6.5039E-03 2006.173.11:41:32.26/wx/22.27,1004.5,94 2006.173.11:41:32.31/fmout-gps/S +3.96E-07 2006.173.11:41:32.32:scan_name=173-1144,jd0606,280 2006.173.11:41:32.32:source=2201+315,220314.98,314538.3,2000.0,cw 2006.173.11:41:33.14#flagr#flagr/antenna,new-source 2006.173.11:41:33.15:checkk5 2006.173.11:41:33.56/chk_autoobs//k5ts1/ autoobs is running! 2006.173.11:41:34.00/chk_autoobs//k5ts2/ autoobs is running! 2006.173.11:41:34.41/chk_autoobs//k5ts3/ autoobs is running! 2006.173.11:41:34.81/chk_autoobs//k5ts4/ autoobs is running! 2006.173.11:41:35.22/chk_obsdata//k5ts1/T1731139??a.dat file size is correct (nominal:360MB, actual:356MB). 2006.173.11:41:35.62/chk_obsdata//k5ts2/T1731139??b.dat file size is correct (nominal:360MB, actual:356MB). 2006.173.11:41:36.03/chk_obsdata//k5ts3/T1731139??c.dat file size is correct (nominal:360MB, actual:356MB). 2006.173.11:41:36.44/chk_obsdata//k5ts4/T1731139??d.dat file size is correct (nominal:360MB, actual:356MB). 2006.173.11:41:37.17/k5log//k5ts1_log_newline 2006.173.11:41:37.90/k5log//k5ts2_log_newline 2006.173.11:41:38.63/k5log//k5ts3_log_newline 2006.173.11:41:39.35/k5log//k5ts4_log_newline 2006.173.11:41:39.38/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.11:41:39.38:setupk4=1 2006.173.11:41:39.38$setupk4/echo=on 2006.173.11:41:39.38$setupk4/pcalon 2006.173.11:41:39.38$pcalon/"no phase cal control is implemented here 2006.173.11:41:39.38$setupk4/"tpicd=stop 2006.173.11:41:39.38$setupk4/"rec=synch_on 2006.173.11:41:39.38$setupk4/"rec_mode=128 2006.173.11:41:39.38$setupk4/!* 2006.173.11:41:39.38$setupk4/recpk4 2006.173.11:41:39.38$recpk4/recpatch= 2006.173.11:41:39.39$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.11:41:39.39$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.11:41:39.39$setupk4/vck44 2006.173.11:41:39.39$vck44/valo=1,524.99 2006.173.11:41:39.39#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.11:41:39.39#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.11:41:39.39#ibcon#ireg 17 cls_cnt 0 2006.173.11:41:39.39#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.11:41:39.39#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.11:41:39.39#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.11:41:39.39#ibcon#enter wrdev, iclass 15, count 0 2006.173.11:41:39.39#ibcon#first serial, iclass 15, count 0 2006.173.11:41:39.39#ibcon#enter sib2, iclass 15, count 0 2006.173.11:41:39.39#ibcon#flushed, iclass 15, count 0 2006.173.11:41:39.39#ibcon#about to write, iclass 15, count 0 2006.173.11:41:39.39#ibcon#wrote, iclass 15, count 0 2006.173.11:41:39.39#ibcon#about to read 3, iclass 15, count 0 2006.173.11:41:39.40#ibcon#read 3, iclass 15, count 0 2006.173.11:41:39.40#ibcon#about to read 4, iclass 15, count 0 2006.173.11:41:39.40#ibcon#read 4, iclass 15, count 0 2006.173.11:41:39.40#ibcon#about to read 5, iclass 15, count 0 2006.173.11:41:39.40#ibcon#read 5, iclass 15, count 0 2006.173.11:41:39.40#ibcon#about to read 6, iclass 15, count 0 2006.173.11:41:39.40#ibcon#read 6, iclass 15, count 0 2006.173.11:41:39.40#ibcon#end of sib2, iclass 15, count 0 2006.173.11:41:39.40#ibcon#*mode == 0, iclass 15, count 0 2006.173.11:41:39.40#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.11:41:39.40#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.11:41:39.40#ibcon#*before write, iclass 15, count 0 2006.173.11:41:39.40#ibcon#enter sib2, iclass 15, count 0 2006.173.11:41:39.40#ibcon#flushed, iclass 15, count 0 2006.173.11:41:39.40#ibcon#about to write, iclass 15, count 0 2006.173.11:41:39.40#ibcon#wrote, iclass 15, count 0 2006.173.11:41:39.40#ibcon#about to read 3, iclass 15, count 0 2006.173.11:41:39.45#ibcon#read 3, iclass 15, count 0 2006.173.11:41:39.45#ibcon#about to read 4, iclass 15, count 0 2006.173.11:41:39.45#ibcon#read 4, iclass 15, count 0 2006.173.11:41:39.45#ibcon#about to read 5, iclass 15, count 0 2006.173.11:41:39.45#ibcon#read 5, iclass 15, count 0 2006.173.11:41:39.45#ibcon#about to read 6, iclass 15, count 0 2006.173.11:41:39.45#ibcon#read 6, iclass 15, count 0 2006.173.11:41:39.45#ibcon#end of sib2, iclass 15, count 0 2006.173.11:41:39.45#ibcon#*after write, iclass 15, count 0 2006.173.11:41:39.45#ibcon#*before return 0, iclass 15, count 0 2006.173.11:41:39.45#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.11:41:39.45#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.11:41:39.45#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.11:41:39.45#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.11:41:39.45$vck44/va=1,7 2006.173.11:41:39.45#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.11:41:39.45#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.11:41:39.45#ibcon#ireg 11 cls_cnt 2 2006.173.11:41:39.45#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.11:41:39.45#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.11:41:39.45#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.11:41:39.45#ibcon#enter wrdev, iclass 17, count 2 2006.173.11:41:39.45#ibcon#first serial, iclass 17, count 2 2006.173.11:41:39.45#ibcon#enter sib2, iclass 17, count 2 2006.173.11:41:39.45#ibcon#flushed, iclass 17, count 2 2006.173.11:41:39.45#ibcon#about to write, iclass 17, count 2 2006.173.11:41:39.45#ibcon#wrote, iclass 17, count 2 2006.173.11:41:39.45#ibcon#about to read 3, iclass 17, count 2 2006.173.11:41:39.47#ibcon#read 3, iclass 17, count 2 2006.173.11:41:39.47#ibcon#about to read 4, iclass 17, count 2 2006.173.11:41:39.47#ibcon#read 4, iclass 17, count 2 2006.173.11:41:39.47#ibcon#about to read 5, iclass 17, count 2 2006.173.11:41:39.47#ibcon#read 5, iclass 17, count 2 2006.173.11:41:39.47#ibcon#about to read 6, iclass 17, count 2 2006.173.11:41:39.47#ibcon#read 6, iclass 17, count 2 2006.173.11:41:39.47#ibcon#end of sib2, iclass 17, count 2 2006.173.11:41:39.47#ibcon#*mode == 0, iclass 17, count 2 2006.173.11:41:39.47#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.11:41:39.47#ibcon#[25=AT01-07\r\n] 2006.173.11:41:39.47#ibcon#*before write, iclass 17, count 2 2006.173.11:41:39.47#ibcon#enter sib2, iclass 17, count 2 2006.173.11:41:39.47#ibcon#flushed, iclass 17, count 2 2006.173.11:41:39.47#ibcon#about to write, iclass 17, count 2 2006.173.11:41:39.47#ibcon#wrote, iclass 17, count 2 2006.173.11:41:39.47#ibcon#about to read 3, iclass 17, count 2 2006.173.11:41:39.50#ibcon#read 3, iclass 17, count 2 2006.173.11:41:39.50#ibcon#about to read 4, iclass 17, count 2 2006.173.11:41:39.50#ibcon#read 4, iclass 17, count 2 2006.173.11:41:39.50#ibcon#about to read 5, iclass 17, count 2 2006.173.11:41:39.50#ibcon#read 5, iclass 17, count 2 2006.173.11:41:39.50#ibcon#about to read 6, iclass 17, count 2 2006.173.11:41:39.50#ibcon#read 6, iclass 17, count 2 2006.173.11:41:39.50#ibcon#end of sib2, iclass 17, count 2 2006.173.11:41:39.50#ibcon#*after write, iclass 17, count 2 2006.173.11:41:39.50#ibcon#*before return 0, iclass 17, count 2 2006.173.11:41:39.50#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.11:41:39.50#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.11:41:39.50#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.11:41:39.50#ibcon#ireg 7 cls_cnt 0 2006.173.11:41:39.50#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.11:41:39.62#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.11:41:39.62#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.11:41:39.62#ibcon#enter wrdev, iclass 17, count 0 2006.173.11:41:39.62#ibcon#first serial, iclass 17, count 0 2006.173.11:41:39.62#ibcon#enter sib2, iclass 17, count 0 2006.173.11:41:39.62#ibcon#flushed, iclass 17, count 0 2006.173.11:41:39.62#ibcon#about to write, iclass 17, count 0 2006.173.11:41:39.62#ibcon#wrote, iclass 17, count 0 2006.173.11:41:39.62#ibcon#about to read 3, iclass 17, count 0 2006.173.11:41:39.64#ibcon#read 3, iclass 17, count 0 2006.173.11:41:39.64#ibcon#about to read 4, iclass 17, count 0 2006.173.11:41:39.64#ibcon#read 4, iclass 17, count 0 2006.173.11:41:39.64#ibcon#about to read 5, iclass 17, count 0 2006.173.11:41:39.64#ibcon#read 5, iclass 17, count 0 2006.173.11:41:39.64#ibcon#about to read 6, iclass 17, count 0 2006.173.11:41:39.64#ibcon#read 6, iclass 17, count 0 2006.173.11:41:39.64#ibcon#end of sib2, iclass 17, count 0 2006.173.11:41:39.64#ibcon#*mode == 0, iclass 17, count 0 2006.173.11:41:39.64#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.11:41:39.64#ibcon#[25=USB\r\n] 2006.173.11:41:39.64#ibcon#*before write, iclass 17, count 0 2006.173.11:41:39.64#ibcon#enter sib2, iclass 17, count 0 2006.173.11:41:39.64#ibcon#flushed, iclass 17, count 0 2006.173.11:41:39.64#ibcon#about to write, iclass 17, count 0 2006.173.11:41:39.64#ibcon#wrote, iclass 17, count 0 2006.173.11:41:39.64#ibcon#about to read 3, iclass 17, count 0 2006.173.11:41:39.67#ibcon#read 3, iclass 17, count 0 2006.173.11:41:39.67#ibcon#about to read 4, iclass 17, count 0 2006.173.11:41:39.67#ibcon#read 4, iclass 17, count 0 2006.173.11:41:39.67#ibcon#about to read 5, iclass 17, count 0 2006.173.11:41:39.67#ibcon#read 5, iclass 17, count 0 2006.173.11:41:39.67#ibcon#about to read 6, iclass 17, count 0 2006.173.11:41:39.67#ibcon#read 6, iclass 17, count 0 2006.173.11:41:39.67#ibcon#end of sib2, iclass 17, count 0 2006.173.11:41:39.67#ibcon#*after write, iclass 17, count 0 2006.173.11:41:39.67#ibcon#*before return 0, iclass 17, count 0 2006.173.11:41:39.67#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.11:41:39.67#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.11:41:39.67#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.11:41:39.67#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.11:41:39.67$vck44/valo=2,534.99 2006.173.11:41:39.67#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.11:41:39.67#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.11:41:39.67#ibcon#ireg 17 cls_cnt 0 2006.173.11:41:39.67#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.11:41:39.67#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.11:41:39.67#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.11:41:39.67#ibcon#enter wrdev, iclass 19, count 0 2006.173.11:41:39.67#ibcon#first serial, iclass 19, count 0 2006.173.11:41:39.67#ibcon#enter sib2, iclass 19, count 0 2006.173.11:41:39.67#ibcon#flushed, iclass 19, count 0 2006.173.11:41:39.67#ibcon#about to write, iclass 19, count 0 2006.173.11:41:39.67#ibcon#wrote, iclass 19, count 0 2006.173.11:41:39.67#ibcon#about to read 3, iclass 19, count 0 2006.173.11:41:39.69#ibcon#read 3, iclass 19, count 0 2006.173.11:41:39.69#ibcon#about to read 4, iclass 19, count 0 2006.173.11:41:39.69#ibcon#read 4, iclass 19, count 0 2006.173.11:41:39.69#ibcon#about to read 5, iclass 19, count 0 2006.173.11:41:39.69#ibcon#read 5, iclass 19, count 0 2006.173.11:41:39.69#ibcon#about to read 6, iclass 19, count 0 2006.173.11:41:39.69#ibcon#read 6, iclass 19, count 0 2006.173.11:41:39.69#ibcon#end of sib2, iclass 19, count 0 2006.173.11:41:39.69#ibcon#*mode == 0, iclass 19, count 0 2006.173.11:41:39.69#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.11:41:39.69#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.11:41:39.69#ibcon#*before write, iclass 19, count 0 2006.173.11:41:39.69#ibcon#enter sib2, iclass 19, count 0 2006.173.11:41:39.69#ibcon#flushed, iclass 19, count 0 2006.173.11:41:39.69#ibcon#about to write, iclass 19, count 0 2006.173.11:41:39.69#ibcon#wrote, iclass 19, count 0 2006.173.11:41:39.69#ibcon#about to read 3, iclass 19, count 0 2006.173.11:41:39.73#ibcon#read 3, iclass 19, count 0 2006.173.11:41:39.73#ibcon#about to read 4, iclass 19, count 0 2006.173.11:41:39.73#ibcon#read 4, iclass 19, count 0 2006.173.11:41:39.73#ibcon#about to read 5, iclass 19, count 0 2006.173.11:41:39.73#ibcon#read 5, iclass 19, count 0 2006.173.11:41:39.73#ibcon#about to read 6, iclass 19, count 0 2006.173.11:41:39.73#ibcon#read 6, iclass 19, count 0 2006.173.11:41:39.73#ibcon#end of sib2, iclass 19, count 0 2006.173.11:41:39.73#ibcon#*after write, iclass 19, count 0 2006.173.11:41:39.73#ibcon#*before return 0, iclass 19, count 0 2006.173.11:41:39.73#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.11:41:39.73#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.11:41:39.73#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.11:41:39.73#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.11:41:39.73$vck44/va=2,6 2006.173.11:41:39.73#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.11:41:39.73#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.11:41:39.73#ibcon#ireg 11 cls_cnt 2 2006.173.11:41:39.73#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.11:41:39.79#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.11:41:39.79#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.11:41:39.79#ibcon#enter wrdev, iclass 21, count 2 2006.173.11:41:39.79#ibcon#first serial, iclass 21, count 2 2006.173.11:41:39.79#ibcon#enter sib2, iclass 21, count 2 2006.173.11:41:39.79#ibcon#flushed, iclass 21, count 2 2006.173.11:41:39.79#ibcon#about to write, iclass 21, count 2 2006.173.11:41:39.79#ibcon#wrote, iclass 21, count 2 2006.173.11:41:39.79#ibcon#about to read 3, iclass 21, count 2 2006.173.11:41:39.81#ibcon#read 3, iclass 21, count 2 2006.173.11:41:39.81#ibcon#about to read 4, iclass 21, count 2 2006.173.11:41:39.81#ibcon#read 4, iclass 21, count 2 2006.173.11:41:39.81#ibcon#about to read 5, iclass 21, count 2 2006.173.11:41:39.81#ibcon#read 5, iclass 21, count 2 2006.173.11:41:39.81#ibcon#about to read 6, iclass 21, count 2 2006.173.11:41:39.81#ibcon#read 6, iclass 21, count 2 2006.173.11:41:39.81#ibcon#end of sib2, iclass 21, count 2 2006.173.11:41:39.81#ibcon#*mode == 0, iclass 21, count 2 2006.173.11:41:39.81#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.11:41:39.81#ibcon#[25=AT02-06\r\n] 2006.173.11:41:39.81#ibcon#*before write, iclass 21, count 2 2006.173.11:41:39.81#ibcon#enter sib2, iclass 21, count 2 2006.173.11:41:39.81#ibcon#flushed, iclass 21, count 2 2006.173.11:41:39.81#ibcon#about to write, iclass 21, count 2 2006.173.11:41:39.81#ibcon#wrote, iclass 21, count 2 2006.173.11:41:39.81#ibcon#about to read 3, iclass 21, count 2 2006.173.11:41:39.84#ibcon#read 3, iclass 21, count 2 2006.173.11:41:39.84#ibcon#about to read 4, iclass 21, count 2 2006.173.11:41:39.84#ibcon#read 4, iclass 21, count 2 2006.173.11:41:39.84#ibcon#about to read 5, iclass 21, count 2 2006.173.11:41:39.84#ibcon#read 5, iclass 21, count 2 2006.173.11:41:39.84#ibcon#about to read 6, iclass 21, count 2 2006.173.11:41:39.84#ibcon#read 6, iclass 21, count 2 2006.173.11:41:39.84#ibcon#end of sib2, iclass 21, count 2 2006.173.11:41:39.84#ibcon#*after write, iclass 21, count 2 2006.173.11:41:39.84#ibcon#*before return 0, iclass 21, count 2 2006.173.11:41:39.84#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.11:41:39.84#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.11:41:39.84#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.11:41:39.84#ibcon#ireg 7 cls_cnt 0 2006.173.11:41:39.84#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.11:41:39.96#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.11:41:39.96#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.11:41:39.96#ibcon#enter wrdev, iclass 21, count 0 2006.173.11:41:39.96#ibcon#first serial, iclass 21, count 0 2006.173.11:41:39.96#ibcon#enter sib2, iclass 21, count 0 2006.173.11:41:39.96#ibcon#flushed, iclass 21, count 0 2006.173.11:41:39.96#ibcon#about to write, iclass 21, count 0 2006.173.11:41:39.96#ibcon#wrote, iclass 21, count 0 2006.173.11:41:39.96#ibcon#about to read 3, iclass 21, count 0 2006.173.11:41:39.98#ibcon#read 3, iclass 21, count 0 2006.173.11:41:39.98#ibcon#about to read 4, iclass 21, count 0 2006.173.11:41:39.98#ibcon#read 4, iclass 21, count 0 2006.173.11:41:39.98#ibcon#about to read 5, iclass 21, count 0 2006.173.11:41:39.98#ibcon#read 5, iclass 21, count 0 2006.173.11:41:39.98#ibcon#about to read 6, iclass 21, count 0 2006.173.11:41:39.98#ibcon#read 6, iclass 21, count 0 2006.173.11:41:39.98#ibcon#end of sib2, iclass 21, count 0 2006.173.11:41:39.98#ibcon#*mode == 0, iclass 21, count 0 2006.173.11:41:39.98#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.11:41:39.98#ibcon#[25=USB\r\n] 2006.173.11:41:39.98#ibcon#*before write, iclass 21, count 0 2006.173.11:41:39.98#ibcon#enter sib2, iclass 21, count 0 2006.173.11:41:39.98#ibcon#flushed, iclass 21, count 0 2006.173.11:41:39.98#ibcon#about to write, iclass 21, count 0 2006.173.11:41:39.98#ibcon#wrote, iclass 21, count 0 2006.173.11:41:39.98#ibcon#about to read 3, iclass 21, count 0 2006.173.11:41:40.01#ibcon#read 3, iclass 21, count 0 2006.173.11:41:40.01#ibcon#about to read 4, iclass 21, count 0 2006.173.11:41:40.01#ibcon#read 4, iclass 21, count 0 2006.173.11:41:40.01#ibcon#about to read 5, iclass 21, count 0 2006.173.11:41:40.01#ibcon#read 5, iclass 21, count 0 2006.173.11:41:40.01#ibcon#about to read 6, iclass 21, count 0 2006.173.11:41:40.01#ibcon#read 6, iclass 21, count 0 2006.173.11:41:40.01#ibcon#end of sib2, iclass 21, count 0 2006.173.11:41:40.01#ibcon#*after write, iclass 21, count 0 2006.173.11:41:40.01#ibcon#*before return 0, iclass 21, count 0 2006.173.11:41:40.01#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.11:41:40.01#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.11:41:40.01#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.11:41:40.01#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.11:41:40.01$vck44/valo=3,564.99 2006.173.11:41:40.01#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.11:41:40.01#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.11:41:40.01#ibcon#ireg 17 cls_cnt 0 2006.173.11:41:40.01#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.11:41:40.01#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.11:41:40.01#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.11:41:40.01#ibcon#enter wrdev, iclass 23, count 0 2006.173.11:41:40.01#ibcon#first serial, iclass 23, count 0 2006.173.11:41:40.01#ibcon#enter sib2, iclass 23, count 0 2006.173.11:41:40.01#ibcon#flushed, iclass 23, count 0 2006.173.11:41:40.01#ibcon#about to write, iclass 23, count 0 2006.173.11:41:40.01#ibcon#wrote, iclass 23, count 0 2006.173.11:41:40.01#ibcon#about to read 3, iclass 23, count 0 2006.173.11:41:40.03#ibcon#read 3, iclass 23, count 0 2006.173.11:41:40.03#ibcon#about to read 4, iclass 23, count 0 2006.173.11:41:40.03#ibcon#read 4, iclass 23, count 0 2006.173.11:41:40.03#ibcon#about to read 5, iclass 23, count 0 2006.173.11:41:40.03#ibcon#read 5, iclass 23, count 0 2006.173.11:41:40.03#ibcon#about to read 6, iclass 23, count 0 2006.173.11:41:40.03#ibcon#read 6, iclass 23, count 0 2006.173.11:41:40.03#ibcon#end of sib2, iclass 23, count 0 2006.173.11:41:40.03#ibcon#*mode == 0, iclass 23, count 0 2006.173.11:41:40.03#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.11:41:40.03#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.11:41:40.03#ibcon#*before write, iclass 23, count 0 2006.173.11:41:40.03#ibcon#enter sib2, iclass 23, count 0 2006.173.11:41:40.03#ibcon#flushed, iclass 23, count 0 2006.173.11:41:40.03#ibcon#about to write, iclass 23, count 0 2006.173.11:41:40.03#ibcon#wrote, iclass 23, count 0 2006.173.11:41:40.03#ibcon#about to read 3, iclass 23, count 0 2006.173.11:41:40.07#ibcon#read 3, iclass 23, count 0 2006.173.11:41:40.07#ibcon#about to read 4, iclass 23, count 0 2006.173.11:41:40.07#ibcon#read 4, iclass 23, count 0 2006.173.11:41:40.07#ibcon#about to read 5, iclass 23, count 0 2006.173.11:41:40.07#ibcon#read 5, iclass 23, count 0 2006.173.11:41:40.07#ibcon#about to read 6, iclass 23, count 0 2006.173.11:41:40.07#ibcon#read 6, iclass 23, count 0 2006.173.11:41:40.07#ibcon#end of sib2, iclass 23, count 0 2006.173.11:41:40.07#ibcon#*after write, iclass 23, count 0 2006.173.11:41:40.07#ibcon#*before return 0, iclass 23, count 0 2006.173.11:41:40.07#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.11:41:40.07#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.11:41:40.07#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.11:41:40.07#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.11:41:40.07$vck44/va=3,5 2006.173.11:41:40.07#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.11:41:40.07#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.11:41:40.07#ibcon#ireg 11 cls_cnt 2 2006.173.11:41:40.07#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.11:41:40.13#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.11:41:40.13#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.11:41:40.13#ibcon#enter wrdev, iclass 25, count 2 2006.173.11:41:40.13#ibcon#first serial, iclass 25, count 2 2006.173.11:41:40.13#ibcon#enter sib2, iclass 25, count 2 2006.173.11:41:40.13#ibcon#flushed, iclass 25, count 2 2006.173.11:41:40.13#ibcon#about to write, iclass 25, count 2 2006.173.11:41:40.13#ibcon#wrote, iclass 25, count 2 2006.173.11:41:40.13#ibcon#about to read 3, iclass 25, count 2 2006.173.11:41:40.15#ibcon#read 3, iclass 25, count 2 2006.173.11:41:40.15#ibcon#about to read 4, iclass 25, count 2 2006.173.11:41:40.15#ibcon#read 4, iclass 25, count 2 2006.173.11:41:40.15#ibcon#about to read 5, iclass 25, count 2 2006.173.11:41:40.15#ibcon#read 5, iclass 25, count 2 2006.173.11:41:40.15#ibcon#about to read 6, iclass 25, count 2 2006.173.11:41:40.15#ibcon#read 6, iclass 25, count 2 2006.173.11:41:40.15#ibcon#end of sib2, iclass 25, count 2 2006.173.11:41:40.15#ibcon#*mode == 0, iclass 25, count 2 2006.173.11:41:40.15#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.11:41:40.15#ibcon#[25=AT03-05\r\n] 2006.173.11:41:40.15#ibcon#*before write, iclass 25, count 2 2006.173.11:41:40.15#ibcon#enter sib2, iclass 25, count 2 2006.173.11:41:40.15#ibcon#flushed, iclass 25, count 2 2006.173.11:41:40.15#ibcon#about to write, iclass 25, count 2 2006.173.11:41:40.15#ibcon#wrote, iclass 25, count 2 2006.173.11:41:40.15#ibcon#about to read 3, iclass 25, count 2 2006.173.11:41:40.18#ibcon#read 3, iclass 25, count 2 2006.173.11:41:40.18#ibcon#about to read 4, iclass 25, count 2 2006.173.11:41:40.18#ibcon#read 4, iclass 25, count 2 2006.173.11:41:40.18#ibcon#about to read 5, iclass 25, count 2 2006.173.11:41:40.18#ibcon#read 5, iclass 25, count 2 2006.173.11:41:40.18#ibcon#about to read 6, iclass 25, count 2 2006.173.11:41:40.18#ibcon#read 6, iclass 25, count 2 2006.173.11:41:40.18#ibcon#end of sib2, iclass 25, count 2 2006.173.11:41:40.18#ibcon#*after write, iclass 25, count 2 2006.173.11:41:40.18#ibcon#*before return 0, iclass 25, count 2 2006.173.11:41:40.18#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.11:41:40.18#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.11:41:40.18#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.11:41:40.18#ibcon#ireg 7 cls_cnt 0 2006.173.11:41:40.18#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.11:41:40.30#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.11:41:40.30#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.11:41:40.30#ibcon#enter wrdev, iclass 25, count 0 2006.173.11:41:40.30#ibcon#first serial, iclass 25, count 0 2006.173.11:41:40.30#ibcon#enter sib2, iclass 25, count 0 2006.173.11:41:40.30#ibcon#flushed, iclass 25, count 0 2006.173.11:41:40.30#ibcon#about to write, iclass 25, count 0 2006.173.11:41:40.30#ibcon#wrote, iclass 25, count 0 2006.173.11:41:40.30#ibcon#about to read 3, iclass 25, count 0 2006.173.11:41:40.32#ibcon#read 3, iclass 25, count 0 2006.173.11:41:40.32#ibcon#about to read 4, iclass 25, count 0 2006.173.11:41:40.32#ibcon#read 4, iclass 25, count 0 2006.173.11:41:40.32#ibcon#about to read 5, iclass 25, count 0 2006.173.11:41:40.32#ibcon#read 5, iclass 25, count 0 2006.173.11:41:40.32#ibcon#about to read 6, iclass 25, count 0 2006.173.11:41:40.32#ibcon#read 6, iclass 25, count 0 2006.173.11:41:40.32#ibcon#end of sib2, iclass 25, count 0 2006.173.11:41:40.32#ibcon#*mode == 0, iclass 25, count 0 2006.173.11:41:40.32#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.11:41:40.32#ibcon#[25=USB\r\n] 2006.173.11:41:40.32#ibcon#*before write, iclass 25, count 0 2006.173.11:41:40.32#ibcon#enter sib2, iclass 25, count 0 2006.173.11:41:40.32#ibcon#flushed, iclass 25, count 0 2006.173.11:41:40.32#ibcon#about to write, iclass 25, count 0 2006.173.11:41:40.32#ibcon#wrote, iclass 25, count 0 2006.173.11:41:40.32#ibcon#about to read 3, iclass 25, count 0 2006.173.11:41:40.35#ibcon#read 3, iclass 25, count 0 2006.173.11:41:40.35#ibcon#about to read 4, iclass 25, count 0 2006.173.11:41:40.35#ibcon#read 4, iclass 25, count 0 2006.173.11:41:40.35#ibcon#about to read 5, iclass 25, count 0 2006.173.11:41:40.35#ibcon#read 5, iclass 25, count 0 2006.173.11:41:40.35#ibcon#about to read 6, iclass 25, count 0 2006.173.11:41:40.35#ibcon#read 6, iclass 25, count 0 2006.173.11:41:40.35#ibcon#end of sib2, iclass 25, count 0 2006.173.11:41:40.35#ibcon#*after write, iclass 25, count 0 2006.173.11:41:40.35#ibcon#*before return 0, iclass 25, count 0 2006.173.11:41:40.35#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.11:41:40.35#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.11:41:40.35#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.11:41:40.35#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.11:41:40.35$vck44/valo=4,624.99 2006.173.11:41:40.35#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.11:41:40.35#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.11:41:40.35#ibcon#ireg 17 cls_cnt 0 2006.173.11:41:40.35#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.11:41:40.35#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.11:41:40.35#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.11:41:40.35#ibcon#enter wrdev, iclass 27, count 0 2006.173.11:41:40.35#ibcon#first serial, iclass 27, count 0 2006.173.11:41:40.35#ibcon#enter sib2, iclass 27, count 0 2006.173.11:41:40.35#ibcon#flushed, iclass 27, count 0 2006.173.11:41:40.35#ibcon#about to write, iclass 27, count 0 2006.173.11:41:40.35#ibcon#wrote, iclass 27, count 0 2006.173.11:41:40.35#ibcon#about to read 3, iclass 27, count 0 2006.173.11:41:40.37#ibcon#read 3, iclass 27, count 0 2006.173.11:41:40.37#ibcon#about to read 4, iclass 27, count 0 2006.173.11:41:40.37#ibcon#read 4, iclass 27, count 0 2006.173.11:41:40.37#ibcon#about to read 5, iclass 27, count 0 2006.173.11:41:40.37#ibcon#read 5, iclass 27, count 0 2006.173.11:41:40.37#ibcon#about to read 6, iclass 27, count 0 2006.173.11:41:40.37#ibcon#read 6, iclass 27, count 0 2006.173.11:41:40.37#ibcon#end of sib2, iclass 27, count 0 2006.173.11:41:40.37#ibcon#*mode == 0, iclass 27, count 0 2006.173.11:41:40.37#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.11:41:40.37#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.11:41:40.37#ibcon#*before write, iclass 27, count 0 2006.173.11:41:40.37#ibcon#enter sib2, iclass 27, count 0 2006.173.11:41:40.37#ibcon#flushed, iclass 27, count 0 2006.173.11:41:40.37#ibcon#about to write, iclass 27, count 0 2006.173.11:41:40.37#ibcon#wrote, iclass 27, count 0 2006.173.11:41:40.37#ibcon#about to read 3, iclass 27, count 0 2006.173.11:41:40.41#ibcon#read 3, iclass 27, count 0 2006.173.11:41:40.41#ibcon#about to read 4, iclass 27, count 0 2006.173.11:41:40.41#ibcon#read 4, iclass 27, count 0 2006.173.11:41:40.41#ibcon#about to read 5, iclass 27, count 0 2006.173.11:41:40.41#ibcon#read 5, iclass 27, count 0 2006.173.11:41:40.41#ibcon#about to read 6, iclass 27, count 0 2006.173.11:41:40.41#ibcon#read 6, iclass 27, count 0 2006.173.11:41:40.41#ibcon#end of sib2, iclass 27, count 0 2006.173.11:41:40.41#ibcon#*after write, iclass 27, count 0 2006.173.11:41:40.41#ibcon#*before return 0, iclass 27, count 0 2006.173.11:41:40.41#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.11:41:40.41#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.11:41:40.41#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.11:41:40.41#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.11:41:40.41$vck44/va=4,6 2006.173.11:41:40.41#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.11:41:40.41#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.11:41:40.41#ibcon#ireg 11 cls_cnt 2 2006.173.11:41:40.41#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.11:41:40.47#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.11:41:40.47#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.11:41:40.47#ibcon#enter wrdev, iclass 29, count 2 2006.173.11:41:40.47#ibcon#first serial, iclass 29, count 2 2006.173.11:41:40.47#ibcon#enter sib2, iclass 29, count 2 2006.173.11:41:40.47#ibcon#flushed, iclass 29, count 2 2006.173.11:41:40.47#ibcon#about to write, iclass 29, count 2 2006.173.11:41:40.47#ibcon#wrote, iclass 29, count 2 2006.173.11:41:40.47#ibcon#about to read 3, iclass 29, count 2 2006.173.11:41:40.49#ibcon#read 3, iclass 29, count 2 2006.173.11:41:40.49#ibcon#about to read 4, iclass 29, count 2 2006.173.11:41:40.49#ibcon#read 4, iclass 29, count 2 2006.173.11:41:40.49#ibcon#about to read 5, iclass 29, count 2 2006.173.11:41:40.49#ibcon#read 5, iclass 29, count 2 2006.173.11:41:40.49#ibcon#about to read 6, iclass 29, count 2 2006.173.11:41:40.49#ibcon#read 6, iclass 29, count 2 2006.173.11:41:40.49#ibcon#end of sib2, iclass 29, count 2 2006.173.11:41:40.49#ibcon#*mode == 0, iclass 29, count 2 2006.173.11:41:40.49#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.11:41:40.49#ibcon#[25=AT04-06\r\n] 2006.173.11:41:40.49#ibcon#*before write, iclass 29, count 2 2006.173.11:41:40.49#ibcon#enter sib2, iclass 29, count 2 2006.173.11:41:40.49#ibcon#flushed, iclass 29, count 2 2006.173.11:41:40.49#ibcon#about to write, iclass 29, count 2 2006.173.11:41:40.49#ibcon#wrote, iclass 29, count 2 2006.173.11:41:40.49#ibcon#about to read 3, iclass 29, count 2 2006.173.11:41:40.52#ibcon#read 3, iclass 29, count 2 2006.173.11:41:40.52#ibcon#about to read 4, iclass 29, count 2 2006.173.11:41:40.52#ibcon#read 4, iclass 29, count 2 2006.173.11:41:40.52#ibcon#about to read 5, iclass 29, count 2 2006.173.11:41:40.52#ibcon#read 5, iclass 29, count 2 2006.173.11:41:40.52#ibcon#about to read 6, iclass 29, count 2 2006.173.11:41:40.52#ibcon#read 6, iclass 29, count 2 2006.173.11:41:40.52#ibcon#end of sib2, iclass 29, count 2 2006.173.11:41:40.52#ibcon#*after write, iclass 29, count 2 2006.173.11:41:40.52#ibcon#*before return 0, iclass 29, count 2 2006.173.11:41:40.52#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.11:41:40.52#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.11:41:40.52#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.11:41:40.52#ibcon#ireg 7 cls_cnt 0 2006.173.11:41:40.52#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.11:41:40.64#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.11:41:40.64#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.11:41:40.64#ibcon#enter wrdev, iclass 29, count 0 2006.173.11:41:40.64#ibcon#first serial, iclass 29, count 0 2006.173.11:41:40.64#ibcon#enter sib2, iclass 29, count 0 2006.173.11:41:40.64#ibcon#flushed, iclass 29, count 0 2006.173.11:41:40.64#ibcon#about to write, iclass 29, count 0 2006.173.11:41:40.64#ibcon#wrote, iclass 29, count 0 2006.173.11:41:40.64#ibcon#about to read 3, iclass 29, count 0 2006.173.11:41:40.66#ibcon#read 3, iclass 29, count 0 2006.173.11:41:40.66#ibcon#about to read 4, iclass 29, count 0 2006.173.11:41:40.66#ibcon#read 4, iclass 29, count 0 2006.173.11:41:40.66#ibcon#about to read 5, iclass 29, count 0 2006.173.11:41:40.66#ibcon#read 5, iclass 29, count 0 2006.173.11:41:40.66#ibcon#about to read 6, iclass 29, count 0 2006.173.11:41:40.66#ibcon#read 6, iclass 29, count 0 2006.173.11:41:40.66#ibcon#end of sib2, iclass 29, count 0 2006.173.11:41:40.66#ibcon#*mode == 0, iclass 29, count 0 2006.173.11:41:40.66#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.11:41:40.66#ibcon#[25=USB\r\n] 2006.173.11:41:40.66#ibcon#*before write, iclass 29, count 0 2006.173.11:41:40.66#ibcon#enter sib2, iclass 29, count 0 2006.173.11:41:40.66#ibcon#flushed, iclass 29, count 0 2006.173.11:41:40.66#ibcon#about to write, iclass 29, count 0 2006.173.11:41:40.66#ibcon#wrote, iclass 29, count 0 2006.173.11:41:40.66#ibcon#about to read 3, iclass 29, count 0 2006.173.11:41:40.69#ibcon#read 3, iclass 29, count 0 2006.173.11:41:40.69#ibcon#about to read 4, iclass 29, count 0 2006.173.11:41:40.69#ibcon#read 4, iclass 29, count 0 2006.173.11:41:40.69#ibcon#about to read 5, iclass 29, count 0 2006.173.11:41:40.69#ibcon#read 5, iclass 29, count 0 2006.173.11:41:40.69#ibcon#about to read 6, iclass 29, count 0 2006.173.11:41:40.69#ibcon#read 6, iclass 29, count 0 2006.173.11:41:40.69#ibcon#end of sib2, iclass 29, count 0 2006.173.11:41:40.69#ibcon#*after write, iclass 29, count 0 2006.173.11:41:40.69#ibcon#*before return 0, iclass 29, count 0 2006.173.11:41:40.69#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.11:41:40.69#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.11:41:40.69#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.11:41:40.69#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.11:41:40.69$vck44/valo=5,734.99 2006.173.11:41:40.69#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.11:41:40.69#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.11:41:40.69#ibcon#ireg 17 cls_cnt 0 2006.173.11:41:40.69#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.11:41:40.69#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.11:41:40.69#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.11:41:40.69#ibcon#enter wrdev, iclass 31, count 0 2006.173.11:41:40.69#ibcon#first serial, iclass 31, count 0 2006.173.11:41:40.69#ibcon#enter sib2, iclass 31, count 0 2006.173.11:41:40.69#ibcon#flushed, iclass 31, count 0 2006.173.11:41:40.69#ibcon#about to write, iclass 31, count 0 2006.173.11:41:40.69#ibcon#wrote, iclass 31, count 0 2006.173.11:41:40.69#ibcon#about to read 3, iclass 31, count 0 2006.173.11:41:40.71#ibcon#read 3, iclass 31, count 0 2006.173.11:41:40.71#ibcon#about to read 4, iclass 31, count 0 2006.173.11:41:40.71#ibcon#read 4, iclass 31, count 0 2006.173.11:41:40.71#ibcon#about to read 5, iclass 31, count 0 2006.173.11:41:40.71#ibcon#read 5, iclass 31, count 0 2006.173.11:41:40.71#ibcon#about to read 6, iclass 31, count 0 2006.173.11:41:40.71#ibcon#read 6, iclass 31, count 0 2006.173.11:41:40.71#ibcon#end of sib2, iclass 31, count 0 2006.173.11:41:40.71#ibcon#*mode == 0, iclass 31, count 0 2006.173.11:41:40.71#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.11:41:40.71#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.11:41:40.71#ibcon#*before write, iclass 31, count 0 2006.173.11:41:40.71#ibcon#enter sib2, iclass 31, count 0 2006.173.11:41:40.71#ibcon#flushed, iclass 31, count 0 2006.173.11:41:40.71#ibcon#about to write, iclass 31, count 0 2006.173.11:41:40.71#ibcon#wrote, iclass 31, count 0 2006.173.11:41:40.71#ibcon#about to read 3, iclass 31, count 0 2006.173.11:41:40.75#ibcon#read 3, iclass 31, count 0 2006.173.11:41:40.75#ibcon#about to read 4, iclass 31, count 0 2006.173.11:41:40.75#ibcon#read 4, iclass 31, count 0 2006.173.11:41:40.75#ibcon#about to read 5, iclass 31, count 0 2006.173.11:41:40.75#ibcon#read 5, iclass 31, count 0 2006.173.11:41:40.75#ibcon#about to read 6, iclass 31, count 0 2006.173.11:41:40.75#ibcon#read 6, iclass 31, count 0 2006.173.11:41:40.75#ibcon#end of sib2, iclass 31, count 0 2006.173.11:41:40.75#ibcon#*after write, iclass 31, count 0 2006.173.11:41:40.75#ibcon#*before return 0, iclass 31, count 0 2006.173.11:41:40.75#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.11:41:40.75#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.11:41:40.75#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.11:41:40.75#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.11:41:40.75$vck44/va=5,4 2006.173.11:41:40.75#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.173.11:41:40.75#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.173.11:41:40.75#ibcon#ireg 11 cls_cnt 2 2006.173.11:41:40.75#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.11:41:40.81#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.11:41:40.81#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.11:41:40.81#ibcon#enter wrdev, iclass 33, count 2 2006.173.11:41:40.81#ibcon#first serial, iclass 33, count 2 2006.173.11:41:40.81#ibcon#enter sib2, iclass 33, count 2 2006.173.11:41:40.81#ibcon#flushed, iclass 33, count 2 2006.173.11:41:40.81#ibcon#about to write, iclass 33, count 2 2006.173.11:41:40.81#ibcon#wrote, iclass 33, count 2 2006.173.11:41:40.81#ibcon#about to read 3, iclass 33, count 2 2006.173.11:41:40.83#ibcon#read 3, iclass 33, count 2 2006.173.11:41:40.83#ibcon#about to read 4, iclass 33, count 2 2006.173.11:41:40.83#ibcon#read 4, iclass 33, count 2 2006.173.11:41:40.83#ibcon#about to read 5, iclass 33, count 2 2006.173.11:41:40.83#ibcon#read 5, iclass 33, count 2 2006.173.11:41:40.83#ibcon#about to read 6, iclass 33, count 2 2006.173.11:41:40.83#ibcon#read 6, iclass 33, count 2 2006.173.11:41:40.83#ibcon#end of sib2, iclass 33, count 2 2006.173.11:41:40.83#ibcon#*mode == 0, iclass 33, count 2 2006.173.11:41:40.83#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.173.11:41:40.83#ibcon#[25=AT05-04\r\n] 2006.173.11:41:40.83#ibcon#*before write, iclass 33, count 2 2006.173.11:41:40.83#ibcon#enter sib2, iclass 33, count 2 2006.173.11:41:40.83#ibcon#flushed, iclass 33, count 2 2006.173.11:41:40.83#ibcon#about to write, iclass 33, count 2 2006.173.11:41:40.83#ibcon#wrote, iclass 33, count 2 2006.173.11:41:40.83#ibcon#about to read 3, iclass 33, count 2 2006.173.11:41:40.86#ibcon#read 3, iclass 33, count 2 2006.173.11:41:40.86#ibcon#about to read 4, iclass 33, count 2 2006.173.11:41:40.86#ibcon#read 4, iclass 33, count 2 2006.173.11:41:40.86#ibcon#about to read 5, iclass 33, count 2 2006.173.11:41:40.86#ibcon#read 5, iclass 33, count 2 2006.173.11:41:40.86#ibcon#about to read 6, iclass 33, count 2 2006.173.11:41:40.86#ibcon#read 6, iclass 33, count 2 2006.173.11:41:40.86#ibcon#end of sib2, iclass 33, count 2 2006.173.11:41:40.86#ibcon#*after write, iclass 33, count 2 2006.173.11:41:40.86#ibcon#*before return 0, iclass 33, count 2 2006.173.11:41:40.86#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.11:41:40.86#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.173.11:41:40.86#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.173.11:41:40.86#ibcon#ireg 7 cls_cnt 0 2006.173.11:41:40.86#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.11:41:40.98#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.11:41:40.98#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.11:41:40.98#ibcon#enter wrdev, iclass 33, count 0 2006.173.11:41:40.98#ibcon#first serial, iclass 33, count 0 2006.173.11:41:40.98#ibcon#enter sib2, iclass 33, count 0 2006.173.11:41:40.98#ibcon#flushed, iclass 33, count 0 2006.173.11:41:40.98#ibcon#about to write, iclass 33, count 0 2006.173.11:41:40.98#ibcon#wrote, iclass 33, count 0 2006.173.11:41:40.98#ibcon#about to read 3, iclass 33, count 0 2006.173.11:41:41.00#ibcon#read 3, iclass 33, count 0 2006.173.11:41:41.00#ibcon#about to read 4, iclass 33, count 0 2006.173.11:41:41.00#ibcon#read 4, iclass 33, count 0 2006.173.11:41:41.00#ibcon#about to read 5, iclass 33, count 0 2006.173.11:41:41.00#ibcon#read 5, iclass 33, count 0 2006.173.11:41:41.00#ibcon#about to read 6, iclass 33, count 0 2006.173.11:41:41.00#ibcon#read 6, iclass 33, count 0 2006.173.11:41:41.00#ibcon#end of sib2, iclass 33, count 0 2006.173.11:41:41.00#ibcon#*mode == 0, iclass 33, count 0 2006.173.11:41:41.00#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.11:41:41.00#ibcon#[25=USB\r\n] 2006.173.11:41:41.00#ibcon#*before write, iclass 33, count 0 2006.173.11:41:41.00#ibcon#enter sib2, iclass 33, count 0 2006.173.11:41:41.00#ibcon#flushed, iclass 33, count 0 2006.173.11:41:41.00#ibcon#about to write, iclass 33, count 0 2006.173.11:41:41.00#ibcon#wrote, iclass 33, count 0 2006.173.11:41:41.00#ibcon#about to read 3, iclass 33, count 0 2006.173.11:41:41.03#ibcon#read 3, iclass 33, count 0 2006.173.11:41:41.03#ibcon#about to read 4, iclass 33, count 0 2006.173.11:41:41.03#ibcon#read 4, iclass 33, count 0 2006.173.11:41:41.03#ibcon#about to read 5, iclass 33, count 0 2006.173.11:41:41.03#ibcon#read 5, iclass 33, count 0 2006.173.11:41:41.03#ibcon#about to read 6, iclass 33, count 0 2006.173.11:41:41.03#ibcon#read 6, iclass 33, count 0 2006.173.11:41:41.03#ibcon#end of sib2, iclass 33, count 0 2006.173.11:41:41.03#ibcon#*after write, iclass 33, count 0 2006.173.11:41:41.03#ibcon#*before return 0, iclass 33, count 0 2006.173.11:41:41.03#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.11:41:41.03#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.173.11:41:41.03#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.11:41:41.03#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.11:41:41.03$vck44/valo=6,814.99 2006.173.11:41:41.03#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.11:41:41.03#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.11:41:41.03#ibcon#ireg 17 cls_cnt 0 2006.173.11:41:41.03#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.11:41:41.03#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.11:41:41.03#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.11:41:41.03#ibcon#enter wrdev, iclass 35, count 0 2006.173.11:41:41.03#ibcon#first serial, iclass 35, count 0 2006.173.11:41:41.03#ibcon#enter sib2, iclass 35, count 0 2006.173.11:41:41.03#ibcon#flushed, iclass 35, count 0 2006.173.11:41:41.03#ibcon#about to write, iclass 35, count 0 2006.173.11:41:41.03#ibcon#wrote, iclass 35, count 0 2006.173.11:41:41.03#ibcon#about to read 3, iclass 35, count 0 2006.173.11:41:41.05#ibcon#read 3, iclass 35, count 0 2006.173.11:41:41.05#ibcon#about to read 4, iclass 35, count 0 2006.173.11:41:41.05#ibcon#read 4, iclass 35, count 0 2006.173.11:41:41.05#ibcon#about to read 5, iclass 35, count 0 2006.173.11:41:41.05#ibcon#read 5, iclass 35, count 0 2006.173.11:41:41.05#ibcon#about to read 6, iclass 35, count 0 2006.173.11:41:41.05#ibcon#read 6, iclass 35, count 0 2006.173.11:41:41.05#ibcon#end of sib2, iclass 35, count 0 2006.173.11:41:41.05#ibcon#*mode == 0, iclass 35, count 0 2006.173.11:41:41.05#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.11:41:41.05#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.11:41:41.05#ibcon#*before write, iclass 35, count 0 2006.173.11:41:41.05#ibcon#enter sib2, iclass 35, count 0 2006.173.11:41:41.05#ibcon#flushed, iclass 35, count 0 2006.173.11:41:41.05#ibcon#about to write, iclass 35, count 0 2006.173.11:41:41.05#ibcon#wrote, iclass 35, count 0 2006.173.11:41:41.05#ibcon#about to read 3, iclass 35, count 0 2006.173.11:41:41.09#ibcon#read 3, iclass 35, count 0 2006.173.11:41:41.09#ibcon#about to read 4, iclass 35, count 0 2006.173.11:41:41.09#ibcon#read 4, iclass 35, count 0 2006.173.11:41:41.09#ibcon#about to read 5, iclass 35, count 0 2006.173.11:41:41.09#ibcon#read 5, iclass 35, count 0 2006.173.11:41:41.09#ibcon#about to read 6, iclass 35, count 0 2006.173.11:41:41.09#ibcon#read 6, iclass 35, count 0 2006.173.11:41:41.09#ibcon#end of sib2, iclass 35, count 0 2006.173.11:41:41.09#ibcon#*after write, iclass 35, count 0 2006.173.11:41:41.09#ibcon#*before return 0, iclass 35, count 0 2006.173.11:41:41.09#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.11:41:41.09#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.11:41:41.09#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.11:41:41.09#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.11:41:41.09$vck44/va=6,3 2006.173.11:41:41.09#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.173.11:41:41.09#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.173.11:41:41.09#ibcon#ireg 11 cls_cnt 2 2006.173.11:41:41.09#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.11:41:41.15#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.11:41:41.15#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.11:41:41.15#ibcon#enter wrdev, iclass 37, count 2 2006.173.11:41:41.15#ibcon#first serial, iclass 37, count 2 2006.173.11:41:41.15#ibcon#enter sib2, iclass 37, count 2 2006.173.11:41:41.15#ibcon#flushed, iclass 37, count 2 2006.173.11:41:41.15#ibcon#about to write, iclass 37, count 2 2006.173.11:41:41.15#ibcon#wrote, iclass 37, count 2 2006.173.11:41:41.15#ibcon#about to read 3, iclass 37, count 2 2006.173.11:41:41.17#ibcon#read 3, iclass 37, count 2 2006.173.11:41:41.17#ibcon#about to read 4, iclass 37, count 2 2006.173.11:41:41.17#ibcon#read 4, iclass 37, count 2 2006.173.11:41:41.17#ibcon#about to read 5, iclass 37, count 2 2006.173.11:41:41.17#ibcon#read 5, iclass 37, count 2 2006.173.11:41:41.17#ibcon#about to read 6, iclass 37, count 2 2006.173.11:41:41.17#ibcon#read 6, iclass 37, count 2 2006.173.11:41:41.17#ibcon#end of sib2, iclass 37, count 2 2006.173.11:41:41.17#ibcon#*mode == 0, iclass 37, count 2 2006.173.11:41:41.17#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.173.11:41:41.17#ibcon#[25=AT06-03\r\n] 2006.173.11:41:41.17#ibcon#*before write, iclass 37, count 2 2006.173.11:41:41.17#ibcon#enter sib2, iclass 37, count 2 2006.173.11:41:41.17#ibcon#flushed, iclass 37, count 2 2006.173.11:41:41.17#ibcon#about to write, iclass 37, count 2 2006.173.11:41:41.17#ibcon#wrote, iclass 37, count 2 2006.173.11:41:41.17#ibcon#about to read 3, iclass 37, count 2 2006.173.11:41:41.20#ibcon#read 3, iclass 37, count 2 2006.173.11:41:41.20#ibcon#about to read 4, iclass 37, count 2 2006.173.11:41:41.20#ibcon#read 4, iclass 37, count 2 2006.173.11:41:41.20#ibcon#about to read 5, iclass 37, count 2 2006.173.11:41:41.20#ibcon#read 5, iclass 37, count 2 2006.173.11:41:41.20#ibcon#about to read 6, iclass 37, count 2 2006.173.11:41:41.20#ibcon#read 6, iclass 37, count 2 2006.173.11:41:41.20#ibcon#end of sib2, iclass 37, count 2 2006.173.11:41:41.20#ibcon#*after write, iclass 37, count 2 2006.173.11:41:41.20#ibcon#*before return 0, iclass 37, count 2 2006.173.11:41:41.20#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.11:41:41.20#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.173.11:41:41.20#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.173.11:41:41.20#ibcon#ireg 7 cls_cnt 0 2006.173.11:41:41.20#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.11:41:41.32#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.11:41:41.32#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.11:41:41.32#ibcon#enter wrdev, iclass 37, count 0 2006.173.11:41:41.32#ibcon#first serial, iclass 37, count 0 2006.173.11:41:41.32#ibcon#enter sib2, iclass 37, count 0 2006.173.11:41:41.32#ibcon#flushed, iclass 37, count 0 2006.173.11:41:41.32#ibcon#about to write, iclass 37, count 0 2006.173.11:41:41.32#ibcon#wrote, iclass 37, count 0 2006.173.11:41:41.32#ibcon#about to read 3, iclass 37, count 0 2006.173.11:41:41.34#ibcon#read 3, iclass 37, count 0 2006.173.11:41:41.34#ibcon#about to read 4, iclass 37, count 0 2006.173.11:41:41.34#ibcon#read 4, iclass 37, count 0 2006.173.11:41:41.34#ibcon#about to read 5, iclass 37, count 0 2006.173.11:41:41.34#ibcon#read 5, iclass 37, count 0 2006.173.11:41:41.34#ibcon#about to read 6, iclass 37, count 0 2006.173.11:41:41.34#ibcon#read 6, iclass 37, count 0 2006.173.11:41:41.34#ibcon#end of sib2, iclass 37, count 0 2006.173.11:41:41.34#ibcon#*mode == 0, iclass 37, count 0 2006.173.11:41:41.34#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.11:41:41.34#ibcon#[25=USB\r\n] 2006.173.11:41:41.34#ibcon#*before write, iclass 37, count 0 2006.173.11:41:41.34#ibcon#enter sib2, iclass 37, count 0 2006.173.11:41:41.34#ibcon#flushed, iclass 37, count 0 2006.173.11:41:41.34#ibcon#about to write, iclass 37, count 0 2006.173.11:41:41.34#ibcon#wrote, iclass 37, count 0 2006.173.11:41:41.34#ibcon#about to read 3, iclass 37, count 0 2006.173.11:41:41.37#ibcon#read 3, iclass 37, count 0 2006.173.11:41:41.37#ibcon#about to read 4, iclass 37, count 0 2006.173.11:41:41.37#ibcon#read 4, iclass 37, count 0 2006.173.11:41:41.37#ibcon#about to read 5, iclass 37, count 0 2006.173.11:41:41.37#ibcon#read 5, iclass 37, count 0 2006.173.11:41:41.37#ibcon#about to read 6, iclass 37, count 0 2006.173.11:41:41.37#ibcon#read 6, iclass 37, count 0 2006.173.11:41:41.37#ibcon#end of sib2, iclass 37, count 0 2006.173.11:41:41.37#ibcon#*after write, iclass 37, count 0 2006.173.11:41:41.37#ibcon#*before return 0, iclass 37, count 0 2006.173.11:41:41.37#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.11:41:41.37#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.173.11:41:41.37#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.11:41:41.37#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.11:41:41.37$vck44/valo=7,864.99 2006.173.11:41:41.37#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.11:41:41.37#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.11:41:41.37#ibcon#ireg 17 cls_cnt 0 2006.173.11:41:41.37#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.11:41:41.37#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.11:41:41.37#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.11:41:41.37#ibcon#enter wrdev, iclass 39, count 0 2006.173.11:41:41.37#ibcon#first serial, iclass 39, count 0 2006.173.11:41:41.37#ibcon#enter sib2, iclass 39, count 0 2006.173.11:41:41.37#ibcon#flushed, iclass 39, count 0 2006.173.11:41:41.37#ibcon#about to write, iclass 39, count 0 2006.173.11:41:41.37#ibcon#wrote, iclass 39, count 0 2006.173.11:41:41.37#ibcon#about to read 3, iclass 39, count 0 2006.173.11:41:41.39#ibcon#read 3, iclass 39, count 0 2006.173.11:41:41.39#ibcon#about to read 4, iclass 39, count 0 2006.173.11:41:41.39#ibcon#read 4, iclass 39, count 0 2006.173.11:41:41.39#ibcon#about to read 5, iclass 39, count 0 2006.173.11:41:41.39#ibcon#read 5, iclass 39, count 0 2006.173.11:41:41.39#ibcon#about to read 6, iclass 39, count 0 2006.173.11:41:41.39#ibcon#read 6, iclass 39, count 0 2006.173.11:41:41.39#ibcon#end of sib2, iclass 39, count 0 2006.173.11:41:41.39#ibcon#*mode == 0, iclass 39, count 0 2006.173.11:41:41.39#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.11:41:41.39#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.11:41:41.39#ibcon#*before write, iclass 39, count 0 2006.173.11:41:41.39#ibcon#enter sib2, iclass 39, count 0 2006.173.11:41:41.39#ibcon#flushed, iclass 39, count 0 2006.173.11:41:41.39#ibcon#about to write, iclass 39, count 0 2006.173.11:41:41.39#ibcon#wrote, iclass 39, count 0 2006.173.11:41:41.39#ibcon#about to read 3, iclass 39, count 0 2006.173.11:41:41.43#ibcon#read 3, iclass 39, count 0 2006.173.11:41:41.43#ibcon#about to read 4, iclass 39, count 0 2006.173.11:41:41.43#ibcon#read 4, iclass 39, count 0 2006.173.11:41:41.43#ibcon#about to read 5, iclass 39, count 0 2006.173.11:41:41.43#ibcon#read 5, iclass 39, count 0 2006.173.11:41:41.43#ibcon#about to read 6, iclass 39, count 0 2006.173.11:41:41.43#ibcon#read 6, iclass 39, count 0 2006.173.11:41:41.43#ibcon#end of sib2, iclass 39, count 0 2006.173.11:41:41.43#ibcon#*after write, iclass 39, count 0 2006.173.11:41:41.43#ibcon#*before return 0, iclass 39, count 0 2006.173.11:41:41.43#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.11:41:41.43#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.11:41:41.43#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.11:41:41.43#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.11:41:41.43$vck44/va=7,4 2006.173.11:41:41.43#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.11:41:41.43#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.11:41:41.43#ibcon#ireg 11 cls_cnt 2 2006.173.11:41:41.43#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.11:41:41.49#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.11:41:41.49#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.11:41:41.49#ibcon#enter wrdev, iclass 3, count 2 2006.173.11:41:41.49#ibcon#first serial, iclass 3, count 2 2006.173.11:41:41.49#ibcon#enter sib2, iclass 3, count 2 2006.173.11:41:41.49#ibcon#flushed, iclass 3, count 2 2006.173.11:41:41.49#ibcon#about to write, iclass 3, count 2 2006.173.11:41:41.49#ibcon#wrote, iclass 3, count 2 2006.173.11:41:41.49#ibcon#about to read 3, iclass 3, count 2 2006.173.11:41:41.51#ibcon#read 3, iclass 3, count 2 2006.173.11:41:41.51#ibcon#about to read 4, iclass 3, count 2 2006.173.11:41:41.51#ibcon#read 4, iclass 3, count 2 2006.173.11:41:41.51#ibcon#about to read 5, iclass 3, count 2 2006.173.11:41:41.51#ibcon#read 5, iclass 3, count 2 2006.173.11:41:41.51#ibcon#about to read 6, iclass 3, count 2 2006.173.11:41:41.51#ibcon#read 6, iclass 3, count 2 2006.173.11:41:41.51#ibcon#end of sib2, iclass 3, count 2 2006.173.11:41:41.51#ibcon#*mode == 0, iclass 3, count 2 2006.173.11:41:41.51#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.11:41:41.51#ibcon#[25=AT07-04\r\n] 2006.173.11:41:41.51#ibcon#*before write, iclass 3, count 2 2006.173.11:41:41.51#ibcon#enter sib2, iclass 3, count 2 2006.173.11:41:41.51#ibcon#flushed, iclass 3, count 2 2006.173.11:41:41.51#ibcon#about to write, iclass 3, count 2 2006.173.11:41:41.51#ibcon#wrote, iclass 3, count 2 2006.173.11:41:41.51#ibcon#about to read 3, iclass 3, count 2 2006.173.11:41:41.54#ibcon#read 3, iclass 3, count 2 2006.173.11:41:41.54#ibcon#about to read 4, iclass 3, count 2 2006.173.11:41:41.54#ibcon#read 4, iclass 3, count 2 2006.173.11:41:41.54#ibcon#about to read 5, iclass 3, count 2 2006.173.11:41:41.54#ibcon#read 5, iclass 3, count 2 2006.173.11:41:41.54#ibcon#about to read 6, iclass 3, count 2 2006.173.11:41:41.54#ibcon#read 6, iclass 3, count 2 2006.173.11:41:41.54#ibcon#end of sib2, iclass 3, count 2 2006.173.11:41:41.54#ibcon#*after write, iclass 3, count 2 2006.173.11:41:41.54#ibcon#*before return 0, iclass 3, count 2 2006.173.11:41:41.54#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.11:41:41.54#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.11:41:41.54#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.11:41:41.54#ibcon#ireg 7 cls_cnt 0 2006.173.11:41:41.54#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.11:41:41.66#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.11:41:41.66#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.11:41:41.66#ibcon#enter wrdev, iclass 3, count 0 2006.173.11:41:41.66#ibcon#first serial, iclass 3, count 0 2006.173.11:41:41.66#ibcon#enter sib2, iclass 3, count 0 2006.173.11:41:41.66#ibcon#flushed, iclass 3, count 0 2006.173.11:41:41.66#ibcon#about to write, iclass 3, count 0 2006.173.11:41:41.66#ibcon#wrote, iclass 3, count 0 2006.173.11:41:41.66#ibcon#about to read 3, iclass 3, count 0 2006.173.11:41:41.68#ibcon#read 3, iclass 3, count 0 2006.173.11:41:41.68#ibcon#about to read 4, iclass 3, count 0 2006.173.11:41:41.68#ibcon#read 4, iclass 3, count 0 2006.173.11:41:41.68#ibcon#about to read 5, iclass 3, count 0 2006.173.11:41:41.68#ibcon#read 5, iclass 3, count 0 2006.173.11:41:41.68#ibcon#about to read 6, iclass 3, count 0 2006.173.11:41:41.68#ibcon#read 6, iclass 3, count 0 2006.173.11:41:41.68#ibcon#end of sib2, iclass 3, count 0 2006.173.11:41:41.68#ibcon#*mode == 0, iclass 3, count 0 2006.173.11:41:41.68#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.11:41:41.68#ibcon#[25=USB\r\n] 2006.173.11:41:41.68#ibcon#*before write, iclass 3, count 0 2006.173.11:41:41.68#ibcon#enter sib2, iclass 3, count 0 2006.173.11:41:41.68#ibcon#flushed, iclass 3, count 0 2006.173.11:41:41.68#ibcon#about to write, iclass 3, count 0 2006.173.11:41:41.68#ibcon#wrote, iclass 3, count 0 2006.173.11:41:41.68#ibcon#about to read 3, iclass 3, count 0 2006.173.11:41:41.71#ibcon#read 3, iclass 3, count 0 2006.173.11:41:41.71#ibcon#about to read 4, iclass 3, count 0 2006.173.11:41:41.71#ibcon#read 4, iclass 3, count 0 2006.173.11:41:41.71#ibcon#about to read 5, iclass 3, count 0 2006.173.11:41:41.71#ibcon#read 5, iclass 3, count 0 2006.173.11:41:41.71#ibcon#about to read 6, iclass 3, count 0 2006.173.11:41:41.71#ibcon#read 6, iclass 3, count 0 2006.173.11:41:41.71#ibcon#end of sib2, iclass 3, count 0 2006.173.11:41:41.71#ibcon#*after write, iclass 3, count 0 2006.173.11:41:41.71#ibcon#*before return 0, iclass 3, count 0 2006.173.11:41:41.71#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.11:41:41.71#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.11:41:41.71#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.11:41:41.71#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.11:41:41.71$vck44/valo=8,884.99 2006.173.11:41:41.71#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.11:41:41.71#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.11:41:41.71#ibcon#ireg 17 cls_cnt 0 2006.173.11:41:41.71#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.11:41:41.71#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.11:41:41.71#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.11:41:41.71#ibcon#enter wrdev, iclass 5, count 0 2006.173.11:41:41.71#ibcon#first serial, iclass 5, count 0 2006.173.11:41:41.71#ibcon#enter sib2, iclass 5, count 0 2006.173.11:41:41.71#ibcon#flushed, iclass 5, count 0 2006.173.11:41:41.71#ibcon#about to write, iclass 5, count 0 2006.173.11:41:41.71#ibcon#wrote, iclass 5, count 0 2006.173.11:41:41.71#ibcon#about to read 3, iclass 5, count 0 2006.173.11:41:41.73#ibcon#read 3, iclass 5, count 0 2006.173.11:41:41.73#ibcon#about to read 4, iclass 5, count 0 2006.173.11:41:41.73#ibcon#read 4, iclass 5, count 0 2006.173.11:41:41.73#ibcon#about to read 5, iclass 5, count 0 2006.173.11:41:41.73#ibcon#read 5, iclass 5, count 0 2006.173.11:41:41.73#ibcon#about to read 6, iclass 5, count 0 2006.173.11:41:41.73#ibcon#read 6, iclass 5, count 0 2006.173.11:41:41.73#ibcon#end of sib2, iclass 5, count 0 2006.173.11:41:41.73#ibcon#*mode == 0, iclass 5, count 0 2006.173.11:41:41.73#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.11:41:41.73#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.11:41:41.73#ibcon#*before write, iclass 5, count 0 2006.173.11:41:41.73#ibcon#enter sib2, iclass 5, count 0 2006.173.11:41:41.73#ibcon#flushed, iclass 5, count 0 2006.173.11:41:41.73#ibcon#about to write, iclass 5, count 0 2006.173.11:41:41.73#ibcon#wrote, iclass 5, count 0 2006.173.11:41:41.73#ibcon#about to read 3, iclass 5, count 0 2006.173.11:41:41.77#ibcon#read 3, iclass 5, count 0 2006.173.11:41:41.77#ibcon#about to read 4, iclass 5, count 0 2006.173.11:41:41.77#ibcon#read 4, iclass 5, count 0 2006.173.11:41:41.77#ibcon#about to read 5, iclass 5, count 0 2006.173.11:41:41.77#ibcon#read 5, iclass 5, count 0 2006.173.11:41:41.77#ibcon#about to read 6, iclass 5, count 0 2006.173.11:41:41.77#ibcon#read 6, iclass 5, count 0 2006.173.11:41:41.77#ibcon#end of sib2, iclass 5, count 0 2006.173.11:41:41.77#ibcon#*after write, iclass 5, count 0 2006.173.11:41:41.77#ibcon#*before return 0, iclass 5, count 0 2006.173.11:41:41.77#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.11:41:41.77#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.11:41:41.77#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.11:41:41.77#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.11:41:41.77$vck44/va=8,4 2006.173.11:41:41.77#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.173.11:41:41.77#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.173.11:41:41.77#ibcon#ireg 11 cls_cnt 2 2006.173.11:41:41.77#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.11:41:41.83#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.11:41:41.83#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.11:41:41.83#ibcon#enter wrdev, iclass 7, count 2 2006.173.11:41:41.83#ibcon#first serial, iclass 7, count 2 2006.173.11:41:41.83#ibcon#enter sib2, iclass 7, count 2 2006.173.11:41:41.83#ibcon#flushed, iclass 7, count 2 2006.173.11:41:41.83#ibcon#about to write, iclass 7, count 2 2006.173.11:41:41.83#ibcon#wrote, iclass 7, count 2 2006.173.11:41:41.83#ibcon#about to read 3, iclass 7, count 2 2006.173.11:41:41.85#ibcon#read 3, iclass 7, count 2 2006.173.11:41:41.85#ibcon#about to read 4, iclass 7, count 2 2006.173.11:41:41.85#ibcon#read 4, iclass 7, count 2 2006.173.11:41:41.85#ibcon#about to read 5, iclass 7, count 2 2006.173.11:41:41.85#ibcon#read 5, iclass 7, count 2 2006.173.11:41:41.85#ibcon#about to read 6, iclass 7, count 2 2006.173.11:41:41.85#ibcon#read 6, iclass 7, count 2 2006.173.11:41:41.85#ibcon#end of sib2, iclass 7, count 2 2006.173.11:41:41.85#ibcon#*mode == 0, iclass 7, count 2 2006.173.11:41:41.85#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.173.11:41:41.85#ibcon#[25=AT08-04\r\n] 2006.173.11:41:41.85#ibcon#*before write, iclass 7, count 2 2006.173.11:41:41.85#ibcon#enter sib2, iclass 7, count 2 2006.173.11:41:41.85#ibcon#flushed, iclass 7, count 2 2006.173.11:41:41.85#ibcon#about to write, iclass 7, count 2 2006.173.11:41:41.85#ibcon#wrote, iclass 7, count 2 2006.173.11:41:41.85#ibcon#about to read 3, iclass 7, count 2 2006.173.11:41:41.88#ibcon#read 3, iclass 7, count 2 2006.173.11:41:41.88#ibcon#about to read 4, iclass 7, count 2 2006.173.11:41:41.88#ibcon#read 4, iclass 7, count 2 2006.173.11:41:41.88#ibcon#about to read 5, iclass 7, count 2 2006.173.11:41:41.88#ibcon#read 5, iclass 7, count 2 2006.173.11:41:41.88#ibcon#about to read 6, iclass 7, count 2 2006.173.11:41:41.88#ibcon#read 6, iclass 7, count 2 2006.173.11:41:41.88#ibcon#end of sib2, iclass 7, count 2 2006.173.11:41:41.88#ibcon#*after write, iclass 7, count 2 2006.173.11:41:41.88#ibcon#*before return 0, iclass 7, count 2 2006.173.11:41:41.88#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.11:41:41.88#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.173.11:41:41.88#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.173.11:41:41.88#ibcon#ireg 7 cls_cnt 0 2006.173.11:41:41.88#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.11:41:42.00#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.11:41:42.00#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.11:41:42.00#ibcon#enter wrdev, iclass 7, count 0 2006.173.11:41:42.00#ibcon#first serial, iclass 7, count 0 2006.173.11:41:42.00#ibcon#enter sib2, iclass 7, count 0 2006.173.11:41:42.00#ibcon#flushed, iclass 7, count 0 2006.173.11:41:42.00#ibcon#about to write, iclass 7, count 0 2006.173.11:41:42.00#ibcon#wrote, iclass 7, count 0 2006.173.11:41:42.00#ibcon#about to read 3, iclass 7, count 0 2006.173.11:41:42.02#ibcon#read 3, iclass 7, count 0 2006.173.11:41:42.02#ibcon#about to read 4, iclass 7, count 0 2006.173.11:41:42.02#ibcon#read 4, iclass 7, count 0 2006.173.11:41:42.02#ibcon#about to read 5, iclass 7, count 0 2006.173.11:41:42.02#ibcon#read 5, iclass 7, count 0 2006.173.11:41:42.02#ibcon#about to read 6, iclass 7, count 0 2006.173.11:41:42.02#ibcon#read 6, iclass 7, count 0 2006.173.11:41:42.02#ibcon#end of sib2, iclass 7, count 0 2006.173.11:41:42.02#ibcon#*mode == 0, iclass 7, count 0 2006.173.11:41:42.02#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.11:41:42.02#ibcon#[25=USB\r\n] 2006.173.11:41:42.02#ibcon#*before write, iclass 7, count 0 2006.173.11:41:42.02#ibcon#enter sib2, iclass 7, count 0 2006.173.11:41:42.02#ibcon#flushed, iclass 7, count 0 2006.173.11:41:42.02#ibcon#about to write, iclass 7, count 0 2006.173.11:41:42.02#ibcon#wrote, iclass 7, count 0 2006.173.11:41:42.02#ibcon#about to read 3, iclass 7, count 0 2006.173.11:41:42.05#ibcon#read 3, iclass 7, count 0 2006.173.11:41:42.05#ibcon#about to read 4, iclass 7, count 0 2006.173.11:41:42.05#ibcon#read 4, iclass 7, count 0 2006.173.11:41:42.05#ibcon#about to read 5, iclass 7, count 0 2006.173.11:41:42.05#ibcon#read 5, iclass 7, count 0 2006.173.11:41:42.05#ibcon#about to read 6, iclass 7, count 0 2006.173.11:41:42.05#ibcon#read 6, iclass 7, count 0 2006.173.11:41:42.05#ibcon#end of sib2, iclass 7, count 0 2006.173.11:41:42.05#ibcon#*after write, iclass 7, count 0 2006.173.11:41:42.05#ibcon#*before return 0, iclass 7, count 0 2006.173.11:41:42.05#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.11:41:42.05#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.173.11:41:42.05#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.11:41:42.05#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.11:41:42.05$vck44/vblo=1,629.99 2006.173.11:41:42.05#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.11:41:42.05#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.11:41:42.05#ibcon#ireg 17 cls_cnt 0 2006.173.11:41:42.05#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.11:41:42.05#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.11:41:42.05#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.11:41:42.05#ibcon#enter wrdev, iclass 11, count 0 2006.173.11:41:42.05#ibcon#first serial, iclass 11, count 0 2006.173.11:41:42.05#ibcon#enter sib2, iclass 11, count 0 2006.173.11:41:42.05#ibcon#flushed, iclass 11, count 0 2006.173.11:41:42.05#ibcon#about to write, iclass 11, count 0 2006.173.11:41:42.05#ibcon#wrote, iclass 11, count 0 2006.173.11:41:42.05#ibcon#about to read 3, iclass 11, count 0 2006.173.11:41:42.07#ibcon#read 3, iclass 11, count 0 2006.173.11:41:42.07#ibcon#about to read 4, iclass 11, count 0 2006.173.11:41:42.07#ibcon#read 4, iclass 11, count 0 2006.173.11:41:42.07#ibcon#about to read 5, iclass 11, count 0 2006.173.11:41:42.07#ibcon#read 5, iclass 11, count 0 2006.173.11:41:42.07#ibcon#about to read 6, iclass 11, count 0 2006.173.11:41:42.07#ibcon#read 6, iclass 11, count 0 2006.173.11:41:42.07#ibcon#end of sib2, iclass 11, count 0 2006.173.11:41:42.07#ibcon#*mode == 0, iclass 11, count 0 2006.173.11:41:42.07#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.11:41:42.07#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.11:41:42.07#ibcon#*before write, iclass 11, count 0 2006.173.11:41:42.07#ibcon#enter sib2, iclass 11, count 0 2006.173.11:41:42.07#ibcon#flushed, iclass 11, count 0 2006.173.11:41:42.07#ibcon#about to write, iclass 11, count 0 2006.173.11:41:42.07#ibcon#wrote, iclass 11, count 0 2006.173.11:41:42.07#ibcon#about to read 3, iclass 11, count 0 2006.173.11:41:42.11#ibcon#read 3, iclass 11, count 0 2006.173.11:41:42.11#ibcon#about to read 4, iclass 11, count 0 2006.173.11:41:42.11#ibcon#read 4, iclass 11, count 0 2006.173.11:41:42.11#ibcon#about to read 5, iclass 11, count 0 2006.173.11:41:42.11#ibcon#read 5, iclass 11, count 0 2006.173.11:41:42.11#ibcon#about to read 6, iclass 11, count 0 2006.173.11:41:42.11#ibcon#read 6, iclass 11, count 0 2006.173.11:41:42.11#ibcon#end of sib2, iclass 11, count 0 2006.173.11:41:42.11#ibcon#*after write, iclass 11, count 0 2006.173.11:41:42.11#ibcon#*before return 0, iclass 11, count 0 2006.173.11:41:42.11#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.11:41:42.11#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.11:41:42.11#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.11:41:42.11#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.11:41:42.11$vck44/vb=1,4 2006.173.11:41:42.11#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.173.11:41:42.11#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.173.11:41:42.11#ibcon#ireg 11 cls_cnt 2 2006.173.11:41:42.11#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.11:41:42.11#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.11:41:42.11#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.11:41:42.11#ibcon#enter wrdev, iclass 13, count 2 2006.173.11:41:42.11#ibcon#first serial, iclass 13, count 2 2006.173.11:41:42.11#ibcon#enter sib2, iclass 13, count 2 2006.173.11:41:42.11#ibcon#flushed, iclass 13, count 2 2006.173.11:41:42.11#ibcon#about to write, iclass 13, count 2 2006.173.11:41:42.11#ibcon#wrote, iclass 13, count 2 2006.173.11:41:42.11#ibcon#about to read 3, iclass 13, count 2 2006.173.11:41:42.13#ibcon#read 3, iclass 13, count 2 2006.173.11:41:42.13#ibcon#about to read 4, iclass 13, count 2 2006.173.11:41:42.13#ibcon#read 4, iclass 13, count 2 2006.173.11:41:42.13#ibcon#about to read 5, iclass 13, count 2 2006.173.11:41:42.13#ibcon#read 5, iclass 13, count 2 2006.173.11:41:42.13#ibcon#about to read 6, iclass 13, count 2 2006.173.11:41:42.13#ibcon#read 6, iclass 13, count 2 2006.173.11:41:42.13#ibcon#end of sib2, iclass 13, count 2 2006.173.11:41:42.13#ibcon#*mode == 0, iclass 13, count 2 2006.173.11:41:42.13#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.173.11:41:42.13#ibcon#[27=AT01-04\r\n] 2006.173.11:41:42.13#ibcon#*before write, iclass 13, count 2 2006.173.11:41:42.13#ibcon#enter sib2, iclass 13, count 2 2006.173.11:41:42.13#ibcon#flushed, iclass 13, count 2 2006.173.11:41:42.13#ibcon#about to write, iclass 13, count 2 2006.173.11:41:42.13#ibcon#wrote, iclass 13, count 2 2006.173.11:41:42.13#ibcon#about to read 3, iclass 13, count 2 2006.173.11:41:42.16#ibcon#read 3, iclass 13, count 2 2006.173.11:41:42.16#ibcon#about to read 4, iclass 13, count 2 2006.173.11:41:42.16#ibcon#read 4, iclass 13, count 2 2006.173.11:41:42.16#ibcon#about to read 5, iclass 13, count 2 2006.173.11:41:42.16#ibcon#read 5, iclass 13, count 2 2006.173.11:41:42.16#ibcon#about to read 6, iclass 13, count 2 2006.173.11:41:42.16#ibcon#read 6, iclass 13, count 2 2006.173.11:41:42.16#ibcon#end of sib2, iclass 13, count 2 2006.173.11:41:42.16#ibcon#*after write, iclass 13, count 2 2006.173.11:41:42.16#ibcon#*before return 0, iclass 13, count 2 2006.173.11:41:42.16#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.11:41:42.16#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.173.11:41:42.16#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.173.11:41:42.16#ibcon#ireg 7 cls_cnt 0 2006.173.11:41:42.16#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.11:41:42.28#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.11:41:42.28#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.11:41:42.28#ibcon#enter wrdev, iclass 13, count 0 2006.173.11:41:42.28#ibcon#first serial, iclass 13, count 0 2006.173.11:41:42.28#ibcon#enter sib2, iclass 13, count 0 2006.173.11:41:42.28#ibcon#flushed, iclass 13, count 0 2006.173.11:41:42.28#ibcon#about to write, iclass 13, count 0 2006.173.11:41:42.28#ibcon#wrote, iclass 13, count 0 2006.173.11:41:42.28#ibcon#about to read 3, iclass 13, count 0 2006.173.11:41:42.30#ibcon#read 3, iclass 13, count 0 2006.173.11:41:42.30#ibcon#about to read 4, iclass 13, count 0 2006.173.11:41:42.30#ibcon#read 4, iclass 13, count 0 2006.173.11:41:42.30#ibcon#about to read 5, iclass 13, count 0 2006.173.11:41:42.30#ibcon#read 5, iclass 13, count 0 2006.173.11:41:42.30#ibcon#about to read 6, iclass 13, count 0 2006.173.11:41:42.30#ibcon#read 6, iclass 13, count 0 2006.173.11:41:42.30#ibcon#end of sib2, iclass 13, count 0 2006.173.11:41:42.30#ibcon#*mode == 0, iclass 13, count 0 2006.173.11:41:42.30#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.11:41:42.30#ibcon#[27=USB\r\n] 2006.173.11:41:42.30#ibcon#*before write, iclass 13, count 0 2006.173.11:41:42.30#ibcon#enter sib2, iclass 13, count 0 2006.173.11:41:42.30#ibcon#flushed, iclass 13, count 0 2006.173.11:41:42.30#ibcon#about to write, iclass 13, count 0 2006.173.11:41:42.30#ibcon#wrote, iclass 13, count 0 2006.173.11:41:42.30#ibcon#about to read 3, iclass 13, count 0 2006.173.11:41:42.33#ibcon#read 3, iclass 13, count 0 2006.173.11:41:42.33#ibcon#about to read 4, iclass 13, count 0 2006.173.11:41:42.33#ibcon#read 4, iclass 13, count 0 2006.173.11:41:42.33#ibcon#about to read 5, iclass 13, count 0 2006.173.11:41:42.33#ibcon#read 5, iclass 13, count 0 2006.173.11:41:42.33#ibcon#about to read 6, iclass 13, count 0 2006.173.11:41:42.33#ibcon#read 6, iclass 13, count 0 2006.173.11:41:42.33#ibcon#end of sib2, iclass 13, count 0 2006.173.11:41:42.33#ibcon#*after write, iclass 13, count 0 2006.173.11:41:42.33#ibcon#*before return 0, iclass 13, count 0 2006.173.11:41:42.33#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.11:41:42.33#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.173.11:41:42.33#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.11:41:42.33#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.11:41:42.33$vck44/vblo=2,634.99 2006.173.11:41:42.33#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.11:41:42.33#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.11:41:42.33#ibcon#ireg 17 cls_cnt 0 2006.173.11:41:42.33#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.11:41:42.33#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.11:41:42.33#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.11:41:42.33#ibcon#enter wrdev, iclass 15, count 0 2006.173.11:41:42.33#ibcon#first serial, iclass 15, count 0 2006.173.11:41:42.33#ibcon#enter sib2, iclass 15, count 0 2006.173.11:41:42.33#ibcon#flushed, iclass 15, count 0 2006.173.11:41:42.33#ibcon#about to write, iclass 15, count 0 2006.173.11:41:42.33#ibcon#wrote, iclass 15, count 0 2006.173.11:41:42.33#ibcon#about to read 3, iclass 15, count 0 2006.173.11:41:42.35#ibcon#read 3, iclass 15, count 0 2006.173.11:41:42.35#ibcon#about to read 4, iclass 15, count 0 2006.173.11:41:42.35#ibcon#read 4, iclass 15, count 0 2006.173.11:41:42.35#ibcon#about to read 5, iclass 15, count 0 2006.173.11:41:42.35#ibcon#read 5, iclass 15, count 0 2006.173.11:41:42.35#ibcon#about to read 6, iclass 15, count 0 2006.173.11:41:42.35#ibcon#read 6, iclass 15, count 0 2006.173.11:41:42.35#ibcon#end of sib2, iclass 15, count 0 2006.173.11:41:42.35#ibcon#*mode == 0, iclass 15, count 0 2006.173.11:41:42.35#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.11:41:42.35#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.11:41:42.35#ibcon#*before write, iclass 15, count 0 2006.173.11:41:42.35#ibcon#enter sib2, iclass 15, count 0 2006.173.11:41:42.35#ibcon#flushed, iclass 15, count 0 2006.173.11:41:42.35#ibcon#about to write, iclass 15, count 0 2006.173.11:41:42.35#ibcon#wrote, iclass 15, count 0 2006.173.11:41:42.35#ibcon#about to read 3, iclass 15, count 0 2006.173.11:41:42.39#ibcon#read 3, iclass 15, count 0 2006.173.11:41:42.39#ibcon#about to read 4, iclass 15, count 0 2006.173.11:41:42.39#ibcon#read 4, iclass 15, count 0 2006.173.11:41:42.39#ibcon#about to read 5, iclass 15, count 0 2006.173.11:41:42.39#ibcon#read 5, iclass 15, count 0 2006.173.11:41:42.39#ibcon#about to read 6, iclass 15, count 0 2006.173.11:41:42.39#ibcon#read 6, iclass 15, count 0 2006.173.11:41:42.39#ibcon#end of sib2, iclass 15, count 0 2006.173.11:41:42.39#ibcon#*after write, iclass 15, count 0 2006.173.11:41:42.39#ibcon#*before return 0, iclass 15, count 0 2006.173.11:41:42.39#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.11:41:42.39#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.11:41:42.39#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.11:41:42.39#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.11:41:42.39$vck44/vb=2,4 2006.173.11:41:42.39#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.11:41:42.39#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.11:41:42.39#ibcon#ireg 11 cls_cnt 2 2006.173.11:41:42.39#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.11:41:42.45#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.11:41:42.45#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.11:41:42.45#ibcon#enter wrdev, iclass 17, count 2 2006.173.11:41:42.45#ibcon#first serial, iclass 17, count 2 2006.173.11:41:42.45#ibcon#enter sib2, iclass 17, count 2 2006.173.11:41:42.45#ibcon#flushed, iclass 17, count 2 2006.173.11:41:42.45#ibcon#about to write, iclass 17, count 2 2006.173.11:41:42.45#ibcon#wrote, iclass 17, count 2 2006.173.11:41:42.45#ibcon#about to read 3, iclass 17, count 2 2006.173.11:41:42.47#ibcon#read 3, iclass 17, count 2 2006.173.11:41:42.47#ibcon#about to read 4, iclass 17, count 2 2006.173.11:41:42.47#ibcon#read 4, iclass 17, count 2 2006.173.11:41:42.47#ibcon#about to read 5, iclass 17, count 2 2006.173.11:41:42.47#ibcon#read 5, iclass 17, count 2 2006.173.11:41:42.47#ibcon#about to read 6, iclass 17, count 2 2006.173.11:41:42.47#ibcon#read 6, iclass 17, count 2 2006.173.11:41:42.47#ibcon#end of sib2, iclass 17, count 2 2006.173.11:41:42.47#ibcon#*mode == 0, iclass 17, count 2 2006.173.11:41:42.47#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.11:41:42.47#ibcon#[27=AT02-04\r\n] 2006.173.11:41:42.47#ibcon#*before write, iclass 17, count 2 2006.173.11:41:42.47#ibcon#enter sib2, iclass 17, count 2 2006.173.11:41:42.47#ibcon#flushed, iclass 17, count 2 2006.173.11:41:42.47#ibcon#about to write, iclass 17, count 2 2006.173.11:41:42.47#ibcon#wrote, iclass 17, count 2 2006.173.11:41:42.47#ibcon#about to read 3, iclass 17, count 2 2006.173.11:41:42.50#ibcon#read 3, iclass 17, count 2 2006.173.11:41:42.50#ibcon#about to read 4, iclass 17, count 2 2006.173.11:41:42.50#ibcon#read 4, iclass 17, count 2 2006.173.11:41:42.50#ibcon#about to read 5, iclass 17, count 2 2006.173.11:41:42.50#ibcon#read 5, iclass 17, count 2 2006.173.11:41:42.50#ibcon#about to read 6, iclass 17, count 2 2006.173.11:41:42.50#ibcon#read 6, iclass 17, count 2 2006.173.11:41:42.50#ibcon#end of sib2, iclass 17, count 2 2006.173.11:41:42.50#ibcon#*after write, iclass 17, count 2 2006.173.11:41:42.50#ibcon#*before return 0, iclass 17, count 2 2006.173.11:41:42.50#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.11:41:42.50#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.11:41:42.50#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.11:41:42.50#ibcon#ireg 7 cls_cnt 0 2006.173.11:41:42.50#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.11:41:42.62#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.11:41:42.62#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.11:41:42.62#ibcon#enter wrdev, iclass 17, count 0 2006.173.11:41:42.62#ibcon#first serial, iclass 17, count 0 2006.173.11:41:42.62#ibcon#enter sib2, iclass 17, count 0 2006.173.11:41:42.62#ibcon#flushed, iclass 17, count 0 2006.173.11:41:42.62#ibcon#about to write, iclass 17, count 0 2006.173.11:41:42.62#ibcon#wrote, iclass 17, count 0 2006.173.11:41:42.62#ibcon#about to read 3, iclass 17, count 0 2006.173.11:41:42.64#ibcon#read 3, iclass 17, count 0 2006.173.11:41:42.64#ibcon#about to read 4, iclass 17, count 0 2006.173.11:41:42.64#ibcon#read 4, iclass 17, count 0 2006.173.11:41:42.64#ibcon#about to read 5, iclass 17, count 0 2006.173.11:41:42.64#ibcon#read 5, iclass 17, count 0 2006.173.11:41:42.64#ibcon#about to read 6, iclass 17, count 0 2006.173.11:41:42.64#ibcon#read 6, iclass 17, count 0 2006.173.11:41:42.64#ibcon#end of sib2, iclass 17, count 0 2006.173.11:41:42.64#ibcon#*mode == 0, iclass 17, count 0 2006.173.11:41:42.64#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.11:41:42.64#ibcon#[27=USB\r\n] 2006.173.11:41:42.64#ibcon#*before write, iclass 17, count 0 2006.173.11:41:42.64#ibcon#enter sib2, iclass 17, count 0 2006.173.11:41:42.64#ibcon#flushed, iclass 17, count 0 2006.173.11:41:42.64#ibcon#about to write, iclass 17, count 0 2006.173.11:41:42.64#ibcon#wrote, iclass 17, count 0 2006.173.11:41:42.64#ibcon#about to read 3, iclass 17, count 0 2006.173.11:41:42.67#ibcon#read 3, iclass 17, count 0 2006.173.11:41:42.67#ibcon#about to read 4, iclass 17, count 0 2006.173.11:41:42.67#ibcon#read 4, iclass 17, count 0 2006.173.11:41:42.67#ibcon#about to read 5, iclass 17, count 0 2006.173.11:41:42.67#ibcon#read 5, iclass 17, count 0 2006.173.11:41:42.67#ibcon#about to read 6, iclass 17, count 0 2006.173.11:41:42.67#ibcon#read 6, iclass 17, count 0 2006.173.11:41:42.67#ibcon#end of sib2, iclass 17, count 0 2006.173.11:41:42.67#ibcon#*after write, iclass 17, count 0 2006.173.11:41:42.67#ibcon#*before return 0, iclass 17, count 0 2006.173.11:41:42.67#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.11:41:42.67#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.11:41:42.67#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.11:41:42.67#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.11:41:42.67$vck44/vblo=3,649.99 2006.173.11:41:42.67#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.11:41:42.67#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.11:41:42.67#ibcon#ireg 17 cls_cnt 0 2006.173.11:41:42.67#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.11:41:42.67#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.11:41:42.67#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.11:41:42.67#ibcon#enter wrdev, iclass 19, count 0 2006.173.11:41:42.67#ibcon#first serial, iclass 19, count 0 2006.173.11:41:42.67#ibcon#enter sib2, iclass 19, count 0 2006.173.11:41:42.67#ibcon#flushed, iclass 19, count 0 2006.173.11:41:42.67#ibcon#about to write, iclass 19, count 0 2006.173.11:41:42.67#ibcon#wrote, iclass 19, count 0 2006.173.11:41:42.67#ibcon#about to read 3, iclass 19, count 0 2006.173.11:41:42.69#ibcon#read 3, iclass 19, count 0 2006.173.11:41:42.69#ibcon#about to read 4, iclass 19, count 0 2006.173.11:41:42.69#ibcon#read 4, iclass 19, count 0 2006.173.11:41:42.69#ibcon#about to read 5, iclass 19, count 0 2006.173.11:41:42.69#ibcon#read 5, iclass 19, count 0 2006.173.11:41:42.69#ibcon#about to read 6, iclass 19, count 0 2006.173.11:41:42.69#ibcon#read 6, iclass 19, count 0 2006.173.11:41:42.69#ibcon#end of sib2, iclass 19, count 0 2006.173.11:41:42.69#ibcon#*mode == 0, iclass 19, count 0 2006.173.11:41:42.69#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.11:41:42.69#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.11:41:42.69#ibcon#*before write, iclass 19, count 0 2006.173.11:41:42.69#ibcon#enter sib2, iclass 19, count 0 2006.173.11:41:42.69#ibcon#flushed, iclass 19, count 0 2006.173.11:41:42.69#ibcon#about to write, iclass 19, count 0 2006.173.11:41:42.69#ibcon#wrote, iclass 19, count 0 2006.173.11:41:42.69#ibcon#about to read 3, iclass 19, count 0 2006.173.11:41:42.73#ibcon#read 3, iclass 19, count 0 2006.173.11:41:42.73#ibcon#about to read 4, iclass 19, count 0 2006.173.11:41:42.73#ibcon#read 4, iclass 19, count 0 2006.173.11:41:42.73#ibcon#about to read 5, iclass 19, count 0 2006.173.11:41:42.73#ibcon#read 5, iclass 19, count 0 2006.173.11:41:42.73#ibcon#about to read 6, iclass 19, count 0 2006.173.11:41:42.73#ibcon#read 6, iclass 19, count 0 2006.173.11:41:42.73#ibcon#end of sib2, iclass 19, count 0 2006.173.11:41:42.73#ibcon#*after write, iclass 19, count 0 2006.173.11:41:42.73#ibcon#*before return 0, iclass 19, count 0 2006.173.11:41:42.73#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.11:41:42.73#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.11:41:42.73#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.11:41:42.73#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.11:41:42.73$vck44/vb=3,4 2006.173.11:41:42.73#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.11:41:42.73#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.11:41:42.73#ibcon#ireg 11 cls_cnt 2 2006.173.11:41:42.73#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.11:41:42.79#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.11:41:42.79#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.11:41:42.79#ibcon#enter wrdev, iclass 21, count 2 2006.173.11:41:42.79#ibcon#first serial, iclass 21, count 2 2006.173.11:41:42.79#ibcon#enter sib2, iclass 21, count 2 2006.173.11:41:42.79#ibcon#flushed, iclass 21, count 2 2006.173.11:41:42.79#ibcon#about to write, iclass 21, count 2 2006.173.11:41:42.79#ibcon#wrote, iclass 21, count 2 2006.173.11:41:42.79#ibcon#about to read 3, iclass 21, count 2 2006.173.11:41:42.81#ibcon#read 3, iclass 21, count 2 2006.173.11:41:42.81#ibcon#about to read 4, iclass 21, count 2 2006.173.11:41:42.81#ibcon#read 4, iclass 21, count 2 2006.173.11:41:42.81#ibcon#about to read 5, iclass 21, count 2 2006.173.11:41:42.81#ibcon#read 5, iclass 21, count 2 2006.173.11:41:42.81#ibcon#about to read 6, iclass 21, count 2 2006.173.11:41:42.81#ibcon#read 6, iclass 21, count 2 2006.173.11:41:42.81#ibcon#end of sib2, iclass 21, count 2 2006.173.11:41:42.81#ibcon#*mode == 0, iclass 21, count 2 2006.173.11:41:42.81#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.11:41:42.81#ibcon#[27=AT03-04\r\n] 2006.173.11:41:42.81#ibcon#*before write, iclass 21, count 2 2006.173.11:41:42.81#ibcon#enter sib2, iclass 21, count 2 2006.173.11:41:42.81#ibcon#flushed, iclass 21, count 2 2006.173.11:41:42.81#ibcon#about to write, iclass 21, count 2 2006.173.11:41:42.81#ibcon#wrote, iclass 21, count 2 2006.173.11:41:42.81#ibcon#about to read 3, iclass 21, count 2 2006.173.11:41:42.84#ibcon#read 3, iclass 21, count 2 2006.173.11:41:42.84#ibcon#about to read 4, iclass 21, count 2 2006.173.11:41:42.84#ibcon#read 4, iclass 21, count 2 2006.173.11:41:42.84#ibcon#about to read 5, iclass 21, count 2 2006.173.11:41:42.84#ibcon#read 5, iclass 21, count 2 2006.173.11:41:42.84#ibcon#about to read 6, iclass 21, count 2 2006.173.11:41:42.84#ibcon#read 6, iclass 21, count 2 2006.173.11:41:42.84#ibcon#end of sib2, iclass 21, count 2 2006.173.11:41:42.84#ibcon#*after write, iclass 21, count 2 2006.173.11:41:42.84#ibcon#*before return 0, iclass 21, count 2 2006.173.11:41:42.84#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.11:41:42.84#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.11:41:42.84#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.11:41:42.84#ibcon#ireg 7 cls_cnt 0 2006.173.11:41:42.84#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.11:41:42.96#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.11:41:42.96#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.11:41:42.96#ibcon#enter wrdev, iclass 21, count 0 2006.173.11:41:42.96#ibcon#first serial, iclass 21, count 0 2006.173.11:41:42.96#ibcon#enter sib2, iclass 21, count 0 2006.173.11:41:42.96#ibcon#flushed, iclass 21, count 0 2006.173.11:41:42.96#ibcon#about to write, iclass 21, count 0 2006.173.11:41:42.96#ibcon#wrote, iclass 21, count 0 2006.173.11:41:42.96#ibcon#about to read 3, iclass 21, count 0 2006.173.11:41:42.98#ibcon#read 3, iclass 21, count 0 2006.173.11:41:42.98#ibcon#about to read 4, iclass 21, count 0 2006.173.11:41:42.98#ibcon#read 4, iclass 21, count 0 2006.173.11:41:42.98#ibcon#about to read 5, iclass 21, count 0 2006.173.11:41:42.98#ibcon#read 5, iclass 21, count 0 2006.173.11:41:42.98#ibcon#about to read 6, iclass 21, count 0 2006.173.11:41:42.98#ibcon#read 6, iclass 21, count 0 2006.173.11:41:42.98#ibcon#end of sib2, iclass 21, count 0 2006.173.11:41:42.98#ibcon#*mode == 0, iclass 21, count 0 2006.173.11:41:42.98#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.11:41:42.98#ibcon#[27=USB\r\n] 2006.173.11:41:42.98#ibcon#*before write, iclass 21, count 0 2006.173.11:41:42.98#ibcon#enter sib2, iclass 21, count 0 2006.173.11:41:42.98#ibcon#flushed, iclass 21, count 0 2006.173.11:41:42.98#ibcon#about to write, iclass 21, count 0 2006.173.11:41:42.98#ibcon#wrote, iclass 21, count 0 2006.173.11:41:42.98#ibcon#about to read 3, iclass 21, count 0 2006.173.11:41:43.01#ibcon#read 3, iclass 21, count 0 2006.173.11:41:43.01#ibcon#about to read 4, iclass 21, count 0 2006.173.11:41:43.01#ibcon#read 4, iclass 21, count 0 2006.173.11:41:43.01#ibcon#about to read 5, iclass 21, count 0 2006.173.11:41:43.01#ibcon#read 5, iclass 21, count 0 2006.173.11:41:43.01#ibcon#about to read 6, iclass 21, count 0 2006.173.11:41:43.01#ibcon#read 6, iclass 21, count 0 2006.173.11:41:43.01#ibcon#end of sib2, iclass 21, count 0 2006.173.11:41:43.01#ibcon#*after write, iclass 21, count 0 2006.173.11:41:43.01#ibcon#*before return 0, iclass 21, count 0 2006.173.11:41:43.01#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.11:41:43.01#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.11:41:43.01#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.11:41:43.01#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.11:41:43.01$vck44/vblo=4,679.99 2006.173.11:41:43.01#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.11:41:43.01#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.11:41:43.01#ibcon#ireg 17 cls_cnt 0 2006.173.11:41:43.01#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.11:41:43.01#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.11:41:43.01#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.11:41:43.01#ibcon#enter wrdev, iclass 23, count 0 2006.173.11:41:43.01#ibcon#first serial, iclass 23, count 0 2006.173.11:41:43.01#ibcon#enter sib2, iclass 23, count 0 2006.173.11:41:43.01#ibcon#flushed, iclass 23, count 0 2006.173.11:41:43.01#ibcon#about to write, iclass 23, count 0 2006.173.11:41:43.01#ibcon#wrote, iclass 23, count 0 2006.173.11:41:43.01#ibcon#about to read 3, iclass 23, count 0 2006.173.11:41:43.03#ibcon#read 3, iclass 23, count 0 2006.173.11:41:43.03#ibcon#about to read 4, iclass 23, count 0 2006.173.11:41:43.03#ibcon#read 4, iclass 23, count 0 2006.173.11:41:43.03#ibcon#about to read 5, iclass 23, count 0 2006.173.11:41:43.03#ibcon#read 5, iclass 23, count 0 2006.173.11:41:43.03#ibcon#about to read 6, iclass 23, count 0 2006.173.11:41:43.03#ibcon#read 6, iclass 23, count 0 2006.173.11:41:43.03#ibcon#end of sib2, iclass 23, count 0 2006.173.11:41:43.03#ibcon#*mode == 0, iclass 23, count 0 2006.173.11:41:43.03#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.11:41:43.03#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.11:41:43.03#ibcon#*before write, iclass 23, count 0 2006.173.11:41:43.03#ibcon#enter sib2, iclass 23, count 0 2006.173.11:41:43.03#ibcon#flushed, iclass 23, count 0 2006.173.11:41:43.03#ibcon#about to write, iclass 23, count 0 2006.173.11:41:43.03#ibcon#wrote, iclass 23, count 0 2006.173.11:41:43.03#ibcon#about to read 3, iclass 23, count 0 2006.173.11:41:43.07#ibcon#read 3, iclass 23, count 0 2006.173.11:41:43.07#ibcon#about to read 4, iclass 23, count 0 2006.173.11:41:43.07#ibcon#read 4, iclass 23, count 0 2006.173.11:41:43.07#ibcon#about to read 5, iclass 23, count 0 2006.173.11:41:43.07#ibcon#read 5, iclass 23, count 0 2006.173.11:41:43.07#ibcon#about to read 6, iclass 23, count 0 2006.173.11:41:43.07#ibcon#read 6, iclass 23, count 0 2006.173.11:41:43.07#ibcon#end of sib2, iclass 23, count 0 2006.173.11:41:43.07#ibcon#*after write, iclass 23, count 0 2006.173.11:41:43.07#ibcon#*before return 0, iclass 23, count 0 2006.173.11:41:43.07#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.11:41:43.07#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.11:41:43.07#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.11:41:43.07#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.11:41:43.07$vck44/vb=4,4 2006.173.11:41:43.07#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.11:41:43.07#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.11:41:43.07#ibcon#ireg 11 cls_cnt 2 2006.173.11:41:43.07#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.11:41:43.13#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.11:41:43.13#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.11:41:43.13#ibcon#enter wrdev, iclass 25, count 2 2006.173.11:41:43.13#ibcon#first serial, iclass 25, count 2 2006.173.11:41:43.13#ibcon#enter sib2, iclass 25, count 2 2006.173.11:41:43.13#ibcon#flushed, iclass 25, count 2 2006.173.11:41:43.13#ibcon#about to write, iclass 25, count 2 2006.173.11:41:43.13#ibcon#wrote, iclass 25, count 2 2006.173.11:41:43.13#ibcon#about to read 3, iclass 25, count 2 2006.173.11:41:43.15#ibcon#read 3, iclass 25, count 2 2006.173.11:41:43.15#ibcon#about to read 4, iclass 25, count 2 2006.173.11:41:43.15#ibcon#read 4, iclass 25, count 2 2006.173.11:41:43.15#ibcon#about to read 5, iclass 25, count 2 2006.173.11:41:43.15#ibcon#read 5, iclass 25, count 2 2006.173.11:41:43.15#ibcon#about to read 6, iclass 25, count 2 2006.173.11:41:43.15#ibcon#read 6, iclass 25, count 2 2006.173.11:41:43.15#ibcon#end of sib2, iclass 25, count 2 2006.173.11:41:43.15#ibcon#*mode == 0, iclass 25, count 2 2006.173.11:41:43.15#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.11:41:43.15#ibcon#[27=AT04-04\r\n] 2006.173.11:41:43.15#ibcon#*before write, iclass 25, count 2 2006.173.11:41:43.15#ibcon#enter sib2, iclass 25, count 2 2006.173.11:41:43.15#ibcon#flushed, iclass 25, count 2 2006.173.11:41:43.15#ibcon#about to write, iclass 25, count 2 2006.173.11:41:43.15#ibcon#wrote, iclass 25, count 2 2006.173.11:41:43.15#ibcon#about to read 3, iclass 25, count 2 2006.173.11:41:43.18#ibcon#read 3, iclass 25, count 2 2006.173.11:41:43.18#ibcon#about to read 4, iclass 25, count 2 2006.173.11:41:43.18#ibcon#read 4, iclass 25, count 2 2006.173.11:41:43.18#ibcon#about to read 5, iclass 25, count 2 2006.173.11:41:43.18#ibcon#read 5, iclass 25, count 2 2006.173.11:41:43.18#ibcon#about to read 6, iclass 25, count 2 2006.173.11:41:43.18#ibcon#read 6, iclass 25, count 2 2006.173.11:41:43.18#ibcon#end of sib2, iclass 25, count 2 2006.173.11:41:43.18#ibcon#*after write, iclass 25, count 2 2006.173.11:41:43.18#ibcon#*before return 0, iclass 25, count 2 2006.173.11:41:43.18#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.11:41:43.18#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.11:41:43.18#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.11:41:43.18#ibcon#ireg 7 cls_cnt 0 2006.173.11:41:43.18#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.11:41:43.30#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.11:41:43.30#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.11:41:43.30#ibcon#enter wrdev, iclass 25, count 0 2006.173.11:41:43.30#ibcon#first serial, iclass 25, count 0 2006.173.11:41:43.30#ibcon#enter sib2, iclass 25, count 0 2006.173.11:41:43.30#ibcon#flushed, iclass 25, count 0 2006.173.11:41:43.30#ibcon#about to write, iclass 25, count 0 2006.173.11:41:43.30#ibcon#wrote, iclass 25, count 0 2006.173.11:41:43.30#ibcon#about to read 3, iclass 25, count 0 2006.173.11:41:43.32#ibcon#read 3, iclass 25, count 0 2006.173.11:41:43.32#ibcon#about to read 4, iclass 25, count 0 2006.173.11:41:43.32#ibcon#read 4, iclass 25, count 0 2006.173.11:41:43.32#ibcon#about to read 5, iclass 25, count 0 2006.173.11:41:43.32#ibcon#read 5, iclass 25, count 0 2006.173.11:41:43.32#ibcon#about to read 6, iclass 25, count 0 2006.173.11:41:43.32#ibcon#read 6, iclass 25, count 0 2006.173.11:41:43.32#ibcon#end of sib2, iclass 25, count 0 2006.173.11:41:43.32#ibcon#*mode == 0, iclass 25, count 0 2006.173.11:41:43.32#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.11:41:43.32#ibcon#[27=USB\r\n] 2006.173.11:41:43.32#ibcon#*before write, iclass 25, count 0 2006.173.11:41:43.32#ibcon#enter sib2, iclass 25, count 0 2006.173.11:41:43.32#ibcon#flushed, iclass 25, count 0 2006.173.11:41:43.32#ibcon#about to write, iclass 25, count 0 2006.173.11:41:43.32#ibcon#wrote, iclass 25, count 0 2006.173.11:41:43.32#ibcon#about to read 3, iclass 25, count 0 2006.173.11:41:43.35#ibcon#read 3, iclass 25, count 0 2006.173.11:41:43.35#ibcon#about to read 4, iclass 25, count 0 2006.173.11:41:43.35#ibcon#read 4, iclass 25, count 0 2006.173.11:41:43.35#ibcon#about to read 5, iclass 25, count 0 2006.173.11:41:43.35#ibcon#read 5, iclass 25, count 0 2006.173.11:41:43.35#ibcon#about to read 6, iclass 25, count 0 2006.173.11:41:43.35#ibcon#read 6, iclass 25, count 0 2006.173.11:41:43.35#ibcon#end of sib2, iclass 25, count 0 2006.173.11:41:43.35#ibcon#*after write, iclass 25, count 0 2006.173.11:41:43.35#ibcon#*before return 0, iclass 25, count 0 2006.173.11:41:43.35#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.11:41:43.35#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.11:41:43.35#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.11:41:43.35#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.11:41:43.35$vck44/vblo=5,709.99 2006.173.11:41:43.35#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.11:41:43.35#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.11:41:43.35#ibcon#ireg 17 cls_cnt 0 2006.173.11:41:43.35#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.11:41:43.35#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.11:41:43.35#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.11:41:43.35#ibcon#enter wrdev, iclass 27, count 0 2006.173.11:41:43.35#ibcon#first serial, iclass 27, count 0 2006.173.11:41:43.35#ibcon#enter sib2, iclass 27, count 0 2006.173.11:41:43.35#ibcon#flushed, iclass 27, count 0 2006.173.11:41:43.35#ibcon#about to write, iclass 27, count 0 2006.173.11:41:43.35#ibcon#wrote, iclass 27, count 0 2006.173.11:41:43.35#ibcon#about to read 3, iclass 27, count 0 2006.173.11:41:43.37#ibcon#read 3, iclass 27, count 0 2006.173.11:41:43.37#ibcon#about to read 4, iclass 27, count 0 2006.173.11:41:43.37#ibcon#read 4, iclass 27, count 0 2006.173.11:41:43.37#ibcon#about to read 5, iclass 27, count 0 2006.173.11:41:43.37#ibcon#read 5, iclass 27, count 0 2006.173.11:41:43.37#ibcon#about to read 6, iclass 27, count 0 2006.173.11:41:43.37#ibcon#read 6, iclass 27, count 0 2006.173.11:41:43.37#ibcon#end of sib2, iclass 27, count 0 2006.173.11:41:43.37#ibcon#*mode == 0, iclass 27, count 0 2006.173.11:41:43.37#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.11:41:43.37#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.11:41:43.37#ibcon#*before write, iclass 27, count 0 2006.173.11:41:43.37#ibcon#enter sib2, iclass 27, count 0 2006.173.11:41:43.37#ibcon#flushed, iclass 27, count 0 2006.173.11:41:43.37#ibcon#about to write, iclass 27, count 0 2006.173.11:41:43.37#ibcon#wrote, iclass 27, count 0 2006.173.11:41:43.37#ibcon#about to read 3, iclass 27, count 0 2006.173.11:41:43.41#ibcon#read 3, iclass 27, count 0 2006.173.11:41:43.41#ibcon#about to read 4, iclass 27, count 0 2006.173.11:41:43.41#ibcon#read 4, iclass 27, count 0 2006.173.11:41:43.41#ibcon#about to read 5, iclass 27, count 0 2006.173.11:41:43.41#ibcon#read 5, iclass 27, count 0 2006.173.11:41:43.41#ibcon#about to read 6, iclass 27, count 0 2006.173.11:41:43.41#ibcon#read 6, iclass 27, count 0 2006.173.11:41:43.41#ibcon#end of sib2, iclass 27, count 0 2006.173.11:41:43.41#ibcon#*after write, iclass 27, count 0 2006.173.11:41:43.41#ibcon#*before return 0, iclass 27, count 0 2006.173.11:41:43.41#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.11:41:43.41#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.11:41:43.41#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.11:41:43.41#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.11:41:43.41$vck44/vb=5,4 2006.173.11:41:43.41#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.11:41:43.41#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.11:41:43.41#ibcon#ireg 11 cls_cnt 2 2006.173.11:41:43.41#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.11:41:43.47#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.11:41:43.47#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.11:41:43.47#ibcon#enter wrdev, iclass 29, count 2 2006.173.11:41:43.47#ibcon#first serial, iclass 29, count 2 2006.173.11:41:43.47#ibcon#enter sib2, iclass 29, count 2 2006.173.11:41:43.47#ibcon#flushed, iclass 29, count 2 2006.173.11:41:43.47#ibcon#about to write, iclass 29, count 2 2006.173.11:41:43.47#ibcon#wrote, iclass 29, count 2 2006.173.11:41:43.47#ibcon#about to read 3, iclass 29, count 2 2006.173.11:41:43.49#ibcon#read 3, iclass 29, count 2 2006.173.11:41:43.49#ibcon#about to read 4, iclass 29, count 2 2006.173.11:41:43.49#ibcon#read 4, iclass 29, count 2 2006.173.11:41:43.49#ibcon#about to read 5, iclass 29, count 2 2006.173.11:41:43.49#ibcon#read 5, iclass 29, count 2 2006.173.11:41:43.49#ibcon#about to read 6, iclass 29, count 2 2006.173.11:41:43.49#ibcon#read 6, iclass 29, count 2 2006.173.11:41:43.49#ibcon#end of sib2, iclass 29, count 2 2006.173.11:41:43.49#ibcon#*mode == 0, iclass 29, count 2 2006.173.11:41:43.49#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.11:41:43.49#ibcon#[27=AT05-04\r\n] 2006.173.11:41:43.49#ibcon#*before write, iclass 29, count 2 2006.173.11:41:43.49#ibcon#enter sib2, iclass 29, count 2 2006.173.11:41:43.49#ibcon#flushed, iclass 29, count 2 2006.173.11:41:43.49#ibcon#about to write, iclass 29, count 2 2006.173.11:41:43.49#ibcon#wrote, iclass 29, count 2 2006.173.11:41:43.49#ibcon#about to read 3, iclass 29, count 2 2006.173.11:41:43.52#ibcon#read 3, iclass 29, count 2 2006.173.11:41:43.52#ibcon#about to read 4, iclass 29, count 2 2006.173.11:41:43.52#ibcon#read 4, iclass 29, count 2 2006.173.11:41:43.52#ibcon#about to read 5, iclass 29, count 2 2006.173.11:41:43.52#ibcon#read 5, iclass 29, count 2 2006.173.11:41:43.52#ibcon#about to read 6, iclass 29, count 2 2006.173.11:41:43.52#ibcon#read 6, iclass 29, count 2 2006.173.11:41:43.52#ibcon#end of sib2, iclass 29, count 2 2006.173.11:41:43.52#ibcon#*after write, iclass 29, count 2 2006.173.11:41:43.52#ibcon#*before return 0, iclass 29, count 2 2006.173.11:41:43.52#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.11:41:43.52#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.11:41:43.52#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.11:41:43.52#ibcon#ireg 7 cls_cnt 0 2006.173.11:41:43.52#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.11:41:43.64#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.11:41:43.64#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.11:41:43.64#ibcon#enter wrdev, iclass 29, count 0 2006.173.11:41:43.64#ibcon#first serial, iclass 29, count 0 2006.173.11:41:43.64#ibcon#enter sib2, iclass 29, count 0 2006.173.11:41:43.64#ibcon#flushed, iclass 29, count 0 2006.173.11:41:43.64#ibcon#about to write, iclass 29, count 0 2006.173.11:41:43.64#ibcon#wrote, iclass 29, count 0 2006.173.11:41:43.64#ibcon#about to read 3, iclass 29, count 0 2006.173.11:41:43.66#ibcon#read 3, iclass 29, count 0 2006.173.11:41:43.66#ibcon#about to read 4, iclass 29, count 0 2006.173.11:41:43.66#ibcon#read 4, iclass 29, count 0 2006.173.11:41:43.66#ibcon#about to read 5, iclass 29, count 0 2006.173.11:41:43.66#ibcon#read 5, iclass 29, count 0 2006.173.11:41:43.66#ibcon#about to read 6, iclass 29, count 0 2006.173.11:41:43.66#ibcon#read 6, iclass 29, count 0 2006.173.11:41:43.66#ibcon#end of sib2, iclass 29, count 0 2006.173.11:41:43.66#ibcon#*mode == 0, iclass 29, count 0 2006.173.11:41:43.66#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.11:41:43.66#ibcon#[27=USB\r\n] 2006.173.11:41:43.66#ibcon#*before write, iclass 29, count 0 2006.173.11:41:43.66#ibcon#enter sib2, iclass 29, count 0 2006.173.11:41:43.66#ibcon#flushed, iclass 29, count 0 2006.173.11:41:43.66#ibcon#about to write, iclass 29, count 0 2006.173.11:41:43.66#ibcon#wrote, iclass 29, count 0 2006.173.11:41:43.66#ibcon#about to read 3, iclass 29, count 0 2006.173.11:41:43.69#ibcon#read 3, iclass 29, count 0 2006.173.11:41:43.69#ibcon#about to read 4, iclass 29, count 0 2006.173.11:41:43.69#ibcon#read 4, iclass 29, count 0 2006.173.11:41:43.69#ibcon#about to read 5, iclass 29, count 0 2006.173.11:41:43.69#ibcon#read 5, iclass 29, count 0 2006.173.11:41:43.69#ibcon#about to read 6, iclass 29, count 0 2006.173.11:41:43.69#ibcon#read 6, iclass 29, count 0 2006.173.11:41:43.69#ibcon#end of sib2, iclass 29, count 0 2006.173.11:41:43.69#ibcon#*after write, iclass 29, count 0 2006.173.11:41:43.69#ibcon#*before return 0, iclass 29, count 0 2006.173.11:41:43.69#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.11:41:43.69#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.11:41:43.69#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.11:41:43.69#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.11:41:43.69$vck44/vblo=6,719.99 2006.173.11:41:43.69#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.11:41:43.69#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.11:41:43.69#ibcon#ireg 17 cls_cnt 0 2006.173.11:41:43.69#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.11:41:43.69#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.11:41:43.69#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.11:41:43.69#ibcon#enter wrdev, iclass 31, count 0 2006.173.11:41:43.69#ibcon#first serial, iclass 31, count 0 2006.173.11:41:43.69#ibcon#enter sib2, iclass 31, count 0 2006.173.11:41:43.69#ibcon#flushed, iclass 31, count 0 2006.173.11:41:43.69#ibcon#about to write, iclass 31, count 0 2006.173.11:41:43.69#ibcon#wrote, iclass 31, count 0 2006.173.11:41:43.69#ibcon#about to read 3, iclass 31, count 0 2006.173.11:41:43.71#ibcon#read 3, iclass 31, count 0 2006.173.11:41:43.71#ibcon#about to read 4, iclass 31, count 0 2006.173.11:41:43.71#ibcon#read 4, iclass 31, count 0 2006.173.11:41:43.71#ibcon#about to read 5, iclass 31, count 0 2006.173.11:41:43.71#ibcon#read 5, iclass 31, count 0 2006.173.11:41:43.71#ibcon#about to read 6, iclass 31, count 0 2006.173.11:41:43.71#ibcon#read 6, iclass 31, count 0 2006.173.11:41:43.71#ibcon#end of sib2, iclass 31, count 0 2006.173.11:41:43.71#ibcon#*mode == 0, iclass 31, count 0 2006.173.11:41:43.71#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.11:41:43.71#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.11:41:43.71#ibcon#*before write, iclass 31, count 0 2006.173.11:41:43.71#ibcon#enter sib2, iclass 31, count 0 2006.173.11:41:43.71#ibcon#flushed, iclass 31, count 0 2006.173.11:41:43.71#ibcon#about to write, iclass 31, count 0 2006.173.11:41:43.71#ibcon#wrote, iclass 31, count 0 2006.173.11:41:43.71#ibcon#about to read 3, iclass 31, count 0 2006.173.11:41:43.75#ibcon#read 3, iclass 31, count 0 2006.173.11:41:43.75#ibcon#about to read 4, iclass 31, count 0 2006.173.11:41:43.75#ibcon#read 4, iclass 31, count 0 2006.173.11:41:43.75#ibcon#about to read 5, iclass 31, count 0 2006.173.11:41:43.75#ibcon#read 5, iclass 31, count 0 2006.173.11:41:43.75#ibcon#about to read 6, iclass 31, count 0 2006.173.11:41:43.75#ibcon#read 6, iclass 31, count 0 2006.173.11:41:43.75#ibcon#end of sib2, iclass 31, count 0 2006.173.11:41:43.75#ibcon#*after write, iclass 31, count 0 2006.173.11:41:43.75#ibcon#*before return 0, iclass 31, count 0 2006.173.11:41:43.75#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.11:41:43.75#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.11:41:43.75#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.11:41:43.75#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.11:41:43.75$vck44/vb=6,4 2006.173.11:41:43.75#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.173.11:41:43.75#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.173.11:41:43.75#ibcon#ireg 11 cls_cnt 2 2006.173.11:41:43.75#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.11:41:43.81#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.11:41:43.81#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.11:41:43.81#ibcon#enter wrdev, iclass 33, count 2 2006.173.11:41:43.81#ibcon#first serial, iclass 33, count 2 2006.173.11:41:43.81#ibcon#enter sib2, iclass 33, count 2 2006.173.11:41:43.81#ibcon#flushed, iclass 33, count 2 2006.173.11:41:43.81#ibcon#about to write, iclass 33, count 2 2006.173.11:41:43.81#ibcon#wrote, iclass 33, count 2 2006.173.11:41:43.81#ibcon#about to read 3, iclass 33, count 2 2006.173.11:41:43.83#ibcon#read 3, iclass 33, count 2 2006.173.11:41:43.83#ibcon#about to read 4, iclass 33, count 2 2006.173.11:41:43.83#ibcon#read 4, iclass 33, count 2 2006.173.11:41:43.83#ibcon#about to read 5, iclass 33, count 2 2006.173.11:41:43.83#ibcon#read 5, iclass 33, count 2 2006.173.11:41:43.83#ibcon#about to read 6, iclass 33, count 2 2006.173.11:41:43.83#ibcon#read 6, iclass 33, count 2 2006.173.11:41:43.83#ibcon#end of sib2, iclass 33, count 2 2006.173.11:41:43.83#ibcon#*mode == 0, iclass 33, count 2 2006.173.11:41:43.83#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.173.11:41:43.83#ibcon#[27=AT06-04\r\n] 2006.173.11:41:43.83#ibcon#*before write, iclass 33, count 2 2006.173.11:41:43.83#ibcon#enter sib2, iclass 33, count 2 2006.173.11:41:43.83#ibcon#flushed, iclass 33, count 2 2006.173.11:41:43.83#ibcon#about to write, iclass 33, count 2 2006.173.11:41:43.83#ibcon#wrote, iclass 33, count 2 2006.173.11:41:43.83#ibcon#about to read 3, iclass 33, count 2 2006.173.11:41:43.86#ibcon#read 3, iclass 33, count 2 2006.173.11:41:43.86#ibcon#about to read 4, iclass 33, count 2 2006.173.11:41:43.86#ibcon#read 4, iclass 33, count 2 2006.173.11:41:43.86#ibcon#about to read 5, iclass 33, count 2 2006.173.11:41:43.86#ibcon#read 5, iclass 33, count 2 2006.173.11:41:43.86#ibcon#about to read 6, iclass 33, count 2 2006.173.11:41:43.86#ibcon#read 6, iclass 33, count 2 2006.173.11:41:43.86#ibcon#end of sib2, iclass 33, count 2 2006.173.11:41:43.86#ibcon#*after write, iclass 33, count 2 2006.173.11:41:43.86#ibcon#*before return 0, iclass 33, count 2 2006.173.11:41:43.86#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.11:41:43.86#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.173.11:41:43.86#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.173.11:41:43.86#ibcon#ireg 7 cls_cnt 0 2006.173.11:41:43.86#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.11:41:43.98#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.11:41:43.98#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.11:41:43.98#ibcon#enter wrdev, iclass 33, count 0 2006.173.11:41:43.98#ibcon#first serial, iclass 33, count 0 2006.173.11:41:43.98#ibcon#enter sib2, iclass 33, count 0 2006.173.11:41:43.98#ibcon#flushed, iclass 33, count 0 2006.173.11:41:43.98#ibcon#about to write, iclass 33, count 0 2006.173.11:41:43.98#ibcon#wrote, iclass 33, count 0 2006.173.11:41:43.98#ibcon#about to read 3, iclass 33, count 0 2006.173.11:41:44.00#ibcon#read 3, iclass 33, count 0 2006.173.11:41:44.00#ibcon#about to read 4, iclass 33, count 0 2006.173.11:41:44.00#ibcon#read 4, iclass 33, count 0 2006.173.11:41:44.00#ibcon#about to read 5, iclass 33, count 0 2006.173.11:41:44.00#ibcon#read 5, iclass 33, count 0 2006.173.11:41:44.00#ibcon#about to read 6, iclass 33, count 0 2006.173.11:41:44.00#ibcon#read 6, iclass 33, count 0 2006.173.11:41:44.00#ibcon#end of sib2, iclass 33, count 0 2006.173.11:41:44.00#ibcon#*mode == 0, iclass 33, count 0 2006.173.11:41:44.00#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.11:41:44.00#ibcon#[27=USB\r\n] 2006.173.11:41:44.00#ibcon#*before write, iclass 33, count 0 2006.173.11:41:44.00#ibcon#enter sib2, iclass 33, count 0 2006.173.11:41:44.00#ibcon#flushed, iclass 33, count 0 2006.173.11:41:44.00#ibcon#about to write, iclass 33, count 0 2006.173.11:41:44.00#ibcon#wrote, iclass 33, count 0 2006.173.11:41:44.00#ibcon#about to read 3, iclass 33, count 0 2006.173.11:41:44.03#ibcon#read 3, iclass 33, count 0 2006.173.11:41:44.03#ibcon#about to read 4, iclass 33, count 0 2006.173.11:41:44.03#ibcon#read 4, iclass 33, count 0 2006.173.11:41:44.03#ibcon#about to read 5, iclass 33, count 0 2006.173.11:41:44.03#ibcon#read 5, iclass 33, count 0 2006.173.11:41:44.03#ibcon#about to read 6, iclass 33, count 0 2006.173.11:41:44.03#ibcon#read 6, iclass 33, count 0 2006.173.11:41:44.03#ibcon#end of sib2, iclass 33, count 0 2006.173.11:41:44.03#ibcon#*after write, iclass 33, count 0 2006.173.11:41:44.03#ibcon#*before return 0, iclass 33, count 0 2006.173.11:41:44.03#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.11:41:44.03#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.173.11:41:44.03#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.11:41:44.03#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.11:41:44.03$vck44/vblo=7,734.99 2006.173.11:41:44.03#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.11:41:44.03#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.11:41:44.03#ibcon#ireg 17 cls_cnt 0 2006.173.11:41:44.03#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.11:41:44.03#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.11:41:44.03#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.11:41:44.03#ibcon#enter wrdev, iclass 35, count 0 2006.173.11:41:44.03#ibcon#first serial, iclass 35, count 0 2006.173.11:41:44.03#ibcon#enter sib2, iclass 35, count 0 2006.173.11:41:44.03#ibcon#flushed, iclass 35, count 0 2006.173.11:41:44.03#ibcon#about to write, iclass 35, count 0 2006.173.11:41:44.03#ibcon#wrote, iclass 35, count 0 2006.173.11:41:44.03#ibcon#about to read 3, iclass 35, count 0 2006.173.11:41:44.05#ibcon#read 3, iclass 35, count 0 2006.173.11:41:44.05#ibcon#about to read 4, iclass 35, count 0 2006.173.11:41:44.05#ibcon#read 4, iclass 35, count 0 2006.173.11:41:44.05#ibcon#about to read 5, iclass 35, count 0 2006.173.11:41:44.05#ibcon#read 5, iclass 35, count 0 2006.173.11:41:44.05#ibcon#about to read 6, iclass 35, count 0 2006.173.11:41:44.05#ibcon#read 6, iclass 35, count 0 2006.173.11:41:44.05#ibcon#end of sib2, iclass 35, count 0 2006.173.11:41:44.05#ibcon#*mode == 0, iclass 35, count 0 2006.173.11:41:44.05#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.11:41:44.05#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.11:41:44.05#ibcon#*before write, iclass 35, count 0 2006.173.11:41:44.05#ibcon#enter sib2, iclass 35, count 0 2006.173.11:41:44.05#ibcon#flushed, iclass 35, count 0 2006.173.11:41:44.05#ibcon#about to write, iclass 35, count 0 2006.173.11:41:44.05#ibcon#wrote, iclass 35, count 0 2006.173.11:41:44.05#ibcon#about to read 3, iclass 35, count 0 2006.173.11:41:44.09#ibcon#read 3, iclass 35, count 0 2006.173.11:41:44.09#ibcon#about to read 4, iclass 35, count 0 2006.173.11:41:44.09#ibcon#read 4, iclass 35, count 0 2006.173.11:41:44.09#ibcon#about to read 5, iclass 35, count 0 2006.173.11:41:44.09#ibcon#read 5, iclass 35, count 0 2006.173.11:41:44.09#ibcon#about to read 6, iclass 35, count 0 2006.173.11:41:44.09#ibcon#read 6, iclass 35, count 0 2006.173.11:41:44.09#ibcon#end of sib2, iclass 35, count 0 2006.173.11:41:44.09#ibcon#*after write, iclass 35, count 0 2006.173.11:41:44.09#ibcon#*before return 0, iclass 35, count 0 2006.173.11:41:44.09#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.11:41:44.09#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.11:41:44.09#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.11:41:44.09#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.11:41:44.09$vck44/vb=7,4 2006.173.11:41:44.09#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.173.11:41:44.09#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.173.11:41:44.09#ibcon#ireg 11 cls_cnt 2 2006.173.11:41:44.09#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.11:41:44.15#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.11:41:44.15#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.11:41:44.15#ibcon#enter wrdev, iclass 37, count 2 2006.173.11:41:44.15#ibcon#first serial, iclass 37, count 2 2006.173.11:41:44.15#ibcon#enter sib2, iclass 37, count 2 2006.173.11:41:44.15#ibcon#flushed, iclass 37, count 2 2006.173.11:41:44.15#ibcon#about to write, iclass 37, count 2 2006.173.11:41:44.15#ibcon#wrote, iclass 37, count 2 2006.173.11:41:44.15#ibcon#about to read 3, iclass 37, count 2 2006.173.11:41:44.17#ibcon#read 3, iclass 37, count 2 2006.173.11:41:44.17#ibcon#about to read 4, iclass 37, count 2 2006.173.11:41:44.17#ibcon#read 4, iclass 37, count 2 2006.173.11:41:44.17#ibcon#about to read 5, iclass 37, count 2 2006.173.11:41:44.17#ibcon#read 5, iclass 37, count 2 2006.173.11:41:44.17#ibcon#about to read 6, iclass 37, count 2 2006.173.11:41:44.17#ibcon#read 6, iclass 37, count 2 2006.173.11:41:44.17#ibcon#end of sib2, iclass 37, count 2 2006.173.11:41:44.17#ibcon#*mode == 0, iclass 37, count 2 2006.173.11:41:44.17#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.173.11:41:44.17#ibcon#[27=AT07-04\r\n] 2006.173.11:41:44.17#ibcon#*before write, iclass 37, count 2 2006.173.11:41:44.17#ibcon#enter sib2, iclass 37, count 2 2006.173.11:41:44.17#ibcon#flushed, iclass 37, count 2 2006.173.11:41:44.17#ibcon#about to write, iclass 37, count 2 2006.173.11:41:44.17#ibcon#wrote, iclass 37, count 2 2006.173.11:41:44.17#ibcon#about to read 3, iclass 37, count 2 2006.173.11:41:44.20#ibcon#read 3, iclass 37, count 2 2006.173.11:41:44.20#ibcon#about to read 4, iclass 37, count 2 2006.173.11:41:44.20#ibcon#read 4, iclass 37, count 2 2006.173.11:41:44.20#ibcon#about to read 5, iclass 37, count 2 2006.173.11:41:44.20#ibcon#read 5, iclass 37, count 2 2006.173.11:41:44.20#ibcon#about to read 6, iclass 37, count 2 2006.173.11:41:44.20#ibcon#read 6, iclass 37, count 2 2006.173.11:41:44.20#ibcon#end of sib2, iclass 37, count 2 2006.173.11:41:44.20#ibcon#*after write, iclass 37, count 2 2006.173.11:41:44.20#ibcon#*before return 0, iclass 37, count 2 2006.173.11:41:44.20#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.11:41:44.20#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.173.11:41:44.20#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.173.11:41:44.20#ibcon#ireg 7 cls_cnt 0 2006.173.11:41:44.20#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.11:41:44.32#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.11:41:44.32#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.11:41:44.32#ibcon#enter wrdev, iclass 37, count 0 2006.173.11:41:44.32#ibcon#first serial, iclass 37, count 0 2006.173.11:41:44.32#ibcon#enter sib2, iclass 37, count 0 2006.173.11:41:44.32#ibcon#flushed, iclass 37, count 0 2006.173.11:41:44.32#ibcon#about to write, iclass 37, count 0 2006.173.11:41:44.32#ibcon#wrote, iclass 37, count 0 2006.173.11:41:44.32#ibcon#about to read 3, iclass 37, count 0 2006.173.11:41:44.34#ibcon#read 3, iclass 37, count 0 2006.173.11:41:44.34#ibcon#about to read 4, iclass 37, count 0 2006.173.11:41:44.34#ibcon#read 4, iclass 37, count 0 2006.173.11:41:44.34#ibcon#about to read 5, iclass 37, count 0 2006.173.11:41:44.34#ibcon#read 5, iclass 37, count 0 2006.173.11:41:44.34#ibcon#about to read 6, iclass 37, count 0 2006.173.11:41:44.34#ibcon#read 6, iclass 37, count 0 2006.173.11:41:44.34#ibcon#end of sib2, iclass 37, count 0 2006.173.11:41:44.34#ibcon#*mode == 0, iclass 37, count 0 2006.173.11:41:44.34#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.11:41:44.34#ibcon#[27=USB\r\n] 2006.173.11:41:44.34#ibcon#*before write, iclass 37, count 0 2006.173.11:41:44.34#ibcon#enter sib2, iclass 37, count 0 2006.173.11:41:44.34#ibcon#flushed, iclass 37, count 0 2006.173.11:41:44.34#ibcon#about to write, iclass 37, count 0 2006.173.11:41:44.34#ibcon#wrote, iclass 37, count 0 2006.173.11:41:44.34#ibcon#about to read 3, iclass 37, count 0 2006.173.11:41:44.37#ibcon#read 3, iclass 37, count 0 2006.173.11:41:44.37#ibcon#about to read 4, iclass 37, count 0 2006.173.11:41:44.37#ibcon#read 4, iclass 37, count 0 2006.173.11:41:44.37#ibcon#about to read 5, iclass 37, count 0 2006.173.11:41:44.37#ibcon#read 5, iclass 37, count 0 2006.173.11:41:44.37#ibcon#about to read 6, iclass 37, count 0 2006.173.11:41:44.37#ibcon#read 6, iclass 37, count 0 2006.173.11:41:44.37#ibcon#end of sib2, iclass 37, count 0 2006.173.11:41:44.37#ibcon#*after write, iclass 37, count 0 2006.173.11:41:44.37#ibcon#*before return 0, iclass 37, count 0 2006.173.11:41:44.37#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.11:41:44.37#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.173.11:41:44.37#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.11:41:44.37#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.11:41:44.37$vck44/vblo=8,744.99 2006.173.11:41:44.37#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.11:41:44.37#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.11:41:44.37#ibcon#ireg 17 cls_cnt 0 2006.173.11:41:44.37#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.11:41:44.37#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.11:41:44.37#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.11:41:44.37#ibcon#enter wrdev, iclass 39, count 0 2006.173.11:41:44.37#ibcon#first serial, iclass 39, count 0 2006.173.11:41:44.37#ibcon#enter sib2, iclass 39, count 0 2006.173.11:41:44.37#ibcon#flushed, iclass 39, count 0 2006.173.11:41:44.37#ibcon#about to write, iclass 39, count 0 2006.173.11:41:44.37#ibcon#wrote, iclass 39, count 0 2006.173.11:41:44.37#ibcon#about to read 3, iclass 39, count 0 2006.173.11:41:44.39#ibcon#read 3, iclass 39, count 0 2006.173.11:41:44.39#ibcon#about to read 4, iclass 39, count 0 2006.173.11:41:44.39#ibcon#read 4, iclass 39, count 0 2006.173.11:41:44.39#ibcon#about to read 5, iclass 39, count 0 2006.173.11:41:44.39#ibcon#read 5, iclass 39, count 0 2006.173.11:41:44.39#ibcon#about to read 6, iclass 39, count 0 2006.173.11:41:44.39#ibcon#read 6, iclass 39, count 0 2006.173.11:41:44.39#ibcon#end of sib2, iclass 39, count 0 2006.173.11:41:44.39#ibcon#*mode == 0, iclass 39, count 0 2006.173.11:41:44.39#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.11:41:44.39#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.11:41:44.39#ibcon#*before write, iclass 39, count 0 2006.173.11:41:44.39#ibcon#enter sib2, iclass 39, count 0 2006.173.11:41:44.39#ibcon#flushed, iclass 39, count 0 2006.173.11:41:44.39#ibcon#about to write, iclass 39, count 0 2006.173.11:41:44.39#ibcon#wrote, iclass 39, count 0 2006.173.11:41:44.39#ibcon#about to read 3, iclass 39, count 0 2006.173.11:41:44.43#ibcon#read 3, iclass 39, count 0 2006.173.11:41:44.43#ibcon#about to read 4, iclass 39, count 0 2006.173.11:41:44.43#ibcon#read 4, iclass 39, count 0 2006.173.11:41:44.43#ibcon#about to read 5, iclass 39, count 0 2006.173.11:41:44.43#ibcon#read 5, iclass 39, count 0 2006.173.11:41:44.43#ibcon#about to read 6, iclass 39, count 0 2006.173.11:41:44.43#ibcon#read 6, iclass 39, count 0 2006.173.11:41:44.43#ibcon#end of sib2, iclass 39, count 0 2006.173.11:41:44.43#ibcon#*after write, iclass 39, count 0 2006.173.11:41:44.43#ibcon#*before return 0, iclass 39, count 0 2006.173.11:41:44.43#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.11:41:44.43#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.11:41:44.43#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.11:41:44.43#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.11:41:44.43$vck44/vb=8,4 2006.173.11:41:44.43#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.11:41:44.43#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.11:41:44.43#ibcon#ireg 11 cls_cnt 2 2006.173.11:41:44.43#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.11:41:44.49#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.11:41:44.49#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.11:41:44.49#ibcon#enter wrdev, iclass 3, count 2 2006.173.11:41:44.49#ibcon#first serial, iclass 3, count 2 2006.173.11:41:44.49#ibcon#enter sib2, iclass 3, count 2 2006.173.11:41:44.49#ibcon#flushed, iclass 3, count 2 2006.173.11:41:44.49#ibcon#about to write, iclass 3, count 2 2006.173.11:41:44.49#ibcon#wrote, iclass 3, count 2 2006.173.11:41:44.49#ibcon#about to read 3, iclass 3, count 2 2006.173.11:41:44.51#ibcon#read 3, iclass 3, count 2 2006.173.11:41:44.51#ibcon#about to read 4, iclass 3, count 2 2006.173.11:41:44.51#ibcon#read 4, iclass 3, count 2 2006.173.11:41:44.51#ibcon#about to read 5, iclass 3, count 2 2006.173.11:41:44.51#ibcon#read 5, iclass 3, count 2 2006.173.11:41:44.51#ibcon#about to read 6, iclass 3, count 2 2006.173.11:41:44.51#ibcon#read 6, iclass 3, count 2 2006.173.11:41:44.51#ibcon#end of sib2, iclass 3, count 2 2006.173.11:41:44.51#ibcon#*mode == 0, iclass 3, count 2 2006.173.11:41:44.51#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.11:41:44.51#ibcon#[27=AT08-04\r\n] 2006.173.11:41:44.51#ibcon#*before write, iclass 3, count 2 2006.173.11:41:44.51#ibcon#enter sib2, iclass 3, count 2 2006.173.11:41:44.51#ibcon#flushed, iclass 3, count 2 2006.173.11:41:44.51#ibcon#about to write, iclass 3, count 2 2006.173.11:41:44.51#ibcon#wrote, iclass 3, count 2 2006.173.11:41:44.51#ibcon#about to read 3, iclass 3, count 2 2006.173.11:41:44.54#ibcon#read 3, iclass 3, count 2 2006.173.11:41:44.54#ibcon#about to read 4, iclass 3, count 2 2006.173.11:41:44.54#ibcon#read 4, iclass 3, count 2 2006.173.11:41:44.54#ibcon#about to read 5, iclass 3, count 2 2006.173.11:41:44.54#ibcon#read 5, iclass 3, count 2 2006.173.11:41:44.54#ibcon#about to read 6, iclass 3, count 2 2006.173.11:41:44.54#ibcon#read 6, iclass 3, count 2 2006.173.11:41:44.54#ibcon#end of sib2, iclass 3, count 2 2006.173.11:41:44.54#ibcon#*after write, iclass 3, count 2 2006.173.11:41:44.54#ibcon#*before return 0, iclass 3, count 2 2006.173.11:41:44.54#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.11:41:44.54#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.11:41:44.54#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.11:41:44.54#ibcon#ireg 7 cls_cnt 0 2006.173.11:41:44.54#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.11:41:44.66#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.11:41:44.66#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.11:41:44.66#ibcon#enter wrdev, iclass 3, count 0 2006.173.11:41:44.66#ibcon#first serial, iclass 3, count 0 2006.173.11:41:44.66#ibcon#enter sib2, iclass 3, count 0 2006.173.11:41:44.66#ibcon#flushed, iclass 3, count 0 2006.173.11:41:44.66#ibcon#about to write, iclass 3, count 0 2006.173.11:41:44.66#ibcon#wrote, iclass 3, count 0 2006.173.11:41:44.66#ibcon#about to read 3, iclass 3, count 0 2006.173.11:41:44.68#ibcon#read 3, iclass 3, count 0 2006.173.11:41:44.68#ibcon#about to read 4, iclass 3, count 0 2006.173.11:41:44.68#ibcon#read 4, iclass 3, count 0 2006.173.11:41:44.68#ibcon#about to read 5, iclass 3, count 0 2006.173.11:41:44.68#ibcon#read 5, iclass 3, count 0 2006.173.11:41:44.68#ibcon#about to read 6, iclass 3, count 0 2006.173.11:41:44.68#ibcon#read 6, iclass 3, count 0 2006.173.11:41:44.68#ibcon#end of sib2, iclass 3, count 0 2006.173.11:41:44.68#ibcon#*mode == 0, iclass 3, count 0 2006.173.11:41:44.68#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.11:41:44.68#ibcon#[27=USB\r\n] 2006.173.11:41:44.68#ibcon#*before write, iclass 3, count 0 2006.173.11:41:44.68#ibcon#enter sib2, iclass 3, count 0 2006.173.11:41:44.68#ibcon#flushed, iclass 3, count 0 2006.173.11:41:44.68#ibcon#about to write, iclass 3, count 0 2006.173.11:41:44.68#ibcon#wrote, iclass 3, count 0 2006.173.11:41:44.68#ibcon#about to read 3, iclass 3, count 0 2006.173.11:41:44.71#ibcon#read 3, iclass 3, count 0 2006.173.11:41:44.71#ibcon#about to read 4, iclass 3, count 0 2006.173.11:41:44.71#ibcon#read 4, iclass 3, count 0 2006.173.11:41:44.71#ibcon#about to read 5, iclass 3, count 0 2006.173.11:41:44.71#ibcon#read 5, iclass 3, count 0 2006.173.11:41:44.71#ibcon#about to read 6, iclass 3, count 0 2006.173.11:41:44.71#ibcon#read 6, iclass 3, count 0 2006.173.11:41:44.71#ibcon#end of sib2, iclass 3, count 0 2006.173.11:41:44.71#ibcon#*after write, iclass 3, count 0 2006.173.11:41:44.71#ibcon#*before return 0, iclass 3, count 0 2006.173.11:41:44.71#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.11:41:44.71#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.11:41:44.71#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.11:41:44.71#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.11:41:44.71$vck44/vabw=wide 2006.173.11:41:44.71#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.11:41:44.71#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.11:41:44.71#ibcon#ireg 8 cls_cnt 0 2006.173.11:41:44.71#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.11:41:44.71#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.11:41:44.71#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.11:41:44.71#ibcon#enter wrdev, iclass 5, count 0 2006.173.11:41:44.71#ibcon#first serial, iclass 5, count 0 2006.173.11:41:44.71#ibcon#enter sib2, iclass 5, count 0 2006.173.11:41:44.71#ibcon#flushed, iclass 5, count 0 2006.173.11:41:44.71#ibcon#about to write, iclass 5, count 0 2006.173.11:41:44.71#ibcon#wrote, iclass 5, count 0 2006.173.11:41:44.71#ibcon#about to read 3, iclass 5, count 0 2006.173.11:41:44.73#ibcon#read 3, iclass 5, count 0 2006.173.11:41:44.73#ibcon#about to read 4, iclass 5, count 0 2006.173.11:41:44.73#ibcon#read 4, iclass 5, count 0 2006.173.11:41:44.73#ibcon#about to read 5, iclass 5, count 0 2006.173.11:41:44.73#ibcon#read 5, iclass 5, count 0 2006.173.11:41:44.73#ibcon#about to read 6, iclass 5, count 0 2006.173.11:41:44.73#ibcon#read 6, iclass 5, count 0 2006.173.11:41:44.73#ibcon#end of sib2, iclass 5, count 0 2006.173.11:41:44.73#ibcon#*mode == 0, iclass 5, count 0 2006.173.11:41:44.73#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.11:41:44.73#ibcon#[25=BW32\r\n] 2006.173.11:41:44.73#ibcon#*before write, iclass 5, count 0 2006.173.11:41:44.73#ibcon#enter sib2, iclass 5, count 0 2006.173.11:41:44.73#ibcon#flushed, iclass 5, count 0 2006.173.11:41:44.73#ibcon#about to write, iclass 5, count 0 2006.173.11:41:44.73#ibcon#wrote, iclass 5, count 0 2006.173.11:41:44.73#ibcon#about to read 3, iclass 5, count 0 2006.173.11:41:44.76#ibcon#read 3, iclass 5, count 0 2006.173.11:41:44.76#ibcon#about to read 4, iclass 5, count 0 2006.173.11:41:44.76#ibcon#read 4, iclass 5, count 0 2006.173.11:41:44.76#ibcon#about to read 5, iclass 5, count 0 2006.173.11:41:44.76#ibcon#read 5, iclass 5, count 0 2006.173.11:41:44.76#ibcon#about to read 6, iclass 5, count 0 2006.173.11:41:44.76#ibcon#read 6, iclass 5, count 0 2006.173.11:41:44.76#ibcon#end of sib2, iclass 5, count 0 2006.173.11:41:44.76#ibcon#*after write, iclass 5, count 0 2006.173.11:41:44.76#ibcon#*before return 0, iclass 5, count 0 2006.173.11:41:44.76#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.11:41:44.76#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.11:41:44.76#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.11:41:44.76#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.11:41:44.76$vck44/vbbw=wide 2006.173.11:41:44.76#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.11:41:44.76#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.11:41:44.76#ibcon#ireg 8 cls_cnt 0 2006.173.11:41:44.76#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.11:41:44.83#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.11:41:44.83#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.11:41:44.83#ibcon#enter wrdev, iclass 7, count 0 2006.173.11:41:44.83#ibcon#first serial, iclass 7, count 0 2006.173.11:41:44.83#ibcon#enter sib2, iclass 7, count 0 2006.173.11:41:44.83#ibcon#flushed, iclass 7, count 0 2006.173.11:41:44.83#ibcon#about to write, iclass 7, count 0 2006.173.11:41:44.83#ibcon#wrote, iclass 7, count 0 2006.173.11:41:44.83#ibcon#about to read 3, iclass 7, count 0 2006.173.11:41:44.85#ibcon#read 3, iclass 7, count 0 2006.173.11:41:44.85#ibcon#about to read 4, iclass 7, count 0 2006.173.11:41:44.85#ibcon#read 4, iclass 7, count 0 2006.173.11:41:44.85#ibcon#about to read 5, iclass 7, count 0 2006.173.11:41:44.85#ibcon#read 5, iclass 7, count 0 2006.173.11:41:44.85#ibcon#about to read 6, iclass 7, count 0 2006.173.11:41:44.85#ibcon#read 6, iclass 7, count 0 2006.173.11:41:44.85#ibcon#end of sib2, iclass 7, count 0 2006.173.11:41:44.85#ibcon#*mode == 0, iclass 7, count 0 2006.173.11:41:44.85#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.11:41:44.85#ibcon#[27=BW32\r\n] 2006.173.11:41:44.85#ibcon#*before write, iclass 7, count 0 2006.173.11:41:44.85#ibcon#enter sib2, iclass 7, count 0 2006.173.11:41:44.85#ibcon#flushed, iclass 7, count 0 2006.173.11:41:44.85#ibcon#about to write, iclass 7, count 0 2006.173.11:41:44.85#ibcon#wrote, iclass 7, count 0 2006.173.11:41:44.85#ibcon#about to read 3, iclass 7, count 0 2006.173.11:41:44.88#ibcon#read 3, iclass 7, count 0 2006.173.11:41:44.88#ibcon#about to read 4, iclass 7, count 0 2006.173.11:41:44.88#ibcon#read 4, iclass 7, count 0 2006.173.11:41:44.88#ibcon#about to read 5, iclass 7, count 0 2006.173.11:41:44.88#ibcon#read 5, iclass 7, count 0 2006.173.11:41:44.88#ibcon#about to read 6, iclass 7, count 0 2006.173.11:41:44.88#ibcon#read 6, iclass 7, count 0 2006.173.11:41:44.88#ibcon#end of sib2, iclass 7, count 0 2006.173.11:41:44.88#ibcon#*after write, iclass 7, count 0 2006.173.11:41:44.88#ibcon#*before return 0, iclass 7, count 0 2006.173.11:41:44.88#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.11:41:44.88#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.11:41:44.88#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.11:41:44.88#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.11:41:44.88$setupk4/ifdk4 2006.173.11:41:44.88$ifdk4/lo= 2006.173.11:41:44.88$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.11:41:44.89$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.11:41:44.89$ifdk4/patch= 2006.173.11:41:44.89$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.11:41:44.89$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.11:41:44.89$setupk4/!*+20s 2006.173.11:41:47.34#abcon#<5=/01 0.7 1.7 22.26 941004.5\r\n> 2006.173.11:41:47.36#abcon#{5=INTERFACE CLEAR} 2006.173.11:41:47.42#abcon#[5=S1D000X0/0*\r\n] 2006.173.11:41:57.51#abcon#<5=/01 0.7 1.7 22.25 941004.6\r\n> 2006.173.11:41:57.53#abcon#{5=INTERFACE CLEAR} 2006.173.11:41:57.59#abcon#[5=S1D000X0/0*\r\n] 2006.173.11:41:59.40$setupk4/"tpicd 2006.173.11:41:59.40$setupk4/echo=off 2006.173.11:41:59.40$setupk4/xlog=off 2006.173.11:41:59.40:!2006.173.11:44:28 2006.173.11:42:43.14#trakl#Source acquired 2006.173.11:42:43.14#flagr#flagr/antenna,acquired 2006.173.11:44:28.00:preob 2006.173.11:44:29.14/onsource/TRACKING 2006.173.11:44:29.14:!2006.173.11:44:38 2006.173.11:44:38.00:"tape 2006.173.11:44:38.00:"st=record 2006.173.11:44:38.00:data_valid=on 2006.173.11:44:38.00:midob 2006.173.11:44:38.14/onsource/TRACKING 2006.173.11:44:38.14/wx/22.18,1004.5,94 2006.173.11:44:38.20/cable/+6.5030E-03 2006.173.11:44:39.29/va/01,07,usb,yes,44,47 2006.173.11:44:39.29/va/02,06,usb,yes,44,45 2006.173.11:44:39.29/va/03,05,usb,yes,55,57 2006.173.11:44:39.29/va/04,06,usb,yes,45,47 2006.173.11:44:39.29/va/05,04,usb,yes,35,36 2006.173.11:44:39.29/va/06,03,usb,yes,49,49 2006.173.11:44:39.29/va/07,04,usb,yes,40,41 2006.173.11:44:39.29/va/08,04,usb,yes,34,41 2006.173.11:44:39.52/valo/01,524.99,yes,locked 2006.173.11:44:39.52/valo/02,534.99,yes,locked 2006.173.11:44:39.52/valo/03,564.99,yes,locked 2006.173.11:44:39.52/valo/04,624.99,yes,locked 2006.173.11:44:39.52/valo/05,734.99,yes,locked 2006.173.11:44:39.52/valo/06,814.99,yes,locked 2006.173.11:44:39.52/valo/07,864.99,yes,locked 2006.173.11:44:39.52/valo/08,884.99,yes,locked 2006.173.11:44:40.61/vb/01,04,usb,yes,33,30 2006.173.11:44:40.61/vb/02,04,usb,yes,35,35 2006.173.11:44:40.61/vb/03,04,usb,yes,32,35 2006.173.11:44:40.61/vb/04,04,usb,yes,37,35 2006.173.11:44:40.61/vb/05,04,usb,yes,29,31 2006.173.11:44:40.61/vb/06,04,usb,yes,34,30 2006.173.11:44:40.61/vb/07,04,usb,yes,33,33 2006.173.11:44:40.61/vb/08,04,usb,yes,31,34 2006.173.11:44:40.84/vblo/01,629.99,yes,locked 2006.173.11:44:40.84/vblo/02,634.99,yes,locked 2006.173.11:44:40.84/vblo/03,649.99,yes,locked 2006.173.11:44:40.84/vblo/04,679.99,yes,locked 2006.173.11:44:40.84/vblo/05,709.99,yes,locked 2006.173.11:44:40.84/vblo/06,719.99,yes,locked 2006.173.11:44:40.84/vblo/07,734.99,yes,locked 2006.173.11:44:40.84/vblo/08,744.99,yes,locked 2006.173.11:44:40.99/vabw/8 2006.173.11:44:41.14/vbbw/8 2006.173.11:44:41.23/xfe/off,on,15.0 2006.173.11:44:41.60/ifatt/23,28,28,28 2006.173.11:44:42.07/fmout-gps/S +3.94E-07 2006.173.11:44:42.12:!2006.173.11:49:18 2006.173.11:49:18.01:data_valid=off 2006.173.11:49:18.02:"et 2006.173.11:49:18.02:!+3s 2006.173.11:49:21.03:"tape 2006.173.11:49:21.04:postob 2006.173.11:49:21.16/cable/+6.5015E-03 2006.173.11:49:21.17/wx/22.12,1004.3,93 2006.173.11:49:21.22/fmout-gps/S +3.90E-07 2006.173.11:49:21.23:scan_name=173-1150,jd0606,40 2006.173.11:49:21.23:source=1424-418,142756.30,-420619.4,2000.0,cw 2006.173.11:49:23.13#flagr#flagr/antenna,new-source 2006.173.11:49:23.13:checkk5 2006.173.11:49:23.48/chk_autoobs//k5ts1/ autoobs is running! 2006.173.11:49:23.87/chk_autoobs//k5ts2/ autoobs is running! 2006.173.11:49:24.31/chk_autoobs//k5ts3/ autoobs is running! 2006.173.11:49:24.70/chk_autoobs//k5ts4/ autoobs is running! 2006.173.11:49:25.09/chk_obsdata//k5ts1/T1731144??a.dat file size is correct (nominal:1120MB, actual:1116MB). 2006.173.11:49:25.51/chk_obsdata//k5ts2/T1731144??b.dat file size is correct (nominal:1120MB, actual:1116MB). 2006.173.11:49:25.93/chk_obsdata//k5ts3/T1731144??c.dat file size is correct (nominal:1120MB, actual:1116MB). 2006.173.11:49:26.32/chk_obsdata//k5ts4/T1731144??d.dat file size is correct (nominal:1120MB, actual:1116MB). 2006.173.11:49:27.06/k5log//k5ts1_log_newline 2006.173.11:49:27.77/k5log//k5ts2_log_newline 2006.173.11:49:28.48/k5log//k5ts3_log_newline 2006.173.11:49:29.19/k5log//k5ts4_log_newline 2006.173.11:49:29.21/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.11:49:29.21:setupk4=1 2006.173.11:49:29.21$setupk4/echo=on 2006.173.11:49:29.22$setupk4/pcalon 2006.173.11:49:29.22$pcalon/"no phase cal control is implemented here 2006.173.11:49:29.22$setupk4/"tpicd=stop 2006.173.11:49:29.22$setupk4/"rec=synch_on 2006.173.11:49:29.22$setupk4/"rec_mode=128 2006.173.11:49:29.22$setupk4/!* 2006.173.11:49:29.22$setupk4/recpk4 2006.173.11:49:29.22$recpk4/recpatch= 2006.173.11:49:29.22$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.11:49:29.22$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.11:49:29.22$setupk4/vck44 2006.173.11:49:29.22$vck44/valo=1,524.99 2006.173.11:49:29.22#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.11:49:29.22#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.11:49:29.22#ibcon#ireg 17 cls_cnt 0 2006.173.11:49:29.22#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.11:49:29.22#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.11:49:29.22#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.11:49:29.22#ibcon#enter wrdev, iclass 18, count 0 2006.173.11:49:29.22#ibcon#first serial, iclass 18, count 0 2006.173.11:49:29.22#ibcon#enter sib2, iclass 18, count 0 2006.173.11:49:29.22#ibcon#flushed, iclass 18, count 0 2006.173.11:49:29.22#ibcon#about to write, iclass 18, count 0 2006.173.11:49:29.22#ibcon#wrote, iclass 18, count 0 2006.173.11:49:29.22#ibcon#about to read 3, iclass 18, count 0 2006.173.11:49:29.24#ibcon#read 3, iclass 18, count 0 2006.173.11:49:29.24#ibcon#about to read 4, iclass 18, count 0 2006.173.11:49:29.24#ibcon#read 4, iclass 18, count 0 2006.173.11:49:29.24#ibcon#about to read 5, iclass 18, count 0 2006.173.11:49:29.24#ibcon#read 5, iclass 18, count 0 2006.173.11:49:29.24#ibcon#about to read 6, iclass 18, count 0 2006.173.11:49:29.24#ibcon#read 6, iclass 18, count 0 2006.173.11:49:29.24#ibcon#end of sib2, iclass 18, count 0 2006.173.11:49:29.24#ibcon#*mode == 0, iclass 18, count 0 2006.173.11:49:29.24#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.11:49:29.24#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.11:49:29.24#ibcon#*before write, iclass 18, count 0 2006.173.11:49:29.24#ibcon#enter sib2, iclass 18, count 0 2006.173.11:49:29.24#ibcon#flushed, iclass 18, count 0 2006.173.11:49:29.24#ibcon#about to write, iclass 18, count 0 2006.173.11:49:29.24#ibcon#wrote, iclass 18, count 0 2006.173.11:49:29.24#ibcon#about to read 3, iclass 18, count 0 2006.173.11:49:29.29#ibcon#read 3, iclass 18, count 0 2006.173.11:49:29.29#ibcon#about to read 4, iclass 18, count 0 2006.173.11:49:29.29#ibcon#read 4, iclass 18, count 0 2006.173.11:49:29.29#ibcon#about to read 5, iclass 18, count 0 2006.173.11:49:29.29#ibcon#read 5, iclass 18, count 0 2006.173.11:49:29.29#ibcon#about to read 6, iclass 18, count 0 2006.173.11:49:29.29#ibcon#read 6, iclass 18, count 0 2006.173.11:49:29.29#ibcon#end of sib2, iclass 18, count 0 2006.173.11:49:29.29#ibcon#*after write, iclass 18, count 0 2006.173.11:49:29.29#ibcon#*before return 0, iclass 18, count 0 2006.173.11:49:29.29#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.11:49:29.29#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.11:49:29.29#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.11:49:29.29#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.11:49:29.29$vck44/va=1,7 2006.173.11:49:29.29#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.11:49:29.29#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.11:49:29.29#ibcon#ireg 11 cls_cnt 2 2006.173.11:49:29.29#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.11:49:29.29#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.11:49:29.29#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.11:49:29.29#ibcon#enter wrdev, iclass 20, count 2 2006.173.11:49:29.29#ibcon#first serial, iclass 20, count 2 2006.173.11:49:29.29#ibcon#enter sib2, iclass 20, count 2 2006.173.11:49:29.29#ibcon#flushed, iclass 20, count 2 2006.173.11:49:29.29#ibcon#about to write, iclass 20, count 2 2006.173.11:49:29.29#ibcon#wrote, iclass 20, count 2 2006.173.11:49:29.29#ibcon#about to read 3, iclass 20, count 2 2006.173.11:49:29.31#ibcon#read 3, iclass 20, count 2 2006.173.11:49:29.31#ibcon#about to read 4, iclass 20, count 2 2006.173.11:49:29.31#ibcon#read 4, iclass 20, count 2 2006.173.11:49:29.31#ibcon#about to read 5, iclass 20, count 2 2006.173.11:49:29.31#ibcon#read 5, iclass 20, count 2 2006.173.11:49:29.31#ibcon#about to read 6, iclass 20, count 2 2006.173.11:49:29.31#ibcon#read 6, iclass 20, count 2 2006.173.11:49:29.31#ibcon#end of sib2, iclass 20, count 2 2006.173.11:49:29.31#ibcon#*mode == 0, iclass 20, count 2 2006.173.11:49:29.31#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.11:49:29.31#ibcon#[25=AT01-07\r\n] 2006.173.11:49:29.31#ibcon#*before write, iclass 20, count 2 2006.173.11:49:29.31#ibcon#enter sib2, iclass 20, count 2 2006.173.11:49:29.31#ibcon#flushed, iclass 20, count 2 2006.173.11:49:29.31#ibcon#about to write, iclass 20, count 2 2006.173.11:49:29.31#ibcon#wrote, iclass 20, count 2 2006.173.11:49:29.31#ibcon#about to read 3, iclass 20, count 2 2006.173.11:49:29.34#ibcon#read 3, iclass 20, count 2 2006.173.11:49:29.34#ibcon#about to read 4, iclass 20, count 2 2006.173.11:49:29.34#ibcon#read 4, iclass 20, count 2 2006.173.11:49:29.34#ibcon#about to read 5, iclass 20, count 2 2006.173.11:49:29.34#ibcon#read 5, iclass 20, count 2 2006.173.11:49:29.34#ibcon#about to read 6, iclass 20, count 2 2006.173.11:49:29.34#ibcon#read 6, iclass 20, count 2 2006.173.11:49:29.34#ibcon#end of sib2, iclass 20, count 2 2006.173.11:49:29.34#ibcon#*after write, iclass 20, count 2 2006.173.11:49:29.34#ibcon#*before return 0, iclass 20, count 2 2006.173.11:49:29.34#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.11:49:29.34#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.11:49:29.34#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.11:49:29.34#ibcon#ireg 7 cls_cnt 0 2006.173.11:49:29.34#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.11:49:29.46#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.11:49:29.46#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.11:49:29.46#ibcon#enter wrdev, iclass 20, count 0 2006.173.11:49:29.46#ibcon#first serial, iclass 20, count 0 2006.173.11:49:29.46#ibcon#enter sib2, iclass 20, count 0 2006.173.11:49:29.46#ibcon#flushed, iclass 20, count 0 2006.173.11:49:29.46#ibcon#about to write, iclass 20, count 0 2006.173.11:49:29.46#ibcon#wrote, iclass 20, count 0 2006.173.11:49:29.46#ibcon#about to read 3, iclass 20, count 0 2006.173.11:49:29.48#ibcon#read 3, iclass 20, count 0 2006.173.11:49:29.48#ibcon#about to read 4, iclass 20, count 0 2006.173.11:49:29.48#ibcon#read 4, iclass 20, count 0 2006.173.11:49:29.48#ibcon#about to read 5, iclass 20, count 0 2006.173.11:49:29.48#ibcon#read 5, iclass 20, count 0 2006.173.11:49:29.48#ibcon#about to read 6, iclass 20, count 0 2006.173.11:49:29.48#ibcon#read 6, iclass 20, count 0 2006.173.11:49:29.48#ibcon#end of sib2, iclass 20, count 0 2006.173.11:49:29.48#ibcon#*mode == 0, iclass 20, count 0 2006.173.11:49:29.48#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.11:49:29.48#ibcon#[25=USB\r\n] 2006.173.11:49:29.48#ibcon#*before write, iclass 20, count 0 2006.173.11:49:29.48#ibcon#enter sib2, iclass 20, count 0 2006.173.11:49:29.48#ibcon#flushed, iclass 20, count 0 2006.173.11:49:29.48#ibcon#about to write, iclass 20, count 0 2006.173.11:49:29.48#ibcon#wrote, iclass 20, count 0 2006.173.11:49:29.48#ibcon#about to read 3, iclass 20, count 0 2006.173.11:49:29.51#ibcon#read 3, iclass 20, count 0 2006.173.11:49:29.51#ibcon#about to read 4, iclass 20, count 0 2006.173.11:49:29.51#ibcon#read 4, iclass 20, count 0 2006.173.11:49:29.51#ibcon#about to read 5, iclass 20, count 0 2006.173.11:49:29.51#ibcon#read 5, iclass 20, count 0 2006.173.11:49:29.51#ibcon#about to read 6, iclass 20, count 0 2006.173.11:49:29.51#ibcon#read 6, iclass 20, count 0 2006.173.11:49:29.51#ibcon#end of sib2, iclass 20, count 0 2006.173.11:49:29.51#ibcon#*after write, iclass 20, count 0 2006.173.11:49:29.51#ibcon#*before return 0, iclass 20, count 0 2006.173.11:49:29.51#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.11:49:29.51#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.11:49:29.51#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.11:49:29.51#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.11:49:29.51$vck44/valo=2,534.99 2006.173.11:49:29.51#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.11:49:29.51#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.11:49:29.51#ibcon#ireg 17 cls_cnt 0 2006.173.11:49:29.51#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.11:49:29.51#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.11:49:29.51#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.11:49:29.51#ibcon#enter wrdev, iclass 22, count 0 2006.173.11:49:29.51#ibcon#first serial, iclass 22, count 0 2006.173.11:49:29.51#ibcon#enter sib2, iclass 22, count 0 2006.173.11:49:29.51#ibcon#flushed, iclass 22, count 0 2006.173.11:49:29.51#ibcon#about to write, iclass 22, count 0 2006.173.11:49:29.51#ibcon#wrote, iclass 22, count 0 2006.173.11:49:29.51#ibcon#about to read 3, iclass 22, count 0 2006.173.11:49:29.53#ibcon#read 3, iclass 22, count 0 2006.173.11:49:29.53#ibcon#about to read 4, iclass 22, count 0 2006.173.11:49:29.53#ibcon#read 4, iclass 22, count 0 2006.173.11:49:29.53#ibcon#about to read 5, iclass 22, count 0 2006.173.11:49:29.53#ibcon#read 5, iclass 22, count 0 2006.173.11:49:29.53#ibcon#about to read 6, iclass 22, count 0 2006.173.11:49:29.53#ibcon#read 6, iclass 22, count 0 2006.173.11:49:29.53#ibcon#end of sib2, iclass 22, count 0 2006.173.11:49:29.53#ibcon#*mode == 0, iclass 22, count 0 2006.173.11:49:29.53#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.11:49:29.53#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.11:49:29.53#ibcon#*before write, iclass 22, count 0 2006.173.11:49:29.53#ibcon#enter sib2, iclass 22, count 0 2006.173.11:49:29.53#ibcon#flushed, iclass 22, count 0 2006.173.11:49:29.53#ibcon#about to write, iclass 22, count 0 2006.173.11:49:29.53#ibcon#wrote, iclass 22, count 0 2006.173.11:49:29.53#ibcon#about to read 3, iclass 22, count 0 2006.173.11:49:29.57#ibcon#read 3, iclass 22, count 0 2006.173.11:49:29.57#ibcon#about to read 4, iclass 22, count 0 2006.173.11:49:29.57#ibcon#read 4, iclass 22, count 0 2006.173.11:49:29.57#ibcon#about to read 5, iclass 22, count 0 2006.173.11:49:29.57#ibcon#read 5, iclass 22, count 0 2006.173.11:49:29.57#ibcon#about to read 6, iclass 22, count 0 2006.173.11:49:29.57#ibcon#read 6, iclass 22, count 0 2006.173.11:49:29.57#ibcon#end of sib2, iclass 22, count 0 2006.173.11:49:29.57#ibcon#*after write, iclass 22, count 0 2006.173.11:49:29.57#ibcon#*before return 0, iclass 22, count 0 2006.173.11:49:29.57#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.11:49:29.57#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.11:49:29.57#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.11:49:29.57#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.11:49:29.57$vck44/va=2,6 2006.173.11:49:29.57#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.11:49:29.57#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.11:49:29.57#ibcon#ireg 11 cls_cnt 2 2006.173.11:49:29.57#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.11:49:29.63#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.11:49:29.63#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.11:49:29.63#ibcon#enter wrdev, iclass 24, count 2 2006.173.11:49:29.63#ibcon#first serial, iclass 24, count 2 2006.173.11:49:29.63#ibcon#enter sib2, iclass 24, count 2 2006.173.11:49:29.63#ibcon#flushed, iclass 24, count 2 2006.173.11:49:29.63#ibcon#about to write, iclass 24, count 2 2006.173.11:49:29.63#ibcon#wrote, iclass 24, count 2 2006.173.11:49:29.63#ibcon#about to read 3, iclass 24, count 2 2006.173.11:49:29.65#ibcon#read 3, iclass 24, count 2 2006.173.11:49:29.65#ibcon#about to read 4, iclass 24, count 2 2006.173.11:49:29.65#ibcon#read 4, iclass 24, count 2 2006.173.11:49:29.65#ibcon#about to read 5, iclass 24, count 2 2006.173.11:49:29.65#ibcon#read 5, iclass 24, count 2 2006.173.11:49:29.65#ibcon#about to read 6, iclass 24, count 2 2006.173.11:49:29.65#ibcon#read 6, iclass 24, count 2 2006.173.11:49:29.65#ibcon#end of sib2, iclass 24, count 2 2006.173.11:49:29.65#ibcon#*mode == 0, iclass 24, count 2 2006.173.11:49:29.65#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.11:49:29.65#ibcon#[25=AT02-06\r\n] 2006.173.11:49:29.65#ibcon#*before write, iclass 24, count 2 2006.173.11:49:29.65#ibcon#enter sib2, iclass 24, count 2 2006.173.11:49:29.65#ibcon#flushed, iclass 24, count 2 2006.173.11:49:29.65#ibcon#about to write, iclass 24, count 2 2006.173.11:49:29.65#ibcon#wrote, iclass 24, count 2 2006.173.11:49:29.65#ibcon#about to read 3, iclass 24, count 2 2006.173.11:49:29.68#ibcon#read 3, iclass 24, count 2 2006.173.11:49:29.68#ibcon#about to read 4, iclass 24, count 2 2006.173.11:49:29.68#ibcon#read 4, iclass 24, count 2 2006.173.11:49:29.68#ibcon#about to read 5, iclass 24, count 2 2006.173.11:49:29.68#ibcon#read 5, iclass 24, count 2 2006.173.11:49:29.68#ibcon#about to read 6, iclass 24, count 2 2006.173.11:49:29.68#ibcon#read 6, iclass 24, count 2 2006.173.11:49:29.68#ibcon#end of sib2, iclass 24, count 2 2006.173.11:49:29.68#ibcon#*after write, iclass 24, count 2 2006.173.11:49:29.68#ibcon#*before return 0, iclass 24, count 2 2006.173.11:49:29.68#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.11:49:29.68#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.11:49:29.68#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.11:49:29.68#ibcon#ireg 7 cls_cnt 0 2006.173.11:49:29.68#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.11:49:29.80#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.11:49:29.80#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.11:49:29.80#ibcon#enter wrdev, iclass 24, count 0 2006.173.11:49:29.80#ibcon#first serial, iclass 24, count 0 2006.173.11:49:29.80#ibcon#enter sib2, iclass 24, count 0 2006.173.11:49:29.80#ibcon#flushed, iclass 24, count 0 2006.173.11:49:29.80#ibcon#about to write, iclass 24, count 0 2006.173.11:49:29.80#ibcon#wrote, iclass 24, count 0 2006.173.11:49:29.80#ibcon#about to read 3, iclass 24, count 0 2006.173.11:49:29.82#ibcon#read 3, iclass 24, count 0 2006.173.11:49:29.82#ibcon#about to read 4, iclass 24, count 0 2006.173.11:49:29.82#ibcon#read 4, iclass 24, count 0 2006.173.11:49:29.82#ibcon#about to read 5, iclass 24, count 0 2006.173.11:49:29.82#ibcon#read 5, iclass 24, count 0 2006.173.11:49:29.82#ibcon#about to read 6, iclass 24, count 0 2006.173.11:49:29.82#ibcon#read 6, iclass 24, count 0 2006.173.11:49:29.82#ibcon#end of sib2, iclass 24, count 0 2006.173.11:49:29.82#ibcon#*mode == 0, iclass 24, count 0 2006.173.11:49:29.82#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.11:49:29.82#ibcon#[25=USB\r\n] 2006.173.11:49:29.82#ibcon#*before write, iclass 24, count 0 2006.173.11:49:29.82#ibcon#enter sib2, iclass 24, count 0 2006.173.11:49:29.82#ibcon#flushed, iclass 24, count 0 2006.173.11:49:29.82#ibcon#about to write, iclass 24, count 0 2006.173.11:49:29.82#ibcon#wrote, iclass 24, count 0 2006.173.11:49:29.82#ibcon#about to read 3, iclass 24, count 0 2006.173.11:49:29.85#ibcon#read 3, iclass 24, count 0 2006.173.11:49:29.85#ibcon#about to read 4, iclass 24, count 0 2006.173.11:49:29.85#ibcon#read 4, iclass 24, count 0 2006.173.11:49:29.85#ibcon#about to read 5, iclass 24, count 0 2006.173.11:49:29.85#ibcon#read 5, iclass 24, count 0 2006.173.11:49:29.85#ibcon#about to read 6, iclass 24, count 0 2006.173.11:49:29.85#ibcon#read 6, iclass 24, count 0 2006.173.11:49:29.85#ibcon#end of sib2, iclass 24, count 0 2006.173.11:49:29.85#ibcon#*after write, iclass 24, count 0 2006.173.11:49:29.85#ibcon#*before return 0, iclass 24, count 0 2006.173.11:49:29.85#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.11:49:29.85#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.11:49:29.85#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.11:49:29.85#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.11:49:29.85$vck44/valo=3,564.99 2006.173.11:49:29.85#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.11:49:29.85#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.11:49:29.85#ibcon#ireg 17 cls_cnt 0 2006.173.11:49:29.85#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.11:49:29.85#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.11:49:29.85#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.11:49:29.85#ibcon#enter wrdev, iclass 26, count 0 2006.173.11:49:29.85#ibcon#first serial, iclass 26, count 0 2006.173.11:49:29.85#ibcon#enter sib2, iclass 26, count 0 2006.173.11:49:29.85#ibcon#flushed, iclass 26, count 0 2006.173.11:49:29.85#ibcon#about to write, iclass 26, count 0 2006.173.11:49:29.85#ibcon#wrote, iclass 26, count 0 2006.173.11:49:29.85#ibcon#about to read 3, iclass 26, count 0 2006.173.11:49:29.87#ibcon#read 3, iclass 26, count 0 2006.173.11:49:29.87#ibcon#about to read 4, iclass 26, count 0 2006.173.11:49:29.87#ibcon#read 4, iclass 26, count 0 2006.173.11:49:29.87#ibcon#about to read 5, iclass 26, count 0 2006.173.11:49:29.87#ibcon#read 5, iclass 26, count 0 2006.173.11:49:29.87#ibcon#about to read 6, iclass 26, count 0 2006.173.11:49:29.87#ibcon#read 6, iclass 26, count 0 2006.173.11:49:29.87#ibcon#end of sib2, iclass 26, count 0 2006.173.11:49:29.87#ibcon#*mode == 0, iclass 26, count 0 2006.173.11:49:29.87#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.11:49:29.87#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.11:49:29.87#ibcon#*before write, iclass 26, count 0 2006.173.11:49:29.87#ibcon#enter sib2, iclass 26, count 0 2006.173.11:49:29.87#ibcon#flushed, iclass 26, count 0 2006.173.11:49:29.87#ibcon#about to write, iclass 26, count 0 2006.173.11:49:29.87#ibcon#wrote, iclass 26, count 0 2006.173.11:49:29.87#ibcon#about to read 3, iclass 26, count 0 2006.173.11:49:29.91#ibcon#read 3, iclass 26, count 0 2006.173.11:49:29.91#ibcon#about to read 4, iclass 26, count 0 2006.173.11:49:29.91#ibcon#read 4, iclass 26, count 0 2006.173.11:49:29.91#ibcon#about to read 5, iclass 26, count 0 2006.173.11:49:29.91#ibcon#read 5, iclass 26, count 0 2006.173.11:49:29.91#ibcon#about to read 6, iclass 26, count 0 2006.173.11:49:29.91#ibcon#read 6, iclass 26, count 0 2006.173.11:49:29.91#ibcon#end of sib2, iclass 26, count 0 2006.173.11:49:29.91#ibcon#*after write, iclass 26, count 0 2006.173.11:49:29.91#ibcon#*before return 0, iclass 26, count 0 2006.173.11:49:29.91#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.11:49:29.91#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.11:49:29.91#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.11:49:29.91#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.11:49:29.91$vck44/va=3,5 2006.173.11:49:29.91#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.11:49:29.91#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.11:49:29.91#ibcon#ireg 11 cls_cnt 2 2006.173.11:49:29.91#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.11:49:29.97#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.11:49:29.97#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.11:49:29.97#ibcon#enter wrdev, iclass 28, count 2 2006.173.11:49:29.97#ibcon#first serial, iclass 28, count 2 2006.173.11:49:29.97#ibcon#enter sib2, iclass 28, count 2 2006.173.11:49:29.97#ibcon#flushed, iclass 28, count 2 2006.173.11:49:29.97#ibcon#about to write, iclass 28, count 2 2006.173.11:49:29.97#ibcon#wrote, iclass 28, count 2 2006.173.11:49:29.97#ibcon#about to read 3, iclass 28, count 2 2006.173.11:49:29.99#ibcon#read 3, iclass 28, count 2 2006.173.11:49:29.99#ibcon#about to read 4, iclass 28, count 2 2006.173.11:49:29.99#ibcon#read 4, iclass 28, count 2 2006.173.11:49:29.99#ibcon#about to read 5, iclass 28, count 2 2006.173.11:49:29.99#ibcon#read 5, iclass 28, count 2 2006.173.11:49:29.99#ibcon#about to read 6, iclass 28, count 2 2006.173.11:49:29.99#ibcon#read 6, iclass 28, count 2 2006.173.11:49:29.99#ibcon#end of sib2, iclass 28, count 2 2006.173.11:49:29.99#ibcon#*mode == 0, iclass 28, count 2 2006.173.11:49:29.99#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.11:49:29.99#ibcon#[25=AT03-05\r\n] 2006.173.11:49:29.99#ibcon#*before write, iclass 28, count 2 2006.173.11:49:29.99#ibcon#enter sib2, iclass 28, count 2 2006.173.11:49:29.99#ibcon#flushed, iclass 28, count 2 2006.173.11:49:29.99#ibcon#about to write, iclass 28, count 2 2006.173.11:49:29.99#ibcon#wrote, iclass 28, count 2 2006.173.11:49:29.99#ibcon#about to read 3, iclass 28, count 2 2006.173.11:49:30.02#ibcon#read 3, iclass 28, count 2 2006.173.11:49:30.02#ibcon#about to read 4, iclass 28, count 2 2006.173.11:49:30.02#ibcon#read 4, iclass 28, count 2 2006.173.11:49:30.02#ibcon#about to read 5, iclass 28, count 2 2006.173.11:49:30.02#ibcon#read 5, iclass 28, count 2 2006.173.11:49:30.02#ibcon#about to read 6, iclass 28, count 2 2006.173.11:49:30.02#ibcon#read 6, iclass 28, count 2 2006.173.11:49:30.02#ibcon#end of sib2, iclass 28, count 2 2006.173.11:49:30.02#ibcon#*after write, iclass 28, count 2 2006.173.11:49:30.02#ibcon#*before return 0, iclass 28, count 2 2006.173.11:49:30.02#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.11:49:30.02#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.11:49:30.02#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.11:49:30.02#ibcon#ireg 7 cls_cnt 0 2006.173.11:49:30.02#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.11:49:30.14#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.11:49:30.14#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.11:49:30.14#ibcon#enter wrdev, iclass 28, count 0 2006.173.11:49:30.14#ibcon#first serial, iclass 28, count 0 2006.173.11:49:30.14#ibcon#enter sib2, iclass 28, count 0 2006.173.11:49:30.14#ibcon#flushed, iclass 28, count 0 2006.173.11:49:30.14#ibcon#about to write, iclass 28, count 0 2006.173.11:49:30.14#ibcon#wrote, iclass 28, count 0 2006.173.11:49:30.14#ibcon#about to read 3, iclass 28, count 0 2006.173.11:49:30.16#ibcon#read 3, iclass 28, count 0 2006.173.11:49:30.16#ibcon#about to read 4, iclass 28, count 0 2006.173.11:49:30.16#ibcon#read 4, iclass 28, count 0 2006.173.11:49:30.16#ibcon#about to read 5, iclass 28, count 0 2006.173.11:49:30.16#ibcon#read 5, iclass 28, count 0 2006.173.11:49:30.16#ibcon#about to read 6, iclass 28, count 0 2006.173.11:49:30.16#ibcon#read 6, iclass 28, count 0 2006.173.11:49:30.16#ibcon#end of sib2, iclass 28, count 0 2006.173.11:49:30.16#ibcon#*mode == 0, iclass 28, count 0 2006.173.11:49:30.16#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.11:49:30.16#ibcon#[25=USB\r\n] 2006.173.11:49:30.16#ibcon#*before write, iclass 28, count 0 2006.173.11:49:30.16#ibcon#enter sib2, iclass 28, count 0 2006.173.11:49:30.16#ibcon#flushed, iclass 28, count 0 2006.173.11:49:30.16#ibcon#about to write, iclass 28, count 0 2006.173.11:49:30.16#ibcon#wrote, iclass 28, count 0 2006.173.11:49:30.16#ibcon#about to read 3, iclass 28, count 0 2006.173.11:49:30.19#ibcon#read 3, iclass 28, count 0 2006.173.11:49:30.19#ibcon#about to read 4, iclass 28, count 0 2006.173.11:49:30.19#ibcon#read 4, iclass 28, count 0 2006.173.11:49:30.19#ibcon#about to read 5, iclass 28, count 0 2006.173.11:49:30.19#ibcon#read 5, iclass 28, count 0 2006.173.11:49:30.19#ibcon#about to read 6, iclass 28, count 0 2006.173.11:49:30.19#ibcon#read 6, iclass 28, count 0 2006.173.11:49:30.19#ibcon#end of sib2, iclass 28, count 0 2006.173.11:49:30.19#ibcon#*after write, iclass 28, count 0 2006.173.11:49:30.19#ibcon#*before return 0, iclass 28, count 0 2006.173.11:49:30.19#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.11:49:30.19#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.11:49:30.19#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.11:49:30.19#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.11:49:30.19$vck44/valo=4,624.99 2006.173.11:49:30.19#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.11:49:30.19#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.11:49:30.19#ibcon#ireg 17 cls_cnt 0 2006.173.11:49:30.19#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.11:49:30.19#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.11:49:30.19#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.11:49:30.19#ibcon#enter wrdev, iclass 30, count 0 2006.173.11:49:30.19#ibcon#first serial, iclass 30, count 0 2006.173.11:49:30.19#ibcon#enter sib2, iclass 30, count 0 2006.173.11:49:30.19#ibcon#flushed, iclass 30, count 0 2006.173.11:49:30.19#ibcon#about to write, iclass 30, count 0 2006.173.11:49:30.19#ibcon#wrote, iclass 30, count 0 2006.173.11:49:30.19#ibcon#about to read 3, iclass 30, count 0 2006.173.11:49:30.21#ibcon#read 3, iclass 30, count 0 2006.173.11:49:30.21#ibcon#about to read 4, iclass 30, count 0 2006.173.11:49:30.21#ibcon#read 4, iclass 30, count 0 2006.173.11:49:30.21#ibcon#about to read 5, iclass 30, count 0 2006.173.11:49:30.21#ibcon#read 5, iclass 30, count 0 2006.173.11:49:30.21#ibcon#about to read 6, iclass 30, count 0 2006.173.11:49:30.21#ibcon#read 6, iclass 30, count 0 2006.173.11:49:30.21#ibcon#end of sib2, iclass 30, count 0 2006.173.11:49:30.21#ibcon#*mode == 0, iclass 30, count 0 2006.173.11:49:30.21#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.11:49:30.21#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.11:49:30.21#ibcon#*before write, iclass 30, count 0 2006.173.11:49:30.21#ibcon#enter sib2, iclass 30, count 0 2006.173.11:49:30.21#ibcon#flushed, iclass 30, count 0 2006.173.11:49:30.21#ibcon#about to write, iclass 30, count 0 2006.173.11:49:30.21#ibcon#wrote, iclass 30, count 0 2006.173.11:49:30.21#ibcon#about to read 3, iclass 30, count 0 2006.173.11:49:30.25#ibcon#read 3, iclass 30, count 0 2006.173.11:49:30.25#ibcon#about to read 4, iclass 30, count 0 2006.173.11:49:30.25#ibcon#read 4, iclass 30, count 0 2006.173.11:49:30.25#ibcon#about to read 5, iclass 30, count 0 2006.173.11:49:30.25#ibcon#read 5, iclass 30, count 0 2006.173.11:49:30.25#ibcon#about to read 6, iclass 30, count 0 2006.173.11:49:30.25#ibcon#read 6, iclass 30, count 0 2006.173.11:49:30.25#ibcon#end of sib2, iclass 30, count 0 2006.173.11:49:30.25#ibcon#*after write, iclass 30, count 0 2006.173.11:49:30.25#ibcon#*before return 0, iclass 30, count 0 2006.173.11:49:30.25#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.11:49:30.25#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.11:49:30.25#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.11:49:30.25#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.11:49:30.25$vck44/va=4,6 2006.173.11:49:30.25#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.173.11:49:30.25#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.173.11:49:30.25#ibcon#ireg 11 cls_cnt 2 2006.173.11:49:30.25#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.11:49:30.31#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.11:49:30.31#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.11:49:30.31#ibcon#enter wrdev, iclass 32, count 2 2006.173.11:49:30.31#ibcon#first serial, iclass 32, count 2 2006.173.11:49:30.31#ibcon#enter sib2, iclass 32, count 2 2006.173.11:49:30.31#ibcon#flushed, iclass 32, count 2 2006.173.11:49:30.31#ibcon#about to write, iclass 32, count 2 2006.173.11:49:30.31#ibcon#wrote, iclass 32, count 2 2006.173.11:49:30.31#ibcon#about to read 3, iclass 32, count 2 2006.173.11:49:30.33#ibcon#read 3, iclass 32, count 2 2006.173.11:49:30.33#ibcon#about to read 4, iclass 32, count 2 2006.173.11:49:30.33#ibcon#read 4, iclass 32, count 2 2006.173.11:49:30.33#ibcon#about to read 5, iclass 32, count 2 2006.173.11:49:30.33#ibcon#read 5, iclass 32, count 2 2006.173.11:49:30.33#ibcon#about to read 6, iclass 32, count 2 2006.173.11:49:30.33#ibcon#read 6, iclass 32, count 2 2006.173.11:49:30.33#ibcon#end of sib2, iclass 32, count 2 2006.173.11:49:30.33#ibcon#*mode == 0, iclass 32, count 2 2006.173.11:49:30.33#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.173.11:49:30.33#ibcon#[25=AT04-06\r\n] 2006.173.11:49:30.33#ibcon#*before write, iclass 32, count 2 2006.173.11:49:30.33#ibcon#enter sib2, iclass 32, count 2 2006.173.11:49:30.33#ibcon#flushed, iclass 32, count 2 2006.173.11:49:30.33#ibcon#about to write, iclass 32, count 2 2006.173.11:49:30.33#ibcon#wrote, iclass 32, count 2 2006.173.11:49:30.33#ibcon#about to read 3, iclass 32, count 2 2006.173.11:49:30.36#ibcon#read 3, iclass 32, count 2 2006.173.11:49:30.36#ibcon#about to read 4, iclass 32, count 2 2006.173.11:49:30.36#ibcon#read 4, iclass 32, count 2 2006.173.11:49:30.36#ibcon#about to read 5, iclass 32, count 2 2006.173.11:49:30.36#ibcon#read 5, iclass 32, count 2 2006.173.11:49:30.36#ibcon#about to read 6, iclass 32, count 2 2006.173.11:49:30.36#ibcon#read 6, iclass 32, count 2 2006.173.11:49:30.36#ibcon#end of sib2, iclass 32, count 2 2006.173.11:49:30.36#ibcon#*after write, iclass 32, count 2 2006.173.11:49:30.36#ibcon#*before return 0, iclass 32, count 2 2006.173.11:49:30.36#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.11:49:30.36#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.173.11:49:30.36#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.173.11:49:30.36#ibcon#ireg 7 cls_cnt 0 2006.173.11:49:30.36#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.11:49:30.48#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.11:49:30.48#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.11:49:30.48#ibcon#enter wrdev, iclass 32, count 0 2006.173.11:49:30.48#ibcon#first serial, iclass 32, count 0 2006.173.11:49:30.48#ibcon#enter sib2, iclass 32, count 0 2006.173.11:49:30.48#ibcon#flushed, iclass 32, count 0 2006.173.11:49:30.48#ibcon#about to write, iclass 32, count 0 2006.173.11:49:30.48#ibcon#wrote, iclass 32, count 0 2006.173.11:49:30.48#ibcon#about to read 3, iclass 32, count 0 2006.173.11:49:30.50#ibcon#read 3, iclass 32, count 0 2006.173.11:49:30.50#ibcon#about to read 4, iclass 32, count 0 2006.173.11:49:30.50#ibcon#read 4, iclass 32, count 0 2006.173.11:49:30.50#ibcon#about to read 5, iclass 32, count 0 2006.173.11:49:30.50#ibcon#read 5, iclass 32, count 0 2006.173.11:49:30.50#ibcon#about to read 6, iclass 32, count 0 2006.173.11:49:30.50#ibcon#read 6, iclass 32, count 0 2006.173.11:49:30.50#ibcon#end of sib2, iclass 32, count 0 2006.173.11:49:30.50#ibcon#*mode == 0, iclass 32, count 0 2006.173.11:49:30.50#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.11:49:30.50#ibcon#[25=USB\r\n] 2006.173.11:49:30.50#ibcon#*before write, iclass 32, count 0 2006.173.11:49:30.50#ibcon#enter sib2, iclass 32, count 0 2006.173.11:49:30.50#ibcon#flushed, iclass 32, count 0 2006.173.11:49:30.50#ibcon#about to write, iclass 32, count 0 2006.173.11:49:30.50#ibcon#wrote, iclass 32, count 0 2006.173.11:49:30.50#ibcon#about to read 3, iclass 32, count 0 2006.173.11:49:30.53#ibcon#read 3, iclass 32, count 0 2006.173.11:49:30.53#ibcon#about to read 4, iclass 32, count 0 2006.173.11:49:30.53#ibcon#read 4, iclass 32, count 0 2006.173.11:49:30.53#ibcon#about to read 5, iclass 32, count 0 2006.173.11:49:30.53#ibcon#read 5, iclass 32, count 0 2006.173.11:49:30.53#ibcon#about to read 6, iclass 32, count 0 2006.173.11:49:30.53#ibcon#read 6, iclass 32, count 0 2006.173.11:49:30.53#ibcon#end of sib2, iclass 32, count 0 2006.173.11:49:30.53#ibcon#*after write, iclass 32, count 0 2006.173.11:49:30.53#ibcon#*before return 0, iclass 32, count 0 2006.173.11:49:30.53#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.11:49:30.53#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.173.11:49:30.53#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.11:49:30.53#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.11:49:30.53$vck44/valo=5,734.99 2006.173.11:49:30.53#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.11:49:30.53#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.11:49:30.53#ibcon#ireg 17 cls_cnt 0 2006.173.11:49:30.53#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.11:49:30.53#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.11:49:30.53#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.11:49:30.53#ibcon#enter wrdev, iclass 34, count 0 2006.173.11:49:30.53#ibcon#first serial, iclass 34, count 0 2006.173.11:49:30.53#ibcon#enter sib2, iclass 34, count 0 2006.173.11:49:30.53#ibcon#flushed, iclass 34, count 0 2006.173.11:49:30.53#ibcon#about to write, iclass 34, count 0 2006.173.11:49:30.53#ibcon#wrote, iclass 34, count 0 2006.173.11:49:30.53#ibcon#about to read 3, iclass 34, count 0 2006.173.11:49:30.55#ibcon#read 3, iclass 34, count 0 2006.173.11:49:30.55#ibcon#about to read 4, iclass 34, count 0 2006.173.11:49:30.55#ibcon#read 4, iclass 34, count 0 2006.173.11:49:30.55#ibcon#about to read 5, iclass 34, count 0 2006.173.11:49:30.55#ibcon#read 5, iclass 34, count 0 2006.173.11:49:30.55#ibcon#about to read 6, iclass 34, count 0 2006.173.11:49:30.55#ibcon#read 6, iclass 34, count 0 2006.173.11:49:30.55#ibcon#end of sib2, iclass 34, count 0 2006.173.11:49:30.55#ibcon#*mode == 0, iclass 34, count 0 2006.173.11:49:30.55#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.11:49:30.55#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.11:49:30.55#ibcon#*before write, iclass 34, count 0 2006.173.11:49:30.55#ibcon#enter sib2, iclass 34, count 0 2006.173.11:49:30.55#ibcon#flushed, iclass 34, count 0 2006.173.11:49:30.55#ibcon#about to write, iclass 34, count 0 2006.173.11:49:30.55#ibcon#wrote, iclass 34, count 0 2006.173.11:49:30.55#ibcon#about to read 3, iclass 34, count 0 2006.173.11:49:30.59#ibcon#read 3, iclass 34, count 0 2006.173.11:49:30.59#ibcon#about to read 4, iclass 34, count 0 2006.173.11:49:30.59#ibcon#read 4, iclass 34, count 0 2006.173.11:49:30.59#ibcon#about to read 5, iclass 34, count 0 2006.173.11:49:30.59#ibcon#read 5, iclass 34, count 0 2006.173.11:49:30.59#ibcon#about to read 6, iclass 34, count 0 2006.173.11:49:30.59#ibcon#read 6, iclass 34, count 0 2006.173.11:49:30.59#ibcon#end of sib2, iclass 34, count 0 2006.173.11:49:30.59#ibcon#*after write, iclass 34, count 0 2006.173.11:49:30.59#ibcon#*before return 0, iclass 34, count 0 2006.173.11:49:30.59#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.11:49:30.59#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.11:49:30.59#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.11:49:30.59#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.11:49:30.59$vck44/va=5,4 2006.173.11:49:30.59#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.11:49:30.59#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.11:49:30.59#ibcon#ireg 11 cls_cnt 2 2006.173.11:49:30.59#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.11:49:30.65#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.11:49:30.65#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.11:49:30.65#ibcon#enter wrdev, iclass 36, count 2 2006.173.11:49:30.65#ibcon#first serial, iclass 36, count 2 2006.173.11:49:30.65#ibcon#enter sib2, iclass 36, count 2 2006.173.11:49:30.65#ibcon#flushed, iclass 36, count 2 2006.173.11:49:30.65#ibcon#about to write, iclass 36, count 2 2006.173.11:49:30.65#ibcon#wrote, iclass 36, count 2 2006.173.11:49:30.65#ibcon#about to read 3, iclass 36, count 2 2006.173.11:49:30.67#ibcon#read 3, iclass 36, count 2 2006.173.11:49:30.67#ibcon#about to read 4, iclass 36, count 2 2006.173.11:49:30.67#ibcon#read 4, iclass 36, count 2 2006.173.11:49:30.67#ibcon#about to read 5, iclass 36, count 2 2006.173.11:49:30.67#ibcon#read 5, iclass 36, count 2 2006.173.11:49:30.67#ibcon#about to read 6, iclass 36, count 2 2006.173.11:49:30.67#ibcon#read 6, iclass 36, count 2 2006.173.11:49:30.67#ibcon#end of sib2, iclass 36, count 2 2006.173.11:49:30.67#ibcon#*mode == 0, iclass 36, count 2 2006.173.11:49:30.67#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.11:49:30.67#ibcon#[25=AT05-04\r\n] 2006.173.11:49:30.67#ibcon#*before write, iclass 36, count 2 2006.173.11:49:30.67#ibcon#enter sib2, iclass 36, count 2 2006.173.11:49:30.67#ibcon#flushed, iclass 36, count 2 2006.173.11:49:30.67#ibcon#about to write, iclass 36, count 2 2006.173.11:49:30.67#ibcon#wrote, iclass 36, count 2 2006.173.11:49:30.67#ibcon#about to read 3, iclass 36, count 2 2006.173.11:49:30.70#ibcon#read 3, iclass 36, count 2 2006.173.11:49:30.70#ibcon#about to read 4, iclass 36, count 2 2006.173.11:49:30.70#ibcon#read 4, iclass 36, count 2 2006.173.11:49:30.70#ibcon#about to read 5, iclass 36, count 2 2006.173.11:49:30.70#ibcon#read 5, iclass 36, count 2 2006.173.11:49:30.70#ibcon#about to read 6, iclass 36, count 2 2006.173.11:49:30.70#ibcon#read 6, iclass 36, count 2 2006.173.11:49:30.70#ibcon#end of sib2, iclass 36, count 2 2006.173.11:49:30.70#ibcon#*after write, iclass 36, count 2 2006.173.11:49:30.70#ibcon#*before return 0, iclass 36, count 2 2006.173.11:49:30.70#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.11:49:30.70#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.11:49:30.70#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.11:49:30.70#ibcon#ireg 7 cls_cnt 0 2006.173.11:49:30.70#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.11:49:30.82#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.11:49:30.82#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.11:49:30.82#ibcon#enter wrdev, iclass 36, count 0 2006.173.11:49:30.82#ibcon#first serial, iclass 36, count 0 2006.173.11:49:30.82#ibcon#enter sib2, iclass 36, count 0 2006.173.11:49:30.82#ibcon#flushed, iclass 36, count 0 2006.173.11:49:30.82#ibcon#about to write, iclass 36, count 0 2006.173.11:49:30.82#ibcon#wrote, iclass 36, count 0 2006.173.11:49:30.82#ibcon#about to read 3, iclass 36, count 0 2006.173.11:49:30.84#ibcon#read 3, iclass 36, count 0 2006.173.11:49:30.84#ibcon#about to read 4, iclass 36, count 0 2006.173.11:49:30.84#ibcon#read 4, iclass 36, count 0 2006.173.11:49:30.84#ibcon#about to read 5, iclass 36, count 0 2006.173.11:49:30.84#ibcon#read 5, iclass 36, count 0 2006.173.11:49:30.84#ibcon#about to read 6, iclass 36, count 0 2006.173.11:49:30.84#ibcon#read 6, iclass 36, count 0 2006.173.11:49:30.84#ibcon#end of sib2, iclass 36, count 0 2006.173.11:49:30.84#ibcon#*mode == 0, iclass 36, count 0 2006.173.11:49:30.84#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.11:49:30.84#ibcon#[25=USB\r\n] 2006.173.11:49:30.84#ibcon#*before write, iclass 36, count 0 2006.173.11:49:30.84#ibcon#enter sib2, iclass 36, count 0 2006.173.11:49:30.84#ibcon#flushed, iclass 36, count 0 2006.173.11:49:30.84#ibcon#about to write, iclass 36, count 0 2006.173.11:49:30.84#ibcon#wrote, iclass 36, count 0 2006.173.11:49:30.84#ibcon#about to read 3, iclass 36, count 0 2006.173.11:49:30.87#ibcon#read 3, iclass 36, count 0 2006.173.11:49:30.87#ibcon#about to read 4, iclass 36, count 0 2006.173.11:49:30.87#ibcon#read 4, iclass 36, count 0 2006.173.11:49:30.87#ibcon#about to read 5, iclass 36, count 0 2006.173.11:49:30.87#ibcon#read 5, iclass 36, count 0 2006.173.11:49:30.87#ibcon#about to read 6, iclass 36, count 0 2006.173.11:49:30.87#ibcon#read 6, iclass 36, count 0 2006.173.11:49:30.87#ibcon#end of sib2, iclass 36, count 0 2006.173.11:49:30.87#ibcon#*after write, iclass 36, count 0 2006.173.11:49:30.87#ibcon#*before return 0, iclass 36, count 0 2006.173.11:49:30.87#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.11:49:30.87#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.11:49:30.87#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.11:49:30.87#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.11:49:30.87$vck44/valo=6,814.99 2006.173.11:49:30.87#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.11:49:30.87#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.11:49:30.87#ibcon#ireg 17 cls_cnt 0 2006.173.11:49:30.87#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.11:49:30.87#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.11:49:30.87#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.11:49:30.87#ibcon#enter wrdev, iclass 38, count 0 2006.173.11:49:30.87#ibcon#first serial, iclass 38, count 0 2006.173.11:49:30.87#ibcon#enter sib2, iclass 38, count 0 2006.173.11:49:30.87#ibcon#flushed, iclass 38, count 0 2006.173.11:49:30.87#ibcon#about to write, iclass 38, count 0 2006.173.11:49:30.87#ibcon#wrote, iclass 38, count 0 2006.173.11:49:30.87#ibcon#about to read 3, iclass 38, count 0 2006.173.11:49:30.89#ibcon#read 3, iclass 38, count 0 2006.173.11:49:30.89#ibcon#about to read 4, iclass 38, count 0 2006.173.11:49:30.89#ibcon#read 4, iclass 38, count 0 2006.173.11:49:30.89#ibcon#about to read 5, iclass 38, count 0 2006.173.11:49:30.89#ibcon#read 5, iclass 38, count 0 2006.173.11:49:30.89#ibcon#about to read 6, iclass 38, count 0 2006.173.11:49:30.89#ibcon#read 6, iclass 38, count 0 2006.173.11:49:30.89#ibcon#end of sib2, iclass 38, count 0 2006.173.11:49:30.89#ibcon#*mode == 0, iclass 38, count 0 2006.173.11:49:30.89#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.11:49:30.89#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.11:49:30.89#ibcon#*before write, iclass 38, count 0 2006.173.11:49:30.89#ibcon#enter sib2, iclass 38, count 0 2006.173.11:49:30.89#ibcon#flushed, iclass 38, count 0 2006.173.11:49:30.89#ibcon#about to write, iclass 38, count 0 2006.173.11:49:30.89#ibcon#wrote, iclass 38, count 0 2006.173.11:49:30.89#ibcon#about to read 3, iclass 38, count 0 2006.173.11:49:30.93#ibcon#read 3, iclass 38, count 0 2006.173.11:49:30.93#ibcon#about to read 4, iclass 38, count 0 2006.173.11:49:30.93#ibcon#read 4, iclass 38, count 0 2006.173.11:49:30.93#ibcon#about to read 5, iclass 38, count 0 2006.173.11:49:30.93#ibcon#read 5, iclass 38, count 0 2006.173.11:49:30.93#ibcon#about to read 6, iclass 38, count 0 2006.173.11:49:30.93#ibcon#read 6, iclass 38, count 0 2006.173.11:49:30.93#ibcon#end of sib2, iclass 38, count 0 2006.173.11:49:30.93#ibcon#*after write, iclass 38, count 0 2006.173.11:49:30.93#ibcon#*before return 0, iclass 38, count 0 2006.173.11:49:30.93#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.11:49:30.93#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.11:49:30.93#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.11:49:30.93#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.11:49:30.93$vck44/va=6,3 2006.173.11:49:30.93#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.11:49:30.93#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.11:49:30.93#ibcon#ireg 11 cls_cnt 2 2006.173.11:49:30.93#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.11:49:30.99#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.11:49:30.99#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.11:49:30.99#ibcon#enter wrdev, iclass 40, count 2 2006.173.11:49:30.99#ibcon#first serial, iclass 40, count 2 2006.173.11:49:30.99#ibcon#enter sib2, iclass 40, count 2 2006.173.11:49:30.99#ibcon#flushed, iclass 40, count 2 2006.173.11:49:30.99#ibcon#about to write, iclass 40, count 2 2006.173.11:49:30.99#ibcon#wrote, iclass 40, count 2 2006.173.11:49:30.99#ibcon#about to read 3, iclass 40, count 2 2006.173.11:49:31.01#ibcon#read 3, iclass 40, count 2 2006.173.11:49:31.01#ibcon#about to read 4, iclass 40, count 2 2006.173.11:49:31.01#ibcon#read 4, iclass 40, count 2 2006.173.11:49:31.01#ibcon#about to read 5, iclass 40, count 2 2006.173.11:49:31.01#ibcon#read 5, iclass 40, count 2 2006.173.11:49:31.01#ibcon#about to read 6, iclass 40, count 2 2006.173.11:49:31.01#ibcon#read 6, iclass 40, count 2 2006.173.11:49:31.01#ibcon#end of sib2, iclass 40, count 2 2006.173.11:49:31.01#ibcon#*mode == 0, iclass 40, count 2 2006.173.11:49:31.01#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.11:49:31.01#ibcon#[25=AT06-03\r\n] 2006.173.11:49:31.01#ibcon#*before write, iclass 40, count 2 2006.173.11:49:31.01#ibcon#enter sib2, iclass 40, count 2 2006.173.11:49:31.01#ibcon#flushed, iclass 40, count 2 2006.173.11:49:31.01#ibcon#about to write, iclass 40, count 2 2006.173.11:49:31.01#ibcon#wrote, iclass 40, count 2 2006.173.11:49:31.01#ibcon#about to read 3, iclass 40, count 2 2006.173.11:49:31.04#ibcon#read 3, iclass 40, count 2 2006.173.11:49:31.04#ibcon#about to read 4, iclass 40, count 2 2006.173.11:49:31.04#ibcon#read 4, iclass 40, count 2 2006.173.11:49:31.04#ibcon#about to read 5, iclass 40, count 2 2006.173.11:49:31.04#ibcon#read 5, iclass 40, count 2 2006.173.11:49:31.04#ibcon#about to read 6, iclass 40, count 2 2006.173.11:49:31.04#ibcon#read 6, iclass 40, count 2 2006.173.11:49:31.04#ibcon#end of sib2, iclass 40, count 2 2006.173.11:49:31.04#ibcon#*after write, iclass 40, count 2 2006.173.11:49:31.04#ibcon#*before return 0, iclass 40, count 2 2006.173.11:49:31.04#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.11:49:31.04#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.11:49:31.04#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.11:49:31.04#ibcon#ireg 7 cls_cnt 0 2006.173.11:49:31.04#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.11:49:31.16#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.11:49:31.16#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.11:49:31.16#ibcon#enter wrdev, iclass 40, count 0 2006.173.11:49:31.16#ibcon#first serial, iclass 40, count 0 2006.173.11:49:31.16#ibcon#enter sib2, iclass 40, count 0 2006.173.11:49:31.16#ibcon#flushed, iclass 40, count 0 2006.173.11:49:31.16#ibcon#about to write, iclass 40, count 0 2006.173.11:49:31.16#ibcon#wrote, iclass 40, count 0 2006.173.11:49:31.16#ibcon#about to read 3, iclass 40, count 0 2006.173.11:49:31.18#ibcon#read 3, iclass 40, count 0 2006.173.11:49:31.18#ibcon#about to read 4, iclass 40, count 0 2006.173.11:49:31.18#ibcon#read 4, iclass 40, count 0 2006.173.11:49:31.18#ibcon#about to read 5, iclass 40, count 0 2006.173.11:49:31.18#ibcon#read 5, iclass 40, count 0 2006.173.11:49:31.18#ibcon#about to read 6, iclass 40, count 0 2006.173.11:49:31.18#ibcon#read 6, iclass 40, count 0 2006.173.11:49:31.18#ibcon#end of sib2, iclass 40, count 0 2006.173.11:49:31.18#ibcon#*mode == 0, iclass 40, count 0 2006.173.11:49:31.18#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.11:49:31.18#ibcon#[25=USB\r\n] 2006.173.11:49:31.18#ibcon#*before write, iclass 40, count 0 2006.173.11:49:31.18#ibcon#enter sib2, iclass 40, count 0 2006.173.11:49:31.18#ibcon#flushed, iclass 40, count 0 2006.173.11:49:31.18#ibcon#about to write, iclass 40, count 0 2006.173.11:49:31.18#ibcon#wrote, iclass 40, count 0 2006.173.11:49:31.18#ibcon#about to read 3, iclass 40, count 0 2006.173.11:49:31.21#ibcon#read 3, iclass 40, count 0 2006.173.11:49:31.21#ibcon#about to read 4, iclass 40, count 0 2006.173.11:49:31.21#ibcon#read 4, iclass 40, count 0 2006.173.11:49:31.21#ibcon#about to read 5, iclass 40, count 0 2006.173.11:49:31.21#ibcon#read 5, iclass 40, count 0 2006.173.11:49:31.21#ibcon#about to read 6, iclass 40, count 0 2006.173.11:49:31.21#ibcon#read 6, iclass 40, count 0 2006.173.11:49:31.21#ibcon#end of sib2, iclass 40, count 0 2006.173.11:49:31.21#ibcon#*after write, iclass 40, count 0 2006.173.11:49:31.21#ibcon#*before return 0, iclass 40, count 0 2006.173.11:49:31.21#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.11:49:31.21#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.11:49:31.21#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.11:49:31.21#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.11:49:31.21$vck44/valo=7,864.99 2006.173.11:49:31.21#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.11:49:31.21#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.11:49:31.21#ibcon#ireg 17 cls_cnt 0 2006.173.11:49:31.21#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.11:49:31.21#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.11:49:31.21#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.11:49:31.21#ibcon#enter wrdev, iclass 4, count 0 2006.173.11:49:31.21#ibcon#first serial, iclass 4, count 0 2006.173.11:49:31.21#ibcon#enter sib2, iclass 4, count 0 2006.173.11:49:31.21#ibcon#flushed, iclass 4, count 0 2006.173.11:49:31.21#ibcon#about to write, iclass 4, count 0 2006.173.11:49:31.21#ibcon#wrote, iclass 4, count 0 2006.173.11:49:31.21#ibcon#about to read 3, iclass 4, count 0 2006.173.11:49:31.23#ibcon#read 3, iclass 4, count 0 2006.173.11:49:31.23#ibcon#about to read 4, iclass 4, count 0 2006.173.11:49:31.23#ibcon#read 4, iclass 4, count 0 2006.173.11:49:31.23#ibcon#about to read 5, iclass 4, count 0 2006.173.11:49:31.23#ibcon#read 5, iclass 4, count 0 2006.173.11:49:31.23#ibcon#about to read 6, iclass 4, count 0 2006.173.11:49:31.23#ibcon#read 6, iclass 4, count 0 2006.173.11:49:31.23#ibcon#end of sib2, iclass 4, count 0 2006.173.11:49:31.23#ibcon#*mode == 0, iclass 4, count 0 2006.173.11:49:31.23#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.11:49:31.23#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.11:49:31.23#ibcon#*before write, iclass 4, count 0 2006.173.11:49:31.23#ibcon#enter sib2, iclass 4, count 0 2006.173.11:49:31.23#ibcon#flushed, iclass 4, count 0 2006.173.11:49:31.23#ibcon#about to write, iclass 4, count 0 2006.173.11:49:31.23#ibcon#wrote, iclass 4, count 0 2006.173.11:49:31.23#ibcon#about to read 3, iclass 4, count 0 2006.173.11:49:31.27#ibcon#read 3, iclass 4, count 0 2006.173.11:49:31.27#ibcon#about to read 4, iclass 4, count 0 2006.173.11:49:31.27#ibcon#read 4, iclass 4, count 0 2006.173.11:49:31.27#ibcon#about to read 5, iclass 4, count 0 2006.173.11:49:31.27#ibcon#read 5, iclass 4, count 0 2006.173.11:49:31.27#ibcon#about to read 6, iclass 4, count 0 2006.173.11:49:31.27#ibcon#read 6, iclass 4, count 0 2006.173.11:49:31.27#ibcon#end of sib2, iclass 4, count 0 2006.173.11:49:31.27#ibcon#*after write, iclass 4, count 0 2006.173.11:49:31.27#ibcon#*before return 0, iclass 4, count 0 2006.173.11:49:31.27#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.11:49:31.27#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.11:49:31.27#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.11:49:31.27#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.11:49:31.27$vck44/va=7,4 2006.173.11:49:31.27#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.11:49:31.27#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.11:49:31.27#ibcon#ireg 11 cls_cnt 2 2006.173.11:49:31.27#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.11:49:31.33#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.11:49:31.33#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.11:49:31.33#ibcon#enter wrdev, iclass 6, count 2 2006.173.11:49:31.33#ibcon#first serial, iclass 6, count 2 2006.173.11:49:31.33#ibcon#enter sib2, iclass 6, count 2 2006.173.11:49:31.33#ibcon#flushed, iclass 6, count 2 2006.173.11:49:31.33#ibcon#about to write, iclass 6, count 2 2006.173.11:49:31.33#ibcon#wrote, iclass 6, count 2 2006.173.11:49:31.33#ibcon#about to read 3, iclass 6, count 2 2006.173.11:49:31.35#ibcon#read 3, iclass 6, count 2 2006.173.11:49:31.35#ibcon#about to read 4, iclass 6, count 2 2006.173.11:49:31.35#ibcon#read 4, iclass 6, count 2 2006.173.11:49:31.35#ibcon#about to read 5, iclass 6, count 2 2006.173.11:49:31.35#ibcon#read 5, iclass 6, count 2 2006.173.11:49:31.35#ibcon#about to read 6, iclass 6, count 2 2006.173.11:49:31.35#ibcon#read 6, iclass 6, count 2 2006.173.11:49:31.35#ibcon#end of sib2, iclass 6, count 2 2006.173.11:49:31.35#ibcon#*mode == 0, iclass 6, count 2 2006.173.11:49:31.35#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.11:49:31.35#ibcon#[25=AT07-04\r\n] 2006.173.11:49:31.35#ibcon#*before write, iclass 6, count 2 2006.173.11:49:31.35#ibcon#enter sib2, iclass 6, count 2 2006.173.11:49:31.35#ibcon#flushed, iclass 6, count 2 2006.173.11:49:31.35#ibcon#about to write, iclass 6, count 2 2006.173.11:49:31.35#ibcon#wrote, iclass 6, count 2 2006.173.11:49:31.35#ibcon#about to read 3, iclass 6, count 2 2006.173.11:49:31.38#ibcon#read 3, iclass 6, count 2 2006.173.11:49:31.38#ibcon#about to read 4, iclass 6, count 2 2006.173.11:49:31.38#ibcon#read 4, iclass 6, count 2 2006.173.11:49:31.38#ibcon#about to read 5, iclass 6, count 2 2006.173.11:49:31.38#ibcon#read 5, iclass 6, count 2 2006.173.11:49:31.38#ibcon#about to read 6, iclass 6, count 2 2006.173.11:49:31.38#ibcon#read 6, iclass 6, count 2 2006.173.11:49:31.38#ibcon#end of sib2, iclass 6, count 2 2006.173.11:49:31.38#ibcon#*after write, iclass 6, count 2 2006.173.11:49:31.38#ibcon#*before return 0, iclass 6, count 2 2006.173.11:49:31.38#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.11:49:31.38#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.11:49:31.38#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.11:49:31.38#ibcon#ireg 7 cls_cnt 0 2006.173.11:49:31.38#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.11:49:31.50#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.11:49:31.50#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.11:49:31.50#ibcon#enter wrdev, iclass 6, count 0 2006.173.11:49:31.50#ibcon#first serial, iclass 6, count 0 2006.173.11:49:31.50#ibcon#enter sib2, iclass 6, count 0 2006.173.11:49:31.50#ibcon#flushed, iclass 6, count 0 2006.173.11:49:31.50#ibcon#about to write, iclass 6, count 0 2006.173.11:49:31.50#ibcon#wrote, iclass 6, count 0 2006.173.11:49:31.50#ibcon#about to read 3, iclass 6, count 0 2006.173.11:49:31.52#ibcon#read 3, iclass 6, count 0 2006.173.11:49:31.52#ibcon#about to read 4, iclass 6, count 0 2006.173.11:49:31.52#ibcon#read 4, iclass 6, count 0 2006.173.11:49:31.52#ibcon#about to read 5, iclass 6, count 0 2006.173.11:49:31.52#ibcon#read 5, iclass 6, count 0 2006.173.11:49:31.52#ibcon#about to read 6, iclass 6, count 0 2006.173.11:49:31.52#ibcon#read 6, iclass 6, count 0 2006.173.11:49:31.52#ibcon#end of sib2, iclass 6, count 0 2006.173.11:49:31.52#ibcon#*mode == 0, iclass 6, count 0 2006.173.11:49:31.52#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.11:49:31.52#ibcon#[25=USB\r\n] 2006.173.11:49:31.52#ibcon#*before write, iclass 6, count 0 2006.173.11:49:31.52#ibcon#enter sib2, iclass 6, count 0 2006.173.11:49:31.52#ibcon#flushed, iclass 6, count 0 2006.173.11:49:31.52#ibcon#about to write, iclass 6, count 0 2006.173.11:49:31.52#ibcon#wrote, iclass 6, count 0 2006.173.11:49:31.52#ibcon#about to read 3, iclass 6, count 0 2006.173.11:49:31.55#ibcon#read 3, iclass 6, count 0 2006.173.11:49:31.55#ibcon#about to read 4, iclass 6, count 0 2006.173.11:49:31.55#ibcon#read 4, iclass 6, count 0 2006.173.11:49:31.55#ibcon#about to read 5, iclass 6, count 0 2006.173.11:49:31.55#ibcon#read 5, iclass 6, count 0 2006.173.11:49:31.55#ibcon#about to read 6, iclass 6, count 0 2006.173.11:49:31.55#ibcon#read 6, iclass 6, count 0 2006.173.11:49:31.55#ibcon#end of sib2, iclass 6, count 0 2006.173.11:49:31.55#ibcon#*after write, iclass 6, count 0 2006.173.11:49:31.55#ibcon#*before return 0, iclass 6, count 0 2006.173.11:49:31.55#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.11:49:31.55#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.11:49:31.55#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.11:49:31.55#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.11:49:31.55$vck44/valo=8,884.99 2006.173.11:49:31.55#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.11:49:31.55#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.11:49:31.55#ibcon#ireg 17 cls_cnt 0 2006.173.11:49:31.55#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.11:49:31.55#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.11:49:31.55#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.11:49:31.55#ibcon#enter wrdev, iclass 10, count 0 2006.173.11:49:31.55#ibcon#first serial, iclass 10, count 0 2006.173.11:49:31.55#ibcon#enter sib2, iclass 10, count 0 2006.173.11:49:31.55#ibcon#flushed, iclass 10, count 0 2006.173.11:49:31.55#ibcon#about to write, iclass 10, count 0 2006.173.11:49:31.55#ibcon#wrote, iclass 10, count 0 2006.173.11:49:31.55#ibcon#about to read 3, iclass 10, count 0 2006.173.11:49:31.57#ibcon#read 3, iclass 10, count 0 2006.173.11:49:31.57#ibcon#about to read 4, iclass 10, count 0 2006.173.11:49:31.57#ibcon#read 4, iclass 10, count 0 2006.173.11:49:31.57#ibcon#about to read 5, iclass 10, count 0 2006.173.11:49:31.57#ibcon#read 5, iclass 10, count 0 2006.173.11:49:31.57#ibcon#about to read 6, iclass 10, count 0 2006.173.11:49:31.57#ibcon#read 6, iclass 10, count 0 2006.173.11:49:31.57#ibcon#end of sib2, iclass 10, count 0 2006.173.11:49:31.57#ibcon#*mode == 0, iclass 10, count 0 2006.173.11:49:31.57#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.11:49:31.57#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.11:49:31.57#ibcon#*before write, iclass 10, count 0 2006.173.11:49:31.57#ibcon#enter sib2, iclass 10, count 0 2006.173.11:49:31.57#ibcon#flushed, iclass 10, count 0 2006.173.11:49:31.57#ibcon#about to write, iclass 10, count 0 2006.173.11:49:31.57#ibcon#wrote, iclass 10, count 0 2006.173.11:49:31.57#ibcon#about to read 3, iclass 10, count 0 2006.173.11:49:31.61#ibcon#read 3, iclass 10, count 0 2006.173.11:49:31.61#ibcon#about to read 4, iclass 10, count 0 2006.173.11:49:31.61#ibcon#read 4, iclass 10, count 0 2006.173.11:49:31.61#ibcon#about to read 5, iclass 10, count 0 2006.173.11:49:31.61#ibcon#read 5, iclass 10, count 0 2006.173.11:49:31.61#ibcon#about to read 6, iclass 10, count 0 2006.173.11:49:31.61#ibcon#read 6, iclass 10, count 0 2006.173.11:49:31.61#ibcon#end of sib2, iclass 10, count 0 2006.173.11:49:31.61#ibcon#*after write, iclass 10, count 0 2006.173.11:49:31.61#ibcon#*before return 0, iclass 10, count 0 2006.173.11:49:31.61#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.11:49:31.61#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.11:49:31.61#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.11:49:31.61#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.11:49:31.61$vck44/va=8,4 2006.173.11:49:31.61#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.11:49:31.61#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.11:49:31.61#ibcon#ireg 11 cls_cnt 2 2006.173.11:49:31.61#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.11:49:31.67#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.11:49:31.67#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.11:49:31.67#ibcon#enter wrdev, iclass 12, count 2 2006.173.11:49:31.67#ibcon#first serial, iclass 12, count 2 2006.173.11:49:31.67#ibcon#enter sib2, iclass 12, count 2 2006.173.11:49:31.67#ibcon#flushed, iclass 12, count 2 2006.173.11:49:31.67#ibcon#about to write, iclass 12, count 2 2006.173.11:49:31.67#ibcon#wrote, iclass 12, count 2 2006.173.11:49:31.67#ibcon#about to read 3, iclass 12, count 2 2006.173.11:49:31.69#ibcon#read 3, iclass 12, count 2 2006.173.11:49:31.69#ibcon#about to read 4, iclass 12, count 2 2006.173.11:49:31.69#ibcon#read 4, iclass 12, count 2 2006.173.11:49:31.69#ibcon#about to read 5, iclass 12, count 2 2006.173.11:49:31.69#ibcon#read 5, iclass 12, count 2 2006.173.11:49:31.69#ibcon#about to read 6, iclass 12, count 2 2006.173.11:49:31.69#ibcon#read 6, iclass 12, count 2 2006.173.11:49:31.69#ibcon#end of sib2, iclass 12, count 2 2006.173.11:49:31.69#ibcon#*mode == 0, iclass 12, count 2 2006.173.11:49:31.69#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.11:49:31.69#ibcon#[25=AT08-04\r\n] 2006.173.11:49:31.69#ibcon#*before write, iclass 12, count 2 2006.173.11:49:31.69#ibcon#enter sib2, iclass 12, count 2 2006.173.11:49:31.69#ibcon#flushed, iclass 12, count 2 2006.173.11:49:31.69#ibcon#about to write, iclass 12, count 2 2006.173.11:49:31.69#ibcon#wrote, iclass 12, count 2 2006.173.11:49:31.69#ibcon#about to read 3, iclass 12, count 2 2006.173.11:49:31.72#ibcon#read 3, iclass 12, count 2 2006.173.11:49:31.72#ibcon#about to read 4, iclass 12, count 2 2006.173.11:49:31.72#ibcon#read 4, iclass 12, count 2 2006.173.11:49:31.72#ibcon#about to read 5, iclass 12, count 2 2006.173.11:49:31.72#ibcon#read 5, iclass 12, count 2 2006.173.11:49:31.72#ibcon#about to read 6, iclass 12, count 2 2006.173.11:49:31.72#ibcon#read 6, iclass 12, count 2 2006.173.11:49:31.72#ibcon#end of sib2, iclass 12, count 2 2006.173.11:49:31.72#ibcon#*after write, iclass 12, count 2 2006.173.11:49:31.72#ibcon#*before return 0, iclass 12, count 2 2006.173.11:49:31.72#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.11:49:31.72#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.11:49:31.72#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.11:49:31.72#ibcon#ireg 7 cls_cnt 0 2006.173.11:49:31.72#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.11:49:31.84#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.11:49:31.84#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.11:49:31.84#ibcon#enter wrdev, iclass 12, count 0 2006.173.11:49:31.84#ibcon#first serial, iclass 12, count 0 2006.173.11:49:31.84#ibcon#enter sib2, iclass 12, count 0 2006.173.11:49:31.84#ibcon#flushed, iclass 12, count 0 2006.173.11:49:31.84#ibcon#about to write, iclass 12, count 0 2006.173.11:49:31.84#ibcon#wrote, iclass 12, count 0 2006.173.11:49:31.84#ibcon#about to read 3, iclass 12, count 0 2006.173.11:49:31.86#ibcon#read 3, iclass 12, count 0 2006.173.11:49:31.86#ibcon#about to read 4, iclass 12, count 0 2006.173.11:49:31.86#ibcon#read 4, iclass 12, count 0 2006.173.11:49:31.86#ibcon#about to read 5, iclass 12, count 0 2006.173.11:49:31.86#ibcon#read 5, iclass 12, count 0 2006.173.11:49:31.86#ibcon#about to read 6, iclass 12, count 0 2006.173.11:49:31.86#ibcon#read 6, iclass 12, count 0 2006.173.11:49:31.86#ibcon#end of sib2, iclass 12, count 0 2006.173.11:49:31.86#ibcon#*mode == 0, iclass 12, count 0 2006.173.11:49:31.86#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.11:49:31.86#ibcon#[25=USB\r\n] 2006.173.11:49:31.86#ibcon#*before write, iclass 12, count 0 2006.173.11:49:31.86#ibcon#enter sib2, iclass 12, count 0 2006.173.11:49:31.86#ibcon#flushed, iclass 12, count 0 2006.173.11:49:31.86#ibcon#about to write, iclass 12, count 0 2006.173.11:49:31.86#ibcon#wrote, iclass 12, count 0 2006.173.11:49:31.86#ibcon#about to read 3, iclass 12, count 0 2006.173.11:49:31.89#ibcon#read 3, iclass 12, count 0 2006.173.11:49:31.89#ibcon#about to read 4, iclass 12, count 0 2006.173.11:49:31.89#ibcon#read 4, iclass 12, count 0 2006.173.11:49:31.89#ibcon#about to read 5, iclass 12, count 0 2006.173.11:49:31.89#ibcon#read 5, iclass 12, count 0 2006.173.11:49:31.89#ibcon#about to read 6, iclass 12, count 0 2006.173.11:49:31.89#ibcon#read 6, iclass 12, count 0 2006.173.11:49:31.89#ibcon#end of sib2, iclass 12, count 0 2006.173.11:49:31.89#ibcon#*after write, iclass 12, count 0 2006.173.11:49:31.89#ibcon#*before return 0, iclass 12, count 0 2006.173.11:49:31.89#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.11:49:31.89#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.11:49:31.89#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.11:49:31.89#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.11:49:31.89$vck44/vblo=1,629.99 2006.173.11:49:31.89#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.11:49:31.89#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.11:49:31.89#ibcon#ireg 17 cls_cnt 0 2006.173.11:49:31.89#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.11:49:31.89#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.11:49:31.89#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.11:49:31.89#ibcon#enter wrdev, iclass 14, count 0 2006.173.11:49:31.89#ibcon#first serial, iclass 14, count 0 2006.173.11:49:31.89#ibcon#enter sib2, iclass 14, count 0 2006.173.11:49:31.89#ibcon#flushed, iclass 14, count 0 2006.173.11:49:31.89#ibcon#about to write, iclass 14, count 0 2006.173.11:49:31.89#ibcon#wrote, iclass 14, count 0 2006.173.11:49:31.89#ibcon#about to read 3, iclass 14, count 0 2006.173.11:49:31.91#ibcon#read 3, iclass 14, count 0 2006.173.11:49:31.91#ibcon#about to read 4, iclass 14, count 0 2006.173.11:49:31.91#ibcon#read 4, iclass 14, count 0 2006.173.11:49:31.91#ibcon#about to read 5, iclass 14, count 0 2006.173.11:49:31.91#ibcon#read 5, iclass 14, count 0 2006.173.11:49:31.91#ibcon#about to read 6, iclass 14, count 0 2006.173.11:49:31.91#ibcon#read 6, iclass 14, count 0 2006.173.11:49:31.91#ibcon#end of sib2, iclass 14, count 0 2006.173.11:49:31.91#ibcon#*mode == 0, iclass 14, count 0 2006.173.11:49:31.91#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.11:49:31.91#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.11:49:31.91#ibcon#*before write, iclass 14, count 0 2006.173.11:49:31.91#ibcon#enter sib2, iclass 14, count 0 2006.173.11:49:31.91#ibcon#flushed, iclass 14, count 0 2006.173.11:49:31.91#ibcon#about to write, iclass 14, count 0 2006.173.11:49:31.91#ibcon#wrote, iclass 14, count 0 2006.173.11:49:31.91#ibcon#about to read 3, iclass 14, count 0 2006.173.11:49:31.95#ibcon#read 3, iclass 14, count 0 2006.173.11:49:31.95#ibcon#about to read 4, iclass 14, count 0 2006.173.11:49:31.95#ibcon#read 4, iclass 14, count 0 2006.173.11:49:31.95#ibcon#about to read 5, iclass 14, count 0 2006.173.11:49:31.95#ibcon#read 5, iclass 14, count 0 2006.173.11:49:31.95#ibcon#about to read 6, iclass 14, count 0 2006.173.11:49:31.95#ibcon#read 6, iclass 14, count 0 2006.173.11:49:31.95#ibcon#end of sib2, iclass 14, count 0 2006.173.11:49:31.95#ibcon#*after write, iclass 14, count 0 2006.173.11:49:31.95#ibcon#*before return 0, iclass 14, count 0 2006.173.11:49:31.95#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.11:49:31.95#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.11:49:31.95#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.11:49:31.95#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.11:49:31.95$vck44/vb=1,4 2006.173.11:49:31.95#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.11:49:31.95#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.11:49:31.95#ibcon#ireg 11 cls_cnt 2 2006.173.11:49:31.95#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.11:49:31.95#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.11:49:31.95#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.11:49:31.95#ibcon#enter wrdev, iclass 16, count 2 2006.173.11:49:31.95#ibcon#first serial, iclass 16, count 2 2006.173.11:49:31.95#ibcon#enter sib2, iclass 16, count 2 2006.173.11:49:31.95#ibcon#flushed, iclass 16, count 2 2006.173.11:49:31.95#ibcon#about to write, iclass 16, count 2 2006.173.11:49:31.95#ibcon#wrote, iclass 16, count 2 2006.173.11:49:31.95#ibcon#about to read 3, iclass 16, count 2 2006.173.11:49:31.97#ibcon#read 3, iclass 16, count 2 2006.173.11:49:31.97#ibcon#about to read 4, iclass 16, count 2 2006.173.11:49:31.97#ibcon#read 4, iclass 16, count 2 2006.173.11:49:31.97#ibcon#about to read 5, iclass 16, count 2 2006.173.11:49:31.97#ibcon#read 5, iclass 16, count 2 2006.173.11:49:31.97#ibcon#about to read 6, iclass 16, count 2 2006.173.11:49:31.97#ibcon#read 6, iclass 16, count 2 2006.173.11:49:31.97#ibcon#end of sib2, iclass 16, count 2 2006.173.11:49:31.97#ibcon#*mode == 0, iclass 16, count 2 2006.173.11:49:31.97#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.11:49:31.97#ibcon#[27=AT01-04\r\n] 2006.173.11:49:31.97#ibcon#*before write, iclass 16, count 2 2006.173.11:49:31.97#ibcon#enter sib2, iclass 16, count 2 2006.173.11:49:31.97#ibcon#flushed, iclass 16, count 2 2006.173.11:49:31.97#ibcon#about to write, iclass 16, count 2 2006.173.11:49:31.97#ibcon#wrote, iclass 16, count 2 2006.173.11:49:31.97#ibcon#about to read 3, iclass 16, count 2 2006.173.11:49:32.00#ibcon#read 3, iclass 16, count 2 2006.173.11:49:32.00#ibcon#about to read 4, iclass 16, count 2 2006.173.11:49:32.00#ibcon#read 4, iclass 16, count 2 2006.173.11:49:32.00#ibcon#about to read 5, iclass 16, count 2 2006.173.11:49:32.00#ibcon#read 5, iclass 16, count 2 2006.173.11:49:32.00#ibcon#about to read 6, iclass 16, count 2 2006.173.11:49:32.00#ibcon#read 6, iclass 16, count 2 2006.173.11:49:32.00#ibcon#end of sib2, iclass 16, count 2 2006.173.11:49:32.00#ibcon#*after write, iclass 16, count 2 2006.173.11:49:32.00#ibcon#*before return 0, iclass 16, count 2 2006.173.11:49:32.00#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.11:49:32.00#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.11:49:32.00#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.11:49:32.00#ibcon#ireg 7 cls_cnt 0 2006.173.11:49:32.00#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.11:49:32.12#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.11:49:32.12#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.11:49:32.12#ibcon#enter wrdev, iclass 16, count 0 2006.173.11:49:32.12#ibcon#first serial, iclass 16, count 0 2006.173.11:49:32.12#ibcon#enter sib2, iclass 16, count 0 2006.173.11:49:32.12#ibcon#flushed, iclass 16, count 0 2006.173.11:49:32.12#ibcon#about to write, iclass 16, count 0 2006.173.11:49:32.12#ibcon#wrote, iclass 16, count 0 2006.173.11:49:32.12#ibcon#about to read 3, iclass 16, count 0 2006.173.11:49:32.14#ibcon#read 3, iclass 16, count 0 2006.173.11:49:32.14#ibcon#about to read 4, iclass 16, count 0 2006.173.11:49:32.14#ibcon#read 4, iclass 16, count 0 2006.173.11:49:32.14#ibcon#about to read 5, iclass 16, count 0 2006.173.11:49:32.14#ibcon#read 5, iclass 16, count 0 2006.173.11:49:32.14#ibcon#about to read 6, iclass 16, count 0 2006.173.11:49:32.14#ibcon#read 6, iclass 16, count 0 2006.173.11:49:32.14#ibcon#end of sib2, iclass 16, count 0 2006.173.11:49:32.14#ibcon#*mode == 0, iclass 16, count 0 2006.173.11:49:32.14#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.11:49:32.14#ibcon#[27=USB\r\n] 2006.173.11:49:32.14#ibcon#*before write, iclass 16, count 0 2006.173.11:49:32.14#ibcon#enter sib2, iclass 16, count 0 2006.173.11:49:32.14#ibcon#flushed, iclass 16, count 0 2006.173.11:49:32.14#ibcon#about to write, iclass 16, count 0 2006.173.11:49:32.14#ibcon#wrote, iclass 16, count 0 2006.173.11:49:32.14#ibcon#about to read 3, iclass 16, count 0 2006.173.11:49:32.17#ibcon#read 3, iclass 16, count 0 2006.173.11:49:32.17#ibcon#about to read 4, iclass 16, count 0 2006.173.11:49:32.17#ibcon#read 4, iclass 16, count 0 2006.173.11:49:32.17#ibcon#about to read 5, iclass 16, count 0 2006.173.11:49:32.17#ibcon#read 5, iclass 16, count 0 2006.173.11:49:32.17#ibcon#about to read 6, iclass 16, count 0 2006.173.11:49:32.17#ibcon#read 6, iclass 16, count 0 2006.173.11:49:32.17#ibcon#end of sib2, iclass 16, count 0 2006.173.11:49:32.17#ibcon#*after write, iclass 16, count 0 2006.173.11:49:32.17#ibcon#*before return 0, iclass 16, count 0 2006.173.11:49:32.17#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.11:49:32.17#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.11:49:32.17#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.11:49:32.17#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.11:49:32.17$vck44/vblo=2,634.99 2006.173.11:49:32.17#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.11:49:32.17#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.11:49:32.17#ibcon#ireg 17 cls_cnt 0 2006.173.11:49:32.17#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.11:49:32.17#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.11:49:32.17#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.11:49:32.17#ibcon#enter wrdev, iclass 18, count 0 2006.173.11:49:32.17#ibcon#first serial, iclass 18, count 0 2006.173.11:49:32.17#ibcon#enter sib2, iclass 18, count 0 2006.173.11:49:32.17#ibcon#flushed, iclass 18, count 0 2006.173.11:49:32.17#ibcon#about to write, iclass 18, count 0 2006.173.11:49:32.17#ibcon#wrote, iclass 18, count 0 2006.173.11:49:32.17#ibcon#about to read 3, iclass 18, count 0 2006.173.11:49:32.19#ibcon#read 3, iclass 18, count 0 2006.173.11:49:32.19#ibcon#about to read 4, iclass 18, count 0 2006.173.11:49:32.19#ibcon#read 4, iclass 18, count 0 2006.173.11:49:32.19#ibcon#about to read 5, iclass 18, count 0 2006.173.11:49:32.19#ibcon#read 5, iclass 18, count 0 2006.173.11:49:32.19#ibcon#about to read 6, iclass 18, count 0 2006.173.11:49:32.19#ibcon#read 6, iclass 18, count 0 2006.173.11:49:32.19#ibcon#end of sib2, iclass 18, count 0 2006.173.11:49:32.19#ibcon#*mode == 0, iclass 18, count 0 2006.173.11:49:32.19#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.11:49:32.19#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.11:49:32.19#ibcon#*before write, iclass 18, count 0 2006.173.11:49:32.19#ibcon#enter sib2, iclass 18, count 0 2006.173.11:49:32.19#ibcon#flushed, iclass 18, count 0 2006.173.11:49:32.19#ibcon#about to write, iclass 18, count 0 2006.173.11:49:32.19#ibcon#wrote, iclass 18, count 0 2006.173.11:49:32.19#ibcon#about to read 3, iclass 18, count 0 2006.173.11:49:32.23#ibcon#read 3, iclass 18, count 0 2006.173.11:49:32.23#ibcon#about to read 4, iclass 18, count 0 2006.173.11:49:32.23#ibcon#read 4, iclass 18, count 0 2006.173.11:49:32.23#ibcon#about to read 5, iclass 18, count 0 2006.173.11:49:32.23#ibcon#read 5, iclass 18, count 0 2006.173.11:49:32.23#ibcon#about to read 6, iclass 18, count 0 2006.173.11:49:32.23#ibcon#read 6, iclass 18, count 0 2006.173.11:49:32.23#ibcon#end of sib2, iclass 18, count 0 2006.173.11:49:32.23#ibcon#*after write, iclass 18, count 0 2006.173.11:49:32.23#ibcon#*before return 0, iclass 18, count 0 2006.173.11:49:32.23#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.11:49:32.23#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.11:49:32.23#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.11:49:32.23#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.11:49:32.23$vck44/vb=2,4 2006.173.11:49:32.23#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.11:49:32.23#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.11:49:32.23#ibcon#ireg 11 cls_cnt 2 2006.173.11:49:32.23#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.11:49:32.29#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.11:49:32.29#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.11:49:32.29#ibcon#enter wrdev, iclass 20, count 2 2006.173.11:49:32.29#ibcon#first serial, iclass 20, count 2 2006.173.11:49:32.29#ibcon#enter sib2, iclass 20, count 2 2006.173.11:49:32.29#ibcon#flushed, iclass 20, count 2 2006.173.11:49:32.29#ibcon#about to write, iclass 20, count 2 2006.173.11:49:32.29#ibcon#wrote, iclass 20, count 2 2006.173.11:49:32.29#ibcon#about to read 3, iclass 20, count 2 2006.173.11:49:32.31#ibcon#read 3, iclass 20, count 2 2006.173.11:49:32.31#ibcon#about to read 4, iclass 20, count 2 2006.173.11:49:32.31#ibcon#read 4, iclass 20, count 2 2006.173.11:49:32.31#ibcon#about to read 5, iclass 20, count 2 2006.173.11:49:32.31#ibcon#read 5, iclass 20, count 2 2006.173.11:49:32.31#ibcon#about to read 6, iclass 20, count 2 2006.173.11:49:32.31#ibcon#read 6, iclass 20, count 2 2006.173.11:49:32.31#ibcon#end of sib2, iclass 20, count 2 2006.173.11:49:32.31#ibcon#*mode == 0, iclass 20, count 2 2006.173.11:49:32.31#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.11:49:32.31#ibcon#[27=AT02-04\r\n] 2006.173.11:49:32.31#ibcon#*before write, iclass 20, count 2 2006.173.11:49:32.31#ibcon#enter sib2, iclass 20, count 2 2006.173.11:49:32.31#ibcon#flushed, iclass 20, count 2 2006.173.11:49:32.31#ibcon#about to write, iclass 20, count 2 2006.173.11:49:32.31#ibcon#wrote, iclass 20, count 2 2006.173.11:49:32.31#ibcon#about to read 3, iclass 20, count 2 2006.173.11:49:32.34#ibcon#read 3, iclass 20, count 2 2006.173.11:49:32.34#ibcon#about to read 4, iclass 20, count 2 2006.173.11:49:32.34#ibcon#read 4, iclass 20, count 2 2006.173.11:49:32.34#ibcon#about to read 5, iclass 20, count 2 2006.173.11:49:32.34#ibcon#read 5, iclass 20, count 2 2006.173.11:49:32.34#ibcon#about to read 6, iclass 20, count 2 2006.173.11:49:32.34#ibcon#read 6, iclass 20, count 2 2006.173.11:49:32.34#ibcon#end of sib2, iclass 20, count 2 2006.173.11:49:32.34#ibcon#*after write, iclass 20, count 2 2006.173.11:49:32.34#ibcon#*before return 0, iclass 20, count 2 2006.173.11:49:32.34#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.11:49:32.34#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.11:49:32.34#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.11:49:32.34#ibcon#ireg 7 cls_cnt 0 2006.173.11:49:32.34#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.11:49:32.46#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.11:49:32.46#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.11:49:32.46#ibcon#enter wrdev, iclass 20, count 0 2006.173.11:49:32.46#ibcon#first serial, iclass 20, count 0 2006.173.11:49:32.46#ibcon#enter sib2, iclass 20, count 0 2006.173.11:49:32.46#ibcon#flushed, iclass 20, count 0 2006.173.11:49:32.46#ibcon#about to write, iclass 20, count 0 2006.173.11:49:32.46#ibcon#wrote, iclass 20, count 0 2006.173.11:49:32.46#ibcon#about to read 3, iclass 20, count 0 2006.173.11:49:32.48#ibcon#read 3, iclass 20, count 0 2006.173.11:49:32.48#ibcon#about to read 4, iclass 20, count 0 2006.173.11:49:32.48#ibcon#read 4, iclass 20, count 0 2006.173.11:49:32.48#ibcon#about to read 5, iclass 20, count 0 2006.173.11:49:32.48#ibcon#read 5, iclass 20, count 0 2006.173.11:49:32.48#ibcon#about to read 6, iclass 20, count 0 2006.173.11:49:32.48#ibcon#read 6, iclass 20, count 0 2006.173.11:49:32.48#ibcon#end of sib2, iclass 20, count 0 2006.173.11:49:32.48#ibcon#*mode == 0, iclass 20, count 0 2006.173.11:49:32.48#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.11:49:32.48#ibcon#[27=USB\r\n] 2006.173.11:49:32.48#ibcon#*before write, iclass 20, count 0 2006.173.11:49:32.48#ibcon#enter sib2, iclass 20, count 0 2006.173.11:49:32.48#ibcon#flushed, iclass 20, count 0 2006.173.11:49:32.48#ibcon#about to write, iclass 20, count 0 2006.173.11:49:32.48#ibcon#wrote, iclass 20, count 0 2006.173.11:49:32.48#ibcon#about to read 3, iclass 20, count 0 2006.173.11:49:32.51#ibcon#read 3, iclass 20, count 0 2006.173.11:49:32.51#ibcon#about to read 4, iclass 20, count 0 2006.173.11:49:32.51#ibcon#read 4, iclass 20, count 0 2006.173.11:49:32.51#ibcon#about to read 5, iclass 20, count 0 2006.173.11:49:32.51#ibcon#read 5, iclass 20, count 0 2006.173.11:49:32.51#ibcon#about to read 6, iclass 20, count 0 2006.173.11:49:32.51#ibcon#read 6, iclass 20, count 0 2006.173.11:49:32.51#ibcon#end of sib2, iclass 20, count 0 2006.173.11:49:32.51#ibcon#*after write, iclass 20, count 0 2006.173.11:49:32.51#ibcon#*before return 0, iclass 20, count 0 2006.173.11:49:32.51#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.11:49:32.51#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.11:49:32.51#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.11:49:32.51#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.11:49:32.51$vck44/vblo=3,649.99 2006.173.11:49:32.51#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.11:49:32.51#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.11:49:32.51#ibcon#ireg 17 cls_cnt 0 2006.173.11:49:32.51#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.11:49:32.51#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.11:49:32.51#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.11:49:32.51#ibcon#enter wrdev, iclass 22, count 0 2006.173.11:49:32.51#ibcon#first serial, iclass 22, count 0 2006.173.11:49:32.51#ibcon#enter sib2, iclass 22, count 0 2006.173.11:49:32.51#ibcon#flushed, iclass 22, count 0 2006.173.11:49:32.51#ibcon#about to write, iclass 22, count 0 2006.173.11:49:32.51#ibcon#wrote, iclass 22, count 0 2006.173.11:49:32.51#ibcon#about to read 3, iclass 22, count 0 2006.173.11:49:32.53#ibcon#read 3, iclass 22, count 0 2006.173.11:49:32.53#ibcon#about to read 4, iclass 22, count 0 2006.173.11:49:32.53#ibcon#read 4, iclass 22, count 0 2006.173.11:49:32.53#ibcon#about to read 5, iclass 22, count 0 2006.173.11:49:32.53#ibcon#read 5, iclass 22, count 0 2006.173.11:49:32.53#ibcon#about to read 6, iclass 22, count 0 2006.173.11:49:32.53#ibcon#read 6, iclass 22, count 0 2006.173.11:49:32.53#ibcon#end of sib2, iclass 22, count 0 2006.173.11:49:32.53#ibcon#*mode == 0, iclass 22, count 0 2006.173.11:49:32.53#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.11:49:32.53#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.11:49:32.53#ibcon#*before write, iclass 22, count 0 2006.173.11:49:32.53#ibcon#enter sib2, iclass 22, count 0 2006.173.11:49:32.53#ibcon#flushed, iclass 22, count 0 2006.173.11:49:32.53#ibcon#about to write, iclass 22, count 0 2006.173.11:49:32.53#ibcon#wrote, iclass 22, count 0 2006.173.11:49:32.53#ibcon#about to read 3, iclass 22, count 0 2006.173.11:49:32.57#ibcon#read 3, iclass 22, count 0 2006.173.11:49:32.57#ibcon#about to read 4, iclass 22, count 0 2006.173.11:49:32.57#ibcon#read 4, iclass 22, count 0 2006.173.11:49:32.57#ibcon#about to read 5, iclass 22, count 0 2006.173.11:49:32.57#ibcon#read 5, iclass 22, count 0 2006.173.11:49:32.57#ibcon#about to read 6, iclass 22, count 0 2006.173.11:49:32.57#ibcon#read 6, iclass 22, count 0 2006.173.11:49:32.57#ibcon#end of sib2, iclass 22, count 0 2006.173.11:49:32.57#ibcon#*after write, iclass 22, count 0 2006.173.11:49:32.57#ibcon#*before return 0, iclass 22, count 0 2006.173.11:49:32.57#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.11:49:32.57#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.11:49:32.57#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.11:49:32.57#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.11:49:32.57$vck44/vb=3,4 2006.173.11:49:32.57#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.11:49:32.57#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.11:49:32.57#ibcon#ireg 11 cls_cnt 2 2006.173.11:49:32.57#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.11:49:32.63#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.11:49:32.63#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.11:49:32.63#ibcon#enter wrdev, iclass 24, count 2 2006.173.11:49:32.63#ibcon#first serial, iclass 24, count 2 2006.173.11:49:32.63#ibcon#enter sib2, iclass 24, count 2 2006.173.11:49:32.63#ibcon#flushed, iclass 24, count 2 2006.173.11:49:32.63#ibcon#about to write, iclass 24, count 2 2006.173.11:49:32.63#ibcon#wrote, iclass 24, count 2 2006.173.11:49:32.63#ibcon#about to read 3, iclass 24, count 2 2006.173.11:49:32.65#ibcon#read 3, iclass 24, count 2 2006.173.11:49:32.65#ibcon#about to read 4, iclass 24, count 2 2006.173.11:49:32.65#ibcon#read 4, iclass 24, count 2 2006.173.11:49:32.65#ibcon#about to read 5, iclass 24, count 2 2006.173.11:49:32.65#ibcon#read 5, iclass 24, count 2 2006.173.11:49:32.65#ibcon#about to read 6, iclass 24, count 2 2006.173.11:49:32.65#ibcon#read 6, iclass 24, count 2 2006.173.11:49:32.65#ibcon#end of sib2, iclass 24, count 2 2006.173.11:49:32.65#ibcon#*mode == 0, iclass 24, count 2 2006.173.11:49:32.65#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.11:49:32.65#ibcon#[27=AT03-04\r\n] 2006.173.11:49:32.65#ibcon#*before write, iclass 24, count 2 2006.173.11:49:32.65#ibcon#enter sib2, iclass 24, count 2 2006.173.11:49:32.65#ibcon#flushed, iclass 24, count 2 2006.173.11:49:32.65#ibcon#about to write, iclass 24, count 2 2006.173.11:49:32.65#ibcon#wrote, iclass 24, count 2 2006.173.11:49:32.65#ibcon#about to read 3, iclass 24, count 2 2006.173.11:49:32.68#ibcon#read 3, iclass 24, count 2 2006.173.11:49:32.68#ibcon#about to read 4, iclass 24, count 2 2006.173.11:49:32.68#ibcon#read 4, iclass 24, count 2 2006.173.11:49:32.68#ibcon#about to read 5, iclass 24, count 2 2006.173.11:49:32.68#ibcon#read 5, iclass 24, count 2 2006.173.11:49:32.68#ibcon#about to read 6, iclass 24, count 2 2006.173.11:49:32.68#ibcon#read 6, iclass 24, count 2 2006.173.11:49:32.68#ibcon#end of sib2, iclass 24, count 2 2006.173.11:49:32.68#ibcon#*after write, iclass 24, count 2 2006.173.11:49:32.68#ibcon#*before return 0, iclass 24, count 2 2006.173.11:49:32.68#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.11:49:32.68#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.11:49:32.68#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.11:49:32.68#ibcon#ireg 7 cls_cnt 0 2006.173.11:49:32.68#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.11:49:32.80#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.11:49:32.80#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.11:49:32.80#ibcon#enter wrdev, iclass 24, count 0 2006.173.11:49:32.80#ibcon#first serial, iclass 24, count 0 2006.173.11:49:32.80#ibcon#enter sib2, iclass 24, count 0 2006.173.11:49:32.80#ibcon#flushed, iclass 24, count 0 2006.173.11:49:32.80#ibcon#about to write, iclass 24, count 0 2006.173.11:49:32.80#ibcon#wrote, iclass 24, count 0 2006.173.11:49:32.80#ibcon#about to read 3, iclass 24, count 0 2006.173.11:49:32.82#ibcon#read 3, iclass 24, count 0 2006.173.11:49:32.82#ibcon#about to read 4, iclass 24, count 0 2006.173.11:49:32.82#ibcon#read 4, iclass 24, count 0 2006.173.11:49:32.82#ibcon#about to read 5, iclass 24, count 0 2006.173.11:49:32.82#ibcon#read 5, iclass 24, count 0 2006.173.11:49:32.82#ibcon#about to read 6, iclass 24, count 0 2006.173.11:49:32.82#ibcon#read 6, iclass 24, count 0 2006.173.11:49:32.82#ibcon#end of sib2, iclass 24, count 0 2006.173.11:49:32.82#ibcon#*mode == 0, iclass 24, count 0 2006.173.11:49:32.82#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.11:49:32.82#ibcon#[27=USB\r\n] 2006.173.11:49:32.82#ibcon#*before write, iclass 24, count 0 2006.173.11:49:32.82#ibcon#enter sib2, iclass 24, count 0 2006.173.11:49:32.82#ibcon#flushed, iclass 24, count 0 2006.173.11:49:32.82#ibcon#about to write, iclass 24, count 0 2006.173.11:49:32.82#ibcon#wrote, iclass 24, count 0 2006.173.11:49:32.82#ibcon#about to read 3, iclass 24, count 0 2006.173.11:49:32.85#ibcon#read 3, iclass 24, count 0 2006.173.11:49:32.85#ibcon#about to read 4, iclass 24, count 0 2006.173.11:49:32.85#ibcon#read 4, iclass 24, count 0 2006.173.11:49:32.85#ibcon#about to read 5, iclass 24, count 0 2006.173.11:49:32.85#ibcon#read 5, iclass 24, count 0 2006.173.11:49:32.85#ibcon#about to read 6, iclass 24, count 0 2006.173.11:49:32.85#ibcon#read 6, iclass 24, count 0 2006.173.11:49:32.85#ibcon#end of sib2, iclass 24, count 0 2006.173.11:49:32.85#ibcon#*after write, iclass 24, count 0 2006.173.11:49:32.85#ibcon#*before return 0, iclass 24, count 0 2006.173.11:49:32.85#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.11:49:32.85#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.11:49:32.85#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.11:49:32.85#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.11:49:32.85$vck44/vblo=4,679.99 2006.173.11:49:32.85#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.11:49:32.85#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.11:49:32.85#ibcon#ireg 17 cls_cnt 0 2006.173.11:49:32.85#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.11:49:32.85#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.11:49:32.85#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.11:49:32.85#ibcon#enter wrdev, iclass 26, count 0 2006.173.11:49:32.85#ibcon#first serial, iclass 26, count 0 2006.173.11:49:32.85#ibcon#enter sib2, iclass 26, count 0 2006.173.11:49:32.85#ibcon#flushed, iclass 26, count 0 2006.173.11:49:32.85#ibcon#about to write, iclass 26, count 0 2006.173.11:49:32.85#ibcon#wrote, iclass 26, count 0 2006.173.11:49:32.85#ibcon#about to read 3, iclass 26, count 0 2006.173.11:49:32.87#ibcon#read 3, iclass 26, count 0 2006.173.11:49:32.87#ibcon#about to read 4, iclass 26, count 0 2006.173.11:49:32.87#ibcon#read 4, iclass 26, count 0 2006.173.11:49:32.87#ibcon#about to read 5, iclass 26, count 0 2006.173.11:49:32.87#ibcon#read 5, iclass 26, count 0 2006.173.11:49:32.87#ibcon#about to read 6, iclass 26, count 0 2006.173.11:49:32.87#ibcon#read 6, iclass 26, count 0 2006.173.11:49:32.87#ibcon#end of sib2, iclass 26, count 0 2006.173.11:49:32.87#ibcon#*mode == 0, iclass 26, count 0 2006.173.11:49:32.87#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.11:49:32.87#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.11:49:32.87#ibcon#*before write, iclass 26, count 0 2006.173.11:49:32.87#ibcon#enter sib2, iclass 26, count 0 2006.173.11:49:32.87#ibcon#flushed, iclass 26, count 0 2006.173.11:49:32.87#ibcon#about to write, iclass 26, count 0 2006.173.11:49:32.87#ibcon#wrote, iclass 26, count 0 2006.173.11:49:32.87#ibcon#about to read 3, iclass 26, count 0 2006.173.11:49:32.91#ibcon#read 3, iclass 26, count 0 2006.173.11:49:32.91#ibcon#about to read 4, iclass 26, count 0 2006.173.11:49:32.91#ibcon#read 4, iclass 26, count 0 2006.173.11:49:32.91#ibcon#about to read 5, iclass 26, count 0 2006.173.11:49:32.91#ibcon#read 5, iclass 26, count 0 2006.173.11:49:32.91#ibcon#about to read 6, iclass 26, count 0 2006.173.11:49:32.91#ibcon#read 6, iclass 26, count 0 2006.173.11:49:32.91#ibcon#end of sib2, iclass 26, count 0 2006.173.11:49:32.91#ibcon#*after write, iclass 26, count 0 2006.173.11:49:32.91#ibcon#*before return 0, iclass 26, count 0 2006.173.11:49:32.91#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.11:49:32.91#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.11:49:32.91#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.11:49:32.91#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.11:49:32.91$vck44/vb=4,4 2006.173.11:49:32.91#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.11:49:32.91#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.11:49:32.91#ibcon#ireg 11 cls_cnt 2 2006.173.11:49:32.91#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.11:49:32.97#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.11:49:32.97#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.11:49:32.97#ibcon#enter wrdev, iclass 28, count 2 2006.173.11:49:32.97#ibcon#first serial, iclass 28, count 2 2006.173.11:49:32.97#ibcon#enter sib2, iclass 28, count 2 2006.173.11:49:32.97#ibcon#flushed, iclass 28, count 2 2006.173.11:49:32.97#ibcon#about to write, iclass 28, count 2 2006.173.11:49:32.97#ibcon#wrote, iclass 28, count 2 2006.173.11:49:32.97#ibcon#about to read 3, iclass 28, count 2 2006.173.11:49:32.99#ibcon#read 3, iclass 28, count 2 2006.173.11:49:32.99#ibcon#about to read 4, iclass 28, count 2 2006.173.11:49:32.99#ibcon#read 4, iclass 28, count 2 2006.173.11:49:32.99#ibcon#about to read 5, iclass 28, count 2 2006.173.11:49:32.99#ibcon#read 5, iclass 28, count 2 2006.173.11:49:32.99#ibcon#about to read 6, iclass 28, count 2 2006.173.11:49:32.99#ibcon#read 6, iclass 28, count 2 2006.173.11:49:32.99#ibcon#end of sib2, iclass 28, count 2 2006.173.11:49:32.99#ibcon#*mode == 0, iclass 28, count 2 2006.173.11:49:32.99#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.11:49:32.99#ibcon#[27=AT04-04\r\n] 2006.173.11:49:32.99#ibcon#*before write, iclass 28, count 2 2006.173.11:49:32.99#ibcon#enter sib2, iclass 28, count 2 2006.173.11:49:32.99#ibcon#flushed, iclass 28, count 2 2006.173.11:49:32.99#ibcon#about to write, iclass 28, count 2 2006.173.11:49:32.99#ibcon#wrote, iclass 28, count 2 2006.173.11:49:32.99#ibcon#about to read 3, iclass 28, count 2 2006.173.11:49:33.02#ibcon#read 3, iclass 28, count 2 2006.173.11:49:33.02#ibcon#about to read 4, iclass 28, count 2 2006.173.11:49:33.02#ibcon#read 4, iclass 28, count 2 2006.173.11:49:33.02#ibcon#about to read 5, iclass 28, count 2 2006.173.11:49:33.02#ibcon#read 5, iclass 28, count 2 2006.173.11:49:33.02#ibcon#about to read 6, iclass 28, count 2 2006.173.11:49:33.02#ibcon#read 6, iclass 28, count 2 2006.173.11:49:33.02#ibcon#end of sib2, iclass 28, count 2 2006.173.11:49:33.02#ibcon#*after write, iclass 28, count 2 2006.173.11:49:33.02#ibcon#*before return 0, iclass 28, count 2 2006.173.11:49:33.02#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.11:49:33.02#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.11:49:33.02#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.11:49:33.02#ibcon#ireg 7 cls_cnt 0 2006.173.11:49:33.02#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.11:49:33.14#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.11:49:33.14#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.11:49:33.14#ibcon#enter wrdev, iclass 28, count 0 2006.173.11:49:33.14#ibcon#first serial, iclass 28, count 0 2006.173.11:49:33.14#ibcon#enter sib2, iclass 28, count 0 2006.173.11:49:33.14#ibcon#flushed, iclass 28, count 0 2006.173.11:49:33.14#ibcon#about to write, iclass 28, count 0 2006.173.11:49:33.14#ibcon#wrote, iclass 28, count 0 2006.173.11:49:33.14#ibcon#about to read 3, iclass 28, count 0 2006.173.11:49:33.16#ibcon#read 3, iclass 28, count 0 2006.173.11:49:33.16#ibcon#about to read 4, iclass 28, count 0 2006.173.11:49:33.16#ibcon#read 4, iclass 28, count 0 2006.173.11:49:33.16#ibcon#about to read 5, iclass 28, count 0 2006.173.11:49:33.16#ibcon#read 5, iclass 28, count 0 2006.173.11:49:33.16#ibcon#about to read 6, iclass 28, count 0 2006.173.11:49:33.16#ibcon#read 6, iclass 28, count 0 2006.173.11:49:33.16#ibcon#end of sib2, iclass 28, count 0 2006.173.11:49:33.16#ibcon#*mode == 0, iclass 28, count 0 2006.173.11:49:33.16#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.11:49:33.16#ibcon#[27=USB\r\n] 2006.173.11:49:33.16#ibcon#*before write, iclass 28, count 0 2006.173.11:49:33.16#ibcon#enter sib2, iclass 28, count 0 2006.173.11:49:33.16#ibcon#flushed, iclass 28, count 0 2006.173.11:49:33.16#ibcon#about to write, iclass 28, count 0 2006.173.11:49:33.16#ibcon#wrote, iclass 28, count 0 2006.173.11:49:33.16#ibcon#about to read 3, iclass 28, count 0 2006.173.11:49:33.19#ibcon#read 3, iclass 28, count 0 2006.173.11:49:33.19#ibcon#about to read 4, iclass 28, count 0 2006.173.11:49:33.19#ibcon#read 4, iclass 28, count 0 2006.173.11:49:33.19#ibcon#about to read 5, iclass 28, count 0 2006.173.11:49:33.19#ibcon#read 5, iclass 28, count 0 2006.173.11:49:33.19#ibcon#about to read 6, iclass 28, count 0 2006.173.11:49:33.19#ibcon#read 6, iclass 28, count 0 2006.173.11:49:33.19#ibcon#end of sib2, iclass 28, count 0 2006.173.11:49:33.19#ibcon#*after write, iclass 28, count 0 2006.173.11:49:33.19#ibcon#*before return 0, iclass 28, count 0 2006.173.11:49:33.19#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.11:49:33.19#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.11:49:33.19#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.11:49:33.19#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.11:49:33.19$vck44/vblo=5,709.99 2006.173.11:49:33.19#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.11:49:33.19#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.11:49:33.19#ibcon#ireg 17 cls_cnt 0 2006.173.11:49:33.19#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.11:49:33.19#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.11:49:33.19#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.11:49:33.19#ibcon#enter wrdev, iclass 30, count 0 2006.173.11:49:33.19#ibcon#first serial, iclass 30, count 0 2006.173.11:49:33.19#ibcon#enter sib2, iclass 30, count 0 2006.173.11:49:33.19#ibcon#flushed, iclass 30, count 0 2006.173.11:49:33.19#ibcon#about to write, iclass 30, count 0 2006.173.11:49:33.19#ibcon#wrote, iclass 30, count 0 2006.173.11:49:33.19#ibcon#about to read 3, iclass 30, count 0 2006.173.11:49:33.21#ibcon#read 3, iclass 30, count 0 2006.173.11:49:33.21#ibcon#about to read 4, iclass 30, count 0 2006.173.11:49:33.21#ibcon#read 4, iclass 30, count 0 2006.173.11:49:33.21#ibcon#about to read 5, iclass 30, count 0 2006.173.11:49:33.21#ibcon#read 5, iclass 30, count 0 2006.173.11:49:33.21#ibcon#about to read 6, iclass 30, count 0 2006.173.11:49:33.21#ibcon#read 6, iclass 30, count 0 2006.173.11:49:33.21#ibcon#end of sib2, iclass 30, count 0 2006.173.11:49:33.21#ibcon#*mode == 0, iclass 30, count 0 2006.173.11:49:33.21#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.11:49:33.21#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.11:49:33.21#ibcon#*before write, iclass 30, count 0 2006.173.11:49:33.21#ibcon#enter sib2, iclass 30, count 0 2006.173.11:49:33.21#ibcon#flushed, iclass 30, count 0 2006.173.11:49:33.21#ibcon#about to write, iclass 30, count 0 2006.173.11:49:33.21#ibcon#wrote, iclass 30, count 0 2006.173.11:49:33.21#ibcon#about to read 3, iclass 30, count 0 2006.173.11:49:33.25#ibcon#read 3, iclass 30, count 0 2006.173.11:49:33.25#ibcon#about to read 4, iclass 30, count 0 2006.173.11:49:33.25#ibcon#read 4, iclass 30, count 0 2006.173.11:49:33.25#ibcon#about to read 5, iclass 30, count 0 2006.173.11:49:33.25#ibcon#read 5, iclass 30, count 0 2006.173.11:49:33.25#ibcon#about to read 6, iclass 30, count 0 2006.173.11:49:33.25#ibcon#read 6, iclass 30, count 0 2006.173.11:49:33.25#ibcon#end of sib2, iclass 30, count 0 2006.173.11:49:33.25#ibcon#*after write, iclass 30, count 0 2006.173.11:49:33.25#ibcon#*before return 0, iclass 30, count 0 2006.173.11:49:33.25#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.11:49:33.25#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.11:49:33.25#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.11:49:33.25#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.11:49:33.25$vck44/vb=5,4 2006.173.11:49:33.25#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.173.11:49:33.25#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.173.11:49:33.25#ibcon#ireg 11 cls_cnt 2 2006.173.11:49:33.25#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.11:49:33.31#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.11:49:33.31#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.11:49:33.31#ibcon#enter wrdev, iclass 32, count 2 2006.173.11:49:33.31#ibcon#first serial, iclass 32, count 2 2006.173.11:49:33.31#ibcon#enter sib2, iclass 32, count 2 2006.173.11:49:33.31#ibcon#flushed, iclass 32, count 2 2006.173.11:49:33.31#ibcon#about to write, iclass 32, count 2 2006.173.11:49:33.31#ibcon#wrote, iclass 32, count 2 2006.173.11:49:33.31#ibcon#about to read 3, iclass 32, count 2 2006.173.11:49:33.33#ibcon#read 3, iclass 32, count 2 2006.173.11:49:33.33#ibcon#about to read 4, iclass 32, count 2 2006.173.11:49:33.33#ibcon#read 4, iclass 32, count 2 2006.173.11:49:33.33#ibcon#about to read 5, iclass 32, count 2 2006.173.11:49:33.33#ibcon#read 5, iclass 32, count 2 2006.173.11:49:33.33#ibcon#about to read 6, iclass 32, count 2 2006.173.11:49:33.33#ibcon#read 6, iclass 32, count 2 2006.173.11:49:33.33#ibcon#end of sib2, iclass 32, count 2 2006.173.11:49:33.33#ibcon#*mode == 0, iclass 32, count 2 2006.173.11:49:33.33#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.173.11:49:33.33#ibcon#[27=AT05-04\r\n] 2006.173.11:49:33.33#ibcon#*before write, iclass 32, count 2 2006.173.11:49:33.33#ibcon#enter sib2, iclass 32, count 2 2006.173.11:49:33.33#ibcon#flushed, iclass 32, count 2 2006.173.11:49:33.33#ibcon#about to write, iclass 32, count 2 2006.173.11:49:33.33#ibcon#wrote, iclass 32, count 2 2006.173.11:49:33.33#ibcon#about to read 3, iclass 32, count 2 2006.173.11:49:33.36#ibcon#read 3, iclass 32, count 2 2006.173.11:49:33.36#ibcon#about to read 4, iclass 32, count 2 2006.173.11:49:33.36#ibcon#read 4, iclass 32, count 2 2006.173.11:49:33.36#ibcon#about to read 5, iclass 32, count 2 2006.173.11:49:33.36#ibcon#read 5, iclass 32, count 2 2006.173.11:49:33.36#ibcon#about to read 6, iclass 32, count 2 2006.173.11:49:33.36#ibcon#read 6, iclass 32, count 2 2006.173.11:49:33.36#ibcon#end of sib2, iclass 32, count 2 2006.173.11:49:33.36#ibcon#*after write, iclass 32, count 2 2006.173.11:49:33.36#ibcon#*before return 0, iclass 32, count 2 2006.173.11:49:33.36#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.11:49:33.36#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.173.11:49:33.36#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.173.11:49:33.36#ibcon#ireg 7 cls_cnt 0 2006.173.11:49:33.36#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.11:49:33.48#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.11:49:33.48#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.11:49:33.48#ibcon#enter wrdev, iclass 32, count 0 2006.173.11:49:33.48#ibcon#first serial, iclass 32, count 0 2006.173.11:49:33.48#ibcon#enter sib2, iclass 32, count 0 2006.173.11:49:33.48#ibcon#flushed, iclass 32, count 0 2006.173.11:49:33.48#ibcon#about to write, iclass 32, count 0 2006.173.11:49:33.48#ibcon#wrote, iclass 32, count 0 2006.173.11:49:33.48#ibcon#about to read 3, iclass 32, count 0 2006.173.11:49:33.50#ibcon#read 3, iclass 32, count 0 2006.173.11:49:33.50#ibcon#about to read 4, iclass 32, count 0 2006.173.11:49:33.50#ibcon#read 4, iclass 32, count 0 2006.173.11:49:33.50#ibcon#about to read 5, iclass 32, count 0 2006.173.11:49:33.50#ibcon#read 5, iclass 32, count 0 2006.173.11:49:33.50#ibcon#about to read 6, iclass 32, count 0 2006.173.11:49:33.50#ibcon#read 6, iclass 32, count 0 2006.173.11:49:33.50#ibcon#end of sib2, iclass 32, count 0 2006.173.11:49:33.50#ibcon#*mode == 0, iclass 32, count 0 2006.173.11:49:33.50#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.11:49:33.50#ibcon#[27=USB\r\n] 2006.173.11:49:33.50#ibcon#*before write, iclass 32, count 0 2006.173.11:49:33.50#ibcon#enter sib2, iclass 32, count 0 2006.173.11:49:33.50#ibcon#flushed, iclass 32, count 0 2006.173.11:49:33.50#ibcon#about to write, iclass 32, count 0 2006.173.11:49:33.50#ibcon#wrote, iclass 32, count 0 2006.173.11:49:33.50#ibcon#about to read 3, iclass 32, count 0 2006.173.11:49:33.53#ibcon#read 3, iclass 32, count 0 2006.173.11:49:33.53#ibcon#about to read 4, iclass 32, count 0 2006.173.11:49:33.53#ibcon#read 4, iclass 32, count 0 2006.173.11:49:33.53#ibcon#about to read 5, iclass 32, count 0 2006.173.11:49:33.53#ibcon#read 5, iclass 32, count 0 2006.173.11:49:33.53#ibcon#about to read 6, iclass 32, count 0 2006.173.11:49:33.53#ibcon#read 6, iclass 32, count 0 2006.173.11:49:33.53#ibcon#end of sib2, iclass 32, count 0 2006.173.11:49:33.53#ibcon#*after write, iclass 32, count 0 2006.173.11:49:33.53#ibcon#*before return 0, iclass 32, count 0 2006.173.11:49:33.53#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.11:49:33.53#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.173.11:49:33.53#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.11:49:33.53#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.11:49:33.53$vck44/vblo=6,719.99 2006.173.11:49:33.53#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.11:49:33.53#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.11:49:33.53#ibcon#ireg 17 cls_cnt 0 2006.173.11:49:33.53#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.11:49:33.53#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.11:49:33.53#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.11:49:33.53#ibcon#enter wrdev, iclass 34, count 0 2006.173.11:49:33.53#ibcon#first serial, iclass 34, count 0 2006.173.11:49:33.53#ibcon#enter sib2, iclass 34, count 0 2006.173.11:49:33.53#ibcon#flushed, iclass 34, count 0 2006.173.11:49:33.53#ibcon#about to write, iclass 34, count 0 2006.173.11:49:33.53#ibcon#wrote, iclass 34, count 0 2006.173.11:49:33.53#ibcon#about to read 3, iclass 34, count 0 2006.173.11:49:33.55#ibcon#read 3, iclass 34, count 0 2006.173.11:49:33.55#ibcon#about to read 4, iclass 34, count 0 2006.173.11:49:33.55#ibcon#read 4, iclass 34, count 0 2006.173.11:49:33.55#ibcon#about to read 5, iclass 34, count 0 2006.173.11:49:33.55#ibcon#read 5, iclass 34, count 0 2006.173.11:49:33.55#ibcon#about to read 6, iclass 34, count 0 2006.173.11:49:33.55#ibcon#read 6, iclass 34, count 0 2006.173.11:49:33.55#ibcon#end of sib2, iclass 34, count 0 2006.173.11:49:33.55#ibcon#*mode == 0, iclass 34, count 0 2006.173.11:49:33.55#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.11:49:33.55#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.11:49:33.55#ibcon#*before write, iclass 34, count 0 2006.173.11:49:33.55#ibcon#enter sib2, iclass 34, count 0 2006.173.11:49:33.55#ibcon#flushed, iclass 34, count 0 2006.173.11:49:33.55#ibcon#about to write, iclass 34, count 0 2006.173.11:49:33.55#ibcon#wrote, iclass 34, count 0 2006.173.11:49:33.55#ibcon#about to read 3, iclass 34, count 0 2006.173.11:49:33.59#ibcon#read 3, iclass 34, count 0 2006.173.11:49:33.59#ibcon#about to read 4, iclass 34, count 0 2006.173.11:49:33.59#ibcon#read 4, iclass 34, count 0 2006.173.11:49:33.59#ibcon#about to read 5, iclass 34, count 0 2006.173.11:49:33.59#ibcon#read 5, iclass 34, count 0 2006.173.11:49:33.59#ibcon#about to read 6, iclass 34, count 0 2006.173.11:49:33.59#ibcon#read 6, iclass 34, count 0 2006.173.11:49:33.59#ibcon#end of sib2, iclass 34, count 0 2006.173.11:49:33.59#ibcon#*after write, iclass 34, count 0 2006.173.11:49:33.59#ibcon#*before return 0, iclass 34, count 0 2006.173.11:49:33.59#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.11:49:33.59#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.11:49:33.59#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.11:49:33.59#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.11:49:33.59$vck44/vb=6,4 2006.173.11:49:33.59#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.11:49:33.59#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.11:49:33.59#ibcon#ireg 11 cls_cnt 2 2006.173.11:49:33.59#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.11:49:33.65#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.11:49:33.65#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.11:49:33.65#ibcon#enter wrdev, iclass 36, count 2 2006.173.11:49:33.65#ibcon#first serial, iclass 36, count 2 2006.173.11:49:33.65#ibcon#enter sib2, iclass 36, count 2 2006.173.11:49:33.65#ibcon#flushed, iclass 36, count 2 2006.173.11:49:33.65#ibcon#about to write, iclass 36, count 2 2006.173.11:49:33.65#ibcon#wrote, iclass 36, count 2 2006.173.11:49:33.65#ibcon#about to read 3, iclass 36, count 2 2006.173.11:49:33.67#ibcon#read 3, iclass 36, count 2 2006.173.11:49:33.67#ibcon#about to read 4, iclass 36, count 2 2006.173.11:49:33.67#ibcon#read 4, iclass 36, count 2 2006.173.11:49:33.67#ibcon#about to read 5, iclass 36, count 2 2006.173.11:49:33.67#ibcon#read 5, iclass 36, count 2 2006.173.11:49:33.67#ibcon#about to read 6, iclass 36, count 2 2006.173.11:49:33.67#ibcon#read 6, iclass 36, count 2 2006.173.11:49:33.67#ibcon#end of sib2, iclass 36, count 2 2006.173.11:49:33.67#ibcon#*mode == 0, iclass 36, count 2 2006.173.11:49:33.67#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.11:49:33.67#ibcon#[27=AT06-04\r\n] 2006.173.11:49:33.67#ibcon#*before write, iclass 36, count 2 2006.173.11:49:33.67#ibcon#enter sib2, iclass 36, count 2 2006.173.11:49:33.67#ibcon#flushed, iclass 36, count 2 2006.173.11:49:33.67#ibcon#about to write, iclass 36, count 2 2006.173.11:49:33.67#ibcon#wrote, iclass 36, count 2 2006.173.11:49:33.67#ibcon#about to read 3, iclass 36, count 2 2006.173.11:49:33.70#ibcon#read 3, iclass 36, count 2 2006.173.11:49:33.70#ibcon#about to read 4, iclass 36, count 2 2006.173.11:49:33.70#ibcon#read 4, iclass 36, count 2 2006.173.11:49:33.70#ibcon#about to read 5, iclass 36, count 2 2006.173.11:49:33.70#ibcon#read 5, iclass 36, count 2 2006.173.11:49:33.70#ibcon#about to read 6, iclass 36, count 2 2006.173.11:49:33.70#ibcon#read 6, iclass 36, count 2 2006.173.11:49:33.70#ibcon#end of sib2, iclass 36, count 2 2006.173.11:49:33.70#ibcon#*after write, iclass 36, count 2 2006.173.11:49:33.70#ibcon#*before return 0, iclass 36, count 2 2006.173.11:49:33.70#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.11:49:33.70#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.11:49:33.70#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.11:49:33.70#ibcon#ireg 7 cls_cnt 0 2006.173.11:49:33.70#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.11:49:33.82#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.11:49:33.82#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.11:49:33.82#ibcon#enter wrdev, iclass 36, count 0 2006.173.11:49:33.82#ibcon#first serial, iclass 36, count 0 2006.173.11:49:33.82#ibcon#enter sib2, iclass 36, count 0 2006.173.11:49:33.82#ibcon#flushed, iclass 36, count 0 2006.173.11:49:33.82#ibcon#about to write, iclass 36, count 0 2006.173.11:49:33.82#ibcon#wrote, iclass 36, count 0 2006.173.11:49:33.82#ibcon#about to read 3, iclass 36, count 0 2006.173.11:49:33.84#ibcon#read 3, iclass 36, count 0 2006.173.11:49:33.84#ibcon#about to read 4, iclass 36, count 0 2006.173.11:49:33.84#ibcon#read 4, iclass 36, count 0 2006.173.11:49:33.84#ibcon#about to read 5, iclass 36, count 0 2006.173.11:49:33.84#ibcon#read 5, iclass 36, count 0 2006.173.11:49:33.84#ibcon#about to read 6, iclass 36, count 0 2006.173.11:49:33.84#ibcon#read 6, iclass 36, count 0 2006.173.11:49:33.84#ibcon#end of sib2, iclass 36, count 0 2006.173.11:49:33.84#ibcon#*mode == 0, iclass 36, count 0 2006.173.11:49:33.84#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.11:49:33.84#ibcon#[27=USB\r\n] 2006.173.11:49:33.84#ibcon#*before write, iclass 36, count 0 2006.173.11:49:33.84#ibcon#enter sib2, iclass 36, count 0 2006.173.11:49:33.84#ibcon#flushed, iclass 36, count 0 2006.173.11:49:33.84#ibcon#about to write, iclass 36, count 0 2006.173.11:49:33.84#ibcon#wrote, iclass 36, count 0 2006.173.11:49:33.84#ibcon#about to read 3, iclass 36, count 0 2006.173.11:49:33.87#ibcon#read 3, iclass 36, count 0 2006.173.11:49:33.87#ibcon#about to read 4, iclass 36, count 0 2006.173.11:49:33.87#ibcon#read 4, iclass 36, count 0 2006.173.11:49:33.87#ibcon#about to read 5, iclass 36, count 0 2006.173.11:49:33.87#ibcon#read 5, iclass 36, count 0 2006.173.11:49:33.87#ibcon#about to read 6, iclass 36, count 0 2006.173.11:49:33.87#ibcon#read 6, iclass 36, count 0 2006.173.11:49:33.87#ibcon#end of sib2, iclass 36, count 0 2006.173.11:49:33.87#ibcon#*after write, iclass 36, count 0 2006.173.11:49:33.87#ibcon#*before return 0, iclass 36, count 0 2006.173.11:49:33.87#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.11:49:33.87#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.11:49:33.87#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.11:49:33.87#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.11:49:33.87$vck44/vblo=7,734.99 2006.173.11:49:33.87#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.11:49:33.87#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.11:49:33.87#ibcon#ireg 17 cls_cnt 0 2006.173.11:49:33.87#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.11:49:33.87#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.11:49:33.87#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.11:49:33.87#ibcon#enter wrdev, iclass 38, count 0 2006.173.11:49:33.87#ibcon#first serial, iclass 38, count 0 2006.173.11:49:33.87#ibcon#enter sib2, iclass 38, count 0 2006.173.11:49:33.87#ibcon#flushed, iclass 38, count 0 2006.173.11:49:33.87#ibcon#about to write, iclass 38, count 0 2006.173.11:49:33.87#ibcon#wrote, iclass 38, count 0 2006.173.11:49:33.87#ibcon#about to read 3, iclass 38, count 0 2006.173.11:49:33.89#ibcon#read 3, iclass 38, count 0 2006.173.11:49:33.89#ibcon#about to read 4, iclass 38, count 0 2006.173.11:49:33.89#ibcon#read 4, iclass 38, count 0 2006.173.11:49:33.89#ibcon#about to read 5, iclass 38, count 0 2006.173.11:49:33.89#ibcon#read 5, iclass 38, count 0 2006.173.11:49:33.89#ibcon#about to read 6, iclass 38, count 0 2006.173.11:49:33.89#ibcon#read 6, iclass 38, count 0 2006.173.11:49:33.89#ibcon#end of sib2, iclass 38, count 0 2006.173.11:49:33.89#ibcon#*mode == 0, iclass 38, count 0 2006.173.11:49:33.89#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.11:49:33.89#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.11:49:33.89#ibcon#*before write, iclass 38, count 0 2006.173.11:49:33.89#ibcon#enter sib2, iclass 38, count 0 2006.173.11:49:33.89#ibcon#flushed, iclass 38, count 0 2006.173.11:49:33.89#ibcon#about to write, iclass 38, count 0 2006.173.11:49:33.89#ibcon#wrote, iclass 38, count 0 2006.173.11:49:33.89#ibcon#about to read 3, iclass 38, count 0 2006.173.11:49:33.93#ibcon#read 3, iclass 38, count 0 2006.173.11:49:33.93#ibcon#about to read 4, iclass 38, count 0 2006.173.11:49:33.93#ibcon#read 4, iclass 38, count 0 2006.173.11:49:33.93#ibcon#about to read 5, iclass 38, count 0 2006.173.11:49:33.93#ibcon#read 5, iclass 38, count 0 2006.173.11:49:33.93#ibcon#about to read 6, iclass 38, count 0 2006.173.11:49:33.93#ibcon#read 6, iclass 38, count 0 2006.173.11:49:33.93#ibcon#end of sib2, iclass 38, count 0 2006.173.11:49:33.93#ibcon#*after write, iclass 38, count 0 2006.173.11:49:33.93#ibcon#*before return 0, iclass 38, count 0 2006.173.11:49:33.93#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.11:49:33.93#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.11:49:33.93#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.11:49:33.93#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.11:49:33.93$vck44/vb=7,4 2006.173.11:49:33.93#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.11:49:33.93#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.11:49:33.93#ibcon#ireg 11 cls_cnt 2 2006.173.11:49:33.93#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.11:49:33.99#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.11:49:33.99#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.11:49:33.99#ibcon#enter wrdev, iclass 40, count 2 2006.173.11:49:33.99#ibcon#first serial, iclass 40, count 2 2006.173.11:49:33.99#ibcon#enter sib2, iclass 40, count 2 2006.173.11:49:33.99#ibcon#flushed, iclass 40, count 2 2006.173.11:49:33.99#ibcon#about to write, iclass 40, count 2 2006.173.11:49:33.99#ibcon#wrote, iclass 40, count 2 2006.173.11:49:33.99#ibcon#about to read 3, iclass 40, count 2 2006.173.11:49:34.01#ibcon#read 3, iclass 40, count 2 2006.173.11:49:34.01#ibcon#about to read 4, iclass 40, count 2 2006.173.11:49:34.01#ibcon#read 4, iclass 40, count 2 2006.173.11:49:34.01#ibcon#about to read 5, iclass 40, count 2 2006.173.11:49:34.01#ibcon#read 5, iclass 40, count 2 2006.173.11:49:34.01#ibcon#about to read 6, iclass 40, count 2 2006.173.11:49:34.01#ibcon#read 6, iclass 40, count 2 2006.173.11:49:34.01#ibcon#end of sib2, iclass 40, count 2 2006.173.11:49:34.01#ibcon#*mode == 0, iclass 40, count 2 2006.173.11:49:34.01#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.11:49:34.01#ibcon#[27=AT07-04\r\n] 2006.173.11:49:34.01#ibcon#*before write, iclass 40, count 2 2006.173.11:49:34.01#ibcon#enter sib2, iclass 40, count 2 2006.173.11:49:34.01#ibcon#flushed, iclass 40, count 2 2006.173.11:49:34.01#ibcon#about to write, iclass 40, count 2 2006.173.11:49:34.01#ibcon#wrote, iclass 40, count 2 2006.173.11:49:34.01#ibcon#about to read 3, iclass 40, count 2 2006.173.11:49:34.04#ibcon#read 3, iclass 40, count 2 2006.173.11:49:34.04#ibcon#about to read 4, iclass 40, count 2 2006.173.11:49:34.04#ibcon#read 4, iclass 40, count 2 2006.173.11:49:34.04#ibcon#about to read 5, iclass 40, count 2 2006.173.11:49:34.04#ibcon#read 5, iclass 40, count 2 2006.173.11:49:34.04#ibcon#about to read 6, iclass 40, count 2 2006.173.11:49:34.04#ibcon#read 6, iclass 40, count 2 2006.173.11:49:34.04#ibcon#end of sib2, iclass 40, count 2 2006.173.11:49:34.04#ibcon#*after write, iclass 40, count 2 2006.173.11:49:34.04#ibcon#*before return 0, iclass 40, count 2 2006.173.11:49:34.04#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.11:49:34.04#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.11:49:34.04#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.11:49:34.04#ibcon#ireg 7 cls_cnt 0 2006.173.11:49:34.04#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.11:49:34.16#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.11:49:34.16#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.11:49:34.16#ibcon#enter wrdev, iclass 40, count 0 2006.173.11:49:34.16#ibcon#first serial, iclass 40, count 0 2006.173.11:49:34.16#ibcon#enter sib2, iclass 40, count 0 2006.173.11:49:34.16#ibcon#flushed, iclass 40, count 0 2006.173.11:49:34.16#ibcon#about to write, iclass 40, count 0 2006.173.11:49:34.16#ibcon#wrote, iclass 40, count 0 2006.173.11:49:34.16#ibcon#about to read 3, iclass 40, count 0 2006.173.11:49:34.18#ibcon#read 3, iclass 40, count 0 2006.173.11:49:34.18#ibcon#about to read 4, iclass 40, count 0 2006.173.11:49:34.18#ibcon#read 4, iclass 40, count 0 2006.173.11:49:34.18#ibcon#about to read 5, iclass 40, count 0 2006.173.11:49:34.18#ibcon#read 5, iclass 40, count 0 2006.173.11:49:34.18#ibcon#about to read 6, iclass 40, count 0 2006.173.11:49:34.18#ibcon#read 6, iclass 40, count 0 2006.173.11:49:34.18#ibcon#end of sib2, iclass 40, count 0 2006.173.11:49:34.18#ibcon#*mode == 0, iclass 40, count 0 2006.173.11:49:34.18#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.11:49:34.18#ibcon#[27=USB\r\n] 2006.173.11:49:34.18#ibcon#*before write, iclass 40, count 0 2006.173.11:49:34.18#ibcon#enter sib2, iclass 40, count 0 2006.173.11:49:34.18#ibcon#flushed, iclass 40, count 0 2006.173.11:49:34.18#ibcon#about to write, iclass 40, count 0 2006.173.11:49:34.18#ibcon#wrote, iclass 40, count 0 2006.173.11:49:34.18#ibcon#about to read 3, iclass 40, count 0 2006.173.11:49:34.21#ibcon#read 3, iclass 40, count 0 2006.173.11:49:34.21#ibcon#about to read 4, iclass 40, count 0 2006.173.11:49:34.21#ibcon#read 4, iclass 40, count 0 2006.173.11:49:34.21#ibcon#about to read 5, iclass 40, count 0 2006.173.11:49:34.21#ibcon#read 5, iclass 40, count 0 2006.173.11:49:34.21#ibcon#about to read 6, iclass 40, count 0 2006.173.11:49:34.21#ibcon#read 6, iclass 40, count 0 2006.173.11:49:34.21#ibcon#end of sib2, iclass 40, count 0 2006.173.11:49:34.21#ibcon#*after write, iclass 40, count 0 2006.173.11:49:34.21#ibcon#*before return 0, iclass 40, count 0 2006.173.11:49:34.21#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.11:49:34.21#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.11:49:34.21#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.11:49:34.21#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.11:49:34.21$vck44/vblo=8,744.99 2006.173.11:49:34.21#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.11:49:34.21#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.11:49:34.21#ibcon#ireg 17 cls_cnt 0 2006.173.11:49:34.21#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.11:49:34.21#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.11:49:34.21#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.11:49:34.21#ibcon#enter wrdev, iclass 4, count 0 2006.173.11:49:34.21#ibcon#first serial, iclass 4, count 0 2006.173.11:49:34.21#ibcon#enter sib2, iclass 4, count 0 2006.173.11:49:34.21#ibcon#flushed, iclass 4, count 0 2006.173.11:49:34.21#ibcon#about to write, iclass 4, count 0 2006.173.11:49:34.21#ibcon#wrote, iclass 4, count 0 2006.173.11:49:34.21#ibcon#about to read 3, iclass 4, count 0 2006.173.11:49:34.23#ibcon#read 3, iclass 4, count 0 2006.173.11:49:34.23#ibcon#about to read 4, iclass 4, count 0 2006.173.11:49:34.23#ibcon#read 4, iclass 4, count 0 2006.173.11:49:34.23#ibcon#about to read 5, iclass 4, count 0 2006.173.11:49:34.23#ibcon#read 5, iclass 4, count 0 2006.173.11:49:34.23#ibcon#about to read 6, iclass 4, count 0 2006.173.11:49:34.23#ibcon#read 6, iclass 4, count 0 2006.173.11:49:34.23#ibcon#end of sib2, iclass 4, count 0 2006.173.11:49:34.23#ibcon#*mode == 0, iclass 4, count 0 2006.173.11:49:34.23#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.11:49:34.23#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.11:49:34.23#ibcon#*before write, iclass 4, count 0 2006.173.11:49:34.23#ibcon#enter sib2, iclass 4, count 0 2006.173.11:49:34.23#ibcon#flushed, iclass 4, count 0 2006.173.11:49:34.23#ibcon#about to write, iclass 4, count 0 2006.173.11:49:34.23#ibcon#wrote, iclass 4, count 0 2006.173.11:49:34.23#ibcon#about to read 3, iclass 4, count 0 2006.173.11:49:34.27#ibcon#read 3, iclass 4, count 0 2006.173.11:49:34.27#ibcon#about to read 4, iclass 4, count 0 2006.173.11:49:34.27#ibcon#read 4, iclass 4, count 0 2006.173.11:49:34.27#ibcon#about to read 5, iclass 4, count 0 2006.173.11:49:34.27#ibcon#read 5, iclass 4, count 0 2006.173.11:49:34.27#ibcon#about to read 6, iclass 4, count 0 2006.173.11:49:34.27#ibcon#read 6, iclass 4, count 0 2006.173.11:49:34.27#ibcon#end of sib2, iclass 4, count 0 2006.173.11:49:34.27#ibcon#*after write, iclass 4, count 0 2006.173.11:49:34.27#ibcon#*before return 0, iclass 4, count 0 2006.173.11:49:34.27#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.11:49:34.27#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.11:49:34.27#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.11:49:34.27#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.11:49:34.27$vck44/vb=8,4 2006.173.11:49:34.27#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.11:49:34.27#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.11:49:34.27#ibcon#ireg 11 cls_cnt 2 2006.173.11:49:34.27#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.11:49:34.33#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.11:49:34.33#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.11:49:34.33#ibcon#enter wrdev, iclass 6, count 2 2006.173.11:49:34.33#ibcon#first serial, iclass 6, count 2 2006.173.11:49:34.33#ibcon#enter sib2, iclass 6, count 2 2006.173.11:49:34.33#ibcon#flushed, iclass 6, count 2 2006.173.11:49:34.33#ibcon#about to write, iclass 6, count 2 2006.173.11:49:34.33#ibcon#wrote, iclass 6, count 2 2006.173.11:49:34.33#ibcon#about to read 3, iclass 6, count 2 2006.173.11:49:34.35#ibcon#read 3, iclass 6, count 2 2006.173.11:49:34.35#ibcon#about to read 4, iclass 6, count 2 2006.173.11:49:34.35#ibcon#read 4, iclass 6, count 2 2006.173.11:49:34.35#ibcon#about to read 5, iclass 6, count 2 2006.173.11:49:34.35#ibcon#read 5, iclass 6, count 2 2006.173.11:49:34.35#ibcon#about to read 6, iclass 6, count 2 2006.173.11:49:34.35#ibcon#read 6, iclass 6, count 2 2006.173.11:49:34.35#ibcon#end of sib2, iclass 6, count 2 2006.173.11:49:34.35#ibcon#*mode == 0, iclass 6, count 2 2006.173.11:49:34.35#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.11:49:34.35#ibcon#[27=AT08-04\r\n] 2006.173.11:49:34.35#ibcon#*before write, iclass 6, count 2 2006.173.11:49:34.35#ibcon#enter sib2, iclass 6, count 2 2006.173.11:49:34.35#ibcon#flushed, iclass 6, count 2 2006.173.11:49:34.35#ibcon#about to write, iclass 6, count 2 2006.173.11:49:34.35#ibcon#wrote, iclass 6, count 2 2006.173.11:49:34.35#ibcon#about to read 3, iclass 6, count 2 2006.173.11:49:34.38#ibcon#read 3, iclass 6, count 2 2006.173.11:49:34.38#ibcon#about to read 4, iclass 6, count 2 2006.173.11:49:34.38#ibcon#read 4, iclass 6, count 2 2006.173.11:49:34.38#ibcon#about to read 5, iclass 6, count 2 2006.173.11:49:34.38#ibcon#read 5, iclass 6, count 2 2006.173.11:49:34.38#ibcon#about to read 6, iclass 6, count 2 2006.173.11:49:34.38#ibcon#read 6, iclass 6, count 2 2006.173.11:49:34.38#ibcon#end of sib2, iclass 6, count 2 2006.173.11:49:34.38#ibcon#*after write, iclass 6, count 2 2006.173.11:49:34.38#ibcon#*before return 0, iclass 6, count 2 2006.173.11:49:34.38#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.11:49:34.38#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.11:49:34.38#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.11:49:34.38#ibcon#ireg 7 cls_cnt 0 2006.173.11:49:34.38#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.11:49:34.50#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.11:49:34.50#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.11:49:34.50#ibcon#enter wrdev, iclass 6, count 0 2006.173.11:49:34.50#ibcon#first serial, iclass 6, count 0 2006.173.11:49:34.50#ibcon#enter sib2, iclass 6, count 0 2006.173.11:49:34.50#ibcon#flushed, iclass 6, count 0 2006.173.11:49:34.50#ibcon#about to write, iclass 6, count 0 2006.173.11:49:34.50#ibcon#wrote, iclass 6, count 0 2006.173.11:49:34.50#ibcon#about to read 3, iclass 6, count 0 2006.173.11:49:34.52#ibcon#read 3, iclass 6, count 0 2006.173.11:49:34.52#ibcon#about to read 4, iclass 6, count 0 2006.173.11:49:34.52#ibcon#read 4, iclass 6, count 0 2006.173.11:49:34.52#ibcon#about to read 5, iclass 6, count 0 2006.173.11:49:34.52#ibcon#read 5, iclass 6, count 0 2006.173.11:49:34.52#ibcon#about to read 6, iclass 6, count 0 2006.173.11:49:34.52#ibcon#read 6, iclass 6, count 0 2006.173.11:49:34.52#ibcon#end of sib2, iclass 6, count 0 2006.173.11:49:34.52#ibcon#*mode == 0, iclass 6, count 0 2006.173.11:49:34.52#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.11:49:34.52#ibcon#[27=USB\r\n] 2006.173.11:49:34.52#ibcon#*before write, iclass 6, count 0 2006.173.11:49:34.52#ibcon#enter sib2, iclass 6, count 0 2006.173.11:49:34.52#ibcon#flushed, iclass 6, count 0 2006.173.11:49:34.52#ibcon#about to write, iclass 6, count 0 2006.173.11:49:34.52#ibcon#wrote, iclass 6, count 0 2006.173.11:49:34.52#ibcon#about to read 3, iclass 6, count 0 2006.173.11:49:34.55#ibcon#read 3, iclass 6, count 0 2006.173.11:49:34.55#ibcon#about to read 4, iclass 6, count 0 2006.173.11:49:34.55#ibcon#read 4, iclass 6, count 0 2006.173.11:49:34.55#ibcon#about to read 5, iclass 6, count 0 2006.173.11:49:34.55#ibcon#read 5, iclass 6, count 0 2006.173.11:49:34.55#ibcon#about to read 6, iclass 6, count 0 2006.173.11:49:34.55#ibcon#read 6, iclass 6, count 0 2006.173.11:49:34.55#ibcon#end of sib2, iclass 6, count 0 2006.173.11:49:34.55#ibcon#*after write, iclass 6, count 0 2006.173.11:49:34.55#ibcon#*before return 0, iclass 6, count 0 2006.173.11:49:34.55#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.11:49:34.55#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.11:49:34.55#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.11:49:34.55#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.11:49:34.55$vck44/vabw=wide 2006.173.11:49:34.55#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.11:49:34.55#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.11:49:34.55#ibcon#ireg 8 cls_cnt 0 2006.173.11:49:34.55#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.11:49:34.55#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.11:49:34.55#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.11:49:34.55#ibcon#enter wrdev, iclass 10, count 0 2006.173.11:49:34.55#ibcon#first serial, iclass 10, count 0 2006.173.11:49:34.55#ibcon#enter sib2, iclass 10, count 0 2006.173.11:49:34.55#ibcon#flushed, iclass 10, count 0 2006.173.11:49:34.55#ibcon#about to write, iclass 10, count 0 2006.173.11:49:34.55#ibcon#wrote, iclass 10, count 0 2006.173.11:49:34.55#ibcon#about to read 3, iclass 10, count 0 2006.173.11:49:34.57#ibcon#read 3, iclass 10, count 0 2006.173.11:49:34.57#ibcon#about to read 4, iclass 10, count 0 2006.173.11:49:34.57#ibcon#read 4, iclass 10, count 0 2006.173.11:49:34.57#ibcon#about to read 5, iclass 10, count 0 2006.173.11:49:34.57#ibcon#read 5, iclass 10, count 0 2006.173.11:49:34.57#ibcon#about to read 6, iclass 10, count 0 2006.173.11:49:34.57#ibcon#read 6, iclass 10, count 0 2006.173.11:49:34.57#ibcon#end of sib2, iclass 10, count 0 2006.173.11:49:34.57#ibcon#*mode == 0, iclass 10, count 0 2006.173.11:49:34.57#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.11:49:34.57#ibcon#[25=BW32\r\n] 2006.173.11:49:34.57#ibcon#*before write, iclass 10, count 0 2006.173.11:49:34.57#ibcon#enter sib2, iclass 10, count 0 2006.173.11:49:34.57#ibcon#flushed, iclass 10, count 0 2006.173.11:49:34.57#ibcon#about to write, iclass 10, count 0 2006.173.11:49:34.57#ibcon#wrote, iclass 10, count 0 2006.173.11:49:34.57#ibcon#about to read 3, iclass 10, count 0 2006.173.11:49:34.60#ibcon#read 3, iclass 10, count 0 2006.173.11:49:34.60#ibcon#about to read 4, iclass 10, count 0 2006.173.11:49:34.60#ibcon#read 4, iclass 10, count 0 2006.173.11:49:34.60#ibcon#about to read 5, iclass 10, count 0 2006.173.11:49:34.60#ibcon#read 5, iclass 10, count 0 2006.173.11:49:34.60#ibcon#about to read 6, iclass 10, count 0 2006.173.11:49:34.60#ibcon#read 6, iclass 10, count 0 2006.173.11:49:34.60#ibcon#end of sib2, iclass 10, count 0 2006.173.11:49:34.60#ibcon#*after write, iclass 10, count 0 2006.173.11:49:34.60#ibcon#*before return 0, iclass 10, count 0 2006.173.11:49:34.60#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.11:49:34.60#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.11:49:34.60#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.11:49:34.60#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.11:49:34.60$vck44/vbbw=wide 2006.173.11:49:34.60#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.11:49:34.60#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.11:49:34.60#ibcon#ireg 8 cls_cnt 0 2006.173.11:49:34.60#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.11:49:34.67#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.11:49:34.67#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.11:49:34.67#ibcon#enter wrdev, iclass 12, count 0 2006.173.11:49:34.67#ibcon#first serial, iclass 12, count 0 2006.173.11:49:34.67#ibcon#enter sib2, iclass 12, count 0 2006.173.11:49:34.67#ibcon#flushed, iclass 12, count 0 2006.173.11:49:34.67#ibcon#about to write, iclass 12, count 0 2006.173.11:49:34.67#ibcon#wrote, iclass 12, count 0 2006.173.11:49:34.67#ibcon#about to read 3, iclass 12, count 0 2006.173.11:49:34.69#ibcon#read 3, iclass 12, count 0 2006.173.11:49:34.69#ibcon#about to read 4, iclass 12, count 0 2006.173.11:49:34.69#ibcon#read 4, iclass 12, count 0 2006.173.11:49:34.69#ibcon#about to read 5, iclass 12, count 0 2006.173.11:49:34.69#ibcon#read 5, iclass 12, count 0 2006.173.11:49:34.69#ibcon#about to read 6, iclass 12, count 0 2006.173.11:49:34.69#ibcon#read 6, iclass 12, count 0 2006.173.11:49:34.69#ibcon#end of sib2, iclass 12, count 0 2006.173.11:49:34.69#ibcon#*mode == 0, iclass 12, count 0 2006.173.11:49:34.69#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.11:49:34.69#ibcon#[27=BW32\r\n] 2006.173.11:49:34.69#ibcon#*before write, iclass 12, count 0 2006.173.11:49:34.69#ibcon#enter sib2, iclass 12, count 0 2006.173.11:49:34.69#ibcon#flushed, iclass 12, count 0 2006.173.11:49:34.69#ibcon#about to write, iclass 12, count 0 2006.173.11:49:34.69#ibcon#wrote, iclass 12, count 0 2006.173.11:49:34.69#ibcon#about to read 3, iclass 12, count 0 2006.173.11:49:34.72#ibcon#read 3, iclass 12, count 0 2006.173.11:49:34.72#ibcon#about to read 4, iclass 12, count 0 2006.173.11:49:34.72#ibcon#read 4, iclass 12, count 0 2006.173.11:49:34.72#ibcon#about to read 5, iclass 12, count 0 2006.173.11:49:34.72#ibcon#read 5, iclass 12, count 0 2006.173.11:49:34.72#ibcon#about to read 6, iclass 12, count 0 2006.173.11:49:34.72#ibcon#read 6, iclass 12, count 0 2006.173.11:49:34.72#ibcon#end of sib2, iclass 12, count 0 2006.173.11:49:34.72#ibcon#*after write, iclass 12, count 0 2006.173.11:49:34.72#ibcon#*before return 0, iclass 12, count 0 2006.173.11:49:34.72#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.11:49:34.72#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.11:49:34.72#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.11:49:34.72#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.11:49:34.72$setupk4/ifdk4 2006.173.11:49:34.72$ifdk4/lo= 2006.173.11:49:34.72$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.11:49:34.72$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.11:49:34.72$ifdk4/patch= 2006.173.11:49:34.72$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.11:49:34.72$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.11:49:34.72$setupk4/!*+20s 2006.173.11:49:35.30#abcon#<5=/16 0.4 1.6 22.12 931004.3\r\n> 2006.173.11:49:35.32#abcon#{5=INTERFACE CLEAR} 2006.173.11:49:35.38#abcon#[5=S1D000X0/0*\r\n] 2006.173.11:49:45.47#abcon#<5=/16 0.5 1.6 22.12 931004.3\r\n> 2006.173.11:49:45.49#abcon#{5=INTERFACE CLEAR} 2006.173.11:49:45.55#abcon#[5=S1D000X0/0*\r\n] 2006.173.11:49:49.23$setupk4/"tpicd 2006.173.11:49:49.23$setupk4/echo=off 2006.173.11:49:49.23$setupk4/xlog=off 2006.173.11:49:49.23:!2006.173.11:50:16 2006.173.11:50:13.14#trakl#Source acquired 2006.173.11:50:15.14#flagr#flagr/antenna,acquired 2006.173.11:50:16.00:preob 2006.173.11:50:16.14/onsource/TRACKING 2006.173.11:50:16.14:!2006.173.11:50:26 2006.173.11:50:26.00:"tape 2006.173.11:50:26.00:"st=record 2006.173.11:50:26.00:data_valid=on 2006.173.11:50:26.00:midob 2006.173.11:50:27.14/onsource/TRACKING 2006.173.11:50:27.14/wx/22.12,1004.3,93 2006.173.11:50:27.32/cable/+6.5041E-03 2006.173.11:50:28.41/va/01,07,usb,yes,41,44 2006.173.11:50:28.41/va/02,06,usb,yes,41,42 2006.173.11:50:28.41/va/03,05,usb,yes,52,54 2006.173.11:50:28.41/va/04,06,usb,yes,42,44 2006.173.11:50:28.41/va/05,04,usb,yes,33,34 2006.173.11:50:28.41/va/06,03,usb,yes,46,46 2006.173.11:50:28.41/va/07,04,usb,yes,37,39 2006.173.11:50:28.41/va/08,04,usb,yes,32,38 2006.173.11:50:28.64/valo/01,524.99,yes,locked 2006.173.11:50:28.64/valo/02,534.99,yes,locked 2006.173.11:50:28.64/valo/03,564.99,yes,locked 2006.173.11:50:28.64/valo/04,624.99,yes,locked 2006.173.11:50:28.64/valo/05,734.99,yes,locked 2006.173.11:50:28.64/valo/06,814.99,yes,locked 2006.173.11:50:28.64/valo/07,864.99,yes,locked 2006.173.11:50:28.64/valo/08,884.99,yes,locked 2006.173.11:50:29.73/vb/01,04,usb,yes,32,29 2006.173.11:50:29.73/vb/02,04,usb,yes,34,34 2006.173.11:50:29.73/vb/03,04,usb,yes,31,34 2006.173.11:50:29.73/vb/04,04,usb,yes,36,35 2006.173.11:50:29.73/vb/05,04,usb,yes,28,31 2006.173.11:50:29.73/vb/06,04,usb,yes,33,29 2006.173.11:50:29.73/vb/07,04,usb,yes,32,32 2006.173.11:50:29.73/vb/08,04,usb,yes,30,33 2006.173.11:50:29.96/vblo/01,629.99,yes,locked 2006.173.11:50:29.96/vblo/02,634.99,yes,locked 2006.173.11:50:29.96/vblo/03,649.99,yes,locked 2006.173.11:50:29.96/vblo/04,679.99,yes,locked 2006.173.11:50:29.96/vblo/05,709.99,yes,locked 2006.173.11:50:29.96/vblo/06,719.99,yes,locked 2006.173.11:50:29.96/vblo/07,734.99,yes,locked 2006.173.11:50:29.96/vblo/08,744.99,yes,locked 2006.173.11:50:30.11/vabw/8 2006.173.11:50:30.26/vbbw/8 2006.173.11:50:30.35/xfe/off,on,15.2 2006.173.11:50:30.73/ifatt/23,28,28,28 2006.173.11:50:31.08/fmout-gps/S +3.90E-07 2006.173.11:50:31.12:!2006.173.11:51:06 2006.173.11:51:06.00:data_valid=off 2006.173.11:51:06.00:"et 2006.173.11:51:06.00:!+3s 2006.173.11:51:09.01:"tape 2006.173.11:51:09.01:postob 2006.173.11:51:09.08/cable/+6.5046E-03 2006.173.11:51:09.08/wx/22.12,1004.3,93 2006.173.11:51:10.07/fmout-gps/S +3.91E-07 2006.173.11:51:10.07:scan_name=173-1155,jd0606,360 2006.173.11:51:10.07:source=1308+326,131028.66,322043.8,2000.0,cw 2006.173.11:51:11.14#flagr#flagr/antenna,new-source 2006.173.11:51:11.14:checkk5 2006.173.11:51:11.50/chk_autoobs//k5ts1/ autoobs is running! 2006.173.11:51:11.89/chk_autoobs//k5ts2/ autoobs is running! 2006.173.11:51:12.28/chk_autoobs//k5ts3/ autoobs is running! 2006.173.11:51:12.67/chk_autoobs//k5ts4/ autoobs is running! 2006.173.11:51:13.06/chk_obsdata//k5ts1/T1731150??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.173.11:51:13.46/chk_obsdata//k5ts2/T1731150??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.173.11:51:13.86/chk_obsdata//k5ts3/T1731150??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.173.11:51:14.26/chk_obsdata//k5ts4/T1731150??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.173.11:51:14.97/k5log//k5ts1_log_newline 2006.173.11:51:15.69/k5log//k5ts2_log_newline 2006.173.11:51:16.40/k5log//k5ts3_log_newline 2006.173.11:51:17.12/k5log//k5ts4_log_newline 2006.173.11:51:17.14/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.11:51:17.14:setupk4=1 2006.173.11:51:17.14$setupk4/echo=on 2006.173.11:51:17.14$setupk4/pcalon 2006.173.11:51:17.14$pcalon/"no phase cal control is implemented here 2006.173.11:51:17.14$setupk4/"tpicd=stop 2006.173.11:51:17.14$setupk4/"rec=synch_on 2006.173.11:51:17.14$setupk4/"rec_mode=128 2006.173.11:51:17.14$setupk4/!* 2006.173.11:51:17.14$setupk4/recpk4 2006.173.11:51:17.14$recpk4/recpatch= 2006.173.11:51:17.14$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.11:51:17.15$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.11:51:17.15$setupk4/vck44 2006.173.11:51:17.15$vck44/valo=1,524.99 2006.173.11:51:17.15#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.11:51:17.15#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.11:51:17.15#ibcon#ireg 17 cls_cnt 0 2006.173.11:51:17.15#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.11:51:17.15#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.11:51:17.15#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.11:51:17.15#ibcon#enter wrdev, iclass 25, count 0 2006.173.11:51:17.15#ibcon#first serial, iclass 25, count 0 2006.173.11:51:17.15#ibcon#enter sib2, iclass 25, count 0 2006.173.11:51:17.15#ibcon#flushed, iclass 25, count 0 2006.173.11:51:17.15#ibcon#about to write, iclass 25, count 0 2006.173.11:51:17.15#ibcon#wrote, iclass 25, count 0 2006.173.11:51:17.15#ibcon#about to read 3, iclass 25, count 0 2006.173.11:51:17.16#ibcon#read 3, iclass 25, count 0 2006.173.11:51:17.16#ibcon#about to read 4, iclass 25, count 0 2006.173.11:51:17.16#ibcon#read 4, iclass 25, count 0 2006.173.11:51:17.16#ibcon#about to read 5, iclass 25, count 0 2006.173.11:51:17.16#ibcon#read 5, iclass 25, count 0 2006.173.11:51:17.16#ibcon#about to read 6, iclass 25, count 0 2006.173.11:51:17.16#ibcon#read 6, iclass 25, count 0 2006.173.11:51:17.16#ibcon#end of sib2, iclass 25, count 0 2006.173.11:51:17.16#ibcon#*mode == 0, iclass 25, count 0 2006.173.11:51:17.16#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.11:51:17.16#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.11:51:17.16#ibcon#*before write, iclass 25, count 0 2006.173.11:51:17.16#ibcon#enter sib2, iclass 25, count 0 2006.173.11:51:17.16#ibcon#flushed, iclass 25, count 0 2006.173.11:51:17.16#ibcon#about to write, iclass 25, count 0 2006.173.11:51:17.16#ibcon#wrote, iclass 25, count 0 2006.173.11:51:17.16#ibcon#about to read 3, iclass 25, count 0 2006.173.11:51:17.21#ibcon#read 3, iclass 25, count 0 2006.173.11:51:17.21#ibcon#about to read 4, iclass 25, count 0 2006.173.11:51:17.21#ibcon#read 4, iclass 25, count 0 2006.173.11:51:17.21#ibcon#about to read 5, iclass 25, count 0 2006.173.11:51:17.21#ibcon#read 5, iclass 25, count 0 2006.173.11:51:17.21#ibcon#about to read 6, iclass 25, count 0 2006.173.11:51:17.21#ibcon#read 6, iclass 25, count 0 2006.173.11:51:17.21#ibcon#end of sib2, iclass 25, count 0 2006.173.11:51:17.21#ibcon#*after write, iclass 25, count 0 2006.173.11:51:17.21#ibcon#*before return 0, iclass 25, count 0 2006.173.11:51:17.21#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.11:51:17.21#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.11:51:17.21#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.11:51:17.21#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.11:51:17.21$vck44/va=1,7 2006.173.11:51:17.21#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.11:51:17.21#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.11:51:17.21#ibcon#ireg 11 cls_cnt 2 2006.173.11:51:17.21#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.11:51:17.21#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.11:51:17.21#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.11:51:17.21#ibcon#enter wrdev, iclass 27, count 2 2006.173.11:51:17.21#ibcon#first serial, iclass 27, count 2 2006.173.11:51:17.21#ibcon#enter sib2, iclass 27, count 2 2006.173.11:51:17.21#ibcon#flushed, iclass 27, count 2 2006.173.11:51:17.21#ibcon#about to write, iclass 27, count 2 2006.173.11:51:17.21#ibcon#wrote, iclass 27, count 2 2006.173.11:51:17.21#ibcon#about to read 3, iclass 27, count 2 2006.173.11:51:17.23#ibcon#read 3, iclass 27, count 2 2006.173.11:51:17.23#ibcon#about to read 4, iclass 27, count 2 2006.173.11:51:17.23#ibcon#read 4, iclass 27, count 2 2006.173.11:51:17.23#ibcon#about to read 5, iclass 27, count 2 2006.173.11:51:17.23#ibcon#read 5, iclass 27, count 2 2006.173.11:51:17.23#ibcon#about to read 6, iclass 27, count 2 2006.173.11:51:17.23#ibcon#read 6, iclass 27, count 2 2006.173.11:51:17.23#ibcon#end of sib2, iclass 27, count 2 2006.173.11:51:17.23#ibcon#*mode == 0, iclass 27, count 2 2006.173.11:51:17.23#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.11:51:17.23#ibcon#[25=AT01-07\r\n] 2006.173.11:51:17.23#ibcon#*before write, iclass 27, count 2 2006.173.11:51:17.23#ibcon#enter sib2, iclass 27, count 2 2006.173.11:51:17.23#ibcon#flushed, iclass 27, count 2 2006.173.11:51:17.23#ibcon#about to write, iclass 27, count 2 2006.173.11:51:17.23#ibcon#wrote, iclass 27, count 2 2006.173.11:51:17.23#ibcon#about to read 3, iclass 27, count 2 2006.173.11:51:17.26#ibcon#read 3, iclass 27, count 2 2006.173.11:51:17.26#ibcon#about to read 4, iclass 27, count 2 2006.173.11:51:17.26#ibcon#read 4, iclass 27, count 2 2006.173.11:51:17.26#ibcon#about to read 5, iclass 27, count 2 2006.173.11:51:17.26#ibcon#read 5, iclass 27, count 2 2006.173.11:51:17.26#ibcon#about to read 6, iclass 27, count 2 2006.173.11:51:17.26#ibcon#read 6, iclass 27, count 2 2006.173.11:51:17.26#ibcon#end of sib2, iclass 27, count 2 2006.173.11:51:17.26#ibcon#*after write, iclass 27, count 2 2006.173.11:51:17.26#ibcon#*before return 0, iclass 27, count 2 2006.173.11:51:17.26#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.11:51:17.26#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.11:51:17.26#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.11:51:17.26#ibcon#ireg 7 cls_cnt 0 2006.173.11:51:17.26#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.11:51:17.38#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.11:51:17.38#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.11:51:17.38#ibcon#enter wrdev, iclass 27, count 0 2006.173.11:51:17.38#ibcon#first serial, iclass 27, count 0 2006.173.11:51:17.38#ibcon#enter sib2, iclass 27, count 0 2006.173.11:51:17.38#ibcon#flushed, iclass 27, count 0 2006.173.11:51:17.38#ibcon#about to write, iclass 27, count 0 2006.173.11:51:17.38#ibcon#wrote, iclass 27, count 0 2006.173.11:51:17.38#ibcon#about to read 3, iclass 27, count 0 2006.173.11:51:17.40#ibcon#read 3, iclass 27, count 0 2006.173.11:51:17.40#ibcon#about to read 4, iclass 27, count 0 2006.173.11:51:17.40#ibcon#read 4, iclass 27, count 0 2006.173.11:51:17.40#ibcon#about to read 5, iclass 27, count 0 2006.173.11:51:17.40#ibcon#read 5, iclass 27, count 0 2006.173.11:51:17.40#ibcon#about to read 6, iclass 27, count 0 2006.173.11:51:17.40#ibcon#read 6, iclass 27, count 0 2006.173.11:51:17.40#ibcon#end of sib2, iclass 27, count 0 2006.173.11:51:17.40#ibcon#*mode == 0, iclass 27, count 0 2006.173.11:51:17.40#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.11:51:17.40#ibcon#[25=USB\r\n] 2006.173.11:51:17.40#ibcon#*before write, iclass 27, count 0 2006.173.11:51:17.40#ibcon#enter sib2, iclass 27, count 0 2006.173.11:51:17.40#ibcon#flushed, iclass 27, count 0 2006.173.11:51:17.40#ibcon#about to write, iclass 27, count 0 2006.173.11:51:17.40#ibcon#wrote, iclass 27, count 0 2006.173.11:51:17.40#ibcon#about to read 3, iclass 27, count 0 2006.173.11:51:17.43#ibcon#read 3, iclass 27, count 0 2006.173.11:51:17.43#ibcon#about to read 4, iclass 27, count 0 2006.173.11:51:17.43#ibcon#read 4, iclass 27, count 0 2006.173.11:51:17.43#ibcon#about to read 5, iclass 27, count 0 2006.173.11:51:17.43#ibcon#read 5, iclass 27, count 0 2006.173.11:51:17.43#ibcon#about to read 6, iclass 27, count 0 2006.173.11:51:17.43#ibcon#read 6, iclass 27, count 0 2006.173.11:51:17.43#ibcon#end of sib2, iclass 27, count 0 2006.173.11:51:17.43#ibcon#*after write, iclass 27, count 0 2006.173.11:51:17.43#ibcon#*before return 0, iclass 27, count 0 2006.173.11:51:17.43#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.11:51:17.43#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.11:51:17.43#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.11:51:17.43#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.11:51:17.43$vck44/valo=2,534.99 2006.173.11:51:17.43#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.11:51:17.43#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.11:51:17.43#ibcon#ireg 17 cls_cnt 0 2006.173.11:51:17.43#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.11:51:17.43#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.11:51:17.43#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.11:51:17.43#ibcon#enter wrdev, iclass 29, count 0 2006.173.11:51:17.43#ibcon#first serial, iclass 29, count 0 2006.173.11:51:17.43#ibcon#enter sib2, iclass 29, count 0 2006.173.11:51:17.43#ibcon#flushed, iclass 29, count 0 2006.173.11:51:17.43#ibcon#about to write, iclass 29, count 0 2006.173.11:51:17.43#ibcon#wrote, iclass 29, count 0 2006.173.11:51:17.43#ibcon#about to read 3, iclass 29, count 0 2006.173.11:51:17.45#ibcon#read 3, iclass 29, count 0 2006.173.11:51:17.45#ibcon#about to read 4, iclass 29, count 0 2006.173.11:51:17.45#ibcon#read 4, iclass 29, count 0 2006.173.11:51:17.45#ibcon#about to read 5, iclass 29, count 0 2006.173.11:51:17.45#ibcon#read 5, iclass 29, count 0 2006.173.11:51:17.45#ibcon#about to read 6, iclass 29, count 0 2006.173.11:51:17.45#ibcon#read 6, iclass 29, count 0 2006.173.11:51:17.45#ibcon#end of sib2, iclass 29, count 0 2006.173.11:51:17.45#ibcon#*mode == 0, iclass 29, count 0 2006.173.11:51:17.45#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.11:51:17.45#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.11:51:17.45#ibcon#*before write, iclass 29, count 0 2006.173.11:51:17.45#ibcon#enter sib2, iclass 29, count 0 2006.173.11:51:17.45#ibcon#flushed, iclass 29, count 0 2006.173.11:51:17.45#ibcon#about to write, iclass 29, count 0 2006.173.11:51:17.45#ibcon#wrote, iclass 29, count 0 2006.173.11:51:17.45#ibcon#about to read 3, iclass 29, count 0 2006.173.11:51:17.49#ibcon#read 3, iclass 29, count 0 2006.173.11:51:17.49#ibcon#about to read 4, iclass 29, count 0 2006.173.11:51:17.49#ibcon#read 4, iclass 29, count 0 2006.173.11:51:17.49#ibcon#about to read 5, iclass 29, count 0 2006.173.11:51:17.49#ibcon#read 5, iclass 29, count 0 2006.173.11:51:17.49#ibcon#about to read 6, iclass 29, count 0 2006.173.11:51:17.49#ibcon#read 6, iclass 29, count 0 2006.173.11:51:17.49#ibcon#end of sib2, iclass 29, count 0 2006.173.11:51:17.49#ibcon#*after write, iclass 29, count 0 2006.173.11:51:17.49#ibcon#*before return 0, iclass 29, count 0 2006.173.11:51:17.49#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.11:51:17.49#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.11:51:17.49#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.11:51:17.49#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.11:51:17.49$vck44/va=2,6 2006.173.11:51:17.49#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.11:51:17.49#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.11:51:17.49#ibcon#ireg 11 cls_cnt 2 2006.173.11:51:17.49#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.11:51:17.55#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.11:51:17.55#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.11:51:17.55#ibcon#enter wrdev, iclass 31, count 2 2006.173.11:51:17.55#ibcon#first serial, iclass 31, count 2 2006.173.11:51:17.55#ibcon#enter sib2, iclass 31, count 2 2006.173.11:51:17.55#ibcon#flushed, iclass 31, count 2 2006.173.11:51:17.55#ibcon#about to write, iclass 31, count 2 2006.173.11:51:17.55#ibcon#wrote, iclass 31, count 2 2006.173.11:51:17.55#ibcon#about to read 3, iclass 31, count 2 2006.173.11:51:17.57#ibcon#read 3, iclass 31, count 2 2006.173.11:51:17.57#ibcon#about to read 4, iclass 31, count 2 2006.173.11:51:17.57#ibcon#read 4, iclass 31, count 2 2006.173.11:51:17.57#ibcon#about to read 5, iclass 31, count 2 2006.173.11:51:17.57#ibcon#read 5, iclass 31, count 2 2006.173.11:51:17.57#ibcon#about to read 6, iclass 31, count 2 2006.173.11:51:17.57#ibcon#read 6, iclass 31, count 2 2006.173.11:51:17.57#ibcon#end of sib2, iclass 31, count 2 2006.173.11:51:17.57#ibcon#*mode == 0, iclass 31, count 2 2006.173.11:51:17.57#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.11:51:17.57#ibcon#[25=AT02-06\r\n] 2006.173.11:51:17.57#ibcon#*before write, iclass 31, count 2 2006.173.11:51:17.57#ibcon#enter sib2, iclass 31, count 2 2006.173.11:51:17.57#ibcon#flushed, iclass 31, count 2 2006.173.11:51:17.57#ibcon#about to write, iclass 31, count 2 2006.173.11:51:17.57#ibcon#wrote, iclass 31, count 2 2006.173.11:51:17.57#ibcon#about to read 3, iclass 31, count 2 2006.173.11:51:17.60#ibcon#read 3, iclass 31, count 2 2006.173.11:51:17.60#ibcon#about to read 4, iclass 31, count 2 2006.173.11:51:17.60#ibcon#read 4, iclass 31, count 2 2006.173.11:51:17.60#ibcon#about to read 5, iclass 31, count 2 2006.173.11:51:17.60#ibcon#read 5, iclass 31, count 2 2006.173.11:51:17.60#ibcon#about to read 6, iclass 31, count 2 2006.173.11:51:17.60#ibcon#read 6, iclass 31, count 2 2006.173.11:51:17.60#ibcon#end of sib2, iclass 31, count 2 2006.173.11:51:17.60#ibcon#*after write, iclass 31, count 2 2006.173.11:51:17.60#ibcon#*before return 0, iclass 31, count 2 2006.173.11:51:17.60#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.11:51:17.60#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.11:51:17.60#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.11:51:17.60#ibcon#ireg 7 cls_cnt 0 2006.173.11:51:17.60#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.11:51:17.72#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.11:51:17.72#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.11:51:17.72#ibcon#enter wrdev, iclass 31, count 0 2006.173.11:51:17.72#ibcon#first serial, iclass 31, count 0 2006.173.11:51:17.72#ibcon#enter sib2, iclass 31, count 0 2006.173.11:51:17.72#ibcon#flushed, iclass 31, count 0 2006.173.11:51:17.72#ibcon#about to write, iclass 31, count 0 2006.173.11:51:17.72#ibcon#wrote, iclass 31, count 0 2006.173.11:51:17.72#ibcon#about to read 3, iclass 31, count 0 2006.173.11:51:17.74#ibcon#read 3, iclass 31, count 0 2006.173.11:51:17.74#ibcon#about to read 4, iclass 31, count 0 2006.173.11:51:17.74#ibcon#read 4, iclass 31, count 0 2006.173.11:51:17.74#ibcon#about to read 5, iclass 31, count 0 2006.173.11:51:17.74#ibcon#read 5, iclass 31, count 0 2006.173.11:51:17.74#ibcon#about to read 6, iclass 31, count 0 2006.173.11:51:17.74#ibcon#read 6, iclass 31, count 0 2006.173.11:51:17.74#ibcon#end of sib2, iclass 31, count 0 2006.173.11:51:17.74#ibcon#*mode == 0, iclass 31, count 0 2006.173.11:51:17.74#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.11:51:17.74#ibcon#[25=USB\r\n] 2006.173.11:51:17.74#ibcon#*before write, iclass 31, count 0 2006.173.11:51:17.74#ibcon#enter sib2, iclass 31, count 0 2006.173.11:51:17.74#ibcon#flushed, iclass 31, count 0 2006.173.11:51:17.74#ibcon#about to write, iclass 31, count 0 2006.173.11:51:17.74#ibcon#wrote, iclass 31, count 0 2006.173.11:51:17.74#ibcon#about to read 3, iclass 31, count 0 2006.173.11:51:17.77#ibcon#read 3, iclass 31, count 0 2006.173.11:51:17.77#ibcon#about to read 4, iclass 31, count 0 2006.173.11:51:17.77#ibcon#read 4, iclass 31, count 0 2006.173.11:51:17.77#ibcon#about to read 5, iclass 31, count 0 2006.173.11:51:17.77#ibcon#read 5, iclass 31, count 0 2006.173.11:51:17.77#ibcon#about to read 6, iclass 31, count 0 2006.173.11:51:17.77#ibcon#read 6, iclass 31, count 0 2006.173.11:51:17.77#ibcon#end of sib2, iclass 31, count 0 2006.173.11:51:17.77#ibcon#*after write, iclass 31, count 0 2006.173.11:51:17.77#ibcon#*before return 0, iclass 31, count 0 2006.173.11:51:17.77#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.11:51:17.77#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.11:51:17.77#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.11:51:17.77#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.11:51:17.77$vck44/valo=3,564.99 2006.173.11:51:17.77#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.11:51:17.77#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.11:51:17.77#ibcon#ireg 17 cls_cnt 0 2006.173.11:51:17.77#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.11:51:17.77#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.11:51:17.77#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.11:51:17.77#ibcon#enter wrdev, iclass 33, count 0 2006.173.11:51:17.77#ibcon#first serial, iclass 33, count 0 2006.173.11:51:17.77#ibcon#enter sib2, iclass 33, count 0 2006.173.11:51:17.77#ibcon#flushed, iclass 33, count 0 2006.173.11:51:17.77#ibcon#about to write, iclass 33, count 0 2006.173.11:51:17.77#ibcon#wrote, iclass 33, count 0 2006.173.11:51:17.77#ibcon#about to read 3, iclass 33, count 0 2006.173.11:51:17.79#ibcon#read 3, iclass 33, count 0 2006.173.11:51:17.79#ibcon#about to read 4, iclass 33, count 0 2006.173.11:51:17.79#ibcon#read 4, iclass 33, count 0 2006.173.11:51:17.79#ibcon#about to read 5, iclass 33, count 0 2006.173.11:51:17.79#ibcon#read 5, iclass 33, count 0 2006.173.11:51:17.79#ibcon#about to read 6, iclass 33, count 0 2006.173.11:51:17.79#ibcon#read 6, iclass 33, count 0 2006.173.11:51:17.79#ibcon#end of sib2, iclass 33, count 0 2006.173.11:51:17.79#ibcon#*mode == 0, iclass 33, count 0 2006.173.11:51:17.79#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.11:51:17.79#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.11:51:17.79#ibcon#*before write, iclass 33, count 0 2006.173.11:51:17.79#ibcon#enter sib2, iclass 33, count 0 2006.173.11:51:17.79#ibcon#flushed, iclass 33, count 0 2006.173.11:51:17.79#ibcon#about to write, iclass 33, count 0 2006.173.11:51:17.79#ibcon#wrote, iclass 33, count 0 2006.173.11:51:17.79#ibcon#about to read 3, iclass 33, count 0 2006.173.11:51:17.83#ibcon#read 3, iclass 33, count 0 2006.173.11:51:17.83#ibcon#about to read 4, iclass 33, count 0 2006.173.11:51:17.83#ibcon#read 4, iclass 33, count 0 2006.173.11:51:17.83#ibcon#about to read 5, iclass 33, count 0 2006.173.11:51:17.83#ibcon#read 5, iclass 33, count 0 2006.173.11:51:17.83#ibcon#about to read 6, iclass 33, count 0 2006.173.11:51:17.83#ibcon#read 6, iclass 33, count 0 2006.173.11:51:17.83#ibcon#end of sib2, iclass 33, count 0 2006.173.11:51:17.83#ibcon#*after write, iclass 33, count 0 2006.173.11:51:17.83#ibcon#*before return 0, iclass 33, count 0 2006.173.11:51:17.83#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.11:51:17.83#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.11:51:17.83#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.11:51:17.83#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.11:51:17.83$vck44/va=3,5 2006.173.11:51:17.83#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.11:51:17.83#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.11:51:17.83#ibcon#ireg 11 cls_cnt 2 2006.173.11:51:17.83#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.11:51:17.89#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.11:51:17.89#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.11:51:17.89#ibcon#enter wrdev, iclass 35, count 2 2006.173.11:51:17.89#ibcon#first serial, iclass 35, count 2 2006.173.11:51:17.89#ibcon#enter sib2, iclass 35, count 2 2006.173.11:51:17.89#ibcon#flushed, iclass 35, count 2 2006.173.11:51:17.89#ibcon#about to write, iclass 35, count 2 2006.173.11:51:17.89#ibcon#wrote, iclass 35, count 2 2006.173.11:51:17.89#ibcon#about to read 3, iclass 35, count 2 2006.173.11:51:17.91#ibcon#read 3, iclass 35, count 2 2006.173.11:51:17.91#ibcon#about to read 4, iclass 35, count 2 2006.173.11:51:17.91#ibcon#read 4, iclass 35, count 2 2006.173.11:51:17.91#ibcon#about to read 5, iclass 35, count 2 2006.173.11:51:17.91#ibcon#read 5, iclass 35, count 2 2006.173.11:51:17.91#ibcon#about to read 6, iclass 35, count 2 2006.173.11:51:17.91#ibcon#read 6, iclass 35, count 2 2006.173.11:51:17.91#ibcon#end of sib2, iclass 35, count 2 2006.173.11:51:17.91#ibcon#*mode == 0, iclass 35, count 2 2006.173.11:51:17.91#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.11:51:17.91#ibcon#[25=AT03-05\r\n] 2006.173.11:51:17.91#ibcon#*before write, iclass 35, count 2 2006.173.11:51:17.91#ibcon#enter sib2, iclass 35, count 2 2006.173.11:51:17.91#ibcon#flushed, iclass 35, count 2 2006.173.11:51:17.91#ibcon#about to write, iclass 35, count 2 2006.173.11:51:17.91#ibcon#wrote, iclass 35, count 2 2006.173.11:51:17.91#ibcon#about to read 3, iclass 35, count 2 2006.173.11:51:17.94#ibcon#read 3, iclass 35, count 2 2006.173.11:51:17.94#ibcon#about to read 4, iclass 35, count 2 2006.173.11:51:17.94#ibcon#read 4, iclass 35, count 2 2006.173.11:51:17.94#ibcon#about to read 5, iclass 35, count 2 2006.173.11:51:17.94#ibcon#read 5, iclass 35, count 2 2006.173.11:51:17.94#ibcon#about to read 6, iclass 35, count 2 2006.173.11:51:17.94#ibcon#read 6, iclass 35, count 2 2006.173.11:51:17.94#ibcon#end of sib2, iclass 35, count 2 2006.173.11:51:17.94#ibcon#*after write, iclass 35, count 2 2006.173.11:51:17.94#ibcon#*before return 0, iclass 35, count 2 2006.173.11:51:17.94#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.11:51:17.94#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.11:51:17.94#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.11:51:17.94#ibcon#ireg 7 cls_cnt 0 2006.173.11:51:17.94#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.11:51:18.06#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.11:51:18.06#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.11:51:18.06#ibcon#enter wrdev, iclass 35, count 0 2006.173.11:51:18.06#ibcon#first serial, iclass 35, count 0 2006.173.11:51:18.06#ibcon#enter sib2, iclass 35, count 0 2006.173.11:51:18.06#ibcon#flushed, iclass 35, count 0 2006.173.11:51:18.06#ibcon#about to write, iclass 35, count 0 2006.173.11:51:18.06#ibcon#wrote, iclass 35, count 0 2006.173.11:51:18.06#ibcon#about to read 3, iclass 35, count 0 2006.173.11:51:18.08#ibcon#read 3, iclass 35, count 0 2006.173.11:51:18.08#ibcon#about to read 4, iclass 35, count 0 2006.173.11:51:18.08#ibcon#read 4, iclass 35, count 0 2006.173.11:51:18.08#ibcon#about to read 5, iclass 35, count 0 2006.173.11:51:18.08#ibcon#read 5, iclass 35, count 0 2006.173.11:51:18.08#ibcon#about to read 6, iclass 35, count 0 2006.173.11:51:18.08#ibcon#read 6, iclass 35, count 0 2006.173.11:51:18.08#ibcon#end of sib2, iclass 35, count 0 2006.173.11:51:18.08#ibcon#*mode == 0, iclass 35, count 0 2006.173.11:51:18.08#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.11:51:18.08#ibcon#[25=USB\r\n] 2006.173.11:51:18.08#ibcon#*before write, iclass 35, count 0 2006.173.11:51:18.08#ibcon#enter sib2, iclass 35, count 0 2006.173.11:51:18.08#ibcon#flushed, iclass 35, count 0 2006.173.11:51:18.08#ibcon#about to write, iclass 35, count 0 2006.173.11:51:18.08#ibcon#wrote, iclass 35, count 0 2006.173.11:51:18.08#ibcon#about to read 3, iclass 35, count 0 2006.173.11:51:18.11#ibcon#read 3, iclass 35, count 0 2006.173.11:51:18.11#ibcon#about to read 4, iclass 35, count 0 2006.173.11:51:18.11#ibcon#read 4, iclass 35, count 0 2006.173.11:51:18.11#ibcon#about to read 5, iclass 35, count 0 2006.173.11:51:18.11#ibcon#read 5, iclass 35, count 0 2006.173.11:51:18.11#ibcon#about to read 6, iclass 35, count 0 2006.173.11:51:18.11#ibcon#read 6, iclass 35, count 0 2006.173.11:51:18.11#ibcon#end of sib2, iclass 35, count 0 2006.173.11:51:18.11#ibcon#*after write, iclass 35, count 0 2006.173.11:51:18.11#ibcon#*before return 0, iclass 35, count 0 2006.173.11:51:18.11#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.11:51:18.11#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.11:51:18.11#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.11:51:18.11#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.11:51:18.11$vck44/valo=4,624.99 2006.173.11:51:18.11#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.11:51:18.11#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.11:51:18.11#ibcon#ireg 17 cls_cnt 0 2006.173.11:51:18.11#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.11:51:18.11#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.11:51:18.11#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.11:51:18.11#ibcon#enter wrdev, iclass 37, count 0 2006.173.11:51:18.11#ibcon#first serial, iclass 37, count 0 2006.173.11:51:18.11#ibcon#enter sib2, iclass 37, count 0 2006.173.11:51:18.11#ibcon#flushed, iclass 37, count 0 2006.173.11:51:18.11#ibcon#about to write, iclass 37, count 0 2006.173.11:51:18.11#ibcon#wrote, iclass 37, count 0 2006.173.11:51:18.11#ibcon#about to read 3, iclass 37, count 0 2006.173.11:51:18.13#ibcon#read 3, iclass 37, count 0 2006.173.11:51:18.13#ibcon#about to read 4, iclass 37, count 0 2006.173.11:51:18.13#ibcon#read 4, iclass 37, count 0 2006.173.11:51:18.13#ibcon#about to read 5, iclass 37, count 0 2006.173.11:51:18.13#ibcon#read 5, iclass 37, count 0 2006.173.11:51:18.13#ibcon#about to read 6, iclass 37, count 0 2006.173.11:51:18.13#ibcon#read 6, iclass 37, count 0 2006.173.11:51:18.13#ibcon#end of sib2, iclass 37, count 0 2006.173.11:51:18.13#ibcon#*mode == 0, iclass 37, count 0 2006.173.11:51:18.13#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.11:51:18.13#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.11:51:18.13#ibcon#*before write, iclass 37, count 0 2006.173.11:51:18.13#ibcon#enter sib2, iclass 37, count 0 2006.173.11:51:18.13#ibcon#flushed, iclass 37, count 0 2006.173.11:51:18.13#ibcon#about to write, iclass 37, count 0 2006.173.11:51:18.13#ibcon#wrote, iclass 37, count 0 2006.173.11:51:18.13#ibcon#about to read 3, iclass 37, count 0 2006.173.11:51:18.17#ibcon#read 3, iclass 37, count 0 2006.173.11:51:18.17#ibcon#about to read 4, iclass 37, count 0 2006.173.11:51:18.17#ibcon#read 4, iclass 37, count 0 2006.173.11:51:18.17#ibcon#about to read 5, iclass 37, count 0 2006.173.11:51:18.17#ibcon#read 5, iclass 37, count 0 2006.173.11:51:18.17#ibcon#about to read 6, iclass 37, count 0 2006.173.11:51:18.17#ibcon#read 6, iclass 37, count 0 2006.173.11:51:18.17#ibcon#end of sib2, iclass 37, count 0 2006.173.11:51:18.17#ibcon#*after write, iclass 37, count 0 2006.173.11:51:18.17#ibcon#*before return 0, iclass 37, count 0 2006.173.11:51:18.17#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.11:51:18.17#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.11:51:18.17#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.11:51:18.17#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.11:51:18.17$vck44/va=4,6 2006.173.11:51:18.17#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.11:51:18.17#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.11:51:18.17#ibcon#ireg 11 cls_cnt 2 2006.173.11:51:18.17#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.11:51:18.23#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.11:51:18.23#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.11:51:18.23#ibcon#enter wrdev, iclass 39, count 2 2006.173.11:51:18.23#ibcon#first serial, iclass 39, count 2 2006.173.11:51:18.23#ibcon#enter sib2, iclass 39, count 2 2006.173.11:51:18.23#ibcon#flushed, iclass 39, count 2 2006.173.11:51:18.23#ibcon#about to write, iclass 39, count 2 2006.173.11:51:18.23#ibcon#wrote, iclass 39, count 2 2006.173.11:51:18.23#ibcon#about to read 3, iclass 39, count 2 2006.173.11:51:18.25#ibcon#read 3, iclass 39, count 2 2006.173.11:51:18.25#ibcon#about to read 4, iclass 39, count 2 2006.173.11:51:18.25#ibcon#read 4, iclass 39, count 2 2006.173.11:51:18.25#ibcon#about to read 5, iclass 39, count 2 2006.173.11:51:18.25#ibcon#read 5, iclass 39, count 2 2006.173.11:51:18.25#ibcon#about to read 6, iclass 39, count 2 2006.173.11:51:18.25#ibcon#read 6, iclass 39, count 2 2006.173.11:51:18.25#ibcon#end of sib2, iclass 39, count 2 2006.173.11:51:18.25#ibcon#*mode == 0, iclass 39, count 2 2006.173.11:51:18.25#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.11:51:18.25#ibcon#[25=AT04-06\r\n] 2006.173.11:51:18.25#ibcon#*before write, iclass 39, count 2 2006.173.11:51:18.25#ibcon#enter sib2, iclass 39, count 2 2006.173.11:51:18.25#ibcon#flushed, iclass 39, count 2 2006.173.11:51:18.25#ibcon#about to write, iclass 39, count 2 2006.173.11:51:18.25#ibcon#wrote, iclass 39, count 2 2006.173.11:51:18.25#ibcon#about to read 3, iclass 39, count 2 2006.173.11:51:18.28#ibcon#read 3, iclass 39, count 2 2006.173.11:51:18.28#ibcon#about to read 4, iclass 39, count 2 2006.173.11:51:18.28#ibcon#read 4, iclass 39, count 2 2006.173.11:51:18.28#ibcon#about to read 5, iclass 39, count 2 2006.173.11:51:18.28#ibcon#read 5, iclass 39, count 2 2006.173.11:51:18.28#ibcon#about to read 6, iclass 39, count 2 2006.173.11:51:18.28#ibcon#read 6, iclass 39, count 2 2006.173.11:51:18.28#ibcon#end of sib2, iclass 39, count 2 2006.173.11:51:18.28#ibcon#*after write, iclass 39, count 2 2006.173.11:51:18.28#ibcon#*before return 0, iclass 39, count 2 2006.173.11:51:18.28#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.11:51:18.28#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.11:51:18.28#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.11:51:18.28#ibcon#ireg 7 cls_cnt 0 2006.173.11:51:18.28#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.11:51:18.40#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.11:51:18.40#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.11:51:18.40#ibcon#enter wrdev, iclass 39, count 0 2006.173.11:51:18.40#ibcon#first serial, iclass 39, count 0 2006.173.11:51:18.40#ibcon#enter sib2, iclass 39, count 0 2006.173.11:51:18.40#ibcon#flushed, iclass 39, count 0 2006.173.11:51:18.40#ibcon#about to write, iclass 39, count 0 2006.173.11:51:18.40#ibcon#wrote, iclass 39, count 0 2006.173.11:51:18.40#ibcon#about to read 3, iclass 39, count 0 2006.173.11:51:18.42#ibcon#read 3, iclass 39, count 0 2006.173.11:51:18.42#ibcon#about to read 4, iclass 39, count 0 2006.173.11:51:18.42#ibcon#read 4, iclass 39, count 0 2006.173.11:51:18.42#ibcon#about to read 5, iclass 39, count 0 2006.173.11:51:18.42#ibcon#read 5, iclass 39, count 0 2006.173.11:51:18.42#ibcon#about to read 6, iclass 39, count 0 2006.173.11:51:18.42#ibcon#read 6, iclass 39, count 0 2006.173.11:51:18.42#ibcon#end of sib2, iclass 39, count 0 2006.173.11:51:18.42#ibcon#*mode == 0, iclass 39, count 0 2006.173.11:51:18.42#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.11:51:18.42#ibcon#[25=USB\r\n] 2006.173.11:51:18.42#ibcon#*before write, iclass 39, count 0 2006.173.11:51:18.42#ibcon#enter sib2, iclass 39, count 0 2006.173.11:51:18.42#ibcon#flushed, iclass 39, count 0 2006.173.11:51:18.42#ibcon#about to write, iclass 39, count 0 2006.173.11:51:18.42#ibcon#wrote, iclass 39, count 0 2006.173.11:51:18.42#ibcon#about to read 3, iclass 39, count 0 2006.173.11:51:18.45#ibcon#read 3, iclass 39, count 0 2006.173.11:51:18.45#ibcon#about to read 4, iclass 39, count 0 2006.173.11:51:18.45#ibcon#read 4, iclass 39, count 0 2006.173.11:51:18.45#ibcon#about to read 5, iclass 39, count 0 2006.173.11:51:18.45#ibcon#read 5, iclass 39, count 0 2006.173.11:51:18.45#ibcon#about to read 6, iclass 39, count 0 2006.173.11:51:18.45#ibcon#read 6, iclass 39, count 0 2006.173.11:51:18.45#ibcon#end of sib2, iclass 39, count 0 2006.173.11:51:18.45#ibcon#*after write, iclass 39, count 0 2006.173.11:51:18.45#ibcon#*before return 0, iclass 39, count 0 2006.173.11:51:18.45#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.11:51:18.45#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.11:51:18.45#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.11:51:18.45#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.11:51:18.45$vck44/valo=5,734.99 2006.173.11:51:18.45#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.11:51:18.45#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.11:51:18.45#ibcon#ireg 17 cls_cnt 0 2006.173.11:51:18.45#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.11:51:18.45#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.11:51:18.45#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.11:51:18.45#ibcon#enter wrdev, iclass 3, count 0 2006.173.11:51:18.45#ibcon#first serial, iclass 3, count 0 2006.173.11:51:18.45#ibcon#enter sib2, iclass 3, count 0 2006.173.11:51:18.45#ibcon#flushed, iclass 3, count 0 2006.173.11:51:18.45#ibcon#about to write, iclass 3, count 0 2006.173.11:51:18.45#ibcon#wrote, iclass 3, count 0 2006.173.11:51:18.45#ibcon#about to read 3, iclass 3, count 0 2006.173.11:51:18.47#ibcon#read 3, iclass 3, count 0 2006.173.11:51:18.47#ibcon#about to read 4, iclass 3, count 0 2006.173.11:51:18.47#ibcon#read 4, iclass 3, count 0 2006.173.11:51:18.47#ibcon#about to read 5, iclass 3, count 0 2006.173.11:51:18.47#ibcon#read 5, iclass 3, count 0 2006.173.11:51:18.47#ibcon#about to read 6, iclass 3, count 0 2006.173.11:51:18.47#ibcon#read 6, iclass 3, count 0 2006.173.11:51:18.47#ibcon#end of sib2, iclass 3, count 0 2006.173.11:51:18.47#ibcon#*mode == 0, iclass 3, count 0 2006.173.11:51:18.47#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.11:51:18.47#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.11:51:18.47#ibcon#*before write, iclass 3, count 0 2006.173.11:51:18.47#ibcon#enter sib2, iclass 3, count 0 2006.173.11:51:18.47#ibcon#flushed, iclass 3, count 0 2006.173.11:51:18.47#ibcon#about to write, iclass 3, count 0 2006.173.11:51:18.47#ibcon#wrote, iclass 3, count 0 2006.173.11:51:18.47#ibcon#about to read 3, iclass 3, count 0 2006.173.11:51:18.51#ibcon#read 3, iclass 3, count 0 2006.173.11:51:18.51#ibcon#about to read 4, iclass 3, count 0 2006.173.11:51:18.51#ibcon#read 4, iclass 3, count 0 2006.173.11:51:18.51#ibcon#about to read 5, iclass 3, count 0 2006.173.11:51:18.51#ibcon#read 5, iclass 3, count 0 2006.173.11:51:18.51#ibcon#about to read 6, iclass 3, count 0 2006.173.11:51:18.51#ibcon#read 6, iclass 3, count 0 2006.173.11:51:18.51#ibcon#end of sib2, iclass 3, count 0 2006.173.11:51:18.51#ibcon#*after write, iclass 3, count 0 2006.173.11:51:18.51#ibcon#*before return 0, iclass 3, count 0 2006.173.11:51:18.51#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.11:51:18.51#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.11:51:18.51#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.11:51:18.51#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.11:51:18.51$vck44/va=5,4 2006.173.11:51:18.51#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.11:51:18.51#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.11:51:18.51#ibcon#ireg 11 cls_cnt 2 2006.173.11:51:18.51#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.11:51:18.57#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.11:51:18.57#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.11:51:18.57#ibcon#enter wrdev, iclass 5, count 2 2006.173.11:51:18.57#ibcon#first serial, iclass 5, count 2 2006.173.11:51:18.57#ibcon#enter sib2, iclass 5, count 2 2006.173.11:51:18.57#ibcon#flushed, iclass 5, count 2 2006.173.11:51:18.57#ibcon#about to write, iclass 5, count 2 2006.173.11:51:18.57#ibcon#wrote, iclass 5, count 2 2006.173.11:51:18.57#ibcon#about to read 3, iclass 5, count 2 2006.173.11:51:18.59#ibcon#read 3, iclass 5, count 2 2006.173.11:51:18.59#ibcon#about to read 4, iclass 5, count 2 2006.173.11:51:18.59#ibcon#read 4, iclass 5, count 2 2006.173.11:51:18.59#ibcon#about to read 5, iclass 5, count 2 2006.173.11:51:18.59#ibcon#read 5, iclass 5, count 2 2006.173.11:51:18.59#ibcon#about to read 6, iclass 5, count 2 2006.173.11:51:18.59#ibcon#read 6, iclass 5, count 2 2006.173.11:51:18.59#ibcon#end of sib2, iclass 5, count 2 2006.173.11:51:18.59#ibcon#*mode == 0, iclass 5, count 2 2006.173.11:51:18.59#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.11:51:18.59#ibcon#[25=AT05-04\r\n] 2006.173.11:51:18.59#ibcon#*before write, iclass 5, count 2 2006.173.11:51:18.59#ibcon#enter sib2, iclass 5, count 2 2006.173.11:51:18.59#ibcon#flushed, iclass 5, count 2 2006.173.11:51:18.59#ibcon#about to write, iclass 5, count 2 2006.173.11:51:18.59#ibcon#wrote, iclass 5, count 2 2006.173.11:51:18.59#ibcon#about to read 3, iclass 5, count 2 2006.173.11:51:18.62#ibcon#read 3, iclass 5, count 2 2006.173.11:51:18.62#ibcon#about to read 4, iclass 5, count 2 2006.173.11:51:18.62#ibcon#read 4, iclass 5, count 2 2006.173.11:51:18.62#ibcon#about to read 5, iclass 5, count 2 2006.173.11:51:18.62#ibcon#read 5, iclass 5, count 2 2006.173.11:51:18.62#ibcon#about to read 6, iclass 5, count 2 2006.173.11:51:18.62#ibcon#read 6, iclass 5, count 2 2006.173.11:51:18.62#ibcon#end of sib2, iclass 5, count 2 2006.173.11:51:18.62#ibcon#*after write, iclass 5, count 2 2006.173.11:51:18.62#ibcon#*before return 0, iclass 5, count 2 2006.173.11:51:18.62#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.11:51:18.62#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.11:51:18.62#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.11:51:18.62#ibcon#ireg 7 cls_cnt 0 2006.173.11:51:18.62#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.11:51:18.74#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.11:51:18.74#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.11:51:18.74#ibcon#enter wrdev, iclass 5, count 0 2006.173.11:51:18.74#ibcon#first serial, iclass 5, count 0 2006.173.11:51:18.74#ibcon#enter sib2, iclass 5, count 0 2006.173.11:51:18.74#ibcon#flushed, iclass 5, count 0 2006.173.11:51:18.74#ibcon#about to write, iclass 5, count 0 2006.173.11:51:18.74#ibcon#wrote, iclass 5, count 0 2006.173.11:51:18.74#ibcon#about to read 3, iclass 5, count 0 2006.173.11:51:18.76#ibcon#read 3, iclass 5, count 0 2006.173.11:51:18.76#ibcon#about to read 4, iclass 5, count 0 2006.173.11:51:18.76#ibcon#read 4, iclass 5, count 0 2006.173.11:51:18.76#ibcon#about to read 5, iclass 5, count 0 2006.173.11:51:18.76#ibcon#read 5, iclass 5, count 0 2006.173.11:51:18.76#ibcon#about to read 6, iclass 5, count 0 2006.173.11:51:18.76#ibcon#read 6, iclass 5, count 0 2006.173.11:51:18.76#ibcon#end of sib2, iclass 5, count 0 2006.173.11:51:18.76#ibcon#*mode == 0, iclass 5, count 0 2006.173.11:51:18.76#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.11:51:18.76#ibcon#[25=USB\r\n] 2006.173.11:51:18.76#ibcon#*before write, iclass 5, count 0 2006.173.11:51:18.76#ibcon#enter sib2, iclass 5, count 0 2006.173.11:51:18.76#ibcon#flushed, iclass 5, count 0 2006.173.11:51:18.76#ibcon#about to write, iclass 5, count 0 2006.173.11:51:18.76#ibcon#wrote, iclass 5, count 0 2006.173.11:51:18.76#ibcon#about to read 3, iclass 5, count 0 2006.173.11:51:18.79#ibcon#read 3, iclass 5, count 0 2006.173.11:51:18.79#ibcon#about to read 4, iclass 5, count 0 2006.173.11:51:18.79#ibcon#read 4, iclass 5, count 0 2006.173.11:51:18.79#ibcon#about to read 5, iclass 5, count 0 2006.173.11:51:18.79#ibcon#read 5, iclass 5, count 0 2006.173.11:51:18.79#ibcon#about to read 6, iclass 5, count 0 2006.173.11:51:18.79#ibcon#read 6, iclass 5, count 0 2006.173.11:51:18.79#ibcon#end of sib2, iclass 5, count 0 2006.173.11:51:18.79#ibcon#*after write, iclass 5, count 0 2006.173.11:51:18.79#ibcon#*before return 0, iclass 5, count 0 2006.173.11:51:18.79#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.11:51:18.79#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.11:51:18.79#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.11:51:18.79#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.11:51:18.79$vck44/valo=6,814.99 2006.173.11:51:18.79#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.11:51:18.79#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.11:51:18.79#ibcon#ireg 17 cls_cnt 0 2006.173.11:51:18.79#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.11:51:18.79#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.11:51:18.79#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.11:51:18.79#ibcon#enter wrdev, iclass 7, count 0 2006.173.11:51:18.79#ibcon#first serial, iclass 7, count 0 2006.173.11:51:18.79#ibcon#enter sib2, iclass 7, count 0 2006.173.11:51:18.79#ibcon#flushed, iclass 7, count 0 2006.173.11:51:18.79#ibcon#about to write, iclass 7, count 0 2006.173.11:51:18.79#ibcon#wrote, iclass 7, count 0 2006.173.11:51:18.79#ibcon#about to read 3, iclass 7, count 0 2006.173.11:51:18.81#ibcon#read 3, iclass 7, count 0 2006.173.11:51:18.81#ibcon#about to read 4, iclass 7, count 0 2006.173.11:51:18.81#ibcon#read 4, iclass 7, count 0 2006.173.11:51:18.81#ibcon#about to read 5, iclass 7, count 0 2006.173.11:51:18.81#ibcon#read 5, iclass 7, count 0 2006.173.11:51:18.81#ibcon#about to read 6, iclass 7, count 0 2006.173.11:51:18.81#ibcon#read 6, iclass 7, count 0 2006.173.11:51:18.81#ibcon#end of sib2, iclass 7, count 0 2006.173.11:51:18.81#ibcon#*mode == 0, iclass 7, count 0 2006.173.11:51:18.81#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.11:51:18.81#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.11:51:18.81#ibcon#*before write, iclass 7, count 0 2006.173.11:51:18.81#ibcon#enter sib2, iclass 7, count 0 2006.173.11:51:18.81#ibcon#flushed, iclass 7, count 0 2006.173.11:51:18.81#ibcon#about to write, iclass 7, count 0 2006.173.11:51:18.81#ibcon#wrote, iclass 7, count 0 2006.173.11:51:18.81#ibcon#about to read 3, iclass 7, count 0 2006.173.11:51:18.85#ibcon#read 3, iclass 7, count 0 2006.173.11:51:18.85#ibcon#about to read 4, iclass 7, count 0 2006.173.11:51:18.85#ibcon#read 4, iclass 7, count 0 2006.173.11:51:18.85#ibcon#about to read 5, iclass 7, count 0 2006.173.11:51:18.85#ibcon#read 5, iclass 7, count 0 2006.173.11:51:18.85#ibcon#about to read 6, iclass 7, count 0 2006.173.11:51:18.85#ibcon#read 6, iclass 7, count 0 2006.173.11:51:18.85#ibcon#end of sib2, iclass 7, count 0 2006.173.11:51:18.85#ibcon#*after write, iclass 7, count 0 2006.173.11:51:18.85#ibcon#*before return 0, iclass 7, count 0 2006.173.11:51:18.85#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.11:51:18.85#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.11:51:18.85#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.11:51:18.85#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.11:51:18.85$vck44/va=6,3 2006.173.11:51:18.85#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.11:51:18.85#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.11:51:18.85#ibcon#ireg 11 cls_cnt 2 2006.173.11:51:18.85#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.11:51:18.91#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.11:51:18.91#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.11:51:18.91#ibcon#enter wrdev, iclass 11, count 2 2006.173.11:51:18.91#ibcon#first serial, iclass 11, count 2 2006.173.11:51:18.91#ibcon#enter sib2, iclass 11, count 2 2006.173.11:51:18.91#ibcon#flushed, iclass 11, count 2 2006.173.11:51:18.91#ibcon#about to write, iclass 11, count 2 2006.173.11:51:18.91#ibcon#wrote, iclass 11, count 2 2006.173.11:51:18.91#ibcon#about to read 3, iclass 11, count 2 2006.173.11:51:18.93#ibcon#read 3, iclass 11, count 2 2006.173.11:51:18.93#ibcon#about to read 4, iclass 11, count 2 2006.173.11:51:18.93#ibcon#read 4, iclass 11, count 2 2006.173.11:51:18.93#ibcon#about to read 5, iclass 11, count 2 2006.173.11:51:18.93#ibcon#read 5, iclass 11, count 2 2006.173.11:51:18.93#ibcon#about to read 6, iclass 11, count 2 2006.173.11:51:18.93#ibcon#read 6, iclass 11, count 2 2006.173.11:51:18.93#ibcon#end of sib2, iclass 11, count 2 2006.173.11:51:18.93#ibcon#*mode == 0, iclass 11, count 2 2006.173.11:51:18.93#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.11:51:18.93#ibcon#[25=AT06-03\r\n] 2006.173.11:51:18.93#ibcon#*before write, iclass 11, count 2 2006.173.11:51:18.93#ibcon#enter sib2, iclass 11, count 2 2006.173.11:51:18.93#ibcon#flushed, iclass 11, count 2 2006.173.11:51:18.93#ibcon#about to write, iclass 11, count 2 2006.173.11:51:18.93#ibcon#wrote, iclass 11, count 2 2006.173.11:51:18.93#ibcon#about to read 3, iclass 11, count 2 2006.173.11:51:18.96#ibcon#read 3, iclass 11, count 2 2006.173.11:51:18.96#ibcon#about to read 4, iclass 11, count 2 2006.173.11:51:18.96#ibcon#read 4, iclass 11, count 2 2006.173.11:51:18.96#ibcon#about to read 5, iclass 11, count 2 2006.173.11:51:18.96#ibcon#read 5, iclass 11, count 2 2006.173.11:51:18.96#ibcon#about to read 6, iclass 11, count 2 2006.173.11:51:18.96#ibcon#read 6, iclass 11, count 2 2006.173.11:51:18.96#ibcon#end of sib2, iclass 11, count 2 2006.173.11:51:18.96#ibcon#*after write, iclass 11, count 2 2006.173.11:51:18.96#ibcon#*before return 0, iclass 11, count 2 2006.173.11:51:18.96#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.11:51:18.96#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.11:51:18.96#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.11:51:18.96#ibcon#ireg 7 cls_cnt 0 2006.173.11:51:18.96#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.11:51:19.08#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.11:51:19.08#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.11:51:19.08#ibcon#enter wrdev, iclass 11, count 0 2006.173.11:51:19.08#ibcon#first serial, iclass 11, count 0 2006.173.11:51:19.08#ibcon#enter sib2, iclass 11, count 0 2006.173.11:51:19.08#ibcon#flushed, iclass 11, count 0 2006.173.11:51:19.08#ibcon#about to write, iclass 11, count 0 2006.173.11:51:19.08#ibcon#wrote, iclass 11, count 0 2006.173.11:51:19.08#ibcon#about to read 3, iclass 11, count 0 2006.173.11:51:19.10#ibcon#read 3, iclass 11, count 0 2006.173.11:51:19.10#ibcon#about to read 4, iclass 11, count 0 2006.173.11:51:19.10#ibcon#read 4, iclass 11, count 0 2006.173.11:51:19.10#ibcon#about to read 5, iclass 11, count 0 2006.173.11:51:19.10#ibcon#read 5, iclass 11, count 0 2006.173.11:51:19.10#ibcon#about to read 6, iclass 11, count 0 2006.173.11:51:19.10#ibcon#read 6, iclass 11, count 0 2006.173.11:51:19.10#ibcon#end of sib2, iclass 11, count 0 2006.173.11:51:19.10#ibcon#*mode == 0, iclass 11, count 0 2006.173.11:51:19.10#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.11:51:19.10#ibcon#[25=USB\r\n] 2006.173.11:51:19.10#ibcon#*before write, iclass 11, count 0 2006.173.11:51:19.10#ibcon#enter sib2, iclass 11, count 0 2006.173.11:51:19.10#ibcon#flushed, iclass 11, count 0 2006.173.11:51:19.10#ibcon#about to write, iclass 11, count 0 2006.173.11:51:19.10#ibcon#wrote, iclass 11, count 0 2006.173.11:51:19.10#ibcon#about to read 3, iclass 11, count 0 2006.173.11:51:19.13#ibcon#read 3, iclass 11, count 0 2006.173.11:51:19.13#ibcon#about to read 4, iclass 11, count 0 2006.173.11:51:19.13#ibcon#read 4, iclass 11, count 0 2006.173.11:51:19.13#ibcon#about to read 5, iclass 11, count 0 2006.173.11:51:19.13#ibcon#read 5, iclass 11, count 0 2006.173.11:51:19.13#ibcon#about to read 6, iclass 11, count 0 2006.173.11:51:19.13#ibcon#read 6, iclass 11, count 0 2006.173.11:51:19.13#ibcon#end of sib2, iclass 11, count 0 2006.173.11:51:19.13#ibcon#*after write, iclass 11, count 0 2006.173.11:51:19.13#ibcon#*before return 0, iclass 11, count 0 2006.173.11:51:19.13#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.11:51:19.13#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.11:51:19.13#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.11:51:19.13#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.11:51:19.13$vck44/valo=7,864.99 2006.173.11:51:19.13#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.11:51:19.13#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.11:51:19.13#ibcon#ireg 17 cls_cnt 0 2006.173.11:51:19.13#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.11:51:19.13#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.11:51:19.13#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.11:51:19.13#ibcon#enter wrdev, iclass 13, count 0 2006.173.11:51:19.13#ibcon#first serial, iclass 13, count 0 2006.173.11:51:19.13#ibcon#enter sib2, iclass 13, count 0 2006.173.11:51:19.13#ibcon#flushed, iclass 13, count 0 2006.173.11:51:19.13#ibcon#about to write, iclass 13, count 0 2006.173.11:51:19.13#ibcon#wrote, iclass 13, count 0 2006.173.11:51:19.13#ibcon#about to read 3, iclass 13, count 0 2006.173.11:51:19.15#ibcon#read 3, iclass 13, count 0 2006.173.11:51:19.15#ibcon#about to read 4, iclass 13, count 0 2006.173.11:51:19.15#ibcon#read 4, iclass 13, count 0 2006.173.11:51:19.15#ibcon#about to read 5, iclass 13, count 0 2006.173.11:51:19.15#ibcon#read 5, iclass 13, count 0 2006.173.11:51:19.15#ibcon#about to read 6, iclass 13, count 0 2006.173.11:51:19.15#ibcon#read 6, iclass 13, count 0 2006.173.11:51:19.15#ibcon#end of sib2, iclass 13, count 0 2006.173.11:51:19.15#ibcon#*mode == 0, iclass 13, count 0 2006.173.11:51:19.15#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.11:51:19.15#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.11:51:19.15#ibcon#*before write, iclass 13, count 0 2006.173.11:51:19.15#ibcon#enter sib2, iclass 13, count 0 2006.173.11:51:19.15#ibcon#flushed, iclass 13, count 0 2006.173.11:51:19.15#ibcon#about to write, iclass 13, count 0 2006.173.11:51:19.15#ibcon#wrote, iclass 13, count 0 2006.173.11:51:19.15#ibcon#about to read 3, iclass 13, count 0 2006.173.11:51:19.19#ibcon#read 3, iclass 13, count 0 2006.173.11:51:19.19#ibcon#about to read 4, iclass 13, count 0 2006.173.11:51:19.19#ibcon#read 4, iclass 13, count 0 2006.173.11:51:19.19#ibcon#about to read 5, iclass 13, count 0 2006.173.11:51:19.19#ibcon#read 5, iclass 13, count 0 2006.173.11:51:19.19#ibcon#about to read 6, iclass 13, count 0 2006.173.11:51:19.19#ibcon#read 6, iclass 13, count 0 2006.173.11:51:19.19#ibcon#end of sib2, iclass 13, count 0 2006.173.11:51:19.19#ibcon#*after write, iclass 13, count 0 2006.173.11:51:19.19#ibcon#*before return 0, iclass 13, count 0 2006.173.11:51:19.19#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.11:51:19.19#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.11:51:19.19#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.11:51:19.19#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.11:51:19.19$vck44/va=7,4 2006.173.11:51:19.19#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.11:51:19.19#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.11:51:19.19#ibcon#ireg 11 cls_cnt 2 2006.173.11:51:19.19#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.11:51:19.25#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.11:51:19.25#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.11:51:19.25#ibcon#enter wrdev, iclass 15, count 2 2006.173.11:51:19.25#ibcon#first serial, iclass 15, count 2 2006.173.11:51:19.25#ibcon#enter sib2, iclass 15, count 2 2006.173.11:51:19.25#ibcon#flushed, iclass 15, count 2 2006.173.11:51:19.25#ibcon#about to write, iclass 15, count 2 2006.173.11:51:19.25#ibcon#wrote, iclass 15, count 2 2006.173.11:51:19.25#ibcon#about to read 3, iclass 15, count 2 2006.173.11:51:19.27#ibcon#read 3, iclass 15, count 2 2006.173.11:51:19.27#ibcon#about to read 4, iclass 15, count 2 2006.173.11:51:19.27#ibcon#read 4, iclass 15, count 2 2006.173.11:51:19.27#ibcon#about to read 5, iclass 15, count 2 2006.173.11:51:19.27#ibcon#read 5, iclass 15, count 2 2006.173.11:51:19.27#ibcon#about to read 6, iclass 15, count 2 2006.173.11:51:19.27#ibcon#read 6, iclass 15, count 2 2006.173.11:51:19.27#ibcon#end of sib2, iclass 15, count 2 2006.173.11:51:19.27#ibcon#*mode == 0, iclass 15, count 2 2006.173.11:51:19.27#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.11:51:19.27#ibcon#[25=AT07-04\r\n] 2006.173.11:51:19.27#ibcon#*before write, iclass 15, count 2 2006.173.11:51:19.27#ibcon#enter sib2, iclass 15, count 2 2006.173.11:51:19.27#ibcon#flushed, iclass 15, count 2 2006.173.11:51:19.27#ibcon#about to write, iclass 15, count 2 2006.173.11:51:19.27#ibcon#wrote, iclass 15, count 2 2006.173.11:51:19.27#ibcon#about to read 3, iclass 15, count 2 2006.173.11:51:19.30#ibcon#read 3, iclass 15, count 2 2006.173.11:51:19.30#ibcon#about to read 4, iclass 15, count 2 2006.173.11:51:19.30#ibcon#read 4, iclass 15, count 2 2006.173.11:51:19.30#ibcon#about to read 5, iclass 15, count 2 2006.173.11:51:19.30#ibcon#read 5, iclass 15, count 2 2006.173.11:51:19.30#ibcon#about to read 6, iclass 15, count 2 2006.173.11:51:19.30#ibcon#read 6, iclass 15, count 2 2006.173.11:51:19.30#ibcon#end of sib2, iclass 15, count 2 2006.173.11:51:19.30#ibcon#*after write, iclass 15, count 2 2006.173.11:51:19.30#ibcon#*before return 0, iclass 15, count 2 2006.173.11:51:19.30#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.11:51:19.30#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.11:51:19.30#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.11:51:19.30#ibcon#ireg 7 cls_cnt 0 2006.173.11:51:19.30#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.11:51:19.42#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.11:51:19.42#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.11:51:19.42#ibcon#enter wrdev, iclass 15, count 0 2006.173.11:51:19.42#ibcon#first serial, iclass 15, count 0 2006.173.11:51:19.42#ibcon#enter sib2, iclass 15, count 0 2006.173.11:51:19.42#ibcon#flushed, iclass 15, count 0 2006.173.11:51:19.42#ibcon#about to write, iclass 15, count 0 2006.173.11:51:19.42#ibcon#wrote, iclass 15, count 0 2006.173.11:51:19.42#ibcon#about to read 3, iclass 15, count 0 2006.173.11:51:19.44#ibcon#read 3, iclass 15, count 0 2006.173.11:51:19.44#ibcon#about to read 4, iclass 15, count 0 2006.173.11:51:19.44#ibcon#read 4, iclass 15, count 0 2006.173.11:51:19.44#ibcon#about to read 5, iclass 15, count 0 2006.173.11:51:19.44#ibcon#read 5, iclass 15, count 0 2006.173.11:51:19.44#ibcon#about to read 6, iclass 15, count 0 2006.173.11:51:19.44#ibcon#read 6, iclass 15, count 0 2006.173.11:51:19.44#ibcon#end of sib2, iclass 15, count 0 2006.173.11:51:19.44#ibcon#*mode == 0, iclass 15, count 0 2006.173.11:51:19.44#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.11:51:19.44#ibcon#[25=USB\r\n] 2006.173.11:51:19.44#ibcon#*before write, iclass 15, count 0 2006.173.11:51:19.44#ibcon#enter sib2, iclass 15, count 0 2006.173.11:51:19.44#ibcon#flushed, iclass 15, count 0 2006.173.11:51:19.44#ibcon#about to write, iclass 15, count 0 2006.173.11:51:19.44#ibcon#wrote, iclass 15, count 0 2006.173.11:51:19.44#ibcon#about to read 3, iclass 15, count 0 2006.173.11:51:19.47#ibcon#read 3, iclass 15, count 0 2006.173.11:51:19.47#ibcon#about to read 4, iclass 15, count 0 2006.173.11:51:19.47#ibcon#read 4, iclass 15, count 0 2006.173.11:51:19.47#ibcon#about to read 5, iclass 15, count 0 2006.173.11:51:19.47#ibcon#read 5, iclass 15, count 0 2006.173.11:51:19.47#ibcon#about to read 6, iclass 15, count 0 2006.173.11:51:19.47#ibcon#read 6, iclass 15, count 0 2006.173.11:51:19.47#ibcon#end of sib2, iclass 15, count 0 2006.173.11:51:19.47#ibcon#*after write, iclass 15, count 0 2006.173.11:51:19.47#ibcon#*before return 0, iclass 15, count 0 2006.173.11:51:19.47#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.11:51:19.47#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.11:51:19.47#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.11:51:19.47#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.11:51:19.47$vck44/valo=8,884.99 2006.173.11:51:19.47#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.11:51:19.47#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.11:51:19.47#ibcon#ireg 17 cls_cnt 0 2006.173.11:51:19.47#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.11:51:19.47#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.11:51:19.47#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.11:51:19.47#ibcon#enter wrdev, iclass 17, count 0 2006.173.11:51:19.47#ibcon#first serial, iclass 17, count 0 2006.173.11:51:19.47#ibcon#enter sib2, iclass 17, count 0 2006.173.11:51:19.47#ibcon#flushed, iclass 17, count 0 2006.173.11:51:19.47#ibcon#about to write, iclass 17, count 0 2006.173.11:51:19.47#ibcon#wrote, iclass 17, count 0 2006.173.11:51:19.47#ibcon#about to read 3, iclass 17, count 0 2006.173.11:51:19.49#ibcon#read 3, iclass 17, count 0 2006.173.11:51:19.49#ibcon#about to read 4, iclass 17, count 0 2006.173.11:51:19.49#ibcon#read 4, iclass 17, count 0 2006.173.11:51:19.49#ibcon#about to read 5, iclass 17, count 0 2006.173.11:51:19.49#ibcon#read 5, iclass 17, count 0 2006.173.11:51:19.49#ibcon#about to read 6, iclass 17, count 0 2006.173.11:51:19.49#ibcon#read 6, iclass 17, count 0 2006.173.11:51:19.49#ibcon#end of sib2, iclass 17, count 0 2006.173.11:51:19.49#ibcon#*mode == 0, iclass 17, count 0 2006.173.11:51:19.49#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.11:51:19.49#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.11:51:19.49#ibcon#*before write, iclass 17, count 0 2006.173.11:51:19.49#ibcon#enter sib2, iclass 17, count 0 2006.173.11:51:19.49#ibcon#flushed, iclass 17, count 0 2006.173.11:51:19.49#ibcon#about to write, iclass 17, count 0 2006.173.11:51:19.49#ibcon#wrote, iclass 17, count 0 2006.173.11:51:19.49#ibcon#about to read 3, iclass 17, count 0 2006.173.11:51:19.53#ibcon#read 3, iclass 17, count 0 2006.173.11:51:19.53#ibcon#about to read 4, iclass 17, count 0 2006.173.11:51:19.53#ibcon#read 4, iclass 17, count 0 2006.173.11:51:19.53#ibcon#about to read 5, iclass 17, count 0 2006.173.11:51:19.53#ibcon#read 5, iclass 17, count 0 2006.173.11:51:19.53#ibcon#about to read 6, iclass 17, count 0 2006.173.11:51:19.53#ibcon#read 6, iclass 17, count 0 2006.173.11:51:19.53#ibcon#end of sib2, iclass 17, count 0 2006.173.11:51:19.53#ibcon#*after write, iclass 17, count 0 2006.173.11:51:19.53#ibcon#*before return 0, iclass 17, count 0 2006.173.11:51:19.53#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.11:51:19.53#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.11:51:19.53#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.11:51:19.53#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.11:51:19.53$vck44/va=8,4 2006.173.11:51:19.53#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.11:51:19.53#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.11:51:19.53#ibcon#ireg 11 cls_cnt 2 2006.173.11:51:19.53#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.11:51:19.59#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.11:51:19.59#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.11:51:19.59#ibcon#enter wrdev, iclass 19, count 2 2006.173.11:51:19.59#ibcon#first serial, iclass 19, count 2 2006.173.11:51:19.59#ibcon#enter sib2, iclass 19, count 2 2006.173.11:51:19.59#ibcon#flushed, iclass 19, count 2 2006.173.11:51:19.59#ibcon#about to write, iclass 19, count 2 2006.173.11:51:19.59#ibcon#wrote, iclass 19, count 2 2006.173.11:51:19.59#ibcon#about to read 3, iclass 19, count 2 2006.173.11:51:19.61#ibcon#read 3, iclass 19, count 2 2006.173.11:51:19.61#ibcon#about to read 4, iclass 19, count 2 2006.173.11:51:19.61#ibcon#read 4, iclass 19, count 2 2006.173.11:51:19.61#ibcon#about to read 5, iclass 19, count 2 2006.173.11:51:19.61#ibcon#read 5, iclass 19, count 2 2006.173.11:51:19.61#ibcon#about to read 6, iclass 19, count 2 2006.173.11:51:19.61#ibcon#read 6, iclass 19, count 2 2006.173.11:51:19.61#ibcon#end of sib2, iclass 19, count 2 2006.173.11:51:19.61#ibcon#*mode == 0, iclass 19, count 2 2006.173.11:51:19.61#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.11:51:19.61#ibcon#[25=AT08-04\r\n] 2006.173.11:51:19.61#ibcon#*before write, iclass 19, count 2 2006.173.11:51:19.61#ibcon#enter sib2, iclass 19, count 2 2006.173.11:51:19.61#ibcon#flushed, iclass 19, count 2 2006.173.11:51:19.61#ibcon#about to write, iclass 19, count 2 2006.173.11:51:19.61#ibcon#wrote, iclass 19, count 2 2006.173.11:51:19.61#ibcon#about to read 3, iclass 19, count 2 2006.173.11:51:19.64#ibcon#read 3, iclass 19, count 2 2006.173.11:51:19.64#ibcon#about to read 4, iclass 19, count 2 2006.173.11:51:19.64#ibcon#read 4, iclass 19, count 2 2006.173.11:51:19.64#ibcon#about to read 5, iclass 19, count 2 2006.173.11:51:19.64#ibcon#read 5, iclass 19, count 2 2006.173.11:51:19.64#ibcon#about to read 6, iclass 19, count 2 2006.173.11:51:19.64#ibcon#read 6, iclass 19, count 2 2006.173.11:51:19.64#ibcon#end of sib2, iclass 19, count 2 2006.173.11:51:19.64#ibcon#*after write, iclass 19, count 2 2006.173.11:51:19.64#ibcon#*before return 0, iclass 19, count 2 2006.173.11:51:19.64#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.11:51:19.64#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.11:51:19.64#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.11:51:19.64#ibcon#ireg 7 cls_cnt 0 2006.173.11:51:19.64#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.11:51:19.76#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.11:51:19.76#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.11:51:19.76#ibcon#enter wrdev, iclass 19, count 0 2006.173.11:51:19.76#ibcon#first serial, iclass 19, count 0 2006.173.11:51:19.76#ibcon#enter sib2, iclass 19, count 0 2006.173.11:51:19.76#ibcon#flushed, iclass 19, count 0 2006.173.11:51:19.76#ibcon#about to write, iclass 19, count 0 2006.173.11:51:19.76#ibcon#wrote, iclass 19, count 0 2006.173.11:51:19.76#ibcon#about to read 3, iclass 19, count 0 2006.173.11:51:19.78#ibcon#read 3, iclass 19, count 0 2006.173.11:51:19.78#ibcon#about to read 4, iclass 19, count 0 2006.173.11:51:19.78#ibcon#read 4, iclass 19, count 0 2006.173.11:51:19.78#ibcon#about to read 5, iclass 19, count 0 2006.173.11:51:19.78#ibcon#read 5, iclass 19, count 0 2006.173.11:51:19.78#ibcon#about to read 6, iclass 19, count 0 2006.173.11:51:19.78#ibcon#read 6, iclass 19, count 0 2006.173.11:51:19.78#ibcon#end of sib2, iclass 19, count 0 2006.173.11:51:19.78#ibcon#*mode == 0, iclass 19, count 0 2006.173.11:51:19.78#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.11:51:19.78#ibcon#[25=USB\r\n] 2006.173.11:51:19.78#ibcon#*before write, iclass 19, count 0 2006.173.11:51:19.78#ibcon#enter sib2, iclass 19, count 0 2006.173.11:51:19.78#ibcon#flushed, iclass 19, count 0 2006.173.11:51:19.78#ibcon#about to write, iclass 19, count 0 2006.173.11:51:19.78#ibcon#wrote, iclass 19, count 0 2006.173.11:51:19.78#ibcon#about to read 3, iclass 19, count 0 2006.173.11:51:19.81#ibcon#read 3, iclass 19, count 0 2006.173.11:51:19.81#ibcon#about to read 4, iclass 19, count 0 2006.173.11:51:19.81#ibcon#read 4, iclass 19, count 0 2006.173.11:51:19.81#ibcon#about to read 5, iclass 19, count 0 2006.173.11:51:19.81#ibcon#read 5, iclass 19, count 0 2006.173.11:51:19.81#ibcon#about to read 6, iclass 19, count 0 2006.173.11:51:19.81#ibcon#read 6, iclass 19, count 0 2006.173.11:51:19.81#ibcon#end of sib2, iclass 19, count 0 2006.173.11:51:19.81#ibcon#*after write, iclass 19, count 0 2006.173.11:51:19.81#ibcon#*before return 0, iclass 19, count 0 2006.173.11:51:19.81#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.11:51:19.81#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.11:51:19.81#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.11:51:19.81#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.11:51:19.81$vck44/vblo=1,629.99 2006.173.11:51:19.81#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.11:51:19.81#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.11:51:19.81#ibcon#ireg 17 cls_cnt 0 2006.173.11:51:19.81#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.11:51:19.81#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.11:51:19.81#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.11:51:19.81#ibcon#enter wrdev, iclass 21, count 0 2006.173.11:51:19.81#ibcon#first serial, iclass 21, count 0 2006.173.11:51:19.81#ibcon#enter sib2, iclass 21, count 0 2006.173.11:51:19.81#ibcon#flushed, iclass 21, count 0 2006.173.11:51:19.81#ibcon#about to write, iclass 21, count 0 2006.173.11:51:19.81#ibcon#wrote, iclass 21, count 0 2006.173.11:51:19.81#ibcon#about to read 3, iclass 21, count 0 2006.173.11:51:19.83#ibcon#read 3, iclass 21, count 0 2006.173.11:51:19.83#ibcon#about to read 4, iclass 21, count 0 2006.173.11:51:19.83#ibcon#read 4, iclass 21, count 0 2006.173.11:51:19.83#ibcon#about to read 5, iclass 21, count 0 2006.173.11:51:19.83#ibcon#read 5, iclass 21, count 0 2006.173.11:51:19.83#ibcon#about to read 6, iclass 21, count 0 2006.173.11:51:19.83#ibcon#read 6, iclass 21, count 0 2006.173.11:51:19.83#ibcon#end of sib2, iclass 21, count 0 2006.173.11:51:19.83#ibcon#*mode == 0, iclass 21, count 0 2006.173.11:51:19.83#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.11:51:19.83#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.11:51:19.83#ibcon#*before write, iclass 21, count 0 2006.173.11:51:19.83#ibcon#enter sib2, iclass 21, count 0 2006.173.11:51:19.83#ibcon#flushed, iclass 21, count 0 2006.173.11:51:19.83#ibcon#about to write, iclass 21, count 0 2006.173.11:51:19.83#ibcon#wrote, iclass 21, count 0 2006.173.11:51:19.83#ibcon#about to read 3, iclass 21, count 0 2006.173.11:51:19.87#ibcon#read 3, iclass 21, count 0 2006.173.11:51:19.87#ibcon#about to read 4, iclass 21, count 0 2006.173.11:51:19.87#ibcon#read 4, iclass 21, count 0 2006.173.11:51:19.87#ibcon#about to read 5, iclass 21, count 0 2006.173.11:51:19.87#ibcon#read 5, iclass 21, count 0 2006.173.11:51:19.87#ibcon#about to read 6, iclass 21, count 0 2006.173.11:51:19.87#ibcon#read 6, iclass 21, count 0 2006.173.11:51:19.87#ibcon#end of sib2, iclass 21, count 0 2006.173.11:51:19.87#ibcon#*after write, iclass 21, count 0 2006.173.11:51:19.87#ibcon#*before return 0, iclass 21, count 0 2006.173.11:51:19.87#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.11:51:19.87#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.11:51:19.87#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.11:51:19.87#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.11:51:19.87$vck44/vb=1,4 2006.173.11:51:19.87#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.11:51:19.87#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.11:51:19.87#ibcon#ireg 11 cls_cnt 2 2006.173.11:51:19.87#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.11:51:19.87#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.11:51:19.87#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.11:51:19.87#ibcon#enter wrdev, iclass 23, count 2 2006.173.11:51:19.87#ibcon#first serial, iclass 23, count 2 2006.173.11:51:19.87#ibcon#enter sib2, iclass 23, count 2 2006.173.11:51:19.87#ibcon#flushed, iclass 23, count 2 2006.173.11:51:19.87#ibcon#about to write, iclass 23, count 2 2006.173.11:51:19.87#ibcon#wrote, iclass 23, count 2 2006.173.11:51:19.87#ibcon#about to read 3, iclass 23, count 2 2006.173.11:51:19.89#ibcon#read 3, iclass 23, count 2 2006.173.11:51:19.89#ibcon#about to read 4, iclass 23, count 2 2006.173.11:51:19.89#ibcon#read 4, iclass 23, count 2 2006.173.11:51:19.89#ibcon#about to read 5, iclass 23, count 2 2006.173.11:51:19.89#ibcon#read 5, iclass 23, count 2 2006.173.11:51:19.89#ibcon#about to read 6, iclass 23, count 2 2006.173.11:51:19.89#ibcon#read 6, iclass 23, count 2 2006.173.11:51:19.89#ibcon#end of sib2, iclass 23, count 2 2006.173.11:51:19.89#ibcon#*mode == 0, iclass 23, count 2 2006.173.11:51:19.89#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.11:51:19.89#ibcon#[27=AT01-04\r\n] 2006.173.11:51:19.89#ibcon#*before write, iclass 23, count 2 2006.173.11:51:19.89#ibcon#enter sib2, iclass 23, count 2 2006.173.11:51:19.89#ibcon#flushed, iclass 23, count 2 2006.173.11:51:19.89#ibcon#about to write, iclass 23, count 2 2006.173.11:51:19.89#ibcon#wrote, iclass 23, count 2 2006.173.11:51:19.89#ibcon#about to read 3, iclass 23, count 2 2006.173.11:51:19.92#ibcon#read 3, iclass 23, count 2 2006.173.11:51:19.92#ibcon#about to read 4, iclass 23, count 2 2006.173.11:51:19.92#ibcon#read 4, iclass 23, count 2 2006.173.11:51:19.92#ibcon#about to read 5, iclass 23, count 2 2006.173.11:51:19.92#ibcon#read 5, iclass 23, count 2 2006.173.11:51:19.92#ibcon#about to read 6, iclass 23, count 2 2006.173.11:51:19.92#ibcon#read 6, iclass 23, count 2 2006.173.11:51:19.92#ibcon#end of sib2, iclass 23, count 2 2006.173.11:51:19.92#ibcon#*after write, iclass 23, count 2 2006.173.11:51:19.92#ibcon#*before return 0, iclass 23, count 2 2006.173.11:51:19.92#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.11:51:19.92#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.11:51:19.92#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.11:51:19.92#ibcon#ireg 7 cls_cnt 0 2006.173.11:51:19.92#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.11:51:20.04#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.11:51:20.04#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.11:51:20.04#ibcon#enter wrdev, iclass 23, count 0 2006.173.11:51:20.04#ibcon#first serial, iclass 23, count 0 2006.173.11:51:20.04#ibcon#enter sib2, iclass 23, count 0 2006.173.11:51:20.04#ibcon#flushed, iclass 23, count 0 2006.173.11:51:20.04#ibcon#about to write, iclass 23, count 0 2006.173.11:51:20.04#ibcon#wrote, iclass 23, count 0 2006.173.11:51:20.04#ibcon#about to read 3, iclass 23, count 0 2006.173.11:51:20.06#ibcon#read 3, iclass 23, count 0 2006.173.11:51:20.06#ibcon#about to read 4, iclass 23, count 0 2006.173.11:51:20.06#ibcon#read 4, iclass 23, count 0 2006.173.11:51:20.06#ibcon#about to read 5, iclass 23, count 0 2006.173.11:51:20.06#ibcon#read 5, iclass 23, count 0 2006.173.11:51:20.06#ibcon#about to read 6, iclass 23, count 0 2006.173.11:51:20.06#ibcon#read 6, iclass 23, count 0 2006.173.11:51:20.06#ibcon#end of sib2, iclass 23, count 0 2006.173.11:51:20.06#ibcon#*mode == 0, iclass 23, count 0 2006.173.11:51:20.06#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.11:51:20.06#ibcon#[27=USB\r\n] 2006.173.11:51:20.06#ibcon#*before write, iclass 23, count 0 2006.173.11:51:20.06#ibcon#enter sib2, iclass 23, count 0 2006.173.11:51:20.06#ibcon#flushed, iclass 23, count 0 2006.173.11:51:20.06#ibcon#about to write, iclass 23, count 0 2006.173.11:51:20.06#ibcon#wrote, iclass 23, count 0 2006.173.11:51:20.06#ibcon#about to read 3, iclass 23, count 0 2006.173.11:51:20.09#ibcon#read 3, iclass 23, count 0 2006.173.11:51:20.09#ibcon#about to read 4, iclass 23, count 0 2006.173.11:51:20.09#ibcon#read 4, iclass 23, count 0 2006.173.11:51:20.09#ibcon#about to read 5, iclass 23, count 0 2006.173.11:51:20.09#ibcon#read 5, iclass 23, count 0 2006.173.11:51:20.09#ibcon#about to read 6, iclass 23, count 0 2006.173.11:51:20.09#ibcon#read 6, iclass 23, count 0 2006.173.11:51:20.09#ibcon#end of sib2, iclass 23, count 0 2006.173.11:51:20.09#ibcon#*after write, iclass 23, count 0 2006.173.11:51:20.09#ibcon#*before return 0, iclass 23, count 0 2006.173.11:51:20.09#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.11:51:20.09#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.11:51:20.09#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.11:51:20.09#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.11:51:20.09$vck44/vblo=2,634.99 2006.173.11:51:20.09#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.11:51:20.09#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.11:51:20.09#ibcon#ireg 17 cls_cnt 0 2006.173.11:51:20.09#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.11:51:20.09#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.11:51:20.09#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.11:51:20.09#ibcon#enter wrdev, iclass 25, count 0 2006.173.11:51:20.09#ibcon#first serial, iclass 25, count 0 2006.173.11:51:20.09#ibcon#enter sib2, iclass 25, count 0 2006.173.11:51:20.09#ibcon#flushed, iclass 25, count 0 2006.173.11:51:20.09#ibcon#about to write, iclass 25, count 0 2006.173.11:51:20.09#ibcon#wrote, iclass 25, count 0 2006.173.11:51:20.09#ibcon#about to read 3, iclass 25, count 0 2006.173.11:51:20.11#ibcon#read 3, iclass 25, count 0 2006.173.11:51:20.11#ibcon#about to read 4, iclass 25, count 0 2006.173.11:51:20.11#ibcon#read 4, iclass 25, count 0 2006.173.11:51:20.11#ibcon#about to read 5, iclass 25, count 0 2006.173.11:51:20.11#ibcon#read 5, iclass 25, count 0 2006.173.11:51:20.11#ibcon#about to read 6, iclass 25, count 0 2006.173.11:51:20.11#ibcon#read 6, iclass 25, count 0 2006.173.11:51:20.11#ibcon#end of sib2, iclass 25, count 0 2006.173.11:51:20.11#ibcon#*mode == 0, iclass 25, count 0 2006.173.11:51:20.11#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.11:51:20.11#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.11:51:20.11#ibcon#*before write, iclass 25, count 0 2006.173.11:51:20.11#ibcon#enter sib2, iclass 25, count 0 2006.173.11:51:20.11#ibcon#flushed, iclass 25, count 0 2006.173.11:51:20.11#ibcon#about to write, iclass 25, count 0 2006.173.11:51:20.11#ibcon#wrote, iclass 25, count 0 2006.173.11:51:20.11#ibcon#about to read 3, iclass 25, count 0 2006.173.11:51:20.15#ibcon#read 3, iclass 25, count 0 2006.173.11:51:20.15#ibcon#about to read 4, iclass 25, count 0 2006.173.11:51:20.15#ibcon#read 4, iclass 25, count 0 2006.173.11:51:20.15#ibcon#about to read 5, iclass 25, count 0 2006.173.11:51:20.15#ibcon#read 5, iclass 25, count 0 2006.173.11:51:20.15#ibcon#about to read 6, iclass 25, count 0 2006.173.11:51:20.15#ibcon#read 6, iclass 25, count 0 2006.173.11:51:20.15#ibcon#end of sib2, iclass 25, count 0 2006.173.11:51:20.15#ibcon#*after write, iclass 25, count 0 2006.173.11:51:20.15#ibcon#*before return 0, iclass 25, count 0 2006.173.11:51:20.15#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.11:51:20.15#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.11:51:20.15#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.11:51:20.15#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.11:51:20.15$vck44/vb=2,4 2006.173.11:51:20.15#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.11:51:20.15#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.11:51:20.15#ibcon#ireg 11 cls_cnt 2 2006.173.11:51:20.15#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.11:51:20.21#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.11:51:20.21#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.11:51:20.21#ibcon#enter wrdev, iclass 27, count 2 2006.173.11:51:20.21#ibcon#first serial, iclass 27, count 2 2006.173.11:51:20.21#ibcon#enter sib2, iclass 27, count 2 2006.173.11:51:20.21#ibcon#flushed, iclass 27, count 2 2006.173.11:51:20.21#ibcon#about to write, iclass 27, count 2 2006.173.11:51:20.21#ibcon#wrote, iclass 27, count 2 2006.173.11:51:20.21#ibcon#about to read 3, iclass 27, count 2 2006.173.11:51:20.23#ibcon#read 3, iclass 27, count 2 2006.173.11:51:20.23#ibcon#about to read 4, iclass 27, count 2 2006.173.11:51:20.23#ibcon#read 4, iclass 27, count 2 2006.173.11:51:20.23#ibcon#about to read 5, iclass 27, count 2 2006.173.11:51:20.23#ibcon#read 5, iclass 27, count 2 2006.173.11:51:20.23#ibcon#about to read 6, iclass 27, count 2 2006.173.11:51:20.23#ibcon#read 6, iclass 27, count 2 2006.173.11:51:20.23#ibcon#end of sib2, iclass 27, count 2 2006.173.11:51:20.23#ibcon#*mode == 0, iclass 27, count 2 2006.173.11:51:20.23#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.11:51:20.23#ibcon#[27=AT02-04\r\n] 2006.173.11:51:20.23#ibcon#*before write, iclass 27, count 2 2006.173.11:51:20.23#ibcon#enter sib2, iclass 27, count 2 2006.173.11:51:20.23#ibcon#flushed, iclass 27, count 2 2006.173.11:51:20.23#ibcon#about to write, iclass 27, count 2 2006.173.11:51:20.23#ibcon#wrote, iclass 27, count 2 2006.173.11:51:20.23#ibcon#about to read 3, iclass 27, count 2 2006.173.11:51:20.26#ibcon#read 3, iclass 27, count 2 2006.173.11:51:20.26#ibcon#about to read 4, iclass 27, count 2 2006.173.11:51:20.26#ibcon#read 4, iclass 27, count 2 2006.173.11:51:20.26#ibcon#about to read 5, iclass 27, count 2 2006.173.11:51:20.26#ibcon#read 5, iclass 27, count 2 2006.173.11:51:20.26#ibcon#about to read 6, iclass 27, count 2 2006.173.11:51:20.26#ibcon#read 6, iclass 27, count 2 2006.173.11:51:20.26#ibcon#end of sib2, iclass 27, count 2 2006.173.11:51:20.26#ibcon#*after write, iclass 27, count 2 2006.173.11:51:20.26#ibcon#*before return 0, iclass 27, count 2 2006.173.11:51:20.26#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.11:51:20.26#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.11:51:20.26#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.11:51:20.26#ibcon#ireg 7 cls_cnt 0 2006.173.11:51:20.26#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.11:51:20.38#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.11:51:20.38#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.11:51:20.38#ibcon#enter wrdev, iclass 27, count 0 2006.173.11:51:20.38#ibcon#first serial, iclass 27, count 0 2006.173.11:51:20.38#ibcon#enter sib2, iclass 27, count 0 2006.173.11:51:20.38#ibcon#flushed, iclass 27, count 0 2006.173.11:51:20.38#ibcon#about to write, iclass 27, count 0 2006.173.11:51:20.38#ibcon#wrote, iclass 27, count 0 2006.173.11:51:20.38#ibcon#about to read 3, iclass 27, count 0 2006.173.11:51:20.40#ibcon#read 3, iclass 27, count 0 2006.173.11:51:20.40#ibcon#about to read 4, iclass 27, count 0 2006.173.11:51:20.40#ibcon#read 4, iclass 27, count 0 2006.173.11:51:20.40#ibcon#about to read 5, iclass 27, count 0 2006.173.11:51:20.40#ibcon#read 5, iclass 27, count 0 2006.173.11:51:20.40#ibcon#about to read 6, iclass 27, count 0 2006.173.11:51:20.40#ibcon#read 6, iclass 27, count 0 2006.173.11:51:20.40#ibcon#end of sib2, iclass 27, count 0 2006.173.11:51:20.40#ibcon#*mode == 0, iclass 27, count 0 2006.173.11:51:20.40#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.11:51:20.40#ibcon#[27=USB\r\n] 2006.173.11:51:20.40#ibcon#*before write, iclass 27, count 0 2006.173.11:51:20.40#ibcon#enter sib2, iclass 27, count 0 2006.173.11:51:20.40#ibcon#flushed, iclass 27, count 0 2006.173.11:51:20.40#ibcon#about to write, iclass 27, count 0 2006.173.11:51:20.40#ibcon#wrote, iclass 27, count 0 2006.173.11:51:20.40#ibcon#about to read 3, iclass 27, count 0 2006.173.11:51:20.43#ibcon#read 3, iclass 27, count 0 2006.173.11:51:20.43#ibcon#about to read 4, iclass 27, count 0 2006.173.11:51:20.43#ibcon#read 4, iclass 27, count 0 2006.173.11:51:20.43#ibcon#about to read 5, iclass 27, count 0 2006.173.11:51:20.43#ibcon#read 5, iclass 27, count 0 2006.173.11:51:20.43#ibcon#about to read 6, iclass 27, count 0 2006.173.11:51:20.43#ibcon#read 6, iclass 27, count 0 2006.173.11:51:20.43#ibcon#end of sib2, iclass 27, count 0 2006.173.11:51:20.43#ibcon#*after write, iclass 27, count 0 2006.173.11:51:20.43#ibcon#*before return 0, iclass 27, count 0 2006.173.11:51:20.43#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.11:51:20.43#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.11:51:20.43#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.11:51:20.43#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.11:51:20.43$vck44/vblo=3,649.99 2006.173.11:51:20.43#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.11:51:20.43#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.11:51:20.43#ibcon#ireg 17 cls_cnt 0 2006.173.11:51:20.43#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.11:51:20.43#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.11:51:20.43#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.11:51:20.43#ibcon#enter wrdev, iclass 29, count 0 2006.173.11:51:20.43#ibcon#first serial, iclass 29, count 0 2006.173.11:51:20.43#ibcon#enter sib2, iclass 29, count 0 2006.173.11:51:20.43#ibcon#flushed, iclass 29, count 0 2006.173.11:51:20.43#ibcon#about to write, iclass 29, count 0 2006.173.11:51:20.43#ibcon#wrote, iclass 29, count 0 2006.173.11:51:20.43#ibcon#about to read 3, iclass 29, count 0 2006.173.11:51:20.45#ibcon#read 3, iclass 29, count 0 2006.173.11:51:20.45#ibcon#about to read 4, iclass 29, count 0 2006.173.11:51:20.45#ibcon#read 4, iclass 29, count 0 2006.173.11:51:20.45#ibcon#about to read 5, iclass 29, count 0 2006.173.11:51:20.45#ibcon#read 5, iclass 29, count 0 2006.173.11:51:20.45#ibcon#about to read 6, iclass 29, count 0 2006.173.11:51:20.45#ibcon#read 6, iclass 29, count 0 2006.173.11:51:20.45#ibcon#end of sib2, iclass 29, count 0 2006.173.11:51:20.45#ibcon#*mode == 0, iclass 29, count 0 2006.173.11:51:20.45#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.11:51:20.45#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.11:51:20.45#ibcon#*before write, iclass 29, count 0 2006.173.11:51:20.45#ibcon#enter sib2, iclass 29, count 0 2006.173.11:51:20.45#ibcon#flushed, iclass 29, count 0 2006.173.11:51:20.45#ibcon#about to write, iclass 29, count 0 2006.173.11:51:20.45#ibcon#wrote, iclass 29, count 0 2006.173.11:51:20.45#ibcon#about to read 3, iclass 29, count 0 2006.173.11:51:20.49#ibcon#read 3, iclass 29, count 0 2006.173.11:51:20.49#ibcon#about to read 4, iclass 29, count 0 2006.173.11:51:20.49#ibcon#read 4, iclass 29, count 0 2006.173.11:51:20.49#ibcon#about to read 5, iclass 29, count 0 2006.173.11:51:20.49#ibcon#read 5, iclass 29, count 0 2006.173.11:51:20.49#ibcon#about to read 6, iclass 29, count 0 2006.173.11:51:20.49#ibcon#read 6, iclass 29, count 0 2006.173.11:51:20.49#ibcon#end of sib2, iclass 29, count 0 2006.173.11:51:20.49#ibcon#*after write, iclass 29, count 0 2006.173.11:51:20.49#ibcon#*before return 0, iclass 29, count 0 2006.173.11:51:20.49#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.11:51:20.49#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.11:51:20.49#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.11:51:20.49#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.11:51:20.49$vck44/vb=3,4 2006.173.11:51:20.49#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.11:51:20.49#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.11:51:20.49#ibcon#ireg 11 cls_cnt 2 2006.173.11:51:20.49#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.11:51:20.55#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.11:51:20.55#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.11:51:20.55#ibcon#enter wrdev, iclass 31, count 2 2006.173.11:51:20.55#ibcon#first serial, iclass 31, count 2 2006.173.11:51:20.55#ibcon#enter sib2, iclass 31, count 2 2006.173.11:51:20.55#ibcon#flushed, iclass 31, count 2 2006.173.11:51:20.55#ibcon#about to write, iclass 31, count 2 2006.173.11:51:20.55#ibcon#wrote, iclass 31, count 2 2006.173.11:51:20.55#ibcon#about to read 3, iclass 31, count 2 2006.173.11:51:20.57#ibcon#read 3, iclass 31, count 2 2006.173.11:51:20.57#ibcon#about to read 4, iclass 31, count 2 2006.173.11:51:20.57#ibcon#read 4, iclass 31, count 2 2006.173.11:51:20.57#ibcon#about to read 5, iclass 31, count 2 2006.173.11:51:20.57#ibcon#read 5, iclass 31, count 2 2006.173.11:51:20.57#ibcon#about to read 6, iclass 31, count 2 2006.173.11:51:20.57#ibcon#read 6, iclass 31, count 2 2006.173.11:51:20.57#ibcon#end of sib2, iclass 31, count 2 2006.173.11:51:20.57#ibcon#*mode == 0, iclass 31, count 2 2006.173.11:51:20.57#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.11:51:20.57#ibcon#[27=AT03-04\r\n] 2006.173.11:51:20.57#ibcon#*before write, iclass 31, count 2 2006.173.11:51:20.57#ibcon#enter sib2, iclass 31, count 2 2006.173.11:51:20.57#ibcon#flushed, iclass 31, count 2 2006.173.11:51:20.57#ibcon#about to write, iclass 31, count 2 2006.173.11:51:20.57#ibcon#wrote, iclass 31, count 2 2006.173.11:51:20.57#ibcon#about to read 3, iclass 31, count 2 2006.173.11:51:20.60#ibcon#read 3, iclass 31, count 2 2006.173.11:51:20.60#ibcon#about to read 4, iclass 31, count 2 2006.173.11:51:20.60#ibcon#read 4, iclass 31, count 2 2006.173.11:51:20.60#ibcon#about to read 5, iclass 31, count 2 2006.173.11:51:20.60#ibcon#read 5, iclass 31, count 2 2006.173.11:51:20.60#ibcon#about to read 6, iclass 31, count 2 2006.173.11:51:20.60#ibcon#read 6, iclass 31, count 2 2006.173.11:51:20.60#ibcon#end of sib2, iclass 31, count 2 2006.173.11:51:20.60#ibcon#*after write, iclass 31, count 2 2006.173.11:51:20.60#ibcon#*before return 0, iclass 31, count 2 2006.173.11:51:20.60#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.11:51:20.60#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.11:51:20.60#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.11:51:20.60#ibcon#ireg 7 cls_cnt 0 2006.173.11:51:20.60#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.11:51:20.72#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.11:51:20.72#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.11:51:20.72#ibcon#enter wrdev, iclass 31, count 0 2006.173.11:51:20.72#ibcon#first serial, iclass 31, count 0 2006.173.11:51:20.72#ibcon#enter sib2, iclass 31, count 0 2006.173.11:51:20.72#ibcon#flushed, iclass 31, count 0 2006.173.11:51:20.72#ibcon#about to write, iclass 31, count 0 2006.173.11:51:20.72#ibcon#wrote, iclass 31, count 0 2006.173.11:51:20.72#ibcon#about to read 3, iclass 31, count 0 2006.173.11:51:20.74#ibcon#read 3, iclass 31, count 0 2006.173.11:51:20.74#ibcon#about to read 4, iclass 31, count 0 2006.173.11:51:20.74#ibcon#read 4, iclass 31, count 0 2006.173.11:51:20.74#ibcon#about to read 5, iclass 31, count 0 2006.173.11:51:20.74#ibcon#read 5, iclass 31, count 0 2006.173.11:51:20.74#ibcon#about to read 6, iclass 31, count 0 2006.173.11:51:20.74#ibcon#read 6, iclass 31, count 0 2006.173.11:51:20.74#ibcon#end of sib2, iclass 31, count 0 2006.173.11:51:20.74#ibcon#*mode == 0, iclass 31, count 0 2006.173.11:51:20.74#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.11:51:20.74#ibcon#[27=USB\r\n] 2006.173.11:51:20.74#ibcon#*before write, iclass 31, count 0 2006.173.11:51:20.74#ibcon#enter sib2, iclass 31, count 0 2006.173.11:51:20.74#ibcon#flushed, iclass 31, count 0 2006.173.11:51:20.74#ibcon#about to write, iclass 31, count 0 2006.173.11:51:20.74#ibcon#wrote, iclass 31, count 0 2006.173.11:51:20.74#ibcon#about to read 3, iclass 31, count 0 2006.173.11:51:20.77#ibcon#read 3, iclass 31, count 0 2006.173.11:51:20.77#ibcon#about to read 4, iclass 31, count 0 2006.173.11:51:20.77#ibcon#read 4, iclass 31, count 0 2006.173.11:51:20.77#ibcon#about to read 5, iclass 31, count 0 2006.173.11:51:20.77#ibcon#read 5, iclass 31, count 0 2006.173.11:51:20.77#ibcon#about to read 6, iclass 31, count 0 2006.173.11:51:20.77#ibcon#read 6, iclass 31, count 0 2006.173.11:51:20.77#ibcon#end of sib2, iclass 31, count 0 2006.173.11:51:20.77#ibcon#*after write, iclass 31, count 0 2006.173.11:51:20.77#ibcon#*before return 0, iclass 31, count 0 2006.173.11:51:20.77#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.11:51:20.77#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.11:51:20.77#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.11:51:20.77#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.11:51:20.77$vck44/vblo=4,679.99 2006.173.11:51:20.77#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.11:51:20.77#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.11:51:20.77#ibcon#ireg 17 cls_cnt 0 2006.173.11:51:20.77#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.11:51:20.77#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.11:51:20.77#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.11:51:20.77#ibcon#enter wrdev, iclass 33, count 0 2006.173.11:51:20.77#ibcon#first serial, iclass 33, count 0 2006.173.11:51:20.77#ibcon#enter sib2, iclass 33, count 0 2006.173.11:51:20.77#ibcon#flushed, iclass 33, count 0 2006.173.11:51:20.77#ibcon#about to write, iclass 33, count 0 2006.173.11:51:20.77#ibcon#wrote, iclass 33, count 0 2006.173.11:51:20.77#ibcon#about to read 3, iclass 33, count 0 2006.173.11:51:20.79#ibcon#read 3, iclass 33, count 0 2006.173.11:51:20.79#ibcon#about to read 4, iclass 33, count 0 2006.173.11:51:20.79#ibcon#read 4, iclass 33, count 0 2006.173.11:51:20.79#ibcon#about to read 5, iclass 33, count 0 2006.173.11:51:20.79#ibcon#read 5, iclass 33, count 0 2006.173.11:51:20.79#ibcon#about to read 6, iclass 33, count 0 2006.173.11:51:20.79#ibcon#read 6, iclass 33, count 0 2006.173.11:51:20.79#ibcon#end of sib2, iclass 33, count 0 2006.173.11:51:20.79#ibcon#*mode == 0, iclass 33, count 0 2006.173.11:51:20.79#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.11:51:20.79#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.11:51:20.79#ibcon#*before write, iclass 33, count 0 2006.173.11:51:20.79#ibcon#enter sib2, iclass 33, count 0 2006.173.11:51:20.79#ibcon#flushed, iclass 33, count 0 2006.173.11:51:20.79#ibcon#about to write, iclass 33, count 0 2006.173.11:51:20.79#ibcon#wrote, iclass 33, count 0 2006.173.11:51:20.79#ibcon#about to read 3, iclass 33, count 0 2006.173.11:51:20.83#ibcon#read 3, iclass 33, count 0 2006.173.11:51:20.83#ibcon#about to read 4, iclass 33, count 0 2006.173.11:51:20.83#ibcon#read 4, iclass 33, count 0 2006.173.11:51:20.83#ibcon#about to read 5, iclass 33, count 0 2006.173.11:51:20.83#ibcon#read 5, iclass 33, count 0 2006.173.11:51:20.83#ibcon#about to read 6, iclass 33, count 0 2006.173.11:51:20.83#ibcon#read 6, iclass 33, count 0 2006.173.11:51:20.83#ibcon#end of sib2, iclass 33, count 0 2006.173.11:51:20.83#ibcon#*after write, iclass 33, count 0 2006.173.11:51:20.83#ibcon#*before return 0, iclass 33, count 0 2006.173.11:51:20.83#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.11:51:20.83#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.11:51:20.83#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.11:51:20.83#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.11:51:20.83$vck44/vb=4,4 2006.173.11:51:20.83#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.11:51:20.83#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.11:51:20.83#ibcon#ireg 11 cls_cnt 2 2006.173.11:51:20.83#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.11:51:20.89#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.11:51:20.89#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.11:51:20.89#ibcon#enter wrdev, iclass 35, count 2 2006.173.11:51:20.89#ibcon#first serial, iclass 35, count 2 2006.173.11:51:20.89#ibcon#enter sib2, iclass 35, count 2 2006.173.11:51:20.89#ibcon#flushed, iclass 35, count 2 2006.173.11:51:20.89#ibcon#about to write, iclass 35, count 2 2006.173.11:51:20.89#ibcon#wrote, iclass 35, count 2 2006.173.11:51:20.89#ibcon#about to read 3, iclass 35, count 2 2006.173.11:51:20.91#ibcon#read 3, iclass 35, count 2 2006.173.11:51:20.91#ibcon#about to read 4, iclass 35, count 2 2006.173.11:51:20.91#ibcon#read 4, iclass 35, count 2 2006.173.11:51:20.91#ibcon#about to read 5, iclass 35, count 2 2006.173.11:51:20.91#ibcon#read 5, iclass 35, count 2 2006.173.11:51:20.91#ibcon#about to read 6, iclass 35, count 2 2006.173.11:51:20.91#ibcon#read 6, iclass 35, count 2 2006.173.11:51:20.91#ibcon#end of sib2, iclass 35, count 2 2006.173.11:51:20.91#ibcon#*mode == 0, iclass 35, count 2 2006.173.11:51:20.91#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.11:51:20.91#ibcon#[27=AT04-04\r\n] 2006.173.11:51:20.91#ibcon#*before write, iclass 35, count 2 2006.173.11:51:20.91#ibcon#enter sib2, iclass 35, count 2 2006.173.11:51:20.91#ibcon#flushed, iclass 35, count 2 2006.173.11:51:20.91#ibcon#about to write, iclass 35, count 2 2006.173.11:51:20.91#ibcon#wrote, iclass 35, count 2 2006.173.11:51:20.91#ibcon#about to read 3, iclass 35, count 2 2006.173.11:51:20.94#ibcon#read 3, iclass 35, count 2 2006.173.11:51:20.94#ibcon#about to read 4, iclass 35, count 2 2006.173.11:51:20.94#ibcon#read 4, iclass 35, count 2 2006.173.11:51:20.94#ibcon#about to read 5, iclass 35, count 2 2006.173.11:51:20.94#ibcon#read 5, iclass 35, count 2 2006.173.11:51:20.94#ibcon#about to read 6, iclass 35, count 2 2006.173.11:51:20.94#ibcon#read 6, iclass 35, count 2 2006.173.11:51:20.94#ibcon#end of sib2, iclass 35, count 2 2006.173.11:51:20.94#ibcon#*after write, iclass 35, count 2 2006.173.11:51:20.94#ibcon#*before return 0, iclass 35, count 2 2006.173.11:51:20.94#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.11:51:20.94#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.11:51:20.94#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.11:51:20.94#ibcon#ireg 7 cls_cnt 0 2006.173.11:51:20.94#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.11:51:21.06#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.11:51:21.06#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.11:51:21.06#ibcon#enter wrdev, iclass 35, count 0 2006.173.11:51:21.06#ibcon#first serial, iclass 35, count 0 2006.173.11:51:21.06#ibcon#enter sib2, iclass 35, count 0 2006.173.11:51:21.06#ibcon#flushed, iclass 35, count 0 2006.173.11:51:21.06#ibcon#about to write, iclass 35, count 0 2006.173.11:51:21.06#ibcon#wrote, iclass 35, count 0 2006.173.11:51:21.06#ibcon#about to read 3, iclass 35, count 0 2006.173.11:51:21.08#ibcon#read 3, iclass 35, count 0 2006.173.11:51:21.08#ibcon#about to read 4, iclass 35, count 0 2006.173.11:51:21.08#ibcon#read 4, iclass 35, count 0 2006.173.11:51:21.08#ibcon#about to read 5, iclass 35, count 0 2006.173.11:51:21.08#ibcon#read 5, iclass 35, count 0 2006.173.11:51:21.08#ibcon#about to read 6, iclass 35, count 0 2006.173.11:51:21.08#ibcon#read 6, iclass 35, count 0 2006.173.11:51:21.08#ibcon#end of sib2, iclass 35, count 0 2006.173.11:51:21.08#ibcon#*mode == 0, iclass 35, count 0 2006.173.11:51:21.08#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.11:51:21.08#ibcon#[27=USB\r\n] 2006.173.11:51:21.08#ibcon#*before write, iclass 35, count 0 2006.173.11:51:21.08#ibcon#enter sib2, iclass 35, count 0 2006.173.11:51:21.08#ibcon#flushed, iclass 35, count 0 2006.173.11:51:21.08#ibcon#about to write, iclass 35, count 0 2006.173.11:51:21.08#ibcon#wrote, iclass 35, count 0 2006.173.11:51:21.08#ibcon#about to read 3, iclass 35, count 0 2006.173.11:51:21.11#ibcon#read 3, iclass 35, count 0 2006.173.11:51:21.11#ibcon#about to read 4, iclass 35, count 0 2006.173.11:51:21.11#ibcon#read 4, iclass 35, count 0 2006.173.11:51:21.11#ibcon#about to read 5, iclass 35, count 0 2006.173.11:51:21.11#ibcon#read 5, iclass 35, count 0 2006.173.11:51:21.11#ibcon#about to read 6, iclass 35, count 0 2006.173.11:51:21.11#ibcon#read 6, iclass 35, count 0 2006.173.11:51:21.11#ibcon#end of sib2, iclass 35, count 0 2006.173.11:51:21.11#ibcon#*after write, iclass 35, count 0 2006.173.11:51:21.11#ibcon#*before return 0, iclass 35, count 0 2006.173.11:51:21.11#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.11:51:21.11#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.11:51:21.11#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.11:51:21.11#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.11:51:21.11$vck44/vblo=5,709.99 2006.173.11:51:21.11#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.11:51:21.11#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.11:51:21.11#ibcon#ireg 17 cls_cnt 0 2006.173.11:51:21.11#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.11:51:21.11#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.11:51:21.11#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.11:51:21.11#ibcon#enter wrdev, iclass 37, count 0 2006.173.11:51:21.11#ibcon#first serial, iclass 37, count 0 2006.173.11:51:21.11#ibcon#enter sib2, iclass 37, count 0 2006.173.11:51:21.11#ibcon#flushed, iclass 37, count 0 2006.173.11:51:21.11#ibcon#about to write, iclass 37, count 0 2006.173.11:51:21.11#ibcon#wrote, iclass 37, count 0 2006.173.11:51:21.11#ibcon#about to read 3, iclass 37, count 0 2006.173.11:51:21.13#ibcon#read 3, iclass 37, count 0 2006.173.11:51:21.13#ibcon#about to read 4, iclass 37, count 0 2006.173.11:51:21.13#ibcon#read 4, iclass 37, count 0 2006.173.11:51:21.13#ibcon#about to read 5, iclass 37, count 0 2006.173.11:51:21.13#ibcon#read 5, iclass 37, count 0 2006.173.11:51:21.13#ibcon#about to read 6, iclass 37, count 0 2006.173.11:51:21.13#ibcon#read 6, iclass 37, count 0 2006.173.11:51:21.13#ibcon#end of sib2, iclass 37, count 0 2006.173.11:51:21.13#ibcon#*mode == 0, iclass 37, count 0 2006.173.11:51:21.13#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.11:51:21.13#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.11:51:21.13#ibcon#*before write, iclass 37, count 0 2006.173.11:51:21.13#ibcon#enter sib2, iclass 37, count 0 2006.173.11:51:21.13#ibcon#flushed, iclass 37, count 0 2006.173.11:51:21.13#ibcon#about to write, iclass 37, count 0 2006.173.11:51:21.13#ibcon#wrote, iclass 37, count 0 2006.173.11:51:21.13#ibcon#about to read 3, iclass 37, count 0 2006.173.11:51:21.17#ibcon#read 3, iclass 37, count 0 2006.173.11:51:21.17#ibcon#about to read 4, iclass 37, count 0 2006.173.11:51:21.17#ibcon#read 4, iclass 37, count 0 2006.173.11:51:21.17#ibcon#about to read 5, iclass 37, count 0 2006.173.11:51:21.17#ibcon#read 5, iclass 37, count 0 2006.173.11:51:21.17#ibcon#about to read 6, iclass 37, count 0 2006.173.11:51:21.17#ibcon#read 6, iclass 37, count 0 2006.173.11:51:21.17#ibcon#end of sib2, iclass 37, count 0 2006.173.11:51:21.17#ibcon#*after write, iclass 37, count 0 2006.173.11:51:21.17#ibcon#*before return 0, iclass 37, count 0 2006.173.11:51:21.17#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.11:51:21.17#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.11:51:21.17#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.11:51:21.17#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.11:51:21.17$vck44/vb=5,4 2006.173.11:51:21.17#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.11:51:21.17#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.11:51:21.17#ibcon#ireg 11 cls_cnt 2 2006.173.11:51:21.17#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.11:51:21.23#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.11:51:21.23#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.11:51:21.23#ibcon#enter wrdev, iclass 39, count 2 2006.173.11:51:21.23#ibcon#first serial, iclass 39, count 2 2006.173.11:51:21.23#ibcon#enter sib2, iclass 39, count 2 2006.173.11:51:21.23#ibcon#flushed, iclass 39, count 2 2006.173.11:51:21.23#ibcon#about to write, iclass 39, count 2 2006.173.11:51:21.23#ibcon#wrote, iclass 39, count 2 2006.173.11:51:21.23#ibcon#about to read 3, iclass 39, count 2 2006.173.11:51:21.25#ibcon#read 3, iclass 39, count 2 2006.173.11:51:21.25#ibcon#about to read 4, iclass 39, count 2 2006.173.11:51:21.25#ibcon#read 4, iclass 39, count 2 2006.173.11:51:21.25#ibcon#about to read 5, iclass 39, count 2 2006.173.11:51:21.25#ibcon#read 5, iclass 39, count 2 2006.173.11:51:21.25#ibcon#about to read 6, iclass 39, count 2 2006.173.11:51:21.25#ibcon#read 6, iclass 39, count 2 2006.173.11:51:21.25#ibcon#end of sib2, iclass 39, count 2 2006.173.11:51:21.25#ibcon#*mode == 0, iclass 39, count 2 2006.173.11:51:21.25#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.11:51:21.25#ibcon#[27=AT05-04\r\n] 2006.173.11:51:21.25#ibcon#*before write, iclass 39, count 2 2006.173.11:51:21.25#ibcon#enter sib2, iclass 39, count 2 2006.173.11:51:21.25#ibcon#flushed, iclass 39, count 2 2006.173.11:51:21.25#ibcon#about to write, iclass 39, count 2 2006.173.11:51:21.25#ibcon#wrote, iclass 39, count 2 2006.173.11:51:21.25#ibcon#about to read 3, iclass 39, count 2 2006.173.11:51:21.28#ibcon#read 3, iclass 39, count 2 2006.173.11:51:21.28#ibcon#about to read 4, iclass 39, count 2 2006.173.11:51:21.28#ibcon#read 4, iclass 39, count 2 2006.173.11:51:21.28#ibcon#about to read 5, iclass 39, count 2 2006.173.11:51:21.28#ibcon#read 5, iclass 39, count 2 2006.173.11:51:21.28#ibcon#about to read 6, iclass 39, count 2 2006.173.11:51:21.28#ibcon#read 6, iclass 39, count 2 2006.173.11:51:21.28#ibcon#end of sib2, iclass 39, count 2 2006.173.11:51:21.28#ibcon#*after write, iclass 39, count 2 2006.173.11:51:21.28#ibcon#*before return 0, iclass 39, count 2 2006.173.11:51:21.28#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.11:51:21.28#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.11:51:21.28#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.11:51:21.28#ibcon#ireg 7 cls_cnt 0 2006.173.11:51:21.28#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.11:51:21.40#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.11:51:21.40#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.11:51:21.40#ibcon#enter wrdev, iclass 39, count 0 2006.173.11:51:21.40#ibcon#first serial, iclass 39, count 0 2006.173.11:51:21.40#ibcon#enter sib2, iclass 39, count 0 2006.173.11:51:21.40#ibcon#flushed, iclass 39, count 0 2006.173.11:51:21.40#ibcon#about to write, iclass 39, count 0 2006.173.11:51:21.40#ibcon#wrote, iclass 39, count 0 2006.173.11:51:21.40#ibcon#about to read 3, iclass 39, count 0 2006.173.11:51:21.42#ibcon#read 3, iclass 39, count 0 2006.173.11:51:21.42#ibcon#about to read 4, iclass 39, count 0 2006.173.11:51:21.42#ibcon#read 4, iclass 39, count 0 2006.173.11:51:21.42#ibcon#about to read 5, iclass 39, count 0 2006.173.11:51:21.42#ibcon#read 5, iclass 39, count 0 2006.173.11:51:21.42#ibcon#about to read 6, iclass 39, count 0 2006.173.11:51:21.42#ibcon#read 6, iclass 39, count 0 2006.173.11:51:21.42#ibcon#end of sib2, iclass 39, count 0 2006.173.11:51:21.42#ibcon#*mode == 0, iclass 39, count 0 2006.173.11:51:21.42#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.11:51:21.42#ibcon#[27=USB\r\n] 2006.173.11:51:21.42#ibcon#*before write, iclass 39, count 0 2006.173.11:51:21.42#ibcon#enter sib2, iclass 39, count 0 2006.173.11:51:21.42#ibcon#flushed, iclass 39, count 0 2006.173.11:51:21.42#ibcon#about to write, iclass 39, count 0 2006.173.11:51:21.42#ibcon#wrote, iclass 39, count 0 2006.173.11:51:21.42#ibcon#about to read 3, iclass 39, count 0 2006.173.11:51:21.45#ibcon#read 3, iclass 39, count 0 2006.173.11:51:21.45#ibcon#about to read 4, iclass 39, count 0 2006.173.11:51:21.45#ibcon#read 4, iclass 39, count 0 2006.173.11:51:21.45#ibcon#about to read 5, iclass 39, count 0 2006.173.11:51:21.45#ibcon#read 5, iclass 39, count 0 2006.173.11:51:21.45#ibcon#about to read 6, iclass 39, count 0 2006.173.11:51:21.45#ibcon#read 6, iclass 39, count 0 2006.173.11:51:21.45#ibcon#end of sib2, iclass 39, count 0 2006.173.11:51:21.45#ibcon#*after write, iclass 39, count 0 2006.173.11:51:21.45#ibcon#*before return 0, iclass 39, count 0 2006.173.11:51:21.45#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.11:51:21.45#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.11:51:21.45#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.11:51:21.45#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.11:51:21.45$vck44/vblo=6,719.99 2006.173.11:51:21.45#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.11:51:21.45#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.11:51:21.45#ibcon#ireg 17 cls_cnt 0 2006.173.11:51:21.45#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.11:51:21.45#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.11:51:21.45#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.11:51:21.45#ibcon#enter wrdev, iclass 3, count 0 2006.173.11:51:21.45#ibcon#first serial, iclass 3, count 0 2006.173.11:51:21.45#ibcon#enter sib2, iclass 3, count 0 2006.173.11:51:21.45#ibcon#flushed, iclass 3, count 0 2006.173.11:51:21.45#ibcon#about to write, iclass 3, count 0 2006.173.11:51:21.45#ibcon#wrote, iclass 3, count 0 2006.173.11:51:21.45#ibcon#about to read 3, iclass 3, count 0 2006.173.11:51:21.47#ibcon#read 3, iclass 3, count 0 2006.173.11:51:21.47#ibcon#about to read 4, iclass 3, count 0 2006.173.11:51:21.47#ibcon#read 4, iclass 3, count 0 2006.173.11:51:21.47#ibcon#about to read 5, iclass 3, count 0 2006.173.11:51:21.47#ibcon#read 5, iclass 3, count 0 2006.173.11:51:21.47#ibcon#about to read 6, iclass 3, count 0 2006.173.11:51:21.47#ibcon#read 6, iclass 3, count 0 2006.173.11:51:21.47#ibcon#end of sib2, iclass 3, count 0 2006.173.11:51:21.47#ibcon#*mode == 0, iclass 3, count 0 2006.173.11:51:21.47#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.11:51:21.47#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.11:51:21.47#ibcon#*before write, iclass 3, count 0 2006.173.11:51:21.47#ibcon#enter sib2, iclass 3, count 0 2006.173.11:51:21.47#ibcon#flushed, iclass 3, count 0 2006.173.11:51:21.47#ibcon#about to write, iclass 3, count 0 2006.173.11:51:21.47#ibcon#wrote, iclass 3, count 0 2006.173.11:51:21.47#ibcon#about to read 3, iclass 3, count 0 2006.173.11:51:21.51#ibcon#read 3, iclass 3, count 0 2006.173.11:51:21.51#ibcon#about to read 4, iclass 3, count 0 2006.173.11:51:21.51#ibcon#read 4, iclass 3, count 0 2006.173.11:51:21.51#ibcon#about to read 5, iclass 3, count 0 2006.173.11:51:21.51#ibcon#read 5, iclass 3, count 0 2006.173.11:51:21.51#ibcon#about to read 6, iclass 3, count 0 2006.173.11:51:21.51#ibcon#read 6, iclass 3, count 0 2006.173.11:51:21.51#ibcon#end of sib2, iclass 3, count 0 2006.173.11:51:21.51#ibcon#*after write, iclass 3, count 0 2006.173.11:51:21.51#ibcon#*before return 0, iclass 3, count 0 2006.173.11:51:21.51#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.11:51:21.51#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.11:51:21.51#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.11:51:21.51#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.11:51:21.51$vck44/vb=6,4 2006.173.11:51:21.51#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.11:51:21.51#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.11:51:21.51#ibcon#ireg 11 cls_cnt 2 2006.173.11:51:21.51#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.11:51:21.57#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.11:51:21.57#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.11:51:21.57#ibcon#enter wrdev, iclass 5, count 2 2006.173.11:51:21.57#ibcon#first serial, iclass 5, count 2 2006.173.11:51:21.57#ibcon#enter sib2, iclass 5, count 2 2006.173.11:51:21.57#ibcon#flushed, iclass 5, count 2 2006.173.11:51:21.57#ibcon#about to write, iclass 5, count 2 2006.173.11:51:21.57#ibcon#wrote, iclass 5, count 2 2006.173.11:51:21.57#ibcon#about to read 3, iclass 5, count 2 2006.173.11:51:21.59#ibcon#read 3, iclass 5, count 2 2006.173.11:51:21.59#ibcon#about to read 4, iclass 5, count 2 2006.173.11:51:21.59#ibcon#read 4, iclass 5, count 2 2006.173.11:51:21.59#ibcon#about to read 5, iclass 5, count 2 2006.173.11:51:21.59#ibcon#read 5, iclass 5, count 2 2006.173.11:51:21.59#ibcon#about to read 6, iclass 5, count 2 2006.173.11:51:21.59#ibcon#read 6, iclass 5, count 2 2006.173.11:51:21.59#ibcon#end of sib2, iclass 5, count 2 2006.173.11:51:21.59#ibcon#*mode == 0, iclass 5, count 2 2006.173.11:51:21.59#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.11:51:21.59#ibcon#[27=AT06-04\r\n] 2006.173.11:51:21.59#ibcon#*before write, iclass 5, count 2 2006.173.11:51:21.59#ibcon#enter sib2, iclass 5, count 2 2006.173.11:51:21.59#ibcon#flushed, iclass 5, count 2 2006.173.11:51:21.59#ibcon#about to write, iclass 5, count 2 2006.173.11:51:21.59#ibcon#wrote, iclass 5, count 2 2006.173.11:51:21.59#ibcon#about to read 3, iclass 5, count 2 2006.173.11:51:21.62#ibcon#read 3, iclass 5, count 2 2006.173.11:51:21.62#ibcon#about to read 4, iclass 5, count 2 2006.173.11:51:21.62#ibcon#read 4, iclass 5, count 2 2006.173.11:51:21.62#ibcon#about to read 5, iclass 5, count 2 2006.173.11:51:21.62#ibcon#read 5, iclass 5, count 2 2006.173.11:51:21.62#ibcon#about to read 6, iclass 5, count 2 2006.173.11:51:21.62#ibcon#read 6, iclass 5, count 2 2006.173.11:51:21.62#ibcon#end of sib2, iclass 5, count 2 2006.173.11:51:21.62#ibcon#*after write, iclass 5, count 2 2006.173.11:51:21.62#ibcon#*before return 0, iclass 5, count 2 2006.173.11:51:21.62#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.11:51:21.62#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.11:51:21.62#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.11:51:21.62#ibcon#ireg 7 cls_cnt 0 2006.173.11:51:21.62#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.11:51:21.74#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.11:51:21.74#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.11:51:21.74#ibcon#enter wrdev, iclass 5, count 0 2006.173.11:51:21.74#ibcon#first serial, iclass 5, count 0 2006.173.11:51:21.74#ibcon#enter sib2, iclass 5, count 0 2006.173.11:51:21.74#ibcon#flushed, iclass 5, count 0 2006.173.11:51:21.74#ibcon#about to write, iclass 5, count 0 2006.173.11:51:21.74#ibcon#wrote, iclass 5, count 0 2006.173.11:51:21.74#ibcon#about to read 3, iclass 5, count 0 2006.173.11:51:21.76#ibcon#read 3, iclass 5, count 0 2006.173.11:51:21.76#ibcon#about to read 4, iclass 5, count 0 2006.173.11:51:21.76#ibcon#read 4, iclass 5, count 0 2006.173.11:51:21.76#ibcon#about to read 5, iclass 5, count 0 2006.173.11:51:21.76#ibcon#read 5, iclass 5, count 0 2006.173.11:51:21.76#ibcon#about to read 6, iclass 5, count 0 2006.173.11:51:21.76#ibcon#read 6, iclass 5, count 0 2006.173.11:51:21.76#ibcon#end of sib2, iclass 5, count 0 2006.173.11:51:21.76#ibcon#*mode == 0, iclass 5, count 0 2006.173.11:51:21.76#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.11:51:21.76#ibcon#[27=USB\r\n] 2006.173.11:51:21.76#ibcon#*before write, iclass 5, count 0 2006.173.11:51:21.76#ibcon#enter sib2, iclass 5, count 0 2006.173.11:51:21.76#ibcon#flushed, iclass 5, count 0 2006.173.11:51:21.76#ibcon#about to write, iclass 5, count 0 2006.173.11:51:21.76#ibcon#wrote, iclass 5, count 0 2006.173.11:51:21.76#ibcon#about to read 3, iclass 5, count 0 2006.173.11:51:21.79#ibcon#read 3, iclass 5, count 0 2006.173.11:51:21.79#ibcon#about to read 4, iclass 5, count 0 2006.173.11:51:21.79#ibcon#read 4, iclass 5, count 0 2006.173.11:51:21.79#ibcon#about to read 5, iclass 5, count 0 2006.173.11:51:21.79#ibcon#read 5, iclass 5, count 0 2006.173.11:51:21.79#ibcon#about to read 6, iclass 5, count 0 2006.173.11:51:21.79#ibcon#read 6, iclass 5, count 0 2006.173.11:51:21.79#ibcon#end of sib2, iclass 5, count 0 2006.173.11:51:21.79#ibcon#*after write, iclass 5, count 0 2006.173.11:51:21.79#ibcon#*before return 0, iclass 5, count 0 2006.173.11:51:21.79#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.11:51:21.79#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.11:51:21.79#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.11:51:21.79#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.11:51:21.79$vck44/vblo=7,734.99 2006.173.11:51:21.79#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.11:51:21.79#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.11:51:21.79#ibcon#ireg 17 cls_cnt 0 2006.173.11:51:21.79#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.11:51:21.79#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.11:51:21.79#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.11:51:21.79#ibcon#enter wrdev, iclass 7, count 0 2006.173.11:51:21.79#ibcon#first serial, iclass 7, count 0 2006.173.11:51:21.79#ibcon#enter sib2, iclass 7, count 0 2006.173.11:51:21.79#ibcon#flushed, iclass 7, count 0 2006.173.11:51:21.79#ibcon#about to write, iclass 7, count 0 2006.173.11:51:21.79#ibcon#wrote, iclass 7, count 0 2006.173.11:51:21.79#ibcon#about to read 3, iclass 7, count 0 2006.173.11:51:21.81#ibcon#read 3, iclass 7, count 0 2006.173.11:51:21.81#ibcon#about to read 4, iclass 7, count 0 2006.173.11:51:21.81#ibcon#read 4, iclass 7, count 0 2006.173.11:51:21.81#ibcon#about to read 5, iclass 7, count 0 2006.173.11:51:21.81#ibcon#read 5, iclass 7, count 0 2006.173.11:51:21.81#ibcon#about to read 6, iclass 7, count 0 2006.173.11:51:21.81#ibcon#read 6, iclass 7, count 0 2006.173.11:51:21.81#ibcon#end of sib2, iclass 7, count 0 2006.173.11:51:21.81#ibcon#*mode == 0, iclass 7, count 0 2006.173.11:51:21.81#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.11:51:21.81#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.11:51:21.81#ibcon#*before write, iclass 7, count 0 2006.173.11:51:21.81#ibcon#enter sib2, iclass 7, count 0 2006.173.11:51:21.81#ibcon#flushed, iclass 7, count 0 2006.173.11:51:21.81#ibcon#about to write, iclass 7, count 0 2006.173.11:51:21.81#ibcon#wrote, iclass 7, count 0 2006.173.11:51:21.81#ibcon#about to read 3, iclass 7, count 0 2006.173.11:51:21.85#ibcon#read 3, iclass 7, count 0 2006.173.11:51:21.85#ibcon#about to read 4, iclass 7, count 0 2006.173.11:51:21.85#ibcon#read 4, iclass 7, count 0 2006.173.11:51:21.85#ibcon#about to read 5, iclass 7, count 0 2006.173.11:51:21.85#ibcon#read 5, iclass 7, count 0 2006.173.11:51:21.85#ibcon#about to read 6, iclass 7, count 0 2006.173.11:51:21.85#ibcon#read 6, iclass 7, count 0 2006.173.11:51:21.85#ibcon#end of sib2, iclass 7, count 0 2006.173.11:51:21.85#ibcon#*after write, iclass 7, count 0 2006.173.11:51:21.85#ibcon#*before return 0, iclass 7, count 0 2006.173.11:51:21.85#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.11:51:21.85#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.11:51:21.85#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.11:51:21.85#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.11:51:21.85$vck44/vb=7,4 2006.173.11:51:21.85#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.11:51:21.85#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.11:51:21.85#ibcon#ireg 11 cls_cnt 2 2006.173.11:51:21.85#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.11:51:21.91#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.11:51:21.91#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.11:51:21.91#ibcon#enter wrdev, iclass 11, count 2 2006.173.11:51:21.91#ibcon#first serial, iclass 11, count 2 2006.173.11:51:21.91#ibcon#enter sib2, iclass 11, count 2 2006.173.11:51:21.91#ibcon#flushed, iclass 11, count 2 2006.173.11:51:21.91#ibcon#about to write, iclass 11, count 2 2006.173.11:51:21.91#ibcon#wrote, iclass 11, count 2 2006.173.11:51:21.91#ibcon#about to read 3, iclass 11, count 2 2006.173.11:51:21.93#ibcon#read 3, iclass 11, count 2 2006.173.11:51:21.93#ibcon#about to read 4, iclass 11, count 2 2006.173.11:51:21.93#ibcon#read 4, iclass 11, count 2 2006.173.11:51:21.93#ibcon#about to read 5, iclass 11, count 2 2006.173.11:51:21.93#ibcon#read 5, iclass 11, count 2 2006.173.11:51:21.93#ibcon#about to read 6, iclass 11, count 2 2006.173.11:51:21.93#ibcon#read 6, iclass 11, count 2 2006.173.11:51:21.93#ibcon#end of sib2, iclass 11, count 2 2006.173.11:51:21.93#ibcon#*mode == 0, iclass 11, count 2 2006.173.11:51:21.93#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.11:51:21.93#ibcon#[27=AT07-04\r\n] 2006.173.11:51:21.93#ibcon#*before write, iclass 11, count 2 2006.173.11:51:21.93#ibcon#enter sib2, iclass 11, count 2 2006.173.11:51:21.93#ibcon#flushed, iclass 11, count 2 2006.173.11:51:21.93#ibcon#about to write, iclass 11, count 2 2006.173.11:51:21.93#ibcon#wrote, iclass 11, count 2 2006.173.11:51:21.93#ibcon#about to read 3, iclass 11, count 2 2006.173.11:51:21.96#ibcon#read 3, iclass 11, count 2 2006.173.11:51:21.96#ibcon#about to read 4, iclass 11, count 2 2006.173.11:51:21.96#ibcon#read 4, iclass 11, count 2 2006.173.11:51:21.96#ibcon#about to read 5, iclass 11, count 2 2006.173.11:51:21.96#ibcon#read 5, iclass 11, count 2 2006.173.11:51:21.96#ibcon#about to read 6, iclass 11, count 2 2006.173.11:51:21.96#ibcon#read 6, iclass 11, count 2 2006.173.11:51:21.96#ibcon#end of sib2, iclass 11, count 2 2006.173.11:51:21.96#ibcon#*after write, iclass 11, count 2 2006.173.11:51:21.96#ibcon#*before return 0, iclass 11, count 2 2006.173.11:51:21.96#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.11:51:21.96#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.11:51:21.96#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.11:51:21.96#ibcon#ireg 7 cls_cnt 0 2006.173.11:51:21.96#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.11:51:22.08#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.11:51:22.08#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.11:51:22.08#ibcon#enter wrdev, iclass 11, count 0 2006.173.11:51:22.08#ibcon#first serial, iclass 11, count 0 2006.173.11:51:22.08#ibcon#enter sib2, iclass 11, count 0 2006.173.11:51:22.08#ibcon#flushed, iclass 11, count 0 2006.173.11:51:22.08#ibcon#about to write, iclass 11, count 0 2006.173.11:51:22.08#ibcon#wrote, iclass 11, count 0 2006.173.11:51:22.08#ibcon#about to read 3, iclass 11, count 0 2006.173.11:51:22.10#ibcon#read 3, iclass 11, count 0 2006.173.11:51:22.10#ibcon#about to read 4, iclass 11, count 0 2006.173.11:51:22.10#ibcon#read 4, iclass 11, count 0 2006.173.11:51:22.10#ibcon#about to read 5, iclass 11, count 0 2006.173.11:51:22.10#ibcon#read 5, iclass 11, count 0 2006.173.11:51:22.10#ibcon#about to read 6, iclass 11, count 0 2006.173.11:51:22.10#ibcon#read 6, iclass 11, count 0 2006.173.11:51:22.10#ibcon#end of sib2, iclass 11, count 0 2006.173.11:51:22.10#ibcon#*mode == 0, iclass 11, count 0 2006.173.11:51:22.10#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.11:51:22.10#ibcon#[27=USB\r\n] 2006.173.11:51:22.10#ibcon#*before write, iclass 11, count 0 2006.173.11:51:22.10#ibcon#enter sib2, iclass 11, count 0 2006.173.11:51:22.10#ibcon#flushed, iclass 11, count 0 2006.173.11:51:22.10#ibcon#about to write, iclass 11, count 0 2006.173.11:51:22.10#ibcon#wrote, iclass 11, count 0 2006.173.11:51:22.10#ibcon#about to read 3, iclass 11, count 0 2006.173.11:51:22.13#ibcon#read 3, iclass 11, count 0 2006.173.11:51:22.13#ibcon#about to read 4, iclass 11, count 0 2006.173.11:51:22.13#ibcon#read 4, iclass 11, count 0 2006.173.11:51:22.13#ibcon#about to read 5, iclass 11, count 0 2006.173.11:51:22.13#ibcon#read 5, iclass 11, count 0 2006.173.11:51:22.13#ibcon#about to read 6, iclass 11, count 0 2006.173.11:51:22.13#ibcon#read 6, iclass 11, count 0 2006.173.11:51:22.13#ibcon#end of sib2, iclass 11, count 0 2006.173.11:51:22.13#ibcon#*after write, iclass 11, count 0 2006.173.11:51:22.13#ibcon#*before return 0, iclass 11, count 0 2006.173.11:51:22.13#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.11:51:22.13#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.11:51:22.13#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.11:51:22.13#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.11:51:22.13$vck44/vblo=8,744.99 2006.173.11:51:22.13#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.11:51:22.13#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.11:51:22.13#ibcon#ireg 17 cls_cnt 0 2006.173.11:51:22.13#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.11:51:22.13#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.11:51:22.13#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.11:51:22.13#ibcon#enter wrdev, iclass 13, count 0 2006.173.11:51:22.13#ibcon#first serial, iclass 13, count 0 2006.173.11:51:22.13#ibcon#enter sib2, iclass 13, count 0 2006.173.11:51:22.13#ibcon#flushed, iclass 13, count 0 2006.173.11:51:22.13#ibcon#about to write, iclass 13, count 0 2006.173.11:51:22.13#ibcon#wrote, iclass 13, count 0 2006.173.11:51:22.13#ibcon#about to read 3, iclass 13, count 0 2006.173.11:51:22.15#ibcon#read 3, iclass 13, count 0 2006.173.11:51:22.15#ibcon#about to read 4, iclass 13, count 0 2006.173.11:51:22.15#ibcon#read 4, iclass 13, count 0 2006.173.11:51:22.15#ibcon#about to read 5, iclass 13, count 0 2006.173.11:51:22.15#ibcon#read 5, iclass 13, count 0 2006.173.11:51:22.15#ibcon#about to read 6, iclass 13, count 0 2006.173.11:51:22.15#ibcon#read 6, iclass 13, count 0 2006.173.11:51:22.15#ibcon#end of sib2, iclass 13, count 0 2006.173.11:51:22.15#ibcon#*mode == 0, iclass 13, count 0 2006.173.11:51:22.15#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.11:51:22.15#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.11:51:22.15#ibcon#*before write, iclass 13, count 0 2006.173.11:51:22.15#ibcon#enter sib2, iclass 13, count 0 2006.173.11:51:22.15#ibcon#flushed, iclass 13, count 0 2006.173.11:51:22.15#ibcon#about to write, iclass 13, count 0 2006.173.11:51:22.15#ibcon#wrote, iclass 13, count 0 2006.173.11:51:22.15#ibcon#about to read 3, iclass 13, count 0 2006.173.11:51:22.19#ibcon#read 3, iclass 13, count 0 2006.173.11:51:22.19#ibcon#about to read 4, iclass 13, count 0 2006.173.11:51:22.19#ibcon#read 4, iclass 13, count 0 2006.173.11:51:22.19#ibcon#about to read 5, iclass 13, count 0 2006.173.11:51:22.19#ibcon#read 5, iclass 13, count 0 2006.173.11:51:22.19#ibcon#about to read 6, iclass 13, count 0 2006.173.11:51:22.19#ibcon#read 6, iclass 13, count 0 2006.173.11:51:22.19#ibcon#end of sib2, iclass 13, count 0 2006.173.11:51:22.19#ibcon#*after write, iclass 13, count 0 2006.173.11:51:22.19#ibcon#*before return 0, iclass 13, count 0 2006.173.11:51:22.19#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.11:51:22.19#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.11:51:22.19#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.11:51:22.19#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.11:51:22.19$vck44/vb=8,4 2006.173.11:51:22.19#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.11:51:22.19#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.11:51:22.19#ibcon#ireg 11 cls_cnt 2 2006.173.11:51:22.19#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.11:51:22.25#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.11:51:22.25#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.11:51:22.25#ibcon#enter wrdev, iclass 15, count 2 2006.173.11:51:22.25#ibcon#first serial, iclass 15, count 2 2006.173.11:51:22.25#ibcon#enter sib2, iclass 15, count 2 2006.173.11:51:22.25#ibcon#flushed, iclass 15, count 2 2006.173.11:51:22.25#ibcon#about to write, iclass 15, count 2 2006.173.11:51:22.25#ibcon#wrote, iclass 15, count 2 2006.173.11:51:22.25#ibcon#about to read 3, iclass 15, count 2 2006.173.11:51:22.27#ibcon#read 3, iclass 15, count 2 2006.173.11:51:22.27#ibcon#about to read 4, iclass 15, count 2 2006.173.11:51:22.27#ibcon#read 4, iclass 15, count 2 2006.173.11:51:22.27#ibcon#about to read 5, iclass 15, count 2 2006.173.11:51:22.27#ibcon#read 5, iclass 15, count 2 2006.173.11:51:22.27#ibcon#about to read 6, iclass 15, count 2 2006.173.11:51:22.27#ibcon#read 6, iclass 15, count 2 2006.173.11:51:22.27#ibcon#end of sib2, iclass 15, count 2 2006.173.11:51:22.27#ibcon#*mode == 0, iclass 15, count 2 2006.173.11:51:22.27#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.11:51:22.27#ibcon#[27=AT08-04\r\n] 2006.173.11:51:22.27#ibcon#*before write, iclass 15, count 2 2006.173.11:51:22.27#ibcon#enter sib2, iclass 15, count 2 2006.173.11:51:22.27#ibcon#flushed, iclass 15, count 2 2006.173.11:51:22.27#ibcon#about to write, iclass 15, count 2 2006.173.11:51:22.27#ibcon#wrote, iclass 15, count 2 2006.173.11:51:22.27#ibcon#about to read 3, iclass 15, count 2 2006.173.11:51:22.30#ibcon#read 3, iclass 15, count 2 2006.173.11:51:22.30#ibcon#about to read 4, iclass 15, count 2 2006.173.11:51:22.30#ibcon#read 4, iclass 15, count 2 2006.173.11:51:22.30#ibcon#about to read 5, iclass 15, count 2 2006.173.11:51:22.30#ibcon#read 5, iclass 15, count 2 2006.173.11:51:22.30#ibcon#about to read 6, iclass 15, count 2 2006.173.11:51:22.30#ibcon#read 6, iclass 15, count 2 2006.173.11:51:22.30#ibcon#end of sib2, iclass 15, count 2 2006.173.11:51:22.30#ibcon#*after write, iclass 15, count 2 2006.173.11:51:22.30#ibcon#*before return 0, iclass 15, count 2 2006.173.11:51:22.30#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.11:51:22.30#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.11:51:22.30#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.11:51:22.30#ibcon#ireg 7 cls_cnt 0 2006.173.11:51:22.30#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.11:51:22.42#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.11:51:22.42#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.11:51:22.42#ibcon#enter wrdev, iclass 15, count 0 2006.173.11:51:22.42#ibcon#first serial, iclass 15, count 0 2006.173.11:51:22.42#ibcon#enter sib2, iclass 15, count 0 2006.173.11:51:22.42#ibcon#flushed, iclass 15, count 0 2006.173.11:51:22.42#ibcon#about to write, iclass 15, count 0 2006.173.11:51:22.42#ibcon#wrote, iclass 15, count 0 2006.173.11:51:22.42#ibcon#about to read 3, iclass 15, count 0 2006.173.11:51:22.44#ibcon#read 3, iclass 15, count 0 2006.173.11:51:22.44#ibcon#about to read 4, iclass 15, count 0 2006.173.11:51:22.44#ibcon#read 4, iclass 15, count 0 2006.173.11:51:22.44#ibcon#about to read 5, iclass 15, count 0 2006.173.11:51:22.44#ibcon#read 5, iclass 15, count 0 2006.173.11:51:22.44#ibcon#about to read 6, iclass 15, count 0 2006.173.11:51:22.44#ibcon#read 6, iclass 15, count 0 2006.173.11:51:22.44#ibcon#end of sib2, iclass 15, count 0 2006.173.11:51:22.44#ibcon#*mode == 0, iclass 15, count 0 2006.173.11:51:22.44#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.11:51:22.44#ibcon#[27=USB\r\n] 2006.173.11:51:22.44#ibcon#*before write, iclass 15, count 0 2006.173.11:51:22.44#ibcon#enter sib2, iclass 15, count 0 2006.173.11:51:22.44#ibcon#flushed, iclass 15, count 0 2006.173.11:51:22.44#ibcon#about to write, iclass 15, count 0 2006.173.11:51:22.44#ibcon#wrote, iclass 15, count 0 2006.173.11:51:22.44#ibcon#about to read 3, iclass 15, count 0 2006.173.11:51:22.47#ibcon#read 3, iclass 15, count 0 2006.173.11:51:22.47#ibcon#about to read 4, iclass 15, count 0 2006.173.11:51:22.47#ibcon#read 4, iclass 15, count 0 2006.173.11:51:22.47#ibcon#about to read 5, iclass 15, count 0 2006.173.11:51:22.47#ibcon#read 5, iclass 15, count 0 2006.173.11:51:22.47#ibcon#about to read 6, iclass 15, count 0 2006.173.11:51:22.47#ibcon#read 6, iclass 15, count 0 2006.173.11:51:22.47#ibcon#end of sib2, iclass 15, count 0 2006.173.11:51:22.47#ibcon#*after write, iclass 15, count 0 2006.173.11:51:22.47#ibcon#*before return 0, iclass 15, count 0 2006.173.11:51:22.47#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.11:51:22.47#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.11:51:22.47#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.11:51:22.47#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.11:51:22.47$vck44/vabw=wide 2006.173.11:51:22.47#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.11:51:22.47#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.11:51:22.47#ibcon#ireg 8 cls_cnt 0 2006.173.11:51:22.47#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.11:51:22.47#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.11:51:22.47#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.11:51:22.47#ibcon#enter wrdev, iclass 17, count 0 2006.173.11:51:22.47#ibcon#first serial, iclass 17, count 0 2006.173.11:51:22.47#ibcon#enter sib2, iclass 17, count 0 2006.173.11:51:22.47#ibcon#flushed, iclass 17, count 0 2006.173.11:51:22.47#ibcon#about to write, iclass 17, count 0 2006.173.11:51:22.47#ibcon#wrote, iclass 17, count 0 2006.173.11:51:22.47#ibcon#about to read 3, iclass 17, count 0 2006.173.11:51:22.49#ibcon#read 3, iclass 17, count 0 2006.173.11:51:22.49#ibcon#about to read 4, iclass 17, count 0 2006.173.11:51:22.49#ibcon#read 4, iclass 17, count 0 2006.173.11:51:22.49#ibcon#about to read 5, iclass 17, count 0 2006.173.11:51:22.49#ibcon#read 5, iclass 17, count 0 2006.173.11:51:22.49#ibcon#about to read 6, iclass 17, count 0 2006.173.11:51:22.49#ibcon#read 6, iclass 17, count 0 2006.173.11:51:22.49#ibcon#end of sib2, iclass 17, count 0 2006.173.11:51:22.49#ibcon#*mode == 0, iclass 17, count 0 2006.173.11:51:22.49#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.11:51:22.49#ibcon#[25=BW32\r\n] 2006.173.11:51:22.49#ibcon#*before write, iclass 17, count 0 2006.173.11:51:22.49#ibcon#enter sib2, iclass 17, count 0 2006.173.11:51:22.49#ibcon#flushed, iclass 17, count 0 2006.173.11:51:22.49#ibcon#about to write, iclass 17, count 0 2006.173.11:51:22.49#ibcon#wrote, iclass 17, count 0 2006.173.11:51:22.49#ibcon#about to read 3, iclass 17, count 0 2006.173.11:51:22.52#ibcon#read 3, iclass 17, count 0 2006.173.11:51:22.52#ibcon#about to read 4, iclass 17, count 0 2006.173.11:51:22.52#ibcon#read 4, iclass 17, count 0 2006.173.11:51:22.52#ibcon#about to read 5, iclass 17, count 0 2006.173.11:51:22.52#ibcon#read 5, iclass 17, count 0 2006.173.11:51:22.52#ibcon#about to read 6, iclass 17, count 0 2006.173.11:51:22.52#ibcon#read 6, iclass 17, count 0 2006.173.11:51:22.52#ibcon#end of sib2, iclass 17, count 0 2006.173.11:51:22.52#ibcon#*after write, iclass 17, count 0 2006.173.11:51:22.52#ibcon#*before return 0, iclass 17, count 0 2006.173.11:51:22.52#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.11:51:22.52#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.11:51:22.52#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.11:51:22.52#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.11:51:22.52$vck44/vbbw=wide 2006.173.11:51:22.52#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.11:51:22.52#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.11:51:22.52#ibcon#ireg 8 cls_cnt 0 2006.173.11:51:22.52#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.11:51:22.59#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.11:51:22.59#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.11:51:22.59#ibcon#enter wrdev, iclass 19, count 0 2006.173.11:51:22.59#ibcon#first serial, iclass 19, count 0 2006.173.11:51:22.59#ibcon#enter sib2, iclass 19, count 0 2006.173.11:51:22.59#ibcon#flushed, iclass 19, count 0 2006.173.11:51:22.59#ibcon#about to write, iclass 19, count 0 2006.173.11:51:22.59#ibcon#wrote, iclass 19, count 0 2006.173.11:51:22.59#ibcon#about to read 3, iclass 19, count 0 2006.173.11:51:22.61#ibcon#read 3, iclass 19, count 0 2006.173.11:51:22.61#ibcon#about to read 4, iclass 19, count 0 2006.173.11:51:22.61#ibcon#read 4, iclass 19, count 0 2006.173.11:51:22.61#ibcon#about to read 5, iclass 19, count 0 2006.173.11:51:22.61#ibcon#read 5, iclass 19, count 0 2006.173.11:51:22.61#ibcon#about to read 6, iclass 19, count 0 2006.173.11:51:22.61#ibcon#read 6, iclass 19, count 0 2006.173.11:51:22.61#ibcon#end of sib2, iclass 19, count 0 2006.173.11:51:22.61#ibcon#*mode == 0, iclass 19, count 0 2006.173.11:51:22.61#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.11:51:22.61#ibcon#[27=BW32\r\n] 2006.173.11:51:22.61#ibcon#*before write, iclass 19, count 0 2006.173.11:51:22.61#ibcon#enter sib2, iclass 19, count 0 2006.173.11:51:22.61#ibcon#flushed, iclass 19, count 0 2006.173.11:51:22.61#ibcon#about to write, iclass 19, count 0 2006.173.11:51:22.61#ibcon#wrote, iclass 19, count 0 2006.173.11:51:22.61#ibcon#about to read 3, iclass 19, count 0 2006.173.11:51:22.64#ibcon#read 3, iclass 19, count 0 2006.173.11:51:22.64#ibcon#about to read 4, iclass 19, count 0 2006.173.11:51:22.64#ibcon#read 4, iclass 19, count 0 2006.173.11:51:22.64#ibcon#about to read 5, iclass 19, count 0 2006.173.11:51:22.64#ibcon#read 5, iclass 19, count 0 2006.173.11:51:22.64#ibcon#about to read 6, iclass 19, count 0 2006.173.11:51:22.64#ibcon#read 6, iclass 19, count 0 2006.173.11:51:22.64#ibcon#end of sib2, iclass 19, count 0 2006.173.11:51:22.64#ibcon#*after write, iclass 19, count 0 2006.173.11:51:22.64#ibcon#*before return 0, iclass 19, count 0 2006.173.11:51:22.64#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.11:51:22.64#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.11:51:22.64#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.11:51:22.64#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.11:51:22.64$setupk4/ifdk4 2006.173.11:51:22.64$ifdk4/lo= 2006.173.11:51:22.64$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.11:51:22.64$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.11:51:22.64$ifdk4/patch= 2006.173.11:51:22.64$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.11:51:22.64$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.11:51:22.64$setupk4/!*+20s 2006.173.11:51:27.17#abcon#<5=/01 0.5 1.6 22.12 931004.4\r\n> 2006.173.11:51:27.19#abcon#{5=INTERFACE CLEAR} 2006.173.11:51:27.25#abcon#[5=S1D000X0/0*\r\n] 2006.173.11:51:37.15$setupk4/"tpicd 2006.173.11:51:37.15$setupk4/echo=off 2006.173.11:51:37.15$setupk4/xlog=off 2006.173.11:51:37.15:!2006.173.11:55:49 2006.173.11:51:46.14#trakl#Source acquired 2006.173.11:51:48.14#flagr#flagr/antenna,acquired 2006.173.11:55:49.00:preob 2006.173.11:55:49.13/onsource/TRACKING 2006.173.11:55:49.13:!2006.173.11:55:59 2006.173.11:55:59.00:"tape 2006.173.11:55:59.00:"st=record 2006.173.11:55:59.00:data_valid=on 2006.173.11:55:59.00:midob 2006.173.11:56:00.13/onsource/TRACKING 2006.173.11:56:00.13/wx/22.17,1004.3,94 2006.173.11:56:00.21/cable/+6.5029E-03 2006.173.11:56:01.30/va/01,07,usb,yes,34,37 2006.173.11:56:01.30/va/02,06,usb,yes,34,35 2006.173.11:56:01.30/va/03,05,usb,yes,43,45 2006.173.11:56:01.30/va/04,06,usb,yes,35,37 2006.173.11:56:01.30/va/05,04,usb,yes,27,28 2006.173.11:56:01.30/va/06,03,usb,yes,38,38 2006.173.11:56:01.30/va/07,04,usb,yes,31,32 2006.173.11:56:01.30/va/08,04,usb,yes,26,32 2006.173.11:56:01.53/valo/01,524.99,yes,locked 2006.173.11:56:01.53/valo/02,534.99,yes,locked 2006.173.11:56:01.53/valo/03,564.99,yes,locked 2006.173.11:56:01.53/valo/04,624.99,yes,locked 2006.173.11:56:01.53/valo/05,734.99,yes,locked 2006.173.11:56:01.53/valo/06,814.99,yes,locked 2006.173.11:56:01.53/valo/07,864.99,yes,locked 2006.173.11:56:01.53/valo/08,884.99,yes,locked 2006.173.11:56:02.62/vb/01,04,usb,yes,28,26 2006.173.11:56:02.62/vb/02,04,usb,yes,31,30 2006.173.11:56:02.62/vb/03,04,usb,yes,28,30 2006.173.11:56:02.62/vb/04,04,usb,yes,32,31 2006.173.11:56:02.62/vb/05,04,usb,yes,24,27 2006.173.11:56:02.62/vb/06,04,usb,yes,29,25 2006.173.11:56:02.62/vb/07,04,usb,yes,29,28 2006.173.11:56:02.62/vb/08,04,usb,yes,26,29 2006.173.11:56:02.85/vblo/01,629.99,yes,locked 2006.173.11:56:02.85/vblo/02,634.99,yes,locked 2006.173.11:56:02.85/vblo/03,649.99,yes,locked 2006.173.11:56:02.85/vblo/04,679.99,yes,locked 2006.173.11:56:02.85/vblo/05,709.99,yes,locked 2006.173.11:56:02.85/vblo/06,719.99,yes,locked 2006.173.11:56:02.85/vblo/07,734.99,yes,locked 2006.173.11:56:02.85/vblo/08,744.99,yes,locked 2006.173.11:56:03.00/vabw/8 2006.173.11:56:03.15/vbbw/8 2006.173.11:56:03.24/xfe/off,on,15.0 2006.173.11:56:03.62/ifatt/23,28,28,28 2006.173.11:56:04.07/fmout-gps/S +3.94E-07 2006.173.11:56:04.11:!2006.173.12:01:59 2006.173.12:01:59.00:data_valid=off 2006.173.12:01:59.00:"et 2006.173.12:01:59.01:!+3s 2006.173.12:02:02.02:"tape 2006.173.12:02:02.02:postob 2006.173.12:02:02.13/cable/+6.5027E-03 2006.173.12:02:02.13/wx/22.20,1004.1,95 2006.173.12:02:02.19/fmout-gps/S +3.96E-07 2006.173.12:02:02.19:scan_name=173-1204,jd0606,320 2006.173.12:02:02.20:source=0059+581,010245.76,582411.1,2000.0,cw 2006.173.12:02:03.14#flagr#flagr/antenna,new-source 2006.173.12:02:03.14:checkk5 2006.173.12:02:03.57/chk_autoobs//k5ts1/ autoobs is running! 2006.173.12:02:03.98/chk_autoobs//k5ts2/ autoobs is running! 2006.173.12:02:04.37/chk_autoobs//k5ts3/ autoobs is running! 2006.173.12:02:04.77/chk_autoobs//k5ts4/ autoobs is running! 2006.173.12:02:05.16/chk_obsdata//k5ts1/T1731155??a.dat file size is correct (nominal:1440MB, actual:1436MB). 2006.173.12:02:05.56/chk_obsdata//k5ts2/T1731155??b.dat file size is correct (nominal:1440MB, actual:1436MB). 2006.173.12:02:05.97/chk_obsdata//k5ts3/T1731155??c.dat file size is correct (nominal:1440MB, actual:1436MB). 2006.173.12:02:06.38/chk_obsdata//k5ts4/T1731155??d.dat file size is correct (nominal:1440MB, actual:1436MB). 2006.173.12:02:07.11/k5log//k5ts1_log_newline 2006.173.12:02:07.85/k5log//k5ts2_log_newline 2006.173.12:02:08.58/k5log//k5ts3_log_newline 2006.173.12:02:09.29/k5log//k5ts4_log_newline 2006.173.12:02:09.32/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.12:02:09.32:setupk4=1 2006.173.12:02:09.32$setupk4/echo=on 2006.173.12:02:09.32$setupk4/pcalon 2006.173.12:02:09.32$pcalon/"no phase cal control is implemented here 2006.173.12:02:09.32$setupk4/"tpicd=stop 2006.173.12:02:09.32$setupk4/"rec=synch_on 2006.173.12:02:09.32$setupk4/"rec_mode=128 2006.173.12:02:09.32$setupk4/!* 2006.173.12:02:09.32$setupk4/recpk4 2006.173.12:02:09.32$recpk4/recpatch= 2006.173.12:02:09.33$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.12:02:09.33$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.12:02:09.33$setupk4/vck44 2006.173.12:02:09.33$vck44/valo=1,524.99 2006.173.12:02:09.33#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.12:02:09.33#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.12:02:09.33#ibcon#ireg 17 cls_cnt 0 2006.173.12:02:09.33#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.12:02:09.33#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.12:02:09.33#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.12:02:09.33#ibcon#enter wrdev, iclass 21, count 0 2006.173.12:02:09.33#ibcon#first serial, iclass 21, count 0 2006.173.12:02:09.33#ibcon#enter sib2, iclass 21, count 0 2006.173.12:02:09.33#ibcon#flushed, iclass 21, count 0 2006.173.12:02:09.33#ibcon#about to write, iclass 21, count 0 2006.173.12:02:09.33#ibcon#wrote, iclass 21, count 0 2006.173.12:02:09.33#ibcon#about to read 3, iclass 21, count 0 2006.173.12:02:09.35#ibcon#read 3, iclass 21, count 0 2006.173.12:02:09.35#ibcon#about to read 4, iclass 21, count 0 2006.173.12:02:09.35#ibcon#read 4, iclass 21, count 0 2006.173.12:02:09.35#ibcon#about to read 5, iclass 21, count 0 2006.173.12:02:09.35#ibcon#read 5, iclass 21, count 0 2006.173.12:02:09.35#ibcon#about to read 6, iclass 21, count 0 2006.173.12:02:09.35#ibcon#read 6, iclass 21, count 0 2006.173.12:02:09.35#ibcon#end of sib2, iclass 21, count 0 2006.173.12:02:09.35#ibcon#*mode == 0, iclass 21, count 0 2006.173.12:02:09.35#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.12:02:09.35#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.12:02:09.35#ibcon#*before write, iclass 21, count 0 2006.173.12:02:09.35#ibcon#enter sib2, iclass 21, count 0 2006.173.12:02:09.35#ibcon#flushed, iclass 21, count 0 2006.173.12:02:09.35#ibcon#about to write, iclass 21, count 0 2006.173.12:02:09.35#ibcon#wrote, iclass 21, count 0 2006.173.12:02:09.35#ibcon#about to read 3, iclass 21, count 0 2006.173.12:02:09.40#ibcon#read 3, iclass 21, count 0 2006.173.12:02:09.40#ibcon#about to read 4, iclass 21, count 0 2006.173.12:02:09.40#ibcon#read 4, iclass 21, count 0 2006.173.12:02:09.40#ibcon#about to read 5, iclass 21, count 0 2006.173.12:02:09.40#ibcon#read 5, iclass 21, count 0 2006.173.12:02:09.40#ibcon#about to read 6, iclass 21, count 0 2006.173.12:02:09.40#ibcon#read 6, iclass 21, count 0 2006.173.12:02:09.40#ibcon#end of sib2, iclass 21, count 0 2006.173.12:02:09.40#ibcon#*after write, iclass 21, count 0 2006.173.12:02:09.40#ibcon#*before return 0, iclass 21, count 0 2006.173.12:02:09.40#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.12:02:09.40#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.12:02:09.40#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.12:02:09.40#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.12:02:09.40$vck44/va=1,7 2006.173.12:02:09.40#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.12:02:09.40#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.12:02:09.40#ibcon#ireg 11 cls_cnt 2 2006.173.12:02:09.40#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.12:02:09.40#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.12:02:09.40#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.12:02:09.40#ibcon#enter wrdev, iclass 23, count 2 2006.173.12:02:09.40#ibcon#first serial, iclass 23, count 2 2006.173.12:02:09.40#ibcon#enter sib2, iclass 23, count 2 2006.173.12:02:09.40#ibcon#flushed, iclass 23, count 2 2006.173.12:02:09.40#ibcon#about to write, iclass 23, count 2 2006.173.12:02:09.40#ibcon#wrote, iclass 23, count 2 2006.173.12:02:09.40#ibcon#about to read 3, iclass 23, count 2 2006.173.12:02:09.42#ibcon#read 3, iclass 23, count 2 2006.173.12:02:09.42#ibcon#about to read 4, iclass 23, count 2 2006.173.12:02:09.42#ibcon#read 4, iclass 23, count 2 2006.173.12:02:09.42#ibcon#about to read 5, iclass 23, count 2 2006.173.12:02:09.42#ibcon#read 5, iclass 23, count 2 2006.173.12:02:09.42#ibcon#about to read 6, iclass 23, count 2 2006.173.12:02:09.42#ibcon#read 6, iclass 23, count 2 2006.173.12:02:09.42#ibcon#end of sib2, iclass 23, count 2 2006.173.12:02:09.42#ibcon#*mode == 0, iclass 23, count 2 2006.173.12:02:09.42#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.12:02:09.42#ibcon#[25=AT01-07\r\n] 2006.173.12:02:09.42#ibcon#*before write, iclass 23, count 2 2006.173.12:02:09.42#ibcon#enter sib2, iclass 23, count 2 2006.173.12:02:09.42#ibcon#flushed, iclass 23, count 2 2006.173.12:02:09.42#ibcon#about to write, iclass 23, count 2 2006.173.12:02:09.42#ibcon#wrote, iclass 23, count 2 2006.173.12:02:09.42#ibcon#about to read 3, iclass 23, count 2 2006.173.12:02:09.45#ibcon#read 3, iclass 23, count 2 2006.173.12:02:09.45#ibcon#about to read 4, iclass 23, count 2 2006.173.12:02:09.45#ibcon#read 4, iclass 23, count 2 2006.173.12:02:09.45#ibcon#about to read 5, iclass 23, count 2 2006.173.12:02:09.45#ibcon#read 5, iclass 23, count 2 2006.173.12:02:09.45#ibcon#about to read 6, iclass 23, count 2 2006.173.12:02:09.45#ibcon#read 6, iclass 23, count 2 2006.173.12:02:09.45#ibcon#end of sib2, iclass 23, count 2 2006.173.12:02:09.45#ibcon#*after write, iclass 23, count 2 2006.173.12:02:09.45#ibcon#*before return 0, iclass 23, count 2 2006.173.12:02:09.45#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.12:02:09.45#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.12:02:09.45#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.12:02:09.45#ibcon#ireg 7 cls_cnt 0 2006.173.12:02:09.45#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.12:02:09.57#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.12:02:09.57#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.12:02:09.57#ibcon#enter wrdev, iclass 23, count 0 2006.173.12:02:09.57#ibcon#first serial, iclass 23, count 0 2006.173.12:02:09.57#ibcon#enter sib2, iclass 23, count 0 2006.173.12:02:09.57#ibcon#flushed, iclass 23, count 0 2006.173.12:02:09.57#ibcon#about to write, iclass 23, count 0 2006.173.12:02:09.57#ibcon#wrote, iclass 23, count 0 2006.173.12:02:09.57#ibcon#about to read 3, iclass 23, count 0 2006.173.12:02:09.59#ibcon#read 3, iclass 23, count 0 2006.173.12:02:09.59#ibcon#about to read 4, iclass 23, count 0 2006.173.12:02:09.59#ibcon#read 4, iclass 23, count 0 2006.173.12:02:09.59#ibcon#about to read 5, iclass 23, count 0 2006.173.12:02:09.59#ibcon#read 5, iclass 23, count 0 2006.173.12:02:09.59#ibcon#about to read 6, iclass 23, count 0 2006.173.12:02:09.59#ibcon#read 6, iclass 23, count 0 2006.173.12:02:09.59#ibcon#end of sib2, iclass 23, count 0 2006.173.12:02:09.59#ibcon#*mode == 0, iclass 23, count 0 2006.173.12:02:09.59#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.12:02:09.59#ibcon#[25=USB\r\n] 2006.173.12:02:09.59#ibcon#*before write, iclass 23, count 0 2006.173.12:02:09.59#ibcon#enter sib2, iclass 23, count 0 2006.173.12:02:09.59#ibcon#flushed, iclass 23, count 0 2006.173.12:02:09.59#ibcon#about to write, iclass 23, count 0 2006.173.12:02:09.59#ibcon#wrote, iclass 23, count 0 2006.173.12:02:09.59#ibcon#about to read 3, iclass 23, count 0 2006.173.12:02:09.62#ibcon#read 3, iclass 23, count 0 2006.173.12:02:09.62#ibcon#about to read 4, iclass 23, count 0 2006.173.12:02:09.62#ibcon#read 4, iclass 23, count 0 2006.173.12:02:09.62#ibcon#about to read 5, iclass 23, count 0 2006.173.12:02:09.62#ibcon#read 5, iclass 23, count 0 2006.173.12:02:09.62#ibcon#about to read 6, iclass 23, count 0 2006.173.12:02:09.62#ibcon#read 6, iclass 23, count 0 2006.173.12:02:09.62#ibcon#end of sib2, iclass 23, count 0 2006.173.12:02:09.62#ibcon#*after write, iclass 23, count 0 2006.173.12:02:09.62#ibcon#*before return 0, iclass 23, count 0 2006.173.12:02:09.62#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.12:02:09.62#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.12:02:09.62#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.12:02:09.62#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.12:02:09.62$vck44/valo=2,534.99 2006.173.12:02:09.62#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.12:02:09.62#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.12:02:09.62#ibcon#ireg 17 cls_cnt 0 2006.173.12:02:09.62#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.12:02:09.62#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.12:02:09.62#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.12:02:09.62#ibcon#enter wrdev, iclass 25, count 0 2006.173.12:02:09.62#ibcon#first serial, iclass 25, count 0 2006.173.12:02:09.62#ibcon#enter sib2, iclass 25, count 0 2006.173.12:02:09.62#ibcon#flushed, iclass 25, count 0 2006.173.12:02:09.62#ibcon#about to write, iclass 25, count 0 2006.173.12:02:09.62#ibcon#wrote, iclass 25, count 0 2006.173.12:02:09.62#ibcon#about to read 3, iclass 25, count 0 2006.173.12:02:09.64#ibcon#read 3, iclass 25, count 0 2006.173.12:02:09.64#ibcon#about to read 4, iclass 25, count 0 2006.173.12:02:09.64#ibcon#read 4, iclass 25, count 0 2006.173.12:02:09.64#ibcon#about to read 5, iclass 25, count 0 2006.173.12:02:09.64#ibcon#read 5, iclass 25, count 0 2006.173.12:02:09.64#ibcon#about to read 6, iclass 25, count 0 2006.173.12:02:09.64#ibcon#read 6, iclass 25, count 0 2006.173.12:02:09.64#ibcon#end of sib2, iclass 25, count 0 2006.173.12:02:09.64#ibcon#*mode == 0, iclass 25, count 0 2006.173.12:02:09.64#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.12:02:09.64#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.12:02:09.64#ibcon#*before write, iclass 25, count 0 2006.173.12:02:09.64#ibcon#enter sib2, iclass 25, count 0 2006.173.12:02:09.64#ibcon#flushed, iclass 25, count 0 2006.173.12:02:09.64#ibcon#about to write, iclass 25, count 0 2006.173.12:02:09.64#ibcon#wrote, iclass 25, count 0 2006.173.12:02:09.64#ibcon#about to read 3, iclass 25, count 0 2006.173.12:02:09.68#ibcon#read 3, iclass 25, count 0 2006.173.12:02:09.68#ibcon#about to read 4, iclass 25, count 0 2006.173.12:02:09.68#ibcon#read 4, iclass 25, count 0 2006.173.12:02:09.68#ibcon#about to read 5, iclass 25, count 0 2006.173.12:02:09.68#ibcon#read 5, iclass 25, count 0 2006.173.12:02:09.68#ibcon#about to read 6, iclass 25, count 0 2006.173.12:02:09.68#ibcon#read 6, iclass 25, count 0 2006.173.12:02:09.68#ibcon#end of sib2, iclass 25, count 0 2006.173.12:02:09.68#ibcon#*after write, iclass 25, count 0 2006.173.12:02:09.68#ibcon#*before return 0, iclass 25, count 0 2006.173.12:02:09.68#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.12:02:09.68#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.12:02:09.68#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.12:02:09.68#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.12:02:09.68$vck44/va=2,6 2006.173.12:02:09.68#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.12:02:09.68#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.12:02:09.68#ibcon#ireg 11 cls_cnt 2 2006.173.12:02:09.68#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.12:02:09.74#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.12:02:09.74#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.12:02:09.74#ibcon#enter wrdev, iclass 27, count 2 2006.173.12:02:09.74#ibcon#first serial, iclass 27, count 2 2006.173.12:02:09.74#ibcon#enter sib2, iclass 27, count 2 2006.173.12:02:09.74#ibcon#flushed, iclass 27, count 2 2006.173.12:02:09.74#ibcon#about to write, iclass 27, count 2 2006.173.12:02:09.74#ibcon#wrote, iclass 27, count 2 2006.173.12:02:09.74#ibcon#about to read 3, iclass 27, count 2 2006.173.12:02:09.76#ibcon#read 3, iclass 27, count 2 2006.173.12:02:09.76#ibcon#about to read 4, iclass 27, count 2 2006.173.12:02:09.76#ibcon#read 4, iclass 27, count 2 2006.173.12:02:09.76#ibcon#about to read 5, iclass 27, count 2 2006.173.12:02:09.76#ibcon#read 5, iclass 27, count 2 2006.173.12:02:09.76#ibcon#about to read 6, iclass 27, count 2 2006.173.12:02:09.76#ibcon#read 6, iclass 27, count 2 2006.173.12:02:09.76#ibcon#end of sib2, iclass 27, count 2 2006.173.12:02:09.76#ibcon#*mode == 0, iclass 27, count 2 2006.173.12:02:09.76#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.12:02:09.76#ibcon#[25=AT02-06\r\n] 2006.173.12:02:09.76#ibcon#*before write, iclass 27, count 2 2006.173.12:02:09.76#ibcon#enter sib2, iclass 27, count 2 2006.173.12:02:09.76#ibcon#flushed, iclass 27, count 2 2006.173.12:02:09.76#ibcon#about to write, iclass 27, count 2 2006.173.12:02:09.76#ibcon#wrote, iclass 27, count 2 2006.173.12:02:09.76#ibcon#about to read 3, iclass 27, count 2 2006.173.12:02:09.79#ibcon#read 3, iclass 27, count 2 2006.173.12:02:09.79#ibcon#about to read 4, iclass 27, count 2 2006.173.12:02:09.79#ibcon#read 4, iclass 27, count 2 2006.173.12:02:09.79#ibcon#about to read 5, iclass 27, count 2 2006.173.12:02:09.79#ibcon#read 5, iclass 27, count 2 2006.173.12:02:09.79#ibcon#about to read 6, iclass 27, count 2 2006.173.12:02:09.79#ibcon#read 6, iclass 27, count 2 2006.173.12:02:09.79#ibcon#end of sib2, iclass 27, count 2 2006.173.12:02:09.79#ibcon#*after write, iclass 27, count 2 2006.173.12:02:09.79#ibcon#*before return 0, iclass 27, count 2 2006.173.12:02:09.79#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.12:02:09.79#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.12:02:09.79#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.12:02:09.79#ibcon#ireg 7 cls_cnt 0 2006.173.12:02:09.79#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.12:02:09.91#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.12:02:09.91#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.12:02:09.91#ibcon#enter wrdev, iclass 27, count 0 2006.173.12:02:09.91#ibcon#first serial, iclass 27, count 0 2006.173.12:02:09.91#ibcon#enter sib2, iclass 27, count 0 2006.173.12:02:09.91#ibcon#flushed, iclass 27, count 0 2006.173.12:02:09.91#ibcon#about to write, iclass 27, count 0 2006.173.12:02:09.91#ibcon#wrote, iclass 27, count 0 2006.173.12:02:09.91#ibcon#about to read 3, iclass 27, count 0 2006.173.12:02:09.93#ibcon#read 3, iclass 27, count 0 2006.173.12:02:09.93#ibcon#about to read 4, iclass 27, count 0 2006.173.12:02:09.93#ibcon#read 4, iclass 27, count 0 2006.173.12:02:09.93#ibcon#about to read 5, iclass 27, count 0 2006.173.12:02:09.93#ibcon#read 5, iclass 27, count 0 2006.173.12:02:09.93#ibcon#about to read 6, iclass 27, count 0 2006.173.12:02:09.93#ibcon#read 6, iclass 27, count 0 2006.173.12:02:09.93#ibcon#end of sib2, iclass 27, count 0 2006.173.12:02:09.93#ibcon#*mode == 0, iclass 27, count 0 2006.173.12:02:09.93#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.12:02:09.93#ibcon#[25=USB\r\n] 2006.173.12:02:09.93#ibcon#*before write, iclass 27, count 0 2006.173.12:02:09.93#ibcon#enter sib2, iclass 27, count 0 2006.173.12:02:09.93#ibcon#flushed, iclass 27, count 0 2006.173.12:02:09.93#ibcon#about to write, iclass 27, count 0 2006.173.12:02:09.93#ibcon#wrote, iclass 27, count 0 2006.173.12:02:09.93#ibcon#about to read 3, iclass 27, count 0 2006.173.12:02:09.96#ibcon#read 3, iclass 27, count 0 2006.173.12:02:09.96#ibcon#about to read 4, iclass 27, count 0 2006.173.12:02:09.96#ibcon#read 4, iclass 27, count 0 2006.173.12:02:09.96#ibcon#about to read 5, iclass 27, count 0 2006.173.12:02:09.96#ibcon#read 5, iclass 27, count 0 2006.173.12:02:09.96#ibcon#about to read 6, iclass 27, count 0 2006.173.12:02:09.96#ibcon#read 6, iclass 27, count 0 2006.173.12:02:09.96#ibcon#end of sib2, iclass 27, count 0 2006.173.12:02:09.96#ibcon#*after write, iclass 27, count 0 2006.173.12:02:09.96#ibcon#*before return 0, iclass 27, count 0 2006.173.12:02:09.96#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.12:02:09.96#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.12:02:09.96#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.12:02:09.96#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.12:02:09.96$vck44/valo=3,564.99 2006.173.12:02:09.96#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.12:02:09.96#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.12:02:09.96#ibcon#ireg 17 cls_cnt 0 2006.173.12:02:09.96#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.12:02:09.96#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.12:02:09.96#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.12:02:09.96#ibcon#enter wrdev, iclass 29, count 0 2006.173.12:02:09.96#ibcon#first serial, iclass 29, count 0 2006.173.12:02:09.96#ibcon#enter sib2, iclass 29, count 0 2006.173.12:02:09.96#ibcon#flushed, iclass 29, count 0 2006.173.12:02:09.96#ibcon#about to write, iclass 29, count 0 2006.173.12:02:09.96#ibcon#wrote, iclass 29, count 0 2006.173.12:02:09.96#ibcon#about to read 3, iclass 29, count 0 2006.173.12:02:09.98#ibcon#read 3, iclass 29, count 0 2006.173.12:02:09.98#ibcon#about to read 4, iclass 29, count 0 2006.173.12:02:09.98#ibcon#read 4, iclass 29, count 0 2006.173.12:02:09.98#ibcon#about to read 5, iclass 29, count 0 2006.173.12:02:09.98#ibcon#read 5, iclass 29, count 0 2006.173.12:02:09.98#ibcon#about to read 6, iclass 29, count 0 2006.173.12:02:09.98#ibcon#read 6, iclass 29, count 0 2006.173.12:02:09.98#ibcon#end of sib2, iclass 29, count 0 2006.173.12:02:09.98#ibcon#*mode == 0, iclass 29, count 0 2006.173.12:02:09.98#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.12:02:09.98#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.12:02:09.98#ibcon#*before write, iclass 29, count 0 2006.173.12:02:09.98#ibcon#enter sib2, iclass 29, count 0 2006.173.12:02:09.98#ibcon#flushed, iclass 29, count 0 2006.173.12:02:09.98#ibcon#about to write, iclass 29, count 0 2006.173.12:02:09.98#ibcon#wrote, iclass 29, count 0 2006.173.12:02:09.98#ibcon#about to read 3, iclass 29, count 0 2006.173.12:02:10.02#ibcon#read 3, iclass 29, count 0 2006.173.12:02:10.02#ibcon#about to read 4, iclass 29, count 0 2006.173.12:02:10.02#ibcon#read 4, iclass 29, count 0 2006.173.12:02:10.02#ibcon#about to read 5, iclass 29, count 0 2006.173.12:02:10.02#ibcon#read 5, iclass 29, count 0 2006.173.12:02:10.02#ibcon#about to read 6, iclass 29, count 0 2006.173.12:02:10.02#ibcon#read 6, iclass 29, count 0 2006.173.12:02:10.02#ibcon#end of sib2, iclass 29, count 0 2006.173.12:02:10.02#ibcon#*after write, iclass 29, count 0 2006.173.12:02:10.02#ibcon#*before return 0, iclass 29, count 0 2006.173.12:02:10.02#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.12:02:10.02#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.12:02:10.02#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.12:02:10.02#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.12:02:10.02$vck44/va=3,5 2006.173.12:02:10.02#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.12:02:10.02#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.12:02:10.02#ibcon#ireg 11 cls_cnt 2 2006.173.12:02:10.02#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.12:02:10.08#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.12:02:10.08#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.12:02:10.08#ibcon#enter wrdev, iclass 31, count 2 2006.173.12:02:10.08#ibcon#first serial, iclass 31, count 2 2006.173.12:02:10.08#ibcon#enter sib2, iclass 31, count 2 2006.173.12:02:10.08#ibcon#flushed, iclass 31, count 2 2006.173.12:02:10.08#ibcon#about to write, iclass 31, count 2 2006.173.12:02:10.08#ibcon#wrote, iclass 31, count 2 2006.173.12:02:10.08#ibcon#about to read 3, iclass 31, count 2 2006.173.12:02:10.10#ibcon#read 3, iclass 31, count 2 2006.173.12:02:10.10#ibcon#about to read 4, iclass 31, count 2 2006.173.12:02:10.10#ibcon#read 4, iclass 31, count 2 2006.173.12:02:10.10#ibcon#about to read 5, iclass 31, count 2 2006.173.12:02:10.10#ibcon#read 5, iclass 31, count 2 2006.173.12:02:10.10#ibcon#about to read 6, iclass 31, count 2 2006.173.12:02:10.10#ibcon#read 6, iclass 31, count 2 2006.173.12:02:10.10#ibcon#end of sib2, iclass 31, count 2 2006.173.12:02:10.10#ibcon#*mode == 0, iclass 31, count 2 2006.173.12:02:10.10#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.12:02:10.10#ibcon#[25=AT03-05\r\n] 2006.173.12:02:10.10#ibcon#*before write, iclass 31, count 2 2006.173.12:02:10.10#ibcon#enter sib2, iclass 31, count 2 2006.173.12:02:10.10#ibcon#flushed, iclass 31, count 2 2006.173.12:02:10.10#ibcon#about to write, iclass 31, count 2 2006.173.12:02:10.10#ibcon#wrote, iclass 31, count 2 2006.173.12:02:10.10#ibcon#about to read 3, iclass 31, count 2 2006.173.12:02:10.13#ibcon#read 3, iclass 31, count 2 2006.173.12:02:10.13#ibcon#about to read 4, iclass 31, count 2 2006.173.12:02:10.13#ibcon#read 4, iclass 31, count 2 2006.173.12:02:10.13#ibcon#about to read 5, iclass 31, count 2 2006.173.12:02:10.13#ibcon#read 5, iclass 31, count 2 2006.173.12:02:10.13#ibcon#about to read 6, iclass 31, count 2 2006.173.12:02:10.13#ibcon#read 6, iclass 31, count 2 2006.173.12:02:10.13#ibcon#end of sib2, iclass 31, count 2 2006.173.12:02:10.13#ibcon#*after write, iclass 31, count 2 2006.173.12:02:10.13#ibcon#*before return 0, iclass 31, count 2 2006.173.12:02:10.13#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.12:02:10.13#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.12:02:10.13#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.12:02:10.13#ibcon#ireg 7 cls_cnt 0 2006.173.12:02:10.13#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.12:02:10.25#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.12:02:10.25#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.12:02:10.25#ibcon#enter wrdev, iclass 31, count 0 2006.173.12:02:10.25#ibcon#first serial, iclass 31, count 0 2006.173.12:02:10.25#ibcon#enter sib2, iclass 31, count 0 2006.173.12:02:10.25#ibcon#flushed, iclass 31, count 0 2006.173.12:02:10.25#ibcon#about to write, iclass 31, count 0 2006.173.12:02:10.25#ibcon#wrote, iclass 31, count 0 2006.173.12:02:10.25#ibcon#about to read 3, iclass 31, count 0 2006.173.12:02:10.27#ibcon#read 3, iclass 31, count 0 2006.173.12:02:10.27#ibcon#about to read 4, iclass 31, count 0 2006.173.12:02:10.27#ibcon#read 4, iclass 31, count 0 2006.173.12:02:10.27#ibcon#about to read 5, iclass 31, count 0 2006.173.12:02:10.27#ibcon#read 5, iclass 31, count 0 2006.173.12:02:10.27#ibcon#about to read 6, iclass 31, count 0 2006.173.12:02:10.27#ibcon#read 6, iclass 31, count 0 2006.173.12:02:10.27#ibcon#end of sib2, iclass 31, count 0 2006.173.12:02:10.27#ibcon#*mode == 0, iclass 31, count 0 2006.173.12:02:10.27#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.12:02:10.27#ibcon#[25=USB\r\n] 2006.173.12:02:10.27#ibcon#*before write, iclass 31, count 0 2006.173.12:02:10.27#ibcon#enter sib2, iclass 31, count 0 2006.173.12:02:10.27#ibcon#flushed, iclass 31, count 0 2006.173.12:02:10.27#ibcon#about to write, iclass 31, count 0 2006.173.12:02:10.27#ibcon#wrote, iclass 31, count 0 2006.173.12:02:10.27#ibcon#about to read 3, iclass 31, count 0 2006.173.12:02:10.30#ibcon#read 3, iclass 31, count 0 2006.173.12:02:10.30#ibcon#about to read 4, iclass 31, count 0 2006.173.12:02:10.30#ibcon#read 4, iclass 31, count 0 2006.173.12:02:10.30#ibcon#about to read 5, iclass 31, count 0 2006.173.12:02:10.30#ibcon#read 5, iclass 31, count 0 2006.173.12:02:10.30#ibcon#about to read 6, iclass 31, count 0 2006.173.12:02:10.30#ibcon#read 6, iclass 31, count 0 2006.173.12:02:10.30#ibcon#end of sib2, iclass 31, count 0 2006.173.12:02:10.30#ibcon#*after write, iclass 31, count 0 2006.173.12:02:10.30#ibcon#*before return 0, iclass 31, count 0 2006.173.12:02:10.30#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.12:02:10.30#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.12:02:10.30#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.12:02:10.30#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.12:02:10.30$vck44/valo=4,624.99 2006.173.12:02:10.30#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.12:02:10.30#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.12:02:10.30#ibcon#ireg 17 cls_cnt 0 2006.173.12:02:10.30#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.12:02:10.30#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.12:02:10.30#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.12:02:10.30#ibcon#enter wrdev, iclass 33, count 0 2006.173.12:02:10.30#ibcon#first serial, iclass 33, count 0 2006.173.12:02:10.30#ibcon#enter sib2, iclass 33, count 0 2006.173.12:02:10.30#ibcon#flushed, iclass 33, count 0 2006.173.12:02:10.30#ibcon#about to write, iclass 33, count 0 2006.173.12:02:10.30#ibcon#wrote, iclass 33, count 0 2006.173.12:02:10.30#ibcon#about to read 3, iclass 33, count 0 2006.173.12:02:10.32#ibcon#read 3, iclass 33, count 0 2006.173.12:02:10.32#ibcon#about to read 4, iclass 33, count 0 2006.173.12:02:10.32#ibcon#read 4, iclass 33, count 0 2006.173.12:02:10.32#ibcon#about to read 5, iclass 33, count 0 2006.173.12:02:10.32#ibcon#read 5, iclass 33, count 0 2006.173.12:02:10.32#ibcon#about to read 6, iclass 33, count 0 2006.173.12:02:10.32#ibcon#read 6, iclass 33, count 0 2006.173.12:02:10.32#ibcon#end of sib2, iclass 33, count 0 2006.173.12:02:10.32#ibcon#*mode == 0, iclass 33, count 0 2006.173.12:02:10.32#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.12:02:10.32#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.12:02:10.32#ibcon#*before write, iclass 33, count 0 2006.173.12:02:10.32#ibcon#enter sib2, iclass 33, count 0 2006.173.12:02:10.32#ibcon#flushed, iclass 33, count 0 2006.173.12:02:10.32#ibcon#about to write, iclass 33, count 0 2006.173.12:02:10.32#ibcon#wrote, iclass 33, count 0 2006.173.12:02:10.32#ibcon#about to read 3, iclass 33, count 0 2006.173.12:02:10.36#ibcon#read 3, iclass 33, count 0 2006.173.12:02:10.36#ibcon#about to read 4, iclass 33, count 0 2006.173.12:02:10.36#ibcon#read 4, iclass 33, count 0 2006.173.12:02:10.36#ibcon#about to read 5, iclass 33, count 0 2006.173.12:02:10.36#ibcon#read 5, iclass 33, count 0 2006.173.12:02:10.36#ibcon#about to read 6, iclass 33, count 0 2006.173.12:02:10.36#ibcon#read 6, iclass 33, count 0 2006.173.12:02:10.36#ibcon#end of sib2, iclass 33, count 0 2006.173.12:02:10.36#ibcon#*after write, iclass 33, count 0 2006.173.12:02:10.36#ibcon#*before return 0, iclass 33, count 0 2006.173.12:02:10.36#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.12:02:10.36#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.12:02:10.36#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.12:02:10.36#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.12:02:10.36$vck44/va=4,6 2006.173.12:02:10.36#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.12:02:10.36#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.12:02:10.36#ibcon#ireg 11 cls_cnt 2 2006.173.12:02:10.36#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.12:02:10.42#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.12:02:10.42#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.12:02:10.42#ibcon#enter wrdev, iclass 35, count 2 2006.173.12:02:10.42#ibcon#first serial, iclass 35, count 2 2006.173.12:02:10.42#ibcon#enter sib2, iclass 35, count 2 2006.173.12:02:10.42#ibcon#flushed, iclass 35, count 2 2006.173.12:02:10.42#ibcon#about to write, iclass 35, count 2 2006.173.12:02:10.42#ibcon#wrote, iclass 35, count 2 2006.173.12:02:10.42#ibcon#about to read 3, iclass 35, count 2 2006.173.12:02:10.44#ibcon#read 3, iclass 35, count 2 2006.173.12:02:10.44#ibcon#about to read 4, iclass 35, count 2 2006.173.12:02:10.44#ibcon#read 4, iclass 35, count 2 2006.173.12:02:10.44#ibcon#about to read 5, iclass 35, count 2 2006.173.12:02:10.44#ibcon#read 5, iclass 35, count 2 2006.173.12:02:10.44#ibcon#about to read 6, iclass 35, count 2 2006.173.12:02:10.44#ibcon#read 6, iclass 35, count 2 2006.173.12:02:10.44#ibcon#end of sib2, iclass 35, count 2 2006.173.12:02:10.44#ibcon#*mode == 0, iclass 35, count 2 2006.173.12:02:10.44#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.12:02:10.44#ibcon#[25=AT04-06\r\n] 2006.173.12:02:10.44#ibcon#*before write, iclass 35, count 2 2006.173.12:02:10.44#ibcon#enter sib2, iclass 35, count 2 2006.173.12:02:10.44#ibcon#flushed, iclass 35, count 2 2006.173.12:02:10.44#ibcon#about to write, iclass 35, count 2 2006.173.12:02:10.44#ibcon#wrote, iclass 35, count 2 2006.173.12:02:10.44#ibcon#about to read 3, iclass 35, count 2 2006.173.12:02:10.47#ibcon#read 3, iclass 35, count 2 2006.173.12:02:10.47#ibcon#about to read 4, iclass 35, count 2 2006.173.12:02:10.47#ibcon#read 4, iclass 35, count 2 2006.173.12:02:10.47#ibcon#about to read 5, iclass 35, count 2 2006.173.12:02:10.47#ibcon#read 5, iclass 35, count 2 2006.173.12:02:10.47#ibcon#about to read 6, iclass 35, count 2 2006.173.12:02:10.47#ibcon#read 6, iclass 35, count 2 2006.173.12:02:10.47#ibcon#end of sib2, iclass 35, count 2 2006.173.12:02:10.47#ibcon#*after write, iclass 35, count 2 2006.173.12:02:10.47#ibcon#*before return 0, iclass 35, count 2 2006.173.12:02:10.47#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.12:02:10.47#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.12:02:10.47#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.12:02:10.47#ibcon#ireg 7 cls_cnt 0 2006.173.12:02:10.47#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.12:02:10.59#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.12:02:10.59#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.12:02:10.59#ibcon#enter wrdev, iclass 35, count 0 2006.173.12:02:10.59#ibcon#first serial, iclass 35, count 0 2006.173.12:02:10.59#ibcon#enter sib2, iclass 35, count 0 2006.173.12:02:10.59#ibcon#flushed, iclass 35, count 0 2006.173.12:02:10.59#ibcon#about to write, iclass 35, count 0 2006.173.12:02:10.59#ibcon#wrote, iclass 35, count 0 2006.173.12:02:10.59#ibcon#about to read 3, iclass 35, count 0 2006.173.12:02:10.61#ibcon#read 3, iclass 35, count 0 2006.173.12:02:10.61#ibcon#about to read 4, iclass 35, count 0 2006.173.12:02:10.61#ibcon#read 4, iclass 35, count 0 2006.173.12:02:10.61#ibcon#about to read 5, iclass 35, count 0 2006.173.12:02:10.61#ibcon#read 5, iclass 35, count 0 2006.173.12:02:10.61#ibcon#about to read 6, iclass 35, count 0 2006.173.12:02:10.61#ibcon#read 6, iclass 35, count 0 2006.173.12:02:10.61#ibcon#end of sib2, iclass 35, count 0 2006.173.12:02:10.61#ibcon#*mode == 0, iclass 35, count 0 2006.173.12:02:10.61#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.12:02:10.61#ibcon#[25=USB\r\n] 2006.173.12:02:10.61#ibcon#*before write, iclass 35, count 0 2006.173.12:02:10.61#ibcon#enter sib2, iclass 35, count 0 2006.173.12:02:10.61#ibcon#flushed, iclass 35, count 0 2006.173.12:02:10.61#ibcon#about to write, iclass 35, count 0 2006.173.12:02:10.61#ibcon#wrote, iclass 35, count 0 2006.173.12:02:10.61#ibcon#about to read 3, iclass 35, count 0 2006.173.12:02:10.64#ibcon#read 3, iclass 35, count 0 2006.173.12:02:10.64#ibcon#about to read 4, iclass 35, count 0 2006.173.12:02:10.64#ibcon#read 4, iclass 35, count 0 2006.173.12:02:10.64#ibcon#about to read 5, iclass 35, count 0 2006.173.12:02:10.64#ibcon#read 5, iclass 35, count 0 2006.173.12:02:10.64#ibcon#about to read 6, iclass 35, count 0 2006.173.12:02:10.64#ibcon#read 6, iclass 35, count 0 2006.173.12:02:10.64#ibcon#end of sib2, iclass 35, count 0 2006.173.12:02:10.64#ibcon#*after write, iclass 35, count 0 2006.173.12:02:10.64#ibcon#*before return 0, iclass 35, count 0 2006.173.12:02:10.64#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.12:02:10.64#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.12:02:10.64#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.12:02:10.64#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.12:02:10.64$vck44/valo=5,734.99 2006.173.12:02:10.64#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.12:02:10.64#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.12:02:10.64#ibcon#ireg 17 cls_cnt 0 2006.173.12:02:10.64#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.12:02:10.64#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.12:02:10.64#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.12:02:10.64#ibcon#enter wrdev, iclass 37, count 0 2006.173.12:02:10.64#ibcon#first serial, iclass 37, count 0 2006.173.12:02:10.64#ibcon#enter sib2, iclass 37, count 0 2006.173.12:02:10.64#ibcon#flushed, iclass 37, count 0 2006.173.12:02:10.64#ibcon#about to write, iclass 37, count 0 2006.173.12:02:10.64#ibcon#wrote, iclass 37, count 0 2006.173.12:02:10.64#ibcon#about to read 3, iclass 37, count 0 2006.173.12:02:10.66#ibcon#read 3, iclass 37, count 0 2006.173.12:02:10.66#ibcon#about to read 4, iclass 37, count 0 2006.173.12:02:10.66#ibcon#read 4, iclass 37, count 0 2006.173.12:02:10.66#ibcon#about to read 5, iclass 37, count 0 2006.173.12:02:10.66#ibcon#read 5, iclass 37, count 0 2006.173.12:02:10.66#ibcon#about to read 6, iclass 37, count 0 2006.173.12:02:10.66#ibcon#read 6, iclass 37, count 0 2006.173.12:02:10.66#ibcon#end of sib2, iclass 37, count 0 2006.173.12:02:10.66#ibcon#*mode == 0, iclass 37, count 0 2006.173.12:02:10.66#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.12:02:10.66#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.12:02:10.66#ibcon#*before write, iclass 37, count 0 2006.173.12:02:10.66#ibcon#enter sib2, iclass 37, count 0 2006.173.12:02:10.66#ibcon#flushed, iclass 37, count 0 2006.173.12:02:10.66#ibcon#about to write, iclass 37, count 0 2006.173.12:02:10.66#ibcon#wrote, iclass 37, count 0 2006.173.12:02:10.66#ibcon#about to read 3, iclass 37, count 0 2006.173.12:02:10.70#ibcon#read 3, iclass 37, count 0 2006.173.12:02:10.70#ibcon#about to read 4, iclass 37, count 0 2006.173.12:02:10.70#ibcon#read 4, iclass 37, count 0 2006.173.12:02:10.70#ibcon#about to read 5, iclass 37, count 0 2006.173.12:02:10.70#ibcon#read 5, iclass 37, count 0 2006.173.12:02:10.70#ibcon#about to read 6, iclass 37, count 0 2006.173.12:02:10.70#ibcon#read 6, iclass 37, count 0 2006.173.12:02:10.70#ibcon#end of sib2, iclass 37, count 0 2006.173.12:02:10.70#ibcon#*after write, iclass 37, count 0 2006.173.12:02:10.70#ibcon#*before return 0, iclass 37, count 0 2006.173.12:02:10.70#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.12:02:10.70#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.12:02:10.70#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.12:02:10.70#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.12:02:10.70$vck44/va=5,4 2006.173.12:02:10.70#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.12:02:10.70#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.12:02:10.70#ibcon#ireg 11 cls_cnt 2 2006.173.12:02:10.70#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.12:02:10.76#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.12:02:10.76#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.12:02:10.76#ibcon#enter wrdev, iclass 39, count 2 2006.173.12:02:10.76#ibcon#first serial, iclass 39, count 2 2006.173.12:02:10.76#ibcon#enter sib2, iclass 39, count 2 2006.173.12:02:10.76#ibcon#flushed, iclass 39, count 2 2006.173.12:02:10.76#ibcon#about to write, iclass 39, count 2 2006.173.12:02:10.76#ibcon#wrote, iclass 39, count 2 2006.173.12:02:10.76#ibcon#about to read 3, iclass 39, count 2 2006.173.12:02:10.78#ibcon#read 3, iclass 39, count 2 2006.173.12:02:10.78#ibcon#about to read 4, iclass 39, count 2 2006.173.12:02:10.78#ibcon#read 4, iclass 39, count 2 2006.173.12:02:10.78#ibcon#about to read 5, iclass 39, count 2 2006.173.12:02:10.78#ibcon#read 5, iclass 39, count 2 2006.173.12:02:10.78#ibcon#about to read 6, iclass 39, count 2 2006.173.12:02:10.78#ibcon#read 6, iclass 39, count 2 2006.173.12:02:10.78#ibcon#end of sib2, iclass 39, count 2 2006.173.12:02:10.78#ibcon#*mode == 0, iclass 39, count 2 2006.173.12:02:10.78#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.12:02:10.78#ibcon#[25=AT05-04\r\n] 2006.173.12:02:10.78#ibcon#*before write, iclass 39, count 2 2006.173.12:02:10.78#ibcon#enter sib2, iclass 39, count 2 2006.173.12:02:10.78#ibcon#flushed, iclass 39, count 2 2006.173.12:02:10.78#ibcon#about to write, iclass 39, count 2 2006.173.12:02:10.78#ibcon#wrote, iclass 39, count 2 2006.173.12:02:10.78#ibcon#about to read 3, iclass 39, count 2 2006.173.12:02:10.81#ibcon#read 3, iclass 39, count 2 2006.173.12:02:10.81#ibcon#about to read 4, iclass 39, count 2 2006.173.12:02:10.81#ibcon#read 4, iclass 39, count 2 2006.173.12:02:10.81#ibcon#about to read 5, iclass 39, count 2 2006.173.12:02:10.81#ibcon#read 5, iclass 39, count 2 2006.173.12:02:10.81#ibcon#about to read 6, iclass 39, count 2 2006.173.12:02:10.81#ibcon#read 6, iclass 39, count 2 2006.173.12:02:10.81#ibcon#end of sib2, iclass 39, count 2 2006.173.12:02:10.81#ibcon#*after write, iclass 39, count 2 2006.173.12:02:10.81#ibcon#*before return 0, iclass 39, count 2 2006.173.12:02:10.81#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.12:02:10.81#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.12:02:10.81#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.12:02:10.81#ibcon#ireg 7 cls_cnt 0 2006.173.12:02:10.81#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.12:02:10.93#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.12:02:10.93#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.12:02:10.93#ibcon#enter wrdev, iclass 39, count 0 2006.173.12:02:10.93#ibcon#first serial, iclass 39, count 0 2006.173.12:02:10.93#ibcon#enter sib2, iclass 39, count 0 2006.173.12:02:10.93#ibcon#flushed, iclass 39, count 0 2006.173.12:02:10.93#ibcon#about to write, iclass 39, count 0 2006.173.12:02:10.93#ibcon#wrote, iclass 39, count 0 2006.173.12:02:10.93#ibcon#about to read 3, iclass 39, count 0 2006.173.12:02:10.95#ibcon#read 3, iclass 39, count 0 2006.173.12:02:10.95#ibcon#about to read 4, iclass 39, count 0 2006.173.12:02:10.95#ibcon#read 4, iclass 39, count 0 2006.173.12:02:10.95#ibcon#about to read 5, iclass 39, count 0 2006.173.12:02:10.95#ibcon#read 5, iclass 39, count 0 2006.173.12:02:10.95#ibcon#about to read 6, iclass 39, count 0 2006.173.12:02:10.95#ibcon#read 6, iclass 39, count 0 2006.173.12:02:10.95#ibcon#end of sib2, iclass 39, count 0 2006.173.12:02:10.95#ibcon#*mode == 0, iclass 39, count 0 2006.173.12:02:10.95#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.12:02:10.95#ibcon#[25=USB\r\n] 2006.173.12:02:10.95#ibcon#*before write, iclass 39, count 0 2006.173.12:02:10.95#ibcon#enter sib2, iclass 39, count 0 2006.173.12:02:10.95#ibcon#flushed, iclass 39, count 0 2006.173.12:02:10.95#ibcon#about to write, iclass 39, count 0 2006.173.12:02:10.95#ibcon#wrote, iclass 39, count 0 2006.173.12:02:10.95#ibcon#about to read 3, iclass 39, count 0 2006.173.12:02:10.95#abcon#{5=INTERFACE CLEAR} 2006.173.12:02:10.98#ibcon#read 3, iclass 39, count 0 2006.173.12:02:10.98#ibcon#about to read 4, iclass 39, count 0 2006.173.12:02:10.98#ibcon#read 4, iclass 39, count 0 2006.173.12:02:10.98#ibcon#about to read 5, iclass 39, count 0 2006.173.12:02:10.98#ibcon#read 5, iclass 39, count 0 2006.173.12:02:10.98#ibcon#about to read 6, iclass 39, count 0 2006.173.12:02:10.98#ibcon#read 6, iclass 39, count 0 2006.173.12:02:10.98#ibcon#end of sib2, iclass 39, count 0 2006.173.12:02:10.98#ibcon#*after write, iclass 39, count 0 2006.173.12:02:10.98#ibcon#*before return 0, iclass 39, count 0 2006.173.12:02:10.98#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.12:02:10.98#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.12:02:10.98#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.12:02:10.98#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.12:02:10.98$vck44/valo=6,814.99 2006.173.12:02:10.98#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.12:02:10.98#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.12:02:10.98#ibcon#ireg 17 cls_cnt 0 2006.173.12:02:10.98#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.12:02:10.98#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.12:02:10.98#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.12:02:10.98#ibcon#enter wrdev, iclass 4, count 0 2006.173.12:02:10.98#ibcon#first serial, iclass 4, count 0 2006.173.12:02:10.98#ibcon#enter sib2, iclass 4, count 0 2006.173.12:02:10.98#ibcon#flushed, iclass 4, count 0 2006.173.12:02:10.98#ibcon#about to write, iclass 4, count 0 2006.173.12:02:10.98#ibcon#wrote, iclass 4, count 0 2006.173.12:02:10.98#ibcon#about to read 3, iclass 4, count 0 2006.173.12:02:11.00#ibcon#read 3, iclass 4, count 0 2006.173.12:02:11.00#ibcon#about to read 4, iclass 4, count 0 2006.173.12:02:11.00#ibcon#read 4, iclass 4, count 0 2006.173.12:02:11.00#ibcon#about to read 5, iclass 4, count 0 2006.173.12:02:11.00#ibcon#read 5, iclass 4, count 0 2006.173.12:02:11.00#ibcon#about to read 6, iclass 4, count 0 2006.173.12:02:11.00#ibcon#read 6, iclass 4, count 0 2006.173.12:02:11.00#ibcon#end of sib2, iclass 4, count 0 2006.173.12:02:11.00#ibcon#*mode == 0, iclass 4, count 0 2006.173.12:02:11.00#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.12:02:11.00#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.12:02:11.00#ibcon#*before write, iclass 4, count 0 2006.173.12:02:11.00#ibcon#enter sib2, iclass 4, count 0 2006.173.12:02:11.00#ibcon#flushed, iclass 4, count 0 2006.173.12:02:11.00#ibcon#about to write, iclass 4, count 0 2006.173.12:02:11.00#ibcon#wrote, iclass 4, count 0 2006.173.12:02:11.00#ibcon#about to read 3, iclass 4, count 0 2006.173.12:02:11.01#abcon#[5=S1D000X0/0*\r\n] 2006.173.12:02:11.04#ibcon#read 3, iclass 4, count 0 2006.173.12:02:11.04#ibcon#about to read 4, iclass 4, count 0 2006.173.12:02:11.04#ibcon#read 4, iclass 4, count 0 2006.173.12:02:11.04#ibcon#about to read 5, iclass 4, count 0 2006.173.12:02:11.04#ibcon#read 5, iclass 4, count 0 2006.173.12:02:11.04#ibcon#about to read 6, iclass 4, count 0 2006.173.12:02:11.04#ibcon#read 6, iclass 4, count 0 2006.173.12:02:11.04#ibcon#end of sib2, iclass 4, count 0 2006.173.12:02:11.04#ibcon#*after write, iclass 4, count 0 2006.173.12:02:11.04#ibcon#*before return 0, iclass 4, count 0 2006.173.12:02:11.04#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.12:02:11.04#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.12:02:11.04#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.12:02:11.04#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.12:02:11.04$vck44/va=6,3 2006.173.12:02:11.04#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.173.12:02:11.04#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.173.12:02:11.04#ibcon#ireg 11 cls_cnt 2 2006.173.12:02:11.04#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.12:02:11.10#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.12:02:11.10#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.12:02:11.10#ibcon#enter wrdev, iclass 7, count 2 2006.173.12:02:11.10#ibcon#first serial, iclass 7, count 2 2006.173.12:02:11.10#ibcon#enter sib2, iclass 7, count 2 2006.173.12:02:11.10#ibcon#flushed, iclass 7, count 2 2006.173.12:02:11.10#ibcon#about to write, iclass 7, count 2 2006.173.12:02:11.10#ibcon#wrote, iclass 7, count 2 2006.173.12:02:11.10#ibcon#about to read 3, iclass 7, count 2 2006.173.12:02:11.12#ibcon#read 3, iclass 7, count 2 2006.173.12:02:11.12#ibcon#about to read 4, iclass 7, count 2 2006.173.12:02:11.12#ibcon#read 4, iclass 7, count 2 2006.173.12:02:11.12#ibcon#about to read 5, iclass 7, count 2 2006.173.12:02:11.12#ibcon#read 5, iclass 7, count 2 2006.173.12:02:11.12#ibcon#about to read 6, iclass 7, count 2 2006.173.12:02:11.12#ibcon#read 6, iclass 7, count 2 2006.173.12:02:11.12#ibcon#end of sib2, iclass 7, count 2 2006.173.12:02:11.12#ibcon#*mode == 0, iclass 7, count 2 2006.173.12:02:11.12#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.173.12:02:11.12#ibcon#[25=AT06-03\r\n] 2006.173.12:02:11.12#ibcon#*before write, iclass 7, count 2 2006.173.12:02:11.12#ibcon#enter sib2, iclass 7, count 2 2006.173.12:02:11.12#ibcon#flushed, iclass 7, count 2 2006.173.12:02:11.12#ibcon#about to write, iclass 7, count 2 2006.173.12:02:11.12#ibcon#wrote, iclass 7, count 2 2006.173.12:02:11.12#ibcon#about to read 3, iclass 7, count 2 2006.173.12:02:11.15#ibcon#read 3, iclass 7, count 2 2006.173.12:02:11.15#ibcon#about to read 4, iclass 7, count 2 2006.173.12:02:11.15#ibcon#read 4, iclass 7, count 2 2006.173.12:02:11.15#ibcon#about to read 5, iclass 7, count 2 2006.173.12:02:11.15#ibcon#read 5, iclass 7, count 2 2006.173.12:02:11.15#ibcon#about to read 6, iclass 7, count 2 2006.173.12:02:11.15#ibcon#read 6, iclass 7, count 2 2006.173.12:02:11.15#ibcon#end of sib2, iclass 7, count 2 2006.173.12:02:11.15#ibcon#*after write, iclass 7, count 2 2006.173.12:02:11.15#ibcon#*before return 0, iclass 7, count 2 2006.173.12:02:11.15#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.12:02:11.15#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.173.12:02:11.15#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.173.12:02:11.15#ibcon#ireg 7 cls_cnt 0 2006.173.12:02:11.15#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.12:02:11.27#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.12:02:11.27#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.12:02:11.27#ibcon#enter wrdev, iclass 7, count 0 2006.173.12:02:11.27#ibcon#first serial, iclass 7, count 0 2006.173.12:02:11.27#ibcon#enter sib2, iclass 7, count 0 2006.173.12:02:11.27#ibcon#flushed, iclass 7, count 0 2006.173.12:02:11.27#ibcon#about to write, iclass 7, count 0 2006.173.12:02:11.27#ibcon#wrote, iclass 7, count 0 2006.173.12:02:11.27#ibcon#about to read 3, iclass 7, count 0 2006.173.12:02:11.29#ibcon#read 3, iclass 7, count 0 2006.173.12:02:11.29#ibcon#about to read 4, iclass 7, count 0 2006.173.12:02:11.29#ibcon#read 4, iclass 7, count 0 2006.173.12:02:11.29#ibcon#about to read 5, iclass 7, count 0 2006.173.12:02:11.29#ibcon#read 5, iclass 7, count 0 2006.173.12:02:11.29#ibcon#about to read 6, iclass 7, count 0 2006.173.12:02:11.29#ibcon#read 6, iclass 7, count 0 2006.173.12:02:11.29#ibcon#end of sib2, iclass 7, count 0 2006.173.12:02:11.29#ibcon#*mode == 0, iclass 7, count 0 2006.173.12:02:11.29#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.12:02:11.29#ibcon#[25=USB\r\n] 2006.173.12:02:11.29#ibcon#*before write, iclass 7, count 0 2006.173.12:02:11.29#ibcon#enter sib2, iclass 7, count 0 2006.173.12:02:11.29#ibcon#flushed, iclass 7, count 0 2006.173.12:02:11.29#ibcon#about to write, iclass 7, count 0 2006.173.12:02:11.29#ibcon#wrote, iclass 7, count 0 2006.173.12:02:11.29#ibcon#about to read 3, iclass 7, count 0 2006.173.12:02:11.32#ibcon#read 3, iclass 7, count 0 2006.173.12:02:11.32#ibcon#about to read 4, iclass 7, count 0 2006.173.12:02:11.32#ibcon#read 4, iclass 7, count 0 2006.173.12:02:11.32#ibcon#about to read 5, iclass 7, count 0 2006.173.12:02:11.32#ibcon#read 5, iclass 7, count 0 2006.173.12:02:11.32#ibcon#about to read 6, iclass 7, count 0 2006.173.12:02:11.32#ibcon#read 6, iclass 7, count 0 2006.173.12:02:11.32#ibcon#end of sib2, iclass 7, count 0 2006.173.12:02:11.32#ibcon#*after write, iclass 7, count 0 2006.173.12:02:11.32#ibcon#*before return 0, iclass 7, count 0 2006.173.12:02:11.32#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.12:02:11.32#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.173.12:02:11.32#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.12:02:11.32#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.12:02:11.32$vck44/valo=7,864.99 2006.173.12:02:11.32#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.12:02:11.32#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.12:02:11.32#ibcon#ireg 17 cls_cnt 0 2006.173.12:02:11.32#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.12:02:11.32#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.12:02:11.32#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.12:02:11.32#ibcon#enter wrdev, iclass 11, count 0 2006.173.12:02:11.32#ibcon#first serial, iclass 11, count 0 2006.173.12:02:11.32#ibcon#enter sib2, iclass 11, count 0 2006.173.12:02:11.32#ibcon#flushed, iclass 11, count 0 2006.173.12:02:11.32#ibcon#about to write, iclass 11, count 0 2006.173.12:02:11.32#ibcon#wrote, iclass 11, count 0 2006.173.12:02:11.32#ibcon#about to read 3, iclass 11, count 0 2006.173.12:02:11.34#ibcon#read 3, iclass 11, count 0 2006.173.12:02:11.34#ibcon#about to read 4, iclass 11, count 0 2006.173.12:02:11.34#ibcon#read 4, iclass 11, count 0 2006.173.12:02:11.34#ibcon#about to read 5, iclass 11, count 0 2006.173.12:02:11.34#ibcon#read 5, iclass 11, count 0 2006.173.12:02:11.34#ibcon#about to read 6, iclass 11, count 0 2006.173.12:02:11.34#ibcon#read 6, iclass 11, count 0 2006.173.12:02:11.34#ibcon#end of sib2, iclass 11, count 0 2006.173.12:02:11.34#ibcon#*mode == 0, iclass 11, count 0 2006.173.12:02:11.34#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.12:02:11.34#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.12:02:11.34#ibcon#*before write, iclass 11, count 0 2006.173.12:02:11.34#ibcon#enter sib2, iclass 11, count 0 2006.173.12:02:11.34#ibcon#flushed, iclass 11, count 0 2006.173.12:02:11.34#ibcon#about to write, iclass 11, count 0 2006.173.12:02:11.34#ibcon#wrote, iclass 11, count 0 2006.173.12:02:11.34#ibcon#about to read 3, iclass 11, count 0 2006.173.12:02:11.38#ibcon#read 3, iclass 11, count 0 2006.173.12:02:11.38#ibcon#about to read 4, iclass 11, count 0 2006.173.12:02:11.38#ibcon#read 4, iclass 11, count 0 2006.173.12:02:11.38#ibcon#about to read 5, iclass 11, count 0 2006.173.12:02:11.38#ibcon#read 5, iclass 11, count 0 2006.173.12:02:11.38#ibcon#about to read 6, iclass 11, count 0 2006.173.12:02:11.38#ibcon#read 6, iclass 11, count 0 2006.173.12:02:11.38#ibcon#end of sib2, iclass 11, count 0 2006.173.12:02:11.38#ibcon#*after write, iclass 11, count 0 2006.173.12:02:11.38#ibcon#*before return 0, iclass 11, count 0 2006.173.12:02:11.38#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.12:02:11.38#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.12:02:11.38#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.12:02:11.38#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.12:02:11.38$vck44/va=7,4 2006.173.12:02:11.38#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.173.12:02:11.38#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.173.12:02:11.38#ibcon#ireg 11 cls_cnt 2 2006.173.12:02:11.38#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.12:02:11.44#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.12:02:11.44#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.12:02:11.44#ibcon#enter wrdev, iclass 13, count 2 2006.173.12:02:11.44#ibcon#first serial, iclass 13, count 2 2006.173.12:02:11.44#ibcon#enter sib2, iclass 13, count 2 2006.173.12:02:11.44#ibcon#flushed, iclass 13, count 2 2006.173.12:02:11.44#ibcon#about to write, iclass 13, count 2 2006.173.12:02:11.44#ibcon#wrote, iclass 13, count 2 2006.173.12:02:11.44#ibcon#about to read 3, iclass 13, count 2 2006.173.12:02:11.46#ibcon#read 3, iclass 13, count 2 2006.173.12:02:11.46#ibcon#about to read 4, iclass 13, count 2 2006.173.12:02:11.46#ibcon#read 4, iclass 13, count 2 2006.173.12:02:11.46#ibcon#about to read 5, iclass 13, count 2 2006.173.12:02:11.46#ibcon#read 5, iclass 13, count 2 2006.173.12:02:11.46#ibcon#about to read 6, iclass 13, count 2 2006.173.12:02:11.46#ibcon#read 6, iclass 13, count 2 2006.173.12:02:11.46#ibcon#end of sib2, iclass 13, count 2 2006.173.12:02:11.46#ibcon#*mode == 0, iclass 13, count 2 2006.173.12:02:11.46#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.173.12:02:11.46#ibcon#[25=AT07-04\r\n] 2006.173.12:02:11.46#ibcon#*before write, iclass 13, count 2 2006.173.12:02:11.46#ibcon#enter sib2, iclass 13, count 2 2006.173.12:02:11.46#ibcon#flushed, iclass 13, count 2 2006.173.12:02:11.46#ibcon#about to write, iclass 13, count 2 2006.173.12:02:11.46#ibcon#wrote, iclass 13, count 2 2006.173.12:02:11.46#ibcon#about to read 3, iclass 13, count 2 2006.173.12:02:11.49#ibcon#read 3, iclass 13, count 2 2006.173.12:02:11.49#ibcon#about to read 4, iclass 13, count 2 2006.173.12:02:11.49#ibcon#read 4, iclass 13, count 2 2006.173.12:02:11.49#ibcon#about to read 5, iclass 13, count 2 2006.173.12:02:11.49#ibcon#read 5, iclass 13, count 2 2006.173.12:02:11.49#ibcon#about to read 6, iclass 13, count 2 2006.173.12:02:11.49#ibcon#read 6, iclass 13, count 2 2006.173.12:02:11.49#ibcon#end of sib2, iclass 13, count 2 2006.173.12:02:11.49#ibcon#*after write, iclass 13, count 2 2006.173.12:02:11.49#ibcon#*before return 0, iclass 13, count 2 2006.173.12:02:11.49#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.12:02:11.49#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.173.12:02:11.49#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.173.12:02:11.49#ibcon#ireg 7 cls_cnt 0 2006.173.12:02:11.49#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.12:02:11.61#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.12:02:11.61#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.12:02:11.61#ibcon#enter wrdev, iclass 13, count 0 2006.173.12:02:11.61#ibcon#first serial, iclass 13, count 0 2006.173.12:02:11.61#ibcon#enter sib2, iclass 13, count 0 2006.173.12:02:11.61#ibcon#flushed, iclass 13, count 0 2006.173.12:02:11.61#ibcon#about to write, iclass 13, count 0 2006.173.12:02:11.61#ibcon#wrote, iclass 13, count 0 2006.173.12:02:11.61#ibcon#about to read 3, iclass 13, count 0 2006.173.12:02:11.63#ibcon#read 3, iclass 13, count 0 2006.173.12:02:11.63#ibcon#about to read 4, iclass 13, count 0 2006.173.12:02:11.63#ibcon#read 4, iclass 13, count 0 2006.173.12:02:11.63#ibcon#about to read 5, iclass 13, count 0 2006.173.12:02:11.63#ibcon#read 5, iclass 13, count 0 2006.173.12:02:11.63#ibcon#about to read 6, iclass 13, count 0 2006.173.12:02:11.63#ibcon#read 6, iclass 13, count 0 2006.173.12:02:11.63#ibcon#end of sib2, iclass 13, count 0 2006.173.12:02:11.63#ibcon#*mode == 0, iclass 13, count 0 2006.173.12:02:11.63#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.12:02:11.63#ibcon#[25=USB\r\n] 2006.173.12:02:11.63#ibcon#*before write, iclass 13, count 0 2006.173.12:02:11.63#ibcon#enter sib2, iclass 13, count 0 2006.173.12:02:11.63#ibcon#flushed, iclass 13, count 0 2006.173.12:02:11.63#ibcon#about to write, iclass 13, count 0 2006.173.12:02:11.63#ibcon#wrote, iclass 13, count 0 2006.173.12:02:11.63#ibcon#about to read 3, iclass 13, count 0 2006.173.12:02:11.66#ibcon#read 3, iclass 13, count 0 2006.173.12:02:11.66#ibcon#about to read 4, iclass 13, count 0 2006.173.12:02:11.66#ibcon#read 4, iclass 13, count 0 2006.173.12:02:11.66#ibcon#about to read 5, iclass 13, count 0 2006.173.12:02:11.66#ibcon#read 5, iclass 13, count 0 2006.173.12:02:11.66#ibcon#about to read 6, iclass 13, count 0 2006.173.12:02:11.66#ibcon#read 6, iclass 13, count 0 2006.173.12:02:11.66#ibcon#end of sib2, iclass 13, count 0 2006.173.12:02:11.66#ibcon#*after write, iclass 13, count 0 2006.173.12:02:11.66#ibcon#*before return 0, iclass 13, count 0 2006.173.12:02:11.66#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.12:02:11.66#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.173.12:02:11.66#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.12:02:11.66#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.12:02:11.66$vck44/valo=8,884.99 2006.173.12:02:11.66#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.12:02:11.66#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.12:02:11.66#ibcon#ireg 17 cls_cnt 0 2006.173.12:02:11.66#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.12:02:11.66#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.12:02:11.66#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.12:02:11.66#ibcon#enter wrdev, iclass 15, count 0 2006.173.12:02:11.66#ibcon#first serial, iclass 15, count 0 2006.173.12:02:11.66#ibcon#enter sib2, iclass 15, count 0 2006.173.12:02:11.66#ibcon#flushed, iclass 15, count 0 2006.173.12:02:11.66#ibcon#about to write, iclass 15, count 0 2006.173.12:02:11.66#ibcon#wrote, iclass 15, count 0 2006.173.12:02:11.66#ibcon#about to read 3, iclass 15, count 0 2006.173.12:02:11.68#ibcon#read 3, iclass 15, count 0 2006.173.12:02:11.68#ibcon#about to read 4, iclass 15, count 0 2006.173.12:02:11.68#ibcon#read 4, iclass 15, count 0 2006.173.12:02:11.68#ibcon#about to read 5, iclass 15, count 0 2006.173.12:02:11.68#ibcon#read 5, iclass 15, count 0 2006.173.12:02:11.68#ibcon#about to read 6, iclass 15, count 0 2006.173.12:02:11.68#ibcon#read 6, iclass 15, count 0 2006.173.12:02:11.68#ibcon#end of sib2, iclass 15, count 0 2006.173.12:02:11.68#ibcon#*mode == 0, iclass 15, count 0 2006.173.12:02:11.68#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.12:02:11.68#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.12:02:11.68#ibcon#*before write, iclass 15, count 0 2006.173.12:02:11.68#ibcon#enter sib2, iclass 15, count 0 2006.173.12:02:11.68#ibcon#flushed, iclass 15, count 0 2006.173.12:02:11.68#ibcon#about to write, iclass 15, count 0 2006.173.12:02:11.68#ibcon#wrote, iclass 15, count 0 2006.173.12:02:11.68#ibcon#about to read 3, iclass 15, count 0 2006.173.12:02:11.72#ibcon#read 3, iclass 15, count 0 2006.173.12:02:11.72#ibcon#about to read 4, iclass 15, count 0 2006.173.12:02:11.72#ibcon#read 4, iclass 15, count 0 2006.173.12:02:11.72#ibcon#about to read 5, iclass 15, count 0 2006.173.12:02:11.72#ibcon#read 5, iclass 15, count 0 2006.173.12:02:11.72#ibcon#about to read 6, iclass 15, count 0 2006.173.12:02:11.72#ibcon#read 6, iclass 15, count 0 2006.173.12:02:11.72#ibcon#end of sib2, iclass 15, count 0 2006.173.12:02:11.72#ibcon#*after write, iclass 15, count 0 2006.173.12:02:11.72#ibcon#*before return 0, iclass 15, count 0 2006.173.12:02:11.72#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.12:02:11.72#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.12:02:11.72#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.12:02:11.72#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.12:02:11.72$vck44/va=8,4 2006.173.12:02:11.72#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.12:02:11.72#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.12:02:11.72#ibcon#ireg 11 cls_cnt 2 2006.173.12:02:11.72#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.12:02:11.78#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.12:02:11.78#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.12:02:11.78#ibcon#enter wrdev, iclass 17, count 2 2006.173.12:02:11.78#ibcon#first serial, iclass 17, count 2 2006.173.12:02:11.78#ibcon#enter sib2, iclass 17, count 2 2006.173.12:02:11.78#ibcon#flushed, iclass 17, count 2 2006.173.12:02:11.78#ibcon#about to write, iclass 17, count 2 2006.173.12:02:11.78#ibcon#wrote, iclass 17, count 2 2006.173.12:02:11.78#ibcon#about to read 3, iclass 17, count 2 2006.173.12:02:11.80#ibcon#read 3, iclass 17, count 2 2006.173.12:02:11.80#ibcon#about to read 4, iclass 17, count 2 2006.173.12:02:11.80#ibcon#read 4, iclass 17, count 2 2006.173.12:02:11.80#ibcon#about to read 5, iclass 17, count 2 2006.173.12:02:11.80#ibcon#read 5, iclass 17, count 2 2006.173.12:02:11.80#ibcon#about to read 6, iclass 17, count 2 2006.173.12:02:11.80#ibcon#read 6, iclass 17, count 2 2006.173.12:02:11.80#ibcon#end of sib2, iclass 17, count 2 2006.173.12:02:11.80#ibcon#*mode == 0, iclass 17, count 2 2006.173.12:02:11.80#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.12:02:11.80#ibcon#[25=AT08-04\r\n] 2006.173.12:02:11.80#ibcon#*before write, iclass 17, count 2 2006.173.12:02:11.80#ibcon#enter sib2, iclass 17, count 2 2006.173.12:02:11.80#ibcon#flushed, iclass 17, count 2 2006.173.12:02:11.80#ibcon#about to write, iclass 17, count 2 2006.173.12:02:11.80#ibcon#wrote, iclass 17, count 2 2006.173.12:02:11.80#ibcon#about to read 3, iclass 17, count 2 2006.173.12:02:11.83#ibcon#read 3, iclass 17, count 2 2006.173.12:02:11.83#ibcon#about to read 4, iclass 17, count 2 2006.173.12:02:11.83#ibcon#read 4, iclass 17, count 2 2006.173.12:02:11.83#ibcon#about to read 5, iclass 17, count 2 2006.173.12:02:11.83#ibcon#read 5, iclass 17, count 2 2006.173.12:02:11.83#ibcon#about to read 6, iclass 17, count 2 2006.173.12:02:11.83#ibcon#read 6, iclass 17, count 2 2006.173.12:02:11.83#ibcon#end of sib2, iclass 17, count 2 2006.173.12:02:11.83#ibcon#*after write, iclass 17, count 2 2006.173.12:02:11.83#ibcon#*before return 0, iclass 17, count 2 2006.173.12:02:11.83#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.12:02:11.83#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.12:02:11.83#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.12:02:11.83#ibcon#ireg 7 cls_cnt 0 2006.173.12:02:11.83#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.12:02:11.95#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.12:02:11.95#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.12:02:11.95#ibcon#enter wrdev, iclass 17, count 0 2006.173.12:02:11.95#ibcon#first serial, iclass 17, count 0 2006.173.12:02:11.95#ibcon#enter sib2, iclass 17, count 0 2006.173.12:02:11.95#ibcon#flushed, iclass 17, count 0 2006.173.12:02:11.95#ibcon#about to write, iclass 17, count 0 2006.173.12:02:11.95#ibcon#wrote, iclass 17, count 0 2006.173.12:02:11.95#ibcon#about to read 3, iclass 17, count 0 2006.173.12:02:11.97#ibcon#read 3, iclass 17, count 0 2006.173.12:02:11.97#ibcon#about to read 4, iclass 17, count 0 2006.173.12:02:11.97#ibcon#read 4, iclass 17, count 0 2006.173.12:02:11.97#ibcon#about to read 5, iclass 17, count 0 2006.173.12:02:11.97#ibcon#read 5, iclass 17, count 0 2006.173.12:02:11.97#ibcon#about to read 6, iclass 17, count 0 2006.173.12:02:11.97#ibcon#read 6, iclass 17, count 0 2006.173.12:02:11.97#ibcon#end of sib2, iclass 17, count 0 2006.173.12:02:11.97#ibcon#*mode == 0, iclass 17, count 0 2006.173.12:02:11.97#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.12:02:11.97#ibcon#[25=USB\r\n] 2006.173.12:02:11.97#ibcon#*before write, iclass 17, count 0 2006.173.12:02:11.97#ibcon#enter sib2, iclass 17, count 0 2006.173.12:02:11.97#ibcon#flushed, iclass 17, count 0 2006.173.12:02:11.97#ibcon#about to write, iclass 17, count 0 2006.173.12:02:11.97#ibcon#wrote, iclass 17, count 0 2006.173.12:02:11.97#ibcon#about to read 3, iclass 17, count 0 2006.173.12:02:12.00#ibcon#read 3, iclass 17, count 0 2006.173.12:02:12.00#ibcon#about to read 4, iclass 17, count 0 2006.173.12:02:12.00#ibcon#read 4, iclass 17, count 0 2006.173.12:02:12.00#ibcon#about to read 5, iclass 17, count 0 2006.173.12:02:12.00#ibcon#read 5, iclass 17, count 0 2006.173.12:02:12.00#ibcon#about to read 6, iclass 17, count 0 2006.173.12:02:12.00#ibcon#read 6, iclass 17, count 0 2006.173.12:02:12.00#ibcon#end of sib2, iclass 17, count 0 2006.173.12:02:12.00#ibcon#*after write, iclass 17, count 0 2006.173.12:02:12.00#ibcon#*before return 0, iclass 17, count 0 2006.173.12:02:12.00#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.12:02:12.00#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.12:02:12.00#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.12:02:12.00#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.12:02:12.00$vck44/vblo=1,629.99 2006.173.12:02:12.00#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.12:02:12.00#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.12:02:12.00#ibcon#ireg 17 cls_cnt 0 2006.173.12:02:12.00#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.12:02:12.00#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.12:02:12.00#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.12:02:12.00#ibcon#enter wrdev, iclass 19, count 0 2006.173.12:02:12.00#ibcon#first serial, iclass 19, count 0 2006.173.12:02:12.00#ibcon#enter sib2, iclass 19, count 0 2006.173.12:02:12.00#ibcon#flushed, iclass 19, count 0 2006.173.12:02:12.00#ibcon#about to write, iclass 19, count 0 2006.173.12:02:12.00#ibcon#wrote, iclass 19, count 0 2006.173.12:02:12.00#ibcon#about to read 3, iclass 19, count 0 2006.173.12:02:12.02#ibcon#read 3, iclass 19, count 0 2006.173.12:02:12.02#ibcon#about to read 4, iclass 19, count 0 2006.173.12:02:12.02#ibcon#read 4, iclass 19, count 0 2006.173.12:02:12.02#ibcon#about to read 5, iclass 19, count 0 2006.173.12:02:12.02#ibcon#read 5, iclass 19, count 0 2006.173.12:02:12.02#ibcon#about to read 6, iclass 19, count 0 2006.173.12:02:12.02#ibcon#read 6, iclass 19, count 0 2006.173.12:02:12.02#ibcon#end of sib2, iclass 19, count 0 2006.173.12:02:12.02#ibcon#*mode == 0, iclass 19, count 0 2006.173.12:02:12.02#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.12:02:12.02#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.12:02:12.02#ibcon#*before write, iclass 19, count 0 2006.173.12:02:12.02#ibcon#enter sib2, iclass 19, count 0 2006.173.12:02:12.02#ibcon#flushed, iclass 19, count 0 2006.173.12:02:12.02#ibcon#about to write, iclass 19, count 0 2006.173.12:02:12.02#ibcon#wrote, iclass 19, count 0 2006.173.12:02:12.02#ibcon#about to read 3, iclass 19, count 0 2006.173.12:02:12.06#ibcon#read 3, iclass 19, count 0 2006.173.12:02:12.06#ibcon#about to read 4, iclass 19, count 0 2006.173.12:02:12.06#ibcon#read 4, iclass 19, count 0 2006.173.12:02:12.06#ibcon#about to read 5, iclass 19, count 0 2006.173.12:02:12.06#ibcon#read 5, iclass 19, count 0 2006.173.12:02:12.06#ibcon#about to read 6, iclass 19, count 0 2006.173.12:02:12.06#ibcon#read 6, iclass 19, count 0 2006.173.12:02:12.06#ibcon#end of sib2, iclass 19, count 0 2006.173.12:02:12.06#ibcon#*after write, iclass 19, count 0 2006.173.12:02:12.06#ibcon#*before return 0, iclass 19, count 0 2006.173.12:02:12.06#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.12:02:12.06#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.12:02:12.06#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.12:02:12.06#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.12:02:12.06$vck44/vb=1,4 2006.173.12:02:12.06#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.12:02:12.06#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.12:02:12.06#ibcon#ireg 11 cls_cnt 2 2006.173.12:02:12.06#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.12:02:12.06#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.12:02:12.06#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.12:02:12.06#ibcon#enter wrdev, iclass 21, count 2 2006.173.12:02:12.06#ibcon#first serial, iclass 21, count 2 2006.173.12:02:12.06#ibcon#enter sib2, iclass 21, count 2 2006.173.12:02:12.06#ibcon#flushed, iclass 21, count 2 2006.173.12:02:12.06#ibcon#about to write, iclass 21, count 2 2006.173.12:02:12.06#ibcon#wrote, iclass 21, count 2 2006.173.12:02:12.06#ibcon#about to read 3, iclass 21, count 2 2006.173.12:02:12.08#ibcon#read 3, iclass 21, count 2 2006.173.12:02:12.08#ibcon#about to read 4, iclass 21, count 2 2006.173.12:02:12.08#ibcon#read 4, iclass 21, count 2 2006.173.12:02:12.08#ibcon#about to read 5, iclass 21, count 2 2006.173.12:02:12.08#ibcon#read 5, iclass 21, count 2 2006.173.12:02:12.08#ibcon#about to read 6, iclass 21, count 2 2006.173.12:02:12.08#ibcon#read 6, iclass 21, count 2 2006.173.12:02:12.08#ibcon#end of sib2, iclass 21, count 2 2006.173.12:02:12.08#ibcon#*mode == 0, iclass 21, count 2 2006.173.12:02:12.08#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.12:02:12.08#ibcon#[27=AT01-04\r\n] 2006.173.12:02:12.08#ibcon#*before write, iclass 21, count 2 2006.173.12:02:12.08#ibcon#enter sib2, iclass 21, count 2 2006.173.12:02:12.08#ibcon#flushed, iclass 21, count 2 2006.173.12:02:12.08#ibcon#about to write, iclass 21, count 2 2006.173.12:02:12.08#ibcon#wrote, iclass 21, count 2 2006.173.12:02:12.08#ibcon#about to read 3, iclass 21, count 2 2006.173.12:02:12.11#ibcon#read 3, iclass 21, count 2 2006.173.12:02:12.11#ibcon#about to read 4, iclass 21, count 2 2006.173.12:02:12.11#ibcon#read 4, iclass 21, count 2 2006.173.12:02:12.11#ibcon#about to read 5, iclass 21, count 2 2006.173.12:02:12.11#ibcon#read 5, iclass 21, count 2 2006.173.12:02:12.11#ibcon#about to read 6, iclass 21, count 2 2006.173.12:02:12.11#ibcon#read 6, iclass 21, count 2 2006.173.12:02:12.11#ibcon#end of sib2, iclass 21, count 2 2006.173.12:02:12.11#ibcon#*after write, iclass 21, count 2 2006.173.12:02:12.11#ibcon#*before return 0, iclass 21, count 2 2006.173.12:02:12.11#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.12:02:12.11#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.12:02:12.11#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.12:02:12.11#ibcon#ireg 7 cls_cnt 0 2006.173.12:02:12.11#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.12:02:12.23#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.12:02:12.23#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.12:02:12.23#ibcon#enter wrdev, iclass 21, count 0 2006.173.12:02:12.23#ibcon#first serial, iclass 21, count 0 2006.173.12:02:12.23#ibcon#enter sib2, iclass 21, count 0 2006.173.12:02:12.23#ibcon#flushed, iclass 21, count 0 2006.173.12:02:12.23#ibcon#about to write, iclass 21, count 0 2006.173.12:02:12.23#ibcon#wrote, iclass 21, count 0 2006.173.12:02:12.23#ibcon#about to read 3, iclass 21, count 0 2006.173.12:02:12.25#ibcon#read 3, iclass 21, count 0 2006.173.12:02:12.25#ibcon#about to read 4, iclass 21, count 0 2006.173.12:02:12.25#ibcon#read 4, iclass 21, count 0 2006.173.12:02:12.25#ibcon#about to read 5, iclass 21, count 0 2006.173.12:02:12.25#ibcon#read 5, iclass 21, count 0 2006.173.12:02:12.25#ibcon#about to read 6, iclass 21, count 0 2006.173.12:02:12.25#ibcon#read 6, iclass 21, count 0 2006.173.12:02:12.25#ibcon#end of sib2, iclass 21, count 0 2006.173.12:02:12.25#ibcon#*mode == 0, iclass 21, count 0 2006.173.12:02:12.25#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.12:02:12.25#ibcon#[27=USB\r\n] 2006.173.12:02:12.25#ibcon#*before write, iclass 21, count 0 2006.173.12:02:12.25#ibcon#enter sib2, iclass 21, count 0 2006.173.12:02:12.25#ibcon#flushed, iclass 21, count 0 2006.173.12:02:12.25#ibcon#about to write, iclass 21, count 0 2006.173.12:02:12.25#ibcon#wrote, iclass 21, count 0 2006.173.12:02:12.25#ibcon#about to read 3, iclass 21, count 0 2006.173.12:02:12.28#ibcon#read 3, iclass 21, count 0 2006.173.12:02:12.28#ibcon#about to read 4, iclass 21, count 0 2006.173.12:02:12.28#ibcon#read 4, iclass 21, count 0 2006.173.12:02:12.28#ibcon#about to read 5, iclass 21, count 0 2006.173.12:02:12.28#ibcon#read 5, iclass 21, count 0 2006.173.12:02:12.28#ibcon#about to read 6, iclass 21, count 0 2006.173.12:02:12.28#ibcon#read 6, iclass 21, count 0 2006.173.12:02:12.28#ibcon#end of sib2, iclass 21, count 0 2006.173.12:02:12.28#ibcon#*after write, iclass 21, count 0 2006.173.12:02:12.28#ibcon#*before return 0, iclass 21, count 0 2006.173.12:02:12.28#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.12:02:12.28#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.12:02:12.28#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.12:02:12.28#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.12:02:12.28$vck44/vblo=2,634.99 2006.173.12:02:12.28#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.12:02:12.28#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.12:02:12.28#ibcon#ireg 17 cls_cnt 0 2006.173.12:02:12.28#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.12:02:12.28#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.12:02:12.28#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.12:02:12.28#ibcon#enter wrdev, iclass 23, count 0 2006.173.12:02:12.28#ibcon#first serial, iclass 23, count 0 2006.173.12:02:12.28#ibcon#enter sib2, iclass 23, count 0 2006.173.12:02:12.28#ibcon#flushed, iclass 23, count 0 2006.173.12:02:12.28#ibcon#about to write, iclass 23, count 0 2006.173.12:02:12.28#ibcon#wrote, iclass 23, count 0 2006.173.12:02:12.28#ibcon#about to read 3, iclass 23, count 0 2006.173.12:02:12.30#ibcon#read 3, iclass 23, count 0 2006.173.12:02:12.30#ibcon#about to read 4, iclass 23, count 0 2006.173.12:02:12.30#ibcon#read 4, iclass 23, count 0 2006.173.12:02:12.30#ibcon#about to read 5, iclass 23, count 0 2006.173.12:02:12.30#ibcon#read 5, iclass 23, count 0 2006.173.12:02:12.30#ibcon#about to read 6, iclass 23, count 0 2006.173.12:02:12.30#ibcon#read 6, iclass 23, count 0 2006.173.12:02:12.30#ibcon#end of sib2, iclass 23, count 0 2006.173.12:02:12.30#ibcon#*mode == 0, iclass 23, count 0 2006.173.12:02:12.30#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.12:02:12.30#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.12:02:12.30#ibcon#*before write, iclass 23, count 0 2006.173.12:02:12.30#ibcon#enter sib2, iclass 23, count 0 2006.173.12:02:12.30#ibcon#flushed, iclass 23, count 0 2006.173.12:02:12.30#ibcon#about to write, iclass 23, count 0 2006.173.12:02:12.30#ibcon#wrote, iclass 23, count 0 2006.173.12:02:12.30#ibcon#about to read 3, iclass 23, count 0 2006.173.12:02:12.34#ibcon#read 3, iclass 23, count 0 2006.173.12:02:12.34#ibcon#about to read 4, iclass 23, count 0 2006.173.12:02:12.34#ibcon#read 4, iclass 23, count 0 2006.173.12:02:12.34#ibcon#about to read 5, iclass 23, count 0 2006.173.12:02:12.34#ibcon#read 5, iclass 23, count 0 2006.173.12:02:12.34#ibcon#about to read 6, iclass 23, count 0 2006.173.12:02:12.34#ibcon#read 6, iclass 23, count 0 2006.173.12:02:12.34#ibcon#end of sib2, iclass 23, count 0 2006.173.12:02:12.34#ibcon#*after write, iclass 23, count 0 2006.173.12:02:12.34#ibcon#*before return 0, iclass 23, count 0 2006.173.12:02:12.34#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.12:02:12.34#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.12:02:12.34#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.12:02:12.34#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.12:02:12.34$vck44/vb=2,4 2006.173.12:02:12.34#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.12:02:12.34#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.12:02:12.34#ibcon#ireg 11 cls_cnt 2 2006.173.12:02:12.34#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.12:02:12.40#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.12:02:12.40#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.12:02:12.40#ibcon#enter wrdev, iclass 25, count 2 2006.173.12:02:12.40#ibcon#first serial, iclass 25, count 2 2006.173.12:02:12.40#ibcon#enter sib2, iclass 25, count 2 2006.173.12:02:12.40#ibcon#flushed, iclass 25, count 2 2006.173.12:02:12.40#ibcon#about to write, iclass 25, count 2 2006.173.12:02:12.40#ibcon#wrote, iclass 25, count 2 2006.173.12:02:12.40#ibcon#about to read 3, iclass 25, count 2 2006.173.12:02:12.42#ibcon#read 3, iclass 25, count 2 2006.173.12:02:12.42#ibcon#about to read 4, iclass 25, count 2 2006.173.12:02:12.42#ibcon#read 4, iclass 25, count 2 2006.173.12:02:12.42#ibcon#about to read 5, iclass 25, count 2 2006.173.12:02:12.42#ibcon#read 5, iclass 25, count 2 2006.173.12:02:12.42#ibcon#about to read 6, iclass 25, count 2 2006.173.12:02:12.42#ibcon#read 6, iclass 25, count 2 2006.173.12:02:12.42#ibcon#end of sib2, iclass 25, count 2 2006.173.12:02:12.42#ibcon#*mode == 0, iclass 25, count 2 2006.173.12:02:12.42#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.12:02:12.42#ibcon#[27=AT02-04\r\n] 2006.173.12:02:12.42#ibcon#*before write, iclass 25, count 2 2006.173.12:02:12.42#ibcon#enter sib2, iclass 25, count 2 2006.173.12:02:12.42#ibcon#flushed, iclass 25, count 2 2006.173.12:02:12.42#ibcon#about to write, iclass 25, count 2 2006.173.12:02:12.42#ibcon#wrote, iclass 25, count 2 2006.173.12:02:12.42#ibcon#about to read 3, iclass 25, count 2 2006.173.12:02:12.45#ibcon#read 3, iclass 25, count 2 2006.173.12:02:12.45#ibcon#about to read 4, iclass 25, count 2 2006.173.12:02:12.45#ibcon#read 4, iclass 25, count 2 2006.173.12:02:12.45#ibcon#about to read 5, iclass 25, count 2 2006.173.12:02:12.45#ibcon#read 5, iclass 25, count 2 2006.173.12:02:12.45#ibcon#about to read 6, iclass 25, count 2 2006.173.12:02:12.45#ibcon#read 6, iclass 25, count 2 2006.173.12:02:12.45#ibcon#end of sib2, iclass 25, count 2 2006.173.12:02:12.45#ibcon#*after write, iclass 25, count 2 2006.173.12:02:12.45#ibcon#*before return 0, iclass 25, count 2 2006.173.12:02:12.45#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.12:02:12.45#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.12:02:12.45#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.12:02:12.45#ibcon#ireg 7 cls_cnt 0 2006.173.12:02:12.45#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.12:02:12.57#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.12:02:12.57#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.12:02:12.57#ibcon#enter wrdev, iclass 25, count 0 2006.173.12:02:12.57#ibcon#first serial, iclass 25, count 0 2006.173.12:02:12.57#ibcon#enter sib2, iclass 25, count 0 2006.173.12:02:12.57#ibcon#flushed, iclass 25, count 0 2006.173.12:02:12.57#ibcon#about to write, iclass 25, count 0 2006.173.12:02:12.57#ibcon#wrote, iclass 25, count 0 2006.173.12:02:12.57#ibcon#about to read 3, iclass 25, count 0 2006.173.12:02:12.59#ibcon#read 3, iclass 25, count 0 2006.173.12:02:12.59#ibcon#about to read 4, iclass 25, count 0 2006.173.12:02:12.59#ibcon#read 4, iclass 25, count 0 2006.173.12:02:12.59#ibcon#about to read 5, iclass 25, count 0 2006.173.12:02:12.59#ibcon#read 5, iclass 25, count 0 2006.173.12:02:12.59#ibcon#about to read 6, iclass 25, count 0 2006.173.12:02:12.59#ibcon#read 6, iclass 25, count 0 2006.173.12:02:12.59#ibcon#end of sib2, iclass 25, count 0 2006.173.12:02:12.59#ibcon#*mode == 0, iclass 25, count 0 2006.173.12:02:12.59#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.12:02:12.59#ibcon#[27=USB\r\n] 2006.173.12:02:12.59#ibcon#*before write, iclass 25, count 0 2006.173.12:02:12.59#ibcon#enter sib2, iclass 25, count 0 2006.173.12:02:12.59#ibcon#flushed, iclass 25, count 0 2006.173.12:02:12.59#ibcon#about to write, iclass 25, count 0 2006.173.12:02:12.59#ibcon#wrote, iclass 25, count 0 2006.173.12:02:12.59#ibcon#about to read 3, iclass 25, count 0 2006.173.12:02:12.62#ibcon#read 3, iclass 25, count 0 2006.173.12:02:12.62#ibcon#about to read 4, iclass 25, count 0 2006.173.12:02:12.62#ibcon#read 4, iclass 25, count 0 2006.173.12:02:12.62#ibcon#about to read 5, iclass 25, count 0 2006.173.12:02:12.62#ibcon#read 5, iclass 25, count 0 2006.173.12:02:12.62#ibcon#about to read 6, iclass 25, count 0 2006.173.12:02:12.62#ibcon#read 6, iclass 25, count 0 2006.173.12:02:12.62#ibcon#end of sib2, iclass 25, count 0 2006.173.12:02:12.62#ibcon#*after write, iclass 25, count 0 2006.173.12:02:12.62#ibcon#*before return 0, iclass 25, count 0 2006.173.12:02:12.62#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.12:02:12.62#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.12:02:12.62#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.12:02:12.62#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.12:02:12.62$vck44/vblo=3,649.99 2006.173.12:02:12.62#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.12:02:12.62#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.12:02:12.62#ibcon#ireg 17 cls_cnt 0 2006.173.12:02:12.62#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.12:02:12.62#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.12:02:12.62#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.12:02:12.62#ibcon#enter wrdev, iclass 27, count 0 2006.173.12:02:12.62#ibcon#first serial, iclass 27, count 0 2006.173.12:02:12.62#ibcon#enter sib2, iclass 27, count 0 2006.173.12:02:12.62#ibcon#flushed, iclass 27, count 0 2006.173.12:02:12.62#ibcon#about to write, iclass 27, count 0 2006.173.12:02:12.62#ibcon#wrote, iclass 27, count 0 2006.173.12:02:12.62#ibcon#about to read 3, iclass 27, count 0 2006.173.12:02:12.64#ibcon#read 3, iclass 27, count 0 2006.173.12:02:12.64#ibcon#about to read 4, iclass 27, count 0 2006.173.12:02:12.64#ibcon#read 4, iclass 27, count 0 2006.173.12:02:12.64#ibcon#about to read 5, iclass 27, count 0 2006.173.12:02:12.64#ibcon#read 5, iclass 27, count 0 2006.173.12:02:12.64#ibcon#about to read 6, iclass 27, count 0 2006.173.12:02:12.64#ibcon#read 6, iclass 27, count 0 2006.173.12:02:12.64#ibcon#end of sib2, iclass 27, count 0 2006.173.12:02:12.64#ibcon#*mode == 0, iclass 27, count 0 2006.173.12:02:12.64#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.12:02:12.64#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.12:02:12.64#ibcon#*before write, iclass 27, count 0 2006.173.12:02:12.64#ibcon#enter sib2, iclass 27, count 0 2006.173.12:02:12.64#ibcon#flushed, iclass 27, count 0 2006.173.12:02:12.64#ibcon#about to write, iclass 27, count 0 2006.173.12:02:12.64#ibcon#wrote, iclass 27, count 0 2006.173.12:02:12.64#ibcon#about to read 3, iclass 27, count 0 2006.173.12:02:12.68#ibcon#read 3, iclass 27, count 0 2006.173.12:02:12.68#ibcon#about to read 4, iclass 27, count 0 2006.173.12:02:12.68#ibcon#read 4, iclass 27, count 0 2006.173.12:02:12.68#ibcon#about to read 5, iclass 27, count 0 2006.173.12:02:12.68#ibcon#read 5, iclass 27, count 0 2006.173.12:02:12.68#ibcon#about to read 6, iclass 27, count 0 2006.173.12:02:12.68#ibcon#read 6, iclass 27, count 0 2006.173.12:02:12.68#ibcon#end of sib2, iclass 27, count 0 2006.173.12:02:12.68#ibcon#*after write, iclass 27, count 0 2006.173.12:02:12.68#ibcon#*before return 0, iclass 27, count 0 2006.173.12:02:12.68#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.12:02:12.68#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.12:02:12.68#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.12:02:12.68#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.12:02:12.68$vck44/vb=3,4 2006.173.12:02:12.68#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.12:02:12.68#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.12:02:12.68#ibcon#ireg 11 cls_cnt 2 2006.173.12:02:12.68#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.12:02:12.74#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.12:02:12.74#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.12:02:12.74#ibcon#enter wrdev, iclass 29, count 2 2006.173.12:02:12.74#ibcon#first serial, iclass 29, count 2 2006.173.12:02:12.74#ibcon#enter sib2, iclass 29, count 2 2006.173.12:02:12.74#ibcon#flushed, iclass 29, count 2 2006.173.12:02:12.74#ibcon#about to write, iclass 29, count 2 2006.173.12:02:12.74#ibcon#wrote, iclass 29, count 2 2006.173.12:02:12.74#ibcon#about to read 3, iclass 29, count 2 2006.173.12:02:12.76#ibcon#read 3, iclass 29, count 2 2006.173.12:02:12.76#ibcon#about to read 4, iclass 29, count 2 2006.173.12:02:12.76#ibcon#read 4, iclass 29, count 2 2006.173.12:02:12.76#ibcon#about to read 5, iclass 29, count 2 2006.173.12:02:12.76#ibcon#read 5, iclass 29, count 2 2006.173.12:02:12.76#ibcon#about to read 6, iclass 29, count 2 2006.173.12:02:12.76#ibcon#read 6, iclass 29, count 2 2006.173.12:02:12.76#ibcon#end of sib2, iclass 29, count 2 2006.173.12:02:12.76#ibcon#*mode == 0, iclass 29, count 2 2006.173.12:02:12.76#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.12:02:12.76#ibcon#[27=AT03-04\r\n] 2006.173.12:02:12.76#ibcon#*before write, iclass 29, count 2 2006.173.12:02:12.76#ibcon#enter sib2, iclass 29, count 2 2006.173.12:02:12.76#ibcon#flushed, iclass 29, count 2 2006.173.12:02:12.76#ibcon#about to write, iclass 29, count 2 2006.173.12:02:12.76#ibcon#wrote, iclass 29, count 2 2006.173.12:02:12.76#ibcon#about to read 3, iclass 29, count 2 2006.173.12:02:12.79#ibcon#read 3, iclass 29, count 2 2006.173.12:02:12.79#ibcon#about to read 4, iclass 29, count 2 2006.173.12:02:12.79#ibcon#read 4, iclass 29, count 2 2006.173.12:02:12.79#ibcon#about to read 5, iclass 29, count 2 2006.173.12:02:12.79#ibcon#read 5, iclass 29, count 2 2006.173.12:02:12.79#ibcon#about to read 6, iclass 29, count 2 2006.173.12:02:12.79#ibcon#read 6, iclass 29, count 2 2006.173.12:02:12.79#ibcon#end of sib2, iclass 29, count 2 2006.173.12:02:12.79#ibcon#*after write, iclass 29, count 2 2006.173.12:02:12.79#ibcon#*before return 0, iclass 29, count 2 2006.173.12:02:12.79#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.12:02:12.79#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.12:02:12.79#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.12:02:12.79#ibcon#ireg 7 cls_cnt 0 2006.173.12:02:12.79#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.12:02:12.91#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.12:02:12.91#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.12:02:12.91#ibcon#enter wrdev, iclass 29, count 0 2006.173.12:02:12.91#ibcon#first serial, iclass 29, count 0 2006.173.12:02:12.91#ibcon#enter sib2, iclass 29, count 0 2006.173.12:02:12.91#ibcon#flushed, iclass 29, count 0 2006.173.12:02:12.91#ibcon#about to write, iclass 29, count 0 2006.173.12:02:12.91#ibcon#wrote, iclass 29, count 0 2006.173.12:02:12.91#ibcon#about to read 3, iclass 29, count 0 2006.173.12:02:12.93#ibcon#read 3, iclass 29, count 0 2006.173.12:02:12.93#ibcon#about to read 4, iclass 29, count 0 2006.173.12:02:12.93#ibcon#read 4, iclass 29, count 0 2006.173.12:02:12.93#ibcon#about to read 5, iclass 29, count 0 2006.173.12:02:12.93#ibcon#read 5, iclass 29, count 0 2006.173.12:02:12.93#ibcon#about to read 6, iclass 29, count 0 2006.173.12:02:12.93#ibcon#read 6, iclass 29, count 0 2006.173.12:02:12.93#ibcon#end of sib2, iclass 29, count 0 2006.173.12:02:12.93#ibcon#*mode == 0, iclass 29, count 0 2006.173.12:02:12.93#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.12:02:12.93#ibcon#[27=USB\r\n] 2006.173.12:02:12.93#ibcon#*before write, iclass 29, count 0 2006.173.12:02:12.93#ibcon#enter sib2, iclass 29, count 0 2006.173.12:02:12.93#ibcon#flushed, iclass 29, count 0 2006.173.12:02:12.93#ibcon#about to write, iclass 29, count 0 2006.173.12:02:12.93#ibcon#wrote, iclass 29, count 0 2006.173.12:02:12.93#ibcon#about to read 3, iclass 29, count 0 2006.173.12:02:12.96#ibcon#read 3, iclass 29, count 0 2006.173.12:02:12.96#ibcon#about to read 4, iclass 29, count 0 2006.173.12:02:12.96#ibcon#read 4, iclass 29, count 0 2006.173.12:02:12.96#ibcon#about to read 5, iclass 29, count 0 2006.173.12:02:12.96#ibcon#read 5, iclass 29, count 0 2006.173.12:02:12.96#ibcon#about to read 6, iclass 29, count 0 2006.173.12:02:12.96#ibcon#read 6, iclass 29, count 0 2006.173.12:02:12.96#ibcon#end of sib2, iclass 29, count 0 2006.173.12:02:12.96#ibcon#*after write, iclass 29, count 0 2006.173.12:02:12.96#ibcon#*before return 0, iclass 29, count 0 2006.173.12:02:12.96#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.12:02:12.96#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.12:02:12.96#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.12:02:12.96#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.12:02:12.96$vck44/vblo=4,679.99 2006.173.12:02:12.96#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.12:02:12.96#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.12:02:12.96#ibcon#ireg 17 cls_cnt 0 2006.173.12:02:12.96#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.12:02:12.96#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.12:02:12.96#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.12:02:12.96#ibcon#enter wrdev, iclass 31, count 0 2006.173.12:02:12.96#ibcon#first serial, iclass 31, count 0 2006.173.12:02:12.96#ibcon#enter sib2, iclass 31, count 0 2006.173.12:02:12.96#ibcon#flushed, iclass 31, count 0 2006.173.12:02:12.96#ibcon#about to write, iclass 31, count 0 2006.173.12:02:12.96#ibcon#wrote, iclass 31, count 0 2006.173.12:02:12.96#ibcon#about to read 3, iclass 31, count 0 2006.173.12:02:12.98#ibcon#read 3, iclass 31, count 0 2006.173.12:02:12.98#ibcon#about to read 4, iclass 31, count 0 2006.173.12:02:12.98#ibcon#read 4, iclass 31, count 0 2006.173.12:02:12.98#ibcon#about to read 5, iclass 31, count 0 2006.173.12:02:12.98#ibcon#read 5, iclass 31, count 0 2006.173.12:02:12.98#ibcon#about to read 6, iclass 31, count 0 2006.173.12:02:12.98#ibcon#read 6, iclass 31, count 0 2006.173.12:02:12.98#ibcon#end of sib2, iclass 31, count 0 2006.173.12:02:12.98#ibcon#*mode == 0, iclass 31, count 0 2006.173.12:02:12.98#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.12:02:12.98#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.12:02:12.98#ibcon#*before write, iclass 31, count 0 2006.173.12:02:12.98#ibcon#enter sib2, iclass 31, count 0 2006.173.12:02:12.98#ibcon#flushed, iclass 31, count 0 2006.173.12:02:12.98#ibcon#about to write, iclass 31, count 0 2006.173.12:02:12.98#ibcon#wrote, iclass 31, count 0 2006.173.12:02:12.98#ibcon#about to read 3, iclass 31, count 0 2006.173.12:02:13.02#ibcon#read 3, iclass 31, count 0 2006.173.12:02:13.02#ibcon#about to read 4, iclass 31, count 0 2006.173.12:02:13.02#ibcon#read 4, iclass 31, count 0 2006.173.12:02:13.02#ibcon#about to read 5, iclass 31, count 0 2006.173.12:02:13.02#ibcon#read 5, iclass 31, count 0 2006.173.12:02:13.02#ibcon#about to read 6, iclass 31, count 0 2006.173.12:02:13.02#ibcon#read 6, iclass 31, count 0 2006.173.12:02:13.02#ibcon#end of sib2, iclass 31, count 0 2006.173.12:02:13.02#ibcon#*after write, iclass 31, count 0 2006.173.12:02:13.02#ibcon#*before return 0, iclass 31, count 0 2006.173.12:02:13.02#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.12:02:13.02#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.12:02:13.02#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.12:02:13.02#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.12:02:13.02$vck44/vb=4,4 2006.173.12:02:13.02#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.173.12:02:13.02#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.173.12:02:13.02#ibcon#ireg 11 cls_cnt 2 2006.173.12:02:13.02#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.12:02:13.08#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.12:02:13.08#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.12:02:13.08#ibcon#enter wrdev, iclass 33, count 2 2006.173.12:02:13.08#ibcon#first serial, iclass 33, count 2 2006.173.12:02:13.08#ibcon#enter sib2, iclass 33, count 2 2006.173.12:02:13.08#ibcon#flushed, iclass 33, count 2 2006.173.12:02:13.08#ibcon#about to write, iclass 33, count 2 2006.173.12:02:13.08#ibcon#wrote, iclass 33, count 2 2006.173.12:02:13.08#ibcon#about to read 3, iclass 33, count 2 2006.173.12:02:13.10#ibcon#read 3, iclass 33, count 2 2006.173.12:02:13.10#ibcon#about to read 4, iclass 33, count 2 2006.173.12:02:13.10#ibcon#read 4, iclass 33, count 2 2006.173.12:02:13.10#ibcon#about to read 5, iclass 33, count 2 2006.173.12:02:13.10#ibcon#read 5, iclass 33, count 2 2006.173.12:02:13.10#ibcon#about to read 6, iclass 33, count 2 2006.173.12:02:13.10#ibcon#read 6, iclass 33, count 2 2006.173.12:02:13.10#ibcon#end of sib2, iclass 33, count 2 2006.173.12:02:13.10#ibcon#*mode == 0, iclass 33, count 2 2006.173.12:02:13.10#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.173.12:02:13.10#ibcon#[27=AT04-04\r\n] 2006.173.12:02:13.10#ibcon#*before write, iclass 33, count 2 2006.173.12:02:13.10#ibcon#enter sib2, iclass 33, count 2 2006.173.12:02:13.10#ibcon#flushed, iclass 33, count 2 2006.173.12:02:13.10#ibcon#about to write, iclass 33, count 2 2006.173.12:02:13.10#ibcon#wrote, iclass 33, count 2 2006.173.12:02:13.10#ibcon#about to read 3, iclass 33, count 2 2006.173.12:02:13.13#ibcon#read 3, iclass 33, count 2 2006.173.12:02:13.13#ibcon#about to read 4, iclass 33, count 2 2006.173.12:02:13.13#ibcon#read 4, iclass 33, count 2 2006.173.12:02:13.13#ibcon#about to read 5, iclass 33, count 2 2006.173.12:02:13.13#ibcon#read 5, iclass 33, count 2 2006.173.12:02:13.13#ibcon#about to read 6, iclass 33, count 2 2006.173.12:02:13.13#ibcon#read 6, iclass 33, count 2 2006.173.12:02:13.13#ibcon#end of sib2, iclass 33, count 2 2006.173.12:02:13.13#ibcon#*after write, iclass 33, count 2 2006.173.12:02:13.13#ibcon#*before return 0, iclass 33, count 2 2006.173.12:02:13.13#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.12:02:13.13#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.173.12:02:13.13#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.173.12:02:13.13#ibcon#ireg 7 cls_cnt 0 2006.173.12:02:13.13#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.12:02:13.25#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.12:02:13.25#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.12:02:13.25#ibcon#enter wrdev, iclass 33, count 0 2006.173.12:02:13.25#ibcon#first serial, iclass 33, count 0 2006.173.12:02:13.25#ibcon#enter sib2, iclass 33, count 0 2006.173.12:02:13.25#ibcon#flushed, iclass 33, count 0 2006.173.12:02:13.25#ibcon#about to write, iclass 33, count 0 2006.173.12:02:13.25#ibcon#wrote, iclass 33, count 0 2006.173.12:02:13.25#ibcon#about to read 3, iclass 33, count 0 2006.173.12:02:13.27#ibcon#read 3, iclass 33, count 0 2006.173.12:02:13.27#ibcon#about to read 4, iclass 33, count 0 2006.173.12:02:13.27#ibcon#read 4, iclass 33, count 0 2006.173.12:02:13.27#ibcon#about to read 5, iclass 33, count 0 2006.173.12:02:13.27#ibcon#read 5, iclass 33, count 0 2006.173.12:02:13.27#ibcon#about to read 6, iclass 33, count 0 2006.173.12:02:13.27#ibcon#read 6, iclass 33, count 0 2006.173.12:02:13.27#ibcon#end of sib2, iclass 33, count 0 2006.173.12:02:13.27#ibcon#*mode == 0, iclass 33, count 0 2006.173.12:02:13.27#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.12:02:13.27#ibcon#[27=USB\r\n] 2006.173.12:02:13.27#ibcon#*before write, iclass 33, count 0 2006.173.12:02:13.27#ibcon#enter sib2, iclass 33, count 0 2006.173.12:02:13.27#ibcon#flushed, iclass 33, count 0 2006.173.12:02:13.27#ibcon#about to write, iclass 33, count 0 2006.173.12:02:13.27#ibcon#wrote, iclass 33, count 0 2006.173.12:02:13.27#ibcon#about to read 3, iclass 33, count 0 2006.173.12:02:13.30#ibcon#read 3, iclass 33, count 0 2006.173.12:02:13.30#ibcon#about to read 4, iclass 33, count 0 2006.173.12:02:13.30#ibcon#read 4, iclass 33, count 0 2006.173.12:02:13.30#ibcon#about to read 5, iclass 33, count 0 2006.173.12:02:13.30#ibcon#read 5, iclass 33, count 0 2006.173.12:02:13.30#ibcon#about to read 6, iclass 33, count 0 2006.173.12:02:13.30#ibcon#read 6, iclass 33, count 0 2006.173.12:02:13.30#ibcon#end of sib2, iclass 33, count 0 2006.173.12:02:13.30#ibcon#*after write, iclass 33, count 0 2006.173.12:02:13.30#ibcon#*before return 0, iclass 33, count 0 2006.173.12:02:13.30#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.12:02:13.30#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.173.12:02:13.30#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.12:02:13.30#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.12:02:13.30$vck44/vblo=5,709.99 2006.173.12:02:13.30#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.12:02:13.30#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.12:02:13.30#ibcon#ireg 17 cls_cnt 0 2006.173.12:02:13.30#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.12:02:13.30#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.12:02:13.30#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.12:02:13.30#ibcon#enter wrdev, iclass 35, count 0 2006.173.12:02:13.30#ibcon#first serial, iclass 35, count 0 2006.173.12:02:13.30#ibcon#enter sib2, iclass 35, count 0 2006.173.12:02:13.30#ibcon#flushed, iclass 35, count 0 2006.173.12:02:13.30#ibcon#about to write, iclass 35, count 0 2006.173.12:02:13.30#ibcon#wrote, iclass 35, count 0 2006.173.12:02:13.30#ibcon#about to read 3, iclass 35, count 0 2006.173.12:02:13.32#ibcon#read 3, iclass 35, count 0 2006.173.12:02:13.32#ibcon#about to read 4, iclass 35, count 0 2006.173.12:02:13.32#ibcon#read 4, iclass 35, count 0 2006.173.12:02:13.32#ibcon#about to read 5, iclass 35, count 0 2006.173.12:02:13.32#ibcon#read 5, iclass 35, count 0 2006.173.12:02:13.32#ibcon#about to read 6, iclass 35, count 0 2006.173.12:02:13.32#ibcon#read 6, iclass 35, count 0 2006.173.12:02:13.32#ibcon#end of sib2, iclass 35, count 0 2006.173.12:02:13.32#ibcon#*mode == 0, iclass 35, count 0 2006.173.12:02:13.32#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.12:02:13.32#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.12:02:13.32#ibcon#*before write, iclass 35, count 0 2006.173.12:02:13.32#ibcon#enter sib2, iclass 35, count 0 2006.173.12:02:13.32#ibcon#flushed, iclass 35, count 0 2006.173.12:02:13.32#ibcon#about to write, iclass 35, count 0 2006.173.12:02:13.32#ibcon#wrote, iclass 35, count 0 2006.173.12:02:13.32#ibcon#about to read 3, iclass 35, count 0 2006.173.12:02:13.36#ibcon#read 3, iclass 35, count 0 2006.173.12:02:13.36#ibcon#about to read 4, iclass 35, count 0 2006.173.12:02:13.36#ibcon#read 4, iclass 35, count 0 2006.173.12:02:13.36#ibcon#about to read 5, iclass 35, count 0 2006.173.12:02:13.36#ibcon#read 5, iclass 35, count 0 2006.173.12:02:13.36#ibcon#about to read 6, iclass 35, count 0 2006.173.12:02:13.36#ibcon#read 6, iclass 35, count 0 2006.173.12:02:13.36#ibcon#end of sib2, iclass 35, count 0 2006.173.12:02:13.36#ibcon#*after write, iclass 35, count 0 2006.173.12:02:13.36#ibcon#*before return 0, iclass 35, count 0 2006.173.12:02:13.36#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.12:02:13.36#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.12:02:13.36#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.12:02:13.36#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.12:02:13.36$vck44/vb=5,4 2006.173.12:02:13.36#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.173.12:02:13.36#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.173.12:02:13.36#ibcon#ireg 11 cls_cnt 2 2006.173.12:02:13.36#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.12:02:13.42#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.12:02:13.42#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.12:02:13.42#ibcon#enter wrdev, iclass 37, count 2 2006.173.12:02:13.42#ibcon#first serial, iclass 37, count 2 2006.173.12:02:13.42#ibcon#enter sib2, iclass 37, count 2 2006.173.12:02:13.42#ibcon#flushed, iclass 37, count 2 2006.173.12:02:13.42#ibcon#about to write, iclass 37, count 2 2006.173.12:02:13.42#ibcon#wrote, iclass 37, count 2 2006.173.12:02:13.42#ibcon#about to read 3, iclass 37, count 2 2006.173.12:02:13.44#ibcon#read 3, iclass 37, count 2 2006.173.12:02:13.44#ibcon#about to read 4, iclass 37, count 2 2006.173.12:02:13.44#ibcon#read 4, iclass 37, count 2 2006.173.12:02:13.44#ibcon#about to read 5, iclass 37, count 2 2006.173.12:02:13.44#ibcon#read 5, iclass 37, count 2 2006.173.12:02:13.44#ibcon#about to read 6, iclass 37, count 2 2006.173.12:02:13.44#ibcon#read 6, iclass 37, count 2 2006.173.12:02:13.44#ibcon#end of sib2, iclass 37, count 2 2006.173.12:02:13.44#ibcon#*mode == 0, iclass 37, count 2 2006.173.12:02:13.44#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.173.12:02:13.44#ibcon#[27=AT05-04\r\n] 2006.173.12:02:13.44#ibcon#*before write, iclass 37, count 2 2006.173.12:02:13.44#ibcon#enter sib2, iclass 37, count 2 2006.173.12:02:13.44#ibcon#flushed, iclass 37, count 2 2006.173.12:02:13.44#ibcon#about to write, iclass 37, count 2 2006.173.12:02:13.44#ibcon#wrote, iclass 37, count 2 2006.173.12:02:13.44#ibcon#about to read 3, iclass 37, count 2 2006.173.12:02:13.47#ibcon#read 3, iclass 37, count 2 2006.173.12:02:13.47#ibcon#about to read 4, iclass 37, count 2 2006.173.12:02:13.47#ibcon#read 4, iclass 37, count 2 2006.173.12:02:13.47#ibcon#about to read 5, iclass 37, count 2 2006.173.12:02:13.47#ibcon#read 5, iclass 37, count 2 2006.173.12:02:13.47#ibcon#about to read 6, iclass 37, count 2 2006.173.12:02:13.47#ibcon#read 6, iclass 37, count 2 2006.173.12:02:13.47#ibcon#end of sib2, iclass 37, count 2 2006.173.12:02:13.47#ibcon#*after write, iclass 37, count 2 2006.173.12:02:13.47#ibcon#*before return 0, iclass 37, count 2 2006.173.12:02:13.47#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.12:02:13.47#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.173.12:02:13.47#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.173.12:02:13.47#ibcon#ireg 7 cls_cnt 0 2006.173.12:02:13.47#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.12:02:13.59#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.12:02:13.59#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.12:02:13.59#ibcon#enter wrdev, iclass 37, count 0 2006.173.12:02:13.59#ibcon#first serial, iclass 37, count 0 2006.173.12:02:13.59#ibcon#enter sib2, iclass 37, count 0 2006.173.12:02:13.59#ibcon#flushed, iclass 37, count 0 2006.173.12:02:13.59#ibcon#about to write, iclass 37, count 0 2006.173.12:02:13.59#ibcon#wrote, iclass 37, count 0 2006.173.12:02:13.59#ibcon#about to read 3, iclass 37, count 0 2006.173.12:02:13.61#ibcon#read 3, iclass 37, count 0 2006.173.12:02:13.61#ibcon#about to read 4, iclass 37, count 0 2006.173.12:02:13.61#ibcon#read 4, iclass 37, count 0 2006.173.12:02:13.61#ibcon#about to read 5, iclass 37, count 0 2006.173.12:02:13.61#ibcon#read 5, iclass 37, count 0 2006.173.12:02:13.61#ibcon#about to read 6, iclass 37, count 0 2006.173.12:02:13.61#ibcon#read 6, iclass 37, count 0 2006.173.12:02:13.61#ibcon#end of sib2, iclass 37, count 0 2006.173.12:02:13.61#ibcon#*mode == 0, iclass 37, count 0 2006.173.12:02:13.61#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.12:02:13.61#ibcon#[27=USB\r\n] 2006.173.12:02:13.61#ibcon#*before write, iclass 37, count 0 2006.173.12:02:13.61#ibcon#enter sib2, iclass 37, count 0 2006.173.12:02:13.61#ibcon#flushed, iclass 37, count 0 2006.173.12:02:13.61#ibcon#about to write, iclass 37, count 0 2006.173.12:02:13.61#ibcon#wrote, iclass 37, count 0 2006.173.12:02:13.61#ibcon#about to read 3, iclass 37, count 0 2006.173.12:02:13.64#ibcon#read 3, iclass 37, count 0 2006.173.12:02:13.64#ibcon#about to read 4, iclass 37, count 0 2006.173.12:02:13.64#ibcon#read 4, iclass 37, count 0 2006.173.12:02:13.64#ibcon#about to read 5, iclass 37, count 0 2006.173.12:02:13.64#ibcon#read 5, iclass 37, count 0 2006.173.12:02:13.64#ibcon#about to read 6, iclass 37, count 0 2006.173.12:02:13.64#ibcon#read 6, iclass 37, count 0 2006.173.12:02:13.64#ibcon#end of sib2, iclass 37, count 0 2006.173.12:02:13.64#ibcon#*after write, iclass 37, count 0 2006.173.12:02:13.64#ibcon#*before return 0, iclass 37, count 0 2006.173.12:02:13.64#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.12:02:13.64#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.173.12:02:13.64#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.12:02:13.64#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.12:02:13.64$vck44/vblo=6,719.99 2006.173.12:02:13.64#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.12:02:13.64#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.12:02:13.64#ibcon#ireg 17 cls_cnt 0 2006.173.12:02:13.64#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.12:02:13.64#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.12:02:13.64#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.12:02:13.64#ibcon#enter wrdev, iclass 39, count 0 2006.173.12:02:13.64#ibcon#first serial, iclass 39, count 0 2006.173.12:02:13.64#ibcon#enter sib2, iclass 39, count 0 2006.173.12:02:13.64#ibcon#flushed, iclass 39, count 0 2006.173.12:02:13.64#ibcon#about to write, iclass 39, count 0 2006.173.12:02:13.64#ibcon#wrote, iclass 39, count 0 2006.173.12:02:13.64#ibcon#about to read 3, iclass 39, count 0 2006.173.12:02:13.66#ibcon#read 3, iclass 39, count 0 2006.173.12:02:13.66#ibcon#about to read 4, iclass 39, count 0 2006.173.12:02:13.66#ibcon#read 4, iclass 39, count 0 2006.173.12:02:13.66#ibcon#about to read 5, iclass 39, count 0 2006.173.12:02:13.66#ibcon#read 5, iclass 39, count 0 2006.173.12:02:13.66#ibcon#about to read 6, iclass 39, count 0 2006.173.12:02:13.66#ibcon#read 6, iclass 39, count 0 2006.173.12:02:13.66#ibcon#end of sib2, iclass 39, count 0 2006.173.12:02:13.66#ibcon#*mode == 0, iclass 39, count 0 2006.173.12:02:13.66#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.12:02:13.66#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.12:02:13.66#ibcon#*before write, iclass 39, count 0 2006.173.12:02:13.66#ibcon#enter sib2, iclass 39, count 0 2006.173.12:02:13.66#ibcon#flushed, iclass 39, count 0 2006.173.12:02:13.66#ibcon#about to write, iclass 39, count 0 2006.173.12:02:13.66#ibcon#wrote, iclass 39, count 0 2006.173.12:02:13.66#ibcon#about to read 3, iclass 39, count 0 2006.173.12:02:13.70#ibcon#read 3, iclass 39, count 0 2006.173.12:02:13.70#ibcon#about to read 4, iclass 39, count 0 2006.173.12:02:13.70#ibcon#read 4, iclass 39, count 0 2006.173.12:02:13.70#ibcon#about to read 5, iclass 39, count 0 2006.173.12:02:13.70#ibcon#read 5, iclass 39, count 0 2006.173.12:02:13.70#ibcon#about to read 6, iclass 39, count 0 2006.173.12:02:13.70#ibcon#read 6, iclass 39, count 0 2006.173.12:02:13.70#ibcon#end of sib2, iclass 39, count 0 2006.173.12:02:13.70#ibcon#*after write, iclass 39, count 0 2006.173.12:02:13.70#ibcon#*before return 0, iclass 39, count 0 2006.173.12:02:13.70#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.12:02:13.70#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.12:02:13.70#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.12:02:13.70#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.12:02:13.70$vck44/vb=6,4 2006.173.12:02:13.70#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.12:02:13.70#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.12:02:13.70#ibcon#ireg 11 cls_cnt 2 2006.173.12:02:13.70#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.12:02:13.76#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.12:02:13.76#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.12:02:13.76#ibcon#enter wrdev, iclass 3, count 2 2006.173.12:02:13.76#ibcon#first serial, iclass 3, count 2 2006.173.12:02:13.76#ibcon#enter sib2, iclass 3, count 2 2006.173.12:02:13.76#ibcon#flushed, iclass 3, count 2 2006.173.12:02:13.76#ibcon#about to write, iclass 3, count 2 2006.173.12:02:13.76#ibcon#wrote, iclass 3, count 2 2006.173.12:02:13.76#ibcon#about to read 3, iclass 3, count 2 2006.173.12:02:13.78#ibcon#read 3, iclass 3, count 2 2006.173.12:02:13.78#ibcon#about to read 4, iclass 3, count 2 2006.173.12:02:13.78#ibcon#read 4, iclass 3, count 2 2006.173.12:02:13.78#ibcon#about to read 5, iclass 3, count 2 2006.173.12:02:13.78#ibcon#read 5, iclass 3, count 2 2006.173.12:02:13.78#ibcon#about to read 6, iclass 3, count 2 2006.173.12:02:13.78#ibcon#read 6, iclass 3, count 2 2006.173.12:02:13.78#ibcon#end of sib2, iclass 3, count 2 2006.173.12:02:13.78#ibcon#*mode == 0, iclass 3, count 2 2006.173.12:02:13.78#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.12:02:13.78#ibcon#[27=AT06-04\r\n] 2006.173.12:02:13.78#ibcon#*before write, iclass 3, count 2 2006.173.12:02:13.78#ibcon#enter sib2, iclass 3, count 2 2006.173.12:02:13.78#ibcon#flushed, iclass 3, count 2 2006.173.12:02:13.78#ibcon#about to write, iclass 3, count 2 2006.173.12:02:13.78#ibcon#wrote, iclass 3, count 2 2006.173.12:02:13.78#ibcon#about to read 3, iclass 3, count 2 2006.173.12:02:13.81#ibcon#read 3, iclass 3, count 2 2006.173.12:02:13.81#ibcon#about to read 4, iclass 3, count 2 2006.173.12:02:13.81#ibcon#read 4, iclass 3, count 2 2006.173.12:02:13.81#ibcon#about to read 5, iclass 3, count 2 2006.173.12:02:13.81#ibcon#read 5, iclass 3, count 2 2006.173.12:02:13.81#ibcon#about to read 6, iclass 3, count 2 2006.173.12:02:13.81#ibcon#read 6, iclass 3, count 2 2006.173.12:02:13.81#ibcon#end of sib2, iclass 3, count 2 2006.173.12:02:13.81#ibcon#*after write, iclass 3, count 2 2006.173.12:02:13.81#ibcon#*before return 0, iclass 3, count 2 2006.173.12:02:13.81#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.12:02:13.81#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.12:02:13.81#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.12:02:13.81#ibcon#ireg 7 cls_cnt 0 2006.173.12:02:13.81#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.12:02:13.93#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.12:02:13.93#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.12:02:13.93#ibcon#enter wrdev, iclass 3, count 0 2006.173.12:02:13.93#ibcon#first serial, iclass 3, count 0 2006.173.12:02:13.93#ibcon#enter sib2, iclass 3, count 0 2006.173.12:02:13.93#ibcon#flushed, iclass 3, count 0 2006.173.12:02:13.93#ibcon#about to write, iclass 3, count 0 2006.173.12:02:13.93#ibcon#wrote, iclass 3, count 0 2006.173.12:02:13.93#ibcon#about to read 3, iclass 3, count 0 2006.173.12:02:13.95#ibcon#read 3, iclass 3, count 0 2006.173.12:02:13.95#ibcon#about to read 4, iclass 3, count 0 2006.173.12:02:13.95#ibcon#read 4, iclass 3, count 0 2006.173.12:02:13.95#ibcon#about to read 5, iclass 3, count 0 2006.173.12:02:13.95#ibcon#read 5, iclass 3, count 0 2006.173.12:02:13.95#ibcon#about to read 6, iclass 3, count 0 2006.173.12:02:13.95#ibcon#read 6, iclass 3, count 0 2006.173.12:02:13.95#ibcon#end of sib2, iclass 3, count 0 2006.173.12:02:13.95#ibcon#*mode == 0, iclass 3, count 0 2006.173.12:02:13.95#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.12:02:13.95#ibcon#[27=USB\r\n] 2006.173.12:02:13.95#ibcon#*before write, iclass 3, count 0 2006.173.12:02:13.95#ibcon#enter sib2, iclass 3, count 0 2006.173.12:02:13.95#ibcon#flushed, iclass 3, count 0 2006.173.12:02:13.95#ibcon#about to write, iclass 3, count 0 2006.173.12:02:13.95#ibcon#wrote, iclass 3, count 0 2006.173.12:02:13.95#ibcon#about to read 3, iclass 3, count 0 2006.173.12:02:13.98#ibcon#read 3, iclass 3, count 0 2006.173.12:02:13.98#ibcon#about to read 4, iclass 3, count 0 2006.173.12:02:13.98#ibcon#read 4, iclass 3, count 0 2006.173.12:02:13.98#ibcon#about to read 5, iclass 3, count 0 2006.173.12:02:13.98#ibcon#read 5, iclass 3, count 0 2006.173.12:02:13.98#ibcon#about to read 6, iclass 3, count 0 2006.173.12:02:13.98#ibcon#read 6, iclass 3, count 0 2006.173.12:02:13.98#ibcon#end of sib2, iclass 3, count 0 2006.173.12:02:13.98#ibcon#*after write, iclass 3, count 0 2006.173.12:02:13.98#ibcon#*before return 0, iclass 3, count 0 2006.173.12:02:13.98#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.12:02:13.98#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.12:02:13.98#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.12:02:13.98#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.12:02:13.98$vck44/vblo=7,734.99 2006.173.12:02:13.98#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.12:02:13.98#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.12:02:13.98#ibcon#ireg 17 cls_cnt 0 2006.173.12:02:13.98#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.12:02:13.98#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.12:02:13.98#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.12:02:13.98#ibcon#enter wrdev, iclass 5, count 0 2006.173.12:02:13.98#ibcon#first serial, iclass 5, count 0 2006.173.12:02:13.98#ibcon#enter sib2, iclass 5, count 0 2006.173.12:02:13.98#ibcon#flushed, iclass 5, count 0 2006.173.12:02:13.98#ibcon#about to write, iclass 5, count 0 2006.173.12:02:13.98#ibcon#wrote, iclass 5, count 0 2006.173.12:02:13.98#ibcon#about to read 3, iclass 5, count 0 2006.173.12:02:14.00#ibcon#read 3, iclass 5, count 0 2006.173.12:02:14.00#ibcon#about to read 4, iclass 5, count 0 2006.173.12:02:14.00#ibcon#read 4, iclass 5, count 0 2006.173.12:02:14.00#ibcon#about to read 5, iclass 5, count 0 2006.173.12:02:14.00#ibcon#read 5, iclass 5, count 0 2006.173.12:02:14.00#ibcon#about to read 6, iclass 5, count 0 2006.173.12:02:14.00#ibcon#read 6, iclass 5, count 0 2006.173.12:02:14.00#ibcon#end of sib2, iclass 5, count 0 2006.173.12:02:14.00#ibcon#*mode == 0, iclass 5, count 0 2006.173.12:02:14.00#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.12:02:14.00#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.12:02:14.00#ibcon#*before write, iclass 5, count 0 2006.173.12:02:14.00#ibcon#enter sib2, iclass 5, count 0 2006.173.12:02:14.00#ibcon#flushed, iclass 5, count 0 2006.173.12:02:14.00#ibcon#about to write, iclass 5, count 0 2006.173.12:02:14.00#ibcon#wrote, iclass 5, count 0 2006.173.12:02:14.00#ibcon#about to read 3, iclass 5, count 0 2006.173.12:02:14.04#ibcon#read 3, iclass 5, count 0 2006.173.12:02:14.04#ibcon#about to read 4, iclass 5, count 0 2006.173.12:02:14.04#ibcon#read 4, iclass 5, count 0 2006.173.12:02:14.04#ibcon#about to read 5, iclass 5, count 0 2006.173.12:02:14.04#ibcon#read 5, iclass 5, count 0 2006.173.12:02:14.04#ibcon#about to read 6, iclass 5, count 0 2006.173.12:02:14.04#ibcon#read 6, iclass 5, count 0 2006.173.12:02:14.04#ibcon#end of sib2, iclass 5, count 0 2006.173.12:02:14.04#ibcon#*after write, iclass 5, count 0 2006.173.12:02:14.04#ibcon#*before return 0, iclass 5, count 0 2006.173.12:02:14.04#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.12:02:14.04#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.12:02:14.04#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.12:02:14.04#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.12:02:14.04$vck44/vb=7,4 2006.173.12:02:14.04#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.173.12:02:14.04#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.173.12:02:14.04#ibcon#ireg 11 cls_cnt 2 2006.173.12:02:14.04#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.12:02:14.10#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.12:02:14.10#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.12:02:14.10#ibcon#enter wrdev, iclass 7, count 2 2006.173.12:02:14.10#ibcon#first serial, iclass 7, count 2 2006.173.12:02:14.10#ibcon#enter sib2, iclass 7, count 2 2006.173.12:02:14.10#ibcon#flushed, iclass 7, count 2 2006.173.12:02:14.10#ibcon#about to write, iclass 7, count 2 2006.173.12:02:14.10#ibcon#wrote, iclass 7, count 2 2006.173.12:02:14.10#ibcon#about to read 3, iclass 7, count 2 2006.173.12:02:14.12#ibcon#read 3, iclass 7, count 2 2006.173.12:02:14.12#ibcon#about to read 4, iclass 7, count 2 2006.173.12:02:14.12#ibcon#read 4, iclass 7, count 2 2006.173.12:02:14.12#ibcon#about to read 5, iclass 7, count 2 2006.173.12:02:14.12#ibcon#read 5, iclass 7, count 2 2006.173.12:02:14.12#ibcon#about to read 6, iclass 7, count 2 2006.173.12:02:14.12#ibcon#read 6, iclass 7, count 2 2006.173.12:02:14.12#ibcon#end of sib2, iclass 7, count 2 2006.173.12:02:14.12#ibcon#*mode == 0, iclass 7, count 2 2006.173.12:02:14.12#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.173.12:02:14.12#ibcon#[27=AT07-04\r\n] 2006.173.12:02:14.12#ibcon#*before write, iclass 7, count 2 2006.173.12:02:14.12#ibcon#enter sib2, iclass 7, count 2 2006.173.12:02:14.12#ibcon#flushed, iclass 7, count 2 2006.173.12:02:14.12#ibcon#about to write, iclass 7, count 2 2006.173.12:02:14.12#ibcon#wrote, iclass 7, count 2 2006.173.12:02:14.12#ibcon#about to read 3, iclass 7, count 2 2006.173.12:02:14.15#ibcon#read 3, iclass 7, count 2 2006.173.12:02:14.15#ibcon#about to read 4, iclass 7, count 2 2006.173.12:02:14.15#ibcon#read 4, iclass 7, count 2 2006.173.12:02:14.15#ibcon#about to read 5, iclass 7, count 2 2006.173.12:02:14.15#ibcon#read 5, iclass 7, count 2 2006.173.12:02:14.15#ibcon#about to read 6, iclass 7, count 2 2006.173.12:02:14.15#ibcon#read 6, iclass 7, count 2 2006.173.12:02:14.15#ibcon#end of sib2, iclass 7, count 2 2006.173.12:02:14.15#ibcon#*after write, iclass 7, count 2 2006.173.12:02:14.15#ibcon#*before return 0, iclass 7, count 2 2006.173.12:02:14.15#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.12:02:14.15#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.173.12:02:14.15#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.173.12:02:14.15#ibcon#ireg 7 cls_cnt 0 2006.173.12:02:14.15#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.12:02:14.27#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.12:02:14.27#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.12:02:14.27#ibcon#enter wrdev, iclass 7, count 0 2006.173.12:02:14.27#ibcon#first serial, iclass 7, count 0 2006.173.12:02:14.27#ibcon#enter sib2, iclass 7, count 0 2006.173.12:02:14.27#ibcon#flushed, iclass 7, count 0 2006.173.12:02:14.27#ibcon#about to write, iclass 7, count 0 2006.173.12:02:14.27#ibcon#wrote, iclass 7, count 0 2006.173.12:02:14.27#ibcon#about to read 3, iclass 7, count 0 2006.173.12:02:14.29#ibcon#read 3, iclass 7, count 0 2006.173.12:02:14.29#ibcon#about to read 4, iclass 7, count 0 2006.173.12:02:14.29#ibcon#read 4, iclass 7, count 0 2006.173.12:02:14.29#ibcon#about to read 5, iclass 7, count 0 2006.173.12:02:14.29#ibcon#read 5, iclass 7, count 0 2006.173.12:02:14.29#ibcon#about to read 6, iclass 7, count 0 2006.173.12:02:14.29#ibcon#read 6, iclass 7, count 0 2006.173.12:02:14.29#ibcon#end of sib2, iclass 7, count 0 2006.173.12:02:14.29#ibcon#*mode == 0, iclass 7, count 0 2006.173.12:02:14.29#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.12:02:14.29#ibcon#[27=USB\r\n] 2006.173.12:02:14.29#ibcon#*before write, iclass 7, count 0 2006.173.12:02:14.29#ibcon#enter sib2, iclass 7, count 0 2006.173.12:02:14.29#ibcon#flushed, iclass 7, count 0 2006.173.12:02:14.29#ibcon#about to write, iclass 7, count 0 2006.173.12:02:14.29#ibcon#wrote, iclass 7, count 0 2006.173.12:02:14.29#ibcon#about to read 3, iclass 7, count 0 2006.173.12:02:14.32#ibcon#read 3, iclass 7, count 0 2006.173.12:02:14.32#ibcon#about to read 4, iclass 7, count 0 2006.173.12:02:14.32#ibcon#read 4, iclass 7, count 0 2006.173.12:02:14.32#ibcon#about to read 5, iclass 7, count 0 2006.173.12:02:14.32#ibcon#read 5, iclass 7, count 0 2006.173.12:02:14.32#ibcon#about to read 6, iclass 7, count 0 2006.173.12:02:14.32#ibcon#read 6, iclass 7, count 0 2006.173.12:02:14.32#ibcon#end of sib2, iclass 7, count 0 2006.173.12:02:14.32#ibcon#*after write, iclass 7, count 0 2006.173.12:02:14.32#ibcon#*before return 0, iclass 7, count 0 2006.173.12:02:14.32#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.12:02:14.32#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.173.12:02:14.32#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.12:02:14.32#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.12:02:14.32$vck44/vblo=8,744.99 2006.173.12:02:14.32#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.12:02:14.32#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.12:02:14.32#ibcon#ireg 17 cls_cnt 0 2006.173.12:02:14.32#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.12:02:14.32#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.12:02:14.32#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.12:02:14.32#ibcon#enter wrdev, iclass 11, count 0 2006.173.12:02:14.32#ibcon#first serial, iclass 11, count 0 2006.173.12:02:14.32#ibcon#enter sib2, iclass 11, count 0 2006.173.12:02:14.32#ibcon#flushed, iclass 11, count 0 2006.173.12:02:14.32#ibcon#about to write, iclass 11, count 0 2006.173.12:02:14.32#ibcon#wrote, iclass 11, count 0 2006.173.12:02:14.32#ibcon#about to read 3, iclass 11, count 0 2006.173.12:02:14.34#ibcon#read 3, iclass 11, count 0 2006.173.12:02:14.34#ibcon#about to read 4, iclass 11, count 0 2006.173.12:02:14.34#ibcon#read 4, iclass 11, count 0 2006.173.12:02:14.34#ibcon#about to read 5, iclass 11, count 0 2006.173.12:02:14.34#ibcon#read 5, iclass 11, count 0 2006.173.12:02:14.34#ibcon#about to read 6, iclass 11, count 0 2006.173.12:02:14.34#ibcon#read 6, iclass 11, count 0 2006.173.12:02:14.34#ibcon#end of sib2, iclass 11, count 0 2006.173.12:02:14.34#ibcon#*mode == 0, iclass 11, count 0 2006.173.12:02:14.34#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.12:02:14.34#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.12:02:14.34#ibcon#*before write, iclass 11, count 0 2006.173.12:02:14.34#ibcon#enter sib2, iclass 11, count 0 2006.173.12:02:14.34#ibcon#flushed, iclass 11, count 0 2006.173.12:02:14.34#ibcon#about to write, iclass 11, count 0 2006.173.12:02:14.34#ibcon#wrote, iclass 11, count 0 2006.173.12:02:14.34#ibcon#about to read 3, iclass 11, count 0 2006.173.12:02:14.38#ibcon#read 3, iclass 11, count 0 2006.173.12:02:14.38#ibcon#about to read 4, iclass 11, count 0 2006.173.12:02:14.38#ibcon#read 4, iclass 11, count 0 2006.173.12:02:14.38#ibcon#about to read 5, iclass 11, count 0 2006.173.12:02:14.38#ibcon#read 5, iclass 11, count 0 2006.173.12:02:14.38#ibcon#about to read 6, iclass 11, count 0 2006.173.12:02:14.38#ibcon#read 6, iclass 11, count 0 2006.173.12:02:14.38#ibcon#end of sib2, iclass 11, count 0 2006.173.12:02:14.38#ibcon#*after write, iclass 11, count 0 2006.173.12:02:14.38#ibcon#*before return 0, iclass 11, count 0 2006.173.12:02:14.38#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.12:02:14.38#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.12:02:14.38#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.12:02:14.38#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.12:02:14.38$vck44/vb=8,4 2006.173.12:02:14.38#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.173.12:02:14.38#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.173.12:02:14.38#ibcon#ireg 11 cls_cnt 2 2006.173.12:02:14.38#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.12:02:14.44#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.12:02:14.44#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.12:02:14.44#ibcon#enter wrdev, iclass 13, count 2 2006.173.12:02:14.44#ibcon#first serial, iclass 13, count 2 2006.173.12:02:14.44#ibcon#enter sib2, iclass 13, count 2 2006.173.12:02:14.44#ibcon#flushed, iclass 13, count 2 2006.173.12:02:14.44#ibcon#about to write, iclass 13, count 2 2006.173.12:02:14.44#ibcon#wrote, iclass 13, count 2 2006.173.12:02:14.44#ibcon#about to read 3, iclass 13, count 2 2006.173.12:02:14.46#ibcon#read 3, iclass 13, count 2 2006.173.12:02:14.46#ibcon#about to read 4, iclass 13, count 2 2006.173.12:02:14.46#ibcon#read 4, iclass 13, count 2 2006.173.12:02:14.46#ibcon#about to read 5, iclass 13, count 2 2006.173.12:02:14.46#ibcon#read 5, iclass 13, count 2 2006.173.12:02:14.46#ibcon#about to read 6, iclass 13, count 2 2006.173.12:02:14.46#ibcon#read 6, iclass 13, count 2 2006.173.12:02:14.46#ibcon#end of sib2, iclass 13, count 2 2006.173.12:02:14.46#ibcon#*mode == 0, iclass 13, count 2 2006.173.12:02:14.46#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.173.12:02:14.46#ibcon#[27=AT08-04\r\n] 2006.173.12:02:14.46#ibcon#*before write, iclass 13, count 2 2006.173.12:02:14.46#ibcon#enter sib2, iclass 13, count 2 2006.173.12:02:14.46#ibcon#flushed, iclass 13, count 2 2006.173.12:02:14.46#ibcon#about to write, iclass 13, count 2 2006.173.12:02:14.46#ibcon#wrote, iclass 13, count 2 2006.173.12:02:14.46#ibcon#about to read 3, iclass 13, count 2 2006.173.12:02:14.49#ibcon#read 3, iclass 13, count 2 2006.173.12:02:14.49#ibcon#about to read 4, iclass 13, count 2 2006.173.12:02:14.49#ibcon#read 4, iclass 13, count 2 2006.173.12:02:14.49#ibcon#about to read 5, iclass 13, count 2 2006.173.12:02:14.49#ibcon#read 5, iclass 13, count 2 2006.173.12:02:14.49#ibcon#about to read 6, iclass 13, count 2 2006.173.12:02:14.49#ibcon#read 6, iclass 13, count 2 2006.173.12:02:14.49#ibcon#end of sib2, iclass 13, count 2 2006.173.12:02:14.49#ibcon#*after write, iclass 13, count 2 2006.173.12:02:14.49#ibcon#*before return 0, iclass 13, count 2 2006.173.12:02:14.49#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.12:02:14.49#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.173.12:02:14.49#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.173.12:02:14.49#ibcon#ireg 7 cls_cnt 0 2006.173.12:02:14.49#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.12:02:14.61#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.12:02:14.61#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.12:02:14.61#ibcon#enter wrdev, iclass 13, count 0 2006.173.12:02:14.61#ibcon#first serial, iclass 13, count 0 2006.173.12:02:14.61#ibcon#enter sib2, iclass 13, count 0 2006.173.12:02:14.61#ibcon#flushed, iclass 13, count 0 2006.173.12:02:14.61#ibcon#about to write, iclass 13, count 0 2006.173.12:02:14.61#ibcon#wrote, iclass 13, count 0 2006.173.12:02:14.61#ibcon#about to read 3, iclass 13, count 0 2006.173.12:02:14.63#ibcon#read 3, iclass 13, count 0 2006.173.12:02:14.63#ibcon#about to read 4, iclass 13, count 0 2006.173.12:02:14.63#ibcon#read 4, iclass 13, count 0 2006.173.12:02:14.63#ibcon#about to read 5, iclass 13, count 0 2006.173.12:02:14.63#ibcon#read 5, iclass 13, count 0 2006.173.12:02:14.63#ibcon#about to read 6, iclass 13, count 0 2006.173.12:02:14.63#ibcon#read 6, iclass 13, count 0 2006.173.12:02:14.63#ibcon#end of sib2, iclass 13, count 0 2006.173.12:02:14.63#ibcon#*mode == 0, iclass 13, count 0 2006.173.12:02:14.63#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.12:02:14.63#ibcon#[27=USB\r\n] 2006.173.12:02:14.63#ibcon#*before write, iclass 13, count 0 2006.173.12:02:14.63#ibcon#enter sib2, iclass 13, count 0 2006.173.12:02:14.63#ibcon#flushed, iclass 13, count 0 2006.173.12:02:14.63#ibcon#about to write, iclass 13, count 0 2006.173.12:02:14.63#ibcon#wrote, iclass 13, count 0 2006.173.12:02:14.63#ibcon#about to read 3, iclass 13, count 0 2006.173.12:02:14.66#ibcon#read 3, iclass 13, count 0 2006.173.12:02:14.66#ibcon#about to read 4, iclass 13, count 0 2006.173.12:02:14.66#ibcon#read 4, iclass 13, count 0 2006.173.12:02:14.66#ibcon#about to read 5, iclass 13, count 0 2006.173.12:02:14.66#ibcon#read 5, iclass 13, count 0 2006.173.12:02:14.66#ibcon#about to read 6, iclass 13, count 0 2006.173.12:02:14.66#ibcon#read 6, iclass 13, count 0 2006.173.12:02:14.66#ibcon#end of sib2, iclass 13, count 0 2006.173.12:02:14.66#ibcon#*after write, iclass 13, count 0 2006.173.12:02:14.66#ibcon#*before return 0, iclass 13, count 0 2006.173.12:02:14.66#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.12:02:14.66#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.173.12:02:14.66#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.12:02:14.66#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.12:02:14.66$vck44/vabw=wide 2006.173.12:02:14.66#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.12:02:14.66#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.12:02:14.66#ibcon#ireg 8 cls_cnt 0 2006.173.12:02:14.66#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.12:02:14.66#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.12:02:14.66#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.12:02:14.66#ibcon#enter wrdev, iclass 15, count 0 2006.173.12:02:14.66#ibcon#first serial, iclass 15, count 0 2006.173.12:02:14.66#ibcon#enter sib2, iclass 15, count 0 2006.173.12:02:14.66#ibcon#flushed, iclass 15, count 0 2006.173.12:02:14.66#ibcon#about to write, iclass 15, count 0 2006.173.12:02:14.66#ibcon#wrote, iclass 15, count 0 2006.173.12:02:14.66#ibcon#about to read 3, iclass 15, count 0 2006.173.12:02:14.68#ibcon#read 3, iclass 15, count 0 2006.173.12:02:14.68#ibcon#about to read 4, iclass 15, count 0 2006.173.12:02:14.68#ibcon#read 4, iclass 15, count 0 2006.173.12:02:14.68#ibcon#about to read 5, iclass 15, count 0 2006.173.12:02:14.68#ibcon#read 5, iclass 15, count 0 2006.173.12:02:14.68#ibcon#about to read 6, iclass 15, count 0 2006.173.12:02:14.68#ibcon#read 6, iclass 15, count 0 2006.173.12:02:14.68#ibcon#end of sib2, iclass 15, count 0 2006.173.12:02:14.68#ibcon#*mode == 0, iclass 15, count 0 2006.173.12:02:14.68#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.12:02:14.68#ibcon#[25=BW32\r\n] 2006.173.12:02:14.68#ibcon#*before write, iclass 15, count 0 2006.173.12:02:14.68#ibcon#enter sib2, iclass 15, count 0 2006.173.12:02:14.68#ibcon#flushed, iclass 15, count 0 2006.173.12:02:14.68#ibcon#about to write, iclass 15, count 0 2006.173.12:02:14.68#ibcon#wrote, iclass 15, count 0 2006.173.12:02:14.68#ibcon#about to read 3, iclass 15, count 0 2006.173.12:02:14.71#ibcon#read 3, iclass 15, count 0 2006.173.12:02:14.71#ibcon#about to read 4, iclass 15, count 0 2006.173.12:02:14.71#ibcon#read 4, iclass 15, count 0 2006.173.12:02:14.71#ibcon#about to read 5, iclass 15, count 0 2006.173.12:02:14.71#ibcon#read 5, iclass 15, count 0 2006.173.12:02:14.71#ibcon#about to read 6, iclass 15, count 0 2006.173.12:02:14.71#ibcon#read 6, iclass 15, count 0 2006.173.12:02:14.71#ibcon#end of sib2, iclass 15, count 0 2006.173.12:02:14.71#ibcon#*after write, iclass 15, count 0 2006.173.12:02:14.71#ibcon#*before return 0, iclass 15, count 0 2006.173.12:02:14.71#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.12:02:14.71#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.12:02:14.71#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.12:02:14.71#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.12:02:14.71$vck44/vbbw=wide 2006.173.12:02:14.71#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.12:02:14.71#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.12:02:14.71#ibcon#ireg 8 cls_cnt 0 2006.173.12:02:14.71#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.12:02:14.78#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.12:02:14.78#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.12:02:14.78#ibcon#enter wrdev, iclass 17, count 0 2006.173.12:02:14.78#ibcon#first serial, iclass 17, count 0 2006.173.12:02:14.78#ibcon#enter sib2, iclass 17, count 0 2006.173.12:02:14.78#ibcon#flushed, iclass 17, count 0 2006.173.12:02:14.78#ibcon#about to write, iclass 17, count 0 2006.173.12:02:14.78#ibcon#wrote, iclass 17, count 0 2006.173.12:02:14.78#ibcon#about to read 3, iclass 17, count 0 2006.173.12:02:14.80#ibcon#read 3, iclass 17, count 0 2006.173.12:02:14.80#ibcon#about to read 4, iclass 17, count 0 2006.173.12:02:14.80#ibcon#read 4, iclass 17, count 0 2006.173.12:02:14.80#ibcon#about to read 5, iclass 17, count 0 2006.173.12:02:14.80#ibcon#read 5, iclass 17, count 0 2006.173.12:02:14.80#ibcon#about to read 6, iclass 17, count 0 2006.173.12:02:14.80#ibcon#read 6, iclass 17, count 0 2006.173.12:02:14.80#ibcon#end of sib2, iclass 17, count 0 2006.173.12:02:14.80#ibcon#*mode == 0, iclass 17, count 0 2006.173.12:02:14.80#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.12:02:14.80#ibcon#[27=BW32\r\n] 2006.173.12:02:14.80#ibcon#*before write, iclass 17, count 0 2006.173.12:02:14.80#ibcon#enter sib2, iclass 17, count 0 2006.173.12:02:14.80#ibcon#flushed, iclass 17, count 0 2006.173.12:02:14.80#ibcon#about to write, iclass 17, count 0 2006.173.12:02:14.80#ibcon#wrote, iclass 17, count 0 2006.173.12:02:14.80#ibcon#about to read 3, iclass 17, count 0 2006.173.12:02:14.83#ibcon#read 3, iclass 17, count 0 2006.173.12:02:14.83#ibcon#about to read 4, iclass 17, count 0 2006.173.12:02:14.83#ibcon#read 4, iclass 17, count 0 2006.173.12:02:14.83#ibcon#about to read 5, iclass 17, count 0 2006.173.12:02:14.83#ibcon#read 5, iclass 17, count 0 2006.173.12:02:14.83#ibcon#about to read 6, iclass 17, count 0 2006.173.12:02:14.83#ibcon#read 6, iclass 17, count 0 2006.173.12:02:14.83#ibcon#end of sib2, iclass 17, count 0 2006.173.12:02:14.83#ibcon#*after write, iclass 17, count 0 2006.173.12:02:14.83#ibcon#*before return 0, iclass 17, count 0 2006.173.12:02:14.83#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.12:02:14.83#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.12:02:14.83#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.12:02:14.83#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.12:02:14.83$setupk4/ifdk4 2006.173.12:02:14.83$ifdk4/lo= 2006.173.12:02:14.83$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.12:02:14.83$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.12:02:14.83$ifdk4/patch= 2006.173.12:02:14.83$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.12:02:14.83$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.12:02:14.83$setupk4/!*+20s 2006.173.12:02:21.10#abcon#<5=/07 1.2 2.2 22.20 951004.1\r\n> 2006.173.12:02:21.12#abcon#{5=INTERFACE CLEAR} 2006.173.12:02:21.18#abcon#[5=S1D000X0/0*\r\n] 2006.173.12:02:29.33$setupk4/"tpicd 2006.173.12:02:29.33$setupk4/echo=off 2006.173.12:02:29.33$setupk4/xlog=off 2006.173.12:02:29.33:!2006.173.12:03:59 2006.173.12:03:34.14#trakl#Source acquired 2006.173.12:03:35.14#flagr#flagr/antenna,acquired 2006.173.12:03:59.00:preob 2006.173.12:04:00.14/onsource/TRACKING 2006.173.12:04:00.14:!2006.173.12:04:09 2006.173.12:04:09.00:"tape 2006.173.12:04:09.00:"st=record 2006.173.12:04:09.00:data_valid=on 2006.173.12:04:09.00:midob 2006.173.12:04:09.13/onsource/TRACKING 2006.173.12:04:09.13/wx/22.20,1004.2,95 2006.173.12:04:09.30/cable/+6.5026E-03 2006.173.12:04:10.39/va/01,07,usb,yes,48,52 2006.173.12:04:10.39/va/02,06,usb,yes,48,49 2006.173.12:04:10.39/va/03,05,usb,yes,61,63 2006.173.12:04:10.39/va/04,06,usb,yes,49,52 2006.173.12:04:10.39/va/05,04,usb,yes,39,40 2006.173.12:04:10.39/va/06,03,usb,yes,54,54 2006.173.12:04:10.39/va/07,04,usb,yes,44,46 2006.173.12:04:10.39/va/08,04,usb,yes,38,45 2006.173.12:04:10.62/valo/01,524.99,yes,locked 2006.173.12:04:10.62/valo/02,534.99,yes,locked 2006.173.12:04:10.62/valo/03,564.99,yes,locked 2006.173.12:04:10.62/valo/04,624.99,yes,locked 2006.173.12:04:10.62/valo/05,734.99,yes,locked 2006.173.12:04:10.62/valo/06,814.99,yes,locked 2006.173.12:04:10.62/valo/07,864.99,yes,locked 2006.173.12:04:10.62/valo/08,884.99,yes,locked 2006.173.12:04:11.71/vb/01,04,usb,yes,37,96 2006.173.12:04:11.71/vb/02,04,usb,yes,34,91 2006.173.12:04:11.71/vb/03,04,usb,yes,31,59 2006.173.12:04:11.71/vb/04,04,usb,yes,35,34 2006.173.12:04:11.71/vb/05,04,usb,yes,29,31 2006.173.12:04:11.71/vb/06,04,usb,yes,34,30 2006.173.12:04:11.71/vb/07,04,usb,yes,32,32 2006.173.12:04:11.71/vb/08,04,usb,yes,30,33 2006.173.12:04:11.94/vblo/01,629.99,yes,locked 2006.173.12:04:11.94/vblo/02,634.99,yes,locked 2006.173.12:04:11.94/vblo/03,649.99,yes,locked 2006.173.12:04:11.94/vblo/04,679.99,yes,locked 2006.173.12:04:11.94/vblo/05,709.99,yes,locked 2006.173.12:04:11.94/vblo/06,719.99,yes,locked 2006.173.12:04:11.94/vblo/07,734.99,yes,locked 2006.173.12:04:11.94/vblo/08,744.99,yes,locked 2006.173.12:04:12.09/vabw/8 2006.173.12:04:12.24/vbbw/8 2006.173.12:04:12.36/xfe/off,on,14.7 2006.173.12:04:12.75/ifatt/23,28,28,28 2006.173.12:04:13.07/fmout-gps/S +3.95E-07 2006.173.12:04:13.11:!2006.173.12:09:29 2006.173.12:09:29.00:data_valid=off 2006.173.12:09:29.00:"et 2006.173.12:09:29.00:!+3s 2006.173.12:09:32.01:"tape 2006.173.12:09:32.01:postob 2006.173.12:09:32.16/cable/+6.5018E-03 2006.173.12:09:32.16/wx/22.20,1004.2,95 2006.173.12:09:33.08/fmout-gps/S +3.97E-07 2006.173.12:09:33.08:scan_name=173-1210,jd0606,40 2006.173.12:09:33.08:source=1908-201,191109.65,-200655.1,2000.0,cw 2006.173.12:09:33.14#flagr#flagr/antenna,new-source 2006.173.12:09:34.14:checkk5 2006.173.12:09:34.54/chk_autoobs//k5ts1/ autoobs is running! 2006.173.12:09:34.94/chk_autoobs//k5ts2/ autoobs is running! 2006.173.12:09:35.34/chk_autoobs//k5ts3/ autoobs is running! 2006.173.12:09:35.74/chk_autoobs//k5ts4/ autoobs is running! 2006.173.12:09:36.12/chk_obsdata//k5ts1/T1731204??a.dat file size is correct (nominal:1280MB, actual:1276MB). 2006.173.12:09:36.52/chk_obsdata//k5ts2/T1731204??b.dat file size is correct (nominal:1280MB, actual:1276MB). 2006.173.12:09:36.92/chk_obsdata//k5ts3/T1731204??c.dat file size is correct (nominal:1280MB, actual:1276MB). 2006.173.12:09:37.33/chk_obsdata//k5ts4/T1731204??d.dat file size is correct (nominal:1280MB, actual:1276MB). 2006.173.12:09:38.06/k5log//k5ts1_log_newline 2006.173.12:09:38.78/k5log//k5ts2_log_newline 2006.173.12:09:39.49/k5log//k5ts3_log_newline 2006.173.12:09:40.20/k5log//k5ts4_log_newline 2006.173.12:09:40.22/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.12:09:40.22:setupk4=1 2006.173.12:09:40.22$setupk4/echo=on 2006.173.12:09:40.22$setupk4/pcalon 2006.173.12:09:40.22$pcalon/"no phase cal control is implemented here 2006.173.12:09:40.22$setupk4/"tpicd=stop 2006.173.12:09:40.22$setupk4/"rec=synch_on 2006.173.12:09:40.22$setupk4/"rec_mode=128 2006.173.12:09:40.22$setupk4/!* 2006.173.12:09:40.22$setupk4/recpk4 2006.173.12:09:40.22$recpk4/recpatch= 2006.173.12:09:40.23$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.12:09:40.23$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.12:09:40.23$setupk4/vck44 2006.173.12:09:40.23$vck44/valo=1,524.99 2006.173.12:09:40.23#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.12:09:40.23#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.12:09:40.23#ibcon#ireg 17 cls_cnt 0 2006.173.12:09:40.23#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.12:09:40.23#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.12:09:40.23#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.12:09:40.23#ibcon#enter wrdev, iclass 18, count 0 2006.173.12:09:40.23#ibcon#first serial, iclass 18, count 0 2006.173.12:09:40.23#ibcon#enter sib2, iclass 18, count 0 2006.173.12:09:40.23#ibcon#flushed, iclass 18, count 0 2006.173.12:09:40.23#ibcon#about to write, iclass 18, count 0 2006.173.12:09:40.23#ibcon#wrote, iclass 18, count 0 2006.173.12:09:40.23#ibcon#about to read 3, iclass 18, count 0 2006.173.12:09:40.25#ibcon#read 3, iclass 18, count 0 2006.173.12:09:40.25#ibcon#about to read 4, iclass 18, count 0 2006.173.12:09:40.25#ibcon#read 4, iclass 18, count 0 2006.173.12:09:40.25#ibcon#about to read 5, iclass 18, count 0 2006.173.12:09:40.25#ibcon#read 5, iclass 18, count 0 2006.173.12:09:40.25#ibcon#about to read 6, iclass 18, count 0 2006.173.12:09:40.25#ibcon#read 6, iclass 18, count 0 2006.173.12:09:40.25#ibcon#end of sib2, iclass 18, count 0 2006.173.12:09:40.25#ibcon#*mode == 0, iclass 18, count 0 2006.173.12:09:40.25#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.12:09:40.25#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.12:09:40.25#ibcon#*before write, iclass 18, count 0 2006.173.12:09:40.25#ibcon#enter sib2, iclass 18, count 0 2006.173.12:09:40.25#ibcon#flushed, iclass 18, count 0 2006.173.12:09:40.25#ibcon#about to write, iclass 18, count 0 2006.173.12:09:40.25#ibcon#wrote, iclass 18, count 0 2006.173.12:09:40.25#ibcon#about to read 3, iclass 18, count 0 2006.173.12:09:40.30#ibcon#read 3, iclass 18, count 0 2006.173.12:09:40.30#ibcon#about to read 4, iclass 18, count 0 2006.173.12:09:40.30#ibcon#read 4, iclass 18, count 0 2006.173.12:09:40.30#ibcon#about to read 5, iclass 18, count 0 2006.173.12:09:40.30#ibcon#read 5, iclass 18, count 0 2006.173.12:09:40.30#ibcon#about to read 6, iclass 18, count 0 2006.173.12:09:40.30#ibcon#read 6, iclass 18, count 0 2006.173.12:09:40.30#ibcon#end of sib2, iclass 18, count 0 2006.173.12:09:40.30#ibcon#*after write, iclass 18, count 0 2006.173.12:09:40.30#ibcon#*before return 0, iclass 18, count 0 2006.173.12:09:40.30#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.12:09:40.30#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.12:09:40.30#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.12:09:40.30#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.12:09:40.30$vck44/va=1,7 2006.173.12:09:40.30#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.12:09:40.30#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.12:09:40.30#ibcon#ireg 11 cls_cnt 2 2006.173.12:09:40.30#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.12:09:40.30#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.12:09:40.30#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.12:09:40.30#ibcon#enter wrdev, iclass 20, count 2 2006.173.12:09:40.30#ibcon#first serial, iclass 20, count 2 2006.173.12:09:40.30#ibcon#enter sib2, iclass 20, count 2 2006.173.12:09:40.30#ibcon#flushed, iclass 20, count 2 2006.173.12:09:40.30#ibcon#about to write, iclass 20, count 2 2006.173.12:09:40.30#ibcon#wrote, iclass 20, count 2 2006.173.12:09:40.30#ibcon#about to read 3, iclass 20, count 2 2006.173.12:09:40.32#ibcon#read 3, iclass 20, count 2 2006.173.12:09:40.32#ibcon#about to read 4, iclass 20, count 2 2006.173.12:09:40.32#ibcon#read 4, iclass 20, count 2 2006.173.12:09:40.32#ibcon#about to read 5, iclass 20, count 2 2006.173.12:09:40.32#ibcon#read 5, iclass 20, count 2 2006.173.12:09:40.32#ibcon#about to read 6, iclass 20, count 2 2006.173.12:09:40.32#ibcon#read 6, iclass 20, count 2 2006.173.12:09:40.32#ibcon#end of sib2, iclass 20, count 2 2006.173.12:09:40.32#ibcon#*mode == 0, iclass 20, count 2 2006.173.12:09:40.32#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.12:09:40.32#ibcon#[25=AT01-07\r\n] 2006.173.12:09:40.32#ibcon#*before write, iclass 20, count 2 2006.173.12:09:40.32#ibcon#enter sib2, iclass 20, count 2 2006.173.12:09:40.32#ibcon#flushed, iclass 20, count 2 2006.173.12:09:40.32#ibcon#about to write, iclass 20, count 2 2006.173.12:09:40.32#ibcon#wrote, iclass 20, count 2 2006.173.12:09:40.32#ibcon#about to read 3, iclass 20, count 2 2006.173.12:09:40.35#ibcon#read 3, iclass 20, count 2 2006.173.12:09:40.35#ibcon#about to read 4, iclass 20, count 2 2006.173.12:09:40.35#ibcon#read 4, iclass 20, count 2 2006.173.12:09:40.35#ibcon#about to read 5, iclass 20, count 2 2006.173.12:09:40.35#ibcon#read 5, iclass 20, count 2 2006.173.12:09:40.35#ibcon#about to read 6, iclass 20, count 2 2006.173.12:09:40.35#ibcon#read 6, iclass 20, count 2 2006.173.12:09:40.35#ibcon#end of sib2, iclass 20, count 2 2006.173.12:09:40.35#ibcon#*after write, iclass 20, count 2 2006.173.12:09:40.35#ibcon#*before return 0, iclass 20, count 2 2006.173.12:09:40.35#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.12:09:40.35#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.12:09:40.35#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.12:09:40.35#ibcon#ireg 7 cls_cnt 0 2006.173.12:09:40.35#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.12:09:40.47#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.12:09:40.47#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.12:09:40.47#ibcon#enter wrdev, iclass 20, count 0 2006.173.12:09:40.47#ibcon#first serial, iclass 20, count 0 2006.173.12:09:40.47#ibcon#enter sib2, iclass 20, count 0 2006.173.12:09:40.47#ibcon#flushed, iclass 20, count 0 2006.173.12:09:40.47#ibcon#about to write, iclass 20, count 0 2006.173.12:09:40.47#ibcon#wrote, iclass 20, count 0 2006.173.12:09:40.47#ibcon#about to read 3, iclass 20, count 0 2006.173.12:09:40.49#ibcon#read 3, iclass 20, count 0 2006.173.12:09:40.49#ibcon#about to read 4, iclass 20, count 0 2006.173.12:09:40.49#ibcon#read 4, iclass 20, count 0 2006.173.12:09:40.49#ibcon#about to read 5, iclass 20, count 0 2006.173.12:09:40.49#ibcon#read 5, iclass 20, count 0 2006.173.12:09:40.49#ibcon#about to read 6, iclass 20, count 0 2006.173.12:09:40.49#ibcon#read 6, iclass 20, count 0 2006.173.12:09:40.49#ibcon#end of sib2, iclass 20, count 0 2006.173.12:09:40.49#ibcon#*mode == 0, iclass 20, count 0 2006.173.12:09:40.49#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.12:09:40.49#ibcon#[25=USB\r\n] 2006.173.12:09:40.49#ibcon#*before write, iclass 20, count 0 2006.173.12:09:40.49#ibcon#enter sib2, iclass 20, count 0 2006.173.12:09:40.49#ibcon#flushed, iclass 20, count 0 2006.173.12:09:40.49#ibcon#about to write, iclass 20, count 0 2006.173.12:09:40.49#ibcon#wrote, iclass 20, count 0 2006.173.12:09:40.49#ibcon#about to read 3, iclass 20, count 0 2006.173.12:09:40.52#ibcon#read 3, iclass 20, count 0 2006.173.12:09:40.52#ibcon#about to read 4, iclass 20, count 0 2006.173.12:09:40.52#ibcon#read 4, iclass 20, count 0 2006.173.12:09:40.52#ibcon#about to read 5, iclass 20, count 0 2006.173.12:09:40.52#ibcon#read 5, iclass 20, count 0 2006.173.12:09:40.52#ibcon#about to read 6, iclass 20, count 0 2006.173.12:09:40.52#ibcon#read 6, iclass 20, count 0 2006.173.12:09:40.52#ibcon#end of sib2, iclass 20, count 0 2006.173.12:09:40.52#ibcon#*after write, iclass 20, count 0 2006.173.12:09:40.52#ibcon#*before return 0, iclass 20, count 0 2006.173.12:09:40.52#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.12:09:40.52#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.12:09:40.52#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.12:09:40.52#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.12:09:40.52$vck44/valo=2,534.99 2006.173.12:09:40.52#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.12:09:40.52#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.12:09:40.52#ibcon#ireg 17 cls_cnt 0 2006.173.12:09:40.52#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.12:09:40.52#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.12:09:40.52#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.12:09:40.52#ibcon#enter wrdev, iclass 22, count 0 2006.173.12:09:40.52#ibcon#first serial, iclass 22, count 0 2006.173.12:09:40.52#ibcon#enter sib2, iclass 22, count 0 2006.173.12:09:40.52#ibcon#flushed, iclass 22, count 0 2006.173.12:09:40.52#ibcon#about to write, iclass 22, count 0 2006.173.12:09:40.52#ibcon#wrote, iclass 22, count 0 2006.173.12:09:40.52#ibcon#about to read 3, iclass 22, count 0 2006.173.12:09:40.54#ibcon#read 3, iclass 22, count 0 2006.173.12:09:40.54#ibcon#about to read 4, iclass 22, count 0 2006.173.12:09:40.54#ibcon#read 4, iclass 22, count 0 2006.173.12:09:40.54#ibcon#about to read 5, iclass 22, count 0 2006.173.12:09:40.54#ibcon#read 5, iclass 22, count 0 2006.173.12:09:40.54#ibcon#about to read 6, iclass 22, count 0 2006.173.12:09:40.54#ibcon#read 6, iclass 22, count 0 2006.173.12:09:40.54#ibcon#end of sib2, iclass 22, count 0 2006.173.12:09:40.54#ibcon#*mode == 0, iclass 22, count 0 2006.173.12:09:40.54#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.12:09:40.54#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.12:09:40.54#ibcon#*before write, iclass 22, count 0 2006.173.12:09:40.54#ibcon#enter sib2, iclass 22, count 0 2006.173.12:09:40.54#ibcon#flushed, iclass 22, count 0 2006.173.12:09:40.54#ibcon#about to write, iclass 22, count 0 2006.173.12:09:40.54#ibcon#wrote, iclass 22, count 0 2006.173.12:09:40.54#ibcon#about to read 3, iclass 22, count 0 2006.173.12:09:40.58#ibcon#read 3, iclass 22, count 0 2006.173.12:09:40.58#ibcon#about to read 4, iclass 22, count 0 2006.173.12:09:40.58#ibcon#read 4, iclass 22, count 0 2006.173.12:09:40.58#ibcon#about to read 5, iclass 22, count 0 2006.173.12:09:40.58#ibcon#read 5, iclass 22, count 0 2006.173.12:09:40.58#ibcon#about to read 6, iclass 22, count 0 2006.173.12:09:40.58#ibcon#read 6, iclass 22, count 0 2006.173.12:09:40.58#ibcon#end of sib2, iclass 22, count 0 2006.173.12:09:40.58#ibcon#*after write, iclass 22, count 0 2006.173.12:09:40.58#ibcon#*before return 0, iclass 22, count 0 2006.173.12:09:40.58#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.12:09:40.58#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.12:09:40.58#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.12:09:40.58#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.12:09:40.58$vck44/va=2,6 2006.173.12:09:40.58#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.12:09:40.58#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.12:09:40.58#ibcon#ireg 11 cls_cnt 2 2006.173.12:09:40.58#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.12:09:40.64#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.12:09:40.64#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.12:09:40.64#ibcon#enter wrdev, iclass 24, count 2 2006.173.12:09:40.64#ibcon#first serial, iclass 24, count 2 2006.173.12:09:40.64#ibcon#enter sib2, iclass 24, count 2 2006.173.12:09:40.64#ibcon#flushed, iclass 24, count 2 2006.173.12:09:40.64#ibcon#about to write, iclass 24, count 2 2006.173.12:09:40.64#ibcon#wrote, iclass 24, count 2 2006.173.12:09:40.64#ibcon#about to read 3, iclass 24, count 2 2006.173.12:09:40.66#ibcon#read 3, iclass 24, count 2 2006.173.12:09:40.66#ibcon#about to read 4, iclass 24, count 2 2006.173.12:09:40.66#ibcon#read 4, iclass 24, count 2 2006.173.12:09:40.66#ibcon#about to read 5, iclass 24, count 2 2006.173.12:09:40.66#ibcon#read 5, iclass 24, count 2 2006.173.12:09:40.66#ibcon#about to read 6, iclass 24, count 2 2006.173.12:09:40.66#ibcon#read 6, iclass 24, count 2 2006.173.12:09:40.66#ibcon#end of sib2, iclass 24, count 2 2006.173.12:09:40.66#ibcon#*mode == 0, iclass 24, count 2 2006.173.12:09:40.66#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.12:09:40.66#ibcon#[25=AT02-06\r\n] 2006.173.12:09:40.66#ibcon#*before write, iclass 24, count 2 2006.173.12:09:40.66#ibcon#enter sib2, iclass 24, count 2 2006.173.12:09:40.66#ibcon#flushed, iclass 24, count 2 2006.173.12:09:40.66#ibcon#about to write, iclass 24, count 2 2006.173.12:09:40.66#ibcon#wrote, iclass 24, count 2 2006.173.12:09:40.66#ibcon#about to read 3, iclass 24, count 2 2006.173.12:09:40.69#ibcon#read 3, iclass 24, count 2 2006.173.12:09:40.69#ibcon#about to read 4, iclass 24, count 2 2006.173.12:09:40.69#ibcon#read 4, iclass 24, count 2 2006.173.12:09:40.69#ibcon#about to read 5, iclass 24, count 2 2006.173.12:09:40.69#ibcon#read 5, iclass 24, count 2 2006.173.12:09:40.69#ibcon#about to read 6, iclass 24, count 2 2006.173.12:09:40.69#ibcon#read 6, iclass 24, count 2 2006.173.12:09:40.69#ibcon#end of sib2, iclass 24, count 2 2006.173.12:09:40.69#ibcon#*after write, iclass 24, count 2 2006.173.12:09:40.69#ibcon#*before return 0, iclass 24, count 2 2006.173.12:09:40.69#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.12:09:40.69#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.12:09:40.69#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.12:09:40.69#ibcon#ireg 7 cls_cnt 0 2006.173.12:09:40.69#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.12:09:40.81#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.12:09:40.81#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.12:09:40.81#ibcon#enter wrdev, iclass 24, count 0 2006.173.12:09:40.81#ibcon#first serial, iclass 24, count 0 2006.173.12:09:40.81#ibcon#enter sib2, iclass 24, count 0 2006.173.12:09:40.81#ibcon#flushed, iclass 24, count 0 2006.173.12:09:40.81#ibcon#about to write, iclass 24, count 0 2006.173.12:09:40.81#ibcon#wrote, iclass 24, count 0 2006.173.12:09:40.81#ibcon#about to read 3, iclass 24, count 0 2006.173.12:09:40.83#ibcon#read 3, iclass 24, count 0 2006.173.12:09:40.83#ibcon#about to read 4, iclass 24, count 0 2006.173.12:09:40.83#ibcon#read 4, iclass 24, count 0 2006.173.12:09:40.83#ibcon#about to read 5, iclass 24, count 0 2006.173.12:09:40.83#ibcon#read 5, iclass 24, count 0 2006.173.12:09:40.83#ibcon#about to read 6, iclass 24, count 0 2006.173.12:09:40.83#ibcon#read 6, iclass 24, count 0 2006.173.12:09:40.83#ibcon#end of sib2, iclass 24, count 0 2006.173.12:09:40.83#ibcon#*mode == 0, iclass 24, count 0 2006.173.12:09:40.83#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.12:09:40.83#ibcon#[25=USB\r\n] 2006.173.12:09:40.83#ibcon#*before write, iclass 24, count 0 2006.173.12:09:40.83#ibcon#enter sib2, iclass 24, count 0 2006.173.12:09:40.83#ibcon#flushed, iclass 24, count 0 2006.173.12:09:40.83#ibcon#about to write, iclass 24, count 0 2006.173.12:09:40.83#ibcon#wrote, iclass 24, count 0 2006.173.12:09:40.83#ibcon#about to read 3, iclass 24, count 0 2006.173.12:09:40.86#ibcon#read 3, iclass 24, count 0 2006.173.12:09:40.86#ibcon#about to read 4, iclass 24, count 0 2006.173.12:09:40.86#ibcon#read 4, iclass 24, count 0 2006.173.12:09:40.86#ibcon#about to read 5, iclass 24, count 0 2006.173.12:09:40.86#ibcon#read 5, iclass 24, count 0 2006.173.12:09:40.86#ibcon#about to read 6, iclass 24, count 0 2006.173.12:09:40.86#ibcon#read 6, iclass 24, count 0 2006.173.12:09:40.86#ibcon#end of sib2, iclass 24, count 0 2006.173.12:09:40.86#ibcon#*after write, iclass 24, count 0 2006.173.12:09:40.86#ibcon#*before return 0, iclass 24, count 0 2006.173.12:09:40.86#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.12:09:40.86#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.12:09:40.86#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.12:09:40.86#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.12:09:40.86$vck44/valo=3,564.99 2006.173.12:09:40.86#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.12:09:40.86#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.12:09:40.86#ibcon#ireg 17 cls_cnt 0 2006.173.12:09:40.86#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.12:09:40.86#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.12:09:40.86#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.12:09:40.86#ibcon#enter wrdev, iclass 26, count 0 2006.173.12:09:40.86#ibcon#first serial, iclass 26, count 0 2006.173.12:09:40.86#ibcon#enter sib2, iclass 26, count 0 2006.173.12:09:40.86#ibcon#flushed, iclass 26, count 0 2006.173.12:09:40.86#ibcon#about to write, iclass 26, count 0 2006.173.12:09:40.86#ibcon#wrote, iclass 26, count 0 2006.173.12:09:40.86#ibcon#about to read 3, iclass 26, count 0 2006.173.12:09:40.88#ibcon#read 3, iclass 26, count 0 2006.173.12:09:40.88#ibcon#about to read 4, iclass 26, count 0 2006.173.12:09:40.88#ibcon#read 4, iclass 26, count 0 2006.173.12:09:40.88#ibcon#about to read 5, iclass 26, count 0 2006.173.12:09:40.88#ibcon#read 5, iclass 26, count 0 2006.173.12:09:40.88#ibcon#about to read 6, iclass 26, count 0 2006.173.12:09:40.88#ibcon#read 6, iclass 26, count 0 2006.173.12:09:40.88#ibcon#end of sib2, iclass 26, count 0 2006.173.12:09:40.88#ibcon#*mode == 0, iclass 26, count 0 2006.173.12:09:40.88#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.12:09:40.88#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.12:09:40.88#ibcon#*before write, iclass 26, count 0 2006.173.12:09:40.88#ibcon#enter sib2, iclass 26, count 0 2006.173.12:09:40.88#ibcon#flushed, iclass 26, count 0 2006.173.12:09:40.88#ibcon#about to write, iclass 26, count 0 2006.173.12:09:40.88#ibcon#wrote, iclass 26, count 0 2006.173.12:09:40.88#ibcon#about to read 3, iclass 26, count 0 2006.173.12:09:40.92#ibcon#read 3, iclass 26, count 0 2006.173.12:09:40.92#ibcon#about to read 4, iclass 26, count 0 2006.173.12:09:40.92#ibcon#read 4, iclass 26, count 0 2006.173.12:09:40.92#ibcon#about to read 5, iclass 26, count 0 2006.173.12:09:40.92#ibcon#read 5, iclass 26, count 0 2006.173.12:09:40.92#ibcon#about to read 6, iclass 26, count 0 2006.173.12:09:40.92#ibcon#read 6, iclass 26, count 0 2006.173.12:09:40.92#ibcon#end of sib2, iclass 26, count 0 2006.173.12:09:40.92#ibcon#*after write, iclass 26, count 0 2006.173.12:09:40.92#ibcon#*before return 0, iclass 26, count 0 2006.173.12:09:40.92#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.12:09:40.92#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.12:09:40.92#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.12:09:40.92#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.12:09:40.92$vck44/va=3,5 2006.173.12:09:40.92#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.12:09:40.92#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.12:09:40.92#ibcon#ireg 11 cls_cnt 2 2006.173.12:09:40.92#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.12:09:40.98#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.12:09:40.98#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.12:09:40.98#ibcon#enter wrdev, iclass 28, count 2 2006.173.12:09:40.98#ibcon#first serial, iclass 28, count 2 2006.173.12:09:40.98#ibcon#enter sib2, iclass 28, count 2 2006.173.12:09:40.98#ibcon#flushed, iclass 28, count 2 2006.173.12:09:40.98#ibcon#about to write, iclass 28, count 2 2006.173.12:09:40.98#ibcon#wrote, iclass 28, count 2 2006.173.12:09:40.98#ibcon#about to read 3, iclass 28, count 2 2006.173.12:09:41.00#ibcon#read 3, iclass 28, count 2 2006.173.12:09:41.00#ibcon#about to read 4, iclass 28, count 2 2006.173.12:09:41.00#ibcon#read 4, iclass 28, count 2 2006.173.12:09:41.00#ibcon#about to read 5, iclass 28, count 2 2006.173.12:09:41.00#ibcon#read 5, iclass 28, count 2 2006.173.12:09:41.00#ibcon#about to read 6, iclass 28, count 2 2006.173.12:09:41.00#ibcon#read 6, iclass 28, count 2 2006.173.12:09:41.00#ibcon#end of sib2, iclass 28, count 2 2006.173.12:09:41.00#ibcon#*mode == 0, iclass 28, count 2 2006.173.12:09:41.00#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.12:09:41.00#ibcon#[25=AT03-05\r\n] 2006.173.12:09:41.00#ibcon#*before write, iclass 28, count 2 2006.173.12:09:41.00#ibcon#enter sib2, iclass 28, count 2 2006.173.12:09:41.00#ibcon#flushed, iclass 28, count 2 2006.173.12:09:41.00#ibcon#about to write, iclass 28, count 2 2006.173.12:09:41.00#ibcon#wrote, iclass 28, count 2 2006.173.12:09:41.00#ibcon#about to read 3, iclass 28, count 2 2006.173.12:09:41.03#ibcon#read 3, iclass 28, count 2 2006.173.12:09:41.03#ibcon#about to read 4, iclass 28, count 2 2006.173.12:09:41.03#ibcon#read 4, iclass 28, count 2 2006.173.12:09:41.03#ibcon#about to read 5, iclass 28, count 2 2006.173.12:09:41.03#ibcon#read 5, iclass 28, count 2 2006.173.12:09:41.03#ibcon#about to read 6, iclass 28, count 2 2006.173.12:09:41.03#ibcon#read 6, iclass 28, count 2 2006.173.12:09:41.03#ibcon#end of sib2, iclass 28, count 2 2006.173.12:09:41.03#ibcon#*after write, iclass 28, count 2 2006.173.12:09:41.03#ibcon#*before return 0, iclass 28, count 2 2006.173.12:09:41.03#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.12:09:41.03#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.12:09:41.03#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.12:09:41.03#ibcon#ireg 7 cls_cnt 0 2006.173.12:09:41.03#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.12:09:41.15#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.12:09:41.15#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.12:09:41.15#ibcon#enter wrdev, iclass 28, count 0 2006.173.12:09:41.15#ibcon#first serial, iclass 28, count 0 2006.173.12:09:41.15#ibcon#enter sib2, iclass 28, count 0 2006.173.12:09:41.15#ibcon#flushed, iclass 28, count 0 2006.173.12:09:41.15#ibcon#about to write, iclass 28, count 0 2006.173.12:09:41.15#ibcon#wrote, iclass 28, count 0 2006.173.12:09:41.15#ibcon#about to read 3, iclass 28, count 0 2006.173.12:09:41.17#ibcon#read 3, iclass 28, count 0 2006.173.12:09:41.17#ibcon#about to read 4, iclass 28, count 0 2006.173.12:09:41.17#ibcon#read 4, iclass 28, count 0 2006.173.12:09:41.17#ibcon#about to read 5, iclass 28, count 0 2006.173.12:09:41.17#ibcon#read 5, iclass 28, count 0 2006.173.12:09:41.17#ibcon#about to read 6, iclass 28, count 0 2006.173.12:09:41.17#ibcon#read 6, iclass 28, count 0 2006.173.12:09:41.17#ibcon#end of sib2, iclass 28, count 0 2006.173.12:09:41.17#ibcon#*mode == 0, iclass 28, count 0 2006.173.12:09:41.17#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.12:09:41.17#ibcon#[25=USB\r\n] 2006.173.12:09:41.17#ibcon#*before write, iclass 28, count 0 2006.173.12:09:41.17#ibcon#enter sib2, iclass 28, count 0 2006.173.12:09:41.17#ibcon#flushed, iclass 28, count 0 2006.173.12:09:41.17#ibcon#about to write, iclass 28, count 0 2006.173.12:09:41.17#ibcon#wrote, iclass 28, count 0 2006.173.12:09:41.17#ibcon#about to read 3, iclass 28, count 0 2006.173.12:09:41.20#ibcon#read 3, iclass 28, count 0 2006.173.12:09:41.20#ibcon#about to read 4, iclass 28, count 0 2006.173.12:09:41.20#ibcon#read 4, iclass 28, count 0 2006.173.12:09:41.20#ibcon#about to read 5, iclass 28, count 0 2006.173.12:09:41.20#ibcon#read 5, iclass 28, count 0 2006.173.12:09:41.20#ibcon#about to read 6, iclass 28, count 0 2006.173.12:09:41.20#ibcon#read 6, iclass 28, count 0 2006.173.12:09:41.20#ibcon#end of sib2, iclass 28, count 0 2006.173.12:09:41.20#ibcon#*after write, iclass 28, count 0 2006.173.12:09:41.20#ibcon#*before return 0, iclass 28, count 0 2006.173.12:09:41.20#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.12:09:41.20#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.12:09:41.20#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.12:09:41.20#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.12:09:41.20$vck44/valo=4,624.99 2006.173.12:09:41.20#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.12:09:41.20#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.12:09:41.20#ibcon#ireg 17 cls_cnt 0 2006.173.12:09:41.20#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.12:09:41.20#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.12:09:41.20#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.12:09:41.20#ibcon#enter wrdev, iclass 30, count 0 2006.173.12:09:41.20#ibcon#first serial, iclass 30, count 0 2006.173.12:09:41.20#ibcon#enter sib2, iclass 30, count 0 2006.173.12:09:41.20#ibcon#flushed, iclass 30, count 0 2006.173.12:09:41.20#ibcon#about to write, iclass 30, count 0 2006.173.12:09:41.20#ibcon#wrote, iclass 30, count 0 2006.173.12:09:41.20#ibcon#about to read 3, iclass 30, count 0 2006.173.12:09:41.22#ibcon#read 3, iclass 30, count 0 2006.173.12:09:41.22#ibcon#about to read 4, iclass 30, count 0 2006.173.12:09:41.22#ibcon#read 4, iclass 30, count 0 2006.173.12:09:41.22#ibcon#about to read 5, iclass 30, count 0 2006.173.12:09:41.22#ibcon#read 5, iclass 30, count 0 2006.173.12:09:41.22#ibcon#about to read 6, iclass 30, count 0 2006.173.12:09:41.22#ibcon#read 6, iclass 30, count 0 2006.173.12:09:41.22#ibcon#end of sib2, iclass 30, count 0 2006.173.12:09:41.22#ibcon#*mode == 0, iclass 30, count 0 2006.173.12:09:41.22#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.12:09:41.22#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.12:09:41.22#ibcon#*before write, iclass 30, count 0 2006.173.12:09:41.22#ibcon#enter sib2, iclass 30, count 0 2006.173.12:09:41.22#ibcon#flushed, iclass 30, count 0 2006.173.12:09:41.22#ibcon#about to write, iclass 30, count 0 2006.173.12:09:41.22#ibcon#wrote, iclass 30, count 0 2006.173.12:09:41.22#ibcon#about to read 3, iclass 30, count 0 2006.173.12:09:41.26#ibcon#read 3, iclass 30, count 0 2006.173.12:09:41.26#ibcon#about to read 4, iclass 30, count 0 2006.173.12:09:41.26#ibcon#read 4, iclass 30, count 0 2006.173.12:09:41.26#ibcon#about to read 5, iclass 30, count 0 2006.173.12:09:41.26#ibcon#read 5, iclass 30, count 0 2006.173.12:09:41.26#ibcon#about to read 6, iclass 30, count 0 2006.173.12:09:41.26#ibcon#read 6, iclass 30, count 0 2006.173.12:09:41.26#ibcon#end of sib2, iclass 30, count 0 2006.173.12:09:41.26#ibcon#*after write, iclass 30, count 0 2006.173.12:09:41.26#ibcon#*before return 0, iclass 30, count 0 2006.173.12:09:41.26#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.12:09:41.26#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.12:09:41.26#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.12:09:41.26#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.12:09:41.26$vck44/va=4,6 2006.173.12:09:41.26#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.173.12:09:41.26#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.173.12:09:41.26#ibcon#ireg 11 cls_cnt 2 2006.173.12:09:41.26#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.12:09:41.32#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.12:09:41.32#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.12:09:41.32#ibcon#enter wrdev, iclass 32, count 2 2006.173.12:09:41.32#ibcon#first serial, iclass 32, count 2 2006.173.12:09:41.32#ibcon#enter sib2, iclass 32, count 2 2006.173.12:09:41.32#ibcon#flushed, iclass 32, count 2 2006.173.12:09:41.32#ibcon#about to write, iclass 32, count 2 2006.173.12:09:41.32#ibcon#wrote, iclass 32, count 2 2006.173.12:09:41.32#ibcon#about to read 3, iclass 32, count 2 2006.173.12:09:41.34#ibcon#read 3, iclass 32, count 2 2006.173.12:09:41.34#ibcon#about to read 4, iclass 32, count 2 2006.173.12:09:41.34#ibcon#read 4, iclass 32, count 2 2006.173.12:09:41.34#ibcon#about to read 5, iclass 32, count 2 2006.173.12:09:41.34#ibcon#read 5, iclass 32, count 2 2006.173.12:09:41.34#ibcon#about to read 6, iclass 32, count 2 2006.173.12:09:41.34#ibcon#read 6, iclass 32, count 2 2006.173.12:09:41.34#ibcon#end of sib2, iclass 32, count 2 2006.173.12:09:41.34#ibcon#*mode == 0, iclass 32, count 2 2006.173.12:09:41.34#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.173.12:09:41.34#ibcon#[25=AT04-06\r\n] 2006.173.12:09:41.34#ibcon#*before write, iclass 32, count 2 2006.173.12:09:41.34#ibcon#enter sib2, iclass 32, count 2 2006.173.12:09:41.34#ibcon#flushed, iclass 32, count 2 2006.173.12:09:41.34#ibcon#about to write, iclass 32, count 2 2006.173.12:09:41.34#ibcon#wrote, iclass 32, count 2 2006.173.12:09:41.34#ibcon#about to read 3, iclass 32, count 2 2006.173.12:09:41.37#ibcon#read 3, iclass 32, count 2 2006.173.12:09:41.37#ibcon#about to read 4, iclass 32, count 2 2006.173.12:09:41.37#ibcon#read 4, iclass 32, count 2 2006.173.12:09:41.37#ibcon#about to read 5, iclass 32, count 2 2006.173.12:09:41.37#ibcon#read 5, iclass 32, count 2 2006.173.12:09:41.37#ibcon#about to read 6, iclass 32, count 2 2006.173.12:09:41.37#ibcon#read 6, iclass 32, count 2 2006.173.12:09:41.37#ibcon#end of sib2, iclass 32, count 2 2006.173.12:09:41.37#ibcon#*after write, iclass 32, count 2 2006.173.12:09:41.37#ibcon#*before return 0, iclass 32, count 2 2006.173.12:09:41.37#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.12:09:41.37#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.173.12:09:41.37#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.173.12:09:41.37#ibcon#ireg 7 cls_cnt 0 2006.173.12:09:41.37#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.12:09:41.49#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.12:09:41.49#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.12:09:41.49#ibcon#enter wrdev, iclass 32, count 0 2006.173.12:09:41.49#ibcon#first serial, iclass 32, count 0 2006.173.12:09:41.49#ibcon#enter sib2, iclass 32, count 0 2006.173.12:09:41.49#ibcon#flushed, iclass 32, count 0 2006.173.12:09:41.49#ibcon#about to write, iclass 32, count 0 2006.173.12:09:41.49#ibcon#wrote, iclass 32, count 0 2006.173.12:09:41.49#ibcon#about to read 3, iclass 32, count 0 2006.173.12:09:41.51#ibcon#read 3, iclass 32, count 0 2006.173.12:09:41.51#ibcon#about to read 4, iclass 32, count 0 2006.173.12:09:41.51#ibcon#read 4, iclass 32, count 0 2006.173.12:09:41.51#ibcon#about to read 5, iclass 32, count 0 2006.173.12:09:41.51#ibcon#read 5, iclass 32, count 0 2006.173.12:09:41.51#ibcon#about to read 6, iclass 32, count 0 2006.173.12:09:41.51#ibcon#read 6, iclass 32, count 0 2006.173.12:09:41.51#ibcon#end of sib2, iclass 32, count 0 2006.173.12:09:41.51#ibcon#*mode == 0, iclass 32, count 0 2006.173.12:09:41.51#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.12:09:41.51#ibcon#[25=USB\r\n] 2006.173.12:09:41.51#ibcon#*before write, iclass 32, count 0 2006.173.12:09:41.51#ibcon#enter sib2, iclass 32, count 0 2006.173.12:09:41.51#ibcon#flushed, iclass 32, count 0 2006.173.12:09:41.51#ibcon#about to write, iclass 32, count 0 2006.173.12:09:41.51#ibcon#wrote, iclass 32, count 0 2006.173.12:09:41.51#ibcon#about to read 3, iclass 32, count 0 2006.173.12:09:41.54#ibcon#read 3, iclass 32, count 0 2006.173.12:09:41.54#ibcon#about to read 4, iclass 32, count 0 2006.173.12:09:41.54#ibcon#read 4, iclass 32, count 0 2006.173.12:09:41.54#ibcon#about to read 5, iclass 32, count 0 2006.173.12:09:41.54#ibcon#read 5, iclass 32, count 0 2006.173.12:09:41.54#ibcon#about to read 6, iclass 32, count 0 2006.173.12:09:41.54#ibcon#read 6, iclass 32, count 0 2006.173.12:09:41.54#ibcon#end of sib2, iclass 32, count 0 2006.173.12:09:41.54#ibcon#*after write, iclass 32, count 0 2006.173.12:09:41.54#ibcon#*before return 0, iclass 32, count 0 2006.173.12:09:41.54#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.12:09:41.54#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.173.12:09:41.54#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.12:09:41.54#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.12:09:41.54$vck44/valo=5,734.99 2006.173.12:09:41.54#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.12:09:41.54#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.12:09:41.54#ibcon#ireg 17 cls_cnt 0 2006.173.12:09:41.54#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.12:09:41.54#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.12:09:41.54#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.12:09:41.54#ibcon#enter wrdev, iclass 34, count 0 2006.173.12:09:41.54#ibcon#first serial, iclass 34, count 0 2006.173.12:09:41.54#ibcon#enter sib2, iclass 34, count 0 2006.173.12:09:41.54#ibcon#flushed, iclass 34, count 0 2006.173.12:09:41.54#ibcon#about to write, iclass 34, count 0 2006.173.12:09:41.54#ibcon#wrote, iclass 34, count 0 2006.173.12:09:41.54#ibcon#about to read 3, iclass 34, count 0 2006.173.12:09:41.56#ibcon#read 3, iclass 34, count 0 2006.173.12:09:41.56#ibcon#about to read 4, iclass 34, count 0 2006.173.12:09:41.56#ibcon#read 4, iclass 34, count 0 2006.173.12:09:41.56#ibcon#about to read 5, iclass 34, count 0 2006.173.12:09:41.56#ibcon#read 5, iclass 34, count 0 2006.173.12:09:41.56#ibcon#about to read 6, iclass 34, count 0 2006.173.12:09:41.56#ibcon#read 6, iclass 34, count 0 2006.173.12:09:41.56#ibcon#end of sib2, iclass 34, count 0 2006.173.12:09:41.56#ibcon#*mode == 0, iclass 34, count 0 2006.173.12:09:41.56#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.12:09:41.56#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.12:09:41.56#ibcon#*before write, iclass 34, count 0 2006.173.12:09:41.56#ibcon#enter sib2, iclass 34, count 0 2006.173.12:09:41.56#ibcon#flushed, iclass 34, count 0 2006.173.12:09:41.56#ibcon#about to write, iclass 34, count 0 2006.173.12:09:41.56#ibcon#wrote, iclass 34, count 0 2006.173.12:09:41.56#ibcon#about to read 3, iclass 34, count 0 2006.173.12:09:41.60#ibcon#read 3, iclass 34, count 0 2006.173.12:09:41.60#ibcon#about to read 4, iclass 34, count 0 2006.173.12:09:41.60#ibcon#read 4, iclass 34, count 0 2006.173.12:09:41.60#ibcon#about to read 5, iclass 34, count 0 2006.173.12:09:41.60#ibcon#read 5, iclass 34, count 0 2006.173.12:09:41.60#ibcon#about to read 6, iclass 34, count 0 2006.173.12:09:41.60#ibcon#read 6, iclass 34, count 0 2006.173.12:09:41.60#ibcon#end of sib2, iclass 34, count 0 2006.173.12:09:41.60#ibcon#*after write, iclass 34, count 0 2006.173.12:09:41.60#ibcon#*before return 0, iclass 34, count 0 2006.173.12:09:41.60#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.12:09:41.60#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.12:09:41.60#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.12:09:41.60#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.12:09:41.60$vck44/va=5,4 2006.173.12:09:41.60#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.12:09:41.60#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.12:09:41.60#ibcon#ireg 11 cls_cnt 2 2006.173.12:09:41.60#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.12:09:41.66#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.12:09:41.66#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.12:09:41.66#ibcon#enter wrdev, iclass 36, count 2 2006.173.12:09:41.66#ibcon#first serial, iclass 36, count 2 2006.173.12:09:41.66#ibcon#enter sib2, iclass 36, count 2 2006.173.12:09:41.66#ibcon#flushed, iclass 36, count 2 2006.173.12:09:41.66#ibcon#about to write, iclass 36, count 2 2006.173.12:09:41.66#ibcon#wrote, iclass 36, count 2 2006.173.12:09:41.66#ibcon#about to read 3, iclass 36, count 2 2006.173.12:09:41.68#ibcon#read 3, iclass 36, count 2 2006.173.12:09:41.68#ibcon#about to read 4, iclass 36, count 2 2006.173.12:09:41.68#ibcon#read 4, iclass 36, count 2 2006.173.12:09:41.68#ibcon#about to read 5, iclass 36, count 2 2006.173.12:09:41.68#ibcon#read 5, iclass 36, count 2 2006.173.12:09:41.68#ibcon#about to read 6, iclass 36, count 2 2006.173.12:09:41.68#ibcon#read 6, iclass 36, count 2 2006.173.12:09:41.68#ibcon#end of sib2, iclass 36, count 2 2006.173.12:09:41.68#ibcon#*mode == 0, iclass 36, count 2 2006.173.12:09:41.68#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.12:09:41.68#ibcon#[25=AT05-04\r\n] 2006.173.12:09:41.68#ibcon#*before write, iclass 36, count 2 2006.173.12:09:41.68#ibcon#enter sib2, iclass 36, count 2 2006.173.12:09:41.68#ibcon#flushed, iclass 36, count 2 2006.173.12:09:41.68#ibcon#about to write, iclass 36, count 2 2006.173.12:09:41.68#ibcon#wrote, iclass 36, count 2 2006.173.12:09:41.68#ibcon#about to read 3, iclass 36, count 2 2006.173.12:09:41.71#ibcon#read 3, iclass 36, count 2 2006.173.12:09:41.71#ibcon#about to read 4, iclass 36, count 2 2006.173.12:09:41.71#ibcon#read 4, iclass 36, count 2 2006.173.12:09:41.71#ibcon#about to read 5, iclass 36, count 2 2006.173.12:09:41.71#ibcon#read 5, iclass 36, count 2 2006.173.12:09:41.71#ibcon#about to read 6, iclass 36, count 2 2006.173.12:09:41.71#ibcon#read 6, iclass 36, count 2 2006.173.12:09:41.71#ibcon#end of sib2, iclass 36, count 2 2006.173.12:09:41.71#ibcon#*after write, iclass 36, count 2 2006.173.12:09:41.71#ibcon#*before return 0, iclass 36, count 2 2006.173.12:09:41.71#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.12:09:41.71#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.12:09:41.71#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.12:09:41.71#ibcon#ireg 7 cls_cnt 0 2006.173.12:09:41.71#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.12:09:41.83#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.12:09:41.83#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.12:09:41.83#ibcon#enter wrdev, iclass 36, count 0 2006.173.12:09:41.83#ibcon#first serial, iclass 36, count 0 2006.173.12:09:41.83#ibcon#enter sib2, iclass 36, count 0 2006.173.12:09:41.83#ibcon#flushed, iclass 36, count 0 2006.173.12:09:41.83#ibcon#about to write, iclass 36, count 0 2006.173.12:09:41.83#ibcon#wrote, iclass 36, count 0 2006.173.12:09:41.83#ibcon#about to read 3, iclass 36, count 0 2006.173.12:09:41.85#ibcon#read 3, iclass 36, count 0 2006.173.12:09:41.85#ibcon#about to read 4, iclass 36, count 0 2006.173.12:09:41.85#ibcon#read 4, iclass 36, count 0 2006.173.12:09:41.85#ibcon#about to read 5, iclass 36, count 0 2006.173.12:09:41.85#ibcon#read 5, iclass 36, count 0 2006.173.12:09:41.85#ibcon#about to read 6, iclass 36, count 0 2006.173.12:09:41.85#ibcon#read 6, iclass 36, count 0 2006.173.12:09:41.85#ibcon#end of sib2, iclass 36, count 0 2006.173.12:09:41.85#ibcon#*mode == 0, iclass 36, count 0 2006.173.12:09:41.85#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.12:09:41.85#ibcon#[25=USB\r\n] 2006.173.12:09:41.85#ibcon#*before write, iclass 36, count 0 2006.173.12:09:41.85#ibcon#enter sib2, iclass 36, count 0 2006.173.12:09:41.85#ibcon#flushed, iclass 36, count 0 2006.173.12:09:41.85#ibcon#about to write, iclass 36, count 0 2006.173.12:09:41.85#ibcon#wrote, iclass 36, count 0 2006.173.12:09:41.85#ibcon#about to read 3, iclass 36, count 0 2006.173.12:09:41.88#ibcon#read 3, iclass 36, count 0 2006.173.12:09:41.88#ibcon#about to read 4, iclass 36, count 0 2006.173.12:09:41.88#ibcon#read 4, iclass 36, count 0 2006.173.12:09:41.88#ibcon#about to read 5, iclass 36, count 0 2006.173.12:09:41.88#ibcon#read 5, iclass 36, count 0 2006.173.12:09:41.88#ibcon#about to read 6, iclass 36, count 0 2006.173.12:09:41.88#ibcon#read 6, iclass 36, count 0 2006.173.12:09:41.88#ibcon#end of sib2, iclass 36, count 0 2006.173.12:09:41.88#ibcon#*after write, iclass 36, count 0 2006.173.12:09:41.88#ibcon#*before return 0, iclass 36, count 0 2006.173.12:09:41.88#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.12:09:41.88#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.12:09:41.88#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.12:09:41.88#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.12:09:41.88$vck44/valo=6,814.99 2006.173.12:09:41.88#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.12:09:41.88#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.12:09:41.88#ibcon#ireg 17 cls_cnt 0 2006.173.12:09:41.88#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.12:09:41.88#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.12:09:41.88#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.12:09:41.88#ibcon#enter wrdev, iclass 38, count 0 2006.173.12:09:41.88#ibcon#first serial, iclass 38, count 0 2006.173.12:09:41.88#ibcon#enter sib2, iclass 38, count 0 2006.173.12:09:41.88#ibcon#flushed, iclass 38, count 0 2006.173.12:09:41.88#ibcon#about to write, iclass 38, count 0 2006.173.12:09:41.88#ibcon#wrote, iclass 38, count 0 2006.173.12:09:41.88#ibcon#about to read 3, iclass 38, count 0 2006.173.12:09:41.90#ibcon#read 3, iclass 38, count 0 2006.173.12:09:41.90#ibcon#about to read 4, iclass 38, count 0 2006.173.12:09:41.90#ibcon#read 4, iclass 38, count 0 2006.173.12:09:41.90#ibcon#about to read 5, iclass 38, count 0 2006.173.12:09:41.90#ibcon#read 5, iclass 38, count 0 2006.173.12:09:41.90#ibcon#about to read 6, iclass 38, count 0 2006.173.12:09:41.90#ibcon#read 6, iclass 38, count 0 2006.173.12:09:41.90#ibcon#end of sib2, iclass 38, count 0 2006.173.12:09:41.90#ibcon#*mode == 0, iclass 38, count 0 2006.173.12:09:41.90#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.12:09:41.90#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.12:09:41.90#ibcon#*before write, iclass 38, count 0 2006.173.12:09:41.90#ibcon#enter sib2, iclass 38, count 0 2006.173.12:09:41.90#ibcon#flushed, iclass 38, count 0 2006.173.12:09:41.90#ibcon#about to write, iclass 38, count 0 2006.173.12:09:41.90#ibcon#wrote, iclass 38, count 0 2006.173.12:09:41.90#ibcon#about to read 3, iclass 38, count 0 2006.173.12:09:41.94#ibcon#read 3, iclass 38, count 0 2006.173.12:09:41.94#ibcon#about to read 4, iclass 38, count 0 2006.173.12:09:41.94#ibcon#read 4, iclass 38, count 0 2006.173.12:09:41.94#ibcon#about to read 5, iclass 38, count 0 2006.173.12:09:41.94#ibcon#read 5, iclass 38, count 0 2006.173.12:09:41.94#ibcon#about to read 6, iclass 38, count 0 2006.173.12:09:41.94#ibcon#read 6, iclass 38, count 0 2006.173.12:09:41.94#ibcon#end of sib2, iclass 38, count 0 2006.173.12:09:41.94#ibcon#*after write, iclass 38, count 0 2006.173.12:09:41.94#ibcon#*before return 0, iclass 38, count 0 2006.173.12:09:41.94#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.12:09:41.94#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.12:09:41.94#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.12:09:41.94#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.12:09:41.94$vck44/va=6,3 2006.173.12:09:41.94#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.12:09:41.94#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.12:09:41.94#ibcon#ireg 11 cls_cnt 2 2006.173.12:09:41.94#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.12:09:42.00#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.12:09:42.00#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.12:09:42.00#ibcon#enter wrdev, iclass 40, count 2 2006.173.12:09:42.00#ibcon#first serial, iclass 40, count 2 2006.173.12:09:42.00#ibcon#enter sib2, iclass 40, count 2 2006.173.12:09:42.00#ibcon#flushed, iclass 40, count 2 2006.173.12:09:42.00#ibcon#about to write, iclass 40, count 2 2006.173.12:09:42.00#ibcon#wrote, iclass 40, count 2 2006.173.12:09:42.00#ibcon#about to read 3, iclass 40, count 2 2006.173.12:09:42.02#ibcon#read 3, iclass 40, count 2 2006.173.12:09:42.02#ibcon#about to read 4, iclass 40, count 2 2006.173.12:09:42.02#ibcon#read 4, iclass 40, count 2 2006.173.12:09:42.02#ibcon#about to read 5, iclass 40, count 2 2006.173.12:09:42.02#ibcon#read 5, iclass 40, count 2 2006.173.12:09:42.02#ibcon#about to read 6, iclass 40, count 2 2006.173.12:09:42.02#ibcon#read 6, iclass 40, count 2 2006.173.12:09:42.02#ibcon#end of sib2, iclass 40, count 2 2006.173.12:09:42.02#ibcon#*mode == 0, iclass 40, count 2 2006.173.12:09:42.02#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.12:09:42.02#ibcon#[25=AT06-03\r\n] 2006.173.12:09:42.02#ibcon#*before write, iclass 40, count 2 2006.173.12:09:42.02#ibcon#enter sib2, iclass 40, count 2 2006.173.12:09:42.02#ibcon#flushed, iclass 40, count 2 2006.173.12:09:42.02#ibcon#about to write, iclass 40, count 2 2006.173.12:09:42.02#ibcon#wrote, iclass 40, count 2 2006.173.12:09:42.02#ibcon#about to read 3, iclass 40, count 2 2006.173.12:09:42.05#ibcon#read 3, iclass 40, count 2 2006.173.12:09:42.05#ibcon#about to read 4, iclass 40, count 2 2006.173.12:09:42.05#ibcon#read 4, iclass 40, count 2 2006.173.12:09:42.05#ibcon#about to read 5, iclass 40, count 2 2006.173.12:09:42.05#ibcon#read 5, iclass 40, count 2 2006.173.12:09:42.05#ibcon#about to read 6, iclass 40, count 2 2006.173.12:09:42.05#ibcon#read 6, iclass 40, count 2 2006.173.12:09:42.05#ibcon#end of sib2, iclass 40, count 2 2006.173.12:09:42.05#ibcon#*after write, iclass 40, count 2 2006.173.12:09:42.05#ibcon#*before return 0, iclass 40, count 2 2006.173.12:09:42.05#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.12:09:42.05#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.12:09:42.05#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.12:09:42.05#ibcon#ireg 7 cls_cnt 0 2006.173.12:09:42.05#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.12:09:42.17#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.12:09:42.17#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.12:09:42.17#ibcon#enter wrdev, iclass 40, count 0 2006.173.12:09:42.17#ibcon#first serial, iclass 40, count 0 2006.173.12:09:42.17#ibcon#enter sib2, iclass 40, count 0 2006.173.12:09:42.17#ibcon#flushed, iclass 40, count 0 2006.173.12:09:42.17#ibcon#about to write, iclass 40, count 0 2006.173.12:09:42.17#ibcon#wrote, iclass 40, count 0 2006.173.12:09:42.17#ibcon#about to read 3, iclass 40, count 0 2006.173.12:09:42.19#ibcon#read 3, iclass 40, count 0 2006.173.12:09:42.19#ibcon#about to read 4, iclass 40, count 0 2006.173.12:09:42.19#ibcon#read 4, iclass 40, count 0 2006.173.12:09:42.19#ibcon#about to read 5, iclass 40, count 0 2006.173.12:09:42.19#ibcon#read 5, iclass 40, count 0 2006.173.12:09:42.19#ibcon#about to read 6, iclass 40, count 0 2006.173.12:09:42.19#ibcon#read 6, iclass 40, count 0 2006.173.12:09:42.19#ibcon#end of sib2, iclass 40, count 0 2006.173.12:09:42.19#ibcon#*mode == 0, iclass 40, count 0 2006.173.12:09:42.19#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.12:09:42.19#ibcon#[25=USB\r\n] 2006.173.12:09:42.19#ibcon#*before write, iclass 40, count 0 2006.173.12:09:42.19#ibcon#enter sib2, iclass 40, count 0 2006.173.12:09:42.19#ibcon#flushed, iclass 40, count 0 2006.173.12:09:42.19#ibcon#about to write, iclass 40, count 0 2006.173.12:09:42.19#ibcon#wrote, iclass 40, count 0 2006.173.12:09:42.19#ibcon#about to read 3, iclass 40, count 0 2006.173.12:09:42.22#ibcon#read 3, iclass 40, count 0 2006.173.12:09:42.22#ibcon#about to read 4, iclass 40, count 0 2006.173.12:09:42.22#ibcon#read 4, iclass 40, count 0 2006.173.12:09:42.22#ibcon#about to read 5, iclass 40, count 0 2006.173.12:09:42.22#ibcon#read 5, iclass 40, count 0 2006.173.12:09:42.22#ibcon#about to read 6, iclass 40, count 0 2006.173.12:09:42.22#ibcon#read 6, iclass 40, count 0 2006.173.12:09:42.22#ibcon#end of sib2, iclass 40, count 0 2006.173.12:09:42.22#ibcon#*after write, iclass 40, count 0 2006.173.12:09:42.22#ibcon#*before return 0, iclass 40, count 0 2006.173.12:09:42.22#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.12:09:42.22#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.12:09:42.22#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.12:09:42.22#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.12:09:42.22$vck44/valo=7,864.99 2006.173.12:09:42.22#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.12:09:42.22#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.12:09:42.22#ibcon#ireg 17 cls_cnt 0 2006.173.12:09:42.22#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.12:09:42.22#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.12:09:42.22#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.12:09:42.22#ibcon#enter wrdev, iclass 4, count 0 2006.173.12:09:42.22#ibcon#first serial, iclass 4, count 0 2006.173.12:09:42.22#ibcon#enter sib2, iclass 4, count 0 2006.173.12:09:42.22#ibcon#flushed, iclass 4, count 0 2006.173.12:09:42.22#ibcon#about to write, iclass 4, count 0 2006.173.12:09:42.22#ibcon#wrote, iclass 4, count 0 2006.173.12:09:42.22#ibcon#about to read 3, iclass 4, count 0 2006.173.12:09:42.24#ibcon#read 3, iclass 4, count 0 2006.173.12:09:42.24#ibcon#about to read 4, iclass 4, count 0 2006.173.12:09:42.24#ibcon#read 4, iclass 4, count 0 2006.173.12:09:42.24#ibcon#about to read 5, iclass 4, count 0 2006.173.12:09:42.24#ibcon#read 5, iclass 4, count 0 2006.173.12:09:42.24#ibcon#about to read 6, iclass 4, count 0 2006.173.12:09:42.24#ibcon#read 6, iclass 4, count 0 2006.173.12:09:42.24#ibcon#end of sib2, iclass 4, count 0 2006.173.12:09:42.24#ibcon#*mode == 0, iclass 4, count 0 2006.173.12:09:42.24#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.12:09:42.24#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.12:09:42.24#ibcon#*before write, iclass 4, count 0 2006.173.12:09:42.24#ibcon#enter sib2, iclass 4, count 0 2006.173.12:09:42.24#ibcon#flushed, iclass 4, count 0 2006.173.12:09:42.24#ibcon#about to write, iclass 4, count 0 2006.173.12:09:42.24#ibcon#wrote, iclass 4, count 0 2006.173.12:09:42.24#ibcon#about to read 3, iclass 4, count 0 2006.173.12:09:42.28#ibcon#read 3, iclass 4, count 0 2006.173.12:09:42.28#ibcon#about to read 4, iclass 4, count 0 2006.173.12:09:42.28#ibcon#read 4, iclass 4, count 0 2006.173.12:09:42.28#ibcon#about to read 5, iclass 4, count 0 2006.173.12:09:42.28#ibcon#read 5, iclass 4, count 0 2006.173.12:09:42.28#ibcon#about to read 6, iclass 4, count 0 2006.173.12:09:42.28#ibcon#read 6, iclass 4, count 0 2006.173.12:09:42.28#ibcon#end of sib2, iclass 4, count 0 2006.173.12:09:42.28#ibcon#*after write, iclass 4, count 0 2006.173.12:09:42.28#ibcon#*before return 0, iclass 4, count 0 2006.173.12:09:42.28#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.12:09:42.28#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.12:09:42.28#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.12:09:42.28#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.12:09:42.28$vck44/va=7,4 2006.173.12:09:42.28#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.12:09:42.28#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.12:09:42.28#ibcon#ireg 11 cls_cnt 2 2006.173.12:09:42.28#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.12:09:42.34#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.12:09:42.34#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.12:09:42.34#ibcon#enter wrdev, iclass 6, count 2 2006.173.12:09:42.34#ibcon#first serial, iclass 6, count 2 2006.173.12:09:42.34#ibcon#enter sib2, iclass 6, count 2 2006.173.12:09:42.34#ibcon#flushed, iclass 6, count 2 2006.173.12:09:42.34#ibcon#about to write, iclass 6, count 2 2006.173.12:09:42.34#ibcon#wrote, iclass 6, count 2 2006.173.12:09:42.34#ibcon#about to read 3, iclass 6, count 2 2006.173.12:09:42.36#ibcon#read 3, iclass 6, count 2 2006.173.12:09:42.36#ibcon#about to read 4, iclass 6, count 2 2006.173.12:09:42.36#ibcon#read 4, iclass 6, count 2 2006.173.12:09:42.36#ibcon#about to read 5, iclass 6, count 2 2006.173.12:09:42.36#ibcon#read 5, iclass 6, count 2 2006.173.12:09:42.36#ibcon#about to read 6, iclass 6, count 2 2006.173.12:09:42.36#ibcon#read 6, iclass 6, count 2 2006.173.12:09:42.36#ibcon#end of sib2, iclass 6, count 2 2006.173.12:09:42.36#ibcon#*mode == 0, iclass 6, count 2 2006.173.12:09:42.36#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.12:09:42.36#ibcon#[25=AT07-04\r\n] 2006.173.12:09:42.36#ibcon#*before write, iclass 6, count 2 2006.173.12:09:42.36#ibcon#enter sib2, iclass 6, count 2 2006.173.12:09:42.36#ibcon#flushed, iclass 6, count 2 2006.173.12:09:42.36#ibcon#about to write, iclass 6, count 2 2006.173.12:09:42.36#ibcon#wrote, iclass 6, count 2 2006.173.12:09:42.36#ibcon#about to read 3, iclass 6, count 2 2006.173.12:09:42.39#ibcon#read 3, iclass 6, count 2 2006.173.12:09:42.39#ibcon#about to read 4, iclass 6, count 2 2006.173.12:09:42.39#ibcon#read 4, iclass 6, count 2 2006.173.12:09:42.39#ibcon#about to read 5, iclass 6, count 2 2006.173.12:09:42.39#ibcon#read 5, iclass 6, count 2 2006.173.12:09:42.39#ibcon#about to read 6, iclass 6, count 2 2006.173.12:09:42.39#ibcon#read 6, iclass 6, count 2 2006.173.12:09:42.39#ibcon#end of sib2, iclass 6, count 2 2006.173.12:09:42.39#ibcon#*after write, iclass 6, count 2 2006.173.12:09:42.39#ibcon#*before return 0, iclass 6, count 2 2006.173.12:09:42.39#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.12:09:42.39#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.12:09:42.39#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.12:09:42.39#ibcon#ireg 7 cls_cnt 0 2006.173.12:09:42.39#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.12:09:42.51#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.12:09:42.51#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.12:09:42.51#ibcon#enter wrdev, iclass 6, count 0 2006.173.12:09:42.51#ibcon#first serial, iclass 6, count 0 2006.173.12:09:42.51#ibcon#enter sib2, iclass 6, count 0 2006.173.12:09:42.51#ibcon#flushed, iclass 6, count 0 2006.173.12:09:42.51#ibcon#about to write, iclass 6, count 0 2006.173.12:09:42.51#ibcon#wrote, iclass 6, count 0 2006.173.12:09:42.51#ibcon#about to read 3, iclass 6, count 0 2006.173.12:09:42.53#ibcon#read 3, iclass 6, count 0 2006.173.12:09:42.53#ibcon#about to read 4, iclass 6, count 0 2006.173.12:09:42.53#ibcon#read 4, iclass 6, count 0 2006.173.12:09:42.53#ibcon#about to read 5, iclass 6, count 0 2006.173.12:09:42.53#ibcon#read 5, iclass 6, count 0 2006.173.12:09:42.53#ibcon#about to read 6, iclass 6, count 0 2006.173.12:09:42.53#ibcon#read 6, iclass 6, count 0 2006.173.12:09:42.53#ibcon#end of sib2, iclass 6, count 0 2006.173.12:09:42.53#ibcon#*mode == 0, iclass 6, count 0 2006.173.12:09:42.53#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.12:09:42.53#ibcon#[25=USB\r\n] 2006.173.12:09:42.53#ibcon#*before write, iclass 6, count 0 2006.173.12:09:42.53#ibcon#enter sib2, iclass 6, count 0 2006.173.12:09:42.53#ibcon#flushed, iclass 6, count 0 2006.173.12:09:42.53#ibcon#about to write, iclass 6, count 0 2006.173.12:09:42.53#ibcon#wrote, iclass 6, count 0 2006.173.12:09:42.53#ibcon#about to read 3, iclass 6, count 0 2006.173.12:09:42.56#ibcon#read 3, iclass 6, count 0 2006.173.12:09:42.56#ibcon#about to read 4, iclass 6, count 0 2006.173.12:09:42.56#ibcon#read 4, iclass 6, count 0 2006.173.12:09:42.56#ibcon#about to read 5, iclass 6, count 0 2006.173.12:09:42.56#ibcon#read 5, iclass 6, count 0 2006.173.12:09:42.56#ibcon#about to read 6, iclass 6, count 0 2006.173.12:09:42.56#ibcon#read 6, iclass 6, count 0 2006.173.12:09:42.56#ibcon#end of sib2, iclass 6, count 0 2006.173.12:09:42.56#ibcon#*after write, iclass 6, count 0 2006.173.12:09:42.56#ibcon#*before return 0, iclass 6, count 0 2006.173.12:09:42.56#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.12:09:42.56#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.12:09:42.56#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.12:09:42.56#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.12:09:42.56$vck44/valo=8,884.99 2006.173.12:09:42.56#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.12:09:42.56#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.12:09:42.56#ibcon#ireg 17 cls_cnt 0 2006.173.12:09:42.56#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.12:09:42.56#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.12:09:42.56#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.12:09:42.56#ibcon#enter wrdev, iclass 10, count 0 2006.173.12:09:42.56#ibcon#first serial, iclass 10, count 0 2006.173.12:09:42.56#ibcon#enter sib2, iclass 10, count 0 2006.173.12:09:42.56#ibcon#flushed, iclass 10, count 0 2006.173.12:09:42.56#ibcon#about to write, iclass 10, count 0 2006.173.12:09:42.56#ibcon#wrote, iclass 10, count 0 2006.173.12:09:42.56#ibcon#about to read 3, iclass 10, count 0 2006.173.12:09:42.58#ibcon#read 3, iclass 10, count 0 2006.173.12:09:42.58#ibcon#about to read 4, iclass 10, count 0 2006.173.12:09:42.58#ibcon#read 4, iclass 10, count 0 2006.173.12:09:42.58#ibcon#about to read 5, iclass 10, count 0 2006.173.12:09:42.58#ibcon#read 5, iclass 10, count 0 2006.173.12:09:42.58#ibcon#about to read 6, iclass 10, count 0 2006.173.12:09:42.58#ibcon#read 6, iclass 10, count 0 2006.173.12:09:42.58#ibcon#end of sib2, iclass 10, count 0 2006.173.12:09:42.58#ibcon#*mode == 0, iclass 10, count 0 2006.173.12:09:42.58#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.12:09:42.58#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.12:09:42.58#ibcon#*before write, iclass 10, count 0 2006.173.12:09:42.58#ibcon#enter sib2, iclass 10, count 0 2006.173.12:09:42.58#ibcon#flushed, iclass 10, count 0 2006.173.12:09:42.58#ibcon#about to write, iclass 10, count 0 2006.173.12:09:42.58#ibcon#wrote, iclass 10, count 0 2006.173.12:09:42.58#ibcon#about to read 3, iclass 10, count 0 2006.173.12:09:42.62#ibcon#read 3, iclass 10, count 0 2006.173.12:09:42.62#ibcon#about to read 4, iclass 10, count 0 2006.173.12:09:42.62#ibcon#read 4, iclass 10, count 0 2006.173.12:09:42.62#ibcon#about to read 5, iclass 10, count 0 2006.173.12:09:42.62#ibcon#read 5, iclass 10, count 0 2006.173.12:09:42.62#ibcon#about to read 6, iclass 10, count 0 2006.173.12:09:42.62#ibcon#read 6, iclass 10, count 0 2006.173.12:09:42.62#ibcon#end of sib2, iclass 10, count 0 2006.173.12:09:42.62#ibcon#*after write, iclass 10, count 0 2006.173.12:09:42.62#ibcon#*before return 0, iclass 10, count 0 2006.173.12:09:42.62#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.12:09:42.62#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.12:09:42.62#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.12:09:42.62#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.12:09:42.62$vck44/va=8,4 2006.173.12:09:42.62#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.12:09:42.62#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.12:09:42.62#ibcon#ireg 11 cls_cnt 2 2006.173.12:09:42.62#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.12:09:42.68#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.12:09:42.68#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.12:09:42.68#ibcon#enter wrdev, iclass 12, count 2 2006.173.12:09:42.68#ibcon#first serial, iclass 12, count 2 2006.173.12:09:42.68#ibcon#enter sib2, iclass 12, count 2 2006.173.12:09:42.68#ibcon#flushed, iclass 12, count 2 2006.173.12:09:42.68#ibcon#about to write, iclass 12, count 2 2006.173.12:09:42.68#ibcon#wrote, iclass 12, count 2 2006.173.12:09:42.68#ibcon#about to read 3, iclass 12, count 2 2006.173.12:09:42.70#ibcon#read 3, iclass 12, count 2 2006.173.12:09:42.70#ibcon#about to read 4, iclass 12, count 2 2006.173.12:09:42.70#ibcon#read 4, iclass 12, count 2 2006.173.12:09:42.70#ibcon#about to read 5, iclass 12, count 2 2006.173.12:09:42.70#ibcon#read 5, iclass 12, count 2 2006.173.12:09:42.70#ibcon#about to read 6, iclass 12, count 2 2006.173.12:09:42.70#ibcon#read 6, iclass 12, count 2 2006.173.12:09:42.70#ibcon#end of sib2, iclass 12, count 2 2006.173.12:09:42.70#ibcon#*mode == 0, iclass 12, count 2 2006.173.12:09:42.70#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.12:09:42.70#ibcon#[25=AT08-04\r\n] 2006.173.12:09:42.70#ibcon#*before write, iclass 12, count 2 2006.173.12:09:42.70#ibcon#enter sib2, iclass 12, count 2 2006.173.12:09:42.70#ibcon#flushed, iclass 12, count 2 2006.173.12:09:42.70#ibcon#about to write, iclass 12, count 2 2006.173.12:09:42.70#ibcon#wrote, iclass 12, count 2 2006.173.12:09:42.70#ibcon#about to read 3, iclass 12, count 2 2006.173.12:09:42.73#ibcon#read 3, iclass 12, count 2 2006.173.12:09:42.73#ibcon#about to read 4, iclass 12, count 2 2006.173.12:09:42.73#ibcon#read 4, iclass 12, count 2 2006.173.12:09:42.73#ibcon#about to read 5, iclass 12, count 2 2006.173.12:09:42.73#ibcon#read 5, iclass 12, count 2 2006.173.12:09:42.73#ibcon#about to read 6, iclass 12, count 2 2006.173.12:09:42.73#ibcon#read 6, iclass 12, count 2 2006.173.12:09:42.73#ibcon#end of sib2, iclass 12, count 2 2006.173.12:09:42.73#ibcon#*after write, iclass 12, count 2 2006.173.12:09:42.73#ibcon#*before return 0, iclass 12, count 2 2006.173.12:09:42.73#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.12:09:42.73#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.12:09:42.73#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.12:09:42.73#ibcon#ireg 7 cls_cnt 0 2006.173.12:09:42.73#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.12:09:42.85#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.12:09:42.85#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.12:09:42.85#ibcon#enter wrdev, iclass 12, count 0 2006.173.12:09:42.85#ibcon#first serial, iclass 12, count 0 2006.173.12:09:42.85#ibcon#enter sib2, iclass 12, count 0 2006.173.12:09:42.85#ibcon#flushed, iclass 12, count 0 2006.173.12:09:42.85#ibcon#about to write, iclass 12, count 0 2006.173.12:09:42.85#ibcon#wrote, iclass 12, count 0 2006.173.12:09:42.85#ibcon#about to read 3, iclass 12, count 0 2006.173.12:09:42.87#ibcon#read 3, iclass 12, count 0 2006.173.12:09:42.87#ibcon#about to read 4, iclass 12, count 0 2006.173.12:09:42.87#ibcon#read 4, iclass 12, count 0 2006.173.12:09:42.87#ibcon#about to read 5, iclass 12, count 0 2006.173.12:09:42.87#ibcon#read 5, iclass 12, count 0 2006.173.12:09:42.87#ibcon#about to read 6, iclass 12, count 0 2006.173.12:09:42.87#ibcon#read 6, iclass 12, count 0 2006.173.12:09:42.87#ibcon#end of sib2, iclass 12, count 0 2006.173.12:09:42.87#ibcon#*mode == 0, iclass 12, count 0 2006.173.12:09:42.87#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.12:09:42.87#ibcon#[25=USB\r\n] 2006.173.12:09:42.87#ibcon#*before write, iclass 12, count 0 2006.173.12:09:42.87#ibcon#enter sib2, iclass 12, count 0 2006.173.12:09:42.87#ibcon#flushed, iclass 12, count 0 2006.173.12:09:42.87#ibcon#about to write, iclass 12, count 0 2006.173.12:09:42.87#ibcon#wrote, iclass 12, count 0 2006.173.12:09:42.87#ibcon#about to read 3, iclass 12, count 0 2006.173.12:09:42.90#ibcon#read 3, iclass 12, count 0 2006.173.12:09:42.90#ibcon#about to read 4, iclass 12, count 0 2006.173.12:09:42.90#ibcon#read 4, iclass 12, count 0 2006.173.12:09:42.90#ibcon#about to read 5, iclass 12, count 0 2006.173.12:09:42.90#ibcon#read 5, iclass 12, count 0 2006.173.12:09:42.90#ibcon#about to read 6, iclass 12, count 0 2006.173.12:09:42.90#ibcon#read 6, iclass 12, count 0 2006.173.12:09:42.90#ibcon#end of sib2, iclass 12, count 0 2006.173.12:09:42.90#ibcon#*after write, iclass 12, count 0 2006.173.12:09:42.90#ibcon#*before return 0, iclass 12, count 0 2006.173.12:09:42.90#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.12:09:42.90#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.12:09:42.90#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.12:09:42.90#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.12:09:42.90$vck44/vblo=1,629.99 2006.173.12:09:42.90#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.12:09:42.90#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.12:09:42.90#ibcon#ireg 17 cls_cnt 0 2006.173.12:09:42.90#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.12:09:42.90#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.12:09:42.90#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.12:09:42.90#ibcon#enter wrdev, iclass 14, count 0 2006.173.12:09:42.90#ibcon#first serial, iclass 14, count 0 2006.173.12:09:42.90#ibcon#enter sib2, iclass 14, count 0 2006.173.12:09:42.90#ibcon#flushed, iclass 14, count 0 2006.173.12:09:42.90#ibcon#about to write, iclass 14, count 0 2006.173.12:09:42.90#ibcon#wrote, iclass 14, count 0 2006.173.12:09:42.90#ibcon#about to read 3, iclass 14, count 0 2006.173.12:09:42.92#ibcon#read 3, iclass 14, count 0 2006.173.12:09:42.92#ibcon#about to read 4, iclass 14, count 0 2006.173.12:09:42.92#ibcon#read 4, iclass 14, count 0 2006.173.12:09:42.92#ibcon#about to read 5, iclass 14, count 0 2006.173.12:09:42.92#ibcon#read 5, iclass 14, count 0 2006.173.12:09:42.92#ibcon#about to read 6, iclass 14, count 0 2006.173.12:09:42.92#ibcon#read 6, iclass 14, count 0 2006.173.12:09:42.92#ibcon#end of sib2, iclass 14, count 0 2006.173.12:09:42.92#ibcon#*mode == 0, iclass 14, count 0 2006.173.12:09:42.92#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.12:09:42.92#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.12:09:42.92#ibcon#*before write, iclass 14, count 0 2006.173.12:09:42.92#ibcon#enter sib2, iclass 14, count 0 2006.173.12:09:42.92#ibcon#flushed, iclass 14, count 0 2006.173.12:09:42.92#ibcon#about to write, iclass 14, count 0 2006.173.12:09:42.92#ibcon#wrote, iclass 14, count 0 2006.173.12:09:42.92#ibcon#about to read 3, iclass 14, count 0 2006.173.12:09:42.96#ibcon#read 3, iclass 14, count 0 2006.173.12:09:42.96#ibcon#about to read 4, iclass 14, count 0 2006.173.12:09:42.96#ibcon#read 4, iclass 14, count 0 2006.173.12:09:42.96#ibcon#about to read 5, iclass 14, count 0 2006.173.12:09:42.96#ibcon#read 5, iclass 14, count 0 2006.173.12:09:42.96#ibcon#about to read 6, iclass 14, count 0 2006.173.12:09:42.96#ibcon#read 6, iclass 14, count 0 2006.173.12:09:42.96#ibcon#end of sib2, iclass 14, count 0 2006.173.12:09:42.96#ibcon#*after write, iclass 14, count 0 2006.173.12:09:42.96#ibcon#*before return 0, iclass 14, count 0 2006.173.12:09:42.96#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.12:09:42.96#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.12:09:42.96#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.12:09:42.96#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.12:09:42.96$vck44/vb=1,4 2006.173.12:09:42.96#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.12:09:42.96#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.12:09:42.96#ibcon#ireg 11 cls_cnt 2 2006.173.12:09:42.96#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.12:09:42.96#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.12:09:42.96#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.12:09:42.96#ibcon#enter wrdev, iclass 16, count 2 2006.173.12:09:42.96#ibcon#first serial, iclass 16, count 2 2006.173.12:09:42.96#ibcon#enter sib2, iclass 16, count 2 2006.173.12:09:42.96#ibcon#flushed, iclass 16, count 2 2006.173.12:09:42.96#ibcon#about to write, iclass 16, count 2 2006.173.12:09:42.96#ibcon#wrote, iclass 16, count 2 2006.173.12:09:42.96#ibcon#about to read 3, iclass 16, count 2 2006.173.12:09:42.98#ibcon#read 3, iclass 16, count 2 2006.173.12:09:42.98#ibcon#about to read 4, iclass 16, count 2 2006.173.12:09:42.98#ibcon#read 4, iclass 16, count 2 2006.173.12:09:42.98#ibcon#about to read 5, iclass 16, count 2 2006.173.12:09:42.98#ibcon#read 5, iclass 16, count 2 2006.173.12:09:42.98#ibcon#about to read 6, iclass 16, count 2 2006.173.12:09:42.98#ibcon#read 6, iclass 16, count 2 2006.173.12:09:42.98#ibcon#end of sib2, iclass 16, count 2 2006.173.12:09:42.98#ibcon#*mode == 0, iclass 16, count 2 2006.173.12:09:42.98#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.12:09:42.98#ibcon#[27=AT01-04\r\n] 2006.173.12:09:42.98#ibcon#*before write, iclass 16, count 2 2006.173.12:09:42.98#ibcon#enter sib2, iclass 16, count 2 2006.173.12:09:42.98#ibcon#flushed, iclass 16, count 2 2006.173.12:09:42.98#ibcon#about to write, iclass 16, count 2 2006.173.12:09:42.98#ibcon#wrote, iclass 16, count 2 2006.173.12:09:42.98#ibcon#about to read 3, iclass 16, count 2 2006.173.12:09:43.01#ibcon#read 3, iclass 16, count 2 2006.173.12:09:43.01#ibcon#about to read 4, iclass 16, count 2 2006.173.12:09:43.01#ibcon#read 4, iclass 16, count 2 2006.173.12:09:43.01#ibcon#about to read 5, iclass 16, count 2 2006.173.12:09:43.01#ibcon#read 5, iclass 16, count 2 2006.173.12:09:43.01#ibcon#about to read 6, iclass 16, count 2 2006.173.12:09:43.01#ibcon#read 6, iclass 16, count 2 2006.173.12:09:43.01#ibcon#end of sib2, iclass 16, count 2 2006.173.12:09:43.01#ibcon#*after write, iclass 16, count 2 2006.173.12:09:43.01#ibcon#*before return 0, iclass 16, count 2 2006.173.12:09:43.01#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.12:09:43.01#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.12:09:43.01#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.12:09:43.01#ibcon#ireg 7 cls_cnt 0 2006.173.12:09:43.01#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.12:09:43.13#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.12:09:43.13#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.12:09:43.13#ibcon#enter wrdev, iclass 16, count 0 2006.173.12:09:43.13#ibcon#first serial, iclass 16, count 0 2006.173.12:09:43.13#ibcon#enter sib2, iclass 16, count 0 2006.173.12:09:43.13#ibcon#flushed, iclass 16, count 0 2006.173.12:09:43.13#ibcon#about to write, iclass 16, count 0 2006.173.12:09:43.13#ibcon#wrote, iclass 16, count 0 2006.173.12:09:43.13#ibcon#about to read 3, iclass 16, count 0 2006.173.12:09:43.15#ibcon#read 3, iclass 16, count 0 2006.173.12:09:43.15#ibcon#about to read 4, iclass 16, count 0 2006.173.12:09:43.15#ibcon#read 4, iclass 16, count 0 2006.173.12:09:43.15#ibcon#about to read 5, iclass 16, count 0 2006.173.12:09:43.15#ibcon#read 5, iclass 16, count 0 2006.173.12:09:43.15#ibcon#about to read 6, iclass 16, count 0 2006.173.12:09:43.15#ibcon#read 6, iclass 16, count 0 2006.173.12:09:43.15#ibcon#end of sib2, iclass 16, count 0 2006.173.12:09:43.15#ibcon#*mode == 0, iclass 16, count 0 2006.173.12:09:43.15#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.12:09:43.15#ibcon#[27=USB\r\n] 2006.173.12:09:43.15#ibcon#*before write, iclass 16, count 0 2006.173.12:09:43.15#ibcon#enter sib2, iclass 16, count 0 2006.173.12:09:43.15#ibcon#flushed, iclass 16, count 0 2006.173.12:09:43.15#ibcon#about to write, iclass 16, count 0 2006.173.12:09:43.15#ibcon#wrote, iclass 16, count 0 2006.173.12:09:43.15#ibcon#about to read 3, iclass 16, count 0 2006.173.12:09:43.18#ibcon#read 3, iclass 16, count 0 2006.173.12:09:43.18#ibcon#about to read 4, iclass 16, count 0 2006.173.12:09:43.18#ibcon#read 4, iclass 16, count 0 2006.173.12:09:43.18#ibcon#about to read 5, iclass 16, count 0 2006.173.12:09:43.18#ibcon#read 5, iclass 16, count 0 2006.173.12:09:43.18#ibcon#about to read 6, iclass 16, count 0 2006.173.12:09:43.18#ibcon#read 6, iclass 16, count 0 2006.173.12:09:43.18#ibcon#end of sib2, iclass 16, count 0 2006.173.12:09:43.18#ibcon#*after write, iclass 16, count 0 2006.173.12:09:43.18#ibcon#*before return 0, iclass 16, count 0 2006.173.12:09:43.18#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.12:09:43.18#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.12:09:43.18#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.12:09:43.18#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.12:09:43.18$vck44/vblo=2,634.99 2006.173.12:09:43.18#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.12:09:43.18#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.12:09:43.18#ibcon#ireg 17 cls_cnt 0 2006.173.12:09:43.18#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.12:09:43.18#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.12:09:43.18#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.12:09:43.18#ibcon#enter wrdev, iclass 18, count 0 2006.173.12:09:43.18#ibcon#first serial, iclass 18, count 0 2006.173.12:09:43.18#ibcon#enter sib2, iclass 18, count 0 2006.173.12:09:43.18#ibcon#flushed, iclass 18, count 0 2006.173.12:09:43.18#ibcon#about to write, iclass 18, count 0 2006.173.12:09:43.18#ibcon#wrote, iclass 18, count 0 2006.173.12:09:43.18#ibcon#about to read 3, iclass 18, count 0 2006.173.12:09:43.20#ibcon#read 3, iclass 18, count 0 2006.173.12:09:43.20#ibcon#about to read 4, iclass 18, count 0 2006.173.12:09:43.20#ibcon#read 4, iclass 18, count 0 2006.173.12:09:43.20#ibcon#about to read 5, iclass 18, count 0 2006.173.12:09:43.20#ibcon#read 5, iclass 18, count 0 2006.173.12:09:43.20#ibcon#about to read 6, iclass 18, count 0 2006.173.12:09:43.20#ibcon#read 6, iclass 18, count 0 2006.173.12:09:43.20#ibcon#end of sib2, iclass 18, count 0 2006.173.12:09:43.20#ibcon#*mode == 0, iclass 18, count 0 2006.173.12:09:43.20#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.12:09:43.20#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.12:09:43.20#ibcon#*before write, iclass 18, count 0 2006.173.12:09:43.20#ibcon#enter sib2, iclass 18, count 0 2006.173.12:09:43.20#ibcon#flushed, iclass 18, count 0 2006.173.12:09:43.20#ibcon#about to write, iclass 18, count 0 2006.173.12:09:43.20#ibcon#wrote, iclass 18, count 0 2006.173.12:09:43.20#ibcon#about to read 3, iclass 18, count 0 2006.173.12:09:43.24#ibcon#read 3, iclass 18, count 0 2006.173.12:09:43.24#ibcon#about to read 4, iclass 18, count 0 2006.173.12:09:43.24#ibcon#read 4, iclass 18, count 0 2006.173.12:09:43.24#ibcon#about to read 5, iclass 18, count 0 2006.173.12:09:43.24#ibcon#read 5, iclass 18, count 0 2006.173.12:09:43.24#ibcon#about to read 6, iclass 18, count 0 2006.173.12:09:43.24#ibcon#read 6, iclass 18, count 0 2006.173.12:09:43.24#ibcon#end of sib2, iclass 18, count 0 2006.173.12:09:43.24#ibcon#*after write, iclass 18, count 0 2006.173.12:09:43.24#ibcon#*before return 0, iclass 18, count 0 2006.173.12:09:43.24#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.12:09:43.24#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.12:09:43.24#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.12:09:43.24#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.12:09:43.24$vck44/vb=2,4 2006.173.12:09:43.24#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.12:09:43.24#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.12:09:43.24#ibcon#ireg 11 cls_cnt 2 2006.173.12:09:43.24#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.12:09:43.30#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.12:09:43.30#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.12:09:43.30#ibcon#enter wrdev, iclass 20, count 2 2006.173.12:09:43.30#ibcon#first serial, iclass 20, count 2 2006.173.12:09:43.30#ibcon#enter sib2, iclass 20, count 2 2006.173.12:09:43.30#ibcon#flushed, iclass 20, count 2 2006.173.12:09:43.30#ibcon#about to write, iclass 20, count 2 2006.173.12:09:43.30#ibcon#wrote, iclass 20, count 2 2006.173.12:09:43.30#ibcon#about to read 3, iclass 20, count 2 2006.173.12:09:43.32#ibcon#read 3, iclass 20, count 2 2006.173.12:09:43.32#ibcon#about to read 4, iclass 20, count 2 2006.173.12:09:43.32#ibcon#read 4, iclass 20, count 2 2006.173.12:09:43.32#ibcon#about to read 5, iclass 20, count 2 2006.173.12:09:43.32#ibcon#read 5, iclass 20, count 2 2006.173.12:09:43.32#ibcon#about to read 6, iclass 20, count 2 2006.173.12:09:43.32#ibcon#read 6, iclass 20, count 2 2006.173.12:09:43.32#ibcon#end of sib2, iclass 20, count 2 2006.173.12:09:43.32#ibcon#*mode == 0, iclass 20, count 2 2006.173.12:09:43.32#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.12:09:43.32#ibcon#[27=AT02-04\r\n] 2006.173.12:09:43.32#ibcon#*before write, iclass 20, count 2 2006.173.12:09:43.32#ibcon#enter sib2, iclass 20, count 2 2006.173.12:09:43.32#ibcon#flushed, iclass 20, count 2 2006.173.12:09:43.32#ibcon#about to write, iclass 20, count 2 2006.173.12:09:43.32#ibcon#wrote, iclass 20, count 2 2006.173.12:09:43.32#ibcon#about to read 3, iclass 20, count 2 2006.173.12:09:43.35#ibcon#read 3, iclass 20, count 2 2006.173.12:09:43.35#ibcon#about to read 4, iclass 20, count 2 2006.173.12:09:43.35#ibcon#read 4, iclass 20, count 2 2006.173.12:09:43.35#ibcon#about to read 5, iclass 20, count 2 2006.173.12:09:43.35#ibcon#read 5, iclass 20, count 2 2006.173.12:09:43.35#ibcon#about to read 6, iclass 20, count 2 2006.173.12:09:43.35#ibcon#read 6, iclass 20, count 2 2006.173.12:09:43.35#ibcon#end of sib2, iclass 20, count 2 2006.173.12:09:43.35#ibcon#*after write, iclass 20, count 2 2006.173.12:09:43.35#ibcon#*before return 0, iclass 20, count 2 2006.173.12:09:43.35#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.12:09:43.35#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.12:09:43.35#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.12:09:43.35#ibcon#ireg 7 cls_cnt 0 2006.173.12:09:43.35#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.12:09:43.47#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.12:09:43.47#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.12:09:43.47#ibcon#enter wrdev, iclass 20, count 0 2006.173.12:09:43.47#ibcon#first serial, iclass 20, count 0 2006.173.12:09:43.47#ibcon#enter sib2, iclass 20, count 0 2006.173.12:09:43.47#ibcon#flushed, iclass 20, count 0 2006.173.12:09:43.47#ibcon#about to write, iclass 20, count 0 2006.173.12:09:43.47#ibcon#wrote, iclass 20, count 0 2006.173.12:09:43.47#ibcon#about to read 3, iclass 20, count 0 2006.173.12:09:43.49#ibcon#read 3, iclass 20, count 0 2006.173.12:09:43.49#ibcon#about to read 4, iclass 20, count 0 2006.173.12:09:43.49#ibcon#read 4, iclass 20, count 0 2006.173.12:09:43.49#ibcon#about to read 5, iclass 20, count 0 2006.173.12:09:43.49#ibcon#read 5, iclass 20, count 0 2006.173.12:09:43.49#ibcon#about to read 6, iclass 20, count 0 2006.173.12:09:43.49#ibcon#read 6, iclass 20, count 0 2006.173.12:09:43.49#ibcon#end of sib2, iclass 20, count 0 2006.173.12:09:43.49#ibcon#*mode == 0, iclass 20, count 0 2006.173.12:09:43.49#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.12:09:43.49#ibcon#[27=USB\r\n] 2006.173.12:09:43.49#ibcon#*before write, iclass 20, count 0 2006.173.12:09:43.49#ibcon#enter sib2, iclass 20, count 0 2006.173.12:09:43.49#ibcon#flushed, iclass 20, count 0 2006.173.12:09:43.49#ibcon#about to write, iclass 20, count 0 2006.173.12:09:43.49#ibcon#wrote, iclass 20, count 0 2006.173.12:09:43.49#ibcon#about to read 3, iclass 20, count 0 2006.173.12:09:43.52#ibcon#read 3, iclass 20, count 0 2006.173.12:09:43.52#ibcon#about to read 4, iclass 20, count 0 2006.173.12:09:43.52#ibcon#read 4, iclass 20, count 0 2006.173.12:09:43.52#ibcon#about to read 5, iclass 20, count 0 2006.173.12:09:43.52#ibcon#read 5, iclass 20, count 0 2006.173.12:09:43.52#ibcon#about to read 6, iclass 20, count 0 2006.173.12:09:43.52#ibcon#read 6, iclass 20, count 0 2006.173.12:09:43.52#ibcon#end of sib2, iclass 20, count 0 2006.173.12:09:43.52#ibcon#*after write, iclass 20, count 0 2006.173.12:09:43.52#ibcon#*before return 0, iclass 20, count 0 2006.173.12:09:43.52#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.12:09:43.52#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.12:09:43.52#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.12:09:43.52#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.12:09:43.52$vck44/vblo=3,649.99 2006.173.12:09:43.52#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.12:09:43.52#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.12:09:43.52#ibcon#ireg 17 cls_cnt 0 2006.173.12:09:43.52#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.12:09:43.52#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.12:09:43.52#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.12:09:43.52#ibcon#enter wrdev, iclass 22, count 0 2006.173.12:09:43.52#ibcon#first serial, iclass 22, count 0 2006.173.12:09:43.52#ibcon#enter sib2, iclass 22, count 0 2006.173.12:09:43.52#ibcon#flushed, iclass 22, count 0 2006.173.12:09:43.52#ibcon#about to write, iclass 22, count 0 2006.173.12:09:43.52#ibcon#wrote, iclass 22, count 0 2006.173.12:09:43.52#ibcon#about to read 3, iclass 22, count 0 2006.173.12:09:43.54#ibcon#read 3, iclass 22, count 0 2006.173.12:09:43.54#ibcon#about to read 4, iclass 22, count 0 2006.173.12:09:43.54#ibcon#read 4, iclass 22, count 0 2006.173.12:09:43.54#ibcon#about to read 5, iclass 22, count 0 2006.173.12:09:43.54#ibcon#read 5, iclass 22, count 0 2006.173.12:09:43.54#ibcon#about to read 6, iclass 22, count 0 2006.173.12:09:43.54#ibcon#read 6, iclass 22, count 0 2006.173.12:09:43.54#ibcon#end of sib2, iclass 22, count 0 2006.173.12:09:43.54#ibcon#*mode == 0, iclass 22, count 0 2006.173.12:09:43.54#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.12:09:43.54#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.12:09:43.54#ibcon#*before write, iclass 22, count 0 2006.173.12:09:43.54#ibcon#enter sib2, iclass 22, count 0 2006.173.12:09:43.54#ibcon#flushed, iclass 22, count 0 2006.173.12:09:43.54#ibcon#about to write, iclass 22, count 0 2006.173.12:09:43.54#ibcon#wrote, iclass 22, count 0 2006.173.12:09:43.54#ibcon#about to read 3, iclass 22, count 0 2006.173.12:09:43.58#ibcon#read 3, iclass 22, count 0 2006.173.12:09:43.58#ibcon#about to read 4, iclass 22, count 0 2006.173.12:09:43.58#ibcon#read 4, iclass 22, count 0 2006.173.12:09:43.58#ibcon#about to read 5, iclass 22, count 0 2006.173.12:09:43.58#ibcon#read 5, iclass 22, count 0 2006.173.12:09:43.58#ibcon#about to read 6, iclass 22, count 0 2006.173.12:09:43.58#ibcon#read 6, iclass 22, count 0 2006.173.12:09:43.58#ibcon#end of sib2, iclass 22, count 0 2006.173.12:09:43.58#ibcon#*after write, iclass 22, count 0 2006.173.12:09:43.58#ibcon#*before return 0, iclass 22, count 0 2006.173.12:09:43.58#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.12:09:43.58#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.12:09:43.58#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.12:09:43.58#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.12:09:43.58$vck44/vb=3,4 2006.173.12:09:43.58#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.12:09:43.58#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.12:09:43.58#ibcon#ireg 11 cls_cnt 2 2006.173.12:09:43.58#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.12:09:43.64#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.12:09:43.64#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.12:09:43.64#ibcon#enter wrdev, iclass 24, count 2 2006.173.12:09:43.64#ibcon#first serial, iclass 24, count 2 2006.173.12:09:43.64#ibcon#enter sib2, iclass 24, count 2 2006.173.12:09:43.64#ibcon#flushed, iclass 24, count 2 2006.173.12:09:43.64#ibcon#about to write, iclass 24, count 2 2006.173.12:09:43.64#ibcon#wrote, iclass 24, count 2 2006.173.12:09:43.64#ibcon#about to read 3, iclass 24, count 2 2006.173.12:09:43.66#ibcon#read 3, iclass 24, count 2 2006.173.12:09:43.66#ibcon#about to read 4, iclass 24, count 2 2006.173.12:09:43.66#ibcon#read 4, iclass 24, count 2 2006.173.12:09:43.66#ibcon#about to read 5, iclass 24, count 2 2006.173.12:09:43.66#ibcon#read 5, iclass 24, count 2 2006.173.12:09:43.66#ibcon#about to read 6, iclass 24, count 2 2006.173.12:09:43.66#ibcon#read 6, iclass 24, count 2 2006.173.12:09:43.66#ibcon#end of sib2, iclass 24, count 2 2006.173.12:09:43.66#ibcon#*mode == 0, iclass 24, count 2 2006.173.12:09:43.66#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.12:09:43.66#ibcon#[27=AT03-04\r\n] 2006.173.12:09:43.66#ibcon#*before write, iclass 24, count 2 2006.173.12:09:43.66#ibcon#enter sib2, iclass 24, count 2 2006.173.12:09:43.66#ibcon#flushed, iclass 24, count 2 2006.173.12:09:43.66#ibcon#about to write, iclass 24, count 2 2006.173.12:09:43.66#ibcon#wrote, iclass 24, count 2 2006.173.12:09:43.66#ibcon#about to read 3, iclass 24, count 2 2006.173.12:09:43.69#ibcon#read 3, iclass 24, count 2 2006.173.12:09:43.69#ibcon#about to read 4, iclass 24, count 2 2006.173.12:09:43.69#ibcon#read 4, iclass 24, count 2 2006.173.12:09:43.69#ibcon#about to read 5, iclass 24, count 2 2006.173.12:09:43.69#ibcon#read 5, iclass 24, count 2 2006.173.12:09:43.69#ibcon#about to read 6, iclass 24, count 2 2006.173.12:09:43.69#ibcon#read 6, iclass 24, count 2 2006.173.12:09:43.69#ibcon#end of sib2, iclass 24, count 2 2006.173.12:09:43.69#ibcon#*after write, iclass 24, count 2 2006.173.12:09:43.69#ibcon#*before return 0, iclass 24, count 2 2006.173.12:09:43.69#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.12:09:43.69#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.12:09:43.69#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.12:09:43.69#ibcon#ireg 7 cls_cnt 0 2006.173.12:09:43.69#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.12:09:43.81#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.12:09:43.81#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.12:09:43.81#ibcon#enter wrdev, iclass 24, count 0 2006.173.12:09:43.81#ibcon#first serial, iclass 24, count 0 2006.173.12:09:43.81#ibcon#enter sib2, iclass 24, count 0 2006.173.12:09:43.81#ibcon#flushed, iclass 24, count 0 2006.173.12:09:43.81#ibcon#about to write, iclass 24, count 0 2006.173.12:09:43.81#ibcon#wrote, iclass 24, count 0 2006.173.12:09:43.81#ibcon#about to read 3, iclass 24, count 0 2006.173.12:09:43.83#ibcon#read 3, iclass 24, count 0 2006.173.12:09:43.83#ibcon#about to read 4, iclass 24, count 0 2006.173.12:09:43.83#ibcon#read 4, iclass 24, count 0 2006.173.12:09:43.83#ibcon#about to read 5, iclass 24, count 0 2006.173.12:09:43.83#ibcon#read 5, iclass 24, count 0 2006.173.12:09:43.83#ibcon#about to read 6, iclass 24, count 0 2006.173.12:09:43.83#ibcon#read 6, iclass 24, count 0 2006.173.12:09:43.83#ibcon#end of sib2, iclass 24, count 0 2006.173.12:09:43.83#ibcon#*mode == 0, iclass 24, count 0 2006.173.12:09:43.83#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.12:09:43.83#ibcon#[27=USB\r\n] 2006.173.12:09:43.83#ibcon#*before write, iclass 24, count 0 2006.173.12:09:43.83#ibcon#enter sib2, iclass 24, count 0 2006.173.12:09:43.83#ibcon#flushed, iclass 24, count 0 2006.173.12:09:43.83#ibcon#about to write, iclass 24, count 0 2006.173.12:09:43.83#ibcon#wrote, iclass 24, count 0 2006.173.12:09:43.83#ibcon#about to read 3, iclass 24, count 0 2006.173.12:09:43.86#ibcon#read 3, iclass 24, count 0 2006.173.12:09:43.86#ibcon#about to read 4, iclass 24, count 0 2006.173.12:09:43.86#ibcon#read 4, iclass 24, count 0 2006.173.12:09:43.86#ibcon#about to read 5, iclass 24, count 0 2006.173.12:09:43.86#ibcon#read 5, iclass 24, count 0 2006.173.12:09:43.86#ibcon#about to read 6, iclass 24, count 0 2006.173.12:09:43.86#ibcon#read 6, iclass 24, count 0 2006.173.12:09:43.86#ibcon#end of sib2, iclass 24, count 0 2006.173.12:09:43.86#ibcon#*after write, iclass 24, count 0 2006.173.12:09:43.86#ibcon#*before return 0, iclass 24, count 0 2006.173.12:09:43.86#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.12:09:43.86#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.12:09:43.86#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.12:09:43.86#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.12:09:43.86$vck44/vblo=4,679.99 2006.173.12:09:43.86#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.12:09:43.86#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.12:09:43.86#ibcon#ireg 17 cls_cnt 0 2006.173.12:09:43.86#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.12:09:43.86#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.12:09:43.86#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.12:09:43.86#ibcon#enter wrdev, iclass 26, count 0 2006.173.12:09:43.86#ibcon#first serial, iclass 26, count 0 2006.173.12:09:43.86#ibcon#enter sib2, iclass 26, count 0 2006.173.12:09:43.86#ibcon#flushed, iclass 26, count 0 2006.173.12:09:43.86#ibcon#about to write, iclass 26, count 0 2006.173.12:09:43.86#ibcon#wrote, iclass 26, count 0 2006.173.12:09:43.86#ibcon#about to read 3, iclass 26, count 0 2006.173.12:09:43.88#ibcon#read 3, iclass 26, count 0 2006.173.12:09:43.88#ibcon#about to read 4, iclass 26, count 0 2006.173.12:09:43.88#ibcon#read 4, iclass 26, count 0 2006.173.12:09:43.88#ibcon#about to read 5, iclass 26, count 0 2006.173.12:09:43.88#ibcon#read 5, iclass 26, count 0 2006.173.12:09:43.88#ibcon#about to read 6, iclass 26, count 0 2006.173.12:09:43.88#ibcon#read 6, iclass 26, count 0 2006.173.12:09:43.88#ibcon#end of sib2, iclass 26, count 0 2006.173.12:09:43.88#ibcon#*mode == 0, iclass 26, count 0 2006.173.12:09:43.88#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.12:09:43.88#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.12:09:43.88#ibcon#*before write, iclass 26, count 0 2006.173.12:09:43.88#ibcon#enter sib2, iclass 26, count 0 2006.173.12:09:43.88#ibcon#flushed, iclass 26, count 0 2006.173.12:09:43.88#ibcon#about to write, iclass 26, count 0 2006.173.12:09:43.88#ibcon#wrote, iclass 26, count 0 2006.173.12:09:43.88#ibcon#about to read 3, iclass 26, count 0 2006.173.12:09:43.92#ibcon#read 3, iclass 26, count 0 2006.173.12:09:43.92#ibcon#about to read 4, iclass 26, count 0 2006.173.12:09:43.92#ibcon#read 4, iclass 26, count 0 2006.173.12:09:43.92#ibcon#about to read 5, iclass 26, count 0 2006.173.12:09:43.92#ibcon#read 5, iclass 26, count 0 2006.173.12:09:43.92#ibcon#about to read 6, iclass 26, count 0 2006.173.12:09:43.92#ibcon#read 6, iclass 26, count 0 2006.173.12:09:43.92#ibcon#end of sib2, iclass 26, count 0 2006.173.12:09:43.92#ibcon#*after write, iclass 26, count 0 2006.173.12:09:43.92#ibcon#*before return 0, iclass 26, count 0 2006.173.12:09:43.92#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.12:09:43.92#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.12:09:43.92#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.12:09:43.92#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.12:09:43.92$vck44/vb=4,4 2006.173.12:09:43.92#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.12:09:43.92#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.12:09:43.92#ibcon#ireg 11 cls_cnt 2 2006.173.12:09:43.92#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.12:09:43.98#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.12:09:43.98#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.12:09:43.98#ibcon#enter wrdev, iclass 28, count 2 2006.173.12:09:43.98#ibcon#first serial, iclass 28, count 2 2006.173.12:09:43.98#ibcon#enter sib2, iclass 28, count 2 2006.173.12:09:43.98#ibcon#flushed, iclass 28, count 2 2006.173.12:09:43.98#ibcon#about to write, iclass 28, count 2 2006.173.12:09:43.98#ibcon#wrote, iclass 28, count 2 2006.173.12:09:43.98#ibcon#about to read 3, iclass 28, count 2 2006.173.12:09:44.00#ibcon#read 3, iclass 28, count 2 2006.173.12:09:44.00#ibcon#about to read 4, iclass 28, count 2 2006.173.12:09:44.00#ibcon#read 4, iclass 28, count 2 2006.173.12:09:44.00#ibcon#about to read 5, iclass 28, count 2 2006.173.12:09:44.00#ibcon#read 5, iclass 28, count 2 2006.173.12:09:44.00#ibcon#about to read 6, iclass 28, count 2 2006.173.12:09:44.00#ibcon#read 6, iclass 28, count 2 2006.173.12:09:44.00#ibcon#end of sib2, iclass 28, count 2 2006.173.12:09:44.00#ibcon#*mode == 0, iclass 28, count 2 2006.173.12:09:44.00#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.12:09:44.00#ibcon#[27=AT04-04\r\n] 2006.173.12:09:44.00#ibcon#*before write, iclass 28, count 2 2006.173.12:09:44.00#ibcon#enter sib2, iclass 28, count 2 2006.173.12:09:44.00#ibcon#flushed, iclass 28, count 2 2006.173.12:09:44.00#ibcon#about to write, iclass 28, count 2 2006.173.12:09:44.00#ibcon#wrote, iclass 28, count 2 2006.173.12:09:44.00#ibcon#about to read 3, iclass 28, count 2 2006.173.12:09:44.03#ibcon#read 3, iclass 28, count 2 2006.173.12:09:44.03#ibcon#about to read 4, iclass 28, count 2 2006.173.12:09:44.03#ibcon#read 4, iclass 28, count 2 2006.173.12:09:44.03#ibcon#about to read 5, iclass 28, count 2 2006.173.12:09:44.03#ibcon#read 5, iclass 28, count 2 2006.173.12:09:44.03#ibcon#about to read 6, iclass 28, count 2 2006.173.12:09:44.03#ibcon#read 6, iclass 28, count 2 2006.173.12:09:44.03#ibcon#end of sib2, iclass 28, count 2 2006.173.12:09:44.03#ibcon#*after write, iclass 28, count 2 2006.173.12:09:44.03#ibcon#*before return 0, iclass 28, count 2 2006.173.12:09:44.03#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.12:09:44.03#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.12:09:44.03#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.12:09:44.03#ibcon#ireg 7 cls_cnt 0 2006.173.12:09:44.03#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.12:09:44.15#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.12:09:44.15#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.12:09:44.15#ibcon#enter wrdev, iclass 28, count 0 2006.173.12:09:44.15#ibcon#first serial, iclass 28, count 0 2006.173.12:09:44.15#ibcon#enter sib2, iclass 28, count 0 2006.173.12:09:44.15#ibcon#flushed, iclass 28, count 0 2006.173.12:09:44.15#ibcon#about to write, iclass 28, count 0 2006.173.12:09:44.15#ibcon#wrote, iclass 28, count 0 2006.173.12:09:44.15#ibcon#about to read 3, iclass 28, count 0 2006.173.12:09:44.17#ibcon#read 3, iclass 28, count 0 2006.173.12:09:44.17#ibcon#about to read 4, iclass 28, count 0 2006.173.12:09:44.17#ibcon#read 4, iclass 28, count 0 2006.173.12:09:44.17#ibcon#about to read 5, iclass 28, count 0 2006.173.12:09:44.17#ibcon#read 5, iclass 28, count 0 2006.173.12:09:44.17#ibcon#about to read 6, iclass 28, count 0 2006.173.12:09:44.17#ibcon#read 6, iclass 28, count 0 2006.173.12:09:44.17#ibcon#end of sib2, iclass 28, count 0 2006.173.12:09:44.17#ibcon#*mode == 0, iclass 28, count 0 2006.173.12:09:44.17#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.12:09:44.17#ibcon#[27=USB\r\n] 2006.173.12:09:44.17#ibcon#*before write, iclass 28, count 0 2006.173.12:09:44.17#ibcon#enter sib2, iclass 28, count 0 2006.173.12:09:44.17#ibcon#flushed, iclass 28, count 0 2006.173.12:09:44.17#ibcon#about to write, iclass 28, count 0 2006.173.12:09:44.17#ibcon#wrote, iclass 28, count 0 2006.173.12:09:44.17#ibcon#about to read 3, iclass 28, count 0 2006.173.12:09:44.20#ibcon#read 3, iclass 28, count 0 2006.173.12:09:44.20#ibcon#about to read 4, iclass 28, count 0 2006.173.12:09:44.20#ibcon#read 4, iclass 28, count 0 2006.173.12:09:44.20#ibcon#about to read 5, iclass 28, count 0 2006.173.12:09:44.20#ibcon#read 5, iclass 28, count 0 2006.173.12:09:44.20#ibcon#about to read 6, iclass 28, count 0 2006.173.12:09:44.20#ibcon#read 6, iclass 28, count 0 2006.173.12:09:44.20#ibcon#end of sib2, iclass 28, count 0 2006.173.12:09:44.20#ibcon#*after write, iclass 28, count 0 2006.173.12:09:44.20#ibcon#*before return 0, iclass 28, count 0 2006.173.12:09:44.20#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.12:09:44.20#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.12:09:44.20#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.12:09:44.20#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.12:09:44.20$vck44/vblo=5,709.99 2006.173.12:09:44.20#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.12:09:44.20#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.12:09:44.20#ibcon#ireg 17 cls_cnt 0 2006.173.12:09:44.20#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.12:09:44.20#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.12:09:44.20#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.12:09:44.20#ibcon#enter wrdev, iclass 30, count 0 2006.173.12:09:44.20#ibcon#first serial, iclass 30, count 0 2006.173.12:09:44.20#ibcon#enter sib2, iclass 30, count 0 2006.173.12:09:44.20#ibcon#flushed, iclass 30, count 0 2006.173.12:09:44.20#ibcon#about to write, iclass 30, count 0 2006.173.12:09:44.20#ibcon#wrote, iclass 30, count 0 2006.173.12:09:44.20#ibcon#about to read 3, iclass 30, count 0 2006.173.12:09:44.22#ibcon#read 3, iclass 30, count 0 2006.173.12:09:44.22#ibcon#about to read 4, iclass 30, count 0 2006.173.12:09:44.22#ibcon#read 4, iclass 30, count 0 2006.173.12:09:44.22#ibcon#about to read 5, iclass 30, count 0 2006.173.12:09:44.22#ibcon#read 5, iclass 30, count 0 2006.173.12:09:44.22#ibcon#about to read 6, iclass 30, count 0 2006.173.12:09:44.22#ibcon#read 6, iclass 30, count 0 2006.173.12:09:44.22#ibcon#end of sib2, iclass 30, count 0 2006.173.12:09:44.22#ibcon#*mode == 0, iclass 30, count 0 2006.173.12:09:44.22#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.12:09:44.22#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.12:09:44.22#ibcon#*before write, iclass 30, count 0 2006.173.12:09:44.22#ibcon#enter sib2, iclass 30, count 0 2006.173.12:09:44.22#ibcon#flushed, iclass 30, count 0 2006.173.12:09:44.22#ibcon#about to write, iclass 30, count 0 2006.173.12:09:44.22#ibcon#wrote, iclass 30, count 0 2006.173.12:09:44.22#ibcon#about to read 3, iclass 30, count 0 2006.173.12:09:44.26#ibcon#read 3, iclass 30, count 0 2006.173.12:09:44.26#ibcon#about to read 4, iclass 30, count 0 2006.173.12:09:44.26#ibcon#read 4, iclass 30, count 0 2006.173.12:09:44.26#ibcon#about to read 5, iclass 30, count 0 2006.173.12:09:44.26#ibcon#read 5, iclass 30, count 0 2006.173.12:09:44.26#ibcon#about to read 6, iclass 30, count 0 2006.173.12:09:44.26#ibcon#read 6, iclass 30, count 0 2006.173.12:09:44.26#ibcon#end of sib2, iclass 30, count 0 2006.173.12:09:44.26#ibcon#*after write, iclass 30, count 0 2006.173.12:09:44.26#ibcon#*before return 0, iclass 30, count 0 2006.173.12:09:44.26#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.12:09:44.26#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.12:09:44.26#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.12:09:44.26#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.12:09:44.26$vck44/vb=5,4 2006.173.12:09:44.26#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.173.12:09:44.26#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.173.12:09:44.26#ibcon#ireg 11 cls_cnt 2 2006.173.12:09:44.26#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.12:09:44.32#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.12:09:44.32#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.12:09:44.32#ibcon#enter wrdev, iclass 32, count 2 2006.173.12:09:44.32#ibcon#first serial, iclass 32, count 2 2006.173.12:09:44.32#ibcon#enter sib2, iclass 32, count 2 2006.173.12:09:44.32#ibcon#flushed, iclass 32, count 2 2006.173.12:09:44.32#ibcon#about to write, iclass 32, count 2 2006.173.12:09:44.32#ibcon#wrote, iclass 32, count 2 2006.173.12:09:44.32#ibcon#about to read 3, iclass 32, count 2 2006.173.12:09:44.34#ibcon#read 3, iclass 32, count 2 2006.173.12:09:44.34#ibcon#about to read 4, iclass 32, count 2 2006.173.12:09:44.34#ibcon#read 4, iclass 32, count 2 2006.173.12:09:44.34#ibcon#about to read 5, iclass 32, count 2 2006.173.12:09:44.34#ibcon#read 5, iclass 32, count 2 2006.173.12:09:44.34#ibcon#about to read 6, iclass 32, count 2 2006.173.12:09:44.34#ibcon#read 6, iclass 32, count 2 2006.173.12:09:44.34#ibcon#end of sib2, iclass 32, count 2 2006.173.12:09:44.34#ibcon#*mode == 0, iclass 32, count 2 2006.173.12:09:44.34#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.173.12:09:44.34#ibcon#[27=AT05-04\r\n] 2006.173.12:09:44.34#ibcon#*before write, iclass 32, count 2 2006.173.12:09:44.34#ibcon#enter sib2, iclass 32, count 2 2006.173.12:09:44.34#ibcon#flushed, iclass 32, count 2 2006.173.12:09:44.34#ibcon#about to write, iclass 32, count 2 2006.173.12:09:44.34#ibcon#wrote, iclass 32, count 2 2006.173.12:09:44.34#ibcon#about to read 3, iclass 32, count 2 2006.173.12:09:44.37#ibcon#read 3, iclass 32, count 2 2006.173.12:09:44.37#ibcon#about to read 4, iclass 32, count 2 2006.173.12:09:44.37#ibcon#read 4, iclass 32, count 2 2006.173.12:09:44.37#ibcon#about to read 5, iclass 32, count 2 2006.173.12:09:44.37#ibcon#read 5, iclass 32, count 2 2006.173.12:09:44.37#ibcon#about to read 6, iclass 32, count 2 2006.173.12:09:44.37#ibcon#read 6, iclass 32, count 2 2006.173.12:09:44.37#ibcon#end of sib2, iclass 32, count 2 2006.173.12:09:44.37#ibcon#*after write, iclass 32, count 2 2006.173.12:09:44.37#ibcon#*before return 0, iclass 32, count 2 2006.173.12:09:44.37#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.12:09:44.37#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.173.12:09:44.37#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.173.12:09:44.37#ibcon#ireg 7 cls_cnt 0 2006.173.12:09:44.37#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.12:09:44.49#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.12:09:44.49#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.12:09:44.49#ibcon#enter wrdev, iclass 32, count 0 2006.173.12:09:44.49#ibcon#first serial, iclass 32, count 0 2006.173.12:09:44.49#ibcon#enter sib2, iclass 32, count 0 2006.173.12:09:44.49#ibcon#flushed, iclass 32, count 0 2006.173.12:09:44.49#ibcon#about to write, iclass 32, count 0 2006.173.12:09:44.49#ibcon#wrote, iclass 32, count 0 2006.173.12:09:44.49#ibcon#about to read 3, iclass 32, count 0 2006.173.12:09:44.51#ibcon#read 3, iclass 32, count 0 2006.173.12:09:44.51#ibcon#about to read 4, iclass 32, count 0 2006.173.12:09:44.51#ibcon#read 4, iclass 32, count 0 2006.173.12:09:44.51#ibcon#about to read 5, iclass 32, count 0 2006.173.12:09:44.51#ibcon#read 5, iclass 32, count 0 2006.173.12:09:44.51#ibcon#about to read 6, iclass 32, count 0 2006.173.12:09:44.51#ibcon#read 6, iclass 32, count 0 2006.173.12:09:44.51#ibcon#end of sib2, iclass 32, count 0 2006.173.12:09:44.51#ibcon#*mode == 0, iclass 32, count 0 2006.173.12:09:44.51#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.12:09:44.51#ibcon#[27=USB\r\n] 2006.173.12:09:44.51#ibcon#*before write, iclass 32, count 0 2006.173.12:09:44.51#ibcon#enter sib2, iclass 32, count 0 2006.173.12:09:44.51#ibcon#flushed, iclass 32, count 0 2006.173.12:09:44.51#ibcon#about to write, iclass 32, count 0 2006.173.12:09:44.51#ibcon#wrote, iclass 32, count 0 2006.173.12:09:44.51#ibcon#about to read 3, iclass 32, count 0 2006.173.12:09:44.54#ibcon#read 3, iclass 32, count 0 2006.173.12:09:44.54#ibcon#about to read 4, iclass 32, count 0 2006.173.12:09:44.54#ibcon#read 4, iclass 32, count 0 2006.173.12:09:44.54#ibcon#about to read 5, iclass 32, count 0 2006.173.12:09:44.54#ibcon#read 5, iclass 32, count 0 2006.173.12:09:44.54#ibcon#about to read 6, iclass 32, count 0 2006.173.12:09:44.54#ibcon#read 6, iclass 32, count 0 2006.173.12:09:44.54#ibcon#end of sib2, iclass 32, count 0 2006.173.12:09:44.54#ibcon#*after write, iclass 32, count 0 2006.173.12:09:44.54#ibcon#*before return 0, iclass 32, count 0 2006.173.12:09:44.54#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.12:09:44.54#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.173.12:09:44.54#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.12:09:44.54#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.12:09:44.54$vck44/vblo=6,719.99 2006.173.12:09:44.54#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.12:09:44.54#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.12:09:44.54#ibcon#ireg 17 cls_cnt 0 2006.173.12:09:44.54#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.12:09:44.54#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.12:09:44.54#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.12:09:44.54#ibcon#enter wrdev, iclass 34, count 0 2006.173.12:09:44.54#ibcon#first serial, iclass 34, count 0 2006.173.12:09:44.54#ibcon#enter sib2, iclass 34, count 0 2006.173.12:09:44.54#ibcon#flushed, iclass 34, count 0 2006.173.12:09:44.54#ibcon#about to write, iclass 34, count 0 2006.173.12:09:44.54#ibcon#wrote, iclass 34, count 0 2006.173.12:09:44.54#ibcon#about to read 3, iclass 34, count 0 2006.173.12:09:44.56#ibcon#read 3, iclass 34, count 0 2006.173.12:09:44.56#ibcon#about to read 4, iclass 34, count 0 2006.173.12:09:44.56#ibcon#read 4, iclass 34, count 0 2006.173.12:09:44.56#ibcon#about to read 5, iclass 34, count 0 2006.173.12:09:44.56#ibcon#read 5, iclass 34, count 0 2006.173.12:09:44.56#ibcon#about to read 6, iclass 34, count 0 2006.173.12:09:44.56#ibcon#read 6, iclass 34, count 0 2006.173.12:09:44.56#ibcon#end of sib2, iclass 34, count 0 2006.173.12:09:44.56#ibcon#*mode == 0, iclass 34, count 0 2006.173.12:09:44.56#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.12:09:44.56#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.12:09:44.56#ibcon#*before write, iclass 34, count 0 2006.173.12:09:44.56#ibcon#enter sib2, iclass 34, count 0 2006.173.12:09:44.56#ibcon#flushed, iclass 34, count 0 2006.173.12:09:44.56#ibcon#about to write, iclass 34, count 0 2006.173.12:09:44.56#ibcon#wrote, iclass 34, count 0 2006.173.12:09:44.56#ibcon#about to read 3, iclass 34, count 0 2006.173.12:09:44.60#ibcon#read 3, iclass 34, count 0 2006.173.12:09:44.60#ibcon#about to read 4, iclass 34, count 0 2006.173.12:09:44.60#ibcon#read 4, iclass 34, count 0 2006.173.12:09:44.60#ibcon#about to read 5, iclass 34, count 0 2006.173.12:09:44.60#ibcon#read 5, iclass 34, count 0 2006.173.12:09:44.60#ibcon#about to read 6, iclass 34, count 0 2006.173.12:09:44.60#ibcon#read 6, iclass 34, count 0 2006.173.12:09:44.60#ibcon#end of sib2, iclass 34, count 0 2006.173.12:09:44.60#ibcon#*after write, iclass 34, count 0 2006.173.12:09:44.60#ibcon#*before return 0, iclass 34, count 0 2006.173.12:09:44.60#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.12:09:44.60#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.12:09:44.60#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.12:09:44.60#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.12:09:44.60$vck44/vb=6,4 2006.173.12:09:44.60#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.12:09:44.60#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.12:09:44.60#ibcon#ireg 11 cls_cnt 2 2006.173.12:09:44.60#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.12:09:44.66#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.12:09:44.66#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.12:09:44.66#ibcon#enter wrdev, iclass 36, count 2 2006.173.12:09:44.66#ibcon#first serial, iclass 36, count 2 2006.173.12:09:44.66#ibcon#enter sib2, iclass 36, count 2 2006.173.12:09:44.66#ibcon#flushed, iclass 36, count 2 2006.173.12:09:44.66#ibcon#about to write, iclass 36, count 2 2006.173.12:09:44.66#ibcon#wrote, iclass 36, count 2 2006.173.12:09:44.66#ibcon#about to read 3, iclass 36, count 2 2006.173.12:09:44.68#ibcon#read 3, iclass 36, count 2 2006.173.12:09:44.68#ibcon#about to read 4, iclass 36, count 2 2006.173.12:09:44.68#ibcon#read 4, iclass 36, count 2 2006.173.12:09:44.68#ibcon#about to read 5, iclass 36, count 2 2006.173.12:09:44.68#ibcon#read 5, iclass 36, count 2 2006.173.12:09:44.68#ibcon#about to read 6, iclass 36, count 2 2006.173.12:09:44.68#ibcon#read 6, iclass 36, count 2 2006.173.12:09:44.68#ibcon#end of sib2, iclass 36, count 2 2006.173.12:09:44.68#ibcon#*mode == 0, iclass 36, count 2 2006.173.12:09:44.68#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.12:09:44.68#ibcon#[27=AT06-04\r\n] 2006.173.12:09:44.68#ibcon#*before write, iclass 36, count 2 2006.173.12:09:44.68#ibcon#enter sib2, iclass 36, count 2 2006.173.12:09:44.68#ibcon#flushed, iclass 36, count 2 2006.173.12:09:44.68#ibcon#about to write, iclass 36, count 2 2006.173.12:09:44.68#ibcon#wrote, iclass 36, count 2 2006.173.12:09:44.68#ibcon#about to read 3, iclass 36, count 2 2006.173.12:09:44.71#ibcon#read 3, iclass 36, count 2 2006.173.12:09:44.71#ibcon#about to read 4, iclass 36, count 2 2006.173.12:09:44.71#ibcon#read 4, iclass 36, count 2 2006.173.12:09:44.71#ibcon#about to read 5, iclass 36, count 2 2006.173.12:09:44.71#ibcon#read 5, iclass 36, count 2 2006.173.12:09:44.71#ibcon#about to read 6, iclass 36, count 2 2006.173.12:09:44.71#ibcon#read 6, iclass 36, count 2 2006.173.12:09:44.71#ibcon#end of sib2, iclass 36, count 2 2006.173.12:09:44.71#ibcon#*after write, iclass 36, count 2 2006.173.12:09:44.71#ibcon#*before return 0, iclass 36, count 2 2006.173.12:09:44.71#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.12:09:44.71#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.12:09:44.71#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.12:09:44.71#ibcon#ireg 7 cls_cnt 0 2006.173.12:09:44.71#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.12:09:44.83#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.12:09:44.83#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.12:09:44.83#ibcon#enter wrdev, iclass 36, count 0 2006.173.12:09:44.83#ibcon#first serial, iclass 36, count 0 2006.173.12:09:44.83#ibcon#enter sib2, iclass 36, count 0 2006.173.12:09:44.83#ibcon#flushed, iclass 36, count 0 2006.173.12:09:44.83#ibcon#about to write, iclass 36, count 0 2006.173.12:09:44.83#ibcon#wrote, iclass 36, count 0 2006.173.12:09:44.83#ibcon#about to read 3, iclass 36, count 0 2006.173.12:09:44.85#ibcon#read 3, iclass 36, count 0 2006.173.12:09:44.85#ibcon#about to read 4, iclass 36, count 0 2006.173.12:09:44.85#ibcon#read 4, iclass 36, count 0 2006.173.12:09:44.85#ibcon#about to read 5, iclass 36, count 0 2006.173.12:09:44.85#ibcon#read 5, iclass 36, count 0 2006.173.12:09:44.85#ibcon#about to read 6, iclass 36, count 0 2006.173.12:09:44.85#ibcon#read 6, iclass 36, count 0 2006.173.12:09:44.85#ibcon#end of sib2, iclass 36, count 0 2006.173.12:09:44.85#ibcon#*mode == 0, iclass 36, count 0 2006.173.12:09:44.85#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.12:09:44.85#ibcon#[27=USB\r\n] 2006.173.12:09:44.85#ibcon#*before write, iclass 36, count 0 2006.173.12:09:44.85#ibcon#enter sib2, iclass 36, count 0 2006.173.12:09:44.85#ibcon#flushed, iclass 36, count 0 2006.173.12:09:44.85#ibcon#about to write, iclass 36, count 0 2006.173.12:09:44.85#ibcon#wrote, iclass 36, count 0 2006.173.12:09:44.85#ibcon#about to read 3, iclass 36, count 0 2006.173.12:09:44.88#ibcon#read 3, iclass 36, count 0 2006.173.12:09:44.88#ibcon#about to read 4, iclass 36, count 0 2006.173.12:09:44.88#ibcon#read 4, iclass 36, count 0 2006.173.12:09:44.88#ibcon#about to read 5, iclass 36, count 0 2006.173.12:09:44.88#ibcon#read 5, iclass 36, count 0 2006.173.12:09:44.88#ibcon#about to read 6, iclass 36, count 0 2006.173.12:09:44.88#ibcon#read 6, iclass 36, count 0 2006.173.12:09:44.88#ibcon#end of sib2, iclass 36, count 0 2006.173.12:09:44.88#ibcon#*after write, iclass 36, count 0 2006.173.12:09:44.88#ibcon#*before return 0, iclass 36, count 0 2006.173.12:09:44.88#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.12:09:44.88#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.12:09:44.88#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.12:09:44.88#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.12:09:44.88$vck44/vblo=7,734.99 2006.173.12:09:44.88#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.12:09:44.88#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.12:09:44.88#ibcon#ireg 17 cls_cnt 0 2006.173.12:09:44.88#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.12:09:44.88#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.12:09:44.88#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.12:09:44.88#ibcon#enter wrdev, iclass 38, count 0 2006.173.12:09:44.88#ibcon#first serial, iclass 38, count 0 2006.173.12:09:44.88#ibcon#enter sib2, iclass 38, count 0 2006.173.12:09:44.88#ibcon#flushed, iclass 38, count 0 2006.173.12:09:44.88#ibcon#about to write, iclass 38, count 0 2006.173.12:09:44.88#ibcon#wrote, iclass 38, count 0 2006.173.12:09:44.88#ibcon#about to read 3, iclass 38, count 0 2006.173.12:09:44.90#ibcon#read 3, iclass 38, count 0 2006.173.12:09:44.90#ibcon#about to read 4, iclass 38, count 0 2006.173.12:09:44.90#ibcon#read 4, iclass 38, count 0 2006.173.12:09:44.90#ibcon#about to read 5, iclass 38, count 0 2006.173.12:09:44.90#ibcon#read 5, iclass 38, count 0 2006.173.12:09:44.90#ibcon#about to read 6, iclass 38, count 0 2006.173.12:09:44.90#ibcon#read 6, iclass 38, count 0 2006.173.12:09:44.90#ibcon#end of sib2, iclass 38, count 0 2006.173.12:09:44.90#ibcon#*mode == 0, iclass 38, count 0 2006.173.12:09:44.90#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.12:09:44.90#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.12:09:44.90#ibcon#*before write, iclass 38, count 0 2006.173.12:09:44.90#ibcon#enter sib2, iclass 38, count 0 2006.173.12:09:44.90#ibcon#flushed, iclass 38, count 0 2006.173.12:09:44.90#ibcon#about to write, iclass 38, count 0 2006.173.12:09:44.90#ibcon#wrote, iclass 38, count 0 2006.173.12:09:44.90#ibcon#about to read 3, iclass 38, count 0 2006.173.12:09:44.94#ibcon#read 3, iclass 38, count 0 2006.173.12:09:44.94#ibcon#about to read 4, iclass 38, count 0 2006.173.12:09:44.94#ibcon#read 4, iclass 38, count 0 2006.173.12:09:44.94#ibcon#about to read 5, iclass 38, count 0 2006.173.12:09:44.94#ibcon#read 5, iclass 38, count 0 2006.173.12:09:44.94#ibcon#about to read 6, iclass 38, count 0 2006.173.12:09:44.94#ibcon#read 6, iclass 38, count 0 2006.173.12:09:44.94#ibcon#end of sib2, iclass 38, count 0 2006.173.12:09:44.94#ibcon#*after write, iclass 38, count 0 2006.173.12:09:44.94#ibcon#*before return 0, iclass 38, count 0 2006.173.12:09:44.94#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.12:09:44.94#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.12:09:44.94#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.12:09:44.94#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.12:09:44.94$vck44/vb=7,4 2006.173.12:09:44.94#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.12:09:44.94#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.12:09:44.94#ibcon#ireg 11 cls_cnt 2 2006.173.12:09:44.94#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.12:09:45.00#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.12:09:45.00#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.12:09:45.00#ibcon#enter wrdev, iclass 40, count 2 2006.173.12:09:45.00#ibcon#first serial, iclass 40, count 2 2006.173.12:09:45.00#ibcon#enter sib2, iclass 40, count 2 2006.173.12:09:45.00#ibcon#flushed, iclass 40, count 2 2006.173.12:09:45.00#ibcon#about to write, iclass 40, count 2 2006.173.12:09:45.00#ibcon#wrote, iclass 40, count 2 2006.173.12:09:45.00#ibcon#about to read 3, iclass 40, count 2 2006.173.12:09:45.02#ibcon#read 3, iclass 40, count 2 2006.173.12:09:45.02#ibcon#about to read 4, iclass 40, count 2 2006.173.12:09:45.02#ibcon#read 4, iclass 40, count 2 2006.173.12:09:45.02#ibcon#about to read 5, iclass 40, count 2 2006.173.12:09:45.02#ibcon#read 5, iclass 40, count 2 2006.173.12:09:45.02#ibcon#about to read 6, iclass 40, count 2 2006.173.12:09:45.02#ibcon#read 6, iclass 40, count 2 2006.173.12:09:45.02#ibcon#end of sib2, iclass 40, count 2 2006.173.12:09:45.02#ibcon#*mode == 0, iclass 40, count 2 2006.173.12:09:45.02#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.12:09:45.02#ibcon#[27=AT07-04\r\n] 2006.173.12:09:45.02#ibcon#*before write, iclass 40, count 2 2006.173.12:09:45.02#ibcon#enter sib2, iclass 40, count 2 2006.173.12:09:45.02#ibcon#flushed, iclass 40, count 2 2006.173.12:09:45.02#ibcon#about to write, iclass 40, count 2 2006.173.12:09:45.02#ibcon#wrote, iclass 40, count 2 2006.173.12:09:45.02#ibcon#about to read 3, iclass 40, count 2 2006.173.12:09:45.05#ibcon#read 3, iclass 40, count 2 2006.173.12:09:45.05#ibcon#about to read 4, iclass 40, count 2 2006.173.12:09:45.05#ibcon#read 4, iclass 40, count 2 2006.173.12:09:45.05#ibcon#about to read 5, iclass 40, count 2 2006.173.12:09:45.05#ibcon#read 5, iclass 40, count 2 2006.173.12:09:45.05#ibcon#about to read 6, iclass 40, count 2 2006.173.12:09:45.05#ibcon#read 6, iclass 40, count 2 2006.173.12:09:45.05#ibcon#end of sib2, iclass 40, count 2 2006.173.12:09:45.05#ibcon#*after write, iclass 40, count 2 2006.173.12:09:45.05#ibcon#*before return 0, iclass 40, count 2 2006.173.12:09:45.05#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.12:09:45.05#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.12:09:45.05#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.12:09:45.05#ibcon#ireg 7 cls_cnt 0 2006.173.12:09:45.05#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.12:09:45.17#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.12:09:45.17#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.12:09:45.17#ibcon#enter wrdev, iclass 40, count 0 2006.173.12:09:45.17#ibcon#first serial, iclass 40, count 0 2006.173.12:09:45.17#ibcon#enter sib2, iclass 40, count 0 2006.173.12:09:45.17#ibcon#flushed, iclass 40, count 0 2006.173.12:09:45.17#ibcon#about to write, iclass 40, count 0 2006.173.12:09:45.17#ibcon#wrote, iclass 40, count 0 2006.173.12:09:45.17#ibcon#about to read 3, iclass 40, count 0 2006.173.12:09:45.19#ibcon#read 3, iclass 40, count 0 2006.173.12:09:45.19#ibcon#about to read 4, iclass 40, count 0 2006.173.12:09:45.19#ibcon#read 4, iclass 40, count 0 2006.173.12:09:45.19#ibcon#about to read 5, iclass 40, count 0 2006.173.12:09:45.19#ibcon#read 5, iclass 40, count 0 2006.173.12:09:45.19#ibcon#about to read 6, iclass 40, count 0 2006.173.12:09:45.19#ibcon#read 6, iclass 40, count 0 2006.173.12:09:45.19#ibcon#end of sib2, iclass 40, count 0 2006.173.12:09:45.19#ibcon#*mode == 0, iclass 40, count 0 2006.173.12:09:45.19#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.12:09:45.19#ibcon#[27=USB\r\n] 2006.173.12:09:45.19#ibcon#*before write, iclass 40, count 0 2006.173.12:09:45.19#ibcon#enter sib2, iclass 40, count 0 2006.173.12:09:45.19#ibcon#flushed, iclass 40, count 0 2006.173.12:09:45.19#ibcon#about to write, iclass 40, count 0 2006.173.12:09:45.19#ibcon#wrote, iclass 40, count 0 2006.173.12:09:45.19#ibcon#about to read 3, iclass 40, count 0 2006.173.12:09:45.22#ibcon#read 3, iclass 40, count 0 2006.173.12:09:45.22#ibcon#about to read 4, iclass 40, count 0 2006.173.12:09:45.22#ibcon#read 4, iclass 40, count 0 2006.173.12:09:45.22#ibcon#about to read 5, iclass 40, count 0 2006.173.12:09:45.22#ibcon#read 5, iclass 40, count 0 2006.173.12:09:45.22#ibcon#about to read 6, iclass 40, count 0 2006.173.12:09:45.22#ibcon#read 6, iclass 40, count 0 2006.173.12:09:45.22#ibcon#end of sib2, iclass 40, count 0 2006.173.12:09:45.22#ibcon#*after write, iclass 40, count 0 2006.173.12:09:45.22#ibcon#*before return 0, iclass 40, count 0 2006.173.12:09:45.22#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.12:09:45.22#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.12:09:45.22#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.12:09:45.22#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.12:09:45.22$vck44/vblo=8,744.99 2006.173.12:09:45.22#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.12:09:45.22#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.12:09:45.22#ibcon#ireg 17 cls_cnt 0 2006.173.12:09:45.22#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.12:09:45.22#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.12:09:45.22#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.12:09:45.22#ibcon#enter wrdev, iclass 4, count 0 2006.173.12:09:45.22#ibcon#first serial, iclass 4, count 0 2006.173.12:09:45.22#ibcon#enter sib2, iclass 4, count 0 2006.173.12:09:45.22#ibcon#flushed, iclass 4, count 0 2006.173.12:09:45.22#ibcon#about to write, iclass 4, count 0 2006.173.12:09:45.22#ibcon#wrote, iclass 4, count 0 2006.173.12:09:45.22#ibcon#about to read 3, iclass 4, count 0 2006.173.12:09:45.24#ibcon#read 3, iclass 4, count 0 2006.173.12:09:45.24#ibcon#about to read 4, iclass 4, count 0 2006.173.12:09:45.24#ibcon#read 4, iclass 4, count 0 2006.173.12:09:45.24#ibcon#about to read 5, iclass 4, count 0 2006.173.12:09:45.24#ibcon#read 5, iclass 4, count 0 2006.173.12:09:45.24#ibcon#about to read 6, iclass 4, count 0 2006.173.12:09:45.24#ibcon#read 6, iclass 4, count 0 2006.173.12:09:45.24#ibcon#end of sib2, iclass 4, count 0 2006.173.12:09:45.24#ibcon#*mode == 0, iclass 4, count 0 2006.173.12:09:45.24#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.12:09:45.24#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.12:09:45.24#ibcon#*before write, iclass 4, count 0 2006.173.12:09:45.24#ibcon#enter sib2, iclass 4, count 0 2006.173.12:09:45.24#ibcon#flushed, iclass 4, count 0 2006.173.12:09:45.24#ibcon#about to write, iclass 4, count 0 2006.173.12:09:45.24#ibcon#wrote, iclass 4, count 0 2006.173.12:09:45.24#ibcon#about to read 3, iclass 4, count 0 2006.173.12:09:45.28#ibcon#read 3, iclass 4, count 0 2006.173.12:09:45.28#ibcon#about to read 4, iclass 4, count 0 2006.173.12:09:45.28#ibcon#read 4, iclass 4, count 0 2006.173.12:09:45.28#ibcon#about to read 5, iclass 4, count 0 2006.173.12:09:45.28#ibcon#read 5, iclass 4, count 0 2006.173.12:09:45.28#ibcon#about to read 6, iclass 4, count 0 2006.173.12:09:45.28#ibcon#read 6, iclass 4, count 0 2006.173.12:09:45.28#ibcon#end of sib2, iclass 4, count 0 2006.173.12:09:45.28#ibcon#*after write, iclass 4, count 0 2006.173.12:09:45.28#ibcon#*before return 0, iclass 4, count 0 2006.173.12:09:45.28#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.12:09:45.28#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.12:09:45.28#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.12:09:45.28#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.12:09:45.28$vck44/vb=8,4 2006.173.12:09:45.28#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.12:09:45.28#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.12:09:45.28#ibcon#ireg 11 cls_cnt 2 2006.173.12:09:45.28#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.12:09:45.34#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.12:09:45.34#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.12:09:45.34#ibcon#enter wrdev, iclass 6, count 2 2006.173.12:09:45.34#ibcon#first serial, iclass 6, count 2 2006.173.12:09:45.34#ibcon#enter sib2, iclass 6, count 2 2006.173.12:09:45.34#ibcon#flushed, iclass 6, count 2 2006.173.12:09:45.34#ibcon#about to write, iclass 6, count 2 2006.173.12:09:45.34#ibcon#wrote, iclass 6, count 2 2006.173.12:09:45.34#ibcon#about to read 3, iclass 6, count 2 2006.173.12:09:45.36#ibcon#read 3, iclass 6, count 2 2006.173.12:09:45.36#ibcon#about to read 4, iclass 6, count 2 2006.173.12:09:45.36#ibcon#read 4, iclass 6, count 2 2006.173.12:09:45.36#ibcon#about to read 5, iclass 6, count 2 2006.173.12:09:45.36#ibcon#read 5, iclass 6, count 2 2006.173.12:09:45.36#ibcon#about to read 6, iclass 6, count 2 2006.173.12:09:45.36#ibcon#read 6, iclass 6, count 2 2006.173.12:09:45.36#ibcon#end of sib2, iclass 6, count 2 2006.173.12:09:45.36#ibcon#*mode == 0, iclass 6, count 2 2006.173.12:09:45.36#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.12:09:45.36#ibcon#[27=AT08-04\r\n] 2006.173.12:09:45.36#ibcon#*before write, iclass 6, count 2 2006.173.12:09:45.36#ibcon#enter sib2, iclass 6, count 2 2006.173.12:09:45.36#ibcon#flushed, iclass 6, count 2 2006.173.12:09:45.36#ibcon#about to write, iclass 6, count 2 2006.173.12:09:45.36#ibcon#wrote, iclass 6, count 2 2006.173.12:09:45.36#ibcon#about to read 3, iclass 6, count 2 2006.173.12:09:45.39#ibcon#read 3, iclass 6, count 2 2006.173.12:09:45.39#ibcon#about to read 4, iclass 6, count 2 2006.173.12:09:45.39#ibcon#read 4, iclass 6, count 2 2006.173.12:09:45.39#ibcon#about to read 5, iclass 6, count 2 2006.173.12:09:45.39#ibcon#read 5, iclass 6, count 2 2006.173.12:09:45.39#ibcon#about to read 6, iclass 6, count 2 2006.173.12:09:45.39#ibcon#read 6, iclass 6, count 2 2006.173.12:09:45.39#ibcon#end of sib2, iclass 6, count 2 2006.173.12:09:45.39#ibcon#*after write, iclass 6, count 2 2006.173.12:09:45.39#ibcon#*before return 0, iclass 6, count 2 2006.173.12:09:45.39#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.12:09:45.39#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.12:09:45.39#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.12:09:45.39#ibcon#ireg 7 cls_cnt 0 2006.173.12:09:45.39#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.12:09:45.51#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.12:09:45.51#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.12:09:45.51#ibcon#enter wrdev, iclass 6, count 0 2006.173.12:09:45.51#ibcon#first serial, iclass 6, count 0 2006.173.12:09:45.51#ibcon#enter sib2, iclass 6, count 0 2006.173.12:09:45.51#ibcon#flushed, iclass 6, count 0 2006.173.12:09:45.51#ibcon#about to write, iclass 6, count 0 2006.173.12:09:45.51#ibcon#wrote, iclass 6, count 0 2006.173.12:09:45.51#ibcon#about to read 3, iclass 6, count 0 2006.173.12:09:45.53#ibcon#read 3, iclass 6, count 0 2006.173.12:09:45.53#ibcon#about to read 4, iclass 6, count 0 2006.173.12:09:45.53#ibcon#read 4, iclass 6, count 0 2006.173.12:09:45.53#ibcon#about to read 5, iclass 6, count 0 2006.173.12:09:45.53#ibcon#read 5, iclass 6, count 0 2006.173.12:09:45.53#ibcon#about to read 6, iclass 6, count 0 2006.173.12:09:45.53#ibcon#read 6, iclass 6, count 0 2006.173.12:09:45.53#ibcon#end of sib2, iclass 6, count 0 2006.173.12:09:45.53#ibcon#*mode == 0, iclass 6, count 0 2006.173.12:09:45.53#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.12:09:45.53#ibcon#[27=USB\r\n] 2006.173.12:09:45.53#ibcon#*before write, iclass 6, count 0 2006.173.12:09:45.53#ibcon#enter sib2, iclass 6, count 0 2006.173.12:09:45.53#ibcon#flushed, iclass 6, count 0 2006.173.12:09:45.53#ibcon#about to write, iclass 6, count 0 2006.173.12:09:45.53#ibcon#wrote, iclass 6, count 0 2006.173.12:09:45.53#ibcon#about to read 3, iclass 6, count 0 2006.173.12:09:45.56#ibcon#read 3, iclass 6, count 0 2006.173.12:09:45.56#ibcon#about to read 4, iclass 6, count 0 2006.173.12:09:45.56#ibcon#read 4, iclass 6, count 0 2006.173.12:09:45.56#ibcon#about to read 5, iclass 6, count 0 2006.173.12:09:45.56#ibcon#read 5, iclass 6, count 0 2006.173.12:09:45.56#ibcon#about to read 6, iclass 6, count 0 2006.173.12:09:45.56#ibcon#read 6, iclass 6, count 0 2006.173.12:09:45.56#ibcon#end of sib2, iclass 6, count 0 2006.173.12:09:45.56#ibcon#*after write, iclass 6, count 0 2006.173.12:09:45.56#ibcon#*before return 0, iclass 6, count 0 2006.173.12:09:45.56#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.12:09:45.56#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.12:09:45.56#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.12:09:45.56#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.12:09:45.56$vck44/vabw=wide 2006.173.12:09:45.56#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.12:09:45.56#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.12:09:45.56#ibcon#ireg 8 cls_cnt 0 2006.173.12:09:45.56#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.12:09:45.56#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.12:09:45.56#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.12:09:45.56#ibcon#enter wrdev, iclass 10, count 0 2006.173.12:09:45.56#ibcon#first serial, iclass 10, count 0 2006.173.12:09:45.56#ibcon#enter sib2, iclass 10, count 0 2006.173.12:09:45.56#ibcon#flushed, iclass 10, count 0 2006.173.12:09:45.56#ibcon#about to write, iclass 10, count 0 2006.173.12:09:45.56#ibcon#wrote, iclass 10, count 0 2006.173.12:09:45.56#ibcon#about to read 3, iclass 10, count 0 2006.173.12:09:45.58#ibcon#read 3, iclass 10, count 0 2006.173.12:09:45.58#ibcon#about to read 4, iclass 10, count 0 2006.173.12:09:45.58#ibcon#read 4, iclass 10, count 0 2006.173.12:09:45.58#ibcon#about to read 5, iclass 10, count 0 2006.173.12:09:45.58#ibcon#read 5, iclass 10, count 0 2006.173.12:09:45.58#ibcon#about to read 6, iclass 10, count 0 2006.173.12:09:45.58#ibcon#read 6, iclass 10, count 0 2006.173.12:09:45.58#ibcon#end of sib2, iclass 10, count 0 2006.173.12:09:45.58#ibcon#*mode == 0, iclass 10, count 0 2006.173.12:09:45.58#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.12:09:45.58#ibcon#[25=BW32\r\n] 2006.173.12:09:45.58#ibcon#*before write, iclass 10, count 0 2006.173.12:09:45.58#ibcon#enter sib2, iclass 10, count 0 2006.173.12:09:45.58#ibcon#flushed, iclass 10, count 0 2006.173.12:09:45.58#ibcon#about to write, iclass 10, count 0 2006.173.12:09:45.58#ibcon#wrote, iclass 10, count 0 2006.173.12:09:45.58#ibcon#about to read 3, iclass 10, count 0 2006.173.12:09:45.61#ibcon#read 3, iclass 10, count 0 2006.173.12:09:45.61#ibcon#about to read 4, iclass 10, count 0 2006.173.12:09:45.61#ibcon#read 4, iclass 10, count 0 2006.173.12:09:45.61#ibcon#about to read 5, iclass 10, count 0 2006.173.12:09:45.61#ibcon#read 5, iclass 10, count 0 2006.173.12:09:45.61#ibcon#about to read 6, iclass 10, count 0 2006.173.12:09:45.61#ibcon#read 6, iclass 10, count 0 2006.173.12:09:45.61#ibcon#end of sib2, iclass 10, count 0 2006.173.12:09:45.61#ibcon#*after write, iclass 10, count 0 2006.173.12:09:45.61#ibcon#*before return 0, iclass 10, count 0 2006.173.12:09:45.61#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.12:09:45.61#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.12:09:45.61#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.12:09:45.61#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.12:09:45.61$vck44/vbbw=wide 2006.173.12:09:45.61#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.12:09:45.61#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.12:09:45.61#ibcon#ireg 8 cls_cnt 0 2006.173.12:09:45.61#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.12:09:45.68#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.12:09:45.68#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.12:09:45.68#ibcon#enter wrdev, iclass 12, count 0 2006.173.12:09:45.68#ibcon#first serial, iclass 12, count 0 2006.173.12:09:45.68#ibcon#enter sib2, iclass 12, count 0 2006.173.12:09:45.68#ibcon#flushed, iclass 12, count 0 2006.173.12:09:45.68#ibcon#about to write, iclass 12, count 0 2006.173.12:09:45.68#ibcon#wrote, iclass 12, count 0 2006.173.12:09:45.68#ibcon#about to read 3, iclass 12, count 0 2006.173.12:09:45.70#ibcon#read 3, iclass 12, count 0 2006.173.12:09:45.70#ibcon#about to read 4, iclass 12, count 0 2006.173.12:09:45.70#ibcon#read 4, iclass 12, count 0 2006.173.12:09:45.70#ibcon#about to read 5, iclass 12, count 0 2006.173.12:09:45.70#ibcon#read 5, iclass 12, count 0 2006.173.12:09:45.70#ibcon#about to read 6, iclass 12, count 0 2006.173.12:09:45.70#ibcon#read 6, iclass 12, count 0 2006.173.12:09:45.70#ibcon#end of sib2, iclass 12, count 0 2006.173.12:09:45.70#ibcon#*mode == 0, iclass 12, count 0 2006.173.12:09:45.70#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.12:09:45.70#ibcon#[27=BW32\r\n] 2006.173.12:09:45.70#ibcon#*before write, iclass 12, count 0 2006.173.12:09:45.70#ibcon#enter sib2, iclass 12, count 0 2006.173.12:09:45.70#ibcon#flushed, iclass 12, count 0 2006.173.12:09:45.70#ibcon#about to write, iclass 12, count 0 2006.173.12:09:45.70#ibcon#wrote, iclass 12, count 0 2006.173.12:09:45.70#ibcon#about to read 3, iclass 12, count 0 2006.173.12:09:45.73#ibcon#read 3, iclass 12, count 0 2006.173.12:09:45.73#ibcon#about to read 4, iclass 12, count 0 2006.173.12:09:45.73#ibcon#read 4, iclass 12, count 0 2006.173.12:09:45.73#ibcon#about to read 5, iclass 12, count 0 2006.173.12:09:45.73#ibcon#read 5, iclass 12, count 0 2006.173.12:09:45.73#ibcon#about to read 6, iclass 12, count 0 2006.173.12:09:45.73#ibcon#read 6, iclass 12, count 0 2006.173.12:09:45.73#ibcon#end of sib2, iclass 12, count 0 2006.173.12:09:45.73#ibcon#*after write, iclass 12, count 0 2006.173.12:09:45.73#ibcon#*before return 0, iclass 12, count 0 2006.173.12:09:45.73#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.12:09:45.73#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.12:09:45.73#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.12:09:45.73#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.12:09:45.73$setupk4/ifdk4 2006.173.12:09:45.73$ifdk4/lo= 2006.173.12:09:45.73$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.12:09:45.73$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.12:09:45.73$ifdk4/patch= 2006.173.12:09:45.73$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.12:09:45.73$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.12:09:45.73$setupk4/!*+20s 2006.173.12:09:48.83#abcon#<5=/06 1.6 2.5 22.20 951004.3\r\n> 2006.173.12:09:48.85#abcon#{5=INTERFACE CLEAR} 2006.173.12:09:48.91#abcon#[5=S1D000X0/0*\r\n] 2006.173.12:09:59.00#abcon#<5=/06 1.7 2.6 22.20 951004.3\r\n> 2006.173.12:09:59.02#abcon#{5=INTERFACE CLEAR} 2006.173.12:09:59.08#abcon#[5=S1D000X0/0*\r\n] 2006.173.12:10:00.23$setupk4/"tpicd 2006.173.12:10:00.23$setupk4/echo=off 2006.173.12:10:00.23$setupk4/xlog=off 2006.173.12:10:00.23:!2006.173.12:10:20 2006.173.12:10:17.14#trakl#Source acquired 2006.173.12:10:18.14#flagr#flagr/antenna,acquired 2006.173.12:10:20.00:preob 2006.173.12:10:20.14/onsource/TRACKING 2006.173.12:10:20.14:!2006.173.12:10:30 2006.173.12:10:30.00:"tape 2006.173.12:10:30.00:"st=record 2006.173.12:10:30.00:data_valid=on 2006.173.12:10:30.00:midob 2006.173.12:10:30.14/onsource/TRACKING 2006.173.12:10:30.14/wx/22.20,1004.3,95 2006.173.12:10:30.29/cable/+6.5044E-03 2006.173.12:10:31.38/va/01,07,usb,yes,39,42 2006.173.12:10:31.38/va/02,06,usb,yes,39,40 2006.173.12:10:31.38/va/03,05,usb,yes,50,52 2006.173.12:10:31.38/va/04,06,usb,yes,40,42 2006.173.12:10:31.38/va/05,04,usb,yes,31,32 2006.173.12:10:31.38/va/06,03,usb,yes,44,44 2006.173.12:10:31.38/va/07,04,usb,yes,36,37 2006.173.12:10:31.38/va/08,04,usb,yes,30,36 2006.173.12:10:31.61/valo/01,524.99,yes,locked 2006.173.12:10:31.61/valo/02,534.99,yes,locked 2006.173.12:10:31.61/valo/03,564.99,yes,locked 2006.173.12:10:31.61/valo/04,624.99,yes,locked 2006.173.12:10:31.61/valo/05,734.99,yes,locked 2006.173.12:10:31.61/valo/06,814.99,yes,locked 2006.173.12:10:31.61/valo/07,864.99,yes,locked 2006.173.12:10:31.61/valo/08,884.99,yes,locked 2006.173.12:10:32.70/vb/01,04,usb,yes,30,30 2006.173.12:10:32.70/vb/02,04,usb,yes,32,37 2006.173.12:10:32.70/vb/03,04,usb,yes,29,32 2006.173.12:10:32.70/vb/04,04,usb,yes,33,32 2006.173.12:10:32.70/vb/05,04,usb,yes,26,28 2006.173.12:10:32.70/vb/06,04,usb,yes,30,27 2006.173.12:10:32.70/vb/07,04,usb,yes,30,30 2006.173.12:10:32.70/vb/08,04,usb,yes,28,31 2006.173.12:10:32.93/vblo/01,629.99,yes,locked 2006.173.12:10:32.93/vblo/02,634.99,yes,locked 2006.173.12:10:32.93/vblo/03,649.99,yes,locked 2006.173.12:10:32.93/vblo/04,679.99,yes,locked 2006.173.12:10:32.93/vblo/05,709.99,yes,locked 2006.173.12:10:32.93/vblo/06,719.99,yes,locked 2006.173.12:10:32.93/vblo/07,734.99,yes,locked 2006.173.12:10:32.93/vblo/08,744.99,yes,locked 2006.173.12:10:33.08/vabw/8 2006.173.12:10:33.23/vbbw/8 2006.173.12:10:33.32/xfe/off,on,15.2 2006.173.12:10:33.72/ifatt/23,28,28,28 2006.173.12:10:34.08/fmout-gps/S +3.98E-07 2006.173.12:10:34.12:!2006.173.12:11:10 2006.173.12:11:10.00:data_valid=off 2006.173.12:11:10.00:"et 2006.173.12:11:10.00:!+3s 2006.173.12:11:13.01:"tape 2006.173.12:11:13.01:postob 2006.173.12:11:13.13/cable/+6.5046E-03 2006.173.12:11:13.13/wx/22.20,1004.3,95 2006.173.12:11:14.08/fmout-gps/S +3.97E-07 2006.173.12:11:14.08:scan_name=173-1217,jd0606,100 2006.173.12:11:14.08:source=1334-127,133739.78,-125724.7,2000.0,cw 2006.173.12:11:15.14#flagr#flagr/antenna,new-source 2006.173.12:11:15.14:checkk5 2006.173.12:11:15.55/chk_autoobs//k5ts1/ autoobs is running! 2006.173.12:11:15.93/chk_autoobs//k5ts2/ autoobs is running! 2006.173.12:11:16.33/chk_autoobs//k5ts3/ autoobs is running! 2006.173.12:11:16.74/chk_autoobs//k5ts4/ autoobs is running! 2006.173.12:11:17.14/chk_obsdata//k5ts1/T1731210??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.12:11:17.56/chk_obsdata//k5ts2/T1731210??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.12:11:17.96/chk_obsdata//k5ts3/T1731210??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.12:11:18.38/chk_obsdata//k5ts4/T1731210??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.12:11:19.10/k5log//k5ts1_log_newline 2006.173.12:11:19.82/k5log//k5ts2_log_newline 2006.173.12:11:20.52/k5log//k5ts3_log_newline 2006.173.12:11:21.22/k5log//k5ts4_log_newline 2006.173.12:11:21.25/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.12:11:21.25:setupk4=1 2006.173.12:11:21.25$setupk4/echo=on 2006.173.12:11:21.25$setupk4/pcalon 2006.173.12:11:21.25$pcalon/"no phase cal control is implemented here 2006.173.12:11:21.25$setupk4/"tpicd=stop 2006.173.12:11:21.25$setupk4/"rec=synch_on 2006.173.12:11:21.25$setupk4/"rec_mode=128 2006.173.12:11:21.25$setupk4/!* 2006.173.12:11:21.25$setupk4/recpk4 2006.173.12:11:21.25$recpk4/recpatch= 2006.173.12:11:21.25$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.12:11:21.25$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.12:11:21.25$setupk4/vck44 2006.173.12:11:21.25$vck44/valo=1,524.99 2006.173.12:11:21.25#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.12:11:21.25#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.12:11:21.25#ibcon#ireg 17 cls_cnt 0 2006.173.12:11:21.25#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.12:11:21.25#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.12:11:21.25#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.12:11:21.25#ibcon#enter wrdev, iclass 21, count 0 2006.173.12:11:21.25#ibcon#first serial, iclass 21, count 0 2006.173.12:11:21.25#ibcon#enter sib2, iclass 21, count 0 2006.173.12:11:21.25#ibcon#flushed, iclass 21, count 0 2006.173.12:11:21.25#ibcon#about to write, iclass 21, count 0 2006.173.12:11:21.25#ibcon#wrote, iclass 21, count 0 2006.173.12:11:21.25#ibcon#about to read 3, iclass 21, count 0 2006.173.12:11:21.27#ibcon#read 3, iclass 21, count 0 2006.173.12:11:21.27#ibcon#about to read 4, iclass 21, count 0 2006.173.12:11:21.27#ibcon#read 4, iclass 21, count 0 2006.173.12:11:21.27#ibcon#about to read 5, iclass 21, count 0 2006.173.12:11:21.27#ibcon#read 5, iclass 21, count 0 2006.173.12:11:21.27#ibcon#about to read 6, iclass 21, count 0 2006.173.12:11:21.27#ibcon#read 6, iclass 21, count 0 2006.173.12:11:21.27#ibcon#end of sib2, iclass 21, count 0 2006.173.12:11:21.27#ibcon#*mode == 0, iclass 21, count 0 2006.173.12:11:21.27#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.12:11:21.27#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.12:11:21.27#ibcon#*before write, iclass 21, count 0 2006.173.12:11:21.27#ibcon#enter sib2, iclass 21, count 0 2006.173.12:11:21.27#ibcon#flushed, iclass 21, count 0 2006.173.12:11:21.27#ibcon#about to write, iclass 21, count 0 2006.173.12:11:21.27#ibcon#wrote, iclass 21, count 0 2006.173.12:11:21.27#ibcon#about to read 3, iclass 21, count 0 2006.173.12:11:21.32#ibcon#read 3, iclass 21, count 0 2006.173.12:11:21.32#ibcon#about to read 4, iclass 21, count 0 2006.173.12:11:21.32#ibcon#read 4, iclass 21, count 0 2006.173.12:11:21.32#ibcon#about to read 5, iclass 21, count 0 2006.173.12:11:21.32#ibcon#read 5, iclass 21, count 0 2006.173.12:11:21.32#ibcon#about to read 6, iclass 21, count 0 2006.173.12:11:21.32#ibcon#read 6, iclass 21, count 0 2006.173.12:11:21.32#ibcon#end of sib2, iclass 21, count 0 2006.173.12:11:21.32#ibcon#*after write, iclass 21, count 0 2006.173.12:11:21.32#ibcon#*before return 0, iclass 21, count 0 2006.173.12:11:21.32#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.12:11:21.32#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.12:11:21.32#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.12:11:21.32#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.12:11:21.32$vck44/va=1,7 2006.173.12:11:21.32#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.12:11:21.32#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.12:11:21.32#ibcon#ireg 11 cls_cnt 2 2006.173.12:11:21.32#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.12:11:21.32#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.12:11:21.32#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.12:11:21.32#ibcon#enter wrdev, iclass 23, count 2 2006.173.12:11:21.32#ibcon#first serial, iclass 23, count 2 2006.173.12:11:21.32#ibcon#enter sib2, iclass 23, count 2 2006.173.12:11:21.32#ibcon#flushed, iclass 23, count 2 2006.173.12:11:21.32#ibcon#about to write, iclass 23, count 2 2006.173.12:11:21.32#ibcon#wrote, iclass 23, count 2 2006.173.12:11:21.32#ibcon#about to read 3, iclass 23, count 2 2006.173.12:11:21.34#ibcon#read 3, iclass 23, count 2 2006.173.12:11:21.34#ibcon#about to read 4, iclass 23, count 2 2006.173.12:11:21.34#ibcon#read 4, iclass 23, count 2 2006.173.12:11:21.34#ibcon#about to read 5, iclass 23, count 2 2006.173.12:11:21.34#ibcon#read 5, iclass 23, count 2 2006.173.12:11:21.34#ibcon#about to read 6, iclass 23, count 2 2006.173.12:11:21.34#ibcon#read 6, iclass 23, count 2 2006.173.12:11:21.34#ibcon#end of sib2, iclass 23, count 2 2006.173.12:11:21.34#ibcon#*mode == 0, iclass 23, count 2 2006.173.12:11:21.34#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.12:11:21.34#ibcon#[25=AT01-07\r\n] 2006.173.12:11:21.34#ibcon#*before write, iclass 23, count 2 2006.173.12:11:21.34#ibcon#enter sib2, iclass 23, count 2 2006.173.12:11:21.34#ibcon#flushed, iclass 23, count 2 2006.173.12:11:21.34#ibcon#about to write, iclass 23, count 2 2006.173.12:11:21.34#ibcon#wrote, iclass 23, count 2 2006.173.12:11:21.34#ibcon#about to read 3, iclass 23, count 2 2006.173.12:11:21.37#ibcon#read 3, iclass 23, count 2 2006.173.12:11:21.37#ibcon#about to read 4, iclass 23, count 2 2006.173.12:11:21.37#ibcon#read 4, iclass 23, count 2 2006.173.12:11:21.37#ibcon#about to read 5, iclass 23, count 2 2006.173.12:11:21.37#ibcon#read 5, iclass 23, count 2 2006.173.12:11:21.37#ibcon#about to read 6, iclass 23, count 2 2006.173.12:11:21.37#ibcon#read 6, iclass 23, count 2 2006.173.12:11:21.37#ibcon#end of sib2, iclass 23, count 2 2006.173.12:11:21.37#ibcon#*after write, iclass 23, count 2 2006.173.12:11:21.37#ibcon#*before return 0, iclass 23, count 2 2006.173.12:11:21.37#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.12:11:21.37#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.12:11:21.37#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.12:11:21.37#ibcon#ireg 7 cls_cnt 0 2006.173.12:11:21.37#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.12:11:21.49#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.12:11:21.49#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.12:11:21.49#ibcon#enter wrdev, iclass 23, count 0 2006.173.12:11:21.49#ibcon#first serial, iclass 23, count 0 2006.173.12:11:21.49#ibcon#enter sib2, iclass 23, count 0 2006.173.12:11:21.49#ibcon#flushed, iclass 23, count 0 2006.173.12:11:21.49#ibcon#about to write, iclass 23, count 0 2006.173.12:11:21.49#ibcon#wrote, iclass 23, count 0 2006.173.12:11:21.49#ibcon#about to read 3, iclass 23, count 0 2006.173.12:11:21.51#ibcon#read 3, iclass 23, count 0 2006.173.12:11:21.51#ibcon#about to read 4, iclass 23, count 0 2006.173.12:11:21.51#ibcon#read 4, iclass 23, count 0 2006.173.12:11:21.51#ibcon#about to read 5, iclass 23, count 0 2006.173.12:11:21.51#ibcon#read 5, iclass 23, count 0 2006.173.12:11:21.51#ibcon#about to read 6, iclass 23, count 0 2006.173.12:11:21.51#ibcon#read 6, iclass 23, count 0 2006.173.12:11:21.51#ibcon#end of sib2, iclass 23, count 0 2006.173.12:11:21.51#ibcon#*mode == 0, iclass 23, count 0 2006.173.12:11:21.51#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.12:11:21.51#ibcon#[25=USB\r\n] 2006.173.12:11:21.51#ibcon#*before write, iclass 23, count 0 2006.173.12:11:21.51#ibcon#enter sib2, iclass 23, count 0 2006.173.12:11:21.51#ibcon#flushed, iclass 23, count 0 2006.173.12:11:21.51#ibcon#about to write, iclass 23, count 0 2006.173.12:11:21.51#ibcon#wrote, iclass 23, count 0 2006.173.12:11:21.51#ibcon#about to read 3, iclass 23, count 0 2006.173.12:11:21.54#ibcon#read 3, iclass 23, count 0 2006.173.12:11:21.54#ibcon#about to read 4, iclass 23, count 0 2006.173.12:11:21.54#ibcon#read 4, iclass 23, count 0 2006.173.12:11:21.54#ibcon#about to read 5, iclass 23, count 0 2006.173.12:11:21.54#ibcon#read 5, iclass 23, count 0 2006.173.12:11:21.54#ibcon#about to read 6, iclass 23, count 0 2006.173.12:11:21.54#ibcon#read 6, iclass 23, count 0 2006.173.12:11:21.54#ibcon#end of sib2, iclass 23, count 0 2006.173.12:11:21.54#ibcon#*after write, iclass 23, count 0 2006.173.12:11:21.54#ibcon#*before return 0, iclass 23, count 0 2006.173.12:11:21.54#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.12:11:21.54#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.12:11:21.54#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.12:11:21.54#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.12:11:21.54$vck44/valo=2,534.99 2006.173.12:11:21.54#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.12:11:21.54#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.12:11:21.54#ibcon#ireg 17 cls_cnt 0 2006.173.12:11:21.54#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.12:11:21.54#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.12:11:21.54#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.12:11:21.54#ibcon#enter wrdev, iclass 25, count 0 2006.173.12:11:21.54#ibcon#first serial, iclass 25, count 0 2006.173.12:11:21.54#ibcon#enter sib2, iclass 25, count 0 2006.173.12:11:21.54#ibcon#flushed, iclass 25, count 0 2006.173.12:11:21.54#ibcon#about to write, iclass 25, count 0 2006.173.12:11:21.54#ibcon#wrote, iclass 25, count 0 2006.173.12:11:21.54#ibcon#about to read 3, iclass 25, count 0 2006.173.12:11:21.56#ibcon#read 3, iclass 25, count 0 2006.173.12:11:21.56#ibcon#about to read 4, iclass 25, count 0 2006.173.12:11:21.56#ibcon#read 4, iclass 25, count 0 2006.173.12:11:21.56#ibcon#about to read 5, iclass 25, count 0 2006.173.12:11:21.56#ibcon#read 5, iclass 25, count 0 2006.173.12:11:21.56#ibcon#about to read 6, iclass 25, count 0 2006.173.12:11:21.56#ibcon#read 6, iclass 25, count 0 2006.173.12:11:21.56#ibcon#end of sib2, iclass 25, count 0 2006.173.12:11:21.56#ibcon#*mode == 0, iclass 25, count 0 2006.173.12:11:21.56#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.12:11:21.56#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.12:11:21.56#ibcon#*before write, iclass 25, count 0 2006.173.12:11:21.56#ibcon#enter sib2, iclass 25, count 0 2006.173.12:11:21.56#ibcon#flushed, iclass 25, count 0 2006.173.12:11:21.56#ibcon#about to write, iclass 25, count 0 2006.173.12:11:21.56#ibcon#wrote, iclass 25, count 0 2006.173.12:11:21.56#ibcon#about to read 3, iclass 25, count 0 2006.173.12:11:21.60#ibcon#read 3, iclass 25, count 0 2006.173.12:11:21.60#ibcon#about to read 4, iclass 25, count 0 2006.173.12:11:21.60#ibcon#read 4, iclass 25, count 0 2006.173.12:11:21.60#ibcon#about to read 5, iclass 25, count 0 2006.173.12:11:21.60#ibcon#read 5, iclass 25, count 0 2006.173.12:11:21.60#ibcon#about to read 6, iclass 25, count 0 2006.173.12:11:21.60#ibcon#read 6, iclass 25, count 0 2006.173.12:11:21.60#ibcon#end of sib2, iclass 25, count 0 2006.173.12:11:21.60#ibcon#*after write, iclass 25, count 0 2006.173.12:11:21.60#ibcon#*before return 0, iclass 25, count 0 2006.173.12:11:21.60#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.12:11:21.60#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.12:11:21.60#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.12:11:21.60#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.12:11:21.60$vck44/va=2,6 2006.173.12:11:21.60#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.12:11:21.60#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.12:11:21.60#ibcon#ireg 11 cls_cnt 2 2006.173.12:11:21.60#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.12:11:21.66#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.12:11:21.66#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.12:11:21.66#ibcon#enter wrdev, iclass 27, count 2 2006.173.12:11:21.66#ibcon#first serial, iclass 27, count 2 2006.173.12:11:21.66#ibcon#enter sib2, iclass 27, count 2 2006.173.12:11:21.66#ibcon#flushed, iclass 27, count 2 2006.173.12:11:21.66#ibcon#about to write, iclass 27, count 2 2006.173.12:11:21.66#ibcon#wrote, iclass 27, count 2 2006.173.12:11:21.66#ibcon#about to read 3, iclass 27, count 2 2006.173.12:11:21.68#ibcon#read 3, iclass 27, count 2 2006.173.12:11:21.68#ibcon#about to read 4, iclass 27, count 2 2006.173.12:11:21.68#ibcon#read 4, iclass 27, count 2 2006.173.12:11:21.68#ibcon#about to read 5, iclass 27, count 2 2006.173.12:11:21.68#ibcon#read 5, iclass 27, count 2 2006.173.12:11:21.68#ibcon#about to read 6, iclass 27, count 2 2006.173.12:11:21.68#ibcon#read 6, iclass 27, count 2 2006.173.12:11:21.68#ibcon#end of sib2, iclass 27, count 2 2006.173.12:11:21.68#ibcon#*mode == 0, iclass 27, count 2 2006.173.12:11:21.68#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.12:11:21.68#ibcon#[25=AT02-06\r\n] 2006.173.12:11:21.68#ibcon#*before write, iclass 27, count 2 2006.173.12:11:21.68#ibcon#enter sib2, iclass 27, count 2 2006.173.12:11:21.68#ibcon#flushed, iclass 27, count 2 2006.173.12:11:21.68#ibcon#about to write, iclass 27, count 2 2006.173.12:11:21.68#ibcon#wrote, iclass 27, count 2 2006.173.12:11:21.68#ibcon#about to read 3, iclass 27, count 2 2006.173.12:11:21.71#ibcon#read 3, iclass 27, count 2 2006.173.12:11:21.71#ibcon#about to read 4, iclass 27, count 2 2006.173.12:11:21.71#ibcon#read 4, iclass 27, count 2 2006.173.12:11:21.71#ibcon#about to read 5, iclass 27, count 2 2006.173.12:11:21.71#ibcon#read 5, iclass 27, count 2 2006.173.12:11:21.71#ibcon#about to read 6, iclass 27, count 2 2006.173.12:11:21.71#ibcon#read 6, iclass 27, count 2 2006.173.12:11:21.71#ibcon#end of sib2, iclass 27, count 2 2006.173.12:11:21.71#ibcon#*after write, iclass 27, count 2 2006.173.12:11:21.71#ibcon#*before return 0, iclass 27, count 2 2006.173.12:11:21.71#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.12:11:21.71#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.12:11:21.71#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.12:11:21.71#ibcon#ireg 7 cls_cnt 0 2006.173.12:11:21.71#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.12:11:21.83#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.12:11:21.83#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.12:11:21.83#ibcon#enter wrdev, iclass 27, count 0 2006.173.12:11:21.83#ibcon#first serial, iclass 27, count 0 2006.173.12:11:21.83#ibcon#enter sib2, iclass 27, count 0 2006.173.12:11:21.83#ibcon#flushed, iclass 27, count 0 2006.173.12:11:21.83#ibcon#about to write, iclass 27, count 0 2006.173.12:11:21.83#ibcon#wrote, iclass 27, count 0 2006.173.12:11:21.83#ibcon#about to read 3, iclass 27, count 0 2006.173.12:11:21.85#ibcon#read 3, iclass 27, count 0 2006.173.12:11:21.85#ibcon#about to read 4, iclass 27, count 0 2006.173.12:11:21.85#ibcon#read 4, iclass 27, count 0 2006.173.12:11:21.85#ibcon#about to read 5, iclass 27, count 0 2006.173.12:11:21.85#ibcon#read 5, iclass 27, count 0 2006.173.12:11:21.85#ibcon#about to read 6, iclass 27, count 0 2006.173.12:11:21.85#ibcon#read 6, iclass 27, count 0 2006.173.12:11:21.85#ibcon#end of sib2, iclass 27, count 0 2006.173.12:11:21.85#ibcon#*mode == 0, iclass 27, count 0 2006.173.12:11:21.85#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.12:11:21.85#ibcon#[25=USB\r\n] 2006.173.12:11:21.85#ibcon#*before write, iclass 27, count 0 2006.173.12:11:21.85#ibcon#enter sib2, iclass 27, count 0 2006.173.12:11:21.85#ibcon#flushed, iclass 27, count 0 2006.173.12:11:21.85#ibcon#about to write, iclass 27, count 0 2006.173.12:11:21.85#ibcon#wrote, iclass 27, count 0 2006.173.12:11:21.85#ibcon#about to read 3, iclass 27, count 0 2006.173.12:11:21.88#ibcon#read 3, iclass 27, count 0 2006.173.12:11:21.88#ibcon#about to read 4, iclass 27, count 0 2006.173.12:11:21.88#ibcon#read 4, iclass 27, count 0 2006.173.12:11:21.88#ibcon#about to read 5, iclass 27, count 0 2006.173.12:11:21.88#ibcon#read 5, iclass 27, count 0 2006.173.12:11:21.88#ibcon#about to read 6, iclass 27, count 0 2006.173.12:11:21.88#ibcon#read 6, iclass 27, count 0 2006.173.12:11:21.88#ibcon#end of sib2, iclass 27, count 0 2006.173.12:11:21.88#ibcon#*after write, iclass 27, count 0 2006.173.12:11:21.88#ibcon#*before return 0, iclass 27, count 0 2006.173.12:11:21.88#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.12:11:21.88#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.12:11:21.88#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.12:11:21.88#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.12:11:21.88$vck44/valo=3,564.99 2006.173.12:11:21.88#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.12:11:21.88#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.12:11:21.88#ibcon#ireg 17 cls_cnt 0 2006.173.12:11:21.88#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.12:11:21.88#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.12:11:21.88#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.12:11:21.88#ibcon#enter wrdev, iclass 29, count 0 2006.173.12:11:21.88#ibcon#first serial, iclass 29, count 0 2006.173.12:11:21.88#ibcon#enter sib2, iclass 29, count 0 2006.173.12:11:21.88#ibcon#flushed, iclass 29, count 0 2006.173.12:11:21.88#ibcon#about to write, iclass 29, count 0 2006.173.12:11:21.88#ibcon#wrote, iclass 29, count 0 2006.173.12:11:21.88#ibcon#about to read 3, iclass 29, count 0 2006.173.12:11:21.90#ibcon#read 3, iclass 29, count 0 2006.173.12:11:21.90#ibcon#about to read 4, iclass 29, count 0 2006.173.12:11:21.90#ibcon#read 4, iclass 29, count 0 2006.173.12:11:21.90#ibcon#about to read 5, iclass 29, count 0 2006.173.12:11:21.90#ibcon#read 5, iclass 29, count 0 2006.173.12:11:21.90#ibcon#about to read 6, iclass 29, count 0 2006.173.12:11:21.90#ibcon#read 6, iclass 29, count 0 2006.173.12:11:21.90#ibcon#end of sib2, iclass 29, count 0 2006.173.12:11:21.90#ibcon#*mode == 0, iclass 29, count 0 2006.173.12:11:21.90#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.12:11:21.90#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.12:11:21.90#ibcon#*before write, iclass 29, count 0 2006.173.12:11:21.90#ibcon#enter sib2, iclass 29, count 0 2006.173.12:11:21.90#ibcon#flushed, iclass 29, count 0 2006.173.12:11:21.90#ibcon#about to write, iclass 29, count 0 2006.173.12:11:21.90#ibcon#wrote, iclass 29, count 0 2006.173.12:11:21.90#ibcon#about to read 3, iclass 29, count 0 2006.173.12:11:21.94#ibcon#read 3, iclass 29, count 0 2006.173.12:11:21.94#ibcon#about to read 4, iclass 29, count 0 2006.173.12:11:21.94#ibcon#read 4, iclass 29, count 0 2006.173.12:11:21.94#ibcon#about to read 5, iclass 29, count 0 2006.173.12:11:21.94#ibcon#read 5, iclass 29, count 0 2006.173.12:11:21.94#ibcon#about to read 6, iclass 29, count 0 2006.173.12:11:21.94#ibcon#read 6, iclass 29, count 0 2006.173.12:11:21.94#ibcon#end of sib2, iclass 29, count 0 2006.173.12:11:21.94#ibcon#*after write, iclass 29, count 0 2006.173.12:11:21.94#ibcon#*before return 0, iclass 29, count 0 2006.173.12:11:21.94#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.12:11:21.94#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.12:11:21.94#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.12:11:21.94#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.12:11:21.94$vck44/va=3,5 2006.173.12:11:21.94#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.12:11:21.94#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.12:11:21.94#ibcon#ireg 11 cls_cnt 2 2006.173.12:11:21.94#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.12:11:22.00#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.12:11:22.00#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.12:11:22.00#ibcon#enter wrdev, iclass 31, count 2 2006.173.12:11:22.00#ibcon#first serial, iclass 31, count 2 2006.173.12:11:22.00#ibcon#enter sib2, iclass 31, count 2 2006.173.12:11:22.00#ibcon#flushed, iclass 31, count 2 2006.173.12:11:22.00#ibcon#about to write, iclass 31, count 2 2006.173.12:11:22.00#ibcon#wrote, iclass 31, count 2 2006.173.12:11:22.00#ibcon#about to read 3, iclass 31, count 2 2006.173.12:11:22.02#ibcon#read 3, iclass 31, count 2 2006.173.12:11:22.02#ibcon#about to read 4, iclass 31, count 2 2006.173.12:11:22.02#ibcon#read 4, iclass 31, count 2 2006.173.12:11:22.02#ibcon#about to read 5, iclass 31, count 2 2006.173.12:11:22.02#ibcon#read 5, iclass 31, count 2 2006.173.12:11:22.02#ibcon#about to read 6, iclass 31, count 2 2006.173.12:11:22.02#ibcon#read 6, iclass 31, count 2 2006.173.12:11:22.02#ibcon#end of sib2, iclass 31, count 2 2006.173.12:11:22.02#ibcon#*mode == 0, iclass 31, count 2 2006.173.12:11:22.02#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.12:11:22.02#ibcon#[25=AT03-05\r\n] 2006.173.12:11:22.02#ibcon#*before write, iclass 31, count 2 2006.173.12:11:22.02#ibcon#enter sib2, iclass 31, count 2 2006.173.12:11:22.02#ibcon#flushed, iclass 31, count 2 2006.173.12:11:22.02#ibcon#about to write, iclass 31, count 2 2006.173.12:11:22.02#ibcon#wrote, iclass 31, count 2 2006.173.12:11:22.02#ibcon#about to read 3, iclass 31, count 2 2006.173.12:11:22.05#ibcon#read 3, iclass 31, count 2 2006.173.12:11:22.05#ibcon#about to read 4, iclass 31, count 2 2006.173.12:11:22.05#ibcon#read 4, iclass 31, count 2 2006.173.12:11:22.05#ibcon#about to read 5, iclass 31, count 2 2006.173.12:11:22.05#ibcon#read 5, iclass 31, count 2 2006.173.12:11:22.05#ibcon#about to read 6, iclass 31, count 2 2006.173.12:11:22.05#ibcon#read 6, iclass 31, count 2 2006.173.12:11:22.05#ibcon#end of sib2, iclass 31, count 2 2006.173.12:11:22.05#ibcon#*after write, iclass 31, count 2 2006.173.12:11:22.05#ibcon#*before return 0, iclass 31, count 2 2006.173.12:11:22.05#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.12:11:22.05#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.12:11:22.05#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.12:11:22.05#ibcon#ireg 7 cls_cnt 0 2006.173.12:11:22.05#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.12:11:22.17#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.12:11:22.17#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.12:11:22.17#ibcon#enter wrdev, iclass 31, count 0 2006.173.12:11:22.17#ibcon#first serial, iclass 31, count 0 2006.173.12:11:22.17#ibcon#enter sib2, iclass 31, count 0 2006.173.12:11:22.17#ibcon#flushed, iclass 31, count 0 2006.173.12:11:22.17#ibcon#about to write, iclass 31, count 0 2006.173.12:11:22.17#ibcon#wrote, iclass 31, count 0 2006.173.12:11:22.17#ibcon#about to read 3, iclass 31, count 0 2006.173.12:11:22.19#ibcon#read 3, iclass 31, count 0 2006.173.12:11:22.19#ibcon#about to read 4, iclass 31, count 0 2006.173.12:11:22.19#ibcon#read 4, iclass 31, count 0 2006.173.12:11:22.19#ibcon#about to read 5, iclass 31, count 0 2006.173.12:11:22.19#ibcon#read 5, iclass 31, count 0 2006.173.12:11:22.19#ibcon#about to read 6, iclass 31, count 0 2006.173.12:11:22.19#ibcon#read 6, iclass 31, count 0 2006.173.12:11:22.19#ibcon#end of sib2, iclass 31, count 0 2006.173.12:11:22.19#ibcon#*mode == 0, iclass 31, count 0 2006.173.12:11:22.19#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.12:11:22.19#ibcon#[25=USB\r\n] 2006.173.12:11:22.19#ibcon#*before write, iclass 31, count 0 2006.173.12:11:22.19#ibcon#enter sib2, iclass 31, count 0 2006.173.12:11:22.19#ibcon#flushed, iclass 31, count 0 2006.173.12:11:22.19#ibcon#about to write, iclass 31, count 0 2006.173.12:11:22.19#ibcon#wrote, iclass 31, count 0 2006.173.12:11:22.19#ibcon#about to read 3, iclass 31, count 0 2006.173.12:11:22.22#ibcon#read 3, iclass 31, count 0 2006.173.12:11:22.22#ibcon#about to read 4, iclass 31, count 0 2006.173.12:11:22.22#ibcon#read 4, iclass 31, count 0 2006.173.12:11:22.22#ibcon#about to read 5, iclass 31, count 0 2006.173.12:11:22.22#ibcon#read 5, iclass 31, count 0 2006.173.12:11:22.22#ibcon#about to read 6, iclass 31, count 0 2006.173.12:11:22.22#ibcon#read 6, iclass 31, count 0 2006.173.12:11:22.22#ibcon#end of sib2, iclass 31, count 0 2006.173.12:11:22.22#ibcon#*after write, iclass 31, count 0 2006.173.12:11:22.22#ibcon#*before return 0, iclass 31, count 0 2006.173.12:11:22.22#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.12:11:22.22#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.12:11:22.22#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.12:11:22.22#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.12:11:22.22$vck44/valo=4,624.99 2006.173.12:11:22.22#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.12:11:22.22#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.12:11:22.22#ibcon#ireg 17 cls_cnt 0 2006.173.12:11:22.22#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.12:11:22.22#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.12:11:22.22#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.12:11:22.22#ibcon#enter wrdev, iclass 33, count 0 2006.173.12:11:22.22#ibcon#first serial, iclass 33, count 0 2006.173.12:11:22.22#ibcon#enter sib2, iclass 33, count 0 2006.173.12:11:22.22#ibcon#flushed, iclass 33, count 0 2006.173.12:11:22.22#ibcon#about to write, iclass 33, count 0 2006.173.12:11:22.22#ibcon#wrote, iclass 33, count 0 2006.173.12:11:22.22#ibcon#about to read 3, iclass 33, count 0 2006.173.12:11:22.24#ibcon#read 3, iclass 33, count 0 2006.173.12:11:22.24#ibcon#about to read 4, iclass 33, count 0 2006.173.12:11:22.24#ibcon#read 4, iclass 33, count 0 2006.173.12:11:22.24#ibcon#about to read 5, iclass 33, count 0 2006.173.12:11:22.24#ibcon#read 5, iclass 33, count 0 2006.173.12:11:22.24#ibcon#about to read 6, iclass 33, count 0 2006.173.12:11:22.24#ibcon#read 6, iclass 33, count 0 2006.173.12:11:22.24#ibcon#end of sib2, iclass 33, count 0 2006.173.12:11:22.24#ibcon#*mode == 0, iclass 33, count 0 2006.173.12:11:22.24#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.12:11:22.24#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.12:11:22.24#ibcon#*before write, iclass 33, count 0 2006.173.12:11:22.24#ibcon#enter sib2, iclass 33, count 0 2006.173.12:11:22.24#ibcon#flushed, iclass 33, count 0 2006.173.12:11:22.24#ibcon#about to write, iclass 33, count 0 2006.173.12:11:22.24#ibcon#wrote, iclass 33, count 0 2006.173.12:11:22.24#ibcon#about to read 3, iclass 33, count 0 2006.173.12:11:22.28#ibcon#read 3, iclass 33, count 0 2006.173.12:11:22.28#ibcon#about to read 4, iclass 33, count 0 2006.173.12:11:22.28#ibcon#read 4, iclass 33, count 0 2006.173.12:11:22.28#ibcon#about to read 5, iclass 33, count 0 2006.173.12:11:22.28#ibcon#read 5, iclass 33, count 0 2006.173.12:11:22.28#ibcon#about to read 6, iclass 33, count 0 2006.173.12:11:22.28#ibcon#read 6, iclass 33, count 0 2006.173.12:11:22.28#ibcon#end of sib2, iclass 33, count 0 2006.173.12:11:22.28#ibcon#*after write, iclass 33, count 0 2006.173.12:11:22.28#ibcon#*before return 0, iclass 33, count 0 2006.173.12:11:22.28#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.12:11:22.28#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.12:11:22.28#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.12:11:22.28#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.12:11:22.28$vck44/va=4,6 2006.173.12:11:22.28#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.12:11:22.28#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.12:11:22.28#ibcon#ireg 11 cls_cnt 2 2006.173.12:11:22.28#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.12:11:22.34#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.12:11:22.34#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.12:11:22.34#ibcon#enter wrdev, iclass 35, count 2 2006.173.12:11:22.34#ibcon#first serial, iclass 35, count 2 2006.173.12:11:22.34#ibcon#enter sib2, iclass 35, count 2 2006.173.12:11:22.34#ibcon#flushed, iclass 35, count 2 2006.173.12:11:22.34#ibcon#about to write, iclass 35, count 2 2006.173.12:11:22.34#ibcon#wrote, iclass 35, count 2 2006.173.12:11:22.34#ibcon#about to read 3, iclass 35, count 2 2006.173.12:11:22.36#ibcon#read 3, iclass 35, count 2 2006.173.12:11:22.36#ibcon#about to read 4, iclass 35, count 2 2006.173.12:11:22.36#ibcon#read 4, iclass 35, count 2 2006.173.12:11:22.36#ibcon#about to read 5, iclass 35, count 2 2006.173.12:11:22.36#ibcon#read 5, iclass 35, count 2 2006.173.12:11:22.36#ibcon#about to read 6, iclass 35, count 2 2006.173.12:11:22.36#ibcon#read 6, iclass 35, count 2 2006.173.12:11:22.36#ibcon#end of sib2, iclass 35, count 2 2006.173.12:11:22.36#ibcon#*mode == 0, iclass 35, count 2 2006.173.12:11:22.36#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.12:11:22.36#ibcon#[25=AT04-06\r\n] 2006.173.12:11:22.36#ibcon#*before write, iclass 35, count 2 2006.173.12:11:22.36#ibcon#enter sib2, iclass 35, count 2 2006.173.12:11:22.36#ibcon#flushed, iclass 35, count 2 2006.173.12:11:22.36#ibcon#about to write, iclass 35, count 2 2006.173.12:11:22.36#ibcon#wrote, iclass 35, count 2 2006.173.12:11:22.36#ibcon#about to read 3, iclass 35, count 2 2006.173.12:11:22.39#ibcon#read 3, iclass 35, count 2 2006.173.12:11:22.39#ibcon#about to read 4, iclass 35, count 2 2006.173.12:11:22.39#ibcon#read 4, iclass 35, count 2 2006.173.12:11:22.39#ibcon#about to read 5, iclass 35, count 2 2006.173.12:11:22.39#ibcon#read 5, iclass 35, count 2 2006.173.12:11:22.39#ibcon#about to read 6, iclass 35, count 2 2006.173.12:11:22.39#ibcon#read 6, iclass 35, count 2 2006.173.12:11:22.39#ibcon#end of sib2, iclass 35, count 2 2006.173.12:11:22.39#ibcon#*after write, iclass 35, count 2 2006.173.12:11:22.39#ibcon#*before return 0, iclass 35, count 2 2006.173.12:11:22.39#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.12:11:22.39#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.12:11:22.39#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.12:11:22.39#ibcon#ireg 7 cls_cnt 0 2006.173.12:11:22.39#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.12:11:22.51#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.12:11:22.51#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.12:11:22.51#ibcon#enter wrdev, iclass 35, count 0 2006.173.12:11:22.51#ibcon#first serial, iclass 35, count 0 2006.173.12:11:22.51#ibcon#enter sib2, iclass 35, count 0 2006.173.12:11:22.51#ibcon#flushed, iclass 35, count 0 2006.173.12:11:22.51#ibcon#about to write, iclass 35, count 0 2006.173.12:11:22.51#ibcon#wrote, iclass 35, count 0 2006.173.12:11:22.51#ibcon#about to read 3, iclass 35, count 0 2006.173.12:11:22.53#ibcon#read 3, iclass 35, count 0 2006.173.12:11:22.53#ibcon#about to read 4, iclass 35, count 0 2006.173.12:11:22.53#ibcon#read 4, iclass 35, count 0 2006.173.12:11:22.53#ibcon#about to read 5, iclass 35, count 0 2006.173.12:11:22.53#ibcon#read 5, iclass 35, count 0 2006.173.12:11:22.53#ibcon#about to read 6, iclass 35, count 0 2006.173.12:11:22.53#ibcon#read 6, iclass 35, count 0 2006.173.12:11:22.53#ibcon#end of sib2, iclass 35, count 0 2006.173.12:11:22.53#ibcon#*mode == 0, iclass 35, count 0 2006.173.12:11:22.53#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.12:11:22.53#ibcon#[25=USB\r\n] 2006.173.12:11:22.53#ibcon#*before write, iclass 35, count 0 2006.173.12:11:22.53#ibcon#enter sib2, iclass 35, count 0 2006.173.12:11:22.53#ibcon#flushed, iclass 35, count 0 2006.173.12:11:22.53#ibcon#about to write, iclass 35, count 0 2006.173.12:11:22.53#ibcon#wrote, iclass 35, count 0 2006.173.12:11:22.53#ibcon#about to read 3, iclass 35, count 0 2006.173.12:11:22.56#ibcon#read 3, iclass 35, count 0 2006.173.12:11:22.56#ibcon#about to read 4, iclass 35, count 0 2006.173.12:11:22.56#ibcon#read 4, iclass 35, count 0 2006.173.12:11:22.56#ibcon#about to read 5, iclass 35, count 0 2006.173.12:11:22.56#ibcon#read 5, iclass 35, count 0 2006.173.12:11:22.56#ibcon#about to read 6, iclass 35, count 0 2006.173.12:11:22.56#ibcon#read 6, iclass 35, count 0 2006.173.12:11:22.56#ibcon#end of sib2, iclass 35, count 0 2006.173.12:11:22.56#ibcon#*after write, iclass 35, count 0 2006.173.12:11:22.56#ibcon#*before return 0, iclass 35, count 0 2006.173.12:11:22.56#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.12:11:22.56#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.12:11:22.56#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.12:11:22.56#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.12:11:22.56$vck44/valo=5,734.99 2006.173.12:11:22.56#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.12:11:22.56#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.12:11:22.56#ibcon#ireg 17 cls_cnt 0 2006.173.12:11:22.56#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.12:11:22.56#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.12:11:22.56#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.12:11:22.56#ibcon#enter wrdev, iclass 37, count 0 2006.173.12:11:22.56#ibcon#first serial, iclass 37, count 0 2006.173.12:11:22.56#ibcon#enter sib2, iclass 37, count 0 2006.173.12:11:22.56#ibcon#flushed, iclass 37, count 0 2006.173.12:11:22.56#ibcon#about to write, iclass 37, count 0 2006.173.12:11:22.56#ibcon#wrote, iclass 37, count 0 2006.173.12:11:22.56#ibcon#about to read 3, iclass 37, count 0 2006.173.12:11:22.58#ibcon#read 3, iclass 37, count 0 2006.173.12:11:22.58#ibcon#about to read 4, iclass 37, count 0 2006.173.12:11:22.58#ibcon#read 4, iclass 37, count 0 2006.173.12:11:22.58#ibcon#about to read 5, iclass 37, count 0 2006.173.12:11:22.58#ibcon#read 5, iclass 37, count 0 2006.173.12:11:22.58#ibcon#about to read 6, iclass 37, count 0 2006.173.12:11:22.58#ibcon#read 6, iclass 37, count 0 2006.173.12:11:22.58#ibcon#end of sib2, iclass 37, count 0 2006.173.12:11:22.58#ibcon#*mode == 0, iclass 37, count 0 2006.173.12:11:22.58#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.12:11:22.58#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.12:11:22.58#ibcon#*before write, iclass 37, count 0 2006.173.12:11:22.58#ibcon#enter sib2, iclass 37, count 0 2006.173.12:11:22.58#ibcon#flushed, iclass 37, count 0 2006.173.12:11:22.58#ibcon#about to write, iclass 37, count 0 2006.173.12:11:22.58#ibcon#wrote, iclass 37, count 0 2006.173.12:11:22.58#ibcon#about to read 3, iclass 37, count 0 2006.173.12:11:22.62#ibcon#read 3, iclass 37, count 0 2006.173.12:11:22.62#ibcon#about to read 4, iclass 37, count 0 2006.173.12:11:22.62#ibcon#read 4, iclass 37, count 0 2006.173.12:11:22.62#ibcon#about to read 5, iclass 37, count 0 2006.173.12:11:22.62#ibcon#read 5, iclass 37, count 0 2006.173.12:11:22.62#ibcon#about to read 6, iclass 37, count 0 2006.173.12:11:22.62#ibcon#read 6, iclass 37, count 0 2006.173.12:11:22.62#ibcon#end of sib2, iclass 37, count 0 2006.173.12:11:22.62#ibcon#*after write, iclass 37, count 0 2006.173.12:11:22.62#ibcon#*before return 0, iclass 37, count 0 2006.173.12:11:22.62#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.12:11:22.62#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.12:11:22.62#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.12:11:22.62#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.12:11:22.62$vck44/va=5,4 2006.173.12:11:22.62#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.12:11:22.62#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.12:11:22.62#ibcon#ireg 11 cls_cnt 2 2006.173.12:11:22.62#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.12:11:22.68#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.12:11:22.68#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.12:11:22.68#ibcon#enter wrdev, iclass 39, count 2 2006.173.12:11:22.68#ibcon#first serial, iclass 39, count 2 2006.173.12:11:22.68#ibcon#enter sib2, iclass 39, count 2 2006.173.12:11:22.68#ibcon#flushed, iclass 39, count 2 2006.173.12:11:22.68#ibcon#about to write, iclass 39, count 2 2006.173.12:11:22.68#ibcon#wrote, iclass 39, count 2 2006.173.12:11:22.68#ibcon#about to read 3, iclass 39, count 2 2006.173.12:11:22.70#ibcon#read 3, iclass 39, count 2 2006.173.12:11:22.70#ibcon#about to read 4, iclass 39, count 2 2006.173.12:11:22.70#ibcon#read 4, iclass 39, count 2 2006.173.12:11:22.70#ibcon#about to read 5, iclass 39, count 2 2006.173.12:11:22.70#ibcon#read 5, iclass 39, count 2 2006.173.12:11:22.70#ibcon#about to read 6, iclass 39, count 2 2006.173.12:11:22.70#ibcon#read 6, iclass 39, count 2 2006.173.12:11:22.70#ibcon#end of sib2, iclass 39, count 2 2006.173.12:11:22.70#ibcon#*mode == 0, iclass 39, count 2 2006.173.12:11:22.70#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.12:11:22.70#ibcon#[25=AT05-04\r\n] 2006.173.12:11:22.70#ibcon#*before write, iclass 39, count 2 2006.173.12:11:22.70#ibcon#enter sib2, iclass 39, count 2 2006.173.12:11:22.70#ibcon#flushed, iclass 39, count 2 2006.173.12:11:22.70#ibcon#about to write, iclass 39, count 2 2006.173.12:11:22.70#ibcon#wrote, iclass 39, count 2 2006.173.12:11:22.70#ibcon#about to read 3, iclass 39, count 2 2006.173.12:11:22.73#ibcon#read 3, iclass 39, count 2 2006.173.12:11:22.73#ibcon#about to read 4, iclass 39, count 2 2006.173.12:11:22.73#ibcon#read 4, iclass 39, count 2 2006.173.12:11:22.73#ibcon#about to read 5, iclass 39, count 2 2006.173.12:11:22.73#ibcon#read 5, iclass 39, count 2 2006.173.12:11:22.73#ibcon#about to read 6, iclass 39, count 2 2006.173.12:11:22.73#ibcon#read 6, iclass 39, count 2 2006.173.12:11:22.73#ibcon#end of sib2, iclass 39, count 2 2006.173.12:11:22.73#ibcon#*after write, iclass 39, count 2 2006.173.12:11:22.73#ibcon#*before return 0, iclass 39, count 2 2006.173.12:11:22.73#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.12:11:22.73#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.12:11:22.73#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.12:11:22.73#ibcon#ireg 7 cls_cnt 0 2006.173.12:11:22.73#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.12:11:22.85#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.12:11:22.85#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.12:11:22.85#ibcon#enter wrdev, iclass 39, count 0 2006.173.12:11:22.85#ibcon#first serial, iclass 39, count 0 2006.173.12:11:22.85#ibcon#enter sib2, iclass 39, count 0 2006.173.12:11:22.85#ibcon#flushed, iclass 39, count 0 2006.173.12:11:22.85#ibcon#about to write, iclass 39, count 0 2006.173.12:11:22.85#ibcon#wrote, iclass 39, count 0 2006.173.12:11:22.85#ibcon#about to read 3, iclass 39, count 0 2006.173.12:11:22.87#ibcon#read 3, iclass 39, count 0 2006.173.12:11:22.87#ibcon#about to read 4, iclass 39, count 0 2006.173.12:11:22.87#ibcon#read 4, iclass 39, count 0 2006.173.12:11:22.87#ibcon#about to read 5, iclass 39, count 0 2006.173.12:11:22.87#ibcon#read 5, iclass 39, count 0 2006.173.12:11:22.87#ibcon#about to read 6, iclass 39, count 0 2006.173.12:11:22.87#ibcon#read 6, iclass 39, count 0 2006.173.12:11:22.87#ibcon#end of sib2, iclass 39, count 0 2006.173.12:11:22.87#ibcon#*mode == 0, iclass 39, count 0 2006.173.12:11:22.87#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.12:11:22.87#ibcon#[25=USB\r\n] 2006.173.12:11:22.87#ibcon#*before write, iclass 39, count 0 2006.173.12:11:22.87#ibcon#enter sib2, iclass 39, count 0 2006.173.12:11:22.87#ibcon#flushed, iclass 39, count 0 2006.173.12:11:22.87#ibcon#about to write, iclass 39, count 0 2006.173.12:11:22.87#ibcon#wrote, iclass 39, count 0 2006.173.12:11:22.87#ibcon#about to read 3, iclass 39, count 0 2006.173.12:11:22.90#ibcon#read 3, iclass 39, count 0 2006.173.12:11:22.90#ibcon#about to read 4, iclass 39, count 0 2006.173.12:11:22.90#ibcon#read 4, iclass 39, count 0 2006.173.12:11:22.90#ibcon#about to read 5, iclass 39, count 0 2006.173.12:11:22.90#ibcon#read 5, iclass 39, count 0 2006.173.12:11:22.90#ibcon#about to read 6, iclass 39, count 0 2006.173.12:11:22.90#ibcon#read 6, iclass 39, count 0 2006.173.12:11:22.90#ibcon#end of sib2, iclass 39, count 0 2006.173.12:11:22.90#ibcon#*after write, iclass 39, count 0 2006.173.12:11:22.90#ibcon#*before return 0, iclass 39, count 0 2006.173.12:11:22.90#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.12:11:22.90#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.12:11:22.90#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.12:11:22.90#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.12:11:22.90$vck44/valo=6,814.99 2006.173.12:11:22.90#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.12:11:22.90#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.12:11:22.90#ibcon#ireg 17 cls_cnt 0 2006.173.12:11:22.90#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.12:11:22.90#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.12:11:22.90#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.12:11:22.90#ibcon#enter wrdev, iclass 3, count 0 2006.173.12:11:22.90#ibcon#first serial, iclass 3, count 0 2006.173.12:11:22.90#ibcon#enter sib2, iclass 3, count 0 2006.173.12:11:22.90#ibcon#flushed, iclass 3, count 0 2006.173.12:11:22.90#ibcon#about to write, iclass 3, count 0 2006.173.12:11:22.90#ibcon#wrote, iclass 3, count 0 2006.173.12:11:22.90#ibcon#about to read 3, iclass 3, count 0 2006.173.12:11:22.92#ibcon#read 3, iclass 3, count 0 2006.173.12:11:22.92#ibcon#about to read 4, iclass 3, count 0 2006.173.12:11:22.92#ibcon#read 4, iclass 3, count 0 2006.173.12:11:22.92#ibcon#about to read 5, iclass 3, count 0 2006.173.12:11:22.92#ibcon#read 5, iclass 3, count 0 2006.173.12:11:22.92#ibcon#about to read 6, iclass 3, count 0 2006.173.12:11:22.92#ibcon#read 6, iclass 3, count 0 2006.173.12:11:22.92#ibcon#end of sib2, iclass 3, count 0 2006.173.12:11:22.92#ibcon#*mode == 0, iclass 3, count 0 2006.173.12:11:22.92#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.12:11:22.92#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.12:11:22.92#ibcon#*before write, iclass 3, count 0 2006.173.12:11:22.92#ibcon#enter sib2, iclass 3, count 0 2006.173.12:11:22.92#ibcon#flushed, iclass 3, count 0 2006.173.12:11:22.92#ibcon#about to write, iclass 3, count 0 2006.173.12:11:22.92#ibcon#wrote, iclass 3, count 0 2006.173.12:11:22.92#ibcon#about to read 3, iclass 3, count 0 2006.173.12:11:22.96#ibcon#read 3, iclass 3, count 0 2006.173.12:11:22.96#ibcon#about to read 4, iclass 3, count 0 2006.173.12:11:22.96#ibcon#read 4, iclass 3, count 0 2006.173.12:11:22.96#ibcon#about to read 5, iclass 3, count 0 2006.173.12:11:22.96#ibcon#read 5, iclass 3, count 0 2006.173.12:11:22.96#ibcon#about to read 6, iclass 3, count 0 2006.173.12:11:22.96#ibcon#read 6, iclass 3, count 0 2006.173.12:11:22.96#ibcon#end of sib2, iclass 3, count 0 2006.173.12:11:22.96#ibcon#*after write, iclass 3, count 0 2006.173.12:11:22.96#ibcon#*before return 0, iclass 3, count 0 2006.173.12:11:22.96#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.12:11:22.96#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.12:11:22.96#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.12:11:22.96#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.12:11:22.96$vck44/va=6,3 2006.173.12:11:22.96#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.12:11:22.96#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.12:11:22.96#ibcon#ireg 11 cls_cnt 2 2006.173.12:11:22.96#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.12:11:23.02#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.12:11:23.02#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.12:11:23.02#ibcon#enter wrdev, iclass 5, count 2 2006.173.12:11:23.02#ibcon#first serial, iclass 5, count 2 2006.173.12:11:23.02#ibcon#enter sib2, iclass 5, count 2 2006.173.12:11:23.02#ibcon#flushed, iclass 5, count 2 2006.173.12:11:23.02#ibcon#about to write, iclass 5, count 2 2006.173.12:11:23.02#ibcon#wrote, iclass 5, count 2 2006.173.12:11:23.02#ibcon#about to read 3, iclass 5, count 2 2006.173.12:11:23.04#ibcon#read 3, iclass 5, count 2 2006.173.12:11:23.04#ibcon#about to read 4, iclass 5, count 2 2006.173.12:11:23.04#ibcon#read 4, iclass 5, count 2 2006.173.12:11:23.04#ibcon#about to read 5, iclass 5, count 2 2006.173.12:11:23.04#ibcon#read 5, iclass 5, count 2 2006.173.12:11:23.04#ibcon#about to read 6, iclass 5, count 2 2006.173.12:11:23.04#ibcon#read 6, iclass 5, count 2 2006.173.12:11:23.04#ibcon#end of sib2, iclass 5, count 2 2006.173.12:11:23.04#ibcon#*mode == 0, iclass 5, count 2 2006.173.12:11:23.04#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.12:11:23.04#ibcon#[25=AT06-03\r\n] 2006.173.12:11:23.04#ibcon#*before write, iclass 5, count 2 2006.173.12:11:23.04#ibcon#enter sib2, iclass 5, count 2 2006.173.12:11:23.04#ibcon#flushed, iclass 5, count 2 2006.173.12:11:23.04#ibcon#about to write, iclass 5, count 2 2006.173.12:11:23.04#ibcon#wrote, iclass 5, count 2 2006.173.12:11:23.04#ibcon#about to read 3, iclass 5, count 2 2006.173.12:11:23.07#ibcon#read 3, iclass 5, count 2 2006.173.12:11:23.07#ibcon#about to read 4, iclass 5, count 2 2006.173.12:11:23.07#ibcon#read 4, iclass 5, count 2 2006.173.12:11:23.07#ibcon#about to read 5, iclass 5, count 2 2006.173.12:11:23.07#ibcon#read 5, iclass 5, count 2 2006.173.12:11:23.07#ibcon#about to read 6, iclass 5, count 2 2006.173.12:11:23.07#ibcon#read 6, iclass 5, count 2 2006.173.12:11:23.07#ibcon#end of sib2, iclass 5, count 2 2006.173.12:11:23.07#ibcon#*after write, iclass 5, count 2 2006.173.12:11:23.07#ibcon#*before return 0, iclass 5, count 2 2006.173.12:11:23.07#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.12:11:23.07#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.12:11:23.07#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.12:11:23.07#ibcon#ireg 7 cls_cnt 0 2006.173.12:11:23.07#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.12:11:23.19#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.12:11:23.19#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.12:11:23.19#ibcon#enter wrdev, iclass 5, count 0 2006.173.12:11:23.19#ibcon#first serial, iclass 5, count 0 2006.173.12:11:23.19#ibcon#enter sib2, iclass 5, count 0 2006.173.12:11:23.19#ibcon#flushed, iclass 5, count 0 2006.173.12:11:23.19#ibcon#about to write, iclass 5, count 0 2006.173.12:11:23.19#ibcon#wrote, iclass 5, count 0 2006.173.12:11:23.19#ibcon#about to read 3, iclass 5, count 0 2006.173.12:11:23.21#ibcon#read 3, iclass 5, count 0 2006.173.12:11:23.21#ibcon#about to read 4, iclass 5, count 0 2006.173.12:11:23.21#ibcon#read 4, iclass 5, count 0 2006.173.12:11:23.21#ibcon#about to read 5, iclass 5, count 0 2006.173.12:11:23.21#ibcon#read 5, iclass 5, count 0 2006.173.12:11:23.21#ibcon#about to read 6, iclass 5, count 0 2006.173.12:11:23.21#ibcon#read 6, iclass 5, count 0 2006.173.12:11:23.21#ibcon#end of sib2, iclass 5, count 0 2006.173.12:11:23.21#ibcon#*mode == 0, iclass 5, count 0 2006.173.12:11:23.21#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.12:11:23.21#ibcon#[25=USB\r\n] 2006.173.12:11:23.21#ibcon#*before write, iclass 5, count 0 2006.173.12:11:23.21#ibcon#enter sib2, iclass 5, count 0 2006.173.12:11:23.21#ibcon#flushed, iclass 5, count 0 2006.173.12:11:23.21#ibcon#about to write, iclass 5, count 0 2006.173.12:11:23.21#ibcon#wrote, iclass 5, count 0 2006.173.12:11:23.21#ibcon#about to read 3, iclass 5, count 0 2006.173.12:11:23.24#ibcon#read 3, iclass 5, count 0 2006.173.12:11:23.24#ibcon#about to read 4, iclass 5, count 0 2006.173.12:11:23.24#ibcon#read 4, iclass 5, count 0 2006.173.12:11:23.24#ibcon#about to read 5, iclass 5, count 0 2006.173.12:11:23.24#ibcon#read 5, iclass 5, count 0 2006.173.12:11:23.24#ibcon#about to read 6, iclass 5, count 0 2006.173.12:11:23.24#ibcon#read 6, iclass 5, count 0 2006.173.12:11:23.24#ibcon#end of sib2, iclass 5, count 0 2006.173.12:11:23.24#ibcon#*after write, iclass 5, count 0 2006.173.12:11:23.24#ibcon#*before return 0, iclass 5, count 0 2006.173.12:11:23.24#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.12:11:23.24#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.12:11:23.24#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.12:11:23.24#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.12:11:23.24$vck44/valo=7,864.99 2006.173.12:11:23.24#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.12:11:23.24#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.12:11:23.24#ibcon#ireg 17 cls_cnt 0 2006.173.12:11:23.24#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.12:11:23.24#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.12:11:23.24#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.12:11:23.24#ibcon#enter wrdev, iclass 7, count 0 2006.173.12:11:23.24#ibcon#first serial, iclass 7, count 0 2006.173.12:11:23.24#ibcon#enter sib2, iclass 7, count 0 2006.173.12:11:23.24#ibcon#flushed, iclass 7, count 0 2006.173.12:11:23.24#ibcon#about to write, iclass 7, count 0 2006.173.12:11:23.24#ibcon#wrote, iclass 7, count 0 2006.173.12:11:23.24#ibcon#about to read 3, iclass 7, count 0 2006.173.12:11:23.26#ibcon#read 3, iclass 7, count 0 2006.173.12:11:23.26#ibcon#about to read 4, iclass 7, count 0 2006.173.12:11:23.26#ibcon#read 4, iclass 7, count 0 2006.173.12:11:23.26#ibcon#about to read 5, iclass 7, count 0 2006.173.12:11:23.26#ibcon#read 5, iclass 7, count 0 2006.173.12:11:23.26#ibcon#about to read 6, iclass 7, count 0 2006.173.12:11:23.26#ibcon#read 6, iclass 7, count 0 2006.173.12:11:23.26#ibcon#end of sib2, iclass 7, count 0 2006.173.12:11:23.26#ibcon#*mode == 0, iclass 7, count 0 2006.173.12:11:23.26#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.12:11:23.26#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.12:11:23.26#ibcon#*before write, iclass 7, count 0 2006.173.12:11:23.26#ibcon#enter sib2, iclass 7, count 0 2006.173.12:11:23.26#ibcon#flushed, iclass 7, count 0 2006.173.12:11:23.26#ibcon#about to write, iclass 7, count 0 2006.173.12:11:23.26#ibcon#wrote, iclass 7, count 0 2006.173.12:11:23.26#ibcon#about to read 3, iclass 7, count 0 2006.173.12:11:23.30#ibcon#read 3, iclass 7, count 0 2006.173.12:11:23.30#ibcon#about to read 4, iclass 7, count 0 2006.173.12:11:23.30#ibcon#read 4, iclass 7, count 0 2006.173.12:11:23.30#ibcon#about to read 5, iclass 7, count 0 2006.173.12:11:23.30#ibcon#read 5, iclass 7, count 0 2006.173.12:11:23.30#ibcon#about to read 6, iclass 7, count 0 2006.173.12:11:23.30#ibcon#read 6, iclass 7, count 0 2006.173.12:11:23.30#ibcon#end of sib2, iclass 7, count 0 2006.173.12:11:23.30#ibcon#*after write, iclass 7, count 0 2006.173.12:11:23.30#ibcon#*before return 0, iclass 7, count 0 2006.173.12:11:23.30#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.12:11:23.30#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.12:11:23.30#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.12:11:23.30#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.12:11:23.30$vck44/va=7,4 2006.173.12:11:23.30#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.12:11:23.30#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.12:11:23.30#ibcon#ireg 11 cls_cnt 2 2006.173.12:11:23.30#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.12:11:23.36#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.12:11:23.36#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.12:11:23.36#ibcon#enter wrdev, iclass 11, count 2 2006.173.12:11:23.36#ibcon#first serial, iclass 11, count 2 2006.173.12:11:23.36#ibcon#enter sib2, iclass 11, count 2 2006.173.12:11:23.36#ibcon#flushed, iclass 11, count 2 2006.173.12:11:23.36#ibcon#about to write, iclass 11, count 2 2006.173.12:11:23.36#ibcon#wrote, iclass 11, count 2 2006.173.12:11:23.36#ibcon#about to read 3, iclass 11, count 2 2006.173.12:11:23.38#ibcon#read 3, iclass 11, count 2 2006.173.12:11:23.38#ibcon#about to read 4, iclass 11, count 2 2006.173.12:11:23.38#ibcon#read 4, iclass 11, count 2 2006.173.12:11:23.38#ibcon#about to read 5, iclass 11, count 2 2006.173.12:11:23.38#ibcon#read 5, iclass 11, count 2 2006.173.12:11:23.38#ibcon#about to read 6, iclass 11, count 2 2006.173.12:11:23.38#ibcon#read 6, iclass 11, count 2 2006.173.12:11:23.38#ibcon#end of sib2, iclass 11, count 2 2006.173.12:11:23.38#ibcon#*mode == 0, iclass 11, count 2 2006.173.12:11:23.38#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.12:11:23.38#ibcon#[25=AT07-04\r\n] 2006.173.12:11:23.38#ibcon#*before write, iclass 11, count 2 2006.173.12:11:23.38#ibcon#enter sib2, iclass 11, count 2 2006.173.12:11:23.38#ibcon#flushed, iclass 11, count 2 2006.173.12:11:23.38#ibcon#about to write, iclass 11, count 2 2006.173.12:11:23.38#ibcon#wrote, iclass 11, count 2 2006.173.12:11:23.38#ibcon#about to read 3, iclass 11, count 2 2006.173.12:11:23.41#ibcon#read 3, iclass 11, count 2 2006.173.12:11:23.41#ibcon#about to read 4, iclass 11, count 2 2006.173.12:11:23.41#ibcon#read 4, iclass 11, count 2 2006.173.12:11:23.41#ibcon#about to read 5, iclass 11, count 2 2006.173.12:11:23.41#ibcon#read 5, iclass 11, count 2 2006.173.12:11:23.41#ibcon#about to read 6, iclass 11, count 2 2006.173.12:11:23.41#ibcon#read 6, iclass 11, count 2 2006.173.12:11:23.41#ibcon#end of sib2, iclass 11, count 2 2006.173.12:11:23.41#ibcon#*after write, iclass 11, count 2 2006.173.12:11:23.41#ibcon#*before return 0, iclass 11, count 2 2006.173.12:11:23.41#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.12:11:23.41#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.12:11:23.41#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.12:11:23.41#ibcon#ireg 7 cls_cnt 0 2006.173.12:11:23.41#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.12:11:23.53#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.12:11:23.53#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.12:11:23.53#ibcon#enter wrdev, iclass 11, count 0 2006.173.12:11:23.53#ibcon#first serial, iclass 11, count 0 2006.173.12:11:23.53#ibcon#enter sib2, iclass 11, count 0 2006.173.12:11:23.53#ibcon#flushed, iclass 11, count 0 2006.173.12:11:23.53#ibcon#about to write, iclass 11, count 0 2006.173.12:11:23.53#ibcon#wrote, iclass 11, count 0 2006.173.12:11:23.53#ibcon#about to read 3, iclass 11, count 0 2006.173.12:11:23.55#ibcon#read 3, iclass 11, count 0 2006.173.12:11:23.55#ibcon#about to read 4, iclass 11, count 0 2006.173.12:11:23.55#ibcon#read 4, iclass 11, count 0 2006.173.12:11:23.55#ibcon#about to read 5, iclass 11, count 0 2006.173.12:11:23.55#ibcon#read 5, iclass 11, count 0 2006.173.12:11:23.55#ibcon#about to read 6, iclass 11, count 0 2006.173.12:11:23.55#ibcon#read 6, iclass 11, count 0 2006.173.12:11:23.55#ibcon#end of sib2, iclass 11, count 0 2006.173.12:11:23.55#ibcon#*mode == 0, iclass 11, count 0 2006.173.12:11:23.55#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.12:11:23.55#ibcon#[25=USB\r\n] 2006.173.12:11:23.55#ibcon#*before write, iclass 11, count 0 2006.173.12:11:23.55#ibcon#enter sib2, iclass 11, count 0 2006.173.12:11:23.55#ibcon#flushed, iclass 11, count 0 2006.173.12:11:23.55#ibcon#about to write, iclass 11, count 0 2006.173.12:11:23.55#ibcon#wrote, iclass 11, count 0 2006.173.12:11:23.55#ibcon#about to read 3, iclass 11, count 0 2006.173.12:11:23.58#ibcon#read 3, iclass 11, count 0 2006.173.12:11:23.58#ibcon#about to read 4, iclass 11, count 0 2006.173.12:11:23.58#ibcon#read 4, iclass 11, count 0 2006.173.12:11:23.58#ibcon#about to read 5, iclass 11, count 0 2006.173.12:11:23.58#ibcon#read 5, iclass 11, count 0 2006.173.12:11:23.58#ibcon#about to read 6, iclass 11, count 0 2006.173.12:11:23.58#ibcon#read 6, iclass 11, count 0 2006.173.12:11:23.58#ibcon#end of sib2, iclass 11, count 0 2006.173.12:11:23.58#ibcon#*after write, iclass 11, count 0 2006.173.12:11:23.58#ibcon#*before return 0, iclass 11, count 0 2006.173.12:11:23.58#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.12:11:23.58#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.12:11:23.58#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.12:11:23.58#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.12:11:23.58$vck44/valo=8,884.99 2006.173.12:11:23.58#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.12:11:23.58#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.12:11:23.58#ibcon#ireg 17 cls_cnt 0 2006.173.12:11:23.58#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.12:11:23.58#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.12:11:23.58#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.12:11:23.58#ibcon#enter wrdev, iclass 13, count 0 2006.173.12:11:23.58#ibcon#first serial, iclass 13, count 0 2006.173.12:11:23.58#ibcon#enter sib2, iclass 13, count 0 2006.173.12:11:23.58#ibcon#flushed, iclass 13, count 0 2006.173.12:11:23.58#ibcon#about to write, iclass 13, count 0 2006.173.12:11:23.58#ibcon#wrote, iclass 13, count 0 2006.173.12:11:23.58#ibcon#about to read 3, iclass 13, count 0 2006.173.12:11:23.60#ibcon#read 3, iclass 13, count 0 2006.173.12:11:23.60#ibcon#about to read 4, iclass 13, count 0 2006.173.12:11:23.60#ibcon#read 4, iclass 13, count 0 2006.173.12:11:23.60#ibcon#about to read 5, iclass 13, count 0 2006.173.12:11:23.60#ibcon#read 5, iclass 13, count 0 2006.173.12:11:23.60#ibcon#about to read 6, iclass 13, count 0 2006.173.12:11:23.60#ibcon#read 6, iclass 13, count 0 2006.173.12:11:23.60#ibcon#end of sib2, iclass 13, count 0 2006.173.12:11:23.60#ibcon#*mode == 0, iclass 13, count 0 2006.173.12:11:23.60#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.12:11:23.60#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.12:11:23.60#ibcon#*before write, iclass 13, count 0 2006.173.12:11:23.60#ibcon#enter sib2, iclass 13, count 0 2006.173.12:11:23.60#ibcon#flushed, iclass 13, count 0 2006.173.12:11:23.60#ibcon#about to write, iclass 13, count 0 2006.173.12:11:23.60#ibcon#wrote, iclass 13, count 0 2006.173.12:11:23.60#ibcon#about to read 3, iclass 13, count 0 2006.173.12:11:23.64#ibcon#read 3, iclass 13, count 0 2006.173.12:11:23.64#ibcon#about to read 4, iclass 13, count 0 2006.173.12:11:23.64#ibcon#read 4, iclass 13, count 0 2006.173.12:11:23.64#ibcon#about to read 5, iclass 13, count 0 2006.173.12:11:23.64#ibcon#read 5, iclass 13, count 0 2006.173.12:11:23.64#ibcon#about to read 6, iclass 13, count 0 2006.173.12:11:23.64#ibcon#read 6, iclass 13, count 0 2006.173.12:11:23.64#ibcon#end of sib2, iclass 13, count 0 2006.173.12:11:23.64#ibcon#*after write, iclass 13, count 0 2006.173.12:11:23.64#ibcon#*before return 0, iclass 13, count 0 2006.173.12:11:23.64#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.12:11:23.64#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.12:11:23.64#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.12:11:23.64#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.12:11:23.64$vck44/va=8,4 2006.173.12:11:23.64#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.12:11:23.64#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.12:11:23.64#ibcon#ireg 11 cls_cnt 2 2006.173.12:11:23.64#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.12:11:23.70#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.12:11:23.70#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.12:11:23.70#ibcon#enter wrdev, iclass 15, count 2 2006.173.12:11:23.70#ibcon#first serial, iclass 15, count 2 2006.173.12:11:23.70#ibcon#enter sib2, iclass 15, count 2 2006.173.12:11:23.70#ibcon#flushed, iclass 15, count 2 2006.173.12:11:23.70#ibcon#about to write, iclass 15, count 2 2006.173.12:11:23.70#ibcon#wrote, iclass 15, count 2 2006.173.12:11:23.70#ibcon#about to read 3, iclass 15, count 2 2006.173.12:11:23.72#ibcon#read 3, iclass 15, count 2 2006.173.12:11:23.72#ibcon#about to read 4, iclass 15, count 2 2006.173.12:11:23.72#ibcon#read 4, iclass 15, count 2 2006.173.12:11:23.72#ibcon#about to read 5, iclass 15, count 2 2006.173.12:11:23.72#ibcon#read 5, iclass 15, count 2 2006.173.12:11:23.72#ibcon#about to read 6, iclass 15, count 2 2006.173.12:11:23.72#ibcon#read 6, iclass 15, count 2 2006.173.12:11:23.72#ibcon#end of sib2, iclass 15, count 2 2006.173.12:11:23.72#ibcon#*mode == 0, iclass 15, count 2 2006.173.12:11:23.72#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.12:11:23.72#ibcon#[25=AT08-04\r\n] 2006.173.12:11:23.72#ibcon#*before write, iclass 15, count 2 2006.173.12:11:23.72#ibcon#enter sib2, iclass 15, count 2 2006.173.12:11:23.72#ibcon#flushed, iclass 15, count 2 2006.173.12:11:23.72#ibcon#about to write, iclass 15, count 2 2006.173.12:11:23.72#ibcon#wrote, iclass 15, count 2 2006.173.12:11:23.72#ibcon#about to read 3, iclass 15, count 2 2006.173.12:11:23.75#ibcon#read 3, iclass 15, count 2 2006.173.12:11:23.75#ibcon#about to read 4, iclass 15, count 2 2006.173.12:11:23.75#ibcon#read 4, iclass 15, count 2 2006.173.12:11:23.75#ibcon#about to read 5, iclass 15, count 2 2006.173.12:11:23.75#ibcon#read 5, iclass 15, count 2 2006.173.12:11:23.75#ibcon#about to read 6, iclass 15, count 2 2006.173.12:11:23.75#ibcon#read 6, iclass 15, count 2 2006.173.12:11:23.75#ibcon#end of sib2, iclass 15, count 2 2006.173.12:11:23.75#ibcon#*after write, iclass 15, count 2 2006.173.12:11:23.75#ibcon#*before return 0, iclass 15, count 2 2006.173.12:11:23.75#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.12:11:23.75#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.12:11:23.75#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.12:11:23.75#ibcon#ireg 7 cls_cnt 0 2006.173.12:11:23.75#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.12:11:23.87#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.12:11:23.87#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.12:11:23.87#ibcon#enter wrdev, iclass 15, count 0 2006.173.12:11:23.87#ibcon#first serial, iclass 15, count 0 2006.173.12:11:23.87#ibcon#enter sib2, iclass 15, count 0 2006.173.12:11:23.87#ibcon#flushed, iclass 15, count 0 2006.173.12:11:23.87#ibcon#about to write, iclass 15, count 0 2006.173.12:11:23.87#ibcon#wrote, iclass 15, count 0 2006.173.12:11:23.87#ibcon#about to read 3, iclass 15, count 0 2006.173.12:11:23.89#ibcon#read 3, iclass 15, count 0 2006.173.12:11:23.89#ibcon#about to read 4, iclass 15, count 0 2006.173.12:11:23.89#ibcon#read 4, iclass 15, count 0 2006.173.12:11:23.89#ibcon#about to read 5, iclass 15, count 0 2006.173.12:11:23.89#ibcon#read 5, iclass 15, count 0 2006.173.12:11:23.89#ibcon#about to read 6, iclass 15, count 0 2006.173.12:11:23.89#ibcon#read 6, iclass 15, count 0 2006.173.12:11:23.89#ibcon#end of sib2, iclass 15, count 0 2006.173.12:11:23.89#ibcon#*mode == 0, iclass 15, count 0 2006.173.12:11:23.89#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.12:11:23.89#ibcon#[25=USB\r\n] 2006.173.12:11:23.89#ibcon#*before write, iclass 15, count 0 2006.173.12:11:23.89#ibcon#enter sib2, iclass 15, count 0 2006.173.12:11:23.89#ibcon#flushed, iclass 15, count 0 2006.173.12:11:23.89#ibcon#about to write, iclass 15, count 0 2006.173.12:11:23.89#ibcon#wrote, iclass 15, count 0 2006.173.12:11:23.89#ibcon#about to read 3, iclass 15, count 0 2006.173.12:11:23.92#ibcon#read 3, iclass 15, count 0 2006.173.12:11:23.92#ibcon#about to read 4, iclass 15, count 0 2006.173.12:11:23.92#ibcon#read 4, iclass 15, count 0 2006.173.12:11:23.92#ibcon#about to read 5, iclass 15, count 0 2006.173.12:11:23.92#ibcon#read 5, iclass 15, count 0 2006.173.12:11:23.92#ibcon#about to read 6, iclass 15, count 0 2006.173.12:11:23.92#ibcon#read 6, iclass 15, count 0 2006.173.12:11:23.92#ibcon#end of sib2, iclass 15, count 0 2006.173.12:11:23.92#ibcon#*after write, iclass 15, count 0 2006.173.12:11:23.92#ibcon#*before return 0, iclass 15, count 0 2006.173.12:11:23.92#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.12:11:23.92#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.12:11:23.92#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.12:11:23.92#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.12:11:23.92$vck44/vblo=1,629.99 2006.173.12:11:23.92#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.12:11:23.92#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.12:11:23.92#ibcon#ireg 17 cls_cnt 0 2006.173.12:11:23.92#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.12:11:23.92#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.12:11:23.92#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.12:11:23.92#ibcon#enter wrdev, iclass 17, count 0 2006.173.12:11:23.92#ibcon#first serial, iclass 17, count 0 2006.173.12:11:23.92#ibcon#enter sib2, iclass 17, count 0 2006.173.12:11:23.92#ibcon#flushed, iclass 17, count 0 2006.173.12:11:23.92#ibcon#about to write, iclass 17, count 0 2006.173.12:11:23.92#ibcon#wrote, iclass 17, count 0 2006.173.12:11:23.92#ibcon#about to read 3, iclass 17, count 0 2006.173.12:11:23.94#ibcon#read 3, iclass 17, count 0 2006.173.12:11:23.94#ibcon#about to read 4, iclass 17, count 0 2006.173.12:11:23.94#ibcon#read 4, iclass 17, count 0 2006.173.12:11:23.94#ibcon#about to read 5, iclass 17, count 0 2006.173.12:11:23.94#ibcon#read 5, iclass 17, count 0 2006.173.12:11:23.94#ibcon#about to read 6, iclass 17, count 0 2006.173.12:11:23.94#ibcon#read 6, iclass 17, count 0 2006.173.12:11:23.94#ibcon#end of sib2, iclass 17, count 0 2006.173.12:11:23.94#ibcon#*mode == 0, iclass 17, count 0 2006.173.12:11:23.94#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.12:11:23.94#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.12:11:23.94#ibcon#*before write, iclass 17, count 0 2006.173.12:11:23.94#ibcon#enter sib2, iclass 17, count 0 2006.173.12:11:23.94#ibcon#flushed, iclass 17, count 0 2006.173.12:11:23.94#ibcon#about to write, iclass 17, count 0 2006.173.12:11:23.94#ibcon#wrote, iclass 17, count 0 2006.173.12:11:23.94#ibcon#about to read 3, iclass 17, count 0 2006.173.12:11:23.98#ibcon#read 3, iclass 17, count 0 2006.173.12:11:23.98#ibcon#about to read 4, iclass 17, count 0 2006.173.12:11:23.98#ibcon#read 4, iclass 17, count 0 2006.173.12:11:23.98#ibcon#about to read 5, iclass 17, count 0 2006.173.12:11:23.98#ibcon#read 5, iclass 17, count 0 2006.173.12:11:23.98#ibcon#about to read 6, iclass 17, count 0 2006.173.12:11:23.98#ibcon#read 6, iclass 17, count 0 2006.173.12:11:23.98#ibcon#end of sib2, iclass 17, count 0 2006.173.12:11:23.98#ibcon#*after write, iclass 17, count 0 2006.173.12:11:23.98#ibcon#*before return 0, iclass 17, count 0 2006.173.12:11:23.98#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.12:11:23.98#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.12:11:23.98#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.12:11:23.98#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.12:11:23.98$vck44/vb=1,4 2006.173.12:11:23.98#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.12:11:23.98#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.12:11:23.98#ibcon#ireg 11 cls_cnt 2 2006.173.12:11:23.98#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.12:11:23.98#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.12:11:23.98#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.12:11:23.98#ibcon#enter wrdev, iclass 19, count 2 2006.173.12:11:23.98#ibcon#first serial, iclass 19, count 2 2006.173.12:11:23.98#ibcon#enter sib2, iclass 19, count 2 2006.173.12:11:23.98#ibcon#flushed, iclass 19, count 2 2006.173.12:11:23.98#ibcon#about to write, iclass 19, count 2 2006.173.12:11:23.98#ibcon#wrote, iclass 19, count 2 2006.173.12:11:23.98#ibcon#about to read 3, iclass 19, count 2 2006.173.12:11:24.00#ibcon#read 3, iclass 19, count 2 2006.173.12:11:24.00#ibcon#about to read 4, iclass 19, count 2 2006.173.12:11:24.00#ibcon#read 4, iclass 19, count 2 2006.173.12:11:24.00#ibcon#about to read 5, iclass 19, count 2 2006.173.12:11:24.00#ibcon#read 5, iclass 19, count 2 2006.173.12:11:24.00#ibcon#about to read 6, iclass 19, count 2 2006.173.12:11:24.00#ibcon#read 6, iclass 19, count 2 2006.173.12:11:24.00#ibcon#end of sib2, iclass 19, count 2 2006.173.12:11:24.00#ibcon#*mode == 0, iclass 19, count 2 2006.173.12:11:24.00#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.12:11:24.00#ibcon#[27=AT01-04\r\n] 2006.173.12:11:24.00#ibcon#*before write, iclass 19, count 2 2006.173.12:11:24.00#ibcon#enter sib2, iclass 19, count 2 2006.173.12:11:24.00#ibcon#flushed, iclass 19, count 2 2006.173.12:11:24.00#ibcon#about to write, iclass 19, count 2 2006.173.12:11:24.00#ibcon#wrote, iclass 19, count 2 2006.173.12:11:24.00#ibcon#about to read 3, iclass 19, count 2 2006.173.12:11:24.03#ibcon#read 3, iclass 19, count 2 2006.173.12:11:24.03#ibcon#about to read 4, iclass 19, count 2 2006.173.12:11:24.03#ibcon#read 4, iclass 19, count 2 2006.173.12:11:24.03#ibcon#about to read 5, iclass 19, count 2 2006.173.12:11:24.03#ibcon#read 5, iclass 19, count 2 2006.173.12:11:24.03#ibcon#about to read 6, iclass 19, count 2 2006.173.12:11:24.03#ibcon#read 6, iclass 19, count 2 2006.173.12:11:24.03#ibcon#end of sib2, iclass 19, count 2 2006.173.12:11:24.03#ibcon#*after write, iclass 19, count 2 2006.173.12:11:24.03#ibcon#*before return 0, iclass 19, count 2 2006.173.12:11:24.03#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.12:11:24.03#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.12:11:24.03#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.12:11:24.03#ibcon#ireg 7 cls_cnt 0 2006.173.12:11:24.03#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.12:11:24.15#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.12:11:24.15#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.12:11:24.15#ibcon#enter wrdev, iclass 19, count 0 2006.173.12:11:24.15#ibcon#first serial, iclass 19, count 0 2006.173.12:11:24.15#ibcon#enter sib2, iclass 19, count 0 2006.173.12:11:24.15#ibcon#flushed, iclass 19, count 0 2006.173.12:11:24.15#ibcon#about to write, iclass 19, count 0 2006.173.12:11:24.15#ibcon#wrote, iclass 19, count 0 2006.173.12:11:24.15#ibcon#about to read 3, iclass 19, count 0 2006.173.12:11:24.17#ibcon#read 3, iclass 19, count 0 2006.173.12:11:24.17#ibcon#about to read 4, iclass 19, count 0 2006.173.12:11:24.17#ibcon#read 4, iclass 19, count 0 2006.173.12:11:24.17#ibcon#about to read 5, iclass 19, count 0 2006.173.12:11:24.17#ibcon#read 5, iclass 19, count 0 2006.173.12:11:24.17#ibcon#about to read 6, iclass 19, count 0 2006.173.12:11:24.17#ibcon#read 6, iclass 19, count 0 2006.173.12:11:24.17#ibcon#end of sib2, iclass 19, count 0 2006.173.12:11:24.17#ibcon#*mode == 0, iclass 19, count 0 2006.173.12:11:24.17#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.12:11:24.17#ibcon#[27=USB\r\n] 2006.173.12:11:24.17#ibcon#*before write, iclass 19, count 0 2006.173.12:11:24.17#ibcon#enter sib2, iclass 19, count 0 2006.173.12:11:24.17#ibcon#flushed, iclass 19, count 0 2006.173.12:11:24.17#ibcon#about to write, iclass 19, count 0 2006.173.12:11:24.17#ibcon#wrote, iclass 19, count 0 2006.173.12:11:24.17#ibcon#about to read 3, iclass 19, count 0 2006.173.12:11:24.20#ibcon#read 3, iclass 19, count 0 2006.173.12:11:24.20#ibcon#about to read 4, iclass 19, count 0 2006.173.12:11:24.20#ibcon#read 4, iclass 19, count 0 2006.173.12:11:24.20#ibcon#about to read 5, iclass 19, count 0 2006.173.12:11:24.20#ibcon#read 5, iclass 19, count 0 2006.173.12:11:24.20#ibcon#about to read 6, iclass 19, count 0 2006.173.12:11:24.20#ibcon#read 6, iclass 19, count 0 2006.173.12:11:24.20#ibcon#end of sib2, iclass 19, count 0 2006.173.12:11:24.20#ibcon#*after write, iclass 19, count 0 2006.173.12:11:24.20#ibcon#*before return 0, iclass 19, count 0 2006.173.12:11:24.20#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.12:11:24.20#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.12:11:24.20#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.12:11:24.20#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.12:11:24.20$vck44/vblo=2,634.99 2006.173.12:11:24.20#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.12:11:24.20#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.12:11:24.20#ibcon#ireg 17 cls_cnt 0 2006.173.12:11:24.20#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.12:11:24.20#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.12:11:24.20#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.12:11:24.20#ibcon#enter wrdev, iclass 21, count 0 2006.173.12:11:24.20#ibcon#first serial, iclass 21, count 0 2006.173.12:11:24.20#ibcon#enter sib2, iclass 21, count 0 2006.173.12:11:24.20#ibcon#flushed, iclass 21, count 0 2006.173.12:11:24.20#ibcon#about to write, iclass 21, count 0 2006.173.12:11:24.20#ibcon#wrote, iclass 21, count 0 2006.173.12:11:24.20#ibcon#about to read 3, iclass 21, count 0 2006.173.12:11:24.22#ibcon#read 3, iclass 21, count 0 2006.173.12:11:24.22#ibcon#about to read 4, iclass 21, count 0 2006.173.12:11:24.22#ibcon#read 4, iclass 21, count 0 2006.173.12:11:24.22#ibcon#about to read 5, iclass 21, count 0 2006.173.12:11:24.22#ibcon#read 5, iclass 21, count 0 2006.173.12:11:24.22#ibcon#about to read 6, iclass 21, count 0 2006.173.12:11:24.22#ibcon#read 6, iclass 21, count 0 2006.173.12:11:24.22#ibcon#end of sib2, iclass 21, count 0 2006.173.12:11:24.22#ibcon#*mode == 0, iclass 21, count 0 2006.173.12:11:24.22#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.12:11:24.22#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.12:11:24.22#ibcon#*before write, iclass 21, count 0 2006.173.12:11:24.22#ibcon#enter sib2, iclass 21, count 0 2006.173.12:11:24.22#ibcon#flushed, iclass 21, count 0 2006.173.12:11:24.22#ibcon#about to write, iclass 21, count 0 2006.173.12:11:24.22#ibcon#wrote, iclass 21, count 0 2006.173.12:11:24.22#ibcon#about to read 3, iclass 21, count 0 2006.173.12:11:24.26#ibcon#read 3, iclass 21, count 0 2006.173.12:11:24.26#ibcon#about to read 4, iclass 21, count 0 2006.173.12:11:24.26#ibcon#read 4, iclass 21, count 0 2006.173.12:11:24.26#ibcon#about to read 5, iclass 21, count 0 2006.173.12:11:24.26#ibcon#read 5, iclass 21, count 0 2006.173.12:11:24.26#ibcon#about to read 6, iclass 21, count 0 2006.173.12:11:24.26#ibcon#read 6, iclass 21, count 0 2006.173.12:11:24.26#ibcon#end of sib2, iclass 21, count 0 2006.173.12:11:24.26#ibcon#*after write, iclass 21, count 0 2006.173.12:11:24.26#ibcon#*before return 0, iclass 21, count 0 2006.173.12:11:24.26#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.12:11:24.26#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.12:11:24.26#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.12:11:24.26#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.12:11:24.26$vck44/vb=2,4 2006.173.12:11:24.26#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.12:11:24.26#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.12:11:24.26#ibcon#ireg 11 cls_cnt 2 2006.173.12:11:24.26#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.12:11:24.32#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.12:11:24.32#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.12:11:24.32#ibcon#enter wrdev, iclass 23, count 2 2006.173.12:11:24.32#ibcon#first serial, iclass 23, count 2 2006.173.12:11:24.32#ibcon#enter sib2, iclass 23, count 2 2006.173.12:11:24.32#ibcon#flushed, iclass 23, count 2 2006.173.12:11:24.32#ibcon#about to write, iclass 23, count 2 2006.173.12:11:24.32#ibcon#wrote, iclass 23, count 2 2006.173.12:11:24.32#ibcon#about to read 3, iclass 23, count 2 2006.173.12:11:24.34#ibcon#read 3, iclass 23, count 2 2006.173.12:11:24.34#ibcon#about to read 4, iclass 23, count 2 2006.173.12:11:24.34#ibcon#read 4, iclass 23, count 2 2006.173.12:11:24.34#ibcon#about to read 5, iclass 23, count 2 2006.173.12:11:24.34#ibcon#read 5, iclass 23, count 2 2006.173.12:11:24.34#ibcon#about to read 6, iclass 23, count 2 2006.173.12:11:24.34#ibcon#read 6, iclass 23, count 2 2006.173.12:11:24.34#ibcon#end of sib2, iclass 23, count 2 2006.173.12:11:24.34#ibcon#*mode == 0, iclass 23, count 2 2006.173.12:11:24.34#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.12:11:24.34#ibcon#[27=AT02-04\r\n] 2006.173.12:11:24.34#ibcon#*before write, iclass 23, count 2 2006.173.12:11:24.34#ibcon#enter sib2, iclass 23, count 2 2006.173.12:11:24.34#ibcon#flushed, iclass 23, count 2 2006.173.12:11:24.34#ibcon#about to write, iclass 23, count 2 2006.173.12:11:24.34#ibcon#wrote, iclass 23, count 2 2006.173.12:11:24.34#ibcon#about to read 3, iclass 23, count 2 2006.173.12:11:24.37#ibcon#read 3, iclass 23, count 2 2006.173.12:11:24.37#ibcon#about to read 4, iclass 23, count 2 2006.173.12:11:24.37#ibcon#read 4, iclass 23, count 2 2006.173.12:11:24.37#ibcon#about to read 5, iclass 23, count 2 2006.173.12:11:24.37#ibcon#read 5, iclass 23, count 2 2006.173.12:11:24.37#ibcon#about to read 6, iclass 23, count 2 2006.173.12:11:24.37#ibcon#read 6, iclass 23, count 2 2006.173.12:11:24.37#ibcon#end of sib2, iclass 23, count 2 2006.173.12:11:24.37#ibcon#*after write, iclass 23, count 2 2006.173.12:11:24.37#ibcon#*before return 0, iclass 23, count 2 2006.173.12:11:24.37#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.12:11:24.37#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.12:11:24.37#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.12:11:24.37#ibcon#ireg 7 cls_cnt 0 2006.173.12:11:24.37#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.12:11:24.49#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.12:11:24.49#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.12:11:24.49#ibcon#enter wrdev, iclass 23, count 0 2006.173.12:11:24.49#ibcon#first serial, iclass 23, count 0 2006.173.12:11:24.49#ibcon#enter sib2, iclass 23, count 0 2006.173.12:11:24.49#ibcon#flushed, iclass 23, count 0 2006.173.12:11:24.49#ibcon#about to write, iclass 23, count 0 2006.173.12:11:24.49#ibcon#wrote, iclass 23, count 0 2006.173.12:11:24.49#ibcon#about to read 3, iclass 23, count 0 2006.173.12:11:24.51#ibcon#read 3, iclass 23, count 0 2006.173.12:11:24.51#ibcon#about to read 4, iclass 23, count 0 2006.173.12:11:24.51#ibcon#read 4, iclass 23, count 0 2006.173.12:11:24.51#ibcon#about to read 5, iclass 23, count 0 2006.173.12:11:24.51#ibcon#read 5, iclass 23, count 0 2006.173.12:11:24.51#ibcon#about to read 6, iclass 23, count 0 2006.173.12:11:24.51#ibcon#read 6, iclass 23, count 0 2006.173.12:11:24.51#ibcon#end of sib2, iclass 23, count 0 2006.173.12:11:24.51#ibcon#*mode == 0, iclass 23, count 0 2006.173.12:11:24.51#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.12:11:24.51#ibcon#[27=USB\r\n] 2006.173.12:11:24.51#ibcon#*before write, iclass 23, count 0 2006.173.12:11:24.51#ibcon#enter sib2, iclass 23, count 0 2006.173.12:11:24.51#ibcon#flushed, iclass 23, count 0 2006.173.12:11:24.51#ibcon#about to write, iclass 23, count 0 2006.173.12:11:24.51#ibcon#wrote, iclass 23, count 0 2006.173.12:11:24.51#ibcon#about to read 3, iclass 23, count 0 2006.173.12:11:24.54#ibcon#read 3, iclass 23, count 0 2006.173.12:11:24.54#ibcon#about to read 4, iclass 23, count 0 2006.173.12:11:24.54#ibcon#read 4, iclass 23, count 0 2006.173.12:11:24.54#ibcon#about to read 5, iclass 23, count 0 2006.173.12:11:24.54#ibcon#read 5, iclass 23, count 0 2006.173.12:11:24.54#ibcon#about to read 6, iclass 23, count 0 2006.173.12:11:24.54#ibcon#read 6, iclass 23, count 0 2006.173.12:11:24.54#ibcon#end of sib2, iclass 23, count 0 2006.173.12:11:24.54#ibcon#*after write, iclass 23, count 0 2006.173.12:11:24.54#ibcon#*before return 0, iclass 23, count 0 2006.173.12:11:24.54#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.12:11:24.54#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.12:11:24.54#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.12:11:24.54#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.12:11:24.54$vck44/vblo=3,649.99 2006.173.12:11:24.54#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.12:11:24.54#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.12:11:24.54#ibcon#ireg 17 cls_cnt 0 2006.173.12:11:24.54#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.12:11:24.54#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.12:11:24.54#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.12:11:24.54#ibcon#enter wrdev, iclass 25, count 0 2006.173.12:11:24.54#ibcon#first serial, iclass 25, count 0 2006.173.12:11:24.54#ibcon#enter sib2, iclass 25, count 0 2006.173.12:11:24.54#ibcon#flushed, iclass 25, count 0 2006.173.12:11:24.54#ibcon#about to write, iclass 25, count 0 2006.173.12:11:24.54#ibcon#wrote, iclass 25, count 0 2006.173.12:11:24.54#ibcon#about to read 3, iclass 25, count 0 2006.173.12:11:24.56#ibcon#read 3, iclass 25, count 0 2006.173.12:11:24.56#ibcon#about to read 4, iclass 25, count 0 2006.173.12:11:24.56#ibcon#read 4, iclass 25, count 0 2006.173.12:11:24.56#ibcon#about to read 5, iclass 25, count 0 2006.173.12:11:24.56#ibcon#read 5, iclass 25, count 0 2006.173.12:11:24.56#ibcon#about to read 6, iclass 25, count 0 2006.173.12:11:24.56#ibcon#read 6, iclass 25, count 0 2006.173.12:11:24.56#ibcon#end of sib2, iclass 25, count 0 2006.173.12:11:24.56#ibcon#*mode == 0, iclass 25, count 0 2006.173.12:11:24.56#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.12:11:24.56#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.12:11:24.56#ibcon#*before write, iclass 25, count 0 2006.173.12:11:24.56#ibcon#enter sib2, iclass 25, count 0 2006.173.12:11:24.56#ibcon#flushed, iclass 25, count 0 2006.173.12:11:24.56#ibcon#about to write, iclass 25, count 0 2006.173.12:11:24.56#ibcon#wrote, iclass 25, count 0 2006.173.12:11:24.56#ibcon#about to read 3, iclass 25, count 0 2006.173.12:11:24.60#ibcon#read 3, iclass 25, count 0 2006.173.12:11:24.60#ibcon#about to read 4, iclass 25, count 0 2006.173.12:11:24.60#ibcon#read 4, iclass 25, count 0 2006.173.12:11:24.60#ibcon#about to read 5, iclass 25, count 0 2006.173.12:11:24.60#ibcon#read 5, iclass 25, count 0 2006.173.12:11:24.60#ibcon#about to read 6, iclass 25, count 0 2006.173.12:11:24.60#ibcon#read 6, iclass 25, count 0 2006.173.12:11:24.60#ibcon#end of sib2, iclass 25, count 0 2006.173.12:11:24.60#ibcon#*after write, iclass 25, count 0 2006.173.12:11:24.60#ibcon#*before return 0, iclass 25, count 0 2006.173.12:11:24.60#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.12:11:24.60#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.12:11:24.60#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.12:11:24.60#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.12:11:24.60$vck44/vb=3,4 2006.173.12:11:24.60#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.12:11:24.60#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.12:11:24.60#ibcon#ireg 11 cls_cnt 2 2006.173.12:11:24.60#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.12:11:24.66#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.12:11:24.66#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.12:11:24.66#ibcon#enter wrdev, iclass 27, count 2 2006.173.12:11:24.66#ibcon#first serial, iclass 27, count 2 2006.173.12:11:24.66#ibcon#enter sib2, iclass 27, count 2 2006.173.12:11:24.66#ibcon#flushed, iclass 27, count 2 2006.173.12:11:24.66#ibcon#about to write, iclass 27, count 2 2006.173.12:11:24.66#ibcon#wrote, iclass 27, count 2 2006.173.12:11:24.66#ibcon#about to read 3, iclass 27, count 2 2006.173.12:11:24.68#ibcon#read 3, iclass 27, count 2 2006.173.12:11:24.68#ibcon#about to read 4, iclass 27, count 2 2006.173.12:11:24.68#ibcon#read 4, iclass 27, count 2 2006.173.12:11:24.68#ibcon#about to read 5, iclass 27, count 2 2006.173.12:11:24.68#ibcon#read 5, iclass 27, count 2 2006.173.12:11:24.68#ibcon#about to read 6, iclass 27, count 2 2006.173.12:11:24.68#ibcon#read 6, iclass 27, count 2 2006.173.12:11:24.68#ibcon#end of sib2, iclass 27, count 2 2006.173.12:11:24.68#ibcon#*mode == 0, iclass 27, count 2 2006.173.12:11:24.68#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.12:11:24.68#ibcon#[27=AT03-04\r\n] 2006.173.12:11:24.68#ibcon#*before write, iclass 27, count 2 2006.173.12:11:24.68#ibcon#enter sib2, iclass 27, count 2 2006.173.12:11:24.68#ibcon#flushed, iclass 27, count 2 2006.173.12:11:24.68#ibcon#about to write, iclass 27, count 2 2006.173.12:11:24.68#ibcon#wrote, iclass 27, count 2 2006.173.12:11:24.68#ibcon#about to read 3, iclass 27, count 2 2006.173.12:11:24.71#ibcon#read 3, iclass 27, count 2 2006.173.12:11:24.71#ibcon#about to read 4, iclass 27, count 2 2006.173.12:11:24.71#ibcon#read 4, iclass 27, count 2 2006.173.12:11:24.71#ibcon#about to read 5, iclass 27, count 2 2006.173.12:11:24.71#ibcon#read 5, iclass 27, count 2 2006.173.12:11:24.71#ibcon#about to read 6, iclass 27, count 2 2006.173.12:11:24.71#ibcon#read 6, iclass 27, count 2 2006.173.12:11:24.71#ibcon#end of sib2, iclass 27, count 2 2006.173.12:11:24.71#ibcon#*after write, iclass 27, count 2 2006.173.12:11:24.71#ibcon#*before return 0, iclass 27, count 2 2006.173.12:11:24.71#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.12:11:24.71#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.12:11:24.71#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.12:11:24.71#ibcon#ireg 7 cls_cnt 0 2006.173.12:11:24.71#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.12:11:24.83#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.12:11:24.83#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.12:11:24.83#ibcon#enter wrdev, iclass 27, count 0 2006.173.12:11:24.83#ibcon#first serial, iclass 27, count 0 2006.173.12:11:24.83#ibcon#enter sib2, iclass 27, count 0 2006.173.12:11:24.83#ibcon#flushed, iclass 27, count 0 2006.173.12:11:24.83#ibcon#about to write, iclass 27, count 0 2006.173.12:11:24.83#ibcon#wrote, iclass 27, count 0 2006.173.12:11:24.83#ibcon#about to read 3, iclass 27, count 0 2006.173.12:11:24.85#ibcon#read 3, iclass 27, count 0 2006.173.12:11:24.85#ibcon#about to read 4, iclass 27, count 0 2006.173.12:11:24.85#ibcon#read 4, iclass 27, count 0 2006.173.12:11:24.85#ibcon#about to read 5, iclass 27, count 0 2006.173.12:11:24.85#ibcon#read 5, iclass 27, count 0 2006.173.12:11:24.85#ibcon#about to read 6, iclass 27, count 0 2006.173.12:11:24.85#ibcon#read 6, iclass 27, count 0 2006.173.12:11:24.85#ibcon#end of sib2, iclass 27, count 0 2006.173.12:11:24.85#ibcon#*mode == 0, iclass 27, count 0 2006.173.12:11:24.85#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.12:11:24.85#ibcon#[27=USB\r\n] 2006.173.12:11:24.85#ibcon#*before write, iclass 27, count 0 2006.173.12:11:24.85#ibcon#enter sib2, iclass 27, count 0 2006.173.12:11:24.85#ibcon#flushed, iclass 27, count 0 2006.173.12:11:24.85#ibcon#about to write, iclass 27, count 0 2006.173.12:11:24.85#ibcon#wrote, iclass 27, count 0 2006.173.12:11:24.85#ibcon#about to read 3, iclass 27, count 0 2006.173.12:11:24.88#ibcon#read 3, iclass 27, count 0 2006.173.12:11:24.88#ibcon#about to read 4, iclass 27, count 0 2006.173.12:11:24.88#ibcon#read 4, iclass 27, count 0 2006.173.12:11:24.88#ibcon#about to read 5, iclass 27, count 0 2006.173.12:11:24.88#ibcon#read 5, iclass 27, count 0 2006.173.12:11:24.88#ibcon#about to read 6, iclass 27, count 0 2006.173.12:11:24.88#ibcon#read 6, iclass 27, count 0 2006.173.12:11:24.88#ibcon#end of sib2, iclass 27, count 0 2006.173.12:11:24.88#ibcon#*after write, iclass 27, count 0 2006.173.12:11:24.88#ibcon#*before return 0, iclass 27, count 0 2006.173.12:11:24.88#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.12:11:24.88#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.12:11:24.88#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.12:11:24.88#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.12:11:24.88$vck44/vblo=4,679.99 2006.173.12:11:24.88#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.12:11:24.88#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.12:11:24.88#ibcon#ireg 17 cls_cnt 0 2006.173.12:11:24.88#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.12:11:24.88#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.12:11:24.88#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.12:11:24.88#ibcon#enter wrdev, iclass 29, count 0 2006.173.12:11:24.88#ibcon#first serial, iclass 29, count 0 2006.173.12:11:24.88#ibcon#enter sib2, iclass 29, count 0 2006.173.12:11:24.88#ibcon#flushed, iclass 29, count 0 2006.173.12:11:24.88#ibcon#about to write, iclass 29, count 0 2006.173.12:11:24.88#ibcon#wrote, iclass 29, count 0 2006.173.12:11:24.88#ibcon#about to read 3, iclass 29, count 0 2006.173.12:11:24.90#ibcon#read 3, iclass 29, count 0 2006.173.12:11:24.90#ibcon#about to read 4, iclass 29, count 0 2006.173.12:11:24.90#ibcon#read 4, iclass 29, count 0 2006.173.12:11:24.90#ibcon#about to read 5, iclass 29, count 0 2006.173.12:11:24.90#ibcon#read 5, iclass 29, count 0 2006.173.12:11:24.90#ibcon#about to read 6, iclass 29, count 0 2006.173.12:11:24.90#ibcon#read 6, iclass 29, count 0 2006.173.12:11:24.90#ibcon#end of sib2, iclass 29, count 0 2006.173.12:11:24.90#ibcon#*mode == 0, iclass 29, count 0 2006.173.12:11:24.90#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.12:11:24.90#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.12:11:24.90#ibcon#*before write, iclass 29, count 0 2006.173.12:11:24.90#ibcon#enter sib2, iclass 29, count 0 2006.173.12:11:24.90#ibcon#flushed, iclass 29, count 0 2006.173.12:11:24.90#ibcon#about to write, iclass 29, count 0 2006.173.12:11:24.90#ibcon#wrote, iclass 29, count 0 2006.173.12:11:24.90#ibcon#about to read 3, iclass 29, count 0 2006.173.12:11:24.94#ibcon#read 3, iclass 29, count 0 2006.173.12:11:24.94#ibcon#about to read 4, iclass 29, count 0 2006.173.12:11:24.94#ibcon#read 4, iclass 29, count 0 2006.173.12:11:24.94#ibcon#about to read 5, iclass 29, count 0 2006.173.12:11:24.94#ibcon#read 5, iclass 29, count 0 2006.173.12:11:24.94#ibcon#about to read 6, iclass 29, count 0 2006.173.12:11:24.94#ibcon#read 6, iclass 29, count 0 2006.173.12:11:24.94#ibcon#end of sib2, iclass 29, count 0 2006.173.12:11:24.94#ibcon#*after write, iclass 29, count 0 2006.173.12:11:24.94#ibcon#*before return 0, iclass 29, count 0 2006.173.12:11:24.94#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.12:11:24.94#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.12:11:24.94#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.12:11:24.94#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.12:11:24.94$vck44/vb=4,4 2006.173.12:11:24.94#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.12:11:24.94#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.12:11:24.94#ibcon#ireg 11 cls_cnt 2 2006.173.12:11:24.94#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.12:11:25.00#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.12:11:25.00#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.12:11:25.00#ibcon#enter wrdev, iclass 31, count 2 2006.173.12:11:25.00#ibcon#first serial, iclass 31, count 2 2006.173.12:11:25.00#ibcon#enter sib2, iclass 31, count 2 2006.173.12:11:25.00#ibcon#flushed, iclass 31, count 2 2006.173.12:11:25.00#ibcon#about to write, iclass 31, count 2 2006.173.12:11:25.00#ibcon#wrote, iclass 31, count 2 2006.173.12:11:25.00#ibcon#about to read 3, iclass 31, count 2 2006.173.12:11:25.02#ibcon#read 3, iclass 31, count 2 2006.173.12:11:25.02#ibcon#about to read 4, iclass 31, count 2 2006.173.12:11:25.02#ibcon#read 4, iclass 31, count 2 2006.173.12:11:25.02#ibcon#about to read 5, iclass 31, count 2 2006.173.12:11:25.02#ibcon#read 5, iclass 31, count 2 2006.173.12:11:25.02#ibcon#about to read 6, iclass 31, count 2 2006.173.12:11:25.02#ibcon#read 6, iclass 31, count 2 2006.173.12:11:25.02#ibcon#end of sib2, iclass 31, count 2 2006.173.12:11:25.02#ibcon#*mode == 0, iclass 31, count 2 2006.173.12:11:25.02#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.12:11:25.02#ibcon#[27=AT04-04\r\n] 2006.173.12:11:25.02#ibcon#*before write, iclass 31, count 2 2006.173.12:11:25.02#ibcon#enter sib2, iclass 31, count 2 2006.173.12:11:25.02#ibcon#flushed, iclass 31, count 2 2006.173.12:11:25.02#ibcon#about to write, iclass 31, count 2 2006.173.12:11:25.02#ibcon#wrote, iclass 31, count 2 2006.173.12:11:25.02#ibcon#about to read 3, iclass 31, count 2 2006.173.12:11:25.05#ibcon#read 3, iclass 31, count 2 2006.173.12:11:25.05#ibcon#about to read 4, iclass 31, count 2 2006.173.12:11:25.05#ibcon#read 4, iclass 31, count 2 2006.173.12:11:25.05#ibcon#about to read 5, iclass 31, count 2 2006.173.12:11:25.05#ibcon#read 5, iclass 31, count 2 2006.173.12:11:25.05#ibcon#about to read 6, iclass 31, count 2 2006.173.12:11:25.05#ibcon#read 6, iclass 31, count 2 2006.173.12:11:25.05#ibcon#end of sib2, iclass 31, count 2 2006.173.12:11:25.05#ibcon#*after write, iclass 31, count 2 2006.173.12:11:25.05#ibcon#*before return 0, iclass 31, count 2 2006.173.12:11:25.05#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.12:11:25.05#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.12:11:25.05#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.12:11:25.05#ibcon#ireg 7 cls_cnt 0 2006.173.12:11:25.05#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.12:11:25.17#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.12:11:25.17#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.12:11:25.17#ibcon#enter wrdev, iclass 31, count 0 2006.173.12:11:25.17#ibcon#first serial, iclass 31, count 0 2006.173.12:11:25.17#ibcon#enter sib2, iclass 31, count 0 2006.173.12:11:25.17#ibcon#flushed, iclass 31, count 0 2006.173.12:11:25.17#ibcon#about to write, iclass 31, count 0 2006.173.12:11:25.17#ibcon#wrote, iclass 31, count 0 2006.173.12:11:25.17#ibcon#about to read 3, iclass 31, count 0 2006.173.12:11:25.19#ibcon#read 3, iclass 31, count 0 2006.173.12:11:25.19#ibcon#about to read 4, iclass 31, count 0 2006.173.12:11:25.19#ibcon#read 4, iclass 31, count 0 2006.173.12:11:25.19#ibcon#about to read 5, iclass 31, count 0 2006.173.12:11:25.19#ibcon#read 5, iclass 31, count 0 2006.173.12:11:25.19#ibcon#about to read 6, iclass 31, count 0 2006.173.12:11:25.19#ibcon#read 6, iclass 31, count 0 2006.173.12:11:25.19#ibcon#end of sib2, iclass 31, count 0 2006.173.12:11:25.19#ibcon#*mode == 0, iclass 31, count 0 2006.173.12:11:25.19#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.12:11:25.19#ibcon#[27=USB\r\n] 2006.173.12:11:25.19#ibcon#*before write, iclass 31, count 0 2006.173.12:11:25.19#ibcon#enter sib2, iclass 31, count 0 2006.173.12:11:25.19#ibcon#flushed, iclass 31, count 0 2006.173.12:11:25.19#ibcon#about to write, iclass 31, count 0 2006.173.12:11:25.19#ibcon#wrote, iclass 31, count 0 2006.173.12:11:25.19#ibcon#about to read 3, iclass 31, count 0 2006.173.12:11:25.22#ibcon#read 3, iclass 31, count 0 2006.173.12:11:25.22#ibcon#about to read 4, iclass 31, count 0 2006.173.12:11:25.22#ibcon#read 4, iclass 31, count 0 2006.173.12:11:25.22#ibcon#about to read 5, iclass 31, count 0 2006.173.12:11:25.22#ibcon#read 5, iclass 31, count 0 2006.173.12:11:25.22#ibcon#about to read 6, iclass 31, count 0 2006.173.12:11:25.22#ibcon#read 6, iclass 31, count 0 2006.173.12:11:25.22#ibcon#end of sib2, iclass 31, count 0 2006.173.12:11:25.22#ibcon#*after write, iclass 31, count 0 2006.173.12:11:25.22#ibcon#*before return 0, iclass 31, count 0 2006.173.12:11:25.22#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.12:11:25.22#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.12:11:25.22#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.12:11:25.22#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.12:11:25.22$vck44/vblo=5,709.99 2006.173.12:11:25.22#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.12:11:25.22#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.12:11:25.22#ibcon#ireg 17 cls_cnt 0 2006.173.12:11:25.22#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.12:11:25.22#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.12:11:25.22#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.12:11:25.22#ibcon#enter wrdev, iclass 33, count 0 2006.173.12:11:25.22#ibcon#first serial, iclass 33, count 0 2006.173.12:11:25.22#ibcon#enter sib2, iclass 33, count 0 2006.173.12:11:25.22#ibcon#flushed, iclass 33, count 0 2006.173.12:11:25.22#ibcon#about to write, iclass 33, count 0 2006.173.12:11:25.22#ibcon#wrote, iclass 33, count 0 2006.173.12:11:25.22#ibcon#about to read 3, iclass 33, count 0 2006.173.12:11:25.24#ibcon#read 3, iclass 33, count 0 2006.173.12:11:25.24#ibcon#about to read 4, iclass 33, count 0 2006.173.12:11:25.24#ibcon#read 4, iclass 33, count 0 2006.173.12:11:25.24#ibcon#about to read 5, iclass 33, count 0 2006.173.12:11:25.24#ibcon#read 5, iclass 33, count 0 2006.173.12:11:25.24#ibcon#about to read 6, iclass 33, count 0 2006.173.12:11:25.24#ibcon#read 6, iclass 33, count 0 2006.173.12:11:25.24#ibcon#end of sib2, iclass 33, count 0 2006.173.12:11:25.24#ibcon#*mode == 0, iclass 33, count 0 2006.173.12:11:25.24#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.12:11:25.24#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.12:11:25.24#ibcon#*before write, iclass 33, count 0 2006.173.12:11:25.24#ibcon#enter sib2, iclass 33, count 0 2006.173.12:11:25.24#ibcon#flushed, iclass 33, count 0 2006.173.12:11:25.24#ibcon#about to write, iclass 33, count 0 2006.173.12:11:25.24#ibcon#wrote, iclass 33, count 0 2006.173.12:11:25.24#ibcon#about to read 3, iclass 33, count 0 2006.173.12:11:25.28#ibcon#read 3, iclass 33, count 0 2006.173.12:11:25.28#ibcon#about to read 4, iclass 33, count 0 2006.173.12:11:25.28#ibcon#read 4, iclass 33, count 0 2006.173.12:11:25.28#ibcon#about to read 5, iclass 33, count 0 2006.173.12:11:25.28#ibcon#read 5, iclass 33, count 0 2006.173.12:11:25.28#ibcon#about to read 6, iclass 33, count 0 2006.173.12:11:25.28#ibcon#read 6, iclass 33, count 0 2006.173.12:11:25.28#ibcon#end of sib2, iclass 33, count 0 2006.173.12:11:25.28#ibcon#*after write, iclass 33, count 0 2006.173.12:11:25.28#ibcon#*before return 0, iclass 33, count 0 2006.173.12:11:25.28#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.12:11:25.28#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.12:11:25.28#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.12:11:25.28#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.12:11:25.28$vck44/vb=5,4 2006.173.12:11:25.28#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.12:11:25.28#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.12:11:25.28#ibcon#ireg 11 cls_cnt 2 2006.173.12:11:25.28#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.12:11:25.34#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.12:11:25.34#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.12:11:25.34#ibcon#enter wrdev, iclass 35, count 2 2006.173.12:11:25.34#ibcon#first serial, iclass 35, count 2 2006.173.12:11:25.34#ibcon#enter sib2, iclass 35, count 2 2006.173.12:11:25.34#ibcon#flushed, iclass 35, count 2 2006.173.12:11:25.34#ibcon#about to write, iclass 35, count 2 2006.173.12:11:25.34#ibcon#wrote, iclass 35, count 2 2006.173.12:11:25.34#ibcon#about to read 3, iclass 35, count 2 2006.173.12:11:25.36#ibcon#read 3, iclass 35, count 2 2006.173.12:11:25.36#ibcon#about to read 4, iclass 35, count 2 2006.173.12:11:25.36#ibcon#read 4, iclass 35, count 2 2006.173.12:11:25.36#ibcon#about to read 5, iclass 35, count 2 2006.173.12:11:25.36#ibcon#read 5, iclass 35, count 2 2006.173.12:11:25.36#ibcon#about to read 6, iclass 35, count 2 2006.173.12:11:25.36#ibcon#read 6, iclass 35, count 2 2006.173.12:11:25.36#ibcon#end of sib2, iclass 35, count 2 2006.173.12:11:25.36#ibcon#*mode == 0, iclass 35, count 2 2006.173.12:11:25.36#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.12:11:25.36#ibcon#[27=AT05-04\r\n] 2006.173.12:11:25.36#ibcon#*before write, iclass 35, count 2 2006.173.12:11:25.36#ibcon#enter sib2, iclass 35, count 2 2006.173.12:11:25.36#ibcon#flushed, iclass 35, count 2 2006.173.12:11:25.36#ibcon#about to write, iclass 35, count 2 2006.173.12:11:25.36#ibcon#wrote, iclass 35, count 2 2006.173.12:11:25.36#ibcon#about to read 3, iclass 35, count 2 2006.173.12:11:25.39#ibcon#read 3, iclass 35, count 2 2006.173.12:11:25.39#ibcon#about to read 4, iclass 35, count 2 2006.173.12:11:25.39#ibcon#read 4, iclass 35, count 2 2006.173.12:11:25.39#ibcon#about to read 5, iclass 35, count 2 2006.173.12:11:25.39#ibcon#read 5, iclass 35, count 2 2006.173.12:11:25.39#ibcon#about to read 6, iclass 35, count 2 2006.173.12:11:25.39#ibcon#read 6, iclass 35, count 2 2006.173.12:11:25.39#ibcon#end of sib2, iclass 35, count 2 2006.173.12:11:25.39#ibcon#*after write, iclass 35, count 2 2006.173.12:11:25.39#ibcon#*before return 0, iclass 35, count 2 2006.173.12:11:25.39#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.12:11:25.39#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.12:11:25.39#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.12:11:25.39#ibcon#ireg 7 cls_cnt 0 2006.173.12:11:25.39#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.12:11:25.51#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.12:11:25.51#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.12:11:25.51#ibcon#enter wrdev, iclass 35, count 0 2006.173.12:11:25.51#ibcon#first serial, iclass 35, count 0 2006.173.12:11:25.51#ibcon#enter sib2, iclass 35, count 0 2006.173.12:11:25.51#ibcon#flushed, iclass 35, count 0 2006.173.12:11:25.51#ibcon#about to write, iclass 35, count 0 2006.173.12:11:25.51#ibcon#wrote, iclass 35, count 0 2006.173.12:11:25.51#ibcon#about to read 3, iclass 35, count 0 2006.173.12:11:25.53#ibcon#read 3, iclass 35, count 0 2006.173.12:11:25.53#ibcon#about to read 4, iclass 35, count 0 2006.173.12:11:25.53#ibcon#read 4, iclass 35, count 0 2006.173.12:11:25.53#ibcon#about to read 5, iclass 35, count 0 2006.173.12:11:25.53#ibcon#read 5, iclass 35, count 0 2006.173.12:11:25.53#ibcon#about to read 6, iclass 35, count 0 2006.173.12:11:25.53#ibcon#read 6, iclass 35, count 0 2006.173.12:11:25.53#ibcon#end of sib2, iclass 35, count 0 2006.173.12:11:25.53#ibcon#*mode == 0, iclass 35, count 0 2006.173.12:11:25.53#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.12:11:25.53#ibcon#[27=USB\r\n] 2006.173.12:11:25.53#ibcon#*before write, iclass 35, count 0 2006.173.12:11:25.53#ibcon#enter sib2, iclass 35, count 0 2006.173.12:11:25.53#ibcon#flushed, iclass 35, count 0 2006.173.12:11:25.53#ibcon#about to write, iclass 35, count 0 2006.173.12:11:25.53#ibcon#wrote, iclass 35, count 0 2006.173.12:11:25.53#ibcon#about to read 3, iclass 35, count 0 2006.173.12:11:25.56#ibcon#read 3, iclass 35, count 0 2006.173.12:11:25.56#ibcon#about to read 4, iclass 35, count 0 2006.173.12:11:25.56#ibcon#read 4, iclass 35, count 0 2006.173.12:11:25.56#ibcon#about to read 5, iclass 35, count 0 2006.173.12:11:25.56#ibcon#read 5, iclass 35, count 0 2006.173.12:11:25.56#ibcon#about to read 6, iclass 35, count 0 2006.173.12:11:25.56#ibcon#read 6, iclass 35, count 0 2006.173.12:11:25.56#ibcon#end of sib2, iclass 35, count 0 2006.173.12:11:25.56#ibcon#*after write, iclass 35, count 0 2006.173.12:11:25.56#ibcon#*before return 0, iclass 35, count 0 2006.173.12:11:25.56#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.12:11:25.56#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.12:11:25.56#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.12:11:25.56#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.12:11:25.56$vck44/vblo=6,719.99 2006.173.12:11:25.56#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.12:11:25.56#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.12:11:25.56#ibcon#ireg 17 cls_cnt 0 2006.173.12:11:25.56#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.12:11:25.56#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.12:11:25.56#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.12:11:25.56#ibcon#enter wrdev, iclass 37, count 0 2006.173.12:11:25.56#ibcon#first serial, iclass 37, count 0 2006.173.12:11:25.56#ibcon#enter sib2, iclass 37, count 0 2006.173.12:11:25.56#ibcon#flushed, iclass 37, count 0 2006.173.12:11:25.56#ibcon#about to write, iclass 37, count 0 2006.173.12:11:25.56#ibcon#wrote, iclass 37, count 0 2006.173.12:11:25.56#ibcon#about to read 3, iclass 37, count 0 2006.173.12:11:25.58#ibcon#read 3, iclass 37, count 0 2006.173.12:11:25.58#ibcon#about to read 4, iclass 37, count 0 2006.173.12:11:25.58#ibcon#read 4, iclass 37, count 0 2006.173.12:11:25.58#ibcon#about to read 5, iclass 37, count 0 2006.173.12:11:25.58#ibcon#read 5, iclass 37, count 0 2006.173.12:11:25.58#ibcon#about to read 6, iclass 37, count 0 2006.173.12:11:25.58#ibcon#read 6, iclass 37, count 0 2006.173.12:11:25.58#ibcon#end of sib2, iclass 37, count 0 2006.173.12:11:25.58#ibcon#*mode == 0, iclass 37, count 0 2006.173.12:11:25.58#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.12:11:25.58#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.12:11:25.58#ibcon#*before write, iclass 37, count 0 2006.173.12:11:25.58#ibcon#enter sib2, iclass 37, count 0 2006.173.12:11:25.58#ibcon#flushed, iclass 37, count 0 2006.173.12:11:25.58#ibcon#about to write, iclass 37, count 0 2006.173.12:11:25.58#ibcon#wrote, iclass 37, count 0 2006.173.12:11:25.58#ibcon#about to read 3, iclass 37, count 0 2006.173.12:11:25.62#ibcon#read 3, iclass 37, count 0 2006.173.12:11:25.62#ibcon#about to read 4, iclass 37, count 0 2006.173.12:11:25.62#ibcon#read 4, iclass 37, count 0 2006.173.12:11:25.62#ibcon#about to read 5, iclass 37, count 0 2006.173.12:11:25.62#ibcon#read 5, iclass 37, count 0 2006.173.12:11:25.62#ibcon#about to read 6, iclass 37, count 0 2006.173.12:11:25.62#ibcon#read 6, iclass 37, count 0 2006.173.12:11:25.62#ibcon#end of sib2, iclass 37, count 0 2006.173.12:11:25.62#ibcon#*after write, iclass 37, count 0 2006.173.12:11:25.62#ibcon#*before return 0, iclass 37, count 0 2006.173.12:11:25.62#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.12:11:25.62#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.12:11:25.62#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.12:11:25.62#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.12:11:25.62$vck44/vb=6,4 2006.173.12:11:25.62#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.12:11:25.62#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.12:11:25.62#ibcon#ireg 11 cls_cnt 2 2006.173.12:11:25.62#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.12:11:25.68#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.12:11:25.68#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.12:11:25.68#ibcon#enter wrdev, iclass 39, count 2 2006.173.12:11:25.68#ibcon#first serial, iclass 39, count 2 2006.173.12:11:25.68#ibcon#enter sib2, iclass 39, count 2 2006.173.12:11:25.68#ibcon#flushed, iclass 39, count 2 2006.173.12:11:25.68#ibcon#about to write, iclass 39, count 2 2006.173.12:11:25.68#ibcon#wrote, iclass 39, count 2 2006.173.12:11:25.68#ibcon#about to read 3, iclass 39, count 2 2006.173.12:11:25.70#ibcon#read 3, iclass 39, count 2 2006.173.12:11:25.70#ibcon#about to read 4, iclass 39, count 2 2006.173.12:11:25.70#ibcon#read 4, iclass 39, count 2 2006.173.12:11:25.70#ibcon#about to read 5, iclass 39, count 2 2006.173.12:11:25.70#ibcon#read 5, iclass 39, count 2 2006.173.12:11:25.70#ibcon#about to read 6, iclass 39, count 2 2006.173.12:11:25.70#ibcon#read 6, iclass 39, count 2 2006.173.12:11:25.70#ibcon#end of sib2, iclass 39, count 2 2006.173.12:11:25.70#ibcon#*mode == 0, iclass 39, count 2 2006.173.12:11:25.70#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.12:11:25.70#ibcon#[27=AT06-04\r\n] 2006.173.12:11:25.70#ibcon#*before write, iclass 39, count 2 2006.173.12:11:25.70#ibcon#enter sib2, iclass 39, count 2 2006.173.12:11:25.70#ibcon#flushed, iclass 39, count 2 2006.173.12:11:25.70#ibcon#about to write, iclass 39, count 2 2006.173.12:11:25.70#ibcon#wrote, iclass 39, count 2 2006.173.12:11:25.70#ibcon#about to read 3, iclass 39, count 2 2006.173.12:11:25.73#ibcon#read 3, iclass 39, count 2 2006.173.12:11:25.73#ibcon#about to read 4, iclass 39, count 2 2006.173.12:11:25.73#ibcon#read 4, iclass 39, count 2 2006.173.12:11:25.73#ibcon#about to read 5, iclass 39, count 2 2006.173.12:11:25.73#ibcon#read 5, iclass 39, count 2 2006.173.12:11:25.73#ibcon#about to read 6, iclass 39, count 2 2006.173.12:11:25.73#ibcon#read 6, iclass 39, count 2 2006.173.12:11:25.73#ibcon#end of sib2, iclass 39, count 2 2006.173.12:11:25.73#ibcon#*after write, iclass 39, count 2 2006.173.12:11:25.73#ibcon#*before return 0, iclass 39, count 2 2006.173.12:11:25.73#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.12:11:25.73#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.12:11:25.73#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.12:11:25.73#ibcon#ireg 7 cls_cnt 0 2006.173.12:11:25.73#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.12:11:25.85#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.12:11:25.85#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.12:11:25.85#ibcon#enter wrdev, iclass 39, count 0 2006.173.12:11:25.85#ibcon#first serial, iclass 39, count 0 2006.173.12:11:25.85#ibcon#enter sib2, iclass 39, count 0 2006.173.12:11:25.85#ibcon#flushed, iclass 39, count 0 2006.173.12:11:25.85#ibcon#about to write, iclass 39, count 0 2006.173.12:11:25.85#ibcon#wrote, iclass 39, count 0 2006.173.12:11:25.85#ibcon#about to read 3, iclass 39, count 0 2006.173.12:11:25.87#ibcon#read 3, iclass 39, count 0 2006.173.12:11:25.87#ibcon#about to read 4, iclass 39, count 0 2006.173.12:11:25.87#ibcon#read 4, iclass 39, count 0 2006.173.12:11:25.87#ibcon#about to read 5, iclass 39, count 0 2006.173.12:11:25.87#ibcon#read 5, iclass 39, count 0 2006.173.12:11:25.87#ibcon#about to read 6, iclass 39, count 0 2006.173.12:11:25.87#ibcon#read 6, iclass 39, count 0 2006.173.12:11:25.87#ibcon#end of sib2, iclass 39, count 0 2006.173.12:11:25.87#ibcon#*mode == 0, iclass 39, count 0 2006.173.12:11:25.87#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.12:11:25.87#ibcon#[27=USB\r\n] 2006.173.12:11:25.87#ibcon#*before write, iclass 39, count 0 2006.173.12:11:25.87#ibcon#enter sib2, iclass 39, count 0 2006.173.12:11:25.87#ibcon#flushed, iclass 39, count 0 2006.173.12:11:25.87#ibcon#about to write, iclass 39, count 0 2006.173.12:11:25.87#ibcon#wrote, iclass 39, count 0 2006.173.12:11:25.87#ibcon#about to read 3, iclass 39, count 0 2006.173.12:11:25.90#ibcon#read 3, iclass 39, count 0 2006.173.12:11:25.90#ibcon#about to read 4, iclass 39, count 0 2006.173.12:11:25.90#ibcon#read 4, iclass 39, count 0 2006.173.12:11:25.90#ibcon#about to read 5, iclass 39, count 0 2006.173.12:11:25.90#ibcon#read 5, iclass 39, count 0 2006.173.12:11:25.90#ibcon#about to read 6, iclass 39, count 0 2006.173.12:11:25.90#ibcon#read 6, iclass 39, count 0 2006.173.12:11:25.90#ibcon#end of sib2, iclass 39, count 0 2006.173.12:11:25.90#ibcon#*after write, iclass 39, count 0 2006.173.12:11:25.90#ibcon#*before return 0, iclass 39, count 0 2006.173.12:11:25.90#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.12:11:25.90#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.12:11:25.90#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.12:11:25.90#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.12:11:25.90$vck44/vblo=7,734.99 2006.173.12:11:25.90#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.12:11:25.90#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.12:11:25.90#ibcon#ireg 17 cls_cnt 0 2006.173.12:11:25.90#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.12:11:25.90#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.12:11:25.90#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.12:11:25.90#ibcon#enter wrdev, iclass 3, count 0 2006.173.12:11:25.90#ibcon#first serial, iclass 3, count 0 2006.173.12:11:25.90#ibcon#enter sib2, iclass 3, count 0 2006.173.12:11:25.90#ibcon#flushed, iclass 3, count 0 2006.173.12:11:25.90#ibcon#about to write, iclass 3, count 0 2006.173.12:11:25.90#ibcon#wrote, iclass 3, count 0 2006.173.12:11:25.90#ibcon#about to read 3, iclass 3, count 0 2006.173.12:11:25.92#ibcon#read 3, iclass 3, count 0 2006.173.12:11:25.92#ibcon#about to read 4, iclass 3, count 0 2006.173.12:11:25.92#ibcon#read 4, iclass 3, count 0 2006.173.12:11:25.92#ibcon#about to read 5, iclass 3, count 0 2006.173.12:11:25.92#ibcon#read 5, iclass 3, count 0 2006.173.12:11:25.92#ibcon#about to read 6, iclass 3, count 0 2006.173.12:11:25.92#ibcon#read 6, iclass 3, count 0 2006.173.12:11:25.92#ibcon#end of sib2, iclass 3, count 0 2006.173.12:11:25.92#ibcon#*mode == 0, iclass 3, count 0 2006.173.12:11:25.92#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.12:11:25.92#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.12:11:25.92#ibcon#*before write, iclass 3, count 0 2006.173.12:11:25.92#ibcon#enter sib2, iclass 3, count 0 2006.173.12:11:25.92#ibcon#flushed, iclass 3, count 0 2006.173.12:11:25.92#ibcon#about to write, iclass 3, count 0 2006.173.12:11:25.92#ibcon#wrote, iclass 3, count 0 2006.173.12:11:25.92#ibcon#about to read 3, iclass 3, count 0 2006.173.12:11:25.96#ibcon#read 3, iclass 3, count 0 2006.173.12:11:25.96#ibcon#about to read 4, iclass 3, count 0 2006.173.12:11:25.96#ibcon#read 4, iclass 3, count 0 2006.173.12:11:25.96#ibcon#about to read 5, iclass 3, count 0 2006.173.12:11:25.96#ibcon#read 5, iclass 3, count 0 2006.173.12:11:25.96#ibcon#about to read 6, iclass 3, count 0 2006.173.12:11:25.96#ibcon#read 6, iclass 3, count 0 2006.173.12:11:25.96#ibcon#end of sib2, iclass 3, count 0 2006.173.12:11:25.96#ibcon#*after write, iclass 3, count 0 2006.173.12:11:25.96#ibcon#*before return 0, iclass 3, count 0 2006.173.12:11:25.96#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.12:11:25.96#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.12:11:25.96#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.12:11:25.96#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.12:11:25.96$vck44/vb=7,4 2006.173.12:11:25.96#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.12:11:25.96#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.12:11:25.96#ibcon#ireg 11 cls_cnt 2 2006.173.12:11:25.96#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.12:11:26.02#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.12:11:26.02#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.12:11:26.02#ibcon#enter wrdev, iclass 5, count 2 2006.173.12:11:26.02#ibcon#first serial, iclass 5, count 2 2006.173.12:11:26.02#ibcon#enter sib2, iclass 5, count 2 2006.173.12:11:26.02#ibcon#flushed, iclass 5, count 2 2006.173.12:11:26.02#ibcon#about to write, iclass 5, count 2 2006.173.12:11:26.02#ibcon#wrote, iclass 5, count 2 2006.173.12:11:26.02#ibcon#about to read 3, iclass 5, count 2 2006.173.12:11:26.04#ibcon#read 3, iclass 5, count 2 2006.173.12:11:26.04#ibcon#about to read 4, iclass 5, count 2 2006.173.12:11:26.04#ibcon#read 4, iclass 5, count 2 2006.173.12:11:26.04#ibcon#about to read 5, iclass 5, count 2 2006.173.12:11:26.04#ibcon#read 5, iclass 5, count 2 2006.173.12:11:26.04#ibcon#about to read 6, iclass 5, count 2 2006.173.12:11:26.04#ibcon#read 6, iclass 5, count 2 2006.173.12:11:26.04#ibcon#end of sib2, iclass 5, count 2 2006.173.12:11:26.04#ibcon#*mode == 0, iclass 5, count 2 2006.173.12:11:26.04#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.12:11:26.04#ibcon#[27=AT07-04\r\n] 2006.173.12:11:26.04#ibcon#*before write, iclass 5, count 2 2006.173.12:11:26.04#ibcon#enter sib2, iclass 5, count 2 2006.173.12:11:26.04#ibcon#flushed, iclass 5, count 2 2006.173.12:11:26.04#ibcon#about to write, iclass 5, count 2 2006.173.12:11:26.04#ibcon#wrote, iclass 5, count 2 2006.173.12:11:26.04#ibcon#about to read 3, iclass 5, count 2 2006.173.12:11:26.07#ibcon#read 3, iclass 5, count 2 2006.173.12:11:26.07#ibcon#about to read 4, iclass 5, count 2 2006.173.12:11:26.07#ibcon#read 4, iclass 5, count 2 2006.173.12:11:26.07#ibcon#about to read 5, iclass 5, count 2 2006.173.12:11:26.07#ibcon#read 5, iclass 5, count 2 2006.173.12:11:26.07#ibcon#about to read 6, iclass 5, count 2 2006.173.12:11:26.07#ibcon#read 6, iclass 5, count 2 2006.173.12:11:26.07#ibcon#end of sib2, iclass 5, count 2 2006.173.12:11:26.07#ibcon#*after write, iclass 5, count 2 2006.173.12:11:26.07#ibcon#*before return 0, iclass 5, count 2 2006.173.12:11:26.07#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.12:11:26.07#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.12:11:26.07#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.12:11:26.07#ibcon#ireg 7 cls_cnt 0 2006.173.12:11:26.07#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.12:11:26.19#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.12:11:26.19#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.12:11:26.19#ibcon#enter wrdev, iclass 5, count 0 2006.173.12:11:26.19#ibcon#first serial, iclass 5, count 0 2006.173.12:11:26.19#ibcon#enter sib2, iclass 5, count 0 2006.173.12:11:26.19#ibcon#flushed, iclass 5, count 0 2006.173.12:11:26.19#ibcon#about to write, iclass 5, count 0 2006.173.12:11:26.19#ibcon#wrote, iclass 5, count 0 2006.173.12:11:26.19#ibcon#about to read 3, iclass 5, count 0 2006.173.12:11:26.21#ibcon#read 3, iclass 5, count 0 2006.173.12:11:26.21#ibcon#about to read 4, iclass 5, count 0 2006.173.12:11:26.21#ibcon#read 4, iclass 5, count 0 2006.173.12:11:26.21#ibcon#about to read 5, iclass 5, count 0 2006.173.12:11:26.21#ibcon#read 5, iclass 5, count 0 2006.173.12:11:26.21#ibcon#about to read 6, iclass 5, count 0 2006.173.12:11:26.21#ibcon#read 6, iclass 5, count 0 2006.173.12:11:26.21#ibcon#end of sib2, iclass 5, count 0 2006.173.12:11:26.21#ibcon#*mode == 0, iclass 5, count 0 2006.173.12:11:26.21#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.12:11:26.21#ibcon#[27=USB\r\n] 2006.173.12:11:26.21#ibcon#*before write, iclass 5, count 0 2006.173.12:11:26.21#ibcon#enter sib2, iclass 5, count 0 2006.173.12:11:26.21#ibcon#flushed, iclass 5, count 0 2006.173.12:11:26.21#ibcon#about to write, iclass 5, count 0 2006.173.12:11:26.21#ibcon#wrote, iclass 5, count 0 2006.173.12:11:26.21#ibcon#about to read 3, iclass 5, count 0 2006.173.12:11:26.24#ibcon#read 3, iclass 5, count 0 2006.173.12:11:26.24#ibcon#about to read 4, iclass 5, count 0 2006.173.12:11:26.24#ibcon#read 4, iclass 5, count 0 2006.173.12:11:26.24#ibcon#about to read 5, iclass 5, count 0 2006.173.12:11:26.24#ibcon#read 5, iclass 5, count 0 2006.173.12:11:26.24#ibcon#about to read 6, iclass 5, count 0 2006.173.12:11:26.24#ibcon#read 6, iclass 5, count 0 2006.173.12:11:26.24#ibcon#end of sib2, iclass 5, count 0 2006.173.12:11:26.24#ibcon#*after write, iclass 5, count 0 2006.173.12:11:26.24#ibcon#*before return 0, iclass 5, count 0 2006.173.12:11:26.24#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.12:11:26.24#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.12:11:26.24#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.12:11:26.24#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.12:11:26.24$vck44/vblo=8,744.99 2006.173.12:11:26.24#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.12:11:26.24#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.12:11:26.24#ibcon#ireg 17 cls_cnt 0 2006.173.12:11:26.24#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.12:11:26.24#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.12:11:26.24#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.12:11:26.24#ibcon#enter wrdev, iclass 7, count 0 2006.173.12:11:26.24#ibcon#first serial, iclass 7, count 0 2006.173.12:11:26.24#ibcon#enter sib2, iclass 7, count 0 2006.173.12:11:26.24#ibcon#flushed, iclass 7, count 0 2006.173.12:11:26.24#ibcon#about to write, iclass 7, count 0 2006.173.12:11:26.24#ibcon#wrote, iclass 7, count 0 2006.173.12:11:26.24#ibcon#about to read 3, iclass 7, count 0 2006.173.12:11:26.26#ibcon#read 3, iclass 7, count 0 2006.173.12:11:26.26#ibcon#about to read 4, iclass 7, count 0 2006.173.12:11:26.26#ibcon#read 4, iclass 7, count 0 2006.173.12:11:26.26#ibcon#about to read 5, iclass 7, count 0 2006.173.12:11:26.26#ibcon#read 5, iclass 7, count 0 2006.173.12:11:26.26#ibcon#about to read 6, iclass 7, count 0 2006.173.12:11:26.26#ibcon#read 6, iclass 7, count 0 2006.173.12:11:26.26#ibcon#end of sib2, iclass 7, count 0 2006.173.12:11:26.26#ibcon#*mode == 0, iclass 7, count 0 2006.173.12:11:26.26#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.12:11:26.26#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.12:11:26.26#ibcon#*before write, iclass 7, count 0 2006.173.12:11:26.26#ibcon#enter sib2, iclass 7, count 0 2006.173.12:11:26.26#ibcon#flushed, iclass 7, count 0 2006.173.12:11:26.26#ibcon#about to write, iclass 7, count 0 2006.173.12:11:26.26#ibcon#wrote, iclass 7, count 0 2006.173.12:11:26.26#ibcon#about to read 3, iclass 7, count 0 2006.173.12:11:26.30#ibcon#read 3, iclass 7, count 0 2006.173.12:11:26.30#ibcon#about to read 4, iclass 7, count 0 2006.173.12:11:26.30#ibcon#read 4, iclass 7, count 0 2006.173.12:11:26.30#ibcon#about to read 5, iclass 7, count 0 2006.173.12:11:26.30#ibcon#read 5, iclass 7, count 0 2006.173.12:11:26.30#ibcon#about to read 6, iclass 7, count 0 2006.173.12:11:26.30#ibcon#read 6, iclass 7, count 0 2006.173.12:11:26.30#ibcon#end of sib2, iclass 7, count 0 2006.173.12:11:26.30#ibcon#*after write, iclass 7, count 0 2006.173.12:11:26.30#ibcon#*before return 0, iclass 7, count 0 2006.173.12:11:26.30#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.12:11:26.30#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.12:11:26.30#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.12:11:26.30#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.12:11:26.30$vck44/vb=8,4 2006.173.12:11:26.30#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.12:11:26.30#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.12:11:26.30#ibcon#ireg 11 cls_cnt 2 2006.173.12:11:26.30#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.12:11:26.36#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.12:11:26.36#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.12:11:26.36#ibcon#enter wrdev, iclass 11, count 2 2006.173.12:11:26.36#ibcon#first serial, iclass 11, count 2 2006.173.12:11:26.36#ibcon#enter sib2, iclass 11, count 2 2006.173.12:11:26.36#ibcon#flushed, iclass 11, count 2 2006.173.12:11:26.36#ibcon#about to write, iclass 11, count 2 2006.173.12:11:26.36#ibcon#wrote, iclass 11, count 2 2006.173.12:11:26.36#ibcon#about to read 3, iclass 11, count 2 2006.173.12:11:26.38#ibcon#read 3, iclass 11, count 2 2006.173.12:11:26.38#ibcon#about to read 4, iclass 11, count 2 2006.173.12:11:26.38#ibcon#read 4, iclass 11, count 2 2006.173.12:11:26.38#ibcon#about to read 5, iclass 11, count 2 2006.173.12:11:26.38#ibcon#read 5, iclass 11, count 2 2006.173.12:11:26.38#ibcon#about to read 6, iclass 11, count 2 2006.173.12:11:26.38#ibcon#read 6, iclass 11, count 2 2006.173.12:11:26.38#ibcon#end of sib2, iclass 11, count 2 2006.173.12:11:26.38#ibcon#*mode == 0, iclass 11, count 2 2006.173.12:11:26.38#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.12:11:26.38#ibcon#[27=AT08-04\r\n] 2006.173.12:11:26.38#ibcon#*before write, iclass 11, count 2 2006.173.12:11:26.38#ibcon#enter sib2, iclass 11, count 2 2006.173.12:11:26.38#ibcon#flushed, iclass 11, count 2 2006.173.12:11:26.38#ibcon#about to write, iclass 11, count 2 2006.173.12:11:26.38#ibcon#wrote, iclass 11, count 2 2006.173.12:11:26.38#ibcon#about to read 3, iclass 11, count 2 2006.173.12:11:26.41#ibcon#read 3, iclass 11, count 2 2006.173.12:11:26.41#ibcon#about to read 4, iclass 11, count 2 2006.173.12:11:26.41#ibcon#read 4, iclass 11, count 2 2006.173.12:11:26.41#ibcon#about to read 5, iclass 11, count 2 2006.173.12:11:26.41#ibcon#read 5, iclass 11, count 2 2006.173.12:11:26.41#ibcon#about to read 6, iclass 11, count 2 2006.173.12:11:26.41#ibcon#read 6, iclass 11, count 2 2006.173.12:11:26.41#ibcon#end of sib2, iclass 11, count 2 2006.173.12:11:26.41#ibcon#*after write, iclass 11, count 2 2006.173.12:11:26.41#ibcon#*before return 0, iclass 11, count 2 2006.173.12:11:26.41#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.12:11:26.41#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.12:11:26.41#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.12:11:26.41#ibcon#ireg 7 cls_cnt 0 2006.173.12:11:26.41#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.12:11:26.53#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.12:11:26.53#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.12:11:26.53#ibcon#enter wrdev, iclass 11, count 0 2006.173.12:11:26.53#ibcon#first serial, iclass 11, count 0 2006.173.12:11:26.53#ibcon#enter sib2, iclass 11, count 0 2006.173.12:11:26.53#ibcon#flushed, iclass 11, count 0 2006.173.12:11:26.53#ibcon#about to write, iclass 11, count 0 2006.173.12:11:26.53#ibcon#wrote, iclass 11, count 0 2006.173.12:11:26.53#ibcon#about to read 3, iclass 11, count 0 2006.173.12:11:26.55#ibcon#read 3, iclass 11, count 0 2006.173.12:11:26.55#ibcon#about to read 4, iclass 11, count 0 2006.173.12:11:26.55#ibcon#read 4, iclass 11, count 0 2006.173.12:11:26.55#ibcon#about to read 5, iclass 11, count 0 2006.173.12:11:26.55#ibcon#read 5, iclass 11, count 0 2006.173.12:11:26.55#ibcon#about to read 6, iclass 11, count 0 2006.173.12:11:26.55#ibcon#read 6, iclass 11, count 0 2006.173.12:11:26.55#ibcon#end of sib2, iclass 11, count 0 2006.173.12:11:26.55#ibcon#*mode == 0, iclass 11, count 0 2006.173.12:11:26.55#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.12:11:26.55#ibcon#[27=USB\r\n] 2006.173.12:11:26.55#ibcon#*before write, iclass 11, count 0 2006.173.12:11:26.55#ibcon#enter sib2, iclass 11, count 0 2006.173.12:11:26.55#ibcon#flushed, iclass 11, count 0 2006.173.12:11:26.55#ibcon#about to write, iclass 11, count 0 2006.173.12:11:26.55#ibcon#wrote, iclass 11, count 0 2006.173.12:11:26.55#ibcon#about to read 3, iclass 11, count 0 2006.173.12:11:26.58#ibcon#read 3, iclass 11, count 0 2006.173.12:11:26.58#ibcon#about to read 4, iclass 11, count 0 2006.173.12:11:26.58#ibcon#read 4, iclass 11, count 0 2006.173.12:11:26.58#ibcon#about to read 5, iclass 11, count 0 2006.173.12:11:26.58#ibcon#read 5, iclass 11, count 0 2006.173.12:11:26.58#ibcon#about to read 6, iclass 11, count 0 2006.173.12:11:26.58#ibcon#read 6, iclass 11, count 0 2006.173.12:11:26.58#ibcon#end of sib2, iclass 11, count 0 2006.173.12:11:26.58#ibcon#*after write, iclass 11, count 0 2006.173.12:11:26.58#ibcon#*before return 0, iclass 11, count 0 2006.173.12:11:26.58#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.12:11:26.58#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.12:11:26.58#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.12:11:26.58#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.12:11:26.58$vck44/vabw=wide 2006.173.12:11:26.58#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.12:11:26.58#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.12:11:26.58#ibcon#ireg 8 cls_cnt 0 2006.173.12:11:26.58#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.12:11:26.58#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.12:11:26.58#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.12:11:26.58#ibcon#enter wrdev, iclass 13, count 0 2006.173.12:11:26.58#ibcon#first serial, iclass 13, count 0 2006.173.12:11:26.58#ibcon#enter sib2, iclass 13, count 0 2006.173.12:11:26.58#ibcon#flushed, iclass 13, count 0 2006.173.12:11:26.58#ibcon#about to write, iclass 13, count 0 2006.173.12:11:26.58#ibcon#wrote, iclass 13, count 0 2006.173.12:11:26.58#ibcon#about to read 3, iclass 13, count 0 2006.173.12:11:26.60#ibcon#read 3, iclass 13, count 0 2006.173.12:11:26.60#ibcon#about to read 4, iclass 13, count 0 2006.173.12:11:26.60#ibcon#read 4, iclass 13, count 0 2006.173.12:11:26.60#ibcon#about to read 5, iclass 13, count 0 2006.173.12:11:26.60#ibcon#read 5, iclass 13, count 0 2006.173.12:11:26.60#ibcon#about to read 6, iclass 13, count 0 2006.173.12:11:26.60#ibcon#read 6, iclass 13, count 0 2006.173.12:11:26.60#ibcon#end of sib2, iclass 13, count 0 2006.173.12:11:26.60#ibcon#*mode == 0, iclass 13, count 0 2006.173.12:11:26.60#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.12:11:26.60#ibcon#[25=BW32\r\n] 2006.173.12:11:26.60#ibcon#*before write, iclass 13, count 0 2006.173.12:11:26.60#ibcon#enter sib2, iclass 13, count 0 2006.173.12:11:26.60#ibcon#flushed, iclass 13, count 0 2006.173.12:11:26.60#ibcon#about to write, iclass 13, count 0 2006.173.12:11:26.60#ibcon#wrote, iclass 13, count 0 2006.173.12:11:26.60#ibcon#about to read 3, iclass 13, count 0 2006.173.12:11:26.63#ibcon#read 3, iclass 13, count 0 2006.173.12:11:26.63#ibcon#about to read 4, iclass 13, count 0 2006.173.12:11:26.63#ibcon#read 4, iclass 13, count 0 2006.173.12:11:26.63#ibcon#about to read 5, iclass 13, count 0 2006.173.12:11:26.63#ibcon#read 5, iclass 13, count 0 2006.173.12:11:26.63#ibcon#about to read 6, iclass 13, count 0 2006.173.12:11:26.63#ibcon#read 6, iclass 13, count 0 2006.173.12:11:26.63#ibcon#end of sib2, iclass 13, count 0 2006.173.12:11:26.63#ibcon#*after write, iclass 13, count 0 2006.173.12:11:26.63#ibcon#*before return 0, iclass 13, count 0 2006.173.12:11:26.63#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.12:11:26.63#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.12:11:26.63#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.12:11:26.63#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.12:11:26.63$vck44/vbbw=wide 2006.173.12:11:26.63#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.12:11:26.63#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.12:11:26.63#ibcon#ireg 8 cls_cnt 0 2006.173.12:11:26.63#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.12:11:26.70#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.12:11:26.70#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.12:11:26.70#ibcon#enter wrdev, iclass 15, count 0 2006.173.12:11:26.70#ibcon#first serial, iclass 15, count 0 2006.173.12:11:26.70#ibcon#enter sib2, iclass 15, count 0 2006.173.12:11:26.70#ibcon#flushed, iclass 15, count 0 2006.173.12:11:26.70#ibcon#about to write, iclass 15, count 0 2006.173.12:11:26.70#ibcon#wrote, iclass 15, count 0 2006.173.12:11:26.70#ibcon#about to read 3, iclass 15, count 0 2006.173.12:11:26.72#ibcon#read 3, iclass 15, count 0 2006.173.12:11:26.72#ibcon#about to read 4, iclass 15, count 0 2006.173.12:11:26.72#ibcon#read 4, iclass 15, count 0 2006.173.12:11:26.72#ibcon#about to read 5, iclass 15, count 0 2006.173.12:11:26.72#ibcon#read 5, iclass 15, count 0 2006.173.12:11:26.72#ibcon#about to read 6, iclass 15, count 0 2006.173.12:11:26.72#ibcon#read 6, iclass 15, count 0 2006.173.12:11:26.72#ibcon#end of sib2, iclass 15, count 0 2006.173.12:11:26.72#ibcon#*mode == 0, iclass 15, count 0 2006.173.12:11:26.72#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.12:11:26.72#ibcon#[27=BW32\r\n] 2006.173.12:11:26.72#ibcon#*before write, iclass 15, count 0 2006.173.12:11:26.72#ibcon#enter sib2, iclass 15, count 0 2006.173.12:11:26.72#ibcon#flushed, iclass 15, count 0 2006.173.12:11:26.72#ibcon#about to write, iclass 15, count 0 2006.173.12:11:26.72#ibcon#wrote, iclass 15, count 0 2006.173.12:11:26.72#ibcon#about to read 3, iclass 15, count 0 2006.173.12:11:26.75#ibcon#read 3, iclass 15, count 0 2006.173.12:11:26.75#ibcon#about to read 4, iclass 15, count 0 2006.173.12:11:26.75#ibcon#read 4, iclass 15, count 0 2006.173.12:11:26.75#ibcon#about to read 5, iclass 15, count 0 2006.173.12:11:26.75#ibcon#read 5, iclass 15, count 0 2006.173.12:11:26.75#ibcon#about to read 6, iclass 15, count 0 2006.173.12:11:26.75#ibcon#read 6, iclass 15, count 0 2006.173.12:11:26.75#ibcon#end of sib2, iclass 15, count 0 2006.173.12:11:26.75#ibcon#*after write, iclass 15, count 0 2006.173.12:11:26.75#ibcon#*before return 0, iclass 15, count 0 2006.173.12:11:26.75#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.12:11:26.75#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.12:11:26.75#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.12:11:26.75#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.12:11:26.75$setupk4/ifdk4 2006.173.12:11:26.75$ifdk4/lo= 2006.173.12:11:26.75$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.12:11:26.75$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.12:11:26.75$ifdk4/patch= 2006.173.12:11:26.75$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.12:11:26.75$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.12:11:26.75$setupk4/!*+20s 2006.173.12:11:30.54#abcon#<5=/06 1.6 2.5 22.20 951004.3\r\n> 2006.173.12:11:30.56#abcon#{5=INTERFACE CLEAR} 2006.173.12:11:30.62#abcon#[5=S1D000X0/0*\r\n] 2006.173.12:11:40.71#abcon#<5=/06 1.6 2.6 22.20 951004.3\r\n> 2006.173.12:11:40.73#abcon#{5=INTERFACE CLEAR} 2006.173.12:11:40.79#abcon#[5=S1D000X0/0*\r\n] 2006.173.12:11:41.26$setupk4/"tpicd 2006.173.12:11:41.26$setupk4/echo=off 2006.173.12:11:41.26$setupk4/xlog=off 2006.173.12:11:41.26:!2006.173.12:17:22 2006.173.12:11:51.14#trakl#Source acquired 2006.173.12:11:52.14#flagr#flagr/antenna,acquired 2006.173.12:17:22.00:preob 2006.173.12:17:23.15/onsource/TRACKING 2006.173.12:17:23.15:!2006.173.12:17:32 2006.173.12:17:32.02:"tape 2006.173.12:17:32.02:"st=record 2006.173.12:17:32.02:data_valid=on 2006.173.12:17:32.02:midob 2006.173.12:17:33.15/onsource/TRACKING 2006.173.12:17:33.15/wx/22.17,1004.3,95 2006.173.12:17:33.28/cable/+6.5059E-03 2006.173.12:17:34.37/va/01,07,usb,yes,36,38 2006.173.12:17:34.37/va/02,06,usb,yes,35,36 2006.173.12:17:34.37/va/03,05,usb,yes,45,47 2006.173.12:17:34.37/va/04,06,usb,yes,36,38 2006.173.12:17:34.37/va/05,04,usb,yes,28,29 2006.173.12:17:34.37/va/06,03,usb,yes,40,40 2006.173.12:17:34.37/va/07,04,usb,yes,32,33 2006.173.12:17:34.37/va/08,04,usb,yes,27,33 2006.173.12:17:34.60/valo/01,524.99,yes,locked 2006.173.12:17:34.60/valo/02,534.99,yes,locked 2006.173.12:17:34.60/valo/03,564.99,yes,locked 2006.173.12:17:34.60/valo/04,624.99,yes,locked 2006.173.12:17:34.60/valo/05,734.99,yes,locked 2006.173.12:17:34.60/valo/06,814.99,yes,locked 2006.173.12:17:34.60/valo/07,864.99,yes,locked 2006.173.12:17:34.60/valo/08,884.99,yes,locked 2006.173.12:17:35.69/vb/01,04,usb,yes,29,27 2006.173.12:17:35.69/vb/02,04,usb,yes,31,31 2006.173.12:17:35.69/vb/03,04,usb,yes,28,31 2006.173.12:17:35.69/vb/04,04,usb,yes,33,32 2006.173.12:17:35.69/vb/05,04,usb,yes,25,28 2006.173.12:17:35.69/vb/06,04,usb,yes,30,26 2006.173.12:17:35.69/vb/07,04,usb,yes,29,29 2006.173.12:17:35.69/vb/08,04,usb,yes,27,30 2006.173.12:17:35.92/vblo/01,629.99,yes,locked 2006.173.12:17:35.92/vblo/02,634.99,yes,locked 2006.173.12:17:35.92/vblo/03,649.99,yes,locked 2006.173.12:17:35.92/vblo/04,679.99,yes,locked 2006.173.12:17:35.92/vblo/05,709.99,yes,locked 2006.173.12:17:35.92/vblo/06,719.99,yes,locked 2006.173.12:17:35.92/vblo/07,734.99,yes,locked 2006.173.12:17:35.92/vblo/08,744.99,yes,locked 2006.173.12:17:36.07/vabw/8 2006.173.12:17:36.22/vbbw/8 2006.173.12:17:36.31/xfe/off,on,14.7 2006.173.12:17:36.69/ifatt/23,28,28,28 2006.173.12:17:37.07/fmout-gps/S +3.98E-07 2006.173.12:17:37.12:!2006.173.12:19:12 2006.173.12:19:12.01:data_valid=off 2006.173.12:19:12.02:"et 2006.173.12:19:12.02:!+3s 2006.173.12:19:15.05:"tape 2006.173.12:19:15.06:postob 2006.173.12:19:15.25/cable/+6.5037E-03 2006.173.12:19:15.26/wx/22.17,1004.2,95 2006.173.12:19:15.31/fmout-gps/S +3.98E-07 2006.173.12:19:15.32:scan_name=173-1221,jd0606,40 2006.173.12:19:15.32:source=1741-038,174358.86,-035004.6,2000.0,cw 2006.173.12:19:16.14#flagr#flagr/antenna,new-source 2006.173.12:19:16.15:checkk5 2006.173.12:19:16.54/chk_autoobs//k5ts1/ autoobs is running! 2006.173.12:19:16.93/chk_autoobs//k5ts2/ autoobs is running! 2006.173.12:19:17.34/chk_autoobs//k5ts3/ autoobs is running! 2006.173.12:19:17.74/chk_autoobs//k5ts4/ autoobs is running! 2006.173.12:19:18.14/chk_obsdata//k5ts1/T1731217??a.dat file size is correct (nominal:400MB, actual:396MB). 2006.173.12:19:18.52/chk_obsdata//k5ts2/T1731217??b.dat file size is correct (nominal:400MB, actual:396MB). 2006.173.12:19:18.91/chk_obsdata//k5ts3/T1731217??c.dat file size is correct (nominal:400MB, actual:396MB). 2006.173.12:19:19.32/chk_obsdata//k5ts4/T1731217??d.dat file size is correct (nominal:400MB, actual:396MB). 2006.173.12:19:20.03/k5log//k5ts1_log_newline 2006.173.12:19:20.73/k5log//k5ts2_log_newline 2006.173.12:19:21.45/k5log//k5ts3_log_newline 2006.173.12:19:22.15/k5log//k5ts4_log_newline 2006.173.12:19:22.18/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.12:19:22.18:setupk4=1 2006.173.12:19:22.18$setupk4/echo=on 2006.173.12:19:22.18$setupk4/pcalon 2006.173.12:19:22.18$pcalon/"no phase cal control is implemented here 2006.173.12:19:22.18$setupk4/"tpicd=stop 2006.173.12:19:22.18$setupk4/"rec=synch_on 2006.173.12:19:22.18$setupk4/"rec_mode=128 2006.173.12:19:22.18$setupk4/!* 2006.173.12:19:22.18$setupk4/recpk4 2006.173.12:19:22.18$recpk4/recpatch= 2006.173.12:19:22.18$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.12:19:22.18$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.12:19:22.18$setupk4/vck44 2006.173.12:19:22.18$vck44/valo=1,524.99 2006.173.12:19:22.18#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.12:19:22.18#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.12:19:22.18#ibcon#ireg 17 cls_cnt 0 2006.173.12:19:22.18#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.12:19:22.18#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.12:19:22.18#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.12:19:22.18#ibcon#enter wrdev, iclass 28, count 0 2006.173.12:19:22.18#ibcon#first serial, iclass 28, count 0 2006.173.12:19:22.18#ibcon#enter sib2, iclass 28, count 0 2006.173.12:19:22.18#ibcon#flushed, iclass 28, count 0 2006.173.12:19:22.18#ibcon#about to write, iclass 28, count 0 2006.173.12:19:22.18#ibcon#wrote, iclass 28, count 0 2006.173.12:19:22.18#ibcon#about to read 3, iclass 28, count 0 2006.173.12:19:22.19#ibcon#read 3, iclass 28, count 0 2006.173.12:19:22.19#ibcon#about to read 4, iclass 28, count 0 2006.173.12:19:22.19#ibcon#read 4, iclass 28, count 0 2006.173.12:19:22.19#ibcon#about to read 5, iclass 28, count 0 2006.173.12:19:22.19#ibcon#read 5, iclass 28, count 0 2006.173.12:19:22.19#ibcon#about to read 6, iclass 28, count 0 2006.173.12:19:22.19#ibcon#read 6, iclass 28, count 0 2006.173.12:19:22.19#ibcon#end of sib2, iclass 28, count 0 2006.173.12:19:22.19#ibcon#*mode == 0, iclass 28, count 0 2006.173.12:19:22.19#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.12:19:22.19#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.12:19:22.19#ibcon#*before write, iclass 28, count 0 2006.173.12:19:22.19#ibcon#enter sib2, iclass 28, count 0 2006.173.12:19:22.19#ibcon#flushed, iclass 28, count 0 2006.173.12:19:22.19#ibcon#about to write, iclass 28, count 0 2006.173.12:19:22.19#ibcon#wrote, iclass 28, count 0 2006.173.12:19:22.19#ibcon#about to read 3, iclass 28, count 0 2006.173.12:19:22.24#ibcon#read 3, iclass 28, count 0 2006.173.12:19:22.24#ibcon#about to read 4, iclass 28, count 0 2006.173.12:19:22.24#ibcon#read 4, iclass 28, count 0 2006.173.12:19:22.24#ibcon#about to read 5, iclass 28, count 0 2006.173.12:19:22.24#ibcon#read 5, iclass 28, count 0 2006.173.12:19:22.24#ibcon#about to read 6, iclass 28, count 0 2006.173.12:19:22.24#ibcon#read 6, iclass 28, count 0 2006.173.12:19:22.24#ibcon#end of sib2, iclass 28, count 0 2006.173.12:19:22.24#ibcon#*after write, iclass 28, count 0 2006.173.12:19:22.24#ibcon#*before return 0, iclass 28, count 0 2006.173.12:19:22.24#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.12:19:22.24#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.12:19:22.24#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.12:19:22.24#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.12:19:22.24$vck44/va=1,7 2006.173.12:19:22.24#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.12:19:22.24#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.12:19:22.24#ibcon#ireg 11 cls_cnt 2 2006.173.12:19:22.24#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.12:19:22.24#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.12:19:22.24#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.12:19:22.24#ibcon#enter wrdev, iclass 30, count 2 2006.173.12:19:22.24#ibcon#first serial, iclass 30, count 2 2006.173.12:19:22.24#ibcon#enter sib2, iclass 30, count 2 2006.173.12:19:22.24#ibcon#flushed, iclass 30, count 2 2006.173.12:19:22.24#ibcon#about to write, iclass 30, count 2 2006.173.12:19:22.24#ibcon#wrote, iclass 30, count 2 2006.173.12:19:22.24#ibcon#about to read 3, iclass 30, count 2 2006.173.12:19:22.26#ibcon#read 3, iclass 30, count 2 2006.173.12:19:22.26#ibcon#about to read 4, iclass 30, count 2 2006.173.12:19:22.26#ibcon#read 4, iclass 30, count 2 2006.173.12:19:22.26#ibcon#about to read 5, iclass 30, count 2 2006.173.12:19:22.26#ibcon#read 5, iclass 30, count 2 2006.173.12:19:22.26#ibcon#about to read 6, iclass 30, count 2 2006.173.12:19:22.26#ibcon#read 6, iclass 30, count 2 2006.173.12:19:22.26#ibcon#end of sib2, iclass 30, count 2 2006.173.12:19:22.26#ibcon#*mode == 0, iclass 30, count 2 2006.173.12:19:22.26#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.12:19:22.26#ibcon#[25=AT01-07\r\n] 2006.173.12:19:22.26#ibcon#*before write, iclass 30, count 2 2006.173.12:19:22.26#ibcon#enter sib2, iclass 30, count 2 2006.173.12:19:22.26#ibcon#flushed, iclass 30, count 2 2006.173.12:19:22.26#ibcon#about to write, iclass 30, count 2 2006.173.12:19:22.26#ibcon#wrote, iclass 30, count 2 2006.173.12:19:22.26#ibcon#about to read 3, iclass 30, count 2 2006.173.12:19:22.29#ibcon#read 3, iclass 30, count 2 2006.173.12:19:22.29#ibcon#about to read 4, iclass 30, count 2 2006.173.12:19:22.29#ibcon#read 4, iclass 30, count 2 2006.173.12:19:22.29#ibcon#about to read 5, iclass 30, count 2 2006.173.12:19:22.29#ibcon#read 5, iclass 30, count 2 2006.173.12:19:22.29#ibcon#about to read 6, iclass 30, count 2 2006.173.12:19:22.29#ibcon#read 6, iclass 30, count 2 2006.173.12:19:22.29#ibcon#end of sib2, iclass 30, count 2 2006.173.12:19:22.29#ibcon#*after write, iclass 30, count 2 2006.173.12:19:22.29#ibcon#*before return 0, iclass 30, count 2 2006.173.12:19:22.29#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.12:19:22.29#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.12:19:22.29#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.12:19:22.29#ibcon#ireg 7 cls_cnt 0 2006.173.12:19:22.29#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.12:19:22.41#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.12:19:22.41#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.12:19:22.41#ibcon#enter wrdev, iclass 30, count 0 2006.173.12:19:22.41#ibcon#first serial, iclass 30, count 0 2006.173.12:19:22.41#ibcon#enter sib2, iclass 30, count 0 2006.173.12:19:22.41#ibcon#flushed, iclass 30, count 0 2006.173.12:19:22.41#ibcon#about to write, iclass 30, count 0 2006.173.12:19:22.41#ibcon#wrote, iclass 30, count 0 2006.173.12:19:22.41#ibcon#about to read 3, iclass 30, count 0 2006.173.12:19:22.43#ibcon#read 3, iclass 30, count 0 2006.173.12:19:22.43#ibcon#about to read 4, iclass 30, count 0 2006.173.12:19:22.43#ibcon#read 4, iclass 30, count 0 2006.173.12:19:22.43#ibcon#about to read 5, iclass 30, count 0 2006.173.12:19:22.43#ibcon#read 5, iclass 30, count 0 2006.173.12:19:22.43#ibcon#about to read 6, iclass 30, count 0 2006.173.12:19:22.43#ibcon#read 6, iclass 30, count 0 2006.173.12:19:22.43#ibcon#end of sib2, iclass 30, count 0 2006.173.12:19:22.43#ibcon#*mode == 0, iclass 30, count 0 2006.173.12:19:22.43#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.12:19:22.43#ibcon#[25=USB\r\n] 2006.173.12:19:22.43#ibcon#*before write, iclass 30, count 0 2006.173.12:19:22.43#ibcon#enter sib2, iclass 30, count 0 2006.173.12:19:22.43#ibcon#flushed, iclass 30, count 0 2006.173.12:19:22.43#ibcon#about to write, iclass 30, count 0 2006.173.12:19:22.43#ibcon#wrote, iclass 30, count 0 2006.173.12:19:22.43#ibcon#about to read 3, iclass 30, count 0 2006.173.12:19:22.46#ibcon#read 3, iclass 30, count 0 2006.173.12:19:22.46#ibcon#about to read 4, iclass 30, count 0 2006.173.12:19:22.46#ibcon#read 4, iclass 30, count 0 2006.173.12:19:22.46#ibcon#about to read 5, iclass 30, count 0 2006.173.12:19:22.46#ibcon#read 5, iclass 30, count 0 2006.173.12:19:22.46#ibcon#about to read 6, iclass 30, count 0 2006.173.12:19:22.46#ibcon#read 6, iclass 30, count 0 2006.173.12:19:22.46#ibcon#end of sib2, iclass 30, count 0 2006.173.12:19:22.46#ibcon#*after write, iclass 30, count 0 2006.173.12:19:22.46#ibcon#*before return 0, iclass 30, count 0 2006.173.12:19:22.46#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.12:19:22.46#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.12:19:22.46#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.12:19:22.46#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.12:19:22.46$vck44/valo=2,534.99 2006.173.12:19:22.46#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.12:19:22.46#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.12:19:22.46#ibcon#ireg 17 cls_cnt 0 2006.173.12:19:22.46#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.12:19:22.46#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.12:19:22.46#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.12:19:22.46#ibcon#enter wrdev, iclass 32, count 0 2006.173.12:19:22.46#ibcon#first serial, iclass 32, count 0 2006.173.12:19:22.46#ibcon#enter sib2, iclass 32, count 0 2006.173.12:19:22.46#ibcon#flushed, iclass 32, count 0 2006.173.12:19:22.46#ibcon#about to write, iclass 32, count 0 2006.173.12:19:22.46#ibcon#wrote, iclass 32, count 0 2006.173.12:19:22.46#ibcon#about to read 3, iclass 32, count 0 2006.173.12:19:22.48#ibcon#read 3, iclass 32, count 0 2006.173.12:19:22.48#ibcon#about to read 4, iclass 32, count 0 2006.173.12:19:22.48#ibcon#read 4, iclass 32, count 0 2006.173.12:19:22.48#ibcon#about to read 5, iclass 32, count 0 2006.173.12:19:22.48#ibcon#read 5, iclass 32, count 0 2006.173.12:19:22.48#ibcon#about to read 6, iclass 32, count 0 2006.173.12:19:22.48#ibcon#read 6, iclass 32, count 0 2006.173.12:19:22.48#ibcon#end of sib2, iclass 32, count 0 2006.173.12:19:22.48#ibcon#*mode == 0, iclass 32, count 0 2006.173.12:19:22.48#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.12:19:22.48#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.12:19:22.48#ibcon#*before write, iclass 32, count 0 2006.173.12:19:22.48#ibcon#enter sib2, iclass 32, count 0 2006.173.12:19:22.48#ibcon#flushed, iclass 32, count 0 2006.173.12:19:22.48#ibcon#about to write, iclass 32, count 0 2006.173.12:19:22.48#ibcon#wrote, iclass 32, count 0 2006.173.12:19:22.48#ibcon#about to read 3, iclass 32, count 0 2006.173.12:19:22.52#ibcon#read 3, iclass 32, count 0 2006.173.12:19:22.52#ibcon#about to read 4, iclass 32, count 0 2006.173.12:19:22.52#ibcon#read 4, iclass 32, count 0 2006.173.12:19:22.52#ibcon#about to read 5, iclass 32, count 0 2006.173.12:19:22.52#ibcon#read 5, iclass 32, count 0 2006.173.12:19:22.52#ibcon#about to read 6, iclass 32, count 0 2006.173.12:19:22.52#ibcon#read 6, iclass 32, count 0 2006.173.12:19:22.52#ibcon#end of sib2, iclass 32, count 0 2006.173.12:19:22.52#ibcon#*after write, iclass 32, count 0 2006.173.12:19:22.52#ibcon#*before return 0, iclass 32, count 0 2006.173.12:19:22.52#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.12:19:22.52#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.12:19:22.52#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.12:19:22.52#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.12:19:22.52$vck44/va=2,6 2006.173.12:19:22.52#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.12:19:22.52#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.12:19:22.52#ibcon#ireg 11 cls_cnt 2 2006.173.12:19:22.52#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.12:19:22.58#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.12:19:22.58#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.12:19:22.58#ibcon#enter wrdev, iclass 34, count 2 2006.173.12:19:22.58#ibcon#first serial, iclass 34, count 2 2006.173.12:19:22.58#ibcon#enter sib2, iclass 34, count 2 2006.173.12:19:22.58#ibcon#flushed, iclass 34, count 2 2006.173.12:19:22.58#ibcon#about to write, iclass 34, count 2 2006.173.12:19:22.58#ibcon#wrote, iclass 34, count 2 2006.173.12:19:22.58#ibcon#about to read 3, iclass 34, count 2 2006.173.12:19:22.60#ibcon#read 3, iclass 34, count 2 2006.173.12:19:22.60#ibcon#about to read 4, iclass 34, count 2 2006.173.12:19:22.60#ibcon#read 4, iclass 34, count 2 2006.173.12:19:22.60#ibcon#about to read 5, iclass 34, count 2 2006.173.12:19:22.60#ibcon#read 5, iclass 34, count 2 2006.173.12:19:22.60#ibcon#about to read 6, iclass 34, count 2 2006.173.12:19:22.60#ibcon#read 6, iclass 34, count 2 2006.173.12:19:22.60#ibcon#end of sib2, iclass 34, count 2 2006.173.12:19:22.60#ibcon#*mode == 0, iclass 34, count 2 2006.173.12:19:22.60#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.12:19:22.60#ibcon#[25=AT02-06\r\n] 2006.173.12:19:22.60#ibcon#*before write, iclass 34, count 2 2006.173.12:19:22.60#ibcon#enter sib2, iclass 34, count 2 2006.173.12:19:22.60#ibcon#flushed, iclass 34, count 2 2006.173.12:19:22.60#ibcon#about to write, iclass 34, count 2 2006.173.12:19:22.60#ibcon#wrote, iclass 34, count 2 2006.173.12:19:22.60#ibcon#about to read 3, iclass 34, count 2 2006.173.12:19:22.63#ibcon#read 3, iclass 34, count 2 2006.173.12:19:22.63#ibcon#about to read 4, iclass 34, count 2 2006.173.12:19:22.63#ibcon#read 4, iclass 34, count 2 2006.173.12:19:22.63#ibcon#about to read 5, iclass 34, count 2 2006.173.12:19:22.63#ibcon#read 5, iclass 34, count 2 2006.173.12:19:22.63#ibcon#about to read 6, iclass 34, count 2 2006.173.12:19:22.63#ibcon#read 6, iclass 34, count 2 2006.173.12:19:22.63#ibcon#end of sib2, iclass 34, count 2 2006.173.12:19:22.63#ibcon#*after write, iclass 34, count 2 2006.173.12:19:22.63#ibcon#*before return 0, iclass 34, count 2 2006.173.12:19:22.63#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.12:19:22.63#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.12:19:22.63#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.12:19:22.63#ibcon#ireg 7 cls_cnt 0 2006.173.12:19:22.63#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.12:19:22.75#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.12:19:22.75#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.12:19:22.75#ibcon#enter wrdev, iclass 34, count 0 2006.173.12:19:22.75#ibcon#first serial, iclass 34, count 0 2006.173.12:19:22.75#ibcon#enter sib2, iclass 34, count 0 2006.173.12:19:22.75#ibcon#flushed, iclass 34, count 0 2006.173.12:19:22.75#ibcon#about to write, iclass 34, count 0 2006.173.12:19:22.75#ibcon#wrote, iclass 34, count 0 2006.173.12:19:22.75#ibcon#about to read 3, iclass 34, count 0 2006.173.12:19:22.77#ibcon#read 3, iclass 34, count 0 2006.173.12:19:22.77#ibcon#about to read 4, iclass 34, count 0 2006.173.12:19:22.77#ibcon#read 4, iclass 34, count 0 2006.173.12:19:22.77#ibcon#about to read 5, iclass 34, count 0 2006.173.12:19:22.77#ibcon#read 5, iclass 34, count 0 2006.173.12:19:22.77#ibcon#about to read 6, iclass 34, count 0 2006.173.12:19:22.77#ibcon#read 6, iclass 34, count 0 2006.173.12:19:22.77#ibcon#end of sib2, iclass 34, count 0 2006.173.12:19:22.77#ibcon#*mode == 0, iclass 34, count 0 2006.173.12:19:22.77#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.12:19:22.77#ibcon#[25=USB\r\n] 2006.173.12:19:22.77#ibcon#*before write, iclass 34, count 0 2006.173.12:19:22.77#ibcon#enter sib2, iclass 34, count 0 2006.173.12:19:22.77#ibcon#flushed, iclass 34, count 0 2006.173.12:19:22.77#ibcon#about to write, iclass 34, count 0 2006.173.12:19:22.77#ibcon#wrote, iclass 34, count 0 2006.173.12:19:22.77#ibcon#about to read 3, iclass 34, count 0 2006.173.12:19:22.80#ibcon#read 3, iclass 34, count 0 2006.173.12:19:22.80#ibcon#about to read 4, iclass 34, count 0 2006.173.12:19:22.80#ibcon#read 4, iclass 34, count 0 2006.173.12:19:22.80#ibcon#about to read 5, iclass 34, count 0 2006.173.12:19:22.80#ibcon#read 5, iclass 34, count 0 2006.173.12:19:22.80#ibcon#about to read 6, iclass 34, count 0 2006.173.12:19:22.80#ibcon#read 6, iclass 34, count 0 2006.173.12:19:22.80#ibcon#end of sib2, iclass 34, count 0 2006.173.12:19:22.80#ibcon#*after write, iclass 34, count 0 2006.173.12:19:22.80#ibcon#*before return 0, iclass 34, count 0 2006.173.12:19:22.80#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.12:19:22.80#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.12:19:22.80#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.12:19:22.80#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.12:19:22.80$vck44/valo=3,564.99 2006.173.12:19:22.80#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.12:19:22.80#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.12:19:22.80#ibcon#ireg 17 cls_cnt 0 2006.173.12:19:22.80#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.12:19:22.80#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.12:19:22.80#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.12:19:22.80#ibcon#enter wrdev, iclass 36, count 0 2006.173.12:19:22.80#ibcon#first serial, iclass 36, count 0 2006.173.12:19:22.80#ibcon#enter sib2, iclass 36, count 0 2006.173.12:19:22.80#ibcon#flushed, iclass 36, count 0 2006.173.12:19:22.80#ibcon#about to write, iclass 36, count 0 2006.173.12:19:22.80#ibcon#wrote, iclass 36, count 0 2006.173.12:19:22.80#ibcon#about to read 3, iclass 36, count 0 2006.173.12:19:22.82#ibcon#read 3, iclass 36, count 0 2006.173.12:19:22.82#ibcon#about to read 4, iclass 36, count 0 2006.173.12:19:22.82#ibcon#read 4, iclass 36, count 0 2006.173.12:19:22.82#ibcon#about to read 5, iclass 36, count 0 2006.173.12:19:22.82#ibcon#read 5, iclass 36, count 0 2006.173.12:19:22.82#ibcon#about to read 6, iclass 36, count 0 2006.173.12:19:22.82#ibcon#read 6, iclass 36, count 0 2006.173.12:19:22.82#ibcon#end of sib2, iclass 36, count 0 2006.173.12:19:22.82#ibcon#*mode == 0, iclass 36, count 0 2006.173.12:19:22.82#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.12:19:22.82#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.12:19:22.82#ibcon#*before write, iclass 36, count 0 2006.173.12:19:22.82#ibcon#enter sib2, iclass 36, count 0 2006.173.12:19:22.82#ibcon#flushed, iclass 36, count 0 2006.173.12:19:22.82#ibcon#about to write, iclass 36, count 0 2006.173.12:19:22.82#ibcon#wrote, iclass 36, count 0 2006.173.12:19:22.82#ibcon#about to read 3, iclass 36, count 0 2006.173.12:19:22.86#ibcon#read 3, iclass 36, count 0 2006.173.12:19:22.86#ibcon#about to read 4, iclass 36, count 0 2006.173.12:19:22.86#ibcon#read 4, iclass 36, count 0 2006.173.12:19:22.86#ibcon#about to read 5, iclass 36, count 0 2006.173.12:19:22.86#ibcon#read 5, iclass 36, count 0 2006.173.12:19:22.86#ibcon#about to read 6, iclass 36, count 0 2006.173.12:19:22.86#ibcon#read 6, iclass 36, count 0 2006.173.12:19:22.86#ibcon#end of sib2, iclass 36, count 0 2006.173.12:19:22.86#ibcon#*after write, iclass 36, count 0 2006.173.12:19:22.86#ibcon#*before return 0, iclass 36, count 0 2006.173.12:19:22.86#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.12:19:22.86#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.12:19:22.86#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.12:19:22.86#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.12:19:22.86$vck44/va=3,5 2006.173.12:19:22.86#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.12:19:22.86#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.12:19:22.86#ibcon#ireg 11 cls_cnt 2 2006.173.12:19:22.86#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.12:19:22.92#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.12:19:22.92#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.12:19:22.92#ibcon#enter wrdev, iclass 38, count 2 2006.173.12:19:22.92#ibcon#first serial, iclass 38, count 2 2006.173.12:19:22.92#ibcon#enter sib2, iclass 38, count 2 2006.173.12:19:22.92#ibcon#flushed, iclass 38, count 2 2006.173.12:19:22.92#ibcon#about to write, iclass 38, count 2 2006.173.12:19:22.92#ibcon#wrote, iclass 38, count 2 2006.173.12:19:22.92#ibcon#about to read 3, iclass 38, count 2 2006.173.12:19:22.94#ibcon#read 3, iclass 38, count 2 2006.173.12:19:22.94#ibcon#about to read 4, iclass 38, count 2 2006.173.12:19:22.94#ibcon#read 4, iclass 38, count 2 2006.173.12:19:22.94#ibcon#about to read 5, iclass 38, count 2 2006.173.12:19:22.94#ibcon#read 5, iclass 38, count 2 2006.173.12:19:22.94#ibcon#about to read 6, iclass 38, count 2 2006.173.12:19:22.94#ibcon#read 6, iclass 38, count 2 2006.173.12:19:22.94#ibcon#end of sib2, iclass 38, count 2 2006.173.12:19:22.94#ibcon#*mode == 0, iclass 38, count 2 2006.173.12:19:22.94#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.12:19:22.94#ibcon#[25=AT03-05\r\n] 2006.173.12:19:22.94#ibcon#*before write, iclass 38, count 2 2006.173.12:19:22.94#ibcon#enter sib2, iclass 38, count 2 2006.173.12:19:22.94#ibcon#flushed, iclass 38, count 2 2006.173.12:19:22.94#ibcon#about to write, iclass 38, count 2 2006.173.12:19:22.94#ibcon#wrote, iclass 38, count 2 2006.173.12:19:22.94#ibcon#about to read 3, iclass 38, count 2 2006.173.12:19:22.97#ibcon#read 3, iclass 38, count 2 2006.173.12:19:22.97#ibcon#about to read 4, iclass 38, count 2 2006.173.12:19:22.97#ibcon#read 4, iclass 38, count 2 2006.173.12:19:22.97#ibcon#about to read 5, iclass 38, count 2 2006.173.12:19:22.97#ibcon#read 5, iclass 38, count 2 2006.173.12:19:22.97#ibcon#about to read 6, iclass 38, count 2 2006.173.12:19:22.97#ibcon#read 6, iclass 38, count 2 2006.173.12:19:22.97#ibcon#end of sib2, iclass 38, count 2 2006.173.12:19:22.97#ibcon#*after write, iclass 38, count 2 2006.173.12:19:22.97#ibcon#*before return 0, iclass 38, count 2 2006.173.12:19:22.97#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.12:19:22.97#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.12:19:22.97#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.12:19:22.97#ibcon#ireg 7 cls_cnt 0 2006.173.12:19:22.97#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.12:19:23.09#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.12:19:23.09#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.12:19:23.09#ibcon#enter wrdev, iclass 38, count 0 2006.173.12:19:23.09#ibcon#first serial, iclass 38, count 0 2006.173.12:19:23.09#ibcon#enter sib2, iclass 38, count 0 2006.173.12:19:23.09#ibcon#flushed, iclass 38, count 0 2006.173.12:19:23.09#ibcon#about to write, iclass 38, count 0 2006.173.12:19:23.09#ibcon#wrote, iclass 38, count 0 2006.173.12:19:23.09#ibcon#about to read 3, iclass 38, count 0 2006.173.12:19:23.11#ibcon#read 3, iclass 38, count 0 2006.173.12:19:23.11#ibcon#about to read 4, iclass 38, count 0 2006.173.12:19:23.11#ibcon#read 4, iclass 38, count 0 2006.173.12:19:23.11#ibcon#about to read 5, iclass 38, count 0 2006.173.12:19:23.11#ibcon#read 5, iclass 38, count 0 2006.173.12:19:23.11#ibcon#about to read 6, iclass 38, count 0 2006.173.12:19:23.11#ibcon#read 6, iclass 38, count 0 2006.173.12:19:23.11#ibcon#end of sib2, iclass 38, count 0 2006.173.12:19:23.11#ibcon#*mode == 0, iclass 38, count 0 2006.173.12:19:23.11#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.12:19:23.11#ibcon#[25=USB\r\n] 2006.173.12:19:23.11#ibcon#*before write, iclass 38, count 0 2006.173.12:19:23.11#ibcon#enter sib2, iclass 38, count 0 2006.173.12:19:23.11#ibcon#flushed, iclass 38, count 0 2006.173.12:19:23.11#ibcon#about to write, iclass 38, count 0 2006.173.12:19:23.11#ibcon#wrote, iclass 38, count 0 2006.173.12:19:23.11#ibcon#about to read 3, iclass 38, count 0 2006.173.12:19:23.14#ibcon#read 3, iclass 38, count 0 2006.173.12:19:23.14#ibcon#about to read 4, iclass 38, count 0 2006.173.12:19:23.14#ibcon#read 4, iclass 38, count 0 2006.173.12:19:23.14#ibcon#about to read 5, iclass 38, count 0 2006.173.12:19:23.14#ibcon#read 5, iclass 38, count 0 2006.173.12:19:23.14#ibcon#about to read 6, iclass 38, count 0 2006.173.12:19:23.14#ibcon#read 6, iclass 38, count 0 2006.173.12:19:23.14#ibcon#end of sib2, iclass 38, count 0 2006.173.12:19:23.14#ibcon#*after write, iclass 38, count 0 2006.173.12:19:23.14#ibcon#*before return 0, iclass 38, count 0 2006.173.12:19:23.14#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.12:19:23.14#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.12:19:23.14#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.12:19:23.14#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.12:19:23.15$vck44/valo=4,624.99 2006.173.12:19:23.15#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.12:19:23.15#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.12:19:23.15#ibcon#ireg 17 cls_cnt 0 2006.173.12:19:23.15#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.12:19:23.15#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.12:19:23.15#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.12:19:23.15#ibcon#enter wrdev, iclass 40, count 0 2006.173.12:19:23.15#ibcon#first serial, iclass 40, count 0 2006.173.12:19:23.15#ibcon#enter sib2, iclass 40, count 0 2006.173.12:19:23.15#ibcon#flushed, iclass 40, count 0 2006.173.12:19:23.15#ibcon#about to write, iclass 40, count 0 2006.173.12:19:23.15#ibcon#wrote, iclass 40, count 0 2006.173.12:19:23.15#ibcon#about to read 3, iclass 40, count 0 2006.173.12:19:23.16#ibcon#read 3, iclass 40, count 0 2006.173.12:19:23.16#ibcon#about to read 4, iclass 40, count 0 2006.173.12:19:23.16#ibcon#read 4, iclass 40, count 0 2006.173.12:19:23.16#ibcon#about to read 5, iclass 40, count 0 2006.173.12:19:23.16#ibcon#read 5, iclass 40, count 0 2006.173.12:19:23.16#ibcon#about to read 6, iclass 40, count 0 2006.173.12:19:23.16#ibcon#read 6, iclass 40, count 0 2006.173.12:19:23.16#ibcon#end of sib2, iclass 40, count 0 2006.173.12:19:23.16#ibcon#*mode == 0, iclass 40, count 0 2006.173.12:19:23.16#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.12:19:23.16#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.12:19:23.16#ibcon#*before write, iclass 40, count 0 2006.173.12:19:23.16#ibcon#enter sib2, iclass 40, count 0 2006.173.12:19:23.16#ibcon#flushed, iclass 40, count 0 2006.173.12:19:23.16#ibcon#about to write, iclass 40, count 0 2006.173.12:19:23.16#ibcon#wrote, iclass 40, count 0 2006.173.12:19:23.16#ibcon#about to read 3, iclass 40, count 0 2006.173.12:19:23.20#ibcon#read 3, iclass 40, count 0 2006.173.12:19:23.20#ibcon#about to read 4, iclass 40, count 0 2006.173.12:19:23.20#ibcon#read 4, iclass 40, count 0 2006.173.12:19:23.20#ibcon#about to read 5, iclass 40, count 0 2006.173.12:19:23.20#ibcon#read 5, iclass 40, count 0 2006.173.12:19:23.20#ibcon#about to read 6, iclass 40, count 0 2006.173.12:19:23.20#ibcon#read 6, iclass 40, count 0 2006.173.12:19:23.20#ibcon#end of sib2, iclass 40, count 0 2006.173.12:19:23.20#ibcon#*after write, iclass 40, count 0 2006.173.12:19:23.20#ibcon#*before return 0, iclass 40, count 0 2006.173.12:19:23.20#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.12:19:23.20#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.12:19:23.20#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.12:19:23.20#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.12:19:23.20$vck44/va=4,6 2006.173.12:19:23.20#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.12:19:23.20#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.12:19:23.20#ibcon#ireg 11 cls_cnt 2 2006.173.12:19:23.20#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.12:19:23.26#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.12:19:23.26#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.12:19:23.26#ibcon#enter wrdev, iclass 4, count 2 2006.173.12:19:23.26#ibcon#first serial, iclass 4, count 2 2006.173.12:19:23.26#ibcon#enter sib2, iclass 4, count 2 2006.173.12:19:23.26#ibcon#flushed, iclass 4, count 2 2006.173.12:19:23.26#ibcon#about to write, iclass 4, count 2 2006.173.12:19:23.26#ibcon#wrote, iclass 4, count 2 2006.173.12:19:23.26#ibcon#about to read 3, iclass 4, count 2 2006.173.12:19:23.28#ibcon#read 3, iclass 4, count 2 2006.173.12:19:23.28#ibcon#about to read 4, iclass 4, count 2 2006.173.12:19:23.28#ibcon#read 4, iclass 4, count 2 2006.173.12:19:23.28#ibcon#about to read 5, iclass 4, count 2 2006.173.12:19:23.28#ibcon#read 5, iclass 4, count 2 2006.173.12:19:23.28#ibcon#about to read 6, iclass 4, count 2 2006.173.12:19:23.28#ibcon#read 6, iclass 4, count 2 2006.173.12:19:23.28#ibcon#end of sib2, iclass 4, count 2 2006.173.12:19:23.28#ibcon#*mode == 0, iclass 4, count 2 2006.173.12:19:23.28#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.12:19:23.28#ibcon#[25=AT04-06\r\n] 2006.173.12:19:23.28#ibcon#*before write, iclass 4, count 2 2006.173.12:19:23.28#ibcon#enter sib2, iclass 4, count 2 2006.173.12:19:23.28#ibcon#flushed, iclass 4, count 2 2006.173.12:19:23.28#ibcon#about to write, iclass 4, count 2 2006.173.12:19:23.28#ibcon#wrote, iclass 4, count 2 2006.173.12:19:23.28#ibcon#about to read 3, iclass 4, count 2 2006.173.12:19:23.31#ibcon#read 3, iclass 4, count 2 2006.173.12:19:23.31#ibcon#about to read 4, iclass 4, count 2 2006.173.12:19:23.31#ibcon#read 4, iclass 4, count 2 2006.173.12:19:23.31#ibcon#about to read 5, iclass 4, count 2 2006.173.12:19:23.31#ibcon#read 5, iclass 4, count 2 2006.173.12:19:23.31#ibcon#about to read 6, iclass 4, count 2 2006.173.12:19:23.31#ibcon#read 6, iclass 4, count 2 2006.173.12:19:23.31#ibcon#end of sib2, iclass 4, count 2 2006.173.12:19:23.31#ibcon#*after write, iclass 4, count 2 2006.173.12:19:23.31#ibcon#*before return 0, iclass 4, count 2 2006.173.12:19:23.31#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.12:19:23.31#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.12:19:23.31#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.12:19:23.31#ibcon#ireg 7 cls_cnt 0 2006.173.12:19:23.31#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.12:19:23.43#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.12:19:23.43#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.12:19:23.43#ibcon#enter wrdev, iclass 4, count 0 2006.173.12:19:23.43#ibcon#first serial, iclass 4, count 0 2006.173.12:19:23.43#ibcon#enter sib2, iclass 4, count 0 2006.173.12:19:23.43#ibcon#flushed, iclass 4, count 0 2006.173.12:19:23.43#ibcon#about to write, iclass 4, count 0 2006.173.12:19:23.43#ibcon#wrote, iclass 4, count 0 2006.173.12:19:23.43#ibcon#about to read 3, iclass 4, count 0 2006.173.12:19:23.45#ibcon#read 3, iclass 4, count 0 2006.173.12:19:23.45#ibcon#about to read 4, iclass 4, count 0 2006.173.12:19:23.45#ibcon#read 4, iclass 4, count 0 2006.173.12:19:23.45#ibcon#about to read 5, iclass 4, count 0 2006.173.12:19:23.45#ibcon#read 5, iclass 4, count 0 2006.173.12:19:23.45#ibcon#about to read 6, iclass 4, count 0 2006.173.12:19:23.45#ibcon#read 6, iclass 4, count 0 2006.173.12:19:23.45#ibcon#end of sib2, iclass 4, count 0 2006.173.12:19:23.45#ibcon#*mode == 0, iclass 4, count 0 2006.173.12:19:23.45#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.12:19:23.45#ibcon#[25=USB\r\n] 2006.173.12:19:23.45#ibcon#*before write, iclass 4, count 0 2006.173.12:19:23.45#ibcon#enter sib2, iclass 4, count 0 2006.173.12:19:23.45#ibcon#flushed, iclass 4, count 0 2006.173.12:19:23.45#ibcon#about to write, iclass 4, count 0 2006.173.12:19:23.45#ibcon#wrote, iclass 4, count 0 2006.173.12:19:23.45#ibcon#about to read 3, iclass 4, count 0 2006.173.12:19:23.48#ibcon#read 3, iclass 4, count 0 2006.173.12:19:23.48#ibcon#about to read 4, iclass 4, count 0 2006.173.12:19:23.48#ibcon#read 4, iclass 4, count 0 2006.173.12:19:23.48#ibcon#about to read 5, iclass 4, count 0 2006.173.12:19:23.48#ibcon#read 5, iclass 4, count 0 2006.173.12:19:23.48#ibcon#about to read 6, iclass 4, count 0 2006.173.12:19:23.48#ibcon#read 6, iclass 4, count 0 2006.173.12:19:23.48#ibcon#end of sib2, iclass 4, count 0 2006.173.12:19:23.48#ibcon#*after write, iclass 4, count 0 2006.173.12:19:23.48#ibcon#*before return 0, iclass 4, count 0 2006.173.12:19:23.48#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.12:19:23.48#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.12:19:23.48#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.12:19:23.48#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.12:19:23.48$vck44/valo=5,734.99 2006.173.12:19:23.48#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.12:19:23.48#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.12:19:23.48#ibcon#ireg 17 cls_cnt 0 2006.173.12:19:23.48#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.12:19:23.48#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.12:19:23.48#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.12:19:23.48#ibcon#enter wrdev, iclass 6, count 0 2006.173.12:19:23.48#ibcon#first serial, iclass 6, count 0 2006.173.12:19:23.48#ibcon#enter sib2, iclass 6, count 0 2006.173.12:19:23.48#ibcon#flushed, iclass 6, count 0 2006.173.12:19:23.48#ibcon#about to write, iclass 6, count 0 2006.173.12:19:23.48#ibcon#wrote, iclass 6, count 0 2006.173.12:19:23.48#ibcon#about to read 3, iclass 6, count 0 2006.173.12:19:23.50#ibcon#read 3, iclass 6, count 0 2006.173.12:19:23.50#ibcon#about to read 4, iclass 6, count 0 2006.173.12:19:23.50#ibcon#read 4, iclass 6, count 0 2006.173.12:19:23.50#ibcon#about to read 5, iclass 6, count 0 2006.173.12:19:23.50#ibcon#read 5, iclass 6, count 0 2006.173.12:19:23.50#ibcon#about to read 6, iclass 6, count 0 2006.173.12:19:23.50#ibcon#read 6, iclass 6, count 0 2006.173.12:19:23.50#ibcon#end of sib2, iclass 6, count 0 2006.173.12:19:23.50#ibcon#*mode == 0, iclass 6, count 0 2006.173.12:19:23.50#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.12:19:23.50#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.12:19:23.50#ibcon#*before write, iclass 6, count 0 2006.173.12:19:23.50#ibcon#enter sib2, iclass 6, count 0 2006.173.12:19:23.50#ibcon#flushed, iclass 6, count 0 2006.173.12:19:23.50#ibcon#about to write, iclass 6, count 0 2006.173.12:19:23.50#ibcon#wrote, iclass 6, count 0 2006.173.12:19:23.50#ibcon#about to read 3, iclass 6, count 0 2006.173.12:19:23.54#ibcon#read 3, iclass 6, count 0 2006.173.12:19:23.54#ibcon#about to read 4, iclass 6, count 0 2006.173.12:19:23.54#ibcon#read 4, iclass 6, count 0 2006.173.12:19:23.54#ibcon#about to read 5, iclass 6, count 0 2006.173.12:19:23.54#ibcon#read 5, iclass 6, count 0 2006.173.12:19:23.54#ibcon#about to read 6, iclass 6, count 0 2006.173.12:19:23.54#ibcon#read 6, iclass 6, count 0 2006.173.12:19:23.54#ibcon#end of sib2, iclass 6, count 0 2006.173.12:19:23.54#ibcon#*after write, iclass 6, count 0 2006.173.12:19:23.54#ibcon#*before return 0, iclass 6, count 0 2006.173.12:19:23.54#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.12:19:23.54#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.12:19:23.54#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.12:19:23.54#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.12:19:23.54$vck44/va=5,4 2006.173.12:19:23.54#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.12:19:23.54#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.12:19:23.54#ibcon#ireg 11 cls_cnt 2 2006.173.12:19:23.54#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.12:19:23.60#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.12:19:23.60#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.12:19:23.60#ibcon#enter wrdev, iclass 10, count 2 2006.173.12:19:23.60#ibcon#first serial, iclass 10, count 2 2006.173.12:19:23.60#ibcon#enter sib2, iclass 10, count 2 2006.173.12:19:23.60#ibcon#flushed, iclass 10, count 2 2006.173.12:19:23.60#ibcon#about to write, iclass 10, count 2 2006.173.12:19:23.60#ibcon#wrote, iclass 10, count 2 2006.173.12:19:23.60#ibcon#about to read 3, iclass 10, count 2 2006.173.12:19:23.62#ibcon#read 3, iclass 10, count 2 2006.173.12:19:23.62#ibcon#about to read 4, iclass 10, count 2 2006.173.12:19:23.62#ibcon#read 4, iclass 10, count 2 2006.173.12:19:23.62#ibcon#about to read 5, iclass 10, count 2 2006.173.12:19:23.62#ibcon#read 5, iclass 10, count 2 2006.173.12:19:23.62#ibcon#about to read 6, iclass 10, count 2 2006.173.12:19:23.62#ibcon#read 6, iclass 10, count 2 2006.173.12:19:23.62#ibcon#end of sib2, iclass 10, count 2 2006.173.12:19:23.62#ibcon#*mode == 0, iclass 10, count 2 2006.173.12:19:23.62#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.12:19:23.62#ibcon#[25=AT05-04\r\n] 2006.173.12:19:23.62#ibcon#*before write, iclass 10, count 2 2006.173.12:19:23.62#ibcon#enter sib2, iclass 10, count 2 2006.173.12:19:23.62#ibcon#flushed, iclass 10, count 2 2006.173.12:19:23.62#ibcon#about to write, iclass 10, count 2 2006.173.12:19:23.62#ibcon#wrote, iclass 10, count 2 2006.173.12:19:23.62#ibcon#about to read 3, iclass 10, count 2 2006.173.12:19:23.65#ibcon#read 3, iclass 10, count 2 2006.173.12:19:23.65#ibcon#about to read 4, iclass 10, count 2 2006.173.12:19:23.65#ibcon#read 4, iclass 10, count 2 2006.173.12:19:23.65#ibcon#about to read 5, iclass 10, count 2 2006.173.12:19:23.65#ibcon#read 5, iclass 10, count 2 2006.173.12:19:23.65#ibcon#about to read 6, iclass 10, count 2 2006.173.12:19:23.65#ibcon#read 6, iclass 10, count 2 2006.173.12:19:23.65#ibcon#end of sib2, iclass 10, count 2 2006.173.12:19:23.65#ibcon#*after write, iclass 10, count 2 2006.173.12:19:23.65#ibcon#*before return 0, iclass 10, count 2 2006.173.12:19:23.65#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.12:19:23.65#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.12:19:23.65#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.12:19:23.65#ibcon#ireg 7 cls_cnt 0 2006.173.12:19:23.65#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.12:19:23.77#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.12:19:23.77#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.12:19:23.77#ibcon#enter wrdev, iclass 10, count 0 2006.173.12:19:23.77#ibcon#first serial, iclass 10, count 0 2006.173.12:19:23.77#ibcon#enter sib2, iclass 10, count 0 2006.173.12:19:23.77#ibcon#flushed, iclass 10, count 0 2006.173.12:19:23.77#ibcon#about to write, iclass 10, count 0 2006.173.12:19:23.77#ibcon#wrote, iclass 10, count 0 2006.173.12:19:23.77#ibcon#about to read 3, iclass 10, count 0 2006.173.12:19:23.79#ibcon#read 3, iclass 10, count 0 2006.173.12:19:23.79#ibcon#about to read 4, iclass 10, count 0 2006.173.12:19:23.79#ibcon#read 4, iclass 10, count 0 2006.173.12:19:23.79#ibcon#about to read 5, iclass 10, count 0 2006.173.12:19:23.79#ibcon#read 5, iclass 10, count 0 2006.173.12:19:23.79#ibcon#about to read 6, iclass 10, count 0 2006.173.12:19:23.79#ibcon#read 6, iclass 10, count 0 2006.173.12:19:23.79#ibcon#end of sib2, iclass 10, count 0 2006.173.12:19:23.79#ibcon#*mode == 0, iclass 10, count 0 2006.173.12:19:23.79#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.12:19:23.79#ibcon#[25=USB\r\n] 2006.173.12:19:23.79#ibcon#*before write, iclass 10, count 0 2006.173.12:19:23.79#ibcon#enter sib2, iclass 10, count 0 2006.173.12:19:23.79#ibcon#flushed, iclass 10, count 0 2006.173.12:19:23.79#ibcon#about to write, iclass 10, count 0 2006.173.12:19:23.79#ibcon#wrote, iclass 10, count 0 2006.173.12:19:23.79#ibcon#about to read 3, iclass 10, count 0 2006.173.12:19:23.82#ibcon#read 3, iclass 10, count 0 2006.173.12:19:23.82#ibcon#about to read 4, iclass 10, count 0 2006.173.12:19:23.82#ibcon#read 4, iclass 10, count 0 2006.173.12:19:23.82#ibcon#about to read 5, iclass 10, count 0 2006.173.12:19:23.82#ibcon#read 5, iclass 10, count 0 2006.173.12:19:23.82#ibcon#about to read 6, iclass 10, count 0 2006.173.12:19:23.82#ibcon#read 6, iclass 10, count 0 2006.173.12:19:23.82#ibcon#end of sib2, iclass 10, count 0 2006.173.12:19:23.82#ibcon#*after write, iclass 10, count 0 2006.173.12:19:23.82#ibcon#*before return 0, iclass 10, count 0 2006.173.12:19:23.82#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.12:19:23.82#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.12:19:23.82#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.12:19:23.82#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.12:19:23.82$vck44/valo=6,814.99 2006.173.12:19:23.82#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.12:19:23.82#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.12:19:23.82#ibcon#ireg 17 cls_cnt 0 2006.173.12:19:23.82#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.12:19:23.82#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.12:19:23.82#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.12:19:23.82#ibcon#enter wrdev, iclass 12, count 0 2006.173.12:19:23.82#ibcon#first serial, iclass 12, count 0 2006.173.12:19:23.82#ibcon#enter sib2, iclass 12, count 0 2006.173.12:19:23.82#ibcon#flushed, iclass 12, count 0 2006.173.12:19:23.82#ibcon#about to write, iclass 12, count 0 2006.173.12:19:23.82#ibcon#wrote, iclass 12, count 0 2006.173.12:19:23.82#ibcon#about to read 3, iclass 12, count 0 2006.173.12:19:23.84#ibcon#read 3, iclass 12, count 0 2006.173.12:19:23.84#ibcon#about to read 4, iclass 12, count 0 2006.173.12:19:23.84#ibcon#read 4, iclass 12, count 0 2006.173.12:19:23.84#ibcon#about to read 5, iclass 12, count 0 2006.173.12:19:23.84#ibcon#read 5, iclass 12, count 0 2006.173.12:19:23.84#ibcon#about to read 6, iclass 12, count 0 2006.173.12:19:23.84#ibcon#read 6, iclass 12, count 0 2006.173.12:19:23.84#ibcon#end of sib2, iclass 12, count 0 2006.173.12:19:23.84#ibcon#*mode == 0, iclass 12, count 0 2006.173.12:19:23.84#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.12:19:23.84#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.12:19:23.84#ibcon#*before write, iclass 12, count 0 2006.173.12:19:23.84#ibcon#enter sib2, iclass 12, count 0 2006.173.12:19:23.84#ibcon#flushed, iclass 12, count 0 2006.173.12:19:23.84#ibcon#about to write, iclass 12, count 0 2006.173.12:19:23.84#ibcon#wrote, iclass 12, count 0 2006.173.12:19:23.84#ibcon#about to read 3, iclass 12, count 0 2006.173.12:19:23.88#ibcon#read 3, iclass 12, count 0 2006.173.12:19:23.88#ibcon#about to read 4, iclass 12, count 0 2006.173.12:19:23.88#ibcon#read 4, iclass 12, count 0 2006.173.12:19:23.88#ibcon#about to read 5, iclass 12, count 0 2006.173.12:19:23.88#ibcon#read 5, iclass 12, count 0 2006.173.12:19:23.88#ibcon#about to read 6, iclass 12, count 0 2006.173.12:19:23.88#ibcon#read 6, iclass 12, count 0 2006.173.12:19:23.88#ibcon#end of sib2, iclass 12, count 0 2006.173.12:19:23.88#ibcon#*after write, iclass 12, count 0 2006.173.12:19:23.88#ibcon#*before return 0, iclass 12, count 0 2006.173.12:19:23.88#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.12:19:23.88#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.12:19:23.88#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.12:19:23.88#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.12:19:23.88$vck44/va=6,3 2006.173.12:19:23.88#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.12:19:23.88#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.12:19:23.88#ibcon#ireg 11 cls_cnt 2 2006.173.12:19:23.88#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.12:19:23.94#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.12:19:23.94#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.12:19:23.94#ibcon#enter wrdev, iclass 14, count 2 2006.173.12:19:23.94#ibcon#first serial, iclass 14, count 2 2006.173.12:19:23.94#ibcon#enter sib2, iclass 14, count 2 2006.173.12:19:23.94#ibcon#flushed, iclass 14, count 2 2006.173.12:19:23.94#ibcon#about to write, iclass 14, count 2 2006.173.12:19:23.94#ibcon#wrote, iclass 14, count 2 2006.173.12:19:23.94#ibcon#about to read 3, iclass 14, count 2 2006.173.12:19:23.96#ibcon#read 3, iclass 14, count 2 2006.173.12:19:23.96#ibcon#about to read 4, iclass 14, count 2 2006.173.12:19:23.96#ibcon#read 4, iclass 14, count 2 2006.173.12:19:23.96#ibcon#about to read 5, iclass 14, count 2 2006.173.12:19:23.96#ibcon#read 5, iclass 14, count 2 2006.173.12:19:23.96#ibcon#about to read 6, iclass 14, count 2 2006.173.12:19:23.96#ibcon#read 6, iclass 14, count 2 2006.173.12:19:23.96#ibcon#end of sib2, iclass 14, count 2 2006.173.12:19:23.96#ibcon#*mode == 0, iclass 14, count 2 2006.173.12:19:23.96#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.12:19:23.96#ibcon#[25=AT06-03\r\n] 2006.173.12:19:23.96#ibcon#*before write, iclass 14, count 2 2006.173.12:19:23.96#ibcon#enter sib2, iclass 14, count 2 2006.173.12:19:23.96#ibcon#flushed, iclass 14, count 2 2006.173.12:19:23.96#ibcon#about to write, iclass 14, count 2 2006.173.12:19:23.96#ibcon#wrote, iclass 14, count 2 2006.173.12:19:23.96#ibcon#about to read 3, iclass 14, count 2 2006.173.12:19:23.99#ibcon#read 3, iclass 14, count 2 2006.173.12:19:23.99#ibcon#about to read 4, iclass 14, count 2 2006.173.12:19:23.99#ibcon#read 4, iclass 14, count 2 2006.173.12:19:23.99#ibcon#about to read 5, iclass 14, count 2 2006.173.12:19:23.99#ibcon#read 5, iclass 14, count 2 2006.173.12:19:23.99#ibcon#about to read 6, iclass 14, count 2 2006.173.12:19:23.99#ibcon#read 6, iclass 14, count 2 2006.173.12:19:23.99#ibcon#end of sib2, iclass 14, count 2 2006.173.12:19:23.99#ibcon#*after write, iclass 14, count 2 2006.173.12:19:23.99#ibcon#*before return 0, iclass 14, count 2 2006.173.12:19:23.99#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.12:19:23.99#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.12:19:23.99#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.12:19:23.99#ibcon#ireg 7 cls_cnt 0 2006.173.12:19:23.99#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.12:19:24.11#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.12:19:24.11#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.12:19:24.11#ibcon#enter wrdev, iclass 14, count 0 2006.173.12:19:24.11#ibcon#first serial, iclass 14, count 0 2006.173.12:19:24.11#ibcon#enter sib2, iclass 14, count 0 2006.173.12:19:24.11#ibcon#flushed, iclass 14, count 0 2006.173.12:19:24.11#ibcon#about to write, iclass 14, count 0 2006.173.12:19:24.11#ibcon#wrote, iclass 14, count 0 2006.173.12:19:24.11#ibcon#about to read 3, iclass 14, count 0 2006.173.12:19:24.13#ibcon#read 3, iclass 14, count 0 2006.173.12:19:24.13#ibcon#about to read 4, iclass 14, count 0 2006.173.12:19:24.13#ibcon#read 4, iclass 14, count 0 2006.173.12:19:24.13#ibcon#about to read 5, iclass 14, count 0 2006.173.12:19:24.13#ibcon#read 5, iclass 14, count 0 2006.173.12:19:24.13#ibcon#about to read 6, iclass 14, count 0 2006.173.12:19:24.13#ibcon#read 6, iclass 14, count 0 2006.173.12:19:24.13#ibcon#end of sib2, iclass 14, count 0 2006.173.12:19:24.13#ibcon#*mode == 0, iclass 14, count 0 2006.173.12:19:24.13#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.12:19:24.13#ibcon#[25=USB\r\n] 2006.173.12:19:24.13#ibcon#*before write, iclass 14, count 0 2006.173.12:19:24.13#ibcon#enter sib2, iclass 14, count 0 2006.173.12:19:24.13#ibcon#flushed, iclass 14, count 0 2006.173.12:19:24.13#ibcon#about to write, iclass 14, count 0 2006.173.12:19:24.13#ibcon#wrote, iclass 14, count 0 2006.173.12:19:24.13#ibcon#about to read 3, iclass 14, count 0 2006.173.12:19:24.16#ibcon#read 3, iclass 14, count 0 2006.173.12:19:24.16#ibcon#about to read 4, iclass 14, count 0 2006.173.12:19:24.16#ibcon#read 4, iclass 14, count 0 2006.173.12:19:24.16#ibcon#about to read 5, iclass 14, count 0 2006.173.12:19:24.16#ibcon#read 5, iclass 14, count 0 2006.173.12:19:24.16#ibcon#about to read 6, iclass 14, count 0 2006.173.12:19:24.16#ibcon#read 6, iclass 14, count 0 2006.173.12:19:24.16#ibcon#end of sib2, iclass 14, count 0 2006.173.12:19:24.16#ibcon#*after write, iclass 14, count 0 2006.173.12:19:24.16#ibcon#*before return 0, iclass 14, count 0 2006.173.12:19:24.16#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.12:19:24.16#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.12:19:24.16#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.12:19:24.16#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.12:19:24.16$vck44/valo=7,864.99 2006.173.12:19:24.17#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.12:19:24.17#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.12:19:24.17#ibcon#ireg 17 cls_cnt 0 2006.173.12:19:24.17#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.12:19:24.17#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.12:19:24.17#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.12:19:24.17#ibcon#enter wrdev, iclass 16, count 0 2006.173.12:19:24.17#ibcon#first serial, iclass 16, count 0 2006.173.12:19:24.17#ibcon#enter sib2, iclass 16, count 0 2006.173.12:19:24.17#ibcon#flushed, iclass 16, count 0 2006.173.12:19:24.17#ibcon#about to write, iclass 16, count 0 2006.173.12:19:24.17#ibcon#wrote, iclass 16, count 0 2006.173.12:19:24.17#ibcon#about to read 3, iclass 16, count 0 2006.173.12:19:24.18#ibcon#read 3, iclass 16, count 0 2006.173.12:19:24.18#ibcon#about to read 4, iclass 16, count 0 2006.173.12:19:24.18#ibcon#read 4, iclass 16, count 0 2006.173.12:19:24.18#ibcon#about to read 5, iclass 16, count 0 2006.173.12:19:24.18#ibcon#read 5, iclass 16, count 0 2006.173.12:19:24.18#ibcon#about to read 6, iclass 16, count 0 2006.173.12:19:24.18#ibcon#read 6, iclass 16, count 0 2006.173.12:19:24.18#ibcon#end of sib2, iclass 16, count 0 2006.173.12:19:24.18#ibcon#*mode == 0, iclass 16, count 0 2006.173.12:19:24.18#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.12:19:24.18#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.12:19:24.18#ibcon#*before write, iclass 16, count 0 2006.173.12:19:24.18#ibcon#enter sib2, iclass 16, count 0 2006.173.12:19:24.18#ibcon#flushed, iclass 16, count 0 2006.173.12:19:24.18#ibcon#about to write, iclass 16, count 0 2006.173.12:19:24.18#ibcon#wrote, iclass 16, count 0 2006.173.12:19:24.18#ibcon#about to read 3, iclass 16, count 0 2006.173.12:19:24.22#ibcon#read 3, iclass 16, count 0 2006.173.12:19:24.22#ibcon#about to read 4, iclass 16, count 0 2006.173.12:19:24.22#ibcon#read 4, iclass 16, count 0 2006.173.12:19:24.22#ibcon#about to read 5, iclass 16, count 0 2006.173.12:19:24.22#ibcon#read 5, iclass 16, count 0 2006.173.12:19:24.22#ibcon#about to read 6, iclass 16, count 0 2006.173.12:19:24.22#ibcon#read 6, iclass 16, count 0 2006.173.12:19:24.22#ibcon#end of sib2, iclass 16, count 0 2006.173.12:19:24.22#ibcon#*after write, iclass 16, count 0 2006.173.12:19:24.22#ibcon#*before return 0, iclass 16, count 0 2006.173.12:19:24.22#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.12:19:24.22#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.12:19:24.22#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.12:19:24.22#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.12:19:24.22$vck44/va=7,4 2006.173.12:19:24.22#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.12:19:24.22#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.12:19:24.22#ibcon#ireg 11 cls_cnt 2 2006.173.12:19:24.22#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.12:19:24.28#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.12:19:24.28#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.12:19:24.28#ibcon#enter wrdev, iclass 18, count 2 2006.173.12:19:24.28#ibcon#first serial, iclass 18, count 2 2006.173.12:19:24.28#ibcon#enter sib2, iclass 18, count 2 2006.173.12:19:24.28#ibcon#flushed, iclass 18, count 2 2006.173.12:19:24.28#ibcon#about to write, iclass 18, count 2 2006.173.12:19:24.28#ibcon#wrote, iclass 18, count 2 2006.173.12:19:24.28#ibcon#about to read 3, iclass 18, count 2 2006.173.12:19:24.30#ibcon#read 3, iclass 18, count 2 2006.173.12:19:24.30#ibcon#about to read 4, iclass 18, count 2 2006.173.12:19:24.30#ibcon#read 4, iclass 18, count 2 2006.173.12:19:24.30#ibcon#about to read 5, iclass 18, count 2 2006.173.12:19:24.30#ibcon#read 5, iclass 18, count 2 2006.173.12:19:24.30#ibcon#about to read 6, iclass 18, count 2 2006.173.12:19:24.30#ibcon#read 6, iclass 18, count 2 2006.173.12:19:24.30#ibcon#end of sib2, iclass 18, count 2 2006.173.12:19:24.30#ibcon#*mode == 0, iclass 18, count 2 2006.173.12:19:24.30#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.12:19:24.30#ibcon#[25=AT07-04\r\n] 2006.173.12:19:24.30#ibcon#*before write, iclass 18, count 2 2006.173.12:19:24.30#ibcon#enter sib2, iclass 18, count 2 2006.173.12:19:24.30#ibcon#flushed, iclass 18, count 2 2006.173.12:19:24.30#ibcon#about to write, iclass 18, count 2 2006.173.12:19:24.30#ibcon#wrote, iclass 18, count 2 2006.173.12:19:24.30#ibcon#about to read 3, iclass 18, count 2 2006.173.12:19:24.33#ibcon#read 3, iclass 18, count 2 2006.173.12:19:24.33#ibcon#about to read 4, iclass 18, count 2 2006.173.12:19:24.33#ibcon#read 4, iclass 18, count 2 2006.173.12:19:24.33#ibcon#about to read 5, iclass 18, count 2 2006.173.12:19:24.33#ibcon#read 5, iclass 18, count 2 2006.173.12:19:24.33#ibcon#about to read 6, iclass 18, count 2 2006.173.12:19:24.33#ibcon#read 6, iclass 18, count 2 2006.173.12:19:24.33#ibcon#end of sib2, iclass 18, count 2 2006.173.12:19:24.33#ibcon#*after write, iclass 18, count 2 2006.173.12:19:24.33#ibcon#*before return 0, iclass 18, count 2 2006.173.12:19:24.33#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.12:19:24.33#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.12:19:24.33#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.12:19:24.33#ibcon#ireg 7 cls_cnt 0 2006.173.12:19:24.33#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.12:19:24.45#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.12:19:24.45#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.12:19:24.45#ibcon#enter wrdev, iclass 18, count 0 2006.173.12:19:24.45#ibcon#first serial, iclass 18, count 0 2006.173.12:19:24.45#ibcon#enter sib2, iclass 18, count 0 2006.173.12:19:24.45#ibcon#flushed, iclass 18, count 0 2006.173.12:19:24.45#ibcon#about to write, iclass 18, count 0 2006.173.12:19:24.45#ibcon#wrote, iclass 18, count 0 2006.173.12:19:24.45#ibcon#about to read 3, iclass 18, count 0 2006.173.12:19:24.47#ibcon#read 3, iclass 18, count 0 2006.173.12:19:24.47#ibcon#about to read 4, iclass 18, count 0 2006.173.12:19:24.47#ibcon#read 4, iclass 18, count 0 2006.173.12:19:24.47#ibcon#about to read 5, iclass 18, count 0 2006.173.12:19:24.47#ibcon#read 5, iclass 18, count 0 2006.173.12:19:24.47#ibcon#about to read 6, iclass 18, count 0 2006.173.12:19:24.47#ibcon#read 6, iclass 18, count 0 2006.173.12:19:24.47#ibcon#end of sib2, iclass 18, count 0 2006.173.12:19:24.47#ibcon#*mode == 0, iclass 18, count 0 2006.173.12:19:24.47#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.12:19:24.47#ibcon#[25=USB\r\n] 2006.173.12:19:24.47#ibcon#*before write, iclass 18, count 0 2006.173.12:19:24.47#ibcon#enter sib2, iclass 18, count 0 2006.173.12:19:24.47#ibcon#flushed, iclass 18, count 0 2006.173.12:19:24.47#ibcon#about to write, iclass 18, count 0 2006.173.12:19:24.47#ibcon#wrote, iclass 18, count 0 2006.173.12:19:24.47#ibcon#about to read 3, iclass 18, count 0 2006.173.12:19:24.50#ibcon#read 3, iclass 18, count 0 2006.173.12:19:24.50#ibcon#about to read 4, iclass 18, count 0 2006.173.12:19:24.50#ibcon#read 4, iclass 18, count 0 2006.173.12:19:24.50#ibcon#about to read 5, iclass 18, count 0 2006.173.12:19:24.50#ibcon#read 5, iclass 18, count 0 2006.173.12:19:24.50#ibcon#about to read 6, iclass 18, count 0 2006.173.12:19:24.50#ibcon#read 6, iclass 18, count 0 2006.173.12:19:24.50#ibcon#end of sib2, iclass 18, count 0 2006.173.12:19:24.50#ibcon#*after write, iclass 18, count 0 2006.173.12:19:24.50#ibcon#*before return 0, iclass 18, count 0 2006.173.12:19:24.50#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.12:19:24.50#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.12:19:24.50#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.12:19:24.50#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.12:19:24.50$vck44/valo=8,884.99 2006.173.12:19:24.50#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.12:19:24.50#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.12:19:24.50#ibcon#ireg 17 cls_cnt 0 2006.173.12:19:24.50#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.12:19:24.50#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.12:19:24.50#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.12:19:24.50#ibcon#enter wrdev, iclass 20, count 0 2006.173.12:19:24.50#ibcon#first serial, iclass 20, count 0 2006.173.12:19:24.50#ibcon#enter sib2, iclass 20, count 0 2006.173.12:19:24.50#ibcon#flushed, iclass 20, count 0 2006.173.12:19:24.50#ibcon#about to write, iclass 20, count 0 2006.173.12:19:24.50#ibcon#wrote, iclass 20, count 0 2006.173.12:19:24.50#ibcon#about to read 3, iclass 20, count 0 2006.173.12:19:24.52#ibcon#read 3, iclass 20, count 0 2006.173.12:19:24.52#ibcon#about to read 4, iclass 20, count 0 2006.173.12:19:24.52#ibcon#read 4, iclass 20, count 0 2006.173.12:19:24.52#ibcon#about to read 5, iclass 20, count 0 2006.173.12:19:24.52#ibcon#read 5, iclass 20, count 0 2006.173.12:19:24.52#ibcon#about to read 6, iclass 20, count 0 2006.173.12:19:24.52#ibcon#read 6, iclass 20, count 0 2006.173.12:19:24.52#ibcon#end of sib2, iclass 20, count 0 2006.173.12:19:24.52#ibcon#*mode == 0, iclass 20, count 0 2006.173.12:19:24.52#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.12:19:24.52#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.12:19:24.52#ibcon#*before write, iclass 20, count 0 2006.173.12:19:24.52#ibcon#enter sib2, iclass 20, count 0 2006.173.12:19:24.52#ibcon#flushed, iclass 20, count 0 2006.173.12:19:24.52#ibcon#about to write, iclass 20, count 0 2006.173.12:19:24.52#ibcon#wrote, iclass 20, count 0 2006.173.12:19:24.52#ibcon#about to read 3, iclass 20, count 0 2006.173.12:19:24.56#ibcon#read 3, iclass 20, count 0 2006.173.12:19:24.56#ibcon#about to read 4, iclass 20, count 0 2006.173.12:19:24.56#ibcon#read 4, iclass 20, count 0 2006.173.12:19:24.56#ibcon#about to read 5, iclass 20, count 0 2006.173.12:19:24.56#ibcon#read 5, iclass 20, count 0 2006.173.12:19:24.56#ibcon#about to read 6, iclass 20, count 0 2006.173.12:19:24.56#ibcon#read 6, iclass 20, count 0 2006.173.12:19:24.56#ibcon#end of sib2, iclass 20, count 0 2006.173.12:19:24.56#ibcon#*after write, iclass 20, count 0 2006.173.12:19:24.56#ibcon#*before return 0, iclass 20, count 0 2006.173.12:19:24.56#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.12:19:24.56#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.12:19:24.56#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.12:19:24.56#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.12:19:24.56$vck44/va=8,4 2006.173.12:19:24.56#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.12:19:24.56#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.12:19:24.56#ibcon#ireg 11 cls_cnt 2 2006.173.12:19:24.56#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.12:19:24.62#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.12:19:24.62#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.12:19:24.62#ibcon#enter wrdev, iclass 22, count 2 2006.173.12:19:24.62#ibcon#first serial, iclass 22, count 2 2006.173.12:19:24.62#ibcon#enter sib2, iclass 22, count 2 2006.173.12:19:24.62#ibcon#flushed, iclass 22, count 2 2006.173.12:19:24.62#ibcon#about to write, iclass 22, count 2 2006.173.12:19:24.62#ibcon#wrote, iclass 22, count 2 2006.173.12:19:24.62#ibcon#about to read 3, iclass 22, count 2 2006.173.12:19:24.64#ibcon#read 3, iclass 22, count 2 2006.173.12:19:24.64#ibcon#about to read 4, iclass 22, count 2 2006.173.12:19:24.64#ibcon#read 4, iclass 22, count 2 2006.173.12:19:24.64#ibcon#about to read 5, iclass 22, count 2 2006.173.12:19:24.64#ibcon#read 5, iclass 22, count 2 2006.173.12:19:24.64#ibcon#about to read 6, iclass 22, count 2 2006.173.12:19:24.64#ibcon#read 6, iclass 22, count 2 2006.173.12:19:24.64#ibcon#end of sib2, iclass 22, count 2 2006.173.12:19:24.64#ibcon#*mode == 0, iclass 22, count 2 2006.173.12:19:24.64#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.12:19:24.64#ibcon#[25=AT08-04\r\n] 2006.173.12:19:24.64#ibcon#*before write, iclass 22, count 2 2006.173.12:19:24.64#ibcon#enter sib2, iclass 22, count 2 2006.173.12:19:24.64#ibcon#flushed, iclass 22, count 2 2006.173.12:19:24.64#ibcon#about to write, iclass 22, count 2 2006.173.12:19:24.64#ibcon#wrote, iclass 22, count 2 2006.173.12:19:24.64#ibcon#about to read 3, iclass 22, count 2 2006.173.12:19:24.67#ibcon#read 3, iclass 22, count 2 2006.173.12:19:24.67#ibcon#about to read 4, iclass 22, count 2 2006.173.12:19:24.67#ibcon#read 4, iclass 22, count 2 2006.173.12:19:24.67#ibcon#about to read 5, iclass 22, count 2 2006.173.12:19:24.67#ibcon#read 5, iclass 22, count 2 2006.173.12:19:24.67#ibcon#about to read 6, iclass 22, count 2 2006.173.12:19:24.67#ibcon#read 6, iclass 22, count 2 2006.173.12:19:24.67#ibcon#end of sib2, iclass 22, count 2 2006.173.12:19:24.67#ibcon#*after write, iclass 22, count 2 2006.173.12:19:24.67#ibcon#*before return 0, iclass 22, count 2 2006.173.12:19:24.67#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.12:19:24.67#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.12:19:24.67#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.12:19:24.67#ibcon#ireg 7 cls_cnt 0 2006.173.12:19:24.67#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.12:19:24.79#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.12:19:24.79#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.12:19:24.79#ibcon#enter wrdev, iclass 22, count 0 2006.173.12:19:24.79#ibcon#first serial, iclass 22, count 0 2006.173.12:19:24.79#ibcon#enter sib2, iclass 22, count 0 2006.173.12:19:24.79#ibcon#flushed, iclass 22, count 0 2006.173.12:19:24.79#ibcon#about to write, iclass 22, count 0 2006.173.12:19:24.79#ibcon#wrote, iclass 22, count 0 2006.173.12:19:24.79#ibcon#about to read 3, iclass 22, count 0 2006.173.12:19:24.81#ibcon#read 3, iclass 22, count 0 2006.173.12:19:24.81#ibcon#about to read 4, iclass 22, count 0 2006.173.12:19:24.81#ibcon#read 4, iclass 22, count 0 2006.173.12:19:24.81#ibcon#about to read 5, iclass 22, count 0 2006.173.12:19:24.81#ibcon#read 5, iclass 22, count 0 2006.173.12:19:24.81#ibcon#about to read 6, iclass 22, count 0 2006.173.12:19:24.81#ibcon#read 6, iclass 22, count 0 2006.173.12:19:24.81#ibcon#end of sib2, iclass 22, count 0 2006.173.12:19:24.81#ibcon#*mode == 0, iclass 22, count 0 2006.173.12:19:24.81#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.12:19:24.81#ibcon#[25=USB\r\n] 2006.173.12:19:24.81#ibcon#*before write, iclass 22, count 0 2006.173.12:19:24.81#ibcon#enter sib2, iclass 22, count 0 2006.173.12:19:24.81#ibcon#flushed, iclass 22, count 0 2006.173.12:19:24.81#ibcon#about to write, iclass 22, count 0 2006.173.12:19:24.81#ibcon#wrote, iclass 22, count 0 2006.173.12:19:24.81#ibcon#about to read 3, iclass 22, count 0 2006.173.12:19:24.84#ibcon#read 3, iclass 22, count 0 2006.173.12:19:24.84#ibcon#about to read 4, iclass 22, count 0 2006.173.12:19:24.84#ibcon#read 4, iclass 22, count 0 2006.173.12:19:24.84#ibcon#about to read 5, iclass 22, count 0 2006.173.12:19:24.84#ibcon#read 5, iclass 22, count 0 2006.173.12:19:24.84#ibcon#about to read 6, iclass 22, count 0 2006.173.12:19:24.84#ibcon#read 6, iclass 22, count 0 2006.173.12:19:24.84#ibcon#end of sib2, iclass 22, count 0 2006.173.12:19:24.84#ibcon#*after write, iclass 22, count 0 2006.173.12:19:24.84#ibcon#*before return 0, iclass 22, count 0 2006.173.12:19:24.84#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.12:19:24.84#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.12:19:24.84#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.12:19:24.84#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.12:19:24.84$vck44/vblo=1,629.99 2006.173.12:19:24.84#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.12:19:24.84#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.12:19:24.84#ibcon#ireg 17 cls_cnt 0 2006.173.12:19:24.84#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.12:19:24.84#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.12:19:24.84#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.12:19:24.84#ibcon#enter wrdev, iclass 24, count 0 2006.173.12:19:24.84#ibcon#first serial, iclass 24, count 0 2006.173.12:19:24.84#ibcon#enter sib2, iclass 24, count 0 2006.173.12:19:24.84#ibcon#flushed, iclass 24, count 0 2006.173.12:19:24.84#ibcon#about to write, iclass 24, count 0 2006.173.12:19:24.84#ibcon#wrote, iclass 24, count 0 2006.173.12:19:24.84#ibcon#about to read 3, iclass 24, count 0 2006.173.12:19:24.86#ibcon#read 3, iclass 24, count 0 2006.173.12:19:24.86#ibcon#about to read 4, iclass 24, count 0 2006.173.12:19:24.86#ibcon#read 4, iclass 24, count 0 2006.173.12:19:24.86#ibcon#about to read 5, iclass 24, count 0 2006.173.12:19:24.86#ibcon#read 5, iclass 24, count 0 2006.173.12:19:24.86#ibcon#about to read 6, iclass 24, count 0 2006.173.12:19:24.86#ibcon#read 6, iclass 24, count 0 2006.173.12:19:24.86#ibcon#end of sib2, iclass 24, count 0 2006.173.12:19:24.86#ibcon#*mode == 0, iclass 24, count 0 2006.173.12:19:24.86#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.12:19:24.86#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.12:19:24.86#ibcon#*before write, iclass 24, count 0 2006.173.12:19:24.86#ibcon#enter sib2, iclass 24, count 0 2006.173.12:19:24.86#ibcon#flushed, iclass 24, count 0 2006.173.12:19:24.86#ibcon#about to write, iclass 24, count 0 2006.173.12:19:24.86#ibcon#wrote, iclass 24, count 0 2006.173.12:19:24.86#ibcon#about to read 3, iclass 24, count 0 2006.173.12:19:24.90#ibcon#read 3, iclass 24, count 0 2006.173.12:19:24.90#ibcon#about to read 4, iclass 24, count 0 2006.173.12:19:24.90#ibcon#read 4, iclass 24, count 0 2006.173.12:19:24.90#ibcon#about to read 5, iclass 24, count 0 2006.173.12:19:24.90#ibcon#read 5, iclass 24, count 0 2006.173.12:19:24.90#ibcon#about to read 6, iclass 24, count 0 2006.173.12:19:24.90#ibcon#read 6, iclass 24, count 0 2006.173.12:19:24.90#ibcon#end of sib2, iclass 24, count 0 2006.173.12:19:24.90#ibcon#*after write, iclass 24, count 0 2006.173.12:19:24.90#ibcon#*before return 0, iclass 24, count 0 2006.173.12:19:24.90#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.12:19:24.90#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.12:19:24.90#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.12:19:24.90#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.12:19:24.90$vck44/vb=1,4 2006.173.12:19:24.90#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.12:19:24.90#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.12:19:24.90#ibcon#ireg 11 cls_cnt 2 2006.173.12:19:24.90#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.12:19:24.90#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.12:19:24.90#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.12:19:24.90#ibcon#enter wrdev, iclass 26, count 2 2006.173.12:19:24.90#ibcon#first serial, iclass 26, count 2 2006.173.12:19:24.90#ibcon#enter sib2, iclass 26, count 2 2006.173.12:19:24.90#ibcon#flushed, iclass 26, count 2 2006.173.12:19:24.90#ibcon#about to write, iclass 26, count 2 2006.173.12:19:24.90#ibcon#wrote, iclass 26, count 2 2006.173.12:19:24.90#ibcon#about to read 3, iclass 26, count 2 2006.173.12:19:24.92#ibcon#read 3, iclass 26, count 2 2006.173.12:19:24.92#ibcon#about to read 4, iclass 26, count 2 2006.173.12:19:24.92#ibcon#read 4, iclass 26, count 2 2006.173.12:19:24.92#ibcon#about to read 5, iclass 26, count 2 2006.173.12:19:24.92#ibcon#read 5, iclass 26, count 2 2006.173.12:19:24.92#ibcon#about to read 6, iclass 26, count 2 2006.173.12:19:24.92#ibcon#read 6, iclass 26, count 2 2006.173.12:19:24.92#ibcon#end of sib2, iclass 26, count 2 2006.173.12:19:24.92#ibcon#*mode == 0, iclass 26, count 2 2006.173.12:19:24.92#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.12:19:24.92#ibcon#[27=AT01-04\r\n] 2006.173.12:19:24.92#ibcon#*before write, iclass 26, count 2 2006.173.12:19:24.92#ibcon#enter sib2, iclass 26, count 2 2006.173.12:19:24.92#ibcon#flushed, iclass 26, count 2 2006.173.12:19:24.92#ibcon#about to write, iclass 26, count 2 2006.173.12:19:24.92#ibcon#wrote, iclass 26, count 2 2006.173.12:19:24.92#ibcon#about to read 3, iclass 26, count 2 2006.173.12:19:24.95#ibcon#read 3, iclass 26, count 2 2006.173.12:19:24.95#ibcon#about to read 4, iclass 26, count 2 2006.173.12:19:24.95#ibcon#read 4, iclass 26, count 2 2006.173.12:19:24.95#ibcon#about to read 5, iclass 26, count 2 2006.173.12:19:24.95#ibcon#read 5, iclass 26, count 2 2006.173.12:19:24.95#ibcon#about to read 6, iclass 26, count 2 2006.173.12:19:24.95#ibcon#read 6, iclass 26, count 2 2006.173.12:19:24.95#ibcon#end of sib2, iclass 26, count 2 2006.173.12:19:24.95#ibcon#*after write, iclass 26, count 2 2006.173.12:19:24.95#ibcon#*before return 0, iclass 26, count 2 2006.173.12:19:24.95#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.12:19:24.95#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.12:19:24.95#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.12:19:24.95#ibcon#ireg 7 cls_cnt 0 2006.173.12:19:24.95#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.12:19:25.07#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.12:19:25.07#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.12:19:25.07#ibcon#enter wrdev, iclass 26, count 0 2006.173.12:19:25.07#ibcon#first serial, iclass 26, count 0 2006.173.12:19:25.07#ibcon#enter sib2, iclass 26, count 0 2006.173.12:19:25.07#ibcon#flushed, iclass 26, count 0 2006.173.12:19:25.07#ibcon#about to write, iclass 26, count 0 2006.173.12:19:25.07#ibcon#wrote, iclass 26, count 0 2006.173.12:19:25.07#ibcon#about to read 3, iclass 26, count 0 2006.173.12:19:25.09#ibcon#read 3, iclass 26, count 0 2006.173.12:19:25.09#ibcon#about to read 4, iclass 26, count 0 2006.173.12:19:25.09#ibcon#read 4, iclass 26, count 0 2006.173.12:19:25.09#ibcon#about to read 5, iclass 26, count 0 2006.173.12:19:25.09#ibcon#read 5, iclass 26, count 0 2006.173.12:19:25.09#ibcon#about to read 6, iclass 26, count 0 2006.173.12:19:25.09#ibcon#read 6, iclass 26, count 0 2006.173.12:19:25.09#ibcon#end of sib2, iclass 26, count 0 2006.173.12:19:25.09#ibcon#*mode == 0, iclass 26, count 0 2006.173.12:19:25.09#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.12:19:25.09#ibcon#[27=USB\r\n] 2006.173.12:19:25.09#ibcon#*before write, iclass 26, count 0 2006.173.12:19:25.09#ibcon#enter sib2, iclass 26, count 0 2006.173.12:19:25.09#ibcon#flushed, iclass 26, count 0 2006.173.12:19:25.09#ibcon#about to write, iclass 26, count 0 2006.173.12:19:25.09#ibcon#wrote, iclass 26, count 0 2006.173.12:19:25.09#ibcon#about to read 3, iclass 26, count 0 2006.173.12:19:25.12#ibcon#read 3, iclass 26, count 0 2006.173.12:19:25.12#ibcon#about to read 4, iclass 26, count 0 2006.173.12:19:25.12#ibcon#read 4, iclass 26, count 0 2006.173.12:19:25.12#ibcon#about to read 5, iclass 26, count 0 2006.173.12:19:25.12#ibcon#read 5, iclass 26, count 0 2006.173.12:19:25.12#ibcon#about to read 6, iclass 26, count 0 2006.173.12:19:25.12#ibcon#read 6, iclass 26, count 0 2006.173.12:19:25.12#ibcon#end of sib2, iclass 26, count 0 2006.173.12:19:25.12#ibcon#*after write, iclass 26, count 0 2006.173.12:19:25.12#ibcon#*before return 0, iclass 26, count 0 2006.173.12:19:25.12#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.12:19:25.12#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.12:19:25.12#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.12:19:25.12#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.12:19:25.12$vck44/vblo=2,634.99 2006.173.12:19:25.12#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.12:19:25.12#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.12:19:25.12#ibcon#ireg 17 cls_cnt 0 2006.173.12:19:25.12#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.12:19:25.12#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.12:19:25.12#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.12:19:25.12#ibcon#enter wrdev, iclass 28, count 0 2006.173.12:19:25.12#ibcon#first serial, iclass 28, count 0 2006.173.12:19:25.12#ibcon#enter sib2, iclass 28, count 0 2006.173.12:19:25.12#ibcon#flushed, iclass 28, count 0 2006.173.12:19:25.12#ibcon#about to write, iclass 28, count 0 2006.173.12:19:25.12#ibcon#wrote, iclass 28, count 0 2006.173.12:19:25.12#ibcon#about to read 3, iclass 28, count 0 2006.173.12:19:25.14#ibcon#read 3, iclass 28, count 0 2006.173.12:19:25.14#ibcon#about to read 4, iclass 28, count 0 2006.173.12:19:25.14#ibcon#read 4, iclass 28, count 0 2006.173.12:19:25.14#ibcon#about to read 5, iclass 28, count 0 2006.173.12:19:25.14#ibcon#read 5, iclass 28, count 0 2006.173.12:19:25.14#ibcon#about to read 6, iclass 28, count 0 2006.173.12:19:25.14#ibcon#read 6, iclass 28, count 0 2006.173.12:19:25.14#ibcon#end of sib2, iclass 28, count 0 2006.173.12:19:25.14#ibcon#*mode == 0, iclass 28, count 0 2006.173.12:19:25.14#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.12:19:25.14#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.12:19:25.14#ibcon#*before write, iclass 28, count 0 2006.173.12:19:25.14#ibcon#enter sib2, iclass 28, count 0 2006.173.12:19:25.14#ibcon#flushed, iclass 28, count 0 2006.173.12:19:25.14#ibcon#about to write, iclass 28, count 0 2006.173.12:19:25.14#ibcon#wrote, iclass 28, count 0 2006.173.12:19:25.14#ibcon#about to read 3, iclass 28, count 0 2006.173.12:19:25.18#ibcon#read 3, iclass 28, count 0 2006.173.12:19:25.18#ibcon#about to read 4, iclass 28, count 0 2006.173.12:19:25.18#ibcon#read 4, iclass 28, count 0 2006.173.12:19:25.18#ibcon#about to read 5, iclass 28, count 0 2006.173.12:19:25.18#ibcon#read 5, iclass 28, count 0 2006.173.12:19:25.18#ibcon#about to read 6, iclass 28, count 0 2006.173.12:19:25.18#ibcon#read 6, iclass 28, count 0 2006.173.12:19:25.18#ibcon#end of sib2, iclass 28, count 0 2006.173.12:19:25.18#ibcon#*after write, iclass 28, count 0 2006.173.12:19:25.18#ibcon#*before return 0, iclass 28, count 0 2006.173.12:19:25.18#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.12:19:25.18#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.12:19:25.18#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.12:19:25.18#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.12:19:25.18$vck44/vb=2,4 2006.173.12:19:25.18#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.12:19:25.18#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.12:19:25.18#ibcon#ireg 11 cls_cnt 2 2006.173.12:19:25.18#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.12:19:25.24#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.12:19:25.24#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.12:19:25.24#ibcon#enter wrdev, iclass 30, count 2 2006.173.12:19:25.24#ibcon#first serial, iclass 30, count 2 2006.173.12:19:25.24#ibcon#enter sib2, iclass 30, count 2 2006.173.12:19:25.24#ibcon#flushed, iclass 30, count 2 2006.173.12:19:25.24#ibcon#about to write, iclass 30, count 2 2006.173.12:19:25.24#ibcon#wrote, iclass 30, count 2 2006.173.12:19:25.24#ibcon#about to read 3, iclass 30, count 2 2006.173.12:19:25.26#ibcon#read 3, iclass 30, count 2 2006.173.12:19:25.26#ibcon#about to read 4, iclass 30, count 2 2006.173.12:19:25.26#ibcon#read 4, iclass 30, count 2 2006.173.12:19:25.26#ibcon#about to read 5, iclass 30, count 2 2006.173.12:19:25.26#ibcon#read 5, iclass 30, count 2 2006.173.12:19:25.26#ibcon#about to read 6, iclass 30, count 2 2006.173.12:19:25.26#ibcon#read 6, iclass 30, count 2 2006.173.12:19:25.26#ibcon#end of sib2, iclass 30, count 2 2006.173.12:19:25.26#ibcon#*mode == 0, iclass 30, count 2 2006.173.12:19:25.26#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.12:19:25.26#ibcon#[27=AT02-04\r\n] 2006.173.12:19:25.26#ibcon#*before write, iclass 30, count 2 2006.173.12:19:25.26#ibcon#enter sib2, iclass 30, count 2 2006.173.12:19:25.26#ibcon#flushed, iclass 30, count 2 2006.173.12:19:25.26#ibcon#about to write, iclass 30, count 2 2006.173.12:19:25.26#ibcon#wrote, iclass 30, count 2 2006.173.12:19:25.26#ibcon#about to read 3, iclass 30, count 2 2006.173.12:19:25.29#ibcon#read 3, iclass 30, count 2 2006.173.12:19:25.29#ibcon#about to read 4, iclass 30, count 2 2006.173.12:19:25.29#ibcon#read 4, iclass 30, count 2 2006.173.12:19:25.29#ibcon#about to read 5, iclass 30, count 2 2006.173.12:19:25.29#ibcon#read 5, iclass 30, count 2 2006.173.12:19:25.29#ibcon#about to read 6, iclass 30, count 2 2006.173.12:19:25.29#ibcon#read 6, iclass 30, count 2 2006.173.12:19:25.29#ibcon#end of sib2, iclass 30, count 2 2006.173.12:19:25.29#ibcon#*after write, iclass 30, count 2 2006.173.12:19:25.29#ibcon#*before return 0, iclass 30, count 2 2006.173.12:19:25.29#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.12:19:25.29#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.12:19:25.29#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.12:19:25.29#ibcon#ireg 7 cls_cnt 0 2006.173.12:19:25.29#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.12:19:25.41#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.12:19:25.41#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.12:19:25.41#ibcon#enter wrdev, iclass 30, count 0 2006.173.12:19:25.41#ibcon#first serial, iclass 30, count 0 2006.173.12:19:25.41#ibcon#enter sib2, iclass 30, count 0 2006.173.12:19:25.41#ibcon#flushed, iclass 30, count 0 2006.173.12:19:25.41#ibcon#about to write, iclass 30, count 0 2006.173.12:19:25.41#ibcon#wrote, iclass 30, count 0 2006.173.12:19:25.41#ibcon#about to read 3, iclass 30, count 0 2006.173.12:19:25.43#ibcon#read 3, iclass 30, count 0 2006.173.12:19:25.43#ibcon#about to read 4, iclass 30, count 0 2006.173.12:19:25.43#ibcon#read 4, iclass 30, count 0 2006.173.12:19:25.43#ibcon#about to read 5, iclass 30, count 0 2006.173.12:19:25.43#ibcon#read 5, iclass 30, count 0 2006.173.12:19:25.43#ibcon#about to read 6, iclass 30, count 0 2006.173.12:19:25.43#ibcon#read 6, iclass 30, count 0 2006.173.12:19:25.43#ibcon#end of sib2, iclass 30, count 0 2006.173.12:19:25.43#ibcon#*mode == 0, iclass 30, count 0 2006.173.12:19:25.43#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.12:19:25.43#ibcon#[27=USB\r\n] 2006.173.12:19:25.43#ibcon#*before write, iclass 30, count 0 2006.173.12:19:25.43#ibcon#enter sib2, iclass 30, count 0 2006.173.12:19:25.43#ibcon#flushed, iclass 30, count 0 2006.173.12:19:25.43#ibcon#about to write, iclass 30, count 0 2006.173.12:19:25.43#ibcon#wrote, iclass 30, count 0 2006.173.12:19:25.43#ibcon#about to read 3, iclass 30, count 0 2006.173.12:19:25.46#ibcon#read 3, iclass 30, count 0 2006.173.12:19:25.46#ibcon#about to read 4, iclass 30, count 0 2006.173.12:19:25.46#ibcon#read 4, iclass 30, count 0 2006.173.12:19:25.46#ibcon#about to read 5, iclass 30, count 0 2006.173.12:19:25.46#ibcon#read 5, iclass 30, count 0 2006.173.12:19:25.46#ibcon#about to read 6, iclass 30, count 0 2006.173.12:19:25.46#ibcon#read 6, iclass 30, count 0 2006.173.12:19:25.46#ibcon#end of sib2, iclass 30, count 0 2006.173.12:19:25.46#ibcon#*after write, iclass 30, count 0 2006.173.12:19:25.46#ibcon#*before return 0, iclass 30, count 0 2006.173.12:19:25.46#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.12:19:25.46#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.12:19:25.46#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.12:19:25.46#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.12:19:25.46$vck44/vblo=3,649.99 2006.173.12:19:25.46#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.12:19:25.46#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.12:19:25.46#ibcon#ireg 17 cls_cnt 0 2006.173.12:19:25.46#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.12:19:25.46#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.12:19:25.46#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.12:19:25.46#ibcon#enter wrdev, iclass 32, count 0 2006.173.12:19:25.46#ibcon#first serial, iclass 32, count 0 2006.173.12:19:25.46#ibcon#enter sib2, iclass 32, count 0 2006.173.12:19:25.46#ibcon#flushed, iclass 32, count 0 2006.173.12:19:25.46#ibcon#about to write, iclass 32, count 0 2006.173.12:19:25.46#ibcon#wrote, iclass 32, count 0 2006.173.12:19:25.46#ibcon#about to read 3, iclass 32, count 0 2006.173.12:19:25.48#ibcon#read 3, iclass 32, count 0 2006.173.12:19:25.48#ibcon#about to read 4, iclass 32, count 0 2006.173.12:19:25.48#ibcon#read 4, iclass 32, count 0 2006.173.12:19:25.48#ibcon#about to read 5, iclass 32, count 0 2006.173.12:19:25.48#ibcon#read 5, iclass 32, count 0 2006.173.12:19:25.48#ibcon#about to read 6, iclass 32, count 0 2006.173.12:19:25.48#ibcon#read 6, iclass 32, count 0 2006.173.12:19:25.48#ibcon#end of sib2, iclass 32, count 0 2006.173.12:19:25.48#ibcon#*mode == 0, iclass 32, count 0 2006.173.12:19:25.48#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.12:19:25.48#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.12:19:25.48#ibcon#*before write, iclass 32, count 0 2006.173.12:19:25.48#ibcon#enter sib2, iclass 32, count 0 2006.173.12:19:25.48#ibcon#flushed, iclass 32, count 0 2006.173.12:19:25.48#ibcon#about to write, iclass 32, count 0 2006.173.12:19:25.48#ibcon#wrote, iclass 32, count 0 2006.173.12:19:25.48#ibcon#about to read 3, iclass 32, count 0 2006.173.12:19:25.52#ibcon#read 3, iclass 32, count 0 2006.173.12:19:25.52#ibcon#about to read 4, iclass 32, count 0 2006.173.12:19:25.52#ibcon#read 4, iclass 32, count 0 2006.173.12:19:25.52#ibcon#about to read 5, iclass 32, count 0 2006.173.12:19:25.52#ibcon#read 5, iclass 32, count 0 2006.173.12:19:25.52#ibcon#about to read 6, iclass 32, count 0 2006.173.12:19:25.52#ibcon#read 6, iclass 32, count 0 2006.173.12:19:25.52#ibcon#end of sib2, iclass 32, count 0 2006.173.12:19:25.52#ibcon#*after write, iclass 32, count 0 2006.173.12:19:25.52#ibcon#*before return 0, iclass 32, count 0 2006.173.12:19:25.52#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.12:19:25.52#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.12:19:25.52#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.12:19:25.52#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.12:19:25.52$vck44/vb=3,4 2006.173.12:19:25.52#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.12:19:25.52#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.12:19:25.52#ibcon#ireg 11 cls_cnt 2 2006.173.12:19:25.52#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.12:19:25.58#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.12:19:25.58#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.12:19:25.58#ibcon#enter wrdev, iclass 34, count 2 2006.173.12:19:25.58#ibcon#first serial, iclass 34, count 2 2006.173.12:19:25.58#ibcon#enter sib2, iclass 34, count 2 2006.173.12:19:25.58#ibcon#flushed, iclass 34, count 2 2006.173.12:19:25.58#ibcon#about to write, iclass 34, count 2 2006.173.12:19:25.58#ibcon#wrote, iclass 34, count 2 2006.173.12:19:25.58#ibcon#about to read 3, iclass 34, count 2 2006.173.12:19:25.60#ibcon#read 3, iclass 34, count 2 2006.173.12:19:25.60#ibcon#about to read 4, iclass 34, count 2 2006.173.12:19:25.60#ibcon#read 4, iclass 34, count 2 2006.173.12:19:25.60#ibcon#about to read 5, iclass 34, count 2 2006.173.12:19:25.60#ibcon#read 5, iclass 34, count 2 2006.173.12:19:25.60#ibcon#about to read 6, iclass 34, count 2 2006.173.12:19:25.60#ibcon#read 6, iclass 34, count 2 2006.173.12:19:25.60#ibcon#end of sib2, iclass 34, count 2 2006.173.12:19:25.60#ibcon#*mode == 0, iclass 34, count 2 2006.173.12:19:25.60#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.12:19:25.60#ibcon#[27=AT03-04\r\n] 2006.173.12:19:25.60#ibcon#*before write, iclass 34, count 2 2006.173.12:19:25.60#ibcon#enter sib2, iclass 34, count 2 2006.173.12:19:25.60#ibcon#flushed, iclass 34, count 2 2006.173.12:19:25.60#ibcon#about to write, iclass 34, count 2 2006.173.12:19:25.60#ibcon#wrote, iclass 34, count 2 2006.173.12:19:25.60#ibcon#about to read 3, iclass 34, count 2 2006.173.12:19:25.63#ibcon#read 3, iclass 34, count 2 2006.173.12:19:25.63#ibcon#about to read 4, iclass 34, count 2 2006.173.12:19:25.63#ibcon#read 4, iclass 34, count 2 2006.173.12:19:25.63#ibcon#about to read 5, iclass 34, count 2 2006.173.12:19:25.63#ibcon#read 5, iclass 34, count 2 2006.173.12:19:25.63#ibcon#about to read 6, iclass 34, count 2 2006.173.12:19:25.63#ibcon#read 6, iclass 34, count 2 2006.173.12:19:25.63#ibcon#end of sib2, iclass 34, count 2 2006.173.12:19:25.63#ibcon#*after write, iclass 34, count 2 2006.173.12:19:25.63#ibcon#*before return 0, iclass 34, count 2 2006.173.12:19:25.63#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.12:19:25.63#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.12:19:25.63#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.12:19:25.63#ibcon#ireg 7 cls_cnt 0 2006.173.12:19:25.63#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.12:19:25.75#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.12:19:25.75#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.12:19:25.75#ibcon#enter wrdev, iclass 34, count 0 2006.173.12:19:25.75#ibcon#first serial, iclass 34, count 0 2006.173.12:19:25.75#ibcon#enter sib2, iclass 34, count 0 2006.173.12:19:25.75#ibcon#flushed, iclass 34, count 0 2006.173.12:19:25.75#ibcon#about to write, iclass 34, count 0 2006.173.12:19:25.75#ibcon#wrote, iclass 34, count 0 2006.173.12:19:25.75#ibcon#about to read 3, iclass 34, count 0 2006.173.12:19:25.77#ibcon#read 3, iclass 34, count 0 2006.173.12:19:25.77#ibcon#about to read 4, iclass 34, count 0 2006.173.12:19:25.77#ibcon#read 4, iclass 34, count 0 2006.173.12:19:25.77#ibcon#about to read 5, iclass 34, count 0 2006.173.12:19:25.77#ibcon#read 5, iclass 34, count 0 2006.173.12:19:25.77#ibcon#about to read 6, iclass 34, count 0 2006.173.12:19:25.77#ibcon#read 6, iclass 34, count 0 2006.173.12:19:25.77#ibcon#end of sib2, iclass 34, count 0 2006.173.12:19:25.77#ibcon#*mode == 0, iclass 34, count 0 2006.173.12:19:25.77#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.12:19:25.77#ibcon#[27=USB\r\n] 2006.173.12:19:25.77#ibcon#*before write, iclass 34, count 0 2006.173.12:19:25.77#ibcon#enter sib2, iclass 34, count 0 2006.173.12:19:25.77#ibcon#flushed, iclass 34, count 0 2006.173.12:19:25.77#ibcon#about to write, iclass 34, count 0 2006.173.12:19:25.77#ibcon#wrote, iclass 34, count 0 2006.173.12:19:25.77#ibcon#about to read 3, iclass 34, count 0 2006.173.12:19:25.80#ibcon#read 3, iclass 34, count 0 2006.173.12:19:25.80#ibcon#about to read 4, iclass 34, count 0 2006.173.12:19:25.80#ibcon#read 4, iclass 34, count 0 2006.173.12:19:25.80#ibcon#about to read 5, iclass 34, count 0 2006.173.12:19:25.80#ibcon#read 5, iclass 34, count 0 2006.173.12:19:25.80#ibcon#about to read 6, iclass 34, count 0 2006.173.12:19:25.80#ibcon#read 6, iclass 34, count 0 2006.173.12:19:25.80#ibcon#end of sib2, iclass 34, count 0 2006.173.12:19:25.80#ibcon#*after write, iclass 34, count 0 2006.173.12:19:25.80#ibcon#*before return 0, iclass 34, count 0 2006.173.12:19:25.80#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.12:19:25.80#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.12:19:25.80#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.12:19:25.80#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.12:19:25.80$vck44/vblo=4,679.99 2006.173.12:19:25.80#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.12:19:25.80#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.12:19:25.80#ibcon#ireg 17 cls_cnt 0 2006.173.12:19:25.80#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.12:19:25.80#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.12:19:25.80#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.12:19:25.80#ibcon#enter wrdev, iclass 36, count 0 2006.173.12:19:25.80#ibcon#first serial, iclass 36, count 0 2006.173.12:19:25.80#ibcon#enter sib2, iclass 36, count 0 2006.173.12:19:25.80#ibcon#flushed, iclass 36, count 0 2006.173.12:19:25.80#ibcon#about to write, iclass 36, count 0 2006.173.12:19:25.80#ibcon#wrote, iclass 36, count 0 2006.173.12:19:25.80#ibcon#about to read 3, iclass 36, count 0 2006.173.12:19:25.82#ibcon#read 3, iclass 36, count 0 2006.173.12:19:25.82#ibcon#about to read 4, iclass 36, count 0 2006.173.12:19:25.82#ibcon#read 4, iclass 36, count 0 2006.173.12:19:25.82#ibcon#about to read 5, iclass 36, count 0 2006.173.12:19:25.82#ibcon#read 5, iclass 36, count 0 2006.173.12:19:25.82#ibcon#about to read 6, iclass 36, count 0 2006.173.12:19:25.82#ibcon#read 6, iclass 36, count 0 2006.173.12:19:25.82#ibcon#end of sib2, iclass 36, count 0 2006.173.12:19:25.82#ibcon#*mode == 0, iclass 36, count 0 2006.173.12:19:25.82#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.12:19:25.82#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.12:19:25.82#ibcon#*before write, iclass 36, count 0 2006.173.12:19:25.82#ibcon#enter sib2, iclass 36, count 0 2006.173.12:19:25.82#ibcon#flushed, iclass 36, count 0 2006.173.12:19:25.82#ibcon#about to write, iclass 36, count 0 2006.173.12:19:25.82#ibcon#wrote, iclass 36, count 0 2006.173.12:19:25.82#ibcon#about to read 3, iclass 36, count 0 2006.173.12:19:25.86#ibcon#read 3, iclass 36, count 0 2006.173.12:19:25.86#ibcon#about to read 4, iclass 36, count 0 2006.173.12:19:25.86#ibcon#read 4, iclass 36, count 0 2006.173.12:19:25.86#ibcon#about to read 5, iclass 36, count 0 2006.173.12:19:25.86#ibcon#read 5, iclass 36, count 0 2006.173.12:19:25.86#ibcon#about to read 6, iclass 36, count 0 2006.173.12:19:25.86#ibcon#read 6, iclass 36, count 0 2006.173.12:19:25.86#ibcon#end of sib2, iclass 36, count 0 2006.173.12:19:25.86#ibcon#*after write, iclass 36, count 0 2006.173.12:19:25.86#ibcon#*before return 0, iclass 36, count 0 2006.173.12:19:25.86#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.12:19:25.86#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.12:19:25.86#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.12:19:25.86#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.12:19:25.86$vck44/vb=4,4 2006.173.12:19:25.86#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.12:19:25.86#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.12:19:25.86#ibcon#ireg 11 cls_cnt 2 2006.173.12:19:25.86#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.12:19:25.92#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.12:19:25.92#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.12:19:25.92#ibcon#enter wrdev, iclass 38, count 2 2006.173.12:19:25.92#ibcon#first serial, iclass 38, count 2 2006.173.12:19:25.92#ibcon#enter sib2, iclass 38, count 2 2006.173.12:19:25.92#ibcon#flushed, iclass 38, count 2 2006.173.12:19:25.92#ibcon#about to write, iclass 38, count 2 2006.173.12:19:25.92#ibcon#wrote, iclass 38, count 2 2006.173.12:19:25.92#ibcon#about to read 3, iclass 38, count 2 2006.173.12:19:25.94#ibcon#read 3, iclass 38, count 2 2006.173.12:19:25.94#ibcon#about to read 4, iclass 38, count 2 2006.173.12:19:25.94#ibcon#read 4, iclass 38, count 2 2006.173.12:19:25.94#ibcon#about to read 5, iclass 38, count 2 2006.173.12:19:25.94#ibcon#read 5, iclass 38, count 2 2006.173.12:19:25.94#ibcon#about to read 6, iclass 38, count 2 2006.173.12:19:25.94#ibcon#read 6, iclass 38, count 2 2006.173.12:19:25.94#ibcon#end of sib2, iclass 38, count 2 2006.173.12:19:25.94#ibcon#*mode == 0, iclass 38, count 2 2006.173.12:19:25.94#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.12:19:25.94#ibcon#[27=AT04-04\r\n] 2006.173.12:19:25.94#ibcon#*before write, iclass 38, count 2 2006.173.12:19:25.94#ibcon#enter sib2, iclass 38, count 2 2006.173.12:19:25.94#ibcon#flushed, iclass 38, count 2 2006.173.12:19:25.94#ibcon#about to write, iclass 38, count 2 2006.173.12:19:25.94#ibcon#wrote, iclass 38, count 2 2006.173.12:19:25.94#ibcon#about to read 3, iclass 38, count 2 2006.173.12:19:25.97#ibcon#read 3, iclass 38, count 2 2006.173.12:19:25.97#ibcon#about to read 4, iclass 38, count 2 2006.173.12:19:25.97#ibcon#read 4, iclass 38, count 2 2006.173.12:19:25.97#ibcon#about to read 5, iclass 38, count 2 2006.173.12:19:25.97#ibcon#read 5, iclass 38, count 2 2006.173.12:19:25.97#ibcon#about to read 6, iclass 38, count 2 2006.173.12:19:25.97#ibcon#read 6, iclass 38, count 2 2006.173.12:19:25.97#ibcon#end of sib2, iclass 38, count 2 2006.173.12:19:25.97#ibcon#*after write, iclass 38, count 2 2006.173.12:19:25.97#ibcon#*before return 0, iclass 38, count 2 2006.173.12:19:25.97#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.12:19:25.97#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.12:19:25.97#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.12:19:25.97#ibcon#ireg 7 cls_cnt 0 2006.173.12:19:25.97#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.12:19:26.09#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.12:19:26.09#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.12:19:26.09#ibcon#enter wrdev, iclass 38, count 0 2006.173.12:19:26.09#ibcon#first serial, iclass 38, count 0 2006.173.12:19:26.09#ibcon#enter sib2, iclass 38, count 0 2006.173.12:19:26.09#ibcon#flushed, iclass 38, count 0 2006.173.12:19:26.09#ibcon#about to write, iclass 38, count 0 2006.173.12:19:26.09#ibcon#wrote, iclass 38, count 0 2006.173.12:19:26.09#ibcon#about to read 3, iclass 38, count 0 2006.173.12:19:26.11#ibcon#read 3, iclass 38, count 0 2006.173.12:19:26.11#ibcon#about to read 4, iclass 38, count 0 2006.173.12:19:26.11#ibcon#read 4, iclass 38, count 0 2006.173.12:19:26.11#ibcon#about to read 5, iclass 38, count 0 2006.173.12:19:26.11#ibcon#read 5, iclass 38, count 0 2006.173.12:19:26.11#ibcon#about to read 6, iclass 38, count 0 2006.173.12:19:26.11#ibcon#read 6, iclass 38, count 0 2006.173.12:19:26.11#ibcon#end of sib2, iclass 38, count 0 2006.173.12:19:26.11#ibcon#*mode == 0, iclass 38, count 0 2006.173.12:19:26.11#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.12:19:26.11#ibcon#[27=USB\r\n] 2006.173.12:19:26.11#ibcon#*before write, iclass 38, count 0 2006.173.12:19:26.11#ibcon#enter sib2, iclass 38, count 0 2006.173.12:19:26.11#ibcon#flushed, iclass 38, count 0 2006.173.12:19:26.11#ibcon#about to write, iclass 38, count 0 2006.173.12:19:26.11#ibcon#wrote, iclass 38, count 0 2006.173.12:19:26.11#ibcon#about to read 3, iclass 38, count 0 2006.173.12:19:26.14#ibcon#read 3, iclass 38, count 0 2006.173.12:19:26.14#ibcon#about to read 4, iclass 38, count 0 2006.173.12:19:26.14#ibcon#read 4, iclass 38, count 0 2006.173.12:19:26.14#ibcon#about to read 5, iclass 38, count 0 2006.173.12:19:26.14#ibcon#read 5, iclass 38, count 0 2006.173.12:19:26.14#ibcon#about to read 6, iclass 38, count 0 2006.173.12:19:26.14#ibcon#read 6, iclass 38, count 0 2006.173.12:19:26.14#ibcon#end of sib2, iclass 38, count 0 2006.173.12:19:26.14#ibcon#*after write, iclass 38, count 0 2006.173.12:19:26.14#ibcon#*before return 0, iclass 38, count 0 2006.173.12:19:26.14#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.12:19:26.14#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.12:19:26.14#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.12:19:26.14#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.12:19:26.15$vck44/vblo=5,709.99 2006.173.12:19:26.15#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.12:19:26.15#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.12:19:26.15#ibcon#ireg 17 cls_cnt 0 2006.173.12:19:26.15#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.12:19:26.15#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.12:19:26.15#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.12:19:26.15#ibcon#enter wrdev, iclass 40, count 0 2006.173.12:19:26.15#ibcon#first serial, iclass 40, count 0 2006.173.12:19:26.15#ibcon#enter sib2, iclass 40, count 0 2006.173.12:19:26.15#ibcon#flushed, iclass 40, count 0 2006.173.12:19:26.15#ibcon#about to write, iclass 40, count 0 2006.173.12:19:26.15#ibcon#wrote, iclass 40, count 0 2006.173.12:19:26.15#ibcon#about to read 3, iclass 40, count 0 2006.173.12:19:26.16#ibcon#read 3, iclass 40, count 0 2006.173.12:19:26.16#ibcon#about to read 4, iclass 40, count 0 2006.173.12:19:26.16#ibcon#read 4, iclass 40, count 0 2006.173.12:19:26.16#ibcon#about to read 5, iclass 40, count 0 2006.173.12:19:26.16#ibcon#read 5, iclass 40, count 0 2006.173.12:19:26.16#ibcon#about to read 6, iclass 40, count 0 2006.173.12:19:26.16#ibcon#read 6, iclass 40, count 0 2006.173.12:19:26.16#ibcon#end of sib2, iclass 40, count 0 2006.173.12:19:26.16#ibcon#*mode == 0, iclass 40, count 0 2006.173.12:19:26.16#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.12:19:26.16#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.12:19:26.16#ibcon#*before write, iclass 40, count 0 2006.173.12:19:26.16#ibcon#enter sib2, iclass 40, count 0 2006.173.12:19:26.16#ibcon#flushed, iclass 40, count 0 2006.173.12:19:26.16#ibcon#about to write, iclass 40, count 0 2006.173.12:19:26.16#ibcon#wrote, iclass 40, count 0 2006.173.12:19:26.16#ibcon#about to read 3, iclass 40, count 0 2006.173.12:19:26.20#ibcon#read 3, iclass 40, count 0 2006.173.12:19:26.20#ibcon#about to read 4, iclass 40, count 0 2006.173.12:19:26.20#ibcon#read 4, iclass 40, count 0 2006.173.12:19:26.20#ibcon#about to read 5, iclass 40, count 0 2006.173.12:19:26.20#ibcon#read 5, iclass 40, count 0 2006.173.12:19:26.20#ibcon#about to read 6, iclass 40, count 0 2006.173.12:19:26.20#ibcon#read 6, iclass 40, count 0 2006.173.12:19:26.20#ibcon#end of sib2, iclass 40, count 0 2006.173.12:19:26.20#ibcon#*after write, iclass 40, count 0 2006.173.12:19:26.20#ibcon#*before return 0, iclass 40, count 0 2006.173.12:19:26.20#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.12:19:26.20#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.12:19:26.20#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.12:19:26.20#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.12:19:26.20$vck44/vb=5,4 2006.173.12:19:26.20#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.12:19:26.20#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.12:19:26.20#ibcon#ireg 11 cls_cnt 2 2006.173.12:19:26.20#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.12:19:26.26#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.12:19:26.26#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.12:19:26.26#ibcon#enter wrdev, iclass 4, count 2 2006.173.12:19:26.26#ibcon#first serial, iclass 4, count 2 2006.173.12:19:26.26#ibcon#enter sib2, iclass 4, count 2 2006.173.12:19:26.26#ibcon#flushed, iclass 4, count 2 2006.173.12:19:26.26#ibcon#about to write, iclass 4, count 2 2006.173.12:19:26.26#ibcon#wrote, iclass 4, count 2 2006.173.12:19:26.26#ibcon#about to read 3, iclass 4, count 2 2006.173.12:19:26.28#ibcon#read 3, iclass 4, count 2 2006.173.12:19:26.28#ibcon#about to read 4, iclass 4, count 2 2006.173.12:19:26.28#ibcon#read 4, iclass 4, count 2 2006.173.12:19:26.28#ibcon#about to read 5, iclass 4, count 2 2006.173.12:19:26.28#ibcon#read 5, iclass 4, count 2 2006.173.12:19:26.28#ibcon#about to read 6, iclass 4, count 2 2006.173.12:19:26.28#ibcon#read 6, iclass 4, count 2 2006.173.12:19:26.28#ibcon#end of sib2, iclass 4, count 2 2006.173.12:19:26.28#ibcon#*mode == 0, iclass 4, count 2 2006.173.12:19:26.28#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.12:19:26.28#ibcon#[27=AT05-04\r\n] 2006.173.12:19:26.28#ibcon#*before write, iclass 4, count 2 2006.173.12:19:26.28#ibcon#enter sib2, iclass 4, count 2 2006.173.12:19:26.28#ibcon#flushed, iclass 4, count 2 2006.173.12:19:26.28#ibcon#about to write, iclass 4, count 2 2006.173.12:19:26.28#ibcon#wrote, iclass 4, count 2 2006.173.12:19:26.28#ibcon#about to read 3, iclass 4, count 2 2006.173.12:19:26.31#ibcon#read 3, iclass 4, count 2 2006.173.12:19:26.31#ibcon#about to read 4, iclass 4, count 2 2006.173.12:19:26.31#ibcon#read 4, iclass 4, count 2 2006.173.12:19:26.31#ibcon#about to read 5, iclass 4, count 2 2006.173.12:19:26.31#ibcon#read 5, iclass 4, count 2 2006.173.12:19:26.31#ibcon#about to read 6, iclass 4, count 2 2006.173.12:19:26.31#ibcon#read 6, iclass 4, count 2 2006.173.12:19:26.31#ibcon#end of sib2, iclass 4, count 2 2006.173.12:19:26.31#ibcon#*after write, iclass 4, count 2 2006.173.12:19:26.31#ibcon#*before return 0, iclass 4, count 2 2006.173.12:19:26.31#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.12:19:26.31#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.12:19:26.31#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.12:19:26.31#ibcon#ireg 7 cls_cnt 0 2006.173.12:19:26.31#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.12:19:26.43#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.12:19:26.43#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.12:19:26.43#ibcon#enter wrdev, iclass 4, count 0 2006.173.12:19:26.43#ibcon#first serial, iclass 4, count 0 2006.173.12:19:26.43#ibcon#enter sib2, iclass 4, count 0 2006.173.12:19:26.43#ibcon#flushed, iclass 4, count 0 2006.173.12:19:26.43#ibcon#about to write, iclass 4, count 0 2006.173.12:19:26.43#ibcon#wrote, iclass 4, count 0 2006.173.12:19:26.43#ibcon#about to read 3, iclass 4, count 0 2006.173.12:19:26.45#ibcon#read 3, iclass 4, count 0 2006.173.12:19:26.45#ibcon#about to read 4, iclass 4, count 0 2006.173.12:19:26.45#ibcon#read 4, iclass 4, count 0 2006.173.12:19:26.45#ibcon#about to read 5, iclass 4, count 0 2006.173.12:19:26.45#ibcon#read 5, iclass 4, count 0 2006.173.12:19:26.45#ibcon#about to read 6, iclass 4, count 0 2006.173.12:19:26.45#ibcon#read 6, iclass 4, count 0 2006.173.12:19:26.45#ibcon#end of sib2, iclass 4, count 0 2006.173.12:19:26.45#ibcon#*mode == 0, iclass 4, count 0 2006.173.12:19:26.45#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.12:19:26.45#ibcon#[27=USB\r\n] 2006.173.12:19:26.45#ibcon#*before write, iclass 4, count 0 2006.173.12:19:26.45#ibcon#enter sib2, iclass 4, count 0 2006.173.12:19:26.45#ibcon#flushed, iclass 4, count 0 2006.173.12:19:26.45#ibcon#about to write, iclass 4, count 0 2006.173.12:19:26.45#ibcon#wrote, iclass 4, count 0 2006.173.12:19:26.45#ibcon#about to read 3, iclass 4, count 0 2006.173.12:19:26.48#ibcon#read 3, iclass 4, count 0 2006.173.12:19:26.48#ibcon#about to read 4, iclass 4, count 0 2006.173.12:19:26.48#ibcon#read 4, iclass 4, count 0 2006.173.12:19:26.48#ibcon#about to read 5, iclass 4, count 0 2006.173.12:19:26.48#ibcon#read 5, iclass 4, count 0 2006.173.12:19:26.48#ibcon#about to read 6, iclass 4, count 0 2006.173.12:19:26.48#ibcon#read 6, iclass 4, count 0 2006.173.12:19:26.48#ibcon#end of sib2, iclass 4, count 0 2006.173.12:19:26.48#ibcon#*after write, iclass 4, count 0 2006.173.12:19:26.48#ibcon#*before return 0, iclass 4, count 0 2006.173.12:19:26.48#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.12:19:26.48#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.12:19:26.48#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.12:19:26.48#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.12:19:26.48$vck44/vblo=6,719.99 2006.173.12:19:26.48#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.12:19:26.48#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.12:19:26.48#ibcon#ireg 17 cls_cnt 0 2006.173.12:19:26.48#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.12:19:26.48#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.12:19:26.48#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.12:19:26.48#ibcon#enter wrdev, iclass 6, count 0 2006.173.12:19:26.48#ibcon#first serial, iclass 6, count 0 2006.173.12:19:26.48#ibcon#enter sib2, iclass 6, count 0 2006.173.12:19:26.48#ibcon#flushed, iclass 6, count 0 2006.173.12:19:26.48#ibcon#about to write, iclass 6, count 0 2006.173.12:19:26.48#ibcon#wrote, iclass 6, count 0 2006.173.12:19:26.48#ibcon#about to read 3, iclass 6, count 0 2006.173.12:19:26.50#ibcon#read 3, iclass 6, count 0 2006.173.12:19:26.50#ibcon#about to read 4, iclass 6, count 0 2006.173.12:19:26.50#ibcon#read 4, iclass 6, count 0 2006.173.12:19:26.50#ibcon#about to read 5, iclass 6, count 0 2006.173.12:19:26.50#ibcon#read 5, iclass 6, count 0 2006.173.12:19:26.50#ibcon#about to read 6, iclass 6, count 0 2006.173.12:19:26.50#ibcon#read 6, iclass 6, count 0 2006.173.12:19:26.50#ibcon#end of sib2, iclass 6, count 0 2006.173.12:19:26.50#ibcon#*mode == 0, iclass 6, count 0 2006.173.12:19:26.50#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.12:19:26.50#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.12:19:26.50#ibcon#*before write, iclass 6, count 0 2006.173.12:19:26.50#ibcon#enter sib2, iclass 6, count 0 2006.173.12:19:26.50#ibcon#flushed, iclass 6, count 0 2006.173.12:19:26.50#ibcon#about to write, iclass 6, count 0 2006.173.12:19:26.50#ibcon#wrote, iclass 6, count 0 2006.173.12:19:26.50#ibcon#about to read 3, iclass 6, count 0 2006.173.12:19:26.54#ibcon#read 3, iclass 6, count 0 2006.173.12:19:26.54#ibcon#about to read 4, iclass 6, count 0 2006.173.12:19:26.54#ibcon#read 4, iclass 6, count 0 2006.173.12:19:26.54#ibcon#about to read 5, iclass 6, count 0 2006.173.12:19:26.54#ibcon#read 5, iclass 6, count 0 2006.173.12:19:26.54#ibcon#about to read 6, iclass 6, count 0 2006.173.12:19:26.54#ibcon#read 6, iclass 6, count 0 2006.173.12:19:26.54#ibcon#end of sib2, iclass 6, count 0 2006.173.12:19:26.54#ibcon#*after write, iclass 6, count 0 2006.173.12:19:26.54#ibcon#*before return 0, iclass 6, count 0 2006.173.12:19:26.54#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.12:19:26.54#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.12:19:26.54#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.12:19:26.54#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.12:19:26.54$vck44/vb=6,4 2006.173.12:19:26.54#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.12:19:26.54#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.12:19:26.54#ibcon#ireg 11 cls_cnt 2 2006.173.12:19:26.54#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.12:19:26.60#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.12:19:26.60#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.12:19:26.60#ibcon#enter wrdev, iclass 10, count 2 2006.173.12:19:26.60#ibcon#first serial, iclass 10, count 2 2006.173.12:19:26.60#ibcon#enter sib2, iclass 10, count 2 2006.173.12:19:26.60#ibcon#flushed, iclass 10, count 2 2006.173.12:19:26.60#ibcon#about to write, iclass 10, count 2 2006.173.12:19:26.60#ibcon#wrote, iclass 10, count 2 2006.173.12:19:26.60#ibcon#about to read 3, iclass 10, count 2 2006.173.12:19:26.62#ibcon#read 3, iclass 10, count 2 2006.173.12:19:26.62#ibcon#about to read 4, iclass 10, count 2 2006.173.12:19:26.62#ibcon#read 4, iclass 10, count 2 2006.173.12:19:26.62#ibcon#about to read 5, iclass 10, count 2 2006.173.12:19:26.62#ibcon#read 5, iclass 10, count 2 2006.173.12:19:26.62#ibcon#about to read 6, iclass 10, count 2 2006.173.12:19:26.62#ibcon#read 6, iclass 10, count 2 2006.173.12:19:26.62#ibcon#end of sib2, iclass 10, count 2 2006.173.12:19:26.62#ibcon#*mode == 0, iclass 10, count 2 2006.173.12:19:26.62#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.12:19:26.62#ibcon#[27=AT06-04\r\n] 2006.173.12:19:26.62#ibcon#*before write, iclass 10, count 2 2006.173.12:19:26.62#ibcon#enter sib2, iclass 10, count 2 2006.173.12:19:26.62#ibcon#flushed, iclass 10, count 2 2006.173.12:19:26.62#ibcon#about to write, iclass 10, count 2 2006.173.12:19:26.62#ibcon#wrote, iclass 10, count 2 2006.173.12:19:26.62#ibcon#about to read 3, iclass 10, count 2 2006.173.12:19:26.65#ibcon#read 3, iclass 10, count 2 2006.173.12:19:26.65#ibcon#about to read 4, iclass 10, count 2 2006.173.12:19:26.65#ibcon#read 4, iclass 10, count 2 2006.173.12:19:26.65#ibcon#about to read 5, iclass 10, count 2 2006.173.12:19:26.65#ibcon#read 5, iclass 10, count 2 2006.173.12:19:26.65#ibcon#about to read 6, iclass 10, count 2 2006.173.12:19:26.65#ibcon#read 6, iclass 10, count 2 2006.173.12:19:26.65#ibcon#end of sib2, iclass 10, count 2 2006.173.12:19:26.65#ibcon#*after write, iclass 10, count 2 2006.173.12:19:26.65#ibcon#*before return 0, iclass 10, count 2 2006.173.12:19:26.65#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.12:19:26.65#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.12:19:26.65#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.12:19:26.65#ibcon#ireg 7 cls_cnt 0 2006.173.12:19:26.65#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.12:19:26.77#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.12:19:26.77#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.12:19:26.77#ibcon#enter wrdev, iclass 10, count 0 2006.173.12:19:26.77#ibcon#first serial, iclass 10, count 0 2006.173.12:19:26.77#ibcon#enter sib2, iclass 10, count 0 2006.173.12:19:26.77#ibcon#flushed, iclass 10, count 0 2006.173.12:19:26.77#ibcon#about to write, iclass 10, count 0 2006.173.12:19:26.77#ibcon#wrote, iclass 10, count 0 2006.173.12:19:26.77#ibcon#about to read 3, iclass 10, count 0 2006.173.12:19:26.79#ibcon#read 3, iclass 10, count 0 2006.173.12:19:26.79#ibcon#about to read 4, iclass 10, count 0 2006.173.12:19:26.79#ibcon#read 4, iclass 10, count 0 2006.173.12:19:26.79#ibcon#about to read 5, iclass 10, count 0 2006.173.12:19:26.79#ibcon#read 5, iclass 10, count 0 2006.173.12:19:26.79#ibcon#about to read 6, iclass 10, count 0 2006.173.12:19:26.79#ibcon#read 6, iclass 10, count 0 2006.173.12:19:26.79#ibcon#end of sib2, iclass 10, count 0 2006.173.12:19:26.79#ibcon#*mode == 0, iclass 10, count 0 2006.173.12:19:26.79#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.12:19:26.79#ibcon#[27=USB\r\n] 2006.173.12:19:26.79#ibcon#*before write, iclass 10, count 0 2006.173.12:19:26.79#ibcon#enter sib2, iclass 10, count 0 2006.173.12:19:26.79#ibcon#flushed, iclass 10, count 0 2006.173.12:19:26.79#ibcon#about to write, iclass 10, count 0 2006.173.12:19:26.79#ibcon#wrote, iclass 10, count 0 2006.173.12:19:26.79#ibcon#about to read 3, iclass 10, count 0 2006.173.12:19:26.82#ibcon#read 3, iclass 10, count 0 2006.173.12:19:26.82#ibcon#about to read 4, iclass 10, count 0 2006.173.12:19:26.82#ibcon#read 4, iclass 10, count 0 2006.173.12:19:26.82#ibcon#about to read 5, iclass 10, count 0 2006.173.12:19:26.82#ibcon#read 5, iclass 10, count 0 2006.173.12:19:26.82#ibcon#about to read 6, iclass 10, count 0 2006.173.12:19:26.82#ibcon#read 6, iclass 10, count 0 2006.173.12:19:26.82#ibcon#end of sib2, iclass 10, count 0 2006.173.12:19:26.82#ibcon#*after write, iclass 10, count 0 2006.173.12:19:26.82#ibcon#*before return 0, iclass 10, count 0 2006.173.12:19:26.82#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.12:19:26.82#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.12:19:26.82#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.12:19:26.82#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.12:19:26.82$vck44/vblo=7,734.99 2006.173.12:19:26.82#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.12:19:26.82#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.12:19:26.82#ibcon#ireg 17 cls_cnt 0 2006.173.12:19:26.82#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.12:19:26.82#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.12:19:26.82#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.12:19:26.82#ibcon#enter wrdev, iclass 12, count 0 2006.173.12:19:26.82#ibcon#first serial, iclass 12, count 0 2006.173.12:19:26.82#ibcon#enter sib2, iclass 12, count 0 2006.173.12:19:26.82#ibcon#flushed, iclass 12, count 0 2006.173.12:19:26.82#ibcon#about to write, iclass 12, count 0 2006.173.12:19:26.82#ibcon#wrote, iclass 12, count 0 2006.173.12:19:26.82#ibcon#about to read 3, iclass 12, count 0 2006.173.12:19:26.84#ibcon#read 3, iclass 12, count 0 2006.173.12:19:26.84#ibcon#about to read 4, iclass 12, count 0 2006.173.12:19:26.84#ibcon#read 4, iclass 12, count 0 2006.173.12:19:26.84#ibcon#about to read 5, iclass 12, count 0 2006.173.12:19:26.84#ibcon#read 5, iclass 12, count 0 2006.173.12:19:26.84#ibcon#about to read 6, iclass 12, count 0 2006.173.12:19:26.84#ibcon#read 6, iclass 12, count 0 2006.173.12:19:26.84#ibcon#end of sib2, iclass 12, count 0 2006.173.12:19:26.84#ibcon#*mode == 0, iclass 12, count 0 2006.173.12:19:26.84#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.12:19:26.84#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.12:19:26.84#ibcon#*before write, iclass 12, count 0 2006.173.12:19:26.84#ibcon#enter sib2, iclass 12, count 0 2006.173.12:19:26.84#ibcon#flushed, iclass 12, count 0 2006.173.12:19:26.84#ibcon#about to write, iclass 12, count 0 2006.173.12:19:26.84#ibcon#wrote, iclass 12, count 0 2006.173.12:19:26.84#ibcon#about to read 3, iclass 12, count 0 2006.173.12:19:26.88#ibcon#read 3, iclass 12, count 0 2006.173.12:19:26.88#ibcon#about to read 4, iclass 12, count 0 2006.173.12:19:26.88#ibcon#read 4, iclass 12, count 0 2006.173.12:19:26.88#ibcon#about to read 5, iclass 12, count 0 2006.173.12:19:26.88#ibcon#read 5, iclass 12, count 0 2006.173.12:19:26.88#ibcon#about to read 6, iclass 12, count 0 2006.173.12:19:26.88#ibcon#read 6, iclass 12, count 0 2006.173.12:19:26.88#ibcon#end of sib2, iclass 12, count 0 2006.173.12:19:26.88#ibcon#*after write, iclass 12, count 0 2006.173.12:19:26.88#ibcon#*before return 0, iclass 12, count 0 2006.173.12:19:26.88#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.12:19:26.88#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.12:19:26.88#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.12:19:26.88#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.12:19:26.88$vck44/vb=7,4 2006.173.12:19:26.88#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.12:19:26.88#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.12:19:26.88#ibcon#ireg 11 cls_cnt 2 2006.173.12:19:26.88#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.12:19:26.94#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.12:19:26.94#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.12:19:26.94#ibcon#enter wrdev, iclass 14, count 2 2006.173.12:19:26.94#ibcon#first serial, iclass 14, count 2 2006.173.12:19:26.94#ibcon#enter sib2, iclass 14, count 2 2006.173.12:19:26.94#ibcon#flushed, iclass 14, count 2 2006.173.12:19:26.94#ibcon#about to write, iclass 14, count 2 2006.173.12:19:26.94#ibcon#wrote, iclass 14, count 2 2006.173.12:19:26.94#ibcon#about to read 3, iclass 14, count 2 2006.173.12:19:26.96#ibcon#read 3, iclass 14, count 2 2006.173.12:19:26.96#ibcon#about to read 4, iclass 14, count 2 2006.173.12:19:26.96#ibcon#read 4, iclass 14, count 2 2006.173.12:19:26.96#ibcon#about to read 5, iclass 14, count 2 2006.173.12:19:26.96#ibcon#read 5, iclass 14, count 2 2006.173.12:19:26.96#ibcon#about to read 6, iclass 14, count 2 2006.173.12:19:26.96#ibcon#read 6, iclass 14, count 2 2006.173.12:19:26.96#ibcon#end of sib2, iclass 14, count 2 2006.173.12:19:26.96#ibcon#*mode == 0, iclass 14, count 2 2006.173.12:19:26.96#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.12:19:26.96#ibcon#[27=AT07-04\r\n] 2006.173.12:19:26.96#ibcon#*before write, iclass 14, count 2 2006.173.12:19:26.96#ibcon#enter sib2, iclass 14, count 2 2006.173.12:19:26.96#ibcon#flushed, iclass 14, count 2 2006.173.12:19:26.96#ibcon#about to write, iclass 14, count 2 2006.173.12:19:26.96#ibcon#wrote, iclass 14, count 2 2006.173.12:19:26.96#ibcon#about to read 3, iclass 14, count 2 2006.173.12:19:26.99#ibcon#read 3, iclass 14, count 2 2006.173.12:19:26.99#ibcon#about to read 4, iclass 14, count 2 2006.173.12:19:26.99#ibcon#read 4, iclass 14, count 2 2006.173.12:19:26.99#ibcon#about to read 5, iclass 14, count 2 2006.173.12:19:26.99#ibcon#read 5, iclass 14, count 2 2006.173.12:19:26.99#ibcon#about to read 6, iclass 14, count 2 2006.173.12:19:26.99#ibcon#read 6, iclass 14, count 2 2006.173.12:19:26.99#ibcon#end of sib2, iclass 14, count 2 2006.173.12:19:26.99#ibcon#*after write, iclass 14, count 2 2006.173.12:19:26.99#ibcon#*before return 0, iclass 14, count 2 2006.173.12:19:26.99#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.12:19:26.99#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.12:19:26.99#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.12:19:26.99#ibcon#ireg 7 cls_cnt 0 2006.173.12:19:26.99#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.12:19:27.11#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.12:19:27.11#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.12:19:27.11#ibcon#enter wrdev, iclass 14, count 0 2006.173.12:19:27.11#ibcon#first serial, iclass 14, count 0 2006.173.12:19:27.11#ibcon#enter sib2, iclass 14, count 0 2006.173.12:19:27.11#ibcon#flushed, iclass 14, count 0 2006.173.12:19:27.11#ibcon#about to write, iclass 14, count 0 2006.173.12:19:27.11#ibcon#wrote, iclass 14, count 0 2006.173.12:19:27.11#ibcon#about to read 3, iclass 14, count 0 2006.173.12:19:27.13#ibcon#read 3, iclass 14, count 0 2006.173.12:19:27.13#ibcon#about to read 4, iclass 14, count 0 2006.173.12:19:27.13#ibcon#read 4, iclass 14, count 0 2006.173.12:19:27.13#ibcon#about to read 5, iclass 14, count 0 2006.173.12:19:27.13#ibcon#read 5, iclass 14, count 0 2006.173.12:19:27.13#ibcon#about to read 6, iclass 14, count 0 2006.173.12:19:27.13#ibcon#read 6, iclass 14, count 0 2006.173.12:19:27.13#ibcon#end of sib2, iclass 14, count 0 2006.173.12:19:27.13#ibcon#*mode == 0, iclass 14, count 0 2006.173.12:19:27.13#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.12:19:27.13#ibcon#[27=USB\r\n] 2006.173.12:19:27.13#ibcon#*before write, iclass 14, count 0 2006.173.12:19:27.13#ibcon#enter sib2, iclass 14, count 0 2006.173.12:19:27.13#ibcon#flushed, iclass 14, count 0 2006.173.12:19:27.13#ibcon#about to write, iclass 14, count 0 2006.173.12:19:27.13#ibcon#wrote, iclass 14, count 0 2006.173.12:19:27.13#ibcon#about to read 3, iclass 14, count 0 2006.173.12:19:27.16#ibcon#read 3, iclass 14, count 0 2006.173.12:19:27.16#ibcon#about to read 4, iclass 14, count 0 2006.173.12:19:27.16#ibcon#read 4, iclass 14, count 0 2006.173.12:19:27.16#ibcon#about to read 5, iclass 14, count 0 2006.173.12:19:27.16#ibcon#read 5, iclass 14, count 0 2006.173.12:19:27.16#ibcon#about to read 6, iclass 14, count 0 2006.173.12:19:27.16#ibcon#read 6, iclass 14, count 0 2006.173.12:19:27.16#ibcon#end of sib2, iclass 14, count 0 2006.173.12:19:27.16#ibcon#*after write, iclass 14, count 0 2006.173.12:19:27.16#ibcon#*before return 0, iclass 14, count 0 2006.173.12:19:27.16#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.12:19:27.16#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.12:19:27.16#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.12:19:27.16#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.12:19:27.16$vck44/vblo=8,744.99 2006.173.12:19:27.16#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.12:19:27.16#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.12:19:27.16#ibcon#ireg 17 cls_cnt 0 2006.173.12:19:27.16#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.12:19:27.16#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.12:19:27.16#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.12:19:27.16#ibcon#enter wrdev, iclass 16, count 0 2006.173.12:19:27.16#ibcon#first serial, iclass 16, count 0 2006.173.12:19:27.16#ibcon#enter sib2, iclass 16, count 0 2006.173.12:19:27.16#ibcon#flushed, iclass 16, count 0 2006.173.12:19:27.16#ibcon#about to write, iclass 16, count 0 2006.173.12:19:27.16#ibcon#wrote, iclass 16, count 0 2006.173.12:19:27.16#ibcon#about to read 3, iclass 16, count 0 2006.173.12:19:27.18#ibcon#read 3, iclass 16, count 0 2006.173.12:19:27.18#ibcon#about to read 4, iclass 16, count 0 2006.173.12:19:27.18#ibcon#read 4, iclass 16, count 0 2006.173.12:19:27.18#ibcon#about to read 5, iclass 16, count 0 2006.173.12:19:27.18#ibcon#read 5, iclass 16, count 0 2006.173.12:19:27.18#ibcon#about to read 6, iclass 16, count 0 2006.173.12:19:27.18#ibcon#read 6, iclass 16, count 0 2006.173.12:19:27.18#ibcon#end of sib2, iclass 16, count 0 2006.173.12:19:27.18#ibcon#*mode == 0, iclass 16, count 0 2006.173.12:19:27.18#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.12:19:27.18#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.12:19:27.18#ibcon#*before write, iclass 16, count 0 2006.173.12:19:27.18#ibcon#enter sib2, iclass 16, count 0 2006.173.12:19:27.18#ibcon#flushed, iclass 16, count 0 2006.173.12:19:27.18#ibcon#about to write, iclass 16, count 0 2006.173.12:19:27.18#ibcon#wrote, iclass 16, count 0 2006.173.12:19:27.18#ibcon#about to read 3, iclass 16, count 0 2006.173.12:19:27.22#ibcon#read 3, iclass 16, count 0 2006.173.12:19:27.22#ibcon#about to read 4, iclass 16, count 0 2006.173.12:19:27.22#ibcon#read 4, iclass 16, count 0 2006.173.12:19:27.22#ibcon#about to read 5, iclass 16, count 0 2006.173.12:19:27.22#ibcon#read 5, iclass 16, count 0 2006.173.12:19:27.22#ibcon#about to read 6, iclass 16, count 0 2006.173.12:19:27.22#ibcon#read 6, iclass 16, count 0 2006.173.12:19:27.22#ibcon#end of sib2, iclass 16, count 0 2006.173.12:19:27.22#ibcon#*after write, iclass 16, count 0 2006.173.12:19:27.22#ibcon#*before return 0, iclass 16, count 0 2006.173.12:19:27.22#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.12:19:27.22#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.12:19:27.22#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.12:19:27.22#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.12:19:27.22$vck44/vb=8,4 2006.173.12:19:27.22#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.12:19:27.22#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.12:19:27.22#ibcon#ireg 11 cls_cnt 2 2006.173.12:19:27.22#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.12:19:27.28#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.12:19:27.28#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.12:19:27.28#ibcon#enter wrdev, iclass 18, count 2 2006.173.12:19:27.28#ibcon#first serial, iclass 18, count 2 2006.173.12:19:27.28#ibcon#enter sib2, iclass 18, count 2 2006.173.12:19:27.28#ibcon#flushed, iclass 18, count 2 2006.173.12:19:27.28#ibcon#about to write, iclass 18, count 2 2006.173.12:19:27.28#ibcon#wrote, iclass 18, count 2 2006.173.12:19:27.28#ibcon#about to read 3, iclass 18, count 2 2006.173.12:19:27.30#ibcon#read 3, iclass 18, count 2 2006.173.12:19:27.30#ibcon#about to read 4, iclass 18, count 2 2006.173.12:19:27.30#ibcon#read 4, iclass 18, count 2 2006.173.12:19:27.30#ibcon#about to read 5, iclass 18, count 2 2006.173.12:19:27.30#ibcon#read 5, iclass 18, count 2 2006.173.12:19:27.30#ibcon#about to read 6, iclass 18, count 2 2006.173.12:19:27.30#ibcon#read 6, iclass 18, count 2 2006.173.12:19:27.30#ibcon#end of sib2, iclass 18, count 2 2006.173.12:19:27.30#ibcon#*mode == 0, iclass 18, count 2 2006.173.12:19:27.30#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.12:19:27.30#ibcon#[27=AT08-04\r\n] 2006.173.12:19:27.30#ibcon#*before write, iclass 18, count 2 2006.173.12:19:27.30#ibcon#enter sib2, iclass 18, count 2 2006.173.12:19:27.30#ibcon#flushed, iclass 18, count 2 2006.173.12:19:27.30#ibcon#about to write, iclass 18, count 2 2006.173.12:19:27.30#ibcon#wrote, iclass 18, count 2 2006.173.12:19:27.30#ibcon#about to read 3, iclass 18, count 2 2006.173.12:19:27.33#ibcon#read 3, iclass 18, count 2 2006.173.12:19:27.33#ibcon#about to read 4, iclass 18, count 2 2006.173.12:19:27.33#ibcon#read 4, iclass 18, count 2 2006.173.12:19:27.33#ibcon#about to read 5, iclass 18, count 2 2006.173.12:19:27.33#ibcon#read 5, iclass 18, count 2 2006.173.12:19:27.33#ibcon#about to read 6, iclass 18, count 2 2006.173.12:19:27.33#ibcon#read 6, iclass 18, count 2 2006.173.12:19:27.33#ibcon#end of sib2, iclass 18, count 2 2006.173.12:19:27.33#ibcon#*after write, iclass 18, count 2 2006.173.12:19:27.33#ibcon#*before return 0, iclass 18, count 2 2006.173.12:19:27.33#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.12:19:27.33#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.12:19:27.33#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.12:19:27.33#ibcon#ireg 7 cls_cnt 0 2006.173.12:19:27.33#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.12:19:27.45#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.12:19:27.45#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.12:19:27.45#ibcon#enter wrdev, iclass 18, count 0 2006.173.12:19:27.45#ibcon#first serial, iclass 18, count 0 2006.173.12:19:27.45#ibcon#enter sib2, iclass 18, count 0 2006.173.12:19:27.45#ibcon#flushed, iclass 18, count 0 2006.173.12:19:27.45#ibcon#about to write, iclass 18, count 0 2006.173.12:19:27.45#ibcon#wrote, iclass 18, count 0 2006.173.12:19:27.45#ibcon#about to read 3, iclass 18, count 0 2006.173.12:19:27.47#ibcon#read 3, iclass 18, count 0 2006.173.12:19:27.47#ibcon#about to read 4, iclass 18, count 0 2006.173.12:19:27.47#ibcon#read 4, iclass 18, count 0 2006.173.12:19:27.47#ibcon#about to read 5, iclass 18, count 0 2006.173.12:19:27.47#ibcon#read 5, iclass 18, count 0 2006.173.12:19:27.47#ibcon#about to read 6, iclass 18, count 0 2006.173.12:19:27.47#ibcon#read 6, iclass 18, count 0 2006.173.12:19:27.47#ibcon#end of sib2, iclass 18, count 0 2006.173.12:19:27.47#ibcon#*mode == 0, iclass 18, count 0 2006.173.12:19:27.47#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.12:19:27.47#ibcon#[27=USB\r\n] 2006.173.12:19:27.47#ibcon#*before write, iclass 18, count 0 2006.173.12:19:27.47#ibcon#enter sib2, iclass 18, count 0 2006.173.12:19:27.47#ibcon#flushed, iclass 18, count 0 2006.173.12:19:27.47#ibcon#about to write, iclass 18, count 0 2006.173.12:19:27.47#ibcon#wrote, iclass 18, count 0 2006.173.12:19:27.47#ibcon#about to read 3, iclass 18, count 0 2006.173.12:19:27.50#ibcon#read 3, iclass 18, count 0 2006.173.12:19:27.50#ibcon#about to read 4, iclass 18, count 0 2006.173.12:19:27.50#ibcon#read 4, iclass 18, count 0 2006.173.12:19:27.50#ibcon#about to read 5, iclass 18, count 0 2006.173.12:19:27.50#ibcon#read 5, iclass 18, count 0 2006.173.12:19:27.50#ibcon#about to read 6, iclass 18, count 0 2006.173.12:19:27.50#ibcon#read 6, iclass 18, count 0 2006.173.12:19:27.50#ibcon#end of sib2, iclass 18, count 0 2006.173.12:19:27.50#ibcon#*after write, iclass 18, count 0 2006.173.12:19:27.50#ibcon#*before return 0, iclass 18, count 0 2006.173.12:19:27.50#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.12:19:27.50#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.12:19:27.50#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.12:19:27.50#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.12:19:27.50$vck44/vabw=wide 2006.173.12:19:27.50#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.12:19:27.50#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.12:19:27.50#ibcon#ireg 8 cls_cnt 0 2006.173.12:19:27.50#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.12:19:27.50#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.12:19:27.50#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.12:19:27.50#ibcon#enter wrdev, iclass 20, count 0 2006.173.12:19:27.50#ibcon#first serial, iclass 20, count 0 2006.173.12:19:27.50#ibcon#enter sib2, iclass 20, count 0 2006.173.12:19:27.50#ibcon#flushed, iclass 20, count 0 2006.173.12:19:27.50#ibcon#about to write, iclass 20, count 0 2006.173.12:19:27.50#ibcon#wrote, iclass 20, count 0 2006.173.12:19:27.50#ibcon#about to read 3, iclass 20, count 0 2006.173.12:19:27.52#ibcon#read 3, iclass 20, count 0 2006.173.12:19:27.52#ibcon#about to read 4, iclass 20, count 0 2006.173.12:19:27.52#ibcon#read 4, iclass 20, count 0 2006.173.12:19:27.52#ibcon#about to read 5, iclass 20, count 0 2006.173.12:19:27.52#ibcon#read 5, iclass 20, count 0 2006.173.12:19:27.52#ibcon#about to read 6, iclass 20, count 0 2006.173.12:19:27.52#ibcon#read 6, iclass 20, count 0 2006.173.12:19:27.52#ibcon#end of sib2, iclass 20, count 0 2006.173.12:19:27.52#ibcon#*mode == 0, iclass 20, count 0 2006.173.12:19:27.52#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.12:19:27.52#ibcon#[25=BW32\r\n] 2006.173.12:19:27.52#ibcon#*before write, iclass 20, count 0 2006.173.12:19:27.52#ibcon#enter sib2, iclass 20, count 0 2006.173.12:19:27.52#ibcon#flushed, iclass 20, count 0 2006.173.12:19:27.52#ibcon#about to write, iclass 20, count 0 2006.173.12:19:27.52#ibcon#wrote, iclass 20, count 0 2006.173.12:19:27.52#ibcon#about to read 3, iclass 20, count 0 2006.173.12:19:27.55#ibcon#read 3, iclass 20, count 0 2006.173.12:19:27.55#ibcon#about to read 4, iclass 20, count 0 2006.173.12:19:27.55#ibcon#read 4, iclass 20, count 0 2006.173.12:19:27.55#ibcon#about to read 5, iclass 20, count 0 2006.173.12:19:27.55#ibcon#read 5, iclass 20, count 0 2006.173.12:19:27.55#ibcon#about to read 6, iclass 20, count 0 2006.173.12:19:27.55#ibcon#read 6, iclass 20, count 0 2006.173.12:19:27.55#ibcon#end of sib2, iclass 20, count 0 2006.173.12:19:27.55#ibcon#*after write, iclass 20, count 0 2006.173.12:19:27.55#ibcon#*before return 0, iclass 20, count 0 2006.173.12:19:27.55#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.12:19:27.55#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.12:19:27.55#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.12:19:27.55#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.12:19:27.55$vck44/vbbw=wide 2006.173.12:19:27.55#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.12:19:27.55#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.12:19:27.55#ibcon#ireg 8 cls_cnt 0 2006.173.12:19:27.55#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.12:19:27.62#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.12:19:27.62#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.12:19:27.62#ibcon#enter wrdev, iclass 22, count 0 2006.173.12:19:27.62#ibcon#first serial, iclass 22, count 0 2006.173.12:19:27.62#ibcon#enter sib2, iclass 22, count 0 2006.173.12:19:27.62#ibcon#flushed, iclass 22, count 0 2006.173.12:19:27.62#ibcon#about to write, iclass 22, count 0 2006.173.12:19:27.62#ibcon#wrote, iclass 22, count 0 2006.173.12:19:27.62#ibcon#about to read 3, iclass 22, count 0 2006.173.12:19:27.64#ibcon#read 3, iclass 22, count 0 2006.173.12:19:27.64#ibcon#about to read 4, iclass 22, count 0 2006.173.12:19:27.64#ibcon#read 4, iclass 22, count 0 2006.173.12:19:27.64#ibcon#about to read 5, iclass 22, count 0 2006.173.12:19:27.64#ibcon#read 5, iclass 22, count 0 2006.173.12:19:27.64#ibcon#about to read 6, iclass 22, count 0 2006.173.12:19:27.64#ibcon#read 6, iclass 22, count 0 2006.173.12:19:27.64#ibcon#end of sib2, iclass 22, count 0 2006.173.12:19:27.64#ibcon#*mode == 0, iclass 22, count 0 2006.173.12:19:27.64#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.12:19:27.64#ibcon#[27=BW32\r\n] 2006.173.12:19:27.64#ibcon#*before write, iclass 22, count 0 2006.173.12:19:27.64#ibcon#enter sib2, iclass 22, count 0 2006.173.12:19:27.64#ibcon#flushed, iclass 22, count 0 2006.173.12:19:27.64#ibcon#about to write, iclass 22, count 0 2006.173.12:19:27.64#ibcon#wrote, iclass 22, count 0 2006.173.12:19:27.64#ibcon#about to read 3, iclass 22, count 0 2006.173.12:19:27.67#ibcon#read 3, iclass 22, count 0 2006.173.12:19:27.67#ibcon#about to read 4, iclass 22, count 0 2006.173.12:19:27.67#ibcon#read 4, iclass 22, count 0 2006.173.12:19:27.67#ibcon#about to read 5, iclass 22, count 0 2006.173.12:19:27.67#ibcon#read 5, iclass 22, count 0 2006.173.12:19:27.67#ibcon#about to read 6, iclass 22, count 0 2006.173.12:19:27.67#ibcon#read 6, iclass 22, count 0 2006.173.12:19:27.67#ibcon#end of sib2, iclass 22, count 0 2006.173.12:19:27.67#ibcon#*after write, iclass 22, count 0 2006.173.12:19:27.67#ibcon#*before return 0, iclass 22, count 0 2006.173.12:19:27.67#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.12:19:27.67#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.12:19:27.67#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.12:19:27.67#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.12:19:27.67$setupk4/ifdk4 2006.173.12:19:27.67$ifdk4/lo= 2006.173.12:19:27.67$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.12:19:27.68$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.12:19:27.68$ifdk4/patch= 2006.173.12:19:27.68$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.12:19:27.68$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.12:19:27.68$setupk4/!*+20s 2006.173.12:19:28.66#abcon#<5=/06 1.4 2.1 22.17 951004.2\r\n> 2006.173.12:19:28.68#abcon#{5=INTERFACE CLEAR} 2006.173.12:19:28.74#abcon#[5=S1D000X0/0*\r\n] 2006.173.12:19:38.83#abcon#<5=/06 1.3 2.1 22.17 951004.2\r\n> 2006.173.12:19:38.85#abcon#{5=INTERFACE CLEAR} 2006.173.12:19:38.91#abcon#[5=S1D000X0/0*\r\n] 2006.173.12:19:42.20$setupk4/"tpicd 2006.173.12:19:42.20$setupk4/echo=off 2006.173.12:19:42.20$setupk4/xlog=off 2006.173.12:19:42.20:!2006.173.12:20:52 2006.173.12:19:50.14#trakl#Source acquired 2006.173.12:19:51.14#flagr#flagr/antenna,acquired 2006.173.12:20:52.00:preob 2006.173.12:20:52.14/onsource/TRACKING 2006.173.12:20:52.14:!2006.173.12:21:02 2006.173.12:21:02.00:"tape 2006.173.12:21:02.00:"st=record 2006.173.12:21:02.00:data_valid=on 2006.173.12:21:02.00:midob 2006.173.12:21:03.13/onsource/TRACKING 2006.173.12:21:03.13/wx/22.17,1004.2,95 2006.173.12:21:03.23/cable/+6.5027E-03 2006.173.12:21:04.32/va/01,07,usb,yes,35,38 2006.173.12:21:04.32/va/02,06,usb,yes,35,36 2006.173.12:21:04.32/va/03,05,usb,yes,45,47 2006.173.12:21:04.32/va/04,06,usb,yes,36,38 2006.173.12:21:04.32/va/05,04,usb,yes,28,29 2006.173.12:21:04.32/va/06,03,usb,yes,39,39 2006.173.12:21:04.32/va/07,04,usb,yes,32,33 2006.173.12:21:04.32/va/08,04,usb,yes,27,33 2006.173.12:21:04.55/valo/01,524.99,yes,locked 2006.173.12:21:04.55/valo/02,534.99,yes,locked 2006.173.12:21:04.55/valo/03,564.99,yes,locked 2006.173.12:21:04.55/valo/04,624.99,yes,locked 2006.173.12:21:04.55/valo/05,734.99,yes,locked 2006.173.12:21:04.55/valo/06,814.99,yes,locked 2006.173.12:21:04.55/valo/07,864.99,yes,locked 2006.173.12:21:04.55/valo/08,884.99,yes,locked 2006.173.12:21:05.64/vb/01,04,usb,yes,29,27 2006.173.12:21:05.64/vb/02,04,usb,yes,31,31 2006.173.12:21:05.64/vb/03,04,usb,yes,28,31 2006.173.12:21:05.64/vb/04,04,usb,yes,33,32 2006.173.12:21:05.64/vb/05,04,usb,yes,25,28 2006.173.12:21:05.64/vb/06,04,usb,yes,30,26 2006.173.12:21:05.64/vb/07,04,usb,yes,29,29 2006.173.12:21:05.64/vb/08,04,usb,yes,27,30 2006.173.12:21:05.87/vblo/01,629.99,yes,locked 2006.173.12:21:05.87/vblo/02,634.99,yes,locked 2006.173.12:21:05.87/vblo/03,649.99,yes,locked 2006.173.12:21:05.87/vblo/04,679.99,yes,locked 2006.173.12:21:05.87/vblo/05,709.99,yes,locked 2006.173.12:21:05.87/vblo/06,719.99,yes,locked 2006.173.12:21:05.87/vblo/07,734.99,yes,locked 2006.173.12:21:05.87/vblo/08,744.99,yes,locked 2006.173.12:21:06.02/vabw/8 2006.173.12:21:06.17/vbbw/8 2006.173.12:21:06.26/xfe/off,on,14.7 2006.173.12:21:06.63/ifatt/23,28,28,28 2006.173.12:21:07.07/fmout-gps/S +3.98E-07 2006.173.12:21:07.12:!2006.173.12:21:42 2006.173.12:21:42.01:data_valid=off 2006.173.12:21:42.02:"et 2006.173.12:21:42.02:!+3s 2006.173.12:21:45.03:"tape 2006.173.12:21:45.04:postob 2006.173.12:21:45.11/cable/+6.5037E-03 2006.173.12:21:45.12/wx/22.17,1004.2,95 2006.173.12:21:45.17/fmout-gps/S +3.98E-07 2006.173.12:21:45.18:scan_name=173-1223,jd0606,100 2006.173.12:21:45.18:source=3c274,123049.42,122328.0,2000.0,cw 2006.173.12:21:47.13#flagr#flagr/antenna,new-source 2006.173.12:21:47.14:checkk5 2006.173.12:21:47.55/chk_autoobs//k5ts1/ autoobs is running! 2006.173.12:21:47.94/chk_autoobs//k5ts2/ autoobs is running! 2006.173.12:21:48.34/chk_autoobs//k5ts3/ autoobs is running! 2006.173.12:21:48.73/chk_autoobs//k5ts4/ autoobs is running! 2006.173.12:21:49.12/chk_obsdata//k5ts1/T1731221??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.12:21:49.52/chk_obsdata//k5ts2/T1731221??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.12:21:49.94/chk_obsdata//k5ts3/T1731221??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.12:21:50.33/chk_obsdata//k5ts4/T1731221??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.12:21:51.06/k5log//k5ts1_log_newline 2006.173.12:21:51.77/k5log//k5ts2_log_newline 2006.173.12:21:52.48/k5log//k5ts3_log_newline 2006.173.12:21:53.19/k5log//k5ts4_log_newline 2006.173.12:21:53.21/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.12:21:53.21:setupk4=1 2006.173.12:21:53.22$setupk4/echo=on 2006.173.12:21:53.22$setupk4/pcalon 2006.173.12:21:53.22$pcalon/"no phase cal control is implemented here 2006.173.12:21:53.22$setupk4/"tpicd=stop 2006.173.12:21:53.22$setupk4/"rec=synch_on 2006.173.12:21:53.22$setupk4/"rec_mode=128 2006.173.12:21:53.22$setupk4/!* 2006.173.12:21:53.22$setupk4/recpk4 2006.173.12:21:53.22$recpk4/recpatch= 2006.173.12:21:53.22$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.12:21:53.22$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.12:21:53.22$setupk4/vck44 2006.173.12:21:53.22$vck44/valo=1,524.99 2006.173.12:21:53.22#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.12:21:53.22#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.12:21:53.22#ibcon#ireg 17 cls_cnt 0 2006.173.12:21:53.22#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.12:21:53.22#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.12:21:53.22#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.12:21:53.22#ibcon#enter wrdev, iclass 15, count 0 2006.173.12:21:53.22#ibcon#first serial, iclass 15, count 0 2006.173.12:21:53.22#ibcon#enter sib2, iclass 15, count 0 2006.173.12:21:53.22#ibcon#flushed, iclass 15, count 0 2006.173.12:21:53.22#ibcon#about to write, iclass 15, count 0 2006.173.12:21:53.22#ibcon#wrote, iclass 15, count 0 2006.173.12:21:53.22#ibcon#about to read 3, iclass 15, count 0 2006.173.12:21:53.23#ibcon#read 3, iclass 15, count 0 2006.173.12:21:53.23#ibcon#about to read 4, iclass 15, count 0 2006.173.12:21:53.23#ibcon#read 4, iclass 15, count 0 2006.173.12:21:53.23#ibcon#about to read 5, iclass 15, count 0 2006.173.12:21:53.23#ibcon#read 5, iclass 15, count 0 2006.173.12:21:53.23#ibcon#about to read 6, iclass 15, count 0 2006.173.12:21:53.23#ibcon#read 6, iclass 15, count 0 2006.173.12:21:53.23#ibcon#end of sib2, iclass 15, count 0 2006.173.12:21:53.23#ibcon#*mode == 0, iclass 15, count 0 2006.173.12:21:53.23#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.12:21:53.23#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.12:21:53.23#ibcon#*before write, iclass 15, count 0 2006.173.12:21:53.23#ibcon#enter sib2, iclass 15, count 0 2006.173.12:21:53.23#ibcon#flushed, iclass 15, count 0 2006.173.12:21:53.23#ibcon#about to write, iclass 15, count 0 2006.173.12:21:53.23#ibcon#wrote, iclass 15, count 0 2006.173.12:21:53.23#ibcon#about to read 3, iclass 15, count 0 2006.173.12:21:53.28#ibcon#read 3, iclass 15, count 0 2006.173.12:21:53.28#ibcon#about to read 4, iclass 15, count 0 2006.173.12:21:53.28#ibcon#read 4, iclass 15, count 0 2006.173.12:21:53.28#ibcon#about to read 5, iclass 15, count 0 2006.173.12:21:53.28#ibcon#read 5, iclass 15, count 0 2006.173.12:21:53.28#ibcon#about to read 6, iclass 15, count 0 2006.173.12:21:53.28#ibcon#read 6, iclass 15, count 0 2006.173.12:21:53.28#ibcon#end of sib2, iclass 15, count 0 2006.173.12:21:53.28#ibcon#*after write, iclass 15, count 0 2006.173.12:21:53.28#ibcon#*before return 0, iclass 15, count 0 2006.173.12:21:53.28#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.12:21:53.28#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.12:21:53.28#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.12:21:53.28#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.12:21:53.28$vck44/va=1,7 2006.173.12:21:53.28#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.12:21:53.28#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.12:21:53.28#ibcon#ireg 11 cls_cnt 2 2006.173.12:21:53.28#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.12:21:53.28#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.12:21:53.28#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.12:21:53.28#ibcon#enter wrdev, iclass 17, count 2 2006.173.12:21:53.28#ibcon#first serial, iclass 17, count 2 2006.173.12:21:53.28#ibcon#enter sib2, iclass 17, count 2 2006.173.12:21:53.28#ibcon#flushed, iclass 17, count 2 2006.173.12:21:53.28#ibcon#about to write, iclass 17, count 2 2006.173.12:21:53.28#ibcon#wrote, iclass 17, count 2 2006.173.12:21:53.28#ibcon#about to read 3, iclass 17, count 2 2006.173.12:21:53.30#ibcon#read 3, iclass 17, count 2 2006.173.12:21:53.30#ibcon#about to read 4, iclass 17, count 2 2006.173.12:21:53.30#ibcon#read 4, iclass 17, count 2 2006.173.12:21:53.30#ibcon#about to read 5, iclass 17, count 2 2006.173.12:21:53.30#ibcon#read 5, iclass 17, count 2 2006.173.12:21:53.30#ibcon#about to read 6, iclass 17, count 2 2006.173.12:21:53.30#ibcon#read 6, iclass 17, count 2 2006.173.12:21:53.30#ibcon#end of sib2, iclass 17, count 2 2006.173.12:21:53.30#ibcon#*mode == 0, iclass 17, count 2 2006.173.12:21:53.30#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.12:21:53.30#ibcon#[25=AT01-07\r\n] 2006.173.12:21:53.30#ibcon#*before write, iclass 17, count 2 2006.173.12:21:53.30#ibcon#enter sib2, iclass 17, count 2 2006.173.12:21:53.30#ibcon#flushed, iclass 17, count 2 2006.173.12:21:53.30#ibcon#about to write, iclass 17, count 2 2006.173.12:21:53.30#ibcon#wrote, iclass 17, count 2 2006.173.12:21:53.30#ibcon#about to read 3, iclass 17, count 2 2006.173.12:21:53.33#ibcon#read 3, iclass 17, count 2 2006.173.12:21:53.33#ibcon#about to read 4, iclass 17, count 2 2006.173.12:21:53.33#ibcon#read 4, iclass 17, count 2 2006.173.12:21:53.33#ibcon#about to read 5, iclass 17, count 2 2006.173.12:21:53.33#ibcon#read 5, iclass 17, count 2 2006.173.12:21:53.33#ibcon#about to read 6, iclass 17, count 2 2006.173.12:21:53.33#ibcon#read 6, iclass 17, count 2 2006.173.12:21:53.33#ibcon#end of sib2, iclass 17, count 2 2006.173.12:21:53.33#ibcon#*after write, iclass 17, count 2 2006.173.12:21:53.33#ibcon#*before return 0, iclass 17, count 2 2006.173.12:21:53.33#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.12:21:53.33#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.12:21:53.33#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.12:21:53.33#ibcon#ireg 7 cls_cnt 0 2006.173.12:21:53.33#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.12:21:53.45#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.12:21:53.45#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.12:21:53.45#ibcon#enter wrdev, iclass 17, count 0 2006.173.12:21:53.45#ibcon#first serial, iclass 17, count 0 2006.173.12:21:53.45#ibcon#enter sib2, iclass 17, count 0 2006.173.12:21:53.45#ibcon#flushed, iclass 17, count 0 2006.173.12:21:53.45#ibcon#about to write, iclass 17, count 0 2006.173.12:21:53.45#ibcon#wrote, iclass 17, count 0 2006.173.12:21:53.45#ibcon#about to read 3, iclass 17, count 0 2006.173.12:21:53.47#ibcon#read 3, iclass 17, count 0 2006.173.12:21:53.47#ibcon#about to read 4, iclass 17, count 0 2006.173.12:21:53.47#ibcon#read 4, iclass 17, count 0 2006.173.12:21:53.47#ibcon#about to read 5, iclass 17, count 0 2006.173.12:21:53.47#ibcon#read 5, iclass 17, count 0 2006.173.12:21:53.47#ibcon#about to read 6, iclass 17, count 0 2006.173.12:21:53.47#ibcon#read 6, iclass 17, count 0 2006.173.12:21:53.47#ibcon#end of sib2, iclass 17, count 0 2006.173.12:21:53.47#ibcon#*mode == 0, iclass 17, count 0 2006.173.12:21:53.47#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.12:21:53.47#ibcon#[25=USB\r\n] 2006.173.12:21:53.47#ibcon#*before write, iclass 17, count 0 2006.173.12:21:53.47#ibcon#enter sib2, iclass 17, count 0 2006.173.12:21:53.47#ibcon#flushed, iclass 17, count 0 2006.173.12:21:53.47#ibcon#about to write, iclass 17, count 0 2006.173.12:21:53.47#ibcon#wrote, iclass 17, count 0 2006.173.12:21:53.47#ibcon#about to read 3, iclass 17, count 0 2006.173.12:21:53.50#ibcon#read 3, iclass 17, count 0 2006.173.12:21:53.50#ibcon#about to read 4, iclass 17, count 0 2006.173.12:21:53.50#ibcon#read 4, iclass 17, count 0 2006.173.12:21:53.50#ibcon#about to read 5, iclass 17, count 0 2006.173.12:21:53.50#ibcon#read 5, iclass 17, count 0 2006.173.12:21:53.50#ibcon#about to read 6, iclass 17, count 0 2006.173.12:21:53.50#ibcon#read 6, iclass 17, count 0 2006.173.12:21:53.50#ibcon#end of sib2, iclass 17, count 0 2006.173.12:21:53.50#ibcon#*after write, iclass 17, count 0 2006.173.12:21:53.50#ibcon#*before return 0, iclass 17, count 0 2006.173.12:21:53.50#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.12:21:53.50#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.12:21:53.50#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.12:21:53.50#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.12:21:53.50$vck44/valo=2,534.99 2006.173.12:21:53.50#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.12:21:53.50#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.12:21:53.50#ibcon#ireg 17 cls_cnt 0 2006.173.12:21:53.50#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.12:21:53.50#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.12:21:53.50#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.12:21:53.50#ibcon#enter wrdev, iclass 19, count 0 2006.173.12:21:53.50#ibcon#first serial, iclass 19, count 0 2006.173.12:21:53.50#ibcon#enter sib2, iclass 19, count 0 2006.173.12:21:53.50#ibcon#flushed, iclass 19, count 0 2006.173.12:21:53.50#ibcon#about to write, iclass 19, count 0 2006.173.12:21:53.50#ibcon#wrote, iclass 19, count 0 2006.173.12:21:53.50#ibcon#about to read 3, iclass 19, count 0 2006.173.12:21:53.52#ibcon#read 3, iclass 19, count 0 2006.173.12:21:53.52#ibcon#about to read 4, iclass 19, count 0 2006.173.12:21:53.52#ibcon#read 4, iclass 19, count 0 2006.173.12:21:53.52#ibcon#about to read 5, iclass 19, count 0 2006.173.12:21:53.52#ibcon#read 5, iclass 19, count 0 2006.173.12:21:53.52#ibcon#about to read 6, iclass 19, count 0 2006.173.12:21:53.52#ibcon#read 6, iclass 19, count 0 2006.173.12:21:53.52#ibcon#end of sib2, iclass 19, count 0 2006.173.12:21:53.52#ibcon#*mode == 0, iclass 19, count 0 2006.173.12:21:53.52#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.12:21:53.52#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.12:21:53.52#ibcon#*before write, iclass 19, count 0 2006.173.12:21:53.52#ibcon#enter sib2, iclass 19, count 0 2006.173.12:21:53.52#ibcon#flushed, iclass 19, count 0 2006.173.12:21:53.52#ibcon#about to write, iclass 19, count 0 2006.173.12:21:53.52#ibcon#wrote, iclass 19, count 0 2006.173.12:21:53.52#ibcon#about to read 3, iclass 19, count 0 2006.173.12:21:53.56#ibcon#read 3, iclass 19, count 0 2006.173.12:21:53.56#ibcon#about to read 4, iclass 19, count 0 2006.173.12:21:53.56#ibcon#read 4, iclass 19, count 0 2006.173.12:21:53.56#ibcon#about to read 5, iclass 19, count 0 2006.173.12:21:53.56#ibcon#read 5, iclass 19, count 0 2006.173.12:21:53.56#ibcon#about to read 6, iclass 19, count 0 2006.173.12:21:53.56#ibcon#read 6, iclass 19, count 0 2006.173.12:21:53.56#ibcon#end of sib2, iclass 19, count 0 2006.173.12:21:53.56#ibcon#*after write, iclass 19, count 0 2006.173.12:21:53.56#ibcon#*before return 0, iclass 19, count 0 2006.173.12:21:53.56#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.12:21:53.56#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.12:21:53.56#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.12:21:53.56#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.12:21:53.56$vck44/va=2,6 2006.173.12:21:53.56#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.12:21:53.56#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.12:21:53.56#ibcon#ireg 11 cls_cnt 2 2006.173.12:21:53.56#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.12:21:53.62#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.12:21:53.62#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.12:21:53.62#ibcon#enter wrdev, iclass 21, count 2 2006.173.12:21:53.62#ibcon#first serial, iclass 21, count 2 2006.173.12:21:53.62#ibcon#enter sib2, iclass 21, count 2 2006.173.12:21:53.62#ibcon#flushed, iclass 21, count 2 2006.173.12:21:53.62#ibcon#about to write, iclass 21, count 2 2006.173.12:21:53.62#ibcon#wrote, iclass 21, count 2 2006.173.12:21:53.62#ibcon#about to read 3, iclass 21, count 2 2006.173.12:21:53.64#ibcon#read 3, iclass 21, count 2 2006.173.12:21:53.64#ibcon#about to read 4, iclass 21, count 2 2006.173.12:21:53.64#ibcon#read 4, iclass 21, count 2 2006.173.12:21:53.64#ibcon#about to read 5, iclass 21, count 2 2006.173.12:21:53.64#ibcon#read 5, iclass 21, count 2 2006.173.12:21:53.64#ibcon#about to read 6, iclass 21, count 2 2006.173.12:21:53.64#ibcon#read 6, iclass 21, count 2 2006.173.12:21:53.64#ibcon#end of sib2, iclass 21, count 2 2006.173.12:21:53.64#ibcon#*mode == 0, iclass 21, count 2 2006.173.12:21:53.64#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.12:21:53.64#ibcon#[25=AT02-06\r\n] 2006.173.12:21:53.64#ibcon#*before write, iclass 21, count 2 2006.173.12:21:53.64#ibcon#enter sib2, iclass 21, count 2 2006.173.12:21:53.64#ibcon#flushed, iclass 21, count 2 2006.173.12:21:53.64#ibcon#about to write, iclass 21, count 2 2006.173.12:21:53.64#ibcon#wrote, iclass 21, count 2 2006.173.12:21:53.64#ibcon#about to read 3, iclass 21, count 2 2006.173.12:21:53.67#ibcon#read 3, iclass 21, count 2 2006.173.12:21:53.67#ibcon#about to read 4, iclass 21, count 2 2006.173.12:21:53.67#ibcon#read 4, iclass 21, count 2 2006.173.12:21:53.67#ibcon#about to read 5, iclass 21, count 2 2006.173.12:21:53.67#ibcon#read 5, iclass 21, count 2 2006.173.12:21:53.67#ibcon#about to read 6, iclass 21, count 2 2006.173.12:21:53.67#ibcon#read 6, iclass 21, count 2 2006.173.12:21:53.67#ibcon#end of sib2, iclass 21, count 2 2006.173.12:21:53.67#ibcon#*after write, iclass 21, count 2 2006.173.12:21:53.67#ibcon#*before return 0, iclass 21, count 2 2006.173.12:21:53.67#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.12:21:53.67#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.12:21:53.67#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.12:21:53.67#ibcon#ireg 7 cls_cnt 0 2006.173.12:21:53.67#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.12:21:53.79#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.12:21:53.79#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.12:21:53.79#ibcon#enter wrdev, iclass 21, count 0 2006.173.12:21:53.79#ibcon#first serial, iclass 21, count 0 2006.173.12:21:53.79#ibcon#enter sib2, iclass 21, count 0 2006.173.12:21:53.79#ibcon#flushed, iclass 21, count 0 2006.173.12:21:53.79#ibcon#about to write, iclass 21, count 0 2006.173.12:21:53.79#ibcon#wrote, iclass 21, count 0 2006.173.12:21:53.79#ibcon#about to read 3, iclass 21, count 0 2006.173.12:21:53.81#ibcon#read 3, iclass 21, count 0 2006.173.12:21:53.81#ibcon#about to read 4, iclass 21, count 0 2006.173.12:21:53.81#ibcon#read 4, iclass 21, count 0 2006.173.12:21:53.81#ibcon#about to read 5, iclass 21, count 0 2006.173.12:21:53.81#ibcon#read 5, iclass 21, count 0 2006.173.12:21:53.81#ibcon#about to read 6, iclass 21, count 0 2006.173.12:21:53.81#ibcon#read 6, iclass 21, count 0 2006.173.12:21:53.81#ibcon#end of sib2, iclass 21, count 0 2006.173.12:21:53.81#ibcon#*mode == 0, iclass 21, count 0 2006.173.12:21:53.81#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.12:21:53.81#ibcon#[25=USB\r\n] 2006.173.12:21:53.81#ibcon#*before write, iclass 21, count 0 2006.173.12:21:53.81#ibcon#enter sib2, iclass 21, count 0 2006.173.12:21:53.81#ibcon#flushed, iclass 21, count 0 2006.173.12:21:53.81#ibcon#about to write, iclass 21, count 0 2006.173.12:21:53.81#ibcon#wrote, iclass 21, count 0 2006.173.12:21:53.81#ibcon#about to read 3, iclass 21, count 0 2006.173.12:21:53.84#ibcon#read 3, iclass 21, count 0 2006.173.12:21:53.84#ibcon#about to read 4, iclass 21, count 0 2006.173.12:21:53.84#ibcon#read 4, iclass 21, count 0 2006.173.12:21:53.84#ibcon#about to read 5, iclass 21, count 0 2006.173.12:21:53.84#ibcon#read 5, iclass 21, count 0 2006.173.12:21:53.84#ibcon#about to read 6, iclass 21, count 0 2006.173.12:21:53.84#ibcon#read 6, iclass 21, count 0 2006.173.12:21:53.84#ibcon#end of sib2, iclass 21, count 0 2006.173.12:21:53.84#ibcon#*after write, iclass 21, count 0 2006.173.12:21:53.84#ibcon#*before return 0, iclass 21, count 0 2006.173.12:21:53.84#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.12:21:53.84#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.12:21:53.84#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.12:21:53.84#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.12:21:53.84$vck44/valo=3,564.99 2006.173.12:21:53.84#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.12:21:53.84#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.12:21:53.84#ibcon#ireg 17 cls_cnt 0 2006.173.12:21:53.84#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.12:21:53.84#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.12:21:53.84#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.12:21:53.84#ibcon#enter wrdev, iclass 23, count 0 2006.173.12:21:53.84#ibcon#first serial, iclass 23, count 0 2006.173.12:21:53.84#ibcon#enter sib2, iclass 23, count 0 2006.173.12:21:53.84#ibcon#flushed, iclass 23, count 0 2006.173.12:21:53.84#ibcon#about to write, iclass 23, count 0 2006.173.12:21:53.84#ibcon#wrote, iclass 23, count 0 2006.173.12:21:53.84#ibcon#about to read 3, iclass 23, count 0 2006.173.12:21:53.86#ibcon#read 3, iclass 23, count 0 2006.173.12:21:53.86#ibcon#about to read 4, iclass 23, count 0 2006.173.12:21:53.86#ibcon#read 4, iclass 23, count 0 2006.173.12:21:53.86#ibcon#about to read 5, iclass 23, count 0 2006.173.12:21:53.86#ibcon#read 5, iclass 23, count 0 2006.173.12:21:53.86#ibcon#about to read 6, iclass 23, count 0 2006.173.12:21:53.86#ibcon#read 6, iclass 23, count 0 2006.173.12:21:53.86#ibcon#end of sib2, iclass 23, count 0 2006.173.12:21:53.86#ibcon#*mode == 0, iclass 23, count 0 2006.173.12:21:53.86#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.12:21:53.86#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.12:21:53.86#ibcon#*before write, iclass 23, count 0 2006.173.12:21:53.86#ibcon#enter sib2, iclass 23, count 0 2006.173.12:21:53.86#ibcon#flushed, iclass 23, count 0 2006.173.12:21:53.86#ibcon#about to write, iclass 23, count 0 2006.173.12:21:53.86#ibcon#wrote, iclass 23, count 0 2006.173.12:21:53.86#ibcon#about to read 3, iclass 23, count 0 2006.173.12:21:53.90#ibcon#read 3, iclass 23, count 0 2006.173.12:21:53.90#ibcon#about to read 4, iclass 23, count 0 2006.173.12:21:53.90#ibcon#read 4, iclass 23, count 0 2006.173.12:21:53.90#ibcon#about to read 5, iclass 23, count 0 2006.173.12:21:53.90#ibcon#read 5, iclass 23, count 0 2006.173.12:21:53.90#ibcon#about to read 6, iclass 23, count 0 2006.173.12:21:53.90#ibcon#read 6, iclass 23, count 0 2006.173.12:21:53.90#ibcon#end of sib2, iclass 23, count 0 2006.173.12:21:53.90#ibcon#*after write, iclass 23, count 0 2006.173.12:21:53.90#ibcon#*before return 0, iclass 23, count 0 2006.173.12:21:53.90#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.12:21:53.90#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.12:21:53.90#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.12:21:53.90#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.12:21:53.90$vck44/va=3,5 2006.173.12:21:53.90#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.12:21:53.90#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.12:21:53.90#ibcon#ireg 11 cls_cnt 2 2006.173.12:21:53.90#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.12:21:53.96#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.12:21:53.96#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.12:21:53.96#ibcon#enter wrdev, iclass 25, count 2 2006.173.12:21:53.96#ibcon#first serial, iclass 25, count 2 2006.173.12:21:53.96#ibcon#enter sib2, iclass 25, count 2 2006.173.12:21:53.96#ibcon#flushed, iclass 25, count 2 2006.173.12:21:53.96#ibcon#about to write, iclass 25, count 2 2006.173.12:21:53.96#ibcon#wrote, iclass 25, count 2 2006.173.12:21:53.96#ibcon#about to read 3, iclass 25, count 2 2006.173.12:21:53.98#ibcon#read 3, iclass 25, count 2 2006.173.12:21:53.98#ibcon#about to read 4, iclass 25, count 2 2006.173.12:21:53.98#ibcon#read 4, iclass 25, count 2 2006.173.12:21:53.98#ibcon#about to read 5, iclass 25, count 2 2006.173.12:21:53.98#ibcon#read 5, iclass 25, count 2 2006.173.12:21:53.98#ibcon#about to read 6, iclass 25, count 2 2006.173.12:21:53.98#ibcon#read 6, iclass 25, count 2 2006.173.12:21:53.98#ibcon#end of sib2, iclass 25, count 2 2006.173.12:21:53.98#ibcon#*mode == 0, iclass 25, count 2 2006.173.12:21:53.98#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.12:21:53.98#ibcon#[25=AT03-05\r\n] 2006.173.12:21:53.98#ibcon#*before write, iclass 25, count 2 2006.173.12:21:53.98#ibcon#enter sib2, iclass 25, count 2 2006.173.12:21:53.98#ibcon#flushed, iclass 25, count 2 2006.173.12:21:53.98#ibcon#about to write, iclass 25, count 2 2006.173.12:21:53.98#ibcon#wrote, iclass 25, count 2 2006.173.12:21:53.98#ibcon#about to read 3, iclass 25, count 2 2006.173.12:21:54.01#ibcon#read 3, iclass 25, count 2 2006.173.12:21:54.01#ibcon#about to read 4, iclass 25, count 2 2006.173.12:21:54.01#ibcon#read 4, iclass 25, count 2 2006.173.12:21:54.01#ibcon#about to read 5, iclass 25, count 2 2006.173.12:21:54.01#ibcon#read 5, iclass 25, count 2 2006.173.12:21:54.01#ibcon#about to read 6, iclass 25, count 2 2006.173.12:21:54.01#ibcon#read 6, iclass 25, count 2 2006.173.12:21:54.01#ibcon#end of sib2, iclass 25, count 2 2006.173.12:21:54.01#ibcon#*after write, iclass 25, count 2 2006.173.12:21:54.01#ibcon#*before return 0, iclass 25, count 2 2006.173.12:21:54.01#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.12:21:54.01#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.12:21:54.01#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.12:21:54.01#ibcon#ireg 7 cls_cnt 0 2006.173.12:21:54.01#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.12:21:54.13#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.12:21:54.13#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.12:21:54.13#ibcon#enter wrdev, iclass 25, count 0 2006.173.12:21:54.13#ibcon#first serial, iclass 25, count 0 2006.173.12:21:54.13#ibcon#enter sib2, iclass 25, count 0 2006.173.12:21:54.13#ibcon#flushed, iclass 25, count 0 2006.173.12:21:54.13#ibcon#about to write, iclass 25, count 0 2006.173.12:21:54.13#ibcon#wrote, iclass 25, count 0 2006.173.12:21:54.13#ibcon#about to read 3, iclass 25, count 0 2006.173.12:21:54.15#ibcon#read 3, iclass 25, count 0 2006.173.12:21:54.15#ibcon#about to read 4, iclass 25, count 0 2006.173.12:21:54.15#ibcon#read 4, iclass 25, count 0 2006.173.12:21:54.15#ibcon#about to read 5, iclass 25, count 0 2006.173.12:21:54.15#ibcon#read 5, iclass 25, count 0 2006.173.12:21:54.15#ibcon#about to read 6, iclass 25, count 0 2006.173.12:21:54.15#ibcon#read 6, iclass 25, count 0 2006.173.12:21:54.15#ibcon#end of sib2, iclass 25, count 0 2006.173.12:21:54.15#ibcon#*mode == 0, iclass 25, count 0 2006.173.12:21:54.15#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.12:21:54.15#ibcon#[25=USB\r\n] 2006.173.12:21:54.15#ibcon#*before write, iclass 25, count 0 2006.173.12:21:54.15#ibcon#enter sib2, iclass 25, count 0 2006.173.12:21:54.15#ibcon#flushed, iclass 25, count 0 2006.173.12:21:54.15#ibcon#about to write, iclass 25, count 0 2006.173.12:21:54.15#ibcon#wrote, iclass 25, count 0 2006.173.12:21:54.15#ibcon#about to read 3, iclass 25, count 0 2006.173.12:21:54.18#ibcon#read 3, iclass 25, count 0 2006.173.12:21:54.18#ibcon#about to read 4, iclass 25, count 0 2006.173.12:21:54.18#ibcon#read 4, iclass 25, count 0 2006.173.12:21:54.18#ibcon#about to read 5, iclass 25, count 0 2006.173.12:21:54.18#ibcon#read 5, iclass 25, count 0 2006.173.12:21:54.18#ibcon#about to read 6, iclass 25, count 0 2006.173.12:21:54.18#ibcon#read 6, iclass 25, count 0 2006.173.12:21:54.18#ibcon#end of sib2, iclass 25, count 0 2006.173.12:21:54.18#ibcon#*after write, iclass 25, count 0 2006.173.12:21:54.18#ibcon#*before return 0, iclass 25, count 0 2006.173.12:21:54.18#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.12:21:54.18#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.12:21:54.18#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.12:21:54.18#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.12:21:54.18$vck44/valo=4,624.99 2006.173.12:21:54.18#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.12:21:54.18#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.12:21:54.18#ibcon#ireg 17 cls_cnt 0 2006.173.12:21:54.18#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.12:21:54.18#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.12:21:54.18#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.12:21:54.18#ibcon#enter wrdev, iclass 27, count 0 2006.173.12:21:54.18#ibcon#first serial, iclass 27, count 0 2006.173.12:21:54.18#ibcon#enter sib2, iclass 27, count 0 2006.173.12:21:54.18#ibcon#flushed, iclass 27, count 0 2006.173.12:21:54.18#ibcon#about to write, iclass 27, count 0 2006.173.12:21:54.18#ibcon#wrote, iclass 27, count 0 2006.173.12:21:54.18#ibcon#about to read 3, iclass 27, count 0 2006.173.12:21:54.20#ibcon#read 3, iclass 27, count 0 2006.173.12:21:54.20#ibcon#about to read 4, iclass 27, count 0 2006.173.12:21:54.20#ibcon#read 4, iclass 27, count 0 2006.173.12:21:54.20#ibcon#about to read 5, iclass 27, count 0 2006.173.12:21:54.20#ibcon#read 5, iclass 27, count 0 2006.173.12:21:54.20#ibcon#about to read 6, iclass 27, count 0 2006.173.12:21:54.20#ibcon#read 6, iclass 27, count 0 2006.173.12:21:54.20#ibcon#end of sib2, iclass 27, count 0 2006.173.12:21:54.20#ibcon#*mode == 0, iclass 27, count 0 2006.173.12:21:54.20#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.12:21:54.20#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.12:21:54.20#ibcon#*before write, iclass 27, count 0 2006.173.12:21:54.20#ibcon#enter sib2, iclass 27, count 0 2006.173.12:21:54.20#ibcon#flushed, iclass 27, count 0 2006.173.12:21:54.20#ibcon#about to write, iclass 27, count 0 2006.173.12:21:54.20#ibcon#wrote, iclass 27, count 0 2006.173.12:21:54.20#ibcon#about to read 3, iclass 27, count 0 2006.173.12:21:54.24#ibcon#read 3, iclass 27, count 0 2006.173.12:21:54.24#ibcon#about to read 4, iclass 27, count 0 2006.173.12:21:54.24#ibcon#read 4, iclass 27, count 0 2006.173.12:21:54.24#ibcon#about to read 5, iclass 27, count 0 2006.173.12:21:54.24#ibcon#read 5, iclass 27, count 0 2006.173.12:21:54.24#ibcon#about to read 6, iclass 27, count 0 2006.173.12:21:54.24#ibcon#read 6, iclass 27, count 0 2006.173.12:21:54.24#ibcon#end of sib2, iclass 27, count 0 2006.173.12:21:54.24#ibcon#*after write, iclass 27, count 0 2006.173.12:21:54.24#ibcon#*before return 0, iclass 27, count 0 2006.173.12:21:54.24#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.12:21:54.24#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.12:21:54.24#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.12:21:54.24#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.12:21:54.24$vck44/va=4,6 2006.173.12:21:54.24#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.12:21:54.24#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.12:21:54.24#ibcon#ireg 11 cls_cnt 2 2006.173.12:21:54.24#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.12:21:54.30#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.12:21:54.30#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.12:21:54.30#ibcon#enter wrdev, iclass 29, count 2 2006.173.12:21:54.30#ibcon#first serial, iclass 29, count 2 2006.173.12:21:54.30#ibcon#enter sib2, iclass 29, count 2 2006.173.12:21:54.30#ibcon#flushed, iclass 29, count 2 2006.173.12:21:54.30#ibcon#about to write, iclass 29, count 2 2006.173.12:21:54.30#ibcon#wrote, iclass 29, count 2 2006.173.12:21:54.30#ibcon#about to read 3, iclass 29, count 2 2006.173.12:21:54.32#ibcon#read 3, iclass 29, count 2 2006.173.12:21:54.32#ibcon#about to read 4, iclass 29, count 2 2006.173.12:21:54.32#ibcon#read 4, iclass 29, count 2 2006.173.12:21:54.32#ibcon#about to read 5, iclass 29, count 2 2006.173.12:21:54.32#ibcon#read 5, iclass 29, count 2 2006.173.12:21:54.32#ibcon#about to read 6, iclass 29, count 2 2006.173.12:21:54.32#ibcon#read 6, iclass 29, count 2 2006.173.12:21:54.32#ibcon#end of sib2, iclass 29, count 2 2006.173.12:21:54.32#ibcon#*mode == 0, iclass 29, count 2 2006.173.12:21:54.32#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.12:21:54.32#ibcon#[25=AT04-06\r\n] 2006.173.12:21:54.32#ibcon#*before write, iclass 29, count 2 2006.173.12:21:54.32#ibcon#enter sib2, iclass 29, count 2 2006.173.12:21:54.32#ibcon#flushed, iclass 29, count 2 2006.173.12:21:54.32#ibcon#about to write, iclass 29, count 2 2006.173.12:21:54.32#ibcon#wrote, iclass 29, count 2 2006.173.12:21:54.32#ibcon#about to read 3, iclass 29, count 2 2006.173.12:21:54.35#ibcon#read 3, iclass 29, count 2 2006.173.12:21:54.35#ibcon#about to read 4, iclass 29, count 2 2006.173.12:21:54.35#ibcon#read 4, iclass 29, count 2 2006.173.12:21:54.35#ibcon#about to read 5, iclass 29, count 2 2006.173.12:21:54.35#ibcon#read 5, iclass 29, count 2 2006.173.12:21:54.35#ibcon#about to read 6, iclass 29, count 2 2006.173.12:21:54.35#ibcon#read 6, iclass 29, count 2 2006.173.12:21:54.35#ibcon#end of sib2, iclass 29, count 2 2006.173.12:21:54.35#ibcon#*after write, iclass 29, count 2 2006.173.12:21:54.35#ibcon#*before return 0, iclass 29, count 2 2006.173.12:21:54.35#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.12:21:54.35#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.12:21:54.35#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.12:21:54.35#ibcon#ireg 7 cls_cnt 0 2006.173.12:21:54.35#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.12:21:54.47#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.12:21:54.47#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.12:21:54.47#ibcon#enter wrdev, iclass 29, count 0 2006.173.12:21:54.47#ibcon#first serial, iclass 29, count 0 2006.173.12:21:54.47#ibcon#enter sib2, iclass 29, count 0 2006.173.12:21:54.47#ibcon#flushed, iclass 29, count 0 2006.173.12:21:54.47#ibcon#about to write, iclass 29, count 0 2006.173.12:21:54.47#ibcon#wrote, iclass 29, count 0 2006.173.12:21:54.47#ibcon#about to read 3, iclass 29, count 0 2006.173.12:21:54.49#ibcon#read 3, iclass 29, count 0 2006.173.12:21:54.49#ibcon#about to read 4, iclass 29, count 0 2006.173.12:21:54.49#ibcon#read 4, iclass 29, count 0 2006.173.12:21:54.49#ibcon#about to read 5, iclass 29, count 0 2006.173.12:21:54.49#ibcon#read 5, iclass 29, count 0 2006.173.12:21:54.49#ibcon#about to read 6, iclass 29, count 0 2006.173.12:21:54.49#ibcon#read 6, iclass 29, count 0 2006.173.12:21:54.49#ibcon#end of sib2, iclass 29, count 0 2006.173.12:21:54.49#ibcon#*mode == 0, iclass 29, count 0 2006.173.12:21:54.49#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.12:21:54.49#ibcon#[25=USB\r\n] 2006.173.12:21:54.49#ibcon#*before write, iclass 29, count 0 2006.173.12:21:54.49#ibcon#enter sib2, iclass 29, count 0 2006.173.12:21:54.49#ibcon#flushed, iclass 29, count 0 2006.173.12:21:54.49#ibcon#about to write, iclass 29, count 0 2006.173.12:21:54.49#ibcon#wrote, iclass 29, count 0 2006.173.12:21:54.49#ibcon#about to read 3, iclass 29, count 0 2006.173.12:21:54.52#ibcon#read 3, iclass 29, count 0 2006.173.12:21:54.52#ibcon#about to read 4, iclass 29, count 0 2006.173.12:21:54.52#ibcon#read 4, iclass 29, count 0 2006.173.12:21:54.52#ibcon#about to read 5, iclass 29, count 0 2006.173.12:21:54.52#ibcon#read 5, iclass 29, count 0 2006.173.12:21:54.52#ibcon#about to read 6, iclass 29, count 0 2006.173.12:21:54.52#ibcon#read 6, iclass 29, count 0 2006.173.12:21:54.52#ibcon#end of sib2, iclass 29, count 0 2006.173.12:21:54.52#ibcon#*after write, iclass 29, count 0 2006.173.12:21:54.52#ibcon#*before return 0, iclass 29, count 0 2006.173.12:21:54.52#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.12:21:54.52#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.12:21:54.52#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.12:21:54.52#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.12:21:54.52$vck44/valo=5,734.99 2006.173.12:21:54.52#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.12:21:54.52#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.12:21:54.52#ibcon#ireg 17 cls_cnt 0 2006.173.12:21:54.52#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.12:21:54.52#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.12:21:54.52#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.12:21:54.52#ibcon#enter wrdev, iclass 31, count 0 2006.173.12:21:54.52#ibcon#first serial, iclass 31, count 0 2006.173.12:21:54.52#ibcon#enter sib2, iclass 31, count 0 2006.173.12:21:54.52#ibcon#flushed, iclass 31, count 0 2006.173.12:21:54.52#ibcon#about to write, iclass 31, count 0 2006.173.12:21:54.52#ibcon#wrote, iclass 31, count 0 2006.173.12:21:54.52#ibcon#about to read 3, iclass 31, count 0 2006.173.12:21:54.54#ibcon#read 3, iclass 31, count 0 2006.173.12:21:54.54#ibcon#about to read 4, iclass 31, count 0 2006.173.12:21:54.54#ibcon#read 4, iclass 31, count 0 2006.173.12:21:54.54#ibcon#about to read 5, iclass 31, count 0 2006.173.12:21:54.54#ibcon#read 5, iclass 31, count 0 2006.173.12:21:54.54#ibcon#about to read 6, iclass 31, count 0 2006.173.12:21:54.54#ibcon#read 6, iclass 31, count 0 2006.173.12:21:54.54#ibcon#end of sib2, iclass 31, count 0 2006.173.12:21:54.54#ibcon#*mode == 0, iclass 31, count 0 2006.173.12:21:54.54#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.12:21:54.54#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.12:21:54.54#ibcon#*before write, iclass 31, count 0 2006.173.12:21:54.54#ibcon#enter sib2, iclass 31, count 0 2006.173.12:21:54.54#ibcon#flushed, iclass 31, count 0 2006.173.12:21:54.54#ibcon#about to write, iclass 31, count 0 2006.173.12:21:54.54#ibcon#wrote, iclass 31, count 0 2006.173.12:21:54.54#ibcon#about to read 3, iclass 31, count 0 2006.173.12:21:54.58#ibcon#read 3, iclass 31, count 0 2006.173.12:21:54.58#ibcon#about to read 4, iclass 31, count 0 2006.173.12:21:54.58#ibcon#read 4, iclass 31, count 0 2006.173.12:21:54.58#ibcon#about to read 5, iclass 31, count 0 2006.173.12:21:54.58#ibcon#read 5, iclass 31, count 0 2006.173.12:21:54.58#ibcon#about to read 6, iclass 31, count 0 2006.173.12:21:54.58#ibcon#read 6, iclass 31, count 0 2006.173.12:21:54.58#ibcon#end of sib2, iclass 31, count 0 2006.173.12:21:54.58#ibcon#*after write, iclass 31, count 0 2006.173.12:21:54.58#ibcon#*before return 0, iclass 31, count 0 2006.173.12:21:54.58#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.12:21:54.58#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.12:21:54.58#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.12:21:54.58#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.12:21:54.58$vck44/va=5,4 2006.173.12:21:54.58#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.173.12:21:54.58#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.173.12:21:54.58#ibcon#ireg 11 cls_cnt 2 2006.173.12:21:54.58#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.12:21:54.64#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.12:21:54.64#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.12:21:54.64#ibcon#enter wrdev, iclass 33, count 2 2006.173.12:21:54.64#ibcon#first serial, iclass 33, count 2 2006.173.12:21:54.64#ibcon#enter sib2, iclass 33, count 2 2006.173.12:21:54.64#ibcon#flushed, iclass 33, count 2 2006.173.12:21:54.64#ibcon#about to write, iclass 33, count 2 2006.173.12:21:54.64#ibcon#wrote, iclass 33, count 2 2006.173.12:21:54.64#ibcon#about to read 3, iclass 33, count 2 2006.173.12:21:54.66#ibcon#read 3, iclass 33, count 2 2006.173.12:21:54.66#ibcon#about to read 4, iclass 33, count 2 2006.173.12:21:54.66#ibcon#read 4, iclass 33, count 2 2006.173.12:21:54.66#ibcon#about to read 5, iclass 33, count 2 2006.173.12:21:54.66#ibcon#read 5, iclass 33, count 2 2006.173.12:21:54.66#ibcon#about to read 6, iclass 33, count 2 2006.173.12:21:54.66#ibcon#read 6, iclass 33, count 2 2006.173.12:21:54.66#ibcon#end of sib2, iclass 33, count 2 2006.173.12:21:54.66#ibcon#*mode == 0, iclass 33, count 2 2006.173.12:21:54.66#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.173.12:21:54.66#ibcon#[25=AT05-04\r\n] 2006.173.12:21:54.66#ibcon#*before write, iclass 33, count 2 2006.173.12:21:54.66#ibcon#enter sib2, iclass 33, count 2 2006.173.12:21:54.66#ibcon#flushed, iclass 33, count 2 2006.173.12:21:54.66#ibcon#about to write, iclass 33, count 2 2006.173.12:21:54.66#ibcon#wrote, iclass 33, count 2 2006.173.12:21:54.66#ibcon#about to read 3, iclass 33, count 2 2006.173.12:21:54.69#ibcon#read 3, iclass 33, count 2 2006.173.12:21:54.69#ibcon#about to read 4, iclass 33, count 2 2006.173.12:21:54.69#ibcon#read 4, iclass 33, count 2 2006.173.12:21:54.69#ibcon#about to read 5, iclass 33, count 2 2006.173.12:21:54.69#ibcon#read 5, iclass 33, count 2 2006.173.12:21:54.69#ibcon#about to read 6, iclass 33, count 2 2006.173.12:21:54.69#ibcon#read 6, iclass 33, count 2 2006.173.12:21:54.69#ibcon#end of sib2, iclass 33, count 2 2006.173.12:21:54.69#ibcon#*after write, iclass 33, count 2 2006.173.12:21:54.69#ibcon#*before return 0, iclass 33, count 2 2006.173.12:21:54.69#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.12:21:54.69#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.173.12:21:54.69#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.173.12:21:54.69#ibcon#ireg 7 cls_cnt 0 2006.173.12:21:54.69#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.12:21:54.81#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.12:21:54.81#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.12:21:54.81#ibcon#enter wrdev, iclass 33, count 0 2006.173.12:21:54.81#ibcon#first serial, iclass 33, count 0 2006.173.12:21:54.81#ibcon#enter sib2, iclass 33, count 0 2006.173.12:21:54.81#ibcon#flushed, iclass 33, count 0 2006.173.12:21:54.81#ibcon#about to write, iclass 33, count 0 2006.173.12:21:54.81#ibcon#wrote, iclass 33, count 0 2006.173.12:21:54.81#ibcon#about to read 3, iclass 33, count 0 2006.173.12:21:54.83#ibcon#read 3, iclass 33, count 0 2006.173.12:21:54.83#ibcon#about to read 4, iclass 33, count 0 2006.173.12:21:54.83#ibcon#read 4, iclass 33, count 0 2006.173.12:21:54.83#ibcon#about to read 5, iclass 33, count 0 2006.173.12:21:54.83#ibcon#read 5, iclass 33, count 0 2006.173.12:21:54.83#ibcon#about to read 6, iclass 33, count 0 2006.173.12:21:54.83#ibcon#read 6, iclass 33, count 0 2006.173.12:21:54.83#ibcon#end of sib2, iclass 33, count 0 2006.173.12:21:54.83#ibcon#*mode == 0, iclass 33, count 0 2006.173.12:21:54.83#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.12:21:54.83#ibcon#[25=USB\r\n] 2006.173.12:21:54.83#ibcon#*before write, iclass 33, count 0 2006.173.12:21:54.83#ibcon#enter sib2, iclass 33, count 0 2006.173.12:21:54.83#ibcon#flushed, iclass 33, count 0 2006.173.12:21:54.83#ibcon#about to write, iclass 33, count 0 2006.173.12:21:54.83#ibcon#wrote, iclass 33, count 0 2006.173.12:21:54.83#ibcon#about to read 3, iclass 33, count 0 2006.173.12:21:54.86#ibcon#read 3, iclass 33, count 0 2006.173.12:21:54.86#ibcon#about to read 4, iclass 33, count 0 2006.173.12:21:54.86#ibcon#read 4, iclass 33, count 0 2006.173.12:21:54.86#ibcon#about to read 5, iclass 33, count 0 2006.173.12:21:54.86#ibcon#read 5, iclass 33, count 0 2006.173.12:21:54.86#ibcon#about to read 6, iclass 33, count 0 2006.173.12:21:54.86#ibcon#read 6, iclass 33, count 0 2006.173.12:21:54.86#ibcon#end of sib2, iclass 33, count 0 2006.173.12:21:54.86#ibcon#*after write, iclass 33, count 0 2006.173.12:21:54.86#ibcon#*before return 0, iclass 33, count 0 2006.173.12:21:54.86#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.12:21:54.86#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.173.12:21:54.86#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.12:21:54.86#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.12:21:54.86$vck44/valo=6,814.99 2006.173.12:21:54.86#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.12:21:54.86#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.12:21:54.86#ibcon#ireg 17 cls_cnt 0 2006.173.12:21:54.86#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.12:21:54.86#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.12:21:54.86#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.12:21:54.86#ibcon#enter wrdev, iclass 35, count 0 2006.173.12:21:54.86#ibcon#first serial, iclass 35, count 0 2006.173.12:21:54.86#ibcon#enter sib2, iclass 35, count 0 2006.173.12:21:54.86#ibcon#flushed, iclass 35, count 0 2006.173.12:21:54.86#ibcon#about to write, iclass 35, count 0 2006.173.12:21:54.86#ibcon#wrote, iclass 35, count 0 2006.173.12:21:54.86#ibcon#about to read 3, iclass 35, count 0 2006.173.12:21:54.88#ibcon#read 3, iclass 35, count 0 2006.173.12:21:54.88#ibcon#about to read 4, iclass 35, count 0 2006.173.12:21:54.88#ibcon#read 4, iclass 35, count 0 2006.173.12:21:54.88#ibcon#about to read 5, iclass 35, count 0 2006.173.12:21:54.88#ibcon#read 5, iclass 35, count 0 2006.173.12:21:54.88#ibcon#about to read 6, iclass 35, count 0 2006.173.12:21:54.88#ibcon#read 6, iclass 35, count 0 2006.173.12:21:54.88#ibcon#end of sib2, iclass 35, count 0 2006.173.12:21:54.88#ibcon#*mode == 0, iclass 35, count 0 2006.173.12:21:54.88#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.12:21:54.88#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.12:21:54.88#ibcon#*before write, iclass 35, count 0 2006.173.12:21:54.88#ibcon#enter sib2, iclass 35, count 0 2006.173.12:21:54.88#ibcon#flushed, iclass 35, count 0 2006.173.12:21:54.88#ibcon#about to write, iclass 35, count 0 2006.173.12:21:54.88#ibcon#wrote, iclass 35, count 0 2006.173.12:21:54.88#ibcon#about to read 3, iclass 35, count 0 2006.173.12:21:54.92#ibcon#read 3, iclass 35, count 0 2006.173.12:21:54.92#ibcon#about to read 4, iclass 35, count 0 2006.173.12:21:54.92#ibcon#read 4, iclass 35, count 0 2006.173.12:21:54.92#ibcon#about to read 5, iclass 35, count 0 2006.173.12:21:54.92#ibcon#read 5, iclass 35, count 0 2006.173.12:21:54.92#ibcon#about to read 6, iclass 35, count 0 2006.173.12:21:54.92#ibcon#read 6, iclass 35, count 0 2006.173.12:21:54.92#ibcon#end of sib2, iclass 35, count 0 2006.173.12:21:54.92#ibcon#*after write, iclass 35, count 0 2006.173.12:21:54.92#ibcon#*before return 0, iclass 35, count 0 2006.173.12:21:54.92#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.12:21:54.92#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.12:21:54.92#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.12:21:54.92#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.12:21:54.92$vck44/va=6,3 2006.173.12:21:54.92#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.173.12:21:54.92#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.173.12:21:54.92#ibcon#ireg 11 cls_cnt 2 2006.173.12:21:54.92#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.12:21:54.98#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.12:21:54.98#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.12:21:54.98#ibcon#enter wrdev, iclass 37, count 2 2006.173.12:21:54.98#ibcon#first serial, iclass 37, count 2 2006.173.12:21:54.98#ibcon#enter sib2, iclass 37, count 2 2006.173.12:21:54.98#ibcon#flushed, iclass 37, count 2 2006.173.12:21:54.98#ibcon#about to write, iclass 37, count 2 2006.173.12:21:54.98#ibcon#wrote, iclass 37, count 2 2006.173.12:21:54.98#ibcon#about to read 3, iclass 37, count 2 2006.173.12:21:55.00#ibcon#read 3, iclass 37, count 2 2006.173.12:21:55.00#ibcon#about to read 4, iclass 37, count 2 2006.173.12:21:55.00#ibcon#read 4, iclass 37, count 2 2006.173.12:21:55.00#ibcon#about to read 5, iclass 37, count 2 2006.173.12:21:55.00#ibcon#read 5, iclass 37, count 2 2006.173.12:21:55.00#ibcon#about to read 6, iclass 37, count 2 2006.173.12:21:55.00#ibcon#read 6, iclass 37, count 2 2006.173.12:21:55.00#ibcon#end of sib2, iclass 37, count 2 2006.173.12:21:55.00#ibcon#*mode == 0, iclass 37, count 2 2006.173.12:21:55.00#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.173.12:21:55.00#ibcon#[25=AT06-03\r\n] 2006.173.12:21:55.00#ibcon#*before write, iclass 37, count 2 2006.173.12:21:55.00#ibcon#enter sib2, iclass 37, count 2 2006.173.12:21:55.00#ibcon#flushed, iclass 37, count 2 2006.173.12:21:55.00#ibcon#about to write, iclass 37, count 2 2006.173.12:21:55.00#ibcon#wrote, iclass 37, count 2 2006.173.12:21:55.00#ibcon#about to read 3, iclass 37, count 2 2006.173.12:21:55.03#ibcon#read 3, iclass 37, count 2 2006.173.12:21:55.03#ibcon#about to read 4, iclass 37, count 2 2006.173.12:21:55.03#ibcon#read 4, iclass 37, count 2 2006.173.12:21:55.03#ibcon#about to read 5, iclass 37, count 2 2006.173.12:21:55.03#ibcon#read 5, iclass 37, count 2 2006.173.12:21:55.03#ibcon#about to read 6, iclass 37, count 2 2006.173.12:21:55.03#ibcon#read 6, iclass 37, count 2 2006.173.12:21:55.03#ibcon#end of sib2, iclass 37, count 2 2006.173.12:21:55.03#ibcon#*after write, iclass 37, count 2 2006.173.12:21:55.03#ibcon#*before return 0, iclass 37, count 2 2006.173.12:21:55.03#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.12:21:55.03#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.173.12:21:55.03#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.173.12:21:55.03#ibcon#ireg 7 cls_cnt 0 2006.173.12:21:55.03#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.12:21:55.15#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.12:21:55.15#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.12:21:55.15#ibcon#enter wrdev, iclass 37, count 0 2006.173.12:21:55.15#ibcon#first serial, iclass 37, count 0 2006.173.12:21:55.15#ibcon#enter sib2, iclass 37, count 0 2006.173.12:21:55.15#ibcon#flushed, iclass 37, count 0 2006.173.12:21:55.15#ibcon#about to write, iclass 37, count 0 2006.173.12:21:55.15#ibcon#wrote, iclass 37, count 0 2006.173.12:21:55.15#ibcon#about to read 3, iclass 37, count 0 2006.173.12:21:55.17#ibcon#read 3, iclass 37, count 0 2006.173.12:21:55.17#ibcon#about to read 4, iclass 37, count 0 2006.173.12:21:55.17#ibcon#read 4, iclass 37, count 0 2006.173.12:21:55.17#ibcon#about to read 5, iclass 37, count 0 2006.173.12:21:55.17#ibcon#read 5, iclass 37, count 0 2006.173.12:21:55.17#ibcon#about to read 6, iclass 37, count 0 2006.173.12:21:55.17#ibcon#read 6, iclass 37, count 0 2006.173.12:21:55.17#ibcon#end of sib2, iclass 37, count 0 2006.173.12:21:55.17#ibcon#*mode == 0, iclass 37, count 0 2006.173.12:21:55.17#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.12:21:55.17#ibcon#[25=USB\r\n] 2006.173.12:21:55.17#ibcon#*before write, iclass 37, count 0 2006.173.12:21:55.17#ibcon#enter sib2, iclass 37, count 0 2006.173.12:21:55.17#ibcon#flushed, iclass 37, count 0 2006.173.12:21:55.17#ibcon#about to write, iclass 37, count 0 2006.173.12:21:55.17#ibcon#wrote, iclass 37, count 0 2006.173.12:21:55.17#ibcon#about to read 3, iclass 37, count 0 2006.173.12:21:55.20#ibcon#read 3, iclass 37, count 0 2006.173.12:21:55.20#ibcon#about to read 4, iclass 37, count 0 2006.173.12:21:55.20#ibcon#read 4, iclass 37, count 0 2006.173.12:21:55.20#ibcon#about to read 5, iclass 37, count 0 2006.173.12:21:55.20#ibcon#read 5, iclass 37, count 0 2006.173.12:21:55.20#ibcon#about to read 6, iclass 37, count 0 2006.173.12:21:55.20#ibcon#read 6, iclass 37, count 0 2006.173.12:21:55.20#ibcon#end of sib2, iclass 37, count 0 2006.173.12:21:55.20#ibcon#*after write, iclass 37, count 0 2006.173.12:21:55.20#ibcon#*before return 0, iclass 37, count 0 2006.173.12:21:55.20#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.12:21:55.20#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.173.12:21:55.20#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.12:21:55.20#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.12:21:55.20$vck44/valo=7,864.99 2006.173.12:21:55.20#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.12:21:55.20#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.12:21:55.20#ibcon#ireg 17 cls_cnt 0 2006.173.12:21:55.20#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.12:21:55.20#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.12:21:55.20#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.12:21:55.20#ibcon#enter wrdev, iclass 39, count 0 2006.173.12:21:55.20#ibcon#first serial, iclass 39, count 0 2006.173.12:21:55.20#ibcon#enter sib2, iclass 39, count 0 2006.173.12:21:55.20#ibcon#flushed, iclass 39, count 0 2006.173.12:21:55.20#ibcon#about to write, iclass 39, count 0 2006.173.12:21:55.20#ibcon#wrote, iclass 39, count 0 2006.173.12:21:55.20#ibcon#about to read 3, iclass 39, count 0 2006.173.12:21:55.22#ibcon#read 3, iclass 39, count 0 2006.173.12:21:55.22#ibcon#about to read 4, iclass 39, count 0 2006.173.12:21:55.22#ibcon#read 4, iclass 39, count 0 2006.173.12:21:55.22#ibcon#about to read 5, iclass 39, count 0 2006.173.12:21:55.22#ibcon#read 5, iclass 39, count 0 2006.173.12:21:55.22#ibcon#about to read 6, iclass 39, count 0 2006.173.12:21:55.22#ibcon#read 6, iclass 39, count 0 2006.173.12:21:55.22#ibcon#end of sib2, iclass 39, count 0 2006.173.12:21:55.22#ibcon#*mode == 0, iclass 39, count 0 2006.173.12:21:55.22#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.12:21:55.22#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.12:21:55.22#ibcon#*before write, iclass 39, count 0 2006.173.12:21:55.22#ibcon#enter sib2, iclass 39, count 0 2006.173.12:21:55.22#ibcon#flushed, iclass 39, count 0 2006.173.12:21:55.22#ibcon#about to write, iclass 39, count 0 2006.173.12:21:55.22#ibcon#wrote, iclass 39, count 0 2006.173.12:21:55.22#ibcon#about to read 3, iclass 39, count 0 2006.173.12:21:55.26#ibcon#read 3, iclass 39, count 0 2006.173.12:21:55.26#ibcon#about to read 4, iclass 39, count 0 2006.173.12:21:55.26#ibcon#read 4, iclass 39, count 0 2006.173.12:21:55.26#ibcon#about to read 5, iclass 39, count 0 2006.173.12:21:55.26#ibcon#read 5, iclass 39, count 0 2006.173.12:21:55.26#ibcon#about to read 6, iclass 39, count 0 2006.173.12:21:55.26#ibcon#read 6, iclass 39, count 0 2006.173.12:21:55.26#ibcon#end of sib2, iclass 39, count 0 2006.173.12:21:55.26#ibcon#*after write, iclass 39, count 0 2006.173.12:21:55.26#ibcon#*before return 0, iclass 39, count 0 2006.173.12:21:55.26#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.12:21:55.26#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.12:21:55.26#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.12:21:55.26#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.12:21:55.26$vck44/va=7,4 2006.173.12:21:55.26#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.12:21:55.26#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.12:21:55.26#ibcon#ireg 11 cls_cnt 2 2006.173.12:21:55.26#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.12:21:55.32#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.12:21:55.32#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.12:21:55.32#ibcon#enter wrdev, iclass 3, count 2 2006.173.12:21:55.32#ibcon#first serial, iclass 3, count 2 2006.173.12:21:55.32#ibcon#enter sib2, iclass 3, count 2 2006.173.12:21:55.32#ibcon#flushed, iclass 3, count 2 2006.173.12:21:55.32#ibcon#about to write, iclass 3, count 2 2006.173.12:21:55.32#ibcon#wrote, iclass 3, count 2 2006.173.12:21:55.32#ibcon#about to read 3, iclass 3, count 2 2006.173.12:21:55.34#ibcon#read 3, iclass 3, count 2 2006.173.12:21:55.34#ibcon#about to read 4, iclass 3, count 2 2006.173.12:21:55.34#ibcon#read 4, iclass 3, count 2 2006.173.12:21:55.34#ibcon#about to read 5, iclass 3, count 2 2006.173.12:21:55.34#ibcon#read 5, iclass 3, count 2 2006.173.12:21:55.34#ibcon#about to read 6, iclass 3, count 2 2006.173.12:21:55.34#ibcon#read 6, iclass 3, count 2 2006.173.12:21:55.34#ibcon#end of sib2, iclass 3, count 2 2006.173.12:21:55.34#ibcon#*mode == 0, iclass 3, count 2 2006.173.12:21:55.34#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.12:21:55.34#ibcon#[25=AT07-04\r\n] 2006.173.12:21:55.34#ibcon#*before write, iclass 3, count 2 2006.173.12:21:55.34#ibcon#enter sib2, iclass 3, count 2 2006.173.12:21:55.34#ibcon#flushed, iclass 3, count 2 2006.173.12:21:55.34#ibcon#about to write, iclass 3, count 2 2006.173.12:21:55.34#ibcon#wrote, iclass 3, count 2 2006.173.12:21:55.34#ibcon#about to read 3, iclass 3, count 2 2006.173.12:21:55.37#ibcon#read 3, iclass 3, count 2 2006.173.12:21:55.37#ibcon#about to read 4, iclass 3, count 2 2006.173.12:21:55.37#ibcon#read 4, iclass 3, count 2 2006.173.12:21:55.37#ibcon#about to read 5, iclass 3, count 2 2006.173.12:21:55.37#ibcon#read 5, iclass 3, count 2 2006.173.12:21:55.37#ibcon#about to read 6, iclass 3, count 2 2006.173.12:21:55.37#ibcon#read 6, iclass 3, count 2 2006.173.12:21:55.37#ibcon#end of sib2, iclass 3, count 2 2006.173.12:21:55.37#ibcon#*after write, iclass 3, count 2 2006.173.12:21:55.37#ibcon#*before return 0, iclass 3, count 2 2006.173.12:21:55.37#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.12:21:55.37#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.12:21:55.37#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.12:21:55.37#ibcon#ireg 7 cls_cnt 0 2006.173.12:21:55.37#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.12:21:55.49#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.12:21:55.49#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.12:21:55.49#ibcon#enter wrdev, iclass 3, count 0 2006.173.12:21:55.49#ibcon#first serial, iclass 3, count 0 2006.173.12:21:55.49#ibcon#enter sib2, iclass 3, count 0 2006.173.12:21:55.49#ibcon#flushed, iclass 3, count 0 2006.173.12:21:55.49#ibcon#about to write, iclass 3, count 0 2006.173.12:21:55.49#ibcon#wrote, iclass 3, count 0 2006.173.12:21:55.49#ibcon#about to read 3, iclass 3, count 0 2006.173.12:21:55.51#ibcon#read 3, iclass 3, count 0 2006.173.12:21:55.51#ibcon#about to read 4, iclass 3, count 0 2006.173.12:21:55.51#ibcon#read 4, iclass 3, count 0 2006.173.12:21:55.51#ibcon#about to read 5, iclass 3, count 0 2006.173.12:21:55.51#ibcon#read 5, iclass 3, count 0 2006.173.12:21:55.51#ibcon#about to read 6, iclass 3, count 0 2006.173.12:21:55.51#ibcon#read 6, iclass 3, count 0 2006.173.12:21:55.51#ibcon#end of sib2, iclass 3, count 0 2006.173.12:21:55.51#ibcon#*mode == 0, iclass 3, count 0 2006.173.12:21:55.51#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.12:21:55.51#ibcon#[25=USB\r\n] 2006.173.12:21:55.51#ibcon#*before write, iclass 3, count 0 2006.173.12:21:55.51#ibcon#enter sib2, iclass 3, count 0 2006.173.12:21:55.51#ibcon#flushed, iclass 3, count 0 2006.173.12:21:55.51#ibcon#about to write, iclass 3, count 0 2006.173.12:21:55.51#ibcon#wrote, iclass 3, count 0 2006.173.12:21:55.51#ibcon#about to read 3, iclass 3, count 0 2006.173.12:21:55.54#ibcon#read 3, iclass 3, count 0 2006.173.12:21:55.54#ibcon#about to read 4, iclass 3, count 0 2006.173.12:21:55.54#ibcon#read 4, iclass 3, count 0 2006.173.12:21:55.54#ibcon#about to read 5, iclass 3, count 0 2006.173.12:21:55.54#ibcon#read 5, iclass 3, count 0 2006.173.12:21:55.54#ibcon#about to read 6, iclass 3, count 0 2006.173.12:21:55.54#ibcon#read 6, iclass 3, count 0 2006.173.12:21:55.54#ibcon#end of sib2, iclass 3, count 0 2006.173.12:21:55.54#ibcon#*after write, iclass 3, count 0 2006.173.12:21:55.54#ibcon#*before return 0, iclass 3, count 0 2006.173.12:21:55.54#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.12:21:55.54#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.12:21:55.54#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.12:21:55.54#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.12:21:55.54$vck44/valo=8,884.99 2006.173.12:21:55.54#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.12:21:55.54#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.12:21:55.54#ibcon#ireg 17 cls_cnt 0 2006.173.12:21:55.54#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.12:21:55.54#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.12:21:55.54#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.12:21:55.54#ibcon#enter wrdev, iclass 5, count 0 2006.173.12:21:55.54#ibcon#first serial, iclass 5, count 0 2006.173.12:21:55.54#ibcon#enter sib2, iclass 5, count 0 2006.173.12:21:55.54#ibcon#flushed, iclass 5, count 0 2006.173.12:21:55.54#ibcon#about to write, iclass 5, count 0 2006.173.12:21:55.54#ibcon#wrote, iclass 5, count 0 2006.173.12:21:55.54#ibcon#about to read 3, iclass 5, count 0 2006.173.12:21:55.56#ibcon#read 3, iclass 5, count 0 2006.173.12:21:55.56#ibcon#about to read 4, iclass 5, count 0 2006.173.12:21:55.56#ibcon#read 4, iclass 5, count 0 2006.173.12:21:55.56#ibcon#about to read 5, iclass 5, count 0 2006.173.12:21:55.56#ibcon#read 5, iclass 5, count 0 2006.173.12:21:55.56#ibcon#about to read 6, iclass 5, count 0 2006.173.12:21:55.56#ibcon#read 6, iclass 5, count 0 2006.173.12:21:55.56#ibcon#end of sib2, iclass 5, count 0 2006.173.12:21:55.56#ibcon#*mode == 0, iclass 5, count 0 2006.173.12:21:55.56#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.12:21:55.56#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.12:21:55.56#ibcon#*before write, iclass 5, count 0 2006.173.12:21:55.56#ibcon#enter sib2, iclass 5, count 0 2006.173.12:21:55.56#ibcon#flushed, iclass 5, count 0 2006.173.12:21:55.56#ibcon#about to write, iclass 5, count 0 2006.173.12:21:55.56#ibcon#wrote, iclass 5, count 0 2006.173.12:21:55.56#ibcon#about to read 3, iclass 5, count 0 2006.173.12:21:55.60#ibcon#read 3, iclass 5, count 0 2006.173.12:21:55.60#ibcon#about to read 4, iclass 5, count 0 2006.173.12:21:55.60#ibcon#read 4, iclass 5, count 0 2006.173.12:21:55.60#ibcon#about to read 5, iclass 5, count 0 2006.173.12:21:55.60#ibcon#read 5, iclass 5, count 0 2006.173.12:21:55.60#ibcon#about to read 6, iclass 5, count 0 2006.173.12:21:55.60#ibcon#read 6, iclass 5, count 0 2006.173.12:21:55.60#ibcon#end of sib2, iclass 5, count 0 2006.173.12:21:55.60#ibcon#*after write, iclass 5, count 0 2006.173.12:21:55.60#ibcon#*before return 0, iclass 5, count 0 2006.173.12:21:55.60#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.12:21:55.60#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.12:21:55.60#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.12:21:55.60#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.12:21:55.60$vck44/va=8,4 2006.173.12:21:55.60#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.173.12:21:55.60#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.173.12:21:55.60#ibcon#ireg 11 cls_cnt 2 2006.173.12:21:55.60#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.12:21:55.66#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.12:21:55.66#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.12:21:55.66#ibcon#enter wrdev, iclass 7, count 2 2006.173.12:21:55.66#ibcon#first serial, iclass 7, count 2 2006.173.12:21:55.66#ibcon#enter sib2, iclass 7, count 2 2006.173.12:21:55.66#ibcon#flushed, iclass 7, count 2 2006.173.12:21:55.66#ibcon#about to write, iclass 7, count 2 2006.173.12:21:55.66#ibcon#wrote, iclass 7, count 2 2006.173.12:21:55.66#ibcon#about to read 3, iclass 7, count 2 2006.173.12:21:55.68#ibcon#read 3, iclass 7, count 2 2006.173.12:21:55.68#ibcon#about to read 4, iclass 7, count 2 2006.173.12:21:55.68#ibcon#read 4, iclass 7, count 2 2006.173.12:21:55.68#ibcon#about to read 5, iclass 7, count 2 2006.173.12:21:55.68#ibcon#read 5, iclass 7, count 2 2006.173.12:21:55.68#ibcon#about to read 6, iclass 7, count 2 2006.173.12:21:55.68#ibcon#read 6, iclass 7, count 2 2006.173.12:21:55.68#ibcon#end of sib2, iclass 7, count 2 2006.173.12:21:55.68#ibcon#*mode == 0, iclass 7, count 2 2006.173.12:21:55.68#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.173.12:21:55.68#ibcon#[25=AT08-04\r\n] 2006.173.12:21:55.68#ibcon#*before write, iclass 7, count 2 2006.173.12:21:55.68#ibcon#enter sib2, iclass 7, count 2 2006.173.12:21:55.68#ibcon#flushed, iclass 7, count 2 2006.173.12:21:55.68#ibcon#about to write, iclass 7, count 2 2006.173.12:21:55.68#ibcon#wrote, iclass 7, count 2 2006.173.12:21:55.68#ibcon#about to read 3, iclass 7, count 2 2006.173.12:21:55.71#ibcon#read 3, iclass 7, count 2 2006.173.12:21:55.71#ibcon#about to read 4, iclass 7, count 2 2006.173.12:21:55.71#ibcon#read 4, iclass 7, count 2 2006.173.12:21:55.71#ibcon#about to read 5, iclass 7, count 2 2006.173.12:21:55.71#ibcon#read 5, iclass 7, count 2 2006.173.12:21:55.71#ibcon#about to read 6, iclass 7, count 2 2006.173.12:21:55.71#ibcon#read 6, iclass 7, count 2 2006.173.12:21:55.71#ibcon#end of sib2, iclass 7, count 2 2006.173.12:21:55.71#ibcon#*after write, iclass 7, count 2 2006.173.12:21:55.71#ibcon#*before return 0, iclass 7, count 2 2006.173.12:21:55.71#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.12:21:55.71#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.173.12:21:55.71#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.173.12:21:55.71#ibcon#ireg 7 cls_cnt 0 2006.173.12:21:55.71#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.12:21:55.83#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.12:21:55.83#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.12:21:55.83#ibcon#enter wrdev, iclass 7, count 0 2006.173.12:21:55.83#ibcon#first serial, iclass 7, count 0 2006.173.12:21:55.83#ibcon#enter sib2, iclass 7, count 0 2006.173.12:21:55.83#ibcon#flushed, iclass 7, count 0 2006.173.12:21:55.83#ibcon#about to write, iclass 7, count 0 2006.173.12:21:55.83#ibcon#wrote, iclass 7, count 0 2006.173.12:21:55.83#ibcon#about to read 3, iclass 7, count 0 2006.173.12:21:55.85#ibcon#read 3, iclass 7, count 0 2006.173.12:21:55.85#ibcon#about to read 4, iclass 7, count 0 2006.173.12:21:55.85#ibcon#read 4, iclass 7, count 0 2006.173.12:21:55.85#ibcon#about to read 5, iclass 7, count 0 2006.173.12:21:55.85#ibcon#read 5, iclass 7, count 0 2006.173.12:21:55.85#ibcon#about to read 6, iclass 7, count 0 2006.173.12:21:55.85#ibcon#read 6, iclass 7, count 0 2006.173.12:21:55.85#ibcon#end of sib2, iclass 7, count 0 2006.173.12:21:55.85#ibcon#*mode == 0, iclass 7, count 0 2006.173.12:21:55.85#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.12:21:55.85#ibcon#[25=USB\r\n] 2006.173.12:21:55.85#ibcon#*before write, iclass 7, count 0 2006.173.12:21:55.85#ibcon#enter sib2, iclass 7, count 0 2006.173.12:21:55.85#ibcon#flushed, iclass 7, count 0 2006.173.12:21:55.85#ibcon#about to write, iclass 7, count 0 2006.173.12:21:55.85#ibcon#wrote, iclass 7, count 0 2006.173.12:21:55.85#ibcon#about to read 3, iclass 7, count 0 2006.173.12:21:55.88#ibcon#read 3, iclass 7, count 0 2006.173.12:21:55.88#ibcon#about to read 4, iclass 7, count 0 2006.173.12:21:55.88#ibcon#read 4, iclass 7, count 0 2006.173.12:21:55.88#ibcon#about to read 5, iclass 7, count 0 2006.173.12:21:55.88#ibcon#read 5, iclass 7, count 0 2006.173.12:21:55.88#ibcon#about to read 6, iclass 7, count 0 2006.173.12:21:55.88#ibcon#read 6, iclass 7, count 0 2006.173.12:21:55.88#ibcon#end of sib2, iclass 7, count 0 2006.173.12:21:55.88#ibcon#*after write, iclass 7, count 0 2006.173.12:21:55.88#ibcon#*before return 0, iclass 7, count 0 2006.173.12:21:55.88#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.12:21:55.88#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.173.12:21:55.88#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.12:21:55.88#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.12:21:55.88$vck44/vblo=1,629.99 2006.173.12:21:55.88#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.12:21:55.88#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.12:21:55.88#ibcon#ireg 17 cls_cnt 0 2006.173.12:21:55.88#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.12:21:55.88#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.12:21:55.88#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.12:21:55.88#ibcon#enter wrdev, iclass 11, count 0 2006.173.12:21:55.88#ibcon#first serial, iclass 11, count 0 2006.173.12:21:55.88#ibcon#enter sib2, iclass 11, count 0 2006.173.12:21:55.88#ibcon#flushed, iclass 11, count 0 2006.173.12:21:55.88#ibcon#about to write, iclass 11, count 0 2006.173.12:21:55.88#ibcon#wrote, iclass 11, count 0 2006.173.12:21:55.88#ibcon#about to read 3, iclass 11, count 0 2006.173.12:21:55.90#ibcon#read 3, iclass 11, count 0 2006.173.12:21:55.90#ibcon#about to read 4, iclass 11, count 0 2006.173.12:21:55.90#ibcon#read 4, iclass 11, count 0 2006.173.12:21:55.90#ibcon#about to read 5, iclass 11, count 0 2006.173.12:21:55.90#ibcon#read 5, iclass 11, count 0 2006.173.12:21:55.90#ibcon#about to read 6, iclass 11, count 0 2006.173.12:21:55.90#ibcon#read 6, iclass 11, count 0 2006.173.12:21:55.90#ibcon#end of sib2, iclass 11, count 0 2006.173.12:21:55.90#ibcon#*mode == 0, iclass 11, count 0 2006.173.12:21:55.90#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.12:21:55.90#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.12:21:55.90#ibcon#*before write, iclass 11, count 0 2006.173.12:21:55.90#ibcon#enter sib2, iclass 11, count 0 2006.173.12:21:55.90#ibcon#flushed, iclass 11, count 0 2006.173.12:21:55.90#ibcon#about to write, iclass 11, count 0 2006.173.12:21:55.90#ibcon#wrote, iclass 11, count 0 2006.173.12:21:55.90#ibcon#about to read 3, iclass 11, count 0 2006.173.12:21:55.94#ibcon#read 3, iclass 11, count 0 2006.173.12:21:55.94#ibcon#about to read 4, iclass 11, count 0 2006.173.12:21:55.94#ibcon#read 4, iclass 11, count 0 2006.173.12:21:55.94#ibcon#about to read 5, iclass 11, count 0 2006.173.12:21:55.94#ibcon#read 5, iclass 11, count 0 2006.173.12:21:55.94#ibcon#about to read 6, iclass 11, count 0 2006.173.12:21:55.94#ibcon#read 6, iclass 11, count 0 2006.173.12:21:55.94#ibcon#end of sib2, iclass 11, count 0 2006.173.12:21:55.94#ibcon#*after write, iclass 11, count 0 2006.173.12:21:55.94#ibcon#*before return 0, iclass 11, count 0 2006.173.12:21:55.94#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.12:21:55.94#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.12:21:55.94#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.12:21:55.94#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.12:21:55.94$vck44/vb=1,4 2006.173.12:21:55.94#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.173.12:21:55.94#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.173.12:21:55.94#ibcon#ireg 11 cls_cnt 2 2006.173.12:21:55.94#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.12:21:55.94#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.12:21:55.94#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.12:21:55.94#ibcon#enter wrdev, iclass 13, count 2 2006.173.12:21:55.94#ibcon#first serial, iclass 13, count 2 2006.173.12:21:55.94#ibcon#enter sib2, iclass 13, count 2 2006.173.12:21:55.94#ibcon#flushed, iclass 13, count 2 2006.173.12:21:55.94#ibcon#about to write, iclass 13, count 2 2006.173.12:21:55.94#ibcon#wrote, iclass 13, count 2 2006.173.12:21:55.94#ibcon#about to read 3, iclass 13, count 2 2006.173.12:21:55.96#ibcon#read 3, iclass 13, count 2 2006.173.12:21:55.96#ibcon#about to read 4, iclass 13, count 2 2006.173.12:21:55.96#ibcon#read 4, iclass 13, count 2 2006.173.12:21:55.96#ibcon#about to read 5, iclass 13, count 2 2006.173.12:21:55.96#ibcon#read 5, iclass 13, count 2 2006.173.12:21:55.96#ibcon#about to read 6, iclass 13, count 2 2006.173.12:21:55.96#ibcon#read 6, iclass 13, count 2 2006.173.12:21:55.96#ibcon#end of sib2, iclass 13, count 2 2006.173.12:21:55.96#ibcon#*mode == 0, iclass 13, count 2 2006.173.12:21:55.96#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.173.12:21:55.96#ibcon#[27=AT01-04\r\n] 2006.173.12:21:55.96#ibcon#*before write, iclass 13, count 2 2006.173.12:21:55.96#ibcon#enter sib2, iclass 13, count 2 2006.173.12:21:55.96#ibcon#flushed, iclass 13, count 2 2006.173.12:21:55.96#ibcon#about to write, iclass 13, count 2 2006.173.12:21:55.96#ibcon#wrote, iclass 13, count 2 2006.173.12:21:55.96#ibcon#about to read 3, iclass 13, count 2 2006.173.12:21:55.99#ibcon#read 3, iclass 13, count 2 2006.173.12:21:55.99#ibcon#about to read 4, iclass 13, count 2 2006.173.12:21:55.99#ibcon#read 4, iclass 13, count 2 2006.173.12:21:55.99#ibcon#about to read 5, iclass 13, count 2 2006.173.12:21:55.99#ibcon#read 5, iclass 13, count 2 2006.173.12:21:55.99#ibcon#about to read 6, iclass 13, count 2 2006.173.12:21:55.99#ibcon#read 6, iclass 13, count 2 2006.173.12:21:55.99#ibcon#end of sib2, iclass 13, count 2 2006.173.12:21:55.99#ibcon#*after write, iclass 13, count 2 2006.173.12:21:55.99#ibcon#*before return 0, iclass 13, count 2 2006.173.12:21:55.99#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.12:21:55.99#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.173.12:21:55.99#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.173.12:21:55.99#ibcon#ireg 7 cls_cnt 0 2006.173.12:21:55.99#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.12:21:56.11#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.12:21:56.11#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.12:21:56.11#ibcon#enter wrdev, iclass 13, count 0 2006.173.12:21:56.11#ibcon#first serial, iclass 13, count 0 2006.173.12:21:56.11#ibcon#enter sib2, iclass 13, count 0 2006.173.12:21:56.11#ibcon#flushed, iclass 13, count 0 2006.173.12:21:56.11#ibcon#about to write, iclass 13, count 0 2006.173.12:21:56.11#ibcon#wrote, iclass 13, count 0 2006.173.12:21:56.11#ibcon#about to read 3, iclass 13, count 0 2006.173.12:21:56.13#ibcon#read 3, iclass 13, count 0 2006.173.12:21:56.13#ibcon#about to read 4, iclass 13, count 0 2006.173.12:21:56.13#ibcon#read 4, iclass 13, count 0 2006.173.12:21:56.13#ibcon#about to read 5, iclass 13, count 0 2006.173.12:21:56.13#ibcon#read 5, iclass 13, count 0 2006.173.12:21:56.13#ibcon#about to read 6, iclass 13, count 0 2006.173.12:21:56.13#ibcon#read 6, iclass 13, count 0 2006.173.12:21:56.13#ibcon#end of sib2, iclass 13, count 0 2006.173.12:21:56.13#ibcon#*mode == 0, iclass 13, count 0 2006.173.12:21:56.13#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.12:21:56.13#ibcon#[27=USB\r\n] 2006.173.12:21:56.13#ibcon#*before write, iclass 13, count 0 2006.173.12:21:56.13#ibcon#enter sib2, iclass 13, count 0 2006.173.12:21:56.13#ibcon#flushed, iclass 13, count 0 2006.173.12:21:56.13#ibcon#about to write, iclass 13, count 0 2006.173.12:21:56.13#ibcon#wrote, iclass 13, count 0 2006.173.12:21:56.13#ibcon#about to read 3, iclass 13, count 0 2006.173.12:21:56.16#ibcon#read 3, iclass 13, count 0 2006.173.12:21:56.16#ibcon#about to read 4, iclass 13, count 0 2006.173.12:21:56.16#ibcon#read 4, iclass 13, count 0 2006.173.12:21:56.16#ibcon#about to read 5, iclass 13, count 0 2006.173.12:21:56.16#ibcon#read 5, iclass 13, count 0 2006.173.12:21:56.16#ibcon#about to read 6, iclass 13, count 0 2006.173.12:21:56.16#ibcon#read 6, iclass 13, count 0 2006.173.12:21:56.16#ibcon#end of sib2, iclass 13, count 0 2006.173.12:21:56.16#ibcon#*after write, iclass 13, count 0 2006.173.12:21:56.16#ibcon#*before return 0, iclass 13, count 0 2006.173.12:21:56.16#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.12:21:56.16#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.173.12:21:56.16#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.12:21:56.16#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.12:21:56.16$vck44/vblo=2,634.99 2006.173.12:21:56.16#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.12:21:56.16#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.12:21:56.16#ibcon#ireg 17 cls_cnt 0 2006.173.12:21:56.16#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.12:21:56.16#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.12:21:56.16#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.12:21:56.16#ibcon#enter wrdev, iclass 15, count 0 2006.173.12:21:56.16#ibcon#first serial, iclass 15, count 0 2006.173.12:21:56.16#ibcon#enter sib2, iclass 15, count 0 2006.173.12:21:56.16#ibcon#flushed, iclass 15, count 0 2006.173.12:21:56.16#ibcon#about to write, iclass 15, count 0 2006.173.12:21:56.16#ibcon#wrote, iclass 15, count 0 2006.173.12:21:56.16#ibcon#about to read 3, iclass 15, count 0 2006.173.12:21:56.18#ibcon#read 3, iclass 15, count 0 2006.173.12:21:56.18#ibcon#about to read 4, iclass 15, count 0 2006.173.12:21:56.18#ibcon#read 4, iclass 15, count 0 2006.173.12:21:56.18#ibcon#about to read 5, iclass 15, count 0 2006.173.12:21:56.18#ibcon#read 5, iclass 15, count 0 2006.173.12:21:56.18#ibcon#about to read 6, iclass 15, count 0 2006.173.12:21:56.18#ibcon#read 6, iclass 15, count 0 2006.173.12:21:56.18#ibcon#end of sib2, iclass 15, count 0 2006.173.12:21:56.18#ibcon#*mode == 0, iclass 15, count 0 2006.173.12:21:56.18#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.12:21:56.18#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.12:21:56.18#ibcon#*before write, iclass 15, count 0 2006.173.12:21:56.18#ibcon#enter sib2, iclass 15, count 0 2006.173.12:21:56.18#ibcon#flushed, iclass 15, count 0 2006.173.12:21:56.18#ibcon#about to write, iclass 15, count 0 2006.173.12:21:56.18#ibcon#wrote, iclass 15, count 0 2006.173.12:21:56.18#ibcon#about to read 3, iclass 15, count 0 2006.173.12:21:56.22#ibcon#read 3, iclass 15, count 0 2006.173.12:21:56.22#ibcon#about to read 4, iclass 15, count 0 2006.173.12:21:56.22#ibcon#read 4, iclass 15, count 0 2006.173.12:21:56.22#ibcon#about to read 5, iclass 15, count 0 2006.173.12:21:56.22#ibcon#read 5, iclass 15, count 0 2006.173.12:21:56.22#ibcon#about to read 6, iclass 15, count 0 2006.173.12:21:56.22#ibcon#read 6, iclass 15, count 0 2006.173.12:21:56.22#ibcon#end of sib2, iclass 15, count 0 2006.173.12:21:56.22#ibcon#*after write, iclass 15, count 0 2006.173.12:21:56.22#ibcon#*before return 0, iclass 15, count 0 2006.173.12:21:56.22#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.12:21:56.22#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.12:21:56.22#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.12:21:56.22#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.12:21:56.22$vck44/vb=2,4 2006.173.12:21:56.22#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.12:21:56.22#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.12:21:56.22#ibcon#ireg 11 cls_cnt 2 2006.173.12:21:56.22#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.12:21:56.28#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.12:21:56.28#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.12:21:56.28#ibcon#enter wrdev, iclass 17, count 2 2006.173.12:21:56.28#ibcon#first serial, iclass 17, count 2 2006.173.12:21:56.28#ibcon#enter sib2, iclass 17, count 2 2006.173.12:21:56.28#ibcon#flushed, iclass 17, count 2 2006.173.12:21:56.28#ibcon#about to write, iclass 17, count 2 2006.173.12:21:56.28#ibcon#wrote, iclass 17, count 2 2006.173.12:21:56.28#ibcon#about to read 3, iclass 17, count 2 2006.173.12:21:56.30#ibcon#read 3, iclass 17, count 2 2006.173.12:21:56.30#ibcon#about to read 4, iclass 17, count 2 2006.173.12:21:56.30#ibcon#read 4, iclass 17, count 2 2006.173.12:21:56.30#ibcon#about to read 5, iclass 17, count 2 2006.173.12:21:56.30#ibcon#read 5, iclass 17, count 2 2006.173.12:21:56.30#ibcon#about to read 6, iclass 17, count 2 2006.173.12:21:56.30#ibcon#read 6, iclass 17, count 2 2006.173.12:21:56.30#ibcon#end of sib2, iclass 17, count 2 2006.173.12:21:56.30#ibcon#*mode == 0, iclass 17, count 2 2006.173.12:21:56.30#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.12:21:56.30#ibcon#[27=AT02-04\r\n] 2006.173.12:21:56.30#ibcon#*before write, iclass 17, count 2 2006.173.12:21:56.30#ibcon#enter sib2, iclass 17, count 2 2006.173.12:21:56.30#ibcon#flushed, iclass 17, count 2 2006.173.12:21:56.30#ibcon#about to write, iclass 17, count 2 2006.173.12:21:56.30#ibcon#wrote, iclass 17, count 2 2006.173.12:21:56.30#ibcon#about to read 3, iclass 17, count 2 2006.173.12:21:56.33#ibcon#read 3, iclass 17, count 2 2006.173.12:21:56.33#ibcon#about to read 4, iclass 17, count 2 2006.173.12:21:56.33#ibcon#read 4, iclass 17, count 2 2006.173.12:21:56.33#ibcon#about to read 5, iclass 17, count 2 2006.173.12:21:56.33#ibcon#read 5, iclass 17, count 2 2006.173.12:21:56.33#ibcon#about to read 6, iclass 17, count 2 2006.173.12:21:56.33#ibcon#read 6, iclass 17, count 2 2006.173.12:21:56.33#ibcon#end of sib2, iclass 17, count 2 2006.173.12:21:56.33#ibcon#*after write, iclass 17, count 2 2006.173.12:21:56.33#ibcon#*before return 0, iclass 17, count 2 2006.173.12:21:56.33#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.12:21:56.33#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.12:21:56.33#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.12:21:56.33#ibcon#ireg 7 cls_cnt 0 2006.173.12:21:56.33#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.12:21:56.45#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.12:21:56.45#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.12:21:56.45#ibcon#enter wrdev, iclass 17, count 0 2006.173.12:21:56.45#ibcon#first serial, iclass 17, count 0 2006.173.12:21:56.45#ibcon#enter sib2, iclass 17, count 0 2006.173.12:21:56.45#ibcon#flushed, iclass 17, count 0 2006.173.12:21:56.45#ibcon#about to write, iclass 17, count 0 2006.173.12:21:56.45#ibcon#wrote, iclass 17, count 0 2006.173.12:21:56.45#ibcon#about to read 3, iclass 17, count 0 2006.173.12:21:56.47#ibcon#read 3, iclass 17, count 0 2006.173.12:21:56.47#ibcon#about to read 4, iclass 17, count 0 2006.173.12:21:56.47#ibcon#read 4, iclass 17, count 0 2006.173.12:21:56.47#ibcon#about to read 5, iclass 17, count 0 2006.173.12:21:56.47#ibcon#read 5, iclass 17, count 0 2006.173.12:21:56.47#ibcon#about to read 6, iclass 17, count 0 2006.173.12:21:56.47#ibcon#read 6, iclass 17, count 0 2006.173.12:21:56.47#ibcon#end of sib2, iclass 17, count 0 2006.173.12:21:56.47#ibcon#*mode == 0, iclass 17, count 0 2006.173.12:21:56.47#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.12:21:56.47#ibcon#[27=USB\r\n] 2006.173.12:21:56.47#ibcon#*before write, iclass 17, count 0 2006.173.12:21:56.47#ibcon#enter sib2, iclass 17, count 0 2006.173.12:21:56.47#ibcon#flushed, iclass 17, count 0 2006.173.12:21:56.47#ibcon#about to write, iclass 17, count 0 2006.173.12:21:56.47#ibcon#wrote, iclass 17, count 0 2006.173.12:21:56.47#ibcon#about to read 3, iclass 17, count 0 2006.173.12:21:56.50#ibcon#read 3, iclass 17, count 0 2006.173.12:21:56.50#ibcon#about to read 4, iclass 17, count 0 2006.173.12:21:56.50#ibcon#read 4, iclass 17, count 0 2006.173.12:21:56.50#ibcon#about to read 5, iclass 17, count 0 2006.173.12:21:56.50#ibcon#read 5, iclass 17, count 0 2006.173.12:21:56.50#ibcon#about to read 6, iclass 17, count 0 2006.173.12:21:56.50#ibcon#read 6, iclass 17, count 0 2006.173.12:21:56.50#ibcon#end of sib2, iclass 17, count 0 2006.173.12:21:56.50#ibcon#*after write, iclass 17, count 0 2006.173.12:21:56.50#ibcon#*before return 0, iclass 17, count 0 2006.173.12:21:56.50#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.12:21:56.50#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.12:21:56.50#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.12:21:56.50#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.12:21:56.50$vck44/vblo=3,649.99 2006.173.12:21:56.50#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.12:21:56.50#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.12:21:56.50#ibcon#ireg 17 cls_cnt 0 2006.173.12:21:56.50#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.12:21:56.50#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.12:21:56.50#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.12:21:56.50#ibcon#enter wrdev, iclass 19, count 0 2006.173.12:21:56.50#ibcon#first serial, iclass 19, count 0 2006.173.12:21:56.50#ibcon#enter sib2, iclass 19, count 0 2006.173.12:21:56.50#ibcon#flushed, iclass 19, count 0 2006.173.12:21:56.50#ibcon#about to write, iclass 19, count 0 2006.173.12:21:56.50#ibcon#wrote, iclass 19, count 0 2006.173.12:21:56.50#ibcon#about to read 3, iclass 19, count 0 2006.173.12:21:56.52#ibcon#read 3, iclass 19, count 0 2006.173.12:21:56.52#ibcon#about to read 4, iclass 19, count 0 2006.173.12:21:56.52#ibcon#read 4, iclass 19, count 0 2006.173.12:21:56.52#ibcon#about to read 5, iclass 19, count 0 2006.173.12:21:56.52#ibcon#read 5, iclass 19, count 0 2006.173.12:21:56.52#ibcon#about to read 6, iclass 19, count 0 2006.173.12:21:56.52#ibcon#read 6, iclass 19, count 0 2006.173.12:21:56.52#ibcon#end of sib2, iclass 19, count 0 2006.173.12:21:56.52#ibcon#*mode == 0, iclass 19, count 0 2006.173.12:21:56.52#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.12:21:56.52#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.12:21:56.52#ibcon#*before write, iclass 19, count 0 2006.173.12:21:56.52#ibcon#enter sib2, iclass 19, count 0 2006.173.12:21:56.52#ibcon#flushed, iclass 19, count 0 2006.173.12:21:56.52#ibcon#about to write, iclass 19, count 0 2006.173.12:21:56.52#ibcon#wrote, iclass 19, count 0 2006.173.12:21:56.52#ibcon#about to read 3, iclass 19, count 0 2006.173.12:21:56.56#ibcon#read 3, iclass 19, count 0 2006.173.12:21:56.56#ibcon#about to read 4, iclass 19, count 0 2006.173.12:21:56.56#ibcon#read 4, iclass 19, count 0 2006.173.12:21:56.56#ibcon#about to read 5, iclass 19, count 0 2006.173.12:21:56.56#ibcon#read 5, iclass 19, count 0 2006.173.12:21:56.56#ibcon#about to read 6, iclass 19, count 0 2006.173.12:21:56.56#ibcon#read 6, iclass 19, count 0 2006.173.12:21:56.56#ibcon#end of sib2, iclass 19, count 0 2006.173.12:21:56.56#ibcon#*after write, iclass 19, count 0 2006.173.12:21:56.56#ibcon#*before return 0, iclass 19, count 0 2006.173.12:21:56.56#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.12:21:56.56#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.12:21:56.56#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.12:21:56.56#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.12:21:56.56$vck44/vb=3,4 2006.173.12:21:56.56#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.12:21:56.56#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.12:21:56.56#ibcon#ireg 11 cls_cnt 2 2006.173.12:21:56.56#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.12:21:56.62#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.12:21:56.62#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.12:21:56.62#ibcon#enter wrdev, iclass 21, count 2 2006.173.12:21:56.62#ibcon#first serial, iclass 21, count 2 2006.173.12:21:56.62#ibcon#enter sib2, iclass 21, count 2 2006.173.12:21:56.62#ibcon#flushed, iclass 21, count 2 2006.173.12:21:56.62#ibcon#about to write, iclass 21, count 2 2006.173.12:21:56.62#ibcon#wrote, iclass 21, count 2 2006.173.12:21:56.62#ibcon#about to read 3, iclass 21, count 2 2006.173.12:21:56.64#ibcon#read 3, iclass 21, count 2 2006.173.12:21:56.64#ibcon#about to read 4, iclass 21, count 2 2006.173.12:21:56.64#ibcon#read 4, iclass 21, count 2 2006.173.12:21:56.64#ibcon#about to read 5, iclass 21, count 2 2006.173.12:21:56.64#ibcon#read 5, iclass 21, count 2 2006.173.12:21:56.64#ibcon#about to read 6, iclass 21, count 2 2006.173.12:21:56.64#ibcon#read 6, iclass 21, count 2 2006.173.12:21:56.64#ibcon#end of sib2, iclass 21, count 2 2006.173.12:21:56.64#ibcon#*mode == 0, iclass 21, count 2 2006.173.12:21:56.64#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.12:21:56.64#ibcon#[27=AT03-04\r\n] 2006.173.12:21:56.64#ibcon#*before write, iclass 21, count 2 2006.173.12:21:56.64#ibcon#enter sib2, iclass 21, count 2 2006.173.12:21:56.64#ibcon#flushed, iclass 21, count 2 2006.173.12:21:56.64#ibcon#about to write, iclass 21, count 2 2006.173.12:21:56.64#ibcon#wrote, iclass 21, count 2 2006.173.12:21:56.64#ibcon#about to read 3, iclass 21, count 2 2006.173.12:21:56.67#ibcon#read 3, iclass 21, count 2 2006.173.12:21:56.67#ibcon#about to read 4, iclass 21, count 2 2006.173.12:21:56.67#ibcon#read 4, iclass 21, count 2 2006.173.12:21:56.67#ibcon#about to read 5, iclass 21, count 2 2006.173.12:21:56.67#ibcon#read 5, iclass 21, count 2 2006.173.12:21:56.67#ibcon#about to read 6, iclass 21, count 2 2006.173.12:21:56.67#ibcon#read 6, iclass 21, count 2 2006.173.12:21:56.67#ibcon#end of sib2, iclass 21, count 2 2006.173.12:21:56.67#ibcon#*after write, iclass 21, count 2 2006.173.12:21:56.67#ibcon#*before return 0, iclass 21, count 2 2006.173.12:21:56.67#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.12:21:56.67#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.12:21:56.67#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.12:21:56.67#ibcon#ireg 7 cls_cnt 0 2006.173.12:21:56.67#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.12:21:56.79#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.12:21:56.79#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.12:21:56.79#ibcon#enter wrdev, iclass 21, count 0 2006.173.12:21:56.79#ibcon#first serial, iclass 21, count 0 2006.173.12:21:56.79#ibcon#enter sib2, iclass 21, count 0 2006.173.12:21:56.79#ibcon#flushed, iclass 21, count 0 2006.173.12:21:56.79#ibcon#about to write, iclass 21, count 0 2006.173.12:21:56.79#ibcon#wrote, iclass 21, count 0 2006.173.12:21:56.79#ibcon#about to read 3, iclass 21, count 0 2006.173.12:21:56.81#ibcon#read 3, iclass 21, count 0 2006.173.12:21:56.81#ibcon#about to read 4, iclass 21, count 0 2006.173.12:21:56.81#ibcon#read 4, iclass 21, count 0 2006.173.12:21:56.81#ibcon#about to read 5, iclass 21, count 0 2006.173.12:21:56.81#ibcon#read 5, iclass 21, count 0 2006.173.12:21:56.81#ibcon#about to read 6, iclass 21, count 0 2006.173.12:21:56.81#ibcon#read 6, iclass 21, count 0 2006.173.12:21:56.81#ibcon#end of sib2, iclass 21, count 0 2006.173.12:21:56.81#ibcon#*mode == 0, iclass 21, count 0 2006.173.12:21:56.81#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.12:21:56.81#ibcon#[27=USB\r\n] 2006.173.12:21:56.81#ibcon#*before write, iclass 21, count 0 2006.173.12:21:56.81#ibcon#enter sib2, iclass 21, count 0 2006.173.12:21:56.81#ibcon#flushed, iclass 21, count 0 2006.173.12:21:56.81#ibcon#about to write, iclass 21, count 0 2006.173.12:21:56.81#ibcon#wrote, iclass 21, count 0 2006.173.12:21:56.81#ibcon#about to read 3, iclass 21, count 0 2006.173.12:21:56.84#ibcon#read 3, iclass 21, count 0 2006.173.12:21:56.84#ibcon#about to read 4, iclass 21, count 0 2006.173.12:21:56.84#ibcon#read 4, iclass 21, count 0 2006.173.12:21:56.84#ibcon#about to read 5, iclass 21, count 0 2006.173.12:21:56.84#ibcon#read 5, iclass 21, count 0 2006.173.12:21:56.84#ibcon#about to read 6, iclass 21, count 0 2006.173.12:21:56.84#ibcon#read 6, iclass 21, count 0 2006.173.12:21:56.84#ibcon#end of sib2, iclass 21, count 0 2006.173.12:21:56.84#ibcon#*after write, iclass 21, count 0 2006.173.12:21:56.84#ibcon#*before return 0, iclass 21, count 0 2006.173.12:21:56.84#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.12:21:56.84#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.12:21:56.84#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.12:21:56.84#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.12:21:56.84$vck44/vblo=4,679.99 2006.173.12:21:56.84#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.12:21:56.84#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.12:21:56.84#ibcon#ireg 17 cls_cnt 0 2006.173.12:21:56.84#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.12:21:56.84#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.12:21:56.84#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.12:21:56.84#ibcon#enter wrdev, iclass 23, count 0 2006.173.12:21:56.84#ibcon#first serial, iclass 23, count 0 2006.173.12:21:56.84#ibcon#enter sib2, iclass 23, count 0 2006.173.12:21:56.84#ibcon#flushed, iclass 23, count 0 2006.173.12:21:56.84#ibcon#about to write, iclass 23, count 0 2006.173.12:21:56.84#ibcon#wrote, iclass 23, count 0 2006.173.12:21:56.84#ibcon#about to read 3, iclass 23, count 0 2006.173.12:21:56.86#ibcon#read 3, iclass 23, count 0 2006.173.12:21:56.86#ibcon#about to read 4, iclass 23, count 0 2006.173.12:21:56.86#ibcon#read 4, iclass 23, count 0 2006.173.12:21:56.86#ibcon#about to read 5, iclass 23, count 0 2006.173.12:21:56.86#ibcon#read 5, iclass 23, count 0 2006.173.12:21:56.86#ibcon#about to read 6, iclass 23, count 0 2006.173.12:21:56.86#ibcon#read 6, iclass 23, count 0 2006.173.12:21:56.86#ibcon#end of sib2, iclass 23, count 0 2006.173.12:21:56.86#ibcon#*mode == 0, iclass 23, count 0 2006.173.12:21:56.86#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.12:21:56.86#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.12:21:56.86#ibcon#*before write, iclass 23, count 0 2006.173.12:21:56.86#ibcon#enter sib2, iclass 23, count 0 2006.173.12:21:56.86#ibcon#flushed, iclass 23, count 0 2006.173.12:21:56.86#ibcon#about to write, iclass 23, count 0 2006.173.12:21:56.86#ibcon#wrote, iclass 23, count 0 2006.173.12:21:56.86#ibcon#about to read 3, iclass 23, count 0 2006.173.12:21:56.90#ibcon#read 3, iclass 23, count 0 2006.173.12:21:56.90#ibcon#about to read 4, iclass 23, count 0 2006.173.12:21:56.90#ibcon#read 4, iclass 23, count 0 2006.173.12:21:56.90#ibcon#about to read 5, iclass 23, count 0 2006.173.12:21:56.90#ibcon#read 5, iclass 23, count 0 2006.173.12:21:56.90#ibcon#about to read 6, iclass 23, count 0 2006.173.12:21:56.90#ibcon#read 6, iclass 23, count 0 2006.173.12:21:56.90#ibcon#end of sib2, iclass 23, count 0 2006.173.12:21:56.90#ibcon#*after write, iclass 23, count 0 2006.173.12:21:56.90#ibcon#*before return 0, iclass 23, count 0 2006.173.12:21:56.90#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.12:21:56.90#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.12:21:56.90#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.12:21:56.90#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.12:21:56.90$vck44/vb=4,4 2006.173.12:21:56.90#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.12:21:56.90#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.12:21:56.90#ibcon#ireg 11 cls_cnt 2 2006.173.12:21:56.90#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.12:21:56.96#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.12:21:56.96#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.12:21:56.96#ibcon#enter wrdev, iclass 25, count 2 2006.173.12:21:56.96#ibcon#first serial, iclass 25, count 2 2006.173.12:21:56.96#ibcon#enter sib2, iclass 25, count 2 2006.173.12:21:56.96#ibcon#flushed, iclass 25, count 2 2006.173.12:21:56.96#ibcon#about to write, iclass 25, count 2 2006.173.12:21:56.96#ibcon#wrote, iclass 25, count 2 2006.173.12:21:56.96#ibcon#about to read 3, iclass 25, count 2 2006.173.12:21:56.98#ibcon#read 3, iclass 25, count 2 2006.173.12:21:56.98#ibcon#about to read 4, iclass 25, count 2 2006.173.12:21:56.98#ibcon#read 4, iclass 25, count 2 2006.173.12:21:56.98#ibcon#about to read 5, iclass 25, count 2 2006.173.12:21:56.98#ibcon#read 5, iclass 25, count 2 2006.173.12:21:56.98#ibcon#about to read 6, iclass 25, count 2 2006.173.12:21:56.98#ibcon#read 6, iclass 25, count 2 2006.173.12:21:56.98#ibcon#end of sib2, iclass 25, count 2 2006.173.12:21:56.98#ibcon#*mode == 0, iclass 25, count 2 2006.173.12:21:56.98#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.12:21:56.98#ibcon#[27=AT04-04\r\n] 2006.173.12:21:56.98#ibcon#*before write, iclass 25, count 2 2006.173.12:21:56.98#ibcon#enter sib2, iclass 25, count 2 2006.173.12:21:56.98#ibcon#flushed, iclass 25, count 2 2006.173.12:21:56.98#ibcon#about to write, iclass 25, count 2 2006.173.12:21:56.98#ibcon#wrote, iclass 25, count 2 2006.173.12:21:56.98#ibcon#about to read 3, iclass 25, count 2 2006.173.12:21:57.01#ibcon#read 3, iclass 25, count 2 2006.173.12:21:57.01#ibcon#about to read 4, iclass 25, count 2 2006.173.12:21:57.01#ibcon#read 4, iclass 25, count 2 2006.173.12:21:57.01#ibcon#about to read 5, iclass 25, count 2 2006.173.12:21:57.01#ibcon#read 5, iclass 25, count 2 2006.173.12:21:57.01#ibcon#about to read 6, iclass 25, count 2 2006.173.12:21:57.01#ibcon#read 6, iclass 25, count 2 2006.173.12:21:57.01#ibcon#end of sib2, iclass 25, count 2 2006.173.12:21:57.01#ibcon#*after write, iclass 25, count 2 2006.173.12:21:57.01#ibcon#*before return 0, iclass 25, count 2 2006.173.12:21:57.01#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.12:21:57.01#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.12:21:57.01#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.12:21:57.01#ibcon#ireg 7 cls_cnt 0 2006.173.12:21:57.01#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.12:21:57.13#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.12:21:57.13#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.12:21:57.13#ibcon#enter wrdev, iclass 25, count 0 2006.173.12:21:57.13#ibcon#first serial, iclass 25, count 0 2006.173.12:21:57.13#ibcon#enter sib2, iclass 25, count 0 2006.173.12:21:57.13#ibcon#flushed, iclass 25, count 0 2006.173.12:21:57.13#ibcon#about to write, iclass 25, count 0 2006.173.12:21:57.13#ibcon#wrote, iclass 25, count 0 2006.173.12:21:57.13#ibcon#about to read 3, iclass 25, count 0 2006.173.12:21:57.15#ibcon#read 3, iclass 25, count 0 2006.173.12:21:57.15#ibcon#about to read 4, iclass 25, count 0 2006.173.12:21:57.15#ibcon#read 4, iclass 25, count 0 2006.173.12:21:57.15#ibcon#about to read 5, iclass 25, count 0 2006.173.12:21:57.15#ibcon#read 5, iclass 25, count 0 2006.173.12:21:57.15#ibcon#about to read 6, iclass 25, count 0 2006.173.12:21:57.15#ibcon#read 6, iclass 25, count 0 2006.173.12:21:57.15#ibcon#end of sib2, iclass 25, count 0 2006.173.12:21:57.15#ibcon#*mode == 0, iclass 25, count 0 2006.173.12:21:57.15#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.12:21:57.15#ibcon#[27=USB\r\n] 2006.173.12:21:57.15#ibcon#*before write, iclass 25, count 0 2006.173.12:21:57.15#ibcon#enter sib2, iclass 25, count 0 2006.173.12:21:57.15#ibcon#flushed, iclass 25, count 0 2006.173.12:21:57.15#ibcon#about to write, iclass 25, count 0 2006.173.12:21:57.15#ibcon#wrote, iclass 25, count 0 2006.173.12:21:57.15#ibcon#about to read 3, iclass 25, count 0 2006.173.12:21:57.18#ibcon#read 3, iclass 25, count 0 2006.173.12:21:57.18#ibcon#about to read 4, iclass 25, count 0 2006.173.12:21:57.18#ibcon#read 4, iclass 25, count 0 2006.173.12:21:57.18#ibcon#about to read 5, iclass 25, count 0 2006.173.12:21:57.18#ibcon#read 5, iclass 25, count 0 2006.173.12:21:57.18#ibcon#about to read 6, iclass 25, count 0 2006.173.12:21:57.18#ibcon#read 6, iclass 25, count 0 2006.173.12:21:57.18#ibcon#end of sib2, iclass 25, count 0 2006.173.12:21:57.18#ibcon#*after write, iclass 25, count 0 2006.173.12:21:57.18#ibcon#*before return 0, iclass 25, count 0 2006.173.12:21:57.18#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.12:21:57.18#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.12:21:57.18#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.12:21:57.18#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.12:21:57.18$vck44/vblo=5,709.99 2006.173.12:21:57.18#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.12:21:57.18#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.12:21:57.18#ibcon#ireg 17 cls_cnt 0 2006.173.12:21:57.18#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.12:21:57.18#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.12:21:57.18#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.12:21:57.18#ibcon#enter wrdev, iclass 27, count 0 2006.173.12:21:57.18#ibcon#first serial, iclass 27, count 0 2006.173.12:21:57.18#ibcon#enter sib2, iclass 27, count 0 2006.173.12:21:57.18#ibcon#flushed, iclass 27, count 0 2006.173.12:21:57.18#ibcon#about to write, iclass 27, count 0 2006.173.12:21:57.18#ibcon#wrote, iclass 27, count 0 2006.173.12:21:57.18#ibcon#about to read 3, iclass 27, count 0 2006.173.12:21:57.20#ibcon#read 3, iclass 27, count 0 2006.173.12:21:57.20#ibcon#about to read 4, iclass 27, count 0 2006.173.12:21:57.20#ibcon#read 4, iclass 27, count 0 2006.173.12:21:57.20#ibcon#about to read 5, iclass 27, count 0 2006.173.12:21:57.20#ibcon#read 5, iclass 27, count 0 2006.173.12:21:57.20#ibcon#about to read 6, iclass 27, count 0 2006.173.12:21:57.20#ibcon#read 6, iclass 27, count 0 2006.173.12:21:57.20#ibcon#end of sib2, iclass 27, count 0 2006.173.12:21:57.20#ibcon#*mode == 0, iclass 27, count 0 2006.173.12:21:57.20#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.12:21:57.20#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.12:21:57.20#ibcon#*before write, iclass 27, count 0 2006.173.12:21:57.20#ibcon#enter sib2, iclass 27, count 0 2006.173.12:21:57.20#ibcon#flushed, iclass 27, count 0 2006.173.12:21:57.20#ibcon#about to write, iclass 27, count 0 2006.173.12:21:57.20#ibcon#wrote, iclass 27, count 0 2006.173.12:21:57.20#ibcon#about to read 3, iclass 27, count 0 2006.173.12:21:57.24#ibcon#read 3, iclass 27, count 0 2006.173.12:21:57.24#ibcon#about to read 4, iclass 27, count 0 2006.173.12:21:57.24#ibcon#read 4, iclass 27, count 0 2006.173.12:21:57.24#ibcon#about to read 5, iclass 27, count 0 2006.173.12:21:57.24#ibcon#read 5, iclass 27, count 0 2006.173.12:21:57.24#ibcon#about to read 6, iclass 27, count 0 2006.173.12:21:57.24#ibcon#read 6, iclass 27, count 0 2006.173.12:21:57.24#ibcon#end of sib2, iclass 27, count 0 2006.173.12:21:57.24#ibcon#*after write, iclass 27, count 0 2006.173.12:21:57.24#ibcon#*before return 0, iclass 27, count 0 2006.173.12:21:57.24#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.12:21:57.24#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.12:21:57.24#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.12:21:57.24#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.12:21:57.24$vck44/vb=5,4 2006.173.12:21:57.24#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.12:21:57.24#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.12:21:57.24#ibcon#ireg 11 cls_cnt 2 2006.173.12:21:57.24#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.12:21:57.30#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.12:21:57.30#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.12:21:57.30#ibcon#enter wrdev, iclass 29, count 2 2006.173.12:21:57.30#ibcon#first serial, iclass 29, count 2 2006.173.12:21:57.30#ibcon#enter sib2, iclass 29, count 2 2006.173.12:21:57.30#ibcon#flushed, iclass 29, count 2 2006.173.12:21:57.30#ibcon#about to write, iclass 29, count 2 2006.173.12:21:57.30#ibcon#wrote, iclass 29, count 2 2006.173.12:21:57.30#ibcon#about to read 3, iclass 29, count 2 2006.173.12:21:57.32#ibcon#read 3, iclass 29, count 2 2006.173.12:21:57.32#ibcon#about to read 4, iclass 29, count 2 2006.173.12:21:57.32#ibcon#read 4, iclass 29, count 2 2006.173.12:21:57.32#ibcon#about to read 5, iclass 29, count 2 2006.173.12:21:57.32#ibcon#read 5, iclass 29, count 2 2006.173.12:21:57.32#ibcon#about to read 6, iclass 29, count 2 2006.173.12:21:57.32#ibcon#read 6, iclass 29, count 2 2006.173.12:21:57.32#ibcon#end of sib2, iclass 29, count 2 2006.173.12:21:57.32#ibcon#*mode == 0, iclass 29, count 2 2006.173.12:21:57.32#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.12:21:57.32#ibcon#[27=AT05-04\r\n] 2006.173.12:21:57.32#ibcon#*before write, iclass 29, count 2 2006.173.12:21:57.32#ibcon#enter sib2, iclass 29, count 2 2006.173.12:21:57.32#ibcon#flushed, iclass 29, count 2 2006.173.12:21:57.32#ibcon#about to write, iclass 29, count 2 2006.173.12:21:57.32#ibcon#wrote, iclass 29, count 2 2006.173.12:21:57.32#ibcon#about to read 3, iclass 29, count 2 2006.173.12:21:57.35#ibcon#read 3, iclass 29, count 2 2006.173.12:21:57.35#ibcon#about to read 4, iclass 29, count 2 2006.173.12:21:57.35#ibcon#read 4, iclass 29, count 2 2006.173.12:21:57.35#ibcon#about to read 5, iclass 29, count 2 2006.173.12:21:57.35#ibcon#read 5, iclass 29, count 2 2006.173.12:21:57.35#ibcon#about to read 6, iclass 29, count 2 2006.173.12:21:57.35#ibcon#read 6, iclass 29, count 2 2006.173.12:21:57.35#ibcon#end of sib2, iclass 29, count 2 2006.173.12:21:57.35#ibcon#*after write, iclass 29, count 2 2006.173.12:21:57.35#ibcon#*before return 0, iclass 29, count 2 2006.173.12:21:57.35#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.12:21:57.35#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.12:21:57.35#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.12:21:57.35#ibcon#ireg 7 cls_cnt 0 2006.173.12:21:57.35#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.12:21:57.47#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.12:21:57.47#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.12:21:57.47#ibcon#enter wrdev, iclass 29, count 0 2006.173.12:21:57.47#ibcon#first serial, iclass 29, count 0 2006.173.12:21:57.47#ibcon#enter sib2, iclass 29, count 0 2006.173.12:21:57.47#ibcon#flushed, iclass 29, count 0 2006.173.12:21:57.47#ibcon#about to write, iclass 29, count 0 2006.173.12:21:57.47#ibcon#wrote, iclass 29, count 0 2006.173.12:21:57.47#ibcon#about to read 3, iclass 29, count 0 2006.173.12:21:57.49#ibcon#read 3, iclass 29, count 0 2006.173.12:21:57.49#ibcon#about to read 4, iclass 29, count 0 2006.173.12:21:57.49#ibcon#read 4, iclass 29, count 0 2006.173.12:21:57.49#ibcon#about to read 5, iclass 29, count 0 2006.173.12:21:57.49#ibcon#read 5, iclass 29, count 0 2006.173.12:21:57.49#ibcon#about to read 6, iclass 29, count 0 2006.173.12:21:57.49#ibcon#read 6, iclass 29, count 0 2006.173.12:21:57.49#ibcon#end of sib2, iclass 29, count 0 2006.173.12:21:57.49#ibcon#*mode == 0, iclass 29, count 0 2006.173.12:21:57.49#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.12:21:57.49#ibcon#[27=USB\r\n] 2006.173.12:21:57.49#ibcon#*before write, iclass 29, count 0 2006.173.12:21:57.49#ibcon#enter sib2, iclass 29, count 0 2006.173.12:21:57.49#ibcon#flushed, iclass 29, count 0 2006.173.12:21:57.49#ibcon#about to write, iclass 29, count 0 2006.173.12:21:57.49#ibcon#wrote, iclass 29, count 0 2006.173.12:21:57.49#ibcon#about to read 3, iclass 29, count 0 2006.173.12:21:57.52#ibcon#read 3, iclass 29, count 0 2006.173.12:21:57.52#ibcon#about to read 4, iclass 29, count 0 2006.173.12:21:57.52#ibcon#read 4, iclass 29, count 0 2006.173.12:21:57.52#ibcon#about to read 5, iclass 29, count 0 2006.173.12:21:57.52#ibcon#read 5, iclass 29, count 0 2006.173.12:21:57.52#ibcon#about to read 6, iclass 29, count 0 2006.173.12:21:57.52#ibcon#read 6, iclass 29, count 0 2006.173.12:21:57.52#ibcon#end of sib2, iclass 29, count 0 2006.173.12:21:57.52#ibcon#*after write, iclass 29, count 0 2006.173.12:21:57.52#ibcon#*before return 0, iclass 29, count 0 2006.173.12:21:57.52#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.12:21:57.52#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.12:21:57.52#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.12:21:57.52#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.12:21:57.52$vck44/vblo=6,719.99 2006.173.12:21:57.52#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.12:21:57.52#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.12:21:57.52#ibcon#ireg 17 cls_cnt 0 2006.173.12:21:57.52#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.12:21:57.52#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.12:21:57.52#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.12:21:57.52#ibcon#enter wrdev, iclass 31, count 0 2006.173.12:21:57.52#ibcon#first serial, iclass 31, count 0 2006.173.12:21:57.52#ibcon#enter sib2, iclass 31, count 0 2006.173.12:21:57.52#ibcon#flushed, iclass 31, count 0 2006.173.12:21:57.52#ibcon#about to write, iclass 31, count 0 2006.173.12:21:57.52#ibcon#wrote, iclass 31, count 0 2006.173.12:21:57.52#ibcon#about to read 3, iclass 31, count 0 2006.173.12:21:57.54#ibcon#read 3, iclass 31, count 0 2006.173.12:21:57.54#ibcon#about to read 4, iclass 31, count 0 2006.173.12:21:57.54#ibcon#read 4, iclass 31, count 0 2006.173.12:21:57.54#ibcon#about to read 5, iclass 31, count 0 2006.173.12:21:57.54#ibcon#read 5, iclass 31, count 0 2006.173.12:21:57.54#ibcon#about to read 6, iclass 31, count 0 2006.173.12:21:57.54#ibcon#read 6, iclass 31, count 0 2006.173.12:21:57.54#ibcon#end of sib2, iclass 31, count 0 2006.173.12:21:57.54#ibcon#*mode == 0, iclass 31, count 0 2006.173.12:21:57.54#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.12:21:57.54#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.12:21:57.54#ibcon#*before write, iclass 31, count 0 2006.173.12:21:57.54#ibcon#enter sib2, iclass 31, count 0 2006.173.12:21:57.54#ibcon#flushed, iclass 31, count 0 2006.173.12:21:57.54#ibcon#about to write, iclass 31, count 0 2006.173.12:21:57.54#ibcon#wrote, iclass 31, count 0 2006.173.12:21:57.54#ibcon#about to read 3, iclass 31, count 0 2006.173.12:21:57.58#ibcon#read 3, iclass 31, count 0 2006.173.12:21:57.58#ibcon#about to read 4, iclass 31, count 0 2006.173.12:21:57.58#ibcon#read 4, iclass 31, count 0 2006.173.12:21:57.58#ibcon#about to read 5, iclass 31, count 0 2006.173.12:21:57.58#ibcon#read 5, iclass 31, count 0 2006.173.12:21:57.58#ibcon#about to read 6, iclass 31, count 0 2006.173.12:21:57.58#ibcon#read 6, iclass 31, count 0 2006.173.12:21:57.58#ibcon#end of sib2, iclass 31, count 0 2006.173.12:21:57.58#ibcon#*after write, iclass 31, count 0 2006.173.12:21:57.58#ibcon#*before return 0, iclass 31, count 0 2006.173.12:21:57.58#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.12:21:57.58#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.12:21:57.58#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.12:21:57.58#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.12:21:57.58$vck44/vb=6,4 2006.173.12:21:57.58#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.173.12:21:57.58#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.173.12:21:57.58#ibcon#ireg 11 cls_cnt 2 2006.173.12:21:57.58#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.12:21:57.64#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.12:21:57.64#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.12:21:57.64#ibcon#enter wrdev, iclass 33, count 2 2006.173.12:21:57.64#ibcon#first serial, iclass 33, count 2 2006.173.12:21:57.64#ibcon#enter sib2, iclass 33, count 2 2006.173.12:21:57.64#ibcon#flushed, iclass 33, count 2 2006.173.12:21:57.64#ibcon#about to write, iclass 33, count 2 2006.173.12:21:57.64#ibcon#wrote, iclass 33, count 2 2006.173.12:21:57.64#ibcon#about to read 3, iclass 33, count 2 2006.173.12:21:57.66#ibcon#read 3, iclass 33, count 2 2006.173.12:21:57.66#ibcon#about to read 4, iclass 33, count 2 2006.173.12:21:57.66#ibcon#read 4, iclass 33, count 2 2006.173.12:21:57.66#ibcon#about to read 5, iclass 33, count 2 2006.173.12:21:57.66#ibcon#read 5, iclass 33, count 2 2006.173.12:21:57.66#ibcon#about to read 6, iclass 33, count 2 2006.173.12:21:57.66#ibcon#read 6, iclass 33, count 2 2006.173.12:21:57.66#ibcon#end of sib2, iclass 33, count 2 2006.173.12:21:57.66#ibcon#*mode == 0, iclass 33, count 2 2006.173.12:21:57.66#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.173.12:21:57.66#ibcon#[27=AT06-04\r\n] 2006.173.12:21:57.66#ibcon#*before write, iclass 33, count 2 2006.173.12:21:57.66#ibcon#enter sib2, iclass 33, count 2 2006.173.12:21:57.66#ibcon#flushed, iclass 33, count 2 2006.173.12:21:57.66#ibcon#about to write, iclass 33, count 2 2006.173.12:21:57.66#ibcon#wrote, iclass 33, count 2 2006.173.12:21:57.66#ibcon#about to read 3, iclass 33, count 2 2006.173.12:21:57.69#ibcon#read 3, iclass 33, count 2 2006.173.12:21:57.69#ibcon#about to read 4, iclass 33, count 2 2006.173.12:21:57.69#ibcon#read 4, iclass 33, count 2 2006.173.12:21:57.69#ibcon#about to read 5, iclass 33, count 2 2006.173.12:21:57.69#ibcon#read 5, iclass 33, count 2 2006.173.12:21:57.69#ibcon#about to read 6, iclass 33, count 2 2006.173.12:21:57.69#ibcon#read 6, iclass 33, count 2 2006.173.12:21:57.69#ibcon#end of sib2, iclass 33, count 2 2006.173.12:21:57.69#ibcon#*after write, iclass 33, count 2 2006.173.12:21:57.69#ibcon#*before return 0, iclass 33, count 2 2006.173.12:21:57.69#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.12:21:57.69#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.173.12:21:57.69#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.173.12:21:57.69#ibcon#ireg 7 cls_cnt 0 2006.173.12:21:57.69#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.12:21:57.81#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.12:21:57.81#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.12:21:57.81#ibcon#enter wrdev, iclass 33, count 0 2006.173.12:21:57.81#ibcon#first serial, iclass 33, count 0 2006.173.12:21:57.81#ibcon#enter sib2, iclass 33, count 0 2006.173.12:21:57.81#ibcon#flushed, iclass 33, count 0 2006.173.12:21:57.81#ibcon#about to write, iclass 33, count 0 2006.173.12:21:57.81#ibcon#wrote, iclass 33, count 0 2006.173.12:21:57.81#ibcon#about to read 3, iclass 33, count 0 2006.173.12:21:57.83#ibcon#read 3, iclass 33, count 0 2006.173.12:21:57.83#ibcon#about to read 4, iclass 33, count 0 2006.173.12:21:57.83#ibcon#read 4, iclass 33, count 0 2006.173.12:21:57.83#ibcon#about to read 5, iclass 33, count 0 2006.173.12:21:57.83#ibcon#read 5, iclass 33, count 0 2006.173.12:21:57.83#ibcon#about to read 6, iclass 33, count 0 2006.173.12:21:57.83#ibcon#read 6, iclass 33, count 0 2006.173.12:21:57.83#ibcon#end of sib2, iclass 33, count 0 2006.173.12:21:57.83#ibcon#*mode == 0, iclass 33, count 0 2006.173.12:21:57.83#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.12:21:57.83#ibcon#[27=USB\r\n] 2006.173.12:21:57.83#ibcon#*before write, iclass 33, count 0 2006.173.12:21:57.83#ibcon#enter sib2, iclass 33, count 0 2006.173.12:21:57.83#ibcon#flushed, iclass 33, count 0 2006.173.12:21:57.83#ibcon#about to write, iclass 33, count 0 2006.173.12:21:57.83#ibcon#wrote, iclass 33, count 0 2006.173.12:21:57.83#ibcon#about to read 3, iclass 33, count 0 2006.173.12:21:57.86#ibcon#read 3, iclass 33, count 0 2006.173.12:21:57.86#ibcon#about to read 4, iclass 33, count 0 2006.173.12:21:57.86#ibcon#read 4, iclass 33, count 0 2006.173.12:21:57.86#ibcon#about to read 5, iclass 33, count 0 2006.173.12:21:57.86#ibcon#read 5, iclass 33, count 0 2006.173.12:21:57.86#ibcon#about to read 6, iclass 33, count 0 2006.173.12:21:57.86#ibcon#read 6, iclass 33, count 0 2006.173.12:21:57.86#ibcon#end of sib2, iclass 33, count 0 2006.173.12:21:57.86#ibcon#*after write, iclass 33, count 0 2006.173.12:21:57.86#ibcon#*before return 0, iclass 33, count 0 2006.173.12:21:57.86#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.12:21:57.86#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.173.12:21:57.86#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.12:21:57.86#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.12:21:57.86$vck44/vblo=7,734.99 2006.173.12:21:57.86#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.12:21:57.86#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.12:21:57.86#ibcon#ireg 17 cls_cnt 0 2006.173.12:21:57.86#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.12:21:57.86#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.12:21:57.86#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.12:21:57.86#ibcon#enter wrdev, iclass 35, count 0 2006.173.12:21:57.86#ibcon#first serial, iclass 35, count 0 2006.173.12:21:57.86#ibcon#enter sib2, iclass 35, count 0 2006.173.12:21:57.86#ibcon#flushed, iclass 35, count 0 2006.173.12:21:57.86#ibcon#about to write, iclass 35, count 0 2006.173.12:21:57.86#ibcon#wrote, iclass 35, count 0 2006.173.12:21:57.86#ibcon#about to read 3, iclass 35, count 0 2006.173.12:21:57.88#ibcon#read 3, iclass 35, count 0 2006.173.12:21:57.88#ibcon#about to read 4, iclass 35, count 0 2006.173.12:21:57.88#ibcon#read 4, iclass 35, count 0 2006.173.12:21:57.88#ibcon#about to read 5, iclass 35, count 0 2006.173.12:21:57.88#ibcon#read 5, iclass 35, count 0 2006.173.12:21:57.88#ibcon#about to read 6, iclass 35, count 0 2006.173.12:21:57.88#ibcon#read 6, iclass 35, count 0 2006.173.12:21:57.88#ibcon#end of sib2, iclass 35, count 0 2006.173.12:21:57.88#ibcon#*mode == 0, iclass 35, count 0 2006.173.12:21:57.88#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.12:21:57.88#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.12:21:57.88#ibcon#*before write, iclass 35, count 0 2006.173.12:21:57.88#ibcon#enter sib2, iclass 35, count 0 2006.173.12:21:57.88#ibcon#flushed, iclass 35, count 0 2006.173.12:21:57.88#ibcon#about to write, iclass 35, count 0 2006.173.12:21:57.88#ibcon#wrote, iclass 35, count 0 2006.173.12:21:57.88#ibcon#about to read 3, iclass 35, count 0 2006.173.12:21:57.92#ibcon#read 3, iclass 35, count 0 2006.173.12:21:57.92#ibcon#about to read 4, iclass 35, count 0 2006.173.12:21:57.92#ibcon#read 4, iclass 35, count 0 2006.173.12:21:57.92#ibcon#about to read 5, iclass 35, count 0 2006.173.12:21:57.92#ibcon#read 5, iclass 35, count 0 2006.173.12:21:57.92#ibcon#about to read 6, iclass 35, count 0 2006.173.12:21:57.92#ibcon#read 6, iclass 35, count 0 2006.173.12:21:57.92#ibcon#end of sib2, iclass 35, count 0 2006.173.12:21:57.92#ibcon#*after write, iclass 35, count 0 2006.173.12:21:57.92#ibcon#*before return 0, iclass 35, count 0 2006.173.12:21:57.92#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.12:21:57.92#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.12:21:57.92#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.12:21:57.92#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.12:21:57.92$vck44/vb=7,4 2006.173.12:21:57.92#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.173.12:21:57.92#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.173.12:21:57.92#ibcon#ireg 11 cls_cnt 2 2006.173.12:21:57.92#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.12:21:57.98#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.12:21:57.98#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.12:21:57.98#ibcon#enter wrdev, iclass 37, count 2 2006.173.12:21:57.98#ibcon#first serial, iclass 37, count 2 2006.173.12:21:57.98#ibcon#enter sib2, iclass 37, count 2 2006.173.12:21:57.98#ibcon#flushed, iclass 37, count 2 2006.173.12:21:57.98#ibcon#about to write, iclass 37, count 2 2006.173.12:21:57.98#ibcon#wrote, iclass 37, count 2 2006.173.12:21:57.98#ibcon#about to read 3, iclass 37, count 2 2006.173.12:21:58.00#ibcon#read 3, iclass 37, count 2 2006.173.12:21:58.00#ibcon#about to read 4, iclass 37, count 2 2006.173.12:21:58.00#ibcon#read 4, iclass 37, count 2 2006.173.12:21:58.00#ibcon#about to read 5, iclass 37, count 2 2006.173.12:21:58.00#ibcon#read 5, iclass 37, count 2 2006.173.12:21:58.00#ibcon#about to read 6, iclass 37, count 2 2006.173.12:21:58.00#ibcon#read 6, iclass 37, count 2 2006.173.12:21:58.00#ibcon#end of sib2, iclass 37, count 2 2006.173.12:21:58.00#ibcon#*mode == 0, iclass 37, count 2 2006.173.12:21:58.00#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.173.12:21:58.00#ibcon#[27=AT07-04\r\n] 2006.173.12:21:58.00#ibcon#*before write, iclass 37, count 2 2006.173.12:21:58.00#ibcon#enter sib2, iclass 37, count 2 2006.173.12:21:58.00#ibcon#flushed, iclass 37, count 2 2006.173.12:21:58.00#ibcon#about to write, iclass 37, count 2 2006.173.12:21:58.00#ibcon#wrote, iclass 37, count 2 2006.173.12:21:58.00#ibcon#about to read 3, iclass 37, count 2 2006.173.12:21:58.03#ibcon#read 3, iclass 37, count 2 2006.173.12:21:58.03#ibcon#about to read 4, iclass 37, count 2 2006.173.12:21:58.03#ibcon#read 4, iclass 37, count 2 2006.173.12:21:58.03#ibcon#about to read 5, iclass 37, count 2 2006.173.12:21:58.03#ibcon#read 5, iclass 37, count 2 2006.173.12:21:58.03#ibcon#about to read 6, iclass 37, count 2 2006.173.12:21:58.03#ibcon#read 6, iclass 37, count 2 2006.173.12:21:58.03#ibcon#end of sib2, iclass 37, count 2 2006.173.12:21:58.03#ibcon#*after write, iclass 37, count 2 2006.173.12:21:58.03#ibcon#*before return 0, iclass 37, count 2 2006.173.12:21:58.03#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.12:21:58.03#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.173.12:21:58.03#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.173.12:21:58.03#ibcon#ireg 7 cls_cnt 0 2006.173.12:21:58.03#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.12:21:58.15#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.12:21:58.15#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.12:21:58.15#ibcon#enter wrdev, iclass 37, count 0 2006.173.12:21:58.15#ibcon#first serial, iclass 37, count 0 2006.173.12:21:58.15#ibcon#enter sib2, iclass 37, count 0 2006.173.12:21:58.15#ibcon#flushed, iclass 37, count 0 2006.173.12:21:58.15#ibcon#about to write, iclass 37, count 0 2006.173.12:21:58.15#ibcon#wrote, iclass 37, count 0 2006.173.12:21:58.15#ibcon#about to read 3, iclass 37, count 0 2006.173.12:21:58.17#ibcon#read 3, iclass 37, count 0 2006.173.12:21:58.17#ibcon#about to read 4, iclass 37, count 0 2006.173.12:21:58.17#ibcon#read 4, iclass 37, count 0 2006.173.12:21:58.17#ibcon#about to read 5, iclass 37, count 0 2006.173.12:21:58.17#ibcon#read 5, iclass 37, count 0 2006.173.12:21:58.17#ibcon#about to read 6, iclass 37, count 0 2006.173.12:21:58.17#ibcon#read 6, iclass 37, count 0 2006.173.12:21:58.17#ibcon#end of sib2, iclass 37, count 0 2006.173.12:21:58.17#ibcon#*mode == 0, iclass 37, count 0 2006.173.12:21:58.17#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.12:21:58.17#ibcon#[27=USB\r\n] 2006.173.12:21:58.17#ibcon#*before write, iclass 37, count 0 2006.173.12:21:58.17#ibcon#enter sib2, iclass 37, count 0 2006.173.12:21:58.17#ibcon#flushed, iclass 37, count 0 2006.173.12:21:58.17#ibcon#about to write, iclass 37, count 0 2006.173.12:21:58.17#ibcon#wrote, iclass 37, count 0 2006.173.12:21:58.17#ibcon#about to read 3, iclass 37, count 0 2006.173.12:21:58.20#ibcon#read 3, iclass 37, count 0 2006.173.12:21:58.20#ibcon#about to read 4, iclass 37, count 0 2006.173.12:21:58.20#ibcon#read 4, iclass 37, count 0 2006.173.12:21:58.20#ibcon#about to read 5, iclass 37, count 0 2006.173.12:21:58.20#ibcon#read 5, iclass 37, count 0 2006.173.12:21:58.20#ibcon#about to read 6, iclass 37, count 0 2006.173.12:21:58.20#ibcon#read 6, iclass 37, count 0 2006.173.12:21:58.20#ibcon#end of sib2, iclass 37, count 0 2006.173.12:21:58.20#ibcon#*after write, iclass 37, count 0 2006.173.12:21:58.20#ibcon#*before return 0, iclass 37, count 0 2006.173.12:21:58.20#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.12:21:58.20#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.173.12:21:58.20#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.12:21:58.20#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.12:21:58.20$vck44/vblo=8,744.99 2006.173.12:21:58.20#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.12:21:58.20#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.12:21:58.20#ibcon#ireg 17 cls_cnt 0 2006.173.12:21:58.20#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.12:21:58.20#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.12:21:58.20#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.12:21:58.20#ibcon#enter wrdev, iclass 39, count 0 2006.173.12:21:58.20#ibcon#first serial, iclass 39, count 0 2006.173.12:21:58.20#ibcon#enter sib2, iclass 39, count 0 2006.173.12:21:58.20#ibcon#flushed, iclass 39, count 0 2006.173.12:21:58.20#ibcon#about to write, iclass 39, count 0 2006.173.12:21:58.20#ibcon#wrote, iclass 39, count 0 2006.173.12:21:58.20#ibcon#about to read 3, iclass 39, count 0 2006.173.12:21:58.22#ibcon#read 3, iclass 39, count 0 2006.173.12:21:58.22#ibcon#about to read 4, iclass 39, count 0 2006.173.12:21:58.22#ibcon#read 4, iclass 39, count 0 2006.173.12:21:58.22#ibcon#about to read 5, iclass 39, count 0 2006.173.12:21:58.22#ibcon#read 5, iclass 39, count 0 2006.173.12:21:58.22#ibcon#about to read 6, iclass 39, count 0 2006.173.12:21:58.22#ibcon#read 6, iclass 39, count 0 2006.173.12:21:58.22#ibcon#end of sib2, iclass 39, count 0 2006.173.12:21:58.22#ibcon#*mode == 0, iclass 39, count 0 2006.173.12:21:58.22#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.12:21:58.22#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.12:21:58.22#ibcon#*before write, iclass 39, count 0 2006.173.12:21:58.22#ibcon#enter sib2, iclass 39, count 0 2006.173.12:21:58.22#ibcon#flushed, iclass 39, count 0 2006.173.12:21:58.22#ibcon#about to write, iclass 39, count 0 2006.173.12:21:58.22#ibcon#wrote, iclass 39, count 0 2006.173.12:21:58.22#ibcon#about to read 3, iclass 39, count 0 2006.173.12:21:58.26#ibcon#read 3, iclass 39, count 0 2006.173.12:21:58.26#ibcon#about to read 4, iclass 39, count 0 2006.173.12:21:58.26#ibcon#read 4, iclass 39, count 0 2006.173.12:21:58.26#ibcon#about to read 5, iclass 39, count 0 2006.173.12:21:58.26#ibcon#read 5, iclass 39, count 0 2006.173.12:21:58.26#ibcon#about to read 6, iclass 39, count 0 2006.173.12:21:58.26#ibcon#read 6, iclass 39, count 0 2006.173.12:21:58.26#ibcon#end of sib2, iclass 39, count 0 2006.173.12:21:58.26#ibcon#*after write, iclass 39, count 0 2006.173.12:21:58.26#ibcon#*before return 0, iclass 39, count 0 2006.173.12:21:58.26#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.12:21:58.26#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.12:21:58.26#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.12:21:58.26#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.12:21:58.26$vck44/vb=8,4 2006.173.12:21:58.26#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.12:21:58.26#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.12:21:58.26#ibcon#ireg 11 cls_cnt 2 2006.173.12:21:58.26#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.12:21:58.32#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.12:21:58.32#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.12:21:58.32#ibcon#enter wrdev, iclass 3, count 2 2006.173.12:21:58.32#ibcon#first serial, iclass 3, count 2 2006.173.12:21:58.32#ibcon#enter sib2, iclass 3, count 2 2006.173.12:21:58.32#ibcon#flushed, iclass 3, count 2 2006.173.12:21:58.32#ibcon#about to write, iclass 3, count 2 2006.173.12:21:58.32#ibcon#wrote, iclass 3, count 2 2006.173.12:21:58.32#ibcon#about to read 3, iclass 3, count 2 2006.173.12:21:58.34#ibcon#read 3, iclass 3, count 2 2006.173.12:21:58.34#ibcon#about to read 4, iclass 3, count 2 2006.173.12:21:58.34#ibcon#read 4, iclass 3, count 2 2006.173.12:21:58.34#ibcon#about to read 5, iclass 3, count 2 2006.173.12:21:58.34#ibcon#read 5, iclass 3, count 2 2006.173.12:21:58.34#ibcon#about to read 6, iclass 3, count 2 2006.173.12:21:58.34#ibcon#read 6, iclass 3, count 2 2006.173.12:21:58.34#ibcon#end of sib2, iclass 3, count 2 2006.173.12:21:58.34#ibcon#*mode == 0, iclass 3, count 2 2006.173.12:21:58.34#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.12:21:58.34#ibcon#[27=AT08-04\r\n] 2006.173.12:21:58.34#ibcon#*before write, iclass 3, count 2 2006.173.12:21:58.34#ibcon#enter sib2, iclass 3, count 2 2006.173.12:21:58.34#ibcon#flushed, iclass 3, count 2 2006.173.12:21:58.34#ibcon#about to write, iclass 3, count 2 2006.173.12:21:58.34#ibcon#wrote, iclass 3, count 2 2006.173.12:21:58.34#ibcon#about to read 3, iclass 3, count 2 2006.173.12:21:58.37#ibcon#read 3, iclass 3, count 2 2006.173.12:21:58.37#ibcon#about to read 4, iclass 3, count 2 2006.173.12:21:58.37#ibcon#read 4, iclass 3, count 2 2006.173.12:21:58.37#ibcon#about to read 5, iclass 3, count 2 2006.173.12:21:58.37#ibcon#read 5, iclass 3, count 2 2006.173.12:21:58.37#ibcon#about to read 6, iclass 3, count 2 2006.173.12:21:58.37#ibcon#read 6, iclass 3, count 2 2006.173.12:21:58.37#ibcon#end of sib2, iclass 3, count 2 2006.173.12:21:58.37#ibcon#*after write, iclass 3, count 2 2006.173.12:21:58.37#ibcon#*before return 0, iclass 3, count 2 2006.173.12:21:58.37#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.12:21:58.37#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.12:21:58.37#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.12:21:58.37#ibcon#ireg 7 cls_cnt 0 2006.173.12:21:58.37#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.12:21:58.49#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.12:21:58.49#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.12:21:58.49#ibcon#enter wrdev, iclass 3, count 0 2006.173.12:21:58.49#ibcon#first serial, iclass 3, count 0 2006.173.12:21:58.49#ibcon#enter sib2, iclass 3, count 0 2006.173.12:21:58.49#ibcon#flushed, iclass 3, count 0 2006.173.12:21:58.49#ibcon#about to write, iclass 3, count 0 2006.173.12:21:58.49#ibcon#wrote, iclass 3, count 0 2006.173.12:21:58.49#ibcon#about to read 3, iclass 3, count 0 2006.173.12:21:58.51#ibcon#read 3, iclass 3, count 0 2006.173.12:21:58.51#ibcon#about to read 4, iclass 3, count 0 2006.173.12:21:58.51#ibcon#read 4, iclass 3, count 0 2006.173.12:21:58.51#ibcon#about to read 5, iclass 3, count 0 2006.173.12:21:58.51#ibcon#read 5, iclass 3, count 0 2006.173.12:21:58.51#ibcon#about to read 6, iclass 3, count 0 2006.173.12:21:58.51#ibcon#read 6, iclass 3, count 0 2006.173.12:21:58.51#ibcon#end of sib2, iclass 3, count 0 2006.173.12:21:58.51#ibcon#*mode == 0, iclass 3, count 0 2006.173.12:21:58.51#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.12:21:58.51#ibcon#[27=USB\r\n] 2006.173.12:21:58.51#ibcon#*before write, iclass 3, count 0 2006.173.12:21:58.51#ibcon#enter sib2, iclass 3, count 0 2006.173.12:21:58.51#ibcon#flushed, iclass 3, count 0 2006.173.12:21:58.51#ibcon#about to write, iclass 3, count 0 2006.173.12:21:58.51#ibcon#wrote, iclass 3, count 0 2006.173.12:21:58.51#ibcon#about to read 3, iclass 3, count 0 2006.173.12:21:58.54#ibcon#read 3, iclass 3, count 0 2006.173.12:21:58.54#ibcon#about to read 4, iclass 3, count 0 2006.173.12:21:58.54#ibcon#read 4, iclass 3, count 0 2006.173.12:21:58.54#ibcon#about to read 5, iclass 3, count 0 2006.173.12:21:58.54#ibcon#read 5, iclass 3, count 0 2006.173.12:21:58.54#ibcon#about to read 6, iclass 3, count 0 2006.173.12:21:58.54#ibcon#read 6, iclass 3, count 0 2006.173.12:21:58.54#ibcon#end of sib2, iclass 3, count 0 2006.173.12:21:58.54#ibcon#*after write, iclass 3, count 0 2006.173.12:21:58.54#ibcon#*before return 0, iclass 3, count 0 2006.173.12:21:58.54#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.12:21:58.54#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.12:21:58.54#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.12:21:58.54#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.12:21:58.54$vck44/vabw=wide 2006.173.12:21:58.54#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.12:21:58.54#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.12:21:58.54#ibcon#ireg 8 cls_cnt 0 2006.173.12:21:58.54#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.12:21:58.54#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.12:21:58.54#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.12:21:58.54#ibcon#enter wrdev, iclass 5, count 0 2006.173.12:21:58.54#ibcon#first serial, iclass 5, count 0 2006.173.12:21:58.54#ibcon#enter sib2, iclass 5, count 0 2006.173.12:21:58.54#ibcon#flushed, iclass 5, count 0 2006.173.12:21:58.54#ibcon#about to write, iclass 5, count 0 2006.173.12:21:58.54#ibcon#wrote, iclass 5, count 0 2006.173.12:21:58.54#ibcon#about to read 3, iclass 5, count 0 2006.173.12:21:58.56#ibcon#read 3, iclass 5, count 0 2006.173.12:21:58.56#ibcon#about to read 4, iclass 5, count 0 2006.173.12:21:58.56#ibcon#read 4, iclass 5, count 0 2006.173.12:21:58.56#ibcon#about to read 5, iclass 5, count 0 2006.173.12:21:58.56#ibcon#read 5, iclass 5, count 0 2006.173.12:21:58.56#ibcon#about to read 6, iclass 5, count 0 2006.173.12:21:58.56#ibcon#read 6, iclass 5, count 0 2006.173.12:21:58.56#ibcon#end of sib2, iclass 5, count 0 2006.173.12:21:58.56#ibcon#*mode == 0, iclass 5, count 0 2006.173.12:21:58.56#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.12:21:58.56#ibcon#[25=BW32\r\n] 2006.173.12:21:58.56#ibcon#*before write, iclass 5, count 0 2006.173.12:21:58.56#ibcon#enter sib2, iclass 5, count 0 2006.173.12:21:58.56#ibcon#flushed, iclass 5, count 0 2006.173.12:21:58.56#ibcon#about to write, iclass 5, count 0 2006.173.12:21:58.56#ibcon#wrote, iclass 5, count 0 2006.173.12:21:58.56#ibcon#about to read 3, iclass 5, count 0 2006.173.12:21:58.59#ibcon#read 3, iclass 5, count 0 2006.173.12:21:58.59#ibcon#about to read 4, iclass 5, count 0 2006.173.12:21:58.59#ibcon#read 4, iclass 5, count 0 2006.173.12:21:58.59#ibcon#about to read 5, iclass 5, count 0 2006.173.12:21:58.59#ibcon#read 5, iclass 5, count 0 2006.173.12:21:58.59#ibcon#about to read 6, iclass 5, count 0 2006.173.12:21:58.59#ibcon#read 6, iclass 5, count 0 2006.173.12:21:58.59#ibcon#end of sib2, iclass 5, count 0 2006.173.12:21:58.59#ibcon#*after write, iclass 5, count 0 2006.173.12:21:58.59#ibcon#*before return 0, iclass 5, count 0 2006.173.12:21:58.59#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.12:21:58.59#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.12:21:58.59#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.12:21:58.59#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.12:21:58.59$vck44/vbbw=wide 2006.173.12:21:58.59#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.12:21:58.59#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.12:21:58.59#ibcon#ireg 8 cls_cnt 0 2006.173.12:21:58.59#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.12:21:58.66#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.12:21:58.66#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.12:21:58.66#ibcon#enter wrdev, iclass 7, count 0 2006.173.12:21:58.66#ibcon#first serial, iclass 7, count 0 2006.173.12:21:58.66#ibcon#enter sib2, iclass 7, count 0 2006.173.12:21:58.66#ibcon#flushed, iclass 7, count 0 2006.173.12:21:58.66#ibcon#about to write, iclass 7, count 0 2006.173.12:21:58.66#ibcon#wrote, iclass 7, count 0 2006.173.12:21:58.66#ibcon#about to read 3, iclass 7, count 0 2006.173.12:21:58.68#ibcon#read 3, iclass 7, count 0 2006.173.12:21:58.68#ibcon#about to read 4, iclass 7, count 0 2006.173.12:21:58.68#ibcon#read 4, iclass 7, count 0 2006.173.12:21:58.68#ibcon#about to read 5, iclass 7, count 0 2006.173.12:21:58.68#ibcon#read 5, iclass 7, count 0 2006.173.12:21:58.68#ibcon#about to read 6, iclass 7, count 0 2006.173.12:21:58.68#ibcon#read 6, iclass 7, count 0 2006.173.12:21:58.68#ibcon#end of sib2, iclass 7, count 0 2006.173.12:21:58.68#ibcon#*mode == 0, iclass 7, count 0 2006.173.12:21:58.68#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.12:21:58.68#ibcon#[27=BW32\r\n] 2006.173.12:21:58.68#ibcon#*before write, iclass 7, count 0 2006.173.12:21:58.68#ibcon#enter sib2, iclass 7, count 0 2006.173.12:21:58.68#ibcon#flushed, iclass 7, count 0 2006.173.12:21:58.68#ibcon#about to write, iclass 7, count 0 2006.173.12:21:58.68#ibcon#wrote, iclass 7, count 0 2006.173.12:21:58.68#ibcon#about to read 3, iclass 7, count 0 2006.173.12:21:58.71#ibcon#read 3, iclass 7, count 0 2006.173.12:21:58.71#ibcon#about to read 4, iclass 7, count 0 2006.173.12:21:58.71#ibcon#read 4, iclass 7, count 0 2006.173.12:21:58.71#ibcon#about to read 5, iclass 7, count 0 2006.173.12:21:58.71#ibcon#read 5, iclass 7, count 0 2006.173.12:21:58.71#ibcon#about to read 6, iclass 7, count 0 2006.173.12:21:58.71#ibcon#read 6, iclass 7, count 0 2006.173.12:21:58.71#ibcon#end of sib2, iclass 7, count 0 2006.173.12:21:58.71#ibcon#*after write, iclass 7, count 0 2006.173.12:21:58.71#ibcon#*before return 0, iclass 7, count 0 2006.173.12:21:58.71#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.12:21:58.71#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.12:21:58.71#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.12:21:58.71#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.12:21:58.71$setupk4/ifdk4 2006.173.12:21:58.71$ifdk4/lo= 2006.173.12:21:58.71$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.12:21:58.71$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.12:21:58.71$ifdk4/patch= 2006.173.12:21:58.71$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.12:21:58.72$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.12:21:58.72$setupk4/!*+20s 2006.173.12:22:01.22#abcon#<5=/05 1.2 2.1 22.17 951004.2\r\n> 2006.173.12:22:01.24#abcon#{5=INTERFACE CLEAR} 2006.173.12:22:01.30#abcon#[5=S1D000X0/0*\r\n] 2006.173.12:22:11.39#abcon#<5=/05 1.2 2.1 22.17 951004.2\r\n> 2006.173.12:22:11.41#abcon#{5=INTERFACE CLEAR} 2006.173.12:22:11.47#abcon#[5=S1D000X0/0*\r\n] 2006.173.12:22:13.24$setupk4/"tpicd 2006.173.12:22:13.24$setupk4/echo=off 2006.173.12:22:13.24$setupk4/xlog=off 2006.173.12:22:13.24:!2006.173.12:23:28 2006.173.12:22:32.13#trakl#Source acquired 2006.173.12:22:33.13#flagr#flagr/antenna,acquired 2006.173.12:23:28.00:preob 2006.173.12:23:28.14/onsource/TRACKING 2006.173.12:23:28.14:!2006.173.12:23:38 2006.173.12:23:38.00:"tape 2006.173.12:23:38.00:"st=record 2006.173.12:23:38.00:data_valid=on 2006.173.12:23:38.00:midob 2006.173.12:23:39.14/onsource/TRACKING 2006.173.12:23:39.14/wx/22.16,1004.4,95 2006.173.12:23:39.24/cable/+6.5049E-03 2006.173.12:23:40.33/va/01,07,usb,yes,39,42 2006.173.12:23:40.33/va/02,06,usb,yes,38,39 2006.173.12:23:40.33/va/03,05,usb,yes,49,51 2006.173.12:23:40.33/va/04,06,usb,yes,39,41 2006.173.12:23:40.33/va/05,04,usb,yes,31,31 2006.173.12:23:40.33/va/06,03,usb,yes,43,43 2006.173.12:23:40.33/va/07,04,usb,yes,35,36 2006.173.12:23:40.33/va/08,04,usb,yes,30,36 2006.173.12:23:40.56/valo/01,524.99,yes,locked 2006.173.12:23:40.56/valo/02,534.99,yes,locked 2006.173.12:23:40.56/valo/03,564.99,yes,locked 2006.173.12:23:40.56/valo/04,624.99,yes,locked 2006.173.12:23:40.56/valo/05,734.99,yes,locked 2006.173.12:23:40.56/valo/06,814.99,yes,locked 2006.173.12:23:40.56/valo/07,864.99,yes,locked 2006.173.12:23:40.56/valo/08,884.99,yes,locked 2006.173.12:23:41.65/vb/01,04,usb,yes,37,34 2006.173.12:23:41.65/vb/02,04,usb,yes,39,39 2006.173.12:23:41.65/vb/03,04,usb,yes,36,39 2006.173.12:23:41.65/vb/04,04,usb,yes,41,39 2006.173.12:23:41.65/vb/05,04,usb,yes,32,35 2006.173.12:23:41.65/vb/06,04,usb,yes,37,33 2006.173.12:23:41.65/vb/07,04,usb,yes,37,37 2006.173.12:23:41.65/vb/08,04,usb,yes,34,38 2006.173.12:23:41.89/vblo/01,629.99,yes,locked 2006.173.12:23:41.89/vblo/02,634.99,yes,locked 2006.173.12:23:41.89/vblo/03,649.99,yes,locked 2006.173.12:23:41.89/vblo/04,679.99,yes,locked 2006.173.12:23:41.89/vblo/05,709.99,yes,locked 2006.173.12:23:41.89/vblo/06,719.99,yes,locked 2006.173.12:23:41.89/vblo/07,734.99,yes,locked 2006.173.12:23:41.89/vblo/08,744.99,yes,locked 2006.173.12:23:42.04/vabw/8 2006.173.12:23:42.19/vbbw/8 2006.173.12:23:42.28/xfe/off,on,15.2 2006.173.12:23:42.66/ifatt/23,28,28,28 2006.173.12:23:43.07/fmout-gps/S +3.97E-07 2006.173.12:23:43.12:!2006.173.12:25:18 2006.173.12:25:18.01:data_valid=off 2006.173.12:25:18.02:"et 2006.173.12:25:18.02:!+3s 2006.173.12:25:21.03:"tape 2006.173.12:25:21.04:postob 2006.173.12:25:21.21/cable/+6.5063E-03 2006.173.12:25:21.22/wx/22.16,1004.4,95 2006.173.12:25:21.27/fmout-gps/S +3.98E-07 2006.173.12:25:21.28:scan_name=173-1232,jd0606,230 2006.173.12:25:21.28:source=1044+719,104827.62,714335.9,2000.0,cw 2006.173.12:25:23.14#flagr#flagr/antenna,new-source 2006.173.12:25:23.15:checkk5 2006.173.12:25:23.56/chk_autoobs//k5ts1/ autoobs is running! 2006.173.12:25:23.97/chk_autoobs//k5ts2/ autoobs is running! 2006.173.12:25:24.38/chk_autoobs//k5ts3/ autoobs is running! 2006.173.12:25:24.77/chk_autoobs//k5ts4/ autoobs is running! 2006.173.12:25:25.19/chk_obsdata//k5ts1/T1731223??a.dat file size is correct (nominal:400MB, actual:396MB). 2006.173.12:25:25.60/chk_obsdata//k5ts2/T1731223??b.dat file size is correct (nominal:400MB, actual:396MB). 2006.173.12:25:25.99/chk_obsdata//k5ts3/T1731223??c.dat file size is correct (nominal:400MB, actual:396MB). 2006.173.12:25:26.39/chk_obsdata//k5ts4/T1731223??d.dat file size is correct (nominal:400MB, actual:396MB). 2006.173.12:25:27.11/k5log//k5ts1_log_newline 2006.173.12:25:27.81/k5log//k5ts2_log_newline 2006.173.12:25:28.53/k5log//k5ts3_log_newline 2006.173.12:25:29.23/k5log//k5ts4_log_newline 2006.173.12:25:29.26/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.12:25:29.26:setupk4=1 2006.173.12:25:29.26$setupk4/echo=on 2006.173.12:25:29.26$setupk4/pcalon 2006.173.12:25:29.26$pcalon/"no phase cal control is implemented here 2006.173.12:25:29.26$setupk4/"tpicd=stop 2006.173.12:25:29.26$setupk4/"rec=synch_on 2006.173.12:25:29.26$setupk4/"rec_mode=128 2006.173.12:25:29.26$setupk4/!* 2006.173.12:25:29.26$setupk4/recpk4 2006.173.12:25:29.26$recpk4/recpatch= 2006.173.12:25:29.27$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.12:25:29.27$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.12:25:29.27$setupk4/vck44 2006.173.12:25:29.27$vck44/valo=1,524.99 2006.173.12:25:29.27#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.12:25:29.27#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.12:25:29.27#ibcon#ireg 17 cls_cnt 0 2006.173.12:25:29.27#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.12:25:29.27#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.12:25:29.27#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.12:25:29.27#ibcon#enter wrdev, iclass 26, count 0 2006.173.12:25:29.27#ibcon#first serial, iclass 26, count 0 2006.173.12:25:29.27#ibcon#enter sib2, iclass 26, count 0 2006.173.12:25:29.27#ibcon#flushed, iclass 26, count 0 2006.173.12:25:29.27#ibcon#about to write, iclass 26, count 0 2006.173.12:25:29.27#ibcon#wrote, iclass 26, count 0 2006.173.12:25:29.27#ibcon#about to read 3, iclass 26, count 0 2006.173.12:25:29.28#ibcon#read 3, iclass 26, count 0 2006.173.12:25:29.28#ibcon#about to read 4, iclass 26, count 0 2006.173.12:25:29.28#ibcon#read 4, iclass 26, count 0 2006.173.12:25:29.28#ibcon#about to read 5, iclass 26, count 0 2006.173.12:25:29.28#ibcon#read 5, iclass 26, count 0 2006.173.12:25:29.28#ibcon#about to read 6, iclass 26, count 0 2006.173.12:25:29.28#ibcon#read 6, iclass 26, count 0 2006.173.12:25:29.28#ibcon#end of sib2, iclass 26, count 0 2006.173.12:25:29.28#ibcon#*mode == 0, iclass 26, count 0 2006.173.12:25:29.28#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.12:25:29.28#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.12:25:29.28#ibcon#*before write, iclass 26, count 0 2006.173.12:25:29.28#ibcon#enter sib2, iclass 26, count 0 2006.173.12:25:29.28#ibcon#flushed, iclass 26, count 0 2006.173.12:25:29.28#ibcon#about to write, iclass 26, count 0 2006.173.12:25:29.28#ibcon#wrote, iclass 26, count 0 2006.173.12:25:29.28#ibcon#about to read 3, iclass 26, count 0 2006.173.12:25:29.33#ibcon#read 3, iclass 26, count 0 2006.173.12:25:29.33#ibcon#about to read 4, iclass 26, count 0 2006.173.12:25:29.33#ibcon#read 4, iclass 26, count 0 2006.173.12:25:29.33#ibcon#about to read 5, iclass 26, count 0 2006.173.12:25:29.33#ibcon#read 5, iclass 26, count 0 2006.173.12:25:29.33#ibcon#about to read 6, iclass 26, count 0 2006.173.12:25:29.33#ibcon#read 6, iclass 26, count 0 2006.173.12:25:29.33#ibcon#end of sib2, iclass 26, count 0 2006.173.12:25:29.33#ibcon#*after write, iclass 26, count 0 2006.173.12:25:29.33#ibcon#*before return 0, iclass 26, count 0 2006.173.12:25:29.33#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.12:25:29.33#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.12:25:29.33#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.12:25:29.33#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.12:25:29.33$vck44/va=1,7 2006.173.12:25:29.33#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.12:25:29.33#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.12:25:29.33#ibcon#ireg 11 cls_cnt 2 2006.173.12:25:29.33#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.12:25:29.33#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.12:25:29.33#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.12:25:29.33#ibcon#enter wrdev, iclass 28, count 2 2006.173.12:25:29.33#ibcon#first serial, iclass 28, count 2 2006.173.12:25:29.33#ibcon#enter sib2, iclass 28, count 2 2006.173.12:25:29.33#ibcon#flushed, iclass 28, count 2 2006.173.12:25:29.33#ibcon#about to write, iclass 28, count 2 2006.173.12:25:29.33#ibcon#wrote, iclass 28, count 2 2006.173.12:25:29.33#ibcon#about to read 3, iclass 28, count 2 2006.173.12:25:29.35#ibcon#read 3, iclass 28, count 2 2006.173.12:25:29.35#ibcon#about to read 4, iclass 28, count 2 2006.173.12:25:29.35#ibcon#read 4, iclass 28, count 2 2006.173.12:25:29.35#ibcon#about to read 5, iclass 28, count 2 2006.173.12:25:29.35#ibcon#read 5, iclass 28, count 2 2006.173.12:25:29.35#ibcon#about to read 6, iclass 28, count 2 2006.173.12:25:29.35#ibcon#read 6, iclass 28, count 2 2006.173.12:25:29.35#ibcon#end of sib2, iclass 28, count 2 2006.173.12:25:29.35#ibcon#*mode == 0, iclass 28, count 2 2006.173.12:25:29.35#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.12:25:29.35#ibcon#[25=AT01-07\r\n] 2006.173.12:25:29.35#ibcon#*before write, iclass 28, count 2 2006.173.12:25:29.35#ibcon#enter sib2, iclass 28, count 2 2006.173.12:25:29.35#ibcon#flushed, iclass 28, count 2 2006.173.12:25:29.35#ibcon#about to write, iclass 28, count 2 2006.173.12:25:29.35#ibcon#wrote, iclass 28, count 2 2006.173.12:25:29.35#ibcon#about to read 3, iclass 28, count 2 2006.173.12:25:29.38#ibcon#read 3, iclass 28, count 2 2006.173.12:25:29.38#ibcon#about to read 4, iclass 28, count 2 2006.173.12:25:29.38#ibcon#read 4, iclass 28, count 2 2006.173.12:25:29.38#ibcon#about to read 5, iclass 28, count 2 2006.173.12:25:29.38#ibcon#read 5, iclass 28, count 2 2006.173.12:25:29.38#ibcon#about to read 6, iclass 28, count 2 2006.173.12:25:29.38#ibcon#read 6, iclass 28, count 2 2006.173.12:25:29.38#ibcon#end of sib2, iclass 28, count 2 2006.173.12:25:29.38#ibcon#*after write, iclass 28, count 2 2006.173.12:25:29.38#ibcon#*before return 0, iclass 28, count 2 2006.173.12:25:29.38#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.12:25:29.38#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.12:25:29.38#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.12:25:29.38#ibcon#ireg 7 cls_cnt 0 2006.173.12:25:29.38#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.12:25:29.50#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.12:25:29.50#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.12:25:29.50#ibcon#enter wrdev, iclass 28, count 0 2006.173.12:25:29.50#ibcon#first serial, iclass 28, count 0 2006.173.12:25:29.50#ibcon#enter sib2, iclass 28, count 0 2006.173.12:25:29.50#ibcon#flushed, iclass 28, count 0 2006.173.12:25:29.50#ibcon#about to write, iclass 28, count 0 2006.173.12:25:29.50#ibcon#wrote, iclass 28, count 0 2006.173.12:25:29.50#ibcon#about to read 3, iclass 28, count 0 2006.173.12:25:29.52#ibcon#read 3, iclass 28, count 0 2006.173.12:25:29.52#ibcon#about to read 4, iclass 28, count 0 2006.173.12:25:29.52#ibcon#read 4, iclass 28, count 0 2006.173.12:25:29.52#ibcon#about to read 5, iclass 28, count 0 2006.173.12:25:29.52#ibcon#read 5, iclass 28, count 0 2006.173.12:25:29.52#ibcon#about to read 6, iclass 28, count 0 2006.173.12:25:29.52#ibcon#read 6, iclass 28, count 0 2006.173.12:25:29.52#ibcon#end of sib2, iclass 28, count 0 2006.173.12:25:29.52#ibcon#*mode == 0, iclass 28, count 0 2006.173.12:25:29.52#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.12:25:29.52#ibcon#[25=USB\r\n] 2006.173.12:25:29.52#ibcon#*before write, iclass 28, count 0 2006.173.12:25:29.52#ibcon#enter sib2, iclass 28, count 0 2006.173.12:25:29.52#ibcon#flushed, iclass 28, count 0 2006.173.12:25:29.52#ibcon#about to write, iclass 28, count 0 2006.173.12:25:29.52#ibcon#wrote, iclass 28, count 0 2006.173.12:25:29.52#ibcon#about to read 3, iclass 28, count 0 2006.173.12:25:29.55#ibcon#read 3, iclass 28, count 0 2006.173.12:25:29.55#ibcon#about to read 4, iclass 28, count 0 2006.173.12:25:29.55#ibcon#read 4, iclass 28, count 0 2006.173.12:25:29.55#ibcon#about to read 5, iclass 28, count 0 2006.173.12:25:29.55#ibcon#read 5, iclass 28, count 0 2006.173.12:25:29.55#ibcon#about to read 6, iclass 28, count 0 2006.173.12:25:29.55#ibcon#read 6, iclass 28, count 0 2006.173.12:25:29.55#ibcon#end of sib2, iclass 28, count 0 2006.173.12:25:29.55#ibcon#*after write, iclass 28, count 0 2006.173.12:25:29.55#ibcon#*before return 0, iclass 28, count 0 2006.173.12:25:29.55#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.12:25:29.55#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.12:25:29.55#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.12:25:29.55#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.12:25:29.55$vck44/valo=2,534.99 2006.173.12:25:29.55#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.12:25:29.55#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.12:25:29.55#ibcon#ireg 17 cls_cnt 0 2006.173.12:25:29.55#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.12:25:29.55#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.12:25:29.55#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.12:25:29.55#ibcon#enter wrdev, iclass 30, count 0 2006.173.12:25:29.55#ibcon#first serial, iclass 30, count 0 2006.173.12:25:29.55#ibcon#enter sib2, iclass 30, count 0 2006.173.12:25:29.55#ibcon#flushed, iclass 30, count 0 2006.173.12:25:29.55#ibcon#about to write, iclass 30, count 0 2006.173.12:25:29.55#ibcon#wrote, iclass 30, count 0 2006.173.12:25:29.55#ibcon#about to read 3, iclass 30, count 0 2006.173.12:25:29.57#ibcon#read 3, iclass 30, count 0 2006.173.12:25:29.57#ibcon#about to read 4, iclass 30, count 0 2006.173.12:25:29.57#ibcon#read 4, iclass 30, count 0 2006.173.12:25:29.57#ibcon#about to read 5, iclass 30, count 0 2006.173.12:25:29.57#ibcon#read 5, iclass 30, count 0 2006.173.12:25:29.57#ibcon#about to read 6, iclass 30, count 0 2006.173.12:25:29.57#ibcon#read 6, iclass 30, count 0 2006.173.12:25:29.57#ibcon#end of sib2, iclass 30, count 0 2006.173.12:25:29.57#ibcon#*mode == 0, iclass 30, count 0 2006.173.12:25:29.57#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.12:25:29.57#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.12:25:29.57#ibcon#*before write, iclass 30, count 0 2006.173.12:25:29.57#ibcon#enter sib2, iclass 30, count 0 2006.173.12:25:29.57#ibcon#flushed, iclass 30, count 0 2006.173.12:25:29.57#ibcon#about to write, iclass 30, count 0 2006.173.12:25:29.57#ibcon#wrote, iclass 30, count 0 2006.173.12:25:29.57#ibcon#about to read 3, iclass 30, count 0 2006.173.12:25:29.61#ibcon#read 3, iclass 30, count 0 2006.173.12:25:29.61#ibcon#about to read 4, iclass 30, count 0 2006.173.12:25:29.61#ibcon#read 4, iclass 30, count 0 2006.173.12:25:29.61#ibcon#about to read 5, iclass 30, count 0 2006.173.12:25:29.61#ibcon#read 5, iclass 30, count 0 2006.173.12:25:29.61#ibcon#about to read 6, iclass 30, count 0 2006.173.12:25:29.61#ibcon#read 6, iclass 30, count 0 2006.173.12:25:29.61#ibcon#end of sib2, iclass 30, count 0 2006.173.12:25:29.61#ibcon#*after write, iclass 30, count 0 2006.173.12:25:29.61#ibcon#*before return 0, iclass 30, count 0 2006.173.12:25:29.61#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.12:25:29.61#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.12:25:29.61#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.12:25:29.61#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.12:25:29.61$vck44/va=2,6 2006.173.12:25:29.61#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.173.12:25:29.61#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.173.12:25:29.61#ibcon#ireg 11 cls_cnt 2 2006.173.12:25:29.61#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.12:25:29.67#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.12:25:29.67#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.12:25:29.67#ibcon#enter wrdev, iclass 32, count 2 2006.173.12:25:29.67#ibcon#first serial, iclass 32, count 2 2006.173.12:25:29.67#ibcon#enter sib2, iclass 32, count 2 2006.173.12:25:29.67#ibcon#flushed, iclass 32, count 2 2006.173.12:25:29.67#ibcon#about to write, iclass 32, count 2 2006.173.12:25:29.67#ibcon#wrote, iclass 32, count 2 2006.173.12:25:29.67#ibcon#about to read 3, iclass 32, count 2 2006.173.12:25:29.69#ibcon#read 3, iclass 32, count 2 2006.173.12:25:29.69#ibcon#about to read 4, iclass 32, count 2 2006.173.12:25:29.69#ibcon#read 4, iclass 32, count 2 2006.173.12:25:29.69#ibcon#about to read 5, iclass 32, count 2 2006.173.12:25:29.69#ibcon#read 5, iclass 32, count 2 2006.173.12:25:29.69#ibcon#about to read 6, iclass 32, count 2 2006.173.12:25:29.69#ibcon#read 6, iclass 32, count 2 2006.173.12:25:29.69#ibcon#end of sib2, iclass 32, count 2 2006.173.12:25:29.69#ibcon#*mode == 0, iclass 32, count 2 2006.173.12:25:29.69#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.173.12:25:29.69#ibcon#[25=AT02-06\r\n] 2006.173.12:25:29.69#ibcon#*before write, iclass 32, count 2 2006.173.12:25:29.69#ibcon#enter sib2, iclass 32, count 2 2006.173.12:25:29.69#ibcon#flushed, iclass 32, count 2 2006.173.12:25:29.69#ibcon#about to write, iclass 32, count 2 2006.173.12:25:29.69#ibcon#wrote, iclass 32, count 2 2006.173.12:25:29.69#ibcon#about to read 3, iclass 32, count 2 2006.173.12:25:29.72#ibcon#read 3, iclass 32, count 2 2006.173.12:25:29.72#ibcon#about to read 4, iclass 32, count 2 2006.173.12:25:29.72#ibcon#read 4, iclass 32, count 2 2006.173.12:25:29.72#ibcon#about to read 5, iclass 32, count 2 2006.173.12:25:29.72#ibcon#read 5, iclass 32, count 2 2006.173.12:25:29.72#ibcon#about to read 6, iclass 32, count 2 2006.173.12:25:29.72#ibcon#read 6, iclass 32, count 2 2006.173.12:25:29.72#ibcon#end of sib2, iclass 32, count 2 2006.173.12:25:29.72#ibcon#*after write, iclass 32, count 2 2006.173.12:25:29.72#ibcon#*before return 0, iclass 32, count 2 2006.173.12:25:29.72#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.12:25:29.72#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.173.12:25:29.72#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.173.12:25:29.72#ibcon#ireg 7 cls_cnt 0 2006.173.12:25:29.72#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.12:25:29.84#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.12:25:29.84#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.12:25:29.84#ibcon#enter wrdev, iclass 32, count 0 2006.173.12:25:29.84#ibcon#first serial, iclass 32, count 0 2006.173.12:25:29.84#ibcon#enter sib2, iclass 32, count 0 2006.173.12:25:29.84#ibcon#flushed, iclass 32, count 0 2006.173.12:25:29.84#ibcon#about to write, iclass 32, count 0 2006.173.12:25:29.84#ibcon#wrote, iclass 32, count 0 2006.173.12:25:29.84#ibcon#about to read 3, iclass 32, count 0 2006.173.12:25:29.86#ibcon#read 3, iclass 32, count 0 2006.173.12:25:29.86#ibcon#about to read 4, iclass 32, count 0 2006.173.12:25:29.86#ibcon#read 4, iclass 32, count 0 2006.173.12:25:29.86#ibcon#about to read 5, iclass 32, count 0 2006.173.12:25:29.86#ibcon#read 5, iclass 32, count 0 2006.173.12:25:29.86#ibcon#about to read 6, iclass 32, count 0 2006.173.12:25:29.86#ibcon#read 6, iclass 32, count 0 2006.173.12:25:29.86#ibcon#end of sib2, iclass 32, count 0 2006.173.12:25:29.86#ibcon#*mode == 0, iclass 32, count 0 2006.173.12:25:29.86#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.12:25:29.86#ibcon#[25=USB\r\n] 2006.173.12:25:29.86#ibcon#*before write, iclass 32, count 0 2006.173.12:25:29.86#ibcon#enter sib2, iclass 32, count 0 2006.173.12:25:29.86#ibcon#flushed, iclass 32, count 0 2006.173.12:25:29.86#ibcon#about to write, iclass 32, count 0 2006.173.12:25:29.86#ibcon#wrote, iclass 32, count 0 2006.173.12:25:29.86#ibcon#about to read 3, iclass 32, count 0 2006.173.12:25:29.89#ibcon#read 3, iclass 32, count 0 2006.173.12:25:29.89#ibcon#about to read 4, iclass 32, count 0 2006.173.12:25:29.89#ibcon#read 4, iclass 32, count 0 2006.173.12:25:29.89#ibcon#about to read 5, iclass 32, count 0 2006.173.12:25:29.89#ibcon#read 5, iclass 32, count 0 2006.173.12:25:29.89#ibcon#about to read 6, iclass 32, count 0 2006.173.12:25:29.89#ibcon#read 6, iclass 32, count 0 2006.173.12:25:29.89#ibcon#end of sib2, iclass 32, count 0 2006.173.12:25:29.89#ibcon#*after write, iclass 32, count 0 2006.173.12:25:29.89#ibcon#*before return 0, iclass 32, count 0 2006.173.12:25:29.89#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.12:25:29.89#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.173.12:25:29.89#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.12:25:29.89#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.12:25:29.89$vck44/valo=3,564.99 2006.173.12:25:29.89#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.12:25:29.89#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.12:25:29.89#ibcon#ireg 17 cls_cnt 0 2006.173.12:25:29.89#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.12:25:29.89#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.12:25:29.89#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.12:25:29.89#ibcon#enter wrdev, iclass 34, count 0 2006.173.12:25:29.89#ibcon#first serial, iclass 34, count 0 2006.173.12:25:29.89#ibcon#enter sib2, iclass 34, count 0 2006.173.12:25:29.89#ibcon#flushed, iclass 34, count 0 2006.173.12:25:29.89#ibcon#about to write, iclass 34, count 0 2006.173.12:25:29.89#ibcon#wrote, iclass 34, count 0 2006.173.12:25:29.89#ibcon#about to read 3, iclass 34, count 0 2006.173.12:25:29.91#ibcon#read 3, iclass 34, count 0 2006.173.12:25:29.91#ibcon#about to read 4, iclass 34, count 0 2006.173.12:25:29.91#ibcon#read 4, iclass 34, count 0 2006.173.12:25:29.91#ibcon#about to read 5, iclass 34, count 0 2006.173.12:25:29.91#ibcon#read 5, iclass 34, count 0 2006.173.12:25:29.91#ibcon#about to read 6, iclass 34, count 0 2006.173.12:25:29.91#ibcon#read 6, iclass 34, count 0 2006.173.12:25:29.91#ibcon#end of sib2, iclass 34, count 0 2006.173.12:25:29.91#ibcon#*mode == 0, iclass 34, count 0 2006.173.12:25:29.91#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.12:25:29.91#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.12:25:29.91#ibcon#*before write, iclass 34, count 0 2006.173.12:25:29.91#ibcon#enter sib2, iclass 34, count 0 2006.173.12:25:29.91#ibcon#flushed, iclass 34, count 0 2006.173.12:25:29.91#ibcon#about to write, iclass 34, count 0 2006.173.12:25:29.91#ibcon#wrote, iclass 34, count 0 2006.173.12:25:29.91#ibcon#about to read 3, iclass 34, count 0 2006.173.12:25:29.95#ibcon#read 3, iclass 34, count 0 2006.173.12:25:29.95#ibcon#about to read 4, iclass 34, count 0 2006.173.12:25:29.95#ibcon#read 4, iclass 34, count 0 2006.173.12:25:29.95#ibcon#about to read 5, iclass 34, count 0 2006.173.12:25:29.95#ibcon#read 5, iclass 34, count 0 2006.173.12:25:29.95#ibcon#about to read 6, iclass 34, count 0 2006.173.12:25:29.95#ibcon#read 6, iclass 34, count 0 2006.173.12:25:29.95#ibcon#end of sib2, iclass 34, count 0 2006.173.12:25:29.95#ibcon#*after write, iclass 34, count 0 2006.173.12:25:29.95#ibcon#*before return 0, iclass 34, count 0 2006.173.12:25:29.95#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.12:25:29.95#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.12:25:29.95#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.12:25:29.95#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.12:25:29.95$vck44/va=3,5 2006.173.12:25:29.95#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.12:25:29.95#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.12:25:29.95#ibcon#ireg 11 cls_cnt 2 2006.173.12:25:29.95#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.12:25:30.01#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.12:25:30.01#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.12:25:30.01#ibcon#enter wrdev, iclass 36, count 2 2006.173.12:25:30.01#ibcon#first serial, iclass 36, count 2 2006.173.12:25:30.01#ibcon#enter sib2, iclass 36, count 2 2006.173.12:25:30.01#ibcon#flushed, iclass 36, count 2 2006.173.12:25:30.01#ibcon#about to write, iclass 36, count 2 2006.173.12:25:30.01#ibcon#wrote, iclass 36, count 2 2006.173.12:25:30.01#ibcon#about to read 3, iclass 36, count 2 2006.173.12:25:30.03#ibcon#read 3, iclass 36, count 2 2006.173.12:25:30.03#ibcon#about to read 4, iclass 36, count 2 2006.173.12:25:30.03#ibcon#read 4, iclass 36, count 2 2006.173.12:25:30.03#ibcon#about to read 5, iclass 36, count 2 2006.173.12:25:30.03#ibcon#read 5, iclass 36, count 2 2006.173.12:25:30.03#ibcon#about to read 6, iclass 36, count 2 2006.173.12:25:30.03#ibcon#read 6, iclass 36, count 2 2006.173.12:25:30.03#ibcon#end of sib2, iclass 36, count 2 2006.173.12:25:30.03#ibcon#*mode == 0, iclass 36, count 2 2006.173.12:25:30.03#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.12:25:30.03#ibcon#[25=AT03-05\r\n] 2006.173.12:25:30.03#ibcon#*before write, iclass 36, count 2 2006.173.12:25:30.03#ibcon#enter sib2, iclass 36, count 2 2006.173.12:25:30.03#ibcon#flushed, iclass 36, count 2 2006.173.12:25:30.03#ibcon#about to write, iclass 36, count 2 2006.173.12:25:30.03#ibcon#wrote, iclass 36, count 2 2006.173.12:25:30.03#ibcon#about to read 3, iclass 36, count 2 2006.173.12:25:30.06#ibcon#read 3, iclass 36, count 2 2006.173.12:25:30.06#ibcon#about to read 4, iclass 36, count 2 2006.173.12:25:30.06#ibcon#read 4, iclass 36, count 2 2006.173.12:25:30.06#ibcon#about to read 5, iclass 36, count 2 2006.173.12:25:30.06#ibcon#read 5, iclass 36, count 2 2006.173.12:25:30.06#ibcon#about to read 6, iclass 36, count 2 2006.173.12:25:30.06#ibcon#read 6, iclass 36, count 2 2006.173.12:25:30.06#ibcon#end of sib2, iclass 36, count 2 2006.173.12:25:30.06#ibcon#*after write, iclass 36, count 2 2006.173.12:25:30.06#ibcon#*before return 0, iclass 36, count 2 2006.173.12:25:30.06#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.12:25:30.06#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.12:25:30.06#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.12:25:30.06#ibcon#ireg 7 cls_cnt 0 2006.173.12:25:30.06#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.12:25:30.18#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.12:25:30.18#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.12:25:30.18#ibcon#enter wrdev, iclass 36, count 0 2006.173.12:25:30.18#ibcon#first serial, iclass 36, count 0 2006.173.12:25:30.18#ibcon#enter sib2, iclass 36, count 0 2006.173.12:25:30.18#ibcon#flushed, iclass 36, count 0 2006.173.12:25:30.18#ibcon#about to write, iclass 36, count 0 2006.173.12:25:30.18#ibcon#wrote, iclass 36, count 0 2006.173.12:25:30.18#ibcon#about to read 3, iclass 36, count 0 2006.173.12:25:30.20#ibcon#read 3, iclass 36, count 0 2006.173.12:25:30.20#ibcon#about to read 4, iclass 36, count 0 2006.173.12:25:30.20#ibcon#read 4, iclass 36, count 0 2006.173.12:25:30.20#ibcon#about to read 5, iclass 36, count 0 2006.173.12:25:30.20#ibcon#read 5, iclass 36, count 0 2006.173.12:25:30.20#ibcon#about to read 6, iclass 36, count 0 2006.173.12:25:30.20#ibcon#read 6, iclass 36, count 0 2006.173.12:25:30.20#ibcon#end of sib2, iclass 36, count 0 2006.173.12:25:30.20#ibcon#*mode == 0, iclass 36, count 0 2006.173.12:25:30.20#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.12:25:30.20#ibcon#[25=USB\r\n] 2006.173.12:25:30.20#ibcon#*before write, iclass 36, count 0 2006.173.12:25:30.20#ibcon#enter sib2, iclass 36, count 0 2006.173.12:25:30.20#ibcon#flushed, iclass 36, count 0 2006.173.12:25:30.20#ibcon#about to write, iclass 36, count 0 2006.173.12:25:30.20#ibcon#wrote, iclass 36, count 0 2006.173.12:25:30.20#ibcon#about to read 3, iclass 36, count 0 2006.173.12:25:30.23#ibcon#read 3, iclass 36, count 0 2006.173.12:25:30.23#ibcon#about to read 4, iclass 36, count 0 2006.173.12:25:30.23#ibcon#read 4, iclass 36, count 0 2006.173.12:25:30.23#ibcon#about to read 5, iclass 36, count 0 2006.173.12:25:30.23#ibcon#read 5, iclass 36, count 0 2006.173.12:25:30.23#ibcon#about to read 6, iclass 36, count 0 2006.173.12:25:30.23#ibcon#read 6, iclass 36, count 0 2006.173.12:25:30.23#ibcon#end of sib2, iclass 36, count 0 2006.173.12:25:30.23#ibcon#*after write, iclass 36, count 0 2006.173.12:25:30.23#ibcon#*before return 0, iclass 36, count 0 2006.173.12:25:30.23#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.12:25:30.23#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.12:25:30.23#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.12:25:30.23#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.12:25:30.23$vck44/valo=4,624.99 2006.173.12:25:30.23#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.12:25:30.23#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.12:25:30.23#ibcon#ireg 17 cls_cnt 0 2006.173.12:25:30.23#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.12:25:30.23#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.12:25:30.23#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.12:25:30.23#ibcon#enter wrdev, iclass 38, count 0 2006.173.12:25:30.23#ibcon#first serial, iclass 38, count 0 2006.173.12:25:30.23#ibcon#enter sib2, iclass 38, count 0 2006.173.12:25:30.23#ibcon#flushed, iclass 38, count 0 2006.173.12:25:30.23#ibcon#about to write, iclass 38, count 0 2006.173.12:25:30.23#ibcon#wrote, iclass 38, count 0 2006.173.12:25:30.23#ibcon#about to read 3, iclass 38, count 0 2006.173.12:25:30.25#ibcon#read 3, iclass 38, count 0 2006.173.12:25:30.25#ibcon#about to read 4, iclass 38, count 0 2006.173.12:25:30.25#ibcon#read 4, iclass 38, count 0 2006.173.12:25:30.25#ibcon#about to read 5, iclass 38, count 0 2006.173.12:25:30.25#ibcon#read 5, iclass 38, count 0 2006.173.12:25:30.25#ibcon#about to read 6, iclass 38, count 0 2006.173.12:25:30.25#ibcon#read 6, iclass 38, count 0 2006.173.12:25:30.25#ibcon#end of sib2, iclass 38, count 0 2006.173.12:25:30.25#ibcon#*mode == 0, iclass 38, count 0 2006.173.12:25:30.25#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.12:25:30.25#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.12:25:30.25#ibcon#*before write, iclass 38, count 0 2006.173.12:25:30.25#ibcon#enter sib2, iclass 38, count 0 2006.173.12:25:30.25#ibcon#flushed, iclass 38, count 0 2006.173.12:25:30.25#ibcon#about to write, iclass 38, count 0 2006.173.12:25:30.25#ibcon#wrote, iclass 38, count 0 2006.173.12:25:30.25#ibcon#about to read 3, iclass 38, count 0 2006.173.12:25:30.29#ibcon#read 3, iclass 38, count 0 2006.173.12:25:30.29#ibcon#about to read 4, iclass 38, count 0 2006.173.12:25:30.29#ibcon#read 4, iclass 38, count 0 2006.173.12:25:30.29#ibcon#about to read 5, iclass 38, count 0 2006.173.12:25:30.29#ibcon#read 5, iclass 38, count 0 2006.173.12:25:30.29#ibcon#about to read 6, iclass 38, count 0 2006.173.12:25:30.29#ibcon#read 6, iclass 38, count 0 2006.173.12:25:30.29#ibcon#end of sib2, iclass 38, count 0 2006.173.12:25:30.29#ibcon#*after write, iclass 38, count 0 2006.173.12:25:30.29#ibcon#*before return 0, iclass 38, count 0 2006.173.12:25:30.29#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.12:25:30.29#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.12:25:30.29#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.12:25:30.29#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.12:25:30.29$vck44/va=4,6 2006.173.12:25:30.29#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.12:25:30.29#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.12:25:30.29#ibcon#ireg 11 cls_cnt 2 2006.173.12:25:30.29#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.12:25:30.35#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.12:25:30.35#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.12:25:30.35#ibcon#enter wrdev, iclass 40, count 2 2006.173.12:25:30.35#ibcon#first serial, iclass 40, count 2 2006.173.12:25:30.35#ibcon#enter sib2, iclass 40, count 2 2006.173.12:25:30.35#ibcon#flushed, iclass 40, count 2 2006.173.12:25:30.35#ibcon#about to write, iclass 40, count 2 2006.173.12:25:30.35#ibcon#wrote, iclass 40, count 2 2006.173.12:25:30.35#ibcon#about to read 3, iclass 40, count 2 2006.173.12:25:30.37#ibcon#read 3, iclass 40, count 2 2006.173.12:25:30.37#ibcon#about to read 4, iclass 40, count 2 2006.173.12:25:30.37#ibcon#read 4, iclass 40, count 2 2006.173.12:25:30.37#ibcon#about to read 5, iclass 40, count 2 2006.173.12:25:30.37#ibcon#read 5, iclass 40, count 2 2006.173.12:25:30.37#ibcon#about to read 6, iclass 40, count 2 2006.173.12:25:30.37#ibcon#read 6, iclass 40, count 2 2006.173.12:25:30.37#ibcon#end of sib2, iclass 40, count 2 2006.173.12:25:30.37#ibcon#*mode == 0, iclass 40, count 2 2006.173.12:25:30.37#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.12:25:30.37#ibcon#[25=AT04-06\r\n] 2006.173.12:25:30.37#ibcon#*before write, iclass 40, count 2 2006.173.12:25:30.37#ibcon#enter sib2, iclass 40, count 2 2006.173.12:25:30.37#ibcon#flushed, iclass 40, count 2 2006.173.12:25:30.37#ibcon#about to write, iclass 40, count 2 2006.173.12:25:30.37#ibcon#wrote, iclass 40, count 2 2006.173.12:25:30.37#ibcon#about to read 3, iclass 40, count 2 2006.173.12:25:30.40#ibcon#read 3, iclass 40, count 2 2006.173.12:25:30.40#ibcon#about to read 4, iclass 40, count 2 2006.173.12:25:30.40#ibcon#read 4, iclass 40, count 2 2006.173.12:25:30.40#ibcon#about to read 5, iclass 40, count 2 2006.173.12:25:30.40#ibcon#read 5, iclass 40, count 2 2006.173.12:25:30.40#ibcon#about to read 6, iclass 40, count 2 2006.173.12:25:30.40#ibcon#read 6, iclass 40, count 2 2006.173.12:25:30.40#ibcon#end of sib2, iclass 40, count 2 2006.173.12:25:30.40#ibcon#*after write, iclass 40, count 2 2006.173.12:25:30.40#ibcon#*before return 0, iclass 40, count 2 2006.173.12:25:30.40#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.12:25:30.40#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.12:25:30.40#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.12:25:30.40#ibcon#ireg 7 cls_cnt 0 2006.173.12:25:30.40#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.12:25:30.52#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.12:25:30.52#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.12:25:30.52#ibcon#enter wrdev, iclass 40, count 0 2006.173.12:25:30.52#ibcon#first serial, iclass 40, count 0 2006.173.12:25:30.52#ibcon#enter sib2, iclass 40, count 0 2006.173.12:25:30.52#ibcon#flushed, iclass 40, count 0 2006.173.12:25:30.52#ibcon#about to write, iclass 40, count 0 2006.173.12:25:30.52#ibcon#wrote, iclass 40, count 0 2006.173.12:25:30.52#ibcon#about to read 3, iclass 40, count 0 2006.173.12:25:30.54#ibcon#read 3, iclass 40, count 0 2006.173.12:25:30.54#ibcon#about to read 4, iclass 40, count 0 2006.173.12:25:30.54#ibcon#read 4, iclass 40, count 0 2006.173.12:25:30.54#ibcon#about to read 5, iclass 40, count 0 2006.173.12:25:30.54#ibcon#read 5, iclass 40, count 0 2006.173.12:25:30.54#ibcon#about to read 6, iclass 40, count 0 2006.173.12:25:30.54#ibcon#read 6, iclass 40, count 0 2006.173.12:25:30.54#ibcon#end of sib2, iclass 40, count 0 2006.173.12:25:30.54#ibcon#*mode == 0, iclass 40, count 0 2006.173.12:25:30.54#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.12:25:30.54#ibcon#[25=USB\r\n] 2006.173.12:25:30.54#ibcon#*before write, iclass 40, count 0 2006.173.12:25:30.54#ibcon#enter sib2, iclass 40, count 0 2006.173.12:25:30.54#ibcon#flushed, iclass 40, count 0 2006.173.12:25:30.54#ibcon#about to write, iclass 40, count 0 2006.173.12:25:30.54#ibcon#wrote, iclass 40, count 0 2006.173.12:25:30.54#ibcon#about to read 3, iclass 40, count 0 2006.173.12:25:30.57#ibcon#read 3, iclass 40, count 0 2006.173.12:25:30.57#ibcon#about to read 4, iclass 40, count 0 2006.173.12:25:30.57#ibcon#read 4, iclass 40, count 0 2006.173.12:25:30.57#ibcon#about to read 5, iclass 40, count 0 2006.173.12:25:30.57#ibcon#read 5, iclass 40, count 0 2006.173.12:25:30.57#ibcon#about to read 6, iclass 40, count 0 2006.173.12:25:30.57#ibcon#read 6, iclass 40, count 0 2006.173.12:25:30.57#ibcon#end of sib2, iclass 40, count 0 2006.173.12:25:30.57#ibcon#*after write, iclass 40, count 0 2006.173.12:25:30.57#ibcon#*before return 0, iclass 40, count 0 2006.173.12:25:30.57#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.12:25:30.57#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.12:25:30.57#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.12:25:30.57#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.12:25:30.57$vck44/valo=5,734.99 2006.173.12:25:30.57#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.12:25:30.57#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.12:25:30.57#ibcon#ireg 17 cls_cnt 0 2006.173.12:25:30.57#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.12:25:30.57#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.12:25:30.57#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.12:25:30.57#ibcon#enter wrdev, iclass 4, count 0 2006.173.12:25:30.57#ibcon#first serial, iclass 4, count 0 2006.173.12:25:30.57#ibcon#enter sib2, iclass 4, count 0 2006.173.12:25:30.57#ibcon#flushed, iclass 4, count 0 2006.173.12:25:30.57#ibcon#about to write, iclass 4, count 0 2006.173.12:25:30.57#ibcon#wrote, iclass 4, count 0 2006.173.12:25:30.57#ibcon#about to read 3, iclass 4, count 0 2006.173.12:25:30.59#ibcon#read 3, iclass 4, count 0 2006.173.12:25:30.59#ibcon#about to read 4, iclass 4, count 0 2006.173.12:25:30.59#ibcon#read 4, iclass 4, count 0 2006.173.12:25:30.59#ibcon#about to read 5, iclass 4, count 0 2006.173.12:25:30.59#ibcon#read 5, iclass 4, count 0 2006.173.12:25:30.59#ibcon#about to read 6, iclass 4, count 0 2006.173.12:25:30.59#ibcon#read 6, iclass 4, count 0 2006.173.12:25:30.59#ibcon#end of sib2, iclass 4, count 0 2006.173.12:25:30.59#ibcon#*mode == 0, iclass 4, count 0 2006.173.12:25:30.59#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.12:25:30.59#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.12:25:30.59#ibcon#*before write, iclass 4, count 0 2006.173.12:25:30.59#ibcon#enter sib2, iclass 4, count 0 2006.173.12:25:30.59#ibcon#flushed, iclass 4, count 0 2006.173.12:25:30.59#ibcon#about to write, iclass 4, count 0 2006.173.12:25:30.59#ibcon#wrote, iclass 4, count 0 2006.173.12:25:30.59#ibcon#about to read 3, iclass 4, count 0 2006.173.12:25:30.63#ibcon#read 3, iclass 4, count 0 2006.173.12:25:30.63#ibcon#about to read 4, iclass 4, count 0 2006.173.12:25:30.63#ibcon#read 4, iclass 4, count 0 2006.173.12:25:30.63#ibcon#about to read 5, iclass 4, count 0 2006.173.12:25:30.63#ibcon#read 5, iclass 4, count 0 2006.173.12:25:30.63#ibcon#about to read 6, iclass 4, count 0 2006.173.12:25:30.63#ibcon#read 6, iclass 4, count 0 2006.173.12:25:30.63#ibcon#end of sib2, iclass 4, count 0 2006.173.12:25:30.63#ibcon#*after write, iclass 4, count 0 2006.173.12:25:30.63#ibcon#*before return 0, iclass 4, count 0 2006.173.12:25:30.63#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.12:25:30.63#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.12:25:30.63#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.12:25:30.63#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.12:25:30.63$vck44/va=5,4 2006.173.12:25:30.63#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.12:25:30.63#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.12:25:30.63#ibcon#ireg 11 cls_cnt 2 2006.173.12:25:30.63#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.12:25:30.69#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.12:25:30.69#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.12:25:30.69#ibcon#enter wrdev, iclass 6, count 2 2006.173.12:25:30.69#ibcon#first serial, iclass 6, count 2 2006.173.12:25:30.69#ibcon#enter sib2, iclass 6, count 2 2006.173.12:25:30.69#ibcon#flushed, iclass 6, count 2 2006.173.12:25:30.69#ibcon#about to write, iclass 6, count 2 2006.173.12:25:30.69#ibcon#wrote, iclass 6, count 2 2006.173.12:25:30.69#ibcon#about to read 3, iclass 6, count 2 2006.173.12:25:30.71#ibcon#read 3, iclass 6, count 2 2006.173.12:25:30.71#ibcon#about to read 4, iclass 6, count 2 2006.173.12:25:30.71#ibcon#read 4, iclass 6, count 2 2006.173.12:25:30.71#ibcon#about to read 5, iclass 6, count 2 2006.173.12:25:30.71#ibcon#read 5, iclass 6, count 2 2006.173.12:25:30.71#ibcon#about to read 6, iclass 6, count 2 2006.173.12:25:30.71#ibcon#read 6, iclass 6, count 2 2006.173.12:25:30.71#ibcon#end of sib2, iclass 6, count 2 2006.173.12:25:30.71#ibcon#*mode == 0, iclass 6, count 2 2006.173.12:25:30.71#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.12:25:30.71#ibcon#[25=AT05-04\r\n] 2006.173.12:25:30.71#ibcon#*before write, iclass 6, count 2 2006.173.12:25:30.71#ibcon#enter sib2, iclass 6, count 2 2006.173.12:25:30.71#ibcon#flushed, iclass 6, count 2 2006.173.12:25:30.71#ibcon#about to write, iclass 6, count 2 2006.173.12:25:30.71#ibcon#wrote, iclass 6, count 2 2006.173.12:25:30.71#ibcon#about to read 3, iclass 6, count 2 2006.173.12:25:30.74#ibcon#read 3, iclass 6, count 2 2006.173.12:25:30.74#ibcon#about to read 4, iclass 6, count 2 2006.173.12:25:30.74#ibcon#read 4, iclass 6, count 2 2006.173.12:25:30.74#ibcon#about to read 5, iclass 6, count 2 2006.173.12:25:30.74#ibcon#read 5, iclass 6, count 2 2006.173.12:25:30.74#ibcon#about to read 6, iclass 6, count 2 2006.173.12:25:30.74#ibcon#read 6, iclass 6, count 2 2006.173.12:25:30.74#ibcon#end of sib2, iclass 6, count 2 2006.173.12:25:30.74#ibcon#*after write, iclass 6, count 2 2006.173.12:25:30.74#ibcon#*before return 0, iclass 6, count 2 2006.173.12:25:30.74#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.12:25:30.74#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.12:25:30.74#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.12:25:30.74#ibcon#ireg 7 cls_cnt 0 2006.173.12:25:30.74#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.12:25:30.86#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.12:25:30.86#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.12:25:30.86#ibcon#enter wrdev, iclass 6, count 0 2006.173.12:25:30.86#ibcon#first serial, iclass 6, count 0 2006.173.12:25:30.86#ibcon#enter sib2, iclass 6, count 0 2006.173.12:25:30.86#ibcon#flushed, iclass 6, count 0 2006.173.12:25:30.86#ibcon#about to write, iclass 6, count 0 2006.173.12:25:30.86#ibcon#wrote, iclass 6, count 0 2006.173.12:25:30.86#ibcon#about to read 3, iclass 6, count 0 2006.173.12:25:30.88#ibcon#read 3, iclass 6, count 0 2006.173.12:25:30.88#ibcon#about to read 4, iclass 6, count 0 2006.173.12:25:30.88#ibcon#read 4, iclass 6, count 0 2006.173.12:25:30.88#ibcon#about to read 5, iclass 6, count 0 2006.173.12:25:30.88#ibcon#read 5, iclass 6, count 0 2006.173.12:25:30.88#ibcon#about to read 6, iclass 6, count 0 2006.173.12:25:30.88#ibcon#read 6, iclass 6, count 0 2006.173.12:25:30.88#ibcon#end of sib2, iclass 6, count 0 2006.173.12:25:30.88#ibcon#*mode == 0, iclass 6, count 0 2006.173.12:25:30.88#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.12:25:30.88#ibcon#[25=USB\r\n] 2006.173.12:25:30.88#ibcon#*before write, iclass 6, count 0 2006.173.12:25:30.88#ibcon#enter sib2, iclass 6, count 0 2006.173.12:25:30.88#ibcon#flushed, iclass 6, count 0 2006.173.12:25:30.88#ibcon#about to write, iclass 6, count 0 2006.173.12:25:30.88#ibcon#wrote, iclass 6, count 0 2006.173.12:25:30.88#ibcon#about to read 3, iclass 6, count 0 2006.173.12:25:30.91#ibcon#read 3, iclass 6, count 0 2006.173.12:25:30.91#ibcon#about to read 4, iclass 6, count 0 2006.173.12:25:30.91#ibcon#read 4, iclass 6, count 0 2006.173.12:25:30.91#ibcon#about to read 5, iclass 6, count 0 2006.173.12:25:30.91#ibcon#read 5, iclass 6, count 0 2006.173.12:25:30.91#ibcon#about to read 6, iclass 6, count 0 2006.173.12:25:30.91#ibcon#read 6, iclass 6, count 0 2006.173.12:25:30.91#ibcon#end of sib2, iclass 6, count 0 2006.173.12:25:30.91#ibcon#*after write, iclass 6, count 0 2006.173.12:25:30.91#ibcon#*before return 0, iclass 6, count 0 2006.173.12:25:30.91#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.12:25:30.91#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.12:25:30.91#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.12:25:30.91#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.12:25:30.91$vck44/valo=6,814.99 2006.173.12:25:30.91#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.12:25:30.91#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.12:25:30.91#ibcon#ireg 17 cls_cnt 0 2006.173.12:25:30.91#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.12:25:30.91#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.12:25:30.91#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.12:25:30.91#ibcon#enter wrdev, iclass 10, count 0 2006.173.12:25:30.91#ibcon#first serial, iclass 10, count 0 2006.173.12:25:30.91#ibcon#enter sib2, iclass 10, count 0 2006.173.12:25:30.91#ibcon#flushed, iclass 10, count 0 2006.173.12:25:30.91#ibcon#about to write, iclass 10, count 0 2006.173.12:25:30.91#ibcon#wrote, iclass 10, count 0 2006.173.12:25:30.91#ibcon#about to read 3, iclass 10, count 0 2006.173.12:25:30.93#ibcon#read 3, iclass 10, count 0 2006.173.12:25:30.93#ibcon#about to read 4, iclass 10, count 0 2006.173.12:25:30.93#ibcon#read 4, iclass 10, count 0 2006.173.12:25:30.93#ibcon#about to read 5, iclass 10, count 0 2006.173.12:25:30.93#ibcon#read 5, iclass 10, count 0 2006.173.12:25:30.93#ibcon#about to read 6, iclass 10, count 0 2006.173.12:25:30.93#ibcon#read 6, iclass 10, count 0 2006.173.12:25:30.93#ibcon#end of sib2, iclass 10, count 0 2006.173.12:25:30.93#ibcon#*mode == 0, iclass 10, count 0 2006.173.12:25:30.93#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.12:25:30.93#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.12:25:30.93#ibcon#*before write, iclass 10, count 0 2006.173.12:25:30.93#ibcon#enter sib2, iclass 10, count 0 2006.173.12:25:30.93#ibcon#flushed, iclass 10, count 0 2006.173.12:25:30.93#ibcon#about to write, iclass 10, count 0 2006.173.12:25:30.93#ibcon#wrote, iclass 10, count 0 2006.173.12:25:30.93#ibcon#about to read 3, iclass 10, count 0 2006.173.12:25:30.97#ibcon#read 3, iclass 10, count 0 2006.173.12:25:30.97#ibcon#about to read 4, iclass 10, count 0 2006.173.12:25:30.97#ibcon#read 4, iclass 10, count 0 2006.173.12:25:30.97#ibcon#about to read 5, iclass 10, count 0 2006.173.12:25:30.97#ibcon#read 5, iclass 10, count 0 2006.173.12:25:30.97#ibcon#about to read 6, iclass 10, count 0 2006.173.12:25:30.97#ibcon#read 6, iclass 10, count 0 2006.173.12:25:30.97#ibcon#end of sib2, iclass 10, count 0 2006.173.12:25:30.97#ibcon#*after write, iclass 10, count 0 2006.173.12:25:30.97#ibcon#*before return 0, iclass 10, count 0 2006.173.12:25:30.97#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.12:25:30.97#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.12:25:30.97#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.12:25:30.97#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.12:25:30.97$vck44/va=6,3 2006.173.12:25:30.97#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.12:25:30.97#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.12:25:30.97#ibcon#ireg 11 cls_cnt 2 2006.173.12:25:30.97#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.12:25:31.03#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.12:25:31.03#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.12:25:31.03#ibcon#enter wrdev, iclass 12, count 2 2006.173.12:25:31.03#ibcon#first serial, iclass 12, count 2 2006.173.12:25:31.03#ibcon#enter sib2, iclass 12, count 2 2006.173.12:25:31.03#ibcon#flushed, iclass 12, count 2 2006.173.12:25:31.03#ibcon#about to write, iclass 12, count 2 2006.173.12:25:31.03#ibcon#wrote, iclass 12, count 2 2006.173.12:25:31.03#ibcon#about to read 3, iclass 12, count 2 2006.173.12:25:31.05#ibcon#read 3, iclass 12, count 2 2006.173.12:25:31.05#ibcon#about to read 4, iclass 12, count 2 2006.173.12:25:31.05#ibcon#read 4, iclass 12, count 2 2006.173.12:25:31.05#ibcon#about to read 5, iclass 12, count 2 2006.173.12:25:31.05#ibcon#read 5, iclass 12, count 2 2006.173.12:25:31.05#ibcon#about to read 6, iclass 12, count 2 2006.173.12:25:31.05#ibcon#read 6, iclass 12, count 2 2006.173.12:25:31.05#ibcon#end of sib2, iclass 12, count 2 2006.173.12:25:31.05#ibcon#*mode == 0, iclass 12, count 2 2006.173.12:25:31.05#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.12:25:31.05#ibcon#[25=AT06-03\r\n] 2006.173.12:25:31.05#ibcon#*before write, iclass 12, count 2 2006.173.12:25:31.05#ibcon#enter sib2, iclass 12, count 2 2006.173.12:25:31.05#ibcon#flushed, iclass 12, count 2 2006.173.12:25:31.05#ibcon#about to write, iclass 12, count 2 2006.173.12:25:31.05#ibcon#wrote, iclass 12, count 2 2006.173.12:25:31.05#ibcon#about to read 3, iclass 12, count 2 2006.173.12:25:31.08#ibcon#read 3, iclass 12, count 2 2006.173.12:25:31.08#ibcon#about to read 4, iclass 12, count 2 2006.173.12:25:31.08#ibcon#read 4, iclass 12, count 2 2006.173.12:25:31.08#ibcon#about to read 5, iclass 12, count 2 2006.173.12:25:31.08#ibcon#read 5, iclass 12, count 2 2006.173.12:25:31.08#ibcon#about to read 6, iclass 12, count 2 2006.173.12:25:31.08#ibcon#read 6, iclass 12, count 2 2006.173.12:25:31.08#ibcon#end of sib2, iclass 12, count 2 2006.173.12:25:31.08#ibcon#*after write, iclass 12, count 2 2006.173.12:25:31.08#ibcon#*before return 0, iclass 12, count 2 2006.173.12:25:31.08#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.12:25:31.08#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.12:25:31.08#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.12:25:31.08#ibcon#ireg 7 cls_cnt 0 2006.173.12:25:31.08#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.12:25:31.20#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.12:25:31.20#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.12:25:31.20#ibcon#enter wrdev, iclass 12, count 0 2006.173.12:25:31.20#ibcon#first serial, iclass 12, count 0 2006.173.12:25:31.20#ibcon#enter sib2, iclass 12, count 0 2006.173.12:25:31.20#ibcon#flushed, iclass 12, count 0 2006.173.12:25:31.20#ibcon#about to write, iclass 12, count 0 2006.173.12:25:31.20#ibcon#wrote, iclass 12, count 0 2006.173.12:25:31.20#ibcon#about to read 3, iclass 12, count 0 2006.173.12:25:31.22#ibcon#read 3, iclass 12, count 0 2006.173.12:25:31.22#ibcon#about to read 4, iclass 12, count 0 2006.173.12:25:31.22#ibcon#read 4, iclass 12, count 0 2006.173.12:25:31.22#ibcon#about to read 5, iclass 12, count 0 2006.173.12:25:31.22#ibcon#read 5, iclass 12, count 0 2006.173.12:25:31.22#ibcon#about to read 6, iclass 12, count 0 2006.173.12:25:31.22#ibcon#read 6, iclass 12, count 0 2006.173.12:25:31.22#ibcon#end of sib2, iclass 12, count 0 2006.173.12:25:31.22#ibcon#*mode == 0, iclass 12, count 0 2006.173.12:25:31.22#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.12:25:31.22#ibcon#[25=USB\r\n] 2006.173.12:25:31.22#ibcon#*before write, iclass 12, count 0 2006.173.12:25:31.22#ibcon#enter sib2, iclass 12, count 0 2006.173.12:25:31.22#ibcon#flushed, iclass 12, count 0 2006.173.12:25:31.22#ibcon#about to write, iclass 12, count 0 2006.173.12:25:31.22#ibcon#wrote, iclass 12, count 0 2006.173.12:25:31.22#ibcon#about to read 3, iclass 12, count 0 2006.173.12:25:31.25#ibcon#read 3, iclass 12, count 0 2006.173.12:25:31.25#ibcon#about to read 4, iclass 12, count 0 2006.173.12:25:31.25#ibcon#read 4, iclass 12, count 0 2006.173.12:25:31.25#ibcon#about to read 5, iclass 12, count 0 2006.173.12:25:31.25#ibcon#read 5, iclass 12, count 0 2006.173.12:25:31.25#ibcon#about to read 6, iclass 12, count 0 2006.173.12:25:31.25#ibcon#read 6, iclass 12, count 0 2006.173.12:25:31.25#ibcon#end of sib2, iclass 12, count 0 2006.173.12:25:31.25#ibcon#*after write, iclass 12, count 0 2006.173.12:25:31.25#ibcon#*before return 0, iclass 12, count 0 2006.173.12:25:31.25#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.12:25:31.25#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.12:25:31.25#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.12:25:31.25#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.12:25:31.25$vck44/valo=7,864.99 2006.173.12:25:31.25#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.12:25:31.25#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.12:25:31.25#ibcon#ireg 17 cls_cnt 0 2006.173.12:25:31.25#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.12:25:31.25#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.12:25:31.25#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.12:25:31.25#ibcon#enter wrdev, iclass 14, count 0 2006.173.12:25:31.25#ibcon#first serial, iclass 14, count 0 2006.173.12:25:31.25#ibcon#enter sib2, iclass 14, count 0 2006.173.12:25:31.25#ibcon#flushed, iclass 14, count 0 2006.173.12:25:31.25#ibcon#about to write, iclass 14, count 0 2006.173.12:25:31.25#ibcon#wrote, iclass 14, count 0 2006.173.12:25:31.25#ibcon#about to read 3, iclass 14, count 0 2006.173.12:25:31.27#ibcon#read 3, iclass 14, count 0 2006.173.12:25:31.27#ibcon#about to read 4, iclass 14, count 0 2006.173.12:25:31.27#ibcon#read 4, iclass 14, count 0 2006.173.12:25:31.27#ibcon#about to read 5, iclass 14, count 0 2006.173.12:25:31.27#ibcon#read 5, iclass 14, count 0 2006.173.12:25:31.27#ibcon#about to read 6, iclass 14, count 0 2006.173.12:25:31.27#ibcon#read 6, iclass 14, count 0 2006.173.12:25:31.27#ibcon#end of sib2, iclass 14, count 0 2006.173.12:25:31.27#ibcon#*mode == 0, iclass 14, count 0 2006.173.12:25:31.27#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.12:25:31.27#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.12:25:31.27#ibcon#*before write, iclass 14, count 0 2006.173.12:25:31.27#ibcon#enter sib2, iclass 14, count 0 2006.173.12:25:31.27#ibcon#flushed, iclass 14, count 0 2006.173.12:25:31.27#ibcon#about to write, iclass 14, count 0 2006.173.12:25:31.27#ibcon#wrote, iclass 14, count 0 2006.173.12:25:31.27#ibcon#about to read 3, iclass 14, count 0 2006.173.12:25:31.31#ibcon#read 3, iclass 14, count 0 2006.173.12:25:31.31#ibcon#about to read 4, iclass 14, count 0 2006.173.12:25:31.31#ibcon#read 4, iclass 14, count 0 2006.173.12:25:31.31#ibcon#about to read 5, iclass 14, count 0 2006.173.12:25:31.31#ibcon#read 5, iclass 14, count 0 2006.173.12:25:31.31#ibcon#about to read 6, iclass 14, count 0 2006.173.12:25:31.31#ibcon#read 6, iclass 14, count 0 2006.173.12:25:31.31#ibcon#end of sib2, iclass 14, count 0 2006.173.12:25:31.31#ibcon#*after write, iclass 14, count 0 2006.173.12:25:31.31#ibcon#*before return 0, iclass 14, count 0 2006.173.12:25:31.31#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.12:25:31.31#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.12:25:31.31#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.12:25:31.31#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.12:25:31.31$vck44/va=7,4 2006.173.12:25:31.31#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.12:25:31.31#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.12:25:31.31#ibcon#ireg 11 cls_cnt 2 2006.173.12:25:31.31#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.12:25:31.37#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.12:25:31.37#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.12:25:31.37#ibcon#enter wrdev, iclass 16, count 2 2006.173.12:25:31.37#ibcon#first serial, iclass 16, count 2 2006.173.12:25:31.37#ibcon#enter sib2, iclass 16, count 2 2006.173.12:25:31.37#ibcon#flushed, iclass 16, count 2 2006.173.12:25:31.37#ibcon#about to write, iclass 16, count 2 2006.173.12:25:31.37#ibcon#wrote, iclass 16, count 2 2006.173.12:25:31.37#ibcon#about to read 3, iclass 16, count 2 2006.173.12:25:31.39#ibcon#read 3, iclass 16, count 2 2006.173.12:25:31.39#ibcon#about to read 4, iclass 16, count 2 2006.173.12:25:31.39#ibcon#read 4, iclass 16, count 2 2006.173.12:25:31.39#ibcon#about to read 5, iclass 16, count 2 2006.173.12:25:31.39#ibcon#read 5, iclass 16, count 2 2006.173.12:25:31.39#ibcon#about to read 6, iclass 16, count 2 2006.173.12:25:31.39#ibcon#read 6, iclass 16, count 2 2006.173.12:25:31.39#ibcon#end of sib2, iclass 16, count 2 2006.173.12:25:31.39#ibcon#*mode == 0, iclass 16, count 2 2006.173.12:25:31.39#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.12:25:31.39#ibcon#[25=AT07-04\r\n] 2006.173.12:25:31.39#ibcon#*before write, iclass 16, count 2 2006.173.12:25:31.39#ibcon#enter sib2, iclass 16, count 2 2006.173.12:25:31.39#ibcon#flushed, iclass 16, count 2 2006.173.12:25:31.39#ibcon#about to write, iclass 16, count 2 2006.173.12:25:31.39#ibcon#wrote, iclass 16, count 2 2006.173.12:25:31.39#ibcon#about to read 3, iclass 16, count 2 2006.173.12:25:31.42#ibcon#read 3, iclass 16, count 2 2006.173.12:25:31.42#ibcon#about to read 4, iclass 16, count 2 2006.173.12:25:31.42#ibcon#read 4, iclass 16, count 2 2006.173.12:25:31.42#ibcon#about to read 5, iclass 16, count 2 2006.173.12:25:31.42#ibcon#read 5, iclass 16, count 2 2006.173.12:25:31.42#ibcon#about to read 6, iclass 16, count 2 2006.173.12:25:31.42#ibcon#read 6, iclass 16, count 2 2006.173.12:25:31.42#ibcon#end of sib2, iclass 16, count 2 2006.173.12:25:31.42#ibcon#*after write, iclass 16, count 2 2006.173.12:25:31.42#ibcon#*before return 0, iclass 16, count 2 2006.173.12:25:31.42#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.12:25:31.42#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.12:25:31.42#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.12:25:31.42#ibcon#ireg 7 cls_cnt 0 2006.173.12:25:31.42#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.12:25:31.54#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.12:25:31.54#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.12:25:31.54#ibcon#enter wrdev, iclass 16, count 0 2006.173.12:25:31.54#ibcon#first serial, iclass 16, count 0 2006.173.12:25:31.54#ibcon#enter sib2, iclass 16, count 0 2006.173.12:25:31.54#ibcon#flushed, iclass 16, count 0 2006.173.12:25:31.54#ibcon#about to write, iclass 16, count 0 2006.173.12:25:31.54#ibcon#wrote, iclass 16, count 0 2006.173.12:25:31.54#ibcon#about to read 3, iclass 16, count 0 2006.173.12:25:31.56#ibcon#read 3, iclass 16, count 0 2006.173.12:25:31.56#ibcon#about to read 4, iclass 16, count 0 2006.173.12:25:31.56#ibcon#read 4, iclass 16, count 0 2006.173.12:25:31.56#ibcon#about to read 5, iclass 16, count 0 2006.173.12:25:31.56#ibcon#read 5, iclass 16, count 0 2006.173.12:25:31.56#ibcon#about to read 6, iclass 16, count 0 2006.173.12:25:31.56#ibcon#read 6, iclass 16, count 0 2006.173.12:25:31.56#ibcon#end of sib2, iclass 16, count 0 2006.173.12:25:31.56#ibcon#*mode == 0, iclass 16, count 0 2006.173.12:25:31.56#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.12:25:31.56#ibcon#[25=USB\r\n] 2006.173.12:25:31.56#ibcon#*before write, iclass 16, count 0 2006.173.12:25:31.56#ibcon#enter sib2, iclass 16, count 0 2006.173.12:25:31.56#ibcon#flushed, iclass 16, count 0 2006.173.12:25:31.56#ibcon#about to write, iclass 16, count 0 2006.173.12:25:31.56#ibcon#wrote, iclass 16, count 0 2006.173.12:25:31.56#ibcon#about to read 3, iclass 16, count 0 2006.173.12:25:31.59#ibcon#read 3, iclass 16, count 0 2006.173.12:25:31.59#ibcon#about to read 4, iclass 16, count 0 2006.173.12:25:31.59#ibcon#read 4, iclass 16, count 0 2006.173.12:25:31.59#ibcon#about to read 5, iclass 16, count 0 2006.173.12:25:31.59#ibcon#read 5, iclass 16, count 0 2006.173.12:25:31.59#ibcon#about to read 6, iclass 16, count 0 2006.173.12:25:31.59#ibcon#read 6, iclass 16, count 0 2006.173.12:25:31.59#ibcon#end of sib2, iclass 16, count 0 2006.173.12:25:31.59#ibcon#*after write, iclass 16, count 0 2006.173.12:25:31.59#ibcon#*before return 0, iclass 16, count 0 2006.173.12:25:31.59#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.12:25:31.59#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.12:25:31.59#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.12:25:31.59#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.12:25:31.59$vck44/valo=8,884.99 2006.173.12:25:31.59#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.12:25:31.59#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.12:25:31.59#ibcon#ireg 17 cls_cnt 0 2006.173.12:25:31.59#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.12:25:31.59#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.12:25:31.59#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.12:25:31.59#ibcon#enter wrdev, iclass 18, count 0 2006.173.12:25:31.59#ibcon#first serial, iclass 18, count 0 2006.173.12:25:31.59#ibcon#enter sib2, iclass 18, count 0 2006.173.12:25:31.59#ibcon#flushed, iclass 18, count 0 2006.173.12:25:31.59#ibcon#about to write, iclass 18, count 0 2006.173.12:25:31.59#ibcon#wrote, iclass 18, count 0 2006.173.12:25:31.59#ibcon#about to read 3, iclass 18, count 0 2006.173.12:25:31.61#ibcon#read 3, iclass 18, count 0 2006.173.12:25:31.61#ibcon#about to read 4, iclass 18, count 0 2006.173.12:25:31.61#ibcon#read 4, iclass 18, count 0 2006.173.12:25:31.61#ibcon#about to read 5, iclass 18, count 0 2006.173.12:25:31.61#ibcon#read 5, iclass 18, count 0 2006.173.12:25:31.61#ibcon#about to read 6, iclass 18, count 0 2006.173.12:25:31.61#ibcon#read 6, iclass 18, count 0 2006.173.12:25:31.61#ibcon#end of sib2, iclass 18, count 0 2006.173.12:25:31.61#ibcon#*mode == 0, iclass 18, count 0 2006.173.12:25:31.61#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.12:25:31.61#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.12:25:31.61#ibcon#*before write, iclass 18, count 0 2006.173.12:25:31.61#ibcon#enter sib2, iclass 18, count 0 2006.173.12:25:31.61#ibcon#flushed, iclass 18, count 0 2006.173.12:25:31.61#ibcon#about to write, iclass 18, count 0 2006.173.12:25:31.61#ibcon#wrote, iclass 18, count 0 2006.173.12:25:31.61#ibcon#about to read 3, iclass 18, count 0 2006.173.12:25:31.65#ibcon#read 3, iclass 18, count 0 2006.173.12:25:31.65#ibcon#about to read 4, iclass 18, count 0 2006.173.12:25:31.65#ibcon#read 4, iclass 18, count 0 2006.173.12:25:31.65#ibcon#about to read 5, iclass 18, count 0 2006.173.12:25:31.65#ibcon#read 5, iclass 18, count 0 2006.173.12:25:31.65#ibcon#about to read 6, iclass 18, count 0 2006.173.12:25:31.65#ibcon#read 6, iclass 18, count 0 2006.173.12:25:31.65#ibcon#end of sib2, iclass 18, count 0 2006.173.12:25:31.65#ibcon#*after write, iclass 18, count 0 2006.173.12:25:31.65#ibcon#*before return 0, iclass 18, count 0 2006.173.12:25:31.65#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.12:25:31.65#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.12:25:31.65#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.12:25:31.65#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.12:25:31.65$vck44/va=8,4 2006.173.12:25:31.65#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.12:25:31.65#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.12:25:31.65#ibcon#ireg 11 cls_cnt 2 2006.173.12:25:31.65#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.12:25:31.71#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.12:25:31.71#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.12:25:31.71#ibcon#enter wrdev, iclass 20, count 2 2006.173.12:25:31.71#ibcon#first serial, iclass 20, count 2 2006.173.12:25:31.71#ibcon#enter sib2, iclass 20, count 2 2006.173.12:25:31.71#ibcon#flushed, iclass 20, count 2 2006.173.12:25:31.71#ibcon#about to write, iclass 20, count 2 2006.173.12:25:31.71#ibcon#wrote, iclass 20, count 2 2006.173.12:25:31.71#ibcon#about to read 3, iclass 20, count 2 2006.173.12:25:31.73#ibcon#read 3, iclass 20, count 2 2006.173.12:25:31.73#ibcon#about to read 4, iclass 20, count 2 2006.173.12:25:31.73#ibcon#read 4, iclass 20, count 2 2006.173.12:25:31.73#ibcon#about to read 5, iclass 20, count 2 2006.173.12:25:31.73#ibcon#read 5, iclass 20, count 2 2006.173.12:25:31.73#ibcon#about to read 6, iclass 20, count 2 2006.173.12:25:31.73#ibcon#read 6, iclass 20, count 2 2006.173.12:25:31.73#ibcon#end of sib2, iclass 20, count 2 2006.173.12:25:31.73#ibcon#*mode == 0, iclass 20, count 2 2006.173.12:25:31.73#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.12:25:31.73#ibcon#[25=AT08-04\r\n] 2006.173.12:25:31.73#ibcon#*before write, iclass 20, count 2 2006.173.12:25:31.73#ibcon#enter sib2, iclass 20, count 2 2006.173.12:25:31.73#ibcon#flushed, iclass 20, count 2 2006.173.12:25:31.73#ibcon#about to write, iclass 20, count 2 2006.173.12:25:31.73#ibcon#wrote, iclass 20, count 2 2006.173.12:25:31.73#ibcon#about to read 3, iclass 20, count 2 2006.173.12:25:31.76#ibcon#read 3, iclass 20, count 2 2006.173.12:25:31.76#ibcon#about to read 4, iclass 20, count 2 2006.173.12:25:31.76#ibcon#read 4, iclass 20, count 2 2006.173.12:25:31.76#ibcon#about to read 5, iclass 20, count 2 2006.173.12:25:31.76#ibcon#read 5, iclass 20, count 2 2006.173.12:25:31.76#ibcon#about to read 6, iclass 20, count 2 2006.173.12:25:31.76#ibcon#read 6, iclass 20, count 2 2006.173.12:25:31.76#ibcon#end of sib2, iclass 20, count 2 2006.173.12:25:31.76#ibcon#*after write, iclass 20, count 2 2006.173.12:25:31.76#ibcon#*before return 0, iclass 20, count 2 2006.173.12:25:31.76#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.12:25:31.76#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.12:25:31.76#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.12:25:31.76#ibcon#ireg 7 cls_cnt 0 2006.173.12:25:31.76#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.12:25:31.88#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.12:25:31.88#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.12:25:31.88#ibcon#enter wrdev, iclass 20, count 0 2006.173.12:25:31.88#ibcon#first serial, iclass 20, count 0 2006.173.12:25:31.88#ibcon#enter sib2, iclass 20, count 0 2006.173.12:25:31.88#ibcon#flushed, iclass 20, count 0 2006.173.12:25:31.88#ibcon#about to write, iclass 20, count 0 2006.173.12:25:31.88#ibcon#wrote, iclass 20, count 0 2006.173.12:25:31.88#ibcon#about to read 3, iclass 20, count 0 2006.173.12:25:31.90#ibcon#read 3, iclass 20, count 0 2006.173.12:25:31.90#ibcon#about to read 4, iclass 20, count 0 2006.173.12:25:31.90#ibcon#read 4, iclass 20, count 0 2006.173.12:25:31.90#ibcon#about to read 5, iclass 20, count 0 2006.173.12:25:31.90#ibcon#read 5, iclass 20, count 0 2006.173.12:25:31.90#ibcon#about to read 6, iclass 20, count 0 2006.173.12:25:31.90#ibcon#read 6, iclass 20, count 0 2006.173.12:25:31.90#ibcon#end of sib2, iclass 20, count 0 2006.173.12:25:31.90#ibcon#*mode == 0, iclass 20, count 0 2006.173.12:25:31.90#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.12:25:31.90#ibcon#[25=USB\r\n] 2006.173.12:25:31.90#ibcon#*before write, iclass 20, count 0 2006.173.12:25:31.90#ibcon#enter sib2, iclass 20, count 0 2006.173.12:25:31.90#ibcon#flushed, iclass 20, count 0 2006.173.12:25:31.90#ibcon#about to write, iclass 20, count 0 2006.173.12:25:31.90#ibcon#wrote, iclass 20, count 0 2006.173.12:25:31.90#ibcon#about to read 3, iclass 20, count 0 2006.173.12:25:31.93#ibcon#read 3, iclass 20, count 0 2006.173.12:25:31.93#ibcon#about to read 4, iclass 20, count 0 2006.173.12:25:31.93#ibcon#read 4, iclass 20, count 0 2006.173.12:25:31.93#ibcon#about to read 5, iclass 20, count 0 2006.173.12:25:31.93#ibcon#read 5, iclass 20, count 0 2006.173.12:25:31.93#ibcon#about to read 6, iclass 20, count 0 2006.173.12:25:31.93#ibcon#read 6, iclass 20, count 0 2006.173.12:25:31.93#ibcon#end of sib2, iclass 20, count 0 2006.173.12:25:31.93#ibcon#*after write, iclass 20, count 0 2006.173.12:25:31.93#ibcon#*before return 0, iclass 20, count 0 2006.173.12:25:31.93#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.12:25:31.93#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.12:25:31.93#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.12:25:31.93#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.12:25:31.93$vck44/vblo=1,629.99 2006.173.12:25:31.93#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.12:25:31.93#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.12:25:31.93#ibcon#ireg 17 cls_cnt 0 2006.173.12:25:31.93#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.12:25:31.93#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.12:25:31.93#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.12:25:31.93#ibcon#enter wrdev, iclass 22, count 0 2006.173.12:25:31.93#ibcon#first serial, iclass 22, count 0 2006.173.12:25:31.93#ibcon#enter sib2, iclass 22, count 0 2006.173.12:25:31.93#ibcon#flushed, iclass 22, count 0 2006.173.12:25:31.93#ibcon#about to write, iclass 22, count 0 2006.173.12:25:31.93#ibcon#wrote, iclass 22, count 0 2006.173.12:25:31.93#ibcon#about to read 3, iclass 22, count 0 2006.173.12:25:31.95#ibcon#read 3, iclass 22, count 0 2006.173.12:25:31.95#ibcon#about to read 4, iclass 22, count 0 2006.173.12:25:31.95#ibcon#read 4, iclass 22, count 0 2006.173.12:25:31.95#ibcon#about to read 5, iclass 22, count 0 2006.173.12:25:31.95#ibcon#read 5, iclass 22, count 0 2006.173.12:25:31.95#ibcon#about to read 6, iclass 22, count 0 2006.173.12:25:31.95#ibcon#read 6, iclass 22, count 0 2006.173.12:25:31.95#ibcon#end of sib2, iclass 22, count 0 2006.173.12:25:31.95#ibcon#*mode == 0, iclass 22, count 0 2006.173.12:25:31.95#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.12:25:31.95#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.12:25:31.95#ibcon#*before write, iclass 22, count 0 2006.173.12:25:31.95#ibcon#enter sib2, iclass 22, count 0 2006.173.12:25:31.95#ibcon#flushed, iclass 22, count 0 2006.173.12:25:31.95#ibcon#about to write, iclass 22, count 0 2006.173.12:25:31.95#ibcon#wrote, iclass 22, count 0 2006.173.12:25:31.95#ibcon#about to read 3, iclass 22, count 0 2006.173.12:25:31.99#ibcon#read 3, iclass 22, count 0 2006.173.12:25:31.99#ibcon#about to read 4, iclass 22, count 0 2006.173.12:25:31.99#ibcon#read 4, iclass 22, count 0 2006.173.12:25:31.99#ibcon#about to read 5, iclass 22, count 0 2006.173.12:25:31.99#ibcon#read 5, iclass 22, count 0 2006.173.12:25:31.99#ibcon#about to read 6, iclass 22, count 0 2006.173.12:25:31.99#ibcon#read 6, iclass 22, count 0 2006.173.12:25:31.99#ibcon#end of sib2, iclass 22, count 0 2006.173.12:25:31.99#ibcon#*after write, iclass 22, count 0 2006.173.12:25:31.99#ibcon#*before return 0, iclass 22, count 0 2006.173.12:25:31.99#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.12:25:31.99#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.12:25:31.99#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.12:25:31.99#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.12:25:31.99$vck44/vb=1,4 2006.173.12:25:31.99#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.12:25:31.99#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.12:25:31.99#ibcon#ireg 11 cls_cnt 2 2006.173.12:25:31.99#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.12:25:31.99#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.12:25:31.99#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.12:25:31.99#ibcon#enter wrdev, iclass 24, count 2 2006.173.12:25:31.99#ibcon#first serial, iclass 24, count 2 2006.173.12:25:31.99#ibcon#enter sib2, iclass 24, count 2 2006.173.12:25:31.99#ibcon#flushed, iclass 24, count 2 2006.173.12:25:31.99#ibcon#about to write, iclass 24, count 2 2006.173.12:25:31.99#ibcon#wrote, iclass 24, count 2 2006.173.12:25:31.99#ibcon#about to read 3, iclass 24, count 2 2006.173.12:25:32.01#ibcon#read 3, iclass 24, count 2 2006.173.12:25:32.01#ibcon#about to read 4, iclass 24, count 2 2006.173.12:25:32.01#ibcon#read 4, iclass 24, count 2 2006.173.12:25:32.01#ibcon#about to read 5, iclass 24, count 2 2006.173.12:25:32.01#ibcon#read 5, iclass 24, count 2 2006.173.12:25:32.01#ibcon#about to read 6, iclass 24, count 2 2006.173.12:25:32.01#ibcon#read 6, iclass 24, count 2 2006.173.12:25:32.01#ibcon#end of sib2, iclass 24, count 2 2006.173.12:25:32.01#ibcon#*mode == 0, iclass 24, count 2 2006.173.12:25:32.01#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.12:25:32.01#ibcon#[27=AT01-04\r\n] 2006.173.12:25:32.01#ibcon#*before write, iclass 24, count 2 2006.173.12:25:32.01#ibcon#enter sib2, iclass 24, count 2 2006.173.12:25:32.01#ibcon#flushed, iclass 24, count 2 2006.173.12:25:32.01#ibcon#about to write, iclass 24, count 2 2006.173.12:25:32.01#ibcon#wrote, iclass 24, count 2 2006.173.12:25:32.01#ibcon#about to read 3, iclass 24, count 2 2006.173.12:25:32.04#ibcon#read 3, iclass 24, count 2 2006.173.12:25:32.04#ibcon#about to read 4, iclass 24, count 2 2006.173.12:25:32.04#ibcon#read 4, iclass 24, count 2 2006.173.12:25:32.04#ibcon#about to read 5, iclass 24, count 2 2006.173.12:25:32.04#ibcon#read 5, iclass 24, count 2 2006.173.12:25:32.04#ibcon#about to read 6, iclass 24, count 2 2006.173.12:25:32.04#ibcon#read 6, iclass 24, count 2 2006.173.12:25:32.04#ibcon#end of sib2, iclass 24, count 2 2006.173.12:25:32.04#ibcon#*after write, iclass 24, count 2 2006.173.12:25:32.04#ibcon#*before return 0, iclass 24, count 2 2006.173.12:25:32.04#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.12:25:32.04#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.12:25:32.04#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.12:25:32.04#ibcon#ireg 7 cls_cnt 0 2006.173.12:25:32.04#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.12:25:32.16#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.12:25:32.16#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.12:25:32.16#ibcon#enter wrdev, iclass 24, count 0 2006.173.12:25:32.16#ibcon#first serial, iclass 24, count 0 2006.173.12:25:32.16#ibcon#enter sib2, iclass 24, count 0 2006.173.12:25:32.16#ibcon#flushed, iclass 24, count 0 2006.173.12:25:32.16#ibcon#about to write, iclass 24, count 0 2006.173.12:25:32.16#ibcon#wrote, iclass 24, count 0 2006.173.12:25:32.16#ibcon#about to read 3, iclass 24, count 0 2006.173.12:25:32.18#ibcon#read 3, iclass 24, count 0 2006.173.12:25:32.18#ibcon#about to read 4, iclass 24, count 0 2006.173.12:25:32.18#ibcon#read 4, iclass 24, count 0 2006.173.12:25:32.18#ibcon#about to read 5, iclass 24, count 0 2006.173.12:25:32.18#ibcon#read 5, iclass 24, count 0 2006.173.12:25:32.18#ibcon#about to read 6, iclass 24, count 0 2006.173.12:25:32.18#ibcon#read 6, iclass 24, count 0 2006.173.12:25:32.18#ibcon#end of sib2, iclass 24, count 0 2006.173.12:25:32.18#ibcon#*mode == 0, iclass 24, count 0 2006.173.12:25:32.18#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.12:25:32.18#ibcon#[27=USB\r\n] 2006.173.12:25:32.18#ibcon#*before write, iclass 24, count 0 2006.173.12:25:32.18#ibcon#enter sib2, iclass 24, count 0 2006.173.12:25:32.18#ibcon#flushed, iclass 24, count 0 2006.173.12:25:32.18#ibcon#about to write, iclass 24, count 0 2006.173.12:25:32.18#ibcon#wrote, iclass 24, count 0 2006.173.12:25:32.18#ibcon#about to read 3, iclass 24, count 0 2006.173.12:25:32.21#ibcon#read 3, iclass 24, count 0 2006.173.12:25:32.21#ibcon#about to read 4, iclass 24, count 0 2006.173.12:25:32.21#ibcon#read 4, iclass 24, count 0 2006.173.12:25:32.21#ibcon#about to read 5, iclass 24, count 0 2006.173.12:25:32.21#ibcon#read 5, iclass 24, count 0 2006.173.12:25:32.21#ibcon#about to read 6, iclass 24, count 0 2006.173.12:25:32.21#ibcon#read 6, iclass 24, count 0 2006.173.12:25:32.21#ibcon#end of sib2, iclass 24, count 0 2006.173.12:25:32.21#ibcon#*after write, iclass 24, count 0 2006.173.12:25:32.21#ibcon#*before return 0, iclass 24, count 0 2006.173.12:25:32.21#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.12:25:32.21#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.12:25:32.21#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.12:25:32.21#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.12:25:32.21$vck44/vblo=2,634.99 2006.173.12:25:32.21#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.12:25:32.21#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.12:25:32.21#ibcon#ireg 17 cls_cnt 0 2006.173.12:25:32.21#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.12:25:32.21#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.12:25:32.21#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.12:25:32.21#ibcon#enter wrdev, iclass 26, count 0 2006.173.12:25:32.21#ibcon#first serial, iclass 26, count 0 2006.173.12:25:32.21#ibcon#enter sib2, iclass 26, count 0 2006.173.12:25:32.21#ibcon#flushed, iclass 26, count 0 2006.173.12:25:32.21#ibcon#about to write, iclass 26, count 0 2006.173.12:25:32.21#ibcon#wrote, iclass 26, count 0 2006.173.12:25:32.21#ibcon#about to read 3, iclass 26, count 0 2006.173.12:25:32.23#ibcon#read 3, iclass 26, count 0 2006.173.12:25:32.23#ibcon#about to read 4, iclass 26, count 0 2006.173.12:25:32.23#ibcon#read 4, iclass 26, count 0 2006.173.12:25:32.23#ibcon#about to read 5, iclass 26, count 0 2006.173.12:25:32.23#ibcon#read 5, iclass 26, count 0 2006.173.12:25:32.23#ibcon#about to read 6, iclass 26, count 0 2006.173.12:25:32.23#ibcon#read 6, iclass 26, count 0 2006.173.12:25:32.23#ibcon#end of sib2, iclass 26, count 0 2006.173.12:25:32.23#ibcon#*mode == 0, iclass 26, count 0 2006.173.12:25:32.23#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.12:25:32.23#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.12:25:32.23#ibcon#*before write, iclass 26, count 0 2006.173.12:25:32.23#ibcon#enter sib2, iclass 26, count 0 2006.173.12:25:32.23#ibcon#flushed, iclass 26, count 0 2006.173.12:25:32.23#ibcon#about to write, iclass 26, count 0 2006.173.12:25:32.23#ibcon#wrote, iclass 26, count 0 2006.173.12:25:32.23#ibcon#about to read 3, iclass 26, count 0 2006.173.12:25:32.27#ibcon#read 3, iclass 26, count 0 2006.173.12:25:32.27#ibcon#about to read 4, iclass 26, count 0 2006.173.12:25:32.27#ibcon#read 4, iclass 26, count 0 2006.173.12:25:32.27#ibcon#about to read 5, iclass 26, count 0 2006.173.12:25:32.27#ibcon#read 5, iclass 26, count 0 2006.173.12:25:32.27#ibcon#about to read 6, iclass 26, count 0 2006.173.12:25:32.27#ibcon#read 6, iclass 26, count 0 2006.173.12:25:32.27#ibcon#end of sib2, iclass 26, count 0 2006.173.12:25:32.27#ibcon#*after write, iclass 26, count 0 2006.173.12:25:32.27#ibcon#*before return 0, iclass 26, count 0 2006.173.12:25:32.27#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.12:25:32.27#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.12:25:32.27#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.12:25:32.27#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.12:25:32.27$vck44/vb=2,4 2006.173.12:25:32.27#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.12:25:32.27#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.12:25:32.27#ibcon#ireg 11 cls_cnt 2 2006.173.12:25:32.27#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.12:25:32.33#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.12:25:32.33#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.12:25:32.33#ibcon#enter wrdev, iclass 28, count 2 2006.173.12:25:32.33#ibcon#first serial, iclass 28, count 2 2006.173.12:25:32.33#ibcon#enter sib2, iclass 28, count 2 2006.173.12:25:32.33#ibcon#flushed, iclass 28, count 2 2006.173.12:25:32.33#ibcon#about to write, iclass 28, count 2 2006.173.12:25:32.33#ibcon#wrote, iclass 28, count 2 2006.173.12:25:32.33#ibcon#about to read 3, iclass 28, count 2 2006.173.12:25:32.35#ibcon#read 3, iclass 28, count 2 2006.173.12:25:32.35#ibcon#about to read 4, iclass 28, count 2 2006.173.12:25:32.35#ibcon#read 4, iclass 28, count 2 2006.173.12:25:32.35#ibcon#about to read 5, iclass 28, count 2 2006.173.12:25:32.35#ibcon#read 5, iclass 28, count 2 2006.173.12:25:32.35#ibcon#about to read 6, iclass 28, count 2 2006.173.12:25:32.35#ibcon#read 6, iclass 28, count 2 2006.173.12:25:32.35#ibcon#end of sib2, iclass 28, count 2 2006.173.12:25:32.35#ibcon#*mode == 0, iclass 28, count 2 2006.173.12:25:32.35#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.12:25:32.35#ibcon#[27=AT02-04\r\n] 2006.173.12:25:32.35#ibcon#*before write, iclass 28, count 2 2006.173.12:25:32.35#ibcon#enter sib2, iclass 28, count 2 2006.173.12:25:32.35#ibcon#flushed, iclass 28, count 2 2006.173.12:25:32.35#ibcon#about to write, iclass 28, count 2 2006.173.12:25:32.35#ibcon#wrote, iclass 28, count 2 2006.173.12:25:32.35#ibcon#about to read 3, iclass 28, count 2 2006.173.12:25:32.38#ibcon#read 3, iclass 28, count 2 2006.173.12:25:32.38#ibcon#about to read 4, iclass 28, count 2 2006.173.12:25:32.38#ibcon#read 4, iclass 28, count 2 2006.173.12:25:32.38#ibcon#about to read 5, iclass 28, count 2 2006.173.12:25:32.38#ibcon#read 5, iclass 28, count 2 2006.173.12:25:32.38#ibcon#about to read 6, iclass 28, count 2 2006.173.12:25:32.38#ibcon#read 6, iclass 28, count 2 2006.173.12:25:32.38#ibcon#end of sib2, iclass 28, count 2 2006.173.12:25:32.38#ibcon#*after write, iclass 28, count 2 2006.173.12:25:32.38#ibcon#*before return 0, iclass 28, count 2 2006.173.12:25:32.38#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.12:25:32.38#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.12:25:32.38#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.12:25:32.38#ibcon#ireg 7 cls_cnt 0 2006.173.12:25:32.38#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.12:25:32.50#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.12:25:32.50#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.12:25:32.50#ibcon#enter wrdev, iclass 28, count 0 2006.173.12:25:32.50#ibcon#first serial, iclass 28, count 0 2006.173.12:25:32.50#ibcon#enter sib2, iclass 28, count 0 2006.173.12:25:32.50#ibcon#flushed, iclass 28, count 0 2006.173.12:25:32.50#ibcon#about to write, iclass 28, count 0 2006.173.12:25:32.50#ibcon#wrote, iclass 28, count 0 2006.173.12:25:32.50#ibcon#about to read 3, iclass 28, count 0 2006.173.12:25:32.52#ibcon#read 3, iclass 28, count 0 2006.173.12:25:32.52#ibcon#about to read 4, iclass 28, count 0 2006.173.12:25:32.52#ibcon#read 4, iclass 28, count 0 2006.173.12:25:32.52#ibcon#about to read 5, iclass 28, count 0 2006.173.12:25:32.52#ibcon#read 5, iclass 28, count 0 2006.173.12:25:32.52#ibcon#about to read 6, iclass 28, count 0 2006.173.12:25:32.52#ibcon#read 6, iclass 28, count 0 2006.173.12:25:32.52#ibcon#end of sib2, iclass 28, count 0 2006.173.12:25:32.52#ibcon#*mode == 0, iclass 28, count 0 2006.173.12:25:32.52#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.12:25:32.52#ibcon#[27=USB\r\n] 2006.173.12:25:32.52#ibcon#*before write, iclass 28, count 0 2006.173.12:25:32.52#ibcon#enter sib2, iclass 28, count 0 2006.173.12:25:32.52#ibcon#flushed, iclass 28, count 0 2006.173.12:25:32.52#ibcon#about to write, iclass 28, count 0 2006.173.12:25:32.52#ibcon#wrote, iclass 28, count 0 2006.173.12:25:32.52#ibcon#about to read 3, iclass 28, count 0 2006.173.12:25:32.55#ibcon#read 3, iclass 28, count 0 2006.173.12:25:32.55#ibcon#about to read 4, iclass 28, count 0 2006.173.12:25:32.55#ibcon#read 4, iclass 28, count 0 2006.173.12:25:32.55#ibcon#about to read 5, iclass 28, count 0 2006.173.12:25:32.55#ibcon#read 5, iclass 28, count 0 2006.173.12:25:32.55#ibcon#about to read 6, iclass 28, count 0 2006.173.12:25:32.55#ibcon#read 6, iclass 28, count 0 2006.173.12:25:32.55#ibcon#end of sib2, iclass 28, count 0 2006.173.12:25:32.55#ibcon#*after write, iclass 28, count 0 2006.173.12:25:32.55#ibcon#*before return 0, iclass 28, count 0 2006.173.12:25:32.55#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.12:25:32.55#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.12:25:32.55#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.12:25:32.55#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.12:25:32.55$vck44/vblo=3,649.99 2006.173.12:25:32.55#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.12:25:32.55#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.12:25:32.55#ibcon#ireg 17 cls_cnt 0 2006.173.12:25:32.55#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.12:25:32.55#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.12:25:32.55#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.12:25:32.55#ibcon#enter wrdev, iclass 30, count 0 2006.173.12:25:32.55#ibcon#first serial, iclass 30, count 0 2006.173.12:25:32.55#ibcon#enter sib2, iclass 30, count 0 2006.173.12:25:32.55#ibcon#flushed, iclass 30, count 0 2006.173.12:25:32.55#ibcon#about to write, iclass 30, count 0 2006.173.12:25:32.55#ibcon#wrote, iclass 30, count 0 2006.173.12:25:32.55#ibcon#about to read 3, iclass 30, count 0 2006.173.12:25:32.57#ibcon#read 3, iclass 30, count 0 2006.173.12:25:32.57#ibcon#about to read 4, iclass 30, count 0 2006.173.12:25:32.57#ibcon#read 4, iclass 30, count 0 2006.173.12:25:32.57#ibcon#about to read 5, iclass 30, count 0 2006.173.12:25:32.57#ibcon#read 5, iclass 30, count 0 2006.173.12:25:32.57#ibcon#about to read 6, iclass 30, count 0 2006.173.12:25:32.57#ibcon#read 6, iclass 30, count 0 2006.173.12:25:32.57#ibcon#end of sib2, iclass 30, count 0 2006.173.12:25:32.57#ibcon#*mode == 0, iclass 30, count 0 2006.173.12:25:32.57#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.12:25:32.57#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.12:25:32.57#ibcon#*before write, iclass 30, count 0 2006.173.12:25:32.57#ibcon#enter sib2, iclass 30, count 0 2006.173.12:25:32.57#ibcon#flushed, iclass 30, count 0 2006.173.12:25:32.57#ibcon#about to write, iclass 30, count 0 2006.173.12:25:32.57#ibcon#wrote, iclass 30, count 0 2006.173.12:25:32.57#ibcon#about to read 3, iclass 30, count 0 2006.173.12:25:32.61#ibcon#read 3, iclass 30, count 0 2006.173.12:25:32.61#ibcon#about to read 4, iclass 30, count 0 2006.173.12:25:32.61#ibcon#read 4, iclass 30, count 0 2006.173.12:25:32.61#ibcon#about to read 5, iclass 30, count 0 2006.173.12:25:32.61#ibcon#read 5, iclass 30, count 0 2006.173.12:25:32.61#ibcon#about to read 6, iclass 30, count 0 2006.173.12:25:32.61#ibcon#read 6, iclass 30, count 0 2006.173.12:25:32.61#ibcon#end of sib2, iclass 30, count 0 2006.173.12:25:32.61#ibcon#*after write, iclass 30, count 0 2006.173.12:25:32.61#ibcon#*before return 0, iclass 30, count 0 2006.173.12:25:32.61#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.12:25:32.61#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.12:25:32.61#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.12:25:32.61#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.12:25:32.61$vck44/vb=3,4 2006.173.12:25:32.61#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.173.12:25:32.61#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.173.12:25:32.61#ibcon#ireg 11 cls_cnt 2 2006.173.12:25:32.61#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.12:25:32.67#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.12:25:32.67#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.12:25:32.67#ibcon#enter wrdev, iclass 32, count 2 2006.173.12:25:32.67#ibcon#first serial, iclass 32, count 2 2006.173.12:25:32.67#ibcon#enter sib2, iclass 32, count 2 2006.173.12:25:32.67#ibcon#flushed, iclass 32, count 2 2006.173.12:25:32.67#ibcon#about to write, iclass 32, count 2 2006.173.12:25:32.67#ibcon#wrote, iclass 32, count 2 2006.173.12:25:32.67#ibcon#about to read 3, iclass 32, count 2 2006.173.12:25:32.69#ibcon#read 3, iclass 32, count 2 2006.173.12:25:32.69#ibcon#about to read 4, iclass 32, count 2 2006.173.12:25:32.69#ibcon#read 4, iclass 32, count 2 2006.173.12:25:32.69#ibcon#about to read 5, iclass 32, count 2 2006.173.12:25:32.69#ibcon#read 5, iclass 32, count 2 2006.173.12:25:32.69#ibcon#about to read 6, iclass 32, count 2 2006.173.12:25:32.69#ibcon#read 6, iclass 32, count 2 2006.173.12:25:32.69#ibcon#end of sib2, iclass 32, count 2 2006.173.12:25:32.69#ibcon#*mode == 0, iclass 32, count 2 2006.173.12:25:32.69#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.173.12:25:32.69#ibcon#[27=AT03-04\r\n] 2006.173.12:25:32.69#ibcon#*before write, iclass 32, count 2 2006.173.12:25:32.69#ibcon#enter sib2, iclass 32, count 2 2006.173.12:25:32.69#ibcon#flushed, iclass 32, count 2 2006.173.12:25:32.69#ibcon#about to write, iclass 32, count 2 2006.173.12:25:32.69#ibcon#wrote, iclass 32, count 2 2006.173.12:25:32.69#ibcon#about to read 3, iclass 32, count 2 2006.173.12:25:32.72#ibcon#read 3, iclass 32, count 2 2006.173.12:25:32.72#ibcon#about to read 4, iclass 32, count 2 2006.173.12:25:32.72#ibcon#read 4, iclass 32, count 2 2006.173.12:25:32.72#ibcon#about to read 5, iclass 32, count 2 2006.173.12:25:32.72#ibcon#read 5, iclass 32, count 2 2006.173.12:25:32.72#ibcon#about to read 6, iclass 32, count 2 2006.173.12:25:32.72#ibcon#read 6, iclass 32, count 2 2006.173.12:25:32.72#ibcon#end of sib2, iclass 32, count 2 2006.173.12:25:32.72#ibcon#*after write, iclass 32, count 2 2006.173.12:25:32.72#ibcon#*before return 0, iclass 32, count 2 2006.173.12:25:32.72#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.12:25:32.72#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.173.12:25:32.72#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.173.12:25:32.72#ibcon#ireg 7 cls_cnt 0 2006.173.12:25:32.72#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.12:25:32.84#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.12:25:32.84#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.12:25:32.84#ibcon#enter wrdev, iclass 32, count 0 2006.173.12:25:32.84#ibcon#first serial, iclass 32, count 0 2006.173.12:25:32.84#ibcon#enter sib2, iclass 32, count 0 2006.173.12:25:32.84#ibcon#flushed, iclass 32, count 0 2006.173.12:25:32.84#ibcon#about to write, iclass 32, count 0 2006.173.12:25:32.84#ibcon#wrote, iclass 32, count 0 2006.173.12:25:32.84#ibcon#about to read 3, iclass 32, count 0 2006.173.12:25:32.86#ibcon#read 3, iclass 32, count 0 2006.173.12:25:32.86#ibcon#about to read 4, iclass 32, count 0 2006.173.12:25:32.86#ibcon#read 4, iclass 32, count 0 2006.173.12:25:32.86#ibcon#about to read 5, iclass 32, count 0 2006.173.12:25:32.86#ibcon#read 5, iclass 32, count 0 2006.173.12:25:32.86#ibcon#about to read 6, iclass 32, count 0 2006.173.12:25:32.86#ibcon#read 6, iclass 32, count 0 2006.173.12:25:32.86#ibcon#end of sib2, iclass 32, count 0 2006.173.12:25:32.86#ibcon#*mode == 0, iclass 32, count 0 2006.173.12:25:32.86#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.12:25:32.86#ibcon#[27=USB\r\n] 2006.173.12:25:32.86#ibcon#*before write, iclass 32, count 0 2006.173.12:25:32.86#ibcon#enter sib2, iclass 32, count 0 2006.173.12:25:32.86#ibcon#flushed, iclass 32, count 0 2006.173.12:25:32.86#ibcon#about to write, iclass 32, count 0 2006.173.12:25:32.86#ibcon#wrote, iclass 32, count 0 2006.173.12:25:32.86#ibcon#about to read 3, iclass 32, count 0 2006.173.12:25:32.89#ibcon#read 3, iclass 32, count 0 2006.173.12:25:32.89#ibcon#about to read 4, iclass 32, count 0 2006.173.12:25:32.89#ibcon#read 4, iclass 32, count 0 2006.173.12:25:32.89#ibcon#about to read 5, iclass 32, count 0 2006.173.12:25:32.89#ibcon#read 5, iclass 32, count 0 2006.173.12:25:32.89#ibcon#about to read 6, iclass 32, count 0 2006.173.12:25:32.89#ibcon#read 6, iclass 32, count 0 2006.173.12:25:32.89#ibcon#end of sib2, iclass 32, count 0 2006.173.12:25:32.89#ibcon#*after write, iclass 32, count 0 2006.173.12:25:32.89#ibcon#*before return 0, iclass 32, count 0 2006.173.12:25:32.89#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.12:25:32.89#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.173.12:25:32.89#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.12:25:32.89#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.12:25:32.89$vck44/vblo=4,679.99 2006.173.12:25:32.89#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.12:25:32.89#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.12:25:32.89#ibcon#ireg 17 cls_cnt 0 2006.173.12:25:32.89#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.12:25:32.89#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.12:25:32.89#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.12:25:32.89#ibcon#enter wrdev, iclass 34, count 0 2006.173.12:25:32.89#ibcon#first serial, iclass 34, count 0 2006.173.12:25:32.89#ibcon#enter sib2, iclass 34, count 0 2006.173.12:25:32.89#ibcon#flushed, iclass 34, count 0 2006.173.12:25:32.89#ibcon#about to write, iclass 34, count 0 2006.173.12:25:32.89#ibcon#wrote, iclass 34, count 0 2006.173.12:25:32.89#ibcon#about to read 3, iclass 34, count 0 2006.173.12:25:32.91#ibcon#read 3, iclass 34, count 0 2006.173.12:25:32.91#ibcon#about to read 4, iclass 34, count 0 2006.173.12:25:32.91#ibcon#read 4, iclass 34, count 0 2006.173.12:25:32.91#ibcon#about to read 5, iclass 34, count 0 2006.173.12:25:32.91#ibcon#read 5, iclass 34, count 0 2006.173.12:25:32.91#ibcon#about to read 6, iclass 34, count 0 2006.173.12:25:32.91#ibcon#read 6, iclass 34, count 0 2006.173.12:25:32.91#ibcon#end of sib2, iclass 34, count 0 2006.173.12:25:32.91#ibcon#*mode == 0, iclass 34, count 0 2006.173.12:25:32.91#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.12:25:32.91#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.12:25:32.91#ibcon#*before write, iclass 34, count 0 2006.173.12:25:32.91#ibcon#enter sib2, iclass 34, count 0 2006.173.12:25:32.91#ibcon#flushed, iclass 34, count 0 2006.173.12:25:32.91#ibcon#about to write, iclass 34, count 0 2006.173.12:25:32.91#ibcon#wrote, iclass 34, count 0 2006.173.12:25:32.91#ibcon#about to read 3, iclass 34, count 0 2006.173.12:25:32.95#ibcon#read 3, iclass 34, count 0 2006.173.12:25:32.95#ibcon#about to read 4, iclass 34, count 0 2006.173.12:25:32.95#ibcon#read 4, iclass 34, count 0 2006.173.12:25:32.95#ibcon#about to read 5, iclass 34, count 0 2006.173.12:25:32.95#ibcon#read 5, iclass 34, count 0 2006.173.12:25:32.95#ibcon#about to read 6, iclass 34, count 0 2006.173.12:25:32.95#ibcon#read 6, iclass 34, count 0 2006.173.12:25:32.95#ibcon#end of sib2, iclass 34, count 0 2006.173.12:25:32.95#ibcon#*after write, iclass 34, count 0 2006.173.12:25:32.95#ibcon#*before return 0, iclass 34, count 0 2006.173.12:25:32.95#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.12:25:32.95#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.12:25:32.95#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.12:25:32.95#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.12:25:32.95$vck44/vb=4,4 2006.173.12:25:32.95#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.12:25:32.95#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.12:25:32.95#ibcon#ireg 11 cls_cnt 2 2006.173.12:25:32.95#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.12:25:33.01#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.12:25:33.01#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.12:25:33.01#ibcon#enter wrdev, iclass 36, count 2 2006.173.12:25:33.01#ibcon#first serial, iclass 36, count 2 2006.173.12:25:33.01#ibcon#enter sib2, iclass 36, count 2 2006.173.12:25:33.01#ibcon#flushed, iclass 36, count 2 2006.173.12:25:33.01#ibcon#about to write, iclass 36, count 2 2006.173.12:25:33.01#ibcon#wrote, iclass 36, count 2 2006.173.12:25:33.01#ibcon#about to read 3, iclass 36, count 2 2006.173.12:25:33.03#ibcon#read 3, iclass 36, count 2 2006.173.12:25:33.03#ibcon#about to read 4, iclass 36, count 2 2006.173.12:25:33.03#ibcon#read 4, iclass 36, count 2 2006.173.12:25:33.03#ibcon#about to read 5, iclass 36, count 2 2006.173.12:25:33.03#ibcon#read 5, iclass 36, count 2 2006.173.12:25:33.03#ibcon#about to read 6, iclass 36, count 2 2006.173.12:25:33.03#ibcon#read 6, iclass 36, count 2 2006.173.12:25:33.03#ibcon#end of sib2, iclass 36, count 2 2006.173.12:25:33.03#ibcon#*mode == 0, iclass 36, count 2 2006.173.12:25:33.03#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.12:25:33.03#ibcon#[27=AT04-04\r\n] 2006.173.12:25:33.03#ibcon#*before write, iclass 36, count 2 2006.173.12:25:33.03#ibcon#enter sib2, iclass 36, count 2 2006.173.12:25:33.03#ibcon#flushed, iclass 36, count 2 2006.173.12:25:33.03#ibcon#about to write, iclass 36, count 2 2006.173.12:25:33.03#ibcon#wrote, iclass 36, count 2 2006.173.12:25:33.03#ibcon#about to read 3, iclass 36, count 2 2006.173.12:25:33.06#ibcon#read 3, iclass 36, count 2 2006.173.12:25:33.06#ibcon#about to read 4, iclass 36, count 2 2006.173.12:25:33.06#ibcon#read 4, iclass 36, count 2 2006.173.12:25:33.06#ibcon#about to read 5, iclass 36, count 2 2006.173.12:25:33.06#ibcon#read 5, iclass 36, count 2 2006.173.12:25:33.06#ibcon#about to read 6, iclass 36, count 2 2006.173.12:25:33.06#ibcon#read 6, iclass 36, count 2 2006.173.12:25:33.06#ibcon#end of sib2, iclass 36, count 2 2006.173.12:25:33.06#ibcon#*after write, iclass 36, count 2 2006.173.12:25:33.06#ibcon#*before return 0, iclass 36, count 2 2006.173.12:25:33.06#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.12:25:33.06#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.12:25:33.06#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.12:25:33.06#ibcon#ireg 7 cls_cnt 0 2006.173.12:25:33.06#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.12:25:33.18#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.12:25:33.18#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.12:25:33.18#ibcon#enter wrdev, iclass 36, count 0 2006.173.12:25:33.18#ibcon#first serial, iclass 36, count 0 2006.173.12:25:33.18#ibcon#enter sib2, iclass 36, count 0 2006.173.12:25:33.18#ibcon#flushed, iclass 36, count 0 2006.173.12:25:33.18#ibcon#about to write, iclass 36, count 0 2006.173.12:25:33.18#ibcon#wrote, iclass 36, count 0 2006.173.12:25:33.18#ibcon#about to read 3, iclass 36, count 0 2006.173.12:25:33.20#ibcon#read 3, iclass 36, count 0 2006.173.12:25:33.20#ibcon#about to read 4, iclass 36, count 0 2006.173.12:25:33.20#ibcon#read 4, iclass 36, count 0 2006.173.12:25:33.20#ibcon#about to read 5, iclass 36, count 0 2006.173.12:25:33.20#ibcon#read 5, iclass 36, count 0 2006.173.12:25:33.20#ibcon#about to read 6, iclass 36, count 0 2006.173.12:25:33.20#ibcon#read 6, iclass 36, count 0 2006.173.12:25:33.20#ibcon#end of sib2, iclass 36, count 0 2006.173.12:25:33.20#ibcon#*mode == 0, iclass 36, count 0 2006.173.12:25:33.20#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.12:25:33.20#ibcon#[27=USB\r\n] 2006.173.12:25:33.20#ibcon#*before write, iclass 36, count 0 2006.173.12:25:33.20#ibcon#enter sib2, iclass 36, count 0 2006.173.12:25:33.20#ibcon#flushed, iclass 36, count 0 2006.173.12:25:33.20#ibcon#about to write, iclass 36, count 0 2006.173.12:25:33.20#ibcon#wrote, iclass 36, count 0 2006.173.12:25:33.20#ibcon#about to read 3, iclass 36, count 0 2006.173.12:25:33.23#ibcon#read 3, iclass 36, count 0 2006.173.12:25:33.23#ibcon#about to read 4, iclass 36, count 0 2006.173.12:25:33.23#ibcon#read 4, iclass 36, count 0 2006.173.12:25:33.23#ibcon#about to read 5, iclass 36, count 0 2006.173.12:25:33.23#ibcon#read 5, iclass 36, count 0 2006.173.12:25:33.23#ibcon#about to read 6, iclass 36, count 0 2006.173.12:25:33.23#ibcon#read 6, iclass 36, count 0 2006.173.12:25:33.23#ibcon#end of sib2, iclass 36, count 0 2006.173.12:25:33.23#ibcon#*after write, iclass 36, count 0 2006.173.12:25:33.23#ibcon#*before return 0, iclass 36, count 0 2006.173.12:25:33.23#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.12:25:33.23#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.12:25:33.23#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.12:25:33.23#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.12:25:33.23$vck44/vblo=5,709.99 2006.173.12:25:33.23#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.12:25:33.23#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.12:25:33.23#ibcon#ireg 17 cls_cnt 0 2006.173.12:25:33.23#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.12:25:33.23#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.12:25:33.23#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.12:25:33.23#ibcon#enter wrdev, iclass 38, count 0 2006.173.12:25:33.23#ibcon#first serial, iclass 38, count 0 2006.173.12:25:33.23#ibcon#enter sib2, iclass 38, count 0 2006.173.12:25:33.23#ibcon#flushed, iclass 38, count 0 2006.173.12:25:33.23#ibcon#about to write, iclass 38, count 0 2006.173.12:25:33.23#ibcon#wrote, iclass 38, count 0 2006.173.12:25:33.23#ibcon#about to read 3, iclass 38, count 0 2006.173.12:25:33.25#ibcon#read 3, iclass 38, count 0 2006.173.12:25:33.25#ibcon#about to read 4, iclass 38, count 0 2006.173.12:25:33.25#ibcon#read 4, iclass 38, count 0 2006.173.12:25:33.25#ibcon#about to read 5, iclass 38, count 0 2006.173.12:25:33.25#ibcon#read 5, iclass 38, count 0 2006.173.12:25:33.25#ibcon#about to read 6, iclass 38, count 0 2006.173.12:25:33.25#ibcon#read 6, iclass 38, count 0 2006.173.12:25:33.25#ibcon#end of sib2, iclass 38, count 0 2006.173.12:25:33.25#ibcon#*mode == 0, iclass 38, count 0 2006.173.12:25:33.25#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.12:25:33.25#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.12:25:33.25#ibcon#*before write, iclass 38, count 0 2006.173.12:25:33.25#ibcon#enter sib2, iclass 38, count 0 2006.173.12:25:33.25#ibcon#flushed, iclass 38, count 0 2006.173.12:25:33.25#ibcon#about to write, iclass 38, count 0 2006.173.12:25:33.25#ibcon#wrote, iclass 38, count 0 2006.173.12:25:33.25#ibcon#about to read 3, iclass 38, count 0 2006.173.12:25:33.29#ibcon#read 3, iclass 38, count 0 2006.173.12:25:33.29#ibcon#about to read 4, iclass 38, count 0 2006.173.12:25:33.29#ibcon#read 4, iclass 38, count 0 2006.173.12:25:33.29#ibcon#about to read 5, iclass 38, count 0 2006.173.12:25:33.29#ibcon#read 5, iclass 38, count 0 2006.173.12:25:33.29#ibcon#about to read 6, iclass 38, count 0 2006.173.12:25:33.29#ibcon#read 6, iclass 38, count 0 2006.173.12:25:33.29#ibcon#end of sib2, iclass 38, count 0 2006.173.12:25:33.29#ibcon#*after write, iclass 38, count 0 2006.173.12:25:33.29#ibcon#*before return 0, iclass 38, count 0 2006.173.12:25:33.29#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.12:25:33.29#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.12:25:33.29#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.12:25:33.29#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.12:25:33.29$vck44/vb=5,4 2006.173.12:25:33.29#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.12:25:33.29#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.12:25:33.29#ibcon#ireg 11 cls_cnt 2 2006.173.12:25:33.29#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.12:25:33.35#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.12:25:33.35#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.12:25:33.35#ibcon#enter wrdev, iclass 40, count 2 2006.173.12:25:33.35#ibcon#first serial, iclass 40, count 2 2006.173.12:25:33.35#ibcon#enter sib2, iclass 40, count 2 2006.173.12:25:33.35#ibcon#flushed, iclass 40, count 2 2006.173.12:25:33.35#ibcon#about to write, iclass 40, count 2 2006.173.12:25:33.35#ibcon#wrote, iclass 40, count 2 2006.173.12:25:33.35#ibcon#about to read 3, iclass 40, count 2 2006.173.12:25:33.37#ibcon#read 3, iclass 40, count 2 2006.173.12:25:33.37#ibcon#about to read 4, iclass 40, count 2 2006.173.12:25:33.37#ibcon#read 4, iclass 40, count 2 2006.173.12:25:33.37#ibcon#about to read 5, iclass 40, count 2 2006.173.12:25:33.37#ibcon#read 5, iclass 40, count 2 2006.173.12:25:33.37#ibcon#about to read 6, iclass 40, count 2 2006.173.12:25:33.37#ibcon#read 6, iclass 40, count 2 2006.173.12:25:33.37#ibcon#end of sib2, iclass 40, count 2 2006.173.12:25:33.37#ibcon#*mode == 0, iclass 40, count 2 2006.173.12:25:33.37#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.12:25:33.37#ibcon#[27=AT05-04\r\n] 2006.173.12:25:33.37#ibcon#*before write, iclass 40, count 2 2006.173.12:25:33.37#ibcon#enter sib2, iclass 40, count 2 2006.173.12:25:33.37#ibcon#flushed, iclass 40, count 2 2006.173.12:25:33.37#ibcon#about to write, iclass 40, count 2 2006.173.12:25:33.37#ibcon#wrote, iclass 40, count 2 2006.173.12:25:33.37#ibcon#about to read 3, iclass 40, count 2 2006.173.12:25:33.40#ibcon#read 3, iclass 40, count 2 2006.173.12:25:33.40#ibcon#about to read 4, iclass 40, count 2 2006.173.12:25:33.40#ibcon#read 4, iclass 40, count 2 2006.173.12:25:33.40#ibcon#about to read 5, iclass 40, count 2 2006.173.12:25:33.40#ibcon#read 5, iclass 40, count 2 2006.173.12:25:33.40#ibcon#about to read 6, iclass 40, count 2 2006.173.12:25:33.40#ibcon#read 6, iclass 40, count 2 2006.173.12:25:33.40#ibcon#end of sib2, iclass 40, count 2 2006.173.12:25:33.40#ibcon#*after write, iclass 40, count 2 2006.173.12:25:33.40#ibcon#*before return 0, iclass 40, count 2 2006.173.12:25:33.40#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.12:25:33.40#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.12:25:33.40#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.12:25:33.40#ibcon#ireg 7 cls_cnt 0 2006.173.12:25:33.40#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.12:25:33.52#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.12:25:33.52#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.12:25:33.52#ibcon#enter wrdev, iclass 40, count 0 2006.173.12:25:33.52#ibcon#first serial, iclass 40, count 0 2006.173.12:25:33.52#ibcon#enter sib2, iclass 40, count 0 2006.173.12:25:33.52#ibcon#flushed, iclass 40, count 0 2006.173.12:25:33.52#ibcon#about to write, iclass 40, count 0 2006.173.12:25:33.52#ibcon#wrote, iclass 40, count 0 2006.173.12:25:33.52#ibcon#about to read 3, iclass 40, count 0 2006.173.12:25:33.54#ibcon#read 3, iclass 40, count 0 2006.173.12:25:33.54#ibcon#about to read 4, iclass 40, count 0 2006.173.12:25:33.54#ibcon#read 4, iclass 40, count 0 2006.173.12:25:33.54#ibcon#about to read 5, iclass 40, count 0 2006.173.12:25:33.54#ibcon#read 5, iclass 40, count 0 2006.173.12:25:33.54#ibcon#about to read 6, iclass 40, count 0 2006.173.12:25:33.54#ibcon#read 6, iclass 40, count 0 2006.173.12:25:33.54#ibcon#end of sib2, iclass 40, count 0 2006.173.12:25:33.54#ibcon#*mode == 0, iclass 40, count 0 2006.173.12:25:33.54#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.12:25:33.54#ibcon#[27=USB\r\n] 2006.173.12:25:33.54#ibcon#*before write, iclass 40, count 0 2006.173.12:25:33.54#ibcon#enter sib2, iclass 40, count 0 2006.173.12:25:33.54#ibcon#flushed, iclass 40, count 0 2006.173.12:25:33.54#ibcon#about to write, iclass 40, count 0 2006.173.12:25:33.54#ibcon#wrote, iclass 40, count 0 2006.173.12:25:33.54#ibcon#about to read 3, iclass 40, count 0 2006.173.12:25:33.57#ibcon#read 3, iclass 40, count 0 2006.173.12:25:33.57#ibcon#about to read 4, iclass 40, count 0 2006.173.12:25:33.57#ibcon#read 4, iclass 40, count 0 2006.173.12:25:33.57#ibcon#about to read 5, iclass 40, count 0 2006.173.12:25:33.57#ibcon#read 5, iclass 40, count 0 2006.173.12:25:33.57#ibcon#about to read 6, iclass 40, count 0 2006.173.12:25:33.57#ibcon#read 6, iclass 40, count 0 2006.173.12:25:33.57#ibcon#end of sib2, iclass 40, count 0 2006.173.12:25:33.57#ibcon#*after write, iclass 40, count 0 2006.173.12:25:33.57#ibcon#*before return 0, iclass 40, count 0 2006.173.12:25:33.57#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.12:25:33.57#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.12:25:33.57#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.12:25:33.57#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.12:25:33.57$vck44/vblo=6,719.99 2006.173.12:25:33.57#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.12:25:33.57#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.12:25:33.57#ibcon#ireg 17 cls_cnt 0 2006.173.12:25:33.57#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.12:25:33.57#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.12:25:33.57#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.12:25:33.57#ibcon#enter wrdev, iclass 4, count 0 2006.173.12:25:33.57#ibcon#first serial, iclass 4, count 0 2006.173.12:25:33.57#ibcon#enter sib2, iclass 4, count 0 2006.173.12:25:33.57#ibcon#flushed, iclass 4, count 0 2006.173.12:25:33.57#ibcon#about to write, iclass 4, count 0 2006.173.12:25:33.57#ibcon#wrote, iclass 4, count 0 2006.173.12:25:33.57#ibcon#about to read 3, iclass 4, count 0 2006.173.12:25:33.59#ibcon#read 3, iclass 4, count 0 2006.173.12:25:33.59#ibcon#about to read 4, iclass 4, count 0 2006.173.12:25:33.59#ibcon#read 4, iclass 4, count 0 2006.173.12:25:33.59#ibcon#about to read 5, iclass 4, count 0 2006.173.12:25:33.59#ibcon#read 5, iclass 4, count 0 2006.173.12:25:33.59#ibcon#about to read 6, iclass 4, count 0 2006.173.12:25:33.59#ibcon#read 6, iclass 4, count 0 2006.173.12:25:33.59#ibcon#end of sib2, iclass 4, count 0 2006.173.12:25:33.59#ibcon#*mode == 0, iclass 4, count 0 2006.173.12:25:33.59#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.12:25:33.59#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.12:25:33.59#ibcon#*before write, iclass 4, count 0 2006.173.12:25:33.59#ibcon#enter sib2, iclass 4, count 0 2006.173.12:25:33.59#ibcon#flushed, iclass 4, count 0 2006.173.12:25:33.59#ibcon#about to write, iclass 4, count 0 2006.173.12:25:33.59#ibcon#wrote, iclass 4, count 0 2006.173.12:25:33.59#ibcon#about to read 3, iclass 4, count 0 2006.173.12:25:33.63#ibcon#read 3, iclass 4, count 0 2006.173.12:25:33.63#ibcon#about to read 4, iclass 4, count 0 2006.173.12:25:33.63#ibcon#read 4, iclass 4, count 0 2006.173.12:25:33.63#ibcon#about to read 5, iclass 4, count 0 2006.173.12:25:33.63#ibcon#read 5, iclass 4, count 0 2006.173.12:25:33.63#ibcon#about to read 6, iclass 4, count 0 2006.173.12:25:33.63#ibcon#read 6, iclass 4, count 0 2006.173.12:25:33.63#ibcon#end of sib2, iclass 4, count 0 2006.173.12:25:33.63#ibcon#*after write, iclass 4, count 0 2006.173.12:25:33.63#ibcon#*before return 0, iclass 4, count 0 2006.173.12:25:33.63#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.12:25:33.63#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.12:25:33.63#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.12:25:33.63#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.12:25:33.63$vck44/vb=6,4 2006.173.12:25:33.63#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.12:25:33.63#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.12:25:33.63#ibcon#ireg 11 cls_cnt 2 2006.173.12:25:33.63#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.12:25:33.69#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.12:25:33.69#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.12:25:33.69#ibcon#enter wrdev, iclass 6, count 2 2006.173.12:25:33.69#ibcon#first serial, iclass 6, count 2 2006.173.12:25:33.69#ibcon#enter sib2, iclass 6, count 2 2006.173.12:25:33.69#ibcon#flushed, iclass 6, count 2 2006.173.12:25:33.69#ibcon#about to write, iclass 6, count 2 2006.173.12:25:33.69#ibcon#wrote, iclass 6, count 2 2006.173.12:25:33.69#ibcon#about to read 3, iclass 6, count 2 2006.173.12:25:33.71#ibcon#read 3, iclass 6, count 2 2006.173.12:25:33.71#ibcon#about to read 4, iclass 6, count 2 2006.173.12:25:33.71#ibcon#read 4, iclass 6, count 2 2006.173.12:25:33.71#ibcon#about to read 5, iclass 6, count 2 2006.173.12:25:33.71#ibcon#read 5, iclass 6, count 2 2006.173.12:25:33.71#ibcon#about to read 6, iclass 6, count 2 2006.173.12:25:33.71#ibcon#read 6, iclass 6, count 2 2006.173.12:25:33.71#ibcon#end of sib2, iclass 6, count 2 2006.173.12:25:33.71#ibcon#*mode == 0, iclass 6, count 2 2006.173.12:25:33.71#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.12:25:33.71#ibcon#[27=AT06-04\r\n] 2006.173.12:25:33.71#ibcon#*before write, iclass 6, count 2 2006.173.12:25:33.71#ibcon#enter sib2, iclass 6, count 2 2006.173.12:25:33.71#ibcon#flushed, iclass 6, count 2 2006.173.12:25:33.71#ibcon#about to write, iclass 6, count 2 2006.173.12:25:33.71#ibcon#wrote, iclass 6, count 2 2006.173.12:25:33.71#ibcon#about to read 3, iclass 6, count 2 2006.173.12:25:33.74#ibcon#read 3, iclass 6, count 2 2006.173.12:25:33.74#ibcon#about to read 4, iclass 6, count 2 2006.173.12:25:33.74#ibcon#read 4, iclass 6, count 2 2006.173.12:25:33.74#ibcon#about to read 5, iclass 6, count 2 2006.173.12:25:33.74#ibcon#read 5, iclass 6, count 2 2006.173.12:25:33.74#ibcon#about to read 6, iclass 6, count 2 2006.173.12:25:33.74#ibcon#read 6, iclass 6, count 2 2006.173.12:25:33.74#ibcon#end of sib2, iclass 6, count 2 2006.173.12:25:33.74#ibcon#*after write, iclass 6, count 2 2006.173.12:25:33.74#ibcon#*before return 0, iclass 6, count 2 2006.173.12:25:33.74#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.12:25:33.74#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.12:25:33.74#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.12:25:33.74#ibcon#ireg 7 cls_cnt 0 2006.173.12:25:33.74#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.12:25:33.86#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.12:25:33.86#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.12:25:33.86#ibcon#enter wrdev, iclass 6, count 0 2006.173.12:25:33.86#ibcon#first serial, iclass 6, count 0 2006.173.12:25:33.86#ibcon#enter sib2, iclass 6, count 0 2006.173.12:25:33.86#ibcon#flushed, iclass 6, count 0 2006.173.12:25:33.86#ibcon#about to write, iclass 6, count 0 2006.173.12:25:33.86#ibcon#wrote, iclass 6, count 0 2006.173.12:25:33.86#ibcon#about to read 3, iclass 6, count 0 2006.173.12:25:33.88#ibcon#read 3, iclass 6, count 0 2006.173.12:25:33.88#ibcon#about to read 4, iclass 6, count 0 2006.173.12:25:33.88#ibcon#read 4, iclass 6, count 0 2006.173.12:25:33.88#ibcon#about to read 5, iclass 6, count 0 2006.173.12:25:33.88#ibcon#read 5, iclass 6, count 0 2006.173.12:25:33.88#ibcon#about to read 6, iclass 6, count 0 2006.173.12:25:33.88#ibcon#read 6, iclass 6, count 0 2006.173.12:25:33.88#ibcon#end of sib2, iclass 6, count 0 2006.173.12:25:33.88#ibcon#*mode == 0, iclass 6, count 0 2006.173.12:25:33.88#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.12:25:33.88#ibcon#[27=USB\r\n] 2006.173.12:25:33.88#ibcon#*before write, iclass 6, count 0 2006.173.12:25:33.88#ibcon#enter sib2, iclass 6, count 0 2006.173.12:25:33.88#ibcon#flushed, iclass 6, count 0 2006.173.12:25:33.88#ibcon#about to write, iclass 6, count 0 2006.173.12:25:33.88#ibcon#wrote, iclass 6, count 0 2006.173.12:25:33.88#ibcon#about to read 3, iclass 6, count 0 2006.173.12:25:33.91#ibcon#read 3, iclass 6, count 0 2006.173.12:25:33.91#ibcon#about to read 4, iclass 6, count 0 2006.173.12:25:33.91#ibcon#read 4, iclass 6, count 0 2006.173.12:25:33.91#ibcon#about to read 5, iclass 6, count 0 2006.173.12:25:33.91#ibcon#read 5, iclass 6, count 0 2006.173.12:25:33.91#ibcon#about to read 6, iclass 6, count 0 2006.173.12:25:33.91#ibcon#read 6, iclass 6, count 0 2006.173.12:25:33.91#ibcon#end of sib2, iclass 6, count 0 2006.173.12:25:33.91#ibcon#*after write, iclass 6, count 0 2006.173.12:25:33.91#ibcon#*before return 0, iclass 6, count 0 2006.173.12:25:33.91#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.12:25:33.91#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.12:25:33.91#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.12:25:33.91#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.12:25:33.91$vck44/vblo=7,734.99 2006.173.12:25:33.91#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.12:25:33.91#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.12:25:33.91#ibcon#ireg 17 cls_cnt 0 2006.173.12:25:33.91#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.12:25:33.91#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.12:25:33.91#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.12:25:33.91#ibcon#enter wrdev, iclass 10, count 0 2006.173.12:25:33.91#ibcon#first serial, iclass 10, count 0 2006.173.12:25:33.91#ibcon#enter sib2, iclass 10, count 0 2006.173.12:25:33.91#ibcon#flushed, iclass 10, count 0 2006.173.12:25:33.91#ibcon#about to write, iclass 10, count 0 2006.173.12:25:33.91#ibcon#wrote, iclass 10, count 0 2006.173.12:25:33.91#ibcon#about to read 3, iclass 10, count 0 2006.173.12:25:33.93#ibcon#read 3, iclass 10, count 0 2006.173.12:25:33.93#ibcon#about to read 4, iclass 10, count 0 2006.173.12:25:33.93#ibcon#read 4, iclass 10, count 0 2006.173.12:25:33.93#ibcon#about to read 5, iclass 10, count 0 2006.173.12:25:33.93#ibcon#read 5, iclass 10, count 0 2006.173.12:25:33.93#ibcon#about to read 6, iclass 10, count 0 2006.173.12:25:33.93#ibcon#read 6, iclass 10, count 0 2006.173.12:25:33.93#ibcon#end of sib2, iclass 10, count 0 2006.173.12:25:33.93#ibcon#*mode == 0, iclass 10, count 0 2006.173.12:25:33.93#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.12:25:33.93#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.12:25:33.93#ibcon#*before write, iclass 10, count 0 2006.173.12:25:33.93#ibcon#enter sib2, iclass 10, count 0 2006.173.12:25:33.93#ibcon#flushed, iclass 10, count 0 2006.173.12:25:33.93#ibcon#about to write, iclass 10, count 0 2006.173.12:25:33.93#ibcon#wrote, iclass 10, count 0 2006.173.12:25:33.93#ibcon#about to read 3, iclass 10, count 0 2006.173.12:25:33.97#ibcon#read 3, iclass 10, count 0 2006.173.12:25:33.97#ibcon#about to read 4, iclass 10, count 0 2006.173.12:25:33.97#ibcon#read 4, iclass 10, count 0 2006.173.12:25:33.97#ibcon#about to read 5, iclass 10, count 0 2006.173.12:25:33.97#ibcon#read 5, iclass 10, count 0 2006.173.12:25:33.97#ibcon#about to read 6, iclass 10, count 0 2006.173.12:25:33.97#ibcon#read 6, iclass 10, count 0 2006.173.12:25:33.97#ibcon#end of sib2, iclass 10, count 0 2006.173.12:25:33.97#ibcon#*after write, iclass 10, count 0 2006.173.12:25:33.97#ibcon#*before return 0, iclass 10, count 0 2006.173.12:25:33.97#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.12:25:33.97#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.12:25:33.97#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.12:25:33.97#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.12:25:33.97$vck44/vb=7,4 2006.173.12:25:33.97#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.12:25:33.97#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.12:25:33.97#ibcon#ireg 11 cls_cnt 2 2006.173.12:25:33.97#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.12:25:34.03#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.12:25:34.03#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.12:25:34.03#ibcon#enter wrdev, iclass 12, count 2 2006.173.12:25:34.03#ibcon#first serial, iclass 12, count 2 2006.173.12:25:34.03#ibcon#enter sib2, iclass 12, count 2 2006.173.12:25:34.03#ibcon#flushed, iclass 12, count 2 2006.173.12:25:34.03#ibcon#about to write, iclass 12, count 2 2006.173.12:25:34.03#ibcon#wrote, iclass 12, count 2 2006.173.12:25:34.03#ibcon#about to read 3, iclass 12, count 2 2006.173.12:25:34.05#ibcon#read 3, iclass 12, count 2 2006.173.12:25:34.05#ibcon#about to read 4, iclass 12, count 2 2006.173.12:25:34.05#ibcon#read 4, iclass 12, count 2 2006.173.12:25:34.05#ibcon#about to read 5, iclass 12, count 2 2006.173.12:25:34.05#ibcon#read 5, iclass 12, count 2 2006.173.12:25:34.05#ibcon#about to read 6, iclass 12, count 2 2006.173.12:25:34.05#ibcon#read 6, iclass 12, count 2 2006.173.12:25:34.05#ibcon#end of sib2, iclass 12, count 2 2006.173.12:25:34.05#ibcon#*mode == 0, iclass 12, count 2 2006.173.12:25:34.05#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.12:25:34.05#ibcon#[27=AT07-04\r\n] 2006.173.12:25:34.05#ibcon#*before write, iclass 12, count 2 2006.173.12:25:34.05#ibcon#enter sib2, iclass 12, count 2 2006.173.12:25:34.05#ibcon#flushed, iclass 12, count 2 2006.173.12:25:34.05#ibcon#about to write, iclass 12, count 2 2006.173.12:25:34.05#ibcon#wrote, iclass 12, count 2 2006.173.12:25:34.05#ibcon#about to read 3, iclass 12, count 2 2006.173.12:25:34.08#ibcon#read 3, iclass 12, count 2 2006.173.12:25:34.08#ibcon#about to read 4, iclass 12, count 2 2006.173.12:25:34.08#ibcon#read 4, iclass 12, count 2 2006.173.12:25:34.08#ibcon#about to read 5, iclass 12, count 2 2006.173.12:25:34.08#ibcon#read 5, iclass 12, count 2 2006.173.12:25:34.08#ibcon#about to read 6, iclass 12, count 2 2006.173.12:25:34.08#ibcon#read 6, iclass 12, count 2 2006.173.12:25:34.08#ibcon#end of sib2, iclass 12, count 2 2006.173.12:25:34.08#ibcon#*after write, iclass 12, count 2 2006.173.12:25:34.08#ibcon#*before return 0, iclass 12, count 2 2006.173.12:25:34.08#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.12:25:34.08#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.12:25:34.08#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.12:25:34.08#ibcon#ireg 7 cls_cnt 0 2006.173.12:25:34.08#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.12:25:34.20#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.12:25:34.20#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.12:25:34.20#ibcon#enter wrdev, iclass 12, count 0 2006.173.12:25:34.20#ibcon#first serial, iclass 12, count 0 2006.173.12:25:34.20#ibcon#enter sib2, iclass 12, count 0 2006.173.12:25:34.20#ibcon#flushed, iclass 12, count 0 2006.173.12:25:34.20#ibcon#about to write, iclass 12, count 0 2006.173.12:25:34.20#ibcon#wrote, iclass 12, count 0 2006.173.12:25:34.20#ibcon#about to read 3, iclass 12, count 0 2006.173.12:25:34.22#ibcon#read 3, iclass 12, count 0 2006.173.12:25:34.22#ibcon#about to read 4, iclass 12, count 0 2006.173.12:25:34.22#ibcon#read 4, iclass 12, count 0 2006.173.12:25:34.22#ibcon#about to read 5, iclass 12, count 0 2006.173.12:25:34.22#ibcon#read 5, iclass 12, count 0 2006.173.12:25:34.22#ibcon#about to read 6, iclass 12, count 0 2006.173.12:25:34.22#ibcon#read 6, iclass 12, count 0 2006.173.12:25:34.22#ibcon#end of sib2, iclass 12, count 0 2006.173.12:25:34.22#ibcon#*mode == 0, iclass 12, count 0 2006.173.12:25:34.22#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.12:25:34.22#ibcon#[27=USB\r\n] 2006.173.12:25:34.22#ibcon#*before write, iclass 12, count 0 2006.173.12:25:34.22#ibcon#enter sib2, iclass 12, count 0 2006.173.12:25:34.22#ibcon#flushed, iclass 12, count 0 2006.173.12:25:34.22#ibcon#about to write, iclass 12, count 0 2006.173.12:25:34.22#ibcon#wrote, iclass 12, count 0 2006.173.12:25:34.22#ibcon#about to read 3, iclass 12, count 0 2006.173.12:25:34.25#ibcon#read 3, iclass 12, count 0 2006.173.12:25:34.25#ibcon#about to read 4, iclass 12, count 0 2006.173.12:25:34.25#ibcon#read 4, iclass 12, count 0 2006.173.12:25:34.25#ibcon#about to read 5, iclass 12, count 0 2006.173.12:25:34.25#ibcon#read 5, iclass 12, count 0 2006.173.12:25:34.25#ibcon#about to read 6, iclass 12, count 0 2006.173.12:25:34.25#ibcon#read 6, iclass 12, count 0 2006.173.12:25:34.25#ibcon#end of sib2, iclass 12, count 0 2006.173.12:25:34.25#ibcon#*after write, iclass 12, count 0 2006.173.12:25:34.25#ibcon#*before return 0, iclass 12, count 0 2006.173.12:25:34.25#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.12:25:34.25#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.12:25:34.25#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.12:25:34.25#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.12:25:34.25$vck44/vblo=8,744.99 2006.173.12:25:34.25#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.12:25:34.25#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.12:25:34.25#ibcon#ireg 17 cls_cnt 0 2006.173.12:25:34.25#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.12:25:34.25#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.12:25:34.25#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.12:25:34.25#ibcon#enter wrdev, iclass 14, count 0 2006.173.12:25:34.25#ibcon#first serial, iclass 14, count 0 2006.173.12:25:34.25#ibcon#enter sib2, iclass 14, count 0 2006.173.12:25:34.25#ibcon#flushed, iclass 14, count 0 2006.173.12:25:34.25#ibcon#about to write, iclass 14, count 0 2006.173.12:25:34.25#ibcon#wrote, iclass 14, count 0 2006.173.12:25:34.25#ibcon#about to read 3, iclass 14, count 0 2006.173.12:25:34.27#ibcon#read 3, iclass 14, count 0 2006.173.12:25:34.27#ibcon#about to read 4, iclass 14, count 0 2006.173.12:25:34.27#ibcon#read 4, iclass 14, count 0 2006.173.12:25:34.27#ibcon#about to read 5, iclass 14, count 0 2006.173.12:25:34.27#ibcon#read 5, iclass 14, count 0 2006.173.12:25:34.27#ibcon#about to read 6, iclass 14, count 0 2006.173.12:25:34.27#ibcon#read 6, iclass 14, count 0 2006.173.12:25:34.27#ibcon#end of sib2, iclass 14, count 0 2006.173.12:25:34.27#ibcon#*mode == 0, iclass 14, count 0 2006.173.12:25:34.27#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.12:25:34.27#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.12:25:34.27#ibcon#*before write, iclass 14, count 0 2006.173.12:25:34.27#ibcon#enter sib2, iclass 14, count 0 2006.173.12:25:34.27#ibcon#flushed, iclass 14, count 0 2006.173.12:25:34.27#ibcon#about to write, iclass 14, count 0 2006.173.12:25:34.27#ibcon#wrote, iclass 14, count 0 2006.173.12:25:34.27#ibcon#about to read 3, iclass 14, count 0 2006.173.12:25:34.31#ibcon#read 3, iclass 14, count 0 2006.173.12:25:34.31#ibcon#about to read 4, iclass 14, count 0 2006.173.12:25:34.31#ibcon#read 4, iclass 14, count 0 2006.173.12:25:34.31#ibcon#about to read 5, iclass 14, count 0 2006.173.12:25:34.31#ibcon#read 5, iclass 14, count 0 2006.173.12:25:34.31#ibcon#about to read 6, iclass 14, count 0 2006.173.12:25:34.31#ibcon#read 6, iclass 14, count 0 2006.173.12:25:34.31#ibcon#end of sib2, iclass 14, count 0 2006.173.12:25:34.31#ibcon#*after write, iclass 14, count 0 2006.173.12:25:34.31#ibcon#*before return 0, iclass 14, count 0 2006.173.12:25:34.31#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.12:25:34.31#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.12:25:34.31#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.12:25:34.31#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.12:25:34.31$vck44/vb=8,4 2006.173.12:25:34.31#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.12:25:34.31#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.12:25:34.31#ibcon#ireg 11 cls_cnt 2 2006.173.12:25:34.31#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.12:25:34.37#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.12:25:34.37#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.12:25:34.37#ibcon#enter wrdev, iclass 16, count 2 2006.173.12:25:34.37#ibcon#first serial, iclass 16, count 2 2006.173.12:25:34.37#ibcon#enter sib2, iclass 16, count 2 2006.173.12:25:34.37#ibcon#flushed, iclass 16, count 2 2006.173.12:25:34.37#ibcon#about to write, iclass 16, count 2 2006.173.12:25:34.37#ibcon#wrote, iclass 16, count 2 2006.173.12:25:34.37#ibcon#about to read 3, iclass 16, count 2 2006.173.12:25:34.39#ibcon#read 3, iclass 16, count 2 2006.173.12:25:34.39#ibcon#about to read 4, iclass 16, count 2 2006.173.12:25:34.39#ibcon#read 4, iclass 16, count 2 2006.173.12:25:34.39#ibcon#about to read 5, iclass 16, count 2 2006.173.12:25:34.39#ibcon#read 5, iclass 16, count 2 2006.173.12:25:34.39#ibcon#about to read 6, iclass 16, count 2 2006.173.12:25:34.39#ibcon#read 6, iclass 16, count 2 2006.173.12:25:34.39#ibcon#end of sib2, iclass 16, count 2 2006.173.12:25:34.39#ibcon#*mode == 0, iclass 16, count 2 2006.173.12:25:34.39#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.12:25:34.39#ibcon#[27=AT08-04\r\n] 2006.173.12:25:34.39#ibcon#*before write, iclass 16, count 2 2006.173.12:25:34.39#ibcon#enter sib2, iclass 16, count 2 2006.173.12:25:34.39#ibcon#flushed, iclass 16, count 2 2006.173.12:25:34.39#ibcon#about to write, iclass 16, count 2 2006.173.12:25:34.39#ibcon#wrote, iclass 16, count 2 2006.173.12:25:34.39#ibcon#about to read 3, iclass 16, count 2 2006.173.12:25:34.42#ibcon#read 3, iclass 16, count 2 2006.173.12:25:34.42#ibcon#about to read 4, iclass 16, count 2 2006.173.12:25:34.42#ibcon#read 4, iclass 16, count 2 2006.173.12:25:34.42#ibcon#about to read 5, iclass 16, count 2 2006.173.12:25:34.42#ibcon#read 5, iclass 16, count 2 2006.173.12:25:34.42#ibcon#about to read 6, iclass 16, count 2 2006.173.12:25:34.42#ibcon#read 6, iclass 16, count 2 2006.173.12:25:34.42#ibcon#end of sib2, iclass 16, count 2 2006.173.12:25:34.42#ibcon#*after write, iclass 16, count 2 2006.173.12:25:34.42#ibcon#*before return 0, iclass 16, count 2 2006.173.12:25:34.42#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.12:25:34.42#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.12:25:34.42#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.12:25:34.42#ibcon#ireg 7 cls_cnt 0 2006.173.12:25:34.42#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.12:25:34.54#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.12:25:34.54#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.12:25:34.54#ibcon#enter wrdev, iclass 16, count 0 2006.173.12:25:34.54#ibcon#first serial, iclass 16, count 0 2006.173.12:25:34.54#ibcon#enter sib2, iclass 16, count 0 2006.173.12:25:34.54#ibcon#flushed, iclass 16, count 0 2006.173.12:25:34.54#ibcon#about to write, iclass 16, count 0 2006.173.12:25:34.54#ibcon#wrote, iclass 16, count 0 2006.173.12:25:34.54#ibcon#about to read 3, iclass 16, count 0 2006.173.12:25:34.56#ibcon#read 3, iclass 16, count 0 2006.173.12:25:34.56#ibcon#about to read 4, iclass 16, count 0 2006.173.12:25:34.56#ibcon#read 4, iclass 16, count 0 2006.173.12:25:34.56#ibcon#about to read 5, iclass 16, count 0 2006.173.12:25:34.56#ibcon#read 5, iclass 16, count 0 2006.173.12:25:34.56#ibcon#about to read 6, iclass 16, count 0 2006.173.12:25:34.56#ibcon#read 6, iclass 16, count 0 2006.173.12:25:34.56#ibcon#end of sib2, iclass 16, count 0 2006.173.12:25:34.56#ibcon#*mode == 0, iclass 16, count 0 2006.173.12:25:34.56#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.12:25:34.56#ibcon#[27=USB\r\n] 2006.173.12:25:34.56#ibcon#*before write, iclass 16, count 0 2006.173.12:25:34.56#ibcon#enter sib2, iclass 16, count 0 2006.173.12:25:34.56#ibcon#flushed, iclass 16, count 0 2006.173.12:25:34.56#ibcon#about to write, iclass 16, count 0 2006.173.12:25:34.56#ibcon#wrote, iclass 16, count 0 2006.173.12:25:34.56#ibcon#about to read 3, iclass 16, count 0 2006.173.12:25:34.59#ibcon#read 3, iclass 16, count 0 2006.173.12:25:34.59#ibcon#about to read 4, iclass 16, count 0 2006.173.12:25:34.59#ibcon#read 4, iclass 16, count 0 2006.173.12:25:34.59#ibcon#about to read 5, iclass 16, count 0 2006.173.12:25:34.59#ibcon#read 5, iclass 16, count 0 2006.173.12:25:34.59#ibcon#about to read 6, iclass 16, count 0 2006.173.12:25:34.59#ibcon#read 6, iclass 16, count 0 2006.173.12:25:34.59#ibcon#end of sib2, iclass 16, count 0 2006.173.12:25:34.59#ibcon#*after write, iclass 16, count 0 2006.173.12:25:34.59#ibcon#*before return 0, iclass 16, count 0 2006.173.12:25:34.59#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.12:25:34.59#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.12:25:34.59#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.12:25:34.59#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.12:25:34.59$vck44/vabw=wide 2006.173.12:25:34.59#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.12:25:34.59#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.12:25:34.59#ibcon#ireg 8 cls_cnt 0 2006.173.12:25:34.59#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.12:25:34.59#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.12:25:34.59#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.12:25:34.59#ibcon#enter wrdev, iclass 18, count 0 2006.173.12:25:34.59#ibcon#first serial, iclass 18, count 0 2006.173.12:25:34.59#ibcon#enter sib2, iclass 18, count 0 2006.173.12:25:34.59#ibcon#flushed, iclass 18, count 0 2006.173.12:25:34.59#ibcon#about to write, iclass 18, count 0 2006.173.12:25:34.59#ibcon#wrote, iclass 18, count 0 2006.173.12:25:34.59#ibcon#about to read 3, iclass 18, count 0 2006.173.12:25:34.61#ibcon#read 3, iclass 18, count 0 2006.173.12:25:34.61#ibcon#about to read 4, iclass 18, count 0 2006.173.12:25:34.61#ibcon#read 4, iclass 18, count 0 2006.173.12:25:34.61#ibcon#about to read 5, iclass 18, count 0 2006.173.12:25:34.61#ibcon#read 5, iclass 18, count 0 2006.173.12:25:34.61#ibcon#about to read 6, iclass 18, count 0 2006.173.12:25:34.61#ibcon#read 6, iclass 18, count 0 2006.173.12:25:34.61#ibcon#end of sib2, iclass 18, count 0 2006.173.12:25:34.61#ibcon#*mode == 0, iclass 18, count 0 2006.173.12:25:34.61#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.12:25:34.61#ibcon#[25=BW32\r\n] 2006.173.12:25:34.61#ibcon#*before write, iclass 18, count 0 2006.173.12:25:34.61#ibcon#enter sib2, iclass 18, count 0 2006.173.12:25:34.61#ibcon#flushed, iclass 18, count 0 2006.173.12:25:34.61#ibcon#about to write, iclass 18, count 0 2006.173.12:25:34.61#ibcon#wrote, iclass 18, count 0 2006.173.12:25:34.61#ibcon#about to read 3, iclass 18, count 0 2006.173.12:25:34.64#ibcon#read 3, iclass 18, count 0 2006.173.12:25:34.64#ibcon#about to read 4, iclass 18, count 0 2006.173.12:25:34.64#ibcon#read 4, iclass 18, count 0 2006.173.12:25:34.64#ibcon#about to read 5, iclass 18, count 0 2006.173.12:25:34.64#ibcon#read 5, iclass 18, count 0 2006.173.12:25:34.64#ibcon#about to read 6, iclass 18, count 0 2006.173.12:25:34.64#ibcon#read 6, iclass 18, count 0 2006.173.12:25:34.64#ibcon#end of sib2, iclass 18, count 0 2006.173.12:25:34.64#ibcon#*after write, iclass 18, count 0 2006.173.12:25:34.64#ibcon#*before return 0, iclass 18, count 0 2006.173.12:25:34.64#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.12:25:34.64#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.12:25:34.64#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.12:25:34.64#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.12:25:34.64$vck44/vbbw=wide 2006.173.12:25:34.64#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.12:25:34.64#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.12:25:34.64#ibcon#ireg 8 cls_cnt 0 2006.173.12:25:34.64#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.12:25:34.71#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.12:25:34.71#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.12:25:34.71#ibcon#enter wrdev, iclass 20, count 0 2006.173.12:25:34.71#ibcon#first serial, iclass 20, count 0 2006.173.12:25:34.71#ibcon#enter sib2, iclass 20, count 0 2006.173.12:25:34.71#ibcon#flushed, iclass 20, count 0 2006.173.12:25:34.71#ibcon#about to write, iclass 20, count 0 2006.173.12:25:34.71#ibcon#wrote, iclass 20, count 0 2006.173.12:25:34.71#ibcon#about to read 3, iclass 20, count 0 2006.173.12:25:34.73#ibcon#read 3, iclass 20, count 0 2006.173.12:25:34.73#ibcon#about to read 4, iclass 20, count 0 2006.173.12:25:34.73#ibcon#read 4, iclass 20, count 0 2006.173.12:25:34.73#ibcon#about to read 5, iclass 20, count 0 2006.173.12:25:34.73#ibcon#read 5, iclass 20, count 0 2006.173.12:25:34.73#ibcon#about to read 6, iclass 20, count 0 2006.173.12:25:34.73#ibcon#read 6, iclass 20, count 0 2006.173.12:25:34.73#ibcon#end of sib2, iclass 20, count 0 2006.173.12:25:34.73#ibcon#*mode == 0, iclass 20, count 0 2006.173.12:25:34.73#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.12:25:34.73#ibcon#[27=BW32\r\n] 2006.173.12:25:34.73#ibcon#*before write, iclass 20, count 0 2006.173.12:25:34.73#ibcon#enter sib2, iclass 20, count 0 2006.173.12:25:34.73#ibcon#flushed, iclass 20, count 0 2006.173.12:25:34.73#ibcon#about to write, iclass 20, count 0 2006.173.12:25:34.73#ibcon#wrote, iclass 20, count 0 2006.173.12:25:34.73#ibcon#about to read 3, iclass 20, count 0 2006.173.12:25:34.76#ibcon#read 3, iclass 20, count 0 2006.173.12:25:34.76#ibcon#about to read 4, iclass 20, count 0 2006.173.12:25:34.76#ibcon#read 4, iclass 20, count 0 2006.173.12:25:34.76#ibcon#about to read 5, iclass 20, count 0 2006.173.12:25:34.76#ibcon#read 5, iclass 20, count 0 2006.173.12:25:34.76#ibcon#about to read 6, iclass 20, count 0 2006.173.12:25:34.76#ibcon#read 6, iclass 20, count 0 2006.173.12:25:34.76#ibcon#end of sib2, iclass 20, count 0 2006.173.12:25:34.76#ibcon#*after write, iclass 20, count 0 2006.173.12:25:34.76#ibcon#*before return 0, iclass 20, count 0 2006.173.12:25:34.76#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.12:25:34.76#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.12:25:34.76#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.12:25:34.76#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.12:25:34.76$setupk4/ifdk4 2006.173.12:25:34.76$ifdk4/lo= 2006.173.12:25:34.76$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.12:25:34.76$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.12:25:34.76$ifdk4/patch= 2006.173.12:25:34.76$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.12:25:34.76$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.12:25:34.76$setupk4/!*+20s 2006.173.12:25:34.90#abcon#<5=/04 0.8 1.9 22.15 951004.4\r\n> 2006.173.12:25:34.92#abcon#{5=INTERFACE CLEAR} 2006.173.12:25:34.98#abcon#[5=S1D000X0/0*\r\n] 2006.173.12:25:45.07#abcon#<5=/04 0.8 1.9 22.15 951004.5\r\n> 2006.173.12:25:45.09#abcon#{5=INTERFACE CLEAR} 2006.173.12:25:45.15#abcon#[5=S1D000X0/0*\r\n] 2006.173.12:25:49.27$setupk4/"tpicd 2006.173.12:25:49.27$setupk4/echo=off 2006.173.12:25:49.27$setupk4/xlog=off 2006.173.12:25:49.27:!2006.173.12:32:47 2006.173.12:25:58.14#trakl#Source acquired 2006.173.12:26:00.14#flagr#flagr/antenna,acquired 2006.173.12:32:47.00:preob 2006.173.12:32:47.14/onsource/TRACKING 2006.173.12:32:47.14:!2006.173.12:32:57 2006.173.12:32:57.00:"tape 2006.173.12:32:57.00:"st=record 2006.173.12:32:57.00:data_valid=on 2006.173.12:32:57.00:midob 2006.173.12:32:57.14/onsource/TRACKING 2006.173.12:32:57.14/wx/22.11,1004.5,95 2006.173.12:32:57.33/cable/+6.5027E-03 2006.173.12:32:58.42/va/01,07,usb,yes,36,39 2006.173.12:32:58.42/va/02,06,usb,yes,36,37 2006.173.12:32:58.42/va/03,05,usb,yes,46,48 2006.173.12:32:58.42/va/04,06,usb,yes,37,39 2006.173.12:32:58.42/va/05,04,usb,yes,29,29 2006.173.12:32:58.42/va/06,03,usb,yes,40,40 2006.173.12:32:58.42/va/07,04,usb,yes,33,34 2006.173.12:32:58.42/va/08,04,usb,yes,28,34 2006.173.12:32:58.65/valo/01,524.99,yes,locked 2006.173.12:32:58.65/valo/02,534.99,yes,locked 2006.173.12:32:58.65/valo/03,564.99,yes,locked 2006.173.12:32:58.65/valo/04,624.99,yes,locked 2006.173.12:32:58.65/valo/05,734.99,yes,locked 2006.173.12:32:58.65/valo/06,814.99,yes,locked 2006.173.12:32:58.65/valo/07,864.99,yes,locked 2006.173.12:32:58.65/valo/08,884.99,yes,locked 2006.173.12:32:59.74/vb/01,04,usb,yes,29,27 2006.173.12:32:59.74/vb/02,04,usb,yes,31,31 2006.173.12:32:59.74/vb/03,04,usb,yes,28,31 2006.173.12:32:59.74/vb/04,04,usb,yes,33,32 2006.173.12:32:59.74/vb/05,04,usb,yes,25,28 2006.173.12:32:59.74/vb/06,04,usb,yes,30,26 2006.173.12:32:59.74/vb/07,04,usb,yes,30,29 2006.173.12:32:59.74/vb/08,04,usb,yes,27,31 2006.173.12:32:59.97/vblo/01,629.99,yes,locked 2006.173.12:32:59.97/vblo/02,634.99,yes,locked 2006.173.12:32:59.97/vblo/03,649.99,yes,locked 2006.173.12:32:59.97/vblo/04,679.99,yes,locked 2006.173.12:32:59.97/vblo/05,709.99,yes,locked 2006.173.12:32:59.97/vblo/06,719.99,yes,locked 2006.173.12:32:59.97/vblo/07,734.99,yes,locked 2006.173.12:32:59.97/vblo/08,744.99,yes,locked 2006.173.12:33:00.12/vabw/8 2006.173.12:33:00.27/vbbw/8 2006.173.12:33:00.36/xfe/off,on,15.0 2006.173.12:33:00.75/ifatt/23,28,28,28 2006.173.12:33:01.07/fmout-gps/S +3.94E-07 2006.173.12:33:01.11:!2006.173.12:36:47 2006.173.12:36:47.00:data_valid=off 2006.173.12:36:47.00:"et 2006.173.12:36:47.00:!+3s 2006.173.12:36:50.01:"tape 2006.173.12:36:50.01:postob 2006.173.12:36:50.24/cable/+6.5030E-03 2006.173.12:36:50.24/wx/22.10,1004.4,95 2006.173.12:36:51.07/fmout-gps/S +3.94E-07 2006.173.12:36:51.07:scan_name=173-1240,jd0606,410 2006.173.12:36:51.07:source=1418+546,141946.60,542314.8,2000.0,cw 2006.173.12:36:52.14#flagr#flagr/antenna,new-source 2006.173.12:36:52.14:checkk5 2006.173.12:36:52.56/chk_autoobs//k5ts1/ autoobs is running! 2006.173.12:36:52.97/chk_autoobs//k5ts2/ autoobs is running! 2006.173.12:36:53.39/chk_autoobs//k5ts3/ autoobs is running! 2006.173.12:36:53.78/chk_autoobs//k5ts4/ autoobs is running! 2006.173.12:36:54.18/chk_obsdata//k5ts1/T1731232??a.dat file size is correct (nominal:920MB, actual:920MB). 2006.173.12:36:54.58/chk_obsdata//k5ts2/T1731232??b.dat file size is correct (nominal:920MB, actual:920MB). 2006.173.12:36:54.99/chk_obsdata//k5ts3/T1731232??c.dat file size is correct (nominal:920MB, actual:920MB). 2006.173.12:36:55.38/chk_obsdata//k5ts4/T1731232??d.dat file size is correct (nominal:920MB, actual:920MB). 2006.173.12:36:56.12/k5log//k5ts1_log_newline 2006.173.12:36:56.81/k5log//k5ts2_log_newline 2006.173.12:36:57.54/k5log//k5ts3_log_newline 2006.173.12:36:58.24/k5log//k5ts4_log_newline 2006.173.12:36:58.27/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.12:36:58.27:setupk4=1 2006.173.12:36:58.27$setupk4/echo=on 2006.173.12:36:58.27$setupk4/pcalon 2006.173.12:36:58.27$pcalon/"no phase cal control is implemented here 2006.173.12:36:58.27$setupk4/"tpicd=stop 2006.173.12:36:58.27$setupk4/"rec=synch_on 2006.173.12:36:58.27$setupk4/"rec_mode=128 2006.173.12:36:58.27$setupk4/!* 2006.173.12:36:58.27$setupk4/recpk4 2006.173.12:36:58.27$recpk4/recpatch= 2006.173.12:36:58.28$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.12:36:58.28$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.12:36:58.28$setupk4/vck44 2006.173.12:36:58.28$vck44/valo=1,524.99 2006.173.12:36:58.28#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.12:36:58.28#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.12:36:58.28#ibcon#ireg 17 cls_cnt 0 2006.173.12:36:58.28#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.12:36:58.28#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.12:36:58.28#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.12:36:58.28#ibcon#enter wrdev, iclass 7, count 0 2006.173.12:36:58.28#ibcon#first serial, iclass 7, count 0 2006.173.12:36:58.28#ibcon#enter sib2, iclass 7, count 0 2006.173.12:36:58.28#ibcon#flushed, iclass 7, count 0 2006.173.12:36:58.28#ibcon#about to write, iclass 7, count 0 2006.173.12:36:58.28#ibcon#wrote, iclass 7, count 0 2006.173.12:36:58.28#ibcon#about to read 3, iclass 7, count 0 2006.173.12:36:58.30#ibcon#read 3, iclass 7, count 0 2006.173.12:36:58.30#ibcon#about to read 4, iclass 7, count 0 2006.173.12:36:58.30#ibcon#read 4, iclass 7, count 0 2006.173.12:36:58.30#ibcon#about to read 5, iclass 7, count 0 2006.173.12:36:58.30#ibcon#read 5, iclass 7, count 0 2006.173.12:36:58.30#ibcon#about to read 6, iclass 7, count 0 2006.173.12:36:58.30#ibcon#read 6, iclass 7, count 0 2006.173.12:36:58.30#ibcon#end of sib2, iclass 7, count 0 2006.173.12:36:58.30#ibcon#*mode == 0, iclass 7, count 0 2006.173.12:36:58.30#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.12:36:58.30#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.12:36:58.30#ibcon#*before write, iclass 7, count 0 2006.173.12:36:58.30#ibcon#enter sib2, iclass 7, count 0 2006.173.12:36:58.30#ibcon#flushed, iclass 7, count 0 2006.173.12:36:58.30#ibcon#about to write, iclass 7, count 0 2006.173.12:36:58.30#ibcon#wrote, iclass 7, count 0 2006.173.12:36:58.30#ibcon#about to read 3, iclass 7, count 0 2006.173.12:36:58.35#ibcon#read 3, iclass 7, count 0 2006.173.12:36:58.35#ibcon#about to read 4, iclass 7, count 0 2006.173.12:36:58.35#ibcon#read 4, iclass 7, count 0 2006.173.12:36:58.35#ibcon#about to read 5, iclass 7, count 0 2006.173.12:36:58.35#ibcon#read 5, iclass 7, count 0 2006.173.12:36:58.35#ibcon#about to read 6, iclass 7, count 0 2006.173.12:36:58.35#ibcon#read 6, iclass 7, count 0 2006.173.12:36:58.35#ibcon#end of sib2, iclass 7, count 0 2006.173.12:36:58.35#ibcon#*after write, iclass 7, count 0 2006.173.12:36:58.35#ibcon#*before return 0, iclass 7, count 0 2006.173.12:36:58.35#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.12:36:58.35#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.12:36:58.35#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.12:36:58.35#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.12:36:58.35$vck44/va=1,7 2006.173.12:36:58.35#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.12:36:58.35#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.12:36:58.35#ibcon#ireg 11 cls_cnt 2 2006.173.12:36:58.35#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.12:36:58.35#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.12:36:58.35#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.12:36:58.35#ibcon#enter wrdev, iclass 11, count 2 2006.173.12:36:58.35#ibcon#first serial, iclass 11, count 2 2006.173.12:36:58.35#ibcon#enter sib2, iclass 11, count 2 2006.173.12:36:58.35#ibcon#flushed, iclass 11, count 2 2006.173.12:36:58.35#ibcon#about to write, iclass 11, count 2 2006.173.12:36:58.35#ibcon#wrote, iclass 11, count 2 2006.173.12:36:58.35#ibcon#about to read 3, iclass 11, count 2 2006.173.12:36:58.37#ibcon#read 3, iclass 11, count 2 2006.173.12:36:58.37#ibcon#about to read 4, iclass 11, count 2 2006.173.12:36:58.37#ibcon#read 4, iclass 11, count 2 2006.173.12:36:58.37#ibcon#about to read 5, iclass 11, count 2 2006.173.12:36:58.37#ibcon#read 5, iclass 11, count 2 2006.173.12:36:58.37#ibcon#about to read 6, iclass 11, count 2 2006.173.12:36:58.37#ibcon#read 6, iclass 11, count 2 2006.173.12:36:58.37#ibcon#end of sib2, iclass 11, count 2 2006.173.12:36:58.37#ibcon#*mode == 0, iclass 11, count 2 2006.173.12:36:58.37#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.12:36:58.37#ibcon#[25=AT01-07\r\n] 2006.173.12:36:58.37#ibcon#*before write, iclass 11, count 2 2006.173.12:36:58.37#ibcon#enter sib2, iclass 11, count 2 2006.173.12:36:58.37#ibcon#flushed, iclass 11, count 2 2006.173.12:36:58.37#ibcon#about to write, iclass 11, count 2 2006.173.12:36:58.37#ibcon#wrote, iclass 11, count 2 2006.173.12:36:58.37#ibcon#about to read 3, iclass 11, count 2 2006.173.12:36:58.40#ibcon#read 3, iclass 11, count 2 2006.173.12:36:58.40#ibcon#about to read 4, iclass 11, count 2 2006.173.12:36:58.40#ibcon#read 4, iclass 11, count 2 2006.173.12:36:58.40#ibcon#about to read 5, iclass 11, count 2 2006.173.12:36:58.40#ibcon#read 5, iclass 11, count 2 2006.173.12:36:58.40#ibcon#about to read 6, iclass 11, count 2 2006.173.12:36:58.40#ibcon#read 6, iclass 11, count 2 2006.173.12:36:58.40#ibcon#end of sib2, iclass 11, count 2 2006.173.12:36:58.40#ibcon#*after write, iclass 11, count 2 2006.173.12:36:58.40#ibcon#*before return 0, iclass 11, count 2 2006.173.12:36:58.40#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.12:36:58.40#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.12:36:58.40#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.12:36:58.40#ibcon#ireg 7 cls_cnt 0 2006.173.12:36:58.40#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.12:36:58.52#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.12:36:58.52#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.12:36:58.52#ibcon#enter wrdev, iclass 11, count 0 2006.173.12:36:58.52#ibcon#first serial, iclass 11, count 0 2006.173.12:36:58.52#ibcon#enter sib2, iclass 11, count 0 2006.173.12:36:58.52#ibcon#flushed, iclass 11, count 0 2006.173.12:36:58.52#ibcon#about to write, iclass 11, count 0 2006.173.12:36:58.52#ibcon#wrote, iclass 11, count 0 2006.173.12:36:58.52#ibcon#about to read 3, iclass 11, count 0 2006.173.12:36:58.54#ibcon#read 3, iclass 11, count 0 2006.173.12:36:58.54#ibcon#about to read 4, iclass 11, count 0 2006.173.12:36:58.54#ibcon#read 4, iclass 11, count 0 2006.173.12:36:58.54#ibcon#about to read 5, iclass 11, count 0 2006.173.12:36:58.54#ibcon#read 5, iclass 11, count 0 2006.173.12:36:58.54#ibcon#about to read 6, iclass 11, count 0 2006.173.12:36:58.54#ibcon#read 6, iclass 11, count 0 2006.173.12:36:58.54#ibcon#end of sib2, iclass 11, count 0 2006.173.12:36:58.54#ibcon#*mode == 0, iclass 11, count 0 2006.173.12:36:58.54#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.12:36:58.54#ibcon#[25=USB\r\n] 2006.173.12:36:58.54#ibcon#*before write, iclass 11, count 0 2006.173.12:36:58.54#ibcon#enter sib2, iclass 11, count 0 2006.173.12:36:58.54#ibcon#flushed, iclass 11, count 0 2006.173.12:36:58.54#ibcon#about to write, iclass 11, count 0 2006.173.12:36:58.54#ibcon#wrote, iclass 11, count 0 2006.173.12:36:58.54#ibcon#about to read 3, iclass 11, count 0 2006.173.12:36:58.57#ibcon#read 3, iclass 11, count 0 2006.173.12:36:58.57#ibcon#about to read 4, iclass 11, count 0 2006.173.12:36:58.57#ibcon#read 4, iclass 11, count 0 2006.173.12:36:58.57#ibcon#about to read 5, iclass 11, count 0 2006.173.12:36:58.57#ibcon#read 5, iclass 11, count 0 2006.173.12:36:58.57#ibcon#about to read 6, iclass 11, count 0 2006.173.12:36:58.57#ibcon#read 6, iclass 11, count 0 2006.173.12:36:58.57#ibcon#end of sib2, iclass 11, count 0 2006.173.12:36:58.57#ibcon#*after write, iclass 11, count 0 2006.173.12:36:58.57#ibcon#*before return 0, iclass 11, count 0 2006.173.12:36:58.57#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.12:36:58.57#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.12:36:58.57#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.12:36:58.57#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.12:36:58.57$vck44/valo=2,534.99 2006.173.12:36:58.57#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.12:36:58.57#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.12:36:58.57#ibcon#ireg 17 cls_cnt 0 2006.173.12:36:58.57#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.12:36:58.57#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.12:36:58.57#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.12:36:58.57#ibcon#enter wrdev, iclass 13, count 0 2006.173.12:36:58.57#ibcon#first serial, iclass 13, count 0 2006.173.12:36:58.57#ibcon#enter sib2, iclass 13, count 0 2006.173.12:36:58.57#ibcon#flushed, iclass 13, count 0 2006.173.12:36:58.57#ibcon#about to write, iclass 13, count 0 2006.173.12:36:58.57#ibcon#wrote, iclass 13, count 0 2006.173.12:36:58.57#ibcon#about to read 3, iclass 13, count 0 2006.173.12:36:58.59#ibcon#read 3, iclass 13, count 0 2006.173.12:36:58.59#ibcon#about to read 4, iclass 13, count 0 2006.173.12:36:58.59#ibcon#read 4, iclass 13, count 0 2006.173.12:36:58.59#ibcon#about to read 5, iclass 13, count 0 2006.173.12:36:58.59#ibcon#read 5, iclass 13, count 0 2006.173.12:36:58.59#ibcon#about to read 6, iclass 13, count 0 2006.173.12:36:58.59#ibcon#read 6, iclass 13, count 0 2006.173.12:36:58.59#ibcon#end of sib2, iclass 13, count 0 2006.173.12:36:58.59#ibcon#*mode == 0, iclass 13, count 0 2006.173.12:36:58.59#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.12:36:58.59#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.12:36:58.59#ibcon#*before write, iclass 13, count 0 2006.173.12:36:58.59#ibcon#enter sib2, iclass 13, count 0 2006.173.12:36:58.59#ibcon#flushed, iclass 13, count 0 2006.173.12:36:58.59#ibcon#about to write, iclass 13, count 0 2006.173.12:36:58.59#ibcon#wrote, iclass 13, count 0 2006.173.12:36:58.59#ibcon#about to read 3, iclass 13, count 0 2006.173.12:36:58.63#ibcon#read 3, iclass 13, count 0 2006.173.12:36:58.63#ibcon#about to read 4, iclass 13, count 0 2006.173.12:36:58.63#ibcon#read 4, iclass 13, count 0 2006.173.12:36:58.63#ibcon#about to read 5, iclass 13, count 0 2006.173.12:36:58.63#ibcon#read 5, iclass 13, count 0 2006.173.12:36:58.63#ibcon#about to read 6, iclass 13, count 0 2006.173.12:36:58.63#ibcon#read 6, iclass 13, count 0 2006.173.12:36:58.63#ibcon#end of sib2, iclass 13, count 0 2006.173.12:36:58.63#ibcon#*after write, iclass 13, count 0 2006.173.12:36:58.63#ibcon#*before return 0, iclass 13, count 0 2006.173.12:36:58.63#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.12:36:58.63#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.12:36:58.63#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.12:36:58.63#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.12:36:58.63$vck44/va=2,6 2006.173.12:36:58.63#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.12:36:58.63#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.12:36:58.63#ibcon#ireg 11 cls_cnt 2 2006.173.12:36:58.63#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.12:36:58.69#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.12:36:58.69#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.12:36:58.69#ibcon#enter wrdev, iclass 15, count 2 2006.173.12:36:58.69#ibcon#first serial, iclass 15, count 2 2006.173.12:36:58.69#ibcon#enter sib2, iclass 15, count 2 2006.173.12:36:58.69#ibcon#flushed, iclass 15, count 2 2006.173.12:36:58.69#ibcon#about to write, iclass 15, count 2 2006.173.12:36:58.69#ibcon#wrote, iclass 15, count 2 2006.173.12:36:58.69#ibcon#about to read 3, iclass 15, count 2 2006.173.12:36:58.71#ibcon#read 3, iclass 15, count 2 2006.173.12:36:58.71#ibcon#about to read 4, iclass 15, count 2 2006.173.12:36:58.71#ibcon#read 4, iclass 15, count 2 2006.173.12:36:58.71#ibcon#about to read 5, iclass 15, count 2 2006.173.12:36:58.71#ibcon#read 5, iclass 15, count 2 2006.173.12:36:58.71#ibcon#about to read 6, iclass 15, count 2 2006.173.12:36:58.71#ibcon#read 6, iclass 15, count 2 2006.173.12:36:58.71#ibcon#end of sib2, iclass 15, count 2 2006.173.12:36:58.71#ibcon#*mode == 0, iclass 15, count 2 2006.173.12:36:58.71#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.12:36:58.71#ibcon#[25=AT02-06\r\n] 2006.173.12:36:58.71#ibcon#*before write, iclass 15, count 2 2006.173.12:36:58.71#ibcon#enter sib2, iclass 15, count 2 2006.173.12:36:58.71#ibcon#flushed, iclass 15, count 2 2006.173.12:36:58.71#ibcon#about to write, iclass 15, count 2 2006.173.12:36:58.71#ibcon#wrote, iclass 15, count 2 2006.173.12:36:58.71#ibcon#about to read 3, iclass 15, count 2 2006.173.12:36:58.74#ibcon#read 3, iclass 15, count 2 2006.173.12:36:58.74#ibcon#about to read 4, iclass 15, count 2 2006.173.12:36:58.74#ibcon#read 4, iclass 15, count 2 2006.173.12:36:58.74#ibcon#about to read 5, iclass 15, count 2 2006.173.12:36:58.74#ibcon#read 5, iclass 15, count 2 2006.173.12:36:58.74#ibcon#about to read 6, iclass 15, count 2 2006.173.12:36:58.74#ibcon#read 6, iclass 15, count 2 2006.173.12:36:58.74#ibcon#end of sib2, iclass 15, count 2 2006.173.12:36:58.74#ibcon#*after write, iclass 15, count 2 2006.173.12:36:58.74#ibcon#*before return 0, iclass 15, count 2 2006.173.12:36:58.74#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.12:36:58.74#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.12:36:58.74#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.12:36:58.74#ibcon#ireg 7 cls_cnt 0 2006.173.12:36:58.74#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.12:36:58.86#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.12:36:58.86#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.12:36:58.86#ibcon#enter wrdev, iclass 15, count 0 2006.173.12:36:58.86#ibcon#first serial, iclass 15, count 0 2006.173.12:36:58.86#ibcon#enter sib2, iclass 15, count 0 2006.173.12:36:58.86#ibcon#flushed, iclass 15, count 0 2006.173.12:36:58.86#ibcon#about to write, iclass 15, count 0 2006.173.12:36:58.86#ibcon#wrote, iclass 15, count 0 2006.173.12:36:58.86#ibcon#about to read 3, iclass 15, count 0 2006.173.12:36:58.88#ibcon#read 3, iclass 15, count 0 2006.173.12:36:58.88#ibcon#about to read 4, iclass 15, count 0 2006.173.12:36:58.88#ibcon#read 4, iclass 15, count 0 2006.173.12:36:58.88#ibcon#about to read 5, iclass 15, count 0 2006.173.12:36:58.88#ibcon#read 5, iclass 15, count 0 2006.173.12:36:58.88#ibcon#about to read 6, iclass 15, count 0 2006.173.12:36:58.88#ibcon#read 6, iclass 15, count 0 2006.173.12:36:58.88#ibcon#end of sib2, iclass 15, count 0 2006.173.12:36:58.88#ibcon#*mode == 0, iclass 15, count 0 2006.173.12:36:58.88#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.12:36:58.88#ibcon#[25=USB\r\n] 2006.173.12:36:58.88#ibcon#*before write, iclass 15, count 0 2006.173.12:36:58.88#ibcon#enter sib2, iclass 15, count 0 2006.173.12:36:58.88#ibcon#flushed, iclass 15, count 0 2006.173.12:36:58.88#ibcon#about to write, iclass 15, count 0 2006.173.12:36:58.88#ibcon#wrote, iclass 15, count 0 2006.173.12:36:58.88#ibcon#about to read 3, iclass 15, count 0 2006.173.12:36:58.91#ibcon#read 3, iclass 15, count 0 2006.173.12:36:58.91#ibcon#about to read 4, iclass 15, count 0 2006.173.12:36:58.91#ibcon#read 4, iclass 15, count 0 2006.173.12:36:58.91#ibcon#about to read 5, iclass 15, count 0 2006.173.12:36:58.91#ibcon#read 5, iclass 15, count 0 2006.173.12:36:58.91#ibcon#about to read 6, iclass 15, count 0 2006.173.12:36:58.91#ibcon#read 6, iclass 15, count 0 2006.173.12:36:58.91#ibcon#end of sib2, iclass 15, count 0 2006.173.12:36:58.91#ibcon#*after write, iclass 15, count 0 2006.173.12:36:58.91#ibcon#*before return 0, iclass 15, count 0 2006.173.12:36:58.91#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.12:36:58.91#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.12:36:58.91#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.12:36:58.91#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.12:36:58.91$vck44/valo=3,564.99 2006.173.12:36:58.91#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.12:36:58.91#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.12:36:58.91#ibcon#ireg 17 cls_cnt 0 2006.173.12:36:58.91#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.12:36:58.91#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.12:36:58.91#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.12:36:58.91#ibcon#enter wrdev, iclass 17, count 0 2006.173.12:36:58.91#ibcon#first serial, iclass 17, count 0 2006.173.12:36:58.91#ibcon#enter sib2, iclass 17, count 0 2006.173.12:36:58.91#ibcon#flushed, iclass 17, count 0 2006.173.12:36:58.91#ibcon#about to write, iclass 17, count 0 2006.173.12:36:58.91#ibcon#wrote, iclass 17, count 0 2006.173.12:36:58.91#ibcon#about to read 3, iclass 17, count 0 2006.173.12:36:58.93#ibcon#read 3, iclass 17, count 0 2006.173.12:36:58.93#ibcon#about to read 4, iclass 17, count 0 2006.173.12:36:58.93#ibcon#read 4, iclass 17, count 0 2006.173.12:36:58.93#ibcon#about to read 5, iclass 17, count 0 2006.173.12:36:58.93#ibcon#read 5, iclass 17, count 0 2006.173.12:36:58.93#ibcon#about to read 6, iclass 17, count 0 2006.173.12:36:58.93#ibcon#read 6, iclass 17, count 0 2006.173.12:36:58.93#ibcon#end of sib2, iclass 17, count 0 2006.173.12:36:58.93#ibcon#*mode == 0, iclass 17, count 0 2006.173.12:36:58.93#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.12:36:58.93#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.12:36:58.93#ibcon#*before write, iclass 17, count 0 2006.173.12:36:58.93#ibcon#enter sib2, iclass 17, count 0 2006.173.12:36:58.93#ibcon#flushed, iclass 17, count 0 2006.173.12:36:58.93#ibcon#about to write, iclass 17, count 0 2006.173.12:36:58.93#ibcon#wrote, iclass 17, count 0 2006.173.12:36:58.93#ibcon#about to read 3, iclass 17, count 0 2006.173.12:36:58.97#ibcon#read 3, iclass 17, count 0 2006.173.12:36:58.97#ibcon#about to read 4, iclass 17, count 0 2006.173.12:36:58.97#ibcon#read 4, iclass 17, count 0 2006.173.12:36:58.97#ibcon#about to read 5, iclass 17, count 0 2006.173.12:36:58.97#ibcon#read 5, iclass 17, count 0 2006.173.12:36:58.97#ibcon#about to read 6, iclass 17, count 0 2006.173.12:36:58.97#ibcon#read 6, iclass 17, count 0 2006.173.12:36:58.97#ibcon#end of sib2, iclass 17, count 0 2006.173.12:36:58.97#ibcon#*after write, iclass 17, count 0 2006.173.12:36:58.97#ibcon#*before return 0, iclass 17, count 0 2006.173.12:36:58.97#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.12:36:58.97#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.12:36:58.97#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.12:36:58.97#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.12:36:58.97$vck44/va=3,5 2006.173.12:36:58.97#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.12:36:58.97#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.12:36:58.97#ibcon#ireg 11 cls_cnt 2 2006.173.12:36:58.97#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.12:36:59.03#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.12:36:59.03#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.12:36:59.03#ibcon#enter wrdev, iclass 19, count 2 2006.173.12:36:59.03#ibcon#first serial, iclass 19, count 2 2006.173.12:36:59.03#ibcon#enter sib2, iclass 19, count 2 2006.173.12:36:59.03#ibcon#flushed, iclass 19, count 2 2006.173.12:36:59.03#ibcon#about to write, iclass 19, count 2 2006.173.12:36:59.03#ibcon#wrote, iclass 19, count 2 2006.173.12:36:59.03#ibcon#about to read 3, iclass 19, count 2 2006.173.12:36:59.05#ibcon#read 3, iclass 19, count 2 2006.173.12:36:59.05#ibcon#about to read 4, iclass 19, count 2 2006.173.12:36:59.05#ibcon#read 4, iclass 19, count 2 2006.173.12:36:59.05#ibcon#about to read 5, iclass 19, count 2 2006.173.12:36:59.05#ibcon#read 5, iclass 19, count 2 2006.173.12:36:59.05#ibcon#about to read 6, iclass 19, count 2 2006.173.12:36:59.05#ibcon#read 6, iclass 19, count 2 2006.173.12:36:59.05#ibcon#end of sib2, iclass 19, count 2 2006.173.12:36:59.05#ibcon#*mode == 0, iclass 19, count 2 2006.173.12:36:59.05#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.12:36:59.05#ibcon#[25=AT03-05\r\n] 2006.173.12:36:59.05#ibcon#*before write, iclass 19, count 2 2006.173.12:36:59.05#ibcon#enter sib2, iclass 19, count 2 2006.173.12:36:59.05#ibcon#flushed, iclass 19, count 2 2006.173.12:36:59.05#ibcon#about to write, iclass 19, count 2 2006.173.12:36:59.05#ibcon#wrote, iclass 19, count 2 2006.173.12:36:59.05#ibcon#about to read 3, iclass 19, count 2 2006.173.12:36:59.08#ibcon#read 3, iclass 19, count 2 2006.173.12:36:59.08#ibcon#about to read 4, iclass 19, count 2 2006.173.12:36:59.08#ibcon#read 4, iclass 19, count 2 2006.173.12:36:59.08#ibcon#about to read 5, iclass 19, count 2 2006.173.12:36:59.08#ibcon#read 5, iclass 19, count 2 2006.173.12:36:59.08#ibcon#about to read 6, iclass 19, count 2 2006.173.12:36:59.08#ibcon#read 6, iclass 19, count 2 2006.173.12:36:59.08#ibcon#end of sib2, iclass 19, count 2 2006.173.12:36:59.08#ibcon#*after write, iclass 19, count 2 2006.173.12:36:59.08#ibcon#*before return 0, iclass 19, count 2 2006.173.12:36:59.08#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.12:36:59.08#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.12:36:59.08#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.12:36:59.08#ibcon#ireg 7 cls_cnt 0 2006.173.12:36:59.08#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.12:36:59.20#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.12:36:59.20#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.12:36:59.20#ibcon#enter wrdev, iclass 19, count 0 2006.173.12:36:59.20#ibcon#first serial, iclass 19, count 0 2006.173.12:36:59.20#ibcon#enter sib2, iclass 19, count 0 2006.173.12:36:59.20#ibcon#flushed, iclass 19, count 0 2006.173.12:36:59.20#ibcon#about to write, iclass 19, count 0 2006.173.12:36:59.20#ibcon#wrote, iclass 19, count 0 2006.173.12:36:59.20#ibcon#about to read 3, iclass 19, count 0 2006.173.12:36:59.22#ibcon#read 3, iclass 19, count 0 2006.173.12:36:59.22#ibcon#about to read 4, iclass 19, count 0 2006.173.12:36:59.22#ibcon#read 4, iclass 19, count 0 2006.173.12:36:59.22#ibcon#about to read 5, iclass 19, count 0 2006.173.12:36:59.22#ibcon#read 5, iclass 19, count 0 2006.173.12:36:59.22#ibcon#about to read 6, iclass 19, count 0 2006.173.12:36:59.22#ibcon#read 6, iclass 19, count 0 2006.173.12:36:59.22#ibcon#end of sib2, iclass 19, count 0 2006.173.12:36:59.22#ibcon#*mode == 0, iclass 19, count 0 2006.173.12:36:59.22#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.12:36:59.22#ibcon#[25=USB\r\n] 2006.173.12:36:59.22#ibcon#*before write, iclass 19, count 0 2006.173.12:36:59.22#ibcon#enter sib2, iclass 19, count 0 2006.173.12:36:59.22#ibcon#flushed, iclass 19, count 0 2006.173.12:36:59.22#ibcon#about to write, iclass 19, count 0 2006.173.12:36:59.22#ibcon#wrote, iclass 19, count 0 2006.173.12:36:59.22#ibcon#about to read 3, iclass 19, count 0 2006.173.12:36:59.25#ibcon#read 3, iclass 19, count 0 2006.173.12:36:59.25#ibcon#about to read 4, iclass 19, count 0 2006.173.12:36:59.25#ibcon#read 4, iclass 19, count 0 2006.173.12:36:59.25#ibcon#about to read 5, iclass 19, count 0 2006.173.12:36:59.25#ibcon#read 5, iclass 19, count 0 2006.173.12:36:59.25#ibcon#about to read 6, iclass 19, count 0 2006.173.12:36:59.25#ibcon#read 6, iclass 19, count 0 2006.173.12:36:59.25#ibcon#end of sib2, iclass 19, count 0 2006.173.12:36:59.25#ibcon#*after write, iclass 19, count 0 2006.173.12:36:59.25#ibcon#*before return 0, iclass 19, count 0 2006.173.12:36:59.25#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.12:36:59.25#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.12:36:59.25#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.12:36:59.25#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.12:36:59.25$vck44/valo=4,624.99 2006.173.12:36:59.25#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.12:36:59.25#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.12:36:59.25#ibcon#ireg 17 cls_cnt 0 2006.173.12:36:59.25#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.12:36:59.25#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.12:36:59.25#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.12:36:59.25#ibcon#enter wrdev, iclass 21, count 0 2006.173.12:36:59.25#ibcon#first serial, iclass 21, count 0 2006.173.12:36:59.25#ibcon#enter sib2, iclass 21, count 0 2006.173.12:36:59.25#ibcon#flushed, iclass 21, count 0 2006.173.12:36:59.25#ibcon#about to write, iclass 21, count 0 2006.173.12:36:59.25#ibcon#wrote, iclass 21, count 0 2006.173.12:36:59.25#ibcon#about to read 3, iclass 21, count 0 2006.173.12:36:59.27#ibcon#read 3, iclass 21, count 0 2006.173.12:36:59.27#ibcon#about to read 4, iclass 21, count 0 2006.173.12:36:59.27#ibcon#read 4, iclass 21, count 0 2006.173.12:36:59.27#ibcon#about to read 5, iclass 21, count 0 2006.173.12:36:59.27#ibcon#read 5, iclass 21, count 0 2006.173.12:36:59.27#ibcon#about to read 6, iclass 21, count 0 2006.173.12:36:59.27#ibcon#read 6, iclass 21, count 0 2006.173.12:36:59.27#ibcon#end of sib2, iclass 21, count 0 2006.173.12:36:59.27#ibcon#*mode == 0, iclass 21, count 0 2006.173.12:36:59.27#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.12:36:59.27#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.12:36:59.27#ibcon#*before write, iclass 21, count 0 2006.173.12:36:59.27#ibcon#enter sib2, iclass 21, count 0 2006.173.12:36:59.27#ibcon#flushed, iclass 21, count 0 2006.173.12:36:59.27#ibcon#about to write, iclass 21, count 0 2006.173.12:36:59.27#ibcon#wrote, iclass 21, count 0 2006.173.12:36:59.27#ibcon#about to read 3, iclass 21, count 0 2006.173.12:36:59.31#ibcon#read 3, iclass 21, count 0 2006.173.12:36:59.31#ibcon#about to read 4, iclass 21, count 0 2006.173.12:36:59.31#ibcon#read 4, iclass 21, count 0 2006.173.12:36:59.31#ibcon#about to read 5, iclass 21, count 0 2006.173.12:36:59.31#ibcon#read 5, iclass 21, count 0 2006.173.12:36:59.31#ibcon#about to read 6, iclass 21, count 0 2006.173.12:36:59.31#ibcon#read 6, iclass 21, count 0 2006.173.12:36:59.31#ibcon#end of sib2, iclass 21, count 0 2006.173.12:36:59.31#ibcon#*after write, iclass 21, count 0 2006.173.12:36:59.31#ibcon#*before return 0, iclass 21, count 0 2006.173.12:36:59.31#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.12:36:59.31#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.12:36:59.31#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.12:36:59.31#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.12:36:59.31$vck44/va=4,6 2006.173.12:36:59.31#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.12:36:59.31#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.12:36:59.31#ibcon#ireg 11 cls_cnt 2 2006.173.12:36:59.31#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.12:36:59.37#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.12:36:59.37#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.12:36:59.37#ibcon#enter wrdev, iclass 23, count 2 2006.173.12:36:59.37#ibcon#first serial, iclass 23, count 2 2006.173.12:36:59.37#ibcon#enter sib2, iclass 23, count 2 2006.173.12:36:59.37#ibcon#flushed, iclass 23, count 2 2006.173.12:36:59.37#ibcon#about to write, iclass 23, count 2 2006.173.12:36:59.37#ibcon#wrote, iclass 23, count 2 2006.173.12:36:59.37#ibcon#about to read 3, iclass 23, count 2 2006.173.12:36:59.39#ibcon#read 3, iclass 23, count 2 2006.173.12:36:59.39#ibcon#about to read 4, iclass 23, count 2 2006.173.12:36:59.39#ibcon#read 4, iclass 23, count 2 2006.173.12:36:59.39#ibcon#about to read 5, iclass 23, count 2 2006.173.12:36:59.39#ibcon#read 5, iclass 23, count 2 2006.173.12:36:59.39#ibcon#about to read 6, iclass 23, count 2 2006.173.12:36:59.39#ibcon#read 6, iclass 23, count 2 2006.173.12:36:59.39#ibcon#end of sib2, iclass 23, count 2 2006.173.12:36:59.39#ibcon#*mode == 0, iclass 23, count 2 2006.173.12:36:59.39#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.12:36:59.39#ibcon#[25=AT04-06\r\n] 2006.173.12:36:59.39#ibcon#*before write, iclass 23, count 2 2006.173.12:36:59.39#ibcon#enter sib2, iclass 23, count 2 2006.173.12:36:59.39#ibcon#flushed, iclass 23, count 2 2006.173.12:36:59.39#ibcon#about to write, iclass 23, count 2 2006.173.12:36:59.39#ibcon#wrote, iclass 23, count 2 2006.173.12:36:59.39#ibcon#about to read 3, iclass 23, count 2 2006.173.12:36:59.42#ibcon#read 3, iclass 23, count 2 2006.173.12:36:59.42#ibcon#about to read 4, iclass 23, count 2 2006.173.12:36:59.42#ibcon#read 4, iclass 23, count 2 2006.173.12:36:59.42#ibcon#about to read 5, iclass 23, count 2 2006.173.12:36:59.42#ibcon#read 5, iclass 23, count 2 2006.173.12:36:59.42#ibcon#about to read 6, iclass 23, count 2 2006.173.12:36:59.42#ibcon#read 6, iclass 23, count 2 2006.173.12:36:59.42#ibcon#end of sib2, iclass 23, count 2 2006.173.12:36:59.42#ibcon#*after write, iclass 23, count 2 2006.173.12:36:59.42#ibcon#*before return 0, iclass 23, count 2 2006.173.12:36:59.42#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.12:36:59.42#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.12:36:59.42#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.12:36:59.42#ibcon#ireg 7 cls_cnt 0 2006.173.12:36:59.42#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.12:36:59.54#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.12:36:59.54#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.12:36:59.54#ibcon#enter wrdev, iclass 23, count 0 2006.173.12:36:59.54#ibcon#first serial, iclass 23, count 0 2006.173.12:36:59.54#ibcon#enter sib2, iclass 23, count 0 2006.173.12:36:59.54#ibcon#flushed, iclass 23, count 0 2006.173.12:36:59.54#ibcon#about to write, iclass 23, count 0 2006.173.12:36:59.54#ibcon#wrote, iclass 23, count 0 2006.173.12:36:59.54#ibcon#about to read 3, iclass 23, count 0 2006.173.12:36:59.56#ibcon#read 3, iclass 23, count 0 2006.173.12:36:59.56#ibcon#about to read 4, iclass 23, count 0 2006.173.12:36:59.56#ibcon#read 4, iclass 23, count 0 2006.173.12:36:59.56#ibcon#about to read 5, iclass 23, count 0 2006.173.12:36:59.56#ibcon#read 5, iclass 23, count 0 2006.173.12:36:59.56#ibcon#about to read 6, iclass 23, count 0 2006.173.12:36:59.56#ibcon#read 6, iclass 23, count 0 2006.173.12:36:59.56#ibcon#end of sib2, iclass 23, count 0 2006.173.12:36:59.56#ibcon#*mode == 0, iclass 23, count 0 2006.173.12:36:59.56#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.12:36:59.56#ibcon#[25=USB\r\n] 2006.173.12:36:59.56#ibcon#*before write, iclass 23, count 0 2006.173.12:36:59.56#ibcon#enter sib2, iclass 23, count 0 2006.173.12:36:59.56#ibcon#flushed, iclass 23, count 0 2006.173.12:36:59.56#ibcon#about to write, iclass 23, count 0 2006.173.12:36:59.56#ibcon#wrote, iclass 23, count 0 2006.173.12:36:59.56#ibcon#about to read 3, iclass 23, count 0 2006.173.12:36:59.59#ibcon#read 3, iclass 23, count 0 2006.173.12:36:59.59#ibcon#about to read 4, iclass 23, count 0 2006.173.12:36:59.59#ibcon#read 4, iclass 23, count 0 2006.173.12:36:59.59#ibcon#about to read 5, iclass 23, count 0 2006.173.12:36:59.59#ibcon#read 5, iclass 23, count 0 2006.173.12:36:59.59#ibcon#about to read 6, iclass 23, count 0 2006.173.12:36:59.59#ibcon#read 6, iclass 23, count 0 2006.173.12:36:59.59#ibcon#end of sib2, iclass 23, count 0 2006.173.12:36:59.59#ibcon#*after write, iclass 23, count 0 2006.173.12:36:59.59#ibcon#*before return 0, iclass 23, count 0 2006.173.12:36:59.59#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.12:36:59.59#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.12:36:59.59#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.12:36:59.59#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.12:36:59.59$vck44/valo=5,734.99 2006.173.12:36:59.59#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.12:36:59.59#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.12:36:59.59#ibcon#ireg 17 cls_cnt 0 2006.173.12:36:59.59#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.12:36:59.59#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.12:36:59.59#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.12:36:59.59#ibcon#enter wrdev, iclass 25, count 0 2006.173.12:36:59.59#ibcon#first serial, iclass 25, count 0 2006.173.12:36:59.59#ibcon#enter sib2, iclass 25, count 0 2006.173.12:36:59.59#ibcon#flushed, iclass 25, count 0 2006.173.12:36:59.59#ibcon#about to write, iclass 25, count 0 2006.173.12:36:59.59#ibcon#wrote, iclass 25, count 0 2006.173.12:36:59.59#ibcon#about to read 3, iclass 25, count 0 2006.173.12:36:59.61#ibcon#read 3, iclass 25, count 0 2006.173.12:36:59.61#ibcon#about to read 4, iclass 25, count 0 2006.173.12:36:59.61#ibcon#read 4, iclass 25, count 0 2006.173.12:36:59.61#ibcon#about to read 5, iclass 25, count 0 2006.173.12:36:59.61#ibcon#read 5, iclass 25, count 0 2006.173.12:36:59.61#ibcon#about to read 6, iclass 25, count 0 2006.173.12:36:59.61#ibcon#read 6, iclass 25, count 0 2006.173.12:36:59.61#ibcon#end of sib2, iclass 25, count 0 2006.173.12:36:59.61#ibcon#*mode == 0, iclass 25, count 0 2006.173.12:36:59.61#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.12:36:59.61#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.12:36:59.61#ibcon#*before write, iclass 25, count 0 2006.173.12:36:59.61#ibcon#enter sib2, iclass 25, count 0 2006.173.12:36:59.61#ibcon#flushed, iclass 25, count 0 2006.173.12:36:59.61#ibcon#about to write, iclass 25, count 0 2006.173.12:36:59.61#ibcon#wrote, iclass 25, count 0 2006.173.12:36:59.61#ibcon#about to read 3, iclass 25, count 0 2006.173.12:36:59.65#ibcon#read 3, iclass 25, count 0 2006.173.12:36:59.65#ibcon#about to read 4, iclass 25, count 0 2006.173.12:36:59.65#ibcon#read 4, iclass 25, count 0 2006.173.12:36:59.65#ibcon#about to read 5, iclass 25, count 0 2006.173.12:36:59.65#ibcon#read 5, iclass 25, count 0 2006.173.12:36:59.65#ibcon#about to read 6, iclass 25, count 0 2006.173.12:36:59.65#ibcon#read 6, iclass 25, count 0 2006.173.12:36:59.65#ibcon#end of sib2, iclass 25, count 0 2006.173.12:36:59.65#ibcon#*after write, iclass 25, count 0 2006.173.12:36:59.65#ibcon#*before return 0, iclass 25, count 0 2006.173.12:36:59.65#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.12:36:59.65#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.12:36:59.65#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.12:36:59.65#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.12:36:59.65$vck44/va=5,4 2006.173.12:36:59.65#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.12:36:59.65#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.12:36:59.65#ibcon#ireg 11 cls_cnt 2 2006.173.12:36:59.65#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.12:36:59.71#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.12:36:59.71#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.12:36:59.71#ibcon#enter wrdev, iclass 27, count 2 2006.173.12:36:59.71#ibcon#first serial, iclass 27, count 2 2006.173.12:36:59.71#ibcon#enter sib2, iclass 27, count 2 2006.173.12:36:59.71#ibcon#flushed, iclass 27, count 2 2006.173.12:36:59.71#ibcon#about to write, iclass 27, count 2 2006.173.12:36:59.71#ibcon#wrote, iclass 27, count 2 2006.173.12:36:59.71#ibcon#about to read 3, iclass 27, count 2 2006.173.12:36:59.73#ibcon#read 3, iclass 27, count 2 2006.173.12:36:59.73#ibcon#about to read 4, iclass 27, count 2 2006.173.12:36:59.73#ibcon#read 4, iclass 27, count 2 2006.173.12:36:59.73#ibcon#about to read 5, iclass 27, count 2 2006.173.12:36:59.73#ibcon#read 5, iclass 27, count 2 2006.173.12:36:59.73#ibcon#about to read 6, iclass 27, count 2 2006.173.12:36:59.73#ibcon#read 6, iclass 27, count 2 2006.173.12:36:59.73#ibcon#end of sib2, iclass 27, count 2 2006.173.12:36:59.73#ibcon#*mode == 0, iclass 27, count 2 2006.173.12:36:59.73#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.12:36:59.73#ibcon#[25=AT05-04\r\n] 2006.173.12:36:59.73#ibcon#*before write, iclass 27, count 2 2006.173.12:36:59.73#ibcon#enter sib2, iclass 27, count 2 2006.173.12:36:59.73#ibcon#flushed, iclass 27, count 2 2006.173.12:36:59.73#ibcon#about to write, iclass 27, count 2 2006.173.12:36:59.73#ibcon#wrote, iclass 27, count 2 2006.173.12:36:59.73#ibcon#about to read 3, iclass 27, count 2 2006.173.12:36:59.76#ibcon#read 3, iclass 27, count 2 2006.173.12:36:59.76#ibcon#about to read 4, iclass 27, count 2 2006.173.12:36:59.76#ibcon#read 4, iclass 27, count 2 2006.173.12:36:59.76#ibcon#about to read 5, iclass 27, count 2 2006.173.12:36:59.76#ibcon#read 5, iclass 27, count 2 2006.173.12:36:59.76#ibcon#about to read 6, iclass 27, count 2 2006.173.12:36:59.76#ibcon#read 6, iclass 27, count 2 2006.173.12:36:59.76#ibcon#end of sib2, iclass 27, count 2 2006.173.12:36:59.76#ibcon#*after write, iclass 27, count 2 2006.173.12:36:59.76#ibcon#*before return 0, iclass 27, count 2 2006.173.12:36:59.76#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.12:36:59.76#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.12:36:59.76#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.12:36:59.76#ibcon#ireg 7 cls_cnt 0 2006.173.12:36:59.76#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.12:36:59.88#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.12:36:59.88#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.12:36:59.88#ibcon#enter wrdev, iclass 27, count 0 2006.173.12:36:59.88#ibcon#first serial, iclass 27, count 0 2006.173.12:36:59.88#ibcon#enter sib2, iclass 27, count 0 2006.173.12:36:59.88#ibcon#flushed, iclass 27, count 0 2006.173.12:36:59.88#ibcon#about to write, iclass 27, count 0 2006.173.12:36:59.88#ibcon#wrote, iclass 27, count 0 2006.173.12:36:59.88#ibcon#about to read 3, iclass 27, count 0 2006.173.12:36:59.90#ibcon#read 3, iclass 27, count 0 2006.173.12:36:59.90#ibcon#about to read 4, iclass 27, count 0 2006.173.12:36:59.90#ibcon#read 4, iclass 27, count 0 2006.173.12:36:59.90#ibcon#about to read 5, iclass 27, count 0 2006.173.12:36:59.90#ibcon#read 5, iclass 27, count 0 2006.173.12:36:59.90#ibcon#about to read 6, iclass 27, count 0 2006.173.12:36:59.90#ibcon#read 6, iclass 27, count 0 2006.173.12:36:59.90#ibcon#end of sib2, iclass 27, count 0 2006.173.12:36:59.90#ibcon#*mode == 0, iclass 27, count 0 2006.173.12:36:59.90#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.12:36:59.90#ibcon#[25=USB\r\n] 2006.173.12:36:59.90#ibcon#*before write, iclass 27, count 0 2006.173.12:36:59.90#ibcon#enter sib2, iclass 27, count 0 2006.173.12:36:59.90#ibcon#flushed, iclass 27, count 0 2006.173.12:36:59.90#ibcon#about to write, iclass 27, count 0 2006.173.12:36:59.90#ibcon#wrote, iclass 27, count 0 2006.173.12:36:59.90#ibcon#about to read 3, iclass 27, count 0 2006.173.12:36:59.93#ibcon#read 3, iclass 27, count 0 2006.173.12:36:59.93#ibcon#about to read 4, iclass 27, count 0 2006.173.12:36:59.93#ibcon#read 4, iclass 27, count 0 2006.173.12:36:59.93#ibcon#about to read 5, iclass 27, count 0 2006.173.12:36:59.93#ibcon#read 5, iclass 27, count 0 2006.173.12:36:59.93#ibcon#about to read 6, iclass 27, count 0 2006.173.12:36:59.93#ibcon#read 6, iclass 27, count 0 2006.173.12:36:59.93#ibcon#end of sib2, iclass 27, count 0 2006.173.12:36:59.93#ibcon#*after write, iclass 27, count 0 2006.173.12:36:59.93#ibcon#*before return 0, iclass 27, count 0 2006.173.12:36:59.93#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.12:36:59.93#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.12:36:59.93#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.12:36:59.93#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.12:36:59.93$vck44/valo=6,814.99 2006.173.12:36:59.93#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.12:36:59.93#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.12:36:59.93#ibcon#ireg 17 cls_cnt 0 2006.173.12:36:59.93#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.12:36:59.93#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.12:36:59.93#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.12:36:59.93#ibcon#enter wrdev, iclass 29, count 0 2006.173.12:36:59.93#ibcon#first serial, iclass 29, count 0 2006.173.12:36:59.93#ibcon#enter sib2, iclass 29, count 0 2006.173.12:36:59.93#ibcon#flushed, iclass 29, count 0 2006.173.12:36:59.93#ibcon#about to write, iclass 29, count 0 2006.173.12:36:59.93#ibcon#wrote, iclass 29, count 0 2006.173.12:36:59.93#ibcon#about to read 3, iclass 29, count 0 2006.173.12:36:59.95#ibcon#read 3, iclass 29, count 0 2006.173.12:36:59.95#ibcon#about to read 4, iclass 29, count 0 2006.173.12:36:59.95#ibcon#read 4, iclass 29, count 0 2006.173.12:36:59.95#ibcon#about to read 5, iclass 29, count 0 2006.173.12:36:59.95#ibcon#read 5, iclass 29, count 0 2006.173.12:36:59.95#ibcon#about to read 6, iclass 29, count 0 2006.173.12:36:59.95#ibcon#read 6, iclass 29, count 0 2006.173.12:36:59.95#ibcon#end of sib2, iclass 29, count 0 2006.173.12:36:59.95#ibcon#*mode == 0, iclass 29, count 0 2006.173.12:36:59.95#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.12:36:59.95#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.12:36:59.95#ibcon#*before write, iclass 29, count 0 2006.173.12:36:59.95#ibcon#enter sib2, iclass 29, count 0 2006.173.12:36:59.95#ibcon#flushed, iclass 29, count 0 2006.173.12:36:59.95#ibcon#about to write, iclass 29, count 0 2006.173.12:36:59.95#ibcon#wrote, iclass 29, count 0 2006.173.12:36:59.95#ibcon#about to read 3, iclass 29, count 0 2006.173.12:36:59.99#ibcon#read 3, iclass 29, count 0 2006.173.12:36:59.99#ibcon#about to read 4, iclass 29, count 0 2006.173.12:36:59.99#ibcon#read 4, iclass 29, count 0 2006.173.12:36:59.99#ibcon#about to read 5, iclass 29, count 0 2006.173.12:36:59.99#ibcon#read 5, iclass 29, count 0 2006.173.12:36:59.99#ibcon#about to read 6, iclass 29, count 0 2006.173.12:36:59.99#ibcon#read 6, iclass 29, count 0 2006.173.12:36:59.99#ibcon#end of sib2, iclass 29, count 0 2006.173.12:36:59.99#ibcon#*after write, iclass 29, count 0 2006.173.12:36:59.99#ibcon#*before return 0, iclass 29, count 0 2006.173.12:36:59.99#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.12:36:59.99#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.12:36:59.99#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.12:36:59.99#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.12:36:59.99$vck44/va=6,3 2006.173.12:36:59.99#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.12:36:59.99#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.12:36:59.99#ibcon#ireg 11 cls_cnt 2 2006.173.12:36:59.99#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.12:37:00.05#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.12:37:00.05#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.12:37:00.05#ibcon#enter wrdev, iclass 31, count 2 2006.173.12:37:00.05#ibcon#first serial, iclass 31, count 2 2006.173.12:37:00.05#ibcon#enter sib2, iclass 31, count 2 2006.173.12:37:00.05#ibcon#flushed, iclass 31, count 2 2006.173.12:37:00.05#ibcon#about to write, iclass 31, count 2 2006.173.12:37:00.05#ibcon#wrote, iclass 31, count 2 2006.173.12:37:00.05#ibcon#about to read 3, iclass 31, count 2 2006.173.12:37:00.07#ibcon#read 3, iclass 31, count 2 2006.173.12:37:00.07#ibcon#about to read 4, iclass 31, count 2 2006.173.12:37:00.07#ibcon#read 4, iclass 31, count 2 2006.173.12:37:00.07#ibcon#about to read 5, iclass 31, count 2 2006.173.12:37:00.07#ibcon#read 5, iclass 31, count 2 2006.173.12:37:00.07#ibcon#about to read 6, iclass 31, count 2 2006.173.12:37:00.07#ibcon#read 6, iclass 31, count 2 2006.173.12:37:00.07#ibcon#end of sib2, iclass 31, count 2 2006.173.12:37:00.07#ibcon#*mode == 0, iclass 31, count 2 2006.173.12:37:00.07#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.12:37:00.07#ibcon#[25=AT06-03\r\n] 2006.173.12:37:00.07#ibcon#*before write, iclass 31, count 2 2006.173.12:37:00.07#ibcon#enter sib2, iclass 31, count 2 2006.173.12:37:00.07#ibcon#flushed, iclass 31, count 2 2006.173.12:37:00.07#ibcon#about to write, iclass 31, count 2 2006.173.12:37:00.07#ibcon#wrote, iclass 31, count 2 2006.173.12:37:00.07#ibcon#about to read 3, iclass 31, count 2 2006.173.12:37:00.10#ibcon#read 3, iclass 31, count 2 2006.173.12:37:00.10#ibcon#about to read 4, iclass 31, count 2 2006.173.12:37:00.10#ibcon#read 4, iclass 31, count 2 2006.173.12:37:00.10#ibcon#about to read 5, iclass 31, count 2 2006.173.12:37:00.10#ibcon#read 5, iclass 31, count 2 2006.173.12:37:00.10#ibcon#about to read 6, iclass 31, count 2 2006.173.12:37:00.10#ibcon#read 6, iclass 31, count 2 2006.173.12:37:00.10#ibcon#end of sib2, iclass 31, count 2 2006.173.12:37:00.10#ibcon#*after write, iclass 31, count 2 2006.173.12:37:00.10#ibcon#*before return 0, iclass 31, count 2 2006.173.12:37:00.10#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.12:37:00.10#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.12:37:00.10#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.12:37:00.10#ibcon#ireg 7 cls_cnt 0 2006.173.12:37:00.10#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.12:37:00.22#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.12:37:00.22#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.12:37:00.22#ibcon#enter wrdev, iclass 31, count 0 2006.173.12:37:00.22#ibcon#first serial, iclass 31, count 0 2006.173.12:37:00.22#ibcon#enter sib2, iclass 31, count 0 2006.173.12:37:00.22#ibcon#flushed, iclass 31, count 0 2006.173.12:37:00.22#ibcon#about to write, iclass 31, count 0 2006.173.12:37:00.22#ibcon#wrote, iclass 31, count 0 2006.173.12:37:00.22#ibcon#about to read 3, iclass 31, count 0 2006.173.12:37:00.24#ibcon#read 3, iclass 31, count 0 2006.173.12:37:00.24#ibcon#about to read 4, iclass 31, count 0 2006.173.12:37:00.24#ibcon#read 4, iclass 31, count 0 2006.173.12:37:00.24#ibcon#about to read 5, iclass 31, count 0 2006.173.12:37:00.24#ibcon#read 5, iclass 31, count 0 2006.173.12:37:00.24#ibcon#about to read 6, iclass 31, count 0 2006.173.12:37:00.24#ibcon#read 6, iclass 31, count 0 2006.173.12:37:00.24#ibcon#end of sib2, iclass 31, count 0 2006.173.12:37:00.24#ibcon#*mode == 0, iclass 31, count 0 2006.173.12:37:00.24#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.12:37:00.24#ibcon#[25=USB\r\n] 2006.173.12:37:00.24#ibcon#*before write, iclass 31, count 0 2006.173.12:37:00.24#ibcon#enter sib2, iclass 31, count 0 2006.173.12:37:00.24#ibcon#flushed, iclass 31, count 0 2006.173.12:37:00.24#ibcon#about to write, iclass 31, count 0 2006.173.12:37:00.24#ibcon#wrote, iclass 31, count 0 2006.173.12:37:00.24#ibcon#about to read 3, iclass 31, count 0 2006.173.12:37:00.27#ibcon#read 3, iclass 31, count 0 2006.173.12:37:00.27#ibcon#about to read 4, iclass 31, count 0 2006.173.12:37:00.27#ibcon#read 4, iclass 31, count 0 2006.173.12:37:00.27#ibcon#about to read 5, iclass 31, count 0 2006.173.12:37:00.27#ibcon#read 5, iclass 31, count 0 2006.173.12:37:00.27#ibcon#about to read 6, iclass 31, count 0 2006.173.12:37:00.27#ibcon#read 6, iclass 31, count 0 2006.173.12:37:00.27#ibcon#end of sib2, iclass 31, count 0 2006.173.12:37:00.27#ibcon#*after write, iclass 31, count 0 2006.173.12:37:00.27#ibcon#*before return 0, iclass 31, count 0 2006.173.12:37:00.27#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.12:37:00.27#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.12:37:00.27#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.12:37:00.27#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.12:37:00.27$vck44/valo=7,864.99 2006.173.12:37:00.27#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.12:37:00.27#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.12:37:00.27#ibcon#ireg 17 cls_cnt 0 2006.173.12:37:00.27#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.12:37:00.27#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.12:37:00.27#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.12:37:00.27#ibcon#enter wrdev, iclass 33, count 0 2006.173.12:37:00.27#ibcon#first serial, iclass 33, count 0 2006.173.12:37:00.27#ibcon#enter sib2, iclass 33, count 0 2006.173.12:37:00.27#ibcon#flushed, iclass 33, count 0 2006.173.12:37:00.27#ibcon#about to write, iclass 33, count 0 2006.173.12:37:00.27#ibcon#wrote, iclass 33, count 0 2006.173.12:37:00.27#ibcon#about to read 3, iclass 33, count 0 2006.173.12:37:00.29#ibcon#read 3, iclass 33, count 0 2006.173.12:37:00.29#ibcon#about to read 4, iclass 33, count 0 2006.173.12:37:00.29#ibcon#read 4, iclass 33, count 0 2006.173.12:37:00.29#ibcon#about to read 5, iclass 33, count 0 2006.173.12:37:00.29#ibcon#read 5, iclass 33, count 0 2006.173.12:37:00.29#ibcon#about to read 6, iclass 33, count 0 2006.173.12:37:00.29#ibcon#read 6, iclass 33, count 0 2006.173.12:37:00.29#ibcon#end of sib2, iclass 33, count 0 2006.173.12:37:00.29#ibcon#*mode == 0, iclass 33, count 0 2006.173.12:37:00.29#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.12:37:00.29#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.12:37:00.29#ibcon#*before write, iclass 33, count 0 2006.173.12:37:00.29#ibcon#enter sib2, iclass 33, count 0 2006.173.12:37:00.29#ibcon#flushed, iclass 33, count 0 2006.173.12:37:00.29#ibcon#about to write, iclass 33, count 0 2006.173.12:37:00.29#ibcon#wrote, iclass 33, count 0 2006.173.12:37:00.29#ibcon#about to read 3, iclass 33, count 0 2006.173.12:37:00.33#ibcon#read 3, iclass 33, count 0 2006.173.12:37:00.33#ibcon#about to read 4, iclass 33, count 0 2006.173.12:37:00.33#ibcon#read 4, iclass 33, count 0 2006.173.12:37:00.33#ibcon#about to read 5, iclass 33, count 0 2006.173.12:37:00.33#ibcon#read 5, iclass 33, count 0 2006.173.12:37:00.33#ibcon#about to read 6, iclass 33, count 0 2006.173.12:37:00.33#ibcon#read 6, iclass 33, count 0 2006.173.12:37:00.33#ibcon#end of sib2, iclass 33, count 0 2006.173.12:37:00.33#ibcon#*after write, iclass 33, count 0 2006.173.12:37:00.33#ibcon#*before return 0, iclass 33, count 0 2006.173.12:37:00.33#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.12:37:00.33#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.12:37:00.33#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.12:37:00.33#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.12:37:00.33$vck44/va=7,4 2006.173.12:37:00.33#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.12:37:00.33#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.12:37:00.33#ibcon#ireg 11 cls_cnt 2 2006.173.12:37:00.33#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.12:37:00.39#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.12:37:00.39#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.12:37:00.39#ibcon#enter wrdev, iclass 35, count 2 2006.173.12:37:00.39#ibcon#first serial, iclass 35, count 2 2006.173.12:37:00.39#ibcon#enter sib2, iclass 35, count 2 2006.173.12:37:00.39#ibcon#flushed, iclass 35, count 2 2006.173.12:37:00.39#ibcon#about to write, iclass 35, count 2 2006.173.12:37:00.39#ibcon#wrote, iclass 35, count 2 2006.173.12:37:00.39#ibcon#about to read 3, iclass 35, count 2 2006.173.12:37:00.41#ibcon#read 3, iclass 35, count 2 2006.173.12:37:00.41#ibcon#about to read 4, iclass 35, count 2 2006.173.12:37:00.41#ibcon#read 4, iclass 35, count 2 2006.173.12:37:00.41#ibcon#about to read 5, iclass 35, count 2 2006.173.12:37:00.41#ibcon#read 5, iclass 35, count 2 2006.173.12:37:00.41#ibcon#about to read 6, iclass 35, count 2 2006.173.12:37:00.41#ibcon#read 6, iclass 35, count 2 2006.173.12:37:00.41#ibcon#end of sib2, iclass 35, count 2 2006.173.12:37:00.41#ibcon#*mode == 0, iclass 35, count 2 2006.173.12:37:00.41#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.12:37:00.41#ibcon#[25=AT07-04\r\n] 2006.173.12:37:00.41#ibcon#*before write, iclass 35, count 2 2006.173.12:37:00.41#ibcon#enter sib2, iclass 35, count 2 2006.173.12:37:00.41#ibcon#flushed, iclass 35, count 2 2006.173.12:37:00.41#ibcon#about to write, iclass 35, count 2 2006.173.12:37:00.41#ibcon#wrote, iclass 35, count 2 2006.173.12:37:00.41#ibcon#about to read 3, iclass 35, count 2 2006.173.12:37:00.44#ibcon#read 3, iclass 35, count 2 2006.173.12:37:00.44#ibcon#about to read 4, iclass 35, count 2 2006.173.12:37:00.44#ibcon#read 4, iclass 35, count 2 2006.173.12:37:00.44#ibcon#about to read 5, iclass 35, count 2 2006.173.12:37:00.44#ibcon#read 5, iclass 35, count 2 2006.173.12:37:00.44#ibcon#about to read 6, iclass 35, count 2 2006.173.12:37:00.44#ibcon#read 6, iclass 35, count 2 2006.173.12:37:00.44#ibcon#end of sib2, iclass 35, count 2 2006.173.12:37:00.44#ibcon#*after write, iclass 35, count 2 2006.173.12:37:00.44#ibcon#*before return 0, iclass 35, count 2 2006.173.12:37:00.44#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.12:37:00.44#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.12:37:00.44#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.12:37:00.44#ibcon#ireg 7 cls_cnt 0 2006.173.12:37:00.44#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.12:37:00.56#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.12:37:00.56#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.12:37:00.56#ibcon#enter wrdev, iclass 35, count 0 2006.173.12:37:00.56#ibcon#first serial, iclass 35, count 0 2006.173.12:37:00.56#ibcon#enter sib2, iclass 35, count 0 2006.173.12:37:00.56#ibcon#flushed, iclass 35, count 0 2006.173.12:37:00.56#ibcon#about to write, iclass 35, count 0 2006.173.12:37:00.56#ibcon#wrote, iclass 35, count 0 2006.173.12:37:00.56#ibcon#about to read 3, iclass 35, count 0 2006.173.12:37:00.58#ibcon#read 3, iclass 35, count 0 2006.173.12:37:00.58#ibcon#about to read 4, iclass 35, count 0 2006.173.12:37:00.58#ibcon#read 4, iclass 35, count 0 2006.173.12:37:00.58#ibcon#about to read 5, iclass 35, count 0 2006.173.12:37:00.58#ibcon#read 5, iclass 35, count 0 2006.173.12:37:00.58#ibcon#about to read 6, iclass 35, count 0 2006.173.12:37:00.58#ibcon#read 6, iclass 35, count 0 2006.173.12:37:00.58#ibcon#end of sib2, iclass 35, count 0 2006.173.12:37:00.58#ibcon#*mode == 0, iclass 35, count 0 2006.173.12:37:00.58#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.12:37:00.58#ibcon#[25=USB\r\n] 2006.173.12:37:00.58#ibcon#*before write, iclass 35, count 0 2006.173.12:37:00.58#ibcon#enter sib2, iclass 35, count 0 2006.173.12:37:00.58#ibcon#flushed, iclass 35, count 0 2006.173.12:37:00.58#ibcon#about to write, iclass 35, count 0 2006.173.12:37:00.58#ibcon#wrote, iclass 35, count 0 2006.173.12:37:00.58#ibcon#about to read 3, iclass 35, count 0 2006.173.12:37:00.61#ibcon#read 3, iclass 35, count 0 2006.173.12:37:00.61#ibcon#about to read 4, iclass 35, count 0 2006.173.12:37:00.61#ibcon#read 4, iclass 35, count 0 2006.173.12:37:00.61#ibcon#about to read 5, iclass 35, count 0 2006.173.12:37:00.61#ibcon#read 5, iclass 35, count 0 2006.173.12:37:00.61#ibcon#about to read 6, iclass 35, count 0 2006.173.12:37:00.61#ibcon#read 6, iclass 35, count 0 2006.173.12:37:00.61#ibcon#end of sib2, iclass 35, count 0 2006.173.12:37:00.61#ibcon#*after write, iclass 35, count 0 2006.173.12:37:00.61#ibcon#*before return 0, iclass 35, count 0 2006.173.12:37:00.61#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.12:37:00.61#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.12:37:00.61#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.12:37:00.61#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.12:37:00.61$vck44/valo=8,884.99 2006.173.12:37:00.61#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.12:37:00.61#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.12:37:00.61#ibcon#ireg 17 cls_cnt 0 2006.173.12:37:00.61#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.12:37:00.61#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.12:37:00.61#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.12:37:00.61#ibcon#enter wrdev, iclass 37, count 0 2006.173.12:37:00.61#ibcon#first serial, iclass 37, count 0 2006.173.12:37:00.61#ibcon#enter sib2, iclass 37, count 0 2006.173.12:37:00.61#ibcon#flushed, iclass 37, count 0 2006.173.12:37:00.61#ibcon#about to write, iclass 37, count 0 2006.173.12:37:00.61#ibcon#wrote, iclass 37, count 0 2006.173.12:37:00.61#ibcon#about to read 3, iclass 37, count 0 2006.173.12:37:00.63#ibcon#read 3, iclass 37, count 0 2006.173.12:37:00.63#ibcon#about to read 4, iclass 37, count 0 2006.173.12:37:00.63#ibcon#read 4, iclass 37, count 0 2006.173.12:37:00.63#ibcon#about to read 5, iclass 37, count 0 2006.173.12:37:00.63#ibcon#read 5, iclass 37, count 0 2006.173.12:37:00.63#ibcon#about to read 6, iclass 37, count 0 2006.173.12:37:00.63#ibcon#read 6, iclass 37, count 0 2006.173.12:37:00.63#ibcon#end of sib2, iclass 37, count 0 2006.173.12:37:00.63#ibcon#*mode == 0, iclass 37, count 0 2006.173.12:37:00.63#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.12:37:00.63#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.12:37:00.63#ibcon#*before write, iclass 37, count 0 2006.173.12:37:00.63#ibcon#enter sib2, iclass 37, count 0 2006.173.12:37:00.63#ibcon#flushed, iclass 37, count 0 2006.173.12:37:00.63#ibcon#about to write, iclass 37, count 0 2006.173.12:37:00.63#ibcon#wrote, iclass 37, count 0 2006.173.12:37:00.63#ibcon#about to read 3, iclass 37, count 0 2006.173.12:37:00.67#ibcon#read 3, iclass 37, count 0 2006.173.12:37:00.67#ibcon#about to read 4, iclass 37, count 0 2006.173.12:37:00.67#ibcon#read 4, iclass 37, count 0 2006.173.12:37:00.67#ibcon#about to read 5, iclass 37, count 0 2006.173.12:37:00.67#ibcon#read 5, iclass 37, count 0 2006.173.12:37:00.67#ibcon#about to read 6, iclass 37, count 0 2006.173.12:37:00.67#ibcon#read 6, iclass 37, count 0 2006.173.12:37:00.67#ibcon#end of sib2, iclass 37, count 0 2006.173.12:37:00.67#ibcon#*after write, iclass 37, count 0 2006.173.12:37:00.67#ibcon#*before return 0, iclass 37, count 0 2006.173.12:37:00.67#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.12:37:00.67#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.12:37:00.67#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.12:37:00.67#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.12:37:00.67$vck44/va=8,4 2006.173.12:37:00.67#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.12:37:00.67#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.12:37:00.67#ibcon#ireg 11 cls_cnt 2 2006.173.12:37:00.67#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.12:37:00.73#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.12:37:00.73#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.12:37:00.73#ibcon#enter wrdev, iclass 39, count 2 2006.173.12:37:00.73#ibcon#first serial, iclass 39, count 2 2006.173.12:37:00.73#ibcon#enter sib2, iclass 39, count 2 2006.173.12:37:00.73#ibcon#flushed, iclass 39, count 2 2006.173.12:37:00.73#ibcon#about to write, iclass 39, count 2 2006.173.12:37:00.73#ibcon#wrote, iclass 39, count 2 2006.173.12:37:00.73#ibcon#about to read 3, iclass 39, count 2 2006.173.12:37:00.75#ibcon#read 3, iclass 39, count 2 2006.173.12:37:00.75#ibcon#about to read 4, iclass 39, count 2 2006.173.12:37:00.75#ibcon#read 4, iclass 39, count 2 2006.173.12:37:00.75#ibcon#about to read 5, iclass 39, count 2 2006.173.12:37:00.75#ibcon#read 5, iclass 39, count 2 2006.173.12:37:00.75#ibcon#about to read 6, iclass 39, count 2 2006.173.12:37:00.75#ibcon#read 6, iclass 39, count 2 2006.173.12:37:00.75#ibcon#end of sib2, iclass 39, count 2 2006.173.12:37:00.75#ibcon#*mode == 0, iclass 39, count 2 2006.173.12:37:00.75#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.12:37:00.75#ibcon#[25=AT08-04\r\n] 2006.173.12:37:00.75#ibcon#*before write, iclass 39, count 2 2006.173.12:37:00.75#ibcon#enter sib2, iclass 39, count 2 2006.173.12:37:00.75#ibcon#flushed, iclass 39, count 2 2006.173.12:37:00.75#ibcon#about to write, iclass 39, count 2 2006.173.12:37:00.75#ibcon#wrote, iclass 39, count 2 2006.173.12:37:00.75#ibcon#about to read 3, iclass 39, count 2 2006.173.12:37:00.78#ibcon#read 3, iclass 39, count 2 2006.173.12:37:00.78#ibcon#about to read 4, iclass 39, count 2 2006.173.12:37:00.78#ibcon#read 4, iclass 39, count 2 2006.173.12:37:00.78#ibcon#about to read 5, iclass 39, count 2 2006.173.12:37:00.78#ibcon#read 5, iclass 39, count 2 2006.173.12:37:00.78#ibcon#about to read 6, iclass 39, count 2 2006.173.12:37:00.78#ibcon#read 6, iclass 39, count 2 2006.173.12:37:00.78#ibcon#end of sib2, iclass 39, count 2 2006.173.12:37:00.78#ibcon#*after write, iclass 39, count 2 2006.173.12:37:00.78#ibcon#*before return 0, iclass 39, count 2 2006.173.12:37:00.78#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.12:37:00.78#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.12:37:00.78#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.12:37:00.78#ibcon#ireg 7 cls_cnt 0 2006.173.12:37:00.78#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.12:37:00.90#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.12:37:00.90#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.12:37:00.90#ibcon#enter wrdev, iclass 39, count 0 2006.173.12:37:00.90#ibcon#first serial, iclass 39, count 0 2006.173.12:37:00.90#ibcon#enter sib2, iclass 39, count 0 2006.173.12:37:00.90#ibcon#flushed, iclass 39, count 0 2006.173.12:37:00.90#ibcon#about to write, iclass 39, count 0 2006.173.12:37:00.90#ibcon#wrote, iclass 39, count 0 2006.173.12:37:00.90#ibcon#about to read 3, iclass 39, count 0 2006.173.12:37:00.92#ibcon#read 3, iclass 39, count 0 2006.173.12:37:00.92#ibcon#about to read 4, iclass 39, count 0 2006.173.12:37:00.92#ibcon#read 4, iclass 39, count 0 2006.173.12:37:00.92#ibcon#about to read 5, iclass 39, count 0 2006.173.12:37:00.92#ibcon#read 5, iclass 39, count 0 2006.173.12:37:00.92#ibcon#about to read 6, iclass 39, count 0 2006.173.12:37:00.92#ibcon#read 6, iclass 39, count 0 2006.173.12:37:00.92#ibcon#end of sib2, iclass 39, count 0 2006.173.12:37:00.92#ibcon#*mode == 0, iclass 39, count 0 2006.173.12:37:00.92#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.12:37:00.92#ibcon#[25=USB\r\n] 2006.173.12:37:00.92#ibcon#*before write, iclass 39, count 0 2006.173.12:37:00.92#ibcon#enter sib2, iclass 39, count 0 2006.173.12:37:00.92#ibcon#flushed, iclass 39, count 0 2006.173.12:37:00.92#ibcon#about to write, iclass 39, count 0 2006.173.12:37:00.92#ibcon#wrote, iclass 39, count 0 2006.173.12:37:00.92#ibcon#about to read 3, iclass 39, count 0 2006.173.12:37:00.95#ibcon#read 3, iclass 39, count 0 2006.173.12:37:00.95#ibcon#about to read 4, iclass 39, count 0 2006.173.12:37:00.95#ibcon#read 4, iclass 39, count 0 2006.173.12:37:00.95#ibcon#about to read 5, iclass 39, count 0 2006.173.12:37:00.95#ibcon#read 5, iclass 39, count 0 2006.173.12:37:00.95#ibcon#about to read 6, iclass 39, count 0 2006.173.12:37:00.95#ibcon#read 6, iclass 39, count 0 2006.173.12:37:00.95#ibcon#end of sib2, iclass 39, count 0 2006.173.12:37:00.95#ibcon#*after write, iclass 39, count 0 2006.173.12:37:00.95#ibcon#*before return 0, iclass 39, count 0 2006.173.12:37:00.95#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.12:37:00.95#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.12:37:00.95#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.12:37:00.95#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.12:37:00.95$vck44/vblo=1,629.99 2006.173.12:37:00.95#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.12:37:00.95#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.12:37:00.95#ibcon#ireg 17 cls_cnt 0 2006.173.12:37:00.95#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.12:37:00.95#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.12:37:00.95#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.12:37:00.95#ibcon#enter wrdev, iclass 3, count 0 2006.173.12:37:00.95#ibcon#first serial, iclass 3, count 0 2006.173.12:37:00.95#ibcon#enter sib2, iclass 3, count 0 2006.173.12:37:00.95#ibcon#flushed, iclass 3, count 0 2006.173.12:37:00.95#ibcon#about to write, iclass 3, count 0 2006.173.12:37:00.95#ibcon#wrote, iclass 3, count 0 2006.173.12:37:00.95#ibcon#about to read 3, iclass 3, count 0 2006.173.12:37:00.97#ibcon#read 3, iclass 3, count 0 2006.173.12:37:00.97#ibcon#about to read 4, iclass 3, count 0 2006.173.12:37:00.97#ibcon#read 4, iclass 3, count 0 2006.173.12:37:00.97#ibcon#about to read 5, iclass 3, count 0 2006.173.12:37:00.97#ibcon#read 5, iclass 3, count 0 2006.173.12:37:00.97#ibcon#about to read 6, iclass 3, count 0 2006.173.12:37:00.97#ibcon#read 6, iclass 3, count 0 2006.173.12:37:00.97#ibcon#end of sib2, iclass 3, count 0 2006.173.12:37:00.97#ibcon#*mode == 0, iclass 3, count 0 2006.173.12:37:00.97#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.12:37:00.97#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.12:37:00.97#ibcon#*before write, iclass 3, count 0 2006.173.12:37:00.97#ibcon#enter sib2, iclass 3, count 0 2006.173.12:37:00.97#ibcon#flushed, iclass 3, count 0 2006.173.12:37:00.97#ibcon#about to write, iclass 3, count 0 2006.173.12:37:00.97#ibcon#wrote, iclass 3, count 0 2006.173.12:37:00.97#ibcon#about to read 3, iclass 3, count 0 2006.173.12:37:01.01#ibcon#read 3, iclass 3, count 0 2006.173.12:37:01.01#ibcon#about to read 4, iclass 3, count 0 2006.173.12:37:01.01#ibcon#read 4, iclass 3, count 0 2006.173.12:37:01.01#ibcon#about to read 5, iclass 3, count 0 2006.173.12:37:01.01#ibcon#read 5, iclass 3, count 0 2006.173.12:37:01.01#ibcon#about to read 6, iclass 3, count 0 2006.173.12:37:01.01#ibcon#read 6, iclass 3, count 0 2006.173.12:37:01.01#ibcon#end of sib2, iclass 3, count 0 2006.173.12:37:01.01#ibcon#*after write, iclass 3, count 0 2006.173.12:37:01.01#ibcon#*before return 0, iclass 3, count 0 2006.173.12:37:01.01#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.12:37:01.01#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.12:37:01.01#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.12:37:01.01#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.12:37:01.01$vck44/vb=1,4 2006.173.12:37:01.01#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.12:37:01.01#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.12:37:01.01#ibcon#ireg 11 cls_cnt 2 2006.173.12:37:01.01#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.12:37:01.01#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.12:37:01.01#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.12:37:01.01#ibcon#enter wrdev, iclass 5, count 2 2006.173.12:37:01.01#ibcon#first serial, iclass 5, count 2 2006.173.12:37:01.01#ibcon#enter sib2, iclass 5, count 2 2006.173.12:37:01.01#ibcon#flushed, iclass 5, count 2 2006.173.12:37:01.01#ibcon#about to write, iclass 5, count 2 2006.173.12:37:01.01#ibcon#wrote, iclass 5, count 2 2006.173.12:37:01.01#ibcon#about to read 3, iclass 5, count 2 2006.173.12:37:01.03#ibcon#read 3, iclass 5, count 2 2006.173.12:37:01.03#ibcon#about to read 4, iclass 5, count 2 2006.173.12:37:01.03#ibcon#read 4, iclass 5, count 2 2006.173.12:37:01.03#ibcon#about to read 5, iclass 5, count 2 2006.173.12:37:01.03#ibcon#read 5, iclass 5, count 2 2006.173.12:37:01.03#ibcon#about to read 6, iclass 5, count 2 2006.173.12:37:01.03#ibcon#read 6, iclass 5, count 2 2006.173.12:37:01.03#ibcon#end of sib2, iclass 5, count 2 2006.173.12:37:01.03#ibcon#*mode == 0, iclass 5, count 2 2006.173.12:37:01.03#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.12:37:01.03#ibcon#[27=AT01-04\r\n] 2006.173.12:37:01.03#ibcon#*before write, iclass 5, count 2 2006.173.12:37:01.03#ibcon#enter sib2, iclass 5, count 2 2006.173.12:37:01.03#ibcon#flushed, iclass 5, count 2 2006.173.12:37:01.03#ibcon#about to write, iclass 5, count 2 2006.173.12:37:01.03#ibcon#wrote, iclass 5, count 2 2006.173.12:37:01.03#ibcon#about to read 3, iclass 5, count 2 2006.173.12:37:01.06#ibcon#read 3, iclass 5, count 2 2006.173.12:37:01.06#ibcon#about to read 4, iclass 5, count 2 2006.173.12:37:01.06#ibcon#read 4, iclass 5, count 2 2006.173.12:37:01.06#ibcon#about to read 5, iclass 5, count 2 2006.173.12:37:01.06#ibcon#read 5, iclass 5, count 2 2006.173.12:37:01.06#ibcon#about to read 6, iclass 5, count 2 2006.173.12:37:01.06#ibcon#read 6, iclass 5, count 2 2006.173.12:37:01.06#ibcon#end of sib2, iclass 5, count 2 2006.173.12:37:01.06#ibcon#*after write, iclass 5, count 2 2006.173.12:37:01.06#ibcon#*before return 0, iclass 5, count 2 2006.173.12:37:01.06#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.12:37:01.06#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.12:37:01.06#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.12:37:01.06#ibcon#ireg 7 cls_cnt 0 2006.173.12:37:01.06#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.12:37:01.18#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.12:37:01.18#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.12:37:01.18#ibcon#enter wrdev, iclass 5, count 0 2006.173.12:37:01.18#ibcon#first serial, iclass 5, count 0 2006.173.12:37:01.18#ibcon#enter sib2, iclass 5, count 0 2006.173.12:37:01.18#ibcon#flushed, iclass 5, count 0 2006.173.12:37:01.18#ibcon#about to write, iclass 5, count 0 2006.173.12:37:01.18#ibcon#wrote, iclass 5, count 0 2006.173.12:37:01.18#ibcon#about to read 3, iclass 5, count 0 2006.173.12:37:01.20#ibcon#read 3, iclass 5, count 0 2006.173.12:37:01.20#ibcon#about to read 4, iclass 5, count 0 2006.173.12:37:01.20#ibcon#read 4, iclass 5, count 0 2006.173.12:37:01.20#ibcon#about to read 5, iclass 5, count 0 2006.173.12:37:01.20#ibcon#read 5, iclass 5, count 0 2006.173.12:37:01.20#ibcon#about to read 6, iclass 5, count 0 2006.173.12:37:01.20#ibcon#read 6, iclass 5, count 0 2006.173.12:37:01.20#ibcon#end of sib2, iclass 5, count 0 2006.173.12:37:01.20#ibcon#*mode == 0, iclass 5, count 0 2006.173.12:37:01.20#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.12:37:01.20#ibcon#[27=USB\r\n] 2006.173.12:37:01.20#ibcon#*before write, iclass 5, count 0 2006.173.12:37:01.20#ibcon#enter sib2, iclass 5, count 0 2006.173.12:37:01.20#ibcon#flushed, iclass 5, count 0 2006.173.12:37:01.20#ibcon#about to write, iclass 5, count 0 2006.173.12:37:01.20#ibcon#wrote, iclass 5, count 0 2006.173.12:37:01.20#ibcon#about to read 3, iclass 5, count 0 2006.173.12:37:01.23#ibcon#read 3, iclass 5, count 0 2006.173.12:37:01.23#ibcon#about to read 4, iclass 5, count 0 2006.173.12:37:01.23#ibcon#read 4, iclass 5, count 0 2006.173.12:37:01.23#ibcon#about to read 5, iclass 5, count 0 2006.173.12:37:01.23#ibcon#read 5, iclass 5, count 0 2006.173.12:37:01.23#ibcon#about to read 6, iclass 5, count 0 2006.173.12:37:01.23#ibcon#read 6, iclass 5, count 0 2006.173.12:37:01.23#ibcon#end of sib2, iclass 5, count 0 2006.173.12:37:01.23#ibcon#*after write, iclass 5, count 0 2006.173.12:37:01.23#ibcon#*before return 0, iclass 5, count 0 2006.173.12:37:01.23#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.12:37:01.23#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.12:37:01.23#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.12:37:01.23#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.12:37:01.23$vck44/vblo=2,634.99 2006.173.12:37:01.23#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.12:37:01.23#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.12:37:01.23#ibcon#ireg 17 cls_cnt 0 2006.173.12:37:01.23#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.12:37:01.23#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.12:37:01.23#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.12:37:01.23#ibcon#enter wrdev, iclass 7, count 0 2006.173.12:37:01.23#ibcon#first serial, iclass 7, count 0 2006.173.12:37:01.23#ibcon#enter sib2, iclass 7, count 0 2006.173.12:37:01.23#ibcon#flushed, iclass 7, count 0 2006.173.12:37:01.23#ibcon#about to write, iclass 7, count 0 2006.173.12:37:01.23#ibcon#wrote, iclass 7, count 0 2006.173.12:37:01.23#ibcon#about to read 3, iclass 7, count 0 2006.173.12:37:01.25#ibcon#read 3, iclass 7, count 0 2006.173.12:37:01.25#ibcon#about to read 4, iclass 7, count 0 2006.173.12:37:01.25#ibcon#read 4, iclass 7, count 0 2006.173.12:37:01.25#ibcon#about to read 5, iclass 7, count 0 2006.173.12:37:01.25#ibcon#read 5, iclass 7, count 0 2006.173.12:37:01.25#ibcon#about to read 6, iclass 7, count 0 2006.173.12:37:01.25#ibcon#read 6, iclass 7, count 0 2006.173.12:37:01.25#ibcon#end of sib2, iclass 7, count 0 2006.173.12:37:01.25#ibcon#*mode == 0, iclass 7, count 0 2006.173.12:37:01.25#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.12:37:01.25#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.12:37:01.25#ibcon#*before write, iclass 7, count 0 2006.173.12:37:01.25#ibcon#enter sib2, iclass 7, count 0 2006.173.12:37:01.25#ibcon#flushed, iclass 7, count 0 2006.173.12:37:01.25#ibcon#about to write, iclass 7, count 0 2006.173.12:37:01.25#ibcon#wrote, iclass 7, count 0 2006.173.12:37:01.25#ibcon#about to read 3, iclass 7, count 0 2006.173.12:37:01.29#ibcon#read 3, iclass 7, count 0 2006.173.12:37:01.29#ibcon#about to read 4, iclass 7, count 0 2006.173.12:37:01.29#ibcon#read 4, iclass 7, count 0 2006.173.12:37:01.29#ibcon#about to read 5, iclass 7, count 0 2006.173.12:37:01.29#ibcon#read 5, iclass 7, count 0 2006.173.12:37:01.29#ibcon#about to read 6, iclass 7, count 0 2006.173.12:37:01.29#ibcon#read 6, iclass 7, count 0 2006.173.12:37:01.29#ibcon#end of sib2, iclass 7, count 0 2006.173.12:37:01.29#ibcon#*after write, iclass 7, count 0 2006.173.12:37:01.29#ibcon#*before return 0, iclass 7, count 0 2006.173.12:37:01.29#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.12:37:01.29#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.12:37:01.29#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.12:37:01.29#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.12:37:01.29$vck44/vb=2,4 2006.173.12:37:01.29#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.12:37:01.29#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.12:37:01.29#ibcon#ireg 11 cls_cnt 2 2006.173.12:37:01.29#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.12:37:01.35#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.12:37:01.35#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.12:37:01.35#ibcon#enter wrdev, iclass 11, count 2 2006.173.12:37:01.35#ibcon#first serial, iclass 11, count 2 2006.173.12:37:01.35#ibcon#enter sib2, iclass 11, count 2 2006.173.12:37:01.35#ibcon#flushed, iclass 11, count 2 2006.173.12:37:01.35#ibcon#about to write, iclass 11, count 2 2006.173.12:37:01.35#ibcon#wrote, iclass 11, count 2 2006.173.12:37:01.35#ibcon#about to read 3, iclass 11, count 2 2006.173.12:37:01.37#ibcon#read 3, iclass 11, count 2 2006.173.12:37:01.37#ibcon#about to read 4, iclass 11, count 2 2006.173.12:37:01.37#ibcon#read 4, iclass 11, count 2 2006.173.12:37:01.37#ibcon#about to read 5, iclass 11, count 2 2006.173.12:37:01.37#ibcon#read 5, iclass 11, count 2 2006.173.12:37:01.37#ibcon#about to read 6, iclass 11, count 2 2006.173.12:37:01.37#ibcon#read 6, iclass 11, count 2 2006.173.12:37:01.37#ibcon#end of sib2, iclass 11, count 2 2006.173.12:37:01.37#ibcon#*mode == 0, iclass 11, count 2 2006.173.12:37:01.37#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.12:37:01.37#ibcon#[27=AT02-04\r\n] 2006.173.12:37:01.37#ibcon#*before write, iclass 11, count 2 2006.173.12:37:01.37#ibcon#enter sib2, iclass 11, count 2 2006.173.12:37:01.37#ibcon#flushed, iclass 11, count 2 2006.173.12:37:01.37#ibcon#about to write, iclass 11, count 2 2006.173.12:37:01.37#ibcon#wrote, iclass 11, count 2 2006.173.12:37:01.37#ibcon#about to read 3, iclass 11, count 2 2006.173.12:37:01.40#ibcon#read 3, iclass 11, count 2 2006.173.12:37:01.40#ibcon#about to read 4, iclass 11, count 2 2006.173.12:37:01.40#ibcon#read 4, iclass 11, count 2 2006.173.12:37:01.40#ibcon#about to read 5, iclass 11, count 2 2006.173.12:37:01.40#ibcon#read 5, iclass 11, count 2 2006.173.12:37:01.40#ibcon#about to read 6, iclass 11, count 2 2006.173.12:37:01.40#ibcon#read 6, iclass 11, count 2 2006.173.12:37:01.40#ibcon#end of sib2, iclass 11, count 2 2006.173.12:37:01.40#ibcon#*after write, iclass 11, count 2 2006.173.12:37:01.40#ibcon#*before return 0, iclass 11, count 2 2006.173.12:37:01.40#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.12:37:01.40#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.12:37:01.40#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.12:37:01.40#ibcon#ireg 7 cls_cnt 0 2006.173.12:37:01.40#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.12:37:01.52#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.12:37:01.52#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.12:37:01.52#ibcon#enter wrdev, iclass 11, count 0 2006.173.12:37:01.52#ibcon#first serial, iclass 11, count 0 2006.173.12:37:01.52#ibcon#enter sib2, iclass 11, count 0 2006.173.12:37:01.52#ibcon#flushed, iclass 11, count 0 2006.173.12:37:01.52#ibcon#about to write, iclass 11, count 0 2006.173.12:37:01.52#ibcon#wrote, iclass 11, count 0 2006.173.12:37:01.52#ibcon#about to read 3, iclass 11, count 0 2006.173.12:37:01.54#ibcon#read 3, iclass 11, count 0 2006.173.12:37:01.54#ibcon#about to read 4, iclass 11, count 0 2006.173.12:37:01.54#ibcon#read 4, iclass 11, count 0 2006.173.12:37:01.54#ibcon#about to read 5, iclass 11, count 0 2006.173.12:37:01.54#ibcon#read 5, iclass 11, count 0 2006.173.12:37:01.54#ibcon#about to read 6, iclass 11, count 0 2006.173.12:37:01.54#ibcon#read 6, iclass 11, count 0 2006.173.12:37:01.54#ibcon#end of sib2, iclass 11, count 0 2006.173.12:37:01.54#ibcon#*mode == 0, iclass 11, count 0 2006.173.12:37:01.54#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.12:37:01.54#ibcon#[27=USB\r\n] 2006.173.12:37:01.54#ibcon#*before write, iclass 11, count 0 2006.173.12:37:01.54#ibcon#enter sib2, iclass 11, count 0 2006.173.12:37:01.54#ibcon#flushed, iclass 11, count 0 2006.173.12:37:01.54#ibcon#about to write, iclass 11, count 0 2006.173.12:37:01.54#ibcon#wrote, iclass 11, count 0 2006.173.12:37:01.54#ibcon#about to read 3, iclass 11, count 0 2006.173.12:37:01.57#ibcon#read 3, iclass 11, count 0 2006.173.12:37:01.57#ibcon#about to read 4, iclass 11, count 0 2006.173.12:37:01.57#ibcon#read 4, iclass 11, count 0 2006.173.12:37:01.57#ibcon#about to read 5, iclass 11, count 0 2006.173.12:37:01.57#ibcon#read 5, iclass 11, count 0 2006.173.12:37:01.57#ibcon#about to read 6, iclass 11, count 0 2006.173.12:37:01.57#ibcon#read 6, iclass 11, count 0 2006.173.12:37:01.57#ibcon#end of sib2, iclass 11, count 0 2006.173.12:37:01.57#ibcon#*after write, iclass 11, count 0 2006.173.12:37:01.57#ibcon#*before return 0, iclass 11, count 0 2006.173.12:37:01.57#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.12:37:01.57#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.12:37:01.57#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.12:37:01.57#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.12:37:01.57$vck44/vblo=3,649.99 2006.173.12:37:01.57#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.12:37:01.57#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.12:37:01.57#ibcon#ireg 17 cls_cnt 0 2006.173.12:37:01.57#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.12:37:01.57#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.12:37:01.57#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.12:37:01.57#ibcon#enter wrdev, iclass 13, count 0 2006.173.12:37:01.57#ibcon#first serial, iclass 13, count 0 2006.173.12:37:01.57#ibcon#enter sib2, iclass 13, count 0 2006.173.12:37:01.57#ibcon#flushed, iclass 13, count 0 2006.173.12:37:01.57#ibcon#about to write, iclass 13, count 0 2006.173.12:37:01.57#ibcon#wrote, iclass 13, count 0 2006.173.12:37:01.57#ibcon#about to read 3, iclass 13, count 0 2006.173.12:37:01.59#ibcon#read 3, iclass 13, count 0 2006.173.12:37:01.59#ibcon#about to read 4, iclass 13, count 0 2006.173.12:37:01.59#ibcon#read 4, iclass 13, count 0 2006.173.12:37:01.59#ibcon#about to read 5, iclass 13, count 0 2006.173.12:37:01.59#ibcon#read 5, iclass 13, count 0 2006.173.12:37:01.59#ibcon#about to read 6, iclass 13, count 0 2006.173.12:37:01.59#ibcon#read 6, iclass 13, count 0 2006.173.12:37:01.59#ibcon#end of sib2, iclass 13, count 0 2006.173.12:37:01.59#ibcon#*mode == 0, iclass 13, count 0 2006.173.12:37:01.59#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.12:37:01.59#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.12:37:01.59#ibcon#*before write, iclass 13, count 0 2006.173.12:37:01.59#ibcon#enter sib2, iclass 13, count 0 2006.173.12:37:01.59#ibcon#flushed, iclass 13, count 0 2006.173.12:37:01.59#ibcon#about to write, iclass 13, count 0 2006.173.12:37:01.59#ibcon#wrote, iclass 13, count 0 2006.173.12:37:01.59#ibcon#about to read 3, iclass 13, count 0 2006.173.12:37:01.63#ibcon#read 3, iclass 13, count 0 2006.173.12:37:01.63#ibcon#about to read 4, iclass 13, count 0 2006.173.12:37:01.63#ibcon#read 4, iclass 13, count 0 2006.173.12:37:01.63#ibcon#about to read 5, iclass 13, count 0 2006.173.12:37:01.63#ibcon#read 5, iclass 13, count 0 2006.173.12:37:01.63#ibcon#about to read 6, iclass 13, count 0 2006.173.12:37:01.63#ibcon#read 6, iclass 13, count 0 2006.173.12:37:01.63#ibcon#end of sib2, iclass 13, count 0 2006.173.12:37:01.63#ibcon#*after write, iclass 13, count 0 2006.173.12:37:01.63#ibcon#*before return 0, iclass 13, count 0 2006.173.12:37:01.63#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.12:37:01.63#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.12:37:01.63#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.12:37:01.63#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.12:37:01.63$vck44/vb=3,4 2006.173.12:37:01.63#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.12:37:01.63#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.12:37:01.63#ibcon#ireg 11 cls_cnt 2 2006.173.12:37:01.63#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.12:37:01.69#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.12:37:01.69#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.12:37:01.69#ibcon#enter wrdev, iclass 15, count 2 2006.173.12:37:01.69#ibcon#first serial, iclass 15, count 2 2006.173.12:37:01.69#ibcon#enter sib2, iclass 15, count 2 2006.173.12:37:01.69#ibcon#flushed, iclass 15, count 2 2006.173.12:37:01.69#ibcon#about to write, iclass 15, count 2 2006.173.12:37:01.69#ibcon#wrote, iclass 15, count 2 2006.173.12:37:01.69#ibcon#about to read 3, iclass 15, count 2 2006.173.12:37:01.71#ibcon#read 3, iclass 15, count 2 2006.173.12:37:01.71#ibcon#about to read 4, iclass 15, count 2 2006.173.12:37:01.71#ibcon#read 4, iclass 15, count 2 2006.173.12:37:01.71#ibcon#about to read 5, iclass 15, count 2 2006.173.12:37:01.71#ibcon#read 5, iclass 15, count 2 2006.173.12:37:01.71#ibcon#about to read 6, iclass 15, count 2 2006.173.12:37:01.71#ibcon#read 6, iclass 15, count 2 2006.173.12:37:01.71#ibcon#end of sib2, iclass 15, count 2 2006.173.12:37:01.71#ibcon#*mode == 0, iclass 15, count 2 2006.173.12:37:01.71#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.12:37:01.71#ibcon#[27=AT03-04\r\n] 2006.173.12:37:01.71#ibcon#*before write, iclass 15, count 2 2006.173.12:37:01.71#ibcon#enter sib2, iclass 15, count 2 2006.173.12:37:01.71#ibcon#flushed, iclass 15, count 2 2006.173.12:37:01.71#ibcon#about to write, iclass 15, count 2 2006.173.12:37:01.71#ibcon#wrote, iclass 15, count 2 2006.173.12:37:01.71#ibcon#about to read 3, iclass 15, count 2 2006.173.12:37:01.74#ibcon#read 3, iclass 15, count 2 2006.173.12:37:01.74#ibcon#about to read 4, iclass 15, count 2 2006.173.12:37:01.74#ibcon#read 4, iclass 15, count 2 2006.173.12:37:01.74#ibcon#about to read 5, iclass 15, count 2 2006.173.12:37:01.74#ibcon#read 5, iclass 15, count 2 2006.173.12:37:01.74#ibcon#about to read 6, iclass 15, count 2 2006.173.12:37:01.74#ibcon#read 6, iclass 15, count 2 2006.173.12:37:01.74#ibcon#end of sib2, iclass 15, count 2 2006.173.12:37:01.74#ibcon#*after write, iclass 15, count 2 2006.173.12:37:01.74#ibcon#*before return 0, iclass 15, count 2 2006.173.12:37:01.74#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.12:37:01.74#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.12:37:01.74#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.12:37:01.74#ibcon#ireg 7 cls_cnt 0 2006.173.12:37:01.74#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.12:37:01.86#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.12:37:01.86#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.12:37:01.86#ibcon#enter wrdev, iclass 15, count 0 2006.173.12:37:01.86#ibcon#first serial, iclass 15, count 0 2006.173.12:37:01.86#ibcon#enter sib2, iclass 15, count 0 2006.173.12:37:01.86#ibcon#flushed, iclass 15, count 0 2006.173.12:37:01.86#ibcon#about to write, iclass 15, count 0 2006.173.12:37:01.86#ibcon#wrote, iclass 15, count 0 2006.173.12:37:01.86#ibcon#about to read 3, iclass 15, count 0 2006.173.12:37:01.88#ibcon#read 3, iclass 15, count 0 2006.173.12:37:01.88#ibcon#about to read 4, iclass 15, count 0 2006.173.12:37:01.88#ibcon#read 4, iclass 15, count 0 2006.173.12:37:01.88#ibcon#about to read 5, iclass 15, count 0 2006.173.12:37:01.88#ibcon#read 5, iclass 15, count 0 2006.173.12:37:01.88#ibcon#about to read 6, iclass 15, count 0 2006.173.12:37:01.88#ibcon#read 6, iclass 15, count 0 2006.173.12:37:01.88#ibcon#end of sib2, iclass 15, count 0 2006.173.12:37:01.88#ibcon#*mode == 0, iclass 15, count 0 2006.173.12:37:01.88#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.12:37:01.88#ibcon#[27=USB\r\n] 2006.173.12:37:01.88#ibcon#*before write, iclass 15, count 0 2006.173.12:37:01.88#ibcon#enter sib2, iclass 15, count 0 2006.173.12:37:01.88#ibcon#flushed, iclass 15, count 0 2006.173.12:37:01.88#ibcon#about to write, iclass 15, count 0 2006.173.12:37:01.88#ibcon#wrote, iclass 15, count 0 2006.173.12:37:01.88#ibcon#about to read 3, iclass 15, count 0 2006.173.12:37:01.91#ibcon#read 3, iclass 15, count 0 2006.173.12:37:01.91#ibcon#about to read 4, iclass 15, count 0 2006.173.12:37:01.91#ibcon#read 4, iclass 15, count 0 2006.173.12:37:01.91#ibcon#about to read 5, iclass 15, count 0 2006.173.12:37:01.91#ibcon#read 5, iclass 15, count 0 2006.173.12:37:01.91#ibcon#about to read 6, iclass 15, count 0 2006.173.12:37:01.91#ibcon#read 6, iclass 15, count 0 2006.173.12:37:01.91#ibcon#end of sib2, iclass 15, count 0 2006.173.12:37:01.91#ibcon#*after write, iclass 15, count 0 2006.173.12:37:01.91#ibcon#*before return 0, iclass 15, count 0 2006.173.12:37:01.91#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.12:37:01.91#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.12:37:01.91#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.12:37:01.91#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.12:37:01.91$vck44/vblo=4,679.99 2006.173.12:37:01.91#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.12:37:01.91#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.12:37:01.91#ibcon#ireg 17 cls_cnt 0 2006.173.12:37:01.91#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.12:37:01.91#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.12:37:01.91#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.12:37:01.91#ibcon#enter wrdev, iclass 17, count 0 2006.173.12:37:01.91#ibcon#first serial, iclass 17, count 0 2006.173.12:37:01.91#ibcon#enter sib2, iclass 17, count 0 2006.173.12:37:01.91#ibcon#flushed, iclass 17, count 0 2006.173.12:37:01.91#ibcon#about to write, iclass 17, count 0 2006.173.12:37:01.91#ibcon#wrote, iclass 17, count 0 2006.173.12:37:01.91#ibcon#about to read 3, iclass 17, count 0 2006.173.12:37:01.93#ibcon#read 3, iclass 17, count 0 2006.173.12:37:01.93#ibcon#about to read 4, iclass 17, count 0 2006.173.12:37:01.93#ibcon#read 4, iclass 17, count 0 2006.173.12:37:01.93#ibcon#about to read 5, iclass 17, count 0 2006.173.12:37:01.93#ibcon#read 5, iclass 17, count 0 2006.173.12:37:01.93#ibcon#about to read 6, iclass 17, count 0 2006.173.12:37:01.93#ibcon#read 6, iclass 17, count 0 2006.173.12:37:01.93#ibcon#end of sib2, iclass 17, count 0 2006.173.12:37:01.93#ibcon#*mode == 0, iclass 17, count 0 2006.173.12:37:01.93#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.12:37:01.93#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.12:37:01.93#ibcon#*before write, iclass 17, count 0 2006.173.12:37:01.93#ibcon#enter sib2, iclass 17, count 0 2006.173.12:37:01.93#ibcon#flushed, iclass 17, count 0 2006.173.12:37:01.93#ibcon#about to write, iclass 17, count 0 2006.173.12:37:01.93#ibcon#wrote, iclass 17, count 0 2006.173.12:37:01.93#ibcon#about to read 3, iclass 17, count 0 2006.173.12:37:01.97#ibcon#read 3, iclass 17, count 0 2006.173.12:37:01.97#ibcon#about to read 4, iclass 17, count 0 2006.173.12:37:01.97#ibcon#read 4, iclass 17, count 0 2006.173.12:37:01.97#ibcon#about to read 5, iclass 17, count 0 2006.173.12:37:01.97#ibcon#read 5, iclass 17, count 0 2006.173.12:37:01.97#ibcon#about to read 6, iclass 17, count 0 2006.173.12:37:01.97#ibcon#read 6, iclass 17, count 0 2006.173.12:37:01.97#ibcon#end of sib2, iclass 17, count 0 2006.173.12:37:01.97#ibcon#*after write, iclass 17, count 0 2006.173.12:37:01.97#ibcon#*before return 0, iclass 17, count 0 2006.173.12:37:01.97#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.12:37:01.97#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.12:37:01.97#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.12:37:01.97#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.12:37:01.97$vck44/vb=4,4 2006.173.12:37:01.97#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.12:37:01.97#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.12:37:01.97#ibcon#ireg 11 cls_cnt 2 2006.173.12:37:01.97#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.12:37:02.03#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.12:37:02.03#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.12:37:02.03#ibcon#enter wrdev, iclass 19, count 2 2006.173.12:37:02.03#ibcon#first serial, iclass 19, count 2 2006.173.12:37:02.03#ibcon#enter sib2, iclass 19, count 2 2006.173.12:37:02.03#ibcon#flushed, iclass 19, count 2 2006.173.12:37:02.03#ibcon#about to write, iclass 19, count 2 2006.173.12:37:02.03#ibcon#wrote, iclass 19, count 2 2006.173.12:37:02.03#ibcon#about to read 3, iclass 19, count 2 2006.173.12:37:02.05#ibcon#read 3, iclass 19, count 2 2006.173.12:37:02.05#ibcon#about to read 4, iclass 19, count 2 2006.173.12:37:02.05#ibcon#read 4, iclass 19, count 2 2006.173.12:37:02.05#ibcon#about to read 5, iclass 19, count 2 2006.173.12:37:02.05#ibcon#read 5, iclass 19, count 2 2006.173.12:37:02.05#ibcon#about to read 6, iclass 19, count 2 2006.173.12:37:02.05#ibcon#read 6, iclass 19, count 2 2006.173.12:37:02.05#ibcon#end of sib2, iclass 19, count 2 2006.173.12:37:02.05#ibcon#*mode == 0, iclass 19, count 2 2006.173.12:37:02.05#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.12:37:02.05#ibcon#[27=AT04-04\r\n] 2006.173.12:37:02.05#ibcon#*before write, iclass 19, count 2 2006.173.12:37:02.05#ibcon#enter sib2, iclass 19, count 2 2006.173.12:37:02.05#ibcon#flushed, iclass 19, count 2 2006.173.12:37:02.05#ibcon#about to write, iclass 19, count 2 2006.173.12:37:02.05#ibcon#wrote, iclass 19, count 2 2006.173.12:37:02.05#ibcon#about to read 3, iclass 19, count 2 2006.173.12:37:02.08#ibcon#read 3, iclass 19, count 2 2006.173.12:37:02.08#ibcon#about to read 4, iclass 19, count 2 2006.173.12:37:02.08#ibcon#read 4, iclass 19, count 2 2006.173.12:37:02.08#ibcon#about to read 5, iclass 19, count 2 2006.173.12:37:02.08#ibcon#read 5, iclass 19, count 2 2006.173.12:37:02.08#ibcon#about to read 6, iclass 19, count 2 2006.173.12:37:02.08#ibcon#read 6, iclass 19, count 2 2006.173.12:37:02.08#ibcon#end of sib2, iclass 19, count 2 2006.173.12:37:02.08#ibcon#*after write, iclass 19, count 2 2006.173.12:37:02.08#ibcon#*before return 0, iclass 19, count 2 2006.173.12:37:02.08#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.12:37:02.08#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.12:37:02.08#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.12:37:02.08#ibcon#ireg 7 cls_cnt 0 2006.173.12:37:02.08#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.12:37:02.20#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.12:37:02.20#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.12:37:02.20#ibcon#enter wrdev, iclass 19, count 0 2006.173.12:37:02.20#ibcon#first serial, iclass 19, count 0 2006.173.12:37:02.20#ibcon#enter sib2, iclass 19, count 0 2006.173.12:37:02.20#ibcon#flushed, iclass 19, count 0 2006.173.12:37:02.20#ibcon#about to write, iclass 19, count 0 2006.173.12:37:02.20#ibcon#wrote, iclass 19, count 0 2006.173.12:37:02.20#ibcon#about to read 3, iclass 19, count 0 2006.173.12:37:02.22#ibcon#read 3, iclass 19, count 0 2006.173.12:37:02.22#ibcon#about to read 4, iclass 19, count 0 2006.173.12:37:02.22#ibcon#read 4, iclass 19, count 0 2006.173.12:37:02.22#ibcon#about to read 5, iclass 19, count 0 2006.173.12:37:02.22#ibcon#read 5, iclass 19, count 0 2006.173.12:37:02.22#ibcon#about to read 6, iclass 19, count 0 2006.173.12:37:02.22#ibcon#read 6, iclass 19, count 0 2006.173.12:37:02.22#ibcon#end of sib2, iclass 19, count 0 2006.173.12:37:02.22#ibcon#*mode == 0, iclass 19, count 0 2006.173.12:37:02.22#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.12:37:02.22#ibcon#[27=USB\r\n] 2006.173.12:37:02.22#ibcon#*before write, iclass 19, count 0 2006.173.12:37:02.22#ibcon#enter sib2, iclass 19, count 0 2006.173.12:37:02.22#ibcon#flushed, iclass 19, count 0 2006.173.12:37:02.22#ibcon#about to write, iclass 19, count 0 2006.173.12:37:02.22#ibcon#wrote, iclass 19, count 0 2006.173.12:37:02.22#ibcon#about to read 3, iclass 19, count 0 2006.173.12:37:02.25#ibcon#read 3, iclass 19, count 0 2006.173.12:37:02.25#ibcon#about to read 4, iclass 19, count 0 2006.173.12:37:02.25#ibcon#read 4, iclass 19, count 0 2006.173.12:37:02.25#ibcon#about to read 5, iclass 19, count 0 2006.173.12:37:02.25#ibcon#read 5, iclass 19, count 0 2006.173.12:37:02.25#ibcon#about to read 6, iclass 19, count 0 2006.173.12:37:02.25#ibcon#read 6, iclass 19, count 0 2006.173.12:37:02.25#ibcon#end of sib2, iclass 19, count 0 2006.173.12:37:02.25#ibcon#*after write, iclass 19, count 0 2006.173.12:37:02.25#ibcon#*before return 0, iclass 19, count 0 2006.173.12:37:02.25#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.12:37:02.25#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.12:37:02.25#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.12:37:02.25#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.12:37:02.25$vck44/vblo=5,709.99 2006.173.12:37:02.25#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.12:37:02.25#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.12:37:02.25#ibcon#ireg 17 cls_cnt 0 2006.173.12:37:02.25#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.12:37:02.25#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.12:37:02.25#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.12:37:02.25#ibcon#enter wrdev, iclass 21, count 0 2006.173.12:37:02.25#ibcon#first serial, iclass 21, count 0 2006.173.12:37:02.25#ibcon#enter sib2, iclass 21, count 0 2006.173.12:37:02.25#ibcon#flushed, iclass 21, count 0 2006.173.12:37:02.25#ibcon#about to write, iclass 21, count 0 2006.173.12:37:02.25#ibcon#wrote, iclass 21, count 0 2006.173.12:37:02.25#ibcon#about to read 3, iclass 21, count 0 2006.173.12:37:02.27#ibcon#read 3, iclass 21, count 0 2006.173.12:37:02.27#ibcon#about to read 4, iclass 21, count 0 2006.173.12:37:02.27#ibcon#read 4, iclass 21, count 0 2006.173.12:37:02.27#ibcon#about to read 5, iclass 21, count 0 2006.173.12:37:02.27#ibcon#read 5, iclass 21, count 0 2006.173.12:37:02.27#ibcon#about to read 6, iclass 21, count 0 2006.173.12:37:02.27#ibcon#read 6, iclass 21, count 0 2006.173.12:37:02.27#ibcon#end of sib2, iclass 21, count 0 2006.173.12:37:02.27#ibcon#*mode == 0, iclass 21, count 0 2006.173.12:37:02.27#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.12:37:02.27#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.12:37:02.27#ibcon#*before write, iclass 21, count 0 2006.173.12:37:02.27#ibcon#enter sib2, iclass 21, count 0 2006.173.12:37:02.27#ibcon#flushed, iclass 21, count 0 2006.173.12:37:02.27#ibcon#about to write, iclass 21, count 0 2006.173.12:37:02.27#ibcon#wrote, iclass 21, count 0 2006.173.12:37:02.27#ibcon#about to read 3, iclass 21, count 0 2006.173.12:37:02.31#ibcon#read 3, iclass 21, count 0 2006.173.12:37:02.31#ibcon#about to read 4, iclass 21, count 0 2006.173.12:37:02.31#ibcon#read 4, iclass 21, count 0 2006.173.12:37:02.31#ibcon#about to read 5, iclass 21, count 0 2006.173.12:37:02.31#ibcon#read 5, iclass 21, count 0 2006.173.12:37:02.31#ibcon#about to read 6, iclass 21, count 0 2006.173.12:37:02.31#ibcon#read 6, iclass 21, count 0 2006.173.12:37:02.31#ibcon#end of sib2, iclass 21, count 0 2006.173.12:37:02.31#ibcon#*after write, iclass 21, count 0 2006.173.12:37:02.31#ibcon#*before return 0, iclass 21, count 0 2006.173.12:37:02.31#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.12:37:02.31#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.12:37:02.31#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.12:37:02.31#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.12:37:02.31$vck44/vb=5,4 2006.173.12:37:02.31#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.12:37:02.31#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.12:37:02.31#ibcon#ireg 11 cls_cnt 2 2006.173.12:37:02.31#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.12:37:02.37#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.12:37:02.37#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.12:37:02.37#ibcon#enter wrdev, iclass 23, count 2 2006.173.12:37:02.37#ibcon#first serial, iclass 23, count 2 2006.173.12:37:02.37#ibcon#enter sib2, iclass 23, count 2 2006.173.12:37:02.37#ibcon#flushed, iclass 23, count 2 2006.173.12:37:02.37#ibcon#about to write, iclass 23, count 2 2006.173.12:37:02.37#ibcon#wrote, iclass 23, count 2 2006.173.12:37:02.37#ibcon#about to read 3, iclass 23, count 2 2006.173.12:37:02.39#ibcon#read 3, iclass 23, count 2 2006.173.12:37:02.39#ibcon#about to read 4, iclass 23, count 2 2006.173.12:37:02.39#ibcon#read 4, iclass 23, count 2 2006.173.12:37:02.39#ibcon#about to read 5, iclass 23, count 2 2006.173.12:37:02.39#ibcon#read 5, iclass 23, count 2 2006.173.12:37:02.39#ibcon#about to read 6, iclass 23, count 2 2006.173.12:37:02.39#ibcon#read 6, iclass 23, count 2 2006.173.12:37:02.39#ibcon#end of sib2, iclass 23, count 2 2006.173.12:37:02.39#ibcon#*mode == 0, iclass 23, count 2 2006.173.12:37:02.39#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.12:37:02.39#ibcon#[27=AT05-04\r\n] 2006.173.12:37:02.39#ibcon#*before write, iclass 23, count 2 2006.173.12:37:02.39#ibcon#enter sib2, iclass 23, count 2 2006.173.12:37:02.39#ibcon#flushed, iclass 23, count 2 2006.173.12:37:02.39#ibcon#about to write, iclass 23, count 2 2006.173.12:37:02.39#ibcon#wrote, iclass 23, count 2 2006.173.12:37:02.39#ibcon#about to read 3, iclass 23, count 2 2006.173.12:37:02.42#ibcon#read 3, iclass 23, count 2 2006.173.12:37:02.42#ibcon#about to read 4, iclass 23, count 2 2006.173.12:37:02.42#ibcon#read 4, iclass 23, count 2 2006.173.12:37:02.42#ibcon#about to read 5, iclass 23, count 2 2006.173.12:37:02.42#ibcon#read 5, iclass 23, count 2 2006.173.12:37:02.42#ibcon#about to read 6, iclass 23, count 2 2006.173.12:37:02.42#ibcon#read 6, iclass 23, count 2 2006.173.12:37:02.42#ibcon#end of sib2, iclass 23, count 2 2006.173.12:37:02.42#ibcon#*after write, iclass 23, count 2 2006.173.12:37:02.42#ibcon#*before return 0, iclass 23, count 2 2006.173.12:37:02.42#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.12:37:02.42#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.12:37:02.42#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.12:37:02.42#ibcon#ireg 7 cls_cnt 0 2006.173.12:37:02.42#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.12:37:02.54#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.12:37:02.54#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.12:37:02.54#ibcon#enter wrdev, iclass 23, count 0 2006.173.12:37:02.54#ibcon#first serial, iclass 23, count 0 2006.173.12:37:02.54#ibcon#enter sib2, iclass 23, count 0 2006.173.12:37:02.54#ibcon#flushed, iclass 23, count 0 2006.173.12:37:02.54#ibcon#about to write, iclass 23, count 0 2006.173.12:37:02.54#ibcon#wrote, iclass 23, count 0 2006.173.12:37:02.54#ibcon#about to read 3, iclass 23, count 0 2006.173.12:37:02.56#ibcon#read 3, iclass 23, count 0 2006.173.12:37:02.56#ibcon#about to read 4, iclass 23, count 0 2006.173.12:37:02.56#ibcon#read 4, iclass 23, count 0 2006.173.12:37:02.56#ibcon#about to read 5, iclass 23, count 0 2006.173.12:37:02.56#ibcon#read 5, iclass 23, count 0 2006.173.12:37:02.56#ibcon#about to read 6, iclass 23, count 0 2006.173.12:37:02.56#ibcon#read 6, iclass 23, count 0 2006.173.12:37:02.56#ibcon#end of sib2, iclass 23, count 0 2006.173.12:37:02.56#ibcon#*mode == 0, iclass 23, count 0 2006.173.12:37:02.56#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.12:37:02.56#ibcon#[27=USB\r\n] 2006.173.12:37:02.56#ibcon#*before write, iclass 23, count 0 2006.173.12:37:02.56#ibcon#enter sib2, iclass 23, count 0 2006.173.12:37:02.56#ibcon#flushed, iclass 23, count 0 2006.173.12:37:02.56#ibcon#about to write, iclass 23, count 0 2006.173.12:37:02.56#ibcon#wrote, iclass 23, count 0 2006.173.12:37:02.56#ibcon#about to read 3, iclass 23, count 0 2006.173.12:37:02.59#ibcon#read 3, iclass 23, count 0 2006.173.12:37:02.59#ibcon#about to read 4, iclass 23, count 0 2006.173.12:37:02.59#ibcon#read 4, iclass 23, count 0 2006.173.12:37:02.59#ibcon#about to read 5, iclass 23, count 0 2006.173.12:37:02.59#ibcon#read 5, iclass 23, count 0 2006.173.12:37:02.59#ibcon#about to read 6, iclass 23, count 0 2006.173.12:37:02.59#ibcon#read 6, iclass 23, count 0 2006.173.12:37:02.59#ibcon#end of sib2, iclass 23, count 0 2006.173.12:37:02.59#ibcon#*after write, iclass 23, count 0 2006.173.12:37:02.59#ibcon#*before return 0, iclass 23, count 0 2006.173.12:37:02.59#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.12:37:02.59#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.12:37:02.59#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.12:37:02.59#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.12:37:02.59$vck44/vblo=6,719.99 2006.173.12:37:02.59#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.12:37:02.59#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.12:37:02.59#ibcon#ireg 17 cls_cnt 0 2006.173.12:37:02.59#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.12:37:02.59#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.12:37:02.59#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.12:37:02.59#ibcon#enter wrdev, iclass 25, count 0 2006.173.12:37:02.59#ibcon#first serial, iclass 25, count 0 2006.173.12:37:02.59#ibcon#enter sib2, iclass 25, count 0 2006.173.12:37:02.59#ibcon#flushed, iclass 25, count 0 2006.173.12:37:02.59#ibcon#about to write, iclass 25, count 0 2006.173.12:37:02.59#ibcon#wrote, iclass 25, count 0 2006.173.12:37:02.59#ibcon#about to read 3, iclass 25, count 0 2006.173.12:37:02.61#ibcon#read 3, iclass 25, count 0 2006.173.12:37:02.61#ibcon#about to read 4, iclass 25, count 0 2006.173.12:37:02.61#ibcon#read 4, iclass 25, count 0 2006.173.12:37:02.61#ibcon#about to read 5, iclass 25, count 0 2006.173.12:37:02.61#ibcon#read 5, iclass 25, count 0 2006.173.12:37:02.61#ibcon#about to read 6, iclass 25, count 0 2006.173.12:37:02.61#ibcon#read 6, iclass 25, count 0 2006.173.12:37:02.61#ibcon#end of sib2, iclass 25, count 0 2006.173.12:37:02.61#ibcon#*mode == 0, iclass 25, count 0 2006.173.12:37:02.61#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.12:37:02.61#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.12:37:02.61#ibcon#*before write, iclass 25, count 0 2006.173.12:37:02.61#ibcon#enter sib2, iclass 25, count 0 2006.173.12:37:02.61#ibcon#flushed, iclass 25, count 0 2006.173.12:37:02.61#ibcon#about to write, iclass 25, count 0 2006.173.12:37:02.61#ibcon#wrote, iclass 25, count 0 2006.173.12:37:02.61#ibcon#about to read 3, iclass 25, count 0 2006.173.12:37:02.65#ibcon#read 3, iclass 25, count 0 2006.173.12:37:02.65#ibcon#about to read 4, iclass 25, count 0 2006.173.12:37:02.65#ibcon#read 4, iclass 25, count 0 2006.173.12:37:02.65#ibcon#about to read 5, iclass 25, count 0 2006.173.12:37:02.65#ibcon#read 5, iclass 25, count 0 2006.173.12:37:02.65#ibcon#about to read 6, iclass 25, count 0 2006.173.12:37:02.65#ibcon#read 6, iclass 25, count 0 2006.173.12:37:02.65#ibcon#end of sib2, iclass 25, count 0 2006.173.12:37:02.65#ibcon#*after write, iclass 25, count 0 2006.173.12:37:02.65#ibcon#*before return 0, iclass 25, count 0 2006.173.12:37:02.65#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.12:37:02.65#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.12:37:02.65#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.12:37:02.65#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.12:37:02.65$vck44/vb=6,4 2006.173.12:37:02.65#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.12:37:02.65#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.12:37:02.65#ibcon#ireg 11 cls_cnt 2 2006.173.12:37:02.65#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.12:37:02.71#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.12:37:02.71#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.12:37:02.71#ibcon#enter wrdev, iclass 27, count 2 2006.173.12:37:02.71#ibcon#first serial, iclass 27, count 2 2006.173.12:37:02.71#ibcon#enter sib2, iclass 27, count 2 2006.173.12:37:02.71#ibcon#flushed, iclass 27, count 2 2006.173.12:37:02.71#ibcon#about to write, iclass 27, count 2 2006.173.12:37:02.71#ibcon#wrote, iclass 27, count 2 2006.173.12:37:02.71#ibcon#about to read 3, iclass 27, count 2 2006.173.12:37:02.73#ibcon#read 3, iclass 27, count 2 2006.173.12:37:02.73#ibcon#about to read 4, iclass 27, count 2 2006.173.12:37:02.73#ibcon#read 4, iclass 27, count 2 2006.173.12:37:02.73#ibcon#about to read 5, iclass 27, count 2 2006.173.12:37:02.73#ibcon#read 5, iclass 27, count 2 2006.173.12:37:02.73#ibcon#about to read 6, iclass 27, count 2 2006.173.12:37:02.73#ibcon#read 6, iclass 27, count 2 2006.173.12:37:02.73#ibcon#end of sib2, iclass 27, count 2 2006.173.12:37:02.73#ibcon#*mode == 0, iclass 27, count 2 2006.173.12:37:02.73#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.12:37:02.73#ibcon#[27=AT06-04\r\n] 2006.173.12:37:02.73#ibcon#*before write, iclass 27, count 2 2006.173.12:37:02.73#ibcon#enter sib2, iclass 27, count 2 2006.173.12:37:02.73#ibcon#flushed, iclass 27, count 2 2006.173.12:37:02.73#ibcon#about to write, iclass 27, count 2 2006.173.12:37:02.73#ibcon#wrote, iclass 27, count 2 2006.173.12:37:02.73#ibcon#about to read 3, iclass 27, count 2 2006.173.12:37:02.76#ibcon#read 3, iclass 27, count 2 2006.173.12:37:02.76#ibcon#about to read 4, iclass 27, count 2 2006.173.12:37:02.76#ibcon#read 4, iclass 27, count 2 2006.173.12:37:02.76#ibcon#about to read 5, iclass 27, count 2 2006.173.12:37:02.76#ibcon#read 5, iclass 27, count 2 2006.173.12:37:02.76#ibcon#about to read 6, iclass 27, count 2 2006.173.12:37:02.76#ibcon#read 6, iclass 27, count 2 2006.173.12:37:02.76#ibcon#end of sib2, iclass 27, count 2 2006.173.12:37:02.76#ibcon#*after write, iclass 27, count 2 2006.173.12:37:02.76#ibcon#*before return 0, iclass 27, count 2 2006.173.12:37:02.76#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.12:37:02.76#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.12:37:02.76#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.12:37:02.76#ibcon#ireg 7 cls_cnt 0 2006.173.12:37:02.76#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.12:37:02.88#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.12:37:02.88#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.12:37:02.88#ibcon#enter wrdev, iclass 27, count 0 2006.173.12:37:02.88#ibcon#first serial, iclass 27, count 0 2006.173.12:37:02.88#ibcon#enter sib2, iclass 27, count 0 2006.173.12:37:02.88#ibcon#flushed, iclass 27, count 0 2006.173.12:37:02.88#ibcon#about to write, iclass 27, count 0 2006.173.12:37:02.88#ibcon#wrote, iclass 27, count 0 2006.173.12:37:02.88#ibcon#about to read 3, iclass 27, count 0 2006.173.12:37:02.90#ibcon#read 3, iclass 27, count 0 2006.173.12:37:02.90#ibcon#about to read 4, iclass 27, count 0 2006.173.12:37:02.90#ibcon#read 4, iclass 27, count 0 2006.173.12:37:02.90#ibcon#about to read 5, iclass 27, count 0 2006.173.12:37:02.90#ibcon#read 5, iclass 27, count 0 2006.173.12:37:02.90#ibcon#about to read 6, iclass 27, count 0 2006.173.12:37:02.90#ibcon#read 6, iclass 27, count 0 2006.173.12:37:02.90#ibcon#end of sib2, iclass 27, count 0 2006.173.12:37:02.90#ibcon#*mode == 0, iclass 27, count 0 2006.173.12:37:02.90#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.12:37:02.90#ibcon#[27=USB\r\n] 2006.173.12:37:02.90#ibcon#*before write, iclass 27, count 0 2006.173.12:37:02.90#ibcon#enter sib2, iclass 27, count 0 2006.173.12:37:02.90#ibcon#flushed, iclass 27, count 0 2006.173.12:37:02.90#ibcon#about to write, iclass 27, count 0 2006.173.12:37:02.90#ibcon#wrote, iclass 27, count 0 2006.173.12:37:02.90#ibcon#about to read 3, iclass 27, count 0 2006.173.12:37:02.93#ibcon#read 3, iclass 27, count 0 2006.173.12:37:02.93#ibcon#about to read 4, iclass 27, count 0 2006.173.12:37:02.93#ibcon#read 4, iclass 27, count 0 2006.173.12:37:02.93#ibcon#about to read 5, iclass 27, count 0 2006.173.12:37:02.93#ibcon#read 5, iclass 27, count 0 2006.173.12:37:02.93#ibcon#about to read 6, iclass 27, count 0 2006.173.12:37:02.93#ibcon#read 6, iclass 27, count 0 2006.173.12:37:02.93#ibcon#end of sib2, iclass 27, count 0 2006.173.12:37:02.93#ibcon#*after write, iclass 27, count 0 2006.173.12:37:02.93#ibcon#*before return 0, iclass 27, count 0 2006.173.12:37:02.93#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.12:37:02.93#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.12:37:02.93#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.12:37:02.93#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.12:37:02.93$vck44/vblo=7,734.99 2006.173.12:37:02.93#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.12:37:02.93#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.12:37:02.93#ibcon#ireg 17 cls_cnt 0 2006.173.12:37:02.93#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.12:37:02.93#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.12:37:02.93#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.12:37:02.93#ibcon#enter wrdev, iclass 29, count 0 2006.173.12:37:02.93#ibcon#first serial, iclass 29, count 0 2006.173.12:37:02.93#ibcon#enter sib2, iclass 29, count 0 2006.173.12:37:02.93#ibcon#flushed, iclass 29, count 0 2006.173.12:37:02.93#ibcon#about to write, iclass 29, count 0 2006.173.12:37:02.93#ibcon#wrote, iclass 29, count 0 2006.173.12:37:02.93#ibcon#about to read 3, iclass 29, count 0 2006.173.12:37:02.95#ibcon#read 3, iclass 29, count 0 2006.173.12:37:02.95#ibcon#about to read 4, iclass 29, count 0 2006.173.12:37:02.95#ibcon#read 4, iclass 29, count 0 2006.173.12:37:02.95#ibcon#about to read 5, iclass 29, count 0 2006.173.12:37:02.95#ibcon#read 5, iclass 29, count 0 2006.173.12:37:02.95#ibcon#about to read 6, iclass 29, count 0 2006.173.12:37:02.95#ibcon#read 6, iclass 29, count 0 2006.173.12:37:02.95#ibcon#end of sib2, iclass 29, count 0 2006.173.12:37:02.95#ibcon#*mode == 0, iclass 29, count 0 2006.173.12:37:02.95#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.12:37:02.95#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.12:37:02.95#ibcon#*before write, iclass 29, count 0 2006.173.12:37:02.95#ibcon#enter sib2, iclass 29, count 0 2006.173.12:37:02.95#ibcon#flushed, iclass 29, count 0 2006.173.12:37:02.95#ibcon#about to write, iclass 29, count 0 2006.173.12:37:02.95#ibcon#wrote, iclass 29, count 0 2006.173.12:37:02.95#ibcon#about to read 3, iclass 29, count 0 2006.173.12:37:02.99#ibcon#read 3, iclass 29, count 0 2006.173.12:37:02.99#ibcon#about to read 4, iclass 29, count 0 2006.173.12:37:02.99#ibcon#read 4, iclass 29, count 0 2006.173.12:37:02.99#ibcon#about to read 5, iclass 29, count 0 2006.173.12:37:02.99#ibcon#read 5, iclass 29, count 0 2006.173.12:37:02.99#ibcon#about to read 6, iclass 29, count 0 2006.173.12:37:02.99#ibcon#read 6, iclass 29, count 0 2006.173.12:37:02.99#ibcon#end of sib2, iclass 29, count 0 2006.173.12:37:02.99#ibcon#*after write, iclass 29, count 0 2006.173.12:37:02.99#ibcon#*before return 0, iclass 29, count 0 2006.173.12:37:02.99#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.12:37:02.99#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.12:37:02.99#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.12:37:02.99#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.12:37:02.99$vck44/vb=7,4 2006.173.12:37:02.99#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.12:37:02.99#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.12:37:02.99#ibcon#ireg 11 cls_cnt 2 2006.173.12:37:02.99#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.12:37:03.05#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.12:37:03.05#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.12:37:03.05#ibcon#enter wrdev, iclass 31, count 2 2006.173.12:37:03.05#ibcon#first serial, iclass 31, count 2 2006.173.12:37:03.05#ibcon#enter sib2, iclass 31, count 2 2006.173.12:37:03.05#ibcon#flushed, iclass 31, count 2 2006.173.12:37:03.05#ibcon#about to write, iclass 31, count 2 2006.173.12:37:03.05#ibcon#wrote, iclass 31, count 2 2006.173.12:37:03.05#ibcon#about to read 3, iclass 31, count 2 2006.173.12:37:03.07#ibcon#read 3, iclass 31, count 2 2006.173.12:37:03.07#ibcon#about to read 4, iclass 31, count 2 2006.173.12:37:03.07#ibcon#read 4, iclass 31, count 2 2006.173.12:37:03.07#ibcon#about to read 5, iclass 31, count 2 2006.173.12:37:03.07#ibcon#read 5, iclass 31, count 2 2006.173.12:37:03.07#ibcon#about to read 6, iclass 31, count 2 2006.173.12:37:03.07#ibcon#read 6, iclass 31, count 2 2006.173.12:37:03.07#ibcon#end of sib2, iclass 31, count 2 2006.173.12:37:03.07#ibcon#*mode == 0, iclass 31, count 2 2006.173.12:37:03.07#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.12:37:03.07#ibcon#[27=AT07-04\r\n] 2006.173.12:37:03.07#ibcon#*before write, iclass 31, count 2 2006.173.12:37:03.07#ibcon#enter sib2, iclass 31, count 2 2006.173.12:37:03.07#ibcon#flushed, iclass 31, count 2 2006.173.12:37:03.07#ibcon#about to write, iclass 31, count 2 2006.173.12:37:03.07#ibcon#wrote, iclass 31, count 2 2006.173.12:37:03.07#ibcon#about to read 3, iclass 31, count 2 2006.173.12:37:03.10#ibcon#read 3, iclass 31, count 2 2006.173.12:37:03.10#ibcon#about to read 4, iclass 31, count 2 2006.173.12:37:03.10#ibcon#read 4, iclass 31, count 2 2006.173.12:37:03.10#ibcon#about to read 5, iclass 31, count 2 2006.173.12:37:03.10#ibcon#read 5, iclass 31, count 2 2006.173.12:37:03.10#ibcon#about to read 6, iclass 31, count 2 2006.173.12:37:03.10#ibcon#read 6, iclass 31, count 2 2006.173.12:37:03.10#ibcon#end of sib2, iclass 31, count 2 2006.173.12:37:03.10#ibcon#*after write, iclass 31, count 2 2006.173.12:37:03.10#ibcon#*before return 0, iclass 31, count 2 2006.173.12:37:03.10#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.12:37:03.10#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.12:37:03.10#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.12:37:03.10#ibcon#ireg 7 cls_cnt 0 2006.173.12:37:03.10#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.12:37:03.22#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.12:37:03.22#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.12:37:03.22#ibcon#enter wrdev, iclass 31, count 0 2006.173.12:37:03.22#ibcon#first serial, iclass 31, count 0 2006.173.12:37:03.22#ibcon#enter sib2, iclass 31, count 0 2006.173.12:37:03.22#ibcon#flushed, iclass 31, count 0 2006.173.12:37:03.22#ibcon#about to write, iclass 31, count 0 2006.173.12:37:03.22#ibcon#wrote, iclass 31, count 0 2006.173.12:37:03.22#ibcon#about to read 3, iclass 31, count 0 2006.173.12:37:03.24#ibcon#read 3, iclass 31, count 0 2006.173.12:37:03.24#ibcon#about to read 4, iclass 31, count 0 2006.173.12:37:03.24#ibcon#read 4, iclass 31, count 0 2006.173.12:37:03.24#ibcon#about to read 5, iclass 31, count 0 2006.173.12:37:03.24#ibcon#read 5, iclass 31, count 0 2006.173.12:37:03.24#ibcon#about to read 6, iclass 31, count 0 2006.173.12:37:03.24#ibcon#read 6, iclass 31, count 0 2006.173.12:37:03.24#ibcon#end of sib2, iclass 31, count 0 2006.173.12:37:03.24#ibcon#*mode == 0, iclass 31, count 0 2006.173.12:37:03.24#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.12:37:03.24#ibcon#[27=USB\r\n] 2006.173.12:37:03.24#ibcon#*before write, iclass 31, count 0 2006.173.12:37:03.24#ibcon#enter sib2, iclass 31, count 0 2006.173.12:37:03.24#ibcon#flushed, iclass 31, count 0 2006.173.12:37:03.24#ibcon#about to write, iclass 31, count 0 2006.173.12:37:03.24#ibcon#wrote, iclass 31, count 0 2006.173.12:37:03.24#ibcon#about to read 3, iclass 31, count 0 2006.173.12:37:03.27#ibcon#read 3, iclass 31, count 0 2006.173.12:37:03.27#ibcon#about to read 4, iclass 31, count 0 2006.173.12:37:03.27#ibcon#read 4, iclass 31, count 0 2006.173.12:37:03.27#ibcon#about to read 5, iclass 31, count 0 2006.173.12:37:03.27#ibcon#read 5, iclass 31, count 0 2006.173.12:37:03.27#ibcon#about to read 6, iclass 31, count 0 2006.173.12:37:03.27#ibcon#read 6, iclass 31, count 0 2006.173.12:37:03.27#ibcon#end of sib2, iclass 31, count 0 2006.173.12:37:03.27#ibcon#*after write, iclass 31, count 0 2006.173.12:37:03.27#ibcon#*before return 0, iclass 31, count 0 2006.173.12:37:03.27#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.12:37:03.27#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.12:37:03.27#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.12:37:03.27#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.12:37:03.27$vck44/vblo=8,744.99 2006.173.12:37:03.27#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.12:37:03.27#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.12:37:03.27#ibcon#ireg 17 cls_cnt 0 2006.173.12:37:03.27#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.12:37:03.27#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.12:37:03.27#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.12:37:03.27#ibcon#enter wrdev, iclass 33, count 0 2006.173.12:37:03.27#ibcon#first serial, iclass 33, count 0 2006.173.12:37:03.27#ibcon#enter sib2, iclass 33, count 0 2006.173.12:37:03.27#ibcon#flushed, iclass 33, count 0 2006.173.12:37:03.27#ibcon#about to write, iclass 33, count 0 2006.173.12:37:03.27#ibcon#wrote, iclass 33, count 0 2006.173.12:37:03.27#ibcon#about to read 3, iclass 33, count 0 2006.173.12:37:03.29#ibcon#read 3, iclass 33, count 0 2006.173.12:37:03.29#ibcon#about to read 4, iclass 33, count 0 2006.173.12:37:03.29#ibcon#read 4, iclass 33, count 0 2006.173.12:37:03.29#ibcon#about to read 5, iclass 33, count 0 2006.173.12:37:03.29#ibcon#read 5, iclass 33, count 0 2006.173.12:37:03.29#ibcon#about to read 6, iclass 33, count 0 2006.173.12:37:03.29#ibcon#read 6, iclass 33, count 0 2006.173.12:37:03.29#ibcon#end of sib2, iclass 33, count 0 2006.173.12:37:03.29#ibcon#*mode == 0, iclass 33, count 0 2006.173.12:37:03.29#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.12:37:03.29#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.12:37:03.29#ibcon#*before write, iclass 33, count 0 2006.173.12:37:03.29#ibcon#enter sib2, iclass 33, count 0 2006.173.12:37:03.29#ibcon#flushed, iclass 33, count 0 2006.173.12:37:03.29#ibcon#about to write, iclass 33, count 0 2006.173.12:37:03.29#ibcon#wrote, iclass 33, count 0 2006.173.12:37:03.29#ibcon#about to read 3, iclass 33, count 0 2006.173.12:37:03.33#ibcon#read 3, iclass 33, count 0 2006.173.12:37:03.33#ibcon#about to read 4, iclass 33, count 0 2006.173.12:37:03.33#ibcon#read 4, iclass 33, count 0 2006.173.12:37:03.33#ibcon#about to read 5, iclass 33, count 0 2006.173.12:37:03.33#ibcon#read 5, iclass 33, count 0 2006.173.12:37:03.33#ibcon#about to read 6, iclass 33, count 0 2006.173.12:37:03.33#ibcon#read 6, iclass 33, count 0 2006.173.12:37:03.33#ibcon#end of sib2, iclass 33, count 0 2006.173.12:37:03.33#ibcon#*after write, iclass 33, count 0 2006.173.12:37:03.33#ibcon#*before return 0, iclass 33, count 0 2006.173.12:37:03.33#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.12:37:03.33#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.12:37:03.33#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.12:37:03.33#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.12:37:03.33$vck44/vb=8,4 2006.173.12:37:03.33#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.12:37:03.33#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.12:37:03.33#ibcon#ireg 11 cls_cnt 2 2006.173.12:37:03.33#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.12:37:03.39#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.12:37:03.39#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.12:37:03.39#ibcon#enter wrdev, iclass 35, count 2 2006.173.12:37:03.39#ibcon#first serial, iclass 35, count 2 2006.173.12:37:03.39#ibcon#enter sib2, iclass 35, count 2 2006.173.12:37:03.39#ibcon#flushed, iclass 35, count 2 2006.173.12:37:03.39#ibcon#about to write, iclass 35, count 2 2006.173.12:37:03.39#ibcon#wrote, iclass 35, count 2 2006.173.12:37:03.39#ibcon#about to read 3, iclass 35, count 2 2006.173.12:37:03.41#ibcon#read 3, iclass 35, count 2 2006.173.12:37:03.41#ibcon#about to read 4, iclass 35, count 2 2006.173.12:37:03.41#ibcon#read 4, iclass 35, count 2 2006.173.12:37:03.41#ibcon#about to read 5, iclass 35, count 2 2006.173.12:37:03.41#ibcon#read 5, iclass 35, count 2 2006.173.12:37:03.41#ibcon#about to read 6, iclass 35, count 2 2006.173.12:37:03.41#ibcon#read 6, iclass 35, count 2 2006.173.12:37:03.41#ibcon#end of sib2, iclass 35, count 2 2006.173.12:37:03.41#ibcon#*mode == 0, iclass 35, count 2 2006.173.12:37:03.41#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.12:37:03.41#ibcon#[27=AT08-04\r\n] 2006.173.12:37:03.41#ibcon#*before write, iclass 35, count 2 2006.173.12:37:03.41#ibcon#enter sib2, iclass 35, count 2 2006.173.12:37:03.41#ibcon#flushed, iclass 35, count 2 2006.173.12:37:03.41#ibcon#about to write, iclass 35, count 2 2006.173.12:37:03.41#ibcon#wrote, iclass 35, count 2 2006.173.12:37:03.41#ibcon#about to read 3, iclass 35, count 2 2006.173.12:37:03.44#ibcon#read 3, iclass 35, count 2 2006.173.12:37:03.44#ibcon#about to read 4, iclass 35, count 2 2006.173.12:37:03.44#ibcon#read 4, iclass 35, count 2 2006.173.12:37:03.44#ibcon#about to read 5, iclass 35, count 2 2006.173.12:37:03.44#ibcon#read 5, iclass 35, count 2 2006.173.12:37:03.44#ibcon#about to read 6, iclass 35, count 2 2006.173.12:37:03.44#ibcon#read 6, iclass 35, count 2 2006.173.12:37:03.44#ibcon#end of sib2, iclass 35, count 2 2006.173.12:37:03.44#ibcon#*after write, iclass 35, count 2 2006.173.12:37:03.44#ibcon#*before return 0, iclass 35, count 2 2006.173.12:37:03.44#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.12:37:03.44#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.12:37:03.44#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.12:37:03.44#ibcon#ireg 7 cls_cnt 0 2006.173.12:37:03.44#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.12:37:03.56#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.12:37:03.56#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.12:37:03.56#ibcon#enter wrdev, iclass 35, count 0 2006.173.12:37:03.56#ibcon#first serial, iclass 35, count 0 2006.173.12:37:03.56#ibcon#enter sib2, iclass 35, count 0 2006.173.12:37:03.56#ibcon#flushed, iclass 35, count 0 2006.173.12:37:03.56#ibcon#about to write, iclass 35, count 0 2006.173.12:37:03.56#ibcon#wrote, iclass 35, count 0 2006.173.12:37:03.56#ibcon#about to read 3, iclass 35, count 0 2006.173.12:37:03.58#ibcon#read 3, iclass 35, count 0 2006.173.12:37:03.58#ibcon#about to read 4, iclass 35, count 0 2006.173.12:37:03.58#ibcon#read 4, iclass 35, count 0 2006.173.12:37:03.58#ibcon#about to read 5, iclass 35, count 0 2006.173.12:37:03.58#ibcon#read 5, iclass 35, count 0 2006.173.12:37:03.58#ibcon#about to read 6, iclass 35, count 0 2006.173.12:37:03.58#ibcon#read 6, iclass 35, count 0 2006.173.12:37:03.58#ibcon#end of sib2, iclass 35, count 0 2006.173.12:37:03.58#ibcon#*mode == 0, iclass 35, count 0 2006.173.12:37:03.58#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.12:37:03.58#ibcon#[27=USB\r\n] 2006.173.12:37:03.58#ibcon#*before write, iclass 35, count 0 2006.173.12:37:03.58#ibcon#enter sib2, iclass 35, count 0 2006.173.12:37:03.58#ibcon#flushed, iclass 35, count 0 2006.173.12:37:03.58#ibcon#about to write, iclass 35, count 0 2006.173.12:37:03.58#ibcon#wrote, iclass 35, count 0 2006.173.12:37:03.58#ibcon#about to read 3, iclass 35, count 0 2006.173.12:37:03.61#ibcon#read 3, iclass 35, count 0 2006.173.12:37:03.61#ibcon#about to read 4, iclass 35, count 0 2006.173.12:37:03.61#ibcon#read 4, iclass 35, count 0 2006.173.12:37:03.61#ibcon#about to read 5, iclass 35, count 0 2006.173.12:37:03.61#ibcon#read 5, iclass 35, count 0 2006.173.12:37:03.61#ibcon#about to read 6, iclass 35, count 0 2006.173.12:37:03.61#ibcon#read 6, iclass 35, count 0 2006.173.12:37:03.61#ibcon#end of sib2, iclass 35, count 0 2006.173.12:37:03.61#ibcon#*after write, iclass 35, count 0 2006.173.12:37:03.61#ibcon#*before return 0, iclass 35, count 0 2006.173.12:37:03.61#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.12:37:03.61#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.12:37:03.61#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.12:37:03.61#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.12:37:03.61$vck44/vabw=wide 2006.173.12:37:03.61#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.12:37:03.61#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.12:37:03.61#ibcon#ireg 8 cls_cnt 0 2006.173.12:37:03.61#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.12:37:03.61#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.12:37:03.61#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.12:37:03.61#ibcon#enter wrdev, iclass 37, count 0 2006.173.12:37:03.61#ibcon#first serial, iclass 37, count 0 2006.173.12:37:03.61#ibcon#enter sib2, iclass 37, count 0 2006.173.12:37:03.61#ibcon#flushed, iclass 37, count 0 2006.173.12:37:03.61#ibcon#about to write, iclass 37, count 0 2006.173.12:37:03.61#ibcon#wrote, iclass 37, count 0 2006.173.12:37:03.61#ibcon#about to read 3, iclass 37, count 0 2006.173.12:37:03.63#ibcon#read 3, iclass 37, count 0 2006.173.12:37:03.63#ibcon#about to read 4, iclass 37, count 0 2006.173.12:37:03.63#ibcon#read 4, iclass 37, count 0 2006.173.12:37:03.63#ibcon#about to read 5, iclass 37, count 0 2006.173.12:37:03.63#ibcon#read 5, iclass 37, count 0 2006.173.12:37:03.63#ibcon#about to read 6, iclass 37, count 0 2006.173.12:37:03.63#ibcon#read 6, iclass 37, count 0 2006.173.12:37:03.63#ibcon#end of sib2, iclass 37, count 0 2006.173.12:37:03.63#ibcon#*mode == 0, iclass 37, count 0 2006.173.12:37:03.63#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.12:37:03.63#ibcon#[25=BW32\r\n] 2006.173.12:37:03.63#ibcon#*before write, iclass 37, count 0 2006.173.12:37:03.63#ibcon#enter sib2, iclass 37, count 0 2006.173.12:37:03.63#ibcon#flushed, iclass 37, count 0 2006.173.12:37:03.63#ibcon#about to write, iclass 37, count 0 2006.173.12:37:03.63#ibcon#wrote, iclass 37, count 0 2006.173.12:37:03.63#ibcon#about to read 3, iclass 37, count 0 2006.173.12:37:03.66#ibcon#read 3, iclass 37, count 0 2006.173.12:37:03.66#ibcon#about to read 4, iclass 37, count 0 2006.173.12:37:03.66#ibcon#read 4, iclass 37, count 0 2006.173.12:37:03.66#ibcon#about to read 5, iclass 37, count 0 2006.173.12:37:03.66#ibcon#read 5, iclass 37, count 0 2006.173.12:37:03.66#ibcon#about to read 6, iclass 37, count 0 2006.173.12:37:03.66#ibcon#read 6, iclass 37, count 0 2006.173.12:37:03.66#ibcon#end of sib2, iclass 37, count 0 2006.173.12:37:03.66#ibcon#*after write, iclass 37, count 0 2006.173.12:37:03.66#ibcon#*before return 0, iclass 37, count 0 2006.173.12:37:03.66#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.12:37:03.66#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.12:37:03.66#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.12:37:03.66#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.12:37:03.66$vck44/vbbw=wide 2006.173.12:37:03.66#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.12:37:03.66#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.12:37:03.66#ibcon#ireg 8 cls_cnt 0 2006.173.12:37:03.66#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.12:37:03.73#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.12:37:03.73#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.12:37:03.73#ibcon#enter wrdev, iclass 39, count 0 2006.173.12:37:03.73#ibcon#first serial, iclass 39, count 0 2006.173.12:37:03.73#ibcon#enter sib2, iclass 39, count 0 2006.173.12:37:03.73#ibcon#flushed, iclass 39, count 0 2006.173.12:37:03.73#ibcon#about to write, iclass 39, count 0 2006.173.12:37:03.73#ibcon#wrote, iclass 39, count 0 2006.173.12:37:03.73#ibcon#about to read 3, iclass 39, count 0 2006.173.12:37:03.75#ibcon#read 3, iclass 39, count 0 2006.173.12:37:03.75#ibcon#about to read 4, iclass 39, count 0 2006.173.12:37:03.75#ibcon#read 4, iclass 39, count 0 2006.173.12:37:03.75#ibcon#about to read 5, iclass 39, count 0 2006.173.12:37:03.75#ibcon#read 5, iclass 39, count 0 2006.173.12:37:03.75#ibcon#about to read 6, iclass 39, count 0 2006.173.12:37:03.75#ibcon#read 6, iclass 39, count 0 2006.173.12:37:03.75#ibcon#end of sib2, iclass 39, count 0 2006.173.12:37:03.75#ibcon#*mode == 0, iclass 39, count 0 2006.173.12:37:03.75#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.12:37:03.75#ibcon#[27=BW32\r\n] 2006.173.12:37:03.75#ibcon#*before write, iclass 39, count 0 2006.173.12:37:03.75#ibcon#enter sib2, iclass 39, count 0 2006.173.12:37:03.75#ibcon#flushed, iclass 39, count 0 2006.173.12:37:03.75#ibcon#about to write, iclass 39, count 0 2006.173.12:37:03.75#ibcon#wrote, iclass 39, count 0 2006.173.12:37:03.75#ibcon#about to read 3, iclass 39, count 0 2006.173.12:37:03.78#ibcon#read 3, iclass 39, count 0 2006.173.12:37:03.78#ibcon#about to read 4, iclass 39, count 0 2006.173.12:37:03.78#ibcon#read 4, iclass 39, count 0 2006.173.12:37:03.78#ibcon#about to read 5, iclass 39, count 0 2006.173.12:37:03.78#ibcon#read 5, iclass 39, count 0 2006.173.12:37:03.78#ibcon#about to read 6, iclass 39, count 0 2006.173.12:37:03.78#ibcon#read 6, iclass 39, count 0 2006.173.12:37:03.78#ibcon#end of sib2, iclass 39, count 0 2006.173.12:37:03.78#ibcon#*after write, iclass 39, count 0 2006.173.12:37:03.78#ibcon#*before return 0, iclass 39, count 0 2006.173.12:37:03.78#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.12:37:03.78#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.12:37:03.78#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.12:37:03.78#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.12:37:03.78$setupk4/ifdk4 2006.173.12:37:03.78$ifdk4/lo= 2006.173.12:37:03.78$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.12:37:03.78$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.12:37:03.78$ifdk4/patch= 2006.173.12:37:03.78$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.12:37:03.78$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.12:37:03.78$setupk4/!*+20s 2006.173.12:37:06.73#abcon#<5=/03 0.9 1.7 22.10 951004.4\r\n> 2006.173.12:37:06.75#abcon#{5=INTERFACE CLEAR} 2006.173.12:37:06.81#abcon#[5=S1D000X0/0*\r\n] 2006.173.12:37:11.14#trakl#Source acquired 2006.173.12:37:12.14#flagr#flagr/antenna,acquired 2006.173.12:37:16.90#abcon#<5=/03 0.9 1.7 22.11 951004.4\r\n> 2006.173.12:37:16.92#abcon#{5=INTERFACE CLEAR} 2006.173.12:37:16.98#abcon#[5=S1D000X0/0*\r\n] 2006.173.12:37:18.28$setupk4/"tpicd 2006.173.12:37:18.28$setupk4/echo=off 2006.173.12:37:18.28$setupk4/xlog=off 2006.173.12:37:18.28:!2006.173.12:40:03 2006.173.12:40:03.00:preob 2006.173.12:40:04.14/onsource/TRACKING 2006.173.12:40:04.14:!2006.173.12:40:13 2006.173.12:40:13.00:"tape 2006.173.12:40:13.00:"st=record 2006.173.12:40:13.00:data_valid=on 2006.173.12:40:13.00:midob 2006.173.12:40:13.14/onsource/TRACKING 2006.173.12:40:13.14/wx/22.11,1004.2,95 2006.173.12:40:13.25/cable/+6.5056E-03 2006.173.12:40:14.34/va/01,07,usb,yes,35,38 2006.173.12:40:14.34/va/02,06,usb,yes,35,36 2006.173.12:40:14.34/va/03,05,usb,yes,45,47 2006.173.12:40:14.34/va/04,06,usb,yes,36,38 2006.173.12:40:14.34/va/05,04,usb,yes,28,29 2006.173.12:40:14.34/va/06,03,usb,yes,40,40 2006.173.12:40:14.34/va/07,04,usb,yes,32,33 2006.173.12:40:14.34/va/08,04,usb,yes,27,33 2006.173.12:40:14.57/valo/01,524.99,yes,locked 2006.173.12:40:14.57/valo/02,534.99,yes,locked 2006.173.12:40:14.57/valo/03,564.99,yes,locked 2006.173.12:40:14.57/valo/04,624.99,yes,locked 2006.173.12:40:14.57/valo/05,734.99,yes,locked 2006.173.12:40:14.57/valo/06,814.99,yes,locked 2006.173.12:40:14.57/valo/07,864.99,yes,locked 2006.173.12:40:14.57/valo/08,884.99,yes,locked 2006.173.12:40:15.66/vb/01,04,usb,yes,29,27 2006.173.12:40:15.66/vb/02,04,usb,yes,31,31 2006.173.12:40:15.66/vb/03,04,usb,yes,28,31 2006.173.12:40:15.66/vb/04,04,usb,yes,32,31 2006.173.12:40:15.66/vb/05,04,usb,yes,27,28 2006.173.12:40:15.66/vb/06,04,usb,yes,29,27 2006.173.12:40:15.66/vb/07,04,usb,yes,29,30 2006.173.12:40:15.66/vb/08,04,usb,yes,27,30 2006.173.12:40:15.90/vblo/01,629.99,yes,locked 2006.173.12:40:15.90/vblo/02,634.99,yes,locked 2006.173.12:40:15.90/vblo/03,649.99,yes,locked 2006.173.12:40:15.90/vblo/04,679.99,yes,locked 2006.173.12:40:15.90/vblo/05,709.99,yes,locked 2006.173.12:40:15.90/vblo/06,719.99,yes,locked 2006.173.12:40:15.90/vblo/07,734.99,yes,locked 2006.173.12:40:15.90/vblo/08,744.99,yes,locked 2006.173.12:40:16.05/vabw/8 2006.173.12:40:16.20/vbbw/8 2006.173.12:40:16.29/xfe/off,on,15.2 2006.173.12:40:16.68/ifatt/23,28,28,28 2006.173.12:40:17.08/fmout-gps/S +3.92E-07 2006.173.12:40:17.12:!2006.173.12:47:03 2006.173.12:47:03.00:data_valid=off 2006.173.12:47:03.00:"et 2006.173.12:47:03.00:!+3s 2006.173.12:47:06.02:"tape 2006.173.12:47:06.02:postob 2006.173.12:47:06.17/cable/+6.5046E-03 2006.173.12:47:06.17/wx/22.13,1004.3,95 2006.173.12:47:07.08/fmout-gps/S +3.89E-07 2006.173.12:47:07.08:scan_name=173-1253,jd0606,370 2006.173.12:47:07.08:source=1308+326,131028.66,322043.8,2000.0,cw 2006.173.12:47:08.13#flagr#flagr/antenna,new-source 2006.173.12:47:08.13:checkk5 2006.173.12:47:08.56/chk_autoobs//k5ts1/ autoobs is running! 2006.173.12:47:08.96/chk_autoobs//k5ts2/ autoobs is running! 2006.173.12:47:09.35/chk_autoobs//k5ts3/ autoobs is running! 2006.173.12:47:09.75/chk_autoobs//k5ts4/ autoobs is running! 2006.173.12:47:10.14/chk_obsdata//k5ts1/T1731240??a.dat file size is correct (nominal:1640MB, actual:1636MB). 2006.173.12:47:10.55/chk_obsdata//k5ts2/T1731240??b.dat file size is correct (nominal:1640MB, actual:1636MB). 2006.173.12:47:10.96/chk_obsdata//k5ts3/T1731240??c.dat file size is correct (nominal:1640MB, actual:1636MB). 2006.173.12:47:11.38/chk_obsdata//k5ts4/T1731240??d.dat file size is correct (nominal:1640MB, actual:1636MB). 2006.173.12:47:12.11/k5log//k5ts1_log_newline 2006.173.12:47:12.84/k5log//k5ts2_log_newline 2006.173.12:47:13.57/k5log//k5ts3_log_newline 2006.173.12:47:14.30/k5log//k5ts4_log_newline 2006.173.12:47:14.32/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.12:47:14.32:setupk4=1 2006.173.12:47:14.32$setupk4/echo=on 2006.173.12:47:14.32$setupk4/pcalon 2006.173.12:47:14.32$pcalon/"no phase cal control is implemented here 2006.173.12:47:14.32$setupk4/"tpicd=stop 2006.173.12:47:14.32$setupk4/"rec=synch_on 2006.173.12:47:14.32$setupk4/"rec_mode=128 2006.173.12:47:14.32$setupk4/!* 2006.173.12:47:14.32$setupk4/recpk4 2006.173.12:47:14.32$recpk4/recpatch= 2006.173.12:47:14.32$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.12:47:14.32$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.12:47:14.32$setupk4/vck44 2006.173.12:47:14.32$vck44/valo=1,524.99 2006.173.12:47:14.32#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.12:47:14.32#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.12:47:14.32#ibcon#ireg 17 cls_cnt 0 2006.173.12:47:14.32#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.12:47:14.32#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.12:47:14.32#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.12:47:14.32#ibcon#enter wrdev, iclass 32, count 0 2006.173.12:47:14.32#ibcon#first serial, iclass 32, count 0 2006.173.12:47:14.32#ibcon#enter sib2, iclass 32, count 0 2006.173.12:47:14.32#ibcon#flushed, iclass 32, count 0 2006.173.12:47:14.32#ibcon#about to write, iclass 32, count 0 2006.173.12:47:14.32#ibcon#wrote, iclass 32, count 0 2006.173.12:47:14.32#ibcon#about to read 3, iclass 32, count 0 2006.173.12:47:14.34#ibcon#read 3, iclass 32, count 0 2006.173.12:47:14.34#ibcon#about to read 4, iclass 32, count 0 2006.173.12:47:14.34#ibcon#read 4, iclass 32, count 0 2006.173.12:47:14.34#ibcon#about to read 5, iclass 32, count 0 2006.173.12:47:14.34#ibcon#read 5, iclass 32, count 0 2006.173.12:47:14.34#ibcon#about to read 6, iclass 32, count 0 2006.173.12:47:14.34#ibcon#read 6, iclass 32, count 0 2006.173.12:47:14.34#ibcon#end of sib2, iclass 32, count 0 2006.173.12:47:14.34#ibcon#*mode == 0, iclass 32, count 0 2006.173.12:47:14.34#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.12:47:14.34#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.12:47:14.34#ibcon#*before write, iclass 32, count 0 2006.173.12:47:14.34#ibcon#enter sib2, iclass 32, count 0 2006.173.12:47:14.34#ibcon#flushed, iclass 32, count 0 2006.173.12:47:14.34#ibcon#about to write, iclass 32, count 0 2006.173.12:47:14.34#ibcon#wrote, iclass 32, count 0 2006.173.12:47:14.34#ibcon#about to read 3, iclass 32, count 0 2006.173.12:47:14.39#ibcon#read 3, iclass 32, count 0 2006.173.12:47:14.39#ibcon#about to read 4, iclass 32, count 0 2006.173.12:47:14.39#ibcon#read 4, iclass 32, count 0 2006.173.12:47:14.39#ibcon#about to read 5, iclass 32, count 0 2006.173.12:47:14.39#ibcon#read 5, iclass 32, count 0 2006.173.12:47:14.39#ibcon#about to read 6, iclass 32, count 0 2006.173.12:47:14.39#ibcon#read 6, iclass 32, count 0 2006.173.12:47:14.39#ibcon#end of sib2, iclass 32, count 0 2006.173.12:47:14.39#ibcon#*after write, iclass 32, count 0 2006.173.12:47:14.39#ibcon#*before return 0, iclass 32, count 0 2006.173.12:47:14.39#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.12:47:14.39#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.12:47:14.39#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.12:47:14.39#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.12:47:14.39$vck44/va=1,7 2006.173.12:47:14.39#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.12:47:14.39#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.12:47:14.39#ibcon#ireg 11 cls_cnt 2 2006.173.12:47:14.39#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.12:47:14.39#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.12:47:14.39#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.12:47:14.39#ibcon#enter wrdev, iclass 34, count 2 2006.173.12:47:14.39#ibcon#first serial, iclass 34, count 2 2006.173.12:47:14.39#ibcon#enter sib2, iclass 34, count 2 2006.173.12:47:14.39#ibcon#flushed, iclass 34, count 2 2006.173.12:47:14.39#ibcon#about to write, iclass 34, count 2 2006.173.12:47:14.39#ibcon#wrote, iclass 34, count 2 2006.173.12:47:14.39#ibcon#about to read 3, iclass 34, count 2 2006.173.12:47:14.41#ibcon#read 3, iclass 34, count 2 2006.173.12:47:14.41#ibcon#about to read 4, iclass 34, count 2 2006.173.12:47:14.41#ibcon#read 4, iclass 34, count 2 2006.173.12:47:14.41#ibcon#about to read 5, iclass 34, count 2 2006.173.12:47:14.41#ibcon#read 5, iclass 34, count 2 2006.173.12:47:14.41#ibcon#about to read 6, iclass 34, count 2 2006.173.12:47:14.41#ibcon#read 6, iclass 34, count 2 2006.173.12:47:14.41#ibcon#end of sib2, iclass 34, count 2 2006.173.12:47:14.41#ibcon#*mode == 0, iclass 34, count 2 2006.173.12:47:14.41#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.12:47:14.41#ibcon#[25=AT01-07\r\n] 2006.173.12:47:14.41#ibcon#*before write, iclass 34, count 2 2006.173.12:47:14.41#ibcon#enter sib2, iclass 34, count 2 2006.173.12:47:14.41#ibcon#flushed, iclass 34, count 2 2006.173.12:47:14.41#ibcon#about to write, iclass 34, count 2 2006.173.12:47:14.41#ibcon#wrote, iclass 34, count 2 2006.173.12:47:14.41#ibcon#about to read 3, iclass 34, count 2 2006.173.12:47:14.44#ibcon#read 3, iclass 34, count 2 2006.173.12:47:14.44#ibcon#about to read 4, iclass 34, count 2 2006.173.12:47:14.44#ibcon#read 4, iclass 34, count 2 2006.173.12:47:14.44#ibcon#about to read 5, iclass 34, count 2 2006.173.12:47:14.44#ibcon#read 5, iclass 34, count 2 2006.173.12:47:14.44#ibcon#about to read 6, iclass 34, count 2 2006.173.12:47:14.44#ibcon#read 6, iclass 34, count 2 2006.173.12:47:14.44#ibcon#end of sib2, iclass 34, count 2 2006.173.12:47:14.44#ibcon#*after write, iclass 34, count 2 2006.173.12:47:14.44#ibcon#*before return 0, iclass 34, count 2 2006.173.12:47:14.44#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.12:47:14.44#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.12:47:14.44#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.12:47:14.44#ibcon#ireg 7 cls_cnt 0 2006.173.12:47:14.44#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.12:47:14.56#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.12:47:14.56#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.12:47:14.56#ibcon#enter wrdev, iclass 34, count 0 2006.173.12:47:14.56#ibcon#first serial, iclass 34, count 0 2006.173.12:47:14.56#ibcon#enter sib2, iclass 34, count 0 2006.173.12:47:14.56#ibcon#flushed, iclass 34, count 0 2006.173.12:47:14.56#ibcon#about to write, iclass 34, count 0 2006.173.12:47:14.56#ibcon#wrote, iclass 34, count 0 2006.173.12:47:14.56#ibcon#about to read 3, iclass 34, count 0 2006.173.12:47:14.58#ibcon#read 3, iclass 34, count 0 2006.173.12:47:14.58#ibcon#about to read 4, iclass 34, count 0 2006.173.12:47:14.58#ibcon#read 4, iclass 34, count 0 2006.173.12:47:14.58#ibcon#about to read 5, iclass 34, count 0 2006.173.12:47:14.58#ibcon#read 5, iclass 34, count 0 2006.173.12:47:14.58#ibcon#about to read 6, iclass 34, count 0 2006.173.12:47:14.58#ibcon#read 6, iclass 34, count 0 2006.173.12:47:14.58#ibcon#end of sib2, iclass 34, count 0 2006.173.12:47:14.58#ibcon#*mode == 0, iclass 34, count 0 2006.173.12:47:14.58#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.12:47:14.58#ibcon#[25=USB\r\n] 2006.173.12:47:14.58#ibcon#*before write, iclass 34, count 0 2006.173.12:47:14.58#ibcon#enter sib2, iclass 34, count 0 2006.173.12:47:14.58#ibcon#flushed, iclass 34, count 0 2006.173.12:47:14.58#ibcon#about to write, iclass 34, count 0 2006.173.12:47:14.58#ibcon#wrote, iclass 34, count 0 2006.173.12:47:14.58#ibcon#about to read 3, iclass 34, count 0 2006.173.12:47:14.61#ibcon#read 3, iclass 34, count 0 2006.173.12:47:14.61#ibcon#about to read 4, iclass 34, count 0 2006.173.12:47:14.61#ibcon#read 4, iclass 34, count 0 2006.173.12:47:14.61#ibcon#about to read 5, iclass 34, count 0 2006.173.12:47:14.61#ibcon#read 5, iclass 34, count 0 2006.173.12:47:14.61#ibcon#about to read 6, iclass 34, count 0 2006.173.12:47:14.61#ibcon#read 6, iclass 34, count 0 2006.173.12:47:14.61#ibcon#end of sib2, iclass 34, count 0 2006.173.12:47:14.61#ibcon#*after write, iclass 34, count 0 2006.173.12:47:14.61#ibcon#*before return 0, iclass 34, count 0 2006.173.12:47:14.61#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.12:47:14.61#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.12:47:14.61#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.12:47:14.61#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.12:47:14.61$vck44/valo=2,534.99 2006.173.12:47:14.61#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.12:47:14.61#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.12:47:14.61#ibcon#ireg 17 cls_cnt 0 2006.173.12:47:14.61#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.12:47:14.61#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.12:47:14.61#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.12:47:14.61#ibcon#enter wrdev, iclass 36, count 0 2006.173.12:47:14.61#ibcon#first serial, iclass 36, count 0 2006.173.12:47:14.61#ibcon#enter sib2, iclass 36, count 0 2006.173.12:47:14.61#ibcon#flushed, iclass 36, count 0 2006.173.12:47:14.61#ibcon#about to write, iclass 36, count 0 2006.173.12:47:14.61#ibcon#wrote, iclass 36, count 0 2006.173.12:47:14.61#ibcon#about to read 3, iclass 36, count 0 2006.173.12:47:14.63#ibcon#read 3, iclass 36, count 0 2006.173.12:47:14.63#ibcon#about to read 4, iclass 36, count 0 2006.173.12:47:14.63#ibcon#read 4, iclass 36, count 0 2006.173.12:47:14.63#ibcon#about to read 5, iclass 36, count 0 2006.173.12:47:14.63#ibcon#read 5, iclass 36, count 0 2006.173.12:47:14.63#ibcon#about to read 6, iclass 36, count 0 2006.173.12:47:14.63#ibcon#read 6, iclass 36, count 0 2006.173.12:47:14.63#ibcon#end of sib2, iclass 36, count 0 2006.173.12:47:14.63#ibcon#*mode == 0, iclass 36, count 0 2006.173.12:47:14.63#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.12:47:14.63#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.12:47:14.63#ibcon#*before write, iclass 36, count 0 2006.173.12:47:14.63#ibcon#enter sib2, iclass 36, count 0 2006.173.12:47:14.63#ibcon#flushed, iclass 36, count 0 2006.173.12:47:14.63#ibcon#about to write, iclass 36, count 0 2006.173.12:47:14.63#ibcon#wrote, iclass 36, count 0 2006.173.12:47:14.63#ibcon#about to read 3, iclass 36, count 0 2006.173.12:47:14.67#ibcon#read 3, iclass 36, count 0 2006.173.12:47:14.67#ibcon#about to read 4, iclass 36, count 0 2006.173.12:47:14.67#ibcon#read 4, iclass 36, count 0 2006.173.12:47:14.67#ibcon#about to read 5, iclass 36, count 0 2006.173.12:47:14.67#ibcon#read 5, iclass 36, count 0 2006.173.12:47:14.67#ibcon#about to read 6, iclass 36, count 0 2006.173.12:47:14.67#ibcon#read 6, iclass 36, count 0 2006.173.12:47:14.67#ibcon#end of sib2, iclass 36, count 0 2006.173.12:47:14.67#ibcon#*after write, iclass 36, count 0 2006.173.12:47:14.67#ibcon#*before return 0, iclass 36, count 0 2006.173.12:47:14.67#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.12:47:14.67#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.12:47:14.67#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.12:47:14.67#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.12:47:14.67$vck44/va=2,6 2006.173.12:47:14.67#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.12:47:14.67#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.12:47:14.67#ibcon#ireg 11 cls_cnt 2 2006.173.12:47:14.67#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.12:47:14.73#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.12:47:14.73#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.12:47:14.73#ibcon#enter wrdev, iclass 38, count 2 2006.173.12:47:14.73#ibcon#first serial, iclass 38, count 2 2006.173.12:47:14.73#ibcon#enter sib2, iclass 38, count 2 2006.173.12:47:14.73#ibcon#flushed, iclass 38, count 2 2006.173.12:47:14.73#ibcon#about to write, iclass 38, count 2 2006.173.12:47:14.73#ibcon#wrote, iclass 38, count 2 2006.173.12:47:14.73#ibcon#about to read 3, iclass 38, count 2 2006.173.12:47:14.75#ibcon#read 3, iclass 38, count 2 2006.173.12:47:14.75#ibcon#about to read 4, iclass 38, count 2 2006.173.12:47:14.75#ibcon#read 4, iclass 38, count 2 2006.173.12:47:14.75#ibcon#about to read 5, iclass 38, count 2 2006.173.12:47:14.75#ibcon#read 5, iclass 38, count 2 2006.173.12:47:14.75#ibcon#about to read 6, iclass 38, count 2 2006.173.12:47:14.75#ibcon#read 6, iclass 38, count 2 2006.173.12:47:14.75#ibcon#end of sib2, iclass 38, count 2 2006.173.12:47:14.75#ibcon#*mode == 0, iclass 38, count 2 2006.173.12:47:14.75#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.12:47:14.75#ibcon#[25=AT02-06\r\n] 2006.173.12:47:14.75#ibcon#*before write, iclass 38, count 2 2006.173.12:47:14.75#ibcon#enter sib2, iclass 38, count 2 2006.173.12:47:14.75#ibcon#flushed, iclass 38, count 2 2006.173.12:47:14.75#ibcon#about to write, iclass 38, count 2 2006.173.12:47:14.75#ibcon#wrote, iclass 38, count 2 2006.173.12:47:14.75#ibcon#about to read 3, iclass 38, count 2 2006.173.12:47:14.78#ibcon#read 3, iclass 38, count 2 2006.173.12:47:14.78#ibcon#about to read 4, iclass 38, count 2 2006.173.12:47:14.78#ibcon#read 4, iclass 38, count 2 2006.173.12:47:14.78#ibcon#about to read 5, iclass 38, count 2 2006.173.12:47:14.78#ibcon#read 5, iclass 38, count 2 2006.173.12:47:14.78#ibcon#about to read 6, iclass 38, count 2 2006.173.12:47:14.78#ibcon#read 6, iclass 38, count 2 2006.173.12:47:14.78#ibcon#end of sib2, iclass 38, count 2 2006.173.12:47:14.78#ibcon#*after write, iclass 38, count 2 2006.173.12:47:14.78#ibcon#*before return 0, iclass 38, count 2 2006.173.12:47:14.78#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.12:47:14.78#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.12:47:14.78#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.12:47:14.78#ibcon#ireg 7 cls_cnt 0 2006.173.12:47:14.78#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.12:47:14.90#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.12:47:14.90#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.12:47:14.90#ibcon#enter wrdev, iclass 38, count 0 2006.173.12:47:14.90#ibcon#first serial, iclass 38, count 0 2006.173.12:47:14.90#ibcon#enter sib2, iclass 38, count 0 2006.173.12:47:14.90#ibcon#flushed, iclass 38, count 0 2006.173.12:47:14.90#ibcon#about to write, iclass 38, count 0 2006.173.12:47:14.90#ibcon#wrote, iclass 38, count 0 2006.173.12:47:14.90#ibcon#about to read 3, iclass 38, count 0 2006.173.12:47:14.92#ibcon#read 3, iclass 38, count 0 2006.173.12:47:14.92#ibcon#about to read 4, iclass 38, count 0 2006.173.12:47:14.92#ibcon#read 4, iclass 38, count 0 2006.173.12:47:14.92#ibcon#about to read 5, iclass 38, count 0 2006.173.12:47:14.92#ibcon#read 5, iclass 38, count 0 2006.173.12:47:14.92#ibcon#about to read 6, iclass 38, count 0 2006.173.12:47:14.92#ibcon#read 6, iclass 38, count 0 2006.173.12:47:14.92#ibcon#end of sib2, iclass 38, count 0 2006.173.12:47:14.92#ibcon#*mode == 0, iclass 38, count 0 2006.173.12:47:14.92#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.12:47:14.92#ibcon#[25=USB\r\n] 2006.173.12:47:14.92#ibcon#*before write, iclass 38, count 0 2006.173.12:47:14.92#ibcon#enter sib2, iclass 38, count 0 2006.173.12:47:14.92#ibcon#flushed, iclass 38, count 0 2006.173.12:47:14.92#ibcon#about to write, iclass 38, count 0 2006.173.12:47:14.92#ibcon#wrote, iclass 38, count 0 2006.173.12:47:14.92#ibcon#about to read 3, iclass 38, count 0 2006.173.12:47:14.95#ibcon#read 3, iclass 38, count 0 2006.173.12:47:14.95#ibcon#about to read 4, iclass 38, count 0 2006.173.12:47:14.95#ibcon#read 4, iclass 38, count 0 2006.173.12:47:14.95#ibcon#about to read 5, iclass 38, count 0 2006.173.12:47:14.95#ibcon#read 5, iclass 38, count 0 2006.173.12:47:14.95#ibcon#about to read 6, iclass 38, count 0 2006.173.12:47:14.95#ibcon#read 6, iclass 38, count 0 2006.173.12:47:14.95#ibcon#end of sib2, iclass 38, count 0 2006.173.12:47:14.95#ibcon#*after write, iclass 38, count 0 2006.173.12:47:14.95#ibcon#*before return 0, iclass 38, count 0 2006.173.12:47:14.95#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.12:47:14.95#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.12:47:14.95#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.12:47:14.95#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.12:47:14.95$vck44/valo=3,564.99 2006.173.12:47:14.95#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.12:47:14.95#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.12:47:14.95#ibcon#ireg 17 cls_cnt 0 2006.173.12:47:14.95#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.12:47:14.95#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.12:47:14.95#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.12:47:14.95#ibcon#enter wrdev, iclass 40, count 0 2006.173.12:47:14.95#ibcon#first serial, iclass 40, count 0 2006.173.12:47:14.95#ibcon#enter sib2, iclass 40, count 0 2006.173.12:47:14.95#ibcon#flushed, iclass 40, count 0 2006.173.12:47:14.95#ibcon#about to write, iclass 40, count 0 2006.173.12:47:14.95#ibcon#wrote, iclass 40, count 0 2006.173.12:47:14.95#ibcon#about to read 3, iclass 40, count 0 2006.173.12:47:14.97#ibcon#read 3, iclass 40, count 0 2006.173.12:47:14.97#ibcon#about to read 4, iclass 40, count 0 2006.173.12:47:14.97#ibcon#read 4, iclass 40, count 0 2006.173.12:47:14.97#ibcon#about to read 5, iclass 40, count 0 2006.173.12:47:14.97#ibcon#read 5, iclass 40, count 0 2006.173.12:47:14.97#ibcon#about to read 6, iclass 40, count 0 2006.173.12:47:14.97#ibcon#read 6, iclass 40, count 0 2006.173.12:47:14.97#ibcon#end of sib2, iclass 40, count 0 2006.173.12:47:14.97#ibcon#*mode == 0, iclass 40, count 0 2006.173.12:47:14.97#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.12:47:14.97#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.12:47:14.97#ibcon#*before write, iclass 40, count 0 2006.173.12:47:14.97#ibcon#enter sib2, iclass 40, count 0 2006.173.12:47:14.97#ibcon#flushed, iclass 40, count 0 2006.173.12:47:14.97#ibcon#about to write, iclass 40, count 0 2006.173.12:47:14.97#ibcon#wrote, iclass 40, count 0 2006.173.12:47:14.97#ibcon#about to read 3, iclass 40, count 0 2006.173.12:47:15.01#ibcon#read 3, iclass 40, count 0 2006.173.12:47:15.01#ibcon#about to read 4, iclass 40, count 0 2006.173.12:47:15.01#ibcon#read 4, iclass 40, count 0 2006.173.12:47:15.01#ibcon#about to read 5, iclass 40, count 0 2006.173.12:47:15.01#ibcon#read 5, iclass 40, count 0 2006.173.12:47:15.01#ibcon#about to read 6, iclass 40, count 0 2006.173.12:47:15.01#ibcon#read 6, iclass 40, count 0 2006.173.12:47:15.01#ibcon#end of sib2, iclass 40, count 0 2006.173.12:47:15.01#ibcon#*after write, iclass 40, count 0 2006.173.12:47:15.01#ibcon#*before return 0, iclass 40, count 0 2006.173.12:47:15.01#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.12:47:15.01#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.12:47:15.01#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.12:47:15.01#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.12:47:15.01$vck44/va=3,5 2006.173.12:47:15.01#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.12:47:15.01#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.12:47:15.01#ibcon#ireg 11 cls_cnt 2 2006.173.12:47:15.01#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.12:47:15.07#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.12:47:15.07#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.12:47:15.07#ibcon#enter wrdev, iclass 4, count 2 2006.173.12:47:15.07#ibcon#first serial, iclass 4, count 2 2006.173.12:47:15.07#ibcon#enter sib2, iclass 4, count 2 2006.173.12:47:15.07#ibcon#flushed, iclass 4, count 2 2006.173.12:47:15.07#ibcon#about to write, iclass 4, count 2 2006.173.12:47:15.07#ibcon#wrote, iclass 4, count 2 2006.173.12:47:15.07#ibcon#about to read 3, iclass 4, count 2 2006.173.12:47:15.09#ibcon#read 3, iclass 4, count 2 2006.173.12:47:15.09#ibcon#about to read 4, iclass 4, count 2 2006.173.12:47:15.09#ibcon#read 4, iclass 4, count 2 2006.173.12:47:15.09#ibcon#about to read 5, iclass 4, count 2 2006.173.12:47:15.09#ibcon#read 5, iclass 4, count 2 2006.173.12:47:15.09#ibcon#about to read 6, iclass 4, count 2 2006.173.12:47:15.09#ibcon#read 6, iclass 4, count 2 2006.173.12:47:15.09#ibcon#end of sib2, iclass 4, count 2 2006.173.12:47:15.09#ibcon#*mode == 0, iclass 4, count 2 2006.173.12:47:15.09#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.12:47:15.09#ibcon#[25=AT03-05\r\n] 2006.173.12:47:15.09#ibcon#*before write, iclass 4, count 2 2006.173.12:47:15.09#ibcon#enter sib2, iclass 4, count 2 2006.173.12:47:15.09#ibcon#flushed, iclass 4, count 2 2006.173.12:47:15.09#ibcon#about to write, iclass 4, count 2 2006.173.12:47:15.09#ibcon#wrote, iclass 4, count 2 2006.173.12:47:15.09#ibcon#about to read 3, iclass 4, count 2 2006.173.12:47:15.12#ibcon#read 3, iclass 4, count 2 2006.173.12:47:15.12#ibcon#about to read 4, iclass 4, count 2 2006.173.12:47:15.12#ibcon#read 4, iclass 4, count 2 2006.173.12:47:15.12#ibcon#about to read 5, iclass 4, count 2 2006.173.12:47:15.12#ibcon#read 5, iclass 4, count 2 2006.173.12:47:15.12#ibcon#about to read 6, iclass 4, count 2 2006.173.12:47:15.12#ibcon#read 6, iclass 4, count 2 2006.173.12:47:15.12#ibcon#end of sib2, iclass 4, count 2 2006.173.12:47:15.12#ibcon#*after write, iclass 4, count 2 2006.173.12:47:15.12#ibcon#*before return 0, iclass 4, count 2 2006.173.12:47:15.12#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.12:47:15.12#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.12:47:15.12#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.12:47:15.12#ibcon#ireg 7 cls_cnt 0 2006.173.12:47:15.12#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.12:47:15.24#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.12:47:15.24#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.12:47:15.24#ibcon#enter wrdev, iclass 4, count 0 2006.173.12:47:15.24#ibcon#first serial, iclass 4, count 0 2006.173.12:47:15.24#ibcon#enter sib2, iclass 4, count 0 2006.173.12:47:15.24#ibcon#flushed, iclass 4, count 0 2006.173.12:47:15.24#ibcon#about to write, iclass 4, count 0 2006.173.12:47:15.24#ibcon#wrote, iclass 4, count 0 2006.173.12:47:15.24#ibcon#about to read 3, iclass 4, count 0 2006.173.12:47:15.26#ibcon#read 3, iclass 4, count 0 2006.173.12:47:15.26#ibcon#about to read 4, iclass 4, count 0 2006.173.12:47:15.26#ibcon#read 4, iclass 4, count 0 2006.173.12:47:15.26#ibcon#about to read 5, iclass 4, count 0 2006.173.12:47:15.26#ibcon#read 5, iclass 4, count 0 2006.173.12:47:15.26#ibcon#about to read 6, iclass 4, count 0 2006.173.12:47:15.26#ibcon#read 6, iclass 4, count 0 2006.173.12:47:15.26#ibcon#end of sib2, iclass 4, count 0 2006.173.12:47:15.26#ibcon#*mode == 0, iclass 4, count 0 2006.173.12:47:15.26#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.12:47:15.26#ibcon#[25=USB\r\n] 2006.173.12:47:15.26#ibcon#*before write, iclass 4, count 0 2006.173.12:47:15.26#ibcon#enter sib2, iclass 4, count 0 2006.173.12:47:15.26#ibcon#flushed, iclass 4, count 0 2006.173.12:47:15.26#ibcon#about to write, iclass 4, count 0 2006.173.12:47:15.26#ibcon#wrote, iclass 4, count 0 2006.173.12:47:15.26#ibcon#about to read 3, iclass 4, count 0 2006.173.12:47:15.29#ibcon#read 3, iclass 4, count 0 2006.173.12:47:15.29#ibcon#about to read 4, iclass 4, count 0 2006.173.12:47:15.29#ibcon#read 4, iclass 4, count 0 2006.173.12:47:15.29#ibcon#about to read 5, iclass 4, count 0 2006.173.12:47:15.29#ibcon#read 5, iclass 4, count 0 2006.173.12:47:15.29#ibcon#about to read 6, iclass 4, count 0 2006.173.12:47:15.29#ibcon#read 6, iclass 4, count 0 2006.173.12:47:15.29#ibcon#end of sib2, iclass 4, count 0 2006.173.12:47:15.29#ibcon#*after write, iclass 4, count 0 2006.173.12:47:15.29#ibcon#*before return 0, iclass 4, count 0 2006.173.12:47:15.29#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.12:47:15.29#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.12:47:15.29#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.12:47:15.29#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.12:47:15.29$vck44/valo=4,624.99 2006.173.12:47:15.29#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.12:47:15.29#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.12:47:15.29#ibcon#ireg 17 cls_cnt 0 2006.173.12:47:15.29#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.12:47:15.29#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.12:47:15.29#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.12:47:15.29#ibcon#enter wrdev, iclass 6, count 0 2006.173.12:47:15.29#ibcon#first serial, iclass 6, count 0 2006.173.12:47:15.29#ibcon#enter sib2, iclass 6, count 0 2006.173.12:47:15.29#ibcon#flushed, iclass 6, count 0 2006.173.12:47:15.29#ibcon#about to write, iclass 6, count 0 2006.173.12:47:15.29#ibcon#wrote, iclass 6, count 0 2006.173.12:47:15.29#ibcon#about to read 3, iclass 6, count 0 2006.173.12:47:15.31#ibcon#read 3, iclass 6, count 0 2006.173.12:47:15.31#ibcon#about to read 4, iclass 6, count 0 2006.173.12:47:15.31#ibcon#read 4, iclass 6, count 0 2006.173.12:47:15.31#ibcon#about to read 5, iclass 6, count 0 2006.173.12:47:15.31#ibcon#read 5, iclass 6, count 0 2006.173.12:47:15.31#ibcon#about to read 6, iclass 6, count 0 2006.173.12:47:15.31#ibcon#read 6, iclass 6, count 0 2006.173.12:47:15.31#ibcon#end of sib2, iclass 6, count 0 2006.173.12:47:15.31#ibcon#*mode == 0, iclass 6, count 0 2006.173.12:47:15.31#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.12:47:15.31#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.12:47:15.31#ibcon#*before write, iclass 6, count 0 2006.173.12:47:15.31#ibcon#enter sib2, iclass 6, count 0 2006.173.12:47:15.31#ibcon#flushed, iclass 6, count 0 2006.173.12:47:15.31#ibcon#about to write, iclass 6, count 0 2006.173.12:47:15.31#ibcon#wrote, iclass 6, count 0 2006.173.12:47:15.31#ibcon#about to read 3, iclass 6, count 0 2006.173.12:47:15.35#ibcon#read 3, iclass 6, count 0 2006.173.12:47:15.35#ibcon#about to read 4, iclass 6, count 0 2006.173.12:47:15.35#ibcon#read 4, iclass 6, count 0 2006.173.12:47:15.35#ibcon#about to read 5, iclass 6, count 0 2006.173.12:47:15.35#ibcon#read 5, iclass 6, count 0 2006.173.12:47:15.35#ibcon#about to read 6, iclass 6, count 0 2006.173.12:47:15.35#ibcon#read 6, iclass 6, count 0 2006.173.12:47:15.35#ibcon#end of sib2, iclass 6, count 0 2006.173.12:47:15.35#ibcon#*after write, iclass 6, count 0 2006.173.12:47:15.35#ibcon#*before return 0, iclass 6, count 0 2006.173.12:47:15.35#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.12:47:15.35#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.12:47:15.35#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.12:47:15.35#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.12:47:15.35$vck44/va=4,6 2006.173.12:47:15.35#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.12:47:15.35#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.12:47:15.35#ibcon#ireg 11 cls_cnt 2 2006.173.12:47:15.35#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.12:47:15.41#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.12:47:15.41#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.12:47:15.41#ibcon#enter wrdev, iclass 10, count 2 2006.173.12:47:15.41#ibcon#first serial, iclass 10, count 2 2006.173.12:47:15.41#ibcon#enter sib2, iclass 10, count 2 2006.173.12:47:15.41#ibcon#flushed, iclass 10, count 2 2006.173.12:47:15.41#ibcon#about to write, iclass 10, count 2 2006.173.12:47:15.41#ibcon#wrote, iclass 10, count 2 2006.173.12:47:15.41#ibcon#about to read 3, iclass 10, count 2 2006.173.12:47:15.43#ibcon#read 3, iclass 10, count 2 2006.173.12:47:15.43#ibcon#about to read 4, iclass 10, count 2 2006.173.12:47:15.43#ibcon#read 4, iclass 10, count 2 2006.173.12:47:15.43#ibcon#about to read 5, iclass 10, count 2 2006.173.12:47:15.43#ibcon#read 5, iclass 10, count 2 2006.173.12:47:15.43#ibcon#about to read 6, iclass 10, count 2 2006.173.12:47:15.43#ibcon#read 6, iclass 10, count 2 2006.173.12:47:15.43#ibcon#end of sib2, iclass 10, count 2 2006.173.12:47:15.43#ibcon#*mode == 0, iclass 10, count 2 2006.173.12:47:15.43#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.12:47:15.43#ibcon#[25=AT04-06\r\n] 2006.173.12:47:15.43#ibcon#*before write, iclass 10, count 2 2006.173.12:47:15.43#ibcon#enter sib2, iclass 10, count 2 2006.173.12:47:15.43#ibcon#flushed, iclass 10, count 2 2006.173.12:47:15.43#ibcon#about to write, iclass 10, count 2 2006.173.12:47:15.43#ibcon#wrote, iclass 10, count 2 2006.173.12:47:15.43#ibcon#about to read 3, iclass 10, count 2 2006.173.12:47:15.46#ibcon#read 3, iclass 10, count 2 2006.173.12:47:15.46#ibcon#about to read 4, iclass 10, count 2 2006.173.12:47:15.46#ibcon#read 4, iclass 10, count 2 2006.173.12:47:15.46#ibcon#about to read 5, iclass 10, count 2 2006.173.12:47:15.46#ibcon#read 5, iclass 10, count 2 2006.173.12:47:15.46#ibcon#about to read 6, iclass 10, count 2 2006.173.12:47:15.46#ibcon#read 6, iclass 10, count 2 2006.173.12:47:15.46#ibcon#end of sib2, iclass 10, count 2 2006.173.12:47:15.46#ibcon#*after write, iclass 10, count 2 2006.173.12:47:15.46#ibcon#*before return 0, iclass 10, count 2 2006.173.12:47:15.46#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.12:47:15.46#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.12:47:15.46#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.12:47:15.46#ibcon#ireg 7 cls_cnt 0 2006.173.12:47:15.46#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.12:47:15.58#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.12:47:15.58#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.12:47:15.58#ibcon#enter wrdev, iclass 10, count 0 2006.173.12:47:15.58#ibcon#first serial, iclass 10, count 0 2006.173.12:47:15.58#ibcon#enter sib2, iclass 10, count 0 2006.173.12:47:15.58#ibcon#flushed, iclass 10, count 0 2006.173.12:47:15.58#ibcon#about to write, iclass 10, count 0 2006.173.12:47:15.58#ibcon#wrote, iclass 10, count 0 2006.173.12:47:15.58#ibcon#about to read 3, iclass 10, count 0 2006.173.12:47:15.60#ibcon#read 3, iclass 10, count 0 2006.173.12:47:15.60#ibcon#about to read 4, iclass 10, count 0 2006.173.12:47:15.60#ibcon#read 4, iclass 10, count 0 2006.173.12:47:15.60#ibcon#about to read 5, iclass 10, count 0 2006.173.12:47:15.60#ibcon#read 5, iclass 10, count 0 2006.173.12:47:15.60#ibcon#about to read 6, iclass 10, count 0 2006.173.12:47:15.60#ibcon#read 6, iclass 10, count 0 2006.173.12:47:15.60#ibcon#end of sib2, iclass 10, count 0 2006.173.12:47:15.60#ibcon#*mode == 0, iclass 10, count 0 2006.173.12:47:15.60#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.12:47:15.60#ibcon#[25=USB\r\n] 2006.173.12:47:15.60#ibcon#*before write, iclass 10, count 0 2006.173.12:47:15.60#ibcon#enter sib2, iclass 10, count 0 2006.173.12:47:15.60#ibcon#flushed, iclass 10, count 0 2006.173.12:47:15.60#ibcon#about to write, iclass 10, count 0 2006.173.12:47:15.60#ibcon#wrote, iclass 10, count 0 2006.173.12:47:15.60#ibcon#about to read 3, iclass 10, count 0 2006.173.12:47:15.63#ibcon#read 3, iclass 10, count 0 2006.173.12:47:15.63#ibcon#about to read 4, iclass 10, count 0 2006.173.12:47:15.63#ibcon#read 4, iclass 10, count 0 2006.173.12:47:15.63#ibcon#about to read 5, iclass 10, count 0 2006.173.12:47:15.63#ibcon#read 5, iclass 10, count 0 2006.173.12:47:15.63#ibcon#about to read 6, iclass 10, count 0 2006.173.12:47:15.63#ibcon#read 6, iclass 10, count 0 2006.173.12:47:15.63#ibcon#end of sib2, iclass 10, count 0 2006.173.12:47:15.63#ibcon#*after write, iclass 10, count 0 2006.173.12:47:15.63#ibcon#*before return 0, iclass 10, count 0 2006.173.12:47:15.63#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.12:47:15.63#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.12:47:15.63#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.12:47:15.63#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.12:47:15.63$vck44/valo=5,734.99 2006.173.12:47:15.63#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.12:47:15.63#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.12:47:15.63#ibcon#ireg 17 cls_cnt 0 2006.173.12:47:15.63#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.12:47:15.63#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.12:47:15.63#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.12:47:15.63#ibcon#enter wrdev, iclass 12, count 0 2006.173.12:47:15.63#ibcon#first serial, iclass 12, count 0 2006.173.12:47:15.63#ibcon#enter sib2, iclass 12, count 0 2006.173.12:47:15.63#ibcon#flushed, iclass 12, count 0 2006.173.12:47:15.63#ibcon#about to write, iclass 12, count 0 2006.173.12:47:15.63#ibcon#wrote, iclass 12, count 0 2006.173.12:47:15.63#ibcon#about to read 3, iclass 12, count 0 2006.173.12:47:15.65#ibcon#read 3, iclass 12, count 0 2006.173.12:47:15.65#ibcon#about to read 4, iclass 12, count 0 2006.173.12:47:15.65#ibcon#read 4, iclass 12, count 0 2006.173.12:47:15.65#ibcon#about to read 5, iclass 12, count 0 2006.173.12:47:15.65#ibcon#read 5, iclass 12, count 0 2006.173.12:47:15.65#ibcon#about to read 6, iclass 12, count 0 2006.173.12:47:15.65#ibcon#read 6, iclass 12, count 0 2006.173.12:47:15.65#ibcon#end of sib2, iclass 12, count 0 2006.173.12:47:15.65#ibcon#*mode == 0, iclass 12, count 0 2006.173.12:47:15.65#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.12:47:15.65#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.12:47:15.65#ibcon#*before write, iclass 12, count 0 2006.173.12:47:15.65#ibcon#enter sib2, iclass 12, count 0 2006.173.12:47:15.65#ibcon#flushed, iclass 12, count 0 2006.173.12:47:15.65#ibcon#about to write, iclass 12, count 0 2006.173.12:47:15.65#ibcon#wrote, iclass 12, count 0 2006.173.12:47:15.65#ibcon#about to read 3, iclass 12, count 0 2006.173.12:47:15.69#ibcon#read 3, iclass 12, count 0 2006.173.12:47:15.69#ibcon#about to read 4, iclass 12, count 0 2006.173.12:47:15.69#ibcon#read 4, iclass 12, count 0 2006.173.12:47:15.69#ibcon#about to read 5, iclass 12, count 0 2006.173.12:47:15.69#ibcon#read 5, iclass 12, count 0 2006.173.12:47:15.69#ibcon#about to read 6, iclass 12, count 0 2006.173.12:47:15.69#ibcon#read 6, iclass 12, count 0 2006.173.12:47:15.69#ibcon#end of sib2, iclass 12, count 0 2006.173.12:47:15.69#ibcon#*after write, iclass 12, count 0 2006.173.12:47:15.69#ibcon#*before return 0, iclass 12, count 0 2006.173.12:47:15.69#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.12:47:15.69#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.12:47:15.69#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.12:47:15.69#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.12:47:15.69$vck44/va=5,4 2006.173.12:47:15.69#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.12:47:15.69#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.12:47:15.69#ibcon#ireg 11 cls_cnt 2 2006.173.12:47:15.69#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.12:47:15.75#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.12:47:15.75#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.12:47:15.75#ibcon#enter wrdev, iclass 14, count 2 2006.173.12:47:15.75#ibcon#first serial, iclass 14, count 2 2006.173.12:47:15.75#ibcon#enter sib2, iclass 14, count 2 2006.173.12:47:15.75#ibcon#flushed, iclass 14, count 2 2006.173.12:47:15.75#ibcon#about to write, iclass 14, count 2 2006.173.12:47:15.75#ibcon#wrote, iclass 14, count 2 2006.173.12:47:15.75#ibcon#about to read 3, iclass 14, count 2 2006.173.12:47:15.77#ibcon#read 3, iclass 14, count 2 2006.173.12:47:15.77#ibcon#about to read 4, iclass 14, count 2 2006.173.12:47:15.77#ibcon#read 4, iclass 14, count 2 2006.173.12:47:15.77#ibcon#about to read 5, iclass 14, count 2 2006.173.12:47:15.77#ibcon#read 5, iclass 14, count 2 2006.173.12:47:15.77#ibcon#about to read 6, iclass 14, count 2 2006.173.12:47:15.77#ibcon#read 6, iclass 14, count 2 2006.173.12:47:15.77#ibcon#end of sib2, iclass 14, count 2 2006.173.12:47:15.77#ibcon#*mode == 0, iclass 14, count 2 2006.173.12:47:15.77#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.12:47:15.77#ibcon#[25=AT05-04\r\n] 2006.173.12:47:15.77#ibcon#*before write, iclass 14, count 2 2006.173.12:47:15.77#ibcon#enter sib2, iclass 14, count 2 2006.173.12:47:15.77#ibcon#flushed, iclass 14, count 2 2006.173.12:47:15.77#ibcon#about to write, iclass 14, count 2 2006.173.12:47:15.77#ibcon#wrote, iclass 14, count 2 2006.173.12:47:15.77#ibcon#about to read 3, iclass 14, count 2 2006.173.12:47:15.80#ibcon#read 3, iclass 14, count 2 2006.173.12:47:15.80#ibcon#about to read 4, iclass 14, count 2 2006.173.12:47:15.80#ibcon#read 4, iclass 14, count 2 2006.173.12:47:15.80#ibcon#about to read 5, iclass 14, count 2 2006.173.12:47:15.80#ibcon#read 5, iclass 14, count 2 2006.173.12:47:15.80#ibcon#about to read 6, iclass 14, count 2 2006.173.12:47:15.80#ibcon#read 6, iclass 14, count 2 2006.173.12:47:15.80#ibcon#end of sib2, iclass 14, count 2 2006.173.12:47:15.80#ibcon#*after write, iclass 14, count 2 2006.173.12:47:15.80#ibcon#*before return 0, iclass 14, count 2 2006.173.12:47:15.80#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.12:47:15.80#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.12:47:15.80#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.12:47:15.80#ibcon#ireg 7 cls_cnt 0 2006.173.12:47:15.80#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.12:47:15.92#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.12:47:15.92#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.12:47:15.92#ibcon#enter wrdev, iclass 14, count 0 2006.173.12:47:15.92#ibcon#first serial, iclass 14, count 0 2006.173.12:47:15.92#ibcon#enter sib2, iclass 14, count 0 2006.173.12:47:15.92#ibcon#flushed, iclass 14, count 0 2006.173.12:47:15.92#ibcon#about to write, iclass 14, count 0 2006.173.12:47:15.92#ibcon#wrote, iclass 14, count 0 2006.173.12:47:15.92#ibcon#about to read 3, iclass 14, count 0 2006.173.12:47:15.94#ibcon#read 3, iclass 14, count 0 2006.173.12:47:15.94#ibcon#about to read 4, iclass 14, count 0 2006.173.12:47:15.94#ibcon#read 4, iclass 14, count 0 2006.173.12:47:15.94#ibcon#about to read 5, iclass 14, count 0 2006.173.12:47:15.94#ibcon#read 5, iclass 14, count 0 2006.173.12:47:15.94#ibcon#about to read 6, iclass 14, count 0 2006.173.12:47:15.94#ibcon#read 6, iclass 14, count 0 2006.173.12:47:15.94#ibcon#end of sib2, iclass 14, count 0 2006.173.12:47:15.94#ibcon#*mode == 0, iclass 14, count 0 2006.173.12:47:15.94#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.12:47:15.94#ibcon#[25=USB\r\n] 2006.173.12:47:15.94#ibcon#*before write, iclass 14, count 0 2006.173.12:47:15.94#ibcon#enter sib2, iclass 14, count 0 2006.173.12:47:15.94#ibcon#flushed, iclass 14, count 0 2006.173.12:47:15.94#ibcon#about to write, iclass 14, count 0 2006.173.12:47:15.94#ibcon#wrote, iclass 14, count 0 2006.173.12:47:15.94#ibcon#about to read 3, iclass 14, count 0 2006.173.12:47:15.97#ibcon#read 3, iclass 14, count 0 2006.173.12:47:15.97#ibcon#about to read 4, iclass 14, count 0 2006.173.12:47:15.97#ibcon#read 4, iclass 14, count 0 2006.173.12:47:15.97#ibcon#about to read 5, iclass 14, count 0 2006.173.12:47:15.97#ibcon#read 5, iclass 14, count 0 2006.173.12:47:15.97#ibcon#about to read 6, iclass 14, count 0 2006.173.12:47:15.97#ibcon#read 6, iclass 14, count 0 2006.173.12:47:15.97#ibcon#end of sib2, iclass 14, count 0 2006.173.12:47:15.97#ibcon#*after write, iclass 14, count 0 2006.173.12:47:15.97#ibcon#*before return 0, iclass 14, count 0 2006.173.12:47:15.97#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.12:47:15.97#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.12:47:15.97#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.12:47:15.97#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.12:47:15.97$vck44/valo=6,814.99 2006.173.12:47:15.97#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.12:47:15.97#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.12:47:15.97#ibcon#ireg 17 cls_cnt 0 2006.173.12:47:15.97#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.12:47:15.97#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.12:47:15.97#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.12:47:15.97#ibcon#enter wrdev, iclass 16, count 0 2006.173.12:47:15.97#ibcon#first serial, iclass 16, count 0 2006.173.12:47:15.97#ibcon#enter sib2, iclass 16, count 0 2006.173.12:47:15.97#ibcon#flushed, iclass 16, count 0 2006.173.12:47:15.97#ibcon#about to write, iclass 16, count 0 2006.173.12:47:15.97#ibcon#wrote, iclass 16, count 0 2006.173.12:47:15.97#ibcon#about to read 3, iclass 16, count 0 2006.173.12:47:15.99#ibcon#read 3, iclass 16, count 0 2006.173.12:47:15.99#ibcon#about to read 4, iclass 16, count 0 2006.173.12:47:15.99#ibcon#read 4, iclass 16, count 0 2006.173.12:47:15.99#ibcon#about to read 5, iclass 16, count 0 2006.173.12:47:15.99#ibcon#read 5, iclass 16, count 0 2006.173.12:47:15.99#ibcon#about to read 6, iclass 16, count 0 2006.173.12:47:15.99#ibcon#read 6, iclass 16, count 0 2006.173.12:47:15.99#ibcon#end of sib2, iclass 16, count 0 2006.173.12:47:15.99#ibcon#*mode == 0, iclass 16, count 0 2006.173.12:47:15.99#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.12:47:15.99#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.12:47:15.99#ibcon#*before write, iclass 16, count 0 2006.173.12:47:15.99#ibcon#enter sib2, iclass 16, count 0 2006.173.12:47:15.99#ibcon#flushed, iclass 16, count 0 2006.173.12:47:15.99#ibcon#about to write, iclass 16, count 0 2006.173.12:47:15.99#ibcon#wrote, iclass 16, count 0 2006.173.12:47:15.99#ibcon#about to read 3, iclass 16, count 0 2006.173.12:47:16.03#ibcon#read 3, iclass 16, count 0 2006.173.12:47:16.03#ibcon#about to read 4, iclass 16, count 0 2006.173.12:47:16.03#ibcon#read 4, iclass 16, count 0 2006.173.12:47:16.03#ibcon#about to read 5, iclass 16, count 0 2006.173.12:47:16.03#ibcon#read 5, iclass 16, count 0 2006.173.12:47:16.03#ibcon#about to read 6, iclass 16, count 0 2006.173.12:47:16.03#ibcon#read 6, iclass 16, count 0 2006.173.12:47:16.03#ibcon#end of sib2, iclass 16, count 0 2006.173.12:47:16.03#ibcon#*after write, iclass 16, count 0 2006.173.12:47:16.03#ibcon#*before return 0, iclass 16, count 0 2006.173.12:47:16.03#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.12:47:16.03#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.12:47:16.03#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.12:47:16.03#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.12:47:16.03$vck44/va=6,3 2006.173.12:47:16.03#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.12:47:16.03#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.12:47:16.03#ibcon#ireg 11 cls_cnt 2 2006.173.12:47:16.03#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.12:47:16.09#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.12:47:16.09#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.12:47:16.09#ibcon#enter wrdev, iclass 18, count 2 2006.173.12:47:16.09#ibcon#first serial, iclass 18, count 2 2006.173.12:47:16.09#ibcon#enter sib2, iclass 18, count 2 2006.173.12:47:16.09#ibcon#flushed, iclass 18, count 2 2006.173.12:47:16.09#ibcon#about to write, iclass 18, count 2 2006.173.12:47:16.09#ibcon#wrote, iclass 18, count 2 2006.173.12:47:16.09#ibcon#about to read 3, iclass 18, count 2 2006.173.12:47:16.11#ibcon#read 3, iclass 18, count 2 2006.173.12:47:16.11#ibcon#about to read 4, iclass 18, count 2 2006.173.12:47:16.11#ibcon#read 4, iclass 18, count 2 2006.173.12:47:16.11#ibcon#about to read 5, iclass 18, count 2 2006.173.12:47:16.11#ibcon#read 5, iclass 18, count 2 2006.173.12:47:16.11#ibcon#about to read 6, iclass 18, count 2 2006.173.12:47:16.11#ibcon#read 6, iclass 18, count 2 2006.173.12:47:16.11#ibcon#end of sib2, iclass 18, count 2 2006.173.12:47:16.11#ibcon#*mode == 0, iclass 18, count 2 2006.173.12:47:16.11#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.12:47:16.11#ibcon#[25=AT06-03\r\n] 2006.173.12:47:16.11#ibcon#*before write, iclass 18, count 2 2006.173.12:47:16.11#ibcon#enter sib2, iclass 18, count 2 2006.173.12:47:16.11#ibcon#flushed, iclass 18, count 2 2006.173.12:47:16.11#ibcon#about to write, iclass 18, count 2 2006.173.12:47:16.11#ibcon#wrote, iclass 18, count 2 2006.173.12:47:16.11#ibcon#about to read 3, iclass 18, count 2 2006.173.12:47:16.14#ibcon#read 3, iclass 18, count 2 2006.173.12:47:16.14#ibcon#about to read 4, iclass 18, count 2 2006.173.12:47:16.14#ibcon#read 4, iclass 18, count 2 2006.173.12:47:16.14#ibcon#about to read 5, iclass 18, count 2 2006.173.12:47:16.14#ibcon#read 5, iclass 18, count 2 2006.173.12:47:16.14#ibcon#about to read 6, iclass 18, count 2 2006.173.12:47:16.14#ibcon#read 6, iclass 18, count 2 2006.173.12:47:16.14#ibcon#end of sib2, iclass 18, count 2 2006.173.12:47:16.14#ibcon#*after write, iclass 18, count 2 2006.173.12:47:16.14#ibcon#*before return 0, iclass 18, count 2 2006.173.12:47:16.14#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.12:47:16.14#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.12:47:16.14#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.12:47:16.14#ibcon#ireg 7 cls_cnt 0 2006.173.12:47:16.14#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.12:47:16.26#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.12:47:16.26#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.12:47:16.26#ibcon#enter wrdev, iclass 18, count 0 2006.173.12:47:16.26#ibcon#first serial, iclass 18, count 0 2006.173.12:47:16.26#ibcon#enter sib2, iclass 18, count 0 2006.173.12:47:16.26#ibcon#flushed, iclass 18, count 0 2006.173.12:47:16.26#ibcon#about to write, iclass 18, count 0 2006.173.12:47:16.26#ibcon#wrote, iclass 18, count 0 2006.173.12:47:16.26#ibcon#about to read 3, iclass 18, count 0 2006.173.12:47:16.28#ibcon#read 3, iclass 18, count 0 2006.173.12:47:16.28#ibcon#about to read 4, iclass 18, count 0 2006.173.12:47:16.28#ibcon#read 4, iclass 18, count 0 2006.173.12:47:16.28#ibcon#about to read 5, iclass 18, count 0 2006.173.12:47:16.28#ibcon#read 5, iclass 18, count 0 2006.173.12:47:16.28#ibcon#about to read 6, iclass 18, count 0 2006.173.12:47:16.28#ibcon#read 6, iclass 18, count 0 2006.173.12:47:16.28#ibcon#end of sib2, iclass 18, count 0 2006.173.12:47:16.28#ibcon#*mode == 0, iclass 18, count 0 2006.173.12:47:16.28#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.12:47:16.28#ibcon#[25=USB\r\n] 2006.173.12:47:16.28#ibcon#*before write, iclass 18, count 0 2006.173.12:47:16.28#ibcon#enter sib2, iclass 18, count 0 2006.173.12:47:16.28#ibcon#flushed, iclass 18, count 0 2006.173.12:47:16.28#ibcon#about to write, iclass 18, count 0 2006.173.12:47:16.28#ibcon#wrote, iclass 18, count 0 2006.173.12:47:16.28#ibcon#about to read 3, iclass 18, count 0 2006.173.12:47:16.31#ibcon#read 3, iclass 18, count 0 2006.173.12:47:16.31#ibcon#about to read 4, iclass 18, count 0 2006.173.12:47:16.31#ibcon#read 4, iclass 18, count 0 2006.173.12:47:16.31#ibcon#about to read 5, iclass 18, count 0 2006.173.12:47:16.31#ibcon#read 5, iclass 18, count 0 2006.173.12:47:16.31#ibcon#about to read 6, iclass 18, count 0 2006.173.12:47:16.31#ibcon#read 6, iclass 18, count 0 2006.173.12:47:16.31#ibcon#end of sib2, iclass 18, count 0 2006.173.12:47:16.31#ibcon#*after write, iclass 18, count 0 2006.173.12:47:16.31#ibcon#*before return 0, iclass 18, count 0 2006.173.12:47:16.31#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.12:47:16.31#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.12:47:16.31#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.12:47:16.31#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.12:47:16.31$vck44/valo=7,864.99 2006.173.12:47:16.31#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.12:47:16.31#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.12:47:16.31#ibcon#ireg 17 cls_cnt 0 2006.173.12:47:16.31#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.12:47:16.31#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.12:47:16.31#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.12:47:16.31#ibcon#enter wrdev, iclass 20, count 0 2006.173.12:47:16.31#ibcon#first serial, iclass 20, count 0 2006.173.12:47:16.31#ibcon#enter sib2, iclass 20, count 0 2006.173.12:47:16.31#ibcon#flushed, iclass 20, count 0 2006.173.12:47:16.31#ibcon#about to write, iclass 20, count 0 2006.173.12:47:16.31#ibcon#wrote, iclass 20, count 0 2006.173.12:47:16.31#ibcon#about to read 3, iclass 20, count 0 2006.173.12:47:16.33#ibcon#read 3, iclass 20, count 0 2006.173.12:47:16.33#ibcon#about to read 4, iclass 20, count 0 2006.173.12:47:16.33#ibcon#read 4, iclass 20, count 0 2006.173.12:47:16.33#ibcon#about to read 5, iclass 20, count 0 2006.173.12:47:16.33#ibcon#read 5, iclass 20, count 0 2006.173.12:47:16.33#ibcon#about to read 6, iclass 20, count 0 2006.173.12:47:16.33#ibcon#read 6, iclass 20, count 0 2006.173.12:47:16.33#ibcon#end of sib2, iclass 20, count 0 2006.173.12:47:16.33#ibcon#*mode == 0, iclass 20, count 0 2006.173.12:47:16.33#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.12:47:16.33#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.12:47:16.33#ibcon#*before write, iclass 20, count 0 2006.173.12:47:16.33#ibcon#enter sib2, iclass 20, count 0 2006.173.12:47:16.33#ibcon#flushed, iclass 20, count 0 2006.173.12:47:16.33#ibcon#about to write, iclass 20, count 0 2006.173.12:47:16.33#ibcon#wrote, iclass 20, count 0 2006.173.12:47:16.33#ibcon#about to read 3, iclass 20, count 0 2006.173.12:47:16.37#ibcon#read 3, iclass 20, count 0 2006.173.12:47:16.37#ibcon#about to read 4, iclass 20, count 0 2006.173.12:47:16.37#ibcon#read 4, iclass 20, count 0 2006.173.12:47:16.37#ibcon#about to read 5, iclass 20, count 0 2006.173.12:47:16.37#ibcon#read 5, iclass 20, count 0 2006.173.12:47:16.37#ibcon#about to read 6, iclass 20, count 0 2006.173.12:47:16.37#ibcon#read 6, iclass 20, count 0 2006.173.12:47:16.37#ibcon#end of sib2, iclass 20, count 0 2006.173.12:47:16.37#ibcon#*after write, iclass 20, count 0 2006.173.12:47:16.37#ibcon#*before return 0, iclass 20, count 0 2006.173.12:47:16.37#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.12:47:16.37#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.12:47:16.37#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.12:47:16.37#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.12:47:16.37$vck44/va=7,4 2006.173.12:47:16.37#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.12:47:16.37#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.12:47:16.37#ibcon#ireg 11 cls_cnt 2 2006.173.12:47:16.37#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.12:47:16.43#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.12:47:16.43#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.12:47:16.43#ibcon#enter wrdev, iclass 22, count 2 2006.173.12:47:16.43#ibcon#first serial, iclass 22, count 2 2006.173.12:47:16.43#ibcon#enter sib2, iclass 22, count 2 2006.173.12:47:16.43#ibcon#flushed, iclass 22, count 2 2006.173.12:47:16.43#ibcon#about to write, iclass 22, count 2 2006.173.12:47:16.43#ibcon#wrote, iclass 22, count 2 2006.173.12:47:16.43#ibcon#about to read 3, iclass 22, count 2 2006.173.12:47:16.45#ibcon#read 3, iclass 22, count 2 2006.173.12:47:16.45#ibcon#about to read 4, iclass 22, count 2 2006.173.12:47:16.45#ibcon#read 4, iclass 22, count 2 2006.173.12:47:16.45#ibcon#about to read 5, iclass 22, count 2 2006.173.12:47:16.45#ibcon#read 5, iclass 22, count 2 2006.173.12:47:16.45#ibcon#about to read 6, iclass 22, count 2 2006.173.12:47:16.45#ibcon#read 6, iclass 22, count 2 2006.173.12:47:16.45#ibcon#end of sib2, iclass 22, count 2 2006.173.12:47:16.45#ibcon#*mode == 0, iclass 22, count 2 2006.173.12:47:16.45#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.12:47:16.45#ibcon#[25=AT07-04\r\n] 2006.173.12:47:16.45#ibcon#*before write, iclass 22, count 2 2006.173.12:47:16.45#ibcon#enter sib2, iclass 22, count 2 2006.173.12:47:16.45#ibcon#flushed, iclass 22, count 2 2006.173.12:47:16.45#ibcon#about to write, iclass 22, count 2 2006.173.12:47:16.45#ibcon#wrote, iclass 22, count 2 2006.173.12:47:16.45#ibcon#about to read 3, iclass 22, count 2 2006.173.12:47:16.48#ibcon#read 3, iclass 22, count 2 2006.173.12:47:16.48#ibcon#about to read 4, iclass 22, count 2 2006.173.12:47:16.48#ibcon#read 4, iclass 22, count 2 2006.173.12:47:16.48#ibcon#about to read 5, iclass 22, count 2 2006.173.12:47:16.48#ibcon#read 5, iclass 22, count 2 2006.173.12:47:16.48#ibcon#about to read 6, iclass 22, count 2 2006.173.12:47:16.48#ibcon#read 6, iclass 22, count 2 2006.173.12:47:16.48#ibcon#end of sib2, iclass 22, count 2 2006.173.12:47:16.48#ibcon#*after write, iclass 22, count 2 2006.173.12:47:16.48#ibcon#*before return 0, iclass 22, count 2 2006.173.12:47:16.48#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.12:47:16.48#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.12:47:16.48#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.12:47:16.48#ibcon#ireg 7 cls_cnt 0 2006.173.12:47:16.48#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.12:47:16.60#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.12:47:16.60#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.12:47:16.60#ibcon#enter wrdev, iclass 22, count 0 2006.173.12:47:16.60#ibcon#first serial, iclass 22, count 0 2006.173.12:47:16.60#ibcon#enter sib2, iclass 22, count 0 2006.173.12:47:16.60#ibcon#flushed, iclass 22, count 0 2006.173.12:47:16.60#ibcon#about to write, iclass 22, count 0 2006.173.12:47:16.60#ibcon#wrote, iclass 22, count 0 2006.173.12:47:16.60#ibcon#about to read 3, iclass 22, count 0 2006.173.12:47:16.62#ibcon#read 3, iclass 22, count 0 2006.173.12:47:16.62#ibcon#about to read 4, iclass 22, count 0 2006.173.12:47:16.62#ibcon#read 4, iclass 22, count 0 2006.173.12:47:16.62#ibcon#about to read 5, iclass 22, count 0 2006.173.12:47:16.62#ibcon#read 5, iclass 22, count 0 2006.173.12:47:16.62#ibcon#about to read 6, iclass 22, count 0 2006.173.12:47:16.62#ibcon#read 6, iclass 22, count 0 2006.173.12:47:16.62#ibcon#end of sib2, iclass 22, count 0 2006.173.12:47:16.62#ibcon#*mode == 0, iclass 22, count 0 2006.173.12:47:16.62#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.12:47:16.62#ibcon#[25=USB\r\n] 2006.173.12:47:16.62#ibcon#*before write, iclass 22, count 0 2006.173.12:47:16.62#ibcon#enter sib2, iclass 22, count 0 2006.173.12:47:16.62#ibcon#flushed, iclass 22, count 0 2006.173.12:47:16.62#ibcon#about to write, iclass 22, count 0 2006.173.12:47:16.62#ibcon#wrote, iclass 22, count 0 2006.173.12:47:16.62#ibcon#about to read 3, iclass 22, count 0 2006.173.12:47:16.65#ibcon#read 3, iclass 22, count 0 2006.173.12:47:16.65#ibcon#about to read 4, iclass 22, count 0 2006.173.12:47:16.65#ibcon#read 4, iclass 22, count 0 2006.173.12:47:16.65#ibcon#about to read 5, iclass 22, count 0 2006.173.12:47:16.65#ibcon#read 5, iclass 22, count 0 2006.173.12:47:16.65#ibcon#about to read 6, iclass 22, count 0 2006.173.12:47:16.65#ibcon#read 6, iclass 22, count 0 2006.173.12:47:16.65#ibcon#end of sib2, iclass 22, count 0 2006.173.12:47:16.65#ibcon#*after write, iclass 22, count 0 2006.173.12:47:16.65#ibcon#*before return 0, iclass 22, count 0 2006.173.12:47:16.65#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.12:47:16.65#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.12:47:16.65#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.12:47:16.65#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.12:47:16.65$vck44/valo=8,884.99 2006.173.12:47:16.65#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.12:47:16.65#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.12:47:16.65#ibcon#ireg 17 cls_cnt 0 2006.173.12:47:16.65#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.12:47:16.65#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.12:47:16.65#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.12:47:16.65#ibcon#enter wrdev, iclass 24, count 0 2006.173.12:47:16.65#ibcon#first serial, iclass 24, count 0 2006.173.12:47:16.65#ibcon#enter sib2, iclass 24, count 0 2006.173.12:47:16.65#ibcon#flushed, iclass 24, count 0 2006.173.12:47:16.65#ibcon#about to write, iclass 24, count 0 2006.173.12:47:16.65#ibcon#wrote, iclass 24, count 0 2006.173.12:47:16.65#ibcon#about to read 3, iclass 24, count 0 2006.173.12:47:16.67#ibcon#read 3, iclass 24, count 0 2006.173.12:47:16.67#ibcon#about to read 4, iclass 24, count 0 2006.173.12:47:16.67#ibcon#read 4, iclass 24, count 0 2006.173.12:47:16.67#ibcon#about to read 5, iclass 24, count 0 2006.173.12:47:16.67#ibcon#read 5, iclass 24, count 0 2006.173.12:47:16.67#ibcon#about to read 6, iclass 24, count 0 2006.173.12:47:16.67#ibcon#read 6, iclass 24, count 0 2006.173.12:47:16.67#ibcon#end of sib2, iclass 24, count 0 2006.173.12:47:16.67#ibcon#*mode == 0, iclass 24, count 0 2006.173.12:47:16.67#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.12:47:16.67#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.12:47:16.67#ibcon#*before write, iclass 24, count 0 2006.173.12:47:16.67#ibcon#enter sib2, iclass 24, count 0 2006.173.12:47:16.67#ibcon#flushed, iclass 24, count 0 2006.173.12:47:16.67#ibcon#about to write, iclass 24, count 0 2006.173.12:47:16.67#ibcon#wrote, iclass 24, count 0 2006.173.12:47:16.67#ibcon#about to read 3, iclass 24, count 0 2006.173.12:47:16.71#ibcon#read 3, iclass 24, count 0 2006.173.12:47:16.71#ibcon#about to read 4, iclass 24, count 0 2006.173.12:47:16.71#ibcon#read 4, iclass 24, count 0 2006.173.12:47:16.71#ibcon#about to read 5, iclass 24, count 0 2006.173.12:47:16.71#ibcon#read 5, iclass 24, count 0 2006.173.12:47:16.71#ibcon#about to read 6, iclass 24, count 0 2006.173.12:47:16.71#ibcon#read 6, iclass 24, count 0 2006.173.12:47:16.71#ibcon#end of sib2, iclass 24, count 0 2006.173.12:47:16.71#ibcon#*after write, iclass 24, count 0 2006.173.12:47:16.71#ibcon#*before return 0, iclass 24, count 0 2006.173.12:47:16.71#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.12:47:16.71#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.12:47:16.71#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.12:47:16.71#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.12:47:16.71$vck44/va=8,4 2006.173.12:47:16.71#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.12:47:16.71#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.12:47:16.71#ibcon#ireg 11 cls_cnt 2 2006.173.12:47:16.71#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.12:47:16.77#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.12:47:16.77#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.12:47:16.77#ibcon#enter wrdev, iclass 26, count 2 2006.173.12:47:16.77#ibcon#first serial, iclass 26, count 2 2006.173.12:47:16.77#ibcon#enter sib2, iclass 26, count 2 2006.173.12:47:16.77#ibcon#flushed, iclass 26, count 2 2006.173.12:47:16.77#ibcon#about to write, iclass 26, count 2 2006.173.12:47:16.77#ibcon#wrote, iclass 26, count 2 2006.173.12:47:16.77#ibcon#about to read 3, iclass 26, count 2 2006.173.12:47:16.79#ibcon#read 3, iclass 26, count 2 2006.173.12:47:16.79#ibcon#about to read 4, iclass 26, count 2 2006.173.12:47:16.79#ibcon#read 4, iclass 26, count 2 2006.173.12:47:16.79#ibcon#about to read 5, iclass 26, count 2 2006.173.12:47:16.79#ibcon#read 5, iclass 26, count 2 2006.173.12:47:16.79#ibcon#about to read 6, iclass 26, count 2 2006.173.12:47:16.79#ibcon#read 6, iclass 26, count 2 2006.173.12:47:16.79#ibcon#end of sib2, iclass 26, count 2 2006.173.12:47:16.79#ibcon#*mode == 0, iclass 26, count 2 2006.173.12:47:16.79#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.12:47:16.79#ibcon#[25=AT08-04\r\n] 2006.173.12:47:16.79#ibcon#*before write, iclass 26, count 2 2006.173.12:47:16.79#ibcon#enter sib2, iclass 26, count 2 2006.173.12:47:16.79#ibcon#flushed, iclass 26, count 2 2006.173.12:47:16.79#ibcon#about to write, iclass 26, count 2 2006.173.12:47:16.79#ibcon#wrote, iclass 26, count 2 2006.173.12:47:16.79#ibcon#about to read 3, iclass 26, count 2 2006.173.12:47:16.82#ibcon#read 3, iclass 26, count 2 2006.173.12:47:16.82#ibcon#about to read 4, iclass 26, count 2 2006.173.12:47:16.82#ibcon#read 4, iclass 26, count 2 2006.173.12:47:16.82#ibcon#about to read 5, iclass 26, count 2 2006.173.12:47:16.82#ibcon#read 5, iclass 26, count 2 2006.173.12:47:16.82#ibcon#about to read 6, iclass 26, count 2 2006.173.12:47:16.82#ibcon#read 6, iclass 26, count 2 2006.173.12:47:16.82#ibcon#end of sib2, iclass 26, count 2 2006.173.12:47:16.82#ibcon#*after write, iclass 26, count 2 2006.173.12:47:16.82#ibcon#*before return 0, iclass 26, count 2 2006.173.12:47:16.82#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.12:47:16.82#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.12:47:16.82#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.12:47:16.82#ibcon#ireg 7 cls_cnt 0 2006.173.12:47:16.82#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.12:47:16.94#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.12:47:16.94#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.12:47:16.94#ibcon#enter wrdev, iclass 26, count 0 2006.173.12:47:16.94#ibcon#first serial, iclass 26, count 0 2006.173.12:47:16.94#ibcon#enter sib2, iclass 26, count 0 2006.173.12:47:16.94#ibcon#flushed, iclass 26, count 0 2006.173.12:47:16.94#ibcon#about to write, iclass 26, count 0 2006.173.12:47:16.94#ibcon#wrote, iclass 26, count 0 2006.173.12:47:16.94#ibcon#about to read 3, iclass 26, count 0 2006.173.12:47:16.96#ibcon#read 3, iclass 26, count 0 2006.173.12:47:16.96#ibcon#about to read 4, iclass 26, count 0 2006.173.12:47:16.96#ibcon#read 4, iclass 26, count 0 2006.173.12:47:16.96#ibcon#about to read 5, iclass 26, count 0 2006.173.12:47:16.96#ibcon#read 5, iclass 26, count 0 2006.173.12:47:16.96#ibcon#about to read 6, iclass 26, count 0 2006.173.12:47:16.96#ibcon#read 6, iclass 26, count 0 2006.173.12:47:16.96#ibcon#end of sib2, iclass 26, count 0 2006.173.12:47:16.96#ibcon#*mode == 0, iclass 26, count 0 2006.173.12:47:16.96#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.12:47:16.96#ibcon#[25=USB\r\n] 2006.173.12:47:16.96#ibcon#*before write, iclass 26, count 0 2006.173.12:47:16.96#ibcon#enter sib2, iclass 26, count 0 2006.173.12:47:16.96#ibcon#flushed, iclass 26, count 0 2006.173.12:47:16.96#ibcon#about to write, iclass 26, count 0 2006.173.12:47:16.96#ibcon#wrote, iclass 26, count 0 2006.173.12:47:16.96#ibcon#about to read 3, iclass 26, count 0 2006.173.12:47:16.99#ibcon#read 3, iclass 26, count 0 2006.173.12:47:16.99#ibcon#about to read 4, iclass 26, count 0 2006.173.12:47:16.99#ibcon#read 4, iclass 26, count 0 2006.173.12:47:16.99#ibcon#about to read 5, iclass 26, count 0 2006.173.12:47:16.99#ibcon#read 5, iclass 26, count 0 2006.173.12:47:16.99#ibcon#about to read 6, iclass 26, count 0 2006.173.12:47:16.99#ibcon#read 6, iclass 26, count 0 2006.173.12:47:16.99#ibcon#end of sib2, iclass 26, count 0 2006.173.12:47:16.99#ibcon#*after write, iclass 26, count 0 2006.173.12:47:16.99#ibcon#*before return 0, iclass 26, count 0 2006.173.12:47:16.99#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.12:47:16.99#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.12:47:16.99#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.12:47:16.99#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.12:47:16.99$vck44/vblo=1,629.99 2006.173.12:47:16.99#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.12:47:16.99#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.12:47:16.99#ibcon#ireg 17 cls_cnt 0 2006.173.12:47:16.99#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.12:47:16.99#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.12:47:16.99#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.12:47:16.99#ibcon#enter wrdev, iclass 28, count 0 2006.173.12:47:16.99#ibcon#first serial, iclass 28, count 0 2006.173.12:47:16.99#ibcon#enter sib2, iclass 28, count 0 2006.173.12:47:16.99#ibcon#flushed, iclass 28, count 0 2006.173.12:47:16.99#ibcon#about to write, iclass 28, count 0 2006.173.12:47:16.99#ibcon#wrote, iclass 28, count 0 2006.173.12:47:16.99#ibcon#about to read 3, iclass 28, count 0 2006.173.12:47:17.01#ibcon#read 3, iclass 28, count 0 2006.173.12:47:17.01#ibcon#about to read 4, iclass 28, count 0 2006.173.12:47:17.01#ibcon#read 4, iclass 28, count 0 2006.173.12:47:17.01#ibcon#about to read 5, iclass 28, count 0 2006.173.12:47:17.01#ibcon#read 5, iclass 28, count 0 2006.173.12:47:17.01#ibcon#about to read 6, iclass 28, count 0 2006.173.12:47:17.01#ibcon#read 6, iclass 28, count 0 2006.173.12:47:17.01#ibcon#end of sib2, iclass 28, count 0 2006.173.12:47:17.01#ibcon#*mode == 0, iclass 28, count 0 2006.173.12:47:17.01#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.12:47:17.01#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.12:47:17.01#ibcon#*before write, iclass 28, count 0 2006.173.12:47:17.01#ibcon#enter sib2, iclass 28, count 0 2006.173.12:47:17.01#ibcon#flushed, iclass 28, count 0 2006.173.12:47:17.01#ibcon#about to write, iclass 28, count 0 2006.173.12:47:17.01#ibcon#wrote, iclass 28, count 0 2006.173.12:47:17.01#ibcon#about to read 3, iclass 28, count 0 2006.173.12:47:17.05#ibcon#read 3, iclass 28, count 0 2006.173.12:47:17.05#ibcon#about to read 4, iclass 28, count 0 2006.173.12:47:17.05#ibcon#read 4, iclass 28, count 0 2006.173.12:47:17.05#ibcon#about to read 5, iclass 28, count 0 2006.173.12:47:17.05#ibcon#read 5, iclass 28, count 0 2006.173.12:47:17.05#ibcon#about to read 6, iclass 28, count 0 2006.173.12:47:17.05#ibcon#read 6, iclass 28, count 0 2006.173.12:47:17.05#ibcon#end of sib2, iclass 28, count 0 2006.173.12:47:17.05#ibcon#*after write, iclass 28, count 0 2006.173.12:47:17.05#ibcon#*before return 0, iclass 28, count 0 2006.173.12:47:17.05#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.12:47:17.05#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.12:47:17.05#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.12:47:17.05#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.12:47:17.05$vck44/vb=1,4 2006.173.12:47:17.05#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.12:47:17.05#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.12:47:17.05#ibcon#ireg 11 cls_cnt 2 2006.173.12:47:17.05#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.12:47:17.05#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.12:47:17.05#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.12:47:17.05#ibcon#enter wrdev, iclass 31, count 2 2006.173.12:47:17.05#ibcon#first serial, iclass 31, count 2 2006.173.12:47:17.05#ibcon#enter sib2, iclass 31, count 2 2006.173.12:47:17.05#ibcon#flushed, iclass 31, count 2 2006.173.12:47:17.05#ibcon#about to write, iclass 31, count 2 2006.173.12:47:17.05#ibcon#wrote, iclass 31, count 2 2006.173.12:47:17.05#ibcon#about to read 3, iclass 31, count 2 2006.173.12:47:17.07#ibcon#read 3, iclass 31, count 2 2006.173.12:47:17.07#ibcon#about to read 4, iclass 31, count 2 2006.173.12:47:17.07#ibcon#read 4, iclass 31, count 2 2006.173.12:47:17.07#ibcon#about to read 5, iclass 31, count 2 2006.173.12:47:17.07#ibcon#read 5, iclass 31, count 2 2006.173.12:47:17.07#ibcon#about to read 6, iclass 31, count 2 2006.173.12:47:17.07#ibcon#read 6, iclass 31, count 2 2006.173.12:47:17.07#ibcon#end of sib2, iclass 31, count 2 2006.173.12:47:17.07#ibcon#*mode == 0, iclass 31, count 2 2006.173.12:47:17.07#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.12:47:17.07#ibcon#[27=AT01-04\r\n] 2006.173.12:47:17.07#ibcon#*before write, iclass 31, count 2 2006.173.12:47:17.07#ibcon#enter sib2, iclass 31, count 2 2006.173.12:47:17.07#ibcon#flushed, iclass 31, count 2 2006.173.12:47:17.07#ibcon#about to write, iclass 31, count 2 2006.173.12:47:17.07#ibcon#wrote, iclass 31, count 2 2006.173.12:47:17.07#ibcon#about to read 3, iclass 31, count 2 2006.173.12:47:17.07#abcon#<5=/03 1.3 1.9 22.13 951004.3\r\n> 2006.173.12:47:17.09#abcon#{5=INTERFACE CLEAR} 2006.173.12:47:17.10#ibcon#read 3, iclass 31, count 2 2006.173.12:47:17.10#ibcon#about to read 4, iclass 31, count 2 2006.173.12:47:17.10#ibcon#read 4, iclass 31, count 2 2006.173.12:47:17.10#ibcon#about to read 5, iclass 31, count 2 2006.173.12:47:17.10#ibcon#read 5, iclass 31, count 2 2006.173.12:47:17.10#ibcon#about to read 6, iclass 31, count 2 2006.173.12:47:17.10#ibcon#read 6, iclass 31, count 2 2006.173.12:47:17.10#ibcon#end of sib2, iclass 31, count 2 2006.173.12:47:17.10#ibcon#*after write, iclass 31, count 2 2006.173.12:47:17.10#ibcon#*before return 0, iclass 31, count 2 2006.173.12:47:17.10#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.12:47:17.10#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.12:47:17.10#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.12:47:17.10#ibcon#ireg 7 cls_cnt 0 2006.173.12:47:17.10#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.12:47:17.15#abcon#[5=S1D000X0/0*\r\n] 2006.173.12:47:17.22#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.12:47:17.22#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.12:47:17.22#ibcon#enter wrdev, iclass 31, count 0 2006.173.12:47:17.22#ibcon#first serial, iclass 31, count 0 2006.173.12:47:17.22#ibcon#enter sib2, iclass 31, count 0 2006.173.12:47:17.22#ibcon#flushed, iclass 31, count 0 2006.173.12:47:17.22#ibcon#about to write, iclass 31, count 0 2006.173.12:47:17.22#ibcon#wrote, iclass 31, count 0 2006.173.12:47:17.22#ibcon#about to read 3, iclass 31, count 0 2006.173.12:47:17.24#ibcon#read 3, iclass 31, count 0 2006.173.12:47:17.24#ibcon#about to read 4, iclass 31, count 0 2006.173.12:47:17.24#ibcon#read 4, iclass 31, count 0 2006.173.12:47:17.24#ibcon#about to read 5, iclass 31, count 0 2006.173.12:47:17.24#ibcon#read 5, iclass 31, count 0 2006.173.12:47:17.24#ibcon#about to read 6, iclass 31, count 0 2006.173.12:47:17.24#ibcon#read 6, iclass 31, count 0 2006.173.12:47:17.24#ibcon#end of sib2, iclass 31, count 0 2006.173.12:47:17.24#ibcon#*mode == 0, iclass 31, count 0 2006.173.12:47:17.24#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.12:47:17.24#ibcon#[27=USB\r\n] 2006.173.12:47:17.24#ibcon#*before write, iclass 31, count 0 2006.173.12:47:17.24#ibcon#enter sib2, iclass 31, count 0 2006.173.12:47:17.24#ibcon#flushed, iclass 31, count 0 2006.173.12:47:17.24#ibcon#about to write, iclass 31, count 0 2006.173.12:47:17.24#ibcon#wrote, iclass 31, count 0 2006.173.12:47:17.24#ibcon#about to read 3, iclass 31, count 0 2006.173.12:47:17.27#ibcon#read 3, iclass 31, count 0 2006.173.12:47:17.27#ibcon#about to read 4, iclass 31, count 0 2006.173.12:47:17.27#ibcon#read 4, iclass 31, count 0 2006.173.12:47:17.27#ibcon#about to read 5, iclass 31, count 0 2006.173.12:47:17.27#ibcon#read 5, iclass 31, count 0 2006.173.12:47:17.27#ibcon#about to read 6, iclass 31, count 0 2006.173.12:47:17.27#ibcon#read 6, iclass 31, count 0 2006.173.12:47:17.27#ibcon#end of sib2, iclass 31, count 0 2006.173.12:47:17.27#ibcon#*after write, iclass 31, count 0 2006.173.12:47:17.27#ibcon#*before return 0, iclass 31, count 0 2006.173.12:47:17.27#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.12:47:17.27#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.12:47:17.27#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.12:47:17.27#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.12:47:17.27$vck44/vblo=2,634.99 2006.173.12:47:17.27#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.12:47:17.27#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.12:47:17.27#ibcon#ireg 17 cls_cnt 0 2006.173.12:47:17.27#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.12:47:17.27#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.12:47:17.27#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.12:47:17.27#ibcon#enter wrdev, iclass 36, count 0 2006.173.12:47:17.27#ibcon#first serial, iclass 36, count 0 2006.173.12:47:17.27#ibcon#enter sib2, iclass 36, count 0 2006.173.12:47:17.27#ibcon#flushed, iclass 36, count 0 2006.173.12:47:17.27#ibcon#about to write, iclass 36, count 0 2006.173.12:47:17.27#ibcon#wrote, iclass 36, count 0 2006.173.12:47:17.27#ibcon#about to read 3, iclass 36, count 0 2006.173.12:47:17.29#ibcon#read 3, iclass 36, count 0 2006.173.12:47:17.29#ibcon#about to read 4, iclass 36, count 0 2006.173.12:47:17.29#ibcon#read 4, iclass 36, count 0 2006.173.12:47:17.29#ibcon#about to read 5, iclass 36, count 0 2006.173.12:47:17.29#ibcon#read 5, iclass 36, count 0 2006.173.12:47:17.29#ibcon#about to read 6, iclass 36, count 0 2006.173.12:47:17.29#ibcon#read 6, iclass 36, count 0 2006.173.12:47:17.29#ibcon#end of sib2, iclass 36, count 0 2006.173.12:47:17.29#ibcon#*mode == 0, iclass 36, count 0 2006.173.12:47:17.29#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.12:47:17.29#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.12:47:17.29#ibcon#*before write, iclass 36, count 0 2006.173.12:47:17.29#ibcon#enter sib2, iclass 36, count 0 2006.173.12:47:17.29#ibcon#flushed, iclass 36, count 0 2006.173.12:47:17.29#ibcon#about to write, iclass 36, count 0 2006.173.12:47:17.29#ibcon#wrote, iclass 36, count 0 2006.173.12:47:17.29#ibcon#about to read 3, iclass 36, count 0 2006.173.12:47:17.33#ibcon#read 3, iclass 36, count 0 2006.173.12:47:17.33#ibcon#about to read 4, iclass 36, count 0 2006.173.12:47:17.33#ibcon#read 4, iclass 36, count 0 2006.173.12:47:17.33#ibcon#about to read 5, iclass 36, count 0 2006.173.12:47:17.33#ibcon#read 5, iclass 36, count 0 2006.173.12:47:17.33#ibcon#about to read 6, iclass 36, count 0 2006.173.12:47:17.33#ibcon#read 6, iclass 36, count 0 2006.173.12:47:17.33#ibcon#end of sib2, iclass 36, count 0 2006.173.12:47:17.33#ibcon#*after write, iclass 36, count 0 2006.173.12:47:17.33#ibcon#*before return 0, iclass 36, count 0 2006.173.12:47:17.33#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.12:47:17.33#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.12:47:17.33#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.12:47:17.33#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.12:47:17.33$vck44/vb=2,4 2006.173.12:47:17.33#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.12:47:17.33#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.12:47:17.33#ibcon#ireg 11 cls_cnt 2 2006.173.12:47:17.33#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.12:47:17.39#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.12:47:17.39#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.12:47:17.39#ibcon#enter wrdev, iclass 38, count 2 2006.173.12:47:17.39#ibcon#first serial, iclass 38, count 2 2006.173.12:47:17.39#ibcon#enter sib2, iclass 38, count 2 2006.173.12:47:17.39#ibcon#flushed, iclass 38, count 2 2006.173.12:47:17.39#ibcon#about to write, iclass 38, count 2 2006.173.12:47:17.39#ibcon#wrote, iclass 38, count 2 2006.173.12:47:17.39#ibcon#about to read 3, iclass 38, count 2 2006.173.12:47:17.41#ibcon#read 3, iclass 38, count 2 2006.173.12:47:17.41#ibcon#about to read 4, iclass 38, count 2 2006.173.12:47:17.41#ibcon#read 4, iclass 38, count 2 2006.173.12:47:17.41#ibcon#about to read 5, iclass 38, count 2 2006.173.12:47:17.41#ibcon#read 5, iclass 38, count 2 2006.173.12:47:17.41#ibcon#about to read 6, iclass 38, count 2 2006.173.12:47:17.41#ibcon#read 6, iclass 38, count 2 2006.173.12:47:17.41#ibcon#end of sib2, iclass 38, count 2 2006.173.12:47:17.41#ibcon#*mode == 0, iclass 38, count 2 2006.173.12:47:17.41#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.12:47:17.41#ibcon#[27=AT02-04\r\n] 2006.173.12:47:17.41#ibcon#*before write, iclass 38, count 2 2006.173.12:47:17.41#ibcon#enter sib2, iclass 38, count 2 2006.173.12:47:17.41#ibcon#flushed, iclass 38, count 2 2006.173.12:47:17.41#ibcon#about to write, iclass 38, count 2 2006.173.12:47:17.41#ibcon#wrote, iclass 38, count 2 2006.173.12:47:17.41#ibcon#about to read 3, iclass 38, count 2 2006.173.12:47:17.44#ibcon#read 3, iclass 38, count 2 2006.173.12:47:17.44#ibcon#about to read 4, iclass 38, count 2 2006.173.12:47:17.44#ibcon#read 4, iclass 38, count 2 2006.173.12:47:17.44#ibcon#about to read 5, iclass 38, count 2 2006.173.12:47:17.44#ibcon#read 5, iclass 38, count 2 2006.173.12:47:17.44#ibcon#about to read 6, iclass 38, count 2 2006.173.12:47:17.44#ibcon#read 6, iclass 38, count 2 2006.173.12:47:17.44#ibcon#end of sib2, iclass 38, count 2 2006.173.12:47:17.44#ibcon#*after write, iclass 38, count 2 2006.173.12:47:17.44#ibcon#*before return 0, iclass 38, count 2 2006.173.12:47:17.44#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.12:47:17.44#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.12:47:17.44#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.12:47:17.44#ibcon#ireg 7 cls_cnt 0 2006.173.12:47:17.44#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.12:47:17.56#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.12:47:17.56#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.12:47:17.56#ibcon#enter wrdev, iclass 38, count 0 2006.173.12:47:17.56#ibcon#first serial, iclass 38, count 0 2006.173.12:47:17.56#ibcon#enter sib2, iclass 38, count 0 2006.173.12:47:17.56#ibcon#flushed, iclass 38, count 0 2006.173.12:47:17.56#ibcon#about to write, iclass 38, count 0 2006.173.12:47:17.56#ibcon#wrote, iclass 38, count 0 2006.173.12:47:17.56#ibcon#about to read 3, iclass 38, count 0 2006.173.12:47:17.58#ibcon#read 3, iclass 38, count 0 2006.173.12:47:17.58#ibcon#about to read 4, iclass 38, count 0 2006.173.12:47:17.58#ibcon#read 4, iclass 38, count 0 2006.173.12:47:17.58#ibcon#about to read 5, iclass 38, count 0 2006.173.12:47:17.58#ibcon#read 5, iclass 38, count 0 2006.173.12:47:17.58#ibcon#about to read 6, iclass 38, count 0 2006.173.12:47:17.58#ibcon#read 6, iclass 38, count 0 2006.173.12:47:17.58#ibcon#end of sib2, iclass 38, count 0 2006.173.12:47:17.58#ibcon#*mode == 0, iclass 38, count 0 2006.173.12:47:17.58#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.12:47:17.58#ibcon#[27=USB\r\n] 2006.173.12:47:17.58#ibcon#*before write, iclass 38, count 0 2006.173.12:47:17.58#ibcon#enter sib2, iclass 38, count 0 2006.173.12:47:17.58#ibcon#flushed, iclass 38, count 0 2006.173.12:47:17.58#ibcon#about to write, iclass 38, count 0 2006.173.12:47:17.58#ibcon#wrote, iclass 38, count 0 2006.173.12:47:17.58#ibcon#about to read 3, iclass 38, count 0 2006.173.12:47:17.61#ibcon#read 3, iclass 38, count 0 2006.173.12:47:17.61#ibcon#about to read 4, iclass 38, count 0 2006.173.12:47:17.61#ibcon#read 4, iclass 38, count 0 2006.173.12:47:17.61#ibcon#about to read 5, iclass 38, count 0 2006.173.12:47:17.61#ibcon#read 5, iclass 38, count 0 2006.173.12:47:17.61#ibcon#about to read 6, iclass 38, count 0 2006.173.12:47:17.61#ibcon#read 6, iclass 38, count 0 2006.173.12:47:17.61#ibcon#end of sib2, iclass 38, count 0 2006.173.12:47:17.61#ibcon#*after write, iclass 38, count 0 2006.173.12:47:17.61#ibcon#*before return 0, iclass 38, count 0 2006.173.12:47:17.61#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.12:47:17.61#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.12:47:17.61#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.12:47:17.61#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.12:47:17.61$vck44/vblo=3,649.99 2006.173.12:47:17.61#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.12:47:17.61#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.12:47:17.61#ibcon#ireg 17 cls_cnt 0 2006.173.12:47:17.61#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.12:47:17.61#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.12:47:17.61#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.12:47:17.61#ibcon#enter wrdev, iclass 40, count 0 2006.173.12:47:17.61#ibcon#first serial, iclass 40, count 0 2006.173.12:47:17.61#ibcon#enter sib2, iclass 40, count 0 2006.173.12:47:17.61#ibcon#flushed, iclass 40, count 0 2006.173.12:47:17.61#ibcon#about to write, iclass 40, count 0 2006.173.12:47:17.61#ibcon#wrote, iclass 40, count 0 2006.173.12:47:17.61#ibcon#about to read 3, iclass 40, count 0 2006.173.12:47:17.63#ibcon#read 3, iclass 40, count 0 2006.173.12:47:17.63#ibcon#about to read 4, iclass 40, count 0 2006.173.12:47:17.63#ibcon#read 4, iclass 40, count 0 2006.173.12:47:17.63#ibcon#about to read 5, iclass 40, count 0 2006.173.12:47:17.63#ibcon#read 5, iclass 40, count 0 2006.173.12:47:17.63#ibcon#about to read 6, iclass 40, count 0 2006.173.12:47:17.63#ibcon#read 6, iclass 40, count 0 2006.173.12:47:17.63#ibcon#end of sib2, iclass 40, count 0 2006.173.12:47:17.63#ibcon#*mode == 0, iclass 40, count 0 2006.173.12:47:17.63#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.12:47:17.63#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.12:47:17.63#ibcon#*before write, iclass 40, count 0 2006.173.12:47:17.63#ibcon#enter sib2, iclass 40, count 0 2006.173.12:47:17.63#ibcon#flushed, iclass 40, count 0 2006.173.12:47:17.63#ibcon#about to write, iclass 40, count 0 2006.173.12:47:17.63#ibcon#wrote, iclass 40, count 0 2006.173.12:47:17.63#ibcon#about to read 3, iclass 40, count 0 2006.173.12:47:17.67#ibcon#read 3, iclass 40, count 0 2006.173.12:47:17.67#ibcon#about to read 4, iclass 40, count 0 2006.173.12:47:17.67#ibcon#read 4, iclass 40, count 0 2006.173.12:47:17.67#ibcon#about to read 5, iclass 40, count 0 2006.173.12:47:17.67#ibcon#read 5, iclass 40, count 0 2006.173.12:47:17.67#ibcon#about to read 6, iclass 40, count 0 2006.173.12:47:17.67#ibcon#read 6, iclass 40, count 0 2006.173.12:47:17.67#ibcon#end of sib2, iclass 40, count 0 2006.173.12:47:17.67#ibcon#*after write, iclass 40, count 0 2006.173.12:47:17.67#ibcon#*before return 0, iclass 40, count 0 2006.173.12:47:17.67#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.12:47:17.67#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.12:47:17.67#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.12:47:17.67#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.12:47:17.67$vck44/vb=3,4 2006.173.12:47:17.67#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.12:47:17.67#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.12:47:17.67#ibcon#ireg 11 cls_cnt 2 2006.173.12:47:17.67#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.12:47:17.73#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.12:47:17.73#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.12:47:17.73#ibcon#enter wrdev, iclass 4, count 2 2006.173.12:47:17.73#ibcon#first serial, iclass 4, count 2 2006.173.12:47:17.73#ibcon#enter sib2, iclass 4, count 2 2006.173.12:47:17.73#ibcon#flushed, iclass 4, count 2 2006.173.12:47:17.73#ibcon#about to write, iclass 4, count 2 2006.173.12:47:17.73#ibcon#wrote, iclass 4, count 2 2006.173.12:47:17.73#ibcon#about to read 3, iclass 4, count 2 2006.173.12:47:17.75#ibcon#read 3, iclass 4, count 2 2006.173.12:47:17.75#ibcon#about to read 4, iclass 4, count 2 2006.173.12:47:17.75#ibcon#read 4, iclass 4, count 2 2006.173.12:47:17.75#ibcon#about to read 5, iclass 4, count 2 2006.173.12:47:17.75#ibcon#read 5, iclass 4, count 2 2006.173.12:47:17.75#ibcon#about to read 6, iclass 4, count 2 2006.173.12:47:17.75#ibcon#read 6, iclass 4, count 2 2006.173.12:47:17.75#ibcon#end of sib2, iclass 4, count 2 2006.173.12:47:17.75#ibcon#*mode == 0, iclass 4, count 2 2006.173.12:47:17.75#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.12:47:17.75#ibcon#[27=AT03-04\r\n] 2006.173.12:47:17.75#ibcon#*before write, iclass 4, count 2 2006.173.12:47:17.75#ibcon#enter sib2, iclass 4, count 2 2006.173.12:47:17.75#ibcon#flushed, iclass 4, count 2 2006.173.12:47:17.75#ibcon#about to write, iclass 4, count 2 2006.173.12:47:17.75#ibcon#wrote, iclass 4, count 2 2006.173.12:47:17.75#ibcon#about to read 3, iclass 4, count 2 2006.173.12:47:17.78#ibcon#read 3, iclass 4, count 2 2006.173.12:47:17.78#ibcon#about to read 4, iclass 4, count 2 2006.173.12:47:17.78#ibcon#read 4, iclass 4, count 2 2006.173.12:47:17.78#ibcon#about to read 5, iclass 4, count 2 2006.173.12:47:17.78#ibcon#read 5, iclass 4, count 2 2006.173.12:47:17.78#ibcon#about to read 6, iclass 4, count 2 2006.173.12:47:17.78#ibcon#read 6, iclass 4, count 2 2006.173.12:47:17.78#ibcon#end of sib2, iclass 4, count 2 2006.173.12:47:17.78#ibcon#*after write, iclass 4, count 2 2006.173.12:47:17.78#ibcon#*before return 0, iclass 4, count 2 2006.173.12:47:17.78#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.12:47:17.78#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.12:47:17.78#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.12:47:17.78#ibcon#ireg 7 cls_cnt 0 2006.173.12:47:17.78#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.12:47:17.90#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.12:47:17.90#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.12:47:17.90#ibcon#enter wrdev, iclass 4, count 0 2006.173.12:47:17.90#ibcon#first serial, iclass 4, count 0 2006.173.12:47:17.90#ibcon#enter sib2, iclass 4, count 0 2006.173.12:47:17.90#ibcon#flushed, iclass 4, count 0 2006.173.12:47:17.90#ibcon#about to write, iclass 4, count 0 2006.173.12:47:17.90#ibcon#wrote, iclass 4, count 0 2006.173.12:47:17.90#ibcon#about to read 3, iclass 4, count 0 2006.173.12:47:17.92#ibcon#read 3, iclass 4, count 0 2006.173.12:47:17.92#ibcon#about to read 4, iclass 4, count 0 2006.173.12:47:17.92#ibcon#read 4, iclass 4, count 0 2006.173.12:47:17.92#ibcon#about to read 5, iclass 4, count 0 2006.173.12:47:17.92#ibcon#read 5, iclass 4, count 0 2006.173.12:47:17.92#ibcon#about to read 6, iclass 4, count 0 2006.173.12:47:17.92#ibcon#read 6, iclass 4, count 0 2006.173.12:47:17.92#ibcon#end of sib2, iclass 4, count 0 2006.173.12:47:17.92#ibcon#*mode == 0, iclass 4, count 0 2006.173.12:47:17.92#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.12:47:17.92#ibcon#[27=USB\r\n] 2006.173.12:47:17.92#ibcon#*before write, iclass 4, count 0 2006.173.12:47:17.92#ibcon#enter sib2, iclass 4, count 0 2006.173.12:47:17.92#ibcon#flushed, iclass 4, count 0 2006.173.12:47:17.92#ibcon#about to write, iclass 4, count 0 2006.173.12:47:17.92#ibcon#wrote, iclass 4, count 0 2006.173.12:47:17.92#ibcon#about to read 3, iclass 4, count 0 2006.173.12:47:17.95#ibcon#read 3, iclass 4, count 0 2006.173.12:47:17.95#ibcon#about to read 4, iclass 4, count 0 2006.173.12:47:17.95#ibcon#read 4, iclass 4, count 0 2006.173.12:47:17.95#ibcon#about to read 5, iclass 4, count 0 2006.173.12:47:17.95#ibcon#read 5, iclass 4, count 0 2006.173.12:47:17.95#ibcon#about to read 6, iclass 4, count 0 2006.173.12:47:17.95#ibcon#read 6, iclass 4, count 0 2006.173.12:47:17.95#ibcon#end of sib2, iclass 4, count 0 2006.173.12:47:17.95#ibcon#*after write, iclass 4, count 0 2006.173.12:47:17.95#ibcon#*before return 0, iclass 4, count 0 2006.173.12:47:17.95#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.12:47:17.95#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.12:47:17.95#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.12:47:17.95#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.12:47:17.95$vck44/vblo=4,679.99 2006.173.12:47:17.95#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.12:47:17.95#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.12:47:17.95#ibcon#ireg 17 cls_cnt 0 2006.173.12:47:17.95#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.12:47:17.95#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.12:47:17.95#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.12:47:17.95#ibcon#enter wrdev, iclass 6, count 0 2006.173.12:47:17.95#ibcon#first serial, iclass 6, count 0 2006.173.12:47:17.95#ibcon#enter sib2, iclass 6, count 0 2006.173.12:47:17.95#ibcon#flushed, iclass 6, count 0 2006.173.12:47:17.95#ibcon#about to write, iclass 6, count 0 2006.173.12:47:17.95#ibcon#wrote, iclass 6, count 0 2006.173.12:47:17.95#ibcon#about to read 3, iclass 6, count 0 2006.173.12:47:17.97#ibcon#read 3, iclass 6, count 0 2006.173.12:47:17.97#ibcon#about to read 4, iclass 6, count 0 2006.173.12:47:17.97#ibcon#read 4, iclass 6, count 0 2006.173.12:47:17.97#ibcon#about to read 5, iclass 6, count 0 2006.173.12:47:17.97#ibcon#read 5, iclass 6, count 0 2006.173.12:47:17.97#ibcon#about to read 6, iclass 6, count 0 2006.173.12:47:17.97#ibcon#read 6, iclass 6, count 0 2006.173.12:47:17.97#ibcon#end of sib2, iclass 6, count 0 2006.173.12:47:17.97#ibcon#*mode == 0, iclass 6, count 0 2006.173.12:47:17.97#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.12:47:17.97#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.12:47:17.97#ibcon#*before write, iclass 6, count 0 2006.173.12:47:17.97#ibcon#enter sib2, iclass 6, count 0 2006.173.12:47:17.97#ibcon#flushed, iclass 6, count 0 2006.173.12:47:17.97#ibcon#about to write, iclass 6, count 0 2006.173.12:47:17.97#ibcon#wrote, iclass 6, count 0 2006.173.12:47:17.97#ibcon#about to read 3, iclass 6, count 0 2006.173.12:47:18.01#ibcon#read 3, iclass 6, count 0 2006.173.12:47:18.01#ibcon#about to read 4, iclass 6, count 0 2006.173.12:47:18.01#ibcon#read 4, iclass 6, count 0 2006.173.12:47:18.01#ibcon#about to read 5, iclass 6, count 0 2006.173.12:47:18.01#ibcon#read 5, iclass 6, count 0 2006.173.12:47:18.01#ibcon#about to read 6, iclass 6, count 0 2006.173.12:47:18.01#ibcon#read 6, iclass 6, count 0 2006.173.12:47:18.01#ibcon#end of sib2, iclass 6, count 0 2006.173.12:47:18.01#ibcon#*after write, iclass 6, count 0 2006.173.12:47:18.01#ibcon#*before return 0, iclass 6, count 0 2006.173.12:47:18.01#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.12:47:18.01#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.12:47:18.01#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.12:47:18.01#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.12:47:18.01$vck44/vb=4,4 2006.173.12:47:18.01#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.12:47:18.01#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.12:47:18.01#ibcon#ireg 11 cls_cnt 2 2006.173.12:47:18.01#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.12:47:18.07#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.12:47:18.07#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.12:47:18.07#ibcon#enter wrdev, iclass 10, count 2 2006.173.12:47:18.07#ibcon#first serial, iclass 10, count 2 2006.173.12:47:18.07#ibcon#enter sib2, iclass 10, count 2 2006.173.12:47:18.07#ibcon#flushed, iclass 10, count 2 2006.173.12:47:18.07#ibcon#about to write, iclass 10, count 2 2006.173.12:47:18.07#ibcon#wrote, iclass 10, count 2 2006.173.12:47:18.07#ibcon#about to read 3, iclass 10, count 2 2006.173.12:47:18.09#ibcon#read 3, iclass 10, count 2 2006.173.12:47:18.09#ibcon#about to read 4, iclass 10, count 2 2006.173.12:47:18.09#ibcon#read 4, iclass 10, count 2 2006.173.12:47:18.09#ibcon#about to read 5, iclass 10, count 2 2006.173.12:47:18.09#ibcon#read 5, iclass 10, count 2 2006.173.12:47:18.09#ibcon#about to read 6, iclass 10, count 2 2006.173.12:47:18.09#ibcon#read 6, iclass 10, count 2 2006.173.12:47:18.09#ibcon#end of sib2, iclass 10, count 2 2006.173.12:47:18.09#ibcon#*mode == 0, iclass 10, count 2 2006.173.12:47:18.09#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.12:47:18.09#ibcon#[27=AT04-04\r\n] 2006.173.12:47:18.09#ibcon#*before write, iclass 10, count 2 2006.173.12:47:18.09#ibcon#enter sib2, iclass 10, count 2 2006.173.12:47:18.09#ibcon#flushed, iclass 10, count 2 2006.173.12:47:18.09#ibcon#about to write, iclass 10, count 2 2006.173.12:47:18.09#ibcon#wrote, iclass 10, count 2 2006.173.12:47:18.09#ibcon#about to read 3, iclass 10, count 2 2006.173.12:47:18.12#ibcon#read 3, iclass 10, count 2 2006.173.12:47:18.12#ibcon#about to read 4, iclass 10, count 2 2006.173.12:47:18.12#ibcon#read 4, iclass 10, count 2 2006.173.12:47:18.12#ibcon#about to read 5, iclass 10, count 2 2006.173.12:47:18.12#ibcon#read 5, iclass 10, count 2 2006.173.12:47:18.12#ibcon#about to read 6, iclass 10, count 2 2006.173.12:47:18.12#ibcon#read 6, iclass 10, count 2 2006.173.12:47:18.12#ibcon#end of sib2, iclass 10, count 2 2006.173.12:47:18.12#ibcon#*after write, iclass 10, count 2 2006.173.12:47:18.12#ibcon#*before return 0, iclass 10, count 2 2006.173.12:47:18.12#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.12:47:18.12#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.12:47:18.12#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.12:47:18.12#ibcon#ireg 7 cls_cnt 0 2006.173.12:47:18.12#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.12:47:18.24#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.12:47:18.24#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.12:47:18.24#ibcon#enter wrdev, iclass 10, count 0 2006.173.12:47:18.24#ibcon#first serial, iclass 10, count 0 2006.173.12:47:18.24#ibcon#enter sib2, iclass 10, count 0 2006.173.12:47:18.24#ibcon#flushed, iclass 10, count 0 2006.173.12:47:18.24#ibcon#about to write, iclass 10, count 0 2006.173.12:47:18.24#ibcon#wrote, iclass 10, count 0 2006.173.12:47:18.24#ibcon#about to read 3, iclass 10, count 0 2006.173.12:47:18.26#ibcon#read 3, iclass 10, count 0 2006.173.12:47:18.26#ibcon#about to read 4, iclass 10, count 0 2006.173.12:47:18.26#ibcon#read 4, iclass 10, count 0 2006.173.12:47:18.26#ibcon#about to read 5, iclass 10, count 0 2006.173.12:47:18.26#ibcon#read 5, iclass 10, count 0 2006.173.12:47:18.26#ibcon#about to read 6, iclass 10, count 0 2006.173.12:47:18.26#ibcon#read 6, iclass 10, count 0 2006.173.12:47:18.26#ibcon#end of sib2, iclass 10, count 0 2006.173.12:47:18.26#ibcon#*mode == 0, iclass 10, count 0 2006.173.12:47:18.26#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.12:47:18.26#ibcon#[27=USB\r\n] 2006.173.12:47:18.26#ibcon#*before write, iclass 10, count 0 2006.173.12:47:18.26#ibcon#enter sib2, iclass 10, count 0 2006.173.12:47:18.26#ibcon#flushed, iclass 10, count 0 2006.173.12:47:18.26#ibcon#about to write, iclass 10, count 0 2006.173.12:47:18.26#ibcon#wrote, iclass 10, count 0 2006.173.12:47:18.26#ibcon#about to read 3, iclass 10, count 0 2006.173.12:47:18.29#ibcon#read 3, iclass 10, count 0 2006.173.12:47:18.29#ibcon#about to read 4, iclass 10, count 0 2006.173.12:47:18.29#ibcon#read 4, iclass 10, count 0 2006.173.12:47:18.29#ibcon#about to read 5, iclass 10, count 0 2006.173.12:47:18.29#ibcon#read 5, iclass 10, count 0 2006.173.12:47:18.29#ibcon#about to read 6, iclass 10, count 0 2006.173.12:47:18.29#ibcon#read 6, iclass 10, count 0 2006.173.12:47:18.29#ibcon#end of sib2, iclass 10, count 0 2006.173.12:47:18.29#ibcon#*after write, iclass 10, count 0 2006.173.12:47:18.29#ibcon#*before return 0, iclass 10, count 0 2006.173.12:47:18.29#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.12:47:18.29#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.12:47:18.29#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.12:47:18.29#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.12:47:18.29$vck44/vblo=5,709.99 2006.173.12:47:18.29#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.12:47:18.29#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.12:47:18.29#ibcon#ireg 17 cls_cnt 0 2006.173.12:47:18.29#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.12:47:18.29#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.12:47:18.29#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.12:47:18.29#ibcon#enter wrdev, iclass 12, count 0 2006.173.12:47:18.29#ibcon#first serial, iclass 12, count 0 2006.173.12:47:18.29#ibcon#enter sib2, iclass 12, count 0 2006.173.12:47:18.29#ibcon#flushed, iclass 12, count 0 2006.173.12:47:18.29#ibcon#about to write, iclass 12, count 0 2006.173.12:47:18.29#ibcon#wrote, iclass 12, count 0 2006.173.12:47:18.29#ibcon#about to read 3, iclass 12, count 0 2006.173.12:47:18.31#ibcon#read 3, iclass 12, count 0 2006.173.12:47:18.31#ibcon#about to read 4, iclass 12, count 0 2006.173.12:47:18.31#ibcon#read 4, iclass 12, count 0 2006.173.12:47:18.31#ibcon#about to read 5, iclass 12, count 0 2006.173.12:47:18.31#ibcon#read 5, iclass 12, count 0 2006.173.12:47:18.31#ibcon#about to read 6, iclass 12, count 0 2006.173.12:47:18.31#ibcon#read 6, iclass 12, count 0 2006.173.12:47:18.31#ibcon#end of sib2, iclass 12, count 0 2006.173.12:47:18.31#ibcon#*mode == 0, iclass 12, count 0 2006.173.12:47:18.31#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.12:47:18.31#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.12:47:18.31#ibcon#*before write, iclass 12, count 0 2006.173.12:47:18.31#ibcon#enter sib2, iclass 12, count 0 2006.173.12:47:18.31#ibcon#flushed, iclass 12, count 0 2006.173.12:47:18.31#ibcon#about to write, iclass 12, count 0 2006.173.12:47:18.31#ibcon#wrote, iclass 12, count 0 2006.173.12:47:18.31#ibcon#about to read 3, iclass 12, count 0 2006.173.12:47:18.35#ibcon#read 3, iclass 12, count 0 2006.173.12:47:18.35#ibcon#about to read 4, iclass 12, count 0 2006.173.12:47:18.35#ibcon#read 4, iclass 12, count 0 2006.173.12:47:18.35#ibcon#about to read 5, iclass 12, count 0 2006.173.12:47:18.35#ibcon#read 5, iclass 12, count 0 2006.173.12:47:18.35#ibcon#about to read 6, iclass 12, count 0 2006.173.12:47:18.35#ibcon#read 6, iclass 12, count 0 2006.173.12:47:18.35#ibcon#end of sib2, iclass 12, count 0 2006.173.12:47:18.35#ibcon#*after write, iclass 12, count 0 2006.173.12:47:18.35#ibcon#*before return 0, iclass 12, count 0 2006.173.12:47:18.35#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.12:47:18.35#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.12:47:18.35#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.12:47:18.35#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.12:47:18.35$vck44/vb=5,4 2006.173.12:47:18.35#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.12:47:18.35#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.12:47:18.35#ibcon#ireg 11 cls_cnt 2 2006.173.12:47:18.35#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.12:47:18.41#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.12:47:18.41#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.12:47:18.41#ibcon#enter wrdev, iclass 14, count 2 2006.173.12:47:18.41#ibcon#first serial, iclass 14, count 2 2006.173.12:47:18.41#ibcon#enter sib2, iclass 14, count 2 2006.173.12:47:18.41#ibcon#flushed, iclass 14, count 2 2006.173.12:47:18.41#ibcon#about to write, iclass 14, count 2 2006.173.12:47:18.41#ibcon#wrote, iclass 14, count 2 2006.173.12:47:18.41#ibcon#about to read 3, iclass 14, count 2 2006.173.12:47:18.43#ibcon#read 3, iclass 14, count 2 2006.173.12:47:18.43#ibcon#about to read 4, iclass 14, count 2 2006.173.12:47:18.43#ibcon#read 4, iclass 14, count 2 2006.173.12:47:18.43#ibcon#about to read 5, iclass 14, count 2 2006.173.12:47:18.43#ibcon#read 5, iclass 14, count 2 2006.173.12:47:18.43#ibcon#about to read 6, iclass 14, count 2 2006.173.12:47:18.43#ibcon#read 6, iclass 14, count 2 2006.173.12:47:18.43#ibcon#end of sib2, iclass 14, count 2 2006.173.12:47:18.43#ibcon#*mode == 0, iclass 14, count 2 2006.173.12:47:18.43#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.12:47:18.43#ibcon#[27=AT05-04\r\n] 2006.173.12:47:18.43#ibcon#*before write, iclass 14, count 2 2006.173.12:47:18.43#ibcon#enter sib2, iclass 14, count 2 2006.173.12:47:18.43#ibcon#flushed, iclass 14, count 2 2006.173.12:47:18.43#ibcon#about to write, iclass 14, count 2 2006.173.12:47:18.43#ibcon#wrote, iclass 14, count 2 2006.173.12:47:18.43#ibcon#about to read 3, iclass 14, count 2 2006.173.12:47:18.46#ibcon#read 3, iclass 14, count 2 2006.173.12:47:18.46#ibcon#about to read 4, iclass 14, count 2 2006.173.12:47:18.46#ibcon#read 4, iclass 14, count 2 2006.173.12:47:18.46#ibcon#about to read 5, iclass 14, count 2 2006.173.12:47:18.46#ibcon#read 5, iclass 14, count 2 2006.173.12:47:18.46#ibcon#about to read 6, iclass 14, count 2 2006.173.12:47:18.46#ibcon#read 6, iclass 14, count 2 2006.173.12:47:18.46#ibcon#end of sib2, iclass 14, count 2 2006.173.12:47:18.46#ibcon#*after write, iclass 14, count 2 2006.173.12:47:18.46#ibcon#*before return 0, iclass 14, count 2 2006.173.12:47:18.46#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.12:47:18.46#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.12:47:18.46#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.12:47:18.46#ibcon#ireg 7 cls_cnt 0 2006.173.12:47:18.46#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.12:47:18.58#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.12:47:18.58#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.12:47:18.58#ibcon#enter wrdev, iclass 14, count 0 2006.173.12:47:18.58#ibcon#first serial, iclass 14, count 0 2006.173.12:47:18.58#ibcon#enter sib2, iclass 14, count 0 2006.173.12:47:18.58#ibcon#flushed, iclass 14, count 0 2006.173.12:47:18.58#ibcon#about to write, iclass 14, count 0 2006.173.12:47:18.58#ibcon#wrote, iclass 14, count 0 2006.173.12:47:18.58#ibcon#about to read 3, iclass 14, count 0 2006.173.12:47:18.60#ibcon#read 3, iclass 14, count 0 2006.173.12:47:18.60#ibcon#about to read 4, iclass 14, count 0 2006.173.12:47:18.60#ibcon#read 4, iclass 14, count 0 2006.173.12:47:18.60#ibcon#about to read 5, iclass 14, count 0 2006.173.12:47:18.60#ibcon#read 5, iclass 14, count 0 2006.173.12:47:18.60#ibcon#about to read 6, iclass 14, count 0 2006.173.12:47:18.60#ibcon#read 6, iclass 14, count 0 2006.173.12:47:18.60#ibcon#end of sib2, iclass 14, count 0 2006.173.12:47:18.60#ibcon#*mode == 0, iclass 14, count 0 2006.173.12:47:18.60#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.12:47:18.60#ibcon#[27=USB\r\n] 2006.173.12:47:18.60#ibcon#*before write, iclass 14, count 0 2006.173.12:47:18.60#ibcon#enter sib2, iclass 14, count 0 2006.173.12:47:18.60#ibcon#flushed, iclass 14, count 0 2006.173.12:47:18.60#ibcon#about to write, iclass 14, count 0 2006.173.12:47:18.60#ibcon#wrote, iclass 14, count 0 2006.173.12:47:18.60#ibcon#about to read 3, iclass 14, count 0 2006.173.12:47:18.63#ibcon#read 3, iclass 14, count 0 2006.173.12:47:18.63#ibcon#about to read 4, iclass 14, count 0 2006.173.12:47:18.63#ibcon#read 4, iclass 14, count 0 2006.173.12:47:18.63#ibcon#about to read 5, iclass 14, count 0 2006.173.12:47:18.63#ibcon#read 5, iclass 14, count 0 2006.173.12:47:18.63#ibcon#about to read 6, iclass 14, count 0 2006.173.12:47:18.63#ibcon#read 6, iclass 14, count 0 2006.173.12:47:18.63#ibcon#end of sib2, iclass 14, count 0 2006.173.12:47:18.63#ibcon#*after write, iclass 14, count 0 2006.173.12:47:18.63#ibcon#*before return 0, iclass 14, count 0 2006.173.12:47:18.63#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.12:47:18.63#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.12:47:18.63#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.12:47:18.63#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.12:47:18.63$vck44/vblo=6,719.99 2006.173.12:47:18.63#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.12:47:18.63#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.12:47:18.63#ibcon#ireg 17 cls_cnt 0 2006.173.12:47:18.63#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.12:47:18.63#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.12:47:18.63#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.12:47:18.63#ibcon#enter wrdev, iclass 16, count 0 2006.173.12:47:18.63#ibcon#first serial, iclass 16, count 0 2006.173.12:47:18.63#ibcon#enter sib2, iclass 16, count 0 2006.173.12:47:18.63#ibcon#flushed, iclass 16, count 0 2006.173.12:47:18.63#ibcon#about to write, iclass 16, count 0 2006.173.12:47:18.63#ibcon#wrote, iclass 16, count 0 2006.173.12:47:18.63#ibcon#about to read 3, iclass 16, count 0 2006.173.12:47:18.65#ibcon#read 3, iclass 16, count 0 2006.173.12:47:18.65#ibcon#about to read 4, iclass 16, count 0 2006.173.12:47:18.65#ibcon#read 4, iclass 16, count 0 2006.173.12:47:18.65#ibcon#about to read 5, iclass 16, count 0 2006.173.12:47:18.65#ibcon#read 5, iclass 16, count 0 2006.173.12:47:18.65#ibcon#about to read 6, iclass 16, count 0 2006.173.12:47:18.65#ibcon#read 6, iclass 16, count 0 2006.173.12:47:18.65#ibcon#end of sib2, iclass 16, count 0 2006.173.12:47:18.65#ibcon#*mode == 0, iclass 16, count 0 2006.173.12:47:18.65#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.12:47:18.65#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.12:47:18.65#ibcon#*before write, iclass 16, count 0 2006.173.12:47:18.65#ibcon#enter sib2, iclass 16, count 0 2006.173.12:47:18.65#ibcon#flushed, iclass 16, count 0 2006.173.12:47:18.65#ibcon#about to write, iclass 16, count 0 2006.173.12:47:18.65#ibcon#wrote, iclass 16, count 0 2006.173.12:47:18.65#ibcon#about to read 3, iclass 16, count 0 2006.173.12:47:18.69#ibcon#read 3, iclass 16, count 0 2006.173.12:47:18.69#ibcon#about to read 4, iclass 16, count 0 2006.173.12:47:18.69#ibcon#read 4, iclass 16, count 0 2006.173.12:47:18.69#ibcon#about to read 5, iclass 16, count 0 2006.173.12:47:18.69#ibcon#read 5, iclass 16, count 0 2006.173.12:47:18.69#ibcon#about to read 6, iclass 16, count 0 2006.173.12:47:18.69#ibcon#read 6, iclass 16, count 0 2006.173.12:47:18.69#ibcon#end of sib2, iclass 16, count 0 2006.173.12:47:18.69#ibcon#*after write, iclass 16, count 0 2006.173.12:47:18.69#ibcon#*before return 0, iclass 16, count 0 2006.173.12:47:18.69#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.12:47:18.69#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.12:47:18.69#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.12:47:18.69#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.12:47:18.69$vck44/vb=6,4 2006.173.12:47:18.69#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.12:47:18.69#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.12:47:18.69#ibcon#ireg 11 cls_cnt 2 2006.173.12:47:18.69#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.12:47:18.75#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.12:47:18.75#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.12:47:18.75#ibcon#enter wrdev, iclass 18, count 2 2006.173.12:47:18.75#ibcon#first serial, iclass 18, count 2 2006.173.12:47:18.75#ibcon#enter sib2, iclass 18, count 2 2006.173.12:47:18.75#ibcon#flushed, iclass 18, count 2 2006.173.12:47:18.75#ibcon#about to write, iclass 18, count 2 2006.173.12:47:18.75#ibcon#wrote, iclass 18, count 2 2006.173.12:47:18.75#ibcon#about to read 3, iclass 18, count 2 2006.173.12:47:18.77#ibcon#read 3, iclass 18, count 2 2006.173.12:47:18.77#ibcon#about to read 4, iclass 18, count 2 2006.173.12:47:18.77#ibcon#read 4, iclass 18, count 2 2006.173.12:47:18.77#ibcon#about to read 5, iclass 18, count 2 2006.173.12:47:18.77#ibcon#read 5, iclass 18, count 2 2006.173.12:47:18.77#ibcon#about to read 6, iclass 18, count 2 2006.173.12:47:18.77#ibcon#read 6, iclass 18, count 2 2006.173.12:47:18.77#ibcon#end of sib2, iclass 18, count 2 2006.173.12:47:18.77#ibcon#*mode == 0, iclass 18, count 2 2006.173.12:47:18.77#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.12:47:18.77#ibcon#[27=AT06-04\r\n] 2006.173.12:47:18.77#ibcon#*before write, iclass 18, count 2 2006.173.12:47:18.77#ibcon#enter sib2, iclass 18, count 2 2006.173.12:47:18.77#ibcon#flushed, iclass 18, count 2 2006.173.12:47:18.77#ibcon#about to write, iclass 18, count 2 2006.173.12:47:18.77#ibcon#wrote, iclass 18, count 2 2006.173.12:47:18.77#ibcon#about to read 3, iclass 18, count 2 2006.173.12:47:18.80#ibcon#read 3, iclass 18, count 2 2006.173.12:47:18.80#ibcon#about to read 4, iclass 18, count 2 2006.173.12:47:18.80#ibcon#read 4, iclass 18, count 2 2006.173.12:47:18.80#ibcon#about to read 5, iclass 18, count 2 2006.173.12:47:18.80#ibcon#read 5, iclass 18, count 2 2006.173.12:47:18.80#ibcon#about to read 6, iclass 18, count 2 2006.173.12:47:18.80#ibcon#read 6, iclass 18, count 2 2006.173.12:47:18.80#ibcon#end of sib2, iclass 18, count 2 2006.173.12:47:18.80#ibcon#*after write, iclass 18, count 2 2006.173.12:47:18.80#ibcon#*before return 0, iclass 18, count 2 2006.173.12:47:18.80#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.12:47:18.80#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.12:47:18.80#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.12:47:18.80#ibcon#ireg 7 cls_cnt 0 2006.173.12:47:18.80#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.12:47:18.92#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.12:47:18.92#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.12:47:18.92#ibcon#enter wrdev, iclass 18, count 0 2006.173.12:47:18.92#ibcon#first serial, iclass 18, count 0 2006.173.12:47:18.92#ibcon#enter sib2, iclass 18, count 0 2006.173.12:47:18.92#ibcon#flushed, iclass 18, count 0 2006.173.12:47:18.92#ibcon#about to write, iclass 18, count 0 2006.173.12:47:18.92#ibcon#wrote, iclass 18, count 0 2006.173.12:47:18.92#ibcon#about to read 3, iclass 18, count 0 2006.173.12:47:18.94#ibcon#read 3, iclass 18, count 0 2006.173.12:47:18.94#ibcon#about to read 4, iclass 18, count 0 2006.173.12:47:18.94#ibcon#read 4, iclass 18, count 0 2006.173.12:47:18.94#ibcon#about to read 5, iclass 18, count 0 2006.173.12:47:18.94#ibcon#read 5, iclass 18, count 0 2006.173.12:47:18.94#ibcon#about to read 6, iclass 18, count 0 2006.173.12:47:18.94#ibcon#read 6, iclass 18, count 0 2006.173.12:47:18.94#ibcon#end of sib2, iclass 18, count 0 2006.173.12:47:18.94#ibcon#*mode == 0, iclass 18, count 0 2006.173.12:47:18.94#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.12:47:18.94#ibcon#[27=USB\r\n] 2006.173.12:47:18.94#ibcon#*before write, iclass 18, count 0 2006.173.12:47:18.94#ibcon#enter sib2, iclass 18, count 0 2006.173.12:47:18.94#ibcon#flushed, iclass 18, count 0 2006.173.12:47:18.94#ibcon#about to write, iclass 18, count 0 2006.173.12:47:18.94#ibcon#wrote, iclass 18, count 0 2006.173.12:47:18.94#ibcon#about to read 3, iclass 18, count 0 2006.173.12:47:18.97#ibcon#read 3, iclass 18, count 0 2006.173.12:47:18.97#ibcon#about to read 4, iclass 18, count 0 2006.173.12:47:18.97#ibcon#read 4, iclass 18, count 0 2006.173.12:47:18.97#ibcon#about to read 5, iclass 18, count 0 2006.173.12:47:18.97#ibcon#read 5, iclass 18, count 0 2006.173.12:47:18.97#ibcon#about to read 6, iclass 18, count 0 2006.173.12:47:18.97#ibcon#read 6, iclass 18, count 0 2006.173.12:47:18.97#ibcon#end of sib2, iclass 18, count 0 2006.173.12:47:18.97#ibcon#*after write, iclass 18, count 0 2006.173.12:47:18.97#ibcon#*before return 0, iclass 18, count 0 2006.173.12:47:18.97#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.12:47:18.97#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.12:47:18.97#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.12:47:18.97#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.12:47:18.97$vck44/vblo=7,734.99 2006.173.12:47:18.97#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.12:47:18.97#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.12:47:18.97#ibcon#ireg 17 cls_cnt 0 2006.173.12:47:18.97#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.12:47:18.97#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.12:47:18.97#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.12:47:18.97#ibcon#enter wrdev, iclass 20, count 0 2006.173.12:47:18.97#ibcon#first serial, iclass 20, count 0 2006.173.12:47:18.97#ibcon#enter sib2, iclass 20, count 0 2006.173.12:47:18.97#ibcon#flushed, iclass 20, count 0 2006.173.12:47:18.97#ibcon#about to write, iclass 20, count 0 2006.173.12:47:18.97#ibcon#wrote, iclass 20, count 0 2006.173.12:47:18.97#ibcon#about to read 3, iclass 20, count 0 2006.173.12:47:18.99#ibcon#read 3, iclass 20, count 0 2006.173.12:47:18.99#ibcon#about to read 4, iclass 20, count 0 2006.173.12:47:18.99#ibcon#read 4, iclass 20, count 0 2006.173.12:47:18.99#ibcon#about to read 5, iclass 20, count 0 2006.173.12:47:18.99#ibcon#read 5, iclass 20, count 0 2006.173.12:47:18.99#ibcon#about to read 6, iclass 20, count 0 2006.173.12:47:18.99#ibcon#read 6, iclass 20, count 0 2006.173.12:47:18.99#ibcon#end of sib2, iclass 20, count 0 2006.173.12:47:18.99#ibcon#*mode == 0, iclass 20, count 0 2006.173.12:47:18.99#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.12:47:18.99#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.12:47:18.99#ibcon#*before write, iclass 20, count 0 2006.173.12:47:18.99#ibcon#enter sib2, iclass 20, count 0 2006.173.12:47:18.99#ibcon#flushed, iclass 20, count 0 2006.173.12:47:18.99#ibcon#about to write, iclass 20, count 0 2006.173.12:47:18.99#ibcon#wrote, iclass 20, count 0 2006.173.12:47:18.99#ibcon#about to read 3, iclass 20, count 0 2006.173.12:47:19.03#ibcon#read 3, iclass 20, count 0 2006.173.12:47:19.03#ibcon#about to read 4, iclass 20, count 0 2006.173.12:47:19.03#ibcon#read 4, iclass 20, count 0 2006.173.12:47:19.03#ibcon#about to read 5, iclass 20, count 0 2006.173.12:47:19.03#ibcon#read 5, iclass 20, count 0 2006.173.12:47:19.03#ibcon#about to read 6, iclass 20, count 0 2006.173.12:47:19.03#ibcon#read 6, iclass 20, count 0 2006.173.12:47:19.03#ibcon#end of sib2, iclass 20, count 0 2006.173.12:47:19.03#ibcon#*after write, iclass 20, count 0 2006.173.12:47:19.03#ibcon#*before return 0, iclass 20, count 0 2006.173.12:47:19.03#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.12:47:19.03#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.12:47:19.03#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.12:47:19.03#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.12:47:19.03$vck44/vb=7,4 2006.173.12:47:19.03#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.12:47:19.03#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.12:47:19.03#ibcon#ireg 11 cls_cnt 2 2006.173.12:47:19.03#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.12:47:19.09#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.12:47:19.09#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.12:47:19.09#ibcon#enter wrdev, iclass 22, count 2 2006.173.12:47:19.09#ibcon#first serial, iclass 22, count 2 2006.173.12:47:19.09#ibcon#enter sib2, iclass 22, count 2 2006.173.12:47:19.09#ibcon#flushed, iclass 22, count 2 2006.173.12:47:19.09#ibcon#about to write, iclass 22, count 2 2006.173.12:47:19.09#ibcon#wrote, iclass 22, count 2 2006.173.12:47:19.09#ibcon#about to read 3, iclass 22, count 2 2006.173.12:47:19.11#ibcon#read 3, iclass 22, count 2 2006.173.12:47:19.11#ibcon#about to read 4, iclass 22, count 2 2006.173.12:47:19.11#ibcon#read 4, iclass 22, count 2 2006.173.12:47:19.11#ibcon#about to read 5, iclass 22, count 2 2006.173.12:47:19.11#ibcon#read 5, iclass 22, count 2 2006.173.12:47:19.11#ibcon#about to read 6, iclass 22, count 2 2006.173.12:47:19.11#ibcon#read 6, iclass 22, count 2 2006.173.12:47:19.11#ibcon#end of sib2, iclass 22, count 2 2006.173.12:47:19.11#ibcon#*mode == 0, iclass 22, count 2 2006.173.12:47:19.11#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.12:47:19.11#ibcon#[27=AT07-04\r\n] 2006.173.12:47:19.11#ibcon#*before write, iclass 22, count 2 2006.173.12:47:19.11#ibcon#enter sib2, iclass 22, count 2 2006.173.12:47:19.11#ibcon#flushed, iclass 22, count 2 2006.173.12:47:19.11#ibcon#about to write, iclass 22, count 2 2006.173.12:47:19.11#ibcon#wrote, iclass 22, count 2 2006.173.12:47:19.11#ibcon#about to read 3, iclass 22, count 2 2006.173.12:47:19.14#ibcon#read 3, iclass 22, count 2 2006.173.12:47:19.14#ibcon#about to read 4, iclass 22, count 2 2006.173.12:47:19.14#ibcon#read 4, iclass 22, count 2 2006.173.12:47:19.14#ibcon#about to read 5, iclass 22, count 2 2006.173.12:47:19.14#ibcon#read 5, iclass 22, count 2 2006.173.12:47:19.14#ibcon#about to read 6, iclass 22, count 2 2006.173.12:47:19.14#ibcon#read 6, iclass 22, count 2 2006.173.12:47:19.14#ibcon#end of sib2, iclass 22, count 2 2006.173.12:47:19.14#ibcon#*after write, iclass 22, count 2 2006.173.12:47:19.14#ibcon#*before return 0, iclass 22, count 2 2006.173.12:47:19.14#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.12:47:19.14#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.12:47:19.14#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.12:47:19.14#ibcon#ireg 7 cls_cnt 0 2006.173.12:47:19.14#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.12:47:19.26#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.12:47:19.26#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.12:47:19.26#ibcon#enter wrdev, iclass 22, count 0 2006.173.12:47:19.26#ibcon#first serial, iclass 22, count 0 2006.173.12:47:19.26#ibcon#enter sib2, iclass 22, count 0 2006.173.12:47:19.26#ibcon#flushed, iclass 22, count 0 2006.173.12:47:19.26#ibcon#about to write, iclass 22, count 0 2006.173.12:47:19.26#ibcon#wrote, iclass 22, count 0 2006.173.12:47:19.26#ibcon#about to read 3, iclass 22, count 0 2006.173.12:47:19.28#ibcon#read 3, iclass 22, count 0 2006.173.12:47:19.28#ibcon#about to read 4, iclass 22, count 0 2006.173.12:47:19.28#ibcon#read 4, iclass 22, count 0 2006.173.12:47:19.28#ibcon#about to read 5, iclass 22, count 0 2006.173.12:47:19.28#ibcon#read 5, iclass 22, count 0 2006.173.12:47:19.28#ibcon#about to read 6, iclass 22, count 0 2006.173.12:47:19.28#ibcon#read 6, iclass 22, count 0 2006.173.12:47:19.28#ibcon#end of sib2, iclass 22, count 0 2006.173.12:47:19.28#ibcon#*mode == 0, iclass 22, count 0 2006.173.12:47:19.28#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.12:47:19.28#ibcon#[27=USB\r\n] 2006.173.12:47:19.28#ibcon#*before write, iclass 22, count 0 2006.173.12:47:19.28#ibcon#enter sib2, iclass 22, count 0 2006.173.12:47:19.28#ibcon#flushed, iclass 22, count 0 2006.173.12:47:19.28#ibcon#about to write, iclass 22, count 0 2006.173.12:47:19.28#ibcon#wrote, iclass 22, count 0 2006.173.12:47:19.28#ibcon#about to read 3, iclass 22, count 0 2006.173.12:47:19.31#ibcon#read 3, iclass 22, count 0 2006.173.12:47:19.31#ibcon#about to read 4, iclass 22, count 0 2006.173.12:47:19.31#ibcon#read 4, iclass 22, count 0 2006.173.12:47:19.31#ibcon#about to read 5, iclass 22, count 0 2006.173.12:47:19.31#ibcon#read 5, iclass 22, count 0 2006.173.12:47:19.31#ibcon#about to read 6, iclass 22, count 0 2006.173.12:47:19.31#ibcon#read 6, iclass 22, count 0 2006.173.12:47:19.31#ibcon#end of sib2, iclass 22, count 0 2006.173.12:47:19.31#ibcon#*after write, iclass 22, count 0 2006.173.12:47:19.31#ibcon#*before return 0, iclass 22, count 0 2006.173.12:47:19.31#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.12:47:19.31#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.12:47:19.31#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.12:47:19.31#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.12:47:19.31$vck44/vblo=8,744.99 2006.173.12:47:19.31#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.12:47:19.31#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.12:47:19.31#ibcon#ireg 17 cls_cnt 0 2006.173.12:47:19.31#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.12:47:19.31#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.12:47:19.31#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.12:47:19.31#ibcon#enter wrdev, iclass 24, count 0 2006.173.12:47:19.31#ibcon#first serial, iclass 24, count 0 2006.173.12:47:19.31#ibcon#enter sib2, iclass 24, count 0 2006.173.12:47:19.31#ibcon#flushed, iclass 24, count 0 2006.173.12:47:19.31#ibcon#about to write, iclass 24, count 0 2006.173.12:47:19.31#ibcon#wrote, iclass 24, count 0 2006.173.12:47:19.31#ibcon#about to read 3, iclass 24, count 0 2006.173.12:47:19.33#ibcon#read 3, iclass 24, count 0 2006.173.12:47:19.33#ibcon#about to read 4, iclass 24, count 0 2006.173.12:47:19.33#ibcon#read 4, iclass 24, count 0 2006.173.12:47:19.33#ibcon#about to read 5, iclass 24, count 0 2006.173.12:47:19.33#ibcon#read 5, iclass 24, count 0 2006.173.12:47:19.33#ibcon#about to read 6, iclass 24, count 0 2006.173.12:47:19.33#ibcon#read 6, iclass 24, count 0 2006.173.12:47:19.33#ibcon#end of sib2, iclass 24, count 0 2006.173.12:47:19.33#ibcon#*mode == 0, iclass 24, count 0 2006.173.12:47:19.33#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.12:47:19.33#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.12:47:19.33#ibcon#*before write, iclass 24, count 0 2006.173.12:47:19.33#ibcon#enter sib2, iclass 24, count 0 2006.173.12:47:19.33#ibcon#flushed, iclass 24, count 0 2006.173.12:47:19.33#ibcon#about to write, iclass 24, count 0 2006.173.12:47:19.33#ibcon#wrote, iclass 24, count 0 2006.173.12:47:19.33#ibcon#about to read 3, iclass 24, count 0 2006.173.12:47:19.37#ibcon#read 3, iclass 24, count 0 2006.173.12:47:19.37#ibcon#about to read 4, iclass 24, count 0 2006.173.12:47:19.37#ibcon#read 4, iclass 24, count 0 2006.173.12:47:19.37#ibcon#about to read 5, iclass 24, count 0 2006.173.12:47:19.37#ibcon#read 5, iclass 24, count 0 2006.173.12:47:19.37#ibcon#about to read 6, iclass 24, count 0 2006.173.12:47:19.37#ibcon#read 6, iclass 24, count 0 2006.173.12:47:19.37#ibcon#end of sib2, iclass 24, count 0 2006.173.12:47:19.37#ibcon#*after write, iclass 24, count 0 2006.173.12:47:19.37#ibcon#*before return 0, iclass 24, count 0 2006.173.12:47:19.37#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.12:47:19.37#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.12:47:19.37#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.12:47:19.37#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.12:47:19.37$vck44/vb=8,4 2006.173.12:47:19.37#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.12:47:19.37#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.12:47:19.37#ibcon#ireg 11 cls_cnt 2 2006.173.12:47:19.37#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.12:47:19.43#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.12:47:19.43#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.12:47:19.43#ibcon#enter wrdev, iclass 26, count 2 2006.173.12:47:19.43#ibcon#first serial, iclass 26, count 2 2006.173.12:47:19.43#ibcon#enter sib2, iclass 26, count 2 2006.173.12:47:19.43#ibcon#flushed, iclass 26, count 2 2006.173.12:47:19.43#ibcon#about to write, iclass 26, count 2 2006.173.12:47:19.43#ibcon#wrote, iclass 26, count 2 2006.173.12:47:19.43#ibcon#about to read 3, iclass 26, count 2 2006.173.12:47:19.45#ibcon#read 3, iclass 26, count 2 2006.173.12:47:19.45#ibcon#about to read 4, iclass 26, count 2 2006.173.12:47:19.45#ibcon#read 4, iclass 26, count 2 2006.173.12:47:19.45#ibcon#about to read 5, iclass 26, count 2 2006.173.12:47:19.45#ibcon#read 5, iclass 26, count 2 2006.173.12:47:19.45#ibcon#about to read 6, iclass 26, count 2 2006.173.12:47:19.45#ibcon#read 6, iclass 26, count 2 2006.173.12:47:19.45#ibcon#end of sib2, iclass 26, count 2 2006.173.12:47:19.45#ibcon#*mode == 0, iclass 26, count 2 2006.173.12:47:19.45#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.12:47:19.45#ibcon#[27=AT08-04\r\n] 2006.173.12:47:19.45#ibcon#*before write, iclass 26, count 2 2006.173.12:47:19.45#ibcon#enter sib2, iclass 26, count 2 2006.173.12:47:19.45#ibcon#flushed, iclass 26, count 2 2006.173.12:47:19.45#ibcon#about to write, iclass 26, count 2 2006.173.12:47:19.45#ibcon#wrote, iclass 26, count 2 2006.173.12:47:19.45#ibcon#about to read 3, iclass 26, count 2 2006.173.12:47:19.48#ibcon#read 3, iclass 26, count 2 2006.173.12:47:19.48#ibcon#about to read 4, iclass 26, count 2 2006.173.12:47:19.48#ibcon#read 4, iclass 26, count 2 2006.173.12:47:19.48#ibcon#about to read 5, iclass 26, count 2 2006.173.12:47:19.48#ibcon#read 5, iclass 26, count 2 2006.173.12:47:19.48#ibcon#about to read 6, iclass 26, count 2 2006.173.12:47:19.48#ibcon#read 6, iclass 26, count 2 2006.173.12:47:19.48#ibcon#end of sib2, iclass 26, count 2 2006.173.12:47:19.48#ibcon#*after write, iclass 26, count 2 2006.173.12:47:19.48#ibcon#*before return 0, iclass 26, count 2 2006.173.12:47:19.48#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.12:47:19.48#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.12:47:19.48#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.12:47:19.48#ibcon#ireg 7 cls_cnt 0 2006.173.12:47:19.48#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.12:47:19.60#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.12:47:19.60#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.12:47:19.60#ibcon#enter wrdev, iclass 26, count 0 2006.173.12:47:19.60#ibcon#first serial, iclass 26, count 0 2006.173.12:47:19.60#ibcon#enter sib2, iclass 26, count 0 2006.173.12:47:19.60#ibcon#flushed, iclass 26, count 0 2006.173.12:47:19.60#ibcon#about to write, iclass 26, count 0 2006.173.12:47:19.60#ibcon#wrote, iclass 26, count 0 2006.173.12:47:19.60#ibcon#about to read 3, iclass 26, count 0 2006.173.12:47:19.62#ibcon#read 3, iclass 26, count 0 2006.173.12:47:19.62#ibcon#about to read 4, iclass 26, count 0 2006.173.12:47:19.62#ibcon#read 4, iclass 26, count 0 2006.173.12:47:19.62#ibcon#about to read 5, iclass 26, count 0 2006.173.12:47:19.62#ibcon#read 5, iclass 26, count 0 2006.173.12:47:19.62#ibcon#about to read 6, iclass 26, count 0 2006.173.12:47:19.62#ibcon#read 6, iclass 26, count 0 2006.173.12:47:19.62#ibcon#end of sib2, iclass 26, count 0 2006.173.12:47:19.62#ibcon#*mode == 0, iclass 26, count 0 2006.173.12:47:19.62#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.12:47:19.62#ibcon#[27=USB\r\n] 2006.173.12:47:19.62#ibcon#*before write, iclass 26, count 0 2006.173.12:47:19.62#ibcon#enter sib2, iclass 26, count 0 2006.173.12:47:19.62#ibcon#flushed, iclass 26, count 0 2006.173.12:47:19.62#ibcon#about to write, iclass 26, count 0 2006.173.12:47:19.62#ibcon#wrote, iclass 26, count 0 2006.173.12:47:19.62#ibcon#about to read 3, iclass 26, count 0 2006.173.12:47:19.65#ibcon#read 3, iclass 26, count 0 2006.173.12:47:19.65#ibcon#about to read 4, iclass 26, count 0 2006.173.12:47:19.65#ibcon#read 4, iclass 26, count 0 2006.173.12:47:19.65#ibcon#about to read 5, iclass 26, count 0 2006.173.12:47:19.65#ibcon#read 5, iclass 26, count 0 2006.173.12:47:19.65#ibcon#about to read 6, iclass 26, count 0 2006.173.12:47:19.65#ibcon#read 6, iclass 26, count 0 2006.173.12:47:19.65#ibcon#end of sib2, iclass 26, count 0 2006.173.12:47:19.65#ibcon#*after write, iclass 26, count 0 2006.173.12:47:19.65#ibcon#*before return 0, iclass 26, count 0 2006.173.12:47:19.65#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.12:47:19.65#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.12:47:19.65#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.12:47:19.65#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.12:47:19.65$vck44/vabw=wide 2006.173.12:47:19.65#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.12:47:19.65#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.12:47:19.65#ibcon#ireg 8 cls_cnt 0 2006.173.12:47:19.65#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.12:47:19.65#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.12:47:19.65#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.12:47:19.65#ibcon#enter wrdev, iclass 28, count 0 2006.173.12:47:19.65#ibcon#first serial, iclass 28, count 0 2006.173.12:47:19.65#ibcon#enter sib2, iclass 28, count 0 2006.173.12:47:19.65#ibcon#flushed, iclass 28, count 0 2006.173.12:47:19.65#ibcon#about to write, iclass 28, count 0 2006.173.12:47:19.65#ibcon#wrote, iclass 28, count 0 2006.173.12:47:19.65#ibcon#about to read 3, iclass 28, count 0 2006.173.12:47:19.67#ibcon#read 3, iclass 28, count 0 2006.173.12:47:19.67#ibcon#about to read 4, iclass 28, count 0 2006.173.12:47:19.67#ibcon#read 4, iclass 28, count 0 2006.173.12:47:19.67#ibcon#about to read 5, iclass 28, count 0 2006.173.12:47:19.67#ibcon#read 5, iclass 28, count 0 2006.173.12:47:19.67#ibcon#about to read 6, iclass 28, count 0 2006.173.12:47:19.67#ibcon#read 6, iclass 28, count 0 2006.173.12:47:19.67#ibcon#end of sib2, iclass 28, count 0 2006.173.12:47:19.67#ibcon#*mode == 0, iclass 28, count 0 2006.173.12:47:19.67#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.12:47:19.67#ibcon#[25=BW32\r\n] 2006.173.12:47:19.67#ibcon#*before write, iclass 28, count 0 2006.173.12:47:19.67#ibcon#enter sib2, iclass 28, count 0 2006.173.12:47:19.67#ibcon#flushed, iclass 28, count 0 2006.173.12:47:19.67#ibcon#about to write, iclass 28, count 0 2006.173.12:47:19.67#ibcon#wrote, iclass 28, count 0 2006.173.12:47:19.67#ibcon#about to read 3, iclass 28, count 0 2006.173.12:47:19.70#ibcon#read 3, iclass 28, count 0 2006.173.12:47:19.70#ibcon#about to read 4, iclass 28, count 0 2006.173.12:47:19.70#ibcon#read 4, iclass 28, count 0 2006.173.12:47:19.70#ibcon#about to read 5, iclass 28, count 0 2006.173.12:47:19.70#ibcon#read 5, iclass 28, count 0 2006.173.12:47:19.70#ibcon#about to read 6, iclass 28, count 0 2006.173.12:47:19.70#ibcon#read 6, iclass 28, count 0 2006.173.12:47:19.70#ibcon#end of sib2, iclass 28, count 0 2006.173.12:47:19.70#ibcon#*after write, iclass 28, count 0 2006.173.12:47:19.70#ibcon#*before return 0, iclass 28, count 0 2006.173.12:47:19.70#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.12:47:19.70#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.12:47:19.70#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.12:47:19.70#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.12:47:19.70$vck44/vbbw=wide 2006.173.12:47:19.70#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.12:47:19.70#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.12:47:19.70#ibcon#ireg 8 cls_cnt 0 2006.173.12:47:19.70#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.12:47:19.77#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.12:47:19.77#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.12:47:19.77#ibcon#enter wrdev, iclass 30, count 0 2006.173.12:47:19.77#ibcon#first serial, iclass 30, count 0 2006.173.12:47:19.77#ibcon#enter sib2, iclass 30, count 0 2006.173.12:47:19.77#ibcon#flushed, iclass 30, count 0 2006.173.12:47:19.77#ibcon#about to write, iclass 30, count 0 2006.173.12:47:19.77#ibcon#wrote, iclass 30, count 0 2006.173.12:47:19.77#ibcon#about to read 3, iclass 30, count 0 2006.173.12:47:19.79#ibcon#read 3, iclass 30, count 0 2006.173.12:47:19.79#ibcon#about to read 4, iclass 30, count 0 2006.173.12:47:19.79#ibcon#read 4, iclass 30, count 0 2006.173.12:47:19.79#ibcon#about to read 5, iclass 30, count 0 2006.173.12:47:19.79#ibcon#read 5, iclass 30, count 0 2006.173.12:47:19.79#ibcon#about to read 6, iclass 30, count 0 2006.173.12:47:19.79#ibcon#read 6, iclass 30, count 0 2006.173.12:47:19.79#ibcon#end of sib2, iclass 30, count 0 2006.173.12:47:19.79#ibcon#*mode == 0, iclass 30, count 0 2006.173.12:47:19.79#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.12:47:19.79#ibcon#[27=BW32\r\n] 2006.173.12:47:19.79#ibcon#*before write, iclass 30, count 0 2006.173.12:47:19.79#ibcon#enter sib2, iclass 30, count 0 2006.173.12:47:19.79#ibcon#flushed, iclass 30, count 0 2006.173.12:47:19.79#ibcon#about to write, iclass 30, count 0 2006.173.12:47:19.79#ibcon#wrote, iclass 30, count 0 2006.173.12:47:19.79#ibcon#about to read 3, iclass 30, count 0 2006.173.12:47:19.82#ibcon#read 3, iclass 30, count 0 2006.173.12:47:19.82#ibcon#about to read 4, iclass 30, count 0 2006.173.12:47:19.82#ibcon#read 4, iclass 30, count 0 2006.173.12:47:19.82#ibcon#about to read 5, iclass 30, count 0 2006.173.12:47:19.82#ibcon#read 5, iclass 30, count 0 2006.173.12:47:19.82#ibcon#about to read 6, iclass 30, count 0 2006.173.12:47:19.82#ibcon#read 6, iclass 30, count 0 2006.173.12:47:19.82#ibcon#end of sib2, iclass 30, count 0 2006.173.12:47:19.82#ibcon#*after write, iclass 30, count 0 2006.173.12:47:19.82#ibcon#*before return 0, iclass 30, count 0 2006.173.12:47:19.82#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.12:47:19.82#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.12:47:19.82#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.12:47:19.82#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.12:47:19.82$setupk4/ifdk4 2006.173.12:47:19.82$ifdk4/lo= 2006.173.12:47:19.82$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.12:47:19.82$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.12:47:19.82$ifdk4/patch= 2006.173.12:47:19.82$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.12:47:19.82$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.12:47:19.82$setupk4/!*+20s 2006.173.12:47:27.24#abcon#<5=/03 1.3 1.9 22.13 951004.2\r\n> 2006.173.12:47:27.26#abcon#{5=INTERFACE CLEAR} 2006.173.12:47:27.32#abcon#[5=S1D000X0/0*\r\n] 2006.173.12:47:32.13#trakl#Source acquired 2006.173.12:47:34.13#flagr#flagr/antenna,acquired 2006.173.12:47:34.33$setupk4/"tpicd 2006.173.12:47:34.33$setupk4/echo=off 2006.173.12:47:34.33$setupk4/xlog=off 2006.173.12:47:34.33:!2006.173.12:53:43 2006.173.12:53:43.02:preob 2006.173.12:53:44.14/onsource/TRACKING 2006.173.12:53:44.14:!2006.173.12:53:53 2006.173.12:53:53.01:"tape 2006.173.12:53:53.02:"st=record 2006.173.12:53:53.02:data_valid=on 2006.173.12:53:53.02:midob 2006.173.12:53:54.15/onsource/TRACKING 2006.173.12:53:54.15/wx/22.15,1004.2,95 2006.173.12:53:54.33/cable/+6.5039E-03 2006.173.12:53:55.41/va/01,07,usb,yes,40,43 2006.173.12:53:55.41/va/02,06,usb,yes,40,41 2006.173.12:53:55.42/va/03,05,usb,yes,51,53 2006.173.12:53:55.42/va/04,06,usb,yes,41,43 2006.173.12:53:55.42/va/05,04,usb,yes,33,33 2006.173.12:53:55.42/va/06,03,usb,yes,45,45 2006.173.12:53:55.42/va/07,04,usb,yes,37,38 2006.173.12:53:55.42/va/08,04,usb,yes,32,38 2006.173.12:53:55.65/valo/01,524.99,yes,locked 2006.173.12:53:55.65/valo/02,534.99,yes,locked 2006.173.12:53:55.65/valo/03,564.99,yes,locked 2006.173.12:53:55.65/valo/04,624.99,yes,locked 2006.173.12:53:55.65/valo/05,734.99,yes,locked 2006.173.12:53:55.65/valo/06,814.99,yes,locked 2006.173.12:53:55.65/valo/07,864.99,yes,locked 2006.173.12:53:55.65/valo/08,884.99,yes,locked 2006.173.12:53:56.73/vb/01,04,usb,yes,29,27 2006.173.12:53:56.73/vb/02,04,usb,yes,31,31 2006.173.12:53:56.73/vb/03,04,usb,yes,28,31 2006.173.12:53:56.74/vb/04,04,usb,yes,33,32 2006.173.12:53:56.74/vb/05,04,usb,yes,25,28 2006.173.12:53:56.74/vb/06,04,usb,yes,30,26 2006.173.12:53:56.74/vb/07,04,usb,yes,29,29 2006.173.12:53:56.74/vb/08,04,usb,yes,27,30 2006.173.12:53:56.98/vblo/01,629.99,yes,locked 2006.173.12:53:56.98/vblo/02,634.99,yes,locked 2006.173.12:53:56.98/vblo/03,649.99,yes,locked 2006.173.12:53:56.98/vblo/04,679.99,yes,locked 2006.173.12:53:56.98/vblo/05,709.99,yes,locked 2006.173.12:53:56.98/vblo/06,719.99,yes,locked 2006.173.12:53:56.98/vblo/07,734.99,yes,locked 2006.173.12:53:56.98/vblo/08,744.99,yes,locked 2006.173.12:53:57.12/vabw/8 2006.173.12:53:57.27/vbbw/8 2006.173.12:53:57.37/xfe/off,on,14.2 2006.173.12:53:57.76/ifatt/23,28,28,28 2006.173.12:53:58.07/fmout-gps/S +3.86E-07 2006.173.12:53:58.12:!2006.173.13:00:03 2006.173.13:00:03.00:data_valid=off 2006.173.13:00:03.01:"et 2006.173.13:00:03.01:!+3s 2006.173.13:00:06.02:"tape 2006.173.13:00:06.03:postob 2006.173.13:00:06.15/cable/+6.5048E-03 2006.173.13:00:06.16/wx/22.16,1004.3,96 2006.173.13:00:06.21/fmout-gps/S +3.83E-07 2006.173.13:00:06.22:scan_name=173-1305,jd0606,80 2006.173.13:00:06.22:source=1908-201,191109.65,-200655.1,2000.0,cw 2006.173.13:00:07.14#flagr#flagr/antenna,new-source 2006.173.13:00:07.14:checkk5 2006.173.13:00:07.50/chk_autoobs//k5ts1/ autoobs is running! 2006.173.13:00:07.90/chk_autoobs//k5ts2/ autoobs is running! 2006.173.13:00:08.31/chk_autoobs//k5ts3/ autoobs is running! 2006.173.13:00:08.71/chk_autoobs//k5ts4/ autoobs is running! 2006.173.13:00:09.10/chk_obsdata//k5ts1/T1731253??a.dat file size is correct (nominal:1480MB, actual:1476MB). 2006.173.13:00:09.51/chk_obsdata//k5ts2/T1731253??b.dat file size is correct (nominal:1480MB, actual:1476MB). 2006.173.13:00:09.91/chk_obsdata//k5ts3/T1731253??c.dat file size is correct (nominal:1480MB, actual:1476MB). 2006.173.13:00:10.31/chk_obsdata//k5ts4/T1731253??d.dat file size is correct (nominal:1480MB, actual:1476MB). 2006.173.13:00:11.05/k5log//k5ts1_log_newline 2006.173.13:00:11.74/k5log//k5ts2_log_newline 2006.173.13:00:12.45/k5log//k5ts3_log_newline 2006.173.13:00:13.15/k5log//k5ts4_log_newline 2006.173.13:00:13.18/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.13:00:13.18:setupk4=1 2006.173.13:00:13.18$setupk4/echo=on 2006.173.13:00:13.18$setupk4/pcalon 2006.173.13:00:13.18$pcalon/"no phase cal control is implemented here 2006.173.13:00:13.18$setupk4/"tpicd=stop 2006.173.13:00:13.18$setupk4/"rec=synch_on 2006.173.13:00:13.18$setupk4/"rec_mode=128 2006.173.13:00:13.18$setupk4/!* 2006.173.13:00:13.18$setupk4/recpk4 2006.173.13:00:13.18$recpk4/recpatch= 2006.173.13:00:13.18$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.13:00:13.18$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.13:00:13.18$setupk4/vck44 2006.173.13:00:13.18$vck44/valo=1,524.99 2006.173.13:00:13.18#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.13:00:13.18#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.13:00:13.18#ibcon#ireg 17 cls_cnt 0 2006.173.13:00:13.18#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.13:00:13.18#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.13:00:13.18#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.13:00:13.18#ibcon#enter wrdev, iclass 37, count 0 2006.173.13:00:13.18#ibcon#first serial, iclass 37, count 0 2006.173.13:00:13.18#ibcon#enter sib2, iclass 37, count 0 2006.173.13:00:13.18#ibcon#flushed, iclass 37, count 0 2006.173.13:00:13.18#ibcon#about to write, iclass 37, count 0 2006.173.13:00:13.18#ibcon#wrote, iclass 37, count 0 2006.173.13:00:13.18#ibcon#about to read 3, iclass 37, count 0 2006.173.13:00:13.19#ibcon#read 3, iclass 37, count 0 2006.173.13:00:13.19#ibcon#about to read 4, iclass 37, count 0 2006.173.13:00:13.19#ibcon#read 4, iclass 37, count 0 2006.173.13:00:13.19#ibcon#about to read 5, iclass 37, count 0 2006.173.13:00:13.19#ibcon#read 5, iclass 37, count 0 2006.173.13:00:13.19#ibcon#about to read 6, iclass 37, count 0 2006.173.13:00:13.19#ibcon#read 6, iclass 37, count 0 2006.173.13:00:13.19#ibcon#end of sib2, iclass 37, count 0 2006.173.13:00:13.19#ibcon#*mode == 0, iclass 37, count 0 2006.173.13:00:13.19#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.13:00:13.19#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.13:00:13.19#ibcon#*before write, iclass 37, count 0 2006.173.13:00:13.19#ibcon#enter sib2, iclass 37, count 0 2006.173.13:00:13.19#ibcon#flushed, iclass 37, count 0 2006.173.13:00:13.19#ibcon#about to write, iclass 37, count 0 2006.173.13:00:13.19#ibcon#wrote, iclass 37, count 0 2006.173.13:00:13.19#ibcon#about to read 3, iclass 37, count 0 2006.173.13:00:13.24#ibcon#read 3, iclass 37, count 0 2006.173.13:00:13.24#ibcon#about to read 4, iclass 37, count 0 2006.173.13:00:13.24#ibcon#read 4, iclass 37, count 0 2006.173.13:00:13.24#ibcon#about to read 5, iclass 37, count 0 2006.173.13:00:13.24#ibcon#read 5, iclass 37, count 0 2006.173.13:00:13.24#ibcon#about to read 6, iclass 37, count 0 2006.173.13:00:13.24#ibcon#read 6, iclass 37, count 0 2006.173.13:00:13.24#ibcon#end of sib2, iclass 37, count 0 2006.173.13:00:13.24#ibcon#*after write, iclass 37, count 0 2006.173.13:00:13.24#ibcon#*before return 0, iclass 37, count 0 2006.173.13:00:13.24#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.13:00:13.24#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.13:00:13.24#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.13:00:13.24#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.13:00:13.24$vck44/va=1,7 2006.173.13:00:13.24#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.13:00:13.24#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.13:00:13.24#ibcon#ireg 11 cls_cnt 2 2006.173.13:00:13.24#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.13:00:13.24#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.13:00:13.24#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.13:00:13.24#ibcon#enter wrdev, iclass 39, count 2 2006.173.13:00:13.24#ibcon#first serial, iclass 39, count 2 2006.173.13:00:13.24#ibcon#enter sib2, iclass 39, count 2 2006.173.13:00:13.24#ibcon#flushed, iclass 39, count 2 2006.173.13:00:13.24#ibcon#about to write, iclass 39, count 2 2006.173.13:00:13.24#ibcon#wrote, iclass 39, count 2 2006.173.13:00:13.24#ibcon#about to read 3, iclass 39, count 2 2006.173.13:00:13.26#ibcon#read 3, iclass 39, count 2 2006.173.13:00:13.26#ibcon#about to read 4, iclass 39, count 2 2006.173.13:00:13.26#ibcon#read 4, iclass 39, count 2 2006.173.13:00:13.26#ibcon#about to read 5, iclass 39, count 2 2006.173.13:00:13.26#ibcon#read 5, iclass 39, count 2 2006.173.13:00:13.26#ibcon#about to read 6, iclass 39, count 2 2006.173.13:00:13.26#ibcon#read 6, iclass 39, count 2 2006.173.13:00:13.26#ibcon#end of sib2, iclass 39, count 2 2006.173.13:00:13.26#ibcon#*mode == 0, iclass 39, count 2 2006.173.13:00:13.26#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.13:00:13.26#ibcon#[25=AT01-07\r\n] 2006.173.13:00:13.26#ibcon#*before write, iclass 39, count 2 2006.173.13:00:13.26#ibcon#enter sib2, iclass 39, count 2 2006.173.13:00:13.26#ibcon#flushed, iclass 39, count 2 2006.173.13:00:13.26#ibcon#about to write, iclass 39, count 2 2006.173.13:00:13.26#ibcon#wrote, iclass 39, count 2 2006.173.13:00:13.26#ibcon#about to read 3, iclass 39, count 2 2006.173.13:00:13.29#ibcon#read 3, iclass 39, count 2 2006.173.13:00:13.29#ibcon#about to read 4, iclass 39, count 2 2006.173.13:00:13.29#ibcon#read 4, iclass 39, count 2 2006.173.13:00:13.29#ibcon#about to read 5, iclass 39, count 2 2006.173.13:00:13.29#ibcon#read 5, iclass 39, count 2 2006.173.13:00:13.29#ibcon#about to read 6, iclass 39, count 2 2006.173.13:00:13.29#ibcon#read 6, iclass 39, count 2 2006.173.13:00:13.29#ibcon#end of sib2, iclass 39, count 2 2006.173.13:00:13.29#ibcon#*after write, iclass 39, count 2 2006.173.13:00:13.29#ibcon#*before return 0, iclass 39, count 2 2006.173.13:00:13.29#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.13:00:13.29#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.13:00:13.29#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.13:00:13.29#ibcon#ireg 7 cls_cnt 0 2006.173.13:00:13.29#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.13:00:13.41#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.13:00:13.41#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.13:00:13.41#ibcon#enter wrdev, iclass 39, count 0 2006.173.13:00:13.41#ibcon#first serial, iclass 39, count 0 2006.173.13:00:13.41#ibcon#enter sib2, iclass 39, count 0 2006.173.13:00:13.41#ibcon#flushed, iclass 39, count 0 2006.173.13:00:13.41#ibcon#about to write, iclass 39, count 0 2006.173.13:00:13.41#ibcon#wrote, iclass 39, count 0 2006.173.13:00:13.41#ibcon#about to read 3, iclass 39, count 0 2006.173.13:00:13.43#ibcon#read 3, iclass 39, count 0 2006.173.13:00:13.43#ibcon#about to read 4, iclass 39, count 0 2006.173.13:00:13.43#ibcon#read 4, iclass 39, count 0 2006.173.13:00:13.43#ibcon#about to read 5, iclass 39, count 0 2006.173.13:00:13.43#ibcon#read 5, iclass 39, count 0 2006.173.13:00:13.43#ibcon#about to read 6, iclass 39, count 0 2006.173.13:00:13.43#ibcon#read 6, iclass 39, count 0 2006.173.13:00:13.43#ibcon#end of sib2, iclass 39, count 0 2006.173.13:00:13.43#ibcon#*mode == 0, iclass 39, count 0 2006.173.13:00:13.43#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.13:00:13.43#ibcon#[25=USB\r\n] 2006.173.13:00:13.43#ibcon#*before write, iclass 39, count 0 2006.173.13:00:13.43#ibcon#enter sib2, iclass 39, count 0 2006.173.13:00:13.43#ibcon#flushed, iclass 39, count 0 2006.173.13:00:13.43#ibcon#about to write, iclass 39, count 0 2006.173.13:00:13.43#ibcon#wrote, iclass 39, count 0 2006.173.13:00:13.43#ibcon#about to read 3, iclass 39, count 0 2006.173.13:00:13.46#ibcon#read 3, iclass 39, count 0 2006.173.13:00:13.46#ibcon#about to read 4, iclass 39, count 0 2006.173.13:00:13.46#ibcon#read 4, iclass 39, count 0 2006.173.13:00:13.46#ibcon#about to read 5, iclass 39, count 0 2006.173.13:00:13.46#ibcon#read 5, iclass 39, count 0 2006.173.13:00:13.46#ibcon#about to read 6, iclass 39, count 0 2006.173.13:00:13.46#ibcon#read 6, iclass 39, count 0 2006.173.13:00:13.46#ibcon#end of sib2, iclass 39, count 0 2006.173.13:00:13.46#ibcon#*after write, iclass 39, count 0 2006.173.13:00:13.46#ibcon#*before return 0, iclass 39, count 0 2006.173.13:00:13.46#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.13:00:13.46#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.13:00:13.46#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.13:00:13.46#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.13:00:13.46$vck44/valo=2,534.99 2006.173.13:00:13.46#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.13:00:13.46#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.13:00:13.46#ibcon#ireg 17 cls_cnt 0 2006.173.13:00:13.46#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.13:00:13.46#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.13:00:13.46#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.13:00:13.46#ibcon#enter wrdev, iclass 3, count 0 2006.173.13:00:13.46#ibcon#first serial, iclass 3, count 0 2006.173.13:00:13.46#ibcon#enter sib2, iclass 3, count 0 2006.173.13:00:13.46#ibcon#flushed, iclass 3, count 0 2006.173.13:00:13.46#ibcon#about to write, iclass 3, count 0 2006.173.13:00:13.46#ibcon#wrote, iclass 3, count 0 2006.173.13:00:13.46#ibcon#about to read 3, iclass 3, count 0 2006.173.13:00:13.48#ibcon#read 3, iclass 3, count 0 2006.173.13:00:13.48#ibcon#about to read 4, iclass 3, count 0 2006.173.13:00:13.48#ibcon#read 4, iclass 3, count 0 2006.173.13:00:13.48#ibcon#about to read 5, iclass 3, count 0 2006.173.13:00:13.48#ibcon#read 5, iclass 3, count 0 2006.173.13:00:13.48#ibcon#about to read 6, iclass 3, count 0 2006.173.13:00:13.48#ibcon#read 6, iclass 3, count 0 2006.173.13:00:13.48#ibcon#end of sib2, iclass 3, count 0 2006.173.13:00:13.48#ibcon#*mode == 0, iclass 3, count 0 2006.173.13:00:13.48#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.13:00:13.48#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.13:00:13.48#ibcon#*before write, iclass 3, count 0 2006.173.13:00:13.48#ibcon#enter sib2, iclass 3, count 0 2006.173.13:00:13.48#ibcon#flushed, iclass 3, count 0 2006.173.13:00:13.48#ibcon#about to write, iclass 3, count 0 2006.173.13:00:13.48#ibcon#wrote, iclass 3, count 0 2006.173.13:00:13.48#ibcon#about to read 3, iclass 3, count 0 2006.173.13:00:13.52#ibcon#read 3, iclass 3, count 0 2006.173.13:00:13.52#ibcon#about to read 4, iclass 3, count 0 2006.173.13:00:13.52#ibcon#read 4, iclass 3, count 0 2006.173.13:00:13.52#ibcon#about to read 5, iclass 3, count 0 2006.173.13:00:13.52#ibcon#read 5, iclass 3, count 0 2006.173.13:00:13.52#ibcon#about to read 6, iclass 3, count 0 2006.173.13:00:13.52#ibcon#read 6, iclass 3, count 0 2006.173.13:00:13.52#ibcon#end of sib2, iclass 3, count 0 2006.173.13:00:13.52#ibcon#*after write, iclass 3, count 0 2006.173.13:00:13.52#ibcon#*before return 0, iclass 3, count 0 2006.173.13:00:13.52#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.13:00:13.52#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.13:00:13.52#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.13:00:13.52#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.13:00:13.52$vck44/va=2,6 2006.173.13:00:13.52#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.13:00:13.52#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.13:00:13.52#ibcon#ireg 11 cls_cnt 2 2006.173.13:00:13.52#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.13:00:13.58#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.13:00:13.58#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.13:00:13.58#ibcon#enter wrdev, iclass 5, count 2 2006.173.13:00:13.58#ibcon#first serial, iclass 5, count 2 2006.173.13:00:13.58#ibcon#enter sib2, iclass 5, count 2 2006.173.13:00:13.58#ibcon#flushed, iclass 5, count 2 2006.173.13:00:13.58#ibcon#about to write, iclass 5, count 2 2006.173.13:00:13.58#ibcon#wrote, iclass 5, count 2 2006.173.13:00:13.58#ibcon#about to read 3, iclass 5, count 2 2006.173.13:00:13.60#ibcon#read 3, iclass 5, count 2 2006.173.13:00:13.60#ibcon#about to read 4, iclass 5, count 2 2006.173.13:00:13.60#ibcon#read 4, iclass 5, count 2 2006.173.13:00:13.60#ibcon#about to read 5, iclass 5, count 2 2006.173.13:00:13.60#ibcon#read 5, iclass 5, count 2 2006.173.13:00:13.60#ibcon#about to read 6, iclass 5, count 2 2006.173.13:00:13.60#ibcon#read 6, iclass 5, count 2 2006.173.13:00:13.60#ibcon#end of sib2, iclass 5, count 2 2006.173.13:00:13.60#ibcon#*mode == 0, iclass 5, count 2 2006.173.13:00:13.60#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.13:00:13.60#ibcon#[25=AT02-06\r\n] 2006.173.13:00:13.60#ibcon#*before write, iclass 5, count 2 2006.173.13:00:13.60#ibcon#enter sib2, iclass 5, count 2 2006.173.13:00:13.60#ibcon#flushed, iclass 5, count 2 2006.173.13:00:13.60#ibcon#about to write, iclass 5, count 2 2006.173.13:00:13.60#ibcon#wrote, iclass 5, count 2 2006.173.13:00:13.60#ibcon#about to read 3, iclass 5, count 2 2006.173.13:00:13.63#ibcon#read 3, iclass 5, count 2 2006.173.13:00:13.63#ibcon#about to read 4, iclass 5, count 2 2006.173.13:00:13.63#ibcon#read 4, iclass 5, count 2 2006.173.13:00:13.63#ibcon#about to read 5, iclass 5, count 2 2006.173.13:00:13.63#ibcon#read 5, iclass 5, count 2 2006.173.13:00:13.63#ibcon#about to read 6, iclass 5, count 2 2006.173.13:00:13.63#ibcon#read 6, iclass 5, count 2 2006.173.13:00:13.63#ibcon#end of sib2, iclass 5, count 2 2006.173.13:00:13.63#ibcon#*after write, iclass 5, count 2 2006.173.13:00:13.63#ibcon#*before return 0, iclass 5, count 2 2006.173.13:00:13.63#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.13:00:13.63#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.13:00:13.63#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.13:00:13.63#ibcon#ireg 7 cls_cnt 0 2006.173.13:00:13.63#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.13:00:13.75#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.13:00:13.75#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.13:00:13.75#ibcon#enter wrdev, iclass 5, count 0 2006.173.13:00:13.75#ibcon#first serial, iclass 5, count 0 2006.173.13:00:13.75#ibcon#enter sib2, iclass 5, count 0 2006.173.13:00:13.75#ibcon#flushed, iclass 5, count 0 2006.173.13:00:13.75#ibcon#about to write, iclass 5, count 0 2006.173.13:00:13.75#ibcon#wrote, iclass 5, count 0 2006.173.13:00:13.75#ibcon#about to read 3, iclass 5, count 0 2006.173.13:00:13.77#ibcon#read 3, iclass 5, count 0 2006.173.13:00:13.77#ibcon#about to read 4, iclass 5, count 0 2006.173.13:00:13.77#ibcon#read 4, iclass 5, count 0 2006.173.13:00:13.77#ibcon#about to read 5, iclass 5, count 0 2006.173.13:00:13.77#ibcon#read 5, iclass 5, count 0 2006.173.13:00:13.77#ibcon#about to read 6, iclass 5, count 0 2006.173.13:00:13.77#ibcon#read 6, iclass 5, count 0 2006.173.13:00:13.77#ibcon#end of sib2, iclass 5, count 0 2006.173.13:00:13.77#ibcon#*mode == 0, iclass 5, count 0 2006.173.13:00:13.77#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.13:00:13.77#ibcon#[25=USB\r\n] 2006.173.13:00:13.77#ibcon#*before write, iclass 5, count 0 2006.173.13:00:13.77#ibcon#enter sib2, iclass 5, count 0 2006.173.13:00:13.77#ibcon#flushed, iclass 5, count 0 2006.173.13:00:13.77#ibcon#about to write, iclass 5, count 0 2006.173.13:00:13.77#ibcon#wrote, iclass 5, count 0 2006.173.13:00:13.77#ibcon#about to read 3, iclass 5, count 0 2006.173.13:00:13.80#ibcon#read 3, iclass 5, count 0 2006.173.13:00:13.80#ibcon#about to read 4, iclass 5, count 0 2006.173.13:00:13.80#ibcon#read 4, iclass 5, count 0 2006.173.13:00:13.80#ibcon#about to read 5, iclass 5, count 0 2006.173.13:00:13.80#ibcon#read 5, iclass 5, count 0 2006.173.13:00:13.80#ibcon#about to read 6, iclass 5, count 0 2006.173.13:00:13.80#ibcon#read 6, iclass 5, count 0 2006.173.13:00:13.80#ibcon#end of sib2, iclass 5, count 0 2006.173.13:00:13.80#ibcon#*after write, iclass 5, count 0 2006.173.13:00:13.80#ibcon#*before return 0, iclass 5, count 0 2006.173.13:00:13.80#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.13:00:13.80#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.13:00:13.80#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.13:00:13.80#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.13:00:13.80$vck44/valo=3,564.99 2006.173.13:00:13.80#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.13:00:13.80#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.13:00:13.80#ibcon#ireg 17 cls_cnt 0 2006.173.13:00:13.80#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.13:00:13.80#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.13:00:13.80#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.13:00:13.80#ibcon#enter wrdev, iclass 7, count 0 2006.173.13:00:13.80#ibcon#first serial, iclass 7, count 0 2006.173.13:00:13.80#ibcon#enter sib2, iclass 7, count 0 2006.173.13:00:13.80#ibcon#flushed, iclass 7, count 0 2006.173.13:00:13.80#ibcon#about to write, iclass 7, count 0 2006.173.13:00:13.80#ibcon#wrote, iclass 7, count 0 2006.173.13:00:13.80#ibcon#about to read 3, iclass 7, count 0 2006.173.13:00:13.82#ibcon#read 3, iclass 7, count 0 2006.173.13:00:13.82#ibcon#about to read 4, iclass 7, count 0 2006.173.13:00:13.82#ibcon#read 4, iclass 7, count 0 2006.173.13:00:13.82#ibcon#about to read 5, iclass 7, count 0 2006.173.13:00:13.82#ibcon#read 5, iclass 7, count 0 2006.173.13:00:13.82#ibcon#about to read 6, iclass 7, count 0 2006.173.13:00:13.82#ibcon#read 6, iclass 7, count 0 2006.173.13:00:13.82#ibcon#end of sib2, iclass 7, count 0 2006.173.13:00:13.82#ibcon#*mode == 0, iclass 7, count 0 2006.173.13:00:13.82#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.13:00:13.82#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.13:00:13.82#ibcon#*before write, iclass 7, count 0 2006.173.13:00:13.82#ibcon#enter sib2, iclass 7, count 0 2006.173.13:00:13.82#ibcon#flushed, iclass 7, count 0 2006.173.13:00:13.82#ibcon#about to write, iclass 7, count 0 2006.173.13:00:13.82#ibcon#wrote, iclass 7, count 0 2006.173.13:00:13.82#ibcon#about to read 3, iclass 7, count 0 2006.173.13:00:13.86#ibcon#read 3, iclass 7, count 0 2006.173.13:00:13.86#ibcon#about to read 4, iclass 7, count 0 2006.173.13:00:13.86#ibcon#read 4, iclass 7, count 0 2006.173.13:00:13.86#ibcon#about to read 5, iclass 7, count 0 2006.173.13:00:13.86#ibcon#read 5, iclass 7, count 0 2006.173.13:00:13.86#ibcon#about to read 6, iclass 7, count 0 2006.173.13:00:13.86#ibcon#read 6, iclass 7, count 0 2006.173.13:00:13.86#ibcon#end of sib2, iclass 7, count 0 2006.173.13:00:13.86#ibcon#*after write, iclass 7, count 0 2006.173.13:00:13.86#ibcon#*before return 0, iclass 7, count 0 2006.173.13:00:13.86#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.13:00:13.86#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.13:00:13.86#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.13:00:13.86#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.13:00:13.86$vck44/va=3,5 2006.173.13:00:13.86#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.13:00:13.86#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.13:00:13.86#ibcon#ireg 11 cls_cnt 2 2006.173.13:00:13.86#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.13:00:13.92#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.13:00:13.92#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.13:00:13.92#ibcon#enter wrdev, iclass 11, count 2 2006.173.13:00:13.92#ibcon#first serial, iclass 11, count 2 2006.173.13:00:13.92#ibcon#enter sib2, iclass 11, count 2 2006.173.13:00:13.92#ibcon#flushed, iclass 11, count 2 2006.173.13:00:13.92#ibcon#about to write, iclass 11, count 2 2006.173.13:00:13.92#ibcon#wrote, iclass 11, count 2 2006.173.13:00:13.92#ibcon#about to read 3, iclass 11, count 2 2006.173.13:00:13.94#ibcon#read 3, iclass 11, count 2 2006.173.13:00:13.94#ibcon#about to read 4, iclass 11, count 2 2006.173.13:00:13.94#ibcon#read 4, iclass 11, count 2 2006.173.13:00:13.94#ibcon#about to read 5, iclass 11, count 2 2006.173.13:00:13.94#ibcon#read 5, iclass 11, count 2 2006.173.13:00:13.94#ibcon#about to read 6, iclass 11, count 2 2006.173.13:00:13.94#ibcon#read 6, iclass 11, count 2 2006.173.13:00:13.94#ibcon#end of sib2, iclass 11, count 2 2006.173.13:00:13.94#ibcon#*mode == 0, iclass 11, count 2 2006.173.13:00:13.94#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.13:00:13.94#ibcon#[25=AT03-05\r\n] 2006.173.13:00:13.94#ibcon#*before write, iclass 11, count 2 2006.173.13:00:13.94#ibcon#enter sib2, iclass 11, count 2 2006.173.13:00:13.94#ibcon#flushed, iclass 11, count 2 2006.173.13:00:13.94#ibcon#about to write, iclass 11, count 2 2006.173.13:00:13.94#ibcon#wrote, iclass 11, count 2 2006.173.13:00:13.94#ibcon#about to read 3, iclass 11, count 2 2006.173.13:00:13.97#ibcon#read 3, iclass 11, count 2 2006.173.13:00:13.97#ibcon#about to read 4, iclass 11, count 2 2006.173.13:00:13.97#ibcon#read 4, iclass 11, count 2 2006.173.13:00:13.97#ibcon#about to read 5, iclass 11, count 2 2006.173.13:00:13.97#ibcon#read 5, iclass 11, count 2 2006.173.13:00:13.97#ibcon#about to read 6, iclass 11, count 2 2006.173.13:00:13.97#ibcon#read 6, iclass 11, count 2 2006.173.13:00:13.97#ibcon#end of sib2, iclass 11, count 2 2006.173.13:00:13.97#ibcon#*after write, iclass 11, count 2 2006.173.13:00:13.97#ibcon#*before return 0, iclass 11, count 2 2006.173.13:00:13.97#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.13:00:13.97#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.13:00:13.97#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.13:00:13.97#ibcon#ireg 7 cls_cnt 0 2006.173.13:00:13.97#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.13:00:14.09#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.13:00:14.09#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.13:00:14.09#ibcon#enter wrdev, iclass 11, count 0 2006.173.13:00:14.09#ibcon#first serial, iclass 11, count 0 2006.173.13:00:14.09#ibcon#enter sib2, iclass 11, count 0 2006.173.13:00:14.09#ibcon#flushed, iclass 11, count 0 2006.173.13:00:14.09#ibcon#about to write, iclass 11, count 0 2006.173.13:00:14.09#ibcon#wrote, iclass 11, count 0 2006.173.13:00:14.09#ibcon#about to read 3, iclass 11, count 0 2006.173.13:00:14.11#ibcon#read 3, iclass 11, count 0 2006.173.13:00:14.11#ibcon#about to read 4, iclass 11, count 0 2006.173.13:00:14.11#ibcon#read 4, iclass 11, count 0 2006.173.13:00:14.11#ibcon#about to read 5, iclass 11, count 0 2006.173.13:00:14.11#ibcon#read 5, iclass 11, count 0 2006.173.13:00:14.11#ibcon#about to read 6, iclass 11, count 0 2006.173.13:00:14.11#ibcon#read 6, iclass 11, count 0 2006.173.13:00:14.11#ibcon#end of sib2, iclass 11, count 0 2006.173.13:00:14.11#ibcon#*mode == 0, iclass 11, count 0 2006.173.13:00:14.11#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.13:00:14.11#ibcon#[25=USB\r\n] 2006.173.13:00:14.11#ibcon#*before write, iclass 11, count 0 2006.173.13:00:14.11#ibcon#enter sib2, iclass 11, count 0 2006.173.13:00:14.11#ibcon#flushed, iclass 11, count 0 2006.173.13:00:14.11#ibcon#about to write, iclass 11, count 0 2006.173.13:00:14.11#ibcon#wrote, iclass 11, count 0 2006.173.13:00:14.11#ibcon#about to read 3, iclass 11, count 0 2006.173.13:00:14.14#ibcon#read 3, iclass 11, count 0 2006.173.13:00:14.14#ibcon#about to read 4, iclass 11, count 0 2006.173.13:00:14.14#ibcon#read 4, iclass 11, count 0 2006.173.13:00:14.14#ibcon#about to read 5, iclass 11, count 0 2006.173.13:00:14.14#ibcon#read 5, iclass 11, count 0 2006.173.13:00:14.14#ibcon#about to read 6, iclass 11, count 0 2006.173.13:00:14.14#ibcon#read 6, iclass 11, count 0 2006.173.13:00:14.14#ibcon#end of sib2, iclass 11, count 0 2006.173.13:00:14.14#ibcon#*after write, iclass 11, count 0 2006.173.13:00:14.14#ibcon#*before return 0, iclass 11, count 0 2006.173.13:00:14.14#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.13:00:14.14#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.13:00:14.14#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.13:00:14.14#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.13:00:14.14$vck44/valo=4,624.99 2006.173.13:00:14.14#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.13:00:14.14#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.13:00:14.14#ibcon#ireg 17 cls_cnt 0 2006.173.13:00:14.14#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.13:00:14.14#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.13:00:14.14#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.13:00:14.14#ibcon#enter wrdev, iclass 13, count 0 2006.173.13:00:14.14#ibcon#first serial, iclass 13, count 0 2006.173.13:00:14.14#ibcon#enter sib2, iclass 13, count 0 2006.173.13:00:14.14#ibcon#flushed, iclass 13, count 0 2006.173.13:00:14.14#ibcon#about to write, iclass 13, count 0 2006.173.13:00:14.14#ibcon#wrote, iclass 13, count 0 2006.173.13:00:14.14#ibcon#about to read 3, iclass 13, count 0 2006.173.13:00:14.16#ibcon#read 3, iclass 13, count 0 2006.173.13:00:14.16#ibcon#about to read 4, iclass 13, count 0 2006.173.13:00:14.16#ibcon#read 4, iclass 13, count 0 2006.173.13:00:14.16#ibcon#about to read 5, iclass 13, count 0 2006.173.13:00:14.16#ibcon#read 5, iclass 13, count 0 2006.173.13:00:14.16#ibcon#about to read 6, iclass 13, count 0 2006.173.13:00:14.16#ibcon#read 6, iclass 13, count 0 2006.173.13:00:14.16#ibcon#end of sib2, iclass 13, count 0 2006.173.13:00:14.16#ibcon#*mode == 0, iclass 13, count 0 2006.173.13:00:14.16#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.13:00:14.16#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.13:00:14.16#ibcon#*before write, iclass 13, count 0 2006.173.13:00:14.16#ibcon#enter sib2, iclass 13, count 0 2006.173.13:00:14.16#ibcon#flushed, iclass 13, count 0 2006.173.13:00:14.16#ibcon#about to write, iclass 13, count 0 2006.173.13:00:14.16#ibcon#wrote, iclass 13, count 0 2006.173.13:00:14.16#ibcon#about to read 3, iclass 13, count 0 2006.173.13:00:14.20#ibcon#read 3, iclass 13, count 0 2006.173.13:00:14.20#ibcon#about to read 4, iclass 13, count 0 2006.173.13:00:14.20#ibcon#read 4, iclass 13, count 0 2006.173.13:00:14.20#ibcon#about to read 5, iclass 13, count 0 2006.173.13:00:14.20#ibcon#read 5, iclass 13, count 0 2006.173.13:00:14.20#ibcon#about to read 6, iclass 13, count 0 2006.173.13:00:14.20#ibcon#read 6, iclass 13, count 0 2006.173.13:00:14.20#ibcon#end of sib2, iclass 13, count 0 2006.173.13:00:14.20#ibcon#*after write, iclass 13, count 0 2006.173.13:00:14.20#ibcon#*before return 0, iclass 13, count 0 2006.173.13:00:14.20#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.13:00:14.20#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.13:00:14.20#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.13:00:14.20#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.13:00:14.20$vck44/va=4,6 2006.173.13:00:14.20#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.13:00:14.20#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.13:00:14.20#ibcon#ireg 11 cls_cnt 2 2006.173.13:00:14.20#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.13:00:14.26#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.13:00:14.26#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.13:00:14.26#ibcon#enter wrdev, iclass 15, count 2 2006.173.13:00:14.26#ibcon#first serial, iclass 15, count 2 2006.173.13:00:14.26#ibcon#enter sib2, iclass 15, count 2 2006.173.13:00:14.26#ibcon#flushed, iclass 15, count 2 2006.173.13:00:14.26#ibcon#about to write, iclass 15, count 2 2006.173.13:00:14.26#ibcon#wrote, iclass 15, count 2 2006.173.13:00:14.26#ibcon#about to read 3, iclass 15, count 2 2006.173.13:00:14.28#ibcon#read 3, iclass 15, count 2 2006.173.13:00:14.28#ibcon#about to read 4, iclass 15, count 2 2006.173.13:00:14.28#ibcon#read 4, iclass 15, count 2 2006.173.13:00:14.28#ibcon#about to read 5, iclass 15, count 2 2006.173.13:00:14.28#ibcon#read 5, iclass 15, count 2 2006.173.13:00:14.28#ibcon#about to read 6, iclass 15, count 2 2006.173.13:00:14.28#ibcon#read 6, iclass 15, count 2 2006.173.13:00:14.28#ibcon#end of sib2, iclass 15, count 2 2006.173.13:00:14.28#ibcon#*mode == 0, iclass 15, count 2 2006.173.13:00:14.28#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.13:00:14.28#ibcon#[25=AT04-06\r\n] 2006.173.13:00:14.28#ibcon#*before write, iclass 15, count 2 2006.173.13:00:14.28#ibcon#enter sib2, iclass 15, count 2 2006.173.13:00:14.28#ibcon#flushed, iclass 15, count 2 2006.173.13:00:14.28#ibcon#about to write, iclass 15, count 2 2006.173.13:00:14.28#ibcon#wrote, iclass 15, count 2 2006.173.13:00:14.28#ibcon#about to read 3, iclass 15, count 2 2006.173.13:00:14.31#ibcon#read 3, iclass 15, count 2 2006.173.13:00:14.31#ibcon#about to read 4, iclass 15, count 2 2006.173.13:00:14.31#ibcon#read 4, iclass 15, count 2 2006.173.13:00:14.31#ibcon#about to read 5, iclass 15, count 2 2006.173.13:00:14.31#ibcon#read 5, iclass 15, count 2 2006.173.13:00:14.31#ibcon#about to read 6, iclass 15, count 2 2006.173.13:00:14.31#ibcon#read 6, iclass 15, count 2 2006.173.13:00:14.31#ibcon#end of sib2, iclass 15, count 2 2006.173.13:00:14.31#ibcon#*after write, iclass 15, count 2 2006.173.13:00:14.31#ibcon#*before return 0, iclass 15, count 2 2006.173.13:00:14.31#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.13:00:14.31#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.13:00:14.31#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.13:00:14.31#ibcon#ireg 7 cls_cnt 0 2006.173.13:00:14.31#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.13:00:14.43#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.13:00:14.43#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.13:00:14.43#ibcon#enter wrdev, iclass 15, count 0 2006.173.13:00:14.43#ibcon#first serial, iclass 15, count 0 2006.173.13:00:14.43#ibcon#enter sib2, iclass 15, count 0 2006.173.13:00:14.43#ibcon#flushed, iclass 15, count 0 2006.173.13:00:14.43#ibcon#about to write, iclass 15, count 0 2006.173.13:00:14.43#ibcon#wrote, iclass 15, count 0 2006.173.13:00:14.43#ibcon#about to read 3, iclass 15, count 0 2006.173.13:00:14.45#ibcon#read 3, iclass 15, count 0 2006.173.13:00:14.45#ibcon#about to read 4, iclass 15, count 0 2006.173.13:00:14.45#ibcon#read 4, iclass 15, count 0 2006.173.13:00:14.45#ibcon#about to read 5, iclass 15, count 0 2006.173.13:00:14.45#ibcon#read 5, iclass 15, count 0 2006.173.13:00:14.45#ibcon#about to read 6, iclass 15, count 0 2006.173.13:00:14.45#ibcon#read 6, iclass 15, count 0 2006.173.13:00:14.45#ibcon#end of sib2, iclass 15, count 0 2006.173.13:00:14.45#ibcon#*mode == 0, iclass 15, count 0 2006.173.13:00:14.45#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.13:00:14.45#ibcon#[25=USB\r\n] 2006.173.13:00:14.45#ibcon#*before write, iclass 15, count 0 2006.173.13:00:14.45#ibcon#enter sib2, iclass 15, count 0 2006.173.13:00:14.45#ibcon#flushed, iclass 15, count 0 2006.173.13:00:14.45#ibcon#about to write, iclass 15, count 0 2006.173.13:00:14.45#ibcon#wrote, iclass 15, count 0 2006.173.13:00:14.45#ibcon#about to read 3, iclass 15, count 0 2006.173.13:00:14.48#ibcon#read 3, iclass 15, count 0 2006.173.13:00:14.48#ibcon#about to read 4, iclass 15, count 0 2006.173.13:00:14.48#ibcon#read 4, iclass 15, count 0 2006.173.13:00:14.48#ibcon#about to read 5, iclass 15, count 0 2006.173.13:00:14.48#ibcon#read 5, iclass 15, count 0 2006.173.13:00:14.48#ibcon#about to read 6, iclass 15, count 0 2006.173.13:00:14.48#ibcon#read 6, iclass 15, count 0 2006.173.13:00:14.48#ibcon#end of sib2, iclass 15, count 0 2006.173.13:00:14.48#ibcon#*after write, iclass 15, count 0 2006.173.13:00:14.48#ibcon#*before return 0, iclass 15, count 0 2006.173.13:00:14.48#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.13:00:14.48#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.13:00:14.48#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.13:00:14.48#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.13:00:14.48$vck44/valo=5,734.99 2006.173.13:00:14.48#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.13:00:14.48#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.13:00:14.48#ibcon#ireg 17 cls_cnt 0 2006.173.13:00:14.48#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.13:00:14.48#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.13:00:14.48#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.13:00:14.48#ibcon#enter wrdev, iclass 17, count 0 2006.173.13:00:14.48#ibcon#first serial, iclass 17, count 0 2006.173.13:00:14.48#ibcon#enter sib2, iclass 17, count 0 2006.173.13:00:14.48#ibcon#flushed, iclass 17, count 0 2006.173.13:00:14.48#ibcon#about to write, iclass 17, count 0 2006.173.13:00:14.48#ibcon#wrote, iclass 17, count 0 2006.173.13:00:14.48#ibcon#about to read 3, iclass 17, count 0 2006.173.13:00:14.50#ibcon#read 3, iclass 17, count 0 2006.173.13:00:14.50#ibcon#about to read 4, iclass 17, count 0 2006.173.13:00:14.50#ibcon#read 4, iclass 17, count 0 2006.173.13:00:14.50#ibcon#about to read 5, iclass 17, count 0 2006.173.13:00:14.50#ibcon#read 5, iclass 17, count 0 2006.173.13:00:14.50#ibcon#about to read 6, iclass 17, count 0 2006.173.13:00:14.50#ibcon#read 6, iclass 17, count 0 2006.173.13:00:14.50#ibcon#end of sib2, iclass 17, count 0 2006.173.13:00:14.50#ibcon#*mode == 0, iclass 17, count 0 2006.173.13:00:14.50#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.13:00:14.50#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.13:00:14.50#ibcon#*before write, iclass 17, count 0 2006.173.13:00:14.50#ibcon#enter sib2, iclass 17, count 0 2006.173.13:00:14.50#ibcon#flushed, iclass 17, count 0 2006.173.13:00:14.50#ibcon#about to write, iclass 17, count 0 2006.173.13:00:14.50#ibcon#wrote, iclass 17, count 0 2006.173.13:00:14.50#ibcon#about to read 3, iclass 17, count 0 2006.173.13:00:14.54#ibcon#read 3, iclass 17, count 0 2006.173.13:00:14.54#ibcon#about to read 4, iclass 17, count 0 2006.173.13:00:14.54#ibcon#read 4, iclass 17, count 0 2006.173.13:00:14.54#ibcon#about to read 5, iclass 17, count 0 2006.173.13:00:14.54#ibcon#read 5, iclass 17, count 0 2006.173.13:00:14.54#ibcon#about to read 6, iclass 17, count 0 2006.173.13:00:14.54#ibcon#read 6, iclass 17, count 0 2006.173.13:00:14.54#ibcon#end of sib2, iclass 17, count 0 2006.173.13:00:14.54#ibcon#*after write, iclass 17, count 0 2006.173.13:00:14.54#ibcon#*before return 0, iclass 17, count 0 2006.173.13:00:14.54#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.13:00:14.54#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.13:00:14.54#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.13:00:14.54#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.13:00:14.54$vck44/va=5,4 2006.173.13:00:14.54#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.13:00:14.54#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.13:00:14.54#ibcon#ireg 11 cls_cnt 2 2006.173.13:00:14.54#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.13:00:14.60#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.13:00:14.60#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.13:00:14.60#ibcon#enter wrdev, iclass 19, count 2 2006.173.13:00:14.60#ibcon#first serial, iclass 19, count 2 2006.173.13:00:14.60#ibcon#enter sib2, iclass 19, count 2 2006.173.13:00:14.60#ibcon#flushed, iclass 19, count 2 2006.173.13:00:14.60#ibcon#about to write, iclass 19, count 2 2006.173.13:00:14.60#ibcon#wrote, iclass 19, count 2 2006.173.13:00:14.60#ibcon#about to read 3, iclass 19, count 2 2006.173.13:00:14.62#ibcon#read 3, iclass 19, count 2 2006.173.13:00:14.62#ibcon#about to read 4, iclass 19, count 2 2006.173.13:00:14.62#ibcon#read 4, iclass 19, count 2 2006.173.13:00:14.62#ibcon#about to read 5, iclass 19, count 2 2006.173.13:00:14.62#ibcon#read 5, iclass 19, count 2 2006.173.13:00:14.62#ibcon#about to read 6, iclass 19, count 2 2006.173.13:00:14.62#ibcon#read 6, iclass 19, count 2 2006.173.13:00:14.62#ibcon#end of sib2, iclass 19, count 2 2006.173.13:00:14.62#ibcon#*mode == 0, iclass 19, count 2 2006.173.13:00:14.62#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.13:00:14.62#ibcon#[25=AT05-04\r\n] 2006.173.13:00:14.62#ibcon#*before write, iclass 19, count 2 2006.173.13:00:14.62#ibcon#enter sib2, iclass 19, count 2 2006.173.13:00:14.62#ibcon#flushed, iclass 19, count 2 2006.173.13:00:14.62#ibcon#about to write, iclass 19, count 2 2006.173.13:00:14.62#ibcon#wrote, iclass 19, count 2 2006.173.13:00:14.62#ibcon#about to read 3, iclass 19, count 2 2006.173.13:00:14.65#ibcon#read 3, iclass 19, count 2 2006.173.13:00:14.65#ibcon#about to read 4, iclass 19, count 2 2006.173.13:00:14.65#ibcon#read 4, iclass 19, count 2 2006.173.13:00:14.65#ibcon#about to read 5, iclass 19, count 2 2006.173.13:00:14.65#ibcon#read 5, iclass 19, count 2 2006.173.13:00:14.65#ibcon#about to read 6, iclass 19, count 2 2006.173.13:00:14.65#ibcon#read 6, iclass 19, count 2 2006.173.13:00:14.65#ibcon#end of sib2, iclass 19, count 2 2006.173.13:00:14.65#ibcon#*after write, iclass 19, count 2 2006.173.13:00:14.65#ibcon#*before return 0, iclass 19, count 2 2006.173.13:00:14.65#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.13:00:14.65#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.13:00:14.65#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.13:00:14.65#ibcon#ireg 7 cls_cnt 0 2006.173.13:00:14.65#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.13:00:14.77#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.13:00:14.77#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.13:00:14.77#ibcon#enter wrdev, iclass 19, count 0 2006.173.13:00:14.77#ibcon#first serial, iclass 19, count 0 2006.173.13:00:14.77#ibcon#enter sib2, iclass 19, count 0 2006.173.13:00:14.77#ibcon#flushed, iclass 19, count 0 2006.173.13:00:14.77#ibcon#about to write, iclass 19, count 0 2006.173.13:00:14.77#ibcon#wrote, iclass 19, count 0 2006.173.13:00:14.77#ibcon#about to read 3, iclass 19, count 0 2006.173.13:00:14.79#ibcon#read 3, iclass 19, count 0 2006.173.13:00:14.79#ibcon#about to read 4, iclass 19, count 0 2006.173.13:00:14.79#ibcon#read 4, iclass 19, count 0 2006.173.13:00:14.79#ibcon#about to read 5, iclass 19, count 0 2006.173.13:00:14.79#ibcon#read 5, iclass 19, count 0 2006.173.13:00:14.79#ibcon#about to read 6, iclass 19, count 0 2006.173.13:00:14.79#ibcon#read 6, iclass 19, count 0 2006.173.13:00:14.79#ibcon#end of sib2, iclass 19, count 0 2006.173.13:00:14.79#ibcon#*mode == 0, iclass 19, count 0 2006.173.13:00:14.79#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.13:00:14.79#ibcon#[25=USB\r\n] 2006.173.13:00:14.79#ibcon#*before write, iclass 19, count 0 2006.173.13:00:14.79#ibcon#enter sib2, iclass 19, count 0 2006.173.13:00:14.79#ibcon#flushed, iclass 19, count 0 2006.173.13:00:14.79#ibcon#about to write, iclass 19, count 0 2006.173.13:00:14.79#ibcon#wrote, iclass 19, count 0 2006.173.13:00:14.79#ibcon#about to read 3, iclass 19, count 0 2006.173.13:00:14.82#ibcon#read 3, iclass 19, count 0 2006.173.13:00:14.82#ibcon#about to read 4, iclass 19, count 0 2006.173.13:00:14.82#ibcon#read 4, iclass 19, count 0 2006.173.13:00:14.82#ibcon#about to read 5, iclass 19, count 0 2006.173.13:00:14.82#ibcon#read 5, iclass 19, count 0 2006.173.13:00:14.82#ibcon#about to read 6, iclass 19, count 0 2006.173.13:00:14.82#ibcon#read 6, iclass 19, count 0 2006.173.13:00:14.82#ibcon#end of sib2, iclass 19, count 0 2006.173.13:00:14.82#ibcon#*after write, iclass 19, count 0 2006.173.13:00:14.82#ibcon#*before return 0, iclass 19, count 0 2006.173.13:00:14.82#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.13:00:14.82#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.13:00:14.82#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.13:00:14.82#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.13:00:14.82$vck44/valo=6,814.99 2006.173.13:00:14.82#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.13:00:14.82#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.13:00:14.82#ibcon#ireg 17 cls_cnt 0 2006.173.13:00:14.82#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.13:00:14.82#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.13:00:14.82#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.13:00:14.82#ibcon#enter wrdev, iclass 21, count 0 2006.173.13:00:14.82#ibcon#first serial, iclass 21, count 0 2006.173.13:00:14.82#ibcon#enter sib2, iclass 21, count 0 2006.173.13:00:14.82#ibcon#flushed, iclass 21, count 0 2006.173.13:00:14.82#ibcon#about to write, iclass 21, count 0 2006.173.13:00:14.82#ibcon#wrote, iclass 21, count 0 2006.173.13:00:14.82#ibcon#about to read 3, iclass 21, count 0 2006.173.13:00:14.84#ibcon#read 3, iclass 21, count 0 2006.173.13:00:14.84#ibcon#about to read 4, iclass 21, count 0 2006.173.13:00:14.84#ibcon#read 4, iclass 21, count 0 2006.173.13:00:14.84#ibcon#about to read 5, iclass 21, count 0 2006.173.13:00:14.84#ibcon#read 5, iclass 21, count 0 2006.173.13:00:14.84#ibcon#about to read 6, iclass 21, count 0 2006.173.13:00:14.84#ibcon#read 6, iclass 21, count 0 2006.173.13:00:14.84#ibcon#end of sib2, iclass 21, count 0 2006.173.13:00:14.84#ibcon#*mode == 0, iclass 21, count 0 2006.173.13:00:14.84#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.13:00:14.84#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.13:00:14.84#ibcon#*before write, iclass 21, count 0 2006.173.13:00:14.84#ibcon#enter sib2, iclass 21, count 0 2006.173.13:00:14.84#ibcon#flushed, iclass 21, count 0 2006.173.13:00:14.84#ibcon#about to write, iclass 21, count 0 2006.173.13:00:14.84#ibcon#wrote, iclass 21, count 0 2006.173.13:00:14.84#ibcon#about to read 3, iclass 21, count 0 2006.173.13:00:14.88#ibcon#read 3, iclass 21, count 0 2006.173.13:00:14.88#ibcon#about to read 4, iclass 21, count 0 2006.173.13:00:14.88#ibcon#read 4, iclass 21, count 0 2006.173.13:00:14.88#ibcon#about to read 5, iclass 21, count 0 2006.173.13:00:14.88#ibcon#read 5, iclass 21, count 0 2006.173.13:00:14.88#ibcon#about to read 6, iclass 21, count 0 2006.173.13:00:14.88#ibcon#read 6, iclass 21, count 0 2006.173.13:00:14.88#ibcon#end of sib2, iclass 21, count 0 2006.173.13:00:14.88#ibcon#*after write, iclass 21, count 0 2006.173.13:00:14.88#ibcon#*before return 0, iclass 21, count 0 2006.173.13:00:14.88#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.13:00:14.88#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.13:00:14.88#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.13:00:14.88#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.13:00:14.88$vck44/va=6,3 2006.173.13:00:14.88#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.13:00:14.88#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.13:00:14.88#ibcon#ireg 11 cls_cnt 2 2006.173.13:00:14.88#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.13:00:14.94#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.13:00:14.94#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.13:00:14.94#ibcon#enter wrdev, iclass 23, count 2 2006.173.13:00:14.94#ibcon#first serial, iclass 23, count 2 2006.173.13:00:14.94#ibcon#enter sib2, iclass 23, count 2 2006.173.13:00:14.94#ibcon#flushed, iclass 23, count 2 2006.173.13:00:14.94#ibcon#about to write, iclass 23, count 2 2006.173.13:00:14.94#ibcon#wrote, iclass 23, count 2 2006.173.13:00:14.94#ibcon#about to read 3, iclass 23, count 2 2006.173.13:00:14.96#ibcon#read 3, iclass 23, count 2 2006.173.13:00:14.96#ibcon#about to read 4, iclass 23, count 2 2006.173.13:00:14.96#ibcon#read 4, iclass 23, count 2 2006.173.13:00:14.96#ibcon#about to read 5, iclass 23, count 2 2006.173.13:00:14.96#ibcon#read 5, iclass 23, count 2 2006.173.13:00:14.96#ibcon#about to read 6, iclass 23, count 2 2006.173.13:00:14.96#ibcon#read 6, iclass 23, count 2 2006.173.13:00:14.96#ibcon#end of sib2, iclass 23, count 2 2006.173.13:00:14.96#ibcon#*mode == 0, iclass 23, count 2 2006.173.13:00:14.96#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.13:00:14.96#ibcon#[25=AT06-03\r\n] 2006.173.13:00:14.96#ibcon#*before write, iclass 23, count 2 2006.173.13:00:14.96#ibcon#enter sib2, iclass 23, count 2 2006.173.13:00:14.96#ibcon#flushed, iclass 23, count 2 2006.173.13:00:14.96#ibcon#about to write, iclass 23, count 2 2006.173.13:00:14.96#ibcon#wrote, iclass 23, count 2 2006.173.13:00:14.96#ibcon#about to read 3, iclass 23, count 2 2006.173.13:00:14.99#ibcon#read 3, iclass 23, count 2 2006.173.13:00:14.99#ibcon#about to read 4, iclass 23, count 2 2006.173.13:00:14.99#ibcon#read 4, iclass 23, count 2 2006.173.13:00:14.99#ibcon#about to read 5, iclass 23, count 2 2006.173.13:00:14.99#ibcon#read 5, iclass 23, count 2 2006.173.13:00:14.99#ibcon#about to read 6, iclass 23, count 2 2006.173.13:00:14.99#ibcon#read 6, iclass 23, count 2 2006.173.13:00:14.99#ibcon#end of sib2, iclass 23, count 2 2006.173.13:00:14.99#ibcon#*after write, iclass 23, count 2 2006.173.13:00:14.99#ibcon#*before return 0, iclass 23, count 2 2006.173.13:00:14.99#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.13:00:14.99#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.13:00:14.99#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.13:00:14.99#ibcon#ireg 7 cls_cnt 0 2006.173.13:00:14.99#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.13:00:15.11#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.13:00:15.11#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.13:00:15.11#ibcon#enter wrdev, iclass 23, count 0 2006.173.13:00:15.11#ibcon#first serial, iclass 23, count 0 2006.173.13:00:15.11#ibcon#enter sib2, iclass 23, count 0 2006.173.13:00:15.11#ibcon#flushed, iclass 23, count 0 2006.173.13:00:15.11#ibcon#about to write, iclass 23, count 0 2006.173.13:00:15.11#ibcon#wrote, iclass 23, count 0 2006.173.13:00:15.11#ibcon#about to read 3, iclass 23, count 0 2006.173.13:00:15.13#ibcon#read 3, iclass 23, count 0 2006.173.13:00:15.13#ibcon#about to read 4, iclass 23, count 0 2006.173.13:00:15.13#ibcon#read 4, iclass 23, count 0 2006.173.13:00:15.13#ibcon#about to read 5, iclass 23, count 0 2006.173.13:00:15.13#ibcon#read 5, iclass 23, count 0 2006.173.13:00:15.13#ibcon#about to read 6, iclass 23, count 0 2006.173.13:00:15.13#ibcon#read 6, iclass 23, count 0 2006.173.13:00:15.13#ibcon#end of sib2, iclass 23, count 0 2006.173.13:00:15.13#ibcon#*mode == 0, iclass 23, count 0 2006.173.13:00:15.13#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.13:00:15.13#ibcon#[25=USB\r\n] 2006.173.13:00:15.13#ibcon#*before write, iclass 23, count 0 2006.173.13:00:15.13#ibcon#enter sib2, iclass 23, count 0 2006.173.13:00:15.13#ibcon#flushed, iclass 23, count 0 2006.173.13:00:15.13#ibcon#about to write, iclass 23, count 0 2006.173.13:00:15.13#ibcon#wrote, iclass 23, count 0 2006.173.13:00:15.13#ibcon#about to read 3, iclass 23, count 0 2006.173.13:00:15.16#ibcon#read 3, iclass 23, count 0 2006.173.13:00:15.16#ibcon#about to read 4, iclass 23, count 0 2006.173.13:00:15.16#ibcon#read 4, iclass 23, count 0 2006.173.13:00:15.16#ibcon#about to read 5, iclass 23, count 0 2006.173.13:00:15.16#ibcon#read 5, iclass 23, count 0 2006.173.13:00:15.16#ibcon#about to read 6, iclass 23, count 0 2006.173.13:00:15.16#ibcon#read 6, iclass 23, count 0 2006.173.13:00:15.16#ibcon#end of sib2, iclass 23, count 0 2006.173.13:00:15.16#ibcon#*after write, iclass 23, count 0 2006.173.13:00:15.16#ibcon#*before return 0, iclass 23, count 0 2006.173.13:00:15.16#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.13:00:15.16#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.13:00:15.16#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.13:00:15.16#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.13:00:15.16$vck44/valo=7,864.99 2006.173.13:00:15.16#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.13:00:15.16#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.13:00:15.16#ibcon#ireg 17 cls_cnt 0 2006.173.13:00:15.16#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.13:00:15.16#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.13:00:15.16#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.13:00:15.16#ibcon#enter wrdev, iclass 25, count 0 2006.173.13:00:15.16#ibcon#first serial, iclass 25, count 0 2006.173.13:00:15.16#ibcon#enter sib2, iclass 25, count 0 2006.173.13:00:15.16#ibcon#flushed, iclass 25, count 0 2006.173.13:00:15.16#ibcon#about to write, iclass 25, count 0 2006.173.13:00:15.16#ibcon#wrote, iclass 25, count 0 2006.173.13:00:15.16#ibcon#about to read 3, iclass 25, count 0 2006.173.13:00:15.18#ibcon#read 3, iclass 25, count 0 2006.173.13:00:15.18#ibcon#about to read 4, iclass 25, count 0 2006.173.13:00:15.18#ibcon#read 4, iclass 25, count 0 2006.173.13:00:15.18#ibcon#about to read 5, iclass 25, count 0 2006.173.13:00:15.18#ibcon#read 5, iclass 25, count 0 2006.173.13:00:15.18#ibcon#about to read 6, iclass 25, count 0 2006.173.13:00:15.18#ibcon#read 6, iclass 25, count 0 2006.173.13:00:15.18#ibcon#end of sib2, iclass 25, count 0 2006.173.13:00:15.18#ibcon#*mode == 0, iclass 25, count 0 2006.173.13:00:15.18#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.13:00:15.18#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.13:00:15.18#ibcon#*before write, iclass 25, count 0 2006.173.13:00:15.18#ibcon#enter sib2, iclass 25, count 0 2006.173.13:00:15.18#ibcon#flushed, iclass 25, count 0 2006.173.13:00:15.18#ibcon#about to write, iclass 25, count 0 2006.173.13:00:15.18#ibcon#wrote, iclass 25, count 0 2006.173.13:00:15.18#ibcon#about to read 3, iclass 25, count 0 2006.173.13:00:15.22#ibcon#read 3, iclass 25, count 0 2006.173.13:00:15.22#ibcon#about to read 4, iclass 25, count 0 2006.173.13:00:15.22#ibcon#read 4, iclass 25, count 0 2006.173.13:00:15.22#ibcon#about to read 5, iclass 25, count 0 2006.173.13:00:15.22#ibcon#read 5, iclass 25, count 0 2006.173.13:00:15.22#ibcon#about to read 6, iclass 25, count 0 2006.173.13:00:15.22#ibcon#read 6, iclass 25, count 0 2006.173.13:00:15.22#ibcon#end of sib2, iclass 25, count 0 2006.173.13:00:15.22#ibcon#*after write, iclass 25, count 0 2006.173.13:00:15.22#ibcon#*before return 0, iclass 25, count 0 2006.173.13:00:15.22#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.13:00:15.22#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.13:00:15.22#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.13:00:15.22#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.13:00:15.22$vck44/va=7,4 2006.173.13:00:15.22#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.13:00:15.22#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.13:00:15.22#ibcon#ireg 11 cls_cnt 2 2006.173.13:00:15.22#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.13:00:15.28#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.13:00:15.28#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.13:00:15.28#ibcon#enter wrdev, iclass 27, count 2 2006.173.13:00:15.28#ibcon#first serial, iclass 27, count 2 2006.173.13:00:15.28#ibcon#enter sib2, iclass 27, count 2 2006.173.13:00:15.28#ibcon#flushed, iclass 27, count 2 2006.173.13:00:15.28#ibcon#about to write, iclass 27, count 2 2006.173.13:00:15.28#ibcon#wrote, iclass 27, count 2 2006.173.13:00:15.28#ibcon#about to read 3, iclass 27, count 2 2006.173.13:00:15.30#ibcon#read 3, iclass 27, count 2 2006.173.13:00:15.30#ibcon#about to read 4, iclass 27, count 2 2006.173.13:00:15.30#ibcon#read 4, iclass 27, count 2 2006.173.13:00:15.30#ibcon#about to read 5, iclass 27, count 2 2006.173.13:00:15.30#ibcon#read 5, iclass 27, count 2 2006.173.13:00:15.30#ibcon#about to read 6, iclass 27, count 2 2006.173.13:00:15.30#ibcon#read 6, iclass 27, count 2 2006.173.13:00:15.30#ibcon#end of sib2, iclass 27, count 2 2006.173.13:00:15.30#ibcon#*mode == 0, iclass 27, count 2 2006.173.13:00:15.30#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.13:00:15.30#ibcon#[25=AT07-04\r\n] 2006.173.13:00:15.30#ibcon#*before write, iclass 27, count 2 2006.173.13:00:15.30#ibcon#enter sib2, iclass 27, count 2 2006.173.13:00:15.30#ibcon#flushed, iclass 27, count 2 2006.173.13:00:15.30#ibcon#about to write, iclass 27, count 2 2006.173.13:00:15.30#ibcon#wrote, iclass 27, count 2 2006.173.13:00:15.30#ibcon#about to read 3, iclass 27, count 2 2006.173.13:00:15.33#ibcon#read 3, iclass 27, count 2 2006.173.13:00:15.33#ibcon#about to read 4, iclass 27, count 2 2006.173.13:00:15.33#ibcon#read 4, iclass 27, count 2 2006.173.13:00:15.33#ibcon#about to read 5, iclass 27, count 2 2006.173.13:00:15.33#ibcon#read 5, iclass 27, count 2 2006.173.13:00:15.33#ibcon#about to read 6, iclass 27, count 2 2006.173.13:00:15.33#ibcon#read 6, iclass 27, count 2 2006.173.13:00:15.33#ibcon#end of sib2, iclass 27, count 2 2006.173.13:00:15.33#ibcon#*after write, iclass 27, count 2 2006.173.13:00:15.33#ibcon#*before return 0, iclass 27, count 2 2006.173.13:00:15.33#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.13:00:15.33#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.13:00:15.33#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.13:00:15.33#ibcon#ireg 7 cls_cnt 0 2006.173.13:00:15.33#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.13:00:15.45#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.13:00:15.45#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.13:00:15.45#ibcon#enter wrdev, iclass 27, count 0 2006.173.13:00:15.45#ibcon#first serial, iclass 27, count 0 2006.173.13:00:15.45#ibcon#enter sib2, iclass 27, count 0 2006.173.13:00:15.45#ibcon#flushed, iclass 27, count 0 2006.173.13:00:15.45#ibcon#about to write, iclass 27, count 0 2006.173.13:00:15.45#ibcon#wrote, iclass 27, count 0 2006.173.13:00:15.45#ibcon#about to read 3, iclass 27, count 0 2006.173.13:00:15.47#ibcon#read 3, iclass 27, count 0 2006.173.13:00:15.47#ibcon#about to read 4, iclass 27, count 0 2006.173.13:00:15.47#ibcon#read 4, iclass 27, count 0 2006.173.13:00:15.47#ibcon#about to read 5, iclass 27, count 0 2006.173.13:00:15.47#ibcon#read 5, iclass 27, count 0 2006.173.13:00:15.47#ibcon#about to read 6, iclass 27, count 0 2006.173.13:00:15.47#ibcon#read 6, iclass 27, count 0 2006.173.13:00:15.47#ibcon#end of sib2, iclass 27, count 0 2006.173.13:00:15.47#ibcon#*mode == 0, iclass 27, count 0 2006.173.13:00:15.47#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.13:00:15.47#ibcon#[25=USB\r\n] 2006.173.13:00:15.47#ibcon#*before write, iclass 27, count 0 2006.173.13:00:15.47#ibcon#enter sib2, iclass 27, count 0 2006.173.13:00:15.47#ibcon#flushed, iclass 27, count 0 2006.173.13:00:15.47#ibcon#about to write, iclass 27, count 0 2006.173.13:00:15.47#ibcon#wrote, iclass 27, count 0 2006.173.13:00:15.47#ibcon#about to read 3, iclass 27, count 0 2006.173.13:00:15.50#ibcon#read 3, iclass 27, count 0 2006.173.13:00:15.50#ibcon#about to read 4, iclass 27, count 0 2006.173.13:00:15.50#ibcon#read 4, iclass 27, count 0 2006.173.13:00:15.50#ibcon#about to read 5, iclass 27, count 0 2006.173.13:00:15.50#ibcon#read 5, iclass 27, count 0 2006.173.13:00:15.50#ibcon#about to read 6, iclass 27, count 0 2006.173.13:00:15.50#ibcon#read 6, iclass 27, count 0 2006.173.13:00:15.50#ibcon#end of sib2, iclass 27, count 0 2006.173.13:00:15.50#ibcon#*after write, iclass 27, count 0 2006.173.13:00:15.50#ibcon#*before return 0, iclass 27, count 0 2006.173.13:00:15.50#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.13:00:15.50#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.13:00:15.50#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.13:00:15.50#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.13:00:15.50$vck44/valo=8,884.99 2006.173.13:00:15.50#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.13:00:15.50#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.13:00:15.50#ibcon#ireg 17 cls_cnt 0 2006.173.13:00:15.50#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.13:00:15.50#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.13:00:15.50#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.13:00:15.50#ibcon#enter wrdev, iclass 29, count 0 2006.173.13:00:15.50#ibcon#first serial, iclass 29, count 0 2006.173.13:00:15.50#ibcon#enter sib2, iclass 29, count 0 2006.173.13:00:15.50#ibcon#flushed, iclass 29, count 0 2006.173.13:00:15.50#ibcon#about to write, iclass 29, count 0 2006.173.13:00:15.50#ibcon#wrote, iclass 29, count 0 2006.173.13:00:15.50#ibcon#about to read 3, iclass 29, count 0 2006.173.13:00:15.52#ibcon#read 3, iclass 29, count 0 2006.173.13:00:15.52#ibcon#about to read 4, iclass 29, count 0 2006.173.13:00:15.52#ibcon#read 4, iclass 29, count 0 2006.173.13:00:15.52#ibcon#about to read 5, iclass 29, count 0 2006.173.13:00:15.52#ibcon#read 5, iclass 29, count 0 2006.173.13:00:15.52#ibcon#about to read 6, iclass 29, count 0 2006.173.13:00:15.52#ibcon#read 6, iclass 29, count 0 2006.173.13:00:15.52#ibcon#end of sib2, iclass 29, count 0 2006.173.13:00:15.52#ibcon#*mode == 0, iclass 29, count 0 2006.173.13:00:15.52#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.13:00:15.52#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.13:00:15.52#ibcon#*before write, iclass 29, count 0 2006.173.13:00:15.52#ibcon#enter sib2, iclass 29, count 0 2006.173.13:00:15.52#ibcon#flushed, iclass 29, count 0 2006.173.13:00:15.52#ibcon#about to write, iclass 29, count 0 2006.173.13:00:15.52#ibcon#wrote, iclass 29, count 0 2006.173.13:00:15.52#ibcon#about to read 3, iclass 29, count 0 2006.173.13:00:15.56#ibcon#read 3, iclass 29, count 0 2006.173.13:00:15.56#ibcon#about to read 4, iclass 29, count 0 2006.173.13:00:15.56#ibcon#read 4, iclass 29, count 0 2006.173.13:00:15.56#ibcon#about to read 5, iclass 29, count 0 2006.173.13:00:15.56#ibcon#read 5, iclass 29, count 0 2006.173.13:00:15.56#ibcon#about to read 6, iclass 29, count 0 2006.173.13:00:15.56#ibcon#read 6, iclass 29, count 0 2006.173.13:00:15.56#ibcon#end of sib2, iclass 29, count 0 2006.173.13:00:15.56#ibcon#*after write, iclass 29, count 0 2006.173.13:00:15.56#ibcon#*before return 0, iclass 29, count 0 2006.173.13:00:15.56#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.13:00:15.56#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.13:00:15.56#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.13:00:15.56#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.13:00:15.56$vck44/va=8,4 2006.173.13:00:15.56#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.13:00:15.56#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.13:00:15.56#ibcon#ireg 11 cls_cnt 2 2006.173.13:00:15.56#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.13:00:15.62#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.13:00:15.62#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.13:00:15.62#ibcon#enter wrdev, iclass 31, count 2 2006.173.13:00:15.62#ibcon#first serial, iclass 31, count 2 2006.173.13:00:15.62#ibcon#enter sib2, iclass 31, count 2 2006.173.13:00:15.62#ibcon#flushed, iclass 31, count 2 2006.173.13:00:15.62#ibcon#about to write, iclass 31, count 2 2006.173.13:00:15.62#ibcon#wrote, iclass 31, count 2 2006.173.13:00:15.62#ibcon#about to read 3, iclass 31, count 2 2006.173.13:00:15.64#ibcon#read 3, iclass 31, count 2 2006.173.13:00:15.64#ibcon#about to read 4, iclass 31, count 2 2006.173.13:00:15.64#ibcon#read 4, iclass 31, count 2 2006.173.13:00:15.64#ibcon#about to read 5, iclass 31, count 2 2006.173.13:00:15.64#ibcon#read 5, iclass 31, count 2 2006.173.13:00:15.64#ibcon#about to read 6, iclass 31, count 2 2006.173.13:00:15.64#ibcon#read 6, iclass 31, count 2 2006.173.13:00:15.64#ibcon#end of sib2, iclass 31, count 2 2006.173.13:00:15.64#ibcon#*mode == 0, iclass 31, count 2 2006.173.13:00:15.64#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.13:00:15.64#ibcon#[25=AT08-04\r\n] 2006.173.13:00:15.64#ibcon#*before write, iclass 31, count 2 2006.173.13:00:15.64#ibcon#enter sib2, iclass 31, count 2 2006.173.13:00:15.64#ibcon#flushed, iclass 31, count 2 2006.173.13:00:15.64#ibcon#about to write, iclass 31, count 2 2006.173.13:00:15.64#ibcon#wrote, iclass 31, count 2 2006.173.13:00:15.64#ibcon#about to read 3, iclass 31, count 2 2006.173.13:00:15.64#abcon#<5=/04 1.1 2.1 22.16 961004.3\r\n> 2006.173.13:00:15.66#abcon#{5=INTERFACE CLEAR} 2006.173.13:00:15.67#ibcon#read 3, iclass 31, count 2 2006.173.13:00:15.67#ibcon#about to read 4, iclass 31, count 2 2006.173.13:00:15.67#ibcon#read 4, iclass 31, count 2 2006.173.13:00:15.67#ibcon#about to read 5, iclass 31, count 2 2006.173.13:00:15.67#ibcon#read 5, iclass 31, count 2 2006.173.13:00:15.67#ibcon#about to read 6, iclass 31, count 2 2006.173.13:00:15.67#ibcon#read 6, iclass 31, count 2 2006.173.13:00:15.67#ibcon#end of sib2, iclass 31, count 2 2006.173.13:00:15.67#ibcon#*after write, iclass 31, count 2 2006.173.13:00:15.67#ibcon#*before return 0, iclass 31, count 2 2006.173.13:00:15.67#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.13:00:15.67#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.13:00:15.67#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.13:00:15.67#ibcon#ireg 7 cls_cnt 0 2006.173.13:00:15.67#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.13:00:15.72#abcon#[5=S1D000X0/0*\r\n] 2006.173.13:00:15.79#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.13:00:15.79#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.13:00:15.79#ibcon#enter wrdev, iclass 31, count 0 2006.173.13:00:15.79#ibcon#first serial, iclass 31, count 0 2006.173.13:00:15.79#ibcon#enter sib2, iclass 31, count 0 2006.173.13:00:15.79#ibcon#flushed, iclass 31, count 0 2006.173.13:00:15.79#ibcon#about to write, iclass 31, count 0 2006.173.13:00:15.79#ibcon#wrote, iclass 31, count 0 2006.173.13:00:15.79#ibcon#about to read 3, iclass 31, count 0 2006.173.13:00:15.81#ibcon#read 3, iclass 31, count 0 2006.173.13:00:15.81#ibcon#about to read 4, iclass 31, count 0 2006.173.13:00:15.81#ibcon#read 4, iclass 31, count 0 2006.173.13:00:15.81#ibcon#about to read 5, iclass 31, count 0 2006.173.13:00:15.81#ibcon#read 5, iclass 31, count 0 2006.173.13:00:15.81#ibcon#about to read 6, iclass 31, count 0 2006.173.13:00:15.81#ibcon#read 6, iclass 31, count 0 2006.173.13:00:15.81#ibcon#end of sib2, iclass 31, count 0 2006.173.13:00:15.81#ibcon#*mode == 0, iclass 31, count 0 2006.173.13:00:15.81#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.13:00:15.81#ibcon#[25=USB\r\n] 2006.173.13:00:15.81#ibcon#*before write, iclass 31, count 0 2006.173.13:00:15.81#ibcon#enter sib2, iclass 31, count 0 2006.173.13:00:15.81#ibcon#flushed, iclass 31, count 0 2006.173.13:00:15.81#ibcon#about to write, iclass 31, count 0 2006.173.13:00:15.81#ibcon#wrote, iclass 31, count 0 2006.173.13:00:15.81#ibcon#about to read 3, iclass 31, count 0 2006.173.13:00:15.84#ibcon#read 3, iclass 31, count 0 2006.173.13:00:15.84#ibcon#about to read 4, iclass 31, count 0 2006.173.13:00:15.84#ibcon#read 4, iclass 31, count 0 2006.173.13:00:15.84#ibcon#about to read 5, iclass 31, count 0 2006.173.13:00:15.84#ibcon#read 5, iclass 31, count 0 2006.173.13:00:15.84#ibcon#about to read 6, iclass 31, count 0 2006.173.13:00:15.84#ibcon#read 6, iclass 31, count 0 2006.173.13:00:15.84#ibcon#end of sib2, iclass 31, count 0 2006.173.13:00:15.84#ibcon#*after write, iclass 31, count 0 2006.173.13:00:15.84#ibcon#*before return 0, iclass 31, count 0 2006.173.13:00:15.84#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.13:00:15.84#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.13:00:15.84#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.13:00:15.84#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.13:00:15.84$vck44/vblo=1,629.99 2006.173.13:00:15.84#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.13:00:15.84#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.13:00:15.84#ibcon#ireg 17 cls_cnt 0 2006.173.13:00:15.84#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.13:00:15.84#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.13:00:15.84#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.13:00:15.84#ibcon#enter wrdev, iclass 37, count 0 2006.173.13:00:15.84#ibcon#first serial, iclass 37, count 0 2006.173.13:00:15.84#ibcon#enter sib2, iclass 37, count 0 2006.173.13:00:15.84#ibcon#flushed, iclass 37, count 0 2006.173.13:00:15.84#ibcon#about to write, iclass 37, count 0 2006.173.13:00:15.84#ibcon#wrote, iclass 37, count 0 2006.173.13:00:15.84#ibcon#about to read 3, iclass 37, count 0 2006.173.13:00:15.86#ibcon#read 3, iclass 37, count 0 2006.173.13:00:15.86#ibcon#about to read 4, iclass 37, count 0 2006.173.13:00:15.86#ibcon#read 4, iclass 37, count 0 2006.173.13:00:15.86#ibcon#about to read 5, iclass 37, count 0 2006.173.13:00:15.86#ibcon#read 5, iclass 37, count 0 2006.173.13:00:15.86#ibcon#about to read 6, iclass 37, count 0 2006.173.13:00:15.86#ibcon#read 6, iclass 37, count 0 2006.173.13:00:15.86#ibcon#end of sib2, iclass 37, count 0 2006.173.13:00:15.86#ibcon#*mode == 0, iclass 37, count 0 2006.173.13:00:15.86#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.13:00:15.86#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.13:00:15.86#ibcon#*before write, iclass 37, count 0 2006.173.13:00:15.86#ibcon#enter sib2, iclass 37, count 0 2006.173.13:00:15.86#ibcon#flushed, iclass 37, count 0 2006.173.13:00:15.86#ibcon#about to write, iclass 37, count 0 2006.173.13:00:15.86#ibcon#wrote, iclass 37, count 0 2006.173.13:00:15.86#ibcon#about to read 3, iclass 37, count 0 2006.173.13:00:15.90#ibcon#read 3, iclass 37, count 0 2006.173.13:00:15.90#ibcon#about to read 4, iclass 37, count 0 2006.173.13:00:15.90#ibcon#read 4, iclass 37, count 0 2006.173.13:00:15.90#ibcon#about to read 5, iclass 37, count 0 2006.173.13:00:15.90#ibcon#read 5, iclass 37, count 0 2006.173.13:00:15.90#ibcon#about to read 6, iclass 37, count 0 2006.173.13:00:15.90#ibcon#read 6, iclass 37, count 0 2006.173.13:00:15.90#ibcon#end of sib2, iclass 37, count 0 2006.173.13:00:15.90#ibcon#*after write, iclass 37, count 0 2006.173.13:00:15.90#ibcon#*before return 0, iclass 37, count 0 2006.173.13:00:15.90#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.13:00:15.90#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.13:00:15.90#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.13:00:15.90#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.13:00:15.90$vck44/vb=1,4 2006.173.13:00:15.90#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.13:00:15.90#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.13:00:15.90#ibcon#ireg 11 cls_cnt 2 2006.173.13:00:15.90#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.13:00:15.90#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.13:00:15.90#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.13:00:15.90#ibcon#enter wrdev, iclass 39, count 2 2006.173.13:00:15.90#ibcon#first serial, iclass 39, count 2 2006.173.13:00:15.90#ibcon#enter sib2, iclass 39, count 2 2006.173.13:00:15.90#ibcon#flushed, iclass 39, count 2 2006.173.13:00:15.90#ibcon#about to write, iclass 39, count 2 2006.173.13:00:15.90#ibcon#wrote, iclass 39, count 2 2006.173.13:00:15.90#ibcon#about to read 3, iclass 39, count 2 2006.173.13:00:15.92#ibcon#read 3, iclass 39, count 2 2006.173.13:00:15.92#ibcon#about to read 4, iclass 39, count 2 2006.173.13:00:15.92#ibcon#read 4, iclass 39, count 2 2006.173.13:00:15.92#ibcon#about to read 5, iclass 39, count 2 2006.173.13:00:15.92#ibcon#read 5, iclass 39, count 2 2006.173.13:00:15.92#ibcon#about to read 6, iclass 39, count 2 2006.173.13:00:15.92#ibcon#read 6, iclass 39, count 2 2006.173.13:00:15.92#ibcon#end of sib2, iclass 39, count 2 2006.173.13:00:15.92#ibcon#*mode == 0, iclass 39, count 2 2006.173.13:00:15.92#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.13:00:15.92#ibcon#[27=AT01-04\r\n] 2006.173.13:00:15.92#ibcon#*before write, iclass 39, count 2 2006.173.13:00:15.92#ibcon#enter sib2, iclass 39, count 2 2006.173.13:00:15.92#ibcon#flushed, iclass 39, count 2 2006.173.13:00:15.92#ibcon#about to write, iclass 39, count 2 2006.173.13:00:15.92#ibcon#wrote, iclass 39, count 2 2006.173.13:00:15.92#ibcon#about to read 3, iclass 39, count 2 2006.173.13:00:15.95#ibcon#read 3, iclass 39, count 2 2006.173.13:00:15.95#ibcon#about to read 4, iclass 39, count 2 2006.173.13:00:15.95#ibcon#read 4, iclass 39, count 2 2006.173.13:00:15.95#ibcon#about to read 5, iclass 39, count 2 2006.173.13:00:15.95#ibcon#read 5, iclass 39, count 2 2006.173.13:00:15.95#ibcon#about to read 6, iclass 39, count 2 2006.173.13:00:15.95#ibcon#read 6, iclass 39, count 2 2006.173.13:00:15.95#ibcon#end of sib2, iclass 39, count 2 2006.173.13:00:15.95#ibcon#*after write, iclass 39, count 2 2006.173.13:00:15.95#ibcon#*before return 0, iclass 39, count 2 2006.173.13:00:15.95#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.13:00:15.95#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.13:00:15.95#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.13:00:15.95#ibcon#ireg 7 cls_cnt 0 2006.173.13:00:15.95#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.13:00:16.07#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.13:00:16.07#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.13:00:16.07#ibcon#enter wrdev, iclass 39, count 0 2006.173.13:00:16.07#ibcon#first serial, iclass 39, count 0 2006.173.13:00:16.07#ibcon#enter sib2, iclass 39, count 0 2006.173.13:00:16.07#ibcon#flushed, iclass 39, count 0 2006.173.13:00:16.07#ibcon#about to write, iclass 39, count 0 2006.173.13:00:16.07#ibcon#wrote, iclass 39, count 0 2006.173.13:00:16.07#ibcon#about to read 3, iclass 39, count 0 2006.173.13:00:16.09#ibcon#read 3, iclass 39, count 0 2006.173.13:00:16.09#ibcon#about to read 4, iclass 39, count 0 2006.173.13:00:16.09#ibcon#read 4, iclass 39, count 0 2006.173.13:00:16.09#ibcon#about to read 5, iclass 39, count 0 2006.173.13:00:16.09#ibcon#read 5, iclass 39, count 0 2006.173.13:00:16.09#ibcon#about to read 6, iclass 39, count 0 2006.173.13:00:16.09#ibcon#read 6, iclass 39, count 0 2006.173.13:00:16.09#ibcon#end of sib2, iclass 39, count 0 2006.173.13:00:16.09#ibcon#*mode == 0, iclass 39, count 0 2006.173.13:00:16.09#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.13:00:16.09#ibcon#[27=USB\r\n] 2006.173.13:00:16.09#ibcon#*before write, iclass 39, count 0 2006.173.13:00:16.09#ibcon#enter sib2, iclass 39, count 0 2006.173.13:00:16.09#ibcon#flushed, iclass 39, count 0 2006.173.13:00:16.09#ibcon#about to write, iclass 39, count 0 2006.173.13:00:16.09#ibcon#wrote, iclass 39, count 0 2006.173.13:00:16.09#ibcon#about to read 3, iclass 39, count 0 2006.173.13:00:16.12#ibcon#read 3, iclass 39, count 0 2006.173.13:00:16.12#ibcon#about to read 4, iclass 39, count 0 2006.173.13:00:16.12#ibcon#read 4, iclass 39, count 0 2006.173.13:00:16.12#ibcon#about to read 5, iclass 39, count 0 2006.173.13:00:16.12#ibcon#read 5, iclass 39, count 0 2006.173.13:00:16.12#ibcon#about to read 6, iclass 39, count 0 2006.173.13:00:16.12#ibcon#read 6, iclass 39, count 0 2006.173.13:00:16.12#ibcon#end of sib2, iclass 39, count 0 2006.173.13:00:16.12#ibcon#*after write, iclass 39, count 0 2006.173.13:00:16.12#ibcon#*before return 0, iclass 39, count 0 2006.173.13:00:16.12#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.13:00:16.12#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.13:00:16.12#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.13:00:16.12#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.13:00:16.12$vck44/vblo=2,634.99 2006.173.13:00:16.12#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.13:00:16.12#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.13:00:16.12#ibcon#ireg 17 cls_cnt 0 2006.173.13:00:16.12#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.13:00:16.12#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.13:00:16.12#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.13:00:16.12#ibcon#enter wrdev, iclass 3, count 0 2006.173.13:00:16.12#ibcon#first serial, iclass 3, count 0 2006.173.13:00:16.12#ibcon#enter sib2, iclass 3, count 0 2006.173.13:00:16.12#ibcon#flushed, iclass 3, count 0 2006.173.13:00:16.12#ibcon#about to write, iclass 3, count 0 2006.173.13:00:16.12#ibcon#wrote, iclass 3, count 0 2006.173.13:00:16.12#ibcon#about to read 3, iclass 3, count 0 2006.173.13:00:16.14#ibcon#read 3, iclass 3, count 0 2006.173.13:00:16.14#ibcon#about to read 4, iclass 3, count 0 2006.173.13:00:16.14#ibcon#read 4, iclass 3, count 0 2006.173.13:00:16.14#ibcon#about to read 5, iclass 3, count 0 2006.173.13:00:16.14#ibcon#read 5, iclass 3, count 0 2006.173.13:00:16.14#ibcon#about to read 6, iclass 3, count 0 2006.173.13:00:16.14#ibcon#read 6, iclass 3, count 0 2006.173.13:00:16.14#ibcon#end of sib2, iclass 3, count 0 2006.173.13:00:16.14#ibcon#*mode == 0, iclass 3, count 0 2006.173.13:00:16.14#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.13:00:16.14#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.13:00:16.14#ibcon#*before write, iclass 3, count 0 2006.173.13:00:16.14#ibcon#enter sib2, iclass 3, count 0 2006.173.13:00:16.14#ibcon#flushed, iclass 3, count 0 2006.173.13:00:16.14#ibcon#about to write, iclass 3, count 0 2006.173.13:00:16.14#ibcon#wrote, iclass 3, count 0 2006.173.13:00:16.14#ibcon#about to read 3, iclass 3, count 0 2006.173.13:00:16.18#ibcon#read 3, iclass 3, count 0 2006.173.13:00:16.18#ibcon#about to read 4, iclass 3, count 0 2006.173.13:00:16.18#ibcon#read 4, iclass 3, count 0 2006.173.13:00:16.18#ibcon#about to read 5, iclass 3, count 0 2006.173.13:00:16.18#ibcon#read 5, iclass 3, count 0 2006.173.13:00:16.18#ibcon#about to read 6, iclass 3, count 0 2006.173.13:00:16.18#ibcon#read 6, iclass 3, count 0 2006.173.13:00:16.18#ibcon#end of sib2, iclass 3, count 0 2006.173.13:00:16.18#ibcon#*after write, iclass 3, count 0 2006.173.13:00:16.18#ibcon#*before return 0, iclass 3, count 0 2006.173.13:00:16.18#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.13:00:16.18#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.13:00:16.18#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.13:00:16.18#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.13:00:16.18$vck44/vb=2,4 2006.173.13:00:16.18#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.13:00:16.18#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.13:00:16.18#ibcon#ireg 11 cls_cnt 2 2006.173.13:00:16.18#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.13:00:16.24#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.13:00:16.24#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.13:00:16.24#ibcon#enter wrdev, iclass 5, count 2 2006.173.13:00:16.24#ibcon#first serial, iclass 5, count 2 2006.173.13:00:16.24#ibcon#enter sib2, iclass 5, count 2 2006.173.13:00:16.24#ibcon#flushed, iclass 5, count 2 2006.173.13:00:16.24#ibcon#about to write, iclass 5, count 2 2006.173.13:00:16.24#ibcon#wrote, iclass 5, count 2 2006.173.13:00:16.24#ibcon#about to read 3, iclass 5, count 2 2006.173.13:00:16.26#ibcon#read 3, iclass 5, count 2 2006.173.13:00:16.26#ibcon#about to read 4, iclass 5, count 2 2006.173.13:00:16.26#ibcon#read 4, iclass 5, count 2 2006.173.13:00:16.26#ibcon#about to read 5, iclass 5, count 2 2006.173.13:00:16.26#ibcon#read 5, iclass 5, count 2 2006.173.13:00:16.26#ibcon#about to read 6, iclass 5, count 2 2006.173.13:00:16.26#ibcon#read 6, iclass 5, count 2 2006.173.13:00:16.26#ibcon#end of sib2, iclass 5, count 2 2006.173.13:00:16.26#ibcon#*mode == 0, iclass 5, count 2 2006.173.13:00:16.26#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.13:00:16.26#ibcon#[27=AT02-04\r\n] 2006.173.13:00:16.26#ibcon#*before write, iclass 5, count 2 2006.173.13:00:16.26#ibcon#enter sib2, iclass 5, count 2 2006.173.13:00:16.26#ibcon#flushed, iclass 5, count 2 2006.173.13:00:16.26#ibcon#about to write, iclass 5, count 2 2006.173.13:00:16.26#ibcon#wrote, iclass 5, count 2 2006.173.13:00:16.26#ibcon#about to read 3, iclass 5, count 2 2006.173.13:00:16.29#ibcon#read 3, iclass 5, count 2 2006.173.13:00:16.29#ibcon#about to read 4, iclass 5, count 2 2006.173.13:00:16.29#ibcon#read 4, iclass 5, count 2 2006.173.13:00:16.29#ibcon#about to read 5, iclass 5, count 2 2006.173.13:00:16.29#ibcon#read 5, iclass 5, count 2 2006.173.13:00:16.29#ibcon#about to read 6, iclass 5, count 2 2006.173.13:00:16.29#ibcon#read 6, iclass 5, count 2 2006.173.13:00:16.29#ibcon#end of sib2, iclass 5, count 2 2006.173.13:00:16.29#ibcon#*after write, iclass 5, count 2 2006.173.13:00:16.29#ibcon#*before return 0, iclass 5, count 2 2006.173.13:00:16.29#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.13:00:16.29#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.13:00:16.29#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.13:00:16.29#ibcon#ireg 7 cls_cnt 0 2006.173.13:00:16.29#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.13:00:16.41#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.13:00:16.41#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.13:00:16.41#ibcon#enter wrdev, iclass 5, count 0 2006.173.13:00:16.41#ibcon#first serial, iclass 5, count 0 2006.173.13:00:16.41#ibcon#enter sib2, iclass 5, count 0 2006.173.13:00:16.41#ibcon#flushed, iclass 5, count 0 2006.173.13:00:16.41#ibcon#about to write, iclass 5, count 0 2006.173.13:00:16.41#ibcon#wrote, iclass 5, count 0 2006.173.13:00:16.41#ibcon#about to read 3, iclass 5, count 0 2006.173.13:00:16.43#ibcon#read 3, iclass 5, count 0 2006.173.13:00:16.43#ibcon#about to read 4, iclass 5, count 0 2006.173.13:00:16.43#ibcon#read 4, iclass 5, count 0 2006.173.13:00:16.43#ibcon#about to read 5, iclass 5, count 0 2006.173.13:00:16.43#ibcon#read 5, iclass 5, count 0 2006.173.13:00:16.43#ibcon#about to read 6, iclass 5, count 0 2006.173.13:00:16.43#ibcon#read 6, iclass 5, count 0 2006.173.13:00:16.43#ibcon#end of sib2, iclass 5, count 0 2006.173.13:00:16.43#ibcon#*mode == 0, iclass 5, count 0 2006.173.13:00:16.43#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.13:00:16.43#ibcon#[27=USB\r\n] 2006.173.13:00:16.43#ibcon#*before write, iclass 5, count 0 2006.173.13:00:16.43#ibcon#enter sib2, iclass 5, count 0 2006.173.13:00:16.43#ibcon#flushed, iclass 5, count 0 2006.173.13:00:16.43#ibcon#about to write, iclass 5, count 0 2006.173.13:00:16.43#ibcon#wrote, iclass 5, count 0 2006.173.13:00:16.43#ibcon#about to read 3, iclass 5, count 0 2006.173.13:00:16.46#ibcon#read 3, iclass 5, count 0 2006.173.13:00:16.46#ibcon#about to read 4, iclass 5, count 0 2006.173.13:00:16.46#ibcon#read 4, iclass 5, count 0 2006.173.13:00:16.46#ibcon#about to read 5, iclass 5, count 0 2006.173.13:00:16.46#ibcon#read 5, iclass 5, count 0 2006.173.13:00:16.46#ibcon#about to read 6, iclass 5, count 0 2006.173.13:00:16.46#ibcon#read 6, iclass 5, count 0 2006.173.13:00:16.46#ibcon#end of sib2, iclass 5, count 0 2006.173.13:00:16.46#ibcon#*after write, iclass 5, count 0 2006.173.13:00:16.46#ibcon#*before return 0, iclass 5, count 0 2006.173.13:00:16.46#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.13:00:16.46#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.13:00:16.46#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.13:00:16.46#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.13:00:16.46$vck44/vblo=3,649.99 2006.173.13:00:16.46#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.13:00:16.46#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.13:00:16.46#ibcon#ireg 17 cls_cnt 0 2006.173.13:00:16.46#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.13:00:16.46#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.13:00:16.46#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.13:00:16.46#ibcon#enter wrdev, iclass 7, count 0 2006.173.13:00:16.46#ibcon#first serial, iclass 7, count 0 2006.173.13:00:16.46#ibcon#enter sib2, iclass 7, count 0 2006.173.13:00:16.46#ibcon#flushed, iclass 7, count 0 2006.173.13:00:16.46#ibcon#about to write, iclass 7, count 0 2006.173.13:00:16.46#ibcon#wrote, iclass 7, count 0 2006.173.13:00:16.46#ibcon#about to read 3, iclass 7, count 0 2006.173.13:00:16.48#ibcon#read 3, iclass 7, count 0 2006.173.13:00:16.48#ibcon#about to read 4, iclass 7, count 0 2006.173.13:00:16.48#ibcon#read 4, iclass 7, count 0 2006.173.13:00:16.48#ibcon#about to read 5, iclass 7, count 0 2006.173.13:00:16.48#ibcon#read 5, iclass 7, count 0 2006.173.13:00:16.48#ibcon#about to read 6, iclass 7, count 0 2006.173.13:00:16.48#ibcon#read 6, iclass 7, count 0 2006.173.13:00:16.48#ibcon#end of sib2, iclass 7, count 0 2006.173.13:00:16.48#ibcon#*mode == 0, iclass 7, count 0 2006.173.13:00:16.48#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.13:00:16.48#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.13:00:16.48#ibcon#*before write, iclass 7, count 0 2006.173.13:00:16.48#ibcon#enter sib2, iclass 7, count 0 2006.173.13:00:16.48#ibcon#flushed, iclass 7, count 0 2006.173.13:00:16.48#ibcon#about to write, iclass 7, count 0 2006.173.13:00:16.48#ibcon#wrote, iclass 7, count 0 2006.173.13:00:16.48#ibcon#about to read 3, iclass 7, count 0 2006.173.13:00:16.52#ibcon#read 3, iclass 7, count 0 2006.173.13:00:16.52#ibcon#about to read 4, iclass 7, count 0 2006.173.13:00:16.52#ibcon#read 4, iclass 7, count 0 2006.173.13:00:16.52#ibcon#about to read 5, iclass 7, count 0 2006.173.13:00:16.52#ibcon#read 5, iclass 7, count 0 2006.173.13:00:16.52#ibcon#about to read 6, iclass 7, count 0 2006.173.13:00:16.52#ibcon#read 6, iclass 7, count 0 2006.173.13:00:16.52#ibcon#end of sib2, iclass 7, count 0 2006.173.13:00:16.52#ibcon#*after write, iclass 7, count 0 2006.173.13:00:16.52#ibcon#*before return 0, iclass 7, count 0 2006.173.13:00:16.52#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.13:00:16.52#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.13:00:16.52#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.13:00:16.52#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.13:00:16.52$vck44/vb=3,4 2006.173.13:00:16.52#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.13:00:16.52#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.13:00:16.52#ibcon#ireg 11 cls_cnt 2 2006.173.13:00:16.52#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.13:00:16.58#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.13:00:16.58#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.13:00:16.58#ibcon#enter wrdev, iclass 11, count 2 2006.173.13:00:16.58#ibcon#first serial, iclass 11, count 2 2006.173.13:00:16.58#ibcon#enter sib2, iclass 11, count 2 2006.173.13:00:16.58#ibcon#flushed, iclass 11, count 2 2006.173.13:00:16.58#ibcon#about to write, iclass 11, count 2 2006.173.13:00:16.58#ibcon#wrote, iclass 11, count 2 2006.173.13:00:16.58#ibcon#about to read 3, iclass 11, count 2 2006.173.13:00:16.60#ibcon#read 3, iclass 11, count 2 2006.173.13:00:16.60#ibcon#about to read 4, iclass 11, count 2 2006.173.13:00:16.60#ibcon#read 4, iclass 11, count 2 2006.173.13:00:16.60#ibcon#about to read 5, iclass 11, count 2 2006.173.13:00:16.60#ibcon#read 5, iclass 11, count 2 2006.173.13:00:16.60#ibcon#about to read 6, iclass 11, count 2 2006.173.13:00:16.60#ibcon#read 6, iclass 11, count 2 2006.173.13:00:16.60#ibcon#end of sib2, iclass 11, count 2 2006.173.13:00:16.60#ibcon#*mode == 0, iclass 11, count 2 2006.173.13:00:16.60#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.13:00:16.60#ibcon#[27=AT03-04\r\n] 2006.173.13:00:16.60#ibcon#*before write, iclass 11, count 2 2006.173.13:00:16.60#ibcon#enter sib2, iclass 11, count 2 2006.173.13:00:16.60#ibcon#flushed, iclass 11, count 2 2006.173.13:00:16.60#ibcon#about to write, iclass 11, count 2 2006.173.13:00:16.60#ibcon#wrote, iclass 11, count 2 2006.173.13:00:16.60#ibcon#about to read 3, iclass 11, count 2 2006.173.13:00:16.63#ibcon#read 3, iclass 11, count 2 2006.173.13:00:16.63#ibcon#about to read 4, iclass 11, count 2 2006.173.13:00:16.63#ibcon#read 4, iclass 11, count 2 2006.173.13:00:16.63#ibcon#about to read 5, iclass 11, count 2 2006.173.13:00:16.63#ibcon#read 5, iclass 11, count 2 2006.173.13:00:16.63#ibcon#about to read 6, iclass 11, count 2 2006.173.13:00:16.63#ibcon#read 6, iclass 11, count 2 2006.173.13:00:16.63#ibcon#end of sib2, iclass 11, count 2 2006.173.13:00:16.63#ibcon#*after write, iclass 11, count 2 2006.173.13:00:16.63#ibcon#*before return 0, iclass 11, count 2 2006.173.13:00:16.63#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.13:00:16.63#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.13:00:16.63#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.13:00:16.63#ibcon#ireg 7 cls_cnt 0 2006.173.13:00:16.63#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.13:00:16.75#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.13:00:16.75#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.13:00:16.75#ibcon#enter wrdev, iclass 11, count 0 2006.173.13:00:16.75#ibcon#first serial, iclass 11, count 0 2006.173.13:00:16.75#ibcon#enter sib2, iclass 11, count 0 2006.173.13:00:16.75#ibcon#flushed, iclass 11, count 0 2006.173.13:00:16.75#ibcon#about to write, iclass 11, count 0 2006.173.13:00:16.75#ibcon#wrote, iclass 11, count 0 2006.173.13:00:16.75#ibcon#about to read 3, iclass 11, count 0 2006.173.13:00:16.77#ibcon#read 3, iclass 11, count 0 2006.173.13:00:16.77#ibcon#about to read 4, iclass 11, count 0 2006.173.13:00:16.77#ibcon#read 4, iclass 11, count 0 2006.173.13:00:16.77#ibcon#about to read 5, iclass 11, count 0 2006.173.13:00:16.77#ibcon#read 5, iclass 11, count 0 2006.173.13:00:16.77#ibcon#about to read 6, iclass 11, count 0 2006.173.13:00:16.77#ibcon#read 6, iclass 11, count 0 2006.173.13:00:16.77#ibcon#end of sib2, iclass 11, count 0 2006.173.13:00:16.77#ibcon#*mode == 0, iclass 11, count 0 2006.173.13:00:16.77#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.13:00:16.77#ibcon#[27=USB\r\n] 2006.173.13:00:16.77#ibcon#*before write, iclass 11, count 0 2006.173.13:00:16.77#ibcon#enter sib2, iclass 11, count 0 2006.173.13:00:16.77#ibcon#flushed, iclass 11, count 0 2006.173.13:00:16.77#ibcon#about to write, iclass 11, count 0 2006.173.13:00:16.77#ibcon#wrote, iclass 11, count 0 2006.173.13:00:16.77#ibcon#about to read 3, iclass 11, count 0 2006.173.13:00:16.80#ibcon#read 3, iclass 11, count 0 2006.173.13:00:16.80#ibcon#about to read 4, iclass 11, count 0 2006.173.13:00:16.80#ibcon#read 4, iclass 11, count 0 2006.173.13:00:16.80#ibcon#about to read 5, iclass 11, count 0 2006.173.13:00:16.80#ibcon#read 5, iclass 11, count 0 2006.173.13:00:16.80#ibcon#about to read 6, iclass 11, count 0 2006.173.13:00:16.80#ibcon#read 6, iclass 11, count 0 2006.173.13:00:16.80#ibcon#end of sib2, iclass 11, count 0 2006.173.13:00:16.80#ibcon#*after write, iclass 11, count 0 2006.173.13:00:16.80#ibcon#*before return 0, iclass 11, count 0 2006.173.13:00:16.80#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.13:00:16.80#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.13:00:16.80#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.13:00:16.80#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.13:00:16.80$vck44/vblo=4,679.99 2006.173.13:00:16.80#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.13:00:16.80#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.13:00:16.80#ibcon#ireg 17 cls_cnt 0 2006.173.13:00:16.80#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.13:00:16.80#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.13:00:16.80#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.13:00:16.80#ibcon#enter wrdev, iclass 13, count 0 2006.173.13:00:16.80#ibcon#first serial, iclass 13, count 0 2006.173.13:00:16.80#ibcon#enter sib2, iclass 13, count 0 2006.173.13:00:16.80#ibcon#flushed, iclass 13, count 0 2006.173.13:00:16.80#ibcon#about to write, iclass 13, count 0 2006.173.13:00:16.80#ibcon#wrote, iclass 13, count 0 2006.173.13:00:16.80#ibcon#about to read 3, iclass 13, count 0 2006.173.13:00:16.82#ibcon#read 3, iclass 13, count 0 2006.173.13:00:16.82#ibcon#about to read 4, iclass 13, count 0 2006.173.13:00:16.82#ibcon#read 4, iclass 13, count 0 2006.173.13:00:16.82#ibcon#about to read 5, iclass 13, count 0 2006.173.13:00:16.82#ibcon#read 5, iclass 13, count 0 2006.173.13:00:16.82#ibcon#about to read 6, iclass 13, count 0 2006.173.13:00:16.82#ibcon#read 6, iclass 13, count 0 2006.173.13:00:16.82#ibcon#end of sib2, iclass 13, count 0 2006.173.13:00:16.82#ibcon#*mode == 0, iclass 13, count 0 2006.173.13:00:16.82#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.13:00:16.82#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.13:00:16.82#ibcon#*before write, iclass 13, count 0 2006.173.13:00:16.82#ibcon#enter sib2, iclass 13, count 0 2006.173.13:00:16.82#ibcon#flushed, iclass 13, count 0 2006.173.13:00:16.82#ibcon#about to write, iclass 13, count 0 2006.173.13:00:16.82#ibcon#wrote, iclass 13, count 0 2006.173.13:00:16.82#ibcon#about to read 3, iclass 13, count 0 2006.173.13:00:16.86#ibcon#read 3, iclass 13, count 0 2006.173.13:00:16.86#ibcon#about to read 4, iclass 13, count 0 2006.173.13:00:16.86#ibcon#read 4, iclass 13, count 0 2006.173.13:00:16.86#ibcon#about to read 5, iclass 13, count 0 2006.173.13:00:16.86#ibcon#read 5, iclass 13, count 0 2006.173.13:00:16.86#ibcon#about to read 6, iclass 13, count 0 2006.173.13:00:16.86#ibcon#read 6, iclass 13, count 0 2006.173.13:00:16.86#ibcon#end of sib2, iclass 13, count 0 2006.173.13:00:16.86#ibcon#*after write, iclass 13, count 0 2006.173.13:00:16.86#ibcon#*before return 0, iclass 13, count 0 2006.173.13:00:16.86#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.13:00:16.86#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.13:00:16.86#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.13:00:16.86#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.13:00:16.86$vck44/vb=4,4 2006.173.13:00:16.86#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.13:00:16.86#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.13:00:16.86#ibcon#ireg 11 cls_cnt 2 2006.173.13:00:16.86#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.13:00:16.92#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.13:00:16.92#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.13:00:16.92#ibcon#enter wrdev, iclass 15, count 2 2006.173.13:00:16.92#ibcon#first serial, iclass 15, count 2 2006.173.13:00:16.92#ibcon#enter sib2, iclass 15, count 2 2006.173.13:00:16.92#ibcon#flushed, iclass 15, count 2 2006.173.13:00:16.92#ibcon#about to write, iclass 15, count 2 2006.173.13:00:16.92#ibcon#wrote, iclass 15, count 2 2006.173.13:00:16.92#ibcon#about to read 3, iclass 15, count 2 2006.173.13:00:16.94#ibcon#read 3, iclass 15, count 2 2006.173.13:00:16.94#ibcon#about to read 4, iclass 15, count 2 2006.173.13:00:16.94#ibcon#read 4, iclass 15, count 2 2006.173.13:00:16.94#ibcon#about to read 5, iclass 15, count 2 2006.173.13:00:16.94#ibcon#read 5, iclass 15, count 2 2006.173.13:00:16.94#ibcon#about to read 6, iclass 15, count 2 2006.173.13:00:16.94#ibcon#read 6, iclass 15, count 2 2006.173.13:00:16.94#ibcon#end of sib2, iclass 15, count 2 2006.173.13:00:16.94#ibcon#*mode == 0, iclass 15, count 2 2006.173.13:00:16.94#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.13:00:16.94#ibcon#[27=AT04-04\r\n] 2006.173.13:00:16.94#ibcon#*before write, iclass 15, count 2 2006.173.13:00:16.94#ibcon#enter sib2, iclass 15, count 2 2006.173.13:00:16.94#ibcon#flushed, iclass 15, count 2 2006.173.13:00:16.94#ibcon#about to write, iclass 15, count 2 2006.173.13:00:16.94#ibcon#wrote, iclass 15, count 2 2006.173.13:00:16.94#ibcon#about to read 3, iclass 15, count 2 2006.173.13:00:16.97#ibcon#read 3, iclass 15, count 2 2006.173.13:00:16.97#ibcon#about to read 4, iclass 15, count 2 2006.173.13:00:16.97#ibcon#read 4, iclass 15, count 2 2006.173.13:00:16.97#ibcon#about to read 5, iclass 15, count 2 2006.173.13:00:16.97#ibcon#read 5, iclass 15, count 2 2006.173.13:00:16.97#ibcon#about to read 6, iclass 15, count 2 2006.173.13:00:16.97#ibcon#read 6, iclass 15, count 2 2006.173.13:00:16.97#ibcon#end of sib2, iclass 15, count 2 2006.173.13:00:16.97#ibcon#*after write, iclass 15, count 2 2006.173.13:00:16.97#ibcon#*before return 0, iclass 15, count 2 2006.173.13:00:16.97#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.13:00:16.97#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.13:00:16.97#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.13:00:16.97#ibcon#ireg 7 cls_cnt 0 2006.173.13:00:16.97#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.13:00:17.09#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.13:00:17.09#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.13:00:17.09#ibcon#enter wrdev, iclass 15, count 0 2006.173.13:00:17.09#ibcon#first serial, iclass 15, count 0 2006.173.13:00:17.09#ibcon#enter sib2, iclass 15, count 0 2006.173.13:00:17.09#ibcon#flushed, iclass 15, count 0 2006.173.13:00:17.09#ibcon#about to write, iclass 15, count 0 2006.173.13:00:17.09#ibcon#wrote, iclass 15, count 0 2006.173.13:00:17.09#ibcon#about to read 3, iclass 15, count 0 2006.173.13:00:17.11#ibcon#read 3, iclass 15, count 0 2006.173.13:00:17.11#ibcon#about to read 4, iclass 15, count 0 2006.173.13:00:17.11#ibcon#read 4, iclass 15, count 0 2006.173.13:00:17.11#ibcon#about to read 5, iclass 15, count 0 2006.173.13:00:17.11#ibcon#read 5, iclass 15, count 0 2006.173.13:00:17.11#ibcon#about to read 6, iclass 15, count 0 2006.173.13:00:17.11#ibcon#read 6, iclass 15, count 0 2006.173.13:00:17.11#ibcon#end of sib2, iclass 15, count 0 2006.173.13:00:17.11#ibcon#*mode == 0, iclass 15, count 0 2006.173.13:00:17.11#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.13:00:17.11#ibcon#[27=USB\r\n] 2006.173.13:00:17.11#ibcon#*before write, iclass 15, count 0 2006.173.13:00:17.11#ibcon#enter sib2, iclass 15, count 0 2006.173.13:00:17.11#ibcon#flushed, iclass 15, count 0 2006.173.13:00:17.11#ibcon#about to write, iclass 15, count 0 2006.173.13:00:17.11#ibcon#wrote, iclass 15, count 0 2006.173.13:00:17.11#ibcon#about to read 3, iclass 15, count 0 2006.173.13:00:17.14#ibcon#read 3, iclass 15, count 0 2006.173.13:00:17.14#ibcon#about to read 4, iclass 15, count 0 2006.173.13:00:17.14#ibcon#read 4, iclass 15, count 0 2006.173.13:00:17.14#ibcon#about to read 5, iclass 15, count 0 2006.173.13:00:17.14#ibcon#read 5, iclass 15, count 0 2006.173.13:00:17.14#ibcon#about to read 6, iclass 15, count 0 2006.173.13:00:17.14#ibcon#read 6, iclass 15, count 0 2006.173.13:00:17.14#ibcon#end of sib2, iclass 15, count 0 2006.173.13:00:17.14#ibcon#*after write, iclass 15, count 0 2006.173.13:00:17.14#ibcon#*before return 0, iclass 15, count 0 2006.173.13:00:17.14#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.13:00:17.14#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.13:00:17.14#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.13:00:17.14#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.13:00:17.14$vck44/vblo=5,709.99 2006.173.13:00:17.14#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.13:00:17.14#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.13:00:17.14#ibcon#ireg 17 cls_cnt 0 2006.173.13:00:17.14#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.13:00:17.14#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.13:00:17.14#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.13:00:17.14#ibcon#enter wrdev, iclass 17, count 0 2006.173.13:00:17.14#ibcon#first serial, iclass 17, count 0 2006.173.13:00:17.14#ibcon#enter sib2, iclass 17, count 0 2006.173.13:00:17.14#ibcon#flushed, iclass 17, count 0 2006.173.13:00:17.14#ibcon#about to write, iclass 17, count 0 2006.173.13:00:17.14#ibcon#wrote, iclass 17, count 0 2006.173.13:00:17.14#ibcon#about to read 3, iclass 17, count 0 2006.173.13:00:17.16#ibcon#read 3, iclass 17, count 0 2006.173.13:00:17.16#ibcon#about to read 4, iclass 17, count 0 2006.173.13:00:17.16#ibcon#read 4, iclass 17, count 0 2006.173.13:00:17.16#ibcon#about to read 5, iclass 17, count 0 2006.173.13:00:17.16#ibcon#read 5, iclass 17, count 0 2006.173.13:00:17.16#ibcon#about to read 6, iclass 17, count 0 2006.173.13:00:17.16#ibcon#read 6, iclass 17, count 0 2006.173.13:00:17.16#ibcon#end of sib2, iclass 17, count 0 2006.173.13:00:17.16#ibcon#*mode == 0, iclass 17, count 0 2006.173.13:00:17.16#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.13:00:17.16#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.13:00:17.16#ibcon#*before write, iclass 17, count 0 2006.173.13:00:17.16#ibcon#enter sib2, iclass 17, count 0 2006.173.13:00:17.16#ibcon#flushed, iclass 17, count 0 2006.173.13:00:17.16#ibcon#about to write, iclass 17, count 0 2006.173.13:00:17.16#ibcon#wrote, iclass 17, count 0 2006.173.13:00:17.16#ibcon#about to read 3, iclass 17, count 0 2006.173.13:00:17.20#ibcon#read 3, iclass 17, count 0 2006.173.13:00:17.20#ibcon#about to read 4, iclass 17, count 0 2006.173.13:00:17.20#ibcon#read 4, iclass 17, count 0 2006.173.13:00:17.20#ibcon#about to read 5, iclass 17, count 0 2006.173.13:00:17.20#ibcon#read 5, iclass 17, count 0 2006.173.13:00:17.20#ibcon#about to read 6, iclass 17, count 0 2006.173.13:00:17.20#ibcon#read 6, iclass 17, count 0 2006.173.13:00:17.20#ibcon#end of sib2, iclass 17, count 0 2006.173.13:00:17.20#ibcon#*after write, iclass 17, count 0 2006.173.13:00:17.20#ibcon#*before return 0, iclass 17, count 0 2006.173.13:00:17.20#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.13:00:17.20#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.13:00:17.20#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.13:00:17.20#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.13:00:17.20$vck44/vb=5,4 2006.173.13:00:17.20#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.13:00:17.20#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.13:00:17.20#ibcon#ireg 11 cls_cnt 2 2006.173.13:00:17.20#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.13:00:17.26#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.13:00:17.26#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.13:00:17.26#ibcon#enter wrdev, iclass 19, count 2 2006.173.13:00:17.26#ibcon#first serial, iclass 19, count 2 2006.173.13:00:17.26#ibcon#enter sib2, iclass 19, count 2 2006.173.13:00:17.26#ibcon#flushed, iclass 19, count 2 2006.173.13:00:17.26#ibcon#about to write, iclass 19, count 2 2006.173.13:00:17.26#ibcon#wrote, iclass 19, count 2 2006.173.13:00:17.26#ibcon#about to read 3, iclass 19, count 2 2006.173.13:00:17.28#ibcon#read 3, iclass 19, count 2 2006.173.13:00:17.28#ibcon#about to read 4, iclass 19, count 2 2006.173.13:00:17.28#ibcon#read 4, iclass 19, count 2 2006.173.13:00:17.28#ibcon#about to read 5, iclass 19, count 2 2006.173.13:00:17.28#ibcon#read 5, iclass 19, count 2 2006.173.13:00:17.28#ibcon#about to read 6, iclass 19, count 2 2006.173.13:00:17.28#ibcon#read 6, iclass 19, count 2 2006.173.13:00:17.28#ibcon#end of sib2, iclass 19, count 2 2006.173.13:00:17.28#ibcon#*mode == 0, iclass 19, count 2 2006.173.13:00:17.28#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.13:00:17.28#ibcon#[27=AT05-04\r\n] 2006.173.13:00:17.28#ibcon#*before write, iclass 19, count 2 2006.173.13:00:17.28#ibcon#enter sib2, iclass 19, count 2 2006.173.13:00:17.28#ibcon#flushed, iclass 19, count 2 2006.173.13:00:17.28#ibcon#about to write, iclass 19, count 2 2006.173.13:00:17.28#ibcon#wrote, iclass 19, count 2 2006.173.13:00:17.28#ibcon#about to read 3, iclass 19, count 2 2006.173.13:00:17.31#ibcon#read 3, iclass 19, count 2 2006.173.13:00:17.31#ibcon#about to read 4, iclass 19, count 2 2006.173.13:00:17.31#ibcon#read 4, iclass 19, count 2 2006.173.13:00:17.31#ibcon#about to read 5, iclass 19, count 2 2006.173.13:00:17.31#ibcon#read 5, iclass 19, count 2 2006.173.13:00:17.31#ibcon#about to read 6, iclass 19, count 2 2006.173.13:00:17.31#ibcon#read 6, iclass 19, count 2 2006.173.13:00:17.31#ibcon#end of sib2, iclass 19, count 2 2006.173.13:00:17.31#ibcon#*after write, iclass 19, count 2 2006.173.13:00:17.31#ibcon#*before return 0, iclass 19, count 2 2006.173.13:00:17.31#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.13:00:17.31#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.13:00:17.31#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.13:00:17.31#ibcon#ireg 7 cls_cnt 0 2006.173.13:00:17.31#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.13:00:17.43#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.13:00:17.43#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.13:00:17.43#ibcon#enter wrdev, iclass 19, count 0 2006.173.13:00:17.43#ibcon#first serial, iclass 19, count 0 2006.173.13:00:17.43#ibcon#enter sib2, iclass 19, count 0 2006.173.13:00:17.43#ibcon#flushed, iclass 19, count 0 2006.173.13:00:17.43#ibcon#about to write, iclass 19, count 0 2006.173.13:00:17.43#ibcon#wrote, iclass 19, count 0 2006.173.13:00:17.43#ibcon#about to read 3, iclass 19, count 0 2006.173.13:00:17.45#ibcon#read 3, iclass 19, count 0 2006.173.13:00:17.45#ibcon#about to read 4, iclass 19, count 0 2006.173.13:00:17.45#ibcon#read 4, iclass 19, count 0 2006.173.13:00:17.45#ibcon#about to read 5, iclass 19, count 0 2006.173.13:00:17.45#ibcon#read 5, iclass 19, count 0 2006.173.13:00:17.45#ibcon#about to read 6, iclass 19, count 0 2006.173.13:00:17.45#ibcon#read 6, iclass 19, count 0 2006.173.13:00:17.45#ibcon#end of sib2, iclass 19, count 0 2006.173.13:00:17.45#ibcon#*mode == 0, iclass 19, count 0 2006.173.13:00:17.45#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.13:00:17.45#ibcon#[27=USB\r\n] 2006.173.13:00:17.45#ibcon#*before write, iclass 19, count 0 2006.173.13:00:17.45#ibcon#enter sib2, iclass 19, count 0 2006.173.13:00:17.45#ibcon#flushed, iclass 19, count 0 2006.173.13:00:17.45#ibcon#about to write, iclass 19, count 0 2006.173.13:00:17.45#ibcon#wrote, iclass 19, count 0 2006.173.13:00:17.45#ibcon#about to read 3, iclass 19, count 0 2006.173.13:00:17.48#ibcon#read 3, iclass 19, count 0 2006.173.13:00:17.48#ibcon#about to read 4, iclass 19, count 0 2006.173.13:00:17.48#ibcon#read 4, iclass 19, count 0 2006.173.13:00:17.48#ibcon#about to read 5, iclass 19, count 0 2006.173.13:00:17.48#ibcon#read 5, iclass 19, count 0 2006.173.13:00:17.48#ibcon#about to read 6, iclass 19, count 0 2006.173.13:00:17.48#ibcon#read 6, iclass 19, count 0 2006.173.13:00:17.48#ibcon#end of sib2, iclass 19, count 0 2006.173.13:00:17.48#ibcon#*after write, iclass 19, count 0 2006.173.13:00:17.48#ibcon#*before return 0, iclass 19, count 0 2006.173.13:00:17.48#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.13:00:17.48#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.13:00:17.48#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.13:00:17.48#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.13:00:17.48$vck44/vblo=6,719.99 2006.173.13:00:17.48#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.13:00:17.48#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.13:00:17.48#ibcon#ireg 17 cls_cnt 0 2006.173.13:00:17.48#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.13:00:17.48#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.13:00:17.48#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.13:00:17.48#ibcon#enter wrdev, iclass 21, count 0 2006.173.13:00:17.48#ibcon#first serial, iclass 21, count 0 2006.173.13:00:17.48#ibcon#enter sib2, iclass 21, count 0 2006.173.13:00:17.48#ibcon#flushed, iclass 21, count 0 2006.173.13:00:17.48#ibcon#about to write, iclass 21, count 0 2006.173.13:00:17.48#ibcon#wrote, iclass 21, count 0 2006.173.13:00:17.48#ibcon#about to read 3, iclass 21, count 0 2006.173.13:00:17.50#ibcon#read 3, iclass 21, count 0 2006.173.13:00:17.50#ibcon#about to read 4, iclass 21, count 0 2006.173.13:00:17.50#ibcon#read 4, iclass 21, count 0 2006.173.13:00:17.50#ibcon#about to read 5, iclass 21, count 0 2006.173.13:00:17.50#ibcon#read 5, iclass 21, count 0 2006.173.13:00:17.50#ibcon#about to read 6, iclass 21, count 0 2006.173.13:00:17.50#ibcon#read 6, iclass 21, count 0 2006.173.13:00:17.50#ibcon#end of sib2, iclass 21, count 0 2006.173.13:00:17.50#ibcon#*mode == 0, iclass 21, count 0 2006.173.13:00:17.50#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.13:00:17.50#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.13:00:17.50#ibcon#*before write, iclass 21, count 0 2006.173.13:00:17.50#ibcon#enter sib2, iclass 21, count 0 2006.173.13:00:17.50#ibcon#flushed, iclass 21, count 0 2006.173.13:00:17.50#ibcon#about to write, iclass 21, count 0 2006.173.13:00:17.50#ibcon#wrote, iclass 21, count 0 2006.173.13:00:17.50#ibcon#about to read 3, iclass 21, count 0 2006.173.13:00:17.54#ibcon#read 3, iclass 21, count 0 2006.173.13:00:17.54#ibcon#about to read 4, iclass 21, count 0 2006.173.13:00:17.54#ibcon#read 4, iclass 21, count 0 2006.173.13:00:17.54#ibcon#about to read 5, iclass 21, count 0 2006.173.13:00:17.54#ibcon#read 5, iclass 21, count 0 2006.173.13:00:17.54#ibcon#about to read 6, iclass 21, count 0 2006.173.13:00:17.54#ibcon#read 6, iclass 21, count 0 2006.173.13:00:17.54#ibcon#end of sib2, iclass 21, count 0 2006.173.13:00:17.54#ibcon#*after write, iclass 21, count 0 2006.173.13:00:17.54#ibcon#*before return 0, iclass 21, count 0 2006.173.13:00:17.54#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.13:00:17.54#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.13:00:17.54#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.13:00:17.54#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.13:00:17.54$vck44/vb=6,4 2006.173.13:00:17.54#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.13:00:17.54#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.13:00:17.54#ibcon#ireg 11 cls_cnt 2 2006.173.13:00:17.54#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.13:00:17.60#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.13:00:17.60#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.13:00:17.60#ibcon#enter wrdev, iclass 23, count 2 2006.173.13:00:17.60#ibcon#first serial, iclass 23, count 2 2006.173.13:00:17.60#ibcon#enter sib2, iclass 23, count 2 2006.173.13:00:17.60#ibcon#flushed, iclass 23, count 2 2006.173.13:00:17.60#ibcon#about to write, iclass 23, count 2 2006.173.13:00:17.60#ibcon#wrote, iclass 23, count 2 2006.173.13:00:17.60#ibcon#about to read 3, iclass 23, count 2 2006.173.13:00:17.62#ibcon#read 3, iclass 23, count 2 2006.173.13:00:17.62#ibcon#about to read 4, iclass 23, count 2 2006.173.13:00:17.62#ibcon#read 4, iclass 23, count 2 2006.173.13:00:17.62#ibcon#about to read 5, iclass 23, count 2 2006.173.13:00:17.62#ibcon#read 5, iclass 23, count 2 2006.173.13:00:17.62#ibcon#about to read 6, iclass 23, count 2 2006.173.13:00:17.62#ibcon#read 6, iclass 23, count 2 2006.173.13:00:17.62#ibcon#end of sib2, iclass 23, count 2 2006.173.13:00:17.62#ibcon#*mode == 0, iclass 23, count 2 2006.173.13:00:17.62#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.13:00:17.62#ibcon#[27=AT06-04\r\n] 2006.173.13:00:17.62#ibcon#*before write, iclass 23, count 2 2006.173.13:00:17.62#ibcon#enter sib2, iclass 23, count 2 2006.173.13:00:17.62#ibcon#flushed, iclass 23, count 2 2006.173.13:00:17.62#ibcon#about to write, iclass 23, count 2 2006.173.13:00:17.62#ibcon#wrote, iclass 23, count 2 2006.173.13:00:17.62#ibcon#about to read 3, iclass 23, count 2 2006.173.13:00:17.65#ibcon#read 3, iclass 23, count 2 2006.173.13:00:17.65#ibcon#about to read 4, iclass 23, count 2 2006.173.13:00:17.65#ibcon#read 4, iclass 23, count 2 2006.173.13:00:17.65#ibcon#about to read 5, iclass 23, count 2 2006.173.13:00:17.65#ibcon#read 5, iclass 23, count 2 2006.173.13:00:17.65#ibcon#about to read 6, iclass 23, count 2 2006.173.13:00:17.65#ibcon#read 6, iclass 23, count 2 2006.173.13:00:17.65#ibcon#end of sib2, iclass 23, count 2 2006.173.13:00:17.65#ibcon#*after write, iclass 23, count 2 2006.173.13:00:17.65#ibcon#*before return 0, iclass 23, count 2 2006.173.13:00:17.65#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.13:00:17.65#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.13:00:17.65#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.13:00:17.65#ibcon#ireg 7 cls_cnt 0 2006.173.13:00:17.65#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.13:00:17.77#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.13:00:17.77#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.13:00:17.77#ibcon#enter wrdev, iclass 23, count 0 2006.173.13:00:17.77#ibcon#first serial, iclass 23, count 0 2006.173.13:00:17.77#ibcon#enter sib2, iclass 23, count 0 2006.173.13:00:17.77#ibcon#flushed, iclass 23, count 0 2006.173.13:00:17.77#ibcon#about to write, iclass 23, count 0 2006.173.13:00:17.77#ibcon#wrote, iclass 23, count 0 2006.173.13:00:17.77#ibcon#about to read 3, iclass 23, count 0 2006.173.13:00:17.79#ibcon#read 3, iclass 23, count 0 2006.173.13:00:17.79#ibcon#about to read 4, iclass 23, count 0 2006.173.13:00:17.79#ibcon#read 4, iclass 23, count 0 2006.173.13:00:17.79#ibcon#about to read 5, iclass 23, count 0 2006.173.13:00:17.79#ibcon#read 5, iclass 23, count 0 2006.173.13:00:17.79#ibcon#about to read 6, iclass 23, count 0 2006.173.13:00:17.79#ibcon#read 6, iclass 23, count 0 2006.173.13:00:17.79#ibcon#end of sib2, iclass 23, count 0 2006.173.13:00:17.79#ibcon#*mode == 0, iclass 23, count 0 2006.173.13:00:17.79#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.13:00:17.79#ibcon#[27=USB\r\n] 2006.173.13:00:17.79#ibcon#*before write, iclass 23, count 0 2006.173.13:00:17.79#ibcon#enter sib2, iclass 23, count 0 2006.173.13:00:17.79#ibcon#flushed, iclass 23, count 0 2006.173.13:00:17.79#ibcon#about to write, iclass 23, count 0 2006.173.13:00:17.79#ibcon#wrote, iclass 23, count 0 2006.173.13:00:17.79#ibcon#about to read 3, iclass 23, count 0 2006.173.13:00:17.82#ibcon#read 3, iclass 23, count 0 2006.173.13:00:17.82#ibcon#about to read 4, iclass 23, count 0 2006.173.13:00:17.82#ibcon#read 4, iclass 23, count 0 2006.173.13:00:17.82#ibcon#about to read 5, iclass 23, count 0 2006.173.13:00:17.82#ibcon#read 5, iclass 23, count 0 2006.173.13:00:17.82#ibcon#about to read 6, iclass 23, count 0 2006.173.13:00:17.82#ibcon#read 6, iclass 23, count 0 2006.173.13:00:17.82#ibcon#end of sib2, iclass 23, count 0 2006.173.13:00:17.82#ibcon#*after write, iclass 23, count 0 2006.173.13:00:17.82#ibcon#*before return 0, iclass 23, count 0 2006.173.13:00:17.82#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.13:00:17.82#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.13:00:17.82#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.13:00:17.82#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.13:00:17.82$vck44/vblo=7,734.99 2006.173.13:00:17.82#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.13:00:17.82#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.13:00:17.82#ibcon#ireg 17 cls_cnt 0 2006.173.13:00:17.82#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.13:00:17.82#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.13:00:17.82#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.13:00:17.82#ibcon#enter wrdev, iclass 25, count 0 2006.173.13:00:17.82#ibcon#first serial, iclass 25, count 0 2006.173.13:00:17.82#ibcon#enter sib2, iclass 25, count 0 2006.173.13:00:17.82#ibcon#flushed, iclass 25, count 0 2006.173.13:00:17.82#ibcon#about to write, iclass 25, count 0 2006.173.13:00:17.82#ibcon#wrote, iclass 25, count 0 2006.173.13:00:17.82#ibcon#about to read 3, iclass 25, count 0 2006.173.13:00:17.84#ibcon#read 3, iclass 25, count 0 2006.173.13:00:17.84#ibcon#about to read 4, iclass 25, count 0 2006.173.13:00:17.84#ibcon#read 4, iclass 25, count 0 2006.173.13:00:17.84#ibcon#about to read 5, iclass 25, count 0 2006.173.13:00:17.84#ibcon#read 5, iclass 25, count 0 2006.173.13:00:17.84#ibcon#about to read 6, iclass 25, count 0 2006.173.13:00:17.84#ibcon#read 6, iclass 25, count 0 2006.173.13:00:17.84#ibcon#end of sib2, iclass 25, count 0 2006.173.13:00:17.84#ibcon#*mode == 0, iclass 25, count 0 2006.173.13:00:17.84#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.13:00:17.84#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.13:00:17.84#ibcon#*before write, iclass 25, count 0 2006.173.13:00:17.84#ibcon#enter sib2, iclass 25, count 0 2006.173.13:00:17.84#ibcon#flushed, iclass 25, count 0 2006.173.13:00:17.84#ibcon#about to write, iclass 25, count 0 2006.173.13:00:17.84#ibcon#wrote, iclass 25, count 0 2006.173.13:00:17.84#ibcon#about to read 3, iclass 25, count 0 2006.173.13:00:17.88#ibcon#read 3, iclass 25, count 0 2006.173.13:00:17.88#ibcon#about to read 4, iclass 25, count 0 2006.173.13:00:17.88#ibcon#read 4, iclass 25, count 0 2006.173.13:00:17.88#ibcon#about to read 5, iclass 25, count 0 2006.173.13:00:17.88#ibcon#read 5, iclass 25, count 0 2006.173.13:00:17.88#ibcon#about to read 6, iclass 25, count 0 2006.173.13:00:17.88#ibcon#read 6, iclass 25, count 0 2006.173.13:00:17.88#ibcon#end of sib2, iclass 25, count 0 2006.173.13:00:17.88#ibcon#*after write, iclass 25, count 0 2006.173.13:00:17.88#ibcon#*before return 0, iclass 25, count 0 2006.173.13:00:17.88#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.13:00:17.88#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.13:00:17.88#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.13:00:17.88#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.13:00:17.88$vck44/vb=7,4 2006.173.13:00:17.88#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.13:00:17.88#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.13:00:17.88#ibcon#ireg 11 cls_cnt 2 2006.173.13:00:17.88#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.13:00:17.94#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.13:00:17.94#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.13:00:17.94#ibcon#enter wrdev, iclass 27, count 2 2006.173.13:00:17.94#ibcon#first serial, iclass 27, count 2 2006.173.13:00:17.94#ibcon#enter sib2, iclass 27, count 2 2006.173.13:00:17.94#ibcon#flushed, iclass 27, count 2 2006.173.13:00:17.94#ibcon#about to write, iclass 27, count 2 2006.173.13:00:17.94#ibcon#wrote, iclass 27, count 2 2006.173.13:00:17.94#ibcon#about to read 3, iclass 27, count 2 2006.173.13:00:17.96#ibcon#read 3, iclass 27, count 2 2006.173.13:00:17.96#ibcon#about to read 4, iclass 27, count 2 2006.173.13:00:17.96#ibcon#read 4, iclass 27, count 2 2006.173.13:00:17.96#ibcon#about to read 5, iclass 27, count 2 2006.173.13:00:17.96#ibcon#read 5, iclass 27, count 2 2006.173.13:00:17.96#ibcon#about to read 6, iclass 27, count 2 2006.173.13:00:17.96#ibcon#read 6, iclass 27, count 2 2006.173.13:00:17.96#ibcon#end of sib2, iclass 27, count 2 2006.173.13:00:17.96#ibcon#*mode == 0, iclass 27, count 2 2006.173.13:00:17.96#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.13:00:17.96#ibcon#[27=AT07-04\r\n] 2006.173.13:00:17.96#ibcon#*before write, iclass 27, count 2 2006.173.13:00:17.96#ibcon#enter sib2, iclass 27, count 2 2006.173.13:00:17.96#ibcon#flushed, iclass 27, count 2 2006.173.13:00:17.96#ibcon#about to write, iclass 27, count 2 2006.173.13:00:17.96#ibcon#wrote, iclass 27, count 2 2006.173.13:00:17.96#ibcon#about to read 3, iclass 27, count 2 2006.173.13:00:17.99#ibcon#read 3, iclass 27, count 2 2006.173.13:00:17.99#ibcon#about to read 4, iclass 27, count 2 2006.173.13:00:17.99#ibcon#read 4, iclass 27, count 2 2006.173.13:00:17.99#ibcon#about to read 5, iclass 27, count 2 2006.173.13:00:17.99#ibcon#read 5, iclass 27, count 2 2006.173.13:00:17.99#ibcon#about to read 6, iclass 27, count 2 2006.173.13:00:17.99#ibcon#read 6, iclass 27, count 2 2006.173.13:00:17.99#ibcon#end of sib2, iclass 27, count 2 2006.173.13:00:17.99#ibcon#*after write, iclass 27, count 2 2006.173.13:00:17.99#ibcon#*before return 0, iclass 27, count 2 2006.173.13:00:17.99#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.13:00:17.99#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.13:00:17.99#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.13:00:17.99#ibcon#ireg 7 cls_cnt 0 2006.173.13:00:17.99#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.13:00:18.11#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.13:00:18.11#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.13:00:18.11#ibcon#enter wrdev, iclass 27, count 0 2006.173.13:00:18.11#ibcon#first serial, iclass 27, count 0 2006.173.13:00:18.11#ibcon#enter sib2, iclass 27, count 0 2006.173.13:00:18.11#ibcon#flushed, iclass 27, count 0 2006.173.13:00:18.11#ibcon#about to write, iclass 27, count 0 2006.173.13:00:18.11#ibcon#wrote, iclass 27, count 0 2006.173.13:00:18.11#ibcon#about to read 3, iclass 27, count 0 2006.173.13:00:18.13#ibcon#read 3, iclass 27, count 0 2006.173.13:00:18.13#ibcon#about to read 4, iclass 27, count 0 2006.173.13:00:18.13#ibcon#read 4, iclass 27, count 0 2006.173.13:00:18.13#ibcon#about to read 5, iclass 27, count 0 2006.173.13:00:18.13#ibcon#read 5, iclass 27, count 0 2006.173.13:00:18.13#ibcon#about to read 6, iclass 27, count 0 2006.173.13:00:18.13#ibcon#read 6, iclass 27, count 0 2006.173.13:00:18.13#ibcon#end of sib2, iclass 27, count 0 2006.173.13:00:18.13#ibcon#*mode == 0, iclass 27, count 0 2006.173.13:00:18.13#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.13:00:18.13#ibcon#[27=USB\r\n] 2006.173.13:00:18.13#ibcon#*before write, iclass 27, count 0 2006.173.13:00:18.13#ibcon#enter sib2, iclass 27, count 0 2006.173.13:00:18.13#ibcon#flushed, iclass 27, count 0 2006.173.13:00:18.13#ibcon#about to write, iclass 27, count 0 2006.173.13:00:18.13#ibcon#wrote, iclass 27, count 0 2006.173.13:00:18.13#ibcon#about to read 3, iclass 27, count 0 2006.173.13:00:18.16#ibcon#read 3, iclass 27, count 0 2006.173.13:00:18.16#ibcon#about to read 4, iclass 27, count 0 2006.173.13:00:18.16#ibcon#read 4, iclass 27, count 0 2006.173.13:00:18.16#ibcon#about to read 5, iclass 27, count 0 2006.173.13:00:18.16#ibcon#read 5, iclass 27, count 0 2006.173.13:00:18.16#ibcon#about to read 6, iclass 27, count 0 2006.173.13:00:18.16#ibcon#read 6, iclass 27, count 0 2006.173.13:00:18.16#ibcon#end of sib2, iclass 27, count 0 2006.173.13:00:18.16#ibcon#*after write, iclass 27, count 0 2006.173.13:00:18.16#ibcon#*before return 0, iclass 27, count 0 2006.173.13:00:18.16#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.13:00:18.16#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.13:00:18.16#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.13:00:18.16#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.13:00:18.16$vck44/vblo=8,744.99 2006.173.13:00:18.16#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.13:00:18.16#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.13:00:18.16#ibcon#ireg 17 cls_cnt 0 2006.173.13:00:18.16#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.13:00:18.16#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.13:00:18.16#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.13:00:18.16#ibcon#enter wrdev, iclass 29, count 0 2006.173.13:00:18.16#ibcon#first serial, iclass 29, count 0 2006.173.13:00:18.16#ibcon#enter sib2, iclass 29, count 0 2006.173.13:00:18.16#ibcon#flushed, iclass 29, count 0 2006.173.13:00:18.16#ibcon#about to write, iclass 29, count 0 2006.173.13:00:18.16#ibcon#wrote, iclass 29, count 0 2006.173.13:00:18.16#ibcon#about to read 3, iclass 29, count 0 2006.173.13:00:18.18#ibcon#read 3, iclass 29, count 0 2006.173.13:00:18.18#ibcon#about to read 4, iclass 29, count 0 2006.173.13:00:18.18#ibcon#read 4, iclass 29, count 0 2006.173.13:00:18.18#ibcon#about to read 5, iclass 29, count 0 2006.173.13:00:18.18#ibcon#read 5, iclass 29, count 0 2006.173.13:00:18.18#ibcon#about to read 6, iclass 29, count 0 2006.173.13:00:18.18#ibcon#read 6, iclass 29, count 0 2006.173.13:00:18.18#ibcon#end of sib2, iclass 29, count 0 2006.173.13:00:18.18#ibcon#*mode == 0, iclass 29, count 0 2006.173.13:00:18.18#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.13:00:18.18#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.13:00:18.18#ibcon#*before write, iclass 29, count 0 2006.173.13:00:18.18#ibcon#enter sib2, iclass 29, count 0 2006.173.13:00:18.18#ibcon#flushed, iclass 29, count 0 2006.173.13:00:18.18#ibcon#about to write, iclass 29, count 0 2006.173.13:00:18.18#ibcon#wrote, iclass 29, count 0 2006.173.13:00:18.18#ibcon#about to read 3, iclass 29, count 0 2006.173.13:00:18.22#ibcon#read 3, iclass 29, count 0 2006.173.13:00:18.22#ibcon#about to read 4, iclass 29, count 0 2006.173.13:00:18.22#ibcon#read 4, iclass 29, count 0 2006.173.13:00:18.22#ibcon#about to read 5, iclass 29, count 0 2006.173.13:00:18.22#ibcon#read 5, iclass 29, count 0 2006.173.13:00:18.22#ibcon#about to read 6, iclass 29, count 0 2006.173.13:00:18.22#ibcon#read 6, iclass 29, count 0 2006.173.13:00:18.22#ibcon#end of sib2, iclass 29, count 0 2006.173.13:00:18.22#ibcon#*after write, iclass 29, count 0 2006.173.13:00:18.22#ibcon#*before return 0, iclass 29, count 0 2006.173.13:00:18.22#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.13:00:18.22#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.13:00:18.22#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.13:00:18.22#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.13:00:18.22$vck44/vb=8,4 2006.173.13:00:18.22#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.13:00:18.22#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.13:00:18.22#ibcon#ireg 11 cls_cnt 2 2006.173.13:00:18.22#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.13:00:18.28#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.13:00:18.28#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.13:00:18.28#ibcon#enter wrdev, iclass 31, count 2 2006.173.13:00:18.28#ibcon#first serial, iclass 31, count 2 2006.173.13:00:18.28#ibcon#enter sib2, iclass 31, count 2 2006.173.13:00:18.28#ibcon#flushed, iclass 31, count 2 2006.173.13:00:18.28#ibcon#about to write, iclass 31, count 2 2006.173.13:00:18.28#ibcon#wrote, iclass 31, count 2 2006.173.13:00:18.28#ibcon#about to read 3, iclass 31, count 2 2006.173.13:00:18.30#ibcon#read 3, iclass 31, count 2 2006.173.13:00:18.30#ibcon#about to read 4, iclass 31, count 2 2006.173.13:00:18.30#ibcon#read 4, iclass 31, count 2 2006.173.13:00:18.30#ibcon#about to read 5, iclass 31, count 2 2006.173.13:00:18.30#ibcon#read 5, iclass 31, count 2 2006.173.13:00:18.30#ibcon#about to read 6, iclass 31, count 2 2006.173.13:00:18.30#ibcon#read 6, iclass 31, count 2 2006.173.13:00:18.30#ibcon#end of sib2, iclass 31, count 2 2006.173.13:00:18.30#ibcon#*mode == 0, iclass 31, count 2 2006.173.13:00:18.30#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.13:00:18.30#ibcon#[27=AT08-04\r\n] 2006.173.13:00:18.30#ibcon#*before write, iclass 31, count 2 2006.173.13:00:18.30#ibcon#enter sib2, iclass 31, count 2 2006.173.13:00:18.30#ibcon#flushed, iclass 31, count 2 2006.173.13:00:18.30#ibcon#about to write, iclass 31, count 2 2006.173.13:00:18.30#ibcon#wrote, iclass 31, count 2 2006.173.13:00:18.30#ibcon#about to read 3, iclass 31, count 2 2006.173.13:00:18.33#ibcon#read 3, iclass 31, count 2 2006.173.13:00:18.33#ibcon#about to read 4, iclass 31, count 2 2006.173.13:00:18.33#ibcon#read 4, iclass 31, count 2 2006.173.13:00:18.33#ibcon#about to read 5, iclass 31, count 2 2006.173.13:00:18.33#ibcon#read 5, iclass 31, count 2 2006.173.13:00:18.33#ibcon#about to read 6, iclass 31, count 2 2006.173.13:00:18.33#ibcon#read 6, iclass 31, count 2 2006.173.13:00:18.33#ibcon#end of sib2, iclass 31, count 2 2006.173.13:00:18.33#ibcon#*after write, iclass 31, count 2 2006.173.13:00:18.33#ibcon#*before return 0, iclass 31, count 2 2006.173.13:00:18.33#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.13:00:18.33#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.13:00:18.33#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.13:00:18.33#ibcon#ireg 7 cls_cnt 0 2006.173.13:00:18.33#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.13:00:18.45#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.13:00:18.45#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.13:00:18.45#ibcon#enter wrdev, iclass 31, count 0 2006.173.13:00:18.45#ibcon#first serial, iclass 31, count 0 2006.173.13:00:18.45#ibcon#enter sib2, iclass 31, count 0 2006.173.13:00:18.45#ibcon#flushed, iclass 31, count 0 2006.173.13:00:18.45#ibcon#about to write, iclass 31, count 0 2006.173.13:00:18.45#ibcon#wrote, iclass 31, count 0 2006.173.13:00:18.45#ibcon#about to read 3, iclass 31, count 0 2006.173.13:00:18.47#ibcon#read 3, iclass 31, count 0 2006.173.13:00:18.47#ibcon#about to read 4, iclass 31, count 0 2006.173.13:00:18.47#ibcon#read 4, iclass 31, count 0 2006.173.13:00:18.47#ibcon#about to read 5, iclass 31, count 0 2006.173.13:00:18.47#ibcon#read 5, iclass 31, count 0 2006.173.13:00:18.47#ibcon#about to read 6, iclass 31, count 0 2006.173.13:00:18.47#ibcon#read 6, iclass 31, count 0 2006.173.13:00:18.47#ibcon#end of sib2, iclass 31, count 0 2006.173.13:00:18.47#ibcon#*mode == 0, iclass 31, count 0 2006.173.13:00:18.47#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.13:00:18.47#ibcon#[27=USB\r\n] 2006.173.13:00:18.47#ibcon#*before write, iclass 31, count 0 2006.173.13:00:18.47#ibcon#enter sib2, iclass 31, count 0 2006.173.13:00:18.47#ibcon#flushed, iclass 31, count 0 2006.173.13:00:18.47#ibcon#about to write, iclass 31, count 0 2006.173.13:00:18.47#ibcon#wrote, iclass 31, count 0 2006.173.13:00:18.47#ibcon#about to read 3, iclass 31, count 0 2006.173.13:00:18.50#ibcon#read 3, iclass 31, count 0 2006.173.13:00:18.50#ibcon#about to read 4, iclass 31, count 0 2006.173.13:00:18.50#ibcon#read 4, iclass 31, count 0 2006.173.13:00:18.50#ibcon#about to read 5, iclass 31, count 0 2006.173.13:00:18.50#ibcon#read 5, iclass 31, count 0 2006.173.13:00:18.50#ibcon#about to read 6, iclass 31, count 0 2006.173.13:00:18.50#ibcon#read 6, iclass 31, count 0 2006.173.13:00:18.50#ibcon#end of sib2, iclass 31, count 0 2006.173.13:00:18.50#ibcon#*after write, iclass 31, count 0 2006.173.13:00:18.50#ibcon#*before return 0, iclass 31, count 0 2006.173.13:00:18.50#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.13:00:18.50#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.13:00:18.50#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.13:00:18.50#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.13:00:18.50$vck44/vabw=wide 2006.173.13:00:18.50#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.13:00:18.50#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.13:00:18.50#ibcon#ireg 8 cls_cnt 0 2006.173.13:00:18.50#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.13:00:18.50#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.13:00:18.50#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.13:00:18.50#ibcon#enter wrdev, iclass 33, count 0 2006.173.13:00:18.50#ibcon#first serial, iclass 33, count 0 2006.173.13:00:18.50#ibcon#enter sib2, iclass 33, count 0 2006.173.13:00:18.50#ibcon#flushed, iclass 33, count 0 2006.173.13:00:18.50#ibcon#about to write, iclass 33, count 0 2006.173.13:00:18.50#ibcon#wrote, iclass 33, count 0 2006.173.13:00:18.50#ibcon#about to read 3, iclass 33, count 0 2006.173.13:00:18.52#ibcon#read 3, iclass 33, count 0 2006.173.13:00:18.52#ibcon#about to read 4, iclass 33, count 0 2006.173.13:00:18.52#ibcon#read 4, iclass 33, count 0 2006.173.13:00:18.52#ibcon#about to read 5, iclass 33, count 0 2006.173.13:00:18.52#ibcon#read 5, iclass 33, count 0 2006.173.13:00:18.52#ibcon#about to read 6, iclass 33, count 0 2006.173.13:00:18.52#ibcon#read 6, iclass 33, count 0 2006.173.13:00:18.52#ibcon#end of sib2, iclass 33, count 0 2006.173.13:00:18.52#ibcon#*mode == 0, iclass 33, count 0 2006.173.13:00:18.52#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.13:00:18.52#ibcon#[25=BW32\r\n] 2006.173.13:00:18.52#ibcon#*before write, iclass 33, count 0 2006.173.13:00:18.52#ibcon#enter sib2, iclass 33, count 0 2006.173.13:00:18.52#ibcon#flushed, iclass 33, count 0 2006.173.13:00:18.52#ibcon#about to write, iclass 33, count 0 2006.173.13:00:18.52#ibcon#wrote, iclass 33, count 0 2006.173.13:00:18.52#ibcon#about to read 3, iclass 33, count 0 2006.173.13:00:18.55#ibcon#read 3, iclass 33, count 0 2006.173.13:00:18.55#ibcon#about to read 4, iclass 33, count 0 2006.173.13:00:18.55#ibcon#read 4, iclass 33, count 0 2006.173.13:00:18.55#ibcon#about to read 5, iclass 33, count 0 2006.173.13:00:18.55#ibcon#read 5, iclass 33, count 0 2006.173.13:00:18.55#ibcon#about to read 6, iclass 33, count 0 2006.173.13:00:18.55#ibcon#read 6, iclass 33, count 0 2006.173.13:00:18.55#ibcon#end of sib2, iclass 33, count 0 2006.173.13:00:18.55#ibcon#*after write, iclass 33, count 0 2006.173.13:00:18.55#ibcon#*before return 0, iclass 33, count 0 2006.173.13:00:18.55#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.13:00:18.55#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.13:00:18.55#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.13:00:18.55#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.13:00:18.55$vck44/vbbw=wide 2006.173.13:00:18.55#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.13:00:18.55#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.13:00:18.55#ibcon#ireg 8 cls_cnt 0 2006.173.13:00:18.55#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.13:00:18.62#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.13:00:18.62#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.13:00:18.62#ibcon#enter wrdev, iclass 35, count 0 2006.173.13:00:18.62#ibcon#first serial, iclass 35, count 0 2006.173.13:00:18.62#ibcon#enter sib2, iclass 35, count 0 2006.173.13:00:18.62#ibcon#flushed, iclass 35, count 0 2006.173.13:00:18.62#ibcon#about to write, iclass 35, count 0 2006.173.13:00:18.62#ibcon#wrote, iclass 35, count 0 2006.173.13:00:18.62#ibcon#about to read 3, iclass 35, count 0 2006.173.13:00:18.64#ibcon#read 3, iclass 35, count 0 2006.173.13:00:18.64#ibcon#about to read 4, iclass 35, count 0 2006.173.13:00:18.64#ibcon#read 4, iclass 35, count 0 2006.173.13:00:18.64#ibcon#about to read 5, iclass 35, count 0 2006.173.13:00:18.64#ibcon#read 5, iclass 35, count 0 2006.173.13:00:18.64#ibcon#about to read 6, iclass 35, count 0 2006.173.13:00:18.64#ibcon#read 6, iclass 35, count 0 2006.173.13:00:18.64#ibcon#end of sib2, iclass 35, count 0 2006.173.13:00:18.64#ibcon#*mode == 0, iclass 35, count 0 2006.173.13:00:18.64#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.13:00:18.64#ibcon#[27=BW32\r\n] 2006.173.13:00:18.64#ibcon#*before write, iclass 35, count 0 2006.173.13:00:18.64#ibcon#enter sib2, iclass 35, count 0 2006.173.13:00:18.64#ibcon#flushed, iclass 35, count 0 2006.173.13:00:18.64#ibcon#about to write, iclass 35, count 0 2006.173.13:00:18.64#ibcon#wrote, iclass 35, count 0 2006.173.13:00:18.64#ibcon#about to read 3, iclass 35, count 0 2006.173.13:00:18.67#ibcon#read 3, iclass 35, count 0 2006.173.13:00:18.67#ibcon#about to read 4, iclass 35, count 0 2006.173.13:00:18.67#ibcon#read 4, iclass 35, count 0 2006.173.13:00:18.67#ibcon#about to read 5, iclass 35, count 0 2006.173.13:00:18.67#ibcon#read 5, iclass 35, count 0 2006.173.13:00:18.67#ibcon#about to read 6, iclass 35, count 0 2006.173.13:00:18.67#ibcon#read 6, iclass 35, count 0 2006.173.13:00:18.67#ibcon#end of sib2, iclass 35, count 0 2006.173.13:00:18.67#ibcon#*after write, iclass 35, count 0 2006.173.13:00:18.67#ibcon#*before return 0, iclass 35, count 0 2006.173.13:00:18.67#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.13:00:18.67#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.13:00:18.67#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.13:00:18.67#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.13:00:18.67$setupk4/ifdk4 2006.173.13:00:18.67$ifdk4/lo= 2006.173.13:00:18.67$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.13:00:18.67$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.13:00:18.67$ifdk4/patch= 2006.173.13:00:18.67$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.13:00:18.67$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.13:00:18.68$setupk4/!*+20s 2006.173.13:00:25.81#abcon#<5=/04 1.1 2.1 22.16 961004.3\r\n> 2006.173.13:00:25.83#abcon#{5=INTERFACE CLEAR} 2006.173.13:00:25.89#abcon#[5=S1D000X0/0*\r\n] 2006.173.13:00:33.20$setupk4/"tpicd 2006.173.13:00:33.20$setupk4/echo=off 2006.173.13:00:33.20$setupk4/xlog=off 2006.173.13:00:33.20:!2006.173.13:05:34 2006.173.13:01:00.14#trakl#Source acquired 2006.173.13:01:00.14#flagr#flagr/antenna,acquired 2006.173.13:05:34.00:preob 2006.173.13:05:34.14/onsource/TRACKING 2006.173.13:05:34.14:!2006.173.13:05:44 2006.173.13:05:44.00:"tape 2006.173.13:05:44.00:"st=record 2006.173.13:05:44.00:data_valid=on 2006.173.13:05:44.00:midob 2006.173.13:05:45.14/onsource/TRACKING 2006.173.13:05:45.14/wx/22.16,1004.2,97 2006.173.13:05:45.21/cable/+6.5051E-03 2006.173.13:05:46.30/va/01,07,usb,yes,45,48 2006.173.13:05:46.30/va/02,06,usb,yes,44,45 2006.173.13:05:46.30/va/03,05,usb,yes,56,58 2006.173.13:05:46.30/va/04,06,usb,yes,46,48 2006.173.13:05:46.30/va/05,04,usb,yes,36,37 2006.173.13:05:46.30/va/06,03,usb,yes,50,50 2006.173.13:05:46.30/va/07,04,usb,yes,41,42 2006.173.13:05:46.30/va/08,04,usb,yes,35,42 2006.173.13:05:46.53/valo/01,524.99,yes,locked 2006.173.13:05:46.53/valo/02,534.99,yes,locked 2006.173.13:05:46.53/valo/03,564.99,yes,locked 2006.173.13:05:46.53/valo/04,624.99,yes,locked 2006.173.13:05:46.53/valo/05,734.99,yes,locked 2006.173.13:05:46.53/valo/06,814.99,yes,locked 2006.173.13:05:46.53/valo/07,864.99,yes,locked 2006.173.13:05:46.53/valo/08,884.99,yes,locked 2006.173.13:05:47.62/vb/01,04,usb,yes,30,28 2006.173.13:05:47.62/vb/02,04,usb,yes,33,32 2006.173.13:05:47.62/vb/03,04,usb,yes,29,32 2006.173.13:05:47.62/vb/04,04,usb,yes,34,33 2006.173.13:05:47.62/vb/05,04,usb,yes,26,29 2006.173.13:05:47.62/vb/06,04,usb,yes,31,27 2006.173.13:05:47.62/vb/07,04,usb,yes,31,30 2006.173.13:05:47.62/vb/08,04,usb,yes,28,32 2006.173.13:05:47.85/vblo/01,629.99,yes,locked 2006.173.13:05:47.85/vblo/02,634.99,yes,locked 2006.173.13:05:47.85/vblo/03,649.99,yes,locked 2006.173.13:05:47.85/vblo/04,679.99,yes,locked 2006.173.13:05:47.85/vblo/05,709.99,yes,locked 2006.173.13:05:47.85/vblo/06,719.99,yes,locked 2006.173.13:05:47.85/vblo/07,734.99,yes,locked 2006.173.13:05:47.85/vblo/08,744.99,yes,locked 2006.173.13:05:48.00/vabw/8 2006.173.13:05:48.15/vbbw/8 2006.173.13:05:48.24/xfe/off,on,14.7 2006.173.13:05:48.63/ifatt/23,28,28,28 2006.173.13:05:49.08/fmout-gps/S +3.83E-07 2006.173.13:05:49.12:!2006.173.13:07:04 2006.173.13:07:04.01:data_valid=off 2006.173.13:07:04.02:"et 2006.173.13:07:04.02:!+3s 2006.173.13:07:07.03:"tape 2006.173.13:07:07.04:postob 2006.173.13:07:07.09/cable/+6.5036E-03 2006.173.13:07:07.10/wx/22.14,1004.1,97 2006.173.13:07:07.15/fmout-gps/S +3.83E-07 2006.173.13:07:07.16:scan_name=173-1310,jd0606,40 2006.173.13:07:07.16:source=1424-418,142756.30,-420619.4,2000.0,cw 2006.173.13:07:08.14#flagr#flagr/antenna,new-source 2006.173.13:07:08.15:checkk5 2006.173.13:07:08.56/chk_autoobs//k5ts1/ autoobs is running! 2006.173.13:07:08.94/chk_autoobs//k5ts2/ autoobs is running! 2006.173.13:07:09.35/chk_autoobs//k5ts3/ autoobs is running! 2006.173.13:07:09.75/chk_autoobs//k5ts4/ autoobs is running! 2006.173.13:07:10.14/chk_obsdata//k5ts1/T1731305??a.dat file size is correct (nominal:320MB, actual:316MB). 2006.173.13:07:10.55/chk_obsdata//k5ts2/T1731305??b.dat file size is correct (nominal:320MB, actual:316MB). 2006.173.13:07:10.93/chk_obsdata//k5ts3/T1731305??c.dat file size is correct (nominal:320MB, actual:316MB). 2006.173.13:07:11.33/chk_obsdata//k5ts4/T1731305??d.dat file size is correct (nominal:320MB, actual:316MB). 2006.173.13:07:12.05/k5log//k5ts1_log_newline 2006.173.13:07:12.76/k5log//k5ts2_log_newline 2006.173.13:07:13.45/k5log//k5ts3_log_newline 2006.173.13:07:14.16/k5log//k5ts4_log_newline 2006.173.13:07:14.19/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.13:07:14.19:setupk4=1 2006.173.13:07:14.19$setupk4/echo=on 2006.173.13:07:14.19$setupk4/pcalon 2006.173.13:07:14.19$pcalon/"no phase cal control is implemented here 2006.173.13:07:14.19$setupk4/"tpicd=stop 2006.173.13:07:14.19$setupk4/"rec=synch_on 2006.173.13:07:14.19$setupk4/"rec_mode=128 2006.173.13:07:14.19$setupk4/!* 2006.173.13:07:14.19$setupk4/recpk4 2006.173.13:07:14.19$recpk4/recpatch= 2006.173.13:07:14.19$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.13:07:14.19$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.13:07:14.19$setupk4/vck44 2006.173.13:07:14.19$vck44/valo=1,524.99 2006.173.13:07:14.19#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.13:07:14.19#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.13:07:14.19#ibcon#ireg 17 cls_cnt 0 2006.173.13:07:14.19#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.13:07:14.19#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.13:07:14.19#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.13:07:14.19#ibcon#enter wrdev, iclass 15, count 0 2006.173.13:07:14.19#ibcon#first serial, iclass 15, count 0 2006.173.13:07:14.19#ibcon#enter sib2, iclass 15, count 0 2006.173.13:07:14.19#ibcon#flushed, iclass 15, count 0 2006.173.13:07:14.19#ibcon#about to write, iclass 15, count 0 2006.173.13:07:14.19#ibcon#wrote, iclass 15, count 0 2006.173.13:07:14.19#ibcon#about to read 3, iclass 15, count 0 2006.173.13:07:14.20#ibcon#read 3, iclass 15, count 0 2006.173.13:07:14.20#ibcon#about to read 4, iclass 15, count 0 2006.173.13:07:14.20#ibcon#read 4, iclass 15, count 0 2006.173.13:07:14.20#ibcon#about to read 5, iclass 15, count 0 2006.173.13:07:14.20#ibcon#read 5, iclass 15, count 0 2006.173.13:07:14.20#ibcon#about to read 6, iclass 15, count 0 2006.173.13:07:14.20#ibcon#read 6, iclass 15, count 0 2006.173.13:07:14.20#ibcon#end of sib2, iclass 15, count 0 2006.173.13:07:14.20#ibcon#*mode == 0, iclass 15, count 0 2006.173.13:07:14.20#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.13:07:14.20#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.13:07:14.20#ibcon#*before write, iclass 15, count 0 2006.173.13:07:14.20#ibcon#enter sib2, iclass 15, count 0 2006.173.13:07:14.20#ibcon#flushed, iclass 15, count 0 2006.173.13:07:14.20#ibcon#about to write, iclass 15, count 0 2006.173.13:07:14.20#ibcon#wrote, iclass 15, count 0 2006.173.13:07:14.20#ibcon#about to read 3, iclass 15, count 0 2006.173.13:07:14.25#ibcon#read 3, iclass 15, count 0 2006.173.13:07:14.25#ibcon#about to read 4, iclass 15, count 0 2006.173.13:07:14.25#ibcon#read 4, iclass 15, count 0 2006.173.13:07:14.25#ibcon#about to read 5, iclass 15, count 0 2006.173.13:07:14.25#ibcon#read 5, iclass 15, count 0 2006.173.13:07:14.25#ibcon#about to read 6, iclass 15, count 0 2006.173.13:07:14.25#ibcon#read 6, iclass 15, count 0 2006.173.13:07:14.25#ibcon#end of sib2, iclass 15, count 0 2006.173.13:07:14.25#ibcon#*after write, iclass 15, count 0 2006.173.13:07:14.25#ibcon#*before return 0, iclass 15, count 0 2006.173.13:07:14.25#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.13:07:14.25#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.13:07:14.25#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.13:07:14.25#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.13:07:14.25$vck44/va=1,7 2006.173.13:07:14.25#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.13:07:14.25#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.13:07:14.25#ibcon#ireg 11 cls_cnt 2 2006.173.13:07:14.25#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.13:07:14.25#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.13:07:14.25#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.13:07:14.25#ibcon#enter wrdev, iclass 17, count 2 2006.173.13:07:14.25#ibcon#first serial, iclass 17, count 2 2006.173.13:07:14.25#ibcon#enter sib2, iclass 17, count 2 2006.173.13:07:14.25#ibcon#flushed, iclass 17, count 2 2006.173.13:07:14.25#ibcon#about to write, iclass 17, count 2 2006.173.13:07:14.25#ibcon#wrote, iclass 17, count 2 2006.173.13:07:14.25#ibcon#about to read 3, iclass 17, count 2 2006.173.13:07:14.27#ibcon#read 3, iclass 17, count 2 2006.173.13:07:14.27#ibcon#about to read 4, iclass 17, count 2 2006.173.13:07:14.27#ibcon#read 4, iclass 17, count 2 2006.173.13:07:14.27#ibcon#about to read 5, iclass 17, count 2 2006.173.13:07:14.27#ibcon#read 5, iclass 17, count 2 2006.173.13:07:14.27#ibcon#about to read 6, iclass 17, count 2 2006.173.13:07:14.27#ibcon#read 6, iclass 17, count 2 2006.173.13:07:14.27#ibcon#end of sib2, iclass 17, count 2 2006.173.13:07:14.27#ibcon#*mode == 0, iclass 17, count 2 2006.173.13:07:14.27#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.13:07:14.27#ibcon#[25=AT01-07\r\n] 2006.173.13:07:14.27#ibcon#*before write, iclass 17, count 2 2006.173.13:07:14.27#ibcon#enter sib2, iclass 17, count 2 2006.173.13:07:14.27#ibcon#flushed, iclass 17, count 2 2006.173.13:07:14.27#ibcon#about to write, iclass 17, count 2 2006.173.13:07:14.27#ibcon#wrote, iclass 17, count 2 2006.173.13:07:14.27#ibcon#about to read 3, iclass 17, count 2 2006.173.13:07:14.30#ibcon#read 3, iclass 17, count 2 2006.173.13:07:14.30#ibcon#about to read 4, iclass 17, count 2 2006.173.13:07:14.30#ibcon#read 4, iclass 17, count 2 2006.173.13:07:14.30#ibcon#about to read 5, iclass 17, count 2 2006.173.13:07:14.30#ibcon#read 5, iclass 17, count 2 2006.173.13:07:14.30#ibcon#about to read 6, iclass 17, count 2 2006.173.13:07:14.30#ibcon#read 6, iclass 17, count 2 2006.173.13:07:14.30#ibcon#end of sib2, iclass 17, count 2 2006.173.13:07:14.30#ibcon#*after write, iclass 17, count 2 2006.173.13:07:14.30#ibcon#*before return 0, iclass 17, count 2 2006.173.13:07:14.30#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.13:07:14.30#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.13:07:14.30#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.13:07:14.30#ibcon#ireg 7 cls_cnt 0 2006.173.13:07:14.30#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.13:07:14.42#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.13:07:14.42#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.13:07:14.42#ibcon#enter wrdev, iclass 17, count 0 2006.173.13:07:14.42#ibcon#first serial, iclass 17, count 0 2006.173.13:07:14.42#ibcon#enter sib2, iclass 17, count 0 2006.173.13:07:14.42#ibcon#flushed, iclass 17, count 0 2006.173.13:07:14.42#ibcon#about to write, iclass 17, count 0 2006.173.13:07:14.42#ibcon#wrote, iclass 17, count 0 2006.173.13:07:14.42#ibcon#about to read 3, iclass 17, count 0 2006.173.13:07:14.44#ibcon#read 3, iclass 17, count 0 2006.173.13:07:14.44#ibcon#about to read 4, iclass 17, count 0 2006.173.13:07:14.44#ibcon#read 4, iclass 17, count 0 2006.173.13:07:14.44#ibcon#about to read 5, iclass 17, count 0 2006.173.13:07:14.44#ibcon#read 5, iclass 17, count 0 2006.173.13:07:14.44#ibcon#about to read 6, iclass 17, count 0 2006.173.13:07:14.44#ibcon#read 6, iclass 17, count 0 2006.173.13:07:14.44#ibcon#end of sib2, iclass 17, count 0 2006.173.13:07:14.44#ibcon#*mode == 0, iclass 17, count 0 2006.173.13:07:14.44#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.13:07:14.44#ibcon#[25=USB\r\n] 2006.173.13:07:14.44#ibcon#*before write, iclass 17, count 0 2006.173.13:07:14.44#ibcon#enter sib2, iclass 17, count 0 2006.173.13:07:14.44#ibcon#flushed, iclass 17, count 0 2006.173.13:07:14.44#ibcon#about to write, iclass 17, count 0 2006.173.13:07:14.44#ibcon#wrote, iclass 17, count 0 2006.173.13:07:14.44#ibcon#about to read 3, iclass 17, count 0 2006.173.13:07:14.47#ibcon#read 3, iclass 17, count 0 2006.173.13:07:14.47#ibcon#about to read 4, iclass 17, count 0 2006.173.13:07:14.47#ibcon#read 4, iclass 17, count 0 2006.173.13:07:14.47#ibcon#about to read 5, iclass 17, count 0 2006.173.13:07:14.47#ibcon#read 5, iclass 17, count 0 2006.173.13:07:14.47#ibcon#about to read 6, iclass 17, count 0 2006.173.13:07:14.47#ibcon#read 6, iclass 17, count 0 2006.173.13:07:14.47#ibcon#end of sib2, iclass 17, count 0 2006.173.13:07:14.47#ibcon#*after write, iclass 17, count 0 2006.173.13:07:14.47#ibcon#*before return 0, iclass 17, count 0 2006.173.13:07:14.47#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.13:07:14.47#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.13:07:14.47#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.13:07:14.47#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.13:07:14.47$vck44/valo=2,534.99 2006.173.13:07:14.47#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.13:07:14.47#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.13:07:14.47#ibcon#ireg 17 cls_cnt 0 2006.173.13:07:14.47#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.13:07:14.47#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.13:07:14.47#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.13:07:14.47#ibcon#enter wrdev, iclass 19, count 0 2006.173.13:07:14.47#ibcon#first serial, iclass 19, count 0 2006.173.13:07:14.47#ibcon#enter sib2, iclass 19, count 0 2006.173.13:07:14.47#ibcon#flushed, iclass 19, count 0 2006.173.13:07:14.47#ibcon#about to write, iclass 19, count 0 2006.173.13:07:14.47#ibcon#wrote, iclass 19, count 0 2006.173.13:07:14.47#ibcon#about to read 3, iclass 19, count 0 2006.173.13:07:14.49#ibcon#read 3, iclass 19, count 0 2006.173.13:07:14.49#ibcon#about to read 4, iclass 19, count 0 2006.173.13:07:14.49#ibcon#read 4, iclass 19, count 0 2006.173.13:07:14.49#ibcon#about to read 5, iclass 19, count 0 2006.173.13:07:14.49#ibcon#read 5, iclass 19, count 0 2006.173.13:07:14.49#ibcon#about to read 6, iclass 19, count 0 2006.173.13:07:14.49#ibcon#read 6, iclass 19, count 0 2006.173.13:07:14.49#ibcon#end of sib2, iclass 19, count 0 2006.173.13:07:14.49#ibcon#*mode == 0, iclass 19, count 0 2006.173.13:07:14.49#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.13:07:14.49#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.13:07:14.49#ibcon#*before write, iclass 19, count 0 2006.173.13:07:14.49#ibcon#enter sib2, iclass 19, count 0 2006.173.13:07:14.49#ibcon#flushed, iclass 19, count 0 2006.173.13:07:14.49#ibcon#about to write, iclass 19, count 0 2006.173.13:07:14.49#ibcon#wrote, iclass 19, count 0 2006.173.13:07:14.49#ibcon#about to read 3, iclass 19, count 0 2006.173.13:07:14.53#ibcon#read 3, iclass 19, count 0 2006.173.13:07:14.53#ibcon#about to read 4, iclass 19, count 0 2006.173.13:07:14.53#ibcon#read 4, iclass 19, count 0 2006.173.13:07:14.53#ibcon#about to read 5, iclass 19, count 0 2006.173.13:07:14.53#ibcon#read 5, iclass 19, count 0 2006.173.13:07:14.53#ibcon#about to read 6, iclass 19, count 0 2006.173.13:07:14.53#ibcon#read 6, iclass 19, count 0 2006.173.13:07:14.53#ibcon#end of sib2, iclass 19, count 0 2006.173.13:07:14.53#ibcon#*after write, iclass 19, count 0 2006.173.13:07:14.53#ibcon#*before return 0, iclass 19, count 0 2006.173.13:07:14.53#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.13:07:14.53#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.13:07:14.53#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.13:07:14.53#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.13:07:14.53$vck44/va=2,6 2006.173.13:07:14.53#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.13:07:14.53#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.13:07:14.53#ibcon#ireg 11 cls_cnt 2 2006.173.13:07:14.53#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.13:07:14.59#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.13:07:14.59#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.13:07:14.59#ibcon#enter wrdev, iclass 21, count 2 2006.173.13:07:14.59#ibcon#first serial, iclass 21, count 2 2006.173.13:07:14.59#ibcon#enter sib2, iclass 21, count 2 2006.173.13:07:14.59#ibcon#flushed, iclass 21, count 2 2006.173.13:07:14.59#ibcon#about to write, iclass 21, count 2 2006.173.13:07:14.59#ibcon#wrote, iclass 21, count 2 2006.173.13:07:14.59#ibcon#about to read 3, iclass 21, count 2 2006.173.13:07:14.61#ibcon#read 3, iclass 21, count 2 2006.173.13:07:14.61#ibcon#about to read 4, iclass 21, count 2 2006.173.13:07:14.61#ibcon#read 4, iclass 21, count 2 2006.173.13:07:14.61#ibcon#about to read 5, iclass 21, count 2 2006.173.13:07:14.61#ibcon#read 5, iclass 21, count 2 2006.173.13:07:14.61#ibcon#about to read 6, iclass 21, count 2 2006.173.13:07:14.61#ibcon#read 6, iclass 21, count 2 2006.173.13:07:14.61#ibcon#end of sib2, iclass 21, count 2 2006.173.13:07:14.61#ibcon#*mode == 0, iclass 21, count 2 2006.173.13:07:14.61#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.13:07:14.61#ibcon#[25=AT02-06\r\n] 2006.173.13:07:14.61#ibcon#*before write, iclass 21, count 2 2006.173.13:07:14.61#ibcon#enter sib2, iclass 21, count 2 2006.173.13:07:14.61#ibcon#flushed, iclass 21, count 2 2006.173.13:07:14.61#ibcon#about to write, iclass 21, count 2 2006.173.13:07:14.61#ibcon#wrote, iclass 21, count 2 2006.173.13:07:14.61#ibcon#about to read 3, iclass 21, count 2 2006.173.13:07:14.64#ibcon#read 3, iclass 21, count 2 2006.173.13:07:14.64#ibcon#about to read 4, iclass 21, count 2 2006.173.13:07:14.64#ibcon#read 4, iclass 21, count 2 2006.173.13:07:14.64#ibcon#about to read 5, iclass 21, count 2 2006.173.13:07:14.64#ibcon#read 5, iclass 21, count 2 2006.173.13:07:14.64#ibcon#about to read 6, iclass 21, count 2 2006.173.13:07:14.64#ibcon#read 6, iclass 21, count 2 2006.173.13:07:14.64#ibcon#end of sib2, iclass 21, count 2 2006.173.13:07:14.64#ibcon#*after write, iclass 21, count 2 2006.173.13:07:14.64#ibcon#*before return 0, iclass 21, count 2 2006.173.13:07:14.64#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.13:07:14.64#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.13:07:14.64#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.13:07:14.64#ibcon#ireg 7 cls_cnt 0 2006.173.13:07:14.64#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.13:07:14.76#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.13:07:14.76#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.13:07:14.76#ibcon#enter wrdev, iclass 21, count 0 2006.173.13:07:14.76#ibcon#first serial, iclass 21, count 0 2006.173.13:07:14.76#ibcon#enter sib2, iclass 21, count 0 2006.173.13:07:14.76#ibcon#flushed, iclass 21, count 0 2006.173.13:07:14.76#ibcon#about to write, iclass 21, count 0 2006.173.13:07:14.76#ibcon#wrote, iclass 21, count 0 2006.173.13:07:14.76#ibcon#about to read 3, iclass 21, count 0 2006.173.13:07:14.78#ibcon#read 3, iclass 21, count 0 2006.173.13:07:14.78#ibcon#about to read 4, iclass 21, count 0 2006.173.13:07:14.78#ibcon#read 4, iclass 21, count 0 2006.173.13:07:14.78#ibcon#about to read 5, iclass 21, count 0 2006.173.13:07:14.78#ibcon#read 5, iclass 21, count 0 2006.173.13:07:14.78#ibcon#about to read 6, iclass 21, count 0 2006.173.13:07:14.78#ibcon#read 6, iclass 21, count 0 2006.173.13:07:14.78#ibcon#end of sib2, iclass 21, count 0 2006.173.13:07:14.78#ibcon#*mode == 0, iclass 21, count 0 2006.173.13:07:14.78#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.13:07:14.78#ibcon#[25=USB\r\n] 2006.173.13:07:14.78#ibcon#*before write, iclass 21, count 0 2006.173.13:07:14.78#ibcon#enter sib2, iclass 21, count 0 2006.173.13:07:14.78#ibcon#flushed, iclass 21, count 0 2006.173.13:07:14.78#ibcon#about to write, iclass 21, count 0 2006.173.13:07:14.78#ibcon#wrote, iclass 21, count 0 2006.173.13:07:14.78#ibcon#about to read 3, iclass 21, count 0 2006.173.13:07:14.81#ibcon#read 3, iclass 21, count 0 2006.173.13:07:14.81#ibcon#about to read 4, iclass 21, count 0 2006.173.13:07:14.81#ibcon#read 4, iclass 21, count 0 2006.173.13:07:14.81#ibcon#about to read 5, iclass 21, count 0 2006.173.13:07:14.81#ibcon#read 5, iclass 21, count 0 2006.173.13:07:14.81#ibcon#about to read 6, iclass 21, count 0 2006.173.13:07:14.81#ibcon#read 6, iclass 21, count 0 2006.173.13:07:14.81#ibcon#end of sib2, iclass 21, count 0 2006.173.13:07:14.81#ibcon#*after write, iclass 21, count 0 2006.173.13:07:14.81#ibcon#*before return 0, iclass 21, count 0 2006.173.13:07:14.81#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.13:07:14.81#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.13:07:14.81#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.13:07:14.81#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.13:07:14.81$vck44/valo=3,564.99 2006.173.13:07:14.81#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.13:07:14.81#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.13:07:14.81#ibcon#ireg 17 cls_cnt 0 2006.173.13:07:14.81#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.13:07:14.81#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.13:07:14.81#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.13:07:14.81#ibcon#enter wrdev, iclass 23, count 0 2006.173.13:07:14.81#ibcon#first serial, iclass 23, count 0 2006.173.13:07:14.81#ibcon#enter sib2, iclass 23, count 0 2006.173.13:07:14.81#ibcon#flushed, iclass 23, count 0 2006.173.13:07:14.81#ibcon#about to write, iclass 23, count 0 2006.173.13:07:14.81#ibcon#wrote, iclass 23, count 0 2006.173.13:07:14.81#ibcon#about to read 3, iclass 23, count 0 2006.173.13:07:14.83#ibcon#read 3, iclass 23, count 0 2006.173.13:07:14.83#ibcon#about to read 4, iclass 23, count 0 2006.173.13:07:14.83#ibcon#read 4, iclass 23, count 0 2006.173.13:07:14.83#ibcon#about to read 5, iclass 23, count 0 2006.173.13:07:14.83#ibcon#read 5, iclass 23, count 0 2006.173.13:07:14.83#ibcon#about to read 6, iclass 23, count 0 2006.173.13:07:14.83#ibcon#read 6, iclass 23, count 0 2006.173.13:07:14.83#ibcon#end of sib2, iclass 23, count 0 2006.173.13:07:14.83#ibcon#*mode == 0, iclass 23, count 0 2006.173.13:07:14.83#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.13:07:14.83#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.13:07:14.83#ibcon#*before write, iclass 23, count 0 2006.173.13:07:14.83#ibcon#enter sib2, iclass 23, count 0 2006.173.13:07:14.83#ibcon#flushed, iclass 23, count 0 2006.173.13:07:14.83#ibcon#about to write, iclass 23, count 0 2006.173.13:07:14.83#ibcon#wrote, iclass 23, count 0 2006.173.13:07:14.83#ibcon#about to read 3, iclass 23, count 0 2006.173.13:07:14.87#ibcon#read 3, iclass 23, count 0 2006.173.13:07:14.87#ibcon#about to read 4, iclass 23, count 0 2006.173.13:07:14.87#ibcon#read 4, iclass 23, count 0 2006.173.13:07:14.87#ibcon#about to read 5, iclass 23, count 0 2006.173.13:07:14.87#ibcon#read 5, iclass 23, count 0 2006.173.13:07:14.87#ibcon#about to read 6, iclass 23, count 0 2006.173.13:07:14.87#ibcon#read 6, iclass 23, count 0 2006.173.13:07:14.87#ibcon#end of sib2, iclass 23, count 0 2006.173.13:07:14.87#ibcon#*after write, iclass 23, count 0 2006.173.13:07:14.87#ibcon#*before return 0, iclass 23, count 0 2006.173.13:07:14.87#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.13:07:14.87#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.13:07:14.87#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.13:07:14.87#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.13:07:14.87$vck44/va=3,5 2006.173.13:07:14.87#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.13:07:14.87#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.13:07:14.87#ibcon#ireg 11 cls_cnt 2 2006.173.13:07:14.87#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.13:07:14.93#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.13:07:14.93#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.13:07:14.93#ibcon#enter wrdev, iclass 25, count 2 2006.173.13:07:14.93#ibcon#first serial, iclass 25, count 2 2006.173.13:07:14.93#ibcon#enter sib2, iclass 25, count 2 2006.173.13:07:14.93#ibcon#flushed, iclass 25, count 2 2006.173.13:07:14.93#ibcon#about to write, iclass 25, count 2 2006.173.13:07:14.93#ibcon#wrote, iclass 25, count 2 2006.173.13:07:14.93#ibcon#about to read 3, iclass 25, count 2 2006.173.13:07:14.95#ibcon#read 3, iclass 25, count 2 2006.173.13:07:14.95#ibcon#about to read 4, iclass 25, count 2 2006.173.13:07:14.95#ibcon#read 4, iclass 25, count 2 2006.173.13:07:14.95#ibcon#about to read 5, iclass 25, count 2 2006.173.13:07:14.95#ibcon#read 5, iclass 25, count 2 2006.173.13:07:14.95#ibcon#about to read 6, iclass 25, count 2 2006.173.13:07:14.95#ibcon#read 6, iclass 25, count 2 2006.173.13:07:14.95#ibcon#end of sib2, iclass 25, count 2 2006.173.13:07:14.95#ibcon#*mode == 0, iclass 25, count 2 2006.173.13:07:14.95#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.13:07:14.95#ibcon#[25=AT03-05\r\n] 2006.173.13:07:14.95#ibcon#*before write, iclass 25, count 2 2006.173.13:07:14.95#ibcon#enter sib2, iclass 25, count 2 2006.173.13:07:14.95#ibcon#flushed, iclass 25, count 2 2006.173.13:07:14.95#ibcon#about to write, iclass 25, count 2 2006.173.13:07:14.95#ibcon#wrote, iclass 25, count 2 2006.173.13:07:14.95#ibcon#about to read 3, iclass 25, count 2 2006.173.13:07:14.98#ibcon#read 3, iclass 25, count 2 2006.173.13:07:14.98#ibcon#about to read 4, iclass 25, count 2 2006.173.13:07:14.98#ibcon#read 4, iclass 25, count 2 2006.173.13:07:14.98#ibcon#about to read 5, iclass 25, count 2 2006.173.13:07:14.98#ibcon#read 5, iclass 25, count 2 2006.173.13:07:14.98#ibcon#about to read 6, iclass 25, count 2 2006.173.13:07:14.98#ibcon#read 6, iclass 25, count 2 2006.173.13:07:14.98#ibcon#end of sib2, iclass 25, count 2 2006.173.13:07:14.98#ibcon#*after write, iclass 25, count 2 2006.173.13:07:14.98#ibcon#*before return 0, iclass 25, count 2 2006.173.13:07:14.98#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.13:07:14.98#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.13:07:14.98#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.13:07:14.98#ibcon#ireg 7 cls_cnt 0 2006.173.13:07:14.98#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.13:07:15.10#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.13:07:15.10#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.13:07:15.10#ibcon#enter wrdev, iclass 25, count 0 2006.173.13:07:15.10#ibcon#first serial, iclass 25, count 0 2006.173.13:07:15.10#ibcon#enter sib2, iclass 25, count 0 2006.173.13:07:15.10#ibcon#flushed, iclass 25, count 0 2006.173.13:07:15.10#ibcon#about to write, iclass 25, count 0 2006.173.13:07:15.10#ibcon#wrote, iclass 25, count 0 2006.173.13:07:15.10#ibcon#about to read 3, iclass 25, count 0 2006.173.13:07:15.12#ibcon#read 3, iclass 25, count 0 2006.173.13:07:15.12#ibcon#about to read 4, iclass 25, count 0 2006.173.13:07:15.12#ibcon#read 4, iclass 25, count 0 2006.173.13:07:15.12#ibcon#about to read 5, iclass 25, count 0 2006.173.13:07:15.12#ibcon#read 5, iclass 25, count 0 2006.173.13:07:15.12#ibcon#about to read 6, iclass 25, count 0 2006.173.13:07:15.12#ibcon#read 6, iclass 25, count 0 2006.173.13:07:15.12#ibcon#end of sib2, iclass 25, count 0 2006.173.13:07:15.12#ibcon#*mode == 0, iclass 25, count 0 2006.173.13:07:15.12#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.13:07:15.12#ibcon#[25=USB\r\n] 2006.173.13:07:15.12#ibcon#*before write, iclass 25, count 0 2006.173.13:07:15.12#ibcon#enter sib2, iclass 25, count 0 2006.173.13:07:15.12#ibcon#flushed, iclass 25, count 0 2006.173.13:07:15.12#ibcon#about to write, iclass 25, count 0 2006.173.13:07:15.12#ibcon#wrote, iclass 25, count 0 2006.173.13:07:15.12#ibcon#about to read 3, iclass 25, count 0 2006.173.13:07:15.15#ibcon#read 3, iclass 25, count 0 2006.173.13:07:15.15#ibcon#about to read 4, iclass 25, count 0 2006.173.13:07:15.15#ibcon#read 4, iclass 25, count 0 2006.173.13:07:15.15#ibcon#about to read 5, iclass 25, count 0 2006.173.13:07:15.15#ibcon#read 5, iclass 25, count 0 2006.173.13:07:15.15#ibcon#about to read 6, iclass 25, count 0 2006.173.13:07:15.15#ibcon#read 6, iclass 25, count 0 2006.173.13:07:15.15#ibcon#end of sib2, iclass 25, count 0 2006.173.13:07:15.15#ibcon#*after write, iclass 25, count 0 2006.173.13:07:15.15#ibcon#*before return 0, iclass 25, count 0 2006.173.13:07:15.15#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.13:07:15.15#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.13:07:15.15#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.13:07:15.15#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.13:07:15.15$vck44/valo=4,624.99 2006.173.13:07:15.15#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.13:07:15.15#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.13:07:15.15#ibcon#ireg 17 cls_cnt 0 2006.173.13:07:15.15#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.13:07:15.15#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.13:07:15.15#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.13:07:15.15#ibcon#enter wrdev, iclass 27, count 0 2006.173.13:07:15.15#ibcon#first serial, iclass 27, count 0 2006.173.13:07:15.15#ibcon#enter sib2, iclass 27, count 0 2006.173.13:07:15.15#ibcon#flushed, iclass 27, count 0 2006.173.13:07:15.15#ibcon#about to write, iclass 27, count 0 2006.173.13:07:15.15#ibcon#wrote, iclass 27, count 0 2006.173.13:07:15.15#ibcon#about to read 3, iclass 27, count 0 2006.173.13:07:15.17#ibcon#read 3, iclass 27, count 0 2006.173.13:07:15.17#ibcon#about to read 4, iclass 27, count 0 2006.173.13:07:15.17#ibcon#read 4, iclass 27, count 0 2006.173.13:07:15.17#ibcon#about to read 5, iclass 27, count 0 2006.173.13:07:15.17#ibcon#read 5, iclass 27, count 0 2006.173.13:07:15.17#ibcon#about to read 6, iclass 27, count 0 2006.173.13:07:15.17#ibcon#read 6, iclass 27, count 0 2006.173.13:07:15.17#ibcon#end of sib2, iclass 27, count 0 2006.173.13:07:15.17#ibcon#*mode == 0, iclass 27, count 0 2006.173.13:07:15.17#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.13:07:15.17#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.13:07:15.17#ibcon#*before write, iclass 27, count 0 2006.173.13:07:15.17#ibcon#enter sib2, iclass 27, count 0 2006.173.13:07:15.17#ibcon#flushed, iclass 27, count 0 2006.173.13:07:15.17#ibcon#about to write, iclass 27, count 0 2006.173.13:07:15.17#ibcon#wrote, iclass 27, count 0 2006.173.13:07:15.17#ibcon#about to read 3, iclass 27, count 0 2006.173.13:07:15.21#ibcon#read 3, iclass 27, count 0 2006.173.13:07:15.21#ibcon#about to read 4, iclass 27, count 0 2006.173.13:07:15.21#ibcon#read 4, iclass 27, count 0 2006.173.13:07:15.21#ibcon#about to read 5, iclass 27, count 0 2006.173.13:07:15.21#ibcon#read 5, iclass 27, count 0 2006.173.13:07:15.21#ibcon#about to read 6, iclass 27, count 0 2006.173.13:07:15.21#ibcon#read 6, iclass 27, count 0 2006.173.13:07:15.21#ibcon#end of sib2, iclass 27, count 0 2006.173.13:07:15.21#ibcon#*after write, iclass 27, count 0 2006.173.13:07:15.21#ibcon#*before return 0, iclass 27, count 0 2006.173.13:07:15.21#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.13:07:15.21#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.13:07:15.21#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.13:07:15.21#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.13:07:15.21$vck44/va=4,6 2006.173.13:07:15.21#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.13:07:15.21#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.13:07:15.21#ibcon#ireg 11 cls_cnt 2 2006.173.13:07:15.21#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.13:07:15.27#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.13:07:15.27#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.13:07:15.27#ibcon#enter wrdev, iclass 29, count 2 2006.173.13:07:15.27#ibcon#first serial, iclass 29, count 2 2006.173.13:07:15.27#ibcon#enter sib2, iclass 29, count 2 2006.173.13:07:15.27#ibcon#flushed, iclass 29, count 2 2006.173.13:07:15.27#ibcon#about to write, iclass 29, count 2 2006.173.13:07:15.27#ibcon#wrote, iclass 29, count 2 2006.173.13:07:15.27#ibcon#about to read 3, iclass 29, count 2 2006.173.13:07:15.29#ibcon#read 3, iclass 29, count 2 2006.173.13:07:15.29#ibcon#about to read 4, iclass 29, count 2 2006.173.13:07:15.29#ibcon#read 4, iclass 29, count 2 2006.173.13:07:15.29#ibcon#about to read 5, iclass 29, count 2 2006.173.13:07:15.29#ibcon#read 5, iclass 29, count 2 2006.173.13:07:15.29#ibcon#about to read 6, iclass 29, count 2 2006.173.13:07:15.29#ibcon#read 6, iclass 29, count 2 2006.173.13:07:15.29#ibcon#end of sib2, iclass 29, count 2 2006.173.13:07:15.29#ibcon#*mode == 0, iclass 29, count 2 2006.173.13:07:15.29#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.13:07:15.29#ibcon#[25=AT04-06\r\n] 2006.173.13:07:15.29#ibcon#*before write, iclass 29, count 2 2006.173.13:07:15.29#ibcon#enter sib2, iclass 29, count 2 2006.173.13:07:15.29#ibcon#flushed, iclass 29, count 2 2006.173.13:07:15.29#ibcon#about to write, iclass 29, count 2 2006.173.13:07:15.29#ibcon#wrote, iclass 29, count 2 2006.173.13:07:15.29#ibcon#about to read 3, iclass 29, count 2 2006.173.13:07:15.32#ibcon#read 3, iclass 29, count 2 2006.173.13:07:15.32#ibcon#about to read 4, iclass 29, count 2 2006.173.13:07:15.32#ibcon#read 4, iclass 29, count 2 2006.173.13:07:15.32#ibcon#about to read 5, iclass 29, count 2 2006.173.13:07:15.32#ibcon#read 5, iclass 29, count 2 2006.173.13:07:15.32#ibcon#about to read 6, iclass 29, count 2 2006.173.13:07:15.32#ibcon#read 6, iclass 29, count 2 2006.173.13:07:15.32#ibcon#end of sib2, iclass 29, count 2 2006.173.13:07:15.32#ibcon#*after write, iclass 29, count 2 2006.173.13:07:15.32#ibcon#*before return 0, iclass 29, count 2 2006.173.13:07:15.32#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.13:07:15.32#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.13:07:15.32#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.13:07:15.32#ibcon#ireg 7 cls_cnt 0 2006.173.13:07:15.32#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.13:07:15.44#abcon#<5=/05 0.6 1.0 22.14 971004.2\r\n> 2006.173.13:07:15.44#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.13:07:15.44#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.13:07:15.44#ibcon#enter wrdev, iclass 29, count 0 2006.173.13:07:15.44#ibcon#first serial, iclass 29, count 0 2006.173.13:07:15.44#ibcon#enter sib2, iclass 29, count 0 2006.173.13:07:15.44#ibcon#flushed, iclass 29, count 0 2006.173.13:07:15.44#ibcon#about to write, iclass 29, count 0 2006.173.13:07:15.44#ibcon#wrote, iclass 29, count 0 2006.173.13:07:15.44#ibcon#about to read 3, iclass 29, count 0 2006.173.13:07:15.46#ibcon#read 3, iclass 29, count 0 2006.173.13:07:15.46#ibcon#about to read 4, iclass 29, count 0 2006.173.13:07:15.46#ibcon#read 4, iclass 29, count 0 2006.173.13:07:15.46#ibcon#about to read 5, iclass 29, count 0 2006.173.13:07:15.46#ibcon#read 5, iclass 29, count 0 2006.173.13:07:15.46#ibcon#about to read 6, iclass 29, count 0 2006.173.13:07:15.46#ibcon#read 6, iclass 29, count 0 2006.173.13:07:15.46#ibcon#end of sib2, iclass 29, count 0 2006.173.13:07:15.46#ibcon#*mode == 0, iclass 29, count 0 2006.173.13:07:15.46#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.13:07:15.46#ibcon#[25=USB\r\n] 2006.173.13:07:15.46#ibcon#*before write, iclass 29, count 0 2006.173.13:07:15.46#ibcon#enter sib2, iclass 29, count 0 2006.173.13:07:15.46#ibcon#flushed, iclass 29, count 0 2006.173.13:07:15.46#ibcon#about to write, iclass 29, count 0 2006.173.13:07:15.46#ibcon#wrote, iclass 29, count 0 2006.173.13:07:15.46#ibcon#about to read 3, iclass 29, count 0 2006.173.13:07:15.46#abcon#{5=INTERFACE CLEAR} 2006.173.13:07:15.49#ibcon#read 3, iclass 29, count 0 2006.173.13:07:15.49#ibcon#about to read 4, iclass 29, count 0 2006.173.13:07:15.49#ibcon#read 4, iclass 29, count 0 2006.173.13:07:15.49#ibcon#about to read 5, iclass 29, count 0 2006.173.13:07:15.49#ibcon#read 5, iclass 29, count 0 2006.173.13:07:15.49#ibcon#about to read 6, iclass 29, count 0 2006.173.13:07:15.49#ibcon#read 6, iclass 29, count 0 2006.173.13:07:15.49#ibcon#end of sib2, iclass 29, count 0 2006.173.13:07:15.49#ibcon#*after write, iclass 29, count 0 2006.173.13:07:15.49#ibcon#*before return 0, iclass 29, count 0 2006.173.13:07:15.49#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.13:07:15.49#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.13:07:15.49#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.13:07:15.49#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.13:07:15.49$vck44/valo=5,734.99 2006.173.13:07:15.49#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.13:07:15.49#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.13:07:15.49#ibcon#ireg 17 cls_cnt 0 2006.173.13:07:15.49#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.13:07:15.49#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.13:07:15.49#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.13:07:15.49#ibcon#enter wrdev, iclass 34, count 0 2006.173.13:07:15.49#ibcon#first serial, iclass 34, count 0 2006.173.13:07:15.49#ibcon#enter sib2, iclass 34, count 0 2006.173.13:07:15.49#ibcon#flushed, iclass 34, count 0 2006.173.13:07:15.49#ibcon#about to write, iclass 34, count 0 2006.173.13:07:15.49#ibcon#wrote, iclass 34, count 0 2006.173.13:07:15.49#ibcon#about to read 3, iclass 34, count 0 2006.173.13:07:15.51#ibcon#read 3, iclass 34, count 0 2006.173.13:07:15.51#ibcon#about to read 4, iclass 34, count 0 2006.173.13:07:15.51#ibcon#read 4, iclass 34, count 0 2006.173.13:07:15.51#ibcon#about to read 5, iclass 34, count 0 2006.173.13:07:15.51#ibcon#read 5, iclass 34, count 0 2006.173.13:07:15.51#ibcon#about to read 6, iclass 34, count 0 2006.173.13:07:15.51#ibcon#read 6, iclass 34, count 0 2006.173.13:07:15.51#ibcon#end of sib2, iclass 34, count 0 2006.173.13:07:15.51#ibcon#*mode == 0, iclass 34, count 0 2006.173.13:07:15.51#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.13:07:15.51#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.13:07:15.51#ibcon#*before write, iclass 34, count 0 2006.173.13:07:15.51#ibcon#enter sib2, iclass 34, count 0 2006.173.13:07:15.51#ibcon#flushed, iclass 34, count 0 2006.173.13:07:15.51#ibcon#about to write, iclass 34, count 0 2006.173.13:07:15.51#ibcon#wrote, iclass 34, count 0 2006.173.13:07:15.51#ibcon#about to read 3, iclass 34, count 0 2006.173.13:07:15.52#abcon#[5=S1D000X0/0*\r\n] 2006.173.13:07:15.55#ibcon#read 3, iclass 34, count 0 2006.173.13:07:15.55#ibcon#about to read 4, iclass 34, count 0 2006.173.13:07:15.55#ibcon#read 4, iclass 34, count 0 2006.173.13:07:15.55#ibcon#about to read 5, iclass 34, count 0 2006.173.13:07:15.55#ibcon#read 5, iclass 34, count 0 2006.173.13:07:15.55#ibcon#about to read 6, iclass 34, count 0 2006.173.13:07:15.55#ibcon#read 6, iclass 34, count 0 2006.173.13:07:15.55#ibcon#end of sib2, iclass 34, count 0 2006.173.13:07:15.55#ibcon#*after write, iclass 34, count 0 2006.173.13:07:15.55#ibcon#*before return 0, iclass 34, count 0 2006.173.13:07:15.55#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.13:07:15.55#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.13:07:15.55#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.13:07:15.55#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.13:07:15.55$vck44/va=5,4 2006.173.13:07:15.55#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.173.13:07:15.55#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.173.13:07:15.55#ibcon#ireg 11 cls_cnt 2 2006.173.13:07:15.55#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.13:07:15.61#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.13:07:15.61#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.13:07:15.61#ibcon#enter wrdev, iclass 37, count 2 2006.173.13:07:15.61#ibcon#first serial, iclass 37, count 2 2006.173.13:07:15.61#ibcon#enter sib2, iclass 37, count 2 2006.173.13:07:15.61#ibcon#flushed, iclass 37, count 2 2006.173.13:07:15.61#ibcon#about to write, iclass 37, count 2 2006.173.13:07:15.61#ibcon#wrote, iclass 37, count 2 2006.173.13:07:15.61#ibcon#about to read 3, iclass 37, count 2 2006.173.13:07:15.63#ibcon#read 3, iclass 37, count 2 2006.173.13:07:15.63#ibcon#about to read 4, iclass 37, count 2 2006.173.13:07:15.63#ibcon#read 4, iclass 37, count 2 2006.173.13:07:15.63#ibcon#about to read 5, iclass 37, count 2 2006.173.13:07:15.63#ibcon#read 5, iclass 37, count 2 2006.173.13:07:15.63#ibcon#about to read 6, iclass 37, count 2 2006.173.13:07:15.63#ibcon#read 6, iclass 37, count 2 2006.173.13:07:15.63#ibcon#end of sib2, iclass 37, count 2 2006.173.13:07:15.63#ibcon#*mode == 0, iclass 37, count 2 2006.173.13:07:15.63#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.173.13:07:15.63#ibcon#[25=AT05-04\r\n] 2006.173.13:07:15.63#ibcon#*before write, iclass 37, count 2 2006.173.13:07:15.63#ibcon#enter sib2, iclass 37, count 2 2006.173.13:07:15.63#ibcon#flushed, iclass 37, count 2 2006.173.13:07:15.63#ibcon#about to write, iclass 37, count 2 2006.173.13:07:15.63#ibcon#wrote, iclass 37, count 2 2006.173.13:07:15.63#ibcon#about to read 3, iclass 37, count 2 2006.173.13:07:15.66#ibcon#read 3, iclass 37, count 2 2006.173.13:07:15.66#ibcon#about to read 4, iclass 37, count 2 2006.173.13:07:15.66#ibcon#read 4, iclass 37, count 2 2006.173.13:07:15.66#ibcon#about to read 5, iclass 37, count 2 2006.173.13:07:15.66#ibcon#read 5, iclass 37, count 2 2006.173.13:07:15.66#ibcon#about to read 6, iclass 37, count 2 2006.173.13:07:15.66#ibcon#read 6, iclass 37, count 2 2006.173.13:07:15.66#ibcon#end of sib2, iclass 37, count 2 2006.173.13:07:15.66#ibcon#*after write, iclass 37, count 2 2006.173.13:07:15.66#ibcon#*before return 0, iclass 37, count 2 2006.173.13:07:15.66#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.13:07:15.66#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.173.13:07:15.66#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.173.13:07:15.66#ibcon#ireg 7 cls_cnt 0 2006.173.13:07:15.66#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.13:07:15.78#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.13:07:15.78#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.13:07:15.78#ibcon#enter wrdev, iclass 37, count 0 2006.173.13:07:15.78#ibcon#first serial, iclass 37, count 0 2006.173.13:07:15.78#ibcon#enter sib2, iclass 37, count 0 2006.173.13:07:15.78#ibcon#flushed, iclass 37, count 0 2006.173.13:07:15.78#ibcon#about to write, iclass 37, count 0 2006.173.13:07:15.78#ibcon#wrote, iclass 37, count 0 2006.173.13:07:15.78#ibcon#about to read 3, iclass 37, count 0 2006.173.13:07:15.80#ibcon#read 3, iclass 37, count 0 2006.173.13:07:15.80#ibcon#about to read 4, iclass 37, count 0 2006.173.13:07:15.80#ibcon#read 4, iclass 37, count 0 2006.173.13:07:15.80#ibcon#about to read 5, iclass 37, count 0 2006.173.13:07:15.80#ibcon#read 5, iclass 37, count 0 2006.173.13:07:15.80#ibcon#about to read 6, iclass 37, count 0 2006.173.13:07:15.80#ibcon#read 6, iclass 37, count 0 2006.173.13:07:15.80#ibcon#end of sib2, iclass 37, count 0 2006.173.13:07:15.80#ibcon#*mode == 0, iclass 37, count 0 2006.173.13:07:15.80#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.13:07:15.80#ibcon#[25=USB\r\n] 2006.173.13:07:15.80#ibcon#*before write, iclass 37, count 0 2006.173.13:07:15.80#ibcon#enter sib2, iclass 37, count 0 2006.173.13:07:15.80#ibcon#flushed, iclass 37, count 0 2006.173.13:07:15.80#ibcon#about to write, iclass 37, count 0 2006.173.13:07:15.80#ibcon#wrote, iclass 37, count 0 2006.173.13:07:15.80#ibcon#about to read 3, iclass 37, count 0 2006.173.13:07:15.83#ibcon#read 3, iclass 37, count 0 2006.173.13:07:15.83#ibcon#about to read 4, iclass 37, count 0 2006.173.13:07:15.83#ibcon#read 4, iclass 37, count 0 2006.173.13:07:15.83#ibcon#about to read 5, iclass 37, count 0 2006.173.13:07:15.83#ibcon#read 5, iclass 37, count 0 2006.173.13:07:15.83#ibcon#about to read 6, iclass 37, count 0 2006.173.13:07:15.83#ibcon#read 6, iclass 37, count 0 2006.173.13:07:15.83#ibcon#end of sib2, iclass 37, count 0 2006.173.13:07:15.83#ibcon#*after write, iclass 37, count 0 2006.173.13:07:15.83#ibcon#*before return 0, iclass 37, count 0 2006.173.13:07:15.83#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.13:07:15.83#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.173.13:07:15.83#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.13:07:15.83#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.13:07:15.83$vck44/valo=6,814.99 2006.173.13:07:15.83#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.13:07:15.83#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.13:07:15.83#ibcon#ireg 17 cls_cnt 0 2006.173.13:07:15.83#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.13:07:15.83#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.13:07:15.83#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.13:07:15.83#ibcon#enter wrdev, iclass 39, count 0 2006.173.13:07:15.83#ibcon#first serial, iclass 39, count 0 2006.173.13:07:15.83#ibcon#enter sib2, iclass 39, count 0 2006.173.13:07:15.83#ibcon#flushed, iclass 39, count 0 2006.173.13:07:15.83#ibcon#about to write, iclass 39, count 0 2006.173.13:07:15.83#ibcon#wrote, iclass 39, count 0 2006.173.13:07:15.83#ibcon#about to read 3, iclass 39, count 0 2006.173.13:07:15.85#ibcon#read 3, iclass 39, count 0 2006.173.13:07:15.85#ibcon#about to read 4, iclass 39, count 0 2006.173.13:07:15.85#ibcon#read 4, iclass 39, count 0 2006.173.13:07:15.85#ibcon#about to read 5, iclass 39, count 0 2006.173.13:07:15.85#ibcon#read 5, iclass 39, count 0 2006.173.13:07:15.85#ibcon#about to read 6, iclass 39, count 0 2006.173.13:07:15.85#ibcon#read 6, iclass 39, count 0 2006.173.13:07:15.85#ibcon#end of sib2, iclass 39, count 0 2006.173.13:07:15.85#ibcon#*mode == 0, iclass 39, count 0 2006.173.13:07:15.85#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.13:07:15.85#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.13:07:15.85#ibcon#*before write, iclass 39, count 0 2006.173.13:07:15.85#ibcon#enter sib2, iclass 39, count 0 2006.173.13:07:15.85#ibcon#flushed, iclass 39, count 0 2006.173.13:07:15.85#ibcon#about to write, iclass 39, count 0 2006.173.13:07:15.85#ibcon#wrote, iclass 39, count 0 2006.173.13:07:15.85#ibcon#about to read 3, iclass 39, count 0 2006.173.13:07:15.89#ibcon#read 3, iclass 39, count 0 2006.173.13:07:15.89#ibcon#about to read 4, iclass 39, count 0 2006.173.13:07:15.89#ibcon#read 4, iclass 39, count 0 2006.173.13:07:15.89#ibcon#about to read 5, iclass 39, count 0 2006.173.13:07:15.89#ibcon#read 5, iclass 39, count 0 2006.173.13:07:15.89#ibcon#about to read 6, iclass 39, count 0 2006.173.13:07:15.89#ibcon#read 6, iclass 39, count 0 2006.173.13:07:15.89#ibcon#end of sib2, iclass 39, count 0 2006.173.13:07:15.89#ibcon#*after write, iclass 39, count 0 2006.173.13:07:15.89#ibcon#*before return 0, iclass 39, count 0 2006.173.13:07:15.89#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.13:07:15.89#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.13:07:15.89#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.13:07:15.89#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.13:07:15.89$vck44/va=6,3 2006.173.13:07:15.89#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.13:07:15.89#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.13:07:15.89#ibcon#ireg 11 cls_cnt 2 2006.173.13:07:15.89#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.13:07:15.95#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.13:07:15.95#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.13:07:15.95#ibcon#enter wrdev, iclass 3, count 2 2006.173.13:07:15.95#ibcon#first serial, iclass 3, count 2 2006.173.13:07:15.95#ibcon#enter sib2, iclass 3, count 2 2006.173.13:07:15.95#ibcon#flushed, iclass 3, count 2 2006.173.13:07:15.95#ibcon#about to write, iclass 3, count 2 2006.173.13:07:15.95#ibcon#wrote, iclass 3, count 2 2006.173.13:07:15.95#ibcon#about to read 3, iclass 3, count 2 2006.173.13:07:15.97#ibcon#read 3, iclass 3, count 2 2006.173.13:07:15.97#ibcon#about to read 4, iclass 3, count 2 2006.173.13:07:15.97#ibcon#read 4, iclass 3, count 2 2006.173.13:07:15.97#ibcon#about to read 5, iclass 3, count 2 2006.173.13:07:15.97#ibcon#read 5, iclass 3, count 2 2006.173.13:07:15.97#ibcon#about to read 6, iclass 3, count 2 2006.173.13:07:15.97#ibcon#read 6, iclass 3, count 2 2006.173.13:07:15.97#ibcon#end of sib2, iclass 3, count 2 2006.173.13:07:15.97#ibcon#*mode == 0, iclass 3, count 2 2006.173.13:07:15.97#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.13:07:15.97#ibcon#[25=AT06-03\r\n] 2006.173.13:07:15.97#ibcon#*before write, iclass 3, count 2 2006.173.13:07:15.97#ibcon#enter sib2, iclass 3, count 2 2006.173.13:07:15.97#ibcon#flushed, iclass 3, count 2 2006.173.13:07:15.97#ibcon#about to write, iclass 3, count 2 2006.173.13:07:15.97#ibcon#wrote, iclass 3, count 2 2006.173.13:07:15.97#ibcon#about to read 3, iclass 3, count 2 2006.173.13:07:16.00#ibcon#read 3, iclass 3, count 2 2006.173.13:07:16.00#ibcon#about to read 4, iclass 3, count 2 2006.173.13:07:16.00#ibcon#read 4, iclass 3, count 2 2006.173.13:07:16.00#ibcon#about to read 5, iclass 3, count 2 2006.173.13:07:16.00#ibcon#read 5, iclass 3, count 2 2006.173.13:07:16.00#ibcon#about to read 6, iclass 3, count 2 2006.173.13:07:16.00#ibcon#read 6, iclass 3, count 2 2006.173.13:07:16.00#ibcon#end of sib2, iclass 3, count 2 2006.173.13:07:16.00#ibcon#*after write, iclass 3, count 2 2006.173.13:07:16.00#ibcon#*before return 0, iclass 3, count 2 2006.173.13:07:16.00#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.13:07:16.00#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.13:07:16.00#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.13:07:16.00#ibcon#ireg 7 cls_cnt 0 2006.173.13:07:16.00#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.13:07:16.12#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.13:07:16.12#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.13:07:16.12#ibcon#enter wrdev, iclass 3, count 0 2006.173.13:07:16.12#ibcon#first serial, iclass 3, count 0 2006.173.13:07:16.12#ibcon#enter sib2, iclass 3, count 0 2006.173.13:07:16.12#ibcon#flushed, iclass 3, count 0 2006.173.13:07:16.12#ibcon#about to write, iclass 3, count 0 2006.173.13:07:16.12#ibcon#wrote, iclass 3, count 0 2006.173.13:07:16.12#ibcon#about to read 3, iclass 3, count 0 2006.173.13:07:16.14#ibcon#read 3, iclass 3, count 0 2006.173.13:07:16.14#ibcon#about to read 4, iclass 3, count 0 2006.173.13:07:16.14#ibcon#read 4, iclass 3, count 0 2006.173.13:07:16.14#ibcon#about to read 5, iclass 3, count 0 2006.173.13:07:16.14#ibcon#read 5, iclass 3, count 0 2006.173.13:07:16.14#ibcon#about to read 6, iclass 3, count 0 2006.173.13:07:16.14#ibcon#read 6, iclass 3, count 0 2006.173.13:07:16.14#ibcon#end of sib2, iclass 3, count 0 2006.173.13:07:16.14#ibcon#*mode == 0, iclass 3, count 0 2006.173.13:07:16.14#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.13:07:16.14#ibcon#[25=USB\r\n] 2006.173.13:07:16.14#ibcon#*before write, iclass 3, count 0 2006.173.13:07:16.14#ibcon#enter sib2, iclass 3, count 0 2006.173.13:07:16.14#ibcon#flushed, iclass 3, count 0 2006.173.13:07:16.14#ibcon#about to write, iclass 3, count 0 2006.173.13:07:16.14#ibcon#wrote, iclass 3, count 0 2006.173.13:07:16.14#ibcon#about to read 3, iclass 3, count 0 2006.173.13:07:16.17#ibcon#read 3, iclass 3, count 0 2006.173.13:07:16.17#ibcon#about to read 4, iclass 3, count 0 2006.173.13:07:16.17#ibcon#read 4, iclass 3, count 0 2006.173.13:07:16.17#ibcon#about to read 5, iclass 3, count 0 2006.173.13:07:16.17#ibcon#read 5, iclass 3, count 0 2006.173.13:07:16.17#ibcon#about to read 6, iclass 3, count 0 2006.173.13:07:16.17#ibcon#read 6, iclass 3, count 0 2006.173.13:07:16.17#ibcon#end of sib2, iclass 3, count 0 2006.173.13:07:16.17#ibcon#*after write, iclass 3, count 0 2006.173.13:07:16.17#ibcon#*before return 0, iclass 3, count 0 2006.173.13:07:16.17#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.13:07:16.17#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.13:07:16.17#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.13:07:16.17#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.13:07:16.17$vck44/valo=7,864.99 2006.173.13:07:16.17#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.13:07:16.17#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.13:07:16.17#ibcon#ireg 17 cls_cnt 0 2006.173.13:07:16.17#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.13:07:16.17#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.13:07:16.17#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.13:07:16.17#ibcon#enter wrdev, iclass 5, count 0 2006.173.13:07:16.17#ibcon#first serial, iclass 5, count 0 2006.173.13:07:16.17#ibcon#enter sib2, iclass 5, count 0 2006.173.13:07:16.17#ibcon#flushed, iclass 5, count 0 2006.173.13:07:16.17#ibcon#about to write, iclass 5, count 0 2006.173.13:07:16.17#ibcon#wrote, iclass 5, count 0 2006.173.13:07:16.17#ibcon#about to read 3, iclass 5, count 0 2006.173.13:07:16.19#ibcon#read 3, iclass 5, count 0 2006.173.13:07:16.19#ibcon#about to read 4, iclass 5, count 0 2006.173.13:07:16.19#ibcon#read 4, iclass 5, count 0 2006.173.13:07:16.19#ibcon#about to read 5, iclass 5, count 0 2006.173.13:07:16.19#ibcon#read 5, iclass 5, count 0 2006.173.13:07:16.19#ibcon#about to read 6, iclass 5, count 0 2006.173.13:07:16.19#ibcon#read 6, iclass 5, count 0 2006.173.13:07:16.19#ibcon#end of sib2, iclass 5, count 0 2006.173.13:07:16.19#ibcon#*mode == 0, iclass 5, count 0 2006.173.13:07:16.19#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.13:07:16.19#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.13:07:16.19#ibcon#*before write, iclass 5, count 0 2006.173.13:07:16.19#ibcon#enter sib2, iclass 5, count 0 2006.173.13:07:16.19#ibcon#flushed, iclass 5, count 0 2006.173.13:07:16.19#ibcon#about to write, iclass 5, count 0 2006.173.13:07:16.19#ibcon#wrote, iclass 5, count 0 2006.173.13:07:16.19#ibcon#about to read 3, iclass 5, count 0 2006.173.13:07:16.23#ibcon#read 3, iclass 5, count 0 2006.173.13:07:16.23#ibcon#about to read 4, iclass 5, count 0 2006.173.13:07:16.23#ibcon#read 4, iclass 5, count 0 2006.173.13:07:16.23#ibcon#about to read 5, iclass 5, count 0 2006.173.13:07:16.23#ibcon#read 5, iclass 5, count 0 2006.173.13:07:16.23#ibcon#about to read 6, iclass 5, count 0 2006.173.13:07:16.23#ibcon#read 6, iclass 5, count 0 2006.173.13:07:16.23#ibcon#end of sib2, iclass 5, count 0 2006.173.13:07:16.23#ibcon#*after write, iclass 5, count 0 2006.173.13:07:16.23#ibcon#*before return 0, iclass 5, count 0 2006.173.13:07:16.23#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.13:07:16.23#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.13:07:16.23#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.13:07:16.23#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.13:07:16.23$vck44/va=7,4 2006.173.13:07:16.23#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.173.13:07:16.23#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.173.13:07:16.23#ibcon#ireg 11 cls_cnt 2 2006.173.13:07:16.23#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.13:07:16.29#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.13:07:16.29#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.13:07:16.29#ibcon#enter wrdev, iclass 7, count 2 2006.173.13:07:16.29#ibcon#first serial, iclass 7, count 2 2006.173.13:07:16.29#ibcon#enter sib2, iclass 7, count 2 2006.173.13:07:16.29#ibcon#flushed, iclass 7, count 2 2006.173.13:07:16.29#ibcon#about to write, iclass 7, count 2 2006.173.13:07:16.29#ibcon#wrote, iclass 7, count 2 2006.173.13:07:16.29#ibcon#about to read 3, iclass 7, count 2 2006.173.13:07:16.31#ibcon#read 3, iclass 7, count 2 2006.173.13:07:16.31#ibcon#about to read 4, iclass 7, count 2 2006.173.13:07:16.31#ibcon#read 4, iclass 7, count 2 2006.173.13:07:16.31#ibcon#about to read 5, iclass 7, count 2 2006.173.13:07:16.31#ibcon#read 5, iclass 7, count 2 2006.173.13:07:16.31#ibcon#about to read 6, iclass 7, count 2 2006.173.13:07:16.31#ibcon#read 6, iclass 7, count 2 2006.173.13:07:16.31#ibcon#end of sib2, iclass 7, count 2 2006.173.13:07:16.31#ibcon#*mode == 0, iclass 7, count 2 2006.173.13:07:16.31#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.173.13:07:16.31#ibcon#[25=AT07-04\r\n] 2006.173.13:07:16.31#ibcon#*before write, iclass 7, count 2 2006.173.13:07:16.31#ibcon#enter sib2, iclass 7, count 2 2006.173.13:07:16.31#ibcon#flushed, iclass 7, count 2 2006.173.13:07:16.31#ibcon#about to write, iclass 7, count 2 2006.173.13:07:16.31#ibcon#wrote, iclass 7, count 2 2006.173.13:07:16.31#ibcon#about to read 3, iclass 7, count 2 2006.173.13:07:16.34#ibcon#read 3, iclass 7, count 2 2006.173.13:07:16.34#ibcon#about to read 4, iclass 7, count 2 2006.173.13:07:16.34#ibcon#read 4, iclass 7, count 2 2006.173.13:07:16.34#ibcon#about to read 5, iclass 7, count 2 2006.173.13:07:16.34#ibcon#read 5, iclass 7, count 2 2006.173.13:07:16.34#ibcon#about to read 6, iclass 7, count 2 2006.173.13:07:16.34#ibcon#read 6, iclass 7, count 2 2006.173.13:07:16.34#ibcon#end of sib2, iclass 7, count 2 2006.173.13:07:16.34#ibcon#*after write, iclass 7, count 2 2006.173.13:07:16.34#ibcon#*before return 0, iclass 7, count 2 2006.173.13:07:16.34#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.13:07:16.34#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.173.13:07:16.34#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.173.13:07:16.34#ibcon#ireg 7 cls_cnt 0 2006.173.13:07:16.34#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.13:07:16.46#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.13:07:16.46#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.13:07:16.46#ibcon#enter wrdev, iclass 7, count 0 2006.173.13:07:16.46#ibcon#first serial, iclass 7, count 0 2006.173.13:07:16.46#ibcon#enter sib2, iclass 7, count 0 2006.173.13:07:16.46#ibcon#flushed, iclass 7, count 0 2006.173.13:07:16.46#ibcon#about to write, iclass 7, count 0 2006.173.13:07:16.46#ibcon#wrote, iclass 7, count 0 2006.173.13:07:16.46#ibcon#about to read 3, iclass 7, count 0 2006.173.13:07:16.48#ibcon#read 3, iclass 7, count 0 2006.173.13:07:16.48#ibcon#about to read 4, iclass 7, count 0 2006.173.13:07:16.48#ibcon#read 4, iclass 7, count 0 2006.173.13:07:16.48#ibcon#about to read 5, iclass 7, count 0 2006.173.13:07:16.48#ibcon#read 5, iclass 7, count 0 2006.173.13:07:16.48#ibcon#about to read 6, iclass 7, count 0 2006.173.13:07:16.48#ibcon#read 6, iclass 7, count 0 2006.173.13:07:16.48#ibcon#end of sib2, iclass 7, count 0 2006.173.13:07:16.48#ibcon#*mode == 0, iclass 7, count 0 2006.173.13:07:16.48#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.13:07:16.48#ibcon#[25=USB\r\n] 2006.173.13:07:16.48#ibcon#*before write, iclass 7, count 0 2006.173.13:07:16.48#ibcon#enter sib2, iclass 7, count 0 2006.173.13:07:16.48#ibcon#flushed, iclass 7, count 0 2006.173.13:07:16.48#ibcon#about to write, iclass 7, count 0 2006.173.13:07:16.48#ibcon#wrote, iclass 7, count 0 2006.173.13:07:16.48#ibcon#about to read 3, iclass 7, count 0 2006.173.13:07:16.51#ibcon#read 3, iclass 7, count 0 2006.173.13:07:16.51#ibcon#about to read 4, iclass 7, count 0 2006.173.13:07:16.51#ibcon#read 4, iclass 7, count 0 2006.173.13:07:16.51#ibcon#about to read 5, iclass 7, count 0 2006.173.13:07:16.51#ibcon#read 5, iclass 7, count 0 2006.173.13:07:16.51#ibcon#about to read 6, iclass 7, count 0 2006.173.13:07:16.51#ibcon#read 6, iclass 7, count 0 2006.173.13:07:16.51#ibcon#end of sib2, iclass 7, count 0 2006.173.13:07:16.51#ibcon#*after write, iclass 7, count 0 2006.173.13:07:16.51#ibcon#*before return 0, iclass 7, count 0 2006.173.13:07:16.51#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.13:07:16.51#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.173.13:07:16.51#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.13:07:16.51#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.13:07:16.51$vck44/valo=8,884.99 2006.173.13:07:16.51#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.13:07:16.51#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.13:07:16.51#ibcon#ireg 17 cls_cnt 0 2006.173.13:07:16.51#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.13:07:16.51#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.13:07:16.51#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.13:07:16.51#ibcon#enter wrdev, iclass 11, count 0 2006.173.13:07:16.51#ibcon#first serial, iclass 11, count 0 2006.173.13:07:16.51#ibcon#enter sib2, iclass 11, count 0 2006.173.13:07:16.51#ibcon#flushed, iclass 11, count 0 2006.173.13:07:16.51#ibcon#about to write, iclass 11, count 0 2006.173.13:07:16.51#ibcon#wrote, iclass 11, count 0 2006.173.13:07:16.51#ibcon#about to read 3, iclass 11, count 0 2006.173.13:07:16.53#ibcon#read 3, iclass 11, count 0 2006.173.13:07:16.53#ibcon#about to read 4, iclass 11, count 0 2006.173.13:07:16.53#ibcon#read 4, iclass 11, count 0 2006.173.13:07:16.53#ibcon#about to read 5, iclass 11, count 0 2006.173.13:07:16.53#ibcon#read 5, iclass 11, count 0 2006.173.13:07:16.53#ibcon#about to read 6, iclass 11, count 0 2006.173.13:07:16.53#ibcon#read 6, iclass 11, count 0 2006.173.13:07:16.53#ibcon#end of sib2, iclass 11, count 0 2006.173.13:07:16.53#ibcon#*mode == 0, iclass 11, count 0 2006.173.13:07:16.53#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.13:07:16.53#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.13:07:16.53#ibcon#*before write, iclass 11, count 0 2006.173.13:07:16.53#ibcon#enter sib2, iclass 11, count 0 2006.173.13:07:16.53#ibcon#flushed, iclass 11, count 0 2006.173.13:07:16.53#ibcon#about to write, iclass 11, count 0 2006.173.13:07:16.53#ibcon#wrote, iclass 11, count 0 2006.173.13:07:16.53#ibcon#about to read 3, iclass 11, count 0 2006.173.13:07:16.57#ibcon#read 3, iclass 11, count 0 2006.173.13:07:16.57#ibcon#about to read 4, iclass 11, count 0 2006.173.13:07:16.57#ibcon#read 4, iclass 11, count 0 2006.173.13:07:16.57#ibcon#about to read 5, iclass 11, count 0 2006.173.13:07:16.57#ibcon#read 5, iclass 11, count 0 2006.173.13:07:16.57#ibcon#about to read 6, iclass 11, count 0 2006.173.13:07:16.57#ibcon#read 6, iclass 11, count 0 2006.173.13:07:16.57#ibcon#end of sib2, iclass 11, count 0 2006.173.13:07:16.57#ibcon#*after write, iclass 11, count 0 2006.173.13:07:16.57#ibcon#*before return 0, iclass 11, count 0 2006.173.13:07:16.57#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.13:07:16.57#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.13:07:16.57#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.13:07:16.57#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.13:07:16.57$vck44/va=8,4 2006.173.13:07:16.57#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.173.13:07:16.57#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.173.13:07:16.57#ibcon#ireg 11 cls_cnt 2 2006.173.13:07:16.57#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.13:07:16.63#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.13:07:16.63#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.13:07:16.63#ibcon#enter wrdev, iclass 13, count 2 2006.173.13:07:16.63#ibcon#first serial, iclass 13, count 2 2006.173.13:07:16.63#ibcon#enter sib2, iclass 13, count 2 2006.173.13:07:16.63#ibcon#flushed, iclass 13, count 2 2006.173.13:07:16.63#ibcon#about to write, iclass 13, count 2 2006.173.13:07:16.63#ibcon#wrote, iclass 13, count 2 2006.173.13:07:16.63#ibcon#about to read 3, iclass 13, count 2 2006.173.13:07:16.65#ibcon#read 3, iclass 13, count 2 2006.173.13:07:16.65#ibcon#about to read 4, iclass 13, count 2 2006.173.13:07:16.65#ibcon#read 4, iclass 13, count 2 2006.173.13:07:16.65#ibcon#about to read 5, iclass 13, count 2 2006.173.13:07:16.65#ibcon#read 5, iclass 13, count 2 2006.173.13:07:16.65#ibcon#about to read 6, iclass 13, count 2 2006.173.13:07:16.65#ibcon#read 6, iclass 13, count 2 2006.173.13:07:16.65#ibcon#end of sib2, iclass 13, count 2 2006.173.13:07:16.65#ibcon#*mode == 0, iclass 13, count 2 2006.173.13:07:16.65#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.173.13:07:16.65#ibcon#[25=AT08-04\r\n] 2006.173.13:07:16.65#ibcon#*before write, iclass 13, count 2 2006.173.13:07:16.65#ibcon#enter sib2, iclass 13, count 2 2006.173.13:07:16.65#ibcon#flushed, iclass 13, count 2 2006.173.13:07:16.65#ibcon#about to write, iclass 13, count 2 2006.173.13:07:16.65#ibcon#wrote, iclass 13, count 2 2006.173.13:07:16.65#ibcon#about to read 3, iclass 13, count 2 2006.173.13:07:16.68#ibcon#read 3, iclass 13, count 2 2006.173.13:07:16.68#ibcon#about to read 4, iclass 13, count 2 2006.173.13:07:16.68#ibcon#read 4, iclass 13, count 2 2006.173.13:07:16.68#ibcon#about to read 5, iclass 13, count 2 2006.173.13:07:16.68#ibcon#read 5, iclass 13, count 2 2006.173.13:07:16.68#ibcon#about to read 6, iclass 13, count 2 2006.173.13:07:16.68#ibcon#read 6, iclass 13, count 2 2006.173.13:07:16.68#ibcon#end of sib2, iclass 13, count 2 2006.173.13:07:16.68#ibcon#*after write, iclass 13, count 2 2006.173.13:07:16.68#ibcon#*before return 0, iclass 13, count 2 2006.173.13:07:16.68#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.13:07:16.68#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.173.13:07:16.68#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.173.13:07:16.68#ibcon#ireg 7 cls_cnt 0 2006.173.13:07:16.68#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.13:07:16.80#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.13:07:16.80#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.13:07:16.80#ibcon#enter wrdev, iclass 13, count 0 2006.173.13:07:16.80#ibcon#first serial, iclass 13, count 0 2006.173.13:07:16.80#ibcon#enter sib2, iclass 13, count 0 2006.173.13:07:16.80#ibcon#flushed, iclass 13, count 0 2006.173.13:07:16.80#ibcon#about to write, iclass 13, count 0 2006.173.13:07:16.80#ibcon#wrote, iclass 13, count 0 2006.173.13:07:16.80#ibcon#about to read 3, iclass 13, count 0 2006.173.13:07:16.82#ibcon#read 3, iclass 13, count 0 2006.173.13:07:16.82#ibcon#about to read 4, iclass 13, count 0 2006.173.13:07:16.82#ibcon#read 4, iclass 13, count 0 2006.173.13:07:16.82#ibcon#about to read 5, iclass 13, count 0 2006.173.13:07:16.82#ibcon#read 5, iclass 13, count 0 2006.173.13:07:16.82#ibcon#about to read 6, iclass 13, count 0 2006.173.13:07:16.82#ibcon#read 6, iclass 13, count 0 2006.173.13:07:16.82#ibcon#end of sib2, iclass 13, count 0 2006.173.13:07:16.82#ibcon#*mode == 0, iclass 13, count 0 2006.173.13:07:16.82#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.13:07:16.82#ibcon#[25=USB\r\n] 2006.173.13:07:16.82#ibcon#*before write, iclass 13, count 0 2006.173.13:07:16.82#ibcon#enter sib2, iclass 13, count 0 2006.173.13:07:16.82#ibcon#flushed, iclass 13, count 0 2006.173.13:07:16.82#ibcon#about to write, iclass 13, count 0 2006.173.13:07:16.82#ibcon#wrote, iclass 13, count 0 2006.173.13:07:16.82#ibcon#about to read 3, iclass 13, count 0 2006.173.13:07:16.85#ibcon#read 3, iclass 13, count 0 2006.173.13:07:16.85#ibcon#about to read 4, iclass 13, count 0 2006.173.13:07:16.85#ibcon#read 4, iclass 13, count 0 2006.173.13:07:16.85#ibcon#about to read 5, iclass 13, count 0 2006.173.13:07:16.85#ibcon#read 5, iclass 13, count 0 2006.173.13:07:16.85#ibcon#about to read 6, iclass 13, count 0 2006.173.13:07:16.85#ibcon#read 6, iclass 13, count 0 2006.173.13:07:16.85#ibcon#end of sib2, iclass 13, count 0 2006.173.13:07:16.85#ibcon#*after write, iclass 13, count 0 2006.173.13:07:16.85#ibcon#*before return 0, iclass 13, count 0 2006.173.13:07:16.85#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.13:07:16.85#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.173.13:07:16.85#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.13:07:16.85#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.13:07:16.85$vck44/vblo=1,629.99 2006.173.13:07:16.85#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.13:07:16.85#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.13:07:16.85#ibcon#ireg 17 cls_cnt 0 2006.173.13:07:16.85#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.13:07:16.85#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.13:07:16.85#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.13:07:16.85#ibcon#enter wrdev, iclass 15, count 0 2006.173.13:07:16.85#ibcon#first serial, iclass 15, count 0 2006.173.13:07:16.85#ibcon#enter sib2, iclass 15, count 0 2006.173.13:07:16.85#ibcon#flushed, iclass 15, count 0 2006.173.13:07:16.85#ibcon#about to write, iclass 15, count 0 2006.173.13:07:16.85#ibcon#wrote, iclass 15, count 0 2006.173.13:07:16.85#ibcon#about to read 3, iclass 15, count 0 2006.173.13:07:16.87#ibcon#read 3, iclass 15, count 0 2006.173.13:07:16.87#ibcon#about to read 4, iclass 15, count 0 2006.173.13:07:16.87#ibcon#read 4, iclass 15, count 0 2006.173.13:07:16.87#ibcon#about to read 5, iclass 15, count 0 2006.173.13:07:16.87#ibcon#read 5, iclass 15, count 0 2006.173.13:07:16.87#ibcon#about to read 6, iclass 15, count 0 2006.173.13:07:16.87#ibcon#read 6, iclass 15, count 0 2006.173.13:07:16.87#ibcon#end of sib2, iclass 15, count 0 2006.173.13:07:16.87#ibcon#*mode == 0, iclass 15, count 0 2006.173.13:07:16.87#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.13:07:16.87#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.13:07:16.87#ibcon#*before write, iclass 15, count 0 2006.173.13:07:16.87#ibcon#enter sib2, iclass 15, count 0 2006.173.13:07:16.87#ibcon#flushed, iclass 15, count 0 2006.173.13:07:16.87#ibcon#about to write, iclass 15, count 0 2006.173.13:07:16.87#ibcon#wrote, iclass 15, count 0 2006.173.13:07:16.87#ibcon#about to read 3, iclass 15, count 0 2006.173.13:07:16.91#ibcon#read 3, iclass 15, count 0 2006.173.13:07:16.91#ibcon#about to read 4, iclass 15, count 0 2006.173.13:07:16.91#ibcon#read 4, iclass 15, count 0 2006.173.13:07:16.91#ibcon#about to read 5, iclass 15, count 0 2006.173.13:07:16.91#ibcon#read 5, iclass 15, count 0 2006.173.13:07:16.91#ibcon#about to read 6, iclass 15, count 0 2006.173.13:07:16.91#ibcon#read 6, iclass 15, count 0 2006.173.13:07:16.91#ibcon#end of sib2, iclass 15, count 0 2006.173.13:07:16.91#ibcon#*after write, iclass 15, count 0 2006.173.13:07:16.91#ibcon#*before return 0, iclass 15, count 0 2006.173.13:07:16.91#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.13:07:16.91#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.13:07:16.91#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.13:07:16.91#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.13:07:16.91$vck44/vb=1,4 2006.173.13:07:16.91#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.13:07:16.91#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.13:07:16.91#ibcon#ireg 11 cls_cnt 2 2006.173.13:07:16.91#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.13:07:16.91#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.13:07:16.91#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.13:07:16.91#ibcon#enter wrdev, iclass 17, count 2 2006.173.13:07:16.91#ibcon#first serial, iclass 17, count 2 2006.173.13:07:16.91#ibcon#enter sib2, iclass 17, count 2 2006.173.13:07:16.91#ibcon#flushed, iclass 17, count 2 2006.173.13:07:16.91#ibcon#about to write, iclass 17, count 2 2006.173.13:07:16.91#ibcon#wrote, iclass 17, count 2 2006.173.13:07:16.91#ibcon#about to read 3, iclass 17, count 2 2006.173.13:07:16.93#ibcon#read 3, iclass 17, count 2 2006.173.13:07:16.93#ibcon#about to read 4, iclass 17, count 2 2006.173.13:07:16.93#ibcon#read 4, iclass 17, count 2 2006.173.13:07:16.93#ibcon#about to read 5, iclass 17, count 2 2006.173.13:07:16.93#ibcon#read 5, iclass 17, count 2 2006.173.13:07:16.93#ibcon#about to read 6, iclass 17, count 2 2006.173.13:07:16.93#ibcon#read 6, iclass 17, count 2 2006.173.13:07:16.93#ibcon#end of sib2, iclass 17, count 2 2006.173.13:07:16.93#ibcon#*mode == 0, iclass 17, count 2 2006.173.13:07:16.93#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.13:07:16.93#ibcon#[27=AT01-04\r\n] 2006.173.13:07:16.93#ibcon#*before write, iclass 17, count 2 2006.173.13:07:16.93#ibcon#enter sib2, iclass 17, count 2 2006.173.13:07:16.93#ibcon#flushed, iclass 17, count 2 2006.173.13:07:16.93#ibcon#about to write, iclass 17, count 2 2006.173.13:07:16.93#ibcon#wrote, iclass 17, count 2 2006.173.13:07:16.93#ibcon#about to read 3, iclass 17, count 2 2006.173.13:07:16.96#ibcon#read 3, iclass 17, count 2 2006.173.13:07:16.96#ibcon#about to read 4, iclass 17, count 2 2006.173.13:07:16.96#ibcon#read 4, iclass 17, count 2 2006.173.13:07:16.96#ibcon#about to read 5, iclass 17, count 2 2006.173.13:07:16.96#ibcon#read 5, iclass 17, count 2 2006.173.13:07:16.96#ibcon#about to read 6, iclass 17, count 2 2006.173.13:07:16.96#ibcon#read 6, iclass 17, count 2 2006.173.13:07:16.96#ibcon#end of sib2, iclass 17, count 2 2006.173.13:07:16.96#ibcon#*after write, iclass 17, count 2 2006.173.13:07:16.96#ibcon#*before return 0, iclass 17, count 2 2006.173.13:07:16.96#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.13:07:16.96#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.13:07:16.96#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.13:07:16.96#ibcon#ireg 7 cls_cnt 0 2006.173.13:07:16.96#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.13:07:17.08#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.13:07:17.08#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.13:07:17.08#ibcon#enter wrdev, iclass 17, count 0 2006.173.13:07:17.08#ibcon#first serial, iclass 17, count 0 2006.173.13:07:17.08#ibcon#enter sib2, iclass 17, count 0 2006.173.13:07:17.08#ibcon#flushed, iclass 17, count 0 2006.173.13:07:17.08#ibcon#about to write, iclass 17, count 0 2006.173.13:07:17.08#ibcon#wrote, iclass 17, count 0 2006.173.13:07:17.08#ibcon#about to read 3, iclass 17, count 0 2006.173.13:07:17.10#ibcon#read 3, iclass 17, count 0 2006.173.13:07:17.10#ibcon#about to read 4, iclass 17, count 0 2006.173.13:07:17.10#ibcon#read 4, iclass 17, count 0 2006.173.13:07:17.10#ibcon#about to read 5, iclass 17, count 0 2006.173.13:07:17.10#ibcon#read 5, iclass 17, count 0 2006.173.13:07:17.10#ibcon#about to read 6, iclass 17, count 0 2006.173.13:07:17.10#ibcon#read 6, iclass 17, count 0 2006.173.13:07:17.10#ibcon#end of sib2, iclass 17, count 0 2006.173.13:07:17.10#ibcon#*mode == 0, iclass 17, count 0 2006.173.13:07:17.10#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.13:07:17.10#ibcon#[27=USB\r\n] 2006.173.13:07:17.10#ibcon#*before write, iclass 17, count 0 2006.173.13:07:17.10#ibcon#enter sib2, iclass 17, count 0 2006.173.13:07:17.10#ibcon#flushed, iclass 17, count 0 2006.173.13:07:17.10#ibcon#about to write, iclass 17, count 0 2006.173.13:07:17.10#ibcon#wrote, iclass 17, count 0 2006.173.13:07:17.10#ibcon#about to read 3, iclass 17, count 0 2006.173.13:07:17.13#ibcon#read 3, iclass 17, count 0 2006.173.13:07:17.13#ibcon#about to read 4, iclass 17, count 0 2006.173.13:07:17.13#ibcon#read 4, iclass 17, count 0 2006.173.13:07:17.13#ibcon#about to read 5, iclass 17, count 0 2006.173.13:07:17.13#ibcon#read 5, iclass 17, count 0 2006.173.13:07:17.13#ibcon#about to read 6, iclass 17, count 0 2006.173.13:07:17.13#ibcon#read 6, iclass 17, count 0 2006.173.13:07:17.13#ibcon#end of sib2, iclass 17, count 0 2006.173.13:07:17.13#ibcon#*after write, iclass 17, count 0 2006.173.13:07:17.13#ibcon#*before return 0, iclass 17, count 0 2006.173.13:07:17.13#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.13:07:17.13#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.13:07:17.13#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.13:07:17.13#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.13:07:17.13$vck44/vblo=2,634.99 2006.173.13:07:17.13#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.13:07:17.13#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.13:07:17.13#ibcon#ireg 17 cls_cnt 0 2006.173.13:07:17.13#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.13:07:17.13#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.13:07:17.13#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.13:07:17.13#ibcon#enter wrdev, iclass 19, count 0 2006.173.13:07:17.13#ibcon#first serial, iclass 19, count 0 2006.173.13:07:17.13#ibcon#enter sib2, iclass 19, count 0 2006.173.13:07:17.13#ibcon#flushed, iclass 19, count 0 2006.173.13:07:17.13#ibcon#about to write, iclass 19, count 0 2006.173.13:07:17.13#ibcon#wrote, iclass 19, count 0 2006.173.13:07:17.13#ibcon#about to read 3, iclass 19, count 0 2006.173.13:07:17.15#ibcon#read 3, iclass 19, count 0 2006.173.13:07:17.15#ibcon#about to read 4, iclass 19, count 0 2006.173.13:07:17.15#ibcon#read 4, iclass 19, count 0 2006.173.13:07:17.15#ibcon#about to read 5, iclass 19, count 0 2006.173.13:07:17.15#ibcon#read 5, iclass 19, count 0 2006.173.13:07:17.15#ibcon#about to read 6, iclass 19, count 0 2006.173.13:07:17.15#ibcon#read 6, iclass 19, count 0 2006.173.13:07:17.15#ibcon#end of sib2, iclass 19, count 0 2006.173.13:07:17.15#ibcon#*mode == 0, iclass 19, count 0 2006.173.13:07:17.15#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.13:07:17.15#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.13:07:17.15#ibcon#*before write, iclass 19, count 0 2006.173.13:07:17.15#ibcon#enter sib2, iclass 19, count 0 2006.173.13:07:17.15#ibcon#flushed, iclass 19, count 0 2006.173.13:07:17.15#ibcon#about to write, iclass 19, count 0 2006.173.13:07:17.15#ibcon#wrote, iclass 19, count 0 2006.173.13:07:17.15#ibcon#about to read 3, iclass 19, count 0 2006.173.13:07:17.19#ibcon#read 3, iclass 19, count 0 2006.173.13:07:17.19#ibcon#about to read 4, iclass 19, count 0 2006.173.13:07:17.19#ibcon#read 4, iclass 19, count 0 2006.173.13:07:17.19#ibcon#about to read 5, iclass 19, count 0 2006.173.13:07:17.19#ibcon#read 5, iclass 19, count 0 2006.173.13:07:17.19#ibcon#about to read 6, iclass 19, count 0 2006.173.13:07:17.19#ibcon#read 6, iclass 19, count 0 2006.173.13:07:17.19#ibcon#end of sib2, iclass 19, count 0 2006.173.13:07:17.19#ibcon#*after write, iclass 19, count 0 2006.173.13:07:17.19#ibcon#*before return 0, iclass 19, count 0 2006.173.13:07:17.19#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.13:07:17.19#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.13:07:17.19#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.13:07:17.19#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.13:07:17.19$vck44/vb=2,4 2006.173.13:07:17.19#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.13:07:17.19#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.13:07:17.19#ibcon#ireg 11 cls_cnt 2 2006.173.13:07:17.19#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.13:07:17.25#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.13:07:17.25#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.13:07:17.25#ibcon#enter wrdev, iclass 21, count 2 2006.173.13:07:17.25#ibcon#first serial, iclass 21, count 2 2006.173.13:07:17.25#ibcon#enter sib2, iclass 21, count 2 2006.173.13:07:17.25#ibcon#flushed, iclass 21, count 2 2006.173.13:07:17.25#ibcon#about to write, iclass 21, count 2 2006.173.13:07:17.25#ibcon#wrote, iclass 21, count 2 2006.173.13:07:17.25#ibcon#about to read 3, iclass 21, count 2 2006.173.13:07:17.27#ibcon#read 3, iclass 21, count 2 2006.173.13:07:17.27#ibcon#about to read 4, iclass 21, count 2 2006.173.13:07:17.27#ibcon#read 4, iclass 21, count 2 2006.173.13:07:17.27#ibcon#about to read 5, iclass 21, count 2 2006.173.13:07:17.27#ibcon#read 5, iclass 21, count 2 2006.173.13:07:17.27#ibcon#about to read 6, iclass 21, count 2 2006.173.13:07:17.27#ibcon#read 6, iclass 21, count 2 2006.173.13:07:17.27#ibcon#end of sib2, iclass 21, count 2 2006.173.13:07:17.27#ibcon#*mode == 0, iclass 21, count 2 2006.173.13:07:17.27#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.13:07:17.27#ibcon#[27=AT02-04\r\n] 2006.173.13:07:17.27#ibcon#*before write, iclass 21, count 2 2006.173.13:07:17.27#ibcon#enter sib2, iclass 21, count 2 2006.173.13:07:17.27#ibcon#flushed, iclass 21, count 2 2006.173.13:07:17.27#ibcon#about to write, iclass 21, count 2 2006.173.13:07:17.27#ibcon#wrote, iclass 21, count 2 2006.173.13:07:17.27#ibcon#about to read 3, iclass 21, count 2 2006.173.13:07:17.30#ibcon#read 3, iclass 21, count 2 2006.173.13:07:17.30#ibcon#about to read 4, iclass 21, count 2 2006.173.13:07:17.30#ibcon#read 4, iclass 21, count 2 2006.173.13:07:17.30#ibcon#about to read 5, iclass 21, count 2 2006.173.13:07:17.30#ibcon#read 5, iclass 21, count 2 2006.173.13:07:17.30#ibcon#about to read 6, iclass 21, count 2 2006.173.13:07:17.30#ibcon#read 6, iclass 21, count 2 2006.173.13:07:17.30#ibcon#end of sib2, iclass 21, count 2 2006.173.13:07:17.30#ibcon#*after write, iclass 21, count 2 2006.173.13:07:17.30#ibcon#*before return 0, iclass 21, count 2 2006.173.13:07:17.30#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.13:07:17.30#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.13:07:17.30#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.13:07:17.30#ibcon#ireg 7 cls_cnt 0 2006.173.13:07:17.30#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.13:07:17.42#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.13:07:17.42#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.13:07:17.42#ibcon#enter wrdev, iclass 21, count 0 2006.173.13:07:17.42#ibcon#first serial, iclass 21, count 0 2006.173.13:07:17.42#ibcon#enter sib2, iclass 21, count 0 2006.173.13:07:17.42#ibcon#flushed, iclass 21, count 0 2006.173.13:07:17.42#ibcon#about to write, iclass 21, count 0 2006.173.13:07:17.42#ibcon#wrote, iclass 21, count 0 2006.173.13:07:17.42#ibcon#about to read 3, iclass 21, count 0 2006.173.13:07:17.44#ibcon#read 3, iclass 21, count 0 2006.173.13:07:17.44#ibcon#about to read 4, iclass 21, count 0 2006.173.13:07:17.44#ibcon#read 4, iclass 21, count 0 2006.173.13:07:17.44#ibcon#about to read 5, iclass 21, count 0 2006.173.13:07:17.44#ibcon#read 5, iclass 21, count 0 2006.173.13:07:17.44#ibcon#about to read 6, iclass 21, count 0 2006.173.13:07:17.44#ibcon#read 6, iclass 21, count 0 2006.173.13:07:17.44#ibcon#end of sib2, iclass 21, count 0 2006.173.13:07:17.44#ibcon#*mode == 0, iclass 21, count 0 2006.173.13:07:17.44#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.13:07:17.44#ibcon#[27=USB\r\n] 2006.173.13:07:17.44#ibcon#*before write, iclass 21, count 0 2006.173.13:07:17.44#ibcon#enter sib2, iclass 21, count 0 2006.173.13:07:17.44#ibcon#flushed, iclass 21, count 0 2006.173.13:07:17.44#ibcon#about to write, iclass 21, count 0 2006.173.13:07:17.44#ibcon#wrote, iclass 21, count 0 2006.173.13:07:17.44#ibcon#about to read 3, iclass 21, count 0 2006.173.13:07:17.47#ibcon#read 3, iclass 21, count 0 2006.173.13:07:17.47#ibcon#about to read 4, iclass 21, count 0 2006.173.13:07:17.47#ibcon#read 4, iclass 21, count 0 2006.173.13:07:17.47#ibcon#about to read 5, iclass 21, count 0 2006.173.13:07:17.47#ibcon#read 5, iclass 21, count 0 2006.173.13:07:17.47#ibcon#about to read 6, iclass 21, count 0 2006.173.13:07:17.47#ibcon#read 6, iclass 21, count 0 2006.173.13:07:17.47#ibcon#end of sib2, iclass 21, count 0 2006.173.13:07:17.47#ibcon#*after write, iclass 21, count 0 2006.173.13:07:17.47#ibcon#*before return 0, iclass 21, count 0 2006.173.13:07:17.47#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.13:07:17.47#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.13:07:17.47#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.13:07:17.47#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.13:07:17.47$vck44/vblo=3,649.99 2006.173.13:07:17.47#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.13:07:17.47#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.13:07:17.47#ibcon#ireg 17 cls_cnt 0 2006.173.13:07:17.47#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.13:07:17.47#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.13:07:17.47#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.13:07:17.47#ibcon#enter wrdev, iclass 23, count 0 2006.173.13:07:17.47#ibcon#first serial, iclass 23, count 0 2006.173.13:07:17.47#ibcon#enter sib2, iclass 23, count 0 2006.173.13:07:17.47#ibcon#flushed, iclass 23, count 0 2006.173.13:07:17.47#ibcon#about to write, iclass 23, count 0 2006.173.13:07:17.47#ibcon#wrote, iclass 23, count 0 2006.173.13:07:17.47#ibcon#about to read 3, iclass 23, count 0 2006.173.13:07:17.49#ibcon#read 3, iclass 23, count 0 2006.173.13:07:17.49#ibcon#about to read 4, iclass 23, count 0 2006.173.13:07:17.49#ibcon#read 4, iclass 23, count 0 2006.173.13:07:17.49#ibcon#about to read 5, iclass 23, count 0 2006.173.13:07:17.49#ibcon#read 5, iclass 23, count 0 2006.173.13:07:17.49#ibcon#about to read 6, iclass 23, count 0 2006.173.13:07:17.49#ibcon#read 6, iclass 23, count 0 2006.173.13:07:17.49#ibcon#end of sib2, iclass 23, count 0 2006.173.13:07:17.49#ibcon#*mode == 0, iclass 23, count 0 2006.173.13:07:17.49#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.13:07:17.49#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.13:07:17.49#ibcon#*before write, iclass 23, count 0 2006.173.13:07:17.49#ibcon#enter sib2, iclass 23, count 0 2006.173.13:07:17.49#ibcon#flushed, iclass 23, count 0 2006.173.13:07:17.49#ibcon#about to write, iclass 23, count 0 2006.173.13:07:17.49#ibcon#wrote, iclass 23, count 0 2006.173.13:07:17.49#ibcon#about to read 3, iclass 23, count 0 2006.173.13:07:17.53#ibcon#read 3, iclass 23, count 0 2006.173.13:07:17.53#ibcon#about to read 4, iclass 23, count 0 2006.173.13:07:17.53#ibcon#read 4, iclass 23, count 0 2006.173.13:07:17.53#ibcon#about to read 5, iclass 23, count 0 2006.173.13:07:17.53#ibcon#read 5, iclass 23, count 0 2006.173.13:07:17.53#ibcon#about to read 6, iclass 23, count 0 2006.173.13:07:17.53#ibcon#read 6, iclass 23, count 0 2006.173.13:07:17.53#ibcon#end of sib2, iclass 23, count 0 2006.173.13:07:17.53#ibcon#*after write, iclass 23, count 0 2006.173.13:07:17.53#ibcon#*before return 0, iclass 23, count 0 2006.173.13:07:17.53#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.13:07:17.53#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.13:07:17.53#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.13:07:17.53#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.13:07:17.53$vck44/vb=3,4 2006.173.13:07:17.53#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.13:07:17.53#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.13:07:17.53#ibcon#ireg 11 cls_cnt 2 2006.173.13:07:17.53#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.13:07:17.59#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.13:07:17.59#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.13:07:17.59#ibcon#enter wrdev, iclass 25, count 2 2006.173.13:07:17.59#ibcon#first serial, iclass 25, count 2 2006.173.13:07:17.59#ibcon#enter sib2, iclass 25, count 2 2006.173.13:07:17.59#ibcon#flushed, iclass 25, count 2 2006.173.13:07:17.59#ibcon#about to write, iclass 25, count 2 2006.173.13:07:17.59#ibcon#wrote, iclass 25, count 2 2006.173.13:07:17.59#ibcon#about to read 3, iclass 25, count 2 2006.173.13:07:17.61#ibcon#read 3, iclass 25, count 2 2006.173.13:07:17.61#ibcon#about to read 4, iclass 25, count 2 2006.173.13:07:17.61#ibcon#read 4, iclass 25, count 2 2006.173.13:07:17.61#ibcon#about to read 5, iclass 25, count 2 2006.173.13:07:17.61#ibcon#read 5, iclass 25, count 2 2006.173.13:07:17.61#ibcon#about to read 6, iclass 25, count 2 2006.173.13:07:17.61#ibcon#read 6, iclass 25, count 2 2006.173.13:07:17.61#ibcon#end of sib2, iclass 25, count 2 2006.173.13:07:17.61#ibcon#*mode == 0, iclass 25, count 2 2006.173.13:07:17.61#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.13:07:17.61#ibcon#[27=AT03-04\r\n] 2006.173.13:07:17.61#ibcon#*before write, iclass 25, count 2 2006.173.13:07:17.61#ibcon#enter sib2, iclass 25, count 2 2006.173.13:07:17.61#ibcon#flushed, iclass 25, count 2 2006.173.13:07:17.61#ibcon#about to write, iclass 25, count 2 2006.173.13:07:17.61#ibcon#wrote, iclass 25, count 2 2006.173.13:07:17.61#ibcon#about to read 3, iclass 25, count 2 2006.173.13:07:17.64#ibcon#read 3, iclass 25, count 2 2006.173.13:07:17.64#ibcon#about to read 4, iclass 25, count 2 2006.173.13:07:17.64#ibcon#read 4, iclass 25, count 2 2006.173.13:07:17.64#ibcon#about to read 5, iclass 25, count 2 2006.173.13:07:17.64#ibcon#read 5, iclass 25, count 2 2006.173.13:07:17.64#ibcon#about to read 6, iclass 25, count 2 2006.173.13:07:17.64#ibcon#read 6, iclass 25, count 2 2006.173.13:07:17.64#ibcon#end of sib2, iclass 25, count 2 2006.173.13:07:17.64#ibcon#*after write, iclass 25, count 2 2006.173.13:07:17.64#ibcon#*before return 0, iclass 25, count 2 2006.173.13:07:17.64#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.13:07:17.64#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.13:07:17.64#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.13:07:17.64#ibcon#ireg 7 cls_cnt 0 2006.173.13:07:17.64#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.13:07:17.76#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.13:07:17.76#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.13:07:17.76#ibcon#enter wrdev, iclass 25, count 0 2006.173.13:07:17.76#ibcon#first serial, iclass 25, count 0 2006.173.13:07:17.76#ibcon#enter sib2, iclass 25, count 0 2006.173.13:07:17.76#ibcon#flushed, iclass 25, count 0 2006.173.13:07:17.76#ibcon#about to write, iclass 25, count 0 2006.173.13:07:17.76#ibcon#wrote, iclass 25, count 0 2006.173.13:07:17.76#ibcon#about to read 3, iclass 25, count 0 2006.173.13:07:17.78#ibcon#read 3, iclass 25, count 0 2006.173.13:07:17.78#ibcon#about to read 4, iclass 25, count 0 2006.173.13:07:17.78#ibcon#read 4, iclass 25, count 0 2006.173.13:07:17.78#ibcon#about to read 5, iclass 25, count 0 2006.173.13:07:17.78#ibcon#read 5, iclass 25, count 0 2006.173.13:07:17.78#ibcon#about to read 6, iclass 25, count 0 2006.173.13:07:17.78#ibcon#read 6, iclass 25, count 0 2006.173.13:07:17.78#ibcon#end of sib2, iclass 25, count 0 2006.173.13:07:17.78#ibcon#*mode == 0, iclass 25, count 0 2006.173.13:07:17.78#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.13:07:17.78#ibcon#[27=USB\r\n] 2006.173.13:07:17.78#ibcon#*before write, iclass 25, count 0 2006.173.13:07:17.78#ibcon#enter sib2, iclass 25, count 0 2006.173.13:07:17.78#ibcon#flushed, iclass 25, count 0 2006.173.13:07:17.78#ibcon#about to write, iclass 25, count 0 2006.173.13:07:17.78#ibcon#wrote, iclass 25, count 0 2006.173.13:07:17.78#ibcon#about to read 3, iclass 25, count 0 2006.173.13:07:17.81#ibcon#read 3, iclass 25, count 0 2006.173.13:07:17.81#ibcon#about to read 4, iclass 25, count 0 2006.173.13:07:17.81#ibcon#read 4, iclass 25, count 0 2006.173.13:07:17.81#ibcon#about to read 5, iclass 25, count 0 2006.173.13:07:17.81#ibcon#read 5, iclass 25, count 0 2006.173.13:07:17.81#ibcon#about to read 6, iclass 25, count 0 2006.173.13:07:17.81#ibcon#read 6, iclass 25, count 0 2006.173.13:07:17.81#ibcon#end of sib2, iclass 25, count 0 2006.173.13:07:17.81#ibcon#*after write, iclass 25, count 0 2006.173.13:07:17.81#ibcon#*before return 0, iclass 25, count 0 2006.173.13:07:17.81#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.13:07:17.81#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.13:07:17.81#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.13:07:17.81#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.13:07:17.81$vck44/vblo=4,679.99 2006.173.13:07:17.81#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.13:07:17.81#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.13:07:17.81#ibcon#ireg 17 cls_cnt 0 2006.173.13:07:17.81#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.13:07:17.81#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.13:07:17.81#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.13:07:17.81#ibcon#enter wrdev, iclass 27, count 0 2006.173.13:07:17.81#ibcon#first serial, iclass 27, count 0 2006.173.13:07:17.81#ibcon#enter sib2, iclass 27, count 0 2006.173.13:07:17.81#ibcon#flushed, iclass 27, count 0 2006.173.13:07:17.81#ibcon#about to write, iclass 27, count 0 2006.173.13:07:17.81#ibcon#wrote, iclass 27, count 0 2006.173.13:07:17.81#ibcon#about to read 3, iclass 27, count 0 2006.173.13:07:17.83#ibcon#read 3, iclass 27, count 0 2006.173.13:07:17.83#ibcon#about to read 4, iclass 27, count 0 2006.173.13:07:17.83#ibcon#read 4, iclass 27, count 0 2006.173.13:07:17.83#ibcon#about to read 5, iclass 27, count 0 2006.173.13:07:17.83#ibcon#read 5, iclass 27, count 0 2006.173.13:07:17.83#ibcon#about to read 6, iclass 27, count 0 2006.173.13:07:17.83#ibcon#read 6, iclass 27, count 0 2006.173.13:07:17.83#ibcon#end of sib2, iclass 27, count 0 2006.173.13:07:17.83#ibcon#*mode == 0, iclass 27, count 0 2006.173.13:07:17.83#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.13:07:17.83#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.13:07:17.83#ibcon#*before write, iclass 27, count 0 2006.173.13:07:17.83#ibcon#enter sib2, iclass 27, count 0 2006.173.13:07:17.83#ibcon#flushed, iclass 27, count 0 2006.173.13:07:17.83#ibcon#about to write, iclass 27, count 0 2006.173.13:07:17.83#ibcon#wrote, iclass 27, count 0 2006.173.13:07:17.83#ibcon#about to read 3, iclass 27, count 0 2006.173.13:07:17.87#ibcon#read 3, iclass 27, count 0 2006.173.13:07:17.87#ibcon#about to read 4, iclass 27, count 0 2006.173.13:07:17.87#ibcon#read 4, iclass 27, count 0 2006.173.13:07:17.87#ibcon#about to read 5, iclass 27, count 0 2006.173.13:07:17.87#ibcon#read 5, iclass 27, count 0 2006.173.13:07:17.87#ibcon#about to read 6, iclass 27, count 0 2006.173.13:07:17.87#ibcon#read 6, iclass 27, count 0 2006.173.13:07:17.87#ibcon#end of sib2, iclass 27, count 0 2006.173.13:07:17.87#ibcon#*after write, iclass 27, count 0 2006.173.13:07:17.87#ibcon#*before return 0, iclass 27, count 0 2006.173.13:07:17.87#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.13:07:17.87#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.13:07:17.87#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.13:07:17.87#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.13:07:17.87$vck44/vb=4,4 2006.173.13:07:17.87#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.13:07:17.87#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.13:07:17.87#ibcon#ireg 11 cls_cnt 2 2006.173.13:07:17.87#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.13:07:17.93#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.13:07:17.93#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.13:07:17.93#ibcon#enter wrdev, iclass 29, count 2 2006.173.13:07:17.93#ibcon#first serial, iclass 29, count 2 2006.173.13:07:17.93#ibcon#enter sib2, iclass 29, count 2 2006.173.13:07:17.93#ibcon#flushed, iclass 29, count 2 2006.173.13:07:17.93#ibcon#about to write, iclass 29, count 2 2006.173.13:07:17.93#ibcon#wrote, iclass 29, count 2 2006.173.13:07:17.93#ibcon#about to read 3, iclass 29, count 2 2006.173.13:07:17.95#ibcon#read 3, iclass 29, count 2 2006.173.13:07:17.95#ibcon#about to read 4, iclass 29, count 2 2006.173.13:07:17.95#ibcon#read 4, iclass 29, count 2 2006.173.13:07:17.95#ibcon#about to read 5, iclass 29, count 2 2006.173.13:07:17.95#ibcon#read 5, iclass 29, count 2 2006.173.13:07:17.95#ibcon#about to read 6, iclass 29, count 2 2006.173.13:07:17.95#ibcon#read 6, iclass 29, count 2 2006.173.13:07:17.95#ibcon#end of sib2, iclass 29, count 2 2006.173.13:07:17.95#ibcon#*mode == 0, iclass 29, count 2 2006.173.13:07:17.95#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.13:07:17.95#ibcon#[27=AT04-04\r\n] 2006.173.13:07:17.95#ibcon#*before write, iclass 29, count 2 2006.173.13:07:17.95#ibcon#enter sib2, iclass 29, count 2 2006.173.13:07:17.95#ibcon#flushed, iclass 29, count 2 2006.173.13:07:17.95#ibcon#about to write, iclass 29, count 2 2006.173.13:07:17.95#ibcon#wrote, iclass 29, count 2 2006.173.13:07:17.95#ibcon#about to read 3, iclass 29, count 2 2006.173.13:07:17.98#ibcon#read 3, iclass 29, count 2 2006.173.13:07:17.98#ibcon#about to read 4, iclass 29, count 2 2006.173.13:07:17.98#ibcon#read 4, iclass 29, count 2 2006.173.13:07:17.98#ibcon#about to read 5, iclass 29, count 2 2006.173.13:07:17.98#ibcon#read 5, iclass 29, count 2 2006.173.13:07:17.98#ibcon#about to read 6, iclass 29, count 2 2006.173.13:07:17.98#ibcon#read 6, iclass 29, count 2 2006.173.13:07:17.98#ibcon#end of sib2, iclass 29, count 2 2006.173.13:07:17.98#ibcon#*after write, iclass 29, count 2 2006.173.13:07:17.98#ibcon#*before return 0, iclass 29, count 2 2006.173.13:07:17.98#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.13:07:17.98#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.13:07:17.98#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.13:07:17.98#ibcon#ireg 7 cls_cnt 0 2006.173.13:07:17.98#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.13:07:18.10#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.13:07:18.10#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.13:07:18.10#ibcon#enter wrdev, iclass 29, count 0 2006.173.13:07:18.10#ibcon#first serial, iclass 29, count 0 2006.173.13:07:18.10#ibcon#enter sib2, iclass 29, count 0 2006.173.13:07:18.10#ibcon#flushed, iclass 29, count 0 2006.173.13:07:18.10#ibcon#about to write, iclass 29, count 0 2006.173.13:07:18.10#ibcon#wrote, iclass 29, count 0 2006.173.13:07:18.10#ibcon#about to read 3, iclass 29, count 0 2006.173.13:07:18.12#ibcon#read 3, iclass 29, count 0 2006.173.13:07:18.12#ibcon#about to read 4, iclass 29, count 0 2006.173.13:07:18.12#ibcon#read 4, iclass 29, count 0 2006.173.13:07:18.12#ibcon#about to read 5, iclass 29, count 0 2006.173.13:07:18.12#ibcon#read 5, iclass 29, count 0 2006.173.13:07:18.12#ibcon#about to read 6, iclass 29, count 0 2006.173.13:07:18.12#ibcon#read 6, iclass 29, count 0 2006.173.13:07:18.12#ibcon#end of sib2, iclass 29, count 0 2006.173.13:07:18.12#ibcon#*mode == 0, iclass 29, count 0 2006.173.13:07:18.12#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.13:07:18.12#ibcon#[27=USB\r\n] 2006.173.13:07:18.12#ibcon#*before write, iclass 29, count 0 2006.173.13:07:18.12#ibcon#enter sib2, iclass 29, count 0 2006.173.13:07:18.12#ibcon#flushed, iclass 29, count 0 2006.173.13:07:18.12#ibcon#about to write, iclass 29, count 0 2006.173.13:07:18.12#ibcon#wrote, iclass 29, count 0 2006.173.13:07:18.12#ibcon#about to read 3, iclass 29, count 0 2006.173.13:07:18.15#ibcon#read 3, iclass 29, count 0 2006.173.13:07:18.15#ibcon#about to read 4, iclass 29, count 0 2006.173.13:07:18.15#ibcon#read 4, iclass 29, count 0 2006.173.13:07:18.15#ibcon#about to read 5, iclass 29, count 0 2006.173.13:07:18.15#ibcon#read 5, iclass 29, count 0 2006.173.13:07:18.15#ibcon#about to read 6, iclass 29, count 0 2006.173.13:07:18.15#ibcon#read 6, iclass 29, count 0 2006.173.13:07:18.15#ibcon#end of sib2, iclass 29, count 0 2006.173.13:07:18.15#ibcon#*after write, iclass 29, count 0 2006.173.13:07:18.15#ibcon#*before return 0, iclass 29, count 0 2006.173.13:07:18.15#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.13:07:18.15#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.13:07:18.15#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.13:07:18.15#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.13:07:18.15$vck44/vblo=5,709.99 2006.173.13:07:18.15#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.13:07:18.15#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.13:07:18.15#ibcon#ireg 17 cls_cnt 0 2006.173.13:07:18.15#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.13:07:18.15#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.13:07:18.15#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.13:07:18.15#ibcon#enter wrdev, iclass 31, count 0 2006.173.13:07:18.15#ibcon#first serial, iclass 31, count 0 2006.173.13:07:18.15#ibcon#enter sib2, iclass 31, count 0 2006.173.13:07:18.15#ibcon#flushed, iclass 31, count 0 2006.173.13:07:18.15#ibcon#about to write, iclass 31, count 0 2006.173.13:07:18.15#ibcon#wrote, iclass 31, count 0 2006.173.13:07:18.15#ibcon#about to read 3, iclass 31, count 0 2006.173.13:07:18.17#ibcon#read 3, iclass 31, count 0 2006.173.13:07:18.17#ibcon#about to read 4, iclass 31, count 0 2006.173.13:07:18.17#ibcon#read 4, iclass 31, count 0 2006.173.13:07:18.17#ibcon#about to read 5, iclass 31, count 0 2006.173.13:07:18.17#ibcon#read 5, iclass 31, count 0 2006.173.13:07:18.17#ibcon#about to read 6, iclass 31, count 0 2006.173.13:07:18.17#ibcon#read 6, iclass 31, count 0 2006.173.13:07:18.17#ibcon#end of sib2, iclass 31, count 0 2006.173.13:07:18.17#ibcon#*mode == 0, iclass 31, count 0 2006.173.13:07:18.17#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.13:07:18.17#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.13:07:18.17#ibcon#*before write, iclass 31, count 0 2006.173.13:07:18.17#ibcon#enter sib2, iclass 31, count 0 2006.173.13:07:18.17#ibcon#flushed, iclass 31, count 0 2006.173.13:07:18.17#ibcon#about to write, iclass 31, count 0 2006.173.13:07:18.17#ibcon#wrote, iclass 31, count 0 2006.173.13:07:18.17#ibcon#about to read 3, iclass 31, count 0 2006.173.13:07:18.21#ibcon#read 3, iclass 31, count 0 2006.173.13:07:18.21#ibcon#about to read 4, iclass 31, count 0 2006.173.13:07:18.21#ibcon#read 4, iclass 31, count 0 2006.173.13:07:18.21#ibcon#about to read 5, iclass 31, count 0 2006.173.13:07:18.21#ibcon#read 5, iclass 31, count 0 2006.173.13:07:18.21#ibcon#about to read 6, iclass 31, count 0 2006.173.13:07:18.21#ibcon#read 6, iclass 31, count 0 2006.173.13:07:18.21#ibcon#end of sib2, iclass 31, count 0 2006.173.13:07:18.21#ibcon#*after write, iclass 31, count 0 2006.173.13:07:18.21#ibcon#*before return 0, iclass 31, count 0 2006.173.13:07:18.21#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.13:07:18.21#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.13:07:18.21#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.13:07:18.21#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.13:07:18.21$vck44/vb=5,4 2006.173.13:07:18.21#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.173.13:07:18.21#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.173.13:07:18.21#ibcon#ireg 11 cls_cnt 2 2006.173.13:07:18.21#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.13:07:18.27#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.13:07:18.27#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.13:07:18.27#ibcon#enter wrdev, iclass 33, count 2 2006.173.13:07:18.27#ibcon#first serial, iclass 33, count 2 2006.173.13:07:18.27#ibcon#enter sib2, iclass 33, count 2 2006.173.13:07:18.27#ibcon#flushed, iclass 33, count 2 2006.173.13:07:18.27#ibcon#about to write, iclass 33, count 2 2006.173.13:07:18.27#ibcon#wrote, iclass 33, count 2 2006.173.13:07:18.27#ibcon#about to read 3, iclass 33, count 2 2006.173.13:07:18.29#ibcon#read 3, iclass 33, count 2 2006.173.13:07:18.29#ibcon#about to read 4, iclass 33, count 2 2006.173.13:07:18.29#ibcon#read 4, iclass 33, count 2 2006.173.13:07:18.29#ibcon#about to read 5, iclass 33, count 2 2006.173.13:07:18.29#ibcon#read 5, iclass 33, count 2 2006.173.13:07:18.29#ibcon#about to read 6, iclass 33, count 2 2006.173.13:07:18.29#ibcon#read 6, iclass 33, count 2 2006.173.13:07:18.29#ibcon#end of sib2, iclass 33, count 2 2006.173.13:07:18.29#ibcon#*mode == 0, iclass 33, count 2 2006.173.13:07:18.29#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.173.13:07:18.29#ibcon#[27=AT05-04\r\n] 2006.173.13:07:18.29#ibcon#*before write, iclass 33, count 2 2006.173.13:07:18.29#ibcon#enter sib2, iclass 33, count 2 2006.173.13:07:18.29#ibcon#flushed, iclass 33, count 2 2006.173.13:07:18.29#ibcon#about to write, iclass 33, count 2 2006.173.13:07:18.29#ibcon#wrote, iclass 33, count 2 2006.173.13:07:18.29#ibcon#about to read 3, iclass 33, count 2 2006.173.13:07:18.32#ibcon#read 3, iclass 33, count 2 2006.173.13:07:18.32#ibcon#about to read 4, iclass 33, count 2 2006.173.13:07:18.32#ibcon#read 4, iclass 33, count 2 2006.173.13:07:18.32#ibcon#about to read 5, iclass 33, count 2 2006.173.13:07:18.32#ibcon#read 5, iclass 33, count 2 2006.173.13:07:18.32#ibcon#about to read 6, iclass 33, count 2 2006.173.13:07:18.32#ibcon#read 6, iclass 33, count 2 2006.173.13:07:18.32#ibcon#end of sib2, iclass 33, count 2 2006.173.13:07:18.32#ibcon#*after write, iclass 33, count 2 2006.173.13:07:18.32#ibcon#*before return 0, iclass 33, count 2 2006.173.13:07:18.32#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.13:07:18.32#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.173.13:07:18.32#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.173.13:07:18.32#ibcon#ireg 7 cls_cnt 0 2006.173.13:07:18.32#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.13:07:18.44#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.13:07:18.44#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.13:07:18.44#ibcon#enter wrdev, iclass 33, count 0 2006.173.13:07:18.44#ibcon#first serial, iclass 33, count 0 2006.173.13:07:18.44#ibcon#enter sib2, iclass 33, count 0 2006.173.13:07:18.44#ibcon#flushed, iclass 33, count 0 2006.173.13:07:18.44#ibcon#about to write, iclass 33, count 0 2006.173.13:07:18.44#ibcon#wrote, iclass 33, count 0 2006.173.13:07:18.44#ibcon#about to read 3, iclass 33, count 0 2006.173.13:07:18.46#ibcon#read 3, iclass 33, count 0 2006.173.13:07:18.46#ibcon#about to read 4, iclass 33, count 0 2006.173.13:07:18.46#ibcon#read 4, iclass 33, count 0 2006.173.13:07:18.46#ibcon#about to read 5, iclass 33, count 0 2006.173.13:07:18.46#ibcon#read 5, iclass 33, count 0 2006.173.13:07:18.46#ibcon#about to read 6, iclass 33, count 0 2006.173.13:07:18.46#ibcon#read 6, iclass 33, count 0 2006.173.13:07:18.46#ibcon#end of sib2, iclass 33, count 0 2006.173.13:07:18.46#ibcon#*mode == 0, iclass 33, count 0 2006.173.13:07:18.46#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.13:07:18.46#ibcon#[27=USB\r\n] 2006.173.13:07:18.46#ibcon#*before write, iclass 33, count 0 2006.173.13:07:18.46#ibcon#enter sib2, iclass 33, count 0 2006.173.13:07:18.46#ibcon#flushed, iclass 33, count 0 2006.173.13:07:18.46#ibcon#about to write, iclass 33, count 0 2006.173.13:07:18.46#ibcon#wrote, iclass 33, count 0 2006.173.13:07:18.46#ibcon#about to read 3, iclass 33, count 0 2006.173.13:07:18.49#ibcon#read 3, iclass 33, count 0 2006.173.13:07:18.49#ibcon#about to read 4, iclass 33, count 0 2006.173.13:07:18.49#ibcon#read 4, iclass 33, count 0 2006.173.13:07:18.49#ibcon#about to read 5, iclass 33, count 0 2006.173.13:07:18.49#ibcon#read 5, iclass 33, count 0 2006.173.13:07:18.49#ibcon#about to read 6, iclass 33, count 0 2006.173.13:07:18.49#ibcon#read 6, iclass 33, count 0 2006.173.13:07:18.49#ibcon#end of sib2, iclass 33, count 0 2006.173.13:07:18.49#ibcon#*after write, iclass 33, count 0 2006.173.13:07:18.49#ibcon#*before return 0, iclass 33, count 0 2006.173.13:07:18.49#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.13:07:18.49#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.173.13:07:18.49#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.13:07:18.49#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.13:07:18.49$vck44/vblo=6,719.99 2006.173.13:07:18.49#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.13:07:18.49#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.13:07:18.49#ibcon#ireg 17 cls_cnt 0 2006.173.13:07:18.49#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.13:07:18.49#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.13:07:18.49#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.13:07:18.49#ibcon#enter wrdev, iclass 35, count 0 2006.173.13:07:18.49#ibcon#first serial, iclass 35, count 0 2006.173.13:07:18.49#ibcon#enter sib2, iclass 35, count 0 2006.173.13:07:18.49#ibcon#flushed, iclass 35, count 0 2006.173.13:07:18.49#ibcon#about to write, iclass 35, count 0 2006.173.13:07:18.49#ibcon#wrote, iclass 35, count 0 2006.173.13:07:18.49#ibcon#about to read 3, iclass 35, count 0 2006.173.13:07:18.51#ibcon#read 3, iclass 35, count 0 2006.173.13:07:18.51#ibcon#about to read 4, iclass 35, count 0 2006.173.13:07:18.51#ibcon#read 4, iclass 35, count 0 2006.173.13:07:18.51#ibcon#about to read 5, iclass 35, count 0 2006.173.13:07:18.51#ibcon#read 5, iclass 35, count 0 2006.173.13:07:18.51#ibcon#about to read 6, iclass 35, count 0 2006.173.13:07:18.51#ibcon#read 6, iclass 35, count 0 2006.173.13:07:18.51#ibcon#end of sib2, iclass 35, count 0 2006.173.13:07:18.51#ibcon#*mode == 0, iclass 35, count 0 2006.173.13:07:18.51#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.13:07:18.51#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.13:07:18.51#ibcon#*before write, iclass 35, count 0 2006.173.13:07:18.51#ibcon#enter sib2, iclass 35, count 0 2006.173.13:07:18.51#ibcon#flushed, iclass 35, count 0 2006.173.13:07:18.51#ibcon#about to write, iclass 35, count 0 2006.173.13:07:18.51#ibcon#wrote, iclass 35, count 0 2006.173.13:07:18.51#ibcon#about to read 3, iclass 35, count 0 2006.173.13:07:18.55#ibcon#read 3, iclass 35, count 0 2006.173.13:07:18.55#ibcon#about to read 4, iclass 35, count 0 2006.173.13:07:18.55#ibcon#read 4, iclass 35, count 0 2006.173.13:07:18.55#ibcon#about to read 5, iclass 35, count 0 2006.173.13:07:18.55#ibcon#read 5, iclass 35, count 0 2006.173.13:07:18.55#ibcon#about to read 6, iclass 35, count 0 2006.173.13:07:18.55#ibcon#read 6, iclass 35, count 0 2006.173.13:07:18.55#ibcon#end of sib2, iclass 35, count 0 2006.173.13:07:18.55#ibcon#*after write, iclass 35, count 0 2006.173.13:07:18.55#ibcon#*before return 0, iclass 35, count 0 2006.173.13:07:18.55#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.13:07:18.55#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.13:07:18.55#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.13:07:18.55#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.13:07:18.55$vck44/vb=6,4 2006.173.13:07:18.55#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.173.13:07:18.55#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.173.13:07:18.55#ibcon#ireg 11 cls_cnt 2 2006.173.13:07:18.55#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.13:07:18.61#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.13:07:18.61#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.13:07:18.61#ibcon#enter wrdev, iclass 37, count 2 2006.173.13:07:18.61#ibcon#first serial, iclass 37, count 2 2006.173.13:07:18.61#ibcon#enter sib2, iclass 37, count 2 2006.173.13:07:18.61#ibcon#flushed, iclass 37, count 2 2006.173.13:07:18.61#ibcon#about to write, iclass 37, count 2 2006.173.13:07:18.61#ibcon#wrote, iclass 37, count 2 2006.173.13:07:18.61#ibcon#about to read 3, iclass 37, count 2 2006.173.13:07:18.63#ibcon#read 3, iclass 37, count 2 2006.173.13:07:18.63#ibcon#about to read 4, iclass 37, count 2 2006.173.13:07:18.63#ibcon#read 4, iclass 37, count 2 2006.173.13:07:18.63#ibcon#about to read 5, iclass 37, count 2 2006.173.13:07:18.63#ibcon#read 5, iclass 37, count 2 2006.173.13:07:18.63#ibcon#about to read 6, iclass 37, count 2 2006.173.13:07:18.63#ibcon#read 6, iclass 37, count 2 2006.173.13:07:18.63#ibcon#end of sib2, iclass 37, count 2 2006.173.13:07:18.63#ibcon#*mode == 0, iclass 37, count 2 2006.173.13:07:18.63#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.173.13:07:18.63#ibcon#[27=AT06-04\r\n] 2006.173.13:07:18.63#ibcon#*before write, iclass 37, count 2 2006.173.13:07:18.63#ibcon#enter sib2, iclass 37, count 2 2006.173.13:07:18.63#ibcon#flushed, iclass 37, count 2 2006.173.13:07:18.63#ibcon#about to write, iclass 37, count 2 2006.173.13:07:18.63#ibcon#wrote, iclass 37, count 2 2006.173.13:07:18.63#ibcon#about to read 3, iclass 37, count 2 2006.173.13:07:18.66#ibcon#read 3, iclass 37, count 2 2006.173.13:07:18.66#ibcon#about to read 4, iclass 37, count 2 2006.173.13:07:18.66#ibcon#read 4, iclass 37, count 2 2006.173.13:07:18.66#ibcon#about to read 5, iclass 37, count 2 2006.173.13:07:18.66#ibcon#read 5, iclass 37, count 2 2006.173.13:07:18.66#ibcon#about to read 6, iclass 37, count 2 2006.173.13:07:18.66#ibcon#read 6, iclass 37, count 2 2006.173.13:07:18.66#ibcon#end of sib2, iclass 37, count 2 2006.173.13:07:18.66#ibcon#*after write, iclass 37, count 2 2006.173.13:07:18.66#ibcon#*before return 0, iclass 37, count 2 2006.173.13:07:18.66#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.13:07:18.66#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.173.13:07:18.66#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.173.13:07:18.66#ibcon#ireg 7 cls_cnt 0 2006.173.13:07:18.66#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.13:07:18.78#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.13:07:18.78#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.13:07:18.78#ibcon#enter wrdev, iclass 37, count 0 2006.173.13:07:18.78#ibcon#first serial, iclass 37, count 0 2006.173.13:07:18.78#ibcon#enter sib2, iclass 37, count 0 2006.173.13:07:18.78#ibcon#flushed, iclass 37, count 0 2006.173.13:07:18.78#ibcon#about to write, iclass 37, count 0 2006.173.13:07:18.78#ibcon#wrote, iclass 37, count 0 2006.173.13:07:18.78#ibcon#about to read 3, iclass 37, count 0 2006.173.13:07:18.80#ibcon#read 3, iclass 37, count 0 2006.173.13:07:18.80#ibcon#about to read 4, iclass 37, count 0 2006.173.13:07:18.80#ibcon#read 4, iclass 37, count 0 2006.173.13:07:18.80#ibcon#about to read 5, iclass 37, count 0 2006.173.13:07:18.80#ibcon#read 5, iclass 37, count 0 2006.173.13:07:18.80#ibcon#about to read 6, iclass 37, count 0 2006.173.13:07:18.80#ibcon#read 6, iclass 37, count 0 2006.173.13:07:18.80#ibcon#end of sib2, iclass 37, count 0 2006.173.13:07:18.80#ibcon#*mode == 0, iclass 37, count 0 2006.173.13:07:18.80#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.13:07:18.80#ibcon#[27=USB\r\n] 2006.173.13:07:18.80#ibcon#*before write, iclass 37, count 0 2006.173.13:07:18.80#ibcon#enter sib2, iclass 37, count 0 2006.173.13:07:18.80#ibcon#flushed, iclass 37, count 0 2006.173.13:07:18.80#ibcon#about to write, iclass 37, count 0 2006.173.13:07:18.80#ibcon#wrote, iclass 37, count 0 2006.173.13:07:18.80#ibcon#about to read 3, iclass 37, count 0 2006.173.13:07:18.83#ibcon#read 3, iclass 37, count 0 2006.173.13:07:18.83#ibcon#about to read 4, iclass 37, count 0 2006.173.13:07:18.83#ibcon#read 4, iclass 37, count 0 2006.173.13:07:18.83#ibcon#about to read 5, iclass 37, count 0 2006.173.13:07:18.83#ibcon#read 5, iclass 37, count 0 2006.173.13:07:18.83#ibcon#about to read 6, iclass 37, count 0 2006.173.13:07:18.83#ibcon#read 6, iclass 37, count 0 2006.173.13:07:18.83#ibcon#end of sib2, iclass 37, count 0 2006.173.13:07:18.83#ibcon#*after write, iclass 37, count 0 2006.173.13:07:18.83#ibcon#*before return 0, iclass 37, count 0 2006.173.13:07:18.83#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.13:07:18.83#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.173.13:07:18.83#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.13:07:18.83#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.13:07:18.83$vck44/vblo=7,734.99 2006.173.13:07:18.83#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.13:07:18.83#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.13:07:18.83#ibcon#ireg 17 cls_cnt 0 2006.173.13:07:18.83#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.13:07:18.83#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.13:07:18.83#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.13:07:18.83#ibcon#enter wrdev, iclass 39, count 0 2006.173.13:07:18.83#ibcon#first serial, iclass 39, count 0 2006.173.13:07:18.83#ibcon#enter sib2, iclass 39, count 0 2006.173.13:07:18.83#ibcon#flushed, iclass 39, count 0 2006.173.13:07:18.83#ibcon#about to write, iclass 39, count 0 2006.173.13:07:18.83#ibcon#wrote, iclass 39, count 0 2006.173.13:07:18.83#ibcon#about to read 3, iclass 39, count 0 2006.173.13:07:18.85#ibcon#read 3, iclass 39, count 0 2006.173.13:07:18.85#ibcon#about to read 4, iclass 39, count 0 2006.173.13:07:18.85#ibcon#read 4, iclass 39, count 0 2006.173.13:07:18.85#ibcon#about to read 5, iclass 39, count 0 2006.173.13:07:18.85#ibcon#read 5, iclass 39, count 0 2006.173.13:07:18.85#ibcon#about to read 6, iclass 39, count 0 2006.173.13:07:18.85#ibcon#read 6, iclass 39, count 0 2006.173.13:07:18.85#ibcon#end of sib2, iclass 39, count 0 2006.173.13:07:18.85#ibcon#*mode == 0, iclass 39, count 0 2006.173.13:07:18.85#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.13:07:18.85#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.13:07:18.85#ibcon#*before write, iclass 39, count 0 2006.173.13:07:18.85#ibcon#enter sib2, iclass 39, count 0 2006.173.13:07:18.85#ibcon#flushed, iclass 39, count 0 2006.173.13:07:18.85#ibcon#about to write, iclass 39, count 0 2006.173.13:07:18.85#ibcon#wrote, iclass 39, count 0 2006.173.13:07:18.85#ibcon#about to read 3, iclass 39, count 0 2006.173.13:07:18.89#ibcon#read 3, iclass 39, count 0 2006.173.13:07:18.89#ibcon#about to read 4, iclass 39, count 0 2006.173.13:07:18.89#ibcon#read 4, iclass 39, count 0 2006.173.13:07:18.89#ibcon#about to read 5, iclass 39, count 0 2006.173.13:07:18.89#ibcon#read 5, iclass 39, count 0 2006.173.13:07:18.89#ibcon#about to read 6, iclass 39, count 0 2006.173.13:07:18.89#ibcon#read 6, iclass 39, count 0 2006.173.13:07:18.89#ibcon#end of sib2, iclass 39, count 0 2006.173.13:07:18.89#ibcon#*after write, iclass 39, count 0 2006.173.13:07:18.89#ibcon#*before return 0, iclass 39, count 0 2006.173.13:07:18.89#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.13:07:18.89#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.13:07:18.89#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.13:07:18.89#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.13:07:18.89$vck44/vb=7,4 2006.173.13:07:18.89#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.13:07:18.89#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.13:07:18.89#ibcon#ireg 11 cls_cnt 2 2006.173.13:07:18.89#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.13:07:18.95#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.13:07:18.95#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.13:07:18.95#ibcon#enter wrdev, iclass 3, count 2 2006.173.13:07:18.95#ibcon#first serial, iclass 3, count 2 2006.173.13:07:18.95#ibcon#enter sib2, iclass 3, count 2 2006.173.13:07:18.95#ibcon#flushed, iclass 3, count 2 2006.173.13:07:18.95#ibcon#about to write, iclass 3, count 2 2006.173.13:07:18.95#ibcon#wrote, iclass 3, count 2 2006.173.13:07:18.95#ibcon#about to read 3, iclass 3, count 2 2006.173.13:07:18.97#ibcon#read 3, iclass 3, count 2 2006.173.13:07:18.97#ibcon#about to read 4, iclass 3, count 2 2006.173.13:07:18.97#ibcon#read 4, iclass 3, count 2 2006.173.13:07:18.97#ibcon#about to read 5, iclass 3, count 2 2006.173.13:07:18.97#ibcon#read 5, iclass 3, count 2 2006.173.13:07:18.97#ibcon#about to read 6, iclass 3, count 2 2006.173.13:07:18.97#ibcon#read 6, iclass 3, count 2 2006.173.13:07:18.97#ibcon#end of sib2, iclass 3, count 2 2006.173.13:07:18.97#ibcon#*mode == 0, iclass 3, count 2 2006.173.13:07:18.97#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.13:07:18.97#ibcon#[27=AT07-04\r\n] 2006.173.13:07:18.97#ibcon#*before write, iclass 3, count 2 2006.173.13:07:18.97#ibcon#enter sib2, iclass 3, count 2 2006.173.13:07:18.97#ibcon#flushed, iclass 3, count 2 2006.173.13:07:18.97#ibcon#about to write, iclass 3, count 2 2006.173.13:07:18.97#ibcon#wrote, iclass 3, count 2 2006.173.13:07:18.97#ibcon#about to read 3, iclass 3, count 2 2006.173.13:07:19.00#ibcon#read 3, iclass 3, count 2 2006.173.13:07:19.00#ibcon#about to read 4, iclass 3, count 2 2006.173.13:07:19.00#ibcon#read 4, iclass 3, count 2 2006.173.13:07:19.00#ibcon#about to read 5, iclass 3, count 2 2006.173.13:07:19.00#ibcon#read 5, iclass 3, count 2 2006.173.13:07:19.00#ibcon#about to read 6, iclass 3, count 2 2006.173.13:07:19.00#ibcon#read 6, iclass 3, count 2 2006.173.13:07:19.00#ibcon#end of sib2, iclass 3, count 2 2006.173.13:07:19.00#ibcon#*after write, iclass 3, count 2 2006.173.13:07:19.00#ibcon#*before return 0, iclass 3, count 2 2006.173.13:07:19.00#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.13:07:19.00#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.13:07:19.00#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.13:07:19.00#ibcon#ireg 7 cls_cnt 0 2006.173.13:07:19.00#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.13:07:19.12#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.13:07:19.12#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.13:07:19.12#ibcon#enter wrdev, iclass 3, count 0 2006.173.13:07:19.12#ibcon#first serial, iclass 3, count 0 2006.173.13:07:19.12#ibcon#enter sib2, iclass 3, count 0 2006.173.13:07:19.12#ibcon#flushed, iclass 3, count 0 2006.173.13:07:19.12#ibcon#about to write, iclass 3, count 0 2006.173.13:07:19.12#ibcon#wrote, iclass 3, count 0 2006.173.13:07:19.12#ibcon#about to read 3, iclass 3, count 0 2006.173.13:07:19.14#ibcon#read 3, iclass 3, count 0 2006.173.13:07:19.14#ibcon#about to read 4, iclass 3, count 0 2006.173.13:07:19.14#ibcon#read 4, iclass 3, count 0 2006.173.13:07:19.14#ibcon#about to read 5, iclass 3, count 0 2006.173.13:07:19.14#ibcon#read 5, iclass 3, count 0 2006.173.13:07:19.14#ibcon#about to read 6, iclass 3, count 0 2006.173.13:07:19.14#ibcon#read 6, iclass 3, count 0 2006.173.13:07:19.14#ibcon#end of sib2, iclass 3, count 0 2006.173.13:07:19.14#ibcon#*mode == 0, iclass 3, count 0 2006.173.13:07:19.14#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.13:07:19.14#ibcon#[27=USB\r\n] 2006.173.13:07:19.14#ibcon#*before write, iclass 3, count 0 2006.173.13:07:19.14#ibcon#enter sib2, iclass 3, count 0 2006.173.13:07:19.14#ibcon#flushed, iclass 3, count 0 2006.173.13:07:19.14#ibcon#about to write, iclass 3, count 0 2006.173.13:07:19.14#ibcon#wrote, iclass 3, count 0 2006.173.13:07:19.14#ibcon#about to read 3, iclass 3, count 0 2006.173.13:07:19.17#ibcon#read 3, iclass 3, count 0 2006.173.13:07:19.17#ibcon#about to read 4, iclass 3, count 0 2006.173.13:07:19.17#ibcon#read 4, iclass 3, count 0 2006.173.13:07:19.17#ibcon#about to read 5, iclass 3, count 0 2006.173.13:07:19.17#ibcon#read 5, iclass 3, count 0 2006.173.13:07:19.17#ibcon#about to read 6, iclass 3, count 0 2006.173.13:07:19.17#ibcon#read 6, iclass 3, count 0 2006.173.13:07:19.17#ibcon#end of sib2, iclass 3, count 0 2006.173.13:07:19.17#ibcon#*after write, iclass 3, count 0 2006.173.13:07:19.17#ibcon#*before return 0, iclass 3, count 0 2006.173.13:07:19.17#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.13:07:19.17#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.13:07:19.17#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.13:07:19.17#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.13:07:19.17$vck44/vblo=8,744.99 2006.173.13:07:19.17#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.13:07:19.17#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.13:07:19.17#ibcon#ireg 17 cls_cnt 0 2006.173.13:07:19.17#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.13:07:19.17#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.13:07:19.17#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.13:07:19.17#ibcon#enter wrdev, iclass 5, count 0 2006.173.13:07:19.17#ibcon#first serial, iclass 5, count 0 2006.173.13:07:19.17#ibcon#enter sib2, iclass 5, count 0 2006.173.13:07:19.17#ibcon#flushed, iclass 5, count 0 2006.173.13:07:19.17#ibcon#about to write, iclass 5, count 0 2006.173.13:07:19.17#ibcon#wrote, iclass 5, count 0 2006.173.13:07:19.17#ibcon#about to read 3, iclass 5, count 0 2006.173.13:07:19.19#ibcon#read 3, iclass 5, count 0 2006.173.13:07:19.19#ibcon#about to read 4, iclass 5, count 0 2006.173.13:07:19.19#ibcon#read 4, iclass 5, count 0 2006.173.13:07:19.19#ibcon#about to read 5, iclass 5, count 0 2006.173.13:07:19.19#ibcon#read 5, iclass 5, count 0 2006.173.13:07:19.19#ibcon#about to read 6, iclass 5, count 0 2006.173.13:07:19.19#ibcon#read 6, iclass 5, count 0 2006.173.13:07:19.19#ibcon#end of sib2, iclass 5, count 0 2006.173.13:07:19.19#ibcon#*mode == 0, iclass 5, count 0 2006.173.13:07:19.19#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.13:07:19.19#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.13:07:19.19#ibcon#*before write, iclass 5, count 0 2006.173.13:07:19.19#ibcon#enter sib2, iclass 5, count 0 2006.173.13:07:19.19#ibcon#flushed, iclass 5, count 0 2006.173.13:07:19.19#ibcon#about to write, iclass 5, count 0 2006.173.13:07:19.19#ibcon#wrote, iclass 5, count 0 2006.173.13:07:19.19#ibcon#about to read 3, iclass 5, count 0 2006.173.13:07:19.23#ibcon#read 3, iclass 5, count 0 2006.173.13:07:19.23#ibcon#about to read 4, iclass 5, count 0 2006.173.13:07:19.23#ibcon#read 4, iclass 5, count 0 2006.173.13:07:19.23#ibcon#about to read 5, iclass 5, count 0 2006.173.13:07:19.23#ibcon#read 5, iclass 5, count 0 2006.173.13:07:19.23#ibcon#about to read 6, iclass 5, count 0 2006.173.13:07:19.23#ibcon#read 6, iclass 5, count 0 2006.173.13:07:19.23#ibcon#end of sib2, iclass 5, count 0 2006.173.13:07:19.23#ibcon#*after write, iclass 5, count 0 2006.173.13:07:19.23#ibcon#*before return 0, iclass 5, count 0 2006.173.13:07:19.23#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.13:07:19.23#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.13:07:19.23#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.13:07:19.23#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.13:07:19.23$vck44/vb=8,4 2006.173.13:07:19.23#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.173.13:07:19.23#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.173.13:07:19.23#ibcon#ireg 11 cls_cnt 2 2006.173.13:07:19.23#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.13:07:19.29#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.13:07:19.29#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.13:07:19.29#ibcon#enter wrdev, iclass 7, count 2 2006.173.13:07:19.29#ibcon#first serial, iclass 7, count 2 2006.173.13:07:19.29#ibcon#enter sib2, iclass 7, count 2 2006.173.13:07:19.29#ibcon#flushed, iclass 7, count 2 2006.173.13:07:19.29#ibcon#about to write, iclass 7, count 2 2006.173.13:07:19.29#ibcon#wrote, iclass 7, count 2 2006.173.13:07:19.29#ibcon#about to read 3, iclass 7, count 2 2006.173.13:07:19.31#ibcon#read 3, iclass 7, count 2 2006.173.13:07:19.31#ibcon#about to read 4, iclass 7, count 2 2006.173.13:07:19.31#ibcon#read 4, iclass 7, count 2 2006.173.13:07:19.31#ibcon#about to read 5, iclass 7, count 2 2006.173.13:07:19.31#ibcon#read 5, iclass 7, count 2 2006.173.13:07:19.31#ibcon#about to read 6, iclass 7, count 2 2006.173.13:07:19.31#ibcon#read 6, iclass 7, count 2 2006.173.13:07:19.31#ibcon#end of sib2, iclass 7, count 2 2006.173.13:07:19.31#ibcon#*mode == 0, iclass 7, count 2 2006.173.13:07:19.31#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.173.13:07:19.31#ibcon#[27=AT08-04\r\n] 2006.173.13:07:19.31#ibcon#*before write, iclass 7, count 2 2006.173.13:07:19.31#ibcon#enter sib2, iclass 7, count 2 2006.173.13:07:19.31#ibcon#flushed, iclass 7, count 2 2006.173.13:07:19.31#ibcon#about to write, iclass 7, count 2 2006.173.13:07:19.31#ibcon#wrote, iclass 7, count 2 2006.173.13:07:19.31#ibcon#about to read 3, iclass 7, count 2 2006.173.13:07:19.34#ibcon#read 3, iclass 7, count 2 2006.173.13:07:19.34#ibcon#about to read 4, iclass 7, count 2 2006.173.13:07:19.34#ibcon#read 4, iclass 7, count 2 2006.173.13:07:19.34#ibcon#about to read 5, iclass 7, count 2 2006.173.13:07:19.34#ibcon#read 5, iclass 7, count 2 2006.173.13:07:19.34#ibcon#about to read 6, iclass 7, count 2 2006.173.13:07:19.34#ibcon#read 6, iclass 7, count 2 2006.173.13:07:19.34#ibcon#end of sib2, iclass 7, count 2 2006.173.13:07:19.34#ibcon#*after write, iclass 7, count 2 2006.173.13:07:19.34#ibcon#*before return 0, iclass 7, count 2 2006.173.13:07:19.34#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.13:07:19.34#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.173.13:07:19.34#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.173.13:07:19.34#ibcon#ireg 7 cls_cnt 0 2006.173.13:07:19.34#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.13:07:19.46#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.13:07:19.46#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.13:07:19.46#ibcon#enter wrdev, iclass 7, count 0 2006.173.13:07:19.46#ibcon#first serial, iclass 7, count 0 2006.173.13:07:19.46#ibcon#enter sib2, iclass 7, count 0 2006.173.13:07:19.46#ibcon#flushed, iclass 7, count 0 2006.173.13:07:19.46#ibcon#about to write, iclass 7, count 0 2006.173.13:07:19.46#ibcon#wrote, iclass 7, count 0 2006.173.13:07:19.46#ibcon#about to read 3, iclass 7, count 0 2006.173.13:07:19.48#ibcon#read 3, iclass 7, count 0 2006.173.13:07:19.48#ibcon#about to read 4, iclass 7, count 0 2006.173.13:07:19.48#ibcon#read 4, iclass 7, count 0 2006.173.13:07:19.48#ibcon#about to read 5, iclass 7, count 0 2006.173.13:07:19.48#ibcon#read 5, iclass 7, count 0 2006.173.13:07:19.48#ibcon#about to read 6, iclass 7, count 0 2006.173.13:07:19.48#ibcon#read 6, iclass 7, count 0 2006.173.13:07:19.48#ibcon#end of sib2, iclass 7, count 0 2006.173.13:07:19.48#ibcon#*mode == 0, iclass 7, count 0 2006.173.13:07:19.48#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.13:07:19.48#ibcon#[27=USB\r\n] 2006.173.13:07:19.48#ibcon#*before write, iclass 7, count 0 2006.173.13:07:19.48#ibcon#enter sib2, iclass 7, count 0 2006.173.13:07:19.48#ibcon#flushed, iclass 7, count 0 2006.173.13:07:19.48#ibcon#about to write, iclass 7, count 0 2006.173.13:07:19.48#ibcon#wrote, iclass 7, count 0 2006.173.13:07:19.48#ibcon#about to read 3, iclass 7, count 0 2006.173.13:07:19.51#ibcon#read 3, iclass 7, count 0 2006.173.13:07:19.51#ibcon#about to read 4, iclass 7, count 0 2006.173.13:07:19.51#ibcon#read 4, iclass 7, count 0 2006.173.13:07:19.51#ibcon#about to read 5, iclass 7, count 0 2006.173.13:07:19.51#ibcon#read 5, iclass 7, count 0 2006.173.13:07:19.51#ibcon#about to read 6, iclass 7, count 0 2006.173.13:07:19.51#ibcon#read 6, iclass 7, count 0 2006.173.13:07:19.51#ibcon#end of sib2, iclass 7, count 0 2006.173.13:07:19.51#ibcon#*after write, iclass 7, count 0 2006.173.13:07:19.51#ibcon#*before return 0, iclass 7, count 0 2006.173.13:07:19.51#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.13:07:19.51#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.173.13:07:19.51#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.13:07:19.51#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.13:07:19.51$vck44/vabw=wide 2006.173.13:07:19.51#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.13:07:19.51#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.13:07:19.51#ibcon#ireg 8 cls_cnt 0 2006.173.13:07:19.51#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.13:07:19.51#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.13:07:19.51#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.13:07:19.51#ibcon#enter wrdev, iclass 11, count 0 2006.173.13:07:19.51#ibcon#first serial, iclass 11, count 0 2006.173.13:07:19.51#ibcon#enter sib2, iclass 11, count 0 2006.173.13:07:19.51#ibcon#flushed, iclass 11, count 0 2006.173.13:07:19.51#ibcon#about to write, iclass 11, count 0 2006.173.13:07:19.51#ibcon#wrote, iclass 11, count 0 2006.173.13:07:19.51#ibcon#about to read 3, iclass 11, count 0 2006.173.13:07:19.53#ibcon#read 3, iclass 11, count 0 2006.173.13:07:19.53#ibcon#about to read 4, iclass 11, count 0 2006.173.13:07:19.53#ibcon#read 4, iclass 11, count 0 2006.173.13:07:19.53#ibcon#about to read 5, iclass 11, count 0 2006.173.13:07:19.53#ibcon#read 5, iclass 11, count 0 2006.173.13:07:19.53#ibcon#about to read 6, iclass 11, count 0 2006.173.13:07:19.53#ibcon#read 6, iclass 11, count 0 2006.173.13:07:19.53#ibcon#end of sib2, iclass 11, count 0 2006.173.13:07:19.53#ibcon#*mode == 0, iclass 11, count 0 2006.173.13:07:19.53#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.13:07:19.53#ibcon#[25=BW32\r\n] 2006.173.13:07:19.53#ibcon#*before write, iclass 11, count 0 2006.173.13:07:19.53#ibcon#enter sib2, iclass 11, count 0 2006.173.13:07:19.53#ibcon#flushed, iclass 11, count 0 2006.173.13:07:19.53#ibcon#about to write, iclass 11, count 0 2006.173.13:07:19.53#ibcon#wrote, iclass 11, count 0 2006.173.13:07:19.53#ibcon#about to read 3, iclass 11, count 0 2006.173.13:07:19.56#ibcon#read 3, iclass 11, count 0 2006.173.13:07:19.56#ibcon#about to read 4, iclass 11, count 0 2006.173.13:07:19.56#ibcon#read 4, iclass 11, count 0 2006.173.13:07:19.56#ibcon#about to read 5, iclass 11, count 0 2006.173.13:07:19.56#ibcon#read 5, iclass 11, count 0 2006.173.13:07:19.56#ibcon#about to read 6, iclass 11, count 0 2006.173.13:07:19.56#ibcon#read 6, iclass 11, count 0 2006.173.13:07:19.56#ibcon#end of sib2, iclass 11, count 0 2006.173.13:07:19.56#ibcon#*after write, iclass 11, count 0 2006.173.13:07:19.56#ibcon#*before return 0, iclass 11, count 0 2006.173.13:07:19.56#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.13:07:19.56#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.13:07:19.56#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.13:07:19.56#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.13:07:19.56$vck44/vbbw=wide 2006.173.13:07:19.56#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.13:07:19.56#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.13:07:19.56#ibcon#ireg 8 cls_cnt 0 2006.173.13:07:19.56#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.13:07:19.63#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.13:07:19.63#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.13:07:19.63#ibcon#enter wrdev, iclass 13, count 0 2006.173.13:07:19.63#ibcon#first serial, iclass 13, count 0 2006.173.13:07:19.63#ibcon#enter sib2, iclass 13, count 0 2006.173.13:07:19.63#ibcon#flushed, iclass 13, count 0 2006.173.13:07:19.63#ibcon#about to write, iclass 13, count 0 2006.173.13:07:19.63#ibcon#wrote, iclass 13, count 0 2006.173.13:07:19.63#ibcon#about to read 3, iclass 13, count 0 2006.173.13:07:19.65#ibcon#read 3, iclass 13, count 0 2006.173.13:07:19.65#ibcon#about to read 4, iclass 13, count 0 2006.173.13:07:19.65#ibcon#read 4, iclass 13, count 0 2006.173.13:07:19.65#ibcon#about to read 5, iclass 13, count 0 2006.173.13:07:19.65#ibcon#read 5, iclass 13, count 0 2006.173.13:07:19.65#ibcon#about to read 6, iclass 13, count 0 2006.173.13:07:19.65#ibcon#read 6, iclass 13, count 0 2006.173.13:07:19.65#ibcon#end of sib2, iclass 13, count 0 2006.173.13:07:19.65#ibcon#*mode == 0, iclass 13, count 0 2006.173.13:07:19.65#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.13:07:19.65#ibcon#[27=BW32\r\n] 2006.173.13:07:19.65#ibcon#*before write, iclass 13, count 0 2006.173.13:07:19.65#ibcon#enter sib2, iclass 13, count 0 2006.173.13:07:19.65#ibcon#flushed, iclass 13, count 0 2006.173.13:07:19.65#ibcon#about to write, iclass 13, count 0 2006.173.13:07:19.65#ibcon#wrote, iclass 13, count 0 2006.173.13:07:19.65#ibcon#about to read 3, iclass 13, count 0 2006.173.13:07:19.68#ibcon#read 3, iclass 13, count 0 2006.173.13:07:19.68#ibcon#about to read 4, iclass 13, count 0 2006.173.13:07:19.68#ibcon#read 4, iclass 13, count 0 2006.173.13:07:19.68#ibcon#about to read 5, iclass 13, count 0 2006.173.13:07:19.68#ibcon#read 5, iclass 13, count 0 2006.173.13:07:19.68#ibcon#about to read 6, iclass 13, count 0 2006.173.13:07:19.68#ibcon#read 6, iclass 13, count 0 2006.173.13:07:19.68#ibcon#end of sib2, iclass 13, count 0 2006.173.13:07:19.68#ibcon#*after write, iclass 13, count 0 2006.173.13:07:19.68#ibcon#*before return 0, iclass 13, count 0 2006.173.13:07:19.68#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.13:07:19.68#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.13:07:19.68#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.13:07:19.68#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.13:07:19.68$setupk4/ifdk4 2006.173.13:07:19.68$ifdk4/lo= 2006.173.13:07:19.68$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.13:07:19.68$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.13:07:19.68$ifdk4/patch= 2006.173.13:07:19.68$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.13:07:19.68$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.13:07:19.68$setupk4/!*+20s 2006.173.13:07:25.61#abcon#<5=/05 0.5 1.0 22.14 971004.1\r\n> 2006.173.13:07:25.63#abcon#{5=INTERFACE CLEAR} 2006.173.13:07:25.69#abcon#[5=S1D000X0/0*\r\n] 2006.173.13:07:34.20$setupk4/"tpicd 2006.173.13:07:34.20$setupk4/echo=off 2006.173.13:07:34.20$setupk4/xlog=off 2006.173.13:07:34.20:!2006.173.13:10:30 2006.173.13:07:37.14#trakl#Source acquired 2006.173.13:07:39.14#flagr#flagr/antenna,acquired 2006.173.13:10:30.00:preob 2006.173.13:10:31.14/onsource/TRACKING 2006.173.13:10:31.14:!2006.173.13:10:40 2006.173.13:10:40.00:"tape 2006.173.13:10:40.00:"st=record 2006.173.13:10:40.00:data_valid=on 2006.173.13:10:40.00:midob 2006.173.13:10:40.14/onsource/TRACKING 2006.173.13:10:40.14/wx/22.12,1004.2,97 2006.173.13:10:40.28/cable/+6.5046E-03 2006.173.13:10:41.37/va/01,07,usb,yes,58,62 2006.173.13:10:41.37/va/02,06,usb,yes,58,59 2006.173.13:10:41.37/va/03,05,usb,yes,72,75 2006.173.13:10:41.37/va/04,06,usb,yes,59,62 2006.173.13:10:41.37/va/05,04,usb,yes,47,48 2006.173.13:10:41.37/va/06,03,usb,yes,65,65 2006.173.13:10:41.37/va/07,04,usb,yes,54,55 2006.173.13:10:41.37/va/08,04,usb,yes,46,55 2006.173.13:10:41.60/valo/01,524.99,yes,locked 2006.173.13:10:41.60/valo/02,534.99,yes,locked 2006.173.13:10:41.60/valo/03,564.99,yes,locked 2006.173.13:10:41.60/valo/04,624.99,yes,locked 2006.173.13:10:41.60/valo/05,734.99,yes,locked 2006.173.13:10:41.60/valo/06,814.99,yes,locked 2006.173.13:10:41.60/valo/07,864.99,yes,locked 2006.173.13:10:41.60/valo/08,884.99,yes,locked 2006.173.13:10:42.69/vb/01,04,usb,yes,35,32 2006.173.13:10:42.69/vb/02,04,usb,yes,38,37 2006.173.13:10:42.69/vb/03,04,usb,yes,34,38 2006.173.13:10:42.69/vb/04,04,usb,yes,39,38 2006.173.13:10:42.69/vb/05,04,usb,yes,32,34 2006.173.13:10:42.69/vb/06,04,usb,yes,36,33 2006.173.13:10:42.69/vb/07,04,usb,yes,36,36 2006.173.13:10:42.69/vb/08,04,usb,yes,33,37 2006.173.13:10:42.92/vblo/01,629.99,yes,locked 2006.173.13:10:42.92/vblo/02,634.99,yes,locked 2006.173.13:10:42.92/vblo/03,649.99,yes,locked 2006.173.13:10:42.92/vblo/04,679.99,yes,locked 2006.173.13:10:42.92/vblo/05,709.99,yes,locked 2006.173.13:10:42.92/vblo/06,719.99,yes,locked 2006.173.13:10:42.92/vblo/07,734.99,yes,locked 2006.173.13:10:42.92/vblo/08,744.99,yes,locked 2006.173.13:10:43.07/vabw/8 2006.173.13:10:43.22/vbbw/8 2006.173.13:10:43.31/xfe/off,on,14.5 2006.173.13:10:43.70/ifatt/23,28,28,28 2006.173.13:10:44.08/fmout-gps/S +3.83E-07 2006.173.13:10:44.12:!2006.173.13:11:20 2006.173.13:11:20.00:data_valid=off 2006.173.13:11:20.00:"et 2006.173.13:11:20.00:!+3s 2006.173.13:11:23.01:"tape 2006.173.13:11:23.01:postob 2006.173.13:11:23.17/cable/+6.5053E-03 2006.173.13:11:23.17/wx/22.12,1004.2,97 2006.173.13:11:24.08/fmout-gps/S +3.83E-07 2006.173.13:11:24.08:scan_name=173-1316,jd0606,110 2006.173.13:11:24.08:source=1334-127,133739.78,-125724.7,2000.0,cw 2006.173.13:11:25.13#flagr#flagr/antenna,new-source 2006.173.13:11:25.13:checkk5 2006.173.13:11:25.51/chk_autoobs//k5ts1/ autoobs is running! 2006.173.13:11:25.90/chk_autoobs//k5ts2/ autoobs is running! 2006.173.13:11:26.31/chk_autoobs//k5ts3/ autoobs is running! 2006.173.13:11:26.71/chk_autoobs//k5ts4/ autoobs is running! 2006.173.13:11:27.10/chk_obsdata//k5ts1/T1731310??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.13:11:27.49/chk_obsdata//k5ts2/T1731310??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.13:11:27.89/chk_obsdata//k5ts3/T1731310??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.13:11:28.29/chk_obsdata//k5ts4/T1731310??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.13:11:29.03/k5log//k5ts1_log_newline 2006.173.13:11:29.74/k5log//k5ts2_log_newline 2006.173.13:11:30.46/k5log//k5ts3_log_newline 2006.173.13:11:31.16/k5log//k5ts4_log_newline 2006.173.13:11:31.19/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.13:11:31.19:setupk4=1 2006.173.13:11:31.19$setupk4/echo=on 2006.173.13:11:31.19$setupk4/pcalon 2006.173.13:11:31.19$pcalon/"no phase cal control is implemented here 2006.173.13:11:31.19$setupk4/"tpicd=stop 2006.173.13:11:31.19$setupk4/"rec=synch_on 2006.173.13:11:31.19$setupk4/"rec_mode=128 2006.173.13:11:31.19$setupk4/!* 2006.173.13:11:31.19$setupk4/recpk4 2006.173.13:11:31.19$recpk4/recpatch= 2006.173.13:11:31.19$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.13:11:31.19$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.13:11:31.19$setupk4/vck44 2006.173.13:11:31.19$vck44/valo=1,524.99 2006.173.13:11:31.19#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.13:11:31.19#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.13:11:31.19#ibcon#ireg 17 cls_cnt 0 2006.173.13:11:31.19#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.13:11:31.19#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.13:11:31.19#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.13:11:31.19#ibcon#enter wrdev, iclass 10, count 0 2006.173.13:11:31.19#ibcon#first serial, iclass 10, count 0 2006.173.13:11:31.19#ibcon#enter sib2, iclass 10, count 0 2006.173.13:11:31.19#ibcon#flushed, iclass 10, count 0 2006.173.13:11:31.19#ibcon#about to write, iclass 10, count 0 2006.173.13:11:31.19#ibcon#wrote, iclass 10, count 0 2006.173.13:11:31.19#ibcon#about to read 3, iclass 10, count 0 2006.173.13:11:31.20#ibcon#read 3, iclass 10, count 0 2006.173.13:11:31.20#ibcon#about to read 4, iclass 10, count 0 2006.173.13:11:31.20#ibcon#read 4, iclass 10, count 0 2006.173.13:11:31.20#ibcon#about to read 5, iclass 10, count 0 2006.173.13:11:31.20#ibcon#read 5, iclass 10, count 0 2006.173.13:11:31.20#ibcon#about to read 6, iclass 10, count 0 2006.173.13:11:31.20#ibcon#read 6, iclass 10, count 0 2006.173.13:11:31.20#ibcon#end of sib2, iclass 10, count 0 2006.173.13:11:31.20#ibcon#*mode == 0, iclass 10, count 0 2006.173.13:11:31.20#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.13:11:31.20#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.13:11:31.20#ibcon#*before write, iclass 10, count 0 2006.173.13:11:31.20#ibcon#enter sib2, iclass 10, count 0 2006.173.13:11:31.20#ibcon#flushed, iclass 10, count 0 2006.173.13:11:31.20#ibcon#about to write, iclass 10, count 0 2006.173.13:11:31.20#ibcon#wrote, iclass 10, count 0 2006.173.13:11:31.20#ibcon#about to read 3, iclass 10, count 0 2006.173.13:11:31.25#ibcon#read 3, iclass 10, count 0 2006.173.13:11:31.25#ibcon#about to read 4, iclass 10, count 0 2006.173.13:11:31.25#ibcon#read 4, iclass 10, count 0 2006.173.13:11:31.25#ibcon#about to read 5, iclass 10, count 0 2006.173.13:11:31.25#ibcon#read 5, iclass 10, count 0 2006.173.13:11:31.25#ibcon#about to read 6, iclass 10, count 0 2006.173.13:11:31.25#ibcon#read 6, iclass 10, count 0 2006.173.13:11:31.25#ibcon#end of sib2, iclass 10, count 0 2006.173.13:11:31.25#ibcon#*after write, iclass 10, count 0 2006.173.13:11:31.25#ibcon#*before return 0, iclass 10, count 0 2006.173.13:11:31.25#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.13:11:31.25#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.13:11:31.25#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.13:11:31.25#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.13:11:31.25$vck44/va=1,7 2006.173.13:11:31.25#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.13:11:31.25#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.13:11:31.25#ibcon#ireg 11 cls_cnt 2 2006.173.13:11:31.25#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.13:11:31.25#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.13:11:31.25#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.13:11:31.25#ibcon#enter wrdev, iclass 12, count 2 2006.173.13:11:31.25#ibcon#first serial, iclass 12, count 2 2006.173.13:11:31.25#ibcon#enter sib2, iclass 12, count 2 2006.173.13:11:31.25#ibcon#flushed, iclass 12, count 2 2006.173.13:11:31.25#ibcon#about to write, iclass 12, count 2 2006.173.13:11:31.25#ibcon#wrote, iclass 12, count 2 2006.173.13:11:31.25#ibcon#about to read 3, iclass 12, count 2 2006.173.13:11:31.27#ibcon#read 3, iclass 12, count 2 2006.173.13:11:31.27#ibcon#about to read 4, iclass 12, count 2 2006.173.13:11:31.27#ibcon#read 4, iclass 12, count 2 2006.173.13:11:31.27#ibcon#about to read 5, iclass 12, count 2 2006.173.13:11:31.27#ibcon#read 5, iclass 12, count 2 2006.173.13:11:31.27#ibcon#about to read 6, iclass 12, count 2 2006.173.13:11:31.27#ibcon#read 6, iclass 12, count 2 2006.173.13:11:31.27#ibcon#end of sib2, iclass 12, count 2 2006.173.13:11:31.27#ibcon#*mode == 0, iclass 12, count 2 2006.173.13:11:31.27#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.13:11:31.27#ibcon#[25=AT01-07\r\n] 2006.173.13:11:31.27#ibcon#*before write, iclass 12, count 2 2006.173.13:11:31.27#ibcon#enter sib2, iclass 12, count 2 2006.173.13:11:31.27#ibcon#flushed, iclass 12, count 2 2006.173.13:11:31.27#ibcon#about to write, iclass 12, count 2 2006.173.13:11:31.27#ibcon#wrote, iclass 12, count 2 2006.173.13:11:31.27#ibcon#about to read 3, iclass 12, count 2 2006.173.13:11:31.30#ibcon#read 3, iclass 12, count 2 2006.173.13:11:31.30#ibcon#about to read 4, iclass 12, count 2 2006.173.13:11:31.30#ibcon#read 4, iclass 12, count 2 2006.173.13:11:31.30#ibcon#about to read 5, iclass 12, count 2 2006.173.13:11:31.30#ibcon#read 5, iclass 12, count 2 2006.173.13:11:31.30#ibcon#about to read 6, iclass 12, count 2 2006.173.13:11:31.30#ibcon#read 6, iclass 12, count 2 2006.173.13:11:31.30#ibcon#end of sib2, iclass 12, count 2 2006.173.13:11:31.30#ibcon#*after write, iclass 12, count 2 2006.173.13:11:31.30#ibcon#*before return 0, iclass 12, count 2 2006.173.13:11:31.30#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.13:11:31.30#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.13:11:31.30#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.13:11:31.30#ibcon#ireg 7 cls_cnt 0 2006.173.13:11:31.30#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.13:11:31.42#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.13:11:31.42#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.13:11:31.42#ibcon#enter wrdev, iclass 12, count 0 2006.173.13:11:31.42#ibcon#first serial, iclass 12, count 0 2006.173.13:11:31.42#ibcon#enter sib2, iclass 12, count 0 2006.173.13:11:31.42#ibcon#flushed, iclass 12, count 0 2006.173.13:11:31.42#ibcon#about to write, iclass 12, count 0 2006.173.13:11:31.42#ibcon#wrote, iclass 12, count 0 2006.173.13:11:31.42#ibcon#about to read 3, iclass 12, count 0 2006.173.13:11:31.44#ibcon#read 3, iclass 12, count 0 2006.173.13:11:31.44#ibcon#about to read 4, iclass 12, count 0 2006.173.13:11:31.44#ibcon#read 4, iclass 12, count 0 2006.173.13:11:31.44#ibcon#about to read 5, iclass 12, count 0 2006.173.13:11:31.44#ibcon#read 5, iclass 12, count 0 2006.173.13:11:31.44#ibcon#about to read 6, iclass 12, count 0 2006.173.13:11:31.44#ibcon#read 6, iclass 12, count 0 2006.173.13:11:31.44#ibcon#end of sib2, iclass 12, count 0 2006.173.13:11:31.44#ibcon#*mode == 0, iclass 12, count 0 2006.173.13:11:31.44#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.13:11:31.44#ibcon#[25=USB\r\n] 2006.173.13:11:31.44#ibcon#*before write, iclass 12, count 0 2006.173.13:11:31.44#ibcon#enter sib2, iclass 12, count 0 2006.173.13:11:31.44#ibcon#flushed, iclass 12, count 0 2006.173.13:11:31.44#ibcon#about to write, iclass 12, count 0 2006.173.13:11:31.44#ibcon#wrote, iclass 12, count 0 2006.173.13:11:31.44#ibcon#about to read 3, iclass 12, count 0 2006.173.13:11:31.47#ibcon#read 3, iclass 12, count 0 2006.173.13:11:31.47#ibcon#about to read 4, iclass 12, count 0 2006.173.13:11:31.47#ibcon#read 4, iclass 12, count 0 2006.173.13:11:31.47#ibcon#about to read 5, iclass 12, count 0 2006.173.13:11:31.47#ibcon#read 5, iclass 12, count 0 2006.173.13:11:31.47#ibcon#about to read 6, iclass 12, count 0 2006.173.13:11:31.47#ibcon#read 6, iclass 12, count 0 2006.173.13:11:31.47#ibcon#end of sib2, iclass 12, count 0 2006.173.13:11:31.47#ibcon#*after write, iclass 12, count 0 2006.173.13:11:31.47#ibcon#*before return 0, iclass 12, count 0 2006.173.13:11:31.47#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.13:11:31.47#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.13:11:31.47#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.13:11:31.47#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.13:11:31.47$vck44/valo=2,534.99 2006.173.13:11:31.47#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.13:11:31.47#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.13:11:31.47#ibcon#ireg 17 cls_cnt 0 2006.173.13:11:31.47#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.13:11:31.47#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.13:11:31.47#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.13:11:31.47#ibcon#enter wrdev, iclass 14, count 0 2006.173.13:11:31.47#ibcon#first serial, iclass 14, count 0 2006.173.13:11:31.47#ibcon#enter sib2, iclass 14, count 0 2006.173.13:11:31.47#ibcon#flushed, iclass 14, count 0 2006.173.13:11:31.47#ibcon#about to write, iclass 14, count 0 2006.173.13:11:31.47#ibcon#wrote, iclass 14, count 0 2006.173.13:11:31.47#ibcon#about to read 3, iclass 14, count 0 2006.173.13:11:31.49#ibcon#read 3, iclass 14, count 0 2006.173.13:11:31.49#ibcon#about to read 4, iclass 14, count 0 2006.173.13:11:31.49#ibcon#read 4, iclass 14, count 0 2006.173.13:11:31.49#ibcon#about to read 5, iclass 14, count 0 2006.173.13:11:31.49#ibcon#read 5, iclass 14, count 0 2006.173.13:11:31.49#ibcon#about to read 6, iclass 14, count 0 2006.173.13:11:31.49#ibcon#read 6, iclass 14, count 0 2006.173.13:11:31.49#ibcon#end of sib2, iclass 14, count 0 2006.173.13:11:31.49#ibcon#*mode == 0, iclass 14, count 0 2006.173.13:11:31.49#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.13:11:31.49#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.13:11:31.49#ibcon#*before write, iclass 14, count 0 2006.173.13:11:31.49#ibcon#enter sib2, iclass 14, count 0 2006.173.13:11:31.49#ibcon#flushed, iclass 14, count 0 2006.173.13:11:31.49#ibcon#about to write, iclass 14, count 0 2006.173.13:11:31.49#ibcon#wrote, iclass 14, count 0 2006.173.13:11:31.49#ibcon#about to read 3, iclass 14, count 0 2006.173.13:11:31.53#ibcon#read 3, iclass 14, count 0 2006.173.13:11:31.53#ibcon#about to read 4, iclass 14, count 0 2006.173.13:11:31.53#ibcon#read 4, iclass 14, count 0 2006.173.13:11:31.53#ibcon#about to read 5, iclass 14, count 0 2006.173.13:11:31.53#ibcon#read 5, iclass 14, count 0 2006.173.13:11:31.53#ibcon#about to read 6, iclass 14, count 0 2006.173.13:11:31.53#ibcon#read 6, iclass 14, count 0 2006.173.13:11:31.53#ibcon#end of sib2, iclass 14, count 0 2006.173.13:11:31.53#ibcon#*after write, iclass 14, count 0 2006.173.13:11:31.53#ibcon#*before return 0, iclass 14, count 0 2006.173.13:11:31.53#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.13:11:31.53#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.13:11:31.53#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.13:11:31.53#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.13:11:31.53$vck44/va=2,6 2006.173.13:11:31.53#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.13:11:31.53#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.13:11:31.53#ibcon#ireg 11 cls_cnt 2 2006.173.13:11:31.53#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.13:11:31.59#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.13:11:31.59#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.13:11:31.59#ibcon#enter wrdev, iclass 16, count 2 2006.173.13:11:31.59#ibcon#first serial, iclass 16, count 2 2006.173.13:11:31.59#ibcon#enter sib2, iclass 16, count 2 2006.173.13:11:31.59#ibcon#flushed, iclass 16, count 2 2006.173.13:11:31.59#ibcon#about to write, iclass 16, count 2 2006.173.13:11:31.59#ibcon#wrote, iclass 16, count 2 2006.173.13:11:31.59#ibcon#about to read 3, iclass 16, count 2 2006.173.13:11:31.61#ibcon#read 3, iclass 16, count 2 2006.173.13:11:31.61#ibcon#about to read 4, iclass 16, count 2 2006.173.13:11:31.61#ibcon#read 4, iclass 16, count 2 2006.173.13:11:31.61#ibcon#about to read 5, iclass 16, count 2 2006.173.13:11:31.61#ibcon#read 5, iclass 16, count 2 2006.173.13:11:31.61#ibcon#about to read 6, iclass 16, count 2 2006.173.13:11:31.61#ibcon#read 6, iclass 16, count 2 2006.173.13:11:31.61#ibcon#end of sib2, iclass 16, count 2 2006.173.13:11:31.61#ibcon#*mode == 0, iclass 16, count 2 2006.173.13:11:31.61#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.13:11:31.61#ibcon#[25=AT02-06\r\n] 2006.173.13:11:31.61#ibcon#*before write, iclass 16, count 2 2006.173.13:11:31.61#ibcon#enter sib2, iclass 16, count 2 2006.173.13:11:31.61#ibcon#flushed, iclass 16, count 2 2006.173.13:11:31.61#ibcon#about to write, iclass 16, count 2 2006.173.13:11:31.61#ibcon#wrote, iclass 16, count 2 2006.173.13:11:31.61#ibcon#about to read 3, iclass 16, count 2 2006.173.13:11:31.64#ibcon#read 3, iclass 16, count 2 2006.173.13:11:31.64#ibcon#about to read 4, iclass 16, count 2 2006.173.13:11:31.64#ibcon#read 4, iclass 16, count 2 2006.173.13:11:31.64#ibcon#about to read 5, iclass 16, count 2 2006.173.13:11:31.64#ibcon#read 5, iclass 16, count 2 2006.173.13:11:31.64#ibcon#about to read 6, iclass 16, count 2 2006.173.13:11:31.64#ibcon#read 6, iclass 16, count 2 2006.173.13:11:31.64#ibcon#end of sib2, iclass 16, count 2 2006.173.13:11:31.64#ibcon#*after write, iclass 16, count 2 2006.173.13:11:31.64#ibcon#*before return 0, iclass 16, count 2 2006.173.13:11:31.64#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.13:11:31.64#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.13:11:31.64#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.13:11:31.64#ibcon#ireg 7 cls_cnt 0 2006.173.13:11:31.64#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.13:11:31.76#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.13:11:31.76#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.13:11:31.76#ibcon#enter wrdev, iclass 16, count 0 2006.173.13:11:31.76#ibcon#first serial, iclass 16, count 0 2006.173.13:11:31.76#ibcon#enter sib2, iclass 16, count 0 2006.173.13:11:31.76#ibcon#flushed, iclass 16, count 0 2006.173.13:11:31.76#ibcon#about to write, iclass 16, count 0 2006.173.13:11:31.76#ibcon#wrote, iclass 16, count 0 2006.173.13:11:31.76#ibcon#about to read 3, iclass 16, count 0 2006.173.13:11:31.78#ibcon#read 3, iclass 16, count 0 2006.173.13:11:31.78#ibcon#about to read 4, iclass 16, count 0 2006.173.13:11:31.78#ibcon#read 4, iclass 16, count 0 2006.173.13:11:31.78#ibcon#about to read 5, iclass 16, count 0 2006.173.13:11:31.78#ibcon#read 5, iclass 16, count 0 2006.173.13:11:31.78#ibcon#about to read 6, iclass 16, count 0 2006.173.13:11:31.78#ibcon#read 6, iclass 16, count 0 2006.173.13:11:31.78#ibcon#end of sib2, iclass 16, count 0 2006.173.13:11:31.78#ibcon#*mode == 0, iclass 16, count 0 2006.173.13:11:31.78#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.13:11:31.78#ibcon#[25=USB\r\n] 2006.173.13:11:31.78#ibcon#*before write, iclass 16, count 0 2006.173.13:11:31.78#ibcon#enter sib2, iclass 16, count 0 2006.173.13:11:31.78#ibcon#flushed, iclass 16, count 0 2006.173.13:11:31.78#ibcon#about to write, iclass 16, count 0 2006.173.13:11:31.78#ibcon#wrote, iclass 16, count 0 2006.173.13:11:31.78#ibcon#about to read 3, iclass 16, count 0 2006.173.13:11:31.81#ibcon#read 3, iclass 16, count 0 2006.173.13:11:31.81#ibcon#about to read 4, iclass 16, count 0 2006.173.13:11:31.81#ibcon#read 4, iclass 16, count 0 2006.173.13:11:31.81#ibcon#about to read 5, iclass 16, count 0 2006.173.13:11:31.81#ibcon#read 5, iclass 16, count 0 2006.173.13:11:31.81#ibcon#about to read 6, iclass 16, count 0 2006.173.13:11:31.81#ibcon#read 6, iclass 16, count 0 2006.173.13:11:31.81#ibcon#end of sib2, iclass 16, count 0 2006.173.13:11:31.81#ibcon#*after write, iclass 16, count 0 2006.173.13:11:31.81#ibcon#*before return 0, iclass 16, count 0 2006.173.13:11:31.81#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.13:11:31.81#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.13:11:31.81#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.13:11:31.81#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.13:11:31.81$vck44/valo=3,564.99 2006.173.13:11:31.81#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.13:11:31.81#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.13:11:31.81#ibcon#ireg 17 cls_cnt 0 2006.173.13:11:31.81#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.13:11:31.81#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.13:11:31.81#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.13:11:31.81#ibcon#enter wrdev, iclass 18, count 0 2006.173.13:11:31.81#ibcon#first serial, iclass 18, count 0 2006.173.13:11:31.81#ibcon#enter sib2, iclass 18, count 0 2006.173.13:11:31.81#ibcon#flushed, iclass 18, count 0 2006.173.13:11:31.81#ibcon#about to write, iclass 18, count 0 2006.173.13:11:31.81#ibcon#wrote, iclass 18, count 0 2006.173.13:11:31.81#ibcon#about to read 3, iclass 18, count 0 2006.173.13:11:31.83#ibcon#read 3, iclass 18, count 0 2006.173.13:11:31.83#ibcon#about to read 4, iclass 18, count 0 2006.173.13:11:31.83#ibcon#read 4, iclass 18, count 0 2006.173.13:11:31.83#ibcon#about to read 5, iclass 18, count 0 2006.173.13:11:31.83#ibcon#read 5, iclass 18, count 0 2006.173.13:11:31.83#ibcon#about to read 6, iclass 18, count 0 2006.173.13:11:31.83#ibcon#read 6, iclass 18, count 0 2006.173.13:11:31.83#ibcon#end of sib2, iclass 18, count 0 2006.173.13:11:31.83#ibcon#*mode == 0, iclass 18, count 0 2006.173.13:11:31.83#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.13:11:31.83#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.13:11:31.83#ibcon#*before write, iclass 18, count 0 2006.173.13:11:31.83#ibcon#enter sib2, iclass 18, count 0 2006.173.13:11:31.83#ibcon#flushed, iclass 18, count 0 2006.173.13:11:31.83#ibcon#about to write, iclass 18, count 0 2006.173.13:11:31.83#ibcon#wrote, iclass 18, count 0 2006.173.13:11:31.83#ibcon#about to read 3, iclass 18, count 0 2006.173.13:11:31.87#ibcon#read 3, iclass 18, count 0 2006.173.13:11:31.87#ibcon#about to read 4, iclass 18, count 0 2006.173.13:11:31.87#ibcon#read 4, iclass 18, count 0 2006.173.13:11:31.87#ibcon#about to read 5, iclass 18, count 0 2006.173.13:11:31.87#ibcon#read 5, iclass 18, count 0 2006.173.13:11:31.87#ibcon#about to read 6, iclass 18, count 0 2006.173.13:11:31.87#ibcon#read 6, iclass 18, count 0 2006.173.13:11:31.87#ibcon#end of sib2, iclass 18, count 0 2006.173.13:11:31.87#ibcon#*after write, iclass 18, count 0 2006.173.13:11:31.87#ibcon#*before return 0, iclass 18, count 0 2006.173.13:11:31.87#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.13:11:31.87#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.13:11:31.87#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.13:11:31.87#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.13:11:31.87$vck44/va=3,5 2006.173.13:11:31.87#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.13:11:31.87#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.13:11:31.87#ibcon#ireg 11 cls_cnt 2 2006.173.13:11:31.87#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.13:11:31.93#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.13:11:31.93#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.13:11:31.93#ibcon#enter wrdev, iclass 20, count 2 2006.173.13:11:31.93#ibcon#first serial, iclass 20, count 2 2006.173.13:11:31.93#ibcon#enter sib2, iclass 20, count 2 2006.173.13:11:31.93#ibcon#flushed, iclass 20, count 2 2006.173.13:11:31.93#ibcon#about to write, iclass 20, count 2 2006.173.13:11:31.93#ibcon#wrote, iclass 20, count 2 2006.173.13:11:31.93#ibcon#about to read 3, iclass 20, count 2 2006.173.13:11:31.95#ibcon#read 3, iclass 20, count 2 2006.173.13:11:31.95#ibcon#about to read 4, iclass 20, count 2 2006.173.13:11:31.95#ibcon#read 4, iclass 20, count 2 2006.173.13:11:31.95#ibcon#about to read 5, iclass 20, count 2 2006.173.13:11:31.95#ibcon#read 5, iclass 20, count 2 2006.173.13:11:31.95#ibcon#about to read 6, iclass 20, count 2 2006.173.13:11:31.95#ibcon#read 6, iclass 20, count 2 2006.173.13:11:31.95#ibcon#end of sib2, iclass 20, count 2 2006.173.13:11:31.95#ibcon#*mode == 0, iclass 20, count 2 2006.173.13:11:31.95#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.13:11:31.95#ibcon#[25=AT03-05\r\n] 2006.173.13:11:31.95#ibcon#*before write, iclass 20, count 2 2006.173.13:11:31.95#ibcon#enter sib2, iclass 20, count 2 2006.173.13:11:31.95#ibcon#flushed, iclass 20, count 2 2006.173.13:11:31.95#ibcon#about to write, iclass 20, count 2 2006.173.13:11:31.95#ibcon#wrote, iclass 20, count 2 2006.173.13:11:31.95#ibcon#about to read 3, iclass 20, count 2 2006.173.13:11:31.98#ibcon#read 3, iclass 20, count 2 2006.173.13:11:31.98#ibcon#about to read 4, iclass 20, count 2 2006.173.13:11:31.98#ibcon#read 4, iclass 20, count 2 2006.173.13:11:31.98#ibcon#about to read 5, iclass 20, count 2 2006.173.13:11:31.98#ibcon#read 5, iclass 20, count 2 2006.173.13:11:31.98#ibcon#about to read 6, iclass 20, count 2 2006.173.13:11:31.98#ibcon#read 6, iclass 20, count 2 2006.173.13:11:31.98#ibcon#end of sib2, iclass 20, count 2 2006.173.13:11:31.98#ibcon#*after write, iclass 20, count 2 2006.173.13:11:31.98#ibcon#*before return 0, iclass 20, count 2 2006.173.13:11:31.98#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.13:11:31.98#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.13:11:31.98#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.13:11:31.98#ibcon#ireg 7 cls_cnt 0 2006.173.13:11:31.98#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.13:11:32.10#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.13:11:32.10#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.13:11:32.10#ibcon#enter wrdev, iclass 20, count 0 2006.173.13:11:32.10#ibcon#first serial, iclass 20, count 0 2006.173.13:11:32.10#ibcon#enter sib2, iclass 20, count 0 2006.173.13:11:32.10#ibcon#flushed, iclass 20, count 0 2006.173.13:11:32.10#ibcon#about to write, iclass 20, count 0 2006.173.13:11:32.10#ibcon#wrote, iclass 20, count 0 2006.173.13:11:32.10#ibcon#about to read 3, iclass 20, count 0 2006.173.13:11:32.12#ibcon#read 3, iclass 20, count 0 2006.173.13:11:32.12#ibcon#about to read 4, iclass 20, count 0 2006.173.13:11:32.12#ibcon#read 4, iclass 20, count 0 2006.173.13:11:32.12#ibcon#about to read 5, iclass 20, count 0 2006.173.13:11:32.12#ibcon#read 5, iclass 20, count 0 2006.173.13:11:32.12#ibcon#about to read 6, iclass 20, count 0 2006.173.13:11:32.12#ibcon#read 6, iclass 20, count 0 2006.173.13:11:32.12#ibcon#end of sib2, iclass 20, count 0 2006.173.13:11:32.12#ibcon#*mode == 0, iclass 20, count 0 2006.173.13:11:32.12#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.13:11:32.12#ibcon#[25=USB\r\n] 2006.173.13:11:32.12#ibcon#*before write, iclass 20, count 0 2006.173.13:11:32.12#ibcon#enter sib2, iclass 20, count 0 2006.173.13:11:32.12#ibcon#flushed, iclass 20, count 0 2006.173.13:11:32.12#ibcon#about to write, iclass 20, count 0 2006.173.13:11:32.12#ibcon#wrote, iclass 20, count 0 2006.173.13:11:32.12#ibcon#about to read 3, iclass 20, count 0 2006.173.13:11:32.15#ibcon#read 3, iclass 20, count 0 2006.173.13:11:32.15#ibcon#about to read 4, iclass 20, count 0 2006.173.13:11:32.15#ibcon#read 4, iclass 20, count 0 2006.173.13:11:32.15#ibcon#about to read 5, iclass 20, count 0 2006.173.13:11:32.15#ibcon#read 5, iclass 20, count 0 2006.173.13:11:32.15#ibcon#about to read 6, iclass 20, count 0 2006.173.13:11:32.15#ibcon#read 6, iclass 20, count 0 2006.173.13:11:32.15#ibcon#end of sib2, iclass 20, count 0 2006.173.13:11:32.15#ibcon#*after write, iclass 20, count 0 2006.173.13:11:32.15#ibcon#*before return 0, iclass 20, count 0 2006.173.13:11:32.15#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.13:11:32.15#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.13:11:32.15#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.13:11:32.15#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.13:11:32.15$vck44/valo=4,624.99 2006.173.13:11:32.15#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.13:11:32.15#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.13:11:32.15#ibcon#ireg 17 cls_cnt 0 2006.173.13:11:32.15#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.13:11:32.15#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.13:11:32.15#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.13:11:32.15#ibcon#enter wrdev, iclass 22, count 0 2006.173.13:11:32.15#ibcon#first serial, iclass 22, count 0 2006.173.13:11:32.15#ibcon#enter sib2, iclass 22, count 0 2006.173.13:11:32.15#ibcon#flushed, iclass 22, count 0 2006.173.13:11:32.15#ibcon#about to write, iclass 22, count 0 2006.173.13:11:32.15#ibcon#wrote, iclass 22, count 0 2006.173.13:11:32.15#ibcon#about to read 3, iclass 22, count 0 2006.173.13:11:32.17#ibcon#read 3, iclass 22, count 0 2006.173.13:11:32.17#ibcon#about to read 4, iclass 22, count 0 2006.173.13:11:32.17#ibcon#read 4, iclass 22, count 0 2006.173.13:11:32.17#ibcon#about to read 5, iclass 22, count 0 2006.173.13:11:32.17#ibcon#read 5, iclass 22, count 0 2006.173.13:11:32.17#ibcon#about to read 6, iclass 22, count 0 2006.173.13:11:32.17#ibcon#read 6, iclass 22, count 0 2006.173.13:11:32.17#ibcon#end of sib2, iclass 22, count 0 2006.173.13:11:32.17#ibcon#*mode == 0, iclass 22, count 0 2006.173.13:11:32.17#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.13:11:32.17#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.13:11:32.17#ibcon#*before write, iclass 22, count 0 2006.173.13:11:32.17#ibcon#enter sib2, iclass 22, count 0 2006.173.13:11:32.17#ibcon#flushed, iclass 22, count 0 2006.173.13:11:32.17#ibcon#about to write, iclass 22, count 0 2006.173.13:11:32.17#ibcon#wrote, iclass 22, count 0 2006.173.13:11:32.17#ibcon#about to read 3, iclass 22, count 0 2006.173.13:11:32.21#ibcon#read 3, iclass 22, count 0 2006.173.13:11:32.21#ibcon#about to read 4, iclass 22, count 0 2006.173.13:11:32.21#ibcon#read 4, iclass 22, count 0 2006.173.13:11:32.21#ibcon#about to read 5, iclass 22, count 0 2006.173.13:11:32.21#ibcon#read 5, iclass 22, count 0 2006.173.13:11:32.21#ibcon#about to read 6, iclass 22, count 0 2006.173.13:11:32.21#ibcon#read 6, iclass 22, count 0 2006.173.13:11:32.21#ibcon#end of sib2, iclass 22, count 0 2006.173.13:11:32.21#ibcon#*after write, iclass 22, count 0 2006.173.13:11:32.21#ibcon#*before return 0, iclass 22, count 0 2006.173.13:11:32.21#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.13:11:32.21#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.13:11:32.21#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.13:11:32.21#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.13:11:32.21$vck44/va=4,6 2006.173.13:11:32.21#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.13:11:32.21#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.13:11:32.21#ibcon#ireg 11 cls_cnt 2 2006.173.13:11:32.21#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.13:11:32.27#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.13:11:32.27#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.13:11:32.27#ibcon#enter wrdev, iclass 24, count 2 2006.173.13:11:32.27#ibcon#first serial, iclass 24, count 2 2006.173.13:11:32.27#ibcon#enter sib2, iclass 24, count 2 2006.173.13:11:32.27#ibcon#flushed, iclass 24, count 2 2006.173.13:11:32.27#ibcon#about to write, iclass 24, count 2 2006.173.13:11:32.27#ibcon#wrote, iclass 24, count 2 2006.173.13:11:32.27#ibcon#about to read 3, iclass 24, count 2 2006.173.13:11:32.29#ibcon#read 3, iclass 24, count 2 2006.173.13:11:32.29#ibcon#about to read 4, iclass 24, count 2 2006.173.13:11:32.29#ibcon#read 4, iclass 24, count 2 2006.173.13:11:32.29#ibcon#about to read 5, iclass 24, count 2 2006.173.13:11:32.29#ibcon#read 5, iclass 24, count 2 2006.173.13:11:32.29#ibcon#about to read 6, iclass 24, count 2 2006.173.13:11:32.29#ibcon#read 6, iclass 24, count 2 2006.173.13:11:32.29#ibcon#end of sib2, iclass 24, count 2 2006.173.13:11:32.29#ibcon#*mode == 0, iclass 24, count 2 2006.173.13:11:32.29#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.13:11:32.29#ibcon#[25=AT04-06\r\n] 2006.173.13:11:32.29#ibcon#*before write, iclass 24, count 2 2006.173.13:11:32.29#ibcon#enter sib2, iclass 24, count 2 2006.173.13:11:32.29#ibcon#flushed, iclass 24, count 2 2006.173.13:11:32.29#ibcon#about to write, iclass 24, count 2 2006.173.13:11:32.29#ibcon#wrote, iclass 24, count 2 2006.173.13:11:32.29#ibcon#about to read 3, iclass 24, count 2 2006.173.13:11:32.32#ibcon#read 3, iclass 24, count 2 2006.173.13:11:32.32#ibcon#about to read 4, iclass 24, count 2 2006.173.13:11:32.32#ibcon#read 4, iclass 24, count 2 2006.173.13:11:32.32#ibcon#about to read 5, iclass 24, count 2 2006.173.13:11:32.32#ibcon#read 5, iclass 24, count 2 2006.173.13:11:32.32#ibcon#about to read 6, iclass 24, count 2 2006.173.13:11:32.32#ibcon#read 6, iclass 24, count 2 2006.173.13:11:32.32#ibcon#end of sib2, iclass 24, count 2 2006.173.13:11:32.32#ibcon#*after write, iclass 24, count 2 2006.173.13:11:32.32#ibcon#*before return 0, iclass 24, count 2 2006.173.13:11:32.32#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.13:11:32.32#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.13:11:32.32#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.13:11:32.32#ibcon#ireg 7 cls_cnt 0 2006.173.13:11:32.32#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.13:11:32.44#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.13:11:32.44#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.13:11:32.44#ibcon#enter wrdev, iclass 24, count 0 2006.173.13:11:32.44#ibcon#first serial, iclass 24, count 0 2006.173.13:11:32.44#ibcon#enter sib2, iclass 24, count 0 2006.173.13:11:32.44#ibcon#flushed, iclass 24, count 0 2006.173.13:11:32.44#ibcon#about to write, iclass 24, count 0 2006.173.13:11:32.44#ibcon#wrote, iclass 24, count 0 2006.173.13:11:32.44#ibcon#about to read 3, iclass 24, count 0 2006.173.13:11:32.46#ibcon#read 3, iclass 24, count 0 2006.173.13:11:32.46#ibcon#about to read 4, iclass 24, count 0 2006.173.13:11:32.46#ibcon#read 4, iclass 24, count 0 2006.173.13:11:32.46#ibcon#about to read 5, iclass 24, count 0 2006.173.13:11:32.46#ibcon#read 5, iclass 24, count 0 2006.173.13:11:32.46#ibcon#about to read 6, iclass 24, count 0 2006.173.13:11:32.46#ibcon#read 6, iclass 24, count 0 2006.173.13:11:32.46#ibcon#end of sib2, iclass 24, count 0 2006.173.13:11:32.46#ibcon#*mode == 0, iclass 24, count 0 2006.173.13:11:32.46#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.13:11:32.46#ibcon#[25=USB\r\n] 2006.173.13:11:32.46#ibcon#*before write, iclass 24, count 0 2006.173.13:11:32.46#ibcon#enter sib2, iclass 24, count 0 2006.173.13:11:32.46#ibcon#flushed, iclass 24, count 0 2006.173.13:11:32.46#ibcon#about to write, iclass 24, count 0 2006.173.13:11:32.46#ibcon#wrote, iclass 24, count 0 2006.173.13:11:32.46#ibcon#about to read 3, iclass 24, count 0 2006.173.13:11:32.49#ibcon#read 3, iclass 24, count 0 2006.173.13:11:32.49#ibcon#about to read 4, iclass 24, count 0 2006.173.13:11:32.49#ibcon#read 4, iclass 24, count 0 2006.173.13:11:32.49#ibcon#about to read 5, iclass 24, count 0 2006.173.13:11:32.49#ibcon#read 5, iclass 24, count 0 2006.173.13:11:32.49#ibcon#about to read 6, iclass 24, count 0 2006.173.13:11:32.49#ibcon#read 6, iclass 24, count 0 2006.173.13:11:32.49#ibcon#end of sib2, iclass 24, count 0 2006.173.13:11:32.49#ibcon#*after write, iclass 24, count 0 2006.173.13:11:32.49#ibcon#*before return 0, iclass 24, count 0 2006.173.13:11:32.49#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.13:11:32.49#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.13:11:32.49#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.13:11:32.49#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.13:11:32.49$vck44/valo=5,734.99 2006.173.13:11:32.49#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.13:11:32.49#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.13:11:32.49#ibcon#ireg 17 cls_cnt 0 2006.173.13:11:32.49#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.13:11:32.49#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.13:11:32.49#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.13:11:32.49#ibcon#enter wrdev, iclass 26, count 0 2006.173.13:11:32.49#ibcon#first serial, iclass 26, count 0 2006.173.13:11:32.49#ibcon#enter sib2, iclass 26, count 0 2006.173.13:11:32.49#ibcon#flushed, iclass 26, count 0 2006.173.13:11:32.49#ibcon#about to write, iclass 26, count 0 2006.173.13:11:32.49#ibcon#wrote, iclass 26, count 0 2006.173.13:11:32.49#ibcon#about to read 3, iclass 26, count 0 2006.173.13:11:32.51#ibcon#read 3, iclass 26, count 0 2006.173.13:11:32.51#ibcon#about to read 4, iclass 26, count 0 2006.173.13:11:32.51#ibcon#read 4, iclass 26, count 0 2006.173.13:11:32.51#ibcon#about to read 5, iclass 26, count 0 2006.173.13:11:32.51#ibcon#read 5, iclass 26, count 0 2006.173.13:11:32.51#ibcon#about to read 6, iclass 26, count 0 2006.173.13:11:32.51#ibcon#read 6, iclass 26, count 0 2006.173.13:11:32.51#ibcon#end of sib2, iclass 26, count 0 2006.173.13:11:32.51#ibcon#*mode == 0, iclass 26, count 0 2006.173.13:11:32.51#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.13:11:32.51#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.13:11:32.51#ibcon#*before write, iclass 26, count 0 2006.173.13:11:32.51#ibcon#enter sib2, iclass 26, count 0 2006.173.13:11:32.51#ibcon#flushed, iclass 26, count 0 2006.173.13:11:32.51#ibcon#about to write, iclass 26, count 0 2006.173.13:11:32.51#ibcon#wrote, iclass 26, count 0 2006.173.13:11:32.51#ibcon#about to read 3, iclass 26, count 0 2006.173.13:11:32.55#ibcon#read 3, iclass 26, count 0 2006.173.13:11:32.55#ibcon#about to read 4, iclass 26, count 0 2006.173.13:11:32.55#ibcon#read 4, iclass 26, count 0 2006.173.13:11:32.55#ibcon#about to read 5, iclass 26, count 0 2006.173.13:11:32.55#ibcon#read 5, iclass 26, count 0 2006.173.13:11:32.55#ibcon#about to read 6, iclass 26, count 0 2006.173.13:11:32.55#ibcon#read 6, iclass 26, count 0 2006.173.13:11:32.55#ibcon#end of sib2, iclass 26, count 0 2006.173.13:11:32.55#ibcon#*after write, iclass 26, count 0 2006.173.13:11:32.55#ibcon#*before return 0, iclass 26, count 0 2006.173.13:11:32.55#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.13:11:32.55#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.13:11:32.55#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.13:11:32.55#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.13:11:32.55$vck44/va=5,4 2006.173.13:11:32.55#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.13:11:32.55#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.13:11:32.55#ibcon#ireg 11 cls_cnt 2 2006.173.13:11:32.55#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.13:11:32.61#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.13:11:32.61#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.13:11:32.61#ibcon#enter wrdev, iclass 28, count 2 2006.173.13:11:32.61#ibcon#first serial, iclass 28, count 2 2006.173.13:11:32.61#ibcon#enter sib2, iclass 28, count 2 2006.173.13:11:32.61#ibcon#flushed, iclass 28, count 2 2006.173.13:11:32.61#ibcon#about to write, iclass 28, count 2 2006.173.13:11:32.61#ibcon#wrote, iclass 28, count 2 2006.173.13:11:32.61#ibcon#about to read 3, iclass 28, count 2 2006.173.13:11:32.63#ibcon#read 3, iclass 28, count 2 2006.173.13:11:32.63#ibcon#about to read 4, iclass 28, count 2 2006.173.13:11:32.63#ibcon#read 4, iclass 28, count 2 2006.173.13:11:32.63#ibcon#about to read 5, iclass 28, count 2 2006.173.13:11:32.63#ibcon#read 5, iclass 28, count 2 2006.173.13:11:32.63#ibcon#about to read 6, iclass 28, count 2 2006.173.13:11:32.63#ibcon#read 6, iclass 28, count 2 2006.173.13:11:32.63#ibcon#end of sib2, iclass 28, count 2 2006.173.13:11:32.63#ibcon#*mode == 0, iclass 28, count 2 2006.173.13:11:32.63#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.13:11:32.63#ibcon#[25=AT05-04\r\n] 2006.173.13:11:32.63#ibcon#*before write, iclass 28, count 2 2006.173.13:11:32.63#ibcon#enter sib2, iclass 28, count 2 2006.173.13:11:32.63#ibcon#flushed, iclass 28, count 2 2006.173.13:11:32.63#ibcon#about to write, iclass 28, count 2 2006.173.13:11:32.63#ibcon#wrote, iclass 28, count 2 2006.173.13:11:32.63#ibcon#about to read 3, iclass 28, count 2 2006.173.13:11:32.66#ibcon#read 3, iclass 28, count 2 2006.173.13:11:32.66#ibcon#about to read 4, iclass 28, count 2 2006.173.13:11:32.66#ibcon#read 4, iclass 28, count 2 2006.173.13:11:32.66#ibcon#about to read 5, iclass 28, count 2 2006.173.13:11:32.66#ibcon#read 5, iclass 28, count 2 2006.173.13:11:32.66#ibcon#about to read 6, iclass 28, count 2 2006.173.13:11:32.66#ibcon#read 6, iclass 28, count 2 2006.173.13:11:32.66#ibcon#end of sib2, iclass 28, count 2 2006.173.13:11:32.66#ibcon#*after write, iclass 28, count 2 2006.173.13:11:32.66#ibcon#*before return 0, iclass 28, count 2 2006.173.13:11:32.66#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.13:11:32.66#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.13:11:32.66#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.13:11:32.66#ibcon#ireg 7 cls_cnt 0 2006.173.13:11:32.66#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.13:11:32.78#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.13:11:32.78#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.13:11:32.78#ibcon#enter wrdev, iclass 28, count 0 2006.173.13:11:32.78#ibcon#first serial, iclass 28, count 0 2006.173.13:11:32.78#ibcon#enter sib2, iclass 28, count 0 2006.173.13:11:32.78#ibcon#flushed, iclass 28, count 0 2006.173.13:11:32.78#ibcon#about to write, iclass 28, count 0 2006.173.13:11:32.78#ibcon#wrote, iclass 28, count 0 2006.173.13:11:32.78#ibcon#about to read 3, iclass 28, count 0 2006.173.13:11:32.80#ibcon#read 3, iclass 28, count 0 2006.173.13:11:32.80#ibcon#about to read 4, iclass 28, count 0 2006.173.13:11:32.80#ibcon#read 4, iclass 28, count 0 2006.173.13:11:32.80#ibcon#about to read 5, iclass 28, count 0 2006.173.13:11:32.80#ibcon#read 5, iclass 28, count 0 2006.173.13:11:32.80#ibcon#about to read 6, iclass 28, count 0 2006.173.13:11:32.80#ibcon#read 6, iclass 28, count 0 2006.173.13:11:32.80#ibcon#end of sib2, iclass 28, count 0 2006.173.13:11:32.80#ibcon#*mode == 0, iclass 28, count 0 2006.173.13:11:32.80#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.13:11:32.80#ibcon#[25=USB\r\n] 2006.173.13:11:32.80#ibcon#*before write, iclass 28, count 0 2006.173.13:11:32.80#ibcon#enter sib2, iclass 28, count 0 2006.173.13:11:32.80#ibcon#flushed, iclass 28, count 0 2006.173.13:11:32.80#ibcon#about to write, iclass 28, count 0 2006.173.13:11:32.80#ibcon#wrote, iclass 28, count 0 2006.173.13:11:32.80#ibcon#about to read 3, iclass 28, count 0 2006.173.13:11:32.83#ibcon#read 3, iclass 28, count 0 2006.173.13:11:32.83#ibcon#about to read 4, iclass 28, count 0 2006.173.13:11:32.83#ibcon#read 4, iclass 28, count 0 2006.173.13:11:32.83#ibcon#about to read 5, iclass 28, count 0 2006.173.13:11:32.83#ibcon#read 5, iclass 28, count 0 2006.173.13:11:32.83#ibcon#about to read 6, iclass 28, count 0 2006.173.13:11:32.83#ibcon#read 6, iclass 28, count 0 2006.173.13:11:32.83#ibcon#end of sib2, iclass 28, count 0 2006.173.13:11:32.83#ibcon#*after write, iclass 28, count 0 2006.173.13:11:32.83#ibcon#*before return 0, iclass 28, count 0 2006.173.13:11:32.83#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.13:11:32.83#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.13:11:32.83#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.13:11:32.83#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.13:11:32.83$vck44/valo=6,814.99 2006.173.13:11:32.83#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.13:11:32.83#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.13:11:32.83#ibcon#ireg 17 cls_cnt 0 2006.173.13:11:32.83#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.13:11:32.83#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.13:11:32.83#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.13:11:32.83#ibcon#enter wrdev, iclass 30, count 0 2006.173.13:11:32.83#ibcon#first serial, iclass 30, count 0 2006.173.13:11:32.83#ibcon#enter sib2, iclass 30, count 0 2006.173.13:11:32.83#ibcon#flushed, iclass 30, count 0 2006.173.13:11:32.83#ibcon#about to write, iclass 30, count 0 2006.173.13:11:32.83#ibcon#wrote, iclass 30, count 0 2006.173.13:11:32.83#ibcon#about to read 3, iclass 30, count 0 2006.173.13:11:32.85#ibcon#read 3, iclass 30, count 0 2006.173.13:11:32.85#ibcon#about to read 4, iclass 30, count 0 2006.173.13:11:32.85#ibcon#read 4, iclass 30, count 0 2006.173.13:11:32.85#ibcon#about to read 5, iclass 30, count 0 2006.173.13:11:32.85#ibcon#read 5, iclass 30, count 0 2006.173.13:11:32.85#ibcon#about to read 6, iclass 30, count 0 2006.173.13:11:32.85#ibcon#read 6, iclass 30, count 0 2006.173.13:11:32.85#ibcon#end of sib2, iclass 30, count 0 2006.173.13:11:32.85#ibcon#*mode == 0, iclass 30, count 0 2006.173.13:11:32.85#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.13:11:32.85#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.13:11:32.85#ibcon#*before write, iclass 30, count 0 2006.173.13:11:32.85#ibcon#enter sib2, iclass 30, count 0 2006.173.13:11:32.85#ibcon#flushed, iclass 30, count 0 2006.173.13:11:32.85#ibcon#about to write, iclass 30, count 0 2006.173.13:11:32.85#ibcon#wrote, iclass 30, count 0 2006.173.13:11:32.85#ibcon#about to read 3, iclass 30, count 0 2006.173.13:11:32.89#ibcon#read 3, iclass 30, count 0 2006.173.13:11:32.89#ibcon#about to read 4, iclass 30, count 0 2006.173.13:11:32.89#ibcon#read 4, iclass 30, count 0 2006.173.13:11:32.89#ibcon#about to read 5, iclass 30, count 0 2006.173.13:11:32.89#ibcon#read 5, iclass 30, count 0 2006.173.13:11:32.89#ibcon#about to read 6, iclass 30, count 0 2006.173.13:11:32.89#ibcon#read 6, iclass 30, count 0 2006.173.13:11:32.89#ibcon#end of sib2, iclass 30, count 0 2006.173.13:11:32.89#ibcon#*after write, iclass 30, count 0 2006.173.13:11:32.89#ibcon#*before return 0, iclass 30, count 0 2006.173.13:11:32.89#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.13:11:32.89#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.13:11:32.89#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.13:11:32.89#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.13:11:32.89$vck44/va=6,3 2006.173.13:11:32.89#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.173.13:11:32.89#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.173.13:11:32.89#ibcon#ireg 11 cls_cnt 2 2006.173.13:11:32.89#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.13:11:32.95#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.13:11:32.95#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.13:11:32.95#ibcon#enter wrdev, iclass 32, count 2 2006.173.13:11:32.95#ibcon#first serial, iclass 32, count 2 2006.173.13:11:32.95#ibcon#enter sib2, iclass 32, count 2 2006.173.13:11:32.95#ibcon#flushed, iclass 32, count 2 2006.173.13:11:32.95#ibcon#about to write, iclass 32, count 2 2006.173.13:11:32.95#ibcon#wrote, iclass 32, count 2 2006.173.13:11:32.95#ibcon#about to read 3, iclass 32, count 2 2006.173.13:11:32.97#ibcon#read 3, iclass 32, count 2 2006.173.13:11:32.97#ibcon#about to read 4, iclass 32, count 2 2006.173.13:11:32.97#ibcon#read 4, iclass 32, count 2 2006.173.13:11:32.97#ibcon#about to read 5, iclass 32, count 2 2006.173.13:11:32.97#ibcon#read 5, iclass 32, count 2 2006.173.13:11:32.97#ibcon#about to read 6, iclass 32, count 2 2006.173.13:11:32.97#ibcon#read 6, iclass 32, count 2 2006.173.13:11:32.97#ibcon#end of sib2, iclass 32, count 2 2006.173.13:11:32.97#ibcon#*mode == 0, iclass 32, count 2 2006.173.13:11:32.97#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.173.13:11:32.97#ibcon#[25=AT06-03\r\n] 2006.173.13:11:32.97#ibcon#*before write, iclass 32, count 2 2006.173.13:11:32.97#ibcon#enter sib2, iclass 32, count 2 2006.173.13:11:32.97#ibcon#flushed, iclass 32, count 2 2006.173.13:11:32.97#ibcon#about to write, iclass 32, count 2 2006.173.13:11:32.97#ibcon#wrote, iclass 32, count 2 2006.173.13:11:32.97#ibcon#about to read 3, iclass 32, count 2 2006.173.13:11:33.00#ibcon#read 3, iclass 32, count 2 2006.173.13:11:33.00#ibcon#about to read 4, iclass 32, count 2 2006.173.13:11:33.00#ibcon#read 4, iclass 32, count 2 2006.173.13:11:33.00#ibcon#about to read 5, iclass 32, count 2 2006.173.13:11:33.00#ibcon#read 5, iclass 32, count 2 2006.173.13:11:33.00#ibcon#about to read 6, iclass 32, count 2 2006.173.13:11:33.00#ibcon#read 6, iclass 32, count 2 2006.173.13:11:33.00#ibcon#end of sib2, iclass 32, count 2 2006.173.13:11:33.00#ibcon#*after write, iclass 32, count 2 2006.173.13:11:33.00#ibcon#*before return 0, iclass 32, count 2 2006.173.13:11:33.00#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.13:11:33.00#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.173.13:11:33.00#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.173.13:11:33.00#ibcon#ireg 7 cls_cnt 0 2006.173.13:11:33.00#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.13:11:33.12#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.13:11:33.12#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.13:11:33.12#ibcon#enter wrdev, iclass 32, count 0 2006.173.13:11:33.12#ibcon#first serial, iclass 32, count 0 2006.173.13:11:33.12#ibcon#enter sib2, iclass 32, count 0 2006.173.13:11:33.12#ibcon#flushed, iclass 32, count 0 2006.173.13:11:33.12#ibcon#about to write, iclass 32, count 0 2006.173.13:11:33.12#ibcon#wrote, iclass 32, count 0 2006.173.13:11:33.12#ibcon#about to read 3, iclass 32, count 0 2006.173.13:11:33.14#ibcon#read 3, iclass 32, count 0 2006.173.13:11:33.14#ibcon#about to read 4, iclass 32, count 0 2006.173.13:11:33.14#ibcon#read 4, iclass 32, count 0 2006.173.13:11:33.14#ibcon#about to read 5, iclass 32, count 0 2006.173.13:11:33.14#ibcon#read 5, iclass 32, count 0 2006.173.13:11:33.14#ibcon#about to read 6, iclass 32, count 0 2006.173.13:11:33.14#ibcon#read 6, iclass 32, count 0 2006.173.13:11:33.14#ibcon#end of sib2, iclass 32, count 0 2006.173.13:11:33.14#ibcon#*mode == 0, iclass 32, count 0 2006.173.13:11:33.14#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.13:11:33.14#ibcon#[25=USB\r\n] 2006.173.13:11:33.14#ibcon#*before write, iclass 32, count 0 2006.173.13:11:33.14#ibcon#enter sib2, iclass 32, count 0 2006.173.13:11:33.14#ibcon#flushed, iclass 32, count 0 2006.173.13:11:33.14#ibcon#about to write, iclass 32, count 0 2006.173.13:11:33.14#ibcon#wrote, iclass 32, count 0 2006.173.13:11:33.14#ibcon#about to read 3, iclass 32, count 0 2006.173.13:11:33.17#ibcon#read 3, iclass 32, count 0 2006.173.13:11:33.17#ibcon#about to read 4, iclass 32, count 0 2006.173.13:11:33.17#ibcon#read 4, iclass 32, count 0 2006.173.13:11:33.17#ibcon#about to read 5, iclass 32, count 0 2006.173.13:11:33.17#ibcon#read 5, iclass 32, count 0 2006.173.13:11:33.17#ibcon#about to read 6, iclass 32, count 0 2006.173.13:11:33.17#ibcon#read 6, iclass 32, count 0 2006.173.13:11:33.17#ibcon#end of sib2, iclass 32, count 0 2006.173.13:11:33.17#ibcon#*after write, iclass 32, count 0 2006.173.13:11:33.17#ibcon#*before return 0, iclass 32, count 0 2006.173.13:11:33.17#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.13:11:33.17#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.173.13:11:33.17#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.13:11:33.17#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.13:11:33.17$vck44/valo=7,864.99 2006.173.13:11:33.17#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.13:11:33.17#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.13:11:33.17#ibcon#ireg 17 cls_cnt 0 2006.173.13:11:33.17#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.13:11:33.17#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.13:11:33.17#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.13:11:33.17#ibcon#enter wrdev, iclass 34, count 0 2006.173.13:11:33.17#ibcon#first serial, iclass 34, count 0 2006.173.13:11:33.17#ibcon#enter sib2, iclass 34, count 0 2006.173.13:11:33.17#ibcon#flushed, iclass 34, count 0 2006.173.13:11:33.17#ibcon#about to write, iclass 34, count 0 2006.173.13:11:33.17#ibcon#wrote, iclass 34, count 0 2006.173.13:11:33.17#ibcon#about to read 3, iclass 34, count 0 2006.173.13:11:33.19#ibcon#read 3, iclass 34, count 0 2006.173.13:11:33.19#ibcon#about to read 4, iclass 34, count 0 2006.173.13:11:33.19#ibcon#read 4, iclass 34, count 0 2006.173.13:11:33.19#ibcon#about to read 5, iclass 34, count 0 2006.173.13:11:33.19#ibcon#read 5, iclass 34, count 0 2006.173.13:11:33.19#ibcon#about to read 6, iclass 34, count 0 2006.173.13:11:33.19#ibcon#read 6, iclass 34, count 0 2006.173.13:11:33.19#ibcon#end of sib2, iclass 34, count 0 2006.173.13:11:33.19#ibcon#*mode == 0, iclass 34, count 0 2006.173.13:11:33.19#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.13:11:33.19#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.13:11:33.19#ibcon#*before write, iclass 34, count 0 2006.173.13:11:33.19#ibcon#enter sib2, iclass 34, count 0 2006.173.13:11:33.19#ibcon#flushed, iclass 34, count 0 2006.173.13:11:33.19#ibcon#about to write, iclass 34, count 0 2006.173.13:11:33.19#ibcon#wrote, iclass 34, count 0 2006.173.13:11:33.19#ibcon#about to read 3, iclass 34, count 0 2006.173.13:11:33.23#ibcon#read 3, iclass 34, count 0 2006.173.13:11:33.23#ibcon#about to read 4, iclass 34, count 0 2006.173.13:11:33.23#ibcon#read 4, iclass 34, count 0 2006.173.13:11:33.23#ibcon#about to read 5, iclass 34, count 0 2006.173.13:11:33.23#ibcon#read 5, iclass 34, count 0 2006.173.13:11:33.23#ibcon#about to read 6, iclass 34, count 0 2006.173.13:11:33.23#ibcon#read 6, iclass 34, count 0 2006.173.13:11:33.23#ibcon#end of sib2, iclass 34, count 0 2006.173.13:11:33.23#ibcon#*after write, iclass 34, count 0 2006.173.13:11:33.23#ibcon#*before return 0, iclass 34, count 0 2006.173.13:11:33.23#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.13:11:33.23#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.13:11:33.23#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.13:11:33.23#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.13:11:33.23$vck44/va=7,4 2006.173.13:11:33.23#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.13:11:33.23#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.13:11:33.23#ibcon#ireg 11 cls_cnt 2 2006.173.13:11:33.23#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.13:11:33.29#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.13:11:33.29#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.13:11:33.29#ibcon#enter wrdev, iclass 36, count 2 2006.173.13:11:33.29#ibcon#first serial, iclass 36, count 2 2006.173.13:11:33.29#ibcon#enter sib2, iclass 36, count 2 2006.173.13:11:33.29#ibcon#flushed, iclass 36, count 2 2006.173.13:11:33.29#ibcon#about to write, iclass 36, count 2 2006.173.13:11:33.29#ibcon#wrote, iclass 36, count 2 2006.173.13:11:33.29#ibcon#about to read 3, iclass 36, count 2 2006.173.13:11:33.31#ibcon#read 3, iclass 36, count 2 2006.173.13:11:33.31#ibcon#about to read 4, iclass 36, count 2 2006.173.13:11:33.31#ibcon#read 4, iclass 36, count 2 2006.173.13:11:33.31#ibcon#about to read 5, iclass 36, count 2 2006.173.13:11:33.31#ibcon#read 5, iclass 36, count 2 2006.173.13:11:33.31#ibcon#about to read 6, iclass 36, count 2 2006.173.13:11:33.31#ibcon#read 6, iclass 36, count 2 2006.173.13:11:33.31#ibcon#end of sib2, iclass 36, count 2 2006.173.13:11:33.31#ibcon#*mode == 0, iclass 36, count 2 2006.173.13:11:33.31#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.13:11:33.31#ibcon#[25=AT07-04\r\n] 2006.173.13:11:33.31#ibcon#*before write, iclass 36, count 2 2006.173.13:11:33.31#ibcon#enter sib2, iclass 36, count 2 2006.173.13:11:33.31#ibcon#flushed, iclass 36, count 2 2006.173.13:11:33.31#ibcon#about to write, iclass 36, count 2 2006.173.13:11:33.31#ibcon#wrote, iclass 36, count 2 2006.173.13:11:33.31#ibcon#about to read 3, iclass 36, count 2 2006.173.13:11:33.34#ibcon#read 3, iclass 36, count 2 2006.173.13:11:33.34#ibcon#about to read 4, iclass 36, count 2 2006.173.13:11:33.34#ibcon#read 4, iclass 36, count 2 2006.173.13:11:33.34#ibcon#about to read 5, iclass 36, count 2 2006.173.13:11:33.34#ibcon#read 5, iclass 36, count 2 2006.173.13:11:33.34#ibcon#about to read 6, iclass 36, count 2 2006.173.13:11:33.34#ibcon#read 6, iclass 36, count 2 2006.173.13:11:33.34#ibcon#end of sib2, iclass 36, count 2 2006.173.13:11:33.34#ibcon#*after write, iclass 36, count 2 2006.173.13:11:33.34#ibcon#*before return 0, iclass 36, count 2 2006.173.13:11:33.34#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.13:11:33.34#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.13:11:33.34#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.13:11:33.34#ibcon#ireg 7 cls_cnt 0 2006.173.13:11:33.34#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.13:11:33.46#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.13:11:33.46#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.13:11:33.46#ibcon#enter wrdev, iclass 36, count 0 2006.173.13:11:33.46#ibcon#first serial, iclass 36, count 0 2006.173.13:11:33.46#ibcon#enter sib2, iclass 36, count 0 2006.173.13:11:33.46#ibcon#flushed, iclass 36, count 0 2006.173.13:11:33.46#ibcon#about to write, iclass 36, count 0 2006.173.13:11:33.46#ibcon#wrote, iclass 36, count 0 2006.173.13:11:33.46#ibcon#about to read 3, iclass 36, count 0 2006.173.13:11:33.48#ibcon#read 3, iclass 36, count 0 2006.173.13:11:33.48#ibcon#about to read 4, iclass 36, count 0 2006.173.13:11:33.48#ibcon#read 4, iclass 36, count 0 2006.173.13:11:33.48#ibcon#about to read 5, iclass 36, count 0 2006.173.13:11:33.48#ibcon#read 5, iclass 36, count 0 2006.173.13:11:33.48#ibcon#about to read 6, iclass 36, count 0 2006.173.13:11:33.48#ibcon#read 6, iclass 36, count 0 2006.173.13:11:33.48#ibcon#end of sib2, iclass 36, count 0 2006.173.13:11:33.48#ibcon#*mode == 0, iclass 36, count 0 2006.173.13:11:33.48#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.13:11:33.48#ibcon#[25=USB\r\n] 2006.173.13:11:33.48#ibcon#*before write, iclass 36, count 0 2006.173.13:11:33.48#ibcon#enter sib2, iclass 36, count 0 2006.173.13:11:33.48#ibcon#flushed, iclass 36, count 0 2006.173.13:11:33.48#ibcon#about to write, iclass 36, count 0 2006.173.13:11:33.48#ibcon#wrote, iclass 36, count 0 2006.173.13:11:33.48#ibcon#about to read 3, iclass 36, count 0 2006.173.13:11:33.51#ibcon#read 3, iclass 36, count 0 2006.173.13:11:33.51#ibcon#about to read 4, iclass 36, count 0 2006.173.13:11:33.51#ibcon#read 4, iclass 36, count 0 2006.173.13:11:33.51#ibcon#about to read 5, iclass 36, count 0 2006.173.13:11:33.51#ibcon#read 5, iclass 36, count 0 2006.173.13:11:33.51#ibcon#about to read 6, iclass 36, count 0 2006.173.13:11:33.51#ibcon#read 6, iclass 36, count 0 2006.173.13:11:33.51#ibcon#end of sib2, iclass 36, count 0 2006.173.13:11:33.51#ibcon#*after write, iclass 36, count 0 2006.173.13:11:33.51#ibcon#*before return 0, iclass 36, count 0 2006.173.13:11:33.51#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.13:11:33.51#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.13:11:33.51#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.13:11:33.51#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.13:11:33.51$vck44/valo=8,884.99 2006.173.13:11:33.51#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.13:11:33.51#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.13:11:33.51#ibcon#ireg 17 cls_cnt 0 2006.173.13:11:33.51#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.13:11:33.51#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.13:11:33.51#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.13:11:33.51#ibcon#enter wrdev, iclass 38, count 0 2006.173.13:11:33.51#ibcon#first serial, iclass 38, count 0 2006.173.13:11:33.51#ibcon#enter sib2, iclass 38, count 0 2006.173.13:11:33.51#ibcon#flushed, iclass 38, count 0 2006.173.13:11:33.51#ibcon#about to write, iclass 38, count 0 2006.173.13:11:33.51#ibcon#wrote, iclass 38, count 0 2006.173.13:11:33.51#ibcon#about to read 3, iclass 38, count 0 2006.173.13:11:33.53#ibcon#read 3, iclass 38, count 0 2006.173.13:11:33.53#ibcon#about to read 4, iclass 38, count 0 2006.173.13:11:33.53#ibcon#read 4, iclass 38, count 0 2006.173.13:11:33.53#ibcon#about to read 5, iclass 38, count 0 2006.173.13:11:33.53#ibcon#read 5, iclass 38, count 0 2006.173.13:11:33.53#ibcon#about to read 6, iclass 38, count 0 2006.173.13:11:33.53#ibcon#read 6, iclass 38, count 0 2006.173.13:11:33.53#ibcon#end of sib2, iclass 38, count 0 2006.173.13:11:33.53#ibcon#*mode == 0, iclass 38, count 0 2006.173.13:11:33.53#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.13:11:33.53#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.13:11:33.53#ibcon#*before write, iclass 38, count 0 2006.173.13:11:33.53#ibcon#enter sib2, iclass 38, count 0 2006.173.13:11:33.53#ibcon#flushed, iclass 38, count 0 2006.173.13:11:33.53#ibcon#about to write, iclass 38, count 0 2006.173.13:11:33.53#ibcon#wrote, iclass 38, count 0 2006.173.13:11:33.53#ibcon#about to read 3, iclass 38, count 0 2006.173.13:11:33.57#ibcon#read 3, iclass 38, count 0 2006.173.13:11:33.57#ibcon#about to read 4, iclass 38, count 0 2006.173.13:11:33.57#ibcon#read 4, iclass 38, count 0 2006.173.13:11:33.57#ibcon#about to read 5, iclass 38, count 0 2006.173.13:11:33.57#ibcon#read 5, iclass 38, count 0 2006.173.13:11:33.57#ibcon#about to read 6, iclass 38, count 0 2006.173.13:11:33.57#ibcon#read 6, iclass 38, count 0 2006.173.13:11:33.57#ibcon#end of sib2, iclass 38, count 0 2006.173.13:11:33.57#ibcon#*after write, iclass 38, count 0 2006.173.13:11:33.57#ibcon#*before return 0, iclass 38, count 0 2006.173.13:11:33.57#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.13:11:33.57#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.13:11:33.57#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.13:11:33.57#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.13:11:33.57$vck44/va=8,4 2006.173.13:11:33.57#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.13:11:33.57#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.13:11:33.57#ibcon#ireg 11 cls_cnt 2 2006.173.13:11:33.57#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.13:11:33.63#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.13:11:33.63#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.13:11:33.63#ibcon#enter wrdev, iclass 40, count 2 2006.173.13:11:33.63#ibcon#first serial, iclass 40, count 2 2006.173.13:11:33.63#ibcon#enter sib2, iclass 40, count 2 2006.173.13:11:33.63#ibcon#flushed, iclass 40, count 2 2006.173.13:11:33.63#ibcon#about to write, iclass 40, count 2 2006.173.13:11:33.63#ibcon#wrote, iclass 40, count 2 2006.173.13:11:33.63#ibcon#about to read 3, iclass 40, count 2 2006.173.13:11:33.65#ibcon#read 3, iclass 40, count 2 2006.173.13:11:33.65#ibcon#about to read 4, iclass 40, count 2 2006.173.13:11:33.65#ibcon#read 4, iclass 40, count 2 2006.173.13:11:33.65#ibcon#about to read 5, iclass 40, count 2 2006.173.13:11:33.65#ibcon#read 5, iclass 40, count 2 2006.173.13:11:33.65#ibcon#about to read 6, iclass 40, count 2 2006.173.13:11:33.65#ibcon#read 6, iclass 40, count 2 2006.173.13:11:33.65#ibcon#end of sib2, iclass 40, count 2 2006.173.13:11:33.65#ibcon#*mode == 0, iclass 40, count 2 2006.173.13:11:33.65#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.13:11:33.65#ibcon#[25=AT08-04\r\n] 2006.173.13:11:33.65#ibcon#*before write, iclass 40, count 2 2006.173.13:11:33.65#ibcon#enter sib2, iclass 40, count 2 2006.173.13:11:33.65#ibcon#flushed, iclass 40, count 2 2006.173.13:11:33.65#ibcon#about to write, iclass 40, count 2 2006.173.13:11:33.65#ibcon#wrote, iclass 40, count 2 2006.173.13:11:33.65#ibcon#about to read 3, iclass 40, count 2 2006.173.13:11:33.68#ibcon#read 3, iclass 40, count 2 2006.173.13:11:33.68#ibcon#about to read 4, iclass 40, count 2 2006.173.13:11:33.68#ibcon#read 4, iclass 40, count 2 2006.173.13:11:33.68#ibcon#about to read 5, iclass 40, count 2 2006.173.13:11:33.68#ibcon#read 5, iclass 40, count 2 2006.173.13:11:33.68#ibcon#about to read 6, iclass 40, count 2 2006.173.13:11:33.68#ibcon#read 6, iclass 40, count 2 2006.173.13:11:33.68#ibcon#end of sib2, iclass 40, count 2 2006.173.13:11:33.68#ibcon#*after write, iclass 40, count 2 2006.173.13:11:33.68#ibcon#*before return 0, iclass 40, count 2 2006.173.13:11:33.68#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.13:11:33.68#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.13:11:33.68#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.13:11:33.68#ibcon#ireg 7 cls_cnt 0 2006.173.13:11:33.68#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.13:11:33.80#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.13:11:33.80#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.13:11:33.80#ibcon#enter wrdev, iclass 40, count 0 2006.173.13:11:33.80#ibcon#first serial, iclass 40, count 0 2006.173.13:11:33.80#ibcon#enter sib2, iclass 40, count 0 2006.173.13:11:33.80#ibcon#flushed, iclass 40, count 0 2006.173.13:11:33.80#ibcon#about to write, iclass 40, count 0 2006.173.13:11:33.80#ibcon#wrote, iclass 40, count 0 2006.173.13:11:33.80#ibcon#about to read 3, iclass 40, count 0 2006.173.13:11:33.82#ibcon#read 3, iclass 40, count 0 2006.173.13:11:33.82#ibcon#about to read 4, iclass 40, count 0 2006.173.13:11:33.82#ibcon#read 4, iclass 40, count 0 2006.173.13:11:33.82#ibcon#about to read 5, iclass 40, count 0 2006.173.13:11:33.82#ibcon#read 5, iclass 40, count 0 2006.173.13:11:33.82#ibcon#about to read 6, iclass 40, count 0 2006.173.13:11:33.82#ibcon#read 6, iclass 40, count 0 2006.173.13:11:33.82#ibcon#end of sib2, iclass 40, count 0 2006.173.13:11:33.82#ibcon#*mode == 0, iclass 40, count 0 2006.173.13:11:33.82#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.13:11:33.82#ibcon#[25=USB\r\n] 2006.173.13:11:33.82#ibcon#*before write, iclass 40, count 0 2006.173.13:11:33.82#ibcon#enter sib2, iclass 40, count 0 2006.173.13:11:33.82#ibcon#flushed, iclass 40, count 0 2006.173.13:11:33.82#ibcon#about to write, iclass 40, count 0 2006.173.13:11:33.82#ibcon#wrote, iclass 40, count 0 2006.173.13:11:33.82#ibcon#about to read 3, iclass 40, count 0 2006.173.13:11:33.85#ibcon#read 3, iclass 40, count 0 2006.173.13:11:33.85#ibcon#about to read 4, iclass 40, count 0 2006.173.13:11:33.85#ibcon#read 4, iclass 40, count 0 2006.173.13:11:33.85#ibcon#about to read 5, iclass 40, count 0 2006.173.13:11:33.85#ibcon#read 5, iclass 40, count 0 2006.173.13:11:33.85#ibcon#about to read 6, iclass 40, count 0 2006.173.13:11:33.85#ibcon#read 6, iclass 40, count 0 2006.173.13:11:33.85#ibcon#end of sib2, iclass 40, count 0 2006.173.13:11:33.85#ibcon#*after write, iclass 40, count 0 2006.173.13:11:33.85#ibcon#*before return 0, iclass 40, count 0 2006.173.13:11:33.85#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.13:11:33.85#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.13:11:33.85#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.13:11:33.85#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.13:11:33.85$vck44/vblo=1,629.99 2006.173.13:11:33.85#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.13:11:33.85#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.13:11:33.85#ibcon#ireg 17 cls_cnt 0 2006.173.13:11:33.85#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.13:11:33.85#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.13:11:33.85#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.13:11:33.85#ibcon#enter wrdev, iclass 4, count 0 2006.173.13:11:33.85#ibcon#first serial, iclass 4, count 0 2006.173.13:11:33.85#ibcon#enter sib2, iclass 4, count 0 2006.173.13:11:33.85#ibcon#flushed, iclass 4, count 0 2006.173.13:11:33.85#ibcon#about to write, iclass 4, count 0 2006.173.13:11:33.85#ibcon#wrote, iclass 4, count 0 2006.173.13:11:33.85#ibcon#about to read 3, iclass 4, count 0 2006.173.13:11:33.87#ibcon#read 3, iclass 4, count 0 2006.173.13:11:33.87#ibcon#about to read 4, iclass 4, count 0 2006.173.13:11:33.87#ibcon#read 4, iclass 4, count 0 2006.173.13:11:33.87#ibcon#about to read 5, iclass 4, count 0 2006.173.13:11:33.87#ibcon#read 5, iclass 4, count 0 2006.173.13:11:33.87#ibcon#about to read 6, iclass 4, count 0 2006.173.13:11:33.87#ibcon#read 6, iclass 4, count 0 2006.173.13:11:33.87#ibcon#end of sib2, iclass 4, count 0 2006.173.13:11:33.87#ibcon#*mode == 0, iclass 4, count 0 2006.173.13:11:33.87#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.13:11:33.87#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.13:11:33.87#ibcon#*before write, iclass 4, count 0 2006.173.13:11:33.87#ibcon#enter sib2, iclass 4, count 0 2006.173.13:11:33.87#ibcon#flushed, iclass 4, count 0 2006.173.13:11:33.87#ibcon#about to write, iclass 4, count 0 2006.173.13:11:33.87#ibcon#wrote, iclass 4, count 0 2006.173.13:11:33.87#ibcon#about to read 3, iclass 4, count 0 2006.173.13:11:33.91#ibcon#read 3, iclass 4, count 0 2006.173.13:11:33.91#ibcon#about to read 4, iclass 4, count 0 2006.173.13:11:33.91#ibcon#read 4, iclass 4, count 0 2006.173.13:11:33.91#ibcon#about to read 5, iclass 4, count 0 2006.173.13:11:33.91#ibcon#read 5, iclass 4, count 0 2006.173.13:11:33.91#ibcon#about to read 6, iclass 4, count 0 2006.173.13:11:33.91#ibcon#read 6, iclass 4, count 0 2006.173.13:11:33.91#ibcon#end of sib2, iclass 4, count 0 2006.173.13:11:33.91#ibcon#*after write, iclass 4, count 0 2006.173.13:11:33.91#ibcon#*before return 0, iclass 4, count 0 2006.173.13:11:33.91#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.13:11:33.91#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.13:11:33.91#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.13:11:33.91#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.13:11:33.91$vck44/vb=1,4 2006.173.13:11:33.91#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.13:11:33.91#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.13:11:33.91#ibcon#ireg 11 cls_cnt 2 2006.173.13:11:33.91#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.13:11:33.91#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.13:11:33.91#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.13:11:33.91#ibcon#enter wrdev, iclass 6, count 2 2006.173.13:11:33.91#ibcon#first serial, iclass 6, count 2 2006.173.13:11:33.91#ibcon#enter sib2, iclass 6, count 2 2006.173.13:11:33.91#ibcon#flushed, iclass 6, count 2 2006.173.13:11:33.91#ibcon#about to write, iclass 6, count 2 2006.173.13:11:33.91#ibcon#wrote, iclass 6, count 2 2006.173.13:11:33.91#ibcon#about to read 3, iclass 6, count 2 2006.173.13:11:33.93#ibcon#read 3, iclass 6, count 2 2006.173.13:11:33.93#ibcon#about to read 4, iclass 6, count 2 2006.173.13:11:33.93#ibcon#read 4, iclass 6, count 2 2006.173.13:11:33.93#ibcon#about to read 5, iclass 6, count 2 2006.173.13:11:33.93#ibcon#read 5, iclass 6, count 2 2006.173.13:11:33.93#ibcon#about to read 6, iclass 6, count 2 2006.173.13:11:33.93#ibcon#read 6, iclass 6, count 2 2006.173.13:11:33.93#ibcon#end of sib2, iclass 6, count 2 2006.173.13:11:33.93#ibcon#*mode == 0, iclass 6, count 2 2006.173.13:11:33.93#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.13:11:33.93#ibcon#[27=AT01-04\r\n] 2006.173.13:11:33.93#ibcon#*before write, iclass 6, count 2 2006.173.13:11:33.93#ibcon#enter sib2, iclass 6, count 2 2006.173.13:11:33.93#ibcon#flushed, iclass 6, count 2 2006.173.13:11:33.93#ibcon#about to write, iclass 6, count 2 2006.173.13:11:33.93#ibcon#wrote, iclass 6, count 2 2006.173.13:11:33.93#ibcon#about to read 3, iclass 6, count 2 2006.173.13:11:33.96#ibcon#read 3, iclass 6, count 2 2006.173.13:11:33.96#ibcon#about to read 4, iclass 6, count 2 2006.173.13:11:33.96#ibcon#read 4, iclass 6, count 2 2006.173.13:11:33.96#ibcon#about to read 5, iclass 6, count 2 2006.173.13:11:33.96#ibcon#read 5, iclass 6, count 2 2006.173.13:11:33.96#ibcon#about to read 6, iclass 6, count 2 2006.173.13:11:33.96#ibcon#read 6, iclass 6, count 2 2006.173.13:11:33.96#ibcon#end of sib2, iclass 6, count 2 2006.173.13:11:33.96#ibcon#*after write, iclass 6, count 2 2006.173.13:11:33.96#ibcon#*before return 0, iclass 6, count 2 2006.173.13:11:33.96#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.13:11:33.96#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.13:11:33.96#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.13:11:33.96#ibcon#ireg 7 cls_cnt 0 2006.173.13:11:33.96#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.13:11:34.08#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.13:11:34.08#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.13:11:34.08#ibcon#enter wrdev, iclass 6, count 0 2006.173.13:11:34.08#ibcon#first serial, iclass 6, count 0 2006.173.13:11:34.08#ibcon#enter sib2, iclass 6, count 0 2006.173.13:11:34.08#ibcon#flushed, iclass 6, count 0 2006.173.13:11:34.08#ibcon#about to write, iclass 6, count 0 2006.173.13:11:34.08#ibcon#wrote, iclass 6, count 0 2006.173.13:11:34.08#ibcon#about to read 3, iclass 6, count 0 2006.173.13:11:34.10#ibcon#read 3, iclass 6, count 0 2006.173.13:11:34.10#ibcon#about to read 4, iclass 6, count 0 2006.173.13:11:34.10#ibcon#read 4, iclass 6, count 0 2006.173.13:11:34.10#ibcon#about to read 5, iclass 6, count 0 2006.173.13:11:34.10#ibcon#read 5, iclass 6, count 0 2006.173.13:11:34.10#ibcon#about to read 6, iclass 6, count 0 2006.173.13:11:34.10#ibcon#read 6, iclass 6, count 0 2006.173.13:11:34.10#ibcon#end of sib2, iclass 6, count 0 2006.173.13:11:34.10#ibcon#*mode == 0, iclass 6, count 0 2006.173.13:11:34.10#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.13:11:34.10#ibcon#[27=USB\r\n] 2006.173.13:11:34.10#ibcon#*before write, iclass 6, count 0 2006.173.13:11:34.10#ibcon#enter sib2, iclass 6, count 0 2006.173.13:11:34.10#ibcon#flushed, iclass 6, count 0 2006.173.13:11:34.10#ibcon#about to write, iclass 6, count 0 2006.173.13:11:34.10#ibcon#wrote, iclass 6, count 0 2006.173.13:11:34.10#ibcon#about to read 3, iclass 6, count 0 2006.173.13:11:34.13#ibcon#read 3, iclass 6, count 0 2006.173.13:11:34.13#ibcon#about to read 4, iclass 6, count 0 2006.173.13:11:34.13#ibcon#read 4, iclass 6, count 0 2006.173.13:11:34.13#ibcon#about to read 5, iclass 6, count 0 2006.173.13:11:34.13#ibcon#read 5, iclass 6, count 0 2006.173.13:11:34.13#ibcon#about to read 6, iclass 6, count 0 2006.173.13:11:34.13#ibcon#read 6, iclass 6, count 0 2006.173.13:11:34.13#ibcon#end of sib2, iclass 6, count 0 2006.173.13:11:34.13#ibcon#*after write, iclass 6, count 0 2006.173.13:11:34.13#ibcon#*before return 0, iclass 6, count 0 2006.173.13:11:34.13#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.13:11:34.13#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.13:11:34.13#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.13:11:34.13#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.13:11:34.13$vck44/vblo=2,634.99 2006.173.13:11:34.13#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.13:11:34.13#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.13:11:34.13#ibcon#ireg 17 cls_cnt 0 2006.173.13:11:34.13#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.13:11:34.13#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.13:11:34.13#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.13:11:34.13#ibcon#enter wrdev, iclass 10, count 0 2006.173.13:11:34.13#ibcon#first serial, iclass 10, count 0 2006.173.13:11:34.13#ibcon#enter sib2, iclass 10, count 0 2006.173.13:11:34.13#ibcon#flushed, iclass 10, count 0 2006.173.13:11:34.13#ibcon#about to write, iclass 10, count 0 2006.173.13:11:34.13#ibcon#wrote, iclass 10, count 0 2006.173.13:11:34.13#ibcon#about to read 3, iclass 10, count 0 2006.173.13:11:34.15#ibcon#read 3, iclass 10, count 0 2006.173.13:11:34.15#ibcon#about to read 4, iclass 10, count 0 2006.173.13:11:34.15#ibcon#read 4, iclass 10, count 0 2006.173.13:11:34.15#ibcon#about to read 5, iclass 10, count 0 2006.173.13:11:34.15#ibcon#read 5, iclass 10, count 0 2006.173.13:11:34.15#ibcon#about to read 6, iclass 10, count 0 2006.173.13:11:34.15#ibcon#read 6, iclass 10, count 0 2006.173.13:11:34.15#ibcon#end of sib2, iclass 10, count 0 2006.173.13:11:34.15#ibcon#*mode == 0, iclass 10, count 0 2006.173.13:11:34.15#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.13:11:34.15#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.13:11:34.15#ibcon#*before write, iclass 10, count 0 2006.173.13:11:34.15#ibcon#enter sib2, iclass 10, count 0 2006.173.13:11:34.15#ibcon#flushed, iclass 10, count 0 2006.173.13:11:34.15#ibcon#about to write, iclass 10, count 0 2006.173.13:11:34.15#ibcon#wrote, iclass 10, count 0 2006.173.13:11:34.15#ibcon#about to read 3, iclass 10, count 0 2006.173.13:11:34.19#ibcon#read 3, iclass 10, count 0 2006.173.13:11:34.19#ibcon#about to read 4, iclass 10, count 0 2006.173.13:11:34.19#ibcon#read 4, iclass 10, count 0 2006.173.13:11:34.19#ibcon#about to read 5, iclass 10, count 0 2006.173.13:11:34.19#ibcon#read 5, iclass 10, count 0 2006.173.13:11:34.19#ibcon#about to read 6, iclass 10, count 0 2006.173.13:11:34.19#ibcon#read 6, iclass 10, count 0 2006.173.13:11:34.19#ibcon#end of sib2, iclass 10, count 0 2006.173.13:11:34.19#ibcon#*after write, iclass 10, count 0 2006.173.13:11:34.19#ibcon#*before return 0, iclass 10, count 0 2006.173.13:11:34.19#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.13:11:34.19#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.13:11:34.19#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.13:11:34.19#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.13:11:34.19$vck44/vb=2,4 2006.173.13:11:34.19#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.13:11:34.19#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.13:11:34.19#ibcon#ireg 11 cls_cnt 2 2006.173.13:11:34.19#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.13:11:34.25#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.13:11:34.25#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.13:11:34.25#ibcon#enter wrdev, iclass 12, count 2 2006.173.13:11:34.25#ibcon#first serial, iclass 12, count 2 2006.173.13:11:34.25#ibcon#enter sib2, iclass 12, count 2 2006.173.13:11:34.25#ibcon#flushed, iclass 12, count 2 2006.173.13:11:34.25#ibcon#about to write, iclass 12, count 2 2006.173.13:11:34.25#ibcon#wrote, iclass 12, count 2 2006.173.13:11:34.25#ibcon#about to read 3, iclass 12, count 2 2006.173.13:11:34.27#ibcon#read 3, iclass 12, count 2 2006.173.13:11:34.27#ibcon#about to read 4, iclass 12, count 2 2006.173.13:11:34.27#ibcon#read 4, iclass 12, count 2 2006.173.13:11:34.27#ibcon#about to read 5, iclass 12, count 2 2006.173.13:11:34.27#ibcon#read 5, iclass 12, count 2 2006.173.13:11:34.27#ibcon#about to read 6, iclass 12, count 2 2006.173.13:11:34.27#ibcon#read 6, iclass 12, count 2 2006.173.13:11:34.27#ibcon#end of sib2, iclass 12, count 2 2006.173.13:11:34.27#ibcon#*mode == 0, iclass 12, count 2 2006.173.13:11:34.27#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.13:11:34.27#ibcon#[27=AT02-04\r\n] 2006.173.13:11:34.27#ibcon#*before write, iclass 12, count 2 2006.173.13:11:34.27#ibcon#enter sib2, iclass 12, count 2 2006.173.13:11:34.27#ibcon#flushed, iclass 12, count 2 2006.173.13:11:34.27#ibcon#about to write, iclass 12, count 2 2006.173.13:11:34.27#ibcon#wrote, iclass 12, count 2 2006.173.13:11:34.27#ibcon#about to read 3, iclass 12, count 2 2006.173.13:11:34.30#ibcon#read 3, iclass 12, count 2 2006.173.13:11:34.30#ibcon#about to read 4, iclass 12, count 2 2006.173.13:11:34.30#ibcon#read 4, iclass 12, count 2 2006.173.13:11:34.30#ibcon#about to read 5, iclass 12, count 2 2006.173.13:11:34.30#ibcon#read 5, iclass 12, count 2 2006.173.13:11:34.30#ibcon#about to read 6, iclass 12, count 2 2006.173.13:11:34.30#ibcon#read 6, iclass 12, count 2 2006.173.13:11:34.30#ibcon#end of sib2, iclass 12, count 2 2006.173.13:11:34.30#ibcon#*after write, iclass 12, count 2 2006.173.13:11:34.30#ibcon#*before return 0, iclass 12, count 2 2006.173.13:11:34.30#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.13:11:34.30#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.13:11:34.30#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.13:11:34.30#ibcon#ireg 7 cls_cnt 0 2006.173.13:11:34.30#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.13:11:34.42#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.13:11:34.42#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.13:11:34.42#ibcon#enter wrdev, iclass 12, count 0 2006.173.13:11:34.42#ibcon#first serial, iclass 12, count 0 2006.173.13:11:34.42#ibcon#enter sib2, iclass 12, count 0 2006.173.13:11:34.42#ibcon#flushed, iclass 12, count 0 2006.173.13:11:34.42#ibcon#about to write, iclass 12, count 0 2006.173.13:11:34.42#ibcon#wrote, iclass 12, count 0 2006.173.13:11:34.42#ibcon#about to read 3, iclass 12, count 0 2006.173.13:11:34.44#ibcon#read 3, iclass 12, count 0 2006.173.13:11:34.44#ibcon#about to read 4, iclass 12, count 0 2006.173.13:11:34.44#ibcon#read 4, iclass 12, count 0 2006.173.13:11:34.44#ibcon#about to read 5, iclass 12, count 0 2006.173.13:11:34.44#ibcon#read 5, iclass 12, count 0 2006.173.13:11:34.44#ibcon#about to read 6, iclass 12, count 0 2006.173.13:11:34.44#ibcon#read 6, iclass 12, count 0 2006.173.13:11:34.44#ibcon#end of sib2, iclass 12, count 0 2006.173.13:11:34.44#ibcon#*mode == 0, iclass 12, count 0 2006.173.13:11:34.44#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.13:11:34.44#ibcon#[27=USB\r\n] 2006.173.13:11:34.44#ibcon#*before write, iclass 12, count 0 2006.173.13:11:34.44#ibcon#enter sib2, iclass 12, count 0 2006.173.13:11:34.44#ibcon#flushed, iclass 12, count 0 2006.173.13:11:34.44#ibcon#about to write, iclass 12, count 0 2006.173.13:11:34.44#ibcon#wrote, iclass 12, count 0 2006.173.13:11:34.44#ibcon#about to read 3, iclass 12, count 0 2006.173.13:11:34.47#ibcon#read 3, iclass 12, count 0 2006.173.13:11:34.47#ibcon#about to read 4, iclass 12, count 0 2006.173.13:11:34.47#ibcon#read 4, iclass 12, count 0 2006.173.13:11:34.47#ibcon#about to read 5, iclass 12, count 0 2006.173.13:11:34.47#ibcon#read 5, iclass 12, count 0 2006.173.13:11:34.47#ibcon#about to read 6, iclass 12, count 0 2006.173.13:11:34.47#ibcon#read 6, iclass 12, count 0 2006.173.13:11:34.47#ibcon#end of sib2, iclass 12, count 0 2006.173.13:11:34.47#ibcon#*after write, iclass 12, count 0 2006.173.13:11:34.47#ibcon#*before return 0, iclass 12, count 0 2006.173.13:11:34.47#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.13:11:34.47#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.13:11:34.47#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.13:11:34.47#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.13:11:34.47$vck44/vblo=3,649.99 2006.173.13:11:34.47#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.13:11:34.47#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.13:11:34.47#ibcon#ireg 17 cls_cnt 0 2006.173.13:11:34.47#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.13:11:34.47#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.13:11:34.47#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.13:11:34.47#ibcon#enter wrdev, iclass 14, count 0 2006.173.13:11:34.47#ibcon#first serial, iclass 14, count 0 2006.173.13:11:34.47#ibcon#enter sib2, iclass 14, count 0 2006.173.13:11:34.47#ibcon#flushed, iclass 14, count 0 2006.173.13:11:34.47#ibcon#about to write, iclass 14, count 0 2006.173.13:11:34.47#ibcon#wrote, iclass 14, count 0 2006.173.13:11:34.47#ibcon#about to read 3, iclass 14, count 0 2006.173.13:11:34.49#ibcon#read 3, iclass 14, count 0 2006.173.13:11:34.49#ibcon#about to read 4, iclass 14, count 0 2006.173.13:11:34.49#ibcon#read 4, iclass 14, count 0 2006.173.13:11:34.49#ibcon#about to read 5, iclass 14, count 0 2006.173.13:11:34.49#ibcon#read 5, iclass 14, count 0 2006.173.13:11:34.49#ibcon#about to read 6, iclass 14, count 0 2006.173.13:11:34.49#ibcon#read 6, iclass 14, count 0 2006.173.13:11:34.49#ibcon#end of sib2, iclass 14, count 0 2006.173.13:11:34.49#ibcon#*mode == 0, iclass 14, count 0 2006.173.13:11:34.49#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.13:11:34.49#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.13:11:34.49#ibcon#*before write, iclass 14, count 0 2006.173.13:11:34.49#ibcon#enter sib2, iclass 14, count 0 2006.173.13:11:34.49#ibcon#flushed, iclass 14, count 0 2006.173.13:11:34.49#ibcon#about to write, iclass 14, count 0 2006.173.13:11:34.49#ibcon#wrote, iclass 14, count 0 2006.173.13:11:34.49#ibcon#about to read 3, iclass 14, count 0 2006.173.13:11:34.53#ibcon#read 3, iclass 14, count 0 2006.173.13:11:34.53#ibcon#about to read 4, iclass 14, count 0 2006.173.13:11:34.53#ibcon#read 4, iclass 14, count 0 2006.173.13:11:34.53#ibcon#about to read 5, iclass 14, count 0 2006.173.13:11:34.53#ibcon#read 5, iclass 14, count 0 2006.173.13:11:34.53#ibcon#about to read 6, iclass 14, count 0 2006.173.13:11:34.53#ibcon#read 6, iclass 14, count 0 2006.173.13:11:34.53#ibcon#end of sib2, iclass 14, count 0 2006.173.13:11:34.53#ibcon#*after write, iclass 14, count 0 2006.173.13:11:34.53#ibcon#*before return 0, iclass 14, count 0 2006.173.13:11:34.53#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.13:11:34.53#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.13:11:34.53#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.13:11:34.53#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.13:11:34.53$vck44/vb=3,4 2006.173.13:11:34.53#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.13:11:34.53#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.13:11:34.53#ibcon#ireg 11 cls_cnt 2 2006.173.13:11:34.53#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.13:11:34.59#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.13:11:34.59#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.13:11:34.59#ibcon#enter wrdev, iclass 16, count 2 2006.173.13:11:34.59#ibcon#first serial, iclass 16, count 2 2006.173.13:11:34.59#ibcon#enter sib2, iclass 16, count 2 2006.173.13:11:34.59#ibcon#flushed, iclass 16, count 2 2006.173.13:11:34.59#ibcon#about to write, iclass 16, count 2 2006.173.13:11:34.59#ibcon#wrote, iclass 16, count 2 2006.173.13:11:34.59#ibcon#about to read 3, iclass 16, count 2 2006.173.13:11:34.61#ibcon#read 3, iclass 16, count 2 2006.173.13:11:34.61#ibcon#about to read 4, iclass 16, count 2 2006.173.13:11:34.61#ibcon#read 4, iclass 16, count 2 2006.173.13:11:34.61#ibcon#about to read 5, iclass 16, count 2 2006.173.13:11:34.61#ibcon#read 5, iclass 16, count 2 2006.173.13:11:34.61#ibcon#about to read 6, iclass 16, count 2 2006.173.13:11:34.61#ibcon#read 6, iclass 16, count 2 2006.173.13:11:34.61#ibcon#end of sib2, iclass 16, count 2 2006.173.13:11:34.61#ibcon#*mode == 0, iclass 16, count 2 2006.173.13:11:34.61#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.13:11:34.61#ibcon#[27=AT03-04\r\n] 2006.173.13:11:34.61#ibcon#*before write, iclass 16, count 2 2006.173.13:11:34.61#ibcon#enter sib2, iclass 16, count 2 2006.173.13:11:34.61#ibcon#flushed, iclass 16, count 2 2006.173.13:11:34.61#ibcon#about to write, iclass 16, count 2 2006.173.13:11:34.61#ibcon#wrote, iclass 16, count 2 2006.173.13:11:34.61#ibcon#about to read 3, iclass 16, count 2 2006.173.13:11:34.64#ibcon#read 3, iclass 16, count 2 2006.173.13:11:34.64#ibcon#about to read 4, iclass 16, count 2 2006.173.13:11:34.64#ibcon#read 4, iclass 16, count 2 2006.173.13:11:34.64#ibcon#about to read 5, iclass 16, count 2 2006.173.13:11:34.64#ibcon#read 5, iclass 16, count 2 2006.173.13:11:34.64#ibcon#about to read 6, iclass 16, count 2 2006.173.13:11:34.64#ibcon#read 6, iclass 16, count 2 2006.173.13:11:34.64#ibcon#end of sib2, iclass 16, count 2 2006.173.13:11:34.64#ibcon#*after write, iclass 16, count 2 2006.173.13:11:34.64#ibcon#*before return 0, iclass 16, count 2 2006.173.13:11:34.64#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.13:11:34.64#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.13:11:34.64#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.13:11:34.64#ibcon#ireg 7 cls_cnt 0 2006.173.13:11:34.64#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.13:11:34.76#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.13:11:34.76#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.13:11:34.76#ibcon#enter wrdev, iclass 16, count 0 2006.173.13:11:34.76#ibcon#first serial, iclass 16, count 0 2006.173.13:11:34.76#ibcon#enter sib2, iclass 16, count 0 2006.173.13:11:34.76#ibcon#flushed, iclass 16, count 0 2006.173.13:11:34.76#ibcon#about to write, iclass 16, count 0 2006.173.13:11:34.76#ibcon#wrote, iclass 16, count 0 2006.173.13:11:34.76#ibcon#about to read 3, iclass 16, count 0 2006.173.13:11:34.78#ibcon#read 3, iclass 16, count 0 2006.173.13:11:34.78#ibcon#about to read 4, iclass 16, count 0 2006.173.13:11:34.78#ibcon#read 4, iclass 16, count 0 2006.173.13:11:34.78#ibcon#about to read 5, iclass 16, count 0 2006.173.13:11:34.78#ibcon#read 5, iclass 16, count 0 2006.173.13:11:34.78#ibcon#about to read 6, iclass 16, count 0 2006.173.13:11:34.78#ibcon#read 6, iclass 16, count 0 2006.173.13:11:34.78#ibcon#end of sib2, iclass 16, count 0 2006.173.13:11:34.78#ibcon#*mode == 0, iclass 16, count 0 2006.173.13:11:34.78#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.13:11:34.78#ibcon#[27=USB\r\n] 2006.173.13:11:34.78#ibcon#*before write, iclass 16, count 0 2006.173.13:11:34.78#ibcon#enter sib2, iclass 16, count 0 2006.173.13:11:34.78#ibcon#flushed, iclass 16, count 0 2006.173.13:11:34.78#ibcon#about to write, iclass 16, count 0 2006.173.13:11:34.78#ibcon#wrote, iclass 16, count 0 2006.173.13:11:34.78#ibcon#about to read 3, iclass 16, count 0 2006.173.13:11:34.81#ibcon#read 3, iclass 16, count 0 2006.173.13:11:34.81#ibcon#about to read 4, iclass 16, count 0 2006.173.13:11:34.81#ibcon#read 4, iclass 16, count 0 2006.173.13:11:34.81#ibcon#about to read 5, iclass 16, count 0 2006.173.13:11:34.81#ibcon#read 5, iclass 16, count 0 2006.173.13:11:34.81#ibcon#about to read 6, iclass 16, count 0 2006.173.13:11:34.81#ibcon#read 6, iclass 16, count 0 2006.173.13:11:34.81#ibcon#end of sib2, iclass 16, count 0 2006.173.13:11:34.81#ibcon#*after write, iclass 16, count 0 2006.173.13:11:34.81#ibcon#*before return 0, iclass 16, count 0 2006.173.13:11:34.81#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.13:11:34.81#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.13:11:34.81#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.13:11:34.81#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.13:11:34.81$vck44/vblo=4,679.99 2006.173.13:11:34.81#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.13:11:34.81#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.13:11:34.81#ibcon#ireg 17 cls_cnt 0 2006.173.13:11:34.81#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.13:11:34.81#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.13:11:34.81#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.13:11:34.81#ibcon#enter wrdev, iclass 18, count 0 2006.173.13:11:34.81#ibcon#first serial, iclass 18, count 0 2006.173.13:11:34.81#ibcon#enter sib2, iclass 18, count 0 2006.173.13:11:34.81#ibcon#flushed, iclass 18, count 0 2006.173.13:11:34.81#ibcon#about to write, iclass 18, count 0 2006.173.13:11:34.81#ibcon#wrote, iclass 18, count 0 2006.173.13:11:34.81#ibcon#about to read 3, iclass 18, count 0 2006.173.13:11:34.83#ibcon#read 3, iclass 18, count 0 2006.173.13:11:34.83#ibcon#about to read 4, iclass 18, count 0 2006.173.13:11:34.83#ibcon#read 4, iclass 18, count 0 2006.173.13:11:34.83#ibcon#about to read 5, iclass 18, count 0 2006.173.13:11:34.83#ibcon#read 5, iclass 18, count 0 2006.173.13:11:34.83#ibcon#about to read 6, iclass 18, count 0 2006.173.13:11:34.83#ibcon#read 6, iclass 18, count 0 2006.173.13:11:34.83#ibcon#end of sib2, iclass 18, count 0 2006.173.13:11:34.83#ibcon#*mode == 0, iclass 18, count 0 2006.173.13:11:34.83#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.13:11:34.83#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.13:11:34.83#ibcon#*before write, iclass 18, count 0 2006.173.13:11:34.83#ibcon#enter sib2, iclass 18, count 0 2006.173.13:11:34.83#ibcon#flushed, iclass 18, count 0 2006.173.13:11:34.83#ibcon#about to write, iclass 18, count 0 2006.173.13:11:34.83#ibcon#wrote, iclass 18, count 0 2006.173.13:11:34.83#ibcon#about to read 3, iclass 18, count 0 2006.173.13:11:34.87#ibcon#read 3, iclass 18, count 0 2006.173.13:11:34.87#ibcon#about to read 4, iclass 18, count 0 2006.173.13:11:34.87#ibcon#read 4, iclass 18, count 0 2006.173.13:11:34.87#ibcon#about to read 5, iclass 18, count 0 2006.173.13:11:34.87#ibcon#read 5, iclass 18, count 0 2006.173.13:11:34.87#ibcon#about to read 6, iclass 18, count 0 2006.173.13:11:34.87#ibcon#read 6, iclass 18, count 0 2006.173.13:11:34.87#ibcon#end of sib2, iclass 18, count 0 2006.173.13:11:34.87#ibcon#*after write, iclass 18, count 0 2006.173.13:11:34.87#ibcon#*before return 0, iclass 18, count 0 2006.173.13:11:34.87#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.13:11:34.87#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.13:11:34.87#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.13:11:34.87#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.13:11:34.87$vck44/vb=4,4 2006.173.13:11:34.87#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.13:11:34.87#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.13:11:34.87#ibcon#ireg 11 cls_cnt 2 2006.173.13:11:34.87#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.13:11:34.93#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.13:11:34.93#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.13:11:34.93#ibcon#enter wrdev, iclass 20, count 2 2006.173.13:11:34.93#ibcon#first serial, iclass 20, count 2 2006.173.13:11:34.93#ibcon#enter sib2, iclass 20, count 2 2006.173.13:11:34.93#ibcon#flushed, iclass 20, count 2 2006.173.13:11:34.93#ibcon#about to write, iclass 20, count 2 2006.173.13:11:34.93#ibcon#wrote, iclass 20, count 2 2006.173.13:11:34.93#ibcon#about to read 3, iclass 20, count 2 2006.173.13:11:34.95#ibcon#read 3, iclass 20, count 2 2006.173.13:11:34.95#ibcon#about to read 4, iclass 20, count 2 2006.173.13:11:34.95#ibcon#read 4, iclass 20, count 2 2006.173.13:11:34.95#ibcon#about to read 5, iclass 20, count 2 2006.173.13:11:34.95#ibcon#read 5, iclass 20, count 2 2006.173.13:11:34.95#ibcon#about to read 6, iclass 20, count 2 2006.173.13:11:34.95#ibcon#read 6, iclass 20, count 2 2006.173.13:11:34.95#ibcon#end of sib2, iclass 20, count 2 2006.173.13:11:34.95#ibcon#*mode == 0, iclass 20, count 2 2006.173.13:11:34.95#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.13:11:34.95#ibcon#[27=AT04-04\r\n] 2006.173.13:11:34.95#ibcon#*before write, iclass 20, count 2 2006.173.13:11:34.95#ibcon#enter sib2, iclass 20, count 2 2006.173.13:11:34.95#ibcon#flushed, iclass 20, count 2 2006.173.13:11:34.95#ibcon#about to write, iclass 20, count 2 2006.173.13:11:34.95#ibcon#wrote, iclass 20, count 2 2006.173.13:11:34.95#ibcon#about to read 3, iclass 20, count 2 2006.173.13:11:34.98#ibcon#read 3, iclass 20, count 2 2006.173.13:11:34.98#ibcon#about to read 4, iclass 20, count 2 2006.173.13:11:34.98#ibcon#read 4, iclass 20, count 2 2006.173.13:11:34.98#ibcon#about to read 5, iclass 20, count 2 2006.173.13:11:34.98#ibcon#read 5, iclass 20, count 2 2006.173.13:11:34.98#ibcon#about to read 6, iclass 20, count 2 2006.173.13:11:34.98#ibcon#read 6, iclass 20, count 2 2006.173.13:11:34.98#ibcon#end of sib2, iclass 20, count 2 2006.173.13:11:34.98#ibcon#*after write, iclass 20, count 2 2006.173.13:11:34.98#ibcon#*before return 0, iclass 20, count 2 2006.173.13:11:34.98#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.13:11:34.98#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.13:11:34.98#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.13:11:34.98#ibcon#ireg 7 cls_cnt 0 2006.173.13:11:34.98#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.13:11:35.10#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.13:11:35.10#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.13:11:35.10#ibcon#enter wrdev, iclass 20, count 0 2006.173.13:11:35.10#ibcon#first serial, iclass 20, count 0 2006.173.13:11:35.10#ibcon#enter sib2, iclass 20, count 0 2006.173.13:11:35.10#ibcon#flushed, iclass 20, count 0 2006.173.13:11:35.10#ibcon#about to write, iclass 20, count 0 2006.173.13:11:35.10#ibcon#wrote, iclass 20, count 0 2006.173.13:11:35.10#ibcon#about to read 3, iclass 20, count 0 2006.173.13:11:35.12#ibcon#read 3, iclass 20, count 0 2006.173.13:11:35.12#ibcon#about to read 4, iclass 20, count 0 2006.173.13:11:35.12#ibcon#read 4, iclass 20, count 0 2006.173.13:11:35.12#ibcon#about to read 5, iclass 20, count 0 2006.173.13:11:35.12#ibcon#read 5, iclass 20, count 0 2006.173.13:11:35.12#ibcon#about to read 6, iclass 20, count 0 2006.173.13:11:35.12#ibcon#read 6, iclass 20, count 0 2006.173.13:11:35.12#ibcon#end of sib2, iclass 20, count 0 2006.173.13:11:35.12#ibcon#*mode == 0, iclass 20, count 0 2006.173.13:11:35.12#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.13:11:35.12#ibcon#[27=USB\r\n] 2006.173.13:11:35.12#ibcon#*before write, iclass 20, count 0 2006.173.13:11:35.12#ibcon#enter sib2, iclass 20, count 0 2006.173.13:11:35.12#ibcon#flushed, iclass 20, count 0 2006.173.13:11:35.12#ibcon#about to write, iclass 20, count 0 2006.173.13:11:35.12#ibcon#wrote, iclass 20, count 0 2006.173.13:11:35.12#ibcon#about to read 3, iclass 20, count 0 2006.173.13:11:35.15#ibcon#read 3, iclass 20, count 0 2006.173.13:11:35.15#ibcon#about to read 4, iclass 20, count 0 2006.173.13:11:35.15#ibcon#read 4, iclass 20, count 0 2006.173.13:11:35.15#ibcon#about to read 5, iclass 20, count 0 2006.173.13:11:35.15#ibcon#read 5, iclass 20, count 0 2006.173.13:11:35.15#ibcon#about to read 6, iclass 20, count 0 2006.173.13:11:35.15#ibcon#read 6, iclass 20, count 0 2006.173.13:11:35.15#ibcon#end of sib2, iclass 20, count 0 2006.173.13:11:35.15#ibcon#*after write, iclass 20, count 0 2006.173.13:11:35.15#ibcon#*before return 0, iclass 20, count 0 2006.173.13:11:35.15#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.13:11:35.15#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.13:11:35.15#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.13:11:35.15#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.13:11:35.15$vck44/vblo=5,709.99 2006.173.13:11:35.15#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.13:11:35.15#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.13:11:35.15#ibcon#ireg 17 cls_cnt 0 2006.173.13:11:35.15#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.13:11:35.15#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.13:11:35.15#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.13:11:35.15#ibcon#enter wrdev, iclass 22, count 0 2006.173.13:11:35.15#ibcon#first serial, iclass 22, count 0 2006.173.13:11:35.15#ibcon#enter sib2, iclass 22, count 0 2006.173.13:11:35.15#ibcon#flushed, iclass 22, count 0 2006.173.13:11:35.15#ibcon#about to write, iclass 22, count 0 2006.173.13:11:35.15#ibcon#wrote, iclass 22, count 0 2006.173.13:11:35.15#ibcon#about to read 3, iclass 22, count 0 2006.173.13:11:35.17#ibcon#read 3, iclass 22, count 0 2006.173.13:11:35.17#ibcon#about to read 4, iclass 22, count 0 2006.173.13:11:35.17#ibcon#read 4, iclass 22, count 0 2006.173.13:11:35.17#ibcon#about to read 5, iclass 22, count 0 2006.173.13:11:35.17#ibcon#read 5, iclass 22, count 0 2006.173.13:11:35.17#ibcon#about to read 6, iclass 22, count 0 2006.173.13:11:35.17#ibcon#read 6, iclass 22, count 0 2006.173.13:11:35.17#ibcon#end of sib2, iclass 22, count 0 2006.173.13:11:35.17#ibcon#*mode == 0, iclass 22, count 0 2006.173.13:11:35.17#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.13:11:35.17#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.13:11:35.17#ibcon#*before write, iclass 22, count 0 2006.173.13:11:35.17#ibcon#enter sib2, iclass 22, count 0 2006.173.13:11:35.17#ibcon#flushed, iclass 22, count 0 2006.173.13:11:35.17#ibcon#about to write, iclass 22, count 0 2006.173.13:11:35.17#ibcon#wrote, iclass 22, count 0 2006.173.13:11:35.17#ibcon#about to read 3, iclass 22, count 0 2006.173.13:11:35.21#ibcon#read 3, iclass 22, count 0 2006.173.13:11:35.21#ibcon#about to read 4, iclass 22, count 0 2006.173.13:11:35.21#ibcon#read 4, iclass 22, count 0 2006.173.13:11:35.21#ibcon#about to read 5, iclass 22, count 0 2006.173.13:11:35.21#ibcon#read 5, iclass 22, count 0 2006.173.13:11:35.21#ibcon#about to read 6, iclass 22, count 0 2006.173.13:11:35.21#ibcon#read 6, iclass 22, count 0 2006.173.13:11:35.21#ibcon#end of sib2, iclass 22, count 0 2006.173.13:11:35.21#ibcon#*after write, iclass 22, count 0 2006.173.13:11:35.21#ibcon#*before return 0, iclass 22, count 0 2006.173.13:11:35.21#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.13:11:35.21#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.13:11:35.21#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.13:11:35.21#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.13:11:35.21$vck44/vb=5,4 2006.173.13:11:35.21#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.13:11:35.21#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.13:11:35.21#ibcon#ireg 11 cls_cnt 2 2006.173.13:11:35.21#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.13:11:35.27#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.13:11:35.27#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.13:11:35.27#ibcon#enter wrdev, iclass 24, count 2 2006.173.13:11:35.27#ibcon#first serial, iclass 24, count 2 2006.173.13:11:35.27#ibcon#enter sib2, iclass 24, count 2 2006.173.13:11:35.27#ibcon#flushed, iclass 24, count 2 2006.173.13:11:35.27#ibcon#about to write, iclass 24, count 2 2006.173.13:11:35.27#ibcon#wrote, iclass 24, count 2 2006.173.13:11:35.27#ibcon#about to read 3, iclass 24, count 2 2006.173.13:11:35.29#ibcon#read 3, iclass 24, count 2 2006.173.13:11:35.29#ibcon#about to read 4, iclass 24, count 2 2006.173.13:11:35.29#ibcon#read 4, iclass 24, count 2 2006.173.13:11:35.29#ibcon#about to read 5, iclass 24, count 2 2006.173.13:11:35.29#ibcon#read 5, iclass 24, count 2 2006.173.13:11:35.29#ibcon#about to read 6, iclass 24, count 2 2006.173.13:11:35.29#ibcon#read 6, iclass 24, count 2 2006.173.13:11:35.29#ibcon#end of sib2, iclass 24, count 2 2006.173.13:11:35.29#ibcon#*mode == 0, iclass 24, count 2 2006.173.13:11:35.29#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.13:11:35.29#ibcon#[27=AT05-04\r\n] 2006.173.13:11:35.29#ibcon#*before write, iclass 24, count 2 2006.173.13:11:35.29#ibcon#enter sib2, iclass 24, count 2 2006.173.13:11:35.29#ibcon#flushed, iclass 24, count 2 2006.173.13:11:35.29#ibcon#about to write, iclass 24, count 2 2006.173.13:11:35.29#ibcon#wrote, iclass 24, count 2 2006.173.13:11:35.29#ibcon#about to read 3, iclass 24, count 2 2006.173.13:11:35.32#ibcon#read 3, iclass 24, count 2 2006.173.13:11:35.32#ibcon#about to read 4, iclass 24, count 2 2006.173.13:11:35.32#ibcon#read 4, iclass 24, count 2 2006.173.13:11:35.32#ibcon#about to read 5, iclass 24, count 2 2006.173.13:11:35.32#ibcon#read 5, iclass 24, count 2 2006.173.13:11:35.32#ibcon#about to read 6, iclass 24, count 2 2006.173.13:11:35.32#ibcon#read 6, iclass 24, count 2 2006.173.13:11:35.32#ibcon#end of sib2, iclass 24, count 2 2006.173.13:11:35.32#ibcon#*after write, iclass 24, count 2 2006.173.13:11:35.32#ibcon#*before return 0, iclass 24, count 2 2006.173.13:11:35.32#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.13:11:35.32#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.13:11:35.32#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.13:11:35.32#ibcon#ireg 7 cls_cnt 0 2006.173.13:11:35.32#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.13:11:35.44#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.13:11:35.44#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.13:11:35.44#ibcon#enter wrdev, iclass 24, count 0 2006.173.13:11:35.44#ibcon#first serial, iclass 24, count 0 2006.173.13:11:35.44#ibcon#enter sib2, iclass 24, count 0 2006.173.13:11:35.44#ibcon#flushed, iclass 24, count 0 2006.173.13:11:35.44#ibcon#about to write, iclass 24, count 0 2006.173.13:11:35.44#ibcon#wrote, iclass 24, count 0 2006.173.13:11:35.44#ibcon#about to read 3, iclass 24, count 0 2006.173.13:11:35.46#ibcon#read 3, iclass 24, count 0 2006.173.13:11:35.46#ibcon#about to read 4, iclass 24, count 0 2006.173.13:11:35.46#ibcon#read 4, iclass 24, count 0 2006.173.13:11:35.46#ibcon#about to read 5, iclass 24, count 0 2006.173.13:11:35.46#ibcon#read 5, iclass 24, count 0 2006.173.13:11:35.46#ibcon#about to read 6, iclass 24, count 0 2006.173.13:11:35.46#ibcon#read 6, iclass 24, count 0 2006.173.13:11:35.46#ibcon#end of sib2, iclass 24, count 0 2006.173.13:11:35.46#ibcon#*mode == 0, iclass 24, count 0 2006.173.13:11:35.46#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.13:11:35.46#ibcon#[27=USB\r\n] 2006.173.13:11:35.46#ibcon#*before write, iclass 24, count 0 2006.173.13:11:35.46#ibcon#enter sib2, iclass 24, count 0 2006.173.13:11:35.46#ibcon#flushed, iclass 24, count 0 2006.173.13:11:35.46#ibcon#about to write, iclass 24, count 0 2006.173.13:11:35.46#ibcon#wrote, iclass 24, count 0 2006.173.13:11:35.46#ibcon#about to read 3, iclass 24, count 0 2006.173.13:11:35.49#ibcon#read 3, iclass 24, count 0 2006.173.13:11:35.49#ibcon#about to read 4, iclass 24, count 0 2006.173.13:11:35.49#ibcon#read 4, iclass 24, count 0 2006.173.13:11:35.49#ibcon#about to read 5, iclass 24, count 0 2006.173.13:11:35.49#ibcon#read 5, iclass 24, count 0 2006.173.13:11:35.49#ibcon#about to read 6, iclass 24, count 0 2006.173.13:11:35.49#ibcon#read 6, iclass 24, count 0 2006.173.13:11:35.49#ibcon#end of sib2, iclass 24, count 0 2006.173.13:11:35.49#ibcon#*after write, iclass 24, count 0 2006.173.13:11:35.49#ibcon#*before return 0, iclass 24, count 0 2006.173.13:11:35.49#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.13:11:35.49#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.13:11:35.49#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.13:11:35.49#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.13:11:35.49$vck44/vblo=6,719.99 2006.173.13:11:35.49#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.13:11:35.49#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.13:11:35.49#ibcon#ireg 17 cls_cnt 0 2006.173.13:11:35.49#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.13:11:35.49#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.13:11:35.49#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.13:11:35.49#ibcon#enter wrdev, iclass 26, count 0 2006.173.13:11:35.49#ibcon#first serial, iclass 26, count 0 2006.173.13:11:35.49#ibcon#enter sib2, iclass 26, count 0 2006.173.13:11:35.49#ibcon#flushed, iclass 26, count 0 2006.173.13:11:35.49#ibcon#about to write, iclass 26, count 0 2006.173.13:11:35.49#ibcon#wrote, iclass 26, count 0 2006.173.13:11:35.49#ibcon#about to read 3, iclass 26, count 0 2006.173.13:11:35.51#ibcon#read 3, iclass 26, count 0 2006.173.13:11:35.51#ibcon#about to read 4, iclass 26, count 0 2006.173.13:11:35.51#ibcon#read 4, iclass 26, count 0 2006.173.13:11:35.51#ibcon#about to read 5, iclass 26, count 0 2006.173.13:11:35.51#ibcon#read 5, iclass 26, count 0 2006.173.13:11:35.51#ibcon#about to read 6, iclass 26, count 0 2006.173.13:11:35.51#ibcon#read 6, iclass 26, count 0 2006.173.13:11:35.51#ibcon#end of sib2, iclass 26, count 0 2006.173.13:11:35.51#ibcon#*mode == 0, iclass 26, count 0 2006.173.13:11:35.51#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.13:11:35.51#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.13:11:35.51#ibcon#*before write, iclass 26, count 0 2006.173.13:11:35.51#ibcon#enter sib2, iclass 26, count 0 2006.173.13:11:35.51#ibcon#flushed, iclass 26, count 0 2006.173.13:11:35.51#ibcon#about to write, iclass 26, count 0 2006.173.13:11:35.51#ibcon#wrote, iclass 26, count 0 2006.173.13:11:35.51#ibcon#about to read 3, iclass 26, count 0 2006.173.13:11:35.55#ibcon#read 3, iclass 26, count 0 2006.173.13:11:35.55#ibcon#about to read 4, iclass 26, count 0 2006.173.13:11:35.55#ibcon#read 4, iclass 26, count 0 2006.173.13:11:35.55#ibcon#about to read 5, iclass 26, count 0 2006.173.13:11:35.55#ibcon#read 5, iclass 26, count 0 2006.173.13:11:35.55#ibcon#about to read 6, iclass 26, count 0 2006.173.13:11:35.55#ibcon#read 6, iclass 26, count 0 2006.173.13:11:35.55#ibcon#end of sib2, iclass 26, count 0 2006.173.13:11:35.55#ibcon#*after write, iclass 26, count 0 2006.173.13:11:35.55#ibcon#*before return 0, iclass 26, count 0 2006.173.13:11:35.55#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.13:11:35.55#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.13:11:35.55#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.13:11:35.55#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.13:11:35.55$vck44/vb=6,4 2006.173.13:11:35.55#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.13:11:35.55#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.13:11:35.55#ibcon#ireg 11 cls_cnt 2 2006.173.13:11:35.55#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.13:11:35.61#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.13:11:35.61#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.13:11:35.61#ibcon#enter wrdev, iclass 28, count 2 2006.173.13:11:35.61#ibcon#first serial, iclass 28, count 2 2006.173.13:11:35.61#ibcon#enter sib2, iclass 28, count 2 2006.173.13:11:35.61#ibcon#flushed, iclass 28, count 2 2006.173.13:11:35.61#ibcon#about to write, iclass 28, count 2 2006.173.13:11:35.61#ibcon#wrote, iclass 28, count 2 2006.173.13:11:35.61#ibcon#about to read 3, iclass 28, count 2 2006.173.13:11:35.63#ibcon#read 3, iclass 28, count 2 2006.173.13:11:35.63#ibcon#about to read 4, iclass 28, count 2 2006.173.13:11:35.63#ibcon#read 4, iclass 28, count 2 2006.173.13:11:35.63#ibcon#about to read 5, iclass 28, count 2 2006.173.13:11:35.63#ibcon#read 5, iclass 28, count 2 2006.173.13:11:35.63#ibcon#about to read 6, iclass 28, count 2 2006.173.13:11:35.63#ibcon#read 6, iclass 28, count 2 2006.173.13:11:35.63#ibcon#end of sib2, iclass 28, count 2 2006.173.13:11:35.63#ibcon#*mode == 0, iclass 28, count 2 2006.173.13:11:35.63#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.13:11:35.63#ibcon#[27=AT06-04\r\n] 2006.173.13:11:35.63#ibcon#*before write, iclass 28, count 2 2006.173.13:11:35.63#ibcon#enter sib2, iclass 28, count 2 2006.173.13:11:35.63#ibcon#flushed, iclass 28, count 2 2006.173.13:11:35.63#ibcon#about to write, iclass 28, count 2 2006.173.13:11:35.63#ibcon#wrote, iclass 28, count 2 2006.173.13:11:35.63#ibcon#about to read 3, iclass 28, count 2 2006.173.13:11:35.66#ibcon#read 3, iclass 28, count 2 2006.173.13:11:35.66#ibcon#about to read 4, iclass 28, count 2 2006.173.13:11:35.66#ibcon#read 4, iclass 28, count 2 2006.173.13:11:35.66#ibcon#about to read 5, iclass 28, count 2 2006.173.13:11:35.66#ibcon#read 5, iclass 28, count 2 2006.173.13:11:35.66#ibcon#about to read 6, iclass 28, count 2 2006.173.13:11:35.66#ibcon#read 6, iclass 28, count 2 2006.173.13:11:35.66#ibcon#end of sib2, iclass 28, count 2 2006.173.13:11:35.66#ibcon#*after write, iclass 28, count 2 2006.173.13:11:35.66#ibcon#*before return 0, iclass 28, count 2 2006.173.13:11:35.66#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.13:11:35.66#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.13:11:35.66#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.13:11:35.66#ibcon#ireg 7 cls_cnt 0 2006.173.13:11:35.66#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.13:11:35.78#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.13:11:35.78#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.13:11:35.78#ibcon#enter wrdev, iclass 28, count 0 2006.173.13:11:35.78#ibcon#first serial, iclass 28, count 0 2006.173.13:11:35.78#ibcon#enter sib2, iclass 28, count 0 2006.173.13:11:35.78#ibcon#flushed, iclass 28, count 0 2006.173.13:11:35.78#ibcon#about to write, iclass 28, count 0 2006.173.13:11:35.78#ibcon#wrote, iclass 28, count 0 2006.173.13:11:35.78#ibcon#about to read 3, iclass 28, count 0 2006.173.13:11:35.80#ibcon#read 3, iclass 28, count 0 2006.173.13:11:35.80#ibcon#about to read 4, iclass 28, count 0 2006.173.13:11:35.80#ibcon#read 4, iclass 28, count 0 2006.173.13:11:35.80#ibcon#about to read 5, iclass 28, count 0 2006.173.13:11:35.80#ibcon#read 5, iclass 28, count 0 2006.173.13:11:35.80#ibcon#about to read 6, iclass 28, count 0 2006.173.13:11:35.80#ibcon#read 6, iclass 28, count 0 2006.173.13:11:35.80#ibcon#end of sib2, iclass 28, count 0 2006.173.13:11:35.80#ibcon#*mode == 0, iclass 28, count 0 2006.173.13:11:35.80#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.13:11:35.80#ibcon#[27=USB\r\n] 2006.173.13:11:35.80#ibcon#*before write, iclass 28, count 0 2006.173.13:11:35.80#ibcon#enter sib2, iclass 28, count 0 2006.173.13:11:35.80#ibcon#flushed, iclass 28, count 0 2006.173.13:11:35.80#ibcon#about to write, iclass 28, count 0 2006.173.13:11:35.80#ibcon#wrote, iclass 28, count 0 2006.173.13:11:35.80#ibcon#about to read 3, iclass 28, count 0 2006.173.13:11:35.83#ibcon#read 3, iclass 28, count 0 2006.173.13:11:35.83#ibcon#about to read 4, iclass 28, count 0 2006.173.13:11:35.83#ibcon#read 4, iclass 28, count 0 2006.173.13:11:35.83#ibcon#about to read 5, iclass 28, count 0 2006.173.13:11:35.83#ibcon#read 5, iclass 28, count 0 2006.173.13:11:35.83#ibcon#about to read 6, iclass 28, count 0 2006.173.13:11:35.83#ibcon#read 6, iclass 28, count 0 2006.173.13:11:35.83#ibcon#end of sib2, iclass 28, count 0 2006.173.13:11:35.83#ibcon#*after write, iclass 28, count 0 2006.173.13:11:35.83#ibcon#*before return 0, iclass 28, count 0 2006.173.13:11:35.83#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.13:11:35.83#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.13:11:35.83#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.13:11:35.83#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.13:11:35.83$vck44/vblo=7,734.99 2006.173.13:11:35.83#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.13:11:35.83#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.13:11:35.83#ibcon#ireg 17 cls_cnt 0 2006.173.13:11:35.83#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.13:11:35.83#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.13:11:35.83#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.13:11:35.83#ibcon#enter wrdev, iclass 30, count 0 2006.173.13:11:35.83#ibcon#first serial, iclass 30, count 0 2006.173.13:11:35.83#ibcon#enter sib2, iclass 30, count 0 2006.173.13:11:35.83#ibcon#flushed, iclass 30, count 0 2006.173.13:11:35.83#ibcon#about to write, iclass 30, count 0 2006.173.13:11:35.83#ibcon#wrote, iclass 30, count 0 2006.173.13:11:35.83#ibcon#about to read 3, iclass 30, count 0 2006.173.13:11:35.85#ibcon#read 3, iclass 30, count 0 2006.173.13:11:35.85#ibcon#about to read 4, iclass 30, count 0 2006.173.13:11:35.85#ibcon#read 4, iclass 30, count 0 2006.173.13:11:35.85#ibcon#about to read 5, iclass 30, count 0 2006.173.13:11:35.85#ibcon#read 5, iclass 30, count 0 2006.173.13:11:35.85#ibcon#about to read 6, iclass 30, count 0 2006.173.13:11:35.85#ibcon#read 6, iclass 30, count 0 2006.173.13:11:35.85#ibcon#end of sib2, iclass 30, count 0 2006.173.13:11:35.85#ibcon#*mode == 0, iclass 30, count 0 2006.173.13:11:35.85#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.13:11:35.85#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.13:11:35.85#ibcon#*before write, iclass 30, count 0 2006.173.13:11:35.85#ibcon#enter sib2, iclass 30, count 0 2006.173.13:11:35.85#ibcon#flushed, iclass 30, count 0 2006.173.13:11:35.85#ibcon#about to write, iclass 30, count 0 2006.173.13:11:35.85#ibcon#wrote, iclass 30, count 0 2006.173.13:11:35.85#ibcon#about to read 3, iclass 30, count 0 2006.173.13:11:35.89#ibcon#read 3, iclass 30, count 0 2006.173.13:11:35.89#ibcon#about to read 4, iclass 30, count 0 2006.173.13:11:35.89#ibcon#read 4, iclass 30, count 0 2006.173.13:11:35.89#ibcon#about to read 5, iclass 30, count 0 2006.173.13:11:35.89#ibcon#read 5, iclass 30, count 0 2006.173.13:11:35.89#ibcon#about to read 6, iclass 30, count 0 2006.173.13:11:35.89#ibcon#read 6, iclass 30, count 0 2006.173.13:11:35.89#ibcon#end of sib2, iclass 30, count 0 2006.173.13:11:35.89#ibcon#*after write, iclass 30, count 0 2006.173.13:11:35.89#ibcon#*before return 0, iclass 30, count 0 2006.173.13:11:35.89#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.13:11:35.89#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.13:11:35.89#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.13:11:35.89#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.13:11:35.89$vck44/vb=7,4 2006.173.13:11:35.89#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.173.13:11:35.89#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.173.13:11:35.89#ibcon#ireg 11 cls_cnt 2 2006.173.13:11:35.89#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.13:11:35.95#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.13:11:35.95#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.13:11:35.95#ibcon#enter wrdev, iclass 32, count 2 2006.173.13:11:35.95#ibcon#first serial, iclass 32, count 2 2006.173.13:11:35.95#ibcon#enter sib2, iclass 32, count 2 2006.173.13:11:35.95#ibcon#flushed, iclass 32, count 2 2006.173.13:11:35.95#ibcon#about to write, iclass 32, count 2 2006.173.13:11:35.95#ibcon#wrote, iclass 32, count 2 2006.173.13:11:35.95#ibcon#about to read 3, iclass 32, count 2 2006.173.13:11:35.97#ibcon#read 3, iclass 32, count 2 2006.173.13:11:35.97#ibcon#about to read 4, iclass 32, count 2 2006.173.13:11:35.97#ibcon#read 4, iclass 32, count 2 2006.173.13:11:35.97#ibcon#about to read 5, iclass 32, count 2 2006.173.13:11:35.97#ibcon#read 5, iclass 32, count 2 2006.173.13:11:35.97#ibcon#about to read 6, iclass 32, count 2 2006.173.13:11:35.97#ibcon#read 6, iclass 32, count 2 2006.173.13:11:35.97#ibcon#end of sib2, iclass 32, count 2 2006.173.13:11:35.97#ibcon#*mode == 0, iclass 32, count 2 2006.173.13:11:35.97#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.173.13:11:35.97#ibcon#[27=AT07-04\r\n] 2006.173.13:11:35.97#ibcon#*before write, iclass 32, count 2 2006.173.13:11:35.97#ibcon#enter sib2, iclass 32, count 2 2006.173.13:11:35.97#ibcon#flushed, iclass 32, count 2 2006.173.13:11:35.97#ibcon#about to write, iclass 32, count 2 2006.173.13:11:35.97#ibcon#wrote, iclass 32, count 2 2006.173.13:11:35.97#ibcon#about to read 3, iclass 32, count 2 2006.173.13:11:36.00#ibcon#read 3, iclass 32, count 2 2006.173.13:11:36.00#ibcon#about to read 4, iclass 32, count 2 2006.173.13:11:36.00#ibcon#read 4, iclass 32, count 2 2006.173.13:11:36.00#ibcon#about to read 5, iclass 32, count 2 2006.173.13:11:36.00#ibcon#read 5, iclass 32, count 2 2006.173.13:11:36.00#ibcon#about to read 6, iclass 32, count 2 2006.173.13:11:36.00#ibcon#read 6, iclass 32, count 2 2006.173.13:11:36.00#ibcon#end of sib2, iclass 32, count 2 2006.173.13:11:36.00#ibcon#*after write, iclass 32, count 2 2006.173.13:11:36.00#ibcon#*before return 0, iclass 32, count 2 2006.173.13:11:36.00#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.13:11:36.00#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.173.13:11:36.00#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.173.13:11:36.00#ibcon#ireg 7 cls_cnt 0 2006.173.13:11:36.00#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.13:11:36.12#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.13:11:36.12#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.13:11:36.12#ibcon#enter wrdev, iclass 32, count 0 2006.173.13:11:36.12#ibcon#first serial, iclass 32, count 0 2006.173.13:11:36.12#ibcon#enter sib2, iclass 32, count 0 2006.173.13:11:36.12#ibcon#flushed, iclass 32, count 0 2006.173.13:11:36.12#ibcon#about to write, iclass 32, count 0 2006.173.13:11:36.12#ibcon#wrote, iclass 32, count 0 2006.173.13:11:36.12#ibcon#about to read 3, iclass 32, count 0 2006.173.13:11:36.14#ibcon#read 3, iclass 32, count 0 2006.173.13:11:36.14#ibcon#about to read 4, iclass 32, count 0 2006.173.13:11:36.14#ibcon#read 4, iclass 32, count 0 2006.173.13:11:36.14#ibcon#about to read 5, iclass 32, count 0 2006.173.13:11:36.14#ibcon#read 5, iclass 32, count 0 2006.173.13:11:36.14#ibcon#about to read 6, iclass 32, count 0 2006.173.13:11:36.14#ibcon#read 6, iclass 32, count 0 2006.173.13:11:36.14#ibcon#end of sib2, iclass 32, count 0 2006.173.13:11:36.14#ibcon#*mode == 0, iclass 32, count 0 2006.173.13:11:36.14#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.13:11:36.14#ibcon#[27=USB\r\n] 2006.173.13:11:36.14#ibcon#*before write, iclass 32, count 0 2006.173.13:11:36.14#ibcon#enter sib2, iclass 32, count 0 2006.173.13:11:36.14#ibcon#flushed, iclass 32, count 0 2006.173.13:11:36.14#ibcon#about to write, iclass 32, count 0 2006.173.13:11:36.14#ibcon#wrote, iclass 32, count 0 2006.173.13:11:36.14#ibcon#about to read 3, iclass 32, count 0 2006.173.13:11:36.17#ibcon#read 3, iclass 32, count 0 2006.173.13:11:36.17#ibcon#about to read 4, iclass 32, count 0 2006.173.13:11:36.17#ibcon#read 4, iclass 32, count 0 2006.173.13:11:36.17#ibcon#about to read 5, iclass 32, count 0 2006.173.13:11:36.17#ibcon#read 5, iclass 32, count 0 2006.173.13:11:36.17#ibcon#about to read 6, iclass 32, count 0 2006.173.13:11:36.17#ibcon#read 6, iclass 32, count 0 2006.173.13:11:36.17#ibcon#end of sib2, iclass 32, count 0 2006.173.13:11:36.17#ibcon#*after write, iclass 32, count 0 2006.173.13:11:36.17#ibcon#*before return 0, iclass 32, count 0 2006.173.13:11:36.17#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.13:11:36.17#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.173.13:11:36.17#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.13:11:36.17#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.13:11:36.17$vck44/vblo=8,744.99 2006.173.13:11:36.17#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.13:11:36.17#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.13:11:36.17#ibcon#ireg 17 cls_cnt 0 2006.173.13:11:36.17#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.13:11:36.17#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.13:11:36.17#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.13:11:36.17#ibcon#enter wrdev, iclass 34, count 0 2006.173.13:11:36.17#ibcon#first serial, iclass 34, count 0 2006.173.13:11:36.17#ibcon#enter sib2, iclass 34, count 0 2006.173.13:11:36.17#ibcon#flushed, iclass 34, count 0 2006.173.13:11:36.17#ibcon#about to write, iclass 34, count 0 2006.173.13:11:36.17#ibcon#wrote, iclass 34, count 0 2006.173.13:11:36.17#ibcon#about to read 3, iclass 34, count 0 2006.173.13:11:36.19#ibcon#read 3, iclass 34, count 0 2006.173.13:11:36.19#ibcon#about to read 4, iclass 34, count 0 2006.173.13:11:36.19#ibcon#read 4, iclass 34, count 0 2006.173.13:11:36.19#ibcon#about to read 5, iclass 34, count 0 2006.173.13:11:36.19#ibcon#read 5, iclass 34, count 0 2006.173.13:11:36.19#ibcon#about to read 6, iclass 34, count 0 2006.173.13:11:36.19#ibcon#read 6, iclass 34, count 0 2006.173.13:11:36.19#ibcon#end of sib2, iclass 34, count 0 2006.173.13:11:36.19#ibcon#*mode == 0, iclass 34, count 0 2006.173.13:11:36.19#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.13:11:36.19#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.13:11:36.19#ibcon#*before write, iclass 34, count 0 2006.173.13:11:36.19#ibcon#enter sib2, iclass 34, count 0 2006.173.13:11:36.19#ibcon#flushed, iclass 34, count 0 2006.173.13:11:36.19#ibcon#about to write, iclass 34, count 0 2006.173.13:11:36.19#ibcon#wrote, iclass 34, count 0 2006.173.13:11:36.19#ibcon#about to read 3, iclass 34, count 0 2006.173.13:11:36.23#ibcon#read 3, iclass 34, count 0 2006.173.13:11:36.23#ibcon#about to read 4, iclass 34, count 0 2006.173.13:11:36.23#ibcon#read 4, iclass 34, count 0 2006.173.13:11:36.23#ibcon#about to read 5, iclass 34, count 0 2006.173.13:11:36.23#ibcon#read 5, iclass 34, count 0 2006.173.13:11:36.23#ibcon#about to read 6, iclass 34, count 0 2006.173.13:11:36.23#ibcon#read 6, iclass 34, count 0 2006.173.13:11:36.23#ibcon#end of sib2, iclass 34, count 0 2006.173.13:11:36.23#ibcon#*after write, iclass 34, count 0 2006.173.13:11:36.23#ibcon#*before return 0, iclass 34, count 0 2006.173.13:11:36.23#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.13:11:36.23#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.13:11:36.23#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.13:11:36.23#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.13:11:36.23$vck44/vb=8,4 2006.173.13:11:36.23#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.13:11:36.23#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.13:11:36.23#ibcon#ireg 11 cls_cnt 2 2006.173.13:11:36.23#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.13:11:36.29#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.13:11:36.29#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.13:11:36.29#ibcon#enter wrdev, iclass 36, count 2 2006.173.13:11:36.29#ibcon#first serial, iclass 36, count 2 2006.173.13:11:36.29#ibcon#enter sib2, iclass 36, count 2 2006.173.13:11:36.29#ibcon#flushed, iclass 36, count 2 2006.173.13:11:36.29#ibcon#about to write, iclass 36, count 2 2006.173.13:11:36.29#ibcon#wrote, iclass 36, count 2 2006.173.13:11:36.29#ibcon#about to read 3, iclass 36, count 2 2006.173.13:11:36.31#ibcon#read 3, iclass 36, count 2 2006.173.13:11:36.31#ibcon#about to read 4, iclass 36, count 2 2006.173.13:11:36.31#ibcon#read 4, iclass 36, count 2 2006.173.13:11:36.31#ibcon#about to read 5, iclass 36, count 2 2006.173.13:11:36.31#ibcon#read 5, iclass 36, count 2 2006.173.13:11:36.31#ibcon#about to read 6, iclass 36, count 2 2006.173.13:11:36.31#ibcon#read 6, iclass 36, count 2 2006.173.13:11:36.31#ibcon#end of sib2, iclass 36, count 2 2006.173.13:11:36.31#ibcon#*mode == 0, iclass 36, count 2 2006.173.13:11:36.31#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.13:11:36.31#ibcon#[27=AT08-04\r\n] 2006.173.13:11:36.31#ibcon#*before write, iclass 36, count 2 2006.173.13:11:36.31#ibcon#enter sib2, iclass 36, count 2 2006.173.13:11:36.31#ibcon#flushed, iclass 36, count 2 2006.173.13:11:36.31#ibcon#about to write, iclass 36, count 2 2006.173.13:11:36.31#ibcon#wrote, iclass 36, count 2 2006.173.13:11:36.31#ibcon#about to read 3, iclass 36, count 2 2006.173.13:11:36.34#ibcon#read 3, iclass 36, count 2 2006.173.13:11:36.34#ibcon#about to read 4, iclass 36, count 2 2006.173.13:11:36.34#ibcon#read 4, iclass 36, count 2 2006.173.13:11:36.34#ibcon#about to read 5, iclass 36, count 2 2006.173.13:11:36.34#ibcon#read 5, iclass 36, count 2 2006.173.13:11:36.34#ibcon#about to read 6, iclass 36, count 2 2006.173.13:11:36.34#ibcon#read 6, iclass 36, count 2 2006.173.13:11:36.34#ibcon#end of sib2, iclass 36, count 2 2006.173.13:11:36.34#ibcon#*after write, iclass 36, count 2 2006.173.13:11:36.34#ibcon#*before return 0, iclass 36, count 2 2006.173.13:11:36.34#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.13:11:36.34#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.13:11:36.34#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.13:11:36.34#ibcon#ireg 7 cls_cnt 0 2006.173.13:11:36.34#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.13:11:36.46#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.13:11:36.46#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.13:11:36.46#ibcon#enter wrdev, iclass 36, count 0 2006.173.13:11:36.46#ibcon#first serial, iclass 36, count 0 2006.173.13:11:36.46#ibcon#enter sib2, iclass 36, count 0 2006.173.13:11:36.46#ibcon#flushed, iclass 36, count 0 2006.173.13:11:36.46#ibcon#about to write, iclass 36, count 0 2006.173.13:11:36.46#ibcon#wrote, iclass 36, count 0 2006.173.13:11:36.46#ibcon#about to read 3, iclass 36, count 0 2006.173.13:11:36.48#ibcon#read 3, iclass 36, count 0 2006.173.13:11:36.48#ibcon#about to read 4, iclass 36, count 0 2006.173.13:11:36.48#ibcon#read 4, iclass 36, count 0 2006.173.13:11:36.48#ibcon#about to read 5, iclass 36, count 0 2006.173.13:11:36.48#ibcon#read 5, iclass 36, count 0 2006.173.13:11:36.48#ibcon#about to read 6, iclass 36, count 0 2006.173.13:11:36.48#ibcon#read 6, iclass 36, count 0 2006.173.13:11:36.48#ibcon#end of sib2, iclass 36, count 0 2006.173.13:11:36.48#ibcon#*mode == 0, iclass 36, count 0 2006.173.13:11:36.48#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.13:11:36.48#ibcon#[27=USB\r\n] 2006.173.13:11:36.48#ibcon#*before write, iclass 36, count 0 2006.173.13:11:36.48#ibcon#enter sib2, iclass 36, count 0 2006.173.13:11:36.48#ibcon#flushed, iclass 36, count 0 2006.173.13:11:36.48#ibcon#about to write, iclass 36, count 0 2006.173.13:11:36.48#ibcon#wrote, iclass 36, count 0 2006.173.13:11:36.48#ibcon#about to read 3, iclass 36, count 0 2006.173.13:11:36.51#ibcon#read 3, iclass 36, count 0 2006.173.13:11:36.51#ibcon#about to read 4, iclass 36, count 0 2006.173.13:11:36.51#ibcon#read 4, iclass 36, count 0 2006.173.13:11:36.51#ibcon#about to read 5, iclass 36, count 0 2006.173.13:11:36.51#ibcon#read 5, iclass 36, count 0 2006.173.13:11:36.51#ibcon#about to read 6, iclass 36, count 0 2006.173.13:11:36.51#ibcon#read 6, iclass 36, count 0 2006.173.13:11:36.51#ibcon#end of sib2, iclass 36, count 0 2006.173.13:11:36.51#ibcon#*after write, iclass 36, count 0 2006.173.13:11:36.51#ibcon#*before return 0, iclass 36, count 0 2006.173.13:11:36.51#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.13:11:36.51#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.13:11:36.51#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.13:11:36.51#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.13:11:36.51$vck44/vabw=wide 2006.173.13:11:36.51#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.13:11:36.51#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.13:11:36.51#ibcon#ireg 8 cls_cnt 0 2006.173.13:11:36.51#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.13:11:36.51#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.13:11:36.51#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.13:11:36.51#ibcon#enter wrdev, iclass 38, count 0 2006.173.13:11:36.51#ibcon#first serial, iclass 38, count 0 2006.173.13:11:36.51#ibcon#enter sib2, iclass 38, count 0 2006.173.13:11:36.51#ibcon#flushed, iclass 38, count 0 2006.173.13:11:36.51#ibcon#about to write, iclass 38, count 0 2006.173.13:11:36.51#ibcon#wrote, iclass 38, count 0 2006.173.13:11:36.51#ibcon#about to read 3, iclass 38, count 0 2006.173.13:11:36.53#ibcon#read 3, iclass 38, count 0 2006.173.13:11:36.53#ibcon#about to read 4, iclass 38, count 0 2006.173.13:11:36.53#ibcon#read 4, iclass 38, count 0 2006.173.13:11:36.53#ibcon#about to read 5, iclass 38, count 0 2006.173.13:11:36.53#ibcon#read 5, iclass 38, count 0 2006.173.13:11:36.53#ibcon#about to read 6, iclass 38, count 0 2006.173.13:11:36.53#ibcon#read 6, iclass 38, count 0 2006.173.13:11:36.53#ibcon#end of sib2, iclass 38, count 0 2006.173.13:11:36.53#ibcon#*mode == 0, iclass 38, count 0 2006.173.13:11:36.53#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.13:11:36.53#ibcon#[25=BW32\r\n] 2006.173.13:11:36.53#ibcon#*before write, iclass 38, count 0 2006.173.13:11:36.53#ibcon#enter sib2, iclass 38, count 0 2006.173.13:11:36.53#ibcon#flushed, iclass 38, count 0 2006.173.13:11:36.53#ibcon#about to write, iclass 38, count 0 2006.173.13:11:36.53#ibcon#wrote, iclass 38, count 0 2006.173.13:11:36.53#ibcon#about to read 3, iclass 38, count 0 2006.173.13:11:36.56#ibcon#read 3, iclass 38, count 0 2006.173.13:11:36.56#ibcon#about to read 4, iclass 38, count 0 2006.173.13:11:36.56#ibcon#read 4, iclass 38, count 0 2006.173.13:11:36.56#ibcon#about to read 5, iclass 38, count 0 2006.173.13:11:36.56#ibcon#read 5, iclass 38, count 0 2006.173.13:11:36.56#ibcon#about to read 6, iclass 38, count 0 2006.173.13:11:36.56#ibcon#read 6, iclass 38, count 0 2006.173.13:11:36.56#ibcon#end of sib2, iclass 38, count 0 2006.173.13:11:36.56#ibcon#*after write, iclass 38, count 0 2006.173.13:11:36.56#ibcon#*before return 0, iclass 38, count 0 2006.173.13:11:36.56#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.13:11:36.56#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.13:11:36.56#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.13:11:36.56#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.13:11:36.56$vck44/vbbw=wide 2006.173.13:11:36.56#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.13:11:36.56#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.13:11:36.56#ibcon#ireg 8 cls_cnt 0 2006.173.13:11:36.56#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.13:11:36.63#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.13:11:36.63#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.13:11:36.63#ibcon#enter wrdev, iclass 40, count 0 2006.173.13:11:36.63#ibcon#first serial, iclass 40, count 0 2006.173.13:11:36.63#ibcon#enter sib2, iclass 40, count 0 2006.173.13:11:36.63#ibcon#flushed, iclass 40, count 0 2006.173.13:11:36.63#ibcon#about to write, iclass 40, count 0 2006.173.13:11:36.63#ibcon#wrote, iclass 40, count 0 2006.173.13:11:36.63#ibcon#about to read 3, iclass 40, count 0 2006.173.13:11:36.65#ibcon#read 3, iclass 40, count 0 2006.173.13:11:36.65#ibcon#about to read 4, iclass 40, count 0 2006.173.13:11:36.65#ibcon#read 4, iclass 40, count 0 2006.173.13:11:36.65#ibcon#about to read 5, iclass 40, count 0 2006.173.13:11:36.65#ibcon#read 5, iclass 40, count 0 2006.173.13:11:36.65#ibcon#about to read 6, iclass 40, count 0 2006.173.13:11:36.65#ibcon#read 6, iclass 40, count 0 2006.173.13:11:36.65#ibcon#end of sib2, iclass 40, count 0 2006.173.13:11:36.65#ibcon#*mode == 0, iclass 40, count 0 2006.173.13:11:36.65#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.13:11:36.65#ibcon#[27=BW32\r\n] 2006.173.13:11:36.65#ibcon#*before write, iclass 40, count 0 2006.173.13:11:36.65#ibcon#enter sib2, iclass 40, count 0 2006.173.13:11:36.65#ibcon#flushed, iclass 40, count 0 2006.173.13:11:36.65#ibcon#about to write, iclass 40, count 0 2006.173.13:11:36.65#ibcon#wrote, iclass 40, count 0 2006.173.13:11:36.65#ibcon#about to read 3, iclass 40, count 0 2006.173.13:11:36.68#ibcon#read 3, iclass 40, count 0 2006.173.13:11:36.68#ibcon#about to read 4, iclass 40, count 0 2006.173.13:11:36.68#ibcon#read 4, iclass 40, count 0 2006.173.13:11:36.68#ibcon#about to read 5, iclass 40, count 0 2006.173.13:11:36.68#ibcon#read 5, iclass 40, count 0 2006.173.13:11:36.68#ibcon#about to read 6, iclass 40, count 0 2006.173.13:11:36.68#ibcon#read 6, iclass 40, count 0 2006.173.13:11:36.68#ibcon#end of sib2, iclass 40, count 0 2006.173.13:11:36.68#ibcon#*after write, iclass 40, count 0 2006.173.13:11:36.68#ibcon#*before return 0, iclass 40, count 0 2006.173.13:11:36.68#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.13:11:36.68#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.13:11:36.68#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.13:11:36.68#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.13:11:36.68$setupk4/ifdk4 2006.173.13:11:36.68$ifdk4/lo= 2006.173.13:11:36.68$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.13:11:36.68$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.13:11:36.68$ifdk4/patch= 2006.173.13:11:36.68$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.13:11:36.68$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.13:11:36.68$setupk4/!*+20s 2006.173.13:11:40.02#abcon#<5=/06 0.4 0.7 22.12 971004.2\r\n> 2006.173.13:11:40.04#abcon#{5=INTERFACE CLEAR} 2006.173.13:11:40.10#abcon#[5=S1D000X0/0*\r\n] 2006.173.13:11:43.13#trakl#Source acquired 2006.173.13:11:44.13#flagr#flagr/antenna,acquired 2006.173.13:11:50.19#abcon#<5=/06 0.4 0.8 22.11 971004.2\r\n> 2006.173.13:11:50.21#abcon#{5=INTERFACE CLEAR} 2006.173.13:11:50.27#abcon#[5=S1D000X0/0*\r\n] 2006.173.13:11:51.20$setupk4/"tpicd 2006.173.13:11:51.20$setupk4/echo=off 2006.173.13:11:51.20$setupk4/xlog=off 2006.173.13:11:51.20:!2006.173.13:16:46 2006.173.13:16:46.00:preob 2006.173.13:16:46.14/onsource/TRACKING 2006.173.13:16:46.14:!2006.173.13:16:56 2006.173.13:16:56.00:"tape 2006.173.13:16:56.00:"st=record 2006.173.13:16:56.00:data_valid=on 2006.173.13:16:56.00:midob 2006.173.13:16:56.14/onsource/TRACKING 2006.173.13:16:56.14/wx/22.08,1004.2,98 2006.173.13:16:56.26/cable/+6.5055E-03 2006.173.13:16:57.35/va/01,07,usb,yes,50,54 2006.173.13:16:57.35/va/02,06,usb,yes,50,51 2006.173.13:16:57.35/va/03,05,usb,yes,63,65 2006.173.13:16:57.35/va/04,06,usb,yes,51,54 2006.173.13:16:57.35/va/05,04,usb,yes,41,42 2006.173.13:16:57.35/va/06,03,usb,yes,57,56 2006.173.13:16:57.35/va/07,04,usb,yes,46,48 2006.173.13:16:57.35/va/08,04,usb,yes,40,47 2006.173.13:16:57.58/valo/01,524.99,yes,locked 2006.173.13:16:57.58/valo/02,534.99,yes,locked 2006.173.13:16:57.58/valo/03,564.99,yes,locked 2006.173.13:16:57.58/valo/04,624.99,yes,locked 2006.173.13:16:57.58/valo/05,734.99,yes,locked 2006.173.13:16:57.58/valo/06,814.99,yes,locked 2006.173.13:16:57.58/valo/07,864.99,yes,locked 2006.173.13:16:57.58/valo/08,884.99,yes,locked 2006.173.13:16:58.67/vb/01,04,usb,yes,31,28 2006.173.13:16:58.67/vb/02,04,usb,yes,33,33 2006.173.13:16:58.67/vb/03,04,usb,yes,30,33 2006.173.13:16:58.67/vb/04,04,usb,yes,34,33 2006.173.13:16:58.67/vb/05,04,usb,yes,27,29 2006.173.13:16:58.67/vb/06,04,usb,yes,31,27 2006.173.13:16:58.67/vb/07,04,usb,yes,31,31 2006.173.13:16:58.67/vb/08,04,usb,yes,28,32 2006.173.13:16:58.90/vblo/01,629.99,yes,locked 2006.173.13:16:58.90/vblo/02,634.99,yes,locked 2006.173.13:16:58.90/vblo/03,649.99,yes,locked 2006.173.13:16:58.90/vblo/04,679.99,yes,locked 2006.173.13:16:58.90/vblo/05,709.99,yes,locked 2006.173.13:16:58.90/vblo/06,719.99,yes,locked 2006.173.13:16:58.90/vblo/07,734.99,yes,locked 2006.173.13:16:58.90/vblo/08,744.99,yes,locked 2006.173.13:16:59.05/vabw/8 2006.173.13:16:59.20/vbbw/8 2006.173.13:16:59.29/xfe/off,on,15.2 2006.173.13:16:59.69/ifatt/23,28,28,28 2006.173.13:17:00.08/fmout-gps/S +3.86E-07 2006.173.13:17:00.12:!2006.173.13:18:46 2006.173.13:18:46.01:data_valid=off 2006.173.13:18:46.01:"et 2006.173.13:18:46.02:!+3s 2006.173.13:18:49.03:"tape 2006.173.13:18:49.03:postob 2006.173.13:18:49.16/cable/+6.5051E-03 2006.173.13:18:49.16/wx/22.07,1004.2,98 2006.173.13:18:49.22/fmout-gps/S +3.84E-07 2006.173.13:18:49.22:scan_name=173-1320,jd0606,710 2006.173.13:18:49.23:source=1749+096,175132.82,093900.7,2000.0,cw 2006.173.13:18:50.14#flagr#flagr/antenna,new-source 2006.173.13:18:50.14:checkk5 2006.173.13:18:50.56/chk_autoobs//k5ts1/ autoobs is running! 2006.173.13:18:50.95/chk_autoobs//k5ts2/ autoobs is running! 2006.173.13:18:51.34/chk_autoobs//k5ts3/ autoobs is running! 2006.173.13:18:51.74/chk_autoobs//k5ts4/ autoobs is running! 2006.173.13:18:52.11/chk_obsdata//k5ts1/T1731316??a.dat file size is correct (nominal:440MB, actual:436MB). 2006.173.13:18:52.51/chk_obsdata//k5ts2/T1731316??b.dat file size is correct (nominal:440MB, actual:436MB). 2006.173.13:18:52.92/chk_obsdata//k5ts3/T1731316??c.dat file size is correct (nominal:440MB, actual:436MB). 2006.173.13:18:53.32/chk_obsdata//k5ts4/T1731316??d.dat file size is correct (nominal:440MB, actual:436MB). 2006.173.13:18:54.03/k5log//k5ts1_log_newline 2006.173.13:18:54.74/k5log//k5ts2_log_newline 2006.173.13:18:55.45/k5log//k5ts3_log_newline 2006.173.13:18:56.15/k5log//k5ts4_log_newline 2006.173.13:18:56.18/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.13:18:56.18:setupk4=1 2006.173.13:18:56.18$setupk4/echo=on 2006.173.13:18:56.18$setupk4/pcalon 2006.173.13:18:56.18$pcalon/"no phase cal control is implemented here 2006.173.13:18:56.18$setupk4/"tpicd=stop 2006.173.13:18:56.18$setupk4/"rec=synch_on 2006.173.13:18:56.18$setupk4/"rec_mode=128 2006.173.13:18:56.18$setupk4/!* 2006.173.13:18:56.18$setupk4/recpk4 2006.173.13:18:56.18$recpk4/recpatch= 2006.173.13:18:56.18$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.13:18:56.18$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.13:18:56.18$setupk4/vck44 2006.173.13:18:56.18$vck44/valo=1,524.99 2006.173.13:18:56.18#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.13:18:56.18#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.13:18:56.18#ibcon#ireg 17 cls_cnt 0 2006.173.13:18:56.18#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.13:18:56.18#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.13:18:56.18#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.13:18:56.18#ibcon#enter wrdev, iclass 37, count 0 2006.173.13:18:56.18#ibcon#first serial, iclass 37, count 0 2006.173.13:18:56.18#ibcon#enter sib2, iclass 37, count 0 2006.173.13:18:56.18#ibcon#flushed, iclass 37, count 0 2006.173.13:18:56.18#ibcon#about to write, iclass 37, count 0 2006.173.13:18:56.18#ibcon#wrote, iclass 37, count 0 2006.173.13:18:56.18#ibcon#about to read 3, iclass 37, count 0 2006.173.13:18:56.20#ibcon#read 3, iclass 37, count 0 2006.173.13:18:56.20#ibcon#about to read 4, iclass 37, count 0 2006.173.13:18:56.20#ibcon#read 4, iclass 37, count 0 2006.173.13:18:56.20#ibcon#about to read 5, iclass 37, count 0 2006.173.13:18:56.20#ibcon#read 5, iclass 37, count 0 2006.173.13:18:56.20#ibcon#about to read 6, iclass 37, count 0 2006.173.13:18:56.20#ibcon#read 6, iclass 37, count 0 2006.173.13:18:56.20#ibcon#end of sib2, iclass 37, count 0 2006.173.13:18:56.20#ibcon#*mode == 0, iclass 37, count 0 2006.173.13:18:56.20#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.13:18:56.20#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.13:18:56.20#ibcon#*before write, iclass 37, count 0 2006.173.13:18:56.20#ibcon#enter sib2, iclass 37, count 0 2006.173.13:18:56.20#ibcon#flushed, iclass 37, count 0 2006.173.13:18:56.20#ibcon#about to write, iclass 37, count 0 2006.173.13:18:56.20#ibcon#wrote, iclass 37, count 0 2006.173.13:18:56.20#ibcon#about to read 3, iclass 37, count 0 2006.173.13:18:56.25#ibcon#read 3, iclass 37, count 0 2006.173.13:18:56.25#ibcon#about to read 4, iclass 37, count 0 2006.173.13:18:56.25#ibcon#read 4, iclass 37, count 0 2006.173.13:18:56.25#ibcon#about to read 5, iclass 37, count 0 2006.173.13:18:56.25#ibcon#read 5, iclass 37, count 0 2006.173.13:18:56.25#ibcon#about to read 6, iclass 37, count 0 2006.173.13:18:56.25#ibcon#read 6, iclass 37, count 0 2006.173.13:18:56.25#ibcon#end of sib2, iclass 37, count 0 2006.173.13:18:56.25#ibcon#*after write, iclass 37, count 0 2006.173.13:18:56.25#ibcon#*before return 0, iclass 37, count 0 2006.173.13:18:56.25#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.13:18:56.25#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.13:18:56.25#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.13:18:56.25#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.13:18:56.25$vck44/va=1,7 2006.173.13:18:56.25#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.13:18:56.25#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.13:18:56.25#ibcon#ireg 11 cls_cnt 2 2006.173.13:18:56.25#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.13:18:56.25#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.13:18:56.25#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.13:18:56.25#ibcon#enter wrdev, iclass 39, count 2 2006.173.13:18:56.25#ibcon#first serial, iclass 39, count 2 2006.173.13:18:56.25#ibcon#enter sib2, iclass 39, count 2 2006.173.13:18:56.25#ibcon#flushed, iclass 39, count 2 2006.173.13:18:56.25#ibcon#about to write, iclass 39, count 2 2006.173.13:18:56.25#ibcon#wrote, iclass 39, count 2 2006.173.13:18:56.25#ibcon#about to read 3, iclass 39, count 2 2006.173.13:18:56.27#ibcon#read 3, iclass 39, count 2 2006.173.13:18:56.27#ibcon#about to read 4, iclass 39, count 2 2006.173.13:18:56.27#ibcon#read 4, iclass 39, count 2 2006.173.13:18:56.27#ibcon#about to read 5, iclass 39, count 2 2006.173.13:18:56.27#ibcon#read 5, iclass 39, count 2 2006.173.13:18:56.27#ibcon#about to read 6, iclass 39, count 2 2006.173.13:18:56.27#ibcon#read 6, iclass 39, count 2 2006.173.13:18:56.27#ibcon#end of sib2, iclass 39, count 2 2006.173.13:18:56.27#ibcon#*mode == 0, iclass 39, count 2 2006.173.13:18:56.27#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.13:18:56.27#ibcon#[25=AT01-07\r\n] 2006.173.13:18:56.27#ibcon#*before write, iclass 39, count 2 2006.173.13:18:56.27#ibcon#enter sib2, iclass 39, count 2 2006.173.13:18:56.27#ibcon#flushed, iclass 39, count 2 2006.173.13:18:56.27#ibcon#about to write, iclass 39, count 2 2006.173.13:18:56.27#ibcon#wrote, iclass 39, count 2 2006.173.13:18:56.27#ibcon#about to read 3, iclass 39, count 2 2006.173.13:18:56.30#ibcon#read 3, iclass 39, count 2 2006.173.13:18:56.30#ibcon#about to read 4, iclass 39, count 2 2006.173.13:18:56.30#ibcon#read 4, iclass 39, count 2 2006.173.13:18:56.30#ibcon#about to read 5, iclass 39, count 2 2006.173.13:18:56.30#ibcon#read 5, iclass 39, count 2 2006.173.13:18:56.30#ibcon#about to read 6, iclass 39, count 2 2006.173.13:18:56.30#ibcon#read 6, iclass 39, count 2 2006.173.13:18:56.30#ibcon#end of sib2, iclass 39, count 2 2006.173.13:18:56.30#ibcon#*after write, iclass 39, count 2 2006.173.13:18:56.30#ibcon#*before return 0, iclass 39, count 2 2006.173.13:18:56.30#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.13:18:56.30#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.13:18:56.30#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.13:18:56.30#ibcon#ireg 7 cls_cnt 0 2006.173.13:18:56.30#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.13:18:56.42#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.13:18:56.42#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.13:18:56.42#ibcon#enter wrdev, iclass 39, count 0 2006.173.13:18:56.42#ibcon#first serial, iclass 39, count 0 2006.173.13:18:56.42#ibcon#enter sib2, iclass 39, count 0 2006.173.13:18:56.42#ibcon#flushed, iclass 39, count 0 2006.173.13:18:56.42#ibcon#about to write, iclass 39, count 0 2006.173.13:18:56.42#ibcon#wrote, iclass 39, count 0 2006.173.13:18:56.42#ibcon#about to read 3, iclass 39, count 0 2006.173.13:18:56.44#ibcon#read 3, iclass 39, count 0 2006.173.13:18:56.44#ibcon#about to read 4, iclass 39, count 0 2006.173.13:18:56.44#ibcon#read 4, iclass 39, count 0 2006.173.13:18:56.44#ibcon#about to read 5, iclass 39, count 0 2006.173.13:18:56.44#ibcon#read 5, iclass 39, count 0 2006.173.13:18:56.44#ibcon#about to read 6, iclass 39, count 0 2006.173.13:18:56.44#ibcon#read 6, iclass 39, count 0 2006.173.13:18:56.44#ibcon#end of sib2, iclass 39, count 0 2006.173.13:18:56.44#ibcon#*mode == 0, iclass 39, count 0 2006.173.13:18:56.44#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.13:18:56.44#ibcon#[25=USB\r\n] 2006.173.13:18:56.44#ibcon#*before write, iclass 39, count 0 2006.173.13:18:56.44#ibcon#enter sib2, iclass 39, count 0 2006.173.13:18:56.44#ibcon#flushed, iclass 39, count 0 2006.173.13:18:56.44#ibcon#about to write, iclass 39, count 0 2006.173.13:18:56.44#ibcon#wrote, iclass 39, count 0 2006.173.13:18:56.44#ibcon#about to read 3, iclass 39, count 0 2006.173.13:18:56.47#ibcon#read 3, iclass 39, count 0 2006.173.13:18:56.47#ibcon#about to read 4, iclass 39, count 0 2006.173.13:18:56.47#ibcon#read 4, iclass 39, count 0 2006.173.13:18:56.47#ibcon#about to read 5, iclass 39, count 0 2006.173.13:18:56.47#ibcon#read 5, iclass 39, count 0 2006.173.13:18:56.47#ibcon#about to read 6, iclass 39, count 0 2006.173.13:18:56.47#ibcon#read 6, iclass 39, count 0 2006.173.13:18:56.47#ibcon#end of sib2, iclass 39, count 0 2006.173.13:18:56.47#ibcon#*after write, iclass 39, count 0 2006.173.13:18:56.47#ibcon#*before return 0, iclass 39, count 0 2006.173.13:18:56.47#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.13:18:56.47#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.13:18:56.47#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.13:18:56.47#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.13:18:56.47$vck44/valo=2,534.99 2006.173.13:18:56.47#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.13:18:56.47#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.13:18:56.47#ibcon#ireg 17 cls_cnt 0 2006.173.13:18:56.47#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.13:18:56.47#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.13:18:56.47#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.13:18:56.47#ibcon#enter wrdev, iclass 3, count 0 2006.173.13:18:56.47#ibcon#first serial, iclass 3, count 0 2006.173.13:18:56.47#ibcon#enter sib2, iclass 3, count 0 2006.173.13:18:56.47#ibcon#flushed, iclass 3, count 0 2006.173.13:18:56.47#ibcon#about to write, iclass 3, count 0 2006.173.13:18:56.47#ibcon#wrote, iclass 3, count 0 2006.173.13:18:56.47#ibcon#about to read 3, iclass 3, count 0 2006.173.13:18:56.49#ibcon#read 3, iclass 3, count 0 2006.173.13:18:56.49#ibcon#about to read 4, iclass 3, count 0 2006.173.13:18:56.49#ibcon#read 4, iclass 3, count 0 2006.173.13:18:56.49#ibcon#about to read 5, iclass 3, count 0 2006.173.13:18:56.49#ibcon#read 5, iclass 3, count 0 2006.173.13:18:56.49#ibcon#about to read 6, iclass 3, count 0 2006.173.13:18:56.49#ibcon#read 6, iclass 3, count 0 2006.173.13:18:56.49#ibcon#end of sib2, iclass 3, count 0 2006.173.13:18:56.49#ibcon#*mode == 0, iclass 3, count 0 2006.173.13:18:56.49#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.13:18:56.49#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.13:18:56.49#ibcon#*before write, iclass 3, count 0 2006.173.13:18:56.49#ibcon#enter sib2, iclass 3, count 0 2006.173.13:18:56.49#ibcon#flushed, iclass 3, count 0 2006.173.13:18:56.49#ibcon#about to write, iclass 3, count 0 2006.173.13:18:56.49#ibcon#wrote, iclass 3, count 0 2006.173.13:18:56.49#ibcon#about to read 3, iclass 3, count 0 2006.173.13:18:56.53#ibcon#read 3, iclass 3, count 0 2006.173.13:18:56.53#ibcon#about to read 4, iclass 3, count 0 2006.173.13:18:56.53#ibcon#read 4, iclass 3, count 0 2006.173.13:18:56.53#ibcon#about to read 5, iclass 3, count 0 2006.173.13:18:56.53#ibcon#read 5, iclass 3, count 0 2006.173.13:18:56.53#ibcon#about to read 6, iclass 3, count 0 2006.173.13:18:56.53#ibcon#read 6, iclass 3, count 0 2006.173.13:18:56.53#ibcon#end of sib2, iclass 3, count 0 2006.173.13:18:56.53#ibcon#*after write, iclass 3, count 0 2006.173.13:18:56.53#ibcon#*before return 0, iclass 3, count 0 2006.173.13:18:56.53#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.13:18:56.53#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.13:18:56.53#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.13:18:56.53#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.13:18:56.53$vck44/va=2,6 2006.173.13:18:56.53#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.13:18:56.53#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.13:18:56.53#ibcon#ireg 11 cls_cnt 2 2006.173.13:18:56.53#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.13:18:56.59#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.13:18:56.59#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.13:18:56.59#ibcon#enter wrdev, iclass 5, count 2 2006.173.13:18:56.59#ibcon#first serial, iclass 5, count 2 2006.173.13:18:56.59#ibcon#enter sib2, iclass 5, count 2 2006.173.13:18:56.59#ibcon#flushed, iclass 5, count 2 2006.173.13:18:56.59#ibcon#about to write, iclass 5, count 2 2006.173.13:18:56.59#ibcon#wrote, iclass 5, count 2 2006.173.13:18:56.59#ibcon#about to read 3, iclass 5, count 2 2006.173.13:18:56.61#ibcon#read 3, iclass 5, count 2 2006.173.13:18:56.61#ibcon#about to read 4, iclass 5, count 2 2006.173.13:18:56.61#ibcon#read 4, iclass 5, count 2 2006.173.13:18:56.61#ibcon#about to read 5, iclass 5, count 2 2006.173.13:18:56.61#ibcon#read 5, iclass 5, count 2 2006.173.13:18:56.61#ibcon#about to read 6, iclass 5, count 2 2006.173.13:18:56.61#ibcon#read 6, iclass 5, count 2 2006.173.13:18:56.61#ibcon#end of sib2, iclass 5, count 2 2006.173.13:18:56.61#ibcon#*mode == 0, iclass 5, count 2 2006.173.13:18:56.61#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.13:18:56.61#ibcon#[25=AT02-06\r\n] 2006.173.13:18:56.61#ibcon#*before write, iclass 5, count 2 2006.173.13:18:56.61#ibcon#enter sib2, iclass 5, count 2 2006.173.13:18:56.61#ibcon#flushed, iclass 5, count 2 2006.173.13:18:56.61#ibcon#about to write, iclass 5, count 2 2006.173.13:18:56.61#ibcon#wrote, iclass 5, count 2 2006.173.13:18:56.61#ibcon#about to read 3, iclass 5, count 2 2006.173.13:18:56.64#ibcon#read 3, iclass 5, count 2 2006.173.13:18:56.64#ibcon#about to read 4, iclass 5, count 2 2006.173.13:18:56.64#ibcon#read 4, iclass 5, count 2 2006.173.13:18:56.64#ibcon#about to read 5, iclass 5, count 2 2006.173.13:18:56.64#ibcon#read 5, iclass 5, count 2 2006.173.13:18:56.64#ibcon#about to read 6, iclass 5, count 2 2006.173.13:18:56.64#ibcon#read 6, iclass 5, count 2 2006.173.13:18:56.64#ibcon#end of sib2, iclass 5, count 2 2006.173.13:18:56.64#ibcon#*after write, iclass 5, count 2 2006.173.13:18:56.64#ibcon#*before return 0, iclass 5, count 2 2006.173.13:18:56.64#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.13:18:56.64#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.13:18:56.64#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.13:18:56.64#ibcon#ireg 7 cls_cnt 0 2006.173.13:18:56.64#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.13:18:56.76#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.13:18:56.76#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.13:18:56.76#ibcon#enter wrdev, iclass 5, count 0 2006.173.13:18:56.76#ibcon#first serial, iclass 5, count 0 2006.173.13:18:56.76#ibcon#enter sib2, iclass 5, count 0 2006.173.13:18:56.76#ibcon#flushed, iclass 5, count 0 2006.173.13:18:56.76#ibcon#about to write, iclass 5, count 0 2006.173.13:18:56.76#ibcon#wrote, iclass 5, count 0 2006.173.13:18:56.76#ibcon#about to read 3, iclass 5, count 0 2006.173.13:18:56.78#ibcon#read 3, iclass 5, count 0 2006.173.13:18:56.78#ibcon#about to read 4, iclass 5, count 0 2006.173.13:18:56.78#ibcon#read 4, iclass 5, count 0 2006.173.13:18:56.78#ibcon#about to read 5, iclass 5, count 0 2006.173.13:18:56.78#ibcon#read 5, iclass 5, count 0 2006.173.13:18:56.78#ibcon#about to read 6, iclass 5, count 0 2006.173.13:18:56.78#ibcon#read 6, iclass 5, count 0 2006.173.13:18:56.78#ibcon#end of sib2, iclass 5, count 0 2006.173.13:18:56.78#ibcon#*mode == 0, iclass 5, count 0 2006.173.13:18:56.78#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.13:18:56.78#ibcon#[25=USB\r\n] 2006.173.13:18:56.78#ibcon#*before write, iclass 5, count 0 2006.173.13:18:56.78#ibcon#enter sib2, iclass 5, count 0 2006.173.13:18:56.78#ibcon#flushed, iclass 5, count 0 2006.173.13:18:56.78#ibcon#about to write, iclass 5, count 0 2006.173.13:18:56.78#ibcon#wrote, iclass 5, count 0 2006.173.13:18:56.78#ibcon#about to read 3, iclass 5, count 0 2006.173.13:18:56.81#ibcon#read 3, iclass 5, count 0 2006.173.13:18:56.81#ibcon#about to read 4, iclass 5, count 0 2006.173.13:18:56.81#ibcon#read 4, iclass 5, count 0 2006.173.13:18:56.81#ibcon#about to read 5, iclass 5, count 0 2006.173.13:18:56.81#ibcon#read 5, iclass 5, count 0 2006.173.13:18:56.81#ibcon#about to read 6, iclass 5, count 0 2006.173.13:18:56.81#ibcon#read 6, iclass 5, count 0 2006.173.13:18:56.81#ibcon#end of sib2, iclass 5, count 0 2006.173.13:18:56.81#ibcon#*after write, iclass 5, count 0 2006.173.13:18:56.81#ibcon#*before return 0, iclass 5, count 0 2006.173.13:18:56.81#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.13:18:56.81#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.13:18:56.81#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.13:18:56.81#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.13:18:56.81$vck44/valo=3,564.99 2006.173.13:18:56.81#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.13:18:56.81#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.13:18:56.81#ibcon#ireg 17 cls_cnt 0 2006.173.13:18:56.81#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.13:18:56.81#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.13:18:56.81#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.13:18:56.81#ibcon#enter wrdev, iclass 7, count 0 2006.173.13:18:56.81#ibcon#first serial, iclass 7, count 0 2006.173.13:18:56.81#ibcon#enter sib2, iclass 7, count 0 2006.173.13:18:56.81#ibcon#flushed, iclass 7, count 0 2006.173.13:18:56.81#ibcon#about to write, iclass 7, count 0 2006.173.13:18:56.81#ibcon#wrote, iclass 7, count 0 2006.173.13:18:56.81#ibcon#about to read 3, iclass 7, count 0 2006.173.13:18:56.83#ibcon#read 3, iclass 7, count 0 2006.173.13:18:56.83#ibcon#about to read 4, iclass 7, count 0 2006.173.13:18:56.83#ibcon#read 4, iclass 7, count 0 2006.173.13:18:56.83#ibcon#about to read 5, iclass 7, count 0 2006.173.13:18:56.83#ibcon#read 5, iclass 7, count 0 2006.173.13:18:56.83#ibcon#about to read 6, iclass 7, count 0 2006.173.13:18:56.83#ibcon#read 6, iclass 7, count 0 2006.173.13:18:56.83#ibcon#end of sib2, iclass 7, count 0 2006.173.13:18:56.83#ibcon#*mode == 0, iclass 7, count 0 2006.173.13:18:56.83#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.13:18:56.83#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.13:18:56.83#ibcon#*before write, iclass 7, count 0 2006.173.13:18:56.83#ibcon#enter sib2, iclass 7, count 0 2006.173.13:18:56.83#ibcon#flushed, iclass 7, count 0 2006.173.13:18:56.83#ibcon#about to write, iclass 7, count 0 2006.173.13:18:56.83#ibcon#wrote, iclass 7, count 0 2006.173.13:18:56.83#ibcon#about to read 3, iclass 7, count 0 2006.173.13:18:56.87#ibcon#read 3, iclass 7, count 0 2006.173.13:18:56.87#ibcon#about to read 4, iclass 7, count 0 2006.173.13:18:56.87#ibcon#read 4, iclass 7, count 0 2006.173.13:18:56.87#ibcon#about to read 5, iclass 7, count 0 2006.173.13:18:56.87#ibcon#read 5, iclass 7, count 0 2006.173.13:18:56.87#ibcon#about to read 6, iclass 7, count 0 2006.173.13:18:56.87#ibcon#read 6, iclass 7, count 0 2006.173.13:18:56.87#ibcon#end of sib2, iclass 7, count 0 2006.173.13:18:56.87#ibcon#*after write, iclass 7, count 0 2006.173.13:18:56.87#ibcon#*before return 0, iclass 7, count 0 2006.173.13:18:56.87#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.13:18:56.87#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.13:18:56.87#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.13:18:56.87#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.13:18:56.87$vck44/va=3,5 2006.173.13:18:56.87#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.13:18:56.87#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.13:18:56.87#ibcon#ireg 11 cls_cnt 2 2006.173.13:18:56.87#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.13:18:56.93#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.13:18:56.93#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.13:18:56.93#ibcon#enter wrdev, iclass 11, count 2 2006.173.13:18:56.93#ibcon#first serial, iclass 11, count 2 2006.173.13:18:56.93#ibcon#enter sib2, iclass 11, count 2 2006.173.13:18:56.93#ibcon#flushed, iclass 11, count 2 2006.173.13:18:56.93#ibcon#about to write, iclass 11, count 2 2006.173.13:18:56.93#ibcon#wrote, iclass 11, count 2 2006.173.13:18:56.93#ibcon#about to read 3, iclass 11, count 2 2006.173.13:18:56.95#ibcon#read 3, iclass 11, count 2 2006.173.13:18:56.95#ibcon#about to read 4, iclass 11, count 2 2006.173.13:18:56.95#ibcon#read 4, iclass 11, count 2 2006.173.13:18:56.95#ibcon#about to read 5, iclass 11, count 2 2006.173.13:18:56.95#ibcon#read 5, iclass 11, count 2 2006.173.13:18:56.95#ibcon#about to read 6, iclass 11, count 2 2006.173.13:18:56.95#ibcon#read 6, iclass 11, count 2 2006.173.13:18:56.95#ibcon#end of sib2, iclass 11, count 2 2006.173.13:18:56.95#ibcon#*mode == 0, iclass 11, count 2 2006.173.13:18:56.95#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.13:18:56.95#ibcon#[25=AT03-05\r\n] 2006.173.13:18:56.95#ibcon#*before write, iclass 11, count 2 2006.173.13:18:56.95#ibcon#enter sib2, iclass 11, count 2 2006.173.13:18:56.95#ibcon#flushed, iclass 11, count 2 2006.173.13:18:56.95#ibcon#about to write, iclass 11, count 2 2006.173.13:18:56.95#ibcon#wrote, iclass 11, count 2 2006.173.13:18:56.95#ibcon#about to read 3, iclass 11, count 2 2006.173.13:18:56.98#ibcon#read 3, iclass 11, count 2 2006.173.13:18:56.98#ibcon#about to read 4, iclass 11, count 2 2006.173.13:18:56.98#ibcon#read 4, iclass 11, count 2 2006.173.13:18:56.98#ibcon#about to read 5, iclass 11, count 2 2006.173.13:18:56.98#ibcon#read 5, iclass 11, count 2 2006.173.13:18:56.98#ibcon#about to read 6, iclass 11, count 2 2006.173.13:18:56.98#ibcon#read 6, iclass 11, count 2 2006.173.13:18:56.98#ibcon#end of sib2, iclass 11, count 2 2006.173.13:18:56.98#ibcon#*after write, iclass 11, count 2 2006.173.13:18:56.98#ibcon#*before return 0, iclass 11, count 2 2006.173.13:18:56.98#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.13:18:56.98#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.13:18:56.98#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.13:18:56.98#ibcon#ireg 7 cls_cnt 0 2006.173.13:18:56.98#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.13:18:57.10#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.13:18:57.10#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.13:18:57.10#ibcon#enter wrdev, iclass 11, count 0 2006.173.13:18:57.10#ibcon#first serial, iclass 11, count 0 2006.173.13:18:57.10#ibcon#enter sib2, iclass 11, count 0 2006.173.13:18:57.10#ibcon#flushed, iclass 11, count 0 2006.173.13:18:57.10#ibcon#about to write, iclass 11, count 0 2006.173.13:18:57.10#ibcon#wrote, iclass 11, count 0 2006.173.13:18:57.10#ibcon#about to read 3, iclass 11, count 0 2006.173.13:18:57.12#ibcon#read 3, iclass 11, count 0 2006.173.13:18:57.12#ibcon#about to read 4, iclass 11, count 0 2006.173.13:18:57.12#ibcon#read 4, iclass 11, count 0 2006.173.13:18:57.12#ibcon#about to read 5, iclass 11, count 0 2006.173.13:18:57.12#ibcon#read 5, iclass 11, count 0 2006.173.13:18:57.12#ibcon#about to read 6, iclass 11, count 0 2006.173.13:18:57.12#ibcon#read 6, iclass 11, count 0 2006.173.13:18:57.12#ibcon#end of sib2, iclass 11, count 0 2006.173.13:18:57.12#ibcon#*mode == 0, iclass 11, count 0 2006.173.13:18:57.12#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.13:18:57.12#ibcon#[25=USB\r\n] 2006.173.13:18:57.12#ibcon#*before write, iclass 11, count 0 2006.173.13:18:57.12#ibcon#enter sib2, iclass 11, count 0 2006.173.13:18:57.12#ibcon#flushed, iclass 11, count 0 2006.173.13:18:57.12#ibcon#about to write, iclass 11, count 0 2006.173.13:18:57.12#ibcon#wrote, iclass 11, count 0 2006.173.13:18:57.12#ibcon#about to read 3, iclass 11, count 0 2006.173.13:18:57.15#ibcon#read 3, iclass 11, count 0 2006.173.13:18:57.15#ibcon#about to read 4, iclass 11, count 0 2006.173.13:18:57.15#ibcon#read 4, iclass 11, count 0 2006.173.13:18:57.15#ibcon#about to read 5, iclass 11, count 0 2006.173.13:18:57.15#ibcon#read 5, iclass 11, count 0 2006.173.13:18:57.15#ibcon#about to read 6, iclass 11, count 0 2006.173.13:18:57.15#ibcon#read 6, iclass 11, count 0 2006.173.13:18:57.15#ibcon#end of sib2, iclass 11, count 0 2006.173.13:18:57.15#ibcon#*after write, iclass 11, count 0 2006.173.13:18:57.15#ibcon#*before return 0, iclass 11, count 0 2006.173.13:18:57.15#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.13:18:57.15#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.13:18:57.15#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.13:18:57.15#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.13:18:57.15$vck44/valo=4,624.99 2006.173.13:18:57.15#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.13:18:57.15#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.13:18:57.15#ibcon#ireg 17 cls_cnt 0 2006.173.13:18:57.15#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.13:18:57.15#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.13:18:57.15#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.13:18:57.15#ibcon#enter wrdev, iclass 13, count 0 2006.173.13:18:57.15#ibcon#first serial, iclass 13, count 0 2006.173.13:18:57.15#ibcon#enter sib2, iclass 13, count 0 2006.173.13:18:57.15#ibcon#flushed, iclass 13, count 0 2006.173.13:18:57.15#ibcon#about to write, iclass 13, count 0 2006.173.13:18:57.15#ibcon#wrote, iclass 13, count 0 2006.173.13:18:57.15#ibcon#about to read 3, iclass 13, count 0 2006.173.13:18:57.17#ibcon#read 3, iclass 13, count 0 2006.173.13:18:57.17#ibcon#about to read 4, iclass 13, count 0 2006.173.13:18:57.17#ibcon#read 4, iclass 13, count 0 2006.173.13:18:57.17#ibcon#about to read 5, iclass 13, count 0 2006.173.13:18:57.17#ibcon#read 5, iclass 13, count 0 2006.173.13:18:57.17#ibcon#about to read 6, iclass 13, count 0 2006.173.13:18:57.17#ibcon#read 6, iclass 13, count 0 2006.173.13:18:57.17#ibcon#end of sib2, iclass 13, count 0 2006.173.13:18:57.17#ibcon#*mode == 0, iclass 13, count 0 2006.173.13:18:57.17#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.13:18:57.17#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.13:18:57.17#ibcon#*before write, iclass 13, count 0 2006.173.13:18:57.17#ibcon#enter sib2, iclass 13, count 0 2006.173.13:18:57.17#ibcon#flushed, iclass 13, count 0 2006.173.13:18:57.17#ibcon#about to write, iclass 13, count 0 2006.173.13:18:57.17#ibcon#wrote, iclass 13, count 0 2006.173.13:18:57.17#ibcon#about to read 3, iclass 13, count 0 2006.173.13:18:57.21#ibcon#read 3, iclass 13, count 0 2006.173.13:18:57.21#ibcon#about to read 4, iclass 13, count 0 2006.173.13:18:57.21#ibcon#read 4, iclass 13, count 0 2006.173.13:18:57.21#ibcon#about to read 5, iclass 13, count 0 2006.173.13:18:57.21#ibcon#read 5, iclass 13, count 0 2006.173.13:18:57.21#ibcon#about to read 6, iclass 13, count 0 2006.173.13:18:57.21#ibcon#read 6, iclass 13, count 0 2006.173.13:18:57.21#ibcon#end of sib2, iclass 13, count 0 2006.173.13:18:57.21#ibcon#*after write, iclass 13, count 0 2006.173.13:18:57.21#ibcon#*before return 0, iclass 13, count 0 2006.173.13:18:57.21#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.13:18:57.21#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.13:18:57.21#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.13:18:57.21#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.13:18:57.21$vck44/va=4,6 2006.173.13:18:57.21#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.13:18:57.21#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.13:18:57.21#ibcon#ireg 11 cls_cnt 2 2006.173.13:18:57.21#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.13:18:57.27#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.13:18:57.27#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.13:18:57.27#ibcon#enter wrdev, iclass 15, count 2 2006.173.13:18:57.27#ibcon#first serial, iclass 15, count 2 2006.173.13:18:57.27#ibcon#enter sib2, iclass 15, count 2 2006.173.13:18:57.27#ibcon#flushed, iclass 15, count 2 2006.173.13:18:57.27#ibcon#about to write, iclass 15, count 2 2006.173.13:18:57.27#ibcon#wrote, iclass 15, count 2 2006.173.13:18:57.27#ibcon#about to read 3, iclass 15, count 2 2006.173.13:18:57.29#ibcon#read 3, iclass 15, count 2 2006.173.13:18:57.29#ibcon#about to read 4, iclass 15, count 2 2006.173.13:18:57.29#ibcon#read 4, iclass 15, count 2 2006.173.13:18:57.29#ibcon#about to read 5, iclass 15, count 2 2006.173.13:18:57.29#ibcon#read 5, iclass 15, count 2 2006.173.13:18:57.29#ibcon#about to read 6, iclass 15, count 2 2006.173.13:18:57.29#ibcon#read 6, iclass 15, count 2 2006.173.13:18:57.29#ibcon#end of sib2, iclass 15, count 2 2006.173.13:18:57.29#ibcon#*mode == 0, iclass 15, count 2 2006.173.13:18:57.29#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.13:18:57.29#ibcon#[25=AT04-06\r\n] 2006.173.13:18:57.29#ibcon#*before write, iclass 15, count 2 2006.173.13:18:57.29#ibcon#enter sib2, iclass 15, count 2 2006.173.13:18:57.29#ibcon#flushed, iclass 15, count 2 2006.173.13:18:57.29#ibcon#about to write, iclass 15, count 2 2006.173.13:18:57.29#ibcon#wrote, iclass 15, count 2 2006.173.13:18:57.29#ibcon#about to read 3, iclass 15, count 2 2006.173.13:18:57.32#ibcon#read 3, iclass 15, count 2 2006.173.13:18:57.32#ibcon#about to read 4, iclass 15, count 2 2006.173.13:18:57.32#ibcon#read 4, iclass 15, count 2 2006.173.13:18:57.32#ibcon#about to read 5, iclass 15, count 2 2006.173.13:18:57.32#ibcon#read 5, iclass 15, count 2 2006.173.13:18:57.32#ibcon#about to read 6, iclass 15, count 2 2006.173.13:18:57.32#ibcon#read 6, iclass 15, count 2 2006.173.13:18:57.32#ibcon#end of sib2, iclass 15, count 2 2006.173.13:18:57.32#ibcon#*after write, iclass 15, count 2 2006.173.13:18:57.32#ibcon#*before return 0, iclass 15, count 2 2006.173.13:18:57.32#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.13:18:57.32#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.13:18:57.32#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.13:18:57.32#ibcon#ireg 7 cls_cnt 0 2006.173.13:18:57.32#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.13:18:57.33#abcon#<5=/06 0.3 0.7 22.07 981004.1\r\n> 2006.173.13:18:57.35#abcon#{5=INTERFACE CLEAR} 2006.173.13:18:57.41#abcon#[5=S1D000X0/0*\r\n] 2006.173.13:18:57.44#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.13:18:57.44#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.13:18:57.44#ibcon#enter wrdev, iclass 15, count 0 2006.173.13:18:57.44#ibcon#first serial, iclass 15, count 0 2006.173.13:18:57.44#ibcon#enter sib2, iclass 15, count 0 2006.173.13:18:57.44#ibcon#flushed, iclass 15, count 0 2006.173.13:18:57.44#ibcon#about to write, iclass 15, count 0 2006.173.13:18:57.44#ibcon#wrote, iclass 15, count 0 2006.173.13:18:57.44#ibcon#about to read 3, iclass 15, count 0 2006.173.13:18:57.46#ibcon#read 3, iclass 15, count 0 2006.173.13:18:57.46#ibcon#about to read 4, iclass 15, count 0 2006.173.13:18:57.46#ibcon#read 4, iclass 15, count 0 2006.173.13:18:57.46#ibcon#about to read 5, iclass 15, count 0 2006.173.13:18:57.46#ibcon#read 5, iclass 15, count 0 2006.173.13:18:57.46#ibcon#about to read 6, iclass 15, count 0 2006.173.13:18:57.46#ibcon#read 6, iclass 15, count 0 2006.173.13:18:57.46#ibcon#end of sib2, iclass 15, count 0 2006.173.13:18:57.46#ibcon#*mode == 0, iclass 15, count 0 2006.173.13:18:57.46#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.13:18:57.46#ibcon#[25=USB\r\n] 2006.173.13:18:57.46#ibcon#*before write, iclass 15, count 0 2006.173.13:18:57.46#ibcon#enter sib2, iclass 15, count 0 2006.173.13:18:57.46#ibcon#flushed, iclass 15, count 0 2006.173.13:18:57.46#ibcon#about to write, iclass 15, count 0 2006.173.13:18:57.46#ibcon#wrote, iclass 15, count 0 2006.173.13:18:57.46#ibcon#about to read 3, iclass 15, count 0 2006.173.13:18:57.49#ibcon#read 3, iclass 15, count 0 2006.173.13:18:57.49#ibcon#about to read 4, iclass 15, count 0 2006.173.13:18:57.49#ibcon#read 4, iclass 15, count 0 2006.173.13:18:57.49#ibcon#about to read 5, iclass 15, count 0 2006.173.13:18:57.49#ibcon#read 5, iclass 15, count 0 2006.173.13:18:57.49#ibcon#about to read 6, iclass 15, count 0 2006.173.13:18:57.49#ibcon#read 6, iclass 15, count 0 2006.173.13:18:57.49#ibcon#end of sib2, iclass 15, count 0 2006.173.13:18:57.49#ibcon#*after write, iclass 15, count 0 2006.173.13:18:57.49#ibcon#*before return 0, iclass 15, count 0 2006.173.13:18:57.49#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.13:18:57.49#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.13:18:57.49#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.13:18:57.49#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.13:18:57.49$vck44/valo=5,734.99 2006.173.13:18:57.49#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.13:18:57.49#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.13:18:57.49#ibcon#ireg 17 cls_cnt 0 2006.173.13:18:57.49#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.13:18:57.49#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.13:18:57.49#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.13:18:57.49#ibcon#enter wrdev, iclass 21, count 0 2006.173.13:18:57.49#ibcon#first serial, iclass 21, count 0 2006.173.13:18:57.49#ibcon#enter sib2, iclass 21, count 0 2006.173.13:18:57.49#ibcon#flushed, iclass 21, count 0 2006.173.13:18:57.49#ibcon#about to write, iclass 21, count 0 2006.173.13:18:57.49#ibcon#wrote, iclass 21, count 0 2006.173.13:18:57.49#ibcon#about to read 3, iclass 21, count 0 2006.173.13:18:57.51#ibcon#read 3, iclass 21, count 0 2006.173.13:18:57.51#ibcon#about to read 4, iclass 21, count 0 2006.173.13:18:57.51#ibcon#read 4, iclass 21, count 0 2006.173.13:18:57.51#ibcon#about to read 5, iclass 21, count 0 2006.173.13:18:57.51#ibcon#read 5, iclass 21, count 0 2006.173.13:18:57.51#ibcon#about to read 6, iclass 21, count 0 2006.173.13:18:57.51#ibcon#read 6, iclass 21, count 0 2006.173.13:18:57.51#ibcon#end of sib2, iclass 21, count 0 2006.173.13:18:57.51#ibcon#*mode == 0, iclass 21, count 0 2006.173.13:18:57.51#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.13:18:57.51#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.13:18:57.51#ibcon#*before write, iclass 21, count 0 2006.173.13:18:57.51#ibcon#enter sib2, iclass 21, count 0 2006.173.13:18:57.51#ibcon#flushed, iclass 21, count 0 2006.173.13:18:57.51#ibcon#about to write, iclass 21, count 0 2006.173.13:18:57.51#ibcon#wrote, iclass 21, count 0 2006.173.13:18:57.51#ibcon#about to read 3, iclass 21, count 0 2006.173.13:18:57.55#ibcon#read 3, iclass 21, count 0 2006.173.13:18:57.55#ibcon#about to read 4, iclass 21, count 0 2006.173.13:18:57.55#ibcon#read 4, iclass 21, count 0 2006.173.13:18:57.55#ibcon#about to read 5, iclass 21, count 0 2006.173.13:18:57.55#ibcon#read 5, iclass 21, count 0 2006.173.13:18:57.55#ibcon#about to read 6, iclass 21, count 0 2006.173.13:18:57.55#ibcon#read 6, iclass 21, count 0 2006.173.13:18:57.55#ibcon#end of sib2, iclass 21, count 0 2006.173.13:18:57.55#ibcon#*after write, iclass 21, count 0 2006.173.13:18:57.55#ibcon#*before return 0, iclass 21, count 0 2006.173.13:18:57.55#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.13:18:57.55#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.13:18:57.55#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.13:18:57.55#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.13:18:57.55$vck44/va=5,4 2006.173.13:18:57.55#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.13:18:57.55#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.13:18:57.55#ibcon#ireg 11 cls_cnt 2 2006.173.13:18:57.55#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.13:18:57.61#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.13:18:57.61#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.13:18:57.61#ibcon#enter wrdev, iclass 23, count 2 2006.173.13:18:57.61#ibcon#first serial, iclass 23, count 2 2006.173.13:18:57.61#ibcon#enter sib2, iclass 23, count 2 2006.173.13:18:57.61#ibcon#flushed, iclass 23, count 2 2006.173.13:18:57.61#ibcon#about to write, iclass 23, count 2 2006.173.13:18:57.61#ibcon#wrote, iclass 23, count 2 2006.173.13:18:57.61#ibcon#about to read 3, iclass 23, count 2 2006.173.13:18:57.63#ibcon#read 3, iclass 23, count 2 2006.173.13:18:57.63#ibcon#about to read 4, iclass 23, count 2 2006.173.13:18:57.63#ibcon#read 4, iclass 23, count 2 2006.173.13:18:57.63#ibcon#about to read 5, iclass 23, count 2 2006.173.13:18:57.63#ibcon#read 5, iclass 23, count 2 2006.173.13:18:57.63#ibcon#about to read 6, iclass 23, count 2 2006.173.13:18:57.63#ibcon#read 6, iclass 23, count 2 2006.173.13:18:57.63#ibcon#end of sib2, iclass 23, count 2 2006.173.13:18:57.63#ibcon#*mode == 0, iclass 23, count 2 2006.173.13:18:57.63#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.13:18:57.63#ibcon#[25=AT05-04\r\n] 2006.173.13:18:57.63#ibcon#*before write, iclass 23, count 2 2006.173.13:18:57.63#ibcon#enter sib2, iclass 23, count 2 2006.173.13:18:57.63#ibcon#flushed, iclass 23, count 2 2006.173.13:18:57.63#ibcon#about to write, iclass 23, count 2 2006.173.13:18:57.63#ibcon#wrote, iclass 23, count 2 2006.173.13:18:57.63#ibcon#about to read 3, iclass 23, count 2 2006.173.13:18:57.66#ibcon#read 3, iclass 23, count 2 2006.173.13:18:57.66#ibcon#about to read 4, iclass 23, count 2 2006.173.13:18:57.66#ibcon#read 4, iclass 23, count 2 2006.173.13:18:57.66#ibcon#about to read 5, iclass 23, count 2 2006.173.13:18:57.66#ibcon#read 5, iclass 23, count 2 2006.173.13:18:57.66#ibcon#about to read 6, iclass 23, count 2 2006.173.13:18:57.66#ibcon#read 6, iclass 23, count 2 2006.173.13:18:57.66#ibcon#end of sib2, iclass 23, count 2 2006.173.13:18:57.66#ibcon#*after write, iclass 23, count 2 2006.173.13:18:57.66#ibcon#*before return 0, iclass 23, count 2 2006.173.13:18:57.66#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.13:18:57.66#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.13:18:57.66#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.13:18:57.66#ibcon#ireg 7 cls_cnt 0 2006.173.13:18:57.66#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.13:18:57.78#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.13:18:57.78#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.13:18:57.78#ibcon#enter wrdev, iclass 23, count 0 2006.173.13:18:57.78#ibcon#first serial, iclass 23, count 0 2006.173.13:18:57.78#ibcon#enter sib2, iclass 23, count 0 2006.173.13:18:57.78#ibcon#flushed, iclass 23, count 0 2006.173.13:18:57.78#ibcon#about to write, iclass 23, count 0 2006.173.13:18:57.78#ibcon#wrote, iclass 23, count 0 2006.173.13:18:57.78#ibcon#about to read 3, iclass 23, count 0 2006.173.13:18:57.80#ibcon#read 3, iclass 23, count 0 2006.173.13:18:57.80#ibcon#about to read 4, iclass 23, count 0 2006.173.13:18:57.80#ibcon#read 4, iclass 23, count 0 2006.173.13:18:57.80#ibcon#about to read 5, iclass 23, count 0 2006.173.13:18:57.80#ibcon#read 5, iclass 23, count 0 2006.173.13:18:57.80#ibcon#about to read 6, iclass 23, count 0 2006.173.13:18:57.80#ibcon#read 6, iclass 23, count 0 2006.173.13:18:57.80#ibcon#end of sib2, iclass 23, count 0 2006.173.13:18:57.80#ibcon#*mode == 0, iclass 23, count 0 2006.173.13:18:57.80#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.13:18:57.80#ibcon#[25=USB\r\n] 2006.173.13:18:57.80#ibcon#*before write, iclass 23, count 0 2006.173.13:18:57.80#ibcon#enter sib2, iclass 23, count 0 2006.173.13:18:57.80#ibcon#flushed, iclass 23, count 0 2006.173.13:18:57.80#ibcon#about to write, iclass 23, count 0 2006.173.13:18:57.80#ibcon#wrote, iclass 23, count 0 2006.173.13:18:57.80#ibcon#about to read 3, iclass 23, count 0 2006.173.13:18:57.83#ibcon#read 3, iclass 23, count 0 2006.173.13:18:57.83#ibcon#about to read 4, iclass 23, count 0 2006.173.13:18:57.83#ibcon#read 4, iclass 23, count 0 2006.173.13:18:57.83#ibcon#about to read 5, iclass 23, count 0 2006.173.13:18:57.83#ibcon#read 5, iclass 23, count 0 2006.173.13:18:57.83#ibcon#about to read 6, iclass 23, count 0 2006.173.13:18:57.83#ibcon#read 6, iclass 23, count 0 2006.173.13:18:57.83#ibcon#end of sib2, iclass 23, count 0 2006.173.13:18:57.83#ibcon#*after write, iclass 23, count 0 2006.173.13:18:57.83#ibcon#*before return 0, iclass 23, count 0 2006.173.13:18:57.83#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.13:18:57.83#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.13:18:57.83#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.13:18:57.83#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.13:18:57.83$vck44/valo=6,814.99 2006.173.13:18:57.83#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.13:18:57.83#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.13:18:57.83#ibcon#ireg 17 cls_cnt 0 2006.173.13:18:57.83#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.13:18:57.83#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.13:18:57.83#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.13:18:57.83#ibcon#enter wrdev, iclass 25, count 0 2006.173.13:18:57.83#ibcon#first serial, iclass 25, count 0 2006.173.13:18:57.83#ibcon#enter sib2, iclass 25, count 0 2006.173.13:18:57.83#ibcon#flushed, iclass 25, count 0 2006.173.13:18:57.83#ibcon#about to write, iclass 25, count 0 2006.173.13:18:57.83#ibcon#wrote, iclass 25, count 0 2006.173.13:18:57.83#ibcon#about to read 3, iclass 25, count 0 2006.173.13:18:57.85#ibcon#read 3, iclass 25, count 0 2006.173.13:18:57.85#ibcon#about to read 4, iclass 25, count 0 2006.173.13:18:57.85#ibcon#read 4, iclass 25, count 0 2006.173.13:18:57.85#ibcon#about to read 5, iclass 25, count 0 2006.173.13:18:57.85#ibcon#read 5, iclass 25, count 0 2006.173.13:18:57.85#ibcon#about to read 6, iclass 25, count 0 2006.173.13:18:57.85#ibcon#read 6, iclass 25, count 0 2006.173.13:18:57.85#ibcon#end of sib2, iclass 25, count 0 2006.173.13:18:57.85#ibcon#*mode == 0, iclass 25, count 0 2006.173.13:18:57.85#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.13:18:57.85#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.13:18:57.85#ibcon#*before write, iclass 25, count 0 2006.173.13:18:57.85#ibcon#enter sib2, iclass 25, count 0 2006.173.13:18:57.85#ibcon#flushed, iclass 25, count 0 2006.173.13:18:57.85#ibcon#about to write, iclass 25, count 0 2006.173.13:18:57.85#ibcon#wrote, iclass 25, count 0 2006.173.13:18:57.85#ibcon#about to read 3, iclass 25, count 0 2006.173.13:18:57.89#ibcon#read 3, iclass 25, count 0 2006.173.13:18:57.89#ibcon#about to read 4, iclass 25, count 0 2006.173.13:18:57.89#ibcon#read 4, iclass 25, count 0 2006.173.13:18:57.89#ibcon#about to read 5, iclass 25, count 0 2006.173.13:18:57.89#ibcon#read 5, iclass 25, count 0 2006.173.13:18:57.89#ibcon#about to read 6, iclass 25, count 0 2006.173.13:18:57.89#ibcon#read 6, iclass 25, count 0 2006.173.13:18:57.89#ibcon#end of sib2, iclass 25, count 0 2006.173.13:18:57.89#ibcon#*after write, iclass 25, count 0 2006.173.13:18:57.89#ibcon#*before return 0, iclass 25, count 0 2006.173.13:18:57.89#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.13:18:57.89#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.13:18:57.89#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.13:18:57.89#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.13:18:57.89$vck44/va=6,3 2006.173.13:18:57.89#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.13:18:57.89#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.13:18:57.89#ibcon#ireg 11 cls_cnt 2 2006.173.13:18:57.89#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.13:18:57.95#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.13:18:57.95#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.13:18:57.95#ibcon#enter wrdev, iclass 27, count 2 2006.173.13:18:57.95#ibcon#first serial, iclass 27, count 2 2006.173.13:18:57.95#ibcon#enter sib2, iclass 27, count 2 2006.173.13:18:57.95#ibcon#flushed, iclass 27, count 2 2006.173.13:18:57.95#ibcon#about to write, iclass 27, count 2 2006.173.13:18:57.95#ibcon#wrote, iclass 27, count 2 2006.173.13:18:57.95#ibcon#about to read 3, iclass 27, count 2 2006.173.13:18:57.97#ibcon#read 3, iclass 27, count 2 2006.173.13:18:57.97#ibcon#about to read 4, iclass 27, count 2 2006.173.13:18:57.97#ibcon#read 4, iclass 27, count 2 2006.173.13:18:57.97#ibcon#about to read 5, iclass 27, count 2 2006.173.13:18:57.97#ibcon#read 5, iclass 27, count 2 2006.173.13:18:57.97#ibcon#about to read 6, iclass 27, count 2 2006.173.13:18:57.97#ibcon#read 6, iclass 27, count 2 2006.173.13:18:57.97#ibcon#end of sib2, iclass 27, count 2 2006.173.13:18:57.97#ibcon#*mode == 0, iclass 27, count 2 2006.173.13:18:57.97#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.13:18:57.97#ibcon#[25=AT06-03\r\n] 2006.173.13:18:57.97#ibcon#*before write, iclass 27, count 2 2006.173.13:18:57.97#ibcon#enter sib2, iclass 27, count 2 2006.173.13:18:57.97#ibcon#flushed, iclass 27, count 2 2006.173.13:18:57.97#ibcon#about to write, iclass 27, count 2 2006.173.13:18:57.97#ibcon#wrote, iclass 27, count 2 2006.173.13:18:57.97#ibcon#about to read 3, iclass 27, count 2 2006.173.13:18:58.00#ibcon#read 3, iclass 27, count 2 2006.173.13:18:58.00#ibcon#about to read 4, iclass 27, count 2 2006.173.13:18:58.00#ibcon#read 4, iclass 27, count 2 2006.173.13:18:58.00#ibcon#about to read 5, iclass 27, count 2 2006.173.13:18:58.00#ibcon#read 5, iclass 27, count 2 2006.173.13:18:58.00#ibcon#about to read 6, iclass 27, count 2 2006.173.13:18:58.00#ibcon#read 6, iclass 27, count 2 2006.173.13:18:58.00#ibcon#end of sib2, iclass 27, count 2 2006.173.13:18:58.00#ibcon#*after write, iclass 27, count 2 2006.173.13:18:58.00#ibcon#*before return 0, iclass 27, count 2 2006.173.13:18:58.00#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.13:18:58.00#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.13:18:58.00#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.13:18:58.00#ibcon#ireg 7 cls_cnt 0 2006.173.13:18:58.00#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.13:18:58.12#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.13:18:58.12#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.13:18:58.12#ibcon#enter wrdev, iclass 27, count 0 2006.173.13:18:58.12#ibcon#first serial, iclass 27, count 0 2006.173.13:18:58.12#ibcon#enter sib2, iclass 27, count 0 2006.173.13:18:58.12#ibcon#flushed, iclass 27, count 0 2006.173.13:18:58.12#ibcon#about to write, iclass 27, count 0 2006.173.13:18:58.12#ibcon#wrote, iclass 27, count 0 2006.173.13:18:58.12#ibcon#about to read 3, iclass 27, count 0 2006.173.13:18:58.14#ibcon#read 3, iclass 27, count 0 2006.173.13:18:58.14#ibcon#about to read 4, iclass 27, count 0 2006.173.13:18:58.14#ibcon#read 4, iclass 27, count 0 2006.173.13:18:58.14#ibcon#about to read 5, iclass 27, count 0 2006.173.13:18:58.14#ibcon#read 5, iclass 27, count 0 2006.173.13:18:58.14#ibcon#about to read 6, iclass 27, count 0 2006.173.13:18:58.14#ibcon#read 6, iclass 27, count 0 2006.173.13:18:58.14#ibcon#end of sib2, iclass 27, count 0 2006.173.13:18:58.14#ibcon#*mode == 0, iclass 27, count 0 2006.173.13:18:58.14#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.13:18:58.14#ibcon#[25=USB\r\n] 2006.173.13:18:58.14#ibcon#*before write, iclass 27, count 0 2006.173.13:18:58.14#ibcon#enter sib2, iclass 27, count 0 2006.173.13:18:58.14#ibcon#flushed, iclass 27, count 0 2006.173.13:18:58.14#ibcon#about to write, iclass 27, count 0 2006.173.13:18:58.14#ibcon#wrote, iclass 27, count 0 2006.173.13:18:58.14#ibcon#about to read 3, iclass 27, count 0 2006.173.13:18:58.17#ibcon#read 3, iclass 27, count 0 2006.173.13:18:58.17#ibcon#about to read 4, iclass 27, count 0 2006.173.13:18:58.17#ibcon#read 4, iclass 27, count 0 2006.173.13:18:58.17#ibcon#about to read 5, iclass 27, count 0 2006.173.13:18:58.17#ibcon#read 5, iclass 27, count 0 2006.173.13:18:58.17#ibcon#about to read 6, iclass 27, count 0 2006.173.13:18:58.17#ibcon#read 6, iclass 27, count 0 2006.173.13:18:58.17#ibcon#end of sib2, iclass 27, count 0 2006.173.13:18:58.17#ibcon#*after write, iclass 27, count 0 2006.173.13:18:58.17#ibcon#*before return 0, iclass 27, count 0 2006.173.13:18:58.17#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.13:18:58.17#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.13:18:58.17#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.13:18:58.17#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.13:18:58.17$vck44/valo=7,864.99 2006.173.13:18:58.17#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.13:18:58.17#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.13:18:58.17#ibcon#ireg 17 cls_cnt 0 2006.173.13:18:58.17#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.13:18:58.17#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.13:18:58.17#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.13:18:58.17#ibcon#enter wrdev, iclass 29, count 0 2006.173.13:18:58.17#ibcon#first serial, iclass 29, count 0 2006.173.13:18:58.17#ibcon#enter sib2, iclass 29, count 0 2006.173.13:18:58.17#ibcon#flushed, iclass 29, count 0 2006.173.13:18:58.17#ibcon#about to write, iclass 29, count 0 2006.173.13:18:58.17#ibcon#wrote, iclass 29, count 0 2006.173.13:18:58.17#ibcon#about to read 3, iclass 29, count 0 2006.173.13:18:58.19#ibcon#read 3, iclass 29, count 0 2006.173.13:18:58.19#ibcon#about to read 4, iclass 29, count 0 2006.173.13:18:58.19#ibcon#read 4, iclass 29, count 0 2006.173.13:18:58.19#ibcon#about to read 5, iclass 29, count 0 2006.173.13:18:58.19#ibcon#read 5, iclass 29, count 0 2006.173.13:18:58.19#ibcon#about to read 6, iclass 29, count 0 2006.173.13:18:58.19#ibcon#read 6, iclass 29, count 0 2006.173.13:18:58.19#ibcon#end of sib2, iclass 29, count 0 2006.173.13:18:58.19#ibcon#*mode == 0, iclass 29, count 0 2006.173.13:18:58.19#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.13:18:58.19#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.13:18:58.19#ibcon#*before write, iclass 29, count 0 2006.173.13:18:58.19#ibcon#enter sib2, iclass 29, count 0 2006.173.13:18:58.19#ibcon#flushed, iclass 29, count 0 2006.173.13:18:58.19#ibcon#about to write, iclass 29, count 0 2006.173.13:18:58.19#ibcon#wrote, iclass 29, count 0 2006.173.13:18:58.19#ibcon#about to read 3, iclass 29, count 0 2006.173.13:18:58.23#ibcon#read 3, iclass 29, count 0 2006.173.13:18:58.23#ibcon#about to read 4, iclass 29, count 0 2006.173.13:18:58.23#ibcon#read 4, iclass 29, count 0 2006.173.13:18:58.23#ibcon#about to read 5, iclass 29, count 0 2006.173.13:18:58.23#ibcon#read 5, iclass 29, count 0 2006.173.13:18:58.23#ibcon#about to read 6, iclass 29, count 0 2006.173.13:18:58.23#ibcon#read 6, iclass 29, count 0 2006.173.13:18:58.23#ibcon#end of sib2, iclass 29, count 0 2006.173.13:18:58.23#ibcon#*after write, iclass 29, count 0 2006.173.13:18:58.23#ibcon#*before return 0, iclass 29, count 0 2006.173.13:18:58.23#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.13:18:58.23#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.13:18:58.23#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.13:18:58.23#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.13:18:58.23$vck44/va=7,4 2006.173.13:18:58.23#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.13:18:58.23#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.13:18:58.23#ibcon#ireg 11 cls_cnt 2 2006.173.13:18:58.23#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.13:18:58.29#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.13:18:58.29#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.13:18:58.29#ibcon#enter wrdev, iclass 31, count 2 2006.173.13:18:58.29#ibcon#first serial, iclass 31, count 2 2006.173.13:18:58.29#ibcon#enter sib2, iclass 31, count 2 2006.173.13:18:58.29#ibcon#flushed, iclass 31, count 2 2006.173.13:18:58.29#ibcon#about to write, iclass 31, count 2 2006.173.13:18:58.29#ibcon#wrote, iclass 31, count 2 2006.173.13:18:58.29#ibcon#about to read 3, iclass 31, count 2 2006.173.13:18:58.31#ibcon#read 3, iclass 31, count 2 2006.173.13:18:58.31#ibcon#about to read 4, iclass 31, count 2 2006.173.13:18:58.31#ibcon#read 4, iclass 31, count 2 2006.173.13:18:58.31#ibcon#about to read 5, iclass 31, count 2 2006.173.13:18:58.31#ibcon#read 5, iclass 31, count 2 2006.173.13:18:58.31#ibcon#about to read 6, iclass 31, count 2 2006.173.13:18:58.31#ibcon#read 6, iclass 31, count 2 2006.173.13:18:58.31#ibcon#end of sib2, iclass 31, count 2 2006.173.13:18:58.31#ibcon#*mode == 0, iclass 31, count 2 2006.173.13:18:58.31#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.13:18:58.31#ibcon#[25=AT07-04\r\n] 2006.173.13:18:58.31#ibcon#*before write, iclass 31, count 2 2006.173.13:18:58.31#ibcon#enter sib2, iclass 31, count 2 2006.173.13:18:58.31#ibcon#flushed, iclass 31, count 2 2006.173.13:18:58.31#ibcon#about to write, iclass 31, count 2 2006.173.13:18:58.31#ibcon#wrote, iclass 31, count 2 2006.173.13:18:58.31#ibcon#about to read 3, iclass 31, count 2 2006.173.13:18:58.34#ibcon#read 3, iclass 31, count 2 2006.173.13:18:58.34#ibcon#about to read 4, iclass 31, count 2 2006.173.13:18:58.34#ibcon#read 4, iclass 31, count 2 2006.173.13:18:58.34#ibcon#about to read 5, iclass 31, count 2 2006.173.13:18:58.34#ibcon#read 5, iclass 31, count 2 2006.173.13:18:58.34#ibcon#about to read 6, iclass 31, count 2 2006.173.13:18:58.34#ibcon#read 6, iclass 31, count 2 2006.173.13:18:58.34#ibcon#end of sib2, iclass 31, count 2 2006.173.13:18:58.34#ibcon#*after write, iclass 31, count 2 2006.173.13:18:58.34#ibcon#*before return 0, iclass 31, count 2 2006.173.13:18:58.34#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.13:18:58.34#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.13:18:58.34#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.13:18:58.34#ibcon#ireg 7 cls_cnt 0 2006.173.13:18:58.34#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.13:18:58.46#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.13:18:58.46#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.13:18:58.46#ibcon#enter wrdev, iclass 31, count 0 2006.173.13:18:58.46#ibcon#first serial, iclass 31, count 0 2006.173.13:18:58.46#ibcon#enter sib2, iclass 31, count 0 2006.173.13:18:58.46#ibcon#flushed, iclass 31, count 0 2006.173.13:18:58.46#ibcon#about to write, iclass 31, count 0 2006.173.13:18:58.46#ibcon#wrote, iclass 31, count 0 2006.173.13:18:58.46#ibcon#about to read 3, iclass 31, count 0 2006.173.13:18:58.48#ibcon#read 3, iclass 31, count 0 2006.173.13:18:58.48#ibcon#about to read 4, iclass 31, count 0 2006.173.13:18:58.48#ibcon#read 4, iclass 31, count 0 2006.173.13:18:58.48#ibcon#about to read 5, iclass 31, count 0 2006.173.13:18:58.48#ibcon#read 5, iclass 31, count 0 2006.173.13:18:58.48#ibcon#about to read 6, iclass 31, count 0 2006.173.13:18:58.48#ibcon#read 6, iclass 31, count 0 2006.173.13:18:58.48#ibcon#end of sib2, iclass 31, count 0 2006.173.13:18:58.48#ibcon#*mode == 0, iclass 31, count 0 2006.173.13:18:58.48#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.13:18:58.48#ibcon#[25=USB\r\n] 2006.173.13:18:58.48#ibcon#*before write, iclass 31, count 0 2006.173.13:18:58.48#ibcon#enter sib2, iclass 31, count 0 2006.173.13:18:58.48#ibcon#flushed, iclass 31, count 0 2006.173.13:18:58.48#ibcon#about to write, iclass 31, count 0 2006.173.13:18:58.48#ibcon#wrote, iclass 31, count 0 2006.173.13:18:58.48#ibcon#about to read 3, iclass 31, count 0 2006.173.13:18:58.51#ibcon#read 3, iclass 31, count 0 2006.173.13:18:58.51#ibcon#about to read 4, iclass 31, count 0 2006.173.13:18:58.51#ibcon#read 4, iclass 31, count 0 2006.173.13:18:58.51#ibcon#about to read 5, iclass 31, count 0 2006.173.13:18:58.51#ibcon#read 5, iclass 31, count 0 2006.173.13:18:58.51#ibcon#about to read 6, iclass 31, count 0 2006.173.13:18:58.51#ibcon#read 6, iclass 31, count 0 2006.173.13:18:58.51#ibcon#end of sib2, iclass 31, count 0 2006.173.13:18:58.51#ibcon#*after write, iclass 31, count 0 2006.173.13:18:58.51#ibcon#*before return 0, iclass 31, count 0 2006.173.13:18:58.51#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.13:18:58.51#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.13:18:58.51#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.13:18:58.51#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.13:18:58.51$vck44/valo=8,884.99 2006.173.13:18:58.51#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.13:18:58.51#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.13:18:58.51#ibcon#ireg 17 cls_cnt 0 2006.173.13:18:58.51#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.13:18:58.51#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.13:18:58.51#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.13:18:58.51#ibcon#enter wrdev, iclass 33, count 0 2006.173.13:18:58.51#ibcon#first serial, iclass 33, count 0 2006.173.13:18:58.51#ibcon#enter sib2, iclass 33, count 0 2006.173.13:18:58.51#ibcon#flushed, iclass 33, count 0 2006.173.13:18:58.51#ibcon#about to write, iclass 33, count 0 2006.173.13:18:58.51#ibcon#wrote, iclass 33, count 0 2006.173.13:18:58.51#ibcon#about to read 3, iclass 33, count 0 2006.173.13:18:58.53#ibcon#read 3, iclass 33, count 0 2006.173.13:18:58.53#ibcon#about to read 4, iclass 33, count 0 2006.173.13:18:58.53#ibcon#read 4, iclass 33, count 0 2006.173.13:18:58.53#ibcon#about to read 5, iclass 33, count 0 2006.173.13:18:58.53#ibcon#read 5, iclass 33, count 0 2006.173.13:18:58.53#ibcon#about to read 6, iclass 33, count 0 2006.173.13:18:58.53#ibcon#read 6, iclass 33, count 0 2006.173.13:18:58.53#ibcon#end of sib2, iclass 33, count 0 2006.173.13:18:58.53#ibcon#*mode == 0, iclass 33, count 0 2006.173.13:18:58.53#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.13:18:58.53#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.13:18:58.53#ibcon#*before write, iclass 33, count 0 2006.173.13:18:58.53#ibcon#enter sib2, iclass 33, count 0 2006.173.13:18:58.53#ibcon#flushed, iclass 33, count 0 2006.173.13:18:58.53#ibcon#about to write, iclass 33, count 0 2006.173.13:18:58.53#ibcon#wrote, iclass 33, count 0 2006.173.13:18:58.53#ibcon#about to read 3, iclass 33, count 0 2006.173.13:18:58.57#ibcon#read 3, iclass 33, count 0 2006.173.13:18:58.57#ibcon#about to read 4, iclass 33, count 0 2006.173.13:18:58.57#ibcon#read 4, iclass 33, count 0 2006.173.13:18:58.57#ibcon#about to read 5, iclass 33, count 0 2006.173.13:18:58.57#ibcon#read 5, iclass 33, count 0 2006.173.13:18:58.57#ibcon#about to read 6, iclass 33, count 0 2006.173.13:18:58.57#ibcon#read 6, iclass 33, count 0 2006.173.13:18:58.57#ibcon#end of sib2, iclass 33, count 0 2006.173.13:18:58.57#ibcon#*after write, iclass 33, count 0 2006.173.13:18:58.57#ibcon#*before return 0, iclass 33, count 0 2006.173.13:18:58.57#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.13:18:58.57#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.13:18:58.57#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.13:18:58.57#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.13:18:58.57$vck44/va=8,4 2006.173.13:18:58.57#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.13:18:58.57#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.13:18:58.57#ibcon#ireg 11 cls_cnt 2 2006.173.13:18:58.57#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.13:18:58.63#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.13:18:58.63#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.13:18:58.63#ibcon#enter wrdev, iclass 35, count 2 2006.173.13:18:58.63#ibcon#first serial, iclass 35, count 2 2006.173.13:18:58.63#ibcon#enter sib2, iclass 35, count 2 2006.173.13:18:58.63#ibcon#flushed, iclass 35, count 2 2006.173.13:18:58.63#ibcon#about to write, iclass 35, count 2 2006.173.13:18:58.63#ibcon#wrote, iclass 35, count 2 2006.173.13:18:58.63#ibcon#about to read 3, iclass 35, count 2 2006.173.13:18:58.65#ibcon#read 3, iclass 35, count 2 2006.173.13:18:58.65#ibcon#about to read 4, iclass 35, count 2 2006.173.13:18:58.65#ibcon#read 4, iclass 35, count 2 2006.173.13:18:58.65#ibcon#about to read 5, iclass 35, count 2 2006.173.13:18:58.65#ibcon#read 5, iclass 35, count 2 2006.173.13:18:58.65#ibcon#about to read 6, iclass 35, count 2 2006.173.13:18:58.65#ibcon#read 6, iclass 35, count 2 2006.173.13:18:58.65#ibcon#end of sib2, iclass 35, count 2 2006.173.13:18:58.65#ibcon#*mode == 0, iclass 35, count 2 2006.173.13:18:58.65#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.13:18:58.65#ibcon#[25=AT08-04\r\n] 2006.173.13:18:58.65#ibcon#*before write, iclass 35, count 2 2006.173.13:18:58.65#ibcon#enter sib2, iclass 35, count 2 2006.173.13:18:58.65#ibcon#flushed, iclass 35, count 2 2006.173.13:18:58.65#ibcon#about to write, iclass 35, count 2 2006.173.13:18:58.65#ibcon#wrote, iclass 35, count 2 2006.173.13:18:58.65#ibcon#about to read 3, iclass 35, count 2 2006.173.13:18:58.68#ibcon#read 3, iclass 35, count 2 2006.173.13:18:58.68#ibcon#about to read 4, iclass 35, count 2 2006.173.13:18:58.68#ibcon#read 4, iclass 35, count 2 2006.173.13:18:58.68#ibcon#about to read 5, iclass 35, count 2 2006.173.13:18:58.68#ibcon#read 5, iclass 35, count 2 2006.173.13:18:58.68#ibcon#about to read 6, iclass 35, count 2 2006.173.13:18:58.68#ibcon#read 6, iclass 35, count 2 2006.173.13:18:58.68#ibcon#end of sib2, iclass 35, count 2 2006.173.13:18:58.68#ibcon#*after write, iclass 35, count 2 2006.173.13:18:58.68#ibcon#*before return 0, iclass 35, count 2 2006.173.13:18:58.68#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.13:18:58.68#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.13:18:58.68#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.13:18:58.68#ibcon#ireg 7 cls_cnt 0 2006.173.13:18:58.68#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.13:18:58.80#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.13:18:58.80#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.13:18:58.80#ibcon#enter wrdev, iclass 35, count 0 2006.173.13:18:58.80#ibcon#first serial, iclass 35, count 0 2006.173.13:18:58.80#ibcon#enter sib2, iclass 35, count 0 2006.173.13:18:58.80#ibcon#flushed, iclass 35, count 0 2006.173.13:18:58.80#ibcon#about to write, iclass 35, count 0 2006.173.13:18:58.80#ibcon#wrote, iclass 35, count 0 2006.173.13:18:58.80#ibcon#about to read 3, iclass 35, count 0 2006.173.13:18:58.82#ibcon#read 3, iclass 35, count 0 2006.173.13:18:58.82#ibcon#about to read 4, iclass 35, count 0 2006.173.13:18:58.82#ibcon#read 4, iclass 35, count 0 2006.173.13:18:58.82#ibcon#about to read 5, iclass 35, count 0 2006.173.13:18:58.82#ibcon#read 5, iclass 35, count 0 2006.173.13:18:58.82#ibcon#about to read 6, iclass 35, count 0 2006.173.13:18:58.82#ibcon#read 6, iclass 35, count 0 2006.173.13:18:58.82#ibcon#end of sib2, iclass 35, count 0 2006.173.13:18:58.82#ibcon#*mode == 0, iclass 35, count 0 2006.173.13:18:58.82#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.13:18:58.82#ibcon#[25=USB\r\n] 2006.173.13:18:58.82#ibcon#*before write, iclass 35, count 0 2006.173.13:18:58.82#ibcon#enter sib2, iclass 35, count 0 2006.173.13:18:58.82#ibcon#flushed, iclass 35, count 0 2006.173.13:18:58.82#ibcon#about to write, iclass 35, count 0 2006.173.13:18:58.82#ibcon#wrote, iclass 35, count 0 2006.173.13:18:58.82#ibcon#about to read 3, iclass 35, count 0 2006.173.13:18:58.85#ibcon#read 3, iclass 35, count 0 2006.173.13:18:58.85#ibcon#about to read 4, iclass 35, count 0 2006.173.13:18:58.85#ibcon#read 4, iclass 35, count 0 2006.173.13:18:58.85#ibcon#about to read 5, iclass 35, count 0 2006.173.13:18:58.85#ibcon#read 5, iclass 35, count 0 2006.173.13:18:58.85#ibcon#about to read 6, iclass 35, count 0 2006.173.13:18:58.85#ibcon#read 6, iclass 35, count 0 2006.173.13:18:58.85#ibcon#end of sib2, iclass 35, count 0 2006.173.13:18:58.85#ibcon#*after write, iclass 35, count 0 2006.173.13:18:58.85#ibcon#*before return 0, iclass 35, count 0 2006.173.13:18:58.85#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.13:18:58.85#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.13:18:58.85#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.13:18:58.85#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.13:18:58.85$vck44/vblo=1,629.99 2006.173.13:18:58.85#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.13:18:58.85#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.13:18:58.85#ibcon#ireg 17 cls_cnt 0 2006.173.13:18:58.85#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.13:18:58.85#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.13:18:58.85#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.13:18:58.85#ibcon#enter wrdev, iclass 37, count 0 2006.173.13:18:58.85#ibcon#first serial, iclass 37, count 0 2006.173.13:18:58.85#ibcon#enter sib2, iclass 37, count 0 2006.173.13:18:58.85#ibcon#flushed, iclass 37, count 0 2006.173.13:18:58.85#ibcon#about to write, iclass 37, count 0 2006.173.13:18:58.85#ibcon#wrote, iclass 37, count 0 2006.173.13:18:58.85#ibcon#about to read 3, iclass 37, count 0 2006.173.13:18:58.87#ibcon#read 3, iclass 37, count 0 2006.173.13:18:58.87#ibcon#about to read 4, iclass 37, count 0 2006.173.13:18:58.87#ibcon#read 4, iclass 37, count 0 2006.173.13:18:58.87#ibcon#about to read 5, iclass 37, count 0 2006.173.13:18:58.87#ibcon#read 5, iclass 37, count 0 2006.173.13:18:58.87#ibcon#about to read 6, iclass 37, count 0 2006.173.13:18:58.87#ibcon#read 6, iclass 37, count 0 2006.173.13:18:58.87#ibcon#end of sib2, iclass 37, count 0 2006.173.13:18:58.87#ibcon#*mode == 0, iclass 37, count 0 2006.173.13:18:58.87#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.13:18:58.87#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.13:18:58.87#ibcon#*before write, iclass 37, count 0 2006.173.13:18:58.87#ibcon#enter sib2, iclass 37, count 0 2006.173.13:18:58.87#ibcon#flushed, iclass 37, count 0 2006.173.13:18:58.87#ibcon#about to write, iclass 37, count 0 2006.173.13:18:58.87#ibcon#wrote, iclass 37, count 0 2006.173.13:18:58.87#ibcon#about to read 3, iclass 37, count 0 2006.173.13:18:58.91#ibcon#read 3, iclass 37, count 0 2006.173.13:18:58.91#ibcon#about to read 4, iclass 37, count 0 2006.173.13:18:58.91#ibcon#read 4, iclass 37, count 0 2006.173.13:18:58.91#ibcon#about to read 5, iclass 37, count 0 2006.173.13:18:58.91#ibcon#read 5, iclass 37, count 0 2006.173.13:18:58.91#ibcon#about to read 6, iclass 37, count 0 2006.173.13:18:58.91#ibcon#read 6, iclass 37, count 0 2006.173.13:18:58.91#ibcon#end of sib2, iclass 37, count 0 2006.173.13:18:58.91#ibcon#*after write, iclass 37, count 0 2006.173.13:18:58.91#ibcon#*before return 0, iclass 37, count 0 2006.173.13:18:58.91#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.13:18:58.91#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.13:18:58.91#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.13:18:58.91#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.13:18:58.91$vck44/vb=1,4 2006.173.13:18:58.91#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.13:18:58.91#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.13:18:58.91#ibcon#ireg 11 cls_cnt 2 2006.173.13:18:58.91#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.13:18:58.91#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.13:18:58.91#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.13:18:58.91#ibcon#enter wrdev, iclass 39, count 2 2006.173.13:18:58.91#ibcon#first serial, iclass 39, count 2 2006.173.13:18:58.91#ibcon#enter sib2, iclass 39, count 2 2006.173.13:18:58.91#ibcon#flushed, iclass 39, count 2 2006.173.13:18:58.91#ibcon#about to write, iclass 39, count 2 2006.173.13:18:58.91#ibcon#wrote, iclass 39, count 2 2006.173.13:18:58.91#ibcon#about to read 3, iclass 39, count 2 2006.173.13:18:58.93#ibcon#read 3, iclass 39, count 2 2006.173.13:18:58.93#ibcon#about to read 4, iclass 39, count 2 2006.173.13:18:58.93#ibcon#read 4, iclass 39, count 2 2006.173.13:18:58.93#ibcon#about to read 5, iclass 39, count 2 2006.173.13:18:58.93#ibcon#read 5, iclass 39, count 2 2006.173.13:18:58.93#ibcon#about to read 6, iclass 39, count 2 2006.173.13:18:58.93#ibcon#read 6, iclass 39, count 2 2006.173.13:18:58.93#ibcon#end of sib2, iclass 39, count 2 2006.173.13:18:58.93#ibcon#*mode == 0, iclass 39, count 2 2006.173.13:18:58.93#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.13:18:58.93#ibcon#[27=AT01-04\r\n] 2006.173.13:18:58.93#ibcon#*before write, iclass 39, count 2 2006.173.13:18:58.93#ibcon#enter sib2, iclass 39, count 2 2006.173.13:18:58.93#ibcon#flushed, iclass 39, count 2 2006.173.13:18:58.93#ibcon#about to write, iclass 39, count 2 2006.173.13:18:58.93#ibcon#wrote, iclass 39, count 2 2006.173.13:18:58.93#ibcon#about to read 3, iclass 39, count 2 2006.173.13:18:58.96#ibcon#read 3, iclass 39, count 2 2006.173.13:18:58.96#ibcon#about to read 4, iclass 39, count 2 2006.173.13:18:58.96#ibcon#read 4, iclass 39, count 2 2006.173.13:18:58.96#ibcon#about to read 5, iclass 39, count 2 2006.173.13:18:58.96#ibcon#read 5, iclass 39, count 2 2006.173.13:18:58.96#ibcon#about to read 6, iclass 39, count 2 2006.173.13:18:58.96#ibcon#read 6, iclass 39, count 2 2006.173.13:18:58.96#ibcon#end of sib2, iclass 39, count 2 2006.173.13:18:58.96#ibcon#*after write, iclass 39, count 2 2006.173.13:18:58.96#ibcon#*before return 0, iclass 39, count 2 2006.173.13:18:58.96#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.13:18:58.96#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.13:18:58.96#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.13:18:58.96#ibcon#ireg 7 cls_cnt 0 2006.173.13:18:58.96#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.13:18:59.08#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.13:18:59.08#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.13:18:59.08#ibcon#enter wrdev, iclass 39, count 0 2006.173.13:18:59.08#ibcon#first serial, iclass 39, count 0 2006.173.13:18:59.08#ibcon#enter sib2, iclass 39, count 0 2006.173.13:18:59.08#ibcon#flushed, iclass 39, count 0 2006.173.13:18:59.08#ibcon#about to write, iclass 39, count 0 2006.173.13:18:59.08#ibcon#wrote, iclass 39, count 0 2006.173.13:18:59.08#ibcon#about to read 3, iclass 39, count 0 2006.173.13:18:59.10#ibcon#read 3, iclass 39, count 0 2006.173.13:18:59.10#ibcon#about to read 4, iclass 39, count 0 2006.173.13:18:59.10#ibcon#read 4, iclass 39, count 0 2006.173.13:18:59.10#ibcon#about to read 5, iclass 39, count 0 2006.173.13:18:59.10#ibcon#read 5, iclass 39, count 0 2006.173.13:18:59.10#ibcon#about to read 6, iclass 39, count 0 2006.173.13:18:59.10#ibcon#read 6, iclass 39, count 0 2006.173.13:18:59.10#ibcon#end of sib2, iclass 39, count 0 2006.173.13:18:59.10#ibcon#*mode == 0, iclass 39, count 0 2006.173.13:18:59.10#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.13:18:59.10#ibcon#[27=USB\r\n] 2006.173.13:18:59.10#ibcon#*before write, iclass 39, count 0 2006.173.13:18:59.10#ibcon#enter sib2, iclass 39, count 0 2006.173.13:18:59.10#ibcon#flushed, iclass 39, count 0 2006.173.13:18:59.10#ibcon#about to write, iclass 39, count 0 2006.173.13:18:59.10#ibcon#wrote, iclass 39, count 0 2006.173.13:18:59.10#ibcon#about to read 3, iclass 39, count 0 2006.173.13:18:59.13#ibcon#read 3, iclass 39, count 0 2006.173.13:18:59.13#ibcon#about to read 4, iclass 39, count 0 2006.173.13:18:59.13#ibcon#read 4, iclass 39, count 0 2006.173.13:18:59.13#ibcon#about to read 5, iclass 39, count 0 2006.173.13:18:59.13#ibcon#read 5, iclass 39, count 0 2006.173.13:18:59.13#ibcon#about to read 6, iclass 39, count 0 2006.173.13:18:59.13#ibcon#read 6, iclass 39, count 0 2006.173.13:18:59.13#ibcon#end of sib2, iclass 39, count 0 2006.173.13:18:59.13#ibcon#*after write, iclass 39, count 0 2006.173.13:18:59.13#ibcon#*before return 0, iclass 39, count 0 2006.173.13:18:59.13#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.13:18:59.13#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.13:18:59.13#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.13:18:59.13#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.13:18:59.13$vck44/vblo=2,634.99 2006.173.13:18:59.13#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.13:18:59.13#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.13:18:59.13#ibcon#ireg 17 cls_cnt 0 2006.173.13:18:59.13#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.13:18:59.13#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.13:18:59.13#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.13:18:59.13#ibcon#enter wrdev, iclass 3, count 0 2006.173.13:18:59.13#ibcon#first serial, iclass 3, count 0 2006.173.13:18:59.13#ibcon#enter sib2, iclass 3, count 0 2006.173.13:18:59.13#ibcon#flushed, iclass 3, count 0 2006.173.13:18:59.13#ibcon#about to write, iclass 3, count 0 2006.173.13:18:59.13#ibcon#wrote, iclass 3, count 0 2006.173.13:18:59.13#ibcon#about to read 3, iclass 3, count 0 2006.173.13:18:59.15#ibcon#read 3, iclass 3, count 0 2006.173.13:18:59.15#ibcon#about to read 4, iclass 3, count 0 2006.173.13:18:59.15#ibcon#read 4, iclass 3, count 0 2006.173.13:18:59.15#ibcon#about to read 5, iclass 3, count 0 2006.173.13:18:59.15#ibcon#read 5, iclass 3, count 0 2006.173.13:18:59.15#ibcon#about to read 6, iclass 3, count 0 2006.173.13:18:59.15#ibcon#read 6, iclass 3, count 0 2006.173.13:18:59.15#ibcon#end of sib2, iclass 3, count 0 2006.173.13:18:59.15#ibcon#*mode == 0, iclass 3, count 0 2006.173.13:18:59.15#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.13:18:59.15#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.13:18:59.15#ibcon#*before write, iclass 3, count 0 2006.173.13:18:59.15#ibcon#enter sib2, iclass 3, count 0 2006.173.13:18:59.15#ibcon#flushed, iclass 3, count 0 2006.173.13:18:59.15#ibcon#about to write, iclass 3, count 0 2006.173.13:18:59.15#ibcon#wrote, iclass 3, count 0 2006.173.13:18:59.15#ibcon#about to read 3, iclass 3, count 0 2006.173.13:18:59.19#ibcon#read 3, iclass 3, count 0 2006.173.13:18:59.19#ibcon#about to read 4, iclass 3, count 0 2006.173.13:18:59.19#ibcon#read 4, iclass 3, count 0 2006.173.13:18:59.19#ibcon#about to read 5, iclass 3, count 0 2006.173.13:18:59.19#ibcon#read 5, iclass 3, count 0 2006.173.13:18:59.19#ibcon#about to read 6, iclass 3, count 0 2006.173.13:18:59.19#ibcon#read 6, iclass 3, count 0 2006.173.13:18:59.19#ibcon#end of sib2, iclass 3, count 0 2006.173.13:18:59.19#ibcon#*after write, iclass 3, count 0 2006.173.13:18:59.19#ibcon#*before return 0, iclass 3, count 0 2006.173.13:18:59.19#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.13:18:59.19#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.13:18:59.19#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.13:18:59.19#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.13:18:59.19$vck44/vb=2,4 2006.173.13:18:59.19#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.13:18:59.19#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.13:18:59.19#ibcon#ireg 11 cls_cnt 2 2006.173.13:18:59.19#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.13:18:59.25#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.13:18:59.25#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.13:18:59.25#ibcon#enter wrdev, iclass 5, count 2 2006.173.13:18:59.25#ibcon#first serial, iclass 5, count 2 2006.173.13:18:59.25#ibcon#enter sib2, iclass 5, count 2 2006.173.13:18:59.25#ibcon#flushed, iclass 5, count 2 2006.173.13:18:59.25#ibcon#about to write, iclass 5, count 2 2006.173.13:18:59.25#ibcon#wrote, iclass 5, count 2 2006.173.13:18:59.25#ibcon#about to read 3, iclass 5, count 2 2006.173.13:18:59.27#ibcon#read 3, iclass 5, count 2 2006.173.13:18:59.27#ibcon#about to read 4, iclass 5, count 2 2006.173.13:18:59.27#ibcon#read 4, iclass 5, count 2 2006.173.13:18:59.27#ibcon#about to read 5, iclass 5, count 2 2006.173.13:18:59.27#ibcon#read 5, iclass 5, count 2 2006.173.13:18:59.27#ibcon#about to read 6, iclass 5, count 2 2006.173.13:18:59.27#ibcon#read 6, iclass 5, count 2 2006.173.13:18:59.27#ibcon#end of sib2, iclass 5, count 2 2006.173.13:18:59.27#ibcon#*mode == 0, iclass 5, count 2 2006.173.13:18:59.27#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.13:18:59.27#ibcon#[27=AT02-04\r\n] 2006.173.13:18:59.27#ibcon#*before write, iclass 5, count 2 2006.173.13:18:59.27#ibcon#enter sib2, iclass 5, count 2 2006.173.13:18:59.27#ibcon#flushed, iclass 5, count 2 2006.173.13:18:59.27#ibcon#about to write, iclass 5, count 2 2006.173.13:18:59.27#ibcon#wrote, iclass 5, count 2 2006.173.13:18:59.27#ibcon#about to read 3, iclass 5, count 2 2006.173.13:18:59.30#ibcon#read 3, iclass 5, count 2 2006.173.13:18:59.30#ibcon#about to read 4, iclass 5, count 2 2006.173.13:18:59.30#ibcon#read 4, iclass 5, count 2 2006.173.13:18:59.30#ibcon#about to read 5, iclass 5, count 2 2006.173.13:18:59.30#ibcon#read 5, iclass 5, count 2 2006.173.13:18:59.30#ibcon#about to read 6, iclass 5, count 2 2006.173.13:18:59.30#ibcon#read 6, iclass 5, count 2 2006.173.13:18:59.30#ibcon#end of sib2, iclass 5, count 2 2006.173.13:18:59.30#ibcon#*after write, iclass 5, count 2 2006.173.13:18:59.30#ibcon#*before return 0, iclass 5, count 2 2006.173.13:18:59.30#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.13:18:59.30#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.13:18:59.30#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.13:18:59.30#ibcon#ireg 7 cls_cnt 0 2006.173.13:18:59.30#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.13:18:59.42#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.13:18:59.42#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.13:18:59.42#ibcon#enter wrdev, iclass 5, count 0 2006.173.13:18:59.42#ibcon#first serial, iclass 5, count 0 2006.173.13:18:59.42#ibcon#enter sib2, iclass 5, count 0 2006.173.13:18:59.42#ibcon#flushed, iclass 5, count 0 2006.173.13:18:59.42#ibcon#about to write, iclass 5, count 0 2006.173.13:18:59.42#ibcon#wrote, iclass 5, count 0 2006.173.13:18:59.42#ibcon#about to read 3, iclass 5, count 0 2006.173.13:18:59.44#ibcon#read 3, iclass 5, count 0 2006.173.13:18:59.44#ibcon#about to read 4, iclass 5, count 0 2006.173.13:18:59.44#ibcon#read 4, iclass 5, count 0 2006.173.13:18:59.44#ibcon#about to read 5, iclass 5, count 0 2006.173.13:18:59.44#ibcon#read 5, iclass 5, count 0 2006.173.13:18:59.44#ibcon#about to read 6, iclass 5, count 0 2006.173.13:18:59.44#ibcon#read 6, iclass 5, count 0 2006.173.13:18:59.44#ibcon#end of sib2, iclass 5, count 0 2006.173.13:18:59.44#ibcon#*mode == 0, iclass 5, count 0 2006.173.13:18:59.44#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.13:18:59.44#ibcon#[27=USB\r\n] 2006.173.13:18:59.44#ibcon#*before write, iclass 5, count 0 2006.173.13:18:59.44#ibcon#enter sib2, iclass 5, count 0 2006.173.13:18:59.44#ibcon#flushed, iclass 5, count 0 2006.173.13:18:59.44#ibcon#about to write, iclass 5, count 0 2006.173.13:18:59.44#ibcon#wrote, iclass 5, count 0 2006.173.13:18:59.44#ibcon#about to read 3, iclass 5, count 0 2006.173.13:18:59.47#ibcon#read 3, iclass 5, count 0 2006.173.13:18:59.47#ibcon#about to read 4, iclass 5, count 0 2006.173.13:18:59.47#ibcon#read 4, iclass 5, count 0 2006.173.13:18:59.47#ibcon#about to read 5, iclass 5, count 0 2006.173.13:18:59.47#ibcon#read 5, iclass 5, count 0 2006.173.13:18:59.47#ibcon#about to read 6, iclass 5, count 0 2006.173.13:18:59.47#ibcon#read 6, iclass 5, count 0 2006.173.13:18:59.47#ibcon#end of sib2, iclass 5, count 0 2006.173.13:18:59.47#ibcon#*after write, iclass 5, count 0 2006.173.13:18:59.47#ibcon#*before return 0, iclass 5, count 0 2006.173.13:18:59.47#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.13:18:59.47#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.13:18:59.47#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.13:18:59.47#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.13:18:59.47$vck44/vblo=3,649.99 2006.173.13:18:59.47#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.13:18:59.47#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.13:18:59.47#ibcon#ireg 17 cls_cnt 0 2006.173.13:18:59.47#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.13:18:59.47#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.13:18:59.47#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.13:18:59.47#ibcon#enter wrdev, iclass 7, count 0 2006.173.13:18:59.47#ibcon#first serial, iclass 7, count 0 2006.173.13:18:59.47#ibcon#enter sib2, iclass 7, count 0 2006.173.13:18:59.47#ibcon#flushed, iclass 7, count 0 2006.173.13:18:59.47#ibcon#about to write, iclass 7, count 0 2006.173.13:18:59.47#ibcon#wrote, iclass 7, count 0 2006.173.13:18:59.47#ibcon#about to read 3, iclass 7, count 0 2006.173.13:18:59.49#ibcon#read 3, iclass 7, count 0 2006.173.13:18:59.49#ibcon#about to read 4, iclass 7, count 0 2006.173.13:18:59.49#ibcon#read 4, iclass 7, count 0 2006.173.13:18:59.49#ibcon#about to read 5, iclass 7, count 0 2006.173.13:18:59.49#ibcon#read 5, iclass 7, count 0 2006.173.13:18:59.49#ibcon#about to read 6, iclass 7, count 0 2006.173.13:18:59.49#ibcon#read 6, iclass 7, count 0 2006.173.13:18:59.49#ibcon#end of sib2, iclass 7, count 0 2006.173.13:18:59.49#ibcon#*mode == 0, iclass 7, count 0 2006.173.13:18:59.49#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.13:18:59.49#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.13:18:59.49#ibcon#*before write, iclass 7, count 0 2006.173.13:18:59.49#ibcon#enter sib2, iclass 7, count 0 2006.173.13:18:59.49#ibcon#flushed, iclass 7, count 0 2006.173.13:18:59.49#ibcon#about to write, iclass 7, count 0 2006.173.13:18:59.49#ibcon#wrote, iclass 7, count 0 2006.173.13:18:59.49#ibcon#about to read 3, iclass 7, count 0 2006.173.13:18:59.53#ibcon#read 3, iclass 7, count 0 2006.173.13:18:59.53#ibcon#about to read 4, iclass 7, count 0 2006.173.13:18:59.53#ibcon#read 4, iclass 7, count 0 2006.173.13:18:59.53#ibcon#about to read 5, iclass 7, count 0 2006.173.13:18:59.53#ibcon#read 5, iclass 7, count 0 2006.173.13:18:59.53#ibcon#about to read 6, iclass 7, count 0 2006.173.13:18:59.53#ibcon#read 6, iclass 7, count 0 2006.173.13:18:59.53#ibcon#end of sib2, iclass 7, count 0 2006.173.13:18:59.53#ibcon#*after write, iclass 7, count 0 2006.173.13:18:59.53#ibcon#*before return 0, iclass 7, count 0 2006.173.13:18:59.53#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.13:18:59.53#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.13:18:59.53#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.13:18:59.53#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.13:18:59.53$vck44/vb=3,4 2006.173.13:18:59.53#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.13:18:59.53#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.13:18:59.53#ibcon#ireg 11 cls_cnt 2 2006.173.13:18:59.53#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.13:18:59.59#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.13:18:59.59#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.13:18:59.59#ibcon#enter wrdev, iclass 11, count 2 2006.173.13:18:59.59#ibcon#first serial, iclass 11, count 2 2006.173.13:18:59.59#ibcon#enter sib2, iclass 11, count 2 2006.173.13:18:59.59#ibcon#flushed, iclass 11, count 2 2006.173.13:18:59.59#ibcon#about to write, iclass 11, count 2 2006.173.13:18:59.59#ibcon#wrote, iclass 11, count 2 2006.173.13:18:59.59#ibcon#about to read 3, iclass 11, count 2 2006.173.13:18:59.61#ibcon#read 3, iclass 11, count 2 2006.173.13:18:59.61#ibcon#about to read 4, iclass 11, count 2 2006.173.13:18:59.61#ibcon#read 4, iclass 11, count 2 2006.173.13:18:59.61#ibcon#about to read 5, iclass 11, count 2 2006.173.13:18:59.61#ibcon#read 5, iclass 11, count 2 2006.173.13:18:59.61#ibcon#about to read 6, iclass 11, count 2 2006.173.13:18:59.61#ibcon#read 6, iclass 11, count 2 2006.173.13:18:59.61#ibcon#end of sib2, iclass 11, count 2 2006.173.13:18:59.61#ibcon#*mode == 0, iclass 11, count 2 2006.173.13:18:59.61#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.13:18:59.61#ibcon#[27=AT03-04\r\n] 2006.173.13:18:59.61#ibcon#*before write, iclass 11, count 2 2006.173.13:18:59.61#ibcon#enter sib2, iclass 11, count 2 2006.173.13:18:59.61#ibcon#flushed, iclass 11, count 2 2006.173.13:18:59.61#ibcon#about to write, iclass 11, count 2 2006.173.13:18:59.61#ibcon#wrote, iclass 11, count 2 2006.173.13:18:59.61#ibcon#about to read 3, iclass 11, count 2 2006.173.13:18:59.64#ibcon#read 3, iclass 11, count 2 2006.173.13:18:59.64#ibcon#about to read 4, iclass 11, count 2 2006.173.13:18:59.64#ibcon#read 4, iclass 11, count 2 2006.173.13:18:59.64#ibcon#about to read 5, iclass 11, count 2 2006.173.13:18:59.64#ibcon#read 5, iclass 11, count 2 2006.173.13:18:59.64#ibcon#about to read 6, iclass 11, count 2 2006.173.13:18:59.64#ibcon#read 6, iclass 11, count 2 2006.173.13:18:59.64#ibcon#end of sib2, iclass 11, count 2 2006.173.13:18:59.64#ibcon#*after write, iclass 11, count 2 2006.173.13:18:59.64#ibcon#*before return 0, iclass 11, count 2 2006.173.13:18:59.64#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.13:18:59.64#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.13:18:59.64#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.13:18:59.64#ibcon#ireg 7 cls_cnt 0 2006.173.13:18:59.64#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.13:18:59.76#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.13:18:59.76#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.13:18:59.76#ibcon#enter wrdev, iclass 11, count 0 2006.173.13:18:59.76#ibcon#first serial, iclass 11, count 0 2006.173.13:18:59.76#ibcon#enter sib2, iclass 11, count 0 2006.173.13:18:59.76#ibcon#flushed, iclass 11, count 0 2006.173.13:18:59.76#ibcon#about to write, iclass 11, count 0 2006.173.13:18:59.76#ibcon#wrote, iclass 11, count 0 2006.173.13:18:59.76#ibcon#about to read 3, iclass 11, count 0 2006.173.13:18:59.78#ibcon#read 3, iclass 11, count 0 2006.173.13:18:59.78#ibcon#about to read 4, iclass 11, count 0 2006.173.13:18:59.78#ibcon#read 4, iclass 11, count 0 2006.173.13:18:59.78#ibcon#about to read 5, iclass 11, count 0 2006.173.13:18:59.78#ibcon#read 5, iclass 11, count 0 2006.173.13:18:59.78#ibcon#about to read 6, iclass 11, count 0 2006.173.13:18:59.78#ibcon#read 6, iclass 11, count 0 2006.173.13:18:59.78#ibcon#end of sib2, iclass 11, count 0 2006.173.13:18:59.78#ibcon#*mode == 0, iclass 11, count 0 2006.173.13:18:59.78#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.13:18:59.78#ibcon#[27=USB\r\n] 2006.173.13:18:59.78#ibcon#*before write, iclass 11, count 0 2006.173.13:18:59.78#ibcon#enter sib2, iclass 11, count 0 2006.173.13:18:59.78#ibcon#flushed, iclass 11, count 0 2006.173.13:18:59.78#ibcon#about to write, iclass 11, count 0 2006.173.13:18:59.78#ibcon#wrote, iclass 11, count 0 2006.173.13:18:59.78#ibcon#about to read 3, iclass 11, count 0 2006.173.13:18:59.81#ibcon#read 3, iclass 11, count 0 2006.173.13:18:59.81#ibcon#about to read 4, iclass 11, count 0 2006.173.13:18:59.81#ibcon#read 4, iclass 11, count 0 2006.173.13:18:59.81#ibcon#about to read 5, iclass 11, count 0 2006.173.13:18:59.81#ibcon#read 5, iclass 11, count 0 2006.173.13:18:59.81#ibcon#about to read 6, iclass 11, count 0 2006.173.13:18:59.81#ibcon#read 6, iclass 11, count 0 2006.173.13:18:59.81#ibcon#end of sib2, iclass 11, count 0 2006.173.13:18:59.81#ibcon#*after write, iclass 11, count 0 2006.173.13:18:59.81#ibcon#*before return 0, iclass 11, count 0 2006.173.13:18:59.81#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.13:18:59.81#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.13:18:59.81#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.13:18:59.81#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.13:18:59.81$vck44/vblo=4,679.99 2006.173.13:18:59.81#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.13:18:59.81#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.13:18:59.81#ibcon#ireg 17 cls_cnt 0 2006.173.13:18:59.81#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.13:18:59.81#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.13:18:59.81#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.13:18:59.81#ibcon#enter wrdev, iclass 13, count 0 2006.173.13:18:59.81#ibcon#first serial, iclass 13, count 0 2006.173.13:18:59.81#ibcon#enter sib2, iclass 13, count 0 2006.173.13:18:59.81#ibcon#flushed, iclass 13, count 0 2006.173.13:18:59.81#ibcon#about to write, iclass 13, count 0 2006.173.13:18:59.81#ibcon#wrote, iclass 13, count 0 2006.173.13:18:59.81#ibcon#about to read 3, iclass 13, count 0 2006.173.13:18:59.83#ibcon#read 3, iclass 13, count 0 2006.173.13:18:59.83#ibcon#about to read 4, iclass 13, count 0 2006.173.13:18:59.83#ibcon#read 4, iclass 13, count 0 2006.173.13:18:59.83#ibcon#about to read 5, iclass 13, count 0 2006.173.13:18:59.83#ibcon#read 5, iclass 13, count 0 2006.173.13:18:59.83#ibcon#about to read 6, iclass 13, count 0 2006.173.13:18:59.83#ibcon#read 6, iclass 13, count 0 2006.173.13:18:59.83#ibcon#end of sib2, iclass 13, count 0 2006.173.13:18:59.83#ibcon#*mode == 0, iclass 13, count 0 2006.173.13:18:59.83#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.13:18:59.83#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.13:18:59.83#ibcon#*before write, iclass 13, count 0 2006.173.13:18:59.83#ibcon#enter sib2, iclass 13, count 0 2006.173.13:18:59.83#ibcon#flushed, iclass 13, count 0 2006.173.13:18:59.83#ibcon#about to write, iclass 13, count 0 2006.173.13:18:59.83#ibcon#wrote, iclass 13, count 0 2006.173.13:18:59.83#ibcon#about to read 3, iclass 13, count 0 2006.173.13:18:59.87#ibcon#read 3, iclass 13, count 0 2006.173.13:18:59.87#ibcon#about to read 4, iclass 13, count 0 2006.173.13:18:59.87#ibcon#read 4, iclass 13, count 0 2006.173.13:18:59.87#ibcon#about to read 5, iclass 13, count 0 2006.173.13:18:59.87#ibcon#read 5, iclass 13, count 0 2006.173.13:18:59.87#ibcon#about to read 6, iclass 13, count 0 2006.173.13:18:59.87#ibcon#read 6, iclass 13, count 0 2006.173.13:18:59.87#ibcon#end of sib2, iclass 13, count 0 2006.173.13:18:59.87#ibcon#*after write, iclass 13, count 0 2006.173.13:18:59.87#ibcon#*before return 0, iclass 13, count 0 2006.173.13:18:59.87#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.13:18:59.87#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.13:18:59.87#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.13:18:59.87#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.13:18:59.87$vck44/vb=4,4 2006.173.13:18:59.87#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.13:18:59.87#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.13:18:59.87#ibcon#ireg 11 cls_cnt 2 2006.173.13:18:59.87#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.13:18:59.93#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.13:18:59.93#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.13:18:59.93#ibcon#enter wrdev, iclass 15, count 2 2006.173.13:18:59.93#ibcon#first serial, iclass 15, count 2 2006.173.13:18:59.93#ibcon#enter sib2, iclass 15, count 2 2006.173.13:18:59.93#ibcon#flushed, iclass 15, count 2 2006.173.13:18:59.93#ibcon#about to write, iclass 15, count 2 2006.173.13:18:59.93#ibcon#wrote, iclass 15, count 2 2006.173.13:18:59.93#ibcon#about to read 3, iclass 15, count 2 2006.173.13:18:59.95#ibcon#read 3, iclass 15, count 2 2006.173.13:18:59.95#ibcon#about to read 4, iclass 15, count 2 2006.173.13:18:59.95#ibcon#read 4, iclass 15, count 2 2006.173.13:18:59.95#ibcon#about to read 5, iclass 15, count 2 2006.173.13:18:59.95#ibcon#read 5, iclass 15, count 2 2006.173.13:18:59.95#ibcon#about to read 6, iclass 15, count 2 2006.173.13:18:59.95#ibcon#read 6, iclass 15, count 2 2006.173.13:18:59.95#ibcon#end of sib2, iclass 15, count 2 2006.173.13:18:59.95#ibcon#*mode == 0, iclass 15, count 2 2006.173.13:18:59.95#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.13:18:59.95#ibcon#[27=AT04-04\r\n] 2006.173.13:18:59.95#ibcon#*before write, iclass 15, count 2 2006.173.13:18:59.95#ibcon#enter sib2, iclass 15, count 2 2006.173.13:18:59.95#ibcon#flushed, iclass 15, count 2 2006.173.13:18:59.95#ibcon#about to write, iclass 15, count 2 2006.173.13:18:59.95#ibcon#wrote, iclass 15, count 2 2006.173.13:18:59.95#ibcon#about to read 3, iclass 15, count 2 2006.173.13:18:59.98#ibcon#read 3, iclass 15, count 2 2006.173.13:18:59.98#ibcon#about to read 4, iclass 15, count 2 2006.173.13:18:59.98#ibcon#read 4, iclass 15, count 2 2006.173.13:18:59.98#ibcon#about to read 5, iclass 15, count 2 2006.173.13:18:59.98#ibcon#read 5, iclass 15, count 2 2006.173.13:18:59.98#ibcon#about to read 6, iclass 15, count 2 2006.173.13:18:59.98#ibcon#read 6, iclass 15, count 2 2006.173.13:18:59.98#ibcon#end of sib2, iclass 15, count 2 2006.173.13:18:59.98#ibcon#*after write, iclass 15, count 2 2006.173.13:18:59.98#ibcon#*before return 0, iclass 15, count 2 2006.173.13:18:59.98#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.13:18:59.98#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.13:18:59.98#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.13:18:59.98#ibcon#ireg 7 cls_cnt 0 2006.173.13:18:59.98#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.13:19:00.10#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.13:19:00.10#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.13:19:00.10#ibcon#enter wrdev, iclass 15, count 0 2006.173.13:19:00.10#ibcon#first serial, iclass 15, count 0 2006.173.13:19:00.10#ibcon#enter sib2, iclass 15, count 0 2006.173.13:19:00.10#ibcon#flushed, iclass 15, count 0 2006.173.13:19:00.10#ibcon#about to write, iclass 15, count 0 2006.173.13:19:00.10#ibcon#wrote, iclass 15, count 0 2006.173.13:19:00.10#ibcon#about to read 3, iclass 15, count 0 2006.173.13:19:00.12#ibcon#read 3, iclass 15, count 0 2006.173.13:19:00.12#ibcon#about to read 4, iclass 15, count 0 2006.173.13:19:00.12#ibcon#read 4, iclass 15, count 0 2006.173.13:19:00.12#ibcon#about to read 5, iclass 15, count 0 2006.173.13:19:00.12#ibcon#read 5, iclass 15, count 0 2006.173.13:19:00.12#ibcon#about to read 6, iclass 15, count 0 2006.173.13:19:00.12#ibcon#read 6, iclass 15, count 0 2006.173.13:19:00.12#ibcon#end of sib2, iclass 15, count 0 2006.173.13:19:00.12#ibcon#*mode == 0, iclass 15, count 0 2006.173.13:19:00.12#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.13:19:00.12#ibcon#[27=USB\r\n] 2006.173.13:19:00.12#ibcon#*before write, iclass 15, count 0 2006.173.13:19:00.12#ibcon#enter sib2, iclass 15, count 0 2006.173.13:19:00.12#ibcon#flushed, iclass 15, count 0 2006.173.13:19:00.12#ibcon#about to write, iclass 15, count 0 2006.173.13:19:00.12#ibcon#wrote, iclass 15, count 0 2006.173.13:19:00.12#ibcon#about to read 3, iclass 15, count 0 2006.173.13:19:00.15#ibcon#read 3, iclass 15, count 0 2006.173.13:19:00.15#ibcon#about to read 4, iclass 15, count 0 2006.173.13:19:00.15#ibcon#read 4, iclass 15, count 0 2006.173.13:19:00.15#ibcon#about to read 5, iclass 15, count 0 2006.173.13:19:00.15#ibcon#read 5, iclass 15, count 0 2006.173.13:19:00.15#ibcon#about to read 6, iclass 15, count 0 2006.173.13:19:00.15#ibcon#read 6, iclass 15, count 0 2006.173.13:19:00.15#ibcon#end of sib2, iclass 15, count 0 2006.173.13:19:00.15#ibcon#*after write, iclass 15, count 0 2006.173.13:19:00.15#ibcon#*before return 0, iclass 15, count 0 2006.173.13:19:00.15#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.13:19:00.15#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.13:19:00.15#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.13:19:00.15#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.13:19:00.15$vck44/vblo=5,709.99 2006.173.13:19:00.15#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.13:19:00.15#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.13:19:00.15#ibcon#ireg 17 cls_cnt 0 2006.173.13:19:00.15#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.13:19:00.15#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.13:19:00.15#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.13:19:00.15#ibcon#enter wrdev, iclass 17, count 0 2006.173.13:19:00.15#ibcon#first serial, iclass 17, count 0 2006.173.13:19:00.15#ibcon#enter sib2, iclass 17, count 0 2006.173.13:19:00.15#ibcon#flushed, iclass 17, count 0 2006.173.13:19:00.15#ibcon#about to write, iclass 17, count 0 2006.173.13:19:00.15#ibcon#wrote, iclass 17, count 0 2006.173.13:19:00.15#ibcon#about to read 3, iclass 17, count 0 2006.173.13:19:00.17#ibcon#read 3, iclass 17, count 0 2006.173.13:19:00.17#ibcon#about to read 4, iclass 17, count 0 2006.173.13:19:00.17#ibcon#read 4, iclass 17, count 0 2006.173.13:19:00.17#ibcon#about to read 5, iclass 17, count 0 2006.173.13:19:00.17#ibcon#read 5, iclass 17, count 0 2006.173.13:19:00.17#ibcon#about to read 6, iclass 17, count 0 2006.173.13:19:00.17#ibcon#read 6, iclass 17, count 0 2006.173.13:19:00.17#ibcon#end of sib2, iclass 17, count 0 2006.173.13:19:00.17#ibcon#*mode == 0, iclass 17, count 0 2006.173.13:19:00.17#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.13:19:00.17#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.13:19:00.17#ibcon#*before write, iclass 17, count 0 2006.173.13:19:00.17#ibcon#enter sib2, iclass 17, count 0 2006.173.13:19:00.17#ibcon#flushed, iclass 17, count 0 2006.173.13:19:00.17#ibcon#about to write, iclass 17, count 0 2006.173.13:19:00.17#ibcon#wrote, iclass 17, count 0 2006.173.13:19:00.17#ibcon#about to read 3, iclass 17, count 0 2006.173.13:19:00.21#ibcon#read 3, iclass 17, count 0 2006.173.13:19:00.21#ibcon#about to read 4, iclass 17, count 0 2006.173.13:19:00.21#ibcon#read 4, iclass 17, count 0 2006.173.13:19:00.21#ibcon#about to read 5, iclass 17, count 0 2006.173.13:19:00.21#ibcon#read 5, iclass 17, count 0 2006.173.13:19:00.21#ibcon#about to read 6, iclass 17, count 0 2006.173.13:19:00.21#ibcon#read 6, iclass 17, count 0 2006.173.13:19:00.21#ibcon#end of sib2, iclass 17, count 0 2006.173.13:19:00.21#ibcon#*after write, iclass 17, count 0 2006.173.13:19:00.21#ibcon#*before return 0, iclass 17, count 0 2006.173.13:19:00.21#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.13:19:00.21#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.13:19:00.21#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.13:19:00.21#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.13:19:00.21$vck44/vb=5,4 2006.173.13:19:00.21#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.13:19:00.21#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.13:19:00.21#ibcon#ireg 11 cls_cnt 2 2006.173.13:19:00.21#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.13:19:00.27#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.13:19:00.27#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.13:19:00.27#ibcon#enter wrdev, iclass 19, count 2 2006.173.13:19:00.27#ibcon#first serial, iclass 19, count 2 2006.173.13:19:00.27#ibcon#enter sib2, iclass 19, count 2 2006.173.13:19:00.27#ibcon#flushed, iclass 19, count 2 2006.173.13:19:00.27#ibcon#about to write, iclass 19, count 2 2006.173.13:19:00.27#ibcon#wrote, iclass 19, count 2 2006.173.13:19:00.27#ibcon#about to read 3, iclass 19, count 2 2006.173.13:19:00.29#ibcon#read 3, iclass 19, count 2 2006.173.13:19:00.29#ibcon#about to read 4, iclass 19, count 2 2006.173.13:19:00.29#ibcon#read 4, iclass 19, count 2 2006.173.13:19:00.29#ibcon#about to read 5, iclass 19, count 2 2006.173.13:19:00.29#ibcon#read 5, iclass 19, count 2 2006.173.13:19:00.29#ibcon#about to read 6, iclass 19, count 2 2006.173.13:19:00.29#ibcon#read 6, iclass 19, count 2 2006.173.13:19:00.29#ibcon#end of sib2, iclass 19, count 2 2006.173.13:19:00.29#ibcon#*mode == 0, iclass 19, count 2 2006.173.13:19:00.29#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.13:19:00.29#ibcon#[27=AT05-04\r\n] 2006.173.13:19:00.29#ibcon#*before write, iclass 19, count 2 2006.173.13:19:00.29#ibcon#enter sib2, iclass 19, count 2 2006.173.13:19:00.29#ibcon#flushed, iclass 19, count 2 2006.173.13:19:00.29#ibcon#about to write, iclass 19, count 2 2006.173.13:19:00.29#ibcon#wrote, iclass 19, count 2 2006.173.13:19:00.29#ibcon#about to read 3, iclass 19, count 2 2006.173.13:19:00.32#ibcon#read 3, iclass 19, count 2 2006.173.13:19:00.32#ibcon#about to read 4, iclass 19, count 2 2006.173.13:19:00.32#ibcon#read 4, iclass 19, count 2 2006.173.13:19:00.32#ibcon#about to read 5, iclass 19, count 2 2006.173.13:19:00.32#ibcon#read 5, iclass 19, count 2 2006.173.13:19:00.32#ibcon#about to read 6, iclass 19, count 2 2006.173.13:19:00.32#ibcon#read 6, iclass 19, count 2 2006.173.13:19:00.32#ibcon#end of sib2, iclass 19, count 2 2006.173.13:19:00.32#ibcon#*after write, iclass 19, count 2 2006.173.13:19:00.32#ibcon#*before return 0, iclass 19, count 2 2006.173.13:19:00.32#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.13:19:00.32#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.13:19:00.32#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.13:19:00.32#ibcon#ireg 7 cls_cnt 0 2006.173.13:19:00.32#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.13:19:00.44#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.13:19:00.44#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.13:19:00.44#ibcon#enter wrdev, iclass 19, count 0 2006.173.13:19:00.44#ibcon#first serial, iclass 19, count 0 2006.173.13:19:00.44#ibcon#enter sib2, iclass 19, count 0 2006.173.13:19:00.44#ibcon#flushed, iclass 19, count 0 2006.173.13:19:00.44#ibcon#about to write, iclass 19, count 0 2006.173.13:19:00.44#ibcon#wrote, iclass 19, count 0 2006.173.13:19:00.44#ibcon#about to read 3, iclass 19, count 0 2006.173.13:19:00.46#ibcon#read 3, iclass 19, count 0 2006.173.13:19:00.46#ibcon#about to read 4, iclass 19, count 0 2006.173.13:19:00.46#ibcon#read 4, iclass 19, count 0 2006.173.13:19:00.46#ibcon#about to read 5, iclass 19, count 0 2006.173.13:19:00.46#ibcon#read 5, iclass 19, count 0 2006.173.13:19:00.46#ibcon#about to read 6, iclass 19, count 0 2006.173.13:19:00.46#ibcon#read 6, iclass 19, count 0 2006.173.13:19:00.46#ibcon#end of sib2, iclass 19, count 0 2006.173.13:19:00.46#ibcon#*mode == 0, iclass 19, count 0 2006.173.13:19:00.46#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.13:19:00.46#ibcon#[27=USB\r\n] 2006.173.13:19:00.46#ibcon#*before write, iclass 19, count 0 2006.173.13:19:00.46#ibcon#enter sib2, iclass 19, count 0 2006.173.13:19:00.46#ibcon#flushed, iclass 19, count 0 2006.173.13:19:00.46#ibcon#about to write, iclass 19, count 0 2006.173.13:19:00.46#ibcon#wrote, iclass 19, count 0 2006.173.13:19:00.46#ibcon#about to read 3, iclass 19, count 0 2006.173.13:19:00.49#ibcon#read 3, iclass 19, count 0 2006.173.13:19:00.49#ibcon#about to read 4, iclass 19, count 0 2006.173.13:19:00.49#ibcon#read 4, iclass 19, count 0 2006.173.13:19:00.49#ibcon#about to read 5, iclass 19, count 0 2006.173.13:19:00.49#ibcon#read 5, iclass 19, count 0 2006.173.13:19:00.49#ibcon#about to read 6, iclass 19, count 0 2006.173.13:19:00.49#ibcon#read 6, iclass 19, count 0 2006.173.13:19:00.49#ibcon#end of sib2, iclass 19, count 0 2006.173.13:19:00.49#ibcon#*after write, iclass 19, count 0 2006.173.13:19:00.49#ibcon#*before return 0, iclass 19, count 0 2006.173.13:19:00.49#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.13:19:00.49#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.13:19:00.49#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.13:19:00.49#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.13:19:00.49$vck44/vblo=6,719.99 2006.173.13:19:00.49#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.13:19:00.49#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.13:19:00.49#ibcon#ireg 17 cls_cnt 0 2006.173.13:19:00.49#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.13:19:00.49#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.13:19:00.49#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.13:19:00.49#ibcon#enter wrdev, iclass 21, count 0 2006.173.13:19:00.49#ibcon#first serial, iclass 21, count 0 2006.173.13:19:00.49#ibcon#enter sib2, iclass 21, count 0 2006.173.13:19:00.49#ibcon#flushed, iclass 21, count 0 2006.173.13:19:00.49#ibcon#about to write, iclass 21, count 0 2006.173.13:19:00.49#ibcon#wrote, iclass 21, count 0 2006.173.13:19:00.49#ibcon#about to read 3, iclass 21, count 0 2006.173.13:19:00.51#ibcon#read 3, iclass 21, count 0 2006.173.13:19:00.51#ibcon#about to read 4, iclass 21, count 0 2006.173.13:19:00.51#ibcon#read 4, iclass 21, count 0 2006.173.13:19:00.51#ibcon#about to read 5, iclass 21, count 0 2006.173.13:19:00.51#ibcon#read 5, iclass 21, count 0 2006.173.13:19:00.51#ibcon#about to read 6, iclass 21, count 0 2006.173.13:19:00.51#ibcon#read 6, iclass 21, count 0 2006.173.13:19:00.51#ibcon#end of sib2, iclass 21, count 0 2006.173.13:19:00.51#ibcon#*mode == 0, iclass 21, count 0 2006.173.13:19:00.51#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.13:19:00.51#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.13:19:00.51#ibcon#*before write, iclass 21, count 0 2006.173.13:19:00.51#ibcon#enter sib2, iclass 21, count 0 2006.173.13:19:00.51#ibcon#flushed, iclass 21, count 0 2006.173.13:19:00.51#ibcon#about to write, iclass 21, count 0 2006.173.13:19:00.51#ibcon#wrote, iclass 21, count 0 2006.173.13:19:00.51#ibcon#about to read 3, iclass 21, count 0 2006.173.13:19:00.55#ibcon#read 3, iclass 21, count 0 2006.173.13:19:00.55#ibcon#about to read 4, iclass 21, count 0 2006.173.13:19:00.55#ibcon#read 4, iclass 21, count 0 2006.173.13:19:00.55#ibcon#about to read 5, iclass 21, count 0 2006.173.13:19:00.55#ibcon#read 5, iclass 21, count 0 2006.173.13:19:00.55#ibcon#about to read 6, iclass 21, count 0 2006.173.13:19:00.55#ibcon#read 6, iclass 21, count 0 2006.173.13:19:00.55#ibcon#end of sib2, iclass 21, count 0 2006.173.13:19:00.55#ibcon#*after write, iclass 21, count 0 2006.173.13:19:00.55#ibcon#*before return 0, iclass 21, count 0 2006.173.13:19:00.55#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.13:19:00.55#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.13:19:00.55#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.13:19:00.55#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.13:19:00.55$vck44/vb=6,4 2006.173.13:19:00.55#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.13:19:00.55#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.13:19:00.55#ibcon#ireg 11 cls_cnt 2 2006.173.13:19:00.55#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.13:19:00.61#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.13:19:00.61#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.13:19:00.61#ibcon#enter wrdev, iclass 23, count 2 2006.173.13:19:00.61#ibcon#first serial, iclass 23, count 2 2006.173.13:19:00.61#ibcon#enter sib2, iclass 23, count 2 2006.173.13:19:00.61#ibcon#flushed, iclass 23, count 2 2006.173.13:19:00.61#ibcon#about to write, iclass 23, count 2 2006.173.13:19:00.61#ibcon#wrote, iclass 23, count 2 2006.173.13:19:00.61#ibcon#about to read 3, iclass 23, count 2 2006.173.13:19:00.63#ibcon#read 3, iclass 23, count 2 2006.173.13:19:00.63#ibcon#about to read 4, iclass 23, count 2 2006.173.13:19:00.63#ibcon#read 4, iclass 23, count 2 2006.173.13:19:00.63#ibcon#about to read 5, iclass 23, count 2 2006.173.13:19:00.63#ibcon#read 5, iclass 23, count 2 2006.173.13:19:00.63#ibcon#about to read 6, iclass 23, count 2 2006.173.13:19:00.63#ibcon#read 6, iclass 23, count 2 2006.173.13:19:00.63#ibcon#end of sib2, iclass 23, count 2 2006.173.13:19:00.63#ibcon#*mode == 0, iclass 23, count 2 2006.173.13:19:00.63#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.13:19:00.63#ibcon#[27=AT06-04\r\n] 2006.173.13:19:00.63#ibcon#*before write, iclass 23, count 2 2006.173.13:19:00.63#ibcon#enter sib2, iclass 23, count 2 2006.173.13:19:00.63#ibcon#flushed, iclass 23, count 2 2006.173.13:19:00.63#ibcon#about to write, iclass 23, count 2 2006.173.13:19:00.63#ibcon#wrote, iclass 23, count 2 2006.173.13:19:00.63#ibcon#about to read 3, iclass 23, count 2 2006.173.13:19:00.66#ibcon#read 3, iclass 23, count 2 2006.173.13:19:00.66#ibcon#about to read 4, iclass 23, count 2 2006.173.13:19:00.66#ibcon#read 4, iclass 23, count 2 2006.173.13:19:00.66#ibcon#about to read 5, iclass 23, count 2 2006.173.13:19:00.66#ibcon#read 5, iclass 23, count 2 2006.173.13:19:00.66#ibcon#about to read 6, iclass 23, count 2 2006.173.13:19:00.66#ibcon#read 6, iclass 23, count 2 2006.173.13:19:00.66#ibcon#end of sib2, iclass 23, count 2 2006.173.13:19:00.66#ibcon#*after write, iclass 23, count 2 2006.173.13:19:00.66#ibcon#*before return 0, iclass 23, count 2 2006.173.13:19:00.66#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.13:19:00.66#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.13:19:00.66#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.13:19:00.66#ibcon#ireg 7 cls_cnt 0 2006.173.13:19:00.66#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.13:19:00.78#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.13:19:00.78#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.13:19:00.78#ibcon#enter wrdev, iclass 23, count 0 2006.173.13:19:00.78#ibcon#first serial, iclass 23, count 0 2006.173.13:19:00.78#ibcon#enter sib2, iclass 23, count 0 2006.173.13:19:00.78#ibcon#flushed, iclass 23, count 0 2006.173.13:19:00.78#ibcon#about to write, iclass 23, count 0 2006.173.13:19:00.78#ibcon#wrote, iclass 23, count 0 2006.173.13:19:00.78#ibcon#about to read 3, iclass 23, count 0 2006.173.13:19:00.80#ibcon#read 3, iclass 23, count 0 2006.173.13:19:00.80#ibcon#about to read 4, iclass 23, count 0 2006.173.13:19:00.80#ibcon#read 4, iclass 23, count 0 2006.173.13:19:00.80#ibcon#about to read 5, iclass 23, count 0 2006.173.13:19:00.80#ibcon#read 5, iclass 23, count 0 2006.173.13:19:00.80#ibcon#about to read 6, iclass 23, count 0 2006.173.13:19:00.80#ibcon#read 6, iclass 23, count 0 2006.173.13:19:00.80#ibcon#end of sib2, iclass 23, count 0 2006.173.13:19:00.80#ibcon#*mode == 0, iclass 23, count 0 2006.173.13:19:00.80#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.13:19:00.80#ibcon#[27=USB\r\n] 2006.173.13:19:00.80#ibcon#*before write, iclass 23, count 0 2006.173.13:19:00.80#ibcon#enter sib2, iclass 23, count 0 2006.173.13:19:00.80#ibcon#flushed, iclass 23, count 0 2006.173.13:19:00.80#ibcon#about to write, iclass 23, count 0 2006.173.13:19:00.80#ibcon#wrote, iclass 23, count 0 2006.173.13:19:00.80#ibcon#about to read 3, iclass 23, count 0 2006.173.13:19:00.83#ibcon#read 3, iclass 23, count 0 2006.173.13:19:00.83#ibcon#about to read 4, iclass 23, count 0 2006.173.13:19:00.83#ibcon#read 4, iclass 23, count 0 2006.173.13:19:00.83#ibcon#about to read 5, iclass 23, count 0 2006.173.13:19:00.83#ibcon#read 5, iclass 23, count 0 2006.173.13:19:00.83#ibcon#about to read 6, iclass 23, count 0 2006.173.13:19:00.83#ibcon#read 6, iclass 23, count 0 2006.173.13:19:00.83#ibcon#end of sib2, iclass 23, count 0 2006.173.13:19:00.83#ibcon#*after write, iclass 23, count 0 2006.173.13:19:00.83#ibcon#*before return 0, iclass 23, count 0 2006.173.13:19:00.83#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.13:19:00.83#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.13:19:00.83#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.13:19:00.83#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.13:19:00.83$vck44/vblo=7,734.99 2006.173.13:19:00.83#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.13:19:00.83#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.13:19:00.83#ibcon#ireg 17 cls_cnt 0 2006.173.13:19:00.83#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.13:19:00.83#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.13:19:00.83#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.13:19:00.83#ibcon#enter wrdev, iclass 25, count 0 2006.173.13:19:00.83#ibcon#first serial, iclass 25, count 0 2006.173.13:19:00.83#ibcon#enter sib2, iclass 25, count 0 2006.173.13:19:00.83#ibcon#flushed, iclass 25, count 0 2006.173.13:19:00.83#ibcon#about to write, iclass 25, count 0 2006.173.13:19:00.83#ibcon#wrote, iclass 25, count 0 2006.173.13:19:00.83#ibcon#about to read 3, iclass 25, count 0 2006.173.13:19:00.85#ibcon#read 3, iclass 25, count 0 2006.173.13:19:00.85#ibcon#about to read 4, iclass 25, count 0 2006.173.13:19:00.85#ibcon#read 4, iclass 25, count 0 2006.173.13:19:00.85#ibcon#about to read 5, iclass 25, count 0 2006.173.13:19:00.85#ibcon#read 5, iclass 25, count 0 2006.173.13:19:00.85#ibcon#about to read 6, iclass 25, count 0 2006.173.13:19:00.85#ibcon#read 6, iclass 25, count 0 2006.173.13:19:00.85#ibcon#end of sib2, iclass 25, count 0 2006.173.13:19:00.85#ibcon#*mode == 0, iclass 25, count 0 2006.173.13:19:00.85#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.13:19:00.85#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.13:19:00.85#ibcon#*before write, iclass 25, count 0 2006.173.13:19:00.85#ibcon#enter sib2, iclass 25, count 0 2006.173.13:19:00.85#ibcon#flushed, iclass 25, count 0 2006.173.13:19:00.85#ibcon#about to write, iclass 25, count 0 2006.173.13:19:00.85#ibcon#wrote, iclass 25, count 0 2006.173.13:19:00.85#ibcon#about to read 3, iclass 25, count 0 2006.173.13:19:00.89#ibcon#read 3, iclass 25, count 0 2006.173.13:19:00.89#ibcon#about to read 4, iclass 25, count 0 2006.173.13:19:00.89#ibcon#read 4, iclass 25, count 0 2006.173.13:19:00.89#ibcon#about to read 5, iclass 25, count 0 2006.173.13:19:00.89#ibcon#read 5, iclass 25, count 0 2006.173.13:19:00.89#ibcon#about to read 6, iclass 25, count 0 2006.173.13:19:00.89#ibcon#read 6, iclass 25, count 0 2006.173.13:19:00.89#ibcon#end of sib2, iclass 25, count 0 2006.173.13:19:00.89#ibcon#*after write, iclass 25, count 0 2006.173.13:19:00.89#ibcon#*before return 0, iclass 25, count 0 2006.173.13:19:00.89#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.13:19:00.89#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.13:19:00.89#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.13:19:00.89#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.13:19:00.89$vck44/vb=7,4 2006.173.13:19:00.89#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.13:19:00.89#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.13:19:00.89#ibcon#ireg 11 cls_cnt 2 2006.173.13:19:00.89#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.13:19:00.95#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.13:19:00.95#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.13:19:00.95#ibcon#enter wrdev, iclass 27, count 2 2006.173.13:19:00.95#ibcon#first serial, iclass 27, count 2 2006.173.13:19:00.95#ibcon#enter sib2, iclass 27, count 2 2006.173.13:19:00.95#ibcon#flushed, iclass 27, count 2 2006.173.13:19:00.95#ibcon#about to write, iclass 27, count 2 2006.173.13:19:00.95#ibcon#wrote, iclass 27, count 2 2006.173.13:19:00.95#ibcon#about to read 3, iclass 27, count 2 2006.173.13:19:00.97#ibcon#read 3, iclass 27, count 2 2006.173.13:19:00.97#ibcon#about to read 4, iclass 27, count 2 2006.173.13:19:00.97#ibcon#read 4, iclass 27, count 2 2006.173.13:19:00.97#ibcon#about to read 5, iclass 27, count 2 2006.173.13:19:00.97#ibcon#read 5, iclass 27, count 2 2006.173.13:19:00.97#ibcon#about to read 6, iclass 27, count 2 2006.173.13:19:00.97#ibcon#read 6, iclass 27, count 2 2006.173.13:19:00.97#ibcon#end of sib2, iclass 27, count 2 2006.173.13:19:00.97#ibcon#*mode == 0, iclass 27, count 2 2006.173.13:19:00.97#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.13:19:00.97#ibcon#[27=AT07-04\r\n] 2006.173.13:19:00.97#ibcon#*before write, iclass 27, count 2 2006.173.13:19:00.97#ibcon#enter sib2, iclass 27, count 2 2006.173.13:19:00.97#ibcon#flushed, iclass 27, count 2 2006.173.13:19:00.97#ibcon#about to write, iclass 27, count 2 2006.173.13:19:00.97#ibcon#wrote, iclass 27, count 2 2006.173.13:19:00.97#ibcon#about to read 3, iclass 27, count 2 2006.173.13:19:01.00#ibcon#read 3, iclass 27, count 2 2006.173.13:19:01.00#ibcon#about to read 4, iclass 27, count 2 2006.173.13:19:01.00#ibcon#read 4, iclass 27, count 2 2006.173.13:19:01.00#ibcon#about to read 5, iclass 27, count 2 2006.173.13:19:01.00#ibcon#read 5, iclass 27, count 2 2006.173.13:19:01.00#ibcon#about to read 6, iclass 27, count 2 2006.173.13:19:01.00#ibcon#read 6, iclass 27, count 2 2006.173.13:19:01.00#ibcon#end of sib2, iclass 27, count 2 2006.173.13:19:01.00#ibcon#*after write, iclass 27, count 2 2006.173.13:19:01.00#ibcon#*before return 0, iclass 27, count 2 2006.173.13:19:01.00#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.13:19:01.00#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.13:19:01.00#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.13:19:01.00#ibcon#ireg 7 cls_cnt 0 2006.173.13:19:01.00#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.13:19:01.12#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.13:19:01.12#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.13:19:01.12#ibcon#enter wrdev, iclass 27, count 0 2006.173.13:19:01.12#ibcon#first serial, iclass 27, count 0 2006.173.13:19:01.12#ibcon#enter sib2, iclass 27, count 0 2006.173.13:19:01.12#ibcon#flushed, iclass 27, count 0 2006.173.13:19:01.12#ibcon#about to write, iclass 27, count 0 2006.173.13:19:01.12#ibcon#wrote, iclass 27, count 0 2006.173.13:19:01.12#ibcon#about to read 3, iclass 27, count 0 2006.173.13:19:01.14#ibcon#read 3, iclass 27, count 0 2006.173.13:19:01.14#ibcon#about to read 4, iclass 27, count 0 2006.173.13:19:01.14#ibcon#read 4, iclass 27, count 0 2006.173.13:19:01.14#ibcon#about to read 5, iclass 27, count 0 2006.173.13:19:01.14#ibcon#read 5, iclass 27, count 0 2006.173.13:19:01.14#ibcon#about to read 6, iclass 27, count 0 2006.173.13:19:01.14#ibcon#read 6, iclass 27, count 0 2006.173.13:19:01.14#ibcon#end of sib2, iclass 27, count 0 2006.173.13:19:01.14#ibcon#*mode == 0, iclass 27, count 0 2006.173.13:19:01.14#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.13:19:01.14#ibcon#[27=USB\r\n] 2006.173.13:19:01.14#ibcon#*before write, iclass 27, count 0 2006.173.13:19:01.14#ibcon#enter sib2, iclass 27, count 0 2006.173.13:19:01.14#ibcon#flushed, iclass 27, count 0 2006.173.13:19:01.14#ibcon#about to write, iclass 27, count 0 2006.173.13:19:01.14#ibcon#wrote, iclass 27, count 0 2006.173.13:19:01.14#ibcon#about to read 3, iclass 27, count 0 2006.173.13:19:01.17#ibcon#read 3, iclass 27, count 0 2006.173.13:19:01.17#ibcon#about to read 4, iclass 27, count 0 2006.173.13:19:01.17#ibcon#read 4, iclass 27, count 0 2006.173.13:19:01.17#ibcon#about to read 5, iclass 27, count 0 2006.173.13:19:01.17#ibcon#read 5, iclass 27, count 0 2006.173.13:19:01.17#ibcon#about to read 6, iclass 27, count 0 2006.173.13:19:01.17#ibcon#read 6, iclass 27, count 0 2006.173.13:19:01.17#ibcon#end of sib2, iclass 27, count 0 2006.173.13:19:01.17#ibcon#*after write, iclass 27, count 0 2006.173.13:19:01.17#ibcon#*before return 0, iclass 27, count 0 2006.173.13:19:01.17#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.13:19:01.17#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.13:19:01.17#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.13:19:01.17#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.13:19:01.17$vck44/vblo=8,744.99 2006.173.13:19:01.17#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.13:19:01.17#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.13:19:01.17#ibcon#ireg 17 cls_cnt 0 2006.173.13:19:01.17#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.13:19:01.17#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.13:19:01.17#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.13:19:01.17#ibcon#enter wrdev, iclass 29, count 0 2006.173.13:19:01.17#ibcon#first serial, iclass 29, count 0 2006.173.13:19:01.17#ibcon#enter sib2, iclass 29, count 0 2006.173.13:19:01.17#ibcon#flushed, iclass 29, count 0 2006.173.13:19:01.17#ibcon#about to write, iclass 29, count 0 2006.173.13:19:01.17#ibcon#wrote, iclass 29, count 0 2006.173.13:19:01.17#ibcon#about to read 3, iclass 29, count 0 2006.173.13:19:01.19#ibcon#read 3, iclass 29, count 0 2006.173.13:19:01.19#ibcon#about to read 4, iclass 29, count 0 2006.173.13:19:01.19#ibcon#read 4, iclass 29, count 0 2006.173.13:19:01.19#ibcon#about to read 5, iclass 29, count 0 2006.173.13:19:01.19#ibcon#read 5, iclass 29, count 0 2006.173.13:19:01.19#ibcon#about to read 6, iclass 29, count 0 2006.173.13:19:01.19#ibcon#read 6, iclass 29, count 0 2006.173.13:19:01.19#ibcon#end of sib2, iclass 29, count 0 2006.173.13:19:01.19#ibcon#*mode == 0, iclass 29, count 0 2006.173.13:19:01.19#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.13:19:01.19#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.13:19:01.19#ibcon#*before write, iclass 29, count 0 2006.173.13:19:01.19#ibcon#enter sib2, iclass 29, count 0 2006.173.13:19:01.19#ibcon#flushed, iclass 29, count 0 2006.173.13:19:01.19#ibcon#about to write, iclass 29, count 0 2006.173.13:19:01.19#ibcon#wrote, iclass 29, count 0 2006.173.13:19:01.19#ibcon#about to read 3, iclass 29, count 0 2006.173.13:19:01.23#ibcon#read 3, iclass 29, count 0 2006.173.13:19:01.23#ibcon#about to read 4, iclass 29, count 0 2006.173.13:19:01.23#ibcon#read 4, iclass 29, count 0 2006.173.13:19:01.23#ibcon#about to read 5, iclass 29, count 0 2006.173.13:19:01.23#ibcon#read 5, iclass 29, count 0 2006.173.13:19:01.23#ibcon#about to read 6, iclass 29, count 0 2006.173.13:19:01.23#ibcon#read 6, iclass 29, count 0 2006.173.13:19:01.23#ibcon#end of sib2, iclass 29, count 0 2006.173.13:19:01.23#ibcon#*after write, iclass 29, count 0 2006.173.13:19:01.23#ibcon#*before return 0, iclass 29, count 0 2006.173.13:19:01.23#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.13:19:01.23#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.13:19:01.23#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.13:19:01.23#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.13:19:01.23$vck44/vb=8,4 2006.173.13:19:01.23#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.13:19:01.23#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.13:19:01.23#ibcon#ireg 11 cls_cnt 2 2006.173.13:19:01.23#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.13:19:01.29#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.13:19:01.29#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.13:19:01.29#ibcon#enter wrdev, iclass 31, count 2 2006.173.13:19:01.29#ibcon#first serial, iclass 31, count 2 2006.173.13:19:01.29#ibcon#enter sib2, iclass 31, count 2 2006.173.13:19:01.29#ibcon#flushed, iclass 31, count 2 2006.173.13:19:01.29#ibcon#about to write, iclass 31, count 2 2006.173.13:19:01.29#ibcon#wrote, iclass 31, count 2 2006.173.13:19:01.29#ibcon#about to read 3, iclass 31, count 2 2006.173.13:19:01.31#ibcon#read 3, iclass 31, count 2 2006.173.13:19:01.31#ibcon#about to read 4, iclass 31, count 2 2006.173.13:19:01.31#ibcon#read 4, iclass 31, count 2 2006.173.13:19:01.31#ibcon#about to read 5, iclass 31, count 2 2006.173.13:19:01.31#ibcon#read 5, iclass 31, count 2 2006.173.13:19:01.31#ibcon#about to read 6, iclass 31, count 2 2006.173.13:19:01.31#ibcon#read 6, iclass 31, count 2 2006.173.13:19:01.31#ibcon#end of sib2, iclass 31, count 2 2006.173.13:19:01.31#ibcon#*mode == 0, iclass 31, count 2 2006.173.13:19:01.31#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.13:19:01.31#ibcon#[27=AT08-04\r\n] 2006.173.13:19:01.31#ibcon#*before write, iclass 31, count 2 2006.173.13:19:01.31#ibcon#enter sib2, iclass 31, count 2 2006.173.13:19:01.31#ibcon#flushed, iclass 31, count 2 2006.173.13:19:01.31#ibcon#about to write, iclass 31, count 2 2006.173.13:19:01.31#ibcon#wrote, iclass 31, count 2 2006.173.13:19:01.31#ibcon#about to read 3, iclass 31, count 2 2006.173.13:19:01.34#ibcon#read 3, iclass 31, count 2 2006.173.13:19:01.34#ibcon#about to read 4, iclass 31, count 2 2006.173.13:19:01.34#ibcon#read 4, iclass 31, count 2 2006.173.13:19:01.34#ibcon#about to read 5, iclass 31, count 2 2006.173.13:19:01.34#ibcon#read 5, iclass 31, count 2 2006.173.13:19:01.34#ibcon#about to read 6, iclass 31, count 2 2006.173.13:19:01.34#ibcon#read 6, iclass 31, count 2 2006.173.13:19:01.34#ibcon#end of sib2, iclass 31, count 2 2006.173.13:19:01.34#ibcon#*after write, iclass 31, count 2 2006.173.13:19:01.34#ibcon#*before return 0, iclass 31, count 2 2006.173.13:19:01.34#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.13:19:01.34#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.13:19:01.34#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.13:19:01.34#ibcon#ireg 7 cls_cnt 0 2006.173.13:19:01.34#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.13:19:01.46#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.13:19:01.46#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.13:19:01.46#ibcon#enter wrdev, iclass 31, count 0 2006.173.13:19:01.46#ibcon#first serial, iclass 31, count 0 2006.173.13:19:01.46#ibcon#enter sib2, iclass 31, count 0 2006.173.13:19:01.46#ibcon#flushed, iclass 31, count 0 2006.173.13:19:01.46#ibcon#about to write, iclass 31, count 0 2006.173.13:19:01.46#ibcon#wrote, iclass 31, count 0 2006.173.13:19:01.46#ibcon#about to read 3, iclass 31, count 0 2006.173.13:19:01.48#ibcon#read 3, iclass 31, count 0 2006.173.13:19:01.48#ibcon#about to read 4, iclass 31, count 0 2006.173.13:19:01.48#ibcon#read 4, iclass 31, count 0 2006.173.13:19:01.48#ibcon#about to read 5, iclass 31, count 0 2006.173.13:19:01.48#ibcon#read 5, iclass 31, count 0 2006.173.13:19:01.48#ibcon#about to read 6, iclass 31, count 0 2006.173.13:19:01.48#ibcon#read 6, iclass 31, count 0 2006.173.13:19:01.48#ibcon#end of sib2, iclass 31, count 0 2006.173.13:19:01.48#ibcon#*mode == 0, iclass 31, count 0 2006.173.13:19:01.48#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.13:19:01.48#ibcon#[27=USB\r\n] 2006.173.13:19:01.48#ibcon#*before write, iclass 31, count 0 2006.173.13:19:01.48#ibcon#enter sib2, iclass 31, count 0 2006.173.13:19:01.48#ibcon#flushed, iclass 31, count 0 2006.173.13:19:01.48#ibcon#about to write, iclass 31, count 0 2006.173.13:19:01.48#ibcon#wrote, iclass 31, count 0 2006.173.13:19:01.48#ibcon#about to read 3, iclass 31, count 0 2006.173.13:19:01.51#ibcon#read 3, iclass 31, count 0 2006.173.13:19:01.51#ibcon#about to read 4, iclass 31, count 0 2006.173.13:19:01.51#ibcon#read 4, iclass 31, count 0 2006.173.13:19:01.51#ibcon#about to read 5, iclass 31, count 0 2006.173.13:19:01.51#ibcon#read 5, iclass 31, count 0 2006.173.13:19:01.51#ibcon#about to read 6, iclass 31, count 0 2006.173.13:19:01.51#ibcon#read 6, iclass 31, count 0 2006.173.13:19:01.51#ibcon#end of sib2, iclass 31, count 0 2006.173.13:19:01.51#ibcon#*after write, iclass 31, count 0 2006.173.13:19:01.51#ibcon#*before return 0, iclass 31, count 0 2006.173.13:19:01.51#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.13:19:01.51#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.13:19:01.51#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.13:19:01.51#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.13:19:01.51$vck44/vabw=wide 2006.173.13:19:01.51#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.13:19:01.51#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.13:19:01.51#ibcon#ireg 8 cls_cnt 0 2006.173.13:19:01.51#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.13:19:01.51#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.13:19:01.51#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.13:19:01.51#ibcon#enter wrdev, iclass 33, count 0 2006.173.13:19:01.51#ibcon#first serial, iclass 33, count 0 2006.173.13:19:01.51#ibcon#enter sib2, iclass 33, count 0 2006.173.13:19:01.51#ibcon#flushed, iclass 33, count 0 2006.173.13:19:01.51#ibcon#about to write, iclass 33, count 0 2006.173.13:19:01.51#ibcon#wrote, iclass 33, count 0 2006.173.13:19:01.51#ibcon#about to read 3, iclass 33, count 0 2006.173.13:19:01.53#ibcon#read 3, iclass 33, count 0 2006.173.13:19:01.53#ibcon#about to read 4, iclass 33, count 0 2006.173.13:19:01.53#ibcon#read 4, iclass 33, count 0 2006.173.13:19:01.53#ibcon#about to read 5, iclass 33, count 0 2006.173.13:19:01.53#ibcon#read 5, iclass 33, count 0 2006.173.13:19:01.53#ibcon#about to read 6, iclass 33, count 0 2006.173.13:19:01.53#ibcon#read 6, iclass 33, count 0 2006.173.13:19:01.53#ibcon#end of sib2, iclass 33, count 0 2006.173.13:19:01.53#ibcon#*mode == 0, iclass 33, count 0 2006.173.13:19:01.53#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.13:19:01.53#ibcon#[25=BW32\r\n] 2006.173.13:19:01.53#ibcon#*before write, iclass 33, count 0 2006.173.13:19:01.53#ibcon#enter sib2, iclass 33, count 0 2006.173.13:19:01.53#ibcon#flushed, iclass 33, count 0 2006.173.13:19:01.53#ibcon#about to write, iclass 33, count 0 2006.173.13:19:01.53#ibcon#wrote, iclass 33, count 0 2006.173.13:19:01.53#ibcon#about to read 3, iclass 33, count 0 2006.173.13:19:01.56#ibcon#read 3, iclass 33, count 0 2006.173.13:19:01.56#ibcon#about to read 4, iclass 33, count 0 2006.173.13:19:01.56#ibcon#read 4, iclass 33, count 0 2006.173.13:19:01.56#ibcon#about to read 5, iclass 33, count 0 2006.173.13:19:01.56#ibcon#read 5, iclass 33, count 0 2006.173.13:19:01.56#ibcon#about to read 6, iclass 33, count 0 2006.173.13:19:01.56#ibcon#read 6, iclass 33, count 0 2006.173.13:19:01.56#ibcon#end of sib2, iclass 33, count 0 2006.173.13:19:01.56#ibcon#*after write, iclass 33, count 0 2006.173.13:19:01.56#ibcon#*before return 0, iclass 33, count 0 2006.173.13:19:01.56#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.13:19:01.56#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.13:19:01.56#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.13:19:01.56#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.13:19:01.56$vck44/vbbw=wide 2006.173.13:19:01.56#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.13:19:01.56#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.13:19:01.56#ibcon#ireg 8 cls_cnt 0 2006.173.13:19:01.56#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.13:19:01.63#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.13:19:01.63#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.13:19:01.63#ibcon#enter wrdev, iclass 35, count 0 2006.173.13:19:01.63#ibcon#first serial, iclass 35, count 0 2006.173.13:19:01.63#ibcon#enter sib2, iclass 35, count 0 2006.173.13:19:01.63#ibcon#flushed, iclass 35, count 0 2006.173.13:19:01.63#ibcon#about to write, iclass 35, count 0 2006.173.13:19:01.63#ibcon#wrote, iclass 35, count 0 2006.173.13:19:01.63#ibcon#about to read 3, iclass 35, count 0 2006.173.13:19:01.65#ibcon#read 3, iclass 35, count 0 2006.173.13:19:01.65#ibcon#about to read 4, iclass 35, count 0 2006.173.13:19:01.65#ibcon#read 4, iclass 35, count 0 2006.173.13:19:01.65#ibcon#about to read 5, iclass 35, count 0 2006.173.13:19:01.65#ibcon#read 5, iclass 35, count 0 2006.173.13:19:01.65#ibcon#about to read 6, iclass 35, count 0 2006.173.13:19:01.65#ibcon#read 6, iclass 35, count 0 2006.173.13:19:01.65#ibcon#end of sib2, iclass 35, count 0 2006.173.13:19:01.65#ibcon#*mode == 0, iclass 35, count 0 2006.173.13:19:01.65#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.13:19:01.65#ibcon#[27=BW32\r\n] 2006.173.13:19:01.65#ibcon#*before write, iclass 35, count 0 2006.173.13:19:01.65#ibcon#enter sib2, iclass 35, count 0 2006.173.13:19:01.65#ibcon#flushed, iclass 35, count 0 2006.173.13:19:01.65#ibcon#about to write, iclass 35, count 0 2006.173.13:19:01.65#ibcon#wrote, iclass 35, count 0 2006.173.13:19:01.65#ibcon#about to read 3, iclass 35, count 0 2006.173.13:19:01.68#ibcon#read 3, iclass 35, count 0 2006.173.13:19:01.68#ibcon#about to read 4, iclass 35, count 0 2006.173.13:19:01.68#ibcon#read 4, iclass 35, count 0 2006.173.13:19:01.68#ibcon#about to read 5, iclass 35, count 0 2006.173.13:19:01.68#ibcon#read 5, iclass 35, count 0 2006.173.13:19:01.68#ibcon#about to read 6, iclass 35, count 0 2006.173.13:19:01.68#ibcon#read 6, iclass 35, count 0 2006.173.13:19:01.68#ibcon#end of sib2, iclass 35, count 0 2006.173.13:19:01.68#ibcon#*after write, iclass 35, count 0 2006.173.13:19:01.68#ibcon#*before return 0, iclass 35, count 0 2006.173.13:19:01.68#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.13:19:01.68#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.13:19:01.68#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.13:19:01.68#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.13:19:01.68$setupk4/ifdk4 2006.173.13:19:01.68$ifdk4/lo= 2006.173.13:19:01.68$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.13:19:01.68$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.13:19:01.68$ifdk4/patch= 2006.173.13:19:01.68$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.13:19:01.68$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.13:19:01.68$setupk4/!*+20s 2006.173.13:19:07.50#abcon#<5=/06 0.3 0.7 22.07 981004.1\r\n> 2006.173.13:19:07.52#abcon#{5=INTERFACE CLEAR} 2006.173.13:19:07.58#abcon#[5=S1D000X0/0*\r\n] 2006.173.13:19:16.19$setupk4/"tpicd 2006.173.13:19:16.19$setupk4/echo=off 2006.173.13:19:16.19$setupk4/xlog=off 2006.173.13:19:16.19:!2006.173.13:20:19 2006.173.13:19:26.14#trakl#Source acquired 2006.173.13:19:27.14#flagr#flagr/antenna,acquired 2006.173.13:20:19.00:preob 2006.173.13:20:19.13/onsource/TRACKING 2006.173.13:20:19.13:!2006.173.13:20:29 2006.173.13:20:29.00:"tape 2006.173.13:20:29.00:"st=record 2006.173.13:20:29.00:data_valid=on 2006.173.13:20:29.00:midob 2006.173.13:20:30.13/onsource/TRACKING 2006.173.13:20:30.13/wx/22.06,1004.1,98 2006.173.13:20:30.20/cable/+6.5052E-03 2006.173.13:20:31.29/va/01,07,usb,yes,53,57 2006.173.13:20:31.29/va/02,06,usb,yes,53,54 2006.173.13:20:31.29/va/03,05,usb,yes,66,69 2006.173.13:20:31.29/va/04,06,usb,yes,54,57 2006.173.13:20:31.29/va/05,04,usb,yes,43,44 2006.173.13:20:31.29/va/06,03,usb,yes,60,60 2006.173.13:20:31.29/va/07,04,usb,yes,49,51 2006.173.13:20:31.29/va/08,04,usb,yes,42,50 2006.173.13:20:31.52/valo/01,524.99,yes,locked 2006.173.13:20:31.52/valo/02,534.99,yes,locked 2006.173.13:20:31.52/valo/03,564.99,yes,locked 2006.173.13:20:31.52/valo/04,624.99,yes,locked 2006.173.13:20:31.52/valo/05,734.99,yes,locked 2006.173.13:20:31.52/valo/06,814.99,yes,locked 2006.173.13:20:31.52/valo/07,864.99,yes,locked 2006.173.13:20:31.52/valo/08,884.99,yes,locked 2006.173.13:20:32.61/vb/01,04,usb,yes,30,28 2006.173.13:20:32.61/vb/02,04,usb,yes,32,32 2006.173.13:20:32.61/vb/03,04,usb,yes,29,32 2006.173.13:20:32.61/vb/04,04,usb,yes,34,32 2006.173.13:20:32.61/vb/05,04,usb,yes,26,29 2006.173.13:20:32.61/vb/06,04,usb,yes,31,27 2006.173.13:20:32.61/vb/07,04,usb,yes,30,30 2006.173.13:20:32.61/vb/08,04,usb,yes,28,31 2006.173.13:20:32.85/vblo/01,629.99,yes,locked 2006.173.13:20:32.85/vblo/02,634.99,yes,locked 2006.173.13:20:32.85/vblo/03,649.99,yes,locked 2006.173.13:20:32.85/vblo/04,679.99,yes,locked 2006.173.13:20:32.85/vblo/05,709.99,yes,locked 2006.173.13:20:32.85/vblo/06,719.99,yes,locked 2006.173.13:20:32.85/vblo/07,734.99,yes,locked 2006.173.13:20:32.85/vblo/08,744.99,yes,locked 2006.173.13:20:33.00/vabw/8 2006.173.13:20:33.15/vbbw/8 2006.173.13:20:33.24/xfe/off,on,15.2 2006.173.13:20:33.64/ifatt/23,28,28,28 2006.173.13:20:34.08/fmout-gps/S +3.83E-07 2006.173.13:20:34.12:!2006.173.13:32:19 2006.173.13:32:19.02:data_valid=off 2006.173.13:32:19.02:"et 2006.173.13:32:19.02:!+3s 2006.173.13:32:22.05:"tape 2006.173.13:32:22.06:postob 2006.173.13:32:22.23/cable/+6.5048E-03 2006.173.13:32:22.24/wx/21.97,1003.9,100 2006.173.13:32:22.29/fmout-gps/S +3.81E-07 2006.173.13:32:22.30:scan_name=173-1334,jd0606,40 2006.173.13:32:22.30:source=3c454.3,225357.75,160853.6,2000.0,cw 2006.173.13:32:23.15#flagr#flagr/antenna,new-source 2006.173.13:32:23.15:checkk5 2006.173.13:32:23.57/chk_autoobs//k5ts1/ autoobs is running! 2006.173.13:32:23.96/chk_autoobs//k5ts2/ autoobs is running! 2006.173.13:32:24.39/chk_autoobs//k5ts3/ autoobs is running! 2006.173.13:32:24.79/chk_autoobs//k5ts4/ autoobs is running! 2006.173.13:32:25.47/chk_obsdata//k5ts1/T1731320??a.dat file size is correct (nominal:2840MB, actual:2836MB). 2006.173.13:32:26.18/chk_obsdata//k5ts2/T1731320??b.dat file size is correct (nominal:2840MB, actual:2836MB). 2006.173.13:32:26.85/chk_obsdata//k5ts3/T1731320??c.dat file size is correct (nominal:2840MB, actual:2836MB). 2006.173.13:32:27.56/chk_obsdata//k5ts4/T1731320??d.dat file size is correct (nominal:2840MB, actual:2836MB). 2006.173.13:32:28.30/k5log//k5ts1_log_newline 2006.173.13:32:29.02/k5log//k5ts2_log_newline 2006.173.13:32:29.73/k5log//k5ts3_log_newline 2006.173.13:32:30.45/k5log//k5ts4_log_newline 2006.173.13:32:30.48/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.13:32:30.48:setupk4=1 2006.173.13:32:30.48$setupk4/echo=on 2006.173.13:32:30.48$setupk4/pcalon 2006.173.13:32:30.48$pcalon/"no phase cal control is implemented here 2006.173.13:32:30.48$setupk4/"tpicd=stop 2006.173.13:32:30.48$setupk4/"rec=synch_on 2006.173.13:32:30.48$setupk4/"rec_mode=128 2006.173.13:32:30.48$setupk4/!* 2006.173.13:32:30.48$setupk4/recpk4 2006.173.13:32:30.48$recpk4/recpatch= 2006.173.13:32:30.48$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.13:32:30.48$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.13:32:30.48$setupk4/vck44 2006.173.13:32:30.48$vck44/valo=1,524.99 2006.173.13:32:30.48#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.13:32:30.48#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.13:32:30.48#ibcon#ireg 17 cls_cnt 0 2006.173.13:32:30.48#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.13:32:30.48#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.13:32:30.48#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.13:32:30.48#ibcon#enter wrdev, iclass 32, count 0 2006.173.13:32:30.48#ibcon#first serial, iclass 32, count 0 2006.173.13:32:30.48#ibcon#enter sib2, iclass 32, count 0 2006.173.13:32:30.48#ibcon#flushed, iclass 32, count 0 2006.173.13:32:30.48#ibcon#about to write, iclass 32, count 0 2006.173.13:32:30.48#ibcon#wrote, iclass 32, count 0 2006.173.13:32:30.48#ibcon#about to read 3, iclass 32, count 0 2006.173.13:32:30.49#ibcon#read 3, iclass 32, count 0 2006.173.13:32:30.49#ibcon#about to read 4, iclass 32, count 0 2006.173.13:32:30.49#ibcon#read 4, iclass 32, count 0 2006.173.13:32:30.49#ibcon#about to read 5, iclass 32, count 0 2006.173.13:32:30.49#ibcon#read 5, iclass 32, count 0 2006.173.13:32:30.49#ibcon#about to read 6, iclass 32, count 0 2006.173.13:32:30.49#ibcon#read 6, iclass 32, count 0 2006.173.13:32:30.49#ibcon#end of sib2, iclass 32, count 0 2006.173.13:32:30.49#ibcon#*mode == 0, iclass 32, count 0 2006.173.13:32:30.49#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.13:32:30.49#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.13:32:30.49#ibcon#*before write, iclass 32, count 0 2006.173.13:32:30.49#ibcon#enter sib2, iclass 32, count 0 2006.173.13:32:30.49#ibcon#flushed, iclass 32, count 0 2006.173.13:32:30.49#ibcon#about to write, iclass 32, count 0 2006.173.13:32:30.50#ibcon#wrote, iclass 32, count 0 2006.173.13:32:30.50#ibcon#about to read 3, iclass 32, count 0 2006.173.13:32:30.54#ibcon#read 3, iclass 32, count 0 2006.173.13:32:30.54#ibcon#about to read 4, iclass 32, count 0 2006.173.13:32:30.54#ibcon#read 4, iclass 32, count 0 2006.173.13:32:30.54#ibcon#about to read 5, iclass 32, count 0 2006.173.13:32:30.54#ibcon#read 5, iclass 32, count 0 2006.173.13:32:30.54#ibcon#about to read 6, iclass 32, count 0 2006.173.13:32:30.54#ibcon#read 6, iclass 32, count 0 2006.173.13:32:30.54#ibcon#end of sib2, iclass 32, count 0 2006.173.13:32:30.54#ibcon#*after write, iclass 32, count 0 2006.173.13:32:30.54#ibcon#*before return 0, iclass 32, count 0 2006.173.13:32:30.54#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.13:32:30.54#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.13:32:30.54#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.13:32:30.54#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.13:32:30.55$vck44/va=1,7 2006.173.13:32:30.55#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.13:32:30.55#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.13:32:30.55#ibcon#ireg 11 cls_cnt 2 2006.173.13:32:30.55#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.13:32:30.55#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.13:32:30.55#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.13:32:30.55#ibcon#enter wrdev, iclass 34, count 2 2006.173.13:32:30.55#ibcon#first serial, iclass 34, count 2 2006.173.13:32:30.55#ibcon#enter sib2, iclass 34, count 2 2006.173.13:32:30.55#ibcon#flushed, iclass 34, count 2 2006.173.13:32:30.55#ibcon#about to write, iclass 34, count 2 2006.173.13:32:30.55#ibcon#wrote, iclass 34, count 2 2006.173.13:32:30.55#ibcon#about to read 3, iclass 34, count 2 2006.173.13:32:30.56#ibcon#read 3, iclass 34, count 2 2006.173.13:32:30.56#ibcon#about to read 4, iclass 34, count 2 2006.173.13:32:30.56#ibcon#read 4, iclass 34, count 2 2006.173.13:32:30.56#ibcon#about to read 5, iclass 34, count 2 2006.173.13:32:30.56#ibcon#read 5, iclass 34, count 2 2006.173.13:32:30.56#ibcon#about to read 6, iclass 34, count 2 2006.173.13:32:30.56#ibcon#read 6, iclass 34, count 2 2006.173.13:32:30.56#ibcon#end of sib2, iclass 34, count 2 2006.173.13:32:30.56#ibcon#*mode == 0, iclass 34, count 2 2006.173.13:32:30.56#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.13:32:30.56#ibcon#[25=AT01-07\r\n] 2006.173.13:32:30.56#ibcon#*before write, iclass 34, count 2 2006.173.13:32:30.56#ibcon#enter sib2, iclass 34, count 2 2006.173.13:32:30.56#ibcon#flushed, iclass 34, count 2 2006.173.13:32:30.56#ibcon#about to write, iclass 34, count 2 2006.173.13:32:30.56#ibcon#wrote, iclass 34, count 2 2006.173.13:32:30.56#ibcon#about to read 3, iclass 34, count 2 2006.173.13:32:30.59#ibcon#read 3, iclass 34, count 2 2006.173.13:32:30.59#ibcon#about to read 4, iclass 34, count 2 2006.173.13:32:30.59#ibcon#read 4, iclass 34, count 2 2006.173.13:32:30.59#ibcon#about to read 5, iclass 34, count 2 2006.173.13:32:30.59#ibcon#read 5, iclass 34, count 2 2006.173.13:32:30.59#ibcon#about to read 6, iclass 34, count 2 2006.173.13:32:30.59#ibcon#read 6, iclass 34, count 2 2006.173.13:32:30.59#ibcon#end of sib2, iclass 34, count 2 2006.173.13:32:30.59#ibcon#*after write, iclass 34, count 2 2006.173.13:32:30.59#ibcon#*before return 0, iclass 34, count 2 2006.173.13:32:30.59#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.13:32:30.59#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.13:32:30.59#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.13:32:30.59#ibcon#ireg 7 cls_cnt 0 2006.173.13:32:30.59#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.13:32:30.71#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.13:32:30.71#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.13:32:30.71#ibcon#enter wrdev, iclass 34, count 0 2006.173.13:32:30.71#ibcon#first serial, iclass 34, count 0 2006.173.13:32:30.71#ibcon#enter sib2, iclass 34, count 0 2006.173.13:32:30.71#ibcon#flushed, iclass 34, count 0 2006.173.13:32:30.71#ibcon#about to write, iclass 34, count 0 2006.173.13:32:30.71#ibcon#wrote, iclass 34, count 0 2006.173.13:32:30.71#ibcon#about to read 3, iclass 34, count 0 2006.173.13:32:30.73#ibcon#read 3, iclass 34, count 0 2006.173.13:32:30.73#ibcon#about to read 4, iclass 34, count 0 2006.173.13:32:30.73#ibcon#read 4, iclass 34, count 0 2006.173.13:32:30.73#ibcon#about to read 5, iclass 34, count 0 2006.173.13:32:30.73#ibcon#read 5, iclass 34, count 0 2006.173.13:32:30.73#ibcon#about to read 6, iclass 34, count 0 2006.173.13:32:30.73#ibcon#read 6, iclass 34, count 0 2006.173.13:32:30.73#ibcon#end of sib2, iclass 34, count 0 2006.173.13:32:30.73#ibcon#*mode == 0, iclass 34, count 0 2006.173.13:32:30.73#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.13:32:30.73#ibcon#[25=USB\r\n] 2006.173.13:32:30.73#ibcon#*before write, iclass 34, count 0 2006.173.13:32:30.73#ibcon#enter sib2, iclass 34, count 0 2006.173.13:32:30.73#ibcon#flushed, iclass 34, count 0 2006.173.13:32:30.73#ibcon#about to write, iclass 34, count 0 2006.173.13:32:30.73#ibcon#wrote, iclass 34, count 0 2006.173.13:32:30.73#ibcon#about to read 3, iclass 34, count 0 2006.173.13:32:30.76#ibcon#read 3, iclass 34, count 0 2006.173.13:32:30.76#ibcon#about to read 4, iclass 34, count 0 2006.173.13:32:30.76#ibcon#read 4, iclass 34, count 0 2006.173.13:32:30.76#ibcon#about to read 5, iclass 34, count 0 2006.173.13:32:30.76#ibcon#read 5, iclass 34, count 0 2006.173.13:32:30.76#ibcon#about to read 6, iclass 34, count 0 2006.173.13:32:30.76#ibcon#read 6, iclass 34, count 0 2006.173.13:32:30.76#ibcon#end of sib2, iclass 34, count 0 2006.173.13:32:30.76#ibcon#*after write, iclass 34, count 0 2006.173.13:32:30.76#ibcon#*before return 0, iclass 34, count 0 2006.173.13:32:30.76#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.13:32:30.76#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.13:32:30.76#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.13:32:30.76#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.13:32:30.77$vck44/valo=2,534.99 2006.173.13:32:30.77#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.13:32:30.77#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.13:32:30.77#ibcon#ireg 17 cls_cnt 0 2006.173.13:32:30.77#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.13:32:30.77#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.13:32:30.77#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.13:32:30.77#ibcon#enter wrdev, iclass 36, count 0 2006.173.13:32:30.77#ibcon#first serial, iclass 36, count 0 2006.173.13:32:30.77#ibcon#enter sib2, iclass 36, count 0 2006.173.13:32:30.77#ibcon#flushed, iclass 36, count 0 2006.173.13:32:30.77#ibcon#about to write, iclass 36, count 0 2006.173.13:32:30.77#ibcon#wrote, iclass 36, count 0 2006.173.13:32:30.77#ibcon#about to read 3, iclass 36, count 0 2006.173.13:32:30.78#ibcon#read 3, iclass 36, count 0 2006.173.13:32:30.78#ibcon#about to read 4, iclass 36, count 0 2006.173.13:32:30.78#ibcon#read 4, iclass 36, count 0 2006.173.13:32:30.78#ibcon#about to read 5, iclass 36, count 0 2006.173.13:32:30.78#ibcon#read 5, iclass 36, count 0 2006.173.13:32:30.78#ibcon#about to read 6, iclass 36, count 0 2006.173.13:32:30.78#ibcon#read 6, iclass 36, count 0 2006.173.13:32:30.78#ibcon#end of sib2, iclass 36, count 0 2006.173.13:32:30.78#ibcon#*mode == 0, iclass 36, count 0 2006.173.13:32:30.78#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.13:32:30.78#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.13:32:30.78#ibcon#*before write, iclass 36, count 0 2006.173.13:32:30.78#ibcon#enter sib2, iclass 36, count 0 2006.173.13:32:30.78#ibcon#flushed, iclass 36, count 0 2006.173.13:32:30.78#ibcon#about to write, iclass 36, count 0 2006.173.13:32:30.78#ibcon#wrote, iclass 36, count 0 2006.173.13:32:30.78#ibcon#about to read 3, iclass 36, count 0 2006.173.13:32:30.82#ibcon#read 3, iclass 36, count 0 2006.173.13:32:30.82#ibcon#about to read 4, iclass 36, count 0 2006.173.13:32:30.82#ibcon#read 4, iclass 36, count 0 2006.173.13:32:30.82#ibcon#about to read 5, iclass 36, count 0 2006.173.13:32:30.82#ibcon#read 5, iclass 36, count 0 2006.173.13:32:30.82#ibcon#about to read 6, iclass 36, count 0 2006.173.13:32:30.82#ibcon#read 6, iclass 36, count 0 2006.173.13:32:30.82#ibcon#end of sib2, iclass 36, count 0 2006.173.13:32:30.82#ibcon#*after write, iclass 36, count 0 2006.173.13:32:30.82#ibcon#*before return 0, iclass 36, count 0 2006.173.13:32:30.82#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.13:32:30.82#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.13:32:30.82#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.13:32:30.82#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.13:32:30.83$vck44/va=2,6 2006.173.13:32:30.83#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.13:32:30.83#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.13:32:30.83#ibcon#ireg 11 cls_cnt 2 2006.173.13:32:30.83#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.13:32:30.87#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.13:32:30.87#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.13:32:30.87#ibcon#enter wrdev, iclass 38, count 2 2006.173.13:32:30.87#ibcon#first serial, iclass 38, count 2 2006.173.13:32:30.87#ibcon#enter sib2, iclass 38, count 2 2006.173.13:32:30.87#ibcon#flushed, iclass 38, count 2 2006.173.13:32:30.87#ibcon#about to write, iclass 38, count 2 2006.173.13:32:30.87#ibcon#wrote, iclass 38, count 2 2006.173.13:32:30.87#ibcon#about to read 3, iclass 38, count 2 2006.173.13:32:30.89#ibcon#read 3, iclass 38, count 2 2006.173.13:32:30.89#ibcon#about to read 4, iclass 38, count 2 2006.173.13:32:30.89#ibcon#read 4, iclass 38, count 2 2006.173.13:32:30.89#ibcon#about to read 5, iclass 38, count 2 2006.173.13:32:30.89#ibcon#read 5, iclass 38, count 2 2006.173.13:32:30.89#ibcon#about to read 6, iclass 38, count 2 2006.173.13:32:30.89#ibcon#read 6, iclass 38, count 2 2006.173.13:32:30.89#ibcon#end of sib2, iclass 38, count 2 2006.173.13:32:30.89#ibcon#*mode == 0, iclass 38, count 2 2006.173.13:32:30.89#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.13:32:30.89#ibcon#[25=AT02-06\r\n] 2006.173.13:32:30.89#ibcon#*before write, iclass 38, count 2 2006.173.13:32:30.89#ibcon#enter sib2, iclass 38, count 2 2006.173.13:32:30.89#ibcon#flushed, iclass 38, count 2 2006.173.13:32:30.89#ibcon#about to write, iclass 38, count 2 2006.173.13:32:30.89#ibcon#wrote, iclass 38, count 2 2006.173.13:32:30.89#ibcon#about to read 3, iclass 38, count 2 2006.173.13:32:30.92#ibcon#read 3, iclass 38, count 2 2006.173.13:32:30.92#ibcon#about to read 4, iclass 38, count 2 2006.173.13:32:30.92#ibcon#read 4, iclass 38, count 2 2006.173.13:32:30.92#ibcon#about to read 5, iclass 38, count 2 2006.173.13:32:30.92#ibcon#read 5, iclass 38, count 2 2006.173.13:32:30.92#ibcon#about to read 6, iclass 38, count 2 2006.173.13:32:30.92#ibcon#read 6, iclass 38, count 2 2006.173.13:32:30.92#ibcon#end of sib2, iclass 38, count 2 2006.173.13:32:30.92#ibcon#*after write, iclass 38, count 2 2006.173.13:32:30.92#ibcon#*before return 0, iclass 38, count 2 2006.173.13:32:30.92#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.13:32:30.92#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.13:32:30.92#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.13:32:30.92#ibcon#ireg 7 cls_cnt 0 2006.173.13:32:30.92#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.13:32:31.04#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.13:32:31.04#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.13:32:31.04#ibcon#enter wrdev, iclass 38, count 0 2006.173.13:32:31.04#ibcon#first serial, iclass 38, count 0 2006.173.13:32:31.04#ibcon#enter sib2, iclass 38, count 0 2006.173.13:32:31.04#ibcon#flushed, iclass 38, count 0 2006.173.13:32:31.04#ibcon#about to write, iclass 38, count 0 2006.173.13:32:31.04#ibcon#wrote, iclass 38, count 0 2006.173.13:32:31.04#ibcon#about to read 3, iclass 38, count 0 2006.173.13:32:31.06#ibcon#read 3, iclass 38, count 0 2006.173.13:32:31.06#ibcon#about to read 4, iclass 38, count 0 2006.173.13:32:31.06#ibcon#read 4, iclass 38, count 0 2006.173.13:32:31.06#ibcon#about to read 5, iclass 38, count 0 2006.173.13:32:31.06#ibcon#read 5, iclass 38, count 0 2006.173.13:32:31.06#ibcon#about to read 6, iclass 38, count 0 2006.173.13:32:31.06#ibcon#read 6, iclass 38, count 0 2006.173.13:32:31.06#ibcon#end of sib2, iclass 38, count 0 2006.173.13:32:31.06#ibcon#*mode == 0, iclass 38, count 0 2006.173.13:32:31.06#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.13:32:31.06#ibcon#[25=USB\r\n] 2006.173.13:32:31.06#ibcon#*before write, iclass 38, count 0 2006.173.13:32:31.06#ibcon#enter sib2, iclass 38, count 0 2006.173.13:32:31.06#ibcon#flushed, iclass 38, count 0 2006.173.13:32:31.06#ibcon#about to write, iclass 38, count 0 2006.173.13:32:31.06#ibcon#wrote, iclass 38, count 0 2006.173.13:32:31.06#ibcon#about to read 3, iclass 38, count 0 2006.173.13:32:31.09#ibcon#read 3, iclass 38, count 0 2006.173.13:32:31.09#ibcon#about to read 4, iclass 38, count 0 2006.173.13:32:31.09#ibcon#read 4, iclass 38, count 0 2006.173.13:32:31.09#ibcon#about to read 5, iclass 38, count 0 2006.173.13:32:31.09#ibcon#read 5, iclass 38, count 0 2006.173.13:32:31.09#ibcon#about to read 6, iclass 38, count 0 2006.173.13:32:31.09#ibcon#read 6, iclass 38, count 0 2006.173.13:32:31.09#ibcon#end of sib2, iclass 38, count 0 2006.173.13:32:31.09#ibcon#*after write, iclass 38, count 0 2006.173.13:32:31.09#ibcon#*before return 0, iclass 38, count 0 2006.173.13:32:31.09#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.13:32:31.09#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.13:32:31.09#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.13:32:31.09#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.13:32:31.10$vck44/valo=3,564.99 2006.173.13:32:31.10#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.13:32:31.10#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.13:32:31.10#ibcon#ireg 17 cls_cnt 0 2006.173.13:32:31.10#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.13:32:31.10#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.13:32:31.10#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.13:32:31.10#ibcon#enter wrdev, iclass 40, count 0 2006.173.13:32:31.10#ibcon#first serial, iclass 40, count 0 2006.173.13:32:31.10#ibcon#enter sib2, iclass 40, count 0 2006.173.13:32:31.10#ibcon#flushed, iclass 40, count 0 2006.173.13:32:31.10#ibcon#about to write, iclass 40, count 0 2006.173.13:32:31.10#ibcon#wrote, iclass 40, count 0 2006.173.13:32:31.10#ibcon#about to read 3, iclass 40, count 0 2006.173.13:32:31.11#ibcon#read 3, iclass 40, count 0 2006.173.13:32:31.11#ibcon#about to read 4, iclass 40, count 0 2006.173.13:32:31.11#ibcon#read 4, iclass 40, count 0 2006.173.13:32:31.11#ibcon#about to read 5, iclass 40, count 0 2006.173.13:32:31.11#ibcon#read 5, iclass 40, count 0 2006.173.13:32:31.11#ibcon#about to read 6, iclass 40, count 0 2006.173.13:32:31.11#ibcon#read 6, iclass 40, count 0 2006.173.13:32:31.11#ibcon#end of sib2, iclass 40, count 0 2006.173.13:32:31.11#ibcon#*mode == 0, iclass 40, count 0 2006.173.13:32:31.11#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.13:32:31.11#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.13:32:31.11#ibcon#*before write, iclass 40, count 0 2006.173.13:32:31.11#ibcon#enter sib2, iclass 40, count 0 2006.173.13:32:31.11#ibcon#flushed, iclass 40, count 0 2006.173.13:32:31.11#ibcon#about to write, iclass 40, count 0 2006.173.13:32:31.11#ibcon#wrote, iclass 40, count 0 2006.173.13:32:31.11#ibcon#about to read 3, iclass 40, count 0 2006.173.13:32:31.15#ibcon#read 3, iclass 40, count 0 2006.173.13:32:31.15#ibcon#about to read 4, iclass 40, count 0 2006.173.13:32:31.15#ibcon#read 4, iclass 40, count 0 2006.173.13:32:31.15#ibcon#about to read 5, iclass 40, count 0 2006.173.13:32:31.15#ibcon#read 5, iclass 40, count 0 2006.173.13:32:31.15#ibcon#about to read 6, iclass 40, count 0 2006.173.13:32:31.15#ibcon#read 6, iclass 40, count 0 2006.173.13:32:31.15#ibcon#end of sib2, iclass 40, count 0 2006.173.13:32:31.15#ibcon#*after write, iclass 40, count 0 2006.173.13:32:31.15#ibcon#*before return 0, iclass 40, count 0 2006.173.13:32:31.15#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.13:32:31.15#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.13:32:31.15#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.13:32:31.15#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.13:32:31.16$vck44/va=3,5 2006.173.13:32:31.16#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.13:32:31.16#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.13:32:31.16#ibcon#ireg 11 cls_cnt 2 2006.173.13:32:31.16#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.13:32:31.20#abcon#<5=/04 0.6 1.3 21.971001003.9\r\n> 2006.173.13:32:31.20#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.13:32:31.20#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.13:32:31.20#ibcon#enter wrdev, iclass 4, count 2 2006.173.13:32:31.21#ibcon#first serial, iclass 4, count 2 2006.173.13:32:31.21#ibcon#enter sib2, iclass 4, count 2 2006.173.13:32:31.21#ibcon#flushed, iclass 4, count 2 2006.173.13:32:31.21#ibcon#about to write, iclass 4, count 2 2006.173.13:32:31.21#ibcon#wrote, iclass 4, count 2 2006.173.13:32:31.21#ibcon#about to read 3, iclass 4, count 2 2006.173.13:32:31.22#ibcon#read 3, iclass 4, count 2 2006.173.13:32:31.22#ibcon#about to read 4, iclass 4, count 2 2006.173.13:32:31.22#ibcon#read 4, iclass 4, count 2 2006.173.13:32:31.22#ibcon#about to read 5, iclass 4, count 2 2006.173.13:32:31.22#ibcon#read 5, iclass 4, count 2 2006.173.13:32:31.22#ibcon#about to read 6, iclass 4, count 2 2006.173.13:32:31.22#ibcon#read 6, iclass 4, count 2 2006.173.13:32:31.22#ibcon#end of sib2, iclass 4, count 2 2006.173.13:32:31.22#ibcon#*mode == 0, iclass 4, count 2 2006.173.13:32:31.22#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.13:32:31.22#ibcon#[25=AT03-05\r\n] 2006.173.13:32:31.22#ibcon#*before write, iclass 4, count 2 2006.173.13:32:31.22#ibcon#enter sib2, iclass 4, count 2 2006.173.13:32:31.22#ibcon#flushed, iclass 4, count 2 2006.173.13:32:31.22#ibcon#about to write, iclass 4, count 2 2006.173.13:32:31.22#ibcon#wrote, iclass 4, count 2 2006.173.13:32:31.22#ibcon#about to read 3, iclass 4, count 2 2006.173.13:32:31.22#abcon#{5=INTERFACE CLEAR} 2006.173.13:32:31.25#ibcon#read 3, iclass 4, count 2 2006.173.13:32:31.25#ibcon#about to read 4, iclass 4, count 2 2006.173.13:32:31.25#ibcon#read 4, iclass 4, count 2 2006.173.13:32:31.25#ibcon#about to read 5, iclass 4, count 2 2006.173.13:32:31.25#ibcon#read 5, iclass 4, count 2 2006.173.13:32:31.25#ibcon#about to read 6, iclass 4, count 2 2006.173.13:32:31.25#ibcon#read 6, iclass 4, count 2 2006.173.13:32:31.25#ibcon#end of sib2, iclass 4, count 2 2006.173.13:32:31.25#ibcon#*after write, iclass 4, count 2 2006.173.13:32:31.25#ibcon#*before return 0, iclass 4, count 2 2006.173.13:32:31.25#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.13:32:31.25#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.13:32:31.25#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.13:32:31.25#ibcon#ireg 7 cls_cnt 0 2006.173.13:32:31.25#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.13:32:31.28#abcon#[5=S1D000X0/0*\r\n] 2006.173.13:32:31.37#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.13:32:31.37#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.13:32:31.37#ibcon#enter wrdev, iclass 4, count 0 2006.173.13:32:31.37#ibcon#first serial, iclass 4, count 0 2006.173.13:32:31.37#ibcon#enter sib2, iclass 4, count 0 2006.173.13:32:31.37#ibcon#flushed, iclass 4, count 0 2006.173.13:32:31.37#ibcon#about to write, iclass 4, count 0 2006.173.13:32:31.37#ibcon#wrote, iclass 4, count 0 2006.173.13:32:31.37#ibcon#about to read 3, iclass 4, count 0 2006.173.13:32:31.39#ibcon#read 3, iclass 4, count 0 2006.173.13:32:31.39#ibcon#about to read 4, iclass 4, count 0 2006.173.13:32:31.39#ibcon#read 4, iclass 4, count 0 2006.173.13:32:31.39#ibcon#about to read 5, iclass 4, count 0 2006.173.13:32:31.39#ibcon#read 5, iclass 4, count 0 2006.173.13:32:31.39#ibcon#about to read 6, iclass 4, count 0 2006.173.13:32:31.39#ibcon#read 6, iclass 4, count 0 2006.173.13:32:31.39#ibcon#end of sib2, iclass 4, count 0 2006.173.13:32:31.39#ibcon#*mode == 0, iclass 4, count 0 2006.173.13:32:31.39#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.13:32:31.39#ibcon#[25=USB\r\n] 2006.173.13:32:31.39#ibcon#*before write, iclass 4, count 0 2006.173.13:32:31.39#ibcon#enter sib2, iclass 4, count 0 2006.173.13:32:31.39#ibcon#flushed, iclass 4, count 0 2006.173.13:32:31.39#ibcon#about to write, iclass 4, count 0 2006.173.13:32:31.39#ibcon#wrote, iclass 4, count 0 2006.173.13:32:31.39#ibcon#about to read 3, iclass 4, count 0 2006.173.13:32:31.42#ibcon#read 3, iclass 4, count 0 2006.173.13:32:31.42#ibcon#about to read 4, iclass 4, count 0 2006.173.13:32:31.42#ibcon#read 4, iclass 4, count 0 2006.173.13:32:31.42#ibcon#about to read 5, iclass 4, count 0 2006.173.13:32:31.42#ibcon#read 5, iclass 4, count 0 2006.173.13:32:31.42#ibcon#about to read 6, iclass 4, count 0 2006.173.13:32:31.42#ibcon#read 6, iclass 4, count 0 2006.173.13:32:31.42#ibcon#end of sib2, iclass 4, count 0 2006.173.13:32:31.42#ibcon#*after write, iclass 4, count 0 2006.173.13:32:31.42#ibcon#*before return 0, iclass 4, count 0 2006.173.13:32:31.42#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.13:32:31.42#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.13:32:31.42#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.13:32:31.42#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.13:32:31.43$vck44/valo=4,624.99 2006.173.13:32:31.43#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.13:32:31.43#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.13:32:31.43#ibcon#ireg 17 cls_cnt 0 2006.173.13:32:31.43#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.13:32:31.43#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.13:32:31.43#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.13:32:31.43#ibcon#enter wrdev, iclass 12, count 0 2006.173.13:32:31.43#ibcon#first serial, iclass 12, count 0 2006.173.13:32:31.43#ibcon#enter sib2, iclass 12, count 0 2006.173.13:32:31.43#ibcon#flushed, iclass 12, count 0 2006.173.13:32:31.43#ibcon#about to write, iclass 12, count 0 2006.173.13:32:31.43#ibcon#wrote, iclass 12, count 0 2006.173.13:32:31.43#ibcon#about to read 3, iclass 12, count 0 2006.173.13:32:31.44#ibcon#read 3, iclass 12, count 0 2006.173.13:32:31.44#ibcon#about to read 4, iclass 12, count 0 2006.173.13:32:31.44#ibcon#read 4, iclass 12, count 0 2006.173.13:32:31.44#ibcon#about to read 5, iclass 12, count 0 2006.173.13:32:31.44#ibcon#read 5, iclass 12, count 0 2006.173.13:32:31.44#ibcon#about to read 6, iclass 12, count 0 2006.173.13:32:31.44#ibcon#read 6, iclass 12, count 0 2006.173.13:32:31.44#ibcon#end of sib2, iclass 12, count 0 2006.173.13:32:31.44#ibcon#*mode == 0, iclass 12, count 0 2006.173.13:32:31.44#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.13:32:31.44#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.13:32:31.44#ibcon#*before write, iclass 12, count 0 2006.173.13:32:31.44#ibcon#enter sib2, iclass 12, count 0 2006.173.13:32:31.44#ibcon#flushed, iclass 12, count 0 2006.173.13:32:31.44#ibcon#about to write, iclass 12, count 0 2006.173.13:32:31.44#ibcon#wrote, iclass 12, count 0 2006.173.13:32:31.44#ibcon#about to read 3, iclass 12, count 0 2006.173.13:32:31.48#ibcon#read 3, iclass 12, count 0 2006.173.13:32:31.48#ibcon#about to read 4, iclass 12, count 0 2006.173.13:32:31.48#ibcon#read 4, iclass 12, count 0 2006.173.13:32:31.48#ibcon#about to read 5, iclass 12, count 0 2006.173.13:32:31.48#ibcon#read 5, iclass 12, count 0 2006.173.13:32:31.48#ibcon#about to read 6, iclass 12, count 0 2006.173.13:32:31.48#ibcon#read 6, iclass 12, count 0 2006.173.13:32:31.48#ibcon#end of sib2, iclass 12, count 0 2006.173.13:32:31.48#ibcon#*after write, iclass 12, count 0 2006.173.13:32:31.48#ibcon#*before return 0, iclass 12, count 0 2006.173.13:32:31.48#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.13:32:31.48#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.13:32:31.48#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.13:32:31.48#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.13:32:31.49$vck44/va=4,6 2006.173.13:32:31.49#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.13:32:31.49#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.13:32:31.49#ibcon#ireg 11 cls_cnt 2 2006.173.13:32:31.49#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.13:32:31.53#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.13:32:31.53#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.13:32:31.53#ibcon#enter wrdev, iclass 14, count 2 2006.173.13:32:31.53#ibcon#first serial, iclass 14, count 2 2006.173.13:32:31.53#ibcon#enter sib2, iclass 14, count 2 2006.173.13:32:31.53#ibcon#flushed, iclass 14, count 2 2006.173.13:32:31.53#ibcon#about to write, iclass 14, count 2 2006.173.13:32:31.53#ibcon#wrote, iclass 14, count 2 2006.173.13:32:31.53#ibcon#about to read 3, iclass 14, count 2 2006.173.13:32:31.55#ibcon#read 3, iclass 14, count 2 2006.173.13:32:31.55#ibcon#about to read 4, iclass 14, count 2 2006.173.13:32:31.55#ibcon#read 4, iclass 14, count 2 2006.173.13:32:31.55#ibcon#about to read 5, iclass 14, count 2 2006.173.13:32:31.55#ibcon#read 5, iclass 14, count 2 2006.173.13:32:31.55#ibcon#about to read 6, iclass 14, count 2 2006.173.13:32:31.55#ibcon#read 6, iclass 14, count 2 2006.173.13:32:31.55#ibcon#end of sib2, iclass 14, count 2 2006.173.13:32:31.55#ibcon#*mode == 0, iclass 14, count 2 2006.173.13:32:31.55#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.13:32:31.55#ibcon#[25=AT04-06\r\n] 2006.173.13:32:31.55#ibcon#*before write, iclass 14, count 2 2006.173.13:32:31.55#ibcon#enter sib2, iclass 14, count 2 2006.173.13:32:31.56#ibcon#flushed, iclass 14, count 2 2006.173.13:32:31.56#ibcon#about to write, iclass 14, count 2 2006.173.13:32:31.56#ibcon#wrote, iclass 14, count 2 2006.173.13:32:31.56#ibcon#about to read 3, iclass 14, count 2 2006.173.13:32:31.58#ibcon#read 3, iclass 14, count 2 2006.173.13:32:31.58#ibcon#about to read 4, iclass 14, count 2 2006.173.13:32:31.58#ibcon#read 4, iclass 14, count 2 2006.173.13:32:31.58#ibcon#about to read 5, iclass 14, count 2 2006.173.13:32:31.58#ibcon#read 5, iclass 14, count 2 2006.173.13:32:31.58#ibcon#about to read 6, iclass 14, count 2 2006.173.13:32:31.58#ibcon#read 6, iclass 14, count 2 2006.173.13:32:31.58#ibcon#end of sib2, iclass 14, count 2 2006.173.13:32:31.58#ibcon#*after write, iclass 14, count 2 2006.173.13:32:31.58#ibcon#*before return 0, iclass 14, count 2 2006.173.13:32:31.58#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.13:32:31.58#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.13:32:31.58#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.13:32:31.58#ibcon#ireg 7 cls_cnt 0 2006.173.13:32:31.59#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.13:32:31.69#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.13:32:31.69#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.13:32:31.69#ibcon#enter wrdev, iclass 14, count 0 2006.173.13:32:31.69#ibcon#first serial, iclass 14, count 0 2006.173.13:32:31.69#ibcon#enter sib2, iclass 14, count 0 2006.173.13:32:31.69#ibcon#flushed, iclass 14, count 0 2006.173.13:32:31.69#ibcon#about to write, iclass 14, count 0 2006.173.13:32:31.69#ibcon#wrote, iclass 14, count 0 2006.173.13:32:31.69#ibcon#about to read 3, iclass 14, count 0 2006.173.13:32:31.71#ibcon#read 3, iclass 14, count 0 2006.173.13:32:31.71#ibcon#about to read 4, iclass 14, count 0 2006.173.13:32:31.71#ibcon#read 4, iclass 14, count 0 2006.173.13:32:31.71#ibcon#about to read 5, iclass 14, count 0 2006.173.13:32:31.71#ibcon#read 5, iclass 14, count 0 2006.173.13:32:31.71#ibcon#about to read 6, iclass 14, count 0 2006.173.13:32:31.71#ibcon#read 6, iclass 14, count 0 2006.173.13:32:31.71#ibcon#end of sib2, iclass 14, count 0 2006.173.13:32:31.71#ibcon#*mode == 0, iclass 14, count 0 2006.173.13:32:31.71#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.13:32:31.71#ibcon#[25=USB\r\n] 2006.173.13:32:31.71#ibcon#*before write, iclass 14, count 0 2006.173.13:32:31.71#ibcon#enter sib2, iclass 14, count 0 2006.173.13:32:31.71#ibcon#flushed, iclass 14, count 0 2006.173.13:32:31.71#ibcon#about to write, iclass 14, count 0 2006.173.13:32:31.71#ibcon#wrote, iclass 14, count 0 2006.173.13:32:31.71#ibcon#about to read 3, iclass 14, count 0 2006.173.13:32:31.74#ibcon#read 3, iclass 14, count 0 2006.173.13:32:31.74#ibcon#about to read 4, iclass 14, count 0 2006.173.13:32:31.74#ibcon#read 4, iclass 14, count 0 2006.173.13:32:31.74#ibcon#about to read 5, iclass 14, count 0 2006.173.13:32:31.74#ibcon#read 5, iclass 14, count 0 2006.173.13:32:31.74#ibcon#about to read 6, iclass 14, count 0 2006.173.13:32:31.74#ibcon#read 6, iclass 14, count 0 2006.173.13:32:31.74#ibcon#end of sib2, iclass 14, count 0 2006.173.13:32:31.74#ibcon#*after write, iclass 14, count 0 2006.173.13:32:31.74#ibcon#*before return 0, iclass 14, count 0 2006.173.13:32:31.74#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.13:32:31.74#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.13:32:31.74#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.13:32:31.74#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.13:32:31.75$vck44/valo=5,734.99 2006.173.13:32:31.75#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.13:32:31.75#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.13:32:31.75#ibcon#ireg 17 cls_cnt 0 2006.173.13:32:31.75#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.13:32:31.75#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.13:32:31.75#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.13:32:31.75#ibcon#enter wrdev, iclass 16, count 0 2006.173.13:32:31.75#ibcon#first serial, iclass 16, count 0 2006.173.13:32:31.75#ibcon#enter sib2, iclass 16, count 0 2006.173.13:32:31.75#ibcon#flushed, iclass 16, count 0 2006.173.13:32:31.75#ibcon#about to write, iclass 16, count 0 2006.173.13:32:31.75#ibcon#wrote, iclass 16, count 0 2006.173.13:32:31.75#ibcon#about to read 3, iclass 16, count 0 2006.173.13:32:31.76#ibcon#read 3, iclass 16, count 0 2006.173.13:32:31.76#ibcon#about to read 4, iclass 16, count 0 2006.173.13:32:31.76#ibcon#read 4, iclass 16, count 0 2006.173.13:32:31.76#ibcon#about to read 5, iclass 16, count 0 2006.173.13:32:31.76#ibcon#read 5, iclass 16, count 0 2006.173.13:32:31.76#ibcon#about to read 6, iclass 16, count 0 2006.173.13:32:31.76#ibcon#read 6, iclass 16, count 0 2006.173.13:32:31.76#ibcon#end of sib2, iclass 16, count 0 2006.173.13:32:31.76#ibcon#*mode == 0, iclass 16, count 0 2006.173.13:32:31.76#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.13:32:31.76#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.13:32:31.76#ibcon#*before write, iclass 16, count 0 2006.173.13:32:31.76#ibcon#enter sib2, iclass 16, count 0 2006.173.13:32:31.76#ibcon#flushed, iclass 16, count 0 2006.173.13:32:31.76#ibcon#about to write, iclass 16, count 0 2006.173.13:32:31.76#ibcon#wrote, iclass 16, count 0 2006.173.13:32:31.76#ibcon#about to read 3, iclass 16, count 0 2006.173.13:32:31.80#ibcon#read 3, iclass 16, count 0 2006.173.13:32:31.80#ibcon#about to read 4, iclass 16, count 0 2006.173.13:32:31.80#ibcon#read 4, iclass 16, count 0 2006.173.13:32:31.80#ibcon#about to read 5, iclass 16, count 0 2006.173.13:32:31.80#ibcon#read 5, iclass 16, count 0 2006.173.13:32:31.80#ibcon#about to read 6, iclass 16, count 0 2006.173.13:32:31.80#ibcon#read 6, iclass 16, count 0 2006.173.13:32:31.80#ibcon#end of sib2, iclass 16, count 0 2006.173.13:32:31.80#ibcon#*after write, iclass 16, count 0 2006.173.13:32:31.80#ibcon#*before return 0, iclass 16, count 0 2006.173.13:32:31.80#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.13:32:31.80#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.13:32:31.80#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.13:32:31.80#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.13:32:31.81$vck44/va=5,4 2006.173.13:32:31.81#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.13:32:31.81#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.13:32:31.81#ibcon#ireg 11 cls_cnt 2 2006.173.13:32:31.81#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.13:32:31.85#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.13:32:31.85#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.13:32:31.85#ibcon#enter wrdev, iclass 18, count 2 2006.173.13:32:31.85#ibcon#first serial, iclass 18, count 2 2006.173.13:32:31.85#ibcon#enter sib2, iclass 18, count 2 2006.173.13:32:31.85#ibcon#flushed, iclass 18, count 2 2006.173.13:32:31.85#ibcon#about to write, iclass 18, count 2 2006.173.13:32:31.85#ibcon#wrote, iclass 18, count 2 2006.173.13:32:31.85#ibcon#about to read 3, iclass 18, count 2 2006.173.13:32:31.87#ibcon#read 3, iclass 18, count 2 2006.173.13:32:31.87#ibcon#about to read 4, iclass 18, count 2 2006.173.13:32:31.87#ibcon#read 4, iclass 18, count 2 2006.173.13:32:31.87#ibcon#about to read 5, iclass 18, count 2 2006.173.13:32:31.87#ibcon#read 5, iclass 18, count 2 2006.173.13:32:31.87#ibcon#about to read 6, iclass 18, count 2 2006.173.13:32:31.87#ibcon#read 6, iclass 18, count 2 2006.173.13:32:31.87#ibcon#end of sib2, iclass 18, count 2 2006.173.13:32:31.87#ibcon#*mode == 0, iclass 18, count 2 2006.173.13:32:31.87#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.13:32:31.87#ibcon#[25=AT05-04\r\n] 2006.173.13:32:31.87#ibcon#*before write, iclass 18, count 2 2006.173.13:32:31.87#ibcon#enter sib2, iclass 18, count 2 2006.173.13:32:31.87#ibcon#flushed, iclass 18, count 2 2006.173.13:32:31.87#ibcon#about to write, iclass 18, count 2 2006.173.13:32:31.87#ibcon#wrote, iclass 18, count 2 2006.173.13:32:31.87#ibcon#about to read 3, iclass 18, count 2 2006.173.13:32:31.90#ibcon#read 3, iclass 18, count 2 2006.173.13:32:31.90#ibcon#about to read 4, iclass 18, count 2 2006.173.13:32:31.90#ibcon#read 4, iclass 18, count 2 2006.173.13:32:31.90#ibcon#about to read 5, iclass 18, count 2 2006.173.13:32:31.90#ibcon#read 5, iclass 18, count 2 2006.173.13:32:31.90#ibcon#about to read 6, iclass 18, count 2 2006.173.13:32:31.90#ibcon#read 6, iclass 18, count 2 2006.173.13:32:31.90#ibcon#end of sib2, iclass 18, count 2 2006.173.13:32:31.90#ibcon#*after write, iclass 18, count 2 2006.173.13:32:31.90#ibcon#*before return 0, iclass 18, count 2 2006.173.13:32:31.90#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.13:32:31.90#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.13:32:31.90#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.13:32:31.90#ibcon#ireg 7 cls_cnt 0 2006.173.13:32:31.90#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.13:32:32.02#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.13:32:32.02#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.13:32:32.02#ibcon#enter wrdev, iclass 18, count 0 2006.173.13:32:32.02#ibcon#first serial, iclass 18, count 0 2006.173.13:32:32.02#ibcon#enter sib2, iclass 18, count 0 2006.173.13:32:32.02#ibcon#flushed, iclass 18, count 0 2006.173.13:32:32.02#ibcon#about to write, iclass 18, count 0 2006.173.13:32:32.02#ibcon#wrote, iclass 18, count 0 2006.173.13:32:32.02#ibcon#about to read 3, iclass 18, count 0 2006.173.13:32:32.04#ibcon#read 3, iclass 18, count 0 2006.173.13:32:32.04#ibcon#about to read 4, iclass 18, count 0 2006.173.13:32:32.04#ibcon#read 4, iclass 18, count 0 2006.173.13:32:32.04#ibcon#about to read 5, iclass 18, count 0 2006.173.13:32:32.04#ibcon#read 5, iclass 18, count 0 2006.173.13:32:32.04#ibcon#about to read 6, iclass 18, count 0 2006.173.13:32:32.04#ibcon#read 6, iclass 18, count 0 2006.173.13:32:32.04#ibcon#end of sib2, iclass 18, count 0 2006.173.13:32:32.04#ibcon#*mode == 0, iclass 18, count 0 2006.173.13:32:32.04#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.13:32:32.04#ibcon#[25=USB\r\n] 2006.173.13:32:32.04#ibcon#*before write, iclass 18, count 0 2006.173.13:32:32.04#ibcon#enter sib2, iclass 18, count 0 2006.173.13:32:32.04#ibcon#flushed, iclass 18, count 0 2006.173.13:32:32.04#ibcon#about to write, iclass 18, count 0 2006.173.13:32:32.04#ibcon#wrote, iclass 18, count 0 2006.173.13:32:32.04#ibcon#about to read 3, iclass 18, count 0 2006.173.13:32:32.07#ibcon#read 3, iclass 18, count 0 2006.173.13:32:32.07#ibcon#about to read 4, iclass 18, count 0 2006.173.13:32:32.07#ibcon#read 4, iclass 18, count 0 2006.173.13:32:32.07#ibcon#about to read 5, iclass 18, count 0 2006.173.13:32:32.07#ibcon#read 5, iclass 18, count 0 2006.173.13:32:32.07#ibcon#about to read 6, iclass 18, count 0 2006.173.13:32:32.07#ibcon#read 6, iclass 18, count 0 2006.173.13:32:32.07#ibcon#end of sib2, iclass 18, count 0 2006.173.13:32:32.07#ibcon#*after write, iclass 18, count 0 2006.173.13:32:32.07#ibcon#*before return 0, iclass 18, count 0 2006.173.13:32:32.07#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.13:32:32.07#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.13:32:32.07#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.13:32:32.07#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.13:32:32.08$vck44/valo=6,814.99 2006.173.13:32:32.08#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.13:32:32.08#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.13:32:32.08#ibcon#ireg 17 cls_cnt 0 2006.173.13:32:32.08#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.13:32:32.08#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.13:32:32.08#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.13:32:32.08#ibcon#enter wrdev, iclass 20, count 0 2006.173.13:32:32.08#ibcon#first serial, iclass 20, count 0 2006.173.13:32:32.08#ibcon#enter sib2, iclass 20, count 0 2006.173.13:32:32.08#ibcon#flushed, iclass 20, count 0 2006.173.13:32:32.08#ibcon#about to write, iclass 20, count 0 2006.173.13:32:32.08#ibcon#wrote, iclass 20, count 0 2006.173.13:32:32.08#ibcon#about to read 3, iclass 20, count 0 2006.173.13:32:32.09#ibcon#read 3, iclass 20, count 0 2006.173.13:32:32.09#ibcon#about to read 4, iclass 20, count 0 2006.173.13:32:32.09#ibcon#read 4, iclass 20, count 0 2006.173.13:32:32.09#ibcon#about to read 5, iclass 20, count 0 2006.173.13:32:32.09#ibcon#read 5, iclass 20, count 0 2006.173.13:32:32.09#ibcon#about to read 6, iclass 20, count 0 2006.173.13:32:32.09#ibcon#read 6, iclass 20, count 0 2006.173.13:32:32.09#ibcon#end of sib2, iclass 20, count 0 2006.173.13:32:32.09#ibcon#*mode == 0, iclass 20, count 0 2006.173.13:32:32.09#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.13:32:32.09#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.13:32:32.09#ibcon#*before write, iclass 20, count 0 2006.173.13:32:32.09#ibcon#enter sib2, iclass 20, count 0 2006.173.13:32:32.09#ibcon#flushed, iclass 20, count 0 2006.173.13:32:32.09#ibcon#about to write, iclass 20, count 0 2006.173.13:32:32.09#ibcon#wrote, iclass 20, count 0 2006.173.13:32:32.09#ibcon#about to read 3, iclass 20, count 0 2006.173.13:32:32.13#ibcon#read 3, iclass 20, count 0 2006.173.13:32:32.13#ibcon#about to read 4, iclass 20, count 0 2006.173.13:32:32.13#ibcon#read 4, iclass 20, count 0 2006.173.13:32:32.13#ibcon#about to read 5, iclass 20, count 0 2006.173.13:32:32.13#ibcon#read 5, iclass 20, count 0 2006.173.13:32:32.13#ibcon#about to read 6, iclass 20, count 0 2006.173.13:32:32.13#ibcon#read 6, iclass 20, count 0 2006.173.13:32:32.13#ibcon#end of sib2, iclass 20, count 0 2006.173.13:32:32.13#ibcon#*after write, iclass 20, count 0 2006.173.13:32:32.13#ibcon#*before return 0, iclass 20, count 0 2006.173.13:32:32.13#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.13:32:32.13#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.13:32:32.13#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.13:32:32.13#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.13:32:32.14$vck44/va=6,3 2006.173.13:32:32.14#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.13:32:32.14#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.13:32:32.14#ibcon#ireg 11 cls_cnt 2 2006.173.13:32:32.14#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.13:32:32.18#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.13:32:32.18#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.13:32:32.18#ibcon#enter wrdev, iclass 22, count 2 2006.173.13:32:32.18#ibcon#first serial, iclass 22, count 2 2006.173.13:32:32.18#ibcon#enter sib2, iclass 22, count 2 2006.173.13:32:32.18#ibcon#flushed, iclass 22, count 2 2006.173.13:32:32.18#ibcon#about to write, iclass 22, count 2 2006.173.13:32:32.18#ibcon#wrote, iclass 22, count 2 2006.173.13:32:32.18#ibcon#about to read 3, iclass 22, count 2 2006.173.13:32:32.20#ibcon#read 3, iclass 22, count 2 2006.173.13:32:32.20#ibcon#about to read 4, iclass 22, count 2 2006.173.13:32:32.20#ibcon#read 4, iclass 22, count 2 2006.173.13:32:32.20#ibcon#about to read 5, iclass 22, count 2 2006.173.13:32:32.20#ibcon#read 5, iclass 22, count 2 2006.173.13:32:32.20#ibcon#about to read 6, iclass 22, count 2 2006.173.13:32:32.20#ibcon#read 6, iclass 22, count 2 2006.173.13:32:32.20#ibcon#end of sib2, iclass 22, count 2 2006.173.13:32:32.20#ibcon#*mode == 0, iclass 22, count 2 2006.173.13:32:32.20#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.13:32:32.20#ibcon#[25=AT06-03\r\n] 2006.173.13:32:32.20#ibcon#*before write, iclass 22, count 2 2006.173.13:32:32.20#ibcon#enter sib2, iclass 22, count 2 2006.173.13:32:32.20#ibcon#flushed, iclass 22, count 2 2006.173.13:32:32.20#ibcon#about to write, iclass 22, count 2 2006.173.13:32:32.20#ibcon#wrote, iclass 22, count 2 2006.173.13:32:32.20#ibcon#about to read 3, iclass 22, count 2 2006.173.13:32:32.23#ibcon#read 3, iclass 22, count 2 2006.173.13:32:32.23#ibcon#about to read 4, iclass 22, count 2 2006.173.13:32:32.23#ibcon#read 4, iclass 22, count 2 2006.173.13:32:32.23#ibcon#about to read 5, iclass 22, count 2 2006.173.13:32:32.23#ibcon#read 5, iclass 22, count 2 2006.173.13:32:32.23#ibcon#about to read 6, iclass 22, count 2 2006.173.13:32:32.23#ibcon#read 6, iclass 22, count 2 2006.173.13:32:32.23#ibcon#end of sib2, iclass 22, count 2 2006.173.13:32:32.23#ibcon#*after write, iclass 22, count 2 2006.173.13:32:32.23#ibcon#*before return 0, iclass 22, count 2 2006.173.13:32:32.23#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.13:32:32.23#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.13:32:32.23#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.13:32:32.23#ibcon#ireg 7 cls_cnt 0 2006.173.13:32:32.23#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.13:32:32.35#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.13:32:32.35#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.13:32:32.35#ibcon#enter wrdev, iclass 22, count 0 2006.173.13:32:32.35#ibcon#first serial, iclass 22, count 0 2006.173.13:32:32.35#ibcon#enter sib2, iclass 22, count 0 2006.173.13:32:32.35#ibcon#flushed, iclass 22, count 0 2006.173.13:32:32.35#ibcon#about to write, iclass 22, count 0 2006.173.13:32:32.35#ibcon#wrote, iclass 22, count 0 2006.173.13:32:32.35#ibcon#about to read 3, iclass 22, count 0 2006.173.13:32:32.37#ibcon#read 3, iclass 22, count 0 2006.173.13:32:32.37#ibcon#about to read 4, iclass 22, count 0 2006.173.13:32:32.37#ibcon#read 4, iclass 22, count 0 2006.173.13:32:32.37#ibcon#about to read 5, iclass 22, count 0 2006.173.13:32:32.37#ibcon#read 5, iclass 22, count 0 2006.173.13:32:32.37#ibcon#about to read 6, iclass 22, count 0 2006.173.13:32:32.37#ibcon#read 6, iclass 22, count 0 2006.173.13:32:32.37#ibcon#end of sib2, iclass 22, count 0 2006.173.13:32:32.37#ibcon#*mode == 0, iclass 22, count 0 2006.173.13:32:32.37#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.13:32:32.37#ibcon#[25=USB\r\n] 2006.173.13:32:32.37#ibcon#*before write, iclass 22, count 0 2006.173.13:32:32.37#ibcon#enter sib2, iclass 22, count 0 2006.173.13:32:32.37#ibcon#flushed, iclass 22, count 0 2006.173.13:32:32.37#ibcon#about to write, iclass 22, count 0 2006.173.13:32:32.37#ibcon#wrote, iclass 22, count 0 2006.173.13:32:32.37#ibcon#about to read 3, iclass 22, count 0 2006.173.13:32:32.40#ibcon#read 3, iclass 22, count 0 2006.173.13:32:32.40#ibcon#about to read 4, iclass 22, count 0 2006.173.13:32:32.40#ibcon#read 4, iclass 22, count 0 2006.173.13:32:32.40#ibcon#about to read 5, iclass 22, count 0 2006.173.13:32:32.40#ibcon#read 5, iclass 22, count 0 2006.173.13:32:32.40#ibcon#about to read 6, iclass 22, count 0 2006.173.13:32:32.40#ibcon#read 6, iclass 22, count 0 2006.173.13:32:32.40#ibcon#end of sib2, iclass 22, count 0 2006.173.13:32:32.40#ibcon#*after write, iclass 22, count 0 2006.173.13:32:32.40#ibcon#*before return 0, iclass 22, count 0 2006.173.13:32:32.40#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.13:32:32.40#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.13:32:32.40#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.13:32:32.40#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.13:32:32.41$vck44/valo=7,864.99 2006.173.13:32:32.41#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.13:32:32.41#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.13:32:32.41#ibcon#ireg 17 cls_cnt 0 2006.173.13:32:32.41#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.13:32:32.41#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.13:32:32.41#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.13:32:32.41#ibcon#enter wrdev, iclass 24, count 0 2006.173.13:32:32.41#ibcon#first serial, iclass 24, count 0 2006.173.13:32:32.41#ibcon#enter sib2, iclass 24, count 0 2006.173.13:32:32.41#ibcon#flushed, iclass 24, count 0 2006.173.13:32:32.41#ibcon#about to write, iclass 24, count 0 2006.173.13:32:32.41#ibcon#wrote, iclass 24, count 0 2006.173.13:32:32.41#ibcon#about to read 3, iclass 24, count 0 2006.173.13:32:32.42#ibcon#read 3, iclass 24, count 0 2006.173.13:32:32.42#ibcon#about to read 4, iclass 24, count 0 2006.173.13:32:32.42#ibcon#read 4, iclass 24, count 0 2006.173.13:32:32.42#ibcon#about to read 5, iclass 24, count 0 2006.173.13:32:32.42#ibcon#read 5, iclass 24, count 0 2006.173.13:32:32.42#ibcon#about to read 6, iclass 24, count 0 2006.173.13:32:32.42#ibcon#read 6, iclass 24, count 0 2006.173.13:32:32.42#ibcon#end of sib2, iclass 24, count 0 2006.173.13:32:32.42#ibcon#*mode == 0, iclass 24, count 0 2006.173.13:32:32.42#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.13:32:32.42#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.13:32:32.42#ibcon#*before write, iclass 24, count 0 2006.173.13:32:32.42#ibcon#enter sib2, iclass 24, count 0 2006.173.13:32:32.42#ibcon#flushed, iclass 24, count 0 2006.173.13:32:32.42#ibcon#about to write, iclass 24, count 0 2006.173.13:32:32.42#ibcon#wrote, iclass 24, count 0 2006.173.13:32:32.42#ibcon#about to read 3, iclass 24, count 0 2006.173.13:32:32.46#ibcon#read 3, iclass 24, count 0 2006.173.13:32:32.46#ibcon#about to read 4, iclass 24, count 0 2006.173.13:32:32.46#ibcon#read 4, iclass 24, count 0 2006.173.13:32:32.46#ibcon#about to read 5, iclass 24, count 0 2006.173.13:32:32.46#ibcon#read 5, iclass 24, count 0 2006.173.13:32:32.46#ibcon#about to read 6, iclass 24, count 0 2006.173.13:32:32.46#ibcon#read 6, iclass 24, count 0 2006.173.13:32:32.46#ibcon#end of sib2, iclass 24, count 0 2006.173.13:32:32.46#ibcon#*after write, iclass 24, count 0 2006.173.13:32:32.46#ibcon#*before return 0, iclass 24, count 0 2006.173.13:32:32.46#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.13:32:32.46#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.13:32:32.46#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.13:32:32.46#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.13:32:32.47$vck44/va=7,4 2006.173.13:32:32.47#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.13:32:32.47#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.13:32:32.47#ibcon#ireg 11 cls_cnt 2 2006.173.13:32:32.47#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.13:32:32.51#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.13:32:32.51#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.13:32:32.51#ibcon#enter wrdev, iclass 26, count 2 2006.173.13:32:32.51#ibcon#first serial, iclass 26, count 2 2006.173.13:32:32.51#ibcon#enter sib2, iclass 26, count 2 2006.173.13:32:32.51#ibcon#flushed, iclass 26, count 2 2006.173.13:32:32.51#ibcon#about to write, iclass 26, count 2 2006.173.13:32:32.51#ibcon#wrote, iclass 26, count 2 2006.173.13:32:32.51#ibcon#about to read 3, iclass 26, count 2 2006.173.13:32:32.53#ibcon#read 3, iclass 26, count 2 2006.173.13:32:32.53#ibcon#about to read 4, iclass 26, count 2 2006.173.13:32:32.53#ibcon#read 4, iclass 26, count 2 2006.173.13:32:32.53#ibcon#about to read 5, iclass 26, count 2 2006.173.13:32:32.53#ibcon#read 5, iclass 26, count 2 2006.173.13:32:32.53#ibcon#about to read 6, iclass 26, count 2 2006.173.13:32:32.53#ibcon#read 6, iclass 26, count 2 2006.173.13:32:32.53#ibcon#end of sib2, iclass 26, count 2 2006.173.13:32:32.53#ibcon#*mode == 0, iclass 26, count 2 2006.173.13:32:32.53#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.13:32:32.53#ibcon#[25=AT07-04\r\n] 2006.173.13:32:32.53#ibcon#*before write, iclass 26, count 2 2006.173.13:32:32.53#ibcon#enter sib2, iclass 26, count 2 2006.173.13:32:32.53#ibcon#flushed, iclass 26, count 2 2006.173.13:32:32.53#ibcon#about to write, iclass 26, count 2 2006.173.13:32:32.53#ibcon#wrote, iclass 26, count 2 2006.173.13:32:32.53#ibcon#about to read 3, iclass 26, count 2 2006.173.13:32:32.56#ibcon#read 3, iclass 26, count 2 2006.173.13:32:32.56#ibcon#about to read 4, iclass 26, count 2 2006.173.13:32:32.56#ibcon#read 4, iclass 26, count 2 2006.173.13:32:32.56#ibcon#about to read 5, iclass 26, count 2 2006.173.13:32:32.56#ibcon#read 5, iclass 26, count 2 2006.173.13:32:32.56#ibcon#about to read 6, iclass 26, count 2 2006.173.13:32:32.56#ibcon#read 6, iclass 26, count 2 2006.173.13:32:32.56#ibcon#end of sib2, iclass 26, count 2 2006.173.13:32:32.56#ibcon#*after write, iclass 26, count 2 2006.173.13:32:32.56#ibcon#*before return 0, iclass 26, count 2 2006.173.13:32:32.56#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.13:32:32.56#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.13:32:32.56#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.13:32:32.56#ibcon#ireg 7 cls_cnt 0 2006.173.13:32:32.56#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.13:32:32.68#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.13:32:32.68#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.13:32:32.68#ibcon#enter wrdev, iclass 26, count 0 2006.173.13:32:32.68#ibcon#first serial, iclass 26, count 0 2006.173.13:32:32.68#ibcon#enter sib2, iclass 26, count 0 2006.173.13:32:32.68#ibcon#flushed, iclass 26, count 0 2006.173.13:32:32.68#ibcon#about to write, iclass 26, count 0 2006.173.13:32:32.68#ibcon#wrote, iclass 26, count 0 2006.173.13:32:32.68#ibcon#about to read 3, iclass 26, count 0 2006.173.13:32:32.70#ibcon#read 3, iclass 26, count 0 2006.173.13:32:32.70#ibcon#about to read 4, iclass 26, count 0 2006.173.13:32:32.70#ibcon#read 4, iclass 26, count 0 2006.173.13:32:32.70#ibcon#about to read 5, iclass 26, count 0 2006.173.13:32:32.70#ibcon#read 5, iclass 26, count 0 2006.173.13:32:32.70#ibcon#about to read 6, iclass 26, count 0 2006.173.13:32:32.70#ibcon#read 6, iclass 26, count 0 2006.173.13:32:32.70#ibcon#end of sib2, iclass 26, count 0 2006.173.13:32:32.70#ibcon#*mode == 0, iclass 26, count 0 2006.173.13:32:32.70#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.13:32:32.70#ibcon#[25=USB\r\n] 2006.173.13:32:32.70#ibcon#*before write, iclass 26, count 0 2006.173.13:32:32.70#ibcon#enter sib2, iclass 26, count 0 2006.173.13:32:32.70#ibcon#flushed, iclass 26, count 0 2006.173.13:32:32.70#ibcon#about to write, iclass 26, count 0 2006.173.13:32:32.70#ibcon#wrote, iclass 26, count 0 2006.173.13:32:32.70#ibcon#about to read 3, iclass 26, count 0 2006.173.13:32:32.73#ibcon#read 3, iclass 26, count 0 2006.173.13:32:32.73#ibcon#about to read 4, iclass 26, count 0 2006.173.13:32:32.73#ibcon#read 4, iclass 26, count 0 2006.173.13:32:32.73#ibcon#about to read 5, iclass 26, count 0 2006.173.13:32:32.73#ibcon#read 5, iclass 26, count 0 2006.173.13:32:32.73#ibcon#about to read 6, iclass 26, count 0 2006.173.13:32:32.73#ibcon#read 6, iclass 26, count 0 2006.173.13:32:32.73#ibcon#end of sib2, iclass 26, count 0 2006.173.13:32:32.73#ibcon#*after write, iclass 26, count 0 2006.173.13:32:32.73#ibcon#*before return 0, iclass 26, count 0 2006.173.13:32:32.73#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.13:32:32.73#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.13:32:32.73#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.13:32:32.73#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.13:32:32.74$vck44/valo=8,884.99 2006.173.13:32:32.74#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.13:32:32.74#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.13:32:32.74#ibcon#ireg 17 cls_cnt 0 2006.173.13:32:32.74#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.13:32:32.74#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.13:32:32.74#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.13:32:32.74#ibcon#enter wrdev, iclass 28, count 0 2006.173.13:32:32.74#ibcon#first serial, iclass 28, count 0 2006.173.13:32:32.74#ibcon#enter sib2, iclass 28, count 0 2006.173.13:32:32.74#ibcon#flushed, iclass 28, count 0 2006.173.13:32:32.74#ibcon#about to write, iclass 28, count 0 2006.173.13:32:32.74#ibcon#wrote, iclass 28, count 0 2006.173.13:32:32.74#ibcon#about to read 3, iclass 28, count 0 2006.173.13:32:32.75#ibcon#read 3, iclass 28, count 0 2006.173.13:32:32.75#ibcon#about to read 4, iclass 28, count 0 2006.173.13:32:32.75#ibcon#read 4, iclass 28, count 0 2006.173.13:32:32.75#ibcon#about to read 5, iclass 28, count 0 2006.173.13:32:32.75#ibcon#read 5, iclass 28, count 0 2006.173.13:32:32.75#ibcon#about to read 6, iclass 28, count 0 2006.173.13:32:32.75#ibcon#read 6, iclass 28, count 0 2006.173.13:32:32.75#ibcon#end of sib2, iclass 28, count 0 2006.173.13:32:32.75#ibcon#*mode == 0, iclass 28, count 0 2006.173.13:32:32.75#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.13:32:32.75#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.13:32:32.75#ibcon#*before write, iclass 28, count 0 2006.173.13:32:32.75#ibcon#enter sib2, iclass 28, count 0 2006.173.13:32:32.75#ibcon#flushed, iclass 28, count 0 2006.173.13:32:32.75#ibcon#about to write, iclass 28, count 0 2006.173.13:32:32.76#ibcon#wrote, iclass 28, count 0 2006.173.13:32:32.76#ibcon#about to read 3, iclass 28, count 0 2006.173.13:32:32.79#ibcon#read 3, iclass 28, count 0 2006.173.13:32:32.79#ibcon#about to read 4, iclass 28, count 0 2006.173.13:32:32.79#ibcon#read 4, iclass 28, count 0 2006.173.13:32:32.79#ibcon#about to read 5, iclass 28, count 0 2006.173.13:32:32.79#ibcon#read 5, iclass 28, count 0 2006.173.13:32:32.79#ibcon#about to read 6, iclass 28, count 0 2006.173.13:32:32.79#ibcon#read 6, iclass 28, count 0 2006.173.13:32:32.79#ibcon#end of sib2, iclass 28, count 0 2006.173.13:32:32.79#ibcon#*after write, iclass 28, count 0 2006.173.13:32:32.79#ibcon#*before return 0, iclass 28, count 0 2006.173.13:32:32.79#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.13:32:32.79#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.13:32:32.79#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.13:32:32.79#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.13:32:32.80$vck44/va=8,4 2006.173.13:32:32.80#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.13:32:32.80#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.13:32:32.80#ibcon#ireg 11 cls_cnt 2 2006.173.13:32:32.80#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.13:32:32.84#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.13:32:32.84#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.13:32:32.84#ibcon#enter wrdev, iclass 30, count 2 2006.173.13:32:32.84#ibcon#first serial, iclass 30, count 2 2006.173.13:32:32.84#ibcon#enter sib2, iclass 30, count 2 2006.173.13:32:32.84#ibcon#flushed, iclass 30, count 2 2006.173.13:32:32.84#ibcon#about to write, iclass 30, count 2 2006.173.13:32:32.84#ibcon#wrote, iclass 30, count 2 2006.173.13:32:32.84#ibcon#about to read 3, iclass 30, count 2 2006.173.13:32:32.86#ibcon#read 3, iclass 30, count 2 2006.173.13:32:32.86#ibcon#about to read 4, iclass 30, count 2 2006.173.13:32:32.86#ibcon#read 4, iclass 30, count 2 2006.173.13:32:32.86#ibcon#about to read 5, iclass 30, count 2 2006.173.13:32:32.86#ibcon#read 5, iclass 30, count 2 2006.173.13:32:32.86#ibcon#about to read 6, iclass 30, count 2 2006.173.13:32:32.86#ibcon#read 6, iclass 30, count 2 2006.173.13:32:32.86#ibcon#end of sib2, iclass 30, count 2 2006.173.13:32:32.86#ibcon#*mode == 0, iclass 30, count 2 2006.173.13:32:32.86#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.13:32:32.86#ibcon#[25=AT08-04\r\n] 2006.173.13:32:32.86#ibcon#*before write, iclass 30, count 2 2006.173.13:32:32.86#ibcon#enter sib2, iclass 30, count 2 2006.173.13:32:32.86#ibcon#flushed, iclass 30, count 2 2006.173.13:32:32.86#ibcon#about to write, iclass 30, count 2 2006.173.13:32:32.86#ibcon#wrote, iclass 30, count 2 2006.173.13:32:32.86#ibcon#about to read 3, iclass 30, count 2 2006.173.13:32:32.89#ibcon#read 3, iclass 30, count 2 2006.173.13:32:32.89#ibcon#about to read 4, iclass 30, count 2 2006.173.13:32:32.89#ibcon#read 4, iclass 30, count 2 2006.173.13:32:32.89#ibcon#about to read 5, iclass 30, count 2 2006.173.13:32:32.89#ibcon#read 5, iclass 30, count 2 2006.173.13:32:32.89#ibcon#about to read 6, iclass 30, count 2 2006.173.13:32:32.89#ibcon#read 6, iclass 30, count 2 2006.173.13:32:32.89#ibcon#end of sib2, iclass 30, count 2 2006.173.13:32:32.89#ibcon#*after write, iclass 30, count 2 2006.173.13:32:32.89#ibcon#*before return 0, iclass 30, count 2 2006.173.13:32:32.89#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.13:32:32.89#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.13:32:32.89#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.13:32:32.89#ibcon#ireg 7 cls_cnt 0 2006.173.13:32:32.89#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.13:32:33.01#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.13:32:33.01#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.13:32:33.01#ibcon#enter wrdev, iclass 30, count 0 2006.173.13:32:33.02#ibcon#first serial, iclass 30, count 0 2006.173.13:32:33.02#ibcon#enter sib2, iclass 30, count 0 2006.173.13:32:33.02#ibcon#flushed, iclass 30, count 0 2006.173.13:32:33.02#ibcon#about to write, iclass 30, count 0 2006.173.13:32:33.02#ibcon#wrote, iclass 30, count 0 2006.173.13:32:33.02#ibcon#about to read 3, iclass 30, count 0 2006.173.13:32:33.03#ibcon#read 3, iclass 30, count 0 2006.173.13:32:33.03#ibcon#about to read 4, iclass 30, count 0 2006.173.13:32:33.03#ibcon#read 4, iclass 30, count 0 2006.173.13:32:33.03#ibcon#about to read 5, iclass 30, count 0 2006.173.13:32:33.03#ibcon#read 5, iclass 30, count 0 2006.173.13:32:33.03#ibcon#about to read 6, iclass 30, count 0 2006.173.13:32:33.03#ibcon#read 6, iclass 30, count 0 2006.173.13:32:33.03#ibcon#end of sib2, iclass 30, count 0 2006.173.13:32:33.03#ibcon#*mode == 0, iclass 30, count 0 2006.173.13:32:33.03#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.13:32:33.03#ibcon#[25=USB\r\n] 2006.173.13:32:33.03#ibcon#*before write, iclass 30, count 0 2006.173.13:32:33.03#ibcon#enter sib2, iclass 30, count 0 2006.173.13:32:33.03#ibcon#flushed, iclass 30, count 0 2006.173.13:32:33.03#ibcon#about to write, iclass 30, count 0 2006.173.13:32:33.03#ibcon#wrote, iclass 30, count 0 2006.173.13:32:33.03#ibcon#about to read 3, iclass 30, count 0 2006.173.13:32:33.06#ibcon#read 3, iclass 30, count 0 2006.173.13:32:33.06#ibcon#about to read 4, iclass 30, count 0 2006.173.13:32:33.06#ibcon#read 4, iclass 30, count 0 2006.173.13:32:33.06#ibcon#about to read 5, iclass 30, count 0 2006.173.13:32:33.06#ibcon#read 5, iclass 30, count 0 2006.173.13:32:33.06#ibcon#about to read 6, iclass 30, count 0 2006.173.13:32:33.06#ibcon#read 6, iclass 30, count 0 2006.173.13:32:33.06#ibcon#end of sib2, iclass 30, count 0 2006.173.13:32:33.06#ibcon#*after write, iclass 30, count 0 2006.173.13:32:33.06#ibcon#*before return 0, iclass 30, count 0 2006.173.13:32:33.06#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.13:32:33.06#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.13:32:33.06#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.13:32:33.06#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.13:32:33.07$vck44/vblo=1,629.99 2006.173.13:32:33.07#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.13:32:33.07#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.13:32:33.07#ibcon#ireg 17 cls_cnt 0 2006.173.13:32:33.07#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.13:32:33.07#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.13:32:33.07#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.13:32:33.07#ibcon#enter wrdev, iclass 32, count 0 2006.173.13:32:33.07#ibcon#first serial, iclass 32, count 0 2006.173.13:32:33.07#ibcon#enter sib2, iclass 32, count 0 2006.173.13:32:33.07#ibcon#flushed, iclass 32, count 0 2006.173.13:32:33.07#ibcon#about to write, iclass 32, count 0 2006.173.13:32:33.07#ibcon#wrote, iclass 32, count 0 2006.173.13:32:33.07#ibcon#about to read 3, iclass 32, count 0 2006.173.13:32:33.08#ibcon#read 3, iclass 32, count 0 2006.173.13:32:33.08#ibcon#about to read 4, iclass 32, count 0 2006.173.13:32:33.08#ibcon#read 4, iclass 32, count 0 2006.173.13:32:33.08#ibcon#about to read 5, iclass 32, count 0 2006.173.13:32:33.08#ibcon#read 5, iclass 32, count 0 2006.173.13:32:33.08#ibcon#about to read 6, iclass 32, count 0 2006.173.13:32:33.08#ibcon#read 6, iclass 32, count 0 2006.173.13:32:33.08#ibcon#end of sib2, iclass 32, count 0 2006.173.13:32:33.08#ibcon#*mode == 0, iclass 32, count 0 2006.173.13:32:33.08#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.13:32:33.08#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.13:32:33.08#ibcon#*before write, iclass 32, count 0 2006.173.13:32:33.08#ibcon#enter sib2, iclass 32, count 0 2006.173.13:32:33.08#ibcon#flushed, iclass 32, count 0 2006.173.13:32:33.08#ibcon#about to write, iclass 32, count 0 2006.173.13:32:33.08#ibcon#wrote, iclass 32, count 0 2006.173.13:32:33.08#ibcon#about to read 3, iclass 32, count 0 2006.173.13:32:33.12#ibcon#read 3, iclass 32, count 0 2006.173.13:32:33.12#ibcon#about to read 4, iclass 32, count 0 2006.173.13:32:33.12#ibcon#read 4, iclass 32, count 0 2006.173.13:32:33.12#ibcon#about to read 5, iclass 32, count 0 2006.173.13:32:33.12#ibcon#read 5, iclass 32, count 0 2006.173.13:32:33.12#ibcon#about to read 6, iclass 32, count 0 2006.173.13:32:33.12#ibcon#read 6, iclass 32, count 0 2006.173.13:32:33.12#ibcon#end of sib2, iclass 32, count 0 2006.173.13:32:33.12#ibcon#*after write, iclass 32, count 0 2006.173.13:32:33.12#ibcon#*before return 0, iclass 32, count 0 2006.173.13:32:33.12#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.13:32:33.12#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.13:32:33.12#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.13:32:33.12#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.13:32:33.13$vck44/vb=1,4 2006.173.13:32:33.13#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.13:32:33.13#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.13:32:33.13#ibcon#ireg 11 cls_cnt 2 2006.173.13:32:33.13#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.13:32:33.13#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.13:32:33.13#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.13:32:33.13#ibcon#enter wrdev, iclass 34, count 2 2006.173.13:32:33.13#ibcon#first serial, iclass 34, count 2 2006.173.13:32:33.13#ibcon#enter sib2, iclass 34, count 2 2006.173.13:32:33.13#ibcon#flushed, iclass 34, count 2 2006.173.13:32:33.13#ibcon#about to write, iclass 34, count 2 2006.173.13:32:33.13#ibcon#wrote, iclass 34, count 2 2006.173.13:32:33.13#ibcon#about to read 3, iclass 34, count 2 2006.173.13:32:33.14#ibcon#read 3, iclass 34, count 2 2006.173.13:32:33.14#ibcon#about to read 4, iclass 34, count 2 2006.173.13:32:33.14#ibcon#read 4, iclass 34, count 2 2006.173.13:32:33.14#ibcon#about to read 5, iclass 34, count 2 2006.173.13:32:33.14#ibcon#read 5, iclass 34, count 2 2006.173.13:32:33.14#ibcon#about to read 6, iclass 34, count 2 2006.173.13:32:33.14#ibcon#read 6, iclass 34, count 2 2006.173.13:32:33.14#ibcon#end of sib2, iclass 34, count 2 2006.173.13:32:33.14#ibcon#*mode == 0, iclass 34, count 2 2006.173.13:32:33.14#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.13:32:33.14#ibcon#[27=AT01-04\r\n] 2006.173.13:32:33.14#ibcon#*before write, iclass 34, count 2 2006.173.13:32:33.14#ibcon#enter sib2, iclass 34, count 2 2006.173.13:32:33.14#ibcon#flushed, iclass 34, count 2 2006.173.13:32:33.14#ibcon#about to write, iclass 34, count 2 2006.173.13:32:33.14#ibcon#wrote, iclass 34, count 2 2006.173.13:32:33.14#ibcon#about to read 3, iclass 34, count 2 2006.173.13:32:33.17#ibcon#read 3, iclass 34, count 2 2006.173.13:32:33.17#ibcon#about to read 4, iclass 34, count 2 2006.173.13:32:33.17#ibcon#read 4, iclass 34, count 2 2006.173.13:32:33.17#ibcon#about to read 5, iclass 34, count 2 2006.173.13:32:33.17#ibcon#read 5, iclass 34, count 2 2006.173.13:32:33.17#ibcon#about to read 6, iclass 34, count 2 2006.173.13:32:33.17#ibcon#read 6, iclass 34, count 2 2006.173.13:32:33.17#ibcon#end of sib2, iclass 34, count 2 2006.173.13:32:33.17#ibcon#*after write, iclass 34, count 2 2006.173.13:32:33.17#ibcon#*before return 0, iclass 34, count 2 2006.173.13:32:33.17#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.13:32:33.17#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.13:32:33.17#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.13:32:33.17#ibcon#ireg 7 cls_cnt 0 2006.173.13:32:33.17#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.13:32:33.29#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.13:32:33.29#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.13:32:33.29#ibcon#enter wrdev, iclass 34, count 0 2006.173.13:32:33.29#ibcon#first serial, iclass 34, count 0 2006.173.13:32:33.29#ibcon#enter sib2, iclass 34, count 0 2006.173.13:32:33.29#ibcon#flushed, iclass 34, count 0 2006.173.13:32:33.29#ibcon#about to write, iclass 34, count 0 2006.173.13:32:33.29#ibcon#wrote, iclass 34, count 0 2006.173.13:32:33.29#ibcon#about to read 3, iclass 34, count 0 2006.173.13:32:33.31#ibcon#read 3, iclass 34, count 0 2006.173.13:32:33.31#ibcon#about to read 4, iclass 34, count 0 2006.173.13:32:33.31#ibcon#read 4, iclass 34, count 0 2006.173.13:32:33.31#ibcon#about to read 5, iclass 34, count 0 2006.173.13:32:33.31#ibcon#read 5, iclass 34, count 0 2006.173.13:32:33.31#ibcon#about to read 6, iclass 34, count 0 2006.173.13:32:33.31#ibcon#read 6, iclass 34, count 0 2006.173.13:32:33.31#ibcon#end of sib2, iclass 34, count 0 2006.173.13:32:33.31#ibcon#*mode == 0, iclass 34, count 0 2006.173.13:32:33.31#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.13:32:33.31#ibcon#[27=USB\r\n] 2006.173.13:32:33.31#ibcon#*before write, iclass 34, count 0 2006.173.13:32:33.31#ibcon#enter sib2, iclass 34, count 0 2006.173.13:32:33.31#ibcon#flushed, iclass 34, count 0 2006.173.13:32:33.31#ibcon#about to write, iclass 34, count 0 2006.173.13:32:33.31#ibcon#wrote, iclass 34, count 0 2006.173.13:32:33.31#ibcon#about to read 3, iclass 34, count 0 2006.173.13:32:33.34#ibcon#read 3, iclass 34, count 0 2006.173.13:32:33.34#ibcon#about to read 4, iclass 34, count 0 2006.173.13:32:33.34#ibcon#read 4, iclass 34, count 0 2006.173.13:32:33.34#ibcon#about to read 5, iclass 34, count 0 2006.173.13:32:33.34#ibcon#read 5, iclass 34, count 0 2006.173.13:32:33.34#ibcon#about to read 6, iclass 34, count 0 2006.173.13:32:33.34#ibcon#read 6, iclass 34, count 0 2006.173.13:32:33.34#ibcon#end of sib2, iclass 34, count 0 2006.173.13:32:33.34#ibcon#*after write, iclass 34, count 0 2006.173.13:32:33.34#ibcon#*before return 0, iclass 34, count 0 2006.173.13:32:33.34#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.13:32:33.34#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.13:32:33.34#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.13:32:33.34#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.13:32:33.35$vck44/vblo=2,634.99 2006.173.13:32:33.35#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.13:32:33.35#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.13:32:33.35#ibcon#ireg 17 cls_cnt 0 2006.173.13:32:33.35#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.13:32:33.35#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.13:32:33.35#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.13:32:33.35#ibcon#enter wrdev, iclass 36, count 0 2006.173.13:32:33.35#ibcon#first serial, iclass 36, count 0 2006.173.13:32:33.35#ibcon#enter sib2, iclass 36, count 0 2006.173.13:32:33.35#ibcon#flushed, iclass 36, count 0 2006.173.13:32:33.35#ibcon#about to write, iclass 36, count 0 2006.173.13:32:33.35#ibcon#wrote, iclass 36, count 0 2006.173.13:32:33.35#ibcon#about to read 3, iclass 36, count 0 2006.173.13:32:33.36#ibcon#read 3, iclass 36, count 0 2006.173.13:32:33.36#ibcon#about to read 4, iclass 36, count 0 2006.173.13:32:33.36#ibcon#read 4, iclass 36, count 0 2006.173.13:32:33.36#ibcon#about to read 5, iclass 36, count 0 2006.173.13:32:33.36#ibcon#read 5, iclass 36, count 0 2006.173.13:32:33.36#ibcon#about to read 6, iclass 36, count 0 2006.173.13:32:33.36#ibcon#read 6, iclass 36, count 0 2006.173.13:32:33.36#ibcon#end of sib2, iclass 36, count 0 2006.173.13:32:33.36#ibcon#*mode == 0, iclass 36, count 0 2006.173.13:32:33.36#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.13:32:33.36#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.13:32:33.36#ibcon#*before write, iclass 36, count 0 2006.173.13:32:33.36#ibcon#enter sib2, iclass 36, count 0 2006.173.13:32:33.36#ibcon#flushed, iclass 36, count 0 2006.173.13:32:33.36#ibcon#about to write, iclass 36, count 0 2006.173.13:32:33.36#ibcon#wrote, iclass 36, count 0 2006.173.13:32:33.36#ibcon#about to read 3, iclass 36, count 0 2006.173.13:32:33.40#ibcon#read 3, iclass 36, count 0 2006.173.13:32:33.40#ibcon#about to read 4, iclass 36, count 0 2006.173.13:32:33.40#ibcon#read 4, iclass 36, count 0 2006.173.13:32:33.40#ibcon#about to read 5, iclass 36, count 0 2006.173.13:32:33.40#ibcon#read 5, iclass 36, count 0 2006.173.13:32:33.40#ibcon#about to read 6, iclass 36, count 0 2006.173.13:32:33.40#ibcon#read 6, iclass 36, count 0 2006.173.13:32:33.40#ibcon#end of sib2, iclass 36, count 0 2006.173.13:32:33.40#ibcon#*after write, iclass 36, count 0 2006.173.13:32:33.40#ibcon#*before return 0, iclass 36, count 0 2006.173.13:32:33.40#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.13:32:33.40#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.13:32:33.40#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.13:32:33.40#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.13:32:33.41$vck44/vb=2,4 2006.173.13:32:33.41#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.13:32:33.41#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.13:32:33.41#ibcon#ireg 11 cls_cnt 2 2006.173.13:32:33.41#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.13:32:33.45#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.13:32:33.45#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.13:32:33.45#ibcon#enter wrdev, iclass 38, count 2 2006.173.13:32:33.45#ibcon#first serial, iclass 38, count 2 2006.173.13:32:33.45#ibcon#enter sib2, iclass 38, count 2 2006.173.13:32:33.45#ibcon#flushed, iclass 38, count 2 2006.173.13:32:33.45#ibcon#about to write, iclass 38, count 2 2006.173.13:32:33.45#ibcon#wrote, iclass 38, count 2 2006.173.13:32:33.45#ibcon#about to read 3, iclass 38, count 2 2006.173.13:32:33.47#ibcon#read 3, iclass 38, count 2 2006.173.13:32:33.47#ibcon#about to read 4, iclass 38, count 2 2006.173.13:32:33.47#ibcon#read 4, iclass 38, count 2 2006.173.13:32:33.47#ibcon#about to read 5, iclass 38, count 2 2006.173.13:32:33.47#ibcon#read 5, iclass 38, count 2 2006.173.13:32:33.47#ibcon#about to read 6, iclass 38, count 2 2006.173.13:32:33.47#ibcon#read 6, iclass 38, count 2 2006.173.13:32:33.47#ibcon#end of sib2, iclass 38, count 2 2006.173.13:32:33.47#ibcon#*mode == 0, iclass 38, count 2 2006.173.13:32:33.47#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.13:32:33.47#ibcon#[27=AT02-04\r\n] 2006.173.13:32:33.47#ibcon#*before write, iclass 38, count 2 2006.173.13:32:33.47#ibcon#enter sib2, iclass 38, count 2 2006.173.13:32:33.47#ibcon#flushed, iclass 38, count 2 2006.173.13:32:33.47#ibcon#about to write, iclass 38, count 2 2006.173.13:32:33.47#ibcon#wrote, iclass 38, count 2 2006.173.13:32:33.47#ibcon#about to read 3, iclass 38, count 2 2006.173.13:32:33.50#ibcon#read 3, iclass 38, count 2 2006.173.13:32:33.50#ibcon#about to read 4, iclass 38, count 2 2006.173.13:32:33.50#ibcon#read 4, iclass 38, count 2 2006.173.13:32:33.50#ibcon#about to read 5, iclass 38, count 2 2006.173.13:32:33.50#ibcon#read 5, iclass 38, count 2 2006.173.13:32:33.50#ibcon#about to read 6, iclass 38, count 2 2006.173.13:32:33.50#ibcon#read 6, iclass 38, count 2 2006.173.13:32:33.50#ibcon#end of sib2, iclass 38, count 2 2006.173.13:32:33.50#ibcon#*after write, iclass 38, count 2 2006.173.13:32:33.50#ibcon#*before return 0, iclass 38, count 2 2006.173.13:32:33.50#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.13:32:33.50#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.13:32:33.50#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.13:32:33.50#ibcon#ireg 7 cls_cnt 0 2006.173.13:32:33.50#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.13:32:33.62#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.13:32:33.62#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.13:32:33.62#ibcon#enter wrdev, iclass 38, count 0 2006.173.13:32:33.62#ibcon#first serial, iclass 38, count 0 2006.173.13:32:33.62#ibcon#enter sib2, iclass 38, count 0 2006.173.13:32:33.62#ibcon#flushed, iclass 38, count 0 2006.173.13:32:33.62#ibcon#about to write, iclass 38, count 0 2006.173.13:32:33.62#ibcon#wrote, iclass 38, count 0 2006.173.13:32:33.62#ibcon#about to read 3, iclass 38, count 0 2006.173.13:32:33.64#ibcon#read 3, iclass 38, count 0 2006.173.13:32:33.64#ibcon#about to read 4, iclass 38, count 0 2006.173.13:32:33.64#ibcon#read 4, iclass 38, count 0 2006.173.13:32:33.64#ibcon#about to read 5, iclass 38, count 0 2006.173.13:32:33.64#ibcon#read 5, iclass 38, count 0 2006.173.13:32:33.64#ibcon#about to read 6, iclass 38, count 0 2006.173.13:32:33.64#ibcon#read 6, iclass 38, count 0 2006.173.13:32:33.64#ibcon#end of sib2, iclass 38, count 0 2006.173.13:32:33.64#ibcon#*mode == 0, iclass 38, count 0 2006.173.13:32:33.64#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.13:32:33.64#ibcon#[27=USB\r\n] 2006.173.13:32:33.64#ibcon#*before write, iclass 38, count 0 2006.173.13:32:33.64#ibcon#enter sib2, iclass 38, count 0 2006.173.13:32:33.64#ibcon#flushed, iclass 38, count 0 2006.173.13:32:33.64#ibcon#about to write, iclass 38, count 0 2006.173.13:32:33.64#ibcon#wrote, iclass 38, count 0 2006.173.13:32:33.64#ibcon#about to read 3, iclass 38, count 0 2006.173.13:32:33.67#ibcon#read 3, iclass 38, count 0 2006.173.13:32:33.67#ibcon#about to read 4, iclass 38, count 0 2006.173.13:32:33.67#ibcon#read 4, iclass 38, count 0 2006.173.13:32:33.67#ibcon#about to read 5, iclass 38, count 0 2006.173.13:32:33.67#ibcon#read 5, iclass 38, count 0 2006.173.13:32:33.67#ibcon#about to read 6, iclass 38, count 0 2006.173.13:32:33.67#ibcon#read 6, iclass 38, count 0 2006.173.13:32:33.67#ibcon#end of sib2, iclass 38, count 0 2006.173.13:32:33.67#ibcon#*after write, iclass 38, count 0 2006.173.13:32:33.67#ibcon#*before return 0, iclass 38, count 0 2006.173.13:32:33.67#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.13:32:33.67#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.13:32:33.67#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.13:32:33.67#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.13:32:33.68$vck44/vblo=3,649.99 2006.173.13:32:33.68#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.13:32:33.68#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.13:32:33.68#ibcon#ireg 17 cls_cnt 0 2006.173.13:32:33.68#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.13:32:33.68#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.13:32:33.68#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.13:32:33.68#ibcon#enter wrdev, iclass 40, count 0 2006.173.13:32:33.68#ibcon#first serial, iclass 40, count 0 2006.173.13:32:33.68#ibcon#enter sib2, iclass 40, count 0 2006.173.13:32:33.68#ibcon#flushed, iclass 40, count 0 2006.173.13:32:33.68#ibcon#about to write, iclass 40, count 0 2006.173.13:32:33.68#ibcon#wrote, iclass 40, count 0 2006.173.13:32:33.68#ibcon#about to read 3, iclass 40, count 0 2006.173.13:32:33.69#ibcon#read 3, iclass 40, count 0 2006.173.13:32:33.69#ibcon#about to read 4, iclass 40, count 0 2006.173.13:32:33.69#ibcon#read 4, iclass 40, count 0 2006.173.13:32:33.69#ibcon#about to read 5, iclass 40, count 0 2006.173.13:32:33.69#ibcon#read 5, iclass 40, count 0 2006.173.13:32:33.69#ibcon#about to read 6, iclass 40, count 0 2006.173.13:32:33.69#ibcon#read 6, iclass 40, count 0 2006.173.13:32:33.69#ibcon#end of sib2, iclass 40, count 0 2006.173.13:32:33.69#ibcon#*mode == 0, iclass 40, count 0 2006.173.13:32:33.69#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.13:32:33.69#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.13:32:33.69#ibcon#*before write, iclass 40, count 0 2006.173.13:32:33.69#ibcon#enter sib2, iclass 40, count 0 2006.173.13:32:33.69#ibcon#flushed, iclass 40, count 0 2006.173.13:32:33.69#ibcon#about to write, iclass 40, count 0 2006.173.13:32:33.69#ibcon#wrote, iclass 40, count 0 2006.173.13:32:33.69#ibcon#about to read 3, iclass 40, count 0 2006.173.13:32:33.73#ibcon#read 3, iclass 40, count 0 2006.173.13:32:33.73#ibcon#about to read 4, iclass 40, count 0 2006.173.13:32:33.73#ibcon#read 4, iclass 40, count 0 2006.173.13:32:33.73#ibcon#about to read 5, iclass 40, count 0 2006.173.13:32:33.73#ibcon#read 5, iclass 40, count 0 2006.173.13:32:33.73#ibcon#about to read 6, iclass 40, count 0 2006.173.13:32:33.73#ibcon#read 6, iclass 40, count 0 2006.173.13:32:33.73#ibcon#end of sib2, iclass 40, count 0 2006.173.13:32:33.73#ibcon#*after write, iclass 40, count 0 2006.173.13:32:33.73#ibcon#*before return 0, iclass 40, count 0 2006.173.13:32:33.73#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.13:32:33.73#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.13:32:33.73#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.13:32:33.73#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.13:32:33.74$vck44/vb=3,4 2006.173.13:32:33.74#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.13:32:33.74#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.13:32:33.74#ibcon#ireg 11 cls_cnt 2 2006.173.13:32:33.74#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.13:32:33.78#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.13:32:33.78#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.13:32:33.78#ibcon#enter wrdev, iclass 4, count 2 2006.173.13:32:33.78#ibcon#first serial, iclass 4, count 2 2006.173.13:32:33.78#ibcon#enter sib2, iclass 4, count 2 2006.173.13:32:33.78#ibcon#flushed, iclass 4, count 2 2006.173.13:32:33.78#ibcon#about to write, iclass 4, count 2 2006.173.13:32:33.78#ibcon#wrote, iclass 4, count 2 2006.173.13:32:33.78#ibcon#about to read 3, iclass 4, count 2 2006.173.13:32:33.80#ibcon#read 3, iclass 4, count 2 2006.173.13:32:33.80#ibcon#about to read 4, iclass 4, count 2 2006.173.13:32:33.80#ibcon#read 4, iclass 4, count 2 2006.173.13:32:33.80#ibcon#about to read 5, iclass 4, count 2 2006.173.13:32:33.80#ibcon#read 5, iclass 4, count 2 2006.173.13:32:33.80#ibcon#about to read 6, iclass 4, count 2 2006.173.13:32:33.80#ibcon#read 6, iclass 4, count 2 2006.173.13:32:33.80#ibcon#end of sib2, iclass 4, count 2 2006.173.13:32:33.80#ibcon#*mode == 0, iclass 4, count 2 2006.173.13:32:33.80#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.13:32:33.80#ibcon#[27=AT03-04\r\n] 2006.173.13:32:33.80#ibcon#*before write, iclass 4, count 2 2006.173.13:32:33.80#ibcon#enter sib2, iclass 4, count 2 2006.173.13:32:33.80#ibcon#flushed, iclass 4, count 2 2006.173.13:32:33.80#ibcon#about to write, iclass 4, count 2 2006.173.13:32:33.80#ibcon#wrote, iclass 4, count 2 2006.173.13:32:33.80#ibcon#about to read 3, iclass 4, count 2 2006.173.13:32:33.83#ibcon#read 3, iclass 4, count 2 2006.173.13:32:33.83#ibcon#about to read 4, iclass 4, count 2 2006.173.13:32:33.83#ibcon#read 4, iclass 4, count 2 2006.173.13:32:33.83#ibcon#about to read 5, iclass 4, count 2 2006.173.13:32:33.83#ibcon#read 5, iclass 4, count 2 2006.173.13:32:33.83#ibcon#about to read 6, iclass 4, count 2 2006.173.13:32:33.83#ibcon#read 6, iclass 4, count 2 2006.173.13:32:33.83#ibcon#end of sib2, iclass 4, count 2 2006.173.13:32:33.83#ibcon#*after write, iclass 4, count 2 2006.173.13:32:33.83#ibcon#*before return 0, iclass 4, count 2 2006.173.13:32:33.83#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.13:32:33.83#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.13:32:33.83#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.13:32:33.83#ibcon#ireg 7 cls_cnt 0 2006.173.13:32:33.83#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.13:32:33.95#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.13:32:33.95#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.13:32:33.95#ibcon#enter wrdev, iclass 4, count 0 2006.173.13:32:33.95#ibcon#first serial, iclass 4, count 0 2006.173.13:32:33.95#ibcon#enter sib2, iclass 4, count 0 2006.173.13:32:33.95#ibcon#flushed, iclass 4, count 0 2006.173.13:32:33.95#ibcon#about to write, iclass 4, count 0 2006.173.13:32:33.95#ibcon#wrote, iclass 4, count 0 2006.173.13:32:33.95#ibcon#about to read 3, iclass 4, count 0 2006.173.13:32:33.97#ibcon#read 3, iclass 4, count 0 2006.173.13:32:33.97#ibcon#about to read 4, iclass 4, count 0 2006.173.13:32:33.97#ibcon#read 4, iclass 4, count 0 2006.173.13:32:33.97#ibcon#about to read 5, iclass 4, count 0 2006.173.13:32:33.97#ibcon#read 5, iclass 4, count 0 2006.173.13:32:33.97#ibcon#about to read 6, iclass 4, count 0 2006.173.13:32:33.97#ibcon#read 6, iclass 4, count 0 2006.173.13:32:33.97#ibcon#end of sib2, iclass 4, count 0 2006.173.13:32:33.97#ibcon#*mode == 0, iclass 4, count 0 2006.173.13:32:33.97#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.13:32:33.97#ibcon#[27=USB\r\n] 2006.173.13:32:33.97#ibcon#*before write, iclass 4, count 0 2006.173.13:32:33.97#ibcon#enter sib2, iclass 4, count 0 2006.173.13:32:33.97#ibcon#flushed, iclass 4, count 0 2006.173.13:32:33.97#ibcon#about to write, iclass 4, count 0 2006.173.13:32:33.97#ibcon#wrote, iclass 4, count 0 2006.173.13:32:33.97#ibcon#about to read 3, iclass 4, count 0 2006.173.13:32:34.00#ibcon#read 3, iclass 4, count 0 2006.173.13:32:34.00#ibcon#about to read 4, iclass 4, count 0 2006.173.13:32:34.00#ibcon#read 4, iclass 4, count 0 2006.173.13:32:34.00#ibcon#about to read 5, iclass 4, count 0 2006.173.13:32:34.00#ibcon#read 5, iclass 4, count 0 2006.173.13:32:34.00#ibcon#about to read 6, iclass 4, count 0 2006.173.13:32:34.00#ibcon#read 6, iclass 4, count 0 2006.173.13:32:34.00#ibcon#end of sib2, iclass 4, count 0 2006.173.13:32:34.00#ibcon#*after write, iclass 4, count 0 2006.173.13:32:34.00#ibcon#*before return 0, iclass 4, count 0 2006.173.13:32:34.00#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.13:32:34.00#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.13:32:34.00#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.13:32:34.00#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.13:32:34.01$vck44/vblo=4,679.99 2006.173.13:32:34.01#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.13:32:34.01#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.13:32:34.01#ibcon#ireg 17 cls_cnt 0 2006.173.13:32:34.01#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.13:32:34.01#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.13:32:34.01#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.13:32:34.01#ibcon#enter wrdev, iclass 6, count 0 2006.173.13:32:34.01#ibcon#first serial, iclass 6, count 0 2006.173.13:32:34.01#ibcon#enter sib2, iclass 6, count 0 2006.173.13:32:34.01#ibcon#flushed, iclass 6, count 0 2006.173.13:32:34.01#ibcon#about to write, iclass 6, count 0 2006.173.13:32:34.01#ibcon#wrote, iclass 6, count 0 2006.173.13:32:34.01#ibcon#about to read 3, iclass 6, count 0 2006.173.13:32:34.02#ibcon#read 3, iclass 6, count 0 2006.173.13:32:34.02#ibcon#about to read 4, iclass 6, count 0 2006.173.13:32:34.02#ibcon#read 4, iclass 6, count 0 2006.173.13:32:34.02#ibcon#about to read 5, iclass 6, count 0 2006.173.13:32:34.02#ibcon#read 5, iclass 6, count 0 2006.173.13:32:34.02#ibcon#about to read 6, iclass 6, count 0 2006.173.13:32:34.02#ibcon#read 6, iclass 6, count 0 2006.173.13:32:34.02#ibcon#end of sib2, iclass 6, count 0 2006.173.13:32:34.02#ibcon#*mode == 0, iclass 6, count 0 2006.173.13:32:34.02#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.13:32:34.02#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.13:32:34.02#ibcon#*before write, iclass 6, count 0 2006.173.13:32:34.02#ibcon#enter sib2, iclass 6, count 0 2006.173.13:32:34.02#ibcon#flushed, iclass 6, count 0 2006.173.13:32:34.02#ibcon#about to write, iclass 6, count 0 2006.173.13:32:34.03#ibcon#wrote, iclass 6, count 0 2006.173.13:32:34.03#ibcon#about to read 3, iclass 6, count 0 2006.173.13:32:34.06#ibcon#read 3, iclass 6, count 0 2006.173.13:32:34.06#ibcon#about to read 4, iclass 6, count 0 2006.173.13:32:34.06#ibcon#read 4, iclass 6, count 0 2006.173.13:32:34.06#ibcon#about to read 5, iclass 6, count 0 2006.173.13:32:34.06#ibcon#read 5, iclass 6, count 0 2006.173.13:32:34.06#ibcon#about to read 6, iclass 6, count 0 2006.173.13:32:34.06#ibcon#read 6, iclass 6, count 0 2006.173.13:32:34.06#ibcon#end of sib2, iclass 6, count 0 2006.173.13:32:34.06#ibcon#*after write, iclass 6, count 0 2006.173.13:32:34.06#ibcon#*before return 0, iclass 6, count 0 2006.173.13:32:34.06#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.13:32:34.06#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.13:32:34.06#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.13:32:34.06#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.13:32:34.07$vck44/vb=4,4 2006.173.13:32:34.07#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.13:32:34.07#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.13:32:34.07#ibcon#ireg 11 cls_cnt 2 2006.173.13:32:34.07#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.13:32:34.11#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.13:32:34.11#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.13:32:34.11#ibcon#enter wrdev, iclass 10, count 2 2006.173.13:32:34.11#ibcon#first serial, iclass 10, count 2 2006.173.13:32:34.11#ibcon#enter sib2, iclass 10, count 2 2006.173.13:32:34.11#ibcon#flushed, iclass 10, count 2 2006.173.13:32:34.11#ibcon#about to write, iclass 10, count 2 2006.173.13:32:34.11#ibcon#wrote, iclass 10, count 2 2006.173.13:32:34.11#ibcon#about to read 3, iclass 10, count 2 2006.173.13:32:34.13#ibcon#read 3, iclass 10, count 2 2006.173.13:32:34.13#ibcon#about to read 4, iclass 10, count 2 2006.173.13:32:34.13#ibcon#read 4, iclass 10, count 2 2006.173.13:32:34.13#ibcon#about to read 5, iclass 10, count 2 2006.173.13:32:34.13#ibcon#read 5, iclass 10, count 2 2006.173.13:32:34.13#ibcon#about to read 6, iclass 10, count 2 2006.173.13:32:34.13#ibcon#read 6, iclass 10, count 2 2006.173.13:32:34.13#ibcon#end of sib2, iclass 10, count 2 2006.173.13:32:34.13#ibcon#*mode == 0, iclass 10, count 2 2006.173.13:32:34.13#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.13:32:34.13#ibcon#[27=AT04-04\r\n] 2006.173.13:32:34.13#ibcon#*before write, iclass 10, count 2 2006.173.13:32:34.13#ibcon#enter sib2, iclass 10, count 2 2006.173.13:32:34.13#ibcon#flushed, iclass 10, count 2 2006.173.13:32:34.13#ibcon#about to write, iclass 10, count 2 2006.173.13:32:34.13#ibcon#wrote, iclass 10, count 2 2006.173.13:32:34.13#ibcon#about to read 3, iclass 10, count 2 2006.173.13:32:34.16#ibcon#read 3, iclass 10, count 2 2006.173.13:32:34.16#ibcon#about to read 4, iclass 10, count 2 2006.173.13:32:34.16#ibcon#read 4, iclass 10, count 2 2006.173.13:32:34.16#ibcon#about to read 5, iclass 10, count 2 2006.173.13:32:34.16#ibcon#read 5, iclass 10, count 2 2006.173.13:32:34.16#ibcon#about to read 6, iclass 10, count 2 2006.173.13:32:34.16#ibcon#read 6, iclass 10, count 2 2006.173.13:32:34.16#ibcon#end of sib2, iclass 10, count 2 2006.173.13:32:34.16#ibcon#*after write, iclass 10, count 2 2006.173.13:32:34.16#ibcon#*before return 0, iclass 10, count 2 2006.173.13:32:34.16#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.13:32:34.16#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.13:32:34.16#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.13:32:34.16#ibcon#ireg 7 cls_cnt 0 2006.173.13:32:34.16#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.13:32:34.28#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.13:32:34.28#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.13:32:34.28#ibcon#enter wrdev, iclass 10, count 0 2006.173.13:32:34.28#ibcon#first serial, iclass 10, count 0 2006.173.13:32:34.28#ibcon#enter sib2, iclass 10, count 0 2006.173.13:32:34.28#ibcon#flushed, iclass 10, count 0 2006.173.13:32:34.28#ibcon#about to write, iclass 10, count 0 2006.173.13:32:34.28#ibcon#wrote, iclass 10, count 0 2006.173.13:32:34.28#ibcon#about to read 3, iclass 10, count 0 2006.173.13:32:34.30#ibcon#read 3, iclass 10, count 0 2006.173.13:32:34.30#ibcon#about to read 4, iclass 10, count 0 2006.173.13:32:34.30#ibcon#read 4, iclass 10, count 0 2006.173.13:32:34.30#ibcon#about to read 5, iclass 10, count 0 2006.173.13:32:34.30#ibcon#read 5, iclass 10, count 0 2006.173.13:32:34.30#ibcon#about to read 6, iclass 10, count 0 2006.173.13:32:34.30#ibcon#read 6, iclass 10, count 0 2006.173.13:32:34.30#ibcon#end of sib2, iclass 10, count 0 2006.173.13:32:34.30#ibcon#*mode == 0, iclass 10, count 0 2006.173.13:32:34.30#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.13:32:34.30#ibcon#[27=USB\r\n] 2006.173.13:32:34.30#ibcon#*before write, iclass 10, count 0 2006.173.13:32:34.30#ibcon#enter sib2, iclass 10, count 0 2006.173.13:32:34.30#ibcon#flushed, iclass 10, count 0 2006.173.13:32:34.30#ibcon#about to write, iclass 10, count 0 2006.173.13:32:34.30#ibcon#wrote, iclass 10, count 0 2006.173.13:32:34.30#ibcon#about to read 3, iclass 10, count 0 2006.173.13:32:34.33#ibcon#read 3, iclass 10, count 0 2006.173.13:32:34.33#ibcon#about to read 4, iclass 10, count 0 2006.173.13:32:34.33#ibcon#read 4, iclass 10, count 0 2006.173.13:32:34.33#ibcon#about to read 5, iclass 10, count 0 2006.173.13:32:34.33#ibcon#read 5, iclass 10, count 0 2006.173.13:32:34.33#ibcon#about to read 6, iclass 10, count 0 2006.173.13:32:34.33#ibcon#read 6, iclass 10, count 0 2006.173.13:32:34.33#ibcon#end of sib2, iclass 10, count 0 2006.173.13:32:34.33#ibcon#*after write, iclass 10, count 0 2006.173.13:32:34.33#ibcon#*before return 0, iclass 10, count 0 2006.173.13:32:34.33#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.13:32:34.33#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.13:32:34.33#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.13:32:34.33#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.13:32:34.34$vck44/vblo=5,709.99 2006.173.13:32:34.34#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.13:32:34.34#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.13:32:34.34#ibcon#ireg 17 cls_cnt 0 2006.173.13:32:34.34#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.13:32:34.34#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.13:32:34.34#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.13:32:34.34#ibcon#enter wrdev, iclass 12, count 0 2006.173.13:32:34.34#ibcon#first serial, iclass 12, count 0 2006.173.13:32:34.34#ibcon#enter sib2, iclass 12, count 0 2006.173.13:32:34.34#ibcon#flushed, iclass 12, count 0 2006.173.13:32:34.34#ibcon#about to write, iclass 12, count 0 2006.173.13:32:34.34#ibcon#wrote, iclass 12, count 0 2006.173.13:32:34.34#ibcon#about to read 3, iclass 12, count 0 2006.173.13:32:34.35#ibcon#read 3, iclass 12, count 0 2006.173.13:32:34.35#ibcon#about to read 4, iclass 12, count 0 2006.173.13:32:34.35#ibcon#read 4, iclass 12, count 0 2006.173.13:32:34.35#ibcon#about to read 5, iclass 12, count 0 2006.173.13:32:34.35#ibcon#read 5, iclass 12, count 0 2006.173.13:32:34.35#ibcon#about to read 6, iclass 12, count 0 2006.173.13:32:34.35#ibcon#read 6, iclass 12, count 0 2006.173.13:32:34.35#ibcon#end of sib2, iclass 12, count 0 2006.173.13:32:34.35#ibcon#*mode == 0, iclass 12, count 0 2006.173.13:32:34.35#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.13:32:34.35#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.13:32:34.35#ibcon#*before write, iclass 12, count 0 2006.173.13:32:34.35#ibcon#enter sib2, iclass 12, count 0 2006.173.13:32:34.35#ibcon#flushed, iclass 12, count 0 2006.173.13:32:34.35#ibcon#about to write, iclass 12, count 0 2006.173.13:32:34.35#ibcon#wrote, iclass 12, count 0 2006.173.13:32:34.35#ibcon#about to read 3, iclass 12, count 0 2006.173.13:32:34.39#ibcon#read 3, iclass 12, count 0 2006.173.13:32:34.39#ibcon#about to read 4, iclass 12, count 0 2006.173.13:32:34.39#ibcon#read 4, iclass 12, count 0 2006.173.13:32:34.39#ibcon#about to read 5, iclass 12, count 0 2006.173.13:32:34.39#ibcon#read 5, iclass 12, count 0 2006.173.13:32:34.39#ibcon#about to read 6, iclass 12, count 0 2006.173.13:32:34.39#ibcon#read 6, iclass 12, count 0 2006.173.13:32:34.39#ibcon#end of sib2, iclass 12, count 0 2006.173.13:32:34.39#ibcon#*after write, iclass 12, count 0 2006.173.13:32:34.39#ibcon#*before return 0, iclass 12, count 0 2006.173.13:32:34.39#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.13:32:34.39#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.13:32:34.39#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.13:32:34.39#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.13:32:34.40$vck44/vb=5,4 2006.173.13:32:34.40#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.13:32:34.40#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.13:32:34.40#ibcon#ireg 11 cls_cnt 2 2006.173.13:32:34.40#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.13:32:34.44#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.13:32:34.44#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.13:32:34.44#ibcon#enter wrdev, iclass 14, count 2 2006.173.13:32:34.44#ibcon#first serial, iclass 14, count 2 2006.173.13:32:34.44#ibcon#enter sib2, iclass 14, count 2 2006.173.13:32:34.44#ibcon#flushed, iclass 14, count 2 2006.173.13:32:34.44#ibcon#about to write, iclass 14, count 2 2006.173.13:32:34.44#ibcon#wrote, iclass 14, count 2 2006.173.13:32:34.44#ibcon#about to read 3, iclass 14, count 2 2006.173.13:32:34.46#ibcon#read 3, iclass 14, count 2 2006.173.13:32:34.46#ibcon#about to read 4, iclass 14, count 2 2006.173.13:32:34.46#ibcon#read 4, iclass 14, count 2 2006.173.13:32:34.46#ibcon#about to read 5, iclass 14, count 2 2006.173.13:32:34.46#ibcon#read 5, iclass 14, count 2 2006.173.13:32:34.46#ibcon#about to read 6, iclass 14, count 2 2006.173.13:32:34.46#ibcon#read 6, iclass 14, count 2 2006.173.13:32:34.46#ibcon#end of sib2, iclass 14, count 2 2006.173.13:32:34.46#ibcon#*mode == 0, iclass 14, count 2 2006.173.13:32:34.46#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.13:32:34.46#ibcon#[27=AT05-04\r\n] 2006.173.13:32:34.46#ibcon#*before write, iclass 14, count 2 2006.173.13:32:34.46#ibcon#enter sib2, iclass 14, count 2 2006.173.13:32:34.46#ibcon#flushed, iclass 14, count 2 2006.173.13:32:34.46#ibcon#about to write, iclass 14, count 2 2006.173.13:32:34.46#ibcon#wrote, iclass 14, count 2 2006.173.13:32:34.46#ibcon#about to read 3, iclass 14, count 2 2006.173.13:32:34.49#ibcon#read 3, iclass 14, count 2 2006.173.13:32:34.49#ibcon#about to read 4, iclass 14, count 2 2006.173.13:32:34.49#ibcon#read 4, iclass 14, count 2 2006.173.13:32:34.49#ibcon#about to read 5, iclass 14, count 2 2006.173.13:32:34.49#ibcon#read 5, iclass 14, count 2 2006.173.13:32:34.49#ibcon#about to read 6, iclass 14, count 2 2006.173.13:32:34.49#ibcon#read 6, iclass 14, count 2 2006.173.13:32:34.49#ibcon#end of sib2, iclass 14, count 2 2006.173.13:32:34.49#ibcon#*after write, iclass 14, count 2 2006.173.13:32:34.49#ibcon#*before return 0, iclass 14, count 2 2006.173.13:32:34.49#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.13:32:34.49#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.13:32:34.49#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.13:32:34.49#ibcon#ireg 7 cls_cnt 0 2006.173.13:32:34.49#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.13:32:34.61#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.13:32:34.61#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.13:32:34.61#ibcon#enter wrdev, iclass 14, count 0 2006.173.13:32:34.61#ibcon#first serial, iclass 14, count 0 2006.173.13:32:34.61#ibcon#enter sib2, iclass 14, count 0 2006.173.13:32:34.61#ibcon#flushed, iclass 14, count 0 2006.173.13:32:34.61#ibcon#about to write, iclass 14, count 0 2006.173.13:32:34.61#ibcon#wrote, iclass 14, count 0 2006.173.13:32:34.61#ibcon#about to read 3, iclass 14, count 0 2006.173.13:32:34.63#ibcon#read 3, iclass 14, count 0 2006.173.13:32:34.63#ibcon#about to read 4, iclass 14, count 0 2006.173.13:32:34.63#ibcon#read 4, iclass 14, count 0 2006.173.13:32:34.63#ibcon#about to read 5, iclass 14, count 0 2006.173.13:32:34.63#ibcon#read 5, iclass 14, count 0 2006.173.13:32:34.63#ibcon#about to read 6, iclass 14, count 0 2006.173.13:32:34.63#ibcon#read 6, iclass 14, count 0 2006.173.13:32:34.63#ibcon#end of sib2, iclass 14, count 0 2006.173.13:32:34.63#ibcon#*mode == 0, iclass 14, count 0 2006.173.13:32:34.63#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.13:32:34.63#ibcon#[27=USB\r\n] 2006.173.13:32:34.63#ibcon#*before write, iclass 14, count 0 2006.173.13:32:34.63#ibcon#enter sib2, iclass 14, count 0 2006.173.13:32:34.63#ibcon#flushed, iclass 14, count 0 2006.173.13:32:34.63#ibcon#about to write, iclass 14, count 0 2006.173.13:32:34.63#ibcon#wrote, iclass 14, count 0 2006.173.13:32:34.63#ibcon#about to read 3, iclass 14, count 0 2006.173.13:32:34.66#ibcon#read 3, iclass 14, count 0 2006.173.13:32:34.66#ibcon#about to read 4, iclass 14, count 0 2006.173.13:32:34.66#ibcon#read 4, iclass 14, count 0 2006.173.13:32:34.66#ibcon#about to read 5, iclass 14, count 0 2006.173.13:32:34.66#ibcon#read 5, iclass 14, count 0 2006.173.13:32:34.66#ibcon#about to read 6, iclass 14, count 0 2006.173.13:32:34.66#ibcon#read 6, iclass 14, count 0 2006.173.13:32:34.66#ibcon#end of sib2, iclass 14, count 0 2006.173.13:32:34.66#ibcon#*after write, iclass 14, count 0 2006.173.13:32:34.66#ibcon#*before return 0, iclass 14, count 0 2006.173.13:32:34.66#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.13:32:34.66#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.13:32:34.66#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.13:32:34.66#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.13:32:34.67$vck44/vblo=6,719.99 2006.173.13:32:34.67#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.13:32:34.67#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.13:32:34.67#ibcon#ireg 17 cls_cnt 0 2006.173.13:32:34.67#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.13:32:34.67#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.13:32:34.67#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.13:32:34.67#ibcon#enter wrdev, iclass 16, count 0 2006.173.13:32:34.67#ibcon#first serial, iclass 16, count 0 2006.173.13:32:34.67#ibcon#enter sib2, iclass 16, count 0 2006.173.13:32:34.67#ibcon#flushed, iclass 16, count 0 2006.173.13:32:34.67#ibcon#about to write, iclass 16, count 0 2006.173.13:32:34.67#ibcon#wrote, iclass 16, count 0 2006.173.13:32:34.67#ibcon#about to read 3, iclass 16, count 0 2006.173.13:32:34.68#ibcon#read 3, iclass 16, count 0 2006.173.13:32:34.68#ibcon#about to read 4, iclass 16, count 0 2006.173.13:32:34.68#ibcon#read 4, iclass 16, count 0 2006.173.13:32:34.68#ibcon#about to read 5, iclass 16, count 0 2006.173.13:32:34.68#ibcon#read 5, iclass 16, count 0 2006.173.13:32:34.68#ibcon#about to read 6, iclass 16, count 0 2006.173.13:32:34.68#ibcon#read 6, iclass 16, count 0 2006.173.13:32:34.68#ibcon#end of sib2, iclass 16, count 0 2006.173.13:32:34.68#ibcon#*mode == 0, iclass 16, count 0 2006.173.13:32:34.68#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.13:32:34.68#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.13:32:34.68#ibcon#*before write, iclass 16, count 0 2006.173.13:32:34.68#ibcon#enter sib2, iclass 16, count 0 2006.173.13:32:34.68#ibcon#flushed, iclass 16, count 0 2006.173.13:32:34.68#ibcon#about to write, iclass 16, count 0 2006.173.13:32:34.68#ibcon#wrote, iclass 16, count 0 2006.173.13:32:34.68#ibcon#about to read 3, iclass 16, count 0 2006.173.13:32:34.72#ibcon#read 3, iclass 16, count 0 2006.173.13:32:34.72#ibcon#about to read 4, iclass 16, count 0 2006.173.13:32:34.72#ibcon#read 4, iclass 16, count 0 2006.173.13:32:34.72#ibcon#about to read 5, iclass 16, count 0 2006.173.13:32:34.72#ibcon#read 5, iclass 16, count 0 2006.173.13:32:34.72#ibcon#about to read 6, iclass 16, count 0 2006.173.13:32:34.72#ibcon#read 6, iclass 16, count 0 2006.173.13:32:34.72#ibcon#end of sib2, iclass 16, count 0 2006.173.13:32:34.72#ibcon#*after write, iclass 16, count 0 2006.173.13:32:34.72#ibcon#*before return 0, iclass 16, count 0 2006.173.13:32:34.72#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.13:32:34.72#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.13:32:34.72#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.13:32:34.72#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.13:32:34.73$vck44/vb=6,4 2006.173.13:32:34.73#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.13:32:34.73#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.13:32:34.73#ibcon#ireg 11 cls_cnt 2 2006.173.13:32:34.73#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.13:32:34.77#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.13:32:34.77#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.13:32:34.77#ibcon#enter wrdev, iclass 18, count 2 2006.173.13:32:34.77#ibcon#first serial, iclass 18, count 2 2006.173.13:32:34.77#ibcon#enter sib2, iclass 18, count 2 2006.173.13:32:34.77#ibcon#flushed, iclass 18, count 2 2006.173.13:32:34.77#ibcon#about to write, iclass 18, count 2 2006.173.13:32:34.77#ibcon#wrote, iclass 18, count 2 2006.173.13:32:34.77#ibcon#about to read 3, iclass 18, count 2 2006.173.13:32:34.79#ibcon#read 3, iclass 18, count 2 2006.173.13:32:34.79#ibcon#about to read 4, iclass 18, count 2 2006.173.13:32:34.79#ibcon#read 4, iclass 18, count 2 2006.173.13:32:34.79#ibcon#about to read 5, iclass 18, count 2 2006.173.13:32:34.79#ibcon#read 5, iclass 18, count 2 2006.173.13:32:34.79#ibcon#about to read 6, iclass 18, count 2 2006.173.13:32:34.79#ibcon#read 6, iclass 18, count 2 2006.173.13:32:34.79#ibcon#end of sib2, iclass 18, count 2 2006.173.13:32:34.79#ibcon#*mode == 0, iclass 18, count 2 2006.173.13:32:34.79#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.13:32:34.79#ibcon#[27=AT06-04\r\n] 2006.173.13:32:34.79#ibcon#*before write, iclass 18, count 2 2006.173.13:32:34.79#ibcon#enter sib2, iclass 18, count 2 2006.173.13:32:34.79#ibcon#flushed, iclass 18, count 2 2006.173.13:32:34.79#ibcon#about to write, iclass 18, count 2 2006.173.13:32:34.79#ibcon#wrote, iclass 18, count 2 2006.173.13:32:34.79#ibcon#about to read 3, iclass 18, count 2 2006.173.13:32:34.82#ibcon#read 3, iclass 18, count 2 2006.173.13:32:34.82#ibcon#about to read 4, iclass 18, count 2 2006.173.13:32:34.82#ibcon#read 4, iclass 18, count 2 2006.173.13:32:34.82#ibcon#about to read 5, iclass 18, count 2 2006.173.13:32:34.82#ibcon#read 5, iclass 18, count 2 2006.173.13:32:34.82#ibcon#about to read 6, iclass 18, count 2 2006.173.13:32:34.82#ibcon#read 6, iclass 18, count 2 2006.173.13:32:34.82#ibcon#end of sib2, iclass 18, count 2 2006.173.13:32:34.82#ibcon#*after write, iclass 18, count 2 2006.173.13:32:34.82#ibcon#*before return 0, iclass 18, count 2 2006.173.13:32:34.82#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.13:32:34.82#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.13:32:34.82#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.13:32:34.82#ibcon#ireg 7 cls_cnt 0 2006.173.13:32:34.82#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.13:32:34.94#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.13:32:34.94#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.13:32:34.94#ibcon#enter wrdev, iclass 18, count 0 2006.173.13:32:34.94#ibcon#first serial, iclass 18, count 0 2006.173.13:32:34.94#ibcon#enter sib2, iclass 18, count 0 2006.173.13:32:34.94#ibcon#flushed, iclass 18, count 0 2006.173.13:32:34.94#ibcon#about to write, iclass 18, count 0 2006.173.13:32:34.94#ibcon#wrote, iclass 18, count 0 2006.173.13:32:34.94#ibcon#about to read 3, iclass 18, count 0 2006.173.13:32:34.96#ibcon#read 3, iclass 18, count 0 2006.173.13:32:34.96#ibcon#about to read 4, iclass 18, count 0 2006.173.13:32:34.96#ibcon#read 4, iclass 18, count 0 2006.173.13:32:34.96#ibcon#about to read 5, iclass 18, count 0 2006.173.13:32:34.96#ibcon#read 5, iclass 18, count 0 2006.173.13:32:34.96#ibcon#about to read 6, iclass 18, count 0 2006.173.13:32:34.96#ibcon#read 6, iclass 18, count 0 2006.173.13:32:34.96#ibcon#end of sib2, iclass 18, count 0 2006.173.13:32:34.96#ibcon#*mode == 0, iclass 18, count 0 2006.173.13:32:34.96#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.13:32:34.96#ibcon#[27=USB\r\n] 2006.173.13:32:34.96#ibcon#*before write, iclass 18, count 0 2006.173.13:32:34.96#ibcon#enter sib2, iclass 18, count 0 2006.173.13:32:34.96#ibcon#flushed, iclass 18, count 0 2006.173.13:32:34.96#ibcon#about to write, iclass 18, count 0 2006.173.13:32:34.96#ibcon#wrote, iclass 18, count 0 2006.173.13:32:34.96#ibcon#about to read 3, iclass 18, count 0 2006.173.13:32:34.99#ibcon#read 3, iclass 18, count 0 2006.173.13:32:34.99#ibcon#about to read 4, iclass 18, count 0 2006.173.13:32:34.99#ibcon#read 4, iclass 18, count 0 2006.173.13:32:34.99#ibcon#about to read 5, iclass 18, count 0 2006.173.13:32:34.99#ibcon#read 5, iclass 18, count 0 2006.173.13:32:34.99#ibcon#about to read 6, iclass 18, count 0 2006.173.13:32:34.99#ibcon#read 6, iclass 18, count 0 2006.173.13:32:34.99#ibcon#end of sib2, iclass 18, count 0 2006.173.13:32:34.99#ibcon#*after write, iclass 18, count 0 2006.173.13:32:34.99#ibcon#*before return 0, iclass 18, count 0 2006.173.13:32:34.99#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.13:32:34.99#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.13:32:34.99#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.13:32:34.99#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.13:32:35.00$vck44/vblo=7,734.99 2006.173.13:32:35.00#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.13:32:35.00#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.13:32:35.00#ibcon#ireg 17 cls_cnt 0 2006.173.13:32:35.00#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.13:32:35.00#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.13:32:35.00#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.13:32:35.00#ibcon#enter wrdev, iclass 20, count 0 2006.173.13:32:35.00#ibcon#first serial, iclass 20, count 0 2006.173.13:32:35.00#ibcon#enter sib2, iclass 20, count 0 2006.173.13:32:35.00#ibcon#flushed, iclass 20, count 0 2006.173.13:32:35.00#ibcon#about to write, iclass 20, count 0 2006.173.13:32:35.00#ibcon#wrote, iclass 20, count 0 2006.173.13:32:35.00#ibcon#about to read 3, iclass 20, count 0 2006.173.13:32:35.01#ibcon#read 3, iclass 20, count 0 2006.173.13:32:35.01#ibcon#about to read 4, iclass 20, count 0 2006.173.13:32:35.01#ibcon#read 4, iclass 20, count 0 2006.173.13:32:35.01#ibcon#about to read 5, iclass 20, count 0 2006.173.13:32:35.01#ibcon#read 5, iclass 20, count 0 2006.173.13:32:35.01#ibcon#about to read 6, iclass 20, count 0 2006.173.13:32:35.01#ibcon#read 6, iclass 20, count 0 2006.173.13:32:35.01#ibcon#end of sib2, iclass 20, count 0 2006.173.13:32:35.01#ibcon#*mode == 0, iclass 20, count 0 2006.173.13:32:35.01#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.13:32:35.01#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.13:32:35.01#ibcon#*before write, iclass 20, count 0 2006.173.13:32:35.01#ibcon#enter sib2, iclass 20, count 0 2006.173.13:32:35.01#ibcon#flushed, iclass 20, count 0 2006.173.13:32:35.01#ibcon#about to write, iclass 20, count 0 2006.173.13:32:35.01#ibcon#wrote, iclass 20, count 0 2006.173.13:32:35.01#ibcon#about to read 3, iclass 20, count 0 2006.173.13:32:35.05#ibcon#read 3, iclass 20, count 0 2006.173.13:32:35.05#ibcon#about to read 4, iclass 20, count 0 2006.173.13:32:35.05#ibcon#read 4, iclass 20, count 0 2006.173.13:32:35.05#ibcon#about to read 5, iclass 20, count 0 2006.173.13:32:35.05#ibcon#read 5, iclass 20, count 0 2006.173.13:32:35.05#ibcon#about to read 6, iclass 20, count 0 2006.173.13:32:35.05#ibcon#read 6, iclass 20, count 0 2006.173.13:32:35.05#ibcon#end of sib2, iclass 20, count 0 2006.173.13:32:35.05#ibcon#*after write, iclass 20, count 0 2006.173.13:32:35.05#ibcon#*before return 0, iclass 20, count 0 2006.173.13:32:35.05#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.13:32:35.05#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.13:32:35.05#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.13:32:35.05#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.13:32:35.06$vck44/vb=7,4 2006.173.13:32:35.06#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.13:32:35.06#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.13:32:35.06#ibcon#ireg 11 cls_cnt 2 2006.173.13:32:35.06#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.13:32:35.10#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.13:32:35.10#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.13:32:35.10#ibcon#enter wrdev, iclass 22, count 2 2006.173.13:32:35.10#ibcon#first serial, iclass 22, count 2 2006.173.13:32:35.10#ibcon#enter sib2, iclass 22, count 2 2006.173.13:32:35.10#ibcon#flushed, iclass 22, count 2 2006.173.13:32:35.10#ibcon#about to write, iclass 22, count 2 2006.173.13:32:35.10#ibcon#wrote, iclass 22, count 2 2006.173.13:32:35.10#ibcon#about to read 3, iclass 22, count 2 2006.173.13:32:35.12#ibcon#read 3, iclass 22, count 2 2006.173.13:32:35.12#ibcon#about to read 4, iclass 22, count 2 2006.173.13:32:35.12#ibcon#read 4, iclass 22, count 2 2006.173.13:32:35.12#ibcon#about to read 5, iclass 22, count 2 2006.173.13:32:35.12#ibcon#read 5, iclass 22, count 2 2006.173.13:32:35.12#ibcon#about to read 6, iclass 22, count 2 2006.173.13:32:35.12#ibcon#read 6, iclass 22, count 2 2006.173.13:32:35.12#ibcon#end of sib2, iclass 22, count 2 2006.173.13:32:35.12#ibcon#*mode == 0, iclass 22, count 2 2006.173.13:32:35.12#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.13:32:35.12#ibcon#[27=AT07-04\r\n] 2006.173.13:32:35.12#ibcon#*before write, iclass 22, count 2 2006.173.13:32:35.12#ibcon#enter sib2, iclass 22, count 2 2006.173.13:32:35.12#ibcon#flushed, iclass 22, count 2 2006.173.13:32:35.12#ibcon#about to write, iclass 22, count 2 2006.173.13:32:35.12#ibcon#wrote, iclass 22, count 2 2006.173.13:32:35.12#ibcon#about to read 3, iclass 22, count 2 2006.173.13:32:35.15#ibcon#read 3, iclass 22, count 2 2006.173.13:32:35.15#ibcon#about to read 4, iclass 22, count 2 2006.173.13:32:35.15#ibcon#read 4, iclass 22, count 2 2006.173.13:32:35.15#ibcon#about to read 5, iclass 22, count 2 2006.173.13:32:35.15#ibcon#read 5, iclass 22, count 2 2006.173.13:32:35.15#ibcon#about to read 6, iclass 22, count 2 2006.173.13:32:35.15#ibcon#read 6, iclass 22, count 2 2006.173.13:32:35.15#ibcon#end of sib2, iclass 22, count 2 2006.173.13:32:35.15#ibcon#*after write, iclass 22, count 2 2006.173.13:32:35.15#ibcon#*before return 0, iclass 22, count 2 2006.173.13:32:35.15#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.13:32:35.15#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.13:32:35.15#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.13:32:35.15#ibcon#ireg 7 cls_cnt 0 2006.173.13:32:35.15#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.13:32:35.27#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.13:32:35.27#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.13:32:35.27#ibcon#enter wrdev, iclass 22, count 0 2006.173.13:32:35.27#ibcon#first serial, iclass 22, count 0 2006.173.13:32:35.27#ibcon#enter sib2, iclass 22, count 0 2006.173.13:32:35.27#ibcon#flushed, iclass 22, count 0 2006.173.13:32:35.27#ibcon#about to write, iclass 22, count 0 2006.173.13:32:35.27#ibcon#wrote, iclass 22, count 0 2006.173.13:32:35.27#ibcon#about to read 3, iclass 22, count 0 2006.173.13:32:35.29#ibcon#read 3, iclass 22, count 0 2006.173.13:32:35.29#ibcon#about to read 4, iclass 22, count 0 2006.173.13:32:35.29#ibcon#read 4, iclass 22, count 0 2006.173.13:32:35.29#ibcon#about to read 5, iclass 22, count 0 2006.173.13:32:35.29#ibcon#read 5, iclass 22, count 0 2006.173.13:32:35.29#ibcon#about to read 6, iclass 22, count 0 2006.173.13:32:35.29#ibcon#read 6, iclass 22, count 0 2006.173.13:32:35.29#ibcon#end of sib2, iclass 22, count 0 2006.173.13:32:35.29#ibcon#*mode == 0, iclass 22, count 0 2006.173.13:32:35.29#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.13:32:35.29#ibcon#[27=USB\r\n] 2006.173.13:32:35.29#ibcon#*before write, iclass 22, count 0 2006.173.13:32:35.29#ibcon#enter sib2, iclass 22, count 0 2006.173.13:32:35.29#ibcon#flushed, iclass 22, count 0 2006.173.13:32:35.29#ibcon#about to write, iclass 22, count 0 2006.173.13:32:35.29#ibcon#wrote, iclass 22, count 0 2006.173.13:32:35.29#ibcon#about to read 3, iclass 22, count 0 2006.173.13:32:35.32#ibcon#read 3, iclass 22, count 0 2006.173.13:32:35.32#ibcon#about to read 4, iclass 22, count 0 2006.173.13:32:35.32#ibcon#read 4, iclass 22, count 0 2006.173.13:32:35.32#ibcon#about to read 5, iclass 22, count 0 2006.173.13:32:35.32#ibcon#read 5, iclass 22, count 0 2006.173.13:32:35.32#ibcon#about to read 6, iclass 22, count 0 2006.173.13:32:35.32#ibcon#read 6, iclass 22, count 0 2006.173.13:32:35.32#ibcon#end of sib2, iclass 22, count 0 2006.173.13:32:35.32#ibcon#*after write, iclass 22, count 0 2006.173.13:32:35.32#ibcon#*before return 0, iclass 22, count 0 2006.173.13:32:35.32#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.13:32:35.32#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.13:32:35.32#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.13:32:35.32#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.13:32:35.33$vck44/vblo=8,744.99 2006.173.13:32:35.33#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.13:32:35.33#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.13:32:35.33#ibcon#ireg 17 cls_cnt 0 2006.173.13:32:35.33#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.13:32:35.33#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.13:32:35.33#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.13:32:35.33#ibcon#enter wrdev, iclass 24, count 0 2006.173.13:32:35.33#ibcon#first serial, iclass 24, count 0 2006.173.13:32:35.33#ibcon#enter sib2, iclass 24, count 0 2006.173.13:32:35.33#ibcon#flushed, iclass 24, count 0 2006.173.13:32:35.33#ibcon#about to write, iclass 24, count 0 2006.173.13:32:35.33#ibcon#wrote, iclass 24, count 0 2006.173.13:32:35.33#ibcon#about to read 3, iclass 24, count 0 2006.173.13:32:35.34#ibcon#read 3, iclass 24, count 0 2006.173.13:32:35.34#ibcon#about to read 4, iclass 24, count 0 2006.173.13:32:35.34#ibcon#read 4, iclass 24, count 0 2006.173.13:32:35.34#ibcon#about to read 5, iclass 24, count 0 2006.173.13:32:35.34#ibcon#read 5, iclass 24, count 0 2006.173.13:32:35.34#ibcon#about to read 6, iclass 24, count 0 2006.173.13:32:35.34#ibcon#read 6, iclass 24, count 0 2006.173.13:32:35.34#ibcon#end of sib2, iclass 24, count 0 2006.173.13:32:35.34#ibcon#*mode == 0, iclass 24, count 0 2006.173.13:32:35.34#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.13:32:35.34#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.13:32:35.34#ibcon#*before write, iclass 24, count 0 2006.173.13:32:35.34#ibcon#enter sib2, iclass 24, count 0 2006.173.13:32:35.34#ibcon#flushed, iclass 24, count 0 2006.173.13:32:35.34#ibcon#about to write, iclass 24, count 0 2006.173.13:32:35.34#ibcon#wrote, iclass 24, count 0 2006.173.13:32:35.34#ibcon#about to read 3, iclass 24, count 0 2006.173.13:32:35.38#ibcon#read 3, iclass 24, count 0 2006.173.13:32:35.38#ibcon#about to read 4, iclass 24, count 0 2006.173.13:32:35.38#ibcon#read 4, iclass 24, count 0 2006.173.13:32:35.38#ibcon#about to read 5, iclass 24, count 0 2006.173.13:32:35.38#ibcon#read 5, iclass 24, count 0 2006.173.13:32:35.38#ibcon#about to read 6, iclass 24, count 0 2006.173.13:32:35.38#ibcon#read 6, iclass 24, count 0 2006.173.13:32:35.38#ibcon#end of sib2, iclass 24, count 0 2006.173.13:32:35.38#ibcon#*after write, iclass 24, count 0 2006.173.13:32:35.38#ibcon#*before return 0, iclass 24, count 0 2006.173.13:32:35.38#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.13:32:35.38#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.13:32:35.38#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.13:32:35.38#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.13:32:35.39$vck44/vb=8,4 2006.173.13:32:35.39#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.13:32:35.39#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.13:32:35.39#ibcon#ireg 11 cls_cnt 2 2006.173.13:32:35.39#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.13:32:35.43#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.13:32:35.43#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.13:32:35.43#ibcon#enter wrdev, iclass 26, count 2 2006.173.13:32:35.43#ibcon#first serial, iclass 26, count 2 2006.173.13:32:35.43#ibcon#enter sib2, iclass 26, count 2 2006.173.13:32:35.43#ibcon#flushed, iclass 26, count 2 2006.173.13:32:35.43#ibcon#about to write, iclass 26, count 2 2006.173.13:32:35.43#ibcon#wrote, iclass 26, count 2 2006.173.13:32:35.43#ibcon#about to read 3, iclass 26, count 2 2006.173.13:32:35.45#ibcon#read 3, iclass 26, count 2 2006.173.13:32:35.45#ibcon#about to read 4, iclass 26, count 2 2006.173.13:32:35.45#ibcon#read 4, iclass 26, count 2 2006.173.13:32:35.45#ibcon#about to read 5, iclass 26, count 2 2006.173.13:32:35.45#ibcon#read 5, iclass 26, count 2 2006.173.13:32:35.45#ibcon#about to read 6, iclass 26, count 2 2006.173.13:32:35.45#ibcon#read 6, iclass 26, count 2 2006.173.13:32:35.45#ibcon#end of sib2, iclass 26, count 2 2006.173.13:32:35.45#ibcon#*mode == 0, iclass 26, count 2 2006.173.13:32:35.45#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.13:32:35.45#ibcon#[27=AT08-04\r\n] 2006.173.13:32:35.45#ibcon#*before write, iclass 26, count 2 2006.173.13:32:35.45#ibcon#enter sib2, iclass 26, count 2 2006.173.13:32:35.45#ibcon#flushed, iclass 26, count 2 2006.173.13:32:35.45#ibcon#about to write, iclass 26, count 2 2006.173.13:32:35.45#ibcon#wrote, iclass 26, count 2 2006.173.13:32:35.45#ibcon#about to read 3, iclass 26, count 2 2006.173.13:32:35.48#ibcon#read 3, iclass 26, count 2 2006.173.13:32:35.48#ibcon#about to read 4, iclass 26, count 2 2006.173.13:32:35.48#ibcon#read 4, iclass 26, count 2 2006.173.13:32:35.48#ibcon#about to read 5, iclass 26, count 2 2006.173.13:32:35.48#ibcon#read 5, iclass 26, count 2 2006.173.13:32:35.48#ibcon#about to read 6, iclass 26, count 2 2006.173.13:32:35.48#ibcon#read 6, iclass 26, count 2 2006.173.13:32:35.48#ibcon#end of sib2, iclass 26, count 2 2006.173.13:32:35.48#ibcon#*after write, iclass 26, count 2 2006.173.13:32:35.48#ibcon#*before return 0, iclass 26, count 2 2006.173.13:32:35.48#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.13:32:35.48#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.13:32:35.48#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.13:32:35.48#ibcon#ireg 7 cls_cnt 0 2006.173.13:32:35.48#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.13:32:35.60#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.13:32:35.60#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.13:32:35.60#ibcon#enter wrdev, iclass 26, count 0 2006.173.13:32:35.60#ibcon#first serial, iclass 26, count 0 2006.173.13:32:35.60#ibcon#enter sib2, iclass 26, count 0 2006.173.13:32:35.60#ibcon#flushed, iclass 26, count 0 2006.173.13:32:35.60#ibcon#about to write, iclass 26, count 0 2006.173.13:32:35.60#ibcon#wrote, iclass 26, count 0 2006.173.13:32:35.60#ibcon#about to read 3, iclass 26, count 0 2006.173.13:32:35.62#ibcon#read 3, iclass 26, count 0 2006.173.13:32:35.62#ibcon#about to read 4, iclass 26, count 0 2006.173.13:32:35.62#ibcon#read 4, iclass 26, count 0 2006.173.13:32:35.62#ibcon#about to read 5, iclass 26, count 0 2006.173.13:32:35.62#ibcon#read 5, iclass 26, count 0 2006.173.13:32:35.62#ibcon#about to read 6, iclass 26, count 0 2006.173.13:32:35.62#ibcon#read 6, iclass 26, count 0 2006.173.13:32:35.62#ibcon#end of sib2, iclass 26, count 0 2006.173.13:32:35.62#ibcon#*mode == 0, iclass 26, count 0 2006.173.13:32:35.62#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.13:32:35.62#ibcon#[27=USB\r\n] 2006.173.13:32:35.62#ibcon#*before write, iclass 26, count 0 2006.173.13:32:35.62#ibcon#enter sib2, iclass 26, count 0 2006.173.13:32:35.62#ibcon#flushed, iclass 26, count 0 2006.173.13:32:35.62#ibcon#about to write, iclass 26, count 0 2006.173.13:32:35.62#ibcon#wrote, iclass 26, count 0 2006.173.13:32:35.62#ibcon#about to read 3, iclass 26, count 0 2006.173.13:32:35.65#ibcon#read 3, iclass 26, count 0 2006.173.13:32:35.65#ibcon#about to read 4, iclass 26, count 0 2006.173.13:32:35.65#ibcon#read 4, iclass 26, count 0 2006.173.13:32:35.65#ibcon#about to read 5, iclass 26, count 0 2006.173.13:32:35.65#ibcon#read 5, iclass 26, count 0 2006.173.13:32:35.65#ibcon#about to read 6, iclass 26, count 0 2006.173.13:32:35.65#ibcon#read 6, iclass 26, count 0 2006.173.13:32:35.65#ibcon#end of sib2, iclass 26, count 0 2006.173.13:32:35.65#ibcon#*after write, iclass 26, count 0 2006.173.13:32:35.65#ibcon#*before return 0, iclass 26, count 0 2006.173.13:32:35.65#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.13:32:35.65#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.13:32:35.65#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.13:32:35.65#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.13:32:35.66$vck44/vabw=wide 2006.173.13:32:35.66#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.13:32:35.66#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.13:32:35.66#ibcon#ireg 8 cls_cnt 0 2006.173.13:32:35.66#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.13:32:35.66#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.13:32:35.66#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.13:32:35.66#ibcon#enter wrdev, iclass 28, count 0 2006.173.13:32:35.66#ibcon#first serial, iclass 28, count 0 2006.173.13:32:35.66#ibcon#enter sib2, iclass 28, count 0 2006.173.13:32:35.66#ibcon#flushed, iclass 28, count 0 2006.173.13:32:35.66#ibcon#about to write, iclass 28, count 0 2006.173.13:32:35.66#ibcon#wrote, iclass 28, count 0 2006.173.13:32:35.66#ibcon#about to read 3, iclass 28, count 0 2006.173.13:32:35.67#ibcon#read 3, iclass 28, count 0 2006.173.13:32:35.67#ibcon#about to read 4, iclass 28, count 0 2006.173.13:32:35.67#ibcon#read 4, iclass 28, count 0 2006.173.13:32:35.67#ibcon#about to read 5, iclass 28, count 0 2006.173.13:32:35.67#ibcon#read 5, iclass 28, count 0 2006.173.13:32:35.67#ibcon#about to read 6, iclass 28, count 0 2006.173.13:32:35.67#ibcon#read 6, iclass 28, count 0 2006.173.13:32:35.67#ibcon#end of sib2, iclass 28, count 0 2006.173.13:32:35.67#ibcon#*mode == 0, iclass 28, count 0 2006.173.13:32:35.67#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.13:32:35.67#ibcon#[25=BW32\r\n] 2006.173.13:32:35.67#ibcon#*before write, iclass 28, count 0 2006.173.13:32:35.67#ibcon#enter sib2, iclass 28, count 0 2006.173.13:32:35.67#ibcon#flushed, iclass 28, count 0 2006.173.13:32:35.67#ibcon#about to write, iclass 28, count 0 2006.173.13:32:35.67#ibcon#wrote, iclass 28, count 0 2006.173.13:32:35.67#ibcon#about to read 3, iclass 28, count 0 2006.173.13:32:35.70#ibcon#read 3, iclass 28, count 0 2006.173.13:32:35.70#ibcon#about to read 4, iclass 28, count 0 2006.173.13:32:35.70#ibcon#read 4, iclass 28, count 0 2006.173.13:32:35.70#ibcon#about to read 5, iclass 28, count 0 2006.173.13:32:35.70#ibcon#read 5, iclass 28, count 0 2006.173.13:32:35.70#ibcon#about to read 6, iclass 28, count 0 2006.173.13:32:35.70#ibcon#read 6, iclass 28, count 0 2006.173.13:32:35.70#ibcon#end of sib2, iclass 28, count 0 2006.173.13:32:35.70#ibcon#*after write, iclass 28, count 0 2006.173.13:32:35.70#ibcon#*before return 0, iclass 28, count 0 2006.173.13:32:35.70#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.13:32:35.70#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.13:32:35.70#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.13:32:35.70#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.13:32:35.71$vck44/vbbw=wide 2006.173.13:32:35.71#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.13:32:35.71#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.13:32:35.71#ibcon#ireg 8 cls_cnt 0 2006.173.13:32:35.71#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.13:32:35.76#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.13:32:35.76#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.13:32:35.76#ibcon#enter wrdev, iclass 30, count 0 2006.173.13:32:35.76#ibcon#first serial, iclass 30, count 0 2006.173.13:32:35.76#ibcon#enter sib2, iclass 30, count 0 2006.173.13:32:35.76#ibcon#flushed, iclass 30, count 0 2006.173.13:32:35.76#ibcon#about to write, iclass 30, count 0 2006.173.13:32:35.76#ibcon#wrote, iclass 30, count 0 2006.173.13:32:35.76#ibcon#about to read 3, iclass 30, count 0 2006.173.13:32:35.78#ibcon#read 3, iclass 30, count 0 2006.173.13:32:35.78#ibcon#about to read 4, iclass 30, count 0 2006.173.13:32:35.78#ibcon#read 4, iclass 30, count 0 2006.173.13:32:35.78#ibcon#about to read 5, iclass 30, count 0 2006.173.13:32:35.78#ibcon#read 5, iclass 30, count 0 2006.173.13:32:35.78#ibcon#about to read 6, iclass 30, count 0 2006.173.13:32:35.78#ibcon#read 6, iclass 30, count 0 2006.173.13:32:35.78#ibcon#end of sib2, iclass 30, count 0 2006.173.13:32:35.78#ibcon#*mode == 0, iclass 30, count 0 2006.173.13:32:35.78#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.13:32:35.78#ibcon#[27=BW32\r\n] 2006.173.13:32:35.78#ibcon#*before write, iclass 30, count 0 2006.173.13:32:35.78#ibcon#enter sib2, iclass 30, count 0 2006.173.13:32:35.78#ibcon#flushed, iclass 30, count 0 2006.173.13:32:35.78#ibcon#about to write, iclass 30, count 0 2006.173.13:32:35.78#ibcon#wrote, iclass 30, count 0 2006.173.13:32:35.78#ibcon#about to read 3, iclass 30, count 0 2006.173.13:32:35.81#ibcon#read 3, iclass 30, count 0 2006.173.13:32:35.81#ibcon#about to read 4, iclass 30, count 0 2006.173.13:32:35.81#ibcon#read 4, iclass 30, count 0 2006.173.13:32:35.81#ibcon#about to read 5, iclass 30, count 0 2006.173.13:32:35.81#ibcon#read 5, iclass 30, count 0 2006.173.13:32:35.81#ibcon#about to read 6, iclass 30, count 0 2006.173.13:32:35.81#ibcon#read 6, iclass 30, count 0 2006.173.13:32:35.81#ibcon#end of sib2, iclass 30, count 0 2006.173.13:32:35.81#ibcon#*after write, iclass 30, count 0 2006.173.13:32:35.81#ibcon#*before return 0, iclass 30, count 0 2006.173.13:32:35.81#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.13:32:35.81#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.13:32:35.81#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.13:32:35.81#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.13:32:35.82$setupk4/ifdk4 2006.173.13:32:35.82$ifdk4/lo= 2006.173.13:32:35.82$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.13:32:35.82$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.13:32:35.82$ifdk4/patch= 2006.173.13:32:35.82$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.13:32:35.82$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.13:32:35.82$setupk4/!*+20s 2006.173.13:32:41.37#abcon#<5=/04 0.5 1.3 21.971001003.8\r\n> 2006.173.13:32:41.39#abcon#{5=INTERFACE CLEAR} 2006.173.13:32:41.45#abcon#[5=S1D000X0/0*\r\n] 2006.173.13:32:50.50$setupk4/"tpicd 2006.173.13:32:50.50$setupk4/echo=off 2006.173.13:32:50.50$setupk4/xlog=off 2006.173.13:32:50.51:!2006.173.13:33:59 2006.173.13:32:56.14#trakl#Source acquired 2006.173.13:32:57.15#flagr#flagr/antenna,acquired 2006.173.13:33:59.01:preob 2006.173.13:34:00.15/onsource/TRACKING 2006.173.13:34:00.15:!2006.173.13:34:09 2006.173.13:34:09.01:"tape 2006.173.13:34:09.01:"st=record 2006.173.13:34:09.02:data_valid=on 2006.173.13:34:09.02:midob 2006.173.13:34:10.14/onsource/TRACKING 2006.173.13:34:10.15/wx/21.97,1003.9,100 2006.173.13:34:10.23/cable/+6.5045E-03 2006.173.13:34:11.32/va/01,07,usb,yes,59,63 2006.173.13:34:11.32/va/02,06,usb,yes,58,60 2006.173.13:34:11.32/va/03,05,usb,yes,73,76 2006.173.13:34:11.32/va/04,06,usb,yes,60,63 2006.173.13:34:11.32/va/05,04,usb,yes,48,49 2006.173.13:34:11.32/va/06,03,usb,yes,66,66 2006.173.13:34:11.32/va/07,04,usb,yes,54,56 2006.173.13:34:11.32/va/08,04,usb,yes,47,55 2006.173.13:34:11.55/valo/01,524.99,yes,locked 2006.173.13:34:11.55/valo/02,534.99,yes,locked 2006.173.13:34:11.55/valo/03,564.99,yes,locked 2006.173.13:34:11.55/valo/04,624.99,yes,locked 2006.173.13:34:11.55/valo/05,734.99,yes,locked 2006.173.13:34:11.55/valo/06,814.99,yes,locked 2006.173.13:34:11.55/valo/07,864.99,yes,locked 2006.173.13:34:11.55/valo/08,884.99,yes,locked 2006.173.13:34:12.64/vb/01,04,usb,yes,33,32 2006.173.13:34:12.64/vb/02,04,usb,yes,36,36 2006.173.13:34:12.64/vb/03,04,usb,yes,33,36 2006.173.13:34:12.64/vb/04,04,usb,yes,37,36 2006.173.13:34:12.64/vb/05,04,usb,yes,30,32 2006.173.13:34:12.64/vb/06,04,usb,yes,35,31 2006.173.13:34:12.64/vb/07,04,usb,yes,34,34 2006.173.13:34:12.64/vb/08,04,usb,yes,32,35 2006.173.13:34:12.87/vblo/01,629.99,yes,locked 2006.173.13:34:12.87/vblo/02,634.99,yes,locked 2006.173.13:34:12.87/vblo/03,649.99,yes,locked 2006.173.13:34:12.87/vblo/04,679.99,yes,locked 2006.173.13:34:12.87/vblo/05,709.99,yes,locked 2006.173.13:34:12.87/vblo/06,719.99,yes,locked 2006.173.13:34:12.87/vblo/07,734.99,yes,locked 2006.173.13:34:12.87/vblo/08,744.99,yes,locked 2006.173.13:34:13.02/vabw/8 2006.173.13:34:13.17/vbbw/8 2006.173.13:34:13.26/xfe/off,on,15.5 2006.173.13:34:13.65/ifatt/23,28,28,28 2006.173.13:34:14.07/fmout-gps/S +3.82E-07 2006.173.13:34:14.12:!2006.173.13:34:49 2006.173.13:34:49.01:data_valid=off 2006.173.13:34:49.02:"et 2006.173.13:34:49.02:!+3s 2006.173.13:34:52.04:"tape 2006.173.13:34:52.04:postob 2006.173.13:34:52.21/cable/+6.5047E-03 2006.173.13:34:52.21/wx/21.97,1003.8,100 2006.173.13:34:52.27/fmout-gps/S +3.83E-07 2006.173.13:34:52.27:scan_name=173-1335,jd0606,150 2006.173.13:34:52.28:source=2201+315,220314.98,314538.3,2000.0,cw 2006.173.13:34:53.14#flagr#flagr/antenna,new-source 2006.173.13:34:53.15:checkk5 2006.173.13:34:53.55/chk_autoobs//k5ts1/ autoobs is running! 2006.173.13:34:53.94/chk_autoobs//k5ts2/ autoobs is running! 2006.173.13:34:54.34/chk_autoobs//k5ts3/ autoobs is running! 2006.173.13:34:54.74/chk_autoobs//k5ts4/ autoobs is running! 2006.173.13:34:55.14/chk_obsdata//k5ts1/T1731334??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.13:34:55.56/chk_obsdata//k5ts2/T1731334??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.13:34:55.96/chk_obsdata//k5ts3/T1731334??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.13:34:56.38/chk_obsdata//k5ts4/T1731334??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.13:34:57.10/k5log//k5ts1_log_newline 2006.173.13:34:57.80/k5log//k5ts2_log_newline 2006.173.13:34:58.51/k5log//k5ts3_log_newline 2006.173.13:34:59.23/k5log//k5ts4_log_newline 2006.173.13:34:59.25/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.13:34:59.25:setupk4=1 2006.173.13:34:59.25$setupk4/echo=on 2006.173.13:34:59.25$setupk4/pcalon 2006.173.13:34:59.25$pcalon/"no phase cal control is implemented here 2006.173.13:34:59.25$setupk4/"tpicd=stop 2006.173.13:34:59.25$setupk4/"rec=synch_on 2006.173.13:34:59.25$setupk4/"rec_mode=128 2006.173.13:34:59.25$setupk4/!* 2006.173.13:34:59.25$setupk4/recpk4 2006.173.13:34:59.25$recpk4/recpatch= 2006.173.13:34:59.26$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.13:34:59.26$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.13:34:59.26$setupk4/vck44 2006.173.13:34:59.26$vck44/valo=1,524.99 2006.173.13:34:59.26#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.13:34:59.26#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.13:34:59.26#ibcon#ireg 17 cls_cnt 0 2006.173.13:34:59.26#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.13:34:59.26#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.13:34:59.26#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.13:34:59.26#ibcon#enter wrdev, iclass 19, count 0 2006.173.13:34:59.26#ibcon#first serial, iclass 19, count 0 2006.173.13:34:59.26#ibcon#enter sib2, iclass 19, count 0 2006.173.13:34:59.26#ibcon#flushed, iclass 19, count 0 2006.173.13:34:59.26#ibcon#about to write, iclass 19, count 0 2006.173.13:34:59.26#ibcon#wrote, iclass 19, count 0 2006.173.13:34:59.26#ibcon#about to read 3, iclass 19, count 0 2006.173.13:34:59.27#ibcon#read 3, iclass 19, count 0 2006.173.13:34:59.27#ibcon#about to read 4, iclass 19, count 0 2006.173.13:34:59.27#ibcon#read 4, iclass 19, count 0 2006.173.13:34:59.27#ibcon#about to read 5, iclass 19, count 0 2006.173.13:34:59.27#ibcon#read 5, iclass 19, count 0 2006.173.13:34:59.27#ibcon#about to read 6, iclass 19, count 0 2006.173.13:34:59.27#ibcon#read 6, iclass 19, count 0 2006.173.13:34:59.27#ibcon#end of sib2, iclass 19, count 0 2006.173.13:34:59.27#ibcon#*mode == 0, iclass 19, count 0 2006.173.13:34:59.27#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.13:34:59.27#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.13:34:59.27#ibcon#*before write, iclass 19, count 0 2006.173.13:34:59.27#ibcon#enter sib2, iclass 19, count 0 2006.173.13:34:59.27#ibcon#flushed, iclass 19, count 0 2006.173.13:34:59.27#ibcon#about to write, iclass 19, count 0 2006.173.13:34:59.27#ibcon#wrote, iclass 19, count 0 2006.173.13:34:59.27#ibcon#about to read 3, iclass 19, count 0 2006.173.13:34:59.32#ibcon#read 3, iclass 19, count 0 2006.173.13:34:59.32#ibcon#about to read 4, iclass 19, count 0 2006.173.13:34:59.32#ibcon#read 4, iclass 19, count 0 2006.173.13:34:59.32#ibcon#about to read 5, iclass 19, count 0 2006.173.13:34:59.32#ibcon#read 5, iclass 19, count 0 2006.173.13:34:59.32#ibcon#about to read 6, iclass 19, count 0 2006.173.13:34:59.32#ibcon#read 6, iclass 19, count 0 2006.173.13:34:59.32#ibcon#end of sib2, iclass 19, count 0 2006.173.13:34:59.32#ibcon#*after write, iclass 19, count 0 2006.173.13:34:59.32#ibcon#*before return 0, iclass 19, count 0 2006.173.13:34:59.32#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.13:34:59.32#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.13:34:59.32#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.13:34:59.32#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.13:34:59.32$vck44/va=1,7 2006.173.13:34:59.32#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.13:34:59.32#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.13:34:59.32#ibcon#ireg 11 cls_cnt 2 2006.173.13:34:59.32#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.13:34:59.32#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.13:34:59.32#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.13:34:59.32#ibcon#enter wrdev, iclass 21, count 2 2006.173.13:34:59.32#ibcon#first serial, iclass 21, count 2 2006.173.13:34:59.32#ibcon#enter sib2, iclass 21, count 2 2006.173.13:34:59.32#ibcon#flushed, iclass 21, count 2 2006.173.13:34:59.32#ibcon#about to write, iclass 21, count 2 2006.173.13:34:59.32#ibcon#wrote, iclass 21, count 2 2006.173.13:34:59.32#ibcon#about to read 3, iclass 21, count 2 2006.173.13:34:59.34#ibcon#read 3, iclass 21, count 2 2006.173.13:34:59.34#ibcon#about to read 4, iclass 21, count 2 2006.173.13:34:59.34#ibcon#read 4, iclass 21, count 2 2006.173.13:34:59.34#ibcon#about to read 5, iclass 21, count 2 2006.173.13:34:59.34#ibcon#read 5, iclass 21, count 2 2006.173.13:34:59.34#ibcon#about to read 6, iclass 21, count 2 2006.173.13:34:59.34#ibcon#read 6, iclass 21, count 2 2006.173.13:34:59.34#ibcon#end of sib2, iclass 21, count 2 2006.173.13:34:59.34#ibcon#*mode == 0, iclass 21, count 2 2006.173.13:34:59.34#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.13:34:59.34#ibcon#[25=AT01-07\r\n] 2006.173.13:34:59.34#ibcon#*before write, iclass 21, count 2 2006.173.13:34:59.34#ibcon#enter sib2, iclass 21, count 2 2006.173.13:34:59.34#ibcon#flushed, iclass 21, count 2 2006.173.13:34:59.34#ibcon#about to write, iclass 21, count 2 2006.173.13:34:59.34#ibcon#wrote, iclass 21, count 2 2006.173.13:34:59.34#ibcon#about to read 3, iclass 21, count 2 2006.173.13:34:59.37#ibcon#read 3, iclass 21, count 2 2006.173.13:34:59.37#ibcon#about to read 4, iclass 21, count 2 2006.173.13:34:59.37#ibcon#read 4, iclass 21, count 2 2006.173.13:34:59.37#ibcon#about to read 5, iclass 21, count 2 2006.173.13:34:59.37#ibcon#read 5, iclass 21, count 2 2006.173.13:34:59.37#ibcon#about to read 6, iclass 21, count 2 2006.173.13:34:59.37#ibcon#read 6, iclass 21, count 2 2006.173.13:34:59.37#ibcon#end of sib2, iclass 21, count 2 2006.173.13:34:59.37#ibcon#*after write, iclass 21, count 2 2006.173.13:34:59.37#ibcon#*before return 0, iclass 21, count 2 2006.173.13:34:59.37#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.13:34:59.37#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.13:34:59.37#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.13:34:59.37#ibcon#ireg 7 cls_cnt 0 2006.173.13:34:59.37#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.13:34:59.49#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.13:34:59.49#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.13:34:59.49#ibcon#enter wrdev, iclass 21, count 0 2006.173.13:34:59.49#ibcon#first serial, iclass 21, count 0 2006.173.13:34:59.49#ibcon#enter sib2, iclass 21, count 0 2006.173.13:34:59.49#ibcon#flushed, iclass 21, count 0 2006.173.13:34:59.49#ibcon#about to write, iclass 21, count 0 2006.173.13:34:59.49#ibcon#wrote, iclass 21, count 0 2006.173.13:34:59.49#ibcon#about to read 3, iclass 21, count 0 2006.173.13:34:59.51#ibcon#read 3, iclass 21, count 0 2006.173.13:34:59.51#ibcon#about to read 4, iclass 21, count 0 2006.173.13:34:59.51#ibcon#read 4, iclass 21, count 0 2006.173.13:34:59.51#ibcon#about to read 5, iclass 21, count 0 2006.173.13:34:59.51#ibcon#read 5, iclass 21, count 0 2006.173.13:34:59.51#ibcon#about to read 6, iclass 21, count 0 2006.173.13:34:59.51#ibcon#read 6, iclass 21, count 0 2006.173.13:34:59.51#ibcon#end of sib2, iclass 21, count 0 2006.173.13:34:59.51#ibcon#*mode == 0, iclass 21, count 0 2006.173.13:34:59.51#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.13:34:59.51#ibcon#[25=USB\r\n] 2006.173.13:34:59.51#ibcon#*before write, iclass 21, count 0 2006.173.13:34:59.51#ibcon#enter sib2, iclass 21, count 0 2006.173.13:34:59.51#ibcon#flushed, iclass 21, count 0 2006.173.13:34:59.51#ibcon#about to write, iclass 21, count 0 2006.173.13:34:59.51#ibcon#wrote, iclass 21, count 0 2006.173.13:34:59.51#ibcon#about to read 3, iclass 21, count 0 2006.173.13:34:59.54#ibcon#read 3, iclass 21, count 0 2006.173.13:34:59.54#ibcon#about to read 4, iclass 21, count 0 2006.173.13:34:59.54#ibcon#read 4, iclass 21, count 0 2006.173.13:34:59.54#ibcon#about to read 5, iclass 21, count 0 2006.173.13:34:59.54#ibcon#read 5, iclass 21, count 0 2006.173.13:34:59.54#ibcon#about to read 6, iclass 21, count 0 2006.173.13:34:59.54#ibcon#read 6, iclass 21, count 0 2006.173.13:34:59.54#ibcon#end of sib2, iclass 21, count 0 2006.173.13:34:59.54#ibcon#*after write, iclass 21, count 0 2006.173.13:34:59.54#ibcon#*before return 0, iclass 21, count 0 2006.173.13:34:59.54#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.13:34:59.54#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.13:34:59.54#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.13:34:59.54#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.13:34:59.54$vck44/valo=2,534.99 2006.173.13:34:59.54#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.13:34:59.54#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.13:34:59.54#ibcon#ireg 17 cls_cnt 0 2006.173.13:34:59.54#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.13:34:59.54#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.13:34:59.54#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.13:34:59.54#ibcon#enter wrdev, iclass 23, count 0 2006.173.13:34:59.54#ibcon#first serial, iclass 23, count 0 2006.173.13:34:59.54#ibcon#enter sib2, iclass 23, count 0 2006.173.13:34:59.54#ibcon#flushed, iclass 23, count 0 2006.173.13:34:59.54#ibcon#about to write, iclass 23, count 0 2006.173.13:34:59.54#ibcon#wrote, iclass 23, count 0 2006.173.13:34:59.54#ibcon#about to read 3, iclass 23, count 0 2006.173.13:34:59.56#ibcon#read 3, iclass 23, count 0 2006.173.13:34:59.56#ibcon#about to read 4, iclass 23, count 0 2006.173.13:34:59.56#ibcon#read 4, iclass 23, count 0 2006.173.13:34:59.56#ibcon#about to read 5, iclass 23, count 0 2006.173.13:34:59.56#ibcon#read 5, iclass 23, count 0 2006.173.13:34:59.56#ibcon#about to read 6, iclass 23, count 0 2006.173.13:34:59.56#ibcon#read 6, iclass 23, count 0 2006.173.13:34:59.56#ibcon#end of sib2, iclass 23, count 0 2006.173.13:34:59.56#ibcon#*mode == 0, iclass 23, count 0 2006.173.13:34:59.56#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.13:34:59.56#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.13:34:59.56#ibcon#*before write, iclass 23, count 0 2006.173.13:34:59.56#ibcon#enter sib2, iclass 23, count 0 2006.173.13:34:59.56#ibcon#flushed, iclass 23, count 0 2006.173.13:34:59.56#ibcon#about to write, iclass 23, count 0 2006.173.13:34:59.56#ibcon#wrote, iclass 23, count 0 2006.173.13:34:59.56#ibcon#about to read 3, iclass 23, count 0 2006.173.13:34:59.60#ibcon#read 3, iclass 23, count 0 2006.173.13:34:59.60#ibcon#about to read 4, iclass 23, count 0 2006.173.13:34:59.60#ibcon#read 4, iclass 23, count 0 2006.173.13:34:59.60#ibcon#about to read 5, iclass 23, count 0 2006.173.13:34:59.60#ibcon#read 5, iclass 23, count 0 2006.173.13:34:59.60#ibcon#about to read 6, iclass 23, count 0 2006.173.13:34:59.60#ibcon#read 6, iclass 23, count 0 2006.173.13:34:59.60#ibcon#end of sib2, iclass 23, count 0 2006.173.13:34:59.60#ibcon#*after write, iclass 23, count 0 2006.173.13:34:59.60#ibcon#*before return 0, iclass 23, count 0 2006.173.13:34:59.60#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.13:34:59.60#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.13:34:59.60#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.13:34:59.60#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.13:34:59.60$vck44/va=2,6 2006.173.13:34:59.60#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.13:34:59.60#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.13:34:59.60#ibcon#ireg 11 cls_cnt 2 2006.173.13:34:59.60#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.13:34:59.66#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.13:34:59.66#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.13:34:59.66#ibcon#enter wrdev, iclass 25, count 2 2006.173.13:34:59.66#ibcon#first serial, iclass 25, count 2 2006.173.13:34:59.66#ibcon#enter sib2, iclass 25, count 2 2006.173.13:34:59.66#ibcon#flushed, iclass 25, count 2 2006.173.13:34:59.66#ibcon#about to write, iclass 25, count 2 2006.173.13:34:59.66#ibcon#wrote, iclass 25, count 2 2006.173.13:34:59.66#ibcon#about to read 3, iclass 25, count 2 2006.173.13:34:59.68#ibcon#read 3, iclass 25, count 2 2006.173.13:34:59.68#ibcon#about to read 4, iclass 25, count 2 2006.173.13:34:59.68#ibcon#read 4, iclass 25, count 2 2006.173.13:34:59.68#ibcon#about to read 5, iclass 25, count 2 2006.173.13:34:59.68#ibcon#read 5, iclass 25, count 2 2006.173.13:34:59.68#ibcon#about to read 6, iclass 25, count 2 2006.173.13:34:59.68#ibcon#read 6, iclass 25, count 2 2006.173.13:34:59.68#ibcon#end of sib2, iclass 25, count 2 2006.173.13:34:59.68#ibcon#*mode == 0, iclass 25, count 2 2006.173.13:34:59.68#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.13:34:59.68#ibcon#[25=AT02-06\r\n] 2006.173.13:34:59.68#ibcon#*before write, iclass 25, count 2 2006.173.13:34:59.68#ibcon#enter sib2, iclass 25, count 2 2006.173.13:34:59.68#ibcon#flushed, iclass 25, count 2 2006.173.13:34:59.68#ibcon#about to write, iclass 25, count 2 2006.173.13:34:59.68#ibcon#wrote, iclass 25, count 2 2006.173.13:34:59.68#ibcon#about to read 3, iclass 25, count 2 2006.173.13:34:59.71#ibcon#read 3, iclass 25, count 2 2006.173.13:34:59.71#ibcon#about to read 4, iclass 25, count 2 2006.173.13:34:59.71#ibcon#read 4, iclass 25, count 2 2006.173.13:34:59.71#ibcon#about to read 5, iclass 25, count 2 2006.173.13:34:59.71#ibcon#read 5, iclass 25, count 2 2006.173.13:34:59.71#ibcon#about to read 6, iclass 25, count 2 2006.173.13:34:59.71#ibcon#read 6, iclass 25, count 2 2006.173.13:34:59.71#ibcon#end of sib2, iclass 25, count 2 2006.173.13:34:59.71#ibcon#*after write, iclass 25, count 2 2006.173.13:34:59.71#ibcon#*before return 0, iclass 25, count 2 2006.173.13:34:59.71#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.13:34:59.71#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.13:34:59.71#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.13:34:59.71#ibcon#ireg 7 cls_cnt 0 2006.173.13:34:59.71#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.13:34:59.83#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.13:34:59.83#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.13:34:59.83#ibcon#enter wrdev, iclass 25, count 0 2006.173.13:34:59.83#ibcon#first serial, iclass 25, count 0 2006.173.13:34:59.83#ibcon#enter sib2, iclass 25, count 0 2006.173.13:34:59.83#ibcon#flushed, iclass 25, count 0 2006.173.13:34:59.83#ibcon#about to write, iclass 25, count 0 2006.173.13:34:59.83#ibcon#wrote, iclass 25, count 0 2006.173.13:34:59.83#ibcon#about to read 3, iclass 25, count 0 2006.173.13:34:59.85#ibcon#read 3, iclass 25, count 0 2006.173.13:34:59.85#ibcon#about to read 4, iclass 25, count 0 2006.173.13:34:59.85#ibcon#read 4, iclass 25, count 0 2006.173.13:34:59.85#ibcon#about to read 5, iclass 25, count 0 2006.173.13:34:59.85#ibcon#read 5, iclass 25, count 0 2006.173.13:34:59.85#ibcon#about to read 6, iclass 25, count 0 2006.173.13:34:59.85#ibcon#read 6, iclass 25, count 0 2006.173.13:34:59.85#ibcon#end of sib2, iclass 25, count 0 2006.173.13:34:59.85#ibcon#*mode == 0, iclass 25, count 0 2006.173.13:34:59.85#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.13:34:59.85#ibcon#[25=USB\r\n] 2006.173.13:34:59.85#ibcon#*before write, iclass 25, count 0 2006.173.13:34:59.85#ibcon#enter sib2, iclass 25, count 0 2006.173.13:34:59.85#ibcon#flushed, iclass 25, count 0 2006.173.13:34:59.85#ibcon#about to write, iclass 25, count 0 2006.173.13:34:59.85#ibcon#wrote, iclass 25, count 0 2006.173.13:34:59.85#ibcon#about to read 3, iclass 25, count 0 2006.173.13:34:59.88#ibcon#read 3, iclass 25, count 0 2006.173.13:34:59.88#ibcon#about to read 4, iclass 25, count 0 2006.173.13:34:59.88#ibcon#read 4, iclass 25, count 0 2006.173.13:34:59.88#ibcon#about to read 5, iclass 25, count 0 2006.173.13:34:59.88#ibcon#read 5, iclass 25, count 0 2006.173.13:34:59.88#ibcon#about to read 6, iclass 25, count 0 2006.173.13:34:59.88#ibcon#read 6, iclass 25, count 0 2006.173.13:34:59.88#ibcon#end of sib2, iclass 25, count 0 2006.173.13:34:59.88#ibcon#*after write, iclass 25, count 0 2006.173.13:34:59.88#ibcon#*before return 0, iclass 25, count 0 2006.173.13:34:59.88#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.13:34:59.88#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.13:34:59.88#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.13:34:59.88#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.13:34:59.88$vck44/valo=3,564.99 2006.173.13:34:59.88#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.13:34:59.88#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.13:34:59.88#ibcon#ireg 17 cls_cnt 0 2006.173.13:34:59.88#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.13:34:59.88#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.13:34:59.88#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.13:34:59.88#ibcon#enter wrdev, iclass 27, count 0 2006.173.13:34:59.88#ibcon#first serial, iclass 27, count 0 2006.173.13:34:59.88#ibcon#enter sib2, iclass 27, count 0 2006.173.13:34:59.88#ibcon#flushed, iclass 27, count 0 2006.173.13:34:59.88#ibcon#about to write, iclass 27, count 0 2006.173.13:34:59.88#ibcon#wrote, iclass 27, count 0 2006.173.13:34:59.88#ibcon#about to read 3, iclass 27, count 0 2006.173.13:34:59.90#ibcon#read 3, iclass 27, count 0 2006.173.13:34:59.90#ibcon#about to read 4, iclass 27, count 0 2006.173.13:34:59.90#ibcon#read 4, iclass 27, count 0 2006.173.13:34:59.90#ibcon#about to read 5, iclass 27, count 0 2006.173.13:34:59.90#ibcon#read 5, iclass 27, count 0 2006.173.13:34:59.90#ibcon#about to read 6, iclass 27, count 0 2006.173.13:34:59.90#ibcon#read 6, iclass 27, count 0 2006.173.13:34:59.90#ibcon#end of sib2, iclass 27, count 0 2006.173.13:34:59.90#ibcon#*mode == 0, iclass 27, count 0 2006.173.13:34:59.90#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.13:34:59.90#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.13:34:59.90#ibcon#*before write, iclass 27, count 0 2006.173.13:34:59.90#ibcon#enter sib2, iclass 27, count 0 2006.173.13:34:59.90#ibcon#flushed, iclass 27, count 0 2006.173.13:34:59.90#ibcon#about to write, iclass 27, count 0 2006.173.13:34:59.90#ibcon#wrote, iclass 27, count 0 2006.173.13:34:59.90#ibcon#about to read 3, iclass 27, count 0 2006.173.13:34:59.94#ibcon#read 3, iclass 27, count 0 2006.173.13:34:59.94#ibcon#about to read 4, iclass 27, count 0 2006.173.13:34:59.94#ibcon#read 4, iclass 27, count 0 2006.173.13:34:59.94#ibcon#about to read 5, iclass 27, count 0 2006.173.13:34:59.94#ibcon#read 5, iclass 27, count 0 2006.173.13:34:59.94#ibcon#about to read 6, iclass 27, count 0 2006.173.13:34:59.94#ibcon#read 6, iclass 27, count 0 2006.173.13:34:59.94#ibcon#end of sib2, iclass 27, count 0 2006.173.13:34:59.94#ibcon#*after write, iclass 27, count 0 2006.173.13:34:59.94#ibcon#*before return 0, iclass 27, count 0 2006.173.13:34:59.94#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.13:34:59.94#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.13:34:59.94#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.13:34:59.94#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.13:34:59.94$vck44/va=3,5 2006.173.13:34:59.94#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.13:34:59.94#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.13:34:59.94#ibcon#ireg 11 cls_cnt 2 2006.173.13:34:59.94#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.13:35:00.00#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.13:35:00.00#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.13:35:00.00#ibcon#enter wrdev, iclass 29, count 2 2006.173.13:35:00.00#ibcon#first serial, iclass 29, count 2 2006.173.13:35:00.00#ibcon#enter sib2, iclass 29, count 2 2006.173.13:35:00.00#ibcon#flushed, iclass 29, count 2 2006.173.13:35:00.00#ibcon#about to write, iclass 29, count 2 2006.173.13:35:00.00#ibcon#wrote, iclass 29, count 2 2006.173.13:35:00.00#ibcon#about to read 3, iclass 29, count 2 2006.173.13:35:00.02#ibcon#read 3, iclass 29, count 2 2006.173.13:35:00.02#ibcon#about to read 4, iclass 29, count 2 2006.173.13:35:00.02#ibcon#read 4, iclass 29, count 2 2006.173.13:35:00.02#ibcon#about to read 5, iclass 29, count 2 2006.173.13:35:00.02#ibcon#read 5, iclass 29, count 2 2006.173.13:35:00.02#ibcon#about to read 6, iclass 29, count 2 2006.173.13:35:00.02#ibcon#read 6, iclass 29, count 2 2006.173.13:35:00.02#ibcon#end of sib2, iclass 29, count 2 2006.173.13:35:00.02#ibcon#*mode == 0, iclass 29, count 2 2006.173.13:35:00.02#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.13:35:00.02#ibcon#[25=AT03-05\r\n] 2006.173.13:35:00.02#ibcon#*before write, iclass 29, count 2 2006.173.13:35:00.02#ibcon#enter sib2, iclass 29, count 2 2006.173.13:35:00.02#ibcon#flushed, iclass 29, count 2 2006.173.13:35:00.02#ibcon#about to write, iclass 29, count 2 2006.173.13:35:00.02#ibcon#wrote, iclass 29, count 2 2006.173.13:35:00.02#ibcon#about to read 3, iclass 29, count 2 2006.173.13:35:00.05#ibcon#read 3, iclass 29, count 2 2006.173.13:35:00.05#ibcon#about to read 4, iclass 29, count 2 2006.173.13:35:00.05#ibcon#read 4, iclass 29, count 2 2006.173.13:35:00.05#ibcon#about to read 5, iclass 29, count 2 2006.173.13:35:00.05#ibcon#read 5, iclass 29, count 2 2006.173.13:35:00.05#ibcon#about to read 6, iclass 29, count 2 2006.173.13:35:00.05#ibcon#read 6, iclass 29, count 2 2006.173.13:35:00.05#ibcon#end of sib2, iclass 29, count 2 2006.173.13:35:00.05#ibcon#*after write, iclass 29, count 2 2006.173.13:35:00.05#ibcon#*before return 0, iclass 29, count 2 2006.173.13:35:00.05#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.13:35:00.05#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.13:35:00.05#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.13:35:00.05#ibcon#ireg 7 cls_cnt 0 2006.173.13:35:00.05#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.13:35:00.17#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.13:35:00.17#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.13:35:00.17#ibcon#enter wrdev, iclass 29, count 0 2006.173.13:35:00.17#ibcon#first serial, iclass 29, count 0 2006.173.13:35:00.17#ibcon#enter sib2, iclass 29, count 0 2006.173.13:35:00.17#ibcon#flushed, iclass 29, count 0 2006.173.13:35:00.17#ibcon#about to write, iclass 29, count 0 2006.173.13:35:00.17#ibcon#wrote, iclass 29, count 0 2006.173.13:35:00.17#ibcon#about to read 3, iclass 29, count 0 2006.173.13:35:00.19#ibcon#read 3, iclass 29, count 0 2006.173.13:35:00.19#ibcon#about to read 4, iclass 29, count 0 2006.173.13:35:00.19#ibcon#read 4, iclass 29, count 0 2006.173.13:35:00.19#ibcon#about to read 5, iclass 29, count 0 2006.173.13:35:00.19#ibcon#read 5, iclass 29, count 0 2006.173.13:35:00.19#ibcon#about to read 6, iclass 29, count 0 2006.173.13:35:00.19#ibcon#read 6, iclass 29, count 0 2006.173.13:35:00.19#ibcon#end of sib2, iclass 29, count 0 2006.173.13:35:00.19#ibcon#*mode == 0, iclass 29, count 0 2006.173.13:35:00.19#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.13:35:00.19#ibcon#[25=USB\r\n] 2006.173.13:35:00.19#ibcon#*before write, iclass 29, count 0 2006.173.13:35:00.19#ibcon#enter sib2, iclass 29, count 0 2006.173.13:35:00.19#ibcon#flushed, iclass 29, count 0 2006.173.13:35:00.19#ibcon#about to write, iclass 29, count 0 2006.173.13:35:00.19#ibcon#wrote, iclass 29, count 0 2006.173.13:35:00.19#ibcon#about to read 3, iclass 29, count 0 2006.173.13:35:00.22#ibcon#read 3, iclass 29, count 0 2006.173.13:35:00.22#ibcon#about to read 4, iclass 29, count 0 2006.173.13:35:00.22#ibcon#read 4, iclass 29, count 0 2006.173.13:35:00.22#ibcon#about to read 5, iclass 29, count 0 2006.173.13:35:00.22#ibcon#read 5, iclass 29, count 0 2006.173.13:35:00.22#ibcon#about to read 6, iclass 29, count 0 2006.173.13:35:00.22#ibcon#read 6, iclass 29, count 0 2006.173.13:35:00.22#ibcon#end of sib2, iclass 29, count 0 2006.173.13:35:00.22#ibcon#*after write, iclass 29, count 0 2006.173.13:35:00.22#ibcon#*before return 0, iclass 29, count 0 2006.173.13:35:00.22#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.13:35:00.22#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.13:35:00.22#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.13:35:00.22#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.13:35:00.22$vck44/valo=4,624.99 2006.173.13:35:00.22#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.13:35:00.22#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.13:35:00.22#ibcon#ireg 17 cls_cnt 0 2006.173.13:35:00.22#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.13:35:00.22#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.13:35:00.22#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.13:35:00.22#ibcon#enter wrdev, iclass 31, count 0 2006.173.13:35:00.22#ibcon#first serial, iclass 31, count 0 2006.173.13:35:00.22#ibcon#enter sib2, iclass 31, count 0 2006.173.13:35:00.22#ibcon#flushed, iclass 31, count 0 2006.173.13:35:00.22#ibcon#about to write, iclass 31, count 0 2006.173.13:35:00.23#ibcon#wrote, iclass 31, count 0 2006.173.13:35:00.23#ibcon#about to read 3, iclass 31, count 0 2006.173.13:35:00.24#ibcon#read 3, iclass 31, count 0 2006.173.13:35:00.24#ibcon#about to read 4, iclass 31, count 0 2006.173.13:35:00.24#ibcon#read 4, iclass 31, count 0 2006.173.13:35:00.24#ibcon#about to read 5, iclass 31, count 0 2006.173.13:35:00.24#ibcon#read 5, iclass 31, count 0 2006.173.13:35:00.24#ibcon#about to read 6, iclass 31, count 0 2006.173.13:35:00.24#ibcon#read 6, iclass 31, count 0 2006.173.13:35:00.24#ibcon#end of sib2, iclass 31, count 0 2006.173.13:35:00.24#ibcon#*mode == 0, iclass 31, count 0 2006.173.13:35:00.24#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.13:35:00.24#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.13:35:00.24#ibcon#*before write, iclass 31, count 0 2006.173.13:35:00.24#ibcon#enter sib2, iclass 31, count 0 2006.173.13:35:00.24#ibcon#flushed, iclass 31, count 0 2006.173.13:35:00.24#ibcon#about to write, iclass 31, count 0 2006.173.13:35:00.24#ibcon#wrote, iclass 31, count 0 2006.173.13:35:00.24#ibcon#about to read 3, iclass 31, count 0 2006.173.13:35:00.28#ibcon#read 3, iclass 31, count 0 2006.173.13:35:00.28#ibcon#about to read 4, iclass 31, count 0 2006.173.13:35:00.28#ibcon#read 4, iclass 31, count 0 2006.173.13:35:00.28#ibcon#about to read 5, iclass 31, count 0 2006.173.13:35:00.28#ibcon#read 5, iclass 31, count 0 2006.173.13:35:00.28#ibcon#about to read 6, iclass 31, count 0 2006.173.13:35:00.28#ibcon#read 6, iclass 31, count 0 2006.173.13:35:00.28#ibcon#end of sib2, iclass 31, count 0 2006.173.13:35:00.28#ibcon#*after write, iclass 31, count 0 2006.173.13:35:00.28#ibcon#*before return 0, iclass 31, count 0 2006.173.13:35:00.28#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.13:35:00.28#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.13:35:00.28#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.13:35:00.28#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.13:35:00.28$vck44/va=4,6 2006.173.13:35:00.28#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.173.13:35:00.28#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.173.13:35:00.28#ibcon#ireg 11 cls_cnt 2 2006.173.13:35:00.28#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.13:35:00.34#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.13:35:00.34#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.13:35:00.34#ibcon#enter wrdev, iclass 33, count 2 2006.173.13:35:00.34#ibcon#first serial, iclass 33, count 2 2006.173.13:35:00.34#ibcon#enter sib2, iclass 33, count 2 2006.173.13:35:00.34#ibcon#flushed, iclass 33, count 2 2006.173.13:35:00.34#ibcon#about to write, iclass 33, count 2 2006.173.13:35:00.34#ibcon#wrote, iclass 33, count 2 2006.173.13:35:00.34#ibcon#about to read 3, iclass 33, count 2 2006.173.13:35:00.36#ibcon#read 3, iclass 33, count 2 2006.173.13:35:00.36#ibcon#about to read 4, iclass 33, count 2 2006.173.13:35:00.36#ibcon#read 4, iclass 33, count 2 2006.173.13:35:00.36#ibcon#about to read 5, iclass 33, count 2 2006.173.13:35:00.36#ibcon#read 5, iclass 33, count 2 2006.173.13:35:00.36#ibcon#about to read 6, iclass 33, count 2 2006.173.13:35:00.36#ibcon#read 6, iclass 33, count 2 2006.173.13:35:00.36#ibcon#end of sib2, iclass 33, count 2 2006.173.13:35:00.36#ibcon#*mode == 0, iclass 33, count 2 2006.173.13:35:00.36#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.173.13:35:00.36#ibcon#[25=AT04-06\r\n] 2006.173.13:35:00.36#ibcon#*before write, iclass 33, count 2 2006.173.13:35:00.36#ibcon#enter sib2, iclass 33, count 2 2006.173.13:35:00.36#ibcon#flushed, iclass 33, count 2 2006.173.13:35:00.36#ibcon#about to write, iclass 33, count 2 2006.173.13:35:00.36#ibcon#wrote, iclass 33, count 2 2006.173.13:35:00.36#ibcon#about to read 3, iclass 33, count 2 2006.173.13:35:00.39#ibcon#read 3, iclass 33, count 2 2006.173.13:35:00.39#ibcon#about to read 4, iclass 33, count 2 2006.173.13:35:00.39#ibcon#read 4, iclass 33, count 2 2006.173.13:35:00.39#ibcon#about to read 5, iclass 33, count 2 2006.173.13:35:00.39#ibcon#read 5, iclass 33, count 2 2006.173.13:35:00.39#ibcon#about to read 6, iclass 33, count 2 2006.173.13:35:00.39#ibcon#read 6, iclass 33, count 2 2006.173.13:35:00.39#ibcon#end of sib2, iclass 33, count 2 2006.173.13:35:00.39#ibcon#*after write, iclass 33, count 2 2006.173.13:35:00.39#ibcon#*before return 0, iclass 33, count 2 2006.173.13:35:00.39#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.13:35:00.39#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.173.13:35:00.39#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.173.13:35:00.39#ibcon#ireg 7 cls_cnt 0 2006.173.13:35:00.39#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.13:35:00.51#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.13:35:00.51#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.13:35:00.51#ibcon#enter wrdev, iclass 33, count 0 2006.173.13:35:00.51#ibcon#first serial, iclass 33, count 0 2006.173.13:35:00.51#ibcon#enter sib2, iclass 33, count 0 2006.173.13:35:00.51#ibcon#flushed, iclass 33, count 0 2006.173.13:35:00.51#ibcon#about to write, iclass 33, count 0 2006.173.13:35:00.51#ibcon#wrote, iclass 33, count 0 2006.173.13:35:00.51#ibcon#about to read 3, iclass 33, count 0 2006.173.13:35:00.53#ibcon#read 3, iclass 33, count 0 2006.173.13:35:00.53#ibcon#about to read 4, iclass 33, count 0 2006.173.13:35:00.53#ibcon#read 4, iclass 33, count 0 2006.173.13:35:00.53#ibcon#about to read 5, iclass 33, count 0 2006.173.13:35:00.53#ibcon#read 5, iclass 33, count 0 2006.173.13:35:00.53#ibcon#about to read 6, iclass 33, count 0 2006.173.13:35:00.53#ibcon#read 6, iclass 33, count 0 2006.173.13:35:00.53#ibcon#end of sib2, iclass 33, count 0 2006.173.13:35:00.53#ibcon#*mode == 0, iclass 33, count 0 2006.173.13:35:00.53#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.13:35:00.53#ibcon#[25=USB\r\n] 2006.173.13:35:00.53#ibcon#*before write, iclass 33, count 0 2006.173.13:35:00.53#ibcon#enter sib2, iclass 33, count 0 2006.173.13:35:00.53#ibcon#flushed, iclass 33, count 0 2006.173.13:35:00.53#ibcon#about to write, iclass 33, count 0 2006.173.13:35:00.53#ibcon#wrote, iclass 33, count 0 2006.173.13:35:00.53#ibcon#about to read 3, iclass 33, count 0 2006.173.13:35:00.56#ibcon#read 3, iclass 33, count 0 2006.173.13:35:00.56#ibcon#about to read 4, iclass 33, count 0 2006.173.13:35:00.56#ibcon#read 4, iclass 33, count 0 2006.173.13:35:00.56#ibcon#about to read 5, iclass 33, count 0 2006.173.13:35:00.56#ibcon#read 5, iclass 33, count 0 2006.173.13:35:00.56#ibcon#about to read 6, iclass 33, count 0 2006.173.13:35:00.56#ibcon#read 6, iclass 33, count 0 2006.173.13:35:00.56#ibcon#end of sib2, iclass 33, count 0 2006.173.13:35:00.56#ibcon#*after write, iclass 33, count 0 2006.173.13:35:00.56#ibcon#*before return 0, iclass 33, count 0 2006.173.13:35:00.56#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.13:35:00.56#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.173.13:35:00.56#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.13:35:00.56#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.13:35:00.56$vck44/valo=5,734.99 2006.173.13:35:00.56#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.13:35:00.56#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.13:35:00.56#ibcon#ireg 17 cls_cnt 0 2006.173.13:35:00.56#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.13:35:00.56#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.13:35:00.56#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.13:35:00.56#ibcon#enter wrdev, iclass 35, count 0 2006.173.13:35:00.56#ibcon#first serial, iclass 35, count 0 2006.173.13:35:00.56#ibcon#enter sib2, iclass 35, count 0 2006.173.13:35:00.56#ibcon#flushed, iclass 35, count 0 2006.173.13:35:00.56#ibcon#about to write, iclass 35, count 0 2006.173.13:35:00.56#ibcon#wrote, iclass 35, count 0 2006.173.13:35:00.56#ibcon#about to read 3, iclass 35, count 0 2006.173.13:35:00.58#ibcon#read 3, iclass 35, count 0 2006.173.13:35:00.58#ibcon#about to read 4, iclass 35, count 0 2006.173.13:35:00.58#ibcon#read 4, iclass 35, count 0 2006.173.13:35:00.58#ibcon#about to read 5, iclass 35, count 0 2006.173.13:35:00.58#ibcon#read 5, iclass 35, count 0 2006.173.13:35:00.58#ibcon#about to read 6, iclass 35, count 0 2006.173.13:35:00.58#ibcon#read 6, iclass 35, count 0 2006.173.13:35:00.58#ibcon#end of sib2, iclass 35, count 0 2006.173.13:35:00.58#ibcon#*mode == 0, iclass 35, count 0 2006.173.13:35:00.58#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.13:35:00.58#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.13:35:00.58#ibcon#*before write, iclass 35, count 0 2006.173.13:35:00.58#ibcon#enter sib2, iclass 35, count 0 2006.173.13:35:00.58#ibcon#flushed, iclass 35, count 0 2006.173.13:35:00.58#ibcon#about to write, iclass 35, count 0 2006.173.13:35:00.58#ibcon#wrote, iclass 35, count 0 2006.173.13:35:00.58#ibcon#about to read 3, iclass 35, count 0 2006.173.13:35:00.62#ibcon#read 3, iclass 35, count 0 2006.173.13:35:00.62#ibcon#about to read 4, iclass 35, count 0 2006.173.13:35:00.62#ibcon#read 4, iclass 35, count 0 2006.173.13:35:00.62#ibcon#about to read 5, iclass 35, count 0 2006.173.13:35:00.62#ibcon#read 5, iclass 35, count 0 2006.173.13:35:00.62#ibcon#about to read 6, iclass 35, count 0 2006.173.13:35:00.62#ibcon#read 6, iclass 35, count 0 2006.173.13:35:00.62#ibcon#end of sib2, iclass 35, count 0 2006.173.13:35:00.62#ibcon#*after write, iclass 35, count 0 2006.173.13:35:00.62#ibcon#*before return 0, iclass 35, count 0 2006.173.13:35:00.62#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.13:35:00.62#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.13:35:00.62#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.13:35:00.62#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.13:35:00.62$vck44/va=5,4 2006.173.13:35:00.62#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.173.13:35:00.62#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.173.13:35:00.62#ibcon#ireg 11 cls_cnt 2 2006.173.13:35:00.62#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.13:35:00.68#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.13:35:00.68#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.13:35:00.68#ibcon#enter wrdev, iclass 37, count 2 2006.173.13:35:00.68#ibcon#first serial, iclass 37, count 2 2006.173.13:35:00.68#ibcon#enter sib2, iclass 37, count 2 2006.173.13:35:00.68#ibcon#flushed, iclass 37, count 2 2006.173.13:35:00.68#ibcon#about to write, iclass 37, count 2 2006.173.13:35:00.68#ibcon#wrote, iclass 37, count 2 2006.173.13:35:00.68#ibcon#about to read 3, iclass 37, count 2 2006.173.13:35:00.70#ibcon#read 3, iclass 37, count 2 2006.173.13:35:00.70#ibcon#about to read 4, iclass 37, count 2 2006.173.13:35:00.70#ibcon#read 4, iclass 37, count 2 2006.173.13:35:00.70#ibcon#about to read 5, iclass 37, count 2 2006.173.13:35:00.70#ibcon#read 5, iclass 37, count 2 2006.173.13:35:00.70#ibcon#about to read 6, iclass 37, count 2 2006.173.13:35:00.70#ibcon#read 6, iclass 37, count 2 2006.173.13:35:00.70#ibcon#end of sib2, iclass 37, count 2 2006.173.13:35:00.70#ibcon#*mode == 0, iclass 37, count 2 2006.173.13:35:00.70#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.173.13:35:00.70#ibcon#[25=AT05-04\r\n] 2006.173.13:35:00.70#ibcon#*before write, iclass 37, count 2 2006.173.13:35:00.70#ibcon#enter sib2, iclass 37, count 2 2006.173.13:35:00.70#ibcon#flushed, iclass 37, count 2 2006.173.13:35:00.70#ibcon#about to write, iclass 37, count 2 2006.173.13:35:00.70#ibcon#wrote, iclass 37, count 2 2006.173.13:35:00.70#ibcon#about to read 3, iclass 37, count 2 2006.173.13:35:00.73#ibcon#read 3, iclass 37, count 2 2006.173.13:35:00.73#ibcon#about to read 4, iclass 37, count 2 2006.173.13:35:00.73#ibcon#read 4, iclass 37, count 2 2006.173.13:35:00.73#ibcon#about to read 5, iclass 37, count 2 2006.173.13:35:00.73#ibcon#read 5, iclass 37, count 2 2006.173.13:35:00.73#ibcon#about to read 6, iclass 37, count 2 2006.173.13:35:00.73#ibcon#read 6, iclass 37, count 2 2006.173.13:35:00.73#ibcon#end of sib2, iclass 37, count 2 2006.173.13:35:00.73#ibcon#*after write, iclass 37, count 2 2006.173.13:35:00.73#ibcon#*before return 0, iclass 37, count 2 2006.173.13:35:00.73#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.13:35:00.73#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.173.13:35:00.73#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.173.13:35:00.73#ibcon#ireg 7 cls_cnt 0 2006.173.13:35:00.73#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.13:35:00.85#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.13:35:00.85#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.13:35:00.85#ibcon#enter wrdev, iclass 37, count 0 2006.173.13:35:00.85#ibcon#first serial, iclass 37, count 0 2006.173.13:35:00.85#ibcon#enter sib2, iclass 37, count 0 2006.173.13:35:00.85#ibcon#flushed, iclass 37, count 0 2006.173.13:35:00.85#ibcon#about to write, iclass 37, count 0 2006.173.13:35:00.85#ibcon#wrote, iclass 37, count 0 2006.173.13:35:00.85#ibcon#about to read 3, iclass 37, count 0 2006.173.13:35:00.87#ibcon#read 3, iclass 37, count 0 2006.173.13:35:00.87#ibcon#about to read 4, iclass 37, count 0 2006.173.13:35:00.87#ibcon#read 4, iclass 37, count 0 2006.173.13:35:00.87#ibcon#about to read 5, iclass 37, count 0 2006.173.13:35:00.87#ibcon#read 5, iclass 37, count 0 2006.173.13:35:00.87#ibcon#about to read 6, iclass 37, count 0 2006.173.13:35:00.87#ibcon#read 6, iclass 37, count 0 2006.173.13:35:00.87#ibcon#end of sib2, iclass 37, count 0 2006.173.13:35:00.87#ibcon#*mode == 0, iclass 37, count 0 2006.173.13:35:00.87#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.13:35:00.87#ibcon#[25=USB\r\n] 2006.173.13:35:00.87#ibcon#*before write, iclass 37, count 0 2006.173.13:35:00.87#ibcon#enter sib2, iclass 37, count 0 2006.173.13:35:00.87#ibcon#flushed, iclass 37, count 0 2006.173.13:35:00.87#ibcon#about to write, iclass 37, count 0 2006.173.13:35:00.87#ibcon#wrote, iclass 37, count 0 2006.173.13:35:00.87#ibcon#about to read 3, iclass 37, count 0 2006.173.13:35:00.90#ibcon#read 3, iclass 37, count 0 2006.173.13:35:00.90#ibcon#about to read 4, iclass 37, count 0 2006.173.13:35:00.90#ibcon#read 4, iclass 37, count 0 2006.173.13:35:00.90#ibcon#about to read 5, iclass 37, count 0 2006.173.13:35:00.90#ibcon#read 5, iclass 37, count 0 2006.173.13:35:00.90#ibcon#about to read 6, iclass 37, count 0 2006.173.13:35:00.90#ibcon#read 6, iclass 37, count 0 2006.173.13:35:00.90#ibcon#end of sib2, iclass 37, count 0 2006.173.13:35:00.90#ibcon#*after write, iclass 37, count 0 2006.173.13:35:00.90#ibcon#*before return 0, iclass 37, count 0 2006.173.13:35:00.90#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.13:35:00.90#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.173.13:35:00.90#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.13:35:00.90#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.13:35:00.90$vck44/valo=6,814.99 2006.173.13:35:00.90#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.13:35:00.90#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.13:35:00.90#ibcon#ireg 17 cls_cnt 0 2006.173.13:35:00.90#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.13:35:00.90#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.13:35:00.90#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.13:35:00.90#ibcon#enter wrdev, iclass 39, count 0 2006.173.13:35:00.90#ibcon#first serial, iclass 39, count 0 2006.173.13:35:00.90#ibcon#enter sib2, iclass 39, count 0 2006.173.13:35:00.90#ibcon#flushed, iclass 39, count 0 2006.173.13:35:00.90#ibcon#about to write, iclass 39, count 0 2006.173.13:35:00.90#ibcon#wrote, iclass 39, count 0 2006.173.13:35:00.90#ibcon#about to read 3, iclass 39, count 0 2006.173.13:35:00.92#ibcon#read 3, iclass 39, count 0 2006.173.13:35:00.92#ibcon#about to read 4, iclass 39, count 0 2006.173.13:35:00.92#ibcon#read 4, iclass 39, count 0 2006.173.13:35:00.92#ibcon#about to read 5, iclass 39, count 0 2006.173.13:35:00.92#ibcon#read 5, iclass 39, count 0 2006.173.13:35:00.92#ibcon#about to read 6, iclass 39, count 0 2006.173.13:35:00.92#ibcon#read 6, iclass 39, count 0 2006.173.13:35:00.92#ibcon#end of sib2, iclass 39, count 0 2006.173.13:35:00.92#ibcon#*mode == 0, iclass 39, count 0 2006.173.13:35:00.92#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.13:35:00.92#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.13:35:00.92#ibcon#*before write, iclass 39, count 0 2006.173.13:35:00.92#ibcon#enter sib2, iclass 39, count 0 2006.173.13:35:00.92#ibcon#flushed, iclass 39, count 0 2006.173.13:35:00.92#ibcon#about to write, iclass 39, count 0 2006.173.13:35:00.92#ibcon#wrote, iclass 39, count 0 2006.173.13:35:00.92#ibcon#about to read 3, iclass 39, count 0 2006.173.13:35:00.96#ibcon#read 3, iclass 39, count 0 2006.173.13:35:00.96#ibcon#about to read 4, iclass 39, count 0 2006.173.13:35:00.96#ibcon#read 4, iclass 39, count 0 2006.173.13:35:00.96#ibcon#about to read 5, iclass 39, count 0 2006.173.13:35:00.96#ibcon#read 5, iclass 39, count 0 2006.173.13:35:00.96#ibcon#about to read 6, iclass 39, count 0 2006.173.13:35:00.96#ibcon#read 6, iclass 39, count 0 2006.173.13:35:00.96#ibcon#end of sib2, iclass 39, count 0 2006.173.13:35:00.96#ibcon#*after write, iclass 39, count 0 2006.173.13:35:00.96#ibcon#*before return 0, iclass 39, count 0 2006.173.13:35:00.96#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.13:35:00.96#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.13:35:00.96#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.13:35:00.96#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.13:35:00.96$vck44/va=6,3 2006.173.13:35:00.96#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.13:35:00.96#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.13:35:00.96#ibcon#ireg 11 cls_cnt 2 2006.173.13:35:00.96#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.13:35:01.02#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.13:35:01.02#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.13:35:01.02#ibcon#enter wrdev, iclass 3, count 2 2006.173.13:35:01.02#ibcon#first serial, iclass 3, count 2 2006.173.13:35:01.02#ibcon#enter sib2, iclass 3, count 2 2006.173.13:35:01.02#ibcon#flushed, iclass 3, count 2 2006.173.13:35:01.02#ibcon#about to write, iclass 3, count 2 2006.173.13:35:01.02#ibcon#wrote, iclass 3, count 2 2006.173.13:35:01.02#ibcon#about to read 3, iclass 3, count 2 2006.173.13:35:01.04#ibcon#read 3, iclass 3, count 2 2006.173.13:35:01.04#ibcon#about to read 4, iclass 3, count 2 2006.173.13:35:01.04#ibcon#read 4, iclass 3, count 2 2006.173.13:35:01.04#ibcon#about to read 5, iclass 3, count 2 2006.173.13:35:01.04#ibcon#read 5, iclass 3, count 2 2006.173.13:35:01.04#ibcon#about to read 6, iclass 3, count 2 2006.173.13:35:01.04#ibcon#read 6, iclass 3, count 2 2006.173.13:35:01.04#ibcon#end of sib2, iclass 3, count 2 2006.173.13:35:01.04#ibcon#*mode == 0, iclass 3, count 2 2006.173.13:35:01.04#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.13:35:01.04#ibcon#[25=AT06-03\r\n] 2006.173.13:35:01.04#ibcon#*before write, iclass 3, count 2 2006.173.13:35:01.04#ibcon#enter sib2, iclass 3, count 2 2006.173.13:35:01.04#ibcon#flushed, iclass 3, count 2 2006.173.13:35:01.04#ibcon#about to write, iclass 3, count 2 2006.173.13:35:01.04#ibcon#wrote, iclass 3, count 2 2006.173.13:35:01.04#ibcon#about to read 3, iclass 3, count 2 2006.173.13:35:01.07#ibcon#read 3, iclass 3, count 2 2006.173.13:35:01.07#ibcon#about to read 4, iclass 3, count 2 2006.173.13:35:01.07#ibcon#read 4, iclass 3, count 2 2006.173.13:35:01.07#ibcon#about to read 5, iclass 3, count 2 2006.173.13:35:01.07#ibcon#read 5, iclass 3, count 2 2006.173.13:35:01.07#ibcon#about to read 6, iclass 3, count 2 2006.173.13:35:01.07#ibcon#read 6, iclass 3, count 2 2006.173.13:35:01.07#ibcon#end of sib2, iclass 3, count 2 2006.173.13:35:01.07#ibcon#*after write, iclass 3, count 2 2006.173.13:35:01.07#ibcon#*before return 0, iclass 3, count 2 2006.173.13:35:01.07#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.13:35:01.07#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.13:35:01.07#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.13:35:01.07#ibcon#ireg 7 cls_cnt 0 2006.173.13:35:01.07#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.13:35:01.19#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.13:35:01.19#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.13:35:01.19#ibcon#enter wrdev, iclass 3, count 0 2006.173.13:35:01.19#ibcon#first serial, iclass 3, count 0 2006.173.13:35:01.19#ibcon#enter sib2, iclass 3, count 0 2006.173.13:35:01.19#ibcon#flushed, iclass 3, count 0 2006.173.13:35:01.19#ibcon#about to write, iclass 3, count 0 2006.173.13:35:01.19#ibcon#wrote, iclass 3, count 0 2006.173.13:35:01.19#ibcon#about to read 3, iclass 3, count 0 2006.173.13:35:01.21#ibcon#read 3, iclass 3, count 0 2006.173.13:35:01.21#ibcon#about to read 4, iclass 3, count 0 2006.173.13:35:01.21#ibcon#read 4, iclass 3, count 0 2006.173.13:35:01.21#ibcon#about to read 5, iclass 3, count 0 2006.173.13:35:01.21#ibcon#read 5, iclass 3, count 0 2006.173.13:35:01.21#ibcon#about to read 6, iclass 3, count 0 2006.173.13:35:01.21#ibcon#read 6, iclass 3, count 0 2006.173.13:35:01.21#ibcon#end of sib2, iclass 3, count 0 2006.173.13:35:01.21#ibcon#*mode == 0, iclass 3, count 0 2006.173.13:35:01.21#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.13:35:01.21#ibcon#[25=USB\r\n] 2006.173.13:35:01.21#ibcon#*before write, iclass 3, count 0 2006.173.13:35:01.21#ibcon#enter sib2, iclass 3, count 0 2006.173.13:35:01.21#ibcon#flushed, iclass 3, count 0 2006.173.13:35:01.21#ibcon#about to write, iclass 3, count 0 2006.173.13:35:01.21#ibcon#wrote, iclass 3, count 0 2006.173.13:35:01.21#ibcon#about to read 3, iclass 3, count 0 2006.173.13:35:01.24#ibcon#read 3, iclass 3, count 0 2006.173.13:35:01.24#ibcon#about to read 4, iclass 3, count 0 2006.173.13:35:01.24#ibcon#read 4, iclass 3, count 0 2006.173.13:35:01.24#ibcon#about to read 5, iclass 3, count 0 2006.173.13:35:01.24#ibcon#read 5, iclass 3, count 0 2006.173.13:35:01.24#ibcon#about to read 6, iclass 3, count 0 2006.173.13:35:01.24#ibcon#read 6, iclass 3, count 0 2006.173.13:35:01.24#ibcon#end of sib2, iclass 3, count 0 2006.173.13:35:01.24#ibcon#*after write, iclass 3, count 0 2006.173.13:35:01.24#ibcon#*before return 0, iclass 3, count 0 2006.173.13:35:01.24#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.13:35:01.24#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.13:35:01.24#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.13:35:01.24#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.13:35:01.24$vck44/valo=7,864.99 2006.173.13:35:01.24#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.13:35:01.24#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.13:35:01.24#ibcon#ireg 17 cls_cnt 0 2006.173.13:35:01.24#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.13:35:01.24#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.13:35:01.24#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.13:35:01.24#ibcon#enter wrdev, iclass 5, count 0 2006.173.13:35:01.24#ibcon#first serial, iclass 5, count 0 2006.173.13:35:01.24#ibcon#enter sib2, iclass 5, count 0 2006.173.13:35:01.24#ibcon#flushed, iclass 5, count 0 2006.173.13:35:01.24#ibcon#about to write, iclass 5, count 0 2006.173.13:35:01.24#ibcon#wrote, iclass 5, count 0 2006.173.13:35:01.24#ibcon#about to read 3, iclass 5, count 0 2006.173.13:35:01.26#ibcon#read 3, iclass 5, count 0 2006.173.13:35:01.26#ibcon#about to read 4, iclass 5, count 0 2006.173.13:35:01.26#ibcon#read 4, iclass 5, count 0 2006.173.13:35:01.26#ibcon#about to read 5, iclass 5, count 0 2006.173.13:35:01.26#ibcon#read 5, iclass 5, count 0 2006.173.13:35:01.26#ibcon#about to read 6, iclass 5, count 0 2006.173.13:35:01.26#ibcon#read 6, iclass 5, count 0 2006.173.13:35:01.26#ibcon#end of sib2, iclass 5, count 0 2006.173.13:35:01.26#ibcon#*mode == 0, iclass 5, count 0 2006.173.13:35:01.26#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.13:35:01.26#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.13:35:01.26#ibcon#*before write, iclass 5, count 0 2006.173.13:35:01.26#ibcon#enter sib2, iclass 5, count 0 2006.173.13:35:01.26#ibcon#flushed, iclass 5, count 0 2006.173.13:35:01.26#ibcon#about to write, iclass 5, count 0 2006.173.13:35:01.26#ibcon#wrote, iclass 5, count 0 2006.173.13:35:01.26#ibcon#about to read 3, iclass 5, count 0 2006.173.13:35:01.30#ibcon#read 3, iclass 5, count 0 2006.173.13:35:01.30#ibcon#about to read 4, iclass 5, count 0 2006.173.13:35:01.30#ibcon#read 4, iclass 5, count 0 2006.173.13:35:01.30#ibcon#about to read 5, iclass 5, count 0 2006.173.13:35:01.30#ibcon#read 5, iclass 5, count 0 2006.173.13:35:01.30#ibcon#about to read 6, iclass 5, count 0 2006.173.13:35:01.30#ibcon#read 6, iclass 5, count 0 2006.173.13:35:01.30#ibcon#end of sib2, iclass 5, count 0 2006.173.13:35:01.30#ibcon#*after write, iclass 5, count 0 2006.173.13:35:01.30#ibcon#*before return 0, iclass 5, count 0 2006.173.13:35:01.30#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.13:35:01.30#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.13:35:01.30#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.13:35:01.30#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.13:35:01.30$vck44/va=7,4 2006.173.13:35:01.30#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.173.13:35:01.30#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.173.13:35:01.30#ibcon#ireg 11 cls_cnt 2 2006.173.13:35:01.30#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.13:35:01.36#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.13:35:01.36#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.13:35:01.36#ibcon#enter wrdev, iclass 7, count 2 2006.173.13:35:01.36#ibcon#first serial, iclass 7, count 2 2006.173.13:35:01.36#ibcon#enter sib2, iclass 7, count 2 2006.173.13:35:01.36#ibcon#flushed, iclass 7, count 2 2006.173.13:35:01.36#ibcon#about to write, iclass 7, count 2 2006.173.13:35:01.36#ibcon#wrote, iclass 7, count 2 2006.173.13:35:01.36#ibcon#about to read 3, iclass 7, count 2 2006.173.13:35:01.38#ibcon#read 3, iclass 7, count 2 2006.173.13:35:01.38#ibcon#about to read 4, iclass 7, count 2 2006.173.13:35:01.38#ibcon#read 4, iclass 7, count 2 2006.173.13:35:01.38#ibcon#about to read 5, iclass 7, count 2 2006.173.13:35:01.38#ibcon#read 5, iclass 7, count 2 2006.173.13:35:01.38#ibcon#about to read 6, iclass 7, count 2 2006.173.13:35:01.38#ibcon#read 6, iclass 7, count 2 2006.173.13:35:01.38#ibcon#end of sib2, iclass 7, count 2 2006.173.13:35:01.38#ibcon#*mode == 0, iclass 7, count 2 2006.173.13:35:01.38#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.173.13:35:01.38#ibcon#[25=AT07-04\r\n] 2006.173.13:35:01.38#ibcon#*before write, iclass 7, count 2 2006.173.13:35:01.38#ibcon#enter sib2, iclass 7, count 2 2006.173.13:35:01.38#ibcon#flushed, iclass 7, count 2 2006.173.13:35:01.38#ibcon#about to write, iclass 7, count 2 2006.173.13:35:01.38#ibcon#wrote, iclass 7, count 2 2006.173.13:35:01.38#ibcon#about to read 3, iclass 7, count 2 2006.173.13:35:01.41#ibcon#read 3, iclass 7, count 2 2006.173.13:35:01.41#ibcon#about to read 4, iclass 7, count 2 2006.173.13:35:01.41#ibcon#read 4, iclass 7, count 2 2006.173.13:35:01.41#ibcon#about to read 5, iclass 7, count 2 2006.173.13:35:01.41#ibcon#read 5, iclass 7, count 2 2006.173.13:35:01.41#ibcon#about to read 6, iclass 7, count 2 2006.173.13:35:01.41#ibcon#read 6, iclass 7, count 2 2006.173.13:35:01.41#ibcon#end of sib2, iclass 7, count 2 2006.173.13:35:01.41#ibcon#*after write, iclass 7, count 2 2006.173.13:35:01.41#ibcon#*before return 0, iclass 7, count 2 2006.173.13:35:01.41#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.13:35:01.41#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.173.13:35:01.41#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.173.13:35:01.41#ibcon#ireg 7 cls_cnt 0 2006.173.13:35:01.41#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.13:35:01.53#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.13:35:01.53#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.13:35:01.53#ibcon#enter wrdev, iclass 7, count 0 2006.173.13:35:01.53#ibcon#first serial, iclass 7, count 0 2006.173.13:35:01.53#ibcon#enter sib2, iclass 7, count 0 2006.173.13:35:01.53#ibcon#flushed, iclass 7, count 0 2006.173.13:35:01.53#ibcon#about to write, iclass 7, count 0 2006.173.13:35:01.53#ibcon#wrote, iclass 7, count 0 2006.173.13:35:01.53#ibcon#about to read 3, iclass 7, count 0 2006.173.13:35:01.55#ibcon#read 3, iclass 7, count 0 2006.173.13:35:01.55#ibcon#about to read 4, iclass 7, count 0 2006.173.13:35:01.55#ibcon#read 4, iclass 7, count 0 2006.173.13:35:01.55#ibcon#about to read 5, iclass 7, count 0 2006.173.13:35:01.55#ibcon#read 5, iclass 7, count 0 2006.173.13:35:01.55#ibcon#about to read 6, iclass 7, count 0 2006.173.13:35:01.55#ibcon#read 6, iclass 7, count 0 2006.173.13:35:01.55#ibcon#end of sib2, iclass 7, count 0 2006.173.13:35:01.55#ibcon#*mode == 0, iclass 7, count 0 2006.173.13:35:01.55#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.13:35:01.55#ibcon#[25=USB\r\n] 2006.173.13:35:01.55#ibcon#*before write, iclass 7, count 0 2006.173.13:35:01.55#ibcon#enter sib2, iclass 7, count 0 2006.173.13:35:01.55#ibcon#flushed, iclass 7, count 0 2006.173.13:35:01.55#ibcon#about to write, iclass 7, count 0 2006.173.13:35:01.55#ibcon#wrote, iclass 7, count 0 2006.173.13:35:01.55#ibcon#about to read 3, iclass 7, count 0 2006.173.13:35:01.58#ibcon#read 3, iclass 7, count 0 2006.173.13:35:01.58#ibcon#about to read 4, iclass 7, count 0 2006.173.13:35:01.58#ibcon#read 4, iclass 7, count 0 2006.173.13:35:01.58#ibcon#about to read 5, iclass 7, count 0 2006.173.13:35:01.58#ibcon#read 5, iclass 7, count 0 2006.173.13:35:01.58#ibcon#about to read 6, iclass 7, count 0 2006.173.13:35:01.58#ibcon#read 6, iclass 7, count 0 2006.173.13:35:01.58#ibcon#end of sib2, iclass 7, count 0 2006.173.13:35:01.58#ibcon#*after write, iclass 7, count 0 2006.173.13:35:01.58#ibcon#*before return 0, iclass 7, count 0 2006.173.13:35:01.58#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.13:35:01.58#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.173.13:35:01.58#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.13:35:01.58#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.13:35:01.58$vck44/valo=8,884.99 2006.173.13:35:01.58#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.13:35:01.58#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.13:35:01.58#ibcon#ireg 17 cls_cnt 0 2006.173.13:35:01.58#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.13:35:01.58#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.13:35:01.58#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.13:35:01.58#ibcon#enter wrdev, iclass 11, count 0 2006.173.13:35:01.58#ibcon#first serial, iclass 11, count 0 2006.173.13:35:01.58#ibcon#enter sib2, iclass 11, count 0 2006.173.13:35:01.58#ibcon#flushed, iclass 11, count 0 2006.173.13:35:01.58#ibcon#about to write, iclass 11, count 0 2006.173.13:35:01.58#ibcon#wrote, iclass 11, count 0 2006.173.13:35:01.58#ibcon#about to read 3, iclass 11, count 0 2006.173.13:35:01.60#ibcon#read 3, iclass 11, count 0 2006.173.13:35:01.60#ibcon#about to read 4, iclass 11, count 0 2006.173.13:35:01.60#ibcon#read 4, iclass 11, count 0 2006.173.13:35:01.60#ibcon#about to read 5, iclass 11, count 0 2006.173.13:35:01.60#ibcon#read 5, iclass 11, count 0 2006.173.13:35:01.60#ibcon#about to read 6, iclass 11, count 0 2006.173.13:35:01.60#ibcon#read 6, iclass 11, count 0 2006.173.13:35:01.60#ibcon#end of sib2, iclass 11, count 0 2006.173.13:35:01.60#ibcon#*mode == 0, iclass 11, count 0 2006.173.13:35:01.60#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.13:35:01.60#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.13:35:01.60#ibcon#*before write, iclass 11, count 0 2006.173.13:35:01.60#ibcon#enter sib2, iclass 11, count 0 2006.173.13:35:01.60#ibcon#flushed, iclass 11, count 0 2006.173.13:35:01.60#ibcon#about to write, iclass 11, count 0 2006.173.13:35:01.60#ibcon#wrote, iclass 11, count 0 2006.173.13:35:01.60#ibcon#about to read 3, iclass 11, count 0 2006.173.13:35:01.64#ibcon#read 3, iclass 11, count 0 2006.173.13:35:01.64#ibcon#about to read 4, iclass 11, count 0 2006.173.13:35:01.64#ibcon#read 4, iclass 11, count 0 2006.173.13:35:01.64#ibcon#about to read 5, iclass 11, count 0 2006.173.13:35:01.64#ibcon#read 5, iclass 11, count 0 2006.173.13:35:01.64#ibcon#about to read 6, iclass 11, count 0 2006.173.13:35:01.64#ibcon#read 6, iclass 11, count 0 2006.173.13:35:01.64#ibcon#end of sib2, iclass 11, count 0 2006.173.13:35:01.64#ibcon#*after write, iclass 11, count 0 2006.173.13:35:01.64#ibcon#*before return 0, iclass 11, count 0 2006.173.13:35:01.64#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.13:35:01.64#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.13:35:01.64#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.13:35:01.64#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.13:35:01.64$vck44/va=8,4 2006.173.13:35:01.64#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.173.13:35:01.64#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.173.13:35:01.64#ibcon#ireg 11 cls_cnt 2 2006.173.13:35:01.64#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.13:35:01.70#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.13:35:01.70#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.13:35:01.70#ibcon#enter wrdev, iclass 13, count 2 2006.173.13:35:01.70#ibcon#first serial, iclass 13, count 2 2006.173.13:35:01.70#ibcon#enter sib2, iclass 13, count 2 2006.173.13:35:01.70#ibcon#flushed, iclass 13, count 2 2006.173.13:35:01.70#ibcon#about to write, iclass 13, count 2 2006.173.13:35:01.70#ibcon#wrote, iclass 13, count 2 2006.173.13:35:01.70#ibcon#about to read 3, iclass 13, count 2 2006.173.13:35:01.72#ibcon#read 3, iclass 13, count 2 2006.173.13:35:01.72#ibcon#about to read 4, iclass 13, count 2 2006.173.13:35:01.72#ibcon#read 4, iclass 13, count 2 2006.173.13:35:01.72#ibcon#about to read 5, iclass 13, count 2 2006.173.13:35:01.72#ibcon#read 5, iclass 13, count 2 2006.173.13:35:01.72#ibcon#about to read 6, iclass 13, count 2 2006.173.13:35:01.72#ibcon#read 6, iclass 13, count 2 2006.173.13:35:01.72#ibcon#end of sib2, iclass 13, count 2 2006.173.13:35:01.72#ibcon#*mode == 0, iclass 13, count 2 2006.173.13:35:01.72#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.173.13:35:01.72#ibcon#[25=AT08-04\r\n] 2006.173.13:35:01.72#ibcon#*before write, iclass 13, count 2 2006.173.13:35:01.72#ibcon#enter sib2, iclass 13, count 2 2006.173.13:35:01.72#ibcon#flushed, iclass 13, count 2 2006.173.13:35:01.72#ibcon#about to write, iclass 13, count 2 2006.173.13:35:01.72#ibcon#wrote, iclass 13, count 2 2006.173.13:35:01.72#ibcon#about to read 3, iclass 13, count 2 2006.173.13:35:01.75#ibcon#read 3, iclass 13, count 2 2006.173.13:35:01.75#ibcon#about to read 4, iclass 13, count 2 2006.173.13:35:01.75#ibcon#read 4, iclass 13, count 2 2006.173.13:35:01.75#ibcon#about to read 5, iclass 13, count 2 2006.173.13:35:01.75#ibcon#read 5, iclass 13, count 2 2006.173.13:35:01.75#ibcon#about to read 6, iclass 13, count 2 2006.173.13:35:01.75#ibcon#read 6, iclass 13, count 2 2006.173.13:35:01.75#ibcon#end of sib2, iclass 13, count 2 2006.173.13:35:01.75#ibcon#*after write, iclass 13, count 2 2006.173.13:35:01.75#ibcon#*before return 0, iclass 13, count 2 2006.173.13:35:01.75#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.13:35:01.75#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.173.13:35:01.75#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.173.13:35:01.75#ibcon#ireg 7 cls_cnt 0 2006.173.13:35:01.75#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.13:35:01.87#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.13:35:01.87#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.13:35:01.87#ibcon#enter wrdev, iclass 13, count 0 2006.173.13:35:01.87#ibcon#first serial, iclass 13, count 0 2006.173.13:35:01.87#ibcon#enter sib2, iclass 13, count 0 2006.173.13:35:01.87#ibcon#flushed, iclass 13, count 0 2006.173.13:35:01.87#ibcon#about to write, iclass 13, count 0 2006.173.13:35:01.87#ibcon#wrote, iclass 13, count 0 2006.173.13:35:01.87#ibcon#about to read 3, iclass 13, count 0 2006.173.13:35:01.89#ibcon#read 3, iclass 13, count 0 2006.173.13:35:01.89#ibcon#about to read 4, iclass 13, count 0 2006.173.13:35:01.89#ibcon#read 4, iclass 13, count 0 2006.173.13:35:01.89#ibcon#about to read 5, iclass 13, count 0 2006.173.13:35:01.89#ibcon#read 5, iclass 13, count 0 2006.173.13:35:01.89#ibcon#about to read 6, iclass 13, count 0 2006.173.13:35:01.89#ibcon#read 6, iclass 13, count 0 2006.173.13:35:01.89#ibcon#end of sib2, iclass 13, count 0 2006.173.13:35:01.89#ibcon#*mode == 0, iclass 13, count 0 2006.173.13:35:01.89#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.13:35:01.89#ibcon#[25=USB\r\n] 2006.173.13:35:01.89#ibcon#*before write, iclass 13, count 0 2006.173.13:35:01.89#ibcon#enter sib2, iclass 13, count 0 2006.173.13:35:01.89#ibcon#flushed, iclass 13, count 0 2006.173.13:35:01.89#ibcon#about to write, iclass 13, count 0 2006.173.13:35:01.89#ibcon#wrote, iclass 13, count 0 2006.173.13:35:01.89#ibcon#about to read 3, iclass 13, count 0 2006.173.13:35:01.92#ibcon#read 3, iclass 13, count 0 2006.173.13:35:01.92#ibcon#about to read 4, iclass 13, count 0 2006.173.13:35:01.92#ibcon#read 4, iclass 13, count 0 2006.173.13:35:01.92#ibcon#about to read 5, iclass 13, count 0 2006.173.13:35:01.92#ibcon#read 5, iclass 13, count 0 2006.173.13:35:01.92#ibcon#about to read 6, iclass 13, count 0 2006.173.13:35:01.92#ibcon#read 6, iclass 13, count 0 2006.173.13:35:01.92#ibcon#end of sib2, iclass 13, count 0 2006.173.13:35:01.92#ibcon#*after write, iclass 13, count 0 2006.173.13:35:01.92#ibcon#*before return 0, iclass 13, count 0 2006.173.13:35:01.92#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.13:35:01.92#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.173.13:35:01.92#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.13:35:01.92#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.13:35:01.92$vck44/vblo=1,629.99 2006.173.13:35:01.92#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.13:35:01.92#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.13:35:01.92#ibcon#ireg 17 cls_cnt 0 2006.173.13:35:01.92#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.13:35:01.92#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.13:35:01.92#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.13:35:01.92#ibcon#enter wrdev, iclass 15, count 0 2006.173.13:35:01.92#ibcon#first serial, iclass 15, count 0 2006.173.13:35:01.92#ibcon#enter sib2, iclass 15, count 0 2006.173.13:35:01.92#ibcon#flushed, iclass 15, count 0 2006.173.13:35:01.92#ibcon#about to write, iclass 15, count 0 2006.173.13:35:01.92#ibcon#wrote, iclass 15, count 0 2006.173.13:35:01.92#ibcon#about to read 3, iclass 15, count 0 2006.173.13:35:01.94#ibcon#read 3, iclass 15, count 0 2006.173.13:35:01.94#ibcon#about to read 4, iclass 15, count 0 2006.173.13:35:01.94#ibcon#read 4, iclass 15, count 0 2006.173.13:35:01.94#ibcon#about to read 5, iclass 15, count 0 2006.173.13:35:01.94#ibcon#read 5, iclass 15, count 0 2006.173.13:35:01.94#ibcon#about to read 6, iclass 15, count 0 2006.173.13:35:01.94#ibcon#read 6, iclass 15, count 0 2006.173.13:35:01.94#ibcon#end of sib2, iclass 15, count 0 2006.173.13:35:01.94#ibcon#*mode == 0, iclass 15, count 0 2006.173.13:35:01.94#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.13:35:01.94#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.13:35:01.94#ibcon#*before write, iclass 15, count 0 2006.173.13:35:01.94#ibcon#enter sib2, iclass 15, count 0 2006.173.13:35:01.94#ibcon#flushed, iclass 15, count 0 2006.173.13:35:01.94#ibcon#about to write, iclass 15, count 0 2006.173.13:35:01.94#ibcon#wrote, iclass 15, count 0 2006.173.13:35:01.94#ibcon#about to read 3, iclass 15, count 0 2006.173.13:35:01.98#ibcon#read 3, iclass 15, count 0 2006.173.13:35:01.98#ibcon#about to read 4, iclass 15, count 0 2006.173.13:35:01.98#ibcon#read 4, iclass 15, count 0 2006.173.13:35:01.98#ibcon#about to read 5, iclass 15, count 0 2006.173.13:35:01.98#ibcon#read 5, iclass 15, count 0 2006.173.13:35:01.98#ibcon#about to read 6, iclass 15, count 0 2006.173.13:35:01.98#ibcon#read 6, iclass 15, count 0 2006.173.13:35:01.98#ibcon#end of sib2, iclass 15, count 0 2006.173.13:35:01.98#ibcon#*after write, iclass 15, count 0 2006.173.13:35:01.98#ibcon#*before return 0, iclass 15, count 0 2006.173.13:35:01.98#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.13:35:01.98#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.13:35:01.98#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.13:35:01.98#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.13:35:01.98$vck44/vb=1,4 2006.173.13:35:01.98#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.13:35:01.98#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.13:35:01.98#ibcon#ireg 11 cls_cnt 2 2006.173.13:35:01.98#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.13:35:01.98#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.13:35:01.98#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.13:35:01.98#ibcon#enter wrdev, iclass 17, count 2 2006.173.13:35:01.98#ibcon#first serial, iclass 17, count 2 2006.173.13:35:01.98#ibcon#enter sib2, iclass 17, count 2 2006.173.13:35:01.98#ibcon#flushed, iclass 17, count 2 2006.173.13:35:01.98#ibcon#about to write, iclass 17, count 2 2006.173.13:35:01.98#ibcon#wrote, iclass 17, count 2 2006.173.13:35:01.98#ibcon#about to read 3, iclass 17, count 2 2006.173.13:35:02.00#ibcon#read 3, iclass 17, count 2 2006.173.13:35:02.00#ibcon#about to read 4, iclass 17, count 2 2006.173.13:35:02.00#ibcon#read 4, iclass 17, count 2 2006.173.13:35:02.00#ibcon#about to read 5, iclass 17, count 2 2006.173.13:35:02.00#ibcon#read 5, iclass 17, count 2 2006.173.13:35:02.00#ibcon#about to read 6, iclass 17, count 2 2006.173.13:35:02.00#ibcon#read 6, iclass 17, count 2 2006.173.13:35:02.00#ibcon#end of sib2, iclass 17, count 2 2006.173.13:35:02.00#ibcon#*mode == 0, iclass 17, count 2 2006.173.13:35:02.00#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.13:35:02.00#ibcon#[27=AT01-04\r\n] 2006.173.13:35:02.00#ibcon#*before write, iclass 17, count 2 2006.173.13:35:02.00#ibcon#enter sib2, iclass 17, count 2 2006.173.13:35:02.00#ibcon#flushed, iclass 17, count 2 2006.173.13:35:02.00#ibcon#about to write, iclass 17, count 2 2006.173.13:35:02.00#ibcon#wrote, iclass 17, count 2 2006.173.13:35:02.00#ibcon#about to read 3, iclass 17, count 2 2006.173.13:35:02.03#ibcon#read 3, iclass 17, count 2 2006.173.13:35:02.03#ibcon#about to read 4, iclass 17, count 2 2006.173.13:35:02.03#ibcon#read 4, iclass 17, count 2 2006.173.13:35:02.03#ibcon#about to read 5, iclass 17, count 2 2006.173.13:35:02.03#ibcon#read 5, iclass 17, count 2 2006.173.13:35:02.03#ibcon#about to read 6, iclass 17, count 2 2006.173.13:35:02.03#ibcon#read 6, iclass 17, count 2 2006.173.13:35:02.03#ibcon#end of sib2, iclass 17, count 2 2006.173.13:35:02.03#ibcon#*after write, iclass 17, count 2 2006.173.13:35:02.03#ibcon#*before return 0, iclass 17, count 2 2006.173.13:35:02.03#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.13:35:02.03#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.13:35:02.03#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.13:35:02.03#ibcon#ireg 7 cls_cnt 0 2006.173.13:35:02.03#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.13:35:02.15#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.13:35:02.15#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.13:35:02.15#ibcon#enter wrdev, iclass 17, count 0 2006.173.13:35:02.15#ibcon#first serial, iclass 17, count 0 2006.173.13:35:02.15#ibcon#enter sib2, iclass 17, count 0 2006.173.13:35:02.15#ibcon#flushed, iclass 17, count 0 2006.173.13:35:02.15#ibcon#about to write, iclass 17, count 0 2006.173.13:35:02.15#ibcon#wrote, iclass 17, count 0 2006.173.13:35:02.15#ibcon#about to read 3, iclass 17, count 0 2006.173.13:35:02.17#ibcon#read 3, iclass 17, count 0 2006.173.13:35:02.17#ibcon#about to read 4, iclass 17, count 0 2006.173.13:35:02.17#ibcon#read 4, iclass 17, count 0 2006.173.13:35:02.17#ibcon#about to read 5, iclass 17, count 0 2006.173.13:35:02.17#ibcon#read 5, iclass 17, count 0 2006.173.13:35:02.17#ibcon#about to read 6, iclass 17, count 0 2006.173.13:35:02.17#ibcon#read 6, iclass 17, count 0 2006.173.13:35:02.17#ibcon#end of sib2, iclass 17, count 0 2006.173.13:35:02.17#ibcon#*mode == 0, iclass 17, count 0 2006.173.13:35:02.17#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.13:35:02.17#ibcon#[27=USB\r\n] 2006.173.13:35:02.17#ibcon#*before write, iclass 17, count 0 2006.173.13:35:02.17#ibcon#enter sib2, iclass 17, count 0 2006.173.13:35:02.17#ibcon#flushed, iclass 17, count 0 2006.173.13:35:02.17#ibcon#about to write, iclass 17, count 0 2006.173.13:35:02.17#ibcon#wrote, iclass 17, count 0 2006.173.13:35:02.17#ibcon#about to read 3, iclass 17, count 0 2006.173.13:35:02.20#ibcon#read 3, iclass 17, count 0 2006.173.13:35:02.20#ibcon#about to read 4, iclass 17, count 0 2006.173.13:35:02.20#ibcon#read 4, iclass 17, count 0 2006.173.13:35:02.20#ibcon#about to read 5, iclass 17, count 0 2006.173.13:35:02.20#ibcon#read 5, iclass 17, count 0 2006.173.13:35:02.20#ibcon#about to read 6, iclass 17, count 0 2006.173.13:35:02.20#ibcon#read 6, iclass 17, count 0 2006.173.13:35:02.20#ibcon#end of sib2, iclass 17, count 0 2006.173.13:35:02.20#ibcon#*after write, iclass 17, count 0 2006.173.13:35:02.20#ibcon#*before return 0, iclass 17, count 0 2006.173.13:35:02.20#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.13:35:02.20#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.13:35:02.20#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.13:35:02.20#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.13:35:02.20$vck44/vblo=2,634.99 2006.173.13:35:02.20#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.13:35:02.20#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.13:35:02.20#ibcon#ireg 17 cls_cnt 0 2006.173.13:35:02.20#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.13:35:02.20#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.13:35:02.20#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.13:35:02.20#ibcon#enter wrdev, iclass 19, count 0 2006.173.13:35:02.20#ibcon#first serial, iclass 19, count 0 2006.173.13:35:02.20#ibcon#enter sib2, iclass 19, count 0 2006.173.13:35:02.20#ibcon#flushed, iclass 19, count 0 2006.173.13:35:02.20#ibcon#about to write, iclass 19, count 0 2006.173.13:35:02.20#ibcon#wrote, iclass 19, count 0 2006.173.13:35:02.20#ibcon#about to read 3, iclass 19, count 0 2006.173.13:35:02.22#ibcon#read 3, iclass 19, count 0 2006.173.13:35:02.22#ibcon#about to read 4, iclass 19, count 0 2006.173.13:35:02.22#ibcon#read 4, iclass 19, count 0 2006.173.13:35:02.22#ibcon#about to read 5, iclass 19, count 0 2006.173.13:35:02.22#ibcon#read 5, iclass 19, count 0 2006.173.13:35:02.22#ibcon#about to read 6, iclass 19, count 0 2006.173.13:35:02.22#ibcon#read 6, iclass 19, count 0 2006.173.13:35:02.22#ibcon#end of sib2, iclass 19, count 0 2006.173.13:35:02.22#ibcon#*mode == 0, iclass 19, count 0 2006.173.13:35:02.22#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.13:35:02.22#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.13:35:02.22#ibcon#*before write, iclass 19, count 0 2006.173.13:35:02.22#ibcon#enter sib2, iclass 19, count 0 2006.173.13:35:02.22#ibcon#flushed, iclass 19, count 0 2006.173.13:35:02.22#ibcon#about to write, iclass 19, count 0 2006.173.13:35:02.22#ibcon#wrote, iclass 19, count 0 2006.173.13:35:02.22#ibcon#about to read 3, iclass 19, count 0 2006.173.13:35:02.26#ibcon#read 3, iclass 19, count 0 2006.173.13:35:02.26#ibcon#about to read 4, iclass 19, count 0 2006.173.13:35:02.26#ibcon#read 4, iclass 19, count 0 2006.173.13:35:02.26#ibcon#about to read 5, iclass 19, count 0 2006.173.13:35:02.26#ibcon#read 5, iclass 19, count 0 2006.173.13:35:02.26#ibcon#about to read 6, iclass 19, count 0 2006.173.13:35:02.26#ibcon#read 6, iclass 19, count 0 2006.173.13:35:02.26#ibcon#end of sib2, iclass 19, count 0 2006.173.13:35:02.26#ibcon#*after write, iclass 19, count 0 2006.173.13:35:02.26#ibcon#*before return 0, iclass 19, count 0 2006.173.13:35:02.26#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.13:35:02.26#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.13:35:02.26#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.13:35:02.26#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.13:35:02.26$vck44/vb=2,4 2006.173.13:35:02.26#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.13:35:02.26#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.13:35:02.26#ibcon#ireg 11 cls_cnt 2 2006.173.13:35:02.26#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.13:35:02.32#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.13:35:02.32#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.13:35:02.32#ibcon#enter wrdev, iclass 21, count 2 2006.173.13:35:02.32#ibcon#first serial, iclass 21, count 2 2006.173.13:35:02.32#ibcon#enter sib2, iclass 21, count 2 2006.173.13:35:02.32#ibcon#flushed, iclass 21, count 2 2006.173.13:35:02.32#ibcon#about to write, iclass 21, count 2 2006.173.13:35:02.32#ibcon#wrote, iclass 21, count 2 2006.173.13:35:02.32#ibcon#about to read 3, iclass 21, count 2 2006.173.13:35:02.34#ibcon#read 3, iclass 21, count 2 2006.173.13:35:02.34#ibcon#about to read 4, iclass 21, count 2 2006.173.13:35:02.34#ibcon#read 4, iclass 21, count 2 2006.173.13:35:02.34#ibcon#about to read 5, iclass 21, count 2 2006.173.13:35:02.34#ibcon#read 5, iclass 21, count 2 2006.173.13:35:02.34#ibcon#about to read 6, iclass 21, count 2 2006.173.13:35:02.34#ibcon#read 6, iclass 21, count 2 2006.173.13:35:02.34#ibcon#end of sib2, iclass 21, count 2 2006.173.13:35:02.34#ibcon#*mode == 0, iclass 21, count 2 2006.173.13:35:02.34#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.13:35:02.34#ibcon#[27=AT02-04\r\n] 2006.173.13:35:02.34#ibcon#*before write, iclass 21, count 2 2006.173.13:35:02.34#ibcon#enter sib2, iclass 21, count 2 2006.173.13:35:02.34#ibcon#flushed, iclass 21, count 2 2006.173.13:35:02.34#ibcon#about to write, iclass 21, count 2 2006.173.13:35:02.34#ibcon#wrote, iclass 21, count 2 2006.173.13:35:02.34#ibcon#about to read 3, iclass 21, count 2 2006.173.13:35:02.37#ibcon#read 3, iclass 21, count 2 2006.173.13:35:02.37#ibcon#about to read 4, iclass 21, count 2 2006.173.13:35:02.37#ibcon#read 4, iclass 21, count 2 2006.173.13:35:02.37#ibcon#about to read 5, iclass 21, count 2 2006.173.13:35:02.37#ibcon#read 5, iclass 21, count 2 2006.173.13:35:02.37#ibcon#about to read 6, iclass 21, count 2 2006.173.13:35:02.37#ibcon#read 6, iclass 21, count 2 2006.173.13:35:02.37#ibcon#end of sib2, iclass 21, count 2 2006.173.13:35:02.37#ibcon#*after write, iclass 21, count 2 2006.173.13:35:02.37#ibcon#*before return 0, iclass 21, count 2 2006.173.13:35:02.37#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.13:35:02.37#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.13:35:02.37#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.13:35:02.37#ibcon#ireg 7 cls_cnt 0 2006.173.13:35:02.37#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.13:35:02.49#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.13:35:02.49#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.13:35:02.49#ibcon#enter wrdev, iclass 21, count 0 2006.173.13:35:02.49#ibcon#first serial, iclass 21, count 0 2006.173.13:35:02.49#ibcon#enter sib2, iclass 21, count 0 2006.173.13:35:02.49#ibcon#flushed, iclass 21, count 0 2006.173.13:35:02.49#ibcon#about to write, iclass 21, count 0 2006.173.13:35:02.49#ibcon#wrote, iclass 21, count 0 2006.173.13:35:02.49#ibcon#about to read 3, iclass 21, count 0 2006.173.13:35:02.51#ibcon#read 3, iclass 21, count 0 2006.173.13:35:02.51#ibcon#about to read 4, iclass 21, count 0 2006.173.13:35:02.51#ibcon#read 4, iclass 21, count 0 2006.173.13:35:02.51#ibcon#about to read 5, iclass 21, count 0 2006.173.13:35:02.51#ibcon#read 5, iclass 21, count 0 2006.173.13:35:02.51#ibcon#about to read 6, iclass 21, count 0 2006.173.13:35:02.51#ibcon#read 6, iclass 21, count 0 2006.173.13:35:02.51#ibcon#end of sib2, iclass 21, count 0 2006.173.13:35:02.51#ibcon#*mode == 0, iclass 21, count 0 2006.173.13:35:02.51#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.13:35:02.51#ibcon#[27=USB\r\n] 2006.173.13:35:02.51#ibcon#*before write, iclass 21, count 0 2006.173.13:35:02.51#ibcon#enter sib2, iclass 21, count 0 2006.173.13:35:02.51#ibcon#flushed, iclass 21, count 0 2006.173.13:35:02.51#ibcon#about to write, iclass 21, count 0 2006.173.13:35:02.51#ibcon#wrote, iclass 21, count 0 2006.173.13:35:02.51#ibcon#about to read 3, iclass 21, count 0 2006.173.13:35:02.54#ibcon#read 3, iclass 21, count 0 2006.173.13:35:02.54#ibcon#about to read 4, iclass 21, count 0 2006.173.13:35:02.54#ibcon#read 4, iclass 21, count 0 2006.173.13:35:02.54#ibcon#about to read 5, iclass 21, count 0 2006.173.13:35:02.54#ibcon#read 5, iclass 21, count 0 2006.173.13:35:02.54#ibcon#about to read 6, iclass 21, count 0 2006.173.13:35:02.54#ibcon#read 6, iclass 21, count 0 2006.173.13:35:02.54#ibcon#end of sib2, iclass 21, count 0 2006.173.13:35:02.54#ibcon#*after write, iclass 21, count 0 2006.173.13:35:02.54#ibcon#*before return 0, iclass 21, count 0 2006.173.13:35:02.54#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.13:35:02.54#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.13:35:02.54#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.13:35:02.54#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.13:35:02.54$vck44/vblo=3,649.99 2006.173.13:35:02.54#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.13:35:02.54#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.13:35:02.54#ibcon#ireg 17 cls_cnt 0 2006.173.13:35:02.54#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.13:35:02.54#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.13:35:02.54#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.13:35:02.54#ibcon#enter wrdev, iclass 23, count 0 2006.173.13:35:02.54#ibcon#first serial, iclass 23, count 0 2006.173.13:35:02.54#ibcon#enter sib2, iclass 23, count 0 2006.173.13:35:02.54#ibcon#flushed, iclass 23, count 0 2006.173.13:35:02.54#ibcon#about to write, iclass 23, count 0 2006.173.13:35:02.54#ibcon#wrote, iclass 23, count 0 2006.173.13:35:02.54#ibcon#about to read 3, iclass 23, count 0 2006.173.13:35:02.56#ibcon#read 3, iclass 23, count 0 2006.173.13:35:02.56#ibcon#about to read 4, iclass 23, count 0 2006.173.13:35:02.56#ibcon#read 4, iclass 23, count 0 2006.173.13:35:02.56#ibcon#about to read 5, iclass 23, count 0 2006.173.13:35:02.56#ibcon#read 5, iclass 23, count 0 2006.173.13:35:02.56#ibcon#about to read 6, iclass 23, count 0 2006.173.13:35:02.56#ibcon#read 6, iclass 23, count 0 2006.173.13:35:02.56#ibcon#end of sib2, iclass 23, count 0 2006.173.13:35:02.56#ibcon#*mode == 0, iclass 23, count 0 2006.173.13:35:02.56#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.13:35:02.56#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.13:35:02.56#ibcon#*before write, iclass 23, count 0 2006.173.13:35:02.56#ibcon#enter sib2, iclass 23, count 0 2006.173.13:35:02.56#ibcon#flushed, iclass 23, count 0 2006.173.13:35:02.56#ibcon#about to write, iclass 23, count 0 2006.173.13:35:02.56#ibcon#wrote, iclass 23, count 0 2006.173.13:35:02.56#ibcon#about to read 3, iclass 23, count 0 2006.173.13:35:02.60#ibcon#read 3, iclass 23, count 0 2006.173.13:35:02.60#ibcon#about to read 4, iclass 23, count 0 2006.173.13:35:02.60#ibcon#read 4, iclass 23, count 0 2006.173.13:35:02.60#ibcon#about to read 5, iclass 23, count 0 2006.173.13:35:02.60#ibcon#read 5, iclass 23, count 0 2006.173.13:35:02.60#ibcon#about to read 6, iclass 23, count 0 2006.173.13:35:02.60#ibcon#read 6, iclass 23, count 0 2006.173.13:35:02.60#ibcon#end of sib2, iclass 23, count 0 2006.173.13:35:02.60#ibcon#*after write, iclass 23, count 0 2006.173.13:35:02.60#ibcon#*before return 0, iclass 23, count 0 2006.173.13:35:02.60#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.13:35:02.60#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.13:35:02.60#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.13:35:02.60#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.13:35:02.60$vck44/vb=3,4 2006.173.13:35:02.60#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.13:35:02.60#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.13:35:02.60#ibcon#ireg 11 cls_cnt 2 2006.173.13:35:02.60#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.13:35:02.66#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.13:35:02.66#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.13:35:02.66#ibcon#enter wrdev, iclass 25, count 2 2006.173.13:35:02.66#ibcon#first serial, iclass 25, count 2 2006.173.13:35:02.66#ibcon#enter sib2, iclass 25, count 2 2006.173.13:35:02.66#ibcon#flushed, iclass 25, count 2 2006.173.13:35:02.66#ibcon#about to write, iclass 25, count 2 2006.173.13:35:02.66#ibcon#wrote, iclass 25, count 2 2006.173.13:35:02.66#ibcon#about to read 3, iclass 25, count 2 2006.173.13:35:02.68#ibcon#read 3, iclass 25, count 2 2006.173.13:35:02.68#ibcon#about to read 4, iclass 25, count 2 2006.173.13:35:02.68#ibcon#read 4, iclass 25, count 2 2006.173.13:35:02.68#ibcon#about to read 5, iclass 25, count 2 2006.173.13:35:02.68#ibcon#read 5, iclass 25, count 2 2006.173.13:35:02.68#ibcon#about to read 6, iclass 25, count 2 2006.173.13:35:02.68#ibcon#read 6, iclass 25, count 2 2006.173.13:35:02.68#ibcon#end of sib2, iclass 25, count 2 2006.173.13:35:02.68#ibcon#*mode == 0, iclass 25, count 2 2006.173.13:35:02.68#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.13:35:02.68#ibcon#[27=AT03-04\r\n] 2006.173.13:35:02.68#ibcon#*before write, iclass 25, count 2 2006.173.13:35:02.68#ibcon#enter sib2, iclass 25, count 2 2006.173.13:35:02.68#ibcon#flushed, iclass 25, count 2 2006.173.13:35:02.68#ibcon#about to write, iclass 25, count 2 2006.173.13:35:02.68#ibcon#wrote, iclass 25, count 2 2006.173.13:35:02.68#ibcon#about to read 3, iclass 25, count 2 2006.173.13:35:02.71#ibcon#read 3, iclass 25, count 2 2006.173.13:35:02.71#ibcon#about to read 4, iclass 25, count 2 2006.173.13:35:02.71#ibcon#read 4, iclass 25, count 2 2006.173.13:35:02.71#ibcon#about to read 5, iclass 25, count 2 2006.173.13:35:02.71#ibcon#read 5, iclass 25, count 2 2006.173.13:35:02.71#ibcon#about to read 6, iclass 25, count 2 2006.173.13:35:02.71#ibcon#read 6, iclass 25, count 2 2006.173.13:35:02.71#ibcon#end of sib2, iclass 25, count 2 2006.173.13:35:02.71#ibcon#*after write, iclass 25, count 2 2006.173.13:35:02.71#ibcon#*before return 0, iclass 25, count 2 2006.173.13:35:02.71#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.13:35:02.71#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.13:35:02.71#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.13:35:02.71#ibcon#ireg 7 cls_cnt 0 2006.173.13:35:02.71#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.13:35:02.83#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.13:35:02.83#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.13:35:02.83#ibcon#enter wrdev, iclass 25, count 0 2006.173.13:35:02.83#ibcon#first serial, iclass 25, count 0 2006.173.13:35:02.83#ibcon#enter sib2, iclass 25, count 0 2006.173.13:35:02.83#ibcon#flushed, iclass 25, count 0 2006.173.13:35:02.83#ibcon#about to write, iclass 25, count 0 2006.173.13:35:02.83#ibcon#wrote, iclass 25, count 0 2006.173.13:35:02.83#ibcon#about to read 3, iclass 25, count 0 2006.173.13:35:02.85#ibcon#read 3, iclass 25, count 0 2006.173.13:35:02.85#ibcon#about to read 4, iclass 25, count 0 2006.173.13:35:02.85#ibcon#read 4, iclass 25, count 0 2006.173.13:35:02.85#ibcon#about to read 5, iclass 25, count 0 2006.173.13:35:02.85#ibcon#read 5, iclass 25, count 0 2006.173.13:35:02.85#ibcon#about to read 6, iclass 25, count 0 2006.173.13:35:02.85#ibcon#read 6, iclass 25, count 0 2006.173.13:35:02.85#ibcon#end of sib2, iclass 25, count 0 2006.173.13:35:02.85#ibcon#*mode == 0, iclass 25, count 0 2006.173.13:35:02.85#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.13:35:02.85#ibcon#[27=USB\r\n] 2006.173.13:35:02.85#ibcon#*before write, iclass 25, count 0 2006.173.13:35:02.85#ibcon#enter sib2, iclass 25, count 0 2006.173.13:35:02.85#ibcon#flushed, iclass 25, count 0 2006.173.13:35:02.85#ibcon#about to write, iclass 25, count 0 2006.173.13:35:02.85#ibcon#wrote, iclass 25, count 0 2006.173.13:35:02.85#ibcon#about to read 3, iclass 25, count 0 2006.173.13:35:02.88#ibcon#read 3, iclass 25, count 0 2006.173.13:35:02.88#ibcon#about to read 4, iclass 25, count 0 2006.173.13:35:02.88#ibcon#read 4, iclass 25, count 0 2006.173.13:35:02.88#ibcon#about to read 5, iclass 25, count 0 2006.173.13:35:02.88#ibcon#read 5, iclass 25, count 0 2006.173.13:35:02.88#ibcon#about to read 6, iclass 25, count 0 2006.173.13:35:02.88#ibcon#read 6, iclass 25, count 0 2006.173.13:35:02.88#ibcon#end of sib2, iclass 25, count 0 2006.173.13:35:02.88#ibcon#*after write, iclass 25, count 0 2006.173.13:35:02.88#ibcon#*before return 0, iclass 25, count 0 2006.173.13:35:02.88#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.13:35:02.88#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.13:35:02.88#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.13:35:02.88#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.13:35:02.88$vck44/vblo=4,679.99 2006.173.13:35:02.88#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.13:35:02.88#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.13:35:02.88#ibcon#ireg 17 cls_cnt 0 2006.173.13:35:02.88#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.13:35:02.88#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.13:35:02.88#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.13:35:02.88#ibcon#enter wrdev, iclass 27, count 0 2006.173.13:35:02.88#ibcon#first serial, iclass 27, count 0 2006.173.13:35:02.88#ibcon#enter sib2, iclass 27, count 0 2006.173.13:35:02.88#ibcon#flushed, iclass 27, count 0 2006.173.13:35:02.88#ibcon#about to write, iclass 27, count 0 2006.173.13:35:02.88#ibcon#wrote, iclass 27, count 0 2006.173.13:35:02.88#ibcon#about to read 3, iclass 27, count 0 2006.173.13:35:02.90#ibcon#read 3, iclass 27, count 0 2006.173.13:35:02.90#ibcon#about to read 4, iclass 27, count 0 2006.173.13:35:02.90#ibcon#read 4, iclass 27, count 0 2006.173.13:35:02.90#ibcon#about to read 5, iclass 27, count 0 2006.173.13:35:02.90#ibcon#read 5, iclass 27, count 0 2006.173.13:35:02.90#ibcon#about to read 6, iclass 27, count 0 2006.173.13:35:02.90#ibcon#read 6, iclass 27, count 0 2006.173.13:35:02.90#ibcon#end of sib2, iclass 27, count 0 2006.173.13:35:02.90#ibcon#*mode == 0, iclass 27, count 0 2006.173.13:35:02.90#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.13:35:02.90#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.13:35:02.90#ibcon#*before write, iclass 27, count 0 2006.173.13:35:02.90#ibcon#enter sib2, iclass 27, count 0 2006.173.13:35:02.90#ibcon#flushed, iclass 27, count 0 2006.173.13:35:02.90#ibcon#about to write, iclass 27, count 0 2006.173.13:35:02.90#ibcon#wrote, iclass 27, count 0 2006.173.13:35:02.90#ibcon#about to read 3, iclass 27, count 0 2006.173.13:35:02.94#ibcon#read 3, iclass 27, count 0 2006.173.13:35:02.94#ibcon#about to read 4, iclass 27, count 0 2006.173.13:35:02.94#ibcon#read 4, iclass 27, count 0 2006.173.13:35:02.94#ibcon#about to read 5, iclass 27, count 0 2006.173.13:35:02.94#ibcon#read 5, iclass 27, count 0 2006.173.13:35:02.94#ibcon#about to read 6, iclass 27, count 0 2006.173.13:35:02.94#ibcon#read 6, iclass 27, count 0 2006.173.13:35:02.94#ibcon#end of sib2, iclass 27, count 0 2006.173.13:35:02.94#ibcon#*after write, iclass 27, count 0 2006.173.13:35:02.94#ibcon#*before return 0, iclass 27, count 0 2006.173.13:35:02.94#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.13:35:02.94#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.13:35:02.94#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.13:35:02.94#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.13:35:02.94$vck44/vb=4,4 2006.173.13:35:02.94#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.13:35:02.94#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.13:35:02.94#ibcon#ireg 11 cls_cnt 2 2006.173.13:35:02.94#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.13:35:03.00#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.13:35:03.00#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.13:35:03.00#ibcon#enter wrdev, iclass 29, count 2 2006.173.13:35:03.00#ibcon#first serial, iclass 29, count 2 2006.173.13:35:03.00#ibcon#enter sib2, iclass 29, count 2 2006.173.13:35:03.00#ibcon#flushed, iclass 29, count 2 2006.173.13:35:03.00#ibcon#about to write, iclass 29, count 2 2006.173.13:35:03.00#ibcon#wrote, iclass 29, count 2 2006.173.13:35:03.00#ibcon#about to read 3, iclass 29, count 2 2006.173.13:35:03.02#ibcon#read 3, iclass 29, count 2 2006.173.13:35:03.02#ibcon#about to read 4, iclass 29, count 2 2006.173.13:35:03.02#ibcon#read 4, iclass 29, count 2 2006.173.13:35:03.02#ibcon#about to read 5, iclass 29, count 2 2006.173.13:35:03.02#ibcon#read 5, iclass 29, count 2 2006.173.13:35:03.02#ibcon#about to read 6, iclass 29, count 2 2006.173.13:35:03.02#ibcon#read 6, iclass 29, count 2 2006.173.13:35:03.02#ibcon#end of sib2, iclass 29, count 2 2006.173.13:35:03.02#ibcon#*mode == 0, iclass 29, count 2 2006.173.13:35:03.02#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.13:35:03.02#ibcon#[27=AT04-04\r\n] 2006.173.13:35:03.02#ibcon#*before write, iclass 29, count 2 2006.173.13:35:03.02#ibcon#enter sib2, iclass 29, count 2 2006.173.13:35:03.02#ibcon#flushed, iclass 29, count 2 2006.173.13:35:03.02#ibcon#about to write, iclass 29, count 2 2006.173.13:35:03.02#ibcon#wrote, iclass 29, count 2 2006.173.13:35:03.02#ibcon#about to read 3, iclass 29, count 2 2006.173.13:35:03.05#ibcon#read 3, iclass 29, count 2 2006.173.13:35:03.05#ibcon#about to read 4, iclass 29, count 2 2006.173.13:35:03.05#ibcon#read 4, iclass 29, count 2 2006.173.13:35:03.05#ibcon#about to read 5, iclass 29, count 2 2006.173.13:35:03.05#ibcon#read 5, iclass 29, count 2 2006.173.13:35:03.05#ibcon#about to read 6, iclass 29, count 2 2006.173.13:35:03.05#ibcon#read 6, iclass 29, count 2 2006.173.13:35:03.05#ibcon#end of sib2, iclass 29, count 2 2006.173.13:35:03.05#ibcon#*after write, iclass 29, count 2 2006.173.13:35:03.05#ibcon#*before return 0, iclass 29, count 2 2006.173.13:35:03.05#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.13:35:03.05#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.13:35:03.05#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.13:35:03.05#ibcon#ireg 7 cls_cnt 0 2006.173.13:35:03.05#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.13:35:03.17#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.13:35:03.17#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.13:35:03.17#ibcon#enter wrdev, iclass 29, count 0 2006.173.13:35:03.17#ibcon#first serial, iclass 29, count 0 2006.173.13:35:03.17#ibcon#enter sib2, iclass 29, count 0 2006.173.13:35:03.17#ibcon#flushed, iclass 29, count 0 2006.173.13:35:03.17#ibcon#about to write, iclass 29, count 0 2006.173.13:35:03.17#ibcon#wrote, iclass 29, count 0 2006.173.13:35:03.17#ibcon#about to read 3, iclass 29, count 0 2006.173.13:35:03.19#ibcon#read 3, iclass 29, count 0 2006.173.13:35:03.19#ibcon#about to read 4, iclass 29, count 0 2006.173.13:35:03.19#ibcon#read 4, iclass 29, count 0 2006.173.13:35:03.19#ibcon#about to read 5, iclass 29, count 0 2006.173.13:35:03.19#ibcon#read 5, iclass 29, count 0 2006.173.13:35:03.19#ibcon#about to read 6, iclass 29, count 0 2006.173.13:35:03.19#ibcon#read 6, iclass 29, count 0 2006.173.13:35:03.19#ibcon#end of sib2, iclass 29, count 0 2006.173.13:35:03.19#ibcon#*mode == 0, iclass 29, count 0 2006.173.13:35:03.19#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.13:35:03.19#ibcon#[27=USB\r\n] 2006.173.13:35:03.19#ibcon#*before write, iclass 29, count 0 2006.173.13:35:03.19#ibcon#enter sib2, iclass 29, count 0 2006.173.13:35:03.19#ibcon#flushed, iclass 29, count 0 2006.173.13:35:03.19#ibcon#about to write, iclass 29, count 0 2006.173.13:35:03.19#ibcon#wrote, iclass 29, count 0 2006.173.13:35:03.19#ibcon#about to read 3, iclass 29, count 0 2006.173.13:35:03.22#ibcon#read 3, iclass 29, count 0 2006.173.13:35:03.22#ibcon#about to read 4, iclass 29, count 0 2006.173.13:35:03.22#ibcon#read 4, iclass 29, count 0 2006.173.13:35:03.22#ibcon#about to read 5, iclass 29, count 0 2006.173.13:35:03.22#ibcon#read 5, iclass 29, count 0 2006.173.13:35:03.22#ibcon#about to read 6, iclass 29, count 0 2006.173.13:35:03.22#ibcon#read 6, iclass 29, count 0 2006.173.13:35:03.22#ibcon#end of sib2, iclass 29, count 0 2006.173.13:35:03.22#ibcon#*after write, iclass 29, count 0 2006.173.13:35:03.22#ibcon#*before return 0, iclass 29, count 0 2006.173.13:35:03.22#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.13:35:03.22#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.13:35:03.22#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.13:35:03.22#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.13:35:03.22$vck44/vblo=5,709.99 2006.173.13:35:03.22#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.13:35:03.22#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.13:35:03.22#ibcon#ireg 17 cls_cnt 0 2006.173.13:35:03.22#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.13:35:03.22#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.13:35:03.22#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.13:35:03.22#ibcon#enter wrdev, iclass 31, count 0 2006.173.13:35:03.22#ibcon#first serial, iclass 31, count 0 2006.173.13:35:03.22#ibcon#enter sib2, iclass 31, count 0 2006.173.13:35:03.22#ibcon#flushed, iclass 31, count 0 2006.173.13:35:03.22#ibcon#about to write, iclass 31, count 0 2006.173.13:35:03.22#ibcon#wrote, iclass 31, count 0 2006.173.13:35:03.22#ibcon#about to read 3, iclass 31, count 0 2006.173.13:35:03.24#ibcon#read 3, iclass 31, count 0 2006.173.13:35:03.24#ibcon#about to read 4, iclass 31, count 0 2006.173.13:35:03.24#ibcon#read 4, iclass 31, count 0 2006.173.13:35:03.24#ibcon#about to read 5, iclass 31, count 0 2006.173.13:35:03.24#ibcon#read 5, iclass 31, count 0 2006.173.13:35:03.24#ibcon#about to read 6, iclass 31, count 0 2006.173.13:35:03.24#ibcon#read 6, iclass 31, count 0 2006.173.13:35:03.24#ibcon#end of sib2, iclass 31, count 0 2006.173.13:35:03.24#ibcon#*mode == 0, iclass 31, count 0 2006.173.13:35:03.24#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.13:35:03.24#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.13:35:03.24#ibcon#*before write, iclass 31, count 0 2006.173.13:35:03.24#ibcon#enter sib2, iclass 31, count 0 2006.173.13:35:03.24#ibcon#flushed, iclass 31, count 0 2006.173.13:35:03.24#ibcon#about to write, iclass 31, count 0 2006.173.13:35:03.24#ibcon#wrote, iclass 31, count 0 2006.173.13:35:03.24#ibcon#about to read 3, iclass 31, count 0 2006.173.13:35:03.28#ibcon#read 3, iclass 31, count 0 2006.173.13:35:03.28#ibcon#about to read 4, iclass 31, count 0 2006.173.13:35:03.28#ibcon#read 4, iclass 31, count 0 2006.173.13:35:03.28#ibcon#about to read 5, iclass 31, count 0 2006.173.13:35:03.28#ibcon#read 5, iclass 31, count 0 2006.173.13:35:03.28#ibcon#about to read 6, iclass 31, count 0 2006.173.13:35:03.28#ibcon#read 6, iclass 31, count 0 2006.173.13:35:03.28#ibcon#end of sib2, iclass 31, count 0 2006.173.13:35:03.28#ibcon#*after write, iclass 31, count 0 2006.173.13:35:03.28#ibcon#*before return 0, iclass 31, count 0 2006.173.13:35:03.28#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.13:35:03.28#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.13:35:03.28#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.13:35:03.28#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.13:35:03.28$vck44/vb=5,4 2006.173.13:35:03.28#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.173.13:35:03.28#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.173.13:35:03.28#ibcon#ireg 11 cls_cnt 2 2006.173.13:35:03.28#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.13:35:03.34#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.13:35:03.34#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.13:35:03.34#ibcon#enter wrdev, iclass 33, count 2 2006.173.13:35:03.34#ibcon#first serial, iclass 33, count 2 2006.173.13:35:03.34#ibcon#enter sib2, iclass 33, count 2 2006.173.13:35:03.34#ibcon#flushed, iclass 33, count 2 2006.173.13:35:03.34#ibcon#about to write, iclass 33, count 2 2006.173.13:35:03.34#ibcon#wrote, iclass 33, count 2 2006.173.13:35:03.34#ibcon#about to read 3, iclass 33, count 2 2006.173.13:35:03.36#ibcon#read 3, iclass 33, count 2 2006.173.13:35:03.36#ibcon#about to read 4, iclass 33, count 2 2006.173.13:35:03.36#ibcon#read 4, iclass 33, count 2 2006.173.13:35:03.36#ibcon#about to read 5, iclass 33, count 2 2006.173.13:35:03.36#ibcon#read 5, iclass 33, count 2 2006.173.13:35:03.36#ibcon#about to read 6, iclass 33, count 2 2006.173.13:35:03.36#ibcon#read 6, iclass 33, count 2 2006.173.13:35:03.36#ibcon#end of sib2, iclass 33, count 2 2006.173.13:35:03.36#ibcon#*mode == 0, iclass 33, count 2 2006.173.13:35:03.36#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.173.13:35:03.36#ibcon#[27=AT05-04\r\n] 2006.173.13:35:03.36#ibcon#*before write, iclass 33, count 2 2006.173.13:35:03.36#ibcon#enter sib2, iclass 33, count 2 2006.173.13:35:03.36#ibcon#flushed, iclass 33, count 2 2006.173.13:35:03.36#ibcon#about to write, iclass 33, count 2 2006.173.13:35:03.36#ibcon#wrote, iclass 33, count 2 2006.173.13:35:03.36#ibcon#about to read 3, iclass 33, count 2 2006.173.13:35:03.39#ibcon#read 3, iclass 33, count 2 2006.173.13:35:03.39#ibcon#about to read 4, iclass 33, count 2 2006.173.13:35:03.39#ibcon#read 4, iclass 33, count 2 2006.173.13:35:03.39#ibcon#about to read 5, iclass 33, count 2 2006.173.13:35:03.39#ibcon#read 5, iclass 33, count 2 2006.173.13:35:03.39#ibcon#about to read 6, iclass 33, count 2 2006.173.13:35:03.39#ibcon#read 6, iclass 33, count 2 2006.173.13:35:03.39#ibcon#end of sib2, iclass 33, count 2 2006.173.13:35:03.39#ibcon#*after write, iclass 33, count 2 2006.173.13:35:03.39#ibcon#*before return 0, iclass 33, count 2 2006.173.13:35:03.39#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.13:35:03.39#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.173.13:35:03.39#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.173.13:35:03.39#ibcon#ireg 7 cls_cnt 0 2006.173.13:35:03.39#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.13:35:03.51#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.13:35:03.51#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.13:35:03.51#ibcon#enter wrdev, iclass 33, count 0 2006.173.13:35:03.51#ibcon#first serial, iclass 33, count 0 2006.173.13:35:03.51#ibcon#enter sib2, iclass 33, count 0 2006.173.13:35:03.51#ibcon#flushed, iclass 33, count 0 2006.173.13:35:03.51#ibcon#about to write, iclass 33, count 0 2006.173.13:35:03.51#ibcon#wrote, iclass 33, count 0 2006.173.13:35:03.51#ibcon#about to read 3, iclass 33, count 0 2006.173.13:35:03.53#ibcon#read 3, iclass 33, count 0 2006.173.13:35:03.53#ibcon#about to read 4, iclass 33, count 0 2006.173.13:35:03.53#ibcon#read 4, iclass 33, count 0 2006.173.13:35:03.53#ibcon#about to read 5, iclass 33, count 0 2006.173.13:35:03.53#ibcon#read 5, iclass 33, count 0 2006.173.13:35:03.53#ibcon#about to read 6, iclass 33, count 0 2006.173.13:35:03.53#ibcon#read 6, iclass 33, count 0 2006.173.13:35:03.53#ibcon#end of sib2, iclass 33, count 0 2006.173.13:35:03.53#ibcon#*mode == 0, iclass 33, count 0 2006.173.13:35:03.53#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.13:35:03.53#ibcon#[27=USB\r\n] 2006.173.13:35:03.53#ibcon#*before write, iclass 33, count 0 2006.173.13:35:03.53#ibcon#enter sib2, iclass 33, count 0 2006.173.13:35:03.53#ibcon#flushed, iclass 33, count 0 2006.173.13:35:03.53#ibcon#about to write, iclass 33, count 0 2006.173.13:35:03.53#ibcon#wrote, iclass 33, count 0 2006.173.13:35:03.53#ibcon#about to read 3, iclass 33, count 0 2006.173.13:35:03.56#ibcon#read 3, iclass 33, count 0 2006.173.13:35:03.56#ibcon#about to read 4, iclass 33, count 0 2006.173.13:35:03.56#ibcon#read 4, iclass 33, count 0 2006.173.13:35:03.56#ibcon#about to read 5, iclass 33, count 0 2006.173.13:35:03.56#ibcon#read 5, iclass 33, count 0 2006.173.13:35:03.56#ibcon#about to read 6, iclass 33, count 0 2006.173.13:35:03.56#ibcon#read 6, iclass 33, count 0 2006.173.13:35:03.56#ibcon#end of sib2, iclass 33, count 0 2006.173.13:35:03.56#ibcon#*after write, iclass 33, count 0 2006.173.13:35:03.56#ibcon#*before return 0, iclass 33, count 0 2006.173.13:35:03.56#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.13:35:03.56#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.173.13:35:03.56#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.13:35:03.56#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.13:35:03.56$vck44/vblo=6,719.99 2006.173.13:35:03.56#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.13:35:03.56#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.13:35:03.56#ibcon#ireg 17 cls_cnt 0 2006.173.13:35:03.56#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.13:35:03.56#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.13:35:03.56#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.13:35:03.56#ibcon#enter wrdev, iclass 35, count 0 2006.173.13:35:03.56#ibcon#first serial, iclass 35, count 0 2006.173.13:35:03.56#ibcon#enter sib2, iclass 35, count 0 2006.173.13:35:03.56#ibcon#flushed, iclass 35, count 0 2006.173.13:35:03.56#ibcon#about to write, iclass 35, count 0 2006.173.13:35:03.56#ibcon#wrote, iclass 35, count 0 2006.173.13:35:03.56#ibcon#about to read 3, iclass 35, count 0 2006.173.13:35:03.58#ibcon#read 3, iclass 35, count 0 2006.173.13:35:03.58#ibcon#about to read 4, iclass 35, count 0 2006.173.13:35:03.58#ibcon#read 4, iclass 35, count 0 2006.173.13:35:03.58#ibcon#about to read 5, iclass 35, count 0 2006.173.13:35:03.58#ibcon#read 5, iclass 35, count 0 2006.173.13:35:03.58#ibcon#about to read 6, iclass 35, count 0 2006.173.13:35:03.58#ibcon#read 6, iclass 35, count 0 2006.173.13:35:03.58#ibcon#end of sib2, iclass 35, count 0 2006.173.13:35:03.58#ibcon#*mode == 0, iclass 35, count 0 2006.173.13:35:03.58#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.13:35:03.58#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.13:35:03.58#ibcon#*before write, iclass 35, count 0 2006.173.13:35:03.58#ibcon#enter sib2, iclass 35, count 0 2006.173.13:35:03.58#ibcon#flushed, iclass 35, count 0 2006.173.13:35:03.58#ibcon#about to write, iclass 35, count 0 2006.173.13:35:03.58#ibcon#wrote, iclass 35, count 0 2006.173.13:35:03.58#ibcon#about to read 3, iclass 35, count 0 2006.173.13:35:03.62#ibcon#read 3, iclass 35, count 0 2006.173.13:35:03.62#ibcon#about to read 4, iclass 35, count 0 2006.173.13:35:03.62#ibcon#read 4, iclass 35, count 0 2006.173.13:35:03.62#ibcon#about to read 5, iclass 35, count 0 2006.173.13:35:03.62#ibcon#read 5, iclass 35, count 0 2006.173.13:35:03.62#ibcon#about to read 6, iclass 35, count 0 2006.173.13:35:03.62#ibcon#read 6, iclass 35, count 0 2006.173.13:35:03.62#ibcon#end of sib2, iclass 35, count 0 2006.173.13:35:03.62#ibcon#*after write, iclass 35, count 0 2006.173.13:35:03.62#ibcon#*before return 0, iclass 35, count 0 2006.173.13:35:03.62#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.13:35:03.62#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.13:35:03.62#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.13:35:03.62#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.13:35:03.62$vck44/vb=6,4 2006.173.13:35:03.62#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.173.13:35:03.62#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.173.13:35:03.62#ibcon#ireg 11 cls_cnt 2 2006.173.13:35:03.62#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.13:35:03.68#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.13:35:03.68#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.13:35:03.68#ibcon#enter wrdev, iclass 37, count 2 2006.173.13:35:03.68#ibcon#first serial, iclass 37, count 2 2006.173.13:35:03.68#ibcon#enter sib2, iclass 37, count 2 2006.173.13:35:03.68#ibcon#flushed, iclass 37, count 2 2006.173.13:35:03.68#ibcon#about to write, iclass 37, count 2 2006.173.13:35:03.68#ibcon#wrote, iclass 37, count 2 2006.173.13:35:03.68#ibcon#about to read 3, iclass 37, count 2 2006.173.13:35:03.70#ibcon#read 3, iclass 37, count 2 2006.173.13:35:03.70#ibcon#about to read 4, iclass 37, count 2 2006.173.13:35:03.70#ibcon#read 4, iclass 37, count 2 2006.173.13:35:03.70#ibcon#about to read 5, iclass 37, count 2 2006.173.13:35:03.70#ibcon#read 5, iclass 37, count 2 2006.173.13:35:03.70#ibcon#about to read 6, iclass 37, count 2 2006.173.13:35:03.70#ibcon#read 6, iclass 37, count 2 2006.173.13:35:03.70#ibcon#end of sib2, iclass 37, count 2 2006.173.13:35:03.70#ibcon#*mode == 0, iclass 37, count 2 2006.173.13:35:03.70#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.173.13:35:03.70#ibcon#[27=AT06-04\r\n] 2006.173.13:35:03.70#ibcon#*before write, iclass 37, count 2 2006.173.13:35:03.70#ibcon#enter sib2, iclass 37, count 2 2006.173.13:35:03.70#ibcon#flushed, iclass 37, count 2 2006.173.13:35:03.70#ibcon#about to write, iclass 37, count 2 2006.173.13:35:03.70#ibcon#wrote, iclass 37, count 2 2006.173.13:35:03.70#ibcon#about to read 3, iclass 37, count 2 2006.173.13:35:03.73#ibcon#read 3, iclass 37, count 2 2006.173.13:35:03.73#ibcon#about to read 4, iclass 37, count 2 2006.173.13:35:03.73#ibcon#read 4, iclass 37, count 2 2006.173.13:35:03.73#ibcon#about to read 5, iclass 37, count 2 2006.173.13:35:03.73#ibcon#read 5, iclass 37, count 2 2006.173.13:35:03.73#ibcon#about to read 6, iclass 37, count 2 2006.173.13:35:03.73#ibcon#read 6, iclass 37, count 2 2006.173.13:35:03.73#ibcon#end of sib2, iclass 37, count 2 2006.173.13:35:03.73#ibcon#*after write, iclass 37, count 2 2006.173.13:35:03.73#ibcon#*before return 0, iclass 37, count 2 2006.173.13:35:03.73#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.13:35:03.73#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.173.13:35:03.73#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.173.13:35:03.73#ibcon#ireg 7 cls_cnt 0 2006.173.13:35:03.73#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.13:35:03.76#abcon#<5=/04 0.6 1.3 21.961001003.8\r\n> 2006.173.13:35:03.78#abcon#{5=INTERFACE CLEAR} 2006.173.13:35:03.84#abcon#[5=S1D000X0/0*\r\n] 2006.173.13:35:03.85#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.13:35:03.85#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.13:35:03.85#ibcon#enter wrdev, iclass 37, count 0 2006.173.13:35:03.85#ibcon#first serial, iclass 37, count 0 2006.173.13:35:03.85#ibcon#enter sib2, iclass 37, count 0 2006.173.13:35:03.85#ibcon#flushed, iclass 37, count 0 2006.173.13:35:03.85#ibcon#about to write, iclass 37, count 0 2006.173.13:35:03.85#ibcon#wrote, iclass 37, count 0 2006.173.13:35:03.85#ibcon#about to read 3, iclass 37, count 0 2006.173.13:35:03.87#ibcon#read 3, iclass 37, count 0 2006.173.13:35:03.87#ibcon#about to read 4, iclass 37, count 0 2006.173.13:35:03.87#ibcon#read 4, iclass 37, count 0 2006.173.13:35:03.87#ibcon#about to read 5, iclass 37, count 0 2006.173.13:35:03.87#ibcon#read 5, iclass 37, count 0 2006.173.13:35:03.87#ibcon#about to read 6, iclass 37, count 0 2006.173.13:35:03.87#ibcon#read 6, iclass 37, count 0 2006.173.13:35:03.87#ibcon#end of sib2, iclass 37, count 0 2006.173.13:35:03.87#ibcon#*mode == 0, iclass 37, count 0 2006.173.13:35:03.87#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.13:35:03.87#ibcon#[27=USB\r\n] 2006.173.13:35:03.87#ibcon#*before write, iclass 37, count 0 2006.173.13:35:03.87#ibcon#enter sib2, iclass 37, count 0 2006.173.13:35:03.87#ibcon#flushed, iclass 37, count 0 2006.173.13:35:03.87#ibcon#about to write, iclass 37, count 0 2006.173.13:35:03.87#ibcon#wrote, iclass 37, count 0 2006.173.13:35:03.87#ibcon#about to read 3, iclass 37, count 0 2006.173.13:35:03.90#ibcon#read 3, iclass 37, count 0 2006.173.13:35:03.90#ibcon#about to read 4, iclass 37, count 0 2006.173.13:35:03.90#ibcon#read 4, iclass 37, count 0 2006.173.13:35:03.90#ibcon#about to read 5, iclass 37, count 0 2006.173.13:35:03.90#ibcon#read 5, iclass 37, count 0 2006.173.13:35:03.90#ibcon#about to read 6, iclass 37, count 0 2006.173.13:35:03.90#ibcon#read 6, iclass 37, count 0 2006.173.13:35:03.90#ibcon#end of sib2, iclass 37, count 0 2006.173.13:35:03.90#ibcon#*after write, iclass 37, count 0 2006.173.13:35:03.90#ibcon#*before return 0, iclass 37, count 0 2006.173.13:35:03.90#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.13:35:03.90#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.173.13:35:03.90#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.13:35:03.90#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.13:35:03.90$vck44/vblo=7,734.99 2006.173.13:35:03.90#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.13:35:03.90#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.13:35:03.90#ibcon#ireg 17 cls_cnt 0 2006.173.13:35:03.90#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.13:35:03.90#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.13:35:03.90#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.13:35:03.90#ibcon#enter wrdev, iclass 5, count 0 2006.173.13:35:03.90#ibcon#first serial, iclass 5, count 0 2006.173.13:35:03.90#ibcon#enter sib2, iclass 5, count 0 2006.173.13:35:03.90#ibcon#flushed, iclass 5, count 0 2006.173.13:35:03.90#ibcon#about to write, iclass 5, count 0 2006.173.13:35:03.90#ibcon#wrote, iclass 5, count 0 2006.173.13:35:03.90#ibcon#about to read 3, iclass 5, count 0 2006.173.13:35:03.92#ibcon#read 3, iclass 5, count 0 2006.173.13:35:03.92#ibcon#about to read 4, iclass 5, count 0 2006.173.13:35:03.92#ibcon#read 4, iclass 5, count 0 2006.173.13:35:03.92#ibcon#about to read 5, iclass 5, count 0 2006.173.13:35:03.92#ibcon#read 5, iclass 5, count 0 2006.173.13:35:03.92#ibcon#about to read 6, iclass 5, count 0 2006.173.13:35:03.92#ibcon#read 6, iclass 5, count 0 2006.173.13:35:03.92#ibcon#end of sib2, iclass 5, count 0 2006.173.13:35:03.92#ibcon#*mode == 0, iclass 5, count 0 2006.173.13:35:03.92#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.13:35:03.92#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.13:35:03.92#ibcon#*before write, iclass 5, count 0 2006.173.13:35:03.92#ibcon#enter sib2, iclass 5, count 0 2006.173.13:35:03.92#ibcon#flushed, iclass 5, count 0 2006.173.13:35:03.92#ibcon#about to write, iclass 5, count 0 2006.173.13:35:03.92#ibcon#wrote, iclass 5, count 0 2006.173.13:35:03.92#ibcon#about to read 3, iclass 5, count 0 2006.173.13:35:03.96#ibcon#read 3, iclass 5, count 0 2006.173.13:35:03.96#ibcon#about to read 4, iclass 5, count 0 2006.173.13:35:03.96#ibcon#read 4, iclass 5, count 0 2006.173.13:35:03.96#ibcon#about to read 5, iclass 5, count 0 2006.173.13:35:03.96#ibcon#read 5, iclass 5, count 0 2006.173.13:35:03.96#ibcon#about to read 6, iclass 5, count 0 2006.173.13:35:03.96#ibcon#read 6, iclass 5, count 0 2006.173.13:35:03.96#ibcon#end of sib2, iclass 5, count 0 2006.173.13:35:03.96#ibcon#*after write, iclass 5, count 0 2006.173.13:35:03.96#ibcon#*before return 0, iclass 5, count 0 2006.173.13:35:03.96#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.13:35:03.96#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.13:35:03.96#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.13:35:03.96#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.13:35:03.96$vck44/vb=7,4 2006.173.13:35:03.96#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.173.13:35:03.96#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.173.13:35:03.96#ibcon#ireg 11 cls_cnt 2 2006.173.13:35:03.96#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.13:35:04.02#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.13:35:04.02#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.13:35:04.02#ibcon#enter wrdev, iclass 7, count 2 2006.173.13:35:04.02#ibcon#first serial, iclass 7, count 2 2006.173.13:35:04.02#ibcon#enter sib2, iclass 7, count 2 2006.173.13:35:04.02#ibcon#flushed, iclass 7, count 2 2006.173.13:35:04.02#ibcon#about to write, iclass 7, count 2 2006.173.13:35:04.02#ibcon#wrote, iclass 7, count 2 2006.173.13:35:04.02#ibcon#about to read 3, iclass 7, count 2 2006.173.13:35:04.04#ibcon#read 3, iclass 7, count 2 2006.173.13:35:04.04#ibcon#about to read 4, iclass 7, count 2 2006.173.13:35:04.04#ibcon#read 4, iclass 7, count 2 2006.173.13:35:04.04#ibcon#about to read 5, iclass 7, count 2 2006.173.13:35:04.04#ibcon#read 5, iclass 7, count 2 2006.173.13:35:04.04#ibcon#about to read 6, iclass 7, count 2 2006.173.13:35:04.04#ibcon#read 6, iclass 7, count 2 2006.173.13:35:04.04#ibcon#end of sib2, iclass 7, count 2 2006.173.13:35:04.04#ibcon#*mode == 0, iclass 7, count 2 2006.173.13:35:04.04#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.173.13:35:04.04#ibcon#[27=AT07-04\r\n] 2006.173.13:35:04.04#ibcon#*before write, iclass 7, count 2 2006.173.13:35:04.04#ibcon#enter sib2, iclass 7, count 2 2006.173.13:35:04.04#ibcon#flushed, iclass 7, count 2 2006.173.13:35:04.04#ibcon#about to write, iclass 7, count 2 2006.173.13:35:04.04#ibcon#wrote, iclass 7, count 2 2006.173.13:35:04.04#ibcon#about to read 3, iclass 7, count 2 2006.173.13:35:04.07#ibcon#read 3, iclass 7, count 2 2006.173.13:35:04.07#ibcon#about to read 4, iclass 7, count 2 2006.173.13:35:04.07#ibcon#read 4, iclass 7, count 2 2006.173.13:35:04.07#ibcon#about to read 5, iclass 7, count 2 2006.173.13:35:04.07#ibcon#read 5, iclass 7, count 2 2006.173.13:35:04.07#ibcon#about to read 6, iclass 7, count 2 2006.173.13:35:04.07#ibcon#read 6, iclass 7, count 2 2006.173.13:35:04.07#ibcon#end of sib2, iclass 7, count 2 2006.173.13:35:04.07#ibcon#*after write, iclass 7, count 2 2006.173.13:35:04.07#ibcon#*before return 0, iclass 7, count 2 2006.173.13:35:04.07#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.13:35:04.07#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.173.13:35:04.07#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.173.13:35:04.07#ibcon#ireg 7 cls_cnt 0 2006.173.13:35:04.07#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.13:35:04.19#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.13:35:04.19#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.13:35:04.19#ibcon#enter wrdev, iclass 7, count 0 2006.173.13:35:04.19#ibcon#first serial, iclass 7, count 0 2006.173.13:35:04.19#ibcon#enter sib2, iclass 7, count 0 2006.173.13:35:04.19#ibcon#flushed, iclass 7, count 0 2006.173.13:35:04.19#ibcon#about to write, iclass 7, count 0 2006.173.13:35:04.19#ibcon#wrote, iclass 7, count 0 2006.173.13:35:04.19#ibcon#about to read 3, iclass 7, count 0 2006.173.13:35:04.21#ibcon#read 3, iclass 7, count 0 2006.173.13:35:04.21#ibcon#about to read 4, iclass 7, count 0 2006.173.13:35:04.21#ibcon#read 4, iclass 7, count 0 2006.173.13:35:04.21#ibcon#about to read 5, iclass 7, count 0 2006.173.13:35:04.21#ibcon#read 5, iclass 7, count 0 2006.173.13:35:04.21#ibcon#about to read 6, iclass 7, count 0 2006.173.13:35:04.21#ibcon#read 6, iclass 7, count 0 2006.173.13:35:04.21#ibcon#end of sib2, iclass 7, count 0 2006.173.13:35:04.21#ibcon#*mode == 0, iclass 7, count 0 2006.173.13:35:04.21#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.13:35:04.21#ibcon#[27=USB\r\n] 2006.173.13:35:04.21#ibcon#*before write, iclass 7, count 0 2006.173.13:35:04.21#ibcon#enter sib2, iclass 7, count 0 2006.173.13:35:04.21#ibcon#flushed, iclass 7, count 0 2006.173.13:35:04.21#ibcon#about to write, iclass 7, count 0 2006.173.13:35:04.21#ibcon#wrote, iclass 7, count 0 2006.173.13:35:04.21#ibcon#about to read 3, iclass 7, count 0 2006.173.13:35:04.24#ibcon#read 3, iclass 7, count 0 2006.173.13:35:04.24#ibcon#about to read 4, iclass 7, count 0 2006.173.13:35:04.24#ibcon#read 4, iclass 7, count 0 2006.173.13:35:04.24#ibcon#about to read 5, iclass 7, count 0 2006.173.13:35:04.24#ibcon#read 5, iclass 7, count 0 2006.173.13:35:04.24#ibcon#about to read 6, iclass 7, count 0 2006.173.13:35:04.24#ibcon#read 6, iclass 7, count 0 2006.173.13:35:04.24#ibcon#end of sib2, iclass 7, count 0 2006.173.13:35:04.24#ibcon#*after write, iclass 7, count 0 2006.173.13:35:04.24#ibcon#*before return 0, iclass 7, count 0 2006.173.13:35:04.24#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.13:35:04.24#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.173.13:35:04.24#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.13:35:04.24#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.13:35:04.24$vck44/vblo=8,744.99 2006.173.13:35:04.24#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.13:35:04.24#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.13:35:04.24#ibcon#ireg 17 cls_cnt 0 2006.173.13:35:04.24#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.13:35:04.24#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.13:35:04.24#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.13:35:04.24#ibcon#enter wrdev, iclass 11, count 0 2006.173.13:35:04.24#ibcon#first serial, iclass 11, count 0 2006.173.13:35:04.24#ibcon#enter sib2, iclass 11, count 0 2006.173.13:35:04.24#ibcon#flushed, iclass 11, count 0 2006.173.13:35:04.24#ibcon#about to write, iclass 11, count 0 2006.173.13:35:04.24#ibcon#wrote, iclass 11, count 0 2006.173.13:35:04.24#ibcon#about to read 3, iclass 11, count 0 2006.173.13:35:04.26#ibcon#read 3, iclass 11, count 0 2006.173.13:35:04.26#ibcon#about to read 4, iclass 11, count 0 2006.173.13:35:04.26#ibcon#read 4, iclass 11, count 0 2006.173.13:35:04.26#ibcon#about to read 5, iclass 11, count 0 2006.173.13:35:04.26#ibcon#read 5, iclass 11, count 0 2006.173.13:35:04.26#ibcon#about to read 6, iclass 11, count 0 2006.173.13:35:04.26#ibcon#read 6, iclass 11, count 0 2006.173.13:35:04.26#ibcon#end of sib2, iclass 11, count 0 2006.173.13:35:04.26#ibcon#*mode == 0, iclass 11, count 0 2006.173.13:35:04.26#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.13:35:04.26#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.13:35:04.26#ibcon#*before write, iclass 11, count 0 2006.173.13:35:04.26#ibcon#enter sib2, iclass 11, count 0 2006.173.13:35:04.26#ibcon#flushed, iclass 11, count 0 2006.173.13:35:04.26#ibcon#about to write, iclass 11, count 0 2006.173.13:35:04.26#ibcon#wrote, iclass 11, count 0 2006.173.13:35:04.26#ibcon#about to read 3, iclass 11, count 0 2006.173.13:35:04.30#ibcon#read 3, iclass 11, count 0 2006.173.13:35:04.30#ibcon#about to read 4, iclass 11, count 0 2006.173.13:35:04.30#ibcon#read 4, iclass 11, count 0 2006.173.13:35:04.30#ibcon#about to read 5, iclass 11, count 0 2006.173.13:35:04.30#ibcon#read 5, iclass 11, count 0 2006.173.13:35:04.30#ibcon#about to read 6, iclass 11, count 0 2006.173.13:35:04.30#ibcon#read 6, iclass 11, count 0 2006.173.13:35:04.30#ibcon#end of sib2, iclass 11, count 0 2006.173.13:35:04.30#ibcon#*after write, iclass 11, count 0 2006.173.13:35:04.30#ibcon#*before return 0, iclass 11, count 0 2006.173.13:35:04.30#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.13:35:04.30#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.13:35:04.30#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.13:35:04.30#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.13:35:04.30$vck44/vb=8,4 2006.173.13:35:04.30#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.173.13:35:04.30#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.173.13:35:04.30#ibcon#ireg 11 cls_cnt 2 2006.173.13:35:04.30#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.13:35:04.36#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.13:35:04.36#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.13:35:04.36#ibcon#enter wrdev, iclass 13, count 2 2006.173.13:35:04.36#ibcon#first serial, iclass 13, count 2 2006.173.13:35:04.36#ibcon#enter sib2, iclass 13, count 2 2006.173.13:35:04.36#ibcon#flushed, iclass 13, count 2 2006.173.13:35:04.36#ibcon#about to write, iclass 13, count 2 2006.173.13:35:04.36#ibcon#wrote, iclass 13, count 2 2006.173.13:35:04.36#ibcon#about to read 3, iclass 13, count 2 2006.173.13:35:04.38#ibcon#read 3, iclass 13, count 2 2006.173.13:35:04.38#ibcon#about to read 4, iclass 13, count 2 2006.173.13:35:04.38#ibcon#read 4, iclass 13, count 2 2006.173.13:35:04.38#ibcon#about to read 5, iclass 13, count 2 2006.173.13:35:04.38#ibcon#read 5, iclass 13, count 2 2006.173.13:35:04.38#ibcon#about to read 6, iclass 13, count 2 2006.173.13:35:04.38#ibcon#read 6, iclass 13, count 2 2006.173.13:35:04.38#ibcon#end of sib2, iclass 13, count 2 2006.173.13:35:04.38#ibcon#*mode == 0, iclass 13, count 2 2006.173.13:35:04.38#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.173.13:35:04.38#ibcon#[27=AT08-04\r\n] 2006.173.13:35:04.38#ibcon#*before write, iclass 13, count 2 2006.173.13:35:04.38#ibcon#enter sib2, iclass 13, count 2 2006.173.13:35:04.38#ibcon#flushed, iclass 13, count 2 2006.173.13:35:04.38#ibcon#about to write, iclass 13, count 2 2006.173.13:35:04.38#ibcon#wrote, iclass 13, count 2 2006.173.13:35:04.38#ibcon#about to read 3, iclass 13, count 2 2006.173.13:35:04.41#ibcon#read 3, iclass 13, count 2 2006.173.13:35:04.41#ibcon#about to read 4, iclass 13, count 2 2006.173.13:35:04.41#ibcon#read 4, iclass 13, count 2 2006.173.13:35:04.41#ibcon#about to read 5, iclass 13, count 2 2006.173.13:35:04.41#ibcon#read 5, iclass 13, count 2 2006.173.13:35:04.41#ibcon#about to read 6, iclass 13, count 2 2006.173.13:35:04.41#ibcon#read 6, iclass 13, count 2 2006.173.13:35:04.41#ibcon#end of sib2, iclass 13, count 2 2006.173.13:35:04.41#ibcon#*after write, iclass 13, count 2 2006.173.13:35:04.41#ibcon#*before return 0, iclass 13, count 2 2006.173.13:35:04.41#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.13:35:04.41#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.173.13:35:04.41#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.173.13:35:04.41#ibcon#ireg 7 cls_cnt 0 2006.173.13:35:04.41#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.13:35:04.53#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.13:35:04.53#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.13:35:04.53#ibcon#enter wrdev, iclass 13, count 0 2006.173.13:35:04.53#ibcon#first serial, iclass 13, count 0 2006.173.13:35:04.53#ibcon#enter sib2, iclass 13, count 0 2006.173.13:35:04.53#ibcon#flushed, iclass 13, count 0 2006.173.13:35:04.53#ibcon#about to write, iclass 13, count 0 2006.173.13:35:04.53#ibcon#wrote, iclass 13, count 0 2006.173.13:35:04.53#ibcon#about to read 3, iclass 13, count 0 2006.173.13:35:04.55#ibcon#read 3, iclass 13, count 0 2006.173.13:35:04.55#ibcon#about to read 4, iclass 13, count 0 2006.173.13:35:04.55#ibcon#read 4, iclass 13, count 0 2006.173.13:35:04.55#ibcon#about to read 5, iclass 13, count 0 2006.173.13:35:04.55#ibcon#read 5, iclass 13, count 0 2006.173.13:35:04.55#ibcon#about to read 6, iclass 13, count 0 2006.173.13:35:04.55#ibcon#read 6, iclass 13, count 0 2006.173.13:35:04.55#ibcon#end of sib2, iclass 13, count 0 2006.173.13:35:04.55#ibcon#*mode == 0, iclass 13, count 0 2006.173.13:35:04.55#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.13:35:04.55#ibcon#[27=USB\r\n] 2006.173.13:35:04.55#ibcon#*before write, iclass 13, count 0 2006.173.13:35:04.55#ibcon#enter sib2, iclass 13, count 0 2006.173.13:35:04.55#ibcon#flushed, iclass 13, count 0 2006.173.13:35:04.55#ibcon#about to write, iclass 13, count 0 2006.173.13:35:04.55#ibcon#wrote, iclass 13, count 0 2006.173.13:35:04.55#ibcon#about to read 3, iclass 13, count 0 2006.173.13:35:04.58#ibcon#read 3, iclass 13, count 0 2006.173.13:35:04.58#ibcon#about to read 4, iclass 13, count 0 2006.173.13:35:04.58#ibcon#read 4, iclass 13, count 0 2006.173.13:35:04.58#ibcon#about to read 5, iclass 13, count 0 2006.173.13:35:04.58#ibcon#read 5, iclass 13, count 0 2006.173.13:35:04.58#ibcon#about to read 6, iclass 13, count 0 2006.173.13:35:04.58#ibcon#read 6, iclass 13, count 0 2006.173.13:35:04.58#ibcon#end of sib2, iclass 13, count 0 2006.173.13:35:04.58#ibcon#*after write, iclass 13, count 0 2006.173.13:35:04.58#ibcon#*before return 0, iclass 13, count 0 2006.173.13:35:04.58#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.13:35:04.58#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.173.13:35:04.58#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.13:35:04.58#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.13:35:04.58$vck44/vabw=wide 2006.173.13:35:04.58#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.13:35:04.58#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.13:35:04.58#ibcon#ireg 8 cls_cnt 0 2006.173.13:35:04.58#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.13:35:04.58#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.13:35:04.58#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.13:35:04.58#ibcon#enter wrdev, iclass 15, count 0 2006.173.13:35:04.58#ibcon#first serial, iclass 15, count 0 2006.173.13:35:04.58#ibcon#enter sib2, iclass 15, count 0 2006.173.13:35:04.58#ibcon#flushed, iclass 15, count 0 2006.173.13:35:04.58#ibcon#about to write, iclass 15, count 0 2006.173.13:35:04.58#ibcon#wrote, iclass 15, count 0 2006.173.13:35:04.58#ibcon#about to read 3, iclass 15, count 0 2006.173.13:35:04.60#ibcon#read 3, iclass 15, count 0 2006.173.13:35:04.60#ibcon#about to read 4, iclass 15, count 0 2006.173.13:35:04.60#ibcon#read 4, iclass 15, count 0 2006.173.13:35:04.60#ibcon#about to read 5, iclass 15, count 0 2006.173.13:35:04.60#ibcon#read 5, iclass 15, count 0 2006.173.13:35:04.60#ibcon#about to read 6, iclass 15, count 0 2006.173.13:35:04.60#ibcon#read 6, iclass 15, count 0 2006.173.13:35:04.60#ibcon#end of sib2, iclass 15, count 0 2006.173.13:35:04.60#ibcon#*mode == 0, iclass 15, count 0 2006.173.13:35:04.60#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.13:35:04.60#ibcon#[25=BW32\r\n] 2006.173.13:35:04.60#ibcon#*before write, iclass 15, count 0 2006.173.13:35:04.60#ibcon#enter sib2, iclass 15, count 0 2006.173.13:35:04.60#ibcon#flushed, iclass 15, count 0 2006.173.13:35:04.60#ibcon#about to write, iclass 15, count 0 2006.173.13:35:04.60#ibcon#wrote, iclass 15, count 0 2006.173.13:35:04.60#ibcon#about to read 3, iclass 15, count 0 2006.173.13:35:04.63#ibcon#read 3, iclass 15, count 0 2006.173.13:35:04.63#ibcon#about to read 4, iclass 15, count 0 2006.173.13:35:04.63#ibcon#read 4, iclass 15, count 0 2006.173.13:35:04.63#ibcon#about to read 5, iclass 15, count 0 2006.173.13:35:04.63#ibcon#read 5, iclass 15, count 0 2006.173.13:35:04.63#ibcon#about to read 6, iclass 15, count 0 2006.173.13:35:04.63#ibcon#read 6, iclass 15, count 0 2006.173.13:35:04.63#ibcon#end of sib2, iclass 15, count 0 2006.173.13:35:04.63#ibcon#*after write, iclass 15, count 0 2006.173.13:35:04.63#ibcon#*before return 0, iclass 15, count 0 2006.173.13:35:04.63#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.13:35:04.63#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.13:35:04.63#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.13:35:04.63#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.13:35:04.63$vck44/vbbw=wide 2006.173.13:35:04.63#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.13:35:04.63#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.13:35:04.63#ibcon#ireg 8 cls_cnt 0 2006.173.13:35:04.63#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.13:35:04.70#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.13:35:04.70#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.13:35:04.70#ibcon#enter wrdev, iclass 17, count 0 2006.173.13:35:04.70#ibcon#first serial, iclass 17, count 0 2006.173.13:35:04.70#ibcon#enter sib2, iclass 17, count 0 2006.173.13:35:04.70#ibcon#flushed, iclass 17, count 0 2006.173.13:35:04.70#ibcon#about to write, iclass 17, count 0 2006.173.13:35:04.70#ibcon#wrote, iclass 17, count 0 2006.173.13:35:04.70#ibcon#about to read 3, iclass 17, count 0 2006.173.13:35:04.72#ibcon#read 3, iclass 17, count 0 2006.173.13:35:04.72#ibcon#about to read 4, iclass 17, count 0 2006.173.13:35:04.72#ibcon#read 4, iclass 17, count 0 2006.173.13:35:04.72#ibcon#about to read 5, iclass 17, count 0 2006.173.13:35:04.72#ibcon#read 5, iclass 17, count 0 2006.173.13:35:04.72#ibcon#about to read 6, iclass 17, count 0 2006.173.13:35:04.72#ibcon#read 6, iclass 17, count 0 2006.173.13:35:04.72#ibcon#end of sib2, iclass 17, count 0 2006.173.13:35:04.72#ibcon#*mode == 0, iclass 17, count 0 2006.173.13:35:04.72#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.13:35:04.72#ibcon#[27=BW32\r\n] 2006.173.13:35:04.72#ibcon#*before write, iclass 17, count 0 2006.173.13:35:04.72#ibcon#enter sib2, iclass 17, count 0 2006.173.13:35:04.72#ibcon#flushed, iclass 17, count 0 2006.173.13:35:04.72#ibcon#about to write, iclass 17, count 0 2006.173.13:35:04.72#ibcon#wrote, iclass 17, count 0 2006.173.13:35:04.72#ibcon#about to read 3, iclass 17, count 0 2006.173.13:35:04.75#ibcon#read 3, iclass 17, count 0 2006.173.13:35:04.75#ibcon#about to read 4, iclass 17, count 0 2006.173.13:35:04.75#ibcon#read 4, iclass 17, count 0 2006.173.13:35:04.75#ibcon#about to read 5, iclass 17, count 0 2006.173.13:35:04.75#ibcon#read 5, iclass 17, count 0 2006.173.13:35:04.75#ibcon#about to read 6, iclass 17, count 0 2006.173.13:35:04.75#ibcon#read 6, iclass 17, count 0 2006.173.13:35:04.75#ibcon#end of sib2, iclass 17, count 0 2006.173.13:35:04.75#ibcon#*after write, iclass 17, count 0 2006.173.13:35:04.75#ibcon#*before return 0, iclass 17, count 0 2006.173.13:35:04.75#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.13:35:04.75#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.13:35:04.75#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.13:35:04.75#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.13:35:04.75$setupk4/ifdk4 2006.173.13:35:04.75$ifdk4/lo= 2006.173.13:35:04.75$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.13:35:04.76$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.13:35:04.76$ifdk4/patch= 2006.173.13:35:04.76$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.13:35:04.76$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.13:35:04.76$setupk4/!*+20s 2006.173.13:35:10.14#trakl#Source acquired 2006.173.13:35:10.14#flagr#flagr/antenna,acquired 2006.173.13:35:13.93#abcon#<5=/04 0.6 1.3 21.961001003.8\r\n> 2006.173.13:35:13.95#abcon#{5=INTERFACE CLEAR} 2006.173.13:35:14.01#abcon#[5=S1D000X0/0*\r\n] 2006.173.13:35:19.27$setupk4/"tpicd 2006.173.13:35:19.27$setupk4/echo=off 2006.173.13:35:19.27$setupk4/xlog=off 2006.173.13:35:19.27:!2006.173.13:35:15 2006.173.13:35:19.27:preob 2006.173.13:35:20.14/onsource/TRACKING 2006.173.13:35:20.14:!2006.173.13:35:25 2006.173.13:35:25.00:"tape 2006.173.13:35:25.00:"st=record 2006.173.13:35:25.00:data_valid=on 2006.173.13:35:25.00:midob 2006.173.13:35:25.14/onsource/TRACKING 2006.173.13:35:25.15/wx/21.96,1003.8,100 2006.173.13:35:25.25/cable/+6.5031E-03 2006.173.13:35:26.34/va/01,07,usb,yes,51,55 2006.173.13:35:26.34/va/02,06,usb,yes,51,52 2006.173.13:35:26.34/va/03,05,usb,yes,64,67 2006.173.13:35:26.34/va/04,06,usb,yes,52,55 2006.173.13:35:26.34/va/05,04,usb,yes,42,43 2006.173.13:35:26.34/va/06,03,usb,yes,58,58 2006.173.13:35:26.34/va/07,04,usb,yes,48,49 2006.173.13:35:26.34/va/08,04,usb,yes,41,48 2006.173.13:35:26.57/valo/01,524.99,yes,locked 2006.173.13:35:26.57/valo/02,534.99,yes,locked 2006.173.13:35:26.57/valo/03,564.99,yes,locked 2006.173.13:35:26.57/valo/04,624.99,yes,locked 2006.173.13:35:26.57/valo/05,734.99,yes,locked 2006.173.13:35:26.57/valo/06,814.99,yes,locked 2006.173.13:35:26.57/valo/07,864.99,yes,locked 2006.173.13:35:26.57/valo/08,884.99,yes,locked 2006.173.13:35:27.66/vb/01,04,usb,yes,30,28 2006.173.13:35:27.66/vb/02,04,usb,yes,33,33 2006.173.13:35:27.66/vb/03,04,usb,yes,30,33 2006.173.13:35:27.66/vb/04,04,usb,yes,34,33 2006.173.13:35:27.66/vb/05,04,usb,yes,27,29 2006.173.13:35:27.66/vb/06,04,usb,yes,31,27 2006.173.13:35:27.66/vb/07,04,usb,yes,31,31 2006.173.13:35:27.66/vb/08,04,usb,yes,29,32 2006.173.13:35:27.89/vblo/01,629.99,yes,locked 2006.173.13:35:27.89/vblo/02,634.99,yes,locked 2006.173.13:35:27.89/vblo/03,649.99,yes,locked 2006.173.13:35:27.89/vblo/04,679.99,yes,locked 2006.173.13:35:27.89/vblo/05,709.99,yes,locked 2006.173.13:35:27.89/vblo/06,719.99,yes,locked 2006.173.13:35:27.89/vblo/07,734.99,yes,locked 2006.173.13:35:27.89/vblo/08,744.99,yes,locked 2006.173.13:35:28.04/vabw/8 2006.173.13:35:28.19/vbbw/8 2006.173.13:35:28.28/xfe/off,on,15.2 2006.173.13:35:28.66/ifatt/23,28,28,28 2006.173.13:35:29.07/fmout-gps/S +3.83E-07 2006.173.13:35:29.12:!2006.173.13:37:55 2006.173.13:37:55.01:data_valid=off 2006.173.13:37:55.01:"et 2006.173.13:37:55.01:!+3s 2006.173.13:37:58.02:"tape 2006.173.13:37:58.02:postob 2006.173.13:37:58.19/cable/+6.5034E-03 2006.173.13:37:58.19/wx/21.96,1003.9,100 2006.173.13:37:58.25/fmout-gps/S +3.84E-07 2006.173.13:37:58.25:scan_name=173-1338,jd0606,784 2006.173.13:37:58.25:source=0133+476,013658.59,475129.1,2000.0,cw 2006.173.13:38:00.13#flagr#flagr/antenna,new-source 2006.173.13:38:00.13:checkk5 2006.173.13:38:00.50/chk_autoobs//k5ts1/ autoobs is running! 2006.173.13:38:00.90/chk_autoobs//k5ts2/ autoobs is running! 2006.173.13:38:01.32/chk_autoobs//k5ts3/ autoobs is running! 2006.173.13:38:01.72/chk_autoobs//k5ts4/ autoobs is running! 2006.173.13:38:02.10/chk_obsdata//k5ts1/T1731335??a.dat file size is correct (nominal:600MB, actual:596MB). 2006.173.13:38:02.50/chk_obsdata//k5ts2/T1731335??b.dat file size is correct (nominal:600MB, actual:596MB). 2006.173.13:38:02.89/chk_obsdata//k5ts3/T1731335??c.dat file size is correct (nominal:600MB, actual:596MB). 2006.173.13:38:03.29/chk_obsdata//k5ts4/T1731335??d.dat file size is correct (nominal:600MB, actual:596MB). 2006.173.13:38:04.01/k5log//k5ts1_log_newline 2006.173.13:38:04.73/k5log//k5ts2_log_newline 2006.173.13:38:05.43/k5log//k5ts3_log_newline 2006.173.13:38:06.14/k5log//k5ts4_log_newline 2006.173.13:38:06.16/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.13:38:06.16:setupk4=1 2006.173.13:38:06.16$setupk4/echo=on 2006.173.13:38:06.16$setupk4/pcalon 2006.173.13:38:06.16$pcalon/"no phase cal control is implemented here 2006.173.13:38:06.16$setupk4/"tpicd=stop 2006.173.13:38:06.16$setupk4/"rec=synch_on 2006.173.13:38:06.16$setupk4/"rec_mode=128 2006.173.13:38:06.16$setupk4/!* 2006.173.13:38:06.16$setupk4/recpk4 2006.173.13:38:06.16$recpk4/recpatch= 2006.173.13:38:06.17$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.13:38:06.17$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.13:38:06.17$setupk4/vck44 2006.173.13:38:06.17$vck44/valo=1,524.99 2006.173.13:38:06.17#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.13:38:06.17#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.13:38:06.17#ibcon#ireg 17 cls_cnt 0 2006.173.13:38:06.17#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.13:38:06.17#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.13:38:06.17#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.13:38:06.17#ibcon#enter wrdev, iclass 18, count 0 2006.173.13:38:06.17#ibcon#first serial, iclass 18, count 0 2006.173.13:38:06.17#ibcon#enter sib2, iclass 18, count 0 2006.173.13:38:06.17#ibcon#flushed, iclass 18, count 0 2006.173.13:38:06.17#ibcon#about to write, iclass 18, count 0 2006.173.13:38:06.17#ibcon#wrote, iclass 18, count 0 2006.173.13:38:06.17#ibcon#about to read 3, iclass 18, count 0 2006.173.13:38:06.18#ibcon#read 3, iclass 18, count 0 2006.173.13:38:06.18#ibcon#about to read 4, iclass 18, count 0 2006.173.13:38:06.18#ibcon#read 4, iclass 18, count 0 2006.173.13:38:06.18#ibcon#about to read 5, iclass 18, count 0 2006.173.13:38:06.18#ibcon#read 5, iclass 18, count 0 2006.173.13:38:06.18#ibcon#about to read 6, iclass 18, count 0 2006.173.13:38:06.18#ibcon#read 6, iclass 18, count 0 2006.173.13:38:06.18#ibcon#end of sib2, iclass 18, count 0 2006.173.13:38:06.18#ibcon#*mode == 0, iclass 18, count 0 2006.173.13:38:06.18#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.13:38:06.18#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.13:38:06.18#ibcon#*before write, iclass 18, count 0 2006.173.13:38:06.18#ibcon#enter sib2, iclass 18, count 0 2006.173.13:38:06.18#ibcon#flushed, iclass 18, count 0 2006.173.13:38:06.18#ibcon#about to write, iclass 18, count 0 2006.173.13:38:06.18#ibcon#wrote, iclass 18, count 0 2006.173.13:38:06.18#ibcon#about to read 3, iclass 18, count 0 2006.173.13:38:06.23#ibcon#read 3, iclass 18, count 0 2006.173.13:38:06.23#ibcon#about to read 4, iclass 18, count 0 2006.173.13:38:06.23#ibcon#read 4, iclass 18, count 0 2006.173.13:38:06.23#ibcon#about to read 5, iclass 18, count 0 2006.173.13:38:06.23#ibcon#read 5, iclass 18, count 0 2006.173.13:38:06.23#ibcon#about to read 6, iclass 18, count 0 2006.173.13:38:06.23#ibcon#read 6, iclass 18, count 0 2006.173.13:38:06.23#ibcon#end of sib2, iclass 18, count 0 2006.173.13:38:06.23#ibcon#*after write, iclass 18, count 0 2006.173.13:38:06.23#ibcon#*before return 0, iclass 18, count 0 2006.173.13:38:06.23#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.13:38:06.23#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.13:38:06.23#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.13:38:06.23#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.13:38:06.23$vck44/va=1,7 2006.173.13:38:06.23#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.13:38:06.23#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.13:38:06.23#ibcon#ireg 11 cls_cnt 2 2006.173.13:38:06.23#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.13:38:06.23#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.13:38:06.23#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.13:38:06.23#ibcon#enter wrdev, iclass 20, count 2 2006.173.13:38:06.23#ibcon#first serial, iclass 20, count 2 2006.173.13:38:06.23#ibcon#enter sib2, iclass 20, count 2 2006.173.13:38:06.23#ibcon#flushed, iclass 20, count 2 2006.173.13:38:06.23#ibcon#about to write, iclass 20, count 2 2006.173.13:38:06.23#ibcon#wrote, iclass 20, count 2 2006.173.13:38:06.23#ibcon#about to read 3, iclass 20, count 2 2006.173.13:38:06.25#ibcon#read 3, iclass 20, count 2 2006.173.13:38:06.25#ibcon#about to read 4, iclass 20, count 2 2006.173.13:38:06.25#ibcon#read 4, iclass 20, count 2 2006.173.13:38:06.25#ibcon#about to read 5, iclass 20, count 2 2006.173.13:38:06.25#ibcon#read 5, iclass 20, count 2 2006.173.13:38:06.25#ibcon#about to read 6, iclass 20, count 2 2006.173.13:38:06.25#ibcon#read 6, iclass 20, count 2 2006.173.13:38:06.25#ibcon#end of sib2, iclass 20, count 2 2006.173.13:38:06.25#ibcon#*mode == 0, iclass 20, count 2 2006.173.13:38:06.25#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.13:38:06.25#ibcon#[25=AT01-07\r\n] 2006.173.13:38:06.25#ibcon#*before write, iclass 20, count 2 2006.173.13:38:06.25#ibcon#enter sib2, iclass 20, count 2 2006.173.13:38:06.25#ibcon#flushed, iclass 20, count 2 2006.173.13:38:06.25#ibcon#about to write, iclass 20, count 2 2006.173.13:38:06.25#ibcon#wrote, iclass 20, count 2 2006.173.13:38:06.25#ibcon#about to read 3, iclass 20, count 2 2006.173.13:38:06.28#ibcon#read 3, iclass 20, count 2 2006.173.13:38:06.28#ibcon#about to read 4, iclass 20, count 2 2006.173.13:38:06.28#ibcon#read 4, iclass 20, count 2 2006.173.13:38:06.28#ibcon#about to read 5, iclass 20, count 2 2006.173.13:38:06.28#ibcon#read 5, iclass 20, count 2 2006.173.13:38:06.28#ibcon#about to read 6, iclass 20, count 2 2006.173.13:38:06.28#ibcon#read 6, iclass 20, count 2 2006.173.13:38:06.28#ibcon#end of sib2, iclass 20, count 2 2006.173.13:38:06.28#ibcon#*after write, iclass 20, count 2 2006.173.13:38:06.28#ibcon#*before return 0, iclass 20, count 2 2006.173.13:38:06.28#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.13:38:06.28#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.13:38:06.28#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.13:38:06.28#ibcon#ireg 7 cls_cnt 0 2006.173.13:38:06.28#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.13:38:06.40#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.13:38:06.40#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.13:38:06.40#ibcon#enter wrdev, iclass 20, count 0 2006.173.13:38:06.40#ibcon#first serial, iclass 20, count 0 2006.173.13:38:06.40#ibcon#enter sib2, iclass 20, count 0 2006.173.13:38:06.40#ibcon#flushed, iclass 20, count 0 2006.173.13:38:06.40#ibcon#about to write, iclass 20, count 0 2006.173.13:38:06.40#ibcon#wrote, iclass 20, count 0 2006.173.13:38:06.40#ibcon#about to read 3, iclass 20, count 0 2006.173.13:38:06.42#ibcon#read 3, iclass 20, count 0 2006.173.13:38:06.42#ibcon#about to read 4, iclass 20, count 0 2006.173.13:38:06.42#ibcon#read 4, iclass 20, count 0 2006.173.13:38:06.42#ibcon#about to read 5, iclass 20, count 0 2006.173.13:38:06.42#ibcon#read 5, iclass 20, count 0 2006.173.13:38:06.42#ibcon#about to read 6, iclass 20, count 0 2006.173.13:38:06.42#ibcon#read 6, iclass 20, count 0 2006.173.13:38:06.42#ibcon#end of sib2, iclass 20, count 0 2006.173.13:38:06.42#ibcon#*mode == 0, iclass 20, count 0 2006.173.13:38:06.42#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.13:38:06.42#ibcon#[25=USB\r\n] 2006.173.13:38:06.42#ibcon#*before write, iclass 20, count 0 2006.173.13:38:06.42#ibcon#enter sib2, iclass 20, count 0 2006.173.13:38:06.42#ibcon#flushed, iclass 20, count 0 2006.173.13:38:06.42#ibcon#about to write, iclass 20, count 0 2006.173.13:38:06.42#ibcon#wrote, iclass 20, count 0 2006.173.13:38:06.42#ibcon#about to read 3, iclass 20, count 0 2006.173.13:38:06.45#ibcon#read 3, iclass 20, count 0 2006.173.13:38:06.45#ibcon#about to read 4, iclass 20, count 0 2006.173.13:38:06.45#ibcon#read 4, iclass 20, count 0 2006.173.13:38:06.45#ibcon#about to read 5, iclass 20, count 0 2006.173.13:38:06.45#ibcon#read 5, iclass 20, count 0 2006.173.13:38:06.45#ibcon#about to read 6, iclass 20, count 0 2006.173.13:38:06.45#ibcon#read 6, iclass 20, count 0 2006.173.13:38:06.45#ibcon#end of sib2, iclass 20, count 0 2006.173.13:38:06.45#ibcon#*after write, iclass 20, count 0 2006.173.13:38:06.45#ibcon#*before return 0, iclass 20, count 0 2006.173.13:38:06.45#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.13:38:06.45#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.13:38:06.45#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.13:38:06.45#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.13:38:06.45$vck44/valo=2,534.99 2006.173.13:38:06.45#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.13:38:06.45#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.13:38:06.45#ibcon#ireg 17 cls_cnt 0 2006.173.13:38:06.45#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.13:38:06.45#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.13:38:06.45#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.13:38:06.45#ibcon#enter wrdev, iclass 22, count 0 2006.173.13:38:06.45#ibcon#first serial, iclass 22, count 0 2006.173.13:38:06.45#ibcon#enter sib2, iclass 22, count 0 2006.173.13:38:06.45#ibcon#flushed, iclass 22, count 0 2006.173.13:38:06.45#ibcon#about to write, iclass 22, count 0 2006.173.13:38:06.45#ibcon#wrote, iclass 22, count 0 2006.173.13:38:06.45#ibcon#about to read 3, iclass 22, count 0 2006.173.13:38:06.47#ibcon#read 3, iclass 22, count 0 2006.173.13:38:06.47#ibcon#about to read 4, iclass 22, count 0 2006.173.13:38:06.47#ibcon#read 4, iclass 22, count 0 2006.173.13:38:06.47#ibcon#about to read 5, iclass 22, count 0 2006.173.13:38:06.47#ibcon#read 5, iclass 22, count 0 2006.173.13:38:06.47#ibcon#about to read 6, iclass 22, count 0 2006.173.13:38:06.47#ibcon#read 6, iclass 22, count 0 2006.173.13:38:06.47#ibcon#end of sib2, iclass 22, count 0 2006.173.13:38:06.47#ibcon#*mode == 0, iclass 22, count 0 2006.173.13:38:06.47#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.13:38:06.47#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.13:38:06.47#ibcon#*before write, iclass 22, count 0 2006.173.13:38:06.47#ibcon#enter sib2, iclass 22, count 0 2006.173.13:38:06.47#ibcon#flushed, iclass 22, count 0 2006.173.13:38:06.47#ibcon#about to write, iclass 22, count 0 2006.173.13:38:06.47#ibcon#wrote, iclass 22, count 0 2006.173.13:38:06.47#ibcon#about to read 3, iclass 22, count 0 2006.173.13:38:06.51#ibcon#read 3, iclass 22, count 0 2006.173.13:38:06.51#ibcon#about to read 4, iclass 22, count 0 2006.173.13:38:06.51#ibcon#read 4, iclass 22, count 0 2006.173.13:38:06.51#ibcon#about to read 5, iclass 22, count 0 2006.173.13:38:06.51#ibcon#read 5, iclass 22, count 0 2006.173.13:38:06.51#ibcon#about to read 6, iclass 22, count 0 2006.173.13:38:06.51#ibcon#read 6, iclass 22, count 0 2006.173.13:38:06.51#ibcon#end of sib2, iclass 22, count 0 2006.173.13:38:06.51#ibcon#*after write, iclass 22, count 0 2006.173.13:38:06.51#ibcon#*before return 0, iclass 22, count 0 2006.173.13:38:06.51#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.13:38:06.51#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.13:38:06.51#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.13:38:06.51#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.13:38:06.51$vck44/va=2,6 2006.173.13:38:06.51#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.13:38:06.51#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.13:38:06.51#ibcon#ireg 11 cls_cnt 2 2006.173.13:38:06.51#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.13:38:06.57#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.13:38:06.57#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.13:38:06.57#ibcon#enter wrdev, iclass 24, count 2 2006.173.13:38:06.57#ibcon#first serial, iclass 24, count 2 2006.173.13:38:06.57#ibcon#enter sib2, iclass 24, count 2 2006.173.13:38:06.57#ibcon#flushed, iclass 24, count 2 2006.173.13:38:06.57#ibcon#about to write, iclass 24, count 2 2006.173.13:38:06.57#ibcon#wrote, iclass 24, count 2 2006.173.13:38:06.57#ibcon#about to read 3, iclass 24, count 2 2006.173.13:38:06.59#ibcon#read 3, iclass 24, count 2 2006.173.13:38:06.59#ibcon#about to read 4, iclass 24, count 2 2006.173.13:38:06.59#ibcon#read 4, iclass 24, count 2 2006.173.13:38:06.59#ibcon#about to read 5, iclass 24, count 2 2006.173.13:38:06.59#ibcon#read 5, iclass 24, count 2 2006.173.13:38:06.59#ibcon#about to read 6, iclass 24, count 2 2006.173.13:38:06.59#ibcon#read 6, iclass 24, count 2 2006.173.13:38:06.59#ibcon#end of sib2, iclass 24, count 2 2006.173.13:38:06.59#ibcon#*mode == 0, iclass 24, count 2 2006.173.13:38:06.59#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.13:38:06.59#ibcon#[25=AT02-06\r\n] 2006.173.13:38:06.59#ibcon#*before write, iclass 24, count 2 2006.173.13:38:06.59#ibcon#enter sib2, iclass 24, count 2 2006.173.13:38:06.59#ibcon#flushed, iclass 24, count 2 2006.173.13:38:06.59#ibcon#about to write, iclass 24, count 2 2006.173.13:38:06.59#ibcon#wrote, iclass 24, count 2 2006.173.13:38:06.59#ibcon#about to read 3, iclass 24, count 2 2006.173.13:38:06.62#ibcon#read 3, iclass 24, count 2 2006.173.13:38:06.62#ibcon#about to read 4, iclass 24, count 2 2006.173.13:38:06.62#ibcon#read 4, iclass 24, count 2 2006.173.13:38:06.62#ibcon#about to read 5, iclass 24, count 2 2006.173.13:38:06.62#ibcon#read 5, iclass 24, count 2 2006.173.13:38:06.62#ibcon#about to read 6, iclass 24, count 2 2006.173.13:38:06.62#ibcon#read 6, iclass 24, count 2 2006.173.13:38:06.62#ibcon#end of sib2, iclass 24, count 2 2006.173.13:38:06.62#ibcon#*after write, iclass 24, count 2 2006.173.13:38:06.62#ibcon#*before return 0, iclass 24, count 2 2006.173.13:38:06.62#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.13:38:06.62#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.13:38:06.62#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.13:38:06.62#ibcon#ireg 7 cls_cnt 0 2006.173.13:38:06.62#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.13:38:06.74#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.13:38:06.74#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.13:38:06.74#ibcon#enter wrdev, iclass 24, count 0 2006.173.13:38:06.74#ibcon#first serial, iclass 24, count 0 2006.173.13:38:06.74#ibcon#enter sib2, iclass 24, count 0 2006.173.13:38:06.74#ibcon#flushed, iclass 24, count 0 2006.173.13:38:06.74#ibcon#about to write, iclass 24, count 0 2006.173.13:38:06.74#ibcon#wrote, iclass 24, count 0 2006.173.13:38:06.74#ibcon#about to read 3, iclass 24, count 0 2006.173.13:38:06.76#ibcon#read 3, iclass 24, count 0 2006.173.13:38:06.76#ibcon#about to read 4, iclass 24, count 0 2006.173.13:38:06.76#ibcon#read 4, iclass 24, count 0 2006.173.13:38:06.76#ibcon#about to read 5, iclass 24, count 0 2006.173.13:38:06.76#ibcon#read 5, iclass 24, count 0 2006.173.13:38:06.76#ibcon#about to read 6, iclass 24, count 0 2006.173.13:38:06.76#ibcon#read 6, iclass 24, count 0 2006.173.13:38:06.76#ibcon#end of sib2, iclass 24, count 0 2006.173.13:38:06.76#ibcon#*mode == 0, iclass 24, count 0 2006.173.13:38:06.76#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.13:38:06.76#ibcon#[25=USB\r\n] 2006.173.13:38:06.76#ibcon#*before write, iclass 24, count 0 2006.173.13:38:06.76#ibcon#enter sib2, iclass 24, count 0 2006.173.13:38:06.76#ibcon#flushed, iclass 24, count 0 2006.173.13:38:06.76#ibcon#about to write, iclass 24, count 0 2006.173.13:38:06.76#ibcon#wrote, iclass 24, count 0 2006.173.13:38:06.76#ibcon#about to read 3, iclass 24, count 0 2006.173.13:38:06.79#ibcon#read 3, iclass 24, count 0 2006.173.13:38:06.79#ibcon#about to read 4, iclass 24, count 0 2006.173.13:38:06.79#ibcon#read 4, iclass 24, count 0 2006.173.13:38:06.79#ibcon#about to read 5, iclass 24, count 0 2006.173.13:38:06.79#ibcon#read 5, iclass 24, count 0 2006.173.13:38:06.79#ibcon#about to read 6, iclass 24, count 0 2006.173.13:38:06.79#ibcon#read 6, iclass 24, count 0 2006.173.13:38:06.79#ibcon#end of sib2, iclass 24, count 0 2006.173.13:38:06.79#ibcon#*after write, iclass 24, count 0 2006.173.13:38:06.79#ibcon#*before return 0, iclass 24, count 0 2006.173.13:38:06.79#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.13:38:06.79#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.13:38:06.79#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.13:38:06.79#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.13:38:06.79$vck44/valo=3,564.99 2006.173.13:38:06.79#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.13:38:06.79#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.13:38:06.79#ibcon#ireg 17 cls_cnt 0 2006.173.13:38:06.79#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.13:38:06.79#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.13:38:06.79#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.13:38:06.79#ibcon#enter wrdev, iclass 26, count 0 2006.173.13:38:06.79#ibcon#first serial, iclass 26, count 0 2006.173.13:38:06.79#ibcon#enter sib2, iclass 26, count 0 2006.173.13:38:06.79#ibcon#flushed, iclass 26, count 0 2006.173.13:38:06.79#ibcon#about to write, iclass 26, count 0 2006.173.13:38:06.79#ibcon#wrote, iclass 26, count 0 2006.173.13:38:06.79#ibcon#about to read 3, iclass 26, count 0 2006.173.13:38:06.81#ibcon#read 3, iclass 26, count 0 2006.173.13:38:06.81#ibcon#about to read 4, iclass 26, count 0 2006.173.13:38:06.81#ibcon#read 4, iclass 26, count 0 2006.173.13:38:06.81#ibcon#about to read 5, iclass 26, count 0 2006.173.13:38:06.81#ibcon#read 5, iclass 26, count 0 2006.173.13:38:06.81#ibcon#about to read 6, iclass 26, count 0 2006.173.13:38:06.81#ibcon#read 6, iclass 26, count 0 2006.173.13:38:06.81#ibcon#end of sib2, iclass 26, count 0 2006.173.13:38:06.81#ibcon#*mode == 0, iclass 26, count 0 2006.173.13:38:06.81#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.13:38:06.81#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.13:38:06.81#ibcon#*before write, iclass 26, count 0 2006.173.13:38:06.81#ibcon#enter sib2, iclass 26, count 0 2006.173.13:38:06.81#ibcon#flushed, iclass 26, count 0 2006.173.13:38:06.81#ibcon#about to write, iclass 26, count 0 2006.173.13:38:06.81#ibcon#wrote, iclass 26, count 0 2006.173.13:38:06.81#ibcon#about to read 3, iclass 26, count 0 2006.173.13:38:06.85#ibcon#read 3, iclass 26, count 0 2006.173.13:38:06.85#ibcon#about to read 4, iclass 26, count 0 2006.173.13:38:06.85#ibcon#read 4, iclass 26, count 0 2006.173.13:38:06.85#ibcon#about to read 5, iclass 26, count 0 2006.173.13:38:06.85#ibcon#read 5, iclass 26, count 0 2006.173.13:38:06.85#ibcon#about to read 6, iclass 26, count 0 2006.173.13:38:06.85#ibcon#read 6, iclass 26, count 0 2006.173.13:38:06.85#ibcon#end of sib2, iclass 26, count 0 2006.173.13:38:06.85#ibcon#*after write, iclass 26, count 0 2006.173.13:38:06.85#ibcon#*before return 0, iclass 26, count 0 2006.173.13:38:06.85#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.13:38:06.85#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.13:38:06.85#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.13:38:06.85#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.13:38:06.85$vck44/va=3,5 2006.173.13:38:06.85#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.13:38:06.85#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.13:38:06.85#ibcon#ireg 11 cls_cnt 2 2006.173.13:38:06.85#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.13:38:06.91#abcon#<5=/04 0.4 1.3 21.961001003.9\r\n> 2006.173.13:38:06.91#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.13:38:06.91#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.13:38:06.91#ibcon#enter wrdev, iclass 28, count 2 2006.173.13:38:06.91#ibcon#first serial, iclass 28, count 2 2006.173.13:38:06.91#ibcon#enter sib2, iclass 28, count 2 2006.173.13:38:06.91#ibcon#flushed, iclass 28, count 2 2006.173.13:38:06.91#ibcon#about to write, iclass 28, count 2 2006.173.13:38:06.91#ibcon#wrote, iclass 28, count 2 2006.173.13:38:06.91#ibcon#about to read 3, iclass 28, count 2 2006.173.13:38:06.93#ibcon#read 3, iclass 28, count 2 2006.173.13:38:06.93#ibcon#about to read 4, iclass 28, count 2 2006.173.13:38:06.93#ibcon#read 4, iclass 28, count 2 2006.173.13:38:06.93#ibcon#about to read 5, iclass 28, count 2 2006.173.13:38:06.93#ibcon#read 5, iclass 28, count 2 2006.173.13:38:06.93#ibcon#about to read 6, iclass 28, count 2 2006.173.13:38:06.93#ibcon#read 6, iclass 28, count 2 2006.173.13:38:06.93#ibcon#end of sib2, iclass 28, count 2 2006.173.13:38:06.93#ibcon#*mode == 0, iclass 28, count 2 2006.173.13:38:06.93#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.13:38:06.93#ibcon#[25=AT03-05\r\n] 2006.173.13:38:06.93#ibcon#*before write, iclass 28, count 2 2006.173.13:38:06.93#ibcon#enter sib2, iclass 28, count 2 2006.173.13:38:06.93#ibcon#flushed, iclass 28, count 2 2006.173.13:38:06.93#ibcon#about to write, iclass 28, count 2 2006.173.13:38:06.93#ibcon#wrote, iclass 28, count 2 2006.173.13:38:06.93#ibcon#about to read 3, iclass 28, count 2 2006.173.13:38:06.93#abcon#{5=INTERFACE CLEAR} 2006.173.13:38:06.96#ibcon#read 3, iclass 28, count 2 2006.173.13:38:06.96#ibcon#about to read 4, iclass 28, count 2 2006.173.13:38:06.96#ibcon#read 4, iclass 28, count 2 2006.173.13:38:06.96#ibcon#about to read 5, iclass 28, count 2 2006.173.13:38:06.96#ibcon#read 5, iclass 28, count 2 2006.173.13:38:06.96#ibcon#about to read 6, iclass 28, count 2 2006.173.13:38:06.96#ibcon#read 6, iclass 28, count 2 2006.173.13:38:06.96#ibcon#end of sib2, iclass 28, count 2 2006.173.13:38:06.96#ibcon#*after write, iclass 28, count 2 2006.173.13:38:06.96#ibcon#*before return 0, iclass 28, count 2 2006.173.13:38:06.96#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.13:38:06.96#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.13:38:06.96#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.13:38:06.96#ibcon#ireg 7 cls_cnt 0 2006.173.13:38:06.96#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.13:38:06.99#abcon#[5=S1D000X0/0*\r\n] 2006.173.13:38:07.08#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.13:38:07.08#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.13:38:07.08#ibcon#enter wrdev, iclass 28, count 0 2006.173.13:38:07.08#ibcon#first serial, iclass 28, count 0 2006.173.13:38:07.08#ibcon#enter sib2, iclass 28, count 0 2006.173.13:38:07.08#ibcon#flushed, iclass 28, count 0 2006.173.13:38:07.08#ibcon#about to write, iclass 28, count 0 2006.173.13:38:07.08#ibcon#wrote, iclass 28, count 0 2006.173.13:38:07.08#ibcon#about to read 3, iclass 28, count 0 2006.173.13:38:07.10#ibcon#read 3, iclass 28, count 0 2006.173.13:38:07.10#ibcon#about to read 4, iclass 28, count 0 2006.173.13:38:07.10#ibcon#read 4, iclass 28, count 0 2006.173.13:38:07.10#ibcon#about to read 5, iclass 28, count 0 2006.173.13:38:07.10#ibcon#read 5, iclass 28, count 0 2006.173.13:38:07.10#ibcon#about to read 6, iclass 28, count 0 2006.173.13:38:07.10#ibcon#read 6, iclass 28, count 0 2006.173.13:38:07.10#ibcon#end of sib2, iclass 28, count 0 2006.173.13:38:07.10#ibcon#*mode == 0, iclass 28, count 0 2006.173.13:38:07.10#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.13:38:07.10#ibcon#[25=USB\r\n] 2006.173.13:38:07.10#ibcon#*before write, iclass 28, count 0 2006.173.13:38:07.10#ibcon#enter sib2, iclass 28, count 0 2006.173.13:38:07.10#ibcon#flushed, iclass 28, count 0 2006.173.13:38:07.10#ibcon#about to write, iclass 28, count 0 2006.173.13:38:07.10#ibcon#wrote, iclass 28, count 0 2006.173.13:38:07.10#ibcon#about to read 3, iclass 28, count 0 2006.173.13:38:07.13#ibcon#read 3, iclass 28, count 0 2006.173.13:38:07.13#ibcon#about to read 4, iclass 28, count 0 2006.173.13:38:07.13#ibcon#read 4, iclass 28, count 0 2006.173.13:38:07.13#ibcon#about to read 5, iclass 28, count 0 2006.173.13:38:07.13#ibcon#read 5, iclass 28, count 0 2006.173.13:38:07.13#ibcon#about to read 6, iclass 28, count 0 2006.173.13:38:07.13#ibcon#read 6, iclass 28, count 0 2006.173.13:38:07.13#ibcon#end of sib2, iclass 28, count 0 2006.173.13:38:07.13#ibcon#*after write, iclass 28, count 0 2006.173.13:38:07.13#ibcon#*before return 0, iclass 28, count 0 2006.173.13:38:07.13#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.13:38:07.13#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.13:38:07.13#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.13:38:07.13#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.13:38:07.13$vck44/valo=4,624.99 2006.173.13:38:07.13#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.13:38:07.13#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.13:38:07.13#ibcon#ireg 17 cls_cnt 0 2006.173.13:38:07.13#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.13:38:07.13#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.13:38:07.13#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.13:38:07.13#ibcon#enter wrdev, iclass 34, count 0 2006.173.13:38:07.13#ibcon#first serial, iclass 34, count 0 2006.173.13:38:07.13#ibcon#enter sib2, iclass 34, count 0 2006.173.13:38:07.13#ibcon#flushed, iclass 34, count 0 2006.173.13:38:07.13#ibcon#about to write, iclass 34, count 0 2006.173.13:38:07.13#ibcon#wrote, iclass 34, count 0 2006.173.13:38:07.13#ibcon#about to read 3, iclass 34, count 0 2006.173.13:38:07.15#ibcon#read 3, iclass 34, count 0 2006.173.13:38:07.15#ibcon#about to read 4, iclass 34, count 0 2006.173.13:38:07.15#ibcon#read 4, iclass 34, count 0 2006.173.13:38:07.15#ibcon#about to read 5, iclass 34, count 0 2006.173.13:38:07.15#ibcon#read 5, iclass 34, count 0 2006.173.13:38:07.15#ibcon#about to read 6, iclass 34, count 0 2006.173.13:38:07.15#ibcon#read 6, iclass 34, count 0 2006.173.13:38:07.15#ibcon#end of sib2, iclass 34, count 0 2006.173.13:38:07.15#ibcon#*mode == 0, iclass 34, count 0 2006.173.13:38:07.15#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.13:38:07.15#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.13:38:07.15#ibcon#*before write, iclass 34, count 0 2006.173.13:38:07.15#ibcon#enter sib2, iclass 34, count 0 2006.173.13:38:07.15#ibcon#flushed, iclass 34, count 0 2006.173.13:38:07.15#ibcon#about to write, iclass 34, count 0 2006.173.13:38:07.15#ibcon#wrote, iclass 34, count 0 2006.173.13:38:07.15#ibcon#about to read 3, iclass 34, count 0 2006.173.13:38:07.19#ibcon#read 3, iclass 34, count 0 2006.173.13:38:07.19#ibcon#about to read 4, iclass 34, count 0 2006.173.13:38:07.19#ibcon#read 4, iclass 34, count 0 2006.173.13:38:07.19#ibcon#about to read 5, iclass 34, count 0 2006.173.13:38:07.19#ibcon#read 5, iclass 34, count 0 2006.173.13:38:07.19#ibcon#about to read 6, iclass 34, count 0 2006.173.13:38:07.19#ibcon#read 6, iclass 34, count 0 2006.173.13:38:07.19#ibcon#end of sib2, iclass 34, count 0 2006.173.13:38:07.19#ibcon#*after write, iclass 34, count 0 2006.173.13:38:07.19#ibcon#*before return 0, iclass 34, count 0 2006.173.13:38:07.19#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.13:38:07.19#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.13:38:07.19#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.13:38:07.19#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.13:38:07.19$vck44/va=4,6 2006.173.13:38:07.19#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.13:38:07.19#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.13:38:07.19#ibcon#ireg 11 cls_cnt 2 2006.173.13:38:07.19#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.13:38:07.25#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.13:38:07.25#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.13:38:07.25#ibcon#enter wrdev, iclass 36, count 2 2006.173.13:38:07.25#ibcon#first serial, iclass 36, count 2 2006.173.13:38:07.25#ibcon#enter sib2, iclass 36, count 2 2006.173.13:38:07.25#ibcon#flushed, iclass 36, count 2 2006.173.13:38:07.25#ibcon#about to write, iclass 36, count 2 2006.173.13:38:07.25#ibcon#wrote, iclass 36, count 2 2006.173.13:38:07.25#ibcon#about to read 3, iclass 36, count 2 2006.173.13:38:07.27#ibcon#read 3, iclass 36, count 2 2006.173.13:38:07.27#ibcon#about to read 4, iclass 36, count 2 2006.173.13:38:07.27#ibcon#read 4, iclass 36, count 2 2006.173.13:38:07.27#ibcon#about to read 5, iclass 36, count 2 2006.173.13:38:07.27#ibcon#read 5, iclass 36, count 2 2006.173.13:38:07.27#ibcon#about to read 6, iclass 36, count 2 2006.173.13:38:07.27#ibcon#read 6, iclass 36, count 2 2006.173.13:38:07.27#ibcon#end of sib2, iclass 36, count 2 2006.173.13:38:07.27#ibcon#*mode == 0, iclass 36, count 2 2006.173.13:38:07.27#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.13:38:07.27#ibcon#[25=AT04-06\r\n] 2006.173.13:38:07.27#ibcon#*before write, iclass 36, count 2 2006.173.13:38:07.27#ibcon#enter sib2, iclass 36, count 2 2006.173.13:38:07.27#ibcon#flushed, iclass 36, count 2 2006.173.13:38:07.27#ibcon#about to write, iclass 36, count 2 2006.173.13:38:07.27#ibcon#wrote, iclass 36, count 2 2006.173.13:38:07.27#ibcon#about to read 3, iclass 36, count 2 2006.173.13:38:07.30#ibcon#read 3, iclass 36, count 2 2006.173.13:38:07.30#ibcon#about to read 4, iclass 36, count 2 2006.173.13:38:07.30#ibcon#read 4, iclass 36, count 2 2006.173.13:38:07.30#ibcon#about to read 5, iclass 36, count 2 2006.173.13:38:07.30#ibcon#read 5, iclass 36, count 2 2006.173.13:38:07.30#ibcon#about to read 6, iclass 36, count 2 2006.173.13:38:07.30#ibcon#read 6, iclass 36, count 2 2006.173.13:38:07.30#ibcon#end of sib2, iclass 36, count 2 2006.173.13:38:07.30#ibcon#*after write, iclass 36, count 2 2006.173.13:38:07.30#ibcon#*before return 0, iclass 36, count 2 2006.173.13:38:07.30#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.13:38:07.30#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.13:38:07.30#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.13:38:07.30#ibcon#ireg 7 cls_cnt 0 2006.173.13:38:07.30#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.13:38:07.42#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.13:38:07.42#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.13:38:07.42#ibcon#enter wrdev, iclass 36, count 0 2006.173.13:38:07.42#ibcon#first serial, iclass 36, count 0 2006.173.13:38:07.42#ibcon#enter sib2, iclass 36, count 0 2006.173.13:38:07.42#ibcon#flushed, iclass 36, count 0 2006.173.13:38:07.42#ibcon#about to write, iclass 36, count 0 2006.173.13:38:07.42#ibcon#wrote, iclass 36, count 0 2006.173.13:38:07.42#ibcon#about to read 3, iclass 36, count 0 2006.173.13:38:07.44#ibcon#read 3, iclass 36, count 0 2006.173.13:38:07.44#ibcon#about to read 4, iclass 36, count 0 2006.173.13:38:07.44#ibcon#read 4, iclass 36, count 0 2006.173.13:38:07.44#ibcon#about to read 5, iclass 36, count 0 2006.173.13:38:07.44#ibcon#read 5, iclass 36, count 0 2006.173.13:38:07.44#ibcon#about to read 6, iclass 36, count 0 2006.173.13:38:07.44#ibcon#read 6, iclass 36, count 0 2006.173.13:38:07.44#ibcon#end of sib2, iclass 36, count 0 2006.173.13:38:07.44#ibcon#*mode == 0, iclass 36, count 0 2006.173.13:38:07.44#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.13:38:07.44#ibcon#[25=USB\r\n] 2006.173.13:38:07.44#ibcon#*before write, iclass 36, count 0 2006.173.13:38:07.44#ibcon#enter sib2, iclass 36, count 0 2006.173.13:38:07.44#ibcon#flushed, iclass 36, count 0 2006.173.13:38:07.44#ibcon#about to write, iclass 36, count 0 2006.173.13:38:07.44#ibcon#wrote, iclass 36, count 0 2006.173.13:38:07.44#ibcon#about to read 3, iclass 36, count 0 2006.173.13:38:07.47#ibcon#read 3, iclass 36, count 0 2006.173.13:38:07.47#ibcon#about to read 4, iclass 36, count 0 2006.173.13:38:07.47#ibcon#read 4, iclass 36, count 0 2006.173.13:38:07.47#ibcon#about to read 5, iclass 36, count 0 2006.173.13:38:07.47#ibcon#read 5, iclass 36, count 0 2006.173.13:38:07.47#ibcon#about to read 6, iclass 36, count 0 2006.173.13:38:07.47#ibcon#read 6, iclass 36, count 0 2006.173.13:38:07.47#ibcon#end of sib2, iclass 36, count 0 2006.173.13:38:07.47#ibcon#*after write, iclass 36, count 0 2006.173.13:38:07.47#ibcon#*before return 0, iclass 36, count 0 2006.173.13:38:07.47#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.13:38:07.47#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.13:38:07.47#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.13:38:07.47#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.13:38:07.47$vck44/valo=5,734.99 2006.173.13:38:07.47#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.13:38:07.47#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.13:38:07.47#ibcon#ireg 17 cls_cnt 0 2006.173.13:38:07.47#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.13:38:07.47#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.13:38:07.47#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.13:38:07.47#ibcon#enter wrdev, iclass 38, count 0 2006.173.13:38:07.47#ibcon#first serial, iclass 38, count 0 2006.173.13:38:07.47#ibcon#enter sib2, iclass 38, count 0 2006.173.13:38:07.47#ibcon#flushed, iclass 38, count 0 2006.173.13:38:07.47#ibcon#about to write, iclass 38, count 0 2006.173.13:38:07.47#ibcon#wrote, iclass 38, count 0 2006.173.13:38:07.47#ibcon#about to read 3, iclass 38, count 0 2006.173.13:38:07.49#ibcon#read 3, iclass 38, count 0 2006.173.13:38:07.49#ibcon#about to read 4, iclass 38, count 0 2006.173.13:38:07.49#ibcon#read 4, iclass 38, count 0 2006.173.13:38:07.49#ibcon#about to read 5, iclass 38, count 0 2006.173.13:38:07.49#ibcon#read 5, iclass 38, count 0 2006.173.13:38:07.49#ibcon#about to read 6, iclass 38, count 0 2006.173.13:38:07.49#ibcon#read 6, iclass 38, count 0 2006.173.13:38:07.49#ibcon#end of sib2, iclass 38, count 0 2006.173.13:38:07.49#ibcon#*mode == 0, iclass 38, count 0 2006.173.13:38:07.49#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.13:38:07.49#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.13:38:07.49#ibcon#*before write, iclass 38, count 0 2006.173.13:38:07.49#ibcon#enter sib2, iclass 38, count 0 2006.173.13:38:07.49#ibcon#flushed, iclass 38, count 0 2006.173.13:38:07.49#ibcon#about to write, iclass 38, count 0 2006.173.13:38:07.49#ibcon#wrote, iclass 38, count 0 2006.173.13:38:07.49#ibcon#about to read 3, iclass 38, count 0 2006.173.13:38:07.53#ibcon#read 3, iclass 38, count 0 2006.173.13:38:07.53#ibcon#about to read 4, iclass 38, count 0 2006.173.13:38:07.53#ibcon#read 4, iclass 38, count 0 2006.173.13:38:07.53#ibcon#about to read 5, iclass 38, count 0 2006.173.13:38:07.53#ibcon#read 5, iclass 38, count 0 2006.173.13:38:07.53#ibcon#about to read 6, iclass 38, count 0 2006.173.13:38:07.53#ibcon#read 6, iclass 38, count 0 2006.173.13:38:07.53#ibcon#end of sib2, iclass 38, count 0 2006.173.13:38:07.53#ibcon#*after write, iclass 38, count 0 2006.173.13:38:07.53#ibcon#*before return 0, iclass 38, count 0 2006.173.13:38:07.53#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.13:38:07.53#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.13:38:07.53#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.13:38:07.53#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.13:38:07.53$vck44/va=5,4 2006.173.13:38:07.53#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.13:38:07.53#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.13:38:07.53#ibcon#ireg 11 cls_cnt 2 2006.173.13:38:07.53#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.13:38:07.59#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.13:38:07.59#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.13:38:07.59#ibcon#enter wrdev, iclass 40, count 2 2006.173.13:38:07.59#ibcon#first serial, iclass 40, count 2 2006.173.13:38:07.59#ibcon#enter sib2, iclass 40, count 2 2006.173.13:38:07.59#ibcon#flushed, iclass 40, count 2 2006.173.13:38:07.59#ibcon#about to write, iclass 40, count 2 2006.173.13:38:07.59#ibcon#wrote, iclass 40, count 2 2006.173.13:38:07.59#ibcon#about to read 3, iclass 40, count 2 2006.173.13:38:07.61#ibcon#read 3, iclass 40, count 2 2006.173.13:38:07.61#ibcon#about to read 4, iclass 40, count 2 2006.173.13:38:07.61#ibcon#read 4, iclass 40, count 2 2006.173.13:38:07.61#ibcon#about to read 5, iclass 40, count 2 2006.173.13:38:07.61#ibcon#read 5, iclass 40, count 2 2006.173.13:38:07.61#ibcon#about to read 6, iclass 40, count 2 2006.173.13:38:07.61#ibcon#read 6, iclass 40, count 2 2006.173.13:38:07.61#ibcon#end of sib2, iclass 40, count 2 2006.173.13:38:07.61#ibcon#*mode == 0, iclass 40, count 2 2006.173.13:38:07.61#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.13:38:07.61#ibcon#[25=AT05-04\r\n] 2006.173.13:38:07.61#ibcon#*before write, iclass 40, count 2 2006.173.13:38:07.61#ibcon#enter sib2, iclass 40, count 2 2006.173.13:38:07.61#ibcon#flushed, iclass 40, count 2 2006.173.13:38:07.61#ibcon#about to write, iclass 40, count 2 2006.173.13:38:07.61#ibcon#wrote, iclass 40, count 2 2006.173.13:38:07.61#ibcon#about to read 3, iclass 40, count 2 2006.173.13:38:07.64#ibcon#read 3, iclass 40, count 2 2006.173.13:38:07.64#ibcon#about to read 4, iclass 40, count 2 2006.173.13:38:07.64#ibcon#read 4, iclass 40, count 2 2006.173.13:38:07.64#ibcon#about to read 5, iclass 40, count 2 2006.173.13:38:07.64#ibcon#read 5, iclass 40, count 2 2006.173.13:38:07.64#ibcon#about to read 6, iclass 40, count 2 2006.173.13:38:07.64#ibcon#read 6, iclass 40, count 2 2006.173.13:38:07.64#ibcon#end of sib2, iclass 40, count 2 2006.173.13:38:07.64#ibcon#*after write, iclass 40, count 2 2006.173.13:38:07.64#ibcon#*before return 0, iclass 40, count 2 2006.173.13:38:07.64#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.13:38:07.64#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.13:38:07.64#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.13:38:07.64#ibcon#ireg 7 cls_cnt 0 2006.173.13:38:07.64#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.13:38:07.76#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.13:38:07.76#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.13:38:07.76#ibcon#enter wrdev, iclass 40, count 0 2006.173.13:38:07.76#ibcon#first serial, iclass 40, count 0 2006.173.13:38:07.76#ibcon#enter sib2, iclass 40, count 0 2006.173.13:38:07.76#ibcon#flushed, iclass 40, count 0 2006.173.13:38:07.76#ibcon#about to write, iclass 40, count 0 2006.173.13:38:07.76#ibcon#wrote, iclass 40, count 0 2006.173.13:38:07.76#ibcon#about to read 3, iclass 40, count 0 2006.173.13:38:07.78#ibcon#read 3, iclass 40, count 0 2006.173.13:38:07.78#ibcon#about to read 4, iclass 40, count 0 2006.173.13:38:07.78#ibcon#read 4, iclass 40, count 0 2006.173.13:38:07.78#ibcon#about to read 5, iclass 40, count 0 2006.173.13:38:07.78#ibcon#read 5, iclass 40, count 0 2006.173.13:38:07.78#ibcon#about to read 6, iclass 40, count 0 2006.173.13:38:07.78#ibcon#read 6, iclass 40, count 0 2006.173.13:38:07.78#ibcon#end of sib2, iclass 40, count 0 2006.173.13:38:07.78#ibcon#*mode == 0, iclass 40, count 0 2006.173.13:38:07.78#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.13:38:07.78#ibcon#[25=USB\r\n] 2006.173.13:38:07.78#ibcon#*before write, iclass 40, count 0 2006.173.13:38:07.78#ibcon#enter sib2, iclass 40, count 0 2006.173.13:38:07.78#ibcon#flushed, iclass 40, count 0 2006.173.13:38:07.78#ibcon#about to write, iclass 40, count 0 2006.173.13:38:07.78#ibcon#wrote, iclass 40, count 0 2006.173.13:38:07.78#ibcon#about to read 3, iclass 40, count 0 2006.173.13:38:07.81#ibcon#read 3, iclass 40, count 0 2006.173.13:38:07.81#ibcon#about to read 4, iclass 40, count 0 2006.173.13:38:07.81#ibcon#read 4, iclass 40, count 0 2006.173.13:38:07.81#ibcon#about to read 5, iclass 40, count 0 2006.173.13:38:07.81#ibcon#read 5, iclass 40, count 0 2006.173.13:38:07.81#ibcon#about to read 6, iclass 40, count 0 2006.173.13:38:07.81#ibcon#read 6, iclass 40, count 0 2006.173.13:38:07.81#ibcon#end of sib2, iclass 40, count 0 2006.173.13:38:07.81#ibcon#*after write, iclass 40, count 0 2006.173.13:38:07.81#ibcon#*before return 0, iclass 40, count 0 2006.173.13:38:07.81#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.13:38:07.81#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.13:38:07.81#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.13:38:07.81#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.13:38:07.81$vck44/valo=6,814.99 2006.173.13:38:07.81#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.13:38:07.81#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.13:38:07.81#ibcon#ireg 17 cls_cnt 0 2006.173.13:38:07.81#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.13:38:07.81#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.13:38:07.81#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.13:38:07.81#ibcon#enter wrdev, iclass 4, count 0 2006.173.13:38:07.81#ibcon#first serial, iclass 4, count 0 2006.173.13:38:07.81#ibcon#enter sib2, iclass 4, count 0 2006.173.13:38:07.81#ibcon#flushed, iclass 4, count 0 2006.173.13:38:07.81#ibcon#about to write, iclass 4, count 0 2006.173.13:38:07.81#ibcon#wrote, iclass 4, count 0 2006.173.13:38:07.81#ibcon#about to read 3, iclass 4, count 0 2006.173.13:38:07.83#ibcon#read 3, iclass 4, count 0 2006.173.13:38:07.83#ibcon#about to read 4, iclass 4, count 0 2006.173.13:38:07.83#ibcon#read 4, iclass 4, count 0 2006.173.13:38:07.83#ibcon#about to read 5, iclass 4, count 0 2006.173.13:38:07.83#ibcon#read 5, iclass 4, count 0 2006.173.13:38:07.83#ibcon#about to read 6, iclass 4, count 0 2006.173.13:38:07.83#ibcon#read 6, iclass 4, count 0 2006.173.13:38:07.83#ibcon#end of sib2, iclass 4, count 0 2006.173.13:38:07.83#ibcon#*mode == 0, iclass 4, count 0 2006.173.13:38:07.83#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.13:38:07.83#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.13:38:07.83#ibcon#*before write, iclass 4, count 0 2006.173.13:38:07.83#ibcon#enter sib2, iclass 4, count 0 2006.173.13:38:07.83#ibcon#flushed, iclass 4, count 0 2006.173.13:38:07.83#ibcon#about to write, iclass 4, count 0 2006.173.13:38:07.83#ibcon#wrote, iclass 4, count 0 2006.173.13:38:07.83#ibcon#about to read 3, iclass 4, count 0 2006.173.13:38:07.87#ibcon#read 3, iclass 4, count 0 2006.173.13:38:07.87#ibcon#about to read 4, iclass 4, count 0 2006.173.13:38:07.87#ibcon#read 4, iclass 4, count 0 2006.173.13:38:07.87#ibcon#about to read 5, iclass 4, count 0 2006.173.13:38:07.87#ibcon#read 5, iclass 4, count 0 2006.173.13:38:07.87#ibcon#about to read 6, iclass 4, count 0 2006.173.13:38:07.87#ibcon#read 6, iclass 4, count 0 2006.173.13:38:07.87#ibcon#end of sib2, iclass 4, count 0 2006.173.13:38:07.87#ibcon#*after write, iclass 4, count 0 2006.173.13:38:07.87#ibcon#*before return 0, iclass 4, count 0 2006.173.13:38:07.87#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.13:38:07.87#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.13:38:07.87#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.13:38:07.87#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.13:38:07.87$vck44/va=6,3 2006.173.13:38:07.87#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.13:38:07.87#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.13:38:07.87#ibcon#ireg 11 cls_cnt 2 2006.173.13:38:07.87#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.13:38:07.93#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.13:38:07.93#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.13:38:07.93#ibcon#enter wrdev, iclass 6, count 2 2006.173.13:38:07.93#ibcon#first serial, iclass 6, count 2 2006.173.13:38:07.93#ibcon#enter sib2, iclass 6, count 2 2006.173.13:38:07.93#ibcon#flushed, iclass 6, count 2 2006.173.13:38:07.93#ibcon#about to write, iclass 6, count 2 2006.173.13:38:07.93#ibcon#wrote, iclass 6, count 2 2006.173.13:38:07.93#ibcon#about to read 3, iclass 6, count 2 2006.173.13:38:07.95#ibcon#read 3, iclass 6, count 2 2006.173.13:38:07.95#ibcon#about to read 4, iclass 6, count 2 2006.173.13:38:07.95#ibcon#read 4, iclass 6, count 2 2006.173.13:38:07.95#ibcon#about to read 5, iclass 6, count 2 2006.173.13:38:07.95#ibcon#read 5, iclass 6, count 2 2006.173.13:38:07.95#ibcon#about to read 6, iclass 6, count 2 2006.173.13:38:07.95#ibcon#read 6, iclass 6, count 2 2006.173.13:38:07.95#ibcon#end of sib2, iclass 6, count 2 2006.173.13:38:07.95#ibcon#*mode == 0, iclass 6, count 2 2006.173.13:38:07.95#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.13:38:07.95#ibcon#[25=AT06-03\r\n] 2006.173.13:38:07.95#ibcon#*before write, iclass 6, count 2 2006.173.13:38:07.95#ibcon#enter sib2, iclass 6, count 2 2006.173.13:38:07.95#ibcon#flushed, iclass 6, count 2 2006.173.13:38:07.95#ibcon#about to write, iclass 6, count 2 2006.173.13:38:07.95#ibcon#wrote, iclass 6, count 2 2006.173.13:38:07.95#ibcon#about to read 3, iclass 6, count 2 2006.173.13:38:07.98#ibcon#read 3, iclass 6, count 2 2006.173.13:38:07.98#ibcon#about to read 4, iclass 6, count 2 2006.173.13:38:07.98#ibcon#read 4, iclass 6, count 2 2006.173.13:38:07.98#ibcon#about to read 5, iclass 6, count 2 2006.173.13:38:07.98#ibcon#read 5, iclass 6, count 2 2006.173.13:38:07.98#ibcon#about to read 6, iclass 6, count 2 2006.173.13:38:07.98#ibcon#read 6, iclass 6, count 2 2006.173.13:38:07.98#ibcon#end of sib2, iclass 6, count 2 2006.173.13:38:07.98#ibcon#*after write, iclass 6, count 2 2006.173.13:38:07.98#ibcon#*before return 0, iclass 6, count 2 2006.173.13:38:07.98#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.13:38:07.98#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.13:38:07.98#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.13:38:07.98#ibcon#ireg 7 cls_cnt 0 2006.173.13:38:07.98#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.13:38:08.10#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.13:38:08.10#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.13:38:08.10#ibcon#enter wrdev, iclass 6, count 0 2006.173.13:38:08.10#ibcon#first serial, iclass 6, count 0 2006.173.13:38:08.10#ibcon#enter sib2, iclass 6, count 0 2006.173.13:38:08.10#ibcon#flushed, iclass 6, count 0 2006.173.13:38:08.10#ibcon#about to write, iclass 6, count 0 2006.173.13:38:08.10#ibcon#wrote, iclass 6, count 0 2006.173.13:38:08.10#ibcon#about to read 3, iclass 6, count 0 2006.173.13:38:08.12#ibcon#read 3, iclass 6, count 0 2006.173.13:38:08.12#ibcon#about to read 4, iclass 6, count 0 2006.173.13:38:08.12#ibcon#read 4, iclass 6, count 0 2006.173.13:38:08.12#ibcon#about to read 5, iclass 6, count 0 2006.173.13:38:08.12#ibcon#read 5, iclass 6, count 0 2006.173.13:38:08.12#ibcon#about to read 6, iclass 6, count 0 2006.173.13:38:08.12#ibcon#read 6, iclass 6, count 0 2006.173.13:38:08.12#ibcon#end of sib2, iclass 6, count 0 2006.173.13:38:08.12#ibcon#*mode == 0, iclass 6, count 0 2006.173.13:38:08.12#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.13:38:08.12#ibcon#[25=USB\r\n] 2006.173.13:38:08.12#ibcon#*before write, iclass 6, count 0 2006.173.13:38:08.12#ibcon#enter sib2, iclass 6, count 0 2006.173.13:38:08.12#ibcon#flushed, iclass 6, count 0 2006.173.13:38:08.12#ibcon#about to write, iclass 6, count 0 2006.173.13:38:08.12#ibcon#wrote, iclass 6, count 0 2006.173.13:38:08.12#ibcon#about to read 3, iclass 6, count 0 2006.173.13:38:08.15#ibcon#read 3, iclass 6, count 0 2006.173.13:38:08.15#ibcon#about to read 4, iclass 6, count 0 2006.173.13:38:08.15#ibcon#read 4, iclass 6, count 0 2006.173.13:38:08.15#ibcon#about to read 5, iclass 6, count 0 2006.173.13:38:08.15#ibcon#read 5, iclass 6, count 0 2006.173.13:38:08.15#ibcon#about to read 6, iclass 6, count 0 2006.173.13:38:08.15#ibcon#read 6, iclass 6, count 0 2006.173.13:38:08.15#ibcon#end of sib2, iclass 6, count 0 2006.173.13:38:08.15#ibcon#*after write, iclass 6, count 0 2006.173.13:38:08.15#ibcon#*before return 0, iclass 6, count 0 2006.173.13:38:08.15#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.13:38:08.15#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.13:38:08.15#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.13:38:08.15#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.13:38:08.15$vck44/valo=7,864.99 2006.173.13:38:08.15#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.13:38:08.15#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.13:38:08.15#ibcon#ireg 17 cls_cnt 0 2006.173.13:38:08.15#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.13:38:08.15#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.13:38:08.15#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.13:38:08.15#ibcon#enter wrdev, iclass 10, count 0 2006.173.13:38:08.15#ibcon#first serial, iclass 10, count 0 2006.173.13:38:08.15#ibcon#enter sib2, iclass 10, count 0 2006.173.13:38:08.15#ibcon#flushed, iclass 10, count 0 2006.173.13:38:08.15#ibcon#about to write, iclass 10, count 0 2006.173.13:38:08.15#ibcon#wrote, iclass 10, count 0 2006.173.13:38:08.15#ibcon#about to read 3, iclass 10, count 0 2006.173.13:38:08.17#ibcon#read 3, iclass 10, count 0 2006.173.13:38:08.17#ibcon#about to read 4, iclass 10, count 0 2006.173.13:38:08.17#ibcon#read 4, iclass 10, count 0 2006.173.13:38:08.17#ibcon#about to read 5, iclass 10, count 0 2006.173.13:38:08.17#ibcon#read 5, iclass 10, count 0 2006.173.13:38:08.17#ibcon#about to read 6, iclass 10, count 0 2006.173.13:38:08.17#ibcon#read 6, iclass 10, count 0 2006.173.13:38:08.17#ibcon#end of sib2, iclass 10, count 0 2006.173.13:38:08.17#ibcon#*mode == 0, iclass 10, count 0 2006.173.13:38:08.17#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.13:38:08.17#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.13:38:08.17#ibcon#*before write, iclass 10, count 0 2006.173.13:38:08.17#ibcon#enter sib2, iclass 10, count 0 2006.173.13:38:08.17#ibcon#flushed, iclass 10, count 0 2006.173.13:38:08.17#ibcon#about to write, iclass 10, count 0 2006.173.13:38:08.17#ibcon#wrote, iclass 10, count 0 2006.173.13:38:08.17#ibcon#about to read 3, iclass 10, count 0 2006.173.13:38:08.21#ibcon#read 3, iclass 10, count 0 2006.173.13:38:08.21#ibcon#about to read 4, iclass 10, count 0 2006.173.13:38:08.21#ibcon#read 4, iclass 10, count 0 2006.173.13:38:08.21#ibcon#about to read 5, iclass 10, count 0 2006.173.13:38:08.21#ibcon#read 5, iclass 10, count 0 2006.173.13:38:08.21#ibcon#about to read 6, iclass 10, count 0 2006.173.13:38:08.21#ibcon#read 6, iclass 10, count 0 2006.173.13:38:08.21#ibcon#end of sib2, iclass 10, count 0 2006.173.13:38:08.21#ibcon#*after write, iclass 10, count 0 2006.173.13:38:08.21#ibcon#*before return 0, iclass 10, count 0 2006.173.13:38:08.21#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.13:38:08.21#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.13:38:08.21#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.13:38:08.21#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.13:38:08.21$vck44/va=7,4 2006.173.13:38:08.21#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.13:38:08.21#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.13:38:08.21#ibcon#ireg 11 cls_cnt 2 2006.173.13:38:08.21#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.13:38:08.27#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.13:38:08.27#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.13:38:08.27#ibcon#enter wrdev, iclass 12, count 2 2006.173.13:38:08.27#ibcon#first serial, iclass 12, count 2 2006.173.13:38:08.27#ibcon#enter sib2, iclass 12, count 2 2006.173.13:38:08.27#ibcon#flushed, iclass 12, count 2 2006.173.13:38:08.27#ibcon#about to write, iclass 12, count 2 2006.173.13:38:08.27#ibcon#wrote, iclass 12, count 2 2006.173.13:38:08.27#ibcon#about to read 3, iclass 12, count 2 2006.173.13:38:08.29#ibcon#read 3, iclass 12, count 2 2006.173.13:38:08.29#ibcon#about to read 4, iclass 12, count 2 2006.173.13:38:08.29#ibcon#read 4, iclass 12, count 2 2006.173.13:38:08.29#ibcon#about to read 5, iclass 12, count 2 2006.173.13:38:08.29#ibcon#read 5, iclass 12, count 2 2006.173.13:38:08.29#ibcon#about to read 6, iclass 12, count 2 2006.173.13:38:08.29#ibcon#read 6, iclass 12, count 2 2006.173.13:38:08.29#ibcon#end of sib2, iclass 12, count 2 2006.173.13:38:08.29#ibcon#*mode == 0, iclass 12, count 2 2006.173.13:38:08.29#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.13:38:08.29#ibcon#[25=AT07-04\r\n] 2006.173.13:38:08.29#ibcon#*before write, iclass 12, count 2 2006.173.13:38:08.29#ibcon#enter sib2, iclass 12, count 2 2006.173.13:38:08.29#ibcon#flushed, iclass 12, count 2 2006.173.13:38:08.29#ibcon#about to write, iclass 12, count 2 2006.173.13:38:08.29#ibcon#wrote, iclass 12, count 2 2006.173.13:38:08.29#ibcon#about to read 3, iclass 12, count 2 2006.173.13:38:08.32#ibcon#read 3, iclass 12, count 2 2006.173.13:38:08.32#ibcon#about to read 4, iclass 12, count 2 2006.173.13:38:08.32#ibcon#read 4, iclass 12, count 2 2006.173.13:38:08.32#ibcon#about to read 5, iclass 12, count 2 2006.173.13:38:08.32#ibcon#read 5, iclass 12, count 2 2006.173.13:38:08.32#ibcon#about to read 6, iclass 12, count 2 2006.173.13:38:08.32#ibcon#read 6, iclass 12, count 2 2006.173.13:38:08.32#ibcon#end of sib2, iclass 12, count 2 2006.173.13:38:08.32#ibcon#*after write, iclass 12, count 2 2006.173.13:38:08.32#ibcon#*before return 0, iclass 12, count 2 2006.173.13:38:08.32#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.13:38:08.32#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.13:38:08.32#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.13:38:08.32#ibcon#ireg 7 cls_cnt 0 2006.173.13:38:08.32#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.13:38:08.44#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.13:38:08.44#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.13:38:08.44#ibcon#enter wrdev, iclass 12, count 0 2006.173.13:38:08.44#ibcon#first serial, iclass 12, count 0 2006.173.13:38:08.44#ibcon#enter sib2, iclass 12, count 0 2006.173.13:38:08.44#ibcon#flushed, iclass 12, count 0 2006.173.13:38:08.44#ibcon#about to write, iclass 12, count 0 2006.173.13:38:08.44#ibcon#wrote, iclass 12, count 0 2006.173.13:38:08.44#ibcon#about to read 3, iclass 12, count 0 2006.173.13:38:08.46#ibcon#read 3, iclass 12, count 0 2006.173.13:38:08.46#ibcon#about to read 4, iclass 12, count 0 2006.173.13:38:08.46#ibcon#read 4, iclass 12, count 0 2006.173.13:38:08.46#ibcon#about to read 5, iclass 12, count 0 2006.173.13:38:08.46#ibcon#read 5, iclass 12, count 0 2006.173.13:38:08.46#ibcon#about to read 6, iclass 12, count 0 2006.173.13:38:08.46#ibcon#read 6, iclass 12, count 0 2006.173.13:38:08.46#ibcon#end of sib2, iclass 12, count 0 2006.173.13:38:08.46#ibcon#*mode == 0, iclass 12, count 0 2006.173.13:38:08.46#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.13:38:08.46#ibcon#[25=USB\r\n] 2006.173.13:38:08.46#ibcon#*before write, iclass 12, count 0 2006.173.13:38:08.46#ibcon#enter sib2, iclass 12, count 0 2006.173.13:38:08.46#ibcon#flushed, iclass 12, count 0 2006.173.13:38:08.46#ibcon#about to write, iclass 12, count 0 2006.173.13:38:08.46#ibcon#wrote, iclass 12, count 0 2006.173.13:38:08.46#ibcon#about to read 3, iclass 12, count 0 2006.173.13:38:08.49#ibcon#read 3, iclass 12, count 0 2006.173.13:38:08.49#ibcon#about to read 4, iclass 12, count 0 2006.173.13:38:08.49#ibcon#read 4, iclass 12, count 0 2006.173.13:38:08.49#ibcon#about to read 5, iclass 12, count 0 2006.173.13:38:08.49#ibcon#read 5, iclass 12, count 0 2006.173.13:38:08.49#ibcon#about to read 6, iclass 12, count 0 2006.173.13:38:08.49#ibcon#read 6, iclass 12, count 0 2006.173.13:38:08.49#ibcon#end of sib2, iclass 12, count 0 2006.173.13:38:08.49#ibcon#*after write, iclass 12, count 0 2006.173.13:38:08.49#ibcon#*before return 0, iclass 12, count 0 2006.173.13:38:08.49#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.13:38:08.49#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.13:38:08.49#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.13:38:08.49#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.13:38:08.49$vck44/valo=8,884.99 2006.173.13:38:08.49#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.13:38:08.49#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.13:38:08.49#ibcon#ireg 17 cls_cnt 0 2006.173.13:38:08.49#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.13:38:08.49#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.13:38:08.49#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.13:38:08.49#ibcon#enter wrdev, iclass 14, count 0 2006.173.13:38:08.49#ibcon#first serial, iclass 14, count 0 2006.173.13:38:08.49#ibcon#enter sib2, iclass 14, count 0 2006.173.13:38:08.49#ibcon#flushed, iclass 14, count 0 2006.173.13:38:08.49#ibcon#about to write, iclass 14, count 0 2006.173.13:38:08.49#ibcon#wrote, iclass 14, count 0 2006.173.13:38:08.49#ibcon#about to read 3, iclass 14, count 0 2006.173.13:38:08.51#ibcon#read 3, iclass 14, count 0 2006.173.13:38:08.51#ibcon#about to read 4, iclass 14, count 0 2006.173.13:38:08.51#ibcon#read 4, iclass 14, count 0 2006.173.13:38:08.51#ibcon#about to read 5, iclass 14, count 0 2006.173.13:38:08.51#ibcon#read 5, iclass 14, count 0 2006.173.13:38:08.51#ibcon#about to read 6, iclass 14, count 0 2006.173.13:38:08.51#ibcon#read 6, iclass 14, count 0 2006.173.13:38:08.51#ibcon#end of sib2, iclass 14, count 0 2006.173.13:38:08.51#ibcon#*mode == 0, iclass 14, count 0 2006.173.13:38:08.51#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.13:38:08.51#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.13:38:08.51#ibcon#*before write, iclass 14, count 0 2006.173.13:38:08.51#ibcon#enter sib2, iclass 14, count 0 2006.173.13:38:08.51#ibcon#flushed, iclass 14, count 0 2006.173.13:38:08.51#ibcon#about to write, iclass 14, count 0 2006.173.13:38:08.51#ibcon#wrote, iclass 14, count 0 2006.173.13:38:08.51#ibcon#about to read 3, iclass 14, count 0 2006.173.13:38:08.55#ibcon#read 3, iclass 14, count 0 2006.173.13:38:08.55#ibcon#about to read 4, iclass 14, count 0 2006.173.13:38:08.55#ibcon#read 4, iclass 14, count 0 2006.173.13:38:08.55#ibcon#about to read 5, iclass 14, count 0 2006.173.13:38:08.55#ibcon#read 5, iclass 14, count 0 2006.173.13:38:08.55#ibcon#about to read 6, iclass 14, count 0 2006.173.13:38:08.55#ibcon#read 6, iclass 14, count 0 2006.173.13:38:08.55#ibcon#end of sib2, iclass 14, count 0 2006.173.13:38:08.55#ibcon#*after write, iclass 14, count 0 2006.173.13:38:08.55#ibcon#*before return 0, iclass 14, count 0 2006.173.13:38:08.55#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.13:38:08.55#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.13:38:08.55#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.13:38:08.55#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.13:38:08.55$vck44/va=8,4 2006.173.13:38:08.55#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.13:38:08.55#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.13:38:08.55#ibcon#ireg 11 cls_cnt 2 2006.173.13:38:08.55#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.13:38:08.61#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.13:38:08.61#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.13:38:08.61#ibcon#enter wrdev, iclass 16, count 2 2006.173.13:38:08.61#ibcon#first serial, iclass 16, count 2 2006.173.13:38:08.61#ibcon#enter sib2, iclass 16, count 2 2006.173.13:38:08.61#ibcon#flushed, iclass 16, count 2 2006.173.13:38:08.61#ibcon#about to write, iclass 16, count 2 2006.173.13:38:08.61#ibcon#wrote, iclass 16, count 2 2006.173.13:38:08.61#ibcon#about to read 3, iclass 16, count 2 2006.173.13:38:08.63#ibcon#read 3, iclass 16, count 2 2006.173.13:38:08.63#ibcon#about to read 4, iclass 16, count 2 2006.173.13:38:08.63#ibcon#read 4, iclass 16, count 2 2006.173.13:38:08.63#ibcon#about to read 5, iclass 16, count 2 2006.173.13:38:08.63#ibcon#read 5, iclass 16, count 2 2006.173.13:38:08.63#ibcon#about to read 6, iclass 16, count 2 2006.173.13:38:08.63#ibcon#read 6, iclass 16, count 2 2006.173.13:38:08.63#ibcon#end of sib2, iclass 16, count 2 2006.173.13:38:08.63#ibcon#*mode == 0, iclass 16, count 2 2006.173.13:38:08.63#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.13:38:08.63#ibcon#[25=AT08-04\r\n] 2006.173.13:38:08.63#ibcon#*before write, iclass 16, count 2 2006.173.13:38:08.63#ibcon#enter sib2, iclass 16, count 2 2006.173.13:38:08.63#ibcon#flushed, iclass 16, count 2 2006.173.13:38:08.63#ibcon#about to write, iclass 16, count 2 2006.173.13:38:08.63#ibcon#wrote, iclass 16, count 2 2006.173.13:38:08.63#ibcon#about to read 3, iclass 16, count 2 2006.173.13:38:08.66#ibcon#read 3, iclass 16, count 2 2006.173.13:38:08.66#ibcon#about to read 4, iclass 16, count 2 2006.173.13:38:08.66#ibcon#read 4, iclass 16, count 2 2006.173.13:38:08.66#ibcon#about to read 5, iclass 16, count 2 2006.173.13:38:08.66#ibcon#read 5, iclass 16, count 2 2006.173.13:38:08.66#ibcon#about to read 6, iclass 16, count 2 2006.173.13:38:08.66#ibcon#read 6, iclass 16, count 2 2006.173.13:38:08.66#ibcon#end of sib2, iclass 16, count 2 2006.173.13:38:08.66#ibcon#*after write, iclass 16, count 2 2006.173.13:38:08.66#ibcon#*before return 0, iclass 16, count 2 2006.173.13:38:08.66#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.13:38:08.66#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.13:38:08.66#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.13:38:08.66#ibcon#ireg 7 cls_cnt 0 2006.173.13:38:08.66#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.13:38:08.78#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.13:38:08.78#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.13:38:08.78#ibcon#enter wrdev, iclass 16, count 0 2006.173.13:38:08.78#ibcon#first serial, iclass 16, count 0 2006.173.13:38:08.78#ibcon#enter sib2, iclass 16, count 0 2006.173.13:38:08.78#ibcon#flushed, iclass 16, count 0 2006.173.13:38:08.78#ibcon#about to write, iclass 16, count 0 2006.173.13:38:08.78#ibcon#wrote, iclass 16, count 0 2006.173.13:38:08.78#ibcon#about to read 3, iclass 16, count 0 2006.173.13:38:08.80#ibcon#read 3, iclass 16, count 0 2006.173.13:38:08.80#ibcon#about to read 4, iclass 16, count 0 2006.173.13:38:08.80#ibcon#read 4, iclass 16, count 0 2006.173.13:38:08.80#ibcon#about to read 5, iclass 16, count 0 2006.173.13:38:08.80#ibcon#read 5, iclass 16, count 0 2006.173.13:38:08.80#ibcon#about to read 6, iclass 16, count 0 2006.173.13:38:08.80#ibcon#read 6, iclass 16, count 0 2006.173.13:38:08.80#ibcon#end of sib2, iclass 16, count 0 2006.173.13:38:08.80#ibcon#*mode == 0, iclass 16, count 0 2006.173.13:38:08.80#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.13:38:08.80#ibcon#[25=USB\r\n] 2006.173.13:38:08.80#ibcon#*before write, iclass 16, count 0 2006.173.13:38:08.80#ibcon#enter sib2, iclass 16, count 0 2006.173.13:38:08.80#ibcon#flushed, iclass 16, count 0 2006.173.13:38:08.80#ibcon#about to write, iclass 16, count 0 2006.173.13:38:08.80#ibcon#wrote, iclass 16, count 0 2006.173.13:38:08.80#ibcon#about to read 3, iclass 16, count 0 2006.173.13:38:08.83#ibcon#read 3, iclass 16, count 0 2006.173.13:38:08.83#ibcon#about to read 4, iclass 16, count 0 2006.173.13:38:08.83#ibcon#read 4, iclass 16, count 0 2006.173.13:38:08.83#ibcon#about to read 5, iclass 16, count 0 2006.173.13:38:08.83#ibcon#read 5, iclass 16, count 0 2006.173.13:38:08.83#ibcon#about to read 6, iclass 16, count 0 2006.173.13:38:08.83#ibcon#read 6, iclass 16, count 0 2006.173.13:38:08.83#ibcon#end of sib2, iclass 16, count 0 2006.173.13:38:08.83#ibcon#*after write, iclass 16, count 0 2006.173.13:38:08.83#ibcon#*before return 0, iclass 16, count 0 2006.173.13:38:08.83#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.13:38:08.83#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.13:38:08.83#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.13:38:08.83#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.13:38:08.83$vck44/vblo=1,629.99 2006.173.13:38:08.83#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.13:38:08.83#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.13:38:08.83#ibcon#ireg 17 cls_cnt 0 2006.173.13:38:08.83#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.13:38:08.83#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.13:38:08.83#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.13:38:08.83#ibcon#enter wrdev, iclass 18, count 0 2006.173.13:38:08.83#ibcon#first serial, iclass 18, count 0 2006.173.13:38:08.83#ibcon#enter sib2, iclass 18, count 0 2006.173.13:38:08.83#ibcon#flushed, iclass 18, count 0 2006.173.13:38:08.83#ibcon#about to write, iclass 18, count 0 2006.173.13:38:08.83#ibcon#wrote, iclass 18, count 0 2006.173.13:38:08.83#ibcon#about to read 3, iclass 18, count 0 2006.173.13:38:08.85#ibcon#read 3, iclass 18, count 0 2006.173.13:38:08.85#ibcon#about to read 4, iclass 18, count 0 2006.173.13:38:08.85#ibcon#read 4, iclass 18, count 0 2006.173.13:38:08.85#ibcon#about to read 5, iclass 18, count 0 2006.173.13:38:08.85#ibcon#read 5, iclass 18, count 0 2006.173.13:38:08.85#ibcon#about to read 6, iclass 18, count 0 2006.173.13:38:08.85#ibcon#read 6, iclass 18, count 0 2006.173.13:38:08.85#ibcon#end of sib2, iclass 18, count 0 2006.173.13:38:08.85#ibcon#*mode == 0, iclass 18, count 0 2006.173.13:38:08.85#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.13:38:08.85#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.13:38:08.85#ibcon#*before write, iclass 18, count 0 2006.173.13:38:08.85#ibcon#enter sib2, iclass 18, count 0 2006.173.13:38:08.85#ibcon#flushed, iclass 18, count 0 2006.173.13:38:08.85#ibcon#about to write, iclass 18, count 0 2006.173.13:38:08.85#ibcon#wrote, iclass 18, count 0 2006.173.13:38:08.85#ibcon#about to read 3, iclass 18, count 0 2006.173.13:38:08.89#ibcon#read 3, iclass 18, count 0 2006.173.13:38:08.89#ibcon#about to read 4, iclass 18, count 0 2006.173.13:38:08.89#ibcon#read 4, iclass 18, count 0 2006.173.13:38:08.89#ibcon#about to read 5, iclass 18, count 0 2006.173.13:38:08.89#ibcon#read 5, iclass 18, count 0 2006.173.13:38:08.89#ibcon#about to read 6, iclass 18, count 0 2006.173.13:38:08.89#ibcon#read 6, iclass 18, count 0 2006.173.13:38:08.89#ibcon#end of sib2, iclass 18, count 0 2006.173.13:38:08.89#ibcon#*after write, iclass 18, count 0 2006.173.13:38:08.89#ibcon#*before return 0, iclass 18, count 0 2006.173.13:38:08.89#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.13:38:08.89#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.13:38:08.89#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.13:38:08.89#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.13:38:08.89$vck44/vb=1,4 2006.173.13:38:08.89#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.13:38:08.89#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.13:38:08.89#ibcon#ireg 11 cls_cnt 2 2006.173.13:38:08.89#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.13:38:08.89#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.13:38:08.89#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.13:38:08.89#ibcon#enter wrdev, iclass 20, count 2 2006.173.13:38:08.89#ibcon#first serial, iclass 20, count 2 2006.173.13:38:08.89#ibcon#enter sib2, iclass 20, count 2 2006.173.13:38:08.89#ibcon#flushed, iclass 20, count 2 2006.173.13:38:08.89#ibcon#about to write, iclass 20, count 2 2006.173.13:38:08.89#ibcon#wrote, iclass 20, count 2 2006.173.13:38:08.89#ibcon#about to read 3, iclass 20, count 2 2006.173.13:38:08.91#ibcon#read 3, iclass 20, count 2 2006.173.13:38:08.91#ibcon#about to read 4, iclass 20, count 2 2006.173.13:38:08.91#ibcon#read 4, iclass 20, count 2 2006.173.13:38:08.91#ibcon#about to read 5, iclass 20, count 2 2006.173.13:38:08.91#ibcon#read 5, iclass 20, count 2 2006.173.13:38:08.91#ibcon#about to read 6, iclass 20, count 2 2006.173.13:38:08.91#ibcon#read 6, iclass 20, count 2 2006.173.13:38:08.91#ibcon#end of sib2, iclass 20, count 2 2006.173.13:38:08.91#ibcon#*mode == 0, iclass 20, count 2 2006.173.13:38:08.91#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.13:38:08.91#ibcon#[27=AT01-04\r\n] 2006.173.13:38:08.91#ibcon#*before write, iclass 20, count 2 2006.173.13:38:08.91#ibcon#enter sib2, iclass 20, count 2 2006.173.13:38:08.91#ibcon#flushed, iclass 20, count 2 2006.173.13:38:08.91#ibcon#about to write, iclass 20, count 2 2006.173.13:38:08.91#ibcon#wrote, iclass 20, count 2 2006.173.13:38:08.91#ibcon#about to read 3, iclass 20, count 2 2006.173.13:38:08.94#ibcon#read 3, iclass 20, count 2 2006.173.13:38:08.94#ibcon#about to read 4, iclass 20, count 2 2006.173.13:38:08.94#ibcon#read 4, iclass 20, count 2 2006.173.13:38:08.94#ibcon#about to read 5, iclass 20, count 2 2006.173.13:38:08.94#ibcon#read 5, iclass 20, count 2 2006.173.13:38:08.94#ibcon#about to read 6, iclass 20, count 2 2006.173.13:38:08.94#ibcon#read 6, iclass 20, count 2 2006.173.13:38:08.94#ibcon#end of sib2, iclass 20, count 2 2006.173.13:38:08.94#ibcon#*after write, iclass 20, count 2 2006.173.13:38:08.94#ibcon#*before return 0, iclass 20, count 2 2006.173.13:38:08.94#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.13:38:08.94#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.13:38:08.94#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.13:38:08.94#ibcon#ireg 7 cls_cnt 0 2006.173.13:38:08.94#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.13:38:09.06#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.13:38:09.06#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.13:38:09.06#ibcon#enter wrdev, iclass 20, count 0 2006.173.13:38:09.06#ibcon#first serial, iclass 20, count 0 2006.173.13:38:09.06#ibcon#enter sib2, iclass 20, count 0 2006.173.13:38:09.06#ibcon#flushed, iclass 20, count 0 2006.173.13:38:09.06#ibcon#about to write, iclass 20, count 0 2006.173.13:38:09.06#ibcon#wrote, iclass 20, count 0 2006.173.13:38:09.06#ibcon#about to read 3, iclass 20, count 0 2006.173.13:38:09.08#ibcon#read 3, iclass 20, count 0 2006.173.13:38:09.08#ibcon#about to read 4, iclass 20, count 0 2006.173.13:38:09.08#ibcon#read 4, iclass 20, count 0 2006.173.13:38:09.08#ibcon#about to read 5, iclass 20, count 0 2006.173.13:38:09.08#ibcon#read 5, iclass 20, count 0 2006.173.13:38:09.08#ibcon#about to read 6, iclass 20, count 0 2006.173.13:38:09.08#ibcon#read 6, iclass 20, count 0 2006.173.13:38:09.08#ibcon#end of sib2, iclass 20, count 0 2006.173.13:38:09.08#ibcon#*mode == 0, iclass 20, count 0 2006.173.13:38:09.08#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.13:38:09.08#ibcon#[27=USB\r\n] 2006.173.13:38:09.08#ibcon#*before write, iclass 20, count 0 2006.173.13:38:09.08#ibcon#enter sib2, iclass 20, count 0 2006.173.13:38:09.08#ibcon#flushed, iclass 20, count 0 2006.173.13:38:09.08#ibcon#about to write, iclass 20, count 0 2006.173.13:38:09.08#ibcon#wrote, iclass 20, count 0 2006.173.13:38:09.08#ibcon#about to read 3, iclass 20, count 0 2006.173.13:38:09.11#ibcon#read 3, iclass 20, count 0 2006.173.13:38:09.11#ibcon#about to read 4, iclass 20, count 0 2006.173.13:38:09.11#ibcon#read 4, iclass 20, count 0 2006.173.13:38:09.11#ibcon#about to read 5, iclass 20, count 0 2006.173.13:38:09.11#ibcon#read 5, iclass 20, count 0 2006.173.13:38:09.11#ibcon#about to read 6, iclass 20, count 0 2006.173.13:38:09.11#ibcon#read 6, iclass 20, count 0 2006.173.13:38:09.11#ibcon#end of sib2, iclass 20, count 0 2006.173.13:38:09.11#ibcon#*after write, iclass 20, count 0 2006.173.13:38:09.11#ibcon#*before return 0, iclass 20, count 0 2006.173.13:38:09.11#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.13:38:09.11#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.13:38:09.11#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.13:38:09.11#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.13:38:09.11$vck44/vblo=2,634.99 2006.173.13:38:09.11#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.13:38:09.11#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.13:38:09.11#ibcon#ireg 17 cls_cnt 0 2006.173.13:38:09.11#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.13:38:09.11#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.13:38:09.11#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.13:38:09.11#ibcon#enter wrdev, iclass 22, count 0 2006.173.13:38:09.11#ibcon#first serial, iclass 22, count 0 2006.173.13:38:09.11#ibcon#enter sib2, iclass 22, count 0 2006.173.13:38:09.11#ibcon#flushed, iclass 22, count 0 2006.173.13:38:09.11#ibcon#about to write, iclass 22, count 0 2006.173.13:38:09.11#ibcon#wrote, iclass 22, count 0 2006.173.13:38:09.11#ibcon#about to read 3, iclass 22, count 0 2006.173.13:38:09.13#ibcon#read 3, iclass 22, count 0 2006.173.13:38:09.13#ibcon#about to read 4, iclass 22, count 0 2006.173.13:38:09.13#ibcon#read 4, iclass 22, count 0 2006.173.13:38:09.13#ibcon#about to read 5, iclass 22, count 0 2006.173.13:38:09.13#ibcon#read 5, iclass 22, count 0 2006.173.13:38:09.13#ibcon#about to read 6, iclass 22, count 0 2006.173.13:38:09.13#ibcon#read 6, iclass 22, count 0 2006.173.13:38:09.13#ibcon#end of sib2, iclass 22, count 0 2006.173.13:38:09.13#ibcon#*mode == 0, iclass 22, count 0 2006.173.13:38:09.13#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.13:38:09.13#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.13:38:09.13#ibcon#*before write, iclass 22, count 0 2006.173.13:38:09.13#ibcon#enter sib2, iclass 22, count 0 2006.173.13:38:09.13#ibcon#flushed, iclass 22, count 0 2006.173.13:38:09.13#ibcon#about to write, iclass 22, count 0 2006.173.13:38:09.13#ibcon#wrote, iclass 22, count 0 2006.173.13:38:09.13#ibcon#about to read 3, iclass 22, count 0 2006.173.13:38:09.17#ibcon#read 3, iclass 22, count 0 2006.173.13:38:09.17#ibcon#about to read 4, iclass 22, count 0 2006.173.13:38:09.17#ibcon#read 4, iclass 22, count 0 2006.173.13:38:09.17#ibcon#about to read 5, iclass 22, count 0 2006.173.13:38:09.17#ibcon#read 5, iclass 22, count 0 2006.173.13:38:09.17#ibcon#about to read 6, iclass 22, count 0 2006.173.13:38:09.17#ibcon#read 6, iclass 22, count 0 2006.173.13:38:09.17#ibcon#end of sib2, iclass 22, count 0 2006.173.13:38:09.17#ibcon#*after write, iclass 22, count 0 2006.173.13:38:09.17#ibcon#*before return 0, iclass 22, count 0 2006.173.13:38:09.17#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.13:38:09.17#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.13:38:09.17#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.13:38:09.17#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.13:38:09.17$vck44/vb=2,4 2006.173.13:38:09.17#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.13:38:09.17#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.13:38:09.17#ibcon#ireg 11 cls_cnt 2 2006.173.13:38:09.17#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.13:38:09.23#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.13:38:09.23#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.13:38:09.23#ibcon#enter wrdev, iclass 24, count 2 2006.173.13:38:09.23#ibcon#first serial, iclass 24, count 2 2006.173.13:38:09.23#ibcon#enter sib2, iclass 24, count 2 2006.173.13:38:09.23#ibcon#flushed, iclass 24, count 2 2006.173.13:38:09.23#ibcon#about to write, iclass 24, count 2 2006.173.13:38:09.23#ibcon#wrote, iclass 24, count 2 2006.173.13:38:09.23#ibcon#about to read 3, iclass 24, count 2 2006.173.13:38:09.25#ibcon#read 3, iclass 24, count 2 2006.173.13:38:09.25#ibcon#about to read 4, iclass 24, count 2 2006.173.13:38:09.25#ibcon#read 4, iclass 24, count 2 2006.173.13:38:09.25#ibcon#about to read 5, iclass 24, count 2 2006.173.13:38:09.25#ibcon#read 5, iclass 24, count 2 2006.173.13:38:09.25#ibcon#about to read 6, iclass 24, count 2 2006.173.13:38:09.25#ibcon#read 6, iclass 24, count 2 2006.173.13:38:09.25#ibcon#end of sib2, iclass 24, count 2 2006.173.13:38:09.25#ibcon#*mode == 0, iclass 24, count 2 2006.173.13:38:09.25#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.13:38:09.25#ibcon#[27=AT02-04\r\n] 2006.173.13:38:09.25#ibcon#*before write, iclass 24, count 2 2006.173.13:38:09.25#ibcon#enter sib2, iclass 24, count 2 2006.173.13:38:09.25#ibcon#flushed, iclass 24, count 2 2006.173.13:38:09.25#ibcon#about to write, iclass 24, count 2 2006.173.13:38:09.25#ibcon#wrote, iclass 24, count 2 2006.173.13:38:09.25#ibcon#about to read 3, iclass 24, count 2 2006.173.13:38:09.28#ibcon#read 3, iclass 24, count 2 2006.173.13:38:09.28#ibcon#about to read 4, iclass 24, count 2 2006.173.13:38:09.28#ibcon#read 4, iclass 24, count 2 2006.173.13:38:09.28#ibcon#about to read 5, iclass 24, count 2 2006.173.13:38:09.28#ibcon#read 5, iclass 24, count 2 2006.173.13:38:09.28#ibcon#about to read 6, iclass 24, count 2 2006.173.13:38:09.28#ibcon#read 6, iclass 24, count 2 2006.173.13:38:09.28#ibcon#end of sib2, iclass 24, count 2 2006.173.13:38:09.28#ibcon#*after write, iclass 24, count 2 2006.173.13:38:09.28#ibcon#*before return 0, iclass 24, count 2 2006.173.13:38:09.28#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.13:38:09.28#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.13:38:09.28#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.13:38:09.28#ibcon#ireg 7 cls_cnt 0 2006.173.13:38:09.28#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.13:38:09.40#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.13:38:09.40#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.13:38:09.40#ibcon#enter wrdev, iclass 24, count 0 2006.173.13:38:09.40#ibcon#first serial, iclass 24, count 0 2006.173.13:38:09.40#ibcon#enter sib2, iclass 24, count 0 2006.173.13:38:09.40#ibcon#flushed, iclass 24, count 0 2006.173.13:38:09.40#ibcon#about to write, iclass 24, count 0 2006.173.13:38:09.40#ibcon#wrote, iclass 24, count 0 2006.173.13:38:09.40#ibcon#about to read 3, iclass 24, count 0 2006.173.13:38:09.42#ibcon#read 3, iclass 24, count 0 2006.173.13:38:09.42#ibcon#about to read 4, iclass 24, count 0 2006.173.13:38:09.42#ibcon#read 4, iclass 24, count 0 2006.173.13:38:09.42#ibcon#about to read 5, iclass 24, count 0 2006.173.13:38:09.42#ibcon#read 5, iclass 24, count 0 2006.173.13:38:09.42#ibcon#about to read 6, iclass 24, count 0 2006.173.13:38:09.42#ibcon#read 6, iclass 24, count 0 2006.173.13:38:09.42#ibcon#end of sib2, iclass 24, count 0 2006.173.13:38:09.42#ibcon#*mode == 0, iclass 24, count 0 2006.173.13:38:09.42#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.13:38:09.42#ibcon#[27=USB\r\n] 2006.173.13:38:09.42#ibcon#*before write, iclass 24, count 0 2006.173.13:38:09.42#ibcon#enter sib2, iclass 24, count 0 2006.173.13:38:09.42#ibcon#flushed, iclass 24, count 0 2006.173.13:38:09.42#ibcon#about to write, iclass 24, count 0 2006.173.13:38:09.42#ibcon#wrote, iclass 24, count 0 2006.173.13:38:09.42#ibcon#about to read 3, iclass 24, count 0 2006.173.13:38:09.45#ibcon#read 3, iclass 24, count 0 2006.173.13:38:09.45#ibcon#about to read 4, iclass 24, count 0 2006.173.13:38:09.45#ibcon#read 4, iclass 24, count 0 2006.173.13:38:09.45#ibcon#about to read 5, iclass 24, count 0 2006.173.13:38:09.45#ibcon#read 5, iclass 24, count 0 2006.173.13:38:09.45#ibcon#about to read 6, iclass 24, count 0 2006.173.13:38:09.45#ibcon#read 6, iclass 24, count 0 2006.173.13:38:09.45#ibcon#end of sib2, iclass 24, count 0 2006.173.13:38:09.45#ibcon#*after write, iclass 24, count 0 2006.173.13:38:09.45#ibcon#*before return 0, iclass 24, count 0 2006.173.13:38:09.45#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.13:38:09.45#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.13:38:09.45#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.13:38:09.45#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.13:38:09.45$vck44/vblo=3,649.99 2006.173.13:38:09.45#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.13:38:09.45#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.13:38:09.45#ibcon#ireg 17 cls_cnt 0 2006.173.13:38:09.45#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.13:38:09.45#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.13:38:09.45#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.13:38:09.45#ibcon#enter wrdev, iclass 26, count 0 2006.173.13:38:09.45#ibcon#first serial, iclass 26, count 0 2006.173.13:38:09.45#ibcon#enter sib2, iclass 26, count 0 2006.173.13:38:09.45#ibcon#flushed, iclass 26, count 0 2006.173.13:38:09.45#ibcon#about to write, iclass 26, count 0 2006.173.13:38:09.45#ibcon#wrote, iclass 26, count 0 2006.173.13:38:09.45#ibcon#about to read 3, iclass 26, count 0 2006.173.13:38:09.47#ibcon#read 3, iclass 26, count 0 2006.173.13:38:09.47#ibcon#about to read 4, iclass 26, count 0 2006.173.13:38:09.47#ibcon#read 4, iclass 26, count 0 2006.173.13:38:09.47#ibcon#about to read 5, iclass 26, count 0 2006.173.13:38:09.47#ibcon#read 5, iclass 26, count 0 2006.173.13:38:09.47#ibcon#about to read 6, iclass 26, count 0 2006.173.13:38:09.47#ibcon#read 6, iclass 26, count 0 2006.173.13:38:09.47#ibcon#end of sib2, iclass 26, count 0 2006.173.13:38:09.47#ibcon#*mode == 0, iclass 26, count 0 2006.173.13:38:09.47#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.13:38:09.47#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.13:38:09.47#ibcon#*before write, iclass 26, count 0 2006.173.13:38:09.47#ibcon#enter sib2, iclass 26, count 0 2006.173.13:38:09.47#ibcon#flushed, iclass 26, count 0 2006.173.13:38:09.47#ibcon#about to write, iclass 26, count 0 2006.173.13:38:09.47#ibcon#wrote, iclass 26, count 0 2006.173.13:38:09.47#ibcon#about to read 3, iclass 26, count 0 2006.173.13:38:09.51#ibcon#read 3, iclass 26, count 0 2006.173.13:38:09.51#ibcon#about to read 4, iclass 26, count 0 2006.173.13:38:09.51#ibcon#read 4, iclass 26, count 0 2006.173.13:38:09.51#ibcon#about to read 5, iclass 26, count 0 2006.173.13:38:09.51#ibcon#read 5, iclass 26, count 0 2006.173.13:38:09.51#ibcon#about to read 6, iclass 26, count 0 2006.173.13:38:09.51#ibcon#read 6, iclass 26, count 0 2006.173.13:38:09.51#ibcon#end of sib2, iclass 26, count 0 2006.173.13:38:09.51#ibcon#*after write, iclass 26, count 0 2006.173.13:38:09.51#ibcon#*before return 0, iclass 26, count 0 2006.173.13:38:09.51#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.13:38:09.51#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.13:38:09.51#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.13:38:09.51#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.13:38:09.51$vck44/vb=3,4 2006.173.13:38:09.51#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.13:38:09.51#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.13:38:09.51#ibcon#ireg 11 cls_cnt 2 2006.173.13:38:09.51#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.13:38:09.57#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.13:38:09.57#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.13:38:09.57#ibcon#enter wrdev, iclass 28, count 2 2006.173.13:38:09.57#ibcon#first serial, iclass 28, count 2 2006.173.13:38:09.57#ibcon#enter sib2, iclass 28, count 2 2006.173.13:38:09.57#ibcon#flushed, iclass 28, count 2 2006.173.13:38:09.57#ibcon#about to write, iclass 28, count 2 2006.173.13:38:09.57#ibcon#wrote, iclass 28, count 2 2006.173.13:38:09.57#ibcon#about to read 3, iclass 28, count 2 2006.173.13:38:09.59#ibcon#read 3, iclass 28, count 2 2006.173.13:38:09.59#ibcon#about to read 4, iclass 28, count 2 2006.173.13:38:09.59#ibcon#read 4, iclass 28, count 2 2006.173.13:38:09.59#ibcon#about to read 5, iclass 28, count 2 2006.173.13:38:09.59#ibcon#read 5, iclass 28, count 2 2006.173.13:38:09.59#ibcon#about to read 6, iclass 28, count 2 2006.173.13:38:09.59#ibcon#read 6, iclass 28, count 2 2006.173.13:38:09.59#ibcon#end of sib2, iclass 28, count 2 2006.173.13:38:09.59#ibcon#*mode == 0, iclass 28, count 2 2006.173.13:38:09.59#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.13:38:09.59#ibcon#[27=AT03-04\r\n] 2006.173.13:38:09.59#ibcon#*before write, iclass 28, count 2 2006.173.13:38:09.59#ibcon#enter sib2, iclass 28, count 2 2006.173.13:38:09.59#ibcon#flushed, iclass 28, count 2 2006.173.13:38:09.59#ibcon#about to write, iclass 28, count 2 2006.173.13:38:09.59#ibcon#wrote, iclass 28, count 2 2006.173.13:38:09.59#ibcon#about to read 3, iclass 28, count 2 2006.173.13:38:09.62#ibcon#read 3, iclass 28, count 2 2006.173.13:38:09.62#ibcon#about to read 4, iclass 28, count 2 2006.173.13:38:09.62#ibcon#read 4, iclass 28, count 2 2006.173.13:38:09.62#ibcon#about to read 5, iclass 28, count 2 2006.173.13:38:09.62#ibcon#read 5, iclass 28, count 2 2006.173.13:38:09.62#ibcon#about to read 6, iclass 28, count 2 2006.173.13:38:09.62#ibcon#read 6, iclass 28, count 2 2006.173.13:38:09.62#ibcon#end of sib2, iclass 28, count 2 2006.173.13:38:09.62#ibcon#*after write, iclass 28, count 2 2006.173.13:38:09.62#ibcon#*before return 0, iclass 28, count 2 2006.173.13:38:09.62#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.13:38:09.62#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.13:38:09.62#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.13:38:09.62#ibcon#ireg 7 cls_cnt 0 2006.173.13:38:09.62#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.13:38:09.74#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.13:38:09.74#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.13:38:09.74#ibcon#enter wrdev, iclass 28, count 0 2006.173.13:38:09.74#ibcon#first serial, iclass 28, count 0 2006.173.13:38:09.74#ibcon#enter sib2, iclass 28, count 0 2006.173.13:38:09.74#ibcon#flushed, iclass 28, count 0 2006.173.13:38:09.74#ibcon#about to write, iclass 28, count 0 2006.173.13:38:09.74#ibcon#wrote, iclass 28, count 0 2006.173.13:38:09.74#ibcon#about to read 3, iclass 28, count 0 2006.173.13:38:09.76#ibcon#read 3, iclass 28, count 0 2006.173.13:38:09.76#ibcon#about to read 4, iclass 28, count 0 2006.173.13:38:09.76#ibcon#read 4, iclass 28, count 0 2006.173.13:38:09.76#ibcon#about to read 5, iclass 28, count 0 2006.173.13:38:09.76#ibcon#read 5, iclass 28, count 0 2006.173.13:38:09.76#ibcon#about to read 6, iclass 28, count 0 2006.173.13:38:09.76#ibcon#read 6, iclass 28, count 0 2006.173.13:38:09.76#ibcon#end of sib2, iclass 28, count 0 2006.173.13:38:09.76#ibcon#*mode == 0, iclass 28, count 0 2006.173.13:38:09.76#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.13:38:09.76#ibcon#[27=USB\r\n] 2006.173.13:38:09.76#ibcon#*before write, iclass 28, count 0 2006.173.13:38:09.76#ibcon#enter sib2, iclass 28, count 0 2006.173.13:38:09.76#ibcon#flushed, iclass 28, count 0 2006.173.13:38:09.76#ibcon#about to write, iclass 28, count 0 2006.173.13:38:09.76#ibcon#wrote, iclass 28, count 0 2006.173.13:38:09.76#ibcon#about to read 3, iclass 28, count 0 2006.173.13:38:09.79#ibcon#read 3, iclass 28, count 0 2006.173.13:38:09.79#ibcon#about to read 4, iclass 28, count 0 2006.173.13:38:09.79#ibcon#read 4, iclass 28, count 0 2006.173.13:38:09.79#ibcon#about to read 5, iclass 28, count 0 2006.173.13:38:09.79#ibcon#read 5, iclass 28, count 0 2006.173.13:38:09.79#ibcon#about to read 6, iclass 28, count 0 2006.173.13:38:09.79#ibcon#read 6, iclass 28, count 0 2006.173.13:38:09.79#ibcon#end of sib2, iclass 28, count 0 2006.173.13:38:09.79#ibcon#*after write, iclass 28, count 0 2006.173.13:38:09.79#ibcon#*before return 0, iclass 28, count 0 2006.173.13:38:09.79#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.13:38:09.79#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.13:38:09.79#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.13:38:09.79#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.13:38:09.79$vck44/vblo=4,679.99 2006.173.13:38:09.79#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.13:38:09.79#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.13:38:09.79#ibcon#ireg 17 cls_cnt 0 2006.173.13:38:09.79#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.13:38:09.79#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.13:38:09.79#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.13:38:09.79#ibcon#enter wrdev, iclass 30, count 0 2006.173.13:38:09.79#ibcon#first serial, iclass 30, count 0 2006.173.13:38:09.79#ibcon#enter sib2, iclass 30, count 0 2006.173.13:38:09.79#ibcon#flushed, iclass 30, count 0 2006.173.13:38:09.79#ibcon#about to write, iclass 30, count 0 2006.173.13:38:09.79#ibcon#wrote, iclass 30, count 0 2006.173.13:38:09.79#ibcon#about to read 3, iclass 30, count 0 2006.173.13:38:09.81#ibcon#read 3, iclass 30, count 0 2006.173.13:38:09.81#ibcon#about to read 4, iclass 30, count 0 2006.173.13:38:09.81#ibcon#read 4, iclass 30, count 0 2006.173.13:38:09.81#ibcon#about to read 5, iclass 30, count 0 2006.173.13:38:09.81#ibcon#read 5, iclass 30, count 0 2006.173.13:38:09.81#ibcon#about to read 6, iclass 30, count 0 2006.173.13:38:09.81#ibcon#read 6, iclass 30, count 0 2006.173.13:38:09.81#ibcon#end of sib2, iclass 30, count 0 2006.173.13:38:09.81#ibcon#*mode == 0, iclass 30, count 0 2006.173.13:38:09.81#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.13:38:09.81#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.13:38:09.81#ibcon#*before write, iclass 30, count 0 2006.173.13:38:09.81#ibcon#enter sib2, iclass 30, count 0 2006.173.13:38:09.81#ibcon#flushed, iclass 30, count 0 2006.173.13:38:09.81#ibcon#about to write, iclass 30, count 0 2006.173.13:38:09.81#ibcon#wrote, iclass 30, count 0 2006.173.13:38:09.81#ibcon#about to read 3, iclass 30, count 0 2006.173.13:38:09.85#ibcon#read 3, iclass 30, count 0 2006.173.13:38:09.85#ibcon#about to read 4, iclass 30, count 0 2006.173.13:38:09.85#ibcon#read 4, iclass 30, count 0 2006.173.13:38:09.85#ibcon#about to read 5, iclass 30, count 0 2006.173.13:38:09.85#ibcon#read 5, iclass 30, count 0 2006.173.13:38:09.85#ibcon#about to read 6, iclass 30, count 0 2006.173.13:38:09.85#ibcon#read 6, iclass 30, count 0 2006.173.13:38:09.85#ibcon#end of sib2, iclass 30, count 0 2006.173.13:38:09.85#ibcon#*after write, iclass 30, count 0 2006.173.13:38:09.85#ibcon#*before return 0, iclass 30, count 0 2006.173.13:38:09.85#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.13:38:09.85#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.13:38:09.85#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.13:38:09.85#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.13:38:09.85$vck44/vb=4,4 2006.173.13:38:09.85#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.173.13:38:09.85#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.173.13:38:09.85#ibcon#ireg 11 cls_cnt 2 2006.173.13:38:09.85#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.13:38:09.91#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.13:38:09.91#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.13:38:09.91#ibcon#enter wrdev, iclass 32, count 2 2006.173.13:38:09.91#ibcon#first serial, iclass 32, count 2 2006.173.13:38:09.91#ibcon#enter sib2, iclass 32, count 2 2006.173.13:38:09.91#ibcon#flushed, iclass 32, count 2 2006.173.13:38:09.91#ibcon#about to write, iclass 32, count 2 2006.173.13:38:09.91#ibcon#wrote, iclass 32, count 2 2006.173.13:38:09.91#ibcon#about to read 3, iclass 32, count 2 2006.173.13:38:09.93#ibcon#read 3, iclass 32, count 2 2006.173.13:38:09.93#ibcon#about to read 4, iclass 32, count 2 2006.173.13:38:09.93#ibcon#read 4, iclass 32, count 2 2006.173.13:38:09.93#ibcon#about to read 5, iclass 32, count 2 2006.173.13:38:09.93#ibcon#read 5, iclass 32, count 2 2006.173.13:38:09.93#ibcon#about to read 6, iclass 32, count 2 2006.173.13:38:09.93#ibcon#read 6, iclass 32, count 2 2006.173.13:38:09.93#ibcon#end of sib2, iclass 32, count 2 2006.173.13:38:09.93#ibcon#*mode == 0, iclass 32, count 2 2006.173.13:38:09.93#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.173.13:38:09.93#ibcon#[27=AT04-04\r\n] 2006.173.13:38:09.93#ibcon#*before write, iclass 32, count 2 2006.173.13:38:09.93#ibcon#enter sib2, iclass 32, count 2 2006.173.13:38:09.93#ibcon#flushed, iclass 32, count 2 2006.173.13:38:09.93#ibcon#about to write, iclass 32, count 2 2006.173.13:38:09.93#ibcon#wrote, iclass 32, count 2 2006.173.13:38:09.93#ibcon#about to read 3, iclass 32, count 2 2006.173.13:38:09.96#ibcon#read 3, iclass 32, count 2 2006.173.13:38:09.96#ibcon#about to read 4, iclass 32, count 2 2006.173.13:38:09.96#ibcon#read 4, iclass 32, count 2 2006.173.13:38:09.96#ibcon#about to read 5, iclass 32, count 2 2006.173.13:38:09.96#ibcon#read 5, iclass 32, count 2 2006.173.13:38:09.96#ibcon#about to read 6, iclass 32, count 2 2006.173.13:38:09.96#ibcon#read 6, iclass 32, count 2 2006.173.13:38:09.96#ibcon#end of sib2, iclass 32, count 2 2006.173.13:38:09.96#ibcon#*after write, iclass 32, count 2 2006.173.13:38:09.96#ibcon#*before return 0, iclass 32, count 2 2006.173.13:38:09.96#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.13:38:09.96#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.173.13:38:09.96#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.173.13:38:09.96#ibcon#ireg 7 cls_cnt 0 2006.173.13:38:09.96#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.13:38:10.08#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.13:38:10.08#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.13:38:10.08#ibcon#enter wrdev, iclass 32, count 0 2006.173.13:38:10.08#ibcon#first serial, iclass 32, count 0 2006.173.13:38:10.08#ibcon#enter sib2, iclass 32, count 0 2006.173.13:38:10.08#ibcon#flushed, iclass 32, count 0 2006.173.13:38:10.08#ibcon#about to write, iclass 32, count 0 2006.173.13:38:10.08#ibcon#wrote, iclass 32, count 0 2006.173.13:38:10.08#ibcon#about to read 3, iclass 32, count 0 2006.173.13:38:10.10#ibcon#read 3, iclass 32, count 0 2006.173.13:38:10.10#ibcon#about to read 4, iclass 32, count 0 2006.173.13:38:10.10#ibcon#read 4, iclass 32, count 0 2006.173.13:38:10.10#ibcon#about to read 5, iclass 32, count 0 2006.173.13:38:10.10#ibcon#read 5, iclass 32, count 0 2006.173.13:38:10.10#ibcon#about to read 6, iclass 32, count 0 2006.173.13:38:10.10#ibcon#read 6, iclass 32, count 0 2006.173.13:38:10.10#ibcon#end of sib2, iclass 32, count 0 2006.173.13:38:10.10#ibcon#*mode == 0, iclass 32, count 0 2006.173.13:38:10.10#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.13:38:10.10#ibcon#[27=USB\r\n] 2006.173.13:38:10.10#ibcon#*before write, iclass 32, count 0 2006.173.13:38:10.10#ibcon#enter sib2, iclass 32, count 0 2006.173.13:38:10.10#ibcon#flushed, iclass 32, count 0 2006.173.13:38:10.10#ibcon#about to write, iclass 32, count 0 2006.173.13:38:10.10#ibcon#wrote, iclass 32, count 0 2006.173.13:38:10.10#ibcon#about to read 3, iclass 32, count 0 2006.173.13:38:10.13#ibcon#read 3, iclass 32, count 0 2006.173.13:38:10.13#ibcon#about to read 4, iclass 32, count 0 2006.173.13:38:10.13#ibcon#read 4, iclass 32, count 0 2006.173.13:38:10.13#ibcon#about to read 5, iclass 32, count 0 2006.173.13:38:10.13#ibcon#read 5, iclass 32, count 0 2006.173.13:38:10.13#ibcon#about to read 6, iclass 32, count 0 2006.173.13:38:10.13#ibcon#read 6, iclass 32, count 0 2006.173.13:38:10.13#ibcon#end of sib2, iclass 32, count 0 2006.173.13:38:10.13#ibcon#*after write, iclass 32, count 0 2006.173.13:38:10.13#ibcon#*before return 0, iclass 32, count 0 2006.173.13:38:10.13#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.13:38:10.13#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.173.13:38:10.13#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.13:38:10.13#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.13:38:10.13$vck44/vblo=5,709.99 2006.173.13:38:10.13#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.13:38:10.13#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.13:38:10.13#ibcon#ireg 17 cls_cnt 0 2006.173.13:38:10.13#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.13:38:10.13#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.13:38:10.13#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.13:38:10.13#ibcon#enter wrdev, iclass 34, count 0 2006.173.13:38:10.13#ibcon#first serial, iclass 34, count 0 2006.173.13:38:10.13#ibcon#enter sib2, iclass 34, count 0 2006.173.13:38:10.13#ibcon#flushed, iclass 34, count 0 2006.173.13:38:10.13#ibcon#about to write, iclass 34, count 0 2006.173.13:38:10.13#ibcon#wrote, iclass 34, count 0 2006.173.13:38:10.13#ibcon#about to read 3, iclass 34, count 0 2006.173.13:38:10.15#ibcon#read 3, iclass 34, count 0 2006.173.13:38:10.15#ibcon#about to read 4, iclass 34, count 0 2006.173.13:38:10.15#ibcon#read 4, iclass 34, count 0 2006.173.13:38:10.15#ibcon#about to read 5, iclass 34, count 0 2006.173.13:38:10.15#ibcon#read 5, iclass 34, count 0 2006.173.13:38:10.15#ibcon#about to read 6, iclass 34, count 0 2006.173.13:38:10.15#ibcon#read 6, iclass 34, count 0 2006.173.13:38:10.15#ibcon#end of sib2, iclass 34, count 0 2006.173.13:38:10.15#ibcon#*mode == 0, iclass 34, count 0 2006.173.13:38:10.15#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.13:38:10.15#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.13:38:10.15#ibcon#*before write, iclass 34, count 0 2006.173.13:38:10.15#ibcon#enter sib2, iclass 34, count 0 2006.173.13:38:10.15#ibcon#flushed, iclass 34, count 0 2006.173.13:38:10.15#ibcon#about to write, iclass 34, count 0 2006.173.13:38:10.15#ibcon#wrote, iclass 34, count 0 2006.173.13:38:10.15#ibcon#about to read 3, iclass 34, count 0 2006.173.13:38:10.19#ibcon#read 3, iclass 34, count 0 2006.173.13:38:10.19#ibcon#about to read 4, iclass 34, count 0 2006.173.13:38:10.19#ibcon#read 4, iclass 34, count 0 2006.173.13:38:10.19#ibcon#about to read 5, iclass 34, count 0 2006.173.13:38:10.19#ibcon#read 5, iclass 34, count 0 2006.173.13:38:10.19#ibcon#about to read 6, iclass 34, count 0 2006.173.13:38:10.19#ibcon#read 6, iclass 34, count 0 2006.173.13:38:10.19#ibcon#end of sib2, iclass 34, count 0 2006.173.13:38:10.19#ibcon#*after write, iclass 34, count 0 2006.173.13:38:10.19#ibcon#*before return 0, iclass 34, count 0 2006.173.13:38:10.19#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.13:38:10.19#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.13:38:10.19#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.13:38:10.19#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.13:38:10.19$vck44/vb=5,4 2006.173.13:38:10.19#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.13:38:10.19#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.13:38:10.19#ibcon#ireg 11 cls_cnt 2 2006.173.13:38:10.19#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.13:38:10.25#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.13:38:10.25#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.13:38:10.25#ibcon#enter wrdev, iclass 36, count 2 2006.173.13:38:10.25#ibcon#first serial, iclass 36, count 2 2006.173.13:38:10.25#ibcon#enter sib2, iclass 36, count 2 2006.173.13:38:10.25#ibcon#flushed, iclass 36, count 2 2006.173.13:38:10.25#ibcon#about to write, iclass 36, count 2 2006.173.13:38:10.25#ibcon#wrote, iclass 36, count 2 2006.173.13:38:10.25#ibcon#about to read 3, iclass 36, count 2 2006.173.13:38:10.27#ibcon#read 3, iclass 36, count 2 2006.173.13:38:10.27#ibcon#about to read 4, iclass 36, count 2 2006.173.13:38:10.27#ibcon#read 4, iclass 36, count 2 2006.173.13:38:10.27#ibcon#about to read 5, iclass 36, count 2 2006.173.13:38:10.27#ibcon#read 5, iclass 36, count 2 2006.173.13:38:10.27#ibcon#about to read 6, iclass 36, count 2 2006.173.13:38:10.27#ibcon#read 6, iclass 36, count 2 2006.173.13:38:10.27#ibcon#end of sib2, iclass 36, count 2 2006.173.13:38:10.27#ibcon#*mode == 0, iclass 36, count 2 2006.173.13:38:10.27#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.13:38:10.27#ibcon#[27=AT05-04\r\n] 2006.173.13:38:10.27#ibcon#*before write, iclass 36, count 2 2006.173.13:38:10.27#ibcon#enter sib2, iclass 36, count 2 2006.173.13:38:10.27#ibcon#flushed, iclass 36, count 2 2006.173.13:38:10.27#ibcon#about to write, iclass 36, count 2 2006.173.13:38:10.27#ibcon#wrote, iclass 36, count 2 2006.173.13:38:10.27#ibcon#about to read 3, iclass 36, count 2 2006.173.13:38:10.30#ibcon#read 3, iclass 36, count 2 2006.173.13:38:10.30#ibcon#about to read 4, iclass 36, count 2 2006.173.13:38:10.30#ibcon#read 4, iclass 36, count 2 2006.173.13:38:10.30#ibcon#about to read 5, iclass 36, count 2 2006.173.13:38:10.30#ibcon#read 5, iclass 36, count 2 2006.173.13:38:10.30#ibcon#about to read 6, iclass 36, count 2 2006.173.13:38:10.30#ibcon#read 6, iclass 36, count 2 2006.173.13:38:10.30#ibcon#end of sib2, iclass 36, count 2 2006.173.13:38:10.30#ibcon#*after write, iclass 36, count 2 2006.173.13:38:10.30#ibcon#*before return 0, iclass 36, count 2 2006.173.13:38:10.30#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.13:38:10.30#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.13:38:10.30#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.13:38:10.30#ibcon#ireg 7 cls_cnt 0 2006.173.13:38:10.30#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.13:38:10.42#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.13:38:10.42#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.13:38:10.42#ibcon#enter wrdev, iclass 36, count 0 2006.173.13:38:10.42#ibcon#first serial, iclass 36, count 0 2006.173.13:38:10.42#ibcon#enter sib2, iclass 36, count 0 2006.173.13:38:10.42#ibcon#flushed, iclass 36, count 0 2006.173.13:38:10.42#ibcon#about to write, iclass 36, count 0 2006.173.13:38:10.42#ibcon#wrote, iclass 36, count 0 2006.173.13:38:10.42#ibcon#about to read 3, iclass 36, count 0 2006.173.13:38:10.44#ibcon#read 3, iclass 36, count 0 2006.173.13:38:10.44#ibcon#about to read 4, iclass 36, count 0 2006.173.13:38:10.44#ibcon#read 4, iclass 36, count 0 2006.173.13:38:10.44#ibcon#about to read 5, iclass 36, count 0 2006.173.13:38:10.44#ibcon#read 5, iclass 36, count 0 2006.173.13:38:10.44#ibcon#about to read 6, iclass 36, count 0 2006.173.13:38:10.44#ibcon#read 6, iclass 36, count 0 2006.173.13:38:10.44#ibcon#end of sib2, iclass 36, count 0 2006.173.13:38:10.44#ibcon#*mode == 0, iclass 36, count 0 2006.173.13:38:10.44#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.13:38:10.44#ibcon#[27=USB\r\n] 2006.173.13:38:10.44#ibcon#*before write, iclass 36, count 0 2006.173.13:38:10.44#ibcon#enter sib2, iclass 36, count 0 2006.173.13:38:10.44#ibcon#flushed, iclass 36, count 0 2006.173.13:38:10.44#ibcon#about to write, iclass 36, count 0 2006.173.13:38:10.44#ibcon#wrote, iclass 36, count 0 2006.173.13:38:10.44#ibcon#about to read 3, iclass 36, count 0 2006.173.13:38:10.47#ibcon#read 3, iclass 36, count 0 2006.173.13:38:10.47#ibcon#about to read 4, iclass 36, count 0 2006.173.13:38:10.47#ibcon#read 4, iclass 36, count 0 2006.173.13:38:10.47#ibcon#about to read 5, iclass 36, count 0 2006.173.13:38:10.47#ibcon#read 5, iclass 36, count 0 2006.173.13:38:10.47#ibcon#about to read 6, iclass 36, count 0 2006.173.13:38:10.47#ibcon#read 6, iclass 36, count 0 2006.173.13:38:10.47#ibcon#end of sib2, iclass 36, count 0 2006.173.13:38:10.47#ibcon#*after write, iclass 36, count 0 2006.173.13:38:10.47#ibcon#*before return 0, iclass 36, count 0 2006.173.13:38:10.47#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.13:38:10.47#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.13:38:10.47#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.13:38:10.47#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.13:38:10.47$vck44/vblo=6,719.99 2006.173.13:38:10.47#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.13:38:10.47#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.13:38:10.47#ibcon#ireg 17 cls_cnt 0 2006.173.13:38:10.47#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.13:38:10.47#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.13:38:10.47#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.13:38:10.47#ibcon#enter wrdev, iclass 38, count 0 2006.173.13:38:10.47#ibcon#first serial, iclass 38, count 0 2006.173.13:38:10.47#ibcon#enter sib2, iclass 38, count 0 2006.173.13:38:10.47#ibcon#flushed, iclass 38, count 0 2006.173.13:38:10.47#ibcon#about to write, iclass 38, count 0 2006.173.13:38:10.47#ibcon#wrote, iclass 38, count 0 2006.173.13:38:10.47#ibcon#about to read 3, iclass 38, count 0 2006.173.13:38:10.49#ibcon#read 3, iclass 38, count 0 2006.173.13:38:10.49#ibcon#about to read 4, iclass 38, count 0 2006.173.13:38:10.49#ibcon#read 4, iclass 38, count 0 2006.173.13:38:10.49#ibcon#about to read 5, iclass 38, count 0 2006.173.13:38:10.49#ibcon#read 5, iclass 38, count 0 2006.173.13:38:10.49#ibcon#about to read 6, iclass 38, count 0 2006.173.13:38:10.49#ibcon#read 6, iclass 38, count 0 2006.173.13:38:10.49#ibcon#end of sib2, iclass 38, count 0 2006.173.13:38:10.49#ibcon#*mode == 0, iclass 38, count 0 2006.173.13:38:10.49#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.13:38:10.49#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.13:38:10.49#ibcon#*before write, iclass 38, count 0 2006.173.13:38:10.49#ibcon#enter sib2, iclass 38, count 0 2006.173.13:38:10.49#ibcon#flushed, iclass 38, count 0 2006.173.13:38:10.49#ibcon#about to write, iclass 38, count 0 2006.173.13:38:10.49#ibcon#wrote, iclass 38, count 0 2006.173.13:38:10.49#ibcon#about to read 3, iclass 38, count 0 2006.173.13:38:10.53#ibcon#read 3, iclass 38, count 0 2006.173.13:38:10.53#ibcon#about to read 4, iclass 38, count 0 2006.173.13:38:10.53#ibcon#read 4, iclass 38, count 0 2006.173.13:38:10.53#ibcon#about to read 5, iclass 38, count 0 2006.173.13:38:10.53#ibcon#read 5, iclass 38, count 0 2006.173.13:38:10.53#ibcon#about to read 6, iclass 38, count 0 2006.173.13:38:10.53#ibcon#read 6, iclass 38, count 0 2006.173.13:38:10.53#ibcon#end of sib2, iclass 38, count 0 2006.173.13:38:10.53#ibcon#*after write, iclass 38, count 0 2006.173.13:38:10.53#ibcon#*before return 0, iclass 38, count 0 2006.173.13:38:10.53#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.13:38:10.53#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.13:38:10.53#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.13:38:10.53#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.13:38:10.53$vck44/vb=6,4 2006.173.13:38:10.53#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.13:38:10.53#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.13:38:10.53#ibcon#ireg 11 cls_cnt 2 2006.173.13:38:10.53#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.13:38:10.59#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.13:38:10.59#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.13:38:10.59#ibcon#enter wrdev, iclass 40, count 2 2006.173.13:38:10.59#ibcon#first serial, iclass 40, count 2 2006.173.13:38:10.59#ibcon#enter sib2, iclass 40, count 2 2006.173.13:38:10.59#ibcon#flushed, iclass 40, count 2 2006.173.13:38:10.59#ibcon#about to write, iclass 40, count 2 2006.173.13:38:10.59#ibcon#wrote, iclass 40, count 2 2006.173.13:38:10.59#ibcon#about to read 3, iclass 40, count 2 2006.173.13:38:10.61#ibcon#read 3, iclass 40, count 2 2006.173.13:38:10.61#ibcon#about to read 4, iclass 40, count 2 2006.173.13:38:10.61#ibcon#read 4, iclass 40, count 2 2006.173.13:38:10.61#ibcon#about to read 5, iclass 40, count 2 2006.173.13:38:10.61#ibcon#read 5, iclass 40, count 2 2006.173.13:38:10.61#ibcon#about to read 6, iclass 40, count 2 2006.173.13:38:10.61#ibcon#read 6, iclass 40, count 2 2006.173.13:38:10.61#ibcon#end of sib2, iclass 40, count 2 2006.173.13:38:10.61#ibcon#*mode == 0, iclass 40, count 2 2006.173.13:38:10.61#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.13:38:10.61#ibcon#[27=AT06-04\r\n] 2006.173.13:38:10.61#ibcon#*before write, iclass 40, count 2 2006.173.13:38:10.61#ibcon#enter sib2, iclass 40, count 2 2006.173.13:38:10.61#ibcon#flushed, iclass 40, count 2 2006.173.13:38:10.61#ibcon#about to write, iclass 40, count 2 2006.173.13:38:10.61#ibcon#wrote, iclass 40, count 2 2006.173.13:38:10.61#ibcon#about to read 3, iclass 40, count 2 2006.173.13:38:10.64#ibcon#read 3, iclass 40, count 2 2006.173.13:38:10.64#ibcon#about to read 4, iclass 40, count 2 2006.173.13:38:10.64#ibcon#read 4, iclass 40, count 2 2006.173.13:38:10.64#ibcon#about to read 5, iclass 40, count 2 2006.173.13:38:10.64#ibcon#read 5, iclass 40, count 2 2006.173.13:38:10.64#ibcon#about to read 6, iclass 40, count 2 2006.173.13:38:10.64#ibcon#read 6, iclass 40, count 2 2006.173.13:38:10.64#ibcon#end of sib2, iclass 40, count 2 2006.173.13:38:10.64#ibcon#*after write, iclass 40, count 2 2006.173.13:38:10.64#ibcon#*before return 0, iclass 40, count 2 2006.173.13:38:10.64#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.13:38:10.64#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.13:38:10.64#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.13:38:10.64#ibcon#ireg 7 cls_cnt 0 2006.173.13:38:10.64#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.13:38:10.76#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.13:38:10.76#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.13:38:10.76#ibcon#enter wrdev, iclass 40, count 0 2006.173.13:38:10.76#ibcon#first serial, iclass 40, count 0 2006.173.13:38:10.76#ibcon#enter sib2, iclass 40, count 0 2006.173.13:38:10.76#ibcon#flushed, iclass 40, count 0 2006.173.13:38:10.76#ibcon#about to write, iclass 40, count 0 2006.173.13:38:10.76#ibcon#wrote, iclass 40, count 0 2006.173.13:38:10.76#ibcon#about to read 3, iclass 40, count 0 2006.173.13:38:10.78#ibcon#read 3, iclass 40, count 0 2006.173.13:38:10.78#ibcon#about to read 4, iclass 40, count 0 2006.173.13:38:10.78#ibcon#read 4, iclass 40, count 0 2006.173.13:38:10.78#ibcon#about to read 5, iclass 40, count 0 2006.173.13:38:10.78#ibcon#read 5, iclass 40, count 0 2006.173.13:38:10.78#ibcon#about to read 6, iclass 40, count 0 2006.173.13:38:10.78#ibcon#read 6, iclass 40, count 0 2006.173.13:38:10.78#ibcon#end of sib2, iclass 40, count 0 2006.173.13:38:10.78#ibcon#*mode == 0, iclass 40, count 0 2006.173.13:38:10.78#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.13:38:10.78#ibcon#[27=USB\r\n] 2006.173.13:38:10.78#ibcon#*before write, iclass 40, count 0 2006.173.13:38:10.78#ibcon#enter sib2, iclass 40, count 0 2006.173.13:38:10.78#ibcon#flushed, iclass 40, count 0 2006.173.13:38:10.78#ibcon#about to write, iclass 40, count 0 2006.173.13:38:10.78#ibcon#wrote, iclass 40, count 0 2006.173.13:38:10.78#ibcon#about to read 3, iclass 40, count 0 2006.173.13:38:10.81#ibcon#read 3, iclass 40, count 0 2006.173.13:38:10.81#ibcon#about to read 4, iclass 40, count 0 2006.173.13:38:10.81#ibcon#read 4, iclass 40, count 0 2006.173.13:38:10.81#ibcon#about to read 5, iclass 40, count 0 2006.173.13:38:10.81#ibcon#read 5, iclass 40, count 0 2006.173.13:38:10.81#ibcon#about to read 6, iclass 40, count 0 2006.173.13:38:10.81#ibcon#read 6, iclass 40, count 0 2006.173.13:38:10.81#ibcon#end of sib2, iclass 40, count 0 2006.173.13:38:10.81#ibcon#*after write, iclass 40, count 0 2006.173.13:38:10.81#ibcon#*before return 0, iclass 40, count 0 2006.173.13:38:10.81#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.13:38:10.81#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.13:38:10.81#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.13:38:10.81#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.13:38:10.81$vck44/vblo=7,734.99 2006.173.13:38:10.81#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.13:38:10.81#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.13:38:10.81#ibcon#ireg 17 cls_cnt 0 2006.173.13:38:10.81#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.13:38:10.81#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.13:38:10.81#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.13:38:10.81#ibcon#enter wrdev, iclass 4, count 0 2006.173.13:38:10.81#ibcon#first serial, iclass 4, count 0 2006.173.13:38:10.81#ibcon#enter sib2, iclass 4, count 0 2006.173.13:38:10.81#ibcon#flushed, iclass 4, count 0 2006.173.13:38:10.81#ibcon#about to write, iclass 4, count 0 2006.173.13:38:10.81#ibcon#wrote, iclass 4, count 0 2006.173.13:38:10.81#ibcon#about to read 3, iclass 4, count 0 2006.173.13:38:10.83#ibcon#read 3, iclass 4, count 0 2006.173.13:38:10.83#ibcon#about to read 4, iclass 4, count 0 2006.173.13:38:10.83#ibcon#read 4, iclass 4, count 0 2006.173.13:38:10.83#ibcon#about to read 5, iclass 4, count 0 2006.173.13:38:10.83#ibcon#read 5, iclass 4, count 0 2006.173.13:38:10.83#ibcon#about to read 6, iclass 4, count 0 2006.173.13:38:10.83#ibcon#read 6, iclass 4, count 0 2006.173.13:38:10.83#ibcon#end of sib2, iclass 4, count 0 2006.173.13:38:10.83#ibcon#*mode == 0, iclass 4, count 0 2006.173.13:38:10.83#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.13:38:10.83#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.13:38:10.83#ibcon#*before write, iclass 4, count 0 2006.173.13:38:10.83#ibcon#enter sib2, iclass 4, count 0 2006.173.13:38:10.83#ibcon#flushed, iclass 4, count 0 2006.173.13:38:10.83#ibcon#about to write, iclass 4, count 0 2006.173.13:38:10.83#ibcon#wrote, iclass 4, count 0 2006.173.13:38:10.83#ibcon#about to read 3, iclass 4, count 0 2006.173.13:38:10.87#ibcon#read 3, iclass 4, count 0 2006.173.13:38:10.87#ibcon#about to read 4, iclass 4, count 0 2006.173.13:38:10.87#ibcon#read 4, iclass 4, count 0 2006.173.13:38:10.87#ibcon#about to read 5, iclass 4, count 0 2006.173.13:38:10.87#ibcon#read 5, iclass 4, count 0 2006.173.13:38:10.87#ibcon#about to read 6, iclass 4, count 0 2006.173.13:38:10.87#ibcon#read 6, iclass 4, count 0 2006.173.13:38:10.87#ibcon#end of sib2, iclass 4, count 0 2006.173.13:38:10.87#ibcon#*after write, iclass 4, count 0 2006.173.13:38:10.87#ibcon#*before return 0, iclass 4, count 0 2006.173.13:38:10.87#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.13:38:10.87#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.13:38:10.87#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.13:38:10.87#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.13:38:10.87$vck44/vb=7,4 2006.173.13:38:10.87#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.13:38:10.87#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.13:38:10.87#ibcon#ireg 11 cls_cnt 2 2006.173.13:38:10.87#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.13:38:10.93#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.13:38:10.93#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.13:38:10.93#ibcon#enter wrdev, iclass 6, count 2 2006.173.13:38:10.93#ibcon#first serial, iclass 6, count 2 2006.173.13:38:10.93#ibcon#enter sib2, iclass 6, count 2 2006.173.13:38:10.93#ibcon#flushed, iclass 6, count 2 2006.173.13:38:10.93#ibcon#about to write, iclass 6, count 2 2006.173.13:38:10.93#ibcon#wrote, iclass 6, count 2 2006.173.13:38:10.93#ibcon#about to read 3, iclass 6, count 2 2006.173.13:38:10.95#ibcon#read 3, iclass 6, count 2 2006.173.13:38:10.95#ibcon#about to read 4, iclass 6, count 2 2006.173.13:38:10.95#ibcon#read 4, iclass 6, count 2 2006.173.13:38:10.95#ibcon#about to read 5, iclass 6, count 2 2006.173.13:38:10.95#ibcon#read 5, iclass 6, count 2 2006.173.13:38:10.95#ibcon#about to read 6, iclass 6, count 2 2006.173.13:38:10.95#ibcon#read 6, iclass 6, count 2 2006.173.13:38:10.95#ibcon#end of sib2, iclass 6, count 2 2006.173.13:38:10.95#ibcon#*mode == 0, iclass 6, count 2 2006.173.13:38:10.95#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.13:38:10.95#ibcon#[27=AT07-04\r\n] 2006.173.13:38:10.95#ibcon#*before write, iclass 6, count 2 2006.173.13:38:10.95#ibcon#enter sib2, iclass 6, count 2 2006.173.13:38:10.95#ibcon#flushed, iclass 6, count 2 2006.173.13:38:10.95#ibcon#about to write, iclass 6, count 2 2006.173.13:38:10.95#ibcon#wrote, iclass 6, count 2 2006.173.13:38:10.95#ibcon#about to read 3, iclass 6, count 2 2006.173.13:38:10.98#ibcon#read 3, iclass 6, count 2 2006.173.13:38:10.98#ibcon#about to read 4, iclass 6, count 2 2006.173.13:38:10.98#ibcon#read 4, iclass 6, count 2 2006.173.13:38:10.98#ibcon#about to read 5, iclass 6, count 2 2006.173.13:38:10.98#ibcon#read 5, iclass 6, count 2 2006.173.13:38:10.98#ibcon#about to read 6, iclass 6, count 2 2006.173.13:38:10.98#ibcon#read 6, iclass 6, count 2 2006.173.13:38:10.98#ibcon#end of sib2, iclass 6, count 2 2006.173.13:38:10.98#ibcon#*after write, iclass 6, count 2 2006.173.13:38:10.98#ibcon#*before return 0, iclass 6, count 2 2006.173.13:38:10.98#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.13:38:10.98#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.13:38:10.98#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.13:38:10.98#ibcon#ireg 7 cls_cnt 0 2006.173.13:38:10.98#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.13:38:11.10#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.13:38:11.10#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.13:38:11.10#ibcon#enter wrdev, iclass 6, count 0 2006.173.13:38:11.10#ibcon#first serial, iclass 6, count 0 2006.173.13:38:11.10#ibcon#enter sib2, iclass 6, count 0 2006.173.13:38:11.10#ibcon#flushed, iclass 6, count 0 2006.173.13:38:11.10#ibcon#about to write, iclass 6, count 0 2006.173.13:38:11.10#ibcon#wrote, iclass 6, count 0 2006.173.13:38:11.10#ibcon#about to read 3, iclass 6, count 0 2006.173.13:38:11.12#ibcon#read 3, iclass 6, count 0 2006.173.13:38:11.12#ibcon#about to read 4, iclass 6, count 0 2006.173.13:38:11.12#ibcon#read 4, iclass 6, count 0 2006.173.13:38:11.12#ibcon#about to read 5, iclass 6, count 0 2006.173.13:38:11.12#ibcon#read 5, iclass 6, count 0 2006.173.13:38:11.12#ibcon#about to read 6, iclass 6, count 0 2006.173.13:38:11.12#ibcon#read 6, iclass 6, count 0 2006.173.13:38:11.12#ibcon#end of sib2, iclass 6, count 0 2006.173.13:38:11.12#ibcon#*mode == 0, iclass 6, count 0 2006.173.13:38:11.12#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.13:38:11.12#ibcon#[27=USB\r\n] 2006.173.13:38:11.12#ibcon#*before write, iclass 6, count 0 2006.173.13:38:11.12#ibcon#enter sib2, iclass 6, count 0 2006.173.13:38:11.12#ibcon#flushed, iclass 6, count 0 2006.173.13:38:11.12#ibcon#about to write, iclass 6, count 0 2006.173.13:38:11.12#ibcon#wrote, iclass 6, count 0 2006.173.13:38:11.12#ibcon#about to read 3, iclass 6, count 0 2006.173.13:38:11.15#ibcon#read 3, iclass 6, count 0 2006.173.13:38:11.15#ibcon#about to read 4, iclass 6, count 0 2006.173.13:38:11.15#ibcon#read 4, iclass 6, count 0 2006.173.13:38:11.15#ibcon#about to read 5, iclass 6, count 0 2006.173.13:38:11.15#ibcon#read 5, iclass 6, count 0 2006.173.13:38:11.15#ibcon#about to read 6, iclass 6, count 0 2006.173.13:38:11.15#ibcon#read 6, iclass 6, count 0 2006.173.13:38:11.15#ibcon#end of sib2, iclass 6, count 0 2006.173.13:38:11.15#ibcon#*after write, iclass 6, count 0 2006.173.13:38:11.15#ibcon#*before return 0, iclass 6, count 0 2006.173.13:38:11.15#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.13:38:11.15#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.13:38:11.15#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.13:38:11.15#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.13:38:11.15$vck44/vblo=8,744.99 2006.173.13:38:11.15#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.13:38:11.15#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.13:38:11.15#ibcon#ireg 17 cls_cnt 0 2006.173.13:38:11.15#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.13:38:11.15#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.13:38:11.15#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.13:38:11.15#ibcon#enter wrdev, iclass 10, count 0 2006.173.13:38:11.15#ibcon#first serial, iclass 10, count 0 2006.173.13:38:11.15#ibcon#enter sib2, iclass 10, count 0 2006.173.13:38:11.15#ibcon#flushed, iclass 10, count 0 2006.173.13:38:11.15#ibcon#about to write, iclass 10, count 0 2006.173.13:38:11.15#ibcon#wrote, iclass 10, count 0 2006.173.13:38:11.15#ibcon#about to read 3, iclass 10, count 0 2006.173.13:38:11.17#ibcon#read 3, iclass 10, count 0 2006.173.13:38:11.17#ibcon#about to read 4, iclass 10, count 0 2006.173.13:38:11.17#ibcon#read 4, iclass 10, count 0 2006.173.13:38:11.17#ibcon#about to read 5, iclass 10, count 0 2006.173.13:38:11.17#ibcon#read 5, iclass 10, count 0 2006.173.13:38:11.17#ibcon#about to read 6, iclass 10, count 0 2006.173.13:38:11.17#ibcon#read 6, iclass 10, count 0 2006.173.13:38:11.17#ibcon#end of sib2, iclass 10, count 0 2006.173.13:38:11.17#ibcon#*mode == 0, iclass 10, count 0 2006.173.13:38:11.17#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.13:38:11.17#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.13:38:11.17#ibcon#*before write, iclass 10, count 0 2006.173.13:38:11.17#ibcon#enter sib2, iclass 10, count 0 2006.173.13:38:11.17#ibcon#flushed, iclass 10, count 0 2006.173.13:38:11.17#ibcon#about to write, iclass 10, count 0 2006.173.13:38:11.17#ibcon#wrote, iclass 10, count 0 2006.173.13:38:11.17#ibcon#about to read 3, iclass 10, count 0 2006.173.13:38:11.21#ibcon#read 3, iclass 10, count 0 2006.173.13:38:11.21#ibcon#about to read 4, iclass 10, count 0 2006.173.13:38:11.21#ibcon#read 4, iclass 10, count 0 2006.173.13:38:11.21#ibcon#about to read 5, iclass 10, count 0 2006.173.13:38:11.21#ibcon#read 5, iclass 10, count 0 2006.173.13:38:11.21#ibcon#about to read 6, iclass 10, count 0 2006.173.13:38:11.21#ibcon#read 6, iclass 10, count 0 2006.173.13:38:11.21#ibcon#end of sib2, iclass 10, count 0 2006.173.13:38:11.21#ibcon#*after write, iclass 10, count 0 2006.173.13:38:11.21#ibcon#*before return 0, iclass 10, count 0 2006.173.13:38:11.21#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.13:38:11.21#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.13:38:11.21#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.13:38:11.21#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.13:38:11.21$vck44/vb=8,4 2006.173.13:38:11.21#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.13:38:11.21#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.13:38:11.21#ibcon#ireg 11 cls_cnt 2 2006.173.13:38:11.21#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.13:38:11.27#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.13:38:11.27#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.13:38:11.27#ibcon#enter wrdev, iclass 12, count 2 2006.173.13:38:11.27#ibcon#first serial, iclass 12, count 2 2006.173.13:38:11.27#ibcon#enter sib2, iclass 12, count 2 2006.173.13:38:11.27#ibcon#flushed, iclass 12, count 2 2006.173.13:38:11.27#ibcon#about to write, iclass 12, count 2 2006.173.13:38:11.27#ibcon#wrote, iclass 12, count 2 2006.173.13:38:11.27#ibcon#about to read 3, iclass 12, count 2 2006.173.13:38:11.29#ibcon#read 3, iclass 12, count 2 2006.173.13:38:11.29#ibcon#about to read 4, iclass 12, count 2 2006.173.13:38:11.29#ibcon#read 4, iclass 12, count 2 2006.173.13:38:11.29#ibcon#about to read 5, iclass 12, count 2 2006.173.13:38:11.29#ibcon#read 5, iclass 12, count 2 2006.173.13:38:11.29#ibcon#about to read 6, iclass 12, count 2 2006.173.13:38:11.29#ibcon#read 6, iclass 12, count 2 2006.173.13:38:11.29#ibcon#end of sib2, iclass 12, count 2 2006.173.13:38:11.29#ibcon#*mode == 0, iclass 12, count 2 2006.173.13:38:11.29#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.13:38:11.29#ibcon#[27=AT08-04\r\n] 2006.173.13:38:11.29#ibcon#*before write, iclass 12, count 2 2006.173.13:38:11.29#ibcon#enter sib2, iclass 12, count 2 2006.173.13:38:11.29#ibcon#flushed, iclass 12, count 2 2006.173.13:38:11.29#ibcon#about to write, iclass 12, count 2 2006.173.13:38:11.29#ibcon#wrote, iclass 12, count 2 2006.173.13:38:11.29#ibcon#about to read 3, iclass 12, count 2 2006.173.13:38:11.32#ibcon#read 3, iclass 12, count 2 2006.173.13:38:11.32#ibcon#about to read 4, iclass 12, count 2 2006.173.13:38:11.32#ibcon#read 4, iclass 12, count 2 2006.173.13:38:11.32#ibcon#about to read 5, iclass 12, count 2 2006.173.13:38:11.32#ibcon#read 5, iclass 12, count 2 2006.173.13:38:11.32#ibcon#about to read 6, iclass 12, count 2 2006.173.13:38:11.32#ibcon#read 6, iclass 12, count 2 2006.173.13:38:11.32#ibcon#end of sib2, iclass 12, count 2 2006.173.13:38:11.32#ibcon#*after write, iclass 12, count 2 2006.173.13:38:11.32#ibcon#*before return 0, iclass 12, count 2 2006.173.13:38:11.32#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.13:38:11.32#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.13:38:11.32#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.13:38:11.32#ibcon#ireg 7 cls_cnt 0 2006.173.13:38:11.32#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.13:38:11.44#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.13:38:11.44#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.13:38:11.44#ibcon#enter wrdev, iclass 12, count 0 2006.173.13:38:11.44#ibcon#first serial, iclass 12, count 0 2006.173.13:38:11.44#ibcon#enter sib2, iclass 12, count 0 2006.173.13:38:11.44#ibcon#flushed, iclass 12, count 0 2006.173.13:38:11.44#ibcon#about to write, iclass 12, count 0 2006.173.13:38:11.44#ibcon#wrote, iclass 12, count 0 2006.173.13:38:11.44#ibcon#about to read 3, iclass 12, count 0 2006.173.13:38:11.46#ibcon#read 3, iclass 12, count 0 2006.173.13:38:11.46#ibcon#about to read 4, iclass 12, count 0 2006.173.13:38:11.46#ibcon#read 4, iclass 12, count 0 2006.173.13:38:11.46#ibcon#about to read 5, iclass 12, count 0 2006.173.13:38:11.46#ibcon#read 5, iclass 12, count 0 2006.173.13:38:11.46#ibcon#about to read 6, iclass 12, count 0 2006.173.13:38:11.46#ibcon#read 6, iclass 12, count 0 2006.173.13:38:11.46#ibcon#end of sib2, iclass 12, count 0 2006.173.13:38:11.46#ibcon#*mode == 0, iclass 12, count 0 2006.173.13:38:11.46#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.13:38:11.46#ibcon#[27=USB\r\n] 2006.173.13:38:11.46#ibcon#*before write, iclass 12, count 0 2006.173.13:38:11.46#ibcon#enter sib2, iclass 12, count 0 2006.173.13:38:11.46#ibcon#flushed, iclass 12, count 0 2006.173.13:38:11.46#ibcon#about to write, iclass 12, count 0 2006.173.13:38:11.46#ibcon#wrote, iclass 12, count 0 2006.173.13:38:11.46#ibcon#about to read 3, iclass 12, count 0 2006.173.13:38:11.49#ibcon#read 3, iclass 12, count 0 2006.173.13:38:11.49#ibcon#about to read 4, iclass 12, count 0 2006.173.13:38:11.49#ibcon#read 4, iclass 12, count 0 2006.173.13:38:11.49#ibcon#about to read 5, iclass 12, count 0 2006.173.13:38:11.49#ibcon#read 5, iclass 12, count 0 2006.173.13:38:11.49#ibcon#about to read 6, iclass 12, count 0 2006.173.13:38:11.49#ibcon#read 6, iclass 12, count 0 2006.173.13:38:11.49#ibcon#end of sib2, iclass 12, count 0 2006.173.13:38:11.49#ibcon#*after write, iclass 12, count 0 2006.173.13:38:11.49#ibcon#*before return 0, iclass 12, count 0 2006.173.13:38:11.49#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.13:38:11.49#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.13:38:11.49#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.13:38:11.49#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.13:38:11.49$vck44/vabw=wide 2006.173.13:38:11.49#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.13:38:11.49#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.13:38:11.49#ibcon#ireg 8 cls_cnt 0 2006.173.13:38:11.49#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.13:38:11.49#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.13:38:11.49#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.13:38:11.49#ibcon#enter wrdev, iclass 14, count 0 2006.173.13:38:11.49#ibcon#first serial, iclass 14, count 0 2006.173.13:38:11.49#ibcon#enter sib2, iclass 14, count 0 2006.173.13:38:11.49#ibcon#flushed, iclass 14, count 0 2006.173.13:38:11.49#ibcon#about to write, iclass 14, count 0 2006.173.13:38:11.49#ibcon#wrote, iclass 14, count 0 2006.173.13:38:11.49#ibcon#about to read 3, iclass 14, count 0 2006.173.13:38:11.51#ibcon#read 3, iclass 14, count 0 2006.173.13:38:11.51#ibcon#about to read 4, iclass 14, count 0 2006.173.13:38:11.51#ibcon#read 4, iclass 14, count 0 2006.173.13:38:11.51#ibcon#about to read 5, iclass 14, count 0 2006.173.13:38:11.51#ibcon#read 5, iclass 14, count 0 2006.173.13:38:11.51#ibcon#about to read 6, iclass 14, count 0 2006.173.13:38:11.51#ibcon#read 6, iclass 14, count 0 2006.173.13:38:11.51#ibcon#end of sib2, iclass 14, count 0 2006.173.13:38:11.51#ibcon#*mode == 0, iclass 14, count 0 2006.173.13:38:11.51#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.13:38:11.51#ibcon#[25=BW32\r\n] 2006.173.13:38:11.51#ibcon#*before write, iclass 14, count 0 2006.173.13:38:11.51#ibcon#enter sib2, iclass 14, count 0 2006.173.13:38:11.51#ibcon#flushed, iclass 14, count 0 2006.173.13:38:11.51#ibcon#about to write, iclass 14, count 0 2006.173.13:38:11.51#ibcon#wrote, iclass 14, count 0 2006.173.13:38:11.51#ibcon#about to read 3, iclass 14, count 0 2006.173.13:38:11.54#ibcon#read 3, iclass 14, count 0 2006.173.13:38:11.54#ibcon#about to read 4, iclass 14, count 0 2006.173.13:38:11.54#ibcon#read 4, iclass 14, count 0 2006.173.13:38:11.54#ibcon#about to read 5, iclass 14, count 0 2006.173.13:38:11.54#ibcon#read 5, iclass 14, count 0 2006.173.13:38:11.54#ibcon#about to read 6, iclass 14, count 0 2006.173.13:38:11.54#ibcon#read 6, iclass 14, count 0 2006.173.13:38:11.54#ibcon#end of sib2, iclass 14, count 0 2006.173.13:38:11.54#ibcon#*after write, iclass 14, count 0 2006.173.13:38:11.54#ibcon#*before return 0, iclass 14, count 0 2006.173.13:38:11.54#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.13:38:11.54#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.13:38:11.54#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.13:38:11.54#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.13:38:11.54$vck44/vbbw=wide 2006.173.13:38:11.54#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.13:38:11.54#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.13:38:11.54#ibcon#ireg 8 cls_cnt 0 2006.173.13:38:11.54#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.13:38:11.61#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.13:38:11.61#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.13:38:11.61#ibcon#enter wrdev, iclass 16, count 0 2006.173.13:38:11.61#ibcon#first serial, iclass 16, count 0 2006.173.13:38:11.61#ibcon#enter sib2, iclass 16, count 0 2006.173.13:38:11.61#ibcon#flushed, iclass 16, count 0 2006.173.13:38:11.61#ibcon#about to write, iclass 16, count 0 2006.173.13:38:11.61#ibcon#wrote, iclass 16, count 0 2006.173.13:38:11.61#ibcon#about to read 3, iclass 16, count 0 2006.173.13:38:11.63#ibcon#read 3, iclass 16, count 0 2006.173.13:38:11.63#ibcon#about to read 4, iclass 16, count 0 2006.173.13:38:11.63#ibcon#read 4, iclass 16, count 0 2006.173.13:38:11.63#ibcon#about to read 5, iclass 16, count 0 2006.173.13:38:11.63#ibcon#read 5, iclass 16, count 0 2006.173.13:38:11.63#ibcon#about to read 6, iclass 16, count 0 2006.173.13:38:11.63#ibcon#read 6, iclass 16, count 0 2006.173.13:38:11.63#ibcon#end of sib2, iclass 16, count 0 2006.173.13:38:11.63#ibcon#*mode == 0, iclass 16, count 0 2006.173.13:38:11.63#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.13:38:11.63#ibcon#[27=BW32\r\n] 2006.173.13:38:11.63#ibcon#*before write, iclass 16, count 0 2006.173.13:38:11.63#ibcon#enter sib2, iclass 16, count 0 2006.173.13:38:11.63#ibcon#flushed, iclass 16, count 0 2006.173.13:38:11.63#ibcon#about to write, iclass 16, count 0 2006.173.13:38:11.63#ibcon#wrote, iclass 16, count 0 2006.173.13:38:11.63#ibcon#about to read 3, iclass 16, count 0 2006.173.13:38:11.66#ibcon#read 3, iclass 16, count 0 2006.173.13:38:11.66#ibcon#about to read 4, iclass 16, count 0 2006.173.13:38:11.66#ibcon#read 4, iclass 16, count 0 2006.173.13:38:11.66#ibcon#about to read 5, iclass 16, count 0 2006.173.13:38:11.66#ibcon#read 5, iclass 16, count 0 2006.173.13:38:11.66#ibcon#about to read 6, iclass 16, count 0 2006.173.13:38:11.66#ibcon#read 6, iclass 16, count 0 2006.173.13:38:11.66#ibcon#end of sib2, iclass 16, count 0 2006.173.13:38:11.66#ibcon#*after write, iclass 16, count 0 2006.173.13:38:11.66#ibcon#*before return 0, iclass 16, count 0 2006.173.13:38:11.66#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.13:38:11.66#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.13:38:11.66#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.13:38:11.66#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.13:38:11.66$setupk4/ifdk4 2006.173.13:38:11.66$ifdk4/lo= 2006.173.13:38:11.66$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.13:38:11.66$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.13:38:11.66$ifdk4/patch= 2006.173.13:38:11.66$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.13:38:11.66$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.13:38:11.67$setupk4/!*+20s 2006.173.13:38:17.08#abcon#<5=/04 0.5 1.3 21.961001003.9\r\n> 2006.173.13:38:17.10#abcon#{5=INTERFACE CLEAR} 2006.173.13:38:17.16#abcon#[5=S1D000X0/0*\r\n] 2006.173.13:38:22.13#trakl#Source acquired 2006.173.13:38:22.13#flagr#flagr/antenna,acquired 2006.173.13:38:26.18$setupk4/"tpicd 2006.173.13:38:26.18$setupk4/echo=off 2006.173.13:38:26.18$setupk4/xlog=off 2006.173.13:38:26.18:!2006.173.13:38:37 2006.173.13:38:37.00:preob 2006.173.13:38:38.13/onsource/TRACKING 2006.173.13:38:38.13:!2006.173.13:38:47 2006.173.13:38:47.00:"tape 2006.173.13:38:47.00:"st=record 2006.173.13:38:47.00:data_valid=on 2006.173.13:38:47.00:midob 2006.173.13:38:47.14/onsource/TRACKING 2006.173.13:38:47.14/wx/21.96,1003.9,100 2006.173.13:38:47.20/cable/+6.5051E-03 2006.173.13:38:48.29/va/01,07,usb,yes,60,64 2006.173.13:38:48.29/va/02,06,usb,yes,59,61 2006.173.13:38:48.29/va/03,05,usb,yes,74,77 2006.173.13:38:48.29/va/04,06,usb,yes,61,64 2006.173.13:38:48.29/va/05,04,usb,yes,49,50 2006.173.13:38:48.29/va/06,03,usb,yes,67,67 2006.173.13:38:48.29/va/07,04,usb,yes,55,57 2006.173.13:38:48.29/va/08,04,usb,yes,48,56 2006.173.13:38:48.52/valo/01,524.99,yes,locked 2006.173.13:38:48.52/valo/02,534.99,yes,locked 2006.173.13:38:48.52/valo/03,564.99,yes,locked 2006.173.13:38:48.52/valo/04,624.99,yes,locked 2006.173.13:38:48.52/valo/05,734.99,yes,locked 2006.173.13:38:48.52/valo/06,814.99,yes,locked 2006.173.13:38:48.52/valo/07,864.99,yes,locked 2006.173.13:38:48.52/valo/08,884.99,yes,locked 2006.173.13:38:49.61/vb/01,04,usb,yes,35,33 2006.173.13:38:49.61/vb/02,04,usb,yes,38,38 2006.173.13:38:49.61/vb/03,04,usb,yes,35,38 2006.173.13:38:49.61/vb/04,04,usb,yes,39,38 2006.173.13:38:49.61/vb/05,04,usb,yes,32,34 2006.173.13:38:49.61/vb/06,04,usb,yes,37,32 2006.173.13:38:49.61/vb/07,04,usb,yes,36,37 2006.173.13:38:49.61/vb/08,04,usb,yes,33,37 2006.173.13:38:49.84/vblo/01,629.99,yes,locked 2006.173.13:38:49.84/vblo/02,634.99,yes,locked 2006.173.13:38:49.84/vblo/03,649.99,yes,locked 2006.173.13:38:49.84/vblo/04,679.99,yes,locked 2006.173.13:38:49.84/vblo/05,709.99,yes,locked 2006.173.13:38:49.84/vblo/06,719.99,yes,locked 2006.173.13:38:49.84/vblo/07,734.99,yes,locked 2006.173.13:38:49.84/vblo/08,744.99,yes,locked 2006.173.13:38:49.99/vabw/8 2006.173.13:38:50.14/vbbw/8 2006.173.13:38:50.23/xfe/off,on,14.2 2006.173.13:38:50.61/ifatt/23,28,28,28 2006.173.13:38:51.07/fmout-gps/S +3.86E-07 2006.173.13:38:51.12:!2006.173.13:51:51 2006.173.13:51:51.00:data_valid=off 2006.173.13:51:51.00:"et 2006.173.13:51:51.00:!+3s 2006.173.13:51:54.01:"tape 2006.173.13:51:54.01:postob 2006.173.13:51:54.08/cable/+6.5060E-03 2006.173.13:51:54.08/wx/21.85,1003.7,100 2006.173.13:51:55.08/fmout-gps/S +3.93E-07 2006.173.13:51:55.08:scan_name=173-1353,jd0606,80 2006.173.13:51:55.08:source=2136+141,213901.31,142336.0,2000.0,cw 2006.173.13:51:56.14#flagr#flagr/antenna,new-source 2006.173.13:51:56.14:checkk5 2006.173.13:51:56.57/chk_autoobs//k5ts1/ autoobs is running! 2006.173.13:51:56.97/chk_autoobs//k5ts2/ autoobs is running! 2006.173.13:51:57.38/chk_autoobs//k5ts3/ autoobs is running! 2006.173.13:51:57.76/chk_autoobs//k5ts4/ autoobs is running! 2006.173.13:51:58.46/chk_obsdata//k5ts1/T1731338??a.dat file size is correct (nominal:3136MB, actual:3132MB). 2006.173.13:51:59.16/chk_obsdata//k5ts2/T1731338??b.dat file size is correct (nominal:3136MB, actual:3132MB). 2006.173.13:51:59.88/chk_obsdata//k5ts3/T1731338??c.dat file size is correct (nominal:3136MB, actual:3132MB). 2006.173.13:52:00.59/chk_obsdata//k5ts4/T1731338??d.dat file size is correct (nominal:3136MB, actual:3132MB). 2006.173.13:52:01.32/k5log//k5ts1_log_newline 2006.173.13:52:02.02/k5log//k5ts2_log_newline 2006.173.13:52:02.75/k5log//k5ts3_log_newline 2006.173.13:52:03.45/k5log//k5ts4_log_newline 2006.173.13:52:03.47/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.13:52:03.47:setupk4=1 2006.173.13:52:03.47$setupk4/echo=on 2006.173.13:52:03.47$setupk4/pcalon 2006.173.13:52:03.47$pcalon/"no phase cal control is implemented here 2006.173.13:52:03.47$setupk4/"tpicd=stop 2006.173.13:52:03.47$setupk4/"rec=synch_on 2006.173.13:52:03.47$setupk4/"rec_mode=128 2006.173.13:52:03.47$setupk4/!* 2006.173.13:52:03.47$setupk4/recpk4 2006.173.13:52:03.47$recpk4/recpatch= 2006.173.13:52:03.47$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.13:52:03.47$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.13:52:03.47$setupk4/vck44 2006.173.13:52:03.47$vck44/valo=1,524.99 2006.173.13:52:03.47#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.13:52:03.47#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.13:52:03.47#ibcon#ireg 17 cls_cnt 0 2006.173.13:52:03.47#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.13:52:03.47#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.13:52:03.47#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.13:52:03.47#ibcon#enter wrdev, iclass 16, count 0 2006.173.13:52:03.47#ibcon#first serial, iclass 16, count 0 2006.173.13:52:03.47#ibcon#enter sib2, iclass 16, count 0 2006.173.13:52:03.47#ibcon#flushed, iclass 16, count 0 2006.173.13:52:03.47#ibcon#about to write, iclass 16, count 0 2006.173.13:52:03.47#ibcon#wrote, iclass 16, count 0 2006.173.13:52:03.47#ibcon#about to read 3, iclass 16, count 0 2006.173.13:52:03.49#ibcon#read 3, iclass 16, count 0 2006.173.13:52:03.49#ibcon#about to read 4, iclass 16, count 0 2006.173.13:52:03.49#ibcon#read 4, iclass 16, count 0 2006.173.13:52:03.49#ibcon#about to read 5, iclass 16, count 0 2006.173.13:52:03.49#ibcon#read 5, iclass 16, count 0 2006.173.13:52:03.49#ibcon#about to read 6, iclass 16, count 0 2006.173.13:52:03.49#ibcon#read 6, iclass 16, count 0 2006.173.13:52:03.49#ibcon#end of sib2, iclass 16, count 0 2006.173.13:52:03.49#ibcon#*mode == 0, iclass 16, count 0 2006.173.13:52:03.49#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.13:52:03.49#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.13:52:03.49#ibcon#*before write, iclass 16, count 0 2006.173.13:52:03.49#ibcon#enter sib2, iclass 16, count 0 2006.173.13:52:03.49#ibcon#flushed, iclass 16, count 0 2006.173.13:52:03.49#ibcon#about to write, iclass 16, count 0 2006.173.13:52:03.49#ibcon#wrote, iclass 16, count 0 2006.173.13:52:03.49#ibcon#about to read 3, iclass 16, count 0 2006.173.13:52:03.54#ibcon#read 3, iclass 16, count 0 2006.173.13:52:03.54#ibcon#about to read 4, iclass 16, count 0 2006.173.13:52:03.54#ibcon#read 4, iclass 16, count 0 2006.173.13:52:03.54#ibcon#about to read 5, iclass 16, count 0 2006.173.13:52:03.54#ibcon#read 5, iclass 16, count 0 2006.173.13:52:03.54#ibcon#about to read 6, iclass 16, count 0 2006.173.13:52:03.54#ibcon#read 6, iclass 16, count 0 2006.173.13:52:03.54#ibcon#end of sib2, iclass 16, count 0 2006.173.13:52:03.54#ibcon#*after write, iclass 16, count 0 2006.173.13:52:03.54#ibcon#*before return 0, iclass 16, count 0 2006.173.13:52:03.54#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.13:52:03.54#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.13:52:03.54#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.13:52:03.54#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.13:52:03.54$vck44/va=1,7 2006.173.13:52:03.54#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.13:52:03.54#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.13:52:03.54#ibcon#ireg 11 cls_cnt 2 2006.173.13:52:03.54#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.13:52:03.54#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.13:52:03.54#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.13:52:03.54#ibcon#enter wrdev, iclass 18, count 2 2006.173.13:52:03.54#ibcon#first serial, iclass 18, count 2 2006.173.13:52:03.54#ibcon#enter sib2, iclass 18, count 2 2006.173.13:52:03.54#ibcon#flushed, iclass 18, count 2 2006.173.13:52:03.54#ibcon#about to write, iclass 18, count 2 2006.173.13:52:03.54#ibcon#wrote, iclass 18, count 2 2006.173.13:52:03.54#ibcon#about to read 3, iclass 18, count 2 2006.173.13:52:03.56#ibcon#read 3, iclass 18, count 2 2006.173.13:52:03.56#ibcon#about to read 4, iclass 18, count 2 2006.173.13:52:03.56#ibcon#read 4, iclass 18, count 2 2006.173.13:52:03.56#ibcon#about to read 5, iclass 18, count 2 2006.173.13:52:03.56#ibcon#read 5, iclass 18, count 2 2006.173.13:52:03.56#ibcon#about to read 6, iclass 18, count 2 2006.173.13:52:03.56#ibcon#read 6, iclass 18, count 2 2006.173.13:52:03.56#ibcon#end of sib2, iclass 18, count 2 2006.173.13:52:03.56#ibcon#*mode == 0, iclass 18, count 2 2006.173.13:52:03.56#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.13:52:03.56#ibcon#[25=AT01-07\r\n] 2006.173.13:52:03.56#ibcon#*before write, iclass 18, count 2 2006.173.13:52:03.56#ibcon#enter sib2, iclass 18, count 2 2006.173.13:52:03.56#ibcon#flushed, iclass 18, count 2 2006.173.13:52:03.56#ibcon#about to write, iclass 18, count 2 2006.173.13:52:03.56#ibcon#wrote, iclass 18, count 2 2006.173.13:52:03.56#ibcon#about to read 3, iclass 18, count 2 2006.173.13:52:03.59#ibcon#read 3, iclass 18, count 2 2006.173.13:52:03.59#ibcon#about to read 4, iclass 18, count 2 2006.173.13:52:03.59#ibcon#read 4, iclass 18, count 2 2006.173.13:52:03.59#ibcon#about to read 5, iclass 18, count 2 2006.173.13:52:03.59#ibcon#read 5, iclass 18, count 2 2006.173.13:52:03.59#ibcon#about to read 6, iclass 18, count 2 2006.173.13:52:03.59#ibcon#read 6, iclass 18, count 2 2006.173.13:52:03.59#ibcon#end of sib2, iclass 18, count 2 2006.173.13:52:03.59#ibcon#*after write, iclass 18, count 2 2006.173.13:52:03.59#ibcon#*before return 0, iclass 18, count 2 2006.173.13:52:03.59#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.13:52:03.59#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.13:52:03.59#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.13:52:03.59#ibcon#ireg 7 cls_cnt 0 2006.173.13:52:03.59#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.13:52:03.71#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.13:52:03.71#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.13:52:03.71#ibcon#enter wrdev, iclass 18, count 0 2006.173.13:52:03.71#ibcon#first serial, iclass 18, count 0 2006.173.13:52:03.71#ibcon#enter sib2, iclass 18, count 0 2006.173.13:52:03.71#ibcon#flushed, iclass 18, count 0 2006.173.13:52:03.71#ibcon#about to write, iclass 18, count 0 2006.173.13:52:03.71#ibcon#wrote, iclass 18, count 0 2006.173.13:52:03.71#ibcon#about to read 3, iclass 18, count 0 2006.173.13:52:03.73#ibcon#read 3, iclass 18, count 0 2006.173.13:52:03.73#ibcon#about to read 4, iclass 18, count 0 2006.173.13:52:03.73#ibcon#read 4, iclass 18, count 0 2006.173.13:52:03.73#ibcon#about to read 5, iclass 18, count 0 2006.173.13:52:03.73#ibcon#read 5, iclass 18, count 0 2006.173.13:52:03.73#ibcon#about to read 6, iclass 18, count 0 2006.173.13:52:03.73#ibcon#read 6, iclass 18, count 0 2006.173.13:52:03.73#ibcon#end of sib2, iclass 18, count 0 2006.173.13:52:03.73#ibcon#*mode == 0, iclass 18, count 0 2006.173.13:52:03.73#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.13:52:03.73#ibcon#[25=USB\r\n] 2006.173.13:52:03.73#ibcon#*before write, iclass 18, count 0 2006.173.13:52:03.73#ibcon#enter sib2, iclass 18, count 0 2006.173.13:52:03.73#ibcon#flushed, iclass 18, count 0 2006.173.13:52:03.73#ibcon#about to write, iclass 18, count 0 2006.173.13:52:03.73#ibcon#wrote, iclass 18, count 0 2006.173.13:52:03.73#ibcon#about to read 3, iclass 18, count 0 2006.173.13:52:03.76#ibcon#read 3, iclass 18, count 0 2006.173.13:52:03.76#ibcon#about to read 4, iclass 18, count 0 2006.173.13:52:03.76#ibcon#read 4, iclass 18, count 0 2006.173.13:52:03.76#ibcon#about to read 5, iclass 18, count 0 2006.173.13:52:03.76#ibcon#read 5, iclass 18, count 0 2006.173.13:52:03.76#ibcon#about to read 6, iclass 18, count 0 2006.173.13:52:03.76#ibcon#read 6, iclass 18, count 0 2006.173.13:52:03.76#ibcon#end of sib2, iclass 18, count 0 2006.173.13:52:03.76#ibcon#*after write, iclass 18, count 0 2006.173.13:52:03.76#ibcon#*before return 0, iclass 18, count 0 2006.173.13:52:03.76#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.13:52:03.76#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.13:52:03.76#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.13:52:03.76#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.13:52:03.76$vck44/valo=2,534.99 2006.173.13:52:03.76#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.13:52:03.76#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.13:52:03.76#ibcon#ireg 17 cls_cnt 0 2006.173.13:52:03.76#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.13:52:03.76#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.13:52:03.76#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.13:52:03.76#ibcon#enter wrdev, iclass 20, count 0 2006.173.13:52:03.76#ibcon#first serial, iclass 20, count 0 2006.173.13:52:03.76#ibcon#enter sib2, iclass 20, count 0 2006.173.13:52:03.76#ibcon#flushed, iclass 20, count 0 2006.173.13:52:03.76#ibcon#about to write, iclass 20, count 0 2006.173.13:52:03.76#ibcon#wrote, iclass 20, count 0 2006.173.13:52:03.76#ibcon#about to read 3, iclass 20, count 0 2006.173.13:52:03.78#ibcon#read 3, iclass 20, count 0 2006.173.13:52:03.78#ibcon#about to read 4, iclass 20, count 0 2006.173.13:52:03.78#ibcon#read 4, iclass 20, count 0 2006.173.13:52:03.78#ibcon#about to read 5, iclass 20, count 0 2006.173.13:52:03.78#ibcon#read 5, iclass 20, count 0 2006.173.13:52:03.78#ibcon#about to read 6, iclass 20, count 0 2006.173.13:52:03.78#ibcon#read 6, iclass 20, count 0 2006.173.13:52:03.78#ibcon#end of sib2, iclass 20, count 0 2006.173.13:52:03.78#ibcon#*mode == 0, iclass 20, count 0 2006.173.13:52:03.78#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.13:52:03.78#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.13:52:03.78#ibcon#*before write, iclass 20, count 0 2006.173.13:52:03.78#ibcon#enter sib2, iclass 20, count 0 2006.173.13:52:03.78#ibcon#flushed, iclass 20, count 0 2006.173.13:52:03.78#ibcon#about to write, iclass 20, count 0 2006.173.13:52:03.78#ibcon#wrote, iclass 20, count 0 2006.173.13:52:03.78#ibcon#about to read 3, iclass 20, count 0 2006.173.13:52:03.82#ibcon#read 3, iclass 20, count 0 2006.173.13:52:03.82#ibcon#about to read 4, iclass 20, count 0 2006.173.13:52:03.82#ibcon#read 4, iclass 20, count 0 2006.173.13:52:03.82#ibcon#about to read 5, iclass 20, count 0 2006.173.13:52:03.82#ibcon#read 5, iclass 20, count 0 2006.173.13:52:03.82#ibcon#about to read 6, iclass 20, count 0 2006.173.13:52:03.82#ibcon#read 6, iclass 20, count 0 2006.173.13:52:03.82#ibcon#end of sib2, iclass 20, count 0 2006.173.13:52:03.82#ibcon#*after write, iclass 20, count 0 2006.173.13:52:03.82#ibcon#*before return 0, iclass 20, count 0 2006.173.13:52:03.82#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.13:52:03.82#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.13:52:03.82#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.13:52:03.82#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.13:52:03.82$vck44/va=2,6 2006.173.13:52:03.82#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.13:52:03.82#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.13:52:03.82#ibcon#ireg 11 cls_cnt 2 2006.173.13:52:03.82#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.13:52:03.88#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.13:52:03.88#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.13:52:03.88#ibcon#enter wrdev, iclass 22, count 2 2006.173.13:52:03.88#ibcon#first serial, iclass 22, count 2 2006.173.13:52:03.88#ibcon#enter sib2, iclass 22, count 2 2006.173.13:52:03.88#ibcon#flushed, iclass 22, count 2 2006.173.13:52:03.88#ibcon#about to write, iclass 22, count 2 2006.173.13:52:03.88#ibcon#wrote, iclass 22, count 2 2006.173.13:52:03.88#ibcon#about to read 3, iclass 22, count 2 2006.173.13:52:03.90#ibcon#read 3, iclass 22, count 2 2006.173.13:52:03.90#ibcon#about to read 4, iclass 22, count 2 2006.173.13:52:03.90#ibcon#read 4, iclass 22, count 2 2006.173.13:52:03.90#ibcon#about to read 5, iclass 22, count 2 2006.173.13:52:03.90#ibcon#read 5, iclass 22, count 2 2006.173.13:52:03.90#ibcon#about to read 6, iclass 22, count 2 2006.173.13:52:03.90#ibcon#read 6, iclass 22, count 2 2006.173.13:52:03.90#ibcon#end of sib2, iclass 22, count 2 2006.173.13:52:03.90#ibcon#*mode == 0, iclass 22, count 2 2006.173.13:52:03.90#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.13:52:03.90#ibcon#[25=AT02-06\r\n] 2006.173.13:52:03.90#ibcon#*before write, iclass 22, count 2 2006.173.13:52:03.90#ibcon#enter sib2, iclass 22, count 2 2006.173.13:52:03.90#ibcon#flushed, iclass 22, count 2 2006.173.13:52:03.90#ibcon#about to write, iclass 22, count 2 2006.173.13:52:03.90#ibcon#wrote, iclass 22, count 2 2006.173.13:52:03.90#ibcon#about to read 3, iclass 22, count 2 2006.173.13:52:03.93#ibcon#read 3, iclass 22, count 2 2006.173.13:52:03.93#ibcon#about to read 4, iclass 22, count 2 2006.173.13:52:03.93#ibcon#read 4, iclass 22, count 2 2006.173.13:52:03.93#ibcon#about to read 5, iclass 22, count 2 2006.173.13:52:03.93#ibcon#read 5, iclass 22, count 2 2006.173.13:52:03.93#ibcon#about to read 6, iclass 22, count 2 2006.173.13:52:03.93#ibcon#read 6, iclass 22, count 2 2006.173.13:52:03.93#ibcon#end of sib2, iclass 22, count 2 2006.173.13:52:03.93#ibcon#*after write, iclass 22, count 2 2006.173.13:52:03.93#ibcon#*before return 0, iclass 22, count 2 2006.173.13:52:03.93#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.13:52:03.93#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.13:52:03.93#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.13:52:03.93#ibcon#ireg 7 cls_cnt 0 2006.173.13:52:03.93#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.13:52:04.05#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.13:52:04.05#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.13:52:04.05#ibcon#enter wrdev, iclass 22, count 0 2006.173.13:52:04.05#ibcon#first serial, iclass 22, count 0 2006.173.13:52:04.05#ibcon#enter sib2, iclass 22, count 0 2006.173.13:52:04.05#ibcon#flushed, iclass 22, count 0 2006.173.13:52:04.05#ibcon#about to write, iclass 22, count 0 2006.173.13:52:04.05#ibcon#wrote, iclass 22, count 0 2006.173.13:52:04.05#ibcon#about to read 3, iclass 22, count 0 2006.173.13:52:04.07#ibcon#read 3, iclass 22, count 0 2006.173.13:52:04.07#ibcon#about to read 4, iclass 22, count 0 2006.173.13:52:04.07#ibcon#read 4, iclass 22, count 0 2006.173.13:52:04.07#ibcon#about to read 5, iclass 22, count 0 2006.173.13:52:04.07#ibcon#read 5, iclass 22, count 0 2006.173.13:52:04.07#ibcon#about to read 6, iclass 22, count 0 2006.173.13:52:04.07#ibcon#read 6, iclass 22, count 0 2006.173.13:52:04.07#ibcon#end of sib2, iclass 22, count 0 2006.173.13:52:04.07#ibcon#*mode == 0, iclass 22, count 0 2006.173.13:52:04.07#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.13:52:04.07#ibcon#[25=USB\r\n] 2006.173.13:52:04.07#ibcon#*before write, iclass 22, count 0 2006.173.13:52:04.07#ibcon#enter sib2, iclass 22, count 0 2006.173.13:52:04.07#ibcon#flushed, iclass 22, count 0 2006.173.13:52:04.07#ibcon#about to write, iclass 22, count 0 2006.173.13:52:04.07#ibcon#wrote, iclass 22, count 0 2006.173.13:52:04.07#ibcon#about to read 3, iclass 22, count 0 2006.173.13:52:04.07#abcon#<5=/05 0.6 1.1 21.851001003.7\r\n> 2006.173.13:52:04.09#abcon#{5=INTERFACE CLEAR} 2006.173.13:52:04.10#ibcon#read 3, iclass 22, count 0 2006.173.13:52:04.10#ibcon#about to read 4, iclass 22, count 0 2006.173.13:52:04.10#ibcon#read 4, iclass 22, count 0 2006.173.13:52:04.10#ibcon#about to read 5, iclass 22, count 0 2006.173.13:52:04.10#ibcon#read 5, iclass 22, count 0 2006.173.13:52:04.10#ibcon#about to read 6, iclass 22, count 0 2006.173.13:52:04.10#ibcon#read 6, iclass 22, count 0 2006.173.13:52:04.10#ibcon#end of sib2, iclass 22, count 0 2006.173.13:52:04.10#ibcon#*after write, iclass 22, count 0 2006.173.13:52:04.10#ibcon#*before return 0, iclass 22, count 0 2006.173.13:52:04.10#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.13:52:04.10#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.13:52:04.10#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.13:52:04.10#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.13:52:04.10$vck44/valo=3,564.99 2006.173.13:52:04.10#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.13:52:04.10#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.13:52:04.10#ibcon#ireg 17 cls_cnt 0 2006.173.13:52:04.10#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.13:52:04.10#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.13:52:04.10#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.13:52:04.10#ibcon#enter wrdev, iclass 27, count 0 2006.173.13:52:04.10#ibcon#first serial, iclass 27, count 0 2006.173.13:52:04.10#ibcon#enter sib2, iclass 27, count 0 2006.173.13:52:04.10#ibcon#flushed, iclass 27, count 0 2006.173.13:52:04.10#ibcon#about to write, iclass 27, count 0 2006.173.13:52:04.10#ibcon#wrote, iclass 27, count 0 2006.173.13:52:04.10#ibcon#about to read 3, iclass 27, count 0 2006.173.13:52:04.12#ibcon#read 3, iclass 27, count 0 2006.173.13:52:04.12#ibcon#about to read 4, iclass 27, count 0 2006.173.13:52:04.12#ibcon#read 4, iclass 27, count 0 2006.173.13:52:04.12#ibcon#about to read 5, iclass 27, count 0 2006.173.13:52:04.12#ibcon#read 5, iclass 27, count 0 2006.173.13:52:04.12#ibcon#about to read 6, iclass 27, count 0 2006.173.13:52:04.12#ibcon#read 6, iclass 27, count 0 2006.173.13:52:04.12#ibcon#end of sib2, iclass 27, count 0 2006.173.13:52:04.12#ibcon#*mode == 0, iclass 27, count 0 2006.173.13:52:04.12#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.13:52:04.12#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.13:52:04.12#ibcon#*before write, iclass 27, count 0 2006.173.13:52:04.12#ibcon#enter sib2, iclass 27, count 0 2006.173.13:52:04.12#ibcon#flushed, iclass 27, count 0 2006.173.13:52:04.12#ibcon#about to write, iclass 27, count 0 2006.173.13:52:04.12#ibcon#wrote, iclass 27, count 0 2006.173.13:52:04.12#ibcon#about to read 3, iclass 27, count 0 2006.173.13:52:04.15#abcon#[5=S1D000X0/0*\r\n] 2006.173.13:52:04.16#ibcon#read 3, iclass 27, count 0 2006.173.13:52:04.16#ibcon#about to read 4, iclass 27, count 0 2006.173.13:52:04.16#ibcon#read 4, iclass 27, count 0 2006.173.13:52:04.16#ibcon#about to read 5, iclass 27, count 0 2006.173.13:52:04.16#ibcon#read 5, iclass 27, count 0 2006.173.13:52:04.16#ibcon#about to read 6, iclass 27, count 0 2006.173.13:52:04.16#ibcon#read 6, iclass 27, count 0 2006.173.13:52:04.16#ibcon#end of sib2, iclass 27, count 0 2006.173.13:52:04.16#ibcon#*after write, iclass 27, count 0 2006.173.13:52:04.16#ibcon#*before return 0, iclass 27, count 0 2006.173.13:52:04.16#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.13:52:04.16#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.13:52:04.16#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.13:52:04.16#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.13:52:04.16$vck44/va=3,5 2006.173.13:52:04.16#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.13:52:04.16#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.13:52:04.16#ibcon#ireg 11 cls_cnt 2 2006.173.13:52:04.16#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.13:52:04.22#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.13:52:04.22#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.13:52:04.22#ibcon#enter wrdev, iclass 30, count 2 2006.173.13:52:04.22#ibcon#first serial, iclass 30, count 2 2006.173.13:52:04.22#ibcon#enter sib2, iclass 30, count 2 2006.173.13:52:04.22#ibcon#flushed, iclass 30, count 2 2006.173.13:52:04.22#ibcon#about to write, iclass 30, count 2 2006.173.13:52:04.22#ibcon#wrote, iclass 30, count 2 2006.173.13:52:04.22#ibcon#about to read 3, iclass 30, count 2 2006.173.13:52:04.24#ibcon#read 3, iclass 30, count 2 2006.173.13:52:04.24#ibcon#about to read 4, iclass 30, count 2 2006.173.13:52:04.24#ibcon#read 4, iclass 30, count 2 2006.173.13:52:04.24#ibcon#about to read 5, iclass 30, count 2 2006.173.13:52:04.24#ibcon#read 5, iclass 30, count 2 2006.173.13:52:04.24#ibcon#about to read 6, iclass 30, count 2 2006.173.13:52:04.24#ibcon#read 6, iclass 30, count 2 2006.173.13:52:04.24#ibcon#end of sib2, iclass 30, count 2 2006.173.13:52:04.24#ibcon#*mode == 0, iclass 30, count 2 2006.173.13:52:04.24#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.13:52:04.24#ibcon#[25=AT03-05\r\n] 2006.173.13:52:04.24#ibcon#*before write, iclass 30, count 2 2006.173.13:52:04.24#ibcon#enter sib2, iclass 30, count 2 2006.173.13:52:04.24#ibcon#flushed, iclass 30, count 2 2006.173.13:52:04.24#ibcon#about to write, iclass 30, count 2 2006.173.13:52:04.24#ibcon#wrote, iclass 30, count 2 2006.173.13:52:04.24#ibcon#about to read 3, iclass 30, count 2 2006.173.13:52:04.27#ibcon#read 3, iclass 30, count 2 2006.173.13:52:04.27#ibcon#about to read 4, iclass 30, count 2 2006.173.13:52:04.27#ibcon#read 4, iclass 30, count 2 2006.173.13:52:04.27#ibcon#about to read 5, iclass 30, count 2 2006.173.13:52:04.27#ibcon#read 5, iclass 30, count 2 2006.173.13:52:04.27#ibcon#about to read 6, iclass 30, count 2 2006.173.13:52:04.27#ibcon#read 6, iclass 30, count 2 2006.173.13:52:04.27#ibcon#end of sib2, iclass 30, count 2 2006.173.13:52:04.27#ibcon#*after write, iclass 30, count 2 2006.173.13:52:04.27#ibcon#*before return 0, iclass 30, count 2 2006.173.13:52:04.27#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.13:52:04.27#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.13:52:04.27#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.13:52:04.27#ibcon#ireg 7 cls_cnt 0 2006.173.13:52:04.27#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.13:52:04.39#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.13:52:04.39#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.13:52:04.39#ibcon#enter wrdev, iclass 30, count 0 2006.173.13:52:04.39#ibcon#first serial, iclass 30, count 0 2006.173.13:52:04.39#ibcon#enter sib2, iclass 30, count 0 2006.173.13:52:04.39#ibcon#flushed, iclass 30, count 0 2006.173.13:52:04.39#ibcon#about to write, iclass 30, count 0 2006.173.13:52:04.39#ibcon#wrote, iclass 30, count 0 2006.173.13:52:04.39#ibcon#about to read 3, iclass 30, count 0 2006.173.13:52:04.41#ibcon#read 3, iclass 30, count 0 2006.173.13:52:04.41#ibcon#about to read 4, iclass 30, count 0 2006.173.13:52:04.41#ibcon#read 4, iclass 30, count 0 2006.173.13:52:04.41#ibcon#about to read 5, iclass 30, count 0 2006.173.13:52:04.41#ibcon#read 5, iclass 30, count 0 2006.173.13:52:04.41#ibcon#about to read 6, iclass 30, count 0 2006.173.13:52:04.41#ibcon#read 6, iclass 30, count 0 2006.173.13:52:04.41#ibcon#end of sib2, iclass 30, count 0 2006.173.13:52:04.41#ibcon#*mode == 0, iclass 30, count 0 2006.173.13:52:04.41#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.13:52:04.41#ibcon#[25=USB\r\n] 2006.173.13:52:04.41#ibcon#*before write, iclass 30, count 0 2006.173.13:52:04.41#ibcon#enter sib2, iclass 30, count 0 2006.173.13:52:04.41#ibcon#flushed, iclass 30, count 0 2006.173.13:52:04.41#ibcon#about to write, iclass 30, count 0 2006.173.13:52:04.41#ibcon#wrote, iclass 30, count 0 2006.173.13:52:04.41#ibcon#about to read 3, iclass 30, count 0 2006.173.13:52:04.44#ibcon#read 3, iclass 30, count 0 2006.173.13:52:04.44#ibcon#about to read 4, iclass 30, count 0 2006.173.13:52:04.44#ibcon#read 4, iclass 30, count 0 2006.173.13:52:04.44#ibcon#about to read 5, iclass 30, count 0 2006.173.13:52:04.44#ibcon#read 5, iclass 30, count 0 2006.173.13:52:04.44#ibcon#about to read 6, iclass 30, count 0 2006.173.13:52:04.44#ibcon#read 6, iclass 30, count 0 2006.173.13:52:04.44#ibcon#end of sib2, iclass 30, count 0 2006.173.13:52:04.44#ibcon#*after write, iclass 30, count 0 2006.173.13:52:04.44#ibcon#*before return 0, iclass 30, count 0 2006.173.13:52:04.44#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.13:52:04.44#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.13:52:04.44#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.13:52:04.44#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.13:52:04.44$vck44/valo=4,624.99 2006.173.13:52:04.44#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.13:52:04.44#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.13:52:04.44#ibcon#ireg 17 cls_cnt 0 2006.173.13:52:04.44#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.13:52:04.44#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.13:52:04.44#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.13:52:04.44#ibcon#enter wrdev, iclass 32, count 0 2006.173.13:52:04.44#ibcon#first serial, iclass 32, count 0 2006.173.13:52:04.44#ibcon#enter sib2, iclass 32, count 0 2006.173.13:52:04.44#ibcon#flushed, iclass 32, count 0 2006.173.13:52:04.44#ibcon#about to write, iclass 32, count 0 2006.173.13:52:04.44#ibcon#wrote, iclass 32, count 0 2006.173.13:52:04.44#ibcon#about to read 3, iclass 32, count 0 2006.173.13:52:04.46#ibcon#read 3, iclass 32, count 0 2006.173.13:52:04.46#ibcon#about to read 4, iclass 32, count 0 2006.173.13:52:04.46#ibcon#read 4, iclass 32, count 0 2006.173.13:52:04.46#ibcon#about to read 5, iclass 32, count 0 2006.173.13:52:04.46#ibcon#read 5, iclass 32, count 0 2006.173.13:52:04.46#ibcon#about to read 6, iclass 32, count 0 2006.173.13:52:04.46#ibcon#read 6, iclass 32, count 0 2006.173.13:52:04.46#ibcon#end of sib2, iclass 32, count 0 2006.173.13:52:04.46#ibcon#*mode == 0, iclass 32, count 0 2006.173.13:52:04.46#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.13:52:04.46#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.13:52:04.46#ibcon#*before write, iclass 32, count 0 2006.173.13:52:04.46#ibcon#enter sib2, iclass 32, count 0 2006.173.13:52:04.46#ibcon#flushed, iclass 32, count 0 2006.173.13:52:04.46#ibcon#about to write, iclass 32, count 0 2006.173.13:52:04.46#ibcon#wrote, iclass 32, count 0 2006.173.13:52:04.46#ibcon#about to read 3, iclass 32, count 0 2006.173.13:52:04.50#ibcon#read 3, iclass 32, count 0 2006.173.13:52:04.50#ibcon#about to read 4, iclass 32, count 0 2006.173.13:52:04.50#ibcon#read 4, iclass 32, count 0 2006.173.13:52:04.50#ibcon#about to read 5, iclass 32, count 0 2006.173.13:52:04.50#ibcon#read 5, iclass 32, count 0 2006.173.13:52:04.50#ibcon#about to read 6, iclass 32, count 0 2006.173.13:52:04.50#ibcon#read 6, iclass 32, count 0 2006.173.13:52:04.50#ibcon#end of sib2, iclass 32, count 0 2006.173.13:52:04.50#ibcon#*after write, iclass 32, count 0 2006.173.13:52:04.50#ibcon#*before return 0, iclass 32, count 0 2006.173.13:52:04.50#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.13:52:04.50#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.13:52:04.50#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.13:52:04.50#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.13:52:04.50$vck44/va=4,6 2006.173.13:52:04.50#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.13:52:04.50#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.13:52:04.50#ibcon#ireg 11 cls_cnt 2 2006.173.13:52:04.50#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.13:52:04.56#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.13:52:04.56#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.13:52:04.56#ibcon#enter wrdev, iclass 34, count 2 2006.173.13:52:04.56#ibcon#first serial, iclass 34, count 2 2006.173.13:52:04.56#ibcon#enter sib2, iclass 34, count 2 2006.173.13:52:04.56#ibcon#flushed, iclass 34, count 2 2006.173.13:52:04.56#ibcon#about to write, iclass 34, count 2 2006.173.13:52:04.56#ibcon#wrote, iclass 34, count 2 2006.173.13:52:04.56#ibcon#about to read 3, iclass 34, count 2 2006.173.13:52:04.58#ibcon#read 3, iclass 34, count 2 2006.173.13:52:04.58#ibcon#about to read 4, iclass 34, count 2 2006.173.13:52:04.58#ibcon#read 4, iclass 34, count 2 2006.173.13:52:04.58#ibcon#about to read 5, iclass 34, count 2 2006.173.13:52:04.58#ibcon#read 5, iclass 34, count 2 2006.173.13:52:04.58#ibcon#about to read 6, iclass 34, count 2 2006.173.13:52:04.58#ibcon#read 6, iclass 34, count 2 2006.173.13:52:04.58#ibcon#end of sib2, iclass 34, count 2 2006.173.13:52:04.58#ibcon#*mode == 0, iclass 34, count 2 2006.173.13:52:04.58#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.13:52:04.58#ibcon#[25=AT04-06\r\n] 2006.173.13:52:04.58#ibcon#*before write, iclass 34, count 2 2006.173.13:52:04.58#ibcon#enter sib2, iclass 34, count 2 2006.173.13:52:04.58#ibcon#flushed, iclass 34, count 2 2006.173.13:52:04.58#ibcon#about to write, iclass 34, count 2 2006.173.13:52:04.58#ibcon#wrote, iclass 34, count 2 2006.173.13:52:04.58#ibcon#about to read 3, iclass 34, count 2 2006.173.13:52:04.61#ibcon#read 3, iclass 34, count 2 2006.173.13:52:04.61#ibcon#about to read 4, iclass 34, count 2 2006.173.13:52:04.61#ibcon#read 4, iclass 34, count 2 2006.173.13:52:04.61#ibcon#about to read 5, iclass 34, count 2 2006.173.13:52:04.61#ibcon#read 5, iclass 34, count 2 2006.173.13:52:04.61#ibcon#about to read 6, iclass 34, count 2 2006.173.13:52:04.61#ibcon#read 6, iclass 34, count 2 2006.173.13:52:04.61#ibcon#end of sib2, iclass 34, count 2 2006.173.13:52:04.61#ibcon#*after write, iclass 34, count 2 2006.173.13:52:04.61#ibcon#*before return 0, iclass 34, count 2 2006.173.13:52:04.61#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.13:52:04.61#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.13:52:04.61#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.13:52:04.61#ibcon#ireg 7 cls_cnt 0 2006.173.13:52:04.61#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.13:52:04.73#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.13:52:04.73#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.13:52:04.73#ibcon#enter wrdev, iclass 34, count 0 2006.173.13:52:04.73#ibcon#first serial, iclass 34, count 0 2006.173.13:52:04.73#ibcon#enter sib2, iclass 34, count 0 2006.173.13:52:04.73#ibcon#flushed, iclass 34, count 0 2006.173.13:52:04.73#ibcon#about to write, iclass 34, count 0 2006.173.13:52:04.73#ibcon#wrote, iclass 34, count 0 2006.173.13:52:04.73#ibcon#about to read 3, iclass 34, count 0 2006.173.13:52:04.75#ibcon#read 3, iclass 34, count 0 2006.173.13:52:04.75#ibcon#about to read 4, iclass 34, count 0 2006.173.13:52:04.75#ibcon#read 4, iclass 34, count 0 2006.173.13:52:04.75#ibcon#about to read 5, iclass 34, count 0 2006.173.13:52:04.75#ibcon#read 5, iclass 34, count 0 2006.173.13:52:04.75#ibcon#about to read 6, iclass 34, count 0 2006.173.13:52:04.75#ibcon#read 6, iclass 34, count 0 2006.173.13:52:04.75#ibcon#end of sib2, iclass 34, count 0 2006.173.13:52:04.75#ibcon#*mode == 0, iclass 34, count 0 2006.173.13:52:04.75#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.13:52:04.75#ibcon#[25=USB\r\n] 2006.173.13:52:04.75#ibcon#*before write, iclass 34, count 0 2006.173.13:52:04.75#ibcon#enter sib2, iclass 34, count 0 2006.173.13:52:04.75#ibcon#flushed, iclass 34, count 0 2006.173.13:52:04.75#ibcon#about to write, iclass 34, count 0 2006.173.13:52:04.75#ibcon#wrote, iclass 34, count 0 2006.173.13:52:04.75#ibcon#about to read 3, iclass 34, count 0 2006.173.13:52:04.78#ibcon#read 3, iclass 34, count 0 2006.173.13:52:04.78#ibcon#about to read 4, iclass 34, count 0 2006.173.13:52:04.78#ibcon#read 4, iclass 34, count 0 2006.173.13:52:04.78#ibcon#about to read 5, iclass 34, count 0 2006.173.13:52:04.78#ibcon#read 5, iclass 34, count 0 2006.173.13:52:04.78#ibcon#about to read 6, iclass 34, count 0 2006.173.13:52:04.78#ibcon#read 6, iclass 34, count 0 2006.173.13:52:04.78#ibcon#end of sib2, iclass 34, count 0 2006.173.13:52:04.78#ibcon#*after write, iclass 34, count 0 2006.173.13:52:04.78#ibcon#*before return 0, iclass 34, count 0 2006.173.13:52:04.78#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.13:52:04.78#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.13:52:04.78#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.13:52:04.78#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.13:52:04.78$vck44/valo=5,734.99 2006.173.13:52:04.78#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.13:52:04.78#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.13:52:04.78#ibcon#ireg 17 cls_cnt 0 2006.173.13:52:04.78#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.13:52:04.78#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.13:52:04.78#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.13:52:04.78#ibcon#enter wrdev, iclass 36, count 0 2006.173.13:52:04.78#ibcon#first serial, iclass 36, count 0 2006.173.13:52:04.78#ibcon#enter sib2, iclass 36, count 0 2006.173.13:52:04.78#ibcon#flushed, iclass 36, count 0 2006.173.13:52:04.78#ibcon#about to write, iclass 36, count 0 2006.173.13:52:04.78#ibcon#wrote, iclass 36, count 0 2006.173.13:52:04.78#ibcon#about to read 3, iclass 36, count 0 2006.173.13:52:04.80#ibcon#read 3, iclass 36, count 0 2006.173.13:52:04.80#ibcon#about to read 4, iclass 36, count 0 2006.173.13:52:04.80#ibcon#read 4, iclass 36, count 0 2006.173.13:52:04.80#ibcon#about to read 5, iclass 36, count 0 2006.173.13:52:04.80#ibcon#read 5, iclass 36, count 0 2006.173.13:52:04.80#ibcon#about to read 6, iclass 36, count 0 2006.173.13:52:04.80#ibcon#read 6, iclass 36, count 0 2006.173.13:52:04.80#ibcon#end of sib2, iclass 36, count 0 2006.173.13:52:04.80#ibcon#*mode == 0, iclass 36, count 0 2006.173.13:52:04.80#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.13:52:04.80#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.13:52:04.80#ibcon#*before write, iclass 36, count 0 2006.173.13:52:04.80#ibcon#enter sib2, iclass 36, count 0 2006.173.13:52:04.80#ibcon#flushed, iclass 36, count 0 2006.173.13:52:04.80#ibcon#about to write, iclass 36, count 0 2006.173.13:52:04.80#ibcon#wrote, iclass 36, count 0 2006.173.13:52:04.80#ibcon#about to read 3, iclass 36, count 0 2006.173.13:52:04.84#ibcon#read 3, iclass 36, count 0 2006.173.13:52:04.84#ibcon#about to read 4, iclass 36, count 0 2006.173.13:52:04.84#ibcon#read 4, iclass 36, count 0 2006.173.13:52:04.84#ibcon#about to read 5, iclass 36, count 0 2006.173.13:52:04.84#ibcon#read 5, iclass 36, count 0 2006.173.13:52:04.84#ibcon#about to read 6, iclass 36, count 0 2006.173.13:52:04.84#ibcon#read 6, iclass 36, count 0 2006.173.13:52:04.84#ibcon#end of sib2, iclass 36, count 0 2006.173.13:52:04.84#ibcon#*after write, iclass 36, count 0 2006.173.13:52:04.84#ibcon#*before return 0, iclass 36, count 0 2006.173.13:52:04.84#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.13:52:04.84#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.13:52:04.84#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.13:52:04.84#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.13:52:04.84$vck44/va=5,4 2006.173.13:52:04.84#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.13:52:04.84#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.13:52:04.84#ibcon#ireg 11 cls_cnt 2 2006.173.13:52:04.84#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.13:52:04.90#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.13:52:04.90#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.13:52:04.90#ibcon#enter wrdev, iclass 38, count 2 2006.173.13:52:04.90#ibcon#first serial, iclass 38, count 2 2006.173.13:52:04.90#ibcon#enter sib2, iclass 38, count 2 2006.173.13:52:04.90#ibcon#flushed, iclass 38, count 2 2006.173.13:52:04.90#ibcon#about to write, iclass 38, count 2 2006.173.13:52:04.90#ibcon#wrote, iclass 38, count 2 2006.173.13:52:04.90#ibcon#about to read 3, iclass 38, count 2 2006.173.13:52:04.92#ibcon#read 3, iclass 38, count 2 2006.173.13:52:04.92#ibcon#about to read 4, iclass 38, count 2 2006.173.13:52:04.92#ibcon#read 4, iclass 38, count 2 2006.173.13:52:04.92#ibcon#about to read 5, iclass 38, count 2 2006.173.13:52:04.92#ibcon#read 5, iclass 38, count 2 2006.173.13:52:04.92#ibcon#about to read 6, iclass 38, count 2 2006.173.13:52:04.92#ibcon#read 6, iclass 38, count 2 2006.173.13:52:04.92#ibcon#end of sib2, iclass 38, count 2 2006.173.13:52:04.92#ibcon#*mode == 0, iclass 38, count 2 2006.173.13:52:04.92#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.13:52:04.92#ibcon#[25=AT05-04\r\n] 2006.173.13:52:04.92#ibcon#*before write, iclass 38, count 2 2006.173.13:52:04.92#ibcon#enter sib2, iclass 38, count 2 2006.173.13:52:04.92#ibcon#flushed, iclass 38, count 2 2006.173.13:52:04.92#ibcon#about to write, iclass 38, count 2 2006.173.13:52:04.92#ibcon#wrote, iclass 38, count 2 2006.173.13:52:04.92#ibcon#about to read 3, iclass 38, count 2 2006.173.13:52:04.95#ibcon#read 3, iclass 38, count 2 2006.173.13:52:04.95#ibcon#about to read 4, iclass 38, count 2 2006.173.13:52:04.95#ibcon#read 4, iclass 38, count 2 2006.173.13:52:04.95#ibcon#about to read 5, iclass 38, count 2 2006.173.13:52:04.95#ibcon#read 5, iclass 38, count 2 2006.173.13:52:04.95#ibcon#about to read 6, iclass 38, count 2 2006.173.13:52:04.95#ibcon#read 6, iclass 38, count 2 2006.173.13:52:04.95#ibcon#end of sib2, iclass 38, count 2 2006.173.13:52:04.95#ibcon#*after write, iclass 38, count 2 2006.173.13:52:04.95#ibcon#*before return 0, iclass 38, count 2 2006.173.13:52:04.95#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.13:52:04.95#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.13:52:04.95#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.13:52:04.95#ibcon#ireg 7 cls_cnt 0 2006.173.13:52:04.95#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.13:52:05.07#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.13:52:05.07#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.13:52:05.07#ibcon#enter wrdev, iclass 38, count 0 2006.173.13:52:05.07#ibcon#first serial, iclass 38, count 0 2006.173.13:52:05.07#ibcon#enter sib2, iclass 38, count 0 2006.173.13:52:05.07#ibcon#flushed, iclass 38, count 0 2006.173.13:52:05.07#ibcon#about to write, iclass 38, count 0 2006.173.13:52:05.07#ibcon#wrote, iclass 38, count 0 2006.173.13:52:05.07#ibcon#about to read 3, iclass 38, count 0 2006.173.13:52:05.09#ibcon#read 3, iclass 38, count 0 2006.173.13:52:05.09#ibcon#about to read 4, iclass 38, count 0 2006.173.13:52:05.09#ibcon#read 4, iclass 38, count 0 2006.173.13:52:05.09#ibcon#about to read 5, iclass 38, count 0 2006.173.13:52:05.09#ibcon#read 5, iclass 38, count 0 2006.173.13:52:05.09#ibcon#about to read 6, iclass 38, count 0 2006.173.13:52:05.09#ibcon#read 6, iclass 38, count 0 2006.173.13:52:05.09#ibcon#end of sib2, iclass 38, count 0 2006.173.13:52:05.09#ibcon#*mode == 0, iclass 38, count 0 2006.173.13:52:05.09#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.13:52:05.09#ibcon#[25=USB\r\n] 2006.173.13:52:05.09#ibcon#*before write, iclass 38, count 0 2006.173.13:52:05.09#ibcon#enter sib2, iclass 38, count 0 2006.173.13:52:05.09#ibcon#flushed, iclass 38, count 0 2006.173.13:52:05.09#ibcon#about to write, iclass 38, count 0 2006.173.13:52:05.09#ibcon#wrote, iclass 38, count 0 2006.173.13:52:05.09#ibcon#about to read 3, iclass 38, count 0 2006.173.13:52:05.12#ibcon#read 3, iclass 38, count 0 2006.173.13:52:05.12#ibcon#about to read 4, iclass 38, count 0 2006.173.13:52:05.12#ibcon#read 4, iclass 38, count 0 2006.173.13:52:05.12#ibcon#about to read 5, iclass 38, count 0 2006.173.13:52:05.12#ibcon#read 5, iclass 38, count 0 2006.173.13:52:05.12#ibcon#about to read 6, iclass 38, count 0 2006.173.13:52:05.12#ibcon#read 6, iclass 38, count 0 2006.173.13:52:05.12#ibcon#end of sib2, iclass 38, count 0 2006.173.13:52:05.12#ibcon#*after write, iclass 38, count 0 2006.173.13:52:05.12#ibcon#*before return 0, iclass 38, count 0 2006.173.13:52:05.12#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.13:52:05.12#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.13:52:05.12#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.13:52:05.12#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.13:52:05.12$vck44/valo=6,814.99 2006.173.13:52:05.12#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.13:52:05.12#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.13:52:05.12#ibcon#ireg 17 cls_cnt 0 2006.173.13:52:05.12#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.13:52:05.12#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.13:52:05.12#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.13:52:05.12#ibcon#enter wrdev, iclass 40, count 0 2006.173.13:52:05.12#ibcon#first serial, iclass 40, count 0 2006.173.13:52:05.12#ibcon#enter sib2, iclass 40, count 0 2006.173.13:52:05.12#ibcon#flushed, iclass 40, count 0 2006.173.13:52:05.12#ibcon#about to write, iclass 40, count 0 2006.173.13:52:05.12#ibcon#wrote, iclass 40, count 0 2006.173.13:52:05.12#ibcon#about to read 3, iclass 40, count 0 2006.173.13:52:05.14#ibcon#read 3, iclass 40, count 0 2006.173.13:52:05.14#ibcon#about to read 4, iclass 40, count 0 2006.173.13:52:05.14#ibcon#read 4, iclass 40, count 0 2006.173.13:52:05.14#ibcon#about to read 5, iclass 40, count 0 2006.173.13:52:05.14#ibcon#read 5, iclass 40, count 0 2006.173.13:52:05.14#ibcon#about to read 6, iclass 40, count 0 2006.173.13:52:05.14#ibcon#read 6, iclass 40, count 0 2006.173.13:52:05.14#ibcon#end of sib2, iclass 40, count 0 2006.173.13:52:05.14#ibcon#*mode == 0, iclass 40, count 0 2006.173.13:52:05.14#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.13:52:05.14#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.13:52:05.14#ibcon#*before write, iclass 40, count 0 2006.173.13:52:05.14#ibcon#enter sib2, iclass 40, count 0 2006.173.13:52:05.14#ibcon#flushed, iclass 40, count 0 2006.173.13:52:05.14#ibcon#about to write, iclass 40, count 0 2006.173.13:52:05.14#ibcon#wrote, iclass 40, count 0 2006.173.13:52:05.14#ibcon#about to read 3, iclass 40, count 0 2006.173.13:52:05.18#ibcon#read 3, iclass 40, count 0 2006.173.13:52:05.18#ibcon#about to read 4, iclass 40, count 0 2006.173.13:52:05.18#ibcon#read 4, iclass 40, count 0 2006.173.13:52:05.18#ibcon#about to read 5, iclass 40, count 0 2006.173.13:52:05.18#ibcon#read 5, iclass 40, count 0 2006.173.13:52:05.18#ibcon#about to read 6, iclass 40, count 0 2006.173.13:52:05.18#ibcon#read 6, iclass 40, count 0 2006.173.13:52:05.18#ibcon#end of sib2, iclass 40, count 0 2006.173.13:52:05.18#ibcon#*after write, iclass 40, count 0 2006.173.13:52:05.18#ibcon#*before return 0, iclass 40, count 0 2006.173.13:52:05.18#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.13:52:05.18#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.13:52:05.18#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.13:52:05.18#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.13:52:05.18$vck44/va=6,3 2006.173.13:52:05.18#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.13:52:05.18#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.13:52:05.18#ibcon#ireg 11 cls_cnt 2 2006.173.13:52:05.18#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.13:52:05.24#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.13:52:05.24#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.13:52:05.24#ibcon#enter wrdev, iclass 4, count 2 2006.173.13:52:05.24#ibcon#first serial, iclass 4, count 2 2006.173.13:52:05.24#ibcon#enter sib2, iclass 4, count 2 2006.173.13:52:05.24#ibcon#flushed, iclass 4, count 2 2006.173.13:52:05.24#ibcon#about to write, iclass 4, count 2 2006.173.13:52:05.24#ibcon#wrote, iclass 4, count 2 2006.173.13:52:05.24#ibcon#about to read 3, iclass 4, count 2 2006.173.13:52:05.26#ibcon#read 3, iclass 4, count 2 2006.173.13:52:05.26#ibcon#about to read 4, iclass 4, count 2 2006.173.13:52:05.26#ibcon#read 4, iclass 4, count 2 2006.173.13:52:05.26#ibcon#about to read 5, iclass 4, count 2 2006.173.13:52:05.26#ibcon#read 5, iclass 4, count 2 2006.173.13:52:05.26#ibcon#about to read 6, iclass 4, count 2 2006.173.13:52:05.26#ibcon#read 6, iclass 4, count 2 2006.173.13:52:05.26#ibcon#end of sib2, iclass 4, count 2 2006.173.13:52:05.26#ibcon#*mode == 0, iclass 4, count 2 2006.173.13:52:05.26#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.13:52:05.26#ibcon#[25=AT06-03\r\n] 2006.173.13:52:05.26#ibcon#*before write, iclass 4, count 2 2006.173.13:52:05.26#ibcon#enter sib2, iclass 4, count 2 2006.173.13:52:05.26#ibcon#flushed, iclass 4, count 2 2006.173.13:52:05.26#ibcon#about to write, iclass 4, count 2 2006.173.13:52:05.26#ibcon#wrote, iclass 4, count 2 2006.173.13:52:05.26#ibcon#about to read 3, iclass 4, count 2 2006.173.13:52:05.29#ibcon#read 3, iclass 4, count 2 2006.173.13:52:05.29#ibcon#about to read 4, iclass 4, count 2 2006.173.13:52:05.29#ibcon#read 4, iclass 4, count 2 2006.173.13:52:05.29#ibcon#about to read 5, iclass 4, count 2 2006.173.13:52:05.29#ibcon#read 5, iclass 4, count 2 2006.173.13:52:05.29#ibcon#about to read 6, iclass 4, count 2 2006.173.13:52:05.29#ibcon#read 6, iclass 4, count 2 2006.173.13:52:05.29#ibcon#end of sib2, iclass 4, count 2 2006.173.13:52:05.29#ibcon#*after write, iclass 4, count 2 2006.173.13:52:05.29#ibcon#*before return 0, iclass 4, count 2 2006.173.13:52:05.29#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.13:52:05.29#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.13:52:05.29#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.13:52:05.29#ibcon#ireg 7 cls_cnt 0 2006.173.13:52:05.29#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.13:52:05.41#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.13:52:05.41#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.13:52:05.41#ibcon#enter wrdev, iclass 4, count 0 2006.173.13:52:05.41#ibcon#first serial, iclass 4, count 0 2006.173.13:52:05.41#ibcon#enter sib2, iclass 4, count 0 2006.173.13:52:05.41#ibcon#flushed, iclass 4, count 0 2006.173.13:52:05.41#ibcon#about to write, iclass 4, count 0 2006.173.13:52:05.41#ibcon#wrote, iclass 4, count 0 2006.173.13:52:05.41#ibcon#about to read 3, iclass 4, count 0 2006.173.13:52:05.43#ibcon#read 3, iclass 4, count 0 2006.173.13:52:05.43#ibcon#about to read 4, iclass 4, count 0 2006.173.13:52:05.43#ibcon#read 4, iclass 4, count 0 2006.173.13:52:05.43#ibcon#about to read 5, iclass 4, count 0 2006.173.13:52:05.43#ibcon#read 5, iclass 4, count 0 2006.173.13:52:05.43#ibcon#about to read 6, iclass 4, count 0 2006.173.13:52:05.43#ibcon#read 6, iclass 4, count 0 2006.173.13:52:05.43#ibcon#end of sib2, iclass 4, count 0 2006.173.13:52:05.43#ibcon#*mode == 0, iclass 4, count 0 2006.173.13:52:05.43#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.13:52:05.43#ibcon#[25=USB\r\n] 2006.173.13:52:05.43#ibcon#*before write, iclass 4, count 0 2006.173.13:52:05.43#ibcon#enter sib2, iclass 4, count 0 2006.173.13:52:05.43#ibcon#flushed, iclass 4, count 0 2006.173.13:52:05.43#ibcon#about to write, iclass 4, count 0 2006.173.13:52:05.43#ibcon#wrote, iclass 4, count 0 2006.173.13:52:05.43#ibcon#about to read 3, iclass 4, count 0 2006.173.13:52:05.46#ibcon#read 3, iclass 4, count 0 2006.173.13:52:05.46#ibcon#about to read 4, iclass 4, count 0 2006.173.13:52:05.46#ibcon#read 4, iclass 4, count 0 2006.173.13:52:05.46#ibcon#about to read 5, iclass 4, count 0 2006.173.13:52:05.46#ibcon#read 5, iclass 4, count 0 2006.173.13:52:05.46#ibcon#about to read 6, iclass 4, count 0 2006.173.13:52:05.46#ibcon#read 6, iclass 4, count 0 2006.173.13:52:05.46#ibcon#end of sib2, iclass 4, count 0 2006.173.13:52:05.46#ibcon#*after write, iclass 4, count 0 2006.173.13:52:05.46#ibcon#*before return 0, iclass 4, count 0 2006.173.13:52:05.46#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.13:52:05.46#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.13:52:05.46#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.13:52:05.46#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.13:52:05.46$vck44/valo=7,864.99 2006.173.13:52:05.46#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.13:52:05.46#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.13:52:05.46#ibcon#ireg 17 cls_cnt 0 2006.173.13:52:05.46#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.13:52:05.46#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.13:52:05.46#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.13:52:05.46#ibcon#enter wrdev, iclass 6, count 0 2006.173.13:52:05.46#ibcon#first serial, iclass 6, count 0 2006.173.13:52:05.46#ibcon#enter sib2, iclass 6, count 0 2006.173.13:52:05.46#ibcon#flushed, iclass 6, count 0 2006.173.13:52:05.46#ibcon#about to write, iclass 6, count 0 2006.173.13:52:05.46#ibcon#wrote, iclass 6, count 0 2006.173.13:52:05.46#ibcon#about to read 3, iclass 6, count 0 2006.173.13:52:05.48#ibcon#read 3, iclass 6, count 0 2006.173.13:52:05.48#ibcon#about to read 4, iclass 6, count 0 2006.173.13:52:05.48#ibcon#read 4, iclass 6, count 0 2006.173.13:52:05.48#ibcon#about to read 5, iclass 6, count 0 2006.173.13:52:05.48#ibcon#read 5, iclass 6, count 0 2006.173.13:52:05.48#ibcon#about to read 6, iclass 6, count 0 2006.173.13:52:05.48#ibcon#read 6, iclass 6, count 0 2006.173.13:52:05.48#ibcon#end of sib2, iclass 6, count 0 2006.173.13:52:05.48#ibcon#*mode == 0, iclass 6, count 0 2006.173.13:52:05.48#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.13:52:05.48#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.13:52:05.48#ibcon#*before write, iclass 6, count 0 2006.173.13:52:05.48#ibcon#enter sib2, iclass 6, count 0 2006.173.13:52:05.48#ibcon#flushed, iclass 6, count 0 2006.173.13:52:05.48#ibcon#about to write, iclass 6, count 0 2006.173.13:52:05.48#ibcon#wrote, iclass 6, count 0 2006.173.13:52:05.48#ibcon#about to read 3, iclass 6, count 0 2006.173.13:52:05.52#ibcon#read 3, iclass 6, count 0 2006.173.13:52:05.52#ibcon#about to read 4, iclass 6, count 0 2006.173.13:52:05.52#ibcon#read 4, iclass 6, count 0 2006.173.13:52:05.52#ibcon#about to read 5, iclass 6, count 0 2006.173.13:52:05.52#ibcon#read 5, iclass 6, count 0 2006.173.13:52:05.52#ibcon#about to read 6, iclass 6, count 0 2006.173.13:52:05.52#ibcon#read 6, iclass 6, count 0 2006.173.13:52:05.52#ibcon#end of sib2, iclass 6, count 0 2006.173.13:52:05.52#ibcon#*after write, iclass 6, count 0 2006.173.13:52:05.52#ibcon#*before return 0, iclass 6, count 0 2006.173.13:52:05.52#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.13:52:05.52#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.13:52:05.52#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.13:52:05.52#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.13:52:05.52$vck44/va=7,4 2006.173.13:52:05.52#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.13:52:05.52#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.13:52:05.52#ibcon#ireg 11 cls_cnt 2 2006.173.13:52:05.52#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.13:52:05.58#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.13:52:05.58#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.13:52:05.58#ibcon#enter wrdev, iclass 10, count 2 2006.173.13:52:05.58#ibcon#first serial, iclass 10, count 2 2006.173.13:52:05.58#ibcon#enter sib2, iclass 10, count 2 2006.173.13:52:05.58#ibcon#flushed, iclass 10, count 2 2006.173.13:52:05.58#ibcon#about to write, iclass 10, count 2 2006.173.13:52:05.58#ibcon#wrote, iclass 10, count 2 2006.173.13:52:05.58#ibcon#about to read 3, iclass 10, count 2 2006.173.13:52:05.60#ibcon#read 3, iclass 10, count 2 2006.173.13:52:05.60#ibcon#about to read 4, iclass 10, count 2 2006.173.13:52:05.60#ibcon#read 4, iclass 10, count 2 2006.173.13:52:05.60#ibcon#about to read 5, iclass 10, count 2 2006.173.13:52:05.60#ibcon#read 5, iclass 10, count 2 2006.173.13:52:05.60#ibcon#about to read 6, iclass 10, count 2 2006.173.13:52:05.60#ibcon#read 6, iclass 10, count 2 2006.173.13:52:05.60#ibcon#end of sib2, iclass 10, count 2 2006.173.13:52:05.60#ibcon#*mode == 0, iclass 10, count 2 2006.173.13:52:05.60#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.13:52:05.60#ibcon#[25=AT07-04\r\n] 2006.173.13:52:05.60#ibcon#*before write, iclass 10, count 2 2006.173.13:52:05.60#ibcon#enter sib2, iclass 10, count 2 2006.173.13:52:05.60#ibcon#flushed, iclass 10, count 2 2006.173.13:52:05.60#ibcon#about to write, iclass 10, count 2 2006.173.13:52:05.60#ibcon#wrote, iclass 10, count 2 2006.173.13:52:05.60#ibcon#about to read 3, iclass 10, count 2 2006.173.13:52:05.63#ibcon#read 3, iclass 10, count 2 2006.173.13:52:05.63#ibcon#about to read 4, iclass 10, count 2 2006.173.13:52:05.63#ibcon#read 4, iclass 10, count 2 2006.173.13:52:05.63#ibcon#about to read 5, iclass 10, count 2 2006.173.13:52:05.63#ibcon#read 5, iclass 10, count 2 2006.173.13:52:05.63#ibcon#about to read 6, iclass 10, count 2 2006.173.13:52:05.63#ibcon#read 6, iclass 10, count 2 2006.173.13:52:05.63#ibcon#end of sib2, iclass 10, count 2 2006.173.13:52:05.63#ibcon#*after write, iclass 10, count 2 2006.173.13:52:05.63#ibcon#*before return 0, iclass 10, count 2 2006.173.13:52:05.63#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.13:52:05.63#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.13:52:05.63#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.13:52:05.63#ibcon#ireg 7 cls_cnt 0 2006.173.13:52:05.63#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.13:52:05.75#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.13:52:05.75#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.13:52:05.75#ibcon#enter wrdev, iclass 10, count 0 2006.173.13:52:05.75#ibcon#first serial, iclass 10, count 0 2006.173.13:52:05.75#ibcon#enter sib2, iclass 10, count 0 2006.173.13:52:05.75#ibcon#flushed, iclass 10, count 0 2006.173.13:52:05.75#ibcon#about to write, iclass 10, count 0 2006.173.13:52:05.75#ibcon#wrote, iclass 10, count 0 2006.173.13:52:05.75#ibcon#about to read 3, iclass 10, count 0 2006.173.13:52:05.77#ibcon#read 3, iclass 10, count 0 2006.173.13:52:05.77#ibcon#about to read 4, iclass 10, count 0 2006.173.13:52:05.77#ibcon#read 4, iclass 10, count 0 2006.173.13:52:05.77#ibcon#about to read 5, iclass 10, count 0 2006.173.13:52:05.77#ibcon#read 5, iclass 10, count 0 2006.173.13:52:05.77#ibcon#about to read 6, iclass 10, count 0 2006.173.13:52:05.77#ibcon#read 6, iclass 10, count 0 2006.173.13:52:05.77#ibcon#end of sib2, iclass 10, count 0 2006.173.13:52:05.77#ibcon#*mode == 0, iclass 10, count 0 2006.173.13:52:05.77#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.13:52:05.77#ibcon#[25=USB\r\n] 2006.173.13:52:05.77#ibcon#*before write, iclass 10, count 0 2006.173.13:52:05.77#ibcon#enter sib2, iclass 10, count 0 2006.173.13:52:05.77#ibcon#flushed, iclass 10, count 0 2006.173.13:52:05.77#ibcon#about to write, iclass 10, count 0 2006.173.13:52:05.77#ibcon#wrote, iclass 10, count 0 2006.173.13:52:05.77#ibcon#about to read 3, iclass 10, count 0 2006.173.13:52:05.80#ibcon#read 3, iclass 10, count 0 2006.173.13:52:05.80#ibcon#about to read 4, iclass 10, count 0 2006.173.13:52:05.80#ibcon#read 4, iclass 10, count 0 2006.173.13:52:05.80#ibcon#about to read 5, iclass 10, count 0 2006.173.13:52:05.80#ibcon#read 5, iclass 10, count 0 2006.173.13:52:05.80#ibcon#about to read 6, iclass 10, count 0 2006.173.13:52:05.80#ibcon#read 6, iclass 10, count 0 2006.173.13:52:05.80#ibcon#end of sib2, iclass 10, count 0 2006.173.13:52:05.80#ibcon#*after write, iclass 10, count 0 2006.173.13:52:05.80#ibcon#*before return 0, iclass 10, count 0 2006.173.13:52:05.80#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.13:52:05.80#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.13:52:05.80#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.13:52:05.80#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.13:52:05.80$vck44/valo=8,884.99 2006.173.13:52:05.80#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.13:52:05.80#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.13:52:05.80#ibcon#ireg 17 cls_cnt 0 2006.173.13:52:05.80#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.13:52:05.80#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.13:52:05.80#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.13:52:05.80#ibcon#enter wrdev, iclass 12, count 0 2006.173.13:52:05.80#ibcon#first serial, iclass 12, count 0 2006.173.13:52:05.80#ibcon#enter sib2, iclass 12, count 0 2006.173.13:52:05.80#ibcon#flushed, iclass 12, count 0 2006.173.13:52:05.80#ibcon#about to write, iclass 12, count 0 2006.173.13:52:05.80#ibcon#wrote, iclass 12, count 0 2006.173.13:52:05.80#ibcon#about to read 3, iclass 12, count 0 2006.173.13:52:05.82#ibcon#read 3, iclass 12, count 0 2006.173.13:52:05.82#ibcon#about to read 4, iclass 12, count 0 2006.173.13:52:05.82#ibcon#read 4, iclass 12, count 0 2006.173.13:52:05.82#ibcon#about to read 5, iclass 12, count 0 2006.173.13:52:05.82#ibcon#read 5, iclass 12, count 0 2006.173.13:52:05.82#ibcon#about to read 6, iclass 12, count 0 2006.173.13:52:05.82#ibcon#read 6, iclass 12, count 0 2006.173.13:52:05.82#ibcon#end of sib2, iclass 12, count 0 2006.173.13:52:05.82#ibcon#*mode == 0, iclass 12, count 0 2006.173.13:52:05.82#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.13:52:05.82#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.13:52:05.82#ibcon#*before write, iclass 12, count 0 2006.173.13:52:05.82#ibcon#enter sib2, iclass 12, count 0 2006.173.13:52:05.82#ibcon#flushed, iclass 12, count 0 2006.173.13:52:05.82#ibcon#about to write, iclass 12, count 0 2006.173.13:52:05.82#ibcon#wrote, iclass 12, count 0 2006.173.13:52:05.82#ibcon#about to read 3, iclass 12, count 0 2006.173.13:52:05.86#ibcon#read 3, iclass 12, count 0 2006.173.13:52:05.86#ibcon#about to read 4, iclass 12, count 0 2006.173.13:52:05.86#ibcon#read 4, iclass 12, count 0 2006.173.13:52:05.86#ibcon#about to read 5, iclass 12, count 0 2006.173.13:52:05.86#ibcon#read 5, iclass 12, count 0 2006.173.13:52:05.86#ibcon#about to read 6, iclass 12, count 0 2006.173.13:52:05.86#ibcon#read 6, iclass 12, count 0 2006.173.13:52:05.86#ibcon#end of sib2, iclass 12, count 0 2006.173.13:52:05.86#ibcon#*after write, iclass 12, count 0 2006.173.13:52:05.86#ibcon#*before return 0, iclass 12, count 0 2006.173.13:52:05.86#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.13:52:05.86#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.13:52:05.86#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.13:52:05.86#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.13:52:05.86$vck44/va=8,4 2006.173.13:52:05.86#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.13:52:05.86#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.13:52:05.86#ibcon#ireg 11 cls_cnt 2 2006.173.13:52:05.86#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.13:52:05.92#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.13:52:05.92#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.13:52:05.92#ibcon#enter wrdev, iclass 14, count 2 2006.173.13:52:05.92#ibcon#first serial, iclass 14, count 2 2006.173.13:52:05.92#ibcon#enter sib2, iclass 14, count 2 2006.173.13:52:05.92#ibcon#flushed, iclass 14, count 2 2006.173.13:52:05.92#ibcon#about to write, iclass 14, count 2 2006.173.13:52:05.92#ibcon#wrote, iclass 14, count 2 2006.173.13:52:05.92#ibcon#about to read 3, iclass 14, count 2 2006.173.13:52:05.94#ibcon#read 3, iclass 14, count 2 2006.173.13:52:05.94#ibcon#about to read 4, iclass 14, count 2 2006.173.13:52:05.94#ibcon#read 4, iclass 14, count 2 2006.173.13:52:05.94#ibcon#about to read 5, iclass 14, count 2 2006.173.13:52:05.94#ibcon#read 5, iclass 14, count 2 2006.173.13:52:05.94#ibcon#about to read 6, iclass 14, count 2 2006.173.13:52:05.94#ibcon#read 6, iclass 14, count 2 2006.173.13:52:05.94#ibcon#end of sib2, iclass 14, count 2 2006.173.13:52:05.94#ibcon#*mode == 0, iclass 14, count 2 2006.173.13:52:05.94#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.13:52:05.94#ibcon#[25=AT08-04\r\n] 2006.173.13:52:05.94#ibcon#*before write, iclass 14, count 2 2006.173.13:52:05.94#ibcon#enter sib2, iclass 14, count 2 2006.173.13:52:05.94#ibcon#flushed, iclass 14, count 2 2006.173.13:52:05.94#ibcon#about to write, iclass 14, count 2 2006.173.13:52:05.94#ibcon#wrote, iclass 14, count 2 2006.173.13:52:05.94#ibcon#about to read 3, iclass 14, count 2 2006.173.13:52:05.97#ibcon#read 3, iclass 14, count 2 2006.173.13:52:05.97#ibcon#about to read 4, iclass 14, count 2 2006.173.13:52:05.97#ibcon#read 4, iclass 14, count 2 2006.173.13:52:05.97#ibcon#about to read 5, iclass 14, count 2 2006.173.13:52:05.97#ibcon#read 5, iclass 14, count 2 2006.173.13:52:05.97#ibcon#about to read 6, iclass 14, count 2 2006.173.13:52:05.97#ibcon#read 6, iclass 14, count 2 2006.173.13:52:05.97#ibcon#end of sib2, iclass 14, count 2 2006.173.13:52:05.97#ibcon#*after write, iclass 14, count 2 2006.173.13:52:05.97#ibcon#*before return 0, iclass 14, count 2 2006.173.13:52:05.97#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.13:52:05.97#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.13:52:05.97#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.13:52:05.97#ibcon#ireg 7 cls_cnt 0 2006.173.13:52:05.97#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.13:52:06.09#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.13:52:06.09#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.13:52:06.09#ibcon#enter wrdev, iclass 14, count 0 2006.173.13:52:06.09#ibcon#first serial, iclass 14, count 0 2006.173.13:52:06.09#ibcon#enter sib2, iclass 14, count 0 2006.173.13:52:06.09#ibcon#flushed, iclass 14, count 0 2006.173.13:52:06.09#ibcon#about to write, iclass 14, count 0 2006.173.13:52:06.09#ibcon#wrote, iclass 14, count 0 2006.173.13:52:06.09#ibcon#about to read 3, iclass 14, count 0 2006.173.13:52:06.11#ibcon#read 3, iclass 14, count 0 2006.173.13:52:06.11#ibcon#about to read 4, iclass 14, count 0 2006.173.13:52:06.11#ibcon#read 4, iclass 14, count 0 2006.173.13:52:06.11#ibcon#about to read 5, iclass 14, count 0 2006.173.13:52:06.11#ibcon#read 5, iclass 14, count 0 2006.173.13:52:06.11#ibcon#about to read 6, iclass 14, count 0 2006.173.13:52:06.11#ibcon#read 6, iclass 14, count 0 2006.173.13:52:06.11#ibcon#end of sib2, iclass 14, count 0 2006.173.13:52:06.11#ibcon#*mode == 0, iclass 14, count 0 2006.173.13:52:06.11#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.13:52:06.11#ibcon#[25=USB\r\n] 2006.173.13:52:06.11#ibcon#*before write, iclass 14, count 0 2006.173.13:52:06.11#ibcon#enter sib2, iclass 14, count 0 2006.173.13:52:06.11#ibcon#flushed, iclass 14, count 0 2006.173.13:52:06.11#ibcon#about to write, iclass 14, count 0 2006.173.13:52:06.11#ibcon#wrote, iclass 14, count 0 2006.173.13:52:06.11#ibcon#about to read 3, iclass 14, count 0 2006.173.13:52:06.14#ibcon#read 3, iclass 14, count 0 2006.173.13:52:06.14#ibcon#about to read 4, iclass 14, count 0 2006.173.13:52:06.14#ibcon#read 4, iclass 14, count 0 2006.173.13:52:06.14#ibcon#about to read 5, iclass 14, count 0 2006.173.13:52:06.14#ibcon#read 5, iclass 14, count 0 2006.173.13:52:06.14#ibcon#about to read 6, iclass 14, count 0 2006.173.13:52:06.14#ibcon#read 6, iclass 14, count 0 2006.173.13:52:06.14#ibcon#end of sib2, iclass 14, count 0 2006.173.13:52:06.14#ibcon#*after write, iclass 14, count 0 2006.173.13:52:06.14#ibcon#*before return 0, iclass 14, count 0 2006.173.13:52:06.14#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.13:52:06.14#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.13:52:06.14#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.13:52:06.14#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.13:52:06.14$vck44/vblo=1,629.99 2006.173.13:52:06.14#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.13:52:06.14#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.13:52:06.14#ibcon#ireg 17 cls_cnt 0 2006.173.13:52:06.14#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.13:52:06.14#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.13:52:06.14#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.13:52:06.14#ibcon#enter wrdev, iclass 16, count 0 2006.173.13:52:06.14#ibcon#first serial, iclass 16, count 0 2006.173.13:52:06.14#ibcon#enter sib2, iclass 16, count 0 2006.173.13:52:06.14#ibcon#flushed, iclass 16, count 0 2006.173.13:52:06.14#ibcon#about to write, iclass 16, count 0 2006.173.13:52:06.14#ibcon#wrote, iclass 16, count 0 2006.173.13:52:06.14#ibcon#about to read 3, iclass 16, count 0 2006.173.13:52:06.16#ibcon#read 3, iclass 16, count 0 2006.173.13:52:06.16#ibcon#about to read 4, iclass 16, count 0 2006.173.13:52:06.16#ibcon#read 4, iclass 16, count 0 2006.173.13:52:06.16#ibcon#about to read 5, iclass 16, count 0 2006.173.13:52:06.16#ibcon#read 5, iclass 16, count 0 2006.173.13:52:06.16#ibcon#about to read 6, iclass 16, count 0 2006.173.13:52:06.16#ibcon#read 6, iclass 16, count 0 2006.173.13:52:06.16#ibcon#end of sib2, iclass 16, count 0 2006.173.13:52:06.16#ibcon#*mode == 0, iclass 16, count 0 2006.173.13:52:06.16#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.13:52:06.16#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.13:52:06.16#ibcon#*before write, iclass 16, count 0 2006.173.13:52:06.16#ibcon#enter sib2, iclass 16, count 0 2006.173.13:52:06.16#ibcon#flushed, iclass 16, count 0 2006.173.13:52:06.16#ibcon#about to write, iclass 16, count 0 2006.173.13:52:06.16#ibcon#wrote, iclass 16, count 0 2006.173.13:52:06.16#ibcon#about to read 3, iclass 16, count 0 2006.173.13:52:06.20#ibcon#read 3, iclass 16, count 0 2006.173.13:52:06.20#ibcon#about to read 4, iclass 16, count 0 2006.173.13:52:06.20#ibcon#read 4, iclass 16, count 0 2006.173.13:52:06.20#ibcon#about to read 5, iclass 16, count 0 2006.173.13:52:06.20#ibcon#read 5, iclass 16, count 0 2006.173.13:52:06.20#ibcon#about to read 6, iclass 16, count 0 2006.173.13:52:06.20#ibcon#read 6, iclass 16, count 0 2006.173.13:52:06.20#ibcon#end of sib2, iclass 16, count 0 2006.173.13:52:06.20#ibcon#*after write, iclass 16, count 0 2006.173.13:52:06.20#ibcon#*before return 0, iclass 16, count 0 2006.173.13:52:06.20#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.13:52:06.20#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.13:52:06.20#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.13:52:06.20#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.13:52:06.20$vck44/vb=1,4 2006.173.13:52:06.20#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.13:52:06.20#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.13:52:06.20#ibcon#ireg 11 cls_cnt 2 2006.173.13:52:06.20#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.13:52:06.20#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.13:52:06.20#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.13:52:06.20#ibcon#enter wrdev, iclass 18, count 2 2006.173.13:52:06.20#ibcon#first serial, iclass 18, count 2 2006.173.13:52:06.20#ibcon#enter sib2, iclass 18, count 2 2006.173.13:52:06.20#ibcon#flushed, iclass 18, count 2 2006.173.13:52:06.20#ibcon#about to write, iclass 18, count 2 2006.173.13:52:06.20#ibcon#wrote, iclass 18, count 2 2006.173.13:52:06.20#ibcon#about to read 3, iclass 18, count 2 2006.173.13:52:06.22#ibcon#read 3, iclass 18, count 2 2006.173.13:52:06.22#ibcon#about to read 4, iclass 18, count 2 2006.173.13:52:06.22#ibcon#read 4, iclass 18, count 2 2006.173.13:52:06.22#ibcon#about to read 5, iclass 18, count 2 2006.173.13:52:06.22#ibcon#read 5, iclass 18, count 2 2006.173.13:52:06.22#ibcon#about to read 6, iclass 18, count 2 2006.173.13:52:06.22#ibcon#read 6, iclass 18, count 2 2006.173.13:52:06.22#ibcon#end of sib2, iclass 18, count 2 2006.173.13:52:06.22#ibcon#*mode == 0, iclass 18, count 2 2006.173.13:52:06.22#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.13:52:06.22#ibcon#[27=AT01-04\r\n] 2006.173.13:52:06.22#ibcon#*before write, iclass 18, count 2 2006.173.13:52:06.22#ibcon#enter sib2, iclass 18, count 2 2006.173.13:52:06.22#ibcon#flushed, iclass 18, count 2 2006.173.13:52:06.22#ibcon#about to write, iclass 18, count 2 2006.173.13:52:06.22#ibcon#wrote, iclass 18, count 2 2006.173.13:52:06.22#ibcon#about to read 3, iclass 18, count 2 2006.173.13:52:06.25#ibcon#read 3, iclass 18, count 2 2006.173.13:52:06.25#ibcon#about to read 4, iclass 18, count 2 2006.173.13:52:06.25#ibcon#read 4, iclass 18, count 2 2006.173.13:52:06.25#ibcon#about to read 5, iclass 18, count 2 2006.173.13:52:06.25#ibcon#read 5, iclass 18, count 2 2006.173.13:52:06.25#ibcon#about to read 6, iclass 18, count 2 2006.173.13:52:06.25#ibcon#read 6, iclass 18, count 2 2006.173.13:52:06.25#ibcon#end of sib2, iclass 18, count 2 2006.173.13:52:06.25#ibcon#*after write, iclass 18, count 2 2006.173.13:52:06.25#ibcon#*before return 0, iclass 18, count 2 2006.173.13:52:06.25#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.13:52:06.25#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.13:52:06.25#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.13:52:06.25#ibcon#ireg 7 cls_cnt 0 2006.173.13:52:06.25#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.13:52:06.37#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.13:52:06.37#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.13:52:06.37#ibcon#enter wrdev, iclass 18, count 0 2006.173.13:52:06.37#ibcon#first serial, iclass 18, count 0 2006.173.13:52:06.37#ibcon#enter sib2, iclass 18, count 0 2006.173.13:52:06.37#ibcon#flushed, iclass 18, count 0 2006.173.13:52:06.37#ibcon#about to write, iclass 18, count 0 2006.173.13:52:06.37#ibcon#wrote, iclass 18, count 0 2006.173.13:52:06.37#ibcon#about to read 3, iclass 18, count 0 2006.173.13:52:06.39#ibcon#read 3, iclass 18, count 0 2006.173.13:52:06.39#ibcon#about to read 4, iclass 18, count 0 2006.173.13:52:06.39#ibcon#read 4, iclass 18, count 0 2006.173.13:52:06.39#ibcon#about to read 5, iclass 18, count 0 2006.173.13:52:06.39#ibcon#read 5, iclass 18, count 0 2006.173.13:52:06.39#ibcon#about to read 6, iclass 18, count 0 2006.173.13:52:06.39#ibcon#read 6, iclass 18, count 0 2006.173.13:52:06.39#ibcon#end of sib2, iclass 18, count 0 2006.173.13:52:06.39#ibcon#*mode == 0, iclass 18, count 0 2006.173.13:52:06.39#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.13:52:06.39#ibcon#[27=USB\r\n] 2006.173.13:52:06.39#ibcon#*before write, iclass 18, count 0 2006.173.13:52:06.39#ibcon#enter sib2, iclass 18, count 0 2006.173.13:52:06.39#ibcon#flushed, iclass 18, count 0 2006.173.13:52:06.39#ibcon#about to write, iclass 18, count 0 2006.173.13:52:06.39#ibcon#wrote, iclass 18, count 0 2006.173.13:52:06.39#ibcon#about to read 3, iclass 18, count 0 2006.173.13:52:06.42#ibcon#read 3, iclass 18, count 0 2006.173.13:52:06.42#ibcon#about to read 4, iclass 18, count 0 2006.173.13:52:06.42#ibcon#read 4, iclass 18, count 0 2006.173.13:52:06.42#ibcon#about to read 5, iclass 18, count 0 2006.173.13:52:06.42#ibcon#read 5, iclass 18, count 0 2006.173.13:52:06.42#ibcon#about to read 6, iclass 18, count 0 2006.173.13:52:06.42#ibcon#read 6, iclass 18, count 0 2006.173.13:52:06.42#ibcon#end of sib2, iclass 18, count 0 2006.173.13:52:06.42#ibcon#*after write, iclass 18, count 0 2006.173.13:52:06.42#ibcon#*before return 0, iclass 18, count 0 2006.173.13:52:06.42#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.13:52:06.42#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.13:52:06.42#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.13:52:06.42#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.13:52:06.42$vck44/vblo=2,634.99 2006.173.13:52:06.42#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.13:52:06.42#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.13:52:06.42#ibcon#ireg 17 cls_cnt 0 2006.173.13:52:06.42#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.13:52:06.42#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.13:52:06.42#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.13:52:06.42#ibcon#enter wrdev, iclass 20, count 0 2006.173.13:52:06.42#ibcon#first serial, iclass 20, count 0 2006.173.13:52:06.42#ibcon#enter sib2, iclass 20, count 0 2006.173.13:52:06.42#ibcon#flushed, iclass 20, count 0 2006.173.13:52:06.42#ibcon#about to write, iclass 20, count 0 2006.173.13:52:06.42#ibcon#wrote, iclass 20, count 0 2006.173.13:52:06.42#ibcon#about to read 3, iclass 20, count 0 2006.173.13:52:06.44#ibcon#read 3, iclass 20, count 0 2006.173.13:52:06.44#ibcon#about to read 4, iclass 20, count 0 2006.173.13:52:06.44#ibcon#read 4, iclass 20, count 0 2006.173.13:52:06.44#ibcon#about to read 5, iclass 20, count 0 2006.173.13:52:06.44#ibcon#read 5, iclass 20, count 0 2006.173.13:52:06.44#ibcon#about to read 6, iclass 20, count 0 2006.173.13:52:06.44#ibcon#read 6, iclass 20, count 0 2006.173.13:52:06.44#ibcon#end of sib2, iclass 20, count 0 2006.173.13:52:06.44#ibcon#*mode == 0, iclass 20, count 0 2006.173.13:52:06.44#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.13:52:06.44#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.13:52:06.44#ibcon#*before write, iclass 20, count 0 2006.173.13:52:06.44#ibcon#enter sib2, iclass 20, count 0 2006.173.13:52:06.44#ibcon#flushed, iclass 20, count 0 2006.173.13:52:06.44#ibcon#about to write, iclass 20, count 0 2006.173.13:52:06.44#ibcon#wrote, iclass 20, count 0 2006.173.13:52:06.44#ibcon#about to read 3, iclass 20, count 0 2006.173.13:52:06.48#ibcon#read 3, iclass 20, count 0 2006.173.13:52:06.48#ibcon#about to read 4, iclass 20, count 0 2006.173.13:52:06.48#ibcon#read 4, iclass 20, count 0 2006.173.13:52:06.48#ibcon#about to read 5, iclass 20, count 0 2006.173.13:52:06.48#ibcon#read 5, iclass 20, count 0 2006.173.13:52:06.48#ibcon#about to read 6, iclass 20, count 0 2006.173.13:52:06.48#ibcon#read 6, iclass 20, count 0 2006.173.13:52:06.48#ibcon#end of sib2, iclass 20, count 0 2006.173.13:52:06.48#ibcon#*after write, iclass 20, count 0 2006.173.13:52:06.48#ibcon#*before return 0, iclass 20, count 0 2006.173.13:52:06.48#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.13:52:06.48#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.13:52:06.48#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.13:52:06.48#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.13:52:06.48$vck44/vb=2,4 2006.173.13:52:06.48#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.13:52:06.48#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.13:52:06.48#ibcon#ireg 11 cls_cnt 2 2006.173.13:52:06.48#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.13:52:06.54#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.13:52:06.54#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.13:52:06.54#ibcon#enter wrdev, iclass 22, count 2 2006.173.13:52:06.54#ibcon#first serial, iclass 22, count 2 2006.173.13:52:06.54#ibcon#enter sib2, iclass 22, count 2 2006.173.13:52:06.54#ibcon#flushed, iclass 22, count 2 2006.173.13:52:06.54#ibcon#about to write, iclass 22, count 2 2006.173.13:52:06.54#ibcon#wrote, iclass 22, count 2 2006.173.13:52:06.54#ibcon#about to read 3, iclass 22, count 2 2006.173.13:52:06.56#ibcon#read 3, iclass 22, count 2 2006.173.13:52:06.56#ibcon#about to read 4, iclass 22, count 2 2006.173.13:52:06.56#ibcon#read 4, iclass 22, count 2 2006.173.13:52:06.56#ibcon#about to read 5, iclass 22, count 2 2006.173.13:52:06.56#ibcon#read 5, iclass 22, count 2 2006.173.13:52:06.56#ibcon#about to read 6, iclass 22, count 2 2006.173.13:52:06.56#ibcon#read 6, iclass 22, count 2 2006.173.13:52:06.56#ibcon#end of sib2, iclass 22, count 2 2006.173.13:52:06.56#ibcon#*mode == 0, iclass 22, count 2 2006.173.13:52:06.56#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.13:52:06.56#ibcon#[27=AT02-04\r\n] 2006.173.13:52:06.56#ibcon#*before write, iclass 22, count 2 2006.173.13:52:06.56#ibcon#enter sib2, iclass 22, count 2 2006.173.13:52:06.56#ibcon#flushed, iclass 22, count 2 2006.173.13:52:06.56#ibcon#about to write, iclass 22, count 2 2006.173.13:52:06.56#ibcon#wrote, iclass 22, count 2 2006.173.13:52:06.56#ibcon#about to read 3, iclass 22, count 2 2006.173.13:52:06.59#ibcon#read 3, iclass 22, count 2 2006.173.13:52:06.59#ibcon#about to read 4, iclass 22, count 2 2006.173.13:52:06.59#ibcon#read 4, iclass 22, count 2 2006.173.13:52:06.59#ibcon#about to read 5, iclass 22, count 2 2006.173.13:52:06.59#ibcon#read 5, iclass 22, count 2 2006.173.13:52:06.59#ibcon#about to read 6, iclass 22, count 2 2006.173.13:52:06.59#ibcon#read 6, iclass 22, count 2 2006.173.13:52:06.59#ibcon#end of sib2, iclass 22, count 2 2006.173.13:52:06.59#ibcon#*after write, iclass 22, count 2 2006.173.13:52:06.59#ibcon#*before return 0, iclass 22, count 2 2006.173.13:52:06.59#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.13:52:06.59#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.13:52:06.59#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.13:52:06.59#ibcon#ireg 7 cls_cnt 0 2006.173.13:52:06.59#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.13:52:06.71#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.13:52:06.71#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.13:52:06.71#ibcon#enter wrdev, iclass 22, count 0 2006.173.13:52:06.71#ibcon#first serial, iclass 22, count 0 2006.173.13:52:06.71#ibcon#enter sib2, iclass 22, count 0 2006.173.13:52:06.71#ibcon#flushed, iclass 22, count 0 2006.173.13:52:06.71#ibcon#about to write, iclass 22, count 0 2006.173.13:52:06.71#ibcon#wrote, iclass 22, count 0 2006.173.13:52:06.71#ibcon#about to read 3, iclass 22, count 0 2006.173.13:52:06.73#ibcon#read 3, iclass 22, count 0 2006.173.13:52:06.73#ibcon#about to read 4, iclass 22, count 0 2006.173.13:52:06.73#ibcon#read 4, iclass 22, count 0 2006.173.13:52:06.73#ibcon#about to read 5, iclass 22, count 0 2006.173.13:52:06.73#ibcon#read 5, iclass 22, count 0 2006.173.13:52:06.73#ibcon#about to read 6, iclass 22, count 0 2006.173.13:52:06.73#ibcon#read 6, iclass 22, count 0 2006.173.13:52:06.73#ibcon#end of sib2, iclass 22, count 0 2006.173.13:52:06.73#ibcon#*mode == 0, iclass 22, count 0 2006.173.13:52:06.73#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.13:52:06.73#ibcon#[27=USB\r\n] 2006.173.13:52:06.73#ibcon#*before write, iclass 22, count 0 2006.173.13:52:06.73#ibcon#enter sib2, iclass 22, count 0 2006.173.13:52:06.73#ibcon#flushed, iclass 22, count 0 2006.173.13:52:06.73#ibcon#about to write, iclass 22, count 0 2006.173.13:52:06.73#ibcon#wrote, iclass 22, count 0 2006.173.13:52:06.73#ibcon#about to read 3, iclass 22, count 0 2006.173.13:52:06.76#ibcon#read 3, iclass 22, count 0 2006.173.13:52:06.76#ibcon#about to read 4, iclass 22, count 0 2006.173.13:52:06.76#ibcon#read 4, iclass 22, count 0 2006.173.13:52:06.76#ibcon#about to read 5, iclass 22, count 0 2006.173.13:52:06.76#ibcon#read 5, iclass 22, count 0 2006.173.13:52:06.76#ibcon#about to read 6, iclass 22, count 0 2006.173.13:52:06.76#ibcon#read 6, iclass 22, count 0 2006.173.13:52:06.76#ibcon#end of sib2, iclass 22, count 0 2006.173.13:52:06.76#ibcon#*after write, iclass 22, count 0 2006.173.13:52:06.76#ibcon#*before return 0, iclass 22, count 0 2006.173.13:52:06.76#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.13:52:06.76#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.13:52:06.76#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.13:52:06.76#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.13:52:06.76$vck44/vblo=3,649.99 2006.173.13:52:06.76#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.13:52:06.76#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.13:52:06.76#ibcon#ireg 17 cls_cnt 0 2006.173.13:52:06.76#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.13:52:06.76#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.13:52:06.76#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.13:52:06.76#ibcon#enter wrdev, iclass 24, count 0 2006.173.13:52:06.76#ibcon#first serial, iclass 24, count 0 2006.173.13:52:06.76#ibcon#enter sib2, iclass 24, count 0 2006.173.13:52:06.76#ibcon#flushed, iclass 24, count 0 2006.173.13:52:06.76#ibcon#about to write, iclass 24, count 0 2006.173.13:52:06.76#ibcon#wrote, iclass 24, count 0 2006.173.13:52:06.76#ibcon#about to read 3, iclass 24, count 0 2006.173.13:52:06.78#ibcon#read 3, iclass 24, count 0 2006.173.13:52:06.78#ibcon#about to read 4, iclass 24, count 0 2006.173.13:52:06.78#ibcon#read 4, iclass 24, count 0 2006.173.13:52:06.78#ibcon#about to read 5, iclass 24, count 0 2006.173.13:52:06.78#ibcon#read 5, iclass 24, count 0 2006.173.13:52:06.78#ibcon#about to read 6, iclass 24, count 0 2006.173.13:52:06.78#ibcon#read 6, iclass 24, count 0 2006.173.13:52:06.78#ibcon#end of sib2, iclass 24, count 0 2006.173.13:52:06.78#ibcon#*mode == 0, iclass 24, count 0 2006.173.13:52:06.78#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.13:52:06.78#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.13:52:06.78#ibcon#*before write, iclass 24, count 0 2006.173.13:52:06.78#ibcon#enter sib2, iclass 24, count 0 2006.173.13:52:06.78#ibcon#flushed, iclass 24, count 0 2006.173.13:52:06.78#ibcon#about to write, iclass 24, count 0 2006.173.13:52:06.78#ibcon#wrote, iclass 24, count 0 2006.173.13:52:06.78#ibcon#about to read 3, iclass 24, count 0 2006.173.13:52:06.82#ibcon#read 3, iclass 24, count 0 2006.173.13:52:06.82#ibcon#about to read 4, iclass 24, count 0 2006.173.13:52:06.82#ibcon#read 4, iclass 24, count 0 2006.173.13:52:06.82#ibcon#about to read 5, iclass 24, count 0 2006.173.13:52:06.82#ibcon#read 5, iclass 24, count 0 2006.173.13:52:06.82#ibcon#about to read 6, iclass 24, count 0 2006.173.13:52:06.82#ibcon#read 6, iclass 24, count 0 2006.173.13:52:06.82#ibcon#end of sib2, iclass 24, count 0 2006.173.13:52:06.82#ibcon#*after write, iclass 24, count 0 2006.173.13:52:06.82#ibcon#*before return 0, iclass 24, count 0 2006.173.13:52:06.82#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.13:52:06.82#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.13:52:06.82#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.13:52:06.82#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.13:52:06.82$vck44/vb=3,4 2006.173.13:52:06.82#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.13:52:06.82#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.13:52:06.82#ibcon#ireg 11 cls_cnt 2 2006.173.13:52:06.82#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.13:52:06.88#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.13:52:06.88#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.13:52:06.88#ibcon#enter wrdev, iclass 26, count 2 2006.173.13:52:06.88#ibcon#first serial, iclass 26, count 2 2006.173.13:52:06.88#ibcon#enter sib2, iclass 26, count 2 2006.173.13:52:06.88#ibcon#flushed, iclass 26, count 2 2006.173.13:52:06.88#ibcon#about to write, iclass 26, count 2 2006.173.13:52:06.88#ibcon#wrote, iclass 26, count 2 2006.173.13:52:06.88#ibcon#about to read 3, iclass 26, count 2 2006.173.13:52:06.90#ibcon#read 3, iclass 26, count 2 2006.173.13:52:06.90#ibcon#about to read 4, iclass 26, count 2 2006.173.13:52:06.90#ibcon#read 4, iclass 26, count 2 2006.173.13:52:06.90#ibcon#about to read 5, iclass 26, count 2 2006.173.13:52:06.90#ibcon#read 5, iclass 26, count 2 2006.173.13:52:06.90#ibcon#about to read 6, iclass 26, count 2 2006.173.13:52:06.90#ibcon#read 6, iclass 26, count 2 2006.173.13:52:06.90#ibcon#end of sib2, iclass 26, count 2 2006.173.13:52:06.90#ibcon#*mode == 0, iclass 26, count 2 2006.173.13:52:06.90#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.13:52:06.90#ibcon#[27=AT03-04\r\n] 2006.173.13:52:06.90#ibcon#*before write, iclass 26, count 2 2006.173.13:52:06.90#ibcon#enter sib2, iclass 26, count 2 2006.173.13:52:06.90#ibcon#flushed, iclass 26, count 2 2006.173.13:52:06.90#ibcon#about to write, iclass 26, count 2 2006.173.13:52:06.90#ibcon#wrote, iclass 26, count 2 2006.173.13:52:06.90#ibcon#about to read 3, iclass 26, count 2 2006.173.13:52:06.93#ibcon#read 3, iclass 26, count 2 2006.173.13:52:06.93#ibcon#about to read 4, iclass 26, count 2 2006.173.13:52:06.93#ibcon#read 4, iclass 26, count 2 2006.173.13:52:06.93#ibcon#about to read 5, iclass 26, count 2 2006.173.13:52:06.93#ibcon#read 5, iclass 26, count 2 2006.173.13:52:06.93#ibcon#about to read 6, iclass 26, count 2 2006.173.13:52:06.93#ibcon#read 6, iclass 26, count 2 2006.173.13:52:06.93#ibcon#end of sib2, iclass 26, count 2 2006.173.13:52:06.93#ibcon#*after write, iclass 26, count 2 2006.173.13:52:06.93#ibcon#*before return 0, iclass 26, count 2 2006.173.13:52:06.93#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.13:52:06.93#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.13:52:06.93#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.13:52:06.93#ibcon#ireg 7 cls_cnt 0 2006.173.13:52:06.93#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.13:52:07.05#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.13:52:07.05#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.13:52:07.05#ibcon#enter wrdev, iclass 26, count 0 2006.173.13:52:07.05#ibcon#first serial, iclass 26, count 0 2006.173.13:52:07.05#ibcon#enter sib2, iclass 26, count 0 2006.173.13:52:07.05#ibcon#flushed, iclass 26, count 0 2006.173.13:52:07.05#ibcon#about to write, iclass 26, count 0 2006.173.13:52:07.05#ibcon#wrote, iclass 26, count 0 2006.173.13:52:07.05#ibcon#about to read 3, iclass 26, count 0 2006.173.13:52:07.07#ibcon#read 3, iclass 26, count 0 2006.173.13:52:07.07#ibcon#about to read 4, iclass 26, count 0 2006.173.13:52:07.07#ibcon#read 4, iclass 26, count 0 2006.173.13:52:07.07#ibcon#about to read 5, iclass 26, count 0 2006.173.13:52:07.07#ibcon#read 5, iclass 26, count 0 2006.173.13:52:07.07#ibcon#about to read 6, iclass 26, count 0 2006.173.13:52:07.07#ibcon#read 6, iclass 26, count 0 2006.173.13:52:07.07#ibcon#end of sib2, iclass 26, count 0 2006.173.13:52:07.07#ibcon#*mode == 0, iclass 26, count 0 2006.173.13:52:07.07#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.13:52:07.07#ibcon#[27=USB\r\n] 2006.173.13:52:07.07#ibcon#*before write, iclass 26, count 0 2006.173.13:52:07.07#ibcon#enter sib2, iclass 26, count 0 2006.173.13:52:07.07#ibcon#flushed, iclass 26, count 0 2006.173.13:52:07.07#ibcon#about to write, iclass 26, count 0 2006.173.13:52:07.07#ibcon#wrote, iclass 26, count 0 2006.173.13:52:07.07#ibcon#about to read 3, iclass 26, count 0 2006.173.13:52:07.10#ibcon#read 3, iclass 26, count 0 2006.173.13:52:07.10#ibcon#about to read 4, iclass 26, count 0 2006.173.13:52:07.10#ibcon#read 4, iclass 26, count 0 2006.173.13:52:07.10#ibcon#about to read 5, iclass 26, count 0 2006.173.13:52:07.10#ibcon#read 5, iclass 26, count 0 2006.173.13:52:07.10#ibcon#about to read 6, iclass 26, count 0 2006.173.13:52:07.10#ibcon#read 6, iclass 26, count 0 2006.173.13:52:07.10#ibcon#end of sib2, iclass 26, count 0 2006.173.13:52:07.10#ibcon#*after write, iclass 26, count 0 2006.173.13:52:07.10#ibcon#*before return 0, iclass 26, count 0 2006.173.13:52:07.10#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.13:52:07.10#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.13:52:07.10#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.13:52:07.10#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.13:52:07.10$vck44/vblo=4,679.99 2006.173.13:52:07.10#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.13:52:07.10#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.13:52:07.10#ibcon#ireg 17 cls_cnt 0 2006.173.13:52:07.10#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.13:52:07.10#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.13:52:07.10#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.13:52:07.10#ibcon#enter wrdev, iclass 28, count 0 2006.173.13:52:07.10#ibcon#first serial, iclass 28, count 0 2006.173.13:52:07.10#ibcon#enter sib2, iclass 28, count 0 2006.173.13:52:07.10#ibcon#flushed, iclass 28, count 0 2006.173.13:52:07.10#ibcon#about to write, iclass 28, count 0 2006.173.13:52:07.10#ibcon#wrote, iclass 28, count 0 2006.173.13:52:07.10#ibcon#about to read 3, iclass 28, count 0 2006.173.13:52:07.12#ibcon#read 3, iclass 28, count 0 2006.173.13:52:07.12#ibcon#about to read 4, iclass 28, count 0 2006.173.13:52:07.12#ibcon#read 4, iclass 28, count 0 2006.173.13:52:07.12#ibcon#about to read 5, iclass 28, count 0 2006.173.13:52:07.12#ibcon#read 5, iclass 28, count 0 2006.173.13:52:07.12#ibcon#about to read 6, iclass 28, count 0 2006.173.13:52:07.12#ibcon#read 6, iclass 28, count 0 2006.173.13:52:07.12#ibcon#end of sib2, iclass 28, count 0 2006.173.13:52:07.12#ibcon#*mode == 0, iclass 28, count 0 2006.173.13:52:07.12#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.13:52:07.12#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.13:52:07.12#ibcon#*before write, iclass 28, count 0 2006.173.13:52:07.12#ibcon#enter sib2, iclass 28, count 0 2006.173.13:52:07.12#ibcon#flushed, iclass 28, count 0 2006.173.13:52:07.12#ibcon#about to write, iclass 28, count 0 2006.173.13:52:07.12#ibcon#wrote, iclass 28, count 0 2006.173.13:52:07.12#ibcon#about to read 3, iclass 28, count 0 2006.173.13:52:07.16#ibcon#read 3, iclass 28, count 0 2006.173.13:52:07.16#ibcon#about to read 4, iclass 28, count 0 2006.173.13:52:07.16#ibcon#read 4, iclass 28, count 0 2006.173.13:52:07.16#ibcon#about to read 5, iclass 28, count 0 2006.173.13:52:07.16#ibcon#read 5, iclass 28, count 0 2006.173.13:52:07.16#ibcon#about to read 6, iclass 28, count 0 2006.173.13:52:07.16#ibcon#read 6, iclass 28, count 0 2006.173.13:52:07.16#ibcon#end of sib2, iclass 28, count 0 2006.173.13:52:07.16#ibcon#*after write, iclass 28, count 0 2006.173.13:52:07.16#ibcon#*before return 0, iclass 28, count 0 2006.173.13:52:07.16#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.13:52:07.16#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.13:52:07.16#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.13:52:07.16#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.13:52:07.16$vck44/vb=4,4 2006.173.13:52:07.16#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.13:52:07.16#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.13:52:07.16#ibcon#ireg 11 cls_cnt 2 2006.173.13:52:07.16#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.13:52:07.22#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.13:52:07.22#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.13:52:07.22#ibcon#enter wrdev, iclass 30, count 2 2006.173.13:52:07.22#ibcon#first serial, iclass 30, count 2 2006.173.13:52:07.22#ibcon#enter sib2, iclass 30, count 2 2006.173.13:52:07.22#ibcon#flushed, iclass 30, count 2 2006.173.13:52:07.22#ibcon#about to write, iclass 30, count 2 2006.173.13:52:07.22#ibcon#wrote, iclass 30, count 2 2006.173.13:52:07.22#ibcon#about to read 3, iclass 30, count 2 2006.173.13:52:07.24#ibcon#read 3, iclass 30, count 2 2006.173.13:52:07.24#ibcon#about to read 4, iclass 30, count 2 2006.173.13:52:07.24#ibcon#read 4, iclass 30, count 2 2006.173.13:52:07.24#ibcon#about to read 5, iclass 30, count 2 2006.173.13:52:07.24#ibcon#read 5, iclass 30, count 2 2006.173.13:52:07.24#ibcon#about to read 6, iclass 30, count 2 2006.173.13:52:07.24#ibcon#read 6, iclass 30, count 2 2006.173.13:52:07.24#ibcon#end of sib2, iclass 30, count 2 2006.173.13:52:07.24#ibcon#*mode == 0, iclass 30, count 2 2006.173.13:52:07.24#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.13:52:07.24#ibcon#[27=AT04-04\r\n] 2006.173.13:52:07.24#ibcon#*before write, iclass 30, count 2 2006.173.13:52:07.24#ibcon#enter sib2, iclass 30, count 2 2006.173.13:52:07.24#ibcon#flushed, iclass 30, count 2 2006.173.13:52:07.24#ibcon#about to write, iclass 30, count 2 2006.173.13:52:07.24#ibcon#wrote, iclass 30, count 2 2006.173.13:52:07.24#ibcon#about to read 3, iclass 30, count 2 2006.173.13:52:07.27#ibcon#read 3, iclass 30, count 2 2006.173.13:52:07.27#ibcon#about to read 4, iclass 30, count 2 2006.173.13:52:07.27#ibcon#read 4, iclass 30, count 2 2006.173.13:52:07.27#ibcon#about to read 5, iclass 30, count 2 2006.173.13:52:07.27#ibcon#read 5, iclass 30, count 2 2006.173.13:52:07.27#ibcon#about to read 6, iclass 30, count 2 2006.173.13:52:07.27#ibcon#read 6, iclass 30, count 2 2006.173.13:52:07.27#ibcon#end of sib2, iclass 30, count 2 2006.173.13:52:07.27#ibcon#*after write, iclass 30, count 2 2006.173.13:52:07.27#ibcon#*before return 0, iclass 30, count 2 2006.173.13:52:07.27#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.13:52:07.27#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.13:52:07.27#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.13:52:07.27#ibcon#ireg 7 cls_cnt 0 2006.173.13:52:07.27#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.13:52:07.39#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.13:52:07.39#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.13:52:07.39#ibcon#enter wrdev, iclass 30, count 0 2006.173.13:52:07.39#ibcon#first serial, iclass 30, count 0 2006.173.13:52:07.39#ibcon#enter sib2, iclass 30, count 0 2006.173.13:52:07.39#ibcon#flushed, iclass 30, count 0 2006.173.13:52:07.39#ibcon#about to write, iclass 30, count 0 2006.173.13:52:07.39#ibcon#wrote, iclass 30, count 0 2006.173.13:52:07.39#ibcon#about to read 3, iclass 30, count 0 2006.173.13:52:07.41#ibcon#read 3, iclass 30, count 0 2006.173.13:52:07.41#ibcon#about to read 4, iclass 30, count 0 2006.173.13:52:07.41#ibcon#read 4, iclass 30, count 0 2006.173.13:52:07.41#ibcon#about to read 5, iclass 30, count 0 2006.173.13:52:07.41#ibcon#read 5, iclass 30, count 0 2006.173.13:52:07.41#ibcon#about to read 6, iclass 30, count 0 2006.173.13:52:07.41#ibcon#read 6, iclass 30, count 0 2006.173.13:52:07.41#ibcon#end of sib2, iclass 30, count 0 2006.173.13:52:07.41#ibcon#*mode == 0, iclass 30, count 0 2006.173.13:52:07.41#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.13:52:07.41#ibcon#[27=USB\r\n] 2006.173.13:52:07.41#ibcon#*before write, iclass 30, count 0 2006.173.13:52:07.41#ibcon#enter sib2, iclass 30, count 0 2006.173.13:52:07.41#ibcon#flushed, iclass 30, count 0 2006.173.13:52:07.41#ibcon#about to write, iclass 30, count 0 2006.173.13:52:07.41#ibcon#wrote, iclass 30, count 0 2006.173.13:52:07.41#ibcon#about to read 3, iclass 30, count 0 2006.173.13:52:07.44#ibcon#read 3, iclass 30, count 0 2006.173.13:52:07.44#ibcon#about to read 4, iclass 30, count 0 2006.173.13:52:07.44#ibcon#read 4, iclass 30, count 0 2006.173.13:52:07.44#ibcon#about to read 5, iclass 30, count 0 2006.173.13:52:07.44#ibcon#read 5, iclass 30, count 0 2006.173.13:52:07.44#ibcon#about to read 6, iclass 30, count 0 2006.173.13:52:07.44#ibcon#read 6, iclass 30, count 0 2006.173.13:52:07.44#ibcon#end of sib2, iclass 30, count 0 2006.173.13:52:07.44#ibcon#*after write, iclass 30, count 0 2006.173.13:52:07.44#ibcon#*before return 0, iclass 30, count 0 2006.173.13:52:07.44#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.13:52:07.44#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.13:52:07.44#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.13:52:07.44#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.13:52:07.44$vck44/vblo=5,709.99 2006.173.13:52:07.44#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.13:52:07.44#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.13:52:07.44#ibcon#ireg 17 cls_cnt 0 2006.173.13:52:07.44#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.13:52:07.44#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.13:52:07.44#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.13:52:07.44#ibcon#enter wrdev, iclass 32, count 0 2006.173.13:52:07.44#ibcon#first serial, iclass 32, count 0 2006.173.13:52:07.44#ibcon#enter sib2, iclass 32, count 0 2006.173.13:52:07.44#ibcon#flushed, iclass 32, count 0 2006.173.13:52:07.44#ibcon#about to write, iclass 32, count 0 2006.173.13:52:07.44#ibcon#wrote, iclass 32, count 0 2006.173.13:52:07.44#ibcon#about to read 3, iclass 32, count 0 2006.173.13:52:07.46#ibcon#read 3, iclass 32, count 0 2006.173.13:52:07.46#ibcon#about to read 4, iclass 32, count 0 2006.173.13:52:07.46#ibcon#read 4, iclass 32, count 0 2006.173.13:52:07.46#ibcon#about to read 5, iclass 32, count 0 2006.173.13:52:07.46#ibcon#read 5, iclass 32, count 0 2006.173.13:52:07.46#ibcon#about to read 6, iclass 32, count 0 2006.173.13:52:07.46#ibcon#read 6, iclass 32, count 0 2006.173.13:52:07.46#ibcon#end of sib2, iclass 32, count 0 2006.173.13:52:07.46#ibcon#*mode == 0, iclass 32, count 0 2006.173.13:52:07.46#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.13:52:07.46#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.13:52:07.46#ibcon#*before write, iclass 32, count 0 2006.173.13:52:07.46#ibcon#enter sib2, iclass 32, count 0 2006.173.13:52:07.46#ibcon#flushed, iclass 32, count 0 2006.173.13:52:07.46#ibcon#about to write, iclass 32, count 0 2006.173.13:52:07.46#ibcon#wrote, iclass 32, count 0 2006.173.13:52:07.46#ibcon#about to read 3, iclass 32, count 0 2006.173.13:52:07.50#ibcon#read 3, iclass 32, count 0 2006.173.13:52:07.50#ibcon#about to read 4, iclass 32, count 0 2006.173.13:52:07.50#ibcon#read 4, iclass 32, count 0 2006.173.13:52:07.50#ibcon#about to read 5, iclass 32, count 0 2006.173.13:52:07.50#ibcon#read 5, iclass 32, count 0 2006.173.13:52:07.50#ibcon#about to read 6, iclass 32, count 0 2006.173.13:52:07.50#ibcon#read 6, iclass 32, count 0 2006.173.13:52:07.50#ibcon#end of sib2, iclass 32, count 0 2006.173.13:52:07.50#ibcon#*after write, iclass 32, count 0 2006.173.13:52:07.50#ibcon#*before return 0, iclass 32, count 0 2006.173.13:52:07.50#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.13:52:07.50#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.13:52:07.50#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.13:52:07.50#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.13:52:07.50$vck44/vb=5,4 2006.173.13:52:07.50#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.13:52:07.50#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.13:52:07.50#ibcon#ireg 11 cls_cnt 2 2006.173.13:52:07.50#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.13:52:07.56#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.13:52:07.56#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.13:52:07.56#ibcon#enter wrdev, iclass 34, count 2 2006.173.13:52:07.56#ibcon#first serial, iclass 34, count 2 2006.173.13:52:07.56#ibcon#enter sib2, iclass 34, count 2 2006.173.13:52:07.56#ibcon#flushed, iclass 34, count 2 2006.173.13:52:07.56#ibcon#about to write, iclass 34, count 2 2006.173.13:52:07.56#ibcon#wrote, iclass 34, count 2 2006.173.13:52:07.56#ibcon#about to read 3, iclass 34, count 2 2006.173.13:52:07.58#ibcon#read 3, iclass 34, count 2 2006.173.13:52:07.58#ibcon#about to read 4, iclass 34, count 2 2006.173.13:52:07.58#ibcon#read 4, iclass 34, count 2 2006.173.13:52:07.58#ibcon#about to read 5, iclass 34, count 2 2006.173.13:52:07.58#ibcon#read 5, iclass 34, count 2 2006.173.13:52:07.58#ibcon#about to read 6, iclass 34, count 2 2006.173.13:52:07.58#ibcon#read 6, iclass 34, count 2 2006.173.13:52:07.58#ibcon#end of sib2, iclass 34, count 2 2006.173.13:52:07.58#ibcon#*mode == 0, iclass 34, count 2 2006.173.13:52:07.58#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.13:52:07.58#ibcon#[27=AT05-04\r\n] 2006.173.13:52:07.58#ibcon#*before write, iclass 34, count 2 2006.173.13:52:07.58#ibcon#enter sib2, iclass 34, count 2 2006.173.13:52:07.58#ibcon#flushed, iclass 34, count 2 2006.173.13:52:07.58#ibcon#about to write, iclass 34, count 2 2006.173.13:52:07.58#ibcon#wrote, iclass 34, count 2 2006.173.13:52:07.58#ibcon#about to read 3, iclass 34, count 2 2006.173.13:52:07.61#ibcon#read 3, iclass 34, count 2 2006.173.13:52:07.61#ibcon#about to read 4, iclass 34, count 2 2006.173.13:52:07.61#ibcon#read 4, iclass 34, count 2 2006.173.13:52:07.61#ibcon#about to read 5, iclass 34, count 2 2006.173.13:52:07.61#ibcon#read 5, iclass 34, count 2 2006.173.13:52:07.61#ibcon#about to read 6, iclass 34, count 2 2006.173.13:52:07.61#ibcon#read 6, iclass 34, count 2 2006.173.13:52:07.61#ibcon#end of sib2, iclass 34, count 2 2006.173.13:52:07.61#ibcon#*after write, iclass 34, count 2 2006.173.13:52:07.61#ibcon#*before return 0, iclass 34, count 2 2006.173.13:52:07.61#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.13:52:07.61#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.13:52:07.61#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.13:52:07.61#ibcon#ireg 7 cls_cnt 0 2006.173.13:52:07.61#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.13:52:07.73#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.13:52:07.73#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.13:52:07.73#ibcon#enter wrdev, iclass 34, count 0 2006.173.13:52:07.73#ibcon#first serial, iclass 34, count 0 2006.173.13:52:07.73#ibcon#enter sib2, iclass 34, count 0 2006.173.13:52:07.73#ibcon#flushed, iclass 34, count 0 2006.173.13:52:07.73#ibcon#about to write, iclass 34, count 0 2006.173.13:52:07.73#ibcon#wrote, iclass 34, count 0 2006.173.13:52:07.73#ibcon#about to read 3, iclass 34, count 0 2006.173.13:52:07.75#ibcon#read 3, iclass 34, count 0 2006.173.13:52:07.75#ibcon#about to read 4, iclass 34, count 0 2006.173.13:52:07.75#ibcon#read 4, iclass 34, count 0 2006.173.13:52:07.75#ibcon#about to read 5, iclass 34, count 0 2006.173.13:52:07.75#ibcon#read 5, iclass 34, count 0 2006.173.13:52:07.75#ibcon#about to read 6, iclass 34, count 0 2006.173.13:52:07.75#ibcon#read 6, iclass 34, count 0 2006.173.13:52:07.75#ibcon#end of sib2, iclass 34, count 0 2006.173.13:52:07.75#ibcon#*mode == 0, iclass 34, count 0 2006.173.13:52:07.75#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.13:52:07.75#ibcon#[27=USB\r\n] 2006.173.13:52:07.75#ibcon#*before write, iclass 34, count 0 2006.173.13:52:07.75#ibcon#enter sib2, iclass 34, count 0 2006.173.13:52:07.75#ibcon#flushed, iclass 34, count 0 2006.173.13:52:07.75#ibcon#about to write, iclass 34, count 0 2006.173.13:52:07.75#ibcon#wrote, iclass 34, count 0 2006.173.13:52:07.75#ibcon#about to read 3, iclass 34, count 0 2006.173.13:52:07.78#ibcon#read 3, iclass 34, count 0 2006.173.13:52:07.78#ibcon#about to read 4, iclass 34, count 0 2006.173.13:52:07.78#ibcon#read 4, iclass 34, count 0 2006.173.13:52:07.78#ibcon#about to read 5, iclass 34, count 0 2006.173.13:52:07.78#ibcon#read 5, iclass 34, count 0 2006.173.13:52:07.78#ibcon#about to read 6, iclass 34, count 0 2006.173.13:52:07.78#ibcon#read 6, iclass 34, count 0 2006.173.13:52:07.78#ibcon#end of sib2, iclass 34, count 0 2006.173.13:52:07.78#ibcon#*after write, iclass 34, count 0 2006.173.13:52:07.78#ibcon#*before return 0, iclass 34, count 0 2006.173.13:52:07.78#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.13:52:07.78#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.13:52:07.78#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.13:52:07.78#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.13:52:07.78$vck44/vblo=6,719.99 2006.173.13:52:07.78#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.13:52:07.78#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.13:52:07.78#ibcon#ireg 17 cls_cnt 0 2006.173.13:52:07.78#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.13:52:07.78#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.13:52:07.78#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.13:52:07.78#ibcon#enter wrdev, iclass 36, count 0 2006.173.13:52:07.78#ibcon#first serial, iclass 36, count 0 2006.173.13:52:07.78#ibcon#enter sib2, iclass 36, count 0 2006.173.13:52:07.78#ibcon#flushed, iclass 36, count 0 2006.173.13:52:07.78#ibcon#about to write, iclass 36, count 0 2006.173.13:52:07.78#ibcon#wrote, iclass 36, count 0 2006.173.13:52:07.78#ibcon#about to read 3, iclass 36, count 0 2006.173.13:52:07.80#ibcon#read 3, iclass 36, count 0 2006.173.13:52:07.80#ibcon#about to read 4, iclass 36, count 0 2006.173.13:52:07.80#ibcon#read 4, iclass 36, count 0 2006.173.13:52:07.80#ibcon#about to read 5, iclass 36, count 0 2006.173.13:52:07.80#ibcon#read 5, iclass 36, count 0 2006.173.13:52:07.80#ibcon#about to read 6, iclass 36, count 0 2006.173.13:52:07.80#ibcon#read 6, iclass 36, count 0 2006.173.13:52:07.80#ibcon#end of sib2, iclass 36, count 0 2006.173.13:52:07.80#ibcon#*mode == 0, iclass 36, count 0 2006.173.13:52:07.80#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.13:52:07.80#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.13:52:07.80#ibcon#*before write, iclass 36, count 0 2006.173.13:52:07.80#ibcon#enter sib2, iclass 36, count 0 2006.173.13:52:07.80#ibcon#flushed, iclass 36, count 0 2006.173.13:52:07.80#ibcon#about to write, iclass 36, count 0 2006.173.13:52:07.80#ibcon#wrote, iclass 36, count 0 2006.173.13:52:07.80#ibcon#about to read 3, iclass 36, count 0 2006.173.13:52:07.84#ibcon#read 3, iclass 36, count 0 2006.173.13:52:07.84#ibcon#about to read 4, iclass 36, count 0 2006.173.13:52:07.84#ibcon#read 4, iclass 36, count 0 2006.173.13:52:07.84#ibcon#about to read 5, iclass 36, count 0 2006.173.13:52:07.84#ibcon#read 5, iclass 36, count 0 2006.173.13:52:07.84#ibcon#about to read 6, iclass 36, count 0 2006.173.13:52:07.84#ibcon#read 6, iclass 36, count 0 2006.173.13:52:07.84#ibcon#end of sib2, iclass 36, count 0 2006.173.13:52:07.84#ibcon#*after write, iclass 36, count 0 2006.173.13:52:07.84#ibcon#*before return 0, iclass 36, count 0 2006.173.13:52:07.84#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.13:52:07.84#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.13:52:07.84#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.13:52:07.84#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.13:52:07.84$vck44/vb=6,4 2006.173.13:52:07.84#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.13:52:07.84#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.13:52:07.84#ibcon#ireg 11 cls_cnt 2 2006.173.13:52:07.84#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.13:52:07.90#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.13:52:07.90#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.13:52:07.90#ibcon#enter wrdev, iclass 38, count 2 2006.173.13:52:07.90#ibcon#first serial, iclass 38, count 2 2006.173.13:52:07.90#ibcon#enter sib2, iclass 38, count 2 2006.173.13:52:07.90#ibcon#flushed, iclass 38, count 2 2006.173.13:52:07.90#ibcon#about to write, iclass 38, count 2 2006.173.13:52:07.90#ibcon#wrote, iclass 38, count 2 2006.173.13:52:07.90#ibcon#about to read 3, iclass 38, count 2 2006.173.13:52:07.92#ibcon#read 3, iclass 38, count 2 2006.173.13:52:07.92#ibcon#about to read 4, iclass 38, count 2 2006.173.13:52:07.92#ibcon#read 4, iclass 38, count 2 2006.173.13:52:07.92#ibcon#about to read 5, iclass 38, count 2 2006.173.13:52:07.92#ibcon#read 5, iclass 38, count 2 2006.173.13:52:07.92#ibcon#about to read 6, iclass 38, count 2 2006.173.13:52:07.92#ibcon#read 6, iclass 38, count 2 2006.173.13:52:07.92#ibcon#end of sib2, iclass 38, count 2 2006.173.13:52:07.92#ibcon#*mode == 0, iclass 38, count 2 2006.173.13:52:07.92#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.13:52:07.92#ibcon#[27=AT06-04\r\n] 2006.173.13:52:07.92#ibcon#*before write, iclass 38, count 2 2006.173.13:52:07.92#ibcon#enter sib2, iclass 38, count 2 2006.173.13:52:07.92#ibcon#flushed, iclass 38, count 2 2006.173.13:52:07.92#ibcon#about to write, iclass 38, count 2 2006.173.13:52:07.92#ibcon#wrote, iclass 38, count 2 2006.173.13:52:07.92#ibcon#about to read 3, iclass 38, count 2 2006.173.13:52:07.95#ibcon#read 3, iclass 38, count 2 2006.173.13:52:07.95#ibcon#about to read 4, iclass 38, count 2 2006.173.13:52:07.95#ibcon#read 4, iclass 38, count 2 2006.173.13:52:07.95#ibcon#about to read 5, iclass 38, count 2 2006.173.13:52:07.95#ibcon#read 5, iclass 38, count 2 2006.173.13:52:07.95#ibcon#about to read 6, iclass 38, count 2 2006.173.13:52:07.95#ibcon#read 6, iclass 38, count 2 2006.173.13:52:07.95#ibcon#end of sib2, iclass 38, count 2 2006.173.13:52:07.95#ibcon#*after write, iclass 38, count 2 2006.173.13:52:07.95#ibcon#*before return 0, iclass 38, count 2 2006.173.13:52:07.95#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.13:52:07.95#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.13:52:07.95#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.13:52:07.95#ibcon#ireg 7 cls_cnt 0 2006.173.13:52:07.95#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.13:52:08.07#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.13:52:08.07#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.13:52:08.07#ibcon#enter wrdev, iclass 38, count 0 2006.173.13:52:08.07#ibcon#first serial, iclass 38, count 0 2006.173.13:52:08.07#ibcon#enter sib2, iclass 38, count 0 2006.173.13:52:08.07#ibcon#flushed, iclass 38, count 0 2006.173.13:52:08.07#ibcon#about to write, iclass 38, count 0 2006.173.13:52:08.07#ibcon#wrote, iclass 38, count 0 2006.173.13:52:08.07#ibcon#about to read 3, iclass 38, count 0 2006.173.13:52:08.09#ibcon#read 3, iclass 38, count 0 2006.173.13:52:08.09#ibcon#about to read 4, iclass 38, count 0 2006.173.13:52:08.09#ibcon#read 4, iclass 38, count 0 2006.173.13:52:08.09#ibcon#about to read 5, iclass 38, count 0 2006.173.13:52:08.09#ibcon#read 5, iclass 38, count 0 2006.173.13:52:08.09#ibcon#about to read 6, iclass 38, count 0 2006.173.13:52:08.09#ibcon#read 6, iclass 38, count 0 2006.173.13:52:08.09#ibcon#end of sib2, iclass 38, count 0 2006.173.13:52:08.09#ibcon#*mode == 0, iclass 38, count 0 2006.173.13:52:08.09#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.13:52:08.09#ibcon#[27=USB\r\n] 2006.173.13:52:08.09#ibcon#*before write, iclass 38, count 0 2006.173.13:52:08.09#ibcon#enter sib2, iclass 38, count 0 2006.173.13:52:08.09#ibcon#flushed, iclass 38, count 0 2006.173.13:52:08.09#ibcon#about to write, iclass 38, count 0 2006.173.13:52:08.09#ibcon#wrote, iclass 38, count 0 2006.173.13:52:08.09#ibcon#about to read 3, iclass 38, count 0 2006.173.13:52:08.12#ibcon#read 3, iclass 38, count 0 2006.173.13:52:08.12#ibcon#about to read 4, iclass 38, count 0 2006.173.13:52:08.12#ibcon#read 4, iclass 38, count 0 2006.173.13:52:08.12#ibcon#about to read 5, iclass 38, count 0 2006.173.13:52:08.12#ibcon#read 5, iclass 38, count 0 2006.173.13:52:08.12#ibcon#about to read 6, iclass 38, count 0 2006.173.13:52:08.12#ibcon#read 6, iclass 38, count 0 2006.173.13:52:08.12#ibcon#end of sib2, iclass 38, count 0 2006.173.13:52:08.12#ibcon#*after write, iclass 38, count 0 2006.173.13:52:08.12#ibcon#*before return 0, iclass 38, count 0 2006.173.13:52:08.12#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.13:52:08.12#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.13:52:08.12#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.13:52:08.12#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.13:52:08.12$vck44/vblo=7,734.99 2006.173.13:52:08.12#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.13:52:08.12#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.13:52:08.12#ibcon#ireg 17 cls_cnt 0 2006.173.13:52:08.12#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.13:52:08.12#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.13:52:08.12#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.13:52:08.12#ibcon#enter wrdev, iclass 40, count 0 2006.173.13:52:08.12#ibcon#first serial, iclass 40, count 0 2006.173.13:52:08.12#ibcon#enter sib2, iclass 40, count 0 2006.173.13:52:08.12#ibcon#flushed, iclass 40, count 0 2006.173.13:52:08.12#ibcon#about to write, iclass 40, count 0 2006.173.13:52:08.12#ibcon#wrote, iclass 40, count 0 2006.173.13:52:08.12#ibcon#about to read 3, iclass 40, count 0 2006.173.13:52:08.14#ibcon#read 3, iclass 40, count 0 2006.173.13:52:08.14#ibcon#about to read 4, iclass 40, count 0 2006.173.13:52:08.14#ibcon#read 4, iclass 40, count 0 2006.173.13:52:08.14#ibcon#about to read 5, iclass 40, count 0 2006.173.13:52:08.14#ibcon#read 5, iclass 40, count 0 2006.173.13:52:08.14#ibcon#about to read 6, iclass 40, count 0 2006.173.13:52:08.14#ibcon#read 6, iclass 40, count 0 2006.173.13:52:08.14#ibcon#end of sib2, iclass 40, count 0 2006.173.13:52:08.14#ibcon#*mode == 0, iclass 40, count 0 2006.173.13:52:08.14#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.13:52:08.14#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.13:52:08.14#ibcon#*before write, iclass 40, count 0 2006.173.13:52:08.14#ibcon#enter sib2, iclass 40, count 0 2006.173.13:52:08.14#ibcon#flushed, iclass 40, count 0 2006.173.13:52:08.14#ibcon#about to write, iclass 40, count 0 2006.173.13:52:08.14#ibcon#wrote, iclass 40, count 0 2006.173.13:52:08.14#ibcon#about to read 3, iclass 40, count 0 2006.173.13:52:08.18#ibcon#read 3, iclass 40, count 0 2006.173.13:52:08.18#ibcon#about to read 4, iclass 40, count 0 2006.173.13:52:08.18#ibcon#read 4, iclass 40, count 0 2006.173.13:52:08.18#ibcon#about to read 5, iclass 40, count 0 2006.173.13:52:08.18#ibcon#read 5, iclass 40, count 0 2006.173.13:52:08.18#ibcon#about to read 6, iclass 40, count 0 2006.173.13:52:08.18#ibcon#read 6, iclass 40, count 0 2006.173.13:52:08.18#ibcon#end of sib2, iclass 40, count 0 2006.173.13:52:08.18#ibcon#*after write, iclass 40, count 0 2006.173.13:52:08.18#ibcon#*before return 0, iclass 40, count 0 2006.173.13:52:08.18#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.13:52:08.18#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.13:52:08.18#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.13:52:08.18#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.13:52:08.18$vck44/vb=7,4 2006.173.13:52:08.18#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.13:52:08.18#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.13:52:08.18#ibcon#ireg 11 cls_cnt 2 2006.173.13:52:08.18#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.13:52:08.24#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.13:52:08.24#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.13:52:08.24#ibcon#enter wrdev, iclass 4, count 2 2006.173.13:52:08.24#ibcon#first serial, iclass 4, count 2 2006.173.13:52:08.24#ibcon#enter sib2, iclass 4, count 2 2006.173.13:52:08.24#ibcon#flushed, iclass 4, count 2 2006.173.13:52:08.24#ibcon#about to write, iclass 4, count 2 2006.173.13:52:08.24#ibcon#wrote, iclass 4, count 2 2006.173.13:52:08.24#ibcon#about to read 3, iclass 4, count 2 2006.173.13:52:08.26#ibcon#read 3, iclass 4, count 2 2006.173.13:52:08.26#ibcon#about to read 4, iclass 4, count 2 2006.173.13:52:08.26#ibcon#read 4, iclass 4, count 2 2006.173.13:52:08.26#ibcon#about to read 5, iclass 4, count 2 2006.173.13:52:08.26#ibcon#read 5, iclass 4, count 2 2006.173.13:52:08.26#ibcon#about to read 6, iclass 4, count 2 2006.173.13:52:08.26#ibcon#read 6, iclass 4, count 2 2006.173.13:52:08.26#ibcon#end of sib2, iclass 4, count 2 2006.173.13:52:08.26#ibcon#*mode == 0, iclass 4, count 2 2006.173.13:52:08.26#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.13:52:08.26#ibcon#[27=AT07-04\r\n] 2006.173.13:52:08.26#ibcon#*before write, iclass 4, count 2 2006.173.13:52:08.26#ibcon#enter sib2, iclass 4, count 2 2006.173.13:52:08.26#ibcon#flushed, iclass 4, count 2 2006.173.13:52:08.26#ibcon#about to write, iclass 4, count 2 2006.173.13:52:08.26#ibcon#wrote, iclass 4, count 2 2006.173.13:52:08.26#ibcon#about to read 3, iclass 4, count 2 2006.173.13:52:08.29#ibcon#read 3, iclass 4, count 2 2006.173.13:52:08.29#ibcon#about to read 4, iclass 4, count 2 2006.173.13:52:08.29#ibcon#read 4, iclass 4, count 2 2006.173.13:52:08.29#ibcon#about to read 5, iclass 4, count 2 2006.173.13:52:08.29#ibcon#read 5, iclass 4, count 2 2006.173.13:52:08.29#ibcon#about to read 6, iclass 4, count 2 2006.173.13:52:08.29#ibcon#read 6, iclass 4, count 2 2006.173.13:52:08.29#ibcon#end of sib2, iclass 4, count 2 2006.173.13:52:08.29#ibcon#*after write, iclass 4, count 2 2006.173.13:52:08.29#ibcon#*before return 0, iclass 4, count 2 2006.173.13:52:08.29#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.13:52:08.29#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.13:52:08.29#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.13:52:08.29#ibcon#ireg 7 cls_cnt 0 2006.173.13:52:08.29#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.13:52:08.41#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.13:52:08.41#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.13:52:08.41#ibcon#enter wrdev, iclass 4, count 0 2006.173.13:52:08.41#ibcon#first serial, iclass 4, count 0 2006.173.13:52:08.41#ibcon#enter sib2, iclass 4, count 0 2006.173.13:52:08.41#ibcon#flushed, iclass 4, count 0 2006.173.13:52:08.41#ibcon#about to write, iclass 4, count 0 2006.173.13:52:08.41#ibcon#wrote, iclass 4, count 0 2006.173.13:52:08.41#ibcon#about to read 3, iclass 4, count 0 2006.173.13:52:08.43#ibcon#read 3, iclass 4, count 0 2006.173.13:52:08.43#ibcon#about to read 4, iclass 4, count 0 2006.173.13:52:08.43#ibcon#read 4, iclass 4, count 0 2006.173.13:52:08.43#ibcon#about to read 5, iclass 4, count 0 2006.173.13:52:08.43#ibcon#read 5, iclass 4, count 0 2006.173.13:52:08.43#ibcon#about to read 6, iclass 4, count 0 2006.173.13:52:08.43#ibcon#read 6, iclass 4, count 0 2006.173.13:52:08.43#ibcon#end of sib2, iclass 4, count 0 2006.173.13:52:08.43#ibcon#*mode == 0, iclass 4, count 0 2006.173.13:52:08.43#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.13:52:08.43#ibcon#[27=USB\r\n] 2006.173.13:52:08.43#ibcon#*before write, iclass 4, count 0 2006.173.13:52:08.43#ibcon#enter sib2, iclass 4, count 0 2006.173.13:52:08.43#ibcon#flushed, iclass 4, count 0 2006.173.13:52:08.43#ibcon#about to write, iclass 4, count 0 2006.173.13:52:08.43#ibcon#wrote, iclass 4, count 0 2006.173.13:52:08.43#ibcon#about to read 3, iclass 4, count 0 2006.173.13:52:08.46#ibcon#read 3, iclass 4, count 0 2006.173.13:52:08.46#ibcon#about to read 4, iclass 4, count 0 2006.173.13:52:08.46#ibcon#read 4, iclass 4, count 0 2006.173.13:52:08.46#ibcon#about to read 5, iclass 4, count 0 2006.173.13:52:08.46#ibcon#read 5, iclass 4, count 0 2006.173.13:52:08.46#ibcon#about to read 6, iclass 4, count 0 2006.173.13:52:08.46#ibcon#read 6, iclass 4, count 0 2006.173.13:52:08.46#ibcon#end of sib2, iclass 4, count 0 2006.173.13:52:08.46#ibcon#*after write, iclass 4, count 0 2006.173.13:52:08.46#ibcon#*before return 0, iclass 4, count 0 2006.173.13:52:08.46#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.13:52:08.46#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.13:52:08.46#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.13:52:08.46#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.13:52:08.46$vck44/vblo=8,744.99 2006.173.13:52:08.46#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.13:52:08.46#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.13:52:08.46#ibcon#ireg 17 cls_cnt 0 2006.173.13:52:08.46#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.13:52:08.46#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.13:52:08.46#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.13:52:08.46#ibcon#enter wrdev, iclass 6, count 0 2006.173.13:52:08.46#ibcon#first serial, iclass 6, count 0 2006.173.13:52:08.46#ibcon#enter sib2, iclass 6, count 0 2006.173.13:52:08.46#ibcon#flushed, iclass 6, count 0 2006.173.13:52:08.46#ibcon#about to write, iclass 6, count 0 2006.173.13:52:08.46#ibcon#wrote, iclass 6, count 0 2006.173.13:52:08.46#ibcon#about to read 3, iclass 6, count 0 2006.173.13:52:08.48#ibcon#read 3, iclass 6, count 0 2006.173.13:52:08.48#ibcon#about to read 4, iclass 6, count 0 2006.173.13:52:08.48#ibcon#read 4, iclass 6, count 0 2006.173.13:52:08.48#ibcon#about to read 5, iclass 6, count 0 2006.173.13:52:08.48#ibcon#read 5, iclass 6, count 0 2006.173.13:52:08.48#ibcon#about to read 6, iclass 6, count 0 2006.173.13:52:08.48#ibcon#read 6, iclass 6, count 0 2006.173.13:52:08.48#ibcon#end of sib2, iclass 6, count 0 2006.173.13:52:08.48#ibcon#*mode == 0, iclass 6, count 0 2006.173.13:52:08.48#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.13:52:08.48#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.13:52:08.48#ibcon#*before write, iclass 6, count 0 2006.173.13:52:08.48#ibcon#enter sib2, iclass 6, count 0 2006.173.13:52:08.48#ibcon#flushed, iclass 6, count 0 2006.173.13:52:08.48#ibcon#about to write, iclass 6, count 0 2006.173.13:52:08.48#ibcon#wrote, iclass 6, count 0 2006.173.13:52:08.48#ibcon#about to read 3, iclass 6, count 0 2006.173.13:52:08.52#ibcon#read 3, iclass 6, count 0 2006.173.13:52:08.52#ibcon#about to read 4, iclass 6, count 0 2006.173.13:52:08.52#ibcon#read 4, iclass 6, count 0 2006.173.13:52:08.52#ibcon#about to read 5, iclass 6, count 0 2006.173.13:52:08.52#ibcon#read 5, iclass 6, count 0 2006.173.13:52:08.52#ibcon#about to read 6, iclass 6, count 0 2006.173.13:52:08.52#ibcon#read 6, iclass 6, count 0 2006.173.13:52:08.52#ibcon#end of sib2, iclass 6, count 0 2006.173.13:52:08.52#ibcon#*after write, iclass 6, count 0 2006.173.13:52:08.52#ibcon#*before return 0, iclass 6, count 0 2006.173.13:52:08.52#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.13:52:08.52#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.13:52:08.52#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.13:52:08.52#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.13:52:08.52$vck44/vb=8,4 2006.173.13:52:08.52#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.13:52:08.52#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.13:52:08.52#ibcon#ireg 11 cls_cnt 2 2006.173.13:52:08.52#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.13:52:08.58#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.13:52:08.58#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.13:52:08.58#ibcon#enter wrdev, iclass 10, count 2 2006.173.13:52:08.58#ibcon#first serial, iclass 10, count 2 2006.173.13:52:08.58#ibcon#enter sib2, iclass 10, count 2 2006.173.13:52:08.58#ibcon#flushed, iclass 10, count 2 2006.173.13:52:08.58#ibcon#about to write, iclass 10, count 2 2006.173.13:52:08.58#ibcon#wrote, iclass 10, count 2 2006.173.13:52:08.58#ibcon#about to read 3, iclass 10, count 2 2006.173.13:52:08.60#ibcon#read 3, iclass 10, count 2 2006.173.13:52:08.60#ibcon#about to read 4, iclass 10, count 2 2006.173.13:52:08.60#ibcon#read 4, iclass 10, count 2 2006.173.13:52:08.60#ibcon#about to read 5, iclass 10, count 2 2006.173.13:52:08.60#ibcon#read 5, iclass 10, count 2 2006.173.13:52:08.60#ibcon#about to read 6, iclass 10, count 2 2006.173.13:52:08.60#ibcon#read 6, iclass 10, count 2 2006.173.13:52:08.60#ibcon#end of sib2, iclass 10, count 2 2006.173.13:52:08.60#ibcon#*mode == 0, iclass 10, count 2 2006.173.13:52:08.60#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.13:52:08.60#ibcon#[27=AT08-04\r\n] 2006.173.13:52:08.60#ibcon#*before write, iclass 10, count 2 2006.173.13:52:08.60#ibcon#enter sib2, iclass 10, count 2 2006.173.13:52:08.60#ibcon#flushed, iclass 10, count 2 2006.173.13:52:08.60#ibcon#about to write, iclass 10, count 2 2006.173.13:52:08.60#ibcon#wrote, iclass 10, count 2 2006.173.13:52:08.60#ibcon#about to read 3, iclass 10, count 2 2006.173.13:52:08.63#ibcon#read 3, iclass 10, count 2 2006.173.13:52:08.63#ibcon#about to read 4, iclass 10, count 2 2006.173.13:52:08.63#ibcon#read 4, iclass 10, count 2 2006.173.13:52:08.63#ibcon#about to read 5, iclass 10, count 2 2006.173.13:52:08.63#ibcon#read 5, iclass 10, count 2 2006.173.13:52:08.63#ibcon#about to read 6, iclass 10, count 2 2006.173.13:52:08.63#ibcon#read 6, iclass 10, count 2 2006.173.13:52:08.63#ibcon#end of sib2, iclass 10, count 2 2006.173.13:52:08.63#ibcon#*after write, iclass 10, count 2 2006.173.13:52:08.63#ibcon#*before return 0, iclass 10, count 2 2006.173.13:52:08.63#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.13:52:08.63#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.13:52:08.63#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.13:52:08.63#ibcon#ireg 7 cls_cnt 0 2006.173.13:52:08.63#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.13:52:08.75#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.13:52:08.75#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.13:52:08.75#ibcon#enter wrdev, iclass 10, count 0 2006.173.13:52:08.75#ibcon#first serial, iclass 10, count 0 2006.173.13:52:08.75#ibcon#enter sib2, iclass 10, count 0 2006.173.13:52:08.75#ibcon#flushed, iclass 10, count 0 2006.173.13:52:08.75#ibcon#about to write, iclass 10, count 0 2006.173.13:52:08.75#ibcon#wrote, iclass 10, count 0 2006.173.13:52:08.75#ibcon#about to read 3, iclass 10, count 0 2006.173.13:52:08.77#ibcon#read 3, iclass 10, count 0 2006.173.13:52:08.77#ibcon#about to read 4, iclass 10, count 0 2006.173.13:52:08.77#ibcon#read 4, iclass 10, count 0 2006.173.13:52:08.77#ibcon#about to read 5, iclass 10, count 0 2006.173.13:52:08.77#ibcon#read 5, iclass 10, count 0 2006.173.13:52:08.77#ibcon#about to read 6, iclass 10, count 0 2006.173.13:52:08.77#ibcon#read 6, iclass 10, count 0 2006.173.13:52:08.77#ibcon#end of sib2, iclass 10, count 0 2006.173.13:52:08.77#ibcon#*mode == 0, iclass 10, count 0 2006.173.13:52:08.77#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.13:52:08.77#ibcon#[27=USB\r\n] 2006.173.13:52:08.77#ibcon#*before write, iclass 10, count 0 2006.173.13:52:08.77#ibcon#enter sib2, iclass 10, count 0 2006.173.13:52:08.77#ibcon#flushed, iclass 10, count 0 2006.173.13:52:08.77#ibcon#about to write, iclass 10, count 0 2006.173.13:52:08.77#ibcon#wrote, iclass 10, count 0 2006.173.13:52:08.77#ibcon#about to read 3, iclass 10, count 0 2006.173.13:52:08.80#ibcon#read 3, iclass 10, count 0 2006.173.13:52:08.80#ibcon#about to read 4, iclass 10, count 0 2006.173.13:52:08.80#ibcon#read 4, iclass 10, count 0 2006.173.13:52:08.80#ibcon#about to read 5, iclass 10, count 0 2006.173.13:52:08.80#ibcon#read 5, iclass 10, count 0 2006.173.13:52:08.80#ibcon#about to read 6, iclass 10, count 0 2006.173.13:52:08.80#ibcon#read 6, iclass 10, count 0 2006.173.13:52:08.80#ibcon#end of sib2, iclass 10, count 0 2006.173.13:52:08.80#ibcon#*after write, iclass 10, count 0 2006.173.13:52:08.80#ibcon#*before return 0, iclass 10, count 0 2006.173.13:52:08.80#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.13:52:08.80#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.13:52:08.80#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.13:52:08.80#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.13:52:08.80$vck44/vabw=wide 2006.173.13:52:08.80#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.13:52:08.80#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.13:52:08.80#ibcon#ireg 8 cls_cnt 0 2006.173.13:52:08.80#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.13:52:08.80#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.13:52:08.80#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.13:52:08.80#ibcon#enter wrdev, iclass 12, count 0 2006.173.13:52:08.80#ibcon#first serial, iclass 12, count 0 2006.173.13:52:08.80#ibcon#enter sib2, iclass 12, count 0 2006.173.13:52:08.80#ibcon#flushed, iclass 12, count 0 2006.173.13:52:08.80#ibcon#about to write, iclass 12, count 0 2006.173.13:52:08.80#ibcon#wrote, iclass 12, count 0 2006.173.13:52:08.80#ibcon#about to read 3, iclass 12, count 0 2006.173.13:52:08.82#ibcon#read 3, iclass 12, count 0 2006.173.13:52:08.82#ibcon#about to read 4, iclass 12, count 0 2006.173.13:52:08.82#ibcon#read 4, iclass 12, count 0 2006.173.13:52:08.82#ibcon#about to read 5, iclass 12, count 0 2006.173.13:52:08.82#ibcon#read 5, iclass 12, count 0 2006.173.13:52:08.82#ibcon#about to read 6, iclass 12, count 0 2006.173.13:52:08.82#ibcon#read 6, iclass 12, count 0 2006.173.13:52:08.82#ibcon#end of sib2, iclass 12, count 0 2006.173.13:52:08.82#ibcon#*mode == 0, iclass 12, count 0 2006.173.13:52:08.82#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.13:52:08.82#ibcon#[25=BW32\r\n] 2006.173.13:52:08.82#ibcon#*before write, iclass 12, count 0 2006.173.13:52:08.82#ibcon#enter sib2, iclass 12, count 0 2006.173.13:52:08.82#ibcon#flushed, iclass 12, count 0 2006.173.13:52:08.82#ibcon#about to write, iclass 12, count 0 2006.173.13:52:08.82#ibcon#wrote, iclass 12, count 0 2006.173.13:52:08.82#ibcon#about to read 3, iclass 12, count 0 2006.173.13:52:08.85#ibcon#read 3, iclass 12, count 0 2006.173.13:52:08.85#ibcon#about to read 4, iclass 12, count 0 2006.173.13:52:08.85#ibcon#read 4, iclass 12, count 0 2006.173.13:52:08.85#ibcon#about to read 5, iclass 12, count 0 2006.173.13:52:08.85#ibcon#read 5, iclass 12, count 0 2006.173.13:52:08.85#ibcon#about to read 6, iclass 12, count 0 2006.173.13:52:08.85#ibcon#read 6, iclass 12, count 0 2006.173.13:52:08.85#ibcon#end of sib2, iclass 12, count 0 2006.173.13:52:08.85#ibcon#*after write, iclass 12, count 0 2006.173.13:52:08.85#ibcon#*before return 0, iclass 12, count 0 2006.173.13:52:08.85#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.13:52:08.85#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.13:52:08.85#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.13:52:08.85#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.13:52:08.85$vck44/vbbw=wide 2006.173.13:52:08.85#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.13:52:08.85#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.13:52:08.85#ibcon#ireg 8 cls_cnt 0 2006.173.13:52:08.85#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.13:52:08.92#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.13:52:08.92#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.13:52:08.92#ibcon#enter wrdev, iclass 14, count 0 2006.173.13:52:08.92#ibcon#first serial, iclass 14, count 0 2006.173.13:52:08.92#ibcon#enter sib2, iclass 14, count 0 2006.173.13:52:08.92#ibcon#flushed, iclass 14, count 0 2006.173.13:52:08.92#ibcon#about to write, iclass 14, count 0 2006.173.13:52:08.92#ibcon#wrote, iclass 14, count 0 2006.173.13:52:08.92#ibcon#about to read 3, iclass 14, count 0 2006.173.13:52:08.94#ibcon#read 3, iclass 14, count 0 2006.173.13:52:08.94#ibcon#about to read 4, iclass 14, count 0 2006.173.13:52:08.94#ibcon#read 4, iclass 14, count 0 2006.173.13:52:08.94#ibcon#about to read 5, iclass 14, count 0 2006.173.13:52:08.94#ibcon#read 5, iclass 14, count 0 2006.173.13:52:08.94#ibcon#about to read 6, iclass 14, count 0 2006.173.13:52:08.94#ibcon#read 6, iclass 14, count 0 2006.173.13:52:08.94#ibcon#end of sib2, iclass 14, count 0 2006.173.13:52:08.94#ibcon#*mode == 0, iclass 14, count 0 2006.173.13:52:08.94#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.13:52:08.94#ibcon#[27=BW32\r\n] 2006.173.13:52:08.94#ibcon#*before write, iclass 14, count 0 2006.173.13:52:08.94#ibcon#enter sib2, iclass 14, count 0 2006.173.13:52:08.94#ibcon#flushed, iclass 14, count 0 2006.173.13:52:08.94#ibcon#about to write, iclass 14, count 0 2006.173.13:52:08.94#ibcon#wrote, iclass 14, count 0 2006.173.13:52:08.94#ibcon#about to read 3, iclass 14, count 0 2006.173.13:52:08.97#ibcon#read 3, iclass 14, count 0 2006.173.13:52:08.97#ibcon#about to read 4, iclass 14, count 0 2006.173.13:52:08.97#ibcon#read 4, iclass 14, count 0 2006.173.13:52:08.97#ibcon#about to read 5, iclass 14, count 0 2006.173.13:52:08.97#ibcon#read 5, iclass 14, count 0 2006.173.13:52:08.97#ibcon#about to read 6, iclass 14, count 0 2006.173.13:52:08.97#ibcon#read 6, iclass 14, count 0 2006.173.13:52:08.97#ibcon#end of sib2, iclass 14, count 0 2006.173.13:52:08.97#ibcon#*after write, iclass 14, count 0 2006.173.13:52:08.97#ibcon#*before return 0, iclass 14, count 0 2006.173.13:52:08.97#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.13:52:08.97#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.13:52:08.97#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.13:52:08.97#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.13:52:08.97$setupk4/ifdk4 2006.173.13:52:08.97$ifdk4/lo= 2006.173.13:52:08.97$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.13:52:08.97$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.13:52:08.97$ifdk4/patch= 2006.173.13:52:08.97$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.13:52:08.97$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.13:52:08.97$setupk4/!*+20s 2006.173.13:52:14.24#abcon#<5=/05 0.6 1.1 21.851001003.7\r\n> 2006.173.13:52:14.26#abcon#{5=INTERFACE CLEAR} 2006.173.13:52:14.32#abcon#[5=S1D000X0/0*\r\n] 2006.173.13:52:23.48$setupk4/"tpicd 2006.173.13:52:23.48$setupk4/echo=off 2006.173.13:52:23.48$setupk4/xlog=off 2006.173.13:52:23.48:!2006.173.13:52:54 2006.173.13:52:24.14#trakl#Source acquired 2006.173.13:52:24.14#flagr#flagr/antenna,acquired 2006.173.13:52:54.00:preob 2006.173.13:52:55.14/onsource/TRACKING 2006.173.13:52:55.14:!2006.173.13:53:04 2006.173.13:53:04.00:"tape 2006.173.13:53:04.00:"st=record 2006.173.13:53:04.00:data_valid=on 2006.173.13:53:04.00:midob 2006.173.13:53:04.14/onsource/TRACKING 2006.173.13:53:04.14/wx/21.84,1003.7,100 2006.173.13:53:04.32/cable/+6.5063E-03 2006.173.13:53:05.41/va/01,07,usb,yes,45,48 2006.173.13:53:05.41/va/02,06,usb,yes,45,46 2006.173.13:53:05.41/va/03,05,usb,yes,57,59 2006.173.13:53:05.41/va/04,06,usb,yes,46,48 2006.173.13:53:05.41/va/05,04,usb,yes,36,37 2006.173.13:53:05.41/va/06,03,usb,yes,50,50 2006.173.13:53:05.41/va/07,04,usb,yes,41,43 2006.173.13:53:05.41/va/08,04,usb,yes,35,42 2006.173.13:53:05.64/valo/01,524.99,yes,locked 2006.173.13:53:05.64/valo/02,534.99,yes,locked 2006.173.13:53:05.64/valo/03,564.99,yes,locked 2006.173.13:53:05.64/valo/04,624.99,yes,locked 2006.173.13:53:05.64/valo/05,734.99,yes,locked 2006.173.13:53:05.64/valo/06,814.99,yes,locked 2006.173.13:53:05.64/valo/07,864.99,yes,locked 2006.173.13:53:05.64/valo/08,884.99,yes,locked 2006.173.13:53:06.73/vb/01,04,usb,yes,30,28 2006.173.13:53:06.73/vb/02,04,usb,yes,32,32 2006.173.13:53:06.73/vb/03,04,usb,yes,29,32 2006.173.13:53:06.73/vb/04,04,usb,yes,34,32 2006.173.13:53:06.73/vb/05,04,usb,yes,26,29 2006.173.13:53:06.73/vb/06,04,usb,yes,31,27 2006.173.13:53:06.73/vb/07,04,usb,yes,30,30 2006.173.13:53:06.73/vb/08,04,usb,yes,28,31 2006.173.13:53:06.96/vblo/01,629.99,yes,locked 2006.173.13:53:06.96/vblo/02,634.99,yes,locked 2006.173.13:53:06.96/vblo/03,649.99,yes,locked 2006.173.13:53:06.96/vblo/04,679.99,yes,locked 2006.173.13:53:06.96/vblo/05,709.99,yes,locked 2006.173.13:53:06.96/vblo/06,719.99,yes,locked 2006.173.13:53:06.96/vblo/07,734.99,yes,locked 2006.173.13:53:06.96/vblo/08,744.99,yes,locked 2006.173.13:53:07.11/vabw/8 2006.173.13:53:07.26/vbbw/8 2006.173.13:53:07.35/xfe/off,on,14.5 2006.173.13:53:07.72/ifatt/23,28,28,28 2006.173.13:53:08.08/fmout-gps/S +3.91E-07 2006.173.13:53:08.12:!2006.173.13:54:24 2006.173.13:54:24.01:data_valid=off 2006.173.13:54:24.01:"et 2006.173.13:54:24.02:!+3s 2006.173.13:54:27.03:"tape 2006.173.13:54:27.03:postob 2006.173.13:54:27.17/cable/+6.5031E-03 2006.173.13:54:27.17/wx/21.83,1003.7,100 2006.173.13:54:27.23/fmout-gps/S +3.90E-07 2006.173.13:54:27.23:scan_name=173-1359,jd0606,40 2006.173.13:54:27.24:source=1921-293,192451.06,-291430.1,2000.0,cw 2006.173.13:54:28.13#flagr#flagr/antenna,new-source 2006.173.13:54:28.13:checkk5 2006.173.13:54:28.57/chk_autoobs//k5ts1/ autoobs is running! 2006.173.13:54:28.95/chk_autoobs//k5ts2/ autoobs is running! 2006.173.13:54:29.34/chk_autoobs//k5ts3/ autoobs is running! 2006.173.13:54:29.72/chk_autoobs//k5ts4/ autoobs is running! 2006.173.13:54:30.10/chk_obsdata//k5ts1/T1731353??a.dat file size is correct (nominal:320MB, actual:320MB). 2006.173.13:54:30.52/chk_obsdata//k5ts2/T1731353??b.dat file size is correct (nominal:320MB, actual:320MB). 2006.173.13:54:30.92/chk_obsdata//k5ts3/T1731353??c.dat file size is correct (nominal:320MB, actual:320MB). 2006.173.13:54:31.34/chk_obsdata//k5ts4/T1731353??d.dat file size is correct (nominal:320MB, actual:320MB). 2006.173.13:54:32.05/k5log//k5ts1_log_newline 2006.173.13:54:32.74/k5log//k5ts2_log_newline 2006.173.13:54:33.47/k5log//k5ts3_log_newline 2006.173.13:54:34.17/k5log//k5ts4_log_newline 2006.173.13:54:34.20/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.13:54:34.20:setupk4=1 2006.173.13:54:34.20$setupk4/echo=on 2006.173.13:54:34.20$setupk4/pcalon 2006.173.13:54:34.20$pcalon/"no phase cal control is implemented here 2006.173.13:54:34.20$setupk4/"tpicd=stop 2006.173.13:54:34.20$setupk4/"rec=synch_on 2006.173.13:54:34.20$setupk4/"rec_mode=128 2006.173.13:54:34.20$setupk4/!* 2006.173.13:54:34.20$setupk4/recpk4 2006.173.13:54:34.20$recpk4/recpatch= 2006.173.13:54:34.20$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.13:54:34.20$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.13:54:34.20$setupk4/vck44 2006.173.13:54:34.20$vck44/valo=1,524.99 2006.173.13:54:34.20#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.13:54:34.20#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.13:54:34.20#ibcon#ireg 17 cls_cnt 0 2006.173.13:54:34.20#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.13:54:34.20#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.13:54:34.20#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.13:54:34.20#ibcon#enter wrdev, iclass 39, count 0 2006.173.13:54:34.20#ibcon#first serial, iclass 39, count 0 2006.173.13:54:34.20#ibcon#enter sib2, iclass 39, count 0 2006.173.13:54:34.20#ibcon#flushed, iclass 39, count 0 2006.173.13:54:34.20#ibcon#about to write, iclass 39, count 0 2006.173.13:54:34.20#ibcon#wrote, iclass 39, count 0 2006.173.13:54:34.20#ibcon#about to read 3, iclass 39, count 0 2006.173.13:54:34.22#ibcon#read 3, iclass 39, count 0 2006.173.13:54:34.22#ibcon#about to read 4, iclass 39, count 0 2006.173.13:54:34.22#ibcon#read 4, iclass 39, count 0 2006.173.13:54:34.22#ibcon#about to read 5, iclass 39, count 0 2006.173.13:54:34.22#ibcon#read 5, iclass 39, count 0 2006.173.13:54:34.22#ibcon#about to read 6, iclass 39, count 0 2006.173.13:54:34.22#ibcon#read 6, iclass 39, count 0 2006.173.13:54:34.22#ibcon#end of sib2, iclass 39, count 0 2006.173.13:54:34.22#ibcon#*mode == 0, iclass 39, count 0 2006.173.13:54:34.22#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.13:54:34.22#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.13:54:34.22#ibcon#*before write, iclass 39, count 0 2006.173.13:54:34.22#ibcon#enter sib2, iclass 39, count 0 2006.173.13:54:34.22#ibcon#flushed, iclass 39, count 0 2006.173.13:54:34.22#ibcon#about to write, iclass 39, count 0 2006.173.13:54:34.22#ibcon#wrote, iclass 39, count 0 2006.173.13:54:34.22#ibcon#about to read 3, iclass 39, count 0 2006.173.13:54:34.27#ibcon#read 3, iclass 39, count 0 2006.173.13:54:34.27#ibcon#about to read 4, iclass 39, count 0 2006.173.13:54:34.27#ibcon#read 4, iclass 39, count 0 2006.173.13:54:34.27#ibcon#about to read 5, iclass 39, count 0 2006.173.13:54:34.27#ibcon#read 5, iclass 39, count 0 2006.173.13:54:34.27#ibcon#about to read 6, iclass 39, count 0 2006.173.13:54:34.27#ibcon#read 6, iclass 39, count 0 2006.173.13:54:34.27#ibcon#end of sib2, iclass 39, count 0 2006.173.13:54:34.27#ibcon#*after write, iclass 39, count 0 2006.173.13:54:34.27#ibcon#*before return 0, iclass 39, count 0 2006.173.13:54:34.27#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.13:54:34.27#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.13:54:34.27#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.13:54:34.27#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.13:54:34.27$vck44/va=1,7 2006.173.13:54:34.27#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.13:54:34.27#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.13:54:34.27#ibcon#ireg 11 cls_cnt 2 2006.173.13:54:34.27#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.13:54:34.27#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.13:54:34.27#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.13:54:34.27#ibcon#enter wrdev, iclass 3, count 2 2006.173.13:54:34.27#ibcon#first serial, iclass 3, count 2 2006.173.13:54:34.27#ibcon#enter sib2, iclass 3, count 2 2006.173.13:54:34.27#ibcon#flushed, iclass 3, count 2 2006.173.13:54:34.27#ibcon#about to write, iclass 3, count 2 2006.173.13:54:34.27#ibcon#wrote, iclass 3, count 2 2006.173.13:54:34.27#ibcon#about to read 3, iclass 3, count 2 2006.173.13:54:34.29#ibcon#read 3, iclass 3, count 2 2006.173.13:54:34.29#ibcon#about to read 4, iclass 3, count 2 2006.173.13:54:34.29#ibcon#read 4, iclass 3, count 2 2006.173.13:54:34.29#ibcon#about to read 5, iclass 3, count 2 2006.173.13:54:34.29#ibcon#read 5, iclass 3, count 2 2006.173.13:54:34.29#ibcon#about to read 6, iclass 3, count 2 2006.173.13:54:34.29#ibcon#read 6, iclass 3, count 2 2006.173.13:54:34.29#ibcon#end of sib2, iclass 3, count 2 2006.173.13:54:34.29#ibcon#*mode == 0, iclass 3, count 2 2006.173.13:54:34.29#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.13:54:34.29#ibcon#[25=AT01-07\r\n] 2006.173.13:54:34.29#ibcon#*before write, iclass 3, count 2 2006.173.13:54:34.29#ibcon#enter sib2, iclass 3, count 2 2006.173.13:54:34.29#ibcon#flushed, iclass 3, count 2 2006.173.13:54:34.29#ibcon#about to write, iclass 3, count 2 2006.173.13:54:34.29#ibcon#wrote, iclass 3, count 2 2006.173.13:54:34.29#ibcon#about to read 3, iclass 3, count 2 2006.173.13:54:34.32#ibcon#read 3, iclass 3, count 2 2006.173.13:54:34.32#ibcon#about to read 4, iclass 3, count 2 2006.173.13:54:34.32#ibcon#read 4, iclass 3, count 2 2006.173.13:54:34.32#ibcon#about to read 5, iclass 3, count 2 2006.173.13:54:34.32#ibcon#read 5, iclass 3, count 2 2006.173.13:54:34.32#ibcon#about to read 6, iclass 3, count 2 2006.173.13:54:34.32#ibcon#read 6, iclass 3, count 2 2006.173.13:54:34.32#ibcon#end of sib2, iclass 3, count 2 2006.173.13:54:34.32#ibcon#*after write, iclass 3, count 2 2006.173.13:54:34.32#ibcon#*before return 0, iclass 3, count 2 2006.173.13:54:34.32#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.13:54:34.32#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.13:54:34.32#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.13:54:34.32#ibcon#ireg 7 cls_cnt 0 2006.173.13:54:34.32#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.13:54:34.44#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.13:54:34.44#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.13:54:34.44#ibcon#enter wrdev, iclass 3, count 0 2006.173.13:54:34.44#ibcon#first serial, iclass 3, count 0 2006.173.13:54:34.44#ibcon#enter sib2, iclass 3, count 0 2006.173.13:54:34.44#ibcon#flushed, iclass 3, count 0 2006.173.13:54:34.44#ibcon#about to write, iclass 3, count 0 2006.173.13:54:34.44#ibcon#wrote, iclass 3, count 0 2006.173.13:54:34.44#ibcon#about to read 3, iclass 3, count 0 2006.173.13:54:34.46#ibcon#read 3, iclass 3, count 0 2006.173.13:54:34.46#ibcon#about to read 4, iclass 3, count 0 2006.173.13:54:34.46#ibcon#read 4, iclass 3, count 0 2006.173.13:54:34.46#ibcon#about to read 5, iclass 3, count 0 2006.173.13:54:34.46#ibcon#read 5, iclass 3, count 0 2006.173.13:54:34.46#ibcon#about to read 6, iclass 3, count 0 2006.173.13:54:34.46#ibcon#read 6, iclass 3, count 0 2006.173.13:54:34.46#ibcon#end of sib2, iclass 3, count 0 2006.173.13:54:34.46#ibcon#*mode == 0, iclass 3, count 0 2006.173.13:54:34.46#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.13:54:34.46#ibcon#[25=USB\r\n] 2006.173.13:54:34.46#ibcon#*before write, iclass 3, count 0 2006.173.13:54:34.46#ibcon#enter sib2, iclass 3, count 0 2006.173.13:54:34.46#ibcon#flushed, iclass 3, count 0 2006.173.13:54:34.46#ibcon#about to write, iclass 3, count 0 2006.173.13:54:34.46#ibcon#wrote, iclass 3, count 0 2006.173.13:54:34.46#ibcon#about to read 3, iclass 3, count 0 2006.173.13:54:34.49#ibcon#read 3, iclass 3, count 0 2006.173.13:54:34.49#ibcon#about to read 4, iclass 3, count 0 2006.173.13:54:34.49#ibcon#read 4, iclass 3, count 0 2006.173.13:54:34.49#ibcon#about to read 5, iclass 3, count 0 2006.173.13:54:34.49#ibcon#read 5, iclass 3, count 0 2006.173.13:54:34.49#ibcon#about to read 6, iclass 3, count 0 2006.173.13:54:34.49#ibcon#read 6, iclass 3, count 0 2006.173.13:54:34.49#ibcon#end of sib2, iclass 3, count 0 2006.173.13:54:34.49#ibcon#*after write, iclass 3, count 0 2006.173.13:54:34.49#ibcon#*before return 0, iclass 3, count 0 2006.173.13:54:34.49#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.13:54:34.49#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.13:54:34.49#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.13:54:34.49#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.13:54:34.49$vck44/valo=2,534.99 2006.173.13:54:34.49#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.13:54:34.49#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.13:54:34.49#ibcon#ireg 17 cls_cnt 0 2006.173.13:54:34.49#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.13:54:34.49#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.13:54:34.49#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.13:54:34.49#ibcon#enter wrdev, iclass 5, count 0 2006.173.13:54:34.49#ibcon#first serial, iclass 5, count 0 2006.173.13:54:34.49#ibcon#enter sib2, iclass 5, count 0 2006.173.13:54:34.49#ibcon#flushed, iclass 5, count 0 2006.173.13:54:34.49#ibcon#about to write, iclass 5, count 0 2006.173.13:54:34.49#ibcon#wrote, iclass 5, count 0 2006.173.13:54:34.49#ibcon#about to read 3, iclass 5, count 0 2006.173.13:54:34.51#ibcon#read 3, iclass 5, count 0 2006.173.13:54:34.51#ibcon#about to read 4, iclass 5, count 0 2006.173.13:54:34.51#ibcon#read 4, iclass 5, count 0 2006.173.13:54:34.51#ibcon#about to read 5, iclass 5, count 0 2006.173.13:54:34.51#ibcon#read 5, iclass 5, count 0 2006.173.13:54:34.51#ibcon#about to read 6, iclass 5, count 0 2006.173.13:54:34.51#ibcon#read 6, iclass 5, count 0 2006.173.13:54:34.51#ibcon#end of sib2, iclass 5, count 0 2006.173.13:54:34.51#ibcon#*mode == 0, iclass 5, count 0 2006.173.13:54:34.51#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.13:54:34.51#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.13:54:34.51#ibcon#*before write, iclass 5, count 0 2006.173.13:54:34.51#ibcon#enter sib2, iclass 5, count 0 2006.173.13:54:34.51#ibcon#flushed, iclass 5, count 0 2006.173.13:54:34.51#ibcon#about to write, iclass 5, count 0 2006.173.13:54:34.51#ibcon#wrote, iclass 5, count 0 2006.173.13:54:34.51#ibcon#about to read 3, iclass 5, count 0 2006.173.13:54:34.55#ibcon#read 3, iclass 5, count 0 2006.173.13:54:34.55#ibcon#about to read 4, iclass 5, count 0 2006.173.13:54:34.55#ibcon#read 4, iclass 5, count 0 2006.173.13:54:34.55#ibcon#about to read 5, iclass 5, count 0 2006.173.13:54:34.55#ibcon#read 5, iclass 5, count 0 2006.173.13:54:34.55#ibcon#about to read 6, iclass 5, count 0 2006.173.13:54:34.55#ibcon#read 6, iclass 5, count 0 2006.173.13:54:34.55#ibcon#end of sib2, iclass 5, count 0 2006.173.13:54:34.55#ibcon#*after write, iclass 5, count 0 2006.173.13:54:34.55#ibcon#*before return 0, iclass 5, count 0 2006.173.13:54:34.55#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.13:54:34.55#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.13:54:34.55#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.13:54:34.55#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.13:54:34.55$vck44/va=2,6 2006.173.13:54:34.55#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.173.13:54:34.55#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.173.13:54:34.55#ibcon#ireg 11 cls_cnt 2 2006.173.13:54:34.55#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.13:54:34.61#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.13:54:34.61#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.13:54:34.61#ibcon#enter wrdev, iclass 7, count 2 2006.173.13:54:34.61#ibcon#first serial, iclass 7, count 2 2006.173.13:54:34.61#ibcon#enter sib2, iclass 7, count 2 2006.173.13:54:34.61#ibcon#flushed, iclass 7, count 2 2006.173.13:54:34.61#ibcon#about to write, iclass 7, count 2 2006.173.13:54:34.61#ibcon#wrote, iclass 7, count 2 2006.173.13:54:34.61#ibcon#about to read 3, iclass 7, count 2 2006.173.13:54:34.63#ibcon#read 3, iclass 7, count 2 2006.173.13:54:34.63#ibcon#about to read 4, iclass 7, count 2 2006.173.13:54:34.63#ibcon#read 4, iclass 7, count 2 2006.173.13:54:34.63#ibcon#about to read 5, iclass 7, count 2 2006.173.13:54:34.63#ibcon#read 5, iclass 7, count 2 2006.173.13:54:34.63#ibcon#about to read 6, iclass 7, count 2 2006.173.13:54:34.63#ibcon#read 6, iclass 7, count 2 2006.173.13:54:34.63#ibcon#end of sib2, iclass 7, count 2 2006.173.13:54:34.63#ibcon#*mode == 0, iclass 7, count 2 2006.173.13:54:34.63#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.173.13:54:34.63#ibcon#[25=AT02-06\r\n] 2006.173.13:54:34.63#ibcon#*before write, iclass 7, count 2 2006.173.13:54:34.63#ibcon#enter sib2, iclass 7, count 2 2006.173.13:54:34.63#ibcon#flushed, iclass 7, count 2 2006.173.13:54:34.63#ibcon#about to write, iclass 7, count 2 2006.173.13:54:34.63#ibcon#wrote, iclass 7, count 2 2006.173.13:54:34.63#ibcon#about to read 3, iclass 7, count 2 2006.173.13:54:34.66#ibcon#read 3, iclass 7, count 2 2006.173.13:54:34.66#ibcon#about to read 4, iclass 7, count 2 2006.173.13:54:34.66#ibcon#read 4, iclass 7, count 2 2006.173.13:54:34.66#ibcon#about to read 5, iclass 7, count 2 2006.173.13:54:34.66#ibcon#read 5, iclass 7, count 2 2006.173.13:54:34.66#ibcon#about to read 6, iclass 7, count 2 2006.173.13:54:34.66#ibcon#read 6, iclass 7, count 2 2006.173.13:54:34.66#ibcon#end of sib2, iclass 7, count 2 2006.173.13:54:34.66#ibcon#*after write, iclass 7, count 2 2006.173.13:54:34.66#ibcon#*before return 0, iclass 7, count 2 2006.173.13:54:34.66#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.13:54:34.66#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.173.13:54:34.66#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.173.13:54:34.66#ibcon#ireg 7 cls_cnt 0 2006.173.13:54:34.66#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.13:54:34.78#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.13:54:34.78#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.13:54:34.78#ibcon#enter wrdev, iclass 7, count 0 2006.173.13:54:34.78#ibcon#first serial, iclass 7, count 0 2006.173.13:54:34.78#ibcon#enter sib2, iclass 7, count 0 2006.173.13:54:34.78#ibcon#flushed, iclass 7, count 0 2006.173.13:54:34.78#ibcon#about to write, iclass 7, count 0 2006.173.13:54:34.78#ibcon#wrote, iclass 7, count 0 2006.173.13:54:34.78#ibcon#about to read 3, iclass 7, count 0 2006.173.13:54:34.80#ibcon#read 3, iclass 7, count 0 2006.173.13:54:34.80#ibcon#about to read 4, iclass 7, count 0 2006.173.13:54:34.80#ibcon#read 4, iclass 7, count 0 2006.173.13:54:34.80#ibcon#about to read 5, iclass 7, count 0 2006.173.13:54:34.80#ibcon#read 5, iclass 7, count 0 2006.173.13:54:34.80#ibcon#about to read 6, iclass 7, count 0 2006.173.13:54:34.80#ibcon#read 6, iclass 7, count 0 2006.173.13:54:34.80#ibcon#end of sib2, iclass 7, count 0 2006.173.13:54:34.80#ibcon#*mode == 0, iclass 7, count 0 2006.173.13:54:34.80#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.13:54:34.80#ibcon#[25=USB\r\n] 2006.173.13:54:34.80#ibcon#*before write, iclass 7, count 0 2006.173.13:54:34.80#ibcon#enter sib2, iclass 7, count 0 2006.173.13:54:34.80#ibcon#flushed, iclass 7, count 0 2006.173.13:54:34.80#ibcon#about to write, iclass 7, count 0 2006.173.13:54:34.80#ibcon#wrote, iclass 7, count 0 2006.173.13:54:34.80#ibcon#about to read 3, iclass 7, count 0 2006.173.13:54:34.83#ibcon#read 3, iclass 7, count 0 2006.173.13:54:34.83#ibcon#about to read 4, iclass 7, count 0 2006.173.13:54:34.83#ibcon#read 4, iclass 7, count 0 2006.173.13:54:34.83#ibcon#about to read 5, iclass 7, count 0 2006.173.13:54:34.83#ibcon#read 5, iclass 7, count 0 2006.173.13:54:34.83#ibcon#about to read 6, iclass 7, count 0 2006.173.13:54:34.83#ibcon#read 6, iclass 7, count 0 2006.173.13:54:34.83#ibcon#end of sib2, iclass 7, count 0 2006.173.13:54:34.83#ibcon#*after write, iclass 7, count 0 2006.173.13:54:34.83#ibcon#*before return 0, iclass 7, count 0 2006.173.13:54:34.83#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.13:54:34.83#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.173.13:54:34.83#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.13:54:34.83#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.13:54:34.83$vck44/valo=3,564.99 2006.173.13:54:34.83#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.13:54:34.83#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.13:54:34.83#ibcon#ireg 17 cls_cnt 0 2006.173.13:54:34.83#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.13:54:34.83#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.13:54:34.83#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.13:54:34.83#ibcon#enter wrdev, iclass 11, count 0 2006.173.13:54:34.83#ibcon#first serial, iclass 11, count 0 2006.173.13:54:34.83#ibcon#enter sib2, iclass 11, count 0 2006.173.13:54:34.83#ibcon#flushed, iclass 11, count 0 2006.173.13:54:34.83#ibcon#about to write, iclass 11, count 0 2006.173.13:54:34.83#ibcon#wrote, iclass 11, count 0 2006.173.13:54:34.83#ibcon#about to read 3, iclass 11, count 0 2006.173.13:54:34.85#ibcon#read 3, iclass 11, count 0 2006.173.13:54:34.85#ibcon#about to read 4, iclass 11, count 0 2006.173.13:54:34.85#ibcon#read 4, iclass 11, count 0 2006.173.13:54:34.85#ibcon#about to read 5, iclass 11, count 0 2006.173.13:54:34.85#ibcon#read 5, iclass 11, count 0 2006.173.13:54:34.85#ibcon#about to read 6, iclass 11, count 0 2006.173.13:54:34.85#ibcon#read 6, iclass 11, count 0 2006.173.13:54:34.85#ibcon#end of sib2, iclass 11, count 0 2006.173.13:54:34.85#ibcon#*mode == 0, iclass 11, count 0 2006.173.13:54:34.85#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.13:54:34.85#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.13:54:34.85#ibcon#*before write, iclass 11, count 0 2006.173.13:54:34.85#ibcon#enter sib2, iclass 11, count 0 2006.173.13:54:34.85#ibcon#flushed, iclass 11, count 0 2006.173.13:54:34.85#ibcon#about to write, iclass 11, count 0 2006.173.13:54:34.85#ibcon#wrote, iclass 11, count 0 2006.173.13:54:34.85#ibcon#about to read 3, iclass 11, count 0 2006.173.13:54:34.89#ibcon#read 3, iclass 11, count 0 2006.173.13:54:34.89#ibcon#about to read 4, iclass 11, count 0 2006.173.13:54:34.89#ibcon#read 4, iclass 11, count 0 2006.173.13:54:34.89#ibcon#about to read 5, iclass 11, count 0 2006.173.13:54:34.89#ibcon#read 5, iclass 11, count 0 2006.173.13:54:34.89#ibcon#about to read 6, iclass 11, count 0 2006.173.13:54:34.89#ibcon#read 6, iclass 11, count 0 2006.173.13:54:34.89#ibcon#end of sib2, iclass 11, count 0 2006.173.13:54:34.89#ibcon#*after write, iclass 11, count 0 2006.173.13:54:34.89#ibcon#*before return 0, iclass 11, count 0 2006.173.13:54:34.89#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.13:54:34.89#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.13:54:34.89#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.13:54:34.89#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.13:54:34.89$vck44/va=3,5 2006.173.13:54:34.89#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.173.13:54:34.89#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.173.13:54:34.89#ibcon#ireg 11 cls_cnt 2 2006.173.13:54:34.89#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.13:54:34.95#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.13:54:34.95#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.13:54:34.95#ibcon#enter wrdev, iclass 13, count 2 2006.173.13:54:34.95#ibcon#first serial, iclass 13, count 2 2006.173.13:54:34.95#ibcon#enter sib2, iclass 13, count 2 2006.173.13:54:34.95#ibcon#flushed, iclass 13, count 2 2006.173.13:54:34.95#ibcon#about to write, iclass 13, count 2 2006.173.13:54:34.95#ibcon#wrote, iclass 13, count 2 2006.173.13:54:34.95#ibcon#about to read 3, iclass 13, count 2 2006.173.13:54:34.97#ibcon#read 3, iclass 13, count 2 2006.173.13:54:34.97#ibcon#about to read 4, iclass 13, count 2 2006.173.13:54:34.97#ibcon#read 4, iclass 13, count 2 2006.173.13:54:34.97#ibcon#about to read 5, iclass 13, count 2 2006.173.13:54:34.97#ibcon#read 5, iclass 13, count 2 2006.173.13:54:34.97#ibcon#about to read 6, iclass 13, count 2 2006.173.13:54:34.97#ibcon#read 6, iclass 13, count 2 2006.173.13:54:34.97#ibcon#end of sib2, iclass 13, count 2 2006.173.13:54:34.97#ibcon#*mode == 0, iclass 13, count 2 2006.173.13:54:34.97#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.173.13:54:34.97#ibcon#[25=AT03-05\r\n] 2006.173.13:54:34.97#ibcon#*before write, iclass 13, count 2 2006.173.13:54:34.97#ibcon#enter sib2, iclass 13, count 2 2006.173.13:54:34.97#ibcon#flushed, iclass 13, count 2 2006.173.13:54:34.97#ibcon#about to write, iclass 13, count 2 2006.173.13:54:34.97#ibcon#wrote, iclass 13, count 2 2006.173.13:54:34.97#ibcon#about to read 3, iclass 13, count 2 2006.173.13:54:35.00#ibcon#read 3, iclass 13, count 2 2006.173.13:54:35.00#ibcon#about to read 4, iclass 13, count 2 2006.173.13:54:35.00#ibcon#read 4, iclass 13, count 2 2006.173.13:54:35.00#ibcon#about to read 5, iclass 13, count 2 2006.173.13:54:35.00#ibcon#read 5, iclass 13, count 2 2006.173.13:54:35.00#ibcon#about to read 6, iclass 13, count 2 2006.173.13:54:35.00#ibcon#read 6, iclass 13, count 2 2006.173.13:54:35.00#ibcon#end of sib2, iclass 13, count 2 2006.173.13:54:35.00#ibcon#*after write, iclass 13, count 2 2006.173.13:54:35.00#ibcon#*before return 0, iclass 13, count 2 2006.173.13:54:35.00#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.13:54:35.00#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.173.13:54:35.00#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.173.13:54:35.00#ibcon#ireg 7 cls_cnt 0 2006.173.13:54:35.00#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.13:54:35.12#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.13:54:35.12#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.13:54:35.12#ibcon#enter wrdev, iclass 13, count 0 2006.173.13:54:35.12#ibcon#first serial, iclass 13, count 0 2006.173.13:54:35.12#ibcon#enter sib2, iclass 13, count 0 2006.173.13:54:35.12#ibcon#flushed, iclass 13, count 0 2006.173.13:54:35.12#ibcon#about to write, iclass 13, count 0 2006.173.13:54:35.12#ibcon#wrote, iclass 13, count 0 2006.173.13:54:35.12#ibcon#about to read 3, iclass 13, count 0 2006.173.13:54:35.14#ibcon#read 3, iclass 13, count 0 2006.173.13:54:35.14#ibcon#about to read 4, iclass 13, count 0 2006.173.13:54:35.14#ibcon#read 4, iclass 13, count 0 2006.173.13:54:35.14#ibcon#about to read 5, iclass 13, count 0 2006.173.13:54:35.14#ibcon#read 5, iclass 13, count 0 2006.173.13:54:35.14#ibcon#about to read 6, iclass 13, count 0 2006.173.13:54:35.14#ibcon#read 6, iclass 13, count 0 2006.173.13:54:35.14#ibcon#end of sib2, iclass 13, count 0 2006.173.13:54:35.14#ibcon#*mode == 0, iclass 13, count 0 2006.173.13:54:35.14#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.13:54:35.14#ibcon#[25=USB\r\n] 2006.173.13:54:35.14#ibcon#*before write, iclass 13, count 0 2006.173.13:54:35.14#ibcon#enter sib2, iclass 13, count 0 2006.173.13:54:35.14#ibcon#flushed, iclass 13, count 0 2006.173.13:54:35.14#ibcon#about to write, iclass 13, count 0 2006.173.13:54:35.14#ibcon#wrote, iclass 13, count 0 2006.173.13:54:35.14#ibcon#about to read 3, iclass 13, count 0 2006.173.13:54:35.17#ibcon#read 3, iclass 13, count 0 2006.173.13:54:35.17#ibcon#about to read 4, iclass 13, count 0 2006.173.13:54:35.17#ibcon#read 4, iclass 13, count 0 2006.173.13:54:35.17#ibcon#about to read 5, iclass 13, count 0 2006.173.13:54:35.17#ibcon#read 5, iclass 13, count 0 2006.173.13:54:35.17#ibcon#about to read 6, iclass 13, count 0 2006.173.13:54:35.17#ibcon#read 6, iclass 13, count 0 2006.173.13:54:35.17#ibcon#end of sib2, iclass 13, count 0 2006.173.13:54:35.17#ibcon#*after write, iclass 13, count 0 2006.173.13:54:35.17#ibcon#*before return 0, iclass 13, count 0 2006.173.13:54:35.17#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.13:54:35.17#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.173.13:54:35.17#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.13:54:35.17#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.13:54:35.17$vck44/valo=4,624.99 2006.173.13:54:35.17#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.13:54:35.17#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.13:54:35.17#ibcon#ireg 17 cls_cnt 0 2006.173.13:54:35.17#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.13:54:35.17#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.13:54:35.17#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.13:54:35.17#ibcon#enter wrdev, iclass 15, count 0 2006.173.13:54:35.17#ibcon#first serial, iclass 15, count 0 2006.173.13:54:35.17#ibcon#enter sib2, iclass 15, count 0 2006.173.13:54:35.17#ibcon#flushed, iclass 15, count 0 2006.173.13:54:35.17#ibcon#about to write, iclass 15, count 0 2006.173.13:54:35.17#ibcon#wrote, iclass 15, count 0 2006.173.13:54:35.17#ibcon#about to read 3, iclass 15, count 0 2006.173.13:54:35.19#ibcon#read 3, iclass 15, count 0 2006.173.13:54:35.19#ibcon#about to read 4, iclass 15, count 0 2006.173.13:54:35.19#ibcon#read 4, iclass 15, count 0 2006.173.13:54:35.19#ibcon#about to read 5, iclass 15, count 0 2006.173.13:54:35.19#ibcon#read 5, iclass 15, count 0 2006.173.13:54:35.19#ibcon#about to read 6, iclass 15, count 0 2006.173.13:54:35.19#ibcon#read 6, iclass 15, count 0 2006.173.13:54:35.19#ibcon#end of sib2, iclass 15, count 0 2006.173.13:54:35.19#ibcon#*mode == 0, iclass 15, count 0 2006.173.13:54:35.19#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.13:54:35.19#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.13:54:35.19#ibcon#*before write, iclass 15, count 0 2006.173.13:54:35.19#ibcon#enter sib2, iclass 15, count 0 2006.173.13:54:35.19#ibcon#flushed, iclass 15, count 0 2006.173.13:54:35.19#ibcon#about to write, iclass 15, count 0 2006.173.13:54:35.19#ibcon#wrote, iclass 15, count 0 2006.173.13:54:35.19#ibcon#about to read 3, iclass 15, count 0 2006.173.13:54:35.23#ibcon#read 3, iclass 15, count 0 2006.173.13:54:35.23#ibcon#about to read 4, iclass 15, count 0 2006.173.13:54:35.23#ibcon#read 4, iclass 15, count 0 2006.173.13:54:35.23#ibcon#about to read 5, iclass 15, count 0 2006.173.13:54:35.23#ibcon#read 5, iclass 15, count 0 2006.173.13:54:35.23#ibcon#about to read 6, iclass 15, count 0 2006.173.13:54:35.23#ibcon#read 6, iclass 15, count 0 2006.173.13:54:35.23#ibcon#end of sib2, iclass 15, count 0 2006.173.13:54:35.23#ibcon#*after write, iclass 15, count 0 2006.173.13:54:35.23#ibcon#*before return 0, iclass 15, count 0 2006.173.13:54:35.23#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.13:54:35.23#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.13:54:35.23#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.13:54:35.23#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.13:54:35.23$vck44/va=4,6 2006.173.13:54:35.23#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.13:54:35.23#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.13:54:35.23#ibcon#ireg 11 cls_cnt 2 2006.173.13:54:35.23#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.13:54:35.29#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.13:54:35.29#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.13:54:35.29#ibcon#enter wrdev, iclass 17, count 2 2006.173.13:54:35.29#ibcon#first serial, iclass 17, count 2 2006.173.13:54:35.29#ibcon#enter sib2, iclass 17, count 2 2006.173.13:54:35.29#ibcon#flushed, iclass 17, count 2 2006.173.13:54:35.29#ibcon#about to write, iclass 17, count 2 2006.173.13:54:35.29#ibcon#wrote, iclass 17, count 2 2006.173.13:54:35.29#ibcon#about to read 3, iclass 17, count 2 2006.173.13:54:35.31#ibcon#read 3, iclass 17, count 2 2006.173.13:54:35.31#ibcon#about to read 4, iclass 17, count 2 2006.173.13:54:35.31#ibcon#read 4, iclass 17, count 2 2006.173.13:54:35.31#ibcon#about to read 5, iclass 17, count 2 2006.173.13:54:35.31#ibcon#read 5, iclass 17, count 2 2006.173.13:54:35.31#ibcon#about to read 6, iclass 17, count 2 2006.173.13:54:35.31#ibcon#read 6, iclass 17, count 2 2006.173.13:54:35.31#ibcon#end of sib2, iclass 17, count 2 2006.173.13:54:35.31#ibcon#*mode == 0, iclass 17, count 2 2006.173.13:54:35.31#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.13:54:35.31#ibcon#[25=AT04-06\r\n] 2006.173.13:54:35.31#ibcon#*before write, iclass 17, count 2 2006.173.13:54:35.31#ibcon#enter sib2, iclass 17, count 2 2006.173.13:54:35.31#ibcon#flushed, iclass 17, count 2 2006.173.13:54:35.31#ibcon#about to write, iclass 17, count 2 2006.173.13:54:35.31#ibcon#wrote, iclass 17, count 2 2006.173.13:54:35.31#ibcon#about to read 3, iclass 17, count 2 2006.173.13:54:35.34#ibcon#read 3, iclass 17, count 2 2006.173.13:54:35.34#ibcon#about to read 4, iclass 17, count 2 2006.173.13:54:35.34#ibcon#read 4, iclass 17, count 2 2006.173.13:54:35.34#ibcon#about to read 5, iclass 17, count 2 2006.173.13:54:35.34#ibcon#read 5, iclass 17, count 2 2006.173.13:54:35.34#ibcon#about to read 6, iclass 17, count 2 2006.173.13:54:35.34#ibcon#read 6, iclass 17, count 2 2006.173.13:54:35.34#ibcon#end of sib2, iclass 17, count 2 2006.173.13:54:35.34#ibcon#*after write, iclass 17, count 2 2006.173.13:54:35.34#ibcon#*before return 0, iclass 17, count 2 2006.173.13:54:35.34#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.13:54:35.34#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.13:54:35.34#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.13:54:35.34#ibcon#ireg 7 cls_cnt 0 2006.173.13:54:35.34#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.13:54:35.46#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.13:54:35.46#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.13:54:35.46#ibcon#enter wrdev, iclass 17, count 0 2006.173.13:54:35.46#ibcon#first serial, iclass 17, count 0 2006.173.13:54:35.46#ibcon#enter sib2, iclass 17, count 0 2006.173.13:54:35.46#ibcon#flushed, iclass 17, count 0 2006.173.13:54:35.46#ibcon#about to write, iclass 17, count 0 2006.173.13:54:35.46#ibcon#wrote, iclass 17, count 0 2006.173.13:54:35.46#ibcon#about to read 3, iclass 17, count 0 2006.173.13:54:35.48#ibcon#read 3, iclass 17, count 0 2006.173.13:54:35.48#ibcon#about to read 4, iclass 17, count 0 2006.173.13:54:35.48#ibcon#read 4, iclass 17, count 0 2006.173.13:54:35.48#ibcon#about to read 5, iclass 17, count 0 2006.173.13:54:35.48#ibcon#read 5, iclass 17, count 0 2006.173.13:54:35.48#ibcon#about to read 6, iclass 17, count 0 2006.173.13:54:35.48#ibcon#read 6, iclass 17, count 0 2006.173.13:54:35.48#ibcon#end of sib2, iclass 17, count 0 2006.173.13:54:35.48#ibcon#*mode == 0, iclass 17, count 0 2006.173.13:54:35.48#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.13:54:35.48#ibcon#[25=USB\r\n] 2006.173.13:54:35.48#ibcon#*before write, iclass 17, count 0 2006.173.13:54:35.48#ibcon#enter sib2, iclass 17, count 0 2006.173.13:54:35.48#ibcon#flushed, iclass 17, count 0 2006.173.13:54:35.48#ibcon#about to write, iclass 17, count 0 2006.173.13:54:35.48#ibcon#wrote, iclass 17, count 0 2006.173.13:54:35.48#ibcon#about to read 3, iclass 17, count 0 2006.173.13:54:35.51#ibcon#read 3, iclass 17, count 0 2006.173.13:54:35.51#ibcon#about to read 4, iclass 17, count 0 2006.173.13:54:35.51#ibcon#read 4, iclass 17, count 0 2006.173.13:54:35.51#ibcon#about to read 5, iclass 17, count 0 2006.173.13:54:35.51#ibcon#read 5, iclass 17, count 0 2006.173.13:54:35.51#ibcon#about to read 6, iclass 17, count 0 2006.173.13:54:35.51#ibcon#read 6, iclass 17, count 0 2006.173.13:54:35.51#ibcon#end of sib2, iclass 17, count 0 2006.173.13:54:35.51#ibcon#*after write, iclass 17, count 0 2006.173.13:54:35.51#ibcon#*before return 0, iclass 17, count 0 2006.173.13:54:35.51#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.13:54:35.51#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.13:54:35.51#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.13:54:35.51#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.13:54:35.51$vck44/valo=5,734.99 2006.173.13:54:35.51#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.13:54:35.51#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.13:54:35.51#ibcon#ireg 17 cls_cnt 0 2006.173.13:54:35.51#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.13:54:35.51#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.13:54:35.51#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.13:54:35.51#ibcon#enter wrdev, iclass 19, count 0 2006.173.13:54:35.51#ibcon#first serial, iclass 19, count 0 2006.173.13:54:35.51#ibcon#enter sib2, iclass 19, count 0 2006.173.13:54:35.51#ibcon#flushed, iclass 19, count 0 2006.173.13:54:35.51#ibcon#about to write, iclass 19, count 0 2006.173.13:54:35.51#ibcon#wrote, iclass 19, count 0 2006.173.13:54:35.51#ibcon#about to read 3, iclass 19, count 0 2006.173.13:54:35.53#ibcon#read 3, iclass 19, count 0 2006.173.13:54:35.53#ibcon#about to read 4, iclass 19, count 0 2006.173.13:54:35.53#ibcon#read 4, iclass 19, count 0 2006.173.13:54:35.53#ibcon#about to read 5, iclass 19, count 0 2006.173.13:54:35.53#ibcon#read 5, iclass 19, count 0 2006.173.13:54:35.53#ibcon#about to read 6, iclass 19, count 0 2006.173.13:54:35.53#ibcon#read 6, iclass 19, count 0 2006.173.13:54:35.53#ibcon#end of sib2, iclass 19, count 0 2006.173.13:54:35.53#ibcon#*mode == 0, iclass 19, count 0 2006.173.13:54:35.53#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.13:54:35.53#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.13:54:35.53#ibcon#*before write, iclass 19, count 0 2006.173.13:54:35.53#ibcon#enter sib2, iclass 19, count 0 2006.173.13:54:35.53#ibcon#flushed, iclass 19, count 0 2006.173.13:54:35.53#ibcon#about to write, iclass 19, count 0 2006.173.13:54:35.53#ibcon#wrote, iclass 19, count 0 2006.173.13:54:35.53#ibcon#about to read 3, iclass 19, count 0 2006.173.13:54:35.57#ibcon#read 3, iclass 19, count 0 2006.173.13:54:35.57#ibcon#about to read 4, iclass 19, count 0 2006.173.13:54:35.57#ibcon#read 4, iclass 19, count 0 2006.173.13:54:35.57#ibcon#about to read 5, iclass 19, count 0 2006.173.13:54:35.57#ibcon#read 5, iclass 19, count 0 2006.173.13:54:35.57#ibcon#about to read 6, iclass 19, count 0 2006.173.13:54:35.57#ibcon#read 6, iclass 19, count 0 2006.173.13:54:35.57#ibcon#end of sib2, iclass 19, count 0 2006.173.13:54:35.57#ibcon#*after write, iclass 19, count 0 2006.173.13:54:35.57#ibcon#*before return 0, iclass 19, count 0 2006.173.13:54:35.57#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.13:54:35.57#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.13:54:35.57#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.13:54:35.57#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.13:54:35.57$vck44/va=5,4 2006.173.13:54:35.57#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.13:54:35.57#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.13:54:35.57#ibcon#ireg 11 cls_cnt 2 2006.173.13:54:35.57#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.13:54:35.63#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.13:54:35.63#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.13:54:35.63#ibcon#enter wrdev, iclass 21, count 2 2006.173.13:54:35.63#ibcon#first serial, iclass 21, count 2 2006.173.13:54:35.63#ibcon#enter sib2, iclass 21, count 2 2006.173.13:54:35.63#ibcon#flushed, iclass 21, count 2 2006.173.13:54:35.63#ibcon#about to write, iclass 21, count 2 2006.173.13:54:35.63#ibcon#wrote, iclass 21, count 2 2006.173.13:54:35.63#ibcon#about to read 3, iclass 21, count 2 2006.173.13:54:35.65#ibcon#read 3, iclass 21, count 2 2006.173.13:54:35.65#ibcon#about to read 4, iclass 21, count 2 2006.173.13:54:35.65#ibcon#read 4, iclass 21, count 2 2006.173.13:54:35.65#ibcon#about to read 5, iclass 21, count 2 2006.173.13:54:35.65#ibcon#read 5, iclass 21, count 2 2006.173.13:54:35.65#ibcon#about to read 6, iclass 21, count 2 2006.173.13:54:35.65#ibcon#read 6, iclass 21, count 2 2006.173.13:54:35.65#ibcon#end of sib2, iclass 21, count 2 2006.173.13:54:35.65#ibcon#*mode == 0, iclass 21, count 2 2006.173.13:54:35.65#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.13:54:35.65#ibcon#[25=AT05-04\r\n] 2006.173.13:54:35.65#ibcon#*before write, iclass 21, count 2 2006.173.13:54:35.65#ibcon#enter sib2, iclass 21, count 2 2006.173.13:54:35.65#ibcon#flushed, iclass 21, count 2 2006.173.13:54:35.65#ibcon#about to write, iclass 21, count 2 2006.173.13:54:35.65#ibcon#wrote, iclass 21, count 2 2006.173.13:54:35.65#ibcon#about to read 3, iclass 21, count 2 2006.173.13:54:35.68#ibcon#read 3, iclass 21, count 2 2006.173.13:54:35.68#ibcon#about to read 4, iclass 21, count 2 2006.173.13:54:35.68#ibcon#read 4, iclass 21, count 2 2006.173.13:54:35.68#ibcon#about to read 5, iclass 21, count 2 2006.173.13:54:35.68#ibcon#read 5, iclass 21, count 2 2006.173.13:54:35.68#ibcon#about to read 6, iclass 21, count 2 2006.173.13:54:35.68#ibcon#read 6, iclass 21, count 2 2006.173.13:54:35.68#ibcon#end of sib2, iclass 21, count 2 2006.173.13:54:35.68#ibcon#*after write, iclass 21, count 2 2006.173.13:54:35.68#ibcon#*before return 0, iclass 21, count 2 2006.173.13:54:35.68#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.13:54:35.68#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.13:54:35.68#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.13:54:35.68#ibcon#ireg 7 cls_cnt 0 2006.173.13:54:35.68#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.13:54:35.80#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.13:54:35.80#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.13:54:35.80#ibcon#enter wrdev, iclass 21, count 0 2006.173.13:54:35.80#ibcon#first serial, iclass 21, count 0 2006.173.13:54:35.80#ibcon#enter sib2, iclass 21, count 0 2006.173.13:54:35.80#ibcon#flushed, iclass 21, count 0 2006.173.13:54:35.80#ibcon#about to write, iclass 21, count 0 2006.173.13:54:35.80#ibcon#wrote, iclass 21, count 0 2006.173.13:54:35.80#ibcon#about to read 3, iclass 21, count 0 2006.173.13:54:35.82#ibcon#read 3, iclass 21, count 0 2006.173.13:54:35.82#ibcon#about to read 4, iclass 21, count 0 2006.173.13:54:35.82#ibcon#read 4, iclass 21, count 0 2006.173.13:54:35.82#ibcon#about to read 5, iclass 21, count 0 2006.173.13:54:35.82#ibcon#read 5, iclass 21, count 0 2006.173.13:54:35.82#ibcon#about to read 6, iclass 21, count 0 2006.173.13:54:35.82#ibcon#read 6, iclass 21, count 0 2006.173.13:54:35.82#ibcon#end of sib2, iclass 21, count 0 2006.173.13:54:35.82#ibcon#*mode == 0, iclass 21, count 0 2006.173.13:54:35.82#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.13:54:35.82#ibcon#[25=USB\r\n] 2006.173.13:54:35.82#ibcon#*before write, iclass 21, count 0 2006.173.13:54:35.82#ibcon#enter sib2, iclass 21, count 0 2006.173.13:54:35.82#ibcon#flushed, iclass 21, count 0 2006.173.13:54:35.82#ibcon#about to write, iclass 21, count 0 2006.173.13:54:35.82#ibcon#wrote, iclass 21, count 0 2006.173.13:54:35.82#ibcon#about to read 3, iclass 21, count 0 2006.173.13:54:35.85#ibcon#read 3, iclass 21, count 0 2006.173.13:54:35.85#ibcon#about to read 4, iclass 21, count 0 2006.173.13:54:35.85#ibcon#read 4, iclass 21, count 0 2006.173.13:54:35.85#ibcon#about to read 5, iclass 21, count 0 2006.173.13:54:35.85#ibcon#read 5, iclass 21, count 0 2006.173.13:54:35.85#ibcon#about to read 6, iclass 21, count 0 2006.173.13:54:35.85#ibcon#read 6, iclass 21, count 0 2006.173.13:54:35.85#ibcon#end of sib2, iclass 21, count 0 2006.173.13:54:35.85#ibcon#*after write, iclass 21, count 0 2006.173.13:54:35.85#ibcon#*before return 0, iclass 21, count 0 2006.173.13:54:35.85#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.13:54:35.85#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.13:54:35.85#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.13:54:35.85#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.13:54:35.85$vck44/valo=6,814.99 2006.173.13:54:35.85#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.13:54:35.85#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.13:54:35.85#ibcon#ireg 17 cls_cnt 0 2006.173.13:54:35.85#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.13:54:35.85#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.13:54:35.85#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.13:54:35.85#ibcon#enter wrdev, iclass 23, count 0 2006.173.13:54:35.85#ibcon#first serial, iclass 23, count 0 2006.173.13:54:35.85#ibcon#enter sib2, iclass 23, count 0 2006.173.13:54:35.85#ibcon#flushed, iclass 23, count 0 2006.173.13:54:35.85#ibcon#about to write, iclass 23, count 0 2006.173.13:54:35.85#ibcon#wrote, iclass 23, count 0 2006.173.13:54:35.85#ibcon#about to read 3, iclass 23, count 0 2006.173.13:54:35.87#ibcon#read 3, iclass 23, count 0 2006.173.13:54:35.87#ibcon#about to read 4, iclass 23, count 0 2006.173.13:54:35.87#ibcon#read 4, iclass 23, count 0 2006.173.13:54:35.87#ibcon#about to read 5, iclass 23, count 0 2006.173.13:54:35.87#ibcon#read 5, iclass 23, count 0 2006.173.13:54:35.87#ibcon#about to read 6, iclass 23, count 0 2006.173.13:54:35.87#ibcon#read 6, iclass 23, count 0 2006.173.13:54:35.87#ibcon#end of sib2, iclass 23, count 0 2006.173.13:54:35.87#ibcon#*mode == 0, iclass 23, count 0 2006.173.13:54:35.87#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.13:54:35.87#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.13:54:35.87#ibcon#*before write, iclass 23, count 0 2006.173.13:54:35.87#ibcon#enter sib2, iclass 23, count 0 2006.173.13:54:35.87#ibcon#flushed, iclass 23, count 0 2006.173.13:54:35.87#ibcon#about to write, iclass 23, count 0 2006.173.13:54:35.87#ibcon#wrote, iclass 23, count 0 2006.173.13:54:35.87#ibcon#about to read 3, iclass 23, count 0 2006.173.13:54:35.91#ibcon#read 3, iclass 23, count 0 2006.173.13:54:35.91#ibcon#about to read 4, iclass 23, count 0 2006.173.13:54:35.91#ibcon#read 4, iclass 23, count 0 2006.173.13:54:35.91#ibcon#about to read 5, iclass 23, count 0 2006.173.13:54:35.91#ibcon#read 5, iclass 23, count 0 2006.173.13:54:35.91#ibcon#about to read 6, iclass 23, count 0 2006.173.13:54:35.91#ibcon#read 6, iclass 23, count 0 2006.173.13:54:35.91#ibcon#end of sib2, iclass 23, count 0 2006.173.13:54:35.91#ibcon#*after write, iclass 23, count 0 2006.173.13:54:35.91#ibcon#*before return 0, iclass 23, count 0 2006.173.13:54:35.91#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.13:54:35.91#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.13:54:35.91#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.13:54:35.91#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.13:54:35.91$vck44/va=6,3 2006.173.13:54:35.91#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.13:54:35.91#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.13:54:35.91#ibcon#ireg 11 cls_cnt 2 2006.173.13:54:35.91#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.13:54:35.97#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.13:54:35.97#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.13:54:35.97#ibcon#enter wrdev, iclass 25, count 2 2006.173.13:54:35.97#ibcon#first serial, iclass 25, count 2 2006.173.13:54:35.97#ibcon#enter sib2, iclass 25, count 2 2006.173.13:54:35.97#ibcon#flushed, iclass 25, count 2 2006.173.13:54:35.97#ibcon#about to write, iclass 25, count 2 2006.173.13:54:35.97#ibcon#wrote, iclass 25, count 2 2006.173.13:54:35.97#ibcon#about to read 3, iclass 25, count 2 2006.173.13:54:35.99#ibcon#read 3, iclass 25, count 2 2006.173.13:54:35.99#ibcon#about to read 4, iclass 25, count 2 2006.173.13:54:35.99#ibcon#read 4, iclass 25, count 2 2006.173.13:54:35.99#ibcon#about to read 5, iclass 25, count 2 2006.173.13:54:35.99#ibcon#read 5, iclass 25, count 2 2006.173.13:54:35.99#ibcon#about to read 6, iclass 25, count 2 2006.173.13:54:35.99#ibcon#read 6, iclass 25, count 2 2006.173.13:54:35.99#ibcon#end of sib2, iclass 25, count 2 2006.173.13:54:35.99#ibcon#*mode == 0, iclass 25, count 2 2006.173.13:54:35.99#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.13:54:35.99#ibcon#[25=AT06-03\r\n] 2006.173.13:54:35.99#ibcon#*before write, iclass 25, count 2 2006.173.13:54:35.99#ibcon#enter sib2, iclass 25, count 2 2006.173.13:54:35.99#ibcon#flushed, iclass 25, count 2 2006.173.13:54:35.99#ibcon#about to write, iclass 25, count 2 2006.173.13:54:35.99#ibcon#wrote, iclass 25, count 2 2006.173.13:54:35.99#ibcon#about to read 3, iclass 25, count 2 2006.173.13:54:36.02#ibcon#read 3, iclass 25, count 2 2006.173.13:54:36.02#ibcon#about to read 4, iclass 25, count 2 2006.173.13:54:36.02#ibcon#read 4, iclass 25, count 2 2006.173.13:54:36.02#ibcon#about to read 5, iclass 25, count 2 2006.173.13:54:36.02#ibcon#read 5, iclass 25, count 2 2006.173.13:54:36.02#ibcon#about to read 6, iclass 25, count 2 2006.173.13:54:36.02#ibcon#read 6, iclass 25, count 2 2006.173.13:54:36.02#ibcon#end of sib2, iclass 25, count 2 2006.173.13:54:36.02#ibcon#*after write, iclass 25, count 2 2006.173.13:54:36.02#ibcon#*before return 0, iclass 25, count 2 2006.173.13:54:36.02#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.13:54:36.02#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.13:54:36.02#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.13:54:36.02#ibcon#ireg 7 cls_cnt 0 2006.173.13:54:36.02#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.13:54:36.14#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.13:54:36.14#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.13:54:36.14#ibcon#enter wrdev, iclass 25, count 0 2006.173.13:54:36.14#ibcon#first serial, iclass 25, count 0 2006.173.13:54:36.14#ibcon#enter sib2, iclass 25, count 0 2006.173.13:54:36.14#ibcon#flushed, iclass 25, count 0 2006.173.13:54:36.14#ibcon#about to write, iclass 25, count 0 2006.173.13:54:36.14#ibcon#wrote, iclass 25, count 0 2006.173.13:54:36.14#ibcon#about to read 3, iclass 25, count 0 2006.173.13:54:36.16#ibcon#read 3, iclass 25, count 0 2006.173.13:54:36.16#ibcon#about to read 4, iclass 25, count 0 2006.173.13:54:36.16#ibcon#read 4, iclass 25, count 0 2006.173.13:54:36.16#ibcon#about to read 5, iclass 25, count 0 2006.173.13:54:36.16#ibcon#read 5, iclass 25, count 0 2006.173.13:54:36.16#ibcon#about to read 6, iclass 25, count 0 2006.173.13:54:36.16#ibcon#read 6, iclass 25, count 0 2006.173.13:54:36.16#ibcon#end of sib2, iclass 25, count 0 2006.173.13:54:36.16#ibcon#*mode == 0, iclass 25, count 0 2006.173.13:54:36.16#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.13:54:36.16#ibcon#[25=USB\r\n] 2006.173.13:54:36.16#ibcon#*before write, iclass 25, count 0 2006.173.13:54:36.16#ibcon#enter sib2, iclass 25, count 0 2006.173.13:54:36.16#ibcon#flushed, iclass 25, count 0 2006.173.13:54:36.16#ibcon#about to write, iclass 25, count 0 2006.173.13:54:36.16#ibcon#wrote, iclass 25, count 0 2006.173.13:54:36.16#ibcon#about to read 3, iclass 25, count 0 2006.173.13:54:36.19#ibcon#read 3, iclass 25, count 0 2006.173.13:54:36.19#ibcon#about to read 4, iclass 25, count 0 2006.173.13:54:36.19#ibcon#read 4, iclass 25, count 0 2006.173.13:54:36.19#ibcon#about to read 5, iclass 25, count 0 2006.173.13:54:36.19#ibcon#read 5, iclass 25, count 0 2006.173.13:54:36.19#ibcon#about to read 6, iclass 25, count 0 2006.173.13:54:36.19#ibcon#read 6, iclass 25, count 0 2006.173.13:54:36.19#ibcon#end of sib2, iclass 25, count 0 2006.173.13:54:36.19#ibcon#*after write, iclass 25, count 0 2006.173.13:54:36.19#ibcon#*before return 0, iclass 25, count 0 2006.173.13:54:36.19#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.13:54:36.19#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.13:54:36.19#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.13:54:36.19#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.13:54:36.19$vck44/valo=7,864.99 2006.173.13:54:36.19#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.13:54:36.19#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.13:54:36.19#ibcon#ireg 17 cls_cnt 0 2006.173.13:54:36.19#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.13:54:36.19#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.13:54:36.19#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.13:54:36.19#ibcon#enter wrdev, iclass 27, count 0 2006.173.13:54:36.19#ibcon#first serial, iclass 27, count 0 2006.173.13:54:36.19#ibcon#enter sib2, iclass 27, count 0 2006.173.13:54:36.19#ibcon#flushed, iclass 27, count 0 2006.173.13:54:36.19#ibcon#about to write, iclass 27, count 0 2006.173.13:54:36.19#ibcon#wrote, iclass 27, count 0 2006.173.13:54:36.19#ibcon#about to read 3, iclass 27, count 0 2006.173.13:54:36.21#ibcon#read 3, iclass 27, count 0 2006.173.13:54:36.21#ibcon#about to read 4, iclass 27, count 0 2006.173.13:54:36.21#ibcon#read 4, iclass 27, count 0 2006.173.13:54:36.21#ibcon#about to read 5, iclass 27, count 0 2006.173.13:54:36.21#ibcon#read 5, iclass 27, count 0 2006.173.13:54:36.21#ibcon#about to read 6, iclass 27, count 0 2006.173.13:54:36.21#ibcon#read 6, iclass 27, count 0 2006.173.13:54:36.21#ibcon#end of sib2, iclass 27, count 0 2006.173.13:54:36.21#ibcon#*mode == 0, iclass 27, count 0 2006.173.13:54:36.21#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.13:54:36.21#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.13:54:36.21#ibcon#*before write, iclass 27, count 0 2006.173.13:54:36.21#ibcon#enter sib2, iclass 27, count 0 2006.173.13:54:36.21#ibcon#flushed, iclass 27, count 0 2006.173.13:54:36.21#ibcon#about to write, iclass 27, count 0 2006.173.13:54:36.21#ibcon#wrote, iclass 27, count 0 2006.173.13:54:36.21#ibcon#about to read 3, iclass 27, count 0 2006.173.13:54:36.25#ibcon#read 3, iclass 27, count 0 2006.173.13:54:36.25#ibcon#about to read 4, iclass 27, count 0 2006.173.13:54:36.25#ibcon#read 4, iclass 27, count 0 2006.173.13:54:36.25#ibcon#about to read 5, iclass 27, count 0 2006.173.13:54:36.25#ibcon#read 5, iclass 27, count 0 2006.173.13:54:36.25#ibcon#about to read 6, iclass 27, count 0 2006.173.13:54:36.25#ibcon#read 6, iclass 27, count 0 2006.173.13:54:36.25#ibcon#end of sib2, iclass 27, count 0 2006.173.13:54:36.25#ibcon#*after write, iclass 27, count 0 2006.173.13:54:36.25#ibcon#*before return 0, iclass 27, count 0 2006.173.13:54:36.25#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.13:54:36.25#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.13:54:36.25#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.13:54:36.25#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.13:54:36.25$vck44/va=7,4 2006.173.13:54:36.25#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.13:54:36.25#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.13:54:36.25#ibcon#ireg 11 cls_cnt 2 2006.173.13:54:36.25#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.13:54:36.31#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.13:54:36.31#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.13:54:36.31#ibcon#enter wrdev, iclass 29, count 2 2006.173.13:54:36.31#ibcon#first serial, iclass 29, count 2 2006.173.13:54:36.31#ibcon#enter sib2, iclass 29, count 2 2006.173.13:54:36.31#ibcon#flushed, iclass 29, count 2 2006.173.13:54:36.31#ibcon#about to write, iclass 29, count 2 2006.173.13:54:36.31#ibcon#wrote, iclass 29, count 2 2006.173.13:54:36.31#ibcon#about to read 3, iclass 29, count 2 2006.173.13:54:36.33#ibcon#read 3, iclass 29, count 2 2006.173.13:54:36.33#ibcon#about to read 4, iclass 29, count 2 2006.173.13:54:36.33#ibcon#read 4, iclass 29, count 2 2006.173.13:54:36.33#ibcon#about to read 5, iclass 29, count 2 2006.173.13:54:36.33#ibcon#read 5, iclass 29, count 2 2006.173.13:54:36.33#ibcon#about to read 6, iclass 29, count 2 2006.173.13:54:36.33#ibcon#read 6, iclass 29, count 2 2006.173.13:54:36.33#ibcon#end of sib2, iclass 29, count 2 2006.173.13:54:36.33#ibcon#*mode == 0, iclass 29, count 2 2006.173.13:54:36.33#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.13:54:36.33#ibcon#[25=AT07-04\r\n] 2006.173.13:54:36.33#ibcon#*before write, iclass 29, count 2 2006.173.13:54:36.33#ibcon#enter sib2, iclass 29, count 2 2006.173.13:54:36.33#ibcon#flushed, iclass 29, count 2 2006.173.13:54:36.33#ibcon#about to write, iclass 29, count 2 2006.173.13:54:36.33#ibcon#wrote, iclass 29, count 2 2006.173.13:54:36.33#ibcon#about to read 3, iclass 29, count 2 2006.173.13:54:36.36#ibcon#read 3, iclass 29, count 2 2006.173.13:54:36.36#ibcon#about to read 4, iclass 29, count 2 2006.173.13:54:36.36#ibcon#read 4, iclass 29, count 2 2006.173.13:54:36.36#ibcon#about to read 5, iclass 29, count 2 2006.173.13:54:36.36#ibcon#read 5, iclass 29, count 2 2006.173.13:54:36.36#ibcon#about to read 6, iclass 29, count 2 2006.173.13:54:36.36#ibcon#read 6, iclass 29, count 2 2006.173.13:54:36.36#ibcon#end of sib2, iclass 29, count 2 2006.173.13:54:36.36#ibcon#*after write, iclass 29, count 2 2006.173.13:54:36.36#ibcon#*before return 0, iclass 29, count 2 2006.173.13:54:36.36#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.13:54:36.36#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.13:54:36.36#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.13:54:36.36#ibcon#ireg 7 cls_cnt 0 2006.173.13:54:36.36#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.13:54:36.48#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.13:54:36.48#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.13:54:36.48#ibcon#enter wrdev, iclass 29, count 0 2006.173.13:54:36.48#ibcon#first serial, iclass 29, count 0 2006.173.13:54:36.48#ibcon#enter sib2, iclass 29, count 0 2006.173.13:54:36.48#ibcon#flushed, iclass 29, count 0 2006.173.13:54:36.48#ibcon#about to write, iclass 29, count 0 2006.173.13:54:36.48#ibcon#wrote, iclass 29, count 0 2006.173.13:54:36.48#ibcon#about to read 3, iclass 29, count 0 2006.173.13:54:36.50#ibcon#read 3, iclass 29, count 0 2006.173.13:54:36.50#ibcon#about to read 4, iclass 29, count 0 2006.173.13:54:36.50#ibcon#read 4, iclass 29, count 0 2006.173.13:54:36.50#ibcon#about to read 5, iclass 29, count 0 2006.173.13:54:36.50#ibcon#read 5, iclass 29, count 0 2006.173.13:54:36.50#ibcon#about to read 6, iclass 29, count 0 2006.173.13:54:36.50#ibcon#read 6, iclass 29, count 0 2006.173.13:54:36.50#ibcon#end of sib2, iclass 29, count 0 2006.173.13:54:36.50#ibcon#*mode == 0, iclass 29, count 0 2006.173.13:54:36.50#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.13:54:36.50#ibcon#[25=USB\r\n] 2006.173.13:54:36.50#ibcon#*before write, iclass 29, count 0 2006.173.13:54:36.50#ibcon#enter sib2, iclass 29, count 0 2006.173.13:54:36.50#ibcon#flushed, iclass 29, count 0 2006.173.13:54:36.50#ibcon#about to write, iclass 29, count 0 2006.173.13:54:36.50#ibcon#wrote, iclass 29, count 0 2006.173.13:54:36.50#ibcon#about to read 3, iclass 29, count 0 2006.173.13:54:36.53#ibcon#read 3, iclass 29, count 0 2006.173.13:54:36.53#ibcon#about to read 4, iclass 29, count 0 2006.173.13:54:36.53#ibcon#read 4, iclass 29, count 0 2006.173.13:54:36.53#ibcon#about to read 5, iclass 29, count 0 2006.173.13:54:36.53#ibcon#read 5, iclass 29, count 0 2006.173.13:54:36.53#ibcon#about to read 6, iclass 29, count 0 2006.173.13:54:36.53#ibcon#read 6, iclass 29, count 0 2006.173.13:54:36.53#ibcon#end of sib2, iclass 29, count 0 2006.173.13:54:36.53#ibcon#*after write, iclass 29, count 0 2006.173.13:54:36.53#ibcon#*before return 0, iclass 29, count 0 2006.173.13:54:36.53#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.13:54:36.53#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.13:54:36.53#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.13:54:36.53#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.13:54:36.53$vck44/valo=8,884.99 2006.173.13:54:36.53#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.13:54:36.53#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.13:54:36.53#ibcon#ireg 17 cls_cnt 0 2006.173.13:54:36.53#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.13:54:36.53#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.13:54:36.53#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.13:54:36.53#ibcon#enter wrdev, iclass 31, count 0 2006.173.13:54:36.53#ibcon#first serial, iclass 31, count 0 2006.173.13:54:36.53#ibcon#enter sib2, iclass 31, count 0 2006.173.13:54:36.53#ibcon#flushed, iclass 31, count 0 2006.173.13:54:36.53#ibcon#about to write, iclass 31, count 0 2006.173.13:54:36.53#ibcon#wrote, iclass 31, count 0 2006.173.13:54:36.53#ibcon#about to read 3, iclass 31, count 0 2006.173.13:54:36.55#ibcon#read 3, iclass 31, count 0 2006.173.13:54:36.55#ibcon#about to read 4, iclass 31, count 0 2006.173.13:54:36.55#ibcon#read 4, iclass 31, count 0 2006.173.13:54:36.55#ibcon#about to read 5, iclass 31, count 0 2006.173.13:54:36.55#ibcon#read 5, iclass 31, count 0 2006.173.13:54:36.55#ibcon#about to read 6, iclass 31, count 0 2006.173.13:54:36.55#ibcon#read 6, iclass 31, count 0 2006.173.13:54:36.55#ibcon#end of sib2, iclass 31, count 0 2006.173.13:54:36.55#ibcon#*mode == 0, iclass 31, count 0 2006.173.13:54:36.55#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.13:54:36.55#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.13:54:36.55#ibcon#*before write, iclass 31, count 0 2006.173.13:54:36.55#ibcon#enter sib2, iclass 31, count 0 2006.173.13:54:36.55#ibcon#flushed, iclass 31, count 0 2006.173.13:54:36.55#ibcon#about to write, iclass 31, count 0 2006.173.13:54:36.55#ibcon#wrote, iclass 31, count 0 2006.173.13:54:36.55#ibcon#about to read 3, iclass 31, count 0 2006.173.13:54:36.59#ibcon#read 3, iclass 31, count 0 2006.173.13:54:36.59#ibcon#about to read 4, iclass 31, count 0 2006.173.13:54:36.59#ibcon#read 4, iclass 31, count 0 2006.173.13:54:36.59#ibcon#about to read 5, iclass 31, count 0 2006.173.13:54:36.59#ibcon#read 5, iclass 31, count 0 2006.173.13:54:36.59#ibcon#about to read 6, iclass 31, count 0 2006.173.13:54:36.59#ibcon#read 6, iclass 31, count 0 2006.173.13:54:36.59#ibcon#end of sib2, iclass 31, count 0 2006.173.13:54:36.59#ibcon#*after write, iclass 31, count 0 2006.173.13:54:36.59#ibcon#*before return 0, iclass 31, count 0 2006.173.13:54:36.59#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.13:54:36.59#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.13:54:36.59#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.13:54:36.59#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.13:54:36.59$vck44/va=8,4 2006.173.13:54:36.59#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.173.13:54:36.59#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.173.13:54:36.59#ibcon#ireg 11 cls_cnt 2 2006.173.13:54:36.59#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.13:54:36.65#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.13:54:36.65#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.13:54:36.65#ibcon#enter wrdev, iclass 33, count 2 2006.173.13:54:36.65#ibcon#first serial, iclass 33, count 2 2006.173.13:54:36.65#ibcon#enter sib2, iclass 33, count 2 2006.173.13:54:36.65#ibcon#flushed, iclass 33, count 2 2006.173.13:54:36.65#ibcon#about to write, iclass 33, count 2 2006.173.13:54:36.65#ibcon#wrote, iclass 33, count 2 2006.173.13:54:36.65#ibcon#about to read 3, iclass 33, count 2 2006.173.13:54:36.67#ibcon#read 3, iclass 33, count 2 2006.173.13:54:36.67#ibcon#about to read 4, iclass 33, count 2 2006.173.13:54:36.67#ibcon#read 4, iclass 33, count 2 2006.173.13:54:36.67#ibcon#about to read 5, iclass 33, count 2 2006.173.13:54:36.67#ibcon#read 5, iclass 33, count 2 2006.173.13:54:36.67#ibcon#about to read 6, iclass 33, count 2 2006.173.13:54:36.67#ibcon#read 6, iclass 33, count 2 2006.173.13:54:36.67#ibcon#end of sib2, iclass 33, count 2 2006.173.13:54:36.67#ibcon#*mode == 0, iclass 33, count 2 2006.173.13:54:36.67#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.173.13:54:36.67#ibcon#[25=AT08-04\r\n] 2006.173.13:54:36.67#ibcon#*before write, iclass 33, count 2 2006.173.13:54:36.67#ibcon#enter sib2, iclass 33, count 2 2006.173.13:54:36.67#ibcon#flushed, iclass 33, count 2 2006.173.13:54:36.67#ibcon#about to write, iclass 33, count 2 2006.173.13:54:36.67#ibcon#wrote, iclass 33, count 2 2006.173.13:54:36.67#ibcon#about to read 3, iclass 33, count 2 2006.173.13:54:36.70#ibcon#read 3, iclass 33, count 2 2006.173.13:54:36.70#ibcon#about to read 4, iclass 33, count 2 2006.173.13:54:36.70#ibcon#read 4, iclass 33, count 2 2006.173.13:54:36.70#ibcon#about to read 5, iclass 33, count 2 2006.173.13:54:36.70#ibcon#read 5, iclass 33, count 2 2006.173.13:54:36.70#ibcon#about to read 6, iclass 33, count 2 2006.173.13:54:36.70#ibcon#read 6, iclass 33, count 2 2006.173.13:54:36.70#ibcon#end of sib2, iclass 33, count 2 2006.173.13:54:36.70#ibcon#*after write, iclass 33, count 2 2006.173.13:54:36.70#ibcon#*before return 0, iclass 33, count 2 2006.173.13:54:36.70#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.13:54:36.70#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.173.13:54:36.70#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.173.13:54:36.70#ibcon#ireg 7 cls_cnt 0 2006.173.13:54:36.70#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.13:54:36.80#abcon#<5=/05 0.7 1.1 21.831001003.7\r\n> 2006.173.13:54:36.82#abcon#{5=INTERFACE CLEAR} 2006.173.13:54:36.82#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.13:54:36.82#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.13:54:36.82#ibcon#enter wrdev, iclass 33, count 0 2006.173.13:54:36.82#ibcon#first serial, iclass 33, count 0 2006.173.13:54:36.82#ibcon#enter sib2, iclass 33, count 0 2006.173.13:54:36.82#ibcon#flushed, iclass 33, count 0 2006.173.13:54:36.82#ibcon#about to write, iclass 33, count 0 2006.173.13:54:36.82#ibcon#wrote, iclass 33, count 0 2006.173.13:54:36.82#ibcon#about to read 3, iclass 33, count 0 2006.173.13:54:36.84#ibcon#read 3, iclass 33, count 0 2006.173.13:54:36.84#ibcon#about to read 4, iclass 33, count 0 2006.173.13:54:36.84#ibcon#read 4, iclass 33, count 0 2006.173.13:54:36.84#ibcon#about to read 5, iclass 33, count 0 2006.173.13:54:36.84#ibcon#read 5, iclass 33, count 0 2006.173.13:54:36.84#ibcon#about to read 6, iclass 33, count 0 2006.173.13:54:36.84#ibcon#read 6, iclass 33, count 0 2006.173.13:54:36.84#ibcon#end of sib2, iclass 33, count 0 2006.173.13:54:36.84#ibcon#*mode == 0, iclass 33, count 0 2006.173.13:54:36.84#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.13:54:36.84#ibcon#[25=USB\r\n] 2006.173.13:54:36.84#ibcon#*before write, iclass 33, count 0 2006.173.13:54:36.84#ibcon#enter sib2, iclass 33, count 0 2006.173.13:54:36.84#ibcon#flushed, iclass 33, count 0 2006.173.13:54:36.84#ibcon#about to write, iclass 33, count 0 2006.173.13:54:36.84#ibcon#wrote, iclass 33, count 0 2006.173.13:54:36.84#ibcon#about to read 3, iclass 33, count 0 2006.173.13:54:36.87#ibcon#read 3, iclass 33, count 0 2006.173.13:54:36.87#ibcon#about to read 4, iclass 33, count 0 2006.173.13:54:36.87#ibcon#read 4, iclass 33, count 0 2006.173.13:54:36.87#ibcon#about to read 5, iclass 33, count 0 2006.173.13:54:36.87#ibcon#read 5, iclass 33, count 0 2006.173.13:54:36.87#ibcon#about to read 6, iclass 33, count 0 2006.173.13:54:36.87#ibcon#read 6, iclass 33, count 0 2006.173.13:54:36.87#ibcon#end of sib2, iclass 33, count 0 2006.173.13:54:36.87#ibcon#*after write, iclass 33, count 0 2006.173.13:54:36.87#ibcon#*before return 0, iclass 33, count 0 2006.173.13:54:36.87#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.13:54:36.87#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.173.13:54:36.87#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.13:54:36.87#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.13:54:36.87$vck44/vblo=1,629.99 2006.173.13:54:36.87#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.13:54:36.87#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.13:54:36.87#ibcon#ireg 17 cls_cnt 0 2006.173.13:54:36.87#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.13:54:36.87#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.13:54:36.87#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.13:54:36.87#ibcon#enter wrdev, iclass 39, count 0 2006.173.13:54:36.87#ibcon#first serial, iclass 39, count 0 2006.173.13:54:36.87#ibcon#enter sib2, iclass 39, count 0 2006.173.13:54:36.87#ibcon#flushed, iclass 39, count 0 2006.173.13:54:36.87#ibcon#about to write, iclass 39, count 0 2006.173.13:54:36.87#ibcon#wrote, iclass 39, count 0 2006.173.13:54:36.87#ibcon#about to read 3, iclass 39, count 0 2006.173.13:54:36.88#abcon#[5=S1D000X0/0*\r\n] 2006.173.13:54:36.89#ibcon#read 3, iclass 39, count 0 2006.173.13:54:36.89#ibcon#about to read 4, iclass 39, count 0 2006.173.13:54:36.89#ibcon#read 4, iclass 39, count 0 2006.173.13:54:36.89#ibcon#about to read 5, iclass 39, count 0 2006.173.13:54:36.89#ibcon#read 5, iclass 39, count 0 2006.173.13:54:36.89#ibcon#about to read 6, iclass 39, count 0 2006.173.13:54:36.89#ibcon#read 6, iclass 39, count 0 2006.173.13:54:36.89#ibcon#end of sib2, iclass 39, count 0 2006.173.13:54:36.89#ibcon#*mode == 0, iclass 39, count 0 2006.173.13:54:36.89#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.13:54:36.89#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.13:54:36.89#ibcon#*before write, iclass 39, count 0 2006.173.13:54:36.89#ibcon#enter sib2, iclass 39, count 0 2006.173.13:54:36.89#ibcon#flushed, iclass 39, count 0 2006.173.13:54:36.89#ibcon#about to write, iclass 39, count 0 2006.173.13:54:36.89#ibcon#wrote, iclass 39, count 0 2006.173.13:54:36.89#ibcon#about to read 3, iclass 39, count 0 2006.173.13:54:36.93#ibcon#read 3, iclass 39, count 0 2006.173.13:54:36.93#ibcon#about to read 4, iclass 39, count 0 2006.173.13:54:36.93#ibcon#read 4, iclass 39, count 0 2006.173.13:54:36.93#ibcon#about to read 5, iclass 39, count 0 2006.173.13:54:36.93#ibcon#read 5, iclass 39, count 0 2006.173.13:54:36.93#ibcon#about to read 6, iclass 39, count 0 2006.173.13:54:36.93#ibcon#read 6, iclass 39, count 0 2006.173.13:54:36.93#ibcon#end of sib2, iclass 39, count 0 2006.173.13:54:36.93#ibcon#*after write, iclass 39, count 0 2006.173.13:54:36.93#ibcon#*before return 0, iclass 39, count 0 2006.173.13:54:36.93#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.13:54:36.93#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.13:54:36.93#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.13:54:36.93#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.13:54:36.93$vck44/vb=1,4 2006.173.13:54:36.93#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.13:54:36.93#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.13:54:36.93#ibcon#ireg 11 cls_cnt 2 2006.173.13:54:36.93#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.13:54:36.93#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.13:54:36.93#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.13:54:36.93#ibcon#enter wrdev, iclass 3, count 2 2006.173.13:54:36.93#ibcon#first serial, iclass 3, count 2 2006.173.13:54:36.93#ibcon#enter sib2, iclass 3, count 2 2006.173.13:54:36.93#ibcon#flushed, iclass 3, count 2 2006.173.13:54:36.93#ibcon#about to write, iclass 3, count 2 2006.173.13:54:36.93#ibcon#wrote, iclass 3, count 2 2006.173.13:54:36.93#ibcon#about to read 3, iclass 3, count 2 2006.173.13:54:36.95#ibcon#read 3, iclass 3, count 2 2006.173.13:54:36.95#ibcon#about to read 4, iclass 3, count 2 2006.173.13:54:36.95#ibcon#read 4, iclass 3, count 2 2006.173.13:54:36.95#ibcon#about to read 5, iclass 3, count 2 2006.173.13:54:36.95#ibcon#read 5, iclass 3, count 2 2006.173.13:54:36.95#ibcon#about to read 6, iclass 3, count 2 2006.173.13:54:36.95#ibcon#read 6, iclass 3, count 2 2006.173.13:54:36.95#ibcon#end of sib2, iclass 3, count 2 2006.173.13:54:36.95#ibcon#*mode == 0, iclass 3, count 2 2006.173.13:54:36.95#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.13:54:36.95#ibcon#[27=AT01-04\r\n] 2006.173.13:54:36.95#ibcon#*before write, iclass 3, count 2 2006.173.13:54:36.95#ibcon#enter sib2, iclass 3, count 2 2006.173.13:54:36.95#ibcon#flushed, iclass 3, count 2 2006.173.13:54:36.95#ibcon#about to write, iclass 3, count 2 2006.173.13:54:36.95#ibcon#wrote, iclass 3, count 2 2006.173.13:54:36.95#ibcon#about to read 3, iclass 3, count 2 2006.173.13:54:36.98#ibcon#read 3, iclass 3, count 2 2006.173.13:54:36.98#ibcon#about to read 4, iclass 3, count 2 2006.173.13:54:36.98#ibcon#read 4, iclass 3, count 2 2006.173.13:54:36.98#ibcon#about to read 5, iclass 3, count 2 2006.173.13:54:36.98#ibcon#read 5, iclass 3, count 2 2006.173.13:54:36.98#ibcon#about to read 6, iclass 3, count 2 2006.173.13:54:36.98#ibcon#read 6, iclass 3, count 2 2006.173.13:54:36.98#ibcon#end of sib2, iclass 3, count 2 2006.173.13:54:36.98#ibcon#*after write, iclass 3, count 2 2006.173.13:54:36.98#ibcon#*before return 0, iclass 3, count 2 2006.173.13:54:36.98#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.13:54:36.98#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.13:54:36.98#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.13:54:36.98#ibcon#ireg 7 cls_cnt 0 2006.173.13:54:36.98#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.13:54:37.10#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.13:54:37.10#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.13:54:37.10#ibcon#enter wrdev, iclass 3, count 0 2006.173.13:54:37.10#ibcon#first serial, iclass 3, count 0 2006.173.13:54:37.10#ibcon#enter sib2, iclass 3, count 0 2006.173.13:54:37.10#ibcon#flushed, iclass 3, count 0 2006.173.13:54:37.10#ibcon#about to write, iclass 3, count 0 2006.173.13:54:37.10#ibcon#wrote, iclass 3, count 0 2006.173.13:54:37.10#ibcon#about to read 3, iclass 3, count 0 2006.173.13:54:37.12#ibcon#read 3, iclass 3, count 0 2006.173.13:54:37.12#ibcon#about to read 4, iclass 3, count 0 2006.173.13:54:37.12#ibcon#read 4, iclass 3, count 0 2006.173.13:54:37.12#ibcon#about to read 5, iclass 3, count 0 2006.173.13:54:37.12#ibcon#read 5, iclass 3, count 0 2006.173.13:54:37.12#ibcon#about to read 6, iclass 3, count 0 2006.173.13:54:37.12#ibcon#read 6, iclass 3, count 0 2006.173.13:54:37.12#ibcon#end of sib2, iclass 3, count 0 2006.173.13:54:37.12#ibcon#*mode == 0, iclass 3, count 0 2006.173.13:54:37.12#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.13:54:37.12#ibcon#[27=USB\r\n] 2006.173.13:54:37.12#ibcon#*before write, iclass 3, count 0 2006.173.13:54:37.12#ibcon#enter sib2, iclass 3, count 0 2006.173.13:54:37.12#ibcon#flushed, iclass 3, count 0 2006.173.13:54:37.12#ibcon#about to write, iclass 3, count 0 2006.173.13:54:37.12#ibcon#wrote, iclass 3, count 0 2006.173.13:54:37.12#ibcon#about to read 3, iclass 3, count 0 2006.173.13:54:37.15#ibcon#read 3, iclass 3, count 0 2006.173.13:54:37.15#ibcon#about to read 4, iclass 3, count 0 2006.173.13:54:37.15#ibcon#read 4, iclass 3, count 0 2006.173.13:54:37.15#ibcon#about to read 5, iclass 3, count 0 2006.173.13:54:37.15#ibcon#read 5, iclass 3, count 0 2006.173.13:54:37.15#ibcon#about to read 6, iclass 3, count 0 2006.173.13:54:37.15#ibcon#read 6, iclass 3, count 0 2006.173.13:54:37.15#ibcon#end of sib2, iclass 3, count 0 2006.173.13:54:37.15#ibcon#*after write, iclass 3, count 0 2006.173.13:54:37.15#ibcon#*before return 0, iclass 3, count 0 2006.173.13:54:37.15#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.13:54:37.15#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.13:54:37.15#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.13:54:37.15#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.13:54:37.15$vck44/vblo=2,634.99 2006.173.13:54:37.15#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.13:54:37.15#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.13:54:37.15#ibcon#ireg 17 cls_cnt 0 2006.173.13:54:37.15#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.13:54:37.15#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.13:54:37.15#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.13:54:37.15#ibcon#enter wrdev, iclass 5, count 0 2006.173.13:54:37.15#ibcon#first serial, iclass 5, count 0 2006.173.13:54:37.15#ibcon#enter sib2, iclass 5, count 0 2006.173.13:54:37.15#ibcon#flushed, iclass 5, count 0 2006.173.13:54:37.15#ibcon#about to write, iclass 5, count 0 2006.173.13:54:37.15#ibcon#wrote, iclass 5, count 0 2006.173.13:54:37.15#ibcon#about to read 3, iclass 5, count 0 2006.173.13:54:37.17#ibcon#read 3, iclass 5, count 0 2006.173.13:54:37.17#ibcon#about to read 4, iclass 5, count 0 2006.173.13:54:37.17#ibcon#read 4, iclass 5, count 0 2006.173.13:54:37.17#ibcon#about to read 5, iclass 5, count 0 2006.173.13:54:37.17#ibcon#read 5, iclass 5, count 0 2006.173.13:54:37.17#ibcon#about to read 6, iclass 5, count 0 2006.173.13:54:37.17#ibcon#read 6, iclass 5, count 0 2006.173.13:54:37.17#ibcon#end of sib2, iclass 5, count 0 2006.173.13:54:37.17#ibcon#*mode == 0, iclass 5, count 0 2006.173.13:54:37.17#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.13:54:37.17#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.13:54:37.17#ibcon#*before write, iclass 5, count 0 2006.173.13:54:37.17#ibcon#enter sib2, iclass 5, count 0 2006.173.13:54:37.17#ibcon#flushed, iclass 5, count 0 2006.173.13:54:37.17#ibcon#about to write, iclass 5, count 0 2006.173.13:54:37.17#ibcon#wrote, iclass 5, count 0 2006.173.13:54:37.17#ibcon#about to read 3, iclass 5, count 0 2006.173.13:54:37.21#ibcon#read 3, iclass 5, count 0 2006.173.13:54:37.21#ibcon#about to read 4, iclass 5, count 0 2006.173.13:54:37.21#ibcon#read 4, iclass 5, count 0 2006.173.13:54:37.21#ibcon#about to read 5, iclass 5, count 0 2006.173.13:54:37.21#ibcon#read 5, iclass 5, count 0 2006.173.13:54:37.21#ibcon#about to read 6, iclass 5, count 0 2006.173.13:54:37.21#ibcon#read 6, iclass 5, count 0 2006.173.13:54:37.21#ibcon#end of sib2, iclass 5, count 0 2006.173.13:54:37.21#ibcon#*after write, iclass 5, count 0 2006.173.13:54:37.21#ibcon#*before return 0, iclass 5, count 0 2006.173.13:54:37.21#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.13:54:37.21#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.13:54:37.21#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.13:54:37.21#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.13:54:37.21$vck44/vb=2,4 2006.173.13:54:37.21#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.173.13:54:37.21#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.173.13:54:37.21#ibcon#ireg 11 cls_cnt 2 2006.173.13:54:37.21#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.13:54:37.27#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.13:54:37.27#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.13:54:37.27#ibcon#enter wrdev, iclass 7, count 2 2006.173.13:54:37.27#ibcon#first serial, iclass 7, count 2 2006.173.13:54:37.27#ibcon#enter sib2, iclass 7, count 2 2006.173.13:54:37.27#ibcon#flushed, iclass 7, count 2 2006.173.13:54:37.27#ibcon#about to write, iclass 7, count 2 2006.173.13:54:37.27#ibcon#wrote, iclass 7, count 2 2006.173.13:54:37.27#ibcon#about to read 3, iclass 7, count 2 2006.173.13:54:37.29#ibcon#read 3, iclass 7, count 2 2006.173.13:54:37.29#ibcon#about to read 4, iclass 7, count 2 2006.173.13:54:37.29#ibcon#read 4, iclass 7, count 2 2006.173.13:54:37.29#ibcon#about to read 5, iclass 7, count 2 2006.173.13:54:37.29#ibcon#read 5, iclass 7, count 2 2006.173.13:54:37.29#ibcon#about to read 6, iclass 7, count 2 2006.173.13:54:37.29#ibcon#read 6, iclass 7, count 2 2006.173.13:54:37.29#ibcon#end of sib2, iclass 7, count 2 2006.173.13:54:37.29#ibcon#*mode == 0, iclass 7, count 2 2006.173.13:54:37.29#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.173.13:54:37.29#ibcon#[27=AT02-04\r\n] 2006.173.13:54:37.29#ibcon#*before write, iclass 7, count 2 2006.173.13:54:37.29#ibcon#enter sib2, iclass 7, count 2 2006.173.13:54:37.29#ibcon#flushed, iclass 7, count 2 2006.173.13:54:37.29#ibcon#about to write, iclass 7, count 2 2006.173.13:54:37.29#ibcon#wrote, iclass 7, count 2 2006.173.13:54:37.29#ibcon#about to read 3, iclass 7, count 2 2006.173.13:54:37.32#ibcon#read 3, iclass 7, count 2 2006.173.13:54:37.32#ibcon#about to read 4, iclass 7, count 2 2006.173.13:54:37.32#ibcon#read 4, iclass 7, count 2 2006.173.13:54:37.32#ibcon#about to read 5, iclass 7, count 2 2006.173.13:54:37.32#ibcon#read 5, iclass 7, count 2 2006.173.13:54:37.32#ibcon#about to read 6, iclass 7, count 2 2006.173.13:54:37.32#ibcon#read 6, iclass 7, count 2 2006.173.13:54:37.32#ibcon#end of sib2, iclass 7, count 2 2006.173.13:54:37.32#ibcon#*after write, iclass 7, count 2 2006.173.13:54:37.32#ibcon#*before return 0, iclass 7, count 2 2006.173.13:54:37.32#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.13:54:37.32#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.173.13:54:37.32#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.173.13:54:37.32#ibcon#ireg 7 cls_cnt 0 2006.173.13:54:37.32#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.13:54:37.44#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.13:54:37.44#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.13:54:37.44#ibcon#enter wrdev, iclass 7, count 0 2006.173.13:54:37.44#ibcon#first serial, iclass 7, count 0 2006.173.13:54:37.44#ibcon#enter sib2, iclass 7, count 0 2006.173.13:54:37.44#ibcon#flushed, iclass 7, count 0 2006.173.13:54:37.44#ibcon#about to write, iclass 7, count 0 2006.173.13:54:37.44#ibcon#wrote, iclass 7, count 0 2006.173.13:54:37.44#ibcon#about to read 3, iclass 7, count 0 2006.173.13:54:37.46#ibcon#read 3, iclass 7, count 0 2006.173.13:54:37.46#ibcon#about to read 4, iclass 7, count 0 2006.173.13:54:37.46#ibcon#read 4, iclass 7, count 0 2006.173.13:54:37.46#ibcon#about to read 5, iclass 7, count 0 2006.173.13:54:37.46#ibcon#read 5, iclass 7, count 0 2006.173.13:54:37.46#ibcon#about to read 6, iclass 7, count 0 2006.173.13:54:37.46#ibcon#read 6, iclass 7, count 0 2006.173.13:54:37.46#ibcon#end of sib2, iclass 7, count 0 2006.173.13:54:37.46#ibcon#*mode == 0, iclass 7, count 0 2006.173.13:54:37.46#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.13:54:37.46#ibcon#[27=USB\r\n] 2006.173.13:54:37.46#ibcon#*before write, iclass 7, count 0 2006.173.13:54:37.46#ibcon#enter sib2, iclass 7, count 0 2006.173.13:54:37.46#ibcon#flushed, iclass 7, count 0 2006.173.13:54:37.46#ibcon#about to write, iclass 7, count 0 2006.173.13:54:37.46#ibcon#wrote, iclass 7, count 0 2006.173.13:54:37.46#ibcon#about to read 3, iclass 7, count 0 2006.173.13:54:37.49#ibcon#read 3, iclass 7, count 0 2006.173.13:54:37.49#ibcon#about to read 4, iclass 7, count 0 2006.173.13:54:37.49#ibcon#read 4, iclass 7, count 0 2006.173.13:54:37.49#ibcon#about to read 5, iclass 7, count 0 2006.173.13:54:37.49#ibcon#read 5, iclass 7, count 0 2006.173.13:54:37.49#ibcon#about to read 6, iclass 7, count 0 2006.173.13:54:37.49#ibcon#read 6, iclass 7, count 0 2006.173.13:54:37.49#ibcon#end of sib2, iclass 7, count 0 2006.173.13:54:37.49#ibcon#*after write, iclass 7, count 0 2006.173.13:54:37.49#ibcon#*before return 0, iclass 7, count 0 2006.173.13:54:37.49#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.13:54:37.49#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.173.13:54:37.49#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.13:54:37.49#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.13:54:37.49$vck44/vblo=3,649.99 2006.173.13:54:37.49#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.13:54:37.49#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.13:54:37.49#ibcon#ireg 17 cls_cnt 0 2006.173.13:54:37.49#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.13:54:37.49#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.13:54:37.49#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.13:54:37.49#ibcon#enter wrdev, iclass 11, count 0 2006.173.13:54:37.49#ibcon#first serial, iclass 11, count 0 2006.173.13:54:37.49#ibcon#enter sib2, iclass 11, count 0 2006.173.13:54:37.49#ibcon#flushed, iclass 11, count 0 2006.173.13:54:37.49#ibcon#about to write, iclass 11, count 0 2006.173.13:54:37.49#ibcon#wrote, iclass 11, count 0 2006.173.13:54:37.49#ibcon#about to read 3, iclass 11, count 0 2006.173.13:54:37.51#ibcon#read 3, iclass 11, count 0 2006.173.13:54:37.51#ibcon#about to read 4, iclass 11, count 0 2006.173.13:54:37.51#ibcon#read 4, iclass 11, count 0 2006.173.13:54:37.51#ibcon#about to read 5, iclass 11, count 0 2006.173.13:54:37.51#ibcon#read 5, iclass 11, count 0 2006.173.13:54:37.51#ibcon#about to read 6, iclass 11, count 0 2006.173.13:54:37.51#ibcon#read 6, iclass 11, count 0 2006.173.13:54:37.51#ibcon#end of sib2, iclass 11, count 0 2006.173.13:54:37.51#ibcon#*mode == 0, iclass 11, count 0 2006.173.13:54:37.51#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.13:54:37.51#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.13:54:37.51#ibcon#*before write, iclass 11, count 0 2006.173.13:54:37.51#ibcon#enter sib2, iclass 11, count 0 2006.173.13:54:37.51#ibcon#flushed, iclass 11, count 0 2006.173.13:54:37.51#ibcon#about to write, iclass 11, count 0 2006.173.13:54:37.51#ibcon#wrote, iclass 11, count 0 2006.173.13:54:37.51#ibcon#about to read 3, iclass 11, count 0 2006.173.13:54:37.55#ibcon#read 3, iclass 11, count 0 2006.173.13:54:37.55#ibcon#about to read 4, iclass 11, count 0 2006.173.13:54:37.55#ibcon#read 4, iclass 11, count 0 2006.173.13:54:37.55#ibcon#about to read 5, iclass 11, count 0 2006.173.13:54:37.55#ibcon#read 5, iclass 11, count 0 2006.173.13:54:37.55#ibcon#about to read 6, iclass 11, count 0 2006.173.13:54:37.55#ibcon#read 6, iclass 11, count 0 2006.173.13:54:37.55#ibcon#end of sib2, iclass 11, count 0 2006.173.13:54:37.55#ibcon#*after write, iclass 11, count 0 2006.173.13:54:37.55#ibcon#*before return 0, iclass 11, count 0 2006.173.13:54:37.55#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.13:54:37.55#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.13:54:37.55#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.13:54:37.55#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.13:54:37.55$vck44/vb=3,4 2006.173.13:54:37.55#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.173.13:54:37.55#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.173.13:54:37.55#ibcon#ireg 11 cls_cnt 2 2006.173.13:54:37.55#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.13:54:37.61#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.13:54:37.61#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.13:54:37.61#ibcon#enter wrdev, iclass 13, count 2 2006.173.13:54:37.61#ibcon#first serial, iclass 13, count 2 2006.173.13:54:37.61#ibcon#enter sib2, iclass 13, count 2 2006.173.13:54:37.61#ibcon#flushed, iclass 13, count 2 2006.173.13:54:37.61#ibcon#about to write, iclass 13, count 2 2006.173.13:54:37.61#ibcon#wrote, iclass 13, count 2 2006.173.13:54:37.61#ibcon#about to read 3, iclass 13, count 2 2006.173.13:54:37.63#ibcon#read 3, iclass 13, count 2 2006.173.13:54:37.63#ibcon#about to read 4, iclass 13, count 2 2006.173.13:54:37.63#ibcon#read 4, iclass 13, count 2 2006.173.13:54:37.63#ibcon#about to read 5, iclass 13, count 2 2006.173.13:54:37.63#ibcon#read 5, iclass 13, count 2 2006.173.13:54:37.63#ibcon#about to read 6, iclass 13, count 2 2006.173.13:54:37.63#ibcon#read 6, iclass 13, count 2 2006.173.13:54:37.63#ibcon#end of sib2, iclass 13, count 2 2006.173.13:54:37.63#ibcon#*mode == 0, iclass 13, count 2 2006.173.13:54:37.63#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.173.13:54:37.63#ibcon#[27=AT03-04\r\n] 2006.173.13:54:37.63#ibcon#*before write, iclass 13, count 2 2006.173.13:54:37.63#ibcon#enter sib2, iclass 13, count 2 2006.173.13:54:37.63#ibcon#flushed, iclass 13, count 2 2006.173.13:54:37.63#ibcon#about to write, iclass 13, count 2 2006.173.13:54:37.63#ibcon#wrote, iclass 13, count 2 2006.173.13:54:37.63#ibcon#about to read 3, iclass 13, count 2 2006.173.13:54:37.66#ibcon#read 3, iclass 13, count 2 2006.173.13:54:37.66#ibcon#about to read 4, iclass 13, count 2 2006.173.13:54:37.66#ibcon#read 4, iclass 13, count 2 2006.173.13:54:37.66#ibcon#about to read 5, iclass 13, count 2 2006.173.13:54:37.66#ibcon#read 5, iclass 13, count 2 2006.173.13:54:37.66#ibcon#about to read 6, iclass 13, count 2 2006.173.13:54:37.66#ibcon#read 6, iclass 13, count 2 2006.173.13:54:37.66#ibcon#end of sib2, iclass 13, count 2 2006.173.13:54:37.66#ibcon#*after write, iclass 13, count 2 2006.173.13:54:37.66#ibcon#*before return 0, iclass 13, count 2 2006.173.13:54:37.66#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.13:54:37.66#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.173.13:54:37.66#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.173.13:54:37.66#ibcon#ireg 7 cls_cnt 0 2006.173.13:54:37.66#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.13:54:37.78#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.13:54:37.78#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.13:54:37.78#ibcon#enter wrdev, iclass 13, count 0 2006.173.13:54:37.78#ibcon#first serial, iclass 13, count 0 2006.173.13:54:37.78#ibcon#enter sib2, iclass 13, count 0 2006.173.13:54:37.78#ibcon#flushed, iclass 13, count 0 2006.173.13:54:37.78#ibcon#about to write, iclass 13, count 0 2006.173.13:54:37.78#ibcon#wrote, iclass 13, count 0 2006.173.13:54:37.78#ibcon#about to read 3, iclass 13, count 0 2006.173.13:54:37.80#ibcon#read 3, iclass 13, count 0 2006.173.13:54:37.80#ibcon#about to read 4, iclass 13, count 0 2006.173.13:54:37.80#ibcon#read 4, iclass 13, count 0 2006.173.13:54:37.80#ibcon#about to read 5, iclass 13, count 0 2006.173.13:54:37.80#ibcon#read 5, iclass 13, count 0 2006.173.13:54:37.80#ibcon#about to read 6, iclass 13, count 0 2006.173.13:54:37.80#ibcon#read 6, iclass 13, count 0 2006.173.13:54:37.80#ibcon#end of sib2, iclass 13, count 0 2006.173.13:54:37.80#ibcon#*mode == 0, iclass 13, count 0 2006.173.13:54:37.80#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.13:54:37.80#ibcon#[27=USB\r\n] 2006.173.13:54:37.80#ibcon#*before write, iclass 13, count 0 2006.173.13:54:37.80#ibcon#enter sib2, iclass 13, count 0 2006.173.13:54:37.80#ibcon#flushed, iclass 13, count 0 2006.173.13:54:37.80#ibcon#about to write, iclass 13, count 0 2006.173.13:54:37.80#ibcon#wrote, iclass 13, count 0 2006.173.13:54:37.80#ibcon#about to read 3, iclass 13, count 0 2006.173.13:54:37.83#ibcon#read 3, iclass 13, count 0 2006.173.13:54:37.83#ibcon#about to read 4, iclass 13, count 0 2006.173.13:54:37.83#ibcon#read 4, iclass 13, count 0 2006.173.13:54:37.83#ibcon#about to read 5, iclass 13, count 0 2006.173.13:54:37.83#ibcon#read 5, iclass 13, count 0 2006.173.13:54:37.83#ibcon#about to read 6, iclass 13, count 0 2006.173.13:54:37.83#ibcon#read 6, iclass 13, count 0 2006.173.13:54:37.83#ibcon#end of sib2, iclass 13, count 0 2006.173.13:54:37.83#ibcon#*after write, iclass 13, count 0 2006.173.13:54:37.83#ibcon#*before return 0, iclass 13, count 0 2006.173.13:54:37.83#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.13:54:37.83#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.173.13:54:37.83#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.13:54:37.83#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.13:54:37.83$vck44/vblo=4,679.99 2006.173.13:54:37.83#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.13:54:37.83#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.13:54:37.83#ibcon#ireg 17 cls_cnt 0 2006.173.13:54:37.83#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.13:54:37.83#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.13:54:37.83#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.13:54:37.83#ibcon#enter wrdev, iclass 15, count 0 2006.173.13:54:37.83#ibcon#first serial, iclass 15, count 0 2006.173.13:54:37.83#ibcon#enter sib2, iclass 15, count 0 2006.173.13:54:37.83#ibcon#flushed, iclass 15, count 0 2006.173.13:54:37.83#ibcon#about to write, iclass 15, count 0 2006.173.13:54:37.83#ibcon#wrote, iclass 15, count 0 2006.173.13:54:37.83#ibcon#about to read 3, iclass 15, count 0 2006.173.13:54:37.85#ibcon#read 3, iclass 15, count 0 2006.173.13:54:37.85#ibcon#about to read 4, iclass 15, count 0 2006.173.13:54:37.85#ibcon#read 4, iclass 15, count 0 2006.173.13:54:37.85#ibcon#about to read 5, iclass 15, count 0 2006.173.13:54:37.85#ibcon#read 5, iclass 15, count 0 2006.173.13:54:37.85#ibcon#about to read 6, iclass 15, count 0 2006.173.13:54:37.85#ibcon#read 6, iclass 15, count 0 2006.173.13:54:37.85#ibcon#end of sib2, iclass 15, count 0 2006.173.13:54:37.85#ibcon#*mode == 0, iclass 15, count 0 2006.173.13:54:37.85#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.13:54:37.85#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.13:54:37.85#ibcon#*before write, iclass 15, count 0 2006.173.13:54:37.85#ibcon#enter sib2, iclass 15, count 0 2006.173.13:54:37.85#ibcon#flushed, iclass 15, count 0 2006.173.13:54:37.85#ibcon#about to write, iclass 15, count 0 2006.173.13:54:37.85#ibcon#wrote, iclass 15, count 0 2006.173.13:54:37.85#ibcon#about to read 3, iclass 15, count 0 2006.173.13:54:37.89#ibcon#read 3, iclass 15, count 0 2006.173.13:54:37.89#ibcon#about to read 4, iclass 15, count 0 2006.173.13:54:37.89#ibcon#read 4, iclass 15, count 0 2006.173.13:54:37.89#ibcon#about to read 5, iclass 15, count 0 2006.173.13:54:37.89#ibcon#read 5, iclass 15, count 0 2006.173.13:54:37.89#ibcon#about to read 6, iclass 15, count 0 2006.173.13:54:37.89#ibcon#read 6, iclass 15, count 0 2006.173.13:54:37.89#ibcon#end of sib2, iclass 15, count 0 2006.173.13:54:37.89#ibcon#*after write, iclass 15, count 0 2006.173.13:54:37.89#ibcon#*before return 0, iclass 15, count 0 2006.173.13:54:37.89#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.13:54:37.89#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.13:54:37.89#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.13:54:37.89#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.13:54:37.89$vck44/vb=4,4 2006.173.13:54:37.89#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.13:54:37.89#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.13:54:37.89#ibcon#ireg 11 cls_cnt 2 2006.173.13:54:37.89#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.13:54:37.95#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.13:54:37.95#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.13:54:37.95#ibcon#enter wrdev, iclass 17, count 2 2006.173.13:54:37.95#ibcon#first serial, iclass 17, count 2 2006.173.13:54:37.95#ibcon#enter sib2, iclass 17, count 2 2006.173.13:54:37.95#ibcon#flushed, iclass 17, count 2 2006.173.13:54:37.95#ibcon#about to write, iclass 17, count 2 2006.173.13:54:37.95#ibcon#wrote, iclass 17, count 2 2006.173.13:54:37.95#ibcon#about to read 3, iclass 17, count 2 2006.173.13:54:37.97#ibcon#read 3, iclass 17, count 2 2006.173.13:54:37.97#ibcon#about to read 4, iclass 17, count 2 2006.173.13:54:37.97#ibcon#read 4, iclass 17, count 2 2006.173.13:54:37.97#ibcon#about to read 5, iclass 17, count 2 2006.173.13:54:37.97#ibcon#read 5, iclass 17, count 2 2006.173.13:54:37.97#ibcon#about to read 6, iclass 17, count 2 2006.173.13:54:37.97#ibcon#read 6, iclass 17, count 2 2006.173.13:54:37.97#ibcon#end of sib2, iclass 17, count 2 2006.173.13:54:37.97#ibcon#*mode == 0, iclass 17, count 2 2006.173.13:54:37.97#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.13:54:37.97#ibcon#[27=AT04-04\r\n] 2006.173.13:54:37.97#ibcon#*before write, iclass 17, count 2 2006.173.13:54:37.97#ibcon#enter sib2, iclass 17, count 2 2006.173.13:54:37.97#ibcon#flushed, iclass 17, count 2 2006.173.13:54:37.97#ibcon#about to write, iclass 17, count 2 2006.173.13:54:37.97#ibcon#wrote, iclass 17, count 2 2006.173.13:54:37.97#ibcon#about to read 3, iclass 17, count 2 2006.173.13:54:38.00#ibcon#read 3, iclass 17, count 2 2006.173.13:54:38.00#ibcon#about to read 4, iclass 17, count 2 2006.173.13:54:38.00#ibcon#read 4, iclass 17, count 2 2006.173.13:54:38.00#ibcon#about to read 5, iclass 17, count 2 2006.173.13:54:38.00#ibcon#read 5, iclass 17, count 2 2006.173.13:54:38.00#ibcon#about to read 6, iclass 17, count 2 2006.173.13:54:38.00#ibcon#read 6, iclass 17, count 2 2006.173.13:54:38.00#ibcon#end of sib2, iclass 17, count 2 2006.173.13:54:38.00#ibcon#*after write, iclass 17, count 2 2006.173.13:54:38.00#ibcon#*before return 0, iclass 17, count 2 2006.173.13:54:38.00#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.13:54:38.00#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.13:54:38.00#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.13:54:38.00#ibcon#ireg 7 cls_cnt 0 2006.173.13:54:38.00#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.13:54:38.12#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.13:54:38.12#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.13:54:38.12#ibcon#enter wrdev, iclass 17, count 0 2006.173.13:54:38.12#ibcon#first serial, iclass 17, count 0 2006.173.13:54:38.12#ibcon#enter sib2, iclass 17, count 0 2006.173.13:54:38.12#ibcon#flushed, iclass 17, count 0 2006.173.13:54:38.12#ibcon#about to write, iclass 17, count 0 2006.173.13:54:38.12#ibcon#wrote, iclass 17, count 0 2006.173.13:54:38.12#ibcon#about to read 3, iclass 17, count 0 2006.173.13:54:38.14#ibcon#read 3, iclass 17, count 0 2006.173.13:54:38.14#ibcon#about to read 4, iclass 17, count 0 2006.173.13:54:38.14#ibcon#read 4, iclass 17, count 0 2006.173.13:54:38.14#ibcon#about to read 5, iclass 17, count 0 2006.173.13:54:38.14#ibcon#read 5, iclass 17, count 0 2006.173.13:54:38.14#ibcon#about to read 6, iclass 17, count 0 2006.173.13:54:38.14#ibcon#read 6, iclass 17, count 0 2006.173.13:54:38.14#ibcon#end of sib2, iclass 17, count 0 2006.173.13:54:38.14#ibcon#*mode == 0, iclass 17, count 0 2006.173.13:54:38.14#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.13:54:38.14#ibcon#[27=USB\r\n] 2006.173.13:54:38.14#ibcon#*before write, iclass 17, count 0 2006.173.13:54:38.14#ibcon#enter sib2, iclass 17, count 0 2006.173.13:54:38.14#ibcon#flushed, iclass 17, count 0 2006.173.13:54:38.14#ibcon#about to write, iclass 17, count 0 2006.173.13:54:38.14#ibcon#wrote, iclass 17, count 0 2006.173.13:54:38.14#ibcon#about to read 3, iclass 17, count 0 2006.173.13:54:38.17#ibcon#read 3, iclass 17, count 0 2006.173.13:54:38.17#ibcon#about to read 4, iclass 17, count 0 2006.173.13:54:38.17#ibcon#read 4, iclass 17, count 0 2006.173.13:54:38.17#ibcon#about to read 5, iclass 17, count 0 2006.173.13:54:38.17#ibcon#read 5, iclass 17, count 0 2006.173.13:54:38.17#ibcon#about to read 6, iclass 17, count 0 2006.173.13:54:38.17#ibcon#read 6, iclass 17, count 0 2006.173.13:54:38.17#ibcon#end of sib2, iclass 17, count 0 2006.173.13:54:38.17#ibcon#*after write, iclass 17, count 0 2006.173.13:54:38.17#ibcon#*before return 0, iclass 17, count 0 2006.173.13:54:38.17#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.13:54:38.17#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.13:54:38.17#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.13:54:38.17#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.13:54:38.17$vck44/vblo=5,709.99 2006.173.13:54:38.17#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.13:54:38.17#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.13:54:38.17#ibcon#ireg 17 cls_cnt 0 2006.173.13:54:38.17#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.13:54:38.17#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.13:54:38.17#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.13:54:38.17#ibcon#enter wrdev, iclass 19, count 0 2006.173.13:54:38.17#ibcon#first serial, iclass 19, count 0 2006.173.13:54:38.17#ibcon#enter sib2, iclass 19, count 0 2006.173.13:54:38.17#ibcon#flushed, iclass 19, count 0 2006.173.13:54:38.17#ibcon#about to write, iclass 19, count 0 2006.173.13:54:38.17#ibcon#wrote, iclass 19, count 0 2006.173.13:54:38.17#ibcon#about to read 3, iclass 19, count 0 2006.173.13:54:38.19#ibcon#read 3, iclass 19, count 0 2006.173.13:54:38.19#ibcon#about to read 4, iclass 19, count 0 2006.173.13:54:38.19#ibcon#read 4, iclass 19, count 0 2006.173.13:54:38.19#ibcon#about to read 5, iclass 19, count 0 2006.173.13:54:38.19#ibcon#read 5, iclass 19, count 0 2006.173.13:54:38.19#ibcon#about to read 6, iclass 19, count 0 2006.173.13:54:38.19#ibcon#read 6, iclass 19, count 0 2006.173.13:54:38.19#ibcon#end of sib2, iclass 19, count 0 2006.173.13:54:38.19#ibcon#*mode == 0, iclass 19, count 0 2006.173.13:54:38.19#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.13:54:38.19#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.13:54:38.19#ibcon#*before write, iclass 19, count 0 2006.173.13:54:38.19#ibcon#enter sib2, iclass 19, count 0 2006.173.13:54:38.19#ibcon#flushed, iclass 19, count 0 2006.173.13:54:38.19#ibcon#about to write, iclass 19, count 0 2006.173.13:54:38.19#ibcon#wrote, iclass 19, count 0 2006.173.13:54:38.19#ibcon#about to read 3, iclass 19, count 0 2006.173.13:54:38.23#ibcon#read 3, iclass 19, count 0 2006.173.13:54:38.23#ibcon#about to read 4, iclass 19, count 0 2006.173.13:54:38.23#ibcon#read 4, iclass 19, count 0 2006.173.13:54:38.23#ibcon#about to read 5, iclass 19, count 0 2006.173.13:54:38.23#ibcon#read 5, iclass 19, count 0 2006.173.13:54:38.23#ibcon#about to read 6, iclass 19, count 0 2006.173.13:54:38.23#ibcon#read 6, iclass 19, count 0 2006.173.13:54:38.23#ibcon#end of sib2, iclass 19, count 0 2006.173.13:54:38.23#ibcon#*after write, iclass 19, count 0 2006.173.13:54:38.23#ibcon#*before return 0, iclass 19, count 0 2006.173.13:54:38.23#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.13:54:38.23#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.13:54:38.23#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.13:54:38.23#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.13:54:38.23$vck44/vb=5,4 2006.173.13:54:38.23#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.13:54:38.23#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.13:54:38.23#ibcon#ireg 11 cls_cnt 2 2006.173.13:54:38.23#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.13:54:38.29#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.13:54:38.29#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.13:54:38.29#ibcon#enter wrdev, iclass 21, count 2 2006.173.13:54:38.29#ibcon#first serial, iclass 21, count 2 2006.173.13:54:38.29#ibcon#enter sib2, iclass 21, count 2 2006.173.13:54:38.29#ibcon#flushed, iclass 21, count 2 2006.173.13:54:38.29#ibcon#about to write, iclass 21, count 2 2006.173.13:54:38.29#ibcon#wrote, iclass 21, count 2 2006.173.13:54:38.29#ibcon#about to read 3, iclass 21, count 2 2006.173.13:54:38.31#ibcon#read 3, iclass 21, count 2 2006.173.13:54:38.31#ibcon#about to read 4, iclass 21, count 2 2006.173.13:54:38.31#ibcon#read 4, iclass 21, count 2 2006.173.13:54:38.31#ibcon#about to read 5, iclass 21, count 2 2006.173.13:54:38.31#ibcon#read 5, iclass 21, count 2 2006.173.13:54:38.31#ibcon#about to read 6, iclass 21, count 2 2006.173.13:54:38.31#ibcon#read 6, iclass 21, count 2 2006.173.13:54:38.31#ibcon#end of sib2, iclass 21, count 2 2006.173.13:54:38.31#ibcon#*mode == 0, iclass 21, count 2 2006.173.13:54:38.31#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.13:54:38.31#ibcon#[27=AT05-04\r\n] 2006.173.13:54:38.31#ibcon#*before write, iclass 21, count 2 2006.173.13:54:38.31#ibcon#enter sib2, iclass 21, count 2 2006.173.13:54:38.31#ibcon#flushed, iclass 21, count 2 2006.173.13:54:38.31#ibcon#about to write, iclass 21, count 2 2006.173.13:54:38.31#ibcon#wrote, iclass 21, count 2 2006.173.13:54:38.31#ibcon#about to read 3, iclass 21, count 2 2006.173.13:54:38.34#ibcon#read 3, iclass 21, count 2 2006.173.13:54:38.34#ibcon#about to read 4, iclass 21, count 2 2006.173.13:54:38.34#ibcon#read 4, iclass 21, count 2 2006.173.13:54:38.34#ibcon#about to read 5, iclass 21, count 2 2006.173.13:54:38.34#ibcon#read 5, iclass 21, count 2 2006.173.13:54:38.34#ibcon#about to read 6, iclass 21, count 2 2006.173.13:54:38.34#ibcon#read 6, iclass 21, count 2 2006.173.13:54:38.34#ibcon#end of sib2, iclass 21, count 2 2006.173.13:54:38.34#ibcon#*after write, iclass 21, count 2 2006.173.13:54:38.34#ibcon#*before return 0, iclass 21, count 2 2006.173.13:54:38.34#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.13:54:38.34#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.13:54:38.34#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.13:54:38.34#ibcon#ireg 7 cls_cnt 0 2006.173.13:54:38.34#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.13:54:38.46#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.13:54:38.46#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.13:54:38.46#ibcon#enter wrdev, iclass 21, count 0 2006.173.13:54:38.46#ibcon#first serial, iclass 21, count 0 2006.173.13:54:38.46#ibcon#enter sib2, iclass 21, count 0 2006.173.13:54:38.46#ibcon#flushed, iclass 21, count 0 2006.173.13:54:38.46#ibcon#about to write, iclass 21, count 0 2006.173.13:54:38.46#ibcon#wrote, iclass 21, count 0 2006.173.13:54:38.46#ibcon#about to read 3, iclass 21, count 0 2006.173.13:54:38.48#ibcon#read 3, iclass 21, count 0 2006.173.13:54:38.48#ibcon#about to read 4, iclass 21, count 0 2006.173.13:54:38.48#ibcon#read 4, iclass 21, count 0 2006.173.13:54:38.48#ibcon#about to read 5, iclass 21, count 0 2006.173.13:54:38.48#ibcon#read 5, iclass 21, count 0 2006.173.13:54:38.48#ibcon#about to read 6, iclass 21, count 0 2006.173.13:54:38.48#ibcon#read 6, iclass 21, count 0 2006.173.13:54:38.48#ibcon#end of sib2, iclass 21, count 0 2006.173.13:54:38.48#ibcon#*mode == 0, iclass 21, count 0 2006.173.13:54:38.48#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.13:54:38.48#ibcon#[27=USB\r\n] 2006.173.13:54:38.48#ibcon#*before write, iclass 21, count 0 2006.173.13:54:38.48#ibcon#enter sib2, iclass 21, count 0 2006.173.13:54:38.48#ibcon#flushed, iclass 21, count 0 2006.173.13:54:38.48#ibcon#about to write, iclass 21, count 0 2006.173.13:54:38.48#ibcon#wrote, iclass 21, count 0 2006.173.13:54:38.48#ibcon#about to read 3, iclass 21, count 0 2006.173.13:54:38.51#ibcon#read 3, iclass 21, count 0 2006.173.13:54:38.51#ibcon#about to read 4, iclass 21, count 0 2006.173.13:54:38.51#ibcon#read 4, iclass 21, count 0 2006.173.13:54:38.51#ibcon#about to read 5, iclass 21, count 0 2006.173.13:54:38.51#ibcon#read 5, iclass 21, count 0 2006.173.13:54:38.51#ibcon#about to read 6, iclass 21, count 0 2006.173.13:54:38.51#ibcon#read 6, iclass 21, count 0 2006.173.13:54:38.51#ibcon#end of sib2, iclass 21, count 0 2006.173.13:54:38.51#ibcon#*after write, iclass 21, count 0 2006.173.13:54:38.51#ibcon#*before return 0, iclass 21, count 0 2006.173.13:54:38.51#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.13:54:38.51#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.13:54:38.51#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.13:54:38.51#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.13:54:38.51$vck44/vblo=6,719.99 2006.173.13:54:38.51#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.13:54:38.51#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.13:54:38.51#ibcon#ireg 17 cls_cnt 0 2006.173.13:54:38.51#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.13:54:38.51#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.13:54:38.51#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.13:54:38.51#ibcon#enter wrdev, iclass 23, count 0 2006.173.13:54:38.51#ibcon#first serial, iclass 23, count 0 2006.173.13:54:38.51#ibcon#enter sib2, iclass 23, count 0 2006.173.13:54:38.51#ibcon#flushed, iclass 23, count 0 2006.173.13:54:38.51#ibcon#about to write, iclass 23, count 0 2006.173.13:54:38.51#ibcon#wrote, iclass 23, count 0 2006.173.13:54:38.51#ibcon#about to read 3, iclass 23, count 0 2006.173.13:54:38.53#ibcon#read 3, iclass 23, count 0 2006.173.13:54:38.53#ibcon#about to read 4, iclass 23, count 0 2006.173.13:54:38.53#ibcon#read 4, iclass 23, count 0 2006.173.13:54:38.53#ibcon#about to read 5, iclass 23, count 0 2006.173.13:54:38.53#ibcon#read 5, iclass 23, count 0 2006.173.13:54:38.53#ibcon#about to read 6, iclass 23, count 0 2006.173.13:54:38.53#ibcon#read 6, iclass 23, count 0 2006.173.13:54:38.53#ibcon#end of sib2, iclass 23, count 0 2006.173.13:54:38.53#ibcon#*mode == 0, iclass 23, count 0 2006.173.13:54:38.53#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.13:54:38.53#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.13:54:38.53#ibcon#*before write, iclass 23, count 0 2006.173.13:54:38.53#ibcon#enter sib2, iclass 23, count 0 2006.173.13:54:38.53#ibcon#flushed, iclass 23, count 0 2006.173.13:54:38.53#ibcon#about to write, iclass 23, count 0 2006.173.13:54:38.53#ibcon#wrote, iclass 23, count 0 2006.173.13:54:38.53#ibcon#about to read 3, iclass 23, count 0 2006.173.13:54:38.57#ibcon#read 3, iclass 23, count 0 2006.173.13:54:38.57#ibcon#about to read 4, iclass 23, count 0 2006.173.13:54:38.57#ibcon#read 4, iclass 23, count 0 2006.173.13:54:38.57#ibcon#about to read 5, iclass 23, count 0 2006.173.13:54:38.57#ibcon#read 5, iclass 23, count 0 2006.173.13:54:38.57#ibcon#about to read 6, iclass 23, count 0 2006.173.13:54:38.57#ibcon#read 6, iclass 23, count 0 2006.173.13:54:38.57#ibcon#end of sib2, iclass 23, count 0 2006.173.13:54:38.57#ibcon#*after write, iclass 23, count 0 2006.173.13:54:38.57#ibcon#*before return 0, iclass 23, count 0 2006.173.13:54:38.57#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.13:54:38.57#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.13:54:38.57#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.13:54:38.57#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.13:54:38.57$vck44/vb=6,4 2006.173.13:54:38.57#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.13:54:38.57#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.13:54:38.57#ibcon#ireg 11 cls_cnt 2 2006.173.13:54:38.57#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.13:54:38.63#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.13:54:38.63#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.13:54:38.63#ibcon#enter wrdev, iclass 25, count 2 2006.173.13:54:38.63#ibcon#first serial, iclass 25, count 2 2006.173.13:54:38.63#ibcon#enter sib2, iclass 25, count 2 2006.173.13:54:38.63#ibcon#flushed, iclass 25, count 2 2006.173.13:54:38.63#ibcon#about to write, iclass 25, count 2 2006.173.13:54:38.63#ibcon#wrote, iclass 25, count 2 2006.173.13:54:38.63#ibcon#about to read 3, iclass 25, count 2 2006.173.13:54:38.65#ibcon#read 3, iclass 25, count 2 2006.173.13:54:38.65#ibcon#about to read 4, iclass 25, count 2 2006.173.13:54:38.65#ibcon#read 4, iclass 25, count 2 2006.173.13:54:38.65#ibcon#about to read 5, iclass 25, count 2 2006.173.13:54:38.65#ibcon#read 5, iclass 25, count 2 2006.173.13:54:38.65#ibcon#about to read 6, iclass 25, count 2 2006.173.13:54:38.65#ibcon#read 6, iclass 25, count 2 2006.173.13:54:38.65#ibcon#end of sib2, iclass 25, count 2 2006.173.13:54:38.65#ibcon#*mode == 0, iclass 25, count 2 2006.173.13:54:38.65#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.13:54:38.65#ibcon#[27=AT06-04\r\n] 2006.173.13:54:38.65#ibcon#*before write, iclass 25, count 2 2006.173.13:54:38.65#ibcon#enter sib2, iclass 25, count 2 2006.173.13:54:38.65#ibcon#flushed, iclass 25, count 2 2006.173.13:54:38.65#ibcon#about to write, iclass 25, count 2 2006.173.13:54:38.65#ibcon#wrote, iclass 25, count 2 2006.173.13:54:38.65#ibcon#about to read 3, iclass 25, count 2 2006.173.13:54:38.68#ibcon#read 3, iclass 25, count 2 2006.173.13:54:38.68#ibcon#about to read 4, iclass 25, count 2 2006.173.13:54:38.68#ibcon#read 4, iclass 25, count 2 2006.173.13:54:38.68#ibcon#about to read 5, iclass 25, count 2 2006.173.13:54:38.68#ibcon#read 5, iclass 25, count 2 2006.173.13:54:38.68#ibcon#about to read 6, iclass 25, count 2 2006.173.13:54:38.68#ibcon#read 6, iclass 25, count 2 2006.173.13:54:38.68#ibcon#end of sib2, iclass 25, count 2 2006.173.13:54:38.68#ibcon#*after write, iclass 25, count 2 2006.173.13:54:38.68#ibcon#*before return 0, iclass 25, count 2 2006.173.13:54:38.68#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.13:54:38.68#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.13:54:38.68#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.13:54:38.68#ibcon#ireg 7 cls_cnt 0 2006.173.13:54:38.68#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.13:54:38.80#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.13:54:38.80#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.13:54:38.80#ibcon#enter wrdev, iclass 25, count 0 2006.173.13:54:38.80#ibcon#first serial, iclass 25, count 0 2006.173.13:54:38.80#ibcon#enter sib2, iclass 25, count 0 2006.173.13:54:38.80#ibcon#flushed, iclass 25, count 0 2006.173.13:54:38.80#ibcon#about to write, iclass 25, count 0 2006.173.13:54:38.80#ibcon#wrote, iclass 25, count 0 2006.173.13:54:38.80#ibcon#about to read 3, iclass 25, count 0 2006.173.13:54:38.82#ibcon#read 3, iclass 25, count 0 2006.173.13:54:38.82#ibcon#about to read 4, iclass 25, count 0 2006.173.13:54:38.82#ibcon#read 4, iclass 25, count 0 2006.173.13:54:38.82#ibcon#about to read 5, iclass 25, count 0 2006.173.13:54:38.82#ibcon#read 5, iclass 25, count 0 2006.173.13:54:38.82#ibcon#about to read 6, iclass 25, count 0 2006.173.13:54:38.82#ibcon#read 6, iclass 25, count 0 2006.173.13:54:38.82#ibcon#end of sib2, iclass 25, count 0 2006.173.13:54:38.82#ibcon#*mode == 0, iclass 25, count 0 2006.173.13:54:38.82#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.13:54:38.82#ibcon#[27=USB\r\n] 2006.173.13:54:38.82#ibcon#*before write, iclass 25, count 0 2006.173.13:54:38.82#ibcon#enter sib2, iclass 25, count 0 2006.173.13:54:38.82#ibcon#flushed, iclass 25, count 0 2006.173.13:54:38.82#ibcon#about to write, iclass 25, count 0 2006.173.13:54:38.82#ibcon#wrote, iclass 25, count 0 2006.173.13:54:38.82#ibcon#about to read 3, iclass 25, count 0 2006.173.13:54:38.85#ibcon#read 3, iclass 25, count 0 2006.173.13:54:38.85#ibcon#about to read 4, iclass 25, count 0 2006.173.13:54:38.85#ibcon#read 4, iclass 25, count 0 2006.173.13:54:38.85#ibcon#about to read 5, iclass 25, count 0 2006.173.13:54:38.85#ibcon#read 5, iclass 25, count 0 2006.173.13:54:38.85#ibcon#about to read 6, iclass 25, count 0 2006.173.13:54:38.85#ibcon#read 6, iclass 25, count 0 2006.173.13:54:38.85#ibcon#end of sib2, iclass 25, count 0 2006.173.13:54:38.85#ibcon#*after write, iclass 25, count 0 2006.173.13:54:38.85#ibcon#*before return 0, iclass 25, count 0 2006.173.13:54:38.85#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.13:54:38.85#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.13:54:38.85#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.13:54:38.85#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.13:54:38.85$vck44/vblo=7,734.99 2006.173.13:54:38.85#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.13:54:38.85#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.13:54:38.85#ibcon#ireg 17 cls_cnt 0 2006.173.13:54:38.85#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.13:54:38.85#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.13:54:38.85#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.13:54:38.85#ibcon#enter wrdev, iclass 27, count 0 2006.173.13:54:38.85#ibcon#first serial, iclass 27, count 0 2006.173.13:54:38.85#ibcon#enter sib2, iclass 27, count 0 2006.173.13:54:38.85#ibcon#flushed, iclass 27, count 0 2006.173.13:54:38.85#ibcon#about to write, iclass 27, count 0 2006.173.13:54:38.85#ibcon#wrote, iclass 27, count 0 2006.173.13:54:38.85#ibcon#about to read 3, iclass 27, count 0 2006.173.13:54:38.87#ibcon#read 3, iclass 27, count 0 2006.173.13:54:38.87#ibcon#about to read 4, iclass 27, count 0 2006.173.13:54:38.87#ibcon#read 4, iclass 27, count 0 2006.173.13:54:38.87#ibcon#about to read 5, iclass 27, count 0 2006.173.13:54:38.87#ibcon#read 5, iclass 27, count 0 2006.173.13:54:38.87#ibcon#about to read 6, iclass 27, count 0 2006.173.13:54:38.87#ibcon#read 6, iclass 27, count 0 2006.173.13:54:38.87#ibcon#end of sib2, iclass 27, count 0 2006.173.13:54:38.87#ibcon#*mode == 0, iclass 27, count 0 2006.173.13:54:38.87#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.13:54:38.87#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.13:54:38.87#ibcon#*before write, iclass 27, count 0 2006.173.13:54:38.87#ibcon#enter sib2, iclass 27, count 0 2006.173.13:54:38.87#ibcon#flushed, iclass 27, count 0 2006.173.13:54:38.87#ibcon#about to write, iclass 27, count 0 2006.173.13:54:38.87#ibcon#wrote, iclass 27, count 0 2006.173.13:54:38.87#ibcon#about to read 3, iclass 27, count 0 2006.173.13:54:38.91#ibcon#read 3, iclass 27, count 0 2006.173.13:54:38.91#ibcon#about to read 4, iclass 27, count 0 2006.173.13:54:38.91#ibcon#read 4, iclass 27, count 0 2006.173.13:54:38.91#ibcon#about to read 5, iclass 27, count 0 2006.173.13:54:38.91#ibcon#read 5, iclass 27, count 0 2006.173.13:54:38.91#ibcon#about to read 6, iclass 27, count 0 2006.173.13:54:38.91#ibcon#read 6, iclass 27, count 0 2006.173.13:54:38.91#ibcon#end of sib2, iclass 27, count 0 2006.173.13:54:38.91#ibcon#*after write, iclass 27, count 0 2006.173.13:54:38.91#ibcon#*before return 0, iclass 27, count 0 2006.173.13:54:38.91#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.13:54:38.91#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.13:54:38.91#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.13:54:38.91#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.13:54:38.91$vck44/vb=7,4 2006.173.13:54:38.91#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.13:54:38.91#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.13:54:38.91#ibcon#ireg 11 cls_cnt 2 2006.173.13:54:38.91#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.13:54:38.97#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.13:54:38.97#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.13:54:38.97#ibcon#enter wrdev, iclass 29, count 2 2006.173.13:54:38.97#ibcon#first serial, iclass 29, count 2 2006.173.13:54:38.97#ibcon#enter sib2, iclass 29, count 2 2006.173.13:54:38.97#ibcon#flushed, iclass 29, count 2 2006.173.13:54:38.97#ibcon#about to write, iclass 29, count 2 2006.173.13:54:38.97#ibcon#wrote, iclass 29, count 2 2006.173.13:54:38.97#ibcon#about to read 3, iclass 29, count 2 2006.173.13:54:38.99#ibcon#read 3, iclass 29, count 2 2006.173.13:54:38.99#ibcon#about to read 4, iclass 29, count 2 2006.173.13:54:38.99#ibcon#read 4, iclass 29, count 2 2006.173.13:54:38.99#ibcon#about to read 5, iclass 29, count 2 2006.173.13:54:38.99#ibcon#read 5, iclass 29, count 2 2006.173.13:54:38.99#ibcon#about to read 6, iclass 29, count 2 2006.173.13:54:38.99#ibcon#read 6, iclass 29, count 2 2006.173.13:54:38.99#ibcon#end of sib2, iclass 29, count 2 2006.173.13:54:38.99#ibcon#*mode == 0, iclass 29, count 2 2006.173.13:54:38.99#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.13:54:38.99#ibcon#[27=AT07-04\r\n] 2006.173.13:54:38.99#ibcon#*before write, iclass 29, count 2 2006.173.13:54:38.99#ibcon#enter sib2, iclass 29, count 2 2006.173.13:54:38.99#ibcon#flushed, iclass 29, count 2 2006.173.13:54:38.99#ibcon#about to write, iclass 29, count 2 2006.173.13:54:38.99#ibcon#wrote, iclass 29, count 2 2006.173.13:54:38.99#ibcon#about to read 3, iclass 29, count 2 2006.173.13:54:39.02#ibcon#read 3, iclass 29, count 2 2006.173.13:54:39.02#ibcon#about to read 4, iclass 29, count 2 2006.173.13:54:39.02#ibcon#read 4, iclass 29, count 2 2006.173.13:54:39.02#ibcon#about to read 5, iclass 29, count 2 2006.173.13:54:39.02#ibcon#read 5, iclass 29, count 2 2006.173.13:54:39.02#ibcon#about to read 6, iclass 29, count 2 2006.173.13:54:39.02#ibcon#read 6, iclass 29, count 2 2006.173.13:54:39.02#ibcon#end of sib2, iclass 29, count 2 2006.173.13:54:39.02#ibcon#*after write, iclass 29, count 2 2006.173.13:54:39.02#ibcon#*before return 0, iclass 29, count 2 2006.173.13:54:39.02#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.13:54:39.02#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.13:54:39.02#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.13:54:39.02#ibcon#ireg 7 cls_cnt 0 2006.173.13:54:39.02#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.13:54:39.14#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.13:54:39.14#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.13:54:39.14#ibcon#enter wrdev, iclass 29, count 0 2006.173.13:54:39.14#ibcon#first serial, iclass 29, count 0 2006.173.13:54:39.14#ibcon#enter sib2, iclass 29, count 0 2006.173.13:54:39.14#ibcon#flushed, iclass 29, count 0 2006.173.13:54:39.14#ibcon#about to write, iclass 29, count 0 2006.173.13:54:39.14#ibcon#wrote, iclass 29, count 0 2006.173.13:54:39.14#ibcon#about to read 3, iclass 29, count 0 2006.173.13:54:39.16#ibcon#read 3, iclass 29, count 0 2006.173.13:54:39.16#ibcon#about to read 4, iclass 29, count 0 2006.173.13:54:39.16#ibcon#read 4, iclass 29, count 0 2006.173.13:54:39.16#ibcon#about to read 5, iclass 29, count 0 2006.173.13:54:39.16#ibcon#read 5, iclass 29, count 0 2006.173.13:54:39.16#ibcon#about to read 6, iclass 29, count 0 2006.173.13:54:39.16#ibcon#read 6, iclass 29, count 0 2006.173.13:54:39.16#ibcon#end of sib2, iclass 29, count 0 2006.173.13:54:39.16#ibcon#*mode == 0, iclass 29, count 0 2006.173.13:54:39.16#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.13:54:39.16#ibcon#[27=USB\r\n] 2006.173.13:54:39.16#ibcon#*before write, iclass 29, count 0 2006.173.13:54:39.16#ibcon#enter sib2, iclass 29, count 0 2006.173.13:54:39.16#ibcon#flushed, iclass 29, count 0 2006.173.13:54:39.16#ibcon#about to write, iclass 29, count 0 2006.173.13:54:39.16#ibcon#wrote, iclass 29, count 0 2006.173.13:54:39.16#ibcon#about to read 3, iclass 29, count 0 2006.173.13:54:39.19#ibcon#read 3, iclass 29, count 0 2006.173.13:54:39.19#ibcon#about to read 4, iclass 29, count 0 2006.173.13:54:39.19#ibcon#read 4, iclass 29, count 0 2006.173.13:54:39.19#ibcon#about to read 5, iclass 29, count 0 2006.173.13:54:39.19#ibcon#read 5, iclass 29, count 0 2006.173.13:54:39.19#ibcon#about to read 6, iclass 29, count 0 2006.173.13:54:39.19#ibcon#read 6, iclass 29, count 0 2006.173.13:54:39.19#ibcon#end of sib2, iclass 29, count 0 2006.173.13:54:39.19#ibcon#*after write, iclass 29, count 0 2006.173.13:54:39.19#ibcon#*before return 0, iclass 29, count 0 2006.173.13:54:39.19#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.13:54:39.19#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.13:54:39.19#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.13:54:39.19#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.13:54:39.19$vck44/vblo=8,744.99 2006.173.13:54:39.19#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.13:54:39.19#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.13:54:39.19#ibcon#ireg 17 cls_cnt 0 2006.173.13:54:39.19#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.13:54:39.19#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.13:54:39.19#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.13:54:39.19#ibcon#enter wrdev, iclass 31, count 0 2006.173.13:54:39.19#ibcon#first serial, iclass 31, count 0 2006.173.13:54:39.19#ibcon#enter sib2, iclass 31, count 0 2006.173.13:54:39.19#ibcon#flushed, iclass 31, count 0 2006.173.13:54:39.19#ibcon#about to write, iclass 31, count 0 2006.173.13:54:39.19#ibcon#wrote, iclass 31, count 0 2006.173.13:54:39.19#ibcon#about to read 3, iclass 31, count 0 2006.173.13:54:39.21#ibcon#read 3, iclass 31, count 0 2006.173.13:54:39.21#ibcon#about to read 4, iclass 31, count 0 2006.173.13:54:39.21#ibcon#read 4, iclass 31, count 0 2006.173.13:54:39.21#ibcon#about to read 5, iclass 31, count 0 2006.173.13:54:39.21#ibcon#read 5, iclass 31, count 0 2006.173.13:54:39.21#ibcon#about to read 6, iclass 31, count 0 2006.173.13:54:39.21#ibcon#read 6, iclass 31, count 0 2006.173.13:54:39.21#ibcon#end of sib2, iclass 31, count 0 2006.173.13:54:39.21#ibcon#*mode == 0, iclass 31, count 0 2006.173.13:54:39.21#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.13:54:39.21#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.13:54:39.21#ibcon#*before write, iclass 31, count 0 2006.173.13:54:39.21#ibcon#enter sib2, iclass 31, count 0 2006.173.13:54:39.21#ibcon#flushed, iclass 31, count 0 2006.173.13:54:39.21#ibcon#about to write, iclass 31, count 0 2006.173.13:54:39.21#ibcon#wrote, iclass 31, count 0 2006.173.13:54:39.21#ibcon#about to read 3, iclass 31, count 0 2006.173.13:54:39.25#ibcon#read 3, iclass 31, count 0 2006.173.13:54:39.25#ibcon#about to read 4, iclass 31, count 0 2006.173.13:54:39.25#ibcon#read 4, iclass 31, count 0 2006.173.13:54:39.25#ibcon#about to read 5, iclass 31, count 0 2006.173.13:54:39.25#ibcon#read 5, iclass 31, count 0 2006.173.13:54:39.25#ibcon#about to read 6, iclass 31, count 0 2006.173.13:54:39.25#ibcon#read 6, iclass 31, count 0 2006.173.13:54:39.25#ibcon#end of sib2, iclass 31, count 0 2006.173.13:54:39.25#ibcon#*after write, iclass 31, count 0 2006.173.13:54:39.25#ibcon#*before return 0, iclass 31, count 0 2006.173.13:54:39.25#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.13:54:39.25#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.13:54:39.25#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.13:54:39.25#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.13:54:39.25$vck44/vb=8,4 2006.173.13:54:39.25#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.173.13:54:39.25#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.173.13:54:39.25#ibcon#ireg 11 cls_cnt 2 2006.173.13:54:39.25#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.13:54:39.31#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.13:54:39.31#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.13:54:39.31#ibcon#enter wrdev, iclass 33, count 2 2006.173.13:54:39.31#ibcon#first serial, iclass 33, count 2 2006.173.13:54:39.31#ibcon#enter sib2, iclass 33, count 2 2006.173.13:54:39.31#ibcon#flushed, iclass 33, count 2 2006.173.13:54:39.31#ibcon#about to write, iclass 33, count 2 2006.173.13:54:39.31#ibcon#wrote, iclass 33, count 2 2006.173.13:54:39.31#ibcon#about to read 3, iclass 33, count 2 2006.173.13:54:39.33#ibcon#read 3, iclass 33, count 2 2006.173.13:54:39.33#ibcon#about to read 4, iclass 33, count 2 2006.173.13:54:39.33#ibcon#read 4, iclass 33, count 2 2006.173.13:54:39.33#ibcon#about to read 5, iclass 33, count 2 2006.173.13:54:39.33#ibcon#read 5, iclass 33, count 2 2006.173.13:54:39.33#ibcon#about to read 6, iclass 33, count 2 2006.173.13:54:39.33#ibcon#read 6, iclass 33, count 2 2006.173.13:54:39.33#ibcon#end of sib2, iclass 33, count 2 2006.173.13:54:39.33#ibcon#*mode == 0, iclass 33, count 2 2006.173.13:54:39.33#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.173.13:54:39.33#ibcon#[27=AT08-04\r\n] 2006.173.13:54:39.33#ibcon#*before write, iclass 33, count 2 2006.173.13:54:39.33#ibcon#enter sib2, iclass 33, count 2 2006.173.13:54:39.33#ibcon#flushed, iclass 33, count 2 2006.173.13:54:39.33#ibcon#about to write, iclass 33, count 2 2006.173.13:54:39.33#ibcon#wrote, iclass 33, count 2 2006.173.13:54:39.33#ibcon#about to read 3, iclass 33, count 2 2006.173.13:54:39.36#ibcon#read 3, iclass 33, count 2 2006.173.13:54:39.36#ibcon#about to read 4, iclass 33, count 2 2006.173.13:54:39.36#ibcon#read 4, iclass 33, count 2 2006.173.13:54:39.36#ibcon#about to read 5, iclass 33, count 2 2006.173.13:54:39.36#ibcon#read 5, iclass 33, count 2 2006.173.13:54:39.36#ibcon#about to read 6, iclass 33, count 2 2006.173.13:54:39.36#ibcon#read 6, iclass 33, count 2 2006.173.13:54:39.36#ibcon#end of sib2, iclass 33, count 2 2006.173.13:54:39.36#ibcon#*after write, iclass 33, count 2 2006.173.13:54:39.36#ibcon#*before return 0, iclass 33, count 2 2006.173.13:54:39.36#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.13:54:39.36#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.173.13:54:39.36#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.173.13:54:39.36#ibcon#ireg 7 cls_cnt 0 2006.173.13:54:39.36#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.13:54:39.48#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.13:54:39.48#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.13:54:39.48#ibcon#enter wrdev, iclass 33, count 0 2006.173.13:54:39.48#ibcon#first serial, iclass 33, count 0 2006.173.13:54:39.48#ibcon#enter sib2, iclass 33, count 0 2006.173.13:54:39.48#ibcon#flushed, iclass 33, count 0 2006.173.13:54:39.48#ibcon#about to write, iclass 33, count 0 2006.173.13:54:39.48#ibcon#wrote, iclass 33, count 0 2006.173.13:54:39.48#ibcon#about to read 3, iclass 33, count 0 2006.173.13:54:39.50#ibcon#read 3, iclass 33, count 0 2006.173.13:54:39.50#ibcon#about to read 4, iclass 33, count 0 2006.173.13:54:39.50#ibcon#read 4, iclass 33, count 0 2006.173.13:54:39.50#ibcon#about to read 5, iclass 33, count 0 2006.173.13:54:39.50#ibcon#read 5, iclass 33, count 0 2006.173.13:54:39.50#ibcon#about to read 6, iclass 33, count 0 2006.173.13:54:39.50#ibcon#read 6, iclass 33, count 0 2006.173.13:54:39.50#ibcon#end of sib2, iclass 33, count 0 2006.173.13:54:39.50#ibcon#*mode == 0, iclass 33, count 0 2006.173.13:54:39.50#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.13:54:39.50#ibcon#[27=USB\r\n] 2006.173.13:54:39.50#ibcon#*before write, iclass 33, count 0 2006.173.13:54:39.50#ibcon#enter sib2, iclass 33, count 0 2006.173.13:54:39.50#ibcon#flushed, iclass 33, count 0 2006.173.13:54:39.50#ibcon#about to write, iclass 33, count 0 2006.173.13:54:39.50#ibcon#wrote, iclass 33, count 0 2006.173.13:54:39.50#ibcon#about to read 3, iclass 33, count 0 2006.173.13:54:39.53#ibcon#read 3, iclass 33, count 0 2006.173.13:54:39.53#ibcon#about to read 4, iclass 33, count 0 2006.173.13:54:39.53#ibcon#read 4, iclass 33, count 0 2006.173.13:54:39.53#ibcon#about to read 5, iclass 33, count 0 2006.173.13:54:39.53#ibcon#read 5, iclass 33, count 0 2006.173.13:54:39.53#ibcon#about to read 6, iclass 33, count 0 2006.173.13:54:39.53#ibcon#read 6, iclass 33, count 0 2006.173.13:54:39.53#ibcon#end of sib2, iclass 33, count 0 2006.173.13:54:39.53#ibcon#*after write, iclass 33, count 0 2006.173.13:54:39.53#ibcon#*before return 0, iclass 33, count 0 2006.173.13:54:39.53#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.13:54:39.53#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.173.13:54:39.53#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.13:54:39.53#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.13:54:39.53$vck44/vabw=wide 2006.173.13:54:39.53#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.13:54:39.53#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.13:54:39.53#ibcon#ireg 8 cls_cnt 0 2006.173.13:54:39.53#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.13:54:39.53#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.13:54:39.53#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.13:54:39.53#ibcon#enter wrdev, iclass 35, count 0 2006.173.13:54:39.53#ibcon#first serial, iclass 35, count 0 2006.173.13:54:39.53#ibcon#enter sib2, iclass 35, count 0 2006.173.13:54:39.53#ibcon#flushed, iclass 35, count 0 2006.173.13:54:39.53#ibcon#about to write, iclass 35, count 0 2006.173.13:54:39.53#ibcon#wrote, iclass 35, count 0 2006.173.13:54:39.53#ibcon#about to read 3, iclass 35, count 0 2006.173.13:54:39.55#ibcon#read 3, iclass 35, count 0 2006.173.13:54:39.55#ibcon#about to read 4, iclass 35, count 0 2006.173.13:54:39.55#ibcon#read 4, iclass 35, count 0 2006.173.13:54:39.55#ibcon#about to read 5, iclass 35, count 0 2006.173.13:54:39.55#ibcon#read 5, iclass 35, count 0 2006.173.13:54:39.55#ibcon#about to read 6, iclass 35, count 0 2006.173.13:54:39.55#ibcon#read 6, iclass 35, count 0 2006.173.13:54:39.55#ibcon#end of sib2, iclass 35, count 0 2006.173.13:54:39.55#ibcon#*mode == 0, iclass 35, count 0 2006.173.13:54:39.55#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.13:54:39.55#ibcon#[25=BW32\r\n] 2006.173.13:54:39.55#ibcon#*before write, iclass 35, count 0 2006.173.13:54:39.55#ibcon#enter sib2, iclass 35, count 0 2006.173.13:54:39.55#ibcon#flushed, iclass 35, count 0 2006.173.13:54:39.55#ibcon#about to write, iclass 35, count 0 2006.173.13:54:39.55#ibcon#wrote, iclass 35, count 0 2006.173.13:54:39.55#ibcon#about to read 3, iclass 35, count 0 2006.173.13:54:39.58#ibcon#read 3, iclass 35, count 0 2006.173.13:54:39.58#ibcon#about to read 4, iclass 35, count 0 2006.173.13:54:39.58#ibcon#read 4, iclass 35, count 0 2006.173.13:54:39.58#ibcon#about to read 5, iclass 35, count 0 2006.173.13:54:39.58#ibcon#read 5, iclass 35, count 0 2006.173.13:54:39.58#ibcon#about to read 6, iclass 35, count 0 2006.173.13:54:39.58#ibcon#read 6, iclass 35, count 0 2006.173.13:54:39.58#ibcon#end of sib2, iclass 35, count 0 2006.173.13:54:39.58#ibcon#*after write, iclass 35, count 0 2006.173.13:54:39.58#ibcon#*before return 0, iclass 35, count 0 2006.173.13:54:39.58#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.13:54:39.58#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.13:54:39.58#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.13:54:39.58#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.13:54:39.58$vck44/vbbw=wide 2006.173.13:54:39.58#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.13:54:39.58#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.13:54:39.58#ibcon#ireg 8 cls_cnt 0 2006.173.13:54:39.58#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.13:54:39.65#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.13:54:39.65#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.13:54:39.65#ibcon#enter wrdev, iclass 37, count 0 2006.173.13:54:39.65#ibcon#first serial, iclass 37, count 0 2006.173.13:54:39.65#ibcon#enter sib2, iclass 37, count 0 2006.173.13:54:39.65#ibcon#flushed, iclass 37, count 0 2006.173.13:54:39.65#ibcon#about to write, iclass 37, count 0 2006.173.13:54:39.65#ibcon#wrote, iclass 37, count 0 2006.173.13:54:39.65#ibcon#about to read 3, iclass 37, count 0 2006.173.13:54:39.67#ibcon#read 3, iclass 37, count 0 2006.173.13:54:39.67#ibcon#about to read 4, iclass 37, count 0 2006.173.13:54:39.67#ibcon#read 4, iclass 37, count 0 2006.173.13:54:39.67#ibcon#about to read 5, iclass 37, count 0 2006.173.13:54:39.67#ibcon#read 5, iclass 37, count 0 2006.173.13:54:39.67#ibcon#about to read 6, iclass 37, count 0 2006.173.13:54:39.67#ibcon#read 6, iclass 37, count 0 2006.173.13:54:39.67#ibcon#end of sib2, iclass 37, count 0 2006.173.13:54:39.67#ibcon#*mode == 0, iclass 37, count 0 2006.173.13:54:39.67#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.13:54:39.67#ibcon#[27=BW32\r\n] 2006.173.13:54:39.67#ibcon#*before write, iclass 37, count 0 2006.173.13:54:39.67#ibcon#enter sib2, iclass 37, count 0 2006.173.13:54:39.67#ibcon#flushed, iclass 37, count 0 2006.173.13:54:39.67#ibcon#about to write, iclass 37, count 0 2006.173.13:54:39.67#ibcon#wrote, iclass 37, count 0 2006.173.13:54:39.67#ibcon#about to read 3, iclass 37, count 0 2006.173.13:54:39.70#ibcon#read 3, iclass 37, count 0 2006.173.13:54:39.70#ibcon#about to read 4, iclass 37, count 0 2006.173.13:54:39.70#ibcon#read 4, iclass 37, count 0 2006.173.13:54:39.70#ibcon#about to read 5, iclass 37, count 0 2006.173.13:54:39.70#ibcon#read 5, iclass 37, count 0 2006.173.13:54:39.70#ibcon#about to read 6, iclass 37, count 0 2006.173.13:54:39.70#ibcon#read 6, iclass 37, count 0 2006.173.13:54:39.70#ibcon#end of sib2, iclass 37, count 0 2006.173.13:54:39.70#ibcon#*after write, iclass 37, count 0 2006.173.13:54:39.70#ibcon#*before return 0, iclass 37, count 0 2006.173.13:54:39.70#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.13:54:39.70#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.13:54:39.70#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.13:54:39.70#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.13:54:39.70$setupk4/ifdk4 2006.173.13:54:39.70$ifdk4/lo= 2006.173.13:54:39.70$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.13:54:39.70$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.13:54:39.70$ifdk4/patch= 2006.173.13:54:39.70$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.13:54:39.70$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.13:54:39.70$setupk4/!*+20s 2006.173.13:54:46.97#abcon#<5=/04 0.7 1.1 21.821001003.7\r\n> 2006.173.13:54:46.99#abcon#{5=INTERFACE CLEAR} 2006.173.13:54:47.05#abcon#[5=S1D000X0/0*\r\n] 2006.173.13:54:54.21$setupk4/"tpicd 2006.173.13:54:54.21$setupk4/echo=off 2006.173.13:54:54.21$setupk4/xlog=off 2006.173.13:54:54.21:!2006.173.13:59:00 2006.173.13:54:56.13#trakl#Source acquired 2006.173.13:54:56.13#flagr#flagr/antenna,acquired 2006.173.13:59:00.00:preob 2006.173.13:59:00.14/onsource/TRACKING 2006.173.13:59:00.14:!2006.173.13:59:10 2006.173.13:59:10.00:"tape 2006.173.13:59:10.00:"st=record 2006.173.13:59:10.00:data_valid=on 2006.173.13:59:10.00:midob 2006.173.13:59:11.14/onsource/TRACKING 2006.173.13:59:11.14/wx/21.78,1003.7,100 2006.173.13:59:11.29/cable/+6.5051E-03 2006.173.13:59:12.38/va/01,07,usb,yes,48,51 2006.173.13:59:12.38/va/02,06,usb,yes,48,49 2006.173.13:59:12.38/va/03,05,usb,yes,60,62 2006.173.13:59:12.38/va/04,06,usb,yes,49,51 2006.173.13:59:12.38/va/05,04,usb,yes,39,40 2006.173.13:59:12.38/va/06,03,usb,yes,54,54 2006.173.13:59:12.38/va/07,04,usb,yes,44,45 2006.173.13:59:12.38/va/08,04,usb,yes,38,45 2006.173.13:59:12.61/valo/01,524.99,yes,locked 2006.173.13:59:12.61/valo/02,534.99,yes,locked 2006.173.13:59:12.61/valo/03,564.99,yes,locked 2006.173.13:59:12.61/valo/04,624.99,yes,locked 2006.173.13:59:12.61/valo/05,734.99,yes,locked 2006.173.13:59:12.61/valo/06,814.99,yes,locked 2006.173.13:59:12.61/valo/07,864.99,yes,locked 2006.173.13:59:12.61/valo/08,884.99,yes,locked 2006.173.13:59:13.70/vb/01,04,usb,yes,31,29 2006.173.13:59:13.70/vb/02,04,usb,yes,33,33 2006.173.13:59:13.70/vb/03,04,usb,yes,30,33 2006.173.13:59:13.70/vb/04,04,usb,yes,35,34 2006.173.13:59:13.70/vb/05,04,usb,yes,27,30 2006.173.13:59:13.70/vb/06,04,usb,yes,32,28 2006.173.13:59:13.70/vb/07,04,usb,yes,32,31 2006.173.13:59:13.70/vb/08,04,usb,yes,29,32 2006.173.13:59:13.94/vblo/01,629.99,yes,locked 2006.173.13:59:13.94/vblo/02,634.99,yes,locked 2006.173.13:59:13.94/vblo/03,649.99,yes,locked 2006.173.13:59:13.94/vblo/04,679.99,yes,locked 2006.173.13:59:13.94/vblo/05,709.99,yes,locked 2006.173.13:59:13.94/vblo/06,719.99,yes,locked 2006.173.13:59:13.94/vblo/07,734.99,yes,locked 2006.173.13:59:13.94/vblo/08,744.99,yes,locked 2006.173.13:59:14.09/vabw/8 2006.173.13:59:14.24/vbbw/8 2006.173.13:59:14.33/xfe/off,on,15.0 2006.173.13:59:14.71/ifatt/23,28,28,28 2006.173.13:59:15.08/fmout-gps/S +3.91E-07 2006.173.13:59:15.12:!2006.173.13:59:50 2006.173.13:59:50.00:data_valid=off 2006.173.13:59:50.00:"et 2006.173.13:59:50.00:!+3s 2006.173.13:59:53.01:"tape 2006.173.13:59:53.01:postob 2006.173.13:59:53.16/cable/+6.5050E-03 2006.173.13:59:53.16/wx/21.78,1003.7,100 2006.173.13:59:54.08/fmout-gps/S +3.92E-07 2006.173.13:59:54.08:scan_name=173-1401,jd0606,110 2006.173.13:59:54.08:source=3c274,123049.42,122328.0,2000.0,cw 2006.173.13:59:55.14#flagr#flagr/antenna,new-source 2006.173.13:59:55.14:checkk5 2006.173.13:59:55.55/chk_autoobs//k5ts1/ autoobs is running! 2006.173.13:59:55.95/chk_autoobs//k5ts2/ autoobs is running! 2006.173.13:59:56.37/chk_autoobs//k5ts3/ autoobs is running! 2006.173.13:59:56.75/chk_autoobs//k5ts4/ autoobs is running! 2006.173.13:59:57.15/chk_obsdata//k5ts1/T1731359??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.173.13:59:57.54/chk_obsdata//k5ts2/T1731359??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.173.13:59:57.96/chk_obsdata//k5ts3/T1731359??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.173.13:59:58.37/chk_obsdata//k5ts4/T1731359??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.173.13:59:59.09/k5log//k5ts1_log_newline 2006.173.13:59:59.82/k5log//k5ts2_log_newline 2006.173.14:00:00.52/k5log//k5ts3_log_newline 2006.173.14:00:01.22/k5log//k5ts4_log_newline 2006.173.14:00:01.25/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.14:00:01.25:setupk4=1 2006.173.14:00:01.25$setupk4/echo=on 2006.173.14:00:01.25$setupk4/pcalon 2006.173.14:00:01.25$pcalon/"no phase cal control is implemented here 2006.173.14:00:01.25$setupk4/"tpicd=stop 2006.173.14:00:01.25$setupk4/"rec=synch_on 2006.173.14:00:01.25$setupk4/"rec_mode=128 2006.173.14:00:01.25$setupk4/!* 2006.173.14:00:01.25$setupk4/recpk4 2006.173.14:00:01.25$recpk4/recpatch= 2006.173.14:00:01.25$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.14:00:01.25$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.14:00:01.25$setupk4/vck44 2006.173.14:00:01.25$vck44/valo=1,524.99 2006.173.14:00:01.25#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.14:00:01.25#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.14:00:01.25#ibcon#ireg 17 cls_cnt 0 2006.173.14:00:01.25#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.14:00:01.25#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.14:00:01.25#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.14:00:01.25#ibcon#enter wrdev, iclass 22, count 0 2006.173.14:00:01.25#ibcon#first serial, iclass 22, count 0 2006.173.14:00:01.25#ibcon#enter sib2, iclass 22, count 0 2006.173.14:00:01.25#ibcon#flushed, iclass 22, count 0 2006.173.14:00:01.25#ibcon#about to write, iclass 22, count 0 2006.173.14:00:01.25#ibcon#wrote, iclass 22, count 0 2006.173.14:00:01.25#ibcon#about to read 3, iclass 22, count 0 2006.173.14:00:01.27#ibcon#read 3, iclass 22, count 0 2006.173.14:00:01.27#ibcon#about to read 4, iclass 22, count 0 2006.173.14:00:01.27#ibcon#read 4, iclass 22, count 0 2006.173.14:00:01.27#ibcon#about to read 5, iclass 22, count 0 2006.173.14:00:01.27#ibcon#read 5, iclass 22, count 0 2006.173.14:00:01.27#ibcon#about to read 6, iclass 22, count 0 2006.173.14:00:01.27#ibcon#read 6, iclass 22, count 0 2006.173.14:00:01.27#ibcon#end of sib2, iclass 22, count 0 2006.173.14:00:01.27#ibcon#*mode == 0, iclass 22, count 0 2006.173.14:00:01.27#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.14:00:01.27#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.14:00:01.27#ibcon#*before write, iclass 22, count 0 2006.173.14:00:01.27#ibcon#enter sib2, iclass 22, count 0 2006.173.14:00:01.27#ibcon#flushed, iclass 22, count 0 2006.173.14:00:01.27#ibcon#about to write, iclass 22, count 0 2006.173.14:00:01.27#ibcon#wrote, iclass 22, count 0 2006.173.14:00:01.27#ibcon#about to read 3, iclass 22, count 0 2006.173.14:00:01.32#ibcon#read 3, iclass 22, count 0 2006.173.14:00:01.32#ibcon#about to read 4, iclass 22, count 0 2006.173.14:00:01.32#ibcon#read 4, iclass 22, count 0 2006.173.14:00:01.32#ibcon#about to read 5, iclass 22, count 0 2006.173.14:00:01.32#ibcon#read 5, iclass 22, count 0 2006.173.14:00:01.32#ibcon#about to read 6, iclass 22, count 0 2006.173.14:00:01.32#ibcon#read 6, iclass 22, count 0 2006.173.14:00:01.32#ibcon#end of sib2, iclass 22, count 0 2006.173.14:00:01.32#ibcon#*after write, iclass 22, count 0 2006.173.14:00:01.32#ibcon#*before return 0, iclass 22, count 0 2006.173.14:00:01.32#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.14:00:01.32#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.14:00:01.32#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.14:00:01.32#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.14:00:01.32$vck44/va=1,7 2006.173.14:00:01.32#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.14:00:01.32#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.14:00:01.32#ibcon#ireg 11 cls_cnt 2 2006.173.14:00:01.32#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.14:00:01.32#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.14:00:01.32#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.14:00:01.32#ibcon#enter wrdev, iclass 24, count 2 2006.173.14:00:01.32#ibcon#first serial, iclass 24, count 2 2006.173.14:00:01.32#ibcon#enter sib2, iclass 24, count 2 2006.173.14:00:01.32#ibcon#flushed, iclass 24, count 2 2006.173.14:00:01.32#ibcon#about to write, iclass 24, count 2 2006.173.14:00:01.32#ibcon#wrote, iclass 24, count 2 2006.173.14:00:01.32#ibcon#about to read 3, iclass 24, count 2 2006.173.14:00:01.34#ibcon#read 3, iclass 24, count 2 2006.173.14:00:01.34#ibcon#about to read 4, iclass 24, count 2 2006.173.14:00:01.34#ibcon#read 4, iclass 24, count 2 2006.173.14:00:01.34#ibcon#about to read 5, iclass 24, count 2 2006.173.14:00:01.34#ibcon#read 5, iclass 24, count 2 2006.173.14:00:01.34#ibcon#about to read 6, iclass 24, count 2 2006.173.14:00:01.34#ibcon#read 6, iclass 24, count 2 2006.173.14:00:01.34#ibcon#end of sib2, iclass 24, count 2 2006.173.14:00:01.34#ibcon#*mode == 0, iclass 24, count 2 2006.173.14:00:01.34#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.14:00:01.34#ibcon#[25=AT01-07\r\n] 2006.173.14:00:01.34#ibcon#*before write, iclass 24, count 2 2006.173.14:00:01.34#ibcon#enter sib2, iclass 24, count 2 2006.173.14:00:01.34#ibcon#flushed, iclass 24, count 2 2006.173.14:00:01.34#ibcon#about to write, iclass 24, count 2 2006.173.14:00:01.34#ibcon#wrote, iclass 24, count 2 2006.173.14:00:01.34#ibcon#about to read 3, iclass 24, count 2 2006.173.14:00:01.37#ibcon#read 3, iclass 24, count 2 2006.173.14:00:01.37#ibcon#about to read 4, iclass 24, count 2 2006.173.14:00:01.37#ibcon#read 4, iclass 24, count 2 2006.173.14:00:01.37#ibcon#about to read 5, iclass 24, count 2 2006.173.14:00:01.37#ibcon#read 5, iclass 24, count 2 2006.173.14:00:01.37#ibcon#about to read 6, iclass 24, count 2 2006.173.14:00:01.37#ibcon#read 6, iclass 24, count 2 2006.173.14:00:01.37#ibcon#end of sib2, iclass 24, count 2 2006.173.14:00:01.37#ibcon#*after write, iclass 24, count 2 2006.173.14:00:01.37#ibcon#*before return 0, iclass 24, count 2 2006.173.14:00:01.37#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.14:00:01.37#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.14:00:01.37#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.14:00:01.37#ibcon#ireg 7 cls_cnt 0 2006.173.14:00:01.37#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.14:00:01.49#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.14:00:01.49#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.14:00:01.49#ibcon#enter wrdev, iclass 24, count 0 2006.173.14:00:01.49#ibcon#first serial, iclass 24, count 0 2006.173.14:00:01.49#ibcon#enter sib2, iclass 24, count 0 2006.173.14:00:01.49#ibcon#flushed, iclass 24, count 0 2006.173.14:00:01.49#ibcon#about to write, iclass 24, count 0 2006.173.14:00:01.49#ibcon#wrote, iclass 24, count 0 2006.173.14:00:01.49#ibcon#about to read 3, iclass 24, count 0 2006.173.14:00:01.51#ibcon#read 3, iclass 24, count 0 2006.173.14:00:01.51#ibcon#about to read 4, iclass 24, count 0 2006.173.14:00:01.51#ibcon#read 4, iclass 24, count 0 2006.173.14:00:01.51#ibcon#about to read 5, iclass 24, count 0 2006.173.14:00:01.51#ibcon#read 5, iclass 24, count 0 2006.173.14:00:01.51#ibcon#about to read 6, iclass 24, count 0 2006.173.14:00:01.51#ibcon#read 6, iclass 24, count 0 2006.173.14:00:01.51#ibcon#end of sib2, iclass 24, count 0 2006.173.14:00:01.51#ibcon#*mode == 0, iclass 24, count 0 2006.173.14:00:01.51#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.14:00:01.51#ibcon#[25=USB\r\n] 2006.173.14:00:01.51#ibcon#*before write, iclass 24, count 0 2006.173.14:00:01.51#ibcon#enter sib2, iclass 24, count 0 2006.173.14:00:01.51#ibcon#flushed, iclass 24, count 0 2006.173.14:00:01.51#ibcon#about to write, iclass 24, count 0 2006.173.14:00:01.51#ibcon#wrote, iclass 24, count 0 2006.173.14:00:01.51#ibcon#about to read 3, iclass 24, count 0 2006.173.14:00:01.54#ibcon#read 3, iclass 24, count 0 2006.173.14:00:01.54#ibcon#about to read 4, iclass 24, count 0 2006.173.14:00:01.54#ibcon#read 4, iclass 24, count 0 2006.173.14:00:01.54#ibcon#about to read 5, iclass 24, count 0 2006.173.14:00:01.54#ibcon#read 5, iclass 24, count 0 2006.173.14:00:01.54#ibcon#about to read 6, iclass 24, count 0 2006.173.14:00:01.54#ibcon#read 6, iclass 24, count 0 2006.173.14:00:01.54#ibcon#end of sib2, iclass 24, count 0 2006.173.14:00:01.54#ibcon#*after write, iclass 24, count 0 2006.173.14:00:01.54#ibcon#*before return 0, iclass 24, count 0 2006.173.14:00:01.54#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.14:00:01.54#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.14:00:01.54#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.14:00:01.54#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.14:00:01.54$vck44/valo=2,534.99 2006.173.14:00:01.54#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.14:00:01.54#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.14:00:01.54#ibcon#ireg 17 cls_cnt 0 2006.173.14:00:01.54#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.14:00:01.54#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.14:00:01.54#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.14:00:01.54#ibcon#enter wrdev, iclass 26, count 0 2006.173.14:00:01.54#ibcon#first serial, iclass 26, count 0 2006.173.14:00:01.54#ibcon#enter sib2, iclass 26, count 0 2006.173.14:00:01.54#ibcon#flushed, iclass 26, count 0 2006.173.14:00:01.54#ibcon#about to write, iclass 26, count 0 2006.173.14:00:01.54#ibcon#wrote, iclass 26, count 0 2006.173.14:00:01.54#ibcon#about to read 3, iclass 26, count 0 2006.173.14:00:01.56#ibcon#read 3, iclass 26, count 0 2006.173.14:00:01.56#ibcon#about to read 4, iclass 26, count 0 2006.173.14:00:01.56#ibcon#read 4, iclass 26, count 0 2006.173.14:00:01.56#ibcon#about to read 5, iclass 26, count 0 2006.173.14:00:01.56#ibcon#read 5, iclass 26, count 0 2006.173.14:00:01.56#ibcon#about to read 6, iclass 26, count 0 2006.173.14:00:01.56#ibcon#read 6, iclass 26, count 0 2006.173.14:00:01.56#ibcon#end of sib2, iclass 26, count 0 2006.173.14:00:01.56#ibcon#*mode == 0, iclass 26, count 0 2006.173.14:00:01.56#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.14:00:01.56#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.14:00:01.56#ibcon#*before write, iclass 26, count 0 2006.173.14:00:01.56#ibcon#enter sib2, iclass 26, count 0 2006.173.14:00:01.56#ibcon#flushed, iclass 26, count 0 2006.173.14:00:01.56#ibcon#about to write, iclass 26, count 0 2006.173.14:00:01.56#ibcon#wrote, iclass 26, count 0 2006.173.14:00:01.56#ibcon#about to read 3, iclass 26, count 0 2006.173.14:00:01.60#ibcon#read 3, iclass 26, count 0 2006.173.14:00:01.60#ibcon#about to read 4, iclass 26, count 0 2006.173.14:00:01.60#ibcon#read 4, iclass 26, count 0 2006.173.14:00:01.60#ibcon#about to read 5, iclass 26, count 0 2006.173.14:00:01.60#ibcon#read 5, iclass 26, count 0 2006.173.14:00:01.60#ibcon#about to read 6, iclass 26, count 0 2006.173.14:00:01.60#ibcon#read 6, iclass 26, count 0 2006.173.14:00:01.60#ibcon#end of sib2, iclass 26, count 0 2006.173.14:00:01.60#ibcon#*after write, iclass 26, count 0 2006.173.14:00:01.60#ibcon#*before return 0, iclass 26, count 0 2006.173.14:00:01.60#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.14:00:01.60#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.14:00:01.60#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.14:00:01.60#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.14:00:01.60$vck44/va=2,6 2006.173.14:00:01.60#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.14:00:01.60#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.14:00:01.60#ibcon#ireg 11 cls_cnt 2 2006.173.14:00:01.60#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.14:00:01.66#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.14:00:01.66#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.14:00:01.66#ibcon#enter wrdev, iclass 28, count 2 2006.173.14:00:01.66#ibcon#first serial, iclass 28, count 2 2006.173.14:00:01.66#ibcon#enter sib2, iclass 28, count 2 2006.173.14:00:01.66#ibcon#flushed, iclass 28, count 2 2006.173.14:00:01.66#ibcon#about to write, iclass 28, count 2 2006.173.14:00:01.66#ibcon#wrote, iclass 28, count 2 2006.173.14:00:01.66#ibcon#about to read 3, iclass 28, count 2 2006.173.14:00:01.68#ibcon#read 3, iclass 28, count 2 2006.173.14:00:01.68#ibcon#about to read 4, iclass 28, count 2 2006.173.14:00:01.68#ibcon#read 4, iclass 28, count 2 2006.173.14:00:01.68#ibcon#about to read 5, iclass 28, count 2 2006.173.14:00:01.68#ibcon#read 5, iclass 28, count 2 2006.173.14:00:01.68#ibcon#about to read 6, iclass 28, count 2 2006.173.14:00:01.68#ibcon#read 6, iclass 28, count 2 2006.173.14:00:01.68#ibcon#end of sib2, iclass 28, count 2 2006.173.14:00:01.68#ibcon#*mode == 0, iclass 28, count 2 2006.173.14:00:01.68#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.14:00:01.68#ibcon#[25=AT02-06\r\n] 2006.173.14:00:01.68#ibcon#*before write, iclass 28, count 2 2006.173.14:00:01.68#ibcon#enter sib2, iclass 28, count 2 2006.173.14:00:01.68#ibcon#flushed, iclass 28, count 2 2006.173.14:00:01.68#ibcon#about to write, iclass 28, count 2 2006.173.14:00:01.68#ibcon#wrote, iclass 28, count 2 2006.173.14:00:01.68#ibcon#about to read 3, iclass 28, count 2 2006.173.14:00:01.71#ibcon#read 3, iclass 28, count 2 2006.173.14:00:01.71#ibcon#about to read 4, iclass 28, count 2 2006.173.14:00:01.71#ibcon#read 4, iclass 28, count 2 2006.173.14:00:01.71#ibcon#about to read 5, iclass 28, count 2 2006.173.14:00:01.71#ibcon#read 5, iclass 28, count 2 2006.173.14:00:01.71#ibcon#about to read 6, iclass 28, count 2 2006.173.14:00:01.71#ibcon#read 6, iclass 28, count 2 2006.173.14:00:01.71#ibcon#end of sib2, iclass 28, count 2 2006.173.14:00:01.71#ibcon#*after write, iclass 28, count 2 2006.173.14:00:01.71#ibcon#*before return 0, iclass 28, count 2 2006.173.14:00:01.71#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.14:00:01.71#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.14:00:01.71#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.14:00:01.71#ibcon#ireg 7 cls_cnt 0 2006.173.14:00:01.71#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.14:00:01.83#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.14:00:01.83#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.14:00:01.83#ibcon#enter wrdev, iclass 28, count 0 2006.173.14:00:01.83#ibcon#first serial, iclass 28, count 0 2006.173.14:00:01.83#ibcon#enter sib2, iclass 28, count 0 2006.173.14:00:01.83#ibcon#flushed, iclass 28, count 0 2006.173.14:00:01.83#ibcon#about to write, iclass 28, count 0 2006.173.14:00:01.83#ibcon#wrote, iclass 28, count 0 2006.173.14:00:01.83#ibcon#about to read 3, iclass 28, count 0 2006.173.14:00:01.85#ibcon#read 3, iclass 28, count 0 2006.173.14:00:01.85#ibcon#about to read 4, iclass 28, count 0 2006.173.14:00:01.85#ibcon#read 4, iclass 28, count 0 2006.173.14:00:01.85#ibcon#about to read 5, iclass 28, count 0 2006.173.14:00:01.85#ibcon#read 5, iclass 28, count 0 2006.173.14:00:01.85#ibcon#about to read 6, iclass 28, count 0 2006.173.14:00:01.85#ibcon#read 6, iclass 28, count 0 2006.173.14:00:01.85#ibcon#end of sib2, iclass 28, count 0 2006.173.14:00:01.85#ibcon#*mode == 0, iclass 28, count 0 2006.173.14:00:01.85#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.14:00:01.85#ibcon#[25=USB\r\n] 2006.173.14:00:01.85#ibcon#*before write, iclass 28, count 0 2006.173.14:00:01.85#ibcon#enter sib2, iclass 28, count 0 2006.173.14:00:01.85#ibcon#flushed, iclass 28, count 0 2006.173.14:00:01.85#ibcon#about to write, iclass 28, count 0 2006.173.14:00:01.85#ibcon#wrote, iclass 28, count 0 2006.173.14:00:01.85#ibcon#about to read 3, iclass 28, count 0 2006.173.14:00:01.88#ibcon#read 3, iclass 28, count 0 2006.173.14:00:01.88#ibcon#about to read 4, iclass 28, count 0 2006.173.14:00:01.88#ibcon#read 4, iclass 28, count 0 2006.173.14:00:01.88#ibcon#about to read 5, iclass 28, count 0 2006.173.14:00:01.88#ibcon#read 5, iclass 28, count 0 2006.173.14:00:01.88#ibcon#about to read 6, iclass 28, count 0 2006.173.14:00:01.88#ibcon#read 6, iclass 28, count 0 2006.173.14:00:01.88#ibcon#end of sib2, iclass 28, count 0 2006.173.14:00:01.88#ibcon#*after write, iclass 28, count 0 2006.173.14:00:01.88#ibcon#*before return 0, iclass 28, count 0 2006.173.14:00:01.88#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.14:00:01.88#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.14:00:01.88#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.14:00:01.88#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.14:00:01.88$vck44/valo=3,564.99 2006.173.14:00:01.88#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.14:00:01.88#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.14:00:01.88#ibcon#ireg 17 cls_cnt 0 2006.173.14:00:01.88#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.14:00:01.88#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.14:00:01.88#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.14:00:01.88#ibcon#enter wrdev, iclass 30, count 0 2006.173.14:00:01.88#ibcon#first serial, iclass 30, count 0 2006.173.14:00:01.88#ibcon#enter sib2, iclass 30, count 0 2006.173.14:00:01.88#ibcon#flushed, iclass 30, count 0 2006.173.14:00:01.88#ibcon#about to write, iclass 30, count 0 2006.173.14:00:01.88#ibcon#wrote, iclass 30, count 0 2006.173.14:00:01.88#ibcon#about to read 3, iclass 30, count 0 2006.173.14:00:01.90#ibcon#read 3, iclass 30, count 0 2006.173.14:00:01.90#ibcon#about to read 4, iclass 30, count 0 2006.173.14:00:01.90#ibcon#read 4, iclass 30, count 0 2006.173.14:00:01.90#ibcon#about to read 5, iclass 30, count 0 2006.173.14:00:01.90#ibcon#read 5, iclass 30, count 0 2006.173.14:00:01.90#ibcon#about to read 6, iclass 30, count 0 2006.173.14:00:01.90#ibcon#read 6, iclass 30, count 0 2006.173.14:00:01.90#ibcon#end of sib2, iclass 30, count 0 2006.173.14:00:01.90#ibcon#*mode == 0, iclass 30, count 0 2006.173.14:00:01.90#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.14:00:01.90#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.14:00:01.90#ibcon#*before write, iclass 30, count 0 2006.173.14:00:01.90#ibcon#enter sib2, iclass 30, count 0 2006.173.14:00:01.90#ibcon#flushed, iclass 30, count 0 2006.173.14:00:01.90#ibcon#about to write, iclass 30, count 0 2006.173.14:00:01.90#ibcon#wrote, iclass 30, count 0 2006.173.14:00:01.90#ibcon#about to read 3, iclass 30, count 0 2006.173.14:00:01.94#ibcon#read 3, iclass 30, count 0 2006.173.14:00:01.94#ibcon#about to read 4, iclass 30, count 0 2006.173.14:00:01.94#ibcon#read 4, iclass 30, count 0 2006.173.14:00:01.94#ibcon#about to read 5, iclass 30, count 0 2006.173.14:00:01.94#ibcon#read 5, iclass 30, count 0 2006.173.14:00:01.94#ibcon#about to read 6, iclass 30, count 0 2006.173.14:00:01.94#ibcon#read 6, iclass 30, count 0 2006.173.14:00:01.94#ibcon#end of sib2, iclass 30, count 0 2006.173.14:00:01.94#ibcon#*after write, iclass 30, count 0 2006.173.14:00:01.94#ibcon#*before return 0, iclass 30, count 0 2006.173.14:00:01.94#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.14:00:01.94#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.14:00:01.94#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.14:00:01.94#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.14:00:01.94$vck44/va=3,5 2006.173.14:00:01.94#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.173.14:00:01.94#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.173.14:00:01.94#ibcon#ireg 11 cls_cnt 2 2006.173.14:00:01.94#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.14:00:02.00#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.14:00:02.00#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.14:00:02.00#ibcon#enter wrdev, iclass 32, count 2 2006.173.14:00:02.00#ibcon#first serial, iclass 32, count 2 2006.173.14:00:02.00#ibcon#enter sib2, iclass 32, count 2 2006.173.14:00:02.00#ibcon#flushed, iclass 32, count 2 2006.173.14:00:02.00#ibcon#about to write, iclass 32, count 2 2006.173.14:00:02.00#ibcon#wrote, iclass 32, count 2 2006.173.14:00:02.00#ibcon#about to read 3, iclass 32, count 2 2006.173.14:00:02.02#ibcon#read 3, iclass 32, count 2 2006.173.14:00:02.02#ibcon#about to read 4, iclass 32, count 2 2006.173.14:00:02.02#ibcon#read 4, iclass 32, count 2 2006.173.14:00:02.02#ibcon#about to read 5, iclass 32, count 2 2006.173.14:00:02.02#ibcon#read 5, iclass 32, count 2 2006.173.14:00:02.02#ibcon#about to read 6, iclass 32, count 2 2006.173.14:00:02.02#ibcon#read 6, iclass 32, count 2 2006.173.14:00:02.02#ibcon#end of sib2, iclass 32, count 2 2006.173.14:00:02.02#ibcon#*mode == 0, iclass 32, count 2 2006.173.14:00:02.02#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.173.14:00:02.02#ibcon#[25=AT03-05\r\n] 2006.173.14:00:02.02#ibcon#*before write, iclass 32, count 2 2006.173.14:00:02.02#ibcon#enter sib2, iclass 32, count 2 2006.173.14:00:02.02#ibcon#flushed, iclass 32, count 2 2006.173.14:00:02.02#ibcon#about to write, iclass 32, count 2 2006.173.14:00:02.02#ibcon#wrote, iclass 32, count 2 2006.173.14:00:02.02#ibcon#about to read 3, iclass 32, count 2 2006.173.14:00:02.05#ibcon#read 3, iclass 32, count 2 2006.173.14:00:02.05#ibcon#about to read 4, iclass 32, count 2 2006.173.14:00:02.05#ibcon#read 4, iclass 32, count 2 2006.173.14:00:02.05#ibcon#about to read 5, iclass 32, count 2 2006.173.14:00:02.05#ibcon#read 5, iclass 32, count 2 2006.173.14:00:02.05#ibcon#about to read 6, iclass 32, count 2 2006.173.14:00:02.05#ibcon#read 6, iclass 32, count 2 2006.173.14:00:02.05#ibcon#end of sib2, iclass 32, count 2 2006.173.14:00:02.05#ibcon#*after write, iclass 32, count 2 2006.173.14:00:02.05#ibcon#*before return 0, iclass 32, count 2 2006.173.14:00:02.05#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.14:00:02.05#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.173.14:00:02.05#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.173.14:00:02.05#ibcon#ireg 7 cls_cnt 0 2006.173.14:00:02.05#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.14:00:02.17#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.14:00:02.17#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.14:00:02.17#ibcon#enter wrdev, iclass 32, count 0 2006.173.14:00:02.17#ibcon#first serial, iclass 32, count 0 2006.173.14:00:02.17#ibcon#enter sib2, iclass 32, count 0 2006.173.14:00:02.17#ibcon#flushed, iclass 32, count 0 2006.173.14:00:02.17#ibcon#about to write, iclass 32, count 0 2006.173.14:00:02.17#ibcon#wrote, iclass 32, count 0 2006.173.14:00:02.17#ibcon#about to read 3, iclass 32, count 0 2006.173.14:00:02.19#ibcon#read 3, iclass 32, count 0 2006.173.14:00:02.19#ibcon#about to read 4, iclass 32, count 0 2006.173.14:00:02.19#ibcon#read 4, iclass 32, count 0 2006.173.14:00:02.19#ibcon#about to read 5, iclass 32, count 0 2006.173.14:00:02.19#ibcon#read 5, iclass 32, count 0 2006.173.14:00:02.19#ibcon#about to read 6, iclass 32, count 0 2006.173.14:00:02.19#ibcon#read 6, iclass 32, count 0 2006.173.14:00:02.19#ibcon#end of sib2, iclass 32, count 0 2006.173.14:00:02.19#ibcon#*mode == 0, iclass 32, count 0 2006.173.14:00:02.19#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.14:00:02.19#ibcon#[25=USB\r\n] 2006.173.14:00:02.19#ibcon#*before write, iclass 32, count 0 2006.173.14:00:02.19#ibcon#enter sib2, iclass 32, count 0 2006.173.14:00:02.19#ibcon#flushed, iclass 32, count 0 2006.173.14:00:02.19#ibcon#about to write, iclass 32, count 0 2006.173.14:00:02.19#ibcon#wrote, iclass 32, count 0 2006.173.14:00:02.19#ibcon#about to read 3, iclass 32, count 0 2006.173.14:00:02.22#ibcon#read 3, iclass 32, count 0 2006.173.14:00:02.22#ibcon#about to read 4, iclass 32, count 0 2006.173.14:00:02.22#ibcon#read 4, iclass 32, count 0 2006.173.14:00:02.22#ibcon#about to read 5, iclass 32, count 0 2006.173.14:00:02.22#ibcon#read 5, iclass 32, count 0 2006.173.14:00:02.22#ibcon#about to read 6, iclass 32, count 0 2006.173.14:00:02.22#ibcon#read 6, iclass 32, count 0 2006.173.14:00:02.22#ibcon#end of sib2, iclass 32, count 0 2006.173.14:00:02.22#ibcon#*after write, iclass 32, count 0 2006.173.14:00:02.22#ibcon#*before return 0, iclass 32, count 0 2006.173.14:00:02.22#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.14:00:02.22#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.173.14:00:02.22#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.14:00:02.22#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.14:00:02.22$vck44/valo=4,624.99 2006.173.14:00:02.22#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.14:00:02.22#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.14:00:02.22#ibcon#ireg 17 cls_cnt 0 2006.173.14:00:02.22#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.14:00:02.22#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.14:00:02.22#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.14:00:02.22#ibcon#enter wrdev, iclass 34, count 0 2006.173.14:00:02.22#ibcon#first serial, iclass 34, count 0 2006.173.14:00:02.22#ibcon#enter sib2, iclass 34, count 0 2006.173.14:00:02.22#ibcon#flushed, iclass 34, count 0 2006.173.14:00:02.22#ibcon#about to write, iclass 34, count 0 2006.173.14:00:02.22#ibcon#wrote, iclass 34, count 0 2006.173.14:00:02.22#ibcon#about to read 3, iclass 34, count 0 2006.173.14:00:02.24#ibcon#read 3, iclass 34, count 0 2006.173.14:00:02.24#ibcon#about to read 4, iclass 34, count 0 2006.173.14:00:02.24#ibcon#read 4, iclass 34, count 0 2006.173.14:00:02.24#ibcon#about to read 5, iclass 34, count 0 2006.173.14:00:02.24#ibcon#read 5, iclass 34, count 0 2006.173.14:00:02.24#ibcon#about to read 6, iclass 34, count 0 2006.173.14:00:02.24#ibcon#read 6, iclass 34, count 0 2006.173.14:00:02.24#ibcon#end of sib2, iclass 34, count 0 2006.173.14:00:02.24#ibcon#*mode == 0, iclass 34, count 0 2006.173.14:00:02.24#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.14:00:02.24#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.14:00:02.24#ibcon#*before write, iclass 34, count 0 2006.173.14:00:02.24#ibcon#enter sib2, iclass 34, count 0 2006.173.14:00:02.24#ibcon#flushed, iclass 34, count 0 2006.173.14:00:02.24#ibcon#about to write, iclass 34, count 0 2006.173.14:00:02.24#ibcon#wrote, iclass 34, count 0 2006.173.14:00:02.24#ibcon#about to read 3, iclass 34, count 0 2006.173.14:00:02.28#ibcon#read 3, iclass 34, count 0 2006.173.14:00:02.28#ibcon#about to read 4, iclass 34, count 0 2006.173.14:00:02.28#ibcon#read 4, iclass 34, count 0 2006.173.14:00:02.28#ibcon#about to read 5, iclass 34, count 0 2006.173.14:00:02.28#ibcon#read 5, iclass 34, count 0 2006.173.14:00:02.28#ibcon#about to read 6, iclass 34, count 0 2006.173.14:00:02.28#ibcon#read 6, iclass 34, count 0 2006.173.14:00:02.28#ibcon#end of sib2, iclass 34, count 0 2006.173.14:00:02.28#ibcon#*after write, iclass 34, count 0 2006.173.14:00:02.28#ibcon#*before return 0, iclass 34, count 0 2006.173.14:00:02.28#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.14:00:02.28#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.14:00:02.28#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.14:00:02.28#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.14:00:02.28$vck44/va=4,6 2006.173.14:00:02.28#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.14:00:02.28#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.14:00:02.28#ibcon#ireg 11 cls_cnt 2 2006.173.14:00:02.28#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.14:00:02.34#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.14:00:02.34#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.14:00:02.34#ibcon#enter wrdev, iclass 36, count 2 2006.173.14:00:02.34#ibcon#first serial, iclass 36, count 2 2006.173.14:00:02.34#ibcon#enter sib2, iclass 36, count 2 2006.173.14:00:02.34#ibcon#flushed, iclass 36, count 2 2006.173.14:00:02.34#ibcon#about to write, iclass 36, count 2 2006.173.14:00:02.34#ibcon#wrote, iclass 36, count 2 2006.173.14:00:02.34#ibcon#about to read 3, iclass 36, count 2 2006.173.14:00:02.36#ibcon#read 3, iclass 36, count 2 2006.173.14:00:02.36#ibcon#about to read 4, iclass 36, count 2 2006.173.14:00:02.36#ibcon#read 4, iclass 36, count 2 2006.173.14:00:02.36#ibcon#about to read 5, iclass 36, count 2 2006.173.14:00:02.36#ibcon#read 5, iclass 36, count 2 2006.173.14:00:02.36#ibcon#about to read 6, iclass 36, count 2 2006.173.14:00:02.36#ibcon#read 6, iclass 36, count 2 2006.173.14:00:02.36#ibcon#end of sib2, iclass 36, count 2 2006.173.14:00:02.36#ibcon#*mode == 0, iclass 36, count 2 2006.173.14:00:02.36#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.14:00:02.36#ibcon#[25=AT04-06\r\n] 2006.173.14:00:02.36#ibcon#*before write, iclass 36, count 2 2006.173.14:00:02.36#ibcon#enter sib2, iclass 36, count 2 2006.173.14:00:02.36#ibcon#flushed, iclass 36, count 2 2006.173.14:00:02.36#ibcon#about to write, iclass 36, count 2 2006.173.14:00:02.36#ibcon#wrote, iclass 36, count 2 2006.173.14:00:02.36#ibcon#about to read 3, iclass 36, count 2 2006.173.14:00:02.39#abcon#<5=/04 0.7 1.4 21.771001003.7\r\n> 2006.173.14:00:02.39#ibcon#read 3, iclass 36, count 2 2006.173.14:00:02.39#ibcon#about to read 4, iclass 36, count 2 2006.173.14:00:02.39#ibcon#read 4, iclass 36, count 2 2006.173.14:00:02.39#ibcon#about to read 5, iclass 36, count 2 2006.173.14:00:02.39#ibcon#read 5, iclass 36, count 2 2006.173.14:00:02.39#ibcon#about to read 6, iclass 36, count 2 2006.173.14:00:02.39#ibcon#read 6, iclass 36, count 2 2006.173.14:00:02.39#ibcon#end of sib2, iclass 36, count 2 2006.173.14:00:02.39#ibcon#*after write, iclass 36, count 2 2006.173.14:00:02.39#ibcon#*before return 0, iclass 36, count 2 2006.173.14:00:02.39#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.14:00:02.39#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.14:00:02.39#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.14:00:02.39#ibcon#ireg 7 cls_cnt 0 2006.173.14:00:02.39#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.14:00:02.41#abcon#{5=INTERFACE CLEAR} 2006.173.14:00:02.47#abcon#[5=S1D000X0/0*\r\n] 2006.173.14:00:02.51#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.14:00:02.51#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.14:00:02.51#ibcon#enter wrdev, iclass 36, count 0 2006.173.14:00:02.51#ibcon#first serial, iclass 36, count 0 2006.173.14:00:02.51#ibcon#enter sib2, iclass 36, count 0 2006.173.14:00:02.51#ibcon#flushed, iclass 36, count 0 2006.173.14:00:02.51#ibcon#about to write, iclass 36, count 0 2006.173.14:00:02.51#ibcon#wrote, iclass 36, count 0 2006.173.14:00:02.51#ibcon#about to read 3, iclass 36, count 0 2006.173.14:00:02.53#ibcon#read 3, iclass 36, count 0 2006.173.14:00:02.53#ibcon#about to read 4, iclass 36, count 0 2006.173.14:00:02.53#ibcon#read 4, iclass 36, count 0 2006.173.14:00:02.53#ibcon#about to read 5, iclass 36, count 0 2006.173.14:00:02.53#ibcon#read 5, iclass 36, count 0 2006.173.14:00:02.53#ibcon#about to read 6, iclass 36, count 0 2006.173.14:00:02.53#ibcon#read 6, iclass 36, count 0 2006.173.14:00:02.53#ibcon#end of sib2, iclass 36, count 0 2006.173.14:00:02.53#ibcon#*mode == 0, iclass 36, count 0 2006.173.14:00:02.53#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.14:00:02.53#ibcon#[25=USB\r\n] 2006.173.14:00:02.53#ibcon#*before write, iclass 36, count 0 2006.173.14:00:02.53#ibcon#enter sib2, iclass 36, count 0 2006.173.14:00:02.53#ibcon#flushed, iclass 36, count 0 2006.173.14:00:02.53#ibcon#about to write, iclass 36, count 0 2006.173.14:00:02.53#ibcon#wrote, iclass 36, count 0 2006.173.14:00:02.53#ibcon#about to read 3, iclass 36, count 0 2006.173.14:00:02.56#ibcon#read 3, iclass 36, count 0 2006.173.14:00:02.56#ibcon#about to read 4, iclass 36, count 0 2006.173.14:00:02.56#ibcon#read 4, iclass 36, count 0 2006.173.14:00:02.56#ibcon#about to read 5, iclass 36, count 0 2006.173.14:00:02.56#ibcon#read 5, iclass 36, count 0 2006.173.14:00:02.56#ibcon#about to read 6, iclass 36, count 0 2006.173.14:00:02.56#ibcon#read 6, iclass 36, count 0 2006.173.14:00:02.56#ibcon#end of sib2, iclass 36, count 0 2006.173.14:00:02.56#ibcon#*after write, iclass 36, count 0 2006.173.14:00:02.56#ibcon#*before return 0, iclass 36, count 0 2006.173.14:00:02.56#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.14:00:02.56#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.14:00:02.56#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.14:00:02.56#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.14:00:02.56$vck44/valo=5,734.99 2006.173.14:00:02.56#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.14:00:02.56#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.14:00:02.56#ibcon#ireg 17 cls_cnt 0 2006.173.14:00:02.56#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.14:00:02.56#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.14:00:02.56#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.14:00:02.56#ibcon#enter wrdev, iclass 4, count 0 2006.173.14:00:02.56#ibcon#first serial, iclass 4, count 0 2006.173.14:00:02.56#ibcon#enter sib2, iclass 4, count 0 2006.173.14:00:02.56#ibcon#flushed, iclass 4, count 0 2006.173.14:00:02.56#ibcon#about to write, iclass 4, count 0 2006.173.14:00:02.56#ibcon#wrote, iclass 4, count 0 2006.173.14:00:02.56#ibcon#about to read 3, iclass 4, count 0 2006.173.14:00:02.58#ibcon#read 3, iclass 4, count 0 2006.173.14:00:02.58#ibcon#about to read 4, iclass 4, count 0 2006.173.14:00:02.58#ibcon#read 4, iclass 4, count 0 2006.173.14:00:02.58#ibcon#about to read 5, iclass 4, count 0 2006.173.14:00:02.58#ibcon#read 5, iclass 4, count 0 2006.173.14:00:02.58#ibcon#about to read 6, iclass 4, count 0 2006.173.14:00:02.58#ibcon#read 6, iclass 4, count 0 2006.173.14:00:02.58#ibcon#end of sib2, iclass 4, count 0 2006.173.14:00:02.58#ibcon#*mode == 0, iclass 4, count 0 2006.173.14:00:02.58#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.14:00:02.58#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.14:00:02.58#ibcon#*before write, iclass 4, count 0 2006.173.14:00:02.58#ibcon#enter sib2, iclass 4, count 0 2006.173.14:00:02.58#ibcon#flushed, iclass 4, count 0 2006.173.14:00:02.58#ibcon#about to write, iclass 4, count 0 2006.173.14:00:02.58#ibcon#wrote, iclass 4, count 0 2006.173.14:00:02.58#ibcon#about to read 3, iclass 4, count 0 2006.173.14:00:02.62#ibcon#read 3, iclass 4, count 0 2006.173.14:00:02.62#ibcon#about to read 4, iclass 4, count 0 2006.173.14:00:02.62#ibcon#read 4, iclass 4, count 0 2006.173.14:00:02.62#ibcon#about to read 5, iclass 4, count 0 2006.173.14:00:02.62#ibcon#read 5, iclass 4, count 0 2006.173.14:00:02.62#ibcon#about to read 6, iclass 4, count 0 2006.173.14:00:02.62#ibcon#read 6, iclass 4, count 0 2006.173.14:00:02.62#ibcon#end of sib2, iclass 4, count 0 2006.173.14:00:02.62#ibcon#*after write, iclass 4, count 0 2006.173.14:00:02.62#ibcon#*before return 0, iclass 4, count 0 2006.173.14:00:02.62#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.14:00:02.62#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.14:00:02.62#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.14:00:02.62#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.14:00:02.62$vck44/va=5,4 2006.173.14:00:02.62#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.14:00:02.62#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.14:00:02.62#ibcon#ireg 11 cls_cnt 2 2006.173.14:00:02.62#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.14:00:02.68#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.14:00:02.68#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.14:00:02.68#ibcon#enter wrdev, iclass 6, count 2 2006.173.14:00:02.68#ibcon#first serial, iclass 6, count 2 2006.173.14:00:02.68#ibcon#enter sib2, iclass 6, count 2 2006.173.14:00:02.68#ibcon#flushed, iclass 6, count 2 2006.173.14:00:02.68#ibcon#about to write, iclass 6, count 2 2006.173.14:00:02.68#ibcon#wrote, iclass 6, count 2 2006.173.14:00:02.68#ibcon#about to read 3, iclass 6, count 2 2006.173.14:00:02.70#ibcon#read 3, iclass 6, count 2 2006.173.14:00:02.70#ibcon#about to read 4, iclass 6, count 2 2006.173.14:00:02.70#ibcon#read 4, iclass 6, count 2 2006.173.14:00:02.70#ibcon#about to read 5, iclass 6, count 2 2006.173.14:00:02.70#ibcon#read 5, iclass 6, count 2 2006.173.14:00:02.70#ibcon#about to read 6, iclass 6, count 2 2006.173.14:00:02.70#ibcon#read 6, iclass 6, count 2 2006.173.14:00:02.70#ibcon#end of sib2, iclass 6, count 2 2006.173.14:00:02.70#ibcon#*mode == 0, iclass 6, count 2 2006.173.14:00:02.70#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.14:00:02.70#ibcon#[25=AT05-04\r\n] 2006.173.14:00:02.70#ibcon#*before write, iclass 6, count 2 2006.173.14:00:02.70#ibcon#enter sib2, iclass 6, count 2 2006.173.14:00:02.70#ibcon#flushed, iclass 6, count 2 2006.173.14:00:02.70#ibcon#about to write, iclass 6, count 2 2006.173.14:00:02.70#ibcon#wrote, iclass 6, count 2 2006.173.14:00:02.70#ibcon#about to read 3, iclass 6, count 2 2006.173.14:00:02.73#ibcon#read 3, iclass 6, count 2 2006.173.14:00:02.73#ibcon#about to read 4, iclass 6, count 2 2006.173.14:00:02.73#ibcon#read 4, iclass 6, count 2 2006.173.14:00:02.73#ibcon#about to read 5, iclass 6, count 2 2006.173.14:00:02.73#ibcon#read 5, iclass 6, count 2 2006.173.14:00:02.73#ibcon#about to read 6, iclass 6, count 2 2006.173.14:00:02.73#ibcon#read 6, iclass 6, count 2 2006.173.14:00:02.73#ibcon#end of sib2, iclass 6, count 2 2006.173.14:00:02.73#ibcon#*after write, iclass 6, count 2 2006.173.14:00:02.73#ibcon#*before return 0, iclass 6, count 2 2006.173.14:00:02.73#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.14:00:02.73#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.14:00:02.73#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.14:00:02.73#ibcon#ireg 7 cls_cnt 0 2006.173.14:00:02.73#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.14:00:02.85#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.14:00:02.85#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.14:00:02.85#ibcon#enter wrdev, iclass 6, count 0 2006.173.14:00:02.85#ibcon#first serial, iclass 6, count 0 2006.173.14:00:02.85#ibcon#enter sib2, iclass 6, count 0 2006.173.14:00:02.85#ibcon#flushed, iclass 6, count 0 2006.173.14:00:02.85#ibcon#about to write, iclass 6, count 0 2006.173.14:00:02.85#ibcon#wrote, iclass 6, count 0 2006.173.14:00:02.85#ibcon#about to read 3, iclass 6, count 0 2006.173.14:00:02.87#ibcon#read 3, iclass 6, count 0 2006.173.14:00:02.87#ibcon#about to read 4, iclass 6, count 0 2006.173.14:00:02.87#ibcon#read 4, iclass 6, count 0 2006.173.14:00:02.87#ibcon#about to read 5, iclass 6, count 0 2006.173.14:00:02.87#ibcon#read 5, iclass 6, count 0 2006.173.14:00:02.87#ibcon#about to read 6, iclass 6, count 0 2006.173.14:00:02.87#ibcon#read 6, iclass 6, count 0 2006.173.14:00:02.87#ibcon#end of sib2, iclass 6, count 0 2006.173.14:00:02.87#ibcon#*mode == 0, iclass 6, count 0 2006.173.14:00:02.87#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.14:00:02.87#ibcon#[25=USB\r\n] 2006.173.14:00:02.87#ibcon#*before write, iclass 6, count 0 2006.173.14:00:02.87#ibcon#enter sib2, iclass 6, count 0 2006.173.14:00:02.87#ibcon#flushed, iclass 6, count 0 2006.173.14:00:02.87#ibcon#about to write, iclass 6, count 0 2006.173.14:00:02.87#ibcon#wrote, iclass 6, count 0 2006.173.14:00:02.87#ibcon#about to read 3, iclass 6, count 0 2006.173.14:00:02.90#ibcon#read 3, iclass 6, count 0 2006.173.14:00:02.90#ibcon#about to read 4, iclass 6, count 0 2006.173.14:00:02.90#ibcon#read 4, iclass 6, count 0 2006.173.14:00:02.90#ibcon#about to read 5, iclass 6, count 0 2006.173.14:00:02.90#ibcon#read 5, iclass 6, count 0 2006.173.14:00:02.90#ibcon#about to read 6, iclass 6, count 0 2006.173.14:00:02.90#ibcon#read 6, iclass 6, count 0 2006.173.14:00:02.90#ibcon#end of sib2, iclass 6, count 0 2006.173.14:00:02.90#ibcon#*after write, iclass 6, count 0 2006.173.14:00:02.90#ibcon#*before return 0, iclass 6, count 0 2006.173.14:00:02.90#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.14:00:02.90#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.14:00:02.90#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.14:00:02.90#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.14:00:02.90$vck44/valo=6,814.99 2006.173.14:00:02.90#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.14:00:02.90#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.14:00:02.90#ibcon#ireg 17 cls_cnt 0 2006.173.14:00:02.90#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.14:00:02.90#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.14:00:02.90#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.14:00:02.90#ibcon#enter wrdev, iclass 10, count 0 2006.173.14:00:02.90#ibcon#first serial, iclass 10, count 0 2006.173.14:00:02.90#ibcon#enter sib2, iclass 10, count 0 2006.173.14:00:02.90#ibcon#flushed, iclass 10, count 0 2006.173.14:00:02.90#ibcon#about to write, iclass 10, count 0 2006.173.14:00:02.90#ibcon#wrote, iclass 10, count 0 2006.173.14:00:02.90#ibcon#about to read 3, iclass 10, count 0 2006.173.14:00:02.92#ibcon#read 3, iclass 10, count 0 2006.173.14:00:02.92#ibcon#about to read 4, iclass 10, count 0 2006.173.14:00:02.92#ibcon#read 4, iclass 10, count 0 2006.173.14:00:02.92#ibcon#about to read 5, iclass 10, count 0 2006.173.14:00:02.92#ibcon#read 5, iclass 10, count 0 2006.173.14:00:02.92#ibcon#about to read 6, iclass 10, count 0 2006.173.14:00:02.92#ibcon#read 6, iclass 10, count 0 2006.173.14:00:02.92#ibcon#end of sib2, iclass 10, count 0 2006.173.14:00:02.92#ibcon#*mode == 0, iclass 10, count 0 2006.173.14:00:02.92#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.14:00:02.92#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.14:00:02.92#ibcon#*before write, iclass 10, count 0 2006.173.14:00:02.92#ibcon#enter sib2, iclass 10, count 0 2006.173.14:00:02.92#ibcon#flushed, iclass 10, count 0 2006.173.14:00:02.92#ibcon#about to write, iclass 10, count 0 2006.173.14:00:02.92#ibcon#wrote, iclass 10, count 0 2006.173.14:00:02.92#ibcon#about to read 3, iclass 10, count 0 2006.173.14:00:02.96#ibcon#read 3, iclass 10, count 0 2006.173.14:00:02.96#ibcon#about to read 4, iclass 10, count 0 2006.173.14:00:02.96#ibcon#read 4, iclass 10, count 0 2006.173.14:00:02.96#ibcon#about to read 5, iclass 10, count 0 2006.173.14:00:02.96#ibcon#read 5, iclass 10, count 0 2006.173.14:00:02.96#ibcon#about to read 6, iclass 10, count 0 2006.173.14:00:02.96#ibcon#read 6, iclass 10, count 0 2006.173.14:00:02.96#ibcon#end of sib2, iclass 10, count 0 2006.173.14:00:02.96#ibcon#*after write, iclass 10, count 0 2006.173.14:00:02.96#ibcon#*before return 0, iclass 10, count 0 2006.173.14:00:02.96#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.14:00:02.96#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.14:00:02.96#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.14:00:02.96#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.14:00:02.96$vck44/va=6,3 2006.173.14:00:02.96#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.14:00:02.96#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.14:00:02.96#ibcon#ireg 11 cls_cnt 2 2006.173.14:00:02.96#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.14:00:03.02#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.14:00:03.02#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.14:00:03.02#ibcon#enter wrdev, iclass 12, count 2 2006.173.14:00:03.02#ibcon#first serial, iclass 12, count 2 2006.173.14:00:03.02#ibcon#enter sib2, iclass 12, count 2 2006.173.14:00:03.02#ibcon#flushed, iclass 12, count 2 2006.173.14:00:03.02#ibcon#about to write, iclass 12, count 2 2006.173.14:00:03.02#ibcon#wrote, iclass 12, count 2 2006.173.14:00:03.02#ibcon#about to read 3, iclass 12, count 2 2006.173.14:00:03.04#ibcon#read 3, iclass 12, count 2 2006.173.14:00:03.04#ibcon#about to read 4, iclass 12, count 2 2006.173.14:00:03.04#ibcon#read 4, iclass 12, count 2 2006.173.14:00:03.04#ibcon#about to read 5, iclass 12, count 2 2006.173.14:00:03.04#ibcon#read 5, iclass 12, count 2 2006.173.14:00:03.04#ibcon#about to read 6, iclass 12, count 2 2006.173.14:00:03.04#ibcon#read 6, iclass 12, count 2 2006.173.14:00:03.04#ibcon#end of sib2, iclass 12, count 2 2006.173.14:00:03.04#ibcon#*mode == 0, iclass 12, count 2 2006.173.14:00:03.04#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.14:00:03.04#ibcon#[25=AT06-03\r\n] 2006.173.14:00:03.04#ibcon#*before write, iclass 12, count 2 2006.173.14:00:03.04#ibcon#enter sib2, iclass 12, count 2 2006.173.14:00:03.04#ibcon#flushed, iclass 12, count 2 2006.173.14:00:03.04#ibcon#about to write, iclass 12, count 2 2006.173.14:00:03.04#ibcon#wrote, iclass 12, count 2 2006.173.14:00:03.04#ibcon#about to read 3, iclass 12, count 2 2006.173.14:00:03.07#ibcon#read 3, iclass 12, count 2 2006.173.14:00:03.07#ibcon#about to read 4, iclass 12, count 2 2006.173.14:00:03.07#ibcon#read 4, iclass 12, count 2 2006.173.14:00:03.07#ibcon#about to read 5, iclass 12, count 2 2006.173.14:00:03.07#ibcon#read 5, iclass 12, count 2 2006.173.14:00:03.07#ibcon#about to read 6, iclass 12, count 2 2006.173.14:00:03.07#ibcon#read 6, iclass 12, count 2 2006.173.14:00:03.07#ibcon#end of sib2, iclass 12, count 2 2006.173.14:00:03.07#ibcon#*after write, iclass 12, count 2 2006.173.14:00:03.07#ibcon#*before return 0, iclass 12, count 2 2006.173.14:00:03.07#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.14:00:03.07#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.14:00:03.07#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.14:00:03.07#ibcon#ireg 7 cls_cnt 0 2006.173.14:00:03.07#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.14:00:03.19#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.14:00:03.19#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.14:00:03.19#ibcon#enter wrdev, iclass 12, count 0 2006.173.14:00:03.19#ibcon#first serial, iclass 12, count 0 2006.173.14:00:03.19#ibcon#enter sib2, iclass 12, count 0 2006.173.14:00:03.19#ibcon#flushed, iclass 12, count 0 2006.173.14:00:03.19#ibcon#about to write, iclass 12, count 0 2006.173.14:00:03.19#ibcon#wrote, iclass 12, count 0 2006.173.14:00:03.19#ibcon#about to read 3, iclass 12, count 0 2006.173.14:00:03.21#ibcon#read 3, iclass 12, count 0 2006.173.14:00:03.21#ibcon#about to read 4, iclass 12, count 0 2006.173.14:00:03.21#ibcon#read 4, iclass 12, count 0 2006.173.14:00:03.21#ibcon#about to read 5, iclass 12, count 0 2006.173.14:00:03.21#ibcon#read 5, iclass 12, count 0 2006.173.14:00:03.21#ibcon#about to read 6, iclass 12, count 0 2006.173.14:00:03.21#ibcon#read 6, iclass 12, count 0 2006.173.14:00:03.21#ibcon#end of sib2, iclass 12, count 0 2006.173.14:00:03.21#ibcon#*mode == 0, iclass 12, count 0 2006.173.14:00:03.21#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.14:00:03.21#ibcon#[25=USB\r\n] 2006.173.14:00:03.21#ibcon#*before write, iclass 12, count 0 2006.173.14:00:03.21#ibcon#enter sib2, iclass 12, count 0 2006.173.14:00:03.21#ibcon#flushed, iclass 12, count 0 2006.173.14:00:03.21#ibcon#about to write, iclass 12, count 0 2006.173.14:00:03.21#ibcon#wrote, iclass 12, count 0 2006.173.14:00:03.21#ibcon#about to read 3, iclass 12, count 0 2006.173.14:00:03.24#ibcon#read 3, iclass 12, count 0 2006.173.14:00:03.24#ibcon#about to read 4, iclass 12, count 0 2006.173.14:00:03.24#ibcon#read 4, iclass 12, count 0 2006.173.14:00:03.24#ibcon#about to read 5, iclass 12, count 0 2006.173.14:00:03.24#ibcon#read 5, iclass 12, count 0 2006.173.14:00:03.24#ibcon#about to read 6, iclass 12, count 0 2006.173.14:00:03.24#ibcon#read 6, iclass 12, count 0 2006.173.14:00:03.24#ibcon#end of sib2, iclass 12, count 0 2006.173.14:00:03.24#ibcon#*after write, iclass 12, count 0 2006.173.14:00:03.24#ibcon#*before return 0, iclass 12, count 0 2006.173.14:00:03.24#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.14:00:03.24#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.14:00:03.24#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.14:00:03.24#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.14:00:03.24$vck44/valo=7,864.99 2006.173.14:00:03.24#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.14:00:03.24#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.14:00:03.24#ibcon#ireg 17 cls_cnt 0 2006.173.14:00:03.24#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.14:00:03.24#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.14:00:03.24#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.14:00:03.24#ibcon#enter wrdev, iclass 14, count 0 2006.173.14:00:03.24#ibcon#first serial, iclass 14, count 0 2006.173.14:00:03.24#ibcon#enter sib2, iclass 14, count 0 2006.173.14:00:03.24#ibcon#flushed, iclass 14, count 0 2006.173.14:00:03.24#ibcon#about to write, iclass 14, count 0 2006.173.14:00:03.24#ibcon#wrote, iclass 14, count 0 2006.173.14:00:03.24#ibcon#about to read 3, iclass 14, count 0 2006.173.14:00:03.26#ibcon#read 3, iclass 14, count 0 2006.173.14:00:03.26#ibcon#about to read 4, iclass 14, count 0 2006.173.14:00:03.26#ibcon#read 4, iclass 14, count 0 2006.173.14:00:03.26#ibcon#about to read 5, iclass 14, count 0 2006.173.14:00:03.26#ibcon#read 5, iclass 14, count 0 2006.173.14:00:03.26#ibcon#about to read 6, iclass 14, count 0 2006.173.14:00:03.26#ibcon#read 6, iclass 14, count 0 2006.173.14:00:03.26#ibcon#end of sib2, iclass 14, count 0 2006.173.14:00:03.26#ibcon#*mode == 0, iclass 14, count 0 2006.173.14:00:03.26#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.14:00:03.26#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.14:00:03.26#ibcon#*before write, iclass 14, count 0 2006.173.14:00:03.26#ibcon#enter sib2, iclass 14, count 0 2006.173.14:00:03.26#ibcon#flushed, iclass 14, count 0 2006.173.14:00:03.26#ibcon#about to write, iclass 14, count 0 2006.173.14:00:03.26#ibcon#wrote, iclass 14, count 0 2006.173.14:00:03.26#ibcon#about to read 3, iclass 14, count 0 2006.173.14:00:03.30#ibcon#read 3, iclass 14, count 0 2006.173.14:00:03.30#ibcon#about to read 4, iclass 14, count 0 2006.173.14:00:03.30#ibcon#read 4, iclass 14, count 0 2006.173.14:00:03.30#ibcon#about to read 5, iclass 14, count 0 2006.173.14:00:03.30#ibcon#read 5, iclass 14, count 0 2006.173.14:00:03.30#ibcon#about to read 6, iclass 14, count 0 2006.173.14:00:03.30#ibcon#read 6, iclass 14, count 0 2006.173.14:00:03.30#ibcon#end of sib2, iclass 14, count 0 2006.173.14:00:03.30#ibcon#*after write, iclass 14, count 0 2006.173.14:00:03.30#ibcon#*before return 0, iclass 14, count 0 2006.173.14:00:03.30#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.14:00:03.30#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.14:00:03.30#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.14:00:03.30#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.14:00:03.30$vck44/va=7,4 2006.173.14:00:03.30#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.14:00:03.30#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.14:00:03.30#ibcon#ireg 11 cls_cnt 2 2006.173.14:00:03.30#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.14:00:03.36#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.14:00:03.36#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.14:00:03.36#ibcon#enter wrdev, iclass 16, count 2 2006.173.14:00:03.36#ibcon#first serial, iclass 16, count 2 2006.173.14:00:03.36#ibcon#enter sib2, iclass 16, count 2 2006.173.14:00:03.36#ibcon#flushed, iclass 16, count 2 2006.173.14:00:03.36#ibcon#about to write, iclass 16, count 2 2006.173.14:00:03.36#ibcon#wrote, iclass 16, count 2 2006.173.14:00:03.36#ibcon#about to read 3, iclass 16, count 2 2006.173.14:00:03.38#ibcon#read 3, iclass 16, count 2 2006.173.14:00:03.38#ibcon#about to read 4, iclass 16, count 2 2006.173.14:00:03.38#ibcon#read 4, iclass 16, count 2 2006.173.14:00:03.38#ibcon#about to read 5, iclass 16, count 2 2006.173.14:00:03.38#ibcon#read 5, iclass 16, count 2 2006.173.14:00:03.38#ibcon#about to read 6, iclass 16, count 2 2006.173.14:00:03.38#ibcon#read 6, iclass 16, count 2 2006.173.14:00:03.38#ibcon#end of sib2, iclass 16, count 2 2006.173.14:00:03.38#ibcon#*mode == 0, iclass 16, count 2 2006.173.14:00:03.38#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.14:00:03.38#ibcon#[25=AT07-04\r\n] 2006.173.14:00:03.38#ibcon#*before write, iclass 16, count 2 2006.173.14:00:03.38#ibcon#enter sib2, iclass 16, count 2 2006.173.14:00:03.38#ibcon#flushed, iclass 16, count 2 2006.173.14:00:03.38#ibcon#about to write, iclass 16, count 2 2006.173.14:00:03.38#ibcon#wrote, iclass 16, count 2 2006.173.14:00:03.38#ibcon#about to read 3, iclass 16, count 2 2006.173.14:00:03.41#ibcon#read 3, iclass 16, count 2 2006.173.14:00:03.41#ibcon#about to read 4, iclass 16, count 2 2006.173.14:00:03.41#ibcon#read 4, iclass 16, count 2 2006.173.14:00:03.41#ibcon#about to read 5, iclass 16, count 2 2006.173.14:00:03.41#ibcon#read 5, iclass 16, count 2 2006.173.14:00:03.41#ibcon#about to read 6, iclass 16, count 2 2006.173.14:00:03.41#ibcon#read 6, iclass 16, count 2 2006.173.14:00:03.41#ibcon#end of sib2, iclass 16, count 2 2006.173.14:00:03.41#ibcon#*after write, iclass 16, count 2 2006.173.14:00:03.41#ibcon#*before return 0, iclass 16, count 2 2006.173.14:00:03.41#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.14:00:03.41#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.14:00:03.41#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.14:00:03.41#ibcon#ireg 7 cls_cnt 0 2006.173.14:00:03.41#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.14:00:03.53#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.14:00:03.53#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.14:00:03.53#ibcon#enter wrdev, iclass 16, count 0 2006.173.14:00:03.53#ibcon#first serial, iclass 16, count 0 2006.173.14:00:03.53#ibcon#enter sib2, iclass 16, count 0 2006.173.14:00:03.53#ibcon#flushed, iclass 16, count 0 2006.173.14:00:03.53#ibcon#about to write, iclass 16, count 0 2006.173.14:00:03.53#ibcon#wrote, iclass 16, count 0 2006.173.14:00:03.53#ibcon#about to read 3, iclass 16, count 0 2006.173.14:00:03.55#ibcon#read 3, iclass 16, count 0 2006.173.14:00:03.55#ibcon#about to read 4, iclass 16, count 0 2006.173.14:00:03.55#ibcon#read 4, iclass 16, count 0 2006.173.14:00:03.55#ibcon#about to read 5, iclass 16, count 0 2006.173.14:00:03.55#ibcon#read 5, iclass 16, count 0 2006.173.14:00:03.55#ibcon#about to read 6, iclass 16, count 0 2006.173.14:00:03.55#ibcon#read 6, iclass 16, count 0 2006.173.14:00:03.55#ibcon#end of sib2, iclass 16, count 0 2006.173.14:00:03.55#ibcon#*mode == 0, iclass 16, count 0 2006.173.14:00:03.55#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.14:00:03.55#ibcon#[25=USB\r\n] 2006.173.14:00:03.55#ibcon#*before write, iclass 16, count 0 2006.173.14:00:03.55#ibcon#enter sib2, iclass 16, count 0 2006.173.14:00:03.55#ibcon#flushed, iclass 16, count 0 2006.173.14:00:03.55#ibcon#about to write, iclass 16, count 0 2006.173.14:00:03.55#ibcon#wrote, iclass 16, count 0 2006.173.14:00:03.55#ibcon#about to read 3, iclass 16, count 0 2006.173.14:00:03.58#ibcon#read 3, iclass 16, count 0 2006.173.14:00:03.58#ibcon#about to read 4, iclass 16, count 0 2006.173.14:00:03.58#ibcon#read 4, iclass 16, count 0 2006.173.14:00:03.58#ibcon#about to read 5, iclass 16, count 0 2006.173.14:00:03.58#ibcon#read 5, iclass 16, count 0 2006.173.14:00:03.58#ibcon#about to read 6, iclass 16, count 0 2006.173.14:00:03.58#ibcon#read 6, iclass 16, count 0 2006.173.14:00:03.58#ibcon#end of sib2, iclass 16, count 0 2006.173.14:00:03.58#ibcon#*after write, iclass 16, count 0 2006.173.14:00:03.58#ibcon#*before return 0, iclass 16, count 0 2006.173.14:00:03.58#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.14:00:03.58#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.14:00:03.58#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.14:00:03.58#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.14:00:03.58$vck44/valo=8,884.99 2006.173.14:00:03.58#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.14:00:03.58#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.14:00:03.58#ibcon#ireg 17 cls_cnt 0 2006.173.14:00:03.58#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.14:00:03.58#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.14:00:03.58#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.14:00:03.58#ibcon#enter wrdev, iclass 18, count 0 2006.173.14:00:03.58#ibcon#first serial, iclass 18, count 0 2006.173.14:00:03.58#ibcon#enter sib2, iclass 18, count 0 2006.173.14:00:03.58#ibcon#flushed, iclass 18, count 0 2006.173.14:00:03.58#ibcon#about to write, iclass 18, count 0 2006.173.14:00:03.58#ibcon#wrote, iclass 18, count 0 2006.173.14:00:03.58#ibcon#about to read 3, iclass 18, count 0 2006.173.14:00:03.60#ibcon#read 3, iclass 18, count 0 2006.173.14:00:03.60#ibcon#about to read 4, iclass 18, count 0 2006.173.14:00:03.60#ibcon#read 4, iclass 18, count 0 2006.173.14:00:03.60#ibcon#about to read 5, iclass 18, count 0 2006.173.14:00:03.60#ibcon#read 5, iclass 18, count 0 2006.173.14:00:03.60#ibcon#about to read 6, iclass 18, count 0 2006.173.14:00:03.60#ibcon#read 6, iclass 18, count 0 2006.173.14:00:03.60#ibcon#end of sib2, iclass 18, count 0 2006.173.14:00:03.60#ibcon#*mode == 0, iclass 18, count 0 2006.173.14:00:03.60#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.14:00:03.60#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.14:00:03.60#ibcon#*before write, iclass 18, count 0 2006.173.14:00:03.60#ibcon#enter sib2, iclass 18, count 0 2006.173.14:00:03.60#ibcon#flushed, iclass 18, count 0 2006.173.14:00:03.60#ibcon#about to write, iclass 18, count 0 2006.173.14:00:03.60#ibcon#wrote, iclass 18, count 0 2006.173.14:00:03.60#ibcon#about to read 3, iclass 18, count 0 2006.173.14:00:03.64#ibcon#read 3, iclass 18, count 0 2006.173.14:00:03.64#ibcon#about to read 4, iclass 18, count 0 2006.173.14:00:03.64#ibcon#read 4, iclass 18, count 0 2006.173.14:00:03.64#ibcon#about to read 5, iclass 18, count 0 2006.173.14:00:03.64#ibcon#read 5, iclass 18, count 0 2006.173.14:00:03.64#ibcon#about to read 6, iclass 18, count 0 2006.173.14:00:03.64#ibcon#read 6, iclass 18, count 0 2006.173.14:00:03.64#ibcon#end of sib2, iclass 18, count 0 2006.173.14:00:03.64#ibcon#*after write, iclass 18, count 0 2006.173.14:00:03.64#ibcon#*before return 0, iclass 18, count 0 2006.173.14:00:03.64#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.14:00:03.64#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.14:00:03.64#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.14:00:03.64#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.14:00:03.64$vck44/va=8,4 2006.173.14:00:03.64#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.14:00:03.64#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.14:00:03.64#ibcon#ireg 11 cls_cnt 2 2006.173.14:00:03.64#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.14:00:03.70#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.14:00:03.70#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.14:00:03.70#ibcon#enter wrdev, iclass 20, count 2 2006.173.14:00:03.70#ibcon#first serial, iclass 20, count 2 2006.173.14:00:03.70#ibcon#enter sib2, iclass 20, count 2 2006.173.14:00:03.70#ibcon#flushed, iclass 20, count 2 2006.173.14:00:03.70#ibcon#about to write, iclass 20, count 2 2006.173.14:00:03.70#ibcon#wrote, iclass 20, count 2 2006.173.14:00:03.70#ibcon#about to read 3, iclass 20, count 2 2006.173.14:00:03.72#ibcon#read 3, iclass 20, count 2 2006.173.14:00:03.72#ibcon#about to read 4, iclass 20, count 2 2006.173.14:00:03.72#ibcon#read 4, iclass 20, count 2 2006.173.14:00:03.72#ibcon#about to read 5, iclass 20, count 2 2006.173.14:00:03.72#ibcon#read 5, iclass 20, count 2 2006.173.14:00:03.72#ibcon#about to read 6, iclass 20, count 2 2006.173.14:00:03.72#ibcon#read 6, iclass 20, count 2 2006.173.14:00:03.72#ibcon#end of sib2, iclass 20, count 2 2006.173.14:00:03.72#ibcon#*mode == 0, iclass 20, count 2 2006.173.14:00:03.72#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.14:00:03.72#ibcon#[25=AT08-04\r\n] 2006.173.14:00:03.72#ibcon#*before write, iclass 20, count 2 2006.173.14:00:03.72#ibcon#enter sib2, iclass 20, count 2 2006.173.14:00:03.72#ibcon#flushed, iclass 20, count 2 2006.173.14:00:03.72#ibcon#about to write, iclass 20, count 2 2006.173.14:00:03.72#ibcon#wrote, iclass 20, count 2 2006.173.14:00:03.72#ibcon#about to read 3, iclass 20, count 2 2006.173.14:00:03.75#ibcon#read 3, iclass 20, count 2 2006.173.14:00:03.75#ibcon#about to read 4, iclass 20, count 2 2006.173.14:00:03.75#ibcon#read 4, iclass 20, count 2 2006.173.14:00:03.75#ibcon#about to read 5, iclass 20, count 2 2006.173.14:00:03.75#ibcon#read 5, iclass 20, count 2 2006.173.14:00:03.75#ibcon#about to read 6, iclass 20, count 2 2006.173.14:00:03.75#ibcon#read 6, iclass 20, count 2 2006.173.14:00:03.75#ibcon#end of sib2, iclass 20, count 2 2006.173.14:00:03.75#ibcon#*after write, iclass 20, count 2 2006.173.14:00:03.75#ibcon#*before return 0, iclass 20, count 2 2006.173.14:00:03.75#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.14:00:03.75#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.14:00:03.75#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.14:00:03.75#ibcon#ireg 7 cls_cnt 0 2006.173.14:00:03.75#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.14:00:03.87#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.14:00:03.87#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.14:00:03.87#ibcon#enter wrdev, iclass 20, count 0 2006.173.14:00:03.87#ibcon#first serial, iclass 20, count 0 2006.173.14:00:03.87#ibcon#enter sib2, iclass 20, count 0 2006.173.14:00:03.87#ibcon#flushed, iclass 20, count 0 2006.173.14:00:03.87#ibcon#about to write, iclass 20, count 0 2006.173.14:00:03.87#ibcon#wrote, iclass 20, count 0 2006.173.14:00:03.87#ibcon#about to read 3, iclass 20, count 0 2006.173.14:00:03.89#ibcon#read 3, iclass 20, count 0 2006.173.14:00:03.89#ibcon#about to read 4, iclass 20, count 0 2006.173.14:00:03.89#ibcon#read 4, iclass 20, count 0 2006.173.14:00:03.89#ibcon#about to read 5, iclass 20, count 0 2006.173.14:00:03.89#ibcon#read 5, iclass 20, count 0 2006.173.14:00:03.89#ibcon#about to read 6, iclass 20, count 0 2006.173.14:00:03.89#ibcon#read 6, iclass 20, count 0 2006.173.14:00:03.89#ibcon#end of sib2, iclass 20, count 0 2006.173.14:00:03.89#ibcon#*mode == 0, iclass 20, count 0 2006.173.14:00:03.89#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.14:00:03.89#ibcon#[25=USB\r\n] 2006.173.14:00:03.89#ibcon#*before write, iclass 20, count 0 2006.173.14:00:03.89#ibcon#enter sib2, iclass 20, count 0 2006.173.14:00:03.89#ibcon#flushed, iclass 20, count 0 2006.173.14:00:03.89#ibcon#about to write, iclass 20, count 0 2006.173.14:00:03.89#ibcon#wrote, iclass 20, count 0 2006.173.14:00:03.89#ibcon#about to read 3, iclass 20, count 0 2006.173.14:00:03.92#ibcon#read 3, iclass 20, count 0 2006.173.14:00:03.92#ibcon#about to read 4, iclass 20, count 0 2006.173.14:00:03.92#ibcon#read 4, iclass 20, count 0 2006.173.14:00:03.92#ibcon#about to read 5, iclass 20, count 0 2006.173.14:00:03.92#ibcon#read 5, iclass 20, count 0 2006.173.14:00:03.92#ibcon#about to read 6, iclass 20, count 0 2006.173.14:00:03.92#ibcon#read 6, iclass 20, count 0 2006.173.14:00:03.92#ibcon#end of sib2, iclass 20, count 0 2006.173.14:00:03.92#ibcon#*after write, iclass 20, count 0 2006.173.14:00:03.92#ibcon#*before return 0, iclass 20, count 0 2006.173.14:00:03.92#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.14:00:03.92#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.14:00:03.92#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.14:00:03.92#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.14:00:03.92$vck44/vblo=1,629.99 2006.173.14:00:03.92#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.14:00:03.92#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.14:00:03.92#ibcon#ireg 17 cls_cnt 0 2006.173.14:00:03.92#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.14:00:03.92#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.14:00:03.92#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.14:00:03.92#ibcon#enter wrdev, iclass 22, count 0 2006.173.14:00:03.92#ibcon#first serial, iclass 22, count 0 2006.173.14:00:03.92#ibcon#enter sib2, iclass 22, count 0 2006.173.14:00:03.92#ibcon#flushed, iclass 22, count 0 2006.173.14:00:03.92#ibcon#about to write, iclass 22, count 0 2006.173.14:00:03.92#ibcon#wrote, iclass 22, count 0 2006.173.14:00:03.92#ibcon#about to read 3, iclass 22, count 0 2006.173.14:00:03.94#ibcon#read 3, iclass 22, count 0 2006.173.14:00:03.94#ibcon#about to read 4, iclass 22, count 0 2006.173.14:00:03.94#ibcon#read 4, iclass 22, count 0 2006.173.14:00:03.94#ibcon#about to read 5, iclass 22, count 0 2006.173.14:00:03.94#ibcon#read 5, iclass 22, count 0 2006.173.14:00:03.94#ibcon#about to read 6, iclass 22, count 0 2006.173.14:00:03.94#ibcon#read 6, iclass 22, count 0 2006.173.14:00:03.94#ibcon#end of sib2, iclass 22, count 0 2006.173.14:00:03.94#ibcon#*mode == 0, iclass 22, count 0 2006.173.14:00:03.94#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.14:00:03.94#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.14:00:03.94#ibcon#*before write, iclass 22, count 0 2006.173.14:00:03.94#ibcon#enter sib2, iclass 22, count 0 2006.173.14:00:03.94#ibcon#flushed, iclass 22, count 0 2006.173.14:00:03.94#ibcon#about to write, iclass 22, count 0 2006.173.14:00:03.94#ibcon#wrote, iclass 22, count 0 2006.173.14:00:03.94#ibcon#about to read 3, iclass 22, count 0 2006.173.14:00:03.98#ibcon#read 3, iclass 22, count 0 2006.173.14:00:03.98#ibcon#about to read 4, iclass 22, count 0 2006.173.14:00:03.98#ibcon#read 4, iclass 22, count 0 2006.173.14:00:03.98#ibcon#about to read 5, iclass 22, count 0 2006.173.14:00:03.98#ibcon#read 5, iclass 22, count 0 2006.173.14:00:03.98#ibcon#about to read 6, iclass 22, count 0 2006.173.14:00:03.98#ibcon#read 6, iclass 22, count 0 2006.173.14:00:03.98#ibcon#end of sib2, iclass 22, count 0 2006.173.14:00:03.98#ibcon#*after write, iclass 22, count 0 2006.173.14:00:03.98#ibcon#*before return 0, iclass 22, count 0 2006.173.14:00:03.98#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.14:00:03.98#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.14:00:03.98#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.14:00:03.98#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.14:00:03.98$vck44/vb=1,4 2006.173.14:00:03.98#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.14:00:03.98#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.14:00:03.98#ibcon#ireg 11 cls_cnt 2 2006.173.14:00:03.98#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.14:00:03.98#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.14:00:03.98#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.14:00:03.98#ibcon#enter wrdev, iclass 24, count 2 2006.173.14:00:03.98#ibcon#first serial, iclass 24, count 2 2006.173.14:00:03.98#ibcon#enter sib2, iclass 24, count 2 2006.173.14:00:03.98#ibcon#flushed, iclass 24, count 2 2006.173.14:00:03.98#ibcon#about to write, iclass 24, count 2 2006.173.14:00:03.98#ibcon#wrote, iclass 24, count 2 2006.173.14:00:03.98#ibcon#about to read 3, iclass 24, count 2 2006.173.14:00:04.00#ibcon#read 3, iclass 24, count 2 2006.173.14:00:04.00#ibcon#about to read 4, iclass 24, count 2 2006.173.14:00:04.00#ibcon#read 4, iclass 24, count 2 2006.173.14:00:04.00#ibcon#about to read 5, iclass 24, count 2 2006.173.14:00:04.00#ibcon#read 5, iclass 24, count 2 2006.173.14:00:04.00#ibcon#about to read 6, iclass 24, count 2 2006.173.14:00:04.00#ibcon#read 6, iclass 24, count 2 2006.173.14:00:04.00#ibcon#end of sib2, iclass 24, count 2 2006.173.14:00:04.00#ibcon#*mode == 0, iclass 24, count 2 2006.173.14:00:04.00#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.14:00:04.00#ibcon#[27=AT01-04\r\n] 2006.173.14:00:04.00#ibcon#*before write, iclass 24, count 2 2006.173.14:00:04.00#ibcon#enter sib2, iclass 24, count 2 2006.173.14:00:04.00#ibcon#flushed, iclass 24, count 2 2006.173.14:00:04.00#ibcon#about to write, iclass 24, count 2 2006.173.14:00:04.00#ibcon#wrote, iclass 24, count 2 2006.173.14:00:04.00#ibcon#about to read 3, iclass 24, count 2 2006.173.14:00:04.03#ibcon#read 3, iclass 24, count 2 2006.173.14:00:04.03#ibcon#about to read 4, iclass 24, count 2 2006.173.14:00:04.03#ibcon#read 4, iclass 24, count 2 2006.173.14:00:04.03#ibcon#about to read 5, iclass 24, count 2 2006.173.14:00:04.03#ibcon#read 5, iclass 24, count 2 2006.173.14:00:04.03#ibcon#about to read 6, iclass 24, count 2 2006.173.14:00:04.03#ibcon#read 6, iclass 24, count 2 2006.173.14:00:04.03#ibcon#end of sib2, iclass 24, count 2 2006.173.14:00:04.03#ibcon#*after write, iclass 24, count 2 2006.173.14:00:04.03#ibcon#*before return 0, iclass 24, count 2 2006.173.14:00:04.03#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.14:00:04.03#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.14:00:04.03#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.14:00:04.03#ibcon#ireg 7 cls_cnt 0 2006.173.14:00:04.03#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.14:00:04.15#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.14:00:04.15#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.14:00:04.15#ibcon#enter wrdev, iclass 24, count 0 2006.173.14:00:04.15#ibcon#first serial, iclass 24, count 0 2006.173.14:00:04.15#ibcon#enter sib2, iclass 24, count 0 2006.173.14:00:04.15#ibcon#flushed, iclass 24, count 0 2006.173.14:00:04.15#ibcon#about to write, iclass 24, count 0 2006.173.14:00:04.15#ibcon#wrote, iclass 24, count 0 2006.173.14:00:04.15#ibcon#about to read 3, iclass 24, count 0 2006.173.14:00:04.17#ibcon#read 3, iclass 24, count 0 2006.173.14:00:04.17#ibcon#about to read 4, iclass 24, count 0 2006.173.14:00:04.17#ibcon#read 4, iclass 24, count 0 2006.173.14:00:04.17#ibcon#about to read 5, iclass 24, count 0 2006.173.14:00:04.17#ibcon#read 5, iclass 24, count 0 2006.173.14:00:04.17#ibcon#about to read 6, iclass 24, count 0 2006.173.14:00:04.17#ibcon#read 6, iclass 24, count 0 2006.173.14:00:04.17#ibcon#end of sib2, iclass 24, count 0 2006.173.14:00:04.17#ibcon#*mode == 0, iclass 24, count 0 2006.173.14:00:04.17#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.14:00:04.17#ibcon#[27=USB\r\n] 2006.173.14:00:04.17#ibcon#*before write, iclass 24, count 0 2006.173.14:00:04.17#ibcon#enter sib2, iclass 24, count 0 2006.173.14:00:04.17#ibcon#flushed, iclass 24, count 0 2006.173.14:00:04.17#ibcon#about to write, iclass 24, count 0 2006.173.14:00:04.17#ibcon#wrote, iclass 24, count 0 2006.173.14:00:04.17#ibcon#about to read 3, iclass 24, count 0 2006.173.14:00:04.20#ibcon#read 3, iclass 24, count 0 2006.173.14:00:04.20#ibcon#about to read 4, iclass 24, count 0 2006.173.14:00:04.20#ibcon#read 4, iclass 24, count 0 2006.173.14:00:04.20#ibcon#about to read 5, iclass 24, count 0 2006.173.14:00:04.20#ibcon#read 5, iclass 24, count 0 2006.173.14:00:04.20#ibcon#about to read 6, iclass 24, count 0 2006.173.14:00:04.20#ibcon#read 6, iclass 24, count 0 2006.173.14:00:04.20#ibcon#end of sib2, iclass 24, count 0 2006.173.14:00:04.20#ibcon#*after write, iclass 24, count 0 2006.173.14:00:04.20#ibcon#*before return 0, iclass 24, count 0 2006.173.14:00:04.20#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.14:00:04.20#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.14:00:04.20#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.14:00:04.20#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.14:00:04.20$vck44/vblo=2,634.99 2006.173.14:00:04.20#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.14:00:04.20#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.14:00:04.20#ibcon#ireg 17 cls_cnt 0 2006.173.14:00:04.20#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.14:00:04.20#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.14:00:04.20#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.14:00:04.20#ibcon#enter wrdev, iclass 26, count 0 2006.173.14:00:04.20#ibcon#first serial, iclass 26, count 0 2006.173.14:00:04.20#ibcon#enter sib2, iclass 26, count 0 2006.173.14:00:04.20#ibcon#flushed, iclass 26, count 0 2006.173.14:00:04.20#ibcon#about to write, iclass 26, count 0 2006.173.14:00:04.20#ibcon#wrote, iclass 26, count 0 2006.173.14:00:04.20#ibcon#about to read 3, iclass 26, count 0 2006.173.14:00:04.22#ibcon#read 3, iclass 26, count 0 2006.173.14:00:04.22#ibcon#about to read 4, iclass 26, count 0 2006.173.14:00:04.22#ibcon#read 4, iclass 26, count 0 2006.173.14:00:04.22#ibcon#about to read 5, iclass 26, count 0 2006.173.14:00:04.22#ibcon#read 5, iclass 26, count 0 2006.173.14:00:04.22#ibcon#about to read 6, iclass 26, count 0 2006.173.14:00:04.22#ibcon#read 6, iclass 26, count 0 2006.173.14:00:04.22#ibcon#end of sib2, iclass 26, count 0 2006.173.14:00:04.22#ibcon#*mode == 0, iclass 26, count 0 2006.173.14:00:04.22#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.14:00:04.22#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.14:00:04.22#ibcon#*before write, iclass 26, count 0 2006.173.14:00:04.22#ibcon#enter sib2, iclass 26, count 0 2006.173.14:00:04.22#ibcon#flushed, iclass 26, count 0 2006.173.14:00:04.22#ibcon#about to write, iclass 26, count 0 2006.173.14:00:04.22#ibcon#wrote, iclass 26, count 0 2006.173.14:00:04.22#ibcon#about to read 3, iclass 26, count 0 2006.173.14:00:04.26#ibcon#read 3, iclass 26, count 0 2006.173.14:00:04.26#ibcon#about to read 4, iclass 26, count 0 2006.173.14:00:04.26#ibcon#read 4, iclass 26, count 0 2006.173.14:00:04.26#ibcon#about to read 5, iclass 26, count 0 2006.173.14:00:04.26#ibcon#read 5, iclass 26, count 0 2006.173.14:00:04.26#ibcon#about to read 6, iclass 26, count 0 2006.173.14:00:04.26#ibcon#read 6, iclass 26, count 0 2006.173.14:00:04.26#ibcon#end of sib2, iclass 26, count 0 2006.173.14:00:04.26#ibcon#*after write, iclass 26, count 0 2006.173.14:00:04.26#ibcon#*before return 0, iclass 26, count 0 2006.173.14:00:04.26#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.14:00:04.26#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.14:00:04.26#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.14:00:04.26#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.14:00:04.26$vck44/vb=2,4 2006.173.14:00:04.26#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.14:00:04.26#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.14:00:04.26#ibcon#ireg 11 cls_cnt 2 2006.173.14:00:04.26#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.14:00:04.32#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.14:00:04.32#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.14:00:04.32#ibcon#enter wrdev, iclass 28, count 2 2006.173.14:00:04.32#ibcon#first serial, iclass 28, count 2 2006.173.14:00:04.32#ibcon#enter sib2, iclass 28, count 2 2006.173.14:00:04.32#ibcon#flushed, iclass 28, count 2 2006.173.14:00:04.32#ibcon#about to write, iclass 28, count 2 2006.173.14:00:04.32#ibcon#wrote, iclass 28, count 2 2006.173.14:00:04.32#ibcon#about to read 3, iclass 28, count 2 2006.173.14:00:04.34#ibcon#read 3, iclass 28, count 2 2006.173.14:00:04.34#ibcon#about to read 4, iclass 28, count 2 2006.173.14:00:04.34#ibcon#read 4, iclass 28, count 2 2006.173.14:00:04.34#ibcon#about to read 5, iclass 28, count 2 2006.173.14:00:04.34#ibcon#read 5, iclass 28, count 2 2006.173.14:00:04.34#ibcon#about to read 6, iclass 28, count 2 2006.173.14:00:04.34#ibcon#read 6, iclass 28, count 2 2006.173.14:00:04.34#ibcon#end of sib2, iclass 28, count 2 2006.173.14:00:04.34#ibcon#*mode == 0, iclass 28, count 2 2006.173.14:00:04.34#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.14:00:04.34#ibcon#[27=AT02-04\r\n] 2006.173.14:00:04.34#ibcon#*before write, iclass 28, count 2 2006.173.14:00:04.34#ibcon#enter sib2, iclass 28, count 2 2006.173.14:00:04.34#ibcon#flushed, iclass 28, count 2 2006.173.14:00:04.34#ibcon#about to write, iclass 28, count 2 2006.173.14:00:04.34#ibcon#wrote, iclass 28, count 2 2006.173.14:00:04.34#ibcon#about to read 3, iclass 28, count 2 2006.173.14:00:04.37#ibcon#read 3, iclass 28, count 2 2006.173.14:00:04.37#ibcon#about to read 4, iclass 28, count 2 2006.173.14:00:04.37#ibcon#read 4, iclass 28, count 2 2006.173.14:00:04.37#ibcon#about to read 5, iclass 28, count 2 2006.173.14:00:04.37#ibcon#read 5, iclass 28, count 2 2006.173.14:00:04.37#ibcon#about to read 6, iclass 28, count 2 2006.173.14:00:04.37#ibcon#read 6, iclass 28, count 2 2006.173.14:00:04.37#ibcon#end of sib2, iclass 28, count 2 2006.173.14:00:04.37#ibcon#*after write, iclass 28, count 2 2006.173.14:00:04.37#ibcon#*before return 0, iclass 28, count 2 2006.173.14:00:04.37#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.14:00:04.37#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.14:00:04.37#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.14:00:04.37#ibcon#ireg 7 cls_cnt 0 2006.173.14:00:04.37#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.14:00:04.49#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.14:00:04.49#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.14:00:04.49#ibcon#enter wrdev, iclass 28, count 0 2006.173.14:00:04.49#ibcon#first serial, iclass 28, count 0 2006.173.14:00:04.49#ibcon#enter sib2, iclass 28, count 0 2006.173.14:00:04.49#ibcon#flushed, iclass 28, count 0 2006.173.14:00:04.49#ibcon#about to write, iclass 28, count 0 2006.173.14:00:04.49#ibcon#wrote, iclass 28, count 0 2006.173.14:00:04.49#ibcon#about to read 3, iclass 28, count 0 2006.173.14:00:04.51#ibcon#read 3, iclass 28, count 0 2006.173.14:00:04.51#ibcon#about to read 4, iclass 28, count 0 2006.173.14:00:04.51#ibcon#read 4, iclass 28, count 0 2006.173.14:00:04.51#ibcon#about to read 5, iclass 28, count 0 2006.173.14:00:04.51#ibcon#read 5, iclass 28, count 0 2006.173.14:00:04.51#ibcon#about to read 6, iclass 28, count 0 2006.173.14:00:04.51#ibcon#read 6, iclass 28, count 0 2006.173.14:00:04.51#ibcon#end of sib2, iclass 28, count 0 2006.173.14:00:04.51#ibcon#*mode == 0, iclass 28, count 0 2006.173.14:00:04.51#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.14:00:04.51#ibcon#[27=USB\r\n] 2006.173.14:00:04.51#ibcon#*before write, iclass 28, count 0 2006.173.14:00:04.51#ibcon#enter sib2, iclass 28, count 0 2006.173.14:00:04.51#ibcon#flushed, iclass 28, count 0 2006.173.14:00:04.51#ibcon#about to write, iclass 28, count 0 2006.173.14:00:04.51#ibcon#wrote, iclass 28, count 0 2006.173.14:00:04.51#ibcon#about to read 3, iclass 28, count 0 2006.173.14:00:04.54#ibcon#read 3, iclass 28, count 0 2006.173.14:00:04.54#ibcon#about to read 4, iclass 28, count 0 2006.173.14:00:04.54#ibcon#read 4, iclass 28, count 0 2006.173.14:00:04.54#ibcon#about to read 5, iclass 28, count 0 2006.173.14:00:04.54#ibcon#read 5, iclass 28, count 0 2006.173.14:00:04.54#ibcon#about to read 6, iclass 28, count 0 2006.173.14:00:04.54#ibcon#read 6, iclass 28, count 0 2006.173.14:00:04.54#ibcon#end of sib2, iclass 28, count 0 2006.173.14:00:04.54#ibcon#*after write, iclass 28, count 0 2006.173.14:00:04.54#ibcon#*before return 0, iclass 28, count 0 2006.173.14:00:04.54#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.14:00:04.54#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.14:00:04.54#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.14:00:04.54#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.14:00:04.54$vck44/vblo=3,649.99 2006.173.14:00:04.54#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.14:00:04.54#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.14:00:04.54#ibcon#ireg 17 cls_cnt 0 2006.173.14:00:04.54#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.14:00:04.54#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.14:00:04.54#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.14:00:04.54#ibcon#enter wrdev, iclass 30, count 0 2006.173.14:00:04.54#ibcon#first serial, iclass 30, count 0 2006.173.14:00:04.54#ibcon#enter sib2, iclass 30, count 0 2006.173.14:00:04.54#ibcon#flushed, iclass 30, count 0 2006.173.14:00:04.54#ibcon#about to write, iclass 30, count 0 2006.173.14:00:04.54#ibcon#wrote, iclass 30, count 0 2006.173.14:00:04.54#ibcon#about to read 3, iclass 30, count 0 2006.173.14:00:04.56#ibcon#read 3, iclass 30, count 0 2006.173.14:00:04.56#ibcon#about to read 4, iclass 30, count 0 2006.173.14:00:04.56#ibcon#read 4, iclass 30, count 0 2006.173.14:00:04.56#ibcon#about to read 5, iclass 30, count 0 2006.173.14:00:04.56#ibcon#read 5, iclass 30, count 0 2006.173.14:00:04.56#ibcon#about to read 6, iclass 30, count 0 2006.173.14:00:04.56#ibcon#read 6, iclass 30, count 0 2006.173.14:00:04.56#ibcon#end of sib2, iclass 30, count 0 2006.173.14:00:04.56#ibcon#*mode == 0, iclass 30, count 0 2006.173.14:00:04.56#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.14:00:04.56#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.14:00:04.56#ibcon#*before write, iclass 30, count 0 2006.173.14:00:04.56#ibcon#enter sib2, iclass 30, count 0 2006.173.14:00:04.56#ibcon#flushed, iclass 30, count 0 2006.173.14:00:04.56#ibcon#about to write, iclass 30, count 0 2006.173.14:00:04.56#ibcon#wrote, iclass 30, count 0 2006.173.14:00:04.56#ibcon#about to read 3, iclass 30, count 0 2006.173.14:00:04.60#ibcon#read 3, iclass 30, count 0 2006.173.14:00:04.60#ibcon#about to read 4, iclass 30, count 0 2006.173.14:00:04.60#ibcon#read 4, iclass 30, count 0 2006.173.14:00:04.60#ibcon#about to read 5, iclass 30, count 0 2006.173.14:00:04.60#ibcon#read 5, iclass 30, count 0 2006.173.14:00:04.60#ibcon#about to read 6, iclass 30, count 0 2006.173.14:00:04.60#ibcon#read 6, iclass 30, count 0 2006.173.14:00:04.60#ibcon#end of sib2, iclass 30, count 0 2006.173.14:00:04.60#ibcon#*after write, iclass 30, count 0 2006.173.14:00:04.60#ibcon#*before return 0, iclass 30, count 0 2006.173.14:00:04.60#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.14:00:04.60#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.14:00:04.60#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.14:00:04.60#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.14:00:04.60$vck44/vb=3,4 2006.173.14:00:04.60#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.173.14:00:04.60#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.173.14:00:04.60#ibcon#ireg 11 cls_cnt 2 2006.173.14:00:04.60#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.14:00:04.66#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.14:00:04.66#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.14:00:04.66#ibcon#enter wrdev, iclass 32, count 2 2006.173.14:00:04.66#ibcon#first serial, iclass 32, count 2 2006.173.14:00:04.66#ibcon#enter sib2, iclass 32, count 2 2006.173.14:00:04.66#ibcon#flushed, iclass 32, count 2 2006.173.14:00:04.66#ibcon#about to write, iclass 32, count 2 2006.173.14:00:04.66#ibcon#wrote, iclass 32, count 2 2006.173.14:00:04.66#ibcon#about to read 3, iclass 32, count 2 2006.173.14:00:04.68#ibcon#read 3, iclass 32, count 2 2006.173.14:00:04.68#ibcon#about to read 4, iclass 32, count 2 2006.173.14:00:04.68#ibcon#read 4, iclass 32, count 2 2006.173.14:00:04.68#ibcon#about to read 5, iclass 32, count 2 2006.173.14:00:04.68#ibcon#read 5, iclass 32, count 2 2006.173.14:00:04.68#ibcon#about to read 6, iclass 32, count 2 2006.173.14:00:04.68#ibcon#read 6, iclass 32, count 2 2006.173.14:00:04.68#ibcon#end of sib2, iclass 32, count 2 2006.173.14:00:04.68#ibcon#*mode == 0, iclass 32, count 2 2006.173.14:00:04.68#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.173.14:00:04.68#ibcon#[27=AT03-04\r\n] 2006.173.14:00:04.68#ibcon#*before write, iclass 32, count 2 2006.173.14:00:04.68#ibcon#enter sib2, iclass 32, count 2 2006.173.14:00:04.68#ibcon#flushed, iclass 32, count 2 2006.173.14:00:04.68#ibcon#about to write, iclass 32, count 2 2006.173.14:00:04.68#ibcon#wrote, iclass 32, count 2 2006.173.14:00:04.68#ibcon#about to read 3, iclass 32, count 2 2006.173.14:00:04.71#ibcon#read 3, iclass 32, count 2 2006.173.14:00:04.71#ibcon#about to read 4, iclass 32, count 2 2006.173.14:00:04.71#ibcon#read 4, iclass 32, count 2 2006.173.14:00:04.71#ibcon#about to read 5, iclass 32, count 2 2006.173.14:00:04.71#ibcon#read 5, iclass 32, count 2 2006.173.14:00:04.71#ibcon#about to read 6, iclass 32, count 2 2006.173.14:00:04.71#ibcon#read 6, iclass 32, count 2 2006.173.14:00:04.71#ibcon#end of sib2, iclass 32, count 2 2006.173.14:00:04.71#ibcon#*after write, iclass 32, count 2 2006.173.14:00:04.71#ibcon#*before return 0, iclass 32, count 2 2006.173.14:00:04.71#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.14:00:04.71#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.173.14:00:04.71#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.173.14:00:04.71#ibcon#ireg 7 cls_cnt 0 2006.173.14:00:04.71#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.14:00:04.83#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.14:00:04.83#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.14:00:04.83#ibcon#enter wrdev, iclass 32, count 0 2006.173.14:00:04.83#ibcon#first serial, iclass 32, count 0 2006.173.14:00:04.83#ibcon#enter sib2, iclass 32, count 0 2006.173.14:00:04.83#ibcon#flushed, iclass 32, count 0 2006.173.14:00:04.83#ibcon#about to write, iclass 32, count 0 2006.173.14:00:04.83#ibcon#wrote, iclass 32, count 0 2006.173.14:00:04.83#ibcon#about to read 3, iclass 32, count 0 2006.173.14:00:04.85#ibcon#read 3, iclass 32, count 0 2006.173.14:00:04.85#ibcon#about to read 4, iclass 32, count 0 2006.173.14:00:04.85#ibcon#read 4, iclass 32, count 0 2006.173.14:00:04.85#ibcon#about to read 5, iclass 32, count 0 2006.173.14:00:04.85#ibcon#read 5, iclass 32, count 0 2006.173.14:00:04.85#ibcon#about to read 6, iclass 32, count 0 2006.173.14:00:04.85#ibcon#read 6, iclass 32, count 0 2006.173.14:00:04.85#ibcon#end of sib2, iclass 32, count 0 2006.173.14:00:04.85#ibcon#*mode == 0, iclass 32, count 0 2006.173.14:00:04.85#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.14:00:04.85#ibcon#[27=USB\r\n] 2006.173.14:00:04.85#ibcon#*before write, iclass 32, count 0 2006.173.14:00:04.85#ibcon#enter sib2, iclass 32, count 0 2006.173.14:00:04.85#ibcon#flushed, iclass 32, count 0 2006.173.14:00:04.85#ibcon#about to write, iclass 32, count 0 2006.173.14:00:04.85#ibcon#wrote, iclass 32, count 0 2006.173.14:00:04.85#ibcon#about to read 3, iclass 32, count 0 2006.173.14:00:04.88#ibcon#read 3, iclass 32, count 0 2006.173.14:00:04.88#ibcon#about to read 4, iclass 32, count 0 2006.173.14:00:04.88#ibcon#read 4, iclass 32, count 0 2006.173.14:00:04.88#ibcon#about to read 5, iclass 32, count 0 2006.173.14:00:04.88#ibcon#read 5, iclass 32, count 0 2006.173.14:00:04.88#ibcon#about to read 6, iclass 32, count 0 2006.173.14:00:04.88#ibcon#read 6, iclass 32, count 0 2006.173.14:00:04.88#ibcon#end of sib2, iclass 32, count 0 2006.173.14:00:04.88#ibcon#*after write, iclass 32, count 0 2006.173.14:00:04.88#ibcon#*before return 0, iclass 32, count 0 2006.173.14:00:04.88#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.14:00:04.88#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.173.14:00:04.88#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.14:00:04.88#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.14:00:04.88$vck44/vblo=4,679.99 2006.173.14:00:04.88#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.14:00:04.88#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.14:00:04.88#ibcon#ireg 17 cls_cnt 0 2006.173.14:00:04.88#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.14:00:04.88#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.14:00:04.88#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.14:00:04.88#ibcon#enter wrdev, iclass 34, count 0 2006.173.14:00:04.88#ibcon#first serial, iclass 34, count 0 2006.173.14:00:04.88#ibcon#enter sib2, iclass 34, count 0 2006.173.14:00:04.88#ibcon#flushed, iclass 34, count 0 2006.173.14:00:04.88#ibcon#about to write, iclass 34, count 0 2006.173.14:00:04.88#ibcon#wrote, iclass 34, count 0 2006.173.14:00:04.88#ibcon#about to read 3, iclass 34, count 0 2006.173.14:00:04.90#ibcon#read 3, iclass 34, count 0 2006.173.14:00:04.90#ibcon#about to read 4, iclass 34, count 0 2006.173.14:00:04.90#ibcon#read 4, iclass 34, count 0 2006.173.14:00:04.90#ibcon#about to read 5, iclass 34, count 0 2006.173.14:00:04.90#ibcon#read 5, iclass 34, count 0 2006.173.14:00:04.90#ibcon#about to read 6, iclass 34, count 0 2006.173.14:00:04.90#ibcon#read 6, iclass 34, count 0 2006.173.14:00:04.90#ibcon#end of sib2, iclass 34, count 0 2006.173.14:00:04.90#ibcon#*mode == 0, iclass 34, count 0 2006.173.14:00:04.90#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.14:00:04.90#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.14:00:04.90#ibcon#*before write, iclass 34, count 0 2006.173.14:00:04.90#ibcon#enter sib2, iclass 34, count 0 2006.173.14:00:04.90#ibcon#flushed, iclass 34, count 0 2006.173.14:00:04.90#ibcon#about to write, iclass 34, count 0 2006.173.14:00:04.90#ibcon#wrote, iclass 34, count 0 2006.173.14:00:04.90#ibcon#about to read 3, iclass 34, count 0 2006.173.14:00:04.94#ibcon#read 3, iclass 34, count 0 2006.173.14:00:04.94#ibcon#about to read 4, iclass 34, count 0 2006.173.14:00:04.94#ibcon#read 4, iclass 34, count 0 2006.173.14:00:04.94#ibcon#about to read 5, iclass 34, count 0 2006.173.14:00:04.94#ibcon#read 5, iclass 34, count 0 2006.173.14:00:04.94#ibcon#about to read 6, iclass 34, count 0 2006.173.14:00:04.94#ibcon#read 6, iclass 34, count 0 2006.173.14:00:04.94#ibcon#end of sib2, iclass 34, count 0 2006.173.14:00:04.94#ibcon#*after write, iclass 34, count 0 2006.173.14:00:04.94#ibcon#*before return 0, iclass 34, count 0 2006.173.14:00:04.94#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.14:00:04.94#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.14:00:04.94#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.14:00:04.94#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.14:00:04.94$vck44/vb=4,4 2006.173.14:00:04.94#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.14:00:04.94#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.14:00:04.94#ibcon#ireg 11 cls_cnt 2 2006.173.14:00:04.94#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.14:00:05.00#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.14:00:05.00#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.14:00:05.00#ibcon#enter wrdev, iclass 36, count 2 2006.173.14:00:05.00#ibcon#first serial, iclass 36, count 2 2006.173.14:00:05.00#ibcon#enter sib2, iclass 36, count 2 2006.173.14:00:05.00#ibcon#flushed, iclass 36, count 2 2006.173.14:00:05.00#ibcon#about to write, iclass 36, count 2 2006.173.14:00:05.00#ibcon#wrote, iclass 36, count 2 2006.173.14:00:05.00#ibcon#about to read 3, iclass 36, count 2 2006.173.14:00:05.02#ibcon#read 3, iclass 36, count 2 2006.173.14:00:05.02#ibcon#about to read 4, iclass 36, count 2 2006.173.14:00:05.02#ibcon#read 4, iclass 36, count 2 2006.173.14:00:05.02#ibcon#about to read 5, iclass 36, count 2 2006.173.14:00:05.02#ibcon#read 5, iclass 36, count 2 2006.173.14:00:05.02#ibcon#about to read 6, iclass 36, count 2 2006.173.14:00:05.02#ibcon#read 6, iclass 36, count 2 2006.173.14:00:05.02#ibcon#end of sib2, iclass 36, count 2 2006.173.14:00:05.02#ibcon#*mode == 0, iclass 36, count 2 2006.173.14:00:05.02#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.14:00:05.02#ibcon#[27=AT04-04\r\n] 2006.173.14:00:05.02#ibcon#*before write, iclass 36, count 2 2006.173.14:00:05.02#ibcon#enter sib2, iclass 36, count 2 2006.173.14:00:05.02#ibcon#flushed, iclass 36, count 2 2006.173.14:00:05.02#ibcon#about to write, iclass 36, count 2 2006.173.14:00:05.02#ibcon#wrote, iclass 36, count 2 2006.173.14:00:05.02#ibcon#about to read 3, iclass 36, count 2 2006.173.14:00:05.05#ibcon#read 3, iclass 36, count 2 2006.173.14:00:05.05#ibcon#about to read 4, iclass 36, count 2 2006.173.14:00:05.05#ibcon#read 4, iclass 36, count 2 2006.173.14:00:05.05#ibcon#about to read 5, iclass 36, count 2 2006.173.14:00:05.05#ibcon#read 5, iclass 36, count 2 2006.173.14:00:05.05#ibcon#about to read 6, iclass 36, count 2 2006.173.14:00:05.05#ibcon#read 6, iclass 36, count 2 2006.173.14:00:05.05#ibcon#end of sib2, iclass 36, count 2 2006.173.14:00:05.05#ibcon#*after write, iclass 36, count 2 2006.173.14:00:05.05#ibcon#*before return 0, iclass 36, count 2 2006.173.14:00:05.05#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.14:00:05.05#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.14:00:05.05#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.14:00:05.05#ibcon#ireg 7 cls_cnt 0 2006.173.14:00:05.05#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.14:00:05.17#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.14:00:05.17#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.14:00:05.17#ibcon#enter wrdev, iclass 36, count 0 2006.173.14:00:05.17#ibcon#first serial, iclass 36, count 0 2006.173.14:00:05.17#ibcon#enter sib2, iclass 36, count 0 2006.173.14:00:05.17#ibcon#flushed, iclass 36, count 0 2006.173.14:00:05.17#ibcon#about to write, iclass 36, count 0 2006.173.14:00:05.17#ibcon#wrote, iclass 36, count 0 2006.173.14:00:05.17#ibcon#about to read 3, iclass 36, count 0 2006.173.14:00:05.19#ibcon#read 3, iclass 36, count 0 2006.173.14:00:05.19#ibcon#about to read 4, iclass 36, count 0 2006.173.14:00:05.19#ibcon#read 4, iclass 36, count 0 2006.173.14:00:05.19#ibcon#about to read 5, iclass 36, count 0 2006.173.14:00:05.19#ibcon#read 5, iclass 36, count 0 2006.173.14:00:05.19#ibcon#about to read 6, iclass 36, count 0 2006.173.14:00:05.19#ibcon#read 6, iclass 36, count 0 2006.173.14:00:05.19#ibcon#end of sib2, iclass 36, count 0 2006.173.14:00:05.19#ibcon#*mode == 0, iclass 36, count 0 2006.173.14:00:05.19#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.14:00:05.19#ibcon#[27=USB\r\n] 2006.173.14:00:05.19#ibcon#*before write, iclass 36, count 0 2006.173.14:00:05.19#ibcon#enter sib2, iclass 36, count 0 2006.173.14:00:05.19#ibcon#flushed, iclass 36, count 0 2006.173.14:00:05.19#ibcon#about to write, iclass 36, count 0 2006.173.14:00:05.19#ibcon#wrote, iclass 36, count 0 2006.173.14:00:05.19#ibcon#about to read 3, iclass 36, count 0 2006.173.14:00:05.22#ibcon#read 3, iclass 36, count 0 2006.173.14:00:05.22#ibcon#about to read 4, iclass 36, count 0 2006.173.14:00:05.22#ibcon#read 4, iclass 36, count 0 2006.173.14:00:05.22#ibcon#about to read 5, iclass 36, count 0 2006.173.14:00:05.22#ibcon#read 5, iclass 36, count 0 2006.173.14:00:05.22#ibcon#about to read 6, iclass 36, count 0 2006.173.14:00:05.22#ibcon#read 6, iclass 36, count 0 2006.173.14:00:05.22#ibcon#end of sib2, iclass 36, count 0 2006.173.14:00:05.22#ibcon#*after write, iclass 36, count 0 2006.173.14:00:05.22#ibcon#*before return 0, iclass 36, count 0 2006.173.14:00:05.22#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.14:00:05.22#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.14:00:05.22#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.14:00:05.22#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.14:00:05.22$vck44/vblo=5,709.99 2006.173.14:00:05.22#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.14:00:05.22#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.14:00:05.22#ibcon#ireg 17 cls_cnt 0 2006.173.14:00:05.22#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.14:00:05.22#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.14:00:05.22#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.14:00:05.22#ibcon#enter wrdev, iclass 38, count 0 2006.173.14:00:05.22#ibcon#first serial, iclass 38, count 0 2006.173.14:00:05.22#ibcon#enter sib2, iclass 38, count 0 2006.173.14:00:05.22#ibcon#flushed, iclass 38, count 0 2006.173.14:00:05.22#ibcon#about to write, iclass 38, count 0 2006.173.14:00:05.22#ibcon#wrote, iclass 38, count 0 2006.173.14:00:05.22#ibcon#about to read 3, iclass 38, count 0 2006.173.14:00:05.24#ibcon#read 3, iclass 38, count 0 2006.173.14:00:05.24#ibcon#about to read 4, iclass 38, count 0 2006.173.14:00:05.24#ibcon#read 4, iclass 38, count 0 2006.173.14:00:05.24#ibcon#about to read 5, iclass 38, count 0 2006.173.14:00:05.24#ibcon#read 5, iclass 38, count 0 2006.173.14:00:05.24#ibcon#about to read 6, iclass 38, count 0 2006.173.14:00:05.24#ibcon#read 6, iclass 38, count 0 2006.173.14:00:05.24#ibcon#end of sib2, iclass 38, count 0 2006.173.14:00:05.24#ibcon#*mode == 0, iclass 38, count 0 2006.173.14:00:05.24#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.14:00:05.24#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.14:00:05.24#ibcon#*before write, iclass 38, count 0 2006.173.14:00:05.24#ibcon#enter sib2, iclass 38, count 0 2006.173.14:00:05.24#ibcon#flushed, iclass 38, count 0 2006.173.14:00:05.24#ibcon#about to write, iclass 38, count 0 2006.173.14:00:05.24#ibcon#wrote, iclass 38, count 0 2006.173.14:00:05.24#ibcon#about to read 3, iclass 38, count 0 2006.173.14:00:05.28#ibcon#read 3, iclass 38, count 0 2006.173.14:00:05.28#ibcon#about to read 4, iclass 38, count 0 2006.173.14:00:05.28#ibcon#read 4, iclass 38, count 0 2006.173.14:00:05.28#ibcon#about to read 5, iclass 38, count 0 2006.173.14:00:05.28#ibcon#read 5, iclass 38, count 0 2006.173.14:00:05.28#ibcon#about to read 6, iclass 38, count 0 2006.173.14:00:05.28#ibcon#read 6, iclass 38, count 0 2006.173.14:00:05.28#ibcon#end of sib2, iclass 38, count 0 2006.173.14:00:05.28#ibcon#*after write, iclass 38, count 0 2006.173.14:00:05.28#ibcon#*before return 0, iclass 38, count 0 2006.173.14:00:05.28#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.14:00:05.28#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.14:00:05.28#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.14:00:05.28#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.14:00:05.28$vck44/vb=5,4 2006.173.14:00:05.28#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.14:00:05.28#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.14:00:05.28#ibcon#ireg 11 cls_cnt 2 2006.173.14:00:05.28#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.14:00:05.34#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.14:00:05.34#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.14:00:05.34#ibcon#enter wrdev, iclass 40, count 2 2006.173.14:00:05.34#ibcon#first serial, iclass 40, count 2 2006.173.14:00:05.34#ibcon#enter sib2, iclass 40, count 2 2006.173.14:00:05.34#ibcon#flushed, iclass 40, count 2 2006.173.14:00:05.34#ibcon#about to write, iclass 40, count 2 2006.173.14:00:05.34#ibcon#wrote, iclass 40, count 2 2006.173.14:00:05.34#ibcon#about to read 3, iclass 40, count 2 2006.173.14:00:05.36#ibcon#read 3, iclass 40, count 2 2006.173.14:00:05.36#ibcon#about to read 4, iclass 40, count 2 2006.173.14:00:05.36#ibcon#read 4, iclass 40, count 2 2006.173.14:00:05.36#ibcon#about to read 5, iclass 40, count 2 2006.173.14:00:05.36#ibcon#read 5, iclass 40, count 2 2006.173.14:00:05.36#ibcon#about to read 6, iclass 40, count 2 2006.173.14:00:05.36#ibcon#read 6, iclass 40, count 2 2006.173.14:00:05.36#ibcon#end of sib2, iclass 40, count 2 2006.173.14:00:05.36#ibcon#*mode == 0, iclass 40, count 2 2006.173.14:00:05.36#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.14:00:05.36#ibcon#[27=AT05-04\r\n] 2006.173.14:00:05.36#ibcon#*before write, iclass 40, count 2 2006.173.14:00:05.36#ibcon#enter sib2, iclass 40, count 2 2006.173.14:00:05.36#ibcon#flushed, iclass 40, count 2 2006.173.14:00:05.36#ibcon#about to write, iclass 40, count 2 2006.173.14:00:05.36#ibcon#wrote, iclass 40, count 2 2006.173.14:00:05.36#ibcon#about to read 3, iclass 40, count 2 2006.173.14:00:05.39#ibcon#read 3, iclass 40, count 2 2006.173.14:00:05.39#ibcon#about to read 4, iclass 40, count 2 2006.173.14:00:05.39#ibcon#read 4, iclass 40, count 2 2006.173.14:00:05.39#ibcon#about to read 5, iclass 40, count 2 2006.173.14:00:05.39#ibcon#read 5, iclass 40, count 2 2006.173.14:00:05.39#ibcon#about to read 6, iclass 40, count 2 2006.173.14:00:05.39#ibcon#read 6, iclass 40, count 2 2006.173.14:00:05.39#ibcon#end of sib2, iclass 40, count 2 2006.173.14:00:05.39#ibcon#*after write, iclass 40, count 2 2006.173.14:00:05.39#ibcon#*before return 0, iclass 40, count 2 2006.173.14:00:05.39#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.14:00:05.39#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.14:00:05.39#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.14:00:05.39#ibcon#ireg 7 cls_cnt 0 2006.173.14:00:05.39#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.14:00:05.51#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.14:00:05.51#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.14:00:05.51#ibcon#enter wrdev, iclass 40, count 0 2006.173.14:00:05.51#ibcon#first serial, iclass 40, count 0 2006.173.14:00:05.51#ibcon#enter sib2, iclass 40, count 0 2006.173.14:00:05.51#ibcon#flushed, iclass 40, count 0 2006.173.14:00:05.51#ibcon#about to write, iclass 40, count 0 2006.173.14:00:05.51#ibcon#wrote, iclass 40, count 0 2006.173.14:00:05.51#ibcon#about to read 3, iclass 40, count 0 2006.173.14:00:05.53#ibcon#read 3, iclass 40, count 0 2006.173.14:00:05.53#ibcon#about to read 4, iclass 40, count 0 2006.173.14:00:05.53#ibcon#read 4, iclass 40, count 0 2006.173.14:00:05.53#ibcon#about to read 5, iclass 40, count 0 2006.173.14:00:05.53#ibcon#read 5, iclass 40, count 0 2006.173.14:00:05.53#ibcon#about to read 6, iclass 40, count 0 2006.173.14:00:05.53#ibcon#read 6, iclass 40, count 0 2006.173.14:00:05.53#ibcon#end of sib2, iclass 40, count 0 2006.173.14:00:05.53#ibcon#*mode == 0, iclass 40, count 0 2006.173.14:00:05.53#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.14:00:05.53#ibcon#[27=USB\r\n] 2006.173.14:00:05.53#ibcon#*before write, iclass 40, count 0 2006.173.14:00:05.53#ibcon#enter sib2, iclass 40, count 0 2006.173.14:00:05.53#ibcon#flushed, iclass 40, count 0 2006.173.14:00:05.53#ibcon#about to write, iclass 40, count 0 2006.173.14:00:05.53#ibcon#wrote, iclass 40, count 0 2006.173.14:00:05.53#ibcon#about to read 3, iclass 40, count 0 2006.173.14:00:05.56#ibcon#read 3, iclass 40, count 0 2006.173.14:00:05.56#ibcon#about to read 4, iclass 40, count 0 2006.173.14:00:05.56#ibcon#read 4, iclass 40, count 0 2006.173.14:00:05.56#ibcon#about to read 5, iclass 40, count 0 2006.173.14:00:05.56#ibcon#read 5, iclass 40, count 0 2006.173.14:00:05.56#ibcon#about to read 6, iclass 40, count 0 2006.173.14:00:05.56#ibcon#read 6, iclass 40, count 0 2006.173.14:00:05.56#ibcon#end of sib2, iclass 40, count 0 2006.173.14:00:05.56#ibcon#*after write, iclass 40, count 0 2006.173.14:00:05.56#ibcon#*before return 0, iclass 40, count 0 2006.173.14:00:05.56#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.14:00:05.56#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.14:00:05.56#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.14:00:05.56#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.14:00:05.56$vck44/vblo=6,719.99 2006.173.14:00:05.56#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.14:00:05.56#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.14:00:05.56#ibcon#ireg 17 cls_cnt 0 2006.173.14:00:05.56#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.14:00:05.56#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.14:00:05.56#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.14:00:05.56#ibcon#enter wrdev, iclass 4, count 0 2006.173.14:00:05.56#ibcon#first serial, iclass 4, count 0 2006.173.14:00:05.56#ibcon#enter sib2, iclass 4, count 0 2006.173.14:00:05.56#ibcon#flushed, iclass 4, count 0 2006.173.14:00:05.56#ibcon#about to write, iclass 4, count 0 2006.173.14:00:05.56#ibcon#wrote, iclass 4, count 0 2006.173.14:00:05.56#ibcon#about to read 3, iclass 4, count 0 2006.173.14:00:05.58#ibcon#read 3, iclass 4, count 0 2006.173.14:00:05.58#ibcon#about to read 4, iclass 4, count 0 2006.173.14:00:05.58#ibcon#read 4, iclass 4, count 0 2006.173.14:00:05.58#ibcon#about to read 5, iclass 4, count 0 2006.173.14:00:05.58#ibcon#read 5, iclass 4, count 0 2006.173.14:00:05.58#ibcon#about to read 6, iclass 4, count 0 2006.173.14:00:05.58#ibcon#read 6, iclass 4, count 0 2006.173.14:00:05.58#ibcon#end of sib2, iclass 4, count 0 2006.173.14:00:05.58#ibcon#*mode == 0, iclass 4, count 0 2006.173.14:00:05.58#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.14:00:05.58#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.14:00:05.58#ibcon#*before write, iclass 4, count 0 2006.173.14:00:05.58#ibcon#enter sib2, iclass 4, count 0 2006.173.14:00:05.58#ibcon#flushed, iclass 4, count 0 2006.173.14:00:05.58#ibcon#about to write, iclass 4, count 0 2006.173.14:00:05.58#ibcon#wrote, iclass 4, count 0 2006.173.14:00:05.58#ibcon#about to read 3, iclass 4, count 0 2006.173.14:00:05.62#ibcon#read 3, iclass 4, count 0 2006.173.14:00:05.62#ibcon#about to read 4, iclass 4, count 0 2006.173.14:00:05.62#ibcon#read 4, iclass 4, count 0 2006.173.14:00:05.62#ibcon#about to read 5, iclass 4, count 0 2006.173.14:00:05.62#ibcon#read 5, iclass 4, count 0 2006.173.14:00:05.62#ibcon#about to read 6, iclass 4, count 0 2006.173.14:00:05.62#ibcon#read 6, iclass 4, count 0 2006.173.14:00:05.62#ibcon#end of sib2, iclass 4, count 0 2006.173.14:00:05.62#ibcon#*after write, iclass 4, count 0 2006.173.14:00:05.62#ibcon#*before return 0, iclass 4, count 0 2006.173.14:00:05.62#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.14:00:05.62#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.14:00:05.62#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.14:00:05.62#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.14:00:05.62$vck44/vb=6,4 2006.173.14:00:05.62#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.14:00:05.62#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.14:00:05.62#ibcon#ireg 11 cls_cnt 2 2006.173.14:00:05.62#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.14:00:05.68#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.14:00:05.68#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.14:00:05.68#ibcon#enter wrdev, iclass 6, count 2 2006.173.14:00:05.68#ibcon#first serial, iclass 6, count 2 2006.173.14:00:05.68#ibcon#enter sib2, iclass 6, count 2 2006.173.14:00:05.68#ibcon#flushed, iclass 6, count 2 2006.173.14:00:05.68#ibcon#about to write, iclass 6, count 2 2006.173.14:00:05.68#ibcon#wrote, iclass 6, count 2 2006.173.14:00:05.68#ibcon#about to read 3, iclass 6, count 2 2006.173.14:00:05.70#ibcon#read 3, iclass 6, count 2 2006.173.14:00:05.70#ibcon#about to read 4, iclass 6, count 2 2006.173.14:00:05.70#ibcon#read 4, iclass 6, count 2 2006.173.14:00:05.70#ibcon#about to read 5, iclass 6, count 2 2006.173.14:00:05.70#ibcon#read 5, iclass 6, count 2 2006.173.14:00:05.70#ibcon#about to read 6, iclass 6, count 2 2006.173.14:00:05.70#ibcon#read 6, iclass 6, count 2 2006.173.14:00:05.70#ibcon#end of sib2, iclass 6, count 2 2006.173.14:00:05.70#ibcon#*mode == 0, iclass 6, count 2 2006.173.14:00:05.70#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.14:00:05.70#ibcon#[27=AT06-04\r\n] 2006.173.14:00:05.70#ibcon#*before write, iclass 6, count 2 2006.173.14:00:05.70#ibcon#enter sib2, iclass 6, count 2 2006.173.14:00:05.70#ibcon#flushed, iclass 6, count 2 2006.173.14:00:05.70#ibcon#about to write, iclass 6, count 2 2006.173.14:00:05.70#ibcon#wrote, iclass 6, count 2 2006.173.14:00:05.70#ibcon#about to read 3, iclass 6, count 2 2006.173.14:00:05.73#ibcon#read 3, iclass 6, count 2 2006.173.14:00:05.73#ibcon#about to read 4, iclass 6, count 2 2006.173.14:00:05.73#ibcon#read 4, iclass 6, count 2 2006.173.14:00:05.73#ibcon#about to read 5, iclass 6, count 2 2006.173.14:00:05.73#ibcon#read 5, iclass 6, count 2 2006.173.14:00:05.73#ibcon#about to read 6, iclass 6, count 2 2006.173.14:00:05.73#ibcon#read 6, iclass 6, count 2 2006.173.14:00:05.73#ibcon#end of sib2, iclass 6, count 2 2006.173.14:00:05.73#ibcon#*after write, iclass 6, count 2 2006.173.14:00:05.73#ibcon#*before return 0, iclass 6, count 2 2006.173.14:00:05.73#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.14:00:05.73#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.14:00:05.73#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.14:00:05.73#ibcon#ireg 7 cls_cnt 0 2006.173.14:00:05.73#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.14:00:05.85#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.14:00:05.85#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.14:00:05.85#ibcon#enter wrdev, iclass 6, count 0 2006.173.14:00:05.85#ibcon#first serial, iclass 6, count 0 2006.173.14:00:05.85#ibcon#enter sib2, iclass 6, count 0 2006.173.14:00:05.85#ibcon#flushed, iclass 6, count 0 2006.173.14:00:05.85#ibcon#about to write, iclass 6, count 0 2006.173.14:00:05.85#ibcon#wrote, iclass 6, count 0 2006.173.14:00:05.85#ibcon#about to read 3, iclass 6, count 0 2006.173.14:00:05.87#ibcon#read 3, iclass 6, count 0 2006.173.14:00:05.87#ibcon#about to read 4, iclass 6, count 0 2006.173.14:00:05.87#ibcon#read 4, iclass 6, count 0 2006.173.14:00:05.87#ibcon#about to read 5, iclass 6, count 0 2006.173.14:00:05.87#ibcon#read 5, iclass 6, count 0 2006.173.14:00:05.87#ibcon#about to read 6, iclass 6, count 0 2006.173.14:00:05.87#ibcon#read 6, iclass 6, count 0 2006.173.14:00:05.87#ibcon#end of sib2, iclass 6, count 0 2006.173.14:00:05.87#ibcon#*mode == 0, iclass 6, count 0 2006.173.14:00:05.87#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.14:00:05.87#ibcon#[27=USB\r\n] 2006.173.14:00:05.87#ibcon#*before write, iclass 6, count 0 2006.173.14:00:05.87#ibcon#enter sib2, iclass 6, count 0 2006.173.14:00:05.87#ibcon#flushed, iclass 6, count 0 2006.173.14:00:05.87#ibcon#about to write, iclass 6, count 0 2006.173.14:00:05.87#ibcon#wrote, iclass 6, count 0 2006.173.14:00:05.87#ibcon#about to read 3, iclass 6, count 0 2006.173.14:00:05.90#ibcon#read 3, iclass 6, count 0 2006.173.14:00:05.90#ibcon#about to read 4, iclass 6, count 0 2006.173.14:00:05.90#ibcon#read 4, iclass 6, count 0 2006.173.14:00:05.90#ibcon#about to read 5, iclass 6, count 0 2006.173.14:00:05.90#ibcon#read 5, iclass 6, count 0 2006.173.14:00:05.90#ibcon#about to read 6, iclass 6, count 0 2006.173.14:00:05.90#ibcon#read 6, iclass 6, count 0 2006.173.14:00:05.90#ibcon#end of sib2, iclass 6, count 0 2006.173.14:00:05.90#ibcon#*after write, iclass 6, count 0 2006.173.14:00:05.90#ibcon#*before return 0, iclass 6, count 0 2006.173.14:00:05.90#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.14:00:05.90#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.14:00:05.90#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.14:00:05.90#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.14:00:05.90$vck44/vblo=7,734.99 2006.173.14:00:05.90#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.14:00:05.90#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.14:00:05.90#ibcon#ireg 17 cls_cnt 0 2006.173.14:00:05.90#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.14:00:05.90#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.14:00:05.90#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.14:00:05.90#ibcon#enter wrdev, iclass 10, count 0 2006.173.14:00:05.90#ibcon#first serial, iclass 10, count 0 2006.173.14:00:05.90#ibcon#enter sib2, iclass 10, count 0 2006.173.14:00:05.90#ibcon#flushed, iclass 10, count 0 2006.173.14:00:05.90#ibcon#about to write, iclass 10, count 0 2006.173.14:00:05.90#ibcon#wrote, iclass 10, count 0 2006.173.14:00:05.90#ibcon#about to read 3, iclass 10, count 0 2006.173.14:00:05.92#ibcon#read 3, iclass 10, count 0 2006.173.14:00:05.92#ibcon#about to read 4, iclass 10, count 0 2006.173.14:00:05.92#ibcon#read 4, iclass 10, count 0 2006.173.14:00:05.92#ibcon#about to read 5, iclass 10, count 0 2006.173.14:00:05.92#ibcon#read 5, iclass 10, count 0 2006.173.14:00:05.92#ibcon#about to read 6, iclass 10, count 0 2006.173.14:00:05.92#ibcon#read 6, iclass 10, count 0 2006.173.14:00:05.92#ibcon#end of sib2, iclass 10, count 0 2006.173.14:00:05.92#ibcon#*mode == 0, iclass 10, count 0 2006.173.14:00:05.92#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.14:00:05.92#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.14:00:05.92#ibcon#*before write, iclass 10, count 0 2006.173.14:00:05.92#ibcon#enter sib2, iclass 10, count 0 2006.173.14:00:05.92#ibcon#flushed, iclass 10, count 0 2006.173.14:00:05.92#ibcon#about to write, iclass 10, count 0 2006.173.14:00:05.92#ibcon#wrote, iclass 10, count 0 2006.173.14:00:05.92#ibcon#about to read 3, iclass 10, count 0 2006.173.14:00:05.96#ibcon#read 3, iclass 10, count 0 2006.173.14:00:05.96#ibcon#about to read 4, iclass 10, count 0 2006.173.14:00:05.96#ibcon#read 4, iclass 10, count 0 2006.173.14:00:05.96#ibcon#about to read 5, iclass 10, count 0 2006.173.14:00:05.96#ibcon#read 5, iclass 10, count 0 2006.173.14:00:05.96#ibcon#about to read 6, iclass 10, count 0 2006.173.14:00:05.96#ibcon#read 6, iclass 10, count 0 2006.173.14:00:05.96#ibcon#end of sib2, iclass 10, count 0 2006.173.14:00:05.96#ibcon#*after write, iclass 10, count 0 2006.173.14:00:05.96#ibcon#*before return 0, iclass 10, count 0 2006.173.14:00:05.96#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.14:00:05.96#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.14:00:05.96#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.14:00:05.96#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.14:00:05.96$vck44/vb=7,4 2006.173.14:00:05.96#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.14:00:05.96#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.14:00:05.96#ibcon#ireg 11 cls_cnt 2 2006.173.14:00:05.96#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.14:00:06.02#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.14:00:06.02#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.14:00:06.02#ibcon#enter wrdev, iclass 12, count 2 2006.173.14:00:06.02#ibcon#first serial, iclass 12, count 2 2006.173.14:00:06.02#ibcon#enter sib2, iclass 12, count 2 2006.173.14:00:06.02#ibcon#flushed, iclass 12, count 2 2006.173.14:00:06.02#ibcon#about to write, iclass 12, count 2 2006.173.14:00:06.02#ibcon#wrote, iclass 12, count 2 2006.173.14:00:06.02#ibcon#about to read 3, iclass 12, count 2 2006.173.14:00:06.04#ibcon#read 3, iclass 12, count 2 2006.173.14:00:06.04#ibcon#about to read 4, iclass 12, count 2 2006.173.14:00:06.04#ibcon#read 4, iclass 12, count 2 2006.173.14:00:06.04#ibcon#about to read 5, iclass 12, count 2 2006.173.14:00:06.04#ibcon#read 5, iclass 12, count 2 2006.173.14:00:06.04#ibcon#about to read 6, iclass 12, count 2 2006.173.14:00:06.04#ibcon#read 6, iclass 12, count 2 2006.173.14:00:06.04#ibcon#end of sib2, iclass 12, count 2 2006.173.14:00:06.04#ibcon#*mode == 0, iclass 12, count 2 2006.173.14:00:06.04#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.14:00:06.04#ibcon#[27=AT07-04\r\n] 2006.173.14:00:06.04#ibcon#*before write, iclass 12, count 2 2006.173.14:00:06.04#ibcon#enter sib2, iclass 12, count 2 2006.173.14:00:06.04#ibcon#flushed, iclass 12, count 2 2006.173.14:00:06.04#ibcon#about to write, iclass 12, count 2 2006.173.14:00:06.04#ibcon#wrote, iclass 12, count 2 2006.173.14:00:06.04#ibcon#about to read 3, iclass 12, count 2 2006.173.14:00:06.07#ibcon#read 3, iclass 12, count 2 2006.173.14:00:06.07#ibcon#about to read 4, iclass 12, count 2 2006.173.14:00:06.07#ibcon#read 4, iclass 12, count 2 2006.173.14:00:06.07#ibcon#about to read 5, iclass 12, count 2 2006.173.14:00:06.07#ibcon#read 5, iclass 12, count 2 2006.173.14:00:06.07#ibcon#about to read 6, iclass 12, count 2 2006.173.14:00:06.07#ibcon#read 6, iclass 12, count 2 2006.173.14:00:06.07#ibcon#end of sib2, iclass 12, count 2 2006.173.14:00:06.07#ibcon#*after write, iclass 12, count 2 2006.173.14:00:06.07#ibcon#*before return 0, iclass 12, count 2 2006.173.14:00:06.07#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.14:00:06.07#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.14:00:06.07#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.14:00:06.07#ibcon#ireg 7 cls_cnt 0 2006.173.14:00:06.07#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.14:00:06.19#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.14:00:06.19#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.14:00:06.19#ibcon#enter wrdev, iclass 12, count 0 2006.173.14:00:06.19#ibcon#first serial, iclass 12, count 0 2006.173.14:00:06.19#ibcon#enter sib2, iclass 12, count 0 2006.173.14:00:06.19#ibcon#flushed, iclass 12, count 0 2006.173.14:00:06.19#ibcon#about to write, iclass 12, count 0 2006.173.14:00:06.19#ibcon#wrote, iclass 12, count 0 2006.173.14:00:06.19#ibcon#about to read 3, iclass 12, count 0 2006.173.14:00:06.21#ibcon#read 3, iclass 12, count 0 2006.173.14:00:06.21#ibcon#about to read 4, iclass 12, count 0 2006.173.14:00:06.21#ibcon#read 4, iclass 12, count 0 2006.173.14:00:06.21#ibcon#about to read 5, iclass 12, count 0 2006.173.14:00:06.21#ibcon#read 5, iclass 12, count 0 2006.173.14:00:06.21#ibcon#about to read 6, iclass 12, count 0 2006.173.14:00:06.21#ibcon#read 6, iclass 12, count 0 2006.173.14:00:06.21#ibcon#end of sib2, iclass 12, count 0 2006.173.14:00:06.21#ibcon#*mode == 0, iclass 12, count 0 2006.173.14:00:06.21#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.14:00:06.21#ibcon#[27=USB\r\n] 2006.173.14:00:06.21#ibcon#*before write, iclass 12, count 0 2006.173.14:00:06.21#ibcon#enter sib2, iclass 12, count 0 2006.173.14:00:06.21#ibcon#flushed, iclass 12, count 0 2006.173.14:00:06.21#ibcon#about to write, iclass 12, count 0 2006.173.14:00:06.21#ibcon#wrote, iclass 12, count 0 2006.173.14:00:06.21#ibcon#about to read 3, iclass 12, count 0 2006.173.14:00:06.24#ibcon#read 3, iclass 12, count 0 2006.173.14:00:06.24#ibcon#about to read 4, iclass 12, count 0 2006.173.14:00:06.24#ibcon#read 4, iclass 12, count 0 2006.173.14:00:06.24#ibcon#about to read 5, iclass 12, count 0 2006.173.14:00:06.24#ibcon#read 5, iclass 12, count 0 2006.173.14:00:06.24#ibcon#about to read 6, iclass 12, count 0 2006.173.14:00:06.24#ibcon#read 6, iclass 12, count 0 2006.173.14:00:06.24#ibcon#end of sib2, iclass 12, count 0 2006.173.14:00:06.24#ibcon#*after write, iclass 12, count 0 2006.173.14:00:06.24#ibcon#*before return 0, iclass 12, count 0 2006.173.14:00:06.24#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.14:00:06.24#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.14:00:06.24#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.14:00:06.24#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.14:00:06.24$vck44/vblo=8,744.99 2006.173.14:00:06.24#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.14:00:06.24#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.14:00:06.24#ibcon#ireg 17 cls_cnt 0 2006.173.14:00:06.24#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.14:00:06.24#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.14:00:06.24#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.14:00:06.24#ibcon#enter wrdev, iclass 14, count 0 2006.173.14:00:06.24#ibcon#first serial, iclass 14, count 0 2006.173.14:00:06.24#ibcon#enter sib2, iclass 14, count 0 2006.173.14:00:06.24#ibcon#flushed, iclass 14, count 0 2006.173.14:00:06.24#ibcon#about to write, iclass 14, count 0 2006.173.14:00:06.24#ibcon#wrote, iclass 14, count 0 2006.173.14:00:06.24#ibcon#about to read 3, iclass 14, count 0 2006.173.14:00:06.26#ibcon#read 3, iclass 14, count 0 2006.173.14:00:06.26#ibcon#about to read 4, iclass 14, count 0 2006.173.14:00:06.26#ibcon#read 4, iclass 14, count 0 2006.173.14:00:06.26#ibcon#about to read 5, iclass 14, count 0 2006.173.14:00:06.26#ibcon#read 5, iclass 14, count 0 2006.173.14:00:06.26#ibcon#about to read 6, iclass 14, count 0 2006.173.14:00:06.26#ibcon#read 6, iclass 14, count 0 2006.173.14:00:06.26#ibcon#end of sib2, iclass 14, count 0 2006.173.14:00:06.26#ibcon#*mode == 0, iclass 14, count 0 2006.173.14:00:06.26#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.14:00:06.26#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.14:00:06.26#ibcon#*before write, iclass 14, count 0 2006.173.14:00:06.26#ibcon#enter sib2, iclass 14, count 0 2006.173.14:00:06.26#ibcon#flushed, iclass 14, count 0 2006.173.14:00:06.26#ibcon#about to write, iclass 14, count 0 2006.173.14:00:06.26#ibcon#wrote, iclass 14, count 0 2006.173.14:00:06.26#ibcon#about to read 3, iclass 14, count 0 2006.173.14:00:06.30#ibcon#read 3, iclass 14, count 0 2006.173.14:00:06.30#ibcon#about to read 4, iclass 14, count 0 2006.173.14:00:06.30#ibcon#read 4, iclass 14, count 0 2006.173.14:00:06.30#ibcon#about to read 5, iclass 14, count 0 2006.173.14:00:06.30#ibcon#read 5, iclass 14, count 0 2006.173.14:00:06.30#ibcon#about to read 6, iclass 14, count 0 2006.173.14:00:06.30#ibcon#read 6, iclass 14, count 0 2006.173.14:00:06.30#ibcon#end of sib2, iclass 14, count 0 2006.173.14:00:06.30#ibcon#*after write, iclass 14, count 0 2006.173.14:00:06.30#ibcon#*before return 0, iclass 14, count 0 2006.173.14:00:06.30#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.14:00:06.30#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.14:00:06.30#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.14:00:06.30#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.14:00:06.30$vck44/vb=8,4 2006.173.14:00:06.30#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.14:00:06.30#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.14:00:06.30#ibcon#ireg 11 cls_cnt 2 2006.173.14:00:06.30#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.14:00:06.36#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.14:00:06.36#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.14:00:06.36#ibcon#enter wrdev, iclass 16, count 2 2006.173.14:00:06.36#ibcon#first serial, iclass 16, count 2 2006.173.14:00:06.36#ibcon#enter sib2, iclass 16, count 2 2006.173.14:00:06.36#ibcon#flushed, iclass 16, count 2 2006.173.14:00:06.36#ibcon#about to write, iclass 16, count 2 2006.173.14:00:06.36#ibcon#wrote, iclass 16, count 2 2006.173.14:00:06.36#ibcon#about to read 3, iclass 16, count 2 2006.173.14:00:06.38#ibcon#read 3, iclass 16, count 2 2006.173.14:00:06.38#ibcon#about to read 4, iclass 16, count 2 2006.173.14:00:06.38#ibcon#read 4, iclass 16, count 2 2006.173.14:00:06.38#ibcon#about to read 5, iclass 16, count 2 2006.173.14:00:06.38#ibcon#read 5, iclass 16, count 2 2006.173.14:00:06.38#ibcon#about to read 6, iclass 16, count 2 2006.173.14:00:06.38#ibcon#read 6, iclass 16, count 2 2006.173.14:00:06.38#ibcon#end of sib2, iclass 16, count 2 2006.173.14:00:06.38#ibcon#*mode == 0, iclass 16, count 2 2006.173.14:00:06.38#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.14:00:06.38#ibcon#[27=AT08-04\r\n] 2006.173.14:00:06.38#ibcon#*before write, iclass 16, count 2 2006.173.14:00:06.38#ibcon#enter sib2, iclass 16, count 2 2006.173.14:00:06.38#ibcon#flushed, iclass 16, count 2 2006.173.14:00:06.38#ibcon#about to write, iclass 16, count 2 2006.173.14:00:06.38#ibcon#wrote, iclass 16, count 2 2006.173.14:00:06.38#ibcon#about to read 3, iclass 16, count 2 2006.173.14:00:06.41#ibcon#read 3, iclass 16, count 2 2006.173.14:00:06.41#ibcon#about to read 4, iclass 16, count 2 2006.173.14:00:06.41#ibcon#read 4, iclass 16, count 2 2006.173.14:00:06.41#ibcon#about to read 5, iclass 16, count 2 2006.173.14:00:06.41#ibcon#read 5, iclass 16, count 2 2006.173.14:00:06.41#ibcon#about to read 6, iclass 16, count 2 2006.173.14:00:06.41#ibcon#read 6, iclass 16, count 2 2006.173.14:00:06.41#ibcon#end of sib2, iclass 16, count 2 2006.173.14:00:06.41#ibcon#*after write, iclass 16, count 2 2006.173.14:00:06.41#ibcon#*before return 0, iclass 16, count 2 2006.173.14:00:06.41#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.14:00:06.41#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.14:00:06.41#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.14:00:06.41#ibcon#ireg 7 cls_cnt 0 2006.173.14:00:06.41#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.14:00:06.53#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.14:00:06.53#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.14:00:06.53#ibcon#enter wrdev, iclass 16, count 0 2006.173.14:00:06.53#ibcon#first serial, iclass 16, count 0 2006.173.14:00:06.53#ibcon#enter sib2, iclass 16, count 0 2006.173.14:00:06.53#ibcon#flushed, iclass 16, count 0 2006.173.14:00:06.53#ibcon#about to write, iclass 16, count 0 2006.173.14:00:06.53#ibcon#wrote, iclass 16, count 0 2006.173.14:00:06.53#ibcon#about to read 3, iclass 16, count 0 2006.173.14:00:06.55#ibcon#read 3, iclass 16, count 0 2006.173.14:00:06.55#ibcon#about to read 4, iclass 16, count 0 2006.173.14:00:06.55#ibcon#read 4, iclass 16, count 0 2006.173.14:00:06.55#ibcon#about to read 5, iclass 16, count 0 2006.173.14:00:06.55#ibcon#read 5, iclass 16, count 0 2006.173.14:00:06.55#ibcon#about to read 6, iclass 16, count 0 2006.173.14:00:06.55#ibcon#read 6, iclass 16, count 0 2006.173.14:00:06.55#ibcon#end of sib2, iclass 16, count 0 2006.173.14:00:06.55#ibcon#*mode == 0, iclass 16, count 0 2006.173.14:00:06.55#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.14:00:06.55#ibcon#[27=USB\r\n] 2006.173.14:00:06.55#ibcon#*before write, iclass 16, count 0 2006.173.14:00:06.55#ibcon#enter sib2, iclass 16, count 0 2006.173.14:00:06.55#ibcon#flushed, iclass 16, count 0 2006.173.14:00:06.55#ibcon#about to write, iclass 16, count 0 2006.173.14:00:06.55#ibcon#wrote, iclass 16, count 0 2006.173.14:00:06.55#ibcon#about to read 3, iclass 16, count 0 2006.173.14:00:06.58#ibcon#read 3, iclass 16, count 0 2006.173.14:00:06.58#ibcon#about to read 4, iclass 16, count 0 2006.173.14:00:06.58#ibcon#read 4, iclass 16, count 0 2006.173.14:00:06.58#ibcon#about to read 5, iclass 16, count 0 2006.173.14:00:06.58#ibcon#read 5, iclass 16, count 0 2006.173.14:00:06.58#ibcon#about to read 6, iclass 16, count 0 2006.173.14:00:06.58#ibcon#read 6, iclass 16, count 0 2006.173.14:00:06.58#ibcon#end of sib2, iclass 16, count 0 2006.173.14:00:06.58#ibcon#*after write, iclass 16, count 0 2006.173.14:00:06.58#ibcon#*before return 0, iclass 16, count 0 2006.173.14:00:06.58#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.14:00:06.58#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.14:00:06.58#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.14:00:06.58#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.14:00:06.58$vck44/vabw=wide 2006.173.14:00:06.58#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.14:00:06.58#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.14:00:06.58#ibcon#ireg 8 cls_cnt 0 2006.173.14:00:06.58#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.14:00:06.58#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.14:00:06.58#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.14:00:06.58#ibcon#enter wrdev, iclass 18, count 0 2006.173.14:00:06.58#ibcon#first serial, iclass 18, count 0 2006.173.14:00:06.58#ibcon#enter sib2, iclass 18, count 0 2006.173.14:00:06.58#ibcon#flushed, iclass 18, count 0 2006.173.14:00:06.58#ibcon#about to write, iclass 18, count 0 2006.173.14:00:06.58#ibcon#wrote, iclass 18, count 0 2006.173.14:00:06.58#ibcon#about to read 3, iclass 18, count 0 2006.173.14:00:06.60#ibcon#read 3, iclass 18, count 0 2006.173.14:00:06.60#ibcon#about to read 4, iclass 18, count 0 2006.173.14:00:06.60#ibcon#read 4, iclass 18, count 0 2006.173.14:00:06.60#ibcon#about to read 5, iclass 18, count 0 2006.173.14:00:06.60#ibcon#read 5, iclass 18, count 0 2006.173.14:00:06.60#ibcon#about to read 6, iclass 18, count 0 2006.173.14:00:06.60#ibcon#read 6, iclass 18, count 0 2006.173.14:00:06.60#ibcon#end of sib2, iclass 18, count 0 2006.173.14:00:06.60#ibcon#*mode == 0, iclass 18, count 0 2006.173.14:00:06.60#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.14:00:06.60#ibcon#[25=BW32\r\n] 2006.173.14:00:06.60#ibcon#*before write, iclass 18, count 0 2006.173.14:00:06.60#ibcon#enter sib2, iclass 18, count 0 2006.173.14:00:06.60#ibcon#flushed, iclass 18, count 0 2006.173.14:00:06.60#ibcon#about to write, iclass 18, count 0 2006.173.14:00:06.60#ibcon#wrote, iclass 18, count 0 2006.173.14:00:06.60#ibcon#about to read 3, iclass 18, count 0 2006.173.14:00:06.63#ibcon#read 3, iclass 18, count 0 2006.173.14:00:06.63#ibcon#about to read 4, iclass 18, count 0 2006.173.14:00:06.63#ibcon#read 4, iclass 18, count 0 2006.173.14:00:06.63#ibcon#about to read 5, iclass 18, count 0 2006.173.14:00:06.63#ibcon#read 5, iclass 18, count 0 2006.173.14:00:06.63#ibcon#about to read 6, iclass 18, count 0 2006.173.14:00:06.63#ibcon#read 6, iclass 18, count 0 2006.173.14:00:06.63#ibcon#end of sib2, iclass 18, count 0 2006.173.14:00:06.63#ibcon#*after write, iclass 18, count 0 2006.173.14:00:06.63#ibcon#*before return 0, iclass 18, count 0 2006.173.14:00:06.63#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.14:00:06.63#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.14:00:06.63#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.14:00:06.63#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.14:00:06.63$vck44/vbbw=wide 2006.173.14:00:06.63#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.14:00:06.63#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.14:00:06.63#ibcon#ireg 8 cls_cnt 0 2006.173.14:00:06.63#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.14:00:06.70#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.14:00:06.70#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.14:00:06.70#ibcon#enter wrdev, iclass 20, count 0 2006.173.14:00:06.70#ibcon#first serial, iclass 20, count 0 2006.173.14:00:06.70#ibcon#enter sib2, iclass 20, count 0 2006.173.14:00:06.70#ibcon#flushed, iclass 20, count 0 2006.173.14:00:06.70#ibcon#about to write, iclass 20, count 0 2006.173.14:00:06.70#ibcon#wrote, iclass 20, count 0 2006.173.14:00:06.70#ibcon#about to read 3, iclass 20, count 0 2006.173.14:00:06.72#ibcon#read 3, iclass 20, count 0 2006.173.14:00:06.72#ibcon#about to read 4, iclass 20, count 0 2006.173.14:00:06.72#ibcon#read 4, iclass 20, count 0 2006.173.14:00:06.72#ibcon#about to read 5, iclass 20, count 0 2006.173.14:00:06.72#ibcon#read 5, iclass 20, count 0 2006.173.14:00:06.72#ibcon#about to read 6, iclass 20, count 0 2006.173.14:00:06.72#ibcon#read 6, iclass 20, count 0 2006.173.14:00:06.72#ibcon#end of sib2, iclass 20, count 0 2006.173.14:00:06.72#ibcon#*mode == 0, iclass 20, count 0 2006.173.14:00:06.72#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.14:00:06.72#ibcon#[27=BW32\r\n] 2006.173.14:00:06.72#ibcon#*before write, iclass 20, count 0 2006.173.14:00:06.72#ibcon#enter sib2, iclass 20, count 0 2006.173.14:00:06.72#ibcon#flushed, iclass 20, count 0 2006.173.14:00:06.72#ibcon#about to write, iclass 20, count 0 2006.173.14:00:06.72#ibcon#wrote, iclass 20, count 0 2006.173.14:00:06.72#ibcon#about to read 3, iclass 20, count 0 2006.173.14:00:06.75#ibcon#read 3, iclass 20, count 0 2006.173.14:00:06.75#ibcon#about to read 4, iclass 20, count 0 2006.173.14:00:06.75#ibcon#read 4, iclass 20, count 0 2006.173.14:00:06.75#ibcon#about to read 5, iclass 20, count 0 2006.173.14:00:06.75#ibcon#read 5, iclass 20, count 0 2006.173.14:00:06.75#ibcon#about to read 6, iclass 20, count 0 2006.173.14:00:06.75#ibcon#read 6, iclass 20, count 0 2006.173.14:00:06.75#ibcon#end of sib2, iclass 20, count 0 2006.173.14:00:06.75#ibcon#*after write, iclass 20, count 0 2006.173.14:00:06.75#ibcon#*before return 0, iclass 20, count 0 2006.173.14:00:06.75#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.14:00:06.75#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.14:00:06.75#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.14:00:06.75#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.14:00:06.75$setupk4/ifdk4 2006.173.14:00:06.75$ifdk4/lo= 2006.173.14:00:06.75$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.14:00:06.75$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.14:00:06.75$ifdk4/patch= 2006.173.14:00:06.75$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.14:00:06.75$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.14:00:06.75$setupk4/!*+20s 2006.173.14:00:12.56#abcon#<5=/04 0.7 1.4 21.771001003.7\r\n> 2006.173.14:00:12.58#abcon#{5=INTERFACE CLEAR} 2006.173.14:00:12.64#abcon#[5=S1D000X0/0*\r\n] 2006.173.14:00:21.26$setupk4/"tpicd 2006.173.14:00:21.26$setupk4/echo=off 2006.173.14:00:21.26$setupk4/xlog=off 2006.173.14:00:21.26:!2006.173.14:01:45 2006.173.14:00:41.14#trakl#Source acquired 2006.173.14:00:41.14#flagr#flagr/antenna,acquired 2006.173.14:01:45.00:preob 2006.173.14:01:45.13/onsource/TRACKING 2006.173.14:01:45.13:!2006.173.14:01:55 2006.173.14:01:55.00:"tape 2006.173.14:01:55.00:"st=record 2006.173.14:01:55.00:data_valid=on 2006.173.14:01:55.00:midob 2006.173.14:01:56.13/onsource/TRACKING 2006.173.14:01:56.13/wx/21.76,1003.7,100 2006.173.14:01:56.32/cable/+6.5054E-03 2006.173.14:01:57.41/va/01,07,usb,yes,48,52 2006.173.14:01:57.41/va/02,06,usb,yes,48,49 2006.173.14:01:57.41/va/03,05,usb,yes,61,63 2006.173.14:01:57.41/va/04,06,usb,yes,49,52 2006.173.14:01:57.41/va/05,04,usb,yes,39,40 2006.173.14:01:57.41/va/06,03,usb,yes,54,54 2006.173.14:01:57.41/va/07,04,usb,yes,44,46 2006.173.14:01:57.41/va/08,04,usb,yes,38,45 2006.173.14:01:57.64/valo/01,524.99,yes,locked 2006.173.14:01:57.64/valo/02,534.99,yes,locked 2006.173.14:01:57.64/valo/03,564.99,yes,locked 2006.173.14:01:57.64/valo/04,624.99,yes,locked 2006.173.14:01:57.64/valo/05,734.99,yes,locked 2006.173.14:01:57.64/valo/06,814.99,yes,locked 2006.173.14:01:57.64/valo/07,864.99,yes,locked 2006.173.14:01:57.64/valo/08,884.99,yes,locked 2006.173.14:01:58.73/vb/01,04,usb,yes,38,35 2006.173.14:01:58.73/vb/02,04,usb,yes,40,40 2006.173.14:01:58.73/vb/03,04,usb,yes,37,40 2006.173.14:01:58.73/vb/04,04,usb,yes,42,40 2006.173.14:01:58.73/vb/05,04,usb,yes,33,36 2006.173.14:01:58.73/vb/06,04,usb,yes,38,34 2006.173.14:01:58.73/vb/07,04,usb,yes,38,38 2006.173.14:01:58.73/vb/08,04,usb,yes,34,39 2006.173.14:01:58.96/vblo/01,629.99,yes,locked 2006.173.14:01:58.96/vblo/02,634.99,yes,locked 2006.173.14:01:58.96/vblo/03,649.99,yes,locked 2006.173.14:01:58.96/vblo/04,679.99,yes,locked 2006.173.14:01:58.96/vblo/05,709.99,yes,locked 2006.173.14:01:58.96/vblo/06,719.99,yes,locked 2006.173.14:01:58.96/vblo/07,734.99,yes,locked 2006.173.14:01:58.96/vblo/08,744.99,yes,locked 2006.173.14:01:59.11/vabw/8 2006.173.14:01:59.26/vbbw/8 2006.173.14:01:59.36/xfe/off,on,15.2 2006.173.14:01:59.73/ifatt/23,28,28,28 2006.173.14:02:00.08/fmout-gps/S +3.93E-07 2006.173.14:02:00.12:!2006.173.14:03:45 2006.173.14:03:45.00:data_valid=off 2006.173.14:03:45.00:"et 2006.173.14:03:45.00:!+3s 2006.173.14:03:48.02:"tape 2006.173.14:03:48.02:postob 2006.173.14:03:48.20/cable/+6.5077E-03 2006.173.14:03:48.20/wx/21.74,1003.7,100 2006.173.14:03:49.08/fmout-gps/S +3.94E-07 2006.173.14:03:49.08:scan_name=173-1409,jd0606,40 2006.173.14:03:49.08:source=1741-038,174358.86,-035004.6,2000.0,cw 2006.173.14:03:50.13#flagr#flagr/antenna,new-source 2006.173.14:03:50.14:checkk5 2006.173.14:03:50.55/chk_autoobs//k5ts1/ autoobs is running! 2006.173.14:03:50.94/chk_autoobs//k5ts2/ autoobs is running! 2006.173.14:03:51.35/chk_autoobs//k5ts3/ autoobs is running! 2006.173.14:03:51.73/chk_autoobs//k5ts4/ autoobs is running! 2006.173.14:03:52.11/chk_obsdata//k5ts1/T1731401??a.dat file size is correct (nominal:440MB, actual:440MB). 2006.173.14:03:52.52/chk_obsdata//k5ts2/T1731401??b.dat file size is correct (nominal:440MB, actual:440MB). 2006.173.14:03:52.92/chk_obsdata//k5ts3/T1731401??c.dat file size is correct (nominal:440MB, actual:440MB). 2006.173.14:03:53.34/chk_obsdata//k5ts4/T1731401??d.dat file size is correct (nominal:440MB, actual:440MB). 2006.173.14:03:54.06/k5log//k5ts1_log_newline 2006.173.14:03:54.77/k5log//k5ts2_log_newline 2006.173.14:03:55.46/k5log//k5ts3_log_newline 2006.173.14:03:56.17/k5log//k5ts4_log_newline 2006.173.14:03:56.20/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.14:03:56.20:setupk4=1 2006.173.14:03:56.20$setupk4/echo=on 2006.173.14:03:56.20$setupk4/pcalon 2006.173.14:03:56.20$pcalon/"no phase cal control is implemented here 2006.173.14:03:56.20$setupk4/"tpicd=stop 2006.173.14:03:56.20$setupk4/"rec=synch_on 2006.173.14:03:56.20$setupk4/"rec_mode=128 2006.173.14:03:56.20$setupk4/!* 2006.173.14:03:56.20$setupk4/recpk4 2006.173.14:03:56.20$recpk4/recpatch= 2006.173.14:03:56.20$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.14:03:56.20$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.14:03:56.20$setupk4/vck44 2006.173.14:03:56.20$vck44/valo=1,524.99 2006.173.14:03:56.21#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.14:03:56.21#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.14:03:56.21#ibcon#ireg 17 cls_cnt 0 2006.173.14:03:56.21#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.14:03:56.21#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.14:03:56.21#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.14:03:56.21#ibcon#enter wrdev, iclass 3, count 0 2006.173.14:03:56.21#ibcon#first serial, iclass 3, count 0 2006.173.14:03:56.21#ibcon#enter sib2, iclass 3, count 0 2006.173.14:03:56.21#ibcon#flushed, iclass 3, count 0 2006.173.14:03:56.21#ibcon#about to write, iclass 3, count 0 2006.173.14:03:56.21#ibcon#wrote, iclass 3, count 0 2006.173.14:03:56.21#ibcon#about to read 3, iclass 3, count 0 2006.173.14:03:56.23#ibcon#read 3, iclass 3, count 0 2006.173.14:03:56.23#ibcon#about to read 4, iclass 3, count 0 2006.173.14:03:56.23#ibcon#read 4, iclass 3, count 0 2006.173.14:03:56.23#ibcon#about to read 5, iclass 3, count 0 2006.173.14:03:56.23#ibcon#read 5, iclass 3, count 0 2006.173.14:03:56.23#ibcon#about to read 6, iclass 3, count 0 2006.173.14:03:56.23#ibcon#read 6, iclass 3, count 0 2006.173.14:03:56.23#ibcon#end of sib2, iclass 3, count 0 2006.173.14:03:56.23#ibcon#*mode == 0, iclass 3, count 0 2006.173.14:03:56.23#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.14:03:56.23#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.14:03:56.23#ibcon#*before write, iclass 3, count 0 2006.173.14:03:56.23#ibcon#enter sib2, iclass 3, count 0 2006.173.14:03:56.23#ibcon#flushed, iclass 3, count 0 2006.173.14:03:56.23#ibcon#about to write, iclass 3, count 0 2006.173.14:03:56.23#ibcon#wrote, iclass 3, count 0 2006.173.14:03:56.23#ibcon#about to read 3, iclass 3, count 0 2006.173.14:03:56.28#ibcon#read 3, iclass 3, count 0 2006.173.14:03:56.28#ibcon#about to read 4, iclass 3, count 0 2006.173.14:03:56.28#ibcon#read 4, iclass 3, count 0 2006.173.14:03:56.28#ibcon#about to read 5, iclass 3, count 0 2006.173.14:03:56.28#ibcon#read 5, iclass 3, count 0 2006.173.14:03:56.28#ibcon#about to read 6, iclass 3, count 0 2006.173.14:03:56.28#ibcon#read 6, iclass 3, count 0 2006.173.14:03:56.28#ibcon#end of sib2, iclass 3, count 0 2006.173.14:03:56.28#ibcon#*after write, iclass 3, count 0 2006.173.14:03:56.28#ibcon#*before return 0, iclass 3, count 0 2006.173.14:03:56.28#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.14:03:56.28#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.14:03:56.28#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.14:03:56.28#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.14:03:56.28$vck44/va=1,7 2006.173.14:03:56.28#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.14:03:56.28#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.14:03:56.28#ibcon#ireg 11 cls_cnt 2 2006.173.14:03:56.28#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.14:03:56.28#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.14:03:56.28#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.14:03:56.28#ibcon#enter wrdev, iclass 6, count 2 2006.173.14:03:56.28#ibcon#first serial, iclass 6, count 2 2006.173.14:03:56.28#ibcon#enter sib2, iclass 6, count 2 2006.173.14:03:56.28#ibcon#flushed, iclass 6, count 2 2006.173.14:03:56.28#ibcon#about to write, iclass 6, count 2 2006.173.14:03:56.28#ibcon#wrote, iclass 6, count 2 2006.173.14:03:56.28#ibcon#about to read 3, iclass 6, count 2 2006.173.14:03:56.30#ibcon#read 3, iclass 6, count 2 2006.173.14:03:56.30#ibcon#about to read 4, iclass 6, count 2 2006.173.14:03:56.30#ibcon#read 4, iclass 6, count 2 2006.173.14:03:56.30#ibcon#about to read 5, iclass 6, count 2 2006.173.14:03:56.30#ibcon#read 5, iclass 6, count 2 2006.173.14:03:56.30#ibcon#about to read 6, iclass 6, count 2 2006.173.14:03:56.30#ibcon#read 6, iclass 6, count 2 2006.173.14:03:56.30#ibcon#end of sib2, iclass 6, count 2 2006.173.14:03:56.30#ibcon#*mode == 0, iclass 6, count 2 2006.173.14:03:56.30#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.14:03:56.30#ibcon#[25=AT01-07\r\n] 2006.173.14:03:56.30#ibcon#*before write, iclass 6, count 2 2006.173.14:03:56.30#ibcon#enter sib2, iclass 6, count 2 2006.173.14:03:56.30#ibcon#flushed, iclass 6, count 2 2006.173.14:03:56.30#ibcon#about to write, iclass 6, count 2 2006.173.14:03:56.30#ibcon#wrote, iclass 6, count 2 2006.173.14:03:56.30#ibcon#about to read 3, iclass 6, count 2 2006.173.14:03:56.30#abcon#<5=/04 0.7 1.4 21.741001003.7\r\n> 2006.173.14:03:56.32#abcon#{5=INTERFACE CLEAR} 2006.173.14:03:56.33#ibcon#read 3, iclass 6, count 2 2006.173.14:03:56.33#ibcon#about to read 4, iclass 6, count 2 2006.173.14:03:56.33#ibcon#read 4, iclass 6, count 2 2006.173.14:03:56.33#ibcon#about to read 5, iclass 6, count 2 2006.173.14:03:56.33#ibcon#read 5, iclass 6, count 2 2006.173.14:03:56.33#ibcon#about to read 6, iclass 6, count 2 2006.173.14:03:56.33#ibcon#read 6, iclass 6, count 2 2006.173.14:03:56.33#ibcon#end of sib2, iclass 6, count 2 2006.173.14:03:56.33#ibcon#*after write, iclass 6, count 2 2006.173.14:03:56.33#ibcon#*before return 0, iclass 6, count 2 2006.173.14:03:56.33#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.14:03:56.33#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.14:03:56.33#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.14:03:56.33#ibcon#ireg 7 cls_cnt 0 2006.173.14:03:56.33#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.14:03:56.38#abcon#[5=S1D000X0/0*\r\n] 2006.173.14:03:56.45#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.14:03:56.45#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.14:03:56.45#ibcon#enter wrdev, iclass 6, count 0 2006.173.14:03:56.45#ibcon#first serial, iclass 6, count 0 2006.173.14:03:56.45#ibcon#enter sib2, iclass 6, count 0 2006.173.14:03:56.45#ibcon#flushed, iclass 6, count 0 2006.173.14:03:56.45#ibcon#about to write, iclass 6, count 0 2006.173.14:03:56.45#ibcon#wrote, iclass 6, count 0 2006.173.14:03:56.45#ibcon#about to read 3, iclass 6, count 0 2006.173.14:03:56.47#ibcon#read 3, iclass 6, count 0 2006.173.14:03:56.47#ibcon#about to read 4, iclass 6, count 0 2006.173.14:03:56.47#ibcon#read 4, iclass 6, count 0 2006.173.14:03:56.47#ibcon#about to read 5, iclass 6, count 0 2006.173.14:03:56.47#ibcon#read 5, iclass 6, count 0 2006.173.14:03:56.47#ibcon#about to read 6, iclass 6, count 0 2006.173.14:03:56.47#ibcon#read 6, iclass 6, count 0 2006.173.14:03:56.47#ibcon#end of sib2, iclass 6, count 0 2006.173.14:03:56.47#ibcon#*mode == 0, iclass 6, count 0 2006.173.14:03:56.47#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.14:03:56.47#ibcon#[25=USB\r\n] 2006.173.14:03:56.47#ibcon#*before write, iclass 6, count 0 2006.173.14:03:56.47#ibcon#enter sib2, iclass 6, count 0 2006.173.14:03:56.47#ibcon#flushed, iclass 6, count 0 2006.173.14:03:56.47#ibcon#about to write, iclass 6, count 0 2006.173.14:03:56.47#ibcon#wrote, iclass 6, count 0 2006.173.14:03:56.47#ibcon#about to read 3, iclass 6, count 0 2006.173.14:03:56.50#ibcon#read 3, iclass 6, count 0 2006.173.14:03:56.50#ibcon#about to read 4, iclass 6, count 0 2006.173.14:03:56.50#ibcon#read 4, iclass 6, count 0 2006.173.14:03:56.50#ibcon#about to read 5, iclass 6, count 0 2006.173.14:03:56.50#ibcon#read 5, iclass 6, count 0 2006.173.14:03:56.50#ibcon#about to read 6, iclass 6, count 0 2006.173.14:03:56.50#ibcon#read 6, iclass 6, count 0 2006.173.14:03:56.50#ibcon#end of sib2, iclass 6, count 0 2006.173.14:03:56.50#ibcon#*after write, iclass 6, count 0 2006.173.14:03:56.50#ibcon#*before return 0, iclass 6, count 0 2006.173.14:03:56.50#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.14:03:56.50#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.14:03:56.50#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.14:03:56.50#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.14:03:56.50$vck44/valo=2,534.99 2006.173.14:03:56.50#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.14:03:56.50#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.14:03:56.50#ibcon#ireg 17 cls_cnt 0 2006.173.14:03:56.50#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.14:03:56.50#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.14:03:56.50#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.14:03:56.50#ibcon#enter wrdev, iclass 13, count 0 2006.173.14:03:56.50#ibcon#first serial, iclass 13, count 0 2006.173.14:03:56.50#ibcon#enter sib2, iclass 13, count 0 2006.173.14:03:56.50#ibcon#flushed, iclass 13, count 0 2006.173.14:03:56.50#ibcon#about to write, iclass 13, count 0 2006.173.14:03:56.50#ibcon#wrote, iclass 13, count 0 2006.173.14:03:56.50#ibcon#about to read 3, iclass 13, count 0 2006.173.14:03:56.52#ibcon#read 3, iclass 13, count 0 2006.173.14:03:56.52#ibcon#about to read 4, iclass 13, count 0 2006.173.14:03:56.52#ibcon#read 4, iclass 13, count 0 2006.173.14:03:56.52#ibcon#about to read 5, iclass 13, count 0 2006.173.14:03:56.52#ibcon#read 5, iclass 13, count 0 2006.173.14:03:56.52#ibcon#about to read 6, iclass 13, count 0 2006.173.14:03:56.52#ibcon#read 6, iclass 13, count 0 2006.173.14:03:56.52#ibcon#end of sib2, iclass 13, count 0 2006.173.14:03:56.52#ibcon#*mode == 0, iclass 13, count 0 2006.173.14:03:56.52#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.14:03:56.52#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.14:03:56.52#ibcon#*before write, iclass 13, count 0 2006.173.14:03:56.52#ibcon#enter sib2, iclass 13, count 0 2006.173.14:03:56.52#ibcon#flushed, iclass 13, count 0 2006.173.14:03:56.52#ibcon#about to write, iclass 13, count 0 2006.173.14:03:56.52#ibcon#wrote, iclass 13, count 0 2006.173.14:03:56.52#ibcon#about to read 3, iclass 13, count 0 2006.173.14:03:56.56#ibcon#read 3, iclass 13, count 0 2006.173.14:03:56.56#ibcon#about to read 4, iclass 13, count 0 2006.173.14:03:56.56#ibcon#read 4, iclass 13, count 0 2006.173.14:03:56.56#ibcon#about to read 5, iclass 13, count 0 2006.173.14:03:56.56#ibcon#read 5, iclass 13, count 0 2006.173.14:03:56.56#ibcon#about to read 6, iclass 13, count 0 2006.173.14:03:56.56#ibcon#read 6, iclass 13, count 0 2006.173.14:03:56.56#ibcon#end of sib2, iclass 13, count 0 2006.173.14:03:56.56#ibcon#*after write, iclass 13, count 0 2006.173.14:03:56.56#ibcon#*before return 0, iclass 13, count 0 2006.173.14:03:56.56#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.14:03:56.56#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.14:03:56.56#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.14:03:56.56#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.14:03:56.56$vck44/va=2,6 2006.173.14:03:56.56#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.14:03:56.56#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.14:03:56.56#ibcon#ireg 11 cls_cnt 2 2006.173.14:03:56.56#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.14:03:56.62#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.14:03:56.62#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.14:03:56.62#ibcon#enter wrdev, iclass 15, count 2 2006.173.14:03:56.62#ibcon#first serial, iclass 15, count 2 2006.173.14:03:56.62#ibcon#enter sib2, iclass 15, count 2 2006.173.14:03:56.62#ibcon#flushed, iclass 15, count 2 2006.173.14:03:56.62#ibcon#about to write, iclass 15, count 2 2006.173.14:03:56.62#ibcon#wrote, iclass 15, count 2 2006.173.14:03:56.62#ibcon#about to read 3, iclass 15, count 2 2006.173.14:03:56.64#ibcon#read 3, iclass 15, count 2 2006.173.14:03:56.64#ibcon#about to read 4, iclass 15, count 2 2006.173.14:03:56.64#ibcon#read 4, iclass 15, count 2 2006.173.14:03:56.64#ibcon#about to read 5, iclass 15, count 2 2006.173.14:03:56.64#ibcon#read 5, iclass 15, count 2 2006.173.14:03:56.64#ibcon#about to read 6, iclass 15, count 2 2006.173.14:03:56.64#ibcon#read 6, iclass 15, count 2 2006.173.14:03:56.64#ibcon#end of sib2, iclass 15, count 2 2006.173.14:03:56.64#ibcon#*mode == 0, iclass 15, count 2 2006.173.14:03:56.64#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.14:03:56.64#ibcon#[25=AT02-06\r\n] 2006.173.14:03:56.64#ibcon#*before write, iclass 15, count 2 2006.173.14:03:56.64#ibcon#enter sib2, iclass 15, count 2 2006.173.14:03:56.64#ibcon#flushed, iclass 15, count 2 2006.173.14:03:56.64#ibcon#about to write, iclass 15, count 2 2006.173.14:03:56.64#ibcon#wrote, iclass 15, count 2 2006.173.14:03:56.64#ibcon#about to read 3, iclass 15, count 2 2006.173.14:03:56.67#ibcon#read 3, iclass 15, count 2 2006.173.14:03:56.67#ibcon#about to read 4, iclass 15, count 2 2006.173.14:03:56.67#ibcon#read 4, iclass 15, count 2 2006.173.14:03:56.67#ibcon#about to read 5, iclass 15, count 2 2006.173.14:03:56.67#ibcon#read 5, iclass 15, count 2 2006.173.14:03:56.67#ibcon#about to read 6, iclass 15, count 2 2006.173.14:03:56.67#ibcon#read 6, iclass 15, count 2 2006.173.14:03:56.67#ibcon#end of sib2, iclass 15, count 2 2006.173.14:03:56.67#ibcon#*after write, iclass 15, count 2 2006.173.14:03:56.67#ibcon#*before return 0, iclass 15, count 2 2006.173.14:03:56.67#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.14:03:56.67#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.14:03:56.67#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.14:03:56.67#ibcon#ireg 7 cls_cnt 0 2006.173.14:03:56.67#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.14:03:56.79#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.14:03:56.79#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.14:03:56.79#ibcon#enter wrdev, iclass 15, count 0 2006.173.14:03:56.79#ibcon#first serial, iclass 15, count 0 2006.173.14:03:56.79#ibcon#enter sib2, iclass 15, count 0 2006.173.14:03:56.79#ibcon#flushed, iclass 15, count 0 2006.173.14:03:56.79#ibcon#about to write, iclass 15, count 0 2006.173.14:03:56.79#ibcon#wrote, iclass 15, count 0 2006.173.14:03:56.79#ibcon#about to read 3, iclass 15, count 0 2006.173.14:03:56.81#ibcon#read 3, iclass 15, count 0 2006.173.14:03:56.81#ibcon#about to read 4, iclass 15, count 0 2006.173.14:03:56.81#ibcon#read 4, iclass 15, count 0 2006.173.14:03:56.81#ibcon#about to read 5, iclass 15, count 0 2006.173.14:03:56.81#ibcon#read 5, iclass 15, count 0 2006.173.14:03:56.81#ibcon#about to read 6, iclass 15, count 0 2006.173.14:03:56.81#ibcon#read 6, iclass 15, count 0 2006.173.14:03:56.81#ibcon#end of sib2, iclass 15, count 0 2006.173.14:03:56.81#ibcon#*mode == 0, iclass 15, count 0 2006.173.14:03:56.81#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.14:03:56.81#ibcon#[25=USB\r\n] 2006.173.14:03:56.81#ibcon#*before write, iclass 15, count 0 2006.173.14:03:56.81#ibcon#enter sib2, iclass 15, count 0 2006.173.14:03:56.81#ibcon#flushed, iclass 15, count 0 2006.173.14:03:56.81#ibcon#about to write, iclass 15, count 0 2006.173.14:03:56.81#ibcon#wrote, iclass 15, count 0 2006.173.14:03:56.81#ibcon#about to read 3, iclass 15, count 0 2006.173.14:03:56.84#ibcon#read 3, iclass 15, count 0 2006.173.14:03:56.84#ibcon#about to read 4, iclass 15, count 0 2006.173.14:03:56.84#ibcon#read 4, iclass 15, count 0 2006.173.14:03:56.84#ibcon#about to read 5, iclass 15, count 0 2006.173.14:03:56.84#ibcon#read 5, iclass 15, count 0 2006.173.14:03:56.84#ibcon#about to read 6, iclass 15, count 0 2006.173.14:03:56.84#ibcon#read 6, iclass 15, count 0 2006.173.14:03:56.84#ibcon#end of sib2, iclass 15, count 0 2006.173.14:03:56.84#ibcon#*after write, iclass 15, count 0 2006.173.14:03:56.84#ibcon#*before return 0, iclass 15, count 0 2006.173.14:03:56.84#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.14:03:56.84#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.14:03:56.84#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.14:03:56.84#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.14:03:56.84$vck44/valo=3,564.99 2006.173.14:03:56.84#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.14:03:56.84#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.14:03:56.84#ibcon#ireg 17 cls_cnt 0 2006.173.14:03:56.84#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.14:03:56.84#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.14:03:56.84#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.14:03:56.84#ibcon#enter wrdev, iclass 17, count 0 2006.173.14:03:56.84#ibcon#first serial, iclass 17, count 0 2006.173.14:03:56.84#ibcon#enter sib2, iclass 17, count 0 2006.173.14:03:56.84#ibcon#flushed, iclass 17, count 0 2006.173.14:03:56.84#ibcon#about to write, iclass 17, count 0 2006.173.14:03:56.84#ibcon#wrote, iclass 17, count 0 2006.173.14:03:56.84#ibcon#about to read 3, iclass 17, count 0 2006.173.14:03:56.86#ibcon#read 3, iclass 17, count 0 2006.173.14:03:56.86#ibcon#about to read 4, iclass 17, count 0 2006.173.14:03:56.86#ibcon#read 4, iclass 17, count 0 2006.173.14:03:56.86#ibcon#about to read 5, iclass 17, count 0 2006.173.14:03:56.86#ibcon#read 5, iclass 17, count 0 2006.173.14:03:56.86#ibcon#about to read 6, iclass 17, count 0 2006.173.14:03:56.86#ibcon#read 6, iclass 17, count 0 2006.173.14:03:56.86#ibcon#end of sib2, iclass 17, count 0 2006.173.14:03:56.86#ibcon#*mode == 0, iclass 17, count 0 2006.173.14:03:56.86#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.14:03:56.86#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.14:03:56.86#ibcon#*before write, iclass 17, count 0 2006.173.14:03:56.86#ibcon#enter sib2, iclass 17, count 0 2006.173.14:03:56.86#ibcon#flushed, iclass 17, count 0 2006.173.14:03:56.86#ibcon#about to write, iclass 17, count 0 2006.173.14:03:56.86#ibcon#wrote, iclass 17, count 0 2006.173.14:03:56.86#ibcon#about to read 3, iclass 17, count 0 2006.173.14:03:56.90#ibcon#read 3, iclass 17, count 0 2006.173.14:03:56.90#ibcon#about to read 4, iclass 17, count 0 2006.173.14:03:56.90#ibcon#read 4, iclass 17, count 0 2006.173.14:03:56.90#ibcon#about to read 5, iclass 17, count 0 2006.173.14:03:56.90#ibcon#read 5, iclass 17, count 0 2006.173.14:03:56.90#ibcon#about to read 6, iclass 17, count 0 2006.173.14:03:56.90#ibcon#read 6, iclass 17, count 0 2006.173.14:03:56.90#ibcon#end of sib2, iclass 17, count 0 2006.173.14:03:56.90#ibcon#*after write, iclass 17, count 0 2006.173.14:03:56.90#ibcon#*before return 0, iclass 17, count 0 2006.173.14:03:56.90#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.14:03:56.90#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.14:03:56.90#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.14:03:56.90#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.14:03:56.90$vck44/va=3,5 2006.173.14:03:56.90#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.14:03:56.90#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.14:03:56.90#ibcon#ireg 11 cls_cnt 2 2006.173.14:03:56.90#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.14:03:56.96#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.14:03:56.96#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.14:03:56.96#ibcon#enter wrdev, iclass 19, count 2 2006.173.14:03:56.96#ibcon#first serial, iclass 19, count 2 2006.173.14:03:56.96#ibcon#enter sib2, iclass 19, count 2 2006.173.14:03:56.96#ibcon#flushed, iclass 19, count 2 2006.173.14:03:56.96#ibcon#about to write, iclass 19, count 2 2006.173.14:03:56.96#ibcon#wrote, iclass 19, count 2 2006.173.14:03:56.96#ibcon#about to read 3, iclass 19, count 2 2006.173.14:03:56.98#ibcon#read 3, iclass 19, count 2 2006.173.14:03:56.98#ibcon#about to read 4, iclass 19, count 2 2006.173.14:03:56.98#ibcon#read 4, iclass 19, count 2 2006.173.14:03:56.98#ibcon#about to read 5, iclass 19, count 2 2006.173.14:03:56.98#ibcon#read 5, iclass 19, count 2 2006.173.14:03:56.98#ibcon#about to read 6, iclass 19, count 2 2006.173.14:03:56.98#ibcon#read 6, iclass 19, count 2 2006.173.14:03:56.98#ibcon#end of sib2, iclass 19, count 2 2006.173.14:03:56.98#ibcon#*mode == 0, iclass 19, count 2 2006.173.14:03:56.98#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.14:03:56.98#ibcon#[25=AT03-05\r\n] 2006.173.14:03:56.98#ibcon#*before write, iclass 19, count 2 2006.173.14:03:56.98#ibcon#enter sib2, iclass 19, count 2 2006.173.14:03:56.98#ibcon#flushed, iclass 19, count 2 2006.173.14:03:56.98#ibcon#about to write, iclass 19, count 2 2006.173.14:03:56.98#ibcon#wrote, iclass 19, count 2 2006.173.14:03:56.98#ibcon#about to read 3, iclass 19, count 2 2006.173.14:03:57.01#ibcon#read 3, iclass 19, count 2 2006.173.14:03:57.01#ibcon#about to read 4, iclass 19, count 2 2006.173.14:03:57.01#ibcon#read 4, iclass 19, count 2 2006.173.14:03:57.01#ibcon#about to read 5, iclass 19, count 2 2006.173.14:03:57.01#ibcon#read 5, iclass 19, count 2 2006.173.14:03:57.01#ibcon#about to read 6, iclass 19, count 2 2006.173.14:03:57.01#ibcon#read 6, iclass 19, count 2 2006.173.14:03:57.01#ibcon#end of sib2, iclass 19, count 2 2006.173.14:03:57.01#ibcon#*after write, iclass 19, count 2 2006.173.14:03:57.01#ibcon#*before return 0, iclass 19, count 2 2006.173.14:03:57.01#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.14:03:57.01#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.14:03:57.01#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.14:03:57.01#ibcon#ireg 7 cls_cnt 0 2006.173.14:03:57.01#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.14:03:57.13#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.14:03:57.13#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.14:03:57.13#ibcon#enter wrdev, iclass 19, count 0 2006.173.14:03:57.13#ibcon#first serial, iclass 19, count 0 2006.173.14:03:57.13#ibcon#enter sib2, iclass 19, count 0 2006.173.14:03:57.13#ibcon#flushed, iclass 19, count 0 2006.173.14:03:57.13#ibcon#about to write, iclass 19, count 0 2006.173.14:03:57.13#ibcon#wrote, iclass 19, count 0 2006.173.14:03:57.13#ibcon#about to read 3, iclass 19, count 0 2006.173.14:03:57.15#ibcon#read 3, iclass 19, count 0 2006.173.14:03:57.15#ibcon#about to read 4, iclass 19, count 0 2006.173.14:03:57.15#ibcon#read 4, iclass 19, count 0 2006.173.14:03:57.15#ibcon#about to read 5, iclass 19, count 0 2006.173.14:03:57.15#ibcon#read 5, iclass 19, count 0 2006.173.14:03:57.15#ibcon#about to read 6, iclass 19, count 0 2006.173.14:03:57.15#ibcon#read 6, iclass 19, count 0 2006.173.14:03:57.15#ibcon#end of sib2, iclass 19, count 0 2006.173.14:03:57.15#ibcon#*mode == 0, iclass 19, count 0 2006.173.14:03:57.15#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.14:03:57.15#ibcon#[25=USB\r\n] 2006.173.14:03:57.15#ibcon#*before write, iclass 19, count 0 2006.173.14:03:57.15#ibcon#enter sib2, iclass 19, count 0 2006.173.14:03:57.15#ibcon#flushed, iclass 19, count 0 2006.173.14:03:57.15#ibcon#about to write, iclass 19, count 0 2006.173.14:03:57.15#ibcon#wrote, iclass 19, count 0 2006.173.14:03:57.15#ibcon#about to read 3, iclass 19, count 0 2006.173.14:03:57.18#ibcon#read 3, iclass 19, count 0 2006.173.14:03:57.18#ibcon#about to read 4, iclass 19, count 0 2006.173.14:03:57.18#ibcon#read 4, iclass 19, count 0 2006.173.14:03:57.18#ibcon#about to read 5, iclass 19, count 0 2006.173.14:03:57.18#ibcon#read 5, iclass 19, count 0 2006.173.14:03:57.18#ibcon#about to read 6, iclass 19, count 0 2006.173.14:03:57.18#ibcon#read 6, iclass 19, count 0 2006.173.14:03:57.18#ibcon#end of sib2, iclass 19, count 0 2006.173.14:03:57.18#ibcon#*after write, iclass 19, count 0 2006.173.14:03:57.18#ibcon#*before return 0, iclass 19, count 0 2006.173.14:03:57.18#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.14:03:57.18#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.14:03:57.18#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.14:03:57.18#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.14:03:57.18$vck44/valo=4,624.99 2006.173.14:03:57.18#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.14:03:57.18#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.14:03:57.18#ibcon#ireg 17 cls_cnt 0 2006.173.14:03:57.18#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.14:03:57.18#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.14:03:57.18#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.14:03:57.18#ibcon#enter wrdev, iclass 21, count 0 2006.173.14:03:57.18#ibcon#first serial, iclass 21, count 0 2006.173.14:03:57.18#ibcon#enter sib2, iclass 21, count 0 2006.173.14:03:57.18#ibcon#flushed, iclass 21, count 0 2006.173.14:03:57.18#ibcon#about to write, iclass 21, count 0 2006.173.14:03:57.18#ibcon#wrote, iclass 21, count 0 2006.173.14:03:57.18#ibcon#about to read 3, iclass 21, count 0 2006.173.14:03:57.20#ibcon#read 3, iclass 21, count 0 2006.173.14:03:57.20#ibcon#about to read 4, iclass 21, count 0 2006.173.14:03:57.20#ibcon#read 4, iclass 21, count 0 2006.173.14:03:57.20#ibcon#about to read 5, iclass 21, count 0 2006.173.14:03:57.20#ibcon#read 5, iclass 21, count 0 2006.173.14:03:57.20#ibcon#about to read 6, iclass 21, count 0 2006.173.14:03:57.20#ibcon#read 6, iclass 21, count 0 2006.173.14:03:57.20#ibcon#end of sib2, iclass 21, count 0 2006.173.14:03:57.20#ibcon#*mode == 0, iclass 21, count 0 2006.173.14:03:57.20#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.14:03:57.20#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.14:03:57.20#ibcon#*before write, iclass 21, count 0 2006.173.14:03:57.20#ibcon#enter sib2, iclass 21, count 0 2006.173.14:03:57.20#ibcon#flushed, iclass 21, count 0 2006.173.14:03:57.20#ibcon#about to write, iclass 21, count 0 2006.173.14:03:57.20#ibcon#wrote, iclass 21, count 0 2006.173.14:03:57.20#ibcon#about to read 3, iclass 21, count 0 2006.173.14:03:57.24#ibcon#read 3, iclass 21, count 0 2006.173.14:03:57.24#ibcon#about to read 4, iclass 21, count 0 2006.173.14:03:57.24#ibcon#read 4, iclass 21, count 0 2006.173.14:03:57.24#ibcon#about to read 5, iclass 21, count 0 2006.173.14:03:57.24#ibcon#read 5, iclass 21, count 0 2006.173.14:03:57.24#ibcon#about to read 6, iclass 21, count 0 2006.173.14:03:57.24#ibcon#read 6, iclass 21, count 0 2006.173.14:03:57.24#ibcon#end of sib2, iclass 21, count 0 2006.173.14:03:57.24#ibcon#*after write, iclass 21, count 0 2006.173.14:03:57.24#ibcon#*before return 0, iclass 21, count 0 2006.173.14:03:57.24#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.14:03:57.24#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.14:03:57.24#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.14:03:57.24#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.14:03:57.24$vck44/va=4,6 2006.173.14:03:57.24#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.14:03:57.24#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.14:03:57.24#ibcon#ireg 11 cls_cnt 2 2006.173.14:03:57.24#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.14:03:57.30#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.14:03:57.30#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.14:03:57.30#ibcon#enter wrdev, iclass 23, count 2 2006.173.14:03:57.30#ibcon#first serial, iclass 23, count 2 2006.173.14:03:57.30#ibcon#enter sib2, iclass 23, count 2 2006.173.14:03:57.30#ibcon#flushed, iclass 23, count 2 2006.173.14:03:57.30#ibcon#about to write, iclass 23, count 2 2006.173.14:03:57.30#ibcon#wrote, iclass 23, count 2 2006.173.14:03:57.30#ibcon#about to read 3, iclass 23, count 2 2006.173.14:03:57.32#ibcon#read 3, iclass 23, count 2 2006.173.14:03:57.32#ibcon#about to read 4, iclass 23, count 2 2006.173.14:03:57.32#ibcon#read 4, iclass 23, count 2 2006.173.14:03:57.32#ibcon#about to read 5, iclass 23, count 2 2006.173.14:03:57.32#ibcon#read 5, iclass 23, count 2 2006.173.14:03:57.32#ibcon#about to read 6, iclass 23, count 2 2006.173.14:03:57.32#ibcon#read 6, iclass 23, count 2 2006.173.14:03:57.32#ibcon#end of sib2, iclass 23, count 2 2006.173.14:03:57.32#ibcon#*mode == 0, iclass 23, count 2 2006.173.14:03:57.32#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.14:03:57.32#ibcon#[25=AT04-06\r\n] 2006.173.14:03:57.32#ibcon#*before write, iclass 23, count 2 2006.173.14:03:57.32#ibcon#enter sib2, iclass 23, count 2 2006.173.14:03:57.32#ibcon#flushed, iclass 23, count 2 2006.173.14:03:57.32#ibcon#about to write, iclass 23, count 2 2006.173.14:03:57.32#ibcon#wrote, iclass 23, count 2 2006.173.14:03:57.32#ibcon#about to read 3, iclass 23, count 2 2006.173.14:03:57.35#ibcon#read 3, iclass 23, count 2 2006.173.14:03:57.35#ibcon#about to read 4, iclass 23, count 2 2006.173.14:03:57.35#ibcon#read 4, iclass 23, count 2 2006.173.14:03:57.35#ibcon#about to read 5, iclass 23, count 2 2006.173.14:03:57.35#ibcon#read 5, iclass 23, count 2 2006.173.14:03:57.35#ibcon#about to read 6, iclass 23, count 2 2006.173.14:03:57.35#ibcon#read 6, iclass 23, count 2 2006.173.14:03:57.35#ibcon#end of sib2, iclass 23, count 2 2006.173.14:03:57.35#ibcon#*after write, iclass 23, count 2 2006.173.14:03:57.35#ibcon#*before return 0, iclass 23, count 2 2006.173.14:03:57.35#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.14:03:57.35#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.14:03:57.35#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.14:03:57.35#ibcon#ireg 7 cls_cnt 0 2006.173.14:03:57.35#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.14:03:57.47#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.14:03:57.47#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.14:03:57.47#ibcon#enter wrdev, iclass 23, count 0 2006.173.14:03:57.47#ibcon#first serial, iclass 23, count 0 2006.173.14:03:57.47#ibcon#enter sib2, iclass 23, count 0 2006.173.14:03:57.47#ibcon#flushed, iclass 23, count 0 2006.173.14:03:57.47#ibcon#about to write, iclass 23, count 0 2006.173.14:03:57.47#ibcon#wrote, iclass 23, count 0 2006.173.14:03:57.47#ibcon#about to read 3, iclass 23, count 0 2006.173.14:03:57.49#ibcon#read 3, iclass 23, count 0 2006.173.14:03:57.49#ibcon#about to read 4, iclass 23, count 0 2006.173.14:03:57.49#ibcon#read 4, iclass 23, count 0 2006.173.14:03:57.49#ibcon#about to read 5, iclass 23, count 0 2006.173.14:03:57.49#ibcon#read 5, iclass 23, count 0 2006.173.14:03:57.49#ibcon#about to read 6, iclass 23, count 0 2006.173.14:03:57.49#ibcon#read 6, iclass 23, count 0 2006.173.14:03:57.49#ibcon#end of sib2, iclass 23, count 0 2006.173.14:03:57.49#ibcon#*mode == 0, iclass 23, count 0 2006.173.14:03:57.49#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.14:03:57.49#ibcon#[25=USB\r\n] 2006.173.14:03:57.49#ibcon#*before write, iclass 23, count 0 2006.173.14:03:57.49#ibcon#enter sib2, iclass 23, count 0 2006.173.14:03:57.49#ibcon#flushed, iclass 23, count 0 2006.173.14:03:57.49#ibcon#about to write, iclass 23, count 0 2006.173.14:03:57.49#ibcon#wrote, iclass 23, count 0 2006.173.14:03:57.49#ibcon#about to read 3, iclass 23, count 0 2006.173.14:03:57.52#ibcon#read 3, iclass 23, count 0 2006.173.14:03:57.52#ibcon#about to read 4, iclass 23, count 0 2006.173.14:03:57.52#ibcon#read 4, iclass 23, count 0 2006.173.14:03:57.52#ibcon#about to read 5, iclass 23, count 0 2006.173.14:03:57.52#ibcon#read 5, iclass 23, count 0 2006.173.14:03:57.52#ibcon#about to read 6, iclass 23, count 0 2006.173.14:03:57.52#ibcon#read 6, iclass 23, count 0 2006.173.14:03:57.52#ibcon#end of sib2, iclass 23, count 0 2006.173.14:03:57.52#ibcon#*after write, iclass 23, count 0 2006.173.14:03:57.52#ibcon#*before return 0, iclass 23, count 0 2006.173.14:03:57.52#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.14:03:57.52#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.14:03:57.52#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.14:03:57.52#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.14:03:57.52$vck44/valo=5,734.99 2006.173.14:03:57.52#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.14:03:57.52#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.14:03:57.52#ibcon#ireg 17 cls_cnt 0 2006.173.14:03:57.52#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.14:03:57.52#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.14:03:57.52#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.14:03:57.52#ibcon#enter wrdev, iclass 25, count 0 2006.173.14:03:57.52#ibcon#first serial, iclass 25, count 0 2006.173.14:03:57.52#ibcon#enter sib2, iclass 25, count 0 2006.173.14:03:57.52#ibcon#flushed, iclass 25, count 0 2006.173.14:03:57.52#ibcon#about to write, iclass 25, count 0 2006.173.14:03:57.52#ibcon#wrote, iclass 25, count 0 2006.173.14:03:57.52#ibcon#about to read 3, iclass 25, count 0 2006.173.14:03:57.54#ibcon#read 3, iclass 25, count 0 2006.173.14:03:57.54#ibcon#about to read 4, iclass 25, count 0 2006.173.14:03:57.54#ibcon#read 4, iclass 25, count 0 2006.173.14:03:57.54#ibcon#about to read 5, iclass 25, count 0 2006.173.14:03:57.54#ibcon#read 5, iclass 25, count 0 2006.173.14:03:57.54#ibcon#about to read 6, iclass 25, count 0 2006.173.14:03:57.54#ibcon#read 6, iclass 25, count 0 2006.173.14:03:57.54#ibcon#end of sib2, iclass 25, count 0 2006.173.14:03:57.54#ibcon#*mode == 0, iclass 25, count 0 2006.173.14:03:57.54#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.14:03:57.54#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.14:03:57.54#ibcon#*before write, iclass 25, count 0 2006.173.14:03:57.54#ibcon#enter sib2, iclass 25, count 0 2006.173.14:03:57.54#ibcon#flushed, iclass 25, count 0 2006.173.14:03:57.54#ibcon#about to write, iclass 25, count 0 2006.173.14:03:57.54#ibcon#wrote, iclass 25, count 0 2006.173.14:03:57.54#ibcon#about to read 3, iclass 25, count 0 2006.173.14:03:57.58#ibcon#read 3, iclass 25, count 0 2006.173.14:03:57.58#ibcon#about to read 4, iclass 25, count 0 2006.173.14:03:57.58#ibcon#read 4, iclass 25, count 0 2006.173.14:03:57.58#ibcon#about to read 5, iclass 25, count 0 2006.173.14:03:57.58#ibcon#read 5, iclass 25, count 0 2006.173.14:03:57.58#ibcon#about to read 6, iclass 25, count 0 2006.173.14:03:57.58#ibcon#read 6, iclass 25, count 0 2006.173.14:03:57.58#ibcon#end of sib2, iclass 25, count 0 2006.173.14:03:57.58#ibcon#*after write, iclass 25, count 0 2006.173.14:03:57.58#ibcon#*before return 0, iclass 25, count 0 2006.173.14:03:57.58#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.14:03:57.58#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.14:03:57.58#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.14:03:57.58#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.14:03:57.58$vck44/va=5,4 2006.173.14:03:57.58#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.14:03:57.58#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.14:03:57.58#ibcon#ireg 11 cls_cnt 2 2006.173.14:03:57.58#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.14:03:57.64#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.14:03:57.64#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.14:03:57.64#ibcon#enter wrdev, iclass 27, count 2 2006.173.14:03:57.64#ibcon#first serial, iclass 27, count 2 2006.173.14:03:57.64#ibcon#enter sib2, iclass 27, count 2 2006.173.14:03:57.64#ibcon#flushed, iclass 27, count 2 2006.173.14:03:57.64#ibcon#about to write, iclass 27, count 2 2006.173.14:03:57.64#ibcon#wrote, iclass 27, count 2 2006.173.14:03:57.64#ibcon#about to read 3, iclass 27, count 2 2006.173.14:03:57.66#ibcon#read 3, iclass 27, count 2 2006.173.14:03:57.66#ibcon#about to read 4, iclass 27, count 2 2006.173.14:03:57.66#ibcon#read 4, iclass 27, count 2 2006.173.14:03:57.66#ibcon#about to read 5, iclass 27, count 2 2006.173.14:03:57.66#ibcon#read 5, iclass 27, count 2 2006.173.14:03:57.66#ibcon#about to read 6, iclass 27, count 2 2006.173.14:03:57.66#ibcon#read 6, iclass 27, count 2 2006.173.14:03:57.66#ibcon#end of sib2, iclass 27, count 2 2006.173.14:03:57.66#ibcon#*mode == 0, iclass 27, count 2 2006.173.14:03:57.66#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.14:03:57.66#ibcon#[25=AT05-04\r\n] 2006.173.14:03:57.66#ibcon#*before write, iclass 27, count 2 2006.173.14:03:57.66#ibcon#enter sib2, iclass 27, count 2 2006.173.14:03:57.66#ibcon#flushed, iclass 27, count 2 2006.173.14:03:57.66#ibcon#about to write, iclass 27, count 2 2006.173.14:03:57.66#ibcon#wrote, iclass 27, count 2 2006.173.14:03:57.66#ibcon#about to read 3, iclass 27, count 2 2006.173.14:03:57.69#ibcon#read 3, iclass 27, count 2 2006.173.14:03:57.69#ibcon#about to read 4, iclass 27, count 2 2006.173.14:03:57.69#ibcon#read 4, iclass 27, count 2 2006.173.14:03:57.69#ibcon#about to read 5, iclass 27, count 2 2006.173.14:03:57.69#ibcon#read 5, iclass 27, count 2 2006.173.14:03:57.69#ibcon#about to read 6, iclass 27, count 2 2006.173.14:03:57.69#ibcon#read 6, iclass 27, count 2 2006.173.14:03:57.69#ibcon#end of sib2, iclass 27, count 2 2006.173.14:03:57.69#ibcon#*after write, iclass 27, count 2 2006.173.14:03:57.69#ibcon#*before return 0, iclass 27, count 2 2006.173.14:03:57.69#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.14:03:57.69#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.14:03:57.69#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.14:03:57.69#ibcon#ireg 7 cls_cnt 0 2006.173.14:03:57.69#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.14:03:57.81#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.14:03:57.81#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.14:03:57.81#ibcon#enter wrdev, iclass 27, count 0 2006.173.14:03:57.81#ibcon#first serial, iclass 27, count 0 2006.173.14:03:57.81#ibcon#enter sib2, iclass 27, count 0 2006.173.14:03:57.81#ibcon#flushed, iclass 27, count 0 2006.173.14:03:57.81#ibcon#about to write, iclass 27, count 0 2006.173.14:03:57.81#ibcon#wrote, iclass 27, count 0 2006.173.14:03:57.81#ibcon#about to read 3, iclass 27, count 0 2006.173.14:03:57.83#ibcon#read 3, iclass 27, count 0 2006.173.14:03:57.83#ibcon#about to read 4, iclass 27, count 0 2006.173.14:03:57.83#ibcon#read 4, iclass 27, count 0 2006.173.14:03:57.83#ibcon#about to read 5, iclass 27, count 0 2006.173.14:03:57.83#ibcon#read 5, iclass 27, count 0 2006.173.14:03:57.83#ibcon#about to read 6, iclass 27, count 0 2006.173.14:03:57.83#ibcon#read 6, iclass 27, count 0 2006.173.14:03:57.83#ibcon#end of sib2, iclass 27, count 0 2006.173.14:03:57.83#ibcon#*mode == 0, iclass 27, count 0 2006.173.14:03:57.83#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.14:03:57.83#ibcon#[25=USB\r\n] 2006.173.14:03:57.83#ibcon#*before write, iclass 27, count 0 2006.173.14:03:57.83#ibcon#enter sib2, iclass 27, count 0 2006.173.14:03:57.83#ibcon#flushed, iclass 27, count 0 2006.173.14:03:57.83#ibcon#about to write, iclass 27, count 0 2006.173.14:03:57.83#ibcon#wrote, iclass 27, count 0 2006.173.14:03:57.83#ibcon#about to read 3, iclass 27, count 0 2006.173.14:03:57.86#ibcon#read 3, iclass 27, count 0 2006.173.14:03:57.86#ibcon#about to read 4, iclass 27, count 0 2006.173.14:03:57.86#ibcon#read 4, iclass 27, count 0 2006.173.14:03:57.86#ibcon#about to read 5, iclass 27, count 0 2006.173.14:03:57.86#ibcon#read 5, iclass 27, count 0 2006.173.14:03:57.86#ibcon#about to read 6, iclass 27, count 0 2006.173.14:03:57.86#ibcon#read 6, iclass 27, count 0 2006.173.14:03:57.86#ibcon#end of sib2, iclass 27, count 0 2006.173.14:03:57.86#ibcon#*after write, iclass 27, count 0 2006.173.14:03:57.86#ibcon#*before return 0, iclass 27, count 0 2006.173.14:03:57.86#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.14:03:57.86#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.14:03:57.86#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.14:03:57.86#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.14:03:57.86$vck44/valo=6,814.99 2006.173.14:03:57.86#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.14:03:57.86#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.14:03:57.86#ibcon#ireg 17 cls_cnt 0 2006.173.14:03:57.86#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.14:03:57.86#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.14:03:57.86#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.14:03:57.86#ibcon#enter wrdev, iclass 29, count 0 2006.173.14:03:57.86#ibcon#first serial, iclass 29, count 0 2006.173.14:03:57.86#ibcon#enter sib2, iclass 29, count 0 2006.173.14:03:57.86#ibcon#flushed, iclass 29, count 0 2006.173.14:03:57.86#ibcon#about to write, iclass 29, count 0 2006.173.14:03:57.86#ibcon#wrote, iclass 29, count 0 2006.173.14:03:57.86#ibcon#about to read 3, iclass 29, count 0 2006.173.14:03:57.88#ibcon#read 3, iclass 29, count 0 2006.173.14:03:57.88#ibcon#about to read 4, iclass 29, count 0 2006.173.14:03:57.88#ibcon#read 4, iclass 29, count 0 2006.173.14:03:57.88#ibcon#about to read 5, iclass 29, count 0 2006.173.14:03:57.88#ibcon#read 5, iclass 29, count 0 2006.173.14:03:57.88#ibcon#about to read 6, iclass 29, count 0 2006.173.14:03:57.88#ibcon#read 6, iclass 29, count 0 2006.173.14:03:57.88#ibcon#end of sib2, iclass 29, count 0 2006.173.14:03:57.88#ibcon#*mode == 0, iclass 29, count 0 2006.173.14:03:57.88#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.14:03:57.88#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.14:03:57.88#ibcon#*before write, iclass 29, count 0 2006.173.14:03:57.88#ibcon#enter sib2, iclass 29, count 0 2006.173.14:03:57.88#ibcon#flushed, iclass 29, count 0 2006.173.14:03:57.88#ibcon#about to write, iclass 29, count 0 2006.173.14:03:57.88#ibcon#wrote, iclass 29, count 0 2006.173.14:03:57.88#ibcon#about to read 3, iclass 29, count 0 2006.173.14:03:57.92#ibcon#read 3, iclass 29, count 0 2006.173.14:03:57.92#ibcon#about to read 4, iclass 29, count 0 2006.173.14:03:57.92#ibcon#read 4, iclass 29, count 0 2006.173.14:03:57.92#ibcon#about to read 5, iclass 29, count 0 2006.173.14:03:57.92#ibcon#read 5, iclass 29, count 0 2006.173.14:03:57.92#ibcon#about to read 6, iclass 29, count 0 2006.173.14:03:57.92#ibcon#read 6, iclass 29, count 0 2006.173.14:03:57.92#ibcon#end of sib2, iclass 29, count 0 2006.173.14:03:57.92#ibcon#*after write, iclass 29, count 0 2006.173.14:03:57.92#ibcon#*before return 0, iclass 29, count 0 2006.173.14:03:57.92#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.14:03:57.92#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.14:03:57.92#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.14:03:57.92#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.14:03:57.92$vck44/va=6,3 2006.173.14:03:57.92#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.14:03:57.92#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.14:03:57.92#ibcon#ireg 11 cls_cnt 2 2006.173.14:03:57.92#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.14:03:57.98#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.14:03:57.98#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.14:03:57.98#ibcon#enter wrdev, iclass 31, count 2 2006.173.14:03:57.98#ibcon#first serial, iclass 31, count 2 2006.173.14:03:57.98#ibcon#enter sib2, iclass 31, count 2 2006.173.14:03:57.98#ibcon#flushed, iclass 31, count 2 2006.173.14:03:57.98#ibcon#about to write, iclass 31, count 2 2006.173.14:03:57.98#ibcon#wrote, iclass 31, count 2 2006.173.14:03:57.98#ibcon#about to read 3, iclass 31, count 2 2006.173.14:03:58.00#ibcon#read 3, iclass 31, count 2 2006.173.14:03:58.00#ibcon#about to read 4, iclass 31, count 2 2006.173.14:03:58.00#ibcon#read 4, iclass 31, count 2 2006.173.14:03:58.00#ibcon#about to read 5, iclass 31, count 2 2006.173.14:03:58.00#ibcon#read 5, iclass 31, count 2 2006.173.14:03:58.00#ibcon#about to read 6, iclass 31, count 2 2006.173.14:03:58.00#ibcon#read 6, iclass 31, count 2 2006.173.14:03:58.00#ibcon#end of sib2, iclass 31, count 2 2006.173.14:03:58.00#ibcon#*mode == 0, iclass 31, count 2 2006.173.14:03:58.00#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.14:03:58.00#ibcon#[25=AT06-03\r\n] 2006.173.14:03:58.00#ibcon#*before write, iclass 31, count 2 2006.173.14:03:58.00#ibcon#enter sib2, iclass 31, count 2 2006.173.14:03:58.00#ibcon#flushed, iclass 31, count 2 2006.173.14:03:58.00#ibcon#about to write, iclass 31, count 2 2006.173.14:03:58.00#ibcon#wrote, iclass 31, count 2 2006.173.14:03:58.00#ibcon#about to read 3, iclass 31, count 2 2006.173.14:03:58.03#ibcon#read 3, iclass 31, count 2 2006.173.14:03:58.03#ibcon#about to read 4, iclass 31, count 2 2006.173.14:03:58.03#ibcon#read 4, iclass 31, count 2 2006.173.14:03:58.03#ibcon#about to read 5, iclass 31, count 2 2006.173.14:03:58.03#ibcon#read 5, iclass 31, count 2 2006.173.14:03:58.03#ibcon#about to read 6, iclass 31, count 2 2006.173.14:03:58.03#ibcon#read 6, iclass 31, count 2 2006.173.14:03:58.03#ibcon#end of sib2, iclass 31, count 2 2006.173.14:03:58.03#ibcon#*after write, iclass 31, count 2 2006.173.14:03:58.03#ibcon#*before return 0, iclass 31, count 2 2006.173.14:03:58.03#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.14:03:58.03#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.14:03:58.03#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.14:03:58.03#ibcon#ireg 7 cls_cnt 0 2006.173.14:03:58.03#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.14:03:58.15#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.14:03:58.15#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.14:03:58.15#ibcon#enter wrdev, iclass 31, count 0 2006.173.14:03:58.15#ibcon#first serial, iclass 31, count 0 2006.173.14:03:58.15#ibcon#enter sib2, iclass 31, count 0 2006.173.14:03:58.15#ibcon#flushed, iclass 31, count 0 2006.173.14:03:58.15#ibcon#about to write, iclass 31, count 0 2006.173.14:03:58.15#ibcon#wrote, iclass 31, count 0 2006.173.14:03:58.15#ibcon#about to read 3, iclass 31, count 0 2006.173.14:03:58.17#ibcon#read 3, iclass 31, count 0 2006.173.14:03:58.17#ibcon#about to read 4, iclass 31, count 0 2006.173.14:03:58.17#ibcon#read 4, iclass 31, count 0 2006.173.14:03:58.17#ibcon#about to read 5, iclass 31, count 0 2006.173.14:03:58.17#ibcon#read 5, iclass 31, count 0 2006.173.14:03:58.17#ibcon#about to read 6, iclass 31, count 0 2006.173.14:03:58.17#ibcon#read 6, iclass 31, count 0 2006.173.14:03:58.17#ibcon#end of sib2, iclass 31, count 0 2006.173.14:03:58.17#ibcon#*mode == 0, iclass 31, count 0 2006.173.14:03:58.17#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.14:03:58.17#ibcon#[25=USB\r\n] 2006.173.14:03:58.17#ibcon#*before write, iclass 31, count 0 2006.173.14:03:58.17#ibcon#enter sib2, iclass 31, count 0 2006.173.14:03:58.17#ibcon#flushed, iclass 31, count 0 2006.173.14:03:58.17#ibcon#about to write, iclass 31, count 0 2006.173.14:03:58.17#ibcon#wrote, iclass 31, count 0 2006.173.14:03:58.17#ibcon#about to read 3, iclass 31, count 0 2006.173.14:03:58.20#ibcon#read 3, iclass 31, count 0 2006.173.14:03:58.20#ibcon#about to read 4, iclass 31, count 0 2006.173.14:03:58.20#ibcon#read 4, iclass 31, count 0 2006.173.14:03:58.20#ibcon#about to read 5, iclass 31, count 0 2006.173.14:03:58.20#ibcon#read 5, iclass 31, count 0 2006.173.14:03:58.20#ibcon#about to read 6, iclass 31, count 0 2006.173.14:03:58.20#ibcon#read 6, iclass 31, count 0 2006.173.14:03:58.20#ibcon#end of sib2, iclass 31, count 0 2006.173.14:03:58.20#ibcon#*after write, iclass 31, count 0 2006.173.14:03:58.20#ibcon#*before return 0, iclass 31, count 0 2006.173.14:03:58.20#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.14:03:58.20#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.14:03:58.20#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.14:03:58.20#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.14:03:58.20$vck44/valo=7,864.99 2006.173.14:03:58.20#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.14:03:58.20#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.14:03:58.20#ibcon#ireg 17 cls_cnt 0 2006.173.14:03:58.20#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.14:03:58.20#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.14:03:58.20#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.14:03:58.20#ibcon#enter wrdev, iclass 33, count 0 2006.173.14:03:58.20#ibcon#first serial, iclass 33, count 0 2006.173.14:03:58.20#ibcon#enter sib2, iclass 33, count 0 2006.173.14:03:58.20#ibcon#flushed, iclass 33, count 0 2006.173.14:03:58.20#ibcon#about to write, iclass 33, count 0 2006.173.14:03:58.20#ibcon#wrote, iclass 33, count 0 2006.173.14:03:58.20#ibcon#about to read 3, iclass 33, count 0 2006.173.14:03:58.22#ibcon#read 3, iclass 33, count 0 2006.173.14:03:58.22#ibcon#about to read 4, iclass 33, count 0 2006.173.14:03:58.22#ibcon#read 4, iclass 33, count 0 2006.173.14:03:58.22#ibcon#about to read 5, iclass 33, count 0 2006.173.14:03:58.22#ibcon#read 5, iclass 33, count 0 2006.173.14:03:58.22#ibcon#about to read 6, iclass 33, count 0 2006.173.14:03:58.22#ibcon#read 6, iclass 33, count 0 2006.173.14:03:58.22#ibcon#end of sib2, iclass 33, count 0 2006.173.14:03:58.22#ibcon#*mode == 0, iclass 33, count 0 2006.173.14:03:58.22#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.14:03:58.22#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.14:03:58.22#ibcon#*before write, iclass 33, count 0 2006.173.14:03:58.22#ibcon#enter sib2, iclass 33, count 0 2006.173.14:03:58.22#ibcon#flushed, iclass 33, count 0 2006.173.14:03:58.22#ibcon#about to write, iclass 33, count 0 2006.173.14:03:58.22#ibcon#wrote, iclass 33, count 0 2006.173.14:03:58.22#ibcon#about to read 3, iclass 33, count 0 2006.173.14:03:58.26#ibcon#read 3, iclass 33, count 0 2006.173.14:03:58.26#ibcon#about to read 4, iclass 33, count 0 2006.173.14:03:58.26#ibcon#read 4, iclass 33, count 0 2006.173.14:03:58.26#ibcon#about to read 5, iclass 33, count 0 2006.173.14:03:58.26#ibcon#read 5, iclass 33, count 0 2006.173.14:03:58.26#ibcon#about to read 6, iclass 33, count 0 2006.173.14:03:58.26#ibcon#read 6, iclass 33, count 0 2006.173.14:03:58.26#ibcon#end of sib2, iclass 33, count 0 2006.173.14:03:58.26#ibcon#*after write, iclass 33, count 0 2006.173.14:03:58.26#ibcon#*before return 0, iclass 33, count 0 2006.173.14:03:58.26#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.14:03:58.26#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.14:03:58.26#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.14:03:58.26#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.14:03:58.26$vck44/va=7,4 2006.173.14:03:58.26#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.14:03:58.26#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.14:03:58.26#ibcon#ireg 11 cls_cnt 2 2006.173.14:03:58.26#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.14:03:58.32#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.14:03:58.32#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.14:03:58.32#ibcon#enter wrdev, iclass 35, count 2 2006.173.14:03:58.32#ibcon#first serial, iclass 35, count 2 2006.173.14:03:58.32#ibcon#enter sib2, iclass 35, count 2 2006.173.14:03:58.32#ibcon#flushed, iclass 35, count 2 2006.173.14:03:58.32#ibcon#about to write, iclass 35, count 2 2006.173.14:03:58.32#ibcon#wrote, iclass 35, count 2 2006.173.14:03:58.32#ibcon#about to read 3, iclass 35, count 2 2006.173.14:03:58.34#ibcon#read 3, iclass 35, count 2 2006.173.14:03:58.34#ibcon#about to read 4, iclass 35, count 2 2006.173.14:03:58.34#ibcon#read 4, iclass 35, count 2 2006.173.14:03:58.34#ibcon#about to read 5, iclass 35, count 2 2006.173.14:03:58.34#ibcon#read 5, iclass 35, count 2 2006.173.14:03:58.34#ibcon#about to read 6, iclass 35, count 2 2006.173.14:03:58.34#ibcon#read 6, iclass 35, count 2 2006.173.14:03:58.34#ibcon#end of sib2, iclass 35, count 2 2006.173.14:03:58.34#ibcon#*mode == 0, iclass 35, count 2 2006.173.14:03:58.34#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.14:03:58.34#ibcon#[25=AT07-04\r\n] 2006.173.14:03:58.34#ibcon#*before write, iclass 35, count 2 2006.173.14:03:58.34#ibcon#enter sib2, iclass 35, count 2 2006.173.14:03:58.34#ibcon#flushed, iclass 35, count 2 2006.173.14:03:58.34#ibcon#about to write, iclass 35, count 2 2006.173.14:03:58.34#ibcon#wrote, iclass 35, count 2 2006.173.14:03:58.34#ibcon#about to read 3, iclass 35, count 2 2006.173.14:03:58.37#ibcon#read 3, iclass 35, count 2 2006.173.14:03:58.37#ibcon#about to read 4, iclass 35, count 2 2006.173.14:03:58.37#ibcon#read 4, iclass 35, count 2 2006.173.14:03:58.37#ibcon#about to read 5, iclass 35, count 2 2006.173.14:03:58.37#ibcon#read 5, iclass 35, count 2 2006.173.14:03:58.37#ibcon#about to read 6, iclass 35, count 2 2006.173.14:03:58.37#ibcon#read 6, iclass 35, count 2 2006.173.14:03:58.37#ibcon#end of sib2, iclass 35, count 2 2006.173.14:03:58.37#ibcon#*after write, iclass 35, count 2 2006.173.14:03:58.37#ibcon#*before return 0, iclass 35, count 2 2006.173.14:03:58.37#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.14:03:58.37#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.14:03:58.37#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.14:03:58.37#ibcon#ireg 7 cls_cnt 0 2006.173.14:03:58.37#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.14:03:58.49#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.14:03:58.49#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.14:03:58.49#ibcon#enter wrdev, iclass 35, count 0 2006.173.14:03:58.49#ibcon#first serial, iclass 35, count 0 2006.173.14:03:58.49#ibcon#enter sib2, iclass 35, count 0 2006.173.14:03:58.49#ibcon#flushed, iclass 35, count 0 2006.173.14:03:58.49#ibcon#about to write, iclass 35, count 0 2006.173.14:03:58.49#ibcon#wrote, iclass 35, count 0 2006.173.14:03:58.49#ibcon#about to read 3, iclass 35, count 0 2006.173.14:03:58.51#ibcon#read 3, iclass 35, count 0 2006.173.14:03:58.51#ibcon#about to read 4, iclass 35, count 0 2006.173.14:03:58.51#ibcon#read 4, iclass 35, count 0 2006.173.14:03:58.51#ibcon#about to read 5, iclass 35, count 0 2006.173.14:03:58.51#ibcon#read 5, iclass 35, count 0 2006.173.14:03:58.51#ibcon#about to read 6, iclass 35, count 0 2006.173.14:03:58.51#ibcon#read 6, iclass 35, count 0 2006.173.14:03:58.51#ibcon#end of sib2, iclass 35, count 0 2006.173.14:03:58.51#ibcon#*mode == 0, iclass 35, count 0 2006.173.14:03:58.51#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.14:03:58.51#ibcon#[25=USB\r\n] 2006.173.14:03:58.51#ibcon#*before write, iclass 35, count 0 2006.173.14:03:58.51#ibcon#enter sib2, iclass 35, count 0 2006.173.14:03:58.51#ibcon#flushed, iclass 35, count 0 2006.173.14:03:58.51#ibcon#about to write, iclass 35, count 0 2006.173.14:03:58.51#ibcon#wrote, iclass 35, count 0 2006.173.14:03:58.51#ibcon#about to read 3, iclass 35, count 0 2006.173.14:03:58.54#ibcon#read 3, iclass 35, count 0 2006.173.14:03:58.54#ibcon#about to read 4, iclass 35, count 0 2006.173.14:03:58.54#ibcon#read 4, iclass 35, count 0 2006.173.14:03:58.54#ibcon#about to read 5, iclass 35, count 0 2006.173.14:03:58.54#ibcon#read 5, iclass 35, count 0 2006.173.14:03:58.54#ibcon#about to read 6, iclass 35, count 0 2006.173.14:03:58.54#ibcon#read 6, iclass 35, count 0 2006.173.14:03:58.54#ibcon#end of sib2, iclass 35, count 0 2006.173.14:03:58.54#ibcon#*after write, iclass 35, count 0 2006.173.14:03:58.54#ibcon#*before return 0, iclass 35, count 0 2006.173.14:03:58.54#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.14:03:58.54#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.14:03:58.54#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.14:03:58.54#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.14:03:58.54$vck44/valo=8,884.99 2006.173.14:03:58.54#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.14:03:58.54#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.14:03:58.54#ibcon#ireg 17 cls_cnt 0 2006.173.14:03:58.54#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.14:03:58.54#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.14:03:58.54#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.14:03:58.54#ibcon#enter wrdev, iclass 37, count 0 2006.173.14:03:58.54#ibcon#first serial, iclass 37, count 0 2006.173.14:03:58.54#ibcon#enter sib2, iclass 37, count 0 2006.173.14:03:58.54#ibcon#flushed, iclass 37, count 0 2006.173.14:03:58.54#ibcon#about to write, iclass 37, count 0 2006.173.14:03:58.54#ibcon#wrote, iclass 37, count 0 2006.173.14:03:58.54#ibcon#about to read 3, iclass 37, count 0 2006.173.14:03:58.56#ibcon#read 3, iclass 37, count 0 2006.173.14:03:58.56#ibcon#about to read 4, iclass 37, count 0 2006.173.14:03:58.56#ibcon#read 4, iclass 37, count 0 2006.173.14:03:58.56#ibcon#about to read 5, iclass 37, count 0 2006.173.14:03:58.56#ibcon#read 5, iclass 37, count 0 2006.173.14:03:58.56#ibcon#about to read 6, iclass 37, count 0 2006.173.14:03:58.56#ibcon#read 6, iclass 37, count 0 2006.173.14:03:58.56#ibcon#end of sib2, iclass 37, count 0 2006.173.14:03:58.56#ibcon#*mode == 0, iclass 37, count 0 2006.173.14:03:58.56#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.14:03:58.56#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.14:03:58.56#ibcon#*before write, iclass 37, count 0 2006.173.14:03:58.56#ibcon#enter sib2, iclass 37, count 0 2006.173.14:03:58.56#ibcon#flushed, iclass 37, count 0 2006.173.14:03:58.56#ibcon#about to write, iclass 37, count 0 2006.173.14:03:58.56#ibcon#wrote, iclass 37, count 0 2006.173.14:03:58.56#ibcon#about to read 3, iclass 37, count 0 2006.173.14:03:58.60#ibcon#read 3, iclass 37, count 0 2006.173.14:03:58.60#ibcon#about to read 4, iclass 37, count 0 2006.173.14:03:58.60#ibcon#read 4, iclass 37, count 0 2006.173.14:03:58.60#ibcon#about to read 5, iclass 37, count 0 2006.173.14:03:58.60#ibcon#read 5, iclass 37, count 0 2006.173.14:03:58.60#ibcon#about to read 6, iclass 37, count 0 2006.173.14:03:58.60#ibcon#read 6, iclass 37, count 0 2006.173.14:03:58.60#ibcon#end of sib2, iclass 37, count 0 2006.173.14:03:58.60#ibcon#*after write, iclass 37, count 0 2006.173.14:03:58.60#ibcon#*before return 0, iclass 37, count 0 2006.173.14:03:58.60#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.14:03:58.60#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.14:03:58.60#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.14:03:58.60#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.14:03:58.60$vck44/va=8,4 2006.173.14:03:58.60#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.14:03:58.60#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.14:03:58.60#ibcon#ireg 11 cls_cnt 2 2006.173.14:03:58.60#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.14:03:58.66#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.14:03:58.66#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.14:03:58.66#ibcon#enter wrdev, iclass 39, count 2 2006.173.14:03:58.66#ibcon#first serial, iclass 39, count 2 2006.173.14:03:58.66#ibcon#enter sib2, iclass 39, count 2 2006.173.14:03:58.66#ibcon#flushed, iclass 39, count 2 2006.173.14:03:58.66#ibcon#about to write, iclass 39, count 2 2006.173.14:03:58.66#ibcon#wrote, iclass 39, count 2 2006.173.14:03:58.66#ibcon#about to read 3, iclass 39, count 2 2006.173.14:03:58.68#ibcon#read 3, iclass 39, count 2 2006.173.14:03:58.68#ibcon#about to read 4, iclass 39, count 2 2006.173.14:03:58.68#ibcon#read 4, iclass 39, count 2 2006.173.14:03:58.68#ibcon#about to read 5, iclass 39, count 2 2006.173.14:03:58.68#ibcon#read 5, iclass 39, count 2 2006.173.14:03:58.68#ibcon#about to read 6, iclass 39, count 2 2006.173.14:03:58.68#ibcon#read 6, iclass 39, count 2 2006.173.14:03:58.68#ibcon#end of sib2, iclass 39, count 2 2006.173.14:03:58.68#ibcon#*mode == 0, iclass 39, count 2 2006.173.14:03:58.68#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.14:03:58.68#ibcon#[25=AT08-04\r\n] 2006.173.14:03:58.68#ibcon#*before write, iclass 39, count 2 2006.173.14:03:58.68#ibcon#enter sib2, iclass 39, count 2 2006.173.14:03:58.68#ibcon#flushed, iclass 39, count 2 2006.173.14:03:58.68#ibcon#about to write, iclass 39, count 2 2006.173.14:03:58.68#ibcon#wrote, iclass 39, count 2 2006.173.14:03:58.68#ibcon#about to read 3, iclass 39, count 2 2006.173.14:03:58.71#ibcon#read 3, iclass 39, count 2 2006.173.14:03:58.71#ibcon#about to read 4, iclass 39, count 2 2006.173.14:03:58.71#ibcon#read 4, iclass 39, count 2 2006.173.14:03:58.71#ibcon#about to read 5, iclass 39, count 2 2006.173.14:03:58.71#ibcon#read 5, iclass 39, count 2 2006.173.14:03:58.71#ibcon#about to read 6, iclass 39, count 2 2006.173.14:03:58.71#ibcon#read 6, iclass 39, count 2 2006.173.14:03:58.71#ibcon#end of sib2, iclass 39, count 2 2006.173.14:03:58.71#ibcon#*after write, iclass 39, count 2 2006.173.14:03:58.71#ibcon#*before return 0, iclass 39, count 2 2006.173.14:03:58.71#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.14:03:58.71#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.14:03:58.71#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.14:03:58.71#ibcon#ireg 7 cls_cnt 0 2006.173.14:03:58.71#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.14:03:58.83#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.14:03:58.83#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.14:03:58.83#ibcon#enter wrdev, iclass 39, count 0 2006.173.14:03:58.83#ibcon#first serial, iclass 39, count 0 2006.173.14:03:58.83#ibcon#enter sib2, iclass 39, count 0 2006.173.14:03:58.83#ibcon#flushed, iclass 39, count 0 2006.173.14:03:58.83#ibcon#about to write, iclass 39, count 0 2006.173.14:03:58.83#ibcon#wrote, iclass 39, count 0 2006.173.14:03:58.83#ibcon#about to read 3, iclass 39, count 0 2006.173.14:03:58.85#ibcon#read 3, iclass 39, count 0 2006.173.14:03:58.85#ibcon#about to read 4, iclass 39, count 0 2006.173.14:03:58.85#ibcon#read 4, iclass 39, count 0 2006.173.14:03:58.85#ibcon#about to read 5, iclass 39, count 0 2006.173.14:03:58.85#ibcon#read 5, iclass 39, count 0 2006.173.14:03:58.85#ibcon#about to read 6, iclass 39, count 0 2006.173.14:03:58.85#ibcon#read 6, iclass 39, count 0 2006.173.14:03:58.85#ibcon#end of sib2, iclass 39, count 0 2006.173.14:03:58.85#ibcon#*mode == 0, iclass 39, count 0 2006.173.14:03:58.85#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.14:03:58.85#ibcon#[25=USB\r\n] 2006.173.14:03:58.85#ibcon#*before write, iclass 39, count 0 2006.173.14:03:58.85#ibcon#enter sib2, iclass 39, count 0 2006.173.14:03:58.85#ibcon#flushed, iclass 39, count 0 2006.173.14:03:58.85#ibcon#about to write, iclass 39, count 0 2006.173.14:03:58.85#ibcon#wrote, iclass 39, count 0 2006.173.14:03:58.85#ibcon#about to read 3, iclass 39, count 0 2006.173.14:03:58.88#ibcon#read 3, iclass 39, count 0 2006.173.14:03:58.88#ibcon#about to read 4, iclass 39, count 0 2006.173.14:03:58.88#ibcon#read 4, iclass 39, count 0 2006.173.14:03:58.88#ibcon#about to read 5, iclass 39, count 0 2006.173.14:03:58.88#ibcon#read 5, iclass 39, count 0 2006.173.14:03:58.88#ibcon#about to read 6, iclass 39, count 0 2006.173.14:03:58.88#ibcon#read 6, iclass 39, count 0 2006.173.14:03:58.88#ibcon#end of sib2, iclass 39, count 0 2006.173.14:03:58.88#ibcon#*after write, iclass 39, count 0 2006.173.14:03:58.88#ibcon#*before return 0, iclass 39, count 0 2006.173.14:03:58.88#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.14:03:58.88#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.14:03:58.88#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.14:03:58.88#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.14:03:58.88$vck44/vblo=1,629.99 2006.173.14:03:58.88#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.14:03:58.88#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.14:03:58.88#ibcon#ireg 17 cls_cnt 0 2006.173.14:03:58.88#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.14:03:58.88#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.14:03:58.88#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.14:03:58.88#ibcon#enter wrdev, iclass 3, count 0 2006.173.14:03:58.88#ibcon#first serial, iclass 3, count 0 2006.173.14:03:58.88#ibcon#enter sib2, iclass 3, count 0 2006.173.14:03:58.88#ibcon#flushed, iclass 3, count 0 2006.173.14:03:58.88#ibcon#about to write, iclass 3, count 0 2006.173.14:03:58.88#ibcon#wrote, iclass 3, count 0 2006.173.14:03:58.88#ibcon#about to read 3, iclass 3, count 0 2006.173.14:03:58.90#ibcon#read 3, iclass 3, count 0 2006.173.14:03:58.90#ibcon#about to read 4, iclass 3, count 0 2006.173.14:03:58.90#ibcon#read 4, iclass 3, count 0 2006.173.14:03:58.90#ibcon#about to read 5, iclass 3, count 0 2006.173.14:03:58.90#ibcon#read 5, iclass 3, count 0 2006.173.14:03:58.90#ibcon#about to read 6, iclass 3, count 0 2006.173.14:03:58.90#ibcon#read 6, iclass 3, count 0 2006.173.14:03:58.90#ibcon#end of sib2, iclass 3, count 0 2006.173.14:03:58.90#ibcon#*mode == 0, iclass 3, count 0 2006.173.14:03:58.90#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.14:03:58.90#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.14:03:58.90#ibcon#*before write, iclass 3, count 0 2006.173.14:03:58.90#ibcon#enter sib2, iclass 3, count 0 2006.173.14:03:58.90#ibcon#flushed, iclass 3, count 0 2006.173.14:03:58.90#ibcon#about to write, iclass 3, count 0 2006.173.14:03:58.90#ibcon#wrote, iclass 3, count 0 2006.173.14:03:58.90#ibcon#about to read 3, iclass 3, count 0 2006.173.14:03:58.94#ibcon#read 3, iclass 3, count 0 2006.173.14:03:58.94#ibcon#about to read 4, iclass 3, count 0 2006.173.14:03:58.94#ibcon#read 4, iclass 3, count 0 2006.173.14:03:58.94#ibcon#about to read 5, iclass 3, count 0 2006.173.14:03:58.94#ibcon#read 5, iclass 3, count 0 2006.173.14:03:58.94#ibcon#about to read 6, iclass 3, count 0 2006.173.14:03:58.94#ibcon#read 6, iclass 3, count 0 2006.173.14:03:58.94#ibcon#end of sib2, iclass 3, count 0 2006.173.14:03:58.94#ibcon#*after write, iclass 3, count 0 2006.173.14:03:58.94#ibcon#*before return 0, iclass 3, count 0 2006.173.14:03:58.94#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.14:03:58.94#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.14:03:58.94#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.14:03:58.94#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.14:03:58.94$vck44/vb=1,4 2006.173.14:03:58.94#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.14:03:58.94#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.14:03:58.94#ibcon#ireg 11 cls_cnt 2 2006.173.14:03:58.94#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.14:03:58.94#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.14:03:58.94#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.14:03:58.94#ibcon#enter wrdev, iclass 5, count 2 2006.173.14:03:58.94#ibcon#first serial, iclass 5, count 2 2006.173.14:03:58.94#ibcon#enter sib2, iclass 5, count 2 2006.173.14:03:58.94#ibcon#flushed, iclass 5, count 2 2006.173.14:03:58.94#ibcon#about to write, iclass 5, count 2 2006.173.14:03:58.94#ibcon#wrote, iclass 5, count 2 2006.173.14:03:58.94#ibcon#about to read 3, iclass 5, count 2 2006.173.14:03:58.96#ibcon#read 3, iclass 5, count 2 2006.173.14:03:58.96#ibcon#about to read 4, iclass 5, count 2 2006.173.14:03:58.96#ibcon#read 4, iclass 5, count 2 2006.173.14:03:58.96#ibcon#about to read 5, iclass 5, count 2 2006.173.14:03:58.96#ibcon#read 5, iclass 5, count 2 2006.173.14:03:58.96#ibcon#about to read 6, iclass 5, count 2 2006.173.14:03:58.96#ibcon#read 6, iclass 5, count 2 2006.173.14:03:58.96#ibcon#end of sib2, iclass 5, count 2 2006.173.14:03:58.96#ibcon#*mode == 0, iclass 5, count 2 2006.173.14:03:58.96#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.14:03:58.96#ibcon#[27=AT01-04\r\n] 2006.173.14:03:58.96#ibcon#*before write, iclass 5, count 2 2006.173.14:03:58.96#ibcon#enter sib2, iclass 5, count 2 2006.173.14:03:58.96#ibcon#flushed, iclass 5, count 2 2006.173.14:03:58.96#ibcon#about to write, iclass 5, count 2 2006.173.14:03:58.96#ibcon#wrote, iclass 5, count 2 2006.173.14:03:58.96#ibcon#about to read 3, iclass 5, count 2 2006.173.14:03:58.99#ibcon#read 3, iclass 5, count 2 2006.173.14:03:58.99#ibcon#about to read 4, iclass 5, count 2 2006.173.14:03:58.99#ibcon#read 4, iclass 5, count 2 2006.173.14:03:58.99#ibcon#about to read 5, iclass 5, count 2 2006.173.14:03:58.99#ibcon#read 5, iclass 5, count 2 2006.173.14:03:58.99#ibcon#about to read 6, iclass 5, count 2 2006.173.14:03:58.99#ibcon#read 6, iclass 5, count 2 2006.173.14:03:58.99#ibcon#end of sib2, iclass 5, count 2 2006.173.14:03:58.99#ibcon#*after write, iclass 5, count 2 2006.173.14:03:58.99#ibcon#*before return 0, iclass 5, count 2 2006.173.14:03:58.99#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.14:03:58.99#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.14:03:58.99#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.14:03:58.99#ibcon#ireg 7 cls_cnt 0 2006.173.14:03:58.99#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.14:03:59.11#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.14:03:59.11#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.14:03:59.11#ibcon#enter wrdev, iclass 5, count 0 2006.173.14:03:59.11#ibcon#first serial, iclass 5, count 0 2006.173.14:03:59.11#ibcon#enter sib2, iclass 5, count 0 2006.173.14:03:59.11#ibcon#flushed, iclass 5, count 0 2006.173.14:03:59.11#ibcon#about to write, iclass 5, count 0 2006.173.14:03:59.11#ibcon#wrote, iclass 5, count 0 2006.173.14:03:59.11#ibcon#about to read 3, iclass 5, count 0 2006.173.14:03:59.13#ibcon#read 3, iclass 5, count 0 2006.173.14:03:59.13#ibcon#about to read 4, iclass 5, count 0 2006.173.14:03:59.13#ibcon#read 4, iclass 5, count 0 2006.173.14:03:59.13#ibcon#about to read 5, iclass 5, count 0 2006.173.14:03:59.13#ibcon#read 5, iclass 5, count 0 2006.173.14:03:59.13#ibcon#about to read 6, iclass 5, count 0 2006.173.14:03:59.13#ibcon#read 6, iclass 5, count 0 2006.173.14:03:59.13#ibcon#end of sib2, iclass 5, count 0 2006.173.14:03:59.13#ibcon#*mode == 0, iclass 5, count 0 2006.173.14:03:59.13#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.14:03:59.13#ibcon#[27=USB\r\n] 2006.173.14:03:59.13#ibcon#*before write, iclass 5, count 0 2006.173.14:03:59.13#ibcon#enter sib2, iclass 5, count 0 2006.173.14:03:59.13#ibcon#flushed, iclass 5, count 0 2006.173.14:03:59.13#ibcon#about to write, iclass 5, count 0 2006.173.14:03:59.13#ibcon#wrote, iclass 5, count 0 2006.173.14:03:59.13#ibcon#about to read 3, iclass 5, count 0 2006.173.14:03:59.16#ibcon#read 3, iclass 5, count 0 2006.173.14:03:59.16#ibcon#about to read 4, iclass 5, count 0 2006.173.14:03:59.16#ibcon#read 4, iclass 5, count 0 2006.173.14:03:59.16#ibcon#about to read 5, iclass 5, count 0 2006.173.14:03:59.16#ibcon#read 5, iclass 5, count 0 2006.173.14:03:59.16#ibcon#about to read 6, iclass 5, count 0 2006.173.14:03:59.16#ibcon#read 6, iclass 5, count 0 2006.173.14:03:59.16#ibcon#end of sib2, iclass 5, count 0 2006.173.14:03:59.16#ibcon#*after write, iclass 5, count 0 2006.173.14:03:59.16#ibcon#*before return 0, iclass 5, count 0 2006.173.14:03:59.16#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.14:03:59.16#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.14:03:59.16#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.14:03:59.16#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.14:03:59.16$vck44/vblo=2,634.99 2006.173.14:03:59.16#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.14:03:59.16#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.14:03:59.16#ibcon#ireg 17 cls_cnt 0 2006.173.14:03:59.16#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.14:03:59.16#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.14:03:59.16#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.14:03:59.16#ibcon#enter wrdev, iclass 7, count 0 2006.173.14:03:59.16#ibcon#first serial, iclass 7, count 0 2006.173.14:03:59.16#ibcon#enter sib2, iclass 7, count 0 2006.173.14:03:59.16#ibcon#flushed, iclass 7, count 0 2006.173.14:03:59.16#ibcon#about to write, iclass 7, count 0 2006.173.14:03:59.16#ibcon#wrote, iclass 7, count 0 2006.173.14:03:59.16#ibcon#about to read 3, iclass 7, count 0 2006.173.14:03:59.18#ibcon#read 3, iclass 7, count 0 2006.173.14:03:59.18#ibcon#about to read 4, iclass 7, count 0 2006.173.14:03:59.18#ibcon#read 4, iclass 7, count 0 2006.173.14:03:59.18#ibcon#about to read 5, iclass 7, count 0 2006.173.14:03:59.18#ibcon#read 5, iclass 7, count 0 2006.173.14:03:59.18#ibcon#about to read 6, iclass 7, count 0 2006.173.14:03:59.18#ibcon#read 6, iclass 7, count 0 2006.173.14:03:59.18#ibcon#end of sib2, iclass 7, count 0 2006.173.14:03:59.18#ibcon#*mode == 0, iclass 7, count 0 2006.173.14:03:59.18#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.14:03:59.18#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.14:03:59.18#ibcon#*before write, iclass 7, count 0 2006.173.14:03:59.18#ibcon#enter sib2, iclass 7, count 0 2006.173.14:03:59.18#ibcon#flushed, iclass 7, count 0 2006.173.14:03:59.18#ibcon#about to write, iclass 7, count 0 2006.173.14:03:59.18#ibcon#wrote, iclass 7, count 0 2006.173.14:03:59.18#ibcon#about to read 3, iclass 7, count 0 2006.173.14:03:59.22#ibcon#read 3, iclass 7, count 0 2006.173.14:03:59.22#ibcon#about to read 4, iclass 7, count 0 2006.173.14:03:59.22#ibcon#read 4, iclass 7, count 0 2006.173.14:03:59.22#ibcon#about to read 5, iclass 7, count 0 2006.173.14:03:59.22#ibcon#read 5, iclass 7, count 0 2006.173.14:03:59.22#ibcon#about to read 6, iclass 7, count 0 2006.173.14:03:59.22#ibcon#read 6, iclass 7, count 0 2006.173.14:03:59.22#ibcon#end of sib2, iclass 7, count 0 2006.173.14:03:59.22#ibcon#*after write, iclass 7, count 0 2006.173.14:03:59.22#ibcon#*before return 0, iclass 7, count 0 2006.173.14:03:59.22#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.14:03:59.22#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.14:03:59.22#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.14:03:59.22#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.14:03:59.22$vck44/vb=2,4 2006.173.14:03:59.22#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.14:03:59.22#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.14:03:59.22#ibcon#ireg 11 cls_cnt 2 2006.173.14:03:59.22#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.14:03:59.28#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.14:03:59.28#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.14:03:59.28#ibcon#enter wrdev, iclass 11, count 2 2006.173.14:03:59.28#ibcon#first serial, iclass 11, count 2 2006.173.14:03:59.28#ibcon#enter sib2, iclass 11, count 2 2006.173.14:03:59.28#ibcon#flushed, iclass 11, count 2 2006.173.14:03:59.28#ibcon#about to write, iclass 11, count 2 2006.173.14:03:59.28#ibcon#wrote, iclass 11, count 2 2006.173.14:03:59.28#ibcon#about to read 3, iclass 11, count 2 2006.173.14:03:59.30#ibcon#read 3, iclass 11, count 2 2006.173.14:03:59.30#ibcon#about to read 4, iclass 11, count 2 2006.173.14:03:59.30#ibcon#read 4, iclass 11, count 2 2006.173.14:03:59.30#ibcon#about to read 5, iclass 11, count 2 2006.173.14:03:59.30#ibcon#read 5, iclass 11, count 2 2006.173.14:03:59.30#ibcon#about to read 6, iclass 11, count 2 2006.173.14:03:59.30#ibcon#read 6, iclass 11, count 2 2006.173.14:03:59.30#ibcon#end of sib2, iclass 11, count 2 2006.173.14:03:59.30#ibcon#*mode == 0, iclass 11, count 2 2006.173.14:03:59.30#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.14:03:59.30#ibcon#[27=AT02-04\r\n] 2006.173.14:03:59.30#ibcon#*before write, iclass 11, count 2 2006.173.14:03:59.30#ibcon#enter sib2, iclass 11, count 2 2006.173.14:03:59.30#ibcon#flushed, iclass 11, count 2 2006.173.14:03:59.30#ibcon#about to write, iclass 11, count 2 2006.173.14:03:59.30#ibcon#wrote, iclass 11, count 2 2006.173.14:03:59.30#ibcon#about to read 3, iclass 11, count 2 2006.173.14:03:59.33#ibcon#read 3, iclass 11, count 2 2006.173.14:03:59.33#ibcon#about to read 4, iclass 11, count 2 2006.173.14:03:59.33#ibcon#read 4, iclass 11, count 2 2006.173.14:03:59.33#ibcon#about to read 5, iclass 11, count 2 2006.173.14:03:59.33#ibcon#read 5, iclass 11, count 2 2006.173.14:03:59.33#ibcon#about to read 6, iclass 11, count 2 2006.173.14:03:59.33#ibcon#read 6, iclass 11, count 2 2006.173.14:03:59.33#ibcon#end of sib2, iclass 11, count 2 2006.173.14:03:59.33#ibcon#*after write, iclass 11, count 2 2006.173.14:03:59.33#ibcon#*before return 0, iclass 11, count 2 2006.173.14:03:59.33#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.14:03:59.33#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.14:03:59.33#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.14:03:59.33#ibcon#ireg 7 cls_cnt 0 2006.173.14:03:59.33#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.14:03:59.45#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.14:03:59.45#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.14:03:59.45#ibcon#enter wrdev, iclass 11, count 0 2006.173.14:03:59.45#ibcon#first serial, iclass 11, count 0 2006.173.14:03:59.45#ibcon#enter sib2, iclass 11, count 0 2006.173.14:03:59.45#ibcon#flushed, iclass 11, count 0 2006.173.14:03:59.45#ibcon#about to write, iclass 11, count 0 2006.173.14:03:59.45#ibcon#wrote, iclass 11, count 0 2006.173.14:03:59.45#ibcon#about to read 3, iclass 11, count 0 2006.173.14:03:59.47#ibcon#read 3, iclass 11, count 0 2006.173.14:03:59.47#ibcon#about to read 4, iclass 11, count 0 2006.173.14:03:59.47#ibcon#read 4, iclass 11, count 0 2006.173.14:03:59.47#ibcon#about to read 5, iclass 11, count 0 2006.173.14:03:59.47#ibcon#read 5, iclass 11, count 0 2006.173.14:03:59.47#ibcon#about to read 6, iclass 11, count 0 2006.173.14:03:59.47#ibcon#read 6, iclass 11, count 0 2006.173.14:03:59.47#ibcon#end of sib2, iclass 11, count 0 2006.173.14:03:59.47#ibcon#*mode == 0, iclass 11, count 0 2006.173.14:03:59.47#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.14:03:59.47#ibcon#[27=USB\r\n] 2006.173.14:03:59.47#ibcon#*before write, iclass 11, count 0 2006.173.14:03:59.47#ibcon#enter sib2, iclass 11, count 0 2006.173.14:03:59.47#ibcon#flushed, iclass 11, count 0 2006.173.14:03:59.47#ibcon#about to write, iclass 11, count 0 2006.173.14:03:59.47#ibcon#wrote, iclass 11, count 0 2006.173.14:03:59.47#ibcon#about to read 3, iclass 11, count 0 2006.173.14:03:59.50#ibcon#read 3, iclass 11, count 0 2006.173.14:03:59.50#ibcon#about to read 4, iclass 11, count 0 2006.173.14:03:59.50#ibcon#read 4, iclass 11, count 0 2006.173.14:03:59.50#ibcon#about to read 5, iclass 11, count 0 2006.173.14:03:59.50#ibcon#read 5, iclass 11, count 0 2006.173.14:03:59.50#ibcon#about to read 6, iclass 11, count 0 2006.173.14:03:59.50#ibcon#read 6, iclass 11, count 0 2006.173.14:03:59.50#ibcon#end of sib2, iclass 11, count 0 2006.173.14:03:59.50#ibcon#*after write, iclass 11, count 0 2006.173.14:03:59.50#ibcon#*before return 0, iclass 11, count 0 2006.173.14:03:59.50#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.14:03:59.50#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.14:03:59.50#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.14:03:59.50#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.14:03:59.50$vck44/vblo=3,649.99 2006.173.14:03:59.50#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.14:03:59.50#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.14:03:59.50#ibcon#ireg 17 cls_cnt 0 2006.173.14:03:59.50#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.14:03:59.50#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.14:03:59.50#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.14:03:59.50#ibcon#enter wrdev, iclass 13, count 0 2006.173.14:03:59.50#ibcon#first serial, iclass 13, count 0 2006.173.14:03:59.50#ibcon#enter sib2, iclass 13, count 0 2006.173.14:03:59.50#ibcon#flushed, iclass 13, count 0 2006.173.14:03:59.50#ibcon#about to write, iclass 13, count 0 2006.173.14:03:59.50#ibcon#wrote, iclass 13, count 0 2006.173.14:03:59.50#ibcon#about to read 3, iclass 13, count 0 2006.173.14:03:59.52#ibcon#read 3, iclass 13, count 0 2006.173.14:03:59.52#ibcon#about to read 4, iclass 13, count 0 2006.173.14:03:59.52#ibcon#read 4, iclass 13, count 0 2006.173.14:03:59.52#ibcon#about to read 5, iclass 13, count 0 2006.173.14:03:59.52#ibcon#read 5, iclass 13, count 0 2006.173.14:03:59.52#ibcon#about to read 6, iclass 13, count 0 2006.173.14:03:59.52#ibcon#read 6, iclass 13, count 0 2006.173.14:03:59.52#ibcon#end of sib2, iclass 13, count 0 2006.173.14:03:59.52#ibcon#*mode == 0, iclass 13, count 0 2006.173.14:03:59.52#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.14:03:59.52#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.14:03:59.52#ibcon#*before write, iclass 13, count 0 2006.173.14:03:59.52#ibcon#enter sib2, iclass 13, count 0 2006.173.14:03:59.52#ibcon#flushed, iclass 13, count 0 2006.173.14:03:59.52#ibcon#about to write, iclass 13, count 0 2006.173.14:03:59.52#ibcon#wrote, iclass 13, count 0 2006.173.14:03:59.52#ibcon#about to read 3, iclass 13, count 0 2006.173.14:03:59.56#ibcon#read 3, iclass 13, count 0 2006.173.14:03:59.56#ibcon#about to read 4, iclass 13, count 0 2006.173.14:03:59.56#ibcon#read 4, iclass 13, count 0 2006.173.14:03:59.56#ibcon#about to read 5, iclass 13, count 0 2006.173.14:03:59.56#ibcon#read 5, iclass 13, count 0 2006.173.14:03:59.56#ibcon#about to read 6, iclass 13, count 0 2006.173.14:03:59.56#ibcon#read 6, iclass 13, count 0 2006.173.14:03:59.56#ibcon#end of sib2, iclass 13, count 0 2006.173.14:03:59.56#ibcon#*after write, iclass 13, count 0 2006.173.14:03:59.56#ibcon#*before return 0, iclass 13, count 0 2006.173.14:03:59.56#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.14:03:59.56#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.14:03:59.56#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.14:03:59.56#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.14:03:59.56$vck44/vb=3,4 2006.173.14:03:59.56#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.14:03:59.56#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.14:03:59.56#ibcon#ireg 11 cls_cnt 2 2006.173.14:03:59.56#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.14:03:59.62#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.14:03:59.62#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.14:03:59.62#ibcon#enter wrdev, iclass 15, count 2 2006.173.14:03:59.62#ibcon#first serial, iclass 15, count 2 2006.173.14:03:59.62#ibcon#enter sib2, iclass 15, count 2 2006.173.14:03:59.62#ibcon#flushed, iclass 15, count 2 2006.173.14:03:59.62#ibcon#about to write, iclass 15, count 2 2006.173.14:03:59.62#ibcon#wrote, iclass 15, count 2 2006.173.14:03:59.62#ibcon#about to read 3, iclass 15, count 2 2006.173.14:03:59.64#ibcon#read 3, iclass 15, count 2 2006.173.14:03:59.64#ibcon#about to read 4, iclass 15, count 2 2006.173.14:03:59.64#ibcon#read 4, iclass 15, count 2 2006.173.14:03:59.64#ibcon#about to read 5, iclass 15, count 2 2006.173.14:03:59.64#ibcon#read 5, iclass 15, count 2 2006.173.14:03:59.64#ibcon#about to read 6, iclass 15, count 2 2006.173.14:03:59.64#ibcon#read 6, iclass 15, count 2 2006.173.14:03:59.64#ibcon#end of sib2, iclass 15, count 2 2006.173.14:03:59.64#ibcon#*mode == 0, iclass 15, count 2 2006.173.14:03:59.64#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.14:03:59.64#ibcon#[27=AT03-04\r\n] 2006.173.14:03:59.64#ibcon#*before write, iclass 15, count 2 2006.173.14:03:59.64#ibcon#enter sib2, iclass 15, count 2 2006.173.14:03:59.64#ibcon#flushed, iclass 15, count 2 2006.173.14:03:59.64#ibcon#about to write, iclass 15, count 2 2006.173.14:03:59.64#ibcon#wrote, iclass 15, count 2 2006.173.14:03:59.64#ibcon#about to read 3, iclass 15, count 2 2006.173.14:03:59.67#ibcon#read 3, iclass 15, count 2 2006.173.14:03:59.67#ibcon#about to read 4, iclass 15, count 2 2006.173.14:03:59.67#ibcon#read 4, iclass 15, count 2 2006.173.14:03:59.67#ibcon#about to read 5, iclass 15, count 2 2006.173.14:03:59.67#ibcon#read 5, iclass 15, count 2 2006.173.14:03:59.67#ibcon#about to read 6, iclass 15, count 2 2006.173.14:03:59.67#ibcon#read 6, iclass 15, count 2 2006.173.14:03:59.67#ibcon#end of sib2, iclass 15, count 2 2006.173.14:03:59.67#ibcon#*after write, iclass 15, count 2 2006.173.14:03:59.67#ibcon#*before return 0, iclass 15, count 2 2006.173.14:03:59.67#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.14:03:59.67#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.14:03:59.67#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.14:03:59.67#ibcon#ireg 7 cls_cnt 0 2006.173.14:03:59.67#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.14:03:59.79#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.14:03:59.79#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.14:03:59.79#ibcon#enter wrdev, iclass 15, count 0 2006.173.14:03:59.79#ibcon#first serial, iclass 15, count 0 2006.173.14:03:59.79#ibcon#enter sib2, iclass 15, count 0 2006.173.14:03:59.79#ibcon#flushed, iclass 15, count 0 2006.173.14:03:59.79#ibcon#about to write, iclass 15, count 0 2006.173.14:03:59.79#ibcon#wrote, iclass 15, count 0 2006.173.14:03:59.79#ibcon#about to read 3, iclass 15, count 0 2006.173.14:03:59.81#ibcon#read 3, iclass 15, count 0 2006.173.14:03:59.81#ibcon#about to read 4, iclass 15, count 0 2006.173.14:03:59.81#ibcon#read 4, iclass 15, count 0 2006.173.14:03:59.81#ibcon#about to read 5, iclass 15, count 0 2006.173.14:03:59.81#ibcon#read 5, iclass 15, count 0 2006.173.14:03:59.81#ibcon#about to read 6, iclass 15, count 0 2006.173.14:03:59.81#ibcon#read 6, iclass 15, count 0 2006.173.14:03:59.81#ibcon#end of sib2, iclass 15, count 0 2006.173.14:03:59.81#ibcon#*mode == 0, iclass 15, count 0 2006.173.14:03:59.81#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.14:03:59.81#ibcon#[27=USB\r\n] 2006.173.14:03:59.81#ibcon#*before write, iclass 15, count 0 2006.173.14:03:59.81#ibcon#enter sib2, iclass 15, count 0 2006.173.14:03:59.81#ibcon#flushed, iclass 15, count 0 2006.173.14:03:59.81#ibcon#about to write, iclass 15, count 0 2006.173.14:03:59.81#ibcon#wrote, iclass 15, count 0 2006.173.14:03:59.81#ibcon#about to read 3, iclass 15, count 0 2006.173.14:03:59.84#ibcon#read 3, iclass 15, count 0 2006.173.14:03:59.84#ibcon#about to read 4, iclass 15, count 0 2006.173.14:03:59.84#ibcon#read 4, iclass 15, count 0 2006.173.14:03:59.84#ibcon#about to read 5, iclass 15, count 0 2006.173.14:03:59.84#ibcon#read 5, iclass 15, count 0 2006.173.14:03:59.84#ibcon#about to read 6, iclass 15, count 0 2006.173.14:03:59.84#ibcon#read 6, iclass 15, count 0 2006.173.14:03:59.84#ibcon#end of sib2, iclass 15, count 0 2006.173.14:03:59.84#ibcon#*after write, iclass 15, count 0 2006.173.14:03:59.84#ibcon#*before return 0, iclass 15, count 0 2006.173.14:03:59.84#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.14:03:59.84#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.14:03:59.84#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.14:03:59.84#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.14:03:59.84$vck44/vblo=4,679.99 2006.173.14:03:59.84#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.14:03:59.84#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.14:03:59.84#ibcon#ireg 17 cls_cnt 0 2006.173.14:03:59.84#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.14:03:59.84#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.14:03:59.84#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.14:03:59.84#ibcon#enter wrdev, iclass 17, count 0 2006.173.14:03:59.84#ibcon#first serial, iclass 17, count 0 2006.173.14:03:59.84#ibcon#enter sib2, iclass 17, count 0 2006.173.14:03:59.84#ibcon#flushed, iclass 17, count 0 2006.173.14:03:59.84#ibcon#about to write, iclass 17, count 0 2006.173.14:03:59.84#ibcon#wrote, iclass 17, count 0 2006.173.14:03:59.84#ibcon#about to read 3, iclass 17, count 0 2006.173.14:03:59.86#ibcon#read 3, iclass 17, count 0 2006.173.14:03:59.86#ibcon#about to read 4, iclass 17, count 0 2006.173.14:03:59.86#ibcon#read 4, iclass 17, count 0 2006.173.14:03:59.86#ibcon#about to read 5, iclass 17, count 0 2006.173.14:03:59.86#ibcon#read 5, iclass 17, count 0 2006.173.14:03:59.86#ibcon#about to read 6, iclass 17, count 0 2006.173.14:03:59.86#ibcon#read 6, iclass 17, count 0 2006.173.14:03:59.86#ibcon#end of sib2, iclass 17, count 0 2006.173.14:03:59.86#ibcon#*mode == 0, iclass 17, count 0 2006.173.14:03:59.86#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.14:03:59.86#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.14:03:59.86#ibcon#*before write, iclass 17, count 0 2006.173.14:03:59.86#ibcon#enter sib2, iclass 17, count 0 2006.173.14:03:59.86#ibcon#flushed, iclass 17, count 0 2006.173.14:03:59.86#ibcon#about to write, iclass 17, count 0 2006.173.14:03:59.86#ibcon#wrote, iclass 17, count 0 2006.173.14:03:59.86#ibcon#about to read 3, iclass 17, count 0 2006.173.14:03:59.90#ibcon#read 3, iclass 17, count 0 2006.173.14:03:59.90#ibcon#about to read 4, iclass 17, count 0 2006.173.14:03:59.90#ibcon#read 4, iclass 17, count 0 2006.173.14:03:59.90#ibcon#about to read 5, iclass 17, count 0 2006.173.14:03:59.90#ibcon#read 5, iclass 17, count 0 2006.173.14:03:59.90#ibcon#about to read 6, iclass 17, count 0 2006.173.14:03:59.90#ibcon#read 6, iclass 17, count 0 2006.173.14:03:59.90#ibcon#end of sib2, iclass 17, count 0 2006.173.14:03:59.90#ibcon#*after write, iclass 17, count 0 2006.173.14:03:59.90#ibcon#*before return 0, iclass 17, count 0 2006.173.14:03:59.90#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.14:03:59.90#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.14:03:59.90#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.14:03:59.90#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.14:03:59.90$vck44/vb=4,4 2006.173.14:03:59.90#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.14:03:59.90#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.14:03:59.90#ibcon#ireg 11 cls_cnt 2 2006.173.14:03:59.90#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.14:03:59.96#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.14:03:59.96#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.14:03:59.96#ibcon#enter wrdev, iclass 19, count 2 2006.173.14:03:59.96#ibcon#first serial, iclass 19, count 2 2006.173.14:03:59.96#ibcon#enter sib2, iclass 19, count 2 2006.173.14:03:59.96#ibcon#flushed, iclass 19, count 2 2006.173.14:03:59.96#ibcon#about to write, iclass 19, count 2 2006.173.14:03:59.96#ibcon#wrote, iclass 19, count 2 2006.173.14:03:59.96#ibcon#about to read 3, iclass 19, count 2 2006.173.14:03:59.98#ibcon#read 3, iclass 19, count 2 2006.173.14:03:59.98#ibcon#about to read 4, iclass 19, count 2 2006.173.14:03:59.98#ibcon#read 4, iclass 19, count 2 2006.173.14:03:59.98#ibcon#about to read 5, iclass 19, count 2 2006.173.14:03:59.98#ibcon#read 5, iclass 19, count 2 2006.173.14:03:59.98#ibcon#about to read 6, iclass 19, count 2 2006.173.14:03:59.98#ibcon#read 6, iclass 19, count 2 2006.173.14:03:59.98#ibcon#end of sib2, iclass 19, count 2 2006.173.14:03:59.98#ibcon#*mode == 0, iclass 19, count 2 2006.173.14:03:59.98#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.14:03:59.98#ibcon#[27=AT04-04\r\n] 2006.173.14:03:59.98#ibcon#*before write, iclass 19, count 2 2006.173.14:03:59.98#ibcon#enter sib2, iclass 19, count 2 2006.173.14:03:59.98#ibcon#flushed, iclass 19, count 2 2006.173.14:03:59.98#ibcon#about to write, iclass 19, count 2 2006.173.14:03:59.98#ibcon#wrote, iclass 19, count 2 2006.173.14:03:59.98#ibcon#about to read 3, iclass 19, count 2 2006.173.14:04:00.01#ibcon#read 3, iclass 19, count 2 2006.173.14:04:00.01#ibcon#about to read 4, iclass 19, count 2 2006.173.14:04:00.01#ibcon#read 4, iclass 19, count 2 2006.173.14:04:00.01#ibcon#about to read 5, iclass 19, count 2 2006.173.14:04:00.01#ibcon#read 5, iclass 19, count 2 2006.173.14:04:00.01#ibcon#about to read 6, iclass 19, count 2 2006.173.14:04:00.01#ibcon#read 6, iclass 19, count 2 2006.173.14:04:00.01#ibcon#end of sib2, iclass 19, count 2 2006.173.14:04:00.01#ibcon#*after write, iclass 19, count 2 2006.173.14:04:00.01#ibcon#*before return 0, iclass 19, count 2 2006.173.14:04:00.01#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.14:04:00.01#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.14:04:00.01#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.14:04:00.01#ibcon#ireg 7 cls_cnt 0 2006.173.14:04:00.01#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.14:04:00.13#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.14:04:00.13#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.14:04:00.13#ibcon#enter wrdev, iclass 19, count 0 2006.173.14:04:00.13#ibcon#first serial, iclass 19, count 0 2006.173.14:04:00.13#ibcon#enter sib2, iclass 19, count 0 2006.173.14:04:00.13#ibcon#flushed, iclass 19, count 0 2006.173.14:04:00.13#ibcon#about to write, iclass 19, count 0 2006.173.14:04:00.13#ibcon#wrote, iclass 19, count 0 2006.173.14:04:00.13#ibcon#about to read 3, iclass 19, count 0 2006.173.14:04:00.15#ibcon#read 3, iclass 19, count 0 2006.173.14:04:00.15#ibcon#about to read 4, iclass 19, count 0 2006.173.14:04:00.15#ibcon#read 4, iclass 19, count 0 2006.173.14:04:00.15#ibcon#about to read 5, iclass 19, count 0 2006.173.14:04:00.15#ibcon#read 5, iclass 19, count 0 2006.173.14:04:00.15#ibcon#about to read 6, iclass 19, count 0 2006.173.14:04:00.15#ibcon#read 6, iclass 19, count 0 2006.173.14:04:00.15#ibcon#end of sib2, iclass 19, count 0 2006.173.14:04:00.15#ibcon#*mode == 0, iclass 19, count 0 2006.173.14:04:00.15#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.14:04:00.15#ibcon#[27=USB\r\n] 2006.173.14:04:00.15#ibcon#*before write, iclass 19, count 0 2006.173.14:04:00.15#ibcon#enter sib2, iclass 19, count 0 2006.173.14:04:00.15#ibcon#flushed, iclass 19, count 0 2006.173.14:04:00.15#ibcon#about to write, iclass 19, count 0 2006.173.14:04:00.15#ibcon#wrote, iclass 19, count 0 2006.173.14:04:00.15#ibcon#about to read 3, iclass 19, count 0 2006.173.14:04:00.18#ibcon#read 3, iclass 19, count 0 2006.173.14:04:00.18#ibcon#about to read 4, iclass 19, count 0 2006.173.14:04:00.18#ibcon#read 4, iclass 19, count 0 2006.173.14:04:00.18#ibcon#about to read 5, iclass 19, count 0 2006.173.14:04:00.18#ibcon#read 5, iclass 19, count 0 2006.173.14:04:00.18#ibcon#about to read 6, iclass 19, count 0 2006.173.14:04:00.18#ibcon#read 6, iclass 19, count 0 2006.173.14:04:00.18#ibcon#end of sib2, iclass 19, count 0 2006.173.14:04:00.18#ibcon#*after write, iclass 19, count 0 2006.173.14:04:00.18#ibcon#*before return 0, iclass 19, count 0 2006.173.14:04:00.18#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.14:04:00.18#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.14:04:00.18#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.14:04:00.18#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.14:04:00.18$vck44/vblo=5,709.99 2006.173.14:04:00.18#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.14:04:00.18#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.14:04:00.18#ibcon#ireg 17 cls_cnt 0 2006.173.14:04:00.18#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.14:04:00.18#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.14:04:00.18#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.14:04:00.18#ibcon#enter wrdev, iclass 21, count 0 2006.173.14:04:00.18#ibcon#first serial, iclass 21, count 0 2006.173.14:04:00.18#ibcon#enter sib2, iclass 21, count 0 2006.173.14:04:00.18#ibcon#flushed, iclass 21, count 0 2006.173.14:04:00.18#ibcon#about to write, iclass 21, count 0 2006.173.14:04:00.18#ibcon#wrote, iclass 21, count 0 2006.173.14:04:00.18#ibcon#about to read 3, iclass 21, count 0 2006.173.14:04:00.20#ibcon#read 3, iclass 21, count 0 2006.173.14:04:00.20#ibcon#about to read 4, iclass 21, count 0 2006.173.14:04:00.20#ibcon#read 4, iclass 21, count 0 2006.173.14:04:00.20#ibcon#about to read 5, iclass 21, count 0 2006.173.14:04:00.20#ibcon#read 5, iclass 21, count 0 2006.173.14:04:00.20#ibcon#about to read 6, iclass 21, count 0 2006.173.14:04:00.20#ibcon#read 6, iclass 21, count 0 2006.173.14:04:00.20#ibcon#end of sib2, iclass 21, count 0 2006.173.14:04:00.20#ibcon#*mode == 0, iclass 21, count 0 2006.173.14:04:00.20#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.14:04:00.20#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.14:04:00.20#ibcon#*before write, iclass 21, count 0 2006.173.14:04:00.20#ibcon#enter sib2, iclass 21, count 0 2006.173.14:04:00.20#ibcon#flushed, iclass 21, count 0 2006.173.14:04:00.20#ibcon#about to write, iclass 21, count 0 2006.173.14:04:00.20#ibcon#wrote, iclass 21, count 0 2006.173.14:04:00.20#ibcon#about to read 3, iclass 21, count 0 2006.173.14:04:00.24#ibcon#read 3, iclass 21, count 0 2006.173.14:04:00.24#ibcon#about to read 4, iclass 21, count 0 2006.173.14:04:00.24#ibcon#read 4, iclass 21, count 0 2006.173.14:04:00.24#ibcon#about to read 5, iclass 21, count 0 2006.173.14:04:00.24#ibcon#read 5, iclass 21, count 0 2006.173.14:04:00.24#ibcon#about to read 6, iclass 21, count 0 2006.173.14:04:00.24#ibcon#read 6, iclass 21, count 0 2006.173.14:04:00.24#ibcon#end of sib2, iclass 21, count 0 2006.173.14:04:00.24#ibcon#*after write, iclass 21, count 0 2006.173.14:04:00.24#ibcon#*before return 0, iclass 21, count 0 2006.173.14:04:00.24#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.14:04:00.24#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.14:04:00.24#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.14:04:00.24#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.14:04:00.24$vck44/vb=5,4 2006.173.14:04:00.24#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.14:04:00.24#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.14:04:00.24#ibcon#ireg 11 cls_cnt 2 2006.173.14:04:00.24#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.14:04:00.30#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.14:04:00.30#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.14:04:00.30#ibcon#enter wrdev, iclass 23, count 2 2006.173.14:04:00.30#ibcon#first serial, iclass 23, count 2 2006.173.14:04:00.30#ibcon#enter sib2, iclass 23, count 2 2006.173.14:04:00.30#ibcon#flushed, iclass 23, count 2 2006.173.14:04:00.30#ibcon#about to write, iclass 23, count 2 2006.173.14:04:00.30#ibcon#wrote, iclass 23, count 2 2006.173.14:04:00.30#ibcon#about to read 3, iclass 23, count 2 2006.173.14:04:00.32#ibcon#read 3, iclass 23, count 2 2006.173.14:04:00.32#ibcon#about to read 4, iclass 23, count 2 2006.173.14:04:00.32#ibcon#read 4, iclass 23, count 2 2006.173.14:04:00.32#ibcon#about to read 5, iclass 23, count 2 2006.173.14:04:00.32#ibcon#read 5, iclass 23, count 2 2006.173.14:04:00.32#ibcon#about to read 6, iclass 23, count 2 2006.173.14:04:00.32#ibcon#read 6, iclass 23, count 2 2006.173.14:04:00.32#ibcon#end of sib2, iclass 23, count 2 2006.173.14:04:00.32#ibcon#*mode == 0, iclass 23, count 2 2006.173.14:04:00.32#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.14:04:00.32#ibcon#[27=AT05-04\r\n] 2006.173.14:04:00.32#ibcon#*before write, iclass 23, count 2 2006.173.14:04:00.32#ibcon#enter sib2, iclass 23, count 2 2006.173.14:04:00.32#ibcon#flushed, iclass 23, count 2 2006.173.14:04:00.32#ibcon#about to write, iclass 23, count 2 2006.173.14:04:00.32#ibcon#wrote, iclass 23, count 2 2006.173.14:04:00.32#ibcon#about to read 3, iclass 23, count 2 2006.173.14:04:00.35#ibcon#read 3, iclass 23, count 2 2006.173.14:04:00.35#ibcon#about to read 4, iclass 23, count 2 2006.173.14:04:00.35#ibcon#read 4, iclass 23, count 2 2006.173.14:04:00.35#ibcon#about to read 5, iclass 23, count 2 2006.173.14:04:00.35#ibcon#read 5, iclass 23, count 2 2006.173.14:04:00.35#ibcon#about to read 6, iclass 23, count 2 2006.173.14:04:00.35#ibcon#read 6, iclass 23, count 2 2006.173.14:04:00.35#ibcon#end of sib2, iclass 23, count 2 2006.173.14:04:00.35#ibcon#*after write, iclass 23, count 2 2006.173.14:04:00.35#ibcon#*before return 0, iclass 23, count 2 2006.173.14:04:00.35#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.14:04:00.35#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.14:04:00.35#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.14:04:00.35#ibcon#ireg 7 cls_cnt 0 2006.173.14:04:00.35#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.14:04:00.47#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.14:04:00.47#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.14:04:00.47#ibcon#enter wrdev, iclass 23, count 0 2006.173.14:04:00.47#ibcon#first serial, iclass 23, count 0 2006.173.14:04:00.47#ibcon#enter sib2, iclass 23, count 0 2006.173.14:04:00.47#ibcon#flushed, iclass 23, count 0 2006.173.14:04:00.47#ibcon#about to write, iclass 23, count 0 2006.173.14:04:00.47#ibcon#wrote, iclass 23, count 0 2006.173.14:04:00.47#ibcon#about to read 3, iclass 23, count 0 2006.173.14:04:00.49#ibcon#read 3, iclass 23, count 0 2006.173.14:04:00.49#ibcon#about to read 4, iclass 23, count 0 2006.173.14:04:00.49#ibcon#read 4, iclass 23, count 0 2006.173.14:04:00.49#ibcon#about to read 5, iclass 23, count 0 2006.173.14:04:00.49#ibcon#read 5, iclass 23, count 0 2006.173.14:04:00.49#ibcon#about to read 6, iclass 23, count 0 2006.173.14:04:00.49#ibcon#read 6, iclass 23, count 0 2006.173.14:04:00.49#ibcon#end of sib2, iclass 23, count 0 2006.173.14:04:00.49#ibcon#*mode == 0, iclass 23, count 0 2006.173.14:04:00.49#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.14:04:00.49#ibcon#[27=USB\r\n] 2006.173.14:04:00.49#ibcon#*before write, iclass 23, count 0 2006.173.14:04:00.49#ibcon#enter sib2, iclass 23, count 0 2006.173.14:04:00.49#ibcon#flushed, iclass 23, count 0 2006.173.14:04:00.49#ibcon#about to write, iclass 23, count 0 2006.173.14:04:00.49#ibcon#wrote, iclass 23, count 0 2006.173.14:04:00.49#ibcon#about to read 3, iclass 23, count 0 2006.173.14:04:00.52#ibcon#read 3, iclass 23, count 0 2006.173.14:04:00.52#ibcon#about to read 4, iclass 23, count 0 2006.173.14:04:00.52#ibcon#read 4, iclass 23, count 0 2006.173.14:04:00.52#ibcon#about to read 5, iclass 23, count 0 2006.173.14:04:00.52#ibcon#read 5, iclass 23, count 0 2006.173.14:04:00.52#ibcon#about to read 6, iclass 23, count 0 2006.173.14:04:00.52#ibcon#read 6, iclass 23, count 0 2006.173.14:04:00.52#ibcon#end of sib2, iclass 23, count 0 2006.173.14:04:00.52#ibcon#*after write, iclass 23, count 0 2006.173.14:04:00.52#ibcon#*before return 0, iclass 23, count 0 2006.173.14:04:00.52#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.14:04:00.52#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.14:04:00.52#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.14:04:00.52#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.14:04:00.52$vck44/vblo=6,719.99 2006.173.14:04:00.52#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.14:04:00.52#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.14:04:00.52#ibcon#ireg 17 cls_cnt 0 2006.173.14:04:00.52#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.14:04:00.52#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.14:04:00.52#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.14:04:00.52#ibcon#enter wrdev, iclass 25, count 0 2006.173.14:04:00.52#ibcon#first serial, iclass 25, count 0 2006.173.14:04:00.52#ibcon#enter sib2, iclass 25, count 0 2006.173.14:04:00.52#ibcon#flushed, iclass 25, count 0 2006.173.14:04:00.52#ibcon#about to write, iclass 25, count 0 2006.173.14:04:00.52#ibcon#wrote, iclass 25, count 0 2006.173.14:04:00.52#ibcon#about to read 3, iclass 25, count 0 2006.173.14:04:00.54#ibcon#read 3, iclass 25, count 0 2006.173.14:04:00.54#ibcon#about to read 4, iclass 25, count 0 2006.173.14:04:00.54#ibcon#read 4, iclass 25, count 0 2006.173.14:04:00.54#ibcon#about to read 5, iclass 25, count 0 2006.173.14:04:00.54#ibcon#read 5, iclass 25, count 0 2006.173.14:04:00.54#ibcon#about to read 6, iclass 25, count 0 2006.173.14:04:00.54#ibcon#read 6, iclass 25, count 0 2006.173.14:04:00.54#ibcon#end of sib2, iclass 25, count 0 2006.173.14:04:00.54#ibcon#*mode == 0, iclass 25, count 0 2006.173.14:04:00.54#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.14:04:00.54#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.14:04:00.54#ibcon#*before write, iclass 25, count 0 2006.173.14:04:00.54#ibcon#enter sib2, iclass 25, count 0 2006.173.14:04:00.54#ibcon#flushed, iclass 25, count 0 2006.173.14:04:00.54#ibcon#about to write, iclass 25, count 0 2006.173.14:04:00.54#ibcon#wrote, iclass 25, count 0 2006.173.14:04:00.54#ibcon#about to read 3, iclass 25, count 0 2006.173.14:04:00.58#ibcon#read 3, iclass 25, count 0 2006.173.14:04:00.58#ibcon#about to read 4, iclass 25, count 0 2006.173.14:04:00.58#ibcon#read 4, iclass 25, count 0 2006.173.14:04:00.58#ibcon#about to read 5, iclass 25, count 0 2006.173.14:04:00.58#ibcon#read 5, iclass 25, count 0 2006.173.14:04:00.58#ibcon#about to read 6, iclass 25, count 0 2006.173.14:04:00.58#ibcon#read 6, iclass 25, count 0 2006.173.14:04:00.58#ibcon#end of sib2, iclass 25, count 0 2006.173.14:04:00.58#ibcon#*after write, iclass 25, count 0 2006.173.14:04:00.58#ibcon#*before return 0, iclass 25, count 0 2006.173.14:04:00.58#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.14:04:00.58#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.14:04:00.58#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.14:04:00.58#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.14:04:00.58$vck44/vb=6,4 2006.173.14:04:00.58#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.14:04:00.58#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.14:04:00.58#ibcon#ireg 11 cls_cnt 2 2006.173.14:04:00.58#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.14:04:00.64#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.14:04:00.64#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.14:04:00.64#ibcon#enter wrdev, iclass 27, count 2 2006.173.14:04:00.64#ibcon#first serial, iclass 27, count 2 2006.173.14:04:00.64#ibcon#enter sib2, iclass 27, count 2 2006.173.14:04:00.64#ibcon#flushed, iclass 27, count 2 2006.173.14:04:00.64#ibcon#about to write, iclass 27, count 2 2006.173.14:04:00.64#ibcon#wrote, iclass 27, count 2 2006.173.14:04:00.64#ibcon#about to read 3, iclass 27, count 2 2006.173.14:04:00.66#ibcon#read 3, iclass 27, count 2 2006.173.14:04:00.66#ibcon#about to read 4, iclass 27, count 2 2006.173.14:04:00.66#ibcon#read 4, iclass 27, count 2 2006.173.14:04:00.66#ibcon#about to read 5, iclass 27, count 2 2006.173.14:04:00.66#ibcon#read 5, iclass 27, count 2 2006.173.14:04:00.66#ibcon#about to read 6, iclass 27, count 2 2006.173.14:04:00.66#ibcon#read 6, iclass 27, count 2 2006.173.14:04:00.66#ibcon#end of sib2, iclass 27, count 2 2006.173.14:04:00.66#ibcon#*mode == 0, iclass 27, count 2 2006.173.14:04:00.66#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.14:04:00.66#ibcon#[27=AT06-04\r\n] 2006.173.14:04:00.66#ibcon#*before write, iclass 27, count 2 2006.173.14:04:00.66#ibcon#enter sib2, iclass 27, count 2 2006.173.14:04:00.66#ibcon#flushed, iclass 27, count 2 2006.173.14:04:00.66#ibcon#about to write, iclass 27, count 2 2006.173.14:04:00.66#ibcon#wrote, iclass 27, count 2 2006.173.14:04:00.66#ibcon#about to read 3, iclass 27, count 2 2006.173.14:04:00.69#ibcon#read 3, iclass 27, count 2 2006.173.14:04:00.69#ibcon#about to read 4, iclass 27, count 2 2006.173.14:04:00.69#ibcon#read 4, iclass 27, count 2 2006.173.14:04:00.69#ibcon#about to read 5, iclass 27, count 2 2006.173.14:04:00.69#ibcon#read 5, iclass 27, count 2 2006.173.14:04:00.69#ibcon#about to read 6, iclass 27, count 2 2006.173.14:04:00.69#ibcon#read 6, iclass 27, count 2 2006.173.14:04:00.69#ibcon#end of sib2, iclass 27, count 2 2006.173.14:04:00.69#ibcon#*after write, iclass 27, count 2 2006.173.14:04:00.69#ibcon#*before return 0, iclass 27, count 2 2006.173.14:04:00.69#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.14:04:00.69#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.14:04:00.69#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.14:04:00.69#ibcon#ireg 7 cls_cnt 0 2006.173.14:04:00.69#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.14:04:00.81#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.14:04:00.81#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.14:04:00.81#ibcon#enter wrdev, iclass 27, count 0 2006.173.14:04:00.81#ibcon#first serial, iclass 27, count 0 2006.173.14:04:00.81#ibcon#enter sib2, iclass 27, count 0 2006.173.14:04:00.81#ibcon#flushed, iclass 27, count 0 2006.173.14:04:00.81#ibcon#about to write, iclass 27, count 0 2006.173.14:04:00.81#ibcon#wrote, iclass 27, count 0 2006.173.14:04:00.81#ibcon#about to read 3, iclass 27, count 0 2006.173.14:04:00.83#ibcon#read 3, iclass 27, count 0 2006.173.14:04:00.83#ibcon#about to read 4, iclass 27, count 0 2006.173.14:04:00.83#ibcon#read 4, iclass 27, count 0 2006.173.14:04:00.83#ibcon#about to read 5, iclass 27, count 0 2006.173.14:04:00.83#ibcon#read 5, iclass 27, count 0 2006.173.14:04:00.83#ibcon#about to read 6, iclass 27, count 0 2006.173.14:04:00.83#ibcon#read 6, iclass 27, count 0 2006.173.14:04:00.83#ibcon#end of sib2, iclass 27, count 0 2006.173.14:04:00.83#ibcon#*mode == 0, iclass 27, count 0 2006.173.14:04:00.83#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.14:04:00.83#ibcon#[27=USB\r\n] 2006.173.14:04:00.83#ibcon#*before write, iclass 27, count 0 2006.173.14:04:00.83#ibcon#enter sib2, iclass 27, count 0 2006.173.14:04:00.83#ibcon#flushed, iclass 27, count 0 2006.173.14:04:00.83#ibcon#about to write, iclass 27, count 0 2006.173.14:04:00.83#ibcon#wrote, iclass 27, count 0 2006.173.14:04:00.83#ibcon#about to read 3, iclass 27, count 0 2006.173.14:04:00.86#ibcon#read 3, iclass 27, count 0 2006.173.14:04:00.86#ibcon#about to read 4, iclass 27, count 0 2006.173.14:04:00.86#ibcon#read 4, iclass 27, count 0 2006.173.14:04:00.86#ibcon#about to read 5, iclass 27, count 0 2006.173.14:04:00.86#ibcon#read 5, iclass 27, count 0 2006.173.14:04:00.86#ibcon#about to read 6, iclass 27, count 0 2006.173.14:04:00.86#ibcon#read 6, iclass 27, count 0 2006.173.14:04:00.86#ibcon#end of sib2, iclass 27, count 0 2006.173.14:04:00.86#ibcon#*after write, iclass 27, count 0 2006.173.14:04:00.86#ibcon#*before return 0, iclass 27, count 0 2006.173.14:04:00.86#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.14:04:00.86#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.14:04:00.86#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.14:04:00.86#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.14:04:00.86$vck44/vblo=7,734.99 2006.173.14:04:00.86#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.14:04:00.86#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.14:04:00.86#ibcon#ireg 17 cls_cnt 0 2006.173.14:04:00.86#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.14:04:00.86#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.14:04:00.86#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.14:04:00.86#ibcon#enter wrdev, iclass 29, count 0 2006.173.14:04:00.86#ibcon#first serial, iclass 29, count 0 2006.173.14:04:00.86#ibcon#enter sib2, iclass 29, count 0 2006.173.14:04:00.86#ibcon#flushed, iclass 29, count 0 2006.173.14:04:00.86#ibcon#about to write, iclass 29, count 0 2006.173.14:04:00.86#ibcon#wrote, iclass 29, count 0 2006.173.14:04:00.86#ibcon#about to read 3, iclass 29, count 0 2006.173.14:04:00.88#ibcon#read 3, iclass 29, count 0 2006.173.14:04:00.88#ibcon#about to read 4, iclass 29, count 0 2006.173.14:04:00.88#ibcon#read 4, iclass 29, count 0 2006.173.14:04:00.88#ibcon#about to read 5, iclass 29, count 0 2006.173.14:04:00.88#ibcon#read 5, iclass 29, count 0 2006.173.14:04:00.88#ibcon#about to read 6, iclass 29, count 0 2006.173.14:04:00.88#ibcon#read 6, iclass 29, count 0 2006.173.14:04:00.88#ibcon#end of sib2, iclass 29, count 0 2006.173.14:04:00.88#ibcon#*mode == 0, iclass 29, count 0 2006.173.14:04:00.88#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.14:04:00.88#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.14:04:00.88#ibcon#*before write, iclass 29, count 0 2006.173.14:04:00.88#ibcon#enter sib2, iclass 29, count 0 2006.173.14:04:00.88#ibcon#flushed, iclass 29, count 0 2006.173.14:04:00.88#ibcon#about to write, iclass 29, count 0 2006.173.14:04:00.88#ibcon#wrote, iclass 29, count 0 2006.173.14:04:00.88#ibcon#about to read 3, iclass 29, count 0 2006.173.14:04:00.92#ibcon#read 3, iclass 29, count 0 2006.173.14:04:00.92#ibcon#about to read 4, iclass 29, count 0 2006.173.14:04:00.92#ibcon#read 4, iclass 29, count 0 2006.173.14:04:00.92#ibcon#about to read 5, iclass 29, count 0 2006.173.14:04:00.92#ibcon#read 5, iclass 29, count 0 2006.173.14:04:00.92#ibcon#about to read 6, iclass 29, count 0 2006.173.14:04:00.92#ibcon#read 6, iclass 29, count 0 2006.173.14:04:00.92#ibcon#end of sib2, iclass 29, count 0 2006.173.14:04:00.92#ibcon#*after write, iclass 29, count 0 2006.173.14:04:00.92#ibcon#*before return 0, iclass 29, count 0 2006.173.14:04:00.92#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.14:04:00.92#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.14:04:00.92#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.14:04:00.92#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.14:04:00.92$vck44/vb=7,4 2006.173.14:04:00.92#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.14:04:00.92#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.14:04:00.92#ibcon#ireg 11 cls_cnt 2 2006.173.14:04:00.92#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.14:04:00.98#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.14:04:00.98#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.14:04:00.98#ibcon#enter wrdev, iclass 31, count 2 2006.173.14:04:00.98#ibcon#first serial, iclass 31, count 2 2006.173.14:04:00.98#ibcon#enter sib2, iclass 31, count 2 2006.173.14:04:00.98#ibcon#flushed, iclass 31, count 2 2006.173.14:04:00.98#ibcon#about to write, iclass 31, count 2 2006.173.14:04:00.98#ibcon#wrote, iclass 31, count 2 2006.173.14:04:00.98#ibcon#about to read 3, iclass 31, count 2 2006.173.14:04:01.00#ibcon#read 3, iclass 31, count 2 2006.173.14:04:01.00#ibcon#about to read 4, iclass 31, count 2 2006.173.14:04:01.00#ibcon#read 4, iclass 31, count 2 2006.173.14:04:01.00#ibcon#about to read 5, iclass 31, count 2 2006.173.14:04:01.00#ibcon#read 5, iclass 31, count 2 2006.173.14:04:01.00#ibcon#about to read 6, iclass 31, count 2 2006.173.14:04:01.00#ibcon#read 6, iclass 31, count 2 2006.173.14:04:01.00#ibcon#end of sib2, iclass 31, count 2 2006.173.14:04:01.00#ibcon#*mode == 0, iclass 31, count 2 2006.173.14:04:01.00#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.14:04:01.00#ibcon#[27=AT07-04\r\n] 2006.173.14:04:01.00#ibcon#*before write, iclass 31, count 2 2006.173.14:04:01.00#ibcon#enter sib2, iclass 31, count 2 2006.173.14:04:01.00#ibcon#flushed, iclass 31, count 2 2006.173.14:04:01.00#ibcon#about to write, iclass 31, count 2 2006.173.14:04:01.00#ibcon#wrote, iclass 31, count 2 2006.173.14:04:01.00#ibcon#about to read 3, iclass 31, count 2 2006.173.14:04:01.03#ibcon#read 3, iclass 31, count 2 2006.173.14:04:01.03#ibcon#about to read 4, iclass 31, count 2 2006.173.14:04:01.03#ibcon#read 4, iclass 31, count 2 2006.173.14:04:01.03#ibcon#about to read 5, iclass 31, count 2 2006.173.14:04:01.03#ibcon#read 5, iclass 31, count 2 2006.173.14:04:01.03#ibcon#about to read 6, iclass 31, count 2 2006.173.14:04:01.03#ibcon#read 6, iclass 31, count 2 2006.173.14:04:01.03#ibcon#end of sib2, iclass 31, count 2 2006.173.14:04:01.03#ibcon#*after write, iclass 31, count 2 2006.173.14:04:01.03#ibcon#*before return 0, iclass 31, count 2 2006.173.14:04:01.03#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.14:04:01.03#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.14:04:01.03#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.14:04:01.03#ibcon#ireg 7 cls_cnt 0 2006.173.14:04:01.03#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.14:04:01.15#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.14:04:01.15#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.14:04:01.15#ibcon#enter wrdev, iclass 31, count 0 2006.173.14:04:01.15#ibcon#first serial, iclass 31, count 0 2006.173.14:04:01.15#ibcon#enter sib2, iclass 31, count 0 2006.173.14:04:01.15#ibcon#flushed, iclass 31, count 0 2006.173.14:04:01.15#ibcon#about to write, iclass 31, count 0 2006.173.14:04:01.15#ibcon#wrote, iclass 31, count 0 2006.173.14:04:01.15#ibcon#about to read 3, iclass 31, count 0 2006.173.14:04:01.17#ibcon#read 3, iclass 31, count 0 2006.173.14:04:01.17#ibcon#about to read 4, iclass 31, count 0 2006.173.14:04:01.17#ibcon#read 4, iclass 31, count 0 2006.173.14:04:01.17#ibcon#about to read 5, iclass 31, count 0 2006.173.14:04:01.17#ibcon#read 5, iclass 31, count 0 2006.173.14:04:01.17#ibcon#about to read 6, iclass 31, count 0 2006.173.14:04:01.17#ibcon#read 6, iclass 31, count 0 2006.173.14:04:01.17#ibcon#end of sib2, iclass 31, count 0 2006.173.14:04:01.17#ibcon#*mode == 0, iclass 31, count 0 2006.173.14:04:01.17#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.14:04:01.17#ibcon#[27=USB\r\n] 2006.173.14:04:01.17#ibcon#*before write, iclass 31, count 0 2006.173.14:04:01.17#ibcon#enter sib2, iclass 31, count 0 2006.173.14:04:01.17#ibcon#flushed, iclass 31, count 0 2006.173.14:04:01.17#ibcon#about to write, iclass 31, count 0 2006.173.14:04:01.17#ibcon#wrote, iclass 31, count 0 2006.173.14:04:01.17#ibcon#about to read 3, iclass 31, count 0 2006.173.14:04:01.20#ibcon#read 3, iclass 31, count 0 2006.173.14:04:01.20#ibcon#about to read 4, iclass 31, count 0 2006.173.14:04:01.20#ibcon#read 4, iclass 31, count 0 2006.173.14:04:01.20#ibcon#about to read 5, iclass 31, count 0 2006.173.14:04:01.20#ibcon#read 5, iclass 31, count 0 2006.173.14:04:01.20#ibcon#about to read 6, iclass 31, count 0 2006.173.14:04:01.20#ibcon#read 6, iclass 31, count 0 2006.173.14:04:01.20#ibcon#end of sib2, iclass 31, count 0 2006.173.14:04:01.20#ibcon#*after write, iclass 31, count 0 2006.173.14:04:01.20#ibcon#*before return 0, iclass 31, count 0 2006.173.14:04:01.20#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.14:04:01.20#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.14:04:01.20#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.14:04:01.20#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.14:04:01.20$vck44/vblo=8,744.99 2006.173.14:04:01.20#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.14:04:01.20#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.14:04:01.20#ibcon#ireg 17 cls_cnt 0 2006.173.14:04:01.20#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.14:04:01.20#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.14:04:01.20#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.14:04:01.20#ibcon#enter wrdev, iclass 33, count 0 2006.173.14:04:01.20#ibcon#first serial, iclass 33, count 0 2006.173.14:04:01.20#ibcon#enter sib2, iclass 33, count 0 2006.173.14:04:01.20#ibcon#flushed, iclass 33, count 0 2006.173.14:04:01.20#ibcon#about to write, iclass 33, count 0 2006.173.14:04:01.20#ibcon#wrote, iclass 33, count 0 2006.173.14:04:01.20#ibcon#about to read 3, iclass 33, count 0 2006.173.14:04:01.22#ibcon#read 3, iclass 33, count 0 2006.173.14:04:01.22#ibcon#about to read 4, iclass 33, count 0 2006.173.14:04:01.22#ibcon#read 4, iclass 33, count 0 2006.173.14:04:01.22#ibcon#about to read 5, iclass 33, count 0 2006.173.14:04:01.22#ibcon#read 5, iclass 33, count 0 2006.173.14:04:01.22#ibcon#about to read 6, iclass 33, count 0 2006.173.14:04:01.22#ibcon#read 6, iclass 33, count 0 2006.173.14:04:01.22#ibcon#end of sib2, iclass 33, count 0 2006.173.14:04:01.22#ibcon#*mode == 0, iclass 33, count 0 2006.173.14:04:01.22#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.14:04:01.22#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.14:04:01.22#ibcon#*before write, iclass 33, count 0 2006.173.14:04:01.22#ibcon#enter sib2, iclass 33, count 0 2006.173.14:04:01.22#ibcon#flushed, iclass 33, count 0 2006.173.14:04:01.22#ibcon#about to write, iclass 33, count 0 2006.173.14:04:01.22#ibcon#wrote, iclass 33, count 0 2006.173.14:04:01.22#ibcon#about to read 3, iclass 33, count 0 2006.173.14:04:01.26#ibcon#read 3, iclass 33, count 0 2006.173.14:04:01.26#ibcon#about to read 4, iclass 33, count 0 2006.173.14:04:01.26#ibcon#read 4, iclass 33, count 0 2006.173.14:04:01.26#ibcon#about to read 5, iclass 33, count 0 2006.173.14:04:01.26#ibcon#read 5, iclass 33, count 0 2006.173.14:04:01.26#ibcon#about to read 6, iclass 33, count 0 2006.173.14:04:01.26#ibcon#read 6, iclass 33, count 0 2006.173.14:04:01.26#ibcon#end of sib2, iclass 33, count 0 2006.173.14:04:01.26#ibcon#*after write, iclass 33, count 0 2006.173.14:04:01.26#ibcon#*before return 0, iclass 33, count 0 2006.173.14:04:01.26#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.14:04:01.26#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.14:04:01.26#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.14:04:01.26#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.14:04:01.26$vck44/vb=8,4 2006.173.14:04:01.26#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.14:04:01.26#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.14:04:01.26#ibcon#ireg 11 cls_cnt 2 2006.173.14:04:01.26#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.14:04:01.32#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.14:04:01.32#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.14:04:01.32#ibcon#enter wrdev, iclass 35, count 2 2006.173.14:04:01.32#ibcon#first serial, iclass 35, count 2 2006.173.14:04:01.32#ibcon#enter sib2, iclass 35, count 2 2006.173.14:04:01.32#ibcon#flushed, iclass 35, count 2 2006.173.14:04:01.32#ibcon#about to write, iclass 35, count 2 2006.173.14:04:01.32#ibcon#wrote, iclass 35, count 2 2006.173.14:04:01.32#ibcon#about to read 3, iclass 35, count 2 2006.173.14:04:01.34#ibcon#read 3, iclass 35, count 2 2006.173.14:04:01.34#ibcon#about to read 4, iclass 35, count 2 2006.173.14:04:01.34#ibcon#read 4, iclass 35, count 2 2006.173.14:04:01.34#ibcon#about to read 5, iclass 35, count 2 2006.173.14:04:01.34#ibcon#read 5, iclass 35, count 2 2006.173.14:04:01.34#ibcon#about to read 6, iclass 35, count 2 2006.173.14:04:01.34#ibcon#read 6, iclass 35, count 2 2006.173.14:04:01.34#ibcon#end of sib2, iclass 35, count 2 2006.173.14:04:01.34#ibcon#*mode == 0, iclass 35, count 2 2006.173.14:04:01.34#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.14:04:01.34#ibcon#[27=AT08-04\r\n] 2006.173.14:04:01.34#ibcon#*before write, iclass 35, count 2 2006.173.14:04:01.34#ibcon#enter sib2, iclass 35, count 2 2006.173.14:04:01.34#ibcon#flushed, iclass 35, count 2 2006.173.14:04:01.34#ibcon#about to write, iclass 35, count 2 2006.173.14:04:01.34#ibcon#wrote, iclass 35, count 2 2006.173.14:04:01.34#ibcon#about to read 3, iclass 35, count 2 2006.173.14:04:01.37#ibcon#read 3, iclass 35, count 2 2006.173.14:04:01.37#ibcon#about to read 4, iclass 35, count 2 2006.173.14:04:01.37#ibcon#read 4, iclass 35, count 2 2006.173.14:04:01.37#ibcon#about to read 5, iclass 35, count 2 2006.173.14:04:01.37#ibcon#read 5, iclass 35, count 2 2006.173.14:04:01.37#ibcon#about to read 6, iclass 35, count 2 2006.173.14:04:01.37#ibcon#read 6, iclass 35, count 2 2006.173.14:04:01.37#ibcon#end of sib2, iclass 35, count 2 2006.173.14:04:01.37#ibcon#*after write, iclass 35, count 2 2006.173.14:04:01.37#ibcon#*before return 0, iclass 35, count 2 2006.173.14:04:01.37#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.14:04:01.37#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.14:04:01.37#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.14:04:01.37#ibcon#ireg 7 cls_cnt 0 2006.173.14:04:01.37#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.14:04:01.49#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.14:04:01.49#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.14:04:01.49#ibcon#enter wrdev, iclass 35, count 0 2006.173.14:04:01.49#ibcon#first serial, iclass 35, count 0 2006.173.14:04:01.49#ibcon#enter sib2, iclass 35, count 0 2006.173.14:04:01.49#ibcon#flushed, iclass 35, count 0 2006.173.14:04:01.49#ibcon#about to write, iclass 35, count 0 2006.173.14:04:01.49#ibcon#wrote, iclass 35, count 0 2006.173.14:04:01.49#ibcon#about to read 3, iclass 35, count 0 2006.173.14:04:01.51#ibcon#read 3, iclass 35, count 0 2006.173.14:04:01.51#ibcon#about to read 4, iclass 35, count 0 2006.173.14:04:01.51#ibcon#read 4, iclass 35, count 0 2006.173.14:04:01.51#ibcon#about to read 5, iclass 35, count 0 2006.173.14:04:01.51#ibcon#read 5, iclass 35, count 0 2006.173.14:04:01.51#ibcon#about to read 6, iclass 35, count 0 2006.173.14:04:01.51#ibcon#read 6, iclass 35, count 0 2006.173.14:04:01.51#ibcon#end of sib2, iclass 35, count 0 2006.173.14:04:01.51#ibcon#*mode == 0, iclass 35, count 0 2006.173.14:04:01.51#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.14:04:01.51#ibcon#[27=USB\r\n] 2006.173.14:04:01.51#ibcon#*before write, iclass 35, count 0 2006.173.14:04:01.51#ibcon#enter sib2, iclass 35, count 0 2006.173.14:04:01.51#ibcon#flushed, iclass 35, count 0 2006.173.14:04:01.51#ibcon#about to write, iclass 35, count 0 2006.173.14:04:01.51#ibcon#wrote, iclass 35, count 0 2006.173.14:04:01.51#ibcon#about to read 3, iclass 35, count 0 2006.173.14:04:01.54#ibcon#read 3, iclass 35, count 0 2006.173.14:04:01.54#ibcon#about to read 4, iclass 35, count 0 2006.173.14:04:01.54#ibcon#read 4, iclass 35, count 0 2006.173.14:04:01.54#ibcon#about to read 5, iclass 35, count 0 2006.173.14:04:01.54#ibcon#read 5, iclass 35, count 0 2006.173.14:04:01.54#ibcon#about to read 6, iclass 35, count 0 2006.173.14:04:01.54#ibcon#read 6, iclass 35, count 0 2006.173.14:04:01.54#ibcon#end of sib2, iclass 35, count 0 2006.173.14:04:01.54#ibcon#*after write, iclass 35, count 0 2006.173.14:04:01.54#ibcon#*before return 0, iclass 35, count 0 2006.173.14:04:01.54#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.14:04:01.54#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.14:04:01.54#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.14:04:01.54#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.14:04:01.54$vck44/vabw=wide 2006.173.14:04:01.54#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.14:04:01.54#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.14:04:01.54#ibcon#ireg 8 cls_cnt 0 2006.173.14:04:01.54#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.14:04:01.54#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.14:04:01.54#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.14:04:01.54#ibcon#enter wrdev, iclass 37, count 0 2006.173.14:04:01.54#ibcon#first serial, iclass 37, count 0 2006.173.14:04:01.54#ibcon#enter sib2, iclass 37, count 0 2006.173.14:04:01.54#ibcon#flushed, iclass 37, count 0 2006.173.14:04:01.54#ibcon#about to write, iclass 37, count 0 2006.173.14:04:01.54#ibcon#wrote, iclass 37, count 0 2006.173.14:04:01.54#ibcon#about to read 3, iclass 37, count 0 2006.173.14:04:01.56#ibcon#read 3, iclass 37, count 0 2006.173.14:04:01.56#ibcon#about to read 4, iclass 37, count 0 2006.173.14:04:01.56#ibcon#read 4, iclass 37, count 0 2006.173.14:04:01.56#ibcon#about to read 5, iclass 37, count 0 2006.173.14:04:01.56#ibcon#read 5, iclass 37, count 0 2006.173.14:04:01.56#ibcon#about to read 6, iclass 37, count 0 2006.173.14:04:01.56#ibcon#read 6, iclass 37, count 0 2006.173.14:04:01.56#ibcon#end of sib2, iclass 37, count 0 2006.173.14:04:01.56#ibcon#*mode == 0, iclass 37, count 0 2006.173.14:04:01.56#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.14:04:01.56#ibcon#[25=BW32\r\n] 2006.173.14:04:01.56#ibcon#*before write, iclass 37, count 0 2006.173.14:04:01.56#ibcon#enter sib2, iclass 37, count 0 2006.173.14:04:01.56#ibcon#flushed, iclass 37, count 0 2006.173.14:04:01.56#ibcon#about to write, iclass 37, count 0 2006.173.14:04:01.56#ibcon#wrote, iclass 37, count 0 2006.173.14:04:01.56#ibcon#about to read 3, iclass 37, count 0 2006.173.14:04:01.59#ibcon#read 3, iclass 37, count 0 2006.173.14:04:01.59#ibcon#about to read 4, iclass 37, count 0 2006.173.14:04:01.59#ibcon#read 4, iclass 37, count 0 2006.173.14:04:01.59#ibcon#about to read 5, iclass 37, count 0 2006.173.14:04:01.59#ibcon#read 5, iclass 37, count 0 2006.173.14:04:01.59#ibcon#about to read 6, iclass 37, count 0 2006.173.14:04:01.59#ibcon#read 6, iclass 37, count 0 2006.173.14:04:01.59#ibcon#end of sib2, iclass 37, count 0 2006.173.14:04:01.59#ibcon#*after write, iclass 37, count 0 2006.173.14:04:01.59#ibcon#*before return 0, iclass 37, count 0 2006.173.14:04:01.59#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.14:04:01.59#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.14:04:01.59#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.14:04:01.59#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.14:04:01.59$vck44/vbbw=wide 2006.173.14:04:01.59#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.14:04:01.59#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.14:04:01.59#ibcon#ireg 8 cls_cnt 0 2006.173.14:04:01.59#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.14:04:01.66#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.14:04:01.66#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.14:04:01.66#ibcon#enter wrdev, iclass 39, count 0 2006.173.14:04:01.66#ibcon#first serial, iclass 39, count 0 2006.173.14:04:01.66#ibcon#enter sib2, iclass 39, count 0 2006.173.14:04:01.66#ibcon#flushed, iclass 39, count 0 2006.173.14:04:01.66#ibcon#about to write, iclass 39, count 0 2006.173.14:04:01.66#ibcon#wrote, iclass 39, count 0 2006.173.14:04:01.66#ibcon#about to read 3, iclass 39, count 0 2006.173.14:04:01.68#ibcon#read 3, iclass 39, count 0 2006.173.14:04:01.68#ibcon#about to read 4, iclass 39, count 0 2006.173.14:04:01.68#ibcon#read 4, iclass 39, count 0 2006.173.14:04:01.68#ibcon#about to read 5, iclass 39, count 0 2006.173.14:04:01.68#ibcon#read 5, iclass 39, count 0 2006.173.14:04:01.68#ibcon#about to read 6, iclass 39, count 0 2006.173.14:04:01.68#ibcon#read 6, iclass 39, count 0 2006.173.14:04:01.68#ibcon#end of sib2, iclass 39, count 0 2006.173.14:04:01.68#ibcon#*mode == 0, iclass 39, count 0 2006.173.14:04:01.68#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.14:04:01.68#ibcon#[27=BW32\r\n] 2006.173.14:04:01.68#ibcon#*before write, iclass 39, count 0 2006.173.14:04:01.68#ibcon#enter sib2, iclass 39, count 0 2006.173.14:04:01.68#ibcon#flushed, iclass 39, count 0 2006.173.14:04:01.68#ibcon#about to write, iclass 39, count 0 2006.173.14:04:01.68#ibcon#wrote, iclass 39, count 0 2006.173.14:04:01.68#ibcon#about to read 3, iclass 39, count 0 2006.173.14:04:01.71#ibcon#read 3, iclass 39, count 0 2006.173.14:04:01.71#ibcon#about to read 4, iclass 39, count 0 2006.173.14:04:01.71#ibcon#read 4, iclass 39, count 0 2006.173.14:04:01.71#ibcon#about to read 5, iclass 39, count 0 2006.173.14:04:01.71#ibcon#read 5, iclass 39, count 0 2006.173.14:04:01.71#ibcon#about to read 6, iclass 39, count 0 2006.173.14:04:01.71#ibcon#read 6, iclass 39, count 0 2006.173.14:04:01.71#ibcon#end of sib2, iclass 39, count 0 2006.173.14:04:01.71#ibcon#*after write, iclass 39, count 0 2006.173.14:04:01.71#ibcon#*before return 0, iclass 39, count 0 2006.173.14:04:01.71#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.14:04:01.71#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.14:04:01.71#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.14:04:01.71#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.14:04:01.71$setupk4/ifdk4 2006.173.14:04:01.71$ifdk4/lo= 2006.173.14:04:01.71$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.14:04:01.71$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.14:04:01.71$ifdk4/patch= 2006.173.14:04:01.71$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.14:04:01.71$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.14:04:01.71$setupk4/!*+20s 2006.173.14:04:06.47#abcon#<5=/04 0.7 1.4 21.741001003.7\r\n> 2006.173.14:04:06.49#abcon#{5=INTERFACE CLEAR} 2006.173.14:04:06.55#abcon#[5=S1D000X0/0*\r\n] 2006.173.14:04:16.21$setupk4/"tpicd 2006.173.14:04:16.21$setupk4/echo=off 2006.173.14:04:16.21$setupk4/xlog=off 2006.173.14:04:16.21:!2006.173.14:08:52 2006.173.14:04:30.14#trakl#Source acquired 2006.173.14:04:31.14#flagr#flagr/antenna,acquired 2006.173.14:08:52.00:preob 2006.173.14:08:53.14/onsource/TRACKING 2006.173.14:08:53.14:!2006.173.14:09:02 2006.173.14:09:02.00:"tape 2006.173.14:09:02.00:"st=record 2006.173.14:09:02.00:data_valid=on 2006.173.14:09:02.00:midob 2006.173.14:09:02.14/onsource/TRACKING 2006.173.14:09:02.14/wx/21.70,1003.6,100 2006.173.14:09:02.24/cable/+6.5051E-03 2006.173.14:09:03.33/va/01,07,usb,yes,48,52 2006.173.14:09:03.33/va/02,06,usb,yes,48,49 2006.173.14:09:03.33/va/03,05,usb,yes,61,63 2006.173.14:09:03.33/va/04,06,usb,yes,50,52 2006.173.14:09:03.33/va/05,04,usb,yes,39,40 2006.173.14:09:03.33/va/06,03,usb,yes,54,54 2006.173.14:09:03.33/va/07,04,usb,yes,45,46 2006.173.14:09:03.33/va/08,04,usb,yes,38,46 2006.173.14:09:03.56/valo/01,524.99,yes,locked 2006.173.14:09:03.56/valo/02,534.99,yes,locked 2006.173.14:09:03.56/valo/03,564.99,yes,locked 2006.173.14:09:03.56/valo/04,624.99,yes,locked 2006.173.14:09:03.56/valo/05,734.99,yes,locked 2006.173.14:09:03.56/valo/06,814.99,yes,locked 2006.173.14:09:03.56/valo/07,864.99,yes,locked 2006.173.14:09:03.56/valo/08,884.99,yes,locked 2006.173.14:09:04.65/vb/01,04,usb,yes,31,28 2006.173.14:09:04.65/vb/02,04,usb,yes,32,33 2006.173.14:09:04.65/vb/03,04,usb,yes,29,33 2006.173.14:09:04.65/vb/04,04,usb,yes,34,32 2006.173.14:09:04.65/vb/05,04,usb,yes,26,28 2006.173.14:09:04.65/vb/06,04,usb,yes,30,27 2006.173.14:09:04.65/vb/07,04,usb,yes,30,30 2006.173.14:09:04.65/vb/08,04,usb,yes,28,31 2006.173.14:09:04.88/vblo/01,629.99,yes,locked 2006.173.14:09:04.88/vblo/02,634.99,yes,locked 2006.173.14:09:04.88/vblo/03,649.99,yes,locked 2006.173.14:09:04.88/vblo/04,679.99,yes,locked 2006.173.14:09:04.88/vblo/05,709.99,yes,locked 2006.173.14:09:04.88/vblo/06,719.99,yes,locked 2006.173.14:09:04.88/vblo/07,734.99,yes,locked 2006.173.14:09:04.88/vblo/08,744.99,yes,locked 2006.173.14:09:05.03/vabw/8 2006.173.14:09:05.18/vbbw/8 2006.173.14:09:05.27/xfe/off,on,14.5 2006.173.14:09:05.64/ifatt/23,28,28,28 2006.173.14:09:06.08/fmout-gps/S +3.94E-07 2006.173.14:09:06.12:!2006.173.14:09:42 2006.173.14:09:42.02:data_valid=off 2006.173.14:09:42.02:"et 2006.173.14:09:42.02:!+3s 2006.173.14:09:45.04:"tape 2006.173.14:09:45.05:postob 2006.173.14:09:45.21/cable/+6.5060E-03 2006.173.14:09:45.21/wx/21.69,1003.6,100 2006.173.14:09:45.27/fmout-gps/S +3.93E-07 2006.173.14:09:45.27:scan_name=173-1410,jd0606,140 2006.173.14:09:45.27:source=1334-127,133739.78,-125724.7,2000.0,cw 2006.173.14:09:47.15#flagr#flagr/antenna,new-source 2006.173.14:09:47.15:checkk5 2006.173.14:09:47.51/chk_autoobs//k5ts1/ autoobs is running! 2006.173.14:09:47.91/chk_autoobs//k5ts2/ autoobs is running! 2006.173.14:09:48.34/chk_autoobs//k5ts3/ autoobs is running! 2006.173.14:09:48.74/chk_autoobs//k5ts4/ autoobs is running! 2006.173.14:09:49.12/chk_obsdata//k5ts1/T1731409??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.173.14:09:49.52/chk_obsdata//k5ts2/T1731409??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.173.14:09:49.94/chk_obsdata//k5ts3/T1731409??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.173.14:09:50.35/chk_obsdata//k5ts4/T1731409??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.173.14:09:51.07/k5log//k5ts1_log_newline 2006.173.14:09:51.78/k5log//k5ts2_log_newline 2006.173.14:09:52.50/k5log//k5ts3_log_newline 2006.173.14:09:53.20/k5log//k5ts4_log_newline 2006.173.14:09:53.23/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.14:09:53.23:setupk4=1 2006.173.14:09:53.23$setupk4/echo=on 2006.173.14:09:53.23$setupk4/pcalon 2006.173.14:09:53.23$pcalon/"no phase cal control is implemented here 2006.173.14:09:53.23$setupk4/"tpicd=stop 2006.173.14:09:53.23$setupk4/"rec=synch_on 2006.173.14:09:53.23$setupk4/"rec_mode=128 2006.173.14:09:53.23$setupk4/!* 2006.173.14:09:53.23$setupk4/recpk4 2006.173.14:09:53.23$recpk4/recpatch= 2006.173.14:09:53.23$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.14:09:53.23$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.14:09:53.23$setupk4/vck44 2006.173.14:09:53.23$vck44/valo=1,524.99 2006.173.14:09:53.23#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.14:09:53.23#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.14:09:53.23#ibcon#ireg 17 cls_cnt 0 2006.173.14:09:53.23#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.14:09:53.23#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.14:09:53.23#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.14:09:53.23#ibcon#enter wrdev, iclass 40, count 0 2006.173.14:09:53.23#ibcon#first serial, iclass 40, count 0 2006.173.14:09:53.23#ibcon#enter sib2, iclass 40, count 0 2006.173.14:09:53.23#ibcon#flushed, iclass 40, count 0 2006.173.14:09:53.23#ibcon#about to write, iclass 40, count 0 2006.173.14:09:53.23#ibcon#wrote, iclass 40, count 0 2006.173.14:09:53.23#ibcon#about to read 3, iclass 40, count 0 2006.173.14:09:53.24#ibcon#read 3, iclass 40, count 0 2006.173.14:09:53.24#ibcon#about to read 4, iclass 40, count 0 2006.173.14:09:53.24#ibcon#read 4, iclass 40, count 0 2006.173.14:09:53.24#ibcon#about to read 5, iclass 40, count 0 2006.173.14:09:53.24#ibcon#read 5, iclass 40, count 0 2006.173.14:09:53.24#ibcon#about to read 6, iclass 40, count 0 2006.173.14:09:53.24#ibcon#read 6, iclass 40, count 0 2006.173.14:09:53.24#ibcon#end of sib2, iclass 40, count 0 2006.173.14:09:53.24#ibcon#*mode == 0, iclass 40, count 0 2006.173.14:09:53.25#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.14:09:53.25#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.14:09:53.25#ibcon#*before write, iclass 40, count 0 2006.173.14:09:53.25#ibcon#enter sib2, iclass 40, count 0 2006.173.14:09:53.25#ibcon#flushed, iclass 40, count 0 2006.173.14:09:53.25#ibcon#about to write, iclass 40, count 0 2006.173.14:09:53.25#ibcon#wrote, iclass 40, count 0 2006.173.14:09:53.25#ibcon#about to read 3, iclass 40, count 0 2006.173.14:09:53.29#ibcon#read 3, iclass 40, count 0 2006.173.14:09:53.29#ibcon#about to read 4, iclass 40, count 0 2006.173.14:09:53.29#ibcon#read 4, iclass 40, count 0 2006.173.14:09:53.29#ibcon#about to read 5, iclass 40, count 0 2006.173.14:09:53.29#ibcon#read 5, iclass 40, count 0 2006.173.14:09:53.29#ibcon#about to read 6, iclass 40, count 0 2006.173.14:09:53.29#ibcon#read 6, iclass 40, count 0 2006.173.14:09:53.29#ibcon#end of sib2, iclass 40, count 0 2006.173.14:09:53.29#ibcon#*after write, iclass 40, count 0 2006.173.14:09:53.29#ibcon#*before return 0, iclass 40, count 0 2006.173.14:09:53.30#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.14:09:53.30#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.14:09:53.30#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.14:09:53.30#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.14:09:53.30$vck44/va=1,7 2006.173.14:09:53.30#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.14:09:53.30#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.14:09:53.30#ibcon#ireg 11 cls_cnt 2 2006.173.14:09:53.30#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.14:09:53.30#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.14:09:53.30#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.14:09:53.30#ibcon#enter wrdev, iclass 4, count 2 2006.173.14:09:53.30#ibcon#first serial, iclass 4, count 2 2006.173.14:09:53.30#ibcon#enter sib2, iclass 4, count 2 2006.173.14:09:53.30#ibcon#flushed, iclass 4, count 2 2006.173.14:09:53.30#ibcon#about to write, iclass 4, count 2 2006.173.14:09:53.30#ibcon#wrote, iclass 4, count 2 2006.173.14:09:53.30#ibcon#about to read 3, iclass 4, count 2 2006.173.14:09:53.31#ibcon#read 3, iclass 4, count 2 2006.173.14:09:53.31#ibcon#about to read 4, iclass 4, count 2 2006.173.14:09:53.31#ibcon#read 4, iclass 4, count 2 2006.173.14:09:53.31#ibcon#about to read 5, iclass 4, count 2 2006.173.14:09:53.31#ibcon#read 5, iclass 4, count 2 2006.173.14:09:53.31#ibcon#about to read 6, iclass 4, count 2 2006.173.14:09:53.31#ibcon#read 6, iclass 4, count 2 2006.173.14:09:53.31#ibcon#end of sib2, iclass 4, count 2 2006.173.14:09:53.31#ibcon#*mode == 0, iclass 4, count 2 2006.173.14:09:53.31#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.14:09:53.32#ibcon#[25=AT01-07\r\n] 2006.173.14:09:53.32#ibcon#*before write, iclass 4, count 2 2006.173.14:09:53.32#ibcon#enter sib2, iclass 4, count 2 2006.173.14:09:53.32#ibcon#flushed, iclass 4, count 2 2006.173.14:09:53.32#ibcon#about to write, iclass 4, count 2 2006.173.14:09:53.32#ibcon#wrote, iclass 4, count 2 2006.173.14:09:53.32#ibcon#about to read 3, iclass 4, count 2 2006.173.14:09:53.34#ibcon#read 3, iclass 4, count 2 2006.173.14:09:53.34#ibcon#about to read 4, iclass 4, count 2 2006.173.14:09:53.34#ibcon#read 4, iclass 4, count 2 2006.173.14:09:53.34#ibcon#about to read 5, iclass 4, count 2 2006.173.14:09:53.34#ibcon#read 5, iclass 4, count 2 2006.173.14:09:53.34#ibcon#about to read 6, iclass 4, count 2 2006.173.14:09:53.34#ibcon#read 6, iclass 4, count 2 2006.173.14:09:53.34#ibcon#end of sib2, iclass 4, count 2 2006.173.14:09:53.34#ibcon#*after write, iclass 4, count 2 2006.173.14:09:53.34#ibcon#*before return 0, iclass 4, count 2 2006.173.14:09:53.34#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.14:09:53.34#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.14:09:53.35#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.14:09:53.35#ibcon#ireg 7 cls_cnt 0 2006.173.14:09:53.35#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.14:09:53.45#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.14:09:53.45#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.14:09:53.45#ibcon#enter wrdev, iclass 4, count 0 2006.173.14:09:53.45#ibcon#first serial, iclass 4, count 0 2006.173.14:09:53.45#ibcon#enter sib2, iclass 4, count 0 2006.173.14:09:53.45#ibcon#flushed, iclass 4, count 0 2006.173.14:09:53.45#ibcon#about to write, iclass 4, count 0 2006.173.14:09:53.45#ibcon#wrote, iclass 4, count 0 2006.173.14:09:53.45#ibcon#about to read 3, iclass 4, count 0 2006.173.14:09:53.47#ibcon#read 3, iclass 4, count 0 2006.173.14:09:53.47#ibcon#about to read 4, iclass 4, count 0 2006.173.14:09:53.47#ibcon#read 4, iclass 4, count 0 2006.173.14:09:53.47#ibcon#about to read 5, iclass 4, count 0 2006.173.14:09:53.47#ibcon#read 5, iclass 4, count 0 2006.173.14:09:53.47#ibcon#about to read 6, iclass 4, count 0 2006.173.14:09:53.47#ibcon#read 6, iclass 4, count 0 2006.173.14:09:53.47#ibcon#end of sib2, iclass 4, count 0 2006.173.14:09:53.47#ibcon#*mode == 0, iclass 4, count 0 2006.173.14:09:53.48#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.14:09:53.48#ibcon#[25=USB\r\n] 2006.173.14:09:53.48#ibcon#*before write, iclass 4, count 0 2006.173.14:09:53.48#ibcon#enter sib2, iclass 4, count 0 2006.173.14:09:53.48#ibcon#flushed, iclass 4, count 0 2006.173.14:09:53.48#ibcon#about to write, iclass 4, count 0 2006.173.14:09:53.48#ibcon#wrote, iclass 4, count 0 2006.173.14:09:53.48#ibcon#about to read 3, iclass 4, count 0 2006.173.14:09:53.50#ibcon#read 3, iclass 4, count 0 2006.173.14:09:53.50#ibcon#about to read 4, iclass 4, count 0 2006.173.14:09:53.50#ibcon#read 4, iclass 4, count 0 2006.173.14:09:53.50#ibcon#about to read 5, iclass 4, count 0 2006.173.14:09:53.50#ibcon#read 5, iclass 4, count 0 2006.173.14:09:53.50#ibcon#about to read 6, iclass 4, count 0 2006.173.14:09:53.50#ibcon#read 6, iclass 4, count 0 2006.173.14:09:53.50#ibcon#end of sib2, iclass 4, count 0 2006.173.14:09:53.50#ibcon#*after write, iclass 4, count 0 2006.173.14:09:53.50#ibcon#*before return 0, iclass 4, count 0 2006.173.14:09:53.51#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.14:09:53.51#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.14:09:53.51#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.14:09:53.51#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.14:09:53.51$vck44/valo=2,534.99 2006.173.14:09:53.51#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.14:09:53.51#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.14:09:53.51#ibcon#ireg 17 cls_cnt 0 2006.173.14:09:53.51#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.14:09:53.51#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.14:09:53.51#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.14:09:53.51#ibcon#enter wrdev, iclass 6, count 0 2006.173.14:09:53.51#ibcon#first serial, iclass 6, count 0 2006.173.14:09:53.51#ibcon#enter sib2, iclass 6, count 0 2006.173.14:09:53.51#ibcon#flushed, iclass 6, count 0 2006.173.14:09:53.51#ibcon#about to write, iclass 6, count 0 2006.173.14:09:53.51#ibcon#wrote, iclass 6, count 0 2006.173.14:09:53.51#ibcon#about to read 3, iclass 6, count 0 2006.173.14:09:53.52#ibcon#read 3, iclass 6, count 0 2006.173.14:09:53.52#ibcon#about to read 4, iclass 6, count 0 2006.173.14:09:53.52#ibcon#read 4, iclass 6, count 0 2006.173.14:09:53.52#ibcon#about to read 5, iclass 6, count 0 2006.173.14:09:53.52#ibcon#read 5, iclass 6, count 0 2006.173.14:09:53.52#ibcon#about to read 6, iclass 6, count 0 2006.173.14:09:53.52#ibcon#read 6, iclass 6, count 0 2006.173.14:09:53.52#ibcon#end of sib2, iclass 6, count 0 2006.173.14:09:53.53#ibcon#*mode == 0, iclass 6, count 0 2006.173.14:09:53.53#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.14:09:53.53#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.14:09:53.53#ibcon#*before write, iclass 6, count 0 2006.173.14:09:53.53#ibcon#enter sib2, iclass 6, count 0 2006.173.14:09:53.53#ibcon#flushed, iclass 6, count 0 2006.173.14:09:53.53#ibcon#about to write, iclass 6, count 0 2006.173.14:09:53.53#ibcon#wrote, iclass 6, count 0 2006.173.14:09:53.53#ibcon#about to read 3, iclass 6, count 0 2006.173.14:09:53.56#ibcon#read 3, iclass 6, count 0 2006.173.14:09:53.56#ibcon#about to read 4, iclass 6, count 0 2006.173.14:09:53.56#ibcon#read 4, iclass 6, count 0 2006.173.14:09:53.56#ibcon#about to read 5, iclass 6, count 0 2006.173.14:09:53.56#ibcon#read 5, iclass 6, count 0 2006.173.14:09:53.56#ibcon#about to read 6, iclass 6, count 0 2006.173.14:09:53.56#ibcon#read 6, iclass 6, count 0 2006.173.14:09:53.57#ibcon#end of sib2, iclass 6, count 0 2006.173.14:09:53.57#ibcon#*after write, iclass 6, count 0 2006.173.14:09:53.57#ibcon#*before return 0, iclass 6, count 0 2006.173.14:09:53.57#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.14:09:53.57#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.14:09:53.57#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.14:09:53.57#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.14:09:53.57$vck44/va=2,6 2006.173.14:09:53.57#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.14:09:53.57#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.14:09:53.57#ibcon#ireg 11 cls_cnt 2 2006.173.14:09:53.57#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.14:09:53.62#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.14:09:53.62#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.14:09:53.62#ibcon#enter wrdev, iclass 10, count 2 2006.173.14:09:53.62#ibcon#first serial, iclass 10, count 2 2006.173.14:09:53.62#ibcon#enter sib2, iclass 10, count 2 2006.173.14:09:53.62#ibcon#flushed, iclass 10, count 2 2006.173.14:09:53.62#ibcon#about to write, iclass 10, count 2 2006.173.14:09:53.62#ibcon#wrote, iclass 10, count 2 2006.173.14:09:53.62#ibcon#about to read 3, iclass 10, count 2 2006.173.14:09:53.64#ibcon#read 3, iclass 10, count 2 2006.173.14:09:53.64#ibcon#about to read 4, iclass 10, count 2 2006.173.14:09:53.64#ibcon#read 4, iclass 10, count 2 2006.173.14:09:53.64#ibcon#about to read 5, iclass 10, count 2 2006.173.14:09:53.64#ibcon#read 5, iclass 10, count 2 2006.173.14:09:53.64#ibcon#about to read 6, iclass 10, count 2 2006.173.14:09:53.64#ibcon#read 6, iclass 10, count 2 2006.173.14:09:53.64#ibcon#end of sib2, iclass 10, count 2 2006.173.14:09:53.64#ibcon#*mode == 0, iclass 10, count 2 2006.173.14:09:53.64#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.14:09:53.64#ibcon#[25=AT02-06\r\n] 2006.173.14:09:53.64#ibcon#*before write, iclass 10, count 2 2006.173.14:09:53.64#ibcon#enter sib2, iclass 10, count 2 2006.173.14:09:53.65#ibcon#flushed, iclass 10, count 2 2006.173.14:09:53.65#ibcon#about to write, iclass 10, count 2 2006.173.14:09:53.65#ibcon#wrote, iclass 10, count 2 2006.173.14:09:53.65#ibcon#about to read 3, iclass 10, count 2 2006.173.14:09:53.67#ibcon#read 3, iclass 10, count 2 2006.173.14:09:53.67#ibcon#about to read 4, iclass 10, count 2 2006.173.14:09:53.67#ibcon#read 4, iclass 10, count 2 2006.173.14:09:53.67#ibcon#about to read 5, iclass 10, count 2 2006.173.14:09:53.67#ibcon#read 5, iclass 10, count 2 2006.173.14:09:53.67#ibcon#about to read 6, iclass 10, count 2 2006.173.14:09:53.67#ibcon#read 6, iclass 10, count 2 2006.173.14:09:53.67#ibcon#end of sib2, iclass 10, count 2 2006.173.14:09:53.67#ibcon#*after write, iclass 10, count 2 2006.173.14:09:53.67#ibcon#*before return 0, iclass 10, count 2 2006.173.14:09:53.67#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.14:09:53.67#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.14:09:53.67#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.14:09:53.68#ibcon#ireg 7 cls_cnt 0 2006.173.14:09:53.68#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.14:09:53.78#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.14:09:53.78#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.14:09:53.78#ibcon#enter wrdev, iclass 10, count 0 2006.173.14:09:53.78#ibcon#first serial, iclass 10, count 0 2006.173.14:09:53.78#ibcon#enter sib2, iclass 10, count 0 2006.173.14:09:53.78#ibcon#flushed, iclass 10, count 0 2006.173.14:09:53.78#ibcon#about to write, iclass 10, count 0 2006.173.14:09:53.78#ibcon#wrote, iclass 10, count 0 2006.173.14:09:53.78#ibcon#about to read 3, iclass 10, count 0 2006.173.14:09:53.80#ibcon#read 3, iclass 10, count 0 2006.173.14:09:53.80#ibcon#about to read 4, iclass 10, count 0 2006.173.14:09:53.80#ibcon#read 4, iclass 10, count 0 2006.173.14:09:53.80#ibcon#about to read 5, iclass 10, count 0 2006.173.14:09:53.80#ibcon#read 5, iclass 10, count 0 2006.173.14:09:53.80#ibcon#about to read 6, iclass 10, count 0 2006.173.14:09:53.80#ibcon#read 6, iclass 10, count 0 2006.173.14:09:53.80#ibcon#end of sib2, iclass 10, count 0 2006.173.14:09:53.80#ibcon#*mode == 0, iclass 10, count 0 2006.173.14:09:53.81#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.14:09:53.81#ibcon#[25=USB\r\n] 2006.173.14:09:53.81#ibcon#*before write, iclass 10, count 0 2006.173.14:09:53.81#ibcon#enter sib2, iclass 10, count 0 2006.173.14:09:53.81#ibcon#flushed, iclass 10, count 0 2006.173.14:09:53.81#ibcon#about to write, iclass 10, count 0 2006.173.14:09:53.81#ibcon#wrote, iclass 10, count 0 2006.173.14:09:53.81#ibcon#about to read 3, iclass 10, count 0 2006.173.14:09:53.83#ibcon#read 3, iclass 10, count 0 2006.173.14:09:53.83#ibcon#about to read 4, iclass 10, count 0 2006.173.14:09:53.83#ibcon#read 4, iclass 10, count 0 2006.173.14:09:53.83#ibcon#about to read 5, iclass 10, count 0 2006.173.14:09:53.83#ibcon#read 5, iclass 10, count 0 2006.173.14:09:53.83#ibcon#about to read 6, iclass 10, count 0 2006.173.14:09:53.83#ibcon#read 6, iclass 10, count 0 2006.173.14:09:53.83#ibcon#end of sib2, iclass 10, count 0 2006.173.14:09:53.83#ibcon#*after write, iclass 10, count 0 2006.173.14:09:53.83#ibcon#*before return 0, iclass 10, count 0 2006.173.14:09:53.83#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.14:09:53.83#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.14:09:53.83#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.14:09:53.84#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.14:09:53.84$vck44/valo=3,564.99 2006.173.14:09:53.84#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.14:09:53.84#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.14:09:53.84#ibcon#ireg 17 cls_cnt 0 2006.173.14:09:53.84#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.14:09:53.84#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.14:09:53.84#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.14:09:53.84#ibcon#enter wrdev, iclass 12, count 0 2006.173.14:09:53.84#ibcon#first serial, iclass 12, count 0 2006.173.14:09:53.84#ibcon#enter sib2, iclass 12, count 0 2006.173.14:09:53.84#ibcon#flushed, iclass 12, count 0 2006.173.14:09:53.84#ibcon#about to write, iclass 12, count 0 2006.173.14:09:53.84#ibcon#wrote, iclass 12, count 0 2006.173.14:09:53.84#ibcon#about to read 3, iclass 12, count 0 2006.173.14:09:53.85#ibcon#read 3, iclass 12, count 0 2006.173.14:09:53.85#ibcon#about to read 4, iclass 12, count 0 2006.173.14:09:53.85#ibcon#read 4, iclass 12, count 0 2006.173.14:09:53.85#ibcon#about to read 5, iclass 12, count 0 2006.173.14:09:53.85#ibcon#read 5, iclass 12, count 0 2006.173.14:09:53.85#ibcon#about to read 6, iclass 12, count 0 2006.173.14:09:53.85#ibcon#read 6, iclass 12, count 0 2006.173.14:09:53.85#ibcon#end of sib2, iclass 12, count 0 2006.173.14:09:53.85#ibcon#*mode == 0, iclass 12, count 0 2006.173.14:09:53.85#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.14:09:53.86#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.14:09:53.86#ibcon#*before write, iclass 12, count 0 2006.173.14:09:53.86#ibcon#enter sib2, iclass 12, count 0 2006.173.14:09:53.86#ibcon#flushed, iclass 12, count 0 2006.173.14:09:53.86#ibcon#about to write, iclass 12, count 0 2006.173.14:09:53.86#ibcon#wrote, iclass 12, count 0 2006.173.14:09:53.86#ibcon#about to read 3, iclass 12, count 0 2006.173.14:09:53.89#ibcon#read 3, iclass 12, count 0 2006.173.14:09:53.89#ibcon#about to read 4, iclass 12, count 0 2006.173.14:09:53.89#ibcon#read 4, iclass 12, count 0 2006.173.14:09:53.89#ibcon#about to read 5, iclass 12, count 0 2006.173.14:09:53.89#ibcon#read 5, iclass 12, count 0 2006.173.14:09:53.89#ibcon#about to read 6, iclass 12, count 0 2006.173.14:09:53.89#ibcon#read 6, iclass 12, count 0 2006.173.14:09:53.89#ibcon#end of sib2, iclass 12, count 0 2006.173.14:09:53.89#ibcon#*after write, iclass 12, count 0 2006.173.14:09:53.89#ibcon#*before return 0, iclass 12, count 0 2006.173.14:09:53.89#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.14:09:53.90#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.14:09:53.90#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.14:09:53.90#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.14:09:53.90$vck44/va=3,5 2006.173.14:09:53.90#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.14:09:53.90#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.14:09:53.90#ibcon#ireg 11 cls_cnt 2 2006.173.14:09:53.90#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.14:09:53.94#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.14:09:53.94#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.14:09:53.94#ibcon#enter wrdev, iclass 14, count 2 2006.173.14:09:53.94#ibcon#first serial, iclass 14, count 2 2006.173.14:09:53.94#ibcon#enter sib2, iclass 14, count 2 2006.173.14:09:53.94#ibcon#flushed, iclass 14, count 2 2006.173.14:09:53.94#ibcon#about to write, iclass 14, count 2 2006.173.14:09:53.94#ibcon#wrote, iclass 14, count 2 2006.173.14:09:53.94#ibcon#about to read 3, iclass 14, count 2 2006.173.14:09:53.96#ibcon#read 3, iclass 14, count 2 2006.173.14:09:53.96#ibcon#about to read 4, iclass 14, count 2 2006.173.14:09:53.96#ibcon#read 4, iclass 14, count 2 2006.173.14:09:53.96#ibcon#about to read 5, iclass 14, count 2 2006.173.14:09:53.96#ibcon#read 5, iclass 14, count 2 2006.173.14:09:53.96#ibcon#about to read 6, iclass 14, count 2 2006.173.14:09:53.96#ibcon#read 6, iclass 14, count 2 2006.173.14:09:53.96#ibcon#end of sib2, iclass 14, count 2 2006.173.14:09:53.96#ibcon#*mode == 0, iclass 14, count 2 2006.173.14:09:53.96#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.14:09:53.96#ibcon#[25=AT03-05\r\n] 2006.173.14:09:53.96#ibcon#*before write, iclass 14, count 2 2006.173.14:09:53.96#ibcon#enter sib2, iclass 14, count 2 2006.173.14:09:53.96#ibcon#flushed, iclass 14, count 2 2006.173.14:09:53.96#ibcon#about to write, iclass 14, count 2 2006.173.14:09:53.97#ibcon#wrote, iclass 14, count 2 2006.173.14:09:53.97#ibcon#about to read 3, iclass 14, count 2 2006.173.14:09:53.99#ibcon#read 3, iclass 14, count 2 2006.173.14:09:53.99#ibcon#about to read 4, iclass 14, count 2 2006.173.14:09:53.99#ibcon#read 4, iclass 14, count 2 2006.173.14:09:53.99#ibcon#about to read 5, iclass 14, count 2 2006.173.14:09:53.99#ibcon#read 5, iclass 14, count 2 2006.173.14:09:53.99#ibcon#about to read 6, iclass 14, count 2 2006.173.14:09:53.99#ibcon#read 6, iclass 14, count 2 2006.173.14:09:53.99#ibcon#end of sib2, iclass 14, count 2 2006.173.14:09:53.99#ibcon#*after write, iclass 14, count 2 2006.173.14:09:53.99#ibcon#*before return 0, iclass 14, count 2 2006.173.14:09:53.99#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.14:09:53.99#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.14:09:53.99#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.14:09:54.00#ibcon#ireg 7 cls_cnt 0 2006.173.14:09:54.00#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.14:09:54.10#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.14:09:54.10#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.14:09:54.10#ibcon#enter wrdev, iclass 14, count 0 2006.173.14:09:54.10#ibcon#first serial, iclass 14, count 0 2006.173.14:09:54.10#ibcon#enter sib2, iclass 14, count 0 2006.173.14:09:54.10#ibcon#flushed, iclass 14, count 0 2006.173.14:09:54.10#ibcon#about to write, iclass 14, count 0 2006.173.14:09:54.10#ibcon#wrote, iclass 14, count 0 2006.173.14:09:54.10#ibcon#about to read 3, iclass 14, count 0 2006.173.14:09:54.12#ibcon#read 3, iclass 14, count 0 2006.173.14:09:54.12#ibcon#about to read 4, iclass 14, count 0 2006.173.14:09:54.12#ibcon#read 4, iclass 14, count 0 2006.173.14:09:54.12#ibcon#about to read 5, iclass 14, count 0 2006.173.14:09:54.12#ibcon#read 5, iclass 14, count 0 2006.173.14:09:54.12#ibcon#about to read 6, iclass 14, count 0 2006.173.14:09:54.12#ibcon#read 6, iclass 14, count 0 2006.173.14:09:54.12#ibcon#end of sib2, iclass 14, count 0 2006.173.14:09:54.12#ibcon#*mode == 0, iclass 14, count 0 2006.173.14:09:54.12#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.14:09:54.12#ibcon#[25=USB\r\n] 2006.173.14:09:54.12#ibcon#*before write, iclass 14, count 0 2006.173.14:09:54.12#ibcon#enter sib2, iclass 14, count 0 2006.173.14:09:54.12#ibcon#flushed, iclass 14, count 0 2006.173.14:09:54.12#ibcon#about to write, iclass 14, count 0 2006.173.14:09:54.13#ibcon#wrote, iclass 14, count 0 2006.173.14:09:54.13#ibcon#about to read 3, iclass 14, count 0 2006.173.14:09:54.15#ibcon#read 3, iclass 14, count 0 2006.173.14:09:54.15#ibcon#about to read 4, iclass 14, count 0 2006.173.14:09:54.15#ibcon#read 4, iclass 14, count 0 2006.173.14:09:54.15#ibcon#about to read 5, iclass 14, count 0 2006.173.14:09:54.15#ibcon#read 5, iclass 14, count 0 2006.173.14:09:54.15#ibcon#about to read 6, iclass 14, count 0 2006.173.14:09:54.15#ibcon#read 6, iclass 14, count 0 2006.173.14:09:54.15#ibcon#end of sib2, iclass 14, count 0 2006.173.14:09:54.15#ibcon#*after write, iclass 14, count 0 2006.173.14:09:54.15#ibcon#*before return 0, iclass 14, count 0 2006.173.14:09:54.15#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.14:09:54.16#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.14:09:54.16#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.14:09:54.16#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.14:09:54.16$vck44/valo=4,624.99 2006.173.14:09:54.16#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.14:09:54.16#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.14:09:54.16#ibcon#ireg 17 cls_cnt 0 2006.173.14:09:54.16#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.14:09:54.16#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.14:09:54.16#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.14:09:54.16#ibcon#enter wrdev, iclass 16, count 0 2006.173.14:09:54.16#ibcon#first serial, iclass 16, count 0 2006.173.14:09:54.16#ibcon#enter sib2, iclass 16, count 0 2006.173.14:09:54.16#ibcon#flushed, iclass 16, count 0 2006.173.14:09:54.16#ibcon#about to write, iclass 16, count 0 2006.173.14:09:54.16#ibcon#wrote, iclass 16, count 0 2006.173.14:09:54.16#ibcon#about to read 3, iclass 16, count 0 2006.173.14:09:54.17#ibcon#read 3, iclass 16, count 0 2006.173.14:09:54.17#ibcon#about to read 4, iclass 16, count 0 2006.173.14:09:54.17#ibcon#read 4, iclass 16, count 0 2006.173.14:09:54.17#ibcon#about to read 5, iclass 16, count 0 2006.173.14:09:54.17#ibcon#read 5, iclass 16, count 0 2006.173.14:09:54.17#ibcon#about to read 6, iclass 16, count 0 2006.173.14:09:54.17#ibcon#read 6, iclass 16, count 0 2006.173.14:09:54.17#ibcon#end of sib2, iclass 16, count 0 2006.173.14:09:54.17#ibcon#*mode == 0, iclass 16, count 0 2006.173.14:09:54.17#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.14:09:54.17#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.14:09:54.17#ibcon#*before write, iclass 16, count 0 2006.173.14:09:54.17#ibcon#enter sib2, iclass 16, count 0 2006.173.14:09:54.17#ibcon#flushed, iclass 16, count 0 2006.173.14:09:54.18#ibcon#about to write, iclass 16, count 0 2006.173.14:09:54.18#ibcon#wrote, iclass 16, count 0 2006.173.14:09:54.18#ibcon#about to read 3, iclass 16, count 0 2006.173.14:09:54.21#ibcon#read 3, iclass 16, count 0 2006.173.14:09:54.21#ibcon#about to read 4, iclass 16, count 0 2006.173.14:09:54.21#ibcon#read 4, iclass 16, count 0 2006.173.14:09:54.21#ibcon#about to read 5, iclass 16, count 0 2006.173.14:09:54.21#ibcon#read 5, iclass 16, count 0 2006.173.14:09:54.21#ibcon#about to read 6, iclass 16, count 0 2006.173.14:09:54.21#ibcon#read 6, iclass 16, count 0 2006.173.14:09:54.21#ibcon#end of sib2, iclass 16, count 0 2006.173.14:09:54.21#ibcon#*after write, iclass 16, count 0 2006.173.14:09:54.22#ibcon#*before return 0, iclass 16, count 0 2006.173.14:09:54.22#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.14:09:54.22#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.14:09:54.22#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.14:09:54.22#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.14:09:54.22$vck44/va=4,6 2006.173.14:09:54.22#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.14:09:54.22#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.14:09:54.22#ibcon#ireg 11 cls_cnt 2 2006.173.14:09:54.22#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.14:09:54.27#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.14:09:54.27#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.14:09:54.27#ibcon#enter wrdev, iclass 18, count 2 2006.173.14:09:54.27#ibcon#first serial, iclass 18, count 2 2006.173.14:09:54.27#ibcon#enter sib2, iclass 18, count 2 2006.173.14:09:54.27#ibcon#flushed, iclass 18, count 2 2006.173.14:09:54.27#ibcon#about to write, iclass 18, count 2 2006.173.14:09:54.27#ibcon#wrote, iclass 18, count 2 2006.173.14:09:54.27#ibcon#about to read 3, iclass 18, count 2 2006.173.14:09:54.29#ibcon#read 3, iclass 18, count 2 2006.173.14:09:54.29#ibcon#about to read 4, iclass 18, count 2 2006.173.14:09:54.29#ibcon#read 4, iclass 18, count 2 2006.173.14:09:54.29#ibcon#about to read 5, iclass 18, count 2 2006.173.14:09:54.29#ibcon#read 5, iclass 18, count 2 2006.173.14:09:54.29#ibcon#about to read 6, iclass 18, count 2 2006.173.14:09:54.29#ibcon#read 6, iclass 18, count 2 2006.173.14:09:54.29#ibcon#end of sib2, iclass 18, count 2 2006.173.14:09:54.29#ibcon#*mode == 0, iclass 18, count 2 2006.173.14:09:54.30#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.14:09:54.30#ibcon#[25=AT04-06\r\n] 2006.173.14:09:54.30#ibcon#*before write, iclass 18, count 2 2006.173.14:09:54.30#ibcon#enter sib2, iclass 18, count 2 2006.173.14:09:54.30#ibcon#flushed, iclass 18, count 2 2006.173.14:09:54.30#ibcon#about to write, iclass 18, count 2 2006.173.14:09:54.30#ibcon#wrote, iclass 18, count 2 2006.173.14:09:54.30#ibcon#about to read 3, iclass 18, count 2 2006.173.14:09:54.32#ibcon#read 3, iclass 18, count 2 2006.173.14:09:54.32#ibcon#about to read 4, iclass 18, count 2 2006.173.14:09:54.32#ibcon#read 4, iclass 18, count 2 2006.173.14:09:54.32#ibcon#about to read 5, iclass 18, count 2 2006.173.14:09:54.32#ibcon#read 5, iclass 18, count 2 2006.173.14:09:54.32#ibcon#about to read 6, iclass 18, count 2 2006.173.14:09:54.32#ibcon#read 6, iclass 18, count 2 2006.173.14:09:54.32#ibcon#end of sib2, iclass 18, count 2 2006.173.14:09:54.32#ibcon#*after write, iclass 18, count 2 2006.173.14:09:54.32#ibcon#*before return 0, iclass 18, count 2 2006.173.14:09:54.33#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.14:09:54.33#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.14:09:54.33#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.14:09:54.33#ibcon#ireg 7 cls_cnt 0 2006.173.14:09:54.33#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.14:09:54.44#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.14:09:54.44#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.14:09:54.44#ibcon#enter wrdev, iclass 18, count 0 2006.173.14:09:54.44#ibcon#first serial, iclass 18, count 0 2006.173.14:09:54.44#ibcon#enter sib2, iclass 18, count 0 2006.173.14:09:54.44#ibcon#flushed, iclass 18, count 0 2006.173.14:09:54.44#ibcon#about to write, iclass 18, count 0 2006.173.14:09:54.44#ibcon#wrote, iclass 18, count 0 2006.173.14:09:54.44#ibcon#about to read 3, iclass 18, count 0 2006.173.14:09:54.46#ibcon#read 3, iclass 18, count 0 2006.173.14:09:54.46#ibcon#about to read 4, iclass 18, count 0 2006.173.14:09:54.46#ibcon#read 4, iclass 18, count 0 2006.173.14:09:54.46#ibcon#about to read 5, iclass 18, count 0 2006.173.14:09:54.46#ibcon#read 5, iclass 18, count 0 2006.173.14:09:54.46#ibcon#about to read 6, iclass 18, count 0 2006.173.14:09:54.46#ibcon#read 6, iclass 18, count 0 2006.173.14:09:54.46#ibcon#end of sib2, iclass 18, count 0 2006.173.14:09:54.46#ibcon#*mode == 0, iclass 18, count 0 2006.173.14:09:54.46#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.14:09:54.47#ibcon#[25=USB\r\n] 2006.173.14:09:54.47#ibcon#*before write, iclass 18, count 0 2006.173.14:09:54.47#ibcon#enter sib2, iclass 18, count 0 2006.173.14:09:54.47#ibcon#flushed, iclass 18, count 0 2006.173.14:09:54.47#ibcon#about to write, iclass 18, count 0 2006.173.14:09:54.47#ibcon#wrote, iclass 18, count 0 2006.173.14:09:54.47#ibcon#about to read 3, iclass 18, count 0 2006.173.14:09:54.49#ibcon#read 3, iclass 18, count 0 2006.173.14:09:54.49#ibcon#about to read 4, iclass 18, count 0 2006.173.14:09:54.49#ibcon#read 4, iclass 18, count 0 2006.173.14:09:54.49#ibcon#about to read 5, iclass 18, count 0 2006.173.14:09:54.49#ibcon#read 5, iclass 18, count 0 2006.173.14:09:54.49#ibcon#about to read 6, iclass 18, count 0 2006.173.14:09:54.49#ibcon#read 6, iclass 18, count 0 2006.173.14:09:54.49#ibcon#end of sib2, iclass 18, count 0 2006.173.14:09:54.49#ibcon#*after write, iclass 18, count 0 2006.173.14:09:54.49#ibcon#*before return 0, iclass 18, count 0 2006.173.14:09:54.50#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.14:09:54.50#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.14:09:54.50#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.14:09:54.50#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.14:09:54.50$vck44/valo=5,734.99 2006.173.14:09:54.50#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.14:09:54.50#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.14:09:54.50#ibcon#ireg 17 cls_cnt 0 2006.173.14:09:54.50#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.14:09:54.50#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.14:09:54.50#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.14:09:54.50#ibcon#enter wrdev, iclass 20, count 0 2006.173.14:09:54.50#ibcon#first serial, iclass 20, count 0 2006.173.14:09:54.50#ibcon#enter sib2, iclass 20, count 0 2006.173.14:09:54.50#ibcon#flushed, iclass 20, count 0 2006.173.14:09:54.50#ibcon#about to write, iclass 20, count 0 2006.173.14:09:54.50#ibcon#wrote, iclass 20, count 0 2006.173.14:09:54.50#ibcon#about to read 3, iclass 20, count 0 2006.173.14:09:54.51#ibcon#read 3, iclass 20, count 0 2006.173.14:09:54.51#ibcon#about to read 4, iclass 20, count 0 2006.173.14:09:54.51#ibcon#read 4, iclass 20, count 0 2006.173.14:09:54.51#ibcon#about to read 5, iclass 20, count 0 2006.173.14:09:54.51#ibcon#read 5, iclass 20, count 0 2006.173.14:09:54.51#ibcon#about to read 6, iclass 20, count 0 2006.173.14:09:54.51#ibcon#read 6, iclass 20, count 0 2006.173.14:09:54.51#ibcon#end of sib2, iclass 20, count 0 2006.173.14:09:54.51#ibcon#*mode == 0, iclass 20, count 0 2006.173.14:09:54.51#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.14:09:54.52#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.14:09:54.52#ibcon#*before write, iclass 20, count 0 2006.173.14:09:54.52#ibcon#enter sib2, iclass 20, count 0 2006.173.14:09:54.52#ibcon#flushed, iclass 20, count 0 2006.173.14:09:54.52#ibcon#about to write, iclass 20, count 0 2006.173.14:09:54.52#ibcon#wrote, iclass 20, count 0 2006.173.14:09:54.52#ibcon#about to read 3, iclass 20, count 0 2006.173.14:09:54.55#ibcon#read 3, iclass 20, count 0 2006.173.14:09:54.55#ibcon#about to read 4, iclass 20, count 0 2006.173.14:09:54.55#ibcon#read 4, iclass 20, count 0 2006.173.14:09:54.55#ibcon#about to read 5, iclass 20, count 0 2006.173.14:09:54.55#ibcon#read 5, iclass 20, count 0 2006.173.14:09:54.55#ibcon#about to read 6, iclass 20, count 0 2006.173.14:09:54.55#ibcon#read 6, iclass 20, count 0 2006.173.14:09:54.55#ibcon#end of sib2, iclass 20, count 0 2006.173.14:09:54.55#ibcon#*after write, iclass 20, count 0 2006.173.14:09:54.55#ibcon#*before return 0, iclass 20, count 0 2006.173.14:09:54.56#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.14:09:54.56#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.14:09:54.56#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.14:09:54.56#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.14:09:54.56$vck44/va=5,4 2006.173.14:09:54.56#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.14:09:54.56#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.14:09:54.56#ibcon#ireg 11 cls_cnt 2 2006.173.14:09:54.56#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.14:09:54.61#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.14:09:54.61#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.14:09:54.61#ibcon#enter wrdev, iclass 22, count 2 2006.173.14:09:54.61#ibcon#first serial, iclass 22, count 2 2006.173.14:09:54.61#ibcon#enter sib2, iclass 22, count 2 2006.173.14:09:54.61#ibcon#flushed, iclass 22, count 2 2006.173.14:09:54.61#ibcon#about to write, iclass 22, count 2 2006.173.14:09:54.61#ibcon#wrote, iclass 22, count 2 2006.173.14:09:54.61#ibcon#about to read 3, iclass 22, count 2 2006.173.14:09:54.63#ibcon#read 3, iclass 22, count 2 2006.173.14:09:54.63#ibcon#about to read 4, iclass 22, count 2 2006.173.14:09:54.63#ibcon#read 4, iclass 22, count 2 2006.173.14:09:54.63#ibcon#about to read 5, iclass 22, count 2 2006.173.14:09:54.63#ibcon#read 5, iclass 22, count 2 2006.173.14:09:54.64#ibcon#about to read 6, iclass 22, count 2 2006.173.14:09:54.64#ibcon#read 6, iclass 22, count 2 2006.173.14:09:54.64#ibcon#end of sib2, iclass 22, count 2 2006.173.14:09:54.64#ibcon#*mode == 0, iclass 22, count 2 2006.173.14:09:54.64#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.14:09:54.64#ibcon#[25=AT05-04\r\n] 2006.173.14:09:54.64#ibcon#*before write, iclass 22, count 2 2006.173.14:09:54.64#ibcon#enter sib2, iclass 22, count 2 2006.173.14:09:54.64#ibcon#flushed, iclass 22, count 2 2006.173.14:09:54.64#ibcon#about to write, iclass 22, count 2 2006.173.14:09:54.64#ibcon#wrote, iclass 22, count 2 2006.173.14:09:54.64#ibcon#about to read 3, iclass 22, count 2 2006.173.14:09:54.66#ibcon#read 3, iclass 22, count 2 2006.173.14:09:54.66#ibcon#about to read 4, iclass 22, count 2 2006.173.14:09:54.66#ibcon#read 4, iclass 22, count 2 2006.173.14:09:54.66#ibcon#about to read 5, iclass 22, count 2 2006.173.14:09:54.66#ibcon#read 5, iclass 22, count 2 2006.173.14:09:54.66#ibcon#about to read 6, iclass 22, count 2 2006.173.14:09:54.66#ibcon#read 6, iclass 22, count 2 2006.173.14:09:54.66#ibcon#end of sib2, iclass 22, count 2 2006.173.14:09:54.66#ibcon#*after write, iclass 22, count 2 2006.173.14:09:54.66#ibcon#*before return 0, iclass 22, count 2 2006.173.14:09:54.67#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.14:09:54.67#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.14:09:54.67#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.14:09:54.67#ibcon#ireg 7 cls_cnt 0 2006.173.14:09:54.67#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.14:09:54.78#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.14:09:54.78#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.14:09:54.78#ibcon#enter wrdev, iclass 22, count 0 2006.173.14:09:54.78#ibcon#first serial, iclass 22, count 0 2006.173.14:09:54.78#ibcon#enter sib2, iclass 22, count 0 2006.173.14:09:54.78#ibcon#flushed, iclass 22, count 0 2006.173.14:09:54.78#ibcon#about to write, iclass 22, count 0 2006.173.14:09:54.78#ibcon#wrote, iclass 22, count 0 2006.173.14:09:54.78#ibcon#about to read 3, iclass 22, count 0 2006.173.14:09:54.80#ibcon#read 3, iclass 22, count 0 2006.173.14:09:54.80#ibcon#about to read 4, iclass 22, count 0 2006.173.14:09:54.80#ibcon#read 4, iclass 22, count 0 2006.173.14:09:54.80#ibcon#about to read 5, iclass 22, count 0 2006.173.14:09:54.80#ibcon#read 5, iclass 22, count 0 2006.173.14:09:54.80#ibcon#about to read 6, iclass 22, count 0 2006.173.14:09:54.80#ibcon#read 6, iclass 22, count 0 2006.173.14:09:54.80#ibcon#end of sib2, iclass 22, count 0 2006.173.14:09:54.81#ibcon#*mode == 0, iclass 22, count 0 2006.173.14:09:54.81#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.14:09:54.81#ibcon#[25=USB\r\n] 2006.173.14:09:54.81#ibcon#*before write, iclass 22, count 0 2006.173.14:09:54.81#ibcon#enter sib2, iclass 22, count 0 2006.173.14:09:54.81#ibcon#flushed, iclass 22, count 0 2006.173.14:09:54.81#ibcon#about to write, iclass 22, count 0 2006.173.14:09:54.81#ibcon#wrote, iclass 22, count 0 2006.173.14:09:54.81#ibcon#about to read 3, iclass 22, count 0 2006.173.14:09:54.83#ibcon#read 3, iclass 22, count 0 2006.173.14:09:54.83#ibcon#about to read 4, iclass 22, count 0 2006.173.14:09:54.83#ibcon#read 4, iclass 22, count 0 2006.173.14:09:54.83#ibcon#about to read 5, iclass 22, count 0 2006.173.14:09:54.83#ibcon#read 5, iclass 22, count 0 2006.173.14:09:54.83#ibcon#about to read 6, iclass 22, count 0 2006.173.14:09:54.83#ibcon#read 6, iclass 22, count 0 2006.173.14:09:54.83#ibcon#end of sib2, iclass 22, count 0 2006.173.14:09:54.83#ibcon#*after write, iclass 22, count 0 2006.173.14:09:54.83#ibcon#*before return 0, iclass 22, count 0 2006.173.14:09:54.84#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.14:09:54.84#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.14:09:54.84#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.14:09:54.84#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.14:09:54.84$vck44/valo=6,814.99 2006.173.14:09:54.84#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.14:09:54.84#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.14:09:54.84#ibcon#ireg 17 cls_cnt 0 2006.173.14:09:54.84#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.14:09:54.84#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.14:09:54.84#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.14:09:54.84#ibcon#enter wrdev, iclass 24, count 0 2006.173.14:09:54.84#ibcon#first serial, iclass 24, count 0 2006.173.14:09:54.84#ibcon#enter sib2, iclass 24, count 0 2006.173.14:09:54.84#ibcon#flushed, iclass 24, count 0 2006.173.14:09:54.84#ibcon#about to write, iclass 24, count 0 2006.173.14:09:54.84#ibcon#wrote, iclass 24, count 0 2006.173.14:09:54.84#ibcon#about to read 3, iclass 24, count 0 2006.173.14:09:54.85#ibcon#read 3, iclass 24, count 0 2006.173.14:09:54.85#ibcon#about to read 4, iclass 24, count 0 2006.173.14:09:54.85#ibcon#read 4, iclass 24, count 0 2006.173.14:09:54.85#ibcon#about to read 5, iclass 24, count 0 2006.173.14:09:54.85#ibcon#read 5, iclass 24, count 0 2006.173.14:09:54.85#ibcon#about to read 6, iclass 24, count 0 2006.173.14:09:54.85#ibcon#read 6, iclass 24, count 0 2006.173.14:09:54.85#ibcon#end of sib2, iclass 24, count 0 2006.173.14:09:54.85#ibcon#*mode == 0, iclass 24, count 0 2006.173.14:09:54.85#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.14:09:54.86#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.14:09:54.86#ibcon#*before write, iclass 24, count 0 2006.173.14:09:54.86#ibcon#enter sib2, iclass 24, count 0 2006.173.14:09:54.86#ibcon#flushed, iclass 24, count 0 2006.173.14:09:54.86#ibcon#about to write, iclass 24, count 0 2006.173.14:09:54.86#ibcon#wrote, iclass 24, count 0 2006.173.14:09:54.86#ibcon#about to read 3, iclass 24, count 0 2006.173.14:09:54.89#ibcon#read 3, iclass 24, count 0 2006.173.14:09:54.89#ibcon#about to read 4, iclass 24, count 0 2006.173.14:09:54.89#ibcon#read 4, iclass 24, count 0 2006.173.14:09:54.89#ibcon#about to read 5, iclass 24, count 0 2006.173.14:09:54.89#ibcon#read 5, iclass 24, count 0 2006.173.14:09:54.89#ibcon#about to read 6, iclass 24, count 0 2006.173.14:09:54.89#ibcon#read 6, iclass 24, count 0 2006.173.14:09:54.89#ibcon#end of sib2, iclass 24, count 0 2006.173.14:09:54.89#ibcon#*after write, iclass 24, count 0 2006.173.14:09:54.89#ibcon#*before return 0, iclass 24, count 0 2006.173.14:09:54.90#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.14:09:54.90#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.14:09:54.90#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.14:09:54.90#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.14:09:54.90$vck44/va=6,3 2006.173.14:09:54.90#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.14:09:54.90#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.14:09:54.90#ibcon#ireg 11 cls_cnt 2 2006.173.14:09:54.90#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.14:09:54.95#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.14:09:54.95#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.14:09:54.95#ibcon#enter wrdev, iclass 26, count 2 2006.173.14:09:54.95#ibcon#first serial, iclass 26, count 2 2006.173.14:09:54.95#ibcon#enter sib2, iclass 26, count 2 2006.173.14:09:54.95#ibcon#flushed, iclass 26, count 2 2006.173.14:09:54.95#ibcon#about to write, iclass 26, count 2 2006.173.14:09:54.95#ibcon#wrote, iclass 26, count 2 2006.173.14:09:54.95#ibcon#about to read 3, iclass 26, count 2 2006.173.14:09:54.97#ibcon#read 3, iclass 26, count 2 2006.173.14:09:54.97#ibcon#about to read 4, iclass 26, count 2 2006.173.14:09:54.97#ibcon#read 4, iclass 26, count 2 2006.173.14:09:54.97#ibcon#about to read 5, iclass 26, count 2 2006.173.14:09:54.97#ibcon#read 5, iclass 26, count 2 2006.173.14:09:54.97#ibcon#about to read 6, iclass 26, count 2 2006.173.14:09:54.97#ibcon#read 6, iclass 26, count 2 2006.173.14:09:54.97#ibcon#end of sib2, iclass 26, count 2 2006.173.14:09:54.97#ibcon#*mode == 0, iclass 26, count 2 2006.173.14:09:54.97#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.14:09:54.97#ibcon#[25=AT06-03\r\n] 2006.173.14:09:54.97#ibcon#*before write, iclass 26, count 2 2006.173.14:09:54.97#ibcon#enter sib2, iclass 26, count 2 2006.173.14:09:54.97#ibcon#flushed, iclass 26, count 2 2006.173.14:09:54.98#ibcon#about to write, iclass 26, count 2 2006.173.14:09:54.98#ibcon#wrote, iclass 26, count 2 2006.173.14:09:54.98#ibcon#about to read 3, iclass 26, count 2 2006.173.14:09:55.00#ibcon#read 3, iclass 26, count 2 2006.173.14:09:55.00#ibcon#about to read 4, iclass 26, count 2 2006.173.14:09:55.00#ibcon#read 4, iclass 26, count 2 2006.173.14:09:55.00#ibcon#about to read 5, iclass 26, count 2 2006.173.14:09:55.00#ibcon#read 5, iclass 26, count 2 2006.173.14:09:55.00#ibcon#about to read 6, iclass 26, count 2 2006.173.14:09:55.00#ibcon#read 6, iclass 26, count 2 2006.173.14:09:55.00#ibcon#end of sib2, iclass 26, count 2 2006.173.14:09:55.00#ibcon#*after write, iclass 26, count 2 2006.173.14:09:55.00#ibcon#*before return 0, iclass 26, count 2 2006.173.14:09:55.00#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.14:09:55.00#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.14:09:55.00#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.14:09:55.00#ibcon#ireg 7 cls_cnt 0 2006.173.14:09:55.00#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.14:09:55.12#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.14:09:55.12#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.14:09:55.12#ibcon#enter wrdev, iclass 26, count 0 2006.173.14:09:55.12#ibcon#first serial, iclass 26, count 0 2006.173.14:09:55.12#ibcon#enter sib2, iclass 26, count 0 2006.173.14:09:55.12#ibcon#flushed, iclass 26, count 0 2006.173.14:09:55.12#ibcon#about to write, iclass 26, count 0 2006.173.14:09:55.12#ibcon#wrote, iclass 26, count 0 2006.173.14:09:55.12#ibcon#about to read 3, iclass 26, count 0 2006.173.14:09:55.15#ibcon#read 3, iclass 26, count 0 2006.173.14:09:55.15#ibcon#about to read 4, iclass 26, count 0 2006.173.14:09:55.15#ibcon#read 4, iclass 26, count 0 2006.173.14:09:55.15#ibcon#about to read 5, iclass 26, count 0 2006.173.14:09:55.15#ibcon#read 5, iclass 26, count 0 2006.173.14:09:55.15#ibcon#about to read 6, iclass 26, count 0 2006.173.14:09:55.15#ibcon#read 6, iclass 26, count 0 2006.173.14:09:55.15#ibcon#end of sib2, iclass 26, count 0 2006.173.14:09:55.15#ibcon#*mode == 0, iclass 26, count 0 2006.173.14:09:55.15#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.14:09:55.15#ibcon#[25=USB\r\n] 2006.173.14:09:55.15#ibcon#*before write, iclass 26, count 0 2006.173.14:09:55.15#ibcon#enter sib2, iclass 26, count 0 2006.173.14:09:55.15#ibcon#flushed, iclass 26, count 0 2006.173.14:09:55.15#ibcon#about to write, iclass 26, count 0 2006.173.14:09:55.15#ibcon#wrote, iclass 26, count 0 2006.173.14:09:55.15#ibcon#about to read 3, iclass 26, count 0 2006.173.14:09:55.17#ibcon#read 3, iclass 26, count 0 2006.173.14:09:55.17#ibcon#about to read 4, iclass 26, count 0 2006.173.14:09:55.17#ibcon#read 4, iclass 26, count 0 2006.173.14:09:55.17#ibcon#about to read 5, iclass 26, count 0 2006.173.14:09:55.17#ibcon#read 5, iclass 26, count 0 2006.173.14:09:55.17#ibcon#about to read 6, iclass 26, count 0 2006.173.14:09:55.17#ibcon#read 6, iclass 26, count 0 2006.173.14:09:55.17#ibcon#end of sib2, iclass 26, count 0 2006.173.14:09:55.17#ibcon#*after write, iclass 26, count 0 2006.173.14:09:55.17#ibcon#*before return 0, iclass 26, count 0 2006.173.14:09:55.17#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.14:09:55.17#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.14:09:55.17#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.14:09:55.18#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.14:09:55.18$vck44/valo=7,864.99 2006.173.14:09:55.18#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.14:09:55.18#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.14:09:55.18#ibcon#ireg 17 cls_cnt 0 2006.173.14:09:55.18#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.14:09:55.18#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.14:09:55.18#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.14:09:55.18#ibcon#enter wrdev, iclass 28, count 0 2006.173.14:09:55.18#ibcon#first serial, iclass 28, count 0 2006.173.14:09:55.18#ibcon#enter sib2, iclass 28, count 0 2006.173.14:09:55.18#ibcon#flushed, iclass 28, count 0 2006.173.14:09:55.18#ibcon#about to write, iclass 28, count 0 2006.173.14:09:55.18#ibcon#wrote, iclass 28, count 0 2006.173.14:09:55.18#ibcon#about to read 3, iclass 28, count 0 2006.173.14:09:55.19#ibcon#read 3, iclass 28, count 0 2006.173.14:09:55.19#ibcon#about to read 4, iclass 28, count 0 2006.173.14:09:55.19#ibcon#read 4, iclass 28, count 0 2006.173.14:09:55.19#ibcon#about to read 5, iclass 28, count 0 2006.173.14:09:55.19#ibcon#read 5, iclass 28, count 0 2006.173.14:09:55.19#ibcon#about to read 6, iclass 28, count 0 2006.173.14:09:55.19#ibcon#read 6, iclass 28, count 0 2006.173.14:09:55.19#ibcon#end of sib2, iclass 28, count 0 2006.173.14:09:55.19#ibcon#*mode == 0, iclass 28, count 0 2006.173.14:09:55.19#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.14:09:55.20#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.14:09:55.20#ibcon#*before write, iclass 28, count 0 2006.173.14:09:55.20#ibcon#enter sib2, iclass 28, count 0 2006.173.14:09:55.20#ibcon#flushed, iclass 28, count 0 2006.173.14:09:55.20#ibcon#about to write, iclass 28, count 0 2006.173.14:09:55.20#ibcon#wrote, iclass 28, count 0 2006.173.14:09:55.20#ibcon#about to read 3, iclass 28, count 0 2006.173.14:09:55.23#ibcon#read 3, iclass 28, count 0 2006.173.14:09:55.23#ibcon#about to read 4, iclass 28, count 0 2006.173.14:09:55.23#ibcon#read 4, iclass 28, count 0 2006.173.14:09:55.23#ibcon#about to read 5, iclass 28, count 0 2006.173.14:09:55.23#ibcon#read 5, iclass 28, count 0 2006.173.14:09:55.23#ibcon#about to read 6, iclass 28, count 0 2006.173.14:09:55.23#ibcon#read 6, iclass 28, count 0 2006.173.14:09:55.23#ibcon#end of sib2, iclass 28, count 0 2006.173.14:09:55.23#ibcon#*after write, iclass 28, count 0 2006.173.14:09:55.23#ibcon#*before return 0, iclass 28, count 0 2006.173.14:09:55.23#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.14:09:55.24#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.14:09:55.24#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.14:09:55.24#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.14:09:55.24$vck44/va=7,4 2006.173.14:09:55.24#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.14:09:55.24#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.14:09:55.24#ibcon#ireg 11 cls_cnt 2 2006.173.14:09:55.24#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.14:09:55.28#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.14:09:55.28#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.14:09:55.28#ibcon#enter wrdev, iclass 30, count 2 2006.173.14:09:55.28#ibcon#first serial, iclass 30, count 2 2006.173.14:09:55.28#ibcon#enter sib2, iclass 30, count 2 2006.173.14:09:55.28#ibcon#flushed, iclass 30, count 2 2006.173.14:09:55.28#ibcon#about to write, iclass 30, count 2 2006.173.14:09:55.28#ibcon#wrote, iclass 30, count 2 2006.173.14:09:55.28#ibcon#about to read 3, iclass 30, count 2 2006.173.14:09:55.30#ibcon#read 3, iclass 30, count 2 2006.173.14:09:55.30#ibcon#about to read 4, iclass 30, count 2 2006.173.14:09:55.30#ibcon#read 4, iclass 30, count 2 2006.173.14:09:55.30#ibcon#about to read 5, iclass 30, count 2 2006.173.14:09:55.30#ibcon#read 5, iclass 30, count 2 2006.173.14:09:55.30#ibcon#about to read 6, iclass 30, count 2 2006.173.14:09:55.30#ibcon#read 6, iclass 30, count 2 2006.173.14:09:55.30#ibcon#end of sib2, iclass 30, count 2 2006.173.14:09:55.30#ibcon#*mode == 0, iclass 30, count 2 2006.173.14:09:55.30#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.14:09:55.30#ibcon#[25=AT07-04\r\n] 2006.173.14:09:55.30#ibcon#*before write, iclass 30, count 2 2006.173.14:09:55.30#ibcon#enter sib2, iclass 30, count 2 2006.173.14:09:55.30#ibcon#flushed, iclass 30, count 2 2006.173.14:09:55.31#ibcon#about to write, iclass 30, count 2 2006.173.14:09:55.31#ibcon#wrote, iclass 30, count 2 2006.173.14:09:55.31#ibcon#about to read 3, iclass 30, count 2 2006.173.14:09:55.33#ibcon#read 3, iclass 30, count 2 2006.173.14:09:55.33#ibcon#about to read 4, iclass 30, count 2 2006.173.14:09:55.33#ibcon#read 4, iclass 30, count 2 2006.173.14:09:55.33#ibcon#about to read 5, iclass 30, count 2 2006.173.14:09:55.33#ibcon#read 5, iclass 30, count 2 2006.173.14:09:55.33#ibcon#about to read 6, iclass 30, count 2 2006.173.14:09:55.33#ibcon#read 6, iclass 30, count 2 2006.173.14:09:55.33#ibcon#end of sib2, iclass 30, count 2 2006.173.14:09:55.33#ibcon#*after write, iclass 30, count 2 2006.173.14:09:55.33#ibcon#*before return 0, iclass 30, count 2 2006.173.14:09:55.33#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.14:09:55.34#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.14:09:55.34#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.14:09:55.34#ibcon#ireg 7 cls_cnt 0 2006.173.14:09:55.34#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.14:09:55.45#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.14:09:55.45#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.14:09:55.45#ibcon#enter wrdev, iclass 30, count 0 2006.173.14:09:55.45#ibcon#first serial, iclass 30, count 0 2006.173.14:09:55.45#ibcon#enter sib2, iclass 30, count 0 2006.173.14:09:55.45#ibcon#flushed, iclass 30, count 0 2006.173.14:09:55.45#ibcon#about to write, iclass 30, count 0 2006.173.14:09:55.45#ibcon#wrote, iclass 30, count 0 2006.173.14:09:55.45#ibcon#about to read 3, iclass 30, count 0 2006.173.14:09:55.47#ibcon#read 3, iclass 30, count 0 2006.173.14:09:55.47#ibcon#about to read 4, iclass 30, count 0 2006.173.14:09:55.47#ibcon#read 4, iclass 30, count 0 2006.173.14:09:55.47#ibcon#about to read 5, iclass 30, count 0 2006.173.14:09:55.47#ibcon#read 5, iclass 30, count 0 2006.173.14:09:55.47#ibcon#about to read 6, iclass 30, count 0 2006.173.14:09:55.47#ibcon#read 6, iclass 30, count 0 2006.173.14:09:55.47#ibcon#end of sib2, iclass 30, count 0 2006.173.14:09:55.47#ibcon#*mode == 0, iclass 30, count 0 2006.173.14:09:55.47#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.14:09:55.47#ibcon#[25=USB\r\n] 2006.173.14:09:55.47#ibcon#*before write, iclass 30, count 0 2006.173.14:09:55.47#ibcon#enter sib2, iclass 30, count 0 2006.173.14:09:55.47#ibcon#flushed, iclass 30, count 0 2006.173.14:09:55.48#ibcon#about to write, iclass 30, count 0 2006.173.14:09:55.48#ibcon#wrote, iclass 30, count 0 2006.173.14:09:55.48#ibcon#about to read 3, iclass 30, count 0 2006.173.14:09:55.50#ibcon#read 3, iclass 30, count 0 2006.173.14:09:55.50#ibcon#about to read 4, iclass 30, count 0 2006.173.14:09:55.50#ibcon#read 4, iclass 30, count 0 2006.173.14:09:55.50#ibcon#about to read 5, iclass 30, count 0 2006.173.14:09:55.50#ibcon#read 5, iclass 30, count 0 2006.173.14:09:55.50#ibcon#about to read 6, iclass 30, count 0 2006.173.14:09:55.50#ibcon#read 6, iclass 30, count 0 2006.173.14:09:55.50#ibcon#end of sib2, iclass 30, count 0 2006.173.14:09:55.50#ibcon#*after write, iclass 30, count 0 2006.173.14:09:55.50#ibcon#*before return 0, iclass 30, count 0 2006.173.14:09:55.50#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.14:09:55.51#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.14:09:55.51#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.14:09:55.51#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.14:09:55.51$vck44/valo=8,884.99 2006.173.14:09:55.51#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.14:09:55.51#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.14:09:55.51#ibcon#ireg 17 cls_cnt 0 2006.173.14:09:55.51#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.14:09:55.51#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.14:09:55.51#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.14:09:55.51#ibcon#enter wrdev, iclass 32, count 0 2006.173.14:09:55.51#ibcon#first serial, iclass 32, count 0 2006.173.14:09:55.51#ibcon#enter sib2, iclass 32, count 0 2006.173.14:09:55.51#ibcon#flushed, iclass 32, count 0 2006.173.14:09:55.51#ibcon#about to write, iclass 32, count 0 2006.173.14:09:55.51#ibcon#wrote, iclass 32, count 0 2006.173.14:09:55.51#ibcon#about to read 3, iclass 32, count 0 2006.173.14:09:55.52#ibcon#read 3, iclass 32, count 0 2006.173.14:09:55.52#ibcon#about to read 4, iclass 32, count 0 2006.173.14:09:55.52#ibcon#read 4, iclass 32, count 0 2006.173.14:09:55.52#ibcon#about to read 5, iclass 32, count 0 2006.173.14:09:55.52#ibcon#read 5, iclass 32, count 0 2006.173.14:09:55.52#ibcon#about to read 6, iclass 32, count 0 2006.173.14:09:55.52#ibcon#read 6, iclass 32, count 0 2006.173.14:09:55.52#ibcon#end of sib2, iclass 32, count 0 2006.173.14:09:55.53#ibcon#*mode == 0, iclass 32, count 0 2006.173.14:09:55.53#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.14:09:55.53#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.14:09:55.53#ibcon#*before write, iclass 32, count 0 2006.173.14:09:55.53#ibcon#enter sib2, iclass 32, count 0 2006.173.14:09:55.53#ibcon#flushed, iclass 32, count 0 2006.173.14:09:55.53#ibcon#about to write, iclass 32, count 0 2006.173.14:09:55.53#ibcon#wrote, iclass 32, count 0 2006.173.14:09:55.53#ibcon#about to read 3, iclass 32, count 0 2006.173.14:09:55.56#ibcon#read 3, iclass 32, count 0 2006.173.14:09:55.56#ibcon#about to read 4, iclass 32, count 0 2006.173.14:09:55.56#ibcon#read 4, iclass 32, count 0 2006.173.14:09:55.56#ibcon#about to read 5, iclass 32, count 0 2006.173.14:09:55.56#ibcon#read 5, iclass 32, count 0 2006.173.14:09:55.56#ibcon#about to read 6, iclass 32, count 0 2006.173.14:09:55.56#ibcon#read 6, iclass 32, count 0 2006.173.14:09:55.56#ibcon#end of sib2, iclass 32, count 0 2006.173.14:09:55.57#ibcon#*after write, iclass 32, count 0 2006.173.14:09:55.57#ibcon#*before return 0, iclass 32, count 0 2006.173.14:09:55.57#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.14:09:55.57#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.14:09:55.57#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.14:09:55.57#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.14:09:55.57$vck44/va=8,4 2006.173.14:09:55.57#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.14:09:55.57#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.14:09:55.57#ibcon#ireg 11 cls_cnt 2 2006.173.14:09:55.57#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.14:09:55.62#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.14:09:55.62#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.14:09:55.62#ibcon#enter wrdev, iclass 34, count 2 2006.173.14:09:55.62#ibcon#first serial, iclass 34, count 2 2006.173.14:09:55.62#ibcon#enter sib2, iclass 34, count 2 2006.173.14:09:55.62#ibcon#flushed, iclass 34, count 2 2006.173.14:09:55.62#ibcon#about to write, iclass 34, count 2 2006.173.14:09:55.62#ibcon#wrote, iclass 34, count 2 2006.173.14:09:55.62#ibcon#about to read 3, iclass 34, count 2 2006.173.14:09:55.64#ibcon#read 3, iclass 34, count 2 2006.173.14:09:55.64#ibcon#about to read 4, iclass 34, count 2 2006.173.14:09:55.64#ibcon#read 4, iclass 34, count 2 2006.173.14:09:55.64#ibcon#about to read 5, iclass 34, count 2 2006.173.14:09:55.64#ibcon#read 5, iclass 34, count 2 2006.173.14:09:55.64#ibcon#about to read 6, iclass 34, count 2 2006.173.14:09:55.64#ibcon#read 6, iclass 34, count 2 2006.173.14:09:55.64#ibcon#end of sib2, iclass 34, count 2 2006.173.14:09:55.64#ibcon#*mode == 0, iclass 34, count 2 2006.173.14:09:55.64#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.14:09:55.65#ibcon#[25=AT08-04\r\n] 2006.173.14:09:55.65#ibcon#*before write, iclass 34, count 2 2006.173.14:09:55.65#ibcon#enter sib2, iclass 34, count 2 2006.173.14:09:55.65#ibcon#flushed, iclass 34, count 2 2006.173.14:09:55.65#ibcon#about to write, iclass 34, count 2 2006.173.14:09:55.65#ibcon#wrote, iclass 34, count 2 2006.173.14:09:55.65#ibcon#about to read 3, iclass 34, count 2 2006.173.14:09:55.67#ibcon#read 3, iclass 34, count 2 2006.173.14:09:55.67#ibcon#about to read 4, iclass 34, count 2 2006.173.14:09:55.67#ibcon#read 4, iclass 34, count 2 2006.173.14:09:55.67#ibcon#about to read 5, iclass 34, count 2 2006.173.14:09:55.67#ibcon#read 5, iclass 34, count 2 2006.173.14:09:55.67#ibcon#about to read 6, iclass 34, count 2 2006.173.14:09:55.67#ibcon#read 6, iclass 34, count 2 2006.173.14:09:55.67#ibcon#end of sib2, iclass 34, count 2 2006.173.14:09:55.67#ibcon#*after write, iclass 34, count 2 2006.173.14:09:55.68#ibcon#*before return 0, iclass 34, count 2 2006.173.14:09:55.68#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.14:09:55.68#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.14:09:55.68#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.14:09:55.68#ibcon#ireg 7 cls_cnt 0 2006.173.14:09:55.68#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.14:09:55.79#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.14:09:55.79#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.14:09:55.79#ibcon#enter wrdev, iclass 34, count 0 2006.173.14:09:55.79#ibcon#first serial, iclass 34, count 0 2006.173.14:09:55.79#ibcon#enter sib2, iclass 34, count 0 2006.173.14:09:55.79#ibcon#flushed, iclass 34, count 0 2006.173.14:09:55.79#ibcon#about to write, iclass 34, count 0 2006.173.14:09:55.79#ibcon#wrote, iclass 34, count 0 2006.173.14:09:55.79#ibcon#about to read 3, iclass 34, count 0 2006.173.14:09:55.81#ibcon#read 3, iclass 34, count 0 2006.173.14:09:55.81#ibcon#about to read 4, iclass 34, count 0 2006.173.14:09:55.81#ibcon#read 4, iclass 34, count 0 2006.173.14:09:55.81#ibcon#about to read 5, iclass 34, count 0 2006.173.14:09:55.81#ibcon#read 5, iclass 34, count 0 2006.173.14:09:55.81#ibcon#about to read 6, iclass 34, count 0 2006.173.14:09:55.81#ibcon#read 6, iclass 34, count 0 2006.173.14:09:55.81#ibcon#end of sib2, iclass 34, count 0 2006.173.14:09:55.81#ibcon#*mode == 0, iclass 34, count 0 2006.173.14:09:55.81#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.14:09:55.81#ibcon#[25=USB\r\n] 2006.173.14:09:55.81#ibcon#*before write, iclass 34, count 0 2006.173.14:09:55.81#ibcon#enter sib2, iclass 34, count 0 2006.173.14:09:55.82#ibcon#flushed, iclass 34, count 0 2006.173.14:09:55.82#ibcon#about to write, iclass 34, count 0 2006.173.14:09:55.82#ibcon#wrote, iclass 34, count 0 2006.173.14:09:55.82#ibcon#about to read 3, iclass 34, count 0 2006.173.14:09:55.84#ibcon#read 3, iclass 34, count 0 2006.173.14:09:55.84#ibcon#about to read 4, iclass 34, count 0 2006.173.14:09:55.84#ibcon#read 4, iclass 34, count 0 2006.173.14:09:55.84#ibcon#about to read 5, iclass 34, count 0 2006.173.14:09:55.84#ibcon#read 5, iclass 34, count 0 2006.173.14:09:55.84#ibcon#about to read 6, iclass 34, count 0 2006.173.14:09:55.84#ibcon#read 6, iclass 34, count 0 2006.173.14:09:55.84#ibcon#end of sib2, iclass 34, count 0 2006.173.14:09:55.84#ibcon#*after write, iclass 34, count 0 2006.173.14:09:55.84#ibcon#*before return 0, iclass 34, count 0 2006.173.14:09:55.84#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.14:09:55.84#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.14:09:55.85#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.14:09:55.85#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.14:09:55.85$vck44/vblo=1,629.99 2006.173.14:09:55.85#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.14:09:55.85#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.14:09:55.85#ibcon#ireg 17 cls_cnt 0 2006.173.14:09:55.85#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.14:09:55.85#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.14:09:55.85#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.14:09:55.85#ibcon#enter wrdev, iclass 36, count 0 2006.173.14:09:55.85#ibcon#first serial, iclass 36, count 0 2006.173.14:09:55.85#ibcon#enter sib2, iclass 36, count 0 2006.173.14:09:55.85#ibcon#flushed, iclass 36, count 0 2006.173.14:09:55.85#ibcon#about to write, iclass 36, count 0 2006.173.14:09:55.85#ibcon#wrote, iclass 36, count 0 2006.173.14:09:55.85#ibcon#about to read 3, iclass 36, count 0 2006.173.14:09:55.86#ibcon#read 3, iclass 36, count 0 2006.173.14:09:55.86#ibcon#about to read 4, iclass 36, count 0 2006.173.14:09:55.86#ibcon#read 4, iclass 36, count 0 2006.173.14:09:55.86#ibcon#about to read 5, iclass 36, count 0 2006.173.14:09:55.86#ibcon#read 5, iclass 36, count 0 2006.173.14:09:55.86#ibcon#about to read 6, iclass 36, count 0 2006.173.14:09:55.86#ibcon#read 6, iclass 36, count 0 2006.173.14:09:55.86#ibcon#end of sib2, iclass 36, count 0 2006.173.14:09:55.86#ibcon#*mode == 0, iclass 36, count 0 2006.173.14:09:55.86#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.14:09:55.86#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.14:09:55.86#ibcon#*before write, iclass 36, count 0 2006.173.14:09:55.86#ibcon#enter sib2, iclass 36, count 0 2006.173.14:09:55.87#ibcon#flushed, iclass 36, count 0 2006.173.14:09:55.87#ibcon#about to write, iclass 36, count 0 2006.173.14:09:55.87#ibcon#wrote, iclass 36, count 0 2006.173.14:09:55.87#ibcon#about to read 3, iclass 36, count 0 2006.173.14:09:55.90#ibcon#read 3, iclass 36, count 0 2006.173.14:09:55.90#ibcon#about to read 4, iclass 36, count 0 2006.173.14:09:55.90#ibcon#read 4, iclass 36, count 0 2006.173.14:09:55.90#ibcon#about to read 5, iclass 36, count 0 2006.173.14:09:55.90#ibcon#read 5, iclass 36, count 0 2006.173.14:09:55.90#ibcon#about to read 6, iclass 36, count 0 2006.173.14:09:55.90#ibcon#read 6, iclass 36, count 0 2006.173.14:09:55.90#ibcon#end of sib2, iclass 36, count 0 2006.173.14:09:55.90#ibcon#*after write, iclass 36, count 0 2006.173.14:09:55.90#ibcon#*before return 0, iclass 36, count 0 2006.173.14:09:55.91#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.14:09:55.91#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.14:09:55.91#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.14:09:55.91#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.14:09:55.91$vck44/vb=1,4 2006.173.14:09:55.91#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.14:09:55.91#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.14:09:55.91#ibcon#ireg 11 cls_cnt 2 2006.173.14:09:55.91#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.14:09:55.91#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.14:09:55.91#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.14:09:55.91#ibcon#enter wrdev, iclass 38, count 2 2006.173.14:09:55.91#ibcon#first serial, iclass 38, count 2 2006.173.14:09:55.91#ibcon#enter sib2, iclass 38, count 2 2006.173.14:09:55.91#ibcon#flushed, iclass 38, count 2 2006.173.14:09:55.91#ibcon#about to write, iclass 38, count 2 2006.173.14:09:55.91#ibcon#wrote, iclass 38, count 2 2006.173.14:09:55.91#ibcon#about to read 3, iclass 38, count 2 2006.173.14:09:55.92#ibcon#read 3, iclass 38, count 2 2006.173.14:09:55.92#ibcon#about to read 4, iclass 38, count 2 2006.173.14:09:55.92#ibcon#read 4, iclass 38, count 2 2006.173.14:09:55.92#ibcon#about to read 5, iclass 38, count 2 2006.173.14:09:55.92#ibcon#read 5, iclass 38, count 2 2006.173.14:09:55.92#ibcon#about to read 6, iclass 38, count 2 2006.173.14:09:55.92#ibcon#read 6, iclass 38, count 2 2006.173.14:09:55.92#ibcon#end of sib2, iclass 38, count 2 2006.173.14:09:55.92#ibcon#*mode == 0, iclass 38, count 2 2006.173.14:09:55.92#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.14:09:55.93#ibcon#[27=AT01-04\r\n] 2006.173.14:09:55.93#ibcon#*before write, iclass 38, count 2 2006.173.14:09:55.93#ibcon#enter sib2, iclass 38, count 2 2006.173.14:09:55.93#ibcon#flushed, iclass 38, count 2 2006.173.14:09:55.93#ibcon#about to write, iclass 38, count 2 2006.173.14:09:55.93#ibcon#wrote, iclass 38, count 2 2006.173.14:09:55.93#ibcon#about to read 3, iclass 38, count 2 2006.173.14:09:55.95#ibcon#read 3, iclass 38, count 2 2006.173.14:09:55.95#ibcon#about to read 4, iclass 38, count 2 2006.173.14:09:55.95#ibcon#read 4, iclass 38, count 2 2006.173.14:09:55.95#ibcon#about to read 5, iclass 38, count 2 2006.173.14:09:55.95#ibcon#read 5, iclass 38, count 2 2006.173.14:09:55.95#ibcon#about to read 6, iclass 38, count 2 2006.173.14:09:55.95#ibcon#read 6, iclass 38, count 2 2006.173.14:09:55.95#ibcon#end of sib2, iclass 38, count 2 2006.173.14:09:55.95#ibcon#*after write, iclass 38, count 2 2006.173.14:09:55.95#ibcon#*before return 0, iclass 38, count 2 2006.173.14:09:55.95#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.14:09:55.96#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.14:09:55.96#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.14:09:55.96#ibcon#ireg 7 cls_cnt 0 2006.173.14:09:55.96#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.14:09:56.07#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.14:09:56.07#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.14:09:56.07#ibcon#enter wrdev, iclass 38, count 0 2006.173.14:09:56.07#ibcon#first serial, iclass 38, count 0 2006.173.14:09:56.07#ibcon#enter sib2, iclass 38, count 0 2006.173.14:09:56.07#ibcon#flushed, iclass 38, count 0 2006.173.14:09:56.07#ibcon#about to write, iclass 38, count 0 2006.173.14:09:56.07#ibcon#wrote, iclass 38, count 0 2006.173.14:09:56.07#ibcon#about to read 3, iclass 38, count 0 2006.173.14:09:56.09#ibcon#read 3, iclass 38, count 0 2006.173.14:09:56.09#ibcon#about to read 4, iclass 38, count 0 2006.173.14:09:56.09#ibcon#read 4, iclass 38, count 0 2006.173.14:09:56.09#ibcon#about to read 5, iclass 38, count 0 2006.173.14:09:56.09#ibcon#read 5, iclass 38, count 0 2006.173.14:09:56.09#ibcon#about to read 6, iclass 38, count 0 2006.173.14:09:56.09#ibcon#read 6, iclass 38, count 0 2006.173.14:09:56.09#ibcon#end of sib2, iclass 38, count 0 2006.173.14:09:56.09#ibcon#*mode == 0, iclass 38, count 0 2006.173.14:09:56.09#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.14:09:56.09#ibcon#[27=USB\r\n] 2006.173.14:09:56.09#ibcon#*before write, iclass 38, count 0 2006.173.14:09:56.09#ibcon#enter sib2, iclass 38, count 0 2006.173.14:09:56.09#ibcon#flushed, iclass 38, count 0 2006.173.14:09:56.09#ibcon#about to write, iclass 38, count 0 2006.173.14:09:56.10#ibcon#wrote, iclass 38, count 0 2006.173.14:09:56.10#ibcon#about to read 3, iclass 38, count 0 2006.173.14:09:56.12#ibcon#read 3, iclass 38, count 0 2006.173.14:09:56.12#ibcon#about to read 4, iclass 38, count 0 2006.173.14:09:56.12#ibcon#read 4, iclass 38, count 0 2006.173.14:09:56.12#ibcon#about to read 5, iclass 38, count 0 2006.173.14:09:56.12#ibcon#read 5, iclass 38, count 0 2006.173.14:09:56.12#ibcon#about to read 6, iclass 38, count 0 2006.173.14:09:56.12#ibcon#read 6, iclass 38, count 0 2006.173.14:09:56.12#ibcon#end of sib2, iclass 38, count 0 2006.173.14:09:56.12#ibcon#*after write, iclass 38, count 0 2006.173.14:09:56.12#ibcon#*before return 0, iclass 38, count 0 2006.173.14:09:56.12#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.14:09:56.12#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.14:09:56.12#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.14:09:56.13#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.14:09:56.13$vck44/vblo=2,634.99 2006.173.14:09:56.13#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.14:09:56.13#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.14:09:56.13#ibcon#ireg 17 cls_cnt 0 2006.173.14:09:56.13#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.14:09:56.13#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.14:09:56.13#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.14:09:56.13#ibcon#enter wrdev, iclass 40, count 0 2006.173.14:09:56.13#ibcon#first serial, iclass 40, count 0 2006.173.14:09:56.13#ibcon#enter sib2, iclass 40, count 0 2006.173.14:09:56.13#ibcon#flushed, iclass 40, count 0 2006.173.14:09:56.13#ibcon#about to write, iclass 40, count 0 2006.173.14:09:56.13#ibcon#wrote, iclass 40, count 0 2006.173.14:09:56.13#ibcon#about to read 3, iclass 40, count 0 2006.173.14:09:56.15#ibcon#read 3, iclass 40, count 0 2006.173.14:09:56.15#ibcon#about to read 4, iclass 40, count 0 2006.173.14:09:56.15#ibcon#read 4, iclass 40, count 0 2006.173.14:09:56.15#ibcon#about to read 5, iclass 40, count 0 2006.173.14:09:56.15#ibcon#read 5, iclass 40, count 0 2006.173.14:09:56.15#ibcon#about to read 6, iclass 40, count 0 2006.173.14:09:56.15#ibcon#read 6, iclass 40, count 0 2006.173.14:09:56.15#ibcon#end of sib2, iclass 40, count 0 2006.173.14:09:56.15#ibcon#*mode == 0, iclass 40, count 0 2006.173.14:09:56.15#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.14:09:56.15#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.14:09:56.15#ibcon#*before write, iclass 40, count 0 2006.173.14:09:56.15#ibcon#enter sib2, iclass 40, count 0 2006.173.14:09:56.15#ibcon#flushed, iclass 40, count 0 2006.173.14:09:56.15#ibcon#about to write, iclass 40, count 0 2006.173.14:09:56.15#ibcon#wrote, iclass 40, count 0 2006.173.14:09:56.15#ibcon#about to read 3, iclass 40, count 0 2006.173.14:09:56.18#ibcon#read 3, iclass 40, count 0 2006.173.14:09:56.18#ibcon#about to read 4, iclass 40, count 0 2006.173.14:09:56.18#ibcon#read 4, iclass 40, count 0 2006.173.14:09:56.18#ibcon#about to read 5, iclass 40, count 0 2006.173.14:09:56.18#ibcon#read 5, iclass 40, count 0 2006.173.14:09:56.18#ibcon#about to read 6, iclass 40, count 0 2006.173.14:09:56.18#ibcon#read 6, iclass 40, count 0 2006.173.14:09:56.18#ibcon#end of sib2, iclass 40, count 0 2006.173.14:09:56.18#ibcon#*after write, iclass 40, count 0 2006.173.14:09:56.18#ibcon#*before return 0, iclass 40, count 0 2006.173.14:09:56.18#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.14:09:56.19#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.14:09:56.19#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.14:09:56.19#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.14:09:56.19$vck44/vb=2,4 2006.173.14:09:56.19#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.14:09:56.19#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.14:09:56.19#ibcon#ireg 11 cls_cnt 2 2006.173.14:09:56.19#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.14:09:56.23#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.14:09:56.23#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.14:09:56.23#ibcon#enter wrdev, iclass 4, count 2 2006.173.14:09:56.23#ibcon#first serial, iclass 4, count 2 2006.173.14:09:56.23#ibcon#enter sib2, iclass 4, count 2 2006.173.14:09:56.23#ibcon#flushed, iclass 4, count 2 2006.173.14:09:56.23#ibcon#about to write, iclass 4, count 2 2006.173.14:09:56.23#ibcon#wrote, iclass 4, count 2 2006.173.14:09:56.23#ibcon#about to read 3, iclass 4, count 2 2006.173.14:09:56.25#ibcon#read 3, iclass 4, count 2 2006.173.14:09:56.25#ibcon#about to read 4, iclass 4, count 2 2006.173.14:09:56.25#ibcon#read 4, iclass 4, count 2 2006.173.14:09:56.25#ibcon#about to read 5, iclass 4, count 2 2006.173.14:09:56.25#ibcon#read 5, iclass 4, count 2 2006.173.14:09:56.25#ibcon#about to read 6, iclass 4, count 2 2006.173.14:09:56.25#ibcon#read 6, iclass 4, count 2 2006.173.14:09:56.25#ibcon#end of sib2, iclass 4, count 2 2006.173.14:09:56.25#ibcon#*mode == 0, iclass 4, count 2 2006.173.14:09:56.25#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.14:09:56.25#ibcon#[27=AT02-04\r\n] 2006.173.14:09:56.25#ibcon#*before write, iclass 4, count 2 2006.173.14:09:56.25#ibcon#enter sib2, iclass 4, count 2 2006.173.14:09:56.25#ibcon#flushed, iclass 4, count 2 2006.173.14:09:56.25#ibcon#about to write, iclass 4, count 2 2006.173.14:09:56.26#ibcon#wrote, iclass 4, count 2 2006.173.14:09:56.26#ibcon#about to read 3, iclass 4, count 2 2006.173.14:09:56.28#ibcon#read 3, iclass 4, count 2 2006.173.14:09:56.28#ibcon#about to read 4, iclass 4, count 2 2006.173.14:09:56.28#ibcon#read 4, iclass 4, count 2 2006.173.14:09:56.28#ibcon#about to read 5, iclass 4, count 2 2006.173.14:09:56.28#ibcon#read 5, iclass 4, count 2 2006.173.14:09:56.28#ibcon#about to read 6, iclass 4, count 2 2006.173.14:09:56.28#ibcon#read 6, iclass 4, count 2 2006.173.14:09:56.28#ibcon#end of sib2, iclass 4, count 2 2006.173.14:09:56.28#ibcon#*after write, iclass 4, count 2 2006.173.14:09:56.28#ibcon#*before return 0, iclass 4, count 2 2006.173.14:09:56.29#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.14:09:56.29#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.14:09:56.29#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.14:09:56.29#ibcon#ireg 7 cls_cnt 0 2006.173.14:09:56.29#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.14:09:56.40#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.14:09:56.40#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.14:09:56.40#ibcon#enter wrdev, iclass 4, count 0 2006.173.14:09:56.40#ibcon#first serial, iclass 4, count 0 2006.173.14:09:56.40#ibcon#enter sib2, iclass 4, count 0 2006.173.14:09:56.40#ibcon#flushed, iclass 4, count 0 2006.173.14:09:56.40#ibcon#about to write, iclass 4, count 0 2006.173.14:09:56.40#ibcon#wrote, iclass 4, count 0 2006.173.14:09:56.40#ibcon#about to read 3, iclass 4, count 0 2006.173.14:09:56.42#ibcon#read 3, iclass 4, count 0 2006.173.14:09:56.42#ibcon#about to read 4, iclass 4, count 0 2006.173.14:09:56.42#ibcon#read 4, iclass 4, count 0 2006.173.14:09:56.42#ibcon#about to read 5, iclass 4, count 0 2006.173.14:09:56.42#ibcon#read 5, iclass 4, count 0 2006.173.14:09:56.42#ibcon#about to read 6, iclass 4, count 0 2006.173.14:09:56.42#ibcon#read 6, iclass 4, count 0 2006.173.14:09:56.42#ibcon#end of sib2, iclass 4, count 0 2006.173.14:09:56.42#ibcon#*mode == 0, iclass 4, count 0 2006.173.14:09:56.42#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.14:09:56.42#ibcon#[27=USB\r\n] 2006.173.14:09:56.42#ibcon#*before write, iclass 4, count 0 2006.173.14:09:56.42#ibcon#enter sib2, iclass 4, count 0 2006.173.14:09:56.42#ibcon#flushed, iclass 4, count 0 2006.173.14:09:56.42#ibcon#about to write, iclass 4, count 0 2006.173.14:09:56.43#ibcon#wrote, iclass 4, count 0 2006.173.14:09:56.43#ibcon#about to read 3, iclass 4, count 0 2006.173.14:09:56.45#ibcon#read 3, iclass 4, count 0 2006.173.14:09:56.45#ibcon#about to read 4, iclass 4, count 0 2006.173.14:09:56.45#ibcon#read 4, iclass 4, count 0 2006.173.14:09:56.45#ibcon#about to read 5, iclass 4, count 0 2006.173.14:09:56.45#ibcon#read 5, iclass 4, count 0 2006.173.14:09:56.45#ibcon#about to read 6, iclass 4, count 0 2006.173.14:09:56.45#ibcon#read 6, iclass 4, count 0 2006.173.14:09:56.45#ibcon#end of sib2, iclass 4, count 0 2006.173.14:09:56.45#ibcon#*after write, iclass 4, count 0 2006.173.14:09:56.45#ibcon#*before return 0, iclass 4, count 0 2006.173.14:09:56.46#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.14:09:56.46#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.14:09:56.46#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.14:09:56.46#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.14:09:56.46$vck44/vblo=3,649.99 2006.173.14:09:56.46#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.14:09:56.46#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.14:09:56.46#ibcon#ireg 17 cls_cnt 0 2006.173.14:09:56.46#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.14:09:56.46#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.14:09:56.46#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.14:09:56.46#ibcon#enter wrdev, iclass 6, count 0 2006.173.14:09:56.46#ibcon#first serial, iclass 6, count 0 2006.173.14:09:56.46#ibcon#enter sib2, iclass 6, count 0 2006.173.14:09:56.46#ibcon#flushed, iclass 6, count 0 2006.173.14:09:56.46#ibcon#about to write, iclass 6, count 0 2006.173.14:09:56.46#ibcon#wrote, iclass 6, count 0 2006.173.14:09:56.46#ibcon#about to read 3, iclass 6, count 0 2006.173.14:09:56.47#ibcon#read 3, iclass 6, count 0 2006.173.14:09:56.47#ibcon#about to read 4, iclass 6, count 0 2006.173.14:09:56.47#ibcon#read 4, iclass 6, count 0 2006.173.14:09:56.47#ibcon#about to read 5, iclass 6, count 0 2006.173.14:09:56.47#ibcon#read 5, iclass 6, count 0 2006.173.14:09:56.47#ibcon#about to read 6, iclass 6, count 0 2006.173.14:09:56.47#ibcon#read 6, iclass 6, count 0 2006.173.14:09:56.47#ibcon#end of sib2, iclass 6, count 0 2006.173.14:09:56.47#ibcon#*mode == 0, iclass 6, count 0 2006.173.14:09:56.47#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.14:09:56.48#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.14:09:56.48#ibcon#*before write, iclass 6, count 0 2006.173.14:09:56.48#ibcon#enter sib2, iclass 6, count 0 2006.173.14:09:56.48#ibcon#flushed, iclass 6, count 0 2006.173.14:09:56.48#ibcon#about to write, iclass 6, count 0 2006.173.14:09:56.48#ibcon#wrote, iclass 6, count 0 2006.173.14:09:56.48#ibcon#about to read 3, iclass 6, count 0 2006.173.14:09:56.51#ibcon#read 3, iclass 6, count 0 2006.173.14:09:56.51#ibcon#about to read 4, iclass 6, count 0 2006.173.14:09:56.51#ibcon#read 4, iclass 6, count 0 2006.173.14:09:56.51#ibcon#about to read 5, iclass 6, count 0 2006.173.14:09:56.51#ibcon#read 5, iclass 6, count 0 2006.173.14:09:56.51#ibcon#about to read 6, iclass 6, count 0 2006.173.14:09:56.51#ibcon#read 6, iclass 6, count 0 2006.173.14:09:56.51#ibcon#end of sib2, iclass 6, count 0 2006.173.14:09:56.51#ibcon#*after write, iclass 6, count 0 2006.173.14:09:56.51#ibcon#*before return 0, iclass 6, count 0 2006.173.14:09:56.51#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.14:09:56.51#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.14:09:56.52#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.14:09:56.52#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.14:09:56.52$vck44/vb=3,4 2006.173.14:09:56.52#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.14:09:56.52#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.14:09:56.52#ibcon#ireg 11 cls_cnt 2 2006.173.14:09:56.52#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.14:09:56.57#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.14:09:56.57#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.14:09:56.57#ibcon#enter wrdev, iclass 10, count 2 2006.173.14:09:56.57#ibcon#first serial, iclass 10, count 2 2006.173.14:09:56.57#ibcon#enter sib2, iclass 10, count 2 2006.173.14:09:56.57#ibcon#flushed, iclass 10, count 2 2006.173.14:09:56.57#ibcon#about to write, iclass 10, count 2 2006.173.14:09:56.57#ibcon#wrote, iclass 10, count 2 2006.173.14:09:56.57#ibcon#about to read 3, iclass 10, count 2 2006.173.14:09:56.59#ibcon#read 3, iclass 10, count 2 2006.173.14:09:56.59#ibcon#about to read 4, iclass 10, count 2 2006.173.14:09:56.59#ibcon#read 4, iclass 10, count 2 2006.173.14:09:56.59#ibcon#about to read 5, iclass 10, count 2 2006.173.14:09:56.59#ibcon#read 5, iclass 10, count 2 2006.173.14:09:56.59#ibcon#about to read 6, iclass 10, count 2 2006.173.14:09:56.59#ibcon#read 6, iclass 10, count 2 2006.173.14:09:56.59#ibcon#end of sib2, iclass 10, count 2 2006.173.14:09:56.59#ibcon#*mode == 0, iclass 10, count 2 2006.173.14:09:56.59#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.14:09:56.59#ibcon#[27=AT03-04\r\n] 2006.173.14:09:56.59#ibcon#*before write, iclass 10, count 2 2006.173.14:09:56.60#ibcon#enter sib2, iclass 10, count 2 2006.173.14:09:56.60#ibcon#flushed, iclass 10, count 2 2006.173.14:09:56.60#ibcon#about to write, iclass 10, count 2 2006.173.14:09:56.60#ibcon#wrote, iclass 10, count 2 2006.173.14:09:56.60#ibcon#about to read 3, iclass 10, count 2 2006.173.14:09:56.62#ibcon#read 3, iclass 10, count 2 2006.173.14:09:56.62#ibcon#about to read 4, iclass 10, count 2 2006.173.14:09:56.62#ibcon#read 4, iclass 10, count 2 2006.173.14:09:56.62#ibcon#about to read 5, iclass 10, count 2 2006.173.14:09:56.62#ibcon#read 5, iclass 10, count 2 2006.173.14:09:56.62#ibcon#about to read 6, iclass 10, count 2 2006.173.14:09:56.62#ibcon#read 6, iclass 10, count 2 2006.173.14:09:56.62#ibcon#end of sib2, iclass 10, count 2 2006.173.14:09:56.62#ibcon#*after write, iclass 10, count 2 2006.173.14:09:56.62#ibcon#*before return 0, iclass 10, count 2 2006.173.14:09:56.63#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.14:09:56.63#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.14:09:56.63#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.14:09:56.63#ibcon#ireg 7 cls_cnt 0 2006.173.14:09:56.63#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.14:09:56.74#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.14:09:56.74#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.14:09:56.74#ibcon#enter wrdev, iclass 10, count 0 2006.173.14:09:56.74#ibcon#first serial, iclass 10, count 0 2006.173.14:09:56.74#ibcon#enter sib2, iclass 10, count 0 2006.173.14:09:56.74#ibcon#flushed, iclass 10, count 0 2006.173.14:09:56.74#ibcon#about to write, iclass 10, count 0 2006.173.14:09:56.74#ibcon#wrote, iclass 10, count 0 2006.173.14:09:56.74#ibcon#about to read 3, iclass 10, count 0 2006.173.14:09:56.76#ibcon#read 3, iclass 10, count 0 2006.173.14:09:56.76#ibcon#about to read 4, iclass 10, count 0 2006.173.14:09:56.76#ibcon#read 4, iclass 10, count 0 2006.173.14:09:56.76#ibcon#about to read 5, iclass 10, count 0 2006.173.14:09:56.76#ibcon#read 5, iclass 10, count 0 2006.173.14:09:56.76#ibcon#about to read 6, iclass 10, count 0 2006.173.14:09:56.76#ibcon#read 6, iclass 10, count 0 2006.173.14:09:56.76#ibcon#end of sib2, iclass 10, count 0 2006.173.14:09:56.76#ibcon#*mode == 0, iclass 10, count 0 2006.173.14:09:56.76#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.14:09:56.77#ibcon#[27=USB\r\n] 2006.173.14:09:56.77#ibcon#*before write, iclass 10, count 0 2006.173.14:09:56.77#ibcon#enter sib2, iclass 10, count 0 2006.173.14:09:56.77#ibcon#flushed, iclass 10, count 0 2006.173.14:09:56.77#ibcon#about to write, iclass 10, count 0 2006.173.14:09:56.77#ibcon#wrote, iclass 10, count 0 2006.173.14:09:56.77#ibcon#about to read 3, iclass 10, count 0 2006.173.14:09:56.79#ibcon#read 3, iclass 10, count 0 2006.173.14:09:56.79#ibcon#about to read 4, iclass 10, count 0 2006.173.14:09:56.79#ibcon#read 4, iclass 10, count 0 2006.173.14:09:56.79#ibcon#about to read 5, iclass 10, count 0 2006.173.14:09:56.79#ibcon#read 5, iclass 10, count 0 2006.173.14:09:56.79#ibcon#about to read 6, iclass 10, count 0 2006.173.14:09:56.79#ibcon#read 6, iclass 10, count 0 2006.173.14:09:56.79#ibcon#end of sib2, iclass 10, count 0 2006.173.14:09:56.79#ibcon#*after write, iclass 10, count 0 2006.173.14:09:56.79#ibcon#*before return 0, iclass 10, count 0 2006.173.14:09:56.80#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.14:09:56.80#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.14:09:56.80#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.14:09:56.80#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.14:09:56.80$vck44/vblo=4,679.99 2006.173.14:09:56.80#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.14:09:56.80#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.14:09:56.80#ibcon#ireg 17 cls_cnt 0 2006.173.14:09:56.80#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.14:09:56.80#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.14:09:56.80#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.14:09:56.80#ibcon#enter wrdev, iclass 12, count 0 2006.173.14:09:56.80#ibcon#first serial, iclass 12, count 0 2006.173.14:09:56.80#ibcon#enter sib2, iclass 12, count 0 2006.173.14:09:56.80#ibcon#flushed, iclass 12, count 0 2006.173.14:09:56.80#ibcon#about to write, iclass 12, count 0 2006.173.14:09:56.80#ibcon#wrote, iclass 12, count 0 2006.173.14:09:56.80#ibcon#about to read 3, iclass 12, count 0 2006.173.14:09:56.81#ibcon#read 3, iclass 12, count 0 2006.173.14:09:56.81#ibcon#about to read 4, iclass 12, count 0 2006.173.14:09:56.81#ibcon#read 4, iclass 12, count 0 2006.173.14:09:56.81#ibcon#about to read 5, iclass 12, count 0 2006.173.14:09:56.81#ibcon#read 5, iclass 12, count 0 2006.173.14:09:56.81#ibcon#about to read 6, iclass 12, count 0 2006.173.14:09:56.81#ibcon#read 6, iclass 12, count 0 2006.173.14:09:56.81#ibcon#end of sib2, iclass 12, count 0 2006.173.14:09:56.81#ibcon#*mode == 0, iclass 12, count 0 2006.173.14:09:56.81#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.14:09:56.81#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.14:09:56.82#ibcon#*before write, iclass 12, count 0 2006.173.14:09:56.82#ibcon#enter sib2, iclass 12, count 0 2006.173.14:09:56.82#ibcon#flushed, iclass 12, count 0 2006.173.14:09:56.82#ibcon#about to write, iclass 12, count 0 2006.173.14:09:56.82#ibcon#wrote, iclass 12, count 0 2006.173.14:09:56.82#ibcon#about to read 3, iclass 12, count 0 2006.173.14:09:56.85#ibcon#read 3, iclass 12, count 0 2006.173.14:09:56.85#ibcon#about to read 4, iclass 12, count 0 2006.173.14:09:56.85#ibcon#read 4, iclass 12, count 0 2006.173.14:09:56.85#ibcon#about to read 5, iclass 12, count 0 2006.173.14:09:56.85#ibcon#read 5, iclass 12, count 0 2006.173.14:09:56.85#ibcon#about to read 6, iclass 12, count 0 2006.173.14:09:56.85#ibcon#read 6, iclass 12, count 0 2006.173.14:09:56.85#ibcon#end of sib2, iclass 12, count 0 2006.173.14:09:56.85#ibcon#*after write, iclass 12, count 0 2006.173.14:09:56.85#ibcon#*before return 0, iclass 12, count 0 2006.173.14:09:56.85#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.14:09:56.86#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.14:09:56.86#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.14:09:56.86#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.14:09:56.86$vck44/vb=4,4 2006.173.14:09:56.86#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.14:09:56.86#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.14:09:56.86#ibcon#ireg 11 cls_cnt 2 2006.173.14:09:56.86#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.14:09:56.91#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.14:09:56.91#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.14:09:56.91#ibcon#enter wrdev, iclass 14, count 2 2006.173.14:09:56.91#ibcon#first serial, iclass 14, count 2 2006.173.14:09:56.91#ibcon#enter sib2, iclass 14, count 2 2006.173.14:09:56.91#ibcon#flushed, iclass 14, count 2 2006.173.14:09:56.91#ibcon#about to write, iclass 14, count 2 2006.173.14:09:56.91#ibcon#wrote, iclass 14, count 2 2006.173.14:09:56.91#ibcon#about to read 3, iclass 14, count 2 2006.173.14:09:56.93#ibcon#read 3, iclass 14, count 2 2006.173.14:09:56.93#ibcon#about to read 4, iclass 14, count 2 2006.173.14:09:56.93#ibcon#read 4, iclass 14, count 2 2006.173.14:09:56.93#ibcon#about to read 5, iclass 14, count 2 2006.173.14:09:56.93#ibcon#read 5, iclass 14, count 2 2006.173.14:09:56.93#ibcon#about to read 6, iclass 14, count 2 2006.173.14:09:56.93#ibcon#read 6, iclass 14, count 2 2006.173.14:09:56.93#ibcon#end of sib2, iclass 14, count 2 2006.173.14:09:56.93#ibcon#*mode == 0, iclass 14, count 2 2006.173.14:09:56.93#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.14:09:56.93#ibcon#[27=AT04-04\r\n] 2006.173.14:09:56.93#ibcon#*before write, iclass 14, count 2 2006.173.14:09:56.93#ibcon#enter sib2, iclass 14, count 2 2006.173.14:09:56.93#ibcon#flushed, iclass 14, count 2 2006.173.14:09:56.93#ibcon#about to write, iclass 14, count 2 2006.173.14:09:56.94#ibcon#wrote, iclass 14, count 2 2006.173.14:09:56.94#ibcon#about to read 3, iclass 14, count 2 2006.173.14:09:56.96#ibcon#read 3, iclass 14, count 2 2006.173.14:09:56.96#ibcon#about to read 4, iclass 14, count 2 2006.173.14:09:56.96#ibcon#read 4, iclass 14, count 2 2006.173.14:09:56.96#ibcon#about to read 5, iclass 14, count 2 2006.173.14:09:56.96#ibcon#read 5, iclass 14, count 2 2006.173.14:09:56.96#ibcon#about to read 6, iclass 14, count 2 2006.173.14:09:56.96#ibcon#read 6, iclass 14, count 2 2006.173.14:09:56.96#ibcon#end of sib2, iclass 14, count 2 2006.173.14:09:56.96#ibcon#*after write, iclass 14, count 2 2006.173.14:09:56.96#ibcon#*before return 0, iclass 14, count 2 2006.173.14:09:56.97#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.14:09:56.97#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.14:09:56.97#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.14:09:56.97#ibcon#ireg 7 cls_cnt 0 2006.173.14:09:56.97#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.14:09:57.08#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.14:09:57.08#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.14:09:57.08#ibcon#enter wrdev, iclass 14, count 0 2006.173.14:09:57.08#ibcon#first serial, iclass 14, count 0 2006.173.14:09:57.08#ibcon#enter sib2, iclass 14, count 0 2006.173.14:09:57.08#ibcon#flushed, iclass 14, count 0 2006.173.14:09:57.08#ibcon#about to write, iclass 14, count 0 2006.173.14:09:57.08#ibcon#wrote, iclass 14, count 0 2006.173.14:09:57.08#ibcon#about to read 3, iclass 14, count 0 2006.173.14:09:57.10#ibcon#read 3, iclass 14, count 0 2006.173.14:09:57.10#ibcon#about to read 4, iclass 14, count 0 2006.173.14:09:57.10#ibcon#read 4, iclass 14, count 0 2006.173.14:09:57.10#ibcon#about to read 5, iclass 14, count 0 2006.173.14:09:57.10#ibcon#read 5, iclass 14, count 0 2006.173.14:09:57.10#ibcon#about to read 6, iclass 14, count 0 2006.173.14:09:57.10#ibcon#read 6, iclass 14, count 0 2006.173.14:09:57.10#ibcon#end of sib2, iclass 14, count 0 2006.173.14:09:57.10#ibcon#*mode == 0, iclass 14, count 0 2006.173.14:09:57.10#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.14:09:57.10#ibcon#[27=USB\r\n] 2006.173.14:09:57.10#ibcon#*before write, iclass 14, count 0 2006.173.14:09:57.10#ibcon#enter sib2, iclass 14, count 0 2006.173.14:09:57.10#ibcon#flushed, iclass 14, count 0 2006.173.14:09:57.11#ibcon#about to write, iclass 14, count 0 2006.173.14:09:57.11#ibcon#wrote, iclass 14, count 0 2006.173.14:09:57.11#ibcon#about to read 3, iclass 14, count 0 2006.173.14:09:57.14#ibcon#read 3, iclass 14, count 0 2006.173.14:09:57.14#ibcon#about to read 4, iclass 14, count 0 2006.173.14:09:57.14#ibcon#read 4, iclass 14, count 0 2006.173.14:09:57.14#ibcon#about to read 5, iclass 14, count 0 2006.173.14:09:57.14#ibcon#read 5, iclass 14, count 0 2006.173.14:09:57.14#ibcon#about to read 6, iclass 14, count 0 2006.173.14:09:57.14#ibcon#read 6, iclass 14, count 0 2006.173.14:09:57.14#ibcon#end of sib2, iclass 14, count 0 2006.173.14:09:57.14#ibcon#*after write, iclass 14, count 0 2006.173.14:09:57.14#ibcon#*before return 0, iclass 14, count 0 2006.173.14:09:57.14#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.14:09:57.14#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.14:09:57.14#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.14:09:57.14#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.14:09:57.14$vck44/vblo=5,709.99 2006.173.14:09:57.14#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.14:09:57.14#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.14:09:57.14#ibcon#ireg 17 cls_cnt 0 2006.173.14:09:57.14#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.14:09:57.14#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.14:09:57.14#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.14:09:57.14#ibcon#enter wrdev, iclass 16, count 0 2006.173.14:09:57.14#ibcon#first serial, iclass 16, count 0 2006.173.14:09:57.14#ibcon#enter sib2, iclass 16, count 0 2006.173.14:09:57.14#ibcon#flushed, iclass 16, count 0 2006.173.14:09:57.14#ibcon#about to write, iclass 16, count 0 2006.173.14:09:57.14#ibcon#wrote, iclass 16, count 0 2006.173.14:09:57.14#ibcon#about to read 3, iclass 16, count 0 2006.173.14:09:57.15#ibcon#read 3, iclass 16, count 0 2006.173.14:09:57.15#ibcon#about to read 4, iclass 16, count 0 2006.173.14:09:57.15#ibcon#read 4, iclass 16, count 0 2006.173.14:09:57.15#ibcon#about to read 5, iclass 16, count 0 2006.173.14:09:57.15#ibcon#read 5, iclass 16, count 0 2006.173.14:09:57.15#ibcon#about to read 6, iclass 16, count 0 2006.173.14:09:57.15#ibcon#read 6, iclass 16, count 0 2006.173.14:09:57.15#ibcon#end of sib2, iclass 16, count 0 2006.173.14:09:57.15#ibcon#*mode == 0, iclass 16, count 0 2006.173.14:09:57.15#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.14:09:57.15#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.14:09:57.15#ibcon#*before write, iclass 16, count 0 2006.173.14:09:57.15#ibcon#enter sib2, iclass 16, count 0 2006.173.14:09:57.15#ibcon#flushed, iclass 16, count 0 2006.173.14:09:57.15#ibcon#about to write, iclass 16, count 0 2006.173.14:09:57.16#ibcon#wrote, iclass 16, count 0 2006.173.14:09:57.16#ibcon#about to read 3, iclass 16, count 0 2006.173.14:09:57.19#ibcon#read 3, iclass 16, count 0 2006.173.14:09:57.19#ibcon#about to read 4, iclass 16, count 0 2006.173.14:09:57.19#ibcon#read 4, iclass 16, count 0 2006.173.14:09:57.19#ibcon#about to read 5, iclass 16, count 0 2006.173.14:09:57.19#ibcon#read 5, iclass 16, count 0 2006.173.14:09:57.19#ibcon#about to read 6, iclass 16, count 0 2006.173.14:09:57.19#ibcon#read 6, iclass 16, count 0 2006.173.14:09:57.19#ibcon#end of sib2, iclass 16, count 0 2006.173.14:09:57.19#ibcon#*after write, iclass 16, count 0 2006.173.14:09:57.19#ibcon#*before return 0, iclass 16, count 0 2006.173.14:09:57.19#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.14:09:57.19#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.14:09:57.20#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.14:09:57.20#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.14:09:57.20$vck44/vb=5,4 2006.173.14:09:57.20#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.14:09:57.20#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.14:09:57.20#ibcon#ireg 11 cls_cnt 2 2006.173.14:09:57.20#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.14:09:57.25#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.14:09:57.25#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.14:09:57.25#ibcon#enter wrdev, iclass 18, count 2 2006.173.14:09:57.25#ibcon#first serial, iclass 18, count 2 2006.173.14:09:57.25#ibcon#enter sib2, iclass 18, count 2 2006.173.14:09:57.25#ibcon#flushed, iclass 18, count 2 2006.173.14:09:57.25#ibcon#about to write, iclass 18, count 2 2006.173.14:09:57.25#ibcon#wrote, iclass 18, count 2 2006.173.14:09:57.25#ibcon#about to read 3, iclass 18, count 2 2006.173.14:09:57.27#ibcon#read 3, iclass 18, count 2 2006.173.14:09:57.27#ibcon#about to read 4, iclass 18, count 2 2006.173.14:09:57.27#ibcon#read 4, iclass 18, count 2 2006.173.14:09:57.27#ibcon#about to read 5, iclass 18, count 2 2006.173.14:09:57.27#ibcon#read 5, iclass 18, count 2 2006.173.14:09:57.27#ibcon#about to read 6, iclass 18, count 2 2006.173.14:09:57.27#ibcon#read 6, iclass 18, count 2 2006.173.14:09:57.27#ibcon#end of sib2, iclass 18, count 2 2006.173.14:09:57.27#ibcon#*mode == 0, iclass 18, count 2 2006.173.14:09:57.27#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.14:09:57.27#ibcon#[27=AT05-04\r\n] 2006.173.14:09:57.27#ibcon#*before write, iclass 18, count 2 2006.173.14:09:57.27#ibcon#enter sib2, iclass 18, count 2 2006.173.14:09:57.27#ibcon#flushed, iclass 18, count 2 2006.173.14:09:57.28#ibcon#about to write, iclass 18, count 2 2006.173.14:09:57.28#ibcon#wrote, iclass 18, count 2 2006.173.14:09:57.28#ibcon#about to read 3, iclass 18, count 2 2006.173.14:09:57.30#ibcon#read 3, iclass 18, count 2 2006.173.14:09:57.30#ibcon#about to read 4, iclass 18, count 2 2006.173.14:09:57.30#ibcon#read 4, iclass 18, count 2 2006.173.14:09:57.30#ibcon#about to read 5, iclass 18, count 2 2006.173.14:09:57.30#ibcon#read 5, iclass 18, count 2 2006.173.14:09:57.30#ibcon#about to read 6, iclass 18, count 2 2006.173.14:09:57.30#ibcon#read 6, iclass 18, count 2 2006.173.14:09:57.30#ibcon#end of sib2, iclass 18, count 2 2006.173.14:09:57.30#ibcon#*after write, iclass 18, count 2 2006.173.14:09:57.30#ibcon#*before return 0, iclass 18, count 2 2006.173.14:09:57.30#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.14:09:57.30#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.14:09:57.30#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.14:09:57.31#ibcon#ireg 7 cls_cnt 0 2006.173.14:09:57.31#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.14:09:57.41#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.14:09:57.41#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.14:09:57.41#ibcon#enter wrdev, iclass 18, count 0 2006.173.14:09:57.41#ibcon#first serial, iclass 18, count 0 2006.173.14:09:57.41#ibcon#enter sib2, iclass 18, count 0 2006.173.14:09:57.41#ibcon#flushed, iclass 18, count 0 2006.173.14:09:57.41#ibcon#about to write, iclass 18, count 0 2006.173.14:09:57.41#ibcon#wrote, iclass 18, count 0 2006.173.14:09:57.41#ibcon#about to read 3, iclass 18, count 0 2006.173.14:09:57.43#ibcon#read 3, iclass 18, count 0 2006.173.14:09:57.43#ibcon#about to read 4, iclass 18, count 0 2006.173.14:09:57.43#ibcon#read 4, iclass 18, count 0 2006.173.14:09:57.43#ibcon#about to read 5, iclass 18, count 0 2006.173.14:09:57.43#ibcon#read 5, iclass 18, count 0 2006.173.14:09:57.43#ibcon#about to read 6, iclass 18, count 0 2006.173.14:09:57.43#ibcon#read 6, iclass 18, count 0 2006.173.14:09:57.43#ibcon#end of sib2, iclass 18, count 0 2006.173.14:09:57.43#ibcon#*mode == 0, iclass 18, count 0 2006.173.14:09:57.43#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.14:09:57.44#ibcon#[27=USB\r\n] 2006.173.14:09:57.44#ibcon#*before write, iclass 18, count 0 2006.173.14:09:57.44#ibcon#enter sib2, iclass 18, count 0 2006.173.14:09:57.44#ibcon#flushed, iclass 18, count 0 2006.173.14:09:57.44#ibcon#about to write, iclass 18, count 0 2006.173.14:09:57.44#ibcon#wrote, iclass 18, count 0 2006.173.14:09:57.44#ibcon#about to read 3, iclass 18, count 0 2006.173.14:09:57.46#ibcon#read 3, iclass 18, count 0 2006.173.14:09:57.46#ibcon#about to read 4, iclass 18, count 0 2006.173.14:09:57.46#ibcon#read 4, iclass 18, count 0 2006.173.14:09:57.46#ibcon#about to read 5, iclass 18, count 0 2006.173.14:09:57.46#ibcon#read 5, iclass 18, count 0 2006.173.14:09:57.46#ibcon#about to read 6, iclass 18, count 0 2006.173.14:09:57.46#ibcon#read 6, iclass 18, count 0 2006.173.14:09:57.46#ibcon#end of sib2, iclass 18, count 0 2006.173.14:09:57.46#ibcon#*after write, iclass 18, count 0 2006.173.14:09:57.46#ibcon#*before return 0, iclass 18, count 0 2006.173.14:09:57.46#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.14:09:57.46#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.14:09:57.46#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.14:09:57.47#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.14:09:57.47$vck44/vblo=6,719.99 2006.173.14:09:57.47#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.14:09:57.47#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.14:09:57.47#ibcon#ireg 17 cls_cnt 0 2006.173.14:09:57.47#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.14:09:57.47#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.14:09:57.47#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.14:09:57.47#ibcon#enter wrdev, iclass 20, count 0 2006.173.14:09:57.47#ibcon#first serial, iclass 20, count 0 2006.173.14:09:57.47#ibcon#enter sib2, iclass 20, count 0 2006.173.14:09:57.47#ibcon#flushed, iclass 20, count 0 2006.173.14:09:57.47#ibcon#about to write, iclass 20, count 0 2006.173.14:09:57.47#ibcon#wrote, iclass 20, count 0 2006.173.14:09:57.47#ibcon#about to read 3, iclass 20, count 0 2006.173.14:09:57.48#ibcon#read 3, iclass 20, count 0 2006.173.14:09:57.48#ibcon#about to read 4, iclass 20, count 0 2006.173.14:09:57.48#ibcon#read 4, iclass 20, count 0 2006.173.14:09:57.48#ibcon#about to read 5, iclass 20, count 0 2006.173.14:09:57.48#ibcon#read 5, iclass 20, count 0 2006.173.14:09:57.48#ibcon#about to read 6, iclass 20, count 0 2006.173.14:09:57.48#ibcon#read 6, iclass 20, count 0 2006.173.14:09:57.48#ibcon#end of sib2, iclass 20, count 0 2006.173.14:09:57.48#ibcon#*mode == 0, iclass 20, count 0 2006.173.14:09:57.48#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.14:09:57.48#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.14:09:57.48#ibcon#*before write, iclass 20, count 0 2006.173.14:09:57.48#ibcon#enter sib2, iclass 20, count 0 2006.173.14:09:57.48#ibcon#flushed, iclass 20, count 0 2006.173.14:09:57.48#ibcon#about to write, iclass 20, count 0 2006.173.14:09:57.49#ibcon#wrote, iclass 20, count 0 2006.173.14:09:57.49#ibcon#about to read 3, iclass 20, count 0 2006.173.14:09:57.52#ibcon#read 3, iclass 20, count 0 2006.173.14:09:57.52#ibcon#about to read 4, iclass 20, count 0 2006.173.14:09:57.52#ibcon#read 4, iclass 20, count 0 2006.173.14:09:57.52#ibcon#about to read 5, iclass 20, count 0 2006.173.14:09:57.52#ibcon#read 5, iclass 20, count 0 2006.173.14:09:57.52#ibcon#about to read 6, iclass 20, count 0 2006.173.14:09:57.52#ibcon#read 6, iclass 20, count 0 2006.173.14:09:57.52#ibcon#end of sib2, iclass 20, count 0 2006.173.14:09:57.52#ibcon#*after write, iclass 20, count 0 2006.173.14:09:57.52#ibcon#*before return 0, iclass 20, count 0 2006.173.14:09:57.52#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.14:09:57.52#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.14:09:57.53#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.14:09:57.53#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.14:09:57.53$vck44/vb=6,4 2006.173.14:09:57.53#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.14:09:57.53#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.14:09:57.53#ibcon#ireg 11 cls_cnt 2 2006.173.14:09:57.53#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.14:09:57.57#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.14:09:57.57#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.14:09:57.57#ibcon#enter wrdev, iclass 22, count 2 2006.173.14:09:57.57#ibcon#first serial, iclass 22, count 2 2006.173.14:09:57.57#ibcon#enter sib2, iclass 22, count 2 2006.173.14:09:57.57#ibcon#flushed, iclass 22, count 2 2006.173.14:09:57.57#ibcon#about to write, iclass 22, count 2 2006.173.14:09:57.57#ibcon#wrote, iclass 22, count 2 2006.173.14:09:57.57#ibcon#about to read 3, iclass 22, count 2 2006.173.14:09:57.59#ibcon#read 3, iclass 22, count 2 2006.173.14:09:57.59#ibcon#about to read 4, iclass 22, count 2 2006.173.14:09:57.59#ibcon#read 4, iclass 22, count 2 2006.173.14:09:57.59#ibcon#about to read 5, iclass 22, count 2 2006.173.14:09:57.59#ibcon#read 5, iclass 22, count 2 2006.173.14:09:57.59#ibcon#about to read 6, iclass 22, count 2 2006.173.14:09:57.59#ibcon#read 6, iclass 22, count 2 2006.173.14:09:57.59#ibcon#end of sib2, iclass 22, count 2 2006.173.14:09:57.59#ibcon#*mode == 0, iclass 22, count 2 2006.173.14:09:57.59#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.14:09:57.60#ibcon#[27=AT06-04\r\n] 2006.173.14:09:57.60#ibcon#*before write, iclass 22, count 2 2006.173.14:09:57.60#ibcon#enter sib2, iclass 22, count 2 2006.173.14:09:57.60#ibcon#flushed, iclass 22, count 2 2006.173.14:09:57.60#ibcon#about to write, iclass 22, count 2 2006.173.14:09:57.60#ibcon#wrote, iclass 22, count 2 2006.173.14:09:57.60#ibcon#about to read 3, iclass 22, count 2 2006.173.14:09:57.62#ibcon#read 3, iclass 22, count 2 2006.173.14:09:57.62#ibcon#about to read 4, iclass 22, count 2 2006.173.14:09:57.62#ibcon#read 4, iclass 22, count 2 2006.173.14:09:57.62#ibcon#about to read 5, iclass 22, count 2 2006.173.14:09:57.62#ibcon#read 5, iclass 22, count 2 2006.173.14:09:57.62#ibcon#about to read 6, iclass 22, count 2 2006.173.14:09:57.62#ibcon#read 6, iclass 22, count 2 2006.173.14:09:57.62#ibcon#end of sib2, iclass 22, count 2 2006.173.14:09:57.62#ibcon#*after write, iclass 22, count 2 2006.173.14:09:57.62#ibcon#*before return 0, iclass 22, count 2 2006.173.14:09:57.62#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.14:09:57.63#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.14:09:57.63#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.14:09:57.63#ibcon#ireg 7 cls_cnt 0 2006.173.14:09:57.63#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.14:09:57.73#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.14:09:57.73#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.14:09:57.73#ibcon#enter wrdev, iclass 22, count 0 2006.173.14:09:57.73#ibcon#first serial, iclass 22, count 0 2006.173.14:09:57.73#ibcon#enter sib2, iclass 22, count 0 2006.173.14:09:57.73#ibcon#flushed, iclass 22, count 0 2006.173.14:09:57.73#ibcon#about to write, iclass 22, count 0 2006.173.14:09:57.73#ibcon#wrote, iclass 22, count 0 2006.173.14:09:57.73#ibcon#about to read 3, iclass 22, count 0 2006.173.14:09:57.75#ibcon#read 3, iclass 22, count 0 2006.173.14:09:57.75#ibcon#about to read 4, iclass 22, count 0 2006.173.14:09:57.75#ibcon#read 4, iclass 22, count 0 2006.173.14:09:57.75#ibcon#about to read 5, iclass 22, count 0 2006.173.14:09:57.75#ibcon#read 5, iclass 22, count 0 2006.173.14:09:57.75#ibcon#about to read 6, iclass 22, count 0 2006.173.14:09:57.75#ibcon#read 6, iclass 22, count 0 2006.173.14:09:57.75#ibcon#end of sib2, iclass 22, count 0 2006.173.14:09:57.75#ibcon#*mode == 0, iclass 22, count 0 2006.173.14:09:57.75#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.14:09:57.75#ibcon#[27=USB\r\n] 2006.173.14:09:57.75#ibcon#*before write, iclass 22, count 0 2006.173.14:09:57.75#ibcon#enter sib2, iclass 22, count 0 2006.173.14:09:57.75#ibcon#flushed, iclass 22, count 0 2006.173.14:09:57.75#ibcon#about to write, iclass 22, count 0 2006.173.14:09:57.76#ibcon#wrote, iclass 22, count 0 2006.173.14:09:57.76#ibcon#about to read 3, iclass 22, count 0 2006.173.14:09:57.78#ibcon#read 3, iclass 22, count 0 2006.173.14:09:57.78#ibcon#about to read 4, iclass 22, count 0 2006.173.14:09:57.78#ibcon#read 4, iclass 22, count 0 2006.173.14:09:57.78#ibcon#about to read 5, iclass 22, count 0 2006.173.14:09:57.78#ibcon#read 5, iclass 22, count 0 2006.173.14:09:57.78#ibcon#about to read 6, iclass 22, count 0 2006.173.14:09:57.78#ibcon#read 6, iclass 22, count 0 2006.173.14:09:57.78#ibcon#end of sib2, iclass 22, count 0 2006.173.14:09:57.78#ibcon#*after write, iclass 22, count 0 2006.173.14:09:57.78#ibcon#*before return 0, iclass 22, count 0 2006.173.14:09:57.79#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.14:09:57.79#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.14:09:57.79#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.14:09:57.79#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.14:09:57.79$vck44/vblo=7,734.99 2006.173.14:09:57.79#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.14:09:57.79#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.14:09:57.79#ibcon#ireg 17 cls_cnt 0 2006.173.14:09:57.79#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.14:09:57.79#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.14:09:57.79#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.14:09:57.79#ibcon#enter wrdev, iclass 24, count 0 2006.173.14:09:57.79#ibcon#first serial, iclass 24, count 0 2006.173.14:09:57.79#ibcon#enter sib2, iclass 24, count 0 2006.173.14:09:57.79#ibcon#flushed, iclass 24, count 0 2006.173.14:09:57.79#ibcon#about to write, iclass 24, count 0 2006.173.14:09:57.79#ibcon#wrote, iclass 24, count 0 2006.173.14:09:57.79#ibcon#about to read 3, iclass 24, count 0 2006.173.14:09:57.80#ibcon#read 3, iclass 24, count 0 2006.173.14:09:57.80#ibcon#about to read 4, iclass 24, count 0 2006.173.14:09:57.80#ibcon#read 4, iclass 24, count 0 2006.173.14:09:57.80#ibcon#about to read 5, iclass 24, count 0 2006.173.14:09:57.80#ibcon#read 5, iclass 24, count 0 2006.173.14:09:57.80#ibcon#about to read 6, iclass 24, count 0 2006.173.14:09:57.80#ibcon#read 6, iclass 24, count 0 2006.173.14:09:57.80#ibcon#end of sib2, iclass 24, count 0 2006.173.14:09:57.80#ibcon#*mode == 0, iclass 24, count 0 2006.173.14:09:57.80#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.14:09:57.81#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.14:09:57.81#ibcon#*before write, iclass 24, count 0 2006.173.14:09:57.81#ibcon#enter sib2, iclass 24, count 0 2006.173.14:09:57.81#ibcon#flushed, iclass 24, count 0 2006.173.14:09:57.81#ibcon#about to write, iclass 24, count 0 2006.173.14:09:57.81#ibcon#wrote, iclass 24, count 0 2006.173.14:09:57.81#ibcon#about to read 3, iclass 24, count 0 2006.173.14:09:57.84#ibcon#read 3, iclass 24, count 0 2006.173.14:09:57.84#ibcon#about to read 4, iclass 24, count 0 2006.173.14:09:57.84#ibcon#read 4, iclass 24, count 0 2006.173.14:09:57.84#ibcon#about to read 5, iclass 24, count 0 2006.173.14:09:57.85#ibcon#read 5, iclass 24, count 0 2006.173.14:09:57.85#ibcon#about to read 6, iclass 24, count 0 2006.173.14:09:57.85#ibcon#read 6, iclass 24, count 0 2006.173.14:09:57.85#ibcon#end of sib2, iclass 24, count 0 2006.173.14:09:57.85#ibcon#*after write, iclass 24, count 0 2006.173.14:09:57.85#ibcon#*before return 0, iclass 24, count 0 2006.173.14:09:57.85#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.14:09:57.85#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.14:09:57.85#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.14:09:57.85#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.14:09:57.85$vck44/vb=7,4 2006.173.14:09:57.85#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.14:09:57.85#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.14:09:57.85#ibcon#ireg 11 cls_cnt 2 2006.173.14:09:57.85#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.14:09:57.90#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.14:09:57.90#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.14:09:57.90#ibcon#enter wrdev, iclass 26, count 2 2006.173.14:09:57.90#ibcon#first serial, iclass 26, count 2 2006.173.14:09:57.90#ibcon#enter sib2, iclass 26, count 2 2006.173.14:09:57.90#ibcon#flushed, iclass 26, count 2 2006.173.14:09:57.90#ibcon#about to write, iclass 26, count 2 2006.173.14:09:57.90#ibcon#wrote, iclass 26, count 2 2006.173.14:09:57.90#ibcon#about to read 3, iclass 26, count 2 2006.173.14:09:57.92#ibcon#read 3, iclass 26, count 2 2006.173.14:09:57.92#ibcon#about to read 4, iclass 26, count 2 2006.173.14:09:57.92#ibcon#read 4, iclass 26, count 2 2006.173.14:09:57.92#ibcon#about to read 5, iclass 26, count 2 2006.173.14:09:57.92#ibcon#read 5, iclass 26, count 2 2006.173.14:09:57.92#ibcon#about to read 6, iclass 26, count 2 2006.173.14:09:57.92#ibcon#read 6, iclass 26, count 2 2006.173.14:09:57.92#ibcon#end of sib2, iclass 26, count 2 2006.173.14:09:57.92#ibcon#*mode == 0, iclass 26, count 2 2006.173.14:09:57.92#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.14:09:57.92#ibcon#[27=AT07-04\r\n] 2006.173.14:09:57.93#ibcon#*before write, iclass 26, count 2 2006.173.14:09:57.93#ibcon#enter sib2, iclass 26, count 2 2006.173.14:09:57.93#ibcon#flushed, iclass 26, count 2 2006.173.14:09:57.93#ibcon#about to write, iclass 26, count 2 2006.173.14:09:57.93#ibcon#wrote, iclass 26, count 2 2006.173.14:09:57.93#ibcon#about to read 3, iclass 26, count 2 2006.173.14:09:57.95#ibcon#read 3, iclass 26, count 2 2006.173.14:09:57.95#ibcon#about to read 4, iclass 26, count 2 2006.173.14:09:57.95#ibcon#read 4, iclass 26, count 2 2006.173.14:09:57.95#ibcon#about to read 5, iclass 26, count 2 2006.173.14:09:57.95#ibcon#read 5, iclass 26, count 2 2006.173.14:09:57.95#ibcon#about to read 6, iclass 26, count 2 2006.173.14:09:57.95#ibcon#read 6, iclass 26, count 2 2006.173.14:09:57.95#ibcon#end of sib2, iclass 26, count 2 2006.173.14:09:57.95#ibcon#*after write, iclass 26, count 2 2006.173.14:09:57.95#ibcon#*before return 0, iclass 26, count 2 2006.173.14:09:57.95#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.14:09:57.96#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.14:09:57.96#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.14:09:57.96#ibcon#ireg 7 cls_cnt 0 2006.173.14:09:57.96#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.14:09:58.06#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.14:09:58.06#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.14:09:58.06#ibcon#enter wrdev, iclass 26, count 0 2006.173.14:09:58.06#ibcon#first serial, iclass 26, count 0 2006.173.14:09:58.06#ibcon#enter sib2, iclass 26, count 0 2006.173.14:09:58.06#ibcon#flushed, iclass 26, count 0 2006.173.14:09:58.06#ibcon#about to write, iclass 26, count 0 2006.173.14:09:58.06#ibcon#wrote, iclass 26, count 0 2006.173.14:09:58.06#ibcon#about to read 3, iclass 26, count 0 2006.173.14:09:58.08#ibcon#read 3, iclass 26, count 0 2006.173.14:09:58.08#ibcon#about to read 4, iclass 26, count 0 2006.173.14:09:58.08#ibcon#read 4, iclass 26, count 0 2006.173.14:09:58.08#ibcon#about to read 5, iclass 26, count 0 2006.173.14:09:58.08#ibcon#read 5, iclass 26, count 0 2006.173.14:09:58.08#ibcon#about to read 6, iclass 26, count 0 2006.173.14:09:58.08#ibcon#read 6, iclass 26, count 0 2006.173.14:09:58.08#ibcon#end of sib2, iclass 26, count 0 2006.173.14:09:58.08#ibcon#*mode == 0, iclass 26, count 0 2006.173.14:09:58.08#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.14:09:58.08#ibcon#[27=USB\r\n] 2006.173.14:09:58.09#ibcon#*before write, iclass 26, count 0 2006.173.14:09:58.09#ibcon#enter sib2, iclass 26, count 0 2006.173.14:09:58.09#ibcon#flushed, iclass 26, count 0 2006.173.14:09:58.09#ibcon#about to write, iclass 26, count 0 2006.173.14:09:58.09#ibcon#wrote, iclass 26, count 0 2006.173.14:09:58.09#ibcon#about to read 3, iclass 26, count 0 2006.173.14:09:58.11#ibcon#read 3, iclass 26, count 0 2006.173.14:09:58.11#ibcon#about to read 4, iclass 26, count 0 2006.173.14:09:58.11#ibcon#read 4, iclass 26, count 0 2006.173.14:09:58.11#ibcon#about to read 5, iclass 26, count 0 2006.173.14:09:58.11#ibcon#read 5, iclass 26, count 0 2006.173.14:09:58.11#ibcon#about to read 6, iclass 26, count 0 2006.173.14:09:58.11#ibcon#read 6, iclass 26, count 0 2006.173.14:09:58.11#ibcon#end of sib2, iclass 26, count 0 2006.173.14:09:58.11#ibcon#*after write, iclass 26, count 0 2006.173.14:09:58.11#ibcon#*before return 0, iclass 26, count 0 2006.173.14:09:58.11#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.14:09:58.12#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.14:09:58.12#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.14:09:58.12#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.14:09:58.12$vck44/vblo=8,744.99 2006.173.14:09:58.12#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.14:09:58.12#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.14:09:58.12#ibcon#ireg 17 cls_cnt 0 2006.173.14:09:58.12#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.14:09:58.12#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.14:09:58.12#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.14:09:58.12#ibcon#enter wrdev, iclass 28, count 0 2006.173.14:09:58.12#ibcon#first serial, iclass 28, count 0 2006.173.14:09:58.12#ibcon#enter sib2, iclass 28, count 0 2006.173.14:09:58.12#ibcon#flushed, iclass 28, count 0 2006.173.14:09:58.12#ibcon#about to write, iclass 28, count 0 2006.173.14:09:58.12#ibcon#wrote, iclass 28, count 0 2006.173.14:09:58.12#ibcon#about to read 3, iclass 28, count 0 2006.173.14:09:58.13#ibcon#read 3, iclass 28, count 0 2006.173.14:09:58.13#ibcon#about to read 4, iclass 28, count 0 2006.173.14:09:58.13#ibcon#read 4, iclass 28, count 0 2006.173.14:09:58.13#ibcon#about to read 5, iclass 28, count 0 2006.173.14:09:58.13#ibcon#read 5, iclass 28, count 0 2006.173.14:09:58.13#ibcon#about to read 6, iclass 28, count 0 2006.173.14:09:58.13#ibcon#read 6, iclass 28, count 0 2006.173.14:09:58.13#ibcon#end of sib2, iclass 28, count 0 2006.173.14:09:58.13#ibcon#*mode == 0, iclass 28, count 0 2006.173.14:09:58.13#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.14:09:58.13#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.14:09:58.14#ibcon#*before write, iclass 28, count 0 2006.173.14:09:58.14#ibcon#enter sib2, iclass 28, count 0 2006.173.14:09:58.14#ibcon#flushed, iclass 28, count 0 2006.173.14:09:58.14#ibcon#about to write, iclass 28, count 0 2006.173.14:09:58.14#ibcon#wrote, iclass 28, count 0 2006.173.14:09:58.14#ibcon#about to read 3, iclass 28, count 0 2006.173.14:09:58.17#ibcon#read 3, iclass 28, count 0 2006.173.14:09:58.17#ibcon#about to read 4, iclass 28, count 0 2006.173.14:09:58.17#ibcon#read 4, iclass 28, count 0 2006.173.14:09:58.17#ibcon#about to read 5, iclass 28, count 0 2006.173.14:09:58.17#ibcon#read 5, iclass 28, count 0 2006.173.14:09:58.17#ibcon#about to read 6, iclass 28, count 0 2006.173.14:09:58.17#ibcon#read 6, iclass 28, count 0 2006.173.14:09:58.17#ibcon#end of sib2, iclass 28, count 0 2006.173.14:09:58.17#ibcon#*after write, iclass 28, count 0 2006.173.14:09:58.17#ibcon#*before return 0, iclass 28, count 0 2006.173.14:09:58.17#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.14:09:58.18#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.14:09:58.18#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.14:09:58.18#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.14:09:58.18$vck44/vb=8,4 2006.173.14:09:58.18#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.14:09:58.18#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.14:09:58.18#ibcon#ireg 11 cls_cnt 2 2006.173.14:09:58.18#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.14:09:58.23#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.14:09:58.23#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.14:09:58.23#ibcon#enter wrdev, iclass 30, count 2 2006.173.14:09:58.23#ibcon#first serial, iclass 30, count 2 2006.173.14:09:58.23#ibcon#enter sib2, iclass 30, count 2 2006.173.14:09:58.23#ibcon#flushed, iclass 30, count 2 2006.173.14:09:58.23#ibcon#about to write, iclass 30, count 2 2006.173.14:09:58.23#ibcon#wrote, iclass 30, count 2 2006.173.14:09:58.23#ibcon#about to read 3, iclass 30, count 2 2006.173.14:09:58.25#ibcon#read 3, iclass 30, count 2 2006.173.14:09:58.25#ibcon#about to read 4, iclass 30, count 2 2006.173.14:09:58.25#ibcon#read 4, iclass 30, count 2 2006.173.14:09:58.25#ibcon#about to read 5, iclass 30, count 2 2006.173.14:09:58.25#ibcon#read 5, iclass 30, count 2 2006.173.14:09:58.25#ibcon#about to read 6, iclass 30, count 2 2006.173.14:09:58.25#ibcon#read 6, iclass 30, count 2 2006.173.14:09:58.25#ibcon#end of sib2, iclass 30, count 2 2006.173.14:09:58.25#ibcon#*mode == 0, iclass 30, count 2 2006.173.14:09:58.25#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.14:09:58.25#ibcon#[27=AT08-04\r\n] 2006.173.14:09:58.25#ibcon#*before write, iclass 30, count 2 2006.173.14:09:58.25#ibcon#enter sib2, iclass 30, count 2 2006.173.14:09:58.25#ibcon#flushed, iclass 30, count 2 2006.173.14:09:58.26#ibcon#about to write, iclass 30, count 2 2006.173.14:09:58.26#ibcon#wrote, iclass 30, count 2 2006.173.14:09:58.26#ibcon#about to read 3, iclass 30, count 2 2006.173.14:09:58.28#ibcon#read 3, iclass 30, count 2 2006.173.14:09:58.28#ibcon#about to read 4, iclass 30, count 2 2006.173.14:09:58.28#ibcon#read 4, iclass 30, count 2 2006.173.14:09:58.28#ibcon#about to read 5, iclass 30, count 2 2006.173.14:09:58.28#ibcon#read 5, iclass 30, count 2 2006.173.14:09:58.28#ibcon#about to read 6, iclass 30, count 2 2006.173.14:09:58.28#ibcon#read 6, iclass 30, count 2 2006.173.14:09:58.28#ibcon#end of sib2, iclass 30, count 2 2006.173.14:09:58.28#ibcon#*after write, iclass 30, count 2 2006.173.14:09:58.28#ibcon#*before return 0, iclass 30, count 2 2006.173.14:09:58.28#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.14:09:58.28#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.14:09:58.28#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.14:09:58.29#ibcon#ireg 7 cls_cnt 0 2006.173.14:09:58.29#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.14:09:58.39#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.14:09:58.39#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.14:09:58.39#ibcon#enter wrdev, iclass 30, count 0 2006.173.14:09:58.39#ibcon#first serial, iclass 30, count 0 2006.173.14:09:58.39#ibcon#enter sib2, iclass 30, count 0 2006.173.14:09:58.39#ibcon#flushed, iclass 30, count 0 2006.173.14:09:58.39#ibcon#about to write, iclass 30, count 0 2006.173.14:09:58.39#ibcon#wrote, iclass 30, count 0 2006.173.14:09:58.39#ibcon#about to read 3, iclass 30, count 0 2006.173.14:09:58.41#ibcon#read 3, iclass 30, count 0 2006.173.14:09:58.41#ibcon#about to read 4, iclass 30, count 0 2006.173.14:09:58.41#ibcon#read 4, iclass 30, count 0 2006.173.14:09:58.41#ibcon#about to read 5, iclass 30, count 0 2006.173.14:09:58.41#ibcon#read 5, iclass 30, count 0 2006.173.14:09:58.41#ibcon#about to read 6, iclass 30, count 0 2006.173.14:09:58.41#ibcon#read 6, iclass 30, count 0 2006.173.14:09:58.41#ibcon#end of sib2, iclass 30, count 0 2006.173.14:09:58.41#ibcon#*mode == 0, iclass 30, count 0 2006.173.14:09:58.41#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.14:09:58.41#ibcon#[27=USB\r\n] 2006.173.14:09:58.41#ibcon#*before write, iclass 30, count 0 2006.173.14:09:58.41#ibcon#enter sib2, iclass 30, count 0 2006.173.14:09:58.41#ibcon#flushed, iclass 30, count 0 2006.173.14:09:58.41#ibcon#about to write, iclass 30, count 0 2006.173.14:09:58.42#ibcon#wrote, iclass 30, count 0 2006.173.14:09:58.42#ibcon#about to read 3, iclass 30, count 0 2006.173.14:09:58.44#ibcon#read 3, iclass 30, count 0 2006.173.14:09:58.44#ibcon#about to read 4, iclass 30, count 0 2006.173.14:09:58.44#ibcon#read 4, iclass 30, count 0 2006.173.14:09:58.44#ibcon#about to read 5, iclass 30, count 0 2006.173.14:09:58.44#ibcon#read 5, iclass 30, count 0 2006.173.14:09:58.44#ibcon#about to read 6, iclass 30, count 0 2006.173.14:09:58.44#ibcon#read 6, iclass 30, count 0 2006.173.14:09:58.44#ibcon#end of sib2, iclass 30, count 0 2006.173.14:09:58.44#ibcon#*after write, iclass 30, count 0 2006.173.14:09:58.45#ibcon#*before return 0, iclass 30, count 0 2006.173.14:09:58.45#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.14:09:58.45#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.14:09:58.45#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.14:09:58.45#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.14:09:58.45$vck44/vabw=wide 2006.173.14:09:58.45#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.14:09:58.45#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.14:09:58.45#ibcon#ireg 8 cls_cnt 0 2006.173.14:09:58.45#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.14:09:58.45#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.14:09:58.45#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.14:09:58.45#ibcon#enter wrdev, iclass 32, count 0 2006.173.14:09:58.45#ibcon#first serial, iclass 32, count 0 2006.173.14:09:58.45#ibcon#enter sib2, iclass 32, count 0 2006.173.14:09:58.45#ibcon#flushed, iclass 32, count 0 2006.173.14:09:58.45#ibcon#about to write, iclass 32, count 0 2006.173.14:09:58.45#ibcon#wrote, iclass 32, count 0 2006.173.14:09:58.45#ibcon#about to read 3, iclass 32, count 0 2006.173.14:09:58.46#ibcon#read 3, iclass 32, count 0 2006.173.14:09:58.46#ibcon#about to read 4, iclass 32, count 0 2006.173.14:09:58.46#ibcon#read 4, iclass 32, count 0 2006.173.14:09:58.46#ibcon#about to read 5, iclass 32, count 0 2006.173.14:09:58.46#ibcon#read 5, iclass 32, count 0 2006.173.14:09:58.46#ibcon#about to read 6, iclass 32, count 0 2006.173.14:09:58.46#ibcon#read 6, iclass 32, count 0 2006.173.14:09:58.46#ibcon#end of sib2, iclass 32, count 0 2006.173.14:09:58.46#ibcon#*mode == 0, iclass 32, count 0 2006.173.14:09:58.46#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.14:09:58.46#ibcon#[25=BW32\r\n] 2006.173.14:09:58.46#ibcon#*before write, iclass 32, count 0 2006.173.14:09:58.47#ibcon#enter sib2, iclass 32, count 0 2006.173.14:09:58.47#ibcon#flushed, iclass 32, count 0 2006.173.14:09:58.47#ibcon#about to write, iclass 32, count 0 2006.173.14:09:58.47#ibcon#wrote, iclass 32, count 0 2006.173.14:09:58.47#ibcon#about to read 3, iclass 32, count 0 2006.173.14:09:58.49#ibcon#read 3, iclass 32, count 0 2006.173.14:09:58.49#ibcon#about to read 4, iclass 32, count 0 2006.173.14:09:58.49#ibcon#read 4, iclass 32, count 0 2006.173.14:09:58.49#ibcon#about to read 5, iclass 32, count 0 2006.173.14:09:58.49#ibcon#read 5, iclass 32, count 0 2006.173.14:09:58.49#ibcon#about to read 6, iclass 32, count 0 2006.173.14:09:58.49#ibcon#read 6, iclass 32, count 0 2006.173.14:09:58.49#ibcon#end of sib2, iclass 32, count 0 2006.173.14:09:58.49#ibcon#*after write, iclass 32, count 0 2006.173.14:09:58.49#ibcon#*before return 0, iclass 32, count 0 2006.173.14:09:58.49#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.14:09:58.49#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.14:09:58.49#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.14:09:58.50#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.14:09:58.50$vck44/vbbw=wide 2006.173.14:09:58.50#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.14:09:58.50#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.14:09:58.50#ibcon#ireg 8 cls_cnt 0 2006.173.14:09:58.50#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.14:09:58.56#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.14:09:58.56#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.14:09:58.56#ibcon#enter wrdev, iclass 34, count 0 2006.173.14:09:58.56#ibcon#first serial, iclass 34, count 0 2006.173.14:09:58.56#ibcon#enter sib2, iclass 34, count 0 2006.173.14:09:58.56#ibcon#flushed, iclass 34, count 0 2006.173.14:09:58.56#ibcon#about to write, iclass 34, count 0 2006.173.14:09:58.56#ibcon#wrote, iclass 34, count 0 2006.173.14:09:58.56#ibcon#about to read 3, iclass 34, count 0 2006.173.14:09:58.58#ibcon#read 3, iclass 34, count 0 2006.173.14:09:58.58#ibcon#about to read 4, iclass 34, count 0 2006.173.14:09:58.58#ibcon#read 4, iclass 34, count 0 2006.173.14:09:58.58#ibcon#about to read 5, iclass 34, count 0 2006.173.14:09:58.58#ibcon#read 5, iclass 34, count 0 2006.173.14:09:58.58#ibcon#about to read 6, iclass 34, count 0 2006.173.14:09:58.58#ibcon#read 6, iclass 34, count 0 2006.173.14:09:58.58#ibcon#end of sib2, iclass 34, count 0 2006.173.14:09:58.58#ibcon#*mode == 0, iclass 34, count 0 2006.173.14:09:58.58#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.14:09:58.58#ibcon#[27=BW32\r\n] 2006.173.14:09:58.58#ibcon#*before write, iclass 34, count 0 2006.173.14:09:58.58#ibcon#enter sib2, iclass 34, count 0 2006.173.14:09:58.58#ibcon#flushed, iclass 34, count 0 2006.173.14:09:58.58#ibcon#about to write, iclass 34, count 0 2006.173.14:09:58.59#ibcon#wrote, iclass 34, count 0 2006.173.14:09:58.59#ibcon#about to read 3, iclass 34, count 0 2006.173.14:09:58.61#ibcon#read 3, iclass 34, count 0 2006.173.14:09:58.61#ibcon#about to read 4, iclass 34, count 0 2006.173.14:09:58.61#ibcon#read 4, iclass 34, count 0 2006.173.14:09:58.61#ibcon#about to read 5, iclass 34, count 0 2006.173.14:09:58.61#ibcon#read 5, iclass 34, count 0 2006.173.14:09:58.61#ibcon#about to read 6, iclass 34, count 0 2006.173.14:09:58.61#ibcon#read 6, iclass 34, count 0 2006.173.14:09:58.61#ibcon#end of sib2, iclass 34, count 0 2006.173.14:09:58.61#ibcon#*after write, iclass 34, count 0 2006.173.14:09:58.61#ibcon#*before return 0, iclass 34, count 0 2006.173.14:09:58.61#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.14:09:58.62#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.14:09:58.62#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.14:09:58.62#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.14:09:58.62$setupk4/ifdk4 2006.173.14:09:58.62$ifdk4/lo= 2006.173.14:09:58.62$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.14:09:58.62$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.14:09:58.62$ifdk4/patch= 2006.173.14:09:58.62$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.14:09:58.62$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.14:09:58.62$setupk4/!*+20s 2006.173.14:10:02.58#abcon#<5=/03 0.5 1.1 21.691001003.6\r\n> 2006.173.14:10:02.60#abcon#{5=INTERFACE CLEAR} 2006.173.14:10:02.66#abcon#[5=S1D000X0/0*\r\n] 2006.173.14:10:12.75#abcon#<5=/03 0.5 1.1 21.691001003.6\r\n> 2006.173.14:10:12.77#abcon#{5=INTERFACE CLEAR} 2006.173.14:10:12.83#abcon#[5=S1D000X0/0*\r\n] 2006.173.14:10:13.25$setupk4/"tpicd 2006.173.14:10:13.25$setupk4/echo=off 2006.173.14:10:13.26$setupk4/xlog=off 2006.173.14:10:13.26:!2006.173.14:10:44 2006.173.14:10:16.13#trakl#Source acquired 2006.173.14:10:18.14#flagr#flagr/antenna,acquired 2006.173.14:10:44.02:preob 2006.173.14:10:45.14/onsource/TRACKING 2006.173.14:10:45.14:!2006.173.14:10:54 2006.173.14:10:54.02:"tape 2006.173.14:10:54.02:"st=record 2006.173.14:10:54.02:data_valid=on 2006.173.14:10:54.02:midob 2006.173.14:10:55.14/onsource/TRACKING 2006.173.14:10:55.14/wx/21.68,1003.7,100 2006.173.14:10:55.29/cable/+6.5054E-03 2006.173.14:10:56.38/va/01,07,usb,yes,50,54 2006.173.14:10:56.38/va/02,06,usb,yes,50,51 2006.173.14:10:56.38/va/03,05,usb,yes,63,66 2006.173.14:10:56.38/va/04,06,usb,yes,51,54 2006.173.14:10:56.38/va/05,04,usb,yes,41,42 2006.173.14:10:56.38/va/06,03,usb,yes,57,57 2006.173.14:10:56.38/va/07,04,usb,yes,46,48 2006.173.14:10:56.38/va/08,04,usb,yes,40,47 2006.173.14:10:56.61/valo/01,524.99,yes,locked 2006.173.14:10:56.61/valo/02,534.99,yes,locked 2006.173.14:10:56.61/valo/03,564.99,yes,locked 2006.173.14:10:56.61/valo/04,624.99,yes,locked 2006.173.14:10:56.61/valo/05,734.99,yes,locked 2006.173.14:10:56.61/valo/06,814.99,yes,locked 2006.173.14:10:56.61/valo/07,864.99,yes,locked 2006.173.14:10:56.61/valo/08,884.99,yes,locked 2006.173.14:10:57.70/vb/01,04,usb,yes,32,29 2006.173.14:10:57.70/vb/02,04,usb,yes,34,34 2006.173.14:10:57.70/vb/03,04,usb,yes,31,34 2006.173.14:10:57.70/vb/04,04,usb,yes,35,34 2006.173.14:10:57.70/vb/05,04,usb,yes,28,30 2006.173.14:10:57.70/vb/06,04,usb,yes,32,28 2006.173.14:10:57.70/vb/07,04,usb,yes,32,32 2006.173.14:10:57.70/vb/08,04,usb,yes,30,33 2006.173.14:10:57.94/vblo/01,629.99,yes,locked 2006.173.14:10:57.94/vblo/02,634.99,yes,locked 2006.173.14:10:57.94/vblo/03,649.99,yes,locked 2006.173.14:10:57.94/vblo/04,679.99,yes,locked 2006.173.14:10:57.94/vblo/05,709.99,yes,locked 2006.173.14:10:57.94/vblo/06,719.99,yes,locked 2006.173.14:10:57.94/vblo/07,734.99,yes,locked 2006.173.14:10:57.94/vblo/08,744.99,yes,locked 2006.173.14:10:58.09/vabw/8 2006.173.14:10:58.24/vbbw/8 2006.173.14:10:58.33/xfe/off,on,14.5 2006.173.14:10:58.70/ifatt/23,28,28,28 2006.173.14:10:59.07/fmout-gps/S +3.92E-07 2006.173.14:10:59.12:!2006.173.14:13:14 2006.173.14:13:14.01:data_valid=off 2006.173.14:13:14.02:"et 2006.173.14:13:14.02:!+3s 2006.173.14:13:17.04:"tape 2006.173.14:13:17.04:postob 2006.173.14:13:17.12/cable/+6.5069E-03 2006.173.14:13:17.12/wx/21.65,1003.8,100 2006.173.14:13:17.18/fmout-gps/S +3.90E-07 2006.173.14:13:17.18:scan_name=173-1414,jd0606,390 2006.173.14:13:17.19:source=1308+326,131028.66,322043.8,2000.0,cw 2006.173.14:13:19.14#flagr#flagr/antenna,new-source 2006.173.14:13:19.15:checkk5 2006.173.14:13:19.50/chk_autoobs//k5ts1/ autoobs is running! 2006.173.14:13:19.89/chk_autoobs//k5ts2/ autoobs is running! 2006.173.14:13:20.29/chk_autoobs//k5ts3/ autoobs is running! 2006.173.14:13:20.70/chk_autoobs//k5ts4/ autoobs is running! 2006.173.14:13:21.09/chk_obsdata//k5ts1/T1731410??a.dat file size is correct (nominal:560MB, actual:556MB). 2006.173.14:13:21.49/chk_obsdata//k5ts2/T1731410??b.dat file size is correct (nominal:560MB, actual:556MB). 2006.173.14:13:21.89/chk_obsdata//k5ts3/T1731410??c.dat file size is correct (nominal:560MB, actual:556MB). 2006.173.14:13:22.30/chk_obsdata//k5ts4/T1731410??d.dat file size is correct (nominal:560MB, actual:556MB). 2006.173.14:13:23.02/k5log//k5ts1_log_newline 2006.173.14:13:23.73/k5log//k5ts2_log_newline 2006.173.14:13:24.45/k5log//k5ts3_log_newline 2006.173.14:13:25.16/k5log//k5ts4_log_newline 2006.173.14:13:25.19/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.14:13:25.19:setupk4=1 2006.173.14:13:25.19$setupk4/echo=on 2006.173.14:13:25.19$setupk4/pcalon 2006.173.14:13:25.19$pcalon/"no phase cal control is implemented here 2006.173.14:13:25.19$setupk4/"tpicd=stop 2006.173.14:13:25.19$setupk4/"rec=synch_on 2006.173.14:13:25.19$setupk4/"rec_mode=128 2006.173.14:13:25.19$setupk4/!* 2006.173.14:13:25.19$setupk4/recpk4 2006.173.14:13:25.19$recpk4/recpatch= 2006.173.14:13:25.19$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.14:13:25.19$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.14:13:25.19$setupk4/vck44 2006.173.14:13:25.19$vck44/valo=1,524.99 2006.173.14:13:25.19#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.14:13:25.19#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.14:13:25.19#ibcon#ireg 17 cls_cnt 0 2006.173.14:13:25.19#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.14:13:25.19#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.14:13:25.19#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.14:13:25.19#ibcon#enter wrdev, iclass 11, count 0 2006.173.14:13:25.19#ibcon#first serial, iclass 11, count 0 2006.173.14:13:25.19#ibcon#enter sib2, iclass 11, count 0 2006.173.14:13:25.19#ibcon#flushed, iclass 11, count 0 2006.173.14:13:25.19#ibcon#about to write, iclass 11, count 0 2006.173.14:13:25.19#ibcon#wrote, iclass 11, count 0 2006.173.14:13:25.19#ibcon#about to read 3, iclass 11, count 0 2006.173.14:13:25.20#ibcon#read 3, iclass 11, count 0 2006.173.14:13:25.20#ibcon#about to read 4, iclass 11, count 0 2006.173.14:13:25.20#ibcon#read 4, iclass 11, count 0 2006.173.14:13:25.20#ibcon#about to read 5, iclass 11, count 0 2006.173.14:13:25.20#ibcon#read 5, iclass 11, count 0 2006.173.14:13:25.20#ibcon#about to read 6, iclass 11, count 0 2006.173.14:13:25.20#ibcon#read 6, iclass 11, count 0 2006.173.14:13:25.20#ibcon#end of sib2, iclass 11, count 0 2006.173.14:13:25.20#ibcon#*mode == 0, iclass 11, count 0 2006.173.14:13:25.20#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.14:13:25.20#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.14:13:25.20#ibcon#*before write, iclass 11, count 0 2006.173.14:13:25.20#ibcon#enter sib2, iclass 11, count 0 2006.173.14:13:25.20#ibcon#flushed, iclass 11, count 0 2006.173.14:13:25.20#ibcon#about to write, iclass 11, count 0 2006.173.14:13:25.20#ibcon#wrote, iclass 11, count 0 2006.173.14:13:25.20#ibcon#about to read 3, iclass 11, count 0 2006.173.14:13:25.25#ibcon#read 3, iclass 11, count 0 2006.173.14:13:25.25#ibcon#about to read 4, iclass 11, count 0 2006.173.14:13:25.25#ibcon#read 4, iclass 11, count 0 2006.173.14:13:25.25#ibcon#about to read 5, iclass 11, count 0 2006.173.14:13:25.25#ibcon#read 5, iclass 11, count 0 2006.173.14:13:25.25#ibcon#about to read 6, iclass 11, count 0 2006.173.14:13:25.25#ibcon#read 6, iclass 11, count 0 2006.173.14:13:25.25#ibcon#end of sib2, iclass 11, count 0 2006.173.14:13:25.25#ibcon#*after write, iclass 11, count 0 2006.173.14:13:25.25#ibcon#*before return 0, iclass 11, count 0 2006.173.14:13:25.25#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.14:13:25.25#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.14:13:25.25#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.14:13:25.25#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.14:13:25.25$vck44/va=1,7 2006.173.14:13:25.25#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.173.14:13:25.25#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.173.14:13:25.25#ibcon#ireg 11 cls_cnt 2 2006.173.14:13:25.25#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.14:13:25.25#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.14:13:25.25#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.14:13:25.25#ibcon#enter wrdev, iclass 13, count 2 2006.173.14:13:25.25#ibcon#first serial, iclass 13, count 2 2006.173.14:13:25.25#ibcon#enter sib2, iclass 13, count 2 2006.173.14:13:25.25#ibcon#flushed, iclass 13, count 2 2006.173.14:13:25.25#ibcon#about to write, iclass 13, count 2 2006.173.14:13:25.25#ibcon#wrote, iclass 13, count 2 2006.173.14:13:25.25#ibcon#about to read 3, iclass 13, count 2 2006.173.14:13:25.27#ibcon#read 3, iclass 13, count 2 2006.173.14:13:25.27#ibcon#about to read 4, iclass 13, count 2 2006.173.14:13:25.27#ibcon#read 4, iclass 13, count 2 2006.173.14:13:25.27#ibcon#about to read 5, iclass 13, count 2 2006.173.14:13:25.27#ibcon#read 5, iclass 13, count 2 2006.173.14:13:25.27#ibcon#about to read 6, iclass 13, count 2 2006.173.14:13:25.27#ibcon#read 6, iclass 13, count 2 2006.173.14:13:25.27#ibcon#end of sib2, iclass 13, count 2 2006.173.14:13:25.27#ibcon#*mode == 0, iclass 13, count 2 2006.173.14:13:25.27#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.173.14:13:25.27#ibcon#[25=AT01-07\r\n] 2006.173.14:13:25.27#ibcon#*before write, iclass 13, count 2 2006.173.14:13:25.27#ibcon#enter sib2, iclass 13, count 2 2006.173.14:13:25.27#ibcon#flushed, iclass 13, count 2 2006.173.14:13:25.27#ibcon#about to write, iclass 13, count 2 2006.173.14:13:25.27#ibcon#wrote, iclass 13, count 2 2006.173.14:13:25.27#ibcon#about to read 3, iclass 13, count 2 2006.173.14:13:25.30#ibcon#read 3, iclass 13, count 2 2006.173.14:13:25.30#ibcon#about to read 4, iclass 13, count 2 2006.173.14:13:25.30#ibcon#read 4, iclass 13, count 2 2006.173.14:13:25.30#ibcon#about to read 5, iclass 13, count 2 2006.173.14:13:25.30#ibcon#read 5, iclass 13, count 2 2006.173.14:13:25.30#ibcon#about to read 6, iclass 13, count 2 2006.173.14:13:25.30#ibcon#read 6, iclass 13, count 2 2006.173.14:13:25.30#ibcon#end of sib2, iclass 13, count 2 2006.173.14:13:25.30#ibcon#*after write, iclass 13, count 2 2006.173.14:13:25.30#ibcon#*before return 0, iclass 13, count 2 2006.173.14:13:25.30#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.14:13:25.30#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.173.14:13:25.30#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.173.14:13:25.30#ibcon#ireg 7 cls_cnt 0 2006.173.14:13:25.30#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.14:13:25.42#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.14:13:25.42#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.14:13:25.42#ibcon#enter wrdev, iclass 13, count 0 2006.173.14:13:25.42#ibcon#first serial, iclass 13, count 0 2006.173.14:13:25.42#ibcon#enter sib2, iclass 13, count 0 2006.173.14:13:25.42#ibcon#flushed, iclass 13, count 0 2006.173.14:13:25.42#ibcon#about to write, iclass 13, count 0 2006.173.14:13:25.42#ibcon#wrote, iclass 13, count 0 2006.173.14:13:25.42#ibcon#about to read 3, iclass 13, count 0 2006.173.14:13:25.44#ibcon#read 3, iclass 13, count 0 2006.173.14:13:25.44#ibcon#about to read 4, iclass 13, count 0 2006.173.14:13:25.44#ibcon#read 4, iclass 13, count 0 2006.173.14:13:25.44#ibcon#about to read 5, iclass 13, count 0 2006.173.14:13:25.44#ibcon#read 5, iclass 13, count 0 2006.173.14:13:25.44#ibcon#about to read 6, iclass 13, count 0 2006.173.14:13:25.44#ibcon#read 6, iclass 13, count 0 2006.173.14:13:25.44#ibcon#end of sib2, iclass 13, count 0 2006.173.14:13:25.44#ibcon#*mode == 0, iclass 13, count 0 2006.173.14:13:25.44#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.14:13:25.44#ibcon#[25=USB\r\n] 2006.173.14:13:25.44#ibcon#*before write, iclass 13, count 0 2006.173.14:13:25.44#ibcon#enter sib2, iclass 13, count 0 2006.173.14:13:25.44#ibcon#flushed, iclass 13, count 0 2006.173.14:13:25.44#ibcon#about to write, iclass 13, count 0 2006.173.14:13:25.44#ibcon#wrote, iclass 13, count 0 2006.173.14:13:25.44#ibcon#about to read 3, iclass 13, count 0 2006.173.14:13:25.47#ibcon#read 3, iclass 13, count 0 2006.173.14:13:25.47#ibcon#about to read 4, iclass 13, count 0 2006.173.14:13:25.47#ibcon#read 4, iclass 13, count 0 2006.173.14:13:25.47#ibcon#about to read 5, iclass 13, count 0 2006.173.14:13:25.47#ibcon#read 5, iclass 13, count 0 2006.173.14:13:25.47#ibcon#about to read 6, iclass 13, count 0 2006.173.14:13:25.47#ibcon#read 6, iclass 13, count 0 2006.173.14:13:25.47#ibcon#end of sib2, iclass 13, count 0 2006.173.14:13:25.47#ibcon#*after write, iclass 13, count 0 2006.173.14:13:25.47#ibcon#*before return 0, iclass 13, count 0 2006.173.14:13:25.47#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.14:13:25.47#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.173.14:13:25.47#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.14:13:25.47#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.14:13:25.47$vck44/valo=2,534.99 2006.173.14:13:25.47#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.14:13:25.47#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.14:13:25.47#ibcon#ireg 17 cls_cnt 0 2006.173.14:13:25.47#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.14:13:25.47#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.14:13:25.47#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.14:13:25.47#ibcon#enter wrdev, iclass 15, count 0 2006.173.14:13:25.47#ibcon#first serial, iclass 15, count 0 2006.173.14:13:25.47#ibcon#enter sib2, iclass 15, count 0 2006.173.14:13:25.47#ibcon#flushed, iclass 15, count 0 2006.173.14:13:25.47#ibcon#about to write, iclass 15, count 0 2006.173.14:13:25.47#ibcon#wrote, iclass 15, count 0 2006.173.14:13:25.47#ibcon#about to read 3, iclass 15, count 0 2006.173.14:13:25.49#ibcon#read 3, iclass 15, count 0 2006.173.14:13:25.49#ibcon#about to read 4, iclass 15, count 0 2006.173.14:13:25.49#ibcon#read 4, iclass 15, count 0 2006.173.14:13:25.49#ibcon#about to read 5, iclass 15, count 0 2006.173.14:13:25.49#ibcon#read 5, iclass 15, count 0 2006.173.14:13:25.49#ibcon#about to read 6, iclass 15, count 0 2006.173.14:13:25.49#ibcon#read 6, iclass 15, count 0 2006.173.14:13:25.49#ibcon#end of sib2, iclass 15, count 0 2006.173.14:13:25.49#ibcon#*mode == 0, iclass 15, count 0 2006.173.14:13:25.49#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.14:13:25.49#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.14:13:25.49#ibcon#*before write, iclass 15, count 0 2006.173.14:13:25.49#ibcon#enter sib2, iclass 15, count 0 2006.173.14:13:25.49#ibcon#flushed, iclass 15, count 0 2006.173.14:13:25.49#ibcon#about to write, iclass 15, count 0 2006.173.14:13:25.49#ibcon#wrote, iclass 15, count 0 2006.173.14:13:25.49#ibcon#about to read 3, iclass 15, count 0 2006.173.14:13:25.53#ibcon#read 3, iclass 15, count 0 2006.173.14:13:25.53#ibcon#about to read 4, iclass 15, count 0 2006.173.14:13:25.53#ibcon#read 4, iclass 15, count 0 2006.173.14:13:25.53#ibcon#about to read 5, iclass 15, count 0 2006.173.14:13:25.53#ibcon#read 5, iclass 15, count 0 2006.173.14:13:25.53#ibcon#about to read 6, iclass 15, count 0 2006.173.14:13:25.53#ibcon#read 6, iclass 15, count 0 2006.173.14:13:25.53#ibcon#end of sib2, iclass 15, count 0 2006.173.14:13:25.53#ibcon#*after write, iclass 15, count 0 2006.173.14:13:25.53#ibcon#*before return 0, iclass 15, count 0 2006.173.14:13:25.53#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.14:13:25.53#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.14:13:25.53#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.14:13:25.53#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.14:13:25.53$vck44/va=2,6 2006.173.14:13:25.53#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.14:13:25.53#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.14:13:25.53#ibcon#ireg 11 cls_cnt 2 2006.173.14:13:25.53#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.14:13:25.59#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.14:13:25.59#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.14:13:25.59#ibcon#enter wrdev, iclass 17, count 2 2006.173.14:13:25.59#ibcon#first serial, iclass 17, count 2 2006.173.14:13:25.59#ibcon#enter sib2, iclass 17, count 2 2006.173.14:13:25.59#ibcon#flushed, iclass 17, count 2 2006.173.14:13:25.59#ibcon#about to write, iclass 17, count 2 2006.173.14:13:25.59#ibcon#wrote, iclass 17, count 2 2006.173.14:13:25.59#ibcon#about to read 3, iclass 17, count 2 2006.173.14:13:25.61#ibcon#read 3, iclass 17, count 2 2006.173.14:13:25.61#ibcon#about to read 4, iclass 17, count 2 2006.173.14:13:25.61#ibcon#read 4, iclass 17, count 2 2006.173.14:13:25.61#ibcon#about to read 5, iclass 17, count 2 2006.173.14:13:25.61#ibcon#read 5, iclass 17, count 2 2006.173.14:13:25.61#ibcon#about to read 6, iclass 17, count 2 2006.173.14:13:25.61#ibcon#read 6, iclass 17, count 2 2006.173.14:13:25.61#ibcon#end of sib2, iclass 17, count 2 2006.173.14:13:25.61#ibcon#*mode == 0, iclass 17, count 2 2006.173.14:13:25.61#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.14:13:25.61#ibcon#[25=AT02-06\r\n] 2006.173.14:13:25.61#ibcon#*before write, iclass 17, count 2 2006.173.14:13:25.61#ibcon#enter sib2, iclass 17, count 2 2006.173.14:13:25.61#ibcon#flushed, iclass 17, count 2 2006.173.14:13:25.61#ibcon#about to write, iclass 17, count 2 2006.173.14:13:25.61#ibcon#wrote, iclass 17, count 2 2006.173.14:13:25.61#ibcon#about to read 3, iclass 17, count 2 2006.173.14:13:25.64#ibcon#read 3, iclass 17, count 2 2006.173.14:13:25.64#ibcon#about to read 4, iclass 17, count 2 2006.173.14:13:25.64#ibcon#read 4, iclass 17, count 2 2006.173.14:13:25.64#ibcon#about to read 5, iclass 17, count 2 2006.173.14:13:25.64#ibcon#read 5, iclass 17, count 2 2006.173.14:13:25.64#ibcon#about to read 6, iclass 17, count 2 2006.173.14:13:25.64#ibcon#read 6, iclass 17, count 2 2006.173.14:13:25.64#ibcon#end of sib2, iclass 17, count 2 2006.173.14:13:25.64#ibcon#*after write, iclass 17, count 2 2006.173.14:13:25.64#ibcon#*before return 0, iclass 17, count 2 2006.173.14:13:25.64#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.14:13:25.64#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.14:13:25.64#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.14:13:25.64#ibcon#ireg 7 cls_cnt 0 2006.173.14:13:25.64#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.14:13:25.76#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.14:13:25.76#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.14:13:25.76#ibcon#enter wrdev, iclass 17, count 0 2006.173.14:13:25.76#ibcon#first serial, iclass 17, count 0 2006.173.14:13:25.76#ibcon#enter sib2, iclass 17, count 0 2006.173.14:13:25.76#ibcon#flushed, iclass 17, count 0 2006.173.14:13:25.76#ibcon#about to write, iclass 17, count 0 2006.173.14:13:25.76#ibcon#wrote, iclass 17, count 0 2006.173.14:13:25.76#ibcon#about to read 3, iclass 17, count 0 2006.173.14:13:25.78#ibcon#read 3, iclass 17, count 0 2006.173.14:13:25.78#ibcon#about to read 4, iclass 17, count 0 2006.173.14:13:25.78#ibcon#read 4, iclass 17, count 0 2006.173.14:13:25.78#ibcon#about to read 5, iclass 17, count 0 2006.173.14:13:25.78#ibcon#read 5, iclass 17, count 0 2006.173.14:13:25.78#ibcon#about to read 6, iclass 17, count 0 2006.173.14:13:25.78#ibcon#read 6, iclass 17, count 0 2006.173.14:13:25.78#ibcon#end of sib2, iclass 17, count 0 2006.173.14:13:25.78#ibcon#*mode == 0, iclass 17, count 0 2006.173.14:13:25.78#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.14:13:25.78#ibcon#[25=USB\r\n] 2006.173.14:13:25.78#ibcon#*before write, iclass 17, count 0 2006.173.14:13:25.78#ibcon#enter sib2, iclass 17, count 0 2006.173.14:13:25.78#ibcon#flushed, iclass 17, count 0 2006.173.14:13:25.78#ibcon#about to write, iclass 17, count 0 2006.173.14:13:25.78#ibcon#wrote, iclass 17, count 0 2006.173.14:13:25.78#ibcon#about to read 3, iclass 17, count 0 2006.173.14:13:25.81#ibcon#read 3, iclass 17, count 0 2006.173.14:13:25.81#ibcon#about to read 4, iclass 17, count 0 2006.173.14:13:25.81#ibcon#read 4, iclass 17, count 0 2006.173.14:13:25.81#ibcon#about to read 5, iclass 17, count 0 2006.173.14:13:25.81#ibcon#read 5, iclass 17, count 0 2006.173.14:13:25.81#ibcon#about to read 6, iclass 17, count 0 2006.173.14:13:25.81#ibcon#read 6, iclass 17, count 0 2006.173.14:13:25.81#ibcon#end of sib2, iclass 17, count 0 2006.173.14:13:25.81#ibcon#*after write, iclass 17, count 0 2006.173.14:13:25.81#ibcon#*before return 0, iclass 17, count 0 2006.173.14:13:25.81#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.14:13:25.81#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.14:13:25.81#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.14:13:25.81#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.14:13:25.81$vck44/valo=3,564.99 2006.173.14:13:25.81#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.14:13:25.81#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.14:13:25.81#ibcon#ireg 17 cls_cnt 0 2006.173.14:13:25.81#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.14:13:25.81#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.14:13:25.81#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.14:13:25.81#ibcon#enter wrdev, iclass 19, count 0 2006.173.14:13:25.81#ibcon#first serial, iclass 19, count 0 2006.173.14:13:25.81#ibcon#enter sib2, iclass 19, count 0 2006.173.14:13:25.81#ibcon#flushed, iclass 19, count 0 2006.173.14:13:25.81#ibcon#about to write, iclass 19, count 0 2006.173.14:13:25.81#ibcon#wrote, iclass 19, count 0 2006.173.14:13:25.81#ibcon#about to read 3, iclass 19, count 0 2006.173.14:13:25.83#ibcon#read 3, iclass 19, count 0 2006.173.14:13:25.83#ibcon#about to read 4, iclass 19, count 0 2006.173.14:13:25.83#ibcon#read 4, iclass 19, count 0 2006.173.14:13:25.83#ibcon#about to read 5, iclass 19, count 0 2006.173.14:13:25.83#ibcon#read 5, iclass 19, count 0 2006.173.14:13:25.83#ibcon#about to read 6, iclass 19, count 0 2006.173.14:13:25.83#ibcon#read 6, iclass 19, count 0 2006.173.14:13:25.83#ibcon#end of sib2, iclass 19, count 0 2006.173.14:13:25.83#ibcon#*mode == 0, iclass 19, count 0 2006.173.14:13:25.83#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.14:13:25.83#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.14:13:25.83#ibcon#*before write, iclass 19, count 0 2006.173.14:13:25.83#ibcon#enter sib2, iclass 19, count 0 2006.173.14:13:25.83#ibcon#flushed, iclass 19, count 0 2006.173.14:13:25.83#ibcon#about to write, iclass 19, count 0 2006.173.14:13:25.83#ibcon#wrote, iclass 19, count 0 2006.173.14:13:25.83#ibcon#about to read 3, iclass 19, count 0 2006.173.14:13:25.87#ibcon#read 3, iclass 19, count 0 2006.173.14:13:25.87#ibcon#about to read 4, iclass 19, count 0 2006.173.14:13:25.87#ibcon#read 4, iclass 19, count 0 2006.173.14:13:25.87#ibcon#about to read 5, iclass 19, count 0 2006.173.14:13:25.87#ibcon#read 5, iclass 19, count 0 2006.173.14:13:25.87#ibcon#about to read 6, iclass 19, count 0 2006.173.14:13:25.87#ibcon#read 6, iclass 19, count 0 2006.173.14:13:25.87#ibcon#end of sib2, iclass 19, count 0 2006.173.14:13:25.87#ibcon#*after write, iclass 19, count 0 2006.173.14:13:25.87#ibcon#*before return 0, iclass 19, count 0 2006.173.14:13:25.87#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.14:13:25.87#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.14:13:25.87#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.14:13:25.87#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.14:13:25.87$vck44/va=3,5 2006.173.14:13:25.87#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.14:13:25.87#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.14:13:25.87#ibcon#ireg 11 cls_cnt 2 2006.173.14:13:25.87#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.14:13:25.93#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.14:13:25.93#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.14:13:25.93#ibcon#enter wrdev, iclass 21, count 2 2006.173.14:13:25.93#ibcon#first serial, iclass 21, count 2 2006.173.14:13:25.93#ibcon#enter sib2, iclass 21, count 2 2006.173.14:13:25.93#ibcon#flushed, iclass 21, count 2 2006.173.14:13:25.93#ibcon#about to write, iclass 21, count 2 2006.173.14:13:25.93#ibcon#wrote, iclass 21, count 2 2006.173.14:13:25.93#ibcon#about to read 3, iclass 21, count 2 2006.173.14:13:25.95#ibcon#read 3, iclass 21, count 2 2006.173.14:13:25.95#ibcon#about to read 4, iclass 21, count 2 2006.173.14:13:25.95#ibcon#read 4, iclass 21, count 2 2006.173.14:13:25.95#ibcon#about to read 5, iclass 21, count 2 2006.173.14:13:25.95#ibcon#read 5, iclass 21, count 2 2006.173.14:13:25.95#ibcon#about to read 6, iclass 21, count 2 2006.173.14:13:25.95#ibcon#read 6, iclass 21, count 2 2006.173.14:13:25.95#ibcon#end of sib2, iclass 21, count 2 2006.173.14:13:25.95#ibcon#*mode == 0, iclass 21, count 2 2006.173.14:13:25.95#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.14:13:25.95#ibcon#[25=AT03-05\r\n] 2006.173.14:13:25.95#ibcon#*before write, iclass 21, count 2 2006.173.14:13:25.95#ibcon#enter sib2, iclass 21, count 2 2006.173.14:13:25.95#ibcon#flushed, iclass 21, count 2 2006.173.14:13:25.95#ibcon#about to write, iclass 21, count 2 2006.173.14:13:25.95#ibcon#wrote, iclass 21, count 2 2006.173.14:13:25.95#ibcon#about to read 3, iclass 21, count 2 2006.173.14:13:25.98#abcon#<5=/02 0.4 1.1 21.651001003.8\r\n> 2006.173.14:13:25.98#ibcon#read 3, iclass 21, count 2 2006.173.14:13:25.98#ibcon#about to read 4, iclass 21, count 2 2006.173.14:13:25.98#ibcon#read 4, iclass 21, count 2 2006.173.14:13:25.98#ibcon#about to read 5, iclass 21, count 2 2006.173.14:13:25.98#ibcon#read 5, iclass 21, count 2 2006.173.14:13:25.98#ibcon#about to read 6, iclass 21, count 2 2006.173.14:13:25.98#ibcon#read 6, iclass 21, count 2 2006.173.14:13:25.98#ibcon#end of sib2, iclass 21, count 2 2006.173.14:13:25.98#ibcon#*after write, iclass 21, count 2 2006.173.14:13:25.98#ibcon#*before return 0, iclass 21, count 2 2006.173.14:13:25.98#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.14:13:25.98#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.14:13:25.98#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.14:13:25.98#ibcon#ireg 7 cls_cnt 0 2006.173.14:13:25.98#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.14:13:26.00#abcon#{5=INTERFACE CLEAR} 2006.173.14:13:26.06#abcon#[5=S1D000X0/0*\r\n] 2006.173.14:13:26.10#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.14:13:26.10#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.14:13:26.10#ibcon#enter wrdev, iclass 21, count 0 2006.173.14:13:26.10#ibcon#first serial, iclass 21, count 0 2006.173.14:13:26.10#ibcon#enter sib2, iclass 21, count 0 2006.173.14:13:26.10#ibcon#flushed, iclass 21, count 0 2006.173.14:13:26.10#ibcon#about to write, iclass 21, count 0 2006.173.14:13:26.10#ibcon#wrote, iclass 21, count 0 2006.173.14:13:26.10#ibcon#about to read 3, iclass 21, count 0 2006.173.14:13:26.12#ibcon#read 3, iclass 21, count 0 2006.173.14:13:26.12#ibcon#about to read 4, iclass 21, count 0 2006.173.14:13:26.12#ibcon#read 4, iclass 21, count 0 2006.173.14:13:26.12#ibcon#about to read 5, iclass 21, count 0 2006.173.14:13:26.12#ibcon#read 5, iclass 21, count 0 2006.173.14:13:26.12#ibcon#about to read 6, iclass 21, count 0 2006.173.14:13:26.12#ibcon#read 6, iclass 21, count 0 2006.173.14:13:26.12#ibcon#end of sib2, iclass 21, count 0 2006.173.14:13:26.12#ibcon#*mode == 0, iclass 21, count 0 2006.173.14:13:26.12#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.14:13:26.12#ibcon#[25=USB\r\n] 2006.173.14:13:26.12#ibcon#*before write, iclass 21, count 0 2006.173.14:13:26.12#ibcon#enter sib2, iclass 21, count 0 2006.173.14:13:26.12#ibcon#flushed, iclass 21, count 0 2006.173.14:13:26.12#ibcon#about to write, iclass 21, count 0 2006.173.14:13:26.12#ibcon#wrote, iclass 21, count 0 2006.173.14:13:26.12#ibcon#about to read 3, iclass 21, count 0 2006.173.14:13:26.15#ibcon#read 3, iclass 21, count 0 2006.173.14:13:26.15#ibcon#about to read 4, iclass 21, count 0 2006.173.14:13:26.15#ibcon#read 4, iclass 21, count 0 2006.173.14:13:26.15#ibcon#about to read 5, iclass 21, count 0 2006.173.14:13:26.15#ibcon#read 5, iclass 21, count 0 2006.173.14:13:26.15#ibcon#about to read 6, iclass 21, count 0 2006.173.14:13:26.15#ibcon#read 6, iclass 21, count 0 2006.173.14:13:26.15#ibcon#end of sib2, iclass 21, count 0 2006.173.14:13:26.15#ibcon#*after write, iclass 21, count 0 2006.173.14:13:26.15#ibcon#*before return 0, iclass 21, count 0 2006.173.14:13:26.15#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.14:13:26.15#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.14:13:26.15#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.14:13:26.15#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.14:13:26.15$vck44/valo=4,624.99 2006.173.14:13:26.15#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.14:13:26.15#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.14:13:26.15#ibcon#ireg 17 cls_cnt 0 2006.173.14:13:26.15#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.14:13:26.15#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.14:13:26.15#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.14:13:26.15#ibcon#enter wrdev, iclass 27, count 0 2006.173.14:13:26.15#ibcon#first serial, iclass 27, count 0 2006.173.14:13:26.15#ibcon#enter sib2, iclass 27, count 0 2006.173.14:13:26.15#ibcon#flushed, iclass 27, count 0 2006.173.14:13:26.15#ibcon#about to write, iclass 27, count 0 2006.173.14:13:26.15#ibcon#wrote, iclass 27, count 0 2006.173.14:13:26.15#ibcon#about to read 3, iclass 27, count 0 2006.173.14:13:26.17#ibcon#read 3, iclass 27, count 0 2006.173.14:13:26.17#ibcon#about to read 4, iclass 27, count 0 2006.173.14:13:26.17#ibcon#read 4, iclass 27, count 0 2006.173.14:13:26.17#ibcon#about to read 5, iclass 27, count 0 2006.173.14:13:26.17#ibcon#read 5, iclass 27, count 0 2006.173.14:13:26.17#ibcon#about to read 6, iclass 27, count 0 2006.173.14:13:26.17#ibcon#read 6, iclass 27, count 0 2006.173.14:13:26.17#ibcon#end of sib2, iclass 27, count 0 2006.173.14:13:26.17#ibcon#*mode == 0, iclass 27, count 0 2006.173.14:13:26.17#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.14:13:26.17#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.14:13:26.17#ibcon#*before write, iclass 27, count 0 2006.173.14:13:26.17#ibcon#enter sib2, iclass 27, count 0 2006.173.14:13:26.17#ibcon#flushed, iclass 27, count 0 2006.173.14:13:26.17#ibcon#about to write, iclass 27, count 0 2006.173.14:13:26.17#ibcon#wrote, iclass 27, count 0 2006.173.14:13:26.17#ibcon#about to read 3, iclass 27, count 0 2006.173.14:13:26.21#ibcon#read 3, iclass 27, count 0 2006.173.14:13:26.21#ibcon#about to read 4, iclass 27, count 0 2006.173.14:13:26.21#ibcon#read 4, iclass 27, count 0 2006.173.14:13:26.21#ibcon#about to read 5, iclass 27, count 0 2006.173.14:13:26.21#ibcon#read 5, iclass 27, count 0 2006.173.14:13:26.21#ibcon#about to read 6, iclass 27, count 0 2006.173.14:13:26.21#ibcon#read 6, iclass 27, count 0 2006.173.14:13:26.21#ibcon#end of sib2, iclass 27, count 0 2006.173.14:13:26.21#ibcon#*after write, iclass 27, count 0 2006.173.14:13:26.21#ibcon#*before return 0, iclass 27, count 0 2006.173.14:13:26.21#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.14:13:26.21#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.14:13:26.21#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.14:13:26.21#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.14:13:26.21$vck44/va=4,6 2006.173.14:13:26.21#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.14:13:26.21#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.14:13:26.21#ibcon#ireg 11 cls_cnt 2 2006.173.14:13:26.21#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.14:13:26.27#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.14:13:26.27#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.14:13:26.27#ibcon#enter wrdev, iclass 29, count 2 2006.173.14:13:26.27#ibcon#first serial, iclass 29, count 2 2006.173.14:13:26.27#ibcon#enter sib2, iclass 29, count 2 2006.173.14:13:26.27#ibcon#flushed, iclass 29, count 2 2006.173.14:13:26.27#ibcon#about to write, iclass 29, count 2 2006.173.14:13:26.27#ibcon#wrote, iclass 29, count 2 2006.173.14:13:26.27#ibcon#about to read 3, iclass 29, count 2 2006.173.14:13:26.29#ibcon#read 3, iclass 29, count 2 2006.173.14:13:26.29#ibcon#about to read 4, iclass 29, count 2 2006.173.14:13:26.29#ibcon#read 4, iclass 29, count 2 2006.173.14:13:26.29#ibcon#about to read 5, iclass 29, count 2 2006.173.14:13:26.29#ibcon#read 5, iclass 29, count 2 2006.173.14:13:26.29#ibcon#about to read 6, iclass 29, count 2 2006.173.14:13:26.29#ibcon#read 6, iclass 29, count 2 2006.173.14:13:26.29#ibcon#end of sib2, iclass 29, count 2 2006.173.14:13:26.29#ibcon#*mode == 0, iclass 29, count 2 2006.173.14:13:26.29#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.14:13:26.29#ibcon#[25=AT04-06\r\n] 2006.173.14:13:26.29#ibcon#*before write, iclass 29, count 2 2006.173.14:13:26.29#ibcon#enter sib2, iclass 29, count 2 2006.173.14:13:26.29#ibcon#flushed, iclass 29, count 2 2006.173.14:13:26.29#ibcon#about to write, iclass 29, count 2 2006.173.14:13:26.29#ibcon#wrote, iclass 29, count 2 2006.173.14:13:26.29#ibcon#about to read 3, iclass 29, count 2 2006.173.14:13:26.32#ibcon#read 3, iclass 29, count 2 2006.173.14:13:26.32#ibcon#about to read 4, iclass 29, count 2 2006.173.14:13:26.32#ibcon#read 4, iclass 29, count 2 2006.173.14:13:26.32#ibcon#about to read 5, iclass 29, count 2 2006.173.14:13:26.32#ibcon#read 5, iclass 29, count 2 2006.173.14:13:26.32#ibcon#about to read 6, iclass 29, count 2 2006.173.14:13:26.32#ibcon#read 6, iclass 29, count 2 2006.173.14:13:26.32#ibcon#end of sib2, iclass 29, count 2 2006.173.14:13:26.32#ibcon#*after write, iclass 29, count 2 2006.173.14:13:26.32#ibcon#*before return 0, iclass 29, count 2 2006.173.14:13:26.32#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.14:13:26.32#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.14:13:26.32#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.14:13:26.32#ibcon#ireg 7 cls_cnt 0 2006.173.14:13:26.32#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.14:13:26.44#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.14:13:26.44#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.14:13:26.44#ibcon#enter wrdev, iclass 29, count 0 2006.173.14:13:26.44#ibcon#first serial, iclass 29, count 0 2006.173.14:13:26.44#ibcon#enter sib2, iclass 29, count 0 2006.173.14:13:26.44#ibcon#flushed, iclass 29, count 0 2006.173.14:13:26.44#ibcon#about to write, iclass 29, count 0 2006.173.14:13:26.44#ibcon#wrote, iclass 29, count 0 2006.173.14:13:26.44#ibcon#about to read 3, iclass 29, count 0 2006.173.14:13:26.46#ibcon#read 3, iclass 29, count 0 2006.173.14:13:26.46#ibcon#about to read 4, iclass 29, count 0 2006.173.14:13:26.46#ibcon#read 4, iclass 29, count 0 2006.173.14:13:26.46#ibcon#about to read 5, iclass 29, count 0 2006.173.14:13:26.46#ibcon#read 5, iclass 29, count 0 2006.173.14:13:26.46#ibcon#about to read 6, iclass 29, count 0 2006.173.14:13:26.46#ibcon#read 6, iclass 29, count 0 2006.173.14:13:26.46#ibcon#end of sib2, iclass 29, count 0 2006.173.14:13:26.46#ibcon#*mode == 0, iclass 29, count 0 2006.173.14:13:26.46#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.14:13:26.46#ibcon#[25=USB\r\n] 2006.173.14:13:26.46#ibcon#*before write, iclass 29, count 0 2006.173.14:13:26.46#ibcon#enter sib2, iclass 29, count 0 2006.173.14:13:26.46#ibcon#flushed, iclass 29, count 0 2006.173.14:13:26.46#ibcon#about to write, iclass 29, count 0 2006.173.14:13:26.46#ibcon#wrote, iclass 29, count 0 2006.173.14:13:26.46#ibcon#about to read 3, iclass 29, count 0 2006.173.14:13:26.49#ibcon#read 3, iclass 29, count 0 2006.173.14:13:26.49#ibcon#about to read 4, iclass 29, count 0 2006.173.14:13:26.49#ibcon#read 4, iclass 29, count 0 2006.173.14:13:26.49#ibcon#about to read 5, iclass 29, count 0 2006.173.14:13:26.49#ibcon#read 5, iclass 29, count 0 2006.173.14:13:26.49#ibcon#about to read 6, iclass 29, count 0 2006.173.14:13:26.49#ibcon#read 6, iclass 29, count 0 2006.173.14:13:26.49#ibcon#end of sib2, iclass 29, count 0 2006.173.14:13:26.49#ibcon#*after write, iclass 29, count 0 2006.173.14:13:26.49#ibcon#*before return 0, iclass 29, count 0 2006.173.14:13:26.49#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.14:13:26.49#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.14:13:26.49#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.14:13:26.49#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.14:13:26.49$vck44/valo=5,734.99 2006.173.14:13:26.49#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.14:13:26.49#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.14:13:26.49#ibcon#ireg 17 cls_cnt 0 2006.173.14:13:26.49#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.14:13:26.49#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.14:13:26.49#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.14:13:26.49#ibcon#enter wrdev, iclass 31, count 0 2006.173.14:13:26.49#ibcon#first serial, iclass 31, count 0 2006.173.14:13:26.49#ibcon#enter sib2, iclass 31, count 0 2006.173.14:13:26.49#ibcon#flushed, iclass 31, count 0 2006.173.14:13:26.49#ibcon#about to write, iclass 31, count 0 2006.173.14:13:26.49#ibcon#wrote, iclass 31, count 0 2006.173.14:13:26.49#ibcon#about to read 3, iclass 31, count 0 2006.173.14:13:26.51#ibcon#read 3, iclass 31, count 0 2006.173.14:13:26.51#ibcon#about to read 4, iclass 31, count 0 2006.173.14:13:26.51#ibcon#read 4, iclass 31, count 0 2006.173.14:13:26.51#ibcon#about to read 5, iclass 31, count 0 2006.173.14:13:26.51#ibcon#read 5, iclass 31, count 0 2006.173.14:13:26.51#ibcon#about to read 6, iclass 31, count 0 2006.173.14:13:26.51#ibcon#read 6, iclass 31, count 0 2006.173.14:13:26.51#ibcon#end of sib2, iclass 31, count 0 2006.173.14:13:26.51#ibcon#*mode == 0, iclass 31, count 0 2006.173.14:13:26.51#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.14:13:26.51#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.14:13:26.51#ibcon#*before write, iclass 31, count 0 2006.173.14:13:26.51#ibcon#enter sib2, iclass 31, count 0 2006.173.14:13:26.51#ibcon#flushed, iclass 31, count 0 2006.173.14:13:26.51#ibcon#about to write, iclass 31, count 0 2006.173.14:13:26.51#ibcon#wrote, iclass 31, count 0 2006.173.14:13:26.51#ibcon#about to read 3, iclass 31, count 0 2006.173.14:13:26.55#ibcon#read 3, iclass 31, count 0 2006.173.14:13:26.55#ibcon#about to read 4, iclass 31, count 0 2006.173.14:13:26.55#ibcon#read 4, iclass 31, count 0 2006.173.14:13:26.55#ibcon#about to read 5, iclass 31, count 0 2006.173.14:13:26.55#ibcon#read 5, iclass 31, count 0 2006.173.14:13:26.55#ibcon#about to read 6, iclass 31, count 0 2006.173.14:13:26.55#ibcon#read 6, iclass 31, count 0 2006.173.14:13:26.55#ibcon#end of sib2, iclass 31, count 0 2006.173.14:13:26.55#ibcon#*after write, iclass 31, count 0 2006.173.14:13:26.55#ibcon#*before return 0, iclass 31, count 0 2006.173.14:13:26.55#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.14:13:26.55#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.14:13:26.55#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.14:13:26.55#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.14:13:26.55$vck44/va=5,4 2006.173.14:13:26.55#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.173.14:13:26.55#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.173.14:13:26.55#ibcon#ireg 11 cls_cnt 2 2006.173.14:13:26.55#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.14:13:26.61#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.14:13:26.61#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.14:13:26.61#ibcon#enter wrdev, iclass 33, count 2 2006.173.14:13:26.61#ibcon#first serial, iclass 33, count 2 2006.173.14:13:26.61#ibcon#enter sib2, iclass 33, count 2 2006.173.14:13:26.61#ibcon#flushed, iclass 33, count 2 2006.173.14:13:26.61#ibcon#about to write, iclass 33, count 2 2006.173.14:13:26.61#ibcon#wrote, iclass 33, count 2 2006.173.14:13:26.61#ibcon#about to read 3, iclass 33, count 2 2006.173.14:13:26.63#ibcon#read 3, iclass 33, count 2 2006.173.14:13:26.63#ibcon#about to read 4, iclass 33, count 2 2006.173.14:13:26.63#ibcon#read 4, iclass 33, count 2 2006.173.14:13:26.63#ibcon#about to read 5, iclass 33, count 2 2006.173.14:13:26.63#ibcon#read 5, iclass 33, count 2 2006.173.14:13:26.63#ibcon#about to read 6, iclass 33, count 2 2006.173.14:13:26.63#ibcon#read 6, iclass 33, count 2 2006.173.14:13:26.63#ibcon#end of sib2, iclass 33, count 2 2006.173.14:13:26.63#ibcon#*mode == 0, iclass 33, count 2 2006.173.14:13:26.63#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.173.14:13:26.63#ibcon#[25=AT05-04\r\n] 2006.173.14:13:26.63#ibcon#*before write, iclass 33, count 2 2006.173.14:13:26.63#ibcon#enter sib2, iclass 33, count 2 2006.173.14:13:26.63#ibcon#flushed, iclass 33, count 2 2006.173.14:13:26.63#ibcon#about to write, iclass 33, count 2 2006.173.14:13:26.63#ibcon#wrote, iclass 33, count 2 2006.173.14:13:26.63#ibcon#about to read 3, iclass 33, count 2 2006.173.14:13:26.66#ibcon#read 3, iclass 33, count 2 2006.173.14:13:26.66#ibcon#about to read 4, iclass 33, count 2 2006.173.14:13:26.66#ibcon#read 4, iclass 33, count 2 2006.173.14:13:26.66#ibcon#about to read 5, iclass 33, count 2 2006.173.14:13:26.66#ibcon#read 5, iclass 33, count 2 2006.173.14:13:26.66#ibcon#about to read 6, iclass 33, count 2 2006.173.14:13:26.66#ibcon#read 6, iclass 33, count 2 2006.173.14:13:26.66#ibcon#end of sib2, iclass 33, count 2 2006.173.14:13:26.66#ibcon#*after write, iclass 33, count 2 2006.173.14:13:26.66#ibcon#*before return 0, iclass 33, count 2 2006.173.14:13:26.66#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.14:13:26.66#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.173.14:13:26.66#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.173.14:13:26.66#ibcon#ireg 7 cls_cnt 0 2006.173.14:13:26.66#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.14:13:26.78#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.14:13:26.78#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.14:13:26.78#ibcon#enter wrdev, iclass 33, count 0 2006.173.14:13:26.78#ibcon#first serial, iclass 33, count 0 2006.173.14:13:26.78#ibcon#enter sib2, iclass 33, count 0 2006.173.14:13:26.78#ibcon#flushed, iclass 33, count 0 2006.173.14:13:26.78#ibcon#about to write, iclass 33, count 0 2006.173.14:13:26.78#ibcon#wrote, iclass 33, count 0 2006.173.14:13:26.78#ibcon#about to read 3, iclass 33, count 0 2006.173.14:13:26.80#ibcon#read 3, iclass 33, count 0 2006.173.14:13:26.80#ibcon#about to read 4, iclass 33, count 0 2006.173.14:13:26.80#ibcon#read 4, iclass 33, count 0 2006.173.14:13:26.80#ibcon#about to read 5, iclass 33, count 0 2006.173.14:13:26.80#ibcon#read 5, iclass 33, count 0 2006.173.14:13:26.80#ibcon#about to read 6, iclass 33, count 0 2006.173.14:13:26.80#ibcon#read 6, iclass 33, count 0 2006.173.14:13:26.80#ibcon#end of sib2, iclass 33, count 0 2006.173.14:13:26.80#ibcon#*mode == 0, iclass 33, count 0 2006.173.14:13:26.80#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.14:13:26.80#ibcon#[25=USB\r\n] 2006.173.14:13:26.80#ibcon#*before write, iclass 33, count 0 2006.173.14:13:26.80#ibcon#enter sib2, iclass 33, count 0 2006.173.14:13:26.80#ibcon#flushed, iclass 33, count 0 2006.173.14:13:26.80#ibcon#about to write, iclass 33, count 0 2006.173.14:13:26.80#ibcon#wrote, iclass 33, count 0 2006.173.14:13:26.80#ibcon#about to read 3, iclass 33, count 0 2006.173.14:13:26.83#ibcon#read 3, iclass 33, count 0 2006.173.14:13:26.83#ibcon#about to read 4, iclass 33, count 0 2006.173.14:13:26.83#ibcon#read 4, iclass 33, count 0 2006.173.14:13:26.83#ibcon#about to read 5, iclass 33, count 0 2006.173.14:13:26.83#ibcon#read 5, iclass 33, count 0 2006.173.14:13:26.83#ibcon#about to read 6, iclass 33, count 0 2006.173.14:13:26.83#ibcon#read 6, iclass 33, count 0 2006.173.14:13:26.83#ibcon#end of sib2, iclass 33, count 0 2006.173.14:13:26.83#ibcon#*after write, iclass 33, count 0 2006.173.14:13:26.83#ibcon#*before return 0, iclass 33, count 0 2006.173.14:13:26.83#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.14:13:26.83#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.173.14:13:26.83#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.14:13:26.83#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.14:13:26.83$vck44/valo=6,814.99 2006.173.14:13:26.83#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.14:13:26.83#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.14:13:26.83#ibcon#ireg 17 cls_cnt 0 2006.173.14:13:26.83#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.14:13:26.83#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.14:13:26.83#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.14:13:26.83#ibcon#enter wrdev, iclass 35, count 0 2006.173.14:13:26.83#ibcon#first serial, iclass 35, count 0 2006.173.14:13:26.83#ibcon#enter sib2, iclass 35, count 0 2006.173.14:13:26.83#ibcon#flushed, iclass 35, count 0 2006.173.14:13:26.83#ibcon#about to write, iclass 35, count 0 2006.173.14:13:26.83#ibcon#wrote, iclass 35, count 0 2006.173.14:13:26.83#ibcon#about to read 3, iclass 35, count 0 2006.173.14:13:26.85#ibcon#read 3, iclass 35, count 0 2006.173.14:13:26.85#ibcon#about to read 4, iclass 35, count 0 2006.173.14:13:26.85#ibcon#read 4, iclass 35, count 0 2006.173.14:13:26.85#ibcon#about to read 5, iclass 35, count 0 2006.173.14:13:26.85#ibcon#read 5, iclass 35, count 0 2006.173.14:13:26.85#ibcon#about to read 6, iclass 35, count 0 2006.173.14:13:26.85#ibcon#read 6, iclass 35, count 0 2006.173.14:13:26.85#ibcon#end of sib2, iclass 35, count 0 2006.173.14:13:26.85#ibcon#*mode == 0, iclass 35, count 0 2006.173.14:13:26.85#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.14:13:26.85#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.14:13:26.85#ibcon#*before write, iclass 35, count 0 2006.173.14:13:26.85#ibcon#enter sib2, iclass 35, count 0 2006.173.14:13:26.85#ibcon#flushed, iclass 35, count 0 2006.173.14:13:26.85#ibcon#about to write, iclass 35, count 0 2006.173.14:13:26.85#ibcon#wrote, iclass 35, count 0 2006.173.14:13:26.85#ibcon#about to read 3, iclass 35, count 0 2006.173.14:13:26.89#ibcon#read 3, iclass 35, count 0 2006.173.14:13:26.89#ibcon#about to read 4, iclass 35, count 0 2006.173.14:13:26.89#ibcon#read 4, iclass 35, count 0 2006.173.14:13:26.89#ibcon#about to read 5, iclass 35, count 0 2006.173.14:13:26.89#ibcon#read 5, iclass 35, count 0 2006.173.14:13:26.89#ibcon#about to read 6, iclass 35, count 0 2006.173.14:13:26.89#ibcon#read 6, iclass 35, count 0 2006.173.14:13:26.89#ibcon#end of sib2, iclass 35, count 0 2006.173.14:13:26.89#ibcon#*after write, iclass 35, count 0 2006.173.14:13:26.89#ibcon#*before return 0, iclass 35, count 0 2006.173.14:13:26.89#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.14:13:26.89#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.14:13:26.89#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.14:13:26.89#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.14:13:26.89$vck44/va=6,3 2006.173.14:13:26.89#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.173.14:13:26.89#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.173.14:13:26.89#ibcon#ireg 11 cls_cnt 2 2006.173.14:13:26.89#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.14:13:26.95#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.14:13:26.95#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.14:13:26.95#ibcon#enter wrdev, iclass 37, count 2 2006.173.14:13:26.95#ibcon#first serial, iclass 37, count 2 2006.173.14:13:26.95#ibcon#enter sib2, iclass 37, count 2 2006.173.14:13:26.95#ibcon#flushed, iclass 37, count 2 2006.173.14:13:26.95#ibcon#about to write, iclass 37, count 2 2006.173.14:13:26.95#ibcon#wrote, iclass 37, count 2 2006.173.14:13:26.95#ibcon#about to read 3, iclass 37, count 2 2006.173.14:13:26.97#ibcon#read 3, iclass 37, count 2 2006.173.14:13:26.97#ibcon#about to read 4, iclass 37, count 2 2006.173.14:13:26.97#ibcon#read 4, iclass 37, count 2 2006.173.14:13:26.97#ibcon#about to read 5, iclass 37, count 2 2006.173.14:13:26.97#ibcon#read 5, iclass 37, count 2 2006.173.14:13:26.97#ibcon#about to read 6, iclass 37, count 2 2006.173.14:13:26.97#ibcon#read 6, iclass 37, count 2 2006.173.14:13:26.97#ibcon#end of sib2, iclass 37, count 2 2006.173.14:13:26.97#ibcon#*mode == 0, iclass 37, count 2 2006.173.14:13:26.97#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.173.14:13:26.97#ibcon#[25=AT06-03\r\n] 2006.173.14:13:26.97#ibcon#*before write, iclass 37, count 2 2006.173.14:13:26.97#ibcon#enter sib2, iclass 37, count 2 2006.173.14:13:26.97#ibcon#flushed, iclass 37, count 2 2006.173.14:13:26.97#ibcon#about to write, iclass 37, count 2 2006.173.14:13:26.97#ibcon#wrote, iclass 37, count 2 2006.173.14:13:26.97#ibcon#about to read 3, iclass 37, count 2 2006.173.14:13:27.00#ibcon#read 3, iclass 37, count 2 2006.173.14:13:27.00#ibcon#about to read 4, iclass 37, count 2 2006.173.14:13:27.00#ibcon#read 4, iclass 37, count 2 2006.173.14:13:27.00#ibcon#about to read 5, iclass 37, count 2 2006.173.14:13:27.00#ibcon#read 5, iclass 37, count 2 2006.173.14:13:27.00#ibcon#about to read 6, iclass 37, count 2 2006.173.14:13:27.00#ibcon#read 6, iclass 37, count 2 2006.173.14:13:27.00#ibcon#end of sib2, iclass 37, count 2 2006.173.14:13:27.00#ibcon#*after write, iclass 37, count 2 2006.173.14:13:27.00#ibcon#*before return 0, iclass 37, count 2 2006.173.14:13:27.00#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.14:13:27.00#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.173.14:13:27.00#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.173.14:13:27.00#ibcon#ireg 7 cls_cnt 0 2006.173.14:13:27.00#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.14:13:27.12#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.14:13:27.12#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.14:13:27.12#ibcon#enter wrdev, iclass 37, count 0 2006.173.14:13:27.12#ibcon#first serial, iclass 37, count 0 2006.173.14:13:27.12#ibcon#enter sib2, iclass 37, count 0 2006.173.14:13:27.12#ibcon#flushed, iclass 37, count 0 2006.173.14:13:27.12#ibcon#about to write, iclass 37, count 0 2006.173.14:13:27.12#ibcon#wrote, iclass 37, count 0 2006.173.14:13:27.12#ibcon#about to read 3, iclass 37, count 0 2006.173.14:13:27.14#ibcon#read 3, iclass 37, count 0 2006.173.14:13:27.14#ibcon#about to read 4, iclass 37, count 0 2006.173.14:13:27.14#ibcon#read 4, iclass 37, count 0 2006.173.14:13:27.14#ibcon#about to read 5, iclass 37, count 0 2006.173.14:13:27.14#ibcon#read 5, iclass 37, count 0 2006.173.14:13:27.14#ibcon#about to read 6, iclass 37, count 0 2006.173.14:13:27.14#ibcon#read 6, iclass 37, count 0 2006.173.14:13:27.14#ibcon#end of sib2, iclass 37, count 0 2006.173.14:13:27.14#ibcon#*mode == 0, iclass 37, count 0 2006.173.14:13:27.14#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.14:13:27.14#ibcon#[25=USB\r\n] 2006.173.14:13:27.14#ibcon#*before write, iclass 37, count 0 2006.173.14:13:27.14#ibcon#enter sib2, iclass 37, count 0 2006.173.14:13:27.14#ibcon#flushed, iclass 37, count 0 2006.173.14:13:27.14#ibcon#about to write, iclass 37, count 0 2006.173.14:13:27.14#ibcon#wrote, iclass 37, count 0 2006.173.14:13:27.14#ibcon#about to read 3, iclass 37, count 0 2006.173.14:13:27.17#ibcon#read 3, iclass 37, count 0 2006.173.14:13:27.17#ibcon#about to read 4, iclass 37, count 0 2006.173.14:13:27.17#ibcon#read 4, iclass 37, count 0 2006.173.14:13:27.17#ibcon#about to read 5, iclass 37, count 0 2006.173.14:13:27.17#ibcon#read 5, iclass 37, count 0 2006.173.14:13:27.17#ibcon#about to read 6, iclass 37, count 0 2006.173.14:13:27.17#ibcon#read 6, iclass 37, count 0 2006.173.14:13:27.17#ibcon#end of sib2, iclass 37, count 0 2006.173.14:13:27.17#ibcon#*after write, iclass 37, count 0 2006.173.14:13:27.17#ibcon#*before return 0, iclass 37, count 0 2006.173.14:13:27.17#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.14:13:27.17#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.173.14:13:27.17#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.14:13:27.17#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.14:13:27.17$vck44/valo=7,864.99 2006.173.14:13:27.17#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.14:13:27.17#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.14:13:27.17#ibcon#ireg 17 cls_cnt 0 2006.173.14:13:27.17#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.14:13:27.17#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.14:13:27.17#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.14:13:27.17#ibcon#enter wrdev, iclass 39, count 0 2006.173.14:13:27.17#ibcon#first serial, iclass 39, count 0 2006.173.14:13:27.17#ibcon#enter sib2, iclass 39, count 0 2006.173.14:13:27.17#ibcon#flushed, iclass 39, count 0 2006.173.14:13:27.17#ibcon#about to write, iclass 39, count 0 2006.173.14:13:27.17#ibcon#wrote, iclass 39, count 0 2006.173.14:13:27.17#ibcon#about to read 3, iclass 39, count 0 2006.173.14:13:27.19#ibcon#read 3, iclass 39, count 0 2006.173.14:13:27.19#ibcon#about to read 4, iclass 39, count 0 2006.173.14:13:27.19#ibcon#read 4, iclass 39, count 0 2006.173.14:13:27.19#ibcon#about to read 5, iclass 39, count 0 2006.173.14:13:27.19#ibcon#read 5, iclass 39, count 0 2006.173.14:13:27.19#ibcon#about to read 6, iclass 39, count 0 2006.173.14:13:27.19#ibcon#read 6, iclass 39, count 0 2006.173.14:13:27.19#ibcon#end of sib2, iclass 39, count 0 2006.173.14:13:27.19#ibcon#*mode == 0, iclass 39, count 0 2006.173.14:13:27.19#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.14:13:27.19#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.14:13:27.19#ibcon#*before write, iclass 39, count 0 2006.173.14:13:27.19#ibcon#enter sib2, iclass 39, count 0 2006.173.14:13:27.19#ibcon#flushed, iclass 39, count 0 2006.173.14:13:27.19#ibcon#about to write, iclass 39, count 0 2006.173.14:13:27.19#ibcon#wrote, iclass 39, count 0 2006.173.14:13:27.19#ibcon#about to read 3, iclass 39, count 0 2006.173.14:13:27.23#ibcon#read 3, iclass 39, count 0 2006.173.14:13:27.23#ibcon#about to read 4, iclass 39, count 0 2006.173.14:13:27.23#ibcon#read 4, iclass 39, count 0 2006.173.14:13:27.23#ibcon#about to read 5, iclass 39, count 0 2006.173.14:13:27.23#ibcon#read 5, iclass 39, count 0 2006.173.14:13:27.23#ibcon#about to read 6, iclass 39, count 0 2006.173.14:13:27.23#ibcon#read 6, iclass 39, count 0 2006.173.14:13:27.23#ibcon#end of sib2, iclass 39, count 0 2006.173.14:13:27.23#ibcon#*after write, iclass 39, count 0 2006.173.14:13:27.23#ibcon#*before return 0, iclass 39, count 0 2006.173.14:13:27.23#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.14:13:27.23#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.14:13:27.23#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.14:13:27.23#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.14:13:27.23$vck44/va=7,4 2006.173.14:13:27.23#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.14:13:27.23#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.14:13:27.23#ibcon#ireg 11 cls_cnt 2 2006.173.14:13:27.23#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.14:13:27.29#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.14:13:27.29#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.14:13:27.29#ibcon#enter wrdev, iclass 3, count 2 2006.173.14:13:27.29#ibcon#first serial, iclass 3, count 2 2006.173.14:13:27.29#ibcon#enter sib2, iclass 3, count 2 2006.173.14:13:27.29#ibcon#flushed, iclass 3, count 2 2006.173.14:13:27.29#ibcon#about to write, iclass 3, count 2 2006.173.14:13:27.29#ibcon#wrote, iclass 3, count 2 2006.173.14:13:27.29#ibcon#about to read 3, iclass 3, count 2 2006.173.14:13:27.31#ibcon#read 3, iclass 3, count 2 2006.173.14:13:27.31#ibcon#about to read 4, iclass 3, count 2 2006.173.14:13:27.31#ibcon#read 4, iclass 3, count 2 2006.173.14:13:27.31#ibcon#about to read 5, iclass 3, count 2 2006.173.14:13:27.31#ibcon#read 5, iclass 3, count 2 2006.173.14:13:27.31#ibcon#about to read 6, iclass 3, count 2 2006.173.14:13:27.31#ibcon#read 6, iclass 3, count 2 2006.173.14:13:27.31#ibcon#end of sib2, iclass 3, count 2 2006.173.14:13:27.31#ibcon#*mode == 0, iclass 3, count 2 2006.173.14:13:27.31#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.14:13:27.31#ibcon#[25=AT07-04\r\n] 2006.173.14:13:27.31#ibcon#*before write, iclass 3, count 2 2006.173.14:13:27.31#ibcon#enter sib2, iclass 3, count 2 2006.173.14:13:27.31#ibcon#flushed, iclass 3, count 2 2006.173.14:13:27.31#ibcon#about to write, iclass 3, count 2 2006.173.14:13:27.31#ibcon#wrote, iclass 3, count 2 2006.173.14:13:27.31#ibcon#about to read 3, iclass 3, count 2 2006.173.14:13:27.34#ibcon#read 3, iclass 3, count 2 2006.173.14:13:27.34#ibcon#about to read 4, iclass 3, count 2 2006.173.14:13:27.34#ibcon#read 4, iclass 3, count 2 2006.173.14:13:27.34#ibcon#about to read 5, iclass 3, count 2 2006.173.14:13:27.34#ibcon#read 5, iclass 3, count 2 2006.173.14:13:27.34#ibcon#about to read 6, iclass 3, count 2 2006.173.14:13:27.34#ibcon#read 6, iclass 3, count 2 2006.173.14:13:27.34#ibcon#end of sib2, iclass 3, count 2 2006.173.14:13:27.34#ibcon#*after write, iclass 3, count 2 2006.173.14:13:27.34#ibcon#*before return 0, iclass 3, count 2 2006.173.14:13:27.34#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.14:13:27.34#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.14:13:27.34#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.14:13:27.34#ibcon#ireg 7 cls_cnt 0 2006.173.14:13:27.34#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.14:13:27.46#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.14:13:27.46#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.14:13:27.46#ibcon#enter wrdev, iclass 3, count 0 2006.173.14:13:27.46#ibcon#first serial, iclass 3, count 0 2006.173.14:13:27.46#ibcon#enter sib2, iclass 3, count 0 2006.173.14:13:27.46#ibcon#flushed, iclass 3, count 0 2006.173.14:13:27.46#ibcon#about to write, iclass 3, count 0 2006.173.14:13:27.46#ibcon#wrote, iclass 3, count 0 2006.173.14:13:27.46#ibcon#about to read 3, iclass 3, count 0 2006.173.14:13:27.48#ibcon#read 3, iclass 3, count 0 2006.173.14:13:27.48#ibcon#about to read 4, iclass 3, count 0 2006.173.14:13:27.48#ibcon#read 4, iclass 3, count 0 2006.173.14:13:27.48#ibcon#about to read 5, iclass 3, count 0 2006.173.14:13:27.48#ibcon#read 5, iclass 3, count 0 2006.173.14:13:27.48#ibcon#about to read 6, iclass 3, count 0 2006.173.14:13:27.48#ibcon#read 6, iclass 3, count 0 2006.173.14:13:27.48#ibcon#end of sib2, iclass 3, count 0 2006.173.14:13:27.48#ibcon#*mode == 0, iclass 3, count 0 2006.173.14:13:27.48#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.14:13:27.48#ibcon#[25=USB\r\n] 2006.173.14:13:27.48#ibcon#*before write, iclass 3, count 0 2006.173.14:13:27.48#ibcon#enter sib2, iclass 3, count 0 2006.173.14:13:27.48#ibcon#flushed, iclass 3, count 0 2006.173.14:13:27.48#ibcon#about to write, iclass 3, count 0 2006.173.14:13:27.48#ibcon#wrote, iclass 3, count 0 2006.173.14:13:27.48#ibcon#about to read 3, iclass 3, count 0 2006.173.14:13:27.51#ibcon#read 3, iclass 3, count 0 2006.173.14:13:27.51#ibcon#about to read 4, iclass 3, count 0 2006.173.14:13:27.51#ibcon#read 4, iclass 3, count 0 2006.173.14:13:27.51#ibcon#about to read 5, iclass 3, count 0 2006.173.14:13:27.51#ibcon#read 5, iclass 3, count 0 2006.173.14:13:27.51#ibcon#about to read 6, iclass 3, count 0 2006.173.14:13:27.51#ibcon#read 6, iclass 3, count 0 2006.173.14:13:27.51#ibcon#end of sib2, iclass 3, count 0 2006.173.14:13:27.51#ibcon#*after write, iclass 3, count 0 2006.173.14:13:27.51#ibcon#*before return 0, iclass 3, count 0 2006.173.14:13:27.51#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.14:13:27.51#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.14:13:27.51#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.14:13:27.51#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.14:13:27.51$vck44/valo=8,884.99 2006.173.14:13:27.51#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.14:13:27.51#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.14:13:27.51#ibcon#ireg 17 cls_cnt 0 2006.173.14:13:27.51#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.14:13:27.51#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.14:13:27.51#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.14:13:27.51#ibcon#enter wrdev, iclass 5, count 0 2006.173.14:13:27.51#ibcon#first serial, iclass 5, count 0 2006.173.14:13:27.51#ibcon#enter sib2, iclass 5, count 0 2006.173.14:13:27.51#ibcon#flushed, iclass 5, count 0 2006.173.14:13:27.51#ibcon#about to write, iclass 5, count 0 2006.173.14:13:27.51#ibcon#wrote, iclass 5, count 0 2006.173.14:13:27.51#ibcon#about to read 3, iclass 5, count 0 2006.173.14:13:27.53#ibcon#read 3, iclass 5, count 0 2006.173.14:13:27.53#ibcon#about to read 4, iclass 5, count 0 2006.173.14:13:27.53#ibcon#read 4, iclass 5, count 0 2006.173.14:13:27.53#ibcon#about to read 5, iclass 5, count 0 2006.173.14:13:27.53#ibcon#read 5, iclass 5, count 0 2006.173.14:13:27.53#ibcon#about to read 6, iclass 5, count 0 2006.173.14:13:27.53#ibcon#read 6, iclass 5, count 0 2006.173.14:13:27.53#ibcon#end of sib2, iclass 5, count 0 2006.173.14:13:27.53#ibcon#*mode == 0, iclass 5, count 0 2006.173.14:13:27.53#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.14:13:27.53#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.14:13:27.53#ibcon#*before write, iclass 5, count 0 2006.173.14:13:27.53#ibcon#enter sib2, iclass 5, count 0 2006.173.14:13:27.53#ibcon#flushed, iclass 5, count 0 2006.173.14:13:27.53#ibcon#about to write, iclass 5, count 0 2006.173.14:13:27.53#ibcon#wrote, iclass 5, count 0 2006.173.14:13:27.53#ibcon#about to read 3, iclass 5, count 0 2006.173.14:13:27.57#ibcon#read 3, iclass 5, count 0 2006.173.14:13:27.57#ibcon#about to read 4, iclass 5, count 0 2006.173.14:13:27.57#ibcon#read 4, iclass 5, count 0 2006.173.14:13:27.57#ibcon#about to read 5, iclass 5, count 0 2006.173.14:13:27.57#ibcon#read 5, iclass 5, count 0 2006.173.14:13:27.57#ibcon#about to read 6, iclass 5, count 0 2006.173.14:13:27.57#ibcon#read 6, iclass 5, count 0 2006.173.14:13:27.57#ibcon#end of sib2, iclass 5, count 0 2006.173.14:13:27.57#ibcon#*after write, iclass 5, count 0 2006.173.14:13:27.57#ibcon#*before return 0, iclass 5, count 0 2006.173.14:13:27.57#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.14:13:27.57#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.14:13:27.57#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.14:13:27.57#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.14:13:27.57$vck44/va=8,4 2006.173.14:13:27.57#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.173.14:13:27.57#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.173.14:13:27.57#ibcon#ireg 11 cls_cnt 2 2006.173.14:13:27.57#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.14:13:27.63#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.14:13:27.63#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.14:13:27.63#ibcon#enter wrdev, iclass 7, count 2 2006.173.14:13:27.63#ibcon#first serial, iclass 7, count 2 2006.173.14:13:27.63#ibcon#enter sib2, iclass 7, count 2 2006.173.14:13:27.63#ibcon#flushed, iclass 7, count 2 2006.173.14:13:27.63#ibcon#about to write, iclass 7, count 2 2006.173.14:13:27.63#ibcon#wrote, iclass 7, count 2 2006.173.14:13:27.63#ibcon#about to read 3, iclass 7, count 2 2006.173.14:13:27.65#ibcon#read 3, iclass 7, count 2 2006.173.14:13:27.65#ibcon#about to read 4, iclass 7, count 2 2006.173.14:13:27.65#ibcon#read 4, iclass 7, count 2 2006.173.14:13:27.65#ibcon#about to read 5, iclass 7, count 2 2006.173.14:13:27.65#ibcon#read 5, iclass 7, count 2 2006.173.14:13:27.65#ibcon#about to read 6, iclass 7, count 2 2006.173.14:13:27.65#ibcon#read 6, iclass 7, count 2 2006.173.14:13:27.65#ibcon#end of sib2, iclass 7, count 2 2006.173.14:13:27.65#ibcon#*mode == 0, iclass 7, count 2 2006.173.14:13:27.65#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.173.14:13:27.65#ibcon#[25=AT08-04\r\n] 2006.173.14:13:27.65#ibcon#*before write, iclass 7, count 2 2006.173.14:13:27.65#ibcon#enter sib2, iclass 7, count 2 2006.173.14:13:27.65#ibcon#flushed, iclass 7, count 2 2006.173.14:13:27.65#ibcon#about to write, iclass 7, count 2 2006.173.14:13:27.65#ibcon#wrote, iclass 7, count 2 2006.173.14:13:27.65#ibcon#about to read 3, iclass 7, count 2 2006.173.14:13:27.68#ibcon#read 3, iclass 7, count 2 2006.173.14:13:27.68#ibcon#about to read 4, iclass 7, count 2 2006.173.14:13:27.68#ibcon#read 4, iclass 7, count 2 2006.173.14:13:27.68#ibcon#about to read 5, iclass 7, count 2 2006.173.14:13:27.68#ibcon#read 5, iclass 7, count 2 2006.173.14:13:27.68#ibcon#about to read 6, iclass 7, count 2 2006.173.14:13:27.68#ibcon#read 6, iclass 7, count 2 2006.173.14:13:27.68#ibcon#end of sib2, iclass 7, count 2 2006.173.14:13:27.68#ibcon#*after write, iclass 7, count 2 2006.173.14:13:27.68#ibcon#*before return 0, iclass 7, count 2 2006.173.14:13:27.68#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.14:13:27.68#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.173.14:13:27.68#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.173.14:13:27.68#ibcon#ireg 7 cls_cnt 0 2006.173.14:13:27.68#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.14:13:27.80#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.14:13:27.80#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.14:13:27.80#ibcon#enter wrdev, iclass 7, count 0 2006.173.14:13:27.80#ibcon#first serial, iclass 7, count 0 2006.173.14:13:27.80#ibcon#enter sib2, iclass 7, count 0 2006.173.14:13:27.80#ibcon#flushed, iclass 7, count 0 2006.173.14:13:27.80#ibcon#about to write, iclass 7, count 0 2006.173.14:13:27.80#ibcon#wrote, iclass 7, count 0 2006.173.14:13:27.80#ibcon#about to read 3, iclass 7, count 0 2006.173.14:13:27.82#ibcon#read 3, iclass 7, count 0 2006.173.14:13:27.82#ibcon#about to read 4, iclass 7, count 0 2006.173.14:13:27.82#ibcon#read 4, iclass 7, count 0 2006.173.14:13:27.82#ibcon#about to read 5, iclass 7, count 0 2006.173.14:13:27.82#ibcon#read 5, iclass 7, count 0 2006.173.14:13:27.82#ibcon#about to read 6, iclass 7, count 0 2006.173.14:13:27.82#ibcon#read 6, iclass 7, count 0 2006.173.14:13:27.82#ibcon#end of sib2, iclass 7, count 0 2006.173.14:13:27.82#ibcon#*mode == 0, iclass 7, count 0 2006.173.14:13:27.82#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.14:13:27.82#ibcon#[25=USB\r\n] 2006.173.14:13:27.82#ibcon#*before write, iclass 7, count 0 2006.173.14:13:27.82#ibcon#enter sib2, iclass 7, count 0 2006.173.14:13:27.82#ibcon#flushed, iclass 7, count 0 2006.173.14:13:27.82#ibcon#about to write, iclass 7, count 0 2006.173.14:13:27.82#ibcon#wrote, iclass 7, count 0 2006.173.14:13:27.82#ibcon#about to read 3, iclass 7, count 0 2006.173.14:13:27.85#ibcon#read 3, iclass 7, count 0 2006.173.14:13:27.85#ibcon#about to read 4, iclass 7, count 0 2006.173.14:13:27.85#ibcon#read 4, iclass 7, count 0 2006.173.14:13:27.85#ibcon#about to read 5, iclass 7, count 0 2006.173.14:13:27.85#ibcon#read 5, iclass 7, count 0 2006.173.14:13:27.85#ibcon#about to read 6, iclass 7, count 0 2006.173.14:13:27.85#ibcon#read 6, iclass 7, count 0 2006.173.14:13:27.85#ibcon#end of sib2, iclass 7, count 0 2006.173.14:13:27.85#ibcon#*after write, iclass 7, count 0 2006.173.14:13:27.85#ibcon#*before return 0, iclass 7, count 0 2006.173.14:13:27.85#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.14:13:27.85#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.173.14:13:27.85#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.14:13:27.85#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.14:13:27.85$vck44/vblo=1,629.99 2006.173.14:13:27.85#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.14:13:27.85#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.14:13:27.85#ibcon#ireg 17 cls_cnt 0 2006.173.14:13:27.85#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.14:13:27.85#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.14:13:27.85#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.14:13:27.85#ibcon#enter wrdev, iclass 11, count 0 2006.173.14:13:27.85#ibcon#first serial, iclass 11, count 0 2006.173.14:13:27.85#ibcon#enter sib2, iclass 11, count 0 2006.173.14:13:27.85#ibcon#flushed, iclass 11, count 0 2006.173.14:13:27.85#ibcon#about to write, iclass 11, count 0 2006.173.14:13:27.85#ibcon#wrote, iclass 11, count 0 2006.173.14:13:27.85#ibcon#about to read 3, iclass 11, count 0 2006.173.14:13:27.87#ibcon#read 3, iclass 11, count 0 2006.173.14:13:27.87#ibcon#about to read 4, iclass 11, count 0 2006.173.14:13:27.87#ibcon#read 4, iclass 11, count 0 2006.173.14:13:27.87#ibcon#about to read 5, iclass 11, count 0 2006.173.14:13:27.87#ibcon#read 5, iclass 11, count 0 2006.173.14:13:27.87#ibcon#about to read 6, iclass 11, count 0 2006.173.14:13:27.87#ibcon#read 6, iclass 11, count 0 2006.173.14:13:27.87#ibcon#end of sib2, iclass 11, count 0 2006.173.14:13:27.87#ibcon#*mode == 0, iclass 11, count 0 2006.173.14:13:27.87#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.14:13:27.87#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.14:13:27.87#ibcon#*before write, iclass 11, count 0 2006.173.14:13:27.87#ibcon#enter sib2, iclass 11, count 0 2006.173.14:13:27.87#ibcon#flushed, iclass 11, count 0 2006.173.14:13:27.87#ibcon#about to write, iclass 11, count 0 2006.173.14:13:27.87#ibcon#wrote, iclass 11, count 0 2006.173.14:13:27.87#ibcon#about to read 3, iclass 11, count 0 2006.173.14:13:27.91#ibcon#read 3, iclass 11, count 0 2006.173.14:13:27.91#ibcon#about to read 4, iclass 11, count 0 2006.173.14:13:27.91#ibcon#read 4, iclass 11, count 0 2006.173.14:13:27.91#ibcon#about to read 5, iclass 11, count 0 2006.173.14:13:27.91#ibcon#read 5, iclass 11, count 0 2006.173.14:13:27.91#ibcon#about to read 6, iclass 11, count 0 2006.173.14:13:27.91#ibcon#read 6, iclass 11, count 0 2006.173.14:13:27.91#ibcon#end of sib2, iclass 11, count 0 2006.173.14:13:27.91#ibcon#*after write, iclass 11, count 0 2006.173.14:13:27.91#ibcon#*before return 0, iclass 11, count 0 2006.173.14:13:27.91#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.14:13:27.91#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.14:13:27.91#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.14:13:27.91#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.14:13:27.91$vck44/vb=1,4 2006.173.14:13:27.91#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.173.14:13:27.91#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.173.14:13:27.91#ibcon#ireg 11 cls_cnt 2 2006.173.14:13:27.91#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.14:13:27.91#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.14:13:27.91#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.14:13:27.91#ibcon#enter wrdev, iclass 13, count 2 2006.173.14:13:27.91#ibcon#first serial, iclass 13, count 2 2006.173.14:13:27.91#ibcon#enter sib2, iclass 13, count 2 2006.173.14:13:27.91#ibcon#flushed, iclass 13, count 2 2006.173.14:13:27.91#ibcon#about to write, iclass 13, count 2 2006.173.14:13:27.91#ibcon#wrote, iclass 13, count 2 2006.173.14:13:27.91#ibcon#about to read 3, iclass 13, count 2 2006.173.14:13:27.93#ibcon#read 3, iclass 13, count 2 2006.173.14:13:27.93#ibcon#about to read 4, iclass 13, count 2 2006.173.14:13:27.93#ibcon#read 4, iclass 13, count 2 2006.173.14:13:27.93#ibcon#about to read 5, iclass 13, count 2 2006.173.14:13:27.93#ibcon#read 5, iclass 13, count 2 2006.173.14:13:27.93#ibcon#about to read 6, iclass 13, count 2 2006.173.14:13:27.93#ibcon#read 6, iclass 13, count 2 2006.173.14:13:27.93#ibcon#end of sib2, iclass 13, count 2 2006.173.14:13:27.93#ibcon#*mode == 0, iclass 13, count 2 2006.173.14:13:27.93#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.173.14:13:27.93#ibcon#[27=AT01-04\r\n] 2006.173.14:13:27.93#ibcon#*before write, iclass 13, count 2 2006.173.14:13:27.93#ibcon#enter sib2, iclass 13, count 2 2006.173.14:13:27.93#ibcon#flushed, iclass 13, count 2 2006.173.14:13:27.93#ibcon#about to write, iclass 13, count 2 2006.173.14:13:27.93#ibcon#wrote, iclass 13, count 2 2006.173.14:13:27.93#ibcon#about to read 3, iclass 13, count 2 2006.173.14:13:27.96#ibcon#read 3, iclass 13, count 2 2006.173.14:13:27.96#ibcon#about to read 4, iclass 13, count 2 2006.173.14:13:27.96#ibcon#read 4, iclass 13, count 2 2006.173.14:13:27.96#ibcon#about to read 5, iclass 13, count 2 2006.173.14:13:27.96#ibcon#read 5, iclass 13, count 2 2006.173.14:13:27.96#ibcon#about to read 6, iclass 13, count 2 2006.173.14:13:27.96#ibcon#read 6, iclass 13, count 2 2006.173.14:13:27.96#ibcon#end of sib2, iclass 13, count 2 2006.173.14:13:27.96#ibcon#*after write, iclass 13, count 2 2006.173.14:13:27.96#ibcon#*before return 0, iclass 13, count 2 2006.173.14:13:27.96#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.14:13:27.96#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.173.14:13:27.96#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.173.14:13:27.96#ibcon#ireg 7 cls_cnt 0 2006.173.14:13:27.96#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.14:13:28.08#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.14:13:28.08#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.14:13:28.08#ibcon#enter wrdev, iclass 13, count 0 2006.173.14:13:28.08#ibcon#first serial, iclass 13, count 0 2006.173.14:13:28.08#ibcon#enter sib2, iclass 13, count 0 2006.173.14:13:28.08#ibcon#flushed, iclass 13, count 0 2006.173.14:13:28.08#ibcon#about to write, iclass 13, count 0 2006.173.14:13:28.08#ibcon#wrote, iclass 13, count 0 2006.173.14:13:28.08#ibcon#about to read 3, iclass 13, count 0 2006.173.14:13:28.10#ibcon#read 3, iclass 13, count 0 2006.173.14:13:28.10#ibcon#about to read 4, iclass 13, count 0 2006.173.14:13:28.10#ibcon#read 4, iclass 13, count 0 2006.173.14:13:28.10#ibcon#about to read 5, iclass 13, count 0 2006.173.14:13:28.10#ibcon#read 5, iclass 13, count 0 2006.173.14:13:28.10#ibcon#about to read 6, iclass 13, count 0 2006.173.14:13:28.10#ibcon#read 6, iclass 13, count 0 2006.173.14:13:28.10#ibcon#end of sib2, iclass 13, count 0 2006.173.14:13:28.10#ibcon#*mode == 0, iclass 13, count 0 2006.173.14:13:28.10#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.14:13:28.10#ibcon#[27=USB\r\n] 2006.173.14:13:28.10#ibcon#*before write, iclass 13, count 0 2006.173.14:13:28.10#ibcon#enter sib2, iclass 13, count 0 2006.173.14:13:28.10#ibcon#flushed, iclass 13, count 0 2006.173.14:13:28.10#ibcon#about to write, iclass 13, count 0 2006.173.14:13:28.10#ibcon#wrote, iclass 13, count 0 2006.173.14:13:28.10#ibcon#about to read 3, iclass 13, count 0 2006.173.14:13:28.13#ibcon#read 3, iclass 13, count 0 2006.173.14:13:28.13#ibcon#about to read 4, iclass 13, count 0 2006.173.14:13:28.13#ibcon#read 4, iclass 13, count 0 2006.173.14:13:28.13#ibcon#about to read 5, iclass 13, count 0 2006.173.14:13:28.13#ibcon#read 5, iclass 13, count 0 2006.173.14:13:28.13#ibcon#about to read 6, iclass 13, count 0 2006.173.14:13:28.13#ibcon#read 6, iclass 13, count 0 2006.173.14:13:28.13#ibcon#end of sib2, iclass 13, count 0 2006.173.14:13:28.13#ibcon#*after write, iclass 13, count 0 2006.173.14:13:28.13#ibcon#*before return 0, iclass 13, count 0 2006.173.14:13:28.13#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.14:13:28.13#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.173.14:13:28.13#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.14:13:28.13#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.14:13:28.13$vck44/vblo=2,634.99 2006.173.14:13:28.13#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.14:13:28.13#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.14:13:28.13#ibcon#ireg 17 cls_cnt 0 2006.173.14:13:28.13#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.14:13:28.13#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.14:13:28.13#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.14:13:28.13#ibcon#enter wrdev, iclass 15, count 0 2006.173.14:13:28.13#ibcon#first serial, iclass 15, count 0 2006.173.14:13:28.13#ibcon#enter sib2, iclass 15, count 0 2006.173.14:13:28.13#ibcon#flushed, iclass 15, count 0 2006.173.14:13:28.13#ibcon#about to write, iclass 15, count 0 2006.173.14:13:28.13#ibcon#wrote, iclass 15, count 0 2006.173.14:13:28.13#ibcon#about to read 3, iclass 15, count 0 2006.173.14:13:28.15#ibcon#read 3, iclass 15, count 0 2006.173.14:13:28.15#ibcon#about to read 4, iclass 15, count 0 2006.173.14:13:28.15#ibcon#read 4, iclass 15, count 0 2006.173.14:13:28.15#ibcon#about to read 5, iclass 15, count 0 2006.173.14:13:28.15#ibcon#read 5, iclass 15, count 0 2006.173.14:13:28.15#ibcon#about to read 6, iclass 15, count 0 2006.173.14:13:28.15#ibcon#read 6, iclass 15, count 0 2006.173.14:13:28.15#ibcon#end of sib2, iclass 15, count 0 2006.173.14:13:28.15#ibcon#*mode == 0, iclass 15, count 0 2006.173.14:13:28.15#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.14:13:28.15#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.14:13:28.15#ibcon#*before write, iclass 15, count 0 2006.173.14:13:28.15#ibcon#enter sib2, iclass 15, count 0 2006.173.14:13:28.15#ibcon#flushed, iclass 15, count 0 2006.173.14:13:28.15#ibcon#about to write, iclass 15, count 0 2006.173.14:13:28.15#ibcon#wrote, iclass 15, count 0 2006.173.14:13:28.15#ibcon#about to read 3, iclass 15, count 0 2006.173.14:13:28.19#ibcon#read 3, iclass 15, count 0 2006.173.14:13:28.19#ibcon#about to read 4, iclass 15, count 0 2006.173.14:13:28.19#ibcon#read 4, iclass 15, count 0 2006.173.14:13:28.19#ibcon#about to read 5, iclass 15, count 0 2006.173.14:13:28.19#ibcon#read 5, iclass 15, count 0 2006.173.14:13:28.19#ibcon#about to read 6, iclass 15, count 0 2006.173.14:13:28.19#ibcon#read 6, iclass 15, count 0 2006.173.14:13:28.19#ibcon#end of sib2, iclass 15, count 0 2006.173.14:13:28.19#ibcon#*after write, iclass 15, count 0 2006.173.14:13:28.19#ibcon#*before return 0, iclass 15, count 0 2006.173.14:13:28.19#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.14:13:28.19#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.14:13:28.19#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.14:13:28.19#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.14:13:28.19$vck44/vb=2,4 2006.173.14:13:28.19#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.14:13:28.19#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.14:13:28.19#ibcon#ireg 11 cls_cnt 2 2006.173.14:13:28.19#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.14:13:28.25#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.14:13:28.25#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.14:13:28.25#ibcon#enter wrdev, iclass 17, count 2 2006.173.14:13:28.25#ibcon#first serial, iclass 17, count 2 2006.173.14:13:28.25#ibcon#enter sib2, iclass 17, count 2 2006.173.14:13:28.25#ibcon#flushed, iclass 17, count 2 2006.173.14:13:28.25#ibcon#about to write, iclass 17, count 2 2006.173.14:13:28.25#ibcon#wrote, iclass 17, count 2 2006.173.14:13:28.25#ibcon#about to read 3, iclass 17, count 2 2006.173.14:13:28.27#ibcon#read 3, iclass 17, count 2 2006.173.14:13:28.27#ibcon#about to read 4, iclass 17, count 2 2006.173.14:13:28.27#ibcon#read 4, iclass 17, count 2 2006.173.14:13:28.27#ibcon#about to read 5, iclass 17, count 2 2006.173.14:13:28.27#ibcon#read 5, iclass 17, count 2 2006.173.14:13:28.27#ibcon#about to read 6, iclass 17, count 2 2006.173.14:13:28.27#ibcon#read 6, iclass 17, count 2 2006.173.14:13:28.27#ibcon#end of sib2, iclass 17, count 2 2006.173.14:13:28.27#ibcon#*mode == 0, iclass 17, count 2 2006.173.14:13:28.27#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.14:13:28.27#ibcon#[27=AT02-04\r\n] 2006.173.14:13:28.27#ibcon#*before write, iclass 17, count 2 2006.173.14:13:28.27#ibcon#enter sib2, iclass 17, count 2 2006.173.14:13:28.27#ibcon#flushed, iclass 17, count 2 2006.173.14:13:28.27#ibcon#about to write, iclass 17, count 2 2006.173.14:13:28.27#ibcon#wrote, iclass 17, count 2 2006.173.14:13:28.27#ibcon#about to read 3, iclass 17, count 2 2006.173.14:13:28.30#ibcon#read 3, iclass 17, count 2 2006.173.14:13:28.30#ibcon#about to read 4, iclass 17, count 2 2006.173.14:13:28.30#ibcon#read 4, iclass 17, count 2 2006.173.14:13:28.30#ibcon#about to read 5, iclass 17, count 2 2006.173.14:13:28.30#ibcon#read 5, iclass 17, count 2 2006.173.14:13:28.30#ibcon#about to read 6, iclass 17, count 2 2006.173.14:13:28.30#ibcon#read 6, iclass 17, count 2 2006.173.14:13:28.30#ibcon#end of sib2, iclass 17, count 2 2006.173.14:13:28.30#ibcon#*after write, iclass 17, count 2 2006.173.14:13:28.30#ibcon#*before return 0, iclass 17, count 2 2006.173.14:13:28.30#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.14:13:28.30#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.14:13:28.30#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.14:13:28.30#ibcon#ireg 7 cls_cnt 0 2006.173.14:13:28.30#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.14:13:28.42#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.14:13:28.42#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.14:13:28.42#ibcon#enter wrdev, iclass 17, count 0 2006.173.14:13:28.42#ibcon#first serial, iclass 17, count 0 2006.173.14:13:28.42#ibcon#enter sib2, iclass 17, count 0 2006.173.14:13:28.42#ibcon#flushed, iclass 17, count 0 2006.173.14:13:28.42#ibcon#about to write, iclass 17, count 0 2006.173.14:13:28.42#ibcon#wrote, iclass 17, count 0 2006.173.14:13:28.42#ibcon#about to read 3, iclass 17, count 0 2006.173.14:13:28.44#ibcon#read 3, iclass 17, count 0 2006.173.14:13:28.44#ibcon#about to read 4, iclass 17, count 0 2006.173.14:13:28.44#ibcon#read 4, iclass 17, count 0 2006.173.14:13:28.44#ibcon#about to read 5, iclass 17, count 0 2006.173.14:13:28.44#ibcon#read 5, iclass 17, count 0 2006.173.14:13:28.44#ibcon#about to read 6, iclass 17, count 0 2006.173.14:13:28.44#ibcon#read 6, iclass 17, count 0 2006.173.14:13:28.44#ibcon#end of sib2, iclass 17, count 0 2006.173.14:13:28.44#ibcon#*mode == 0, iclass 17, count 0 2006.173.14:13:28.44#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.14:13:28.44#ibcon#[27=USB\r\n] 2006.173.14:13:28.44#ibcon#*before write, iclass 17, count 0 2006.173.14:13:28.44#ibcon#enter sib2, iclass 17, count 0 2006.173.14:13:28.44#ibcon#flushed, iclass 17, count 0 2006.173.14:13:28.44#ibcon#about to write, iclass 17, count 0 2006.173.14:13:28.44#ibcon#wrote, iclass 17, count 0 2006.173.14:13:28.44#ibcon#about to read 3, iclass 17, count 0 2006.173.14:13:28.47#ibcon#read 3, iclass 17, count 0 2006.173.14:13:28.47#ibcon#about to read 4, iclass 17, count 0 2006.173.14:13:28.47#ibcon#read 4, iclass 17, count 0 2006.173.14:13:28.47#ibcon#about to read 5, iclass 17, count 0 2006.173.14:13:28.47#ibcon#read 5, iclass 17, count 0 2006.173.14:13:28.47#ibcon#about to read 6, iclass 17, count 0 2006.173.14:13:28.47#ibcon#read 6, iclass 17, count 0 2006.173.14:13:28.47#ibcon#end of sib2, iclass 17, count 0 2006.173.14:13:28.47#ibcon#*after write, iclass 17, count 0 2006.173.14:13:28.47#ibcon#*before return 0, iclass 17, count 0 2006.173.14:13:28.47#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.14:13:28.47#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.14:13:28.47#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.14:13:28.47#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.14:13:28.47$vck44/vblo=3,649.99 2006.173.14:13:28.47#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.14:13:28.47#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.14:13:28.47#ibcon#ireg 17 cls_cnt 0 2006.173.14:13:28.47#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.14:13:28.47#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.14:13:28.47#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.14:13:28.47#ibcon#enter wrdev, iclass 19, count 0 2006.173.14:13:28.47#ibcon#first serial, iclass 19, count 0 2006.173.14:13:28.47#ibcon#enter sib2, iclass 19, count 0 2006.173.14:13:28.47#ibcon#flushed, iclass 19, count 0 2006.173.14:13:28.47#ibcon#about to write, iclass 19, count 0 2006.173.14:13:28.47#ibcon#wrote, iclass 19, count 0 2006.173.14:13:28.47#ibcon#about to read 3, iclass 19, count 0 2006.173.14:13:28.49#ibcon#read 3, iclass 19, count 0 2006.173.14:13:28.49#ibcon#about to read 4, iclass 19, count 0 2006.173.14:13:28.49#ibcon#read 4, iclass 19, count 0 2006.173.14:13:28.49#ibcon#about to read 5, iclass 19, count 0 2006.173.14:13:28.49#ibcon#read 5, iclass 19, count 0 2006.173.14:13:28.49#ibcon#about to read 6, iclass 19, count 0 2006.173.14:13:28.49#ibcon#read 6, iclass 19, count 0 2006.173.14:13:28.49#ibcon#end of sib2, iclass 19, count 0 2006.173.14:13:28.49#ibcon#*mode == 0, iclass 19, count 0 2006.173.14:13:28.49#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.14:13:28.49#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.14:13:28.49#ibcon#*before write, iclass 19, count 0 2006.173.14:13:28.49#ibcon#enter sib2, iclass 19, count 0 2006.173.14:13:28.49#ibcon#flushed, iclass 19, count 0 2006.173.14:13:28.49#ibcon#about to write, iclass 19, count 0 2006.173.14:13:28.49#ibcon#wrote, iclass 19, count 0 2006.173.14:13:28.49#ibcon#about to read 3, iclass 19, count 0 2006.173.14:13:28.53#ibcon#read 3, iclass 19, count 0 2006.173.14:13:28.53#ibcon#about to read 4, iclass 19, count 0 2006.173.14:13:28.53#ibcon#read 4, iclass 19, count 0 2006.173.14:13:28.53#ibcon#about to read 5, iclass 19, count 0 2006.173.14:13:28.53#ibcon#read 5, iclass 19, count 0 2006.173.14:13:28.53#ibcon#about to read 6, iclass 19, count 0 2006.173.14:13:28.53#ibcon#read 6, iclass 19, count 0 2006.173.14:13:28.53#ibcon#end of sib2, iclass 19, count 0 2006.173.14:13:28.53#ibcon#*after write, iclass 19, count 0 2006.173.14:13:28.53#ibcon#*before return 0, iclass 19, count 0 2006.173.14:13:28.53#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.14:13:28.53#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.14:13:28.53#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.14:13:28.53#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.14:13:28.53$vck44/vb=3,4 2006.173.14:13:28.53#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.14:13:28.53#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.14:13:28.53#ibcon#ireg 11 cls_cnt 2 2006.173.14:13:28.53#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.14:13:28.59#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.14:13:28.59#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.14:13:28.59#ibcon#enter wrdev, iclass 21, count 2 2006.173.14:13:28.59#ibcon#first serial, iclass 21, count 2 2006.173.14:13:28.59#ibcon#enter sib2, iclass 21, count 2 2006.173.14:13:28.59#ibcon#flushed, iclass 21, count 2 2006.173.14:13:28.59#ibcon#about to write, iclass 21, count 2 2006.173.14:13:28.59#ibcon#wrote, iclass 21, count 2 2006.173.14:13:28.59#ibcon#about to read 3, iclass 21, count 2 2006.173.14:13:28.61#ibcon#read 3, iclass 21, count 2 2006.173.14:13:28.61#ibcon#about to read 4, iclass 21, count 2 2006.173.14:13:28.61#ibcon#read 4, iclass 21, count 2 2006.173.14:13:28.61#ibcon#about to read 5, iclass 21, count 2 2006.173.14:13:28.61#ibcon#read 5, iclass 21, count 2 2006.173.14:13:28.61#ibcon#about to read 6, iclass 21, count 2 2006.173.14:13:28.61#ibcon#read 6, iclass 21, count 2 2006.173.14:13:28.61#ibcon#end of sib2, iclass 21, count 2 2006.173.14:13:28.61#ibcon#*mode == 0, iclass 21, count 2 2006.173.14:13:28.61#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.14:13:28.61#ibcon#[27=AT03-04\r\n] 2006.173.14:13:28.61#ibcon#*before write, iclass 21, count 2 2006.173.14:13:28.61#ibcon#enter sib2, iclass 21, count 2 2006.173.14:13:28.61#ibcon#flushed, iclass 21, count 2 2006.173.14:13:28.61#ibcon#about to write, iclass 21, count 2 2006.173.14:13:28.61#ibcon#wrote, iclass 21, count 2 2006.173.14:13:28.61#ibcon#about to read 3, iclass 21, count 2 2006.173.14:13:28.64#ibcon#read 3, iclass 21, count 2 2006.173.14:13:28.64#ibcon#about to read 4, iclass 21, count 2 2006.173.14:13:28.64#ibcon#read 4, iclass 21, count 2 2006.173.14:13:28.64#ibcon#about to read 5, iclass 21, count 2 2006.173.14:13:28.64#ibcon#read 5, iclass 21, count 2 2006.173.14:13:28.64#ibcon#about to read 6, iclass 21, count 2 2006.173.14:13:28.64#ibcon#read 6, iclass 21, count 2 2006.173.14:13:28.64#ibcon#end of sib2, iclass 21, count 2 2006.173.14:13:28.64#ibcon#*after write, iclass 21, count 2 2006.173.14:13:28.64#ibcon#*before return 0, iclass 21, count 2 2006.173.14:13:28.64#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.14:13:28.64#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.14:13:28.64#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.14:13:28.64#ibcon#ireg 7 cls_cnt 0 2006.173.14:13:28.64#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.14:13:28.76#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.14:13:28.76#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.14:13:28.76#ibcon#enter wrdev, iclass 21, count 0 2006.173.14:13:28.76#ibcon#first serial, iclass 21, count 0 2006.173.14:13:28.76#ibcon#enter sib2, iclass 21, count 0 2006.173.14:13:28.76#ibcon#flushed, iclass 21, count 0 2006.173.14:13:28.76#ibcon#about to write, iclass 21, count 0 2006.173.14:13:28.76#ibcon#wrote, iclass 21, count 0 2006.173.14:13:28.76#ibcon#about to read 3, iclass 21, count 0 2006.173.14:13:28.78#ibcon#read 3, iclass 21, count 0 2006.173.14:13:28.78#ibcon#about to read 4, iclass 21, count 0 2006.173.14:13:28.78#ibcon#read 4, iclass 21, count 0 2006.173.14:13:28.78#ibcon#about to read 5, iclass 21, count 0 2006.173.14:13:28.78#ibcon#read 5, iclass 21, count 0 2006.173.14:13:28.78#ibcon#about to read 6, iclass 21, count 0 2006.173.14:13:28.78#ibcon#read 6, iclass 21, count 0 2006.173.14:13:28.78#ibcon#end of sib2, iclass 21, count 0 2006.173.14:13:28.78#ibcon#*mode == 0, iclass 21, count 0 2006.173.14:13:28.78#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.14:13:28.78#ibcon#[27=USB\r\n] 2006.173.14:13:28.78#ibcon#*before write, iclass 21, count 0 2006.173.14:13:28.78#ibcon#enter sib2, iclass 21, count 0 2006.173.14:13:28.78#ibcon#flushed, iclass 21, count 0 2006.173.14:13:28.78#ibcon#about to write, iclass 21, count 0 2006.173.14:13:28.78#ibcon#wrote, iclass 21, count 0 2006.173.14:13:28.78#ibcon#about to read 3, iclass 21, count 0 2006.173.14:13:28.81#ibcon#read 3, iclass 21, count 0 2006.173.14:13:28.81#ibcon#about to read 4, iclass 21, count 0 2006.173.14:13:28.81#ibcon#read 4, iclass 21, count 0 2006.173.14:13:28.81#ibcon#about to read 5, iclass 21, count 0 2006.173.14:13:28.81#ibcon#read 5, iclass 21, count 0 2006.173.14:13:28.81#ibcon#about to read 6, iclass 21, count 0 2006.173.14:13:28.81#ibcon#read 6, iclass 21, count 0 2006.173.14:13:28.81#ibcon#end of sib2, iclass 21, count 0 2006.173.14:13:28.81#ibcon#*after write, iclass 21, count 0 2006.173.14:13:28.81#ibcon#*before return 0, iclass 21, count 0 2006.173.14:13:28.81#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.14:13:28.81#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.14:13:28.81#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.14:13:28.81#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.14:13:28.81$vck44/vblo=4,679.99 2006.173.14:13:28.81#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.14:13:28.81#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.14:13:28.81#ibcon#ireg 17 cls_cnt 0 2006.173.14:13:28.81#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.14:13:28.81#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.14:13:28.81#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.14:13:28.81#ibcon#enter wrdev, iclass 23, count 0 2006.173.14:13:28.81#ibcon#first serial, iclass 23, count 0 2006.173.14:13:28.81#ibcon#enter sib2, iclass 23, count 0 2006.173.14:13:28.81#ibcon#flushed, iclass 23, count 0 2006.173.14:13:28.81#ibcon#about to write, iclass 23, count 0 2006.173.14:13:28.81#ibcon#wrote, iclass 23, count 0 2006.173.14:13:28.81#ibcon#about to read 3, iclass 23, count 0 2006.173.14:13:28.83#ibcon#read 3, iclass 23, count 0 2006.173.14:13:28.83#ibcon#about to read 4, iclass 23, count 0 2006.173.14:13:28.83#ibcon#read 4, iclass 23, count 0 2006.173.14:13:28.83#ibcon#about to read 5, iclass 23, count 0 2006.173.14:13:28.83#ibcon#read 5, iclass 23, count 0 2006.173.14:13:28.83#ibcon#about to read 6, iclass 23, count 0 2006.173.14:13:28.83#ibcon#read 6, iclass 23, count 0 2006.173.14:13:28.83#ibcon#end of sib2, iclass 23, count 0 2006.173.14:13:28.83#ibcon#*mode == 0, iclass 23, count 0 2006.173.14:13:28.83#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.14:13:28.83#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.14:13:28.83#ibcon#*before write, iclass 23, count 0 2006.173.14:13:28.83#ibcon#enter sib2, iclass 23, count 0 2006.173.14:13:28.83#ibcon#flushed, iclass 23, count 0 2006.173.14:13:28.83#ibcon#about to write, iclass 23, count 0 2006.173.14:13:28.83#ibcon#wrote, iclass 23, count 0 2006.173.14:13:28.83#ibcon#about to read 3, iclass 23, count 0 2006.173.14:13:28.87#ibcon#read 3, iclass 23, count 0 2006.173.14:13:28.87#ibcon#about to read 4, iclass 23, count 0 2006.173.14:13:28.87#ibcon#read 4, iclass 23, count 0 2006.173.14:13:28.87#ibcon#about to read 5, iclass 23, count 0 2006.173.14:13:28.87#ibcon#read 5, iclass 23, count 0 2006.173.14:13:28.87#ibcon#about to read 6, iclass 23, count 0 2006.173.14:13:28.87#ibcon#read 6, iclass 23, count 0 2006.173.14:13:28.87#ibcon#end of sib2, iclass 23, count 0 2006.173.14:13:28.87#ibcon#*after write, iclass 23, count 0 2006.173.14:13:28.87#ibcon#*before return 0, iclass 23, count 0 2006.173.14:13:28.87#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.14:13:28.87#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.14:13:28.87#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.14:13:28.87#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.14:13:28.87$vck44/vb=4,4 2006.173.14:13:28.87#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.14:13:28.87#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.14:13:28.87#ibcon#ireg 11 cls_cnt 2 2006.173.14:13:28.87#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.14:13:28.93#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.14:13:28.93#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.14:13:28.93#ibcon#enter wrdev, iclass 25, count 2 2006.173.14:13:28.93#ibcon#first serial, iclass 25, count 2 2006.173.14:13:28.93#ibcon#enter sib2, iclass 25, count 2 2006.173.14:13:28.93#ibcon#flushed, iclass 25, count 2 2006.173.14:13:28.93#ibcon#about to write, iclass 25, count 2 2006.173.14:13:28.93#ibcon#wrote, iclass 25, count 2 2006.173.14:13:28.93#ibcon#about to read 3, iclass 25, count 2 2006.173.14:13:28.95#ibcon#read 3, iclass 25, count 2 2006.173.14:13:28.95#ibcon#about to read 4, iclass 25, count 2 2006.173.14:13:28.95#ibcon#read 4, iclass 25, count 2 2006.173.14:13:28.95#ibcon#about to read 5, iclass 25, count 2 2006.173.14:13:28.95#ibcon#read 5, iclass 25, count 2 2006.173.14:13:28.95#ibcon#about to read 6, iclass 25, count 2 2006.173.14:13:28.95#ibcon#read 6, iclass 25, count 2 2006.173.14:13:28.95#ibcon#end of sib2, iclass 25, count 2 2006.173.14:13:28.95#ibcon#*mode == 0, iclass 25, count 2 2006.173.14:13:28.95#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.14:13:28.95#ibcon#[27=AT04-04\r\n] 2006.173.14:13:28.95#ibcon#*before write, iclass 25, count 2 2006.173.14:13:28.95#ibcon#enter sib2, iclass 25, count 2 2006.173.14:13:28.95#ibcon#flushed, iclass 25, count 2 2006.173.14:13:28.95#ibcon#about to write, iclass 25, count 2 2006.173.14:13:28.95#ibcon#wrote, iclass 25, count 2 2006.173.14:13:28.95#ibcon#about to read 3, iclass 25, count 2 2006.173.14:13:28.98#ibcon#read 3, iclass 25, count 2 2006.173.14:13:28.98#ibcon#about to read 4, iclass 25, count 2 2006.173.14:13:28.98#ibcon#read 4, iclass 25, count 2 2006.173.14:13:28.98#ibcon#about to read 5, iclass 25, count 2 2006.173.14:13:28.98#ibcon#read 5, iclass 25, count 2 2006.173.14:13:28.98#ibcon#about to read 6, iclass 25, count 2 2006.173.14:13:28.98#ibcon#read 6, iclass 25, count 2 2006.173.14:13:28.98#ibcon#end of sib2, iclass 25, count 2 2006.173.14:13:28.98#ibcon#*after write, iclass 25, count 2 2006.173.14:13:28.98#ibcon#*before return 0, iclass 25, count 2 2006.173.14:13:28.98#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.14:13:28.98#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.14:13:28.98#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.14:13:28.98#ibcon#ireg 7 cls_cnt 0 2006.173.14:13:28.98#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.14:13:29.10#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.14:13:29.10#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.14:13:29.10#ibcon#enter wrdev, iclass 25, count 0 2006.173.14:13:29.10#ibcon#first serial, iclass 25, count 0 2006.173.14:13:29.10#ibcon#enter sib2, iclass 25, count 0 2006.173.14:13:29.10#ibcon#flushed, iclass 25, count 0 2006.173.14:13:29.10#ibcon#about to write, iclass 25, count 0 2006.173.14:13:29.10#ibcon#wrote, iclass 25, count 0 2006.173.14:13:29.10#ibcon#about to read 3, iclass 25, count 0 2006.173.14:13:29.12#ibcon#read 3, iclass 25, count 0 2006.173.14:13:29.12#ibcon#about to read 4, iclass 25, count 0 2006.173.14:13:29.12#ibcon#read 4, iclass 25, count 0 2006.173.14:13:29.12#ibcon#about to read 5, iclass 25, count 0 2006.173.14:13:29.12#ibcon#read 5, iclass 25, count 0 2006.173.14:13:29.12#ibcon#about to read 6, iclass 25, count 0 2006.173.14:13:29.12#ibcon#read 6, iclass 25, count 0 2006.173.14:13:29.12#ibcon#end of sib2, iclass 25, count 0 2006.173.14:13:29.12#ibcon#*mode == 0, iclass 25, count 0 2006.173.14:13:29.12#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.14:13:29.12#ibcon#[27=USB\r\n] 2006.173.14:13:29.12#ibcon#*before write, iclass 25, count 0 2006.173.14:13:29.12#ibcon#enter sib2, iclass 25, count 0 2006.173.14:13:29.12#ibcon#flushed, iclass 25, count 0 2006.173.14:13:29.12#ibcon#about to write, iclass 25, count 0 2006.173.14:13:29.12#ibcon#wrote, iclass 25, count 0 2006.173.14:13:29.12#ibcon#about to read 3, iclass 25, count 0 2006.173.14:13:29.15#ibcon#read 3, iclass 25, count 0 2006.173.14:13:29.15#ibcon#about to read 4, iclass 25, count 0 2006.173.14:13:29.15#ibcon#read 4, iclass 25, count 0 2006.173.14:13:29.15#ibcon#about to read 5, iclass 25, count 0 2006.173.14:13:29.15#ibcon#read 5, iclass 25, count 0 2006.173.14:13:29.15#ibcon#about to read 6, iclass 25, count 0 2006.173.14:13:29.15#ibcon#read 6, iclass 25, count 0 2006.173.14:13:29.15#ibcon#end of sib2, iclass 25, count 0 2006.173.14:13:29.15#ibcon#*after write, iclass 25, count 0 2006.173.14:13:29.15#ibcon#*before return 0, iclass 25, count 0 2006.173.14:13:29.15#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.14:13:29.15#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.14:13:29.15#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.14:13:29.15#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.14:13:29.15$vck44/vblo=5,709.99 2006.173.14:13:29.15#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.14:13:29.15#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.14:13:29.15#ibcon#ireg 17 cls_cnt 0 2006.173.14:13:29.15#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.14:13:29.15#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.14:13:29.15#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.14:13:29.15#ibcon#enter wrdev, iclass 27, count 0 2006.173.14:13:29.15#ibcon#first serial, iclass 27, count 0 2006.173.14:13:29.15#ibcon#enter sib2, iclass 27, count 0 2006.173.14:13:29.15#ibcon#flushed, iclass 27, count 0 2006.173.14:13:29.15#ibcon#about to write, iclass 27, count 0 2006.173.14:13:29.15#ibcon#wrote, iclass 27, count 0 2006.173.14:13:29.15#ibcon#about to read 3, iclass 27, count 0 2006.173.14:13:29.17#ibcon#read 3, iclass 27, count 0 2006.173.14:13:29.17#ibcon#about to read 4, iclass 27, count 0 2006.173.14:13:29.17#ibcon#read 4, iclass 27, count 0 2006.173.14:13:29.17#ibcon#about to read 5, iclass 27, count 0 2006.173.14:13:29.17#ibcon#read 5, iclass 27, count 0 2006.173.14:13:29.17#ibcon#about to read 6, iclass 27, count 0 2006.173.14:13:29.17#ibcon#read 6, iclass 27, count 0 2006.173.14:13:29.17#ibcon#end of sib2, iclass 27, count 0 2006.173.14:13:29.17#ibcon#*mode == 0, iclass 27, count 0 2006.173.14:13:29.17#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.14:13:29.17#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.14:13:29.17#ibcon#*before write, iclass 27, count 0 2006.173.14:13:29.17#ibcon#enter sib2, iclass 27, count 0 2006.173.14:13:29.17#ibcon#flushed, iclass 27, count 0 2006.173.14:13:29.17#ibcon#about to write, iclass 27, count 0 2006.173.14:13:29.17#ibcon#wrote, iclass 27, count 0 2006.173.14:13:29.17#ibcon#about to read 3, iclass 27, count 0 2006.173.14:13:29.21#ibcon#read 3, iclass 27, count 0 2006.173.14:13:29.21#ibcon#about to read 4, iclass 27, count 0 2006.173.14:13:29.21#ibcon#read 4, iclass 27, count 0 2006.173.14:13:29.21#ibcon#about to read 5, iclass 27, count 0 2006.173.14:13:29.21#ibcon#read 5, iclass 27, count 0 2006.173.14:13:29.21#ibcon#about to read 6, iclass 27, count 0 2006.173.14:13:29.21#ibcon#read 6, iclass 27, count 0 2006.173.14:13:29.21#ibcon#end of sib2, iclass 27, count 0 2006.173.14:13:29.21#ibcon#*after write, iclass 27, count 0 2006.173.14:13:29.21#ibcon#*before return 0, iclass 27, count 0 2006.173.14:13:29.21#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.14:13:29.21#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.14:13:29.21#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.14:13:29.21#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.14:13:29.21$vck44/vb=5,4 2006.173.14:13:29.21#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.14:13:29.21#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.14:13:29.21#ibcon#ireg 11 cls_cnt 2 2006.173.14:13:29.21#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.14:13:29.27#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.14:13:29.27#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.14:13:29.27#ibcon#enter wrdev, iclass 29, count 2 2006.173.14:13:29.27#ibcon#first serial, iclass 29, count 2 2006.173.14:13:29.27#ibcon#enter sib2, iclass 29, count 2 2006.173.14:13:29.27#ibcon#flushed, iclass 29, count 2 2006.173.14:13:29.27#ibcon#about to write, iclass 29, count 2 2006.173.14:13:29.27#ibcon#wrote, iclass 29, count 2 2006.173.14:13:29.27#ibcon#about to read 3, iclass 29, count 2 2006.173.14:13:29.29#ibcon#read 3, iclass 29, count 2 2006.173.14:13:29.29#ibcon#about to read 4, iclass 29, count 2 2006.173.14:13:29.29#ibcon#read 4, iclass 29, count 2 2006.173.14:13:29.29#ibcon#about to read 5, iclass 29, count 2 2006.173.14:13:29.29#ibcon#read 5, iclass 29, count 2 2006.173.14:13:29.29#ibcon#about to read 6, iclass 29, count 2 2006.173.14:13:29.29#ibcon#read 6, iclass 29, count 2 2006.173.14:13:29.29#ibcon#end of sib2, iclass 29, count 2 2006.173.14:13:29.29#ibcon#*mode == 0, iclass 29, count 2 2006.173.14:13:29.29#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.14:13:29.29#ibcon#[27=AT05-04\r\n] 2006.173.14:13:29.29#ibcon#*before write, iclass 29, count 2 2006.173.14:13:29.29#ibcon#enter sib2, iclass 29, count 2 2006.173.14:13:29.29#ibcon#flushed, iclass 29, count 2 2006.173.14:13:29.29#ibcon#about to write, iclass 29, count 2 2006.173.14:13:29.29#ibcon#wrote, iclass 29, count 2 2006.173.14:13:29.29#ibcon#about to read 3, iclass 29, count 2 2006.173.14:13:29.32#ibcon#read 3, iclass 29, count 2 2006.173.14:13:29.32#ibcon#about to read 4, iclass 29, count 2 2006.173.14:13:29.32#ibcon#read 4, iclass 29, count 2 2006.173.14:13:29.32#ibcon#about to read 5, iclass 29, count 2 2006.173.14:13:29.32#ibcon#read 5, iclass 29, count 2 2006.173.14:13:29.32#ibcon#about to read 6, iclass 29, count 2 2006.173.14:13:29.32#ibcon#read 6, iclass 29, count 2 2006.173.14:13:29.32#ibcon#end of sib2, iclass 29, count 2 2006.173.14:13:29.32#ibcon#*after write, iclass 29, count 2 2006.173.14:13:29.32#ibcon#*before return 0, iclass 29, count 2 2006.173.14:13:29.32#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.14:13:29.32#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.14:13:29.32#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.14:13:29.32#ibcon#ireg 7 cls_cnt 0 2006.173.14:13:29.32#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.14:13:29.44#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.14:13:29.44#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.14:13:29.44#ibcon#enter wrdev, iclass 29, count 0 2006.173.14:13:29.44#ibcon#first serial, iclass 29, count 0 2006.173.14:13:29.44#ibcon#enter sib2, iclass 29, count 0 2006.173.14:13:29.44#ibcon#flushed, iclass 29, count 0 2006.173.14:13:29.44#ibcon#about to write, iclass 29, count 0 2006.173.14:13:29.44#ibcon#wrote, iclass 29, count 0 2006.173.14:13:29.44#ibcon#about to read 3, iclass 29, count 0 2006.173.14:13:29.46#ibcon#read 3, iclass 29, count 0 2006.173.14:13:29.46#ibcon#about to read 4, iclass 29, count 0 2006.173.14:13:29.46#ibcon#read 4, iclass 29, count 0 2006.173.14:13:29.46#ibcon#about to read 5, iclass 29, count 0 2006.173.14:13:29.46#ibcon#read 5, iclass 29, count 0 2006.173.14:13:29.46#ibcon#about to read 6, iclass 29, count 0 2006.173.14:13:29.46#ibcon#read 6, iclass 29, count 0 2006.173.14:13:29.46#ibcon#end of sib2, iclass 29, count 0 2006.173.14:13:29.46#ibcon#*mode == 0, iclass 29, count 0 2006.173.14:13:29.46#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.14:13:29.46#ibcon#[27=USB\r\n] 2006.173.14:13:29.46#ibcon#*before write, iclass 29, count 0 2006.173.14:13:29.46#ibcon#enter sib2, iclass 29, count 0 2006.173.14:13:29.46#ibcon#flushed, iclass 29, count 0 2006.173.14:13:29.46#ibcon#about to write, iclass 29, count 0 2006.173.14:13:29.46#ibcon#wrote, iclass 29, count 0 2006.173.14:13:29.46#ibcon#about to read 3, iclass 29, count 0 2006.173.14:13:29.49#ibcon#read 3, iclass 29, count 0 2006.173.14:13:29.49#ibcon#about to read 4, iclass 29, count 0 2006.173.14:13:29.49#ibcon#read 4, iclass 29, count 0 2006.173.14:13:29.49#ibcon#about to read 5, iclass 29, count 0 2006.173.14:13:29.49#ibcon#read 5, iclass 29, count 0 2006.173.14:13:29.49#ibcon#about to read 6, iclass 29, count 0 2006.173.14:13:29.49#ibcon#read 6, iclass 29, count 0 2006.173.14:13:29.49#ibcon#end of sib2, iclass 29, count 0 2006.173.14:13:29.49#ibcon#*after write, iclass 29, count 0 2006.173.14:13:29.49#ibcon#*before return 0, iclass 29, count 0 2006.173.14:13:29.49#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.14:13:29.49#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.14:13:29.49#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.14:13:29.49#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.14:13:29.49$vck44/vblo=6,719.99 2006.173.14:13:29.49#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.14:13:29.49#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.14:13:29.49#ibcon#ireg 17 cls_cnt 0 2006.173.14:13:29.49#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.14:13:29.49#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.14:13:29.49#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.14:13:29.49#ibcon#enter wrdev, iclass 31, count 0 2006.173.14:13:29.49#ibcon#first serial, iclass 31, count 0 2006.173.14:13:29.49#ibcon#enter sib2, iclass 31, count 0 2006.173.14:13:29.49#ibcon#flushed, iclass 31, count 0 2006.173.14:13:29.49#ibcon#about to write, iclass 31, count 0 2006.173.14:13:29.49#ibcon#wrote, iclass 31, count 0 2006.173.14:13:29.49#ibcon#about to read 3, iclass 31, count 0 2006.173.14:13:29.51#ibcon#read 3, iclass 31, count 0 2006.173.14:13:29.51#ibcon#about to read 4, iclass 31, count 0 2006.173.14:13:29.51#ibcon#read 4, iclass 31, count 0 2006.173.14:13:29.51#ibcon#about to read 5, iclass 31, count 0 2006.173.14:13:29.51#ibcon#read 5, iclass 31, count 0 2006.173.14:13:29.51#ibcon#about to read 6, iclass 31, count 0 2006.173.14:13:29.51#ibcon#read 6, iclass 31, count 0 2006.173.14:13:29.51#ibcon#end of sib2, iclass 31, count 0 2006.173.14:13:29.51#ibcon#*mode == 0, iclass 31, count 0 2006.173.14:13:29.51#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.14:13:29.51#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.14:13:29.51#ibcon#*before write, iclass 31, count 0 2006.173.14:13:29.51#ibcon#enter sib2, iclass 31, count 0 2006.173.14:13:29.51#ibcon#flushed, iclass 31, count 0 2006.173.14:13:29.51#ibcon#about to write, iclass 31, count 0 2006.173.14:13:29.51#ibcon#wrote, iclass 31, count 0 2006.173.14:13:29.51#ibcon#about to read 3, iclass 31, count 0 2006.173.14:13:29.55#ibcon#read 3, iclass 31, count 0 2006.173.14:13:29.55#ibcon#about to read 4, iclass 31, count 0 2006.173.14:13:29.55#ibcon#read 4, iclass 31, count 0 2006.173.14:13:29.55#ibcon#about to read 5, iclass 31, count 0 2006.173.14:13:29.55#ibcon#read 5, iclass 31, count 0 2006.173.14:13:29.55#ibcon#about to read 6, iclass 31, count 0 2006.173.14:13:29.55#ibcon#read 6, iclass 31, count 0 2006.173.14:13:29.55#ibcon#end of sib2, iclass 31, count 0 2006.173.14:13:29.55#ibcon#*after write, iclass 31, count 0 2006.173.14:13:29.55#ibcon#*before return 0, iclass 31, count 0 2006.173.14:13:29.55#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.14:13:29.55#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.14:13:29.55#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.14:13:29.55#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.14:13:29.55$vck44/vb=6,4 2006.173.14:13:29.55#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.173.14:13:29.55#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.173.14:13:29.55#ibcon#ireg 11 cls_cnt 2 2006.173.14:13:29.55#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.14:13:29.61#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.14:13:29.61#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.14:13:29.61#ibcon#enter wrdev, iclass 33, count 2 2006.173.14:13:29.61#ibcon#first serial, iclass 33, count 2 2006.173.14:13:29.61#ibcon#enter sib2, iclass 33, count 2 2006.173.14:13:29.61#ibcon#flushed, iclass 33, count 2 2006.173.14:13:29.61#ibcon#about to write, iclass 33, count 2 2006.173.14:13:29.61#ibcon#wrote, iclass 33, count 2 2006.173.14:13:29.61#ibcon#about to read 3, iclass 33, count 2 2006.173.14:13:29.63#ibcon#read 3, iclass 33, count 2 2006.173.14:13:29.63#ibcon#about to read 4, iclass 33, count 2 2006.173.14:13:29.63#ibcon#read 4, iclass 33, count 2 2006.173.14:13:29.63#ibcon#about to read 5, iclass 33, count 2 2006.173.14:13:29.63#ibcon#read 5, iclass 33, count 2 2006.173.14:13:29.63#ibcon#about to read 6, iclass 33, count 2 2006.173.14:13:29.63#ibcon#read 6, iclass 33, count 2 2006.173.14:13:29.63#ibcon#end of sib2, iclass 33, count 2 2006.173.14:13:29.63#ibcon#*mode == 0, iclass 33, count 2 2006.173.14:13:29.63#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.173.14:13:29.63#ibcon#[27=AT06-04\r\n] 2006.173.14:13:29.63#ibcon#*before write, iclass 33, count 2 2006.173.14:13:29.63#ibcon#enter sib2, iclass 33, count 2 2006.173.14:13:29.63#ibcon#flushed, iclass 33, count 2 2006.173.14:13:29.63#ibcon#about to write, iclass 33, count 2 2006.173.14:13:29.63#ibcon#wrote, iclass 33, count 2 2006.173.14:13:29.63#ibcon#about to read 3, iclass 33, count 2 2006.173.14:13:29.66#ibcon#read 3, iclass 33, count 2 2006.173.14:13:29.66#ibcon#about to read 4, iclass 33, count 2 2006.173.14:13:29.66#ibcon#read 4, iclass 33, count 2 2006.173.14:13:29.66#ibcon#about to read 5, iclass 33, count 2 2006.173.14:13:29.66#ibcon#read 5, iclass 33, count 2 2006.173.14:13:29.66#ibcon#about to read 6, iclass 33, count 2 2006.173.14:13:29.66#ibcon#read 6, iclass 33, count 2 2006.173.14:13:29.66#ibcon#end of sib2, iclass 33, count 2 2006.173.14:13:29.66#ibcon#*after write, iclass 33, count 2 2006.173.14:13:29.66#ibcon#*before return 0, iclass 33, count 2 2006.173.14:13:29.66#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.14:13:29.66#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.173.14:13:29.66#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.173.14:13:29.66#ibcon#ireg 7 cls_cnt 0 2006.173.14:13:29.66#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.14:13:29.78#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.14:13:29.78#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.14:13:29.78#ibcon#enter wrdev, iclass 33, count 0 2006.173.14:13:29.78#ibcon#first serial, iclass 33, count 0 2006.173.14:13:29.78#ibcon#enter sib2, iclass 33, count 0 2006.173.14:13:29.78#ibcon#flushed, iclass 33, count 0 2006.173.14:13:29.78#ibcon#about to write, iclass 33, count 0 2006.173.14:13:29.78#ibcon#wrote, iclass 33, count 0 2006.173.14:13:29.78#ibcon#about to read 3, iclass 33, count 0 2006.173.14:13:29.80#ibcon#read 3, iclass 33, count 0 2006.173.14:13:29.80#ibcon#about to read 4, iclass 33, count 0 2006.173.14:13:29.80#ibcon#read 4, iclass 33, count 0 2006.173.14:13:29.80#ibcon#about to read 5, iclass 33, count 0 2006.173.14:13:29.80#ibcon#read 5, iclass 33, count 0 2006.173.14:13:29.80#ibcon#about to read 6, iclass 33, count 0 2006.173.14:13:29.80#ibcon#read 6, iclass 33, count 0 2006.173.14:13:29.80#ibcon#end of sib2, iclass 33, count 0 2006.173.14:13:29.80#ibcon#*mode == 0, iclass 33, count 0 2006.173.14:13:29.80#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.14:13:29.80#ibcon#[27=USB\r\n] 2006.173.14:13:29.80#ibcon#*before write, iclass 33, count 0 2006.173.14:13:29.80#ibcon#enter sib2, iclass 33, count 0 2006.173.14:13:29.80#ibcon#flushed, iclass 33, count 0 2006.173.14:13:29.80#ibcon#about to write, iclass 33, count 0 2006.173.14:13:29.80#ibcon#wrote, iclass 33, count 0 2006.173.14:13:29.80#ibcon#about to read 3, iclass 33, count 0 2006.173.14:13:29.83#ibcon#read 3, iclass 33, count 0 2006.173.14:13:29.83#ibcon#about to read 4, iclass 33, count 0 2006.173.14:13:29.83#ibcon#read 4, iclass 33, count 0 2006.173.14:13:29.83#ibcon#about to read 5, iclass 33, count 0 2006.173.14:13:29.83#ibcon#read 5, iclass 33, count 0 2006.173.14:13:29.83#ibcon#about to read 6, iclass 33, count 0 2006.173.14:13:29.83#ibcon#read 6, iclass 33, count 0 2006.173.14:13:29.83#ibcon#end of sib2, iclass 33, count 0 2006.173.14:13:29.83#ibcon#*after write, iclass 33, count 0 2006.173.14:13:29.83#ibcon#*before return 0, iclass 33, count 0 2006.173.14:13:29.83#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.14:13:29.83#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.173.14:13:29.83#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.14:13:29.83#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.14:13:29.83$vck44/vblo=7,734.99 2006.173.14:13:29.83#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.14:13:29.83#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.14:13:29.83#ibcon#ireg 17 cls_cnt 0 2006.173.14:13:29.83#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.14:13:29.83#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.14:13:29.83#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.14:13:29.83#ibcon#enter wrdev, iclass 35, count 0 2006.173.14:13:29.83#ibcon#first serial, iclass 35, count 0 2006.173.14:13:29.83#ibcon#enter sib2, iclass 35, count 0 2006.173.14:13:29.83#ibcon#flushed, iclass 35, count 0 2006.173.14:13:29.83#ibcon#about to write, iclass 35, count 0 2006.173.14:13:29.83#ibcon#wrote, iclass 35, count 0 2006.173.14:13:29.83#ibcon#about to read 3, iclass 35, count 0 2006.173.14:13:29.85#ibcon#read 3, iclass 35, count 0 2006.173.14:13:29.85#ibcon#about to read 4, iclass 35, count 0 2006.173.14:13:29.85#ibcon#read 4, iclass 35, count 0 2006.173.14:13:29.85#ibcon#about to read 5, iclass 35, count 0 2006.173.14:13:29.85#ibcon#read 5, iclass 35, count 0 2006.173.14:13:29.85#ibcon#about to read 6, iclass 35, count 0 2006.173.14:13:29.85#ibcon#read 6, iclass 35, count 0 2006.173.14:13:29.85#ibcon#end of sib2, iclass 35, count 0 2006.173.14:13:29.85#ibcon#*mode == 0, iclass 35, count 0 2006.173.14:13:29.85#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.14:13:29.85#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.14:13:29.85#ibcon#*before write, iclass 35, count 0 2006.173.14:13:29.85#ibcon#enter sib2, iclass 35, count 0 2006.173.14:13:29.85#ibcon#flushed, iclass 35, count 0 2006.173.14:13:29.85#ibcon#about to write, iclass 35, count 0 2006.173.14:13:29.85#ibcon#wrote, iclass 35, count 0 2006.173.14:13:29.85#ibcon#about to read 3, iclass 35, count 0 2006.173.14:13:29.89#ibcon#read 3, iclass 35, count 0 2006.173.14:13:29.89#ibcon#about to read 4, iclass 35, count 0 2006.173.14:13:29.89#ibcon#read 4, iclass 35, count 0 2006.173.14:13:29.89#ibcon#about to read 5, iclass 35, count 0 2006.173.14:13:29.89#ibcon#read 5, iclass 35, count 0 2006.173.14:13:29.89#ibcon#about to read 6, iclass 35, count 0 2006.173.14:13:29.89#ibcon#read 6, iclass 35, count 0 2006.173.14:13:29.89#ibcon#end of sib2, iclass 35, count 0 2006.173.14:13:29.89#ibcon#*after write, iclass 35, count 0 2006.173.14:13:29.89#ibcon#*before return 0, iclass 35, count 0 2006.173.14:13:29.89#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.14:13:29.89#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.14:13:29.89#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.14:13:29.89#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.14:13:29.89$vck44/vb=7,4 2006.173.14:13:29.89#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.173.14:13:29.89#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.173.14:13:29.89#ibcon#ireg 11 cls_cnt 2 2006.173.14:13:29.89#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.14:13:29.95#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.14:13:29.95#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.14:13:29.95#ibcon#enter wrdev, iclass 37, count 2 2006.173.14:13:29.95#ibcon#first serial, iclass 37, count 2 2006.173.14:13:29.95#ibcon#enter sib2, iclass 37, count 2 2006.173.14:13:29.95#ibcon#flushed, iclass 37, count 2 2006.173.14:13:29.95#ibcon#about to write, iclass 37, count 2 2006.173.14:13:29.95#ibcon#wrote, iclass 37, count 2 2006.173.14:13:29.95#ibcon#about to read 3, iclass 37, count 2 2006.173.14:13:29.97#ibcon#read 3, iclass 37, count 2 2006.173.14:13:29.97#ibcon#about to read 4, iclass 37, count 2 2006.173.14:13:29.97#ibcon#read 4, iclass 37, count 2 2006.173.14:13:29.97#ibcon#about to read 5, iclass 37, count 2 2006.173.14:13:29.97#ibcon#read 5, iclass 37, count 2 2006.173.14:13:29.97#ibcon#about to read 6, iclass 37, count 2 2006.173.14:13:29.97#ibcon#read 6, iclass 37, count 2 2006.173.14:13:29.97#ibcon#end of sib2, iclass 37, count 2 2006.173.14:13:29.97#ibcon#*mode == 0, iclass 37, count 2 2006.173.14:13:29.97#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.173.14:13:29.97#ibcon#[27=AT07-04\r\n] 2006.173.14:13:29.97#ibcon#*before write, iclass 37, count 2 2006.173.14:13:29.97#ibcon#enter sib2, iclass 37, count 2 2006.173.14:13:29.97#ibcon#flushed, iclass 37, count 2 2006.173.14:13:29.97#ibcon#about to write, iclass 37, count 2 2006.173.14:13:29.97#ibcon#wrote, iclass 37, count 2 2006.173.14:13:29.97#ibcon#about to read 3, iclass 37, count 2 2006.173.14:13:30.00#ibcon#read 3, iclass 37, count 2 2006.173.14:13:30.00#ibcon#about to read 4, iclass 37, count 2 2006.173.14:13:30.00#ibcon#read 4, iclass 37, count 2 2006.173.14:13:30.00#ibcon#about to read 5, iclass 37, count 2 2006.173.14:13:30.00#ibcon#read 5, iclass 37, count 2 2006.173.14:13:30.00#ibcon#about to read 6, iclass 37, count 2 2006.173.14:13:30.00#ibcon#read 6, iclass 37, count 2 2006.173.14:13:30.00#ibcon#end of sib2, iclass 37, count 2 2006.173.14:13:30.00#ibcon#*after write, iclass 37, count 2 2006.173.14:13:30.00#ibcon#*before return 0, iclass 37, count 2 2006.173.14:13:30.00#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.14:13:30.00#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.173.14:13:30.00#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.173.14:13:30.00#ibcon#ireg 7 cls_cnt 0 2006.173.14:13:30.00#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.14:13:30.12#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.14:13:30.12#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.14:13:30.12#ibcon#enter wrdev, iclass 37, count 0 2006.173.14:13:30.12#ibcon#first serial, iclass 37, count 0 2006.173.14:13:30.12#ibcon#enter sib2, iclass 37, count 0 2006.173.14:13:30.12#ibcon#flushed, iclass 37, count 0 2006.173.14:13:30.12#ibcon#about to write, iclass 37, count 0 2006.173.14:13:30.12#ibcon#wrote, iclass 37, count 0 2006.173.14:13:30.12#ibcon#about to read 3, iclass 37, count 0 2006.173.14:13:30.14#ibcon#read 3, iclass 37, count 0 2006.173.14:13:30.14#ibcon#about to read 4, iclass 37, count 0 2006.173.14:13:30.14#ibcon#read 4, iclass 37, count 0 2006.173.14:13:30.14#ibcon#about to read 5, iclass 37, count 0 2006.173.14:13:30.14#ibcon#read 5, iclass 37, count 0 2006.173.14:13:30.14#ibcon#about to read 6, iclass 37, count 0 2006.173.14:13:30.14#ibcon#read 6, iclass 37, count 0 2006.173.14:13:30.14#ibcon#end of sib2, iclass 37, count 0 2006.173.14:13:30.14#ibcon#*mode == 0, iclass 37, count 0 2006.173.14:13:30.14#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.14:13:30.14#ibcon#[27=USB\r\n] 2006.173.14:13:30.14#ibcon#*before write, iclass 37, count 0 2006.173.14:13:30.14#ibcon#enter sib2, iclass 37, count 0 2006.173.14:13:30.14#ibcon#flushed, iclass 37, count 0 2006.173.14:13:30.14#ibcon#about to write, iclass 37, count 0 2006.173.14:13:30.14#ibcon#wrote, iclass 37, count 0 2006.173.14:13:30.14#ibcon#about to read 3, iclass 37, count 0 2006.173.14:13:30.17#ibcon#read 3, iclass 37, count 0 2006.173.14:13:30.17#ibcon#about to read 4, iclass 37, count 0 2006.173.14:13:30.17#ibcon#read 4, iclass 37, count 0 2006.173.14:13:30.17#ibcon#about to read 5, iclass 37, count 0 2006.173.14:13:30.17#ibcon#read 5, iclass 37, count 0 2006.173.14:13:30.17#ibcon#about to read 6, iclass 37, count 0 2006.173.14:13:30.17#ibcon#read 6, iclass 37, count 0 2006.173.14:13:30.17#ibcon#end of sib2, iclass 37, count 0 2006.173.14:13:30.17#ibcon#*after write, iclass 37, count 0 2006.173.14:13:30.17#ibcon#*before return 0, iclass 37, count 0 2006.173.14:13:30.17#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.14:13:30.17#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.173.14:13:30.17#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.14:13:30.17#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.14:13:30.17$vck44/vblo=8,744.99 2006.173.14:13:30.17#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.14:13:30.17#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.14:13:30.17#ibcon#ireg 17 cls_cnt 0 2006.173.14:13:30.17#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.14:13:30.17#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.14:13:30.17#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.14:13:30.17#ibcon#enter wrdev, iclass 39, count 0 2006.173.14:13:30.17#ibcon#first serial, iclass 39, count 0 2006.173.14:13:30.17#ibcon#enter sib2, iclass 39, count 0 2006.173.14:13:30.17#ibcon#flushed, iclass 39, count 0 2006.173.14:13:30.17#ibcon#about to write, iclass 39, count 0 2006.173.14:13:30.17#ibcon#wrote, iclass 39, count 0 2006.173.14:13:30.17#ibcon#about to read 3, iclass 39, count 0 2006.173.14:13:30.19#ibcon#read 3, iclass 39, count 0 2006.173.14:13:30.19#ibcon#about to read 4, iclass 39, count 0 2006.173.14:13:30.19#ibcon#read 4, iclass 39, count 0 2006.173.14:13:30.19#ibcon#about to read 5, iclass 39, count 0 2006.173.14:13:30.19#ibcon#read 5, iclass 39, count 0 2006.173.14:13:30.19#ibcon#about to read 6, iclass 39, count 0 2006.173.14:13:30.19#ibcon#read 6, iclass 39, count 0 2006.173.14:13:30.19#ibcon#end of sib2, iclass 39, count 0 2006.173.14:13:30.19#ibcon#*mode == 0, iclass 39, count 0 2006.173.14:13:30.19#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.14:13:30.19#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.14:13:30.19#ibcon#*before write, iclass 39, count 0 2006.173.14:13:30.19#ibcon#enter sib2, iclass 39, count 0 2006.173.14:13:30.19#ibcon#flushed, iclass 39, count 0 2006.173.14:13:30.19#ibcon#about to write, iclass 39, count 0 2006.173.14:13:30.19#ibcon#wrote, iclass 39, count 0 2006.173.14:13:30.19#ibcon#about to read 3, iclass 39, count 0 2006.173.14:13:30.23#ibcon#read 3, iclass 39, count 0 2006.173.14:13:30.23#ibcon#about to read 4, iclass 39, count 0 2006.173.14:13:30.23#ibcon#read 4, iclass 39, count 0 2006.173.14:13:30.23#ibcon#about to read 5, iclass 39, count 0 2006.173.14:13:30.23#ibcon#read 5, iclass 39, count 0 2006.173.14:13:30.23#ibcon#about to read 6, iclass 39, count 0 2006.173.14:13:30.23#ibcon#read 6, iclass 39, count 0 2006.173.14:13:30.23#ibcon#end of sib2, iclass 39, count 0 2006.173.14:13:30.23#ibcon#*after write, iclass 39, count 0 2006.173.14:13:30.23#ibcon#*before return 0, iclass 39, count 0 2006.173.14:13:30.23#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.14:13:30.23#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.14:13:30.23#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.14:13:30.23#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.14:13:30.23$vck44/vb=8,4 2006.173.14:13:30.23#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.14:13:30.23#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.14:13:30.23#ibcon#ireg 11 cls_cnt 2 2006.173.14:13:30.23#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.14:13:30.29#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.14:13:30.29#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.14:13:30.29#ibcon#enter wrdev, iclass 3, count 2 2006.173.14:13:30.29#ibcon#first serial, iclass 3, count 2 2006.173.14:13:30.29#ibcon#enter sib2, iclass 3, count 2 2006.173.14:13:30.29#ibcon#flushed, iclass 3, count 2 2006.173.14:13:30.29#ibcon#about to write, iclass 3, count 2 2006.173.14:13:30.29#ibcon#wrote, iclass 3, count 2 2006.173.14:13:30.29#ibcon#about to read 3, iclass 3, count 2 2006.173.14:13:30.31#ibcon#read 3, iclass 3, count 2 2006.173.14:13:30.31#ibcon#about to read 4, iclass 3, count 2 2006.173.14:13:30.31#ibcon#read 4, iclass 3, count 2 2006.173.14:13:30.31#ibcon#about to read 5, iclass 3, count 2 2006.173.14:13:30.31#ibcon#read 5, iclass 3, count 2 2006.173.14:13:30.31#ibcon#about to read 6, iclass 3, count 2 2006.173.14:13:30.31#ibcon#read 6, iclass 3, count 2 2006.173.14:13:30.31#ibcon#end of sib2, iclass 3, count 2 2006.173.14:13:30.31#ibcon#*mode == 0, iclass 3, count 2 2006.173.14:13:30.31#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.14:13:30.31#ibcon#[27=AT08-04\r\n] 2006.173.14:13:30.31#ibcon#*before write, iclass 3, count 2 2006.173.14:13:30.31#ibcon#enter sib2, iclass 3, count 2 2006.173.14:13:30.31#ibcon#flushed, iclass 3, count 2 2006.173.14:13:30.31#ibcon#about to write, iclass 3, count 2 2006.173.14:13:30.31#ibcon#wrote, iclass 3, count 2 2006.173.14:13:30.31#ibcon#about to read 3, iclass 3, count 2 2006.173.14:13:30.34#ibcon#read 3, iclass 3, count 2 2006.173.14:13:30.34#ibcon#about to read 4, iclass 3, count 2 2006.173.14:13:30.34#ibcon#read 4, iclass 3, count 2 2006.173.14:13:30.34#ibcon#about to read 5, iclass 3, count 2 2006.173.14:13:30.34#ibcon#read 5, iclass 3, count 2 2006.173.14:13:30.34#ibcon#about to read 6, iclass 3, count 2 2006.173.14:13:30.34#ibcon#read 6, iclass 3, count 2 2006.173.14:13:30.34#ibcon#end of sib2, iclass 3, count 2 2006.173.14:13:30.34#ibcon#*after write, iclass 3, count 2 2006.173.14:13:30.34#ibcon#*before return 0, iclass 3, count 2 2006.173.14:13:30.34#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.14:13:30.34#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.14:13:30.34#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.14:13:30.34#ibcon#ireg 7 cls_cnt 0 2006.173.14:13:30.34#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.14:13:30.46#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.14:13:30.46#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.14:13:30.46#ibcon#enter wrdev, iclass 3, count 0 2006.173.14:13:30.46#ibcon#first serial, iclass 3, count 0 2006.173.14:13:30.46#ibcon#enter sib2, iclass 3, count 0 2006.173.14:13:30.46#ibcon#flushed, iclass 3, count 0 2006.173.14:13:30.46#ibcon#about to write, iclass 3, count 0 2006.173.14:13:30.46#ibcon#wrote, iclass 3, count 0 2006.173.14:13:30.46#ibcon#about to read 3, iclass 3, count 0 2006.173.14:13:30.48#ibcon#read 3, iclass 3, count 0 2006.173.14:13:30.48#ibcon#about to read 4, iclass 3, count 0 2006.173.14:13:30.48#ibcon#read 4, iclass 3, count 0 2006.173.14:13:30.48#ibcon#about to read 5, iclass 3, count 0 2006.173.14:13:30.48#ibcon#read 5, iclass 3, count 0 2006.173.14:13:30.48#ibcon#about to read 6, iclass 3, count 0 2006.173.14:13:30.48#ibcon#read 6, iclass 3, count 0 2006.173.14:13:30.48#ibcon#end of sib2, iclass 3, count 0 2006.173.14:13:30.48#ibcon#*mode == 0, iclass 3, count 0 2006.173.14:13:30.48#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.14:13:30.48#ibcon#[27=USB\r\n] 2006.173.14:13:30.48#ibcon#*before write, iclass 3, count 0 2006.173.14:13:30.48#ibcon#enter sib2, iclass 3, count 0 2006.173.14:13:30.48#ibcon#flushed, iclass 3, count 0 2006.173.14:13:30.48#ibcon#about to write, iclass 3, count 0 2006.173.14:13:30.48#ibcon#wrote, iclass 3, count 0 2006.173.14:13:30.48#ibcon#about to read 3, iclass 3, count 0 2006.173.14:13:30.51#ibcon#read 3, iclass 3, count 0 2006.173.14:13:30.51#ibcon#about to read 4, iclass 3, count 0 2006.173.14:13:30.51#ibcon#read 4, iclass 3, count 0 2006.173.14:13:30.51#ibcon#about to read 5, iclass 3, count 0 2006.173.14:13:30.51#ibcon#read 5, iclass 3, count 0 2006.173.14:13:30.51#ibcon#about to read 6, iclass 3, count 0 2006.173.14:13:30.51#ibcon#read 6, iclass 3, count 0 2006.173.14:13:30.51#ibcon#end of sib2, iclass 3, count 0 2006.173.14:13:30.51#ibcon#*after write, iclass 3, count 0 2006.173.14:13:30.51#ibcon#*before return 0, iclass 3, count 0 2006.173.14:13:30.51#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.14:13:30.51#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.14:13:30.51#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.14:13:30.51#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.14:13:30.51$vck44/vabw=wide 2006.173.14:13:30.51#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.14:13:30.51#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.14:13:30.51#ibcon#ireg 8 cls_cnt 0 2006.173.14:13:30.51#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.14:13:30.51#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.14:13:30.51#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.14:13:30.51#ibcon#enter wrdev, iclass 5, count 0 2006.173.14:13:30.51#ibcon#first serial, iclass 5, count 0 2006.173.14:13:30.51#ibcon#enter sib2, iclass 5, count 0 2006.173.14:13:30.51#ibcon#flushed, iclass 5, count 0 2006.173.14:13:30.51#ibcon#about to write, iclass 5, count 0 2006.173.14:13:30.51#ibcon#wrote, iclass 5, count 0 2006.173.14:13:30.51#ibcon#about to read 3, iclass 5, count 0 2006.173.14:13:30.53#ibcon#read 3, iclass 5, count 0 2006.173.14:13:30.53#ibcon#about to read 4, iclass 5, count 0 2006.173.14:13:30.53#ibcon#read 4, iclass 5, count 0 2006.173.14:13:30.53#ibcon#about to read 5, iclass 5, count 0 2006.173.14:13:30.53#ibcon#read 5, iclass 5, count 0 2006.173.14:13:30.53#ibcon#about to read 6, iclass 5, count 0 2006.173.14:13:30.53#ibcon#read 6, iclass 5, count 0 2006.173.14:13:30.53#ibcon#end of sib2, iclass 5, count 0 2006.173.14:13:30.53#ibcon#*mode == 0, iclass 5, count 0 2006.173.14:13:30.53#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.14:13:30.53#ibcon#[25=BW32\r\n] 2006.173.14:13:30.53#ibcon#*before write, iclass 5, count 0 2006.173.14:13:30.53#ibcon#enter sib2, iclass 5, count 0 2006.173.14:13:30.53#ibcon#flushed, iclass 5, count 0 2006.173.14:13:30.53#ibcon#about to write, iclass 5, count 0 2006.173.14:13:30.53#ibcon#wrote, iclass 5, count 0 2006.173.14:13:30.53#ibcon#about to read 3, iclass 5, count 0 2006.173.14:13:30.56#ibcon#read 3, iclass 5, count 0 2006.173.14:13:30.56#ibcon#about to read 4, iclass 5, count 0 2006.173.14:13:30.56#ibcon#read 4, iclass 5, count 0 2006.173.14:13:30.56#ibcon#about to read 5, iclass 5, count 0 2006.173.14:13:30.56#ibcon#read 5, iclass 5, count 0 2006.173.14:13:30.56#ibcon#about to read 6, iclass 5, count 0 2006.173.14:13:30.56#ibcon#read 6, iclass 5, count 0 2006.173.14:13:30.56#ibcon#end of sib2, iclass 5, count 0 2006.173.14:13:30.56#ibcon#*after write, iclass 5, count 0 2006.173.14:13:30.56#ibcon#*before return 0, iclass 5, count 0 2006.173.14:13:30.56#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.14:13:30.56#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.14:13:30.56#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.14:13:30.56#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.14:13:30.56$vck44/vbbw=wide 2006.173.14:13:30.56#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.14:13:30.56#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.14:13:30.56#ibcon#ireg 8 cls_cnt 0 2006.173.14:13:30.56#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.14:13:30.63#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.14:13:30.63#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.14:13:30.63#ibcon#enter wrdev, iclass 7, count 0 2006.173.14:13:30.63#ibcon#first serial, iclass 7, count 0 2006.173.14:13:30.63#ibcon#enter sib2, iclass 7, count 0 2006.173.14:13:30.63#ibcon#flushed, iclass 7, count 0 2006.173.14:13:30.63#ibcon#about to write, iclass 7, count 0 2006.173.14:13:30.63#ibcon#wrote, iclass 7, count 0 2006.173.14:13:30.63#ibcon#about to read 3, iclass 7, count 0 2006.173.14:13:30.65#ibcon#read 3, iclass 7, count 0 2006.173.14:13:30.65#ibcon#about to read 4, iclass 7, count 0 2006.173.14:13:30.65#ibcon#read 4, iclass 7, count 0 2006.173.14:13:30.65#ibcon#about to read 5, iclass 7, count 0 2006.173.14:13:30.65#ibcon#read 5, iclass 7, count 0 2006.173.14:13:30.65#ibcon#about to read 6, iclass 7, count 0 2006.173.14:13:30.65#ibcon#read 6, iclass 7, count 0 2006.173.14:13:30.65#ibcon#end of sib2, iclass 7, count 0 2006.173.14:13:30.65#ibcon#*mode == 0, iclass 7, count 0 2006.173.14:13:30.65#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.14:13:30.65#ibcon#[27=BW32\r\n] 2006.173.14:13:30.65#ibcon#*before write, iclass 7, count 0 2006.173.14:13:30.65#ibcon#enter sib2, iclass 7, count 0 2006.173.14:13:30.65#ibcon#flushed, iclass 7, count 0 2006.173.14:13:30.65#ibcon#about to write, iclass 7, count 0 2006.173.14:13:30.65#ibcon#wrote, iclass 7, count 0 2006.173.14:13:30.65#ibcon#about to read 3, iclass 7, count 0 2006.173.14:13:30.68#ibcon#read 3, iclass 7, count 0 2006.173.14:13:30.68#ibcon#about to read 4, iclass 7, count 0 2006.173.14:13:30.68#ibcon#read 4, iclass 7, count 0 2006.173.14:13:30.68#ibcon#about to read 5, iclass 7, count 0 2006.173.14:13:30.68#ibcon#read 5, iclass 7, count 0 2006.173.14:13:30.68#ibcon#about to read 6, iclass 7, count 0 2006.173.14:13:30.68#ibcon#read 6, iclass 7, count 0 2006.173.14:13:30.68#ibcon#end of sib2, iclass 7, count 0 2006.173.14:13:30.68#ibcon#*after write, iclass 7, count 0 2006.173.14:13:30.68#ibcon#*before return 0, iclass 7, count 0 2006.173.14:13:30.68#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.14:13:30.68#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.14:13:30.68#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.14:13:30.68#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.14:13:30.68$setupk4/ifdk4 2006.173.14:13:30.68$ifdk4/lo= 2006.173.14:13:30.68$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.14:13:30.68$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.14:13:30.69$ifdk4/patch= 2006.173.14:13:30.69$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.14:13:30.69$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.14:13:30.69$setupk4/!*+20s 2006.173.14:13:36.15#abcon#<5=/02 0.5 1.1 21.651001003.8\r\n> 2006.173.14:13:36.17#abcon#{5=INTERFACE CLEAR} 2006.173.14:13:36.23#abcon#[5=S1D000X0/0*\r\n] 2006.173.14:13:43.14#trakl#Source acquired 2006.173.14:13:44.14#flagr#flagr/antenna,acquired 2006.173.14:13:45.21$setupk4/"tpicd 2006.173.14:13:45.21$setupk4/echo=off 2006.173.14:13:45.21$setupk4/xlog=off 2006.173.14:13:45.21:!2006.173.14:14:30 2006.173.14:14:30.00:preob 2006.173.14:14:30.14/onsource/TRACKING 2006.173.14:14:30.14:!2006.173.14:14:40 2006.173.14:14:40.00:"tape 2006.173.14:14:40.00:"st=record 2006.173.14:14:40.00:data_valid=on 2006.173.14:14:40.00:midob 2006.173.14:14:41.14/onsource/TRACKING 2006.173.14:14:41.14/wx/21.63,1003.8,100 2006.173.14:14:41.21/cable/+6.5059E-03 2006.173.14:14:42.30/va/01,07,usb,yes,46,49 2006.173.14:14:42.30/va/02,06,usb,yes,46,47 2006.173.14:14:42.30/va/03,05,usb,yes,58,60 2006.173.14:14:42.30/va/04,06,usb,yes,47,50 2006.173.14:14:42.30/va/05,04,usb,yes,37,38 2006.173.14:14:42.30/va/06,03,usb,yes,52,52 2006.173.14:14:42.30/va/07,04,usb,yes,42,44 2006.173.14:14:42.30/va/08,04,usb,yes,36,43 2006.173.14:14:42.53/valo/01,524.99,yes,locked 2006.173.14:14:42.53/valo/02,534.99,yes,locked 2006.173.14:14:42.53/valo/03,564.99,yes,locked 2006.173.14:14:42.53/valo/04,624.99,yes,locked 2006.173.14:14:42.53/valo/05,734.99,yes,locked 2006.173.14:14:42.53/valo/06,814.99,yes,locked 2006.173.14:14:42.53/valo/07,864.99,yes,locked 2006.173.14:14:42.53/valo/08,884.99,yes,locked 2006.173.14:14:43.62/vb/01,04,usb,yes,36,29 2006.173.14:14:43.62/vb/02,04,usb,yes,32,38 2006.173.14:14:43.62/vb/03,04,usb,yes,29,34 2006.173.14:14:43.62/vb/04,04,usb,yes,34,33 2006.173.14:14:43.62/vb/05,04,usb,yes,26,29 2006.173.14:14:43.62/vb/06,04,usb,yes,31,27 2006.173.14:14:43.62/vb/07,04,usb,yes,30,30 2006.173.14:14:43.62/vb/08,04,usb,yes,28,31 2006.173.14:14:43.85/vblo/01,629.99,yes,locked 2006.173.14:14:43.85/vblo/02,634.99,yes,locked 2006.173.14:14:43.85/vblo/03,649.99,yes,locked 2006.173.14:14:43.85/vblo/04,679.99,yes,locked 2006.173.14:14:43.85/vblo/05,709.99,yes,locked 2006.173.14:14:43.85/vblo/06,719.99,yes,locked 2006.173.14:14:43.85/vblo/07,734.99,yes,locked 2006.173.14:14:43.85/vblo/08,744.99,yes,locked 2006.173.14:14:44.00/vabw/8 2006.173.14:14:44.15/vbbw/8 2006.173.14:14:44.29/xfe/off,on,15.2 2006.173.14:14:44.66/ifatt/23,28,28,28 2006.173.14:14:45.07/fmout-gps/S +3.90E-07 2006.173.14:14:45.12:!2006.173.14:21:10 2006.173.14:21:10.00:data_valid=off 2006.173.14:21:10.01:"et 2006.173.14:21:10.01:!+3s 2006.173.14:21:13.02:"tape 2006.173.14:21:13.03:postob 2006.173.14:21:13.09/cable/+6.5070E-03 2006.173.14:21:13.10/wx/21.55,1004.0,100 2006.173.14:21:13.15/fmout-gps/S +3.88E-07 2006.173.14:21:13.15:scan_name=173-1427,jd0606,240 2006.173.14:21:13.15:source=3c446,222547.26,-045701.4,2000.0,cw 2006.173.14:21:14.14#flagr#flagr/antenna,new-source 2006.173.14:21:14.15:checkk5 2006.173.14:21:14.56/chk_autoobs//k5ts1/ autoobs is running! 2006.173.14:21:14.95/chk_autoobs//k5ts2/ autoobs is running! 2006.173.14:21:15.36/chk_autoobs//k5ts3/ autoobs is running! 2006.173.14:21:15.76/chk_autoobs//k5ts4/ autoobs is running! 2006.173.14:21:16.14/chk_obsdata//k5ts1/T1731414??a.dat file size is correct (nominal:1560MB, actual:1556MB). 2006.173.14:21:16.55/chk_obsdata//k5ts2/T1731414??b.dat file size is correct (nominal:1560MB, actual:1556MB). 2006.173.14:21:16.95/chk_obsdata//k5ts3/T1731414??c.dat file size is correct (nominal:1560MB, actual:1556MB). 2006.173.14:21:17.35/chk_obsdata//k5ts4/T1731414??d.dat file size is correct (nominal:1560MB, actual:1556MB). 2006.173.14:21:18.07/k5log//k5ts1_log_newline 2006.173.14:21:18.79/k5log//k5ts2_log_newline 2006.173.14:21:19.53/k5log//k5ts3_log_newline 2006.173.14:21:20.24/k5log//k5ts4_log_newline 2006.173.14:21:20.26/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.14:21:20.26:setupk4=1 2006.173.14:21:20.26$setupk4/echo=on 2006.173.14:21:20.26$setupk4/pcalon 2006.173.14:21:20.26$pcalon/"no phase cal control is implemented here 2006.173.14:21:20.26$setupk4/"tpicd=stop 2006.173.14:21:20.26$setupk4/"rec=synch_on 2006.173.14:21:20.26$setupk4/"rec_mode=128 2006.173.14:21:20.26$setupk4/!* 2006.173.14:21:20.26$setupk4/recpk4 2006.173.14:21:20.26$recpk4/recpatch= 2006.173.14:21:20.27$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.14:21:20.27$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.14:21:20.27$setupk4/vck44 2006.173.14:21:20.27$vck44/valo=1,524.99 2006.173.14:21:20.27#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.14:21:20.27#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.14:21:20.27#ibcon#ireg 17 cls_cnt 0 2006.173.14:21:20.27#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.14:21:20.27#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.14:21:20.27#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.14:21:20.27#ibcon#enter wrdev, iclass 18, count 0 2006.173.14:21:20.27#ibcon#first serial, iclass 18, count 0 2006.173.14:21:20.27#ibcon#enter sib2, iclass 18, count 0 2006.173.14:21:20.27#ibcon#flushed, iclass 18, count 0 2006.173.14:21:20.27#ibcon#about to write, iclass 18, count 0 2006.173.14:21:20.27#ibcon#wrote, iclass 18, count 0 2006.173.14:21:20.27#ibcon#about to read 3, iclass 18, count 0 2006.173.14:21:20.28#ibcon#read 3, iclass 18, count 0 2006.173.14:21:20.28#ibcon#about to read 4, iclass 18, count 0 2006.173.14:21:20.28#ibcon#read 4, iclass 18, count 0 2006.173.14:21:20.28#ibcon#about to read 5, iclass 18, count 0 2006.173.14:21:20.28#ibcon#read 5, iclass 18, count 0 2006.173.14:21:20.28#ibcon#about to read 6, iclass 18, count 0 2006.173.14:21:20.28#ibcon#read 6, iclass 18, count 0 2006.173.14:21:20.28#ibcon#end of sib2, iclass 18, count 0 2006.173.14:21:20.28#ibcon#*mode == 0, iclass 18, count 0 2006.173.14:21:20.28#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.14:21:20.28#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.14:21:20.28#ibcon#*before write, iclass 18, count 0 2006.173.14:21:20.28#ibcon#enter sib2, iclass 18, count 0 2006.173.14:21:20.28#ibcon#flushed, iclass 18, count 0 2006.173.14:21:20.28#ibcon#about to write, iclass 18, count 0 2006.173.14:21:20.28#ibcon#wrote, iclass 18, count 0 2006.173.14:21:20.28#ibcon#about to read 3, iclass 18, count 0 2006.173.14:21:20.33#ibcon#read 3, iclass 18, count 0 2006.173.14:21:20.33#ibcon#about to read 4, iclass 18, count 0 2006.173.14:21:20.33#ibcon#read 4, iclass 18, count 0 2006.173.14:21:20.33#ibcon#about to read 5, iclass 18, count 0 2006.173.14:21:20.33#ibcon#read 5, iclass 18, count 0 2006.173.14:21:20.33#ibcon#about to read 6, iclass 18, count 0 2006.173.14:21:20.33#ibcon#read 6, iclass 18, count 0 2006.173.14:21:20.33#ibcon#end of sib2, iclass 18, count 0 2006.173.14:21:20.33#ibcon#*after write, iclass 18, count 0 2006.173.14:21:20.33#ibcon#*before return 0, iclass 18, count 0 2006.173.14:21:20.33#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.14:21:20.33#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.14:21:20.33#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.14:21:20.33#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.14:21:20.33$vck44/va=1,7 2006.173.14:21:20.33#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.14:21:20.33#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.14:21:20.33#ibcon#ireg 11 cls_cnt 2 2006.173.14:21:20.33#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.14:21:20.33#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.14:21:20.33#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.14:21:20.33#ibcon#enter wrdev, iclass 20, count 2 2006.173.14:21:20.33#ibcon#first serial, iclass 20, count 2 2006.173.14:21:20.33#ibcon#enter sib2, iclass 20, count 2 2006.173.14:21:20.33#ibcon#flushed, iclass 20, count 2 2006.173.14:21:20.33#ibcon#about to write, iclass 20, count 2 2006.173.14:21:20.33#ibcon#wrote, iclass 20, count 2 2006.173.14:21:20.33#ibcon#about to read 3, iclass 20, count 2 2006.173.14:21:20.35#ibcon#read 3, iclass 20, count 2 2006.173.14:21:20.35#ibcon#about to read 4, iclass 20, count 2 2006.173.14:21:20.35#ibcon#read 4, iclass 20, count 2 2006.173.14:21:20.35#ibcon#about to read 5, iclass 20, count 2 2006.173.14:21:20.35#ibcon#read 5, iclass 20, count 2 2006.173.14:21:20.35#ibcon#about to read 6, iclass 20, count 2 2006.173.14:21:20.35#ibcon#read 6, iclass 20, count 2 2006.173.14:21:20.35#ibcon#end of sib2, iclass 20, count 2 2006.173.14:21:20.35#ibcon#*mode == 0, iclass 20, count 2 2006.173.14:21:20.35#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.14:21:20.35#ibcon#[25=AT01-07\r\n] 2006.173.14:21:20.35#ibcon#*before write, iclass 20, count 2 2006.173.14:21:20.35#ibcon#enter sib2, iclass 20, count 2 2006.173.14:21:20.35#ibcon#flushed, iclass 20, count 2 2006.173.14:21:20.35#ibcon#about to write, iclass 20, count 2 2006.173.14:21:20.35#ibcon#wrote, iclass 20, count 2 2006.173.14:21:20.35#ibcon#about to read 3, iclass 20, count 2 2006.173.14:21:20.38#ibcon#read 3, iclass 20, count 2 2006.173.14:21:20.38#ibcon#about to read 4, iclass 20, count 2 2006.173.14:21:20.38#ibcon#read 4, iclass 20, count 2 2006.173.14:21:20.38#ibcon#about to read 5, iclass 20, count 2 2006.173.14:21:20.38#ibcon#read 5, iclass 20, count 2 2006.173.14:21:20.38#ibcon#about to read 6, iclass 20, count 2 2006.173.14:21:20.38#ibcon#read 6, iclass 20, count 2 2006.173.14:21:20.38#ibcon#end of sib2, iclass 20, count 2 2006.173.14:21:20.38#ibcon#*after write, iclass 20, count 2 2006.173.14:21:20.38#ibcon#*before return 0, iclass 20, count 2 2006.173.14:21:20.38#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.14:21:20.38#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.14:21:20.38#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.14:21:20.38#ibcon#ireg 7 cls_cnt 0 2006.173.14:21:20.38#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.14:21:20.50#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.14:21:20.50#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.14:21:20.50#ibcon#enter wrdev, iclass 20, count 0 2006.173.14:21:20.50#ibcon#first serial, iclass 20, count 0 2006.173.14:21:20.50#ibcon#enter sib2, iclass 20, count 0 2006.173.14:21:20.50#ibcon#flushed, iclass 20, count 0 2006.173.14:21:20.50#ibcon#about to write, iclass 20, count 0 2006.173.14:21:20.50#ibcon#wrote, iclass 20, count 0 2006.173.14:21:20.50#ibcon#about to read 3, iclass 20, count 0 2006.173.14:21:20.52#ibcon#read 3, iclass 20, count 0 2006.173.14:21:20.52#ibcon#about to read 4, iclass 20, count 0 2006.173.14:21:20.52#ibcon#read 4, iclass 20, count 0 2006.173.14:21:20.52#ibcon#about to read 5, iclass 20, count 0 2006.173.14:21:20.52#ibcon#read 5, iclass 20, count 0 2006.173.14:21:20.52#ibcon#about to read 6, iclass 20, count 0 2006.173.14:21:20.52#ibcon#read 6, iclass 20, count 0 2006.173.14:21:20.52#ibcon#end of sib2, iclass 20, count 0 2006.173.14:21:20.52#ibcon#*mode == 0, iclass 20, count 0 2006.173.14:21:20.52#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.14:21:20.52#ibcon#[25=USB\r\n] 2006.173.14:21:20.52#ibcon#*before write, iclass 20, count 0 2006.173.14:21:20.52#ibcon#enter sib2, iclass 20, count 0 2006.173.14:21:20.52#ibcon#flushed, iclass 20, count 0 2006.173.14:21:20.52#ibcon#about to write, iclass 20, count 0 2006.173.14:21:20.52#ibcon#wrote, iclass 20, count 0 2006.173.14:21:20.52#ibcon#about to read 3, iclass 20, count 0 2006.173.14:21:20.55#ibcon#read 3, iclass 20, count 0 2006.173.14:21:20.55#ibcon#about to read 4, iclass 20, count 0 2006.173.14:21:20.55#ibcon#read 4, iclass 20, count 0 2006.173.14:21:20.55#ibcon#about to read 5, iclass 20, count 0 2006.173.14:21:20.55#ibcon#read 5, iclass 20, count 0 2006.173.14:21:20.55#ibcon#about to read 6, iclass 20, count 0 2006.173.14:21:20.55#ibcon#read 6, iclass 20, count 0 2006.173.14:21:20.55#ibcon#end of sib2, iclass 20, count 0 2006.173.14:21:20.55#ibcon#*after write, iclass 20, count 0 2006.173.14:21:20.55#ibcon#*before return 0, iclass 20, count 0 2006.173.14:21:20.55#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.14:21:20.55#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.14:21:20.55#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.14:21:20.55#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.14:21:20.55$vck44/valo=2,534.99 2006.173.14:21:20.55#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.14:21:20.55#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.14:21:20.55#ibcon#ireg 17 cls_cnt 0 2006.173.14:21:20.55#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.14:21:20.55#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.14:21:20.55#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.14:21:20.55#ibcon#enter wrdev, iclass 22, count 0 2006.173.14:21:20.55#ibcon#first serial, iclass 22, count 0 2006.173.14:21:20.55#ibcon#enter sib2, iclass 22, count 0 2006.173.14:21:20.55#ibcon#flushed, iclass 22, count 0 2006.173.14:21:20.55#ibcon#about to write, iclass 22, count 0 2006.173.14:21:20.55#ibcon#wrote, iclass 22, count 0 2006.173.14:21:20.55#ibcon#about to read 3, iclass 22, count 0 2006.173.14:21:20.57#ibcon#read 3, iclass 22, count 0 2006.173.14:21:20.57#ibcon#about to read 4, iclass 22, count 0 2006.173.14:21:20.57#ibcon#read 4, iclass 22, count 0 2006.173.14:21:20.57#ibcon#about to read 5, iclass 22, count 0 2006.173.14:21:20.57#ibcon#read 5, iclass 22, count 0 2006.173.14:21:20.57#ibcon#about to read 6, iclass 22, count 0 2006.173.14:21:20.57#ibcon#read 6, iclass 22, count 0 2006.173.14:21:20.57#ibcon#end of sib2, iclass 22, count 0 2006.173.14:21:20.57#ibcon#*mode == 0, iclass 22, count 0 2006.173.14:21:20.57#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.14:21:20.57#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.14:21:20.57#ibcon#*before write, iclass 22, count 0 2006.173.14:21:20.57#ibcon#enter sib2, iclass 22, count 0 2006.173.14:21:20.57#ibcon#flushed, iclass 22, count 0 2006.173.14:21:20.57#ibcon#about to write, iclass 22, count 0 2006.173.14:21:20.57#ibcon#wrote, iclass 22, count 0 2006.173.14:21:20.57#ibcon#about to read 3, iclass 22, count 0 2006.173.14:21:20.61#ibcon#read 3, iclass 22, count 0 2006.173.14:21:20.61#ibcon#about to read 4, iclass 22, count 0 2006.173.14:21:20.61#ibcon#read 4, iclass 22, count 0 2006.173.14:21:20.61#ibcon#about to read 5, iclass 22, count 0 2006.173.14:21:20.61#ibcon#read 5, iclass 22, count 0 2006.173.14:21:20.61#ibcon#about to read 6, iclass 22, count 0 2006.173.14:21:20.61#ibcon#read 6, iclass 22, count 0 2006.173.14:21:20.61#ibcon#end of sib2, iclass 22, count 0 2006.173.14:21:20.61#ibcon#*after write, iclass 22, count 0 2006.173.14:21:20.61#ibcon#*before return 0, iclass 22, count 0 2006.173.14:21:20.61#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.14:21:20.61#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.14:21:20.61#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.14:21:20.61#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.14:21:20.61$vck44/va=2,6 2006.173.14:21:20.61#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.14:21:20.61#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.14:21:20.61#ibcon#ireg 11 cls_cnt 2 2006.173.14:21:20.61#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.14:21:20.67#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.14:21:20.67#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.14:21:20.67#ibcon#enter wrdev, iclass 24, count 2 2006.173.14:21:20.67#ibcon#first serial, iclass 24, count 2 2006.173.14:21:20.67#ibcon#enter sib2, iclass 24, count 2 2006.173.14:21:20.67#ibcon#flushed, iclass 24, count 2 2006.173.14:21:20.67#ibcon#about to write, iclass 24, count 2 2006.173.14:21:20.67#ibcon#wrote, iclass 24, count 2 2006.173.14:21:20.67#ibcon#about to read 3, iclass 24, count 2 2006.173.14:21:20.69#ibcon#read 3, iclass 24, count 2 2006.173.14:21:20.69#ibcon#about to read 4, iclass 24, count 2 2006.173.14:21:20.69#ibcon#read 4, iclass 24, count 2 2006.173.14:21:20.69#ibcon#about to read 5, iclass 24, count 2 2006.173.14:21:20.69#ibcon#read 5, iclass 24, count 2 2006.173.14:21:20.69#ibcon#about to read 6, iclass 24, count 2 2006.173.14:21:20.69#ibcon#read 6, iclass 24, count 2 2006.173.14:21:20.69#ibcon#end of sib2, iclass 24, count 2 2006.173.14:21:20.69#ibcon#*mode == 0, iclass 24, count 2 2006.173.14:21:20.69#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.14:21:20.69#ibcon#[25=AT02-06\r\n] 2006.173.14:21:20.69#ibcon#*before write, iclass 24, count 2 2006.173.14:21:20.69#ibcon#enter sib2, iclass 24, count 2 2006.173.14:21:20.69#ibcon#flushed, iclass 24, count 2 2006.173.14:21:20.69#ibcon#about to write, iclass 24, count 2 2006.173.14:21:20.69#ibcon#wrote, iclass 24, count 2 2006.173.14:21:20.69#ibcon#about to read 3, iclass 24, count 2 2006.173.14:21:20.72#ibcon#read 3, iclass 24, count 2 2006.173.14:21:20.72#ibcon#about to read 4, iclass 24, count 2 2006.173.14:21:20.72#ibcon#read 4, iclass 24, count 2 2006.173.14:21:20.72#ibcon#about to read 5, iclass 24, count 2 2006.173.14:21:20.72#ibcon#read 5, iclass 24, count 2 2006.173.14:21:20.72#ibcon#about to read 6, iclass 24, count 2 2006.173.14:21:20.72#ibcon#read 6, iclass 24, count 2 2006.173.14:21:20.72#ibcon#end of sib2, iclass 24, count 2 2006.173.14:21:20.72#ibcon#*after write, iclass 24, count 2 2006.173.14:21:20.72#ibcon#*before return 0, iclass 24, count 2 2006.173.14:21:20.72#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.14:21:20.72#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.14:21:20.72#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.14:21:20.72#ibcon#ireg 7 cls_cnt 0 2006.173.14:21:20.72#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.14:21:20.84#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.14:21:20.84#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.14:21:20.84#ibcon#enter wrdev, iclass 24, count 0 2006.173.14:21:20.84#ibcon#first serial, iclass 24, count 0 2006.173.14:21:20.84#ibcon#enter sib2, iclass 24, count 0 2006.173.14:21:20.84#ibcon#flushed, iclass 24, count 0 2006.173.14:21:20.84#ibcon#about to write, iclass 24, count 0 2006.173.14:21:20.84#ibcon#wrote, iclass 24, count 0 2006.173.14:21:20.84#ibcon#about to read 3, iclass 24, count 0 2006.173.14:21:20.86#ibcon#read 3, iclass 24, count 0 2006.173.14:21:20.86#ibcon#about to read 4, iclass 24, count 0 2006.173.14:21:20.86#ibcon#read 4, iclass 24, count 0 2006.173.14:21:20.86#ibcon#about to read 5, iclass 24, count 0 2006.173.14:21:20.86#ibcon#read 5, iclass 24, count 0 2006.173.14:21:20.86#ibcon#about to read 6, iclass 24, count 0 2006.173.14:21:20.86#ibcon#read 6, iclass 24, count 0 2006.173.14:21:20.86#ibcon#end of sib2, iclass 24, count 0 2006.173.14:21:20.86#ibcon#*mode == 0, iclass 24, count 0 2006.173.14:21:20.86#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.14:21:20.86#ibcon#[25=USB\r\n] 2006.173.14:21:20.86#ibcon#*before write, iclass 24, count 0 2006.173.14:21:20.86#ibcon#enter sib2, iclass 24, count 0 2006.173.14:21:20.86#ibcon#flushed, iclass 24, count 0 2006.173.14:21:20.86#ibcon#about to write, iclass 24, count 0 2006.173.14:21:20.86#ibcon#wrote, iclass 24, count 0 2006.173.14:21:20.86#ibcon#about to read 3, iclass 24, count 0 2006.173.14:21:20.89#ibcon#read 3, iclass 24, count 0 2006.173.14:21:20.89#ibcon#about to read 4, iclass 24, count 0 2006.173.14:21:20.89#ibcon#read 4, iclass 24, count 0 2006.173.14:21:20.89#ibcon#about to read 5, iclass 24, count 0 2006.173.14:21:20.89#ibcon#read 5, iclass 24, count 0 2006.173.14:21:20.89#ibcon#about to read 6, iclass 24, count 0 2006.173.14:21:20.89#ibcon#read 6, iclass 24, count 0 2006.173.14:21:20.89#ibcon#end of sib2, iclass 24, count 0 2006.173.14:21:20.89#ibcon#*after write, iclass 24, count 0 2006.173.14:21:20.89#ibcon#*before return 0, iclass 24, count 0 2006.173.14:21:20.89#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.14:21:20.89#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.14:21:20.89#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.14:21:20.89#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.14:21:20.89$vck44/valo=3,564.99 2006.173.14:21:20.89#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.14:21:20.89#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.14:21:20.89#ibcon#ireg 17 cls_cnt 0 2006.173.14:21:20.89#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.14:21:20.89#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.14:21:20.89#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.14:21:20.89#ibcon#enter wrdev, iclass 26, count 0 2006.173.14:21:20.89#ibcon#first serial, iclass 26, count 0 2006.173.14:21:20.89#ibcon#enter sib2, iclass 26, count 0 2006.173.14:21:20.89#ibcon#flushed, iclass 26, count 0 2006.173.14:21:20.89#ibcon#about to write, iclass 26, count 0 2006.173.14:21:20.89#ibcon#wrote, iclass 26, count 0 2006.173.14:21:20.89#ibcon#about to read 3, iclass 26, count 0 2006.173.14:21:20.91#ibcon#read 3, iclass 26, count 0 2006.173.14:21:20.91#ibcon#about to read 4, iclass 26, count 0 2006.173.14:21:20.91#ibcon#read 4, iclass 26, count 0 2006.173.14:21:20.91#ibcon#about to read 5, iclass 26, count 0 2006.173.14:21:20.91#ibcon#read 5, iclass 26, count 0 2006.173.14:21:20.91#ibcon#about to read 6, iclass 26, count 0 2006.173.14:21:20.91#ibcon#read 6, iclass 26, count 0 2006.173.14:21:20.91#ibcon#end of sib2, iclass 26, count 0 2006.173.14:21:20.91#ibcon#*mode == 0, iclass 26, count 0 2006.173.14:21:20.91#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.14:21:20.91#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.14:21:20.91#ibcon#*before write, iclass 26, count 0 2006.173.14:21:20.91#ibcon#enter sib2, iclass 26, count 0 2006.173.14:21:20.91#ibcon#flushed, iclass 26, count 0 2006.173.14:21:20.91#ibcon#about to write, iclass 26, count 0 2006.173.14:21:20.91#ibcon#wrote, iclass 26, count 0 2006.173.14:21:20.91#ibcon#about to read 3, iclass 26, count 0 2006.173.14:21:20.95#ibcon#read 3, iclass 26, count 0 2006.173.14:21:20.95#ibcon#about to read 4, iclass 26, count 0 2006.173.14:21:20.95#ibcon#read 4, iclass 26, count 0 2006.173.14:21:20.95#ibcon#about to read 5, iclass 26, count 0 2006.173.14:21:20.95#ibcon#read 5, iclass 26, count 0 2006.173.14:21:20.95#ibcon#about to read 6, iclass 26, count 0 2006.173.14:21:20.95#ibcon#read 6, iclass 26, count 0 2006.173.14:21:20.95#ibcon#end of sib2, iclass 26, count 0 2006.173.14:21:20.95#ibcon#*after write, iclass 26, count 0 2006.173.14:21:20.95#ibcon#*before return 0, iclass 26, count 0 2006.173.14:21:20.95#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.14:21:20.95#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.14:21:20.95#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.14:21:20.95#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.14:21:20.95$vck44/va=3,5 2006.173.14:21:20.95#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.14:21:20.95#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.14:21:20.95#ibcon#ireg 11 cls_cnt 2 2006.173.14:21:20.95#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.14:21:21.01#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.14:21:21.01#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.14:21:21.01#ibcon#enter wrdev, iclass 28, count 2 2006.173.14:21:21.01#ibcon#first serial, iclass 28, count 2 2006.173.14:21:21.01#ibcon#enter sib2, iclass 28, count 2 2006.173.14:21:21.01#ibcon#flushed, iclass 28, count 2 2006.173.14:21:21.01#ibcon#about to write, iclass 28, count 2 2006.173.14:21:21.01#ibcon#wrote, iclass 28, count 2 2006.173.14:21:21.01#ibcon#about to read 3, iclass 28, count 2 2006.173.14:21:21.03#ibcon#read 3, iclass 28, count 2 2006.173.14:21:21.03#ibcon#about to read 4, iclass 28, count 2 2006.173.14:21:21.03#ibcon#read 4, iclass 28, count 2 2006.173.14:21:21.03#ibcon#about to read 5, iclass 28, count 2 2006.173.14:21:21.03#ibcon#read 5, iclass 28, count 2 2006.173.14:21:21.03#ibcon#about to read 6, iclass 28, count 2 2006.173.14:21:21.03#ibcon#read 6, iclass 28, count 2 2006.173.14:21:21.03#ibcon#end of sib2, iclass 28, count 2 2006.173.14:21:21.03#ibcon#*mode == 0, iclass 28, count 2 2006.173.14:21:21.03#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.14:21:21.03#ibcon#[25=AT03-05\r\n] 2006.173.14:21:21.03#ibcon#*before write, iclass 28, count 2 2006.173.14:21:21.03#ibcon#enter sib2, iclass 28, count 2 2006.173.14:21:21.03#ibcon#flushed, iclass 28, count 2 2006.173.14:21:21.03#ibcon#about to write, iclass 28, count 2 2006.173.14:21:21.03#ibcon#wrote, iclass 28, count 2 2006.173.14:21:21.03#ibcon#about to read 3, iclass 28, count 2 2006.173.14:21:21.06#ibcon#read 3, iclass 28, count 2 2006.173.14:21:21.06#ibcon#about to read 4, iclass 28, count 2 2006.173.14:21:21.06#ibcon#read 4, iclass 28, count 2 2006.173.14:21:21.06#ibcon#about to read 5, iclass 28, count 2 2006.173.14:21:21.06#ibcon#read 5, iclass 28, count 2 2006.173.14:21:21.06#ibcon#about to read 6, iclass 28, count 2 2006.173.14:21:21.06#ibcon#read 6, iclass 28, count 2 2006.173.14:21:21.06#ibcon#end of sib2, iclass 28, count 2 2006.173.14:21:21.06#ibcon#*after write, iclass 28, count 2 2006.173.14:21:21.06#ibcon#*before return 0, iclass 28, count 2 2006.173.14:21:21.06#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.14:21:21.06#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.14:21:21.06#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.14:21:21.06#ibcon#ireg 7 cls_cnt 0 2006.173.14:21:21.06#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.14:21:21.18#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.14:21:21.18#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.14:21:21.18#ibcon#enter wrdev, iclass 28, count 0 2006.173.14:21:21.18#ibcon#first serial, iclass 28, count 0 2006.173.14:21:21.18#ibcon#enter sib2, iclass 28, count 0 2006.173.14:21:21.18#ibcon#flushed, iclass 28, count 0 2006.173.14:21:21.18#ibcon#about to write, iclass 28, count 0 2006.173.14:21:21.18#ibcon#wrote, iclass 28, count 0 2006.173.14:21:21.18#ibcon#about to read 3, iclass 28, count 0 2006.173.14:21:21.20#ibcon#read 3, iclass 28, count 0 2006.173.14:21:21.20#ibcon#about to read 4, iclass 28, count 0 2006.173.14:21:21.20#ibcon#read 4, iclass 28, count 0 2006.173.14:21:21.20#ibcon#about to read 5, iclass 28, count 0 2006.173.14:21:21.20#ibcon#read 5, iclass 28, count 0 2006.173.14:21:21.20#ibcon#about to read 6, iclass 28, count 0 2006.173.14:21:21.20#ibcon#read 6, iclass 28, count 0 2006.173.14:21:21.20#ibcon#end of sib2, iclass 28, count 0 2006.173.14:21:21.20#ibcon#*mode == 0, iclass 28, count 0 2006.173.14:21:21.20#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.14:21:21.20#ibcon#[25=USB\r\n] 2006.173.14:21:21.20#ibcon#*before write, iclass 28, count 0 2006.173.14:21:21.20#ibcon#enter sib2, iclass 28, count 0 2006.173.14:21:21.20#ibcon#flushed, iclass 28, count 0 2006.173.14:21:21.20#ibcon#about to write, iclass 28, count 0 2006.173.14:21:21.20#ibcon#wrote, iclass 28, count 0 2006.173.14:21:21.20#ibcon#about to read 3, iclass 28, count 0 2006.173.14:21:21.23#ibcon#read 3, iclass 28, count 0 2006.173.14:21:21.23#ibcon#about to read 4, iclass 28, count 0 2006.173.14:21:21.23#ibcon#read 4, iclass 28, count 0 2006.173.14:21:21.23#ibcon#about to read 5, iclass 28, count 0 2006.173.14:21:21.23#ibcon#read 5, iclass 28, count 0 2006.173.14:21:21.23#ibcon#about to read 6, iclass 28, count 0 2006.173.14:21:21.23#ibcon#read 6, iclass 28, count 0 2006.173.14:21:21.23#ibcon#end of sib2, iclass 28, count 0 2006.173.14:21:21.23#ibcon#*after write, iclass 28, count 0 2006.173.14:21:21.23#ibcon#*before return 0, iclass 28, count 0 2006.173.14:21:21.23#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.14:21:21.23#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.14:21:21.23#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.14:21:21.23#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.14:21:21.23$vck44/valo=4,624.99 2006.173.14:21:21.23#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.14:21:21.23#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.14:21:21.23#ibcon#ireg 17 cls_cnt 0 2006.173.14:21:21.23#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.14:21:21.23#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.14:21:21.23#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.14:21:21.23#ibcon#enter wrdev, iclass 30, count 0 2006.173.14:21:21.23#ibcon#first serial, iclass 30, count 0 2006.173.14:21:21.23#ibcon#enter sib2, iclass 30, count 0 2006.173.14:21:21.23#ibcon#flushed, iclass 30, count 0 2006.173.14:21:21.23#ibcon#about to write, iclass 30, count 0 2006.173.14:21:21.23#ibcon#wrote, iclass 30, count 0 2006.173.14:21:21.23#ibcon#about to read 3, iclass 30, count 0 2006.173.14:21:21.25#ibcon#read 3, iclass 30, count 0 2006.173.14:21:21.25#ibcon#about to read 4, iclass 30, count 0 2006.173.14:21:21.25#ibcon#read 4, iclass 30, count 0 2006.173.14:21:21.25#ibcon#about to read 5, iclass 30, count 0 2006.173.14:21:21.25#ibcon#read 5, iclass 30, count 0 2006.173.14:21:21.25#ibcon#about to read 6, iclass 30, count 0 2006.173.14:21:21.25#ibcon#read 6, iclass 30, count 0 2006.173.14:21:21.25#ibcon#end of sib2, iclass 30, count 0 2006.173.14:21:21.25#ibcon#*mode == 0, iclass 30, count 0 2006.173.14:21:21.25#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.14:21:21.25#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.14:21:21.25#ibcon#*before write, iclass 30, count 0 2006.173.14:21:21.25#ibcon#enter sib2, iclass 30, count 0 2006.173.14:21:21.25#ibcon#flushed, iclass 30, count 0 2006.173.14:21:21.25#ibcon#about to write, iclass 30, count 0 2006.173.14:21:21.25#ibcon#wrote, iclass 30, count 0 2006.173.14:21:21.25#ibcon#about to read 3, iclass 30, count 0 2006.173.14:21:21.29#ibcon#read 3, iclass 30, count 0 2006.173.14:21:21.29#ibcon#about to read 4, iclass 30, count 0 2006.173.14:21:21.29#ibcon#read 4, iclass 30, count 0 2006.173.14:21:21.29#ibcon#about to read 5, iclass 30, count 0 2006.173.14:21:21.29#ibcon#read 5, iclass 30, count 0 2006.173.14:21:21.29#ibcon#about to read 6, iclass 30, count 0 2006.173.14:21:21.29#ibcon#read 6, iclass 30, count 0 2006.173.14:21:21.29#ibcon#end of sib2, iclass 30, count 0 2006.173.14:21:21.29#ibcon#*after write, iclass 30, count 0 2006.173.14:21:21.29#ibcon#*before return 0, iclass 30, count 0 2006.173.14:21:21.29#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.14:21:21.29#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.14:21:21.29#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.14:21:21.29#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.14:21:21.29$vck44/va=4,6 2006.173.14:21:21.29#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.173.14:21:21.29#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.173.14:21:21.29#ibcon#ireg 11 cls_cnt 2 2006.173.14:21:21.29#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.14:21:21.35#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.14:21:21.35#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.14:21:21.35#ibcon#enter wrdev, iclass 32, count 2 2006.173.14:21:21.35#ibcon#first serial, iclass 32, count 2 2006.173.14:21:21.35#ibcon#enter sib2, iclass 32, count 2 2006.173.14:21:21.35#ibcon#flushed, iclass 32, count 2 2006.173.14:21:21.35#ibcon#about to write, iclass 32, count 2 2006.173.14:21:21.35#ibcon#wrote, iclass 32, count 2 2006.173.14:21:21.35#ibcon#about to read 3, iclass 32, count 2 2006.173.14:21:21.37#ibcon#read 3, iclass 32, count 2 2006.173.14:21:21.37#ibcon#about to read 4, iclass 32, count 2 2006.173.14:21:21.37#ibcon#read 4, iclass 32, count 2 2006.173.14:21:21.37#ibcon#about to read 5, iclass 32, count 2 2006.173.14:21:21.37#ibcon#read 5, iclass 32, count 2 2006.173.14:21:21.37#ibcon#about to read 6, iclass 32, count 2 2006.173.14:21:21.37#ibcon#read 6, iclass 32, count 2 2006.173.14:21:21.37#ibcon#end of sib2, iclass 32, count 2 2006.173.14:21:21.37#ibcon#*mode == 0, iclass 32, count 2 2006.173.14:21:21.37#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.173.14:21:21.37#ibcon#[25=AT04-06\r\n] 2006.173.14:21:21.37#ibcon#*before write, iclass 32, count 2 2006.173.14:21:21.37#ibcon#enter sib2, iclass 32, count 2 2006.173.14:21:21.37#ibcon#flushed, iclass 32, count 2 2006.173.14:21:21.37#ibcon#about to write, iclass 32, count 2 2006.173.14:21:21.37#ibcon#wrote, iclass 32, count 2 2006.173.14:21:21.37#ibcon#about to read 3, iclass 32, count 2 2006.173.14:21:21.40#ibcon#read 3, iclass 32, count 2 2006.173.14:21:21.40#ibcon#about to read 4, iclass 32, count 2 2006.173.14:21:21.40#ibcon#read 4, iclass 32, count 2 2006.173.14:21:21.40#ibcon#about to read 5, iclass 32, count 2 2006.173.14:21:21.40#ibcon#read 5, iclass 32, count 2 2006.173.14:21:21.40#ibcon#about to read 6, iclass 32, count 2 2006.173.14:21:21.40#ibcon#read 6, iclass 32, count 2 2006.173.14:21:21.40#ibcon#end of sib2, iclass 32, count 2 2006.173.14:21:21.40#ibcon#*after write, iclass 32, count 2 2006.173.14:21:21.40#ibcon#*before return 0, iclass 32, count 2 2006.173.14:21:21.40#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.14:21:21.40#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.173.14:21:21.40#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.173.14:21:21.40#ibcon#ireg 7 cls_cnt 0 2006.173.14:21:21.40#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.14:21:21.52#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.14:21:21.52#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.14:21:21.52#ibcon#enter wrdev, iclass 32, count 0 2006.173.14:21:21.52#ibcon#first serial, iclass 32, count 0 2006.173.14:21:21.52#ibcon#enter sib2, iclass 32, count 0 2006.173.14:21:21.52#ibcon#flushed, iclass 32, count 0 2006.173.14:21:21.52#ibcon#about to write, iclass 32, count 0 2006.173.14:21:21.52#ibcon#wrote, iclass 32, count 0 2006.173.14:21:21.52#ibcon#about to read 3, iclass 32, count 0 2006.173.14:21:21.54#ibcon#read 3, iclass 32, count 0 2006.173.14:21:21.54#ibcon#about to read 4, iclass 32, count 0 2006.173.14:21:21.54#ibcon#read 4, iclass 32, count 0 2006.173.14:21:21.54#ibcon#about to read 5, iclass 32, count 0 2006.173.14:21:21.54#ibcon#read 5, iclass 32, count 0 2006.173.14:21:21.54#ibcon#about to read 6, iclass 32, count 0 2006.173.14:21:21.54#ibcon#read 6, iclass 32, count 0 2006.173.14:21:21.54#ibcon#end of sib2, iclass 32, count 0 2006.173.14:21:21.54#ibcon#*mode == 0, iclass 32, count 0 2006.173.14:21:21.54#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.14:21:21.54#ibcon#[25=USB\r\n] 2006.173.14:21:21.54#ibcon#*before write, iclass 32, count 0 2006.173.14:21:21.54#ibcon#enter sib2, iclass 32, count 0 2006.173.14:21:21.54#ibcon#flushed, iclass 32, count 0 2006.173.14:21:21.54#ibcon#about to write, iclass 32, count 0 2006.173.14:21:21.54#ibcon#wrote, iclass 32, count 0 2006.173.14:21:21.54#ibcon#about to read 3, iclass 32, count 0 2006.173.14:21:21.57#ibcon#read 3, iclass 32, count 0 2006.173.14:21:21.57#ibcon#about to read 4, iclass 32, count 0 2006.173.14:21:21.57#ibcon#read 4, iclass 32, count 0 2006.173.14:21:21.57#ibcon#about to read 5, iclass 32, count 0 2006.173.14:21:21.57#ibcon#read 5, iclass 32, count 0 2006.173.14:21:21.57#ibcon#about to read 6, iclass 32, count 0 2006.173.14:21:21.57#ibcon#read 6, iclass 32, count 0 2006.173.14:21:21.57#ibcon#end of sib2, iclass 32, count 0 2006.173.14:21:21.57#ibcon#*after write, iclass 32, count 0 2006.173.14:21:21.57#ibcon#*before return 0, iclass 32, count 0 2006.173.14:21:21.57#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.14:21:21.57#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.173.14:21:21.57#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.14:21:21.57#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.14:21:21.57$vck44/valo=5,734.99 2006.173.14:21:21.57#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.14:21:21.57#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.14:21:21.57#ibcon#ireg 17 cls_cnt 0 2006.173.14:21:21.57#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.14:21:21.57#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.14:21:21.57#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.14:21:21.57#ibcon#enter wrdev, iclass 34, count 0 2006.173.14:21:21.57#ibcon#first serial, iclass 34, count 0 2006.173.14:21:21.57#ibcon#enter sib2, iclass 34, count 0 2006.173.14:21:21.57#ibcon#flushed, iclass 34, count 0 2006.173.14:21:21.57#ibcon#about to write, iclass 34, count 0 2006.173.14:21:21.57#ibcon#wrote, iclass 34, count 0 2006.173.14:21:21.57#ibcon#about to read 3, iclass 34, count 0 2006.173.14:21:21.59#ibcon#read 3, iclass 34, count 0 2006.173.14:21:21.59#ibcon#about to read 4, iclass 34, count 0 2006.173.14:21:21.59#ibcon#read 4, iclass 34, count 0 2006.173.14:21:21.59#ibcon#about to read 5, iclass 34, count 0 2006.173.14:21:21.59#ibcon#read 5, iclass 34, count 0 2006.173.14:21:21.59#ibcon#about to read 6, iclass 34, count 0 2006.173.14:21:21.59#ibcon#read 6, iclass 34, count 0 2006.173.14:21:21.59#ibcon#end of sib2, iclass 34, count 0 2006.173.14:21:21.59#ibcon#*mode == 0, iclass 34, count 0 2006.173.14:21:21.59#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.14:21:21.59#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.14:21:21.59#ibcon#*before write, iclass 34, count 0 2006.173.14:21:21.59#ibcon#enter sib2, iclass 34, count 0 2006.173.14:21:21.59#ibcon#flushed, iclass 34, count 0 2006.173.14:21:21.59#ibcon#about to write, iclass 34, count 0 2006.173.14:21:21.59#ibcon#wrote, iclass 34, count 0 2006.173.14:21:21.59#ibcon#about to read 3, iclass 34, count 0 2006.173.14:21:21.63#ibcon#read 3, iclass 34, count 0 2006.173.14:21:21.63#ibcon#about to read 4, iclass 34, count 0 2006.173.14:21:21.63#ibcon#read 4, iclass 34, count 0 2006.173.14:21:21.63#ibcon#about to read 5, iclass 34, count 0 2006.173.14:21:21.63#ibcon#read 5, iclass 34, count 0 2006.173.14:21:21.63#ibcon#about to read 6, iclass 34, count 0 2006.173.14:21:21.63#ibcon#read 6, iclass 34, count 0 2006.173.14:21:21.63#ibcon#end of sib2, iclass 34, count 0 2006.173.14:21:21.63#ibcon#*after write, iclass 34, count 0 2006.173.14:21:21.63#ibcon#*before return 0, iclass 34, count 0 2006.173.14:21:21.63#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.14:21:21.63#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.14:21:21.63#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.14:21:21.63#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.14:21:21.63$vck44/va=5,4 2006.173.14:21:21.63#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.14:21:21.63#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.14:21:21.63#ibcon#ireg 11 cls_cnt 2 2006.173.14:21:21.63#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.14:21:21.69#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.14:21:21.69#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.14:21:21.69#ibcon#enter wrdev, iclass 36, count 2 2006.173.14:21:21.69#ibcon#first serial, iclass 36, count 2 2006.173.14:21:21.69#ibcon#enter sib2, iclass 36, count 2 2006.173.14:21:21.69#ibcon#flushed, iclass 36, count 2 2006.173.14:21:21.69#ibcon#about to write, iclass 36, count 2 2006.173.14:21:21.69#ibcon#wrote, iclass 36, count 2 2006.173.14:21:21.69#ibcon#about to read 3, iclass 36, count 2 2006.173.14:21:21.71#ibcon#read 3, iclass 36, count 2 2006.173.14:21:21.71#ibcon#about to read 4, iclass 36, count 2 2006.173.14:21:21.71#ibcon#read 4, iclass 36, count 2 2006.173.14:21:21.71#ibcon#about to read 5, iclass 36, count 2 2006.173.14:21:21.71#ibcon#read 5, iclass 36, count 2 2006.173.14:21:21.71#ibcon#about to read 6, iclass 36, count 2 2006.173.14:21:21.71#ibcon#read 6, iclass 36, count 2 2006.173.14:21:21.71#ibcon#end of sib2, iclass 36, count 2 2006.173.14:21:21.71#ibcon#*mode == 0, iclass 36, count 2 2006.173.14:21:21.71#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.14:21:21.71#ibcon#[25=AT05-04\r\n] 2006.173.14:21:21.71#ibcon#*before write, iclass 36, count 2 2006.173.14:21:21.71#ibcon#enter sib2, iclass 36, count 2 2006.173.14:21:21.71#ibcon#flushed, iclass 36, count 2 2006.173.14:21:21.71#ibcon#about to write, iclass 36, count 2 2006.173.14:21:21.71#ibcon#wrote, iclass 36, count 2 2006.173.14:21:21.71#ibcon#about to read 3, iclass 36, count 2 2006.173.14:21:21.74#ibcon#read 3, iclass 36, count 2 2006.173.14:21:21.74#ibcon#about to read 4, iclass 36, count 2 2006.173.14:21:21.74#ibcon#read 4, iclass 36, count 2 2006.173.14:21:21.74#ibcon#about to read 5, iclass 36, count 2 2006.173.14:21:21.74#ibcon#read 5, iclass 36, count 2 2006.173.14:21:21.74#ibcon#about to read 6, iclass 36, count 2 2006.173.14:21:21.74#ibcon#read 6, iclass 36, count 2 2006.173.14:21:21.74#ibcon#end of sib2, iclass 36, count 2 2006.173.14:21:21.74#ibcon#*after write, iclass 36, count 2 2006.173.14:21:21.74#ibcon#*before return 0, iclass 36, count 2 2006.173.14:21:21.74#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.14:21:21.74#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.14:21:21.74#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.14:21:21.74#ibcon#ireg 7 cls_cnt 0 2006.173.14:21:21.74#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.14:21:21.86#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.14:21:21.86#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.14:21:21.86#ibcon#enter wrdev, iclass 36, count 0 2006.173.14:21:21.86#ibcon#first serial, iclass 36, count 0 2006.173.14:21:21.86#ibcon#enter sib2, iclass 36, count 0 2006.173.14:21:21.86#ibcon#flushed, iclass 36, count 0 2006.173.14:21:21.86#ibcon#about to write, iclass 36, count 0 2006.173.14:21:21.86#ibcon#wrote, iclass 36, count 0 2006.173.14:21:21.86#ibcon#about to read 3, iclass 36, count 0 2006.173.14:21:21.88#ibcon#read 3, iclass 36, count 0 2006.173.14:21:21.88#ibcon#about to read 4, iclass 36, count 0 2006.173.14:21:21.88#ibcon#read 4, iclass 36, count 0 2006.173.14:21:21.88#ibcon#about to read 5, iclass 36, count 0 2006.173.14:21:21.88#ibcon#read 5, iclass 36, count 0 2006.173.14:21:21.88#ibcon#about to read 6, iclass 36, count 0 2006.173.14:21:21.88#ibcon#read 6, iclass 36, count 0 2006.173.14:21:21.88#ibcon#end of sib2, iclass 36, count 0 2006.173.14:21:21.88#ibcon#*mode == 0, iclass 36, count 0 2006.173.14:21:21.88#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.14:21:21.88#ibcon#[25=USB\r\n] 2006.173.14:21:21.88#ibcon#*before write, iclass 36, count 0 2006.173.14:21:21.88#ibcon#enter sib2, iclass 36, count 0 2006.173.14:21:21.88#ibcon#flushed, iclass 36, count 0 2006.173.14:21:21.88#ibcon#about to write, iclass 36, count 0 2006.173.14:21:21.88#ibcon#wrote, iclass 36, count 0 2006.173.14:21:21.88#ibcon#about to read 3, iclass 36, count 0 2006.173.14:21:21.91#ibcon#read 3, iclass 36, count 0 2006.173.14:21:21.91#ibcon#about to read 4, iclass 36, count 0 2006.173.14:21:21.91#ibcon#read 4, iclass 36, count 0 2006.173.14:21:21.91#ibcon#about to read 5, iclass 36, count 0 2006.173.14:21:21.91#ibcon#read 5, iclass 36, count 0 2006.173.14:21:21.91#ibcon#about to read 6, iclass 36, count 0 2006.173.14:21:21.91#ibcon#read 6, iclass 36, count 0 2006.173.14:21:21.91#ibcon#end of sib2, iclass 36, count 0 2006.173.14:21:21.91#ibcon#*after write, iclass 36, count 0 2006.173.14:21:21.91#ibcon#*before return 0, iclass 36, count 0 2006.173.14:21:21.91#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.14:21:21.91#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.14:21:21.91#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.14:21:21.91#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.14:21:21.91$vck44/valo=6,814.99 2006.173.14:21:21.91#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.14:21:21.91#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.14:21:21.91#ibcon#ireg 17 cls_cnt 0 2006.173.14:21:21.91#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.14:21:21.91#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.14:21:21.91#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.14:21:21.91#ibcon#enter wrdev, iclass 38, count 0 2006.173.14:21:21.91#ibcon#first serial, iclass 38, count 0 2006.173.14:21:21.91#ibcon#enter sib2, iclass 38, count 0 2006.173.14:21:21.91#ibcon#flushed, iclass 38, count 0 2006.173.14:21:21.91#ibcon#about to write, iclass 38, count 0 2006.173.14:21:21.91#ibcon#wrote, iclass 38, count 0 2006.173.14:21:21.91#ibcon#about to read 3, iclass 38, count 0 2006.173.14:21:21.93#ibcon#read 3, iclass 38, count 0 2006.173.14:21:21.93#ibcon#about to read 4, iclass 38, count 0 2006.173.14:21:21.93#ibcon#read 4, iclass 38, count 0 2006.173.14:21:21.93#ibcon#about to read 5, iclass 38, count 0 2006.173.14:21:21.93#ibcon#read 5, iclass 38, count 0 2006.173.14:21:21.93#ibcon#about to read 6, iclass 38, count 0 2006.173.14:21:21.93#ibcon#read 6, iclass 38, count 0 2006.173.14:21:21.93#ibcon#end of sib2, iclass 38, count 0 2006.173.14:21:21.93#ibcon#*mode == 0, iclass 38, count 0 2006.173.14:21:21.93#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.14:21:21.93#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.14:21:21.93#ibcon#*before write, iclass 38, count 0 2006.173.14:21:21.93#ibcon#enter sib2, iclass 38, count 0 2006.173.14:21:21.93#ibcon#flushed, iclass 38, count 0 2006.173.14:21:21.93#ibcon#about to write, iclass 38, count 0 2006.173.14:21:21.93#ibcon#wrote, iclass 38, count 0 2006.173.14:21:21.93#ibcon#about to read 3, iclass 38, count 0 2006.173.14:21:21.97#ibcon#read 3, iclass 38, count 0 2006.173.14:21:21.97#ibcon#about to read 4, iclass 38, count 0 2006.173.14:21:21.97#ibcon#read 4, iclass 38, count 0 2006.173.14:21:21.97#ibcon#about to read 5, iclass 38, count 0 2006.173.14:21:21.97#ibcon#read 5, iclass 38, count 0 2006.173.14:21:21.97#ibcon#about to read 6, iclass 38, count 0 2006.173.14:21:21.97#ibcon#read 6, iclass 38, count 0 2006.173.14:21:21.97#ibcon#end of sib2, iclass 38, count 0 2006.173.14:21:21.97#ibcon#*after write, iclass 38, count 0 2006.173.14:21:21.97#ibcon#*before return 0, iclass 38, count 0 2006.173.14:21:21.97#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.14:21:21.97#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.14:21:21.97#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.14:21:21.97#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.14:21:21.97$vck44/va=6,3 2006.173.14:21:21.97#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.14:21:21.97#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.14:21:21.97#ibcon#ireg 11 cls_cnt 2 2006.173.14:21:21.97#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.14:21:22.03#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.14:21:22.03#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.14:21:22.03#ibcon#enter wrdev, iclass 40, count 2 2006.173.14:21:22.03#ibcon#first serial, iclass 40, count 2 2006.173.14:21:22.03#ibcon#enter sib2, iclass 40, count 2 2006.173.14:21:22.03#ibcon#flushed, iclass 40, count 2 2006.173.14:21:22.03#ibcon#about to write, iclass 40, count 2 2006.173.14:21:22.03#ibcon#wrote, iclass 40, count 2 2006.173.14:21:22.03#ibcon#about to read 3, iclass 40, count 2 2006.173.14:21:22.05#ibcon#read 3, iclass 40, count 2 2006.173.14:21:22.05#ibcon#about to read 4, iclass 40, count 2 2006.173.14:21:22.05#ibcon#read 4, iclass 40, count 2 2006.173.14:21:22.05#ibcon#about to read 5, iclass 40, count 2 2006.173.14:21:22.05#ibcon#read 5, iclass 40, count 2 2006.173.14:21:22.05#ibcon#about to read 6, iclass 40, count 2 2006.173.14:21:22.05#ibcon#read 6, iclass 40, count 2 2006.173.14:21:22.05#ibcon#end of sib2, iclass 40, count 2 2006.173.14:21:22.05#ibcon#*mode == 0, iclass 40, count 2 2006.173.14:21:22.05#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.14:21:22.05#ibcon#[25=AT06-03\r\n] 2006.173.14:21:22.05#ibcon#*before write, iclass 40, count 2 2006.173.14:21:22.05#ibcon#enter sib2, iclass 40, count 2 2006.173.14:21:22.05#ibcon#flushed, iclass 40, count 2 2006.173.14:21:22.05#ibcon#about to write, iclass 40, count 2 2006.173.14:21:22.05#ibcon#wrote, iclass 40, count 2 2006.173.14:21:22.05#ibcon#about to read 3, iclass 40, count 2 2006.173.14:21:22.08#ibcon#read 3, iclass 40, count 2 2006.173.14:21:22.08#ibcon#about to read 4, iclass 40, count 2 2006.173.14:21:22.08#ibcon#read 4, iclass 40, count 2 2006.173.14:21:22.08#ibcon#about to read 5, iclass 40, count 2 2006.173.14:21:22.08#ibcon#read 5, iclass 40, count 2 2006.173.14:21:22.08#ibcon#about to read 6, iclass 40, count 2 2006.173.14:21:22.08#ibcon#read 6, iclass 40, count 2 2006.173.14:21:22.08#ibcon#end of sib2, iclass 40, count 2 2006.173.14:21:22.08#ibcon#*after write, iclass 40, count 2 2006.173.14:21:22.08#ibcon#*before return 0, iclass 40, count 2 2006.173.14:21:22.08#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.14:21:22.08#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.14:21:22.08#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.14:21:22.08#ibcon#ireg 7 cls_cnt 0 2006.173.14:21:22.08#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.14:21:22.20#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.14:21:22.20#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.14:21:22.20#ibcon#enter wrdev, iclass 40, count 0 2006.173.14:21:22.20#ibcon#first serial, iclass 40, count 0 2006.173.14:21:22.20#ibcon#enter sib2, iclass 40, count 0 2006.173.14:21:22.20#ibcon#flushed, iclass 40, count 0 2006.173.14:21:22.20#ibcon#about to write, iclass 40, count 0 2006.173.14:21:22.20#ibcon#wrote, iclass 40, count 0 2006.173.14:21:22.20#ibcon#about to read 3, iclass 40, count 0 2006.173.14:21:22.22#ibcon#read 3, iclass 40, count 0 2006.173.14:21:22.22#ibcon#about to read 4, iclass 40, count 0 2006.173.14:21:22.22#ibcon#read 4, iclass 40, count 0 2006.173.14:21:22.22#ibcon#about to read 5, iclass 40, count 0 2006.173.14:21:22.22#ibcon#read 5, iclass 40, count 0 2006.173.14:21:22.22#ibcon#about to read 6, iclass 40, count 0 2006.173.14:21:22.22#ibcon#read 6, iclass 40, count 0 2006.173.14:21:22.22#ibcon#end of sib2, iclass 40, count 0 2006.173.14:21:22.22#ibcon#*mode == 0, iclass 40, count 0 2006.173.14:21:22.22#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.14:21:22.22#ibcon#[25=USB\r\n] 2006.173.14:21:22.22#ibcon#*before write, iclass 40, count 0 2006.173.14:21:22.22#ibcon#enter sib2, iclass 40, count 0 2006.173.14:21:22.22#ibcon#flushed, iclass 40, count 0 2006.173.14:21:22.22#ibcon#about to write, iclass 40, count 0 2006.173.14:21:22.22#ibcon#wrote, iclass 40, count 0 2006.173.14:21:22.22#ibcon#about to read 3, iclass 40, count 0 2006.173.14:21:22.25#ibcon#read 3, iclass 40, count 0 2006.173.14:21:22.25#ibcon#about to read 4, iclass 40, count 0 2006.173.14:21:22.25#ibcon#read 4, iclass 40, count 0 2006.173.14:21:22.25#ibcon#about to read 5, iclass 40, count 0 2006.173.14:21:22.25#ibcon#read 5, iclass 40, count 0 2006.173.14:21:22.25#ibcon#about to read 6, iclass 40, count 0 2006.173.14:21:22.25#ibcon#read 6, iclass 40, count 0 2006.173.14:21:22.25#ibcon#end of sib2, iclass 40, count 0 2006.173.14:21:22.25#ibcon#*after write, iclass 40, count 0 2006.173.14:21:22.25#ibcon#*before return 0, iclass 40, count 0 2006.173.14:21:22.25#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.14:21:22.25#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.14:21:22.25#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.14:21:22.25#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.14:21:22.25$vck44/valo=7,864.99 2006.173.14:21:22.25#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.14:21:22.25#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.14:21:22.25#ibcon#ireg 17 cls_cnt 0 2006.173.14:21:22.25#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.14:21:22.25#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.14:21:22.25#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.14:21:22.25#ibcon#enter wrdev, iclass 4, count 0 2006.173.14:21:22.25#ibcon#first serial, iclass 4, count 0 2006.173.14:21:22.25#ibcon#enter sib2, iclass 4, count 0 2006.173.14:21:22.25#ibcon#flushed, iclass 4, count 0 2006.173.14:21:22.25#ibcon#about to write, iclass 4, count 0 2006.173.14:21:22.25#ibcon#wrote, iclass 4, count 0 2006.173.14:21:22.25#ibcon#about to read 3, iclass 4, count 0 2006.173.14:21:22.27#ibcon#read 3, iclass 4, count 0 2006.173.14:21:22.27#ibcon#about to read 4, iclass 4, count 0 2006.173.14:21:22.27#ibcon#read 4, iclass 4, count 0 2006.173.14:21:22.27#ibcon#about to read 5, iclass 4, count 0 2006.173.14:21:22.27#ibcon#read 5, iclass 4, count 0 2006.173.14:21:22.27#ibcon#about to read 6, iclass 4, count 0 2006.173.14:21:22.27#ibcon#read 6, iclass 4, count 0 2006.173.14:21:22.27#ibcon#end of sib2, iclass 4, count 0 2006.173.14:21:22.27#ibcon#*mode == 0, iclass 4, count 0 2006.173.14:21:22.27#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.14:21:22.27#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.14:21:22.27#ibcon#*before write, iclass 4, count 0 2006.173.14:21:22.27#ibcon#enter sib2, iclass 4, count 0 2006.173.14:21:22.27#ibcon#flushed, iclass 4, count 0 2006.173.14:21:22.27#ibcon#about to write, iclass 4, count 0 2006.173.14:21:22.27#ibcon#wrote, iclass 4, count 0 2006.173.14:21:22.27#ibcon#about to read 3, iclass 4, count 0 2006.173.14:21:22.31#ibcon#read 3, iclass 4, count 0 2006.173.14:21:22.31#ibcon#about to read 4, iclass 4, count 0 2006.173.14:21:22.31#ibcon#read 4, iclass 4, count 0 2006.173.14:21:22.31#ibcon#about to read 5, iclass 4, count 0 2006.173.14:21:22.31#ibcon#read 5, iclass 4, count 0 2006.173.14:21:22.31#ibcon#about to read 6, iclass 4, count 0 2006.173.14:21:22.31#ibcon#read 6, iclass 4, count 0 2006.173.14:21:22.31#ibcon#end of sib2, iclass 4, count 0 2006.173.14:21:22.31#ibcon#*after write, iclass 4, count 0 2006.173.14:21:22.31#ibcon#*before return 0, iclass 4, count 0 2006.173.14:21:22.31#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.14:21:22.31#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.14:21:22.31#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.14:21:22.31#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.14:21:22.31$vck44/va=7,4 2006.173.14:21:22.31#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.14:21:22.31#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.14:21:22.31#ibcon#ireg 11 cls_cnt 2 2006.173.14:21:22.31#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.14:21:22.37#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.14:21:22.37#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.14:21:22.37#ibcon#enter wrdev, iclass 6, count 2 2006.173.14:21:22.37#ibcon#first serial, iclass 6, count 2 2006.173.14:21:22.37#ibcon#enter sib2, iclass 6, count 2 2006.173.14:21:22.37#ibcon#flushed, iclass 6, count 2 2006.173.14:21:22.37#ibcon#about to write, iclass 6, count 2 2006.173.14:21:22.37#ibcon#wrote, iclass 6, count 2 2006.173.14:21:22.37#ibcon#about to read 3, iclass 6, count 2 2006.173.14:21:22.39#ibcon#read 3, iclass 6, count 2 2006.173.14:21:22.39#ibcon#about to read 4, iclass 6, count 2 2006.173.14:21:22.39#ibcon#read 4, iclass 6, count 2 2006.173.14:21:22.39#ibcon#about to read 5, iclass 6, count 2 2006.173.14:21:22.39#ibcon#read 5, iclass 6, count 2 2006.173.14:21:22.39#ibcon#about to read 6, iclass 6, count 2 2006.173.14:21:22.39#ibcon#read 6, iclass 6, count 2 2006.173.14:21:22.39#ibcon#end of sib2, iclass 6, count 2 2006.173.14:21:22.39#ibcon#*mode == 0, iclass 6, count 2 2006.173.14:21:22.39#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.14:21:22.39#ibcon#[25=AT07-04\r\n] 2006.173.14:21:22.39#ibcon#*before write, iclass 6, count 2 2006.173.14:21:22.39#ibcon#enter sib2, iclass 6, count 2 2006.173.14:21:22.39#ibcon#flushed, iclass 6, count 2 2006.173.14:21:22.39#ibcon#about to write, iclass 6, count 2 2006.173.14:21:22.39#ibcon#wrote, iclass 6, count 2 2006.173.14:21:22.39#ibcon#about to read 3, iclass 6, count 2 2006.173.14:21:22.42#ibcon#read 3, iclass 6, count 2 2006.173.14:21:22.42#ibcon#about to read 4, iclass 6, count 2 2006.173.14:21:22.42#ibcon#read 4, iclass 6, count 2 2006.173.14:21:22.42#ibcon#about to read 5, iclass 6, count 2 2006.173.14:21:22.42#ibcon#read 5, iclass 6, count 2 2006.173.14:21:22.42#ibcon#about to read 6, iclass 6, count 2 2006.173.14:21:22.42#ibcon#read 6, iclass 6, count 2 2006.173.14:21:22.42#ibcon#end of sib2, iclass 6, count 2 2006.173.14:21:22.42#ibcon#*after write, iclass 6, count 2 2006.173.14:21:22.42#ibcon#*before return 0, iclass 6, count 2 2006.173.14:21:22.42#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.14:21:22.42#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.14:21:22.42#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.14:21:22.42#ibcon#ireg 7 cls_cnt 0 2006.173.14:21:22.42#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.14:21:22.54#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.14:21:22.54#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.14:21:22.54#ibcon#enter wrdev, iclass 6, count 0 2006.173.14:21:22.54#ibcon#first serial, iclass 6, count 0 2006.173.14:21:22.54#ibcon#enter sib2, iclass 6, count 0 2006.173.14:21:22.54#ibcon#flushed, iclass 6, count 0 2006.173.14:21:22.54#ibcon#about to write, iclass 6, count 0 2006.173.14:21:22.54#ibcon#wrote, iclass 6, count 0 2006.173.14:21:22.54#ibcon#about to read 3, iclass 6, count 0 2006.173.14:21:22.56#ibcon#read 3, iclass 6, count 0 2006.173.14:21:22.56#ibcon#about to read 4, iclass 6, count 0 2006.173.14:21:22.56#ibcon#read 4, iclass 6, count 0 2006.173.14:21:22.56#ibcon#about to read 5, iclass 6, count 0 2006.173.14:21:22.56#ibcon#read 5, iclass 6, count 0 2006.173.14:21:22.56#ibcon#about to read 6, iclass 6, count 0 2006.173.14:21:22.56#ibcon#read 6, iclass 6, count 0 2006.173.14:21:22.56#ibcon#end of sib2, iclass 6, count 0 2006.173.14:21:22.56#ibcon#*mode == 0, iclass 6, count 0 2006.173.14:21:22.56#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.14:21:22.56#ibcon#[25=USB\r\n] 2006.173.14:21:22.56#ibcon#*before write, iclass 6, count 0 2006.173.14:21:22.56#ibcon#enter sib2, iclass 6, count 0 2006.173.14:21:22.56#ibcon#flushed, iclass 6, count 0 2006.173.14:21:22.56#ibcon#about to write, iclass 6, count 0 2006.173.14:21:22.56#ibcon#wrote, iclass 6, count 0 2006.173.14:21:22.56#ibcon#about to read 3, iclass 6, count 0 2006.173.14:21:22.59#ibcon#read 3, iclass 6, count 0 2006.173.14:21:22.59#ibcon#about to read 4, iclass 6, count 0 2006.173.14:21:22.59#ibcon#read 4, iclass 6, count 0 2006.173.14:21:22.59#ibcon#about to read 5, iclass 6, count 0 2006.173.14:21:22.59#ibcon#read 5, iclass 6, count 0 2006.173.14:21:22.59#ibcon#about to read 6, iclass 6, count 0 2006.173.14:21:22.59#ibcon#read 6, iclass 6, count 0 2006.173.14:21:22.59#ibcon#end of sib2, iclass 6, count 0 2006.173.14:21:22.59#ibcon#*after write, iclass 6, count 0 2006.173.14:21:22.59#ibcon#*before return 0, iclass 6, count 0 2006.173.14:21:22.59#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.14:21:22.59#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.14:21:22.59#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.14:21:22.59#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.14:21:22.59$vck44/valo=8,884.99 2006.173.14:21:22.59#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.14:21:22.59#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.14:21:22.59#ibcon#ireg 17 cls_cnt 0 2006.173.14:21:22.59#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.14:21:22.59#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.14:21:22.59#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.14:21:22.59#ibcon#enter wrdev, iclass 10, count 0 2006.173.14:21:22.59#ibcon#first serial, iclass 10, count 0 2006.173.14:21:22.59#ibcon#enter sib2, iclass 10, count 0 2006.173.14:21:22.59#ibcon#flushed, iclass 10, count 0 2006.173.14:21:22.59#ibcon#about to write, iclass 10, count 0 2006.173.14:21:22.59#ibcon#wrote, iclass 10, count 0 2006.173.14:21:22.59#ibcon#about to read 3, iclass 10, count 0 2006.173.14:21:22.61#ibcon#read 3, iclass 10, count 0 2006.173.14:21:22.61#ibcon#about to read 4, iclass 10, count 0 2006.173.14:21:22.61#ibcon#read 4, iclass 10, count 0 2006.173.14:21:22.61#ibcon#about to read 5, iclass 10, count 0 2006.173.14:21:22.61#ibcon#read 5, iclass 10, count 0 2006.173.14:21:22.61#ibcon#about to read 6, iclass 10, count 0 2006.173.14:21:22.61#ibcon#read 6, iclass 10, count 0 2006.173.14:21:22.61#ibcon#end of sib2, iclass 10, count 0 2006.173.14:21:22.61#ibcon#*mode == 0, iclass 10, count 0 2006.173.14:21:22.61#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.14:21:22.61#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.14:21:22.61#ibcon#*before write, iclass 10, count 0 2006.173.14:21:22.61#ibcon#enter sib2, iclass 10, count 0 2006.173.14:21:22.61#ibcon#flushed, iclass 10, count 0 2006.173.14:21:22.61#ibcon#about to write, iclass 10, count 0 2006.173.14:21:22.61#ibcon#wrote, iclass 10, count 0 2006.173.14:21:22.61#ibcon#about to read 3, iclass 10, count 0 2006.173.14:21:22.65#ibcon#read 3, iclass 10, count 0 2006.173.14:21:22.65#ibcon#about to read 4, iclass 10, count 0 2006.173.14:21:22.65#ibcon#read 4, iclass 10, count 0 2006.173.14:21:22.65#ibcon#about to read 5, iclass 10, count 0 2006.173.14:21:22.65#ibcon#read 5, iclass 10, count 0 2006.173.14:21:22.65#ibcon#about to read 6, iclass 10, count 0 2006.173.14:21:22.65#ibcon#read 6, iclass 10, count 0 2006.173.14:21:22.65#ibcon#end of sib2, iclass 10, count 0 2006.173.14:21:22.65#ibcon#*after write, iclass 10, count 0 2006.173.14:21:22.65#ibcon#*before return 0, iclass 10, count 0 2006.173.14:21:22.65#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.14:21:22.65#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.14:21:22.65#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.14:21:22.65#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.14:21:22.65$vck44/va=8,4 2006.173.14:21:22.65#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.14:21:22.65#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.14:21:22.65#ibcon#ireg 11 cls_cnt 2 2006.173.14:21:22.65#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.14:21:22.71#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.14:21:22.71#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.14:21:22.71#ibcon#enter wrdev, iclass 12, count 2 2006.173.14:21:22.71#ibcon#first serial, iclass 12, count 2 2006.173.14:21:22.71#ibcon#enter sib2, iclass 12, count 2 2006.173.14:21:22.71#ibcon#flushed, iclass 12, count 2 2006.173.14:21:22.71#ibcon#about to write, iclass 12, count 2 2006.173.14:21:22.71#ibcon#wrote, iclass 12, count 2 2006.173.14:21:22.71#ibcon#about to read 3, iclass 12, count 2 2006.173.14:21:22.73#ibcon#read 3, iclass 12, count 2 2006.173.14:21:22.73#ibcon#about to read 4, iclass 12, count 2 2006.173.14:21:22.73#ibcon#read 4, iclass 12, count 2 2006.173.14:21:22.73#ibcon#about to read 5, iclass 12, count 2 2006.173.14:21:22.73#ibcon#read 5, iclass 12, count 2 2006.173.14:21:22.73#ibcon#about to read 6, iclass 12, count 2 2006.173.14:21:22.73#ibcon#read 6, iclass 12, count 2 2006.173.14:21:22.73#ibcon#end of sib2, iclass 12, count 2 2006.173.14:21:22.73#ibcon#*mode == 0, iclass 12, count 2 2006.173.14:21:22.73#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.14:21:22.73#ibcon#[25=AT08-04\r\n] 2006.173.14:21:22.73#ibcon#*before write, iclass 12, count 2 2006.173.14:21:22.73#ibcon#enter sib2, iclass 12, count 2 2006.173.14:21:22.73#ibcon#flushed, iclass 12, count 2 2006.173.14:21:22.73#ibcon#about to write, iclass 12, count 2 2006.173.14:21:22.73#ibcon#wrote, iclass 12, count 2 2006.173.14:21:22.73#ibcon#about to read 3, iclass 12, count 2 2006.173.14:21:22.76#ibcon#read 3, iclass 12, count 2 2006.173.14:21:22.76#ibcon#about to read 4, iclass 12, count 2 2006.173.14:21:22.76#ibcon#read 4, iclass 12, count 2 2006.173.14:21:22.76#ibcon#about to read 5, iclass 12, count 2 2006.173.14:21:22.76#ibcon#read 5, iclass 12, count 2 2006.173.14:21:22.76#ibcon#about to read 6, iclass 12, count 2 2006.173.14:21:22.76#ibcon#read 6, iclass 12, count 2 2006.173.14:21:22.76#ibcon#end of sib2, iclass 12, count 2 2006.173.14:21:22.76#ibcon#*after write, iclass 12, count 2 2006.173.14:21:22.76#ibcon#*before return 0, iclass 12, count 2 2006.173.14:21:22.76#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.14:21:22.76#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.14:21:22.76#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.14:21:22.76#ibcon#ireg 7 cls_cnt 0 2006.173.14:21:22.76#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.14:21:22.88#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.14:21:22.88#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.14:21:22.88#ibcon#enter wrdev, iclass 12, count 0 2006.173.14:21:22.88#ibcon#first serial, iclass 12, count 0 2006.173.14:21:22.88#ibcon#enter sib2, iclass 12, count 0 2006.173.14:21:22.88#ibcon#flushed, iclass 12, count 0 2006.173.14:21:22.88#ibcon#about to write, iclass 12, count 0 2006.173.14:21:22.88#ibcon#wrote, iclass 12, count 0 2006.173.14:21:22.88#ibcon#about to read 3, iclass 12, count 0 2006.173.14:21:22.90#ibcon#read 3, iclass 12, count 0 2006.173.14:21:22.90#ibcon#about to read 4, iclass 12, count 0 2006.173.14:21:22.90#ibcon#read 4, iclass 12, count 0 2006.173.14:21:22.90#ibcon#about to read 5, iclass 12, count 0 2006.173.14:21:22.90#ibcon#read 5, iclass 12, count 0 2006.173.14:21:22.90#ibcon#about to read 6, iclass 12, count 0 2006.173.14:21:22.90#ibcon#read 6, iclass 12, count 0 2006.173.14:21:22.90#ibcon#end of sib2, iclass 12, count 0 2006.173.14:21:22.90#ibcon#*mode == 0, iclass 12, count 0 2006.173.14:21:22.90#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.14:21:22.90#ibcon#[25=USB\r\n] 2006.173.14:21:22.90#ibcon#*before write, iclass 12, count 0 2006.173.14:21:22.90#ibcon#enter sib2, iclass 12, count 0 2006.173.14:21:22.90#ibcon#flushed, iclass 12, count 0 2006.173.14:21:22.90#ibcon#about to write, iclass 12, count 0 2006.173.14:21:22.90#ibcon#wrote, iclass 12, count 0 2006.173.14:21:22.90#ibcon#about to read 3, iclass 12, count 0 2006.173.14:21:22.93#ibcon#read 3, iclass 12, count 0 2006.173.14:21:22.93#ibcon#about to read 4, iclass 12, count 0 2006.173.14:21:22.93#ibcon#read 4, iclass 12, count 0 2006.173.14:21:22.93#ibcon#about to read 5, iclass 12, count 0 2006.173.14:21:22.93#ibcon#read 5, iclass 12, count 0 2006.173.14:21:22.93#ibcon#about to read 6, iclass 12, count 0 2006.173.14:21:22.93#ibcon#read 6, iclass 12, count 0 2006.173.14:21:22.93#ibcon#end of sib2, iclass 12, count 0 2006.173.14:21:22.93#ibcon#*after write, iclass 12, count 0 2006.173.14:21:22.93#ibcon#*before return 0, iclass 12, count 0 2006.173.14:21:22.93#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.14:21:22.93#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.14:21:22.93#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.14:21:22.93#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.14:21:22.93$vck44/vblo=1,629.99 2006.173.14:21:22.93#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.14:21:22.93#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.14:21:22.93#ibcon#ireg 17 cls_cnt 0 2006.173.14:21:22.93#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.14:21:22.93#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.14:21:22.93#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.14:21:22.93#ibcon#enter wrdev, iclass 14, count 0 2006.173.14:21:22.93#ibcon#first serial, iclass 14, count 0 2006.173.14:21:22.93#ibcon#enter sib2, iclass 14, count 0 2006.173.14:21:22.93#ibcon#flushed, iclass 14, count 0 2006.173.14:21:22.93#ibcon#about to write, iclass 14, count 0 2006.173.14:21:22.93#ibcon#wrote, iclass 14, count 0 2006.173.14:21:22.93#ibcon#about to read 3, iclass 14, count 0 2006.173.14:21:22.95#ibcon#read 3, iclass 14, count 0 2006.173.14:21:22.95#ibcon#about to read 4, iclass 14, count 0 2006.173.14:21:22.95#ibcon#read 4, iclass 14, count 0 2006.173.14:21:22.95#ibcon#about to read 5, iclass 14, count 0 2006.173.14:21:22.95#ibcon#read 5, iclass 14, count 0 2006.173.14:21:22.95#ibcon#about to read 6, iclass 14, count 0 2006.173.14:21:22.95#ibcon#read 6, iclass 14, count 0 2006.173.14:21:22.95#ibcon#end of sib2, iclass 14, count 0 2006.173.14:21:22.95#ibcon#*mode == 0, iclass 14, count 0 2006.173.14:21:22.95#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.14:21:22.95#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.14:21:22.95#ibcon#*before write, iclass 14, count 0 2006.173.14:21:22.95#ibcon#enter sib2, iclass 14, count 0 2006.173.14:21:22.95#ibcon#flushed, iclass 14, count 0 2006.173.14:21:22.95#ibcon#about to write, iclass 14, count 0 2006.173.14:21:22.95#ibcon#wrote, iclass 14, count 0 2006.173.14:21:22.95#ibcon#about to read 3, iclass 14, count 0 2006.173.14:21:22.99#ibcon#read 3, iclass 14, count 0 2006.173.14:21:22.99#ibcon#about to read 4, iclass 14, count 0 2006.173.14:21:22.99#ibcon#read 4, iclass 14, count 0 2006.173.14:21:22.99#ibcon#about to read 5, iclass 14, count 0 2006.173.14:21:22.99#ibcon#read 5, iclass 14, count 0 2006.173.14:21:22.99#ibcon#about to read 6, iclass 14, count 0 2006.173.14:21:22.99#ibcon#read 6, iclass 14, count 0 2006.173.14:21:22.99#ibcon#end of sib2, iclass 14, count 0 2006.173.14:21:22.99#ibcon#*after write, iclass 14, count 0 2006.173.14:21:22.99#ibcon#*before return 0, iclass 14, count 0 2006.173.14:21:22.99#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.14:21:22.99#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.14:21:22.99#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.14:21:22.99#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.14:21:22.99$vck44/vb=1,4 2006.173.14:21:22.99#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.14:21:22.99#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.14:21:22.99#ibcon#ireg 11 cls_cnt 2 2006.173.14:21:22.99#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.14:21:22.99#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.14:21:22.99#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.14:21:22.99#ibcon#enter wrdev, iclass 16, count 2 2006.173.14:21:22.99#ibcon#first serial, iclass 16, count 2 2006.173.14:21:22.99#ibcon#enter sib2, iclass 16, count 2 2006.173.14:21:22.99#ibcon#flushed, iclass 16, count 2 2006.173.14:21:22.99#ibcon#about to write, iclass 16, count 2 2006.173.14:21:22.99#ibcon#wrote, iclass 16, count 2 2006.173.14:21:22.99#ibcon#about to read 3, iclass 16, count 2 2006.173.14:21:23.01#ibcon#read 3, iclass 16, count 2 2006.173.14:21:23.01#ibcon#about to read 4, iclass 16, count 2 2006.173.14:21:23.01#ibcon#read 4, iclass 16, count 2 2006.173.14:21:23.01#ibcon#about to read 5, iclass 16, count 2 2006.173.14:21:23.01#ibcon#read 5, iclass 16, count 2 2006.173.14:21:23.01#ibcon#about to read 6, iclass 16, count 2 2006.173.14:21:23.01#ibcon#read 6, iclass 16, count 2 2006.173.14:21:23.01#ibcon#end of sib2, iclass 16, count 2 2006.173.14:21:23.01#ibcon#*mode == 0, iclass 16, count 2 2006.173.14:21:23.01#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.14:21:23.01#ibcon#[27=AT01-04\r\n] 2006.173.14:21:23.01#ibcon#*before write, iclass 16, count 2 2006.173.14:21:23.01#ibcon#enter sib2, iclass 16, count 2 2006.173.14:21:23.01#ibcon#flushed, iclass 16, count 2 2006.173.14:21:23.01#ibcon#about to write, iclass 16, count 2 2006.173.14:21:23.01#ibcon#wrote, iclass 16, count 2 2006.173.14:21:23.01#ibcon#about to read 3, iclass 16, count 2 2006.173.14:21:23.04#ibcon#read 3, iclass 16, count 2 2006.173.14:21:23.04#ibcon#about to read 4, iclass 16, count 2 2006.173.14:21:23.04#ibcon#read 4, iclass 16, count 2 2006.173.14:21:23.04#ibcon#about to read 5, iclass 16, count 2 2006.173.14:21:23.04#ibcon#read 5, iclass 16, count 2 2006.173.14:21:23.04#ibcon#about to read 6, iclass 16, count 2 2006.173.14:21:23.04#ibcon#read 6, iclass 16, count 2 2006.173.14:21:23.04#ibcon#end of sib2, iclass 16, count 2 2006.173.14:21:23.04#ibcon#*after write, iclass 16, count 2 2006.173.14:21:23.04#ibcon#*before return 0, iclass 16, count 2 2006.173.14:21:23.04#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.14:21:23.04#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.14:21:23.04#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.14:21:23.04#ibcon#ireg 7 cls_cnt 0 2006.173.14:21:23.04#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.14:21:23.16#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.14:21:23.16#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.14:21:23.16#ibcon#enter wrdev, iclass 16, count 0 2006.173.14:21:23.16#ibcon#first serial, iclass 16, count 0 2006.173.14:21:23.16#ibcon#enter sib2, iclass 16, count 0 2006.173.14:21:23.16#ibcon#flushed, iclass 16, count 0 2006.173.14:21:23.16#ibcon#about to write, iclass 16, count 0 2006.173.14:21:23.16#ibcon#wrote, iclass 16, count 0 2006.173.14:21:23.16#ibcon#about to read 3, iclass 16, count 0 2006.173.14:21:23.18#ibcon#read 3, iclass 16, count 0 2006.173.14:21:23.18#ibcon#about to read 4, iclass 16, count 0 2006.173.14:21:23.18#ibcon#read 4, iclass 16, count 0 2006.173.14:21:23.18#ibcon#about to read 5, iclass 16, count 0 2006.173.14:21:23.18#ibcon#read 5, iclass 16, count 0 2006.173.14:21:23.18#ibcon#about to read 6, iclass 16, count 0 2006.173.14:21:23.18#ibcon#read 6, iclass 16, count 0 2006.173.14:21:23.18#ibcon#end of sib2, iclass 16, count 0 2006.173.14:21:23.18#ibcon#*mode == 0, iclass 16, count 0 2006.173.14:21:23.18#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.14:21:23.18#ibcon#[27=USB\r\n] 2006.173.14:21:23.18#ibcon#*before write, iclass 16, count 0 2006.173.14:21:23.18#ibcon#enter sib2, iclass 16, count 0 2006.173.14:21:23.18#ibcon#flushed, iclass 16, count 0 2006.173.14:21:23.18#ibcon#about to write, iclass 16, count 0 2006.173.14:21:23.18#ibcon#wrote, iclass 16, count 0 2006.173.14:21:23.18#ibcon#about to read 3, iclass 16, count 0 2006.173.14:21:23.21#ibcon#read 3, iclass 16, count 0 2006.173.14:21:23.21#ibcon#about to read 4, iclass 16, count 0 2006.173.14:21:23.21#ibcon#read 4, iclass 16, count 0 2006.173.14:21:23.21#ibcon#about to read 5, iclass 16, count 0 2006.173.14:21:23.21#ibcon#read 5, iclass 16, count 0 2006.173.14:21:23.21#ibcon#about to read 6, iclass 16, count 0 2006.173.14:21:23.21#ibcon#read 6, iclass 16, count 0 2006.173.14:21:23.21#ibcon#end of sib2, iclass 16, count 0 2006.173.14:21:23.21#ibcon#*after write, iclass 16, count 0 2006.173.14:21:23.21#ibcon#*before return 0, iclass 16, count 0 2006.173.14:21:23.21#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.14:21:23.21#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.14:21:23.21#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.14:21:23.21#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.14:21:23.21$vck44/vblo=2,634.99 2006.173.14:21:23.21#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.14:21:23.21#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.14:21:23.21#ibcon#ireg 17 cls_cnt 0 2006.173.14:21:23.21#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.14:21:23.21#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.14:21:23.21#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.14:21:23.21#ibcon#enter wrdev, iclass 18, count 0 2006.173.14:21:23.21#ibcon#first serial, iclass 18, count 0 2006.173.14:21:23.21#ibcon#enter sib2, iclass 18, count 0 2006.173.14:21:23.21#ibcon#flushed, iclass 18, count 0 2006.173.14:21:23.21#ibcon#about to write, iclass 18, count 0 2006.173.14:21:23.21#ibcon#wrote, iclass 18, count 0 2006.173.14:21:23.21#ibcon#about to read 3, iclass 18, count 0 2006.173.14:21:23.23#ibcon#read 3, iclass 18, count 0 2006.173.14:21:23.23#ibcon#about to read 4, iclass 18, count 0 2006.173.14:21:23.23#ibcon#read 4, iclass 18, count 0 2006.173.14:21:23.23#ibcon#about to read 5, iclass 18, count 0 2006.173.14:21:23.23#ibcon#read 5, iclass 18, count 0 2006.173.14:21:23.23#ibcon#about to read 6, iclass 18, count 0 2006.173.14:21:23.23#ibcon#read 6, iclass 18, count 0 2006.173.14:21:23.23#ibcon#end of sib2, iclass 18, count 0 2006.173.14:21:23.23#ibcon#*mode == 0, iclass 18, count 0 2006.173.14:21:23.23#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.14:21:23.23#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.14:21:23.23#ibcon#*before write, iclass 18, count 0 2006.173.14:21:23.23#ibcon#enter sib2, iclass 18, count 0 2006.173.14:21:23.23#ibcon#flushed, iclass 18, count 0 2006.173.14:21:23.23#ibcon#about to write, iclass 18, count 0 2006.173.14:21:23.23#ibcon#wrote, iclass 18, count 0 2006.173.14:21:23.23#ibcon#about to read 3, iclass 18, count 0 2006.173.14:21:23.27#ibcon#read 3, iclass 18, count 0 2006.173.14:21:23.27#ibcon#about to read 4, iclass 18, count 0 2006.173.14:21:23.27#ibcon#read 4, iclass 18, count 0 2006.173.14:21:23.27#ibcon#about to read 5, iclass 18, count 0 2006.173.14:21:23.27#ibcon#read 5, iclass 18, count 0 2006.173.14:21:23.27#ibcon#about to read 6, iclass 18, count 0 2006.173.14:21:23.27#ibcon#read 6, iclass 18, count 0 2006.173.14:21:23.27#ibcon#end of sib2, iclass 18, count 0 2006.173.14:21:23.27#ibcon#*after write, iclass 18, count 0 2006.173.14:21:23.27#ibcon#*before return 0, iclass 18, count 0 2006.173.14:21:23.27#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.14:21:23.27#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.14:21:23.27#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.14:21:23.27#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.14:21:23.27$vck44/vb=2,4 2006.173.14:21:23.27#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.14:21:23.27#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.14:21:23.27#ibcon#ireg 11 cls_cnt 2 2006.173.14:21:23.27#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.14:21:23.33#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.14:21:23.33#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.14:21:23.33#ibcon#enter wrdev, iclass 20, count 2 2006.173.14:21:23.33#ibcon#first serial, iclass 20, count 2 2006.173.14:21:23.33#ibcon#enter sib2, iclass 20, count 2 2006.173.14:21:23.33#ibcon#flushed, iclass 20, count 2 2006.173.14:21:23.33#ibcon#about to write, iclass 20, count 2 2006.173.14:21:23.33#ibcon#wrote, iclass 20, count 2 2006.173.14:21:23.33#ibcon#about to read 3, iclass 20, count 2 2006.173.14:21:23.35#ibcon#read 3, iclass 20, count 2 2006.173.14:21:23.35#ibcon#about to read 4, iclass 20, count 2 2006.173.14:21:23.35#ibcon#read 4, iclass 20, count 2 2006.173.14:21:23.35#ibcon#about to read 5, iclass 20, count 2 2006.173.14:21:23.35#ibcon#read 5, iclass 20, count 2 2006.173.14:21:23.35#ibcon#about to read 6, iclass 20, count 2 2006.173.14:21:23.35#ibcon#read 6, iclass 20, count 2 2006.173.14:21:23.35#ibcon#end of sib2, iclass 20, count 2 2006.173.14:21:23.35#ibcon#*mode == 0, iclass 20, count 2 2006.173.14:21:23.35#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.14:21:23.35#ibcon#[27=AT02-04\r\n] 2006.173.14:21:23.35#ibcon#*before write, iclass 20, count 2 2006.173.14:21:23.35#ibcon#enter sib2, iclass 20, count 2 2006.173.14:21:23.35#ibcon#flushed, iclass 20, count 2 2006.173.14:21:23.35#ibcon#about to write, iclass 20, count 2 2006.173.14:21:23.35#ibcon#wrote, iclass 20, count 2 2006.173.14:21:23.35#ibcon#about to read 3, iclass 20, count 2 2006.173.14:21:23.38#ibcon#read 3, iclass 20, count 2 2006.173.14:21:23.38#ibcon#about to read 4, iclass 20, count 2 2006.173.14:21:23.38#ibcon#read 4, iclass 20, count 2 2006.173.14:21:23.38#ibcon#about to read 5, iclass 20, count 2 2006.173.14:21:23.38#ibcon#read 5, iclass 20, count 2 2006.173.14:21:23.38#ibcon#about to read 6, iclass 20, count 2 2006.173.14:21:23.38#ibcon#read 6, iclass 20, count 2 2006.173.14:21:23.38#ibcon#end of sib2, iclass 20, count 2 2006.173.14:21:23.38#ibcon#*after write, iclass 20, count 2 2006.173.14:21:23.38#ibcon#*before return 0, iclass 20, count 2 2006.173.14:21:23.38#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.14:21:23.38#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.14:21:23.38#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.14:21:23.38#ibcon#ireg 7 cls_cnt 0 2006.173.14:21:23.38#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.14:21:23.50#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.14:21:23.50#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.14:21:23.50#ibcon#enter wrdev, iclass 20, count 0 2006.173.14:21:23.50#ibcon#first serial, iclass 20, count 0 2006.173.14:21:23.50#ibcon#enter sib2, iclass 20, count 0 2006.173.14:21:23.50#ibcon#flushed, iclass 20, count 0 2006.173.14:21:23.50#ibcon#about to write, iclass 20, count 0 2006.173.14:21:23.50#ibcon#wrote, iclass 20, count 0 2006.173.14:21:23.50#ibcon#about to read 3, iclass 20, count 0 2006.173.14:21:23.52#ibcon#read 3, iclass 20, count 0 2006.173.14:21:23.52#ibcon#about to read 4, iclass 20, count 0 2006.173.14:21:23.52#ibcon#read 4, iclass 20, count 0 2006.173.14:21:23.52#ibcon#about to read 5, iclass 20, count 0 2006.173.14:21:23.52#ibcon#read 5, iclass 20, count 0 2006.173.14:21:23.52#ibcon#about to read 6, iclass 20, count 0 2006.173.14:21:23.52#ibcon#read 6, iclass 20, count 0 2006.173.14:21:23.52#ibcon#end of sib2, iclass 20, count 0 2006.173.14:21:23.52#ibcon#*mode == 0, iclass 20, count 0 2006.173.14:21:23.52#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.14:21:23.52#ibcon#[27=USB\r\n] 2006.173.14:21:23.52#ibcon#*before write, iclass 20, count 0 2006.173.14:21:23.52#ibcon#enter sib2, iclass 20, count 0 2006.173.14:21:23.52#ibcon#flushed, iclass 20, count 0 2006.173.14:21:23.52#ibcon#about to write, iclass 20, count 0 2006.173.14:21:23.52#ibcon#wrote, iclass 20, count 0 2006.173.14:21:23.52#ibcon#about to read 3, iclass 20, count 0 2006.173.14:21:23.55#ibcon#read 3, iclass 20, count 0 2006.173.14:21:23.55#ibcon#about to read 4, iclass 20, count 0 2006.173.14:21:23.55#ibcon#read 4, iclass 20, count 0 2006.173.14:21:23.55#ibcon#about to read 5, iclass 20, count 0 2006.173.14:21:23.55#ibcon#read 5, iclass 20, count 0 2006.173.14:21:23.55#ibcon#about to read 6, iclass 20, count 0 2006.173.14:21:23.55#ibcon#read 6, iclass 20, count 0 2006.173.14:21:23.55#ibcon#end of sib2, iclass 20, count 0 2006.173.14:21:23.55#ibcon#*after write, iclass 20, count 0 2006.173.14:21:23.55#ibcon#*before return 0, iclass 20, count 0 2006.173.14:21:23.55#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.14:21:23.55#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.14:21:23.55#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.14:21:23.55#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.14:21:23.55$vck44/vblo=3,649.99 2006.173.14:21:23.55#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.14:21:23.55#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.14:21:23.55#ibcon#ireg 17 cls_cnt 0 2006.173.14:21:23.55#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.14:21:23.55#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.14:21:23.55#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.14:21:23.55#ibcon#enter wrdev, iclass 22, count 0 2006.173.14:21:23.55#ibcon#first serial, iclass 22, count 0 2006.173.14:21:23.55#ibcon#enter sib2, iclass 22, count 0 2006.173.14:21:23.55#ibcon#flushed, iclass 22, count 0 2006.173.14:21:23.55#ibcon#about to write, iclass 22, count 0 2006.173.14:21:23.55#ibcon#wrote, iclass 22, count 0 2006.173.14:21:23.55#ibcon#about to read 3, iclass 22, count 0 2006.173.14:21:23.57#ibcon#read 3, iclass 22, count 0 2006.173.14:21:23.57#ibcon#about to read 4, iclass 22, count 0 2006.173.14:21:23.57#ibcon#read 4, iclass 22, count 0 2006.173.14:21:23.57#ibcon#about to read 5, iclass 22, count 0 2006.173.14:21:23.57#ibcon#read 5, iclass 22, count 0 2006.173.14:21:23.57#ibcon#about to read 6, iclass 22, count 0 2006.173.14:21:23.57#ibcon#read 6, iclass 22, count 0 2006.173.14:21:23.57#ibcon#end of sib2, iclass 22, count 0 2006.173.14:21:23.57#ibcon#*mode == 0, iclass 22, count 0 2006.173.14:21:23.57#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.14:21:23.57#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.14:21:23.57#ibcon#*before write, iclass 22, count 0 2006.173.14:21:23.57#ibcon#enter sib2, iclass 22, count 0 2006.173.14:21:23.57#ibcon#flushed, iclass 22, count 0 2006.173.14:21:23.57#ibcon#about to write, iclass 22, count 0 2006.173.14:21:23.57#ibcon#wrote, iclass 22, count 0 2006.173.14:21:23.57#ibcon#about to read 3, iclass 22, count 0 2006.173.14:21:23.61#ibcon#read 3, iclass 22, count 0 2006.173.14:21:23.61#ibcon#about to read 4, iclass 22, count 0 2006.173.14:21:23.61#ibcon#read 4, iclass 22, count 0 2006.173.14:21:23.61#ibcon#about to read 5, iclass 22, count 0 2006.173.14:21:23.61#ibcon#read 5, iclass 22, count 0 2006.173.14:21:23.61#ibcon#about to read 6, iclass 22, count 0 2006.173.14:21:23.61#ibcon#read 6, iclass 22, count 0 2006.173.14:21:23.61#ibcon#end of sib2, iclass 22, count 0 2006.173.14:21:23.61#ibcon#*after write, iclass 22, count 0 2006.173.14:21:23.61#ibcon#*before return 0, iclass 22, count 0 2006.173.14:21:23.61#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.14:21:23.61#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.14:21:23.61#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.14:21:23.61#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.14:21:23.61$vck44/vb=3,4 2006.173.14:21:23.61#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.14:21:23.61#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.14:21:23.61#ibcon#ireg 11 cls_cnt 2 2006.173.14:21:23.61#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.14:21:23.67#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.14:21:23.67#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.14:21:23.67#ibcon#enter wrdev, iclass 24, count 2 2006.173.14:21:23.67#ibcon#first serial, iclass 24, count 2 2006.173.14:21:23.67#ibcon#enter sib2, iclass 24, count 2 2006.173.14:21:23.67#ibcon#flushed, iclass 24, count 2 2006.173.14:21:23.67#ibcon#about to write, iclass 24, count 2 2006.173.14:21:23.67#ibcon#wrote, iclass 24, count 2 2006.173.14:21:23.67#ibcon#about to read 3, iclass 24, count 2 2006.173.14:21:23.69#ibcon#read 3, iclass 24, count 2 2006.173.14:21:23.69#ibcon#about to read 4, iclass 24, count 2 2006.173.14:21:23.69#ibcon#read 4, iclass 24, count 2 2006.173.14:21:23.69#ibcon#about to read 5, iclass 24, count 2 2006.173.14:21:23.69#ibcon#read 5, iclass 24, count 2 2006.173.14:21:23.69#ibcon#about to read 6, iclass 24, count 2 2006.173.14:21:23.69#ibcon#read 6, iclass 24, count 2 2006.173.14:21:23.69#ibcon#end of sib2, iclass 24, count 2 2006.173.14:21:23.69#ibcon#*mode == 0, iclass 24, count 2 2006.173.14:21:23.69#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.14:21:23.69#ibcon#[27=AT03-04\r\n] 2006.173.14:21:23.69#ibcon#*before write, iclass 24, count 2 2006.173.14:21:23.69#ibcon#enter sib2, iclass 24, count 2 2006.173.14:21:23.69#ibcon#flushed, iclass 24, count 2 2006.173.14:21:23.69#ibcon#about to write, iclass 24, count 2 2006.173.14:21:23.69#ibcon#wrote, iclass 24, count 2 2006.173.14:21:23.69#ibcon#about to read 3, iclass 24, count 2 2006.173.14:21:23.72#ibcon#read 3, iclass 24, count 2 2006.173.14:21:23.72#ibcon#about to read 4, iclass 24, count 2 2006.173.14:21:23.72#ibcon#read 4, iclass 24, count 2 2006.173.14:21:23.72#ibcon#about to read 5, iclass 24, count 2 2006.173.14:21:23.72#ibcon#read 5, iclass 24, count 2 2006.173.14:21:23.72#ibcon#about to read 6, iclass 24, count 2 2006.173.14:21:23.72#ibcon#read 6, iclass 24, count 2 2006.173.14:21:23.72#ibcon#end of sib2, iclass 24, count 2 2006.173.14:21:23.72#ibcon#*after write, iclass 24, count 2 2006.173.14:21:23.72#ibcon#*before return 0, iclass 24, count 2 2006.173.14:21:23.72#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.14:21:23.72#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.14:21:23.72#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.14:21:23.72#ibcon#ireg 7 cls_cnt 0 2006.173.14:21:23.72#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.14:21:23.84#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.14:21:23.84#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.14:21:23.84#ibcon#enter wrdev, iclass 24, count 0 2006.173.14:21:23.84#ibcon#first serial, iclass 24, count 0 2006.173.14:21:23.84#ibcon#enter sib2, iclass 24, count 0 2006.173.14:21:23.84#ibcon#flushed, iclass 24, count 0 2006.173.14:21:23.84#ibcon#about to write, iclass 24, count 0 2006.173.14:21:23.84#ibcon#wrote, iclass 24, count 0 2006.173.14:21:23.84#ibcon#about to read 3, iclass 24, count 0 2006.173.14:21:23.86#ibcon#read 3, iclass 24, count 0 2006.173.14:21:23.86#ibcon#about to read 4, iclass 24, count 0 2006.173.14:21:23.86#ibcon#read 4, iclass 24, count 0 2006.173.14:21:23.86#ibcon#about to read 5, iclass 24, count 0 2006.173.14:21:23.86#ibcon#read 5, iclass 24, count 0 2006.173.14:21:23.86#ibcon#about to read 6, iclass 24, count 0 2006.173.14:21:23.86#ibcon#read 6, iclass 24, count 0 2006.173.14:21:23.86#ibcon#end of sib2, iclass 24, count 0 2006.173.14:21:23.86#ibcon#*mode == 0, iclass 24, count 0 2006.173.14:21:23.86#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.14:21:23.86#ibcon#[27=USB\r\n] 2006.173.14:21:23.86#ibcon#*before write, iclass 24, count 0 2006.173.14:21:23.86#ibcon#enter sib2, iclass 24, count 0 2006.173.14:21:23.86#ibcon#flushed, iclass 24, count 0 2006.173.14:21:23.86#ibcon#about to write, iclass 24, count 0 2006.173.14:21:23.86#ibcon#wrote, iclass 24, count 0 2006.173.14:21:23.86#ibcon#about to read 3, iclass 24, count 0 2006.173.14:21:23.89#ibcon#read 3, iclass 24, count 0 2006.173.14:21:23.89#ibcon#about to read 4, iclass 24, count 0 2006.173.14:21:23.89#ibcon#read 4, iclass 24, count 0 2006.173.14:21:23.89#ibcon#about to read 5, iclass 24, count 0 2006.173.14:21:23.89#ibcon#read 5, iclass 24, count 0 2006.173.14:21:23.89#ibcon#about to read 6, iclass 24, count 0 2006.173.14:21:23.89#ibcon#read 6, iclass 24, count 0 2006.173.14:21:23.89#ibcon#end of sib2, iclass 24, count 0 2006.173.14:21:23.89#ibcon#*after write, iclass 24, count 0 2006.173.14:21:23.89#ibcon#*before return 0, iclass 24, count 0 2006.173.14:21:23.89#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.14:21:23.89#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.14:21:23.89#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.14:21:23.89#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.14:21:23.89$vck44/vblo=4,679.99 2006.173.14:21:23.89#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.14:21:23.89#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.14:21:23.89#ibcon#ireg 17 cls_cnt 0 2006.173.14:21:23.89#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.14:21:23.89#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.14:21:23.89#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.14:21:23.89#ibcon#enter wrdev, iclass 26, count 0 2006.173.14:21:23.89#ibcon#first serial, iclass 26, count 0 2006.173.14:21:23.89#ibcon#enter sib2, iclass 26, count 0 2006.173.14:21:23.89#ibcon#flushed, iclass 26, count 0 2006.173.14:21:23.89#ibcon#about to write, iclass 26, count 0 2006.173.14:21:23.89#ibcon#wrote, iclass 26, count 0 2006.173.14:21:23.89#ibcon#about to read 3, iclass 26, count 0 2006.173.14:21:23.91#ibcon#read 3, iclass 26, count 0 2006.173.14:21:23.91#ibcon#about to read 4, iclass 26, count 0 2006.173.14:21:23.91#ibcon#read 4, iclass 26, count 0 2006.173.14:21:23.91#ibcon#about to read 5, iclass 26, count 0 2006.173.14:21:23.91#ibcon#read 5, iclass 26, count 0 2006.173.14:21:23.91#ibcon#about to read 6, iclass 26, count 0 2006.173.14:21:23.91#ibcon#read 6, iclass 26, count 0 2006.173.14:21:23.91#ibcon#end of sib2, iclass 26, count 0 2006.173.14:21:23.91#ibcon#*mode == 0, iclass 26, count 0 2006.173.14:21:23.91#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.14:21:23.91#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.14:21:23.91#ibcon#*before write, iclass 26, count 0 2006.173.14:21:23.91#ibcon#enter sib2, iclass 26, count 0 2006.173.14:21:23.91#ibcon#flushed, iclass 26, count 0 2006.173.14:21:23.91#ibcon#about to write, iclass 26, count 0 2006.173.14:21:23.91#ibcon#wrote, iclass 26, count 0 2006.173.14:21:23.91#ibcon#about to read 3, iclass 26, count 0 2006.173.14:21:23.95#ibcon#read 3, iclass 26, count 0 2006.173.14:21:23.95#ibcon#about to read 4, iclass 26, count 0 2006.173.14:21:23.95#ibcon#read 4, iclass 26, count 0 2006.173.14:21:23.95#ibcon#about to read 5, iclass 26, count 0 2006.173.14:21:23.95#ibcon#read 5, iclass 26, count 0 2006.173.14:21:23.95#ibcon#about to read 6, iclass 26, count 0 2006.173.14:21:23.95#ibcon#read 6, iclass 26, count 0 2006.173.14:21:23.95#ibcon#end of sib2, iclass 26, count 0 2006.173.14:21:23.95#ibcon#*after write, iclass 26, count 0 2006.173.14:21:23.95#ibcon#*before return 0, iclass 26, count 0 2006.173.14:21:23.95#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.14:21:23.95#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.14:21:23.95#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.14:21:23.95#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.14:21:23.95$vck44/vb=4,4 2006.173.14:21:23.95#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.14:21:23.95#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.14:21:23.95#ibcon#ireg 11 cls_cnt 2 2006.173.14:21:23.95#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.14:21:24.01#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.14:21:24.01#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.14:21:24.01#ibcon#enter wrdev, iclass 28, count 2 2006.173.14:21:24.01#ibcon#first serial, iclass 28, count 2 2006.173.14:21:24.01#ibcon#enter sib2, iclass 28, count 2 2006.173.14:21:24.01#ibcon#flushed, iclass 28, count 2 2006.173.14:21:24.01#ibcon#about to write, iclass 28, count 2 2006.173.14:21:24.01#ibcon#wrote, iclass 28, count 2 2006.173.14:21:24.01#ibcon#about to read 3, iclass 28, count 2 2006.173.14:21:24.03#ibcon#read 3, iclass 28, count 2 2006.173.14:21:24.03#ibcon#about to read 4, iclass 28, count 2 2006.173.14:21:24.03#ibcon#read 4, iclass 28, count 2 2006.173.14:21:24.03#ibcon#about to read 5, iclass 28, count 2 2006.173.14:21:24.03#ibcon#read 5, iclass 28, count 2 2006.173.14:21:24.03#ibcon#about to read 6, iclass 28, count 2 2006.173.14:21:24.03#ibcon#read 6, iclass 28, count 2 2006.173.14:21:24.03#ibcon#end of sib2, iclass 28, count 2 2006.173.14:21:24.03#ibcon#*mode == 0, iclass 28, count 2 2006.173.14:21:24.03#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.14:21:24.03#ibcon#[27=AT04-04\r\n] 2006.173.14:21:24.03#ibcon#*before write, iclass 28, count 2 2006.173.14:21:24.03#ibcon#enter sib2, iclass 28, count 2 2006.173.14:21:24.03#ibcon#flushed, iclass 28, count 2 2006.173.14:21:24.03#ibcon#about to write, iclass 28, count 2 2006.173.14:21:24.03#ibcon#wrote, iclass 28, count 2 2006.173.14:21:24.03#ibcon#about to read 3, iclass 28, count 2 2006.173.14:21:24.06#ibcon#read 3, iclass 28, count 2 2006.173.14:21:24.06#ibcon#about to read 4, iclass 28, count 2 2006.173.14:21:24.06#ibcon#read 4, iclass 28, count 2 2006.173.14:21:24.06#ibcon#about to read 5, iclass 28, count 2 2006.173.14:21:24.06#ibcon#read 5, iclass 28, count 2 2006.173.14:21:24.06#ibcon#about to read 6, iclass 28, count 2 2006.173.14:21:24.06#ibcon#read 6, iclass 28, count 2 2006.173.14:21:24.06#ibcon#end of sib2, iclass 28, count 2 2006.173.14:21:24.06#ibcon#*after write, iclass 28, count 2 2006.173.14:21:24.06#ibcon#*before return 0, iclass 28, count 2 2006.173.14:21:24.06#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.14:21:24.06#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.14:21:24.06#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.14:21:24.06#ibcon#ireg 7 cls_cnt 0 2006.173.14:21:24.06#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.14:21:24.09#abcon#<5=/14 1.2 2.4 21.551001004.0\r\n> 2006.173.14:21:24.11#abcon#{5=INTERFACE CLEAR} 2006.173.14:21:24.17#abcon#[5=S1D000X0/0*\r\n] 2006.173.14:21:24.18#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.14:21:24.18#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.14:21:24.18#ibcon#enter wrdev, iclass 28, count 0 2006.173.14:21:24.18#ibcon#first serial, iclass 28, count 0 2006.173.14:21:24.18#ibcon#enter sib2, iclass 28, count 0 2006.173.14:21:24.18#ibcon#flushed, iclass 28, count 0 2006.173.14:21:24.18#ibcon#about to write, iclass 28, count 0 2006.173.14:21:24.18#ibcon#wrote, iclass 28, count 0 2006.173.14:21:24.18#ibcon#about to read 3, iclass 28, count 0 2006.173.14:21:24.20#ibcon#read 3, iclass 28, count 0 2006.173.14:21:24.20#ibcon#about to read 4, iclass 28, count 0 2006.173.14:21:24.20#ibcon#read 4, iclass 28, count 0 2006.173.14:21:24.20#ibcon#about to read 5, iclass 28, count 0 2006.173.14:21:24.20#ibcon#read 5, iclass 28, count 0 2006.173.14:21:24.20#ibcon#about to read 6, iclass 28, count 0 2006.173.14:21:24.20#ibcon#read 6, iclass 28, count 0 2006.173.14:21:24.20#ibcon#end of sib2, iclass 28, count 0 2006.173.14:21:24.20#ibcon#*mode == 0, iclass 28, count 0 2006.173.14:21:24.20#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.14:21:24.20#ibcon#[27=USB\r\n] 2006.173.14:21:24.20#ibcon#*before write, iclass 28, count 0 2006.173.14:21:24.20#ibcon#enter sib2, iclass 28, count 0 2006.173.14:21:24.20#ibcon#flushed, iclass 28, count 0 2006.173.14:21:24.20#ibcon#about to write, iclass 28, count 0 2006.173.14:21:24.20#ibcon#wrote, iclass 28, count 0 2006.173.14:21:24.20#ibcon#about to read 3, iclass 28, count 0 2006.173.14:21:24.23#ibcon#read 3, iclass 28, count 0 2006.173.14:21:24.23#ibcon#about to read 4, iclass 28, count 0 2006.173.14:21:24.23#ibcon#read 4, iclass 28, count 0 2006.173.14:21:24.23#ibcon#about to read 5, iclass 28, count 0 2006.173.14:21:24.23#ibcon#read 5, iclass 28, count 0 2006.173.14:21:24.23#ibcon#about to read 6, iclass 28, count 0 2006.173.14:21:24.23#ibcon#read 6, iclass 28, count 0 2006.173.14:21:24.23#ibcon#end of sib2, iclass 28, count 0 2006.173.14:21:24.23#ibcon#*after write, iclass 28, count 0 2006.173.14:21:24.23#ibcon#*before return 0, iclass 28, count 0 2006.173.14:21:24.23#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.14:21:24.23#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.14:21:24.23#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.14:21:24.23#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.14:21:24.23$vck44/vblo=5,709.99 2006.173.14:21:24.23#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.14:21:24.23#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.14:21:24.23#ibcon#ireg 17 cls_cnt 0 2006.173.14:21:24.23#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.14:21:24.23#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.14:21:24.23#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.14:21:24.23#ibcon#enter wrdev, iclass 34, count 0 2006.173.14:21:24.23#ibcon#first serial, iclass 34, count 0 2006.173.14:21:24.23#ibcon#enter sib2, iclass 34, count 0 2006.173.14:21:24.23#ibcon#flushed, iclass 34, count 0 2006.173.14:21:24.23#ibcon#about to write, iclass 34, count 0 2006.173.14:21:24.23#ibcon#wrote, iclass 34, count 0 2006.173.14:21:24.23#ibcon#about to read 3, iclass 34, count 0 2006.173.14:21:24.25#ibcon#read 3, iclass 34, count 0 2006.173.14:21:24.25#ibcon#about to read 4, iclass 34, count 0 2006.173.14:21:24.25#ibcon#read 4, iclass 34, count 0 2006.173.14:21:24.25#ibcon#about to read 5, iclass 34, count 0 2006.173.14:21:24.25#ibcon#read 5, iclass 34, count 0 2006.173.14:21:24.25#ibcon#about to read 6, iclass 34, count 0 2006.173.14:21:24.25#ibcon#read 6, iclass 34, count 0 2006.173.14:21:24.25#ibcon#end of sib2, iclass 34, count 0 2006.173.14:21:24.25#ibcon#*mode == 0, iclass 34, count 0 2006.173.14:21:24.25#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.14:21:24.25#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.14:21:24.25#ibcon#*before write, iclass 34, count 0 2006.173.14:21:24.25#ibcon#enter sib2, iclass 34, count 0 2006.173.14:21:24.25#ibcon#flushed, iclass 34, count 0 2006.173.14:21:24.25#ibcon#about to write, iclass 34, count 0 2006.173.14:21:24.25#ibcon#wrote, iclass 34, count 0 2006.173.14:21:24.25#ibcon#about to read 3, iclass 34, count 0 2006.173.14:21:24.29#ibcon#read 3, iclass 34, count 0 2006.173.14:21:24.29#ibcon#about to read 4, iclass 34, count 0 2006.173.14:21:24.29#ibcon#read 4, iclass 34, count 0 2006.173.14:21:24.29#ibcon#about to read 5, iclass 34, count 0 2006.173.14:21:24.29#ibcon#read 5, iclass 34, count 0 2006.173.14:21:24.29#ibcon#about to read 6, iclass 34, count 0 2006.173.14:21:24.29#ibcon#read 6, iclass 34, count 0 2006.173.14:21:24.29#ibcon#end of sib2, iclass 34, count 0 2006.173.14:21:24.29#ibcon#*after write, iclass 34, count 0 2006.173.14:21:24.29#ibcon#*before return 0, iclass 34, count 0 2006.173.14:21:24.29#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.14:21:24.29#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.14:21:24.29#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.14:21:24.29#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.14:21:24.29$vck44/vb=5,4 2006.173.14:21:24.29#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.14:21:24.29#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.14:21:24.29#ibcon#ireg 11 cls_cnt 2 2006.173.14:21:24.29#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.14:21:24.35#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.14:21:24.35#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.14:21:24.35#ibcon#enter wrdev, iclass 36, count 2 2006.173.14:21:24.35#ibcon#first serial, iclass 36, count 2 2006.173.14:21:24.35#ibcon#enter sib2, iclass 36, count 2 2006.173.14:21:24.35#ibcon#flushed, iclass 36, count 2 2006.173.14:21:24.35#ibcon#about to write, iclass 36, count 2 2006.173.14:21:24.35#ibcon#wrote, iclass 36, count 2 2006.173.14:21:24.35#ibcon#about to read 3, iclass 36, count 2 2006.173.14:21:24.37#ibcon#read 3, iclass 36, count 2 2006.173.14:21:24.37#ibcon#about to read 4, iclass 36, count 2 2006.173.14:21:24.37#ibcon#read 4, iclass 36, count 2 2006.173.14:21:24.37#ibcon#about to read 5, iclass 36, count 2 2006.173.14:21:24.37#ibcon#read 5, iclass 36, count 2 2006.173.14:21:24.37#ibcon#about to read 6, iclass 36, count 2 2006.173.14:21:24.37#ibcon#read 6, iclass 36, count 2 2006.173.14:21:24.37#ibcon#end of sib2, iclass 36, count 2 2006.173.14:21:24.37#ibcon#*mode == 0, iclass 36, count 2 2006.173.14:21:24.37#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.14:21:24.37#ibcon#[27=AT05-04\r\n] 2006.173.14:21:24.37#ibcon#*before write, iclass 36, count 2 2006.173.14:21:24.37#ibcon#enter sib2, iclass 36, count 2 2006.173.14:21:24.37#ibcon#flushed, iclass 36, count 2 2006.173.14:21:24.37#ibcon#about to write, iclass 36, count 2 2006.173.14:21:24.37#ibcon#wrote, iclass 36, count 2 2006.173.14:21:24.37#ibcon#about to read 3, iclass 36, count 2 2006.173.14:21:24.40#ibcon#read 3, iclass 36, count 2 2006.173.14:21:24.40#ibcon#about to read 4, iclass 36, count 2 2006.173.14:21:24.40#ibcon#read 4, iclass 36, count 2 2006.173.14:21:24.40#ibcon#about to read 5, iclass 36, count 2 2006.173.14:21:24.40#ibcon#read 5, iclass 36, count 2 2006.173.14:21:24.40#ibcon#about to read 6, iclass 36, count 2 2006.173.14:21:24.40#ibcon#read 6, iclass 36, count 2 2006.173.14:21:24.40#ibcon#end of sib2, iclass 36, count 2 2006.173.14:21:24.40#ibcon#*after write, iclass 36, count 2 2006.173.14:21:24.40#ibcon#*before return 0, iclass 36, count 2 2006.173.14:21:24.40#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.14:21:24.40#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.14:21:24.40#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.14:21:24.40#ibcon#ireg 7 cls_cnt 0 2006.173.14:21:24.40#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.14:21:24.52#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.14:21:24.52#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.14:21:24.52#ibcon#enter wrdev, iclass 36, count 0 2006.173.14:21:24.52#ibcon#first serial, iclass 36, count 0 2006.173.14:21:24.52#ibcon#enter sib2, iclass 36, count 0 2006.173.14:21:24.52#ibcon#flushed, iclass 36, count 0 2006.173.14:21:24.52#ibcon#about to write, iclass 36, count 0 2006.173.14:21:24.52#ibcon#wrote, iclass 36, count 0 2006.173.14:21:24.52#ibcon#about to read 3, iclass 36, count 0 2006.173.14:21:24.54#ibcon#read 3, iclass 36, count 0 2006.173.14:21:24.54#ibcon#about to read 4, iclass 36, count 0 2006.173.14:21:24.54#ibcon#read 4, iclass 36, count 0 2006.173.14:21:24.54#ibcon#about to read 5, iclass 36, count 0 2006.173.14:21:24.54#ibcon#read 5, iclass 36, count 0 2006.173.14:21:24.54#ibcon#about to read 6, iclass 36, count 0 2006.173.14:21:24.54#ibcon#read 6, iclass 36, count 0 2006.173.14:21:24.54#ibcon#end of sib2, iclass 36, count 0 2006.173.14:21:24.54#ibcon#*mode == 0, iclass 36, count 0 2006.173.14:21:24.54#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.14:21:24.54#ibcon#[27=USB\r\n] 2006.173.14:21:24.54#ibcon#*before write, iclass 36, count 0 2006.173.14:21:24.54#ibcon#enter sib2, iclass 36, count 0 2006.173.14:21:24.54#ibcon#flushed, iclass 36, count 0 2006.173.14:21:24.54#ibcon#about to write, iclass 36, count 0 2006.173.14:21:24.54#ibcon#wrote, iclass 36, count 0 2006.173.14:21:24.54#ibcon#about to read 3, iclass 36, count 0 2006.173.14:21:24.57#ibcon#read 3, iclass 36, count 0 2006.173.14:21:24.57#ibcon#about to read 4, iclass 36, count 0 2006.173.14:21:24.57#ibcon#read 4, iclass 36, count 0 2006.173.14:21:24.57#ibcon#about to read 5, iclass 36, count 0 2006.173.14:21:24.57#ibcon#read 5, iclass 36, count 0 2006.173.14:21:24.57#ibcon#about to read 6, iclass 36, count 0 2006.173.14:21:24.57#ibcon#read 6, iclass 36, count 0 2006.173.14:21:24.57#ibcon#end of sib2, iclass 36, count 0 2006.173.14:21:24.57#ibcon#*after write, iclass 36, count 0 2006.173.14:21:24.57#ibcon#*before return 0, iclass 36, count 0 2006.173.14:21:24.57#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.14:21:24.57#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.14:21:24.57#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.14:21:24.57#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.14:21:24.57$vck44/vblo=6,719.99 2006.173.14:21:24.57#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.14:21:24.57#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.14:21:24.57#ibcon#ireg 17 cls_cnt 0 2006.173.14:21:24.57#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.14:21:24.57#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.14:21:24.57#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.14:21:24.57#ibcon#enter wrdev, iclass 38, count 0 2006.173.14:21:24.57#ibcon#first serial, iclass 38, count 0 2006.173.14:21:24.57#ibcon#enter sib2, iclass 38, count 0 2006.173.14:21:24.57#ibcon#flushed, iclass 38, count 0 2006.173.14:21:24.57#ibcon#about to write, iclass 38, count 0 2006.173.14:21:24.57#ibcon#wrote, iclass 38, count 0 2006.173.14:21:24.57#ibcon#about to read 3, iclass 38, count 0 2006.173.14:21:24.59#ibcon#read 3, iclass 38, count 0 2006.173.14:21:24.59#ibcon#about to read 4, iclass 38, count 0 2006.173.14:21:24.59#ibcon#read 4, iclass 38, count 0 2006.173.14:21:24.59#ibcon#about to read 5, iclass 38, count 0 2006.173.14:21:24.59#ibcon#read 5, iclass 38, count 0 2006.173.14:21:24.59#ibcon#about to read 6, iclass 38, count 0 2006.173.14:21:24.59#ibcon#read 6, iclass 38, count 0 2006.173.14:21:24.59#ibcon#end of sib2, iclass 38, count 0 2006.173.14:21:24.59#ibcon#*mode == 0, iclass 38, count 0 2006.173.14:21:24.59#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.14:21:24.59#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.14:21:24.59#ibcon#*before write, iclass 38, count 0 2006.173.14:21:24.59#ibcon#enter sib2, iclass 38, count 0 2006.173.14:21:24.59#ibcon#flushed, iclass 38, count 0 2006.173.14:21:24.59#ibcon#about to write, iclass 38, count 0 2006.173.14:21:24.59#ibcon#wrote, iclass 38, count 0 2006.173.14:21:24.59#ibcon#about to read 3, iclass 38, count 0 2006.173.14:21:24.63#ibcon#read 3, iclass 38, count 0 2006.173.14:21:24.63#ibcon#about to read 4, iclass 38, count 0 2006.173.14:21:24.63#ibcon#read 4, iclass 38, count 0 2006.173.14:21:24.63#ibcon#about to read 5, iclass 38, count 0 2006.173.14:21:24.63#ibcon#read 5, iclass 38, count 0 2006.173.14:21:24.63#ibcon#about to read 6, iclass 38, count 0 2006.173.14:21:24.63#ibcon#read 6, iclass 38, count 0 2006.173.14:21:24.63#ibcon#end of sib2, iclass 38, count 0 2006.173.14:21:24.63#ibcon#*after write, iclass 38, count 0 2006.173.14:21:24.63#ibcon#*before return 0, iclass 38, count 0 2006.173.14:21:24.63#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.14:21:24.63#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.14:21:24.63#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.14:21:24.63#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.14:21:24.63$vck44/vb=6,4 2006.173.14:21:24.63#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.14:21:24.63#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.14:21:24.63#ibcon#ireg 11 cls_cnt 2 2006.173.14:21:24.63#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.14:21:24.69#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.14:21:24.69#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.14:21:24.69#ibcon#enter wrdev, iclass 40, count 2 2006.173.14:21:24.69#ibcon#first serial, iclass 40, count 2 2006.173.14:21:24.69#ibcon#enter sib2, iclass 40, count 2 2006.173.14:21:24.69#ibcon#flushed, iclass 40, count 2 2006.173.14:21:24.69#ibcon#about to write, iclass 40, count 2 2006.173.14:21:24.69#ibcon#wrote, iclass 40, count 2 2006.173.14:21:24.69#ibcon#about to read 3, iclass 40, count 2 2006.173.14:21:24.71#ibcon#read 3, iclass 40, count 2 2006.173.14:21:24.71#ibcon#about to read 4, iclass 40, count 2 2006.173.14:21:24.71#ibcon#read 4, iclass 40, count 2 2006.173.14:21:24.71#ibcon#about to read 5, iclass 40, count 2 2006.173.14:21:24.71#ibcon#read 5, iclass 40, count 2 2006.173.14:21:24.71#ibcon#about to read 6, iclass 40, count 2 2006.173.14:21:24.71#ibcon#read 6, iclass 40, count 2 2006.173.14:21:24.71#ibcon#end of sib2, iclass 40, count 2 2006.173.14:21:24.71#ibcon#*mode == 0, iclass 40, count 2 2006.173.14:21:24.71#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.14:21:24.71#ibcon#[27=AT06-04\r\n] 2006.173.14:21:24.71#ibcon#*before write, iclass 40, count 2 2006.173.14:21:24.71#ibcon#enter sib2, iclass 40, count 2 2006.173.14:21:24.71#ibcon#flushed, iclass 40, count 2 2006.173.14:21:24.71#ibcon#about to write, iclass 40, count 2 2006.173.14:21:24.71#ibcon#wrote, iclass 40, count 2 2006.173.14:21:24.71#ibcon#about to read 3, iclass 40, count 2 2006.173.14:21:24.74#ibcon#read 3, iclass 40, count 2 2006.173.14:21:24.74#ibcon#about to read 4, iclass 40, count 2 2006.173.14:21:24.74#ibcon#read 4, iclass 40, count 2 2006.173.14:21:24.74#ibcon#about to read 5, iclass 40, count 2 2006.173.14:21:24.74#ibcon#read 5, iclass 40, count 2 2006.173.14:21:24.74#ibcon#about to read 6, iclass 40, count 2 2006.173.14:21:24.74#ibcon#read 6, iclass 40, count 2 2006.173.14:21:24.74#ibcon#end of sib2, iclass 40, count 2 2006.173.14:21:24.74#ibcon#*after write, iclass 40, count 2 2006.173.14:21:24.74#ibcon#*before return 0, iclass 40, count 2 2006.173.14:21:24.74#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.14:21:24.74#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.14:21:24.74#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.14:21:24.74#ibcon#ireg 7 cls_cnt 0 2006.173.14:21:24.74#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.14:21:24.86#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.14:21:24.86#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.14:21:24.86#ibcon#enter wrdev, iclass 40, count 0 2006.173.14:21:24.86#ibcon#first serial, iclass 40, count 0 2006.173.14:21:24.86#ibcon#enter sib2, iclass 40, count 0 2006.173.14:21:24.86#ibcon#flushed, iclass 40, count 0 2006.173.14:21:24.86#ibcon#about to write, iclass 40, count 0 2006.173.14:21:24.86#ibcon#wrote, iclass 40, count 0 2006.173.14:21:24.86#ibcon#about to read 3, iclass 40, count 0 2006.173.14:21:24.88#ibcon#read 3, iclass 40, count 0 2006.173.14:21:24.88#ibcon#about to read 4, iclass 40, count 0 2006.173.14:21:24.88#ibcon#read 4, iclass 40, count 0 2006.173.14:21:24.88#ibcon#about to read 5, iclass 40, count 0 2006.173.14:21:24.88#ibcon#read 5, iclass 40, count 0 2006.173.14:21:24.88#ibcon#about to read 6, iclass 40, count 0 2006.173.14:21:24.88#ibcon#read 6, iclass 40, count 0 2006.173.14:21:24.88#ibcon#end of sib2, iclass 40, count 0 2006.173.14:21:24.88#ibcon#*mode == 0, iclass 40, count 0 2006.173.14:21:24.88#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.14:21:24.88#ibcon#[27=USB\r\n] 2006.173.14:21:24.88#ibcon#*before write, iclass 40, count 0 2006.173.14:21:24.88#ibcon#enter sib2, iclass 40, count 0 2006.173.14:21:24.88#ibcon#flushed, iclass 40, count 0 2006.173.14:21:24.88#ibcon#about to write, iclass 40, count 0 2006.173.14:21:24.88#ibcon#wrote, iclass 40, count 0 2006.173.14:21:24.88#ibcon#about to read 3, iclass 40, count 0 2006.173.14:21:24.91#ibcon#read 3, iclass 40, count 0 2006.173.14:21:24.91#ibcon#about to read 4, iclass 40, count 0 2006.173.14:21:24.91#ibcon#read 4, iclass 40, count 0 2006.173.14:21:24.91#ibcon#about to read 5, iclass 40, count 0 2006.173.14:21:24.91#ibcon#read 5, iclass 40, count 0 2006.173.14:21:24.91#ibcon#about to read 6, iclass 40, count 0 2006.173.14:21:24.91#ibcon#read 6, iclass 40, count 0 2006.173.14:21:24.91#ibcon#end of sib2, iclass 40, count 0 2006.173.14:21:24.91#ibcon#*after write, iclass 40, count 0 2006.173.14:21:24.91#ibcon#*before return 0, iclass 40, count 0 2006.173.14:21:24.91#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.14:21:24.91#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.14:21:24.91#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.14:21:24.91#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.14:21:24.91$vck44/vblo=7,734.99 2006.173.14:21:24.91#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.14:21:24.91#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.14:21:24.91#ibcon#ireg 17 cls_cnt 0 2006.173.14:21:24.91#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.14:21:24.91#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.14:21:24.91#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.14:21:24.91#ibcon#enter wrdev, iclass 4, count 0 2006.173.14:21:24.91#ibcon#first serial, iclass 4, count 0 2006.173.14:21:24.91#ibcon#enter sib2, iclass 4, count 0 2006.173.14:21:24.91#ibcon#flushed, iclass 4, count 0 2006.173.14:21:24.91#ibcon#about to write, iclass 4, count 0 2006.173.14:21:24.91#ibcon#wrote, iclass 4, count 0 2006.173.14:21:24.91#ibcon#about to read 3, iclass 4, count 0 2006.173.14:21:24.93#ibcon#read 3, iclass 4, count 0 2006.173.14:21:24.93#ibcon#about to read 4, iclass 4, count 0 2006.173.14:21:24.93#ibcon#read 4, iclass 4, count 0 2006.173.14:21:24.93#ibcon#about to read 5, iclass 4, count 0 2006.173.14:21:24.93#ibcon#read 5, iclass 4, count 0 2006.173.14:21:24.93#ibcon#about to read 6, iclass 4, count 0 2006.173.14:21:24.93#ibcon#read 6, iclass 4, count 0 2006.173.14:21:24.93#ibcon#end of sib2, iclass 4, count 0 2006.173.14:21:24.93#ibcon#*mode == 0, iclass 4, count 0 2006.173.14:21:24.93#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.14:21:24.93#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.14:21:24.93#ibcon#*before write, iclass 4, count 0 2006.173.14:21:24.93#ibcon#enter sib2, iclass 4, count 0 2006.173.14:21:24.93#ibcon#flushed, iclass 4, count 0 2006.173.14:21:24.93#ibcon#about to write, iclass 4, count 0 2006.173.14:21:24.93#ibcon#wrote, iclass 4, count 0 2006.173.14:21:24.93#ibcon#about to read 3, iclass 4, count 0 2006.173.14:21:24.97#ibcon#read 3, iclass 4, count 0 2006.173.14:21:24.97#ibcon#about to read 4, iclass 4, count 0 2006.173.14:21:24.97#ibcon#read 4, iclass 4, count 0 2006.173.14:21:24.97#ibcon#about to read 5, iclass 4, count 0 2006.173.14:21:24.97#ibcon#read 5, iclass 4, count 0 2006.173.14:21:24.97#ibcon#about to read 6, iclass 4, count 0 2006.173.14:21:24.97#ibcon#read 6, iclass 4, count 0 2006.173.14:21:24.97#ibcon#end of sib2, iclass 4, count 0 2006.173.14:21:24.97#ibcon#*after write, iclass 4, count 0 2006.173.14:21:24.97#ibcon#*before return 0, iclass 4, count 0 2006.173.14:21:24.97#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.14:21:24.97#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.14:21:24.97#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.14:21:24.97#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.14:21:24.97$vck44/vb=7,4 2006.173.14:21:24.97#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.14:21:24.97#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.14:21:24.97#ibcon#ireg 11 cls_cnt 2 2006.173.14:21:24.97#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.14:21:25.03#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.14:21:25.03#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.14:21:25.03#ibcon#enter wrdev, iclass 6, count 2 2006.173.14:21:25.03#ibcon#first serial, iclass 6, count 2 2006.173.14:21:25.03#ibcon#enter sib2, iclass 6, count 2 2006.173.14:21:25.03#ibcon#flushed, iclass 6, count 2 2006.173.14:21:25.03#ibcon#about to write, iclass 6, count 2 2006.173.14:21:25.03#ibcon#wrote, iclass 6, count 2 2006.173.14:21:25.03#ibcon#about to read 3, iclass 6, count 2 2006.173.14:21:25.05#ibcon#read 3, iclass 6, count 2 2006.173.14:21:25.05#ibcon#about to read 4, iclass 6, count 2 2006.173.14:21:25.05#ibcon#read 4, iclass 6, count 2 2006.173.14:21:25.05#ibcon#about to read 5, iclass 6, count 2 2006.173.14:21:25.05#ibcon#read 5, iclass 6, count 2 2006.173.14:21:25.05#ibcon#about to read 6, iclass 6, count 2 2006.173.14:21:25.05#ibcon#read 6, iclass 6, count 2 2006.173.14:21:25.05#ibcon#end of sib2, iclass 6, count 2 2006.173.14:21:25.05#ibcon#*mode == 0, iclass 6, count 2 2006.173.14:21:25.05#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.14:21:25.05#ibcon#[27=AT07-04\r\n] 2006.173.14:21:25.05#ibcon#*before write, iclass 6, count 2 2006.173.14:21:25.05#ibcon#enter sib2, iclass 6, count 2 2006.173.14:21:25.05#ibcon#flushed, iclass 6, count 2 2006.173.14:21:25.05#ibcon#about to write, iclass 6, count 2 2006.173.14:21:25.05#ibcon#wrote, iclass 6, count 2 2006.173.14:21:25.05#ibcon#about to read 3, iclass 6, count 2 2006.173.14:21:25.08#ibcon#read 3, iclass 6, count 2 2006.173.14:21:25.08#ibcon#about to read 4, iclass 6, count 2 2006.173.14:21:25.08#ibcon#read 4, iclass 6, count 2 2006.173.14:21:25.08#ibcon#about to read 5, iclass 6, count 2 2006.173.14:21:25.08#ibcon#read 5, iclass 6, count 2 2006.173.14:21:25.08#ibcon#about to read 6, iclass 6, count 2 2006.173.14:21:25.08#ibcon#read 6, iclass 6, count 2 2006.173.14:21:25.08#ibcon#end of sib2, iclass 6, count 2 2006.173.14:21:25.08#ibcon#*after write, iclass 6, count 2 2006.173.14:21:25.08#ibcon#*before return 0, iclass 6, count 2 2006.173.14:21:25.08#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.14:21:25.08#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.14:21:25.08#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.14:21:25.08#ibcon#ireg 7 cls_cnt 0 2006.173.14:21:25.08#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.14:21:25.20#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.14:21:25.20#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.14:21:25.20#ibcon#enter wrdev, iclass 6, count 0 2006.173.14:21:25.20#ibcon#first serial, iclass 6, count 0 2006.173.14:21:25.20#ibcon#enter sib2, iclass 6, count 0 2006.173.14:21:25.20#ibcon#flushed, iclass 6, count 0 2006.173.14:21:25.20#ibcon#about to write, iclass 6, count 0 2006.173.14:21:25.20#ibcon#wrote, iclass 6, count 0 2006.173.14:21:25.20#ibcon#about to read 3, iclass 6, count 0 2006.173.14:21:25.22#ibcon#read 3, iclass 6, count 0 2006.173.14:21:25.22#ibcon#about to read 4, iclass 6, count 0 2006.173.14:21:25.22#ibcon#read 4, iclass 6, count 0 2006.173.14:21:25.22#ibcon#about to read 5, iclass 6, count 0 2006.173.14:21:25.22#ibcon#read 5, iclass 6, count 0 2006.173.14:21:25.22#ibcon#about to read 6, iclass 6, count 0 2006.173.14:21:25.22#ibcon#read 6, iclass 6, count 0 2006.173.14:21:25.22#ibcon#end of sib2, iclass 6, count 0 2006.173.14:21:25.22#ibcon#*mode == 0, iclass 6, count 0 2006.173.14:21:25.22#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.14:21:25.22#ibcon#[27=USB\r\n] 2006.173.14:21:25.22#ibcon#*before write, iclass 6, count 0 2006.173.14:21:25.22#ibcon#enter sib2, iclass 6, count 0 2006.173.14:21:25.22#ibcon#flushed, iclass 6, count 0 2006.173.14:21:25.22#ibcon#about to write, iclass 6, count 0 2006.173.14:21:25.22#ibcon#wrote, iclass 6, count 0 2006.173.14:21:25.22#ibcon#about to read 3, iclass 6, count 0 2006.173.14:21:25.25#ibcon#read 3, iclass 6, count 0 2006.173.14:21:25.25#ibcon#about to read 4, iclass 6, count 0 2006.173.14:21:25.25#ibcon#read 4, iclass 6, count 0 2006.173.14:21:25.25#ibcon#about to read 5, iclass 6, count 0 2006.173.14:21:25.25#ibcon#read 5, iclass 6, count 0 2006.173.14:21:25.25#ibcon#about to read 6, iclass 6, count 0 2006.173.14:21:25.25#ibcon#read 6, iclass 6, count 0 2006.173.14:21:25.25#ibcon#end of sib2, iclass 6, count 0 2006.173.14:21:25.25#ibcon#*after write, iclass 6, count 0 2006.173.14:21:25.25#ibcon#*before return 0, iclass 6, count 0 2006.173.14:21:25.25#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.14:21:25.25#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.14:21:25.25#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.14:21:25.25#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.14:21:25.25$vck44/vblo=8,744.99 2006.173.14:21:25.25#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.14:21:25.25#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.14:21:25.25#ibcon#ireg 17 cls_cnt 0 2006.173.14:21:25.25#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.14:21:25.25#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.14:21:25.25#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.14:21:25.25#ibcon#enter wrdev, iclass 10, count 0 2006.173.14:21:25.25#ibcon#first serial, iclass 10, count 0 2006.173.14:21:25.25#ibcon#enter sib2, iclass 10, count 0 2006.173.14:21:25.25#ibcon#flushed, iclass 10, count 0 2006.173.14:21:25.25#ibcon#about to write, iclass 10, count 0 2006.173.14:21:25.25#ibcon#wrote, iclass 10, count 0 2006.173.14:21:25.25#ibcon#about to read 3, iclass 10, count 0 2006.173.14:21:25.27#ibcon#read 3, iclass 10, count 0 2006.173.14:21:25.27#ibcon#about to read 4, iclass 10, count 0 2006.173.14:21:25.27#ibcon#read 4, iclass 10, count 0 2006.173.14:21:25.27#ibcon#about to read 5, iclass 10, count 0 2006.173.14:21:25.27#ibcon#read 5, iclass 10, count 0 2006.173.14:21:25.27#ibcon#about to read 6, iclass 10, count 0 2006.173.14:21:25.27#ibcon#read 6, iclass 10, count 0 2006.173.14:21:25.27#ibcon#end of sib2, iclass 10, count 0 2006.173.14:21:25.27#ibcon#*mode == 0, iclass 10, count 0 2006.173.14:21:25.27#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.14:21:25.27#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.14:21:25.27#ibcon#*before write, iclass 10, count 0 2006.173.14:21:25.27#ibcon#enter sib2, iclass 10, count 0 2006.173.14:21:25.27#ibcon#flushed, iclass 10, count 0 2006.173.14:21:25.27#ibcon#about to write, iclass 10, count 0 2006.173.14:21:25.27#ibcon#wrote, iclass 10, count 0 2006.173.14:21:25.27#ibcon#about to read 3, iclass 10, count 0 2006.173.14:21:25.31#ibcon#read 3, iclass 10, count 0 2006.173.14:21:25.31#ibcon#about to read 4, iclass 10, count 0 2006.173.14:21:25.31#ibcon#read 4, iclass 10, count 0 2006.173.14:21:25.31#ibcon#about to read 5, iclass 10, count 0 2006.173.14:21:25.31#ibcon#read 5, iclass 10, count 0 2006.173.14:21:25.31#ibcon#about to read 6, iclass 10, count 0 2006.173.14:21:25.31#ibcon#read 6, iclass 10, count 0 2006.173.14:21:25.31#ibcon#end of sib2, iclass 10, count 0 2006.173.14:21:25.31#ibcon#*after write, iclass 10, count 0 2006.173.14:21:25.31#ibcon#*before return 0, iclass 10, count 0 2006.173.14:21:25.31#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.14:21:25.31#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.14:21:25.31#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.14:21:25.31#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.14:21:25.31$vck44/vb=8,4 2006.173.14:21:25.31#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.14:21:25.31#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.14:21:25.31#ibcon#ireg 11 cls_cnt 2 2006.173.14:21:25.31#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.14:21:25.37#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.14:21:25.37#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.14:21:25.37#ibcon#enter wrdev, iclass 12, count 2 2006.173.14:21:25.37#ibcon#first serial, iclass 12, count 2 2006.173.14:21:25.37#ibcon#enter sib2, iclass 12, count 2 2006.173.14:21:25.37#ibcon#flushed, iclass 12, count 2 2006.173.14:21:25.37#ibcon#about to write, iclass 12, count 2 2006.173.14:21:25.37#ibcon#wrote, iclass 12, count 2 2006.173.14:21:25.37#ibcon#about to read 3, iclass 12, count 2 2006.173.14:21:25.39#ibcon#read 3, iclass 12, count 2 2006.173.14:21:25.39#ibcon#about to read 4, iclass 12, count 2 2006.173.14:21:25.39#ibcon#read 4, iclass 12, count 2 2006.173.14:21:25.39#ibcon#about to read 5, iclass 12, count 2 2006.173.14:21:25.39#ibcon#read 5, iclass 12, count 2 2006.173.14:21:25.39#ibcon#about to read 6, iclass 12, count 2 2006.173.14:21:25.39#ibcon#read 6, iclass 12, count 2 2006.173.14:21:25.39#ibcon#end of sib2, iclass 12, count 2 2006.173.14:21:25.39#ibcon#*mode == 0, iclass 12, count 2 2006.173.14:21:25.39#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.14:21:25.39#ibcon#[27=AT08-04\r\n] 2006.173.14:21:25.39#ibcon#*before write, iclass 12, count 2 2006.173.14:21:25.39#ibcon#enter sib2, iclass 12, count 2 2006.173.14:21:25.39#ibcon#flushed, iclass 12, count 2 2006.173.14:21:25.39#ibcon#about to write, iclass 12, count 2 2006.173.14:21:25.39#ibcon#wrote, iclass 12, count 2 2006.173.14:21:25.39#ibcon#about to read 3, iclass 12, count 2 2006.173.14:21:25.42#ibcon#read 3, iclass 12, count 2 2006.173.14:21:25.42#ibcon#about to read 4, iclass 12, count 2 2006.173.14:21:25.42#ibcon#read 4, iclass 12, count 2 2006.173.14:21:25.42#ibcon#about to read 5, iclass 12, count 2 2006.173.14:21:25.42#ibcon#read 5, iclass 12, count 2 2006.173.14:21:25.42#ibcon#about to read 6, iclass 12, count 2 2006.173.14:21:25.42#ibcon#read 6, iclass 12, count 2 2006.173.14:21:25.42#ibcon#end of sib2, iclass 12, count 2 2006.173.14:21:25.42#ibcon#*after write, iclass 12, count 2 2006.173.14:21:25.42#ibcon#*before return 0, iclass 12, count 2 2006.173.14:21:25.42#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.14:21:25.42#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.14:21:25.42#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.14:21:25.42#ibcon#ireg 7 cls_cnt 0 2006.173.14:21:25.42#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.14:21:25.54#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.14:21:25.54#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.14:21:25.54#ibcon#enter wrdev, iclass 12, count 0 2006.173.14:21:25.54#ibcon#first serial, iclass 12, count 0 2006.173.14:21:25.54#ibcon#enter sib2, iclass 12, count 0 2006.173.14:21:25.54#ibcon#flushed, iclass 12, count 0 2006.173.14:21:25.54#ibcon#about to write, iclass 12, count 0 2006.173.14:21:25.54#ibcon#wrote, iclass 12, count 0 2006.173.14:21:25.54#ibcon#about to read 3, iclass 12, count 0 2006.173.14:21:25.56#ibcon#read 3, iclass 12, count 0 2006.173.14:21:25.56#ibcon#about to read 4, iclass 12, count 0 2006.173.14:21:25.56#ibcon#read 4, iclass 12, count 0 2006.173.14:21:25.56#ibcon#about to read 5, iclass 12, count 0 2006.173.14:21:25.56#ibcon#read 5, iclass 12, count 0 2006.173.14:21:25.56#ibcon#about to read 6, iclass 12, count 0 2006.173.14:21:25.56#ibcon#read 6, iclass 12, count 0 2006.173.14:21:25.56#ibcon#end of sib2, iclass 12, count 0 2006.173.14:21:25.56#ibcon#*mode == 0, iclass 12, count 0 2006.173.14:21:25.56#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.14:21:25.56#ibcon#[27=USB\r\n] 2006.173.14:21:25.56#ibcon#*before write, iclass 12, count 0 2006.173.14:21:25.56#ibcon#enter sib2, iclass 12, count 0 2006.173.14:21:25.56#ibcon#flushed, iclass 12, count 0 2006.173.14:21:25.56#ibcon#about to write, iclass 12, count 0 2006.173.14:21:25.56#ibcon#wrote, iclass 12, count 0 2006.173.14:21:25.56#ibcon#about to read 3, iclass 12, count 0 2006.173.14:21:25.59#ibcon#read 3, iclass 12, count 0 2006.173.14:21:25.59#ibcon#about to read 4, iclass 12, count 0 2006.173.14:21:25.59#ibcon#read 4, iclass 12, count 0 2006.173.14:21:25.59#ibcon#about to read 5, iclass 12, count 0 2006.173.14:21:25.59#ibcon#read 5, iclass 12, count 0 2006.173.14:21:25.59#ibcon#about to read 6, iclass 12, count 0 2006.173.14:21:25.59#ibcon#read 6, iclass 12, count 0 2006.173.14:21:25.59#ibcon#end of sib2, iclass 12, count 0 2006.173.14:21:25.59#ibcon#*after write, iclass 12, count 0 2006.173.14:21:25.59#ibcon#*before return 0, iclass 12, count 0 2006.173.14:21:25.59#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.14:21:25.59#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.14:21:25.59#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.14:21:25.59#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.14:21:25.59$vck44/vabw=wide 2006.173.14:21:25.59#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.14:21:25.59#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.14:21:25.59#ibcon#ireg 8 cls_cnt 0 2006.173.14:21:25.59#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.14:21:25.59#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.14:21:25.59#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.14:21:25.59#ibcon#enter wrdev, iclass 14, count 0 2006.173.14:21:25.59#ibcon#first serial, iclass 14, count 0 2006.173.14:21:25.59#ibcon#enter sib2, iclass 14, count 0 2006.173.14:21:25.59#ibcon#flushed, iclass 14, count 0 2006.173.14:21:25.59#ibcon#about to write, iclass 14, count 0 2006.173.14:21:25.59#ibcon#wrote, iclass 14, count 0 2006.173.14:21:25.59#ibcon#about to read 3, iclass 14, count 0 2006.173.14:21:25.61#ibcon#read 3, iclass 14, count 0 2006.173.14:21:25.61#ibcon#about to read 4, iclass 14, count 0 2006.173.14:21:25.61#ibcon#read 4, iclass 14, count 0 2006.173.14:21:25.61#ibcon#about to read 5, iclass 14, count 0 2006.173.14:21:25.61#ibcon#read 5, iclass 14, count 0 2006.173.14:21:25.61#ibcon#about to read 6, iclass 14, count 0 2006.173.14:21:25.61#ibcon#read 6, iclass 14, count 0 2006.173.14:21:25.61#ibcon#end of sib2, iclass 14, count 0 2006.173.14:21:25.61#ibcon#*mode == 0, iclass 14, count 0 2006.173.14:21:25.61#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.14:21:25.61#ibcon#[25=BW32\r\n] 2006.173.14:21:25.61#ibcon#*before write, iclass 14, count 0 2006.173.14:21:25.61#ibcon#enter sib2, iclass 14, count 0 2006.173.14:21:25.61#ibcon#flushed, iclass 14, count 0 2006.173.14:21:25.61#ibcon#about to write, iclass 14, count 0 2006.173.14:21:25.61#ibcon#wrote, iclass 14, count 0 2006.173.14:21:25.61#ibcon#about to read 3, iclass 14, count 0 2006.173.14:21:25.64#ibcon#read 3, iclass 14, count 0 2006.173.14:21:25.64#ibcon#about to read 4, iclass 14, count 0 2006.173.14:21:25.64#ibcon#read 4, iclass 14, count 0 2006.173.14:21:25.64#ibcon#about to read 5, iclass 14, count 0 2006.173.14:21:25.64#ibcon#read 5, iclass 14, count 0 2006.173.14:21:25.64#ibcon#about to read 6, iclass 14, count 0 2006.173.14:21:25.64#ibcon#read 6, iclass 14, count 0 2006.173.14:21:25.64#ibcon#end of sib2, iclass 14, count 0 2006.173.14:21:25.64#ibcon#*after write, iclass 14, count 0 2006.173.14:21:25.64#ibcon#*before return 0, iclass 14, count 0 2006.173.14:21:25.64#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.14:21:25.64#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.14:21:25.64#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.14:21:25.64#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.14:21:25.64$vck44/vbbw=wide 2006.173.14:21:25.64#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.14:21:25.64#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.14:21:25.64#ibcon#ireg 8 cls_cnt 0 2006.173.14:21:25.64#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.14:21:25.71#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.14:21:25.71#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.14:21:25.71#ibcon#enter wrdev, iclass 16, count 0 2006.173.14:21:25.71#ibcon#first serial, iclass 16, count 0 2006.173.14:21:25.71#ibcon#enter sib2, iclass 16, count 0 2006.173.14:21:25.71#ibcon#flushed, iclass 16, count 0 2006.173.14:21:25.71#ibcon#about to write, iclass 16, count 0 2006.173.14:21:25.71#ibcon#wrote, iclass 16, count 0 2006.173.14:21:25.71#ibcon#about to read 3, iclass 16, count 0 2006.173.14:21:25.73#ibcon#read 3, iclass 16, count 0 2006.173.14:21:25.73#ibcon#about to read 4, iclass 16, count 0 2006.173.14:21:25.73#ibcon#read 4, iclass 16, count 0 2006.173.14:21:25.73#ibcon#about to read 5, iclass 16, count 0 2006.173.14:21:25.73#ibcon#read 5, iclass 16, count 0 2006.173.14:21:25.73#ibcon#about to read 6, iclass 16, count 0 2006.173.14:21:25.73#ibcon#read 6, iclass 16, count 0 2006.173.14:21:25.73#ibcon#end of sib2, iclass 16, count 0 2006.173.14:21:25.73#ibcon#*mode == 0, iclass 16, count 0 2006.173.14:21:25.73#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.14:21:25.73#ibcon#[27=BW32\r\n] 2006.173.14:21:25.73#ibcon#*before write, iclass 16, count 0 2006.173.14:21:25.73#ibcon#enter sib2, iclass 16, count 0 2006.173.14:21:25.73#ibcon#flushed, iclass 16, count 0 2006.173.14:21:25.73#ibcon#about to write, iclass 16, count 0 2006.173.14:21:25.73#ibcon#wrote, iclass 16, count 0 2006.173.14:21:25.73#ibcon#about to read 3, iclass 16, count 0 2006.173.14:21:25.76#ibcon#read 3, iclass 16, count 0 2006.173.14:21:25.76#ibcon#about to read 4, iclass 16, count 0 2006.173.14:21:25.76#ibcon#read 4, iclass 16, count 0 2006.173.14:21:25.76#ibcon#about to read 5, iclass 16, count 0 2006.173.14:21:25.76#ibcon#read 5, iclass 16, count 0 2006.173.14:21:25.76#ibcon#about to read 6, iclass 16, count 0 2006.173.14:21:25.76#ibcon#read 6, iclass 16, count 0 2006.173.14:21:25.76#ibcon#end of sib2, iclass 16, count 0 2006.173.14:21:25.76#ibcon#*after write, iclass 16, count 0 2006.173.14:21:25.76#ibcon#*before return 0, iclass 16, count 0 2006.173.14:21:25.76#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.14:21:25.76#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.14:21:25.76#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.14:21:25.76#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.14:21:25.76$setupk4/ifdk4 2006.173.14:21:25.76$ifdk4/lo= 2006.173.14:21:25.76$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.14:21:25.76$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.14:21:25.76$ifdk4/patch= 2006.173.14:21:25.76$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.14:21:25.76$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.14:21:25.76$setupk4/!*+20s 2006.173.14:21:34.26#abcon#<5=/14 1.2 2.4 21.551001004.0\r\n> 2006.173.14:21:34.28#abcon#{5=INTERFACE CLEAR} 2006.173.14:21:34.34#abcon#[5=S1D000X0/0*\r\n] 2006.173.14:21:40.27$setupk4/"tpicd 2006.173.14:21:40.27$setupk4/echo=off 2006.173.14:21:40.27$setupk4/xlog=off 2006.173.14:21:40.27:!2006.173.14:27:03 2006.173.14:22:19.14#trakl#Source acquired 2006.173.14:22:19.14#flagr#flagr/antenna,acquired 2006.173.14:27:03.00:preob 2006.173.14:27:03.13/onsource/TRACKING 2006.173.14:27:03.13:!2006.173.14:27:13 2006.173.14:27:13.00:"tape 2006.173.14:27:13.00:"st=record 2006.173.14:27:13.00:data_valid=on 2006.173.14:27:13.00:midob 2006.173.14:27:13.13/onsource/TRACKING 2006.173.14:27:13.13/wx/21.53,1003.9,100 2006.173.14:27:13.32/cable/+6.5051E-03 2006.173.14:27:14.41/va/01,07,usb,yes,50,54 2006.173.14:27:14.41/va/02,06,usb,yes,50,51 2006.173.14:27:14.41/va/03,05,usb,yes,63,66 2006.173.14:27:14.41/va/04,06,usb,yes,52,54 2006.173.14:27:14.41/va/05,04,usb,yes,41,42 2006.173.14:27:14.41/va/06,03,usb,yes,57,57 2006.173.14:27:14.41/va/07,04,usb,yes,47,48 2006.173.14:27:14.41/va/08,04,usb,yes,40,48 2006.173.14:27:14.64/valo/01,524.99,yes,locked 2006.173.14:27:14.64/valo/02,534.99,yes,locked 2006.173.14:27:14.64/valo/03,564.99,yes,locked 2006.173.14:27:14.64/valo/04,624.99,yes,locked 2006.173.14:27:14.64/valo/05,734.99,yes,locked 2006.173.14:27:14.64/valo/06,814.99,yes,locked 2006.173.14:27:14.64/valo/07,864.99,yes,locked 2006.173.14:27:14.64/valo/08,884.99,yes,locked 2006.173.14:27:15.73/vb/01,04,usb,yes,32,29 2006.173.14:27:15.73/vb/02,04,usb,yes,34,34 2006.173.14:27:15.73/vb/03,04,usb,yes,31,34 2006.173.14:27:15.73/vb/04,04,usb,yes,35,34 2006.173.14:27:15.73/vb/05,04,usb,yes,28,30 2006.173.14:27:15.73/vb/06,04,usb,yes,33,29 2006.173.14:27:15.73/vb/07,04,usb,yes,32,32 2006.173.14:27:15.73/vb/08,04,usb,yes,30,33 2006.173.14:27:15.96/vblo/01,629.99,yes,locked 2006.173.14:27:15.96/vblo/02,634.99,yes,locked 2006.173.14:27:15.96/vblo/03,649.99,yes,locked 2006.173.14:27:15.96/vblo/04,679.99,yes,locked 2006.173.14:27:15.96/vblo/05,709.99,yes,locked 2006.173.14:27:15.96/vblo/06,719.99,yes,locked 2006.173.14:27:15.96/vblo/07,734.99,yes,locked 2006.173.14:27:15.96/vblo/08,744.99,yes,locked 2006.173.14:27:16.11/vabw/8 2006.173.14:27:16.26/vbbw/8 2006.173.14:27:16.35/xfe/off,on,14.7 2006.173.14:27:16.73/ifatt/23,28,28,28 2006.173.14:27:17.07/fmout-gps/S +3.92E-07 2006.173.14:27:17.11:!2006.173.14:31:13 2006.173.14:31:13.01:data_valid=off 2006.173.14:31:13.01:"et 2006.173.14:31:13.02:!+3s 2006.173.14:31:16.03:"tape 2006.173.14:31:16.03:postob 2006.173.14:31:16.17/cable/+6.5052E-03 2006.173.14:31:16.17/wx/21.44,1003.8,100 2006.173.14:31:16.23/fmout-gps/S +3.90E-07 2006.173.14:31:16.23:scan_name=173-1433,jd0606,70 2006.173.14:31:16.24:source=1908-201,191109.65,-200655.1,2000.0,cw 2006.173.14:31:17.14#flagr#flagr/antenna,new-source 2006.173.14:31:17.14:checkk5 2006.173.14:31:17.56/chk_autoobs//k5ts1/ autoobs is running! 2006.173.14:31:17.97/chk_autoobs//k5ts2/ autoobs is running! 2006.173.14:31:18.37/chk_autoobs//k5ts3/ autoobs is running! 2006.173.14:31:18.78/chk_autoobs//k5ts4/ autoobs is running! 2006.173.14:31:19.17/chk_obsdata//k5ts1/T1731427??a.dat file size is correct (nominal:960MB, actual:956MB). 2006.173.14:31:19.58/chk_obsdata//k5ts2/T1731427??b.dat file size is correct (nominal:960MB, actual:956MB). 2006.173.14:31:19.98/chk_obsdata//k5ts3/T1731427??c.dat file size is correct (nominal:960MB, actual:956MB). 2006.173.14:31:20.40/chk_obsdata//k5ts4/T1731427??d.dat file size is correct (nominal:960MB, actual:956MB). 2006.173.14:31:21.14/k5log//k5ts1_log_newline 2006.173.14:31:21.85/k5log//k5ts2_log_newline 2006.173.14:31:22.58/k5log//k5ts3_log_newline 2006.173.14:31:23.29/k5log//k5ts4_log_newline 2006.173.14:31:23.31/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.14:31:23.31:setupk4=1 2006.173.14:31:23.31$setupk4/echo=on 2006.173.14:31:23.31$setupk4/pcalon 2006.173.14:31:23.31$pcalon/"no phase cal control is implemented here 2006.173.14:31:23.31$setupk4/"tpicd=stop 2006.173.14:31:23.31$setupk4/"rec=synch_on 2006.173.14:31:23.31$setupk4/"rec_mode=128 2006.173.14:31:23.31$setupk4/!* 2006.173.14:31:23.31$setupk4/recpk4 2006.173.14:31:23.31$recpk4/recpatch= 2006.173.14:31:23.31$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.14:31:23.31$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.14:31:23.31$setupk4/vck44 2006.173.14:31:23.31$vck44/valo=1,524.99 2006.173.14:31:23.32#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.14:31:23.32#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.14:31:23.32#ibcon#ireg 17 cls_cnt 0 2006.173.14:31:23.32#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.14:31:23.32#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.14:31:23.32#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.14:31:23.32#ibcon#enter wrdev, iclass 37, count 0 2006.173.14:31:23.32#ibcon#first serial, iclass 37, count 0 2006.173.14:31:23.32#ibcon#enter sib2, iclass 37, count 0 2006.173.14:31:23.32#ibcon#flushed, iclass 37, count 0 2006.173.14:31:23.32#ibcon#about to write, iclass 37, count 0 2006.173.14:31:23.32#ibcon#wrote, iclass 37, count 0 2006.173.14:31:23.32#ibcon#about to read 3, iclass 37, count 0 2006.173.14:31:23.33#ibcon#read 3, iclass 37, count 0 2006.173.14:31:23.33#ibcon#about to read 4, iclass 37, count 0 2006.173.14:31:23.33#ibcon#read 4, iclass 37, count 0 2006.173.14:31:23.33#ibcon#about to read 5, iclass 37, count 0 2006.173.14:31:23.33#ibcon#read 5, iclass 37, count 0 2006.173.14:31:23.33#ibcon#about to read 6, iclass 37, count 0 2006.173.14:31:23.33#ibcon#read 6, iclass 37, count 0 2006.173.14:31:23.33#ibcon#end of sib2, iclass 37, count 0 2006.173.14:31:23.33#ibcon#*mode == 0, iclass 37, count 0 2006.173.14:31:23.33#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.14:31:23.33#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.14:31:23.33#ibcon#*before write, iclass 37, count 0 2006.173.14:31:23.33#ibcon#enter sib2, iclass 37, count 0 2006.173.14:31:23.33#ibcon#flushed, iclass 37, count 0 2006.173.14:31:23.33#ibcon#about to write, iclass 37, count 0 2006.173.14:31:23.33#ibcon#wrote, iclass 37, count 0 2006.173.14:31:23.33#ibcon#about to read 3, iclass 37, count 0 2006.173.14:31:23.38#ibcon#read 3, iclass 37, count 0 2006.173.14:31:23.38#ibcon#about to read 4, iclass 37, count 0 2006.173.14:31:23.38#ibcon#read 4, iclass 37, count 0 2006.173.14:31:23.38#ibcon#about to read 5, iclass 37, count 0 2006.173.14:31:23.38#ibcon#read 5, iclass 37, count 0 2006.173.14:31:23.38#ibcon#about to read 6, iclass 37, count 0 2006.173.14:31:23.38#ibcon#read 6, iclass 37, count 0 2006.173.14:31:23.38#ibcon#end of sib2, iclass 37, count 0 2006.173.14:31:23.38#ibcon#*after write, iclass 37, count 0 2006.173.14:31:23.38#ibcon#*before return 0, iclass 37, count 0 2006.173.14:31:23.38#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.14:31:23.38#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.14:31:23.38#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.14:31:23.38#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.14:31:23.38$vck44/va=1,7 2006.173.14:31:23.38#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.14:31:23.38#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.14:31:23.38#ibcon#ireg 11 cls_cnt 2 2006.173.14:31:23.38#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.14:31:23.38#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.14:31:23.38#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.14:31:23.38#ibcon#enter wrdev, iclass 39, count 2 2006.173.14:31:23.38#ibcon#first serial, iclass 39, count 2 2006.173.14:31:23.38#ibcon#enter sib2, iclass 39, count 2 2006.173.14:31:23.38#ibcon#flushed, iclass 39, count 2 2006.173.14:31:23.38#ibcon#about to write, iclass 39, count 2 2006.173.14:31:23.38#ibcon#wrote, iclass 39, count 2 2006.173.14:31:23.38#ibcon#about to read 3, iclass 39, count 2 2006.173.14:31:23.40#ibcon#read 3, iclass 39, count 2 2006.173.14:31:23.40#ibcon#about to read 4, iclass 39, count 2 2006.173.14:31:23.40#ibcon#read 4, iclass 39, count 2 2006.173.14:31:23.40#ibcon#about to read 5, iclass 39, count 2 2006.173.14:31:23.40#ibcon#read 5, iclass 39, count 2 2006.173.14:31:23.40#ibcon#about to read 6, iclass 39, count 2 2006.173.14:31:23.40#ibcon#read 6, iclass 39, count 2 2006.173.14:31:23.40#ibcon#end of sib2, iclass 39, count 2 2006.173.14:31:23.40#ibcon#*mode == 0, iclass 39, count 2 2006.173.14:31:23.40#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.14:31:23.40#ibcon#[25=AT01-07\r\n] 2006.173.14:31:23.40#ibcon#*before write, iclass 39, count 2 2006.173.14:31:23.40#ibcon#enter sib2, iclass 39, count 2 2006.173.14:31:23.40#ibcon#flushed, iclass 39, count 2 2006.173.14:31:23.40#ibcon#about to write, iclass 39, count 2 2006.173.14:31:23.40#ibcon#wrote, iclass 39, count 2 2006.173.14:31:23.40#ibcon#about to read 3, iclass 39, count 2 2006.173.14:31:23.43#ibcon#read 3, iclass 39, count 2 2006.173.14:31:23.43#ibcon#about to read 4, iclass 39, count 2 2006.173.14:31:23.43#ibcon#read 4, iclass 39, count 2 2006.173.14:31:23.43#ibcon#about to read 5, iclass 39, count 2 2006.173.14:31:23.43#ibcon#read 5, iclass 39, count 2 2006.173.14:31:23.43#ibcon#about to read 6, iclass 39, count 2 2006.173.14:31:23.43#ibcon#read 6, iclass 39, count 2 2006.173.14:31:23.43#ibcon#end of sib2, iclass 39, count 2 2006.173.14:31:23.43#ibcon#*after write, iclass 39, count 2 2006.173.14:31:23.43#ibcon#*before return 0, iclass 39, count 2 2006.173.14:31:23.43#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.14:31:23.43#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.14:31:23.43#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.14:31:23.43#ibcon#ireg 7 cls_cnt 0 2006.173.14:31:23.43#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.14:31:23.55#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.14:31:23.55#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.14:31:23.55#ibcon#enter wrdev, iclass 39, count 0 2006.173.14:31:23.55#ibcon#first serial, iclass 39, count 0 2006.173.14:31:23.55#ibcon#enter sib2, iclass 39, count 0 2006.173.14:31:23.55#ibcon#flushed, iclass 39, count 0 2006.173.14:31:23.55#ibcon#about to write, iclass 39, count 0 2006.173.14:31:23.55#ibcon#wrote, iclass 39, count 0 2006.173.14:31:23.55#ibcon#about to read 3, iclass 39, count 0 2006.173.14:31:23.57#ibcon#read 3, iclass 39, count 0 2006.173.14:31:23.57#ibcon#about to read 4, iclass 39, count 0 2006.173.14:31:23.57#ibcon#read 4, iclass 39, count 0 2006.173.14:31:23.57#ibcon#about to read 5, iclass 39, count 0 2006.173.14:31:23.57#ibcon#read 5, iclass 39, count 0 2006.173.14:31:23.57#ibcon#about to read 6, iclass 39, count 0 2006.173.14:31:23.57#ibcon#read 6, iclass 39, count 0 2006.173.14:31:23.57#ibcon#end of sib2, iclass 39, count 0 2006.173.14:31:23.57#ibcon#*mode == 0, iclass 39, count 0 2006.173.14:31:23.57#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.14:31:23.57#ibcon#[25=USB\r\n] 2006.173.14:31:23.57#ibcon#*before write, iclass 39, count 0 2006.173.14:31:23.57#ibcon#enter sib2, iclass 39, count 0 2006.173.14:31:23.57#ibcon#flushed, iclass 39, count 0 2006.173.14:31:23.57#ibcon#about to write, iclass 39, count 0 2006.173.14:31:23.57#ibcon#wrote, iclass 39, count 0 2006.173.14:31:23.57#ibcon#about to read 3, iclass 39, count 0 2006.173.14:31:23.60#ibcon#read 3, iclass 39, count 0 2006.173.14:31:23.60#ibcon#about to read 4, iclass 39, count 0 2006.173.14:31:23.60#ibcon#read 4, iclass 39, count 0 2006.173.14:31:23.60#ibcon#about to read 5, iclass 39, count 0 2006.173.14:31:23.60#ibcon#read 5, iclass 39, count 0 2006.173.14:31:23.60#ibcon#about to read 6, iclass 39, count 0 2006.173.14:31:23.60#ibcon#read 6, iclass 39, count 0 2006.173.14:31:23.60#ibcon#end of sib2, iclass 39, count 0 2006.173.14:31:23.60#ibcon#*after write, iclass 39, count 0 2006.173.14:31:23.60#ibcon#*before return 0, iclass 39, count 0 2006.173.14:31:23.60#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.14:31:23.60#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.14:31:23.60#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.14:31:23.60#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.14:31:23.60$vck44/valo=2,534.99 2006.173.14:31:23.60#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.14:31:23.60#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.14:31:23.60#ibcon#ireg 17 cls_cnt 0 2006.173.14:31:23.60#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.14:31:23.60#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.14:31:23.60#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.14:31:23.60#ibcon#enter wrdev, iclass 3, count 0 2006.173.14:31:23.60#ibcon#first serial, iclass 3, count 0 2006.173.14:31:23.60#ibcon#enter sib2, iclass 3, count 0 2006.173.14:31:23.60#ibcon#flushed, iclass 3, count 0 2006.173.14:31:23.60#ibcon#about to write, iclass 3, count 0 2006.173.14:31:23.60#ibcon#wrote, iclass 3, count 0 2006.173.14:31:23.60#ibcon#about to read 3, iclass 3, count 0 2006.173.14:31:23.62#ibcon#read 3, iclass 3, count 0 2006.173.14:31:23.62#ibcon#about to read 4, iclass 3, count 0 2006.173.14:31:23.62#ibcon#read 4, iclass 3, count 0 2006.173.14:31:23.62#ibcon#about to read 5, iclass 3, count 0 2006.173.14:31:23.62#ibcon#read 5, iclass 3, count 0 2006.173.14:31:23.62#ibcon#about to read 6, iclass 3, count 0 2006.173.14:31:23.62#ibcon#read 6, iclass 3, count 0 2006.173.14:31:23.62#ibcon#end of sib2, iclass 3, count 0 2006.173.14:31:23.62#ibcon#*mode == 0, iclass 3, count 0 2006.173.14:31:23.62#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.14:31:23.62#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.14:31:23.62#ibcon#*before write, iclass 3, count 0 2006.173.14:31:23.62#ibcon#enter sib2, iclass 3, count 0 2006.173.14:31:23.62#ibcon#flushed, iclass 3, count 0 2006.173.14:31:23.62#ibcon#about to write, iclass 3, count 0 2006.173.14:31:23.62#ibcon#wrote, iclass 3, count 0 2006.173.14:31:23.62#ibcon#about to read 3, iclass 3, count 0 2006.173.14:31:23.66#ibcon#read 3, iclass 3, count 0 2006.173.14:31:23.66#ibcon#about to read 4, iclass 3, count 0 2006.173.14:31:23.66#ibcon#read 4, iclass 3, count 0 2006.173.14:31:23.66#ibcon#about to read 5, iclass 3, count 0 2006.173.14:31:23.66#ibcon#read 5, iclass 3, count 0 2006.173.14:31:23.66#ibcon#about to read 6, iclass 3, count 0 2006.173.14:31:23.66#ibcon#read 6, iclass 3, count 0 2006.173.14:31:23.66#ibcon#end of sib2, iclass 3, count 0 2006.173.14:31:23.66#ibcon#*after write, iclass 3, count 0 2006.173.14:31:23.66#ibcon#*before return 0, iclass 3, count 0 2006.173.14:31:23.66#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.14:31:23.66#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.14:31:23.66#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.14:31:23.66#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.14:31:23.66$vck44/va=2,6 2006.173.14:31:23.66#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.14:31:23.66#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.14:31:23.66#ibcon#ireg 11 cls_cnt 2 2006.173.14:31:23.66#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.14:31:23.72#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.14:31:23.72#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.14:31:23.72#ibcon#enter wrdev, iclass 5, count 2 2006.173.14:31:23.72#ibcon#first serial, iclass 5, count 2 2006.173.14:31:23.72#ibcon#enter sib2, iclass 5, count 2 2006.173.14:31:23.72#ibcon#flushed, iclass 5, count 2 2006.173.14:31:23.72#ibcon#about to write, iclass 5, count 2 2006.173.14:31:23.72#ibcon#wrote, iclass 5, count 2 2006.173.14:31:23.72#ibcon#about to read 3, iclass 5, count 2 2006.173.14:31:23.74#ibcon#read 3, iclass 5, count 2 2006.173.14:31:23.74#ibcon#about to read 4, iclass 5, count 2 2006.173.14:31:23.74#ibcon#read 4, iclass 5, count 2 2006.173.14:31:23.74#ibcon#about to read 5, iclass 5, count 2 2006.173.14:31:23.74#ibcon#read 5, iclass 5, count 2 2006.173.14:31:23.74#ibcon#about to read 6, iclass 5, count 2 2006.173.14:31:23.74#ibcon#read 6, iclass 5, count 2 2006.173.14:31:23.74#ibcon#end of sib2, iclass 5, count 2 2006.173.14:31:23.74#ibcon#*mode == 0, iclass 5, count 2 2006.173.14:31:23.74#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.14:31:23.74#ibcon#[25=AT02-06\r\n] 2006.173.14:31:23.74#ibcon#*before write, iclass 5, count 2 2006.173.14:31:23.74#ibcon#enter sib2, iclass 5, count 2 2006.173.14:31:23.74#ibcon#flushed, iclass 5, count 2 2006.173.14:31:23.74#ibcon#about to write, iclass 5, count 2 2006.173.14:31:23.74#ibcon#wrote, iclass 5, count 2 2006.173.14:31:23.74#ibcon#about to read 3, iclass 5, count 2 2006.173.14:31:23.77#ibcon#read 3, iclass 5, count 2 2006.173.14:31:23.77#ibcon#about to read 4, iclass 5, count 2 2006.173.14:31:23.77#ibcon#read 4, iclass 5, count 2 2006.173.14:31:23.77#ibcon#about to read 5, iclass 5, count 2 2006.173.14:31:23.77#ibcon#read 5, iclass 5, count 2 2006.173.14:31:23.77#ibcon#about to read 6, iclass 5, count 2 2006.173.14:31:23.77#ibcon#read 6, iclass 5, count 2 2006.173.14:31:23.77#ibcon#end of sib2, iclass 5, count 2 2006.173.14:31:23.77#ibcon#*after write, iclass 5, count 2 2006.173.14:31:23.77#ibcon#*before return 0, iclass 5, count 2 2006.173.14:31:23.77#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.14:31:23.77#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.14:31:23.77#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.14:31:23.77#ibcon#ireg 7 cls_cnt 0 2006.173.14:31:23.77#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.14:31:23.89#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.14:31:23.89#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.14:31:23.89#ibcon#enter wrdev, iclass 5, count 0 2006.173.14:31:23.89#ibcon#first serial, iclass 5, count 0 2006.173.14:31:23.89#ibcon#enter sib2, iclass 5, count 0 2006.173.14:31:23.89#ibcon#flushed, iclass 5, count 0 2006.173.14:31:23.89#ibcon#about to write, iclass 5, count 0 2006.173.14:31:23.89#ibcon#wrote, iclass 5, count 0 2006.173.14:31:23.89#ibcon#about to read 3, iclass 5, count 0 2006.173.14:31:23.91#ibcon#read 3, iclass 5, count 0 2006.173.14:31:23.91#ibcon#about to read 4, iclass 5, count 0 2006.173.14:31:23.91#ibcon#read 4, iclass 5, count 0 2006.173.14:31:23.91#ibcon#about to read 5, iclass 5, count 0 2006.173.14:31:23.91#ibcon#read 5, iclass 5, count 0 2006.173.14:31:23.91#ibcon#about to read 6, iclass 5, count 0 2006.173.14:31:23.91#ibcon#read 6, iclass 5, count 0 2006.173.14:31:23.91#ibcon#end of sib2, iclass 5, count 0 2006.173.14:31:23.91#ibcon#*mode == 0, iclass 5, count 0 2006.173.14:31:23.91#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.14:31:23.91#ibcon#[25=USB\r\n] 2006.173.14:31:23.91#ibcon#*before write, iclass 5, count 0 2006.173.14:31:23.91#ibcon#enter sib2, iclass 5, count 0 2006.173.14:31:23.91#ibcon#flushed, iclass 5, count 0 2006.173.14:31:23.91#ibcon#about to write, iclass 5, count 0 2006.173.14:31:23.91#ibcon#wrote, iclass 5, count 0 2006.173.14:31:23.91#ibcon#about to read 3, iclass 5, count 0 2006.173.14:31:23.94#ibcon#read 3, iclass 5, count 0 2006.173.14:31:23.94#ibcon#about to read 4, iclass 5, count 0 2006.173.14:31:23.94#ibcon#read 4, iclass 5, count 0 2006.173.14:31:23.94#ibcon#about to read 5, iclass 5, count 0 2006.173.14:31:23.94#ibcon#read 5, iclass 5, count 0 2006.173.14:31:23.94#ibcon#about to read 6, iclass 5, count 0 2006.173.14:31:23.94#ibcon#read 6, iclass 5, count 0 2006.173.14:31:23.94#ibcon#end of sib2, iclass 5, count 0 2006.173.14:31:23.94#ibcon#*after write, iclass 5, count 0 2006.173.14:31:23.94#ibcon#*before return 0, iclass 5, count 0 2006.173.14:31:23.94#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.14:31:23.94#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.14:31:23.94#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.14:31:23.94#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.14:31:23.94$vck44/valo=3,564.99 2006.173.14:31:23.94#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.14:31:23.94#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.14:31:23.94#ibcon#ireg 17 cls_cnt 0 2006.173.14:31:23.94#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.14:31:23.94#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.14:31:23.94#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.14:31:23.94#ibcon#enter wrdev, iclass 7, count 0 2006.173.14:31:23.94#ibcon#first serial, iclass 7, count 0 2006.173.14:31:23.94#ibcon#enter sib2, iclass 7, count 0 2006.173.14:31:23.94#ibcon#flushed, iclass 7, count 0 2006.173.14:31:23.94#ibcon#about to write, iclass 7, count 0 2006.173.14:31:23.94#ibcon#wrote, iclass 7, count 0 2006.173.14:31:23.94#ibcon#about to read 3, iclass 7, count 0 2006.173.14:31:23.96#ibcon#read 3, iclass 7, count 0 2006.173.14:31:23.96#ibcon#about to read 4, iclass 7, count 0 2006.173.14:31:23.96#ibcon#read 4, iclass 7, count 0 2006.173.14:31:23.96#ibcon#about to read 5, iclass 7, count 0 2006.173.14:31:23.96#ibcon#read 5, iclass 7, count 0 2006.173.14:31:23.96#ibcon#about to read 6, iclass 7, count 0 2006.173.14:31:23.96#ibcon#read 6, iclass 7, count 0 2006.173.14:31:23.96#ibcon#end of sib2, iclass 7, count 0 2006.173.14:31:23.96#ibcon#*mode == 0, iclass 7, count 0 2006.173.14:31:23.96#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.14:31:23.96#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.14:31:23.96#ibcon#*before write, iclass 7, count 0 2006.173.14:31:23.96#ibcon#enter sib2, iclass 7, count 0 2006.173.14:31:23.96#ibcon#flushed, iclass 7, count 0 2006.173.14:31:23.96#ibcon#about to write, iclass 7, count 0 2006.173.14:31:23.96#ibcon#wrote, iclass 7, count 0 2006.173.14:31:23.96#ibcon#about to read 3, iclass 7, count 0 2006.173.14:31:24.00#ibcon#read 3, iclass 7, count 0 2006.173.14:31:24.00#ibcon#about to read 4, iclass 7, count 0 2006.173.14:31:24.00#ibcon#read 4, iclass 7, count 0 2006.173.14:31:24.00#ibcon#about to read 5, iclass 7, count 0 2006.173.14:31:24.00#ibcon#read 5, iclass 7, count 0 2006.173.14:31:24.00#ibcon#about to read 6, iclass 7, count 0 2006.173.14:31:24.00#ibcon#read 6, iclass 7, count 0 2006.173.14:31:24.00#ibcon#end of sib2, iclass 7, count 0 2006.173.14:31:24.00#ibcon#*after write, iclass 7, count 0 2006.173.14:31:24.00#ibcon#*before return 0, iclass 7, count 0 2006.173.14:31:24.00#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.14:31:24.00#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.14:31:24.00#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.14:31:24.00#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.14:31:24.00$vck44/va=3,5 2006.173.14:31:24.00#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.14:31:24.00#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.14:31:24.00#ibcon#ireg 11 cls_cnt 2 2006.173.14:31:24.00#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.14:31:24.06#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.14:31:24.06#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.14:31:24.06#ibcon#enter wrdev, iclass 11, count 2 2006.173.14:31:24.06#ibcon#first serial, iclass 11, count 2 2006.173.14:31:24.06#ibcon#enter sib2, iclass 11, count 2 2006.173.14:31:24.06#ibcon#flushed, iclass 11, count 2 2006.173.14:31:24.06#ibcon#about to write, iclass 11, count 2 2006.173.14:31:24.06#ibcon#wrote, iclass 11, count 2 2006.173.14:31:24.06#ibcon#about to read 3, iclass 11, count 2 2006.173.14:31:24.08#ibcon#read 3, iclass 11, count 2 2006.173.14:31:24.08#ibcon#about to read 4, iclass 11, count 2 2006.173.14:31:24.08#ibcon#read 4, iclass 11, count 2 2006.173.14:31:24.08#ibcon#about to read 5, iclass 11, count 2 2006.173.14:31:24.08#ibcon#read 5, iclass 11, count 2 2006.173.14:31:24.08#ibcon#about to read 6, iclass 11, count 2 2006.173.14:31:24.08#ibcon#read 6, iclass 11, count 2 2006.173.14:31:24.08#ibcon#end of sib2, iclass 11, count 2 2006.173.14:31:24.08#ibcon#*mode == 0, iclass 11, count 2 2006.173.14:31:24.08#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.14:31:24.08#ibcon#[25=AT03-05\r\n] 2006.173.14:31:24.08#ibcon#*before write, iclass 11, count 2 2006.173.14:31:24.08#ibcon#enter sib2, iclass 11, count 2 2006.173.14:31:24.08#ibcon#flushed, iclass 11, count 2 2006.173.14:31:24.08#ibcon#about to write, iclass 11, count 2 2006.173.14:31:24.08#ibcon#wrote, iclass 11, count 2 2006.173.14:31:24.08#ibcon#about to read 3, iclass 11, count 2 2006.173.14:31:24.11#ibcon#read 3, iclass 11, count 2 2006.173.14:31:24.11#ibcon#about to read 4, iclass 11, count 2 2006.173.14:31:24.11#ibcon#read 4, iclass 11, count 2 2006.173.14:31:24.11#ibcon#about to read 5, iclass 11, count 2 2006.173.14:31:24.11#ibcon#read 5, iclass 11, count 2 2006.173.14:31:24.11#ibcon#about to read 6, iclass 11, count 2 2006.173.14:31:24.11#ibcon#read 6, iclass 11, count 2 2006.173.14:31:24.11#ibcon#end of sib2, iclass 11, count 2 2006.173.14:31:24.11#ibcon#*after write, iclass 11, count 2 2006.173.14:31:24.11#ibcon#*before return 0, iclass 11, count 2 2006.173.14:31:24.11#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.14:31:24.11#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.14:31:24.11#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.14:31:24.11#ibcon#ireg 7 cls_cnt 0 2006.173.14:31:24.11#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.14:31:24.23#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.14:31:24.23#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.14:31:24.23#ibcon#enter wrdev, iclass 11, count 0 2006.173.14:31:24.23#ibcon#first serial, iclass 11, count 0 2006.173.14:31:24.23#ibcon#enter sib2, iclass 11, count 0 2006.173.14:31:24.23#ibcon#flushed, iclass 11, count 0 2006.173.14:31:24.23#ibcon#about to write, iclass 11, count 0 2006.173.14:31:24.23#ibcon#wrote, iclass 11, count 0 2006.173.14:31:24.23#ibcon#about to read 3, iclass 11, count 0 2006.173.14:31:24.25#ibcon#read 3, iclass 11, count 0 2006.173.14:31:24.25#ibcon#about to read 4, iclass 11, count 0 2006.173.14:31:24.25#ibcon#read 4, iclass 11, count 0 2006.173.14:31:24.25#ibcon#about to read 5, iclass 11, count 0 2006.173.14:31:24.25#ibcon#read 5, iclass 11, count 0 2006.173.14:31:24.25#ibcon#about to read 6, iclass 11, count 0 2006.173.14:31:24.25#ibcon#read 6, iclass 11, count 0 2006.173.14:31:24.25#ibcon#end of sib2, iclass 11, count 0 2006.173.14:31:24.25#ibcon#*mode == 0, iclass 11, count 0 2006.173.14:31:24.25#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.14:31:24.25#ibcon#[25=USB\r\n] 2006.173.14:31:24.25#ibcon#*before write, iclass 11, count 0 2006.173.14:31:24.25#ibcon#enter sib2, iclass 11, count 0 2006.173.14:31:24.25#ibcon#flushed, iclass 11, count 0 2006.173.14:31:24.25#ibcon#about to write, iclass 11, count 0 2006.173.14:31:24.25#ibcon#wrote, iclass 11, count 0 2006.173.14:31:24.25#ibcon#about to read 3, iclass 11, count 0 2006.173.14:31:24.25#abcon#<5=/14 1.6 2.9 21.441001003.7\r\n> 2006.173.14:31:24.27#abcon#{5=INTERFACE CLEAR} 2006.173.14:31:24.28#ibcon#read 3, iclass 11, count 0 2006.173.14:31:24.28#ibcon#about to read 4, iclass 11, count 0 2006.173.14:31:24.28#ibcon#read 4, iclass 11, count 0 2006.173.14:31:24.28#ibcon#about to read 5, iclass 11, count 0 2006.173.14:31:24.28#ibcon#read 5, iclass 11, count 0 2006.173.14:31:24.28#ibcon#about to read 6, iclass 11, count 0 2006.173.14:31:24.28#ibcon#read 6, iclass 11, count 0 2006.173.14:31:24.28#ibcon#end of sib2, iclass 11, count 0 2006.173.14:31:24.28#ibcon#*after write, iclass 11, count 0 2006.173.14:31:24.28#ibcon#*before return 0, iclass 11, count 0 2006.173.14:31:24.28#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.14:31:24.28#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.14:31:24.28#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.14:31:24.28#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.14:31:24.28$vck44/valo=4,624.99 2006.173.14:31:24.28#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.14:31:24.28#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.14:31:24.28#ibcon#ireg 17 cls_cnt 0 2006.173.14:31:24.28#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.14:31:24.28#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.14:31:24.28#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.14:31:24.28#ibcon#enter wrdev, iclass 16, count 0 2006.173.14:31:24.28#ibcon#first serial, iclass 16, count 0 2006.173.14:31:24.28#ibcon#enter sib2, iclass 16, count 0 2006.173.14:31:24.28#ibcon#flushed, iclass 16, count 0 2006.173.14:31:24.28#ibcon#about to write, iclass 16, count 0 2006.173.14:31:24.28#ibcon#wrote, iclass 16, count 0 2006.173.14:31:24.28#ibcon#about to read 3, iclass 16, count 0 2006.173.14:31:24.30#ibcon#read 3, iclass 16, count 0 2006.173.14:31:24.30#ibcon#about to read 4, iclass 16, count 0 2006.173.14:31:24.30#ibcon#read 4, iclass 16, count 0 2006.173.14:31:24.30#ibcon#about to read 5, iclass 16, count 0 2006.173.14:31:24.30#ibcon#read 5, iclass 16, count 0 2006.173.14:31:24.30#ibcon#about to read 6, iclass 16, count 0 2006.173.14:31:24.30#ibcon#read 6, iclass 16, count 0 2006.173.14:31:24.30#ibcon#end of sib2, iclass 16, count 0 2006.173.14:31:24.30#ibcon#*mode == 0, iclass 16, count 0 2006.173.14:31:24.30#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.14:31:24.30#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.14:31:24.30#ibcon#*before write, iclass 16, count 0 2006.173.14:31:24.30#ibcon#enter sib2, iclass 16, count 0 2006.173.14:31:24.30#ibcon#flushed, iclass 16, count 0 2006.173.14:31:24.30#ibcon#about to write, iclass 16, count 0 2006.173.14:31:24.30#ibcon#wrote, iclass 16, count 0 2006.173.14:31:24.30#ibcon#about to read 3, iclass 16, count 0 2006.173.14:31:24.33#abcon#[5=S1D000X0/0*\r\n] 2006.173.14:31:24.34#ibcon#read 3, iclass 16, count 0 2006.173.14:31:24.34#ibcon#about to read 4, iclass 16, count 0 2006.173.14:31:24.34#ibcon#read 4, iclass 16, count 0 2006.173.14:31:24.34#ibcon#about to read 5, iclass 16, count 0 2006.173.14:31:24.34#ibcon#read 5, iclass 16, count 0 2006.173.14:31:24.34#ibcon#about to read 6, iclass 16, count 0 2006.173.14:31:24.34#ibcon#read 6, iclass 16, count 0 2006.173.14:31:24.34#ibcon#end of sib2, iclass 16, count 0 2006.173.14:31:24.34#ibcon#*after write, iclass 16, count 0 2006.173.14:31:24.34#ibcon#*before return 0, iclass 16, count 0 2006.173.14:31:24.34#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.14:31:24.34#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.14:31:24.34#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.14:31:24.34#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.14:31:24.34$vck44/va=4,6 2006.173.14:31:24.34#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.14:31:24.34#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.14:31:24.34#ibcon#ireg 11 cls_cnt 2 2006.173.14:31:24.34#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.14:31:24.40#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.14:31:24.40#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.14:31:24.40#ibcon#enter wrdev, iclass 19, count 2 2006.173.14:31:24.40#ibcon#first serial, iclass 19, count 2 2006.173.14:31:24.40#ibcon#enter sib2, iclass 19, count 2 2006.173.14:31:24.40#ibcon#flushed, iclass 19, count 2 2006.173.14:31:24.40#ibcon#about to write, iclass 19, count 2 2006.173.14:31:24.40#ibcon#wrote, iclass 19, count 2 2006.173.14:31:24.40#ibcon#about to read 3, iclass 19, count 2 2006.173.14:31:24.42#ibcon#read 3, iclass 19, count 2 2006.173.14:31:24.42#ibcon#about to read 4, iclass 19, count 2 2006.173.14:31:24.42#ibcon#read 4, iclass 19, count 2 2006.173.14:31:24.42#ibcon#about to read 5, iclass 19, count 2 2006.173.14:31:24.42#ibcon#read 5, iclass 19, count 2 2006.173.14:31:24.42#ibcon#about to read 6, iclass 19, count 2 2006.173.14:31:24.42#ibcon#read 6, iclass 19, count 2 2006.173.14:31:24.42#ibcon#end of sib2, iclass 19, count 2 2006.173.14:31:24.42#ibcon#*mode == 0, iclass 19, count 2 2006.173.14:31:24.42#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.14:31:24.42#ibcon#[25=AT04-06\r\n] 2006.173.14:31:24.42#ibcon#*before write, iclass 19, count 2 2006.173.14:31:24.42#ibcon#enter sib2, iclass 19, count 2 2006.173.14:31:24.42#ibcon#flushed, iclass 19, count 2 2006.173.14:31:24.42#ibcon#about to write, iclass 19, count 2 2006.173.14:31:24.42#ibcon#wrote, iclass 19, count 2 2006.173.14:31:24.42#ibcon#about to read 3, iclass 19, count 2 2006.173.14:31:24.45#ibcon#read 3, iclass 19, count 2 2006.173.14:31:24.45#ibcon#about to read 4, iclass 19, count 2 2006.173.14:31:24.45#ibcon#read 4, iclass 19, count 2 2006.173.14:31:24.45#ibcon#about to read 5, iclass 19, count 2 2006.173.14:31:24.45#ibcon#read 5, iclass 19, count 2 2006.173.14:31:24.45#ibcon#about to read 6, iclass 19, count 2 2006.173.14:31:24.45#ibcon#read 6, iclass 19, count 2 2006.173.14:31:24.45#ibcon#end of sib2, iclass 19, count 2 2006.173.14:31:24.45#ibcon#*after write, iclass 19, count 2 2006.173.14:31:24.45#ibcon#*before return 0, iclass 19, count 2 2006.173.14:31:24.45#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.14:31:24.45#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.14:31:24.45#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.14:31:24.45#ibcon#ireg 7 cls_cnt 0 2006.173.14:31:24.45#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.14:31:24.57#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.14:31:24.57#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.14:31:24.57#ibcon#enter wrdev, iclass 19, count 0 2006.173.14:31:24.57#ibcon#first serial, iclass 19, count 0 2006.173.14:31:24.57#ibcon#enter sib2, iclass 19, count 0 2006.173.14:31:24.57#ibcon#flushed, iclass 19, count 0 2006.173.14:31:24.57#ibcon#about to write, iclass 19, count 0 2006.173.14:31:24.57#ibcon#wrote, iclass 19, count 0 2006.173.14:31:24.57#ibcon#about to read 3, iclass 19, count 0 2006.173.14:31:24.59#ibcon#read 3, iclass 19, count 0 2006.173.14:31:24.59#ibcon#about to read 4, iclass 19, count 0 2006.173.14:31:24.59#ibcon#read 4, iclass 19, count 0 2006.173.14:31:24.59#ibcon#about to read 5, iclass 19, count 0 2006.173.14:31:24.59#ibcon#read 5, iclass 19, count 0 2006.173.14:31:24.59#ibcon#about to read 6, iclass 19, count 0 2006.173.14:31:24.59#ibcon#read 6, iclass 19, count 0 2006.173.14:31:24.59#ibcon#end of sib2, iclass 19, count 0 2006.173.14:31:24.59#ibcon#*mode == 0, iclass 19, count 0 2006.173.14:31:24.59#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.14:31:24.59#ibcon#[25=USB\r\n] 2006.173.14:31:24.59#ibcon#*before write, iclass 19, count 0 2006.173.14:31:24.59#ibcon#enter sib2, iclass 19, count 0 2006.173.14:31:24.59#ibcon#flushed, iclass 19, count 0 2006.173.14:31:24.59#ibcon#about to write, iclass 19, count 0 2006.173.14:31:24.59#ibcon#wrote, iclass 19, count 0 2006.173.14:31:24.59#ibcon#about to read 3, iclass 19, count 0 2006.173.14:31:24.62#ibcon#read 3, iclass 19, count 0 2006.173.14:31:24.62#ibcon#about to read 4, iclass 19, count 0 2006.173.14:31:24.62#ibcon#read 4, iclass 19, count 0 2006.173.14:31:24.62#ibcon#about to read 5, iclass 19, count 0 2006.173.14:31:24.62#ibcon#read 5, iclass 19, count 0 2006.173.14:31:24.62#ibcon#about to read 6, iclass 19, count 0 2006.173.14:31:24.62#ibcon#read 6, iclass 19, count 0 2006.173.14:31:24.62#ibcon#end of sib2, iclass 19, count 0 2006.173.14:31:24.62#ibcon#*after write, iclass 19, count 0 2006.173.14:31:24.62#ibcon#*before return 0, iclass 19, count 0 2006.173.14:31:24.62#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.14:31:24.62#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.14:31:24.62#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.14:31:24.62#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.14:31:24.62$vck44/valo=5,734.99 2006.173.14:31:24.62#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.14:31:24.62#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.14:31:24.62#ibcon#ireg 17 cls_cnt 0 2006.173.14:31:24.62#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.14:31:24.62#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.14:31:24.62#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.14:31:24.62#ibcon#enter wrdev, iclass 21, count 0 2006.173.14:31:24.62#ibcon#first serial, iclass 21, count 0 2006.173.14:31:24.62#ibcon#enter sib2, iclass 21, count 0 2006.173.14:31:24.62#ibcon#flushed, iclass 21, count 0 2006.173.14:31:24.62#ibcon#about to write, iclass 21, count 0 2006.173.14:31:24.62#ibcon#wrote, iclass 21, count 0 2006.173.14:31:24.62#ibcon#about to read 3, iclass 21, count 0 2006.173.14:31:24.64#ibcon#read 3, iclass 21, count 0 2006.173.14:31:24.64#ibcon#about to read 4, iclass 21, count 0 2006.173.14:31:24.64#ibcon#read 4, iclass 21, count 0 2006.173.14:31:24.64#ibcon#about to read 5, iclass 21, count 0 2006.173.14:31:24.64#ibcon#read 5, iclass 21, count 0 2006.173.14:31:24.64#ibcon#about to read 6, iclass 21, count 0 2006.173.14:31:24.64#ibcon#read 6, iclass 21, count 0 2006.173.14:31:24.64#ibcon#end of sib2, iclass 21, count 0 2006.173.14:31:24.64#ibcon#*mode == 0, iclass 21, count 0 2006.173.14:31:24.64#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.14:31:24.64#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.14:31:24.64#ibcon#*before write, iclass 21, count 0 2006.173.14:31:24.64#ibcon#enter sib2, iclass 21, count 0 2006.173.14:31:24.64#ibcon#flushed, iclass 21, count 0 2006.173.14:31:24.64#ibcon#about to write, iclass 21, count 0 2006.173.14:31:24.64#ibcon#wrote, iclass 21, count 0 2006.173.14:31:24.64#ibcon#about to read 3, iclass 21, count 0 2006.173.14:31:24.68#ibcon#read 3, iclass 21, count 0 2006.173.14:31:24.68#ibcon#about to read 4, iclass 21, count 0 2006.173.14:31:24.68#ibcon#read 4, iclass 21, count 0 2006.173.14:31:24.68#ibcon#about to read 5, iclass 21, count 0 2006.173.14:31:24.68#ibcon#read 5, iclass 21, count 0 2006.173.14:31:24.68#ibcon#about to read 6, iclass 21, count 0 2006.173.14:31:24.68#ibcon#read 6, iclass 21, count 0 2006.173.14:31:24.68#ibcon#end of sib2, iclass 21, count 0 2006.173.14:31:24.68#ibcon#*after write, iclass 21, count 0 2006.173.14:31:24.68#ibcon#*before return 0, iclass 21, count 0 2006.173.14:31:24.68#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.14:31:24.68#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.14:31:24.68#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.14:31:24.68#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.14:31:24.68$vck44/va=5,4 2006.173.14:31:24.68#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.14:31:24.68#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.14:31:24.68#ibcon#ireg 11 cls_cnt 2 2006.173.14:31:24.68#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.14:31:24.74#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.14:31:24.74#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.14:31:24.74#ibcon#enter wrdev, iclass 23, count 2 2006.173.14:31:24.74#ibcon#first serial, iclass 23, count 2 2006.173.14:31:24.74#ibcon#enter sib2, iclass 23, count 2 2006.173.14:31:24.74#ibcon#flushed, iclass 23, count 2 2006.173.14:31:24.74#ibcon#about to write, iclass 23, count 2 2006.173.14:31:24.74#ibcon#wrote, iclass 23, count 2 2006.173.14:31:24.74#ibcon#about to read 3, iclass 23, count 2 2006.173.14:31:24.76#ibcon#read 3, iclass 23, count 2 2006.173.14:31:24.76#ibcon#about to read 4, iclass 23, count 2 2006.173.14:31:24.76#ibcon#read 4, iclass 23, count 2 2006.173.14:31:24.76#ibcon#about to read 5, iclass 23, count 2 2006.173.14:31:24.76#ibcon#read 5, iclass 23, count 2 2006.173.14:31:24.76#ibcon#about to read 6, iclass 23, count 2 2006.173.14:31:24.76#ibcon#read 6, iclass 23, count 2 2006.173.14:31:24.76#ibcon#end of sib2, iclass 23, count 2 2006.173.14:31:24.76#ibcon#*mode == 0, iclass 23, count 2 2006.173.14:31:24.76#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.14:31:24.76#ibcon#[25=AT05-04\r\n] 2006.173.14:31:24.76#ibcon#*before write, iclass 23, count 2 2006.173.14:31:24.76#ibcon#enter sib2, iclass 23, count 2 2006.173.14:31:24.76#ibcon#flushed, iclass 23, count 2 2006.173.14:31:24.76#ibcon#about to write, iclass 23, count 2 2006.173.14:31:24.76#ibcon#wrote, iclass 23, count 2 2006.173.14:31:24.76#ibcon#about to read 3, iclass 23, count 2 2006.173.14:31:24.79#ibcon#read 3, iclass 23, count 2 2006.173.14:31:24.79#ibcon#about to read 4, iclass 23, count 2 2006.173.14:31:24.79#ibcon#read 4, iclass 23, count 2 2006.173.14:31:24.79#ibcon#about to read 5, iclass 23, count 2 2006.173.14:31:24.79#ibcon#read 5, iclass 23, count 2 2006.173.14:31:24.79#ibcon#about to read 6, iclass 23, count 2 2006.173.14:31:24.79#ibcon#read 6, iclass 23, count 2 2006.173.14:31:24.79#ibcon#end of sib2, iclass 23, count 2 2006.173.14:31:24.79#ibcon#*after write, iclass 23, count 2 2006.173.14:31:24.79#ibcon#*before return 0, iclass 23, count 2 2006.173.14:31:24.79#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.14:31:24.79#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.14:31:24.79#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.14:31:24.79#ibcon#ireg 7 cls_cnt 0 2006.173.14:31:24.79#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.14:31:24.91#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.14:31:24.91#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.14:31:24.91#ibcon#enter wrdev, iclass 23, count 0 2006.173.14:31:24.91#ibcon#first serial, iclass 23, count 0 2006.173.14:31:24.91#ibcon#enter sib2, iclass 23, count 0 2006.173.14:31:24.91#ibcon#flushed, iclass 23, count 0 2006.173.14:31:24.91#ibcon#about to write, iclass 23, count 0 2006.173.14:31:24.91#ibcon#wrote, iclass 23, count 0 2006.173.14:31:24.91#ibcon#about to read 3, iclass 23, count 0 2006.173.14:31:24.93#ibcon#read 3, iclass 23, count 0 2006.173.14:31:24.93#ibcon#about to read 4, iclass 23, count 0 2006.173.14:31:24.93#ibcon#read 4, iclass 23, count 0 2006.173.14:31:24.93#ibcon#about to read 5, iclass 23, count 0 2006.173.14:31:24.93#ibcon#read 5, iclass 23, count 0 2006.173.14:31:24.93#ibcon#about to read 6, iclass 23, count 0 2006.173.14:31:24.93#ibcon#read 6, iclass 23, count 0 2006.173.14:31:24.93#ibcon#end of sib2, iclass 23, count 0 2006.173.14:31:24.93#ibcon#*mode == 0, iclass 23, count 0 2006.173.14:31:24.93#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.14:31:24.93#ibcon#[25=USB\r\n] 2006.173.14:31:24.93#ibcon#*before write, iclass 23, count 0 2006.173.14:31:24.93#ibcon#enter sib2, iclass 23, count 0 2006.173.14:31:24.93#ibcon#flushed, iclass 23, count 0 2006.173.14:31:24.93#ibcon#about to write, iclass 23, count 0 2006.173.14:31:24.93#ibcon#wrote, iclass 23, count 0 2006.173.14:31:24.93#ibcon#about to read 3, iclass 23, count 0 2006.173.14:31:24.96#ibcon#read 3, iclass 23, count 0 2006.173.14:31:24.96#ibcon#about to read 4, iclass 23, count 0 2006.173.14:31:24.96#ibcon#read 4, iclass 23, count 0 2006.173.14:31:24.96#ibcon#about to read 5, iclass 23, count 0 2006.173.14:31:24.96#ibcon#read 5, iclass 23, count 0 2006.173.14:31:24.96#ibcon#about to read 6, iclass 23, count 0 2006.173.14:31:24.96#ibcon#read 6, iclass 23, count 0 2006.173.14:31:24.96#ibcon#end of sib2, iclass 23, count 0 2006.173.14:31:24.96#ibcon#*after write, iclass 23, count 0 2006.173.14:31:24.96#ibcon#*before return 0, iclass 23, count 0 2006.173.14:31:24.96#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.14:31:24.96#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.14:31:24.96#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.14:31:24.96#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.14:31:24.96$vck44/valo=6,814.99 2006.173.14:31:24.96#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.14:31:24.96#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.14:31:24.96#ibcon#ireg 17 cls_cnt 0 2006.173.14:31:24.96#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.14:31:24.96#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.14:31:24.96#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.14:31:24.96#ibcon#enter wrdev, iclass 25, count 0 2006.173.14:31:24.96#ibcon#first serial, iclass 25, count 0 2006.173.14:31:24.96#ibcon#enter sib2, iclass 25, count 0 2006.173.14:31:24.96#ibcon#flushed, iclass 25, count 0 2006.173.14:31:24.96#ibcon#about to write, iclass 25, count 0 2006.173.14:31:24.96#ibcon#wrote, iclass 25, count 0 2006.173.14:31:24.96#ibcon#about to read 3, iclass 25, count 0 2006.173.14:31:24.98#ibcon#read 3, iclass 25, count 0 2006.173.14:31:24.98#ibcon#about to read 4, iclass 25, count 0 2006.173.14:31:24.98#ibcon#read 4, iclass 25, count 0 2006.173.14:31:24.98#ibcon#about to read 5, iclass 25, count 0 2006.173.14:31:24.98#ibcon#read 5, iclass 25, count 0 2006.173.14:31:24.98#ibcon#about to read 6, iclass 25, count 0 2006.173.14:31:24.98#ibcon#read 6, iclass 25, count 0 2006.173.14:31:24.98#ibcon#end of sib2, iclass 25, count 0 2006.173.14:31:24.98#ibcon#*mode == 0, iclass 25, count 0 2006.173.14:31:24.98#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.14:31:24.98#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.14:31:24.98#ibcon#*before write, iclass 25, count 0 2006.173.14:31:24.98#ibcon#enter sib2, iclass 25, count 0 2006.173.14:31:24.98#ibcon#flushed, iclass 25, count 0 2006.173.14:31:24.98#ibcon#about to write, iclass 25, count 0 2006.173.14:31:24.98#ibcon#wrote, iclass 25, count 0 2006.173.14:31:24.98#ibcon#about to read 3, iclass 25, count 0 2006.173.14:31:25.02#ibcon#read 3, iclass 25, count 0 2006.173.14:31:25.02#ibcon#about to read 4, iclass 25, count 0 2006.173.14:31:25.02#ibcon#read 4, iclass 25, count 0 2006.173.14:31:25.02#ibcon#about to read 5, iclass 25, count 0 2006.173.14:31:25.02#ibcon#read 5, iclass 25, count 0 2006.173.14:31:25.02#ibcon#about to read 6, iclass 25, count 0 2006.173.14:31:25.02#ibcon#read 6, iclass 25, count 0 2006.173.14:31:25.02#ibcon#end of sib2, iclass 25, count 0 2006.173.14:31:25.02#ibcon#*after write, iclass 25, count 0 2006.173.14:31:25.02#ibcon#*before return 0, iclass 25, count 0 2006.173.14:31:25.02#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.14:31:25.02#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.14:31:25.02#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.14:31:25.02#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.14:31:25.02$vck44/va=6,3 2006.173.14:31:25.02#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.14:31:25.02#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.14:31:25.02#ibcon#ireg 11 cls_cnt 2 2006.173.14:31:25.02#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.14:31:25.08#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.14:31:25.08#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.14:31:25.08#ibcon#enter wrdev, iclass 27, count 2 2006.173.14:31:25.08#ibcon#first serial, iclass 27, count 2 2006.173.14:31:25.08#ibcon#enter sib2, iclass 27, count 2 2006.173.14:31:25.08#ibcon#flushed, iclass 27, count 2 2006.173.14:31:25.08#ibcon#about to write, iclass 27, count 2 2006.173.14:31:25.08#ibcon#wrote, iclass 27, count 2 2006.173.14:31:25.08#ibcon#about to read 3, iclass 27, count 2 2006.173.14:31:25.10#ibcon#read 3, iclass 27, count 2 2006.173.14:31:25.10#ibcon#about to read 4, iclass 27, count 2 2006.173.14:31:25.10#ibcon#read 4, iclass 27, count 2 2006.173.14:31:25.10#ibcon#about to read 5, iclass 27, count 2 2006.173.14:31:25.10#ibcon#read 5, iclass 27, count 2 2006.173.14:31:25.10#ibcon#about to read 6, iclass 27, count 2 2006.173.14:31:25.10#ibcon#read 6, iclass 27, count 2 2006.173.14:31:25.10#ibcon#end of sib2, iclass 27, count 2 2006.173.14:31:25.10#ibcon#*mode == 0, iclass 27, count 2 2006.173.14:31:25.10#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.14:31:25.10#ibcon#[25=AT06-03\r\n] 2006.173.14:31:25.10#ibcon#*before write, iclass 27, count 2 2006.173.14:31:25.10#ibcon#enter sib2, iclass 27, count 2 2006.173.14:31:25.10#ibcon#flushed, iclass 27, count 2 2006.173.14:31:25.10#ibcon#about to write, iclass 27, count 2 2006.173.14:31:25.10#ibcon#wrote, iclass 27, count 2 2006.173.14:31:25.10#ibcon#about to read 3, iclass 27, count 2 2006.173.14:31:25.13#ibcon#read 3, iclass 27, count 2 2006.173.14:31:25.13#ibcon#about to read 4, iclass 27, count 2 2006.173.14:31:25.13#ibcon#read 4, iclass 27, count 2 2006.173.14:31:25.13#ibcon#about to read 5, iclass 27, count 2 2006.173.14:31:25.13#ibcon#read 5, iclass 27, count 2 2006.173.14:31:25.13#ibcon#about to read 6, iclass 27, count 2 2006.173.14:31:25.13#ibcon#read 6, iclass 27, count 2 2006.173.14:31:25.13#ibcon#end of sib2, iclass 27, count 2 2006.173.14:31:25.13#ibcon#*after write, iclass 27, count 2 2006.173.14:31:25.13#ibcon#*before return 0, iclass 27, count 2 2006.173.14:31:25.13#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.14:31:25.13#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.14:31:25.13#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.14:31:25.13#ibcon#ireg 7 cls_cnt 0 2006.173.14:31:25.13#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.14:31:25.25#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.14:31:25.25#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.14:31:25.25#ibcon#enter wrdev, iclass 27, count 0 2006.173.14:31:25.25#ibcon#first serial, iclass 27, count 0 2006.173.14:31:25.25#ibcon#enter sib2, iclass 27, count 0 2006.173.14:31:25.25#ibcon#flushed, iclass 27, count 0 2006.173.14:31:25.25#ibcon#about to write, iclass 27, count 0 2006.173.14:31:25.25#ibcon#wrote, iclass 27, count 0 2006.173.14:31:25.25#ibcon#about to read 3, iclass 27, count 0 2006.173.14:31:25.27#ibcon#read 3, iclass 27, count 0 2006.173.14:31:25.27#ibcon#about to read 4, iclass 27, count 0 2006.173.14:31:25.27#ibcon#read 4, iclass 27, count 0 2006.173.14:31:25.27#ibcon#about to read 5, iclass 27, count 0 2006.173.14:31:25.27#ibcon#read 5, iclass 27, count 0 2006.173.14:31:25.27#ibcon#about to read 6, iclass 27, count 0 2006.173.14:31:25.27#ibcon#read 6, iclass 27, count 0 2006.173.14:31:25.27#ibcon#end of sib2, iclass 27, count 0 2006.173.14:31:25.27#ibcon#*mode == 0, iclass 27, count 0 2006.173.14:31:25.27#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.14:31:25.27#ibcon#[25=USB\r\n] 2006.173.14:31:25.27#ibcon#*before write, iclass 27, count 0 2006.173.14:31:25.27#ibcon#enter sib2, iclass 27, count 0 2006.173.14:31:25.27#ibcon#flushed, iclass 27, count 0 2006.173.14:31:25.27#ibcon#about to write, iclass 27, count 0 2006.173.14:31:25.27#ibcon#wrote, iclass 27, count 0 2006.173.14:31:25.27#ibcon#about to read 3, iclass 27, count 0 2006.173.14:31:25.30#ibcon#read 3, iclass 27, count 0 2006.173.14:31:25.30#ibcon#about to read 4, iclass 27, count 0 2006.173.14:31:25.30#ibcon#read 4, iclass 27, count 0 2006.173.14:31:25.30#ibcon#about to read 5, iclass 27, count 0 2006.173.14:31:25.30#ibcon#read 5, iclass 27, count 0 2006.173.14:31:25.30#ibcon#about to read 6, iclass 27, count 0 2006.173.14:31:25.30#ibcon#read 6, iclass 27, count 0 2006.173.14:31:25.30#ibcon#end of sib2, iclass 27, count 0 2006.173.14:31:25.30#ibcon#*after write, iclass 27, count 0 2006.173.14:31:25.30#ibcon#*before return 0, iclass 27, count 0 2006.173.14:31:25.30#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.14:31:25.30#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.14:31:25.30#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.14:31:25.30#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.14:31:25.30$vck44/valo=7,864.99 2006.173.14:31:25.30#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.14:31:25.30#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.14:31:25.30#ibcon#ireg 17 cls_cnt 0 2006.173.14:31:25.30#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.14:31:25.30#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.14:31:25.30#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.14:31:25.30#ibcon#enter wrdev, iclass 29, count 0 2006.173.14:31:25.30#ibcon#first serial, iclass 29, count 0 2006.173.14:31:25.30#ibcon#enter sib2, iclass 29, count 0 2006.173.14:31:25.30#ibcon#flushed, iclass 29, count 0 2006.173.14:31:25.30#ibcon#about to write, iclass 29, count 0 2006.173.14:31:25.30#ibcon#wrote, iclass 29, count 0 2006.173.14:31:25.30#ibcon#about to read 3, iclass 29, count 0 2006.173.14:31:25.32#ibcon#read 3, iclass 29, count 0 2006.173.14:31:25.32#ibcon#about to read 4, iclass 29, count 0 2006.173.14:31:25.32#ibcon#read 4, iclass 29, count 0 2006.173.14:31:25.32#ibcon#about to read 5, iclass 29, count 0 2006.173.14:31:25.32#ibcon#read 5, iclass 29, count 0 2006.173.14:31:25.32#ibcon#about to read 6, iclass 29, count 0 2006.173.14:31:25.32#ibcon#read 6, iclass 29, count 0 2006.173.14:31:25.32#ibcon#end of sib2, iclass 29, count 0 2006.173.14:31:25.32#ibcon#*mode == 0, iclass 29, count 0 2006.173.14:31:25.32#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.14:31:25.32#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.14:31:25.32#ibcon#*before write, iclass 29, count 0 2006.173.14:31:25.32#ibcon#enter sib2, iclass 29, count 0 2006.173.14:31:25.32#ibcon#flushed, iclass 29, count 0 2006.173.14:31:25.32#ibcon#about to write, iclass 29, count 0 2006.173.14:31:25.32#ibcon#wrote, iclass 29, count 0 2006.173.14:31:25.32#ibcon#about to read 3, iclass 29, count 0 2006.173.14:31:25.36#ibcon#read 3, iclass 29, count 0 2006.173.14:31:25.36#ibcon#about to read 4, iclass 29, count 0 2006.173.14:31:25.36#ibcon#read 4, iclass 29, count 0 2006.173.14:31:25.36#ibcon#about to read 5, iclass 29, count 0 2006.173.14:31:25.36#ibcon#read 5, iclass 29, count 0 2006.173.14:31:25.36#ibcon#about to read 6, iclass 29, count 0 2006.173.14:31:25.36#ibcon#read 6, iclass 29, count 0 2006.173.14:31:25.36#ibcon#end of sib2, iclass 29, count 0 2006.173.14:31:25.36#ibcon#*after write, iclass 29, count 0 2006.173.14:31:25.36#ibcon#*before return 0, iclass 29, count 0 2006.173.14:31:25.36#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.14:31:25.36#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.14:31:25.36#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.14:31:25.36#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.14:31:25.36$vck44/va=7,4 2006.173.14:31:25.36#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.14:31:25.36#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.14:31:25.36#ibcon#ireg 11 cls_cnt 2 2006.173.14:31:25.36#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.14:31:25.42#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.14:31:25.42#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.14:31:25.42#ibcon#enter wrdev, iclass 31, count 2 2006.173.14:31:25.42#ibcon#first serial, iclass 31, count 2 2006.173.14:31:25.42#ibcon#enter sib2, iclass 31, count 2 2006.173.14:31:25.42#ibcon#flushed, iclass 31, count 2 2006.173.14:31:25.42#ibcon#about to write, iclass 31, count 2 2006.173.14:31:25.42#ibcon#wrote, iclass 31, count 2 2006.173.14:31:25.42#ibcon#about to read 3, iclass 31, count 2 2006.173.14:31:25.44#ibcon#read 3, iclass 31, count 2 2006.173.14:31:25.44#ibcon#about to read 4, iclass 31, count 2 2006.173.14:31:25.44#ibcon#read 4, iclass 31, count 2 2006.173.14:31:25.44#ibcon#about to read 5, iclass 31, count 2 2006.173.14:31:25.44#ibcon#read 5, iclass 31, count 2 2006.173.14:31:25.44#ibcon#about to read 6, iclass 31, count 2 2006.173.14:31:25.44#ibcon#read 6, iclass 31, count 2 2006.173.14:31:25.44#ibcon#end of sib2, iclass 31, count 2 2006.173.14:31:25.44#ibcon#*mode == 0, iclass 31, count 2 2006.173.14:31:25.44#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.14:31:25.44#ibcon#[25=AT07-04\r\n] 2006.173.14:31:25.44#ibcon#*before write, iclass 31, count 2 2006.173.14:31:25.44#ibcon#enter sib2, iclass 31, count 2 2006.173.14:31:25.44#ibcon#flushed, iclass 31, count 2 2006.173.14:31:25.44#ibcon#about to write, iclass 31, count 2 2006.173.14:31:25.44#ibcon#wrote, iclass 31, count 2 2006.173.14:31:25.44#ibcon#about to read 3, iclass 31, count 2 2006.173.14:31:25.47#ibcon#read 3, iclass 31, count 2 2006.173.14:31:25.47#ibcon#about to read 4, iclass 31, count 2 2006.173.14:31:25.47#ibcon#read 4, iclass 31, count 2 2006.173.14:31:25.47#ibcon#about to read 5, iclass 31, count 2 2006.173.14:31:25.47#ibcon#read 5, iclass 31, count 2 2006.173.14:31:25.47#ibcon#about to read 6, iclass 31, count 2 2006.173.14:31:25.47#ibcon#read 6, iclass 31, count 2 2006.173.14:31:25.47#ibcon#end of sib2, iclass 31, count 2 2006.173.14:31:25.47#ibcon#*after write, iclass 31, count 2 2006.173.14:31:25.47#ibcon#*before return 0, iclass 31, count 2 2006.173.14:31:25.47#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.14:31:25.47#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.14:31:25.47#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.14:31:25.47#ibcon#ireg 7 cls_cnt 0 2006.173.14:31:25.47#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.14:31:25.59#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.14:31:25.59#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.14:31:25.59#ibcon#enter wrdev, iclass 31, count 0 2006.173.14:31:25.59#ibcon#first serial, iclass 31, count 0 2006.173.14:31:25.59#ibcon#enter sib2, iclass 31, count 0 2006.173.14:31:25.59#ibcon#flushed, iclass 31, count 0 2006.173.14:31:25.59#ibcon#about to write, iclass 31, count 0 2006.173.14:31:25.59#ibcon#wrote, iclass 31, count 0 2006.173.14:31:25.59#ibcon#about to read 3, iclass 31, count 0 2006.173.14:31:25.61#ibcon#read 3, iclass 31, count 0 2006.173.14:31:25.61#ibcon#about to read 4, iclass 31, count 0 2006.173.14:31:25.61#ibcon#read 4, iclass 31, count 0 2006.173.14:31:25.61#ibcon#about to read 5, iclass 31, count 0 2006.173.14:31:25.61#ibcon#read 5, iclass 31, count 0 2006.173.14:31:25.61#ibcon#about to read 6, iclass 31, count 0 2006.173.14:31:25.61#ibcon#read 6, iclass 31, count 0 2006.173.14:31:25.61#ibcon#end of sib2, iclass 31, count 0 2006.173.14:31:25.61#ibcon#*mode == 0, iclass 31, count 0 2006.173.14:31:25.61#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.14:31:25.61#ibcon#[25=USB\r\n] 2006.173.14:31:25.61#ibcon#*before write, iclass 31, count 0 2006.173.14:31:25.61#ibcon#enter sib2, iclass 31, count 0 2006.173.14:31:25.61#ibcon#flushed, iclass 31, count 0 2006.173.14:31:25.61#ibcon#about to write, iclass 31, count 0 2006.173.14:31:25.61#ibcon#wrote, iclass 31, count 0 2006.173.14:31:25.61#ibcon#about to read 3, iclass 31, count 0 2006.173.14:31:25.64#ibcon#read 3, iclass 31, count 0 2006.173.14:31:25.64#ibcon#about to read 4, iclass 31, count 0 2006.173.14:31:25.64#ibcon#read 4, iclass 31, count 0 2006.173.14:31:25.64#ibcon#about to read 5, iclass 31, count 0 2006.173.14:31:25.64#ibcon#read 5, iclass 31, count 0 2006.173.14:31:25.64#ibcon#about to read 6, iclass 31, count 0 2006.173.14:31:25.64#ibcon#read 6, iclass 31, count 0 2006.173.14:31:25.64#ibcon#end of sib2, iclass 31, count 0 2006.173.14:31:25.64#ibcon#*after write, iclass 31, count 0 2006.173.14:31:25.64#ibcon#*before return 0, iclass 31, count 0 2006.173.14:31:25.64#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.14:31:25.64#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.14:31:25.64#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.14:31:25.64#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.14:31:25.64$vck44/valo=8,884.99 2006.173.14:31:25.64#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.14:31:25.64#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.14:31:25.64#ibcon#ireg 17 cls_cnt 0 2006.173.14:31:25.64#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.14:31:25.64#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.14:31:25.64#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.14:31:25.64#ibcon#enter wrdev, iclass 33, count 0 2006.173.14:31:25.64#ibcon#first serial, iclass 33, count 0 2006.173.14:31:25.64#ibcon#enter sib2, iclass 33, count 0 2006.173.14:31:25.64#ibcon#flushed, iclass 33, count 0 2006.173.14:31:25.64#ibcon#about to write, iclass 33, count 0 2006.173.14:31:25.64#ibcon#wrote, iclass 33, count 0 2006.173.14:31:25.64#ibcon#about to read 3, iclass 33, count 0 2006.173.14:31:25.66#ibcon#read 3, iclass 33, count 0 2006.173.14:31:25.66#ibcon#about to read 4, iclass 33, count 0 2006.173.14:31:25.66#ibcon#read 4, iclass 33, count 0 2006.173.14:31:25.66#ibcon#about to read 5, iclass 33, count 0 2006.173.14:31:25.66#ibcon#read 5, iclass 33, count 0 2006.173.14:31:25.66#ibcon#about to read 6, iclass 33, count 0 2006.173.14:31:25.66#ibcon#read 6, iclass 33, count 0 2006.173.14:31:25.66#ibcon#end of sib2, iclass 33, count 0 2006.173.14:31:25.66#ibcon#*mode == 0, iclass 33, count 0 2006.173.14:31:25.66#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.14:31:25.66#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.14:31:25.66#ibcon#*before write, iclass 33, count 0 2006.173.14:31:25.66#ibcon#enter sib2, iclass 33, count 0 2006.173.14:31:25.66#ibcon#flushed, iclass 33, count 0 2006.173.14:31:25.66#ibcon#about to write, iclass 33, count 0 2006.173.14:31:25.66#ibcon#wrote, iclass 33, count 0 2006.173.14:31:25.66#ibcon#about to read 3, iclass 33, count 0 2006.173.14:31:25.70#ibcon#read 3, iclass 33, count 0 2006.173.14:31:25.70#ibcon#about to read 4, iclass 33, count 0 2006.173.14:31:25.70#ibcon#read 4, iclass 33, count 0 2006.173.14:31:25.70#ibcon#about to read 5, iclass 33, count 0 2006.173.14:31:25.70#ibcon#read 5, iclass 33, count 0 2006.173.14:31:25.70#ibcon#about to read 6, iclass 33, count 0 2006.173.14:31:25.70#ibcon#read 6, iclass 33, count 0 2006.173.14:31:25.70#ibcon#end of sib2, iclass 33, count 0 2006.173.14:31:25.70#ibcon#*after write, iclass 33, count 0 2006.173.14:31:25.70#ibcon#*before return 0, iclass 33, count 0 2006.173.14:31:25.70#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.14:31:25.70#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.14:31:25.70#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.14:31:25.70#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.14:31:25.70$vck44/va=8,4 2006.173.14:31:25.70#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.14:31:25.70#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.14:31:25.70#ibcon#ireg 11 cls_cnt 2 2006.173.14:31:25.70#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.14:31:25.76#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.14:31:25.76#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.14:31:25.76#ibcon#enter wrdev, iclass 35, count 2 2006.173.14:31:25.76#ibcon#first serial, iclass 35, count 2 2006.173.14:31:25.76#ibcon#enter sib2, iclass 35, count 2 2006.173.14:31:25.76#ibcon#flushed, iclass 35, count 2 2006.173.14:31:25.76#ibcon#about to write, iclass 35, count 2 2006.173.14:31:25.76#ibcon#wrote, iclass 35, count 2 2006.173.14:31:25.76#ibcon#about to read 3, iclass 35, count 2 2006.173.14:31:25.78#ibcon#read 3, iclass 35, count 2 2006.173.14:31:25.78#ibcon#about to read 4, iclass 35, count 2 2006.173.14:31:25.78#ibcon#read 4, iclass 35, count 2 2006.173.14:31:25.78#ibcon#about to read 5, iclass 35, count 2 2006.173.14:31:25.78#ibcon#read 5, iclass 35, count 2 2006.173.14:31:25.78#ibcon#about to read 6, iclass 35, count 2 2006.173.14:31:25.78#ibcon#read 6, iclass 35, count 2 2006.173.14:31:25.78#ibcon#end of sib2, iclass 35, count 2 2006.173.14:31:25.78#ibcon#*mode == 0, iclass 35, count 2 2006.173.14:31:25.78#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.14:31:25.78#ibcon#[25=AT08-04\r\n] 2006.173.14:31:25.78#ibcon#*before write, iclass 35, count 2 2006.173.14:31:25.78#ibcon#enter sib2, iclass 35, count 2 2006.173.14:31:25.78#ibcon#flushed, iclass 35, count 2 2006.173.14:31:25.78#ibcon#about to write, iclass 35, count 2 2006.173.14:31:25.78#ibcon#wrote, iclass 35, count 2 2006.173.14:31:25.78#ibcon#about to read 3, iclass 35, count 2 2006.173.14:31:25.81#ibcon#read 3, iclass 35, count 2 2006.173.14:31:25.81#ibcon#about to read 4, iclass 35, count 2 2006.173.14:31:25.81#ibcon#read 4, iclass 35, count 2 2006.173.14:31:25.81#ibcon#about to read 5, iclass 35, count 2 2006.173.14:31:25.81#ibcon#read 5, iclass 35, count 2 2006.173.14:31:25.81#ibcon#about to read 6, iclass 35, count 2 2006.173.14:31:25.81#ibcon#read 6, iclass 35, count 2 2006.173.14:31:25.81#ibcon#end of sib2, iclass 35, count 2 2006.173.14:31:25.81#ibcon#*after write, iclass 35, count 2 2006.173.14:31:25.81#ibcon#*before return 0, iclass 35, count 2 2006.173.14:31:25.81#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.14:31:25.81#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.14:31:25.81#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.14:31:25.81#ibcon#ireg 7 cls_cnt 0 2006.173.14:31:25.81#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.14:31:25.93#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.14:31:25.93#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.14:31:25.93#ibcon#enter wrdev, iclass 35, count 0 2006.173.14:31:25.93#ibcon#first serial, iclass 35, count 0 2006.173.14:31:25.93#ibcon#enter sib2, iclass 35, count 0 2006.173.14:31:25.93#ibcon#flushed, iclass 35, count 0 2006.173.14:31:25.93#ibcon#about to write, iclass 35, count 0 2006.173.14:31:25.93#ibcon#wrote, iclass 35, count 0 2006.173.14:31:25.93#ibcon#about to read 3, iclass 35, count 0 2006.173.14:31:25.95#ibcon#read 3, iclass 35, count 0 2006.173.14:31:25.95#ibcon#about to read 4, iclass 35, count 0 2006.173.14:31:25.95#ibcon#read 4, iclass 35, count 0 2006.173.14:31:25.95#ibcon#about to read 5, iclass 35, count 0 2006.173.14:31:25.95#ibcon#read 5, iclass 35, count 0 2006.173.14:31:25.95#ibcon#about to read 6, iclass 35, count 0 2006.173.14:31:25.95#ibcon#read 6, iclass 35, count 0 2006.173.14:31:25.95#ibcon#end of sib2, iclass 35, count 0 2006.173.14:31:25.95#ibcon#*mode == 0, iclass 35, count 0 2006.173.14:31:25.95#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.14:31:25.95#ibcon#[25=USB\r\n] 2006.173.14:31:25.95#ibcon#*before write, iclass 35, count 0 2006.173.14:31:25.95#ibcon#enter sib2, iclass 35, count 0 2006.173.14:31:25.95#ibcon#flushed, iclass 35, count 0 2006.173.14:31:25.95#ibcon#about to write, iclass 35, count 0 2006.173.14:31:25.95#ibcon#wrote, iclass 35, count 0 2006.173.14:31:25.95#ibcon#about to read 3, iclass 35, count 0 2006.173.14:31:25.98#ibcon#read 3, iclass 35, count 0 2006.173.14:31:25.98#ibcon#about to read 4, iclass 35, count 0 2006.173.14:31:25.98#ibcon#read 4, iclass 35, count 0 2006.173.14:31:25.98#ibcon#about to read 5, iclass 35, count 0 2006.173.14:31:25.98#ibcon#read 5, iclass 35, count 0 2006.173.14:31:25.98#ibcon#about to read 6, iclass 35, count 0 2006.173.14:31:25.98#ibcon#read 6, iclass 35, count 0 2006.173.14:31:25.98#ibcon#end of sib2, iclass 35, count 0 2006.173.14:31:25.98#ibcon#*after write, iclass 35, count 0 2006.173.14:31:25.98#ibcon#*before return 0, iclass 35, count 0 2006.173.14:31:25.98#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.14:31:25.98#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.14:31:25.98#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.14:31:25.98#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.14:31:25.98$vck44/vblo=1,629.99 2006.173.14:31:25.98#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.14:31:25.98#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.14:31:25.98#ibcon#ireg 17 cls_cnt 0 2006.173.14:31:25.98#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.14:31:25.98#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.14:31:25.98#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.14:31:25.98#ibcon#enter wrdev, iclass 37, count 0 2006.173.14:31:25.98#ibcon#first serial, iclass 37, count 0 2006.173.14:31:25.98#ibcon#enter sib2, iclass 37, count 0 2006.173.14:31:25.98#ibcon#flushed, iclass 37, count 0 2006.173.14:31:25.98#ibcon#about to write, iclass 37, count 0 2006.173.14:31:25.98#ibcon#wrote, iclass 37, count 0 2006.173.14:31:25.98#ibcon#about to read 3, iclass 37, count 0 2006.173.14:31:26.00#ibcon#read 3, iclass 37, count 0 2006.173.14:31:26.00#ibcon#about to read 4, iclass 37, count 0 2006.173.14:31:26.00#ibcon#read 4, iclass 37, count 0 2006.173.14:31:26.00#ibcon#about to read 5, iclass 37, count 0 2006.173.14:31:26.00#ibcon#read 5, iclass 37, count 0 2006.173.14:31:26.00#ibcon#about to read 6, iclass 37, count 0 2006.173.14:31:26.00#ibcon#read 6, iclass 37, count 0 2006.173.14:31:26.00#ibcon#end of sib2, iclass 37, count 0 2006.173.14:31:26.00#ibcon#*mode == 0, iclass 37, count 0 2006.173.14:31:26.00#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.14:31:26.00#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.14:31:26.00#ibcon#*before write, iclass 37, count 0 2006.173.14:31:26.00#ibcon#enter sib2, iclass 37, count 0 2006.173.14:31:26.00#ibcon#flushed, iclass 37, count 0 2006.173.14:31:26.00#ibcon#about to write, iclass 37, count 0 2006.173.14:31:26.00#ibcon#wrote, iclass 37, count 0 2006.173.14:31:26.00#ibcon#about to read 3, iclass 37, count 0 2006.173.14:31:26.04#ibcon#read 3, iclass 37, count 0 2006.173.14:31:26.04#ibcon#about to read 4, iclass 37, count 0 2006.173.14:31:26.04#ibcon#read 4, iclass 37, count 0 2006.173.14:31:26.04#ibcon#about to read 5, iclass 37, count 0 2006.173.14:31:26.04#ibcon#read 5, iclass 37, count 0 2006.173.14:31:26.04#ibcon#about to read 6, iclass 37, count 0 2006.173.14:31:26.04#ibcon#read 6, iclass 37, count 0 2006.173.14:31:26.04#ibcon#end of sib2, iclass 37, count 0 2006.173.14:31:26.04#ibcon#*after write, iclass 37, count 0 2006.173.14:31:26.04#ibcon#*before return 0, iclass 37, count 0 2006.173.14:31:26.04#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.14:31:26.04#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.14:31:26.04#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.14:31:26.04#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.14:31:26.04$vck44/vb=1,4 2006.173.14:31:26.04#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.14:31:26.04#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.14:31:26.04#ibcon#ireg 11 cls_cnt 2 2006.173.14:31:26.04#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.14:31:26.04#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.14:31:26.04#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.14:31:26.04#ibcon#enter wrdev, iclass 39, count 2 2006.173.14:31:26.04#ibcon#first serial, iclass 39, count 2 2006.173.14:31:26.04#ibcon#enter sib2, iclass 39, count 2 2006.173.14:31:26.04#ibcon#flushed, iclass 39, count 2 2006.173.14:31:26.04#ibcon#about to write, iclass 39, count 2 2006.173.14:31:26.04#ibcon#wrote, iclass 39, count 2 2006.173.14:31:26.04#ibcon#about to read 3, iclass 39, count 2 2006.173.14:31:26.06#ibcon#read 3, iclass 39, count 2 2006.173.14:31:26.06#ibcon#about to read 4, iclass 39, count 2 2006.173.14:31:26.06#ibcon#read 4, iclass 39, count 2 2006.173.14:31:26.06#ibcon#about to read 5, iclass 39, count 2 2006.173.14:31:26.06#ibcon#read 5, iclass 39, count 2 2006.173.14:31:26.06#ibcon#about to read 6, iclass 39, count 2 2006.173.14:31:26.06#ibcon#read 6, iclass 39, count 2 2006.173.14:31:26.06#ibcon#end of sib2, iclass 39, count 2 2006.173.14:31:26.06#ibcon#*mode == 0, iclass 39, count 2 2006.173.14:31:26.06#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.14:31:26.06#ibcon#[27=AT01-04\r\n] 2006.173.14:31:26.06#ibcon#*before write, iclass 39, count 2 2006.173.14:31:26.06#ibcon#enter sib2, iclass 39, count 2 2006.173.14:31:26.06#ibcon#flushed, iclass 39, count 2 2006.173.14:31:26.06#ibcon#about to write, iclass 39, count 2 2006.173.14:31:26.06#ibcon#wrote, iclass 39, count 2 2006.173.14:31:26.06#ibcon#about to read 3, iclass 39, count 2 2006.173.14:31:26.09#ibcon#read 3, iclass 39, count 2 2006.173.14:31:26.09#ibcon#about to read 4, iclass 39, count 2 2006.173.14:31:26.09#ibcon#read 4, iclass 39, count 2 2006.173.14:31:26.09#ibcon#about to read 5, iclass 39, count 2 2006.173.14:31:26.09#ibcon#read 5, iclass 39, count 2 2006.173.14:31:26.09#ibcon#about to read 6, iclass 39, count 2 2006.173.14:31:26.09#ibcon#read 6, iclass 39, count 2 2006.173.14:31:26.09#ibcon#end of sib2, iclass 39, count 2 2006.173.14:31:26.09#ibcon#*after write, iclass 39, count 2 2006.173.14:31:26.09#ibcon#*before return 0, iclass 39, count 2 2006.173.14:31:26.09#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.14:31:26.09#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.14:31:26.09#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.14:31:26.09#ibcon#ireg 7 cls_cnt 0 2006.173.14:31:26.09#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.14:31:26.21#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.14:31:26.21#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.14:31:26.21#ibcon#enter wrdev, iclass 39, count 0 2006.173.14:31:26.21#ibcon#first serial, iclass 39, count 0 2006.173.14:31:26.21#ibcon#enter sib2, iclass 39, count 0 2006.173.14:31:26.21#ibcon#flushed, iclass 39, count 0 2006.173.14:31:26.21#ibcon#about to write, iclass 39, count 0 2006.173.14:31:26.21#ibcon#wrote, iclass 39, count 0 2006.173.14:31:26.21#ibcon#about to read 3, iclass 39, count 0 2006.173.14:31:26.23#ibcon#read 3, iclass 39, count 0 2006.173.14:31:26.23#ibcon#about to read 4, iclass 39, count 0 2006.173.14:31:26.23#ibcon#read 4, iclass 39, count 0 2006.173.14:31:26.23#ibcon#about to read 5, iclass 39, count 0 2006.173.14:31:26.23#ibcon#read 5, iclass 39, count 0 2006.173.14:31:26.23#ibcon#about to read 6, iclass 39, count 0 2006.173.14:31:26.23#ibcon#read 6, iclass 39, count 0 2006.173.14:31:26.23#ibcon#end of sib2, iclass 39, count 0 2006.173.14:31:26.23#ibcon#*mode == 0, iclass 39, count 0 2006.173.14:31:26.23#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.14:31:26.23#ibcon#[27=USB\r\n] 2006.173.14:31:26.23#ibcon#*before write, iclass 39, count 0 2006.173.14:31:26.23#ibcon#enter sib2, iclass 39, count 0 2006.173.14:31:26.23#ibcon#flushed, iclass 39, count 0 2006.173.14:31:26.23#ibcon#about to write, iclass 39, count 0 2006.173.14:31:26.23#ibcon#wrote, iclass 39, count 0 2006.173.14:31:26.23#ibcon#about to read 3, iclass 39, count 0 2006.173.14:31:26.26#ibcon#read 3, iclass 39, count 0 2006.173.14:31:26.26#ibcon#about to read 4, iclass 39, count 0 2006.173.14:31:26.26#ibcon#read 4, iclass 39, count 0 2006.173.14:31:26.26#ibcon#about to read 5, iclass 39, count 0 2006.173.14:31:26.26#ibcon#read 5, iclass 39, count 0 2006.173.14:31:26.26#ibcon#about to read 6, iclass 39, count 0 2006.173.14:31:26.26#ibcon#read 6, iclass 39, count 0 2006.173.14:31:26.26#ibcon#end of sib2, iclass 39, count 0 2006.173.14:31:26.26#ibcon#*after write, iclass 39, count 0 2006.173.14:31:26.26#ibcon#*before return 0, iclass 39, count 0 2006.173.14:31:26.26#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.14:31:26.26#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.14:31:26.26#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.14:31:26.26#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.14:31:26.26$vck44/vblo=2,634.99 2006.173.14:31:26.26#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.14:31:26.26#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.14:31:26.26#ibcon#ireg 17 cls_cnt 0 2006.173.14:31:26.26#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.14:31:26.26#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.14:31:26.26#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.14:31:26.26#ibcon#enter wrdev, iclass 3, count 0 2006.173.14:31:26.26#ibcon#first serial, iclass 3, count 0 2006.173.14:31:26.26#ibcon#enter sib2, iclass 3, count 0 2006.173.14:31:26.26#ibcon#flushed, iclass 3, count 0 2006.173.14:31:26.26#ibcon#about to write, iclass 3, count 0 2006.173.14:31:26.26#ibcon#wrote, iclass 3, count 0 2006.173.14:31:26.26#ibcon#about to read 3, iclass 3, count 0 2006.173.14:31:26.28#ibcon#read 3, iclass 3, count 0 2006.173.14:31:26.28#ibcon#about to read 4, iclass 3, count 0 2006.173.14:31:26.28#ibcon#read 4, iclass 3, count 0 2006.173.14:31:26.28#ibcon#about to read 5, iclass 3, count 0 2006.173.14:31:26.28#ibcon#read 5, iclass 3, count 0 2006.173.14:31:26.28#ibcon#about to read 6, iclass 3, count 0 2006.173.14:31:26.28#ibcon#read 6, iclass 3, count 0 2006.173.14:31:26.28#ibcon#end of sib2, iclass 3, count 0 2006.173.14:31:26.28#ibcon#*mode == 0, iclass 3, count 0 2006.173.14:31:26.28#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.14:31:26.28#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.14:31:26.28#ibcon#*before write, iclass 3, count 0 2006.173.14:31:26.28#ibcon#enter sib2, iclass 3, count 0 2006.173.14:31:26.28#ibcon#flushed, iclass 3, count 0 2006.173.14:31:26.28#ibcon#about to write, iclass 3, count 0 2006.173.14:31:26.28#ibcon#wrote, iclass 3, count 0 2006.173.14:31:26.28#ibcon#about to read 3, iclass 3, count 0 2006.173.14:31:26.32#ibcon#read 3, iclass 3, count 0 2006.173.14:31:26.32#ibcon#about to read 4, iclass 3, count 0 2006.173.14:31:26.32#ibcon#read 4, iclass 3, count 0 2006.173.14:31:26.32#ibcon#about to read 5, iclass 3, count 0 2006.173.14:31:26.32#ibcon#read 5, iclass 3, count 0 2006.173.14:31:26.32#ibcon#about to read 6, iclass 3, count 0 2006.173.14:31:26.32#ibcon#read 6, iclass 3, count 0 2006.173.14:31:26.32#ibcon#end of sib2, iclass 3, count 0 2006.173.14:31:26.32#ibcon#*after write, iclass 3, count 0 2006.173.14:31:26.32#ibcon#*before return 0, iclass 3, count 0 2006.173.14:31:26.32#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.14:31:26.32#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.14:31:26.32#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.14:31:26.32#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.14:31:26.32$vck44/vb=2,4 2006.173.14:31:26.32#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.14:31:26.32#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.14:31:26.32#ibcon#ireg 11 cls_cnt 2 2006.173.14:31:26.32#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.14:31:26.38#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.14:31:26.38#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.14:31:26.38#ibcon#enter wrdev, iclass 5, count 2 2006.173.14:31:26.38#ibcon#first serial, iclass 5, count 2 2006.173.14:31:26.38#ibcon#enter sib2, iclass 5, count 2 2006.173.14:31:26.38#ibcon#flushed, iclass 5, count 2 2006.173.14:31:26.38#ibcon#about to write, iclass 5, count 2 2006.173.14:31:26.38#ibcon#wrote, iclass 5, count 2 2006.173.14:31:26.38#ibcon#about to read 3, iclass 5, count 2 2006.173.14:31:26.40#ibcon#read 3, iclass 5, count 2 2006.173.14:31:26.40#ibcon#about to read 4, iclass 5, count 2 2006.173.14:31:26.40#ibcon#read 4, iclass 5, count 2 2006.173.14:31:26.40#ibcon#about to read 5, iclass 5, count 2 2006.173.14:31:26.40#ibcon#read 5, iclass 5, count 2 2006.173.14:31:26.40#ibcon#about to read 6, iclass 5, count 2 2006.173.14:31:26.40#ibcon#read 6, iclass 5, count 2 2006.173.14:31:26.40#ibcon#end of sib2, iclass 5, count 2 2006.173.14:31:26.40#ibcon#*mode == 0, iclass 5, count 2 2006.173.14:31:26.40#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.14:31:26.40#ibcon#[27=AT02-04\r\n] 2006.173.14:31:26.40#ibcon#*before write, iclass 5, count 2 2006.173.14:31:26.40#ibcon#enter sib2, iclass 5, count 2 2006.173.14:31:26.40#ibcon#flushed, iclass 5, count 2 2006.173.14:31:26.40#ibcon#about to write, iclass 5, count 2 2006.173.14:31:26.40#ibcon#wrote, iclass 5, count 2 2006.173.14:31:26.40#ibcon#about to read 3, iclass 5, count 2 2006.173.14:31:26.43#ibcon#read 3, iclass 5, count 2 2006.173.14:31:26.43#ibcon#about to read 4, iclass 5, count 2 2006.173.14:31:26.43#ibcon#read 4, iclass 5, count 2 2006.173.14:31:26.43#ibcon#about to read 5, iclass 5, count 2 2006.173.14:31:26.43#ibcon#read 5, iclass 5, count 2 2006.173.14:31:26.43#ibcon#about to read 6, iclass 5, count 2 2006.173.14:31:26.43#ibcon#read 6, iclass 5, count 2 2006.173.14:31:26.43#ibcon#end of sib2, iclass 5, count 2 2006.173.14:31:26.43#ibcon#*after write, iclass 5, count 2 2006.173.14:31:26.43#ibcon#*before return 0, iclass 5, count 2 2006.173.14:31:26.43#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.14:31:26.43#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.14:31:26.43#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.14:31:26.43#ibcon#ireg 7 cls_cnt 0 2006.173.14:31:26.43#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.14:31:26.55#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.14:31:26.55#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.14:31:26.55#ibcon#enter wrdev, iclass 5, count 0 2006.173.14:31:26.55#ibcon#first serial, iclass 5, count 0 2006.173.14:31:26.55#ibcon#enter sib2, iclass 5, count 0 2006.173.14:31:26.55#ibcon#flushed, iclass 5, count 0 2006.173.14:31:26.55#ibcon#about to write, iclass 5, count 0 2006.173.14:31:26.55#ibcon#wrote, iclass 5, count 0 2006.173.14:31:26.55#ibcon#about to read 3, iclass 5, count 0 2006.173.14:31:26.57#ibcon#read 3, iclass 5, count 0 2006.173.14:31:26.57#ibcon#about to read 4, iclass 5, count 0 2006.173.14:31:26.57#ibcon#read 4, iclass 5, count 0 2006.173.14:31:26.57#ibcon#about to read 5, iclass 5, count 0 2006.173.14:31:26.57#ibcon#read 5, iclass 5, count 0 2006.173.14:31:26.57#ibcon#about to read 6, iclass 5, count 0 2006.173.14:31:26.57#ibcon#read 6, iclass 5, count 0 2006.173.14:31:26.57#ibcon#end of sib2, iclass 5, count 0 2006.173.14:31:26.57#ibcon#*mode == 0, iclass 5, count 0 2006.173.14:31:26.57#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.14:31:26.57#ibcon#[27=USB\r\n] 2006.173.14:31:26.57#ibcon#*before write, iclass 5, count 0 2006.173.14:31:26.57#ibcon#enter sib2, iclass 5, count 0 2006.173.14:31:26.57#ibcon#flushed, iclass 5, count 0 2006.173.14:31:26.57#ibcon#about to write, iclass 5, count 0 2006.173.14:31:26.57#ibcon#wrote, iclass 5, count 0 2006.173.14:31:26.57#ibcon#about to read 3, iclass 5, count 0 2006.173.14:31:26.60#ibcon#read 3, iclass 5, count 0 2006.173.14:31:26.60#ibcon#about to read 4, iclass 5, count 0 2006.173.14:31:26.60#ibcon#read 4, iclass 5, count 0 2006.173.14:31:26.60#ibcon#about to read 5, iclass 5, count 0 2006.173.14:31:26.60#ibcon#read 5, iclass 5, count 0 2006.173.14:31:26.60#ibcon#about to read 6, iclass 5, count 0 2006.173.14:31:26.60#ibcon#read 6, iclass 5, count 0 2006.173.14:31:26.60#ibcon#end of sib2, iclass 5, count 0 2006.173.14:31:26.60#ibcon#*after write, iclass 5, count 0 2006.173.14:31:26.60#ibcon#*before return 0, iclass 5, count 0 2006.173.14:31:26.60#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.14:31:26.60#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.14:31:26.60#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.14:31:26.60#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.14:31:26.60$vck44/vblo=3,649.99 2006.173.14:31:26.60#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.14:31:26.60#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.14:31:26.60#ibcon#ireg 17 cls_cnt 0 2006.173.14:31:26.60#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.14:31:26.60#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.14:31:26.60#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.14:31:26.60#ibcon#enter wrdev, iclass 7, count 0 2006.173.14:31:26.60#ibcon#first serial, iclass 7, count 0 2006.173.14:31:26.60#ibcon#enter sib2, iclass 7, count 0 2006.173.14:31:26.60#ibcon#flushed, iclass 7, count 0 2006.173.14:31:26.60#ibcon#about to write, iclass 7, count 0 2006.173.14:31:26.60#ibcon#wrote, iclass 7, count 0 2006.173.14:31:26.60#ibcon#about to read 3, iclass 7, count 0 2006.173.14:31:26.62#ibcon#read 3, iclass 7, count 0 2006.173.14:31:26.62#ibcon#about to read 4, iclass 7, count 0 2006.173.14:31:26.62#ibcon#read 4, iclass 7, count 0 2006.173.14:31:26.62#ibcon#about to read 5, iclass 7, count 0 2006.173.14:31:26.62#ibcon#read 5, iclass 7, count 0 2006.173.14:31:26.62#ibcon#about to read 6, iclass 7, count 0 2006.173.14:31:26.62#ibcon#read 6, iclass 7, count 0 2006.173.14:31:26.62#ibcon#end of sib2, iclass 7, count 0 2006.173.14:31:26.62#ibcon#*mode == 0, iclass 7, count 0 2006.173.14:31:26.62#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.14:31:26.62#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.14:31:26.62#ibcon#*before write, iclass 7, count 0 2006.173.14:31:26.62#ibcon#enter sib2, iclass 7, count 0 2006.173.14:31:26.62#ibcon#flushed, iclass 7, count 0 2006.173.14:31:26.62#ibcon#about to write, iclass 7, count 0 2006.173.14:31:26.62#ibcon#wrote, iclass 7, count 0 2006.173.14:31:26.62#ibcon#about to read 3, iclass 7, count 0 2006.173.14:31:26.66#ibcon#read 3, iclass 7, count 0 2006.173.14:31:26.66#ibcon#about to read 4, iclass 7, count 0 2006.173.14:31:26.66#ibcon#read 4, iclass 7, count 0 2006.173.14:31:26.66#ibcon#about to read 5, iclass 7, count 0 2006.173.14:31:26.66#ibcon#read 5, iclass 7, count 0 2006.173.14:31:26.66#ibcon#about to read 6, iclass 7, count 0 2006.173.14:31:26.66#ibcon#read 6, iclass 7, count 0 2006.173.14:31:26.66#ibcon#end of sib2, iclass 7, count 0 2006.173.14:31:26.66#ibcon#*after write, iclass 7, count 0 2006.173.14:31:26.66#ibcon#*before return 0, iclass 7, count 0 2006.173.14:31:26.66#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.14:31:26.66#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.14:31:26.66#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.14:31:26.66#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.14:31:26.66$vck44/vb=3,4 2006.173.14:31:26.66#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.14:31:26.66#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.14:31:26.66#ibcon#ireg 11 cls_cnt 2 2006.173.14:31:26.66#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.14:31:26.72#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.14:31:26.72#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.14:31:26.72#ibcon#enter wrdev, iclass 11, count 2 2006.173.14:31:26.72#ibcon#first serial, iclass 11, count 2 2006.173.14:31:26.72#ibcon#enter sib2, iclass 11, count 2 2006.173.14:31:26.72#ibcon#flushed, iclass 11, count 2 2006.173.14:31:26.72#ibcon#about to write, iclass 11, count 2 2006.173.14:31:26.72#ibcon#wrote, iclass 11, count 2 2006.173.14:31:26.72#ibcon#about to read 3, iclass 11, count 2 2006.173.14:31:26.74#ibcon#read 3, iclass 11, count 2 2006.173.14:31:26.74#ibcon#about to read 4, iclass 11, count 2 2006.173.14:31:26.74#ibcon#read 4, iclass 11, count 2 2006.173.14:31:26.74#ibcon#about to read 5, iclass 11, count 2 2006.173.14:31:26.74#ibcon#read 5, iclass 11, count 2 2006.173.14:31:26.74#ibcon#about to read 6, iclass 11, count 2 2006.173.14:31:26.74#ibcon#read 6, iclass 11, count 2 2006.173.14:31:26.74#ibcon#end of sib2, iclass 11, count 2 2006.173.14:31:26.74#ibcon#*mode == 0, iclass 11, count 2 2006.173.14:31:26.74#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.14:31:26.74#ibcon#[27=AT03-04\r\n] 2006.173.14:31:26.74#ibcon#*before write, iclass 11, count 2 2006.173.14:31:26.74#ibcon#enter sib2, iclass 11, count 2 2006.173.14:31:26.74#ibcon#flushed, iclass 11, count 2 2006.173.14:31:26.74#ibcon#about to write, iclass 11, count 2 2006.173.14:31:26.74#ibcon#wrote, iclass 11, count 2 2006.173.14:31:26.74#ibcon#about to read 3, iclass 11, count 2 2006.173.14:31:26.77#ibcon#read 3, iclass 11, count 2 2006.173.14:31:26.77#ibcon#about to read 4, iclass 11, count 2 2006.173.14:31:26.77#ibcon#read 4, iclass 11, count 2 2006.173.14:31:26.77#ibcon#about to read 5, iclass 11, count 2 2006.173.14:31:26.77#ibcon#read 5, iclass 11, count 2 2006.173.14:31:26.77#ibcon#about to read 6, iclass 11, count 2 2006.173.14:31:26.77#ibcon#read 6, iclass 11, count 2 2006.173.14:31:26.77#ibcon#end of sib2, iclass 11, count 2 2006.173.14:31:26.77#ibcon#*after write, iclass 11, count 2 2006.173.14:31:26.77#ibcon#*before return 0, iclass 11, count 2 2006.173.14:31:26.77#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.14:31:26.77#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.14:31:26.77#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.14:31:26.77#ibcon#ireg 7 cls_cnt 0 2006.173.14:31:26.77#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.14:31:26.89#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.14:31:26.89#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.14:31:26.89#ibcon#enter wrdev, iclass 11, count 0 2006.173.14:31:26.89#ibcon#first serial, iclass 11, count 0 2006.173.14:31:26.89#ibcon#enter sib2, iclass 11, count 0 2006.173.14:31:26.89#ibcon#flushed, iclass 11, count 0 2006.173.14:31:26.89#ibcon#about to write, iclass 11, count 0 2006.173.14:31:26.89#ibcon#wrote, iclass 11, count 0 2006.173.14:31:26.89#ibcon#about to read 3, iclass 11, count 0 2006.173.14:31:26.91#ibcon#read 3, iclass 11, count 0 2006.173.14:31:26.91#ibcon#about to read 4, iclass 11, count 0 2006.173.14:31:26.91#ibcon#read 4, iclass 11, count 0 2006.173.14:31:26.91#ibcon#about to read 5, iclass 11, count 0 2006.173.14:31:26.91#ibcon#read 5, iclass 11, count 0 2006.173.14:31:26.91#ibcon#about to read 6, iclass 11, count 0 2006.173.14:31:26.91#ibcon#read 6, iclass 11, count 0 2006.173.14:31:26.91#ibcon#end of sib2, iclass 11, count 0 2006.173.14:31:26.91#ibcon#*mode == 0, iclass 11, count 0 2006.173.14:31:26.91#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.14:31:26.91#ibcon#[27=USB\r\n] 2006.173.14:31:26.91#ibcon#*before write, iclass 11, count 0 2006.173.14:31:26.91#ibcon#enter sib2, iclass 11, count 0 2006.173.14:31:26.91#ibcon#flushed, iclass 11, count 0 2006.173.14:31:26.91#ibcon#about to write, iclass 11, count 0 2006.173.14:31:26.91#ibcon#wrote, iclass 11, count 0 2006.173.14:31:26.91#ibcon#about to read 3, iclass 11, count 0 2006.173.14:31:26.94#ibcon#read 3, iclass 11, count 0 2006.173.14:31:26.94#ibcon#about to read 4, iclass 11, count 0 2006.173.14:31:26.94#ibcon#read 4, iclass 11, count 0 2006.173.14:31:26.94#ibcon#about to read 5, iclass 11, count 0 2006.173.14:31:26.94#ibcon#read 5, iclass 11, count 0 2006.173.14:31:26.94#ibcon#about to read 6, iclass 11, count 0 2006.173.14:31:26.94#ibcon#read 6, iclass 11, count 0 2006.173.14:31:26.94#ibcon#end of sib2, iclass 11, count 0 2006.173.14:31:26.94#ibcon#*after write, iclass 11, count 0 2006.173.14:31:26.94#ibcon#*before return 0, iclass 11, count 0 2006.173.14:31:26.94#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.14:31:26.94#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.14:31:26.94#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.14:31:26.94#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.14:31:26.94$vck44/vblo=4,679.99 2006.173.14:31:26.94#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.14:31:26.94#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.14:31:26.94#ibcon#ireg 17 cls_cnt 0 2006.173.14:31:26.94#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.14:31:26.94#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.14:31:26.94#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.14:31:26.94#ibcon#enter wrdev, iclass 13, count 0 2006.173.14:31:26.94#ibcon#first serial, iclass 13, count 0 2006.173.14:31:26.94#ibcon#enter sib2, iclass 13, count 0 2006.173.14:31:26.94#ibcon#flushed, iclass 13, count 0 2006.173.14:31:26.94#ibcon#about to write, iclass 13, count 0 2006.173.14:31:26.94#ibcon#wrote, iclass 13, count 0 2006.173.14:31:26.94#ibcon#about to read 3, iclass 13, count 0 2006.173.14:31:26.96#ibcon#read 3, iclass 13, count 0 2006.173.14:31:26.96#ibcon#about to read 4, iclass 13, count 0 2006.173.14:31:26.96#ibcon#read 4, iclass 13, count 0 2006.173.14:31:26.96#ibcon#about to read 5, iclass 13, count 0 2006.173.14:31:26.96#ibcon#read 5, iclass 13, count 0 2006.173.14:31:26.96#ibcon#about to read 6, iclass 13, count 0 2006.173.14:31:26.96#ibcon#read 6, iclass 13, count 0 2006.173.14:31:26.96#ibcon#end of sib2, iclass 13, count 0 2006.173.14:31:26.96#ibcon#*mode == 0, iclass 13, count 0 2006.173.14:31:26.96#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.14:31:26.96#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.14:31:26.96#ibcon#*before write, iclass 13, count 0 2006.173.14:31:26.96#ibcon#enter sib2, iclass 13, count 0 2006.173.14:31:26.96#ibcon#flushed, iclass 13, count 0 2006.173.14:31:26.96#ibcon#about to write, iclass 13, count 0 2006.173.14:31:26.96#ibcon#wrote, iclass 13, count 0 2006.173.14:31:26.96#ibcon#about to read 3, iclass 13, count 0 2006.173.14:31:27.00#ibcon#read 3, iclass 13, count 0 2006.173.14:31:27.00#ibcon#about to read 4, iclass 13, count 0 2006.173.14:31:27.00#ibcon#read 4, iclass 13, count 0 2006.173.14:31:27.00#ibcon#about to read 5, iclass 13, count 0 2006.173.14:31:27.00#ibcon#read 5, iclass 13, count 0 2006.173.14:31:27.00#ibcon#about to read 6, iclass 13, count 0 2006.173.14:31:27.00#ibcon#read 6, iclass 13, count 0 2006.173.14:31:27.00#ibcon#end of sib2, iclass 13, count 0 2006.173.14:31:27.00#ibcon#*after write, iclass 13, count 0 2006.173.14:31:27.00#ibcon#*before return 0, iclass 13, count 0 2006.173.14:31:27.00#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.14:31:27.00#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.14:31:27.00#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.14:31:27.00#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.14:31:27.00$vck44/vb=4,4 2006.173.14:31:27.00#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.14:31:27.00#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.14:31:27.00#ibcon#ireg 11 cls_cnt 2 2006.173.14:31:27.00#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.14:31:27.06#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.14:31:27.06#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.14:31:27.06#ibcon#enter wrdev, iclass 15, count 2 2006.173.14:31:27.06#ibcon#first serial, iclass 15, count 2 2006.173.14:31:27.06#ibcon#enter sib2, iclass 15, count 2 2006.173.14:31:27.06#ibcon#flushed, iclass 15, count 2 2006.173.14:31:27.06#ibcon#about to write, iclass 15, count 2 2006.173.14:31:27.06#ibcon#wrote, iclass 15, count 2 2006.173.14:31:27.06#ibcon#about to read 3, iclass 15, count 2 2006.173.14:31:27.08#ibcon#read 3, iclass 15, count 2 2006.173.14:31:27.08#ibcon#about to read 4, iclass 15, count 2 2006.173.14:31:27.08#ibcon#read 4, iclass 15, count 2 2006.173.14:31:27.08#ibcon#about to read 5, iclass 15, count 2 2006.173.14:31:27.08#ibcon#read 5, iclass 15, count 2 2006.173.14:31:27.08#ibcon#about to read 6, iclass 15, count 2 2006.173.14:31:27.08#ibcon#read 6, iclass 15, count 2 2006.173.14:31:27.08#ibcon#end of sib2, iclass 15, count 2 2006.173.14:31:27.08#ibcon#*mode == 0, iclass 15, count 2 2006.173.14:31:27.08#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.14:31:27.08#ibcon#[27=AT04-04\r\n] 2006.173.14:31:27.08#ibcon#*before write, iclass 15, count 2 2006.173.14:31:27.08#ibcon#enter sib2, iclass 15, count 2 2006.173.14:31:27.08#ibcon#flushed, iclass 15, count 2 2006.173.14:31:27.08#ibcon#about to write, iclass 15, count 2 2006.173.14:31:27.08#ibcon#wrote, iclass 15, count 2 2006.173.14:31:27.08#ibcon#about to read 3, iclass 15, count 2 2006.173.14:31:27.11#ibcon#read 3, iclass 15, count 2 2006.173.14:31:27.11#ibcon#about to read 4, iclass 15, count 2 2006.173.14:31:27.11#ibcon#read 4, iclass 15, count 2 2006.173.14:31:27.11#ibcon#about to read 5, iclass 15, count 2 2006.173.14:31:27.11#ibcon#read 5, iclass 15, count 2 2006.173.14:31:27.11#ibcon#about to read 6, iclass 15, count 2 2006.173.14:31:27.11#ibcon#read 6, iclass 15, count 2 2006.173.14:31:27.11#ibcon#end of sib2, iclass 15, count 2 2006.173.14:31:27.11#ibcon#*after write, iclass 15, count 2 2006.173.14:31:27.11#ibcon#*before return 0, iclass 15, count 2 2006.173.14:31:27.11#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.14:31:27.11#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.14:31:27.11#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.14:31:27.11#ibcon#ireg 7 cls_cnt 0 2006.173.14:31:27.11#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.14:31:27.23#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.14:31:27.23#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.14:31:27.23#ibcon#enter wrdev, iclass 15, count 0 2006.173.14:31:27.23#ibcon#first serial, iclass 15, count 0 2006.173.14:31:27.23#ibcon#enter sib2, iclass 15, count 0 2006.173.14:31:27.23#ibcon#flushed, iclass 15, count 0 2006.173.14:31:27.23#ibcon#about to write, iclass 15, count 0 2006.173.14:31:27.23#ibcon#wrote, iclass 15, count 0 2006.173.14:31:27.23#ibcon#about to read 3, iclass 15, count 0 2006.173.14:31:27.25#ibcon#read 3, iclass 15, count 0 2006.173.14:31:27.25#ibcon#about to read 4, iclass 15, count 0 2006.173.14:31:27.25#ibcon#read 4, iclass 15, count 0 2006.173.14:31:27.25#ibcon#about to read 5, iclass 15, count 0 2006.173.14:31:27.25#ibcon#read 5, iclass 15, count 0 2006.173.14:31:27.25#ibcon#about to read 6, iclass 15, count 0 2006.173.14:31:27.25#ibcon#read 6, iclass 15, count 0 2006.173.14:31:27.25#ibcon#end of sib2, iclass 15, count 0 2006.173.14:31:27.25#ibcon#*mode == 0, iclass 15, count 0 2006.173.14:31:27.25#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.14:31:27.25#ibcon#[27=USB\r\n] 2006.173.14:31:27.25#ibcon#*before write, iclass 15, count 0 2006.173.14:31:27.25#ibcon#enter sib2, iclass 15, count 0 2006.173.14:31:27.25#ibcon#flushed, iclass 15, count 0 2006.173.14:31:27.25#ibcon#about to write, iclass 15, count 0 2006.173.14:31:27.25#ibcon#wrote, iclass 15, count 0 2006.173.14:31:27.25#ibcon#about to read 3, iclass 15, count 0 2006.173.14:31:27.28#ibcon#read 3, iclass 15, count 0 2006.173.14:31:27.28#ibcon#about to read 4, iclass 15, count 0 2006.173.14:31:27.28#ibcon#read 4, iclass 15, count 0 2006.173.14:31:27.28#ibcon#about to read 5, iclass 15, count 0 2006.173.14:31:27.28#ibcon#read 5, iclass 15, count 0 2006.173.14:31:27.28#ibcon#about to read 6, iclass 15, count 0 2006.173.14:31:27.28#ibcon#read 6, iclass 15, count 0 2006.173.14:31:27.28#ibcon#end of sib2, iclass 15, count 0 2006.173.14:31:27.28#ibcon#*after write, iclass 15, count 0 2006.173.14:31:27.28#ibcon#*before return 0, iclass 15, count 0 2006.173.14:31:27.28#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.14:31:27.28#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.14:31:27.28#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.14:31:27.28#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.14:31:27.28$vck44/vblo=5,709.99 2006.173.14:31:27.28#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.14:31:27.28#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.14:31:27.28#ibcon#ireg 17 cls_cnt 0 2006.173.14:31:27.28#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.14:31:27.28#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.14:31:27.28#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.14:31:27.28#ibcon#enter wrdev, iclass 17, count 0 2006.173.14:31:27.28#ibcon#first serial, iclass 17, count 0 2006.173.14:31:27.28#ibcon#enter sib2, iclass 17, count 0 2006.173.14:31:27.28#ibcon#flushed, iclass 17, count 0 2006.173.14:31:27.28#ibcon#about to write, iclass 17, count 0 2006.173.14:31:27.28#ibcon#wrote, iclass 17, count 0 2006.173.14:31:27.28#ibcon#about to read 3, iclass 17, count 0 2006.173.14:31:27.30#ibcon#read 3, iclass 17, count 0 2006.173.14:31:27.30#ibcon#about to read 4, iclass 17, count 0 2006.173.14:31:27.30#ibcon#read 4, iclass 17, count 0 2006.173.14:31:27.30#ibcon#about to read 5, iclass 17, count 0 2006.173.14:31:27.30#ibcon#read 5, iclass 17, count 0 2006.173.14:31:27.30#ibcon#about to read 6, iclass 17, count 0 2006.173.14:31:27.30#ibcon#read 6, iclass 17, count 0 2006.173.14:31:27.30#ibcon#end of sib2, iclass 17, count 0 2006.173.14:31:27.30#ibcon#*mode == 0, iclass 17, count 0 2006.173.14:31:27.30#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.14:31:27.30#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.14:31:27.30#ibcon#*before write, iclass 17, count 0 2006.173.14:31:27.30#ibcon#enter sib2, iclass 17, count 0 2006.173.14:31:27.30#ibcon#flushed, iclass 17, count 0 2006.173.14:31:27.30#ibcon#about to write, iclass 17, count 0 2006.173.14:31:27.30#ibcon#wrote, iclass 17, count 0 2006.173.14:31:27.30#ibcon#about to read 3, iclass 17, count 0 2006.173.14:31:27.34#ibcon#read 3, iclass 17, count 0 2006.173.14:31:27.34#ibcon#about to read 4, iclass 17, count 0 2006.173.14:31:27.34#ibcon#read 4, iclass 17, count 0 2006.173.14:31:27.34#ibcon#about to read 5, iclass 17, count 0 2006.173.14:31:27.34#ibcon#read 5, iclass 17, count 0 2006.173.14:31:27.34#ibcon#about to read 6, iclass 17, count 0 2006.173.14:31:27.34#ibcon#read 6, iclass 17, count 0 2006.173.14:31:27.34#ibcon#end of sib2, iclass 17, count 0 2006.173.14:31:27.34#ibcon#*after write, iclass 17, count 0 2006.173.14:31:27.34#ibcon#*before return 0, iclass 17, count 0 2006.173.14:31:27.34#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.14:31:27.34#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.14:31:27.34#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.14:31:27.34#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.14:31:27.34$vck44/vb=5,4 2006.173.14:31:27.34#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.14:31:27.34#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.14:31:27.34#ibcon#ireg 11 cls_cnt 2 2006.173.14:31:27.34#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.14:31:27.40#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.14:31:27.40#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.14:31:27.40#ibcon#enter wrdev, iclass 19, count 2 2006.173.14:31:27.40#ibcon#first serial, iclass 19, count 2 2006.173.14:31:27.40#ibcon#enter sib2, iclass 19, count 2 2006.173.14:31:27.40#ibcon#flushed, iclass 19, count 2 2006.173.14:31:27.40#ibcon#about to write, iclass 19, count 2 2006.173.14:31:27.40#ibcon#wrote, iclass 19, count 2 2006.173.14:31:27.40#ibcon#about to read 3, iclass 19, count 2 2006.173.14:31:27.42#ibcon#read 3, iclass 19, count 2 2006.173.14:31:27.42#ibcon#about to read 4, iclass 19, count 2 2006.173.14:31:27.42#ibcon#read 4, iclass 19, count 2 2006.173.14:31:27.42#ibcon#about to read 5, iclass 19, count 2 2006.173.14:31:27.42#ibcon#read 5, iclass 19, count 2 2006.173.14:31:27.42#ibcon#about to read 6, iclass 19, count 2 2006.173.14:31:27.42#ibcon#read 6, iclass 19, count 2 2006.173.14:31:27.42#ibcon#end of sib2, iclass 19, count 2 2006.173.14:31:27.42#ibcon#*mode == 0, iclass 19, count 2 2006.173.14:31:27.42#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.14:31:27.42#ibcon#[27=AT05-04\r\n] 2006.173.14:31:27.42#ibcon#*before write, iclass 19, count 2 2006.173.14:31:27.42#ibcon#enter sib2, iclass 19, count 2 2006.173.14:31:27.42#ibcon#flushed, iclass 19, count 2 2006.173.14:31:27.42#ibcon#about to write, iclass 19, count 2 2006.173.14:31:27.42#ibcon#wrote, iclass 19, count 2 2006.173.14:31:27.42#ibcon#about to read 3, iclass 19, count 2 2006.173.14:31:27.45#ibcon#read 3, iclass 19, count 2 2006.173.14:31:27.45#ibcon#about to read 4, iclass 19, count 2 2006.173.14:31:27.45#ibcon#read 4, iclass 19, count 2 2006.173.14:31:27.45#ibcon#about to read 5, iclass 19, count 2 2006.173.14:31:27.45#ibcon#read 5, iclass 19, count 2 2006.173.14:31:27.45#ibcon#about to read 6, iclass 19, count 2 2006.173.14:31:27.45#ibcon#read 6, iclass 19, count 2 2006.173.14:31:27.45#ibcon#end of sib2, iclass 19, count 2 2006.173.14:31:27.45#ibcon#*after write, iclass 19, count 2 2006.173.14:31:27.45#ibcon#*before return 0, iclass 19, count 2 2006.173.14:31:27.45#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.14:31:27.45#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.14:31:27.45#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.14:31:27.45#ibcon#ireg 7 cls_cnt 0 2006.173.14:31:27.45#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.14:31:27.57#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.14:31:27.57#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.14:31:27.57#ibcon#enter wrdev, iclass 19, count 0 2006.173.14:31:27.57#ibcon#first serial, iclass 19, count 0 2006.173.14:31:27.57#ibcon#enter sib2, iclass 19, count 0 2006.173.14:31:27.57#ibcon#flushed, iclass 19, count 0 2006.173.14:31:27.57#ibcon#about to write, iclass 19, count 0 2006.173.14:31:27.57#ibcon#wrote, iclass 19, count 0 2006.173.14:31:27.57#ibcon#about to read 3, iclass 19, count 0 2006.173.14:31:27.59#ibcon#read 3, iclass 19, count 0 2006.173.14:31:27.59#ibcon#about to read 4, iclass 19, count 0 2006.173.14:31:27.59#ibcon#read 4, iclass 19, count 0 2006.173.14:31:27.59#ibcon#about to read 5, iclass 19, count 0 2006.173.14:31:27.59#ibcon#read 5, iclass 19, count 0 2006.173.14:31:27.59#ibcon#about to read 6, iclass 19, count 0 2006.173.14:31:27.59#ibcon#read 6, iclass 19, count 0 2006.173.14:31:27.59#ibcon#end of sib2, iclass 19, count 0 2006.173.14:31:27.59#ibcon#*mode == 0, iclass 19, count 0 2006.173.14:31:27.59#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.14:31:27.59#ibcon#[27=USB\r\n] 2006.173.14:31:27.59#ibcon#*before write, iclass 19, count 0 2006.173.14:31:27.59#ibcon#enter sib2, iclass 19, count 0 2006.173.14:31:27.59#ibcon#flushed, iclass 19, count 0 2006.173.14:31:27.59#ibcon#about to write, iclass 19, count 0 2006.173.14:31:27.59#ibcon#wrote, iclass 19, count 0 2006.173.14:31:27.59#ibcon#about to read 3, iclass 19, count 0 2006.173.14:31:27.62#ibcon#read 3, iclass 19, count 0 2006.173.14:31:27.62#ibcon#about to read 4, iclass 19, count 0 2006.173.14:31:27.62#ibcon#read 4, iclass 19, count 0 2006.173.14:31:27.62#ibcon#about to read 5, iclass 19, count 0 2006.173.14:31:27.62#ibcon#read 5, iclass 19, count 0 2006.173.14:31:27.62#ibcon#about to read 6, iclass 19, count 0 2006.173.14:31:27.62#ibcon#read 6, iclass 19, count 0 2006.173.14:31:27.62#ibcon#end of sib2, iclass 19, count 0 2006.173.14:31:27.62#ibcon#*after write, iclass 19, count 0 2006.173.14:31:27.62#ibcon#*before return 0, iclass 19, count 0 2006.173.14:31:27.62#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.14:31:27.62#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.14:31:27.62#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.14:31:27.62#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.14:31:27.62$vck44/vblo=6,719.99 2006.173.14:31:27.62#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.14:31:27.62#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.14:31:27.62#ibcon#ireg 17 cls_cnt 0 2006.173.14:31:27.62#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.14:31:27.62#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.14:31:27.62#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.14:31:27.62#ibcon#enter wrdev, iclass 21, count 0 2006.173.14:31:27.62#ibcon#first serial, iclass 21, count 0 2006.173.14:31:27.62#ibcon#enter sib2, iclass 21, count 0 2006.173.14:31:27.62#ibcon#flushed, iclass 21, count 0 2006.173.14:31:27.62#ibcon#about to write, iclass 21, count 0 2006.173.14:31:27.62#ibcon#wrote, iclass 21, count 0 2006.173.14:31:27.62#ibcon#about to read 3, iclass 21, count 0 2006.173.14:31:27.64#ibcon#read 3, iclass 21, count 0 2006.173.14:31:27.64#ibcon#about to read 4, iclass 21, count 0 2006.173.14:31:27.64#ibcon#read 4, iclass 21, count 0 2006.173.14:31:27.64#ibcon#about to read 5, iclass 21, count 0 2006.173.14:31:27.64#ibcon#read 5, iclass 21, count 0 2006.173.14:31:27.64#ibcon#about to read 6, iclass 21, count 0 2006.173.14:31:27.64#ibcon#read 6, iclass 21, count 0 2006.173.14:31:27.64#ibcon#end of sib2, iclass 21, count 0 2006.173.14:31:27.64#ibcon#*mode == 0, iclass 21, count 0 2006.173.14:31:27.64#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.14:31:27.64#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.14:31:27.64#ibcon#*before write, iclass 21, count 0 2006.173.14:31:27.64#ibcon#enter sib2, iclass 21, count 0 2006.173.14:31:27.64#ibcon#flushed, iclass 21, count 0 2006.173.14:31:27.64#ibcon#about to write, iclass 21, count 0 2006.173.14:31:27.64#ibcon#wrote, iclass 21, count 0 2006.173.14:31:27.64#ibcon#about to read 3, iclass 21, count 0 2006.173.14:31:27.68#ibcon#read 3, iclass 21, count 0 2006.173.14:31:27.68#ibcon#about to read 4, iclass 21, count 0 2006.173.14:31:27.68#ibcon#read 4, iclass 21, count 0 2006.173.14:31:27.68#ibcon#about to read 5, iclass 21, count 0 2006.173.14:31:27.68#ibcon#read 5, iclass 21, count 0 2006.173.14:31:27.68#ibcon#about to read 6, iclass 21, count 0 2006.173.14:31:27.68#ibcon#read 6, iclass 21, count 0 2006.173.14:31:27.68#ibcon#end of sib2, iclass 21, count 0 2006.173.14:31:27.68#ibcon#*after write, iclass 21, count 0 2006.173.14:31:27.68#ibcon#*before return 0, iclass 21, count 0 2006.173.14:31:27.68#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.14:31:27.68#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.14:31:27.68#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.14:31:27.68#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.14:31:27.68$vck44/vb=6,4 2006.173.14:31:27.68#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.14:31:27.68#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.14:31:27.68#ibcon#ireg 11 cls_cnt 2 2006.173.14:31:27.68#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.14:31:27.74#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.14:31:27.74#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.14:31:27.74#ibcon#enter wrdev, iclass 23, count 2 2006.173.14:31:27.74#ibcon#first serial, iclass 23, count 2 2006.173.14:31:27.74#ibcon#enter sib2, iclass 23, count 2 2006.173.14:31:27.74#ibcon#flushed, iclass 23, count 2 2006.173.14:31:27.74#ibcon#about to write, iclass 23, count 2 2006.173.14:31:27.74#ibcon#wrote, iclass 23, count 2 2006.173.14:31:27.74#ibcon#about to read 3, iclass 23, count 2 2006.173.14:31:27.76#ibcon#read 3, iclass 23, count 2 2006.173.14:31:27.76#ibcon#about to read 4, iclass 23, count 2 2006.173.14:31:27.76#ibcon#read 4, iclass 23, count 2 2006.173.14:31:27.76#ibcon#about to read 5, iclass 23, count 2 2006.173.14:31:27.76#ibcon#read 5, iclass 23, count 2 2006.173.14:31:27.76#ibcon#about to read 6, iclass 23, count 2 2006.173.14:31:27.76#ibcon#read 6, iclass 23, count 2 2006.173.14:31:27.76#ibcon#end of sib2, iclass 23, count 2 2006.173.14:31:27.76#ibcon#*mode == 0, iclass 23, count 2 2006.173.14:31:27.76#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.14:31:27.76#ibcon#[27=AT06-04\r\n] 2006.173.14:31:27.76#ibcon#*before write, iclass 23, count 2 2006.173.14:31:27.76#ibcon#enter sib2, iclass 23, count 2 2006.173.14:31:27.76#ibcon#flushed, iclass 23, count 2 2006.173.14:31:27.76#ibcon#about to write, iclass 23, count 2 2006.173.14:31:27.76#ibcon#wrote, iclass 23, count 2 2006.173.14:31:27.76#ibcon#about to read 3, iclass 23, count 2 2006.173.14:31:27.79#ibcon#read 3, iclass 23, count 2 2006.173.14:31:27.79#ibcon#about to read 4, iclass 23, count 2 2006.173.14:31:27.79#ibcon#read 4, iclass 23, count 2 2006.173.14:31:27.79#ibcon#about to read 5, iclass 23, count 2 2006.173.14:31:27.79#ibcon#read 5, iclass 23, count 2 2006.173.14:31:27.79#ibcon#about to read 6, iclass 23, count 2 2006.173.14:31:27.79#ibcon#read 6, iclass 23, count 2 2006.173.14:31:27.79#ibcon#end of sib2, iclass 23, count 2 2006.173.14:31:27.79#ibcon#*after write, iclass 23, count 2 2006.173.14:31:27.79#ibcon#*before return 0, iclass 23, count 2 2006.173.14:31:27.79#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.14:31:27.79#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.14:31:27.79#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.14:31:27.79#ibcon#ireg 7 cls_cnt 0 2006.173.14:31:27.79#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.14:31:27.91#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.14:31:27.91#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.14:31:27.91#ibcon#enter wrdev, iclass 23, count 0 2006.173.14:31:27.91#ibcon#first serial, iclass 23, count 0 2006.173.14:31:27.91#ibcon#enter sib2, iclass 23, count 0 2006.173.14:31:27.91#ibcon#flushed, iclass 23, count 0 2006.173.14:31:27.91#ibcon#about to write, iclass 23, count 0 2006.173.14:31:27.91#ibcon#wrote, iclass 23, count 0 2006.173.14:31:27.91#ibcon#about to read 3, iclass 23, count 0 2006.173.14:31:27.93#ibcon#read 3, iclass 23, count 0 2006.173.14:31:27.93#ibcon#about to read 4, iclass 23, count 0 2006.173.14:31:27.93#ibcon#read 4, iclass 23, count 0 2006.173.14:31:27.93#ibcon#about to read 5, iclass 23, count 0 2006.173.14:31:27.93#ibcon#read 5, iclass 23, count 0 2006.173.14:31:27.93#ibcon#about to read 6, iclass 23, count 0 2006.173.14:31:27.93#ibcon#read 6, iclass 23, count 0 2006.173.14:31:27.93#ibcon#end of sib2, iclass 23, count 0 2006.173.14:31:27.93#ibcon#*mode == 0, iclass 23, count 0 2006.173.14:31:27.93#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.14:31:27.93#ibcon#[27=USB\r\n] 2006.173.14:31:27.93#ibcon#*before write, iclass 23, count 0 2006.173.14:31:27.93#ibcon#enter sib2, iclass 23, count 0 2006.173.14:31:27.93#ibcon#flushed, iclass 23, count 0 2006.173.14:31:27.93#ibcon#about to write, iclass 23, count 0 2006.173.14:31:27.93#ibcon#wrote, iclass 23, count 0 2006.173.14:31:27.93#ibcon#about to read 3, iclass 23, count 0 2006.173.14:31:27.96#ibcon#read 3, iclass 23, count 0 2006.173.14:31:27.96#ibcon#about to read 4, iclass 23, count 0 2006.173.14:31:27.96#ibcon#read 4, iclass 23, count 0 2006.173.14:31:27.96#ibcon#about to read 5, iclass 23, count 0 2006.173.14:31:27.96#ibcon#read 5, iclass 23, count 0 2006.173.14:31:27.96#ibcon#about to read 6, iclass 23, count 0 2006.173.14:31:27.96#ibcon#read 6, iclass 23, count 0 2006.173.14:31:27.96#ibcon#end of sib2, iclass 23, count 0 2006.173.14:31:27.96#ibcon#*after write, iclass 23, count 0 2006.173.14:31:27.96#ibcon#*before return 0, iclass 23, count 0 2006.173.14:31:27.96#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.14:31:27.96#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.14:31:27.96#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.14:31:27.96#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.14:31:27.96$vck44/vblo=7,734.99 2006.173.14:31:27.96#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.14:31:27.96#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.14:31:27.96#ibcon#ireg 17 cls_cnt 0 2006.173.14:31:27.96#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.14:31:27.96#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.14:31:27.96#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.14:31:27.96#ibcon#enter wrdev, iclass 25, count 0 2006.173.14:31:27.96#ibcon#first serial, iclass 25, count 0 2006.173.14:31:27.96#ibcon#enter sib2, iclass 25, count 0 2006.173.14:31:27.96#ibcon#flushed, iclass 25, count 0 2006.173.14:31:27.96#ibcon#about to write, iclass 25, count 0 2006.173.14:31:27.96#ibcon#wrote, iclass 25, count 0 2006.173.14:31:27.96#ibcon#about to read 3, iclass 25, count 0 2006.173.14:31:27.98#ibcon#read 3, iclass 25, count 0 2006.173.14:31:27.98#ibcon#about to read 4, iclass 25, count 0 2006.173.14:31:27.98#ibcon#read 4, iclass 25, count 0 2006.173.14:31:27.98#ibcon#about to read 5, iclass 25, count 0 2006.173.14:31:27.98#ibcon#read 5, iclass 25, count 0 2006.173.14:31:27.98#ibcon#about to read 6, iclass 25, count 0 2006.173.14:31:27.98#ibcon#read 6, iclass 25, count 0 2006.173.14:31:27.98#ibcon#end of sib2, iclass 25, count 0 2006.173.14:31:27.98#ibcon#*mode == 0, iclass 25, count 0 2006.173.14:31:27.98#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.14:31:27.98#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.14:31:27.98#ibcon#*before write, iclass 25, count 0 2006.173.14:31:27.98#ibcon#enter sib2, iclass 25, count 0 2006.173.14:31:27.98#ibcon#flushed, iclass 25, count 0 2006.173.14:31:27.98#ibcon#about to write, iclass 25, count 0 2006.173.14:31:27.98#ibcon#wrote, iclass 25, count 0 2006.173.14:31:27.98#ibcon#about to read 3, iclass 25, count 0 2006.173.14:31:28.02#ibcon#read 3, iclass 25, count 0 2006.173.14:31:28.02#ibcon#about to read 4, iclass 25, count 0 2006.173.14:31:28.02#ibcon#read 4, iclass 25, count 0 2006.173.14:31:28.02#ibcon#about to read 5, iclass 25, count 0 2006.173.14:31:28.02#ibcon#read 5, iclass 25, count 0 2006.173.14:31:28.02#ibcon#about to read 6, iclass 25, count 0 2006.173.14:31:28.02#ibcon#read 6, iclass 25, count 0 2006.173.14:31:28.02#ibcon#end of sib2, iclass 25, count 0 2006.173.14:31:28.02#ibcon#*after write, iclass 25, count 0 2006.173.14:31:28.02#ibcon#*before return 0, iclass 25, count 0 2006.173.14:31:28.02#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.14:31:28.02#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.14:31:28.02#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.14:31:28.02#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.14:31:28.02$vck44/vb=7,4 2006.173.14:31:28.02#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.14:31:28.02#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.14:31:28.02#ibcon#ireg 11 cls_cnt 2 2006.173.14:31:28.02#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.14:31:28.08#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.14:31:28.08#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.14:31:28.08#ibcon#enter wrdev, iclass 27, count 2 2006.173.14:31:28.08#ibcon#first serial, iclass 27, count 2 2006.173.14:31:28.08#ibcon#enter sib2, iclass 27, count 2 2006.173.14:31:28.08#ibcon#flushed, iclass 27, count 2 2006.173.14:31:28.08#ibcon#about to write, iclass 27, count 2 2006.173.14:31:28.08#ibcon#wrote, iclass 27, count 2 2006.173.14:31:28.08#ibcon#about to read 3, iclass 27, count 2 2006.173.14:31:28.10#ibcon#read 3, iclass 27, count 2 2006.173.14:31:28.10#ibcon#about to read 4, iclass 27, count 2 2006.173.14:31:28.10#ibcon#read 4, iclass 27, count 2 2006.173.14:31:28.10#ibcon#about to read 5, iclass 27, count 2 2006.173.14:31:28.10#ibcon#read 5, iclass 27, count 2 2006.173.14:31:28.10#ibcon#about to read 6, iclass 27, count 2 2006.173.14:31:28.10#ibcon#read 6, iclass 27, count 2 2006.173.14:31:28.10#ibcon#end of sib2, iclass 27, count 2 2006.173.14:31:28.10#ibcon#*mode == 0, iclass 27, count 2 2006.173.14:31:28.10#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.14:31:28.10#ibcon#[27=AT07-04\r\n] 2006.173.14:31:28.10#ibcon#*before write, iclass 27, count 2 2006.173.14:31:28.10#ibcon#enter sib2, iclass 27, count 2 2006.173.14:31:28.10#ibcon#flushed, iclass 27, count 2 2006.173.14:31:28.10#ibcon#about to write, iclass 27, count 2 2006.173.14:31:28.10#ibcon#wrote, iclass 27, count 2 2006.173.14:31:28.10#ibcon#about to read 3, iclass 27, count 2 2006.173.14:31:28.13#ibcon#read 3, iclass 27, count 2 2006.173.14:31:28.13#ibcon#about to read 4, iclass 27, count 2 2006.173.14:31:28.13#ibcon#read 4, iclass 27, count 2 2006.173.14:31:28.13#ibcon#about to read 5, iclass 27, count 2 2006.173.14:31:28.13#ibcon#read 5, iclass 27, count 2 2006.173.14:31:28.13#ibcon#about to read 6, iclass 27, count 2 2006.173.14:31:28.13#ibcon#read 6, iclass 27, count 2 2006.173.14:31:28.13#ibcon#end of sib2, iclass 27, count 2 2006.173.14:31:28.13#ibcon#*after write, iclass 27, count 2 2006.173.14:31:28.13#ibcon#*before return 0, iclass 27, count 2 2006.173.14:31:28.13#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.14:31:28.13#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.14:31:28.13#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.14:31:28.13#ibcon#ireg 7 cls_cnt 0 2006.173.14:31:28.13#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.14:31:28.25#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.14:31:28.25#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.14:31:28.25#ibcon#enter wrdev, iclass 27, count 0 2006.173.14:31:28.25#ibcon#first serial, iclass 27, count 0 2006.173.14:31:28.25#ibcon#enter sib2, iclass 27, count 0 2006.173.14:31:28.25#ibcon#flushed, iclass 27, count 0 2006.173.14:31:28.25#ibcon#about to write, iclass 27, count 0 2006.173.14:31:28.25#ibcon#wrote, iclass 27, count 0 2006.173.14:31:28.25#ibcon#about to read 3, iclass 27, count 0 2006.173.14:31:28.27#ibcon#read 3, iclass 27, count 0 2006.173.14:31:28.27#ibcon#about to read 4, iclass 27, count 0 2006.173.14:31:28.27#ibcon#read 4, iclass 27, count 0 2006.173.14:31:28.27#ibcon#about to read 5, iclass 27, count 0 2006.173.14:31:28.27#ibcon#read 5, iclass 27, count 0 2006.173.14:31:28.27#ibcon#about to read 6, iclass 27, count 0 2006.173.14:31:28.27#ibcon#read 6, iclass 27, count 0 2006.173.14:31:28.27#ibcon#end of sib2, iclass 27, count 0 2006.173.14:31:28.27#ibcon#*mode == 0, iclass 27, count 0 2006.173.14:31:28.27#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.14:31:28.27#ibcon#[27=USB\r\n] 2006.173.14:31:28.27#ibcon#*before write, iclass 27, count 0 2006.173.14:31:28.27#ibcon#enter sib2, iclass 27, count 0 2006.173.14:31:28.27#ibcon#flushed, iclass 27, count 0 2006.173.14:31:28.27#ibcon#about to write, iclass 27, count 0 2006.173.14:31:28.27#ibcon#wrote, iclass 27, count 0 2006.173.14:31:28.27#ibcon#about to read 3, iclass 27, count 0 2006.173.14:31:28.30#ibcon#read 3, iclass 27, count 0 2006.173.14:31:28.30#ibcon#about to read 4, iclass 27, count 0 2006.173.14:31:28.30#ibcon#read 4, iclass 27, count 0 2006.173.14:31:28.30#ibcon#about to read 5, iclass 27, count 0 2006.173.14:31:28.30#ibcon#read 5, iclass 27, count 0 2006.173.14:31:28.30#ibcon#about to read 6, iclass 27, count 0 2006.173.14:31:28.30#ibcon#read 6, iclass 27, count 0 2006.173.14:31:28.30#ibcon#end of sib2, iclass 27, count 0 2006.173.14:31:28.30#ibcon#*after write, iclass 27, count 0 2006.173.14:31:28.30#ibcon#*before return 0, iclass 27, count 0 2006.173.14:31:28.30#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.14:31:28.30#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.14:31:28.30#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.14:31:28.30#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.14:31:28.30$vck44/vblo=8,744.99 2006.173.14:31:28.30#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.14:31:28.30#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.14:31:28.30#ibcon#ireg 17 cls_cnt 0 2006.173.14:31:28.30#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.14:31:28.30#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.14:31:28.30#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.14:31:28.30#ibcon#enter wrdev, iclass 29, count 0 2006.173.14:31:28.30#ibcon#first serial, iclass 29, count 0 2006.173.14:31:28.30#ibcon#enter sib2, iclass 29, count 0 2006.173.14:31:28.30#ibcon#flushed, iclass 29, count 0 2006.173.14:31:28.30#ibcon#about to write, iclass 29, count 0 2006.173.14:31:28.30#ibcon#wrote, iclass 29, count 0 2006.173.14:31:28.30#ibcon#about to read 3, iclass 29, count 0 2006.173.14:31:28.32#ibcon#read 3, iclass 29, count 0 2006.173.14:31:28.32#ibcon#about to read 4, iclass 29, count 0 2006.173.14:31:28.32#ibcon#read 4, iclass 29, count 0 2006.173.14:31:28.32#ibcon#about to read 5, iclass 29, count 0 2006.173.14:31:28.32#ibcon#read 5, iclass 29, count 0 2006.173.14:31:28.32#ibcon#about to read 6, iclass 29, count 0 2006.173.14:31:28.32#ibcon#read 6, iclass 29, count 0 2006.173.14:31:28.32#ibcon#end of sib2, iclass 29, count 0 2006.173.14:31:28.32#ibcon#*mode == 0, iclass 29, count 0 2006.173.14:31:28.32#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.14:31:28.32#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.14:31:28.32#ibcon#*before write, iclass 29, count 0 2006.173.14:31:28.32#ibcon#enter sib2, iclass 29, count 0 2006.173.14:31:28.32#ibcon#flushed, iclass 29, count 0 2006.173.14:31:28.32#ibcon#about to write, iclass 29, count 0 2006.173.14:31:28.32#ibcon#wrote, iclass 29, count 0 2006.173.14:31:28.32#ibcon#about to read 3, iclass 29, count 0 2006.173.14:31:28.36#ibcon#read 3, iclass 29, count 0 2006.173.14:31:28.36#ibcon#about to read 4, iclass 29, count 0 2006.173.14:31:28.36#ibcon#read 4, iclass 29, count 0 2006.173.14:31:28.36#ibcon#about to read 5, iclass 29, count 0 2006.173.14:31:28.36#ibcon#read 5, iclass 29, count 0 2006.173.14:31:28.36#ibcon#about to read 6, iclass 29, count 0 2006.173.14:31:28.36#ibcon#read 6, iclass 29, count 0 2006.173.14:31:28.36#ibcon#end of sib2, iclass 29, count 0 2006.173.14:31:28.36#ibcon#*after write, iclass 29, count 0 2006.173.14:31:28.36#ibcon#*before return 0, iclass 29, count 0 2006.173.14:31:28.36#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.14:31:28.36#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.14:31:28.36#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.14:31:28.36#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.14:31:28.36$vck44/vb=8,4 2006.173.14:31:28.36#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.14:31:28.36#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.14:31:28.36#ibcon#ireg 11 cls_cnt 2 2006.173.14:31:28.36#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.14:31:28.42#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.14:31:28.42#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.14:31:28.42#ibcon#enter wrdev, iclass 31, count 2 2006.173.14:31:28.42#ibcon#first serial, iclass 31, count 2 2006.173.14:31:28.42#ibcon#enter sib2, iclass 31, count 2 2006.173.14:31:28.42#ibcon#flushed, iclass 31, count 2 2006.173.14:31:28.42#ibcon#about to write, iclass 31, count 2 2006.173.14:31:28.42#ibcon#wrote, iclass 31, count 2 2006.173.14:31:28.42#ibcon#about to read 3, iclass 31, count 2 2006.173.14:31:28.44#ibcon#read 3, iclass 31, count 2 2006.173.14:31:28.44#ibcon#about to read 4, iclass 31, count 2 2006.173.14:31:28.44#ibcon#read 4, iclass 31, count 2 2006.173.14:31:28.44#ibcon#about to read 5, iclass 31, count 2 2006.173.14:31:28.44#ibcon#read 5, iclass 31, count 2 2006.173.14:31:28.44#ibcon#about to read 6, iclass 31, count 2 2006.173.14:31:28.44#ibcon#read 6, iclass 31, count 2 2006.173.14:31:28.44#ibcon#end of sib2, iclass 31, count 2 2006.173.14:31:28.44#ibcon#*mode == 0, iclass 31, count 2 2006.173.14:31:28.44#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.14:31:28.44#ibcon#[27=AT08-04\r\n] 2006.173.14:31:28.44#ibcon#*before write, iclass 31, count 2 2006.173.14:31:28.44#ibcon#enter sib2, iclass 31, count 2 2006.173.14:31:28.44#ibcon#flushed, iclass 31, count 2 2006.173.14:31:28.44#ibcon#about to write, iclass 31, count 2 2006.173.14:31:28.44#ibcon#wrote, iclass 31, count 2 2006.173.14:31:28.44#ibcon#about to read 3, iclass 31, count 2 2006.173.14:31:28.47#ibcon#read 3, iclass 31, count 2 2006.173.14:31:28.47#ibcon#about to read 4, iclass 31, count 2 2006.173.14:31:28.47#ibcon#read 4, iclass 31, count 2 2006.173.14:31:28.47#ibcon#about to read 5, iclass 31, count 2 2006.173.14:31:28.47#ibcon#read 5, iclass 31, count 2 2006.173.14:31:28.47#ibcon#about to read 6, iclass 31, count 2 2006.173.14:31:28.47#ibcon#read 6, iclass 31, count 2 2006.173.14:31:28.47#ibcon#end of sib2, iclass 31, count 2 2006.173.14:31:28.47#ibcon#*after write, iclass 31, count 2 2006.173.14:31:28.47#ibcon#*before return 0, iclass 31, count 2 2006.173.14:31:28.47#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.14:31:28.47#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.14:31:28.47#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.14:31:28.47#ibcon#ireg 7 cls_cnt 0 2006.173.14:31:28.47#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.14:31:28.59#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.14:31:28.59#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.14:31:28.59#ibcon#enter wrdev, iclass 31, count 0 2006.173.14:31:28.59#ibcon#first serial, iclass 31, count 0 2006.173.14:31:28.59#ibcon#enter sib2, iclass 31, count 0 2006.173.14:31:28.59#ibcon#flushed, iclass 31, count 0 2006.173.14:31:28.59#ibcon#about to write, iclass 31, count 0 2006.173.14:31:28.59#ibcon#wrote, iclass 31, count 0 2006.173.14:31:28.59#ibcon#about to read 3, iclass 31, count 0 2006.173.14:31:28.61#ibcon#read 3, iclass 31, count 0 2006.173.14:31:28.61#ibcon#about to read 4, iclass 31, count 0 2006.173.14:31:28.61#ibcon#read 4, iclass 31, count 0 2006.173.14:31:28.61#ibcon#about to read 5, iclass 31, count 0 2006.173.14:31:28.61#ibcon#read 5, iclass 31, count 0 2006.173.14:31:28.61#ibcon#about to read 6, iclass 31, count 0 2006.173.14:31:28.61#ibcon#read 6, iclass 31, count 0 2006.173.14:31:28.61#ibcon#end of sib2, iclass 31, count 0 2006.173.14:31:28.61#ibcon#*mode == 0, iclass 31, count 0 2006.173.14:31:28.61#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.14:31:28.61#ibcon#[27=USB\r\n] 2006.173.14:31:28.61#ibcon#*before write, iclass 31, count 0 2006.173.14:31:28.61#ibcon#enter sib2, iclass 31, count 0 2006.173.14:31:28.61#ibcon#flushed, iclass 31, count 0 2006.173.14:31:28.61#ibcon#about to write, iclass 31, count 0 2006.173.14:31:28.61#ibcon#wrote, iclass 31, count 0 2006.173.14:31:28.61#ibcon#about to read 3, iclass 31, count 0 2006.173.14:31:28.64#ibcon#read 3, iclass 31, count 0 2006.173.14:31:28.64#ibcon#about to read 4, iclass 31, count 0 2006.173.14:31:28.64#ibcon#read 4, iclass 31, count 0 2006.173.14:31:28.64#ibcon#about to read 5, iclass 31, count 0 2006.173.14:31:28.64#ibcon#read 5, iclass 31, count 0 2006.173.14:31:28.64#ibcon#about to read 6, iclass 31, count 0 2006.173.14:31:28.64#ibcon#read 6, iclass 31, count 0 2006.173.14:31:28.64#ibcon#end of sib2, iclass 31, count 0 2006.173.14:31:28.64#ibcon#*after write, iclass 31, count 0 2006.173.14:31:28.64#ibcon#*before return 0, iclass 31, count 0 2006.173.14:31:28.64#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.14:31:28.64#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.14:31:28.64#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.14:31:28.64#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.14:31:28.64$vck44/vabw=wide 2006.173.14:31:28.64#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.14:31:28.64#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.14:31:28.64#ibcon#ireg 8 cls_cnt 0 2006.173.14:31:28.64#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.14:31:28.64#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.14:31:28.64#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.14:31:28.64#ibcon#enter wrdev, iclass 33, count 0 2006.173.14:31:28.64#ibcon#first serial, iclass 33, count 0 2006.173.14:31:28.64#ibcon#enter sib2, iclass 33, count 0 2006.173.14:31:28.64#ibcon#flushed, iclass 33, count 0 2006.173.14:31:28.64#ibcon#about to write, iclass 33, count 0 2006.173.14:31:28.64#ibcon#wrote, iclass 33, count 0 2006.173.14:31:28.64#ibcon#about to read 3, iclass 33, count 0 2006.173.14:31:28.66#ibcon#read 3, iclass 33, count 0 2006.173.14:31:28.66#ibcon#about to read 4, iclass 33, count 0 2006.173.14:31:28.66#ibcon#read 4, iclass 33, count 0 2006.173.14:31:28.66#ibcon#about to read 5, iclass 33, count 0 2006.173.14:31:28.66#ibcon#read 5, iclass 33, count 0 2006.173.14:31:28.66#ibcon#about to read 6, iclass 33, count 0 2006.173.14:31:28.66#ibcon#read 6, iclass 33, count 0 2006.173.14:31:28.66#ibcon#end of sib2, iclass 33, count 0 2006.173.14:31:28.66#ibcon#*mode == 0, iclass 33, count 0 2006.173.14:31:28.66#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.14:31:28.66#ibcon#[25=BW32\r\n] 2006.173.14:31:28.66#ibcon#*before write, iclass 33, count 0 2006.173.14:31:28.66#ibcon#enter sib2, iclass 33, count 0 2006.173.14:31:28.66#ibcon#flushed, iclass 33, count 0 2006.173.14:31:28.66#ibcon#about to write, iclass 33, count 0 2006.173.14:31:28.66#ibcon#wrote, iclass 33, count 0 2006.173.14:31:28.66#ibcon#about to read 3, iclass 33, count 0 2006.173.14:31:28.69#ibcon#read 3, iclass 33, count 0 2006.173.14:31:28.69#ibcon#about to read 4, iclass 33, count 0 2006.173.14:31:28.69#ibcon#read 4, iclass 33, count 0 2006.173.14:31:28.69#ibcon#about to read 5, iclass 33, count 0 2006.173.14:31:28.69#ibcon#read 5, iclass 33, count 0 2006.173.14:31:28.69#ibcon#about to read 6, iclass 33, count 0 2006.173.14:31:28.69#ibcon#read 6, iclass 33, count 0 2006.173.14:31:28.69#ibcon#end of sib2, iclass 33, count 0 2006.173.14:31:28.69#ibcon#*after write, iclass 33, count 0 2006.173.14:31:28.69#ibcon#*before return 0, iclass 33, count 0 2006.173.14:31:28.69#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.14:31:28.69#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.14:31:28.69#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.14:31:28.69#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.14:31:28.69$vck44/vbbw=wide 2006.173.14:31:28.69#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.14:31:28.69#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.14:31:28.69#ibcon#ireg 8 cls_cnt 0 2006.173.14:31:28.69#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.14:31:28.76#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.14:31:28.76#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.14:31:28.76#ibcon#enter wrdev, iclass 35, count 0 2006.173.14:31:28.76#ibcon#first serial, iclass 35, count 0 2006.173.14:31:28.76#ibcon#enter sib2, iclass 35, count 0 2006.173.14:31:28.76#ibcon#flushed, iclass 35, count 0 2006.173.14:31:28.76#ibcon#about to write, iclass 35, count 0 2006.173.14:31:28.76#ibcon#wrote, iclass 35, count 0 2006.173.14:31:28.76#ibcon#about to read 3, iclass 35, count 0 2006.173.14:31:28.78#ibcon#read 3, iclass 35, count 0 2006.173.14:31:28.78#ibcon#about to read 4, iclass 35, count 0 2006.173.14:31:28.78#ibcon#read 4, iclass 35, count 0 2006.173.14:31:28.78#ibcon#about to read 5, iclass 35, count 0 2006.173.14:31:28.78#ibcon#read 5, iclass 35, count 0 2006.173.14:31:28.78#ibcon#about to read 6, iclass 35, count 0 2006.173.14:31:28.78#ibcon#read 6, iclass 35, count 0 2006.173.14:31:28.78#ibcon#end of sib2, iclass 35, count 0 2006.173.14:31:28.78#ibcon#*mode == 0, iclass 35, count 0 2006.173.14:31:28.78#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.14:31:28.78#ibcon#[27=BW32\r\n] 2006.173.14:31:28.78#ibcon#*before write, iclass 35, count 0 2006.173.14:31:28.78#ibcon#enter sib2, iclass 35, count 0 2006.173.14:31:28.78#ibcon#flushed, iclass 35, count 0 2006.173.14:31:28.78#ibcon#about to write, iclass 35, count 0 2006.173.14:31:28.78#ibcon#wrote, iclass 35, count 0 2006.173.14:31:28.78#ibcon#about to read 3, iclass 35, count 0 2006.173.14:31:28.81#ibcon#read 3, iclass 35, count 0 2006.173.14:31:28.81#ibcon#about to read 4, iclass 35, count 0 2006.173.14:31:28.81#ibcon#read 4, iclass 35, count 0 2006.173.14:31:28.81#ibcon#about to read 5, iclass 35, count 0 2006.173.14:31:28.81#ibcon#read 5, iclass 35, count 0 2006.173.14:31:28.81#ibcon#about to read 6, iclass 35, count 0 2006.173.14:31:28.81#ibcon#read 6, iclass 35, count 0 2006.173.14:31:28.81#ibcon#end of sib2, iclass 35, count 0 2006.173.14:31:28.81#ibcon#*after write, iclass 35, count 0 2006.173.14:31:28.81#ibcon#*before return 0, iclass 35, count 0 2006.173.14:31:28.81#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.14:31:28.81#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.14:31:28.81#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.14:31:28.81#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.14:31:28.81$setupk4/ifdk4 2006.173.14:31:28.81$ifdk4/lo= 2006.173.14:31:28.81$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.14:31:28.81$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.14:31:28.81$ifdk4/patch= 2006.173.14:31:28.81$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.14:31:28.81$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.14:31:28.81$setupk4/!*+20s 2006.173.14:31:34.42#abcon#<5=/14 1.5 2.9 21.431001003.8\r\n> 2006.173.14:31:34.44#abcon#{5=INTERFACE CLEAR} 2006.173.14:31:34.50#abcon#[5=S1D000X0/0*\r\n] 2006.173.14:31:42.14#trakl#Source acquired 2006.173.14:31:43.14#flagr#flagr/antenna,acquired 2006.173.14:31:43.32$setupk4/"tpicd 2006.173.14:31:43.32$setupk4/echo=off 2006.173.14:31:43.32$setupk4/xlog=off 2006.173.14:31:43.32:!2006.173.14:33:49 2006.173.14:33:49.00:preob 2006.173.14:33:50.14/onsource/TRACKING 2006.173.14:33:50.14:!2006.173.14:33:59 2006.173.14:33:59.00:"tape 2006.173.14:33:59.00:"st=record 2006.173.14:33:59.00:data_valid=on 2006.173.14:33:59.00:midob 2006.173.14:33:59.14/onsource/TRACKING 2006.173.14:33:59.14/wx/21.38,1003.9,100 2006.173.14:33:59.22/cable/+6.5065E-03 2006.173.14:34:00.31/va/01,07,usb,yes,43,46 2006.173.14:34:00.31/va/02,06,usb,yes,43,44 2006.173.14:34:00.31/va/03,05,usb,yes,54,56 2006.173.14:34:00.31/va/04,06,usb,yes,44,46 2006.173.14:34:00.31/va/05,04,usb,yes,35,35 2006.173.14:34:00.31/va/06,03,usb,yes,48,48 2006.173.14:34:00.31/va/07,04,usb,yes,39,41 2006.173.14:34:00.31/va/08,04,usb,yes,34,40 2006.173.14:34:00.54/valo/01,524.99,yes,locked 2006.173.14:34:00.54/valo/02,534.99,yes,locked 2006.173.14:34:00.54/valo/03,564.99,yes,locked 2006.173.14:34:00.54/valo/04,624.99,yes,locked 2006.173.14:34:00.54/valo/05,734.99,yes,locked 2006.173.14:34:00.54/valo/06,814.99,yes,locked 2006.173.14:34:00.54/valo/07,864.99,yes,locked 2006.173.14:34:00.54/valo/08,884.99,yes,locked 2006.173.14:34:01.63/vb/01,04,usb,yes,30,28 2006.173.14:34:01.63/vb/02,04,usb,yes,32,32 2006.173.14:34:01.63/vb/03,04,usb,yes,29,32 2006.173.14:34:01.63/vb/04,04,usb,yes,33,32 2006.173.14:34:01.63/vb/05,04,usb,yes,26,28 2006.173.14:34:01.63/vb/06,04,usb,yes,30,27 2006.173.14:34:01.63/vb/07,04,usb,yes,30,30 2006.173.14:34:01.63/vb/08,04,usb,yes,28,31 2006.173.14:34:01.87/vblo/01,629.99,yes,locked 2006.173.14:34:01.87/vblo/02,634.99,yes,locked 2006.173.14:34:01.87/vblo/03,649.99,yes,locked 2006.173.14:34:01.87/vblo/04,679.99,yes,locked 2006.173.14:34:01.87/vblo/05,709.99,yes,locked 2006.173.14:34:01.87/vblo/06,719.99,yes,locked 2006.173.14:34:01.87/vblo/07,734.99,yes,locked 2006.173.14:34:01.87/vblo/08,744.99,yes,locked 2006.173.14:34:02.02/vabw/8 2006.173.14:34:02.17/vbbw/8 2006.173.14:34:02.26/xfe/off,on,14.5 2006.173.14:34:02.63/ifatt/23,28,28,28 2006.173.14:34:03.08/fmout-gps/S +3.90E-07 2006.173.14:34:03.12:!2006.173.14:35:09 2006.173.14:35:09.00:data_valid=off 2006.173.14:35:09.00:"et 2006.173.14:35:09.00:!+3s 2006.173.14:35:12.01:"tape 2006.173.14:35:12.01:postob 2006.173.14:35:12.16/cable/+6.5065E-03 2006.173.14:35:12.16/wx/21.35,1003.9,100 2006.173.14:35:13.08/fmout-gps/S +3.90E-07 2006.173.14:35:13.08:scan_name=173-1438,jd0606,130 2006.173.14:35:13.08:source=2201+315,220314.98,314538.3,2000.0,cw 2006.173.14:35:14.14#flagr#flagr/antenna,new-source 2006.173.14:35:14.14:checkk5 2006.173.14:35:14.51/chk_autoobs//k5ts1/ autoobs is running! 2006.173.14:35:14.89/chk_autoobs//k5ts2/ autoobs is running! 2006.173.14:35:15.32/chk_autoobs//k5ts3/ autoobs is running! 2006.173.14:35:15.71/chk_autoobs//k5ts4/ autoobs is running! 2006.173.14:35:16.09/chk_obsdata//k5ts1/T1731433??a.dat file size is correct (nominal:280MB, actual:276MB). 2006.173.14:35:16.49/chk_obsdata//k5ts2/T1731433??b.dat file size is correct (nominal:280MB, actual:276MB). 2006.173.14:35:16.90/chk_obsdata//k5ts3/T1731433??c.dat file size is correct (nominal:280MB, actual:276MB). 2006.173.14:35:17.30/chk_obsdata//k5ts4/T1731433??d.dat file size is correct (nominal:280MB, actual:276MB). 2006.173.14:35:18.03/k5log//k5ts1_log_newline 2006.173.14:35:18.73/k5log//k5ts2_log_newline 2006.173.14:35:19.44/k5log//k5ts3_log_newline 2006.173.14:35:20.15/k5log//k5ts4_log_newline 2006.173.14:35:20.17/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.14:35:20.17:setupk4=1 2006.173.14:35:20.17$setupk4/echo=on 2006.173.14:35:20.17$setupk4/pcalon 2006.173.14:35:20.17$pcalon/"no phase cal control is implemented here 2006.173.14:35:20.17$setupk4/"tpicd=stop 2006.173.14:35:20.17$setupk4/"rec=synch_on 2006.173.14:35:20.17$setupk4/"rec_mode=128 2006.173.14:35:20.17$setupk4/!* 2006.173.14:35:20.17$setupk4/recpk4 2006.173.14:35:20.17$recpk4/recpatch= 2006.173.14:35:20.18$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.14:35:20.18$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.14:35:20.18$setupk4/vck44 2006.173.14:35:20.18$vck44/valo=1,524.99 2006.173.14:35:20.18#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.14:35:20.18#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.14:35:20.18#ibcon#ireg 17 cls_cnt 0 2006.173.14:35:20.18#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.14:35:20.18#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.14:35:20.18#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.14:35:20.18#ibcon#enter wrdev, iclass 24, count 0 2006.173.14:35:20.18#ibcon#first serial, iclass 24, count 0 2006.173.14:35:20.18#ibcon#enter sib2, iclass 24, count 0 2006.173.14:35:20.18#ibcon#flushed, iclass 24, count 0 2006.173.14:35:20.18#ibcon#about to write, iclass 24, count 0 2006.173.14:35:20.18#ibcon#wrote, iclass 24, count 0 2006.173.14:35:20.18#ibcon#about to read 3, iclass 24, count 0 2006.173.14:35:20.19#ibcon#read 3, iclass 24, count 0 2006.173.14:35:20.19#ibcon#about to read 4, iclass 24, count 0 2006.173.14:35:20.19#ibcon#read 4, iclass 24, count 0 2006.173.14:35:20.19#ibcon#about to read 5, iclass 24, count 0 2006.173.14:35:20.19#ibcon#read 5, iclass 24, count 0 2006.173.14:35:20.19#ibcon#about to read 6, iclass 24, count 0 2006.173.14:35:20.19#ibcon#read 6, iclass 24, count 0 2006.173.14:35:20.19#ibcon#end of sib2, iclass 24, count 0 2006.173.14:35:20.19#ibcon#*mode == 0, iclass 24, count 0 2006.173.14:35:20.19#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.14:35:20.19#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.14:35:20.19#ibcon#*before write, iclass 24, count 0 2006.173.14:35:20.19#ibcon#enter sib2, iclass 24, count 0 2006.173.14:35:20.19#ibcon#flushed, iclass 24, count 0 2006.173.14:35:20.19#ibcon#about to write, iclass 24, count 0 2006.173.14:35:20.19#ibcon#wrote, iclass 24, count 0 2006.173.14:35:20.19#ibcon#about to read 3, iclass 24, count 0 2006.173.14:35:20.24#ibcon#read 3, iclass 24, count 0 2006.173.14:35:20.24#ibcon#about to read 4, iclass 24, count 0 2006.173.14:35:20.24#ibcon#read 4, iclass 24, count 0 2006.173.14:35:20.24#ibcon#about to read 5, iclass 24, count 0 2006.173.14:35:20.24#ibcon#read 5, iclass 24, count 0 2006.173.14:35:20.24#ibcon#about to read 6, iclass 24, count 0 2006.173.14:35:20.24#ibcon#read 6, iclass 24, count 0 2006.173.14:35:20.24#ibcon#end of sib2, iclass 24, count 0 2006.173.14:35:20.24#ibcon#*after write, iclass 24, count 0 2006.173.14:35:20.24#ibcon#*before return 0, iclass 24, count 0 2006.173.14:35:20.24#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.14:35:20.24#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.14:35:20.24#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.14:35:20.24#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.14:35:20.24$vck44/va=1,7 2006.173.14:35:20.24#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.14:35:20.24#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.14:35:20.24#ibcon#ireg 11 cls_cnt 2 2006.173.14:35:20.24#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.14:35:20.24#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.14:35:20.24#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.14:35:20.24#ibcon#enter wrdev, iclass 26, count 2 2006.173.14:35:20.24#ibcon#first serial, iclass 26, count 2 2006.173.14:35:20.24#ibcon#enter sib2, iclass 26, count 2 2006.173.14:35:20.24#ibcon#flushed, iclass 26, count 2 2006.173.14:35:20.24#ibcon#about to write, iclass 26, count 2 2006.173.14:35:20.24#ibcon#wrote, iclass 26, count 2 2006.173.14:35:20.24#ibcon#about to read 3, iclass 26, count 2 2006.173.14:35:20.26#ibcon#read 3, iclass 26, count 2 2006.173.14:35:20.26#ibcon#about to read 4, iclass 26, count 2 2006.173.14:35:20.26#ibcon#read 4, iclass 26, count 2 2006.173.14:35:20.26#ibcon#about to read 5, iclass 26, count 2 2006.173.14:35:20.26#ibcon#read 5, iclass 26, count 2 2006.173.14:35:20.26#ibcon#about to read 6, iclass 26, count 2 2006.173.14:35:20.26#ibcon#read 6, iclass 26, count 2 2006.173.14:35:20.26#ibcon#end of sib2, iclass 26, count 2 2006.173.14:35:20.26#ibcon#*mode == 0, iclass 26, count 2 2006.173.14:35:20.26#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.14:35:20.26#ibcon#[25=AT01-07\r\n] 2006.173.14:35:20.26#ibcon#*before write, iclass 26, count 2 2006.173.14:35:20.26#ibcon#enter sib2, iclass 26, count 2 2006.173.14:35:20.26#ibcon#flushed, iclass 26, count 2 2006.173.14:35:20.26#ibcon#about to write, iclass 26, count 2 2006.173.14:35:20.26#ibcon#wrote, iclass 26, count 2 2006.173.14:35:20.26#ibcon#about to read 3, iclass 26, count 2 2006.173.14:35:20.29#ibcon#read 3, iclass 26, count 2 2006.173.14:35:20.29#ibcon#about to read 4, iclass 26, count 2 2006.173.14:35:20.29#ibcon#read 4, iclass 26, count 2 2006.173.14:35:20.29#ibcon#about to read 5, iclass 26, count 2 2006.173.14:35:20.29#ibcon#read 5, iclass 26, count 2 2006.173.14:35:20.29#ibcon#about to read 6, iclass 26, count 2 2006.173.14:35:20.29#ibcon#read 6, iclass 26, count 2 2006.173.14:35:20.29#ibcon#end of sib2, iclass 26, count 2 2006.173.14:35:20.29#ibcon#*after write, iclass 26, count 2 2006.173.14:35:20.29#ibcon#*before return 0, iclass 26, count 2 2006.173.14:35:20.29#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.14:35:20.29#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.14:35:20.29#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.14:35:20.29#ibcon#ireg 7 cls_cnt 0 2006.173.14:35:20.29#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.14:35:20.41#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.14:35:20.41#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.14:35:20.41#ibcon#enter wrdev, iclass 26, count 0 2006.173.14:35:20.41#ibcon#first serial, iclass 26, count 0 2006.173.14:35:20.41#ibcon#enter sib2, iclass 26, count 0 2006.173.14:35:20.41#ibcon#flushed, iclass 26, count 0 2006.173.14:35:20.41#ibcon#about to write, iclass 26, count 0 2006.173.14:35:20.41#ibcon#wrote, iclass 26, count 0 2006.173.14:35:20.41#ibcon#about to read 3, iclass 26, count 0 2006.173.14:35:20.43#ibcon#read 3, iclass 26, count 0 2006.173.14:35:20.43#ibcon#about to read 4, iclass 26, count 0 2006.173.14:35:20.43#ibcon#read 4, iclass 26, count 0 2006.173.14:35:20.43#ibcon#about to read 5, iclass 26, count 0 2006.173.14:35:20.43#ibcon#read 5, iclass 26, count 0 2006.173.14:35:20.43#ibcon#about to read 6, iclass 26, count 0 2006.173.14:35:20.43#ibcon#read 6, iclass 26, count 0 2006.173.14:35:20.43#ibcon#end of sib2, iclass 26, count 0 2006.173.14:35:20.43#ibcon#*mode == 0, iclass 26, count 0 2006.173.14:35:20.43#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.14:35:20.43#ibcon#[25=USB\r\n] 2006.173.14:35:20.43#ibcon#*before write, iclass 26, count 0 2006.173.14:35:20.43#ibcon#enter sib2, iclass 26, count 0 2006.173.14:35:20.43#ibcon#flushed, iclass 26, count 0 2006.173.14:35:20.43#ibcon#about to write, iclass 26, count 0 2006.173.14:35:20.43#ibcon#wrote, iclass 26, count 0 2006.173.14:35:20.43#ibcon#about to read 3, iclass 26, count 0 2006.173.14:35:20.46#ibcon#read 3, iclass 26, count 0 2006.173.14:35:20.46#ibcon#about to read 4, iclass 26, count 0 2006.173.14:35:20.46#ibcon#read 4, iclass 26, count 0 2006.173.14:35:20.46#ibcon#about to read 5, iclass 26, count 0 2006.173.14:35:20.46#ibcon#read 5, iclass 26, count 0 2006.173.14:35:20.46#ibcon#about to read 6, iclass 26, count 0 2006.173.14:35:20.46#ibcon#read 6, iclass 26, count 0 2006.173.14:35:20.46#ibcon#end of sib2, iclass 26, count 0 2006.173.14:35:20.46#ibcon#*after write, iclass 26, count 0 2006.173.14:35:20.46#ibcon#*before return 0, iclass 26, count 0 2006.173.14:35:20.46#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.14:35:20.46#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.14:35:20.46#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.14:35:20.46#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.14:35:20.46$vck44/valo=2,534.99 2006.173.14:35:20.46#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.14:35:20.46#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.14:35:20.46#ibcon#ireg 17 cls_cnt 0 2006.173.14:35:20.46#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.14:35:20.46#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.14:35:20.46#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.14:35:20.46#ibcon#enter wrdev, iclass 28, count 0 2006.173.14:35:20.46#ibcon#first serial, iclass 28, count 0 2006.173.14:35:20.46#ibcon#enter sib2, iclass 28, count 0 2006.173.14:35:20.46#ibcon#flushed, iclass 28, count 0 2006.173.14:35:20.46#ibcon#about to write, iclass 28, count 0 2006.173.14:35:20.46#ibcon#wrote, iclass 28, count 0 2006.173.14:35:20.46#ibcon#about to read 3, iclass 28, count 0 2006.173.14:35:20.48#ibcon#read 3, iclass 28, count 0 2006.173.14:35:20.48#ibcon#about to read 4, iclass 28, count 0 2006.173.14:35:20.48#ibcon#read 4, iclass 28, count 0 2006.173.14:35:20.48#ibcon#about to read 5, iclass 28, count 0 2006.173.14:35:20.48#ibcon#read 5, iclass 28, count 0 2006.173.14:35:20.48#ibcon#about to read 6, iclass 28, count 0 2006.173.14:35:20.48#ibcon#read 6, iclass 28, count 0 2006.173.14:35:20.48#ibcon#end of sib2, iclass 28, count 0 2006.173.14:35:20.48#ibcon#*mode == 0, iclass 28, count 0 2006.173.14:35:20.48#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.14:35:20.48#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.14:35:20.48#ibcon#*before write, iclass 28, count 0 2006.173.14:35:20.48#ibcon#enter sib2, iclass 28, count 0 2006.173.14:35:20.48#ibcon#flushed, iclass 28, count 0 2006.173.14:35:20.48#ibcon#about to write, iclass 28, count 0 2006.173.14:35:20.48#ibcon#wrote, iclass 28, count 0 2006.173.14:35:20.48#ibcon#about to read 3, iclass 28, count 0 2006.173.14:35:20.52#ibcon#read 3, iclass 28, count 0 2006.173.14:35:20.52#ibcon#about to read 4, iclass 28, count 0 2006.173.14:35:20.52#ibcon#read 4, iclass 28, count 0 2006.173.14:35:20.52#ibcon#about to read 5, iclass 28, count 0 2006.173.14:35:20.52#ibcon#read 5, iclass 28, count 0 2006.173.14:35:20.52#ibcon#about to read 6, iclass 28, count 0 2006.173.14:35:20.52#ibcon#read 6, iclass 28, count 0 2006.173.14:35:20.52#ibcon#end of sib2, iclass 28, count 0 2006.173.14:35:20.52#ibcon#*after write, iclass 28, count 0 2006.173.14:35:20.52#ibcon#*before return 0, iclass 28, count 0 2006.173.14:35:20.52#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.14:35:20.52#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.14:35:20.52#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.14:35:20.52#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.14:35:20.52$vck44/va=2,6 2006.173.14:35:20.52#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.14:35:20.52#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.14:35:20.52#ibcon#ireg 11 cls_cnt 2 2006.173.14:35:20.52#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.14:35:20.58#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.14:35:20.58#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.14:35:20.58#ibcon#enter wrdev, iclass 30, count 2 2006.173.14:35:20.58#ibcon#first serial, iclass 30, count 2 2006.173.14:35:20.58#ibcon#enter sib2, iclass 30, count 2 2006.173.14:35:20.58#ibcon#flushed, iclass 30, count 2 2006.173.14:35:20.58#ibcon#about to write, iclass 30, count 2 2006.173.14:35:20.58#ibcon#wrote, iclass 30, count 2 2006.173.14:35:20.58#ibcon#about to read 3, iclass 30, count 2 2006.173.14:35:20.60#ibcon#read 3, iclass 30, count 2 2006.173.14:35:20.60#ibcon#about to read 4, iclass 30, count 2 2006.173.14:35:20.60#ibcon#read 4, iclass 30, count 2 2006.173.14:35:20.60#ibcon#about to read 5, iclass 30, count 2 2006.173.14:35:20.60#ibcon#read 5, iclass 30, count 2 2006.173.14:35:20.60#ibcon#about to read 6, iclass 30, count 2 2006.173.14:35:20.60#ibcon#read 6, iclass 30, count 2 2006.173.14:35:20.60#ibcon#end of sib2, iclass 30, count 2 2006.173.14:35:20.60#ibcon#*mode == 0, iclass 30, count 2 2006.173.14:35:20.60#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.14:35:20.60#ibcon#[25=AT02-06\r\n] 2006.173.14:35:20.60#ibcon#*before write, iclass 30, count 2 2006.173.14:35:20.60#ibcon#enter sib2, iclass 30, count 2 2006.173.14:35:20.60#ibcon#flushed, iclass 30, count 2 2006.173.14:35:20.60#ibcon#about to write, iclass 30, count 2 2006.173.14:35:20.60#ibcon#wrote, iclass 30, count 2 2006.173.14:35:20.60#ibcon#about to read 3, iclass 30, count 2 2006.173.14:35:20.63#ibcon#read 3, iclass 30, count 2 2006.173.14:35:20.63#ibcon#about to read 4, iclass 30, count 2 2006.173.14:35:20.63#ibcon#read 4, iclass 30, count 2 2006.173.14:35:20.63#ibcon#about to read 5, iclass 30, count 2 2006.173.14:35:20.63#ibcon#read 5, iclass 30, count 2 2006.173.14:35:20.63#ibcon#about to read 6, iclass 30, count 2 2006.173.14:35:20.63#ibcon#read 6, iclass 30, count 2 2006.173.14:35:20.63#ibcon#end of sib2, iclass 30, count 2 2006.173.14:35:20.63#ibcon#*after write, iclass 30, count 2 2006.173.14:35:20.63#ibcon#*before return 0, iclass 30, count 2 2006.173.14:35:20.63#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.14:35:20.63#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.14:35:20.63#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.14:35:20.63#ibcon#ireg 7 cls_cnt 0 2006.173.14:35:20.63#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.14:35:20.75#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.14:35:20.75#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.14:35:20.75#ibcon#enter wrdev, iclass 30, count 0 2006.173.14:35:20.75#ibcon#first serial, iclass 30, count 0 2006.173.14:35:20.75#ibcon#enter sib2, iclass 30, count 0 2006.173.14:35:20.75#ibcon#flushed, iclass 30, count 0 2006.173.14:35:20.75#ibcon#about to write, iclass 30, count 0 2006.173.14:35:20.75#ibcon#wrote, iclass 30, count 0 2006.173.14:35:20.75#ibcon#about to read 3, iclass 30, count 0 2006.173.14:35:20.77#ibcon#read 3, iclass 30, count 0 2006.173.14:35:20.77#ibcon#about to read 4, iclass 30, count 0 2006.173.14:35:20.77#ibcon#read 4, iclass 30, count 0 2006.173.14:35:20.77#ibcon#about to read 5, iclass 30, count 0 2006.173.14:35:20.77#ibcon#read 5, iclass 30, count 0 2006.173.14:35:20.77#ibcon#about to read 6, iclass 30, count 0 2006.173.14:35:20.77#ibcon#read 6, iclass 30, count 0 2006.173.14:35:20.77#ibcon#end of sib2, iclass 30, count 0 2006.173.14:35:20.77#ibcon#*mode == 0, iclass 30, count 0 2006.173.14:35:20.77#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.14:35:20.77#ibcon#[25=USB\r\n] 2006.173.14:35:20.77#ibcon#*before write, iclass 30, count 0 2006.173.14:35:20.77#ibcon#enter sib2, iclass 30, count 0 2006.173.14:35:20.77#ibcon#flushed, iclass 30, count 0 2006.173.14:35:20.77#ibcon#about to write, iclass 30, count 0 2006.173.14:35:20.77#ibcon#wrote, iclass 30, count 0 2006.173.14:35:20.77#ibcon#about to read 3, iclass 30, count 0 2006.173.14:35:20.80#ibcon#read 3, iclass 30, count 0 2006.173.14:35:20.80#ibcon#about to read 4, iclass 30, count 0 2006.173.14:35:20.80#ibcon#read 4, iclass 30, count 0 2006.173.14:35:20.80#ibcon#about to read 5, iclass 30, count 0 2006.173.14:35:20.80#ibcon#read 5, iclass 30, count 0 2006.173.14:35:20.80#ibcon#about to read 6, iclass 30, count 0 2006.173.14:35:20.80#ibcon#read 6, iclass 30, count 0 2006.173.14:35:20.80#ibcon#end of sib2, iclass 30, count 0 2006.173.14:35:20.80#ibcon#*after write, iclass 30, count 0 2006.173.14:35:20.80#ibcon#*before return 0, iclass 30, count 0 2006.173.14:35:20.80#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.14:35:20.80#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.14:35:20.80#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.14:35:20.80#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.14:35:20.80$vck44/valo=3,564.99 2006.173.14:35:20.80#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.14:35:20.80#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.14:35:20.80#ibcon#ireg 17 cls_cnt 0 2006.173.14:35:20.80#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.14:35:20.80#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.14:35:20.80#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.14:35:20.80#ibcon#enter wrdev, iclass 32, count 0 2006.173.14:35:20.80#ibcon#first serial, iclass 32, count 0 2006.173.14:35:20.80#ibcon#enter sib2, iclass 32, count 0 2006.173.14:35:20.80#ibcon#flushed, iclass 32, count 0 2006.173.14:35:20.80#ibcon#about to write, iclass 32, count 0 2006.173.14:35:20.80#ibcon#wrote, iclass 32, count 0 2006.173.14:35:20.80#ibcon#about to read 3, iclass 32, count 0 2006.173.14:35:20.82#ibcon#read 3, iclass 32, count 0 2006.173.14:35:20.82#ibcon#about to read 4, iclass 32, count 0 2006.173.14:35:20.82#ibcon#read 4, iclass 32, count 0 2006.173.14:35:20.82#ibcon#about to read 5, iclass 32, count 0 2006.173.14:35:20.82#ibcon#read 5, iclass 32, count 0 2006.173.14:35:20.82#ibcon#about to read 6, iclass 32, count 0 2006.173.14:35:20.82#ibcon#read 6, iclass 32, count 0 2006.173.14:35:20.82#ibcon#end of sib2, iclass 32, count 0 2006.173.14:35:20.82#ibcon#*mode == 0, iclass 32, count 0 2006.173.14:35:20.82#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.14:35:20.82#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.14:35:20.82#ibcon#*before write, iclass 32, count 0 2006.173.14:35:20.82#ibcon#enter sib2, iclass 32, count 0 2006.173.14:35:20.82#ibcon#flushed, iclass 32, count 0 2006.173.14:35:20.82#ibcon#about to write, iclass 32, count 0 2006.173.14:35:20.82#ibcon#wrote, iclass 32, count 0 2006.173.14:35:20.82#ibcon#about to read 3, iclass 32, count 0 2006.173.14:35:20.86#ibcon#read 3, iclass 32, count 0 2006.173.14:35:20.86#ibcon#about to read 4, iclass 32, count 0 2006.173.14:35:20.86#ibcon#read 4, iclass 32, count 0 2006.173.14:35:20.86#ibcon#about to read 5, iclass 32, count 0 2006.173.14:35:20.86#ibcon#read 5, iclass 32, count 0 2006.173.14:35:20.86#ibcon#about to read 6, iclass 32, count 0 2006.173.14:35:20.86#ibcon#read 6, iclass 32, count 0 2006.173.14:35:20.86#ibcon#end of sib2, iclass 32, count 0 2006.173.14:35:20.86#ibcon#*after write, iclass 32, count 0 2006.173.14:35:20.86#ibcon#*before return 0, iclass 32, count 0 2006.173.14:35:20.86#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.14:35:20.86#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.14:35:20.86#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.14:35:20.86#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.14:35:20.86$vck44/va=3,5 2006.173.14:35:20.86#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.14:35:20.86#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.14:35:20.86#ibcon#ireg 11 cls_cnt 2 2006.173.14:35:20.86#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.14:35:20.92#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.14:35:20.92#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.14:35:20.92#ibcon#enter wrdev, iclass 34, count 2 2006.173.14:35:20.92#ibcon#first serial, iclass 34, count 2 2006.173.14:35:20.92#ibcon#enter sib2, iclass 34, count 2 2006.173.14:35:20.92#ibcon#flushed, iclass 34, count 2 2006.173.14:35:20.92#ibcon#about to write, iclass 34, count 2 2006.173.14:35:20.92#ibcon#wrote, iclass 34, count 2 2006.173.14:35:20.92#ibcon#about to read 3, iclass 34, count 2 2006.173.14:35:20.94#ibcon#read 3, iclass 34, count 2 2006.173.14:35:20.94#ibcon#about to read 4, iclass 34, count 2 2006.173.14:35:20.94#ibcon#read 4, iclass 34, count 2 2006.173.14:35:20.94#ibcon#about to read 5, iclass 34, count 2 2006.173.14:35:20.94#ibcon#read 5, iclass 34, count 2 2006.173.14:35:20.94#ibcon#about to read 6, iclass 34, count 2 2006.173.14:35:20.94#ibcon#read 6, iclass 34, count 2 2006.173.14:35:20.94#ibcon#end of sib2, iclass 34, count 2 2006.173.14:35:20.94#ibcon#*mode == 0, iclass 34, count 2 2006.173.14:35:20.94#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.14:35:20.94#ibcon#[25=AT03-05\r\n] 2006.173.14:35:20.94#ibcon#*before write, iclass 34, count 2 2006.173.14:35:20.94#ibcon#enter sib2, iclass 34, count 2 2006.173.14:35:20.94#ibcon#flushed, iclass 34, count 2 2006.173.14:35:20.94#ibcon#about to write, iclass 34, count 2 2006.173.14:35:20.94#ibcon#wrote, iclass 34, count 2 2006.173.14:35:20.94#ibcon#about to read 3, iclass 34, count 2 2006.173.14:35:20.97#ibcon#read 3, iclass 34, count 2 2006.173.14:35:20.97#ibcon#about to read 4, iclass 34, count 2 2006.173.14:35:20.97#ibcon#read 4, iclass 34, count 2 2006.173.14:35:20.97#ibcon#about to read 5, iclass 34, count 2 2006.173.14:35:20.97#ibcon#read 5, iclass 34, count 2 2006.173.14:35:20.97#ibcon#about to read 6, iclass 34, count 2 2006.173.14:35:20.97#ibcon#read 6, iclass 34, count 2 2006.173.14:35:20.97#ibcon#end of sib2, iclass 34, count 2 2006.173.14:35:20.97#ibcon#*after write, iclass 34, count 2 2006.173.14:35:20.97#ibcon#*before return 0, iclass 34, count 2 2006.173.14:35:20.97#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.14:35:20.97#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.14:35:20.97#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.14:35:20.97#ibcon#ireg 7 cls_cnt 0 2006.173.14:35:20.97#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.14:35:21.09#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.14:35:21.09#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.14:35:21.09#ibcon#enter wrdev, iclass 34, count 0 2006.173.14:35:21.09#ibcon#first serial, iclass 34, count 0 2006.173.14:35:21.09#ibcon#enter sib2, iclass 34, count 0 2006.173.14:35:21.09#ibcon#flushed, iclass 34, count 0 2006.173.14:35:21.09#ibcon#about to write, iclass 34, count 0 2006.173.14:35:21.09#ibcon#wrote, iclass 34, count 0 2006.173.14:35:21.09#ibcon#about to read 3, iclass 34, count 0 2006.173.14:35:21.11#ibcon#read 3, iclass 34, count 0 2006.173.14:35:21.11#ibcon#about to read 4, iclass 34, count 0 2006.173.14:35:21.11#ibcon#read 4, iclass 34, count 0 2006.173.14:35:21.11#ibcon#about to read 5, iclass 34, count 0 2006.173.14:35:21.11#ibcon#read 5, iclass 34, count 0 2006.173.14:35:21.11#ibcon#about to read 6, iclass 34, count 0 2006.173.14:35:21.11#ibcon#read 6, iclass 34, count 0 2006.173.14:35:21.11#ibcon#end of sib2, iclass 34, count 0 2006.173.14:35:21.11#ibcon#*mode == 0, iclass 34, count 0 2006.173.14:35:21.11#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.14:35:21.11#ibcon#[25=USB\r\n] 2006.173.14:35:21.11#ibcon#*before write, iclass 34, count 0 2006.173.14:35:21.11#ibcon#enter sib2, iclass 34, count 0 2006.173.14:35:21.11#ibcon#flushed, iclass 34, count 0 2006.173.14:35:21.11#ibcon#about to write, iclass 34, count 0 2006.173.14:35:21.11#ibcon#wrote, iclass 34, count 0 2006.173.14:35:21.11#ibcon#about to read 3, iclass 34, count 0 2006.173.14:35:21.14#ibcon#read 3, iclass 34, count 0 2006.173.14:35:21.14#ibcon#about to read 4, iclass 34, count 0 2006.173.14:35:21.14#ibcon#read 4, iclass 34, count 0 2006.173.14:35:21.14#ibcon#about to read 5, iclass 34, count 0 2006.173.14:35:21.14#ibcon#read 5, iclass 34, count 0 2006.173.14:35:21.14#ibcon#about to read 6, iclass 34, count 0 2006.173.14:35:21.14#ibcon#read 6, iclass 34, count 0 2006.173.14:35:21.14#ibcon#end of sib2, iclass 34, count 0 2006.173.14:35:21.14#ibcon#*after write, iclass 34, count 0 2006.173.14:35:21.14#ibcon#*before return 0, iclass 34, count 0 2006.173.14:35:21.14#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.14:35:21.14#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.14:35:21.14#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.14:35:21.14#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.14:35:21.14$vck44/valo=4,624.99 2006.173.14:35:21.14#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.14:35:21.14#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.14:35:21.14#ibcon#ireg 17 cls_cnt 0 2006.173.14:35:21.14#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.14:35:21.14#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.14:35:21.14#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.14:35:21.14#ibcon#enter wrdev, iclass 36, count 0 2006.173.14:35:21.14#ibcon#first serial, iclass 36, count 0 2006.173.14:35:21.14#ibcon#enter sib2, iclass 36, count 0 2006.173.14:35:21.14#ibcon#flushed, iclass 36, count 0 2006.173.14:35:21.14#ibcon#about to write, iclass 36, count 0 2006.173.14:35:21.14#ibcon#wrote, iclass 36, count 0 2006.173.14:35:21.14#ibcon#about to read 3, iclass 36, count 0 2006.173.14:35:21.16#ibcon#read 3, iclass 36, count 0 2006.173.14:35:21.16#ibcon#about to read 4, iclass 36, count 0 2006.173.14:35:21.16#ibcon#read 4, iclass 36, count 0 2006.173.14:35:21.16#ibcon#about to read 5, iclass 36, count 0 2006.173.14:35:21.16#ibcon#read 5, iclass 36, count 0 2006.173.14:35:21.16#ibcon#about to read 6, iclass 36, count 0 2006.173.14:35:21.16#ibcon#read 6, iclass 36, count 0 2006.173.14:35:21.16#ibcon#end of sib2, iclass 36, count 0 2006.173.14:35:21.16#ibcon#*mode == 0, iclass 36, count 0 2006.173.14:35:21.16#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.14:35:21.16#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.14:35:21.16#ibcon#*before write, iclass 36, count 0 2006.173.14:35:21.16#ibcon#enter sib2, iclass 36, count 0 2006.173.14:35:21.16#ibcon#flushed, iclass 36, count 0 2006.173.14:35:21.16#ibcon#about to write, iclass 36, count 0 2006.173.14:35:21.16#ibcon#wrote, iclass 36, count 0 2006.173.14:35:21.16#ibcon#about to read 3, iclass 36, count 0 2006.173.14:35:21.20#ibcon#read 3, iclass 36, count 0 2006.173.14:35:21.20#ibcon#about to read 4, iclass 36, count 0 2006.173.14:35:21.20#ibcon#read 4, iclass 36, count 0 2006.173.14:35:21.20#ibcon#about to read 5, iclass 36, count 0 2006.173.14:35:21.20#ibcon#read 5, iclass 36, count 0 2006.173.14:35:21.20#ibcon#about to read 6, iclass 36, count 0 2006.173.14:35:21.20#ibcon#read 6, iclass 36, count 0 2006.173.14:35:21.20#ibcon#end of sib2, iclass 36, count 0 2006.173.14:35:21.20#ibcon#*after write, iclass 36, count 0 2006.173.14:35:21.20#ibcon#*before return 0, iclass 36, count 0 2006.173.14:35:21.20#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.14:35:21.20#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.14:35:21.20#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.14:35:21.20#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.14:35:21.20$vck44/va=4,6 2006.173.14:35:21.20#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.14:35:21.20#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.14:35:21.20#ibcon#ireg 11 cls_cnt 2 2006.173.14:35:21.20#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.14:35:21.26#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.14:35:21.26#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.14:35:21.26#ibcon#enter wrdev, iclass 38, count 2 2006.173.14:35:21.26#ibcon#first serial, iclass 38, count 2 2006.173.14:35:21.26#ibcon#enter sib2, iclass 38, count 2 2006.173.14:35:21.26#ibcon#flushed, iclass 38, count 2 2006.173.14:35:21.26#ibcon#about to write, iclass 38, count 2 2006.173.14:35:21.26#ibcon#wrote, iclass 38, count 2 2006.173.14:35:21.26#ibcon#about to read 3, iclass 38, count 2 2006.173.14:35:21.28#ibcon#read 3, iclass 38, count 2 2006.173.14:35:21.28#ibcon#about to read 4, iclass 38, count 2 2006.173.14:35:21.28#ibcon#read 4, iclass 38, count 2 2006.173.14:35:21.28#ibcon#about to read 5, iclass 38, count 2 2006.173.14:35:21.28#ibcon#read 5, iclass 38, count 2 2006.173.14:35:21.28#ibcon#about to read 6, iclass 38, count 2 2006.173.14:35:21.28#ibcon#read 6, iclass 38, count 2 2006.173.14:35:21.28#ibcon#end of sib2, iclass 38, count 2 2006.173.14:35:21.28#ibcon#*mode == 0, iclass 38, count 2 2006.173.14:35:21.28#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.14:35:21.28#ibcon#[25=AT04-06\r\n] 2006.173.14:35:21.28#ibcon#*before write, iclass 38, count 2 2006.173.14:35:21.28#ibcon#enter sib2, iclass 38, count 2 2006.173.14:35:21.28#ibcon#flushed, iclass 38, count 2 2006.173.14:35:21.28#ibcon#about to write, iclass 38, count 2 2006.173.14:35:21.28#ibcon#wrote, iclass 38, count 2 2006.173.14:35:21.28#ibcon#about to read 3, iclass 38, count 2 2006.173.14:35:21.31#ibcon#read 3, iclass 38, count 2 2006.173.14:35:21.31#ibcon#about to read 4, iclass 38, count 2 2006.173.14:35:21.31#ibcon#read 4, iclass 38, count 2 2006.173.14:35:21.31#ibcon#about to read 5, iclass 38, count 2 2006.173.14:35:21.31#ibcon#read 5, iclass 38, count 2 2006.173.14:35:21.31#ibcon#about to read 6, iclass 38, count 2 2006.173.14:35:21.31#ibcon#read 6, iclass 38, count 2 2006.173.14:35:21.31#ibcon#end of sib2, iclass 38, count 2 2006.173.14:35:21.31#ibcon#*after write, iclass 38, count 2 2006.173.14:35:21.31#ibcon#*before return 0, iclass 38, count 2 2006.173.14:35:21.31#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.14:35:21.31#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.14:35:21.31#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.14:35:21.31#ibcon#ireg 7 cls_cnt 0 2006.173.14:35:21.31#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.14:35:21.43#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.14:35:21.43#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.14:35:21.43#ibcon#enter wrdev, iclass 38, count 0 2006.173.14:35:21.43#ibcon#first serial, iclass 38, count 0 2006.173.14:35:21.43#ibcon#enter sib2, iclass 38, count 0 2006.173.14:35:21.43#ibcon#flushed, iclass 38, count 0 2006.173.14:35:21.43#ibcon#about to write, iclass 38, count 0 2006.173.14:35:21.43#ibcon#wrote, iclass 38, count 0 2006.173.14:35:21.43#ibcon#about to read 3, iclass 38, count 0 2006.173.14:35:21.45#ibcon#read 3, iclass 38, count 0 2006.173.14:35:21.45#ibcon#about to read 4, iclass 38, count 0 2006.173.14:35:21.45#ibcon#read 4, iclass 38, count 0 2006.173.14:35:21.45#ibcon#about to read 5, iclass 38, count 0 2006.173.14:35:21.45#ibcon#read 5, iclass 38, count 0 2006.173.14:35:21.45#ibcon#about to read 6, iclass 38, count 0 2006.173.14:35:21.45#ibcon#read 6, iclass 38, count 0 2006.173.14:35:21.45#ibcon#end of sib2, iclass 38, count 0 2006.173.14:35:21.45#ibcon#*mode == 0, iclass 38, count 0 2006.173.14:35:21.45#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.14:35:21.45#ibcon#[25=USB\r\n] 2006.173.14:35:21.45#ibcon#*before write, iclass 38, count 0 2006.173.14:35:21.45#ibcon#enter sib2, iclass 38, count 0 2006.173.14:35:21.45#ibcon#flushed, iclass 38, count 0 2006.173.14:35:21.45#ibcon#about to write, iclass 38, count 0 2006.173.14:35:21.45#ibcon#wrote, iclass 38, count 0 2006.173.14:35:21.45#ibcon#about to read 3, iclass 38, count 0 2006.173.14:35:21.48#ibcon#read 3, iclass 38, count 0 2006.173.14:35:21.48#ibcon#about to read 4, iclass 38, count 0 2006.173.14:35:21.48#ibcon#read 4, iclass 38, count 0 2006.173.14:35:21.48#ibcon#about to read 5, iclass 38, count 0 2006.173.14:35:21.48#ibcon#read 5, iclass 38, count 0 2006.173.14:35:21.48#ibcon#about to read 6, iclass 38, count 0 2006.173.14:35:21.48#ibcon#read 6, iclass 38, count 0 2006.173.14:35:21.48#ibcon#end of sib2, iclass 38, count 0 2006.173.14:35:21.48#ibcon#*after write, iclass 38, count 0 2006.173.14:35:21.48#ibcon#*before return 0, iclass 38, count 0 2006.173.14:35:21.48#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.14:35:21.48#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.14:35:21.48#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.14:35:21.48#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.14:35:21.48$vck44/valo=5,734.99 2006.173.14:35:21.48#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.14:35:21.48#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.14:35:21.48#ibcon#ireg 17 cls_cnt 0 2006.173.14:35:21.48#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.14:35:21.48#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.14:35:21.48#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.14:35:21.48#ibcon#enter wrdev, iclass 40, count 0 2006.173.14:35:21.48#ibcon#first serial, iclass 40, count 0 2006.173.14:35:21.48#ibcon#enter sib2, iclass 40, count 0 2006.173.14:35:21.48#ibcon#flushed, iclass 40, count 0 2006.173.14:35:21.48#ibcon#about to write, iclass 40, count 0 2006.173.14:35:21.48#ibcon#wrote, iclass 40, count 0 2006.173.14:35:21.48#ibcon#about to read 3, iclass 40, count 0 2006.173.14:35:21.50#ibcon#read 3, iclass 40, count 0 2006.173.14:35:21.50#ibcon#about to read 4, iclass 40, count 0 2006.173.14:35:21.50#ibcon#read 4, iclass 40, count 0 2006.173.14:35:21.50#ibcon#about to read 5, iclass 40, count 0 2006.173.14:35:21.50#ibcon#read 5, iclass 40, count 0 2006.173.14:35:21.50#ibcon#about to read 6, iclass 40, count 0 2006.173.14:35:21.50#ibcon#read 6, iclass 40, count 0 2006.173.14:35:21.50#ibcon#end of sib2, iclass 40, count 0 2006.173.14:35:21.50#ibcon#*mode == 0, iclass 40, count 0 2006.173.14:35:21.50#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.14:35:21.50#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.14:35:21.50#ibcon#*before write, iclass 40, count 0 2006.173.14:35:21.50#ibcon#enter sib2, iclass 40, count 0 2006.173.14:35:21.50#ibcon#flushed, iclass 40, count 0 2006.173.14:35:21.50#ibcon#about to write, iclass 40, count 0 2006.173.14:35:21.50#ibcon#wrote, iclass 40, count 0 2006.173.14:35:21.50#ibcon#about to read 3, iclass 40, count 0 2006.173.14:35:21.54#ibcon#read 3, iclass 40, count 0 2006.173.14:35:21.54#ibcon#about to read 4, iclass 40, count 0 2006.173.14:35:21.54#ibcon#read 4, iclass 40, count 0 2006.173.14:35:21.54#ibcon#about to read 5, iclass 40, count 0 2006.173.14:35:21.54#ibcon#read 5, iclass 40, count 0 2006.173.14:35:21.54#ibcon#about to read 6, iclass 40, count 0 2006.173.14:35:21.54#ibcon#read 6, iclass 40, count 0 2006.173.14:35:21.54#ibcon#end of sib2, iclass 40, count 0 2006.173.14:35:21.54#ibcon#*after write, iclass 40, count 0 2006.173.14:35:21.54#ibcon#*before return 0, iclass 40, count 0 2006.173.14:35:21.54#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.14:35:21.54#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.14:35:21.54#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.14:35:21.54#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.14:35:21.54$vck44/va=5,4 2006.173.14:35:21.54#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.14:35:21.54#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.14:35:21.54#ibcon#ireg 11 cls_cnt 2 2006.173.14:35:21.54#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.14:35:21.60#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.14:35:21.60#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.14:35:21.60#ibcon#enter wrdev, iclass 4, count 2 2006.173.14:35:21.60#ibcon#first serial, iclass 4, count 2 2006.173.14:35:21.60#ibcon#enter sib2, iclass 4, count 2 2006.173.14:35:21.60#ibcon#flushed, iclass 4, count 2 2006.173.14:35:21.60#ibcon#about to write, iclass 4, count 2 2006.173.14:35:21.60#ibcon#wrote, iclass 4, count 2 2006.173.14:35:21.60#ibcon#about to read 3, iclass 4, count 2 2006.173.14:35:21.62#ibcon#read 3, iclass 4, count 2 2006.173.14:35:21.62#ibcon#about to read 4, iclass 4, count 2 2006.173.14:35:21.62#ibcon#read 4, iclass 4, count 2 2006.173.14:35:21.62#ibcon#about to read 5, iclass 4, count 2 2006.173.14:35:21.62#ibcon#read 5, iclass 4, count 2 2006.173.14:35:21.62#ibcon#about to read 6, iclass 4, count 2 2006.173.14:35:21.62#ibcon#read 6, iclass 4, count 2 2006.173.14:35:21.62#ibcon#end of sib2, iclass 4, count 2 2006.173.14:35:21.62#ibcon#*mode == 0, iclass 4, count 2 2006.173.14:35:21.62#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.14:35:21.62#ibcon#[25=AT05-04\r\n] 2006.173.14:35:21.62#ibcon#*before write, iclass 4, count 2 2006.173.14:35:21.62#ibcon#enter sib2, iclass 4, count 2 2006.173.14:35:21.62#ibcon#flushed, iclass 4, count 2 2006.173.14:35:21.62#ibcon#about to write, iclass 4, count 2 2006.173.14:35:21.62#ibcon#wrote, iclass 4, count 2 2006.173.14:35:21.62#ibcon#about to read 3, iclass 4, count 2 2006.173.14:35:21.65#ibcon#read 3, iclass 4, count 2 2006.173.14:35:21.65#ibcon#about to read 4, iclass 4, count 2 2006.173.14:35:21.65#ibcon#read 4, iclass 4, count 2 2006.173.14:35:21.65#ibcon#about to read 5, iclass 4, count 2 2006.173.14:35:21.65#ibcon#read 5, iclass 4, count 2 2006.173.14:35:21.65#ibcon#about to read 6, iclass 4, count 2 2006.173.14:35:21.65#ibcon#read 6, iclass 4, count 2 2006.173.14:35:21.65#ibcon#end of sib2, iclass 4, count 2 2006.173.14:35:21.65#ibcon#*after write, iclass 4, count 2 2006.173.14:35:21.65#ibcon#*before return 0, iclass 4, count 2 2006.173.14:35:21.65#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.14:35:21.65#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.14:35:21.65#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.14:35:21.65#ibcon#ireg 7 cls_cnt 0 2006.173.14:35:21.65#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.14:35:21.77#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.14:35:21.77#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.14:35:21.77#ibcon#enter wrdev, iclass 4, count 0 2006.173.14:35:21.77#ibcon#first serial, iclass 4, count 0 2006.173.14:35:21.77#ibcon#enter sib2, iclass 4, count 0 2006.173.14:35:21.77#ibcon#flushed, iclass 4, count 0 2006.173.14:35:21.77#ibcon#about to write, iclass 4, count 0 2006.173.14:35:21.77#ibcon#wrote, iclass 4, count 0 2006.173.14:35:21.77#ibcon#about to read 3, iclass 4, count 0 2006.173.14:35:21.79#ibcon#read 3, iclass 4, count 0 2006.173.14:35:21.79#ibcon#about to read 4, iclass 4, count 0 2006.173.14:35:21.79#ibcon#read 4, iclass 4, count 0 2006.173.14:35:21.79#ibcon#about to read 5, iclass 4, count 0 2006.173.14:35:21.79#ibcon#read 5, iclass 4, count 0 2006.173.14:35:21.79#ibcon#about to read 6, iclass 4, count 0 2006.173.14:35:21.79#ibcon#read 6, iclass 4, count 0 2006.173.14:35:21.79#ibcon#end of sib2, iclass 4, count 0 2006.173.14:35:21.79#ibcon#*mode == 0, iclass 4, count 0 2006.173.14:35:21.79#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.14:35:21.79#ibcon#[25=USB\r\n] 2006.173.14:35:21.79#ibcon#*before write, iclass 4, count 0 2006.173.14:35:21.79#ibcon#enter sib2, iclass 4, count 0 2006.173.14:35:21.79#ibcon#flushed, iclass 4, count 0 2006.173.14:35:21.79#ibcon#about to write, iclass 4, count 0 2006.173.14:35:21.79#ibcon#wrote, iclass 4, count 0 2006.173.14:35:21.79#ibcon#about to read 3, iclass 4, count 0 2006.173.14:35:21.82#ibcon#read 3, iclass 4, count 0 2006.173.14:35:21.82#ibcon#about to read 4, iclass 4, count 0 2006.173.14:35:21.82#ibcon#read 4, iclass 4, count 0 2006.173.14:35:21.82#ibcon#about to read 5, iclass 4, count 0 2006.173.14:35:21.82#ibcon#read 5, iclass 4, count 0 2006.173.14:35:21.82#ibcon#about to read 6, iclass 4, count 0 2006.173.14:35:21.82#ibcon#read 6, iclass 4, count 0 2006.173.14:35:21.82#ibcon#end of sib2, iclass 4, count 0 2006.173.14:35:21.82#ibcon#*after write, iclass 4, count 0 2006.173.14:35:21.82#ibcon#*before return 0, iclass 4, count 0 2006.173.14:35:21.82#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.14:35:21.82#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.14:35:21.82#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.14:35:21.82#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.14:35:21.82$vck44/valo=6,814.99 2006.173.14:35:21.82#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.14:35:21.82#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.14:35:21.82#ibcon#ireg 17 cls_cnt 0 2006.173.14:35:21.82#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.14:35:21.82#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.14:35:21.82#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.14:35:21.82#ibcon#enter wrdev, iclass 6, count 0 2006.173.14:35:21.82#ibcon#first serial, iclass 6, count 0 2006.173.14:35:21.82#ibcon#enter sib2, iclass 6, count 0 2006.173.14:35:21.82#ibcon#flushed, iclass 6, count 0 2006.173.14:35:21.82#ibcon#about to write, iclass 6, count 0 2006.173.14:35:21.82#ibcon#wrote, iclass 6, count 0 2006.173.14:35:21.82#ibcon#about to read 3, iclass 6, count 0 2006.173.14:35:21.84#ibcon#read 3, iclass 6, count 0 2006.173.14:35:21.84#ibcon#about to read 4, iclass 6, count 0 2006.173.14:35:21.84#ibcon#read 4, iclass 6, count 0 2006.173.14:35:21.84#ibcon#about to read 5, iclass 6, count 0 2006.173.14:35:21.84#ibcon#read 5, iclass 6, count 0 2006.173.14:35:21.84#ibcon#about to read 6, iclass 6, count 0 2006.173.14:35:21.84#ibcon#read 6, iclass 6, count 0 2006.173.14:35:21.84#ibcon#end of sib2, iclass 6, count 0 2006.173.14:35:21.84#ibcon#*mode == 0, iclass 6, count 0 2006.173.14:35:21.84#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.14:35:21.84#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.14:35:21.84#ibcon#*before write, iclass 6, count 0 2006.173.14:35:21.84#ibcon#enter sib2, iclass 6, count 0 2006.173.14:35:21.84#ibcon#flushed, iclass 6, count 0 2006.173.14:35:21.84#ibcon#about to write, iclass 6, count 0 2006.173.14:35:21.84#ibcon#wrote, iclass 6, count 0 2006.173.14:35:21.84#ibcon#about to read 3, iclass 6, count 0 2006.173.14:35:21.88#ibcon#read 3, iclass 6, count 0 2006.173.14:35:21.88#ibcon#about to read 4, iclass 6, count 0 2006.173.14:35:21.88#ibcon#read 4, iclass 6, count 0 2006.173.14:35:21.88#ibcon#about to read 5, iclass 6, count 0 2006.173.14:35:21.88#ibcon#read 5, iclass 6, count 0 2006.173.14:35:21.88#ibcon#about to read 6, iclass 6, count 0 2006.173.14:35:21.88#ibcon#read 6, iclass 6, count 0 2006.173.14:35:21.88#ibcon#end of sib2, iclass 6, count 0 2006.173.14:35:21.88#ibcon#*after write, iclass 6, count 0 2006.173.14:35:21.88#ibcon#*before return 0, iclass 6, count 0 2006.173.14:35:21.88#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.14:35:21.88#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.14:35:21.88#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.14:35:21.88#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.14:35:21.88$vck44/va=6,3 2006.173.14:35:21.88#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.14:35:21.88#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.14:35:21.88#ibcon#ireg 11 cls_cnt 2 2006.173.14:35:21.88#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.14:35:21.94#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.14:35:21.94#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.14:35:21.94#ibcon#enter wrdev, iclass 10, count 2 2006.173.14:35:21.94#ibcon#first serial, iclass 10, count 2 2006.173.14:35:21.94#ibcon#enter sib2, iclass 10, count 2 2006.173.14:35:21.94#ibcon#flushed, iclass 10, count 2 2006.173.14:35:21.94#ibcon#about to write, iclass 10, count 2 2006.173.14:35:21.94#ibcon#wrote, iclass 10, count 2 2006.173.14:35:21.94#ibcon#about to read 3, iclass 10, count 2 2006.173.14:35:21.96#ibcon#read 3, iclass 10, count 2 2006.173.14:35:21.96#ibcon#about to read 4, iclass 10, count 2 2006.173.14:35:21.96#ibcon#read 4, iclass 10, count 2 2006.173.14:35:21.96#ibcon#about to read 5, iclass 10, count 2 2006.173.14:35:21.96#ibcon#read 5, iclass 10, count 2 2006.173.14:35:21.96#ibcon#about to read 6, iclass 10, count 2 2006.173.14:35:21.96#ibcon#read 6, iclass 10, count 2 2006.173.14:35:21.96#ibcon#end of sib2, iclass 10, count 2 2006.173.14:35:21.96#ibcon#*mode == 0, iclass 10, count 2 2006.173.14:35:21.96#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.14:35:21.96#ibcon#[25=AT06-03\r\n] 2006.173.14:35:21.96#ibcon#*before write, iclass 10, count 2 2006.173.14:35:21.96#ibcon#enter sib2, iclass 10, count 2 2006.173.14:35:21.96#ibcon#flushed, iclass 10, count 2 2006.173.14:35:21.96#ibcon#about to write, iclass 10, count 2 2006.173.14:35:21.96#ibcon#wrote, iclass 10, count 2 2006.173.14:35:21.96#ibcon#about to read 3, iclass 10, count 2 2006.173.14:35:21.99#ibcon#read 3, iclass 10, count 2 2006.173.14:35:21.99#ibcon#about to read 4, iclass 10, count 2 2006.173.14:35:21.99#ibcon#read 4, iclass 10, count 2 2006.173.14:35:21.99#ibcon#about to read 5, iclass 10, count 2 2006.173.14:35:21.99#ibcon#read 5, iclass 10, count 2 2006.173.14:35:21.99#ibcon#about to read 6, iclass 10, count 2 2006.173.14:35:21.99#ibcon#read 6, iclass 10, count 2 2006.173.14:35:21.99#ibcon#end of sib2, iclass 10, count 2 2006.173.14:35:21.99#ibcon#*after write, iclass 10, count 2 2006.173.14:35:21.99#ibcon#*before return 0, iclass 10, count 2 2006.173.14:35:21.99#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.14:35:21.99#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.14:35:21.99#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.14:35:21.99#ibcon#ireg 7 cls_cnt 0 2006.173.14:35:21.99#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.14:35:22.11#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.14:35:22.11#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.14:35:22.11#ibcon#enter wrdev, iclass 10, count 0 2006.173.14:35:22.11#ibcon#first serial, iclass 10, count 0 2006.173.14:35:22.11#ibcon#enter sib2, iclass 10, count 0 2006.173.14:35:22.11#ibcon#flushed, iclass 10, count 0 2006.173.14:35:22.11#ibcon#about to write, iclass 10, count 0 2006.173.14:35:22.11#ibcon#wrote, iclass 10, count 0 2006.173.14:35:22.11#ibcon#about to read 3, iclass 10, count 0 2006.173.14:35:22.13#ibcon#read 3, iclass 10, count 0 2006.173.14:35:22.13#ibcon#about to read 4, iclass 10, count 0 2006.173.14:35:22.13#ibcon#read 4, iclass 10, count 0 2006.173.14:35:22.13#ibcon#about to read 5, iclass 10, count 0 2006.173.14:35:22.13#ibcon#read 5, iclass 10, count 0 2006.173.14:35:22.13#ibcon#about to read 6, iclass 10, count 0 2006.173.14:35:22.13#ibcon#read 6, iclass 10, count 0 2006.173.14:35:22.13#ibcon#end of sib2, iclass 10, count 0 2006.173.14:35:22.13#ibcon#*mode == 0, iclass 10, count 0 2006.173.14:35:22.13#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.14:35:22.13#ibcon#[25=USB\r\n] 2006.173.14:35:22.13#ibcon#*before write, iclass 10, count 0 2006.173.14:35:22.13#ibcon#enter sib2, iclass 10, count 0 2006.173.14:35:22.13#ibcon#flushed, iclass 10, count 0 2006.173.14:35:22.13#ibcon#about to write, iclass 10, count 0 2006.173.14:35:22.13#ibcon#wrote, iclass 10, count 0 2006.173.14:35:22.13#ibcon#about to read 3, iclass 10, count 0 2006.173.14:35:22.16#ibcon#read 3, iclass 10, count 0 2006.173.14:35:22.16#ibcon#about to read 4, iclass 10, count 0 2006.173.14:35:22.16#ibcon#read 4, iclass 10, count 0 2006.173.14:35:22.16#ibcon#about to read 5, iclass 10, count 0 2006.173.14:35:22.16#ibcon#read 5, iclass 10, count 0 2006.173.14:35:22.16#ibcon#about to read 6, iclass 10, count 0 2006.173.14:35:22.16#ibcon#read 6, iclass 10, count 0 2006.173.14:35:22.16#ibcon#end of sib2, iclass 10, count 0 2006.173.14:35:22.16#ibcon#*after write, iclass 10, count 0 2006.173.14:35:22.16#ibcon#*before return 0, iclass 10, count 0 2006.173.14:35:22.16#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.14:35:22.16#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.14:35:22.16#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.14:35:22.16#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.14:35:22.16$vck44/valo=7,864.99 2006.173.14:35:22.16#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.14:35:22.16#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.14:35:22.16#ibcon#ireg 17 cls_cnt 0 2006.173.14:35:22.16#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.14:35:22.16#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.14:35:22.16#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.14:35:22.16#ibcon#enter wrdev, iclass 12, count 0 2006.173.14:35:22.16#ibcon#first serial, iclass 12, count 0 2006.173.14:35:22.16#ibcon#enter sib2, iclass 12, count 0 2006.173.14:35:22.16#ibcon#flushed, iclass 12, count 0 2006.173.14:35:22.16#ibcon#about to write, iclass 12, count 0 2006.173.14:35:22.16#ibcon#wrote, iclass 12, count 0 2006.173.14:35:22.16#ibcon#about to read 3, iclass 12, count 0 2006.173.14:35:22.18#ibcon#read 3, iclass 12, count 0 2006.173.14:35:22.18#ibcon#about to read 4, iclass 12, count 0 2006.173.14:35:22.18#ibcon#read 4, iclass 12, count 0 2006.173.14:35:22.18#ibcon#about to read 5, iclass 12, count 0 2006.173.14:35:22.18#ibcon#read 5, iclass 12, count 0 2006.173.14:35:22.18#ibcon#about to read 6, iclass 12, count 0 2006.173.14:35:22.18#ibcon#read 6, iclass 12, count 0 2006.173.14:35:22.18#ibcon#end of sib2, iclass 12, count 0 2006.173.14:35:22.18#ibcon#*mode == 0, iclass 12, count 0 2006.173.14:35:22.18#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.14:35:22.18#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.14:35:22.18#ibcon#*before write, iclass 12, count 0 2006.173.14:35:22.18#ibcon#enter sib2, iclass 12, count 0 2006.173.14:35:22.18#ibcon#flushed, iclass 12, count 0 2006.173.14:35:22.18#ibcon#about to write, iclass 12, count 0 2006.173.14:35:22.18#ibcon#wrote, iclass 12, count 0 2006.173.14:35:22.18#ibcon#about to read 3, iclass 12, count 0 2006.173.14:35:22.22#ibcon#read 3, iclass 12, count 0 2006.173.14:35:22.22#ibcon#about to read 4, iclass 12, count 0 2006.173.14:35:22.22#ibcon#read 4, iclass 12, count 0 2006.173.14:35:22.22#ibcon#about to read 5, iclass 12, count 0 2006.173.14:35:22.22#ibcon#read 5, iclass 12, count 0 2006.173.14:35:22.22#ibcon#about to read 6, iclass 12, count 0 2006.173.14:35:22.22#ibcon#read 6, iclass 12, count 0 2006.173.14:35:22.22#ibcon#end of sib2, iclass 12, count 0 2006.173.14:35:22.22#ibcon#*after write, iclass 12, count 0 2006.173.14:35:22.22#ibcon#*before return 0, iclass 12, count 0 2006.173.14:35:22.22#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.14:35:22.22#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.14:35:22.22#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.14:35:22.22#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.14:35:22.22$vck44/va=7,4 2006.173.14:35:22.22#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.14:35:22.22#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.14:35:22.22#ibcon#ireg 11 cls_cnt 2 2006.173.14:35:22.22#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.14:35:22.28#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.14:35:22.28#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.14:35:22.28#ibcon#enter wrdev, iclass 14, count 2 2006.173.14:35:22.28#ibcon#first serial, iclass 14, count 2 2006.173.14:35:22.28#ibcon#enter sib2, iclass 14, count 2 2006.173.14:35:22.28#ibcon#flushed, iclass 14, count 2 2006.173.14:35:22.28#ibcon#about to write, iclass 14, count 2 2006.173.14:35:22.28#ibcon#wrote, iclass 14, count 2 2006.173.14:35:22.28#ibcon#about to read 3, iclass 14, count 2 2006.173.14:35:22.30#ibcon#read 3, iclass 14, count 2 2006.173.14:35:22.30#ibcon#about to read 4, iclass 14, count 2 2006.173.14:35:22.30#ibcon#read 4, iclass 14, count 2 2006.173.14:35:22.30#ibcon#about to read 5, iclass 14, count 2 2006.173.14:35:22.30#ibcon#read 5, iclass 14, count 2 2006.173.14:35:22.30#ibcon#about to read 6, iclass 14, count 2 2006.173.14:35:22.30#ibcon#read 6, iclass 14, count 2 2006.173.14:35:22.30#ibcon#end of sib2, iclass 14, count 2 2006.173.14:35:22.30#ibcon#*mode == 0, iclass 14, count 2 2006.173.14:35:22.30#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.14:35:22.30#ibcon#[25=AT07-04\r\n] 2006.173.14:35:22.30#ibcon#*before write, iclass 14, count 2 2006.173.14:35:22.30#ibcon#enter sib2, iclass 14, count 2 2006.173.14:35:22.30#ibcon#flushed, iclass 14, count 2 2006.173.14:35:22.30#ibcon#about to write, iclass 14, count 2 2006.173.14:35:22.30#ibcon#wrote, iclass 14, count 2 2006.173.14:35:22.30#ibcon#about to read 3, iclass 14, count 2 2006.173.14:35:22.33#ibcon#read 3, iclass 14, count 2 2006.173.14:35:22.33#ibcon#about to read 4, iclass 14, count 2 2006.173.14:35:22.33#ibcon#read 4, iclass 14, count 2 2006.173.14:35:22.33#ibcon#about to read 5, iclass 14, count 2 2006.173.14:35:22.33#ibcon#read 5, iclass 14, count 2 2006.173.14:35:22.33#ibcon#about to read 6, iclass 14, count 2 2006.173.14:35:22.33#ibcon#read 6, iclass 14, count 2 2006.173.14:35:22.33#ibcon#end of sib2, iclass 14, count 2 2006.173.14:35:22.33#ibcon#*after write, iclass 14, count 2 2006.173.14:35:22.33#ibcon#*before return 0, iclass 14, count 2 2006.173.14:35:22.33#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.14:35:22.33#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.14:35:22.33#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.14:35:22.33#ibcon#ireg 7 cls_cnt 0 2006.173.14:35:22.33#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.14:35:22.45#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.14:35:22.45#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.14:35:22.45#ibcon#enter wrdev, iclass 14, count 0 2006.173.14:35:22.45#ibcon#first serial, iclass 14, count 0 2006.173.14:35:22.45#ibcon#enter sib2, iclass 14, count 0 2006.173.14:35:22.45#ibcon#flushed, iclass 14, count 0 2006.173.14:35:22.45#ibcon#about to write, iclass 14, count 0 2006.173.14:35:22.45#ibcon#wrote, iclass 14, count 0 2006.173.14:35:22.45#ibcon#about to read 3, iclass 14, count 0 2006.173.14:35:22.47#ibcon#read 3, iclass 14, count 0 2006.173.14:35:22.47#ibcon#about to read 4, iclass 14, count 0 2006.173.14:35:22.47#ibcon#read 4, iclass 14, count 0 2006.173.14:35:22.47#ibcon#about to read 5, iclass 14, count 0 2006.173.14:35:22.47#ibcon#read 5, iclass 14, count 0 2006.173.14:35:22.47#ibcon#about to read 6, iclass 14, count 0 2006.173.14:35:22.47#ibcon#read 6, iclass 14, count 0 2006.173.14:35:22.47#ibcon#end of sib2, iclass 14, count 0 2006.173.14:35:22.47#ibcon#*mode == 0, iclass 14, count 0 2006.173.14:35:22.47#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.14:35:22.47#ibcon#[25=USB\r\n] 2006.173.14:35:22.47#ibcon#*before write, iclass 14, count 0 2006.173.14:35:22.47#ibcon#enter sib2, iclass 14, count 0 2006.173.14:35:22.47#ibcon#flushed, iclass 14, count 0 2006.173.14:35:22.47#ibcon#about to write, iclass 14, count 0 2006.173.14:35:22.47#ibcon#wrote, iclass 14, count 0 2006.173.14:35:22.47#ibcon#about to read 3, iclass 14, count 0 2006.173.14:35:22.50#ibcon#read 3, iclass 14, count 0 2006.173.14:35:22.50#ibcon#about to read 4, iclass 14, count 0 2006.173.14:35:22.50#ibcon#read 4, iclass 14, count 0 2006.173.14:35:22.50#ibcon#about to read 5, iclass 14, count 0 2006.173.14:35:22.50#ibcon#read 5, iclass 14, count 0 2006.173.14:35:22.50#ibcon#about to read 6, iclass 14, count 0 2006.173.14:35:22.50#ibcon#read 6, iclass 14, count 0 2006.173.14:35:22.50#ibcon#end of sib2, iclass 14, count 0 2006.173.14:35:22.50#ibcon#*after write, iclass 14, count 0 2006.173.14:35:22.50#ibcon#*before return 0, iclass 14, count 0 2006.173.14:35:22.50#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.14:35:22.50#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.14:35:22.50#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.14:35:22.50#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.14:35:22.50$vck44/valo=8,884.99 2006.173.14:35:22.50#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.14:35:22.50#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.14:35:22.50#ibcon#ireg 17 cls_cnt 0 2006.173.14:35:22.50#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.14:35:22.50#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.14:35:22.50#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.14:35:22.50#ibcon#enter wrdev, iclass 16, count 0 2006.173.14:35:22.50#ibcon#first serial, iclass 16, count 0 2006.173.14:35:22.50#ibcon#enter sib2, iclass 16, count 0 2006.173.14:35:22.50#ibcon#flushed, iclass 16, count 0 2006.173.14:35:22.50#ibcon#about to write, iclass 16, count 0 2006.173.14:35:22.50#ibcon#wrote, iclass 16, count 0 2006.173.14:35:22.50#ibcon#about to read 3, iclass 16, count 0 2006.173.14:35:22.52#ibcon#read 3, iclass 16, count 0 2006.173.14:35:22.52#ibcon#about to read 4, iclass 16, count 0 2006.173.14:35:22.52#ibcon#read 4, iclass 16, count 0 2006.173.14:35:22.52#ibcon#about to read 5, iclass 16, count 0 2006.173.14:35:22.52#ibcon#read 5, iclass 16, count 0 2006.173.14:35:22.52#ibcon#about to read 6, iclass 16, count 0 2006.173.14:35:22.52#ibcon#read 6, iclass 16, count 0 2006.173.14:35:22.52#ibcon#end of sib2, iclass 16, count 0 2006.173.14:35:22.52#ibcon#*mode == 0, iclass 16, count 0 2006.173.14:35:22.52#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.14:35:22.52#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.14:35:22.52#ibcon#*before write, iclass 16, count 0 2006.173.14:35:22.52#ibcon#enter sib2, iclass 16, count 0 2006.173.14:35:22.52#ibcon#flushed, iclass 16, count 0 2006.173.14:35:22.52#ibcon#about to write, iclass 16, count 0 2006.173.14:35:22.52#ibcon#wrote, iclass 16, count 0 2006.173.14:35:22.52#ibcon#about to read 3, iclass 16, count 0 2006.173.14:35:22.56#ibcon#read 3, iclass 16, count 0 2006.173.14:35:22.56#ibcon#about to read 4, iclass 16, count 0 2006.173.14:35:22.56#ibcon#read 4, iclass 16, count 0 2006.173.14:35:22.56#ibcon#about to read 5, iclass 16, count 0 2006.173.14:35:22.56#ibcon#read 5, iclass 16, count 0 2006.173.14:35:22.56#ibcon#about to read 6, iclass 16, count 0 2006.173.14:35:22.56#ibcon#read 6, iclass 16, count 0 2006.173.14:35:22.56#ibcon#end of sib2, iclass 16, count 0 2006.173.14:35:22.56#ibcon#*after write, iclass 16, count 0 2006.173.14:35:22.56#ibcon#*before return 0, iclass 16, count 0 2006.173.14:35:22.56#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.14:35:22.56#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.14:35:22.56#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.14:35:22.56#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.14:35:22.56$vck44/va=8,4 2006.173.14:35:22.56#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.14:35:22.56#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.14:35:22.56#ibcon#ireg 11 cls_cnt 2 2006.173.14:35:22.56#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.14:35:22.62#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.14:35:22.62#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.14:35:22.62#ibcon#enter wrdev, iclass 18, count 2 2006.173.14:35:22.62#ibcon#first serial, iclass 18, count 2 2006.173.14:35:22.62#ibcon#enter sib2, iclass 18, count 2 2006.173.14:35:22.62#ibcon#flushed, iclass 18, count 2 2006.173.14:35:22.62#ibcon#about to write, iclass 18, count 2 2006.173.14:35:22.62#ibcon#wrote, iclass 18, count 2 2006.173.14:35:22.62#ibcon#about to read 3, iclass 18, count 2 2006.173.14:35:22.64#ibcon#read 3, iclass 18, count 2 2006.173.14:35:22.64#ibcon#about to read 4, iclass 18, count 2 2006.173.14:35:22.64#ibcon#read 4, iclass 18, count 2 2006.173.14:35:22.64#ibcon#about to read 5, iclass 18, count 2 2006.173.14:35:22.64#ibcon#read 5, iclass 18, count 2 2006.173.14:35:22.64#ibcon#about to read 6, iclass 18, count 2 2006.173.14:35:22.64#ibcon#read 6, iclass 18, count 2 2006.173.14:35:22.64#ibcon#end of sib2, iclass 18, count 2 2006.173.14:35:22.64#ibcon#*mode == 0, iclass 18, count 2 2006.173.14:35:22.64#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.14:35:22.64#ibcon#[25=AT08-04\r\n] 2006.173.14:35:22.64#ibcon#*before write, iclass 18, count 2 2006.173.14:35:22.64#ibcon#enter sib2, iclass 18, count 2 2006.173.14:35:22.64#ibcon#flushed, iclass 18, count 2 2006.173.14:35:22.64#ibcon#about to write, iclass 18, count 2 2006.173.14:35:22.64#ibcon#wrote, iclass 18, count 2 2006.173.14:35:22.64#ibcon#about to read 3, iclass 18, count 2 2006.173.14:35:22.67#ibcon#read 3, iclass 18, count 2 2006.173.14:35:22.67#ibcon#about to read 4, iclass 18, count 2 2006.173.14:35:22.67#ibcon#read 4, iclass 18, count 2 2006.173.14:35:22.67#ibcon#about to read 5, iclass 18, count 2 2006.173.14:35:22.67#ibcon#read 5, iclass 18, count 2 2006.173.14:35:22.67#ibcon#about to read 6, iclass 18, count 2 2006.173.14:35:22.67#ibcon#read 6, iclass 18, count 2 2006.173.14:35:22.67#ibcon#end of sib2, iclass 18, count 2 2006.173.14:35:22.67#ibcon#*after write, iclass 18, count 2 2006.173.14:35:22.67#ibcon#*before return 0, iclass 18, count 2 2006.173.14:35:22.67#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.14:35:22.67#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.14:35:22.67#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.14:35:22.67#ibcon#ireg 7 cls_cnt 0 2006.173.14:35:22.67#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.14:35:22.79#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.14:35:22.79#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.14:35:22.79#ibcon#enter wrdev, iclass 18, count 0 2006.173.14:35:22.79#ibcon#first serial, iclass 18, count 0 2006.173.14:35:22.79#ibcon#enter sib2, iclass 18, count 0 2006.173.14:35:22.79#ibcon#flushed, iclass 18, count 0 2006.173.14:35:22.79#ibcon#about to write, iclass 18, count 0 2006.173.14:35:22.79#ibcon#wrote, iclass 18, count 0 2006.173.14:35:22.79#ibcon#about to read 3, iclass 18, count 0 2006.173.14:35:22.81#ibcon#read 3, iclass 18, count 0 2006.173.14:35:22.81#ibcon#about to read 4, iclass 18, count 0 2006.173.14:35:22.81#ibcon#read 4, iclass 18, count 0 2006.173.14:35:22.81#ibcon#about to read 5, iclass 18, count 0 2006.173.14:35:22.81#ibcon#read 5, iclass 18, count 0 2006.173.14:35:22.81#ibcon#about to read 6, iclass 18, count 0 2006.173.14:35:22.81#ibcon#read 6, iclass 18, count 0 2006.173.14:35:22.81#ibcon#end of sib2, iclass 18, count 0 2006.173.14:35:22.81#ibcon#*mode == 0, iclass 18, count 0 2006.173.14:35:22.81#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.14:35:22.81#ibcon#[25=USB\r\n] 2006.173.14:35:22.81#ibcon#*before write, iclass 18, count 0 2006.173.14:35:22.81#ibcon#enter sib2, iclass 18, count 0 2006.173.14:35:22.81#ibcon#flushed, iclass 18, count 0 2006.173.14:35:22.81#ibcon#about to write, iclass 18, count 0 2006.173.14:35:22.81#ibcon#wrote, iclass 18, count 0 2006.173.14:35:22.81#ibcon#about to read 3, iclass 18, count 0 2006.173.14:35:22.84#ibcon#read 3, iclass 18, count 0 2006.173.14:35:22.84#ibcon#about to read 4, iclass 18, count 0 2006.173.14:35:22.84#ibcon#read 4, iclass 18, count 0 2006.173.14:35:22.84#ibcon#about to read 5, iclass 18, count 0 2006.173.14:35:22.84#ibcon#read 5, iclass 18, count 0 2006.173.14:35:22.84#ibcon#about to read 6, iclass 18, count 0 2006.173.14:35:22.84#ibcon#read 6, iclass 18, count 0 2006.173.14:35:22.84#ibcon#end of sib2, iclass 18, count 0 2006.173.14:35:22.84#ibcon#*after write, iclass 18, count 0 2006.173.14:35:22.84#ibcon#*before return 0, iclass 18, count 0 2006.173.14:35:22.84#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.14:35:22.84#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.14:35:22.84#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.14:35:22.84#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.14:35:22.84$vck44/vblo=1,629.99 2006.173.14:35:22.84#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.14:35:22.84#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.14:35:22.84#ibcon#ireg 17 cls_cnt 0 2006.173.14:35:22.84#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.14:35:22.84#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.14:35:22.84#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.14:35:22.84#ibcon#enter wrdev, iclass 20, count 0 2006.173.14:35:22.84#ibcon#first serial, iclass 20, count 0 2006.173.14:35:22.84#ibcon#enter sib2, iclass 20, count 0 2006.173.14:35:22.84#ibcon#flushed, iclass 20, count 0 2006.173.14:35:22.84#ibcon#about to write, iclass 20, count 0 2006.173.14:35:22.84#ibcon#wrote, iclass 20, count 0 2006.173.14:35:22.84#ibcon#about to read 3, iclass 20, count 0 2006.173.14:35:22.86#ibcon#read 3, iclass 20, count 0 2006.173.14:35:22.86#ibcon#about to read 4, iclass 20, count 0 2006.173.14:35:22.86#ibcon#read 4, iclass 20, count 0 2006.173.14:35:22.86#ibcon#about to read 5, iclass 20, count 0 2006.173.14:35:22.86#ibcon#read 5, iclass 20, count 0 2006.173.14:35:22.86#ibcon#about to read 6, iclass 20, count 0 2006.173.14:35:22.86#ibcon#read 6, iclass 20, count 0 2006.173.14:35:22.86#ibcon#end of sib2, iclass 20, count 0 2006.173.14:35:22.86#ibcon#*mode == 0, iclass 20, count 0 2006.173.14:35:22.86#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.14:35:22.86#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.14:35:22.86#ibcon#*before write, iclass 20, count 0 2006.173.14:35:22.86#ibcon#enter sib2, iclass 20, count 0 2006.173.14:35:22.86#ibcon#flushed, iclass 20, count 0 2006.173.14:35:22.86#ibcon#about to write, iclass 20, count 0 2006.173.14:35:22.86#ibcon#wrote, iclass 20, count 0 2006.173.14:35:22.86#ibcon#about to read 3, iclass 20, count 0 2006.173.14:35:22.90#ibcon#read 3, iclass 20, count 0 2006.173.14:35:22.90#ibcon#about to read 4, iclass 20, count 0 2006.173.14:35:22.90#ibcon#read 4, iclass 20, count 0 2006.173.14:35:22.90#ibcon#about to read 5, iclass 20, count 0 2006.173.14:35:22.90#ibcon#read 5, iclass 20, count 0 2006.173.14:35:22.90#ibcon#about to read 6, iclass 20, count 0 2006.173.14:35:22.90#ibcon#read 6, iclass 20, count 0 2006.173.14:35:22.90#ibcon#end of sib2, iclass 20, count 0 2006.173.14:35:22.90#ibcon#*after write, iclass 20, count 0 2006.173.14:35:22.90#ibcon#*before return 0, iclass 20, count 0 2006.173.14:35:22.90#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.14:35:22.90#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.14:35:22.90#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.14:35:22.90#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.14:35:22.90$vck44/vb=1,4 2006.173.14:35:22.90#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.14:35:22.90#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.14:35:22.90#ibcon#ireg 11 cls_cnt 2 2006.173.14:35:22.90#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.14:35:22.90#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.14:35:22.90#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.14:35:22.90#ibcon#enter wrdev, iclass 22, count 2 2006.173.14:35:22.90#ibcon#first serial, iclass 22, count 2 2006.173.14:35:22.90#ibcon#enter sib2, iclass 22, count 2 2006.173.14:35:22.90#ibcon#flushed, iclass 22, count 2 2006.173.14:35:22.90#ibcon#about to write, iclass 22, count 2 2006.173.14:35:22.90#ibcon#wrote, iclass 22, count 2 2006.173.14:35:22.90#ibcon#about to read 3, iclass 22, count 2 2006.173.14:35:22.92#ibcon#read 3, iclass 22, count 2 2006.173.14:35:22.92#ibcon#about to read 4, iclass 22, count 2 2006.173.14:35:22.92#ibcon#read 4, iclass 22, count 2 2006.173.14:35:22.92#ibcon#about to read 5, iclass 22, count 2 2006.173.14:35:22.92#ibcon#read 5, iclass 22, count 2 2006.173.14:35:22.92#ibcon#about to read 6, iclass 22, count 2 2006.173.14:35:22.92#ibcon#read 6, iclass 22, count 2 2006.173.14:35:22.92#ibcon#end of sib2, iclass 22, count 2 2006.173.14:35:22.92#ibcon#*mode == 0, iclass 22, count 2 2006.173.14:35:22.92#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.14:35:22.92#ibcon#[27=AT01-04\r\n] 2006.173.14:35:22.92#ibcon#*before write, iclass 22, count 2 2006.173.14:35:22.92#ibcon#enter sib2, iclass 22, count 2 2006.173.14:35:22.92#ibcon#flushed, iclass 22, count 2 2006.173.14:35:22.92#ibcon#about to write, iclass 22, count 2 2006.173.14:35:22.92#ibcon#wrote, iclass 22, count 2 2006.173.14:35:22.92#ibcon#about to read 3, iclass 22, count 2 2006.173.14:35:22.95#ibcon#read 3, iclass 22, count 2 2006.173.14:35:22.95#ibcon#about to read 4, iclass 22, count 2 2006.173.14:35:22.95#ibcon#read 4, iclass 22, count 2 2006.173.14:35:22.95#ibcon#about to read 5, iclass 22, count 2 2006.173.14:35:22.95#ibcon#read 5, iclass 22, count 2 2006.173.14:35:22.95#ibcon#about to read 6, iclass 22, count 2 2006.173.14:35:22.95#ibcon#read 6, iclass 22, count 2 2006.173.14:35:22.95#ibcon#end of sib2, iclass 22, count 2 2006.173.14:35:22.95#ibcon#*after write, iclass 22, count 2 2006.173.14:35:22.95#ibcon#*before return 0, iclass 22, count 2 2006.173.14:35:22.95#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.14:35:22.95#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.14:35:22.95#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.14:35:22.95#ibcon#ireg 7 cls_cnt 0 2006.173.14:35:22.95#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.14:35:23.07#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.14:35:23.07#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.14:35:23.07#ibcon#enter wrdev, iclass 22, count 0 2006.173.14:35:23.07#ibcon#first serial, iclass 22, count 0 2006.173.14:35:23.07#ibcon#enter sib2, iclass 22, count 0 2006.173.14:35:23.07#ibcon#flushed, iclass 22, count 0 2006.173.14:35:23.07#ibcon#about to write, iclass 22, count 0 2006.173.14:35:23.07#ibcon#wrote, iclass 22, count 0 2006.173.14:35:23.07#ibcon#about to read 3, iclass 22, count 0 2006.173.14:35:23.09#ibcon#read 3, iclass 22, count 0 2006.173.14:35:23.09#ibcon#about to read 4, iclass 22, count 0 2006.173.14:35:23.09#ibcon#read 4, iclass 22, count 0 2006.173.14:35:23.09#ibcon#about to read 5, iclass 22, count 0 2006.173.14:35:23.09#ibcon#read 5, iclass 22, count 0 2006.173.14:35:23.09#ibcon#about to read 6, iclass 22, count 0 2006.173.14:35:23.09#ibcon#read 6, iclass 22, count 0 2006.173.14:35:23.09#ibcon#end of sib2, iclass 22, count 0 2006.173.14:35:23.09#ibcon#*mode == 0, iclass 22, count 0 2006.173.14:35:23.09#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.14:35:23.09#ibcon#[27=USB\r\n] 2006.173.14:35:23.09#ibcon#*before write, iclass 22, count 0 2006.173.14:35:23.09#ibcon#enter sib2, iclass 22, count 0 2006.173.14:35:23.09#ibcon#flushed, iclass 22, count 0 2006.173.14:35:23.09#ibcon#about to write, iclass 22, count 0 2006.173.14:35:23.09#ibcon#wrote, iclass 22, count 0 2006.173.14:35:23.09#ibcon#about to read 3, iclass 22, count 0 2006.173.14:35:23.12#ibcon#read 3, iclass 22, count 0 2006.173.14:35:23.12#ibcon#about to read 4, iclass 22, count 0 2006.173.14:35:23.12#ibcon#read 4, iclass 22, count 0 2006.173.14:35:23.12#ibcon#about to read 5, iclass 22, count 0 2006.173.14:35:23.12#ibcon#read 5, iclass 22, count 0 2006.173.14:35:23.12#ibcon#about to read 6, iclass 22, count 0 2006.173.14:35:23.12#ibcon#read 6, iclass 22, count 0 2006.173.14:35:23.12#ibcon#end of sib2, iclass 22, count 0 2006.173.14:35:23.12#ibcon#*after write, iclass 22, count 0 2006.173.14:35:23.12#ibcon#*before return 0, iclass 22, count 0 2006.173.14:35:23.12#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.14:35:23.12#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.14:35:23.12#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.14:35:23.12#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.14:35:23.12$vck44/vblo=2,634.99 2006.173.14:35:23.12#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.14:35:23.12#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.14:35:23.12#ibcon#ireg 17 cls_cnt 0 2006.173.14:35:23.12#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.14:35:23.12#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.14:35:23.12#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.14:35:23.12#ibcon#enter wrdev, iclass 24, count 0 2006.173.14:35:23.12#ibcon#first serial, iclass 24, count 0 2006.173.14:35:23.12#ibcon#enter sib2, iclass 24, count 0 2006.173.14:35:23.12#ibcon#flushed, iclass 24, count 0 2006.173.14:35:23.12#ibcon#about to write, iclass 24, count 0 2006.173.14:35:23.12#ibcon#wrote, iclass 24, count 0 2006.173.14:35:23.12#ibcon#about to read 3, iclass 24, count 0 2006.173.14:35:23.14#ibcon#read 3, iclass 24, count 0 2006.173.14:35:23.14#ibcon#about to read 4, iclass 24, count 0 2006.173.14:35:23.14#ibcon#read 4, iclass 24, count 0 2006.173.14:35:23.14#ibcon#about to read 5, iclass 24, count 0 2006.173.14:35:23.14#ibcon#read 5, iclass 24, count 0 2006.173.14:35:23.14#ibcon#about to read 6, iclass 24, count 0 2006.173.14:35:23.14#ibcon#read 6, iclass 24, count 0 2006.173.14:35:23.14#ibcon#end of sib2, iclass 24, count 0 2006.173.14:35:23.14#ibcon#*mode == 0, iclass 24, count 0 2006.173.14:35:23.14#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.14:35:23.14#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.14:35:23.14#ibcon#*before write, iclass 24, count 0 2006.173.14:35:23.14#ibcon#enter sib2, iclass 24, count 0 2006.173.14:35:23.14#ibcon#flushed, iclass 24, count 0 2006.173.14:35:23.14#ibcon#about to write, iclass 24, count 0 2006.173.14:35:23.14#ibcon#wrote, iclass 24, count 0 2006.173.14:35:23.14#ibcon#about to read 3, iclass 24, count 0 2006.173.14:35:23.18#ibcon#read 3, iclass 24, count 0 2006.173.14:35:23.18#ibcon#about to read 4, iclass 24, count 0 2006.173.14:35:23.18#ibcon#read 4, iclass 24, count 0 2006.173.14:35:23.18#ibcon#about to read 5, iclass 24, count 0 2006.173.14:35:23.18#ibcon#read 5, iclass 24, count 0 2006.173.14:35:23.18#ibcon#about to read 6, iclass 24, count 0 2006.173.14:35:23.18#ibcon#read 6, iclass 24, count 0 2006.173.14:35:23.18#ibcon#end of sib2, iclass 24, count 0 2006.173.14:35:23.18#ibcon#*after write, iclass 24, count 0 2006.173.14:35:23.18#ibcon#*before return 0, iclass 24, count 0 2006.173.14:35:23.18#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.14:35:23.18#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.14:35:23.18#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.14:35:23.18#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.14:35:23.18$vck44/vb=2,4 2006.173.14:35:23.18#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.14:35:23.18#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.14:35:23.18#ibcon#ireg 11 cls_cnt 2 2006.173.14:35:23.18#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.14:35:23.24#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.14:35:23.24#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.14:35:23.24#ibcon#enter wrdev, iclass 26, count 2 2006.173.14:35:23.24#ibcon#first serial, iclass 26, count 2 2006.173.14:35:23.24#ibcon#enter sib2, iclass 26, count 2 2006.173.14:35:23.24#ibcon#flushed, iclass 26, count 2 2006.173.14:35:23.24#ibcon#about to write, iclass 26, count 2 2006.173.14:35:23.24#ibcon#wrote, iclass 26, count 2 2006.173.14:35:23.24#ibcon#about to read 3, iclass 26, count 2 2006.173.14:35:23.26#ibcon#read 3, iclass 26, count 2 2006.173.14:35:23.26#ibcon#about to read 4, iclass 26, count 2 2006.173.14:35:23.26#ibcon#read 4, iclass 26, count 2 2006.173.14:35:23.26#ibcon#about to read 5, iclass 26, count 2 2006.173.14:35:23.26#ibcon#read 5, iclass 26, count 2 2006.173.14:35:23.26#ibcon#about to read 6, iclass 26, count 2 2006.173.14:35:23.26#ibcon#read 6, iclass 26, count 2 2006.173.14:35:23.26#ibcon#end of sib2, iclass 26, count 2 2006.173.14:35:23.26#ibcon#*mode == 0, iclass 26, count 2 2006.173.14:35:23.26#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.14:35:23.26#ibcon#[27=AT02-04\r\n] 2006.173.14:35:23.26#ibcon#*before write, iclass 26, count 2 2006.173.14:35:23.26#ibcon#enter sib2, iclass 26, count 2 2006.173.14:35:23.26#ibcon#flushed, iclass 26, count 2 2006.173.14:35:23.26#ibcon#about to write, iclass 26, count 2 2006.173.14:35:23.26#ibcon#wrote, iclass 26, count 2 2006.173.14:35:23.26#ibcon#about to read 3, iclass 26, count 2 2006.173.14:35:23.29#ibcon#read 3, iclass 26, count 2 2006.173.14:35:23.29#ibcon#about to read 4, iclass 26, count 2 2006.173.14:35:23.29#ibcon#read 4, iclass 26, count 2 2006.173.14:35:23.29#ibcon#about to read 5, iclass 26, count 2 2006.173.14:35:23.29#ibcon#read 5, iclass 26, count 2 2006.173.14:35:23.29#ibcon#about to read 6, iclass 26, count 2 2006.173.14:35:23.29#ibcon#read 6, iclass 26, count 2 2006.173.14:35:23.29#ibcon#end of sib2, iclass 26, count 2 2006.173.14:35:23.29#ibcon#*after write, iclass 26, count 2 2006.173.14:35:23.29#ibcon#*before return 0, iclass 26, count 2 2006.173.14:35:23.29#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.14:35:23.29#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.14:35:23.29#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.14:35:23.29#ibcon#ireg 7 cls_cnt 0 2006.173.14:35:23.29#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.14:35:23.41#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.14:35:23.41#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.14:35:23.41#ibcon#enter wrdev, iclass 26, count 0 2006.173.14:35:23.41#ibcon#first serial, iclass 26, count 0 2006.173.14:35:23.41#ibcon#enter sib2, iclass 26, count 0 2006.173.14:35:23.41#ibcon#flushed, iclass 26, count 0 2006.173.14:35:23.41#ibcon#about to write, iclass 26, count 0 2006.173.14:35:23.41#ibcon#wrote, iclass 26, count 0 2006.173.14:35:23.41#ibcon#about to read 3, iclass 26, count 0 2006.173.14:35:23.43#ibcon#read 3, iclass 26, count 0 2006.173.14:35:23.43#ibcon#about to read 4, iclass 26, count 0 2006.173.14:35:23.43#ibcon#read 4, iclass 26, count 0 2006.173.14:35:23.43#ibcon#about to read 5, iclass 26, count 0 2006.173.14:35:23.43#ibcon#read 5, iclass 26, count 0 2006.173.14:35:23.43#ibcon#about to read 6, iclass 26, count 0 2006.173.14:35:23.43#ibcon#read 6, iclass 26, count 0 2006.173.14:35:23.43#ibcon#end of sib2, iclass 26, count 0 2006.173.14:35:23.43#ibcon#*mode == 0, iclass 26, count 0 2006.173.14:35:23.43#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.14:35:23.43#ibcon#[27=USB\r\n] 2006.173.14:35:23.43#ibcon#*before write, iclass 26, count 0 2006.173.14:35:23.43#ibcon#enter sib2, iclass 26, count 0 2006.173.14:35:23.43#ibcon#flushed, iclass 26, count 0 2006.173.14:35:23.43#ibcon#about to write, iclass 26, count 0 2006.173.14:35:23.43#ibcon#wrote, iclass 26, count 0 2006.173.14:35:23.43#ibcon#about to read 3, iclass 26, count 0 2006.173.14:35:23.46#ibcon#read 3, iclass 26, count 0 2006.173.14:35:23.46#ibcon#about to read 4, iclass 26, count 0 2006.173.14:35:23.46#ibcon#read 4, iclass 26, count 0 2006.173.14:35:23.46#ibcon#about to read 5, iclass 26, count 0 2006.173.14:35:23.46#ibcon#read 5, iclass 26, count 0 2006.173.14:35:23.46#ibcon#about to read 6, iclass 26, count 0 2006.173.14:35:23.46#ibcon#read 6, iclass 26, count 0 2006.173.14:35:23.46#ibcon#end of sib2, iclass 26, count 0 2006.173.14:35:23.46#ibcon#*after write, iclass 26, count 0 2006.173.14:35:23.46#ibcon#*before return 0, iclass 26, count 0 2006.173.14:35:23.46#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.14:35:23.46#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.14:35:23.46#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.14:35:23.46#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.14:35:23.46$vck44/vblo=3,649.99 2006.173.14:35:23.46#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.14:35:23.46#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.14:35:23.46#ibcon#ireg 17 cls_cnt 0 2006.173.14:35:23.46#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.14:35:23.46#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.14:35:23.46#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.14:35:23.46#ibcon#enter wrdev, iclass 28, count 0 2006.173.14:35:23.46#ibcon#first serial, iclass 28, count 0 2006.173.14:35:23.46#ibcon#enter sib2, iclass 28, count 0 2006.173.14:35:23.46#ibcon#flushed, iclass 28, count 0 2006.173.14:35:23.46#ibcon#about to write, iclass 28, count 0 2006.173.14:35:23.46#ibcon#wrote, iclass 28, count 0 2006.173.14:35:23.46#ibcon#about to read 3, iclass 28, count 0 2006.173.14:35:23.48#ibcon#read 3, iclass 28, count 0 2006.173.14:35:23.48#ibcon#about to read 4, iclass 28, count 0 2006.173.14:35:23.48#ibcon#read 4, iclass 28, count 0 2006.173.14:35:23.48#ibcon#about to read 5, iclass 28, count 0 2006.173.14:35:23.48#ibcon#read 5, iclass 28, count 0 2006.173.14:35:23.48#ibcon#about to read 6, iclass 28, count 0 2006.173.14:35:23.48#ibcon#read 6, iclass 28, count 0 2006.173.14:35:23.48#ibcon#end of sib2, iclass 28, count 0 2006.173.14:35:23.48#ibcon#*mode == 0, iclass 28, count 0 2006.173.14:35:23.48#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.14:35:23.48#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.14:35:23.48#ibcon#*before write, iclass 28, count 0 2006.173.14:35:23.48#ibcon#enter sib2, iclass 28, count 0 2006.173.14:35:23.48#ibcon#flushed, iclass 28, count 0 2006.173.14:35:23.48#ibcon#about to write, iclass 28, count 0 2006.173.14:35:23.48#ibcon#wrote, iclass 28, count 0 2006.173.14:35:23.48#ibcon#about to read 3, iclass 28, count 0 2006.173.14:35:23.52#ibcon#read 3, iclass 28, count 0 2006.173.14:35:23.52#ibcon#about to read 4, iclass 28, count 0 2006.173.14:35:23.52#ibcon#read 4, iclass 28, count 0 2006.173.14:35:23.52#ibcon#about to read 5, iclass 28, count 0 2006.173.14:35:23.52#ibcon#read 5, iclass 28, count 0 2006.173.14:35:23.52#ibcon#about to read 6, iclass 28, count 0 2006.173.14:35:23.52#ibcon#read 6, iclass 28, count 0 2006.173.14:35:23.52#ibcon#end of sib2, iclass 28, count 0 2006.173.14:35:23.52#ibcon#*after write, iclass 28, count 0 2006.173.14:35:23.52#ibcon#*before return 0, iclass 28, count 0 2006.173.14:35:23.52#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.14:35:23.52#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.14:35:23.52#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.14:35:23.52#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.14:35:23.52$vck44/vb=3,4 2006.173.14:35:23.52#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.14:35:23.52#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.14:35:23.52#ibcon#ireg 11 cls_cnt 2 2006.173.14:35:23.52#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.14:35:23.58#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.14:35:23.58#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.14:35:23.58#ibcon#enter wrdev, iclass 30, count 2 2006.173.14:35:23.58#ibcon#first serial, iclass 30, count 2 2006.173.14:35:23.58#ibcon#enter sib2, iclass 30, count 2 2006.173.14:35:23.58#ibcon#flushed, iclass 30, count 2 2006.173.14:35:23.58#ibcon#about to write, iclass 30, count 2 2006.173.14:35:23.58#ibcon#wrote, iclass 30, count 2 2006.173.14:35:23.58#ibcon#about to read 3, iclass 30, count 2 2006.173.14:35:23.60#ibcon#read 3, iclass 30, count 2 2006.173.14:35:23.60#ibcon#about to read 4, iclass 30, count 2 2006.173.14:35:23.60#ibcon#read 4, iclass 30, count 2 2006.173.14:35:23.60#ibcon#about to read 5, iclass 30, count 2 2006.173.14:35:23.60#ibcon#read 5, iclass 30, count 2 2006.173.14:35:23.60#ibcon#about to read 6, iclass 30, count 2 2006.173.14:35:23.60#ibcon#read 6, iclass 30, count 2 2006.173.14:35:23.60#ibcon#end of sib2, iclass 30, count 2 2006.173.14:35:23.60#ibcon#*mode == 0, iclass 30, count 2 2006.173.14:35:23.60#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.14:35:23.60#ibcon#[27=AT03-04\r\n] 2006.173.14:35:23.60#ibcon#*before write, iclass 30, count 2 2006.173.14:35:23.60#ibcon#enter sib2, iclass 30, count 2 2006.173.14:35:23.60#ibcon#flushed, iclass 30, count 2 2006.173.14:35:23.60#ibcon#about to write, iclass 30, count 2 2006.173.14:35:23.60#ibcon#wrote, iclass 30, count 2 2006.173.14:35:23.60#ibcon#about to read 3, iclass 30, count 2 2006.173.14:35:23.63#ibcon#read 3, iclass 30, count 2 2006.173.14:35:23.63#ibcon#about to read 4, iclass 30, count 2 2006.173.14:35:23.63#ibcon#read 4, iclass 30, count 2 2006.173.14:35:23.63#ibcon#about to read 5, iclass 30, count 2 2006.173.14:35:23.63#ibcon#read 5, iclass 30, count 2 2006.173.14:35:23.63#ibcon#about to read 6, iclass 30, count 2 2006.173.14:35:23.63#ibcon#read 6, iclass 30, count 2 2006.173.14:35:23.63#ibcon#end of sib2, iclass 30, count 2 2006.173.14:35:23.63#ibcon#*after write, iclass 30, count 2 2006.173.14:35:23.63#ibcon#*before return 0, iclass 30, count 2 2006.173.14:35:23.63#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.14:35:23.63#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.14:35:23.63#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.14:35:23.63#ibcon#ireg 7 cls_cnt 0 2006.173.14:35:23.63#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.14:35:23.75#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.14:35:23.75#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.14:35:23.75#ibcon#enter wrdev, iclass 30, count 0 2006.173.14:35:23.75#ibcon#first serial, iclass 30, count 0 2006.173.14:35:23.75#ibcon#enter sib2, iclass 30, count 0 2006.173.14:35:23.75#ibcon#flushed, iclass 30, count 0 2006.173.14:35:23.75#ibcon#about to write, iclass 30, count 0 2006.173.14:35:23.75#ibcon#wrote, iclass 30, count 0 2006.173.14:35:23.75#ibcon#about to read 3, iclass 30, count 0 2006.173.14:35:23.77#ibcon#read 3, iclass 30, count 0 2006.173.14:35:23.77#ibcon#about to read 4, iclass 30, count 0 2006.173.14:35:23.77#ibcon#read 4, iclass 30, count 0 2006.173.14:35:23.77#ibcon#about to read 5, iclass 30, count 0 2006.173.14:35:23.77#ibcon#read 5, iclass 30, count 0 2006.173.14:35:23.77#ibcon#about to read 6, iclass 30, count 0 2006.173.14:35:23.77#ibcon#read 6, iclass 30, count 0 2006.173.14:35:23.77#ibcon#end of sib2, iclass 30, count 0 2006.173.14:35:23.77#ibcon#*mode == 0, iclass 30, count 0 2006.173.14:35:23.77#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.14:35:23.77#ibcon#[27=USB\r\n] 2006.173.14:35:23.77#ibcon#*before write, iclass 30, count 0 2006.173.14:35:23.77#ibcon#enter sib2, iclass 30, count 0 2006.173.14:35:23.77#ibcon#flushed, iclass 30, count 0 2006.173.14:35:23.77#ibcon#about to write, iclass 30, count 0 2006.173.14:35:23.77#ibcon#wrote, iclass 30, count 0 2006.173.14:35:23.77#ibcon#about to read 3, iclass 30, count 0 2006.173.14:35:23.80#ibcon#read 3, iclass 30, count 0 2006.173.14:35:23.80#ibcon#about to read 4, iclass 30, count 0 2006.173.14:35:23.80#ibcon#read 4, iclass 30, count 0 2006.173.14:35:23.80#ibcon#about to read 5, iclass 30, count 0 2006.173.14:35:23.80#ibcon#read 5, iclass 30, count 0 2006.173.14:35:23.80#ibcon#about to read 6, iclass 30, count 0 2006.173.14:35:23.80#ibcon#read 6, iclass 30, count 0 2006.173.14:35:23.80#ibcon#end of sib2, iclass 30, count 0 2006.173.14:35:23.80#ibcon#*after write, iclass 30, count 0 2006.173.14:35:23.80#ibcon#*before return 0, iclass 30, count 0 2006.173.14:35:23.80#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.14:35:23.80#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.14:35:23.80#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.14:35:23.80#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.14:35:23.80$vck44/vblo=4,679.99 2006.173.14:35:23.80#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.14:35:23.80#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.14:35:23.80#ibcon#ireg 17 cls_cnt 0 2006.173.14:35:23.80#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.14:35:23.80#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.14:35:23.80#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.14:35:23.80#ibcon#enter wrdev, iclass 32, count 0 2006.173.14:35:23.80#ibcon#first serial, iclass 32, count 0 2006.173.14:35:23.80#ibcon#enter sib2, iclass 32, count 0 2006.173.14:35:23.80#ibcon#flushed, iclass 32, count 0 2006.173.14:35:23.80#ibcon#about to write, iclass 32, count 0 2006.173.14:35:23.80#ibcon#wrote, iclass 32, count 0 2006.173.14:35:23.80#ibcon#about to read 3, iclass 32, count 0 2006.173.14:35:23.82#ibcon#read 3, iclass 32, count 0 2006.173.14:35:23.82#ibcon#about to read 4, iclass 32, count 0 2006.173.14:35:23.82#ibcon#read 4, iclass 32, count 0 2006.173.14:35:23.82#ibcon#about to read 5, iclass 32, count 0 2006.173.14:35:23.82#ibcon#read 5, iclass 32, count 0 2006.173.14:35:23.82#ibcon#about to read 6, iclass 32, count 0 2006.173.14:35:23.82#ibcon#read 6, iclass 32, count 0 2006.173.14:35:23.82#ibcon#end of sib2, iclass 32, count 0 2006.173.14:35:23.82#ibcon#*mode == 0, iclass 32, count 0 2006.173.14:35:23.82#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.14:35:23.82#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.14:35:23.82#ibcon#*before write, iclass 32, count 0 2006.173.14:35:23.82#ibcon#enter sib2, iclass 32, count 0 2006.173.14:35:23.82#ibcon#flushed, iclass 32, count 0 2006.173.14:35:23.82#ibcon#about to write, iclass 32, count 0 2006.173.14:35:23.82#ibcon#wrote, iclass 32, count 0 2006.173.14:35:23.82#ibcon#about to read 3, iclass 32, count 0 2006.173.14:35:23.86#ibcon#read 3, iclass 32, count 0 2006.173.14:35:23.86#ibcon#about to read 4, iclass 32, count 0 2006.173.14:35:23.86#ibcon#read 4, iclass 32, count 0 2006.173.14:35:23.86#ibcon#about to read 5, iclass 32, count 0 2006.173.14:35:23.86#ibcon#read 5, iclass 32, count 0 2006.173.14:35:23.86#ibcon#about to read 6, iclass 32, count 0 2006.173.14:35:23.86#ibcon#read 6, iclass 32, count 0 2006.173.14:35:23.86#ibcon#end of sib2, iclass 32, count 0 2006.173.14:35:23.86#ibcon#*after write, iclass 32, count 0 2006.173.14:35:23.86#ibcon#*before return 0, iclass 32, count 0 2006.173.14:35:23.86#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.14:35:23.86#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.14:35:23.86#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.14:35:23.86#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.14:35:23.86$vck44/vb=4,4 2006.173.14:35:23.86#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.14:35:23.86#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.14:35:23.86#ibcon#ireg 11 cls_cnt 2 2006.173.14:35:23.86#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.14:35:23.92#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.14:35:23.92#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.14:35:23.92#ibcon#enter wrdev, iclass 34, count 2 2006.173.14:35:23.92#ibcon#first serial, iclass 34, count 2 2006.173.14:35:23.92#ibcon#enter sib2, iclass 34, count 2 2006.173.14:35:23.92#ibcon#flushed, iclass 34, count 2 2006.173.14:35:23.92#ibcon#about to write, iclass 34, count 2 2006.173.14:35:23.92#ibcon#wrote, iclass 34, count 2 2006.173.14:35:23.92#ibcon#about to read 3, iclass 34, count 2 2006.173.14:35:23.94#ibcon#read 3, iclass 34, count 2 2006.173.14:35:23.94#ibcon#about to read 4, iclass 34, count 2 2006.173.14:35:23.94#ibcon#read 4, iclass 34, count 2 2006.173.14:35:23.94#ibcon#about to read 5, iclass 34, count 2 2006.173.14:35:23.94#ibcon#read 5, iclass 34, count 2 2006.173.14:35:23.94#ibcon#about to read 6, iclass 34, count 2 2006.173.14:35:23.94#ibcon#read 6, iclass 34, count 2 2006.173.14:35:23.94#ibcon#end of sib2, iclass 34, count 2 2006.173.14:35:23.94#ibcon#*mode == 0, iclass 34, count 2 2006.173.14:35:23.94#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.14:35:23.94#ibcon#[27=AT04-04\r\n] 2006.173.14:35:23.94#ibcon#*before write, iclass 34, count 2 2006.173.14:35:23.94#ibcon#enter sib2, iclass 34, count 2 2006.173.14:35:23.94#ibcon#flushed, iclass 34, count 2 2006.173.14:35:23.94#ibcon#about to write, iclass 34, count 2 2006.173.14:35:23.94#ibcon#wrote, iclass 34, count 2 2006.173.14:35:23.94#ibcon#about to read 3, iclass 34, count 2 2006.173.14:35:23.97#ibcon#read 3, iclass 34, count 2 2006.173.14:35:23.97#ibcon#about to read 4, iclass 34, count 2 2006.173.14:35:23.97#ibcon#read 4, iclass 34, count 2 2006.173.14:35:23.97#ibcon#about to read 5, iclass 34, count 2 2006.173.14:35:23.97#ibcon#read 5, iclass 34, count 2 2006.173.14:35:23.97#ibcon#about to read 6, iclass 34, count 2 2006.173.14:35:23.97#ibcon#read 6, iclass 34, count 2 2006.173.14:35:23.97#ibcon#end of sib2, iclass 34, count 2 2006.173.14:35:23.97#ibcon#*after write, iclass 34, count 2 2006.173.14:35:23.97#ibcon#*before return 0, iclass 34, count 2 2006.173.14:35:23.97#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.14:35:23.97#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.14:35:23.97#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.14:35:23.97#ibcon#ireg 7 cls_cnt 0 2006.173.14:35:23.97#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.14:35:24.09#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.14:35:24.09#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.14:35:24.09#ibcon#enter wrdev, iclass 34, count 0 2006.173.14:35:24.09#ibcon#first serial, iclass 34, count 0 2006.173.14:35:24.09#ibcon#enter sib2, iclass 34, count 0 2006.173.14:35:24.09#ibcon#flushed, iclass 34, count 0 2006.173.14:35:24.09#ibcon#about to write, iclass 34, count 0 2006.173.14:35:24.09#ibcon#wrote, iclass 34, count 0 2006.173.14:35:24.09#ibcon#about to read 3, iclass 34, count 0 2006.173.14:35:24.11#ibcon#read 3, iclass 34, count 0 2006.173.14:35:24.11#ibcon#about to read 4, iclass 34, count 0 2006.173.14:35:24.11#ibcon#read 4, iclass 34, count 0 2006.173.14:35:24.11#ibcon#about to read 5, iclass 34, count 0 2006.173.14:35:24.11#ibcon#read 5, iclass 34, count 0 2006.173.14:35:24.11#ibcon#about to read 6, iclass 34, count 0 2006.173.14:35:24.11#ibcon#read 6, iclass 34, count 0 2006.173.14:35:24.11#ibcon#end of sib2, iclass 34, count 0 2006.173.14:35:24.11#ibcon#*mode == 0, iclass 34, count 0 2006.173.14:35:24.11#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.14:35:24.11#ibcon#[27=USB\r\n] 2006.173.14:35:24.11#ibcon#*before write, iclass 34, count 0 2006.173.14:35:24.11#ibcon#enter sib2, iclass 34, count 0 2006.173.14:35:24.11#ibcon#flushed, iclass 34, count 0 2006.173.14:35:24.11#ibcon#about to write, iclass 34, count 0 2006.173.14:35:24.11#ibcon#wrote, iclass 34, count 0 2006.173.14:35:24.11#ibcon#about to read 3, iclass 34, count 0 2006.173.14:35:24.14#ibcon#read 3, iclass 34, count 0 2006.173.14:35:24.14#ibcon#about to read 4, iclass 34, count 0 2006.173.14:35:24.14#ibcon#read 4, iclass 34, count 0 2006.173.14:35:24.14#ibcon#about to read 5, iclass 34, count 0 2006.173.14:35:24.14#ibcon#read 5, iclass 34, count 0 2006.173.14:35:24.14#ibcon#about to read 6, iclass 34, count 0 2006.173.14:35:24.14#ibcon#read 6, iclass 34, count 0 2006.173.14:35:24.14#ibcon#end of sib2, iclass 34, count 0 2006.173.14:35:24.14#ibcon#*after write, iclass 34, count 0 2006.173.14:35:24.14#ibcon#*before return 0, iclass 34, count 0 2006.173.14:35:24.14#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.14:35:24.14#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.14:35:24.14#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.14:35:24.14#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.14:35:24.14$vck44/vblo=5,709.99 2006.173.14:35:24.14#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.14:35:24.14#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.14:35:24.14#ibcon#ireg 17 cls_cnt 0 2006.173.14:35:24.14#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.14:35:24.14#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.14:35:24.14#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.14:35:24.14#ibcon#enter wrdev, iclass 36, count 0 2006.173.14:35:24.14#ibcon#first serial, iclass 36, count 0 2006.173.14:35:24.14#ibcon#enter sib2, iclass 36, count 0 2006.173.14:35:24.14#ibcon#flushed, iclass 36, count 0 2006.173.14:35:24.14#ibcon#about to write, iclass 36, count 0 2006.173.14:35:24.14#ibcon#wrote, iclass 36, count 0 2006.173.14:35:24.14#ibcon#about to read 3, iclass 36, count 0 2006.173.14:35:24.16#ibcon#read 3, iclass 36, count 0 2006.173.14:35:24.16#ibcon#about to read 4, iclass 36, count 0 2006.173.14:35:24.16#ibcon#read 4, iclass 36, count 0 2006.173.14:35:24.16#ibcon#about to read 5, iclass 36, count 0 2006.173.14:35:24.16#ibcon#read 5, iclass 36, count 0 2006.173.14:35:24.16#ibcon#about to read 6, iclass 36, count 0 2006.173.14:35:24.16#ibcon#read 6, iclass 36, count 0 2006.173.14:35:24.16#ibcon#end of sib2, iclass 36, count 0 2006.173.14:35:24.16#ibcon#*mode == 0, iclass 36, count 0 2006.173.14:35:24.16#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.14:35:24.16#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.14:35:24.16#ibcon#*before write, iclass 36, count 0 2006.173.14:35:24.16#ibcon#enter sib2, iclass 36, count 0 2006.173.14:35:24.16#ibcon#flushed, iclass 36, count 0 2006.173.14:35:24.16#ibcon#about to write, iclass 36, count 0 2006.173.14:35:24.16#ibcon#wrote, iclass 36, count 0 2006.173.14:35:24.16#ibcon#about to read 3, iclass 36, count 0 2006.173.14:35:24.20#ibcon#read 3, iclass 36, count 0 2006.173.14:35:24.20#ibcon#about to read 4, iclass 36, count 0 2006.173.14:35:24.20#ibcon#read 4, iclass 36, count 0 2006.173.14:35:24.20#ibcon#about to read 5, iclass 36, count 0 2006.173.14:35:24.20#ibcon#read 5, iclass 36, count 0 2006.173.14:35:24.20#ibcon#about to read 6, iclass 36, count 0 2006.173.14:35:24.20#ibcon#read 6, iclass 36, count 0 2006.173.14:35:24.20#ibcon#end of sib2, iclass 36, count 0 2006.173.14:35:24.20#ibcon#*after write, iclass 36, count 0 2006.173.14:35:24.20#ibcon#*before return 0, iclass 36, count 0 2006.173.14:35:24.20#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.14:35:24.20#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.14:35:24.20#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.14:35:24.20#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.14:35:24.20$vck44/vb=5,4 2006.173.14:35:24.20#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.14:35:24.20#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.14:35:24.20#ibcon#ireg 11 cls_cnt 2 2006.173.14:35:24.20#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.14:35:24.26#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.14:35:24.26#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.14:35:24.26#ibcon#enter wrdev, iclass 38, count 2 2006.173.14:35:24.26#ibcon#first serial, iclass 38, count 2 2006.173.14:35:24.26#ibcon#enter sib2, iclass 38, count 2 2006.173.14:35:24.26#ibcon#flushed, iclass 38, count 2 2006.173.14:35:24.26#ibcon#about to write, iclass 38, count 2 2006.173.14:35:24.26#ibcon#wrote, iclass 38, count 2 2006.173.14:35:24.26#ibcon#about to read 3, iclass 38, count 2 2006.173.14:35:24.28#ibcon#read 3, iclass 38, count 2 2006.173.14:35:24.28#ibcon#about to read 4, iclass 38, count 2 2006.173.14:35:24.28#ibcon#read 4, iclass 38, count 2 2006.173.14:35:24.28#ibcon#about to read 5, iclass 38, count 2 2006.173.14:35:24.28#ibcon#read 5, iclass 38, count 2 2006.173.14:35:24.28#ibcon#about to read 6, iclass 38, count 2 2006.173.14:35:24.28#ibcon#read 6, iclass 38, count 2 2006.173.14:35:24.28#ibcon#end of sib2, iclass 38, count 2 2006.173.14:35:24.28#ibcon#*mode == 0, iclass 38, count 2 2006.173.14:35:24.28#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.14:35:24.28#ibcon#[27=AT05-04\r\n] 2006.173.14:35:24.28#ibcon#*before write, iclass 38, count 2 2006.173.14:35:24.28#ibcon#enter sib2, iclass 38, count 2 2006.173.14:35:24.28#ibcon#flushed, iclass 38, count 2 2006.173.14:35:24.28#ibcon#about to write, iclass 38, count 2 2006.173.14:35:24.28#ibcon#wrote, iclass 38, count 2 2006.173.14:35:24.28#ibcon#about to read 3, iclass 38, count 2 2006.173.14:35:24.31#ibcon#read 3, iclass 38, count 2 2006.173.14:35:24.31#ibcon#about to read 4, iclass 38, count 2 2006.173.14:35:24.31#ibcon#read 4, iclass 38, count 2 2006.173.14:35:24.31#ibcon#about to read 5, iclass 38, count 2 2006.173.14:35:24.31#ibcon#read 5, iclass 38, count 2 2006.173.14:35:24.31#ibcon#about to read 6, iclass 38, count 2 2006.173.14:35:24.31#ibcon#read 6, iclass 38, count 2 2006.173.14:35:24.31#ibcon#end of sib2, iclass 38, count 2 2006.173.14:35:24.31#ibcon#*after write, iclass 38, count 2 2006.173.14:35:24.31#ibcon#*before return 0, iclass 38, count 2 2006.173.14:35:24.31#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.14:35:24.31#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.14:35:24.31#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.14:35:24.31#ibcon#ireg 7 cls_cnt 0 2006.173.14:35:24.31#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.14:35:24.43#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.14:35:24.43#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.14:35:24.43#ibcon#enter wrdev, iclass 38, count 0 2006.173.14:35:24.43#ibcon#first serial, iclass 38, count 0 2006.173.14:35:24.43#ibcon#enter sib2, iclass 38, count 0 2006.173.14:35:24.43#ibcon#flushed, iclass 38, count 0 2006.173.14:35:24.43#ibcon#about to write, iclass 38, count 0 2006.173.14:35:24.43#ibcon#wrote, iclass 38, count 0 2006.173.14:35:24.43#ibcon#about to read 3, iclass 38, count 0 2006.173.14:35:24.45#ibcon#read 3, iclass 38, count 0 2006.173.14:35:24.45#ibcon#about to read 4, iclass 38, count 0 2006.173.14:35:24.45#ibcon#read 4, iclass 38, count 0 2006.173.14:35:24.45#ibcon#about to read 5, iclass 38, count 0 2006.173.14:35:24.45#ibcon#read 5, iclass 38, count 0 2006.173.14:35:24.45#ibcon#about to read 6, iclass 38, count 0 2006.173.14:35:24.45#ibcon#read 6, iclass 38, count 0 2006.173.14:35:24.45#ibcon#end of sib2, iclass 38, count 0 2006.173.14:35:24.45#ibcon#*mode == 0, iclass 38, count 0 2006.173.14:35:24.45#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.14:35:24.45#ibcon#[27=USB\r\n] 2006.173.14:35:24.45#ibcon#*before write, iclass 38, count 0 2006.173.14:35:24.45#ibcon#enter sib2, iclass 38, count 0 2006.173.14:35:24.45#ibcon#flushed, iclass 38, count 0 2006.173.14:35:24.45#ibcon#about to write, iclass 38, count 0 2006.173.14:35:24.45#ibcon#wrote, iclass 38, count 0 2006.173.14:35:24.45#ibcon#about to read 3, iclass 38, count 0 2006.173.14:35:24.48#ibcon#read 3, iclass 38, count 0 2006.173.14:35:24.48#ibcon#about to read 4, iclass 38, count 0 2006.173.14:35:24.48#ibcon#read 4, iclass 38, count 0 2006.173.14:35:24.48#ibcon#about to read 5, iclass 38, count 0 2006.173.14:35:24.48#ibcon#read 5, iclass 38, count 0 2006.173.14:35:24.48#ibcon#about to read 6, iclass 38, count 0 2006.173.14:35:24.48#ibcon#read 6, iclass 38, count 0 2006.173.14:35:24.48#ibcon#end of sib2, iclass 38, count 0 2006.173.14:35:24.48#ibcon#*after write, iclass 38, count 0 2006.173.14:35:24.48#ibcon#*before return 0, iclass 38, count 0 2006.173.14:35:24.48#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.14:35:24.48#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.14:35:24.48#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.14:35:24.48#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.14:35:24.48$vck44/vblo=6,719.99 2006.173.14:35:24.48#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.14:35:24.48#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.14:35:24.48#ibcon#ireg 17 cls_cnt 0 2006.173.14:35:24.48#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.14:35:24.48#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.14:35:24.48#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.14:35:24.48#ibcon#enter wrdev, iclass 40, count 0 2006.173.14:35:24.48#ibcon#first serial, iclass 40, count 0 2006.173.14:35:24.48#ibcon#enter sib2, iclass 40, count 0 2006.173.14:35:24.48#ibcon#flushed, iclass 40, count 0 2006.173.14:35:24.48#ibcon#about to write, iclass 40, count 0 2006.173.14:35:24.48#ibcon#wrote, iclass 40, count 0 2006.173.14:35:24.48#ibcon#about to read 3, iclass 40, count 0 2006.173.14:35:24.50#ibcon#read 3, iclass 40, count 0 2006.173.14:35:24.50#ibcon#about to read 4, iclass 40, count 0 2006.173.14:35:24.50#ibcon#read 4, iclass 40, count 0 2006.173.14:35:24.50#ibcon#about to read 5, iclass 40, count 0 2006.173.14:35:24.50#ibcon#read 5, iclass 40, count 0 2006.173.14:35:24.50#ibcon#about to read 6, iclass 40, count 0 2006.173.14:35:24.50#ibcon#read 6, iclass 40, count 0 2006.173.14:35:24.50#ibcon#end of sib2, iclass 40, count 0 2006.173.14:35:24.50#ibcon#*mode == 0, iclass 40, count 0 2006.173.14:35:24.50#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.14:35:24.50#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.14:35:24.50#ibcon#*before write, iclass 40, count 0 2006.173.14:35:24.50#ibcon#enter sib2, iclass 40, count 0 2006.173.14:35:24.50#ibcon#flushed, iclass 40, count 0 2006.173.14:35:24.50#ibcon#about to write, iclass 40, count 0 2006.173.14:35:24.50#ibcon#wrote, iclass 40, count 0 2006.173.14:35:24.50#ibcon#about to read 3, iclass 40, count 0 2006.173.14:35:24.54#ibcon#read 3, iclass 40, count 0 2006.173.14:35:24.54#ibcon#about to read 4, iclass 40, count 0 2006.173.14:35:24.54#ibcon#read 4, iclass 40, count 0 2006.173.14:35:24.54#ibcon#about to read 5, iclass 40, count 0 2006.173.14:35:24.54#ibcon#read 5, iclass 40, count 0 2006.173.14:35:24.54#ibcon#about to read 6, iclass 40, count 0 2006.173.14:35:24.54#ibcon#read 6, iclass 40, count 0 2006.173.14:35:24.54#ibcon#end of sib2, iclass 40, count 0 2006.173.14:35:24.54#ibcon#*after write, iclass 40, count 0 2006.173.14:35:24.54#ibcon#*before return 0, iclass 40, count 0 2006.173.14:35:24.54#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.14:35:24.54#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.14:35:24.54#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.14:35:24.54#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.14:35:24.54$vck44/vb=6,4 2006.173.14:35:24.54#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.14:35:24.54#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.14:35:24.54#ibcon#ireg 11 cls_cnt 2 2006.173.14:35:24.54#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.14:35:24.60#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.14:35:24.60#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.14:35:24.60#ibcon#enter wrdev, iclass 4, count 2 2006.173.14:35:24.60#ibcon#first serial, iclass 4, count 2 2006.173.14:35:24.60#ibcon#enter sib2, iclass 4, count 2 2006.173.14:35:24.60#ibcon#flushed, iclass 4, count 2 2006.173.14:35:24.60#ibcon#about to write, iclass 4, count 2 2006.173.14:35:24.60#ibcon#wrote, iclass 4, count 2 2006.173.14:35:24.60#ibcon#about to read 3, iclass 4, count 2 2006.173.14:35:24.62#ibcon#read 3, iclass 4, count 2 2006.173.14:35:24.62#ibcon#about to read 4, iclass 4, count 2 2006.173.14:35:24.62#ibcon#read 4, iclass 4, count 2 2006.173.14:35:24.62#ibcon#about to read 5, iclass 4, count 2 2006.173.14:35:24.62#ibcon#read 5, iclass 4, count 2 2006.173.14:35:24.62#ibcon#about to read 6, iclass 4, count 2 2006.173.14:35:24.62#ibcon#read 6, iclass 4, count 2 2006.173.14:35:24.62#ibcon#end of sib2, iclass 4, count 2 2006.173.14:35:24.62#ibcon#*mode == 0, iclass 4, count 2 2006.173.14:35:24.62#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.14:35:24.62#ibcon#[27=AT06-04\r\n] 2006.173.14:35:24.62#ibcon#*before write, iclass 4, count 2 2006.173.14:35:24.62#ibcon#enter sib2, iclass 4, count 2 2006.173.14:35:24.62#ibcon#flushed, iclass 4, count 2 2006.173.14:35:24.62#ibcon#about to write, iclass 4, count 2 2006.173.14:35:24.62#ibcon#wrote, iclass 4, count 2 2006.173.14:35:24.62#ibcon#about to read 3, iclass 4, count 2 2006.173.14:35:24.65#ibcon#read 3, iclass 4, count 2 2006.173.14:35:24.65#ibcon#about to read 4, iclass 4, count 2 2006.173.14:35:24.65#ibcon#read 4, iclass 4, count 2 2006.173.14:35:24.65#ibcon#about to read 5, iclass 4, count 2 2006.173.14:35:24.65#ibcon#read 5, iclass 4, count 2 2006.173.14:35:24.65#ibcon#about to read 6, iclass 4, count 2 2006.173.14:35:24.65#ibcon#read 6, iclass 4, count 2 2006.173.14:35:24.65#ibcon#end of sib2, iclass 4, count 2 2006.173.14:35:24.65#ibcon#*after write, iclass 4, count 2 2006.173.14:35:24.65#ibcon#*before return 0, iclass 4, count 2 2006.173.14:35:24.65#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.14:35:24.65#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.14:35:24.65#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.14:35:24.65#ibcon#ireg 7 cls_cnt 0 2006.173.14:35:24.65#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.14:35:24.77#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.14:35:24.77#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.14:35:24.77#ibcon#enter wrdev, iclass 4, count 0 2006.173.14:35:24.77#ibcon#first serial, iclass 4, count 0 2006.173.14:35:24.77#ibcon#enter sib2, iclass 4, count 0 2006.173.14:35:24.77#ibcon#flushed, iclass 4, count 0 2006.173.14:35:24.77#ibcon#about to write, iclass 4, count 0 2006.173.14:35:24.77#ibcon#wrote, iclass 4, count 0 2006.173.14:35:24.77#ibcon#about to read 3, iclass 4, count 0 2006.173.14:35:24.79#ibcon#read 3, iclass 4, count 0 2006.173.14:35:24.79#ibcon#about to read 4, iclass 4, count 0 2006.173.14:35:24.79#ibcon#read 4, iclass 4, count 0 2006.173.14:35:24.79#ibcon#about to read 5, iclass 4, count 0 2006.173.14:35:24.79#ibcon#read 5, iclass 4, count 0 2006.173.14:35:24.79#ibcon#about to read 6, iclass 4, count 0 2006.173.14:35:24.79#ibcon#read 6, iclass 4, count 0 2006.173.14:35:24.79#ibcon#end of sib2, iclass 4, count 0 2006.173.14:35:24.79#ibcon#*mode == 0, iclass 4, count 0 2006.173.14:35:24.79#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.14:35:24.79#ibcon#[27=USB\r\n] 2006.173.14:35:24.79#ibcon#*before write, iclass 4, count 0 2006.173.14:35:24.79#ibcon#enter sib2, iclass 4, count 0 2006.173.14:35:24.79#ibcon#flushed, iclass 4, count 0 2006.173.14:35:24.79#ibcon#about to write, iclass 4, count 0 2006.173.14:35:24.79#ibcon#wrote, iclass 4, count 0 2006.173.14:35:24.79#ibcon#about to read 3, iclass 4, count 0 2006.173.14:35:24.82#ibcon#read 3, iclass 4, count 0 2006.173.14:35:24.82#ibcon#about to read 4, iclass 4, count 0 2006.173.14:35:24.82#ibcon#read 4, iclass 4, count 0 2006.173.14:35:24.82#ibcon#about to read 5, iclass 4, count 0 2006.173.14:35:24.82#ibcon#read 5, iclass 4, count 0 2006.173.14:35:24.82#ibcon#about to read 6, iclass 4, count 0 2006.173.14:35:24.82#ibcon#read 6, iclass 4, count 0 2006.173.14:35:24.82#ibcon#end of sib2, iclass 4, count 0 2006.173.14:35:24.82#ibcon#*after write, iclass 4, count 0 2006.173.14:35:24.82#ibcon#*before return 0, iclass 4, count 0 2006.173.14:35:24.82#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.14:35:24.82#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.14:35:24.82#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.14:35:24.82#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.14:35:24.82$vck44/vblo=7,734.99 2006.173.14:35:24.82#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.14:35:24.82#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.14:35:24.82#ibcon#ireg 17 cls_cnt 0 2006.173.14:35:24.82#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.14:35:24.82#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.14:35:24.82#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.14:35:24.82#ibcon#enter wrdev, iclass 6, count 0 2006.173.14:35:24.82#ibcon#first serial, iclass 6, count 0 2006.173.14:35:24.82#ibcon#enter sib2, iclass 6, count 0 2006.173.14:35:24.82#ibcon#flushed, iclass 6, count 0 2006.173.14:35:24.82#ibcon#about to write, iclass 6, count 0 2006.173.14:35:24.82#ibcon#wrote, iclass 6, count 0 2006.173.14:35:24.82#ibcon#about to read 3, iclass 6, count 0 2006.173.14:35:24.84#ibcon#read 3, iclass 6, count 0 2006.173.14:35:24.84#ibcon#about to read 4, iclass 6, count 0 2006.173.14:35:24.84#ibcon#read 4, iclass 6, count 0 2006.173.14:35:24.84#ibcon#about to read 5, iclass 6, count 0 2006.173.14:35:24.84#ibcon#read 5, iclass 6, count 0 2006.173.14:35:24.84#ibcon#about to read 6, iclass 6, count 0 2006.173.14:35:24.84#ibcon#read 6, iclass 6, count 0 2006.173.14:35:24.84#ibcon#end of sib2, iclass 6, count 0 2006.173.14:35:24.84#ibcon#*mode == 0, iclass 6, count 0 2006.173.14:35:24.84#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.14:35:24.84#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.14:35:24.84#ibcon#*before write, iclass 6, count 0 2006.173.14:35:24.84#ibcon#enter sib2, iclass 6, count 0 2006.173.14:35:24.84#ibcon#flushed, iclass 6, count 0 2006.173.14:35:24.84#ibcon#about to write, iclass 6, count 0 2006.173.14:35:24.84#ibcon#wrote, iclass 6, count 0 2006.173.14:35:24.84#ibcon#about to read 3, iclass 6, count 0 2006.173.14:35:24.88#ibcon#read 3, iclass 6, count 0 2006.173.14:35:24.88#ibcon#about to read 4, iclass 6, count 0 2006.173.14:35:24.88#ibcon#read 4, iclass 6, count 0 2006.173.14:35:24.88#ibcon#about to read 5, iclass 6, count 0 2006.173.14:35:24.88#ibcon#read 5, iclass 6, count 0 2006.173.14:35:24.88#ibcon#about to read 6, iclass 6, count 0 2006.173.14:35:24.88#ibcon#read 6, iclass 6, count 0 2006.173.14:35:24.88#ibcon#end of sib2, iclass 6, count 0 2006.173.14:35:24.88#ibcon#*after write, iclass 6, count 0 2006.173.14:35:24.88#ibcon#*before return 0, iclass 6, count 0 2006.173.14:35:24.88#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.14:35:24.88#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.14:35:24.88#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.14:35:24.88#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.14:35:24.88$vck44/vb=7,4 2006.173.14:35:24.88#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.14:35:24.88#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.14:35:24.88#ibcon#ireg 11 cls_cnt 2 2006.173.14:35:24.88#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.14:35:24.94#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.14:35:24.94#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.14:35:24.94#ibcon#enter wrdev, iclass 10, count 2 2006.173.14:35:24.94#ibcon#first serial, iclass 10, count 2 2006.173.14:35:24.94#ibcon#enter sib2, iclass 10, count 2 2006.173.14:35:24.94#ibcon#flushed, iclass 10, count 2 2006.173.14:35:24.94#ibcon#about to write, iclass 10, count 2 2006.173.14:35:24.94#ibcon#wrote, iclass 10, count 2 2006.173.14:35:24.94#ibcon#about to read 3, iclass 10, count 2 2006.173.14:35:24.96#ibcon#read 3, iclass 10, count 2 2006.173.14:35:24.96#ibcon#about to read 4, iclass 10, count 2 2006.173.14:35:24.96#ibcon#read 4, iclass 10, count 2 2006.173.14:35:24.96#ibcon#about to read 5, iclass 10, count 2 2006.173.14:35:24.96#ibcon#read 5, iclass 10, count 2 2006.173.14:35:24.96#ibcon#about to read 6, iclass 10, count 2 2006.173.14:35:24.96#ibcon#read 6, iclass 10, count 2 2006.173.14:35:24.96#ibcon#end of sib2, iclass 10, count 2 2006.173.14:35:24.96#ibcon#*mode == 0, iclass 10, count 2 2006.173.14:35:24.96#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.14:35:24.96#ibcon#[27=AT07-04\r\n] 2006.173.14:35:24.96#ibcon#*before write, iclass 10, count 2 2006.173.14:35:24.96#ibcon#enter sib2, iclass 10, count 2 2006.173.14:35:24.96#ibcon#flushed, iclass 10, count 2 2006.173.14:35:24.96#ibcon#about to write, iclass 10, count 2 2006.173.14:35:24.96#ibcon#wrote, iclass 10, count 2 2006.173.14:35:24.96#ibcon#about to read 3, iclass 10, count 2 2006.173.14:35:24.99#ibcon#read 3, iclass 10, count 2 2006.173.14:35:24.99#ibcon#about to read 4, iclass 10, count 2 2006.173.14:35:24.99#ibcon#read 4, iclass 10, count 2 2006.173.14:35:24.99#ibcon#about to read 5, iclass 10, count 2 2006.173.14:35:24.99#ibcon#read 5, iclass 10, count 2 2006.173.14:35:24.99#ibcon#about to read 6, iclass 10, count 2 2006.173.14:35:24.99#ibcon#read 6, iclass 10, count 2 2006.173.14:35:24.99#ibcon#end of sib2, iclass 10, count 2 2006.173.14:35:24.99#ibcon#*after write, iclass 10, count 2 2006.173.14:35:24.99#ibcon#*before return 0, iclass 10, count 2 2006.173.14:35:24.99#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.14:35:24.99#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.14:35:24.99#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.14:35:24.99#ibcon#ireg 7 cls_cnt 0 2006.173.14:35:24.99#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.14:35:25.11#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.14:35:25.11#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.14:35:25.11#ibcon#enter wrdev, iclass 10, count 0 2006.173.14:35:25.11#ibcon#first serial, iclass 10, count 0 2006.173.14:35:25.11#ibcon#enter sib2, iclass 10, count 0 2006.173.14:35:25.11#ibcon#flushed, iclass 10, count 0 2006.173.14:35:25.11#ibcon#about to write, iclass 10, count 0 2006.173.14:35:25.11#ibcon#wrote, iclass 10, count 0 2006.173.14:35:25.11#ibcon#about to read 3, iclass 10, count 0 2006.173.14:35:25.13#ibcon#read 3, iclass 10, count 0 2006.173.14:35:25.13#ibcon#about to read 4, iclass 10, count 0 2006.173.14:35:25.13#ibcon#read 4, iclass 10, count 0 2006.173.14:35:25.13#ibcon#about to read 5, iclass 10, count 0 2006.173.14:35:25.13#ibcon#read 5, iclass 10, count 0 2006.173.14:35:25.13#ibcon#about to read 6, iclass 10, count 0 2006.173.14:35:25.13#ibcon#read 6, iclass 10, count 0 2006.173.14:35:25.13#ibcon#end of sib2, iclass 10, count 0 2006.173.14:35:25.13#ibcon#*mode == 0, iclass 10, count 0 2006.173.14:35:25.13#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.14:35:25.13#ibcon#[27=USB\r\n] 2006.173.14:35:25.13#ibcon#*before write, iclass 10, count 0 2006.173.14:35:25.13#ibcon#enter sib2, iclass 10, count 0 2006.173.14:35:25.13#ibcon#flushed, iclass 10, count 0 2006.173.14:35:25.13#ibcon#about to write, iclass 10, count 0 2006.173.14:35:25.13#ibcon#wrote, iclass 10, count 0 2006.173.14:35:25.13#ibcon#about to read 3, iclass 10, count 0 2006.173.14:35:25.16#ibcon#read 3, iclass 10, count 0 2006.173.14:35:25.16#ibcon#about to read 4, iclass 10, count 0 2006.173.14:35:25.16#ibcon#read 4, iclass 10, count 0 2006.173.14:35:25.16#ibcon#about to read 5, iclass 10, count 0 2006.173.14:35:25.16#ibcon#read 5, iclass 10, count 0 2006.173.14:35:25.16#ibcon#about to read 6, iclass 10, count 0 2006.173.14:35:25.16#ibcon#read 6, iclass 10, count 0 2006.173.14:35:25.16#ibcon#end of sib2, iclass 10, count 0 2006.173.14:35:25.16#ibcon#*after write, iclass 10, count 0 2006.173.14:35:25.16#ibcon#*before return 0, iclass 10, count 0 2006.173.14:35:25.16#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.14:35:25.16#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.14:35:25.16#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.14:35:25.16#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.14:35:25.16$vck44/vblo=8,744.99 2006.173.14:35:25.16#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.14:35:25.16#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.14:35:25.16#ibcon#ireg 17 cls_cnt 0 2006.173.14:35:25.16#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.14:35:25.16#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.14:35:25.16#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.14:35:25.16#ibcon#enter wrdev, iclass 12, count 0 2006.173.14:35:25.16#ibcon#first serial, iclass 12, count 0 2006.173.14:35:25.16#ibcon#enter sib2, iclass 12, count 0 2006.173.14:35:25.16#ibcon#flushed, iclass 12, count 0 2006.173.14:35:25.16#ibcon#about to write, iclass 12, count 0 2006.173.14:35:25.16#ibcon#wrote, iclass 12, count 0 2006.173.14:35:25.16#ibcon#about to read 3, iclass 12, count 0 2006.173.14:35:25.18#ibcon#read 3, iclass 12, count 0 2006.173.14:35:25.18#ibcon#about to read 4, iclass 12, count 0 2006.173.14:35:25.18#ibcon#read 4, iclass 12, count 0 2006.173.14:35:25.18#ibcon#about to read 5, iclass 12, count 0 2006.173.14:35:25.18#ibcon#read 5, iclass 12, count 0 2006.173.14:35:25.18#ibcon#about to read 6, iclass 12, count 0 2006.173.14:35:25.18#ibcon#read 6, iclass 12, count 0 2006.173.14:35:25.18#ibcon#end of sib2, iclass 12, count 0 2006.173.14:35:25.18#ibcon#*mode == 0, iclass 12, count 0 2006.173.14:35:25.18#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.14:35:25.18#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.14:35:25.18#ibcon#*before write, iclass 12, count 0 2006.173.14:35:25.18#ibcon#enter sib2, iclass 12, count 0 2006.173.14:35:25.18#ibcon#flushed, iclass 12, count 0 2006.173.14:35:25.18#ibcon#about to write, iclass 12, count 0 2006.173.14:35:25.18#ibcon#wrote, iclass 12, count 0 2006.173.14:35:25.18#ibcon#about to read 3, iclass 12, count 0 2006.173.14:35:25.22#ibcon#read 3, iclass 12, count 0 2006.173.14:35:25.22#ibcon#about to read 4, iclass 12, count 0 2006.173.14:35:25.22#ibcon#read 4, iclass 12, count 0 2006.173.14:35:25.22#ibcon#about to read 5, iclass 12, count 0 2006.173.14:35:25.22#ibcon#read 5, iclass 12, count 0 2006.173.14:35:25.22#ibcon#about to read 6, iclass 12, count 0 2006.173.14:35:25.22#ibcon#read 6, iclass 12, count 0 2006.173.14:35:25.22#ibcon#end of sib2, iclass 12, count 0 2006.173.14:35:25.22#ibcon#*after write, iclass 12, count 0 2006.173.14:35:25.22#ibcon#*before return 0, iclass 12, count 0 2006.173.14:35:25.22#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.14:35:25.22#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.14:35:25.22#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.14:35:25.22#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.14:35:25.22$vck44/vb=8,4 2006.173.14:35:25.22#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.14:35:25.22#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.14:35:25.22#ibcon#ireg 11 cls_cnt 2 2006.173.14:35:25.22#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.14:35:25.28#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.14:35:25.28#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.14:35:25.28#ibcon#enter wrdev, iclass 14, count 2 2006.173.14:35:25.28#ibcon#first serial, iclass 14, count 2 2006.173.14:35:25.28#ibcon#enter sib2, iclass 14, count 2 2006.173.14:35:25.28#ibcon#flushed, iclass 14, count 2 2006.173.14:35:25.28#ibcon#about to write, iclass 14, count 2 2006.173.14:35:25.28#ibcon#wrote, iclass 14, count 2 2006.173.14:35:25.28#ibcon#about to read 3, iclass 14, count 2 2006.173.14:35:25.30#ibcon#read 3, iclass 14, count 2 2006.173.14:35:25.30#ibcon#about to read 4, iclass 14, count 2 2006.173.14:35:25.30#ibcon#read 4, iclass 14, count 2 2006.173.14:35:25.30#ibcon#about to read 5, iclass 14, count 2 2006.173.14:35:25.30#ibcon#read 5, iclass 14, count 2 2006.173.14:35:25.30#ibcon#about to read 6, iclass 14, count 2 2006.173.14:35:25.30#ibcon#read 6, iclass 14, count 2 2006.173.14:35:25.30#ibcon#end of sib2, iclass 14, count 2 2006.173.14:35:25.30#ibcon#*mode == 0, iclass 14, count 2 2006.173.14:35:25.30#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.14:35:25.30#ibcon#[27=AT08-04\r\n] 2006.173.14:35:25.30#ibcon#*before write, iclass 14, count 2 2006.173.14:35:25.30#ibcon#enter sib2, iclass 14, count 2 2006.173.14:35:25.30#ibcon#flushed, iclass 14, count 2 2006.173.14:35:25.30#ibcon#about to write, iclass 14, count 2 2006.173.14:35:25.30#ibcon#wrote, iclass 14, count 2 2006.173.14:35:25.30#ibcon#about to read 3, iclass 14, count 2 2006.173.14:35:25.33#ibcon#read 3, iclass 14, count 2 2006.173.14:35:25.33#ibcon#about to read 4, iclass 14, count 2 2006.173.14:35:25.33#ibcon#read 4, iclass 14, count 2 2006.173.14:35:25.33#ibcon#about to read 5, iclass 14, count 2 2006.173.14:35:25.33#ibcon#read 5, iclass 14, count 2 2006.173.14:35:25.33#ibcon#about to read 6, iclass 14, count 2 2006.173.14:35:25.33#ibcon#read 6, iclass 14, count 2 2006.173.14:35:25.33#ibcon#end of sib2, iclass 14, count 2 2006.173.14:35:25.33#ibcon#*after write, iclass 14, count 2 2006.173.14:35:25.33#ibcon#*before return 0, iclass 14, count 2 2006.173.14:35:25.33#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.14:35:25.33#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.14:35:25.33#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.14:35:25.33#ibcon#ireg 7 cls_cnt 0 2006.173.14:35:25.33#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.14:35:25.45#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.14:35:25.45#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.14:35:25.45#ibcon#enter wrdev, iclass 14, count 0 2006.173.14:35:25.45#ibcon#first serial, iclass 14, count 0 2006.173.14:35:25.45#ibcon#enter sib2, iclass 14, count 0 2006.173.14:35:25.45#ibcon#flushed, iclass 14, count 0 2006.173.14:35:25.45#ibcon#about to write, iclass 14, count 0 2006.173.14:35:25.45#ibcon#wrote, iclass 14, count 0 2006.173.14:35:25.45#ibcon#about to read 3, iclass 14, count 0 2006.173.14:35:25.47#ibcon#read 3, iclass 14, count 0 2006.173.14:35:25.47#ibcon#about to read 4, iclass 14, count 0 2006.173.14:35:25.47#ibcon#read 4, iclass 14, count 0 2006.173.14:35:25.47#ibcon#about to read 5, iclass 14, count 0 2006.173.14:35:25.47#ibcon#read 5, iclass 14, count 0 2006.173.14:35:25.47#ibcon#about to read 6, iclass 14, count 0 2006.173.14:35:25.47#ibcon#read 6, iclass 14, count 0 2006.173.14:35:25.47#ibcon#end of sib2, iclass 14, count 0 2006.173.14:35:25.47#ibcon#*mode == 0, iclass 14, count 0 2006.173.14:35:25.47#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.14:35:25.47#ibcon#[27=USB\r\n] 2006.173.14:35:25.47#ibcon#*before write, iclass 14, count 0 2006.173.14:35:25.47#ibcon#enter sib2, iclass 14, count 0 2006.173.14:35:25.47#ibcon#flushed, iclass 14, count 0 2006.173.14:35:25.47#ibcon#about to write, iclass 14, count 0 2006.173.14:35:25.47#ibcon#wrote, iclass 14, count 0 2006.173.14:35:25.47#ibcon#about to read 3, iclass 14, count 0 2006.173.14:35:25.50#ibcon#read 3, iclass 14, count 0 2006.173.14:35:25.50#ibcon#about to read 4, iclass 14, count 0 2006.173.14:35:25.50#ibcon#read 4, iclass 14, count 0 2006.173.14:35:25.50#ibcon#about to read 5, iclass 14, count 0 2006.173.14:35:25.50#ibcon#read 5, iclass 14, count 0 2006.173.14:35:25.50#ibcon#about to read 6, iclass 14, count 0 2006.173.14:35:25.50#ibcon#read 6, iclass 14, count 0 2006.173.14:35:25.50#ibcon#end of sib2, iclass 14, count 0 2006.173.14:35:25.50#ibcon#*after write, iclass 14, count 0 2006.173.14:35:25.50#ibcon#*before return 0, iclass 14, count 0 2006.173.14:35:25.50#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.14:35:25.50#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.14:35:25.50#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.14:35:25.50#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.14:35:25.50$vck44/vabw=wide 2006.173.14:35:25.50#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.14:35:25.50#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.14:35:25.50#ibcon#ireg 8 cls_cnt 0 2006.173.14:35:25.50#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.14:35:25.50#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.14:35:25.50#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.14:35:25.50#ibcon#enter wrdev, iclass 16, count 0 2006.173.14:35:25.50#ibcon#first serial, iclass 16, count 0 2006.173.14:35:25.50#ibcon#enter sib2, iclass 16, count 0 2006.173.14:35:25.50#ibcon#flushed, iclass 16, count 0 2006.173.14:35:25.50#ibcon#about to write, iclass 16, count 0 2006.173.14:35:25.50#ibcon#wrote, iclass 16, count 0 2006.173.14:35:25.50#ibcon#about to read 3, iclass 16, count 0 2006.173.14:35:25.52#ibcon#read 3, iclass 16, count 0 2006.173.14:35:25.52#ibcon#about to read 4, iclass 16, count 0 2006.173.14:35:25.52#ibcon#read 4, iclass 16, count 0 2006.173.14:35:25.52#ibcon#about to read 5, iclass 16, count 0 2006.173.14:35:25.52#ibcon#read 5, iclass 16, count 0 2006.173.14:35:25.52#ibcon#about to read 6, iclass 16, count 0 2006.173.14:35:25.52#ibcon#read 6, iclass 16, count 0 2006.173.14:35:25.52#ibcon#end of sib2, iclass 16, count 0 2006.173.14:35:25.52#ibcon#*mode == 0, iclass 16, count 0 2006.173.14:35:25.52#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.14:35:25.52#ibcon#[25=BW32\r\n] 2006.173.14:35:25.52#ibcon#*before write, iclass 16, count 0 2006.173.14:35:25.52#ibcon#enter sib2, iclass 16, count 0 2006.173.14:35:25.52#ibcon#flushed, iclass 16, count 0 2006.173.14:35:25.52#ibcon#about to write, iclass 16, count 0 2006.173.14:35:25.52#ibcon#wrote, iclass 16, count 0 2006.173.14:35:25.52#ibcon#about to read 3, iclass 16, count 0 2006.173.14:35:25.55#ibcon#read 3, iclass 16, count 0 2006.173.14:35:25.55#ibcon#about to read 4, iclass 16, count 0 2006.173.14:35:25.55#ibcon#read 4, iclass 16, count 0 2006.173.14:35:25.55#ibcon#about to read 5, iclass 16, count 0 2006.173.14:35:25.55#ibcon#read 5, iclass 16, count 0 2006.173.14:35:25.55#ibcon#about to read 6, iclass 16, count 0 2006.173.14:35:25.55#ibcon#read 6, iclass 16, count 0 2006.173.14:35:25.55#ibcon#end of sib2, iclass 16, count 0 2006.173.14:35:25.55#ibcon#*after write, iclass 16, count 0 2006.173.14:35:25.55#ibcon#*before return 0, iclass 16, count 0 2006.173.14:35:25.55#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.14:35:25.55#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.14:35:25.55#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.14:35:25.55#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.14:35:25.55$vck44/vbbw=wide 2006.173.14:35:25.55#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.14:35:25.55#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.14:35:25.55#ibcon#ireg 8 cls_cnt 0 2006.173.14:35:25.55#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.14:35:25.62#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.14:35:25.62#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.14:35:25.62#ibcon#enter wrdev, iclass 18, count 0 2006.173.14:35:25.62#ibcon#first serial, iclass 18, count 0 2006.173.14:35:25.62#ibcon#enter sib2, iclass 18, count 0 2006.173.14:35:25.62#ibcon#flushed, iclass 18, count 0 2006.173.14:35:25.62#ibcon#about to write, iclass 18, count 0 2006.173.14:35:25.62#ibcon#wrote, iclass 18, count 0 2006.173.14:35:25.62#ibcon#about to read 3, iclass 18, count 0 2006.173.14:35:25.64#ibcon#read 3, iclass 18, count 0 2006.173.14:35:25.64#ibcon#about to read 4, iclass 18, count 0 2006.173.14:35:25.64#ibcon#read 4, iclass 18, count 0 2006.173.14:35:25.64#ibcon#about to read 5, iclass 18, count 0 2006.173.14:35:25.64#ibcon#read 5, iclass 18, count 0 2006.173.14:35:25.64#ibcon#about to read 6, iclass 18, count 0 2006.173.14:35:25.64#ibcon#read 6, iclass 18, count 0 2006.173.14:35:25.64#ibcon#end of sib2, iclass 18, count 0 2006.173.14:35:25.64#ibcon#*mode == 0, iclass 18, count 0 2006.173.14:35:25.64#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.14:35:25.64#ibcon#[27=BW32\r\n] 2006.173.14:35:25.64#ibcon#*before write, iclass 18, count 0 2006.173.14:35:25.64#ibcon#enter sib2, iclass 18, count 0 2006.173.14:35:25.64#ibcon#flushed, iclass 18, count 0 2006.173.14:35:25.64#ibcon#about to write, iclass 18, count 0 2006.173.14:35:25.64#ibcon#wrote, iclass 18, count 0 2006.173.14:35:25.64#ibcon#about to read 3, iclass 18, count 0 2006.173.14:35:25.67#ibcon#read 3, iclass 18, count 0 2006.173.14:35:25.67#ibcon#about to read 4, iclass 18, count 0 2006.173.14:35:25.67#ibcon#read 4, iclass 18, count 0 2006.173.14:35:25.67#ibcon#about to read 5, iclass 18, count 0 2006.173.14:35:25.67#ibcon#read 5, iclass 18, count 0 2006.173.14:35:25.67#ibcon#about to read 6, iclass 18, count 0 2006.173.14:35:25.67#ibcon#read 6, iclass 18, count 0 2006.173.14:35:25.67#ibcon#end of sib2, iclass 18, count 0 2006.173.14:35:25.67#ibcon#*after write, iclass 18, count 0 2006.173.14:35:25.67#ibcon#*before return 0, iclass 18, count 0 2006.173.14:35:25.67#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.14:35:25.67#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.14:35:25.67#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.14:35:25.67#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.14:35:25.67$setupk4/ifdk4 2006.173.14:35:25.67$ifdk4/lo= 2006.173.14:35:25.67$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.14:35:25.67$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.14:35:25.67$ifdk4/patch= 2006.173.14:35:25.67$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.14:35:25.67$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.14:35:25.67$setupk4/!*+20s 2006.173.14:35:28.48#abcon#<5=/14 1.3 2.9 21.341001003.9\r\n> 2006.173.14:35:28.50#abcon#{5=INTERFACE CLEAR} 2006.173.14:35:28.56#abcon#[5=S1D000X0/0*\r\n] 2006.173.14:35:38.65#abcon#<5=/14 1.3 2.9 21.331001003.9\r\n> 2006.173.14:35:38.67#abcon#{5=INTERFACE CLEAR} 2006.173.14:35:38.73#abcon#[5=S1D000X0/0*\r\n] 2006.173.14:35:40.18$setupk4/"tpicd 2006.173.14:35:40.18$setupk4/echo=off 2006.173.14:35:40.18$setupk4/xlog=off 2006.173.14:35:40.18:!2006.173.14:38:10 2006.173.14:35:49.13#trakl#Source acquired 2006.173.14:35:51.13#flagr#flagr/antenna,acquired 2006.173.14:38:10.00:preob 2006.173.14:38:10.14/onsource/TRACKING 2006.173.14:38:10.14:!2006.173.14:38:20 2006.173.14:38:20.00:"tape 2006.173.14:38:20.00:"st=record 2006.173.14:38:20.00:data_valid=on 2006.173.14:38:20.00:midob 2006.173.14:38:21.14/onsource/TRACKING 2006.173.14:38:21.14/wx/21.25,1004.0,100 2006.173.14:38:21.34/cable/+6.5071E-03 2006.173.14:38:22.43/va/01,07,usb,yes,41,44 2006.173.14:38:22.43/va/02,06,usb,yes,41,42 2006.173.14:38:22.43/va/03,05,usb,yes,52,54 2006.173.14:38:22.43/va/04,06,usb,yes,42,44 2006.173.14:38:22.43/va/05,04,usb,yes,33,34 2006.173.14:38:22.43/va/06,03,usb,yes,46,46 2006.173.14:38:22.43/va/07,04,usb,yes,38,39 2006.173.14:38:22.43/va/08,04,usb,yes,32,39 2006.173.14:38:22.66/valo/01,524.99,yes,locked 2006.173.14:38:22.66/valo/02,534.99,yes,locked 2006.173.14:38:22.66/valo/03,564.99,yes,locked 2006.173.14:38:22.66/valo/04,624.99,yes,locked 2006.173.14:38:22.66/valo/05,734.99,yes,locked 2006.173.14:38:22.66/valo/06,814.99,yes,locked 2006.173.14:38:22.66/valo/07,864.99,yes,locked 2006.173.14:38:22.66/valo/08,884.99,yes,locked 2006.173.14:38:23.75/vb/01,04,usb,yes,29,27 2006.173.14:38:23.75/vb/02,04,usb,yes,32,31 2006.173.14:38:23.75/vb/03,04,usb,yes,29,32 2006.173.14:38:23.75/vb/04,04,usb,yes,33,32 2006.173.14:38:23.75/vb/05,04,usb,yes,26,28 2006.173.14:38:23.75/vb/06,04,usb,yes,30,26 2006.173.14:38:23.75/vb/07,04,usb,yes,30,30 2006.173.14:38:23.75/vb/08,04,usb,yes,27,31 2006.173.14:38:23.98/vblo/01,629.99,yes,locked 2006.173.14:38:23.98/vblo/02,634.99,yes,locked 2006.173.14:38:23.98/vblo/03,649.99,yes,locked 2006.173.14:38:23.98/vblo/04,679.99,yes,locked 2006.173.14:38:23.98/vblo/05,709.99,yes,locked 2006.173.14:38:23.98/vblo/06,719.99,yes,locked 2006.173.14:38:23.98/vblo/07,734.99,yes,locked 2006.173.14:38:23.98/vblo/08,744.99,yes,locked 2006.173.14:38:24.13/vabw/8 2006.173.14:38:24.28/vbbw/8 2006.173.14:38:24.37/xfe/off,on,15.2 2006.173.14:38:24.74/ifatt/23,28,28,28 2006.173.14:38:25.08/fmout-gps/S +3.91E-07 2006.173.14:38:25.12:!2006.173.14:40:30 2006.173.14:40:30.00:data_valid=off 2006.173.14:40:30.00:"et 2006.173.14:40:30.00:!+3s 2006.173.14:40:33.02:"tape 2006.173.14:40:33.02:postob 2006.173.14:40:33.13/cable/+6.5060E-03 2006.173.14:40:33.13/wx/21.16,1004.0,100 2006.173.14:40:34.08/fmout-gps/S +3.91E-07 2006.173.14:40:34.08:scan_name=173-1447,jd0606,240 2006.173.14:40:34.08:source=0059+581,010245.76,582411.1,2000.0,cw 2006.173.14:40:35.14#flagr#flagr/antenna,new-source 2006.173.14:40:35.14:checkk5 2006.173.14:40:35.54/chk_autoobs//k5ts1/ autoobs is running! 2006.173.14:40:35.93/chk_autoobs//k5ts2/ autoobs is running! 2006.173.14:40:36.34/chk_autoobs//k5ts3/ autoobs is running! 2006.173.14:40:36.73/chk_autoobs//k5ts4/ autoobs is running! 2006.173.14:40:37.12/chk_obsdata//k5ts1/T1731438??a.dat file size is correct (nominal:520MB, actual:516MB). 2006.173.14:40:37.52/chk_obsdata//k5ts2/T1731438??b.dat file size is correct (nominal:520MB, actual:516MB). 2006.173.14:40:37.92/chk_obsdata//k5ts3/T1731438??c.dat file size is correct (nominal:520MB, actual:516MB). 2006.173.14:40:38.32/chk_obsdata//k5ts4/T1731438??d.dat file size is correct (nominal:520MB, actual:516MB). 2006.173.14:40:39.04/k5log//k5ts1_log_newline 2006.173.14:40:39.75/k5log//k5ts2_log_newline 2006.173.14:40:40.49/k5log//k5ts3_log_newline 2006.173.14:40:41.19/k5log//k5ts4_log_newline 2006.173.14:40:41.21/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.14:40:41.21:setupk4=1 2006.173.14:40:41.21$setupk4/echo=on 2006.173.14:40:41.21$setupk4/pcalon 2006.173.14:40:41.21$pcalon/"no phase cal control is implemented here 2006.173.14:40:41.21$setupk4/"tpicd=stop 2006.173.14:40:41.21$setupk4/"rec=synch_on 2006.173.14:40:41.21$setupk4/"rec_mode=128 2006.173.14:40:41.21$setupk4/!* 2006.173.14:40:41.21$setupk4/recpk4 2006.173.14:40:41.21$recpk4/recpatch= 2006.173.14:40:41.21$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.14:40:41.21$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.14:40:41.22$setupk4/vck44 2006.173.14:40:41.22$vck44/valo=1,524.99 2006.173.14:40:41.22#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.14:40:41.22#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.14:40:41.22#ibcon#ireg 17 cls_cnt 0 2006.173.14:40:41.22#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.14:40:41.22#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.14:40:41.22#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.14:40:41.22#ibcon#enter wrdev, iclass 39, count 0 2006.173.14:40:41.22#ibcon#first serial, iclass 39, count 0 2006.173.14:40:41.22#ibcon#enter sib2, iclass 39, count 0 2006.173.14:40:41.22#ibcon#flushed, iclass 39, count 0 2006.173.14:40:41.22#ibcon#about to write, iclass 39, count 0 2006.173.14:40:41.22#ibcon#wrote, iclass 39, count 0 2006.173.14:40:41.22#ibcon#about to read 3, iclass 39, count 0 2006.173.14:40:41.23#ibcon#read 3, iclass 39, count 0 2006.173.14:40:41.23#ibcon#about to read 4, iclass 39, count 0 2006.173.14:40:41.23#ibcon#read 4, iclass 39, count 0 2006.173.14:40:41.23#ibcon#about to read 5, iclass 39, count 0 2006.173.14:40:41.23#ibcon#read 5, iclass 39, count 0 2006.173.14:40:41.23#ibcon#about to read 6, iclass 39, count 0 2006.173.14:40:41.23#ibcon#read 6, iclass 39, count 0 2006.173.14:40:41.23#ibcon#end of sib2, iclass 39, count 0 2006.173.14:40:41.23#ibcon#*mode == 0, iclass 39, count 0 2006.173.14:40:41.23#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.14:40:41.23#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.14:40:41.23#ibcon#*before write, iclass 39, count 0 2006.173.14:40:41.23#ibcon#enter sib2, iclass 39, count 0 2006.173.14:40:41.23#ibcon#flushed, iclass 39, count 0 2006.173.14:40:41.23#ibcon#about to write, iclass 39, count 0 2006.173.14:40:41.23#ibcon#wrote, iclass 39, count 0 2006.173.14:40:41.23#ibcon#about to read 3, iclass 39, count 0 2006.173.14:40:41.28#ibcon#read 3, iclass 39, count 0 2006.173.14:40:41.28#ibcon#about to read 4, iclass 39, count 0 2006.173.14:40:41.28#ibcon#read 4, iclass 39, count 0 2006.173.14:40:41.28#ibcon#about to read 5, iclass 39, count 0 2006.173.14:40:41.28#ibcon#read 5, iclass 39, count 0 2006.173.14:40:41.28#ibcon#about to read 6, iclass 39, count 0 2006.173.14:40:41.28#ibcon#read 6, iclass 39, count 0 2006.173.14:40:41.28#ibcon#end of sib2, iclass 39, count 0 2006.173.14:40:41.28#ibcon#*after write, iclass 39, count 0 2006.173.14:40:41.28#ibcon#*before return 0, iclass 39, count 0 2006.173.14:40:41.28#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.14:40:41.28#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.14:40:41.28#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.14:40:41.28#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.14:40:41.28$vck44/va=1,7 2006.173.14:40:41.28#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.14:40:41.28#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.14:40:41.28#ibcon#ireg 11 cls_cnt 2 2006.173.14:40:41.28#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.14:40:41.28#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.14:40:41.28#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.14:40:41.28#ibcon#enter wrdev, iclass 3, count 2 2006.173.14:40:41.28#ibcon#first serial, iclass 3, count 2 2006.173.14:40:41.28#ibcon#enter sib2, iclass 3, count 2 2006.173.14:40:41.28#ibcon#flushed, iclass 3, count 2 2006.173.14:40:41.28#ibcon#about to write, iclass 3, count 2 2006.173.14:40:41.28#ibcon#wrote, iclass 3, count 2 2006.173.14:40:41.28#ibcon#about to read 3, iclass 3, count 2 2006.173.14:40:41.30#ibcon#read 3, iclass 3, count 2 2006.173.14:40:41.30#ibcon#about to read 4, iclass 3, count 2 2006.173.14:40:41.30#ibcon#read 4, iclass 3, count 2 2006.173.14:40:41.30#ibcon#about to read 5, iclass 3, count 2 2006.173.14:40:41.30#ibcon#read 5, iclass 3, count 2 2006.173.14:40:41.30#ibcon#about to read 6, iclass 3, count 2 2006.173.14:40:41.30#ibcon#read 6, iclass 3, count 2 2006.173.14:40:41.30#ibcon#end of sib2, iclass 3, count 2 2006.173.14:40:41.30#ibcon#*mode == 0, iclass 3, count 2 2006.173.14:40:41.30#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.14:40:41.30#ibcon#[25=AT01-07\r\n] 2006.173.14:40:41.30#ibcon#*before write, iclass 3, count 2 2006.173.14:40:41.30#ibcon#enter sib2, iclass 3, count 2 2006.173.14:40:41.30#ibcon#flushed, iclass 3, count 2 2006.173.14:40:41.30#ibcon#about to write, iclass 3, count 2 2006.173.14:40:41.30#ibcon#wrote, iclass 3, count 2 2006.173.14:40:41.30#ibcon#about to read 3, iclass 3, count 2 2006.173.14:40:41.33#ibcon#read 3, iclass 3, count 2 2006.173.14:40:41.33#ibcon#about to read 4, iclass 3, count 2 2006.173.14:40:41.33#ibcon#read 4, iclass 3, count 2 2006.173.14:40:41.33#ibcon#about to read 5, iclass 3, count 2 2006.173.14:40:41.33#ibcon#read 5, iclass 3, count 2 2006.173.14:40:41.33#ibcon#about to read 6, iclass 3, count 2 2006.173.14:40:41.33#ibcon#read 6, iclass 3, count 2 2006.173.14:40:41.33#ibcon#end of sib2, iclass 3, count 2 2006.173.14:40:41.33#ibcon#*after write, iclass 3, count 2 2006.173.14:40:41.33#ibcon#*before return 0, iclass 3, count 2 2006.173.14:40:41.33#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.14:40:41.33#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.14:40:41.33#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.14:40:41.33#ibcon#ireg 7 cls_cnt 0 2006.173.14:40:41.33#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.14:40:41.45#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.14:40:41.45#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.14:40:41.45#ibcon#enter wrdev, iclass 3, count 0 2006.173.14:40:41.45#ibcon#first serial, iclass 3, count 0 2006.173.14:40:41.45#ibcon#enter sib2, iclass 3, count 0 2006.173.14:40:41.45#ibcon#flushed, iclass 3, count 0 2006.173.14:40:41.45#ibcon#about to write, iclass 3, count 0 2006.173.14:40:41.45#ibcon#wrote, iclass 3, count 0 2006.173.14:40:41.45#ibcon#about to read 3, iclass 3, count 0 2006.173.14:40:41.47#ibcon#read 3, iclass 3, count 0 2006.173.14:40:41.47#ibcon#about to read 4, iclass 3, count 0 2006.173.14:40:41.47#ibcon#read 4, iclass 3, count 0 2006.173.14:40:41.47#ibcon#about to read 5, iclass 3, count 0 2006.173.14:40:41.47#ibcon#read 5, iclass 3, count 0 2006.173.14:40:41.47#ibcon#about to read 6, iclass 3, count 0 2006.173.14:40:41.47#ibcon#read 6, iclass 3, count 0 2006.173.14:40:41.47#ibcon#end of sib2, iclass 3, count 0 2006.173.14:40:41.47#ibcon#*mode == 0, iclass 3, count 0 2006.173.14:40:41.47#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.14:40:41.47#ibcon#[25=USB\r\n] 2006.173.14:40:41.47#ibcon#*before write, iclass 3, count 0 2006.173.14:40:41.47#ibcon#enter sib2, iclass 3, count 0 2006.173.14:40:41.47#ibcon#flushed, iclass 3, count 0 2006.173.14:40:41.47#ibcon#about to write, iclass 3, count 0 2006.173.14:40:41.47#ibcon#wrote, iclass 3, count 0 2006.173.14:40:41.47#ibcon#about to read 3, iclass 3, count 0 2006.173.14:40:41.50#ibcon#read 3, iclass 3, count 0 2006.173.14:40:41.50#ibcon#about to read 4, iclass 3, count 0 2006.173.14:40:41.50#ibcon#read 4, iclass 3, count 0 2006.173.14:40:41.50#ibcon#about to read 5, iclass 3, count 0 2006.173.14:40:41.50#ibcon#read 5, iclass 3, count 0 2006.173.14:40:41.50#ibcon#about to read 6, iclass 3, count 0 2006.173.14:40:41.50#ibcon#read 6, iclass 3, count 0 2006.173.14:40:41.50#ibcon#end of sib2, iclass 3, count 0 2006.173.14:40:41.50#ibcon#*after write, iclass 3, count 0 2006.173.14:40:41.50#ibcon#*before return 0, iclass 3, count 0 2006.173.14:40:41.50#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.14:40:41.50#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.14:40:41.50#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.14:40:41.50#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.14:40:41.50$vck44/valo=2,534.99 2006.173.14:40:41.50#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.14:40:41.50#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.14:40:41.50#ibcon#ireg 17 cls_cnt 0 2006.173.14:40:41.50#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.14:40:41.50#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.14:40:41.50#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.14:40:41.50#ibcon#enter wrdev, iclass 5, count 0 2006.173.14:40:41.50#ibcon#first serial, iclass 5, count 0 2006.173.14:40:41.50#ibcon#enter sib2, iclass 5, count 0 2006.173.14:40:41.50#ibcon#flushed, iclass 5, count 0 2006.173.14:40:41.50#ibcon#about to write, iclass 5, count 0 2006.173.14:40:41.50#ibcon#wrote, iclass 5, count 0 2006.173.14:40:41.50#ibcon#about to read 3, iclass 5, count 0 2006.173.14:40:41.52#ibcon#read 3, iclass 5, count 0 2006.173.14:40:41.52#ibcon#about to read 4, iclass 5, count 0 2006.173.14:40:41.52#ibcon#read 4, iclass 5, count 0 2006.173.14:40:41.52#ibcon#about to read 5, iclass 5, count 0 2006.173.14:40:41.52#ibcon#read 5, iclass 5, count 0 2006.173.14:40:41.52#ibcon#about to read 6, iclass 5, count 0 2006.173.14:40:41.52#ibcon#read 6, iclass 5, count 0 2006.173.14:40:41.52#ibcon#end of sib2, iclass 5, count 0 2006.173.14:40:41.52#ibcon#*mode == 0, iclass 5, count 0 2006.173.14:40:41.52#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.14:40:41.52#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.14:40:41.52#ibcon#*before write, iclass 5, count 0 2006.173.14:40:41.52#ibcon#enter sib2, iclass 5, count 0 2006.173.14:40:41.52#ibcon#flushed, iclass 5, count 0 2006.173.14:40:41.52#ibcon#about to write, iclass 5, count 0 2006.173.14:40:41.52#ibcon#wrote, iclass 5, count 0 2006.173.14:40:41.52#ibcon#about to read 3, iclass 5, count 0 2006.173.14:40:41.56#ibcon#read 3, iclass 5, count 0 2006.173.14:40:41.56#ibcon#about to read 4, iclass 5, count 0 2006.173.14:40:41.56#ibcon#read 4, iclass 5, count 0 2006.173.14:40:41.56#ibcon#about to read 5, iclass 5, count 0 2006.173.14:40:41.56#ibcon#read 5, iclass 5, count 0 2006.173.14:40:41.56#ibcon#about to read 6, iclass 5, count 0 2006.173.14:40:41.56#ibcon#read 6, iclass 5, count 0 2006.173.14:40:41.56#ibcon#end of sib2, iclass 5, count 0 2006.173.14:40:41.56#ibcon#*after write, iclass 5, count 0 2006.173.14:40:41.56#ibcon#*before return 0, iclass 5, count 0 2006.173.14:40:41.56#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.14:40:41.56#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.14:40:41.56#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.14:40:41.56#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.14:40:41.56$vck44/va=2,6 2006.173.14:40:41.56#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.173.14:40:41.56#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.173.14:40:41.56#ibcon#ireg 11 cls_cnt 2 2006.173.14:40:41.56#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.14:40:41.62#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.14:40:41.62#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.14:40:41.62#ibcon#enter wrdev, iclass 7, count 2 2006.173.14:40:41.62#ibcon#first serial, iclass 7, count 2 2006.173.14:40:41.62#ibcon#enter sib2, iclass 7, count 2 2006.173.14:40:41.62#ibcon#flushed, iclass 7, count 2 2006.173.14:40:41.62#ibcon#about to write, iclass 7, count 2 2006.173.14:40:41.62#ibcon#wrote, iclass 7, count 2 2006.173.14:40:41.62#ibcon#about to read 3, iclass 7, count 2 2006.173.14:40:41.64#ibcon#read 3, iclass 7, count 2 2006.173.14:40:41.64#ibcon#about to read 4, iclass 7, count 2 2006.173.14:40:41.64#ibcon#read 4, iclass 7, count 2 2006.173.14:40:41.64#ibcon#about to read 5, iclass 7, count 2 2006.173.14:40:41.64#ibcon#read 5, iclass 7, count 2 2006.173.14:40:41.64#ibcon#about to read 6, iclass 7, count 2 2006.173.14:40:41.64#ibcon#read 6, iclass 7, count 2 2006.173.14:40:41.64#ibcon#end of sib2, iclass 7, count 2 2006.173.14:40:41.64#ibcon#*mode == 0, iclass 7, count 2 2006.173.14:40:41.64#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.173.14:40:41.64#ibcon#[25=AT02-06\r\n] 2006.173.14:40:41.64#ibcon#*before write, iclass 7, count 2 2006.173.14:40:41.64#ibcon#enter sib2, iclass 7, count 2 2006.173.14:40:41.64#ibcon#flushed, iclass 7, count 2 2006.173.14:40:41.64#ibcon#about to write, iclass 7, count 2 2006.173.14:40:41.64#ibcon#wrote, iclass 7, count 2 2006.173.14:40:41.64#ibcon#about to read 3, iclass 7, count 2 2006.173.14:40:41.67#ibcon#read 3, iclass 7, count 2 2006.173.14:40:41.67#ibcon#about to read 4, iclass 7, count 2 2006.173.14:40:41.67#ibcon#read 4, iclass 7, count 2 2006.173.14:40:41.67#ibcon#about to read 5, iclass 7, count 2 2006.173.14:40:41.67#ibcon#read 5, iclass 7, count 2 2006.173.14:40:41.67#ibcon#about to read 6, iclass 7, count 2 2006.173.14:40:41.67#ibcon#read 6, iclass 7, count 2 2006.173.14:40:41.67#ibcon#end of sib2, iclass 7, count 2 2006.173.14:40:41.67#ibcon#*after write, iclass 7, count 2 2006.173.14:40:41.67#ibcon#*before return 0, iclass 7, count 2 2006.173.14:40:41.67#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.14:40:41.67#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.173.14:40:41.67#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.173.14:40:41.67#ibcon#ireg 7 cls_cnt 0 2006.173.14:40:41.67#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.14:40:41.79#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.14:40:41.79#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.14:40:41.79#ibcon#enter wrdev, iclass 7, count 0 2006.173.14:40:41.79#ibcon#first serial, iclass 7, count 0 2006.173.14:40:41.79#ibcon#enter sib2, iclass 7, count 0 2006.173.14:40:41.79#ibcon#flushed, iclass 7, count 0 2006.173.14:40:41.79#ibcon#about to write, iclass 7, count 0 2006.173.14:40:41.79#ibcon#wrote, iclass 7, count 0 2006.173.14:40:41.79#ibcon#about to read 3, iclass 7, count 0 2006.173.14:40:41.81#ibcon#read 3, iclass 7, count 0 2006.173.14:40:41.81#ibcon#about to read 4, iclass 7, count 0 2006.173.14:40:41.81#ibcon#read 4, iclass 7, count 0 2006.173.14:40:41.81#ibcon#about to read 5, iclass 7, count 0 2006.173.14:40:41.81#ibcon#read 5, iclass 7, count 0 2006.173.14:40:41.81#ibcon#about to read 6, iclass 7, count 0 2006.173.14:40:41.81#ibcon#read 6, iclass 7, count 0 2006.173.14:40:41.81#ibcon#end of sib2, iclass 7, count 0 2006.173.14:40:41.81#ibcon#*mode == 0, iclass 7, count 0 2006.173.14:40:41.81#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.14:40:41.81#ibcon#[25=USB\r\n] 2006.173.14:40:41.81#ibcon#*before write, iclass 7, count 0 2006.173.14:40:41.81#ibcon#enter sib2, iclass 7, count 0 2006.173.14:40:41.81#ibcon#flushed, iclass 7, count 0 2006.173.14:40:41.81#ibcon#about to write, iclass 7, count 0 2006.173.14:40:41.81#ibcon#wrote, iclass 7, count 0 2006.173.14:40:41.81#ibcon#about to read 3, iclass 7, count 0 2006.173.14:40:41.84#ibcon#read 3, iclass 7, count 0 2006.173.14:40:41.84#ibcon#about to read 4, iclass 7, count 0 2006.173.14:40:41.84#ibcon#read 4, iclass 7, count 0 2006.173.14:40:41.84#ibcon#about to read 5, iclass 7, count 0 2006.173.14:40:41.84#ibcon#read 5, iclass 7, count 0 2006.173.14:40:41.84#ibcon#about to read 6, iclass 7, count 0 2006.173.14:40:41.84#ibcon#read 6, iclass 7, count 0 2006.173.14:40:41.84#ibcon#end of sib2, iclass 7, count 0 2006.173.14:40:41.84#ibcon#*after write, iclass 7, count 0 2006.173.14:40:41.84#ibcon#*before return 0, iclass 7, count 0 2006.173.14:40:41.84#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.14:40:41.84#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.173.14:40:41.84#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.14:40:41.84#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.14:40:41.84$vck44/valo=3,564.99 2006.173.14:40:41.84#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.14:40:41.84#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.14:40:41.84#ibcon#ireg 17 cls_cnt 0 2006.173.14:40:41.84#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.14:40:41.84#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.14:40:41.84#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.14:40:41.84#ibcon#enter wrdev, iclass 11, count 0 2006.173.14:40:41.84#ibcon#first serial, iclass 11, count 0 2006.173.14:40:41.84#ibcon#enter sib2, iclass 11, count 0 2006.173.14:40:41.84#ibcon#flushed, iclass 11, count 0 2006.173.14:40:41.84#ibcon#about to write, iclass 11, count 0 2006.173.14:40:41.84#ibcon#wrote, iclass 11, count 0 2006.173.14:40:41.84#ibcon#about to read 3, iclass 11, count 0 2006.173.14:40:41.86#ibcon#read 3, iclass 11, count 0 2006.173.14:40:41.86#ibcon#about to read 4, iclass 11, count 0 2006.173.14:40:41.86#ibcon#read 4, iclass 11, count 0 2006.173.14:40:41.86#ibcon#about to read 5, iclass 11, count 0 2006.173.14:40:41.86#ibcon#read 5, iclass 11, count 0 2006.173.14:40:41.86#ibcon#about to read 6, iclass 11, count 0 2006.173.14:40:41.86#ibcon#read 6, iclass 11, count 0 2006.173.14:40:41.86#ibcon#end of sib2, iclass 11, count 0 2006.173.14:40:41.86#ibcon#*mode == 0, iclass 11, count 0 2006.173.14:40:41.86#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.14:40:41.86#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.14:40:41.86#ibcon#*before write, iclass 11, count 0 2006.173.14:40:41.86#ibcon#enter sib2, iclass 11, count 0 2006.173.14:40:41.86#ibcon#flushed, iclass 11, count 0 2006.173.14:40:41.86#ibcon#about to write, iclass 11, count 0 2006.173.14:40:41.86#ibcon#wrote, iclass 11, count 0 2006.173.14:40:41.86#ibcon#about to read 3, iclass 11, count 0 2006.173.14:40:41.90#ibcon#read 3, iclass 11, count 0 2006.173.14:40:41.90#ibcon#about to read 4, iclass 11, count 0 2006.173.14:40:41.90#ibcon#read 4, iclass 11, count 0 2006.173.14:40:41.90#ibcon#about to read 5, iclass 11, count 0 2006.173.14:40:41.90#ibcon#read 5, iclass 11, count 0 2006.173.14:40:41.90#ibcon#about to read 6, iclass 11, count 0 2006.173.14:40:41.90#ibcon#read 6, iclass 11, count 0 2006.173.14:40:41.90#ibcon#end of sib2, iclass 11, count 0 2006.173.14:40:41.90#ibcon#*after write, iclass 11, count 0 2006.173.14:40:41.90#ibcon#*before return 0, iclass 11, count 0 2006.173.14:40:41.90#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.14:40:41.90#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.14:40:41.90#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.14:40:41.90#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.14:40:41.90$vck44/va=3,5 2006.173.14:40:41.90#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.173.14:40:41.90#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.173.14:40:41.90#ibcon#ireg 11 cls_cnt 2 2006.173.14:40:41.90#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.14:40:41.96#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.14:40:41.96#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.14:40:41.96#ibcon#enter wrdev, iclass 13, count 2 2006.173.14:40:41.96#ibcon#first serial, iclass 13, count 2 2006.173.14:40:41.96#ibcon#enter sib2, iclass 13, count 2 2006.173.14:40:41.96#ibcon#flushed, iclass 13, count 2 2006.173.14:40:41.96#ibcon#about to write, iclass 13, count 2 2006.173.14:40:41.96#ibcon#wrote, iclass 13, count 2 2006.173.14:40:41.96#ibcon#about to read 3, iclass 13, count 2 2006.173.14:40:41.98#ibcon#read 3, iclass 13, count 2 2006.173.14:40:41.98#ibcon#about to read 4, iclass 13, count 2 2006.173.14:40:41.98#ibcon#read 4, iclass 13, count 2 2006.173.14:40:41.98#ibcon#about to read 5, iclass 13, count 2 2006.173.14:40:41.98#ibcon#read 5, iclass 13, count 2 2006.173.14:40:41.98#ibcon#about to read 6, iclass 13, count 2 2006.173.14:40:41.98#ibcon#read 6, iclass 13, count 2 2006.173.14:40:41.98#ibcon#end of sib2, iclass 13, count 2 2006.173.14:40:41.98#ibcon#*mode == 0, iclass 13, count 2 2006.173.14:40:41.98#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.173.14:40:41.98#ibcon#[25=AT03-05\r\n] 2006.173.14:40:41.98#ibcon#*before write, iclass 13, count 2 2006.173.14:40:41.98#ibcon#enter sib2, iclass 13, count 2 2006.173.14:40:41.98#ibcon#flushed, iclass 13, count 2 2006.173.14:40:41.98#ibcon#about to write, iclass 13, count 2 2006.173.14:40:41.98#ibcon#wrote, iclass 13, count 2 2006.173.14:40:41.98#ibcon#about to read 3, iclass 13, count 2 2006.173.14:40:42.01#ibcon#read 3, iclass 13, count 2 2006.173.14:40:42.01#ibcon#about to read 4, iclass 13, count 2 2006.173.14:40:42.01#ibcon#read 4, iclass 13, count 2 2006.173.14:40:42.01#ibcon#about to read 5, iclass 13, count 2 2006.173.14:40:42.01#ibcon#read 5, iclass 13, count 2 2006.173.14:40:42.01#ibcon#about to read 6, iclass 13, count 2 2006.173.14:40:42.01#ibcon#read 6, iclass 13, count 2 2006.173.14:40:42.01#ibcon#end of sib2, iclass 13, count 2 2006.173.14:40:42.01#ibcon#*after write, iclass 13, count 2 2006.173.14:40:42.01#ibcon#*before return 0, iclass 13, count 2 2006.173.14:40:42.01#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.14:40:42.01#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.173.14:40:42.01#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.173.14:40:42.01#ibcon#ireg 7 cls_cnt 0 2006.173.14:40:42.01#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.14:40:42.13#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.14:40:42.13#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.14:40:42.13#ibcon#enter wrdev, iclass 13, count 0 2006.173.14:40:42.13#ibcon#first serial, iclass 13, count 0 2006.173.14:40:42.13#ibcon#enter sib2, iclass 13, count 0 2006.173.14:40:42.13#ibcon#flushed, iclass 13, count 0 2006.173.14:40:42.13#ibcon#about to write, iclass 13, count 0 2006.173.14:40:42.13#ibcon#wrote, iclass 13, count 0 2006.173.14:40:42.13#ibcon#about to read 3, iclass 13, count 0 2006.173.14:40:42.15#ibcon#read 3, iclass 13, count 0 2006.173.14:40:42.15#ibcon#about to read 4, iclass 13, count 0 2006.173.14:40:42.15#ibcon#read 4, iclass 13, count 0 2006.173.14:40:42.15#ibcon#about to read 5, iclass 13, count 0 2006.173.14:40:42.15#ibcon#read 5, iclass 13, count 0 2006.173.14:40:42.15#ibcon#about to read 6, iclass 13, count 0 2006.173.14:40:42.15#ibcon#read 6, iclass 13, count 0 2006.173.14:40:42.15#ibcon#end of sib2, iclass 13, count 0 2006.173.14:40:42.15#ibcon#*mode == 0, iclass 13, count 0 2006.173.14:40:42.15#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.14:40:42.15#ibcon#[25=USB\r\n] 2006.173.14:40:42.15#ibcon#*before write, iclass 13, count 0 2006.173.14:40:42.15#ibcon#enter sib2, iclass 13, count 0 2006.173.14:40:42.15#ibcon#flushed, iclass 13, count 0 2006.173.14:40:42.15#ibcon#about to write, iclass 13, count 0 2006.173.14:40:42.15#ibcon#wrote, iclass 13, count 0 2006.173.14:40:42.15#ibcon#about to read 3, iclass 13, count 0 2006.173.14:40:42.18#ibcon#read 3, iclass 13, count 0 2006.173.14:40:42.18#ibcon#about to read 4, iclass 13, count 0 2006.173.14:40:42.18#ibcon#read 4, iclass 13, count 0 2006.173.14:40:42.18#ibcon#about to read 5, iclass 13, count 0 2006.173.14:40:42.18#ibcon#read 5, iclass 13, count 0 2006.173.14:40:42.18#ibcon#about to read 6, iclass 13, count 0 2006.173.14:40:42.18#ibcon#read 6, iclass 13, count 0 2006.173.14:40:42.18#ibcon#end of sib2, iclass 13, count 0 2006.173.14:40:42.18#ibcon#*after write, iclass 13, count 0 2006.173.14:40:42.18#ibcon#*before return 0, iclass 13, count 0 2006.173.14:40:42.18#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.14:40:42.18#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.173.14:40:42.18#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.14:40:42.18#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.14:40:42.18$vck44/valo=4,624.99 2006.173.14:40:42.18#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.14:40:42.18#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.14:40:42.18#ibcon#ireg 17 cls_cnt 0 2006.173.14:40:42.18#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.14:40:42.18#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.14:40:42.18#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.14:40:42.18#ibcon#enter wrdev, iclass 15, count 0 2006.173.14:40:42.18#ibcon#first serial, iclass 15, count 0 2006.173.14:40:42.18#ibcon#enter sib2, iclass 15, count 0 2006.173.14:40:42.18#ibcon#flushed, iclass 15, count 0 2006.173.14:40:42.18#ibcon#about to write, iclass 15, count 0 2006.173.14:40:42.18#ibcon#wrote, iclass 15, count 0 2006.173.14:40:42.18#ibcon#about to read 3, iclass 15, count 0 2006.173.14:40:42.20#ibcon#read 3, iclass 15, count 0 2006.173.14:40:42.20#ibcon#about to read 4, iclass 15, count 0 2006.173.14:40:42.20#ibcon#read 4, iclass 15, count 0 2006.173.14:40:42.20#ibcon#about to read 5, iclass 15, count 0 2006.173.14:40:42.20#ibcon#read 5, iclass 15, count 0 2006.173.14:40:42.20#ibcon#about to read 6, iclass 15, count 0 2006.173.14:40:42.20#ibcon#read 6, iclass 15, count 0 2006.173.14:40:42.20#ibcon#end of sib2, iclass 15, count 0 2006.173.14:40:42.20#ibcon#*mode == 0, iclass 15, count 0 2006.173.14:40:42.20#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.14:40:42.20#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.14:40:42.20#ibcon#*before write, iclass 15, count 0 2006.173.14:40:42.20#ibcon#enter sib2, iclass 15, count 0 2006.173.14:40:42.20#ibcon#flushed, iclass 15, count 0 2006.173.14:40:42.20#ibcon#about to write, iclass 15, count 0 2006.173.14:40:42.20#ibcon#wrote, iclass 15, count 0 2006.173.14:40:42.20#ibcon#about to read 3, iclass 15, count 0 2006.173.14:40:42.24#ibcon#read 3, iclass 15, count 0 2006.173.14:40:42.24#ibcon#about to read 4, iclass 15, count 0 2006.173.14:40:42.24#ibcon#read 4, iclass 15, count 0 2006.173.14:40:42.24#ibcon#about to read 5, iclass 15, count 0 2006.173.14:40:42.24#ibcon#read 5, iclass 15, count 0 2006.173.14:40:42.24#ibcon#about to read 6, iclass 15, count 0 2006.173.14:40:42.24#ibcon#read 6, iclass 15, count 0 2006.173.14:40:42.24#ibcon#end of sib2, iclass 15, count 0 2006.173.14:40:42.24#ibcon#*after write, iclass 15, count 0 2006.173.14:40:42.24#ibcon#*before return 0, iclass 15, count 0 2006.173.14:40:42.24#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.14:40:42.24#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.14:40:42.24#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.14:40:42.24#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.14:40:42.24$vck44/va=4,6 2006.173.14:40:42.24#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.14:40:42.24#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.14:40:42.24#ibcon#ireg 11 cls_cnt 2 2006.173.14:40:42.24#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.14:40:42.30#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.14:40:42.30#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.14:40:42.30#ibcon#enter wrdev, iclass 17, count 2 2006.173.14:40:42.30#ibcon#first serial, iclass 17, count 2 2006.173.14:40:42.30#ibcon#enter sib2, iclass 17, count 2 2006.173.14:40:42.30#ibcon#flushed, iclass 17, count 2 2006.173.14:40:42.30#ibcon#about to write, iclass 17, count 2 2006.173.14:40:42.30#ibcon#wrote, iclass 17, count 2 2006.173.14:40:42.30#ibcon#about to read 3, iclass 17, count 2 2006.173.14:40:42.32#ibcon#read 3, iclass 17, count 2 2006.173.14:40:42.32#ibcon#about to read 4, iclass 17, count 2 2006.173.14:40:42.32#ibcon#read 4, iclass 17, count 2 2006.173.14:40:42.32#ibcon#about to read 5, iclass 17, count 2 2006.173.14:40:42.32#ibcon#read 5, iclass 17, count 2 2006.173.14:40:42.32#ibcon#about to read 6, iclass 17, count 2 2006.173.14:40:42.32#ibcon#read 6, iclass 17, count 2 2006.173.14:40:42.32#ibcon#end of sib2, iclass 17, count 2 2006.173.14:40:42.32#ibcon#*mode == 0, iclass 17, count 2 2006.173.14:40:42.32#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.14:40:42.32#ibcon#[25=AT04-06\r\n] 2006.173.14:40:42.32#ibcon#*before write, iclass 17, count 2 2006.173.14:40:42.32#ibcon#enter sib2, iclass 17, count 2 2006.173.14:40:42.32#ibcon#flushed, iclass 17, count 2 2006.173.14:40:42.32#ibcon#about to write, iclass 17, count 2 2006.173.14:40:42.32#ibcon#wrote, iclass 17, count 2 2006.173.14:40:42.32#ibcon#about to read 3, iclass 17, count 2 2006.173.14:40:42.35#ibcon#read 3, iclass 17, count 2 2006.173.14:40:42.35#ibcon#about to read 4, iclass 17, count 2 2006.173.14:40:42.35#ibcon#read 4, iclass 17, count 2 2006.173.14:40:42.35#ibcon#about to read 5, iclass 17, count 2 2006.173.14:40:42.35#ibcon#read 5, iclass 17, count 2 2006.173.14:40:42.35#ibcon#about to read 6, iclass 17, count 2 2006.173.14:40:42.35#ibcon#read 6, iclass 17, count 2 2006.173.14:40:42.35#ibcon#end of sib2, iclass 17, count 2 2006.173.14:40:42.35#ibcon#*after write, iclass 17, count 2 2006.173.14:40:42.35#ibcon#*before return 0, iclass 17, count 2 2006.173.14:40:42.35#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.14:40:42.35#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.14:40:42.35#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.14:40:42.35#ibcon#ireg 7 cls_cnt 0 2006.173.14:40:42.35#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.14:40:42.47#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.14:40:42.47#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.14:40:42.47#ibcon#enter wrdev, iclass 17, count 0 2006.173.14:40:42.47#ibcon#first serial, iclass 17, count 0 2006.173.14:40:42.47#ibcon#enter sib2, iclass 17, count 0 2006.173.14:40:42.47#ibcon#flushed, iclass 17, count 0 2006.173.14:40:42.47#ibcon#about to write, iclass 17, count 0 2006.173.14:40:42.47#ibcon#wrote, iclass 17, count 0 2006.173.14:40:42.47#ibcon#about to read 3, iclass 17, count 0 2006.173.14:40:42.49#ibcon#read 3, iclass 17, count 0 2006.173.14:40:42.49#ibcon#about to read 4, iclass 17, count 0 2006.173.14:40:42.49#ibcon#read 4, iclass 17, count 0 2006.173.14:40:42.49#ibcon#about to read 5, iclass 17, count 0 2006.173.14:40:42.49#ibcon#read 5, iclass 17, count 0 2006.173.14:40:42.49#ibcon#about to read 6, iclass 17, count 0 2006.173.14:40:42.49#ibcon#read 6, iclass 17, count 0 2006.173.14:40:42.49#ibcon#end of sib2, iclass 17, count 0 2006.173.14:40:42.49#ibcon#*mode == 0, iclass 17, count 0 2006.173.14:40:42.49#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.14:40:42.49#ibcon#[25=USB\r\n] 2006.173.14:40:42.49#ibcon#*before write, iclass 17, count 0 2006.173.14:40:42.49#ibcon#enter sib2, iclass 17, count 0 2006.173.14:40:42.49#ibcon#flushed, iclass 17, count 0 2006.173.14:40:42.49#ibcon#about to write, iclass 17, count 0 2006.173.14:40:42.49#ibcon#wrote, iclass 17, count 0 2006.173.14:40:42.49#ibcon#about to read 3, iclass 17, count 0 2006.173.14:40:42.52#ibcon#read 3, iclass 17, count 0 2006.173.14:40:42.52#ibcon#about to read 4, iclass 17, count 0 2006.173.14:40:42.52#ibcon#read 4, iclass 17, count 0 2006.173.14:40:42.52#ibcon#about to read 5, iclass 17, count 0 2006.173.14:40:42.52#ibcon#read 5, iclass 17, count 0 2006.173.14:40:42.52#ibcon#about to read 6, iclass 17, count 0 2006.173.14:40:42.52#ibcon#read 6, iclass 17, count 0 2006.173.14:40:42.52#ibcon#end of sib2, iclass 17, count 0 2006.173.14:40:42.52#ibcon#*after write, iclass 17, count 0 2006.173.14:40:42.52#ibcon#*before return 0, iclass 17, count 0 2006.173.14:40:42.52#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.14:40:42.52#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.14:40:42.52#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.14:40:42.52#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.14:40:42.52$vck44/valo=5,734.99 2006.173.14:40:42.52#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.14:40:42.52#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.14:40:42.52#ibcon#ireg 17 cls_cnt 0 2006.173.14:40:42.52#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.14:40:42.52#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.14:40:42.52#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.14:40:42.52#ibcon#enter wrdev, iclass 19, count 0 2006.173.14:40:42.52#ibcon#first serial, iclass 19, count 0 2006.173.14:40:42.52#ibcon#enter sib2, iclass 19, count 0 2006.173.14:40:42.52#ibcon#flushed, iclass 19, count 0 2006.173.14:40:42.52#ibcon#about to write, iclass 19, count 0 2006.173.14:40:42.52#ibcon#wrote, iclass 19, count 0 2006.173.14:40:42.52#ibcon#about to read 3, iclass 19, count 0 2006.173.14:40:42.54#ibcon#read 3, iclass 19, count 0 2006.173.14:40:42.54#ibcon#about to read 4, iclass 19, count 0 2006.173.14:40:42.54#ibcon#read 4, iclass 19, count 0 2006.173.14:40:42.54#ibcon#about to read 5, iclass 19, count 0 2006.173.14:40:42.54#ibcon#read 5, iclass 19, count 0 2006.173.14:40:42.54#ibcon#about to read 6, iclass 19, count 0 2006.173.14:40:42.54#ibcon#read 6, iclass 19, count 0 2006.173.14:40:42.54#ibcon#end of sib2, iclass 19, count 0 2006.173.14:40:42.54#ibcon#*mode == 0, iclass 19, count 0 2006.173.14:40:42.54#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.14:40:42.54#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.14:40:42.54#ibcon#*before write, iclass 19, count 0 2006.173.14:40:42.54#ibcon#enter sib2, iclass 19, count 0 2006.173.14:40:42.54#ibcon#flushed, iclass 19, count 0 2006.173.14:40:42.54#ibcon#about to write, iclass 19, count 0 2006.173.14:40:42.54#ibcon#wrote, iclass 19, count 0 2006.173.14:40:42.54#ibcon#about to read 3, iclass 19, count 0 2006.173.14:40:42.58#ibcon#read 3, iclass 19, count 0 2006.173.14:40:42.58#ibcon#about to read 4, iclass 19, count 0 2006.173.14:40:42.58#ibcon#read 4, iclass 19, count 0 2006.173.14:40:42.58#ibcon#about to read 5, iclass 19, count 0 2006.173.14:40:42.58#ibcon#read 5, iclass 19, count 0 2006.173.14:40:42.58#ibcon#about to read 6, iclass 19, count 0 2006.173.14:40:42.58#ibcon#read 6, iclass 19, count 0 2006.173.14:40:42.58#ibcon#end of sib2, iclass 19, count 0 2006.173.14:40:42.58#ibcon#*after write, iclass 19, count 0 2006.173.14:40:42.58#ibcon#*before return 0, iclass 19, count 0 2006.173.14:40:42.58#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.14:40:42.58#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.14:40:42.58#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.14:40:42.58#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.14:40:42.58$vck44/va=5,4 2006.173.14:40:42.58#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.14:40:42.58#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.14:40:42.58#ibcon#ireg 11 cls_cnt 2 2006.173.14:40:42.58#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.14:40:42.64#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.14:40:42.64#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.14:40:42.64#ibcon#enter wrdev, iclass 21, count 2 2006.173.14:40:42.64#ibcon#first serial, iclass 21, count 2 2006.173.14:40:42.64#ibcon#enter sib2, iclass 21, count 2 2006.173.14:40:42.64#ibcon#flushed, iclass 21, count 2 2006.173.14:40:42.64#ibcon#about to write, iclass 21, count 2 2006.173.14:40:42.64#ibcon#wrote, iclass 21, count 2 2006.173.14:40:42.64#ibcon#about to read 3, iclass 21, count 2 2006.173.14:40:42.66#ibcon#read 3, iclass 21, count 2 2006.173.14:40:42.66#ibcon#about to read 4, iclass 21, count 2 2006.173.14:40:42.66#ibcon#read 4, iclass 21, count 2 2006.173.14:40:42.66#ibcon#about to read 5, iclass 21, count 2 2006.173.14:40:42.66#ibcon#read 5, iclass 21, count 2 2006.173.14:40:42.66#ibcon#about to read 6, iclass 21, count 2 2006.173.14:40:42.66#ibcon#read 6, iclass 21, count 2 2006.173.14:40:42.66#ibcon#end of sib2, iclass 21, count 2 2006.173.14:40:42.66#ibcon#*mode == 0, iclass 21, count 2 2006.173.14:40:42.66#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.14:40:42.66#ibcon#[25=AT05-04\r\n] 2006.173.14:40:42.66#ibcon#*before write, iclass 21, count 2 2006.173.14:40:42.66#ibcon#enter sib2, iclass 21, count 2 2006.173.14:40:42.66#ibcon#flushed, iclass 21, count 2 2006.173.14:40:42.66#ibcon#about to write, iclass 21, count 2 2006.173.14:40:42.66#ibcon#wrote, iclass 21, count 2 2006.173.14:40:42.66#ibcon#about to read 3, iclass 21, count 2 2006.173.14:40:42.69#ibcon#read 3, iclass 21, count 2 2006.173.14:40:42.69#ibcon#about to read 4, iclass 21, count 2 2006.173.14:40:42.69#ibcon#read 4, iclass 21, count 2 2006.173.14:40:42.69#ibcon#about to read 5, iclass 21, count 2 2006.173.14:40:42.69#ibcon#read 5, iclass 21, count 2 2006.173.14:40:42.69#ibcon#about to read 6, iclass 21, count 2 2006.173.14:40:42.69#ibcon#read 6, iclass 21, count 2 2006.173.14:40:42.69#ibcon#end of sib2, iclass 21, count 2 2006.173.14:40:42.69#ibcon#*after write, iclass 21, count 2 2006.173.14:40:42.69#ibcon#*before return 0, iclass 21, count 2 2006.173.14:40:42.69#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.14:40:42.69#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.14:40:42.69#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.14:40:42.69#ibcon#ireg 7 cls_cnt 0 2006.173.14:40:42.69#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.14:40:42.81#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.14:40:42.81#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.14:40:42.81#ibcon#enter wrdev, iclass 21, count 0 2006.173.14:40:42.81#ibcon#first serial, iclass 21, count 0 2006.173.14:40:42.81#ibcon#enter sib2, iclass 21, count 0 2006.173.14:40:42.81#ibcon#flushed, iclass 21, count 0 2006.173.14:40:42.81#ibcon#about to write, iclass 21, count 0 2006.173.14:40:42.81#ibcon#wrote, iclass 21, count 0 2006.173.14:40:42.81#ibcon#about to read 3, iclass 21, count 0 2006.173.14:40:42.83#ibcon#read 3, iclass 21, count 0 2006.173.14:40:42.83#ibcon#about to read 4, iclass 21, count 0 2006.173.14:40:42.83#ibcon#read 4, iclass 21, count 0 2006.173.14:40:42.83#ibcon#about to read 5, iclass 21, count 0 2006.173.14:40:42.83#ibcon#read 5, iclass 21, count 0 2006.173.14:40:42.83#ibcon#about to read 6, iclass 21, count 0 2006.173.14:40:42.83#ibcon#read 6, iclass 21, count 0 2006.173.14:40:42.83#ibcon#end of sib2, iclass 21, count 0 2006.173.14:40:42.83#ibcon#*mode == 0, iclass 21, count 0 2006.173.14:40:42.83#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.14:40:42.83#ibcon#[25=USB\r\n] 2006.173.14:40:42.83#ibcon#*before write, iclass 21, count 0 2006.173.14:40:42.83#ibcon#enter sib2, iclass 21, count 0 2006.173.14:40:42.83#ibcon#flushed, iclass 21, count 0 2006.173.14:40:42.83#ibcon#about to write, iclass 21, count 0 2006.173.14:40:42.83#ibcon#wrote, iclass 21, count 0 2006.173.14:40:42.83#ibcon#about to read 3, iclass 21, count 0 2006.173.14:40:42.86#ibcon#read 3, iclass 21, count 0 2006.173.14:40:42.86#ibcon#about to read 4, iclass 21, count 0 2006.173.14:40:42.86#ibcon#read 4, iclass 21, count 0 2006.173.14:40:42.86#ibcon#about to read 5, iclass 21, count 0 2006.173.14:40:42.86#ibcon#read 5, iclass 21, count 0 2006.173.14:40:42.86#ibcon#about to read 6, iclass 21, count 0 2006.173.14:40:42.86#ibcon#read 6, iclass 21, count 0 2006.173.14:40:42.86#ibcon#end of sib2, iclass 21, count 0 2006.173.14:40:42.86#ibcon#*after write, iclass 21, count 0 2006.173.14:40:42.86#ibcon#*before return 0, iclass 21, count 0 2006.173.14:40:42.86#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.14:40:42.86#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.14:40:42.86#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.14:40:42.86#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.14:40:42.86$vck44/valo=6,814.99 2006.173.14:40:42.86#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.14:40:42.86#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.14:40:42.86#ibcon#ireg 17 cls_cnt 0 2006.173.14:40:42.86#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.14:40:42.86#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.14:40:42.86#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.14:40:42.86#ibcon#enter wrdev, iclass 23, count 0 2006.173.14:40:42.86#ibcon#first serial, iclass 23, count 0 2006.173.14:40:42.86#ibcon#enter sib2, iclass 23, count 0 2006.173.14:40:42.86#ibcon#flushed, iclass 23, count 0 2006.173.14:40:42.86#ibcon#about to write, iclass 23, count 0 2006.173.14:40:42.86#ibcon#wrote, iclass 23, count 0 2006.173.14:40:42.86#ibcon#about to read 3, iclass 23, count 0 2006.173.14:40:42.88#ibcon#read 3, iclass 23, count 0 2006.173.14:40:42.88#ibcon#about to read 4, iclass 23, count 0 2006.173.14:40:42.88#ibcon#read 4, iclass 23, count 0 2006.173.14:40:42.88#ibcon#about to read 5, iclass 23, count 0 2006.173.14:40:42.88#ibcon#read 5, iclass 23, count 0 2006.173.14:40:42.88#ibcon#about to read 6, iclass 23, count 0 2006.173.14:40:42.88#ibcon#read 6, iclass 23, count 0 2006.173.14:40:42.88#ibcon#end of sib2, iclass 23, count 0 2006.173.14:40:42.88#ibcon#*mode == 0, iclass 23, count 0 2006.173.14:40:42.88#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.14:40:42.88#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.14:40:42.88#ibcon#*before write, iclass 23, count 0 2006.173.14:40:42.88#ibcon#enter sib2, iclass 23, count 0 2006.173.14:40:42.88#ibcon#flushed, iclass 23, count 0 2006.173.14:40:42.88#ibcon#about to write, iclass 23, count 0 2006.173.14:40:42.88#ibcon#wrote, iclass 23, count 0 2006.173.14:40:42.88#ibcon#about to read 3, iclass 23, count 0 2006.173.14:40:42.92#ibcon#read 3, iclass 23, count 0 2006.173.14:40:42.92#ibcon#about to read 4, iclass 23, count 0 2006.173.14:40:42.92#ibcon#read 4, iclass 23, count 0 2006.173.14:40:42.92#ibcon#about to read 5, iclass 23, count 0 2006.173.14:40:42.92#ibcon#read 5, iclass 23, count 0 2006.173.14:40:42.92#ibcon#about to read 6, iclass 23, count 0 2006.173.14:40:42.92#ibcon#read 6, iclass 23, count 0 2006.173.14:40:42.92#ibcon#end of sib2, iclass 23, count 0 2006.173.14:40:42.92#ibcon#*after write, iclass 23, count 0 2006.173.14:40:42.92#ibcon#*before return 0, iclass 23, count 0 2006.173.14:40:42.92#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.14:40:42.92#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.14:40:42.92#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.14:40:42.92#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.14:40:42.92$vck44/va=6,3 2006.173.14:40:42.92#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.14:40:42.92#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.14:40:42.92#ibcon#ireg 11 cls_cnt 2 2006.173.14:40:42.92#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.14:40:42.98#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.14:40:42.98#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.14:40:42.98#ibcon#enter wrdev, iclass 25, count 2 2006.173.14:40:42.98#ibcon#first serial, iclass 25, count 2 2006.173.14:40:42.98#ibcon#enter sib2, iclass 25, count 2 2006.173.14:40:42.98#ibcon#flushed, iclass 25, count 2 2006.173.14:40:42.98#ibcon#about to write, iclass 25, count 2 2006.173.14:40:42.98#ibcon#wrote, iclass 25, count 2 2006.173.14:40:42.98#ibcon#about to read 3, iclass 25, count 2 2006.173.14:40:43.00#ibcon#read 3, iclass 25, count 2 2006.173.14:40:43.00#ibcon#about to read 4, iclass 25, count 2 2006.173.14:40:43.00#ibcon#read 4, iclass 25, count 2 2006.173.14:40:43.00#ibcon#about to read 5, iclass 25, count 2 2006.173.14:40:43.00#ibcon#read 5, iclass 25, count 2 2006.173.14:40:43.00#ibcon#about to read 6, iclass 25, count 2 2006.173.14:40:43.00#ibcon#read 6, iclass 25, count 2 2006.173.14:40:43.00#ibcon#end of sib2, iclass 25, count 2 2006.173.14:40:43.00#ibcon#*mode == 0, iclass 25, count 2 2006.173.14:40:43.00#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.14:40:43.00#ibcon#[25=AT06-03\r\n] 2006.173.14:40:43.00#ibcon#*before write, iclass 25, count 2 2006.173.14:40:43.00#ibcon#enter sib2, iclass 25, count 2 2006.173.14:40:43.00#ibcon#flushed, iclass 25, count 2 2006.173.14:40:43.00#ibcon#about to write, iclass 25, count 2 2006.173.14:40:43.00#ibcon#wrote, iclass 25, count 2 2006.173.14:40:43.00#ibcon#about to read 3, iclass 25, count 2 2006.173.14:40:43.03#ibcon#read 3, iclass 25, count 2 2006.173.14:40:43.03#ibcon#about to read 4, iclass 25, count 2 2006.173.14:40:43.03#ibcon#read 4, iclass 25, count 2 2006.173.14:40:43.03#ibcon#about to read 5, iclass 25, count 2 2006.173.14:40:43.03#ibcon#read 5, iclass 25, count 2 2006.173.14:40:43.03#ibcon#about to read 6, iclass 25, count 2 2006.173.14:40:43.03#ibcon#read 6, iclass 25, count 2 2006.173.14:40:43.03#ibcon#end of sib2, iclass 25, count 2 2006.173.14:40:43.03#ibcon#*after write, iclass 25, count 2 2006.173.14:40:43.03#ibcon#*before return 0, iclass 25, count 2 2006.173.14:40:43.03#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.14:40:43.03#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.14:40:43.03#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.14:40:43.03#ibcon#ireg 7 cls_cnt 0 2006.173.14:40:43.03#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.14:40:43.15#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.14:40:43.15#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.14:40:43.15#ibcon#enter wrdev, iclass 25, count 0 2006.173.14:40:43.15#ibcon#first serial, iclass 25, count 0 2006.173.14:40:43.15#ibcon#enter sib2, iclass 25, count 0 2006.173.14:40:43.15#ibcon#flushed, iclass 25, count 0 2006.173.14:40:43.15#ibcon#about to write, iclass 25, count 0 2006.173.14:40:43.15#ibcon#wrote, iclass 25, count 0 2006.173.14:40:43.15#ibcon#about to read 3, iclass 25, count 0 2006.173.14:40:43.17#ibcon#read 3, iclass 25, count 0 2006.173.14:40:43.17#ibcon#about to read 4, iclass 25, count 0 2006.173.14:40:43.17#ibcon#read 4, iclass 25, count 0 2006.173.14:40:43.17#ibcon#about to read 5, iclass 25, count 0 2006.173.14:40:43.17#ibcon#read 5, iclass 25, count 0 2006.173.14:40:43.17#ibcon#about to read 6, iclass 25, count 0 2006.173.14:40:43.17#ibcon#read 6, iclass 25, count 0 2006.173.14:40:43.17#ibcon#end of sib2, iclass 25, count 0 2006.173.14:40:43.17#ibcon#*mode == 0, iclass 25, count 0 2006.173.14:40:43.17#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.14:40:43.17#ibcon#[25=USB\r\n] 2006.173.14:40:43.17#ibcon#*before write, iclass 25, count 0 2006.173.14:40:43.17#ibcon#enter sib2, iclass 25, count 0 2006.173.14:40:43.17#ibcon#flushed, iclass 25, count 0 2006.173.14:40:43.17#ibcon#about to write, iclass 25, count 0 2006.173.14:40:43.17#ibcon#wrote, iclass 25, count 0 2006.173.14:40:43.17#ibcon#about to read 3, iclass 25, count 0 2006.173.14:40:43.20#ibcon#read 3, iclass 25, count 0 2006.173.14:40:43.20#ibcon#about to read 4, iclass 25, count 0 2006.173.14:40:43.20#ibcon#read 4, iclass 25, count 0 2006.173.14:40:43.20#ibcon#about to read 5, iclass 25, count 0 2006.173.14:40:43.20#ibcon#read 5, iclass 25, count 0 2006.173.14:40:43.20#ibcon#about to read 6, iclass 25, count 0 2006.173.14:40:43.20#ibcon#read 6, iclass 25, count 0 2006.173.14:40:43.20#ibcon#end of sib2, iclass 25, count 0 2006.173.14:40:43.20#ibcon#*after write, iclass 25, count 0 2006.173.14:40:43.20#ibcon#*before return 0, iclass 25, count 0 2006.173.14:40:43.20#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.14:40:43.20#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.14:40:43.20#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.14:40:43.20#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.14:40:43.20$vck44/valo=7,864.99 2006.173.14:40:43.20#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.14:40:43.20#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.14:40:43.20#ibcon#ireg 17 cls_cnt 0 2006.173.14:40:43.20#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.14:40:43.20#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.14:40:43.20#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.14:40:43.20#ibcon#enter wrdev, iclass 27, count 0 2006.173.14:40:43.20#ibcon#first serial, iclass 27, count 0 2006.173.14:40:43.20#ibcon#enter sib2, iclass 27, count 0 2006.173.14:40:43.20#ibcon#flushed, iclass 27, count 0 2006.173.14:40:43.20#ibcon#about to write, iclass 27, count 0 2006.173.14:40:43.20#ibcon#wrote, iclass 27, count 0 2006.173.14:40:43.20#ibcon#about to read 3, iclass 27, count 0 2006.173.14:40:43.22#ibcon#read 3, iclass 27, count 0 2006.173.14:40:43.22#ibcon#about to read 4, iclass 27, count 0 2006.173.14:40:43.22#ibcon#read 4, iclass 27, count 0 2006.173.14:40:43.22#ibcon#about to read 5, iclass 27, count 0 2006.173.14:40:43.22#ibcon#read 5, iclass 27, count 0 2006.173.14:40:43.22#ibcon#about to read 6, iclass 27, count 0 2006.173.14:40:43.22#ibcon#read 6, iclass 27, count 0 2006.173.14:40:43.22#ibcon#end of sib2, iclass 27, count 0 2006.173.14:40:43.22#ibcon#*mode == 0, iclass 27, count 0 2006.173.14:40:43.22#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.14:40:43.22#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.14:40:43.22#ibcon#*before write, iclass 27, count 0 2006.173.14:40:43.22#ibcon#enter sib2, iclass 27, count 0 2006.173.14:40:43.22#ibcon#flushed, iclass 27, count 0 2006.173.14:40:43.22#ibcon#about to write, iclass 27, count 0 2006.173.14:40:43.22#ibcon#wrote, iclass 27, count 0 2006.173.14:40:43.22#ibcon#about to read 3, iclass 27, count 0 2006.173.14:40:43.26#ibcon#read 3, iclass 27, count 0 2006.173.14:40:43.26#ibcon#about to read 4, iclass 27, count 0 2006.173.14:40:43.26#ibcon#read 4, iclass 27, count 0 2006.173.14:40:43.26#ibcon#about to read 5, iclass 27, count 0 2006.173.14:40:43.26#ibcon#read 5, iclass 27, count 0 2006.173.14:40:43.26#ibcon#about to read 6, iclass 27, count 0 2006.173.14:40:43.26#ibcon#read 6, iclass 27, count 0 2006.173.14:40:43.26#ibcon#end of sib2, iclass 27, count 0 2006.173.14:40:43.26#ibcon#*after write, iclass 27, count 0 2006.173.14:40:43.26#ibcon#*before return 0, iclass 27, count 0 2006.173.14:40:43.26#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.14:40:43.26#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.14:40:43.26#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.14:40:43.26#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.14:40:43.26$vck44/va=7,4 2006.173.14:40:43.26#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.14:40:43.26#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.14:40:43.26#ibcon#ireg 11 cls_cnt 2 2006.173.14:40:43.26#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.14:40:43.32#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.14:40:43.32#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.14:40:43.32#ibcon#enter wrdev, iclass 29, count 2 2006.173.14:40:43.32#ibcon#first serial, iclass 29, count 2 2006.173.14:40:43.32#ibcon#enter sib2, iclass 29, count 2 2006.173.14:40:43.32#ibcon#flushed, iclass 29, count 2 2006.173.14:40:43.32#ibcon#about to write, iclass 29, count 2 2006.173.14:40:43.32#ibcon#wrote, iclass 29, count 2 2006.173.14:40:43.32#ibcon#about to read 3, iclass 29, count 2 2006.173.14:40:43.34#ibcon#read 3, iclass 29, count 2 2006.173.14:40:43.34#ibcon#about to read 4, iclass 29, count 2 2006.173.14:40:43.34#ibcon#read 4, iclass 29, count 2 2006.173.14:40:43.34#ibcon#about to read 5, iclass 29, count 2 2006.173.14:40:43.34#ibcon#read 5, iclass 29, count 2 2006.173.14:40:43.34#ibcon#about to read 6, iclass 29, count 2 2006.173.14:40:43.34#ibcon#read 6, iclass 29, count 2 2006.173.14:40:43.34#ibcon#end of sib2, iclass 29, count 2 2006.173.14:40:43.34#ibcon#*mode == 0, iclass 29, count 2 2006.173.14:40:43.34#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.14:40:43.34#ibcon#[25=AT07-04\r\n] 2006.173.14:40:43.34#ibcon#*before write, iclass 29, count 2 2006.173.14:40:43.34#ibcon#enter sib2, iclass 29, count 2 2006.173.14:40:43.34#ibcon#flushed, iclass 29, count 2 2006.173.14:40:43.34#ibcon#about to write, iclass 29, count 2 2006.173.14:40:43.34#ibcon#wrote, iclass 29, count 2 2006.173.14:40:43.34#ibcon#about to read 3, iclass 29, count 2 2006.173.14:40:43.37#ibcon#read 3, iclass 29, count 2 2006.173.14:40:43.37#ibcon#about to read 4, iclass 29, count 2 2006.173.14:40:43.37#ibcon#read 4, iclass 29, count 2 2006.173.14:40:43.37#ibcon#about to read 5, iclass 29, count 2 2006.173.14:40:43.37#ibcon#read 5, iclass 29, count 2 2006.173.14:40:43.37#ibcon#about to read 6, iclass 29, count 2 2006.173.14:40:43.37#ibcon#read 6, iclass 29, count 2 2006.173.14:40:43.37#ibcon#end of sib2, iclass 29, count 2 2006.173.14:40:43.37#ibcon#*after write, iclass 29, count 2 2006.173.14:40:43.37#ibcon#*before return 0, iclass 29, count 2 2006.173.14:40:43.37#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.14:40:43.37#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.14:40:43.37#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.14:40:43.37#ibcon#ireg 7 cls_cnt 0 2006.173.14:40:43.37#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.14:40:43.49#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.14:40:43.49#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.14:40:43.49#ibcon#enter wrdev, iclass 29, count 0 2006.173.14:40:43.49#ibcon#first serial, iclass 29, count 0 2006.173.14:40:43.49#ibcon#enter sib2, iclass 29, count 0 2006.173.14:40:43.49#ibcon#flushed, iclass 29, count 0 2006.173.14:40:43.49#ibcon#about to write, iclass 29, count 0 2006.173.14:40:43.49#ibcon#wrote, iclass 29, count 0 2006.173.14:40:43.49#ibcon#about to read 3, iclass 29, count 0 2006.173.14:40:43.51#ibcon#read 3, iclass 29, count 0 2006.173.14:40:43.51#ibcon#about to read 4, iclass 29, count 0 2006.173.14:40:43.51#ibcon#read 4, iclass 29, count 0 2006.173.14:40:43.51#ibcon#about to read 5, iclass 29, count 0 2006.173.14:40:43.51#ibcon#read 5, iclass 29, count 0 2006.173.14:40:43.51#ibcon#about to read 6, iclass 29, count 0 2006.173.14:40:43.51#ibcon#read 6, iclass 29, count 0 2006.173.14:40:43.51#ibcon#end of sib2, iclass 29, count 0 2006.173.14:40:43.51#ibcon#*mode == 0, iclass 29, count 0 2006.173.14:40:43.51#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.14:40:43.51#ibcon#[25=USB\r\n] 2006.173.14:40:43.51#ibcon#*before write, iclass 29, count 0 2006.173.14:40:43.51#ibcon#enter sib2, iclass 29, count 0 2006.173.14:40:43.51#ibcon#flushed, iclass 29, count 0 2006.173.14:40:43.51#ibcon#about to write, iclass 29, count 0 2006.173.14:40:43.51#ibcon#wrote, iclass 29, count 0 2006.173.14:40:43.51#ibcon#about to read 3, iclass 29, count 0 2006.173.14:40:43.54#ibcon#read 3, iclass 29, count 0 2006.173.14:40:43.54#ibcon#about to read 4, iclass 29, count 0 2006.173.14:40:43.54#ibcon#read 4, iclass 29, count 0 2006.173.14:40:43.54#ibcon#about to read 5, iclass 29, count 0 2006.173.14:40:43.54#ibcon#read 5, iclass 29, count 0 2006.173.14:40:43.54#ibcon#about to read 6, iclass 29, count 0 2006.173.14:40:43.54#ibcon#read 6, iclass 29, count 0 2006.173.14:40:43.54#ibcon#end of sib2, iclass 29, count 0 2006.173.14:40:43.54#ibcon#*after write, iclass 29, count 0 2006.173.14:40:43.54#ibcon#*before return 0, iclass 29, count 0 2006.173.14:40:43.54#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.14:40:43.54#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.14:40:43.54#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.14:40:43.54#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.14:40:43.54$vck44/valo=8,884.99 2006.173.14:40:43.54#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.14:40:43.54#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.14:40:43.54#ibcon#ireg 17 cls_cnt 0 2006.173.14:40:43.54#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.14:40:43.54#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.14:40:43.54#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.14:40:43.54#ibcon#enter wrdev, iclass 31, count 0 2006.173.14:40:43.54#ibcon#first serial, iclass 31, count 0 2006.173.14:40:43.54#ibcon#enter sib2, iclass 31, count 0 2006.173.14:40:43.54#ibcon#flushed, iclass 31, count 0 2006.173.14:40:43.54#ibcon#about to write, iclass 31, count 0 2006.173.14:40:43.54#ibcon#wrote, iclass 31, count 0 2006.173.14:40:43.54#ibcon#about to read 3, iclass 31, count 0 2006.173.14:40:43.56#ibcon#read 3, iclass 31, count 0 2006.173.14:40:43.56#ibcon#about to read 4, iclass 31, count 0 2006.173.14:40:43.56#ibcon#read 4, iclass 31, count 0 2006.173.14:40:43.56#ibcon#about to read 5, iclass 31, count 0 2006.173.14:40:43.56#ibcon#read 5, iclass 31, count 0 2006.173.14:40:43.56#ibcon#about to read 6, iclass 31, count 0 2006.173.14:40:43.56#ibcon#read 6, iclass 31, count 0 2006.173.14:40:43.56#ibcon#end of sib2, iclass 31, count 0 2006.173.14:40:43.56#ibcon#*mode == 0, iclass 31, count 0 2006.173.14:40:43.56#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.14:40:43.56#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.14:40:43.56#ibcon#*before write, iclass 31, count 0 2006.173.14:40:43.56#ibcon#enter sib2, iclass 31, count 0 2006.173.14:40:43.56#ibcon#flushed, iclass 31, count 0 2006.173.14:40:43.56#ibcon#about to write, iclass 31, count 0 2006.173.14:40:43.56#ibcon#wrote, iclass 31, count 0 2006.173.14:40:43.56#ibcon#about to read 3, iclass 31, count 0 2006.173.14:40:43.60#ibcon#read 3, iclass 31, count 0 2006.173.14:40:43.60#ibcon#about to read 4, iclass 31, count 0 2006.173.14:40:43.60#ibcon#read 4, iclass 31, count 0 2006.173.14:40:43.60#ibcon#about to read 5, iclass 31, count 0 2006.173.14:40:43.60#ibcon#read 5, iclass 31, count 0 2006.173.14:40:43.60#ibcon#about to read 6, iclass 31, count 0 2006.173.14:40:43.60#ibcon#read 6, iclass 31, count 0 2006.173.14:40:43.60#ibcon#end of sib2, iclass 31, count 0 2006.173.14:40:43.60#ibcon#*after write, iclass 31, count 0 2006.173.14:40:43.60#ibcon#*before return 0, iclass 31, count 0 2006.173.14:40:43.60#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.14:40:43.60#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.14:40:43.60#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.14:40:43.60#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.14:40:43.60$vck44/va=8,4 2006.173.14:40:43.60#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.173.14:40:43.60#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.173.14:40:43.60#ibcon#ireg 11 cls_cnt 2 2006.173.14:40:43.60#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.14:40:43.66#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.14:40:43.66#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.14:40:43.66#ibcon#enter wrdev, iclass 33, count 2 2006.173.14:40:43.66#ibcon#first serial, iclass 33, count 2 2006.173.14:40:43.66#ibcon#enter sib2, iclass 33, count 2 2006.173.14:40:43.66#ibcon#flushed, iclass 33, count 2 2006.173.14:40:43.66#ibcon#about to write, iclass 33, count 2 2006.173.14:40:43.66#ibcon#wrote, iclass 33, count 2 2006.173.14:40:43.66#ibcon#about to read 3, iclass 33, count 2 2006.173.14:40:43.68#ibcon#read 3, iclass 33, count 2 2006.173.14:40:43.68#ibcon#about to read 4, iclass 33, count 2 2006.173.14:40:43.68#ibcon#read 4, iclass 33, count 2 2006.173.14:40:43.68#ibcon#about to read 5, iclass 33, count 2 2006.173.14:40:43.68#ibcon#read 5, iclass 33, count 2 2006.173.14:40:43.68#ibcon#about to read 6, iclass 33, count 2 2006.173.14:40:43.68#ibcon#read 6, iclass 33, count 2 2006.173.14:40:43.68#ibcon#end of sib2, iclass 33, count 2 2006.173.14:40:43.68#ibcon#*mode == 0, iclass 33, count 2 2006.173.14:40:43.68#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.173.14:40:43.68#ibcon#[25=AT08-04\r\n] 2006.173.14:40:43.68#ibcon#*before write, iclass 33, count 2 2006.173.14:40:43.68#ibcon#enter sib2, iclass 33, count 2 2006.173.14:40:43.68#ibcon#flushed, iclass 33, count 2 2006.173.14:40:43.68#ibcon#about to write, iclass 33, count 2 2006.173.14:40:43.68#ibcon#wrote, iclass 33, count 2 2006.173.14:40:43.68#ibcon#about to read 3, iclass 33, count 2 2006.173.14:40:43.71#ibcon#read 3, iclass 33, count 2 2006.173.14:40:43.71#ibcon#about to read 4, iclass 33, count 2 2006.173.14:40:43.71#ibcon#read 4, iclass 33, count 2 2006.173.14:40:43.71#ibcon#about to read 5, iclass 33, count 2 2006.173.14:40:43.71#ibcon#read 5, iclass 33, count 2 2006.173.14:40:43.71#ibcon#about to read 6, iclass 33, count 2 2006.173.14:40:43.71#ibcon#read 6, iclass 33, count 2 2006.173.14:40:43.71#ibcon#end of sib2, iclass 33, count 2 2006.173.14:40:43.71#ibcon#*after write, iclass 33, count 2 2006.173.14:40:43.71#ibcon#*before return 0, iclass 33, count 2 2006.173.14:40:43.71#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.14:40:43.71#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.173.14:40:43.71#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.173.14:40:43.71#ibcon#ireg 7 cls_cnt 0 2006.173.14:40:43.71#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.14:40:43.75#abcon#<5=/14 1.4 4.0 21.151001004.0\r\n> 2006.173.14:40:43.77#abcon#{5=INTERFACE CLEAR} 2006.173.14:40:43.83#abcon#[5=S1D000X0/0*\r\n] 2006.173.14:40:43.83#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.14:40:43.83#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.14:40:43.83#ibcon#enter wrdev, iclass 33, count 0 2006.173.14:40:43.83#ibcon#first serial, iclass 33, count 0 2006.173.14:40:43.83#ibcon#enter sib2, iclass 33, count 0 2006.173.14:40:43.83#ibcon#flushed, iclass 33, count 0 2006.173.14:40:43.83#ibcon#about to write, iclass 33, count 0 2006.173.14:40:43.83#ibcon#wrote, iclass 33, count 0 2006.173.14:40:43.83#ibcon#about to read 3, iclass 33, count 0 2006.173.14:40:43.85#ibcon#read 3, iclass 33, count 0 2006.173.14:40:43.85#ibcon#about to read 4, iclass 33, count 0 2006.173.14:40:43.85#ibcon#read 4, iclass 33, count 0 2006.173.14:40:43.85#ibcon#about to read 5, iclass 33, count 0 2006.173.14:40:43.85#ibcon#read 5, iclass 33, count 0 2006.173.14:40:43.85#ibcon#about to read 6, iclass 33, count 0 2006.173.14:40:43.85#ibcon#read 6, iclass 33, count 0 2006.173.14:40:43.85#ibcon#end of sib2, iclass 33, count 0 2006.173.14:40:43.85#ibcon#*mode == 0, iclass 33, count 0 2006.173.14:40:43.85#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.14:40:43.85#ibcon#[25=USB\r\n] 2006.173.14:40:43.85#ibcon#*before write, iclass 33, count 0 2006.173.14:40:43.85#ibcon#enter sib2, iclass 33, count 0 2006.173.14:40:43.85#ibcon#flushed, iclass 33, count 0 2006.173.14:40:43.85#ibcon#about to write, iclass 33, count 0 2006.173.14:40:43.85#ibcon#wrote, iclass 33, count 0 2006.173.14:40:43.85#ibcon#about to read 3, iclass 33, count 0 2006.173.14:40:43.88#ibcon#read 3, iclass 33, count 0 2006.173.14:40:43.88#ibcon#about to read 4, iclass 33, count 0 2006.173.14:40:43.88#ibcon#read 4, iclass 33, count 0 2006.173.14:40:43.88#ibcon#about to read 5, iclass 33, count 0 2006.173.14:40:43.88#ibcon#read 5, iclass 33, count 0 2006.173.14:40:43.88#ibcon#about to read 6, iclass 33, count 0 2006.173.14:40:43.88#ibcon#read 6, iclass 33, count 0 2006.173.14:40:43.88#ibcon#end of sib2, iclass 33, count 0 2006.173.14:40:43.88#ibcon#*after write, iclass 33, count 0 2006.173.14:40:43.88#ibcon#*before return 0, iclass 33, count 0 2006.173.14:40:43.88#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.14:40:43.88#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.173.14:40:43.88#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.14:40:43.88#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.14:40:43.88$vck44/vblo=1,629.99 2006.173.14:40:43.88#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.14:40:43.88#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.14:40:43.88#ibcon#ireg 17 cls_cnt 0 2006.173.14:40:43.88#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.14:40:43.88#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.14:40:43.88#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.14:40:43.88#ibcon#enter wrdev, iclass 39, count 0 2006.173.14:40:43.88#ibcon#first serial, iclass 39, count 0 2006.173.14:40:43.88#ibcon#enter sib2, iclass 39, count 0 2006.173.14:40:43.88#ibcon#flushed, iclass 39, count 0 2006.173.14:40:43.88#ibcon#about to write, iclass 39, count 0 2006.173.14:40:43.88#ibcon#wrote, iclass 39, count 0 2006.173.14:40:43.88#ibcon#about to read 3, iclass 39, count 0 2006.173.14:40:43.90#ibcon#read 3, iclass 39, count 0 2006.173.14:40:43.90#ibcon#about to read 4, iclass 39, count 0 2006.173.14:40:43.90#ibcon#read 4, iclass 39, count 0 2006.173.14:40:43.90#ibcon#about to read 5, iclass 39, count 0 2006.173.14:40:43.90#ibcon#read 5, iclass 39, count 0 2006.173.14:40:43.90#ibcon#about to read 6, iclass 39, count 0 2006.173.14:40:43.90#ibcon#read 6, iclass 39, count 0 2006.173.14:40:43.90#ibcon#end of sib2, iclass 39, count 0 2006.173.14:40:43.90#ibcon#*mode == 0, iclass 39, count 0 2006.173.14:40:43.90#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.14:40:43.90#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.14:40:43.90#ibcon#*before write, iclass 39, count 0 2006.173.14:40:43.90#ibcon#enter sib2, iclass 39, count 0 2006.173.14:40:43.90#ibcon#flushed, iclass 39, count 0 2006.173.14:40:43.90#ibcon#about to write, iclass 39, count 0 2006.173.14:40:43.90#ibcon#wrote, iclass 39, count 0 2006.173.14:40:43.90#ibcon#about to read 3, iclass 39, count 0 2006.173.14:40:43.94#ibcon#read 3, iclass 39, count 0 2006.173.14:40:43.94#ibcon#about to read 4, iclass 39, count 0 2006.173.14:40:43.94#ibcon#read 4, iclass 39, count 0 2006.173.14:40:43.94#ibcon#about to read 5, iclass 39, count 0 2006.173.14:40:43.94#ibcon#read 5, iclass 39, count 0 2006.173.14:40:43.94#ibcon#about to read 6, iclass 39, count 0 2006.173.14:40:43.94#ibcon#read 6, iclass 39, count 0 2006.173.14:40:43.94#ibcon#end of sib2, iclass 39, count 0 2006.173.14:40:43.94#ibcon#*after write, iclass 39, count 0 2006.173.14:40:43.94#ibcon#*before return 0, iclass 39, count 0 2006.173.14:40:43.94#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.14:40:43.94#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.14:40:43.94#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.14:40:43.94#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.14:40:43.94$vck44/vb=1,4 2006.173.14:40:43.94#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.14:40:43.94#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.14:40:43.94#ibcon#ireg 11 cls_cnt 2 2006.173.14:40:43.94#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.14:40:43.94#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.14:40:43.94#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.14:40:43.94#ibcon#enter wrdev, iclass 3, count 2 2006.173.14:40:43.94#ibcon#first serial, iclass 3, count 2 2006.173.14:40:43.94#ibcon#enter sib2, iclass 3, count 2 2006.173.14:40:43.94#ibcon#flushed, iclass 3, count 2 2006.173.14:40:43.94#ibcon#about to write, iclass 3, count 2 2006.173.14:40:43.94#ibcon#wrote, iclass 3, count 2 2006.173.14:40:43.94#ibcon#about to read 3, iclass 3, count 2 2006.173.14:40:43.96#ibcon#read 3, iclass 3, count 2 2006.173.14:40:43.96#ibcon#about to read 4, iclass 3, count 2 2006.173.14:40:43.96#ibcon#read 4, iclass 3, count 2 2006.173.14:40:43.96#ibcon#about to read 5, iclass 3, count 2 2006.173.14:40:43.96#ibcon#read 5, iclass 3, count 2 2006.173.14:40:43.96#ibcon#about to read 6, iclass 3, count 2 2006.173.14:40:43.96#ibcon#read 6, iclass 3, count 2 2006.173.14:40:43.96#ibcon#end of sib2, iclass 3, count 2 2006.173.14:40:43.96#ibcon#*mode == 0, iclass 3, count 2 2006.173.14:40:43.96#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.14:40:43.96#ibcon#[27=AT01-04\r\n] 2006.173.14:40:43.96#ibcon#*before write, iclass 3, count 2 2006.173.14:40:43.96#ibcon#enter sib2, iclass 3, count 2 2006.173.14:40:43.96#ibcon#flushed, iclass 3, count 2 2006.173.14:40:43.96#ibcon#about to write, iclass 3, count 2 2006.173.14:40:43.96#ibcon#wrote, iclass 3, count 2 2006.173.14:40:43.96#ibcon#about to read 3, iclass 3, count 2 2006.173.14:40:43.99#ibcon#read 3, iclass 3, count 2 2006.173.14:40:43.99#ibcon#about to read 4, iclass 3, count 2 2006.173.14:40:43.99#ibcon#read 4, iclass 3, count 2 2006.173.14:40:43.99#ibcon#about to read 5, iclass 3, count 2 2006.173.14:40:43.99#ibcon#read 5, iclass 3, count 2 2006.173.14:40:43.99#ibcon#about to read 6, iclass 3, count 2 2006.173.14:40:43.99#ibcon#read 6, iclass 3, count 2 2006.173.14:40:43.99#ibcon#end of sib2, iclass 3, count 2 2006.173.14:40:43.99#ibcon#*after write, iclass 3, count 2 2006.173.14:40:43.99#ibcon#*before return 0, iclass 3, count 2 2006.173.14:40:43.99#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.14:40:43.99#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.14:40:43.99#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.14:40:43.99#ibcon#ireg 7 cls_cnt 0 2006.173.14:40:43.99#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.14:40:44.11#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.14:40:44.11#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.14:40:44.11#ibcon#enter wrdev, iclass 3, count 0 2006.173.14:40:44.11#ibcon#first serial, iclass 3, count 0 2006.173.14:40:44.11#ibcon#enter sib2, iclass 3, count 0 2006.173.14:40:44.11#ibcon#flushed, iclass 3, count 0 2006.173.14:40:44.11#ibcon#about to write, iclass 3, count 0 2006.173.14:40:44.11#ibcon#wrote, iclass 3, count 0 2006.173.14:40:44.11#ibcon#about to read 3, iclass 3, count 0 2006.173.14:40:44.13#ibcon#read 3, iclass 3, count 0 2006.173.14:40:44.13#ibcon#about to read 4, iclass 3, count 0 2006.173.14:40:44.13#ibcon#read 4, iclass 3, count 0 2006.173.14:40:44.13#ibcon#about to read 5, iclass 3, count 0 2006.173.14:40:44.13#ibcon#read 5, iclass 3, count 0 2006.173.14:40:44.13#ibcon#about to read 6, iclass 3, count 0 2006.173.14:40:44.13#ibcon#read 6, iclass 3, count 0 2006.173.14:40:44.13#ibcon#end of sib2, iclass 3, count 0 2006.173.14:40:44.13#ibcon#*mode == 0, iclass 3, count 0 2006.173.14:40:44.13#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.14:40:44.13#ibcon#[27=USB\r\n] 2006.173.14:40:44.13#ibcon#*before write, iclass 3, count 0 2006.173.14:40:44.13#ibcon#enter sib2, iclass 3, count 0 2006.173.14:40:44.13#ibcon#flushed, iclass 3, count 0 2006.173.14:40:44.13#ibcon#about to write, iclass 3, count 0 2006.173.14:40:44.13#ibcon#wrote, iclass 3, count 0 2006.173.14:40:44.13#ibcon#about to read 3, iclass 3, count 0 2006.173.14:40:44.16#ibcon#read 3, iclass 3, count 0 2006.173.14:40:44.16#ibcon#about to read 4, iclass 3, count 0 2006.173.14:40:44.16#ibcon#read 4, iclass 3, count 0 2006.173.14:40:44.16#ibcon#about to read 5, iclass 3, count 0 2006.173.14:40:44.16#ibcon#read 5, iclass 3, count 0 2006.173.14:40:44.16#ibcon#about to read 6, iclass 3, count 0 2006.173.14:40:44.16#ibcon#read 6, iclass 3, count 0 2006.173.14:40:44.16#ibcon#end of sib2, iclass 3, count 0 2006.173.14:40:44.16#ibcon#*after write, iclass 3, count 0 2006.173.14:40:44.16#ibcon#*before return 0, iclass 3, count 0 2006.173.14:40:44.16#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.14:40:44.16#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.14:40:44.16#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.14:40:44.16#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.14:40:44.16$vck44/vblo=2,634.99 2006.173.14:40:44.16#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.14:40:44.16#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.14:40:44.16#ibcon#ireg 17 cls_cnt 0 2006.173.14:40:44.16#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.14:40:44.16#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.14:40:44.16#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.14:40:44.16#ibcon#enter wrdev, iclass 5, count 0 2006.173.14:40:44.16#ibcon#first serial, iclass 5, count 0 2006.173.14:40:44.16#ibcon#enter sib2, iclass 5, count 0 2006.173.14:40:44.16#ibcon#flushed, iclass 5, count 0 2006.173.14:40:44.16#ibcon#about to write, iclass 5, count 0 2006.173.14:40:44.16#ibcon#wrote, iclass 5, count 0 2006.173.14:40:44.16#ibcon#about to read 3, iclass 5, count 0 2006.173.14:40:44.18#ibcon#read 3, iclass 5, count 0 2006.173.14:40:44.18#ibcon#about to read 4, iclass 5, count 0 2006.173.14:40:44.18#ibcon#read 4, iclass 5, count 0 2006.173.14:40:44.18#ibcon#about to read 5, iclass 5, count 0 2006.173.14:40:44.18#ibcon#read 5, iclass 5, count 0 2006.173.14:40:44.18#ibcon#about to read 6, iclass 5, count 0 2006.173.14:40:44.18#ibcon#read 6, iclass 5, count 0 2006.173.14:40:44.18#ibcon#end of sib2, iclass 5, count 0 2006.173.14:40:44.18#ibcon#*mode == 0, iclass 5, count 0 2006.173.14:40:44.18#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.14:40:44.18#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.14:40:44.18#ibcon#*before write, iclass 5, count 0 2006.173.14:40:44.18#ibcon#enter sib2, iclass 5, count 0 2006.173.14:40:44.18#ibcon#flushed, iclass 5, count 0 2006.173.14:40:44.18#ibcon#about to write, iclass 5, count 0 2006.173.14:40:44.18#ibcon#wrote, iclass 5, count 0 2006.173.14:40:44.18#ibcon#about to read 3, iclass 5, count 0 2006.173.14:40:44.22#ibcon#read 3, iclass 5, count 0 2006.173.14:40:44.22#ibcon#about to read 4, iclass 5, count 0 2006.173.14:40:44.22#ibcon#read 4, iclass 5, count 0 2006.173.14:40:44.22#ibcon#about to read 5, iclass 5, count 0 2006.173.14:40:44.22#ibcon#read 5, iclass 5, count 0 2006.173.14:40:44.22#ibcon#about to read 6, iclass 5, count 0 2006.173.14:40:44.22#ibcon#read 6, iclass 5, count 0 2006.173.14:40:44.22#ibcon#end of sib2, iclass 5, count 0 2006.173.14:40:44.22#ibcon#*after write, iclass 5, count 0 2006.173.14:40:44.22#ibcon#*before return 0, iclass 5, count 0 2006.173.14:40:44.22#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.14:40:44.22#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.14:40:44.22#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.14:40:44.22#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.14:40:44.22$vck44/vb=2,4 2006.173.14:40:44.22#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.173.14:40:44.22#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.173.14:40:44.22#ibcon#ireg 11 cls_cnt 2 2006.173.14:40:44.22#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.14:40:44.28#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.14:40:44.28#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.14:40:44.28#ibcon#enter wrdev, iclass 7, count 2 2006.173.14:40:44.28#ibcon#first serial, iclass 7, count 2 2006.173.14:40:44.28#ibcon#enter sib2, iclass 7, count 2 2006.173.14:40:44.28#ibcon#flushed, iclass 7, count 2 2006.173.14:40:44.28#ibcon#about to write, iclass 7, count 2 2006.173.14:40:44.28#ibcon#wrote, iclass 7, count 2 2006.173.14:40:44.28#ibcon#about to read 3, iclass 7, count 2 2006.173.14:40:44.30#ibcon#read 3, iclass 7, count 2 2006.173.14:40:44.30#ibcon#about to read 4, iclass 7, count 2 2006.173.14:40:44.30#ibcon#read 4, iclass 7, count 2 2006.173.14:40:44.30#ibcon#about to read 5, iclass 7, count 2 2006.173.14:40:44.30#ibcon#read 5, iclass 7, count 2 2006.173.14:40:44.30#ibcon#about to read 6, iclass 7, count 2 2006.173.14:40:44.30#ibcon#read 6, iclass 7, count 2 2006.173.14:40:44.30#ibcon#end of sib2, iclass 7, count 2 2006.173.14:40:44.30#ibcon#*mode == 0, iclass 7, count 2 2006.173.14:40:44.30#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.173.14:40:44.30#ibcon#[27=AT02-04\r\n] 2006.173.14:40:44.30#ibcon#*before write, iclass 7, count 2 2006.173.14:40:44.30#ibcon#enter sib2, iclass 7, count 2 2006.173.14:40:44.30#ibcon#flushed, iclass 7, count 2 2006.173.14:40:44.30#ibcon#about to write, iclass 7, count 2 2006.173.14:40:44.30#ibcon#wrote, iclass 7, count 2 2006.173.14:40:44.30#ibcon#about to read 3, iclass 7, count 2 2006.173.14:40:44.33#ibcon#read 3, iclass 7, count 2 2006.173.14:40:44.33#ibcon#about to read 4, iclass 7, count 2 2006.173.14:40:44.33#ibcon#read 4, iclass 7, count 2 2006.173.14:40:44.33#ibcon#about to read 5, iclass 7, count 2 2006.173.14:40:44.33#ibcon#read 5, iclass 7, count 2 2006.173.14:40:44.33#ibcon#about to read 6, iclass 7, count 2 2006.173.14:40:44.33#ibcon#read 6, iclass 7, count 2 2006.173.14:40:44.33#ibcon#end of sib2, iclass 7, count 2 2006.173.14:40:44.33#ibcon#*after write, iclass 7, count 2 2006.173.14:40:44.33#ibcon#*before return 0, iclass 7, count 2 2006.173.14:40:44.33#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.14:40:44.33#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.173.14:40:44.33#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.173.14:40:44.33#ibcon#ireg 7 cls_cnt 0 2006.173.14:40:44.33#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.14:40:44.45#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.14:40:44.45#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.14:40:44.45#ibcon#enter wrdev, iclass 7, count 0 2006.173.14:40:44.45#ibcon#first serial, iclass 7, count 0 2006.173.14:40:44.45#ibcon#enter sib2, iclass 7, count 0 2006.173.14:40:44.45#ibcon#flushed, iclass 7, count 0 2006.173.14:40:44.45#ibcon#about to write, iclass 7, count 0 2006.173.14:40:44.45#ibcon#wrote, iclass 7, count 0 2006.173.14:40:44.45#ibcon#about to read 3, iclass 7, count 0 2006.173.14:40:44.47#ibcon#read 3, iclass 7, count 0 2006.173.14:40:44.47#ibcon#about to read 4, iclass 7, count 0 2006.173.14:40:44.47#ibcon#read 4, iclass 7, count 0 2006.173.14:40:44.47#ibcon#about to read 5, iclass 7, count 0 2006.173.14:40:44.47#ibcon#read 5, iclass 7, count 0 2006.173.14:40:44.47#ibcon#about to read 6, iclass 7, count 0 2006.173.14:40:44.47#ibcon#read 6, iclass 7, count 0 2006.173.14:40:44.47#ibcon#end of sib2, iclass 7, count 0 2006.173.14:40:44.47#ibcon#*mode == 0, iclass 7, count 0 2006.173.14:40:44.47#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.14:40:44.47#ibcon#[27=USB\r\n] 2006.173.14:40:44.47#ibcon#*before write, iclass 7, count 0 2006.173.14:40:44.47#ibcon#enter sib2, iclass 7, count 0 2006.173.14:40:44.47#ibcon#flushed, iclass 7, count 0 2006.173.14:40:44.47#ibcon#about to write, iclass 7, count 0 2006.173.14:40:44.47#ibcon#wrote, iclass 7, count 0 2006.173.14:40:44.47#ibcon#about to read 3, iclass 7, count 0 2006.173.14:40:44.50#ibcon#read 3, iclass 7, count 0 2006.173.14:40:44.50#ibcon#about to read 4, iclass 7, count 0 2006.173.14:40:44.50#ibcon#read 4, iclass 7, count 0 2006.173.14:40:44.50#ibcon#about to read 5, iclass 7, count 0 2006.173.14:40:44.50#ibcon#read 5, iclass 7, count 0 2006.173.14:40:44.50#ibcon#about to read 6, iclass 7, count 0 2006.173.14:40:44.50#ibcon#read 6, iclass 7, count 0 2006.173.14:40:44.50#ibcon#end of sib2, iclass 7, count 0 2006.173.14:40:44.50#ibcon#*after write, iclass 7, count 0 2006.173.14:40:44.50#ibcon#*before return 0, iclass 7, count 0 2006.173.14:40:44.50#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.14:40:44.50#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.173.14:40:44.50#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.14:40:44.50#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.14:40:44.50$vck44/vblo=3,649.99 2006.173.14:40:44.50#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.14:40:44.50#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.14:40:44.50#ibcon#ireg 17 cls_cnt 0 2006.173.14:40:44.50#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.14:40:44.50#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.14:40:44.50#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.14:40:44.50#ibcon#enter wrdev, iclass 11, count 0 2006.173.14:40:44.50#ibcon#first serial, iclass 11, count 0 2006.173.14:40:44.50#ibcon#enter sib2, iclass 11, count 0 2006.173.14:40:44.50#ibcon#flushed, iclass 11, count 0 2006.173.14:40:44.50#ibcon#about to write, iclass 11, count 0 2006.173.14:40:44.50#ibcon#wrote, iclass 11, count 0 2006.173.14:40:44.50#ibcon#about to read 3, iclass 11, count 0 2006.173.14:40:44.52#ibcon#read 3, iclass 11, count 0 2006.173.14:40:44.52#ibcon#about to read 4, iclass 11, count 0 2006.173.14:40:44.52#ibcon#read 4, iclass 11, count 0 2006.173.14:40:44.52#ibcon#about to read 5, iclass 11, count 0 2006.173.14:40:44.52#ibcon#read 5, iclass 11, count 0 2006.173.14:40:44.52#ibcon#about to read 6, iclass 11, count 0 2006.173.14:40:44.52#ibcon#read 6, iclass 11, count 0 2006.173.14:40:44.52#ibcon#end of sib2, iclass 11, count 0 2006.173.14:40:44.52#ibcon#*mode == 0, iclass 11, count 0 2006.173.14:40:44.52#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.14:40:44.52#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.14:40:44.52#ibcon#*before write, iclass 11, count 0 2006.173.14:40:44.52#ibcon#enter sib2, iclass 11, count 0 2006.173.14:40:44.52#ibcon#flushed, iclass 11, count 0 2006.173.14:40:44.52#ibcon#about to write, iclass 11, count 0 2006.173.14:40:44.52#ibcon#wrote, iclass 11, count 0 2006.173.14:40:44.52#ibcon#about to read 3, iclass 11, count 0 2006.173.14:40:44.56#ibcon#read 3, iclass 11, count 0 2006.173.14:40:44.56#ibcon#about to read 4, iclass 11, count 0 2006.173.14:40:44.56#ibcon#read 4, iclass 11, count 0 2006.173.14:40:44.56#ibcon#about to read 5, iclass 11, count 0 2006.173.14:40:44.56#ibcon#read 5, iclass 11, count 0 2006.173.14:40:44.56#ibcon#about to read 6, iclass 11, count 0 2006.173.14:40:44.56#ibcon#read 6, iclass 11, count 0 2006.173.14:40:44.56#ibcon#end of sib2, iclass 11, count 0 2006.173.14:40:44.56#ibcon#*after write, iclass 11, count 0 2006.173.14:40:44.56#ibcon#*before return 0, iclass 11, count 0 2006.173.14:40:44.56#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.14:40:44.56#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.14:40:44.56#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.14:40:44.56#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.14:40:44.56$vck44/vb=3,4 2006.173.14:40:44.56#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.173.14:40:44.56#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.173.14:40:44.56#ibcon#ireg 11 cls_cnt 2 2006.173.14:40:44.56#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.14:40:44.62#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.14:40:44.62#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.14:40:44.62#ibcon#enter wrdev, iclass 13, count 2 2006.173.14:40:44.62#ibcon#first serial, iclass 13, count 2 2006.173.14:40:44.62#ibcon#enter sib2, iclass 13, count 2 2006.173.14:40:44.62#ibcon#flushed, iclass 13, count 2 2006.173.14:40:44.62#ibcon#about to write, iclass 13, count 2 2006.173.14:40:44.62#ibcon#wrote, iclass 13, count 2 2006.173.14:40:44.62#ibcon#about to read 3, iclass 13, count 2 2006.173.14:40:44.64#ibcon#read 3, iclass 13, count 2 2006.173.14:40:44.64#ibcon#about to read 4, iclass 13, count 2 2006.173.14:40:44.64#ibcon#read 4, iclass 13, count 2 2006.173.14:40:44.64#ibcon#about to read 5, iclass 13, count 2 2006.173.14:40:44.64#ibcon#read 5, iclass 13, count 2 2006.173.14:40:44.64#ibcon#about to read 6, iclass 13, count 2 2006.173.14:40:44.64#ibcon#read 6, iclass 13, count 2 2006.173.14:40:44.64#ibcon#end of sib2, iclass 13, count 2 2006.173.14:40:44.64#ibcon#*mode == 0, iclass 13, count 2 2006.173.14:40:44.64#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.173.14:40:44.64#ibcon#[27=AT03-04\r\n] 2006.173.14:40:44.64#ibcon#*before write, iclass 13, count 2 2006.173.14:40:44.64#ibcon#enter sib2, iclass 13, count 2 2006.173.14:40:44.64#ibcon#flushed, iclass 13, count 2 2006.173.14:40:44.64#ibcon#about to write, iclass 13, count 2 2006.173.14:40:44.64#ibcon#wrote, iclass 13, count 2 2006.173.14:40:44.64#ibcon#about to read 3, iclass 13, count 2 2006.173.14:40:44.67#ibcon#read 3, iclass 13, count 2 2006.173.14:40:44.67#ibcon#about to read 4, iclass 13, count 2 2006.173.14:40:44.67#ibcon#read 4, iclass 13, count 2 2006.173.14:40:44.67#ibcon#about to read 5, iclass 13, count 2 2006.173.14:40:44.67#ibcon#read 5, iclass 13, count 2 2006.173.14:40:44.67#ibcon#about to read 6, iclass 13, count 2 2006.173.14:40:44.67#ibcon#read 6, iclass 13, count 2 2006.173.14:40:44.67#ibcon#end of sib2, iclass 13, count 2 2006.173.14:40:44.67#ibcon#*after write, iclass 13, count 2 2006.173.14:40:44.67#ibcon#*before return 0, iclass 13, count 2 2006.173.14:40:44.67#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.14:40:44.67#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.173.14:40:44.67#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.173.14:40:44.67#ibcon#ireg 7 cls_cnt 0 2006.173.14:40:44.67#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.14:40:44.79#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.14:40:44.79#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.14:40:44.79#ibcon#enter wrdev, iclass 13, count 0 2006.173.14:40:44.79#ibcon#first serial, iclass 13, count 0 2006.173.14:40:44.79#ibcon#enter sib2, iclass 13, count 0 2006.173.14:40:44.79#ibcon#flushed, iclass 13, count 0 2006.173.14:40:44.79#ibcon#about to write, iclass 13, count 0 2006.173.14:40:44.79#ibcon#wrote, iclass 13, count 0 2006.173.14:40:44.79#ibcon#about to read 3, iclass 13, count 0 2006.173.14:40:44.81#ibcon#read 3, iclass 13, count 0 2006.173.14:40:44.81#ibcon#about to read 4, iclass 13, count 0 2006.173.14:40:44.81#ibcon#read 4, iclass 13, count 0 2006.173.14:40:44.81#ibcon#about to read 5, iclass 13, count 0 2006.173.14:40:44.81#ibcon#read 5, iclass 13, count 0 2006.173.14:40:44.81#ibcon#about to read 6, iclass 13, count 0 2006.173.14:40:44.81#ibcon#read 6, iclass 13, count 0 2006.173.14:40:44.81#ibcon#end of sib2, iclass 13, count 0 2006.173.14:40:44.81#ibcon#*mode == 0, iclass 13, count 0 2006.173.14:40:44.81#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.14:40:44.81#ibcon#[27=USB\r\n] 2006.173.14:40:44.81#ibcon#*before write, iclass 13, count 0 2006.173.14:40:44.81#ibcon#enter sib2, iclass 13, count 0 2006.173.14:40:44.81#ibcon#flushed, iclass 13, count 0 2006.173.14:40:44.81#ibcon#about to write, iclass 13, count 0 2006.173.14:40:44.81#ibcon#wrote, iclass 13, count 0 2006.173.14:40:44.81#ibcon#about to read 3, iclass 13, count 0 2006.173.14:40:44.84#ibcon#read 3, iclass 13, count 0 2006.173.14:40:44.84#ibcon#about to read 4, iclass 13, count 0 2006.173.14:40:44.84#ibcon#read 4, iclass 13, count 0 2006.173.14:40:44.84#ibcon#about to read 5, iclass 13, count 0 2006.173.14:40:44.84#ibcon#read 5, iclass 13, count 0 2006.173.14:40:44.84#ibcon#about to read 6, iclass 13, count 0 2006.173.14:40:44.84#ibcon#read 6, iclass 13, count 0 2006.173.14:40:44.84#ibcon#end of sib2, iclass 13, count 0 2006.173.14:40:44.84#ibcon#*after write, iclass 13, count 0 2006.173.14:40:44.84#ibcon#*before return 0, iclass 13, count 0 2006.173.14:40:44.84#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.14:40:44.84#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.173.14:40:44.84#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.14:40:44.84#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.14:40:44.84$vck44/vblo=4,679.99 2006.173.14:40:44.84#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.14:40:44.84#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.14:40:44.84#ibcon#ireg 17 cls_cnt 0 2006.173.14:40:44.84#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.14:40:44.84#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.14:40:44.84#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.14:40:44.84#ibcon#enter wrdev, iclass 15, count 0 2006.173.14:40:44.84#ibcon#first serial, iclass 15, count 0 2006.173.14:40:44.84#ibcon#enter sib2, iclass 15, count 0 2006.173.14:40:44.84#ibcon#flushed, iclass 15, count 0 2006.173.14:40:44.84#ibcon#about to write, iclass 15, count 0 2006.173.14:40:44.84#ibcon#wrote, iclass 15, count 0 2006.173.14:40:44.84#ibcon#about to read 3, iclass 15, count 0 2006.173.14:40:44.86#ibcon#read 3, iclass 15, count 0 2006.173.14:40:44.86#ibcon#about to read 4, iclass 15, count 0 2006.173.14:40:44.86#ibcon#read 4, iclass 15, count 0 2006.173.14:40:44.86#ibcon#about to read 5, iclass 15, count 0 2006.173.14:40:44.86#ibcon#read 5, iclass 15, count 0 2006.173.14:40:44.86#ibcon#about to read 6, iclass 15, count 0 2006.173.14:40:44.86#ibcon#read 6, iclass 15, count 0 2006.173.14:40:44.86#ibcon#end of sib2, iclass 15, count 0 2006.173.14:40:44.86#ibcon#*mode == 0, iclass 15, count 0 2006.173.14:40:44.86#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.14:40:44.86#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.14:40:44.86#ibcon#*before write, iclass 15, count 0 2006.173.14:40:44.86#ibcon#enter sib2, iclass 15, count 0 2006.173.14:40:44.86#ibcon#flushed, iclass 15, count 0 2006.173.14:40:44.86#ibcon#about to write, iclass 15, count 0 2006.173.14:40:44.86#ibcon#wrote, iclass 15, count 0 2006.173.14:40:44.86#ibcon#about to read 3, iclass 15, count 0 2006.173.14:40:44.90#ibcon#read 3, iclass 15, count 0 2006.173.14:40:44.90#ibcon#about to read 4, iclass 15, count 0 2006.173.14:40:44.90#ibcon#read 4, iclass 15, count 0 2006.173.14:40:44.90#ibcon#about to read 5, iclass 15, count 0 2006.173.14:40:44.90#ibcon#read 5, iclass 15, count 0 2006.173.14:40:44.90#ibcon#about to read 6, iclass 15, count 0 2006.173.14:40:44.90#ibcon#read 6, iclass 15, count 0 2006.173.14:40:44.90#ibcon#end of sib2, iclass 15, count 0 2006.173.14:40:44.90#ibcon#*after write, iclass 15, count 0 2006.173.14:40:44.90#ibcon#*before return 0, iclass 15, count 0 2006.173.14:40:44.90#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.14:40:44.90#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.14:40:44.90#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.14:40:44.90#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.14:40:44.90$vck44/vb=4,4 2006.173.14:40:44.90#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.14:40:44.90#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.14:40:44.90#ibcon#ireg 11 cls_cnt 2 2006.173.14:40:44.90#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.14:40:44.96#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.14:40:44.96#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.14:40:44.96#ibcon#enter wrdev, iclass 17, count 2 2006.173.14:40:44.96#ibcon#first serial, iclass 17, count 2 2006.173.14:40:44.96#ibcon#enter sib2, iclass 17, count 2 2006.173.14:40:44.96#ibcon#flushed, iclass 17, count 2 2006.173.14:40:44.96#ibcon#about to write, iclass 17, count 2 2006.173.14:40:44.96#ibcon#wrote, iclass 17, count 2 2006.173.14:40:44.96#ibcon#about to read 3, iclass 17, count 2 2006.173.14:40:44.98#ibcon#read 3, iclass 17, count 2 2006.173.14:40:44.98#ibcon#about to read 4, iclass 17, count 2 2006.173.14:40:44.98#ibcon#read 4, iclass 17, count 2 2006.173.14:40:44.98#ibcon#about to read 5, iclass 17, count 2 2006.173.14:40:44.98#ibcon#read 5, iclass 17, count 2 2006.173.14:40:44.98#ibcon#about to read 6, iclass 17, count 2 2006.173.14:40:44.98#ibcon#read 6, iclass 17, count 2 2006.173.14:40:44.98#ibcon#end of sib2, iclass 17, count 2 2006.173.14:40:44.98#ibcon#*mode == 0, iclass 17, count 2 2006.173.14:40:44.98#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.14:40:44.98#ibcon#[27=AT04-04\r\n] 2006.173.14:40:44.98#ibcon#*before write, iclass 17, count 2 2006.173.14:40:44.98#ibcon#enter sib2, iclass 17, count 2 2006.173.14:40:44.98#ibcon#flushed, iclass 17, count 2 2006.173.14:40:44.98#ibcon#about to write, iclass 17, count 2 2006.173.14:40:44.98#ibcon#wrote, iclass 17, count 2 2006.173.14:40:44.98#ibcon#about to read 3, iclass 17, count 2 2006.173.14:40:45.01#ibcon#read 3, iclass 17, count 2 2006.173.14:40:45.01#ibcon#about to read 4, iclass 17, count 2 2006.173.14:40:45.01#ibcon#read 4, iclass 17, count 2 2006.173.14:40:45.01#ibcon#about to read 5, iclass 17, count 2 2006.173.14:40:45.01#ibcon#read 5, iclass 17, count 2 2006.173.14:40:45.01#ibcon#about to read 6, iclass 17, count 2 2006.173.14:40:45.01#ibcon#read 6, iclass 17, count 2 2006.173.14:40:45.01#ibcon#end of sib2, iclass 17, count 2 2006.173.14:40:45.01#ibcon#*after write, iclass 17, count 2 2006.173.14:40:45.01#ibcon#*before return 0, iclass 17, count 2 2006.173.14:40:45.01#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.14:40:45.01#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.14:40:45.01#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.14:40:45.01#ibcon#ireg 7 cls_cnt 0 2006.173.14:40:45.01#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.14:40:45.13#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.14:40:45.13#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.14:40:45.13#ibcon#enter wrdev, iclass 17, count 0 2006.173.14:40:45.13#ibcon#first serial, iclass 17, count 0 2006.173.14:40:45.13#ibcon#enter sib2, iclass 17, count 0 2006.173.14:40:45.13#ibcon#flushed, iclass 17, count 0 2006.173.14:40:45.13#ibcon#about to write, iclass 17, count 0 2006.173.14:40:45.13#ibcon#wrote, iclass 17, count 0 2006.173.14:40:45.13#ibcon#about to read 3, iclass 17, count 0 2006.173.14:40:45.15#ibcon#read 3, iclass 17, count 0 2006.173.14:40:45.15#ibcon#about to read 4, iclass 17, count 0 2006.173.14:40:45.15#ibcon#read 4, iclass 17, count 0 2006.173.14:40:45.15#ibcon#about to read 5, iclass 17, count 0 2006.173.14:40:45.15#ibcon#read 5, iclass 17, count 0 2006.173.14:40:45.15#ibcon#about to read 6, iclass 17, count 0 2006.173.14:40:45.15#ibcon#read 6, iclass 17, count 0 2006.173.14:40:45.15#ibcon#end of sib2, iclass 17, count 0 2006.173.14:40:45.15#ibcon#*mode == 0, iclass 17, count 0 2006.173.14:40:45.15#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.14:40:45.15#ibcon#[27=USB\r\n] 2006.173.14:40:45.15#ibcon#*before write, iclass 17, count 0 2006.173.14:40:45.15#ibcon#enter sib2, iclass 17, count 0 2006.173.14:40:45.15#ibcon#flushed, iclass 17, count 0 2006.173.14:40:45.15#ibcon#about to write, iclass 17, count 0 2006.173.14:40:45.15#ibcon#wrote, iclass 17, count 0 2006.173.14:40:45.15#ibcon#about to read 3, iclass 17, count 0 2006.173.14:40:45.18#ibcon#read 3, iclass 17, count 0 2006.173.14:40:45.18#ibcon#about to read 4, iclass 17, count 0 2006.173.14:40:45.18#ibcon#read 4, iclass 17, count 0 2006.173.14:40:45.18#ibcon#about to read 5, iclass 17, count 0 2006.173.14:40:45.18#ibcon#read 5, iclass 17, count 0 2006.173.14:40:45.18#ibcon#about to read 6, iclass 17, count 0 2006.173.14:40:45.18#ibcon#read 6, iclass 17, count 0 2006.173.14:40:45.18#ibcon#end of sib2, iclass 17, count 0 2006.173.14:40:45.18#ibcon#*after write, iclass 17, count 0 2006.173.14:40:45.18#ibcon#*before return 0, iclass 17, count 0 2006.173.14:40:45.18#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.14:40:45.18#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.14:40:45.18#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.14:40:45.18#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.14:40:45.18$vck44/vblo=5,709.99 2006.173.14:40:45.18#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.14:40:45.18#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.14:40:45.18#ibcon#ireg 17 cls_cnt 0 2006.173.14:40:45.18#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.14:40:45.18#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.14:40:45.18#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.14:40:45.18#ibcon#enter wrdev, iclass 19, count 0 2006.173.14:40:45.18#ibcon#first serial, iclass 19, count 0 2006.173.14:40:45.18#ibcon#enter sib2, iclass 19, count 0 2006.173.14:40:45.18#ibcon#flushed, iclass 19, count 0 2006.173.14:40:45.18#ibcon#about to write, iclass 19, count 0 2006.173.14:40:45.18#ibcon#wrote, iclass 19, count 0 2006.173.14:40:45.18#ibcon#about to read 3, iclass 19, count 0 2006.173.14:40:45.20#ibcon#read 3, iclass 19, count 0 2006.173.14:40:45.20#ibcon#about to read 4, iclass 19, count 0 2006.173.14:40:45.20#ibcon#read 4, iclass 19, count 0 2006.173.14:40:45.20#ibcon#about to read 5, iclass 19, count 0 2006.173.14:40:45.20#ibcon#read 5, iclass 19, count 0 2006.173.14:40:45.20#ibcon#about to read 6, iclass 19, count 0 2006.173.14:40:45.20#ibcon#read 6, iclass 19, count 0 2006.173.14:40:45.20#ibcon#end of sib2, iclass 19, count 0 2006.173.14:40:45.20#ibcon#*mode == 0, iclass 19, count 0 2006.173.14:40:45.20#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.14:40:45.20#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.14:40:45.20#ibcon#*before write, iclass 19, count 0 2006.173.14:40:45.20#ibcon#enter sib2, iclass 19, count 0 2006.173.14:40:45.20#ibcon#flushed, iclass 19, count 0 2006.173.14:40:45.20#ibcon#about to write, iclass 19, count 0 2006.173.14:40:45.20#ibcon#wrote, iclass 19, count 0 2006.173.14:40:45.20#ibcon#about to read 3, iclass 19, count 0 2006.173.14:40:45.24#ibcon#read 3, iclass 19, count 0 2006.173.14:40:45.24#ibcon#about to read 4, iclass 19, count 0 2006.173.14:40:45.24#ibcon#read 4, iclass 19, count 0 2006.173.14:40:45.24#ibcon#about to read 5, iclass 19, count 0 2006.173.14:40:45.24#ibcon#read 5, iclass 19, count 0 2006.173.14:40:45.24#ibcon#about to read 6, iclass 19, count 0 2006.173.14:40:45.24#ibcon#read 6, iclass 19, count 0 2006.173.14:40:45.24#ibcon#end of sib2, iclass 19, count 0 2006.173.14:40:45.24#ibcon#*after write, iclass 19, count 0 2006.173.14:40:45.24#ibcon#*before return 0, iclass 19, count 0 2006.173.14:40:45.24#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.14:40:45.24#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.14:40:45.24#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.14:40:45.24#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.14:40:45.24$vck44/vb=5,4 2006.173.14:40:45.24#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.14:40:45.24#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.14:40:45.24#ibcon#ireg 11 cls_cnt 2 2006.173.14:40:45.24#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.14:40:45.30#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.14:40:45.30#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.14:40:45.30#ibcon#enter wrdev, iclass 21, count 2 2006.173.14:40:45.30#ibcon#first serial, iclass 21, count 2 2006.173.14:40:45.30#ibcon#enter sib2, iclass 21, count 2 2006.173.14:40:45.30#ibcon#flushed, iclass 21, count 2 2006.173.14:40:45.30#ibcon#about to write, iclass 21, count 2 2006.173.14:40:45.30#ibcon#wrote, iclass 21, count 2 2006.173.14:40:45.30#ibcon#about to read 3, iclass 21, count 2 2006.173.14:40:45.32#ibcon#read 3, iclass 21, count 2 2006.173.14:40:45.32#ibcon#about to read 4, iclass 21, count 2 2006.173.14:40:45.32#ibcon#read 4, iclass 21, count 2 2006.173.14:40:45.32#ibcon#about to read 5, iclass 21, count 2 2006.173.14:40:45.32#ibcon#read 5, iclass 21, count 2 2006.173.14:40:45.32#ibcon#about to read 6, iclass 21, count 2 2006.173.14:40:45.32#ibcon#read 6, iclass 21, count 2 2006.173.14:40:45.32#ibcon#end of sib2, iclass 21, count 2 2006.173.14:40:45.32#ibcon#*mode == 0, iclass 21, count 2 2006.173.14:40:45.32#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.14:40:45.32#ibcon#[27=AT05-04\r\n] 2006.173.14:40:45.32#ibcon#*before write, iclass 21, count 2 2006.173.14:40:45.32#ibcon#enter sib2, iclass 21, count 2 2006.173.14:40:45.32#ibcon#flushed, iclass 21, count 2 2006.173.14:40:45.32#ibcon#about to write, iclass 21, count 2 2006.173.14:40:45.32#ibcon#wrote, iclass 21, count 2 2006.173.14:40:45.32#ibcon#about to read 3, iclass 21, count 2 2006.173.14:40:45.35#ibcon#read 3, iclass 21, count 2 2006.173.14:40:45.35#ibcon#about to read 4, iclass 21, count 2 2006.173.14:40:45.35#ibcon#read 4, iclass 21, count 2 2006.173.14:40:45.35#ibcon#about to read 5, iclass 21, count 2 2006.173.14:40:45.35#ibcon#read 5, iclass 21, count 2 2006.173.14:40:45.35#ibcon#about to read 6, iclass 21, count 2 2006.173.14:40:45.35#ibcon#read 6, iclass 21, count 2 2006.173.14:40:45.35#ibcon#end of sib2, iclass 21, count 2 2006.173.14:40:45.35#ibcon#*after write, iclass 21, count 2 2006.173.14:40:45.35#ibcon#*before return 0, iclass 21, count 2 2006.173.14:40:45.35#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.14:40:45.35#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.14:40:45.35#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.14:40:45.35#ibcon#ireg 7 cls_cnt 0 2006.173.14:40:45.35#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.14:40:45.47#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.14:40:45.47#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.14:40:45.47#ibcon#enter wrdev, iclass 21, count 0 2006.173.14:40:45.47#ibcon#first serial, iclass 21, count 0 2006.173.14:40:45.47#ibcon#enter sib2, iclass 21, count 0 2006.173.14:40:45.47#ibcon#flushed, iclass 21, count 0 2006.173.14:40:45.47#ibcon#about to write, iclass 21, count 0 2006.173.14:40:45.47#ibcon#wrote, iclass 21, count 0 2006.173.14:40:45.47#ibcon#about to read 3, iclass 21, count 0 2006.173.14:40:45.49#ibcon#read 3, iclass 21, count 0 2006.173.14:40:45.49#ibcon#about to read 4, iclass 21, count 0 2006.173.14:40:45.49#ibcon#read 4, iclass 21, count 0 2006.173.14:40:45.49#ibcon#about to read 5, iclass 21, count 0 2006.173.14:40:45.49#ibcon#read 5, iclass 21, count 0 2006.173.14:40:45.49#ibcon#about to read 6, iclass 21, count 0 2006.173.14:40:45.49#ibcon#read 6, iclass 21, count 0 2006.173.14:40:45.49#ibcon#end of sib2, iclass 21, count 0 2006.173.14:40:45.49#ibcon#*mode == 0, iclass 21, count 0 2006.173.14:40:45.49#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.14:40:45.49#ibcon#[27=USB\r\n] 2006.173.14:40:45.49#ibcon#*before write, iclass 21, count 0 2006.173.14:40:45.49#ibcon#enter sib2, iclass 21, count 0 2006.173.14:40:45.49#ibcon#flushed, iclass 21, count 0 2006.173.14:40:45.49#ibcon#about to write, iclass 21, count 0 2006.173.14:40:45.49#ibcon#wrote, iclass 21, count 0 2006.173.14:40:45.49#ibcon#about to read 3, iclass 21, count 0 2006.173.14:40:45.52#ibcon#read 3, iclass 21, count 0 2006.173.14:40:45.52#ibcon#about to read 4, iclass 21, count 0 2006.173.14:40:45.52#ibcon#read 4, iclass 21, count 0 2006.173.14:40:45.52#ibcon#about to read 5, iclass 21, count 0 2006.173.14:40:45.52#ibcon#read 5, iclass 21, count 0 2006.173.14:40:45.52#ibcon#about to read 6, iclass 21, count 0 2006.173.14:40:45.52#ibcon#read 6, iclass 21, count 0 2006.173.14:40:45.52#ibcon#end of sib2, iclass 21, count 0 2006.173.14:40:45.52#ibcon#*after write, iclass 21, count 0 2006.173.14:40:45.52#ibcon#*before return 0, iclass 21, count 0 2006.173.14:40:45.52#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.14:40:45.52#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.14:40:45.52#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.14:40:45.52#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.14:40:45.52$vck44/vblo=6,719.99 2006.173.14:40:45.52#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.14:40:45.52#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.14:40:45.52#ibcon#ireg 17 cls_cnt 0 2006.173.14:40:45.52#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.14:40:45.52#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.14:40:45.52#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.14:40:45.52#ibcon#enter wrdev, iclass 23, count 0 2006.173.14:40:45.52#ibcon#first serial, iclass 23, count 0 2006.173.14:40:45.52#ibcon#enter sib2, iclass 23, count 0 2006.173.14:40:45.52#ibcon#flushed, iclass 23, count 0 2006.173.14:40:45.52#ibcon#about to write, iclass 23, count 0 2006.173.14:40:45.52#ibcon#wrote, iclass 23, count 0 2006.173.14:40:45.52#ibcon#about to read 3, iclass 23, count 0 2006.173.14:40:45.54#ibcon#read 3, iclass 23, count 0 2006.173.14:40:45.54#ibcon#about to read 4, iclass 23, count 0 2006.173.14:40:45.54#ibcon#read 4, iclass 23, count 0 2006.173.14:40:45.54#ibcon#about to read 5, iclass 23, count 0 2006.173.14:40:45.54#ibcon#read 5, iclass 23, count 0 2006.173.14:40:45.54#ibcon#about to read 6, iclass 23, count 0 2006.173.14:40:45.54#ibcon#read 6, iclass 23, count 0 2006.173.14:40:45.54#ibcon#end of sib2, iclass 23, count 0 2006.173.14:40:45.54#ibcon#*mode == 0, iclass 23, count 0 2006.173.14:40:45.54#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.14:40:45.54#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.14:40:45.54#ibcon#*before write, iclass 23, count 0 2006.173.14:40:45.54#ibcon#enter sib2, iclass 23, count 0 2006.173.14:40:45.54#ibcon#flushed, iclass 23, count 0 2006.173.14:40:45.54#ibcon#about to write, iclass 23, count 0 2006.173.14:40:45.54#ibcon#wrote, iclass 23, count 0 2006.173.14:40:45.54#ibcon#about to read 3, iclass 23, count 0 2006.173.14:40:45.58#ibcon#read 3, iclass 23, count 0 2006.173.14:40:45.58#ibcon#about to read 4, iclass 23, count 0 2006.173.14:40:45.58#ibcon#read 4, iclass 23, count 0 2006.173.14:40:45.58#ibcon#about to read 5, iclass 23, count 0 2006.173.14:40:45.58#ibcon#read 5, iclass 23, count 0 2006.173.14:40:45.58#ibcon#about to read 6, iclass 23, count 0 2006.173.14:40:45.58#ibcon#read 6, iclass 23, count 0 2006.173.14:40:45.58#ibcon#end of sib2, iclass 23, count 0 2006.173.14:40:45.58#ibcon#*after write, iclass 23, count 0 2006.173.14:40:45.58#ibcon#*before return 0, iclass 23, count 0 2006.173.14:40:45.58#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.14:40:45.58#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.14:40:45.58#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.14:40:45.58#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.14:40:45.58$vck44/vb=6,4 2006.173.14:40:45.58#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.14:40:45.58#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.14:40:45.58#ibcon#ireg 11 cls_cnt 2 2006.173.14:40:45.58#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.14:40:45.64#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.14:40:45.64#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.14:40:45.64#ibcon#enter wrdev, iclass 25, count 2 2006.173.14:40:45.64#ibcon#first serial, iclass 25, count 2 2006.173.14:40:45.64#ibcon#enter sib2, iclass 25, count 2 2006.173.14:40:45.64#ibcon#flushed, iclass 25, count 2 2006.173.14:40:45.64#ibcon#about to write, iclass 25, count 2 2006.173.14:40:45.64#ibcon#wrote, iclass 25, count 2 2006.173.14:40:45.64#ibcon#about to read 3, iclass 25, count 2 2006.173.14:40:45.66#ibcon#read 3, iclass 25, count 2 2006.173.14:40:45.66#ibcon#about to read 4, iclass 25, count 2 2006.173.14:40:45.66#ibcon#read 4, iclass 25, count 2 2006.173.14:40:45.66#ibcon#about to read 5, iclass 25, count 2 2006.173.14:40:45.66#ibcon#read 5, iclass 25, count 2 2006.173.14:40:45.66#ibcon#about to read 6, iclass 25, count 2 2006.173.14:40:45.66#ibcon#read 6, iclass 25, count 2 2006.173.14:40:45.66#ibcon#end of sib2, iclass 25, count 2 2006.173.14:40:45.66#ibcon#*mode == 0, iclass 25, count 2 2006.173.14:40:45.66#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.14:40:45.66#ibcon#[27=AT06-04\r\n] 2006.173.14:40:45.66#ibcon#*before write, iclass 25, count 2 2006.173.14:40:45.66#ibcon#enter sib2, iclass 25, count 2 2006.173.14:40:45.66#ibcon#flushed, iclass 25, count 2 2006.173.14:40:45.66#ibcon#about to write, iclass 25, count 2 2006.173.14:40:45.66#ibcon#wrote, iclass 25, count 2 2006.173.14:40:45.66#ibcon#about to read 3, iclass 25, count 2 2006.173.14:40:45.69#ibcon#read 3, iclass 25, count 2 2006.173.14:40:45.69#ibcon#about to read 4, iclass 25, count 2 2006.173.14:40:45.69#ibcon#read 4, iclass 25, count 2 2006.173.14:40:45.69#ibcon#about to read 5, iclass 25, count 2 2006.173.14:40:45.69#ibcon#read 5, iclass 25, count 2 2006.173.14:40:45.69#ibcon#about to read 6, iclass 25, count 2 2006.173.14:40:45.69#ibcon#read 6, iclass 25, count 2 2006.173.14:40:45.69#ibcon#end of sib2, iclass 25, count 2 2006.173.14:40:45.69#ibcon#*after write, iclass 25, count 2 2006.173.14:40:45.69#ibcon#*before return 0, iclass 25, count 2 2006.173.14:40:45.69#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.14:40:45.69#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.14:40:45.69#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.14:40:45.69#ibcon#ireg 7 cls_cnt 0 2006.173.14:40:45.69#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.14:40:45.81#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.14:40:45.81#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.14:40:45.81#ibcon#enter wrdev, iclass 25, count 0 2006.173.14:40:45.81#ibcon#first serial, iclass 25, count 0 2006.173.14:40:45.81#ibcon#enter sib2, iclass 25, count 0 2006.173.14:40:45.81#ibcon#flushed, iclass 25, count 0 2006.173.14:40:45.81#ibcon#about to write, iclass 25, count 0 2006.173.14:40:45.81#ibcon#wrote, iclass 25, count 0 2006.173.14:40:45.81#ibcon#about to read 3, iclass 25, count 0 2006.173.14:40:45.83#ibcon#read 3, iclass 25, count 0 2006.173.14:40:45.83#ibcon#about to read 4, iclass 25, count 0 2006.173.14:40:45.83#ibcon#read 4, iclass 25, count 0 2006.173.14:40:45.83#ibcon#about to read 5, iclass 25, count 0 2006.173.14:40:45.83#ibcon#read 5, iclass 25, count 0 2006.173.14:40:45.83#ibcon#about to read 6, iclass 25, count 0 2006.173.14:40:45.83#ibcon#read 6, iclass 25, count 0 2006.173.14:40:45.83#ibcon#end of sib2, iclass 25, count 0 2006.173.14:40:45.83#ibcon#*mode == 0, iclass 25, count 0 2006.173.14:40:45.83#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.14:40:45.83#ibcon#[27=USB\r\n] 2006.173.14:40:45.83#ibcon#*before write, iclass 25, count 0 2006.173.14:40:45.83#ibcon#enter sib2, iclass 25, count 0 2006.173.14:40:45.83#ibcon#flushed, iclass 25, count 0 2006.173.14:40:45.83#ibcon#about to write, iclass 25, count 0 2006.173.14:40:45.83#ibcon#wrote, iclass 25, count 0 2006.173.14:40:45.83#ibcon#about to read 3, iclass 25, count 0 2006.173.14:40:45.86#ibcon#read 3, iclass 25, count 0 2006.173.14:40:45.86#ibcon#about to read 4, iclass 25, count 0 2006.173.14:40:45.86#ibcon#read 4, iclass 25, count 0 2006.173.14:40:45.86#ibcon#about to read 5, iclass 25, count 0 2006.173.14:40:45.86#ibcon#read 5, iclass 25, count 0 2006.173.14:40:45.86#ibcon#about to read 6, iclass 25, count 0 2006.173.14:40:45.86#ibcon#read 6, iclass 25, count 0 2006.173.14:40:45.86#ibcon#end of sib2, iclass 25, count 0 2006.173.14:40:45.86#ibcon#*after write, iclass 25, count 0 2006.173.14:40:45.86#ibcon#*before return 0, iclass 25, count 0 2006.173.14:40:45.86#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.14:40:45.86#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.14:40:45.86#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.14:40:45.86#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.14:40:45.86$vck44/vblo=7,734.99 2006.173.14:40:45.86#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.14:40:45.86#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.14:40:45.86#ibcon#ireg 17 cls_cnt 0 2006.173.14:40:45.86#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.14:40:45.86#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.14:40:45.86#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.14:40:45.86#ibcon#enter wrdev, iclass 27, count 0 2006.173.14:40:45.86#ibcon#first serial, iclass 27, count 0 2006.173.14:40:45.86#ibcon#enter sib2, iclass 27, count 0 2006.173.14:40:45.86#ibcon#flushed, iclass 27, count 0 2006.173.14:40:45.86#ibcon#about to write, iclass 27, count 0 2006.173.14:40:45.86#ibcon#wrote, iclass 27, count 0 2006.173.14:40:45.86#ibcon#about to read 3, iclass 27, count 0 2006.173.14:40:45.88#ibcon#read 3, iclass 27, count 0 2006.173.14:40:45.88#ibcon#about to read 4, iclass 27, count 0 2006.173.14:40:45.88#ibcon#read 4, iclass 27, count 0 2006.173.14:40:45.88#ibcon#about to read 5, iclass 27, count 0 2006.173.14:40:45.88#ibcon#read 5, iclass 27, count 0 2006.173.14:40:45.88#ibcon#about to read 6, iclass 27, count 0 2006.173.14:40:45.88#ibcon#read 6, iclass 27, count 0 2006.173.14:40:45.88#ibcon#end of sib2, iclass 27, count 0 2006.173.14:40:45.88#ibcon#*mode == 0, iclass 27, count 0 2006.173.14:40:45.88#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.14:40:45.88#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.14:40:45.88#ibcon#*before write, iclass 27, count 0 2006.173.14:40:45.88#ibcon#enter sib2, iclass 27, count 0 2006.173.14:40:45.88#ibcon#flushed, iclass 27, count 0 2006.173.14:40:45.88#ibcon#about to write, iclass 27, count 0 2006.173.14:40:45.88#ibcon#wrote, iclass 27, count 0 2006.173.14:40:45.88#ibcon#about to read 3, iclass 27, count 0 2006.173.14:40:45.92#ibcon#read 3, iclass 27, count 0 2006.173.14:40:45.92#ibcon#about to read 4, iclass 27, count 0 2006.173.14:40:45.92#ibcon#read 4, iclass 27, count 0 2006.173.14:40:45.92#ibcon#about to read 5, iclass 27, count 0 2006.173.14:40:45.92#ibcon#read 5, iclass 27, count 0 2006.173.14:40:45.92#ibcon#about to read 6, iclass 27, count 0 2006.173.14:40:45.92#ibcon#read 6, iclass 27, count 0 2006.173.14:40:45.92#ibcon#end of sib2, iclass 27, count 0 2006.173.14:40:45.92#ibcon#*after write, iclass 27, count 0 2006.173.14:40:45.92#ibcon#*before return 0, iclass 27, count 0 2006.173.14:40:45.92#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.14:40:45.92#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.14:40:45.92#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.14:40:45.92#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.14:40:45.92$vck44/vb=7,4 2006.173.14:40:45.92#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.14:40:45.92#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.14:40:45.92#ibcon#ireg 11 cls_cnt 2 2006.173.14:40:45.92#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.14:40:45.98#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.14:40:45.98#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.14:40:45.98#ibcon#enter wrdev, iclass 29, count 2 2006.173.14:40:45.98#ibcon#first serial, iclass 29, count 2 2006.173.14:40:45.98#ibcon#enter sib2, iclass 29, count 2 2006.173.14:40:45.98#ibcon#flushed, iclass 29, count 2 2006.173.14:40:45.98#ibcon#about to write, iclass 29, count 2 2006.173.14:40:45.98#ibcon#wrote, iclass 29, count 2 2006.173.14:40:45.98#ibcon#about to read 3, iclass 29, count 2 2006.173.14:40:46.00#ibcon#read 3, iclass 29, count 2 2006.173.14:40:46.00#ibcon#about to read 4, iclass 29, count 2 2006.173.14:40:46.00#ibcon#read 4, iclass 29, count 2 2006.173.14:40:46.00#ibcon#about to read 5, iclass 29, count 2 2006.173.14:40:46.00#ibcon#read 5, iclass 29, count 2 2006.173.14:40:46.00#ibcon#about to read 6, iclass 29, count 2 2006.173.14:40:46.00#ibcon#read 6, iclass 29, count 2 2006.173.14:40:46.00#ibcon#end of sib2, iclass 29, count 2 2006.173.14:40:46.00#ibcon#*mode == 0, iclass 29, count 2 2006.173.14:40:46.00#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.14:40:46.00#ibcon#[27=AT07-04\r\n] 2006.173.14:40:46.00#ibcon#*before write, iclass 29, count 2 2006.173.14:40:46.00#ibcon#enter sib2, iclass 29, count 2 2006.173.14:40:46.00#ibcon#flushed, iclass 29, count 2 2006.173.14:40:46.00#ibcon#about to write, iclass 29, count 2 2006.173.14:40:46.00#ibcon#wrote, iclass 29, count 2 2006.173.14:40:46.00#ibcon#about to read 3, iclass 29, count 2 2006.173.14:40:46.03#ibcon#read 3, iclass 29, count 2 2006.173.14:40:46.03#ibcon#about to read 4, iclass 29, count 2 2006.173.14:40:46.03#ibcon#read 4, iclass 29, count 2 2006.173.14:40:46.03#ibcon#about to read 5, iclass 29, count 2 2006.173.14:40:46.03#ibcon#read 5, iclass 29, count 2 2006.173.14:40:46.03#ibcon#about to read 6, iclass 29, count 2 2006.173.14:40:46.03#ibcon#read 6, iclass 29, count 2 2006.173.14:40:46.03#ibcon#end of sib2, iclass 29, count 2 2006.173.14:40:46.03#ibcon#*after write, iclass 29, count 2 2006.173.14:40:46.03#ibcon#*before return 0, iclass 29, count 2 2006.173.14:40:46.03#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.14:40:46.03#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.14:40:46.03#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.14:40:46.03#ibcon#ireg 7 cls_cnt 0 2006.173.14:40:46.03#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.14:40:46.15#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.14:40:46.15#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.14:40:46.15#ibcon#enter wrdev, iclass 29, count 0 2006.173.14:40:46.15#ibcon#first serial, iclass 29, count 0 2006.173.14:40:46.15#ibcon#enter sib2, iclass 29, count 0 2006.173.14:40:46.15#ibcon#flushed, iclass 29, count 0 2006.173.14:40:46.15#ibcon#about to write, iclass 29, count 0 2006.173.14:40:46.15#ibcon#wrote, iclass 29, count 0 2006.173.14:40:46.15#ibcon#about to read 3, iclass 29, count 0 2006.173.14:40:46.17#ibcon#read 3, iclass 29, count 0 2006.173.14:40:46.17#ibcon#about to read 4, iclass 29, count 0 2006.173.14:40:46.17#ibcon#read 4, iclass 29, count 0 2006.173.14:40:46.17#ibcon#about to read 5, iclass 29, count 0 2006.173.14:40:46.17#ibcon#read 5, iclass 29, count 0 2006.173.14:40:46.17#ibcon#about to read 6, iclass 29, count 0 2006.173.14:40:46.17#ibcon#read 6, iclass 29, count 0 2006.173.14:40:46.17#ibcon#end of sib2, iclass 29, count 0 2006.173.14:40:46.17#ibcon#*mode == 0, iclass 29, count 0 2006.173.14:40:46.17#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.14:40:46.17#ibcon#[27=USB\r\n] 2006.173.14:40:46.17#ibcon#*before write, iclass 29, count 0 2006.173.14:40:46.17#ibcon#enter sib2, iclass 29, count 0 2006.173.14:40:46.17#ibcon#flushed, iclass 29, count 0 2006.173.14:40:46.17#ibcon#about to write, iclass 29, count 0 2006.173.14:40:46.17#ibcon#wrote, iclass 29, count 0 2006.173.14:40:46.17#ibcon#about to read 3, iclass 29, count 0 2006.173.14:40:46.20#ibcon#read 3, iclass 29, count 0 2006.173.14:40:46.20#ibcon#about to read 4, iclass 29, count 0 2006.173.14:40:46.20#ibcon#read 4, iclass 29, count 0 2006.173.14:40:46.20#ibcon#about to read 5, iclass 29, count 0 2006.173.14:40:46.20#ibcon#read 5, iclass 29, count 0 2006.173.14:40:46.20#ibcon#about to read 6, iclass 29, count 0 2006.173.14:40:46.20#ibcon#read 6, iclass 29, count 0 2006.173.14:40:46.20#ibcon#end of sib2, iclass 29, count 0 2006.173.14:40:46.20#ibcon#*after write, iclass 29, count 0 2006.173.14:40:46.20#ibcon#*before return 0, iclass 29, count 0 2006.173.14:40:46.20#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.14:40:46.20#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.14:40:46.20#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.14:40:46.20#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.14:40:46.20$vck44/vblo=8,744.99 2006.173.14:40:46.20#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.14:40:46.20#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.14:40:46.20#ibcon#ireg 17 cls_cnt 0 2006.173.14:40:46.20#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.14:40:46.20#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.14:40:46.20#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.14:40:46.20#ibcon#enter wrdev, iclass 31, count 0 2006.173.14:40:46.20#ibcon#first serial, iclass 31, count 0 2006.173.14:40:46.20#ibcon#enter sib2, iclass 31, count 0 2006.173.14:40:46.20#ibcon#flushed, iclass 31, count 0 2006.173.14:40:46.20#ibcon#about to write, iclass 31, count 0 2006.173.14:40:46.20#ibcon#wrote, iclass 31, count 0 2006.173.14:40:46.20#ibcon#about to read 3, iclass 31, count 0 2006.173.14:40:46.22#ibcon#read 3, iclass 31, count 0 2006.173.14:40:46.22#ibcon#about to read 4, iclass 31, count 0 2006.173.14:40:46.22#ibcon#read 4, iclass 31, count 0 2006.173.14:40:46.22#ibcon#about to read 5, iclass 31, count 0 2006.173.14:40:46.22#ibcon#read 5, iclass 31, count 0 2006.173.14:40:46.22#ibcon#about to read 6, iclass 31, count 0 2006.173.14:40:46.22#ibcon#read 6, iclass 31, count 0 2006.173.14:40:46.22#ibcon#end of sib2, iclass 31, count 0 2006.173.14:40:46.22#ibcon#*mode == 0, iclass 31, count 0 2006.173.14:40:46.22#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.14:40:46.22#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.14:40:46.22#ibcon#*before write, iclass 31, count 0 2006.173.14:40:46.22#ibcon#enter sib2, iclass 31, count 0 2006.173.14:40:46.22#ibcon#flushed, iclass 31, count 0 2006.173.14:40:46.22#ibcon#about to write, iclass 31, count 0 2006.173.14:40:46.22#ibcon#wrote, iclass 31, count 0 2006.173.14:40:46.22#ibcon#about to read 3, iclass 31, count 0 2006.173.14:40:46.26#ibcon#read 3, iclass 31, count 0 2006.173.14:40:46.26#ibcon#about to read 4, iclass 31, count 0 2006.173.14:40:46.26#ibcon#read 4, iclass 31, count 0 2006.173.14:40:46.26#ibcon#about to read 5, iclass 31, count 0 2006.173.14:40:46.26#ibcon#read 5, iclass 31, count 0 2006.173.14:40:46.26#ibcon#about to read 6, iclass 31, count 0 2006.173.14:40:46.26#ibcon#read 6, iclass 31, count 0 2006.173.14:40:46.26#ibcon#end of sib2, iclass 31, count 0 2006.173.14:40:46.26#ibcon#*after write, iclass 31, count 0 2006.173.14:40:46.26#ibcon#*before return 0, iclass 31, count 0 2006.173.14:40:46.26#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.14:40:46.26#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.14:40:46.26#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.14:40:46.26#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.14:40:46.26$vck44/vb=8,4 2006.173.14:40:46.26#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.173.14:40:46.26#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.173.14:40:46.26#ibcon#ireg 11 cls_cnt 2 2006.173.14:40:46.26#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.14:40:46.32#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.14:40:46.32#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.14:40:46.32#ibcon#enter wrdev, iclass 33, count 2 2006.173.14:40:46.32#ibcon#first serial, iclass 33, count 2 2006.173.14:40:46.32#ibcon#enter sib2, iclass 33, count 2 2006.173.14:40:46.32#ibcon#flushed, iclass 33, count 2 2006.173.14:40:46.32#ibcon#about to write, iclass 33, count 2 2006.173.14:40:46.32#ibcon#wrote, iclass 33, count 2 2006.173.14:40:46.32#ibcon#about to read 3, iclass 33, count 2 2006.173.14:40:46.34#ibcon#read 3, iclass 33, count 2 2006.173.14:40:46.34#ibcon#about to read 4, iclass 33, count 2 2006.173.14:40:46.34#ibcon#read 4, iclass 33, count 2 2006.173.14:40:46.34#ibcon#about to read 5, iclass 33, count 2 2006.173.14:40:46.34#ibcon#read 5, iclass 33, count 2 2006.173.14:40:46.34#ibcon#about to read 6, iclass 33, count 2 2006.173.14:40:46.34#ibcon#read 6, iclass 33, count 2 2006.173.14:40:46.34#ibcon#end of sib2, iclass 33, count 2 2006.173.14:40:46.34#ibcon#*mode == 0, iclass 33, count 2 2006.173.14:40:46.34#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.173.14:40:46.34#ibcon#[27=AT08-04\r\n] 2006.173.14:40:46.34#ibcon#*before write, iclass 33, count 2 2006.173.14:40:46.34#ibcon#enter sib2, iclass 33, count 2 2006.173.14:40:46.34#ibcon#flushed, iclass 33, count 2 2006.173.14:40:46.34#ibcon#about to write, iclass 33, count 2 2006.173.14:40:46.34#ibcon#wrote, iclass 33, count 2 2006.173.14:40:46.34#ibcon#about to read 3, iclass 33, count 2 2006.173.14:40:46.37#ibcon#read 3, iclass 33, count 2 2006.173.14:40:46.37#ibcon#about to read 4, iclass 33, count 2 2006.173.14:40:46.37#ibcon#read 4, iclass 33, count 2 2006.173.14:40:46.37#ibcon#about to read 5, iclass 33, count 2 2006.173.14:40:46.37#ibcon#read 5, iclass 33, count 2 2006.173.14:40:46.37#ibcon#about to read 6, iclass 33, count 2 2006.173.14:40:46.37#ibcon#read 6, iclass 33, count 2 2006.173.14:40:46.37#ibcon#end of sib2, iclass 33, count 2 2006.173.14:40:46.37#ibcon#*after write, iclass 33, count 2 2006.173.14:40:46.37#ibcon#*before return 0, iclass 33, count 2 2006.173.14:40:46.37#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.14:40:46.37#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.173.14:40:46.37#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.173.14:40:46.37#ibcon#ireg 7 cls_cnt 0 2006.173.14:40:46.37#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.14:40:46.49#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.14:40:46.49#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.14:40:46.49#ibcon#enter wrdev, iclass 33, count 0 2006.173.14:40:46.49#ibcon#first serial, iclass 33, count 0 2006.173.14:40:46.49#ibcon#enter sib2, iclass 33, count 0 2006.173.14:40:46.49#ibcon#flushed, iclass 33, count 0 2006.173.14:40:46.49#ibcon#about to write, iclass 33, count 0 2006.173.14:40:46.49#ibcon#wrote, iclass 33, count 0 2006.173.14:40:46.49#ibcon#about to read 3, iclass 33, count 0 2006.173.14:40:46.51#ibcon#read 3, iclass 33, count 0 2006.173.14:40:46.51#ibcon#about to read 4, iclass 33, count 0 2006.173.14:40:46.51#ibcon#read 4, iclass 33, count 0 2006.173.14:40:46.51#ibcon#about to read 5, iclass 33, count 0 2006.173.14:40:46.51#ibcon#read 5, iclass 33, count 0 2006.173.14:40:46.51#ibcon#about to read 6, iclass 33, count 0 2006.173.14:40:46.51#ibcon#read 6, iclass 33, count 0 2006.173.14:40:46.51#ibcon#end of sib2, iclass 33, count 0 2006.173.14:40:46.51#ibcon#*mode == 0, iclass 33, count 0 2006.173.14:40:46.51#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.14:40:46.51#ibcon#[27=USB\r\n] 2006.173.14:40:46.51#ibcon#*before write, iclass 33, count 0 2006.173.14:40:46.51#ibcon#enter sib2, iclass 33, count 0 2006.173.14:40:46.51#ibcon#flushed, iclass 33, count 0 2006.173.14:40:46.51#ibcon#about to write, iclass 33, count 0 2006.173.14:40:46.51#ibcon#wrote, iclass 33, count 0 2006.173.14:40:46.51#ibcon#about to read 3, iclass 33, count 0 2006.173.14:40:46.54#ibcon#read 3, iclass 33, count 0 2006.173.14:40:46.54#ibcon#about to read 4, iclass 33, count 0 2006.173.14:40:46.54#ibcon#read 4, iclass 33, count 0 2006.173.14:40:46.54#ibcon#about to read 5, iclass 33, count 0 2006.173.14:40:46.54#ibcon#read 5, iclass 33, count 0 2006.173.14:40:46.54#ibcon#about to read 6, iclass 33, count 0 2006.173.14:40:46.54#ibcon#read 6, iclass 33, count 0 2006.173.14:40:46.54#ibcon#end of sib2, iclass 33, count 0 2006.173.14:40:46.54#ibcon#*after write, iclass 33, count 0 2006.173.14:40:46.54#ibcon#*before return 0, iclass 33, count 0 2006.173.14:40:46.54#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.14:40:46.54#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.173.14:40:46.54#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.14:40:46.54#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.14:40:46.54$vck44/vabw=wide 2006.173.14:40:46.54#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.14:40:46.54#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.14:40:46.54#ibcon#ireg 8 cls_cnt 0 2006.173.14:40:46.54#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.14:40:46.54#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.14:40:46.54#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.14:40:46.54#ibcon#enter wrdev, iclass 35, count 0 2006.173.14:40:46.54#ibcon#first serial, iclass 35, count 0 2006.173.14:40:46.54#ibcon#enter sib2, iclass 35, count 0 2006.173.14:40:46.54#ibcon#flushed, iclass 35, count 0 2006.173.14:40:46.54#ibcon#about to write, iclass 35, count 0 2006.173.14:40:46.54#ibcon#wrote, iclass 35, count 0 2006.173.14:40:46.54#ibcon#about to read 3, iclass 35, count 0 2006.173.14:40:46.56#ibcon#read 3, iclass 35, count 0 2006.173.14:40:46.56#ibcon#about to read 4, iclass 35, count 0 2006.173.14:40:46.56#ibcon#read 4, iclass 35, count 0 2006.173.14:40:46.56#ibcon#about to read 5, iclass 35, count 0 2006.173.14:40:46.56#ibcon#read 5, iclass 35, count 0 2006.173.14:40:46.56#ibcon#about to read 6, iclass 35, count 0 2006.173.14:40:46.56#ibcon#read 6, iclass 35, count 0 2006.173.14:40:46.56#ibcon#end of sib2, iclass 35, count 0 2006.173.14:40:46.56#ibcon#*mode == 0, iclass 35, count 0 2006.173.14:40:46.56#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.14:40:46.56#ibcon#[25=BW32\r\n] 2006.173.14:40:46.56#ibcon#*before write, iclass 35, count 0 2006.173.14:40:46.56#ibcon#enter sib2, iclass 35, count 0 2006.173.14:40:46.56#ibcon#flushed, iclass 35, count 0 2006.173.14:40:46.56#ibcon#about to write, iclass 35, count 0 2006.173.14:40:46.56#ibcon#wrote, iclass 35, count 0 2006.173.14:40:46.56#ibcon#about to read 3, iclass 35, count 0 2006.173.14:40:46.59#ibcon#read 3, iclass 35, count 0 2006.173.14:40:46.59#ibcon#about to read 4, iclass 35, count 0 2006.173.14:40:46.59#ibcon#read 4, iclass 35, count 0 2006.173.14:40:46.59#ibcon#about to read 5, iclass 35, count 0 2006.173.14:40:46.59#ibcon#read 5, iclass 35, count 0 2006.173.14:40:46.59#ibcon#about to read 6, iclass 35, count 0 2006.173.14:40:46.59#ibcon#read 6, iclass 35, count 0 2006.173.14:40:46.59#ibcon#end of sib2, iclass 35, count 0 2006.173.14:40:46.59#ibcon#*after write, iclass 35, count 0 2006.173.14:40:46.59#ibcon#*before return 0, iclass 35, count 0 2006.173.14:40:46.59#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.14:40:46.59#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.14:40:46.59#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.14:40:46.59#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.14:40:46.59$vck44/vbbw=wide 2006.173.14:40:46.59#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.14:40:46.59#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.14:40:46.59#ibcon#ireg 8 cls_cnt 0 2006.173.14:40:46.59#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.14:40:46.66#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.14:40:46.66#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.14:40:46.66#ibcon#enter wrdev, iclass 37, count 0 2006.173.14:40:46.66#ibcon#first serial, iclass 37, count 0 2006.173.14:40:46.66#ibcon#enter sib2, iclass 37, count 0 2006.173.14:40:46.66#ibcon#flushed, iclass 37, count 0 2006.173.14:40:46.66#ibcon#about to write, iclass 37, count 0 2006.173.14:40:46.66#ibcon#wrote, iclass 37, count 0 2006.173.14:40:46.66#ibcon#about to read 3, iclass 37, count 0 2006.173.14:40:46.68#ibcon#read 3, iclass 37, count 0 2006.173.14:40:46.68#ibcon#about to read 4, iclass 37, count 0 2006.173.14:40:46.68#ibcon#read 4, iclass 37, count 0 2006.173.14:40:46.68#ibcon#about to read 5, iclass 37, count 0 2006.173.14:40:46.68#ibcon#read 5, iclass 37, count 0 2006.173.14:40:46.68#ibcon#about to read 6, iclass 37, count 0 2006.173.14:40:46.68#ibcon#read 6, iclass 37, count 0 2006.173.14:40:46.68#ibcon#end of sib2, iclass 37, count 0 2006.173.14:40:46.68#ibcon#*mode == 0, iclass 37, count 0 2006.173.14:40:46.68#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.14:40:46.68#ibcon#[27=BW32\r\n] 2006.173.14:40:46.68#ibcon#*before write, iclass 37, count 0 2006.173.14:40:46.68#ibcon#enter sib2, iclass 37, count 0 2006.173.14:40:46.68#ibcon#flushed, iclass 37, count 0 2006.173.14:40:46.68#ibcon#about to write, iclass 37, count 0 2006.173.14:40:46.68#ibcon#wrote, iclass 37, count 0 2006.173.14:40:46.68#ibcon#about to read 3, iclass 37, count 0 2006.173.14:40:46.71#ibcon#read 3, iclass 37, count 0 2006.173.14:40:46.71#ibcon#about to read 4, iclass 37, count 0 2006.173.14:40:46.71#ibcon#read 4, iclass 37, count 0 2006.173.14:40:46.71#ibcon#about to read 5, iclass 37, count 0 2006.173.14:40:46.71#ibcon#read 5, iclass 37, count 0 2006.173.14:40:46.71#ibcon#about to read 6, iclass 37, count 0 2006.173.14:40:46.71#ibcon#read 6, iclass 37, count 0 2006.173.14:40:46.71#ibcon#end of sib2, iclass 37, count 0 2006.173.14:40:46.71#ibcon#*after write, iclass 37, count 0 2006.173.14:40:46.71#ibcon#*before return 0, iclass 37, count 0 2006.173.14:40:46.71#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.14:40:46.71#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.14:40:46.71#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.14:40:46.71#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.14:40:46.71$setupk4/ifdk4 2006.173.14:40:46.71$ifdk4/lo= 2006.173.14:40:46.71$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.14:40:46.71$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.14:40:46.71$ifdk4/patch= 2006.173.14:40:46.71$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.14:40:46.71$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.14:40:46.71$setupk4/!*+20s 2006.173.14:40:53.92#abcon#<5=/14 1.4 4.0 21.141001004.0\r\n> 2006.173.14:40:53.94#abcon#{5=INTERFACE CLEAR} 2006.173.14:40:54.00#abcon#[5=S1D000X0/0*\r\n] 2006.173.14:40:58.14#trakl#Source acquired 2006.173.14:41:00.14#flagr#flagr/antenna,acquired 2006.173.14:41:01.22$setupk4/"tpicd 2006.173.14:41:01.22$setupk4/echo=off 2006.173.14:41:01.22$setupk4/xlog=off 2006.173.14:41:01.22:!2006.173.14:47:16 2006.173.14:47:16.02:preob 2006.173.14:47:17.14/onsource/TRACKING 2006.173.14:47:17.14:!2006.173.14:47:26 2006.173.14:47:26.01:"tape 2006.173.14:47:26.02:"st=record 2006.173.14:47:26.02:data_valid=on 2006.173.14:47:26.02:midob 2006.173.14:47:27.14/onsource/TRACKING 2006.173.14:47:27.14/wx/20.87,1003.7,100 2006.173.14:47:27.29/cable/+6.5061E-03 2006.173.14:47:28.37/va/01,07,usb,yes,42,45 2006.173.14:47:28.38/va/02,06,usb,yes,42,42 2006.173.14:47:28.38/va/03,05,usb,yes,53,55 2006.173.14:47:28.38/va/04,06,usb,yes,43,45 2006.173.14:47:28.38/va/05,04,usb,yes,34,34 2006.173.14:47:28.38/va/06,03,usb,yes,47,47 2006.173.14:47:28.38/va/07,04,usb,yes,38,39 2006.173.14:47:28.38/va/08,04,usb,yes,33,39 2006.173.14:47:28.61/valo/01,524.99,yes,locked 2006.173.14:47:28.61/valo/02,534.99,yes,locked 2006.173.14:47:28.61/valo/03,564.99,yes,locked 2006.173.14:47:28.61/valo/04,624.99,yes,locked 2006.173.14:47:28.61/valo/05,734.99,yes,locked 2006.173.14:47:28.61/valo/06,814.99,yes,locked 2006.173.14:47:28.61/valo/07,864.99,yes,locked 2006.173.14:47:28.61/valo/08,884.99,yes,locked 2006.173.14:47:29.69/vb/01,04,usb,yes,30,28 2006.173.14:47:29.70/vb/02,04,usb,yes,32,32 2006.173.14:47:29.70/vb/03,04,usb,yes,29,32 2006.173.14:47:29.70/vb/04,04,usb,yes,34,32 2006.173.14:47:29.70/vb/05,04,usb,yes,26,29 2006.173.14:47:29.70/vb/06,04,usb,yes,31,27 2006.173.14:47:29.70/vb/07,04,usb,yes,30,30 2006.173.14:47:29.70/vb/08,04,usb,yes,28,31 2006.173.14:47:29.93/vblo/01,629.99,yes,locked 2006.173.14:47:29.93/vblo/02,634.99,yes,locked 2006.173.14:47:29.93/vblo/03,649.99,yes,locked 2006.173.14:47:29.93/vblo/04,679.99,yes,locked 2006.173.14:47:29.93/vblo/05,709.99,yes,locked 2006.173.14:47:29.93/vblo/06,719.99,yes,locked 2006.173.14:47:29.93/vblo/07,734.99,yes,locked 2006.173.14:47:29.93/vblo/08,744.99,yes,locked 2006.173.14:47:30.07/vabw/8 2006.173.14:47:30.22/vbbw/8 2006.173.14:47:30.32/xfe/off,on,14.7 2006.173.14:47:30.70/ifatt/23,28,28,28 2006.173.14:47:31.07/fmout-gps/S +3.88E-07 2006.173.14:47:31.11:!2006.173.14:51:26 2006.173.14:51:26.01:data_valid=off 2006.173.14:51:26.02:"et 2006.173.14:51:26.02:!+3s 2006.173.14:51:29.04:"tape 2006.173.14:51:29.04:postob 2006.173.14:51:29.20/cable/+6.5069E-03 2006.173.14:51:29.20/wx/20.85,1003.6,100 2006.173.14:51:29.26/fmout-gps/S +3.88E-07 2006.173.14:51:29.26:scan_name=173-1455,jd0606,80 2006.173.14:51:29.27:source=2136+141,213901.31,142336.0,2000.0,cw 2006.173.14:51:30.14#flagr#flagr/antenna,new-source 2006.173.14:51:30.15:checkk5 2006.173.14:51:30.57/chk_autoobs//k5ts1/ autoobs is running! 2006.173.14:51:30.98/chk_autoobs//k5ts2/ autoobs is running! 2006.173.14:51:31.39/chk_autoobs//k5ts3/ autoobs is running! 2006.173.14:51:31.79/chk_autoobs//k5ts4/ autoobs is running! 2006.173.14:51:32.19/chk_obsdata//k5ts1/T1731447??a.dat file size is correct (nominal:960MB, actual:960MB). 2006.173.14:51:32.59/chk_obsdata//k5ts2/T1731447??b.dat file size is correct (nominal:960MB, actual:960MB). 2006.173.14:51:32.97/chk_obsdata//k5ts3/T1731447??c.dat file size is correct (nominal:960MB, actual:960MB). 2006.173.14:51:33.37/chk_obsdata//k5ts4/T1731447??d.dat file size is correct (nominal:960MB, actual:960MB). 2006.173.14:51:34.10/k5log//k5ts1_log_newline 2006.173.14:51:34.81/k5log//k5ts2_log_newline 2006.173.14:51:35.51/k5log//k5ts3_log_newline 2006.173.14:51:36.22/k5log//k5ts4_log_newline 2006.173.14:51:36.24/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.14:51:36.24:setupk4=1 2006.173.14:51:36.24$setupk4/echo=on 2006.173.14:51:36.24$setupk4/pcalon 2006.173.14:51:36.25$pcalon/"no phase cal control is implemented here 2006.173.14:51:36.25$setupk4/"tpicd=stop 2006.173.14:51:36.25$setupk4/"rec=synch_on 2006.173.14:51:36.25$setupk4/"rec_mode=128 2006.173.14:51:36.25$setupk4/!* 2006.173.14:51:36.25$setupk4/recpk4 2006.173.14:51:36.25$recpk4/recpatch= 2006.173.14:51:36.25$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.14:51:36.25$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.14:51:36.25$setupk4/vck44 2006.173.14:51:36.25$vck44/valo=1,524.99 2006.173.14:51:36.25#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.14:51:36.25#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.14:51:36.25#ibcon#ireg 17 cls_cnt 0 2006.173.14:51:36.25#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.14:51:36.25#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.14:51:36.25#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.14:51:36.25#ibcon#enter wrdev, iclass 10, count 0 2006.173.14:51:36.25#ibcon#first serial, iclass 10, count 0 2006.173.14:51:36.25#ibcon#enter sib2, iclass 10, count 0 2006.173.14:51:36.25#ibcon#flushed, iclass 10, count 0 2006.173.14:51:36.25#ibcon#about to write, iclass 10, count 0 2006.173.14:51:36.25#ibcon#wrote, iclass 10, count 0 2006.173.14:51:36.25#ibcon#about to read 3, iclass 10, count 0 2006.173.14:51:36.26#ibcon#read 3, iclass 10, count 0 2006.173.14:51:36.26#ibcon#about to read 4, iclass 10, count 0 2006.173.14:51:36.26#ibcon#read 4, iclass 10, count 0 2006.173.14:51:36.26#ibcon#about to read 5, iclass 10, count 0 2006.173.14:51:36.26#ibcon#read 5, iclass 10, count 0 2006.173.14:51:36.26#ibcon#about to read 6, iclass 10, count 0 2006.173.14:51:36.26#ibcon#read 6, iclass 10, count 0 2006.173.14:51:36.26#ibcon#end of sib2, iclass 10, count 0 2006.173.14:51:36.26#ibcon#*mode == 0, iclass 10, count 0 2006.173.14:51:36.26#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.14:51:36.26#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.14:51:36.26#ibcon#*before write, iclass 10, count 0 2006.173.14:51:36.26#ibcon#enter sib2, iclass 10, count 0 2006.173.14:51:36.26#ibcon#flushed, iclass 10, count 0 2006.173.14:51:36.26#ibcon#about to write, iclass 10, count 0 2006.173.14:51:36.26#ibcon#wrote, iclass 10, count 0 2006.173.14:51:36.26#ibcon#about to read 3, iclass 10, count 0 2006.173.14:51:36.31#ibcon#read 3, iclass 10, count 0 2006.173.14:51:36.31#ibcon#about to read 4, iclass 10, count 0 2006.173.14:51:36.31#ibcon#read 4, iclass 10, count 0 2006.173.14:51:36.31#ibcon#about to read 5, iclass 10, count 0 2006.173.14:51:36.31#ibcon#read 5, iclass 10, count 0 2006.173.14:51:36.31#ibcon#about to read 6, iclass 10, count 0 2006.173.14:51:36.31#ibcon#read 6, iclass 10, count 0 2006.173.14:51:36.31#ibcon#end of sib2, iclass 10, count 0 2006.173.14:51:36.31#ibcon#*after write, iclass 10, count 0 2006.173.14:51:36.31#ibcon#*before return 0, iclass 10, count 0 2006.173.14:51:36.31#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.14:51:36.31#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.14:51:36.31#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.14:51:36.31#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.14:51:36.31$vck44/va=1,7 2006.173.14:51:36.31#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.14:51:36.31#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.14:51:36.31#ibcon#ireg 11 cls_cnt 2 2006.173.14:51:36.31#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.14:51:36.31#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.14:51:36.31#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.14:51:36.31#ibcon#enter wrdev, iclass 12, count 2 2006.173.14:51:36.31#ibcon#first serial, iclass 12, count 2 2006.173.14:51:36.31#ibcon#enter sib2, iclass 12, count 2 2006.173.14:51:36.31#ibcon#flushed, iclass 12, count 2 2006.173.14:51:36.31#ibcon#about to write, iclass 12, count 2 2006.173.14:51:36.31#ibcon#wrote, iclass 12, count 2 2006.173.14:51:36.31#ibcon#about to read 3, iclass 12, count 2 2006.173.14:51:36.33#ibcon#read 3, iclass 12, count 2 2006.173.14:51:36.33#ibcon#about to read 4, iclass 12, count 2 2006.173.14:51:36.33#ibcon#read 4, iclass 12, count 2 2006.173.14:51:36.33#ibcon#about to read 5, iclass 12, count 2 2006.173.14:51:36.33#ibcon#read 5, iclass 12, count 2 2006.173.14:51:36.33#ibcon#about to read 6, iclass 12, count 2 2006.173.14:51:36.33#ibcon#read 6, iclass 12, count 2 2006.173.14:51:36.33#ibcon#end of sib2, iclass 12, count 2 2006.173.14:51:36.33#ibcon#*mode == 0, iclass 12, count 2 2006.173.14:51:36.33#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.14:51:36.33#ibcon#[25=AT01-07\r\n] 2006.173.14:51:36.33#ibcon#*before write, iclass 12, count 2 2006.173.14:51:36.33#ibcon#enter sib2, iclass 12, count 2 2006.173.14:51:36.33#ibcon#flushed, iclass 12, count 2 2006.173.14:51:36.33#ibcon#about to write, iclass 12, count 2 2006.173.14:51:36.33#ibcon#wrote, iclass 12, count 2 2006.173.14:51:36.33#ibcon#about to read 3, iclass 12, count 2 2006.173.14:51:36.36#ibcon#read 3, iclass 12, count 2 2006.173.14:51:36.36#ibcon#about to read 4, iclass 12, count 2 2006.173.14:51:36.36#ibcon#read 4, iclass 12, count 2 2006.173.14:51:36.36#ibcon#about to read 5, iclass 12, count 2 2006.173.14:51:36.36#ibcon#read 5, iclass 12, count 2 2006.173.14:51:36.36#ibcon#about to read 6, iclass 12, count 2 2006.173.14:51:36.36#ibcon#read 6, iclass 12, count 2 2006.173.14:51:36.36#ibcon#end of sib2, iclass 12, count 2 2006.173.14:51:36.36#ibcon#*after write, iclass 12, count 2 2006.173.14:51:36.36#ibcon#*before return 0, iclass 12, count 2 2006.173.14:51:36.36#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.14:51:36.36#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.14:51:36.36#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.14:51:36.36#ibcon#ireg 7 cls_cnt 0 2006.173.14:51:36.36#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.14:51:36.48#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.14:51:36.48#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.14:51:36.48#ibcon#enter wrdev, iclass 12, count 0 2006.173.14:51:36.48#ibcon#first serial, iclass 12, count 0 2006.173.14:51:36.48#ibcon#enter sib2, iclass 12, count 0 2006.173.14:51:36.48#ibcon#flushed, iclass 12, count 0 2006.173.14:51:36.48#ibcon#about to write, iclass 12, count 0 2006.173.14:51:36.48#ibcon#wrote, iclass 12, count 0 2006.173.14:51:36.48#ibcon#about to read 3, iclass 12, count 0 2006.173.14:51:36.50#ibcon#read 3, iclass 12, count 0 2006.173.14:51:36.50#ibcon#about to read 4, iclass 12, count 0 2006.173.14:51:36.50#ibcon#read 4, iclass 12, count 0 2006.173.14:51:36.50#ibcon#about to read 5, iclass 12, count 0 2006.173.14:51:36.50#ibcon#read 5, iclass 12, count 0 2006.173.14:51:36.50#ibcon#about to read 6, iclass 12, count 0 2006.173.14:51:36.50#ibcon#read 6, iclass 12, count 0 2006.173.14:51:36.50#ibcon#end of sib2, iclass 12, count 0 2006.173.14:51:36.50#ibcon#*mode == 0, iclass 12, count 0 2006.173.14:51:36.50#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.14:51:36.50#ibcon#[25=USB\r\n] 2006.173.14:51:36.50#ibcon#*before write, iclass 12, count 0 2006.173.14:51:36.50#ibcon#enter sib2, iclass 12, count 0 2006.173.14:51:36.50#ibcon#flushed, iclass 12, count 0 2006.173.14:51:36.50#ibcon#about to write, iclass 12, count 0 2006.173.14:51:36.50#ibcon#wrote, iclass 12, count 0 2006.173.14:51:36.50#ibcon#about to read 3, iclass 12, count 0 2006.173.14:51:36.53#ibcon#read 3, iclass 12, count 0 2006.173.14:51:36.53#ibcon#about to read 4, iclass 12, count 0 2006.173.14:51:36.53#ibcon#read 4, iclass 12, count 0 2006.173.14:51:36.53#ibcon#about to read 5, iclass 12, count 0 2006.173.14:51:36.53#ibcon#read 5, iclass 12, count 0 2006.173.14:51:36.53#ibcon#about to read 6, iclass 12, count 0 2006.173.14:51:36.53#ibcon#read 6, iclass 12, count 0 2006.173.14:51:36.53#ibcon#end of sib2, iclass 12, count 0 2006.173.14:51:36.53#ibcon#*after write, iclass 12, count 0 2006.173.14:51:36.53#ibcon#*before return 0, iclass 12, count 0 2006.173.14:51:36.53#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.14:51:36.53#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.14:51:36.53#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.14:51:36.53#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.14:51:36.53$vck44/valo=2,534.99 2006.173.14:51:36.53#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.14:51:36.53#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.14:51:36.53#ibcon#ireg 17 cls_cnt 0 2006.173.14:51:36.53#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.14:51:36.53#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.14:51:36.53#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.14:51:36.53#ibcon#enter wrdev, iclass 14, count 0 2006.173.14:51:36.53#ibcon#first serial, iclass 14, count 0 2006.173.14:51:36.53#ibcon#enter sib2, iclass 14, count 0 2006.173.14:51:36.53#ibcon#flushed, iclass 14, count 0 2006.173.14:51:36.53#ibcon#about to write, iclass 14, count 0 2006.173.14:51:36.53#ibcon#wrote, iclass 14, count 0 2006.173.14:51:36.53#ibcon#about to read 3, iclass 14, count 0 2006.173.14:51:36.55#ibcon#read 3, iclass 14, count 0 2006.173.14:51:36.55#ibcon#about to read 4, iclass 14, count 0 2006.173.14:51:36.55#ibcon#read 4, iclass 14, count 0 2006.173.14:51:36.55#ibcon#about to read 5, iclass 14, count 0 2006.173.14:51:36.55#ibcon#read 5, iclass 14, count 0 2006.173.14:51:36.55#ibcon#about to read 6, iclass 14, count 0 2006.173.14:51:36.55#ibcon#read 6, iclass 14, count 0 2006.173.14:51:36.55#ibcon#end of sib2, iclass 14, count 0 2006.173.14:51:36.55#ibcon#*mode == 0, iclass 14, count 0 2006.173.14:51:36.55#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.14:51:36.55#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.14:51:36.55#ibcon#*before write, iclass 14, count 0 2006.173.14:51:36.55#ibcon#enter sib2, iclass 14, count 0 2006.173.14:51:36.55#ibcon#flushed, iclass 14, count 0 2006.173.14:51:36.55#ibcon#about to write, iclass 14, count 0 2006.173.14:51:36.55#ibcon#wrote, iclass 14, count 0 2006.173.14:51:36.55#ibcon#about to read 3, iclass 14, count 0 2006.173.14:51:36.59#ibcon#read 3, iclass 14, count 0 2006.173.14:51:36.59#ibcon#about to read 4, iclass 14, count 0 2006.173.14:51:36.59#ibcon#read 4, iclass 14, count 0 2006.173.14:51:36.59#ibcon#about to read 5, iclass 14, count 0 2006.173.14:51:36.59#ibcon#read 5, iclass 14, count 0 2006.173.14:51:36.59#ibcon#about to read 6, iclass 14, count 0 2006.173.14:51:36.59#ibcon#read 6, iclass 14, count 0 2006.173.14:51:36.59#ibcon#end of sib2, iclass 14, count 0 2006.173.14:51:36.59#ibcon#*after write, iclass 14, count 0 2006.173.14:51:36.59#ibcon#*before return 0, iclass 14, count 0 2006.173.14:51:36.59#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.14:51:36.59#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.14:51:36.59#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.14:51:36.59#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.14:51:36.59$vck44/va=2,6 2006.173.14:51:36.59#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.14:51:36.59#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.14:51:36.59#ibcon#ireg 11 cls_cnt 2 2006.173.14:51:36.59#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.14:51:36.65#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.14:51:36.65#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.14:51:36.65#ibcon#enter wrdev, iclass 16, count 2 2006.173.14:51:36.65#ibcon#first serial, iclass 16, count 2 2006.173.14:51:36.65#ibcon#enter sib2, iclass 16, count 2 2006.173.14:51:36.65#ibcon#flushed, iclass 16, count 2 2006.173.14:51:36.65#ibcon#about to write, iclass 16, count 2 2006.173.14:51:36.65#ibcon#wrote, iclass 16, count 2 2006.173.14:51:36.65#ibcon#about to read 3, iclass 16, count 2 2006.173.14:51:36.67#ibcon#read 3, iclass 16, count 2 2006.173.14:51:36.67#ibcon#about to read 4, iclass 16, count 2 2006.173.14:51:36.67#ibcon#read 4, iclass 16, count 2 2006.173.14:51:36.67#ibcon#about to read 5, iclass 16, count 2 2006.173.14:51:36.67#ibcon#read 5, iclass 16, count 2 2006.173.14:51:36.67#ibcon#about to read 6, iclass 16, count 2 2006.173.14:51:36.67#ibcon#read 6, iclass 16, count 2 2006.173.14:51:36.67#ibcon#end of sib2, iclass 16, count 2 2006.173.14:51:36.67#ibcon#*mode == 0, iclass 16, count 2 2006.173.14:51:36.67#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.14:51:36.67#ibcon#[25=AT02-06\r\n] 2006.173.14:51:36.67#ibcon#*before write, iclass 16, count 2 2006.173.14:51:36.67#ibcon#enter sib2, iclass 16, count 2 2006.173.14:51:36.67#ibcon#flushed, iclass 16, count 2 2006.173.14:51:36.67#ibcon#about to write, iclass 16, count 2 2006.173.14:51:36.67#ibcon#wrote, iclass 16, count 2 2006.173.14:51:36.67#ibcon#about to read 3, iclass 16, count 2 2006.173.14:51:36.70#ibcon#read 3, iclass 16, count 2 2006.173.14:51:36.70#ibcon#about to read 4, iclass 16, count 2 2006.173.14:51:36.70#ibcon#read 4, iclass 16, count 2 2006.173.14:51:36.70#ibcon#about to read 5, iclass 16, count 2 2006.173.14:51:36.70#ibcon#read 5, iclass 16, count 2 2006.173.14:51:36.70#ibcon#about to read 6, iclass 16, count 2 2006.173.14:51:36.70#ibcon#read 6, iclass 16, count 2 2006.173.14:51:36.70#ibcon#end of sib2, iclass 16, count 2 2006.173.14:51:36.70#ibcon#*after write, iclass 16, count 2 2006.173.14:51:36.70#ibcon#*before return 0, iclass 16, count 2 2006.173.14:51:36.70#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.14:51:36.70#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.14:51:36.70#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.14:51:36.70#ibcon#ireg 7 cls_cnt 0 2006.173.14:51:36.70#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.14:51:36.82#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.14:51:36.82#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.14:51:36.82#ibcon#enter wrdev, iclass 16, count 0 2006.173.14:51:36.82#ibcon#first serial, iclass 16, count 0 2006.173.14:51:36.82#ibcon#enter sib2, iclass 16, count 0 2006.173.14:51:36.82#ibcon#flushed, iclass 16, count 0 2006.173.14:51:36.82#ibcon#about to write, iclass 16, count 0 2006.173.14:51:36.82#ibcon#wrote, iclass 16, count 0 2006.173.14:51:36.82#ibcon#about to read 3, iclass 16, count 0 2006.173.14:51:36.84#ibcon#read 3, iclass 16, count 0 2006.173.14:51:36.84#ibcon#about to read 4, iclass 16, count 0 2006.173.14:51:36.84#ibcon#read 4, iclass 16, count 0 2006.173.14:51:36.84#ibcon#about to read 5, iclass 16, count 0 2006.173.14:51:36.84#ibcon#read 5, iclass 16, count 0 2006.173.14:51:36.84#ibcon#about to read 6, iclass 16, count 0 2006.173.14:51:36.84#ibcon#read 6, iclass 16, count 0 2006.173.14:51:36.84#ibcon#end of sib2, iclass 16, count 0 2006.173.14:51:36.84#ibcon#*mode == 0, iclass 16, count 0 2006.173.14:51:36.84#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.14:51:36.84#ibcon#[25=USB\r\n] 2006.173.14:51:36.84#ibcon#*before write, iclass 16, count 0 2006.173.14:51:36.84#ibcon#enter sib2, iclass 16, count 0 2006.173.14:51:36.84#ibcon#flushed, iclass 16, count 0 2006.173.14:51:36.84#ibcon#about to write, iclass 16, count 0 2006.173.14:51:36.84#ibcon#wrote, iclass 16, count 0 2006.173.14:51:36.84#ibcon#about to read 3, iclass 16, count 0 2006.173.14:51:36.87#ibcon#read 3, iclass 16, count 0 2006.173.14:51:36.87#ibcon#about to read 4, iclass 16, count 0 2006.173.14:51:36.87#ibcon#read 4, iclass 16, count 0 2006.173.14:51:36.87#ibcon#about to read 5, iclass 16, count 0 2006.173.14:51:36.87#ibcon#read 5, iclass 16, count 0 2006.173.14:51:36.87#ibcon#about to read 6, iclass 16, count 0 2006.173.14:51:36.87#ibcon#read 6, iclass 16, count 0 2006.173.14:51:36.87#ibcon#end of sib2, iclass 16, count 0 2006.173.14:51:36.87#ibcon#*after write, iclass 16, count 0 2006.173.14:51:36.87#ibcon#*before return 0, iclass 16, count 0 2006.173.14:51:36.87#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.14:51:36.87#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.14:51:36.87#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.14:51:36.87#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.14:51:36.87$vck44/valo=3,564.99 2006.173.14:51:36.87#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.14:51:36.87#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.14:51:36.87#ibcon#ireg 17 cls_cnt 0 2006.173.14:51:36.87#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.14:51:36.87#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.14:51:36.87#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.14:51:36.87#ibcon#enter wrdev, iclass 18, count 0 2006.173.14:51:36.87#ibcon#first serial, iclass 18, count 0 2006.173.14:51:36.87#ibcon#enter sib2, iclass 18, count 0 2006.173.14:51:36.87#ibcon#flushed, iclass 18, count 0 2006.173.14:51:36.87#ibcon#about to write, iclass 18, count 0 2006.173.14:51:36.87#ibcon#wrote, iclass 18, count 0 2006.173.14:51:36.87#ibcon#about to read 3, iclass 18, count 0 2006.173.14:51:36.89#ibcon#read 3, iclass 18, count 0 2006.173.14:51:36.89#ibcon#about to read 4, iclass 18, count 0 2006.173.14:51:36.89#ibcon#read 4, iclass 18, count 0 2006.173.14:51:36.89#ibcon#about to read 5, iclass 18, count 0 2006.173.14:51:36.89#ibcon#read 5, iclass 18, count 0 2006.173.14:51:36.89#ibcon#about to read 6, iclass 18, count 0 2006.173.14:51:36.89#ibcon#read 6, iclass 18, count 0 2006.173.14:51:36.89#ibcon#end of sib2, iclass 18, count 0 2006.173.14:51:36.89#ibcon#*mode == 0, iclass 18, count 0 2006.173.14:51:36.89#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.14:51:36.89#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.14:51:36.89#ibcon#*before write, iclass 18, count 0 2006.173.14:51:36.89#ibcon#enter sib2, iclass 18, count 0 2006.173.14:51:36.89#ibcon#flushed, iclass 18, count 0 2006.173.14:51:36.89#ibcon#about to write, iclass 18, count 0 2006.173.14:51:36.89#ibcon#wrote, iclass 18, count 0 2006.173.14:51:36.89#ibcon#about to read 3, iclass 18, count 0 2006.173.14:51:36.93#ibcon#read 3, iclass 18, count 0 2006.173.14:51:36.93#ibcon#about to read 4, iclass 18, count 0 2006.173.14:51:36.93#ibcon#read 4, iclass 18, count 0 2006.173.14:51:36.93#ibcon#about to read 5, iclass 18, count 0 2006.173.14:51:36.93#ibcon#read 5, iclass 18, count 0 2006.173.14:51:36.93#ibcon#about to read 6, iclass 18, count 0 2006.173.14:51:36.93#ibcon#read 6, iclass 18, count 0 2006.173.14:51:36.93#ibcon#end of sib2, iclass 18, count 0 2006.173.14:51:36.93#ibcon#*after write, iclass 18, count 0 2006.173.14:51:36.93#ibcon#*before return 0, iclass 18, count 0 2006.173.14:51:36.93#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.14:51:36.93#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.14:51:36.93#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.14:51:36.93#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.14:51:36.93$vck44/va=3,5 2006.173.14:51:36.93#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.14:51:36.93#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.14:51:36.93#ibcon#ireg 11 cls_cnt 2 2006.173.14:51:36.93#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.14:51:37.00#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.14:51:37.00#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.14:51:37.00#ibcon#enter wrdev, iclass 20, count 2 2006.173.14:51:37.00#ibcon#first serial, iclass 20, count 2 2006.173.14:51:37.00#ibcon#enter sib2, iclass 20, count 2 2006.173.14:51:37.00#ibcon#flushed, iclass 20, count 2 2006.173.14:51:37.00#ibcon#about to write, iclass 20, count 2 2006.173.14:51:37.00#ibcon#wrote, iclass 20, count 2 2006.173.14:51:37.00#ibcon#about to read 3, iclass 20, count 2 2006.173.14:51:37.02#ibcon#read 3, iclass 20, count 2 2006.173.14:51:37.02#ibcon#about to read 4, iclass 20, count 2 2006.173.14:51:37.02#ibcon#read 4, iclass 20, count 2 2006.173.14:51:37.02#ibcon#about to read 5, iclass 20, count 2 2006.173.14:51:37.02#ibcon#read 5, iclass 20, count 2 2006.173.14:51:37.02#ibcon#about to read 6, iclass 20, count 2 2006.173.14:51:37.02#ibcon#read 6, iclass 20, count 2 2006.173.14:51:37.02#ibcon#end of sib2, iclass 20, count 2 2006.173.14:51:37.02#ibcon#*mode == 0, iclass 20, count 2 2006.173.14:51:37.02#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.14:51:37.02#ibcon#[25=AT03-05\r\n] 2006.173.14:51:37.02#ibcon#*before write, iclass 20, count 2 2006.173.14:51:37.02#ibcon#enter sib2, iclass 20, count 2 2006.173.14:51:37.02#ibcon#flushed, iclass 20, count 2 2006.173.14:51:37.02#ibcon#about to write, iclass 20, count 2 2006.173.14:51:37.02#ibcon#wrote, iclass 20, count 2 2006.173.14:51:37.02#ibcon#about to read 3, iclass 20, count 2 2006.173.14:51:37.05#ibcon#read 3, iclass 20, count 2 2006.173.14:51:37.05#ibcon#about to read 4, iclass 20, count 2 2006.173.14:51:37.05#ibcon#read 4, iclass 20, count 2 2006.173.14:51:37.05#ibcon#about to read 5, iclass 20, count 2 2006.173.14:51:37.05#ibcon#read 5, iclass 20, count 2 2006.173.14:51:37.05#ibcon#about to read 6, iclass 20, count 2 2006.173.14:51:37.05#ibcon#read 6, iclass 20, count 2 2006.173.14:51:37.05#ibcon#end of sib2, iclass 20, count 2 2006.173.14:51:37.05#ibcon#*after write, iclass 20, count 2 2006.173.14:51:37.05#ibcon#*before return 0, iclass 20, count 2 2006.173.14:51:37.05#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.14:51:37.05#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.14:51:37.05#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.14:51:37.05#ibcon#ireg 7 cls_cnt 0 2006.173.14:51:37.05#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.14:51:37.17#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.14:51:37.17#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.14:51:37.17#ibcon#enter wrdev, iclass 20, count 0 2006.173.14:51:37.17#ibcon#first serial, iclass 20, count 0 2006.173.14:51:37.17#ibcon#enter sib2, iclass 20, count 0 2006.173.14:51:37.17#ibcon#flushed, iclass 20, count 0 2006.173.14:51:37.17#ibcon#about to write, iclass 20, count 0 2006.173.14:51:37.17#ibcon#wrote, iclass 20, count 0 2006.173.14:51:37.17#ibcon#about to read 3, iclass 20, count 0 2006.173.14:51:37.19#ibcon#read 3, iclass 20, count 0 2006.173.14:51:37.19#ibcon#about to read 4, iclass 20, count 0 2006.173.14:51:37.19#ibcon#read 4, iclass 20, count 0 2006.173.14:51:37.19#ibcon#about to read 5, iclass 20, count 0 2006.173.14:51:37.19#ibcon#read 5, iclass 20, count 0 2006.173.14:51:37.19#ibcon#about to read 6, iclass 20, count 0 2006.173.14:51:37.19#ibcon#read 6, iclass 20, count 0 2006.173.14:51:37.19#ibcon#end of sib2, iclass 20, count 0 2006.173.14:51:37.19#ibcon#*mode == 0, iclass 20, count 0 2006.173.14:51:37.19#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.14:51:37.19#ibcon#[25=USB\r\n] 2006.173.14:51:37.19#ibcon#*before write, iclass 20, count 0 2006.173.14:51:37.19#ibcon#enter sib2, iclass 20, count 0 2006.173.14:51:37.19#ibcon#flushed, iclass 20, count 0 2006.173.14:51:37.19#ibcon#about to write, iclass 20, count 0 2006.173.14:51:37.19#ibcon#wrote, iclass 20, count 0 2006.173.14:51:37.19#ibcon#about to read 3, iclass 20, count 0 2006.173.14:51:37.22#ibcon#read 3, iclass 20, count 0 2006.173.14:51:37.22#ibcon#about to read 4, iclass 20, count 0 2006.173.14:51:37.22#ibcon#read 4, iclass 20, count 0 2006.173.14:51:37.22#ibcon#about to read 5, iclass 20, count 0 2006.173.14:51:37.22#ibcon#read 5, iclass 20, count 0 2006.173.14:51:37.22#ibcon#about to read 6, iclass 20, count 0 2006.173.14:51:37.22#ibcon#read 6, iclass 20, count 0 2006.173.14:51:37.22#ibcon#end of sib2, iclass 20, count 0 2006.173.14:51:37.22#ibcon#*after write, iclass 20, count 0 2006.173.14:51:37.22#ibcon#*before return 0, iclass 20, count 0 2006.173.14:51:37.22#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.14:51:37.22#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.14:51:37.22#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.14:51:37.22#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.14:51:37.22$vck44/valo=4,624.99 2006.173.14:51:37.22#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.14:51:37.22#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.14:51:37.22#ibcon#ireg 17 cls_cnt 0 2006.173.14:51:37.22#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.14:51:37.22#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.14:51:37.22#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.14:51:37.22#ibcon#enter wrdev, iclass 22, count 0 2006.173.14:51:37.22#ibcon#first serial, iclass 22, count 0 2006.173.14:51:37.22#ibcon#enter sib2, iclass 22, count 0 2006.173.14:51:37.22#ibcon#flushed, iclass 22, count 0 2006.173.14:51:37.22#ibcon#about to write, iclass 22, count 0 2006.173.14:51:37.22#ibcon#wrote, iclass 22, count 0 2006.173.14:51:37.22#ibcon#about to read 3, iclass 22, count 0 2006.173.14:51:37.24#ibcon#read 3, iclass 22, count 0 2006.173.14:51:37.24#ibcon#about to read 4, iclass 22, count 0 2006.173.14:51:37.24#ibcon#read 4, iclass 22, count 0 2006.173.14:51:37.24#ibcon#about to read 5, iclass 22, count 0 2006.173.14:51:37.24#ibcon#read 5, iclass 22, count 0 2006.173.14:51:37.24#ibcon#about to read 6, iclass 22, count 0 2006.173.14:51:37.24#ibcon#read 6, iclass 22, count 0 2006.173.14:51:37.24#ibcon#end of sib2, iclass 22, count 0 2006.173.14:51:37.24#ibcon#*mode == 0, iclass 22, count 0 2006.173.14:51:37.24#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.14:51:37.24#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.14:51:37.24#ibcon#*before write, iclass 22, count 0 2006.173.14:51:37.24#ibcon#enter sib2, iclass 22, count 0 2006.173.14:51:37.24#ibcon#flushed, iclass 22, count 0 2006.173.14:51:37.24#ibcon#about to write, iclass 22, count 0 2006.173.14:51:37.24#ibcon#wrote, iclass 22, count 0 2006.173.14:51:37.24#ibcon#about to read 3, iclass 22, count 0 2006.173.14:51:37.28#ibcon#read 3, iclass 22, count 0 2006.173.14:51:37.28#ibcon#about to read 4, iclass 22, count 0 2006.173.14:51:37.28#ibcon#read 4, iclass 22, count 0 2006.173.14:51:37.28#ibcon#about to read 5, iclass 22, count 0 2006.173.14:51:37.28#ibcon#read 5, iclass 22, count 0 2006.173.14:51:37.28#ibcon#about to read 6, iclass 22, count 0 2006.173.14:51:37.28#ibcon#read 6, iclass 22, count 0 2006.173.14:51:37.28#ibcon#end of sib2, iclass 22, count 0 2006.173.14:51:37.28#ibcon#*after write, iclass 22, count 0 2006.173.14:51:37.28#ibcon#*before return 0, iclass 22, count 0 2006.173.14:51:37.28#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.14:51:37.28#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.14:51:37.28#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.14:51:37.28#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.14:51:37.28$vck44/va=4,6 2006.173.14:51:37.28#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.14:51:37.28#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.14:51:37.28#ibcon#ireg 11 cls_cnt 2 2006.173.14:51:37.28#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.14:51:37.34#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.14:51:37.34#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.14:51:37.34#ibcon#enter wrdev, iclass 24, count 2 2006.173.14:51:37.34#ibcon#first serial, iclass 24, count 2 2006.173.14:51:37.34#ibcon#enter sib2, iclass 24, count 2 2006.173.14:51:37.34#ibcon#flushed, iclass 24, count 2 2006.173.14:51:37.34#ibcon#about to write, iclass 24, count 2 2006.173.14:51:37.34#ibcon#wrote, iclass 24, count 2 2006.173.14:51:37.34#ibcon#about to read 3, iclass 24, count 2 2006.173.14:51:37.36#ibcon#read 3, iclass 24, count 2 2006.173.14:51:37.36#ibcon#about to read 4, iclass 24, count 2 2006.173.14:51:37.36#ibcon#read 4, iclass 24, count 2 2006.173.14:51:37.36#ibcon#about to read 5, iclass 24, count 2 2006.173.14:51:37.36#ibcon#read 5, iclass 24, count 2 2006.173.14:51:37.36#ibcon#about to read 6, iclass 24, count 2 2006.173.14:51:37.36#ibcon#read 6, iclass 24, count 2 2006.173.14:51:37.36#ibcon#end of sib2, iclass 24, count 2 2006.173.14:51:37.36#ibcon#*mode == 0, iclass 24, count 2 2006.173.14:51:37.36#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.14:51:37.36#ibcon#[25=AT04-06\r\n] 2006.173.14:51:37.36#ibcon#*before write, iclass 24, count 2 2006.173.14:51:37.36#ibcon#enter sib2, iclass 24, count 2 2006.173.14:51:37.36#ibcon#flushed, iclass 24, count 2 2006.173.14:51:37.36#ibcon#about to write, iclass 24, count 2 2006.173.14:51:37.36#ibcon#wrote, iclass 24, count 2 2006.173.14:51:37.36#ibcon#about to read 3, iclass 24, count 2 2006.173.14:51:37.39#ibcon#read 3, iclass 24, count 2 2006.173.14:51:37.39#ibcon#about to read 4, iclass 24, count 2 2006.173.14:51:37.39#ibcon#read 4, iclass 24, count 2 2006.173.14:51:37.39#ibcon#about to read 5, iclass 24, count 2 2006.173.14:51:37.39#ibcon#read 5, iclass 24, count 2 2006.173.14:51:37.39#ibcon#about to read 6, iclass 24, count 2 2006.173.14:51:37.39#ibcon#read 6, iclass 24, count 2 2006.173.14:51:37.39#ibcon#end of sib2, iclass 24, count 2 2006.173.14:51:37.39#ibcon#*after write, iclass 24, count 2 2006.173.14:51:37.39#ibcon#*before return 0, iclass 24, count 2 2006.173.14:51:37.39#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.14:51:37.39#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.14:51:37.39#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.14:51:37.39#ibcon#ireg 7 cls_cnt 0 2006.173.14:51:37.39#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.14:51:37.51#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.14:51:37.51#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.14:51:37.51#ibcon#enter wrdev, iclass 24, count 0 2006.173.14:51:37.51#ibcon#first serial, iclass 24, count 0 2006.173.14:51:37.51#ibcon#enter sib2, iclass 24, count 0 2006.173.14:51:37.51#ibcon#flushed, iclass 24, count 0 2006.173.14:51:37.51#ibcon#about to write, iclass 24, count 0 2006.173.14:51:37.51#ibcon#wrote, iclass 24, count 0 2006.173.14:51:37.51#ibcon#about to read 3, iclass 24, count 0 2006.173.14:51:37.53#ibcon#read 3, iclass 24, count 0 2006.173.14:51:37.53#ibcon#about to read 4, iclass 24, count 0 2006.173.14:51:37.53#ibcon#read 4, iclass 24, count 0 2006.173.14:51:37.53#ibcon#about to read 5, iclass 24, count 0 2006.173.14:51:37.53#ibcon#read 5, iclass 24, count 0 2006.173.14:51:37.53#ibcon#about to read 6, iclass 24, count 0 2006.173.14:51:37.53#ibcon#read 6, iclass 24, count 0 2006.173.14:51:37.53#ibcon#end of sib2, iclass 24, count 0 2006.173.14:51:37.53#ibcon#*mode == 0, iclass 24, count 0 2006.173.14:51:37.53#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.14:51:37.53#ibcon#[25=USB\r\n] 2006.173.14:51:37.53#ibcon#*before write, iclass 24, count 0 2006.173.14:51:37.53#ibcon#enter sib2, iclass 24, count 0 2006.173.14:51:37.53#ibcon#flushed, iclass 24, count 0 2006.173.14:51:37.53#ibcon#about to write, iclass 24, count 0 2006.173.14:51:37.53#ibcon#wrote, iclass 24, count 0 2006.173.14:51:37.53#ibcon#about to read 3, iclass 24, count 0 2006.173.14:51:37.56#ibcon#read 3, iclass 24, count 0 2006.173.14:51:37.56#ibcon#about to read 4, iclass 24, count 0 2006.173.14:51:37.56#ibcon#read 4, iclass 24, count 0 2006.173.14:51:37.56#ibcon#about to read 5, iclass 24, count 0 2006.173.14:51:37.56#ibcon#read 5, iclass 24, count 0 2006.173.14:51:37.56#ibcon#about to read 6, iclass 24, count 0 2006.173.14:51:37.56#ibcon#read 6, iclass 24, count 0 2006.173.14:51:37.56#ibcon#end of sib2, iclass 24, count 0 2006.173.14:51:37.56#ibcon#*after write, iclass 24, count 0 2006.173.14:51:37.56#ibcon#*before return 0, iclass 24, count 0 2006.173.14:51:37.56#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.14:51:37.56#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.14:51:37.56#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.14:51:37.56#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.14:51:37.56$vck44/valo=5,734.99 2006.173.14:51:37.56#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.14:51:37.56#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.14:51:37.56#ibcon#ireg 17 cls_cnt 0 2006.173.14:51:37.56#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.14:51:37.56#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.14:51:37.56#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.14:51:37.56#ibcon#enter wrdev, iclass 26, count 0 2006.173.14:51:37.56#ibcon#first serial, iclass 26, count 0 2006.173.14:51:37.56#ibcon#enter sib2, iclass 26, count 0 2006.173.14:51:37.56#ibcon#flushed, iclass 26, count 0 2006.173.14:51:37.56#ibcon#about to write, iclass 26, count 0 2006.173.14:51:37.56#ibcon#wrote, iclass 26, count 0 2006.173.14:51:37.56#ibcon#about to read 3, iclass 26, count 0 2006.173.14:51:37.58#ibcon#read 3, iclass 26, count 0 2006.173.14:51:37.58#ibcon#about to read 4, iclass 26, count 0 2006.173.14:51:37.58#ibcon#read 4, iclass 26, count 0 2006.173.14:51:37.58#ibcon#about to read 5, iclass 26, count 0 2006.173.14:51:37.58#ibcon#read 5, iclass 26, count 0 2006.173.14:51:37.58#ibcon#about to read 6, iclass 26, count 0 2006.173.14:51:37.58#ibcon#read 6, iclass 26, count 0 2006.173.14:51:37.58#ibcon#end of sib2, iclass 26, count 0 2006.173.14:51:37.58#ibcon#*mode == 0, iclass 26, count 0 2006.173.14:51:37.58#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.14:51:37.58#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.14:51:37.58#ibcon#*before write, iclass 26, count 0 2006.173.14:51:37.58#ibcon#enter sib2, iclass 26, count 0 2006.173.14:51:37.58#ibcon#flushed, iclass 26, count 0 2006.173.14:51:37.58#ibcon#about to write, iclass 26, count 0 2006.173.14:51:37.58#ibcon#wrote, iclass 26, count 0 2006.173.14:51:37.58#ibcon#about to read 3, iclass 26, count 0 2006.173.14:51:37.62#ibcon#read 3, iclass 26, count 0 2006.173.14:51:37.62#ibcon#about to read 4, iclass 26, count 0 2006.173.14:51:37.62#ibcon#read 4, iclass 26, count 0 2006.173.14:51:37.62#ibcon#about to read 5, iclass 26, count 0 2006.173.14:51:37.62#ibcon#read 5, iclass 26, count 0 2006.173.14:51:37.62#ibcon#about to read 6, iclass 26, count 0 2006.173.14:51:37.62#ibcon#read 6, iclass 26, count 0 2006.173.14:51:37.62#ibcon#end of sib2, iclass 26, count 0 2006.173.14:51:37.62#ibcon#*after write, iclass 26, count 0 2006.173.14:51:37.62#ibcon#*before return 0, iclass 26, count 0 2006.173.14:51:37.62#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.14:51:37.62#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.14:51:37.62#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.14:51:37.62#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.14:51:37.62$vck44/va=5,4 2006.173.14:51:37.62#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.14:51:37.62#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.14:51:37.62#ibcon#ireg 11 cls_cnt 2 2006.173.14:51:37.62#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.14:51:37.68#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.14:51:37.68#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.14:51:37.68#ibcon#enter wrdev, iclass 28, count 2 2006.173.14:51:37.68#ibcon#first serial, iclass 28, count 2 2006.173.14:51:37.68#ibcon#enter sib2, iclass 28, count 2 2006.173.14:51:37.68#ibcon#flushed, iclass 28, count 2 2006.173.14:51:37.68#ibcon#about to write, iclass 28, count 2 2006.173.14:51:37.68#ibcon#wrote, iclass 28, count 2 2006.173.14:51:37.68#ibcon#about to read 3, iclass 28, count 2 2006.173.14:51:37.70#ibcon#read 3, iclass 28, count 2 2006.173.14:51:37.70#ibcon#about to read 4, iclass 28, count 2 2006.173.14:51:37.70#ibcon#read 4, iclass 28, count 2 2006.173.14:51:37.70#ibcon#about to read 5, iclass 28, count 2 2006.173.14:51:37.70#ibcon#read 5, iclass 28, count 2 2006.173.14:51:37.70#ibcon#about to read 6, iclass 28, count 2 2006.173.14:51:37.70#ibcon#read 6, iclass 28, count 2 2006.173.14:51:37.70#ibcon#end of sib2, iclass 28, count 2 2006.173.14:51:37.70#ibcon#*mode == 0, iclass 28, count 2 2006.173.14:51:37.70#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.14:51:37.70#ibcon#[25=AT05-04\r\n] 2006.173.14:51:37.70#ibcon#*before write, iclass 28, count 2 2006.173.14:51:37.70#ibcon#enter sib2, iclass 28, count 2 2006.173.14:51:37.70#ibcon#flushed, iclass 28, count 2 2006.173.14:51:37.70#ibcon#about to write, iclass 28, count 2 2006.173.14:51:37.70#ibcon#wrote, iclass 28, count 2 2006.173.14:51:37.70#ibcon#about to read 3, iclass 28, count 2 2006.173.14:51:37.73#ibcon#read 3, iclass 28, count 2 2006.173.14:51:37.73#ibcon#about to read 4, iclass 28, count 2 2006.173.14:51:37.73#ibcon#read 4, iclass 28, count 2 2006.173.14:51:37.73#ibcon#about to read 5, iclass 28, count 2 2006.173.14:51:37.73#ibcon#read 5, iclass 28, count 2 2006.173.14:51:37.73#ibcon#about to read 6, iclass 28, count 2 2006.173.14:51:37.73#ibcon#read 6, iclass 28, count 2 2006.173.14:51:37.73#ibcon#end of sib2, iclass 28, count 2 2006.173.14:51:37.73#ibcon#*after write, iclass 28, count 2 2006.173.14:51:37.73#ibcon#*before return 0, iclass 28, count 2 2006.173.14:51:37.73#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.14:51:37.73#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.14:51:37.73#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.14:51:37.73#ibcon#ireg 7 cls_cnt 0 2006.173.14:51:37.73#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.14:51:37.85#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.14:51:37.85#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.14:51:37.85#ibcon#enter wrdev, iclass 28, count 0 2006.173.14:51:37.85#ibcon#first serial, iclass 28, count 0 2006.173.14:51:37.85#ibcon#enter sib2, iclass 28, count 0 2006.173.14:51:37.85#ibcon#flushed, iclass 28, count 0 2006.173.14:51:37.85#ibcon#about to write, iclass 28, count 0 2006.173.14:51:37.85#ibcon#wrote, iclass 28, count 0 2006.173.14:51:37.85#ibcon#about to read 3, iclass 28, count 0 2006.173.14:51:37.87#ibcon#read 3, iclass 28, count 0 2006.173.14:51:37.87#ibcon#about to read 4, iclass 28, count 0 2006.173.14:51:37.87#ibcon#read 4, iclass 28, count 0 2006.173.14:51:37.87#ibcon#about to read 5, iclass 28, count 0 2006.173.14:51:37.87#ibcon#read 5, iclass 28, count 0 2006.173.14:51:37.87#ibcon#about to read 6, iclass 28, count 0 2006.173.14:51:37.87#ibcon#read 6, iclass 28, count 0 2006.173.14:51:37.87#ibcon#end of sib2, iclass 28, count 0 2006.173.14:51:37.87#ibcon#*mode == 0, iclass 28, count 0 2006.173.14:51:37.87#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.14:51:37.87#ibcon#[25=USB\r\n] 2006.173.14:51:37.87#ibcon#*before write, iclass 28, count 0 2006.173.14:51:37.87#ibcon#enter sib2, iclass 28, count 0 2006.173.14:51:37.87#ibcon#flushed, iclass 28, count 0 2006.173.14:51:37.87#ibcon#about to write, iclass 28, count 0 2006.173.14:51:37.87#ibcon#wrote, iclass 28, count 0 2006.173.14:51:37.87#ibcon#about to read 3, iclass 28, count 0 2006.173.14:51:37.90#ibcon#read 3, iclass 28, count 0 2006.173.14:51:37.90#ibcon#about to read 4, iclass 28, count 0 2006.173.14:51:37.90#ibcon#read 4, iclass 28, count 0 2006.173.14:51:37.90#ibcon#about to read 5, iclass 28, count 0 2006.173.14:51:37.90#ibcon#read 5, iclass 28, count 0 2006.173.14:51:37.90#ibcon#about to read 6, iclass 28, count 0 2006.173.14:51:37.90#ibcon#read 6, iclass 28, count 0 2006.173.14:51:37.90#ibcon#end of sib2, iclass 28, count 0 2006.173.14:51:37.90#ibcon#*after write, iclass 28, count 0 2006.173.14:51:37.90#ibcon#*before return 0, iclass 28, count 0 2006.173.14:51:37.90#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.14:51:37.90#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.14:51:37.90#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.14:51:37.90#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.14:51:37.90$vck44/valo=6,814.99 2006.173.14:51:37.90#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.14:51:37.90#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.14:51:37.90#ibcon#ireg 17 cls_cnt 0 2006.173.14:51:37.90#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.14:51:37.90#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.14:51:37.90#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.14:51:37.90#ibcon#enter wrdev, iclass 30, count 0 2006.173.14:51:37.90#ibcon#first serial, iclass 30, count 0 2006.173.14:51:37.90#ibcon#enter sib2, iclass 30, count 0 2006.173.14:51:37.90#ibcon#flushed, iclass 30, count 0 2006.173.14:51:37.90#ibcon#about to write, iclass 30, count 0 2006.173.14:51:37.90#ibcon#wrote, iclass 30, count 0 2006.173.14:51:37.90#ibcon#about to read 3, iclass 30, count 0 2006.173.14:51:37.92#ibcon#read 3, iclass 30, count 0 2006.173.14:51:37.92#ibcon#about to read 4, iclass 30, count 0 2006.173.14:51:37.92#ibcon#read 4, iclass 30, count 0 2006.173.14:51:37.92#ibcon#about to read 5, iclass 30, count 0 2006.173.14:51:37.92#ibcon#read 5, iclass 30, count 0 2006.173.14:51:37.92#ibcon#about to read 6, iclass 30, count 0 2006.173.14:51:37.92#ibcon#read 6, iclass 30, count 0 2006.173.14:51:37.92#ibcon#end of sib2, iclass 30, count 0 2006.173.14:51:37.92#ibcon#*mode == 0, iclass 30, count 0 2006.173.14:51:37.92#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.14:51:37.92#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.14:51:37.92#ibcon#*before write, iclass 30, count 0 2006.173.14:51:37.92#ibcon#enter sib2, iclass 30, count 0 2006.173.14:51:37.92#ibcon#flushed, iclass 30, count 0 2006.173.14:51:37.92#ibcon#about to write, iclass 30, count 0 2006.173.14:51:37.92#ibcon#wrote, iclass 30, count 0 2006.173.14:51:37.92#ibcon#about to read 3, iclass 30, count 0 2006.173.14:51:37.96#ibcon#read 3, iclass 30, count 0 2006.173.14:51:37.96#ibcon#about to read 4, iclass 30, count 0 2006.173.14:51:37.96#ibcon#read 4, iclass 30, count 0 2006.173.14:51:37.96#ibcon#about to read 5, iclass 30, count 0 2006.173.14:51:37.96#ibcon#read 5, iclass 30, count 0 2006.173.14:51:37.96#ibcon#about to read 6, iclass 30, count 0 2006.173.14:51:37.96#ibcon#read 6, iclass 30, count 0 2006.173.14:51:37.96#ibcon#end of sib2, iclass 30, count 0 2006.173.14:51:37.96#ibcon#*after write, iclass 30, count 0 2006.173.14:51:37.96#ibcon#*before return 0, iclass 30, count 0 2006.173.14:51:37.96#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.14:51:37.96#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.14:51:37.96#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.14:51:37.96#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.14:51:37.96$vck44/va=6,3 2006.173.14:51:37.96#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.173.14:51:37.96#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.173.14:51:37.96#ibcon#ireg 11 cls_cnt 2 2006.173.14:51:37.96#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.14:51:38.02#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.14:51:38.02#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.14:51:38.02#ibcon#enter wrdev, iclass 32, count 2 2006.173.14:51:38.02#ibcon#first serial, iclass 32, count 2 2006.173.14:51:38.02#ibcon#enter sib2, iclass 32, count 2 2006.173.14:51:38.02#ibcon#flushed, iclass 32, count 2 2006.173.14:51:38.02#ibcon#about to write, iclass 32, count 2 2006.173.14:51:38.02#ibcon#wrote, iclass 32, count 2 2006.173.14:51:38.02#ibcon#about to read 3, iclass 32, count 2 2006.173.14:51:38.04#ibcon#read 3, iclass 32, count 2 2006.173.14:51:38.04#ibcon#about to read 4, iclass 32, count 2 2006.173.14:51:38.04#ibcon#read 4, iclass 32, count 2 2006.173.14:51:38.04#ibcon#about to read 5, iclass 32, count 2 2006.173.14:51:38.04#ibcon#read 5, iclass 32, count 2 2006.173.14:51:38.04#ibcon#about to read 6, iclass 32, count 2 2006.173.14:51:38.04#ibcon#read 6, iclass 32, count 2 2006.173.14:51:38.04#ibcon#end of sib2, iclass 32, count 2 2006.173.14:51:38.04#ibcon#*mode == 0, iclass 32, count 2 2006.173.14:51:38.04#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.173.14:51:38.04#ibcon#[25=AT06-03\r\n] 2006.173.14:51:38.04#ibcon#*before write, iclass 32, count 2 2006.173.14:51:38.04#ibcon#enter sib2, iclass 32, count 2 2006.173.14:51:38.04#ibcon#flushed, iclass 32, count 2 2006.173.14:51:38.04#ibcon#about to write, iclass 32, count 2 2006.173.14:51:38.04#ibcon#wrote, iclass 32, count 2 2006.173.14:51:38.04#ibcon#about to read 3, iclass 32, count 2 2006.173.14:51:38.07#ibcon#read 3, iclass 32, count 2 2006.173.14:51:38.07#ibcon#about to read 4, iclass 32, count 2 2006.173.14:51:38.07#ibcon#read 4, iclass 32, count 2 2006.173.14:51:38.07#ibcon#about to read 5, iclass 32, count 2 2006.173.14:51:38.07#ibcon#read 5, iclass 32, count 2 2006.173.14:51:38.07#ibcon#about to read 6, iclass 32, count 2 2006.173.14:51:38.07#ibcon#read 6, iclass 32, count 2 2006.173.14:51:38.07#ibcon#end of sib2, iclass 32, count 2 2006.173.14:51:38.07#ibcon#*after write, iclass 32, count 2 2006.173.14:51:38.07#ibcon#*before return 0, iclass 32, count 2 2006.173.14:51:38.07#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.14:51:38.07#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.173.14:51:38.07#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.173.14:51:38.07#ibcon#ireg 7 cls_cnt 0 2006.173.14:51:38.07#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.14:51:38.19#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.14:51:38.19#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.14:51:38.19#ibcon#enter wrdev, iclass 32, count 0 2006.173.14:51:38.19#ibcon#first serial, iclass 32, count 0 2006.173.14:51:38.19#ibcon#enter sib2, iclass 32, count 0 2006.173.14:51:38.19#ibcon#flushed, iclass 32, count 0 2006.173.14:51:38.19#ibcon#about to write, iclass 32, count 0 2006.173.14:51:38.19#ibcon#wrote, iclass 32, count 0 2006.173.14:51:38.19#ibcon#about to read 3, iclass 32, count 0 2006.173.14:51:38.21#ibcon#read 3, iclass 32, count 0 2006.173.14:51:38.21#ibcon#about to read 4, iclass 32, count 0 2006.173.14:51:38.21#ibcon#read 4, iclass 32, count 0 2006.173.14:51:38.21#ibcon#about to read 5, iclass 32, count 0 2006.173.14:51:38.21#ibcon#read 5, iclass 32, count 0 2006.173.14:51:38.21#ibcon#about to read 6, iclass 32, count 0 2006.173.14:51:38.21#ibcon#read 6, iclass 32, count 0 2006.173.14:51:38.21#ibcon#end of sib2, iclass 32, count 0 2006.173.14:51:38.21#ibcon#*mode == 0, iclass 32, count 0 2006.173.14:51:38.21#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.14:51:38.21#ibcon#[25=USB\r\n] 2006.173.14:51:38.21#ibcon#*before write, iclass 32, count 0 2006.173.14:51:38.21#ibcon#enter sib2, iclass 32, count 0 2006.173.14:51:38.21#ibcon#flushed, iclass 32, count 0 2006.173.14:51:38.21#ibcon#about to write, iclass 32, count 0 2006.173.14:51:38.21#ibcon#wrote, iclass 32, count 0 2006.173.14:51:38.21#ibcon#about to read 3, iclass 32, count 0 2006.173.14:51:38.24#ibcon#read 3, iclass 32, count 0 2006.173.14:51:38.24#ibcon#about to read 4, iclass 32, count 0 2006.173.14:51:38.24#ibcon#read 4, iclass 32, count 0 2006.173.14:51:38.24#ibcon#about to read 5, iclass 32, count 0 2006.173.14:51:38.24#ibcon#read 5, iclass 32, count 0 2006.173.14:51:38.24#ibcon#about to read 6, iclass 32, count 0 2006.173.14:51:38.24#ibcon#read 6, iclass 32, count 0 2006.173.14:51:38.24#ibcon#end of sib2, iclass 32, count 0 2006.173.14:51:38.24#ibcon#*after write, iclass 32, count 0 2006.173.14:51:38.24#ibcon#*before return 0, iclass 32, count 0 2006.173.14:51:38.24#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.14:51:38.24#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.173.14:51:38.24#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.14:51:38.24#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.14:51:38.24$vck44/valo=7,864.99 2006.173.14:51:38.24#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.14:51:38.24#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.14:51:38.24#ibcon#ireg 17 cls_cnt 0 2006.173.14:51:38.24#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.14:51:38.24#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.14:51:38.24#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.14:51:38.24#ibcon#enter wrdev, iclass 34, count 0 2006.173.14:51:38.24#ibcon#first serial, iclass 34, count 0 2006.173.14:51:38.24#ibcon#enter sib2, iclass 34, count 0 2006.173.14:51:38.24#ibcon#flushed, iclass 34, count 0 2006.173.14:51:38.24#ibcon#about to write, iclass 34, count 0 2006.173.14:51:38.24#ibcon#wrote, iclass 34, count 0 2006.173.14:51:38.24#ibcon#about to read 3, iclass 34, count 0 2006.173.14:51:38.26#ibcon#read 3, iclass 34, count 0 2006.173.14:51:38.26#ibcon#about to read 4, iclass 34, count 0 2006.173.14:51:38.26#ibcon#read 4, iclass 34, count 0 2006.173.14:51:38.26#ibcon#about to read 5, iclass 34, count 0 2006.173.14:51:38.26#ibcon#read 5, iclass 34, count 0 2006.173.14:51:38.26#ibcon#about to read 6, iclass 34, count 0 2006.173.14:51:38.26#ibcon#read 6, iclass 34, count 0 2006.173.14:51:38.26#ibcon#end of sib2, iclass 34, count 0 2006.173.14:51:38.26#ibcon#*mode == 0, iclass 34, count 0 2006.173.14:51:38.26#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.14:51:38.26#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.14:51:38.26#ibcon#*before write, iclass 34, count 0 2006.173.14:51:38.26#ibcon#enter sib2, iclass 34, count 0 2006.173.14:51:38.26#ibcon#flushed, iclass 34, count 0 2006.173.14:51:38.26#ibcon#about to write, iclass 34, count 0 2006.173.14:51:38.26#ibcon#wrote, iclass 34, count 0 2006.173.14:51:38.26#ibcon#about to read 3, iclass 34, count 0 2006.173.14:51:38.30#ibcon#read 3, iclass 34, count 0 2006.173.14:51:38.30#ibcon#about to read 4, iclass 34, count 0 2006.173.14:51:38.30#ibcon#read 4, iclass 34, count 0 2006.173.14:51:38.30#ibcon#about to read 5, iclass 34, count 0 2006.173.14:51:38.30#ibcon#read 5, iclass 34, count 0 2006.173.14:51:38.30#ibcon#about to read 6, iclass 34, count 0 2006.173.14:51:38.30#ibcon#read 6, iclass 34, count 0 2006.173.14:51:38.30#ibcon#end of sib2, iclass 34, count 0 2006.173.14:51:38.30#ibcon#*after write, iclass 34, count 0 2006.173.14:51:38.30#ibcon#*before return 0, iclass 34, count 0 2006.173.14:51:38.30#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.14:51:38.30#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.14:51:38.30#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.14:51:38.30#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.14:51:38.30$vck44/va=7,4 2006.173.14:51:38.30#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.14:51:38.30#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.14:51:38.30#ibcon#ireg 11 cls_cnt 2 2006.173.14:51:38.30#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.14:51:38.36#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.14:51:38.36#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.14:51:38.36#ibcon#enter wrdev, iclass 36, count 2 2006.173.14:51:38.36#ibcon#first serial, iclass 36, count 2 2006.173.14:51:38.36#ibcon#enter sib2, iclass 36, count 2 2006.173.14:51:38.36#ibcon#flushed, iclass 36, count 2 2006.173.14:51:38.36#ibcon#about to write, iclass 36, count 2 2006.173.14:51:38.36#ibcon#wrote, iclass 36, count 2 2006.173.14:51:38.36#ibcon#about to read 3, iclass 36, count 2 2006.173.14:51:38.38#ibcon#read 3, iclass 36, count 2 2006.173.14:51:38.38#ibcon#about to read 4, iclass 36, count 2 2006.173.14:51:38.38#ibcon#read 4, iclass 36, count 2 2006.173.14:51:38.38#ibcon#about to read 5, iclass 36, count 2 2006.173.14:51:38.38#ibcon#read 5, iclass 36, count 2 2006.173.14:51:38.38#ibcon#about to read 6, iclass 36, count 2 2006.173.14:51:38.38#ibcon#read 6, iclass 36, count 2 2006.173.14:51:38.38#ibcon#end of sib2, iclass 36, count 2 2006.173.14:51:38.38#ibcon#*mode == 0, iclass 36, count 2 2006.173.14:51:38.38#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.14:51:38.38#ibcon#[25=AT07-04\r\n] 2006.173.14:51:38.38#ibcon#*before write, iclass 36, count 2 2006.173.14:51:38.38#ibcon#enter sib2, iclass 36, count 2 2006.173.14:51:38.38#ibcon#flushed, iclass 36, count 2 2006.173.14:51:38.38#ibcon#about to write, iclass 36, count 2 2006.173.14:51:38.38#ibcon#wrote, iclass 36, count 2 2006.173.14:51:38.38#ibcon#about to read 3, iclass 36, count 2 2006.173.14:51:38.41#ibcon#read 3, iclass 36, count 2 2006.173.14:51:38.41#ibcon#about to read 4, iclass 36, count 2 2006.173.14:51:38.41#ibcon#read 4, iclass 36, count 2 2006.173.14:51:38.41#ibcon#about to read 5, iclass 36, count 2 2006.173.14:51:38.41#ibcon#read 5, iclass 36, count 2 2006.173.14:51:38.41#ibcon#about to read 6, iclass 36, count 2 2006.173.14:51:38.41#ibcon#read 6, iclass 36, count 2 2006.173.14:51:38.41#ibcon#end of sib2, iclass 36, count 2 2006.173.14:51:38.41#ibcon#*after write, iclass 36, count 2 2006.173.14:51:38.41#ibcon#*before return 0, iclass 36, count 2 2006.173.14:51:38.41#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.14:51:38.41#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.14:51:38.41#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.14:51:38.41#ibcon#ireg 7 cls_cnt 0 2006.173.14:51:38.41#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.14:51:38.53#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.14:51:38.53#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.14:51:38.53#ibcon#enter wrdev, iclass 36, count 0 2006.173.14:51:38.53#ibcon#first serial, iclass 36, count 0 2006.173.14:51:38.53#ibcon#enter sib2, iclass 36, count 0 2006.173.14:51:38.53#ibcon#flushed, iclass 36, count 0 2006.173.14:51:38.53#ibcon#about to write, iclass 36, count 0 2006.173.14:51:38.53#ibcon#wrote, iclass 36, count 0 2006.173.14:51:38.53#ibcon#about to read 3, iclass 36, count 0 2006.173.14:51:38.55#ibcon#read 3, iclass 36, count 0 2006.173.14:51:38.55#ibcon#about to read 4, iclass 36, count 0 2006.173.14:51:38.55#ibcon#read 4, iclass 36, count 0 2006.173.14:51:38.55#ibcon#about to read 5, iclass 36, count 0 2006.173.14:51:38.55#ibcon#read 5, iclass 36, count 0 2006.173.14:51:38.55#ibcon#about to read 6, iclass 36, count 0 2006.173.14:51:38.55#ibcon#read 6, iclass 36, count 0 2006.173.14:51:38.55#ibcon#end of sib2, iclass 36, count 0 2006.173.14:51:38.55#ibcon#*mode == 0, iclass 36, count 0 2006.173.14:51:38.55#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.14:51:38.55#ibcon#[25=USB\r\n] 2006.173.14:51:38.55#ibcon#*before write, iclass 36, count 0 2006.173.14:51:38.55#ibcon#enter sib2, iclass 36, count 0 2006.173.14:51:38.55#ibcon#flushed, iclass 36, count 0 2006.173.14:51:38.55#ibcon#about to write, iclass 36, count 0 2006.173.14:51:38.55#ibcon#wrote, iclass 36, count 0 2006.173.14:51:38.55#ibcon#about to read 3, iclass 36, count 0 2006.173.14:51:38.58#ibcon#read 3, iclass 36, count 0 2006.173.14:51:38.58#ibcon#about to read 4, iclass 36, count 0 2006.173.14:51:38.58#ibcon#read 4, iclass 36, count 0 2006.173.14:51:38.58#ibcon#about to read 5, iclass 36, count 0 2006.173.14:51:38.58#ibcon#read 5, iclass 36, count 0 2006.173.14:51:38.58#ibcon#about to read 6, iclass 36, count 0 2006.173.14:51:38.58#ibcon#read 6, iclass 36, count 0 2006.173.14:51:38.58#ibcon#end of sib2, iclass 36, count 0 2006.173.14:51:38.58#ibcon#*after write, iclass 36, count 0 2006.173.14:51:38.58#ibcon#*before return 0, iclass 36, count 0 2006.173.14:51:38.58#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.14:51:38.58#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.14:51:38.58#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.14:51:38.58#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.14:51:38.58$vck44/valo=8,884.99 2006.173.14:51:38.58#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.14:51:38.58#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.14:51:38.58#ibcon#ireg 17 cls_cnt 0 2006.173.14:51:38.58#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.14:51:38.58#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.14:51:38.58#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.14:51:38.58#ibcon#enter wrdev, iclass 38, count 0 2006.173.14:51:38.58#ibcon#first serial, iclass 38, count 0 2006.173.14:51:38.58#ibcon#enter sib2, iclass 38, count 0 2006.173.14:51:38.58#ibcon#flushed, iclass 38, count 0 2006.173.14:51:38.58#ibcon#about to write, iclass 38, count 0 2006.173.14:51:38.58#ibcon#wrote, iclass 38, count 0 2006.173.14:51:38.58#ibcon#about to read 3, iclass 38, count 0 2006.173.14:51:38.60#ibcon#read 3, iclass 38, count 0 2006.173.14:51:38.60#ibcon#about to read 4, iclass 38, count 0 2006.173.14:51:38.60#ibcon#read 4, iclass 38, count 0 2006.173.14:51:38.60#ibcon#about to read 5, iclass 38, count 0 2006.173.14:51:38.60#ibcon#read 5, iclass 38, count 0 2006.173.14:51:38.60#ibcon#about to read 6, iclass 38, count 0 2006.173.14:51:38.60#ibcon#read 6, iclass 38, count 0 2006.173.14:51:38.60#ibcon#end of sib2, iclass 38, count 0 2006.173.14:51:38.60#ibcon#*mode == 0, iclass 38, count 0 2006.173.14:51:38.60#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.14:51:38.60#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.14:51:38.60#ibcon#*before write, iclass 38, count 0 2006.173.14:51:38.60#ibcon#enter sib2, iclass 38, count 0 2006.173.14:51:38.60#ibcon#flushed, iclass 38, count 0 2006.173.14:51:38.60#ibcon#about to write, iclass 38, count 0 2006.173.14:51:38.60#ibcon#wrote, iclass 38, count 0 2006.173.14:51:38.60#ibcon#about to read 3, iclass 38, count 0 2006.173.14:51:38.64#ibcon#read 3, iclass 38, count 0 2006.173.14:51:38.64#ibcon#about to read 4, iclass 38, count 0 2006.173.14:51:38.64#ibcon#read 4, iclass 38, count 0 2006.173.14:51:38.64#ibcon#about to read 5, iclass 38, count 0 2006.173.14:51:38.64#ibcon#read 5, iclass 38, count 0 2006.173.14:51:38.64#ibcon#about to read 6, iclass 38, count 0 2006.173.14:51:38.64#ibcon#read 6, iclass 38, count 0 2006.173.14:51:38.64#ibcon#end of sib2, iclass 38, count 0 2006.173.14:51:38.64#ibcon#*after write, iclass 38, count 0 2006.173.14:51:38.64#ibcon#*before return 0, iclass 38, count 0 2006.173.14:51:38.64#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.14:51:38.64#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.14:51:38.64#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.14:51:38.64#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.14:51:38.64$vck44/va=8,4 2006.173.14:51:38.64#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.14:51:38.64#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.14:51:38.64#ibcon#ireg 11 cls_cnt 2 2006.173.14:51:38.64#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.14:51:38.70#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.14:51:38.70#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.14:51:38.70#ibcon#enter wrdev, iclass 40, count 2 2006.173.14:51:38.70#ibcon#first serial, iclass 40, count 2 2006.173.14:51:38.70#ibcon#enter sib2, iclass 40, count 2 2006.173.14:51:38.70#ibcon#flushed, iclass 40, count 2 2006.173.14:51:38.70#ibcon#about to write, iclass 40, count 2 2006.173.14:51:38.70#ibcon#wrote, iclass 40, count 2 2006.173.14:51:38.70#ibcon#about to read 3, iclass 40, count 2 2006.173.14:51:38.72#ibcon#read 3, iclass 40, count 2 2006.173.14:51:38.72#ibcon#about to read 4, iclass 40, count 2 2006.173.14:51:38.72#ibcon#read 4, iclass 40, count 2 2006.173.14:51:38.72#ibcon#about to read 5, iclass 40, count 2 2006.173.14:51:38.72#ibcon#read 5, iclass 40, count 2 2006.173.14:51:38.72#ibcon#about to read 6, iclass 40, count 2 2006.173.14:51:38.72#ibcon#read 6, iclass 40, count 2 2006.173.14:51:38.72#ibcon#end of sib2, iclass 40, count 2 2006.173.14:51:38.72#ibcon#*mode == 0, iclass 40, count 2 2006.173.14:51:38.72#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.14:51:38.72#ibcon#[25=AT08-04\r\n] 2006.173.14:51:38.72#ibcon#*before write, iclass 40, count 2 2006.173.14:51:38.72#ibcon#enter sib2, iclass 40, count 2 2006.173.14:51:38.72#ibcon#flushed, iclass 40, count 2 2006.173.14:51:38.72#ibcon#about to write, iclass 40, count 2 2006.173.14:51:38.72#ibcon#wrote, iclass 40, count 2 2006.173.14:51:38.72#ibcon#about to read 3, iclass 40, count 2 2006.173.14:51:38.75#ibcon#read 3, iclass 40, count 2 2006.173.14:51:38.75#ibcon#about to read 4, iclass 40, count 2 2006.173.14:51:38.75#ibcon#read 4, iclass 40, count 2 2006.173.14:51:38.75#ibcon#about to read 5, iclass 40, count 2 2006.173.14:51:38.75#ibcon#read 5, iclass 40, count 2 2006.173.14:51:38.75#ibcon#about to read 6, iclass 40, count 2 2006.173.14:51:38.75#ibcon#read 6, iclass 40, count 2 2006.173.14:51:38.75#ibcon#end of sib2, iclass 40, count 2 2006.173.14:51:38.75#ibcon#*after write, iclass 40, count 2 2006.173.14:51:38.75#ibcon#*before return 0, iclass 40, count 2 2006.173.14:51:38.75#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.14:51:38.75#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.14:51:38.75#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.14:51:38.75#ibcon#ireg 7 cls_cnt 0 2006.173.14:51:38.75#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.14:51:38.87#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.14:51:38.87#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.14:51:38.87#ibcon#enter wrdev, iclass 40, count 0 2006.173.14:51:38.87#ibcon#first serial, iclass 40, count 0 2006.173.14:51:38.87#ibcon#enter sib2, iclass 40, count 0 2006.173.14:51:38.87#ibcon#flushed, iclass 40, count 0 2006.173.14:51:38.87#ibcon#about to write, iclass 40, count 0 2006.173.14:51:38.87#ibcon#wrote, iclass 40, count 0 2006.173.14:51:38.87#ibcon#about to read 3, iclass 40, count 0 2006.173.14:51:38.89#ibcon#read 3, iclass 40, count 0 2006.173.14:51:38.89#ibcon#about to read 4, iclass 40, count 0 2006.173.14:51:38.89#ibcon#read 4, iclass 40, count 0 2006.173.14:51:38.89#ibcon#about to read 5, iclass 40, count 0 2006.173.14:51:38.89#ibcon#read 5, iclass 40, count 0 2006.173.14:51:38.89#ibcon#about to read 6, iclass 40, count 0 2006.173.14:51:38.89#ibcon#read 6, iclass 40, count 0 2006.173.14:51:38.89#ibcon#end of sib2, iclass 40, count 0 2006.173.14:51:38.89#ibcon#*mode == 0, iclass 40, count 0 2006.173.14:51:38.89#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.14:51:38.89#ibcon#[25=USB\r\n] 2006.173.14:51:38.89#ibcon#*before write, iclass 40, count 0 2006.173.14:51:38.89#ibcon#enter sib2, iclass 40, count 0 2006.173.14:51:38.89#ibcon#flushed, iclass 40, count 0 2006.173.14:51:38.89#ibcon#about to write, iclass 40, count 0 2006.173.14:51:38.89#ibcon#wrote, iclass 40, count 0 2006.173.14:51:38.89#ibcon#about to read 3, iclass 40, count 0 2006.173.14:51:38.92#ibcon#read 3, iclass 40, count 0 2006.173.14:51:38.92#ibcon#about to read 4, iclass 40, count 0 2006.173.14:51:38.92#ibcon#read 4, iclass 40, count 0 2006.173.14:51:38.92#ibcon#about to read 5, iclass 40, count 0 2006.173.14:51:38.92#ibcon#read 5, iclass 40, count 0 2006.173.14:51:38.92#ibcon#about to read 6, iclass 40, count 0 2006.173.14:51:38.92#ibcon#read 6, iclass 40, count 0 2006.173.14:51:38.92#ibcon#end of sib2, iclass 40, count 0 2006.173.14:51:38.92#ibcon#*after write, iclass 40, count 0 2006.173.14:51:38.92#ibcon#*before return 0, iclass 40, count 0 2006.173.14:51:38.92#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.14:51:38.92#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.14:51:38.92#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.14:51:38.92#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.14:51:38.92$vck44/vblo=1,629.99 2006.173.14:51:38.92#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.14:51:38.92#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.14:51:38.92#ibcon#ireg 17 cls_cnt 0 2006.173.14:51:38.92#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.14:51:38.92#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.14:51:38.92#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.14:51:38.92#ibcon#enter wrdev, iclass 4, count 0 2006.173.14:51:38.92#ibcon#first serial, iclass 4, count 0 2006.173.14:51:38.92#ibcon#enter sib2, iclass 4, count 0 2006.173.14:51:38.92#ibcon#flushed, iclass 4, count 0 2006.173.14:51:38.92#ibcon#about to write, iclass 4, count 0 2006.173.14:51:38.92#ibcon#wrote, iclass 4, count 0 2006.173.14:51:38.92#ibcon#about to read 3, iclass 4, count 0 2006.173.14:51:38.94#ibcon#read 3, iclass 4, count 0 2006.173.14:51:38.94#ibcon#about to read 4, iclass 4, count 0 2006.173.14:51:38.94#ibcon#read 4, iclass 4, count 0 2006.173.14:51:38.94#ibcon#about to read 5, iclass 4, count 0 2006.173.14:51:38.94#ibcon#read 5, iclass 4, count 0 2006.173.14:51:38.94#ibcon#about to read 6, iclass 4, count 0 2006.173.14:51:38.94#ibcon#read 6, iclass 4, count 0 2006.173.14:51:38.94#ibcon#end of sib2, iclass 4, count 0 2006.173.14:51:38.94#ibcon#*mode == 0, iclass 4, count 0 2006.173.14:51:38.94#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.14:51:38.94#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.14:51:38.94#ibcon#*before write, iclass 4, count 0 2006.173.14:51:38.94#ibcon#enter sib2, iclass 4, count 0 2006.173.14:51:38.94#ibcon#flushed, iclass 4, count 0 2006.173.14:51:38.94#ibcon#about to write, iclass 4, count 0 2006.173.14:51:38.94#ibcon#wrote, iclass 4, count 0 2006.173.14:51:38.94#ibcon#about to read 3, iclass 4, count 0 2006.173.14:51:38.98#ibcon#read 3, iclass 4, count 0 2006.173.14:51:38.98#ibcon#about to read 4, iclass 4, count 0 2006.173.14:51:38.98#ibcon#read 4, iclass 4, count 0 2006.173.14:51:38.98#ibcon#about to read 5, iclass 4, count 0 2006.173.14:51:38.98#ibcon#read 5, iclass 4, count 0 2006.173.14:51:38.98#ibcon#about to read 6, iclass 4, count 0 2006.173.14:51:38.98#ibcon#read 6, iclass 4, count 0 2006.173.14:51:38.98#ibcon#end of sib2, iclass 4, count 0 2006.173.14:51:38.98#ibcon#*after write, iclass 4, count 0 2006.173.14:51:38.98#ibcon#*before return 0, iclass 4, count 0 2006.173.14:51:38.98#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.14:51:38.98#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.14:51:38.98#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.14:51:38.98#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.14:51:38.98$vck44/vb=1,4 2006.173.14:51:38.98#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.14:51:38.98#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.14:51:38.98#ibcon#ireg 11 cls_cnt 2 2006.173.14:51:38.98#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.14:51:38.98#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.14:51:38.98#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.14:51:38.98#ibcon#enter wrdev, iclass 6, count 2 2006.173.14:51:38.98#ibcon#first serial, iclass 6, count 2 2006.173.14:51:38.98#ibcon#enter sib2, iclass 6, count 2 2006.173.14:51:38.98#ibcon#flushed, iclass 6, count 2 2006.173.14:51:38.98#ibcon#about to write, iclass 6, count 2 2006.173.14:51:38.98#ibcon#wrote, iclass 6, count 2 2006.173.14:51:38.98#ibcon#about to read 3, iclass 6, count 2 2006.173.14:51:39.00#ibcon#read 3, iclass 6, count 2 2006.173.14:51:39.00#ibcon#about to read 4, iclass 6, count 2 2006.173.14:51:39.00#ibcon#read 4, iclass 6, count 2 2006.173.14:51:39.00#ibcon#about to read 5, iclass 6, count 2 2006.173.14:51:39.00#ibcon#read 5, iclass 6, count 2 2006.173.14:51:39.00#ibcon#about to read 6, iclass 6, count 2 2006.173.14:51:39.00#ibcon#read 6, iclass 6, count 2 2006.173.14:51:39.00#ibcon#end of sib2, iclass 6, count 2 2006.173.14:51:39.00#ibcon#*mode == 0, iclass 6, count 2 2006.173.14:51:39.00#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.14:51:39.00#ibcon#[27=AT01-04\r\n] 2006.173.14:51:39.00#ibcon#*before write, iclass 6, count 2 2006.173.14:51:39.00#ibcon#enter sib2, iclass 6, count 2 2006.173.14:51:39.00#ibcon#flushed, iclass 6, count 2 2006.173.14:51:39.00#ibcon#about to write, iclass 6, count 2 2006.173.14:51:39.00#ibcon#wrote, iclass 6, count 2 2006.173.14:51:39.00#ibcon#about to read 3, iclass 6, count 2 2006.173.14:51:39.03#ibcon#read 3, iclass 6, count 2 2006.173.14:51:39.03#ibcon#about to read 4, iclass 6, count 2 2006.173.14:51:39.03#ibcon#read 4, iclass 6, count 2 2006.173.14:51:39.03#ibcon#about to read 5, iclass 6, count 2 2006.173.14:51:39.03#ibcon#read 5, iclass 6, count 2 2006.173.14:51:39.03#ibcon#about to read 6, iclass 6, count 2 2006.173.14:51:39.03#ibcon#read 6, iclass 6, count 2 2006.173.14:51:39.03#ibcon#end of sib2, iclass 6, count 2 2006.173.14:51:39.03#ibcon#*after write, iclass 6, count 2 2006.173.14:51:39.03#ibcon#*before return 0, iclass 6, count 2 2006.173.14:51:39.03#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.14:51:39.03#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.14:51:39.03#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.14:51:39.03#ibcon#ireg 7 cls_cnt 0 2006.173.14:51:39.03#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.14:51:39.15#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.14:51:39.15#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.14:51:39.15#ibcon#enter wrdev, iclass 6, count 0 2006.173.14:51:39.15#ibcon#first serial, iclass 6, count 0 2006.173.14:51:39.15#ibcon#enter sib2, iclass 6, count 0 2006.173.14:51:39.15#ibcon#flushed, iclass 6, count 0 2006.173.14:51:39.15#ibcon#about to write, iclass 6, count 0 2006.173.14:51:39.15#ibcon#wrote, iclass 6, count 0 2006.173.14:51:39.15#ibcon#about to read 3, iclass 6, count 0 2006.173.14:51:39.17#ibcon#read 3, iclass 6, count 0 2006.173.14:51:39.17#ibcon#about to read 4, iclass 6, count 0 2006.173.14:51:39.17#ibcon#read 4, iclass 6, count 0 2006.173.14:51:39.17#ibcon#about to read 5, iclass 6, count 0 2006.173.14:51:39.17#ibcon#read 5, iclass 6, count 0 2006.173.14:51:39.17#ibcon#about to read 6, iclass 6, count 0 2006.173.14:51:39.17#ibcon#read 6, iclass 6, count 0 2006.173.14:51:39.17#ibcon#end of sib2, iclass 6, count 0 2006.173.14:51:39.17#ibcon#*mode == 0, iclass 6, count 0 2006.173.14:51:39.17#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.14:51:39.17#ibcon#[27=USB\r\n] 2006.173.14:51:39.17#ibcon#*before write, iclass 6, count 0 2006.173.14:51:39.17#ibcon#enter sib2, iclass 6, count 0 2006.173.14:51:39.17#ibcon#flushed, iclass 6, count 0 2006.173.14:51:39.17#ibcon#about to write, iclass 6, count 0 2006.173.14:51:39.17#ibcon#wrote, iclass 6, count 0 2006.173.14:51:39.17#ibcon#about to read 3, iclass 6, count 0 2006.173.14:51:39.20#ibcon#read 3, iclass 6, count 0 2006.173.14:51:39.20#ibcon#about to read 4, iclass 6, count 0 2006.173.14:51:39.20#ibcon#read 4, iclass 6, count 0 2006.173.14:51:39.20#ibcon#about to read 5, iclass 6, count 0 2006.173.14:51:39.20#ibcon#read 5, iclass 6, count 0 2006.173.14:51:39.20#ibcon#about to read 6, iclass 6, count 0 2006.173.14:51:39.20#ibcon#read 6, iclass 6, count 0 2006.173.14:51:39.20#ibcon#end of sib2, iclass 6, count 0 2006.173.14:51:39.20#ibcon#*after write, iclass 6, count 0 2006.173.14:51:39.20#ibcon#*before return 0, iclass 6, count 0 2006.173.14:51:39.20#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.14:51:39.20#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.14:51:39.20#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.14:51:39.20#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.14:51:39.20$vck44/vblo=2,634.99 2006.173.14:51:39.20#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.14:51:39.20#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.14:51:39.20#ibcon#ireg 17 cls_cnt 0 2006.173.14:51:39.20#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.14:51:39.20#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.14:51:39.20#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.14:51:39.20#ibcon#enter wrdev, iclass 10, count 0 2006.173.14:51:39.20#ibcon#first serial, iclass 10, count 0 2006.173.14:51:39.20#ibcon#enter sib2, iclass 10, count 0 2006.173.14:51:39.20#ibcon#flushed, iclass 10, count 0 2006.173.14:51:39.20#ibcon#about to write, iclass 10, count 0 2006.173.14:51:39.20#ibcon#wrote, iclass 10, count 0 2006.173.14:51:39.20#ibcon#about to read 3, iclass 10, count 0 2006.173.14:51:39.22#ibcon#read 3, iclass 10, count 0 2006.173.14:51:39.22#ibcon#about to read 4, iclass 10, count 0 2006.173.14:51:39.22#ibcon#read 4, iclass 10, count 0 2006.173.14:51:39.22#ibcon#about to read 5, iclass 10, count 0 2006.173.14:51:39.22#ibcon#read 5, iclass 10, count 0 2006.173.14:51:39.22#ibcon#about to read 6, iclass 10, count 0 2006.173.14:51:39.22#ibcon#read 6, iclass 10, count 0 2006.173.14:51:39.22#ibcon#end of sib2, iclass 10, count 0 2006.173.14:51:39.22#ibcon#*mode == 0, iclass 10, count 0 2006.173.14:51:39.22#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.14:51:39.22#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.14:51:39.22#ibcon#*before write, iclass 10, count 0 2006.173.14:51:39.22#ibcon#enter sib2, iclass 10, count 0 2006.173.14:51:39.22#ibcon#flushed, iclass 10, count 0 2006.173.14:51:39.22#ibcon#about to write, iclass 10, count 0 2006.173.14:51:39.22#ibcon#wrote, iclass 10, count 0 2006.173.14:51:39.22#ibcon#about to read 3, iclass 10, count 0 2006.173.14:51:39.26#ibcon#read 3, iclass 10, count 0 2006.173.14:51:39.26#ibcon#about to read 4, iclass 10, count 0 2006.173.14:51:39.26#ibcon#read 4, iclass 10, count 0 2006.173.14:51:39.26#ibcon#about to read 5, iclass 10, count 0 2006.173.14:51:39.26#ibcon#read 5, iclass 10, count 0 2006.173.14:51:39.26#ibcon#about to read 6, iclass 10, count 0 2006.173.14:51:39.26#ibcon#read 6, iclass 10, count 0 2006.173.14:51:39.26#ibcon#end of sib2, iclass 10, count 0 2006.173.14:51:39.26#ibcon#*after write, iclass 10, count 0 2006.173.14:51:39.26#ibcon#*before return 0, iclass 10, count 0 2006.173.14:51:39.26#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.14:51:39.26#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.14:51:39.26#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.14:51:39.26#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.14:51:39.26$vck44/vb=2,4 2006.173.14:51:39.26#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.14:51:39.26#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.14:51:39.26#ibcon#ireg 11 cls_cnt 2 2006.173.14:51:39.26#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.14:51:39.32#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.14:51:39.32#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.14:51:39.32#ibcon#enter wrdev, iclass 12, count 2 2006.173.14:51:39.32#ibcon#first serial, iclass 12, count 2 2006.173.14:51:39.32#ibcon#enter sib2, iclass 12, count 2 2006.173.14:51:39.32#ibcon#flushed, iclass 12, count 2 2006.173.14:51:39.32#ibcon#about to write, iclass 12, count 2 2006.173.14:51:39.32#ibcon#wrote, iclass 12, count 2 2006.173.14:51:39.32#ibcon#about to read 3, iclass 12, count 2 2006.173.14:51:39.34#ibcon#read 3, iclass 12, count 2 2006.173.14:51:39.34#ibcon#about to read 4, iclass 12, count 2 2006.173.14:51:39.34#ibcon#read 4, iclass 12, count 2 2006.173.14:51:39.34#ibcon#about to read 5, iclass 12, count 2 2006.173.14:51:39.34#ibcon#read 5, iclass 12, count 2 2006.173.14:51:39.34#ibcon#about to read 6, iclass 12, count 2 2006.173.14:51:39.34#ibcon#read 6, iclass 12, count 2 2006.173.14:51:39.34#ibcon#end of sib2, iclass 12, count 2 2006.173.14:51:39.34#ibcon#*mode == 0, iclass 12, count 2 2006.173.14:51:39.34#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.14:51:39.34#ibcon#[27=AT02-04\r\n] 2006.173.14:51:39.34#ibcon#*before write, iclass 12, count 2 2006.173.14:51:39.34#ibcon#enter sib2, iclass 12, count 2 2006.173.14:51:39.34#ibcon#flushed, iclass 12, count 2 2006.173.14:51:39.34#ibcon#about to write, iclass 12, count 2 2006.173.14:51:39.34#ibcon#wrote, iclass 12, count 2 2006.173.14:51:39.34#ibcon#about to read 3, iclass 12, count 2 2006.173.14:51:39.37#ibcon#read 3, iclass 12, count 2 2006.173.14:51:39.37#ibcon#about to read 4, iclass 12, count 2 2006.173.14:51:39.37#ibcon#read 4, iclass 12, count 2 2006.173.14:51:39.37#ibcon#about to read 5, iclass 12, count 2 2006.173.14:51:39.37#ibcon#read 5, iclass 12, count 2 2006.173.14:51:39.37#ibcon#about to read 6, iclass 12, count 2 2006.173.14:51:39.37#ibcon#read 6, iclass 12, count 2 2006.173.14:51:39.37#ibcon#end of sib2, iclass 12, count 2 2006.173.14:51:39.37#ibcon#*after write, iclass 12, count 2 2006.173.14:51:39.37#ibcon#*before return 0, iclass 12, count 2 2006.173.14:51:39.37#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.14:51:39.37#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.14:51:39.37#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.14:51:39.37#ibcon#ireg 7 cls_cnt 0 2006.173.14:51:39.37#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.14:51:39.49#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.14:51:39.49#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.14:51:39.49#ibcon#enter wrdev, iclass 12, count 0 2006.173.14:51:39.49#ibcon#first serial, iclass 12, count 0 2006.173.14:51:39.49#ibcon#enter sib2, iclass 12, count 0 2006.173.14:51:39.49#ibcon#flushed, iclass 12, count 0 2006.173.14:51:39.49#ibcon#about to write, iclass 12, count 0 2006.173.14:51:39.49#ibcon#wrote, iclass 12, count 0 2006.173.14:51:39.49#ibcon#about to read 3, iclass 12, count 0 2006.173.14:51:39.51#ibcon#read 3, iclass 12, count 0 2006.173.14:51:39.51#ibcon#about to read 4, iclass 12, count 0 2006.173.14:51:39.51#ibcon#read 4, iclass 12, count 0 2006.173.14:51:39.51#ibcon#about to read 5, iclass 12, count 0 2006.173.14:51:39.51#ibcon#read 5, iclass 12, count 0 2006.173.14:51:39.51#ibcon#about to read 6, iclass 12, count 0 2006.173.14:51:39.51#ibcon#read 6, iclass 12, count 0 2006.173.14:51:39.51#ibcon#end of sib2, iclass 12, count 0 2006.173.14:51:39.51#ibcon#*mode == 0, iclass 12, count 0 2006.173.14:51:39.51#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.14:51:39.51#ibcon#[27=USB\r\n] 2006.173.14:51:39.51#ibcon#*before write, iclass 12, count 0 2006.173.14:51:39.51#ibcon#enter sib2, iclass 12, count 0 2006.173.14:51:39.51#ibcon#flushed, iclass 12, count 0 2006.173.14:51:39.51#ibcon#about to write, iclass 12, count 0 2006.173.14:51:39.51#ibcon#wrote, iclass 12, count 0 2006.173.14:51:39.51#ibcon#about to read 3, iclass 12, count 0 2006.173.14:51:39.54#ibcon#read 3, iclass 12, count 0 2006.173.14:51:39.54#ibcon#about to read 4, iclass 12, count 0 2006.173.14:51:39.54#ibcon#read 4, iclass 12, count 0 2006.173.14:51:39.54#ibcon#about to read 5, iclass 12, count 0 2006.173.14:51:39.54#ibcon#read 5, iclass 12, count 0 2006.173.14:51:39.54#ibcon#about to read 6, iclass 12, count 0 2006.173.14:51:39.54#ibcon#read 6, iclass 12, count 0 2006.173.14:51:39.54#ibcon#end of sib2, iclass 12, count 0 2006.173.14:51:39.54#ibcon#*after write, iclass 12, count 0 2006.173.14:51:39.54#ibcon#*before return 0, iclass 12, count 0 2006.173.14:51:39.54#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.14:51:39.54#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.14:51:39.54#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.14:51:39.54#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.14:51:39.54$vck44/vblo=3,649.99 2006.173.14:51:39.54#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.14:51:39.54#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.14:51:39.54#ibcon#ireg 17 cls_cnt 0 2006.173.14:51:39.54#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.14:51:39.54#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.14:51:39.54#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.14:51:39.54#ibcon#enter wrdev, iclass 14, count 0 2006.173.14:51:39.54#ibcon#first serial, iclass 14, count 0 2006.173.14:51:39.54#ibcon#enter sib2, iclass 14, count 0 2006.173.14:51:39.54#ibcon#flushed, iclass 14, count 0 2006.173.14:51:39.54#ibcon#about to write, iclass 14, count 0 2006.173.14:51:39.54#ibcon#wrote, iclass 14, count 0 2006.173.14:51:39.54#ibcon#about to read 3, iclass 14, count 0 2006.173.14:51:39.56#ibcon#read 3, iclass 14, count 0 2006.173.14:51:39.56#ibcon#about to read 4, iclass 14, count 0 2006.173.14:51:39.56#ibcon#read 4, iclass 14, count 0 2006.173.14:51:39.56#ibcon#about to read 5, iclass 14, count 0 2006.173.14:51:39.56#ibcon#read 5, iclass 14, count 0 2006.173.14:51:39.56#ibcon#about to read 6, iclass 14, count 0 2006.173.14:51:39.56#ibcon#read 6, iclass 14, count 0 2006.173.14:51:39.56#ibcon#end of sib2, iclass 14, count 0 2006.173.14:51:39.56#ibcon#*mode == 0, iclass 14, count 0 2006.173.14:51:39.56#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.14:51:39.56#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.14:51:39.56#ibcon#*before write, iclass 14, count 0 2006.173.14:51:39.56#ibcon#enter sib2, iclass 14, count 0 2006.173.14:51:39.56#ibcon#flushed, iclass 14, count 0 2006.173.14:51:39.56#ibcon#about to write, iclass 14, count 0 2006.173.14:51:39.56#ibcon#wrote, iclass 14, count 0 2006.173.14:51:39.56#ibcon#about to read 3, iclass 14, count 0 2006.173.14:51:39.60#ibcon#read 3, iclass 14, count 0 2006.173.14:51:39.60#ibcon#about to read 4, iclass 14, count 0 2006.173.14:51:39.60#ibcon#read 4, iclass 14, count 0 2006.173.14:51:39.60#ibcon#about to read 5, iclass 14, count 0 2006.173.14:51:39.60#ibcon#read 5, iclass 14, count 0 2006.173.14:51:39.60#ibcon#about to read 6, iclass 14, count 0 2006.173.14:51:39.60#ibcon#read 6, iclass 14, count 0 2006.173.14:51:39.60#ibcon#end of sib2, iclass 14, count 0 2006.173.14:51:39.60#ibcon#*after write, iclass 14, count 0 2006.173.14:51:39.60#ibcon#*before return 0, iclass 14, count 0 2006.173.14:51:39.60#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.14:51:39.60#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.14:51:39.60#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.14:51:39.60#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.14:51:39.60$vck44/vb=3,4 2006.173.14:51:39.60#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.14:51:39.60#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.14:51:39.60#ibcon#ireg 11 cls_cnt 2 2006.173.14:51:39.60#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.14:51:39.66#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.14:51:39.66#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.14:51:39.66#ibcon#enter wrdev, iclass 16, count 2 2006.173.14:51:39.66#ibcon#first serial, iclass 16, count 2 2006.173.14:51:39.66#ibcon#enter sib2, iclass 16, count 2 2006.173.14:51:39.66#ibcon#flushed, iclass 16, count 2 2006.173.14:51:39.66#ibcon#about to write, iclass 16, count 2 2006.173.14:51:39.66#ibcon#wrote, iclass 16, count 2 2006.173.14:51:39.66#ibcon#about to read 3, iclass 16, count 2 2006.173.14:51:39.68#ibcon#read 3, iclass 16, count 2 2006.173.14:51:39.68#ibcon#about to read 4, iclass 16, count 2 2006.173.14:51:39.68#ibcon#read 4, iclass 16, count 2 2006.173.14:51:39.68#ibcon#about to read 5, iclass 16, count 2 2006.173.14:51:39.68#ibcon#read 5, iclass 16, count 2 2006.173.14:51:39.68#ibcon#about to read 6, iclass 16, count 2 2006.173.14:51:39.68#ibcon#read 6, iclass 16, count 2 2006.173.14:51:39.68#ibcon#end of sib2, iclass 16, count 2 2006.173.14:51:39.68#ibcon#*mode == 0, iclass 16, count 2 2006.173.14:51:39.68#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.14:51:39.68#ibcon#[27=AT03-04\r\n] 2006.173.14:51:39.68#ibcon#*before write, iclass 16, count 2 2006.173.14:51:39.68#ibcon#enter sib2, iclass 16, count 2 2006.173.14:51:39.68#ibcon#flushed, iclass 16, count 2 2006.173.14:51:39.68#ibcon#about to write, iclass 16, count 2 2006.173.14:51:39.68#ibcon#wrote, iclass 16, count 2 2006.173.14:51:39.68#ibcon#about to read 3, iclass 16, count 2 2006.173.14:51:39.71#ibcon#read 3, iclass 16, count 2 2006.173.14:51:39.71#ibcon#about to read 4, iclass 16, count 2 2006.173.14:51:39.71#ibcon#read 4, iclass 16, count 2 2006.173.14:51:39.71#ibcon#about to read 5, iclass 16, count 2 2006.173.14:51:39.71#ibcon#read 5, iclass 16, count 2 2006.173.14:51:39.71#ibcon#about to read 6, iclass 16, count 2 2006.173.14:51:39.71#ibcon#read 6, iclass 16, count 2 2006.173.14:51:39.71#ibcon#end of sib2, iclass 16, count 2 2006.173.14:51:39.71#ibcon#*after write, iclass 16, count 2 2006.173.14:51:39.71#ibcon#*before return 0, iclass 16, count 2 2006.173.14:51:39.71#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.14:51:39.71#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.14:51:39.71#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.14:51:39.71#ibcon#ireg 7 cls_cnt 0 2006.173.14:51:39.71#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.14:51:39.83#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.14:51:39.83#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.14:51:39.83#ibcon#enter wrdev, iclass 16, count 0 2006.173.14:51:39.83#ibcon#first serial, iclass 16, count 0 2006.173.14:51:39.83#ibcon#enter sib2, iclass 16, count 0 2006.173.14:51:39.83#ibcon#flushed, iclass 16, count 0 2006.173.14:51:39.83#ibcon#about to write, iclass 16, count 0 2006.173.14:51:39.83#ibcon#wrote, iclass 16, count 0 2006.173.14:51:39.83#ibcon#about to read 3, iclass 16, count 0 2006.173.14:51:39.85#ibcon#read 3, iclass 16, count 0 2006.173.14:51:39.85#ibcon#about to read 4, iclass 16, count 0 2006.173.14:51:39.85#ibcon#read 4, iclass 16, count 0 2006.173.14:51:39.85#ibcon#about to read 5, iclass 16, count 0 2006.173.14:51:39.85#ibcon#read 5, iclass 16, count 0 2006.173.14:51:39.85#ibcon#about to read 6, iclass 16, count 0 2006.173.14:51:39.85#ibcon#read 6, iclass 16, count 0 2006.173.14:51:39.85#ibcon#end of sib2, iclass 16, count 0 2006.173.14:51:39.85#ibcon#*mode == 0, iclass 16, count 0 2006.173.14:51:39.85#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.14:51:39.85#ibcon#[27=USB\r\n] 2006.173.14:51:39.85#ibcon#*before write, iclass 16, count 0 2006.173.14:51:39.85#ibcon#enter sib2, iclass 16, count 0 2006.173.14:51:39.85#ibcon#flushed, iclass 16, count 0 2006.173.14:51:39.85#ibcon#about to write, iclass 16, count 0 2006.173.14:51:39.85#ibcon#wrote, iclass 16, count 0 2006.173.14:51:39.85#ibcon#about to read 3, iclass 16, count 0 2006.173.14:51:39.88#ibcon#read 3, iclass 16, count 0 2006.173.14:51:39.88#ibcon#about to read 4, iclass 16, count 0 2006.173.14:51:39.88#ibcon#read 4, iclass 16, count 0 2006.173.14:51:39.88#ibcon#about to read 5, iclass 16, count 0 2006.173.14:51:39.88#ibcon#read 5, iclass 16, count 0 2006.173.14:51:39.88#ibcon#about to read 6, iclass 16, count 0 2006.173.14:51:39.88#ibcon#read 6, iclass 16, count 0 2006.173.14:51:39.88#ibcon#end of sib2, iclass 16, count 0 2006.173.14:51:39.88#ibcon#*after write, iclass 16, count 0 2006.173.14:51:39.88#ibcon#*before return 0, iclass 16, count 0 2006.173.14:51:39.88#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.14:51:39.88#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.14:51:39.88#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.14:51:39.88#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.14:51:39.88$vck44/vblo=4,679.99 2006.173.14:51:39.88#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.14:51:39.88#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.14:51:39.88#ibcon#ireg 17 cls_cnt 0 2006.173.14:51:39.88#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.14:51:39.88#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.14:51:39.88#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.14:51:39.88#ibcon#enter wrdev, iclass 18, count 0 2006.173.14:51:39.88#ibcon#first serial, iclass 18, count 0 2006.173.14:51:39.88#ibcon#enter sib2, iclass 18, count 0 2006.173.14:51:39.88#ibcon#flushed, iclass 18, count 0 2006.173.14:51:39.88#ibcon#about to write, iclass 18, count 0 2006.173.14:51:39.88#ibcon#wrote, iclass 18, count 0 2006.173.14:51:39.88#ibcon#about to read 3, iclass 18, count 0 2006.173.14:51:39.90#ibcon#read 3, iclass 18, count 0 2006.173.14:51:39.90#ibcon#about to read 4, iclass 18, count 0 2006.173.14:51:39.90#ibcon#read 4, iclass 18, count 0 2006.173.14:51:39.90#ibcon#about to read 5, iclass 18, count 0 2006.173.14:51:39.90#ibcon#read 5, iclass 18, count 0 2006.173.14:51:39.90#ibcon#about to read 6, iclass 18, count 0 2006.173.14:51:39.90#ibcon#read 6, iclass 18, count 0 2006.173.14:51:39.90#ibcon#end of sib2, iclass 18, count 0 2006.173.14:51:39.90#ibcon#*mode == 0, iclass 18, count 0 2006.173.14:51:39.90#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.14:51:39.90#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.14:51:39.90#ibcon#*before write, iclass 18, count 0 2006.173.14:51:39.90#ibcon#enter sib2, iclass 18, count 0 2006.173.14:51:39.90#ibcon#flushed, iclass 18, count 0 2006.173.14:51:39.90#ibcon#about to write, iclass 18, count 0 2006.173.14:51:39.90#ibcon#wrote, iclass 18, count 0 2006.173.14:51:39.90#ibcon#about to read 3, iclass 18, count 0 2006.173.14:51:39.94#ibcon#read 3, iclass 18, count 0 2006.173.14:51:39.94#ibcon#about to read 4, iclass 18, count 0 2006.173.14:51:39.94#ibcon#read 4, iclass 18, count 0 2006.173.14:51:39.94#ibcon#about to read 5, iclass 18, count 0 2006.173.14:51:39.94#ibcon#read 5, iclass 18, count 0 2006.173.14:51:39.94#ibcon#about to read 6, iclass 18, count 0 2006.173.14:51:39.94#ibcon#read 6, iclass 18, count 0 2006.173.14:51:39.94#ibcon#end of sib2, iclass 18, count 0 2006.173.14:51:39.94#ibcon#*after write, iclass 18, count 0 2006.173.14:51:39.94#ibcon#*before return 0, iclass 18, count 0 2006.173.14:51:39.94#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.14:51:39.94#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.14:51:39.94#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.14:51:39.94#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.14:51:39.94$vck44/vb=4,4 2006.173.14:51:39.94#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.14:51:39.94#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.14:51:39.94#ibcon#ireg 11 cls_cnt 2 2006.173.14:51:39.94#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.14:51:40.00#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.14:51:40.00#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.14:51:40.00#ibcon#enter wrdev, iclass 20, count 2 2006.173.14:51:40.00#ibcon#first serial, iclass 20, count 2 2006.173.14:51:40.00#ibcon#enter sib2, iclass 20, count 2 2006.173.14:51:40.00#ibcon#flushed, iclass 20, count 2 2006.173.14:51:40.00#ibcon#about to write, iclass 20, count 2 2006.173.14:51:40.00#ibcon#wrote, iclass 20, count 2 2006.173.14:51:40.00#ibcon#about to read 3, iclass 20, count 2 2006.173.14:51:40.02#ibcon#read 3, iclass 20, count 2 2006.173.14:51:40.02#ibcon#about to read 4, iclass 20, count 2 2006.173.14:51:40.02#ibcon#read 4, iclass 20, count 2 2006.173.14:51:40.02#ibcon#about to read 5, iclass 20, count 2 2006.173.14:51:40.02#ibcon#read 5, iclass 20, count 2 2006.173.14:51:40.02#ibcon#about to read 6, iclass 20, count 2 2006.173.14:51:40.02#ibcon#read 6, iclass 20, count 2 2006.173.14:51:40.02#ibcon#end of sib2, iclass 20, count 2 2006.173.14:51:40.02#ibcon#*mode == 0, iclass 20, count 2 2006.173.14:51:40.02#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.14:51:40.02#ibcon#[27=AT04-04\r\n] 2006.173.14:51:40.02#ibcon#*before write, iclass 20, count 2 2006.173.14:51:40.02#ibcon#enter sib2, iclass 20, count 2 2006.173.14:51:40.02#ibcon#flushed, iclass 20, count 2 2006.173.14:51:40.02#ibcon#about to write, iclass 20, count 2 2006.173.14:51:40.02#ibcon#wrote, iclass 20, count 2 2006.173.14:51:40.02#ibcon#about to read 3, iclass 20, count 2 2006.173.14:51:40.05#ibcon#read 3, iclass 20, count 2 2006.173.14:51:40.05#ibcon#about to read 4, iclass 20, count 2 2006.173.14:51:40.05#ibcon#read 4, iclass 20, count 2 2006.173.14:51:40.05#ibcon#about to read 5, iclass 20, count 2 2006.173.14:51:40.05#ibcon#read 5, iclass 20, count 2 2006.173.14:51:40.05#ibcon#about to read 6, iclass 20, count 2 2006.173.14:51:40.05#ibcon#read 6, iclass 20, count 2 2006.173.14:51:40.05#ibcon#end of sib2, iclass 20, count 2 2006.173.14:51:40.05#ibcon#*after write, iclass 20, count 2 2006.173.14:51:40.05#ibcon#*before return 0, iclass 20, count 2 2006.173.14:51:40.05#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.14:51:40.05#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.14:51:40.05#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.14:51:40.05#ibcon#ireg 7 cls_cnt 0 2006.173.14:51:40.05#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.14:51:40.17#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.14:51:40.17#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.14:51:40.17#ibcon#enter wrdev, iclass 20, count 0 2006.173.14:51:40.17#ibcon#first serial, iclass 20, count 0 2006.173.14:51:40.17#ibcon#enter sib2, iclass 20, count 0 2006.173.14:51:40.17#ibcon#flushed, iclass 20, count 0 2006.173.14:51:40.17#ibcon#about to write, iclass 20, count 0 2006.173.14:51:40.17#ibcon#wrote, iclass 20, count 0 2006.173.14:51:40.17#ibcon#about to read 3, iclass 20, count 0 2006.173.14:51:40.19#ibcon#read 3, iclass 20, count 0 2006.173.14:51:40.19#ibcon#about to read 4, iclass 20, count 0 2006.173.14:51:40.19#ibcon#read 4, iclass 20, count 0 2006.173.14:51:40.19#ibcon#about to read 5, iclass 20, count 0 2006.173.14:51:40.19#ibcon#read 5, iclass 20, count 0 2006.173.14:51:40.19#ibcon#about to read 6, iclass 20, count 0 2006.173.14:51:40.19#ibcon#read 6, iclass 20, count 0 2006.173.14:51:40.19#ibcon#end of sib2, iclass 20, count 0 2006.173.14:51:40.19#ibcon#*mode == 0, iclass 20, count 0 2006.173.14:51:40.19#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.14:51:40.19#ibcon#[27=USB\r\n] 2006.173.14:51:40.19#ibcon#*before write, iclass 20, count 0 2006.173.14:51:40.19#ibcon#enter sib2, iclass 20, count 0 2006.173.14:51:40.19#ibcon#flushed, iclass 20, count 0 2006.173.14:51:40.19#ibcon#about to write, iclass 20, count 0 2006.173.14:51:40.19#ibcon#wrote, iclass 20, count 0 2006.173.14:51:40.19#ibcon#about to read 3, iclass 20, count 0 2006.173.14:51:40.22#ibcon#read 3, iclass 20, count 0 2006.173.14:51:40.22#ibcon#about to read 4, iclass 20, count 0 2006.173.14:51:40.22#ibcon#read 4, iclass 20, count 0 2006.173.14:51:40.22#ibcon#about to read 5, iclass 20, count 0 2006.173.14:51:40.22#ibcon#read 5, iclass 20, count 0 2006.173.14:51:40.22#ibcon#about to read 6, iclass 20, count 0 2006.173.14:51:40.22#ibcon#read 6, iclass 20, count 0 2006.173.14:51:40.22#ibcon#end of sib2, iclass 20, count 0 2006.173.14:51:40.22#ibcon#*after write, iclass 20, count 0 2006.173.14:51:40.22#ibcon#*before return 0, iclass 20, count 0 2006.173.14:51:40.22#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.14:51:40.22#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.14:51:40.22#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.14:51:40.22#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.14:51:40.22$vck44/vblo=5,709.99 2006.173.14:51:40.22#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.14:51:40.22#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.14:51:40.22#ibcon#ireg 17 cls_cnt 0 2006.173.14:51:40.22#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.14:51:40.22#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.14:51:40.22#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.14:51:40.22#ibcon#enter wrdev, iclass 22, count 0 2006.173.14:51:40.22#ibcon#first serial, iclass 22, count 0 2006.173.14:51:40.22#ibcon#enter sib2, iclass 22, count 0 2006.173.14:51:40.22#ibcon#flushed, iclass 22, count 0 2006.173.14:51:40.22#ibcon#about to write, iclass 22, count 0 2006.173.14:51:40.22#ibcon#wrote, iclass 22, count 0 2006.173.14:51:40.22#ibcon#about to read 3, iclass 22, count 0 2006.173.14:51:40.24#ibcon#read 3, iclass 22, count 0 2006.173.14:51:40.24#ibcon#about to read 4, iclass 22, count 0 2006.173.14:51:40.24#ibcon#read 4, iclass 22, count 0 2006.173.14:51:40.24#ibcon#about to read 5, iclass 22, count 0 2006.173.14:51:40.24#ibcon#read 5, iclass 22, count 0 2006.173.14:51:40.24#ibcon#about to read 6, iclass 22, count 0 2006.173.14:51:40.24#ibcon#read 6, iclass 22, count 0 2006.173.14:51:40.24#ibcon#end of sib2, iclass 22, count 0 2006.173.14:51:40.24#ibcon#*mode == 0, iclass 22, count 0 2006.173.14:51:40.24#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.14:51:40.24#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.14:51:40.24#ibcon#*before write, iclass 22, count 0 2006.173.14:51:40.24#ibcon#enter sib2, iclass 22, count 0 2006.173.14:51:40.24#ibcon#flushed, iclass 22, count 0 2006.173.14:51:40.24#ibcon#about to write, iclass 22, count 0 2006.173.14:51:40.24#ibcon#wrote, iclass 22, count 0 2006.173.14:51:40.24#ibcon#about to read 3, iclass 22, count 0 2006.173.14:51:40.28#ibcon#read 3, iclass 22, count 0 2006.173.14:51:40.28#ibcon#about to read 4, iclass 22, count 0 2006.173.14:51:40.28#ibcon#read 4, iclass 22, count 0 2006.173.14:51:40.28#ibcon#about to read 5, iclass 22, count 0 2006.173.14:51:40.28#ibcon#read 5, iclass 22, count 0 2006.173.14:51:40.28#ibcon#about to read 6, iclass 22, count 0 2006.173.14:51:40.28#ibcon#read 6, iclass 22, count 0 2006.173.14:51:40.28#ibcon#end of sib2, iclass 22, count 0 2006.173.14:51:40.28#ibcon#*after write, iclass 22, count 0 2006.173.14:51:40.28#ibcon#*before return 0, iclass 22, count 0 2006.173.14:51:40.28#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.14:51:40.28#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.14:51:40.28#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.14:51:40.28#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.14:51:40.28$vck44/vb=5,4 2006.173.14:51:40.28#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.14:51:40.28#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.14:51:40.28#ibcon#ireg 11 cls_cnt 2 2006.173.14:51:40.28#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.14:51:40.34#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.14:51:40.34#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.14:51:40.34#ibcon#enter wrdev, iclass 24, count 2 2006.173.14:51:40.34#ibcon#first serial, iclass 24, count 2 2006.173.14:51:40.34#ibcon#enter sib2, iclass 24, count 2 2006.173.14:51:40.34#ibcon#flushed, iclass 24, count 2 2006.173.14:51:40.34#ibcon#about to write, iclass 24, count 2 2006.173.14:51:40.34#ibcon#wrote, iclass 24, count 2 2006.173.14:51:40.34#ibcon#about to read 3, iclass 24, count 2 2006.173.14:51:40.36#ibcon#read 3, iclass 24, count 2 2006.173.14:51:40.36#ibcon#about to read 4, iclass 24, count 2 2006.173.14:51:40.36#ibcon#read 4, iclass 24, count 2 2006.173.14:51:40.36#ibcon#about to read 5, iclass 24, count 2 2006.173.14:51:40.36#ibcon#read 5, iclass 24, count 2 2006.173.14:51:40.36#ibcon#about to read 6, iclass 24, count 2 2006.173.14:51:40.36#ibcon#read 6, iclass 24, count 2 2006.173.14:51:40.36#ibcon#end of sib2, iclass 24, count 2 2006.173.14:51:40.36#ibcon#*mode == 0, iclass 24, count 2 2006.173.14:51:40.36#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.14:51:40.36#ibcon#[27=AT05-04\r\n] 2006.173.14:51:40.36#ibcon#*before write, iclass 24, count 2 2006.173.14:51:40.36#ibcon#enter sib2, iclass 24, count 2 2006.173.14:51:40.36#ibcon#flushed, iclass 24, count 2 2006.173.14:51:40.36#ibcon#about to write, iclass 24, count 2 2006.173.14:51:40.36#ibcon#wrote, iclass 24, count 2 2006.173.14:51:40.36#ibcon#about to read 3, iclass 24, count 2 2006.173.14:51:40.39#ibcon#read 3, iclass 24, count 2 2006.173.14:51:40.39#ibcon#about to read 4, iclass 24, count 2 2006.173.14:51:40.39#ibcon#read 4, iclass 24, count 2 2006.173.14:51:40.39#ibcon#about to read 5, iclass 24, count 2 2006.173.14:51:40.39#ibcon#read 5, iclass 24, count 2 2006.173.14:51:40.39#ibcon#about to read 6, iclass 24, count 2 2006.173.14:51:40.39#ibcon#read 6, iclass 24, count 2 2006.173.14:51:40.39#ibcon#end of sib2, iclass 24, count 2 2006.173.14:51:40.39#ibcon#*after write, iclass 24, count 2 2006.173.14:51:40.39#ibcon#*before return 0, iclass 24, count 2 2006.173.14:51:40.39#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.14:51:40.39#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.14:51:40.39#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.14:51:40.39#ibcon#ireg 7 cls_cnt 0 2006.173.14:51:40.39#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.14:51:40.51#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.14:51:40.51#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.14:51:40.51#ibcon#enter wrdev, iclass 24, count 0 2006.173.14:51:40.51#ibcon#first serial, iclass 24, count 0 2006.173.14:51:40.51#ibcon#enter sib2, iclass 24, count 0 2006.173.14:51:40.51#ibcon#flushed, iclass 24, count 0 2006.173.14:51:40.51#ibcon#about to write, iclass 24, count 0 2006.173.14:51:40.51#ibcon#wrote, iclass 24, count 0 2006.173.14:51:40.51#ibcon#about to read 3, iclass 24, count 0 2006.173.14:51:40.53#ibcon#read 3, iclass 24, count 0 2006.173.14:51:40.53#ibcon#about to read 4, iclass 24, count 0 2006.173.14:51:40.53#ibcon#read 4, iclass 24, count 0 2006.173.14:51:40.53#ibcon#about to read 5, iclass 24, count 0 2006.173.14:51:40.53#ibcon#read 5, iclass 24, count 0 2006.173.14:51:40.53#ibcon#about to read 6, iclass 24, count 0 2006.173.14:51:40.53#ibcon#read 6, iclass 24, count 0 2006.173.14:51:40.53#ibcon#end of sib2, iclass 24, count 0 2006.173.14:51:40.53#ibcon#*mode == 0, iclass 24, count 0 2006.173.14:51:40.53#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.14:51:40.53#ibcon#[27=USB\r\n] 2006.173.14:51:40.53#ibcon#*before write, iclass 24, count 0 2006.173.14:51:40.53#ibcon#enter sib2, iclass 24, count 0 2006.173.14:51:40.53#ibcon#flushed, iclass 24, count 0 2006.173.14:51:40.53#ibcon#about to write, iclass 24, count 0 2006.173.14:51:40.53#ibcon#wrote, iclass 24, count 0 2006.173.14:51:40.53#ibcon#about to read 3, iclass 24, count 0 2006.173.14:51:40.56#ibcon#read 3, iclass 24, count 0 2006.173.14:51:40.56#ibcon#about to read 4, iclass 24, count 0 2006.173.14:51:40.56#ibcon#read 4, iclass 24, count 0 2006.173.14:51:40.56#ibcon#about to read 5, iclass 24, count 0 2006.173.14:51:40.56#ibcon#read 5, iclass 24, count 0 2006.173.14:51:40.56#ibcon#about to read 6, iclass 24, count 0 2006.173.14:51:40.56#ibcon#read 6, iclass 24, count 0 2006.173.14:51:40.56#ibcon#end of sib2, iclass 24, count 0 2006.173.14:51:40.56#ibcon#*after write, iclass 24, count 0 2006.173.14:51:40.56#ibcon#*before return 0, iclass 24, count 0 2006.173.14:51:40.56#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.14:51:40.56#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.14:51:40.56#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.14:51:40.56#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.14:51:40.56$vck44/vblo=6,719.99 2006.173.14:51:40.56#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.14:51:40.56#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.14:51:40.56#ibcon#ireg 17 cls_cnt 0 2006.173.14:51:40.56#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.14:51:40.56#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.14:51:40.56#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.14:51:40.56#ibcon#enter wrdev, iclass 26, count 0 2006.173.14:51:40.56#ibcon#first serial, iclass 26, count 0 2006.173.14:51:40.56#ibcon#enter sib2, iclass 26, count 0 2006.173.14:51:40.56#ibcon#flushed, iclass 26, count 0 2006.173.14:51:40.56#ibcon#about to write, iclass 26, count 0 2006.173.14:51:40.56#ibcon#wrote, iclass 26, count 0 2006.173.14:51:40.56#ibcon#about to read 3, iclass 26, count 0 2006.173.14:51:40.58#ibcon#read 3, iclass 26, count 0 2006.173.14:51:40.58#ibcon#about to read 4, iclass 26, count 0 2006.173.14:51:40.58#ibcon#read 4, iclass 26, count 0 2006.173.14:51:40.58#ibcon#about to read 5, iclass 26, count 0 2006.173.14:51:40.58#ibcon#read 5, iclass 26, count 0 2006.173.14:51:40.58#ibcon#about to read 6, iclass 26, count 0 2006.173.14:51:40.58#ibcon#read 6, iclass 26, count 0 2006.173.14:51:40.58#ibcon#end of sib2, iclass 26, count 0 2006.173.14:51:40.58#ibcon#*mode == 0, iclass 26, count 0 2006.173.14:51:40.58#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.14:51:40.58#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.14:51:40.58#ibcon#*before write, iclass 26, count 0 2006.173.14:51:40.58#ibcon#enter sib2, iclass 26, count 0 2006.173.14:51:40.58#ibcon#flushed, iclass 26, count 0 2006.173.14:51:40.58#ibcon#about to write, iclass 26, count 0 2006.173.14:51:40.58#ibcon#wrote, iclass 26, count 0 2006.173.14:51:40.58#ibcon#about to read 3, iclass 26, count 0 2006.173.14:51:40.62#ibcon#read 3, iclass 26, count 0 2006.173.14:51:40.62#ibcon#about to read 4, iclass 26, count 0 2006.173.14:51:40.62#ibcon#read 4, iclass 26, count 0 2006.173.14:51:40.62#ibcon#about to read 5, iclass 26, count 0 2006.173.14:51:40.62#ibcon#read 5, iclass 26, count 0 2006.173.14:51:40.62#ibcon#about to read 6, iclass 26, count 0 2006.173.14:51:40.62#ibcon#read 6, iclass 26, count 0 2006.173.14:51:40.62#ibcon#end of sib2, iclass 26, count 0 2006.173.14:51:40.62#ibcon#*after write, iclass 26, count 0 2006.173.14:51:40.62#ibcon#*before return 0, iclass 26, count 0 2006.173.14:51:40.62#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.14:51:40.62#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.14:51:40.62#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.14:51:40.62#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.14:51:40.62$vck44/vb=6,4 2006.173.14:51:40.62#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.14:51:40.62#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.14:51:40.62#ibcon#ireg 11 cls_cnt 2 2006.173.14:51:40.62#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.14:51:40.68#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.14:51:40.68#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.14:51:40.68#ibcon#enter wrdev, iclass 28, count 2 2006.173.14:51:40.68#ibcon#first serial, iclass 28, count 2 2006.173.14:51:40.68#ibcon#enter sib2, iclass 28, count 2 2006.173.14:51:40.68#ibcon#flushed, iclass 28, count 2 2006.173.14:51:40.68#ibcon#about to write, iclass 28, count 2 2006.173.14:51:40.68#ibcon#wrote, iclass 28, count 2 2006.173.14:51:40.68#ibcon#about to read 3, iclass 28, count 2 2006.173.14:51:40.70#ibcon#read 3, iclass 28, count 2 2006.173.14:51:40.70#ibcon#about to read 4, iclass 28, count 2 2006.173.14:51:40.70#ibcon#read 4, iclass 28, count 2 2006.173.14:51:40.70#ibcon#about to read 5, iclass 28, count 2 2006.173.14:51:40.70#ibcon#read 5, iclass 28, count 2 2006.173.14:51:40.70#ibcon#about to read 6, iclass 28, count 2 2006.173.14:51:40.70#ibcon#read 6, iclass 28, count 2 2006.173.14:51:40.70#ibcon#end of sib2, iclass 28, count 2 2006.173.14:51:40.70#ibcon#*mode == 0, iclass 28, count 2 2006.173.14:51:40.70#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.14:51:40.70#ibcon#[27=AT06-04\r\n] 2006.173.14:51:40.70#ibcon#*before write, iclass 28, count 2 2006.173.14:51:40.70#ibcon#enter sib2, iclass 28, count 2 2006.173.14:51:40.70#ibcon#flushed, iclass 28, count 2 2006.173.14:51:40.70#ibcon#about to write, iclass 28, count 2 2006.173.14:51:40.70#ibcon#wrote, iclass 28, count 2 2006.173.14:51:40.70#ibcon#about to read 3, iclass 28, count 2 2006.173.14:51:40.73#ibcon#read 3, iclass 28, count 2 2006.173.14:51:40.73#ibcon#about to read 4, iclass 28, count 2 2006.173.14:51:40.73#ibcon#read 4, iclass 28, count 2 2006.173.14:51:40.73#ibcon#about to read 5, iclass 28, count 2 2006.173.14:51:40.73#ibcon#read 5, iclass 28, count 2 2006.173.14:51:40.73#ibcon#about to read 6, iclass 28, count 2 2006.173.14:51:40.73#ibcon#read 6, iclass 28, count 2 2006.173.14:51:40.73#ibcon#end of sib2, iclass 28, count 2 2006.173.14:51:40.73#ibcon#*after write, iclass 28, count 2 2006.173.14:51:40.73#ibcon#*before return 0, iclass 28, count 2 2006.173.14:51:40.73#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.14:51:40.73#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.14:51:40.73#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.14:51:40.73#ibcon#ireg 7 cls_cnt 0 2006.173.14:51:40.73#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.14:51:40.85#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.14:51:40.85#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.14:51:40.85#ibcon#enter wrdev, iclass 28, count 0 2006.173.14:51:40.85#ibcon#first serial, iclass 28, count 0 2006.173.14:51:40.85#ibcon#enter sib2, iclass 28, count 0 2006.173.14:51:40.85#ibcon#flushed, iclass 28, count 0 2006.173.14:51:40.85#ibcon#about to write, iclass 28, count 0 2006.173.14:51:40.85#ibcon#wrote, iclass 28, count 0 2006.173.14:51:40.85#ibcon#about to read 3, iclass 28, count 0 2006.173.14:51:40.87#ibcon#read 3, iclass 28, count 0 2006.173.14:51:40.87#ibcon#about to read 4, iclass 28, count 0 2006.173.14:51:40.87#ibcon#read 4, iclass 28, count 0 2006.173.14:51:40.87#ibcon#about to read 5, iclass 28, count 0 2006.173.14:51:40.87#ibcon#read 5, iclass 28, count 0 2006.173.14:51:40.87#ibcon#about to read 6, iclass 28, count 0 2006.173.14:51:40.87#ibcon#read 6, iclass 28, count 0 2006.173.14:51:40.87#ibcon#end of sib2, iclass 28, count 0 2006.173.14:51:40.87#ibcon#*mode == 0, iclass 28, count 0 2006.173.14:51:40.87#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.14:51:40.87#ibcon#[27=USB\r\n] 2006.173.14:51:40.87#ibcon#*before write, iclass 28, count 0 2006.173.14:51:40.87#ibcon#enter sib2, iclass 28, count 0 2006.173.14:51:40.87#ibcon#flushed, iclass 28, count 0 2006.173.14:51:40.87#ibcon#about to write, iclass 28, count 0 2006.173.14:51:40.87#ibcon#wrote, iclass 28, count 0 2006.173.14:51:40.87#ibcon#about to read 3, iclass 28, count 0 2006.173.14:51:40.90#ibcon#read 3, iclass 28, count 0 2006.173.14:51:40.90#ibcon#about to read 4, iclass 28, count 0 2006.173.14:51:40.90#ibcon#read 4, iclass 28, count 0 2006.173.14:51:40.90#ibcon#about to read 5, iclass 28, count 0 2006.173.14:51:40.90#ibcon#read 5, iclass 28, count 0 2006.173.14:51:40.90#ibcon#about to read 6, iclass 28, count 0 2006.173.14:51:40.90#ibcon#read 6, iclass 28, count 0 2006.173.14:51:40.90#ibcon#end of sib2, iclass 28, count 0 2006.173.14:51:40.90#ibcon#*after write, iclass 28, count 0 2006.173.14:51:40.90#ibcon#*before return 0, iclass 28, count 0 2006.173.14:51:40.90#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.14:51:40.90#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.14:51:40.90#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.14:51:40.90#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.14:51:40.90$vck44/vblo=7,734.99 2006.173.14:51:40.90#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.14:51:40.90#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.14:51:40.90#ibcon#ireg 17 cls_cnt 0 2006.173.14:51:40.90#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.14:51:40.90#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.14:51:40.90#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.14:51:40.90#ibcon#enter wrdev, iclass 30, count 0 2006.173.14:51:40.90#ibcon#first serial, iclass 30, count 0 2006.173.14:51:40.90#ibcon#enter sib2, iclass 30, count 0 2006.173.14:51:40.90#ibcon#flushed, iclass 30, count 0 2006.173.14:51:40.90#ibcon#about to write, iclass 30, count 0 2006.173.14:51:40.90#ibcon#wrote, iclass 30, count 0 2006.173.14:51:40.90#ibcon#about to read 3, iclass 30, count 0 2006.173.14:51:40.92#ibcon#read 3, iclass 30, count 0 2006.173.14:51:40.92#ibcon#about to read 4, iclass 30, count 0 2006.173.14:51:40.92#ibcon#read 4, iclass 30, count 0 2006.173.14:51:40.92#ibcon#about to read 5, iclass 30, count 0 2006.173.14:51:40.92#ibcon#read 5, iclass 30, count 0 2006.173.14:51:40.92#ibcon#about to read 6, iclass 30, count 0 2006.173.14:51:40.92#ibcon#read 6, iclass 30, count 0 2006.173.14:51:40.92#ibcon#end of sib2, iclass 30, count 0 2006.173.14:51:40.92#ibcon#*mode == 0, iclass 30, count 0 2006.173.14:51:40.92#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.14:51:40.92#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.14:51:40.92#ibcon#*before write, iclass 30, count 0 2006.173.14:51:40.92#ibcon#enter sib2, iclass 30, count 0 2006.173.14:51:40.92#ibcon#flushed, iclass 30, count 0 2006.173.14:51:40.92#ibcon#about to write, iclass 30, count 0 2006.173.14:51:40.92#ibcon#wrote, iclass 30, count 0 2006.173.14:51:40.92#ibcon#about to read 3, iclass 30, count 0 2006.173.14:51:40.96#ibcon#read 3, iclass 30, count 0 2006.173.14:51:40.96#ibcon#about to read 4, iclass 30, count 0 2006.173.14:51:40.96#ibcon#read 4, iclass 30, count 0 2006.173.14:51:40.96#ibcon#about to read 5, iclass 30, count 0 2006.173.14:51:40.96#ibcon#read 5, iclass 30, count 0 2006.173.14:51:40.96#ibcon#about to read 6, iclass 30, count 0 2006.173.14:51:40.96#ibcon#read 6, iclass 30, count 0 2006.173.14:51:40.96#ibcon#end of sib2, iclass 30, count 0 2006.173.14:51:40.96#ibcon#*after write, iclass 30, count 0 2006.173.14:51:40.96#ibcon#*before return 0, iclass 30, count 0 2006.173.14:51:40.96#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.14:51:40.96#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.14:51:40.96#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.14:51:40.96#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.14:51:40.96$vck44/vb=7,4 2006.173.14:51:40.96#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.173.14:51:40.96#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.173.14:51:40.96#ibcon#ireg 11 cls_cnt 2 2006.173.14:51:40.96#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.14:51:41.02#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.14:51:41.02#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.14:51:41.02#ibcon#enter wrdev, iclass 32, count 2 2006.173.14:51:41.02#ibcon#first serial, iclass 32, count 2 2006.173.14:51:41.02#ibcon#enter sib2, iclass 32, count 2 2006.173.14:51:41.02#ibcon#flushed, iclass 32, count 2 2006.173.14:51:41.02#ibcon#about to write, iclass 32, count 2 2006.173.14:51:41.02#ibcon#wrote, iclass 32, count 2 2006.173.14:51:41.02#ibcon#about to read 3, iclass 32, count 2 2006.173.14:51:41.04#ibcon#read 3, iclass 32, count 2 2006.173.14:51:41.04#ibcon#about to read 4, iclass 32, count 2 2006.173.14:51:41.04#ibcon#read 4, iclass 32, count 2 2006.173.14:51:41.04#ibcon#about to read 5, iclass 32, count 2 2006.173.14:51:41.04#ibcon#read 5, iclass 32, count 2 2006.173.14:51:41.04#ibcon#about to read 6, iclass 32, count 2 2006.173.14:51:41.04#ibcon#read 6, iclass 32, count 2 2006.173.14:51:41.04#ibcon#end of sib2, iclass 32, count 2 2006.173.14:51:41.04#ibcon#*mode == 0, iclass 32, count 2 2006.173.14:51:41.04#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.173.14:51:41.04#ibcon#[27=AT07-04\r\n] 2006.173.14:51:41.04#ibcon#*before write, iclass 32, count 2 2006.173.14:51:41.04#ibcon#enter sib2, iclass 32, count 2 2006.173.14:51:41.04#ibcon#flushed, iclass 32, count 2 2006.173.14:51:41.04#ibcon#about to write, iclass 32, count 2 2006.173.14:51:41.04#ibcon#wrote, iclass 32, count 2 2006.173.14:51:41.04#ibcon#about to read 3, iclass 32, count 2 2006.173.14:51:41.07#ibcon#read 3, iclass 32, count 2 2006.173.14:51:41.07#ibcon#about to read 4, iclass 32, count 2 2006.173.14:51:41.07#ibcon#read 4, iclass 32, count 2 2006.173.14:51:41.07#ibcon#about to read 5, iclass 32, count 2 2006.173.14:51:41.07#ibcon#read 5, iclass 32, count 2 2006.173.14:51:41.07#ibcon#about to read 6, iclass 32, count 2 2006.173.14:51:41.07#ibcon#read 6, iclass 32, count 2 2006.173.14:51:41.07#ibcon#end of sib2, iclass 32, count 2 2006.173.14:51:41.07#ibcon#*after write, iclass 32, count 2 2006.173.14:51:41.07#ibcon#*before return 0, iclass 32, count 2 2006.173.14:51:41.07#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.14:51:41.07#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.173.14:51:41.07#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.173.14:51:41.07#ibcon#ireg 7 cls_cnt 0 2006.173.14:51:41.07#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.14:51:41.19#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.14:51:41.19#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.14:51:41.19#ibcon#enter wrdev, iclass 32, count 0 2006.173.14:51:41.19#ibcon#first serial, iclass 32, count 0 2006.173.14:51:41.19#ibcon#enter sib2, iclass 32, count 0 2006.173.14:51:41.19#ibcon#flushed, iclass 32, count 0 2006.173.14:51:41.19#ibcon#about to write, iclass 32, count 0 2006.173.14:51:41.19#ibcon#wrote, iclass 32, count 0 2006.173.14:51:41.19#ibcon#about to read 3, iclass 32, count 0 2006.173.14:51:41.21#ibcon#read 3, iclass 32, count 0 2006.173.14:51:41.21#ibcon#about to read 4, iclass 32, count 0 2006.173.14:51:41.21#ibcon#read 4, iclass 32, count 0 2006.173.14:51:41.21#ibcon#about to read 5, iclass 32, count 0 2006.173.14:51:41.21#ibcon#read 5, iclass 32, count 0 2006.173.14:51:41.21#ibcon#about to read 6, iclass 32, count 0 2006.173.14:51:41.21#ibcon#read 6, iclass 32, count 0 2006.173.14:51:41.21#ibcon#end of sib2, iclass 32, count 0 2006.173.14:51:41.21#ibcon#*mode == 0, iclass 32, count 0 2006.173.14:51:41.21#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.14:51:41.21#ibcon#[27=USB\r\n] 2006.173.14:51:41.21#ibcon#*before write, iclass 32, count 0 2006.173.14:51:41.21#ibcon#enter sib2, iclass 32, count 0 2006.173.14:51:41.21#ibcon#flushed, iclass 32, count 0 2006.173.14:51:41.21#ibcon#about to write, iclass 32, count 0 2006.173.14:51:41.21#ibcon#wrote, iclass 32, count 0 2006.173.14:51:41.21#ibcon#about to read 3, iclass 32, count 0 2006.173.14:51:41.24#ibcon#read 3, iclass 32, count 0 2006.173.14:51:41.24#ibcon#about to read 4, iclass 32, count 0 2006.173.14:51:41.24#ibcon#read 4, iclass 32, count 0 2006.173.14:51:41.24#ibcon#about to read 5, iclass 32, count 0 2006.173.14:51:41.24#ibcon#read 5, iclass 32, count 0 2006.173.14:51:41.24#ibcon#about to read 6, iclass 32, count 0 2006.173.14:51:41.24#ibcon#read 6, iclass 32, count 0 2006.173.14:51:41.24#ibcon#end of sib2, iclass 32, count 0 2006.173.14:51:41.24#ibcon#*after write, iclass 32, count 0 2006.173.14:51:41.24#ibcon#*before return 0, iclass 32, count 0 2006.173.14:51:41.24#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.14:51:41.24#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.173.14:51:41.24#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.14:51:41.24#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.14:51:41.24$vck44/vblo=8,744.99 2006.173.14:51:41.24#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.14:51:41.24#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.14:51:41.24#ibcon#ireg 17 cls_cnt 0 2006.173.14:51:41.24#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.14:51:41.24#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.14:51:41.24#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.14:51:41.24#ibcon#enter wrdev, iclass 34, count 0 2006.173.14:51:41.24#ibcon#first serial, iclass 34, count 0 2006.173.14:51:41.24#ibcon#enter sib2, iclass 34, count 0 2006.173.14:51:41.24#ibcon#flushed, iclass 34, count 0 2006.173.14:51:41.24#ibcon#about to write, iclass 34, count 0 2006.173.14:51:41.24#ibcon#wrote, iclass 34, count 0 2006.173.14:51:41.24#ibcon#about to read 3, iclass 34, count 0 2006.173.14:51:41.26#ibcon#read 3, iclass 34, count 0 2006.173.14:51:41.26#ibcon#about to read 4, iclass 34, count 0 2006.173.14:51:41.26#ibcon#read 4, iclass 34, count 0 2006.173.14:51:41.26#ibcon#about to read 5, iclass 34, count 0 2006.173.14:51:41.26#ibcon#read 5, iclass 34, count 0 2006.173.14:51:41.26#ibcon#about to read 6, iclass 34, count 0 2006.173.14:51:41.26#ibcon#read 6, iclass 34, count 0 2006.173.14:51:41.26#ibcon#end of sib2, iclass 34, count 0 2006.173.14:51:41.26#ibcon#*mode == 0, iclass 34, count 0 2006.173.14:51:41.26#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.14:51:41.26#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.14:51:41.26#ibcon#*before write, iclass 34, count 0 2006.173.14:51:41.26#ibcon#enter sib2, iclass 34, count 0 2006.173.14:51:41.26#ibcon#flushed, iclass 34, count 0 2006.173.14:51:41.26#ibcon#about to write, iclass 34, count 0 2006.173.14:51:41.26#ibcon#wrote, iclass 34, count 0 2006.173.14:51:41.26#ibcon#about to read 3, iclass 34, count 0 2006.173.14:51:41.30#ibcon#read 3, iclass 34, count 0 2006.173.14:51:41.30#ibcon#about to read 4, iclass 34, count 0 2006.173.14:51:41.30#ibcon#read 4, iclass 34, count 0 2006.173.14:51:41.30#ibcon#about to read 5, iclass 34, count 0 2006.173.14:51:41.30#ibcon#read 5, iclass 34, count 0 2006.173.14:51:41.30#ibcon#about to read 6, iclass 34, count 0 2006.173.14:51:41.30#ibcon#read 6, iclass 34, count 0 2006.173.14:51:41.30#ibcon#end of sib2, iclass 34, count 0 2006.173.14:51:41.30#ibcon#*after write, iclass 34, count 0 2006.173.14:51:41.30#ibcon#*before return 0, iclass 34, count 0 2006.173.14:51:41.30#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.14:51:41.30#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.14:51:41.30#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.14:51:41.30#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.14:51:41.30$vck44/vb=8,4 2006.173.14:51:41.30#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.14:51:41.30#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.14:51:41.30#ibcon#ireg 11 cls_cnt 2 2006.173.14:51:41.30#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.14:51:41.36#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.14:51:41.36#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.14:51:41.36#ibcon#enter wrdev, iclass 36, count 2 2006.173.14:51:41.36#ibcon#first serial, iclass 36, count 2 2006.173.14:51:41.36#ibcon#enter sib2, iclass 36, count 2 2006.173.14:51:41.36#ibcon#flushed, iclass 36, count 2 2006.173.14:51:41.36#ibcon#about to write, iclass 36, count 2 2006.173.14:51:41.36#ibcon#wrote, iclass 36, count 2 2006.173.14:51:41.36#ibcon#about to read 3, iclass 36, count 2 2006.173.14:51:41.38#ibcon#read 3, iclass 36, count 2 2006.173.14:51:41.38#ibcon#about to read 4, iclass 36, count 2 2006.173.14:51:41.38#ibcon#read 4, iclass 36, count 2 2006.173.14:51:41.38#ibcon#about to read 5, iclass 36, count 2 2006.173.14:51:41.38#ibcon#read 5, iclass 36, count 2 2006.173.14:51:41.38#ibcon#about to read 6, iclass 36, count 2 2006.173.14:51:41.38#ibcon#read 6, iclass 36, count 2 2006.173.14:51:41.38#ibcon#end of sib2, iclass 36, count 2 2006.173.14:51:41.38#ibcon#*mode == 0, iclass 36, count 2 2006.173.14:51:41.38#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.14:51:41.38#ibcon#[27=AT08-04\r\n] 2006.173.14:51:41.38#ibcon#*before write, iclass 36, count 2 2006.173.14:51:41.38#ibcon#enter sib2, iclass 36, count 2 2006.173.14:51:41.38#ibcon#flushed, iclass 36, count 2 2006.173.14:51:41.38#ibcon#about to write, iclass 36, count 2 2006.173.14:51:41.38#ibcon#wrote, iclass 36, count 2 2006.173.14:51:41.38#ibcon#about to read 3, iclass 36, count 2 2006.173.14:51:41.41#ibcon#read 3, iclass 36, count 2 2006.173.14:51:41.41#ibcon#about to read 4, iclass 36, count 2 2006.173.14:51:41.41#ibcon#read 4, iclass 36, count 2 2006.173.14:51:41.41#ibcon#about to read 5, iclass 36, count 2 2006.173.14:51:41.41#ibcon#read 5, iclass 36, count 2 2006.173.14:51:41.41#ibcon#about to read 6, iclass 36, count 2 2006.173.14:51:41.41#ibcon#read 6, iclass 36, count 2 2006.173.14:51:41.41#ibcon#end of sib2, iclass 36, count 2 2006.173.14:51:41.41#ibcon#*after write, iclass 36, count 2 2006.173.14:51:41.41#ibcon#*before return 0, iclass 36, count 2 2006.173.14:51:41.41#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.14:51:41.41#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.14:51:41.41#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.14:51:41.41#ibcon#ireg 7 cls_cnt 0 2006.173.14:51:41.41#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.14:51:41.53#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.14:51:41.53#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.14:51:41.53#ibcon#enter wrdev, iclass 36, count 0 2006.173.14:51:41.53#ibcon#first serial, iclass 36, count 0 2006.173.14:51:41.53#ibcon#enter sib2, iclass 36, count 0 2006.173.14:51:41.53#ibcon#flushed, iclass 36, count 0 2006.173.14:51:41.53#ibcon#about to write, iclass 36, count 0 2006.173.14:51:41.53#ibcon#wrote, iclass 36, count 0 2006.173.14:51:41.53#ibcon#about to read 3, iclass 36, count 0 2006.173.14:51:41.55#ibcon#read 3, iclass 36, count 0 2006.173.14:51:41.55#ibcon#about to read 4, iclass 36, count 0 2006.173.14:51:41.55#ibcon#read 4, iclass 36, count 0 2006.173.14:51:41.55#ibcon#about to read 5, iclass 36, count 0 2006.173.14:51:41.55#ibcon#read 5, iclass 36, count 0 2006.173.14:51:41.55#ibcon#about to read 6, iclass 36, count 0 2006.173.14:51:41.55#ibcon#read 6, iclass 36, count 0 2006.173.14:51:41.55#ibcon#end of sib2, iclass 36, count 0 2006.173.14:51:41.55#ibcon#*mode == 0, iclass 36, count 0 2006.173.14:51:41.55#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.14:51:41.55#ibcon#[27=USB\r\n] 2006.173.14:51:41.55#ibcon#*before write, iclass 36, count 0 2006.173.14:51:41.55#ibcon#enter sib2, iclass 36, count 0 2006.173.14:51:41.55#ibcon#flushed, iclass 36, count 0 2006.173.14:51:41.55#ibcon#about to write, iclass 36, count 0 2006.173.14:51:41.55#ibcon#wrote, iclass 36, count 0 2006.173.14:51:41.55#ibcon#about to read 3, iclass 36, count 0 2006.173.14:51:41.58#ibcon#read 3, iclass 36, count 0 2006.173.14:51:41.58#ibcon#about to read 4, iclass 36, count 0 2006.173.14:51:41.58#ibcon#read 4, iclass 36, count 0 2006.173.14:51:41.58#ibcon#about to read 5, iclass 36, count 0 2006.173.14:51:41.58#ibcon#read 5, iclass 36, count 0 2006.173.14:51:41.58#ibcon#about to read 6, iclass 36, count 0 2006.173.14:51:41.58#ibcon#read 6, iclass 36, count 0 2006.173.14:51:41.58#ibcon#end of sib2, iclass 36, count 0 2006.173.14:51:41.58#ibcon#*after write, iclass 36, count 0 2006.173.14:51:41.58#ibcon#*before return 0, iclass 36, count 0 2006.173.14:51:41.58#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.14:51:41.58#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.14:51:41.58#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.14:51:41.58#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.14:51:41.58$vck44/vabw=wide 2006.173.14:51:41.58#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.14:51:41.58#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.14:51:41.58#ibcon#ireg 8 cls_cnt 0 2006.173.14:51:41.58#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.14:51:41.58#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.14:51:41.58#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.14:51:41.58#ibcon#enter wrdev, iclass 38, count 0 2006.173.14:51:41.58#ibcon#first serial, iclass 38, count 0 2006.173.14:51:41.58#ibcon#enter sib2, iclass 38, count 0 2006.173.14:51:41.58#ibcon#flushed, iclass 38, count 0 2006.173.14:51:41.58#ibcon#about to write, iclass 38, count 0 2006.173.14:51:41.58#ibcon#wrote, iclass 38, count 0 2006.173.14:51:41.58#ibcon#about to read 3, iclass 38, count 0 2006.173.14:51:41.60#ibcon#read 3, iclass 38, count 0 2006.173.14:51:41.60#ibcon#about to read 4, iclass 38, count 0 2006.173.14:51:41.60#ibcon#read 4, iclass 38, count 0 2006.173.14:51:41.60#ibcon#about to read 5, iclass 38, count 0 2006.173.14:51:41.60#ibcon#read 5, iclass 38, count 0 2006.173.14:51:41.60#ibcon#about to read 6, iclass 38, count 0 2006.173.14:51:41.60#ibcon#read 6, iclass 38, count 0 2006.173.14:51:41.60#ibcon#end of sib2, iclass 38, count 0 2006.173.14:51:41.60#ibcon#*mode == 0, iclass 38, count 0 2006.173.14:51:41.60#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.14:51:41.60#ibcon#[25=BW32\r\n] 2006.173.14:51:41.60#ibcon#*before write, iclass 38, count 0 2006.173.14:51:41.60#ibcon#enter sib2, iclass 38, count 0 2006.173.14:51:41.60#ibcon#flushed, iclass 38, count 0 2006.173.14:51:41.60#ibcon#about to write, iclass 38, count 0 2006.173.14:51:41.60#ibcon#wrote, iclass 38, count 0 2006.173.14:51:41.60#ibcon#about to read 3, iclass 38, count 0 2006.173.14:51:41.63#ibcon#read 3, iclass 38, count 0 2006.173.14:51:41.63#ibcon#about to read 4, iclass 38, count 0 2006.173.14:51:41.63#ibcon#read 4, iclass 38, count 0 2006.173.14:51:41.63#ibcon#about to read 5, iclass 38, count 0 2006.173.14:51:41.63#ibcon#read 5, iclass 38, count 0 2006.173.14:51:41.63#ibcon#about to read 6, iclass 38, count 0 2006.173.14:51:41.63#ibcon#read 6, iclass 38, count 0 2006.173.14:51:41.63#ibcon#end of sib2, iclass 38, count 0 2006.173.14:51:41.63#ibcon#*after write, iclass 38, count 0 2006.173.14:51:41.63#ibcon#*before return 0, iclass 38, count 0 2006.173.14:51:41.63#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.14:51:41.63#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.14:51:41.63#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.14:51:41.63#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.14:51:41.63$vck44/vbbw=wide 2006.173.14:51:41.63#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.14:51:41.63#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.14:51:41.63#ibcon#ireg 8 cls_cnt 0 2006.173.14:51:41.63#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.14:51:41.70#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.14:51:41.70#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.14:51:41.70#ibcon#enter wrdev, iclass 40, count 0 2006.173.14:51:41.70#ibcon#first serial, iclass 40, count 0 2006.173.14:51:41.70#ibcon#enter sib2, iclass 40, count 0 2006.173.14:51:41.70#ibcon#flushed, iclass 40, count 0 2006.173.14:51:41.70#ibcon#about to write, iclass 40, count 0 2006.173.14:51:41.70#ibcon#wrote, iclass 40, count 0 2006.173.14:51:41.70#ibcon#about to read 3, iclass 40, count 0 2006.173.14:51:41.72#ibcon#read 3, iclass 40, count 0 2006.173.14:51:41.72#ibcon#about to read 4, iclass 40, count 0 2006.173.14:51:41.72#ibcon#read 4, iclass 40, count 0 2006.173.14:51:41.72#ibcon#about to read 5, iclass 40, count 0 2006.173.14:51:41.72#ibcon#read 5, iclass 40, count 0 2006.173.14:51:41.72#ibcon#about to read 6, iclass 40, count 0 2006.173.14:51:41.72#ibcon#read 6, iclass 40, count 0 2006.173.14:51:41.72#ibcon#end of sib2, iclass 40, count 0 2006.173.14:51:41.72#ibcon#*mode == 0, iclass 40, count 0 2006.173.14:51:41.72#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.14:51:41.72#ibcon#[27=BW32\r\n] 2006.173.14:51:41.72#ibcon#*before write, iclass 40, count 0 2006.173.14:51:41.72#ibcon#enter sib2, iclass 40, count 0 2006.173.14:51:41.72#ibcon#flushed, iclass 40, count 0 2006.173.14:51:41.72#ibcon#about to write, iclass 40, count 0 2006.173.14:51:41.72#ibcon#wrote, iclass 40, count 0 2006.173.14:51:41.72#ibcon#about to read 3, iclass 40, count 0 2006.173.14:51:41.75#ibcon#read 3, iclass 40, count 0 2006.173.14:51:41.75#ibcon#about to read 4, iclass 40, count 0 2006.173.14:51:41.75#ibcon#read 4, iclass 40, count 0 2006.173.14:51:41.75#ibcon#about to read 5, iclass 40, count 0 2006.173.14:51:41.75#ibcon#read 5, iclass 40, count 0 2006.173.14:51:41.75#ibcon#about to read 6, iclass 40, count 0 2006.173.14:51:41.75#ibcon#read 6, iclass 40, count 0 2006.173.14:51:41.75#ibcon#end of sib2, iclass 40, count 0 2006.173.14:51:41.75#ibcon#*after write, iclass 40, count 0 2006.173.14:51:41.75#ibcon#*before return 0, iclass 40, count 0 2006.173.14:51:41.75#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.14:51:41.75#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.14:51:41.75#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.14:51:41.75#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.14:51:41.75$setupk4/ifdk4 2006.173.14:51:41.75$ifdk4/lo= 2006.173.14:51:41.75$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.14:51:41.75$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.14:51:41.76$ifdk4/patch= 2006.173.14:51:41.76$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.14:51:41.76$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.14:51:41.76$setupk4/!*+20s 2006.173.14:51:45.02#abcon#<5=/02 1.0 2.4 20.861001003.6\r\n> 2006.173.14:51:45.04#abcon#{5=INTERFACE CLEAR} 2006.173.14:51:45.10#abcon#[5=S1D000X0/0*\r\n] 2006.173.14:51:55.19#abcon#<5=/02 1.0 2.4 20.861001003.6\r\n> 2006.173.14:51:55.21#abcon#{5=INTERFACE CLEAR} 2006.173.14:51:55.27#abcon#[5=S1D000X0/0*\r\n] 2006.173.14:51:56.27$setupk4/"tpicd 2006.173.14:51:56.27$setupk4/echo=off 2006.173.14:51:56.27$setupk4/xlog=off 2006.173.14:51:56.27:!2006.173.14:55:32 2006.173.14:52:00.14#trakl#Source acquired 2006.173.14:52:01.14#flagr#flagr/antenna,acquired 2006.173.14:55:32.00:preob 2006.173.14:55:32.14/onsource/TRACKING 2006.173.14:55:32.14:!2006.173.14:55:42 2006.173.14:55:42.00:"tape 2006.173.14:55:42.00:"st=record 2006.173.14:55:42.00:data_valid=on 2006.173.14:55:42.00:midob 2006.173.14:55:43.14/onsource/TRACKING 2006.173.14:55:43.14/wx/20.89,1003.6,100 2006.173.14:55:43.28/cable/+6.5072E-03 2006.173.14:55:44.37/va/01,07,usb,yes,39,42 2006.173.14:55:44.37/va/02,06,usb,yes,38,39 2006.173.14:55:44.37/va/03,05,usb,yes,49,51 2006.173.14:55:44.37/va/04,06,usb,yes,39,41 2006.173.14:55:44.37/va/05,04,usb,yes,31,32 2006.173.14:55:44.37/va/06,03,usb,yes,43,43 2006.173.14:55:44.37/va/07,04,usb,yes,35,36 2006.173.14:55:44.37/va/08,04,usb,yes,30,36 2006.173.14:55:44.60/valo/01,524.99,yes,locked 2006.173.14:55:44.60/valo/02,534.99,yes,locked 2006.173.14:55:44.60/valo/03,564.99,yes,locked 2006.173.14:55:44.60/valo/04,624.99,yes,locked 2006.173.14:55:44.60/valo/05,734.99,yes,locked 2006.173.14:55:44.60/valo/06,814.99,yes,locked 2006.173.14:55:44.60/valo/07,864.99,yes,locked 2006.173.14:55:44.60/valo/08,884.99,yes,locked 2006.173.14:55:45.69/vb/01,04,usb,yes,29,27 2006.173.14:55:45.69/vb/02,04,usb,yes,31,31 2006.173.14:55:45.69/vb/03,04,usb,yes,28,31 2006.173.14:55:45.69/vb/04,04,usb,yes,32,31 2006.173.14:55:45.69/vb/05,04,usb,yes,25,27 2006.173.14:55:45.69/vb/06,04,usb,yes,29,26 2006.173.14:55:45.69/vb/07,04,usb,yes,29,29 2006.173.14:55:45.69/vb/08,04,usb,yes,27,30 2006.173.14:55:45.92/vblo/01,629.99,yes,locked 2006.173.14:55:45.92/vblo/02,634.99,yes,locked 2006.173.14:55:45.92/vblo/03,649.99,yes,locked 2006.173.14:55:45.92/vblo/04,679.99,yes,locked 2006.173.14:55:45.92/vblo/05,709.99,yes,locked 2006.173.14:55:45.92/vblo/06,719.99,yes,locked 2006.173.14:55:45.92/vblo/07,734.99,yes,locked 2006.173.14:55:45.92/vblo/08,744.99,yes,locked 2006.173.14:55:46.07/vabw/8 2006.173.14:55:46.22/vbbw/8 2006.173.14:55:46.32/xfe/off,on,15.2 2006.173.14:55:46.70/ifatt/23,28,28,28 2006.173.14:55:47.07/fmout-gps/S +3.88E-07 2006.173.14:55:47.11:!2006.173.14:57:02 2006.173.14:57:02.01:data_valid=off 2006.173.14:57:02.02:"et 2006.173.14:57:02.02:!+3s 2006.173.14:57:05.03:"tape 2006.173.14:57:05.04:postob 2006.173.14:57:05.09/cable/+6.5072E-03 2006.173.14:57:05.10/wx/20.90,1003.5,100 2006.173.14:57:05.15/fmout-gps/S +3.90E-07 2006.173.14:57:05.16:scan_name=173-1500,jd0606,40 2006.173.14:57:05.16:source=1741-038,174358.86,-035004.6,2000.0,cw 2006.173.14:57:06.14#flagr#flagr/antenna,new-source 2006.173.14:57:06.15:checkk5 2006.173.14:57:06.54/chk_autoobs//k5ts1/ autoobs is running! 2006.173.14:57:06.94/chk_autoobs//k5ts2/ autoobs is running! 2006.173.14:57:07.34/chk_autoobs//k5ts3/ autoobs is running! 2006.173.14:57:07.75/chk_autoobs//k5ts4/ autoobs is running! 2006.173.14:57:08.13/chk_obsdata//k5ts1/T1731455??a.dat file size is correct (nominal:320MB, actual:316MB). 2006.173.14:57:08.52/chk_obsdata//k5ts2/T1731455??b.dat file size is correct (nominal:320MB, actual:316MB). 2006.173.14:57:08.95/chk_obsdata//k5ts3/T1731455??c.dat file size is correct (nominal:320MB, actual:316MB). 2006.173.14:57:09.34/chk_obsdata//k5ts4/T1731455??d.dat file size is correct (nominal:320MB, actual:316MB). 2006.173.14:57:10.06/k5log//k5ts1_log_newline 2006.173.14:57:10.77/k5log//k5ts2_log_newline 2006.173.14:57:11.49/k5log//k5ts3_log_newline 2006.173.14:57:12.20/k5log//k5ts4_log_newline 2006.173.14:57:12.22/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.14:57:12.22:setupk4=1 2006.173.14:57:12.22$setupk4/echo=on 2006.173.14:57:12.22$setupk4/pcalon 2006.173.14:57:12.22$pcalon/"no phase cal control is implemented here 2006.173.14:57:12.22$setupk4/"tpicd=stop 2006.173.14:57:12.22$setupk4/"rec=synch_on 2006.173.14:57:12.22$setupk4/"rec_mode=128 2006.173.14:57:12.22$setupk4/!* 2006.173.14:57:12.22$setupk4/recpk4 2006.173.14:57:12.22$recpk4/recpatch= 2006.173.14:57:12.23$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.14:57:12.23$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.14:57:12.23$setupk4/vck44 2006.173.14:57:12.23$vck44/valo=1,524.99 2006.173.14:57:12.23#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.14:57:12.23#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.14:57:12.23#ibcon#ireg 17 cls_cnt 0 2006.173.14:57:12.23#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.14:57:12.23#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.14:57:12.23#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.14:57:12.23#ibcon#enter wrdev, iclass 33, count 0 2006.173.14:57:12.23#ibcon#first serial, iclass 33, count 0 2006.173.14:57:12.23#ibcon#enter sib2, iclass 33, count 0 2006.173.14:57:12.23#ibcon#flushed, iclass 33, count 0 2006.173.14:57:12.23#ibcon#about to write, iclass 33, count 0 2006.173.14:57:12.23#ibcon#wrote, iclass 33, count 0 2006.173.14:57:12.23#ibcon#about to read 3, iclass 33, count 0 2006.173.14:57:12.24#ibcon#read 3, iclass 33, count 0 2006.173.14:57:12.24#ibcon#about to read 4, iclass 33, count 0 2006.173.14:57:12.24#ibcon#read 4, iclass 33, count 0 2006.173.14:57:12.24#ibcon#about to read 5, iclass 33, count 0 2006.173.14:57:12.24#ibcon#read 5, iclass 33, count 0 2006.173.14:57:12.24#ibcon#about to read 6, iclass 33, count 0 2006.173.14:57:12.24#ibcon#read 6, iclass 33, count 0 2006.173.14:57:12.24#ibcon#end of sib2, iclass 33, count 0 2006.173.14:57:12.24#ibcon#*mode == 0, iclass 33, count 0 2006.173.14:57:12.24#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.14:57:12.24#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.14:57:12.24#ibcon#*before write, iclass 33, count 0 2006.173.14:57:12.24#ibcon#enter sib2, iclass 33, count 0 2006.173.14:57:12.24#ibcon#flushed, iclass 33, count 0 2006.173.14:57:12.24#ibcon#about to write, iclass 33, count 0 2006.173.14:57:12.24#ibcon#wrote, iclass 33, count 0 2006.173.14:57:12.24#ibcon#about to read 3, iclass 33, count 0 2006.173.14:57:12.29#ibcon#read 3, iclass 33, count 0 2006.173.14:57:12.29#ibcon#about to read 4, iclass 33, count 0 2006.173.14:57:12.29#ibcon#read 4, iclass 33, count 0 2006.173.14:57:12.29#ibcon#about to read 5, iclass 33, count 0 2006.173.14:57:12.29#ibcon#read 5, iclass 33, count 0 2006.173.14:57:12.29#ibcon#about to read 6, iclass 33, count 0 2006.173.14:57:12.29#ibcon#read 6, iclass 33, count 0 2006.173.14:57:12.29#ibcon#end of sib2, iclass 33, count 0 2006.173.14:57:12.29#ibcon#*after write, iclass 33, count 0 2006.173.14:57:12.29#ibcon#*before return 0, iclass 33, count 0 2006.173.14:57:12.29#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.14:57:12.29#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.14:57:12.29#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.14:57:12.29#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.14:57:12.29$vck44/va=1,7 2006.173.14:57:12.29#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.14:57:12.29#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.14:57:12.29#ibcon#ireg 11 cls_cnt 2 2006.173.14:57:12.29#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.14:57:12.29#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.14:57:12.29#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.14:57:12.29#ibcon#enter wrdev, iclass 35, count 2 2006.173.14:57:12.29#ibcon#first serial, iclass 35, count 2 2006.173.14:57:12.29#ibcon#enter sib2, iclass 35, count 2 2006.173.14:57:12.29#ibcon#flushed, iclass 35, count 2 2006.173.14:57:12.29#ibcon#about to write, iclass 35, count 2 2006.173.14:57:12.29#ibcon#wrote, iclass 35, count 2 2006.173.14:57:12.29#ibcon#about to read 3, iclass 35, count 2 2006.173.14:57:12.31#ibcon#read 3, iclass 35, count 2 2006.173.14:57:12.31#ibcon#about to read 4, iclass 35, count 2 2006.173.14:57:12.31#ibcon#read 4, iclass 35, count 2 2006.173.14:57:12.31#ibcon#about to read 5, iclass 35, count 2 2006.173.14:57:12.31#ibcon#read 5, iclass 35, count 2 2006.173.14:57:12.31#ibcon#about to read 6, iclass 35, count 2 2006.173.14:57:12.31#ibcon#read 6, iclass 35, count 2 2006.173.14:57:12.31#ibcon#end of sib2, iclass 35, count 2 2006.173.14:57:12.31#ibcon#*mode == 0, iclass 35, count 2 2006.173.14:57:12.31#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.14:57:12.31#ibcon#[25=AT01-07\r\n] 2006.173.14:57:12.31#ibcon#*before write, iclass 35, count 2 2006.173.14:57:12.31#ibcon#enter sib2, iclass 35, count 2 2006.173.14:57:12.31#ibcon#flushed, iclass 35, count 2 2006.173.14:57:12.31#ibcon#about to write, iclass 35, count 2 2006.173.14:57:12.31#ibcon#wrote, iclass 35, count 2 2006.173.14:57:12.31#ibcon#about to read 3, iclass 35, count 2 2006.173.14:57:12.34#ibcon#read 3, iclass 35, count 2 2006.173.14:57:12.34#ibcon#about to read 4, iclass 35, count 2 2006.173.14:57:12.34#ibcon#read 4, iclass 35, count 2 2006.173.14:57:12.34#ibcon#about to read 5, iclass 35, count 2 2006.173.14:57:12.34#ibcon#read 5, iclass 35, count 2 2006.173.14:57:12.34#ibcon#about to read 6, iclass 35, count 2 2006.173.14:57:12.34#ibcon#read 6, iclass 35, count 2 2006.173.14:57:12.34#ibcon#end of sib2, iclass 35, count 2 2006.173.14:57:12.34#ibcon#*after write, iclass 35, count 2 2006.173.14:57:12.34#ibcon#*before return 0, iclass 35, count 2 2006.173.14:57:12.34#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.14:57:12.34#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.14:57:12.34#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.14:57:12.34#ibcon#ireg 7 cls_cnt 0 2006.173.14:57:12.34#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.14:57:12.46#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.14:57:12.46#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.14:57:12.46#ibcon#enter wrdev, iclass 35, count 0 2006.173.14:57:12.46#ibcon#first serial, iclass 35, count 0 2006.173.14:57:12.46#ibcon#enter sib2, iclass 35, count 0 2006.173.14:57:12.46#ibcon#flushed, iclass 35, count 0 2006.173.14:57:12.46#ibcon#about to write, iclass 35, count 0 2006.173.14:57:12.46#ibcon#wrote, iclass 35, count 0 2006.173.14:57:12.46#ibcon#about to read 3, iclass 35, count 0 2006.173.14:57:12.48#ibcon#read 3, iclass 35, count 0 2006.173.14:57:12.48#ibcon#about to read 4, iclass 35, count 0 2006.173.14:57:12.48#ibcon#read 4, iclass 35, count 0 2006.173.14:57:12.48#ibcon#about to read 5, iclass 35, count 0 2006.173.14:57:12.48#ibcon#read 5, iclass 35, count 0 2006.173.14:57:12.48#ibcon#about to read 6, iclass 35, count 0 2006.173.14:57:12.48#ibcon#read 6, iclass 35, count 0 2006.173.14:57:12.48#ibcon#end of sib2, iclass 35, count 0 2006.173.14:57:12.48#ibcon#*mode == 0, iclass 35, count 0 2006.173.14:57:12.48#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.14:57:12.48#ibcon#[25=USB\r\n] 2006.173.14:57:12.48#ibcon#*before write, iclass 35, count 0 2006.173.14:57:12.48#ibcon#enter sib2, iclass 35, count 0 2006.173.14:57:12.48#ibcon#flushed, iclass 35, count 0 2006.173.14:57:12.48#ibcon#about to write, iclass 35, count 0 2006.173.14:57:12.48#ibcon#wrote, iclass 35, count 0 2006.173.14:57:12.48#ibcon#about to read 3, iclass 35, count 0 2006.173.14:57:12.51#ibcon#read 3, iclass 35, count 0 2006.173.14:57:12.51#ibcon#about to read 4, iclass 35, count 0 2006.173.14:57:12.51#ibcon#read 4, iclass 35, count 0 2006.173.14:57:12.51#ibcon#about to read 5, iclass 35, count 0 2006.173.14:57:12.51#ibcon#read 5, iclass 35, count 0 2006.173.14:57:12.51#ibcon#about to read 6, iclass 35, count 0 2006.173.14:57:12.51#ibcon#read 6, iclass 35, count 0 2006.173.14:57:12.51#ibcon#end of sib2, iclass 35, count 0 2006.173.14:57:12.51#ibcon#*after write, iclass 35, count 0 2006.173.14:57:12.51#ibcon#*before return 0, iclass 35, count 0 2006.173.14:57:12.51#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.14:57:12.51#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.14:57:12.51#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.14:57:12.51#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.14:57:12.51$vck44/valo=2,534.99 2006.173.14:57:12.51#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.14:57:12.51#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.14:57:12.51#ibcon#ireg 17 cls_cnt 0 2006.173.14:57:12.51#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.14:57:12.51#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.14:57:12.51#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.14:57:12.51#ibcon#enter wrdev, iclass 37, count 0 2006.173.14:57:12.51#ibcon#first serial, iclass 37, count 0 2006.173.14:57:12.51#ibcon#enter sib2, iclass 37, count 0 2006.173.14:57:12.51#ibcon#flushed, iclass 37, count 0 2006.173.14:57:12.51#ibcon#about to write, iclass 37, count 0 2006.173.14:57:12.51#ibcon#wrote, iclass 37, count 0 2006.173.14:57:12.51#ibcon#about to read 3, iclass 37, count 0 2006.173.14:57:12.53#ibcon#read 3, iclass 37, count 0 2006.173.14:57:12.53#ibcon#about to read 4, iclass 37, count 0 2006.173.14:57:12.53#ibcon#read 4, iclass 37, count 0 2006.173.14:57:12.53#ibcon#about to read 5, iclass 37, count 0 2006.173.14:57:12.53#ibcon#read 5, iclass 37, count 0 2006.173.14:57:12.53#ibcon#about to read 6, iclass 37, count 0 2006.173.14:57:12.53#ibcon#read 6, iclass 37, count 0 2006.173.14:57:12.53#ibcon#end of sib2, iclass 37, count 0 2006.173.14:57:12.53#ibcon#*mode == 0, iclass 37, count 0 2006.173.14:57:12.53#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.14:57:12.53#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.14:57:12.53#ibcon#*before write, iclass 37, count 0 2006.173.14:57:12.53#ibcon#enter sib2, iclass 37, count 0 2006.173.14:57:12.53#ibcon#flushed, iclass 37, count 0 2006.173.14:57:12.53#ibcon#about to write, iclass 37, count 0 2006.173.14:57:12.53#ibcon#wrote, iclass 37, count 0 2006.173.14:57:12.53#ibcon#about to read 3, iclass 37, count 0 2006.173.14:57:12.57#ibcon#read 3, iclass 37, count 0 2006.173.14:57:12.57#ibcon#about to read 4, iclass 37, count 0 2006.173.14:57:12.57#ibcon#read 4, iclass 37, count 0 2006.173.14:57:12.57#ibcon#about to read 5, iclass 37, count 0 2006.173.14:57:12.57#ibcon#read 5, iclass 37, count 0 2006.173.14:57:12.57#ibcon#about to read 6, iclass 37, count 0 2006.173.14:57:12.57#ibcon#read 6, iclass 37, count 0 2006.173.14:57:12.57#ibcon#end of sib2, iclass 37, count 0 2006.173.14:57:12.57#ibcon#*after write, iclass 37, count 0 2006.173.14:57:12.57#ibcon#*before return 0, iclass 37, count 0 2006.173.14:57:12.57#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.14:57:12.57#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.14:57:12.57#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.14:57:12.57#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.14:57:12.57$vck44/va=2,6 2006.173.14:57:12.57#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.14:57:12.57#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.14:57:12.57#ibcon#ireg 11 cls_cnt 2 2006.173.14:57:12.57#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.14:57:12.63#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.14:57:12.63#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.14:57:12.63#ibcon#enter wrdev, iclass 39, count 2 2006.173.14:57:12.63#ibcon#first serial, iclass 39, count 2 2006.173.14:57:12.63#ibcon#enter sib2, iclass 39, count 2 2006.173.14:57:12.63#ibcon#flushed, iclass 39, count 2 2006.173.14:57:12.63#ibcon#about to write, iclass 39, count 2 2006.173.14:57:12.63#ibcon#wrote, iclass 39, count 2 2006.173.14:57:12.63#ibcon#about to read 3, iclass 39, count 2 2006.173.14:57:12.65#ibcon#read 3, iclass 39, count 2 2006.173.14:57:12.65#ibcon#about to read 4, iclass 39, count 2 2006.173.14:57:12.65#ibcon#read 4, iclass 39, count 2 2006.173.14:57:12.65#ibcon#about to read 5, iclass 39, count 2 2006.173.14:57:12.65#ibcon#read 5, iclass 39, count 2 2006.173.14:57:12.65#ibcon#about to read 6, iclass 39, count 2 2006.173.14:57:12.65#ibcon#read 6, iclass 39, count 2 2006.173.14:57:12.65#ibcon#end of sib2, iclass 39, count 2 2006.173.14:57:12.65#ibcon#*mode == 0, iclass 39, count 2 2006.173.14:57:12.65#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.14:57:12.65#ibcon#[25=AT02-06\r\n] 2006.173.14:57:12.65#ibcon#*before write, iclass 39, count 2 2006.173.14:57:12.65#ibcon#enter sib2, iclass 39, count 2 2006.173.14:57:12.65#ibcon#flushed, iclass 39, count 2 2006.173.14:57:12.65#ibcon#about to write, iclass 39, count 2 2006.173.14:57:12.65#ibcon#wrote, iclass 39, count 2 2006.173.14:57:12.65#ibcon#about to read 3, iclass 39, count 2 2006.173.14:57:12.68#ibcon#read 3, iclass 39, count 2 2006.173.14:57:12.68#ibcon#about to read 4, iclass 39, count 2 2006.173.14:57:12.68#ibcon#read 4, iclass 39, count 2 2006.173.14:57:12.68#ibcon#about to read 5, iclass 39, count 2 2006.173.14:57:12.68#ibcon#read 5, iclass 39, count 2 2006.173.14:57:12.68#ibcon#about to read 6, iclass 39, count 2 2006.173.14:57:12.68#ibcon#read 6, iclass 39, count 2 2006.173.14:57:12.68#ibcon#end of sib2, iclass 39, count 2 2006.173.14:57:12.68#ibcon#*after write, iclass 39, count 2 2006.173.14:57:12.68#ibcon#*before return 0, iclass 39, count 2 2006.173.14:57:12.68#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.14:57:12.68#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.14:57:12.68#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.14:57:12.68#ibcon#ireg 7 cls_cnt 0 2006.173.14:57:12.68#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.14:57:12.80#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.14:57:12.80#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.14:57:12.80#ibcon#enter wrdev, iclass 39, count 0 2006.173.14:57:12.80#ibcon#first serial, iclass 39, count 0 2006.173.14:57:12.80#ibcon#enter sib2, iclass 39, count 0 2006.173.14:57:12.80#ibcon#flushed, iclass 39, count 0 2006.173.14:57:12.80#ibcon#about to write, iclass 39, count 0 2006.173.14:57:12.80#ibcon#wrote, iclass 39, count 0 2006.173.14:57:12.80#ibcon#about to read 3, iclass 39, count 0 2006.173.14:57:12.82#ibcon#read 3, iclass 39, count 0 2006.173.14:57:12.82#ibcon#about to read 4, iclass 39, count 0 2006.173.14:57:12.82#ibcon#read 4, iclass 39, count 0 2006.173.14:57:12.82#ibcon#about to read 5, iclass 39, count 0 2006.173.14:57:12.82#ibcon#read 5, iclass 39, count 0 2006.173.14:57:12.82#ibcon#about to read 6, iclass 39, count 0 2006.173.14:57:12.82#ibcon#read 6, iclass 39, count 0 2006.173.14:57:12.82#ibcon#end of sib2, iclass 39, count 0 2006.173.14:57:12.82#ibcon#*mode == 0, iclass 39, count 0 2006.173.14:57:12.82#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.14:57:12.82#ibcon#[25=USB\r\n] 2006.173.14:57:12.82#ibcon#*before write, iclass 39, count 0 2006.173.14:57:12.82#ibcon#enter sib2, iclass 39, count 0 2006.173.14:57:12.82#ibcon#flushed, iclass 39, count 0 2006.173.14:57:12.82#ibcon#about to write, iclass 39, count 0 2006.173.14:57:12.82#ibcon#wrote, iclass 39, count 0 2006.173.14:57:12.82#ibcon#about to read 3, iclass 39, count 0 2006.173.14:57:12.85#ibcon#read 3, iclass 39, count 0 2006.173.14:57:12.85#ibcon#about to read 4, iclass 39, count 0 2006.173.14:57:12.85#ibcon#read 4, iclass 39, count 0 2006.173.14:57:12.85#ibcon#about to read 5, iclass 39, count 0 2006.173.14:57:12.85#ibcon#read 5, iclass 39, count 0 2006.173.14:57:12.85#ibcon#about to read 6, iclass 39, count 0 2006.173.14:57:12.85#ibcon#read 6, iclass 39, count 0 2006.173.14:57:12.85#ibcon#end of sib2, iclass 39, count 0 2006.173.14:57:12.85#ibcon#*after write, iclass 39, count 0 2006.173.14:57:12.85#ibcon#*before return 0, iclass 39, count 0 2006.173.14:57:12.85#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.14:57:12.85#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.14:57:12.85#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.14:57:12.85#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.14:57:12.85$vck44/valo=3,564.99 2006.173.14:57:12.85#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.14:57:12.85#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.14:57:12.85#ibcon#ireg 17 cls_cnt 0 2006.173.14:57:12.85#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.14:57:12.85#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.14:57:12.85#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.14:57:12.85#ibcon#enter wrdev, iclass 3, count 0 2006.173.14:57:12.85#ibcon#first serial, iclass 3, count 0 2006.173.14:57:12.85#ibcon#enter sib2, iclass 3, count 0 2006.173.14:57:12.85#ibcon#flushed, iclass 3, count 0 2006.173.14:57:12.85#ibcon#about to write, iclass 3, count 0 2006.173.14:57:12.85#ibcon#wrote, iclass 3, count 0 2006.173.14:57:12.85#ibcon#about to read 3, iclass 3, count 0 2006.173.14:57:12.87#ibcon#read 3, iclass 3, count 0 2006.173.14:57:12.87#ibcon#about to read 4, iclass 3, count 0 2006.173.14:57:12.87#ibcon#read 4, iclass 3, count 0 2006.173.14:57:12.87#ibcon#about to read 5, iclass 3, count 0 2006.173.14:57:12.87#ibcon#read 5, iclass 3, count 0 2006.173.14:57:12.87#ibcon#about to read 6, iclass 3, count 0 2006.173.14:57:12.87#ibcon#read 6, iclass 3, count 0 2006.173.14:57:12.87#ibcon#end of sib2, iclass 3, count 0 2006.173.14:57:12.87#ibcon#*mode == 0, iclass 3, count 0 2006.173.14:57:12.87#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.14:57:12.87#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.14:57:12.87#ibcon#*before write, iclass 3, count 0 2006.173.14:57:12.87#ibcon#enter sib2, iclass 3, count 0 2006.173.14:57:12.87#ibcon#flushed, iclass 3, count 0 2006.173.14:57:12.87#ibcon#about to write, iclass 3, count 0 2006.173.14:57:12.87#ibcon#wrote, iclass 3, count 0 2006.173.14:57:12.87#ibcon#about to read 3, iclass 3, count 0 2006.173.14:57:12.91#ibcon#read 3, iclass 3, count 0 2006.173.14:57:12.91#ibcon#about to read 4, iclass 3, count 0 2006.173.14:57:12.91#ibcon#read 4, iclass 3, count 0 2006.173.14:57:12.91#ibcon#about to read 5, iclass 3, count 0 2006.173.14:57:12.91#ibcon#read 5, iclass 3, count 0 2006.173.14:57:12.91#ibcon#about to read 6, iclass 3, count 0 2006.173.14:57:12.91#ibcon#read 6, iclass 3, count 0 2006.173.14:57:12.91#ibcon#end of sib2, iclass 3, count 0 2006.173.14:57:12.91#ibcon#*after write, iclass 3, count 0 2006.173.14:57:12.91#ibcon#*before return 0, iclass 3, count 0 2006.173.14:57:12.91#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.14:57:12.91#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.14:57:12.91#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.14:57:12.91#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.14:57:12.91$vck44/va=3,5 2006.173.14:57:12.91#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.14:57:12.91#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.14:57:12.91#ibcon#ireg 11 cls_cnt 2 2006.173.14:57:12.91#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.14:57:12.97#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.14:57:12.97#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.14:57:12.97#ibcon#enter wrdev, iclass 5, count 2 2006.173.14:57:12.97#ibcon#first serial, iclass 5, count 2 2006.173.14:57:12.97#ibcon#enter sib2, iclass 5, count 2 2006.173.14:57:12.97#ibcon#flushed, iclass 5, count 2 2006.173.14:57:12.97#ibcon#about to write, iclass 5, count 2 2006.173.14:57:12.97#ibcon#wrote, iclass 5, count 2 2006.173.14:57:12.97#ibcon#about to read 3, iclass 5, count 2 2006.173.14:57:12.99#ibcon#read 3, iclass 5, count 2 2006.173.14:57:12.99#ibcon#about to read 4, iclass 5, count 2 2006.173.14:57:12.99#ibcon#read 4, iclass 5, count 2 2006.173.14:57:12.99#ibcon#about to read 5, iclass 5, count 2 2006.173.14:57:12.99#ibcon#read 5, iclass 5, count 2 2006.173.14:57:12.99#ibcon#about to read 6, iclass 5, count 2 2006.173.14:57:12.99#ibcon#read 6, iclass 5, count 2 2006.173.14:57:12.99#ibcon#end of sib2, iclass 5, count 2 2006.173.14:57:12.99#ibcon#*mode == 0, iclass 5, count 2 2006.173.14:57:12.99#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.14:57:12.99#ibcon#[25=AT03-05\r\n] 2006.173.14:57:12.99#ibcon#*before write, iclass 5, count 2 2006.173.14:57:12.99#ibcon#enter sib2, iclass 5, count 2 2006.173.14:57:12.99#ibcon#flushed, iclass 5, count 2 2006.173.14:57:12.99#ibcon#about to write, iclass 5, count 2 2006.173.14:57:12.99#ibcon#wrote, iclass 5, count 2 2006.173.14:57:12.99#ibcon#about to read 3, iclass 5, count 2 2006.173.14:57:13.02#ibcon#read 3, iclass 5, count 2 2006.173.14:57:13.02#ibcon#about to read 4, iclass 5, count 2 2006.173.14:57:13.02#ibcon#read 4, iclass 5, count 2 2006.173.14:57:13.02#ibcon#about to read 5, iclass 5, count 2 2006.173.14:57:13.02#ibcon#read 5, iclass 5, count 2 2006.173.14:57:13.02#ibcon#about to read 6, iclass 5, count 2 2006.173.14:57:13.02#ibcon#read 6, iclass 5, count 2 2006.173.14:57:13.02#ibcon#end of sib2, iclass 5, count 2 2006.173.14:57:13.02#ibcon#*after write, iclass 5, count 2 2006.173.14:57:13.02#ibcon#*before return 0, iclass 5, count 2 2006.173.14:57:13.02#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.14:57:13.02#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.14:57:13.02#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.14:57:13.02#ibcon#ireg 7 cls_cnt 0 2006.173.14:57:13.02#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.14:57:13.14#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.14:57:13.14#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.14:57:13.14#ibcon#enter wrdev, iclass 5, count 0 2006.173.14:57:13.14#ibcon#first serial, iclass 5, count 0 2006.173.14:57:13.14#ibcon#enter sib2, iclass 5, count 0 2006.173.14:57:13.14#ibcon#flushed, iclass 5, count 0 2006.173.14:57:13.14#ibcon#about to write, iclass 5, count 0 2006.173.14:57:13.14#ibcon#wrote, iclass 5, count 0 2006.173.14:57:13.14#ibcon#about to read 3, iclass 5, count 0 2006.173.14:57:13.16#ibcon#read 3, iclass 5, count 0 2006.173.14:57:13.16#ibcon#about to read 4, iclass 5, count 0 2006.173.14:57:13.16#ibcon#read 4, iclass 5, count 0 2006.173.14:57:13.16#ibcon#about to read 5, iclass 5, count 0 2006.173.14:57:13.16#ibcon#read 5, iclass 5, count 0 2006.173.14:57:13.16#ibcon#about to read 6, iclass 5, count 0 2006.173.14:57:13.16#ibcon#read 6, iclass 5, count 0 2006.173.14:57:13.16#ibcon#end of sib2, iclass 5, count 0 2006.173.14:57:13.16#ibcon#*mode == 0, iclass 5, count 0 2006.173.14:57:13.16#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.14:57:13.16#ibcon#[25=USB\r\n] 2006.173.14:57:13.16#ibcon#*before write, iclass 5, count 0 2006.173.14:57:13.16#ibcon#enter sib2, iclass 5, count 0 2006.173.14:57:13.16#ibcon#flushed, iclass 5, count 0 2006.173.14:57:13.16#ibcon#about to write, iclass 5, count 0 2006.173.14:57:13.16#ibcon#wrote, iclass 5, count 0 2006.173.14:57:13.16#ibcon#about to read 3, iclass 5, count 0 2006.173.14:57:13.19#ibcon#read 3, iclass 5, count 0 2006.173.14:57:13.19#ibcon#about to read 4, iclass 5, count 0 2006.173.14:57:13.19#ibcon#read 4, iclass 5, count 0 2006.173.14:57:13.19#ibcon#about to read 5, iclass 5, count 0 2006.173.14:57:13.19#ibcon#read 5, iclass 5, count 0 2006.173.14:57:13.19#ibcon#about to read 6, iclass 5, count 0 2006.173.14:57:13.19#ibcon#read 6, iclass 5, count 0 2006.173.14:57:13.19#ibcon#end of sib2, iclass 5, count 0 2006.173.14:57:13.19#ibcon#*after write, iclass 5, count 0 2006.173.14:57:13.19#ibcon#*before return 0, iclass 5, count 0 2006.173.14:57:13.19#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.14:57:13.19#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.14:57:13.19#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.14:57:13.19#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.14:57:13.19$vck44/valo=4,624.99 2006.173.14:57:13.19#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.14:57:13.19#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.14:57:13.19#ibcon#ireg 17 cls_cnt 0 2006.173.14:57:13.19#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.14:57:13.19#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.14:57:13.19#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.14:57:13.19#ibcon#enter wrdev, iclass 7, count 0 2006.173.14:57:13.19#ibcon#first serial, iclass 7, count 0 2006.173.14:57:13.19#ibcon#enter sib2, iclass 7, count 0 2006.173.14:57:13.19#ibcon#flushed, iclass 7, count 0 2006.173.14:57:13.19#ibcon#about to write, iclass 7, count 0 2006.173.14:57:13.19#ibcon#wrote, iclass 7, count 0 2006.173.14:57:13.19#ibcon#about to read 3, iclass 7, count 0 2006.173.14:57:13.21#ibcon#read 3, iclass 7, count 0 2006.173.14:57:13.21#ibcon#about to read 4, iclass 7, count 0 2006.173.14:57:13.21#ibcon#read 4, iclass 7, count 0 2006.173.14:57:13.21#ibcon#about to read 5, iclass 7, count 0 2006.173.14:57:13.21#ibcon#read 5, iclass 7, count 0 2006.173.14:57:13.21#ibcon#about to read 6, iclass 7, count 0 2006.173.14:57:13.21#ibcon#read 6, iclass 7, count 0 2006.173.14:57:13.21#ibcon#end of sib2, iclass 7, count 0 2006.173.14:57:13.21#ibcon#*mode == 0, iclass 7, count 0 2006.173.14:57:13.21#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.14:57:13.21#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.14:57:13.21#ibcon#*before write, iclass 7, count 0 2006.173.14:57:13.21#ibcon#enter sib2, iclass 7, count 0 2006.173.14:57:13.21#ibcon#flushed, iclass 7, count 0 2006.173.14:57:13.21#ibcon#about to write, iclass 7, count 0 2006.173.14:57:13.21#ibcon#wrote, iclass 7, count 0 2006.173.14:57:13.21#ibcon#about to read 3, iclass 7, count 0 2006.173.14:57:13.25#ibcon#read 3, iclass 7, count 0 2006.173.14:57:13.25#ibcon#about to read 4, iclass 7, count 0 2006.173.14:57:13.25#ibcon#read 4, iclass 7, count 0 2006.173.14:57:13.25#ibcon#about to read 5, iclass 7, count 0 2006.173.14:57:13.25#ibcon#read 5, iclass 7, count 0 2006.173.14:57:13.25#ibcon#about to read 6, iclass 7, count 0 2006.173.14:57:13.25#ibcon#read 6, iclass 7, count 0 2006.173.14:57:13.25#ibcon#end of sib2, iclass 7, count 0 2006.173.14:57:13.25#ibcon#*after write, iclass 7, count 0 2006.173.14:57:13.25#ibcon#*before return 0, iclass 7, count 0 2006.173.14:57:13.25#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.14:57:13.25#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.14:57:13.25#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.14:57:13.25#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.14:57:13.25$vck44/va=4,6 2006.173.14:57:13.25#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.14:57:13.25#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.14:57:13.25#ibcon#ireg 11 cls_cnt 2 2006.173.14:57:13.25#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.14:57:13.31#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.14:57:13.31#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.14:57:13.31#ibcon#enter wrdev, iclass 11, count 2 2006.173.14:57:13.31#ibcon#first serial, iclass 11, count 2 2006.173.14:57:13.31#ibcon#enter sib2, iclass 11, count 2 2006.173.14:57:13.31#ibcon#flushed, iclass 11, count 2 2006.173.14:57:13.31#ibcon#about to write, iclass 11, count 2 2006.173.14:57:13.31#ibcon#wrote, iclass 11, count 2 2006.173.14:57:13.31#ibcon#about to read 3, iclass 11, count 2 2006.173.14:57:13.33#ibcon#read 3, iclass 11, count 2 2006.173.14:57:13.33#ibcon#about to read 4, iclass 11, count 2 2006.173.14:57:13.33#ibcon#read 4, iclass 11, count 2 2006.173.14:57:13.33#ibcon#about to read 5, iclass 11, count 2 2006.173.14:57:13.33#ibcon#read 5, iclass 11, count 2 2006.173.14:57:13.33#ibcon#about to read 6, iclass 11, count 2 2006.173.14:57:13.33#ibcon#read 6, iclass 11, count 2 2006.173.14:57:13.33#ibcon#end of sib2, iclass 11, count 2 2006.173.14:57:13.33#ibcon#*mode == 0, iclass 11, count 2 2006.173.14:57:13.33#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.14:57:13.33#ibcon#[25=AT04-06\r\n] 2006.173.14:57:13.33#ibcon#*before write, iclass 11, count 2 2006.173.14:57:13.33#ibcon#enter sib2, iclass 11, count 2 2006.173.14:57:13.33#ibcon#flushed, iclass 11, count 2 2006.173.14:57:13.33#ibcon#about to write, iclass 11, count 2 2006.173.14:57:13.33#ibcon#wrote, iclass 11, count 2 2006.173.14:57:13.33#ibcon#about to read 3, iclass 11, count 2 2006.173.14:57:13.36#ibcon#read 3, iclass 11, count 2 2006.173.14:57:13.36#ibcon#about to read 4, iclass 11, count 2 2006.173.14:57:13.36#ibcon#read 4, iclass 11, count 2 2006.173.14:57:13.36#ibcon#about to read 5, iclass 11, count 2 2006.173.14:57:13.36#ibcon#read 5, iclass 11, count 2 2006.173.14:57:13.36#ibcon#about to read 6, iclass 11, count 2 2006.173.14:57:13.36#ibcon#read 6, iclass 11, count 2 2006.173.14:57:13.36#ibcon#end of sib2, iclass 11, count 2 2006.173.14:57:13.36#ibcon#*after write, iclass 11, count 2 2006.173.14:57:13.36#ibcon#*before return 0, iclass 11, count 2 2006.173.14:57:13.36#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.14:57:13.36#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.14:57:13.36#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.14:57:13.36#ibcon#ireg 7 cls_cnt 0 2006.173.14:57:13.36#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.14:57:13.48#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.14:57:13.48#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.14:57:13.48#ibcon#enter wrdev, iclass 11, count 0 2006.173.14:57:13.48#ibcon#first serial, iclass 11, count 0 2006.173.14:57:13.48#ibcon#enter sib2, iclass 11, count 0 2006.173.14:57:13.48#ibcon#flushed, iclass 11, count 0 2006.173.14:57:13.48#ibcon#about to write, iclass 11, count 0 2006.173.14:57:13.48#ibcon#wrote, iclass 11, count 0 2006.173.14:57:13.48#ibcon#about to read 3, iclass 11, count 0 2006.173.14:57:13.50#ibcon#read 3, iclass 11, count 0 2006.173.14:57:13.50#ibcon#about to read 4, iclass 11, count 0 2006.173.14:57:13.50#ibcon#read 4, iclass 11, count 0 2006.173.14:57:13.50#ibcon#about to read 5, iclass 11, count 0 2006.173.14:57:13.50#ibcon#read 5, iclass 11, count 0 2006.173.14:57:13.50#ibcon#about to read 6, iclass 11, count 0 2006.173.14:57:13.50#ibcon#read 6, iclass 11, count 0 2006.173.14:57:13.50#ibcon#end of sib2, iclass 11, count 0 2006.173.14:57:13.50#ibcon#*mode == 0, iclass 11, count 0 2006.173.14:57:13.50#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.14:57:13.50#ibcon#[25=USB\r\n] 2006.173.14:57:13.50#ibcon#*before write, iclass 11, count 0 2006.173.14:57:13.50#ibcon#enter sib2, iclass 11, count 0 2006.173.14:57:13.50#ibcon#flushed, iclass 11, count 0 2006.173.14:57:13.50#ibcon#about to write, iclass 11, count 0 2006.173.14:57:13.50#ibcon#wrote, iclass 11, count 0 2006.173.14:57:13.50#ibcon#about to read 3, iclass 11, count 0 2006.173.14:57:13.53#ibcon#read 3, iclass 11, count 0 2006.173.14:57:13.53#ibcon#about to read 4, iclass 11, count 0 2006.173.14:57:13.53#ibcon#read 4, iclass 11, count 0 2006.173.14:57:13.53#ibcon#about to read 5, iclass 11, count 0 2006.173.14:57:13.53#ibcon#read 5, iclass 11, count 0 2006.173.14:57:13.53#ibcon#about to read 6, iclass 11, count 0 2006.173.14:57:13.53#ibcon#read 6, iclass 11, count 0 2006.173.14:57:13.53#ibcon#end of sib2, iclass 11, count 0 2006.173.14:57:13.53#ibcon#*after write, iclass 11, count 0 2006.173.14:57:13.53#ibcon#*before return 0, iclass 11, count 0 2006.173.14:57:13.53#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.14:57:13.53#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.14:57:13.53#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.14:57:13.53#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.14:57:13.53$vck44/valo=5,734.99 2006.173.14:57:13.53#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.14:57:13.53#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.14:57:13.53#ibcon#ireg 17 cls_cnt 0 2006.173.14:57:13.53#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.14:57:13.53#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.14:57:13.53#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.14:57:13.53#ibcon#enter wrdev, iclass 13, count 0 2006.173.14:57:13.53#ibcon#first serial, iclass 13, count 0 2006.173.14:57:13.53#ibcon#enter sib2, iclass 13, count 0 2006.173.14:57:13.53#ibcon#flushed, iclass 13, count 0 2006.173.14:57:13.53#ibcon#about to write, iclass 13, count 0 2006.173.14:57:13.53#ibcon#wrote, iclass 13, count 0 2006.173.14:57:13.53#ibcon#about to read 3, iclass 13, count 0 2006.173.14:57:13.55#ibcon#read 3, iclass 13, count 0 2006.173.14:57:13.55#ibcon#about to read 4, iclass 13, count 0 2006.173.14:57:13.55#ibcon#read 4, iclass 13, count 0 2006.173.14:57:13.55#ibcon#about to read 5, iclass 13, count 0 2006.173.14:57:13.55#ibcon#read 5, iclass 13, count 0 2006.173.14:57:13.55#ibcon#about to read 6, iclass 13, count 0 2006.173.14:57:13.55#ibcon#read 6, iclass 13, count 0 2006.173.14:57:13.55#ibcon#end of sib2, iclass 13, count 0 2006.173.14:57:13.55#ibcon#*mode == 0, iclass 13, count 0 2006.173.14:57:13.55#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.14:57:13.55#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.14:57:13.55#ibcon#*before write, iclass 13, count 0 2006.173.14:57:13.55#ibcon#enter sib2, iclass 13, count 0 2006.173.14:57:13.55#ibcon#flushed, iclass 13, count 0 2006.173.14:57:13.55#ibcon#about to write, iclass 13, count 0 2006.173.14:57:13.55#ibcon#wrote, iclass 13, count 0 2006.173.14:57:13.55#ibcon#about to read 3, iclass 13, count 0 2006.173.14:57:13.59#ibcon#read 3, iclass 13, count 0 2006.173.14:57:13.59#ibcon#about to read 4, iclass 13, count 0 2006.173.14:57:13.59#ibcon#read 4, iclass 13, count 0 2006.173.14:57:13.59#ibcon#about to read 5, iclass 13, count 0 2006.173.14:57:13.59#ibcon#read 5, iclass 13, count 0 2006.173.14:57:13.59#ibcon#about to read 6, iclass 13, count 0 2006.173.14:57:13.59#ibcon#read 6, iclass 13, count 0 2006.173.14:57:13.59#ibcon#end of sib2, iclass 13, count 0 2006.173.14:57:13.59#ibcon#*after write, iclass 13, count 0 2006.173.14:57:13.59#ibcon#*before return 0, iclass 13, count 0 2006.173.14:57:13.59#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.14:57:13.59#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.14:57:13.59#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.14:57:13.59#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.14:57:13.59$vck44/va=5,4 2006.173.14:57:13.59#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.14:57:13.59#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.14:57:13.59#ibcon#ireg 11 cls_cnt 2 2006.173.14:57:13.59#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.14:57:13.65#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.14:57:13.65#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.14:57:13.65#ibcon#enter wrdev, iclass 15, count 2 2006.173.14:57:13.65#ibcon#first serial, iclass 15, count 2 2006.173.14:57:13.65#ibcon#enter sib2, iclass 15, count 2 2006.173.14:57:13.65#ibcon#flushed, iclass 15, count 2 2006.173.14:57:13.65#ibcon#about to write, iclass 15, count 2 2006.173.14:57:13.65#ibcon#wrote, iclass 15, count 2 2006.173.14:57:13.65#ibcon#about to read 3, iclass 15, count 2 2006.173.14:57:13.67#ibcon#read 3, iclass 15, count 2 2006.173.14:57:13.67#ibcon#about to read 4, iclass 15, count 2 2006.173.14:57:13.67#ibcon#read 4, iclass 15, count 2 2006.173.14:57:13.67#ibcon#about to read 5, iclass 15, count 2 2006.173.14:57:13.67#ibcon#read 5, iclass 15, count 2 2006.173.14:57:13.67#ibcon#about to read 6, iclass 15, count 2 2006.173.14:57:13.67#ibcon#read 6, iclass 15, count 2 2006.173.14:57:13.67#ibcon#end of sib2, iclass 15, count 2 2006.173.14:57:13.67#ibcon#*mode == 0, iclass 15, count 2 2006.173.14:57:13.67#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.14:57:13.67#ibcon#[25=AT05-04\r\n] 2006.173.14:57:13.67#ibcon#*before write, iclass 15, count 2 2006.173.14:57:13.67#ibcon#enter sib2, iclass 15, count 2 2006.173.14:57:13.67#ibcon#flushed, iclass 15, count 2 2006.173.14:57:13.67#ibcon#about to write, iclass 15, count 2 2006.173.14:57:13.67#ibcon#wrote, iclass 15, count 2 2006.173.14:57:13.67#ibcon#about to read 3, iclass 15, count 2 2006.173.14:57:13.70#ibcon#read 3, iclass 15, count 2 2006.173.14:57:13.70#ibcon#about to read 4, iclass 15, count 2 2006.173.14:57:13.70#ibcon#read 4, iclass 15, count 2 2006.173.14:57:13.70#ibcon#about to read 5, iclass 15, count 2 2006.173.14:57:13.70#ibcon#read 5, iclass 15, count 2 2006.173.14:57:13.70#ibcon#about to read 6, iclass 15, count 2 2006.173.14:57:13.70#ibcon#read 6, iclass 15, count 2 2006.173.14:57:13.70#ibcon#end of sib2, iclass 15, count 2 2006.173.14:57:13.70#ibcon#*after write, iclass 15, count 2 2006.173.14:57:13.70#ibcon#*before return 0, iclass 15, count 2 2006.173.14:57:13.70#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.14:57:13.70#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.14:57:13.70#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.14:57:13.70#ibcon#ireg 7 cls_cnt 0 2006.173.14:57:13.70#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.14:57:13.82#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.14:57:13.82#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.14:57:13.82#ibcon#enter wrdev, iclass 15, count 0 2006.173.14:57:13.82#ibcon#first serial, iclass 15, count 0 2006.173.14:57:13.82#ibcon#enter sib2, iclass 15, count 0 2006.173.14:57:13.82#ibcon#flushed, iclass 15, count 0 2006.173.14:57:13.82#ibcon#about to write, iclass 15, count 0 2006.173.14:57:13.82#ibcon#wrote, iclass 15, count 0 2006.173.14:57:13.82#ibcon#about to read 3, iclass 15, count 0 2006.173.14:57:13.84#ibcon#read 3, iclass 15, count 0 2006.173.14:57:13.84#ibcon#about to read 4, iclass 15, count 0 2006.173.14:57:13.84#ibcon#read 4, iclass 15, count 0 2006.173.14:57:13.84#ibcon#about to read 5, iclass 15, count 0 2006.173.14:57:13.84#ibcon#read 5, iclass 15, count 0 2006.173.14:57:13.84#ibcon#about to read 6, iclass 15, count 0 2006.173.14:57:13.84#ibcon#read 6, iclass 15, count 0 2006.173.14:57:13.84#ibcon#end of sib2, iclass 15, count 0 2006.173.14:57:13.84#ibcon#*mode == 0, iclass 15, count 0 2006.173.14:57:13.84#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.14:57:13.84#ibcon#[25=USB\r\n] 2006.173.14:57:13.84#ibcon#*before write, iclass 15, count 0 2006.173.14:57:13.84#ibcon#enter sib2, iclass 15, count 0 2006.173.14:57:13.84#ibcon#flushed, iclass 15, count 0 2006.173.14:57:13.84#ibcon#about to write, iclass 15, count 0 2006.173.14:57:13.84#ibcon#wrote, iclass 15, count 0 2006.173.14:57:13.84#ibcon#about to read 3, iclass 15, count 0 2006.173.14:57:13.87#ibcon#read 3, iclass 15, count 0 2006.173.14:57:13.87#ibcon#about to read 4, iclass 15, count 0 2006.173.14:57:13.87#ibcon#read 4, iclass 15, count 0 2006.173.14:57:13.87#ibcon#about to read 5, iclass 15, count 0 2006.173.14:57:13.87#ibcon#read 5, iclass 15, count 0 2006.173.14:57:13.87#ibcon#about to read 6, iclass 15, count 0 2006.173.14:57:13.87#ibcon#read 6, iclass 15, count 0 2006.173.14:57:13.87#ibcon#end of sib2, iclass 15, count 0 2006.173.14:57:13.87#ibcon#*after write, iclass 15, count 0 2006.173.14:57:13.87#ibcon#*before return 0, iclass 15, count 0 2006.173.14:57:13.87#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.14:57:13.87#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.14:57:13.87#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.14:57:13.87#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.14:57:13.87$vck44/valo=6,814.99 2006.173.14:57:13.87#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.14:57:13.87#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.14:57:13.87#ibcon#ireg 17 cls_cnt 0 2006.173.14:57:13.87#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.14:57:13.87#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.14:57:13.87#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.14:57:13.87#ibcon#enter wrdev, iclass 17, count 0 2006.173.14:57:13.87#ibcon#first serial, iclass 17, count 0 2006.173.14:57:13.87#ibcon#enter sib2, iclass 17, count 0 2006.173.14:57:13.87#ibcon#flushed, iclass 17, count 0 2006.173.14:57:13.87#ibcon#about to write, iclass 17, count 0 2006.173.14:57:13.87#ibcon#wrote, iclass 17, count 0 2006.173.14:57:13.87#ibcon#about to read 3, iclass 17, count 0 2006.173.14:57:13.89#ibcon#read 3, iclass 17, count 0 2006.173.14:57:13.89#ibcon#about to read 4, iclass 17, count 0 2006.173.14:57:13.89#ibcon#read 4, iclass 17, count 0 2006.173.14:57:13.89#ibcon#about to read 5, iclass 17, count 0 2006.173.14:57:13.89#ibcon#read 5, iclass 17, count 0 2006.173.14:57:13.89#ibcon#about to read 6, iclass 17, count 0 2006.173.14:57:13.89#ibcon#read 6, iclass 17, count 0 2006.173.14:57:13.89#ibcon#end of sib2, iclass 17, count 0 2006.173.14:57:13.89#ibcon#*mode == 0, iclass 17, count 0 2006.173.14:57:13.89#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.14:57:13.89#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.14:57:13.89#ibcon#*before write, iclass 17, count 0 2006.173.14:57:13.89#ibcon#enter sib2, iclass 17, count 0 2006.173.14:57:13.89#ibcon#flushed, iclass 17, count 0 2006.173.14:57:13.89#ibcon#about to write, iclass 17, count 0 2006.173.14:57:13.89#ibcon#wrote, iclass 17, count 0 2006.173.14:57:13.89#ibcon#about to read 3, iclass 17, count 0 2006.173.14:57:13.93#ibcon#read 3, iclass 17, count 0 2006.173.14:57:13.93#ibcon#about to read 4, iclass 17, count 0 2006.173.14:57:13.93#ibcon#read 4, iclass 17, count 0 2006.173.14:57:13.93#ibcon#about to read 5, iclass 17, count 0 2006.173.14:57:13.93#ibcon#read 5, iclass 17, count 0 2006.173.14:57:13.93#ibcon#about to read 6, iclass 17, count 0 2006.173.14:57:13.93#ibcon#read 6, iclass 17, count 0 2006.173.14:57:13.93#ibcon#end of sib2, iclass 17, count 0 2006.173.14:57:13.93#ibcon#*after write, iclass 17, count 0 2006.173.14:57:13.93#ibcon#*before return 0, iclass 17, count 0 2006.173.14:57:13.93#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.14:57:13.93#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.14:57:13.93#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.14:57:13.93#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.14:57:13.93$vck44/va=6,3 2006.173.14:57:13.93#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.14:57:13.93#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.14:57:13.93#ibcon#ireg 11 cls_cnt 2 2006.173.14:57:13.93#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.14:57:13.99#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.14:57:13.99#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.14:57:13.99#ibcon#enter wrdev, iclass 19, count 2 2006.173.14:57:13.99#ibcon#first serial, iclass 19, count 2 2006.173.14:57:13.99#ibcon#enter sib2, iclass 19, count 2 2006.173.14:57:13.99#ibcon#flushed, iclass 19, count 2 2006.173.14:57:13.99#ibcon#about to write, iclass 19, count 2 2006.173.14:57:13.99#ibcon#wrote, iclass 19, count 2 2006.173.14:57:13.99#ibcon#about to read 3, iclass 19, count 2 2006.173.14:57:14.01#ibcon#read 3, iclass 19, count 2 2006.173.14:57:14.01#ibcon#about to read 4, iclass 19, count 2 2006.173.14:57:14.01#ibcon#read 4, iclass 19, count 2 2006.173.14:57:14.01#ibcon#about to read 5, iclass 19, count 2 2006.173.14:57:14.01#ibcon#read 5, iclass 19, count 2 2006.173.14:57:14.01#ibcon#about to read 6, iclass 19, count 2 2006.173.14:57:14.01#ibcon#read 6, iclass 19, count 2 2006.173.14:57:14.01#ibcon#end of sib2, iclass 19, count 2 2006.173.14:57:14.01#ibcon#*mode == 0, iclass 19, count 2 2006.173.14:57:14.01#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.14:57:14.01#ibcon#[25=AT06-03\r\n] 2006.173.14:57:14.01#ibcon#*before write, iclass 19, count 2 2006.173.14:57:14.01#ibcon#enter sib2, iclass 19, count 2 2006.173.14:57:14.01#ibcon#flushed, iclass 19, count 2 2006.173.14:57:14.01#ibcon#about to write, iclass 19, count 2 2006.173.14:57:14.01#ibcon#wrote, iclass 19, count 2 2006.173.14:57:14.01#ibcon#about to read 3, iclass 19, count 2 2006.173.14:57:14.04#ibcon#read 3, iclass 19, count 2 2006.173.14:57:14.04#ibcon#about to read 4, iclass 19, count 2 2006.173.14:57:14.04#ibcon#read 4, iclass 19, count 2 2006.173.14:57:14.04#ibcon#about to read 5, iclass 19, count 2 2006.173.14:57:14.04#ibcon#read 5, iclass 19, count 2 2006.173.14:57:14.04#ibcon#about to read 6, iclass 19, count 2 2006.173.14:57:14.04#ibcon#read 6, iclass 19, count 2 2006.173.14:57:14.04#ibcon#end of sib2, iclass 19, count 2 2006.173.14:57:14.04#ibcon#*after write, iclass 19, count 2 2006.173.14:57:14.04#ibcon#*before return 0, iclass 19, count 2 2006.173.14:57:14.04#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.14:57:14.04#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.14:57:14.04#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.14:57:14.04#ibcon#ireg 7 cls_cnt 0 2006.173.14:57:14.04#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.14:57:14.16#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.14:57:14.16#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.14:57:14.16#ibcon#enter wrdev, iclass 19, count 0 2006.173.14:57:14.16#ibcon#first serial, iclass 19, count 0 2006.173.14:57:14.16#ibcon#enter sib2, iclass 19, count 0 2006.173.14:57:14.16#ibcon#flushed, iclass 19, count 0 2006.173.14:57:14.16#ibcon#about to write, iclass 19, count 0 2006.173.14:57:14.16#ibcon#wrote, iclass 19, count 0 2006.173.14:57:14.16#ibcon#about to read 3, iclass 19, count 0 2006.173.14:57:14.18#ibcon#read 3, iclass 19, count 0 2006.173.14:57:14.18#ibcon#about to read 4, iclass 19, count 0 2006.173.14:57:14.18#ibcon#read 4, iclass 19, count 0 2006.173.14:57:14.18#ibcon#about to read 5, iclass 19, count 0 2006.173.14:57:14.18#ibcon#read 5, iclass 19, count 0 2006.173.14:57:14.18#ibcon#about to read 6, iclass 19, count 0 2006.173.14:57:14.18#ibcon#read 6, iclass 19, count 0 2006.173.14:57:14.18#ibcon#end of sib2, iclass 19, count 0 2006.173.14:57:14.18#ibcon#*mode == 0, iclass 19, count 0 2006.173.14:57:14.18#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.14:57:14.18#ibcon#[25=USB\r\n] 2006.173.14:57:14.18#ibcon#*before write, iclass 19, count 0 2006.173.14:57:14.18#ibcon#enter sib2, iclass 19, count 0 2006.173.14:57:14.18#ibcon#flushed, iclass 19, count 0 2006.173.14:57:14.18#ibcon#about to write, iclass 19, count 0 2006.173.14:57:14.18#ibcon#wrote, iclass 19, count 0 2006.173.14:57:14.18#ibcon#about to read 3, iclass 19, count 0 2006.173.14:57:14.21#ibcon#read 3, iclass 19, count 0 2006.173.14:57:14.21#ibcon#about to read 4, iclass 19, count 0 2006.173.14:57:14.21#ibcon#read 4, iclass 19, count 0 2006.173.14:57:14.21#ibcon#about to read 5, iclass 19, count 0 2006.173.14:57:14.21#ibcon#read 5, iclass 19, count 0 2006.173.14:57:14.21#ibcon#about to read 6, iclass 19, count 0 2006.173.14:57:14.21#ibcon#read 6, iclass 19, count 0 2006.173.14:57:14.21#ibcon#end of sib2, iclass 19, count 0 2006.173.14:57:14.21#ibcon#*after write, iclass 19, count 0 2006.173.14:57:14.21#ibcon#*before return 0, iclass 19, count 0 2006.173.14:57:14.21#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.14:57:14.21#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.14:57:14.21#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.14:57:14.21#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.14:57:14.21$vck44/valo=7,864.99 2006.173.14:57:14.21#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.14:57:14.21#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.14:57:14.21#ibcon#ireg 17 cls_cnt 0 2006.173.14:57:14.21#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.14:57:14.21#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.14:57:14.21#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.14:57:14.21#ibcon#enter wrdev, iclass 21, count 0 2006.173.14:57:14.21#ibcon#first serial, iclass 21, count 0 2006.173.14:57:14.21#ibcon#enter sib2, iclass 21, count 0 2006.173.14:57:14.21#ibcon#flushed, iclass 21, count 0 2006.173.14:57:14.21#ibcon#about to write, iclass 21, count 0 2006.173.14:57:14.21#ibcon#wrote, iclass 21, count 0 2006.173.14:57:14.21#ibcon#about to read 3, iclass 21, count 0 2006.173.14:57:14.23#ibcon#read 3, iclass 21, count 0 2006.173.14:57:14.23#ibcon#about to read 4, iclass 21, count 0 2006.173.14:57:14.23#ibcon#read 4, iclass 21, count 0 2006.173.14:57:14.23#ibcon#about to read 5, iclass 21, count 0 2006.173.14:57:14.23#ibcon#read 5, iclass 21, count 0 2006.173.14:57:14.23#ibcon#about to read 6, iclass 21, count 0 2006.173.14:57:14.23#ibcon#read 6, iclass 21, count 0 2006.173.14:57:14.23#ibcon#end of sib2, iclass 21, count 0 2006.173.14:57:14.23#ibcon#*mode == 0, iclass 21, count 0 2006.173.14:57:14.23#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.14:57:14.23#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.14:57:14.23#ibcon#*before write, iclass 21, count 0 2006.173.14:57:14.23#ibcon#enter sib2, iclass 21, count 0 2006.173.14:57:14.23#ibcon#flushed, iclass 21, count 0 2006.173.14:57:14.23#ibcon#about to write, iclass 21, count 0 2006.173.14:57:14.23#ibcon#wrote, iclass 21, count 0 2006.173.14:57:14.23#ibcon#about to read 3, iclass 21, count 0 2006.173.14:57:14.27#ibcon#read 3, iclass 21, count 0 2006.173.14:57:14.27#ibcon#about to read 4, iclass 21, count 0 2006.173.14:57:14.27#ibcon#read 4, iclass 21, count 0 2006.173.14:57:14.27#ibcon#about to read 5, iclass 21, count 0 2006.173.14:57:14.27#ibcon#read 5, iclass 21, count 0 2006.173.14:57:14.27#ibcon#about to read 6, iclass 21, count 0 2006.173.14:57:14.27#ibcon#read 6, iclass 21, count 0 2006.173.14:57:14.27#ibcon#end of sib2, iclass 21, count 0 2006.173.14:57:14.27#ibcon#*after write, iclass 21, count 0 2006.173.14:57:14.27#ibcon#*before return 0, iclass 21, count 0 2006.173.14:57:14.27#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.14:57:14.27#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.14:57:14.27#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.14:57:14.27#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.14:57:14.27$vck44/va=7,4 2006.173.14:57:14.27#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.14:57:14.27#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.14:57:14.27#ibcon#ireg 11 cls_cnt 2 2006.173.14:57:14.27#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.14:57:14.33#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.14:57:14.33#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.14:57:14.33#ibcon#enter wrdev, iclass 23, count 2 2006.173.14:57:14.33#ibcon#first serial, iclass 23, count 2 2006.173.14:57:14.33#ibcon#enter sib2, iclass 23, count 2 2006.173.14:57:14.33#ibcon#flushed, iclass 23, count 2 2006.173.14:57:14.33#ibcon#about to write, iclass 23, count 2 2006.173.14:57:14.33#ibcon#wrote, iclass 23, count 2 2006.173.14:57:14.33#ibcon#about to read 3, iclass 23, count 2 2006.173.14:57:14.35#ibcon#read 3, iclass 23, count 2 2006.173.14:57:14.35#ibcon#about to read 4, iclass 23, count 2 2006.173.14:57:14.35#ibcon#read 4, iclass 23, count 2 2006.173.14:57:14.35#ibcon#about to read 5, iclass 23, count 2 2006.173.14:57:14.35#ibcon#read 5, iclass 23, count 2 2006.173.14:57:14.35#ibcon#about to read 6, iclass 23, count 2 2006.173.14:57:14.35#ibcon#read 6, iclass 23, count 2 2006.173.14:57:14.35#ibcon#end of sib2, iclass 23, count 2 2006.173.14:57:14.35#ibcon#*mode == 0, iclass 23, count 2 2006.173.14:57:14.35#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.14:57:14.35#ibcon#[25=AT07-04\r\n] 2006.173.14:57:14.35#ibcon#*before write, iclass 23, count 2 2006.173.14:57:14.35#ibcon#enter sib2, iclass 23, count 2 2006.173.14:57:14.35#ibcon#flushed, iclass 23, count 2 2006.173.14:57:14.35#ibcon#about to write, iclass 23, count 2 2006.173.14:57:14.35#ibcon#wrote, iclass 23, count 2 2006.173.14:57:14.35#ibcon#about to read 3, iclass 23, count 2 2006.173.14:57:14.38#ibcon#read 3, iclass 23, count 2 2006.173.14:57:14.38#ibcon#about to read 4, iclass 23, count 2 2006.173.14:57:14.38#ibcon#read 4, iclass 23, count 2 2006.173.14:57:14.38#ibcon#about to read 5, iclass 23, count 2 2006.173.14:57:14.38#ibcon#read 5, iclass 23, count 2 2006.173.14:57:14.38#ibcon#about to read 6, iclass 23, count 2 2006.173.14:57:14.38#ibcon#read 6, iclass 23, count 2 2006.173.14:57:14.38#ibcon#end of sib2, iclass 23, count 2 2006.173.14:57:14.38#ibcon#*after write, iclass 23, count 2 2006.173.14:57:14.38#ibcon#*before return 0, iclass 23, count 2 2006.173.14:57:14.38#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.14:57:14.38#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.14:57:14.38#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.14:57:14.38#ibcon#ireg 7 cls_cnt 0 2006.173.14:57:14.38#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.14:57:14.50#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.14:57:14.50#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.14:57:14.50#ibcon#enter wrdev, iclass 23, count 0 2006.173.14:57:14.50#ibcon#first serial, iclass 23, count 0 2006.173.14:57:14.50#ibcon#enter sib2, iclass 23, count 0 2006.173.14:57:14.50#ibcon#flushed, iclass 23, count 0 2006.173.14:57:14.50#ibcon#about to write, iclass 23, count 0 2006.173.14:57:14.50#ibcon#wrote, iclass 23, count 0 2006.173.14:57:14.50#ibcon#about to read 3, iclass 23, count 0 2006.173.14:57:14.52#ibcon#read 3, iclass 23, count 0 2006.173.14:57:14.52#ibcon#about to read 4, iclass 23, count 0 2006.173.14:57:14.52#ibcon#read 4, iclass 23, count 0 2006.173.14:57:14.52#ibcon#about to read 5, iclass 23, count 0 2006.173.14:57:14.52#ibcon#read 5, iclass 23, count 0 2006.173.14:57:14.52#ibcon#about to read 6, iclass 23, count 0 2006.173.14:57:14.52#ibcon#read 6, iclass 23, count 0 2006.173.14:57:14.52#ibcon#end of sib2, iclass 23, count 0 2006.173.14:57:14.52#ibcon#*mode == 0, iclass 23, count 0 2006.173.14:57:14.52#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.14:57:14.52#ibcon#[25=USB\r\n] 2006.173.14:57:14.52#ibcon#*before write, iclass 23, count 0 2006.173.14:57:14.52#ibcon#enter sib2, iclass 23, count 0 2006.173.14:57:14.52#ibcon#flushed, iclass 23, count 0 2006.173.14:57:14.52#ibcon#about to write, iclass 23, count 0 2006.173.14:57:14.52#ibcon#wrote, iclass 23, count 0 2006.173.14:57:14.52#ibcon#about to read 3, iclass 23, count 0 2006.173.14:57:14.55#ibcon#read 3, iclass 23, count 0 2006.173.14:57:14.55#ibcon#about to read 4, iclass 23, count 0 2006.173.14:57:14.55#ibcon#read 4, iclass 23, count 0 2006.173.14:57:14.55#ibcon#about to read 5, iclass 23, count 0 2006.173.14:57:14.55#ibcon#read 5, iclass 23, count 0 2006.173.14:57:14.55#ibcon#about to read 6, iclass 23, count 0 2006.173.14:57:14.55#ibcon#read 6, iclass 23, count 0 2006.173.14:57:14.55#ibcon#end of sib2, iclass 23, count 0 2006.173.14:57:14.55#ibcon#*after write, iclass 23, count 0 2006.173.14:57:14.55#ibcon#*before return 0, iclass 23, count 0 2006.173.14:57:14.55#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.14:57:14.55#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.14:57:14.55#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.14:57:14.55#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.14:57:14.55$vck44/valo=8,884.99 2006.173.14:57:14.55#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.14:57:14.55#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.14:57:14.55#ibcon#ireg 17 cls_cnt 0 2006.173.14:57:14.55#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.14:57:14.55#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.14:57:14.55#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.14:57:14.55#ibcon#enter wrdev, iclass 25, count 0 2006.173.14:57:14.55#ibcon#first serial, iclass 25, count 0 2006.173.14:57:14.55#ibcon#enter sib2, iclass 25, count 0 2006.173.14:57:14.55#ibcon#flushed, iclass 25, count 0 2006.173.14:57:14.55#ibcon#about to write, iclass 25, count 0 2006.173.14:57:14.55#ibcon#wrote, iclass 25, count 0 2006.173.14:57:14.55#ibcon#about to read 3, iclass 25, count 0 2006.173.14:57:14.57#ibcon#read 3, iclass 25, count 0 2006.173.14:57:14.57#ibcon#about to read 4, iclass 25, count 0 2006.173.14:57:14.57#ibcon#read 4, iclass 25, count 0 2006.173.14:57:14.57#ibcon#about to read 5, iclass 25, count 0 2006.173.14:57:14.57#ibcon#read 5, iclass 25, count 0 2006.173.14:57:14.57#ibcon#about to read 6, iclass 25, count 0 2006.173.14:57:14.57#ibcon#read 6, iclass 25, count 0 2006.173.14:57:14.57#ibcon#end of sib2, iclass 25, count 0 2006.173.14:57:14.57#ibcon#*mode == 0, iclass 25, count 0 2006.173.14:57:14.57#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.14:57:14.57#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.14:57:14.57#ibcon#*before write, iclass 25, count 0 2006.173.14:57:14.57#ibcon#enter sib2, iclass 25, count 0 2006.173.14:57:14.57#ibcon#flushed, iclass 25, count 0 2006.173.14:57:14.57#ibcon#about to write, iclass 25, count 0 2006.173.14:57:14.57#ibcon#wrote, iclass 25, count 0 2006.173.14:57:14.57#ibcon#about to read 3, iclass 25, count 0 2006.173.14:57:14.61#ibcon#read 3, iclass 25, count 0 2006.173.14:57:14.61#ibcon#about to read 4, iclass 25, count 0 2006.173.14:57:14.61#ibcon#read 4, iclass 25, count 0 2006.173.14:57:14.61#ibcon#about to read 5, iclass 25, count 0 2006.173.14:57:14.61#ibcon#read 5, iclass 25, count 0 2006.173.14:57:14.61#ibcon#about to read 6, iclass 25, count 0 2006.173.14:57:14.61#ibcon#read 6, iclass 25, count 0 2006.173.14:57:14.61#ibcon#end of sib2, iclass 25, count 0 2006.173.14:57:14.61#ibcon#*after write, iclass 25, count 0 2006.173.14:57:14.61#ibcon#*before return 0, iclass 25, count 0 2006.173.14:57:14.61#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.14:57:14.61#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.14:57:14.61#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.14:57:14.61#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.14:57:14.61$vck44/va=8,4 2006.173.14:57:14.61#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.14:57:14.61#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.14:57:14.61#ibcon#ireg 11 cls_cnt 2 2006.173.14:57:14.61#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.14:57:14.67#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.14:57:14.67#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.14:57:14.67#ibcon#enter wrdev, iclass 27, count 2 2006.173.14:57:14.67#ibcon#first serial, iclass 27, count 2 2006.173.14:57:14.67#ibcon#enter sib2, iclass 27, count 2 2006.173.14:57:14.67#ibcon#flushed, iclass 27, count 2 2006.173.14:57:14.67#ibcon#about to write, iclass 27, count 2 2006.173.14:57:14.67#ibcon#wrote, iclass 27, count 2 2006.173.14:57:14.67#ibcon#about to read 3, iclass 27, count 2 2006.173.14:57:14.69#ibcon#read 3, iclass 27, count 2 2006.173.14:57:14.69#ibcon#about to read 4, iclass 27, count 2 2006.173.14:57:14.69#ibcon#read 4, iclass 27, count 2 2006.173.14:57:14.69#ibcon#about to read 5, iclass 27, count 2 2006.173.14:57:14.69#ibcon#read 5, iclass 27, count 2 2006.173.14:57:14.69#ibcon#about to read 6, iclass 27, count 2 2006.173.14:57:14.69#ibcon#read 6, iclass 27, count 2 2006.173.14:57:14.69#ibcon#end of sib2, iclass 27, count 2 2006.173.14:57:14.69#ibcon#*mode == 0, iclass 27, count 2 2006.173.14:57:14.69#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.14:57:14.69#ibcon#[25=AT08-04\r\n] 2006.173.14:57:14.69#ibcon#*before write, iclass 27, count 2 2006.173.14:57:14.69#ibcon#enter sib2, iclass 27, count 2 2006.173.14:57:14.69#ibcon#flushed, iclass 27, count 2 2006.173.14:57:14.69#ibcon#about to write, iclass 27, count 2 2006.173.14:57:14.69#ibcon#wrote, iclass 27, count 2 2006.173.14:57:14.69#ibcon#about to read 3, iclass 27, count 2 2006.173.14:57:14.72#ibcon#read 3, iclass 27, count 2 2006.173.14:57:14.72#ibcon#about to read 4, iclass 27, count 2 2006.173.14:57:14.72#ibcon#read 4, iclass 27, count 2 2006.173.14:57:14.72#ibcon#about to read 5, iclass 27, count 2 2006.173.14:57:14.72#ibcon#read 5, iclass 27, count 2 2006.173.14:57:14.72#ibcon#about to read 6, iclass 27, count 2 2006.173.14:57:14.72#ibcon#read 6, iclass 27, count 2 2006.173.14:57:14.72#ibcon#end of sib2, iclass 27, count 2 2006.173.14:57:14.72#ibcon#*after write, iclass 27, count 2 2006.173.14:57:14.72#ibcon#*before return 0, iclass 27, count 2 2006.173.14:57:14.72#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.14:57:14.72#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.14:57:14.72#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.14:57:14.72#ibcon#ireg 7 cls_cnt 0 2006.173.14:57:14.72#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.14:57:14.84#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.14:57:14.84#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.14:57:14.84#ibcon#enter wrdev, iclass 27, count 0 2006.173.14:57:14.84#ibcon#first serial, iclass 27, count 0 2006.173.14:57:14.84#ibcon#enter sib2, iclass 27, count 0 2006.173.14:57:14.84#ibcon#flushed, iclass 27, count 0 2006.173.14:57:14.84#ibcon#about to write, iclass 27, count 0 2006.173.14:57:14.84#ibcon#wrote, iclass 27, count 0 2006.173.14:57:14.84#ibcon#about to read 3, iclass 27, count 0 2006.173.14:57:14.86#ibcon#read 3, iclass 27, count 0 2006.173.14:57:14.86#ibcon#about to read 4, iclass 27, count 0 2006.173.14:57:14.86#ibcon#read 4, iclass 27, count 0 2006.173.14:57:14.86#ibcon#about to read 5, iclass 27, count 0 2006.173.14:57:14.86#ibcon#read 5, iclass 27, count 0 2006.173.14:57:14.86#ibcon#about to read 6, iclass 27, count 0 2006.173.14:57:14.86#ibcon#read 6, iclass 27, count 0 2006.173.14:57:14.86#ibcon#end of sib2, iclass 27, count 0 2006.173.14:57:14.86#ibcon#*mode == 0, iclass 27, count 0 2006.173.14:57:14.86#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.14:57:14.86#ibcon#[25=USB\r\n] 2006.173.14:57:14.86#ibcon#*before write, iclass 27, count 0 2006.173.14:57:14.86#ibcon#enter sib2, iclass 27, count 0 2006.173.14:57:14.86#ibcon#flushed, iclass 27, count 0 2006.173.14:57:14.86#ibcon#about to write, iclass 27, count 0 2006.173.14:57:14.86#ibcon#wrote, iclass 27, count 0 2006.173.14:57:14.86#ibcon#about to read 3, iclass 27, count 0 2006.173.14:57:14.89#ibcon#read 3, iclass 27, count 0 2006.173.14:57:14.89#ibcon#about to read 4, iclass 27, count 0 2006.173.14:57:14.89#ibcon#read 4, iclass 27, count 0 2006.173.14:57:14.89#ibcon#about to read 5, iclass 27, count 0 2006.173.14:57:14.89#ibcon#read 5, iclass 27, count 0 2006.173.14:57:14.89#ibcon#about to read 6, iclass 27, count 0 2006.173.14:57:14.89#ibcon#read 6, iclass 27, count 0 2006.173.14:57:14.89#ibcon#end of sib2, iclass 27, count 0 2006.173.14:57:14.89#ibcon#*after write, iclass 27, count 0 2006.173.14:57:14.89#ibcon#*before return 0, iclass 27, count 0 2006.173.14:57:14.89#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.14:57:14.89#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.14:57:14.89#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.14:57:14.89#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.14:57:14.89$vck44/vblo=1,629.99 2006.173.14:57:14.89#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.14:57:14.89#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.14:57:14.89#ibcon#ireg 17 cls_cnt 0 2006.173.14:57:14.89#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.14:57:14.89#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.14:57:14.89#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.14:57:14.89#ibcon#enter wrdev, iclass 29, count 0 2006.173.14:57:14.89#ibcon#first serial, iclass 29, count 0 2006.173.14:57:14.89#ibcon#enter sib2, iclass 29, count 0 2006.173.14:57:14.89#ibcon#flushed, iclass 29, count 0 2006.173.14:57:14.89#ibcon#about to write, iclass 29, count 0 2006.173.14:57:14.89#ibcon#wrote, iclass 29, count 0 2006.173.14:57:14.89#ibcon#about to read 3, iclass 29, count 0 2006.173.14:57:14.91#ibcon#read 3, iclass 29, count 0 2006.173.14:57:14.91#ibcon#about to read 4, iclass 29, count 0 2006.173.14:57:14.91#ibcon#read 4, iclass 29, count 0 2006.173.14:57:14.91#ibcon#about to read 5, iclass 29, count 0 2006.173.14:57:14.91#ibcon#read 5, iclass 29, count 0 2006.173.14:57:14.91#ibcon#about to read 6, iclass 29, count 0 2006.173.14:57:14.91#ibcon#read 6, iclass 29, count 0 2006.173.14:57:14.91#ibcon#end of sib2, iclass 29, count 0 2006.173.14:57:14.91#ibcon#*mode == 0, iclass 29, count 0 2006.173.14:57:14.91#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.14:57:14.91#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.14:57:14.91#ibcon#*before write, iclass 29, count 0 2006.173.14:57:14.91#ibcon#enter sib2, iclass 29, count 0 2006.173.14:57:14.91#ibcon#flushed, iclass 29, count 0 2006.173.14:57:14.91#ibcon#about to write, iclass 29, count 0 2006.173.14:57:14.91#ibcon#wrote, iclass 29, count 0 2006.173.14:57:14.91#ibcon#about to read 3, iclass 29, count 0 2006.173.14:57:14.95#ibcon#read 3, iclass 29, count 0 2006.173.14:57:14.95#ibcon#about to read 4, iclass 29, count 0 2006.173.14:57:14.95#ibcon#read 4, iclass 29, count 0 2006.173.14:57:14.95#ibcon#about to read 5, iclass 29, count 0 2006.173.14:57:14.95#ibcon#read 5, iclass 29, count 0 2006.173.14:57:14.95#ibcon#about to read 6, iclass 29, count 0 2006.173.14:57:14.95#ibcon#read 6, iclass 29, count 0 2006.173.14:57:14.95#ibcon#end of sib2, iclass 29, count 0 2006.173.14:57:14.95#ibcon#*after write, iclass 29, count 0 2006.173.14:57:14.95#ibcon#*before return 0, iclass 29, count 0 2006.173.14:57:14.95#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.14:57:14.95#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.14:57:14.95#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.14:57:14.95#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.14:57:14.95$vck44/vb=1,4 2006.173.14:57:14.95#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.14:57:14.95#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.14:57:14.95#ibcon#ireg 11 cls_cnt 2 2006.173.14:57:14.95#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.14:57:14.95#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.14:57:14.95#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.14:57:14.95#ibcon#enter wrdev, iclass 31, count 2 2006.173.14:57:14.95#ibcon#first serial, iclass 31, count 2 2006.173.14:57:14.95#ibcon#enter sib2, iclass 31, count 2 2006.173.14:57:14.95#ibcon#flushed, iclass 31, count 2 2006.173.14:57:14.95#ibcon#about to write, iclass 31, count 2 2006.173.14:57:14.95#ibcon#wrote, iclass 31, count 2 2006.173.14:57:14.95#ibcon#about to read 3, iclass 31, count 2 2006.173.14:57:14.97#ibcon#read 3, iclass 31, count 2 2006.173.14:57:14.97#ibcon#about to read 4, iclass 31, count 2 2006.173.14:57:14.97#ibcon#read 4, iclass 31, count 2 2006.173.14:57:14.97#ibcon#about to read 5, iclass 31, count 2 2006.173.14:57:14.97#ibcon#read 5, iclass 31, count 2 2006.173.14:57:14.97#ibcon#about to read 6, iclass 31, count 2 2006.173.14:57:14.97#ibcon#read 6, iclass 31, count 2 2006.173.14:57:14.97#ibcon#end of sib2, iclass 31, count 2 2006.173.14:57:14.97#ibcon#*mode == 0, iclass 31, count 2 2006.173.14:57:14.97#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.14:57:14.97#ibcon#[27=AT01-04\r\n] 2006.173.14:57:14.97#ibcon#*before write, iclass 31, count 2 2006.173.14:57:14.97#ibcon#enter sib2, iclass 31, count 2 2006.173.14:57:14.97#ibcon#flushed, iclass 31, count 2 2006.173.14:57:14.97#ibcon#about to write, iclass 31, count 2 2006.173.14:57:14.97#ibcon#wrote, iclass 31, count 2 2006.173.14:57:14.97#ibcon#about to read 3, iclass 31, count 2 2006.173.14:57:15.00#ibcon#read 3, iclass 31, count 2 2006.173.14:57:15.00#ibcon#about to read 4, iclass 31, count 2 2006.173.14:57:15.00#ibcon#read 4, iclass 31, count 2 2006.173.14:57:15.00#ibcon#about to read 5, iclass 31, count 2 2006.173.14:57:15.00#ibcon#read 5, iclass 31, count 2 2006.173.14:57:15.00#ibcon#about to read 6, iclass 31, count 2 2006.173.14:57:15.00#ibcon#read 6, iclass 31, count 2 2006.173.14:57:15.00#ibcon#end of sib2, iclass 31, count 2 2006.173.14:57:15.00#ibcon#*after write, iclass 31, count 2 2006.173.14:57:15.00#ibcon#*before return 0, iclass 31, count 2 2006.173.14:57:15.00#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.14:57:15.00#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.14:57:15.00#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.14:57:15.00#ibcon#ireg 7 cls_cnt 0 2006.173.14:57:15.00#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.14:57:15.12#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.14:57:15.12#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.14:57:15.12#ibcon#enter wrdev, iclass 31, count 0 2006.173.14:57:15.12#ibcon#first serial, iclass 31, count 0 2006.173.14:57:15.12#ibcon#enter sib2, iclass 31, count 0 2006.173.14:57:15.12#ibcon#flushed, iclass 31, count 0 2006.173.14:57:15.12#ibcon#about to write, iclass 31, count 0 2006.173.14:57:15.12#ibcon#wrote, iclass 31, count 0 2006.173.14:57:15.12#ibcon#about to read 3, iclass 31, count 0 2006.173.14:57:15.14#ibcon#read 3, iclass 31, count 0 2006.173.14:57:15.14#ibcon#about to read 4, iclass 31, count 0 2006.173.14:57:15.14#ibcon#read 4, iclass 31, count 0 2006.173.14:57:15.14#ibcon#about to read 5, iclass 31, count 0 2006.173.14:57:15.14#ibcon#read 5, iclass 31, count 0 2006.173.14:57:15.14#ibcon#about to read 6, iclass 31, count 0 2006.173.14:57:15.14#ibcon#read 6, iclass 31, count 0 2006.173.14:57:15.14#ibcon#end of sib2, iclass 31, count 0 2006.173.14:57:15.14#ibcon#*mode == 0, iclass 31, count 0 2006.173.14:57:15.14#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.14:57:15.14#ibcon#[27=USB\r\n] 2006.173.14:57:15.14#ibcon#*before write, iclass 31, count 0 2006.173.14:57:15.14#ibcon#enter sib2, iclass 31, count 0 2006.173.14:57:15.14#ibcon#flushed, iclass 31, count 0 2006.173.14:57:15.14#ibcon#about to write, iclass 31, count 0 2006.173.14:57:15.14#ibcon#wrote, iclass 31, count 0 2006.173.14:57:15.14#ibcon#about to read 3, iclass 31, count 0 2006.173.14:57:15.17#ibcon#read 3, iclass 31, count 0 2006.173.14:57:15.17#ibcon#about to read 4, iclass 31, count 0 2006.173.14:57:15.17#ibcon#read 4, iclass 31, count 0 2006.173.14:57:15.17#ibcon#about to read 5, iclass 31, count 0 2006.173.14:57:15.17#ibcon#read 5, iclass 31, count 0 2006.173.14:57:15.17#ibcon#about to read 6, iclass 31, count 0 2006.173.14:57:15.17#ibcon#read 6, iclass 31, count 0 2006.173.14:57:15.17#ibcon#end of sib2, iclass 31, count 0 2006.173.14:57:15.17#ibcon#*after write, iclass 31, count 0 2006.173.14:57:15.17#ibcon#*before return 0, iclass 31, count 0 2006.173.14:57:15.17#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.14:57:15.17#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.14:57:15.17#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.14:57:15.17#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.14:57:15.17$vck44/vblo=2,634.99 2006.173.14:57:15.17#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.14:57:15.17#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.14:57:15.17#ibcon#ireg 17 cls_cnt 0 2006.173.14:57:15.17#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.14:57:15.17#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.14:57:15.17#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.14:57:15.17#ibcon#enter wrdev, iclass 33, count 0 2006.173.14:57:15.17#ibcon#first serial, iclass 33, count 0 2006.173.14:57:15.17#ibcon#enter sib2, iclass 33, count 0 2006.173.14:57:15.17#ibcon#flushed, iclass 33, count 0 2006.173.14:57:15.17#ibcon#about to write, iclass 33, count 0 2006.173.14:57:15.17#ibcon#wrote, iclass 33, count 0 2006.173.14:57:15.17#ibcon#about to read 3, iclass 33, count 0 2006.173.14:57:15.19#ibcon#read 3, iclass 33, count 0 2006.173.14:57:15.19#ibcon#about to read 4, iclass 33, count 0 2006.173.14:57:15.19#ibcon#read 4, iclass 33, count 0 2006.173.14:57:15.19#ibcon#about to read 5, iclass 33, count 0 2006.173.14:57:15.19#ibcon#read 5, iclass 33, count 0 2006.173.14:57:15.19#ibcon#about to read 6, iclass 33, count 0 2006.173.14:57:15.19#ibcon#read 6, iclass 33, count 0 2006.173.14:57:15.19#ibcon#end of sib2, iclass 33, count 0 2006.173.14:57:15.19#ibcon#*mode == 0, iclass 33, count 0 2006.173.14:57:15.19#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.14:57:15.19#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.14:57:15.19#ibcon#*before write, iclass 33, count 0 2006.173.14:57:15.19#ibcon#enter sib2, iclass 33, count 0 2006.173.14:57:15.19#ibcon#flushed, iclass 33, count 0 2006.173.14:57:15.19#ibcon#about to write, iclass 33, count 0 2006.173.14:57:15.19#ibcon#wrote, iclass 33, count 0 2006.173.14:57:15.19#ibcon#about to read 3, iclass 33, count 0 2006.173.14:57:15.23#ibcon#read 3, iclass 33, count 0 2006.173.14:57:15.23#ibcon#about to read 4, iclass 33, count 0 2006.173.14:57:15.23#ibcon#read 4, iclass 33, count 0 2006.173.14:57:15.23#ibcon#about to read 5, iclass 33, count 0 2006.173.14:57:15.23#ibcon#read 5, iclass 33, count 0 2006.173.14:57:15.23#ibcon#about to read 6, iclass 33, count 0 2006.173.14:57:15.23#ibcon#read 6, iclass 33, count 0 2006.173.14:57:15.23#ibcon#end of sib2, iclass 33, count 0 2006.173.14:57:15.23#ibcon#*after write, iclass 33, count 0 2006.173.14:57:15.23#ibcon#*before return 0, iclass 33, count 0 2006.173.14:57:15.23#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.14:57:15.23#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.14:57:15.23#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.14:57:15.23#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.14:57:15.23$vck44/vb=2,4 2006.173.14:57:15.23#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.14:57:15.23#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.14:57:15.23#ibcon#ireg 11 cls_cnt 2 2006.173.14:57:15.23#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.14:57:15.29#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.14:57:15.29#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.14:57:15.29#ibcon#enter wrdev, iclass 35, count 2 2006.173.14:57:15.29#ibcon#first serial, iclass 35, count 2 2006.173.14:57:15.29#ibcon#enter sib2, iclass 35, count 2 2006.173.14:57:15.29#ibcon#flushed, iclass 35, count 2 2006.173.14:57:15.29#ibcon#about to write, iclass 35, count 2 2006.173.14:57:15.29#ibcon#wrote, iclass 35, count 2 2006.173.14:57:15.29#ibcon#about to read 3, iclass 35, count 2 2006.173.14:57:15.31#ibcon#read 3, iclass 35, count 2 2006.173.14:57:15.31#ibcon#about to read 4, iclass 35, count 2 2006.173.14:57:15.31#ibcon#read 4, iclass 35, count 2 2006.173.14:57:15.31#ibcon#about to read 5, iclass 35, count 2 2006.173.14:57:15.31#ibcon#read 5, iclass 35, count 2 2006.173.14:57:15.31#ibcon#about to read 6, iclass 35, count 2 2006.173.14:57:15.31#ibcon#read 6, iclass 35, count 2 2006.173.14:57:15.31#ibcon#end of sib2, iclass 35, count 2 2006.173.14:57:15.31#ibcon#*mode == 0, iclass 35, count 2 2006.173.14:57:15.31#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.14:57:15.31#ibcon#[27=AT02-04\r\n] 2006.173.14:57:15.31#ibcon#*before write, iclass 35, count 2 2006.173.14:57:15.31#ibcon#enter sib2, iclass 35, count 2 2006.173.14:57:15.31#ibcon#flushed, iclass 35, count 2 2006.173.14:57:15.31#ibcon#about to write, iclass 35, count 2 2006.173.14:57:15.31#ibcon#wrote, iclass 35, count 2 2006.173.14:57:15.31#ibcon#about to read 3, iclass 35, count 2 2006.173.14:57:15.34#ibcon#read 3, iclass 35, count 2 2006.173.14:57:15.34#ibcon#about to read 4, iclass 35, count 2 2006.173.14:57:15.34#ibcon#read 4, iclass 35, count 2 2006.173.14:57:15.34#ibcon#about to read 5, iclass 35, count 2 2006.173.14:57:15.34#ibcon#read 5, iclass 35, count 2 2006.173.14:57:15.34#ibcon#about to read 6, iclass 35, count 2 2006.173.14:57:15.34#ibcon#read 6, iclass 35, count 2 2006.173.14:57:15.34#ibcon#end of sib2, iclass 35, count 2 2006.173.14:57:15.34#ibcon#*after write, iclass 35, count 2 2006.173.14:57:15.34#ibcon#*before return 0, iclass 35, count 2 2006.173.14:57:15.34#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.14:57:15.34#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.14:57:15.34#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.14:57:15.34#ibcon#ireg 7 cls_cnt 0 2006.173.14:57:15.34#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.14:57:15.46#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.14:57:15.46#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.14:57:15.46#ibcon#enter wrdev, iclass 35, count 0 2006.173.14:57:15.46#ibcon#first serial, iclass 35, count 0 2006.173.14:57:15.46#ibcon#enter sib2, iclass 35, count 0 2006.173.14:57:15.46#ibcon#flushed, iclass 35, count 0 2006.173.14:57:15.46#ibcon#about to write, iclass 35, count 0 2006.173.14:57:15.46#ibcon#wrote, iclass 35, count 0 2006.173.14:57:15.46#ibcon#about to read 3, iclass 35, count 0 2006.173.14:57:15.48#ibcon#read 3, iclass 35, count 0 2006.173.14:57:15.48#ibcon#about to read 4, iclass 35, count 0 2006.173.14:57:15.48#ibcon#read 4, iclass 35, count 0 2006.173.14:57:15.48#ibcon#about to read 5, iclass 35, count 0 2006.173.14:57:15.48#ibcon#read 5, iclass 35, count 0 2006.173.14:57:15.48#ibcon#about to read 6, iclass 35, count 0 2006.173.14:57:15.48#ibcon#read 6, iclass 35, count 0 2006.173.14:57:15.48#ibcon#end of sib2, iclass 35, count 0 2006.173.14:57:15.48#ibcon#*mode == 0, iclass 35, count 0 2006.173.14:57:15.48#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.14:57:15.48#ibcon#[27=USB\r\n] 2006.173.14:57:15.48#ibcon#*before write, iclass 35, count 0 2006.173.14:57:15.48#ibcon#enter sib2, iclass 35, count 0 2006.173.14:57:15.48#ibcon#flushed, iclass 35, count 0 2006.173.14:57:15.48#ibcon#about to write, iclass 35, count 0 2006.173.14:57:15.48#ibcon#wrote, iclass 35, count 0 2006.173.14:57:15.48#ibcon#about to read 3, iclass 35, count 0 2006.173.14:57:15.51#ibcon#read 3, iclass 35, count 0 2006.173.14:57:15.51#ibcon#about to read 4, iclass 35, count 0 2006.173.14:57:15.51#ibcon#read 4, iclass 35, count 0 2006.173.14:57:15.51#ibcon#about to read 5, iclass 35, count 0 2006.173.14:57:15.51#ibcon#read 5, iclass 35, count 0 2006.173.14:57:15.51#ibcon#about to read 6, iclass 35, count 0 2006.173.14:57:15.51#ibcon#read 6, iclass 35, count 0 2006.173.14:57:15.51#ibcon#end of sib2, iclass 35, count 0 2006.173.14:57:15.51#ibcon#*after write, iclass 35, count 0 2006.173.14:57:15.51#ibcon#*before return 0, iclass 35, count 0 2006.173.14:57:15.51#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.14:57:15.51#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.14:57:15.51#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.14:57:15.51#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.14:57:15.51$vck44/vblo=3,649.99 2006.173.14:57:15.51#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.14:57:15.51#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.14:57:15.51#ibcon#ireg 17 cls_cnt 0 2006.173.14:57:15.51#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.14:57:15.51#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.14:57:15.51#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.14:57:15.51#ibcon#enter wrdev, iclass 37, count 0 2006.173.14:57:15.51#ibcon#first serial, iclass 37, count 0 2006.173.14:57:15.51#ibcon#enter sib2, iclass 37, count 0 2006.173.14:57:15.51#ibcon#flushed, iclass 37, count 0 2006.173.14:57:15.51#ibcon#about to write, iclass 37, count 0 2006.173.14:57:15.51#ibcon#wrote, iclass 37, count 0 2006.173.14:57:15.51#ibcon#about to read 3, iclass 37, count 0 2006.173.14:57:15.53#ibcon#read 3, iclass 37, count 0 2006.173.14:57:15.53#ibcon#about to read 4, iclass 37, count 0 2006.173.14:57:15.53#ibcon#read 4, iclass 37, count 0 2006.173.14:57:15.53#ibcon#about to read 5, iclass 37, count 0 2006.173.14:57:15.53#ibcon#read 5, iclass 37, count 0 2006.173.14:57:15.53#ibcon#about to read 6, iclass 37, count 0 2006.173.14:57:15.53#ibcon#read 6, iclass 37, count 0 2006.173.14:57:15.53#ibcon#end of sib2, iclass 37, count 0 2006.173.14:57:15.53#ibcon#*mode == 0, iclass 37, count 0 2006.173.14:57:15.53#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.14:57:15.53#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.14:57:15.53#ibcon#*before write, iclass 37, count 0 2006.173.14:57:15.53#ibcon#enter sib2, iclass 37, count 0 2006.173.14:57:15.53#ibcon#flushed, iclass 37, count 0 2006.173.14:57:15.53#ibcon#about to write, iclass 37, count 0 2006.173.14:57:15.53#ibcon#wrote, iclass 37, count 0 2006.173.14:57:15.53#ibcon#about to read 3, iclass 37, count 0 2006.173.14:57:15.57#ibcon#read 3, iclass 37, count 0 2006.173.14:57:15.57#ibcon#about to read 4, iclass 37, count 0 2006.173.14:57:15.57#ibcon#read 4, iclass 37, count 0 2006.173.14:57:15.57#ibcon#about to read 5, iclass 37, count 0 2006.173.14:57:15.57#ibcon#read 5, iclass 37, count 0 2006.173.14:57:15.57#ibcon#about to read 6, iclass 37, count 0 2006.173.14:57:15.57#ibcon#read 6, iclass 37, count 0 2006.173.14:57:15.57#ibcon#end of sib2, iclass 37, count 0 2006.173.14:57:15.57#ibcon#*after write, iclass 37, count 0 2006.173.14:57:15.57#ibcon#*before return 0, iclass 37, count 0 2006.173.14:57:15.57#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.14:57:15.57#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.14:57:15.57#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.14:57:15.57#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.14:57:15.57$vck44/vb=3,4 2006.173.14:57:15.57#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.14:57:15.57#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.14:57:15.57#ibcon#ireg 11 cls_cnt 2 2006.173.14:57:15.57#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.14:57:15.63#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.14:57:15.63#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.14:57:15.63#ibcon#enter wrdev, iclass 39, count 2 2006.173.14:57:15.63#ibcon#first serial, iclass 39, count 2 2006.173.14:57:15.63#ibcon#enter sib2, iclass 39, count 2 2006.173.14:57:15.63#ibcon#flushed, iclass 39, count 2 2006.173.14:57:15.63#ibcon#about to write, iclass 39, count 2 2006.173.14:57:15.63#ibcon#wrote, iclass 39, count 2 2006.173.14:57:15.63#ibcon#about to read 3, iclass 39, count 2 2006.173.14:57:15.65#ibcon#read 3, iclass 39, count 2 2006.173.14:57:15.65#ibcon#about to read 4, iclass 39, count 2 2006.173.14:57:15.65#ibcon#read 4, iclass 39, count 2 2006.173.14:57:15.65#ibcon#about to read 5, iclass 39, count 2 2006.173.14:57:15.65#ibcon#read 5, iclass 39, count 2 2006.173.14:57:15.65#ibcon#about to read 6, iclass 39, count 2 2006.173.14:57:15.65#ibcon#read 6, iclass 39, count 2 2006.173.14:57:15.65#ibcon#end of sib2, iclass 39, count 2 2006.173.14:57:15.65#ibcon#*mode == 0, iclass 39, count 2 2006.173.14:57:15.65#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.14:57:15.65#ibcon#[27=AT03-04\r\n] 2006.173.14:57:15.65#ibcon#*before write, iclass 39, count 2 2006.173.14:57:15.65#ibcon#enter sib2, iclass 39, count 2 2006.173.14:57:15.65#ibcon#flushed, iclass 39, count 2 2006.173.14:57:15.65#ibcon#about to write, iclass 39, count 2 2006.173.14:57:15.65#ibcon#wrote, iclass 39, count 2 2006.173.14:57:15.65#ibcon#about to read 3, iclass 39, count 2 2006.173.14:57:15.68#ibcon#read 3, iclass 39, count 2 2006.173.14:57:15.68#ibcon#about to read 4, iclass 39, count 2 2006.173.14:57:15.68#ibcon#read 4, iclass 39, count 2 2006.173.14:57:15.68#ibcon#about to read 5, iclass 39, count 2 2006.173.14:57:15.68#ibcon#read 5, iclass 39, count 2 2006.173.14:57:15.68#ibcon#about to read 6, iclass 39, count 2 2006.173.14:57:15.68#ibcon#read 6, iclass 39, count 2 2006.173.14:57:15.68#ibcon#end of sib2, iclass 39, count 2 2006.173.14:57:15.68#ibcon#*after write, iclass 39, count 2 2006.173.14:57:15.68#ibcon#*before return 0, iclass 39, count 2 2006.173.14:57:15.68#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.14:57:15.68#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.14:57:15.68#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.14:57:15.68#ibcon#ireg 7 cls_cnt 0 2006.173.14:57:15.68#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.14:57:15.80#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.14:57:15.80#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.14:57:15.80#ibcon#enter wrdev, iclass 39, count 0 2006.173.14:57:15.80#ibcon#first serial, iclass 39, count 0 2006.173.14:57:15.80#ibcon#enter sib2, iclass 39, count 0 2006.173.14:57:15.80#ibcon#flushed, iclass 39, count 0 2006.173.14:57:15.80#ibcon#about to write, iclass 39, count 0 2006.173.14:57:15.80#ibcon#wrote, iclass 39, count 0 2006.173.14:57:15.80#ibcon#about to read 3, iclass 39, count 0 2006.173.14:57:15.82#ibcon#read 3, iclass 39, count 0 2006.173.14:57:15.82#ibcon#about to read 4, iclass 39, count 0 2006.173.14:57:15.82#ibcon#read 4, iclass 39, count 0 2006.173.14:57:15.82#ibcon#about to read 5, iclass 39, count 0 2006.173.14:57:15.82#ibcon#read 5, iclass 39, count 0 2006.173.14:57:15.82#ibcon#about to read 6, iclass 39, count 0 2006.173.14:57:15.82#ibcon#read 6, iclass 39, count 0 2006.173.14:57:15.82#ibcon#end of sib2, iclass 39, count 0 2006.173.14:57:15.82#ibcon#*mode == 0, iclass 39, count 0 2006.173.14:57:15.82#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.14:57:15.82#ibcon#[27=USB\r\n] 2006.173.14:57:15.82#ibcon#*before write, iclass 39, count 0 2006.173.14:57:15.82#ibcon#enter sib2, iclass 39, count 0 2006.173.14:57:15.82#ibcon#flushed, iclass 39, count 0 2006.173.14:57:15.82#ibcon#about to write, iclass 39, count 0 2006.173.14:57:15.82#ibcon#wrote, iclass 39, count 0 2006.173.14:57:15.82#ibcon#about to read 3, iclass 39, count 0 2006.173.14:57:15.85#ibcon#read 3, iclass 39, count 0 2006.173.14:57:15.85#ibcon#about to read 4, iclass 39, count 0 2006.173.14:57:15.85#ibcon#read 4, iclass 39, count 0 2006.173.14:57:15.85#ibcon#about to read 5, iclass 39, count 0 2006.173.14:57:15.85#ibcon#read 5, iclass 39, count 0 2006.173.14:57:15.85#ibcon#about to read 6, iclass 39, count 0 2006.173.14:57:15.85#ibcon#read 6, iclass 39, count 0 2006.173.14:57:15.85#ibcon#end of sib2, iclass 39, count 0 2006.173.14:57:15.85#ibcon#*after write, iclass 39, count 0 2006.173.14:57:15.85#ibcon#*before return 0, iclass 39, count 0 2006.173.14:57:15.85#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.14:57:15.85#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.14:57:15.85#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.14:57:15.85#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.14:57:15.85$vck44/vblo=4,679.99 2006.173.14:57:15.85#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.14:57:15.85#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.14:57:15.85#ibcon#ireg 17 cls_cnt 0 2006.173.14:57:15.85#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.14:57:15.85#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.14:57:15.85#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.14:57:15.85#ibcon#enter wrdev, iclass 3, count 0 2006.173.14:57:15.85#ibcon#first serial, iclass 3, count 0 2006.173.14:57:15.85#ibcon#enter sib2, iclass 3, count 0 2006.173.14:57:15.85#ibcon#flushed, iclass 3, count 0 2006.173.14:57:15.85#ibcon#about to write, iclass 3, count 0 2006.173.14:57:15.85#ibcon#wrote, iclass 3, count 0 2006.173.14:57:15.85#ibcon#about to read 3, iclass 3, count 0 2006.173.14:57:15.87#ibcon#read 3, iclass 3, count 0 2006.173.14:57:15.87#ibcon#about to read 4, iclass 3, count 0 2006.173.14:57:15.87#ibcon#read 4, iclass 3, count 0 2006.173.14:57:15.87#ibcon#about to read 5, iclass 3, count 0 2006.173.14:57:15.87#ibcon#read 5, iclass 3, count 0 2006.173.14:57:15.87#ibcon#about to read 6, iclass 3, count 0 2006.173.14:57:15.87#ibcon#read 6, iclass 3, count 0 2006.173.14:57:15.87#ibcon#end of sib2, iclass 3, count 0 2006.173.14:57:15.87#ibcon#*mode == 0, iclass 3, count 0 2006.173.14:57:15.87#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.14:57:15.87#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.14:57:15.87#ibcon#*before write, iclass 3, count 0 2006.173.14:57:15.87#ibcon#enter sib2, iclass 3, count 0 2006.173.14:57:15.87#ibcon#flushed, iclass 3, count 0 2006.173.14:57:15.87#ibcon#about to write, iclass 3, count 0 2006.173.14:57:15.87#ibcon#wrote, iclass 3, count 0 2006.173.14:57:15.87#ibcon#about to read 3, iclass 3, count 0 2006.173.14:57:15.91#ibcon#read 3, iclass 3, count 0 2006.173.14:57:15.91#ibcon#about to read 4, iclass 3, count 0 2006.173.14:57:15.91#ibcon#read 4, iclass 3, count 0 2006.173.14:57:15.91#ibcon#about to read 5, iclass 3, count 0 2006.173.14:57:15.91#ibcon#read 5, iclass 3, count 0 2006.173.14:57:15.91#ibcon#about to read 6, iclass 3, count 0 2006.173.14:57:15.91#ibcon#read 6, iclass 3, count 0 2006.173.14:57:15.91#ibcon#end of sib2, iclass 3, count 0 2006.173.14:57:15.91#ibcon#*after write, iclass 3, count 0 2006.173.14:57:15.91#ibcon#*before return 0, iclass 3, count 0 2006.173.14:57:15.91#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.14:57:15.91#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.14:57:15.91#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.14:57:15.91#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.14:57:15.91$vck44/vb=4,4 2006.173.14:57:15.91#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.14:57:15.91#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.14:57:15.91#ibcon#ireg 11 cls_cnt 2 2006.173.14:57:15.91#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.14:57:15.97#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.14:57:15.97#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.14:57:15.97#ibcon#enter wrdev, iclass 5, count 2 2006.173.14:57:15.97#ibcon#first serial, iclass 5, count 2 2006.173.14:57:15.97#ibcon#enter sib2, iclass 5, count 2 2006.173.14:57:15.97#ibcon#flushed, iclass 5, count 2 2006.173.14:57:15.97#ibcon#about to write, iclass 5, count 2 2006.173.14:57:15.97#ibcon#wrote, iclass 5, count 2 2006.173.14:57:15.97#ibcon#about to read 3, iclass 5, count 2 2006.173.14:57:15.99#ibcon#read 3, iclass 5, count 2 2006.173.14:57:15.99#ibcon#about to read 4, iclass 5, count 2 2006.173.14:57:15.99#ibcon#read 4, iclass 5, count 2 2006.173.14:57:15.99#ibcon#about to read 5, iclass 5, count 2 2006.173.14:57:15.99#ibcon#read 5, iclass 5, count 2 2006.173.14:57:15.99#ibcon#about to read 6, iclass 5, count 2 2006.173.14:57:15.99#ibcon#read 6, iclass 5, count 2 2006.173.14:57:15.99#ibcon#end of sib2, iclass 5, count 2 2006.173.14:57:15.99#ibcon#*mode == 0, iclass 5, count 2 2006.173.14:57:15.99#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.14:57:15.99#ibcon#[27=AT04-04\r\n] 2006.173.14:57:15.99#ibcon#*before write, iclass 5, count 2 2006.173.14:57:15.99#ibcon#enter sib2, iclass 5, count 2 2006.173.14:57:15.99#ibcon#flushed, iclass 5, count 2 2006.173.14:57:15.99#ibcon#about to write, iclass 5, count 2 2006.173.14:57:15.99#ibcon#wrote, iclass 5, count 2 2006.173.14:57:15.99#ibcon#about to read 3, iclass 5, count 2 2006.173.14:57:16.02#ibcon#read 3, iclass 5, count 2 2006.173.14:57:16.02#ibcon#about to read 4, iclass 5, count 2 2006.173.14:57:16.02#ibcon#read 4, iclass 5, count 2 2006.173.14:57:16.02#ibcon#about to read 5, iclass 5, count 2 2006.173.14:57:16.02#ibcon#read 5, iclass 5, count 2 2006.173.14:57:16.02#ibcon#about to read 6, iclass 5, count 2 2006.173.14:57:16.02#ibcon#read 6, iclass 5, count 2 2006.173.14:57:16.02#ibcon#end of sib2, iclass 5, count 2 2006.173.14:57:16.02#ibcon#*after write, iclass 5, count 2 2006.173.14:57:16.02#ibcon#*before return 0, iclass 5, count 2 2006.173.14:57:16.02#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.14:57:16.02#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.14:57:16.02#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.14:57:16.02#ibcon#ireg 7 cls_cnt 0 2006.173.14:57:16.02#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.14:57:16.14#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.14:57:16.14#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.14:57:16.14#ibcon#enter wrdev, iclass 5, count 0 2006.173.14:57:16.14#ibcon#first serial, iclass 5, count 0 2006.173.14:57:16.14#ibcon#enter sib2, iclass 5, count 0 2006.173.14:57:16.14#ibcon#flushed, iclass 5, count 0 2006.173.14:57:16.14#ibcon#about to write, iclass 5, count 0 2006.173.14:57:16.14#ibcon#wrote, iclass 5, count 0 2006.173.14:57:16.14#ibcon#about to read 3, iclass 5, count 0 2006.173.14:57:16.16#ibcon#read 3, iclass 5, count 0 2006.173.14:57:16.16#ibcon#about to read 4, iclass 5, count 0 2006.173.14:57:16.16#ibcon#read 4, iclass 5, count 0 2006.173.14:57:16.16#ibcon#about to read 5, iclass 5, count 0 2006.173.14:57:16.16#ibcon#read 5, iclass 5, count 0 2006.173.14:57:16.16#ibcon#about to read 6, iclass 5, count 0 2006.173.14:57:16.16#ibcon#read 6, iclass 5, count 0 2006.173.14:57:16.16#ibcon#end of sib2, iclass 5, count 0 2006.173.14:57:16.16#ibcon#*mode == 0, iclass 5, count 0 2006.173.14:57:16.16#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.14:57:16.16#ibcon#[27=USB\r\n] 2006.173.14:57:16.16#ibcon#*before write, iclass 5, count 0 2006.173.14:57:16.16#ibcon#enter sib2, iclass 5, count 0 2006.173.14:57:16.16#ibcon#flushed, iclass 5, count 0 2006.173.14:57:16.16#ibcon#about to write, iclass 5, count 0 2006.173.14:57:16.16#ibcon#wrote, iclass 5, count 0 2006.173.14:57:16.16#ibcon#about to read 3, iclass 5, count 0 2006.173.14:57:16.19#ibcon#read 3, iclass 5, count 0 2006.173.14:57:16.19#ibcon#about to read 4, iclass 5, count 0 2006.173.14:57:16.19#ibcon#read 4, iclass 5, count 0 2006.173.14:57:16.19#ibcon#about to read 5, iclass 5, count 0 2006.173.14:57:16.19#ibcon#read 5, iclass 5, count 0 2006.173.14:57:16.19#ibcon#about to read 6, iclass 5, count 0 2006.173.14:57:16.19#ibcon#read 6, iclass 5, count 0 2006.173.14:57:16.19#ibcon#end of sib2, iclass 5, count 0 2006.173.14:57:16.19#ibcon#*after write, iclass 5, count 0 2006.173.14:57:16.19#ibcon#*before return 0, iclass 5, count 0 2006.173.14:57:16.19#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.14:57:16.19#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.14:57:16.19#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.14:57:16.19#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.14:57:16.19$vck44/vblo=5,709.99 2006.173.14:57:16.19#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.14:57:16.19#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.14:57:16.19#ibcon#ireg 17 cls_cnt 0 2006.173.14:57:16.19#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.14:57:16.19#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.14:57:16.19#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.14:57:16.19#ibcon#enter wrdev, iclass 7, count 0 2006.173.14:57:16.19#ibcon#first serial, iclass 7, count 0 2006.173.14:57:16.19#ibcon#enter sib2, iclass 7, count 0 2006.173.14:57:16.19#ibcon#flushed, iclass 7, count 0 2006.173.14:57:16.19#ibcon#about to write, iclass 7, count 0 2006.173.14:57:16.19#ibcon#wrote, iclass 7, count 0 2006.173.14:57:16.19#ibcon#about to read 3, iclass 7, count 0 2006.173.14:57:16.21#ibcon#read 3, iclass 7, count 0 2006.173.14:57:16.21#ibcon#about to read 4, iclass 7, count 0 2006.173.14:57:16.21#ibcon#read 4, iclass 7, count 0 2006.173.14:57:16.21#ibcon#about to read 5, iclass 7, count 0 2006.173.14:57:16.21#ibcon#read 5, iclass 7, count 0 2006.173.14:57:16.21#ibcon#about to read 6, iclass 7, count 0 2006.173.14:57:16.21#ibcon#read 6, iclass 7, count 0 2006.173.14:57:16.21#ibcon#end of sib2, iclass 7, count 0 2006.173.14:57:16.21#ibcon#*mode == 0, iclass 7, count 0 2006.173.14:57:16.21#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.14:57:16.21#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.14:57:16.21#ibcon#*before write, iclass 7, count 0 2006.173.14:57:16.21#ibcon#enter sib2, iclass 7, count 0 2006.173.14:57:16.21#ibcon#flushed, iclass 7, count 0 2006.173.14:57:16.21#ibcon#about to write, iclass 7, count 0 2006.173.14:57:16.21#ibcon#wrote, iclass 7, count 0 2006.173.14:57:16.21#ibcon#about to read 3, iclass 7, count 0 2006.173.14:57:16.25#ibcon#read 3, iclass 7, count 0 2006.173.14:57:16.25#ibcon#about to read 4, iclass 7, count 0 2006.173.14:57:16.25#ibcon#read 4, iclass 7, count 0 2006.173.14:57:16.25#ibcon#about to read 5, iclass 7, count 0 2006.173.14:57:16.25#ibcon#read 5, iclass 7, count 0 2006.173.14:57:16.25#ibcon#about to read 6, iclass 7, count 0 2006.173.14:57:16.25#ibcon#read 6, iclass 7, count 0 2006.173.14:57:16.25#ibcon#end of sib2, iclass 7, count 0 2006.173.14:57:16.25#ibcon#*after write, iclass 7, count 0 2006.173.14:57:16.25#ibcon#*before return 0, iclass 7, count 0 2006.173.14:57:16.25#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.14:57:16.25#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.14:57:16.25#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.14:57:16.25#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.14:57:16.25$vck44/vb=5,4 2006.173.14:57:16.25#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.14:57:16.25#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.14:57:16.25#ibcon#ireg 11 cls_cnt 2 2006.173.14:57:16.25#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.14:57:16.31#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.14:57:16.31#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.14:57:16.31#ibcon#enter wrdev, iclass 11, count 2 2006.173.14:57:16.31#ibcon#first serial, iclass 11, count 2 2006.173.14:57:16.31#ibcon#enter sib2, iclass 11, count 2 2006.173.14:57:16.31#ibcon#flushed, iclass 11, count 2 2006.173.14:57:16.31#ibcon#about to write, iclass 11, count 2 2006.173.14:57:16.31#ibcon#wrote, iclass 11, count 2 2006.173.14:57:16.31#ibcon#about to read 3, iclass 11, count 2 2006.173.14:57:16.33#ibcon#read 3, iclass 11, count 2 2006.173.14:57:16.33#ibcon#about to read 4, iclass 11, count 2 2006.173.14:57:16.33#ibcon#read 4, iclass 11, count 2 2006.173.14:57:16.33#ibcon#about to read 5, iclass 11, count 2 2006.173.14:57:16.33#ibcon#read 5, iclass 11, count 2 2006.173.14:57:16.33#ibcon#about to read 6, iclass 11, count 2 2006.173.14:57:16.33#ibcon#read 6, iclass 11, count 2 2006.173.14:57:16.33#ibcon#end of sib2, iclass 11, count 2 2006.173.14:57:16.33#ibcon#*mode == 0, iclass 11, count 2 2006.173.14:57:16.33#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.14:57:16.33#ibcon#[27=AT05-04\r\n] 2006.173.14:57:16.33#ibcon#*before write, iclass 11, count 2 2006.173.14:57:16.33#ibcon#enter sib2, iclass 11, count 2 2006.173.14:57:16.33#ibcon#flushed, iclass 11, count 2 2006.173.14:57:16.33#ibcon#about to write, iclass 11, count 2 2006.173.14:57:16.33#ibcon#wrote, iclass 11, count 2 2006.173.14:57:16.33#ibcon#about to read 3, iclass 11, count 2 2006.173.14:57:16.36#ibcon#read 3, iclass 11, count 2 2006.173.14:57:16.36#ibcon#about to read 4, iclass 11, count 2 2006.173.14:57:16.36#ibcon#read 4, iclass 11, count 2 2006.173.14:57:16.36#ibcon#about to read 5, iclass 11, count 2 2006.173.14:57:16.36#ibcon#read 5, iclass 11, count 2 2006.173.14:57:16.36#ibcon#about to read 6, iclass 11, count 2 2006.173.14:57:16.36#ibcon#read 6, iclass 11, count 2 2006.173.14:57:16.36#ibcon#end of sib2, iclass 11, count 2 2006.173.14:57:16.36#ibcon#*after write, iclass 11, count 2 2006.173.14:57:16.36#ibcon#*before return 0, iclass 11, count 2 2006.173.14:57:16.36#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.14:57:16.36#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.14:57:16.36#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.14:57:16.36#ibcon#ireg 7 cls_cnt 0 2006.173.14:57:16.36#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.14:57:16.48#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.14:57:16.48#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.14:57:16.48#ibcon#enter wrdev, iclass 11, count 0 2006.173.14:57:16.48#ibcon#first serial, iclass 11, count 0 2006.173.14:57:16.48#ibcon#enter sib2, iclass 11, count 0 2006.173.14:57:16.48#ibcon#flushed, iclass 11, count 0 2006.173.14:57:16.48#ibcon#about to write, iclass 11, count 0 2006.173.14:57:16.48#ibcon#wrote, iclass 11, count 0 2006.173.14:57:16.48#ibcon#about to read 3, iclass 11, count 0 2006.173.14:57:16.50#ibcon#read 3, iclass 11, count 0 2006.173.14:57:16.50#ibcon#about to read 4, iclass 11, count 0 2006.173.14:57:16.50#ibcon#read 4, iclass 11, count 0 2006.173.14:57:16.50#ibcon#about to read 5, iclass 11, count 0 2006.173.14:57:16.50#ibcon#read 5, iclass 11, count 0 2006.173.14:57:16.50#ibcon#about to read 6, iclass 11, count 0 2006.173.14:57:16.50#ibcon#read 6, iclass 11, count 0 2006.173.14:57:16.50#ibcon#end of sib2, iclass 11, count 0 2006.173.14:57:16.50#ibcon#*mode == 0, iclass 11, count 0 2006.173.14:57:16.50#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.14:57:16.50#ibcon#[27=USB\r\n] 2006.173.14:57:16.50#ibcon#*before write, iclass 11, count 0 2006.173.14:57:16.50#ibcon#enter sib2, iclass 11, count 0 2006.173.14:57:16.50#ibcon#flushed, iclass 11, count 0 2006.173.14:57:16.50#ibcon#about to write, iclass 11, count 0 2006.173.14:57:16.50#ibcon#wrote, iclass 11, count 0 2006.173.14:57:16.50#ibcon#about to read 3, iclass 11, count 0 2006.173.14:57:16.53#ibcon#read 3, iclass 11, count 0 2006.173.14:57:16.53#ibcon#about to read 4, iclass 11, count 0 2006.173.14:57:16.53#ibcon#read 4, iclass 11, count 0 2006.173.14:57:16.53#ibcon#about to read 5, iclass 11, count 0 2006.173.14:57:16.53#ibcon#read 5, iclass 11, count 0 2006.173.14:57:16.53#ibcon#about to read 6, iclass 11, count 0 2006.173.14:57:16.53#ibcon#read 6, iclass 11, count 0 2006.173.14:57:16.53#ibcon#end of sib2, iclass 11, count 0 2006.173.14:57:16.53#ibcon#*after write, iclass 11, count 0 2006.173.14:57:16.53#ibcon#*before return 0, iclass 11, count 0 2006.173.14:57:16.53#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.14:57:16.53#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.14:57:16.53#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.14:57:16.53#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.14:57:16.53$vck44/vblo=6,719.99 2006.173.14:57:16.53#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.14:57:16.53#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.14:57:16.53#ibcon#ireg 17 cls_cnt 0 2006.173.14:57:16.53#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.14:57:16.53#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.14:57:16.53#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.14:57:16.53#ibcon#enter wrdev, iclass 13, count 0 2006.173.14:57:16.53#ibcon#first serial, iclass 13, count 0 2006.173.14:57:16.53#ibcon#enter sib2, iclass 13, count 0 2006.173.14:57:16.53#ibcon#flushed, iclass 13, count 0 2006.173.14:57:16.53#ibcon#about to write, iclass 13, count 0 2006.173.14:57:16.53#ibcon#wrote, iclass 13, count 0 2006.173.14:57:16.53#ibcon#about to read 3, iclass 13, count 0 2006.173.14:57:16.55#ibcon#read 3, iclass 13, count 0 2006.173.14:57:16.55#ibcon#about to read 4, iclass 13, count 0 2006.173.14:57:16.55#ibcon#read 4, iclass 13, count 0 2006.173.14:57:16.55#ibcon#about to read 5, iclass 13, count 0 2006.173.14:57:16.55#ibcon#read 5, iclass 13, count 0 2006.173.14:57:16.55#ibcon#about to read 6, iclass 13, count 0 2006.173.14:57:16.55#ibcon#read 6, iclass 13, count 0 2006.173.14:57:16.55#ibcon#end of sib2, iclass 13, count 0 2006.173.14:57:16.55#ibcon#*mode == 0, iclass 13, count 0 2006.173.14:57:16.55#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.14:57:16.55#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.14:57:16.55#ibcon#*before write, iclass 13, count 0 2006.173.14:57:16.55#ibcon#enter sib2, iclass 13, count 0 2006.173.14:57:16.55#ibcon#flushed, iclass 13, count 0 2006.173.14:57:16.55#ibcon#about to write, iclass 13, count 0 2006.173.14:57:16.55#ibcon#wrote, iclass 13, count 0 2006.173.14:57:16.55#ibcon#about to read 3, iclass 13, count 0 2006.173.14:57:16.59#ibcon#read 3, iclass 13, count 0 2006.173.14:57:16.59#ibcon#about to read 4, iclass 13, count 0 2006.173.14:57:16.59#ibcon#read 4, iclass 13, count 0 2006.173.14:57:16.59#ibcon#about to read 5, iclass 13, count 0 2006.173.14:57:16.59#ibcon#read 5, iclass 13, count 0 2006.173.14:57:16.59#ibcon#about to read 6, iclass 13, count 0 2006.173.14:57:16.59#ibcon#read 6, iclass 13, count 0 2006.173.14:57:16.59#ibcon#end of sib2, iclass 13, count 0 2006.173.14:57:16.59#ibcon#*after write, iclass 13, count 0 2006.173.14:57:16.59#ibcon#*before return 0, iclass 13, count 0 2006.173.14:57:16.59#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.14:57:16.59#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.14:57:16.59#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.14:57:16.59#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.14:57:16.59$vck44/vb=6,4 2006.173.14:57:16.59#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.14:57:16.59#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.14:57:16.59#ibcon#ireg 11 cls_cnt 2 2006.173.14:57:16.59#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.14:57:16.65#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.14:57:16.65#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.14:57:16.65#ibcon#enter wrdev, iclass 15, count 2 2006.173.14:57:16.65#ibcon#first serial, iclass 15, count 2 2006.173.14:57:16.65#ibcon#enter sib2, iclass 15, count 2 2006.173.14:57:16.65#ibcon#flushed, iclass 15, count 2 2006.173.14:57:16.65#ibcon#about to write, iclass 15, count 2 2006.173.14:57:16.65#ibcon#wrote, iclass 15, count 2 2006.173.14:57:16.65#ibcon#about to read 3, iclass 15, count 2 2006.173.14:57:16.67#ibcon#read 3, iclass 15, count 2 2006.173.14:57:16.67#ibcon#about to read 4, iclass 15, count 2 2006.173.14:57:16.67#ibcon#read 4, iclass 15, count 2 2006.173.14:57:16.67#ibcon#about to read 5, iclass 15, count 2 2006.173.14:57:16.67#ibcon#read 5, iclass 15, count 2 2006.173.14:57:16.67#ibcon#about to read 6, iclass 15, count 2 2006.173.14:57:16.67#ibcon#read 6, iclass 15, count 2 2006.173.14:57:16.67#ibcon#end of sib2, iclass 15, count 2 2006.173.14:57:16.67#ibcon#*mode == 0, iclass 15, count 2 2006.173.14:57:16.67#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.14:57:16.67#ibcon#[27=AT06-04\r\n] 2006.173.14:57:16.67#ibcon#*before write, iclass 15, count 2 2006.173.14:57:16.67#ibcon#enter sib2, iclass 15, count 2 2006.173.14:57:16.67#ibcon#flushed, iclass 15, count 2 2006.173.14:57:16.67#ibcon#about to write, iclass 15, count 2 2006.173.14:57:16.67#ibcon#wrote, iclass 15, count 2 2006.173.14:57:16.67#ibcon#about to read 3, iclass 15, count 2 2006.173.14:57:16.70#ibcon#read 3, iclass 15, count 2 2006.173.14:57:16.70#ibcon#about to read 4, iclass 15, count 2 2006.173.14:57:16.70#ibcon#read 4, iclass 15, count 2 2006.173.14:57:16.70#ibcon#about to read 5, iclass 15, count 2 2006.173.14:57:16.70#ibcon#read 5, iclass 15, count 2 2006.173.14:57:16.70#ibcon#about to read 6, iclass 15, count 2 2006.173.14:57:16.70#ibcon#read 6, iclass 15, count 2 2006.173.14:57:16.70#ibcon#end of sib2, iclass 15, count 2 2006.173.14:57:16.70#ibcon#*after write, iclass 15, count 2 2006.173.14:57:16.70#ibcon#*before return 0, iclass 15, count 2 2006.173.14:57:16.70#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.14:57:16.70#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.14:57:16.70#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.14:57:16.70#ibcon#ireg 7 cls_cnt 0 2006.173.14:57:16.70#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.14:57:16.82#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.14:57:16.82#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.14:57:16.82#ibcon#enter wrdev, iclass 15, count 0 2006.173.14:57:16.82#ibcon#first serial, iclass 15, count 0 2006.173.14:57:16.82#ibcon#enter sib2, iclass 15, count 0 2006.173.14:57:16.82#ibcon#flushed, iclass 15, count 0 2006.173.14:57:16.82#ibcon#about to write, iclass 15, count 0 2006.173.14:57:16.82#ibcon#wrote, iclass 15, count 0 2006.173.14:57:16.82#ibcon#about to read 3, iclass 15, count 0 2006.173.14:57:16.84#ibcon#read 3, iclass 15, count 0 2006.173.14:57:16.84#ibcon#about to read 4, iclass 15, count 0 2006.173.14:57:16.84#ibcon#read 4, iclass 15, count 0 2006.173.14:57:16.84#ibcon#about to read 5, iclass 15, count 0 2006.173.14:57:16.84#ibcon#read 5, iclass 15, count 0 2006.173.14:57:16.84#ibcon#about to read 6, iclass 15, count 0 2006.173.14:57:16.84#ibcon#read 6, iclass 15, count 0 2006.173.14:57:16.84#ibcon#end of sib2, iclass 15, count 0 2006.173.14:57:16.84#ibcon#*mode == 0, iclass 15, count 0 2006.173.14:57:16.84#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.14:57:16.84#ibcon#[27=USB\r\n] 2006.173.14:57:16.84#ibcon#*before write, iclass 15, count 0 2006.173.14:57:16.84#ibcon#enter sib2, iclass 15, count 0 2006.173.14:57:16.84#ibcon#flushed, iclass 15, count 0 2006.173.14:57:16.84#ibcon#about to write, iclass 15, count 0 2006.173.14:57:16.84#ibcon#wrote, iclass 15, count 0 2006.173.14:57:16.84#ibcon#about to read 3, iclass 15, count 0 2006.173.14:57:16.87#ibcon#read 3, iclass 15, count 0 2006.173.14:57:16.87#ibcon#about to read 4, iclass 15, count 0 2006.173.14:57:16.87#ibcon#read 4, iclass 15, count 0 2006.173.14:57:16.87#ibcon#about to read 5, iclass 15, count 0 2006.173.14:57:16.87#ibcon#read 5, iclass 15, count 0 2006.173.14:57:16.87#ibcon#about to read 6, iclass 15, count 0 2006.173.14:57:16.87#ibcon#read 6, iclass 15, count 0 2006.173.14:57:16.87#ibcon#end of sib2, iclass 15, count 0 2006.173.14:57:16.87#ibcon#*after write, iclass 15, count 0 2006.173.14:57:16.87#ibcon#*before return 0, iclass 15, count 0 2006.173.14:57:16.87#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.14:57:16.87#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.14:57:16.87#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.14:57:16.87#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.14:57:16.87$vck44/vblo=7,734.99 2006.173.14:57:16.87#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.14:57:16.87#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.14:57:16.87#ibcon#ireg 17 cls_cnt 0 2006.173.14:57:16.87#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.14:57:16.87#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.14:57:16.87#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.14:57:16.87#ibcon#enter wrdev, iclass 17, count 0 2006.173.14:57:16.87#ibcon#first serial, iclass 17, count 0 2006.173.14:57:16.87#ibcon#enter sib2, iclass 17, count 0 2006.173.14:57:16.87#ibcon#flushed, iclass 17, count 0 2006.173.14:57:16.87#ibcon#about to write, iclass 17, count 0 2006.173.14:57:16.87#ibcon#wrote, iclass 17, count 0 2006.173.14:57:16.87#ibcon#about to read 3, iclass 17, count 0 2006.173.14:57:16.89#ibcon#read 3, iclass 17, count 0 2006.173.14:57:16.89#ibcon#about to read 4, iclass 17, count 0 2006.173.14:57:16.89#ibcon#read 4, iclass 17, count 0 2006.173.14:57:16.89#ibcon#about to read 5, iclass 17, count 0 2006.173.14:57:16.89#ibcon#read 5, iclass 17, count 0 2006.173.14:57:16.89#ibcon#about to read 6, iclass 17, count 0 2006.173.14:57:16.89#ibcon#read 6, iclass 17, count 0 2006.173.14:57:16.89#ibcon#end of sib2, iclass 17, count 0 2006.173.14:57:16.89#ibcon#*mode == 0, iclass 17, count 0 2006.173.14:57:16.89#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.14:57:16.89#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.14:57:16.89#ibcon#*before write, iclass 17, count 0 2006.173.14:57:16.89#ibcon#enter sib2, iclass 17, count 0 2006.173.14:57:16.89#ibcon#flushed, iclass 17, count 0 2006.173.14:57:16.89#ibcon#about to write, iclass 17, count 0 2006.173.14:57:16.89#ibcon#wrote, iclass 17, count 0 2006.173.14:57:16.89#ibcon#about to read 3, iclass 17, count 0 2006.173.14:57:16.93#ibcon#read 3, iclass 17, count 0 2006.173.14:57:16.93#ibcon#about to read 4, iclass 17, count 0 2006.173.14:57:16.93#ibcon#read 4, iclass 17, count 0 2006.173.14:57:16.93#ibcon#about to read 5, iclass 17, count 0 2006.173.14:57:16.93#ibcon#read 5, iclass 17, count 0 2006.173.14:57:16.93#ibcon#about to read 6, iclass 17, count 0 2006.173.14:57:16.93#ibcon#read 6, iclass 17, count 0 2006.173.14:57:16.93#ibcon#end of sib2, iclass 17, count 0 2006.173.14:57:16.93#ibcon#*after write, iclass 17, count 0 2006.173.14:57:16.93#ibcon#*before return 0, iclass 17, count 0 2006.173.14:57:16.93#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.14:57:16.93#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.14:57:16.93#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.14:57:16.93#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.14:57:16.93$vck44/vb=7,4 2006.173.14:57:16.93#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.14:57:16.93#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.14:57:16.93#ibcon#ireg 11 cls_cnt 2 2006.173.14:57:16.93#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.14:57:16.99#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.14:57:16.99#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.14:57:16.99#ibcon#enter wrdev, iclass 19, count 2 2006.173.14:57:16.99#ibcon#first serial, iclass 19, count 2 2006.173.14:57:16.99#ibcon#enter sib2, iclass 19, count 2 2006.173.14:57:16.99#ibcon#flushed, iclass 19, count 2 2006.173.14:57:16.99#ibcon#about to write, iclass 19, count 2 2006.173.14:57:16.99#ibcon#wrote, iclass 19, count 2 2006.173.14:57:16.99#ibcon#about to read 3, iclass 19, count 2 2006.173.14:57:17.01#ibcon#read 3, iclass 19, count 2 2006.173.14:57:17.01#ibcon#about to read 4, iclass 19, count 2 2006.173.14:57:17.01#ibcon#read 4, iclass 19, count 2 2006.173.14:57:17.01#ibcon#about to read 5, iclass 19, count 2 2006.173.14:57:17.01#ibcon#read 5, iclass 19, count 2 2006.173.14:57:17.01#ibcon#about to read 6, iclass 19, count 2 2006.173.14:57:17.01#ibcon#read 6, iclass 19, count 2 2006.173.14:57:17.01#ibcon#end of sib2, iclass 19, count 2 2006.173.14:57:17.01#ibcon#*mode == 0, iclass 19, count 2 2006.173.14:57:17.01#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.14:57:17.01#ibcon#[27=AT07-04\r\n] 2006.173.14:57:17.01#ibcon#*before write, iclass 19, count 2 2006.173.14:57:17.01#ibcon#enter sib2, iclass 19, count 2 2006.173.14:57:17.01#ibcon#flushed, iclass 19, count 2 2006.173.14:57:17.01#ibcon#about to write, iclass 19, count 2 2006.173.14:57:17.01#ibcon#wrote, iclass 19, count 2 2006.173.14:57:17.01#ibcon#about to read 3, iclass 19, count 2 2006.173.14:57:17.04#ibcon#read 3, iclass 19, count 2 2006.173.14:57:17.04#ibcon#about to read 4, iclass 19, count 2 2006.173.14:57:17.04#ibcon#read 4, iclass 19, count 2 2006.173.14:57:17.04#ibcon#about to read 5, iclass 19, count 2 2006.173.14:57:17.04#ibcon#read 5, iclass 19, count 2 2006.173.14:57:17.04#ibcon#about to read 6, iclass 19, count 2 2006.173.14:57:17.04#ibcon#read 6, iclass 19, count 2 2006.173.14:57:17.04#ibcon#end of sib2, iclass 19, count 2 2006.173.14:57:17.04#ibcon#*after write, iclass 19, count 2 2006.173.14:57:17.04#ibcon#*before return 0, iclass 19, count 2 2006.173.14:57:17.04#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.14:57:17.04#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.14:57:17.04#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.14:57:17.04#ibcon#ireg 7 cls_cnt 0 2006.173.14:57:17.04#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.14:57:17.16#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.14:57:17.16#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.14:57:17.16#ibcon#enter wrdev, iclass 19, count 0 2006.173.14:57:17.16#ibcon#first serial, iclass 19, count 0 2006.173.14:57:17.16#ibcon#enter sib2, iclass 19, count 0 2006.173.14:57:17.16#ibcon#flushed, iclass 19, count 0 2006.173.14:57:17.16#ibcon#about to write, iclass 19, count 0 2006.173.14:57:17.16#ibcon#wrote, iclass 19, count 0 2006.173.14:57:17.16#ibcon#about to read 3, iclass 19, count 0 2006.173.14:57:17.18#ibcon#read 3, iclass 19, count 0 2006.173.14:57:17.18#ibcon#about to read 4, iclass 19, count 0 2006.173.14:57:17.18#ibcon#read 4, iclass 19, count 0 2006.173.14:57:17.18#ibcon#about to read 5, iclass 19, count 0 2006.173.14:57:17.18#ibcon#read 5, iclass 19, count 0 2006.173.14:57:17.18#ibcon#about to read 6, iclass 19, count 0 2006.173.14:57:17.18#ibcon#read 6, iclass 19, count 0 2006.173.14:57:17.18#ibcon#end of sib2, iclass 19, count 0 2006.173.14:57:17.18#ibcon#*mode == 0, iclass 19, count 0 2006.173.14:57:17.18#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.14:57:17.18#ibcon#[27=USB\r\n] 2006.173.14:57:17.18#ibcon#*before write, iclass 19, count 0 2006.173.14:57:17.18#ibcon#enter sib2, iclass 19, count 0 2006.173.14:57:17.18#ibcon#flushed, iclass 19, count 0 2006.173.14:57:17.18#ibcon#about to write, iclass 19, count 0 2006.173.14:57:17.18#ibcon#wrote, iclass 19, count 0 2006.173.14:57:17.18#ibcon#about to read 3, iclass 19, count 0 2006.173.14:57:17.21#ibcon#read 3, iclass 19, count 0 2006.173.14:57:17.21#ibcon#about to read 4, iclass 19, count 0 2006.173.14:57:17.21#ibcon#read 4, iclass 19, count 0 2006.173.14:57:17.21#ibcon#about to read 5, iclass 19, count 0 2006.173.14:57:17.21#ibcon#read 5, iclass 19, count 0 2006.173.14:57:17.21#ibcon#about to read 6, iclass 19, count 0 2006.173.14:57:17.21#ibcon#read 6, iclass 19, count 0 2006.173.14:57:17.21#ibcon#end of sib2, iclass 19, count 0 2006.173.14:57:17.21#ibcon#*after write, iclass 19, count 0 2006.173.14:57:17.21#ibcon#*before return 0, iclass 19, count 0 2006.173.14:57:17.21#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.14:57:17.21#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.14:57:17.21#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.14:57:17.21#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.14:57:17.21$vck44/vblo=8,744.99 2006.173.14:57:17.21#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.14:57:17.21#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.14:57:17.21#ibcon#ireg 17 cls_cnt 0 2006.173.14:57:17.21#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.14:57:17.21#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.14:57:17.21#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.14:57:17.21#ibcon#enter wrdev, iclass 21, count 0 2006.173.14:57:17.21#ibcon#first serial, iclass 21, count 0 2006.173.14:57:17.21#ibcon#enter sib2, iclass 21, count 0 2006.173.14:57:17.21#ibcon#flushed, iclass 21, count 0 2006.173.14:57:17.21#ibcon#about to write, iclass 21, count 0 2006.173.14:57:17.21#ibcon#wrote, iclass 21, count 0 2006.173.14:57:17.21#ibcon#about to read 3, iclass 21, count 0 2006.173.14:57:17.23#ibcon#read 3, iclass 21, count 0 2006.173.14:57:17.23#ibcon#about to read 4, iclass 21, count 0 2006.173.14:57:17.23#ibcon#read 4, iclass 21, count 0 2006.173.14:57:17.23#ibcon#about to read 5, iclass 21, count 0 2006.173.14:57:17.23#ibcon#read 5, iclass 21, count 0 2006.173.14:57:17.23#ibcon#about to read 6, iclass 21, count 0 2006.173.14:57:17.23#ibcon#read 6, iclass 21, count 0 2006.173.14:57:17.23#ibcon#end of sib2, iclass 21, count 0 2006.173.14:57:17.23#ibcon#*mode == 0, iclass 21, count 0 2006.173.14:57:17.23#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.14:57:17.23#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.14:57:17.23#ibcon#*before write, iclass 21, count 0 2006.173.14:57:17.23#ibcon#enter sib2, iclass 21, count 0 2006.173.14:57:17.23#ibcon#flushed, iclass 21, count 0 2006.173.14:57:17.23#ibcon#about to write, iclass 21, count 0 2006.173.14:57:17.23#ibcon#wrote, iclass 21, count 0 2006.173.14:57:17.23#ibcon#about to read 3, iclass 21, count 0 2006.173.14:57:17.27#ibcon#read 3, iclass 21, count 0 2006.173.14:57:17.27#ibcon#about to read 4, iclass 21, count 0 2006.173.14:57:17.27#ibcon#read 4, iclass 21, count 0 2006.173.14:57:17.27#ibcon#about to read 5, iclass 21, count 0 2006.173.14:57:17.27#ibcon#read 5, iclass 21, count 0 2006.173.14:57:17.27#ibcon#about to read 6, iclass 21, count 0 2006.173.14:57:17.27#ibcon#read 6, iclass 21, count 0 2006.173.14:57:17.27#ibcon#end of sib2, iclass 21, count 0 2006.173.14:57:17.27#ibcon#*after write, iclass 21, count 0 2006.173.14:57:17.27#ibcon#*before return 0, iclass 21, count 0 2006.173.14:57:17.27#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.14:57:17.27#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.14:57:17.27#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.14:57:17.27#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.14:57:17.27$vck44/vb=8,4 2006.173.14:57:17.27#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.14:57:17.27#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.14:57:17.27#ibcon#ireg 11 cls_cnt 2 2006.173.14:57:17.27#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.14:57:17.33#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.14:57:17.33#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.14:57:17.33#ibcon#enter wrdev, iclass 23, count 2 2006.173.14:57:17.33#ibcon#first serial, iclass 23, count 2 2006.173.14:57:17.33#ibcon#enter sib2, iclass 23, count 2 2006.173.14:57:17.33#ibcon#flushed, iclass 23, count 2 2006.173.14:57:17.33#ibcon#about to write, iclass 23, count 2 2006.173.14:57:17.33#ibcon#wrote, iclass 23, count 2 2006.173.14:57:17.33#ibcon#about to read 3, iclass 23, count 2 2006.173.14:57:17.35#ibcon#read 3, iclass 23, count 2 2006.173.14:57:17.35#ibcon#about to read 4, iclass 23, count 2 2006.173.14:57:17.35#ibcon#read 4, iclass 23, count 2 2006.173.14:57:17.35#ibcon#about to read 5, iclass 23, count 2 2006.173.14:57:17.35#ibcon#read 5, iclass 23, count 2 2006.173.14:57:17.35#ibcon#about to read 6, iclass 23, count 2 2006.173.14:57:17.35#ibcon#read 6, iclass 23, count 2 2006.173.14:57:17.35#ibcon#end of sib2, iclass 23, count 2 2006.173.14:57:17.35#ibcon#*mode == 0, iclass 23, count 2 2006.173.14:57:17.35#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.14:57:17.35#ibcon#[27=AT08-04\r\n] 2006.173.14:57:17.35#ibcon#*before write, iclass 23, count 2 2006.173.14:57:17.35#ibcon#enter sib2, iclass 23, count 2 2006.173.14:57:17.35#ibcon#flushed, iclass 23, count 2 2006.173.14:57:17.35#ibcon#about to write, iclass 23, count 2 2006.173.14:57:17.35#ibcon#wrote, iclass 23, count 2 2006.173.14:57:17.35#ibcon#about to read 3, iclass 23, count 2 2006.173.14:57:17.38#ibcon#read 3, iclass 23, count 2 2006.173.14:57:17.38#ibcon#about to read 4, iclass 23, count 2 2006.173.14:57:17.38#ibcon#read 4, iclass 23, count 2 2006.173.14:57:17.38#ibcon#about to read 5, iclass 23, count 2 2006.173.14:57:17.38#ibcon#read 5, iclass 23, count 2 2006.173.14:57:17.38#ibcon#about to read 6, iclass 23, count 2 2006.173.14:57:17.38#ibcon#read 6, iclass 23, count 2 2006.173.14:57:17.38#ibcon#end of sib2, iclass 23, count 2 2006.173.14:57:17.38#ibcon#*after write, iclass 23, count 2 2006.173.14:57:17.38#ibcon#*before return 0, iclass 23, count 2 2006.173.14:57:17.38#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.14:57:17.38#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.14:57:17.38#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.14:57:17.38#ibcon#ireg 7 cls_cnt 0 2006.173.14:57:17.38#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.14:57:17.50#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.14:57:17.50#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.14:57:17.50#ibcon#enter wrdev, iclass 23, count 0 2006.173.14:57:17.50#ibcon#first serial, iclass 23, count 0 2006.173.14:57:17.50#ibcon#enter sib2, iclass 23, count 0 2006.173.14:57:17.50#ibcon#flushed, iclass 23, count 0 2006.173.14:57:17.50#ibcon#about to write, iclass 23, count 0 2006.173.14:57:17.50#ibcon#wrote, iclass 23, count 0 2006.173.14:57:17.50#ibcon#about to read 3, iclass 23, count 0 2006.173.14:57:17.52#ibcon#read 3, iclass 23, count 0 2006.173.14:57:17.52#ibcon#about to read 4, iclass 23, count 0 2006.173.14:57:17.52#ibcon#read 4, iclass 23, count 0 2006.173.14:57:17.52#ibcon#about to read 5, iclass 23, count 0 2006.173.14:57:17.52#ibcon#read 5, iclass 23, count 0 2006.173.14:57:17.52#ibcon#about to read 6, iclass 23, count 0 2006.173.14:57:17.52#ibcon#read 6, iclass 23, count 0 2006.173.14:57:17.52#ibcon#end of sib2, iclass 23, count 0 2006.173.14:57:17.52#ibcon#*mode == 0, iclass 23, count 0 2006.173.14:57:17.52#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.14:57:17.52#ibcon#[27=USB\r\n] 2006.173.14:57:17.52#ibcon#*before write, iclass 23, count 0 2006.173.14:57:17.52#ibcon#enter sib2, iclass 23, count 0 2006.173.14:57:17.52#ibcon#flushed, iclass 23, count 0 2006.173.14:57:17.52#ibcon#about to write, iclass 23, count 0 2006.173.14:57:17.52#ibcon#wrote, iclass 23, count 0 2006.173.14:57:17.52#ibcon#about to read 3, iclass 23, count 0 2006.173.14:57:17.55#ibcon#read 3, iclass 23, count 0 2006.173.14:57:17.55#ibcon#about to read 4, iclass 23, count 0 2006.173.14:57:17.55#ibcon#read 4, iclass 23, count 0 2006.173.14:57:17.55#ibcon#about to read 5, iclass 23, count 0 2006.173.14:57:17.55#ibcon#read 5, iclass 23, count 0 2006.173.14:57:17.55#ibcon#about to read 6, iclass 23, count 0 2006.173.14:57:17.55#ibcon#read 6, iclass 23, count 0 2006.173.14:57:17.55#ibcon#end of sib2, iclass 23, count 0 2006.173.14:57:17.55#ibcon#*after write, iclass 23, count 0 2006.173.14:57:17.55#ibcon#*before return 0, iclass 23, count 0 2006.173.14:57:17.55#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.14:57:17.55#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.14:57:17.55#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.14:57:17.55#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.14:57:17.55$vck44/vabw=wide 2006.173.14:57:17.55#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.14:57:17.55#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.14:57:17.55#ibcon#ireg 8 cls_cnt 0 2006.173.14:57:17.55#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.14:57:17.55#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.14:57:17.55#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.14:57:17.55#ibcon#enter wrdev, iclass 25, count 0 2006.173.14:57:17.55#ibcon#first serial, iclass 25, count 0 2006.173.14:57:17.55#ibcon#enter sib2, iclass 25, count 0 2006.173.14:57:17.55#ibcon#flushed, iclass 25, count 0 2006.173.14:57:17.55#ibcon#about to write, iclass 25, count 0 2006.173.14:57:17.55#ibcon#wrote, iclass 25, count 0 2006.173.14:57:17.55#ibcon#about to read 3, iclass 25, count 0 2006.173.14:57:17.57#ibcon#read 3, iclass 25, count 0 2006.173.14:57:17.57#ibcon#about to read 4, iclass 25, count 0 2006.173.14:57:17.57#ibcon#read 4, iclass 25, count 0 2006.173.14:57:17.57#ibcon#about to read 5, iclass 25, count 0 2006.173.14:57:17.57#ibcon#read 5, iclass 25, count 0 2006.173.14:57:17.57#ibcon#about to read 6, iclass 25, count 0 2006.173.14:57:17.57#ibcon#read 6, iclass 25, count 0 2006.173.14:57:17.57#ibcon#end of sib2, iclass 25, count 0 2006.173.14:57:17.57#ibcon#*mode == 0, iclass 25, count 0 2006.173.14:57:17.57#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.14:57:17.57#ibcon#[25=BW32\r\n] 2006.173.14:57:17.57#ibcon#*before write, iclass 25, count 0 2006.173.14:57:17.57#ibcon#enter sib2, iclass 25, count 0 2006.173.14:57:17.57#ibcon#flushed, iclass 25, count 0 2006.173.14:57:17.57#ibcon#about to write, iclass 25, count 0 2006.173.14:57:17.57#ibcon#wrote, iclass 25, count 0 2006.173.14:57:17.57#ibcon#about to read 3, iclass 25, count 0 2006.173.14:57:17.60#ibcon#read 3, iclass 25, count 0 2006.173.14:57:17.60#ibcon#about to read 4, iclass 25, count 0 2006.173.14:57:17.60#ibcon#read 4, iclass 25, count 0 2006.173.14:57:17.60#ibcon#about to read 5, iclass 25, count 0 2006.173.14:57:17.60#ibcon#read 5, iclass 25, count 0 2006.173.14:57:17.60#ibcon#about to read 6, iclass 25, count 0 2006.173.14:57:17.60#ibcon#read 6, iclass 25, count 0 2006.173.14:57:17.60#ibcon#end of sib2, iclass 25, count 0 2006.173.14:57:17.60#ibcon#*after write, iclass 25, count 0 2006.173.14:57:17.60#ibcon#*before return 0, iclass 25, count 0 2006.173.14:57:17.60#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.14:57:17.60#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.14:57:17.60#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.14:57:17.60#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.14:57:17.60$vck44/vbbw=wide 2006.173.14:57:17.60#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.14:57:17.60#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.14:57:17.60#ibcon#ireg 8 cls_cnt 0 2006.173.14:57:17.60#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.14:57:17.67#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.14:57:17.67#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.14:57:17.67#ibcon#enter wrdev, iclass 27, count 0 2006.173.14:57:17.67#ibcon#first serial, iclass 27, count 0 2006.173.14:57:17.67#ibcon#enter sib2, iclass 27, count 0 2006.173.14:57:17.67#ibcon#flushed, iclass 27, count 0 2006.173.14:57:17.67#ibcon#about to write, iclass 27, count 0 2006.173.14:57:17.67#ibcon#wrote, iclass 27, count 0 2006.173.14:57:17.67#ibcon#about to read 3, iclass 27, count 0 2006.173.14:57:17.69#ibcon#read 3, iclass 27, count 0 2006.173.14:57:17.69#ibcon#about to read 4, iclass 27, count 0 2006.173.14:57:17.69#ibcon#read 4, iclass 27, count 0 2006.173.14:57:17.69#ibcon#about to read 5, iclass 27, count 0 2006.173.14:57:17.69#ibcon#read 5, iclass 27, count 0 2006.173.14:57:17.69#ibcon#about to read 6, iclass 27, count 0 2006.173.14:57:17.69#ibcon#read 6, iclass 27, count 0 2006.173.14:57:17.69#ibcon#end of sib2, iclass 27, count 0 2006.173.14:57:17.69#ibcon#*mode == 0, iclass 27, count 0 2006.173.14:57:17.69#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.14:57:17.69#ibcon#[27=BW32\r\n] 2006.173.14:57:17.69#ibcon#*before write, iclass 27, count 0 2006.173.14:57:17.69#ibcon#enter sib2, iclass 27, count 0 2006.173.14:57:17.69#ibcon#flushed, iclass 27, count 0 2006.173.14:57:17.69#ibcon#about to write, iclass 27, count 0 2006.173.14:57:17.69#ibcon#wrote, iclass 27, count 0 2006.173.14:57:17.69#ibcon#about to read 3, iclass 27, count 0 2006.173.14:57:17.72#ibcon#read 3, iclass 27, count 0 2006.173.14:57:17.72#ibcon#about to read 4, iclass 27, count 0 2006.173.14:57:17.72#ibcon#read 4, iclass 27, count 0 2006.173.14:57:17.72#ibcon#about to read 5, iclass 27, count 0 2006.173.14:57:17.72#ibcon#read 5, iclass 27, count 0 2006.173.14:57:17.72#ibcon#about to read 6, iclass 27, count 0 2006.173.14:57:17.72#ibcon#read 6, iclass 27, count 0 2006.173.14:57:17.72#ibcon#end of sib2, iclass 27, count 0 2006.173.14:57:17.72#ibcon#*after write, iclass 27, count 0 2006.173.14:57:17.72#ibcon#*before return 0, iclass 27, count 0 2006.173.14:57:17.72#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.14:57:17.72#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.14:57:17.72#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.14:57:17.72#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.14:57:17.72$setupk4/ifdk4 2006.173.14:57:17.72$ifdk4/lo= 2006.173.14:57:17.72$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.14:57:17.72$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.14:57:17.72$ifdk4/patch= 2006.173.14:57:17.72$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.14:57:17.72$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.14:57:17.72$setupk4/!*+20s 2006.173.14:57:20.69#abcon#<5=/05 1.1 1.8 20.901001003.5\r\n> 2006.173.14:57:20.71#abcon#{5=INTERFACE CLEAR} 2006.173.14:57:20.77#abcon#[5=S1D000X0/0*\r\n] 2006.173.14:57:30.86#abcon#<5=/05 1.1 1.7 20.901001003.5\r\n> 2006.173.14:57:30.88#abcon#{5=INTERFACE CLEAR} 2006.173.14:57:30.94#abcon#[5=S1D000X0/0*\r\n] 2006.173.14:57:32.23$setupk4/"tpicd 2006.173.14:57:32.23$setupk4/echo=off 2006.173.14:57:32.23$setupk4/xlog=off 2006.173.14:57:32.23:!2006.173.15:00:48 2006.173.14:57:44.14#trakl#Source acquired 2006.173.14:57:46.14#flagr#flagr/antenna,acquired 2006.173.15:00:48.00:preob 2006.173.15:00:48.13/onsource/TRACKING 2006.173.15:00:48.13:!2006.173.15:00:58 2006.173.15:00:58.00:"tape 2006.173.15:00:58.00:"st=record 2006.173.15:00:58.00:data_valid=on 2006.173.15:00:58.00:midob 2006.173.15:00:58.13/onsource/TRACKING 2006.173.15:00:58.13/wx/20.92,1003.4,100 2006.173.15:00:58.29/cable/+6.5078E-03 2006.173.15:00:59.38/va/01,07,usb,yes,38,41 2006.173.15:00:59.38/va/02,06,usb,yes,38,39 2006.173.15:00:59.38/va/03,05,usb,yes,48,50 2006.173.15:00:59.38/va/04,06,usb,yes,39,41 2006.173.15:00:59.38/va/05,04,usb,yes,31,31 2006.173.15:00:59.38/va/06,03,usb,yes,43,43 2006.173.15:00:59.38/va/07,04,usb,yes,35,36 2006.173.15:00:59.38/va/08,04,usb,yes,30,36 2006.173.15:00:59.61/valo/01,524.99,yes,locked 2006.173.15:00:59.61/valo/02,534.99,yes,locked 2006.173.15:00:59.61/valo/03,564.99,yes,locked 2006.173.15:00:59.61/valo/04,624.99,yes,locked 2006.173.15:00:59.61/valo/05,734.99,yes,locked 2006.173.15:00:59.61/valo/06,814.99,yes,locked 2006.173.15:00:59.61/valo/07,864.99,yes,locked 2006.173.15:00:59.61/valo/08,884.99,yes,locked 2006.173.15:01:00.70/vb/01,04,usb,yes,29,27 2006.173.15:01:00.70/vb/02,04,usb,yes,32,31 2006.173.15:01:00.70/vb/03,04,usb,yes,28,31 2006.173.15:01:00.70/vb/04,04,usb,yes,33,32 2006.173.15:01:00.70/vb/05,04,usb,yes,26,28 2006.173.15:01:00.70/vb/06,04,usb,yes,30,26 2006.173.15:01:00.70/vb/07,04,usb,yes,30,29 2006.173.15:01:00.70/vb/08,04,usb,yes,27,30 2006.173.15:01:00.94/vblo/01,629.99,yes,locked 2006.173.15:01:00.94/vblo/02,634.99,yes,locked 2006.173.15:01:00.94/vblo/03,649.99,yes,locked 2006.173.15:01:00.94/vblo/04,679.99,yes,locked 2006.173.15:01:00.94/vblo/05,709.99,yes,locked 2006.173.15:01:00.94/vblo/06,719.99,yes,locked 2006.173.15:01:00.94/vblo/07,734.99,yes,locked 2006.173.15:01:00.94/vblo/08,744.99,yes,locked 2006.173.15:01:01.09/vabw/8 2006.173.15:01:01.24/vbbw/8 2006.173.15:01:01.33/xfe/off,on,14.5 2006.173.15:01:01.71/ifatt/23,28,28,28 2006.173.15:01:02.07/fmout-gps/S +3.95E-07 2006.173.15:01:02.11:!2006.173.15:01:38 2006.173.15:01:38.01:data_valid=off 2006.173.15:01:38.01:"et 2006.173.15:01:38.01:!+3s 2006.173.15:01:41.02:"tape 2006.173.15:01:41.02:postob 2006.173.15:01:41.24/cable/+6.5089E-03 2006.173.15:01:41.24/wx/20.92,1003.3,100 2006.173.15:01:41.30/fmout-gps/S +3.95E-07 2006.173.15:01:41.30:scan_name=173-1502,jd0606,40 2006.173.15:01:41.30:source=1334-127,133739.78,-125724.7,2000.0,cw 2006.173.15:01:43.13#flagr#flagr/antenna,new-source 2006.173.15:01:43.13:checkk5 2006.173.15:01:43.49/chk_autoobs//k5ts1/ autoobs is running! 2006.173.15:01:43.89/chk_autoobs//k5ts2/ autoobs is running! 2006.173.15:01:44.31/chk_autoobs//k5ts3/ autoobs is running! 2006.173.15:01:44.71/chk_autoobs//k5ts4/ autoobs is running! 2006.173.15:01:45.10/chk_obsdata//k5ts1/T1731500??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.15:01:45.50/chk_obsdata//k5ts2/T1731500??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.15:01:45.91/chk_obsdata//k5ts3/T1731500??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.15:01:46.32/chk_obsdata//k5ts4/T1731500??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.15:01:47.03/k5log//k5ts1_log_newline 2006.173.15:01:47.74/k5log//k5ts2_log_newline 2006.173.15:01:48.46/k5log//k5ts3_log_newline 2006.173.15:01:49.16/k5log//k5ts4_log_newline 2006.173.15:01:49.19/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.15:01:49.19:setupk4=1 2006.173.15:01:49.19$setupk4/echo=on 2006.173.15:01:49.19$setupk4/pcalon 2006.173.15:01:49.19$pcalon/"no phase cal control is implemented here 2006.173.15:01:49.19$setupk4/"tpicd=stop 2006.173.15:01:49.19$setupk4/"rec=synch_on 2006.173.15:01:49.19$setupk4/"rec_mode=128 2006.173.15:01:49.19$setupk4/!* 2006.173.15:01:49.19$setupk4/recpk4 2006.173.15:01:49.19$recpk4/recpatch= 2006.173.15:01:49.19$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.15:01:49.19$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.15:01:49.19$setupk4/vck44 2006.173.15:01:49.19$vck44/valo=1,524.99 2006.173.15:01:49.19#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.15:01:49.19#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.15:01:49.19#ibcon#ireg 17 cls_cnt 0 2006.173.15:01:49.19#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.15:01:49.19#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.15:01:49.19#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.15:01:49.19#ibcon#enter wrdev, iclass 32, count 0 2006.173.15:01:49.19#ibcon#first serial, iclass 32, count 0 2006.173.15:01:49.19#ibcon#enter sib2, iclass 32, count 0 2006.173.15:01:49.19#ibcon#flushed, iclass 32, count 0 2006.173.15:01:49.19#ibcon#about to write, iclass 32, count 0 2006.173.15:01:49.19#ibcon#wrote, iclass 32, count 0 2006.173.15:01:49.19#ibcon#about to read 3, iclass 32, count 0 2006.173.15:01:49.20#ibcon#read 3, iclass 32, count 0 2006.173.15:01:49.20#ibcon#about to read 4, iclass 32, count 0 2006.173.15:01:49.20#ibcon#read 4, iclass 32, count 0 2006.173.15:01:49.20#ibcon#about to read 5, iclass 32, count 0 2006.173.15:01:49.20#ibcon#read 5, iclass 32, count 0 2006.173.15:01:49.20#ibcon#about to read 6, iclass 32, count 0 2006.173.15:01:49.20#ibcon#read 6, iclass 32, count 0 2006.173.15:01:49.20#ibcon#end of sib2, iclass 32, count 0 2006.173.15:01:49.20#ibcon#*mode == 0, iclass 32, count 0 2006.173.15:01:49.20#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.15:01:49.20#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.15:01:49.20#ibcon#*before write, iclass 32, count 0 2006.173.15:01:49.20#ibcon#enter sib2, iclass 32, count 0 2006.173.15:01:49.20#ibcon#flushed, iclass 32, count 0 2006.173.15:01:49.20#ibcon#about to write, iclass 32, count 0 2006.173.15:01:49.20#ibcon#wrote, iclass 32, count 0 2006.173.15:01:49.20#ibcon#about to read 3, iclass 32, count 0 2006.173.15:01:49.25#ibcon#read 3, iclass 32, count 0 2006.173.15:01:49.25#ibcon#about to read 4, iclass 32, count 0 2006.173.15:01:49.25#ibcon#read 4, iclass 32, count 0 2006.173.15:01:49.25#ibcon#about to read 5, iclass 32, count 0 2006.173.15:01:49.25#ibcon#read 5, iclass 32, count 0 2006.173.15:01:49.25#ibcon#about to read 6, iclass 32, count 0 2006.173.15:01:49.25#ibcon#read 6, iclass 32, count 0 2006.173.15:01:49.25#ibcon#end of sib2, iclass 32, count 0 2006.173.15:01:49.25#ibcon#*after write, iclass 32, count 0 2006.173.15:01:49.25#ibcon#*before return 0, iclass 32, count 0 2006.173.15:01:49.25#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.15:01:49.25#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.15:01:49.25#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.15:01:49.25#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.15:01:49.25$vck44/va=1,7 2006.173.15:01:49.25#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.15:01:49.25#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.15:01:49.25#ibcon#ireg 11 cls_cnt 2 2006.173.15:01:49.25#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.15:01:49.25#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.15:01:49.25#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.15:01:49.25#ibcon#enter wrdev, iclass 34, count 2 2006.173.15:01:49.25#ibcon#first serial, iclass 34, count 2 2006.173.15:01:49.25#ibcon#enter sib2, iclass 34, count 2 2006.173.15:01:49.25#ibcon#flushed, iclass 34, count 2 2006.173.15:01:49.25#ibcon#about to write, iclass 34, count 2 2006.173.15:01:49.25#ibcon#wrote, iclass 34, count 2 2006.173.15:01:49.25#ibcon#about to read 3, iclass 34, count 2 2006.173.15:01:49.27#ibcon#read 3, iclass 34, count 2 2006.173.15:01:49.27#ibcon#about to read 4, iclass 34, count 2 2006.173.15:01:49.27#ibcon#read 4, iclass 34, count 2 2006.173.15:01:49.27#ibcon#about to read 5, iclass 34, count 2 2006.173.15:01:49.27#ibcon#read 5, iclass 34, count 2 2006.173.15:01:49.27#ibcon#about to read 6, iclass 34, count 2 2006.173.15:01:49.27#ibcon#read 6, iclass 34, count 2 2006.173.15:01:49.27#ibcon#end of sib2, iclass 34, count 2 2006.173.15:01:49.27#ibcon#*mode == 0, iclass 34, count 2 2006.173.15:01:49.27#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.15:01:49.27#ibcon#[25=AT01-07\r\n] 2006.173.15:01:49.27#ibcon#*before write, iclass 34, count 2 2006.173.15:01:49.27#ibcon#enter sib2, iclass 34, count 2 2006.173.15:01:49.27#ibcon#flushed, iclass 34, count 2 2006.173.15:01:49.27#ibcon#about to write, iclass 34, count 2 2006.173.15:01:49.27#ibcon#wrote, iclass 34, count 2 2006.173.15:01:49.27#ibcon#about to read 3, iclass 34, count 2 2006.173.15:01:49.30#ibcon#read 3, iclass 34, count 2 2006.173.15:01:49.30#ibcon#about to read 4, iclass 34, count 2 2006.173.15:01:49.30#ibcon#read 4, iclass 34, count 2 2006.173.15:01:49.30#ibcon#about to read 5, iclass 34, count 2 2006.173.15:01:49.30#ibcon#read 5, iclass 34, count 2 2006.173.15:01:49.30#ibcon#about to read 6, iclass 34, count 2 2006.173.15:01:49.30#ibcon#read 6, iclass 34, count 2 2006.173.15:01:49.30#ibcon#end of sib2, iclass 34, count 2 2006.173.15:01:49.30#ibcon#*after write, iclass 34, count 2 2006.173.15:01:49.30#ibcon#*before return 0, iclass 34, count 2 2006.173.15:01:49.30#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.15:01:49.30#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.15:01:49.30#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.15:01:49.30#ibcon#ireg 7 cls_cnt 0 2006.173.15:01:49.30#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.15:01:49.42#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.15:01:49.42#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.15:01:49.42#ibcon#enter wrdev, iclass 34, count 0 2006.173.15:01:49.42#ibcon#first serial, iclass 34, count 0 2006.173.15:01:49.42#ibcon#enter sib2, iclass 34, count 0 2006.173.15:01:49.42#ibcon#flushed, iclass 34, count 0 2006.173.15:01:49.42#ibcon#about to write, iclass 34, count 0 2006.173.15:01:49.42#ibcon#wrote, iclass 34, count 0 2006.173.15:01:49.42#ibcon#about to read 3, iclass 34, count 0 2006.173.15:01:49.44#ibcon#read 3, iclass 34, count 0 2006.173.15:01:49.44#ibcon#about to read 4, iclass 34, count 0 2006.173.15:01:49.44#ibcon#read 4, iclass 34, count 0 2006.173.15:01:49.44#ibcon#about to read 5, iclass 34, count 0 2006.173.15:01:49.44#ibcon#read 5, iclass 34, count 0 2006.173.15:01:49.44#ibcon#about to read 6, iclass 34, count 0 2006.173.15:01:49.44#ibcon#read 6, iclass 34, count 0 2006.173.15:01:49.44#ibcon#end of sib2, iclass 34, count 0 2006.173.15:01:49.44#ibcon#*mode == 0, iclass 34, count 0 2006.173.15:01:49.44#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.15:01:49.44#ibcon#[25=USB\r\n] 2006.173.15:01:49.44#ibcon#*before write, iclass 34, count 0 2006.173.15:01:49.44#ibcon#enter sib2, iclass 34, count 0 2006.173.15:01:49.44#ibcon#flushed, iclass 34, count 0 2006.173.15:01:49.44#ibcon#about to write, iclass 34, count 0 2006.173.15:01:49.44#ibcon#wrote, iclass 34, count 0 2006.173.15:01:49.44#ibcon#about to read 3, iclass 34, count 0 2006.173.15:01:49.47#ibcon#read 3, iclass 34, count 0 2006.173.15:01:49.47#ibcon#about to read 4, iclass 34, count 0 2006.173.15:01:49.47#ibcon#read 4, iclass 34, count 0 2006.173.15:01:49.47#ibcon#about to read 5, iclass 34, count 0 2006.173.15:01:49.47#ibcon#read 5, iclass 34, count 0 2006.173.15:01:49.47#ibcon#about to read 6, iclass 34, count 0 2006.173.15:01:49.47#ibcon#read 6, iclass 34, count 0 2006.173.15:01:49.47#ibcon#end of sib2, iclass 34, count 0 2006.173.15:01:49.47#ibcon#*after write, iclass 34, count 0 2006.173.15:01:49.47#ibcon#*before return 0, iclass 34, count 0 2006.173.15:01:49.47#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.15:01:49.47#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.15:01:49.47#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.15:01:49.47#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.15:01:49.47$vck44/valo=2,534.99 2006.173.15:01:49.47#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.15:01:49.47#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.15:01:49.47#ibcon#ireg 17 cls_cnt 0 2006.173.15:01:49.47#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.15:01:49.47#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.15:01:49.47#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.15:01:49.47#ibcon#enter wrdev, iclass 36, count 0 2006.173.15:01:49.47#ibcon#first serial, iclass 36, count 0 2006.173.15:01:49.47#ibcon#enter sib2, iclass 36, count 0 2006.173.15:01:49.47#ibcon#flushed, iclass 36, count 0 2006.173.15:01:49.47#ibcon#about to write, iclass 36, count 0 2006.173.15:01:49.47#ibcon#wrote, iclass 36, count 0 2006.173.15:01:49.47#ibcon#about to read 3, iclass 36, count 0 2006.173.15:01:49.49#ibcon#read 3, iclass 36, count 0 2006.173.15:01:49.49#ibcon#about to read 4, iclass 36, count 0 2006.173.15:01:49.49#ibcon#read 4, iclass 36, count 0 2006.173.15:01:49.49#ibcon#about to read 5, iclass 36, count 0 2006.173.15:01:49.49#ibcon#read 5, iclass 36, count 0 2006.173.15:01:49.49#ibcon#about to read 6, iclass 36, count 0 2006.173.15:01:49.49#ibcon#read 6, iclass 36, count 0 2006.173.15:01:49.49#ibcon#end of sib2, iclass 36, count 0 2006.173.15:01:49.49#ibcon#*mode == 0, iclass 36, count 0 2006.173.15:01:49.49#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.15:01:49.49#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.15:01:49.49#ibcon#*before write, iclass 36, count 0 2006.173.15:01:49.49#ibcon#enter sib2, iclass 36, count 0 2006.173.15:01:49.49#ibcon#flushed, iclass 36, count 0 2006.173.15:01:49.49#ibcon#about to write, iclass 36, count 0 2006.173.15:01:49.49#ibcon#wrote, iclass 36, count 0 2006.173.15:01:49.49#ibcon#about to read 3, iclass 36, count 0 2006.173.15:01:49.53#ibcon#read 3, iclass 36, count 0 2006.173.15:01:49.53#ibcon#about to read 4, iclass 36, count 0 2006.173.15:01:49.53#ibcon#read 4, iclass 36, count 0 2006.173.15:01:49.53#ibcon#about to read 5, iclass 36, count 0 2006.173.15:01:49.53#ibcon#read 5, iclass 36, count 0 2006.173.15:01:49.53#ibcon#about to read 6, iclass 36, count 0 2006.173.15:01:49.53#ibcon#read 6, iclass 36, count 0 2006.173.15:01:49.53#ibcon#end of sib2, iclass 36, count 0 2006.173.15:01:49.53#ibcon#*after write, iclass 36, count 0 2006.173.15:01:49.53#ibcon#*before return 0, iclass 36, count 0 2006.173.15:01:49.53#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.15:01:49.53#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.15:01:49.53#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.15:01:49.53#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.15:01:49.53$vck44/va=2,6 2006.173.15:01:49.53#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.15:01:49.53#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.15:01:49.53#ibcon#ireg 11 cls_cnt 2 2006.173.15:01:49.53#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.15:01:49.59#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.15:01:49.59#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.15:01:49.59#ibcon#enter wrdev, iclass 38, count 2 2006.173.15:01:49.59#ibcon#first serial, iclass 38, count 2 2006.173.15:01:49.59#ibcon#enter sib2, iclass 38, count 2 2006.173.15:01:49.59#ibcon#flushed, iclass 38, count 2 2006.173.15:01:49.59#ibcon#about to write, iclass 38, count 2 2006.173.15:01:49.59#ibcon#wrote, iclass 38, count 2 2006.173.15:01:49.59#ibcon#about to read 3, iclass 38, count 2 2006.173.15:01:49.61#ibcon#read 3, iclass 38, count 2 2006.173.15:01:49.61#ibcon#about to read 4, iclass 38, count 2 2006.173.15:01:49.61#ibcon#read 4, iclass 38, count 2 2006.173.15:01:49.61#ibcon#about to read 5, iclass 38, count 2 2006.173.15:01:49.61#ibcon#read 5, iclass 38, count 2 2006.173.15:01:49.61#ibcon#about to read 6, iclass 38, count 2 2006.173.15:01:49.61#ibcon#read 6, iclass 38, count 2 2006.173.15:01:49.61#ibcon#end of sib2, iclass 38, count 2 2006.173.15:01:49.61#ibcon#*mode == 0, iclass 38, count 2 2006.173.15:01:49.61#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.15:01:49.61#ibcon#[25=AT02-06\r\n] 2006.173.15:01:49.61#ibcon#*before write, iclass 38, count 2 2006.173.15:01:49.61#ibcon#enter sib2, iclass 38, count 2 2006.173.15:01:49.61#ibcon#flushed, iclass 38, count 2 2006.173.15:01:49.61#ibcon#about to write, iclass 38, count 2 2006.173.15:01:49.61#ibcon#wrote, iclass 38, count 2 2006.173.15:01:49.61#ibcon#about to read 3, iclass 38, count 2 2006.173.15:01:49.64#ibcon#read 3, iclass 38, count 2 2006.173.15:01:49.64#ibcon#about to read 4, iclass 38, count 2 2006.173.15:01:49.64#ibcon#read 4, iclass 38, count 2 2006.173.15:01:49.64#ibcon#about to read 5, iclass 38, count 2 2006.173.15:01:49.64#ibcon#read 5, iclass 38, count 2 2006.173.15:01:49.64#ibcon#about to read 6, iclass 38, count 2 2006.173.15:01:49.64#ibcon#read 6, iclass 38, count 2 2006.173.15:01:49.64#ibcon#end of sib2, iclass 38, count 2 2006.173.15:01:49.64#ibcon#*after write, iclass 38, count 2 2006.173.15:01:49.64#ibcon#*before return 0, iclass 38, count 2 2006.173.15:01:49.64#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.15:01:49.64#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.15:01:49.64#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.15:01:49.64#ibcon#ireg 7 cls_cnt 0 2006.173.15:01:49.64#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.15:01:49.76#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.15:01:49.76#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.15:01:49.76#ibcon#enter wrdev, iclass 38, count 0 2006.173.15:01:49.76#ibcon#first serial, iclass 38, count 0 2006.173.15:01:49.76#ibcon#enter sib2, iclass 38, count 0 2006.173.15:01:49.76#ibcon#flushed, iclass 38, count 0 2006.173.15:01:49.76#ibcon#about to write, iclass 38, count 0 2006.173.15:01:49.76#ibcon#wrote, iclass 38, count 0 2006.173.15:01:49.76#ibcon#about to read 3, iclass 38, count 0 2006.173.15:01:49.78#ibcon#read 3, iclass 38, count 0 2006.173.15:01:49.78#ibcon#about to read 4, iclass 38, count 0 2006.173.15:01:49.78#ibcon#read 4, iclass 38, count 0 2006.173.15:01:49.78#ibcon#about to read 5, iclass 38, count 0 2006.173.15:01:49.78#ibcon#read 5, iclass 38, count 0 2006.173.15:01:49.78#ibcon#about to read 6, iclass 38, count 0 2006.173.15:01:49.78#ibcon#read 6, iclass 38, count 0 2006.173.15:01:49.78#ibcon#end of sib2, iclass 38, count 0 2006.173.15:01:49.78#ibcon#*mode == 0, iclass 38, count 0 2006.173.15:01:49.78#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.15:01:49.78#ibcon#[25=USB\r\n] 2006.173.15:01:49.78#ibcon#*before write, iclass 38, count 0 2006.173.15:01:49.78#ibcon#enter sib2, iclass 38, count 0 2006.173.15:01:49.78#ibcon#flushed, iclass 38, count 0 2006.173.15:01:49.78#ibcon#about to write, iclass 38, count 0 2006.173.15:01:49.78#ibcon#wrote, iclass 38, count 0 2006.173.15:01:49.78#ibcon#about to read 3, iclass 38, count 0 2006.173.15:01:49.81#ibcon#read 3, iclass 38, count 0 2006.173.15:01:49.81#ibcon#about to read 4, iclass 38, count 0 2006.173.15:01:49.81#ibcon#read 4, iclass 38, count 0 2006.173.15:01:49.81#ibcon#about to read 5, iclass 38, count 0 2006.173.15:01:49.81#ibcon#read 5, iclass 38, count 0 2006.173.15:01:49.81#ibcon#about to read 6, iclass 38, count 0 2006.173.15:01:49.81#ibcon#read 6, iclass 38, count 0 2006.173.15:01:49.81#ibcon#end of sib2, iclass 38, count 0 2006.173.15:01:49.81#ibcon#*after write, iclass 38, count 0 2006.173.15:01:49.81#ibcon#*before return 0, iclass 38, count 0 2006.173.15:01:49.81#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.15:01:49.81#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.15:01:49.81#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.15:01:49.81#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.15:01:49.81$vck44/valo=3,564.99 2006.173.15:01:49.81#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.15:01:49.81#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.15:01:49.81#ibcon#ireg 17 cls_cnt 0 2006.173.15:01:49.81#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.15:01:49.81#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.15:01:49.81#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.15:01:49.81#ibcon#enter wrdev, iclass 40, count 0 2006.173.15:01:49.81#ibcon#first serial, iclass 40, count 0 2006.173.15:01:49.81#ibcon#enter sib2, iclass 40, count 0 2006.173.15:01:49.81#ibcon#flushed, iclass 40, count 0 2006.173.15:01:49.81#ibcon#about to write, iclass 40, count 0 2006.173.15:01:49.81#ibcon#wrote, iclass 40, count 0 2006.173.15:01:49.81#ibcon#about to read 3, iclass 40, count 0 2006.173.15:01:49.83#ibcon#read 3, iclass 40, count 0 2006.173.15:01:49.83#ibcon#about to read 4, iclass 40, count 0 2006.173.15:01:49.83#ibcon#read 4, iclass 40, count 0 2006.173.15:01:49.83#ibcon#about to read 5, iclass 40, count 0 2006.173.15:01:49.83#ibcon#read 5, iclass 40, count 0 2006.173.15:01:49.83#ibcon#about to read 6, iclass 40, count 0 2006.173.15:01:49.83#ibcon#read 6, iclass 40, count 0 2006.173.15:01:49.83#ibcon#end of sib2, iclass 40, count 0 2006.173.15:01:49.83#ibcon#*mode == 0, iclass 40, count 0 2006.173.15:01:49.83#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.15:01:49.83#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.15:01:49.83#ibcon#*before write, iclass 40, count 0 2006.173.15:01:49.83#ibcon#enter sib2, iclass 40, count 0 2006.173.15:01:49.83#ibcon#flushed, iclass 40, count 0 2006.173.15:01:49.83#ibcon#about to write, iclass 40, count 0 2006.173.15:01:49.83#ibcon#wrote, iclass 40, count 0 2006.173.15:01:49.83#ibcon#about to read 3, iclass 40, count 0 2006.173.15:01:49.87#ibcon#read 3, iclass 40, count 0 2006.173.15:01:49.87#ibcon#about to read 4, iclass 40, count 0 2006.173.15:01:49.87#ibcon#read 4, iclass 40, count 0 2006.173.15:01:49.87#ibcon#about to read 5, iclass 40, count 0 2006.173.15:01:49.87#ibcon#read 5, iclass 40, count 0 2006.173.15:01:49.87#ibcon#about to read 6, iclass 40, count 0 2006.173.15:01:49.87#ibcon#read 6, iclass 40, count 0 2006.173.15:01:49.87#ibcon#end of sib2, iclass 40, count 0 2006.173.15:01:49.87#ibcon#*after write, iclass 40, count 0 2006.173.15:01:49.87#ibcon#*before return 0, iclass 40, count 0 2006.173.15:01:49.87#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.15:01:49.87#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.15:01:49.87#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.15:01:49.87#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.15:01:49.87$vck44/va=3,5 2006.173.15:01:49.87#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.15:01:49.87#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.15:01:49.87#ibcon#ireg 11 cls_cnt 2 2006.173.15:01:49.87#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.15:01:49.93#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.15:01:49.93#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.15:01:49.93#ibcon#enter wrdev, iclass 4, count 2 2006.173.15:01:49.93#ibcon#first serial, iclass 4, count 2 2006.173.15:01:49.93#ibcon#enter sib2, iclass 4, count 2 2006.173.15:01:49.93#ibcon#flushed, iclass 4, count 2 2006.173.15:01:49.93#ibcon#about to write, iclass 4, count 2 2006.173.15:01:49.93#ibcon#wrote, iclass 4, count 2 2006.173.15:01:49.93#ibcon#about to read 3, iclass 4, count 2 2006.173.15:01:49.95#ibcon#read 3, iclass 4, count 2 2006.173.15:01:49.95#ibcon#about to read 4, iclass 4, count 2 2006.173.15:01:49.95#ibcon#read 4, iclass 4, count 2 2006.173.15:01:49.95#ibcon#about to read 5, iclass 4, count 2 2006.173.15:01:49.95#ibcon#read 5, iclass 4, count 2 2006.173.15:01:49.95#ibcon#about to read 6, iclass 4, count 2 2006.173.15:01:49.95#ibcon#read 6, iclass 4, count 2 2006.173.15:01:49.95#ibcon#end of sib2, iclass 4, count 2 2006.173.15:01:49.95#ibcon#*mode == 0, iclass 4, count 2 2006.173.15:01:49.95#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.15:01:49.95#ibcon#[25=AT03-05\r\n] 2006.173.15:01:49.95#ibcon#*before write, iclass 4, count 2 2006.173.15:01:49.95#ibcon#enter sib2, iclass 4, count 2 2006.173.15:01:49.95#ibcon#flushed, iclass 4, count 2 2006.173.15:01:49.95#ibcon#about to write, iclass 4, count 2 2006.173.15:01:49.95#ibcon#wrote, iclass 4, count 2 2006.173.15:01:49.95#ibcon#about to read 3, iclass 4, count 2 2006.173.15:01:49.98#ibcon#read 3, iclass 4, count 2 2006.173.15:01:49.98#ibcon#about to read 4, iclass 4, count 2 2006.173.15:01:49.98#ibcon#read 4, iclass 4, count 2 2006.173.15:01:49.98#ibcon#about to read 5, iclass 4, count 2 2006.173.15:01:49.98#ibcon#read 5, iclass 4, count 2 2006.173.15:01:49.98#ibcon#about to read 6, iclass 4, count 2 2006.173.15:01:49.98#ibcon#read 6, iclass 4, count 2 2006.173.15:01:49.98#ibcon#end of sib2, iclass 4, count 2 2006.173.15:01:49.98#ibcon#*after write, iclass 4, count 2 2006.173.15:01:49.98#ibcon#*before return 0, iclass 4, count 2 2006.173.15:01:49.98#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.15:01:49.98#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.15:01:49.98#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.15:01:49.98#ibcon#ireg 7 cls_cnt 0 2006.173.15:01:49.98#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.15:01:50.10#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.15:01:50.10#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.15:01:50.10#ibcon#enter wrdev, iclass 4, count 0 2006.173.15:01:50.10#ibcon#first serial, iclass 4, count 0 2006.173.15:01:50.10#ibcon#enter sib2, iclass 4, count 0 2006.173.15:01:50.10#ibcon#flushed, iclass 4, count 0 2006.173.15:01:50.10#ibcon#about to write, iclass 4, count 0 2006.173.15:01:50.10#ibcon#wrote, iclass 4, count 0 2006.173.15:01:50.10#ibcon#about to read 3, iclass 4, count 0 2006.173.15:01:50.12#ibcon#read 3, iclass 4, count 0 2006.173.15:01:50.12#ibcon#about to read 4, iclass 4, count 0 2006.173.15:01:50.12#ibcon#read 4, iclass 4, count 0 2006.173.15:01:50.12#ibcon#about to read 5, iclass 4, count 0 2006.173.15:01:50.12#ibcon#read 5, iclass 4, count 0 2006.173.15:01:50.12#ibcon#about to read 6, iclass 4, count 0 2006.173.15:01:50.12#ibcon#read 6, iclass 4, count 0 2006.173.15:01:50.12#ibcon#end of sib2, iclass 4, count 0 2006.173.15:01:50.12#ibcon#*mode == 0, iclass 4, count 0 2006.173.15:01:50.12#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.15:01:50.12#ibcon#[25=USB\r\n] 2006.173.15:01:50.12#ibcon#*before write, iclass 4, count 0 2006.173.15:01:50.12#ibcon#enter sib2, iclass 4, count 0 2006.173.15:01:50.12#ibcon#flushed, iclass 4, count 0 2006.173.15:01:50.12#ibcon#about to write, iclass 4, count 0 2006.173.15:01:50.12#ibcon#wrote, iclass 4, count 0 2006.173.15:01:50.12#ibcon#about to read 3, iclass 4, count 0 2006.173.15:01:50.15#ibcon#read 3, iclass 4, count 0 2006.173.15:01:50.15#ibcon#about to read 4, iclass 4, count 0 2006.173.15:01:50.15#ibcon#read 4, iclass 4, count 0 2006.173.15:01:50.15#ibcon#about to read 5, iclass 4, count 0 2006.173.15:01:50.15#ibcon#read 5, iclass 4, count 0 2006.173.15:01:50.15#ibcon#about to read 6, iclass 4, count 0 2006.173.15:01:50.15#ibcon#read 6, iclass 4, count 0 2006.173.15:01:50.15#ibcon#end of sib2, iclass 4, count 0 2006.173.15:01:50.15#ibcon#*after write, iclass 4, count 0 2006.173.15:01:50.15#ibcon#*before return 0, iclass 4, count 0 2006.173.15:01:50.15#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.15:01:50.15#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.15:01:50.15#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.15:01:50.15#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.15:01:50.15$vck44/valo=4,624.99 2006.173.15:01:50.15#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.15:01:50.15#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.15:01:50.15#ibcon#ireg 17 cls_cnt 0 2006.173.15:01:50.15#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.15:01:50.15#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.15:01:50.15#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.15:01:50.15#ibcon#enter wrdev, iclass 6, count 0 2006.173.15:01:50.15#ibcon#first serial, iclass 6, count 0 2006.173.15:01:50.15#ibcon#enter sib2, iclass 6, count 0 2006.173.15:01:50.15#ibcon#flushed, iclass 6, count 0 2006.173.15:01:50.15#ibcon#about to write, iclass 6, count 0 2006.173.15:01:50.15#ibcon#wrote, iclass 6, count 0 2006.173.15:01:50.15#ibcon#about to read 3, iclass 6, count 0 2006.173.15:01:50.17#ibcon#read 3, iclass 6, count 0 2006.173.15:01:50.17#ibcon#about to read 4, iclass 6, count 0 2006.173.15:01:50.17#ibcon#read 4, iclass 6, count 0 2006.173.15:01:50.17#ibcon#about to read 5, iclass 6, count 0 2006.173.15:01:50.17#ibcon#read 5, iclass 6, count 0 2006.173.15:01:50.17#ibcon#about to read 6, iclass 6, count 0 2006.173.15:01:50.17#ibcon#read 6, iclass 6, count 0 2006.173.15:01:50.17#ibcon#end of sib2, iclass 6, count 0 2006.173.15:01:50.17#ibcon#*mode == 0, iclass 6, count 0 2006.173.15:01:50.17#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.15:01:50.17#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.15:01:50.17#ibcon#*before write, iclass 6, count 0 2006.173.15:01:50.17#ibcon#enter sib2, iclass 6, count 0 2006.173.15:01:50.17#ibcon#flushed, iclass 6, count 0 2006.173.15:01:50.17#ibcon#about to write, iclass 6, count 0 2006.173.15:01:50.17#ibcon#wrote, iclass 6, count 0 2006.173.15:01:50.17#ibcon#about to read 3, iclass 6, count 0 2006.173.15:01:50.21#ibcon#read 3, iclass 6, count 0 2006.173.15:01:50.21#ibcon#about to read 4, iclass 6, count 0 2006.173.15:01:50.21#ibcon#read 4, iclass 6, count 0 2006.173.15:01:50.21#ibcon#about to read 5, iclass 6, count 0 2006.173.15:01:50.21#ibcon#read 5, iclass 6, count 0 2006.173.15:01:50.21#ibcon#about to read 6, iclass 6, count 0 2006.173.15:01:50.21#ibcon#read 6, iclass 6, count 0 2006.173.15:01:50.21#ibcon#end of sib2, iclass 6, count 0 2006.173.15:01:50.21#ibcon#*after write, iclass 6, count 0 2006.173.15:01:50.21#ibcon#*before return 0, iclass 6, count 0 2006.173.15:01:50.21#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.15:01:50.21#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.15:01:50.21#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.15:01:50.21#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.15:01:50.21$vck44/va=4,6 2006.173.15:01:50.21#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.15:01:50.21#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.15:01:50.21#ibcon#ireg 11 cls_cnt 2 2006.173.15:01:50.21#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.15:01:50.27#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.15:01:50.27#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.15:01:50.27#ibcon#enter wrdev, iclass 10, count 2 2006.173.15:01:50.27#ibcon#first serial, iclass 10, count 2 2006.173.15:01:50.27#ibcon#enter sib2, iclass 10, count 2 2006.173.15:01:50.27#ibcon#flushed, iclass 10, count 2 2006.173.15:01:50.27#ibcon#about to write, iclass 10, count 2 2006.173.15:01:50.27#ibcon#wrote, iclass 10, count 2 2006.173.15:01:50.27#ibcon#about to read 3, iclass 10, count 2 2006.173.15:01:50.29#ibcon#read 3, iclass 10, count 2 2006.173.15:01:50.29#ibcon#about to read 4, iclass 10, count 2 2006.173.15:01:50.29#ibcon#read 4, iclass 10, count 2 2006.173.15:01:50.29#ibcon#about to read 5, iclass 10, count 2 2006.173.15:01:50.29#ibcon#read 5, iclass 10, count 2 2006.173.15:01:50.29#ibcon#about to read 6, iclass 10, count 2 2006.173.15:01:50.29#ibcon#read 6, iclass 10, count 2 2006.173.15:01:50.29#ibcon#end of sib2, iclass 10, count 2 2006.173.15:01:50.29#ibcon#*mode == 0, iclass 10, count 2 2006.173.15:01:50.29#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.15:01:50.29#ibcon#[25=AT04-06\r\n] 2006.173.15:01:50.29#ibcon#*before write, iclass 10, count 2 2006.173.15:01:50.29#ibcon#enter sib2, iclass 10, count 2 2006.173.15:01:50.29#ibcon#flushed, iclass 10, count 2 2006.173.15:01:50.29#ibcon#about to write, iclass 10, count 2 2006.173.15:01:50.29#ibcon#wrote, iclass 10, count 2 2006.173.15:01:50.29#ibcon#about to read 3, iclass 10, count 2 2006.173.15:01:50.32#ibcon#read 3, iclass 10, count 2 2006.173.15:01:50.32#ibcon#about to read 4, iclass 10, count 2 2006.173.15:01:50.32#ibcon#read 4, iclass 10, count 2 2006.173.15:01:50.32#ibcon#about to read 5, iclass 10, count 2 2006.173.15:01:50.32#ibcon#read 5, iclass 10, count 2 2006.173.15:01:50.32#ibcon#about to read 6, iclass 10, count 2 2006.173.15:01:50.32#ibcon#read 6, iclass 10, count 2 2006.173.15:01:50.32#ibcon#end of sib2, iclass 10, count 2 2006.173.15:01:50.32#ibcon#*after write, iclass 10, count 2 2006.173.15:01:50.32#ibcon#*before return 0, iclass 10, count 2 2006.173.15:01:50.32#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.15:01:50.32#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.15:01:50.32#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.15:01:50.32#ibcon#ireg 7 cls_cnt 0 2006.173.15:01:50.32#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.15:01:50.44#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.15:01:50.44#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.15:01:50.44#ibcon#enter wrdev, iclass 10, count 0 2006.173.15:01:50.44#ibcon#first serial, iclass 10, count 0 2006.173.15:01:50.44#ibcon#enter sib2, iclass 10, count 0 2006.173.15:01:50.44#ibcon#flushed, iclass 10, count 0 2006.173.15:01:50.44#ibcon#about to write, iclass 10, count 0 2006.173.15:01:50.44#ibcon#wrote, iclass 10, count 0 2006.173.15:01:50.44#ibcon#about to read 3, iclass 10, count 0 2006.173.15:01:50.46#ibcon#read 3, iclass 10, count 0 2006.173.15:01:50.46#ibcon#about to read 4, iclass 10, count 0 2006.173.15:01:50.46#ibcon#read 4, iclass 10, count 0 2006.173.15:01:50.46#ibcon#about to read 5, iclass 10, count 0 2006.173.15:01:50.46#ibcon#read 5, iclass 10, count 0 2006.173.15:01:50.46#ibcon#about to read 6, iclass 10, count 0 2006.173.15:01:50.46#ibcon#read 6, iclass 10, count 0 2006.173.15:01:50.46#ibcon#end of sib2, iclass 10, count 0 2006.173.15:01:50.46#ibcon#*mode == 0, iclass 10, count 0 2006.173.15:01:50.46#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.15:01:50.46#ibcon#[25=USB\r\n] 2006.173.15:01:50.46#ibcon#*before write, iclass 10, count 0 2006.173.15:01:50.46#ibcon#enter sib2, iclass 10, count 0 2006.173.15:01:50.46#ibcon#flushed, iclass 10, count 0 2006.173.15:01:50.46#ibcon#about to write, iclass 10, count 0 2006.173.15:01:50.46#ibcon#wrote, iclass 10, count 0 2006.173.15:01:50.46#ibcon#about to read 3, iclass 10, count 0 2006.173.15:01:50.49#ibcon#read 3, iclass 10, count 0 2006.173.15:01:50.49#ibcon#about to read 4, iclass 10, count 0 2006.173.15:01:50.49#ibcon#read 4, iclass 10, count 0 2006.173.15:01:50.49#ibcon#about to read 5, iclass 10, count 0 2006.173.15:01:50.49#ibcon#read 5, iclass 10, count 0 2006.173.15:01:50.49#ibcon#about to read 6, iclass 10, count 0 2006.173.15:01:50.49#ibcon#read 6, iclass 10, count 0 2006.173.15:01:50.49#ibcon#end of sib2, iclass 10, count 0 2006.173.15:01:50.49#ibcon#*after write, iclass 10, count 0 2006.173.15:01:50.49#ibcon#*before return 0, iclass 10, count 0 2006.173.15:01:50.49#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.15:01:50.49#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.15:01:50.49#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.15:01:50.49#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.15:01:50.49$vck44/valo=5,734.99 2006.173.15:01:50.49#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.15:01:50.49#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.15:01:50.49#ibcon#ireg 17 cls_cnt 0 2006.173.15:01:50.49#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.15:01:50.49#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.15:01:50.49#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.15:01:50.49#ibcon#enter wrdev, iclass 12, count 0 2006.173.15:01:50.49#ibcon#first serial, iclass 12, count 0 2006.173.15:01:50.49#ibcon#enter sib2, iclass 12, count 0 2006.173.15:01:50.49#ibcon#flushed, iclass 12, count 0 2006.173.15:01:50.49#ibcon#about to write, iclass 12, count 0 2006.173.15:01:50.49#ibcon#wrote, iclass 12, count 0 2006.173.15:01:50.49#ibcon#about to read 3, iclass 12, count 0 2006.173.15:01:50.51#ibcon#read 3, iclass 12, count 0 2006.173.15:01:50.51#ibcon#about to read 4, iclass 12, count 0 2006.173.15:01:50.51#ibcon#read 4, iclass 12, count 0 2006.173.15:01:50.51#ibcon#about to read 5, iclass 12, count 0 2006.173.15:01:50.51#ibcon#read 5, iclass 12, count 0 2006.173.15:01:50.51#ibcon#about to read 6, iclass 12, count 0 2006.173.15:01:50.51#ibcon#read 6, iclass 12, count 0 2006.173.15:01:50.51#ibcon#end of sib2, iclass 12, count 0 2006.173.15:01:50.51#ibcon#*mode == 0, iclass 12, count 0 2006.173.15:01:50.51#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.15:01:50.51#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.15:01:50.51#ibcon#*before write, iclass 12, count 0 2006.173.15:01:50.51#ibcon#enter sib2, iclass 12, count 0 2006.173.15:01:50.51#ibcon#flushed, iclass 12, count 0 2006.173.15:01:50.51#ibcon#about to write, iclass 12, count 0 2006.173.15:01:50.51#ibcon#wrote, iclass 12, count 0 2006.173.15:01:50.51#ibcon#about to read 3, iclass 12, count 0 2006.173.15:01:50.55#ibcon#read 3, iclass 12, count 0 2006.173.15:01:50.55#ibcon#about to read 4, iclass 12, count 0 2006.173.15:01:50.55#ibcon#read 4, iclass 12, count 0 2006.173.15:01:50.55#ibcon#about to read 5, iclass 12, count 0 2006.173.15:01:50.55#ibcon#read 5, iclass 12, count 0 2006.173.15:01:50.55#ibcon#about to read 6, iclass 12, count 0 2006.173.15:01:50.55#ibcon#read 6, iclass 12, count 0 2006.173.15:01:50.55#ibcon#end of sib2, iclass 12, count 0 2006.173.15:01:50.55#ibcon#*after write, iclass 12, count 0 2006.173.15:01:50.55#ibcon#*before return 0, iclass 12, count 0 2006.173.15:01:50.55#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.15:01:50.55#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.15:01:50.55#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.15:01:50.55#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.15:01:50.55$vck44/va=5,4 2006.173.15:01:50.55#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.15:01:50.55#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.15:01:50.55#ibcon#ireg 11 cls_cnt 2 2006.173.15:01:50.55#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.15:01:50.61#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.15:01:50.61#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.15:01:50.61#ibcon#enter wrdev, iclass 14, count 2 2006.173.15:01:50.61#ibcon#first serial, iclass 14, count 2 2006.173.15:01:50.61#ibcon#enter sib2, iclass 14, count 2 2006.173.15:01:50.61#ibcon#flushed, iclass 14, count 2 2006.173.15:01:50.61#ibcon#about to write, iclass 14, count 2 2006.173.15:01:50.61#ibcon#wrote, iclass 14, count 2 2006.173.15:01:50.61#ibcon#about to read 3, iclass 14, count 2 2006.173.15:01:50.63#ibcon#read 3, iclass 14, count 2 2006.173.15:01:50.63#ibcon#about to read 4, iclass 14, count 2 2006.173.15:01:50.63#ibcon#read 4, iclass 14, count 2 2006.173.15:01:50.63#ibcon#about to read 5, iclass 14, count 2 2006.173.15:01:50.63#ibcon#read 5, iclass 14, count 2 2006.173.15:01:50.63#ibcon#about to read 6, iclass 14, count 2 2006.173.15:01:50.63#ibcon#read 6, iclass 14, count 2 2006.173.15:01:50.63#ibcon#end of sib2, iclass 14, count 2 2006.173.15:01:50.63#ibcon#*mode == 0, iclass 14, count 2 2006.173.15:01:50.63#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.15:01:50.63#ibcon#[25=AT05-04\r\n] 2006.173.15:01:50.63#ibcon#*before write, iclass 14, count 2 2006.173.15:01:50.63#ibcon#enter sib2, iclass 14, count 2 2006.173.15:01:50.63#ibcon#flushed, iclass 14, count 2 2006.173.15:01:50.63#ibcon#about to write, iclass 14, count 2 2006.173.15:01:50.63#ibcon#wrote, iclass 14, count 2 2006.173.15:01:50.63#ibcon#about to read 3, iclass 14, count 2 2006.173.15:01:50.66#ibcon#read 3, iclass 14, count 2 2006.173.15:01:50.66#ibcon#about to read 4, iclass 14, count 2 2006.173.15:01:50.66#ibcon#read 4, iclass 14, count 2 2006.173.15:01:50.66#ibcon#about to read 5, iclass 14, count 2 2006.173.15:01:50.66#ibcon#read 5, iclass 14, count 2 2006.173.15:01:50.66#ibcon#about to read 6, iclass 14, count 2 2006.173.15:01:50.66#ibcon#read 6, iclass 14, count 2 2006.173.15:01:50.66#ibcon#end of sib2, iclass 14, count 2 2006.173.15:01:50.66#ibcon#*after write, iclass 14, count 2 2006.173.15:01:50.66#ibcon#*before return 0, iclass 14, count 2 2006.173.15:01:50.66#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.15:01:50.66#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.15:01:50.66#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.15:01:50.66#ibcon#ireg 7 cls_cnt 0 2006.173.15:01:50.66#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.15:01:50.78#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.15:01:50.78#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.15:01:50.78#ibcon#enter wrdev, iclass 14, count 0 2006.173.15:01:50.78#ibcon#first serial, iclass 14, count 0 2006.173.15:01:50.78#ibcon#enter sib2, iclass 14, count 0 2006.173.15:01:50.78#ibcon#flushed, iclass 14, count 0 2006.173.15:01:50.78#ibcon#about to write, iclass 14, count 0 2006.173.15:01:50.78#ibcon#wrote, iclass 14, count 0 2006.173.15:01:50.78#ibcon#about to read 3, iclass 14, count 0 2006.173.15:01:50.80#ibcon#read 3, iclass 14, count 0 2006.173.15:01:50.80#ibcon#about to read 4, iclass 14, count 0 2006.173.15:01:50.80#ibcon#read 4, iclass 14, count 0 2006.173.15:01:50.80#ibcon#about to read 5, iclass 14, count 0 2006.173.15:01:50.80#ibcon#read 5, iclass 14, count 0 2006.173.15:01:50.80#ibcon#about to read 6, iclass 14, count 0 2006.173.15:01:50.80#ibcon#read 6, iclass 14, count 0 2006.173.15:01:50.80#ibcon#end of sib2, iclass 14, count 0 2006.173.15:01:50.80#ibcon#*mode == 0, iclass 14, count 0 2006.173.15:01:50.80#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.15:01:50.80#ibcon#[25=USB\r\n] 2006.173.15:01:50.80#ibcon#*before write, iclass 14, count 0 2006.173.15:01:50.80#ibcon#enter sib2, iclass 14, count 0 2006.173.15:01:50.80#ibcon#flushed, iclass 14, count 0 2006.173.15:01:50.80#ibcon#about to write, iclass 14, count 0 2006.173.15:01:50.80#ibcon#wrote, iclass 14, count 0 2006.173.15:01:50.80#ibcon#about to read 3, iclass 14, count 0 2006.173.15:01:50.83#ibcon#read 3, iclass 14, count 0 2006.173.15:01:50.83#ibcon#about to read 4, iclass 14, count 0 2006.173.15:01:50.83#ibcon#read 4, iclass 14, count 0 2006.173.15:01:50.83#ibcon#about to read 5, iclass 14, count 0 2006.173.15:01:50.83#ibcon#read 5, iclass 14, count 0 2006.173.15:01:50.83#ibcon#about to read 6, iclass 14, count 0 2006.173.15:01:50.83#ibcon#read 6, iclass 14, count 0 2006.173.15:01:50.83#ibcon#end of sib2, iclass 14, count 0 2006.173.15:01:50.83#ibcon#*after write, iclass 14, count 0 2006.173.15:01:50.83#ibcon#*before return 0, iclass 14, count 0 2006.173.15:01:50.83#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.15:01:50.83#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.15:01:50.83#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.15:01:50.83#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.15:01:50.83$vck44/valo=6,814.99 2006.173.15:01:50.83#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.15:01:50.83#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.15:01:50.83#ibcon#ireg 17 cls_cnt 0 2006.173.15:01:50.83#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.15:01:50.83#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.15:01:50.83#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.15:01:50.83#ibcon#enter wrdev, iclass 16, count 0 2006.173.15:01:50.83#ibcon#first serial, iclass 16, count 0 2006.173.15:01:50.83#ibcon#enter sib2, iclass 16, count 0 2006.173.15:01:50.83#ibcon#flushed, iclass 16, count 0 2006.173.15:01:50.83#ibcon#about to write, iclass 16, count 0 2006.173.15:01:50.83#ibcon#wrote, iclass 16, count 0 2006.173.15:01:50.83#ibcon#about to read 3, iclass 16, count 0 2006.173.15:01:50.85#ibcon#read 3, iclass 16, count 0 2006.173.15:01:50.85#ibcon#about to read 4, iclass 16, count 0 2006.173.15:01:50.85#ibcon#read 4, iclass 16, count 0 2006.173.15:01:50.85#ibcon#about to read 5, iclass 16, count 0 2006.173.15:01:50.85#ibcon#read 5, iclass 16, count 0 2006.173.15:01:50.85#ibcon#about to read 6, iclass 16, count 0 2006.173.15:01:50.85#ibcon#read 6, iclass 16, count 0 2006.173.15:01:50.85#ibcon#end of sib2, iclass 16, count 0 2006.173.15:01:50.85#ibcon#*mode == 0, iclass 16, count 0 2006.173.15:01:50.85#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.15:01:50.85#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.15:01:50.85#ibcon#*before write, iclass 16, count 0 2006.173.15:01:50.85#ibcon#enter sib2, iclass 16, count 0 2006.173.15:01:50.85#ibcon#flushed, iclass 16, count 0 2006.173.15:01:50.85#ibcon#about to write, iclass 16, count 0 2006.173.15:01:50.85#ibcon#wrote, iclass 16, count 0 2006.173.15:01:50.85#ibcon#about to read 3, iclass 16, count 0 2006.173.15:01:50.89#ibcon#read 3, iclass 16, count 0 2006.173.15:01:50.89#ibcon#about to read 4, iclass 16, count 0 2006.173.15:01:50.89#ibcon#read 4, iclass 16, count 0 2006.173.15:01:50.89#ibcon#about to read 5, iclass 16, count 0 2006.173.15:01:50.89#ibcon#read 5, iclass 16, count 0 2006.173.15:01:50.89#ibcon#about to read 6, iclass 16, count 0 2006.173.15:01:50.89#ibcon#read 6, iclass 16, count 0 2006.173.15:01:50.89#ibcon#end of sib2, iclass 16, count 0 2006.173.15:01:50.89#ibcon#*after write, iclass 16, count 0 2006.173.15:01:50.89#ibcon#*before return 0, iclass 16, count 0 2006.173.15:01:50.89#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.15:01:50.89#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.15:01:50.89#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.15:01:50.89#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.15:01:50.89$vck44/va=6,3 2006.173.15:01:50.89#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.15:01:50.89#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.15:01:50.89#ibcon#ireg 11 cls_cnt 2 2006.173.15:01:50.89#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.15:01:50.95#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.15:01:50.95#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.15:01:50.95#ibcon#enter wrdev, iclass 18, count 2 2006.173.15:01:50.95#ibcon#first serial, iclass 18, count 2 2006.173.15:01:50.95#ibcon#enter sib2, iclass 18, count 2 2006.173.15:01:50.95#ibcon#flushed, iclass 18, count 2 2006.173.15:01:50.95#ibcon#about to write, iclass 18, count 2 2006.173.15:01:50.95#ibcon#wrote, iclass 18, count 2 2006.173.15:01:50.95#ibcon#about to read 3, iclass 18, count 2 2006.173.15:01:50.97#ibcon#read 3, iclass 18, count 2 2006.173.15:01:50.97#ibcon#about to read 4, iclass 18, count 2 2006.173.15:01:50.97#ibcon#read 4, iclass 18, count 2 2006.173.15:01:50.97#ibcon#about to read 5, iclass 18, count 2 2006.173.15:01:50.97#ibcon#read 5, iclass 18, count 2 2006.173.15:01:50.97#ibcon#about to read 6, iclass 18, count 2 2006.173.15:01:50.97#ibcon#read 6, iclass 18, count 2 2006.173.15:01:50.97#ibcon#end of sib2, iclass 18, count 2 2006.173.15:01:50.97#ibcon#*mode == 0, iclass 18, count 2 2006.173.15:01:50.97#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.15:01:50.97#ibcon#[25=AT06-03\r\n] 2006.173.15:01:50.97#ibcon#*before write, iclass 18, count 2 2006.173.15:01:50.97#ibcon#enter sib2, iclass 18, count 2 2006.173.15:01:50.97#ibcon#flushed, iclass 18, count 2 2006.173.15:01:50.97#ibcon#about to write, iclass 18, count 2 2006.173.15:01:50.97#ibcon#wrote, iclass 18, count 2 2006.173.15:01:50.97#ibcon#about to read 3, iclass 18, count 2 2006.173.15:01:51.00#ibcon#read 3, iclass 18, count 2 2006.173.15:01:51.00#ibcon#about to read 4, iclass 18, count 2 2006.173.15:01:51.00#ibcon#read 4, iclass 18, count 2 2006.173.15:01:51.00#ibcon#about to read 5, iclass 18, count 2 2006.173.15:01:51.00#ibcon#read 5, iclass 18, count 2 2006.173.15:01:51.00#ibcon#about to read 6, iclass 18, count 2 2006.173.15:01:51.00#ibcon#read 6, iclass 18, count 2 2006.173.15:01:51.00#ibcon#end of sib2, iclass 18, count 2 2006.173.15:01:51.00#ibcon#*after write, iclass 18, count 2 2006.173.15:01:51.00#ibcon#*before return 0, iclass 18, count 2 2006.173.15:01:51.00#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.15:01:51.00#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.15:01:51.00#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.15:01:51.00#ibcon#ireg 7 cls_cnt 0 2006.173.15:01:51.00#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.15:01:51.12#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.15:01:51.12#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.15:01:51.12#ibcon#enter wrdev, iclass 18, count 0 2006.173.15:01:51.12#ibcon#first serial, iclass 18, count 0 2006.173.15:01:51.12#ibcon#enter sib2, iclass 18, count 0 2006.173.15:01:51.12#ibcon#flushed, iclass 18, count 0 2006.173.15:01:51.12#ibcon#about to write, iclass 18, count 0 2006.173.15:01:51.12#ibcon#wrote, iclass 18, count 0 2006.173.15:01:51.12#ibcon#about to read 3, iclass 18, count 0 2006.173.15:01:51.14#ibcon#read 3, iclass 18, count 0 2006.173.15:01:51.14#ibcon#about to read 4, iclass 18, count 0 2006.173.15:01:51.14#ibcon#read 4, iclass 18, count 0 2006.173.15:01:51.14#ibcon#about to read 5, iclass 18, count 0 2006.173.15:01:51.14#ibcon#read 5, iclass 18, count 0 2006.173.15:01:51.14#ibcon#about to read 6, iclass 18, count 0 2006.173.15:01:51.14#ibcon#read 6, iclass 18, count 0 2006.173.15:01:51.14#ibcon#end of sib2, iclass 18, count 0 2006.173.15:01:51.14#ibcon#*mode == 0, iclass 18, count 0 2006.173.15:01:51.14#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.15:01:51.14#ibcon#[25=USB\r\n] 2006.173.15:01:51.14#ibcon#*before write, iclass 18, count 0 2006.173.15:01:51.14#ibcon#enter sib2, iclass 18, count 0 2006.173.15:01:51.14#ibcon#flushed, iclass 18, count 0 2006.173.15:01:51.14#ibcon#about to write, iclass 18, count 0 2006.173.15:01:51.14#ibcon#wrote, iclass 18, count 0 2006.173.15:01:51.14#ibcon#about to read 3, iclass 18, count 0 2006.173.15:01:51.17#ibcon#read 3, iclass 18, count 0 2006.173.15:01:51.17#ibcon#about to read 4, iclass 18, count 0 2006.173.15:01:51.17#ibcon#read 4, iclass 18, count 0 2006.173.15:01:51.17#ibcon#about to read 5, iclass 18, count 0 2006.173.15:01:51.17#ibcon#read 5, iclass 18, count 0 2006.173.15:01:51.17#ibcon#about to read 6, iclass 18, count 0 2006.173.15:01:51.17#ibcon#read 6, iclass 18, count 0 2006.173.15:01:51.17#ibcon#end of sib2, iclass 18, count 0 2006.173.15:01:51.17#ibcon#*after write, iclass 18, count 0 2006.173.15:01:51.17#ibcon#*before return 0, iclass 18, count 0 2006.173.15:01:51.17#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.15:01:51.17#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.15:01:51.17#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.15:01:51.17#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.15:01:51.17$vck44/valo=7,864.99 2006.173.15:01:51.17#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.15:01:51.17#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.15:01:51.17#ibcon#ireg 17 cls_cnt 0 2006.173.15:01:51.17#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.15:01:51.17#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.15:01:51.17#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.15:01:51.17#ibcon#enter wrdev, iclass 20, count 0 2006.173.15:01:51.17#ibcon#first serial, iclass 20, count 0 2006.173.15:01:51.17#ibcon#enter sib2, iclass 20, count 0 2006.173.15:01:51.17#ibcon#flushed, iclass 20, count 0 2006.173.15:01:51.17#ibcon#about to write, iclass 20, count 0 2006.173.15:01:51.17#ibcon#wrote, iclass 20, count 0 2006.173.15:01:51.17#ibcon#about to read 3, iclass 20, count 0 2006.173.15:01:51.19#ibcon#read 3, iclass 20, count 0 2006.173.15:01:51.19#ibcon#about to read 4, iclass 20, count 0 2006.173.15:01:51.19#ibcon#read 4, iclass 20, count 0 2006.173.15:01:51.19#ibcon#about to read 5, iclass 20, count 0 2006.173.15:01:51.19#ibcon#read 5, iclass 20, count 0 2006.173.15:01:51.19#ibcon#about to read 6, iclass 20, count 0 2006.173.15:01:51.19#ibcon#read 6, iclass 20, count 0 2006.173.15:01:51.19#ibcon#end of sib2, iclass 20, count 0 2006.173.15:01:51.19#ibcon#*mode == 0, iclass 20, count 0 2006.173.15:01:51.19#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.15:01:51.19#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.15:01:51.19#ibcon#*before write, iclass 20, count 0 2006.173.15:01:51.19#ibcon#enter sib2, iclass 20, count 0 2006.173.15:01:51.19#ibcon#flushed, iclass 20, count 0 2006.173.15:01:51.19#ibcon#about to write, iclass 20, count 0 2006.173.15:01:51.19#ibcon#wrote, iclass 20, count 0 2006.173.15:01:51.19#ibcon#about to read 3, iclass 20, count 0 2006.173.15:01:51.23#ibcon#read 3, iclass 20, count 0 2006.173.15:01:51.23#ibcon#about to read 4, iclass 20, count 0 2006.173.15:01:51.23#ibcon#read 4, iclass 20, count 0 2006.173.15:01:51.23#ibcon#about to read 5, iclass 20, count 0 2006.173.15:01:51.23#ibcon#read 5, iclass 20, count 0 2006.173.15:01:51.23#ibcon#about to read 6, iclass 20, count 0 2006.173.15:01:51.23#ibcon#read 6, iclass 20, count 0 2006.173.15:01:51.23#ibcon#end of sib2, iclass 20, count 0 2006.173.15:01:51.23#ibcon#*after write, iclass 20, count 0 2006.173.15:01:51.23#ibcon#*before return 0, iclass 20, count 0 2006.173.15:01:51.23#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.15:01:51.23#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.15:01:51.23#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.15:01:51.23#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.15:01:51.23$vck44/va=7,4 2006.173.15:01:51.23#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.15:01:51.23#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.15:01:51.23#ibcon#ireg 11 cls_cnt 2 2006.173.15:01:51.23#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.15:01:51.29#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.15:01:51.29#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.15:01:51.29#ibcon#enter wrdev, iclass 22, count 2 2006.173.15:01:51.29#ibcon#first serial, iclass 22, count 2 2006.173.15:01:51.29#ibcon#enter sib2, iclass 22, count 2 2006.173.15:01:51.29#ibcon#flushed, iclass 22, count 2 2006.173.15:01:51.29#ibcon#about to write, iclass 22, count 2 2006.173.15:01:51.29#ibcon#wrote, iclass 22, count 2 2006.173.15:01:51.29#ibcon#about to read 3, iclass 22, count 2 2006.173.15:01:51.31#ibcon#read 3, iclass 22, count 2 2006.173.15:01:51.31#ibcon#about to read 4, iclass 22, count 2 2006.173.15:01:51.31#ibcon#read 4, iclass 22, count 2 2006.173.15:01:51.31#ibcon#about to read 5, iclass 22, count 2 2006.173.15:01:51.31#ibcon#read 5, iclass 22, count 2 2006.173.15:01:51.31#ibcon#about to read 6, iclass 22, count 2 2006.173.15:01:51.31#ibcon#read 6, iclass 22, count 2 2006.173.15:01:51.31#ibcon#end of sib2, iclass 22, count 2 2006.173.15:01:51.31#ibcon#*mode == 0, iclass 22, count 2 2006.173.15:01:51.31#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.15:01:51.31#ibcon#[25=AT07-04\r\n] 2006.173.15:01:51.31#ibcon#*before write, iclass 22, count 2 2006.173.15:01:51.31#ibcon#enter sib2, iclass 22, count 2 2006.173.15:01:51.31#ibcon#flushed, iclass 22, count 2 2006.173.15:01:51.31#ibcon#about to write, iclass 22, count 2 2006.173.15:01:51.31#ibcon#wrote, iclass 22, count 2 2006.173.15:01:51.31#ibcon#about to read 3, iclass 22, count 2 2006.173.15:01:51.34#ibcon#read 3, iclass 22, count 2 2006.173.15:01:51.34#ibcon#about to read 4, iclass 22, count 2 2006.173.15:01:51.34#ibcon#read 4, iclass 22, count 2 2006.173.15:01:51.34#ibcon#about to read 5, iclass 22, count 2 2006.173.15:01:51.34#ibcon#read 5, iclass 22, count 2 2006.173.15:01:51.34#ibcon#about to read 6, iclass 22, count 2 2006.173.15:01:51.34#ibcon#read 6, iclass 22, count 2 2006.173.15:01:51.34#ibcon#end of sib2, iclass 22, count 2 2006.173.15:01:51.34#ibcon#*after write, iclass 22, count 2 2006.173.15:01:51.34#ibcon#*before return 0, iclass 22, count 2 2006.173.15:01:51.34#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.15:01:51.34#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.15:01:51.34#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.15:01:51.34#ibcon#ireg 7 cls_cnt 0 2006.173.15:01:51.34#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.15:01:51.46#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.15:01:51.46#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.15:01:51.46#ibcon#enter wrdev, iclass 22, count 0 2006.173.15:01:51.46#ibcon#first serial, iclass 22, count 0 2006.173.15:01:51.46#ibcon#enter sib2, iclass 22, count 0 2006.173.15:01:51.46#ibcon#flushed, iclass 22, count 0 2006.173.15:01:51.46#ibcon#about to write, iclass 22, count 0 2006.173.15:01:51.46#ibcon#wrote, iclass 22, count 0 2006.173.15:01:51.46#ibcon#about to read 3, iclass 22, count 0 2006.173.15:01:51.48#ibcon#read 3, iclass 22, count 0 2006.173.15:01:51.48#ibcon#about to read 4, iclass 22, count 0 2006.173.15:01:51.48#ibcon#read 4, iclass 22, count 0 2006.173.15:01:51.48#ibcon#about to read 5, iclass 22, count 0 2006.173.15:01:51.48#ibcon#read 5, iclass 22, count 0 2006.173.15:01:51.48#ibcon#about to read 6, iclass 22, count 0 2006.173.15:01:51.48#ibcon#read 6, iclass 22, count 0 2006.173.15:01:51.48#ibcon#end of sib2, iclass 22, count 0 2006.173.15:01:51.48#ibcon#*mode == 0, iclass 22, count 0 2006.173.15:01:51.48#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.15:01:51.48#ibcon#[25=USB\r\n] 2006.173.15:01:51.48#ibcon#*before write, iclass 22, count 0 2006.173.15:01:51.48#ibcon#enter sib2, iclass 22, count 0 2006.173.15:01:51.48#ibcon#flushed, iclass 22, count 0 2006.173.15:01:51.48#ibcon#about to write, iclass 22, count 0 2006.173.15:01:51.48#ibcon#wrote, iclass 22, count 0 2006.173.15:01:51.48#ibcon#about to read 3, iclass 22, count 0 2006.173.15:01:51.51#ibcon#read 3, iclass 22, count 0 2006.173.15:01:51.51#ibcon#about to read 4, iclass 22, count 0 2006.173.15:01:51.51#ibcon#read 4, iclass 22, count 0 2006.173.15:01:51.51#ibcon#about to read 5, iclass 22, count 0 2006.173.15:01:51.51#ibcon#read 5, iclass 22, count 0 2006.173.15:01:51.51#ibcon#about to read 6, iclass 22, count 0 2006.173.15:01:51.51#ibcon#read 6, iclass 22, count 0 2006.173.15:01:51.51#ibcon#end of sib2, iclass 22, count 0 2006.173.15:01:51.51#ibcon#*after write, iclass 22, count 0 2006.173.15:01:51.51#ibcon#*before return 0, iclass 22, count 0 2006.173.15:01:51.51#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.15:01:51.51#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.15:01:51.51#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.15:01:51.51#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.15:01:51.51$vck44/valo=8,884.99 2006.173.15:01:51.51#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.15:01:51.51#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.15:01:51.51#ibcon#ireg 17 cls_cnt 0 2006.173.15:01:51.51#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.15:01:51.51#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.15:01:51.51#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.15:01:51.51#ibcon#enter wrdev, iclass 24, count 0 2006.173.15:01:51.51#ibcon#first serial, iclass 24, count 0 2006.173.15:01:51.51#ibcon#enter sib2, iclass 24, count 0 2006.173.15:01:51.51#ibcon#flushed, iclass 24, count 0 2006.173.15:01:51.51#ibcon#about to write, iclass 24, count 0 2006.173.15:01:51.51#ibcon#wrote, iclass 24, count 0 2006.173.15:01:51.51#ibcon#about to read 3, iclass 24, count 0 2006.173.15:01:51.53#ibcon#read 3, iclass 24, count 0 2006.173.15:01:51.53#ibcon#about to read 4, iclass 24, count 0 2006.173.15:01:51.53#ibcon#read 4, iclass 24, count 0 2006.173.15:01:51.53#ibcon#about to read 5, iclass 24, count 0 2006.173.15:01:51.53#ibcon#read 5, iclass 24, count 0 2006.173.15:01:51.53#ibcon#about to read 6, iclass 24, count 0 2006.173.15:01:51.53#ibcon#read 6, iclass 24, count 0 2006.173.15:01:51.53#ibcon#end of sib2, iclass 24, count 0 2006.173.15:01:51.53#ibcon#*mode == 0, iclass 24, count 0 2006.173.15:01:51.53#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.15:01:51.53#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.15:01:51.53#ibcon#*before write, iclass 24, count 0 2006.173.15:01:51.53#ibcon#enter sib2, iclass 24, count 0 2006.173.15:01:51.53#ibcon#flushed, iclass 24, count 0 2006.173.15:01:51.53#ibcon#about to write, iclass 24, count 0 2006.173.15:01:51.53#ibcon#wrote, iclass 24, count 0 2006.173.15:01:51.53#ibcon#about to read 3, iclass 24, count 0 2006.173.15:01:51.57#ibcon#read 3, iclass 24, count 0 2006.173.15:01:51.57#ibcon#about to read 4, iclass 24, count 0 2006.173.15:01:51.57#ibcon#read 4, iclass 24, count 0 2006.173.15:01:51.57#ibcon#about to read 5, iclass 24, count 0 2006.173.15:01:51.57#ibcon#read 5, iclass 24, count 0 2006.173.15:01:51.57#ibcon#about to read 6, iclass 24, count 0 2006.173.15:01:51.57#ibcon#read 6, iclass 24, count 0 2006.173.15:01:51.57#ibcon#end of sib2, iclass 24, count 0 2006.173.15:01:51.57#ibcon#*after write, iclass 24, count 0 2006.173.15:01:51.57#ibcon#*before return 0, iclass 24, count 0 2006.173.15:01:51.57#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.15:01:51.57#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.15:01:51.57#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.15:01:51.57#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.15:01:51.57$vck44/va=8,4 2006.173.15:01:51.57#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.15:01:51.57#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.15:01:51.57#ibcon#ireg 11 cls_cnt 2 2006.173.15:01:51.57#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.15:01:51.63#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.15:01:51.63#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.15:01:51.63#ibcon#enter wrdev, iclass 26, count 2 2006.173.15:01:51.63#ibcon#first serial, iclass 26, count 2 2006.173.15:01:51.63#ibcon#enter sib2, iclass 26, count 2 2006.173.15:01:51.63#ibcon#flushed, iclass 26, count 2 2006.173.15:01:51.63#ibcon#about to write, iclass 26, count 2 2006.173.15:01:51.63#ibcon#wrote, iclass 26, count 2 2006.173.15:01:51.63#ibcon#about to read 3, iclass 26, count 2 2006.173.15:01:51.65#ibcon#read 3, iclass 26, count 2 2006.173.15:01:51.65#ibcon#about to read 4, iclass 26, count 2 2006.173.15:01:51.65#ibcon#read 4, iclass 26, count 2 2006.173.15:01:51.65#ibcon#about to read 5, iclass 26, count 2 2006.173.15:01:51.65#ibcon#read 5, iclass 26, count 2 2006.173.15:01:51.65#ibcon#about to read 6, iclass 26, count 2 2006.173.15:01:51.65#ibcon#read 6, iclass 26, count 2 2006.173.15:01:51.65#ibcon#end of sib2, iclass 26, count 2 2006.173.15:01:51.65#ibcon#*mode == 0, iclass 26, count 2 2006.173.15:01:51.65#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.15:01:51.65#ibcon#[25=AT08-04\r\n] 2006.173.15:01:51.65#ibcon#*before write, iclass 26, count 2 2006.173.15:01:51.65#ibcon#enter sib2, iclass 26, count 2 2006.173.15:01:51.65#ibcon#flushed, iclass 26, count 2 2006.173.15:01:51.65#ibcon#about to write, iclass 26, count 2 2006.173.15:01:51.65#ibcon#wrote, iclass 26, count 2 2006.173.15:01:51.65#ibcon#about to read 3, iclass 26, count 2 2006.173.15:01:51.68#ibcon#read 3, iclass 26, count 2 2006.173.15:01:51.68#ibcon#about to read 4, iclass 26, count 2 2006.173.15:01:51.68#ibcon#read 4, iclass 26, count 2 2006.173.15:01:51.68#ibcon#about to read 5, iclass 26, count 2 2006.173.15:01:51.68#ibcon#read 5, iclass 26, count 2 2006.173.15:01:51.68#ibcon#about to read 6, iclass 26, count 2 2006.173.15:01:51.68#ibcon#read 6, iclass 26, count 2 2006.173.15:01:51.68#ibcon#end of sib2, iclass 26, count 2 2006.173.15:01:51.68#ibcon#*after write, iclass 26, count 2 2006.173.15:01:51.68#ibcon#*before return 0, iclass 26, count 2 2006.173.15:01:51.68#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.15:01:51.68#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.15:01:51.68#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.15:01:51.68#ibcon#ireg 7 cls_cnt 0 2006.173.15:01:51.68#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.15:01:51.80#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.15:01:51.80#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.15:01:51.80#ibcon#enter wrdev, iclass 26, count 0 2006.173.15:01:51.80#ibcon#first serial, iclass 26, count 0 2006.173.15:01:51.80#ibcon#enter sib2, iclass 26, count 0 2006.173.15:01:51.80#ibcon#flushed, iclass 26, count 0 2006.173.15:01:51.80#ibcon#about to write, iclass 26, count 0 2006.173.15:01:51.80#ibcon#wrote, iclass 26, count 0 2006.173.15:01:51.80#ibcon#about to read 3, iclass 26, count 0 2006.173.15:01:51.82#ibcon#read 3, iclass 26, count 0 2006.173.15:01:51.82#ibcon#about to read 4, iclass 26, count 0 2006.173.15:01:51.82#ibcon#read 4, iclass 26, count 0 2006.173.15:01:51.82#ibcon#about to read 5, iclass 26, count 0 2006.173.15:01:51.82#ibcon#read 5, iclass 26, count 0 2006.173.15:01:51.82#ibcon#about to read 6, iclass 26, count 0 2006.173.15:01:51.82#ibcon#read 6, iclass 26, count 0 2006.173.15:01:51.82#ibcon#end of sib2, iclass 26, count 0 2006.173.15:01:51.82#ibcon#*mode == 0, iclass 26, count 0 2006.173.15:01:51.82#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.15:01:51.82#ibcon#[25=USB\r\n] 2006.173.15:01:51.82#ibcon#*before write, iclass 26, count 0 2006.173.15:01:51.82#ibcon#enter sib2, iclass 26, count 0 2006.173.15:01:51.82#ibcon#flushed, iclass 26, count 0 2006.173.15:01:51.82#ibcon#about to write, iclass 26, count 0 2006.173.15:01:51.82#ibcon#wrote, iclass 26, count 0 2006.173.15:01:51.82#ibcon#about to read 3, iclass 26, count 0 2006.173.15:01:51.85#ibcon#read 3, iclass 26, count 0 2006.173.15:01:51.85#ibcon#about to read 4, iclass 26, count 0 2006.173.15:01:51.85#ibcon#read 4, iclass 26, count 0 2006.173.15:01:51.85#ibcon#about to read 5, iclass 26, count 0 2006.173.15:01:51.85#ibcon#read 5, iclass 26, count 0 2006.173.15:01:51.85#ibcon#about to read 6, iclass 26, count 0 2006.173.15:01:51.85#ibcon#read 6, iclass 26, count 0 2006.173.15:01:51.85#ibcon#end of sib2, iclass 26, count 0 2006.173.15:01:51.85#ibcon#*after write, iclass 26, count 0 2006.173.15:01:51.85#ibcon#*before return 0, iclass 26, count 0 2006.173.15:01:51.85#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.15:01:51.85#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.15:01:51.85#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.15:01:51.85#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.15:01:51.85$vck44/vblo=1,629.99 2006.173.15:01:51.85#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.15:01:51.85#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.15:01:51.85#ibcon#ireg 17 cls_cnt 0 2006.173.15:01:51.85#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.15:01:51.85#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.15:01:51.85#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.15:01:51.85#ibcon#enter wrdev, iclass 28, count 0 2006.173.15:01:51.85#ibcon#first serial, iclass 28, count 0 2006.173.15:01:51.85#ibcon#enter sib2, iclass 28, count 0 2006.173.15:01:51.85#ibcon#flushed, iclass 28, count 0 2006.173.15:01:51.85#ibcon#about to write, iclass 28, count 0 2006.173.15:01:51.85#ibcon#wrote, iclass 28, count 0 2006.173.15:01:51.85#ibcon#about to read 3, iclass 28, count 0 2006.173.15:01:51.87#ibcon#read 3, iclass 28, count 0 2006.173.15:01:51.87#ibcon#about to read 4, iclass 28, count 0 2006.173.15:01:51.87#ibcon#read 4, iclass 28, count 0 2006.173.15:01:51.87#ibcon#about to read 5, iclass 28, count 0 2006.173.15:01:51.87#ibcon#read 5, iclass 28, count 0 2006.173.15:01:51.87#ibcon#about to read 6, iclass 28, count 0 2006.173.15:01:51.87#ibcon#read 6, iclass 28, count 0 2006.173.15:01:51.87#ibcon#end of sib2, iclass 28, count 0 2006.173.15:01:51.87#ibcon#*mode == 0, iclass 28, count 0 2006.173.15:01:51.87#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.15:01:51.87#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.15:01:51.87#ibcon#*before write, iclass 28, count 0 2006.173.15:01:51.87#ibcon#enter sib2, iclass 28, count 0 2006.173.15:01:51.87#ibcon#flushed, iclass 28, count 0 2006.173.15:01:51.87#ibcon#about to write, iclass 28, count 0 2006.173.15:01:51.87#ibcon#wrote, iclass 28, count 0 2006.173.15:01:51.87#ibcon#about to read 3, iclass 28, count 0 2006.173.15:01:51.91#ibcon#read 3, iclass 28, count 0 2006.173.15:01:51.91#ibcon#about to read 4, iclass 28, count 0 2006.173.15:01:51.91#ibcon#read 4, iclass 28, count 0 2006.173.15:01:51.91#ibcon#about to read 5, iclass 28, count 0 2006.173.15:01:51.91#ibcon#read 5, iclass 28, count 0 2006.173.15:01:51.91#ibcon#about to read 6, iclass 28, count 0 2006.173.15:01:51.91#ibcon#read 6, iclass 28, count 0 2006.173.15:01:51.91#ibcon#end of sib2, iclass 28, count 0 2006.173.15:01:51.91#ibcon#*after write, iclass 28, count 0 2006.173.15:01:51.91#ibcon#*before return 0, iclass 28, count 0 2006.173.15:01:51.91#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.15:01:51.91#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.15:01:51.91#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.15:01:51.91#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.15:01:51.91$vck44/vb=1,4 2006.173.15:01:51.91#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.15:01:51.91#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.15:01:51.91#ibcon#ireg 11 cls_cnt 2 2006.173.15:01:51.91#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.15:01:51.91#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.15:01:51.91#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.15:01:51.91#ibcon#enter wrdev, iclass 30, count 2 2006.173.15:01:51.91#ibcon#first serial, iclass 30, count 2 2006.173.15:01:51.91#ibcon#enter sib2, iclass 30, count 2 2006.173.15:01:51.91#ibcon#flushed, iclass 30, count 2 2006.173.15:01:51.91#ibcon#about to write, iclass 30, count 2 2006.173.15:01:51.91#ibcon#wrote, iclass 30, count 2 2006.173.15:01:51.91#ibcon#about to read 3, iclass 30, count 2 2006.173.15:01:51.93#ibcon#read 3, iclass 30, count 2 2006.173.15:01:51.93#ibcon#about to read 4, iclass 30, count 2 2006.173.15:01:51.93#ibcon#read 4, iclass 30, count 2 2006.173.15:01:51.93#ibcon#about to read 5, iclass 30, count 2 2006.173.15:01:51.93#ibcon#read 5, iclass 30, count 2 2006.173.15:01:51.93#ibcon#about to read 6, iclass 30, count 2 2006.173.15:01:51.93#ibcon#read 6, iclass 30, count 2 2006.173.15:01:51.93#ibcon#end of sib2, iclass 30, count 2 2006.173.15:01:51.93#ibcon#*mode == 0, iclass 30, count 2 2006.173.15:01:51.93#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.15:01:51.93#ibcon#[27=AT01-04\r\n] 2006.173.15:01:51.93#ibcon#*before write, iclass 30, count 2 2006.173.15:01:51.93#ibcon#enter sib2, iclass 30, count 2 2006.173.15:01:51.93#ibcon#flushed, iclass 30, count 2 2006.173.15:01:51.93#ibcon#about to write, iclass 30, count 2 2006.173.15:01:51.93#ibcon#wrote, iclass 30, count 2 2006.173.15:01:51.93#ibcon#about to read 3, iclass 30, count 2 2006.173.15:01:51.96#ibcon#read 3, iclass 30, count 2 2006.173.15:01:51.96#ibcon#about to read 4, iclass 30, count 2 2006.173.15:01:51.96#ibcon#read 4, iclass 30, count 2 2006.173.15:01:51.96#ibcon#about to read 5, iclass 30, count 2 2006.173.15:01:51.96#ibcon#read 5, iclass 30, count 2 2006.173.15:01:51.96#ibcon#about to read 6, iclass 30, count 2 2006.173.15:01:51.96#ibcon#read 6, iclass 30, count 2 2006.173.15:01:51.96#ibcon#end of sib2, iclass 30, count 2 2006.173.15:01:51.96#ibcon#*after write, iclass 30, count 2 2006.173.15:01:51.96#ibcon#*before return 0, iclass 30, count 2 2006.173.15:01:51.96#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.15:01:51.96#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.15:01:51.96#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.15:01:51.96#ibcon#ireg 7 cls_cnt 0 2006.173.15:01:51.96#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.15:01:52.08#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.15:01:52.08#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.15:01:52.08#ibcon#enter wrdev, iclass 30, count 0 2006.173.15:01:52.08#ibcon#first serial, iclass 30, count 0 2006.173.15:01:52.08#ibcon#enter sib2, iclass 30, count 0 2006.173.15:01:52.08#ibcon#flushed, iclass 30, count 0 2006.173.15:01:52.08#ibcon#about to write, iclass 30, count 0 2006.173.15:01:52.08#ibcon#wrote, iclass 30, count 0 2006.173.15:01:52.08#ibcon#about to read 3, iclass 30, count 0 2006.173.15:01:52.10#ibcon#read 3, iclass 30, count 0 2006.173.15:01:52.10#ibcon#about to read 4, iclass 30, count 0 2006.173.15:01:52.10#ibcon#read 4, iclass 30, count 0 2006.173.15:01:52.10#ibcon#about to read 5, iclass 30, count 0 2006.173.15:01:52.10#ibcon#read 5, iclass 30, count 0 2006.173.15:01:52.10#ibcon#about to read 6, iclass 30, count 0 2006.173.15:01:52.10#ibcon#read 6, iclass 30, count 0 2006.173.15:01:52.10#ibcon#end of sib2, iclass 30, count 0 2006.173.15:01:52.10#ibcon#*mode == 0, iclass 30, count 0 2006.173.15:01:52.10#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.15:01:52.10#ibcon#[27=USB\r\n] 2006.173.15:01:52.10#ibcon#*before write, iclass 30, count 0 2006.173.15:01:52.10#ibcon#enter sib2, iclass 30, count 0 2006.173.15:01:52.10#ibcon#flushed, iclass 30, count 0 2006.173.15:01:52.10#ibcon#about to write, iclass 30, count 0 2006.173.15:01:52.10#ibcon#wrote, iclass 30, count 0 2006.173.15:01:52.10#ibcon#about to read 3, iclass 30, count 0 2006.173.15:01:52.13#ibcon#read 3, iclass 30, count 0 2006.173.15:01:52.13#ibcon#about to read 4, iclass 30, count 0 2006.173.15:01:52.13#ibcon#read 4, iclass 30, count 0 2006.173.15:01:52.13#ibcon#about to read 5, iclass 30, count 0 2006.173.15:01:52.13#ibcon#read 5, iclass 30, count 0 2006.173.15:01:52.13#ibcon#about to read 6, iclass 30, count 0 2006.173.15:01:52.13#ibcon#read 6, iclass 30, count 0 2006.173.15:01:52.13#ibcon#end of sib2, iclass 30, count 0 2006.173.15:01:52.13#ibcon#*after write, iclass 30, count 0 2006.173.15:01:52.13#ibcon#*before return 0, iclass 30, count 0 2006.173.15:01:52.13#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.15:01:52.13#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.15:01:52.13#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.15:01:52.13#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.15:01:52.13$vck44/vblo=2,634.99 2006.173.15:01:52.13#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.15:01:52.13#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.15:01:52.13#ibcon#ireg 17 cls_cnt 0 2006.173.15:01:52.13#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.15:01:52.13#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.15:01:52.13#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.15:01:52.13#ibcon#enter wrdev, iclass 32, count 0 2006.173.15:01:52.13#ibcon#first serial, iclass 32, count 0 2006.173.15:01:52.13#ibcon#enter sib2, iclass 32, count 0 2006.173.15:01:52.13#ibcon#flushed, iclass 32, count 0 2006.173.15:01:52.13#ibcon#about to write, iclass 32, count 0 2006.173.15:01:52.13#ibcon#wrote, iclass 32, count 0 2006.173.15:01:52.13#ibcon#about to read 3, iclass 32, count 0 2006.173.15:01:52.15#ibcon#read 3, iclass 32, count 0 2006.173.15:01:52.15#ibcon#about to read 4, iclass 32, count 0 2006.173.15:01:52.15#ibcon#read 4, iclass 32, count 0 2006.173.15:01:52.15#ibcon#about to read 5, iclass 32, count 0 2006.173.15:01:52.15#ibcon#read 5, iclass 32, count 0 2006.173.15:01:52.15#ibcon#about to read 6, iclass 32, count 0 2006.173.15:01:52.15#ibcon#read 6, iclass 32, count 0 2006.173.15:01:52.15#ibcon#end of sib2, iclass 32, count 0 2006.173.15:01:52.15#ibcon#*mode == 0, iclass 32, count 0 2006.173.15:01:52.15#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.15:01:52.15#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.15:01:52.15#ibcon#*before write, iclass 32, count 0 2006.173.15:01:52.15#ibcon#enter sib2, iclass 32, count 0 2006.173.15:01:52.15#ibcon#flushed, iclass 32, count 0 2006.173.15:01:52.15#ibcon#about to write, iclass 32, count 0 2006.173.15:01:52.15#ibcon#wrote, iclass 32, count 0 2006.173.15:01:52.15#ibcon#about to read 3, iclass 32, count 0 2006.173.15:01:52.19#ibcon#read 3, iclass 32, count 0 2006.173.15:01:52.19#ibcon#about to read 4, iclass 32, count 0 2006.173.15:01:52.19#ibcon#read 4, iclass 32, count 0 2006.173.15:01:52.19#ibcon#about to read 5, iclass 32, count 0 2006.173.15:01:52.19#ibcon#read 5, iclass 32, count 0 2006.173.15:01:52.19#ibcon#about to read 6, iclass 32, count 0 2006.173.15:01:52.19#ibcon#read 6, iclass 32, count 0 2006.173.15:01:52.19#ibcon#end of sib2, iclass 32, count 0 2006.173.15:01:52.19#ibcon#*after write, iclass 32, count 0 2006.173.15:01:52.19#ibcon#*before return 0, iclass 32, count 0 2006.173.15:01:52.19#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.15:01:52.19#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.15:01:52.19#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.15:01:52.19#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.15:01:52.19$vck44/vb=2,4 2006.173.15:01:52.19#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.15:01:52.19#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.15:01:52.19#ibcon#ireg 11 cls_cnt 2 2006.173.15:01:52.19#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.15:01:52.25#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.15:01:52.25#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.15:01:52.25#ibcon#enter wrdev, iclass 34, count 2 2006.173.15:01:52.25#ibcon#first serial, iclass 34, count 2 2006.173.15:01:52.25#ibcon#enter sib2, iclass 34, count 2 2006.173.15:01:52.25#ibcon#flushed, iclass 34, count 2 2006.173.15:01:52.25#ibcon#about to write, iclass 34, count 2 2006.173.15:01:52.25#ibcon#wrote, iclass 34, count 2 2006.173.15:01:52.25#ibcon#about to read 3, iclass 34, count 2 2006.173.15:01:52.27#ibcon#read 3, iclass 34, count 2 2006.173.15:01:52.27#ibcon#about to read 4, iclass 34, count 2 2006.173.15:01:52.27#ibcon#read 4, iclass 34, count 2 2006.173.15:01:52.27#ibcon#about to read 5, iclass 34, count 2 2006.173.15:01:52.27#ibcon#read 5, iclass 34, count 2 2006.173.15:01:52.27#ibcon#about to read 6, iclass 34, count 2 2006.173.15:01:52.27#ibcon#read 6, iclass 34, count 2 2006.173.15:01:52.27#ibcon#end of sib2, iclass 34, count 2 2006.173.15:01:52.27#ibcon#*mode == 0, iclass 34, count 2 2006.173.15:01:52.27#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.15:01:52.27#ibcon#[27=AT02-04\r\n] 2006.173.15:01:52.27#ibcon#*before write, iclass 34, count 2 2006.173.15:01:52.27#ibcon#enter sib2, iclass 34, count 2 2006.173.15:01:52.27#ibcon#flushed, iclass 34, count 2 2006.173.15:01:52.27#ibcon#about to write, iclass 34, count 2 2006.173.15:01:52.27#ibcon#wrote, iclass 34, count 2 2006.173.15:01:52.27#ibcon#about to read 3, iclass 34, count 2 2006.173.15:01:52.30#ibcon#read 3, iclass 34, count 2 2006.173.15:01:52.30#ibcon#about to read 4, iclass 34, count 2 2006.173.15:01:52.30#ibcon#read 4, iclass 34, count 2 2006.173.15:01:52.30#ibcon#about to read 5, iclass 34, count 2 2006.173.15:01:52.30#ibcon#read 5, iclass 34, count 2 2006.173.15:01:52.30#ibcon#about to read 6, iclass 34, count 2 2006.173.15:01:52.30#ibcon#read 6, iclass 34, count 2 2006.173.15:01:52.30#ibcon#end of sib2, iclass 34, count 2 2006.173.15:01:52.30#ibcon#*after write, iclass 34, count 2 2006.173.15:01:52.30#ibcon#*before return 0, iclass 34, count 2 2006.173.15:01:52.30#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.15:01:52.30#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.15:01:52.30#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.15:01:52.30#ibcon#ireg 7 cls_cnt 0 2006.173.15:01:52.30#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.15:01:52.42#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.15:01:52.42#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.15:01:52.42#ibcon#enter wrdev, iclass 34, count 0 2006.173.15:01:52.42#ibcon#first serial, iclass 34, count 0 2006.173.15:01:52.42#ibcon#enter sib2, iclass 34, count 0 2006.173.15:01:52.42#ibcon#flushed, iclass 34, count 0 2006.173.15:01:52.42#ibcon#about to write, iclass 34, count 0 2006.173.15:01:52.42#ibcon#wrote, iclass 34, count 0 2006.173.15:01:52.42#ibcon#about to read 3, iclass 34, count 0 2006.173.15:01:52.44#ibcon#read 3, iclass 34, count 0 2006.173.15:01:52.44#ibcon#about to read 4, iclass 34, count 0 2006.173.15:01:52.44#ibcon#read 4, iclass 34, count 0 2006.173.15:01:52.44#ibcon#about to read 5, iclass 34, count 0 2006.173.15:01:52.44#ibcon#read 5, iclass 34, count 0 2006.173.15:01:52.44#ibcon#about to read 6, iclass 34, count 0 2006.173.15:01:52.44#ibcon#read 6, iclass 34, count 0 2006.173.15:01:52.44#ibcon#end of sib2, iclass 34, count 0 2006.173.15:01:52.44#ibcon#*mode == 0, iclass 34, count 0 2006.173.15:01:52.44#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.15:01:52.44#ibcon#[27=USB\r\n] 2006.173.15:01:52.44#ibcon#*before write, iclass 34, count 0 2006.173.15:01:52.44#ibcon#enter sib2, iclass 34, count 0 2006.173.15:01:52.44#ibcon#flushed, iclass 34, count 0 2006.173.15:01:52.44#ibcon#about to write, iclass 34, count 0 2006.173.15:01:52.44#ibcon#wrote, iclass 34, count 0 2006.173.15:01:52.44#ibcon#about to read 3, iclass 34, count 0 2006.173.15:01:52.47#ibcon#read 3, iclass 34, count 0 2006.173.15:01:52.47#ibcon#about to read 4, iclass 34, count 0 2006.173.15:01:52.47#ibcon#read 4, iclass 34, count 0 2006.173.15:01:52.47#ibcon#about to read 5, iclass 34, count 0 2006.173.15:01:52.47#ibcon#read 5, iclass 34, count 0 2006.173.15:01:52.47#ibcon#about to read 6, iclass 34, count 0 2006.173.15:01:52.47#ibcon#read 6, iclass 34, count 0 2006.173.15:01:52.47#ibcon#end of sib2, iclass 34, count 0 2006.173.15:01:52.47#ibcon#*after write, iclass 34, count 0 2006.173.15:01:52.47#ibcon#*before return 0, iclass 34, count 0 2006.173.15:01:52.47#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.15:01:52.47#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.15:01:52.47#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.15:01:52.47#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.15:01:52.47$vck44/vblo=3,649.99 2006.173.15:01:52.47#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.15:01:52.47#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.15:01:52.47#ibcon#ireg 17 cls_cnt 0 2006.173.15:01:52.47#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.15:01:52.47#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.15:01:52.47#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.15:01:52.47#ibcon#enter wrdev, iclass 36, count 0 2006.173.15:01:52.47#ibcon#first serial, iclass 36, count 0 2006.173.15:01:52.47#ibcon#enter sib2, iclass 36, count 0 2006.173.15:01:52.47#ibcon#flushed, iclass 36, count 0 2006.173.15:01:52.47#ibcon#about to write, iclass 36, count 0 2006.173.15:01:52.47#ibcon#wrote, iclass 36, count 0 2006.173.15:01:52.47#ibcon#about to read 3, iclass 36, count 0 2006.173.15:01:52.49#ibcon#read 3, iclass 36, count 0 2006.173.15:01:52.49#ibcon#about to read 4, iclass 36, count 0 2006.173.15:01:52.49#ibcon#read 4, iclass 36, count 0 2006.173.15:01:52.49#ibcon#about to read 5, iclass 36, count 0 2006.173.15:01:52.49#ibcon#read 5, iclass 36, count 0 2006.173.15:01:52.49#ibcon#about to read 6, iclass 36, count 0 2006.173.15:01:52.49#ibcon#read 6, iclass 36, count 0 2006.173.15:01:52.49#ibcon#end of sib2, iclass 36, count 0 2006.173.15:01:52.49#ibcon#*mode == 0, iclass 36, count 0 2006.173.15:01:52.49#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.15:01:52.49#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.15:01:52.49#ibcon#*before write, iclass 36, count 0 2006.173.15:01:52.49#ibcon#enter sib2, iclass 36, count 0 2006.173.15:01:52.49#ibcon#flushed, iclass 36, count 0 2006.173.15:01:52.49#ibcon#about to write, iclass 36, count 0 2006.173.15:01:52.49#ibcon#wrote, iclass 36, count 0 2006.173.15:01:52.49#ibcon#about to read 3, iclass 36, count 0 2006.173.15:01:52.53#ibcon#read 3, iclass 36, count 0 2006.173.15:01:52.53#ibcon#about to read 4, iclass 36, count 0 2006.173.15:01:52.53#ibcon#read 4, iclass 36, count 0 2006.173.15:01:52.53#ibcon#about to read 5, iclass 36, count 0 2006.173.15:01:52.53#ibcon#read 5, iclass 36, count 0 2006.173.15:01:52.53#ibcon#about to read 6, iclass 36, count 0 2006.173.15:01:52.53#ibcon#read 6, iclass 36, count 0 2006.173.15:01:52.53#ibcon#end of sib2, iclass 36, count 0 2006.173.15:01:52.53#ibcon#*after write, iclass 36, count 0 2006.173.15:01:52.53#ibcon#*before return 0, iclass 36, count 0 2006.173.15:01:52.53#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.15:01:52.53#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.15:01:52.53#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.15:01:52.53#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.15:01:52.53$vck44/vb=3,4 2006.173.15:01:52.53#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.15:01:52.53#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.15:01:52.53#ibcon#ireg 11 cls_cnt 2 2006.173.15:01:52.53#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.15:01:52.59#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.15:01:52.59#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.15:01:52.59#ibcon#enter wrdev, iclass 38, count 2 2006.173.15:01:52.59#ibcon#first serial, iclass 38, count 2 2006.173.15:01:52.59#ibcon#enter sib2, iclass 38, count 2 2006.173.15:01:52.59#ibcon#flushed, iclass 38, count 2 2006.173.15:01:52.59#ibcon#about to write, iclass 38, count 2 2006.173.15:01:52.59#ibcon#wrote, iclass 38, count 2 2006.173.15:01:52.59#ibcon#about to read 3, iclass 38, count 2 2006.173.15:01:52.61#ibcon#read 3, iclass 38, count 2 2006.173.15:01:52.61#ibcon#about to read 4, iclass 38, count 2 2006.173.15:01:52.61#ibcon#read 4, iclass 38, count 2 2006.173.15:01:52.61#ibcon#about to read 5, iclass 38, count 2 2006.173.15:01:52.61#ibcon#read 5, iclass 38, count 2 2006.173.15:01:52.61#ibcon#about to read 6, iclass 38, count 2 2006.173.15:01:52.61#ibcon#read 6, iclass 38, count 2 2006.173.15:01:52.61#ibcon#end of sib2, iclass 38, count 2 2006.173.15:01:52.61#ibcon#*mode == 0, iclass 38, count 2 2006.173.15:01:52.61#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.15:01:52.61#ibcon#[27=AT03-04\r\n] 2006.173.15:01:52.61#ibcon#*before write, iclass 38, count 2 2006.173.15:01:52.61#ibcon#enter sib2, iclass 38, count 2 2006.173.15:01:52.61#ibcon#flushed, iclass 38, count 2 2006.173.15:01:52.61#ibcon#about to write, iclass 38, count 2 2006.173.15:01:52.61#ibcon#wrote, iclass 38, count 2 2006.173.15:01:52.61#ibcon#about to read 3, iclass 38, count 2 2006.173.15:01:52.64#ibcon#read 3, iclass 38, count 2 2006.173.15:01:52.64#ibcon#about to read 4, iclass 38, count 2 2006.173.15:01:52.64#ibcon#read 4, iclass 38, count 2 2006.173.15:01:52.64#ibcon#about to read 5, iclass 38, count 2 2006.173.15:01:52.64#ibcon#read 5, iclass 38, count 2 2006.173.15:01:52.64#ibcon#about to read 6, iclass 38, count 2 2006.173.15:01:52.64#ibcon#read 6, iclass 38, count 2 2006.173.15:01:52.64#ibcon#end of sib2, iclass 38, count 2 2006.173.15:01:52.64#ibcon#*after write, iclass 38, count 2 2006.173.15:01:52.64#ibcon#*before return 0, iclass 38, count 2 2006.173.15:01:52.64#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.15:01:52.64#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.15:01:52.64#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.15:01:52.64#ibcon#ireg 7 cls_cnt 0 2006.173.15:01:52.64#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.15:01:52.76#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.15:01:52.76#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.15:01:52.76#ibcon#enter wrdev, iclass 38, count 0 2006.173.15:01:52.76#ibcon#first serial, iclass 38, count 0 2006.173.15:01:52.76#ibcon#enter sib2, iclass 38, count 0 2006.173.15:01:52.76#ibcon#flushed, iclass 38, count 0 2006.173.15:01:52.76#ibcon#about to write, iclass 38, count 0 2006.173.15:01:52.76#ibcon#wrote, iclass 38, count 0 2006.173.15:01:52.76#ibcon#about to read 3, iclass 38, count 0 2006.173.15:01:52.78#ibcon#read 3, iclass 38, count 0 2006.173.15:01:52.78#ibcon#about to read 4, iclass 38, count 0 2006.173.15:01:52.78#ibcon#read 4, iclass 38, count 0 2006.173.15:01:52.78#ibcon#about to read 5, iclass 38, count 0 2006.173.15:01:52.78#ibcon#read 5, iclass 38, count 0 2006.173.15:01:52.78#ibcon#about to read 6, iclass 38, count 0 2006.173.15:01:52.78#ibcon#read 6, iclass 38, count 0 2006.173.15:01:52.78#ibcon#end of sib2, iclass 38, count 0 2006.173.15:01:52.78#ibcon#*mode == 0, iclass 38, count 0 2006.173.15:01:52.78#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.15:01:52.78#ibcon#[27=USB\r\n] 2006.173.15:01:52.78#ibcon#*before write, iclass 38, count 0 2006.173.15:01:52.78#ibcon#enter sib2, iclass 38, count 0 2006.173.15:01:52.78#ibcon#flushed, iclass 38, count 0 2006.173.15:01:52.78#ibcon#about to write, iclass 38, count 0 2006.173.15:01:52.78#ibcon#wrote, iclass 38, count 0 2006.173.15:01:52.78#ibcon#about to read 3, iclass 38, count 0 2006.173.15:01:52.81#ibcon#read 3, iclass 38, count 0 2006.173.15:01:52.81#ibcon#about to read 4, iclass 38, count 0 2006.173.15:01:52.81#ibcon#read 4, iclass 38, count 0 2006.173.15:01:52.81#ibcon#about to read 5, iclass 38, count 0 2006.173.15:01:52.81#ibcon#read 5, iclass 38, count 0 2006.173.15:01:52.81#ibcon#about to read 6, iclass 38, count 0 2006.173.15:01:52.81#ibcon#read 6, iclass 38, count 0 2006.173.15:01:52.81#ibcon#end of sib2, iclass 38, count 0 2006.173.15:01:52.81#ibcon#*after write, iclass 38, count 0 2006.173.15:01:52.81#ibcon#*before return 0, iclass 38, count 0 2006.173.15:01:52.81#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.15:01:52.81#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.15:01:52.81#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.15:01:52.81#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.15:01:52.81$vck44/vblo=4,679.99 2006.173.15:01:52.81#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.15:01:52.81#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.15:01:52.81#ibcon#ireg 17 cls_cnt 0 2006.173.15:01:52.81#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.15:01:52.81#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.15:01:52.81#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.15:01:52.81#ibcon#enter wrdev, iclass 40, count 0 2006.173.15:01:52.81#ibcon#first serial, iclass 40, count 0 2006.173.15:01:52.81#ibcon#enter sib2, iclass 40, count 0 2006.173.15:01:52.81#ibcon#flushed, iclass 40, count 0 2006.173.15:01:52.81#ibcon#about to write, iclass 40, count 0 2006.173.15:01:52.81#ibcon#wrote, iclass 40, count 0 2006.173.15:01:52.81#ibcon#about to read 3, iclass 40, count 0 2006.173.15:01:52.83#ibcon#read 3, iclass 40, count 0 2006.173.15:01:52.83#ibcon#about to read 4, iclass 40, count 0 2006.173.15:01:52.83#ibcon#read 4, iclass 40, count 0 2006.173.15:01:52.83#ibcon#about to read 5, iclass 40, count 0 2006.173.15:01:52.83#ibcon#read 5, iclass 40, count 0 2006.173.15:01:52.83#ibcon#about to read 6, iclass 40, count 0 2006.173.15:01:52.83#ibcon#read 6, iclass 40, count 0 2006.173.15:01:52.83#ibcon#end of sib2, iclass 40, count 0 2006.173.15:01:52.83#ibcon#*mode == 0, iclass 40, count 0 2006.173.15:01:52.83#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.15:01:52.83#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.15:01:52.83#ibcon#*before write, iclass 40, count 0 2006.173.15:01:52.83#ibcon#enter sib2, iclass 40, count 0 2006.173.15:01:52.83#ibcon#flushed, iclass 40, count 0 2006.173.15:01:52.83#ibcon#about to write, iclass 40, count 0 2006.173.15:01:52.83#ibcon#wrote, iclass 40, count 0 2006.173.15:01:52.83#ibcon#about to read 3, iclass 40, count 0 2006.173.15:01:52.87#ibcon#read 3, iclass 40, count 0 2006.173.15:01:52.87#ibcon#about to read 4, iclass 40, count 0 2006.173.15:01:52.87#ibcon#read 4, iclass 40, count 0 2006.173.15:01:52.87#ibcon#about to read 5, iclass 40, count 0 2006.173.15:01:52.87#ibcon#read 5, iclass 40, count 0 2006.173.15:01:52.87#ibcon#about to read 6, iclass 40, count 0 2006.173.15:01:52.87#ibcon#read 6, iclass 40, count 0 2006.173.15:01:52.87#ibcon#end of sib2, iclass 40, count 0 2006.173.15:01:52.87#ibcon#*after write, iclass 40, count 0 2006.173.15:01:52.87#ibcon#*before return 0, iclass 40, count 0 2006.173.15:01:52.87#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.15:01:52.87#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.15:01:52.87#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.15:01:52.87#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.15:01:52.87$vck44/vb=4,4 2006.173.15:01:52.87#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.15:01:52.87#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.15:01:52.87#ibcon#ireg 11 cls_cnt 2 2006.173.15:01:52.87#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.15:01:52.93#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.15:01:52.93#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.15:01:52.93#ibcon#enter wrdev, iclass 4, count 2 2006.173.15:01:52.93#ibcon#first serial, iclass 4, count 2 2006.173.15:01:52.93#ibcon#enter sib2, iclass 4, count 2 2006.173.15:01:52.93#ibcon#flushed, iclass 4, count 2 2006.173.15:01:52.93#ibcon#about to write, iclass 4, count 2 2006.173.15:01:52.93#ibcon#wrote, iclass 4, count 2 2006.173.15:01:52.93#ibcon#about to read 3, iclass 4, count 2 2006.173.15:01:52.95#ibcon#read 3, iclass 4, count 2 2006.173.15:01:52.95#ibcon#about to read 4, iclass 4, count 2 2006.173.15:01:52.95#ibcon#read 4, iclass 4, count 2 2006.173.15:01:52.95#ibcon#about to read 5, iclass 4, count 2 2006.173.15:01:52.95#ibcon#read 5, iclass 4, count 2 2006.173.15:01:52.95#ibcon#about to read 6, iclass 4, count 2 2006.173.15:01:52.95#ibcon#read 6, iclass 4, count 2 2006.173.15:01:52.95#ibcon#end of sib2, iclass 4, count 2 2006.173.15:01:52.95#ibcon#*mode == 0, iclass 4, count 2 2006.173.15:01:52.95#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.15:01:52.95#ibcon#[27=AT04-04\r\n] 2006.173.15:01:52.95#ibcon#*before write, iclass 4, count 2 2006.173.15:01:52.95#ibcon#enter sib2, iclass 4, count 2 2006.173.15:01:52.95#ibcon#flushed, iclass 4, count 2 2006.173.15:01:52.95#ibcon#about to write, iclass 4, count 2 2006.173.15:01:52.95#ibcon#wrote, iclass 4, count 2 2006.173.15:01:52.95#ibcon#about to read 3, iclass 4, count 2 2006.173.15:01:52.98#ibcon#read 3, iclass 4, count 2 2006.173.15:01:52.98#ibcon#about to read 4, iclass 4, count 2 2006.173.15:01:52.98#ibcon#read 4, iclass 4, count 2 2006.173.15:01:52.98#ibcon#about to read 5, iclass 4, count 2 2006.173.15:01:52.98#ibcon#read 5, iclass 4, count 2 2006.173.15:01:52.98#ibcon#about to read 6, iclass 4, count 2 2006.173.15:01:52.98#ibcon#read 6, iclass 4, count 2 2006.173.15:01:52.98#ibcon#end of sib2, iclass 4, count 2 2006.173.15:01:52.98#ibcon#*after write, iclass 4, count 2 2006.173.15:01:52.98#ibcon#*before return 0, iclass 4, count 2 2006.173.15:01:52.98#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.15:01:52.98#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.15:01:52.98#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.15:01:52.98#ibcon#ireg 7 cls_cnt 0 2006.173.15:01:52.98#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.15:01:53.10#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.15:01:53.10#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.15:01:53.10#ibcon#enter wrdev, iclass 4, count 0 2006.173.15:01:53.10#ibcon#first serial, iclass 4, count 0 2006.173.15:01:53.10#ibcon#enter sib2, iclass 4, count 0 2006.173.15:01:53.10#ibcon#flushed, iclass 4, count 0 2006.173.15:01:53.10#ibcon#about to write, iclass 4, count 0 2006.173.15:01:53.10#ibcon#wrote, iclass 4, count 0 2006.173.15:01:53.10#ibcon#about to read 3, iclass 4, count 0 2006.173.15:01:53.12#ibcon#read 3, iclass 4, count 0 2006.173.15:01:53.12#ibcon#about to read 4, iclass 4, count 0 2006.173.15:01:53.12#ibcon#read 4, iclass 4, count 0 2006.173.15:01:53.12#ibcon#about to read 5, iclass 4, count 0 2006.173.15:01:53.12#ibcon#read 5, iclass 4, count 0 2006.173.15:01:53.12#ibcon#about to read 6, iclass 4, count 0 2006.173.15:01:53.12#ibcon#read 6, iclass 4, count 0 2006.173.15:01:53.12#ibcon#end of sib2, iclass 4, count 0 2006.173.15:01:53.12#ibcon#*mode == 0, iclass 4, count 0 2006.173.15:01:53.12#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.15:01:53.12#ibcon#[27=USB\r\n] 2006.173.15:01:53.12#ibcon#*before write, iclass 4, count 0 2006.173.15:01:53.12#ibcon#enter sib2, iclass 4, count 0 2006.173.15:01:53.12#ibcon#flushed, iclass 4, count 0 2006.173.15:01:53.12#ibcon#about to write, iclass 4, count 0 2006.173.15:01:53.12#ibcon#wrote, iclass 4, count 0 2006.173.15:01:53.12#ibcon#about to read 3, iclass 4, count 0 2006.173.15:01:53.15#ibcon#read 3, iclass 4, count 0 2006.173.15:01:53.15#ibcon#about to read 4, iclass 4, count 0 2006.173.15:01:53.15#ibcon#read 4, iclass 4, count 0 2006.173.15:01:53.15#ibcon#about to read 5, iclass 4, count 0 2006.173.15:01:53.15#ibcon#read 5, iclass 4, count 0 2006.173.15:01:53.15#ibcon#about to read 6, iclass 4, count 0 2006.173.15:01:53.15#ibcon#read 6, iclass 4, count 0 2006.173.15:01:53.15#ibcon#end of sib2, iclass 4, count 0 2006.173.15:01:53.15#ibcon#*after write, iclass 4, count 0 2006.173.15:01:53.15#ibcon#*before return 0, iclass 4, count 0 2006.173.15:01:53.15#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.15:01:53.15#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.15:01:53.15#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.15:01:53.15#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.15:01:53.15$vck44/vblo=5,709.99 2006.173.15:01:53.15#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.15:01:53.15#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.15:01:53.15#ibcon#ireg 17 cls_cnt 0 2006.173.15:01:53.15#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.15:01:53.15#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.15:01:53.15#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.15:01:53.15#ibcon#enter wrdev, iclass 6, count 0 2006.173.15:01:53.15#ibcon#first serial, iclass 6, count 0 2006.173.15:01:53.15#ibcon#enter sib2, iclass 6, count 0 2006.173.15:01:53.15#ibcon#flushed, iclass 6, count 0 2006.173.15:01:53.15#ibcon#about to write, iclass 6, count 0 2006.173.15:01:53.15#ibcon#wrote, iclass 6, count 0 2006.173.15:01:53.15#ibcon#about to read 3, iclass 6, count 0 2006.173.15:01:53.17#ibcon#read 3, iclass 6, count 0 2006.173.15:01:53.17#ibcon#about to read 4, iclass 6, count 0 2006.173.15:01:53.17#ibcon#read 4, iclass 6, count 0 2006.173.15:01:53.17#ibcon#about to read 5, iclass 6, count 0 2006.173.15:01:53.17#ibcon#read 5, iclass 6, count 0 2006.173.15:01:53.17#ibcon#about to read 6, iclass 6, count 0 2006.173.15:01:53.17#ibcon#read 6, iclass 6, count 0 2006.173.15:01:53.17#ibcon#end of sib2, iclass 6, count 0 2006.173.15:01:53.17#ibcon#*mode == 0, iclass 6, count 0 2006.173.15:01:53.17#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.15:01:53.17#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.15:01:53.17#ibcon#*before write, iclass 6, count 0 2006.173.15:01:53.17#ibcon#enter sib2, iclass 6, count 0 2006.173.15:01:53.17#ibcon#flushed, iclass 6, count 0 2006.173.15:01:53.17#ibcon#about to write, iclass 6, count 0 2006.173.15:01:53.17#ibcon#wrote, iclass 6, count 0 2006.173.15:01:53.17#ibcon#about to read 3, iclass 6, count 0 2006.173.15:01:53.21#ibcon#read 3, iclass 6, count 0 2006.173.15:01:53.21#ibcon#about to read 4, iclass 6, count 0 2006.173.15:01:53.21#ibcon#read 4, iclass 6, count 0 2006.173.15:01:53.21#ibcon#about to read 5, iclass 6, count 0 2006.173.15:01:53.21#ibcon#read 5, iclass 6, count 0 2006.173.15:01:53.21#ibcon#about to read 6, iclass 6, count 0 2006.173.15:01:53.21#ibcon#read 6, iclass 6, count 0 2006.173.15:01:53.21#ibcon#end of sib2, iclass 6, count 0 2006.173.15:01:53.21#ibcon#*after write, iclass 6, count 0 2006.173.15:01:53.21#ibcon#*before return 0, iclass 6, count 0 2006.173.15:01:53.21#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.15:01:53.21#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.15:01:53.21#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.15:01:53.21#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.15:01:53.21$vck44/vb=5,4 2006.173.15:01:53.21#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.15:01:53.21#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.15:01:53.21#ibcon#ireg 11 cls_cnt 2 2006.173.15:01:53.21#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.15:01:53.27#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.15:01:53.27#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.15:01:53.27#ibcon#enter wrdev, iclass 10, count 2 2006.173.15:01:53.27#ibcon#first serial, iclass 10, count 2 2006.173.15:01:53.27#ibcon#enter sib2, iclass 10, count 2 2006.173.15:01:53.27#ibcon#flushed, iclass 10, count 2 2006.173.15:01:53.27#ibcon#about to write, iclass 10, count 2 2006.173.15:01:53.27#ibcon#wrote, iclass 10, count 2 2006.173.15:01:53.27#ibcon#about to read 3, iclass 10, count 2 2006.173.15:01:53.29#ibcon#read 3, iclass 10, count 2 2006.173.15:01:53.29#ibcon#about to read 4, iclass 10, count 2 2006.173.15:01:53.29#ibcon#read 4, iclass 10, count 2 2006.173.15:01:53.29#ibcon#about to read 5, iclass 10, count 2 2006.173.15:01:53.29#ibcon#read 5, iclass 10, count 2 2006.173.15:01:53.29#ibcon#about to read 6, iclass 10, count 2 2006.173.15:01:53.29#ibcon#read 6, iclass 10, count 2 2006.173.15:01:53.29#ibcon#end of sib2, iclass 10, count 2 2006.173.15:01:53.29#ibcon#*mode == 0, iclass 10, count 2 2006.173.15:01:53.29#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.15:01:53.29#ibcon#[27=AT05-04\r\n] 2006.173.15:01:53.29#ibcon#*before write, iclass 10, count 2 2006.173.15:01:53.29#ibcon#enter sib2, iclass 10, count 2 2006.173.15:01:53.29#ibcon#flushed, iclass 10, count 2 2006.173.15:01:53.29#ibcon#about to write, iclass 10, count 2 2006.173.15:01:53.29#ibcon#wrote, iclass 10, count 2 2006.173.15:01:53.29#ibcon#about to read 3, iclass 10, count 2 2006.173.15:01:53.32#ibcon#read 3, iclass 10, count 2 2006.173.15:01:53.32#ibcon#about to read 4, iclass 10, count 2 2006.173.15:01:53.32#ibcon#read 4, iclass 10, count 2 2006.173.15:01:53.32#ibcon#about to read 5, iclass 10, count 2 2006.173.15:01:53.32#ibcon#read 5, iclass 10, count 2 2006.173.15:01:53.32#ibcon#about to read 6, iclass 10, count 2 2006.173.15:01:53.32#ibcon#read 6, iclass 10, count 2 2006.173.15:01:53.32#ibcon#end of sib2, iclass 10, count 2 2006.173.15:01:53.32#ibcon#*after write, iclass 10, count 2 2006.173.15:01:53.32#ibcon#*before return 0, iclass 10, count 2 2006.173.15:01:53.32#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.15:01:53.32#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.15:01:53.32#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.15:01:53.32#ibcon#ireg 7 cls_cnt 0 2006.173.15:01:53.32#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.15:01:53.44#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.15:01:53.44#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.15:01:53.44#ibcon#enter wrdev, iclass 10, count 0 2006.173.15:01:53.44#ibcon#first serial, iclass 10, count 0 2006.173.15:01:53.44#ibcon#enter sib2, iclass 10, count 0 2006.173.15:01:53.44#ibcon#flushed, iclass 10, count 0 2006.173.15:01:53.44#ibcon#about to write, iclass 10, count 0 2006.173.15:01:53.44#ibcon#wrote, iclass 10, count 0 2006.173.15:01:53.44#ibcon#about to read 3, iclass 10, count 0 2006.173.15:01:53.46#ibcon#read 3, iclass 10, count 0 2006.173.15:01:53.46#ibcon#about to read 4, iclass 10, count 0 2006.173.15:01:53.46#ibcon#read 4, iclass 10, count 0 2006.173.15:01:53.46#ibcon#about to read 5, iclass 10, count 0 2006.173.15:01:53.46#ibcon#read 5, iclass 10, count 0 2006.173.15:01:53.46#ibcon#about to read 6, iclass 10, count 0 2006.173.15:01:53.46#ibcon#read 6, iclass 10, count 0 2006.173.15:01:53.46#ibcon#end of sib2, iclass 10, count 0 2006.173.15:01:53.46#ibcon#*mode == 0, iclass 10, count 0 2006.173.15:01:53.46#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.15:01:53.46#ibcon#[27=USB\r\n] 2006.173.15:01:53.46#ibcon#*before write, iclass 10, count 0 2006.173.15:01:53.46#ibcon#enter sib2, iclass 10, count 0 2006.173.15:01:53.46#ibcon#flushed, iclass 10, count 0 2006.173.15:01:53.46#ibcon#about to write, iclass 10, count 0 2006.173.15:01:53.46#ibcon#wrote, iclass 10, count 0 2006.173.15:01:53.46#ibcon#about to read 3, iclass 10, count 0 2006.173.15:01:53.49#ibcon#read 3, iclass 10, count 0 2006.173.15:01:53.49#ibcon#about to read 4, iclass 10, count 0 2006.173.15:01:53.49#ibcon#read 4, iclass 10, count 0 2006.173.15:01:53.49#ibcon#about to read 5, iclass 10, count 0 2006.173.15:01:53.49#ibcon#read 5, iclass 10, count 0 2006.173.15:01:53.49#ibcon#about to read 6, iclass 10, count 0 2006.173.15:01:53.49#ibcon#read 6, iclass 10, count 0 2006.173.15:01:53.49#ibcon#end of sib2, iclass 10, count 0 2006.173.15:01:53.49#ibcon#*after write, iclass 10, count 0 2006.173.15:01:53.49#ibcon#*before return 0, iclass 10, count 0 2006.173.15:01:53.49#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.15:01:53.49#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.15:01:53.49#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.15:01:53.49#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.15:01:53.49$vck44/vblo=6,719.99 2006.173.15:01:53.49#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.15:01:53.49#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.15:01:53.49#ibcon#ireg 17 cls_cnt 0 2006.173.15:01:53.49#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.15:01:53.49#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.15:01:53.49#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.15:01:53.49#ibcon#enter wrdev, iclass 12, count 0 2006.173.15:01:53.49#ibcon#first serial, iclass 12, count 0 2006.173.15:01:53.49#ibcon#enter sib2, iclass 12, count 0 2006.173.15:01:53.49#ibcon#flushed, iclass 12, count 0 2006.173.15:01:53.49#ibcon#about to write, iclass 12, count 0 2006.173.15:01:53.49#ibcon#wrote, iclass 12, count 0 2006.173.15:01:53.49#ibcon#about to read 3, iclass 12, count 0 2006.173.15:01:53.51#ibcon#read 3, iclass 12, count 0 2006.173.15:01:53.51#ibcon#about to read 4, iclass 12, count 0 2006.173.15:01:53.51#ibcon#read 4, iclass 12, count 0 2006.173.15:01:53.51#ibcon#about to read 5, iclass 12, count 0 2006.173.15:01:53.51#ibcon#read 5, iclass 12, count 0 2006.173.15:01:53.51#ibcon#about to read 6, iclass 12, count 0 2006.173.15:01:53.51#ibcon#read 6, iclass 12, count 0 2006.173.15:01:53.51#ibcon#end of sib2, iclass 12, count 0 2006.173.15:01:53.51#ibcon#*mode == 0, iclass 12, count 0 2006.173.15:01:53.51#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.15:01:53.51#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.15:01:53.51#ibcon#*before write, iclass 12, count 0 2006.173.15:01:53.51#ibcon#enter sib2, iclass 12, count 0 2006.173.15:01:53.51#ibcon#flushed, iclass 12, count 0 2006.173.15:01:53.51#ibcon#about to write, iclass 12, count 0 2006.173.15:01:53.51#ibcon#wrote, iclass 12, count 0 2006.173.15:01:53.51#ibcon#about to read 3, iclass 12, count 0 2006.173.15:01:53.55#ibcon#read 3, iclass 12, count 0 2006.173.15:01:53.55#ibcon#about to read 4, iclass 12, count 0 2006.173.15:01:53.55#ibcon#read 4, iclass 12, count 0 2006.173.15:01:53.55#ibcon#about to read 5, iclass 12, count 0 2006.173.15:01:53.55#ibcon#read 5, iclass 12, count 0 2006.173.15:01:53.55#ibcon#about to read 6, iclass 12, count 0 2006.173.15:01:53.55#ibcon#read 6, iclass 12, count 0 2006.173.15:01:53.55#ibcon#end of sib2, iclass 12, count 0 2006.173.15:01:53.55#ibcon#*after write, iclass 12, count 0 2006.173.15:01:53.55#ibcon#*before return 0, iclass 12, count 0 2006.173.15:01:53.55#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.15:01:53.55#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.15:01:53.55#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.15:01:53.55#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.15:01:53.55$vck44/vb=6,4 2006.173.15:01:53.55#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.15:01:53.55#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.15:01:53.55#ibcon#ireg 11 cls_cnt 2 2006.173.15:01:53.55#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.15:01:53.61#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.15:01:53.61#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.15:01:53.61#ibcon#enter wrdev, iclass 14, count 2 2006.173.15:01:53.61#ibcon#first serial, iclass 14, count 2 2006.173.15:01:53.61#ibcon#enter sib2, iclass 14, count 2 2006.173.15:01:53.61#ibcon#flushed, iclass 14, count 2 2006.173.15:01:53.61#ibcon#about to write, iclass 14, count 2 2006.173.15:01:53.61#ibcon#wrote, iclass 14, count 2 2006.173.15:01:53.61#ibcon#about to read 3, iclass 14, count 2 2006.173.15:01:53.63#ibcon#read 3, iclass 14, count 2 2006.173.15:01:53.63#ibcon#about to read 4, iclass 14, count 2 2006.173.15:01:53.63#ibcon#read 4, iclass 14, count 2 2006.173.15:01:53.63#ibcon#about to read 5, iclass 14, count 2 2006.173.15:01:53.63#ibcon#read 5, iclass 14, count 2 2006.173.15:01:53.63#ibcon#about to read 6, iclass 14, count 2 2006.173.15:01:53.63#ibcon#read 6, iclass 14, count 2 2006.173.15:01:53.63#ibcon#end of sib2, iclass 14, count 2 2006.173.15:01:53.63#ibcon#*mode == 0, iclass 14, count 2 2006.173.15:01:53.63#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.15:01:53.63#ibcon#[27=AT06-04\r\n] 2006.173.15:01:53.63#ibcon#*before write, iclass 14, count 2 2006.173.15:01:53.63#ibcon#enter sib2, iclass 14, count 2 2006.173.15:01:53.63#ibcon#flushed, iclass 14, count 2 2006.173.15:01:53.63#ibcon#about to write, iclass 14, count 2 2006.173.15:01:53.63#ibcon#wrote, iclass 14, count 2 2006.173.15:01:53.63#ibcon#about to read 3, iclass 14, count 2 2006.173.15:01:53.66#ibcon#read 3, iclass 14, count 2 2006.173.15:01:53.66#ibcon#about to read 4, iclass 14, count 2 2006.173.15:01:53.66#ibcon#read 4, iclass 14, count 2 2006.173.15:01:53.66#ibcon#about to read 5, iclass 14, count 2 2006.173.15:01:53.66#ibcon#read 5, iclass 14, count 2 2006.173.15:01:53.66#ibcon#about to read 6, iclass 14, count 2 2006.173.15:01:53.66#ibcon#read 6, iclass 14, count 2 2006.173.15:01:53.66#ibcon#end of sib2, iclass 14, count 2 2006.173.15:01:53.66#ibcon#*after write, iclass 14, count 2 2006.173.15:01:53.66#ibcon#*before return 0, iclass 14, count 2 2006.173.15:01:53.66#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.15:01:53.66#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.15:01:53.66#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.15:01:53.66#ibcon#ireg 7 cls_cnt 0 2006.173.15:01:53.66#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.15:01:53.78#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.15:01:53.78#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.15:01:53.78#ibcon#enter wrdev, iclass 14, count 0 2006.173.15:01:53.78#ibcon#first serial, iclass 14, count 0 2006.173.15:01:53.78#ibcon#enter sib2, iclass 14, count 0 2006.173.15:01:53.78#ibcon#flushed, iclass 14, count 0 2006.173.15:01:53.78#ibcon#about to write, iclass 14, count 0 2006.173.15:01:53.78#ibcon#wrote, iclass 14, count 0 2006.173.15:01:53.78#ibcon#about to read 3, iclass 14, count 0 2006.173.15:01:53.80#ibcon#read 3, iclass 14, count 0 2006.173.15:01:53.80#ibcon#about to read 4, iclass 14, count 0 2006.173.15:01:53.80#ibcon#read 4, iclass 14, count 0 2006.173.15:01:53.80#ibcon#about to read 5, iclass 14, count 0 2006.173.15:01:53.80#ibcon#read 5, iclass 14, count 0 2006.173.15:01:53.80#ibcon#about to read 6, iclass 14, count 0 2006.173.15:01:53.80#ibcon#read 6, iclass 14, count 0 2006.173.15:01:53.80#ibcon#end of sib2, iclass 14, count 0 2006.173.15:01:53.80#ibcon#*mode == 0, iclass 14, count 0 2006.173.15:01:53.80#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.15:01:53.80#ibcon#[27=USB\r\n] 2006.173.15:01:53.80#ibcon#*before write, iclass 14, count 0 2006.173.15:01:53.80#ibcon#enter sib2, iclass 14, count 0 2006.173.15:01:53.80#ibcon#flushed, iclass 14, count 0 2006.173.15:01:53.80#ibcon#about to write, iclass 14, count 0 2006.173.15:01:53.80#ibcon#wrote, iclass 14, count 0 2006.173.15:01:53.80#ibcon#about to read 3, iclass 14, count 0 2006.173.15:01:53.83#ibcon#read 3, iclass 14, count 0 2006.173.15:01:53.83#ibcon#about to read 4, iclass 14, count 0 2006.173.15:01:53.83#ibcon#read 4, iclass 14, count 0 2006.173.15:01:53.83#ibcon#about to read 5, iclass 14, count 0 2006.173.15:01:53.83#ibcon#read 5, iclass 14, count 0 2006.173.15:01:53.83#ibcon#about to read 6, iclass 14, count 0 2006.173.15:01:53.83#ibcon#read 6, iclass 14, count 0 2006.173.15:01:53.83#ibcon#end of sib2, iclass 14, count 0 2006.173.15:01:53.83#ibcon#*after write, iclass 14, count 0 2006.173.15:01:53.83#ibcon#*before return 0, iclass 14, count 0 2006.173.15:01:53.83#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.15:01:53.83#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.15:01:53.83#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.15:01:53.83#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.15:01:53.83$vck44/vblo=7,734.99 2006.173.15:01:53.83#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.15:01:53.83#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.15:01:53.83#ibcon#ireg 17 cls_cnt 0 2006.173.15:01:53.83#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.15:01:53.83#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.15:01:53.83#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.15:01:53.83#ibcon#enter wrdev, iclass 16, count 0 2006.173.15:01:53.83#ibcon#first serial, iclass 16, count 0 2006.173.15:01:53.83#ibcon#enter sib2, iclass 16, count 0 2006.173.15:01:53.83#ibcon#flushed, iclass 16, count 0 2006.173.15:01:53.83#ibcon#about to write, iclass 16, count 0 2006.173.15:01:53.83#ibcon#wrote, iclass 16, count 0 2006.173.15:01:53.83#ibcon#about to read 3, iclass 16, count 0 2006.173.15:01:53.85#ibcon#read 3, iclass 16, count 0 2006.173.15:01:53.85#ibcon#about to read 4, iclass 16, count 0 2006.173.15:01:53.85#ibcon#read 4, iclass 16, count 0 2006.173.15:01:53.85#ibcon#about to read 5, iclass 16, count 0 2006.173.15:01:53.85#ibcon#read 5, iclass 16, count 0 2006.173.15:01:53.85#ibcon#about to read 6, iclass 16, count 0 2006.173.15:01:53.85#ibcon#read 6, iclass 16, count 0 2006.173.15:01:53.85#ibcon#end of sib2, iclass 16, count 0 2006.173.15:01:53.85#ibcon#*mode == 0, iclass 16, count 0 2006.173.15:01:53.85#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.15:01:53.85#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.15:01:53.85#ibcon#*before write, iclass 16, count 0 2006.173.15:01:53.85#ibcon#enter sib2, iclass 16, count 0 2006.173.15:01:53.85#ibcon#flushed, iclass 16, count 0 2006.173.15:01:53.85#ibcon#about to write, iclass 16, count 0 2006.173.15:01:53.85#ibcon#wrote, iclass 16, count 0 2006.173.15:01:53.85#ibcon#about to read 3, iclass 16, count 0 2006.173.15:01:53.89#ibcon#read 3, iclass 16, count 0 2006.173.15:01:53.89#ibcon#about to read 4, iclass 16, count 0 2006.173.15:01:53.89#ibcon#read 4, iclass 16, count 0 2006.173.15:01:53.89#ibcon#about to read 5, iclass 16, count 0 2006.173.15:01:53.89#ibcon#read 5, iclass 16, count 0 2006.173.15:01:53.89#ibcon#about to read 6, iclass 16, count 0 2006.173.15:01:53.89#ibcon#read 6, iclass 16, count 0 2006.173.15:01:53.89#ibcon#end of sib2, iclass 16, count 0 2006.173.15:01:53.89#ibcon#*after write, iclass 16, count 0 2006.173.15:01:53.89#ibcon#*before return 0, iclass 16, count 0 2006.173.15:01:53.89#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.15:01:53.89#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.15:01:53.89#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.15:01:53.89#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.15:01:53.89$vck44/vb=7,4 2006.173.15:01:53.89#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.15:01:53.89#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.15:01:53.89#ibcon#ireg 11 cls_cnt 2 2006.173.15:01:53.89#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.15:01:53.95#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.15:01:53.95#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.15:01:53.95#ibcon#enter wrdev, iclass 18, count 2 2006.173.15:01:53.95#ibcon#first serial, iclass 18, count 2 2006.173.15:01:53.95#ibcon#enter sib2, iclass 18, count 2 2006.173.15:01:53.95#ibcon#flushed, iclass 18, count 2 2006.173.15:01:53.95#ibcon#about to write, iclass 18, count 2 2006.173.15:01:53.95#ibcon#wrote, iclass 18, count 2 2006.173.15:01:53.95#ibcon#about to read 3, iclass 18, count 2 2006.173.15:01:53.97#ibcon#read 3, iclass 18, count 2 2006.173.15:01:53.97#ibcon#about to read 4, iclass 18, count 2 2006.173.15:01:53.97#ibcon#read 4, iclass 18, count 2 2006.173.15:01:53.97#ibcon#about to read 5, iclass 18, count 2 2006.173.15:01:53.97#ibcon#read 5, iclass 18, count 2 2006.173.15:01:53.97#ibcon#about to read 6, iclass 18, count 2 2006.173.15:01:53.97#ibcon#read 6, iclass 18, count 2 2006.173.15:01:53.97#ibcon#end of sib2, iclass 18, count 2 2006.173.15:01:53.97#ibcon#*mode == 0, iclass 18, count 2 2006.173.15:01:53.97#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.15:01:53.97#ibcon#[27=AT07-04\r\n] 2006.173.15:01:53.97#ibcon#*before write, iclass 18, count 2 2006.173.15:01:53.97#ibcon#enter sib2, iclass 18, count 2 2006.173.15:01:53.97#ibcon#flushed, iclass 18, count 2 2006.173.15:01:53.97#ibcon#about to write, iclass 18, count 2 2006.173.15:01:53.97#ibcon#wrote, iclass 18, count 2 2006.173.15:01:53.97#ibcon#about to read 3, iclass 18, count 2 2006.173.15:01:54.00#ibcon#read 3, iclass 18, count 2 2006.173.15:01:54.00#ibcon#about to read 4, iclass 18, count 2 2006.173.15:01:54.00#ibcon#read 4, iclass 18, count 2 2006.173.15:01:54.00#ibcon#about to read 5, iclass 18, count 2 2006.173.15:01:54.00#ibcon#read 5, iclass 18, count 2 2006.173.15:01:54.00#ibcon#about to read 6, iclass 18, count 2 2006.173.15:01:54.00#ibcon#read 6, iclass 18, count 2 2006.173.15:01:54.00#ibcon#end of sib2, iclass 18, count 2 2006.173.15:01:54.00#ibcon#*after write, iclass 18, count 2 2006.173.15:01:54.00#ibcon#*before return 0, iclass 18, count 2 2006.173.15:01:54.00#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.15:01:54.00#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.15:01:54.00#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.15:01:54.00#ibcon#ireg 7 cls_cnt 0 2006.173.15:01:54.00#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.15:01:54.12#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.15:01:54.12#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.15:01:54.12#ibcon#enter wrdev, iclass 18, count 0 2006.173.15:01:54.12#ibcon#first serial, iclass 18, count 0 2006.173.15:01:54.12#ibcon#enter sib2, iclass 18, count 0 2006.173.15:01:54.12#ibcon#flushed, iclass 18, count 0 2006.173.15:01:54.12#ibcon#about to write, iclass 18, count 0 2006.173.15:01:54.12#ibcon#wrote, iclass 18, count 0 2006.173.15:01:54.12#ibcon#about to read 3, iclass 18, count 0 2006.173.15:01:54.14#ibcon#read 3, iclass 18, count 0 2006.173.15:01:54.14#ibcon#about to read 4, iclass 18, count 0 2006.173.15:01:54.14#ibcon#read 4, iclass 18, count 0 2006.173.15:01:54.14#ibcon#about to read 5, iclass 18, count 0 2006.173.15:01:54.14#ibcon#read 5, iclass 18, count 0 2006.173.15:01:54.14#ibcon#about to read 6, iclass 18, count 0 2006.173.15:01:54.14#ibcon#read 6, iclass 18, count 0 2006.173.15:01:54.14#ibcon#end of sib2, iclass 18, count 0 2006.173.15:01:54.14#ibcon#*mode == 0, iclass 18, count 0 2006.173.15:01:54.14#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.15:01:54.14#ibcon#[27=USB\r\n] 2006.173.15:01:54.14#ibcon#*before write, iclass 18, count 0 2006.173.15:01:54.14#ibcon#enter sib2, iclass 18, count 0 2006.173.15:01:54.14#ibcon#flushed, iclass 18, count 0 2006.173.15:01:54.14#ibcon#about to write, iclass 18, count 0 2006.173.15:01:54.14#ibcon#wrote, iclass 18, count 0 2006.173.15:01:54.14#ibcon#about to read 3, iclass 18, count 0 2006.173.15:01:54.17#ibcon#read 3, iclass 18, count 0 2006.173.15:01:54.17#ibcon#about to read 4, iclass 18, count 0 2006.173.15:01:54.17#ibcon#read 4, iclass 18, count 0 2006.173.15:01:54.17#ibcon#about to read 5, iclass 18, count 0 2006.173.15:01:54.17#ibcon#read 5, iclass 18, count 0 2006.173.15:01:54.17#ibcon#about to read 6, iclass 18, count 0 2006.173.15:01:54.17#ibcon#read 6, iclass 18, count 0 2006.173.15:01:54.17#ibcon#end of sib2, iclass 18, count 0 2006.173.15:01:54.17#ibcon#*after write, iclass 18, count 0 2006.173.15:01:54.17#ibcon#*before return 0, iclass 18, count 0 2006.173.15:01:54.17#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.15:01:54.17#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.15:01:54.17#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.15:01:54.17#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.15:01:54.17$vck44/vblo=8,744.99 2006.173.15:01:54.17#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.15:01:54.17#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.15:01:54.17#ibcon#ireg 17 cls_cnt 0 2006.173.15:01:54.17#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.15:01:54.17#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.15:01:54.17#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.15:01:54.17#ibcon#enter wrdev, iclass 20, count 0 2006.173.15:01:54.17#ibcon#first serial, iclass 20, count 0 2006.173.15:01:54.17#ibcon#enter sib2, iclass 20, count 0 2006.173.15:01:54.17#ibcon#flushed, iclass 20, count 0 2006.173.15:01:54.17#ibcon#about to write, iclass 20, count 0 2006.173.15:01:54.17#ibcon#wrote, iclass 20, count 0 2006.173.15:01:54.17#ibcon#about to read 3, iclass 20, count 0 2006.173.15:01:54.19#ibcon#read 3, iclass 20, count 0 2006.173.15:01:54.19#ibcon#about to read 4, iclass 20, count 0 2006.173.15:01:54.19#ibcon#read 4, iclass 20, count 0 2006.173.15:01:54.19#ibcon#about to read 5, iclass 20, count 0 2006.173.15:01:54.19#ibcon#read 5, iclass 20, count 0 2006.173.15:01:54.19#ibcon#about to read 6, iclass 20, count 0 2006.173.15:01:54.19#ibcon#read 6, iclass 20, count 0 2006.173.15:01:54.19#ibcon#end of sib2, iclass 20, count 0 2006.173.15:01:54.19#ibcon#*mode == 0, iclass 20, count 0 2006.173.15:01:54.19#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.15:01:54.19#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.15:01:54.19#ibcon#*before write, iclass 20, count 0 2006.173.15:01:54.19#ibcon#enter sib2, iclass 20, count 0 2006.173.15:01:54.19#ibcon#flushed, iclass 20, count 0 2006.173.15:01:54.19#ibcon#about to write, iclass 20, count 0 2006.173.15:01:54.19#ibcon#wrote, iclass 20, count 0 2006.173.15:01:54.19#ibcon#about to read 3, iclass 20, count 0 2006.173.15:01:54.23#ibcon#read 3, iclass 20, count 0 2006.173.15:01:54.23#ibcon#about to read 4, iclass 20, count 0 2006.173.15:01:54.23#ibcon#read 4, iclass 20, count 0 2006.173.15:01:54.23#ibcon#about to read 5, iclass 20, count 0 2006.173.15:01:54.23#ibcon#read 5, iclass 20, count 0 2006.173.15:01:54.23#ibcon#about to read 6, iclass 20, count 0 2006.173.15:01:54.23#ibcon#read 6, iclass 20, count 0 2006.173.15:01:54.23#ibcon#end of sib2, iclass 20, count 0 2006.173.15:01:54.23#ibcon#*after write, iclass 20, count 0 2006.173.15:01:54.23#ibcon#*before return 0, iclass 20, count 0 2006.173.15:01:54.23#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.15:01:54.23#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.15:01:54.23#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.15:01:54.23#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.15:01:54.23$vck44/vb=8,4 2006.173.15:01:54.23#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.15:01:54.23#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.15:01:54.23#ibcon#ireg 11 cls_cnt 2 2006.173.15:01:54.23#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.15:01:54.29#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.15:01:54.29#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.15:01:54.29#ibcon#enter wrdev, iclass 22, count 2 2006.173.15:01:54.29#ibcon#first serial, iclass 22, count 2 2006.173.15:01:54.29#ibcon#enter sib2, iclass 22, count 2 2006.173.15:01:54.29#ibcon#flushed, iclass 22, count 2 2006.173.15:01:54.29#ibcon#about to write, iclass 22, count 2 2006.173.15:01:54.29#ibcon#wrote, iclass 22, count 2 2006.173.15:01:54.29#ibcon#about to read 3, iclass 22, count 2 2006.173.15:01:54.31#ibcon#read 3, iclass 22, count 2 2006.173.15:01:54.31#ibcon#about to read 4, iclass 22, count 2 2006.173.15:01:54.31#ibcon#read 4, iclass 22, count 2 2006.173.15:01:54.31#ibcon#about to read 5, iclass 22, count 2 2006.173.15:01:54.31#ibcon#read 5, iclass 22, count 2 2006.173.15:01:54.31#ibcon#about to read 6, iclass 22, count 2 2006.173.15:01:54.31#ibcon#read 6, iclass 22, count 2 2006.173.15:01:54.31#ibcon#end of sib2, iclass 22, count 2 2006.173.15:01:54.31#ibcon#*mode == 0, iclass 22, count 2 2006.173.15:01:54.31#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.15:01:54.31#ibcon#[27=AT08-04\r\n] 2006.173.15:01:54.31#ibcon#*before write, iclass 22, count 2 2006.173.15:01:54.31#ibcon#enter sib2, iclass 22, count 2 2006.173.15:01:54.31#ibcon#flushed, iclass 22, count 2 2006.173.15:01:54.31#ibcon#about to write, iclass 22, count 2 2006.173.15:01:54.31#ibcon#wrote, iclass 22, count 2 2006.173.15:01:54.31#ibcon#about to read 3, iclass 22, count 2 2006.173.15:01:54.34#ibcon#read 3, iclass 22, count 2 2006.173.15:01:54.34#ibcon#about to read 4, iclass 22, count 2 2006.173.15:01:54.34#ibcon#read 4, iclass 22, count 2 2006.173.15:01:54.34#ibcon#about to read 5, iclass 22, count 2 2006.173.15:01:54.34#ibcon#read 5, iclass 22, count 2 2006.173.15:01:54.34#ibcon#about to read 6, iclass 22, count 2 2006.173.15:01:54.34#ibcon#read 6, iclass 22, count 2 2006.173.15:01:54.34#ibcon#end of sib2, iclass 22, count 2 2006.173.15:01:54.34#ibcon#*after write, iclass 22, count 2 2006.173.15:01:54.34#ibcon#*before return 0, iclass 22, count 2 2006.173.15:01:54.34#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.15:01:54.34#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.15:01:54.34#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.15:01:54.34#ibcon#ireg 7 cls_cnt 0 2006.173.15:01:54.34#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.15:01:54.46#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.15:01:54.46#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.15:01:54.46#ibcon#enter wrdev, iclass 22, count 0 2006.173.15:01:54.46#ibcon#first serial, iclass 22, count 0 2006.173.15:01:54.46#ibcon#enter sib2, iclass 22, count 0 2006.173.15:01:54.46#ibcon#flushed, iclass 22, count 0 2006.173.15:01:54.46#ibcon#about to write, iclass 22, count 0 2006.173.15:01:54.46#ibcon#wrote, iclass 22, count 0 2006.173.15:01:54.46#ibcon#about to read 3, iclass 22, count 0 2006.173.15:01:54.48#ibcon#read 3, iclass 22, count 0 2006.173.15:01:54.48#ibcon#about to read 4, iclass 22, count 0 2006.173.15:01:54.48#ibcon#read 4, iclass 22, count 0 2006.173.15:01:54.48#ibcon#about to read 5, iclass 22, count 0 2006.173.15:01:54.48#ibcon#read 5, iclass 22, count 0 2006.173.15:01:54.48#ibcon#about to read 6, iclass 22, count 0 2006.173.15:01:54.48#ibcon#read 6, iclass 22, count 0 2006.173.15:01:54.48#ibcon#end of sib2, iclass 22, count 0 2006.173.15:01:54.48#ibcon#*mode == 0, iclass 22, count 0 2006.173.15:01:54.48#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.15:01:54.48#ibcon#[27=USB\r\n] 2006.173.15:01:54.48#ibcon#*before write, iclass 22, count 0 2006.173.15:01:54.48#ibcon#enter sib2, iclass 22, count 0 2006.173.15:01:54.48#ibcon#flushed, iclass 22, count 0 2006.173.15:01:54.48#ibcon#about to write, iclass 22, count 0 2006.173.15:01:54.48#ibcon#wrote, iclass 22, count 0 2006.173.15:01:54.48#ibcon#about to read 3, iclass 22, count 0 2006.173.15:01:54.51#ibcon#read 3, iclass 22, count 0 2006.173.15:01:54.51#ibcon#about to read 4, iclass 22, count 0 2006.173.15:01:54.51#ibcon#read 4, iclass 22, count 0 2006.173.15:01:54.51#ibcon#about to read 5, iclass 22, count 0 2006.173.15:01:54.51#ibcon#read 5, iclass 22, count 0 2006.173.15:01:54.51#ibcon#about to read 6, iclass 22, count 0 2006.173.15:01:54.51#ibcon#read 6, iclass 22, count 0 2006.173.15:01:54.51#ibcon#end of sib2, iclass 22, count 0 2006.173.15:01:54.51#ibcon#*after write, iclass 22, count 0 2006.173.15:01:54.51#ibcon#*before return 0, iclass 22, count 0 2006.173.15:01:54.51#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.15:01:54.51#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.15:01:54.51#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.15:01:54.51#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.15:01:54.51$vck44/vabw=wide 2006.173.15:01:54.51#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.15:01:54.51#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.15:01:54.51#ibcon#ireg 8 cls_cnt 0 2006.173.15:01:54.51#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.15:01:54.51#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.15:01:54.51#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.15:01:54.51#ibcon#enter wrdev, iclass 24, count 0 2006.173.15:01:54.51#ibcon#first serial, iclass 24, count 0 2006.173.15:01:54.51#ibcon#enter sib2, iclass 24, count 0 2006.173.15:01:54.51#ibcon#flushed, iclass 24, count 0 2006.173.15:01:54.51#ibcon#about to write, iclass 24, count 0 2006.173.15:01:54.51#ibcon#wrote, iclass 24, count 0 2006.173.15:01:54.51#ibcon#about to read 3, iclass 24, count 0 2006.173.15:01:54.53#ibcon#read 3, iclass 24, count 0 2006.173.15:01:54.53#ibcon#about to read 4, iclass 24, count 0 2006.173.15:01:54.53#ibcon#read 4, iclass 24, count 0 2006.173.15:01:54.53#ibcon#about to read 5, iclass 24, count 0 2006.173.15:01:54.53#ibcon#read 5, iclass 24, count 0 2006.173.15:01:54.53#ibcon#about to read 6, iclass 24, count 0 2006.173.15:01:54.53#ibcon#read 6, iclass 24, count 0 2006.173.15:01:54.53#ibcon#end of sib2, iclass 24, count 0 2006.173.15:01:54.53#ibcon#*mode == 0, iclass 24, count 0 2006.173.15:01:54.53#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.15:01:54.53#ibcon#[25=BW32\r\n] 2006.173.15:01:54.53#ibcon#*before write, iclass 24, count 0 2006.173.15:01:54.53#ibcon#enter sib2, iclass 24, count 0 2006.173.15:01:54.53#ibcon#flushed, iclass 24, count 0 2006.173.15:01:54.53#ibcon#about to write, iclass 24, count 0 2006.173.15:01:54.53#ibcon#wrote, iclass 24, count 0 2006.173.15:01:54.53#ibcon#about to read 3, iclass 24, count 0 2006.173.15:01:54.56#ibcon#read 3, iclass 24, count 0 2006.173.15:01:54.56#ibcon#about to read 4, iclass 24, count 0 2006.173.15:01:54.56#ibcon#read 4, iclass 24, count 0 2006.173.15:01:54.56#ibcon#about to read 5, iclass 24, count 0 2006.173.15:01:54.56#ibcon#read 5, iclass 24, count 0 2006.173.15:01:54.56#ibcon#about to read 6, iclass 24, count 0 2006.173.15:01:54.56#ibcon#read 6, iclass 24, count 0 2006.173.15:01:54.56#ibcon#end of sib2, iclass 24, count 0 2006.173.15:01:54.56#ibcon#*after write, iclass 24, count 0 2006.173.15:01:54.56#ibcon#*before return 0, iclass 24, count 0 2006.173.15:01:54.56#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.15:01:54.56#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.15:01:54.56#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.15:01:54.56#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.15:01:54.56$vck44/vbbw=wide 2006.173.15:01:54.56#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.15:01:54.56#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.15:01:54.56#ibcon#ireg 8 cls_cnt 0 2006.173.15:01:54.56#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.15:01:54.63#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.15:01:54.63#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.15:01:54.63#ibcon#enter wrdev, iclass 26, count 0 2006.173.15:01:54.63#ibcon#first serial, iclass 26, count 0 2006.173.15:01:54.63#ibcon#enter sib2, iclass 26, count 0 2006.173.15:01:54.63#ibcon#flushed, iclass 26, count 0 2006.173.15:01:54.63#ibcon#about to write, iclass 26, count 0 2006.173.15:01:54.63#ibcon#wrote, iclass 26, count 0 2006.173.15:01:54.63#ibcon#about to read 3, iclass 26, count 0 2006.173.15:01:54.65#ibcon#read 3, iclass 26, count 0 2006.173.15:01:54.65#ibcon#about to read 4, iclass 26, count 0 2006.173.15:01:54.65#ibcon#read 4, iclass 26, count 0 2006.173.15:01:54.65#ibcon#about to read 5, iclass 26, count 0 2006.173.15:01:54.65#ibcon#read 5, iclass 26, count 0 2006.173.15:01:54.65#ibcon#about to read 6, iclass 26, count 0 2006.173.15:01:54.65#ibcon#read 6, iclass 26, count 0 2006.173.15:01:54.65#ibcon#end of sib2, iclass 26, count 0 2006.173.15:01:54.65#ibcon#*mode == 0, iclass 26, count 0 2006.173.15:01:54.65#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.15:01:54.65#ibcon#[27=BW32\r\n] 2006.173.15:01:54.65#ibcon#*before write, iclass 26, count 0 2006.173.15:01:54.65#ibcon#enter sib2, iclass 26, count 0 2006.173.15:01:54.65#ibcon#flushed, iclass 26, count 0 2006.173.15:01:54.65#ibcon#about to write, iclass 26, count 0 2006.173.15:01:54.65#ibcon#wrote, iclass 26, count 0 2006.173.15:01:54.65#ibcon#about to read 3, iclass 26, count 0 2006.173.15:01:54.68#ibcon#read 3, iclass 26, count 0 2006.173.15:01:54.68#ibcon#about to read 4, iclass 26, count 0 2006.173.15:01:54.68#ibcon#read 4, iclass 26, count 0 2006.173.15:01:54.68#ibcon#about to read 5, iclass 26, count 0 2006.173.15:01:54.68#ibcon#read 5, iclass 26, count 0 2006.173.15:01:54.68#ibcon#about to read 6, iclass 26, count 0 2006.173.15:01:54.68#ibcon#read 6, iclass 26, count 0 2006.173.15:01:54.68#ibcon#end of sib2, iclass 26, count 0 2006.173.15:01:54.68#ibcon#*after write, iclass 26, count 0 2006.173.15:01:54.68#ibcon#*before return 0, iclass 26, count 0 2006.173.15:01:54.68#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.15:01:54.68#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.15:01:54.68#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.15:01:54.68#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.15:01:54.68$setupk4/ifdk4 2006.173.15:01:54.68$ifdk4/lo= 2006.173.15:01:54.68$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.15:01:54.68$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.15:01:54.68$ifdk4/patch= 2006.173.15:01:54.68$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.15:01:54.68$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.15:01:54.68$setupk4/!*+20s 2006.173.15:01:55.37#abcon#<5=/06 1.2 2.7 20.921001003.3\r\n> 2006.173.15:01:55.39#abcon#{5=INTERFACE CLEAR} 2006.173.15:01:55.45#abcon#[5=S1D000X0/0*\r\n] 2006.173.15:02:05.54#abcon#<5=/06 1.3 3.0 20.921001003.3\r\n> 2006.173.15:02:05.56#abcon#{5=INTERFACE CLEAR} 2006.173.15:02:05.62#abcon#[5=S1D000X0/0*\r\n] 2006.173.15:02:09.13#trakl#Source acquired 2006.173.15:02:09.20$setupk4/"tpicd 2006.173.15:02:09.20$setupk4/echo=off 2006.173.15:02:09.20$setupk4/xlog=off 2006.173.15:02:09.20:!2006.173.15:02:34 2006.173.15:02:11.13#flagr#flagr/antenna,acquired 2006.173.15:02:34.00:preob 2006.173.15:02:34.14/onsource/TRACKING 2006.173.15:02:34.14:!2006.173.15:02:44 2006.173.15:02:44.00:"tape 2006.173.15:02:44.00:"st=record 2006.173.15:02:44.00:data_valid=on 2006.173.15:02:44.00:midob 2006.173.15:02:44.14/onsource/TRACKING 2006.173.15:02:44.14/wx/20.92,1003.3,100 2006.173.15:02:44.21/cable/+6.5084E-03 2006.173.15:02:45.30/va/01,07,usb,yes,52,55 2006.173.15:02:45.30/va/02,06,usb,yes,51,52 2006.173.15:02:45.30/va/03,05,usb,yes,65,67 2006.173.15:02:45.30/va/04,06,usb,yes,53,56 2006.173.15:02:45.30/va/05,04,usb,yes,42,43 2006.173.15:02:45.30/va/06,03,usb,yes,58,58 2006.173.15:02:45.30/va/07,04,usb,yes,47,49 2006.173.15:02:45.30/va/08,04,usb,yes,41,48 2006.173.15:02:45.53/valo/01,524.99,yes,locked 2006.173.15:02:45.53/valo/02,534.99,yes,locked 2006.173.15:02:45.53/valo/03,564.99,yes,locked 2006.173.15:02:45.53/valo/04,624.99,yes,locked 2006.173.15:02:45.53/valo/05,734.99,yes,locked 2006.173.15:02:45.53/valo/06,814.99,yes,locked 2006.173.15:02:45.53/valo/07,864.99,yes,locked 2006.173.15:02:45.53/valo/08,884.99,yes,locked 2006.173.15:02:46.62/vb/01,04,usb,yes,34,31 2006.173.15:02:46.62/vb/02,04,usb,yes,36,36 2006.173.15:02:46.62/vb/03,04,usb,yes,33,36 2006.173.15:02:46.62/vb/04,04,usb,yes,37,36 2006.173.15:02:46.62/vb/05,04,usb,yes,29,32 2006.173.15:02:46.62/vb/06,04,usb,yes,34,30 2006.173.15:02:46.62/vb/07,04,usb,yes,34,34 2006.173.15:02:46.62/vb/08,04,usb,yes,31,35 2006.173.15:02:46.85/vblo/01,629.99,yes,locked 2006.173.15:02:46.85/vblo/02,634.99,yes,locked 2006.173.15:02:46.85/vblo/03,649.99,yes,locked 2006.173.15:02:46.85/vblo/04,679.99,yes,locked 2006.173.15:02:46.85/vblo/05,709.99,yes,locked 2006.173.15:02:46.85/vblo/06,719.99,yes,locked 2006.173.15:02:46.85/vblo/07,734.99,yes,locked 2006.173.15:02:46.85/vblo/08,744.99,yes,locked 2006.173.15:02:47.00/vabw/8 2006.173.15:02:47.15/vbbw/8 2006.173.15:02:47.30/xfe/off,on,15.0 2006.173.15:02:47.69/ifatt/23,28,28,28 2006.173.15:02:48.08/fmout-gps/S +3.97E-07 2006.173.15:02:48.12:!2006.173.15:03:24 2006.173.15:03:24.00:data_valid=off 2006.173.15:03:24.00:"et 2006.173.15:03:24.00:!+3s 2006.173.15:03:27.01:"tape 2006.173.15:03:27.01:postob 2006.173.15:03:27.17/cable/+6.5100E-03 2006.173.15:03:27.17/wx/20.92,1003.2,100 2006.173.15:03:28.08/fmout-gps/S +3.97E-07 2006.173.15:03:28.08:scan_name=173-1508,jd0606,40 2006.173.15:03:28.08:source=3c274,123049.42,122328.0,2000.0,cw 2006.173.15:03:29.14#flagr#flagr/antenna,new-source 2006.173.15:03:29.14:checkk5 2006.173.15:03:29.55/chk_autoobs//k5ts1/ autoobs is running! 2006.173.15:03:29.95/chk_autoobs//k5ts2/ autoobs is running! 2006.173.15:03:30.36/chk_autoobs//k5ts3/ autoobs is running! 2006.173.15:03:30.75/chk_autoobs//k5ts4/ autoobs is running! 2006.173.15:03:31.15/chk_obsdata//k5ts1/T1731502??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.15:03:31.55/chk_obsdata//k5ts2/T1731502??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.15:03:34.92/chk_obsdata//k5ts3/T1731502??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.15:03:35.32/chk_obsdata//k5ts4/T1731502??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.15:03:36.03/k5log//k5ts1_log_newline 2006.173.15:03:36.73/k5log//k5ts2_log_newline 2006.173.15:03:37.44/k5log//k5ts3_log_newline 2006.173.15:03:38.15/k5log//k5ts4_log_newline 2006.173.15:03:38.17/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.15:03:38.17:setupk4=1 2006.173.15:03:38.17$setupk4/echo=on 2006.173.15:03:38.17$setupk4/pcalon 2006.173.15:03:38.17$pcalon/"no phase cal control is implemented here 2006.173.15:03:38.17$setupk4/"tpicd=stop 2006.173.15:03:38.17$setupk4/"rec=synch_on 2006.173.15:03:38.17$setupk4/"rec_mode=128 2006.173.15:03:38.17$setupk4/!* 2006.173.15:03:38.17$setupk4/recpk4 2006.173.15:03:38.18$recpk4/recpatch= 2006.173.15:03:38.18$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.15:03:38.18$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.15:03:38.18$setupk4/vck44 2006.173.15:03:38.18$vck44/valo=1,524.99 2006.173.15:03:38.18#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.15:03:38.18#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.15:03:38.18#ibcon#ireg 17 cls_cnt 0 2006.173.15:03:38.18#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.15:03:38.18#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.15:03:38.18#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.15:03:38.18#ibcon#enter wrdev, iclass 39, count 0 2006.173.15:03:38.18#ibcon#first serial, iclass 39, count 0 2006.173.15:03:38.18#ibcon#enter sib2, iclass 39, count 0 2006.173.15:03:38.18#ibcon#flushed, iclass 39, count 0 2006.173.15:03:38.18#ibcon#about to write, iclass 39, count 0 2006.173.15:03:38.18#ibcon#wrote, iclass 39, count 0 2006.173.15:03:38.18#ibcon#about to read 3, iclass 39, count 0 2006.173.15:03:38.19#ibcon#read 3, iclass 39, count 0 2006.173.15:03:38.19#ibcon#about to read 4, iclass 39, count 0 2006.173.15:03:38.19#ibcon#read 4, iclass 39, count 0 2006.173.15:03:38.19#ibcon#about to read 5, iclass 39, count 0 2006.173.15:03:38.19#ibcon#read 5, iclass 39, count 0 2006.173.15:03:38.19#ibcon#about to read 6, iclass 39, count 0 2006.173.15:03:38.19#ibcon#read 6, iclass 39, count 0 2006.173.15:03:38.19#ibcon#end of sib2, iclass 39, count 0 2006.173.15:03:38.19#ibcon#*mode == 0, iclass 39, count 0 2006.173.15:03:38.19#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.15:03:38.19#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.15:03:38.19#ibcon#*before write, iclass 39, count 0 2006.173.15:03:38.19#ibcon#enter sib2, iclass 39, count 0 2006.173.15:03:38.19#ibcon#flushed, iclass 39, count 0 2006.173.15:03:38.19#ibcon#about to write, iclass 39, count 0 2006.173.15:03:38.19#ibcon#wrote, iclass 39, count 0 2006.173.15:03:38.19#ibcon#about to read 3, iclass 39, count 0 2006.173.15:03:38.24#ibcon#read 3, iclass 39, count 0 2006.173.15:03:38.24#ibcon#about to read 4, iclass 39, count 0 2006.173.15:03:38.24#ibcon#read 4, iclass 39, count 0 2006.173.15:03:38.24#ibcon#about to read 5, iclass 39, count 0 2006.173.15:03:38.24#ibcon#read 5, iclass 39, count 0 2006.173.15:03:38.24#ibcon#about to read 6, iclass 39, count 0 2006.173.15:03:38.24#ibcon#read 6, iclass 39, count 0 2006.173.15:03:38.24#ibcon#end of sib2, iclass 39, count 0 2006.173.15:03:38.24#ibcon#*after write, iclass 39, count 0 2006.173.15:03:38.24#ibcon#*before return 0, iclass 39, count 0 2006.173.15:03:38.24#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.15:03:38.24#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.15:03:38.24#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.15:03:38.24#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.15:03:38.24$vck44/va=1,7 2006.173.15:03:38.24#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.15:03:38.24#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.15:03:38.24#ibcon#ireg 11 cls_cnt 2 2006.173.15:03:38.24#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.15:03:38.24#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.15:03:38.24#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.15:03:38.24#ibcon#enter wrdev, iclass 3, count 2 2006.173.15:03:38.24#ibcon#first serial, iclass 3, count 2 2006.173.15:03:38.24#ibcon#enter sib2, iclass 3, count 2 2006.173.15:03:38.24#ibcon#flushed, iclass 3, count 2 2006.173.15:03:38.24#ibcon#about to write, iclass 3, count 2 2006.173.15:03:38.24#ibcon#wrote, iclass 3, count 2 2006.173.15:03:38.24#ibcon#about to read 3, iclass 3, count 2 2006.173.15:03:38.26#ibcon#read 3, iclass 3, count 2 2006.173.15:03:38.26#ibcon#about to read 4, iclass 3, count 2 2006.173.15:03:38.26#ibcon#read 4, iclass 3, count 2 2006.173.15:03:38.26#ibcon#about to read 5, iclass 3, count 2 2006.173.15:03:38.26#ibcon#read 5, iclass 3, count 2 2006.173.15:03:38.26#ibcon#about to read 6, iclass 3, count 2 2006.173.15:03:38.26#ibcon#read 6, iclass 3, count 2 2006.173.15:03:38.26#ibcon#end of sib2, iclass 3, count 2 2006.173.15:03:38.26#ibcon#*mode == 0, iclass 3, count 2 2006.173.15:03:38.26#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.15:03:38.26#ibcon#[25=AT01-07\r\n] 2006.173.15:03:38.26#ibcon#*before write, iclass 3, count 2 2006.173.15:03:38.26#ibcon#enter sib2, iclass 3, count 2 2006.173.15:03:38.26#ibcon#flushed, iclass 3, count 2 2006.173.15:03:38.26#ibcon#about to write, iclass 3, count 2 2006.173.15:03:38.26#ibcon#wrote, iclass 3, count 2 2006.173.15:03:38.26#ibcon#about to read 3, iclass 3, count 2 2006.173.15:03:38.29#ibcon#read 3, iclass 3, count 2 2006.173.15:03:38.29#ibcon#about to read 4, iclass 3, count 2 2006.173.15:03:38.29#ibcon#read 4, iclass 3, count 2 2006.173.15:03:38.29#ibcon#about to read 5, iclass 3, count 2 2006.173.15:03:38.29#ibcon#read 5, iclass 3, count 2 2006.173.15:03:38.29#ibcon#about to read 6, iclass 3, count 2 2006.173.15:03:38.29#ibcon#read 6, iclass 3, count 2 2006.173.15:03:38.29#ibcon#end of sib2, iclass 3, count 2 2006.173.15:03:38.29#ibcon#*after write, iclass 3, count 2 2006.173.15:03:38.29#ibcon#*before return 0, iclass 3, count 2 2006.173.15:03:38.29#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.15:03:38.29#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.15:03:38.29#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.15:03:38.29#ibcon#ireg 7 cls_cnt 0 2006.173.15:03:38.29#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.15:03:38.41#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.15:03:38.41#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.15:03:38.41#ibcon#enter wrdev, iclass 3, count 0 2006.173.15:03:38.41#ibcon#first serial, iclass 3, count 0 2006.173.15:03:38.41#ibcon#enter sib2, iclass 3, count 0 2006.173.15:03:38.41#ibcon#flushed, iclass 3, count 0 2006.173.15:03:38.41#ibcon#about to write, iclass 3, count 0 2006.173.15:03:38.41#ibcon#wrote, iclass 3, count 0 2006.173.15:03:38.41#ibcon#about to read 3, iclass 3, count 0 2006.173.15:03:38.43#ibcon#read 3, iclass 3, count 0 2006.173.15:03:38.43#ibcon#about to read 4, iclass 3, count 0 2006.173.15:03:38.43#ibcon#read 4, iclass 3, count 0 2006.173.15:03:38.43#ibcon#about to read 5, iclass 3, count 0 2006.173.15:03:38.43#ibcon#read 5, iclass 3, count 0 2006.173.15:03:38.43#ibcon#about to read 6, iclass 3, count 0 2006.173.15:03:38.43#ibcon#read 6, iclass 3, count 0 2006.173.15:03:38.43#ibcon#end of sib2, iclass 3, count 0 2006.173.15:03:38.43#ibcon#*mode == 0, iclass 3, count 0 2006.173.15:03:38.43#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.15:03:38.43#ibcon#[25=USB\r\n] 2006.173.15:03:38.43#ibcon#*before write, iclass 3, count 0 2006.173.15:03:38.43#ibcon#enter sib2, iclass 3, count 0 2006.173.15:03:38.43#ibcon#flushed, iclass 3, count 0 2006.173.15:03:38.43#ibcon#about to write, iclass 3, count 0 2006.173.15:03:38.43#ibcon#wrote, iclass 3, count 0 2006.173.15:03:38.43#ibcon#about to read 3, iclass 3, count 0 2006.173.15:03:38.46#ibcon#read 3, iclass 3, count 0 2006.173.15:03:38.46#ibcon#about to read 4, iclass 3, count 0 2006.173.15:03:38.46#ibcon#read 4, iclass 3, count 0 2006.173.15:03:38.46#ibcon#about to read 5, iclass 3, count 0 2006.173.15:03:38.46#ibcon#read 5, iclass 3, count 0 2006.173.15:03:38.46#ibcon#about to read 6, iclass 3, count 0 2006.173.15:03:38.46#ibcon#read 6, iclass 3, count 0 2006.173.15:03:38.46#ibcon#end of sib2, iclass 3, count 0 2006.173.15:03:38.46#ibcon#*after write, iclass 3, count 0 2006.173.15:03:38.46#ibcon#*before return 0, iclass 3, count 0 2006.173.15:03:38.46#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.15:03:38.46#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.15:03:38.46#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.15:03:38.46#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.15:03:38.46$vck44/valo=2,534.99 2006.173.15:03:38.46#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.15:03:38.46#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.15:03:38.46#ibcon#ireg 17 cls_cnt 0 2006.173.15:03:38.46#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.15:03:38.46#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.15:03:38.46#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.15:03:38.46#ibcon#enter wrdev, iclass 5, count 0 2006.173.15:03:38.46#ibcon#first serial, iclass 5, count 0 2006.173.15:03:38.46#ibcon#enter sib2, iclass 5, count 0 2006.173.15:03:38.46#ibcon#flushed, iclass 5, count 0 2006.173.15:03:38.46#ibcon#about to write, iclass 5, count 0 2006.173.15:03:38.46#ibcon#wrote, iclass 5, count 0 2006.173.15:03:38.46#ibcon#about to read 3, iclass 5, count 0 2006.173.15:03:38.48#ibcon#read 3, iclass 5, count 0 2006.173.15:03:38.48#ibcon#about to read 4, iclass 5, count 0 2006.173.15:03:38.48#ibcon#read 4, iclass 5, count 0 2006.173.15:03:38.48#ibcon#about to read 5, iclass 5, count 0 2006.173.15:03:38.48#ibcon#read 5, iclass 5, count 0 2006.173.15:03:38.48#ibcon#about to read 6, iclass 5, count 0 2006.173.15:03:38.48#ibcon#read 6, iclass 5, count 0 2006.173.15:03:38.48#ibcon#end of sib2, iclass 5, count 0 2006.173.15:03:38.48#ibcon#*mode == 0, iclass 5, count 0 2006.173.15:03:38.48#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.15:03:38.48#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.15:03:38.48#ibcon#*before write, iclass 5, count 0 2006.173.15:03:38.48#ibcon#enter sib2, iclass 5, count 0 2006.173.15:03:38.48#ibcon#flushed, iclass 5, count 0 2006.173.15:03:38.48#ibcon#about to write, iclass 5, count 0 2006.173.15:03:38.48#ibcon#wrote, iclass 5, count 0 2006.173.15:03:38.48#ibcon#about to read 3, iclass 5, count 0 2006.173.15:03:38.52#ibcon#read 3, iclass 5, count 0 2006.173.15:03:38.52#ibcon#about to read 4, iclass 5, count 0 2006.173.15:03:38.52#ibcon#read 4, iclass 5, count 0 2006.173.15:03:38.52#ibcon#about to read 5, iclass 5, count 0 2006.173.15:03:38.52#ibcon#read 5, iclass 5, count 0 2006.173.15:03:38.52#ibcon#about to read 6, iclass 5, count 0 2006.173.15:03:38.52#ibcon#read 6, iclass 5, count 0 2006.173.15:03:38.52#ibcon#end of sib2, iclass 5, count 0 2006.173.15:03:38.52#ibcon#*after write, iclass 5, count 0 2006.173.15:03:38.52#ibcon#*before return 0, iclass 5, count 0 2006.173.15:03:38.52#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.15:03:38.52#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.15:03:38.52#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.15:03:38.52#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.15:03:38.52$vck44/va=2,6 2006.173.15:03:38.52#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.173.15:03:38.52#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.173.15:03:38.52#ibcon#ireg 11 cls_cnt 2 2006.173.15:03:38.52#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.15:03:38.58#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.15:03:38.58#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.15:03:38.58#ibcon#enter wrdev, iclass 7, count 2 2006.173.15:03:38.58#ibcon#first serial, iclass 7, count 2 2006.173.15:03:38.58#ibcon#enter sib2, iclass 7, count 2 2006.173.15:03:38.58#ibcon#flushed, iclass 7, count 2 2006.173.15:03:38.58#ibcon#about to write, iclass 7, count 2 2006.173.15:03:38.58#ibcon#wrote, iclass 7, count 2 2006.173.15:03:38.58#ibcon#about to read 3, iclass 7, count 2 2006.173.15:03:38.60#ibcon#read 3, iclass 7, count 2 2006.173.15:03:38.60#ibcon#about to read 4, iclass 7, count 2 2006.173.15:03:38.60#ibcon#read 4, iclass 7, count 2 2006.173.15:03:38.60#ibcon#about to read 5, iclass 7, count 2 2006.173.15:03:38.60#ibcon#read 5, iclass 7, count 2 2006.173.15:03:38.60#ibcon#about to read 6, iclass 7, count 2 2006.173.15:03:38.60#ibcon#read 6, iclass 7, count 2 2006.173.15:03:38.60#ibcon#end of sib2, iclass 7, count 2 2006.173.15:03:38.60#ibcon#*mode == 0, iclass 7, count 2 2006.173.15:03:38.60#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.173.15:03:38.60#ibcon#[25=AT02-06\r\n] 2006.173.15:03:38.60#ibcon#*before write, iclass 7, count 2 2006.173.15:03:38.60#ibcon#enter sib2, iclass 7, count 2 2006.173.15:03:38.60#ibcon#flushed, iclass 7, count 2 2006.173.15:03:38.60#ibcon#about to write, iclass 7, count 2 2006.173.15:03:38.60#ibcon#wrote, iclass 7, count 2 2006.173.15:03:38.60#ibcon#about to read 3, iclass 7, count 2 2006.173.15:03:38.63#ibcon#read 3, iclass 7, count 2 2006.173.15:03:38.63#ibcon#about to read 4, iclass 7, count 2 2006.173.15:03:38.63#ibcon#read 4, iclass 7, count 2 2006.173.15:03:38.63#ibcon#about to read 5, iclass 7, count 2 2006.173.15:03:38.63#ibcon#read 5, iclass 7, count 2 2006.173.15:03:38.63#ibcon#about to read 6, iclass 7, count 2 2006.173.15:03:38.63#ibcon#read 6, iclass 7, count 2 2006.173.15:03:38.63#ibcon#end of sib2, iclass 7, count 2 2006.173.15:03:38.63#ibcon#*after write, iclass 7, count 2 2006.173.15:03:38.63#ibcon#*before return 0, iclass 7, count 2 2006.173.15:03:38.63#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.15:03:38.63#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.173.15:03:38.63#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.173.15:03:38.63#ibcon#ireg 7 cls_cnt 0 2006.173.15:03:38.63#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.15:03:38.75#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.15:03:38.75#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.15:03:38.75#ibcon#enter wrdev, iclass 7, count 0 2006.173.15:03:38.75#ibcon#first serial, iclass 7, count 0 2006.173.15:03:38.75#ibcon#enter sib2, iclass 7, count 0 2006.173.15:03:38.75#ibcon#flushed, iclass 7, count 0 2006.173.15:03:38.75#ibcon#about to write, iclass 7, count 0 2006.173.15:03:38.75#ibcon#wrote, iclass 7, count 0 2006.173.15:03:38.75#ibcon#about to read 3, iclass 7, count 0 2006.173.15:03:38.77#ibcon#read 3, iclass 7, count 0 2006.173.15:03:38.77#ibcon#about to read 4, iclass 7, count 0 2006.173.15:03:38.77#ibcon#read 4, iclass 7, count 0 2006.173.15:03:38.77#ibcon#about to read 5, iclass 7, count 0 2006.173.15:03:38.77#ibcon#read 5, iclass 7, count 0 2006.173.15:03:38.77#ibcon#about to read 6, iclass 7, count 0 2006.173.15:03:38.77#ibcon#read 6, iclass 7, count 0 2006.173.15:03:38.77#ibcon#end of sib2, iclass 7, count 0 2006.173.15:03:38.77#ibcon#*mode == 0, iclass 7, count 0 2006.173.15:03:38.77#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.15:03:38.77#ibcon#[25=USB\r\n] 2006.173.15:03:38.77#ibcon#*before write, iclass 7, count 0 2006.173.15:03:38.77#ibcon#enter sib2, iclass 7, count 0 2006.173.15:03:38.77#ibcon#flushed, iclass 7, count 0 2006.173.15:03:38.77#ibcon#about to write, iclass 7, count 0 2006.173.15:03:38.77#ibcon#wrote, iclass 7, count 0 2006.173.15:03:38.77#ibcon#about to read 3, iclass 7, count 0 2006.173.15:03:38.80#ibcon#read 3, iclass 7, count 0 2006.173.15:03:38.80#ibcon#about to read 4, iclass 7, count 0 2006.173.15:03:38.80#ibcon#read 4, iclass 7, count 0 2006.173.15:03:38.80#ibcon#about to read 5, iclass 7, count 0 2006.173.15:03:38.80#ibcon#read 5, iclass 7, count 0 2006.173.15:03:38.80#ibcon#about to read 6, iclass 7, count 0 2006.173.15:03:38.80#ibcon#read 6, iclass 7, count 0 2006.173.15:03:38.80#ibcon#end of sib2, iclass 7, count 0 2006.173.15:03:38.80#ibcon#*after write, iclass 7, count 0 2006.173.15:03:38.80#ibcon#*before return 0, iclass 7, count 0 2006.173.15:03:38.80#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.15:03:38.80#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.173.15:03:38.80#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.15:03:38.80#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.15:03:38.80$vck44/valo=3,564.99 2006.173.15:03:38.80#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.15:03:38.80#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.15:03:38.80#ibcon#ireg 17 cls_cnt 0 2006.173.15:03:38.80#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.15:03:38.80#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.15:03:38.80#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.15:03:38.80#ibcon#enter wrdev, iclass 11, count 0 2006.173.15:03:38.80#ibcon#first serial, iclass 11, count 0 2006.173.15:03:38.80#ibcon#enter sib2, iclass 11, count 0 2006.173.15:03:38.80#ibcon#flushed, iclass 11, count 0 2006.173.15:03:38.80#ibcon#about to write, iclass 11, count 0 2006.173.15:03:38.80#ibcon#wrote, iclass 11, count 0 2006.173.15:03:38.80#ibcon#about to read 3, iclass 11, count 0 2006.173.15:03:38.82#ibcon#read 3, iclass 11, count 0 2006.173.15:03:38.82#ibcon#about to read 4, iclass 11, count 0 2006.173.15:03:38.82#ibcon#read 4, iclass 11, count 0 2006.173.15:03:38.82#ibcon#about to read 5, iclass 11, count 0 2006.173.15:03:38.82#ibcon#read 5, iclass 11, count 0 2006.173.15:03:38.82#ibcon#about to read 6, iclass 11, count 0 2006.173.15:03:38.82#ibcon#read 6, iclass 11, count 0 2006.173.15:03:38.82#ibcon#end of sib2, iclass 11, count 0 2006.173.15:03:38.82#ibcon#*mode == 0, iclass 11, count 0 2006.173.15:03:38.82#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.15:03:38.82#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.15:03:38.82#ibcon#*before write, iclass 11, count 0 2006.173.15:03:38.82#ibcon#enter sib2, iclass 11, count 0 2006.173.15:03:38.82#ibcon#flushed, iclass 11, count 0 2006.173.15:03:38.82#ibcon#about to write, iclass 11, count 0 2006.173.15:03:38.82#ibcon#wrote, iclass 11, count 0 2006.173.15:03:38.82#ibcon#about to read 3, iclass 11, count 0 2006.173.15:03:38.86#ibcon#read 3, iclass 11, count 0 2006.173.15:03:38.86#ibcon#about to read 4, iclass 11, count 0 2006.173.15:03:38.86#ibcon#read 4, iclass 11, count 0 2006.173.15:03:38.86#ibcon#about to read 5, iclass 11, count 0 2006.173.15:03:38.86#ibcon#read 5, iclass 11, count 0 2006.173.15:03:38.86#ibcon#about to read 6, iclass 11, count 0 2006.173.15:03:38.86#ibcon#read 6, iclass 11, count 0 2006.173.15:03:38.86#ibcon#end of sib2, iclass 11, count 0 2006.173.15:03:38.86#ibcon#*after write, iclass 11, count 0 2006.173.15:03:38.86#ibcon#*before return 0, iclass 11, count 0 2006.173.15:03:38.86#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.15:03:38.86#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.15:03:38.86#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.15:03:38.86#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.15:03:38.86$vck44/va=3,5 2006.173.15:03:38.86#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.173.15:03:38.86#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.173.15:03:38.86#ibcon#ireg 11 cls_cnt 2 2006.173.15:03:38.86#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.15:03:38.92#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.15:03:38.92#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.15:03:38.92#ibcon#enter wrdev, iclass 13, count 2 2006.173.15:03:38.92#ibcon#first serial, iclass 13, count 2 2006.173.15:03:38.92#ibcon#enter sib2, iclass 13, count 2 2006.173.15:03:38.92#ibcon#flushed, iclass 13, count 2 2006.173.15:03:38.92#ibcon#about to write, iclass 13, count 2 2006.173.15:03:38.92#ibcon#wrote, iclass 13, count 2 2006.173.15:03:38.92#ibcon#about to read 3, iclass 13, count 2 2006.173.15:03:38.94#ibcon#read 3, iclass 13, count 2 2006.173.15:03:38.94#ibcon#about to read 4, iclass 13, count 2 2006.173.15:03:38.94#ibcon#read 4, iclass 13, count 2 2006.173.15:03:38.94#ibcon#about to read 5, iclass 13, count 2 2006.173.15:03:38.94#ibcon#read 5, iclass 13, count 2 2006.173.15:03:38.94#ibcon#about to read 6, iclass 13, count 2 2006.173.15:03:38.94#ibcon#read 6, iclass 13, count 2 2006.173.15:03:38.94#ibcon#end of sib2, iclass 13, count 2 2006.173.15:03:38.94#ibcon#*mode == 0, iclass 13, count 2 2006.173.15:03:38.94#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.173.15:03:38.94#ibcon#[25=AT03-05\r\n] 2006.173.15:03:38.94#ibcon#*before write, iclass 13, count 2 2006.173.15:03:38.94#ibcon#enter sib2, iclass 13, count 2 2006.173.15:03:38.94#ibcon#flushed, iclass 13, count 2 2006.173.15:03:38.94#ibcon#about to write, iclass 13, count 2 2006.173.15:03:38.94#ibcon#wrote, iclass 13, count 2 2006.173.15:03:38.94#ibcon#about to read 3, iclass 13, count 2 2006.173.15:03:38.97#ibcon#read 3, iclass 13, count 2 2006.173.15:03:38.97#ibcon#about to read 4, iclass 13, count 2 2006.173.15:03:38.97#ibcon#read 4, iclass 13, count 2 2006.173.15:03:38.97#ibcon#about to read 5, iclass 13, count 2 2006.173.15:03:38.97#ibcon#read 5, iclass 13, count 2 2006.173.15:03:38.97#ibcon#about to read 6, iclass 13, count 2 2006.173.15:03:38.97#ibcon#read 6, iclass 13, count 2 2006.173.15:03:38.97#ibcon#end of sib2, iclass 13, count 2 2006.173.15:03:38.97#ibcon#*after write, iclass 13, count 2 2006.173.15:03:38.97#ibcon#*before return 0, iclass 13, count 2 2006.173.15:03:38.97#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.15:03:38.97#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.173.15:03:38.97#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.173.15:03:38.97#ibcon#ireg 7 cls_cnt 0 2006.173.15:03:38.97#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.15:03:39.09#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.15:03:39.09#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.15:03:39.09#ibcon#enter wrdev, iclass 13, count 0 2006.173.15:03:39.09#ibcon#first serial, iclass 13, count 0 2006.173.15:03:39.09#ibcon#enter sib2, iclass 13, count 0 2006.173.15:03:39.09#ibcon#flushed, iclass 13, count 0 2006.173.15:03:39.09#ibcon#about to write, iclass 13, count 0 2006.173.15:03:39.09#ibcon#wrote, iclass 13, count 0 2006.173.15:03:39.09#ibcon#about to read 3, iclass 13, count 0 2006.173.15:03:39.11#ibcon#read 3, iclass 13, count 0 2006.173.15:03:39.11#ibcon#about to read 4, iclass 13, count 0 2006.173.15:03:39.11#ibcon#read 4, iclass 13, count 0 2006.173.15:03:39.11#ibcon#about to read 5, iclass 13, count 0 2006.173.15:03:39.11#ibcon#read 5, iclass 13, count 0 2006.173.15:03:39.11#ibcon#about to read 6, iclass 13, count 0 2006.173.15:03:39.11#ibcon#read 6, iclass 13, count 0 2006.173.15:03:39.11#ibcon#end of sib2, iclass 13, count 0 2006.173.15:03:39.11#ibcon#*mode == 0, iclass 13, count 0 2006.173.15:03:39.11#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.15:03:39.11#ibcon#[25=USB\r\n] 2006.173.15:03:39.11#ibcon#*before write, iclass 13, count 0 2006.173.15:03:39.11#ibcon#enter sib2, iclass 13, count 0 2006.173.15:03:39.11#ibcon#flushed, iclass 13, count 0 2006.173.15:03:39.11#ibcon#about to write, iclass 13, count 0 2006.173.15:03:39.11#ibcon#wrote, iclass 13, count 0 2006.173.15:03:39.11#ibcon#about to read 3, iclass 13, count 0 2006.173.15:03:39.14#ibcon#read 3, iclass 13, count 0 2006.173.15:03:39.14#ibcon#about to read 4, iclass 13, count 0 2006.173.15:03:39.14#ibcon#read 4, iclass 13, count 0 2006.173.15:03:39.14#ibcon#about to read 5, iclass 13, count 0 2006.173.15:03:39.14#ibcon#read 5, iclass 13, count 0 2006.173.15:03:39.14#ibcon#about to read 6, iclass 13, count 0 2006.173.15:03:39.14#ibcon#read 6, iclass 13, count 0 2006.173.15:03:39.14#ibcon#end of sib2, iclass 13, count 0 2006.173.15:03:39.14#ibcon#*after write, iclass 13, count 0 2006.173.15:03:39.14#ibcon#*before return 0, iclass 13, count 0 2006.173.15:03:39.14#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.15:03:39.14#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.173.15:03:39.14#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.15:03:39.14#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.15:03:39.14$vck44/valo=4,624.99 2006.173.15:03:39.14#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.15:03:39.14#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.15:03:39.14#ibcon#ireg 17 cls_cnt 0 2006.173.15:03:39.14#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.15:03:39.14#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.15:03:39.14#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.15:03:39.14#ibcon#enter wrdev, iclass 15, count 0 2006.173.15:03:39.14#ibcon#first serial, iclass 15, count 0 2006.173.15:03:39.14#ibcon#enter sib2, iclass 15, count 0 2006.173.15:03:39.14#ibcon#flushed, iclass 15, count 0 2006.173.15:03:39.14#ibcon#about to write, iclass 15, count 0 2006.173.15:03:39.14#ibcon#wrote, iclass 15, count 0 2006.173.15:03:39.14#ibcon#about to read 3, iclass 15, count 0 2006.173.15:03:39.16#ibcon#read 3, iclass 15, count 0 2006.173.15:03:39.16#ibcon#about to read 4, iclass 15, count 0 2006.173.15:03:39.16#ibcon#read 4, iclass 15, count 0 2006.173.15:03:39.16#ibcon#about to read 5, iclass 15, count 0 2006.173.15:03:39.16#ibcon#read 5, iclass 15, count 0 2006.173.15:03:39.16#ibcon#about to read 6, iclass 15, count 0 2006.173.15:03:39.16#ibcon#read 6, iclass 15, count 0 2006.173.15:03:39.16#ibcon#end of sib2, iclass 15, count 0 2006.173.15:03:39.16#ibcon#*mode == 0, iclass 15, count 0 2006.173.15:03:39.16#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.15:03:39.16#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.15:03:39.16#ibcon#*before write, iclass 15, count 0 2006.173.15:03:39.16#ibcon#enter sib2, iclass 15, count 0 2006.173.15:03:39.16#ibcon#flushed, iclass 15, count 0 2006.173.15:03:39.16#ibcon#about to write, iclass 15, count 0 2006.173.15:03:39.16#ibcon#wrote, iclass 15, count 0 2006.173.15:03:39.16#ibcon#about to read 3, iclass 15, count 0 2006.173.15:03:39.20#ibcon#read 3, iclass 15, count 0 2006.173.15:03:39.20#ibcon#about to read 4, iclass 15, count 0 2006.173.15:03:39.20#ibcon#read 4, iclass 15, count 0 2006.173.15:03:39.20#ibcon#about to read 5, iclass 15, count 0 2006.173.15:03:39.20#ibcon#read 5, iclass 15, count 0 2006.173.15:03:39.20#ibcon#about to read 6, iclass 15, count 0 2006.173.15:03:39.20#ibcon#read 6, iclass 15, count 0 2006.173.15:03:39.20#ibcon#end of sib2, iclass 15, count 0 2006.173.15:03:39.20#ibcon#*after write, iclass 15, count 0 2006.173.15:03:39.20#ibcon#*before return 0, iclass 15, count 0 2006.173.15:03:39.20#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.15:03:39.20#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.15:03:39.20#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.15:03:39.20#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.15:03:39.20$vck44/va=4,6 2006.173.15:03:39.20#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.15:03:39.20#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.15:03:39.20#ibcon#ireg 11 cls_cnt 2 2006.173.15:03:39.20#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.15:03:39.26#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.15:03:39.26#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.15:03:39.26#ibcon#enter wrdev, iclass 17, count 2 2006.173.15:03:39.26#ibcon#first serial, iclass 17, count 2 2006.173.15:03:39.26#ibcon#enter sib2, iclass 17, count 2 2006.173.15:03:39.26#ibcon#flushed, iclass 17, count 2 2006.173.15:03:39.26#ibcon#about to write, iclass 17, count 2 2006.173.15:03:39.26#ibcon#wrote, iclass 17, count 2 2006.173.15:03:39.26#ibcon#about to read 3, iclass 17, count 2 2006.173.15:03:39.28#ibcon#read 3, iclass 17, count 2 2006.173.15:03:39.28#ibcon#about to read 4, iclass 17, count 2 2006.173.15:03:39.28#ibcon#read 4, iclass 17, count 2 2006.173.15:03:39.28#ibcon#about to read 5, iclass 17, count 2 2006.173.15:03:39.28#ibcon#read 5, iclass 17, count 2 2006.173.15:03:39.28#ibcon#about to read 6, iclass 17, count 2 2006.173.15:03:39.28#ibcon#read 6, iclass 17, count 2 2006.173.15:03:39.28#ibcon#end of sib2, iclass 17, count 2 2006.173.15:03:39.28#ibcon#*mode == 0, iclass 17, count 2 2006.173.15:03:39.28#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.15:03:39.28#ibcon#[25=AT04-06\r\n] 2006.173.15:03:39.28#ibcon#*before write, iclass 17, count 2 2006.173.15:03:39.28#ibcon#enter sib2, iclass 17, count 2 2006.173.15:03:39.28#ibcon#flushed, iclass 17, count 2 2006.173.15:03:39.28#ibcon#about to write, iclass 17, count 2 2006.173.15:03:39.28#ibcon#wrote, iclass 17, count 2 2006.173.15:03:39.28#ibcon#about to read 3, iclass 17, count 2 2006.173.15:03:39.31#ibcon#read 3, iclass 17, count 2 2006.173.15:03:39.31#ibcon#about to read 4, iclass 17, count 2 2006.173.15:03:39.31#ibcon#read 4, iclass 17, count 2 2006.173.15:03:39.31#ibcon#about to read 5, iclass 17, count 2 2006.173.15:03:39.31#ibcon#read 5, iclass 17, count 2 2006.173.15:03:39.31#ibcon#about to read 6, iclass 17, count 2 2006.173.15:03:39.31#ibcon#read 6, iclass 17, count 2 2006.173.15:03:39.31#ibcon#end of sib2, iclass 17, count 2 2006.173.15:03:39.31#ibcon#*after write, iclass 17, count 2 2006.173.15:03:39.31#ibcon#*before return 0, iclass 17, count 2 2006.173.15:03:39.31#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.15:03:39.31#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.15:03:39.31#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.15:03:39.31#ibcon#ireg 7 cls_cnt 0 2006.173.15:03:39.31#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.15:03:39.43#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.15:03:39.43#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.15:03:39.43#ibcon#enter wrdev, iclass 17, count 0 2006.173.15:03:39.43#ibcon#first serial, iclass 17, count 0 2006.173.15:03:39.43#ibcon#enter sib2, iclass 17, count 0 2006.173.15:03:39.43#ibcon#flushed, iclass 17, count 0 2006.173.15:03:39.43#ibcon#about to write, iclass 17, count 0 2006.173.15:03:39.43#ibcon#wrote, iclass 17, count 0 2006.173.15:03:39.43#ibcon#about to read 3, iclass 17, count 0 2006.173.15:03:39.45#ibcon#read 3, iclass 17, count 0 2006.173.15:03:39.45#ibcon#about to read 4, iclass 17, count 0 2006.173.15:03:39.45#ibcon#read 4, iclass 17, count 0 2006.173.15:03:39.45#ibcon#about to read 5, iclass 17, count 0 2006.173.15:03:39.45#ibcon#read 5, iclass 17, count 0 2006.173.15:03:39.45#ibcon#about to read 6, iclass 17, count 0 2006.173.15:03:39.45#ibcon#read 6, iclass 17, count 0 2006.173.15:03:39.45#ibcon#end of sib2, iclass 17, count 0 2006.173.15:03:39.45#ibcon#*mode == 0, iclass 17, count 0 2006.173.15:03:39.45#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.15:03:39.45#ibcon#[25=USB\r\n] 2006.173.15:03:39.45#ibcon#*before write, iclass 17, count 0 2006.173.15:03:39.45#ibcon#enter sib2, iclass 17, count 0 2006.173.15:03:39.45#ibcon#flushed, iclass 17, count 0 2006.173.15:03:39.45#ibcon#about to write, iclass 17, count 0 2006.173.15:03:39.45#ibcon#wrote, iclass 17, count 0 2006.173.15:03:39.45#ibcon#about to read 3, iclass 17, count 0 2006.173.15:03:39.48#ibcon#read 3, iclass 17, count 0 2006.173.15:03:39.48#ibcon#about to read 4, iclass 17, count 0 2006.173.15:03:39.48#ibcon#read 4, iclass 17, count 0 2006.173.15:03:39.48#ibcon#about to read 5, iclass 17, count 0 2006.173.15:03:39.48#ibcon#read 5, iclass 17, count 0 2006.173.15:03:39.48#ibcon#about to read 6, iclass 17, count 0 2006.173.15:03:39.48#ibcon#read 6, iclass 17, count 0 2006.173.15:03:39.48#ibcon#end of sib2, iclass 17, count 0 2006.173.15:03:39.48#ibcon#*after write, iclass 17, count 0 2006.173.15:03:39.48#ibcon#*before return 0, iclass 17, count 0 2006.173.15:03:39.48#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.15:03:39.48#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.15:03:39.48#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.15:03:39.48#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.15:03:39.48$vck44/valo=5,734.99 2006.173.15:03:39.48#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.15:03:39.48#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.15:03:39.48#ibcon#ireg 17 cls_cnt 0 2006.173.15:03:39.48#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.15:03:39.48#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.15:03:39.48#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.15:03:39.48#ibcon#enter wrdev, iclass 19, count 0 2006.173.15:03:39.48#ibcon#first serial, iclass 19, count 0 2006.173.15:03:39.48#ibcon#enter sib2, iclass 19, count 0 2006.173.15:03:39.48#ibcon#flushed, iclass 19, count 0 2006.173.15:03:39.48#ibcon#about to write, iclass 19, count 0 2006.173.15:03:39.48#ibcon#wrote, iclass 19, count 0 2006.173.15:03:39.48#ibcon#about to read 3, iclass 19, count 0 2006.173.15:03:39.50#ibcon#read 3, iclass 19, count 0 2006.173.15:03:39.50#ibcon#about to read 4, iclass 19, count 0 2006.173.15:03:39.50#ibcon#read 4, iclass 19, count 0 2006.173.15:03:39.50#ibcon#about to read 5, iclass 19, count 0 2006.173.15:03:39.50#ibcon#read 5, iclass 19, count 0 2006.173.15:03:39.50#ibcon#about to read 6, iclass 19, count 0 2006.173.15:03:39.50#ibcon#read 6, iclass 19, count 0 2006.173.15:03:39.50#ibcon#end of sib2, iclass 19, count 0 2006.173.15:03:39.50#ibcon#*mode == 0, iclass 19, count 0 2006.173.15:03:39.50#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.15:03:39.50#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.15:03:39.50#ibcon#*before write, iclass 19, count 0 2006.173.15:03:39.50#ibcon#enter sib2, iclass 19, count 0 2006.173.15:03:39.50#ibcon#flushed, iclass 19, count 0 2006.173.15:03:39.50#ibcon#about to write, iclass 19, count 0 2006.173.15:03:39.50#ibcon#wrote, iclass 19, count 0 2006.173.15:03:39.50#ibcon#about to read 3, iclass 19, count 0 2006.173.15:03:39.54#ibcon#read 3, iclass 19, count 0 2006.173.15:03:39.54#ibcon#about to read 4, iclass 19, count 0 2006.173.15:03:39.54#ibcon#read 4, iclass 19, count 0 2006.173.15:03:39.54#ibcon#about to read 5, iclass 19, count 0 2006.173.15:03:39.54#ibcon#read 5, iclass 19, count 0 2006.173.15:03:39.54#ibcon#about to read 6, iclass 19, count 0 2006.173.15:03:39.54#ibcon#read 6, iclass 19, count 0 2006.173.15:03:39.54#ibcon#end of sib2, iclass 19, count 0 2006.173.15:03:39.54#ibcon#*after write, iclass 19, count 0 2006.173.15:03:39.54#ibcon#*before return 0, iclass 19, count 0 2006.173.15:03:39.54#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.15:03:39.54#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.15:03:39.54#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.15:03:39.54#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.15:03:39.54$vck44/va=5,4 2006.173.15:03:39.54#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.15:03:39.54#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.15:03:39.54#ibcon#ireg 11 cls_cnt 2 2006.173.15:03:39.54#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.15:03:39.60#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.15:03:39.60#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.15:03:39.60#ibcon#enter wrdev, iclass 21, count 2 2006.173.15:03:39.60#ibcon#first serial, iclass 21, count 2 2006.173.15:03:39.60#ibcon#enter sib2, iclass 21, count 2 2006.173.15:03:39.60#ibcon#flushed, iclass 21, count 2 2006.173.15:03:39.60#ibcon#about to write, iclass 21, count 2 2006.173.15:03:39.60#ibcon#wrote, iclass 21, count 2 2006.173.15:03:39.60#ibcon#about to read 3, iclass 21, count 2 2006.173.15:03:39.62#ibcon#read 3, iclass 21, count 2 2006.173.15:03:39.62#ibcon#about to read 4, iclass 21, count 2 2006.173.15:03:39.62#ibcon#read 4, iclass 21, count 2 2006.173.15:03:39.62#ibcon#about to read 5, iclass 21, count 2 2006.173.15:03:39.62#ibcon#read 5, iclass 21, count 2 2006.173.15:03:39.62#ibcon#about to read 6, iclass 21, count 2 2006.173.15:03:39.62#ibcon#read 6, iclass 21, count 2 2006.173.15:03:39.62#ibcon#end of sib2, iclass 21, count 2 2006.173.15:03:39.62#ibcon#*mode == 0, iclass 21, count 2 2006.173.15:03:39.62#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.15:03:39.62#ibcon#[25=AT05-04\r\n] 2006.173.15:03:39.62#ibcon#*before write, iclass 21, count 2 2006.173.15:03:39.62#ibcon#enter sib2, iclass 21, count 2 2006.173.15:03:39.62#ibcon#flushed, iclass 21, count 2 2006.173.15:03:39.62#ibcon#about to write, iclass 21, count 2 2006.173.15:03:39.62#ibcon#wrote, iclass 21, count 2 2006.173.15:03:39.62#ibcon#about to read 3, iclass 21, count 2 2006.173.15:03:39.65#ibcon#read 3, iclass 21, count 2 2006.173.15:03:39.65#ibcon#about to read 4, iclass 21, count 2 2006.173.15:03:39.65#ibcon#read 4, iclass 21, count 2 2006.173.15:03:39.65#ibcon#about to read 5, iclass 21, count 2 2006.173.15:03:39.65#ibcon#read 5, iclass 21, count 2 2006.173.15:03:39.65#ibcon#about to read 6, iclass 21, count 2 2006.173.15:03:39.65#ibcon#read 6, iclass 21, count 2 2006.173.15:03:39.65#ibcon#end of sib2, iclass 21, count 2 2006.173.15:03:39.65#ibcon#*after write, iclass 21, count 2 2006.173.15:03:39.65#ibcon#*before return 0, iclass 21, count 2 2006.173.15:03:39.65#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.15:03:39.65#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.15:03:39.65#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.15:03:39.65#ibcon#ireg 7 cls_cnt 0 2006.173.15:03:39.65#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.15:03:39.77#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.15:03:39.77#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.15:03:39.77#ibcon#enter wrdev, iclass 21, count 0 2006.173.15:03:39.77#ibcon#first serial, iclass 21, count 0 2006.173.15:03:39.77#ibcon#enter sib2, iclass 21, count 0 2006.173.15:03:39.77#ibcon#flushed, iclass 21, count 0 2006.173.15:03:39.77#ibcon#about to write, iclass 21, count 0 2006.173.15:03:39.77#ibcon#wrote, iclass 21, count 0 2006.173.15:03:39.77#ibcon#about to read 3, iclass 21, count 0 2006.173.15:03:39.79#ibcon#read 3, iclass 21, count 0 2006.173.15:03:39.79#ibcon#about to read 4, iclass 21, count 0 2006.173.15:03:39.79#ibcon#read 4, iclass 21, count 0 2006.173.15:03:39.79#ibcon#about to read 5, iclass 21, count 0 2006.173.15:03:39.79#ibcon#read 5, iclass 21, count 0 2006.173.15:03:39.79#ibcon#about to read 6, iclass 21, count 0 2006.173.15:03:39.79#ibcon#read 6, iclass 21, count 0 2006.173.15:03:39.79#ibcon#end of sib2, iclass 21, count 0 2006.173.15:03:39.79#ibcon#*mode == 0, iclass 21, count 0 2006.173.15:03:39.79#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.15:03:39.79#ibcon#[25=USB\r\n] 2006.173.15:03:39.79#ibcon#*before write, iclass 21, count 0 2006.173.15:03:39.79#ibcon#enter sib2, iclass 21, count 0 2006.173.15:03:39.79#ibcon#flushed, iclass 21, count 0 2006.173.15:03:39.79#ibcon#about to write, iclass 21, count 0 2006.173.15:03:39.79#ibcon#wrote, iclass 21, count 0 2006.173.15:03:39.79#ibcon#about to read 3, iclass 21, count 0 2006.173.15:03:39.82#ibcon#read 3, iclass 21, count 0 2006.173.15:03:39.82#ibcon#about to read 4, iclass 21, count 0 2006.173.15:03:39.82#ibcon#read 4, iclass 21, count 0 2006.173.15:03:39.82#ibcon#about to read 5, iclass 21, count 0 2006.173.15:03:39.82#ibcon#read 5, iclass 21, count 0 2006.173.15:03:39.82#ibcon#about to read 6, iclass 21, count 0 2006.173.15:03:39.82#ibcon#read 6, iclass 21, count 0 2006.173.15:03:39.82#ibcon#end of sib2, iclass 21, count 0 2006.173.15:03:39.82#ibcon#*after write, iclass 21, count 0 2006.173.15:03:39.82#ibcon#*before return 0, iclass 21, count 0 2006.173.15:03:39.82#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.15:03:39.82#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.15:03:39.82#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.15:03:39.82#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.15:03:39.82$vck44/valo=6,814.99 2006.173.15:03:39.82#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.15:03:39.82#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.15:03:39.82#ibcon#ireg 17 cls_cnt 0 2006.173.15:03:39.82#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.15:03:39.82#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.15:03:39.82#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.15:03:39.82#ibcon#enter wrdev, iclass 23, count 0 2006.173.15:03:39.82#ibcon#first serial, iclass 23, count 0 2006.173.15:03:39.82#ibcon#enter sib2, iclass 23, count 0 2006.173.15:03:39.82#ibcon#flushed, iclass 23, count 0 2006.173.15:03:39.82#ibcon#about to write, iclass 23, count 0 2006.173.15:03:39.82#ibcon#wrote, iclass 23, count 0 2006.173.15:03:39.82#ibcon#about to read 3, iclass 23, count 0 2006.173.15:03:39.84#ibcon#read 3, iclass 23, count 0 2006.173.15:03:39.84#ibcon#about to read 4, iclass 23, count 0 2006.173.15:03:39.84#ibcon#read 4, iclass 23, count 0 2006.173.15:03:39.84#ibcon#about to read 5, iclass 23, count 0 2006.173.15:03:39.84#ibcon#read 5, iclass 23, count 0 2006.173.15:03:39.84#ibcon#about to read 6, iclass 23, count 0 2006.173.15:03:39.84#ibcon#read 6, iclass 23, count 0 2006.173.15:03:39.84#ibcon#end of sib2, iclass 23, count 0 2006.173.15:03:39.84#ibcon#*mode == 0, iclass 23, count 0 2006.173.15:03:39.84#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.15:03:39.84#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.15:03:39.84#ibcon#*before write, iclass 23, count 0 2006.173.15:03:39.84#ibcon#enter sib2, iclass 23, count 0 2006.173.15:03:39.84#ibcon#flushed, iclass 23, count 0 2006.173.15:03:39.84#ibcon#about to write, iclass 23, count 0 2006.173.15:03:39.84#ibcon#wrote, iclass 23, count 0 2006.173.15:03:39.84#ibcon#about to read 3, iclass 23, count 0 2006.173.15:03:39.88#ibcon#read 3, iclass 23, count 0 2006.173.15:03:39.88#ibcon#about to read 4, iclass 23, count 0 2006.173.15:03:39.88#ibcon#read 4, iclass 23, count 0 2006.173.15:03:39.88#ibcon#about to read 5, iclass 23, count 0 2006.173.15:03:39.88#ibcon#read 5, iclass 23, count 0 2006.173.15:03:39.88#ibcon#about to read 6, iclass 23, count 0 2006.173.15:03:39.88#ibcon#read 6, iclass 23, count 0 2006.173.15:03:39.88#ibcon#end of sib2, iclass 23, count 0 2006.173.15:03:39.88#ibcon#*after write, iclass 23, count 0 2006.173.15:03:39.88#ibcon#*before return 0, iclass 23, count 0 2006.173.15:03:39.88#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.15:03:39.88#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.15:03:39.88#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.15:03:39.88#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.15:03:39.88$vck44/va=6,3 2006.173.15:03:39.88#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.15:03:39.88#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.15:03:39.88#ibcon#ireg 11 cls_cnt 2 2006.173.15:03:39.88#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.15:03:39.94#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.15:03:39.94#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.15:03:39.94#ibcon#enter wrdev, iclass 25, count 2 2006.173.15:03:39.94#ibcon#first serial, iclass 25, count 2 2006.173.15:03:39.94#ibcon#enter sib2, iclass 25, count 2 2006.173.15:03:39.94#ibcon#flushed, iclass 25, count 2 2006.173.15:03:39.94#ibcon#about to write, iclass 25, count 2 2006.173.15:03:39.94#ibcon#wrote, iclass 25, count 2 2006.173.15:03:39.94#ibcon#about to read 3, iclass 25, count 2 2006.173.15:03:39.96#ibcon#read 3, iclass 25, count 2 2006.173.15:03:39.96#ibcon#about to read 4, iclass 25, count 2 2006.173.15:03:39.96#ibcon#read 4, iclass 25, count 2 2006.173.15:03:39.96#ibcon#about to read 5, iclass 25, count 2 2006.173.15:03:39.96#ibcon#read 5, iclass 25, count 2 2006.173.15:03:39.96#ibcon#about to read 6, iclass 25, count 2 2006.173.15:03:39.96#ibcon#read 6, iclass 25, count 2 2006.173.15:03:39.96#ibcon#end of sib2, iclass 25, count 2 2006.173.15:03:39.96#ibcon#*mode == 0, iclass 25, count 2 2006.173.15:03:39.96#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.15:03:39.96#ibcon#[25=AT06-03\r\n] 2006.173.15:03:39.96#ibcon#*before write, iclass 25, count 2 2006.173.15:03:39.96#ibcon#enter sib2, iclass 25, count 2 2006.173.15:03:39.96#ibcon#flushed, iclass 25, count 2 2006.173.15:03:39.96#ibcon#about to write, iclass 25, count 2 2006.173.15:03:39.96#ibcon#wrote, iclass 25, count 2 2006.173.15:03:39.96#ibcon#about to read 3, iclass 25, count 2 2006.173.15:03:39.99#ibcon#read 3, iclass 25, count 2 2006.173.15:03:39.99#ibcon#about to read 4, iclass 25, count 2 2006.173.15:03:39.99#ibcon#read 4, iclass 25, count 2 2006.173.15:03:39.99#ibcon#about to read 5, iclass 25, count 2 2006.173.15:03:39.99#ibcon#read 5, iclass 25, count 2 2006.173.15:03:39.99#ibcon#about to read 6, iclass 25, count 2 2006.173.15:03:39.99#ibcon#read 6, iclass 25, count 2 2006.173.15:03:39.99#ibcon#end of sib2, iclass 25, count 2 2006.173.15:03:39.99#ibcon#*after write, iclass 25, count 2 2006.173.15:03:39.99#ibcon#*before return 0, iclass 25, count 2 2006.173.15:03:39.99#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.15:03:39.99#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.15:03:39.99#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.15:03:39.99#ibcon#ireg 7 cls_cnt 0 2006.173.15:03:39.99#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.15:03:40.11#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.15:03:40.11#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.15:03:40.11#ibcon#enter wrdev, iclass 25, count 0 2006.173.15:03:40.11#ibcon#first serial, iclass 25, count 0 2006.173.15:03:40.11#ibcon#enter sib2, iclass 25, count 0 2006.173.15:03:40.11#ibcon#flushed, iclass 25, count 0 2006.173.15:03:40.11#ibcon#about to write, iclass 25, count 0 2006.173.15:03:40.11#ibcon#wrote, iclass 25, count 0 2006.173.15:03:40.11#ibcon#about to read 3, iclass 25, count 0 2006.173.15:03:40.13#ibcon#read 3, iclass 25, count 0 2006.173.15:03:40.13#ibcon#about to read 4, iclass 25, count 0 2006.173.15:03:40.13#ibcon#read 4, iclass 25, count 0 2006.173.15:03:40.13#ibcon#about to read 5, iclass 25, count 0 2006.173.15:03:40.13#ibcon#read 5, iclass 25, count 0 2006.173.15:03:40.13#ibcon#about to read 6, iclass 25, count 0 2006.173.15:03:40.13#ibcon#read 6, iclass 25, count 0 2006.173.15:03:40.13#ibcon#end of sib2, iclass 25, count 0 2006.173.15:03:40.13#ibcon#*mode == 0, iclass 25, count 0 2006.173.15:03:40.13#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.15:03:40.13#ibcon#[25=USB\r\n] 2006.173.15:03:40.13#ibcon#*before write, iclass 25, count 0 2006.173.15:03:40.13#ibcon#enter sib2, iclass 25, count 0 2006.173.15:03:40.13#ibcon#flushed, iclass 25, count 0 2006.173.15:03:40.13#ibcon#about to write, iclass 25, count 0 2006.173.15:03:40.13#ibcon#wrote, iclass 25, count 0 2006.173.15:03:40.13#ibcon#about to read 3, iclass 25, count 0 2006.173.15:03:40.16#ibcon#read 3, iclass 25, count 0 2006.173.15:03:40.16#ibcon#about to read 4, iclass 25, count 0 2006.173.15:03:40.16#ibcon#read 4, iclass 25, count 0 2006.173.15:03:40.16#ibcon#about to read 5, iclass 25, count 0 2006.173.15:03:40.16#ibcon#read 5, iclass 25, count 0 2006.173.15:03:40.16#ibcon#about to read 6, iclass 25, count 0 2006.173.15:03:40.16#ibcon#read 6, iclass 25, count 0 2006.173.15:03:40.16#ibcon#end of sib2, iclass 25, count 0 2006.173.15:03:40.16#ibcon#*after write, iclass 25, count 0 2006.173.15:03:40.16#ibcon#*before return 0, iclass 25, count 0 2006.173.15:03:40.16#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.15:03:40.16#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.15:03:40.16#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.15:03:40.16#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.15:03:40.16$vck44/valo=7,864.99 2006.173.15:03:40.16#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.15:03:40.16#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.15:03:40.16#ibcon#ireg 17 cls_cnt 0 2006.173.15:03:40.16#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.15:03:40.16#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.15:03:40.16#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.15:03:40.16#ibcon#enter wrdev, iclass 27, count 0 2006.173.15:03:40.16#ibcon#first serial, iclass 27, count 0 2006.173.15:03:40.16#ibcon#enter sib2, iclass 27, count 0 2006.173.15:03:40.16#ibcon#flushed, iclass 27, count 0 2006.173.15:03:40.16#ibcon#about to write, iclass 27, count 0 2006.173.15:03:40.16#ibcon#wrote, iclass 27, count 0 2006.173.15:03:40.16#ibcon#about to read 3, iclass 27, count 0 2006.173.15:03:40.18#ibcon#read 3, iclass 27, count 0 2006.173.15:03:40.18#ibcon#about to read 4, iclass 27, count 0 2006.173.15:03:40.18#ibcon#read 4, iclass 27, count 0 2006.173.15:03:40.18#ibcon#about to read 5, iclass 27, count 0 2006.173.15:03:40.18#ibcon#read 5, iclass 27, count 0 2006.173.15:03:40.18#ibcon#about to read 6, iclass 27, count 0 2006.173.15:03:40.18#ibcon#read 6, iclass 27, count 0 2006.173.15:03:40.18#ibcon#end of sib2, iclass 27, count 0 2006.173.15:03:40.18#ibcon#*mode == 0, iclass 27, count 0 2006.173.15:03:40.18#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.15:03:40.18#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.15:03:40.18#ibcon#*before write, iclass 27, count 0 2006.173.15:03:40.18#ibcon#enter sib2, iclass 27, count 0 2006.173.15:03:40.18#ibcon#flushed, iclass 27, count 0 2006.173.15:03:40.18#ibcon#about to write, iclass 27, count 0 2006.173.15:03:40.18#ibcon#wrote, iclass 27, count 0 2006.173.15:03:40.18#ibcon#about to read 3, iclass 27, count 0 2006.173.15:03:40.22#ibcon#read 3, iclass 27, count 0 2006.173.15:03:40.22#ibcon#about to read 4, iclass 27, count 0 2006.173.15:03:40.22#ibcon#read 4, iclass 27, count 0 2006.173.15:03:40.22#ibcon#about to read 5, iclass 27, count 0 2006.173.15:03:40.22#ibcon#read 5, iclass 27, count 0 2006.173.15:03:40.22#ibcon#about to read 6, iclass 27, count 0 2006.173.15:03:40.22#ibcon#read 6, iclass 27, count 0 2006.173.15:03:40.22#ibcon#end of sib2, iclass 27, count 0 2006.173.15:03:40.22#ibcon#*after write, iclass 27, count 0 2006.173.15:03:40.22#ibcon#*before return 0, iclass 27, count 0 2006.173.15:03:40.22#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.15:03:40.22#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.15:03:40.22#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.15:03:40.22#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.15:03:40.22$vck44/va=7,4 2006.173.15:03:40.22#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.15:03:40.22#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.15:03:40.22#ibcon#ireg 11 cls_cnt 2 2006.173.15:03:40.22#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.15:03:40.28#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.15:03:40.28#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.15:03:40.28#ibcon#enter wrdev, iclass 29, count 2 2006.173.15:03:40.28#ibcon#first serial, iclass 29, count 2 2006.173.15:03:40.28#ibcon#enter sib2, iclass 29, count 2 2006.173.15:03:40.28#ibcon#flushed, iclass 29, count 2 2006.173.15:03:40.28#ibcon#about to write, iclass 29, count 2 2006.173.15:03:40.28#ibcon#wrote, iclass 29, count 2 2006.173.15:03:40.28#ibcon#about to read 3, iclass 29, count 2 2006.173.15:03:40.30#ibcon#read 3, iclass 29, count 2 2006.173.15:03:40.30#ibcon#about to read 4, iclass 29, count 2 2006.173.15:03:40.30#ibcon#read 4, iclass 29, count 2 2006.173.15:03:40.30#ibcon#about to read 5, iclass 29, count 2 2006.173.15:03:40.30#ibcon#read 5, iclass 29, count 2 2006.173.15:03:40.30#ibcon#about to read 6, iclass 29, count 2 2006.173.15:03:40.30#ibcon#read 6, iclass 29, count 2 2006.173.15:03:40.30#ibcon#end of sib2, iclass 29, count 2 2006.173.15:03:40.30#ibcon#*mode == 0, iclass 29, count 2 2006.173.15:03:40.30#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.15:03:40.30#ibcon#[25=AT07-04\r\n] 2006.173.15:03:40.30#ibcon#*before write, iclass 29, count 2 2006.173.15:03:40.30#ibcon#enter sib2, iclass 29, count 2 2006.173.15:03:40.30#ibcon#flushed, iclass 29, count 2 2006.173.15:03:40.30#ibcon#about to write, iclass 29, count 2 2006.173.15:03:40.30#ibcon#wrote, iclass 29, count 2 2006.173.15:03:40.30#ibcon#about to read 3, iclass 29, count 2 2006.173.15:03:40.33#ibcon#read 3, iclass 29, count 2 2006.173.15:03:40.38#ibcon#about to read 4, iclass 29, count 2 2006.173.15:03:40.38#ibcon#read 4, iclass 29, count 2 2006.173.15:03:40.38#ibcon#about to read 5, iclass 29, count 2 2006.173.15:03:40.38#ibcon#read 5, iclass 29, count 2 2006.173.15:03:40.38#ibcon#about to read 6, iclass 29, count 2 2006.173.15:03:40.38#ibcon#read 6, iclass 29, count 2 2006.173.15:03:40.38#ibcon#end of sib2, iclass 29, count 2 2006.173.15:03:40.38#ibcon#*after write, iclass 29, count 2 2006.173.15:03:40.38#ibcon#*before return 0, iclass 29, count 2 2006.173.15:03:40.38#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.15:03:40.38#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.15:03:40.38#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.15:03:40.38#ibcon#ireg 7 cls_cnt 0 2006.173.15:03:40.38#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.15:03:40.49#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.15:03:40.49#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.15:03:40.49#ibcon#enter wrdev, iclass 29, count 0 2006.173.15:03:40.49#ibcon#first serial, iclass 29, count 0 2006.173.15:03:40.49#ibcon#enter sib2, iclass 29, count 0 2006.173.15:03:40.49#ibcon#flushed, iclass 29, count 0 2006.173.15:03:40.49#ibcon#about to write, iclass 29, count 0 2006.173.15:03:40.49#ibcon#wrote, iclass 29, count 0 2006.173.15:03:40.49#ibcon#about to read 3, iclass 29, count 0 2006.173.15:03:40.51#ibcon#read 3, iclass 29, count 0 2006.173.15:03:40.51#ibcon#about to read 4, iclass 29, count 0 2006.173.15:03:40.51#ibcon#read 4, iclass 29, count 0 2006.173.15:03:40.51#ibcon#about to read 5, iclass 29, count 0 2006.173.15:03:40.51#ibcon#read 5, iclass 29, count 0 2006.173.15:03:40.51#ibcon#about to read 6, iclass 29, count 0 2006.173.15:03:40.51#ibcon#read 6, iclass 29, count 0 2006.173.15:03:40.51#ibcon#end of sib2, iclass 29, count 0 2006.173.15:03:40.51#ibcon#*mode == 0, iclass 29, count 0 2006.173.15:03:40.51#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.15:03:40.51#ibcon#[25=USB\r\n] 2006.173.15:03:40.51#ibcon#*before write, iclass 29, count 0 2006.173.15:03:40.51#ibcon#enter sib2, iclass 29, count 0 2006.173.15:03:40.51#ibcon#flushed, iclass 29, count 0 2006.173.15:03:40.51#ibcon#about to write, iclass 29, count 0 2006.173.15:03:40.51#ibcon#wrote, iclass 29, count 0 2006.173.15:03:40.51#ibcon#about to read 3, iclass 29, count 0 2006.173.15:03:40.54#ibcon#read 3, iclass 29, count 0 2006.173.15:03:40.54#ibcon#about to read 4, iclass 29, count 0 2006.173.15:03:40.54#ibcon#read 4, iclass 29, count 0 2006.173.15:03:40.54#ibcon#about to read 5, iclass 29, count 0 2006.173.15:03:40.54#ibcon#read 5, iclass 29, count 0 2006.173.15:03:40.54#ibcon#about to read 6, iclass 29, count 0 2006.173.15:03:40.54#ibcon#read 6, iclass 29, count 0 2006.173.15:03:40.54#ibcon#end of sib2, iclass 29, count 0 2006.173.15:03:40.54#ibcon#*after write, iclass 29, count 0 2006.173.15:03:40.54#ibcon#*before return 0, iclass 29, count 0 2006.173.15:03:40.54#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.15:03:40.54#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.15:03:40.54#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.15:03:40.54#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.15:03:40.54$vck44/valo=8,884.99 2006.173.15:03:40.54#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.15:03:40.54#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.15:03:40.54#ibcon#ireg 17 cls_cnt 0 2006.173.15:03:40.54#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.15:03:40.54#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.15:03:40.54#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.15:03:40.54#ibcon#enter wrdev, iclass 31, count 0 2006.173.15:03:40.54#ibcon#first serial, iclass 31, count 0 2006.173.15:03:40.54#ibcon#enter sib2, iclass 31, count 0 2006.173.15:03:40.54#ibcon#flushed, iclass 31, count 0 2006.173.15:03:40.54#ibcon#about to write, iclass 31, count 0 2006.173.15:03:40.54#ibcon#wrote, iclass 31, count 0 2006.173.15:03:40.54#ibcon#about to read 3, iclass 31, count 0 2006.173.15:03:40.56#ibcon#read 3, iclass 31, count 0 2006.173.15:03:40.56#ibcon#about to read 4, iclass 31, count 0 2006.173.15:03:40.56#ibcon#read 4, iclass 31, count 0 2006.173.15:03:40.56#ibcon#about to read 5, iclass 31, count 0 2006.173.15:03:40.56#ibcon#read 5, iclass 31, count 0 2006.173.15:03:40.56#ibcon#about to read 6, iclass 31, count 0 2006.173.15:03:40.56#ibcon#read 6, iclass 31, count 0 2006.173.15:03:40.56#ibcon#end of sib2, iclass 31, count 0 2006.173.15:03:40.56#ibcon#*mode == 0, iclass 31, count 0 2006.173.15:03:40.56#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.15:03:40.56#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.15:03:40.56#ibcon#*before write, iclass 31, count 0 2006.173.15:03:40.56#ibcon#enter sib2, iclass 31, count 0 2006.173.15:03:40.56#ibcon#flushed, iclass 31, count 0 2006.173.15:03:40.56#ibcon#about to write, iclass 31, count 0 2006.173.15:03:40.56#ibcon#wrote, iclass 31, count 0 2006.173.15:03:40.56#ibcon#about to read 3, iclass 31, count 0 2006.173.15:03:40.60#ibcon#read 3, iclass 31, count 0 2006.173.15:03:40.60#ibcon#about to read 4, iclass 31, count 0 2006.173.15:03:40.60#ibcon#read 4, iclass 31, count 0 2006.173.15:03:40.60#ibcon#about to read 5, iclass 31, count 0 2006.173.15:03:40.60#ibcon#read 5, iclass 31, count 0 2006.173.15:03:40.60#ibcon#about to read 6, iclass 31, count 0 2006.173.15:03:40.60#ibcon#read 6, iclass 31, count 0 2006.173.15:03:40.60#ibcon#end of sib2, iclass 31, count 0 2006.173.15:03:40.60#ibcon#*after write, iclass 31, count 0 2006.173.15:03:40.60#ibcon#*before return 0, iclass 31, count 0 2006.173.15:03:40.60#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.15:03:40.60#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.15:03:40.60#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.15:03:40.60#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.15:03:40.60$vck44/va=8,4 2006.173.15:03:40.60#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.173.15:03:40.60#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.173.15:03:40.60#ibcon#ireg 11 cls_cnt 2 2006.173.15:03:40.60#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.15:03:40.66#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.15:03:40.66#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.15:03:40.66#ibcon#enter wrdev, iclass 33, count 2 2006.173.15:03:40.66#ibcon#first serial, iclass 33, count 2 2006.173.15:03:40.66#ibcon#enter sib2, iclass 33, count 2 2006.173.15:03:40.66#ibcon#flushed, iclass 33, count 2 2006.173.15:03:40.66#ibcon#about to write, iclass 33, count 2 2006.173.15:03:40.66#ibcon#wrote, iclass 33, count 2 2006.173.15:03:40.66#ibcon#about to read 3, iclass 33, count 2 2006.173.15:03:40.68#ibcon#read 3, iclass 33, count 2 2006.173.15:03:40.68#ibcon#about to read 4, iclass 33, count 2 2006.173.15:03:40.68#ibcon#read 4, iclass 33, count 2 2006.173.15:03:40.68#ibcon#about to read 5, iclass 33, count 2 2006.173.15:03:40.68#ibcon#read 5, iclass 33, count 2 2006.173.15:03:40.68#ibcon#about to read 6, iclass 33, count 2 2006.173.15:03:40.68#ibcon#read 6, iclass 33, count 2 2006.173.15:03:40.68#ibcon#end of sib2, iclass 33, count 2 2006.173.15:03:40.68#ibcon#*mode == 0, iclass 33, count 2 2006.173.15:03:40.68#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.173.15:03:40.68#ibcon#[25=AT08-04\r\n] 2006.173.15:03:40.68#ibcon#*before write, iclass 33, count 2 2006.173.15:03:40.68#ibcon#enter sib2, iclass 33, count 2 2006.173.15:03:40.68#ibcon#flushed, iclass 33, count 2 2006.173.15:03:40.68#ibcon#about to write, iclass 33, count 2 2006.173.15:03:40.68#ibcon#wrote, iclass 33, count 2 2006.173.15:03:40.68#ibcon#about to read 3, iclass 33, count 2 2006.173.15:03:40.71#ibcon#read 3, iclass 33, count 2 2006.173.15:03:40.71#ibcon#about to read 4, iclass 33, count 2 2006.173.15:03:40.71#ibcon#read 4, iclass 33, count 2 2006.173.15:03:40.71#ibcon#about to read 5, iclass 33, count 2 2006.173.15:03:40.71#ibcon#read 5, iclass 33, count 2 2006.173.15:03:40.71#ibcon#about to read 6, iclass 33, count 2 2006.173.15:03:40.71#ibcon#read 6, iclass 33, count 2 2006.173.15:03:40.71#ibcon#end of sib2, iclass 33, count 2 2006.173.15:03:40.71#ibcon#*after write, iclass 33, count 2 2006.173.15:03:40.71#ibcon#*before return 0, iclass 33, count 2 2006.173.15:03:40.71#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.15:03:40.71#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.173.15:03:40.71#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.173.15:03:40.71#ibcon#ireg 7 cls_cnt 0 2006.173.15:03:40.71#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.15:03:40.83#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.15:03:40.83#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.15:03:40.83#ibcon#enter wrdev, iclass 33, count 0 2006.173.15:03:40.83#ibcon#first serial, iclass 33, count 0 2006.173.15:03:40.83#ibcon#enter sib2, iclass 33, count 0 2006.173.15:03:40.83#ibcon#flushed, iclass 33, count 0 2006.173.15:03:40.83#ibcon#about to write, iclass 33, count 0 2006.173.15:03:40.83#ibcon#wrote, iclass 33, count 0 2006.173.15:03:40.83#ibcon#about to read 3, iclass 33, count 0 2006.173.15:03:40.85#ibcon#read 3, iclass 33, count 0 2006.173.15:03:40.85#ibcon#about to read 4, iclass 33, count 0 2006.173.15:03:40.85#ibcon#read 4, iclass 33, count 0 2006.173.15:03:40.85#ibcon#about to read 5, iclass 33, count 0 2006.173.15:03:40.85#ibcon#read 5, iclass 33, count 0 2006.173.15:03:40.85#ibcon#about to read 6, iclass 33, count 0 2006.173.15:03:40.85#ibcon#read 6, iclass 33, count 0 2006.173.15:03:40.85#ibcon#end of sib2, iclass 33, count 0 2006.173.15:03:40.85#ibcon#*mode == 0, iclass 33, count 0 2006.173.15:03:40.85#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.15:03:40.85#ibcon#[25=USB\r\n] 2006.173.15:03:40.85#ibcon#*before write, iclass 33, count 0 2006.173.15:03:40.85#ibcon#enter sib2, iclass 33, count 0 2006.173.15:03:40.85#ibcon#flushed, iclass 33, count 0 2006.173.15:03:40.85#ibcon#about to write, iclass 33, count 0 2006.173.15:03:40.85#ibcon#wrote, iclass 33, count 0 2006.173.15:03:40.85#ibcon#about to read 3, iclass 33, count 0 2006.173.15:03:40.88#ibcon#read 3, iclass 33, count 0 2006.173.15:03:40.88#ibcon#about to read 4, iclass 33, count 0 2006.173.15:03:40.88#ibcon#read 4, iclass 33, count 0 2006.173.15:03:40.88#ibcon#about to read 5, iclass 33, count 0 2006.173.15:03:40.88#ibcon#read 5, iclass 33, count 0 2006.173.15:03:40.88#ibcon#about to read 6, iclass 33, count 0 2006.173.15:03:40.88#ibcon#read 6, iclass 33, count 0 2006.173.15:03:40.88#ibcon#end of sib2, iclass 33, count 0 2006.173.15:03:40.88#ibcon#*after write, iclass 33, count 0 2006.173.15:03:40.88#ibcon#*before return 0, iclass 33, count 0 2006.173.15:03:40.88#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.15:03:40.88#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.173.15:03:40.88#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.15:03:40.88#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.15:03:40.88$vck44/vblo=1,629.99 2006.173.15:03:40.88#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.15:03:40.88#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.15:03:40.88#ibcon#ireg 17 cls_cnt 0 2006.173.15:03:40.88#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.15:03:40.88#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.15:03:40.88#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.15:03:40.88#ibcon#enter wrdev, iclass 35, count 0 2006.173.15:03:40.88#ibcon#first serial, iclass 35, count 0 2006.173.15:03:40.88#ibcon#enter sib2, iclass 35, count 0 2006.173.15:03:40.88#ibcon#flushed, iclass 35, count 0 2006.173.15:03:40.88#ibcon#about to write, iclass 35, count 0 2006.173.15:03:40.88#ibcon#wrote, iclass 35, count 0 2006.173.15:03:40.88#ibcon#about to read 3, iclass 35, count 0 2006.173.15:03:40.90#ibcon#read 3, iclass 35, count 0 2006.173.15:03:40.90#ibcon#about to read 4, iclass 35, count 0 2006.173.15:03:40.90#ibcon#read 4, iclass 35, count 0 2006.173.15:03:40.90#ibcon#about to read 5, iclass 35, count 0 2006.173.15:03:40.90#ibcon#read 5, iclass 35, count 0 2006.173.15:03:40.90#ibcon#about to read 6, iclass 35, count 0 2006.173.15:03:40.90#ibcon#read 6, iclass 35, count 0 2006.173.15:03:40.90#ibcon#end of sib2, iclass 35, count 0 2006.173.15:03:40.90#ibcon#*mode == 0, iclass 35, count 0 2006.173.15:03:40.90#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.15:03:40.90#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.15:03:40.90#ibcon#*before write, iclass 35, count 0 2006.173.15:03:40.90#ibcon#enter sib2, iclass 35, count 0 2006.173.15:03:40.90#ibcon#flushed, iclass 35, count 0 2006.173.15:03:40.90#ibcon#about to write, iclass 35, count 0 2006.173.15:03:40.90#ibcon#wrote, iclass 35, count 0 2006.173.15:03:40.90#ibcon#about to read 3, iclass 35, count 0 2006.173.15:03:40.94#ibcon#read 3, iclass 35, count 0 2006.173.15:03:40.94#ibcon#about to read 4, iclass 35, count 0 2006.173.15:03:40.94#ibcon#read 4, iclass 35, count 0 2006.173.15:03:40.94#ibcon#about to read 5, iclass 35, count 0 2006.173.15:03:40.94#ibcon#read 5, iclass 35, count 0 2006.173.15:03:40.94#ibcon#about to read 6, iclass 35, count 0 2006.173.15:03:40.94#ibcon#read 6, iclass 35, count 0 2006.173.15:03:40.94#ibcon#end of sib2, iclass 35, count 0 2006.173.15:03:40.94#ibcon#*after write, iclass 35, count 0 2006.173.15:03:40.94#ibcon#*before return 0, iclass 35, count 0 2006.173.15:03:40.94#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.15:03:40.94#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.15:03:40.94#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.15:03:40.94#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.15:03:40.94$vck44/vb=1,4 2006.173.15:03:40.94#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.173.15:03:40.94#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.173.15:03:40.94#ibcon#ireg 11 cls_cnt 2 2006.173.15:03:40.94#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.15:03:40.94#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.15:03:40.94#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.15:03:40.94#ibcon#enter wrdev, iclass 37, count 2 2006.173.15:03:40.94#ibcon#first serial, iclass 37, count 2 2006.173.15:03:40.94#ibcon#enter sib2, iclass 37, count 2 2006.173.15:03:40.94#ibcon#flushed, iclass 37, count 2 2006.173.15:03:40.94#ibcon#about to write, iclass 37, count 2 2006.173.15:03:40.94#ibcon#wrote, iclass 37, count 2 2006.173.15:03:40.94#ibcon#about to read 3, iclass 37, count 2 2006.173.15:03:40.96#ibcon#read 3, iclass 37, count 2 2006.173.15:03:40.96#ibcon#about to read 4, iclass 37, count 2 2006.173.15:03:40.96#ibcon#read 4, iclass 37, count 2 2006.173.15:03:40.96#ibcon#about to read 5, iclass 37, count 2 2006.173.15:03:40.96#ibcon#read 5, iclass 37, count 2 2006.173.15:03:40.96#ibcon#about to read 6, iclass 37, count 2 2006.173.15:03:40.96#ibcon#read 6, iclass 37, count 2 2006.173.15:03:40.96#ibcon#end of sib2, iclass 37, count 2 2006.173.15:03:40.96#ibcon#*mode == 0, iclass 37, count 2 2006.173.15:03:40.96#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.173.15:03:40.96#ibcon#[27=AT01-04\r\n] 2006.173.15:03:40.96#ibcon#*before write, iclass 37, count 2 2006.173.15:03:40.96#ibcon#enter sib2, iclass 37, count 2 2006.173.15:03:40.96#ibcon#flushed, iclass 37, count 2 2006.173.15:03:40.96#ibcon#about to write, iclass 37, count 2 2006.173.15:03:40.96#ibcon#wrote, iclass 37, count 2 2006.173.15:03:40.96#ibcon#about to read 3, iclass 37, count 2 2006.173.15:03:40.99#ibcon#read 3, iclass 37, count 2 2006.173.15:03:40.99#ibcon#about to read 4, iclass 37, count 2 2006.173.15:03:40.99#ibcon#read 4, iclass 37, count 2 2006.173.15:03:40.99#ibcon#about to read 5, iclass 37, count 2 2006.173.15:03:40.99#ibcon#read 5, iclass 37, count 2 2006.173.15:03:40.99#ibcon#about to read 6, iclass 37, count 2 2006.173.15:03:40.99#ibcon#read 6, iclass 37, count 2 2006.173.15:03:40.99#ibcon#end of sib2, iclass 37, count 2 2006.173.15:03:40.99#ibcon#*after write, iclass 37, count 2 2006.173.15:03:40.99#ibcon#*before return 0, iclass 37, count 2 2006.173.15:03:40.99#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.15:03:40.99#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.173.15:03:40.99#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.173.15:03:40.99#ibcon#ireg 7 cls_cnt 0 2006.173.15:03:40.99#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.15:03:41.11#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.15:03:41.11#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.15:03:41.11#ibcon#enter wrdev, iclass 37, count 0 2006.173.15:03:41.11#ibcon#first serial, iclass 37, count 0 2006.173.15:03:41.11#ibcon#enter sib2, iclass 37, count 0 2006.173.15:03:41.11#ibcon#flushed, iclass 37, count 0 2006.173.15:03:41.11#ibcon#about to write, iclass 37, count 0 2006.173.15:03:41.11#ibcon#wrote, iclass 37, count 0 2006.173.15:03:41.11#ibcon#about to read 3, iclass 37, count 0 2006.173.15:03:41.13#ibcon#read 3, iclass 37, count 0 2006.173.15:03:41.13#ibcon#about to read 4, iclass 37, count 0 2006.173.15:03:41.13#ibcon#read 4, iclass 37, count 0 2006.173.15:03:41.13#ibcon#about to read 5, iclass 37, count 0 2006.173.15:03:41.13#ibcon#read 5, iclass 37, count 0 2006.173.15:03:41.13#ibcon#about to read 6, iclass 37, count 0 2006.173.15:03:41.13#ibcon#read 6, iclass 37, count 0 2006.173.15:03:41.13#ibcon#end of sib2, iclass 37, count 0 2006.173.15:03:41.13#ibcon#*mode == 0, iclass 37, count 0 2006.173.15:03:41.13#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.15:03:41.13#ibcon#[27=USB\r\n] 2006.173.15:03:41.13#ibcon#*before write, iclass 37, count 0 2006.173.15:03:41.13#ibcon#enter sib2, iclass 37, count 0 2006.173.15:03:41.13#ibcon#flushed, iclass 37, count 0 2006.173.15:03:41.13#ibcon#about to write, iclass 37, count 0 2006.173.15:03:41.13#ibcon#wrote, iclass 37, count 0 2006.173.15:03:41.13#ibcon#about to read 3, iclass 37, count 0 2006.173.15:03:41.16#ibcon#read 3, iclass 37, count 0 2006.173.15:03:41.16#ibcon#about to read 4, iclass 37, count 0 2006.173.15:03:41.16#ibcon#read 4, iclass 37, count 0 2006.173.15:03:41.16#ibcon#about to read 5, iclass 37, count 0 2006.173.15:03:41.16#ibcon#read 5, iclass 37, count 0 2006.173.15:03:41.16#ibcon#about to read 6, iclass 37, count 0 2006.173.15:03:41.16#ibcon#read 6, iclass 37, count 0 2006.173.15:03:41.16#ibcon#end of sib2, iclass 37, count 0 2006.173.15:03:41.16#ibcon#*after write, iclass 37, count 0 2006.173.15:03:41.16#ibcon#*before return 0, iclass 37, count 0 2006.173.15:03:41.16#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.15:03:41.16#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.173.15:03:41.16#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.15:03:41.16#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.15:03:41.16$vck44/vblo=2,634.99 2006.173.15:03:41.16#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.15:03:41.16#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.15:03:41.16#ibcon#ireg 17 cls_cnt 0 2006.173.15:03:41.16#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.15:03:41.16#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.15:03:41.16#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.15:03:41.16#ibcon#enter wrdev, iclass 39, count 0 2006.173.15:03:41.16#ibcon#first serial, iclass 39, count 0 2006.173.15:03:41.16#ibcon#enter sib2, iclass 39, count 0 2006.173.15:03:41.16#ibcon#flushed, iclass 39, count 0 2006.173.15:03:41.16#ibcon#about to write, iclass 39, count 0 2006.173.15:03:41.16#ibcon#wrote, iclass 39, count 0 2006.173.15:03:41.16#ibcon#about to read 3, iclass 39, count 0 2006.173.15:03:41.18#ibcon#read 3, iclass 39, count 0 2006.173.15:03:41.18#ibcon#about to read 4, iclass 39, count 0 2006.173.15:03:41.18#ibcon#read 4, iclass 39, count 0 2006.173.15:03:41.18#ibcon#about to read 5, iclass 39, count 0 2006.173.15:03:41.18#ibcon#read 5, iclass 39, count 0 2006.173.15:03:41.18#ibcon#about to read 6, iclass 39, count 0 2006.173.15:03:41.18#ibcon#read 6, iclass 39, count 0 2006.173.15:03:41.18#ibcon#end of sib2, iclass 39, count 0 2006.173.15:03:41.18#ibcon#*mode == 0, iclass 39, count 0 2006.173.15:03:41.18#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.15:03:41.18#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.15:03:41.18#ibcon#*before write, iclass 39, count 0 2006.173.15:03:41.18#ibcon#enter sib2, iclass 39, count 0 2006.173.15:03:41.18#ibcon#flushed, iclass 39, count 0 2006.173.15:03:41.18#ibcon#about to write, iclass 39, count 0 2006.173.15:03:41.18#ibcon#wrote, iclass 39, count 0 2006.173.15:03:41.18#ibcon#about to read 3, iclass 39, count 0 2006.173.15:03:41.22#ibcon#read 3, iclass 39, count 0 2006.173.15:03:41.22#ibcon#about to read 4, iclass 39, count 0 2006.173.15:03:41.22#ibcon#read 4, iclass 39, count 0 2006.173.15:03:41.22#ibcon#about to read 5, iclass 39, count 0 2006.173.15:03:41.22#ibcon#read 5, iclass 39, count 0 2006.173.15:03:41.22#ibcon#about to read 6, iclass 39, count 0 2006.173.15:03:41.22#ibcon#read 6, iclass 39, count 0 2006.173.15:03:41.22#ibcon#end of sib2, iclass 39, count 0 2006.173.15:03:41.22#ibcon#*after write, iclass 39, count 0 2006.173.15:03:41.22#ibcon#*before return 0, iclass 39, count 0 2006.173.15:03:41.22#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.15:03:41.22#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.15:03:41.22#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.15:03:41.22#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.15:03:41.22$vck44/vb=2,4 2006.173.15:03:41.22#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.15:03:41.22#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.15:03:41.22#ibcon#ireg 11 cls_cnt 2 2006.173.15:03:41.22#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.15:03:41.28#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.15:03:41.28#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.15:03:41.28#ibcon#enter wrdev, iclass 3, count 2 2006.173.15:03:41.28#ibcon#first serial, iclass 3, count 2 2006.173.15:03:41.28#ibcon#enter sib2, iclass 3, count 2 2006.173.15:03:41.28#ibcon#flushed, iclass 3, count 2 2006.173.15:03:41.28#ibcon#about to write, iclass 3, count 2 2006.173.15:03:41.28#ibcon#wrote, iclass 3, count 2 2006.173.15:03:41.28#ibcon#about to read 3, iclass 3, count 2 2006.173.15:03:41.30#ibcon#read 3, iclass 3, count 2 2006.173.15:03:41.30#ibcon#about to read 4, iclass 3, count 2 2006.173.15:03:41.30#ibcon#read 4, iclass 3, count 2 2006.173.15:03:41.30#ibcon#about to read 5, iclass 3, count 2 2006.173.15:03:41.30#ibcon#read 5, iclass 3, count 2 2006.173.15:03:41.30#ibcon#about to read 6, iclass 3, count 2 2006.173.15:03:41.30#ibcon#read 6, iclass 3, count 2 2006.173.15:03:41.30#ibcon#end of sib2, iclass 3, count 2 2006.173.15:03:41.30#ibcon#*mode == 0, iclass 3, count 2 2006.173.15:03:41.30#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.15:03:41.30#ibcon#[27=AT02-04\r\n] 2006.173.15:03:41.30#ibcon#*before write, iclass 3, count 2 2006.173.15:03:41.30#ibcon#enter sib2, iclass 3, count 2 2006.173.15:03:41.30#ibcon#flushed, iclass 3, count 2 2006.173.15:03:41.30#ibcon#about to write, iclass 3, count 2 2006.173.15:03:41.30#ibcon#wrote, iclass 3, count 2 2006.173.15:03:41.30#ibcon#about to read 3, iclass 3, count 2 2006.173.15:03:41.33#ibcon#read 3, iclass 3, count 2 2006.173.15:03:41.33#ibcon#about to read 4, iclass 3, count 2 2006.173.15:03:41.33#ibcon#read 4, iclass 3, count 2 2006.173.15:03:41.33#ibcon#about to read 5, iclass 3, count 2 2006.173.15:03:41.33#ibcon#read 5, iclass 3, count 2 2006.173.15:03:41.33#ibcon#about to read 6, iclass 3, count 2 2006.173.15:03:41.33#ibcon#read 6, iclass 3, count 2 2006.173.15:03:41.33#ibcon#end of sib2, iclass 3, count 2 2006.173.15:03:41.33#ibcon#*after write, iclass 3, count 2 2006.173.15:03:41.33#ibcon#*before return 0, iclass 3, count 2 2006.173.15:03:41.33#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.15:03:41.33#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.15:03:41.33#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.15:03:41.33#ibcon#ireg 7 cls_cnt 0 2006.173.15:03:41.33#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.15:03:41.45#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.15:03:41.45#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.15:03:41.45#ibcon#enter wrdev, iclass 3, count 0 2006.173.15:03:41.45#ibcon#first serial, iclass 3, count 0 2006.173.15:03:41.45#ibcon#enter sib2, iclass 3, count 0 2006.173.15:03:41.45#ibcon#flushed, iclass 3, count 0 2006.173.15:03:41.45#ibcon#about to write, iclass 3, count 0 2006.173.15:03:41.45#ibcon#wrote, iclass 3, count 0 2006.173.15:03:41.45#ibcon#about to read 3, iclass 3, count 0 2006.173.15:03:41.47#ibcon#read 3, iclass 3, count 0 2006.173.15:03:41.47#ibcon#about to read 4, iclass 3, count 0 2006.173.15:03:41.47#ibcon#read 4, iclass 3, count 0 2006.173.15:03:41.47#ibcon#about to read 5, iclass 3, count 0 2006.173.15:03:41.47#ibcon#read 5, iclass 3, count 0 2006.173.15:03:41.47#ibcon#about to read 6, iclass 3, count 0 2006.173.15:03:41.47#ibcon#read 6, iclass 3, count 0 2006.173.15:03:41.47#ibcon#end of sib2, iclass 3, count 0 2006.173.15:03:41.47#ibcon#*mode == 0, iclass 3, count 0 2006.173.15:03:41.47#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.15:03:41.47#ibcon#[27=USB\r\n] 2006.173.15:03:41.47#ibcon#*before write, iclass 3, count 0 2006.173.15:03:41.47#ibcon#enter sib2, iclass 3, count 0 2006.173.15:03:41.47#ibcon#flushed, iclass 3, count 0 2006.173.15:03:41.47#ibcon#about to write, iclass 3, count 0 2006.173.15:03:41.47#ibcon#wrote, iclass 3, count 0 2006.173.15:03:41.47#ibcon#about to read 3, iclass 3, count 0 2006.173.15:03:41.50#ibcon#read 3, iclass 3, count 0 2006.173.15:03:41.50#ibcon#about to read 4, iclass 3, count 0 2006.173.15:03:41.50#ibcon#read 4, iclass 3, count 0 2006.173.15:03:41.50#ibcon#about to read 5, iclass 3, count 0 2006.173.15:03:41.50#ibcon#read 5, iclass 3, count 0 2006.173.15:03:41.50#ibcon#about to read 6, iclass 3, count 0 2006.173.15:03:41.50#ibcon#read 6, iclass 3, count 0 2006.173.15:03:41.50#ibcon#end of sib2, iclass 3, count 0 2006.173.15:03:41.50#ibcon#*after write, iclass 3, count 0 2006.173.15:03:41.50#ibcon#*before return 0, iclass 3, count 0 2006.173.15:03:41.50#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.15:03:41.50#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.15:03:41.50#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.15:03:41.50#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.15:03:41.50$vck44/vblo=3,649.99 2006.173.15:03:41.50#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.15:03:41.50#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.15:03:41.50#ibcon#ireg 17 cls_cnt 0 2006.173.15:03:41.50#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.15:03:41.50#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.15:03:41.50#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.15:03:41.50#ibcon#enter wrdev, iclass 5, count 0 2006.173.15:03:41.50#ibcon#first serial, iclass 5, count 0 2006.173.15:03:41.50#ibcon#enter sib2, iclass 5, count 0 2006.173.15:03:41.50#ibcon#flushed, iclass 5, count 0 2006.173.15:03:41.50#ibcon#about to write, iclass 5, count 0 2006.173.15:03:41.50#ibcon#wrote, iclass 5, count 0 2006.173.15:03:41.50#ibcon#about to read 3, iclass 5, count 0 2006.173.15:03:41.52#ibcon#read 3, iclass 5, count 0 2006.173.15:03:41.52#ibcon#about to read 4, iclass 5, count 0 2006.173.15:03:41.52#ibcon#read 4, iclass 5, count 0 2006.173.15:03:41.52#ibcon#about to read 5, iclass 5, count 0 2006.173.15:03:41.52#ibcon#read 5, iclass 5, count 0 2006.173.15:03:41.52#ibcon#about to read 6, iclass 5, count 0 2006.173.15:03:41.52#ibcon#read 6, iclass 5, count 0 2006.173.15:03:41.52#ibcon#end of sib2, iclass 5, count 0 2006.173.15:03:41.52#ibcon#*mode == 0, iclass 5, count 0 2006.173.15:03:41.52#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.15:03:41.52#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.15:03:41.52#ibcon#*before write, iclass 5, count 0 2006.173.15:03:41.52#ibcon#enter sib2, iclass 5, count 0 2006.173.15:03:41.52#ibcon#flushed, iclass 5, count 0 2006.173.15:03:41.52#ibcon#about to write, iclass 5, count 0 2006.173.15:03:41.52#ibcon#wrote, iclass 5, count 0 2006.173.15:03:41.52#ibcon#about to read 3, iclass 5, count 0 2006.173.15:03:41.56#ibcon#read 3, iclass 5, count 0 2006.173.15:03:41.56#ibcon#about to read 4, iclass 5, count 0 2006.173.15:03:41.56#ibcon#read 4, iclass 5, count 0 2006.173.15:03:41.56#ibcon#about to read 5, iclass 5, count 0 2006.173.15:03:41.56#ibcon#read 5, iclass 5, count 0 2006.173.15:03:41.56#ibcon#about to read 6, iclass 5, count 0 2006.173.15:03:41.56#ibcon#read 6, iclass 5, count 0 2006.173.15:03:41.56#ibcon#end of sib2, iclass 5, count 0 2006.173.15:03:41.56#ibcon#*after write, iclass 5, count 0 2006.173.15:03:41.56#ibcon#*before return 0, iclass 5, count 0 2006.173.15:03:41.56#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.15:03:41.56#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.15:03:41.56#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.15:03:41.56#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.15:03:41.56$vck44/vb=3,4 2006.173.15:03:41.56#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.173.15:03:41.56#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.173.15:03:41.56#ibcon#ireg 11 cls_cnt 2 2006.173.15:03:41.56#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.15:03:41.62#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.15:03:41.62#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.15:03:41.62#ibcon#enter wrdev, iclass 7, count 2 2006.173.15:03:41.62#ibcon#first serial, iclass 7, count 2 2006.173.15:03:41.62#ibcon#enter sib2, iclass 7, count 2 2006.173.15:03:41.62#ibcon#flushed, iclass 7, count 2 2006.173.15:03:41.62#ibcon#about to write, iclass 7, count 2 2006.173.15:03:41.62#ibcon#wrote, iclass 7, count 2 2006.173.15:03:41.62#ibcon#about to read 3, iclass 7, count 2 2006.173.15:03:41.64#ibcon#read 3, iclass 7, count 2 2006.173.15:03:41.64#ibcon#about to read 4, iclass 7, count 2 2006.173.15:03:41.64#ibcon#read 4, iclass 7, count 2 2006.173.15:03:41.64#ibcon#about to read 5, iclass 7, count 2 2006.173.15:03:41.64#ibcon#read 5, iclass 7, count 2 2006.173.15:03:41.64#ibcon#about to read 6, iclass 7, count 2 2006.173.15:03:41.64#ibcon#read 6, iclass 7, count 2 2006.173.15:03:41.64#ibcon#end of sib2, iclass 7, count 2 2006.173.15:03:41.64#ibcon#*mode == 0, iclass 7, count 2 2006.173.15:03:41.64#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.173.15:03:41.64#ibcon#[27=AT03-04\r\n] 2006.173.15:03:41.64#ibcon#*before write, iclass 7, count 2 2006.173.15:03:41.64#ibcon#enter sib2, iclass 7, count 2 2006.173.15:03:41.64#ibcon#flushed, iclass 7, count 2 2006.173.15:03:41.64#ibcon#about to write, iclass 7, count 2 2006.173.15:03:41.64#ibcon#wrote, iclass 7, count 2 2006.173.15:03:41.64#ibcon#about to read 3, iclass 7, count 2 2006.173.15:03:41.67#ibcon#read 3, iclass 7, count 2 2006.173.15:03:41.67#ibcon#about to read 4, iclass 7, count 2 2006.173.15:03:41.67#ibcon#read 4, iclass 7, count 2 2006.173.15:03:41.67#ibcon#about to read 5, iclass 7, count 2 2006.173.15:03:41.67#ibcon#read 5, iclass 7, count 2 2006.173.15:03:41.67#ibcon#about to read 6, iclass 7, count 2 2006.173.15:03:41.67#ibcon#read 6, iclass 7, count 2 2006.173.15:03:41.67#ibcon#end of sib2, iclass 7, count 2 2006.173.15:03:41.67#ibcon#*after write, iclass 7, count 2 2006.173.15:03:41.67#ibcon#*before return 0, iclass 7, count 2 2006.173.15:03:41.67#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.15:03:41.67#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.173.15:03:41.67#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.173.15:03:41.67#ibcon#ireg 7 cls_cnt 0 2006.173.15:03:41.67#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.15:03:41.79#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.15:03:41.79#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.15:03:41.79#ibcon#enter wrdev, iclass 7, count 0 2006.173.15:03:41.79#ibcon#first serial, iclass 7, count 0 2006.173.15:03:41.79#ibcon#enter sib2, iclass 7, count 0 2006.173.15:03:41.79#ibcon#flushed, iclass 7, count 0 2006.173.15:03:41.79#ibcon#about to write, iclass 7, count 0 2006.173.15:03:41.79#ibcon#wrote, iclass 7, count 0 2006.173.15:03:41.79#ibcon#about to read 3, iclass 7, count 0 2006.173.15:03:41.81#ibcon#read 3, iclass 7, count 0 2006.173.15:03:41.81#ibcon#about to read 4, iclass 7, count 0 2006.173.15:03:41.81#ibcon#read 4, iclass 7, count 0 2006.173.15:03:41.81#ibcon#about to read 5, iclass 7, count 0 2006.173.15:03:41.81#ibcon#read 5, iclass 7, count 0 2006.173.15:03:41.81#ibcon#about to read 6, iclass 7, count 0 2006.173.15:03:41.81#ibcon#read 6, iclass 7, count 0 2006.173.15:03:41.81#ibcon#end of sib2, iclass 7, count 0 2006.173.15:03:41.81#ibcon#*mode == 0, iclass 7, count 0 2006.173.15:03:41.81#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.15:03:41.81#ibcon#[27=USB\r\n] 2006.173.15:03:41.81#ibcon#*before write, iclass 7, count 0 2006.173.15:03:41.81#ibcon#enter sib2, iclass 7, count 0 2006.173.15:03:41.81#ibcon#flushed, iclass 7, count 0 2006.173.15:03:41.81#ibcon#about to write, iclass 7, count 0 2006.173.15:03:41.81#ibcon#wrote, iclass 7, count 0 2006.173.15:03:41.81#ibcon#about to read 3, iclass 7, count 0 2006.173.15:03:41.84#ibcon#read 3, iclass 7, count 0 2006.173.15:03:41.84#ibcon#about to read 4, iclass 7, count 0 2006.173.15:03:41.84#ibcon#read 4, iclass 7, count 0 2006.173.15:03:41.84#ibcon#about to read 5, iclass 7, count 0 2006.173.15:03:41.84#ibcon#read 5, iclass 7, count 0 2006.173.15:03:41.84#ibcon#about to read 6, iclass 7, count 0 2006.173.15:03:41.84#ibcon#read 6, iclass 7, count 0 2006.173.15:03:41.84#ibcon#end of sib2, iclass 7, count 0 2006.173.15:03:41.84#ibcon#*after write, iclass 7, count 0 2006.173.15:03:41.84#ibcon#*before return 0, iclass 7, count 0 2006.173.15:03:41.84#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.15:03:41.84#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.173.15:03:41.84#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.15:03:41.84#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.15:03:41.84$vck44/vblo=4,679.99 2006.173.15:03:41.84#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.15:03:41.84#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.15:03:41.84#ibcon#ireg 17 cls_cnt 0 2006.173.15:03:41.84#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.15:03:41.84#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.15:03:41.84#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.15:03:41.84#ibcon#enter wrdev, iclass 11, count 0 2006.173.15:03:41.84#ibcon#first serial, iclass 11, count 0 2006.173.15:03:41.84#ibcon#enter sib2, iclass 11, count 0 2006.173.15:03:41.84#ibcon#flushed, iclass 11, count 0 2006.173.15:03:41.84#ibcon#about to write, iclass 11, count 0 2006.173.15:03:41.84#ibcon#wrote, iclass 11, count 0 2006.173.15:03:41.84#ibcon#about to read 3, iclass 11, count 0 2006.173.15:03:41.86#ibcon#read 3, iclass 11, count 0 2006.173.15:03:41.86#ibcon#about to read 4, iclass 11, count 0 2006.173.15:03:41.86#ibcon#read 4, iclass 11, count 0 2006.173.15:03:41.86#ibcon#about to read 5, iclass 11, count 0 2006.173.15:03:41.86#ibcon#read 5, iclass 11, count 0 2006.173.15:03:41.86#ibcon#about to read 6, iclass 11, count 0 2006.173.15:03:41.86#ibcon#read 6, iclass 11, count 0 2006.173.15:03:41.86#ibcon#end of sib2, iclass 11, count 0 2006.173.15:03:41.86#ibcon#*mode == 0, iclass 11, count 0 2006.173.15:03:41.86#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.15:03:41.86#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.15:03:41.86#ibcon#*before write, iclass 11, count 0 2006.173.15:03:41.86#ibcon#enter sib2, iclass 11, count 0 2006.173.15:03:41.86#ibcon#flushed, iclass 11, count 0 2006.173.15:03:41.86#ibcon#about to write, iclass 11, count 0 2006.173.15:03:41.86#ibcon#wrote, iclass 11, count 0 2006.173.15:03:41.86#ibcon#about to read 3, iclass 11, count 0 2006.173.15:03:41.90#ibcon#read 3, iclass 11, count 0 2006.173.15:03:41.90#ibcon#about to read 4, iclass 11, count 0 2006.173.15:03:41.90#ibcon#read 4, iclass 11, count 0 2006.173.15:03:41.90#ibcon#about to read 5, iclass 11, count 0 2006.173.15:03:41.90#ibcon#read 5, iclass 11, count 0 2006.173.15:03:41.90#ibcon#about to read 6, iclass 11, count 0 2006.173.15:03:41.90#ibcon#read 6, iclass 11, count 0 2006.173.15:03:41.90#ibcon#end of sib2, iclass 11, count 0 2006.173.15:03:41.90#ibcon#*after write, iclass 11, count 0 2006.173.15:03:41.90#ibcon#*before return 0, iclass 11, count 0 2006.173.15:03:41.90#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.15:03:41.90#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.15:03:41.90#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.15:03:41.90#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.15:03:41.90$vck44/vb=4,4 2006.173.15:03:41.90#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.173.15:03:41.90#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.173.15:03:41.90#ibcon#ireg 11 cls_cnt 2 2006.173.15:03:41.90#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.15:03:41.96#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.15:03:41.96#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.15:03:41.96#ibcon#enter wrdev, iclass 13, count 2 2006.173.15:03:41.96#ibcon#first serial, iclass 13, count 2 2006.173.15:03:41.96#ibcon#enter sib2, iclass 13, count 2 2006.173.15:03:41.96#ibcon#flushed, iclass 13, count 2 2006.173.15:03:41.96#ibcon#about to write, iclass 13, count 2 2006.173.15:03:41.96#ibcon#wrote, iclass 13, count 2 2006.173.15:03:41.96#ibcon#about to read 3, iclass 13, count 2 2006.173.15:03:41.98#ibcon#read 3, iclass 13, count 2 2006.173.15:03:41.98#ibcon#about to read 4, iclass 13, count 2 2006.173.15:03:41.98#ibcon#read 4, iclass 13, count 2 2006.173.15:03:41.98#ibcon#about to read 5, iclass 13, count 2 2006.173.15:03:41.98#ibcon#read 5, iclass 13, count 2 2006.173.15:03:41.98#ibcon#about to read 6, iclass 13, count 2 2006.173.15:03:41.98#ibcon#read 6, iclass 13, count 2 2006.173.15:03:41.98#ibcon#end of sib2, iclass 13, count 2 2006.173.15:03:41.98#ibcon#*mode == 0, iclass 13, count 2 2006.173.15:03:41.98#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.173.15:03:41.98#ibcon#[27=AT04-04\r\n] 2006.173.15:03:41.98#ibcon#*before write, iclass 13, count 2 2006.173.15:03:41.98#ibcon#enter sib2, iclass 13, count 2 2006.173.15:03:41.98#ibcon#flushed, iclass 13, count 2 2006.173.15:03:41.98#ibcon#about to write, iclass 13, count 2 2006.173.15:03:41.98#ibcon#wrote, iclass 13, count 2 2006.173.15:03:41.98#ibcon#about to read 3, iclass 13, count 2 2006.173.15:03:42.01#ibcon#read 3, iclass 13, count 2 2006.173.15:03:42.01#ibcon#about to read 4, iclass 13, count 2 2006.173.15:03:42.01#ibcon#read 4, iclass 13, count 2 2006.173.15:03:42.01#ibcon#about to read 5, iclass 13, count 2 2006.173.15:03:42.01#ibcon#read 5, iclass 13, count 2 2006.173.15:03:42.01#ibcon#about to read 6, iclass 13, count 2 2006.173.15:03:42.01#ibcon#read 6, iclass 13, count 2 2006.173.15:03:42.01#ibcon#end of sib2, iclass 13, count 2 2006.173.15:03:42.01#ibcon#*after write, iclass 13, count 2 2006.173.15:03:42.01#ibcon#*before return 0, iclass 13, count 2 2006.173.15:03:42.01#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.15:03:42.01#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.173.15:03:42.01#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.173.15:03:42.01#ibcon#ireg 7 cls_cnt 0 2006.173.15:03:42.01#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.15:03:42.13#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.15:03:42.13#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.15:03:42.13#ibcon#enter wrdev, iclass 13, count 0 2006.173.15:03:42.13#ibcon#first serial, iclass 13, count 0 2006.173.15:03:42.13#ibcon#enter sib2, iclass 13, count 0 2006.173.15:03:42.13#ibcon#flushed, iclass 13, count 0 2006.173.15:03:42.13#ibcon#about to write, iclass 13, count 0 2006.173.15:03:42.13#ibcon#wrote, iclass 13, count 0 2006.173.15:03:42.13#ibcon#about to read 3, iclass 13, count 0 2006.173.15:03:42.15#ibcon#read 3, iclass 13, count 0 2006.173.15:03:42.15#ibcon#about to read 4, iclass 13, count 0 2006.173.15:03:42.15#ibcon#read 4, iclass 13, count 0 2006.173.15:03:42.15#ibcon#about to read 5, iclass 13, count 0 2006.173.15:03:42.15#ibcon#read 5, iclass 13, count 0 2006.173.15:03:42.15#ibcon#about to read 6, iclass 13, count 0 2006.173.15:03:42.15#ibcon#read 6, iclass 13, count 0 2006.173.15:03:42.15#ibcon#end of sib2, iclass 13, count 0 2006.173.15:03:42.15#ibcon#*mode == 0, iclass 13, count 0 2006.173.15:03:42.15#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.15:03:42.15#ibcon#[27=USB\r\n] 2006.173.15:03:42.15#ibcon#*before write, iclass 13, count 0 2006.173.15:03:42.15#ibcon#enter sib2, iclass 13, count 0 2006.173.15:03:42.15#ibcon#flushed, iclass 13, count 0 2006.173.15:03:42.15#ibcon#about to write, iclass 13, count 0 2006.173.15:03:42.15#ibcon#wrote, iclass 13, count 0 2006.173.15:03:42.15#ibcon#about to read 3, iclass 13, count 0 2006.173.15:03:42.18#ibcon#read 3, iclass 13, count 0 2006.173.15:03:42.18#ibcon#about to read 4, iclass 13, count 0 2006.173.15:03:42.18#ibcon#read 4, iclass 13, count 0 2006.173.15:03:42.18#ibcon#about to read 5, iclass 13, count 0 2006.173.15:03:42.18#ibcon#read 5, iclass 13, count 0 2006.173.15:03:42.18#ibcon#about to read 6, iclass 13, count 0 2006.173.15:03:42.18#ibcon#read 6, iclass 13, count 0 2006.173.15:03:42.18#ibcon#end of sib2, iclass 13, count 0 2006.173.15:03:42.18#ibcon#*after write, iclass 13, count 0 2006.173.15:03:42.18#ibcon#*before return 0, iclass 13, count 0 2006.173.15:03:42.18#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.15:03:42.18#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.173.15:03:42.18#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.15:03:42.18#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.15:03:42.18$vck44/vblo=5,709.99 2006.173.15:03:42.18#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.15:03:42.18#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.15:03:42.18#ibcon#ireg 17 cls_cnt 0 2006.173.15:03:42.18#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.15:03:42.18#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.15:03:42.18#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.15:03:42.18#ibcon#enter wrdev, iclass 15, count 0 2006.173.15:03:42.18#ibcon#first serial, iclass 15, count 0 2006.173.15:03:42.18#ibcon#enter sib2, iclass 15, count 0 2006.173.15:03:42.18#ibcon#flushed, iclass 15, count 0 2006.173.15:03:42.18#ibcon#about to write, iclass 15, count 0 2006.173.15:03:42.18#ibcon#wrote, iclass 15, count 0 2006.173.15:03:42.18#ibcon#about to read 3, iclass 15, count 0 2006.173.15:03:42.20#ibcon#read 3, iclass 15, count 0 2006.173.15:03:42.20#ibcon#about to read 4, iclass 15, count 0 2006.173.15:03:42.20#ibcon#read 4, iclass 15, count 0 2006.173.15:03:42.20#ibcon#about to read 5, iclass 15, count 0 2006.173.15:03:42.20#ibcon#read 5, iclass 15, count 0 2006.173.15:03:42.20#ibcon#about to read 6, iclass 15, count 0 2006.173.15:03:42.20#ibcon#read 6, iclass 15, count 0 2006.173.15:03:42.20#ibcon#end of sib2, iclass 15, count 0 2006.173.15:03:42.20#ibcon#*mode == 0, iclass 15, count 0 2006.173.15:03:42.20#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.15:03:42.20#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.15:03:42.20#ibcon#*before write, iclass 15, count 0 2006.173.15:03:42.20#ibcon#enter sib2, iclass 15, count 0 2006.173.15:03:42.20#ibcon#flushed, iclass 15, count 0 2006.173.15:03:42.20#ibcon#about to write, iclass 15, count 0 2006.173.15:03:42.20#ibcon#wrote, iclass 15, count 0 2006.173.15:03:42.20#ibcon#about to read 3, iclass 15, count 0 2006.173.15:03:42.24#ibcon#read 3, iclass 15, count 0 2006.173.15:03:42.24#ibcon#about to read 4, iclass 15, count 0 2006.173.15:03:42.24#ibcon#read 4, iclass 15, count 0 2006.173.15:03:42.24#ibcon#about to read 5, iclass 15, count 0 2006.173.15:03:42.24#ibcon#read 5, iclass 15, count 0 2006.173.15:03:42.24#ibcon#about to read 6, iclass 15, count 0 2006.173.15:03:42.24#ibcon#read 6, iclass 15, count 0 2006.173.15:03:42.24#ibcon#end of sib2, iclass 15, count 0 2006.173.15:03:42.24#ibcon#*after write, iclass 15, count 0 2006.173.15:03:42.24#ibcon#*before return 0, iclass 15, count 0 2006.173.15:03:42.24#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.15:03:42.24#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.15:03:42.24#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.15:03:42.24#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.15:03:42.24$vck44/vb=5,4 2006.173.15:03:42.24#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.15:03:42.24#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.15:03:42.24#ibcon#ireg 11 cls_cnt 2 2006.173.15:03:42.24#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.15:03:42.30#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.15:03:42.30#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.15:03:42.30#ibcon#enter wrdev, iclass 17, count 2 2006.173.15:03:42.30#ibcon#first serial, iclass 17, count 2 2006.173.15:03:42.30#ibcon#enter sib2, iclass 17, count 2 2006.173.15:03:42.30#ibcon#flushed, iclass 17, count 2 2006.173.15:03:42.30#ibcon#about to write, iclass 17, count 2 2006.173.15:03:42.30#ibcon#wrote, iclass 17, count 2 2006.173.15:03:42.30#ibcon#about to read 3, iclass 17, count 2 2006.173.15:03:42.32#ibcon#read 3, iclass 17, count 2 2006.173.15:03:42.32#ibcon#about to read 4, iclass 17, count 2 2006.173.15:03:42.32#ibcon#read 4, iclass 17, count 2 2006.173.15:03:42.32#ibcon#about to read 5, iclass 17, count 2 2006.173.15:03:42.32#ibcon#read 5, iclass 17, count 2 2006.173.15:03:42.32#ibcon#about to read 6, iclass 17, count 2 2006.173.15:03:42.32#ibcon#read 6, iclass 17, count 2 2006.173.15:03:42.32#ibcon#end of sib2, iclass 17, count 2 2006.173.15:03:42.32#ibcon#*mode == 0, iclass 17, count 2 2006.173.15:03:42.32#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.15:03:42.32#ibcon#[27=AT05-04\r\n] 2006.173.15:03:42.32#ibcon#*before write, iclass 17, count 2 2006.173.15:03:42.32#ibcon#enter sib2, iclass 17, count 2 2006.173.15:03:42.32#ibcon#flushed, iclass 17, count 2 2006.173.15:03:42.32#ibcon#about to write, iclass 17, count 2 2006.173.15:03:42.32#ibcon#wrote, iclass 17, count 2 2006.173.15:03:42.32#ibcon#about to read 3, iclass 17, count 2 2006.173.15:03:42.35#ibcon#read 3, iclass 17, count 2 2006.173.15:03:42.35#ibcon#about to read 4, iclass 17, count 2 2006.173.15:03:42.35#ibcon#read 4, iclass 17, count 2 2006.173.15:03:42.35#ibcon#about to read 5, iclass 17, count 2 2006.173.15:03:42.35#ibcon#read 5, iclass 17, count 2 2006.173.15:03:42.35#ibcon#about to read 6, iclass 17, count 2 2006.173.15:03:42.35#ibcon#read 6, iclass 17, count 2 2006.173.15:03:42.35#ibcon#end of sib2, iclass 17, count 2 2006.173.15:03:42.35#ibcon#*after write, iclass 17, count 2 2006.173.15:03:42.35#ibcon#*before return 0, iclass 17, count 2 2006.173.15:03:42.35#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.15:03:42.35#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.15:03:42.35#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.15:03:42.35#ibcon#ireg 7 cls_cnt 0 2006.173.15:03:42.35#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.15:03:42.47#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.15:03:42.47#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.15:03:42.47#ibcon#enter wrdev, iclass 17, count 0 2006.173.15:03:42.47#ibcon#first serial, iclass 17, count 0 2006.173.15:03:42.47#ibcon#enter sib2, iclass 17, count 0 2006.173.15:03:42.47#ibcon#flushed, iclass 17, count 0 2006.173.15:03:42.47#ibcon#about to write, iclass 17, count 0 2006.173.15:03:42.47#ibcon#wrote, iclass 17, count 0 2006.173.15:03:42.47#ibcon#about to read 3, iclass 17, count 0 2006.173.15:03:42.49#ibcon#read 3, iclass 17, count 0 2006.173.15:03:42.49#ibcon#about to read 4, iclass 17, count 0 2006.173.15:03:42.49#ibcon#read 4, iclass 17, count 0 2006.173.15:03:42.49#ibcon#about to read 5, iclass 17, count 0 2006.173.15:03:42.49#ibcon#read 5, iclass 17, count 0 2006.173.15:03:42.49#ibcon#about to read 6, iclass 17, count 0 2006.173.15:03:42.49#ibcon#read 6, iclass 17, count 0 2006.173.15:03:42.49#ibcon#end of sib2, iclass 17, count 0 2006.173.15:03:42.49#ibcon#*mode == 0, iclass 17, count 0 2006.173.15:03:42.49#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.15:03:42.49#ibcon#[27=USB\r\n] 2006.173.15:03:42.49#ibcon#*before write, iclass 17, count 0 2006.173.15:03:42.49#ibcon#enter sib2, iclass 17, count 0 2006.173.15:03:42.49#ibcon#flushed, iclass 17, count 0 2006.173.15:03:42.49#ibcon#about to write, iclass 17, count 0 2006.173.15:03:42.49#ibcon#wrote, iclass 17, count 0 2006.173.15:03:42.49#ibcon#about to read 3, iclass 17, count 0 2006.173.15:03:42.52#ibcon#read 3, iclass 17, count 0 2006.173.15:03:42.52#ibcon#about to read 4, iclass 17, count 0 2006.173.15:03:42.52#ibcon#read 4, iclass 17, count 0 2006.173.15:03:42.52#ibcon#about to read 5, iclass 17, count 0 2006.173.15:03:42.52#ibcon#read 5, iclass 17, count 0 2006.173.15:03:42.52#ibcon#about to read 6, iclass 17, count 0 2006.173.15:03:42.52#ibcon#read 6, iclass 17, count 0 2006.173.15:03:42.52#ibcon#end of sib2, iclass 17, count 0 2006.173.15:03:42.52#ibcon#*after write, iclass 17, count 0 2006.173.15:03:42.52#ibcon#*before return 0, iclass 17, count 0 2006.173.15:03:42.52#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.15:03:42.52#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.15:03:42.52#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.15:03:42.52#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.15:03:42.52$vck44/vblo=6,719.99 2006.173.15:03:42.52#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.15:03:42.52#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.15:03:42.52#ibcon#ireg 17 cls_cnt 0 2006.173.15:03:42.52#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.15:03:42.52#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.15:03:42.52#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.15:03:42.52#ibcon#enter wrdev, iclass 19, count 0 2006.173.15:03:42.52#ibcon#first serial, iclass 19, count 0 2006.173.15:03:42.52#ibcon#enter sib2, iclass 19, count 0 2006.173.15:03:42.52#ibcon#flushed, iclass 19, count 0 2006.173.15:03:42.52#ibcon#about to write, iclass 19, count 0 2006.173.15:03:42.52#ibcon#wrote, iclass 19, count 0 2006.173.15:03:42.52#ibcon#about to read 3, iclass 19, count 0 2006.173.15:03:42.54#ibcon#read 3, iclass 19, count 0 2006.173.15:03:42.54#ibcon#about to read 4, iclass 19, count 0 2006.173.15:03:42.54#ibcon#read 4, iclass 19, count 0 2006.173.15:03:42.54#ibcon#about to read 5, iclass 19, count 0 2006.173.15:03:42.54#ibcon#read 5, iclass 19, count 0 2006.173.15:03:42.54#ibcon#about to read 6, iclass 19, count 0 2006.173.15:03:42.54#ibcon#read 6, iclass 19, count 0 2006.173.15:03:42.54#ibcon#end of sib2, iclass 19, count 0 2006.173.15:03:42.54#ibcon#*mode == 0, iclass 19, count 0 2006.173.15:03:42.54#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.15:03:42.54#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.15:03:42.54#ibcon#*before write, iclass 19, count 0 2006.173.15:03:42.54#ibcon#enter sib2, iclass 19, count 0 2006.173.15:03:42.54#ibcon#flushed, iclass 19, count 0 2006.173.15:03:42.54#ibcon#about to write, iclass 19, count 0 2006.173.15:03:42.54#ibcon#wrote, iclass 19, count 0 2006.173.15:03:42.54#ibcon#about to read 3, iclass 19, count 0 2006.173.15:03:42.58#ibcon#read 3, iclass 19, count 0 2006.173.15:03:42.58#ibcon#about to read 4, iclass 19, count 0 2006.173.15:03:42.58#ibcon#read 4, iclass 19, count 0 2006.173.15:03:42.58#ibcon#about to read 5, iclass 19, count 0 2006.173.15:03:42.58#ibcon#read 5, iclass 19, count 0 2006.173.15:03:42.58#ibcon#about to read 6, iclass 19, count 0 2006.173.15:03:42.58#ibcon#read 6, iclass 19, count 0 2006.173.15:03:42.58#ibcon#end of sib2, iclass 19, count 0 2006.173.15:03:42.58#ibcon#*after write, iclass 19, count 0 2006.173.15:03:42.58#ibcon#*before return 0, iclass 19, count 0 2006.173.15:03:42.58#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.15:03:42.58#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.15:03:42.58#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.15:03:42.58#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.15:03:42.58$vck44/vb=6,4 2006.173.15:03:42.58#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.15:03:42.58#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.15:03:42.58#ibcon#ireg 11 cls_cnt 2 2006.173.15:03:42.58#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.15:03:42.64#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.15:03:42.64#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.15:03:42.64#ibcon#enter wrdev, iclass 21, count 2 2006.173.15:03:42.64#ibcon#first serial, iclass 21, count 2 2006.173.15:03:42.64#ibcon#enter sib2, iclass 21, count 2 2006.173.15:03:42.64#ibcon#flushed, iclass 21, count 2 2006.173.15:03:42.64#ibcon#about to write, iclass 21, count 2 2006.173.15:03:42.64#ibcon#wrote, iclass 21, count 2 2006.173.15:03:42.64#ibcon#about to read 3, iclass 21, count 2 2006.173.15:03:42.66#ibcon#read 3, iclass 21, count 2 2006.173.15:03:42.66#ibcon#about to read 4, iclass 21, count 2 2006.173.15:03:42.66#ibcon#read 4, iclass 21, count 2 2006.173.15:03:42.66#ibcon#about to read 5, iclass 21, count 2 2006.173.15:03:42.66#ibcon#read 5, iclass 21, count 2 2006.173.15:03:42.66#ibcon#about to read 6, iclass 21, count 2 2006.173.15:03:42.66#ibcon#read 6, iclass 21, count 2 2006.173.15:03:42.66#ibcon#end of sib2, iclass 21, count 2 2006.173.15:03:42.66#ibcon#*mode == 0, iclass 21, count 2 2006.173.15:03:42.66#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.15:03:42.66#ibcon#[27=AT06-04\r\n] 2006.173.15:03:42.66#ibcon#*before write, iclass 21, count 2 2006.173.15:03:42.66#ibcon#enter sib2, iclass 21, count 2 2006.173.15:03:42.66#ibcon#flushed, iclass 21, count 2 2006.173.15:03:42.66#ibcon#about to write, iclass 21, count 2 2006.173.15:03:42.66#ibcon#wrote, iclass 21, count 2 2006.173.15:03:42.66#ibcon#about to read 3, iclass 21, count 2 2006.173.15:03:42.69#ibcon#read 3, iclass 21, count 2 2006.173.15:03:42.69#ibcon#about to read 4, iclass 21, count 2 2006.173.15:03:42.69#ibcon#read 4, iclass 21, count 2 2006.173.15:03:42.69#ibcon#about to read 5, iclass 21, count 2 2006.173.15:03:42.69#ibcon#read 5, iclass 21, count 2 2006.173.15:03:42.69#ibcon#about to read 6, iclass 21, count 2 2006.173.15:03:42.69#ibcon#read 6, iclass 21, count 2 2006.173.15:03:42.69#ibcon#end of sib2, iclass 21, count 2 2006.173.15:03:42.69#ibcon#*after write, iclass 21, count 2 2006.173.15:03:42.69#ibcon#*before return 0, iclass 21, count 2 2006.173.15:03:42.69#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.15:03:42.69#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.15:03:42.69#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.15:03:42.69#ibcon#ireg 7 cls_cnt 0 2006.173.15:03:42.69#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.15:03:42.81#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.15:03:42.81#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.15:03:42.81#ibcon#enter wrdev, iclass 21, count 0 2006.173.15:03:42.81#ibcon#first serial, iclass 21, count 0 2006.173.15:03:42.81#ibcon#enter sib2, iclass 21, count 0 2006.173.15:03:42.81#ibcon#flushed, iclass 21, count 0 2006.173.15:03:42.81#ibcon#about to write, iclass 21, count 0 2006.173.15:03:42.81#ibcon#wrote, iclass 21, count 0 2006.173.15:03:42.81#ibcon#about to read 3, iclass 21, count 0 2006.173.15:03:42.83#ibcon#read 3, iclass 21, count 0 2006.173.15:03:42.83#ibcon#about to read 4, iclass 21, count 0 2006.173.15:03:42.83#ibcon#read 4, iclass 21, count 0 2006.173.15:03:42.83#ibcon#about to read 5, iclass 21, count 0 2006.173.15:03:42.83#ibcon#read 5, iclass 21, count 0 2006.173.15:03:42.83#ibcon#about to read 6, iclass 21, count 0 2006.173.15:03:42.83#ibcon#read 6, iclass 21, count 0 2006.173.15:03:42.83#ibcon#end of sib2, iclass 21, count 0 2006.173.15:03:42.83#ibcon#*mode == 0, iclass 21, count 0 2006.173.15:03:42.83#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.15:03:42.83#ibcon#[27=USB\r\n] 2006.173.15:03:42.83#ibcon#*before write, iclass 21, count 0 2006.173.15:03:42.83#ibcon#enter sib2, iclass 21, count 0 2006.173.15:03:42.83#ibcon#flushed, iclass 21, count 0 2006.173.15:03:42.83#ibcon#about to write, iclass 21, count 0 2006.173.15:03:42.83#ibcon#wrote, iclass 21, count 0 2006.173.15:03:42.83#ibcon#about to read 3, iclass 21, count 0 2006.173.15:03:42.86#ibcon#read 3, iclass 21, count 0 2006.173.15:03:42.86#ibcon#about to read 4, iclass 21, count 0 2006.173.15:03:42.86#ibcon#read 4, iclass 21, count 0 2006.173.15:03:42.86#ibcon#about to read 5, iclass 21, count 0 2006.173.15:03:42.86#ibcon#read 5, iclass 21, count 0 2006.173.15:03:42.86#ibcon#about to read 6, iclass 21, count 0 2006.173.15:03:42.86#ibcon#read 6, iclass 21, count 0 2006.173.15:03:42.86#ibcon#end of sib2, iclass 21, count 0 2006.173.15:03:42.86#ibcon#*after write, iclass 21, count 0 2006.173.15:03:42.86#ibcon#*before return 0, iclass 21, count 0 2006.173.15:03:42.86#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.15:03:42.86#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.15:03:42.86#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.15:03:42.86#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.15:03:42.86$vck44/vblo=7,734.99 2006.173.15:03:42.86#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.15:03:42.86#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.15:03:42.86#ibcon#ireg 17 cls_cnt 0 2006.173.15:03:42.86#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.15:03:42.86#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.15:03:42.86#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.15:03:42.86#ibcon#enter wrdev, iclass 23, count 0 2006.173.15:03:42.86#ibcon#first serial, iclass 23, count 0 2006.173.15:03:42.86#ibcon#enter sib2, iclass 23, count 0 2006.173.15:03:42.86#ibcon#flushed, iclass 23, count 0 2006.173.15:03:42.86#ibcon#about to write, iclass 23, count 0 2006.173.15:03:42.86#ibcon#wrote, iclass 23, count 0 2006.173.15:03:42.86#ibcon#about to read 3, iclass 23, count 0 2006.173.15:03:42.88#ibcon#read 3, iclass 23, count 0 2006.173.15:03:42.88#ibcon#about to read 4, iclass 23, count 0 2006.173.15:03:42.88#ibcon#read 4, iclass 23, count 0 2006.173.15:03:42.88#ibcon#about to read 5, iclass 23, count 0 2006.173.15:03:42.88#ibcon#read 5, iclass 23, count 0 2006.173.15:03:42.88#ibcon#about to read 6, iclass 23, count 0 2006.173.15:03:42.88#ibcon#read 6, iclass 23, count 0 2006.173.15:03:42.88#ibcon#end of sib2, iclass 23, count 0 2006.173.15:03:42.88#ibcon#*mode == 0, iclass 23, count 0 2006.173.15:03:42.88#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.15:03:42.88#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.15:03:42.88#ibcon#*before write, iclass 23, count 0 2006.173.15:03:42.88#ibcon#enter sib2, iclass 23, count 0 2006.173.15:03:42.88#ibcon#flushed, iclass 23, count 0 2006.173.15:03:42.88#ibcon#about to write, iclass 23, count 0 2006.173.15:03:42.88#ibcon#wrote, iclass 23, count 0 2006.173.15:03:42.88#ibcon#about to read 3, iclass 23, count 0 2006.173.15:03:42.92#ibcon#read 3, iclass 23, count 0 2006.173.15:03:42.92#ibcon#about to read 4, iclass 23, count 0 2006.173.15:03:42.92#ibcon#read 4, iclass 23, count 0 2006.173.15:03:42.92#ibcon#about to read 5, iclass 23, count 0 2006.173.15:03:42.92#ibcon#read 5, iclass 23, count 0 2006.173.15:03:42.92#ibcon#about to read 6, iclass 23, count 0 2006.173.15:03:42.92#ibcon#read 6, iclass 23, count 0 2006.173.15:03:42.92#ibcon#end of sib2, iclass 23, count 0 2006.173.15:03:42.92#ibcon#*after write, iclass 23, count 0 2006.173.15:03:42.92#ibcon#*before return 0, iclass 23, count 0 2006.173.15:03:42.92#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.15:03:42.92#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.15:03:42.92#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.15:03:42.92#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.15:03:42.92$vck44/vb=7,4 2006.173.15:03:42.92#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.15:03:42.92#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.15:03:42.92#ibcon#ireg 11 cls_cnt 2 2006.173.15:03:42.92#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.15:03:42.98#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.15:03:42.98#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.15:03:42.98#ibcon#enter wrdev, iclass 25, count 2 2006.173.15:03:42.98#ibcon#first serial, iclass 25, count 2 2006.173.15:03:42.98#ibcon#enter sib2, iclass 25, count 2 2006.173.15:03:42.98#ibcon#flushed, iclass 25, count 2 2006.173.15:03:42.98#ibcon#about to write, iclass 25, count 2 2006.173.15:03:42.98#ibcon#wrote, iclass 25, count 2 2006.173.15:03:42.98#ibcon#about to read 3, iclass 25, count 2 2006.173.15:03:43.00#ibcon#read 3, iclass 25, count 2 2006.173.15:03:43.00#ibcon#about to read 4, iclass 25, count 2 2006.173.15:03:43.00#ibcon#read 4, iclass 25, count 2 2006.173.15:03:43.00#ibcon#about to read 5, iclass 25, count 2 2006.173.15:03:43.00#ibcon#read 5, iclass 25, count 2 2006.173.15:03:43.00#ibcon#about to read 6, iclass 25, count 2 2006.173.15:03:43.00#ibcon#read 6, iclass 25, count 2 2006.173.15:03:43.00#ibcon#end of sib2, iclass 25, count 2 2006.173.15:03:43.00#ibcon#*mode == 0, iclass 25, count 2 2006.173.15:03:43.00#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.15:03:43.00#ibcon#[27=AT07-04\r\n] 2006.173.15:03:43.00#ibcon#*before write, iclass 25, count 2 2006.173.15:03:43.00#ibcon#enter sib2, iclass 25, count 2 2006.173.15:03:43.00#ibcon#flushed, iclass 25, count 2 2006.173.15:03:43.00#ibcon#about to write, iclass 25, count 2 2006.173.15:03:43.00#ibcon#wrote, iclass 25, count 2 2006.173.15:03:43.00#ibcon#about to read 3, iclass 25, count 2 2006.173.15:03:43.03#ibcon#read 3, iclass 25, count 2 2006.173.15:03:43.03#ibcon#about to read 4, iclass 25, count 2 2006.173.15:03:43.03#ibcon#read 4, iclass 25, count 2 2006.173.15:03:43.03#ibcon#about to read 5, iclass 25, count 2 2006.173.15:03:43.03#ibcon#read 5, iclass 25, count 2 2006.173.15:03:43.03#ibcon#about to read 6, iclass 25, count 2 2006.173.15:03:43.03#ibcon#read 6, iclass 25, count 2 2006.173.15:03:43.03#ibcon#end of sib2, iclass 25, count 2 2006.173.15:03:43.03#ibcon#*after write, iclass 25, count 2 2006.173.15:03:43.03#ibcon#*before return 0, iclass 25, count 2 2006.173.15:03:43.03#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.15:03:43.03#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.15:03:43.03#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.15:03:43.03#ibcon#ireg 7 cls_cnt 0 2006.173.15:03:43.03#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.15:03:43.15#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.15:03:43.15#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.15:03:43.15#ibcon#enter wrdev, iclass 25, count 0 2006.173.15:03:43.15#ibcon#first serial, iclass 25, count 0 2006.173.15:03:43.15#ibcon#enter sib2, iclass 25, count 0 2006.173.15:03:43.15#ibcon#flushed, iclass 25, count 0 2006.173.15:03:43.15#ibcon#about to write, iclass 25, count 0 2006.173.15:03:43.15#ibcon#wrote, iclass 25, count 0 2006.173.15:03:43.15#ibcon#about to read 3, iclass 25, count 0 2006.173.15:03:43.17#ibcon#read 3, iclass 25, count 0 2006.173.15:03:43.17#ibcon#about to read 4, iclass 25, count 0 2006.173.15:03:43.17#ibcon#read 4, iclass 25, count 0 2006.173.15:03:43.17#ibcon#about to read 5, iclass 25, count 0 2006.173.15:03:43.17#ibcon#read 5, iclass 25, count 0 2006.173.15:03:43.17#ibcon#about to read 6, iclass 25, count 0 2006.173.15:03:43.17#ibcon#read 6, iclass 25, count 0 2006.173.15:03:43.17#ibcon#end of sib2, iclass 25, count 0 2006.173.15:03:43.17#ibcon#*mode == 0, iclass 25, count 0 2006.173.15:03:43.17#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.15:03:43.17#ibcon#[27=USB\r\n] 2006.173.15:03:43.17#ibcon#*before write, iclass 25, count 0 2006.173.15:03:43.17#ibcon#enter sib2, iclass 25, count 0 2006.173.15:03:43.17#ibcon#flushed, iclass 25, count 0 2006.173.15:03:43.17#ibcon#about to write, iclass 25, count 0 2006.173.15:03:43.17#ibcon#wrote, iclass 25, count 0 2006.173.15:03:43.17#ibcon#about to read 3, iclass 25, count 0 2006.173.15:03:43.20#ibcon#read 3, iclass 25, count 0 2006.173.15:03:43.20#ibcon#about to read 4, iclass 25, count 0 2006.173.15:03:43.20#ibcon#read 4, iclass 25, count 0 2006.173.15:03:43.20#ibcon#about to read 5, iclass 25, count 0 2006.173.15:03:43.20#ibcon#read 5, iclass 25, count 0 2006.173.15:03:43.20#ibcon#about to read 6, iclass 25, count 0 2006.173.15:03:43.20#ibcon#read 6, iclass 25, count 0 2006.173.15:03:43.20#ibcon#end of sib2, iclass 25, count 0 2006.173.15:03:43.20#ibcon#*after write, iclass 25, count 0 2006.173.15:03:43.20#ibcon#*before return 0, iclass 25, count 0 2006.173.15:03:43.20#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.15:03:43.20#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.15:03:43.20#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.15:03:43.20#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.15:03:43.20$vck44/vblo=8,744.99 2006.173.15:03:43.20#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.15:03:43.20#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.15:03:43.20#ibcon#ireg 17 cls_cnt 0 2006.173.15:03:43.20#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.15:03:43.20#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.15:03:43.20#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.15:03:43.20#ibcon#enter wrdev, iclass 27, count 0 2006.173.15:03:43.20#ibcon#first serial, iclass 27, count 0 2006.173.15:03:43.20#ibcon#enter sib2, iclass 27, count 0 2006.173.15:03:43.20#ibcon#flushed, iclass 27, count 0 2006.173.15:03:43.20#ibcon#about to write, iclass 27, count 0 2006.173.15:03:43.20#ibcon#wrote, iclass 27, count 0 2006.173.15:03:43.20#ibcon#about to read 3, iclass 27, count 0 2006.173.15:03:43.22#ibcon#read 3, iclass 27, count 0 2006.173.15:03:43.22#ibcon#about to read 4, iclass 27, count 0 2006.173.15:03:43.22#ibcon#read 4, iclass 27, count 0 2006.173.15:03:43.22#ibcon#about to read 5, iclass 27, count 0 2006.173.15:03:43.22#ibcon#read 5, iclass 27, count 0 2006.173.15:03:43.22#ibcon#about to read 6, iclass 27, count 0 2006.173.15:03:43.22#ibcon#read 6, iclass 27, count 0 2006.173.15:03:43.22#ibcon#end of sib2, iclass 27, count 0 2006.173.15:03:43.22#ibcon#*mode == 0, iclass 27, count 0 2006.173.15:03:43.22#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.15:03:43.22#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.15:03:43.22#ibcon#*before write, iclass 27, count 0 2006.173.15:03:43.22#ibcon#enter sib2, iclass 27, count 0 2006.173.15:03:43.22#ibcon#flushed, iclass 27, count 0 2006.173.15:03:43.22#ibcon#about to write, iclass 27, count 0 2006.173.15:03:43.22#ibcon#wrote, iclass 27, count 0 2006.173.15:03:43.22#ibcon#about to read 3, iclass 27, count 0 2006.173.15:03:43.26#ibcon#read 3, iclass 27, count 0 2006.173.15:03:43.26#ibcon#about to read 4, iclass 27, count 0 2006.173.15:03:43.26#ibcon#read 4, iclass 27, count 0 2006.173.15:03:43.26#ibcon#about to read 5, iclass 27, count 0 2006.173.15:03:43.26#ibcon#read 5, iclass 27, count 0 2006.173.15:03:43.26#ibcon#about to read 6, iclass 27, count 0 2006.173.15:03:43.26#ibcon#read 6, iclass 27, count 0 2006.173.15:03:43.26#ibcon#end of sib2, iclass 27, count 0 2006.173.15:03:43.26#ibcon#*after write, iclass 27, count 0 2006.173.15:03:43.26#ibcon#*before return 0, iclass 27, count 0 2006.173.15:03:43.26#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.15:03:43.26#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.15:03:43.26#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.15:03:43.26#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.15:03:43.26$vck44/vb=8,4 2006.173.15:03:43.26#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.15:03:43.26#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.15:03:43.26#ibcon#ireg 11 cls_cnt 2 2006.173.15:03:43.26#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.15:03:43.32#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.15:03:43.32#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.15:03:43.32#ibcon#enter wrdev, iclass 29, count 2 2006.173.15:03:43.32#ibcon#first serial, iclass 29, count 2 2006.173.15:03:43.32#ibcon#enter sib2, iclass 29, count 2 2006.173.15:03:43.32#ibcon#flushed, iclass 29, count 2 2006.173.15:03:43.32#ibcon#about to write, iclass 29, count 2 2006.173.15:03:43.32#ibcon#wrote, iclass 29, count 2 2006.173.15:03:43.32#ibcon#about to read 3, iclass 29, count 2 2006.173.15:03:43.34#ibcon#read 3, iclass 29, count 2 2006.173.15:03:43.34#ibcon#about to read 4, iclass 29, count 2 2006.173.15:03:43.34#ibcon#read 4, iclass 29, count 2 2006.173.15:03:43.34#ibcon#about to read 5, iclass 29, count 2 2006.173.15:03:43.34#ibcon#read 5, iclass 29, count 2 2006.173.15:03:43.34#ibcon#about to read 6, iclass 29, count 2 2006.173.15:03:43.34#ibcon#read 6, iclass 29, count 2 2006.173.15:03:43.34#ibcon#end of sib2, iclass 29, count 2 2006.173.15:03:43.34#ibcon#*mode == 0, iclass 29, count 2 2006.173.15:03:43.34#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.15:03:43.34#ibcon#[27=AT08-04\r\n] 2006.173.15:03:43.34#ibcon#*before write, iclass 29, count 2 2006.173.15:03:43.34#ibcon#enter sib2, iclass 29, count 2 2006.173.15:03:43.34#ibcon#flushed, iclass 29, count 2 2006.173.15:03:43.34#ibcon#about to write, iclass 29, count 2 2006.173.15:03:43.34#ibcon#wrote, iclass 29, count 2 2006.173.15:03:43.34#ibcon#about to read 3, iclass 29, count 2 2006.173.15:03:43.37#ibcon#read 3, iclass 29, count 2 2006.173.15:03:43.37#ibcon#about to read 4, iclass 29, count 2 2006.173.15:03:43.37#ibcon#read 4, iclass 29, count 2 2006.173.15:03:43.37#ibcon#about to read 5, iclass 29, count 2 2006.173.15:03:43.37#ibcon#read 5, iclass 29, count 2 2006.173.15:03:43.37#ibcon#about to read 6, iclass 29, count 2 2006.173.15:03:43.37#ibcon#read 6, iclass 29, count 2 2006.173.15:03:43.37#ibcon#end of sib2, iclass 29, count 2 2006.173.15:03:43.37#ibcon#*after write, iclass 29, count 2 2006.173.15:03:43.37#ibcon#*before return 0, iclass 29, count 2 2006.173.15:03:43.37#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.15:03:43.37#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.15:03:43.37#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.15:03:43.37#ibcon#ireg 7 cls_cnt 0 2006.173.15:03:43.37#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.15:03:43.49#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.15:03:43.49#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.15:03:43.49#ibcon#enter wrdev, iclass 29, count 0 2006.173.15:03:43.49#ibcon#first serial, iclass 29, count 0 2006.173.15:03:43.49#ibcon#enter sib2, iclass 29, count 0 2006.173.15:03:43.49#ibcon#flushed, iclass 29, count 0 2006.173.15:03:43.49#ibcon#about to write, iclass 29, count 0 2006.173.15:03:43.49#ibcon#wrote, iclass 29, count 0 2006.173.15:03:43.49#ibcon#about to read 3, iclass 29, count 0 2006.173.15:03:43.51#ibcon#read 3, iclass 29, count 0 2006.173.15:03:43.51#ibcon#about to read 4, iclass 29, count 0 2006.173.15:03:43.51#ibcon#read 4, iclass 29, count 0 2006.173.15:03:43.51#ibcon#about to read 5, iclass 29, count 0 2006.173.15:03:43.51#ibcon#read 5, iclass 29, count 0 2006.173.15:03:43.51#ibcon#about to read 6, iclass 29, count 0 2006.173.15:03:43.51#ibcon#read 6, iclass 29, count 0 2006.173.15:03:43.51#ibcon#end of sib2, iclass 29, count 0 2006.173.15:03:43.51#ibcon#*mode == 0, iclass 29, count 0 2006.173.15:03:43.51#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.15:03:43.51#ibcon#[27=USB\r\n] 2006.173.15:03:43.51#ibcon#*before write, iclass 29, count 0 2006.173.15:03:43.51#ibcon#enter sib2, iclass 29, count 0 2006.173.15:03:43.51#ibcon#flushed, iclass 29, count 0 2006.173.15:03:43.51#ibcon#about to write, iclass 29, count 0 2006.173.15:03:43.51#ibcon#wrote, iclass 29, count 0 2006.173.15:03:43.51#ibcon#about to read 3, iclass 29, count 0 2006.173.15:03:43.54#ibcon#read 3, iclass 29, count 0 2006.173.15:03:43.54#ibcon#about to read 4, iclass 29, count 0 2006.173.15:03:43.54#ibcon#read 4, iclass 29, count 0 2006.173.15:03:43.54#ibcon#about to read 5, iclass 29, count 0 2006.173.15:03:43.54#ibcon#read 5, iclass 29, count 0 2006.173.15:03:43.54#ibcon#about to read 6, iclass 29, count 0 2006.173.15:03:43.54#ibcon#read 6, iclass 29, count 0 2006.173.15:03:43.54#ibcon#end of sib2, iclass 29, count 0 2006.173.15:03:43.54#ibcon#*after write, iclass 29, count 0 2006.173.15:03:43.54#ibcon#*before return 0, iclass 29, count 0 2006.173.15:03:43.54#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.15:03:43.54#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.15:03:43.54#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.15:03:43.54#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.15:03:43.54$vck44/vabw=wide 2006.173.15:03:43.54#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.15:03:43.54#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.15:03:43.54#ibcon#ireg 8 cls_cnt 0 2006.173.15:03:43.54#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.15:03:43.54#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.15:03:43.54#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.15:03:43.54#ibcon#enter wrdev, iclass 31, count 0 2006.173.15:03:43.54#ibcon#first serial, iclass 31, count 0 2006.173.15:03:43.54#ibcon#enter sib2, iclass 31, count 0 2006.173.15:03:43.54#ibcon#flushed, iclass 31, count 0 2006.173.15:03:43.54#ibcon#about to write, iclass 31, count 0 2006.173.15:03:43.54#ibcon#wrote, iclass 31, count 0 2006.173.15:03:43.54#ibcon#about to read 3, iclass 31, count 0 2006.173.15:03:43.56#ibcon#read 3, iclass 31, count 0 2006.173.15:03:43.56#ibcon#about to read 4, iclass 31, count 0 2006.173.15:03:43.56#ibcon#read 4, iclass 31, count 0 2006.173.15:03:43.56#ibcon#about to read 5, iclass 31, count 0 2006.173.15:03:43.56#ibcon#read 5, iclass 31, count 0 2006.173.15:03:43.56#ibcon#about to read 6, iclass 31, count 0 2006.173.15:03:43.56#ibcon#read 6, iclass 31, count 0 2006.173.15:03:43.56#ibcon#end of sib2, iclass 31, count 0 2006.173.15:03:43.56#ibcon#*mode == 0, iclass 31, count 0 2006.173.15:03:43.56#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.15:03:43.56#ibcon#[25=BW32\r\n] 2006.173.15:03:43.56#ibcon#*before write, iclass 31, count 0 2006.173.15:03:43.56#ibcon#enter sib2, iclass 31, count 0 2006.173.15:03:43.56#ibcon#flushed, iclass 31, count 0 2006.173.15:03:43.56#ibcon#about to write, iclass 31, count 0 2006.173.15:03:43.56#ibcon#wrote, iclass 31, count 0 2006.173.15:03:43.56#ibcon#about to read 3, iclass 31, count 0 2006.173.15:03:43.59#ibcon#read 3, iclass 31, count 0 2006.173.15:03:43.59#ibcon#about to read 4, iclass 31, count 0 2006.173.15:03:43.59#ibcon#read 4, iclass 31, count 0 2006.173.15:03:43.59#ibcon#about to read 5, iclass 31, count 0 2006.173.15:03:43.59#ibcon#read 5, iclass 31, count 0 2006.173.15:03:43.59#ibcon#about to read 6, iclass 31, count 0 2006.173.15:03:43.59#ibcon#read 6, iclass 31, count 0 2006.173.15:03:43.59#ibcon#end of sib2, iclass 31, count 0 2006.173.15:03:43.59#ibcon#*after write, iclass 31, count 0 2006.173.15:03:43.59#ibcon#*before return 0, iclass 31, count 0 2006.173.15:03:43.59#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.15:03:43.59#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.15:03:43.59#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.15:03:43.59#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.15:03:43.59$vck44/vbbw=wide 2006.173.15:03:43.59#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.15:03:43.59#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.15:03:43.59#ibcon#ireg 8 cls_cnt 0 2006.173.15:03:43.59#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.15:03:43.66#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.15:03:43.66#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.15:03:43.66#ibcon#enter wrdev, iclass 33, count 0 2006.173.15:03:43.66#ibcon#first serial, iclass 33, count 0 2006.173.15:03:43.66#ibcon#enter sib2, iclass 33, count 0 2006.173.15:03:43.66#ibcon#flushed, iclass 33, count 0 2006.173.15:03:43.66#ibcon#about to write, iclass 33, count 0 2006.173.15:03:43.66#ibcon#wrote, iclass 33, count 0 2006.173.15:03:43.66#ibcon#about to read 3, iclass 33, count 0 2006.173.15:03:43.68#ibcon#read 3, iclass 33, count 0 2006.173.15:03:43.68#ibcon#about to read 4, iclass 33, count 0 2006.173.15:03:43.68#ibcon#read 4, iclass 33, count 0 2006.173.15:03:43.68#ibcon#about to read 5, iclass 33, count 0 2006.173.15:03:43.68#ibcon#read 5, iclass 33, count 0 2006.173.15:03:43.68#ibcon#about to read 6, iclass 33, count 0 2006.173.15:03:43.68#ibcon#read 6, iclass 33, count 0 2006.173.15:03:43.68#ibcon#end of sib2, iclass 33, count 0 2006.173.15:03:43.68#ibcon#*mode == 0, iclass 33, count 0 2006.173.15:03:43.68#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.15:03:43.68#ibcon#[27=BW32\r\n] 2006.173.15:03:43.68#ibcon#*before write, iclass 33, count 0 2006.173.15:03:43.68#ibcon#enter sib2, iclass 33, count 0 2006.173.15:03:43.68#ibcon#flushed, iclass 33, count 0 2006.173.15:03:43.68#ibcon#about to write, iclass 33, count 0 2006.173.15:03:43.68#ibcon#wrote, iclass 33, count 0 2006.173.15:03:43.68#ibcon#about to read 3, iclass 33, count 0 2006.173.15:03:43.71#ibcon#read 3, iclass 33, count 0 2006.173.15:03:43.71#ibcon#about to read 4, iclass 33, count 0 2006.173.15:03:43.71#ibcon#read 4, iclass 33, count 0 2006.173.15:03:43.71#ibcon#about to read 5, iclass 33, count 0 2006.173.15:03:43.71#ibcon#read 5, iclass 33, count 0 2006.173.15:03:43.71#ibcon#about to read 6, iclass 33, count 0 2006.173.15:03:43.71#ibcon#read 6, iclass 33, count 0 2006.173.15:03:43.71#ibcon#end of sib2, iclass 33, count 0 2006.173.15:03:43.71#ibcon#*after write, iclass 33, count 0 2006.173.15:03:43.71#ibcon#*before return 0, iclass 33, count 0 2006.173.15:03:43.71#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.15:03:43.71#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.15:03:43.71#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.15:03:43.71#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.15:03:43.71$setupk4/ifdk4 2006.173.15:03:43.71$ifdk4/lo= 2006.173.15:03:43.71$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.15:03:43.71$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.15:03:43.71$ifdk4/patch= 2006.173.15:03:43.71$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.15:03:43.71$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.15:03:43.71$setupk4/!*+20s 2006.173.15:03:47.24#abcon#<5=/06 1.6 3.4 20.931001003.2\r\n> 2006.173.15:03:47.26#abcon#{5=INTERFACE CLEAR} 2006.173.15:03:47.32#abcon#[5=S1D000X0/0*\r\n] 2006.173.15:03:48.14#trakl#Source acquired 2006.173.15:03:48.14#flagr#flagr/antenna,acquired 2006.173.15:03:57.41#abcon#<5=/06 1.7 3.4 20.921001003.2\r\n> 2006.173.15:03:57.43#abcon#{5=INTERFACE CLEAR} 2006.173.15:03:57.49#abcon#[5=S1D000X0/0*\r\n] 2006.173.15:03:58.18$setupk4/"tpicd 2006.173.15:03:58.18$setupk4/echo=off 2006.173.15:03:58.18$setupk4/xlog=off 2006.173.15:03:58.18:!2006.173.15:08:10 2006.173.15:08:10.00:preob 2006.173.15:08:10.14/onsource/TRACKING 2006.173.15:08:10.14:!2006.173.15:08:20 2006.173.15:08:20.00:"tape 2006.173.15:08:20.00:"st=record 2006.173.15:08:20.00:data_valid=on 2006.173.15:08:20.00:midob 2006.173.15:08:21.14/onsource/TRACKING 2006.173.15:08:21.14/wx/20.96,1003.0,100 2006.173.15:08:21.25/cable/+6.5100E-03 2006.173.15:08:22.34/va/01,07,usb,yes,51,55 2006.173.15:08:22.34/va/02,06,usb,yes,51,52 2006.173.15:08:22.34/va/03,05,usb,yes,64,66 2006.173.15:08:22.34/va/04,06,usb,yes,52,55 2006.173.15:08:22.34/va/05,04,usb,yes,41,42 2006.173.15:08:22.34/va/06,03,usb,yes,57,57 2006.173.15:08:22.34/va/07,04,usb,yes,47,48 2006.173.15:08:22.34/va/08,04,usb,yes,40,48 2006.173.15:08:22.57/valo/01,524.99,yes,locked 2006.173.15:08:22.57/valo/02,534.99,yes,locked 2006.173.15:08:22.57/valo/03,564.99,yes,locked 2006.173.15:08:22.57/valo/04,624.99,yes,locked 2006.173.15:08:22.57/valo/05,734.99,yes,locked 2006.173.15:08:22.57/valo/06,814.99,yes,locked 2006.173.15:08:22.57/valo/07,864.99,yes,locked 2006.173.15:08:22.57/valo/08,884.99,yes,locked 2006.173.15:08:23.66/vb/01,04,usb,yes,36,33 2006.173.15:08:23.66/vb/02,04,usb,yes,39,39 2006.173.15:08:23.66/vb/03,04,usb,yes,36,39 2006.173.15:08:23.66/vb/04,04,usb,yes,41,39 2006.173.15:08:23.66/vb/05,04,usb,yes,32,35 2006.173.15:08:23.66/vb/06,04,usb,yes,37,33 2006.173.15:08:23.66/vb/07,04,usb,yes,37,37 2006.173.15:08:23.66/vb/08,04,usb,yes,34,38 2006.173.15:08:23.89/vblo/01,629.99,yes,locked 2006.173.15:08:23.89/vblo/02,634.99,yes,locked 2006.173.15:08:23.89/vblo/03,649.99,yes,locked 2006.173.15:08:23.89/vblo/04,679.99,yes,locked 2006.173.15:08:23.89/vblo/05,709.99,yes,locked 2006.173.15:08:23.89/vblo/06,719.99,yes,locked 2006.173.15:08:23.89/vblo/07,734.99,yes,locked 2006.173.15:08:23.89/vblo/08,744.99,yes,locked 2006.173.15:08:24.04/vabw/8 2006.173.15:08:24.19/vbbw/8 2006.173.15:08:24.28/xfe/off,on,15.2 2006.173.15:08:24.66/ifatt/23,28,28,28 2006.173.15:08:25.07/fmout-gps/S +4.00E-07 2006.173.15:08:25.11:!2006.173.15:09:00 2006.173.15:09:00.00:data_valid=off 2006.173.15:09:00.00:"et 2006.173.15:09:00.00:!+3s 2006.173.15:09:03.01:"tape 2006.173.15:09:03.01:postob 2006.173.15:09:03.13/cable/+6.5087E-03 2006.173.15:09:03.13/wx/20.97,1003.0,100 2006.173.15:09:04.07/fmout-gps/S +4.00E-07 2006.173.15:09:04.07:scan_name=173-1510,jd0606,40 2006.173.15:09:04.07:source=1954-388,195800.00,-384506.4,2000.0,cw 2006.173.15:09:05.13#flagr#flagr/antenna,new-source 2006.173.15:09:05.13:checkk5 2006.173.15:09:05.49/chk_autoobs//k5ts1/ autoobs is running! 2006.173.15:09:05.89/chk_autoobs//k5ts2/ autoobs is running! 2006.173.15:09:06.31/chk_autoobs//k5ts3/ autoobs is running! 2006.173.15:09:06.70/chk_autoobs//k5ts4/ autoobs is running! 2006.173.15:09:07.09/chk_obsdata//k5ts1/T1731508??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.15:09:07.48/chk_obsdata//k5ts2/T1731508??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.15:09:07.88/chk_obsdata//k5ts3/T1731508??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.15:09:08.28/chk_obsdata//k5ts4/T1731508??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.15:09:09.00/k5log//k5ts1_log_newline 2006.173.15:09:09.70/k5log//k5ts2_log_newline 2006.173.15:09:10.40/k5log//k5ts3_log_newline 2006.173.15:09:11.11/k5log//k5ts4_log_newline 2006.173.15:09:11.14/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.15:09:11.14:setupk4=1 2006.173.15:09:11.14$setupk4/echo=on 2006.173.15:09:11.14$setupk4/pcalon 2006.173.15:09:11.14$pcalon/"no phase cal control is implemented here 2006.173.15:09:11.14$setupk4/"tpicd=stop 2006.173.15:09:11.14$setupk4/"rec=synch_on 2006.173.15:09:11.14$setupk4/"rec_mode=128 2006.173.15:09:11.14$setupk4/!* 2006.173.15:09:11.14$setupk4/recpk4 2006.173.15:09:11.14$recpk4/recpatch= 2006.173.15:09:11.14$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.15:09:11.14$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.15:09:11.14$setupk4/vck44 2006.173.15:09:11.14$vck44/valo=1,524.99 2006.173.15:09:11.14#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.15:09:11.14#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.15:09:11.14#ibcon#ireg 17 cls_cnt 0 2006.173.15:09:11.14#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.15:09:11.14#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.15:09:11.14#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.15:09:11.14#ibcon#enter wrdev, iclass 22, count 0 2006.173.15:09:11.14#ibcon#first serial, iclass 22, count 0 2006.173.15:09:11.14#ibcon#enter sib2, iclass 22, count 0 2006.173.15:09:11.14#ibcon#flushed, iclass 22, count 0 2006.173.15:09:11.14#ibcon#about to write, iclass 22, count 0 2006.173.15:09:11.14#ibcon#wrote, iclass 22, count 0 2006.173.15:09:11.14#ibcon#about to read 3, iclass 22, count 0 2006.173.15:09:11.16#ibcon#read 3, iclass 22, count 0 2006.173.15:09:11.16#ibcon#about to read 4, iclass 22, count 0 2006.173.15:09:11.16#ibcon#read 4, iclass 22, count 0 2006.173.15:09:11.16#ibcon#about to read 5, iclass 22, count 0 2006.173.15:09:11.16#ibcon#read 5, iclass 22, count 0 2006.173.15:09:11.16#ibcon#about to read 6, iclass 22, count 0 2006.173.15:09:11.16#ibcon#read 6, iclass 22, count 0 2006.173.15:09:11.16#ibcon#end of sib2, iclass 22, count 0 2006.173.15:09:11.16#ibcon#*mode == 0, iclass 22, count 0 2006.173.15:09:11.16#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.15:09:11.16#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.15:09:11.16#ibcon#*before write, iclass 22, count 0 2006.173.15:09:11.16#ibcon#enter sib2, iclass 22, count 0 2006.173.15:09:11.16#ibcon#flushed, iclass 22, count 0 2006.173.15:09:11.16#ibcon#about to write, iclass 22, count 0 2006.173.15:09:11.16#ibcon#wrote, iclass 22, count 0 2006.173.15:09:11.16#ibcon#about to read 3, iclass 22, count 0 2006.173.15:09:11.21#ibcon#read 3, iclass 22, count 0 2006.173.15:09:11.21#ibcon#about to read 4, iclass 22, count 0 2006.173.15:09:11.21#ibcon#read 4, iclass 22, count 0 2006.173.15:09:11.21#ibcon#about to read 5, iclass 22, count 0 2006.173.15:09:11.21#ibcon#read 5, iclass 22, count 0 2006.173.15:09:11.21#ibcon#about to read 6, iclass 22, count 0 2006.173.15:09:11.21#ibcon#read 6, iclass 22, count 0 2006.173.15:09:11.21#ibcon#end of sib2, iclass 22, count 0 2006.173.15:09:11.21#ibcon#*after write, iclass 22, count 0 2006.173.15:09:11.21#ibcon#*before return 0, iclass 22, count 0 2006.173.15:09:11.21#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.15:09:11.21#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.15:09:11.21#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.15:09:11.21#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.15:09:11.21$vck44/va=1,7 2006.173.15:09:11.21#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.15:09:11.21#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.15:09:11.21#ibcon#ireg 11 cls_cnt 2 2006.173.15:09:11.21#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.15:09:11.21#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.15:09:11.21#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.15:09:11.21#ibcon#enter wrdev, iclass 24, count 2 2006.173.15:09:11.21#ibcon#first serial, iclass 24, count 2 2006.173.15:09:11.21#ibcon#enter sib2, iclass 24, count 2 2006.173.15:09:11.21#ibcon#flushed, iclass 24, count 2 2006.173.15:09:11.21#ibcon#about to write, iclass 24, count 2 2006.173.15:09:11.21#ibcon#wrote, iclass 24, count 2 2006.173.15:09:11.21#ibcon#about to read 3, iclass 24, count 2 2006.173.15:09:11.23#ibcon#read 3, iclass 24, count 2 2006.173.15:09:11.23#ibcon#about to read 4, iclass 24, count 2 2006.173.15:09:11.23#ibcon#read 4, iclass 24, count 2 2006.173.15:09:11.23#ibcon#about to read 5, iclass 24, count 2 2006.173.15:09:11.23#ibcon#read 5, iclass 24, count 2 2006.173.15:09:11.23#ibcon#about to read 6, iclass 24, count 2 2006.173.15:09:11.23#ibcon#read 6, iclass 24, count 2 2006.173.15:09:11.23#ibcon#end of sib2, iclass 24, count 2 2006.173.15:09:11.23#ibcon#*mode == 0, iclass 24, count 2 2006.173.15:09:11.23#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.15:09:11.23#ibcon#[25=AT01-07\r\n] 2006.173.15:09:11.23#ibcon#*before write, iclass 24, count 2 2006.173.15:09:11.23#ibcon#enter sib2, iclass 24, count 2 2006.173.15:09:11.23#ibcon#flushed, iclass 24, count 2 2006.173.15:09:11.23#ibcon#about to write, iclass 24, count 2 2006.173.15:09:11.23#ibcon#wrote, iclass 24, count 2 2006.173.15:09:11.23#ibcon#about to read 3, iclass 24, count 2 2006.173.15:09:11.26#ibcon#read 3, iclass 24, count 2 2006.173.15:09:11.26#ibcon#about to read 4, iclass 24, count 2 2006.173.15:09:11.26#ibcon#read 4, iclass 24, count 2 2006.173.15:09:11.26#ibcon#about to read 5, iclass 24, count 2 2006.173.15:09:11.26#ibcon#read 5, iclass 24, count 2 2006.173.15:09:11.26#ibcon#about to read 6, iclass 24, count 2 2006.173.15:09:11.26#ibcon#read 6, iclass 24, count 2 2006.173.15:09:11.26#ibcon#end of sib2, iclass 24, count 2 2006.173.15:09:11.26#ibcon#*after write, iclass 24, count 2 2006.173.15:09:11.26#ibcon#*before return 0, iclass 24, count 2 2006.173.15:09:11.26#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.15:09:11.26#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.15:09:11.26#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.15:09:11.26#ibcon#ireg 7 cls_cnt 0 2006.173.15:09:11.26#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.15:09:11.38#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.15:09:11.38#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.15:09:11.38#ibcon#enter wrdev, iclass 24, count 0 2006.173.15:09:11.38#ibcon#first serial, iclass 24, count 0 2006.173.15:09:11.38#ibcon#enter sib2, iclass 24, count 0 2006.173.15:09:11.38#ibcon#flushed, iclass 24, count 0 2006.173.15:09:11.38#ibcon#about to write, iclass 24, count 0 2006.173.15:09:11.38#ibcon#wrote, iclass 24, count 0 2006.173.15:09:11.38#ibcon#about to read 3, iclass 24, count 0 2006.173.15:09:11.40#ibcon#read 3, iclass 24, count 0 2006.173.15:09:11.40#ibcon#about to read 4, iclass 24, count 0 2006.173.15:09:11.40#ibcon#read 4, iclass 24, count 0 2006.173.15:09:11.40#ibcon#about to read 5, iclass 24, count 0 2006.173.15:09:11.40#ibcon#read 5, iclass 24, count 0 2006.173.15:09:11.40#ibcon#about to read 6, iclass 24, count 0 2006.173.15:09:11.40#ibcon#read 6, iclass 24, count 0 2006.173.15:09:11.40#ibcon#end of sib2, iclass 24, count 0 2006.173.15:09:11.40#ibcon#*mode == 0, iclass 24, count 0 2006.173.15:09:11.40#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.15:09:11.40#ibcon#[25=USB\r\n] 2006.173.15:09:11.40#ibcon#*before write, iclass 24, count 0 2006.173.15:09:11.40#ibcon#enter sib2, iclass 24, count 0 2006.173.15:09:11.40#ibcon#flushed, iclass 24, count 0 2006.173.15:09:11.40#ibcon#about to write, iclass 24, count 0 2006.173.15:09:11.40#ibcon#wrote, iclass 24, count 0 2006.173.15:09:11.40#ibcon#about to read 3, iclass 24, count 0 2006.173.15:09:11.43#ibcon#read 3, iclass 24, count 0 2006.173.15:09:11.43#ibcon#about to read 4, iclass 24, count 0 2006.173.15:09:11.43#ibcon#read 4, iclass 24, count 0 2006.173.15:09:11.43#ibcon#about to read 5, iclass 24, count 0 2006.173.15:09:11.43#ibcon#read 5, iclass 24, count 0 2006.173.15:09:11.43#ibcon#about to read 6, iclass 24, count 0 2006.173.15:09:11.43#ibcon#read 6, iclass 24, count 0 2006.173.15:09:11.43#ibcon#end of sib2, iclass 24, count 0 2006.173.15:09:11.43#ibcon#*after write, iclass 24, count 0 2006.173.15:09:11.43#ibcon#*before return 0, iclass 24, count 0 2006.173.15:09:11.43#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.15:09:11.43#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.15:09:11.43#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.15:09:11.43#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.15:09:11.43$vck44/valo=2,534.99 2006.173.15:09:11.43#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.15:09:11.43#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.15:09:11.43#ibcon#ireg 17 cls_cnt 0 2006.173.15:09:11.43#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.15:09:11.43#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.15:09:11.43#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.15:09:11.43#ibcon#enter wrdev, iclass 26, count 0 2006.173.15:09:11.43#ibcon#first serial, iclass 26, count 0 2006.173.15:09:11.43#ibcon#enter sib2, iclass 26, count 0 2006.173.15:09:11.43#ibcon#flushed, iclass 26, count 0 2006.173.15:09:11.43#ibcon#about to write, iclass 26, count 0 2006.173.15:09:11.43#ibcon#wrote, iclass 26, count 0 2006.173.15:09:11.43#ibcon#about to read 3, iclass 26, count 0 2006.173.15:09:11.45#ibcon#read 3, iclass 26, count 0 2006.173.15:09:11.45#ibcon#about to read 4, iclass 26, count 0 2006.173.15:09:11.45#ibcon#read 4, iclass 26, count 0 2006.173.15:09:11.45#ibcon#about to read 5, iclass 26, count 0 2006.173.15:09:11.45#ibcon#read 5, iclass 26, count 0 2006.173.15:09:11.45#ibcon#about to read 6, iclass 26, count 0 2006.173.15:09:11.45#ibcon#read 6, iclass 26, count 0 2006.173.15:09:11.45#ibcon#end of sib2, iclass 26, count 0 2006.173.15:09:11.45#ibcon#*mode == 0, iclass 26, count 0 2006.173.15:09:11.45#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.15:09:11.45#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.15:09:11.45#ibcon#*before write, iclass 26, count 0 2006.173.15:09:11.45#ibcon#enter sib2, iclass 26, count 0 2006.173.15:09:11.45#ibcon#flushed, iclass 26, count 0 2006.173.15:09:11.45#ibcon#about to write, iclass 26, count 0 2006.173.15:09:11.45#ibcon#wrote, iclass 26, count 0 2006.173.15:09:11.45#ibcon#about to read 3, iclass 26, count 0 2006.173.15:09:11.49#ibcon#read 3, iclass 26, count 0 2006.173.15:09:11.49#ibcon#about to read 4, iclass 26, count 0 2006.173.15:09:11.49#ibcon#read 4, iclass 26, count 0 2006.173.15:09:11.49#ibcon#about to read 5, iclass 26, count 0 2006.173.15:09:11.49#ibcon#read 5, iclass 26, count 0 2006.173.15:09:11.49#ibcon#about to read 6, iclass 26, count 0 2006.173.15:09:11.49#ibcon#read 6, iclass 26, count 0 2006.173.15:09:11.49#ibcon#end of sib2, iclass 26, count 0 2006.173.15:09:11.49#ibcon#*after write, iclass 26, count 0 2006.173.15:09:11.49#ibcon#*before return 0, iclass 26, count 0 2006.173.15:09:11.49#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.15:09:11.49#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.15:09:11.49#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.15:09:11.49#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.15:09:11.49$vck44/va=2,6 2006.173.15:09:11.49#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.15:09:11.49#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.15:09:11.49#ibcon#ireg 11 cls_cnt 2 2006.173.15:09:11.49#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.15:09:11.55#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.15:09:11.55#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.15:09:11.55#ibcon#enter wrdev, iclass 28, count 2 2006.173.15:09:11.55#ibcon#first serial, iclass 28, count 2 2006.173.15:09:11.55#ibcon#enter sib2, iclass 28, count 2 2006.173.15:09:11.55#ibcon#flushed, iclass 28, count 2 2006.173.15:09:11.55#ibcon#about to write, iclass 28, count 2 2006.173.15:09:11.55#ibcon#wrote, iclass 28, count 2 2006.173.15:09:11.55#ibcon#about to read 3, iclass 28, count 2 2006.173.15:09:11.57#ibcon#read 3, iclass 28, count 2 2006.173.15:09:11.57#ibcon#about to read 4, iclass 28, count 2 2006.173.15:09:11.57#ibcon#read 4, iclass 28, count 2 2006.173.15:09:11.57#ibcon#about to read 5, iclass 28, count 2 2006.173.15:09:11.57#ibcon#read 5, iclass 28, count 2 2006.173.15:09:11.57#ibcon#about to read 6, iclass 28, count 2 2006.173.15:09:11.57#ibcon#read 6, iclass 28, count 2 2006.173.15:09:11.57#ibcon#end of sib2, iclass 28, count 2 2006.173.15:09:11.57#ibcon#*mode == 0, iclass 28, count 2 2006.173.15:09:11.57#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.15:09:11.57#ibcon#[25=AT02-06\r\n] 2006.173.15:09:11.57#ibcon#*before write, iclass 28, count 2 2006.173.15:09:11.57#ibcon#enter sib2, iclass 28, count 2 2006.173.15:09:11.57#ibcon#flushed, iclass 28, count 2 2006.173.15:09:11.57#ibcon#about to write, iclass 28, count 2 2006.173.15:09:11.57#ibcon#wrote, iclass 28, count 2 2006.173.15:09:11.57#ibcon#about to read 3, iclass 28, count 2 2006.173.15:09:11.60#ibcon#read 3, iclass 28, count 2 2006.173.15:09:11.60#ibcon#about to read 4, iclass 28, count 2 2006.173.15:09:11.60#ibcon#read 4, iclass 28, count 2 2006.173.15:09:11.60#ibcon#about to read 5, iclass 28, count 2 2006.173.15:09:11.60#ibcon#read 5, iclass 28, count 2 2006.173.15:09:11.60#ibcon#about to read 6, iclass 28, count 2 2006.173.15:09:11.60#ibcon#read 6, iclass 28, count 2 2006.173.15:09:11.60#ibcon#end of sib2, iclass 28, count 2 2006.173.15:09:11.60#ibcon#*after write, iclass 28, count 2 2006.173.15:09:11.60#ibcon#*before return 0, iclass 28, count 2 2006.173.15:09:11.60#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.15:09:11.60#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.15:09:11.60#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.15:09:11.60#ibcon#ireg 7 cls_cnt 0 2006.173.15:09:11.60#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.15:09:11.72#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.15:09:11.72#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.15:09:11.72#ibcon#enter wrdev, iclass 28, count 0 2006.173.15:09:11.72#ibcon#first serial, iclass 28, count 0 2006.173.15:09:11.72#ibcon#enter sib2, iclass 28, count 0 2006.173.15:09:11.72#ibcon#flushed, iclass 28, count 0 2006.173.15:09:11.72#ibcon#about to write, iclass 28, count 0 2006.173.15:09:11.72#ibcon#wrote, iclass 28, count 0 2006.173.15:09:11.72#ibcon#about to read 3, iclass 28, count 0 2006.173.15:09:11.74#ibcon#read 3, iclass 28, count 0 2006.173.15:09:11.74#ibcon#about to read 4, iclass 28, count 0 2006.173.15:09:11.74#ibcon#read 4, iclass 28, count 0 2006.173.15:09:11.74#ibcon#about to read 5, iclass 28, count 0 2006.173.15:09:11.74#ibcon#read 5, iclass 28, count 0 2006.173.15:09:11.74#ibcon#about to read 6, iclass 28, count 0 2006.173.15:09:11.74#ibcon#read 6, iclass 28, count 0 2006.173.15:09:11.74#ibcon#end of sib2, iclass 28, count 0 2006.173.15:09:11.74#ibcon#*mode == 0, iclass 28, count 0 2006.173.15:09:11.74#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.15:09:11.74#ibcon#[25=USB\r\n] 2006.173.15:09:11.74#ibcon#*before write, iclass 28, count 0 2006.173.15:09:11.74#ibcon#enter sib2, iclass 28, count 0 2006.173.15:09:11.74#ibcon#flushed, iclass 28, count 0 2006.173.15:09:11.74#ibcon#about to write, iclass 28, count 0 2006.173.15:09:11.74#ibcon#wrote, iclass 28, count 0 2006.173.15:09:11.74#ibcon#about to read 3, iclass 28, count 0 2006.173.15:09:11.77#ibcon#read 3, iclass 28, count 0 2006.173.15:09:11.77#ibcon#about to read 4, iclass 28, count 0 2006.173.15:09:11.77#ibcon#read 4, iclass 28, count 0 2006.173.15:09:11.77#ibcon#about to read 5, iclass 28, count 0 2006.173.15:09:11.77#ibcon#read 5, iclass 28, count 0 2006.173.15:09:11.77#ibcon#about to read 6, iclass 28, count 0 2006.173.15:09:11.77#ibcon#read 6, iclass 28, count 0 2006.173.15:09:11.77#ibcon#end of sib2, iclass 28, count 0 2006.173.15:09:11.77#ibcon#*after write, iclass 28, count 0 2006.173.15:09:11.77#ibcon#*before return 0, iclass 28, count 0 2006.173.15:09:11.77#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.15:09:11.77#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.15:09:11.77#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.15:09:11.77#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.15:09:11.77$vck44/valo=3,564.99 2006.173.15:09:11.77#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.15:09:11.77#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.15:09:11.77#ibcon#ireg 17 cls_cnt 0 2006.173.15:09:11.77#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.15:09:11.77#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.15:09:11.77#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.15:09:11.77#ibcon#enter wrdev, iclass 30, count 0 2006.173.15:09:11.77#ibcon#first serial, iclass 30, count 0 2006.173.15:09:11.77#ibcon#enter sib2, iclass 30, count 0 2006.173.15:09:11.77#ibcon#flushed, iclass 30, count 0 2006.173.15:09:11.77#ibcon#about to write, iclass 30, count 0 2006.173.15:09:11.77#ibcon#wrote, iclass 30, count 0 2006.173.15:09:11.77#ibcon#about to read 3, iclass 30, count 0 2006.173.15:09:11.79#ibcon#read 3, iclass 30, count 0 2006.173.15:09:11.79#ibcon#about to read 4, iclass 30, count 0 2006.173.15:09:11.79#ibcon#read 4, iclass 30, count 0 2006.173.15:09:11.79#ibcon#about to read 5, iclass 30, count 0 2006.173.15:09:11.79#ibcon#read 5, iclass 30, count 0 2006.173.15:09:11.79#ibcon#about to read 6, iclass 30, count 0 2006.173.15:09:11.79#ibcon#read 6, iclass 30, count 0 2006.173.15:09:11.79#ibcon#end of sib2, iclass 30, count 0 2006.173.15:09:11.79#ibcon#*mode == 0, iclass 30, count 0 2006.173.15:09:11.79#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.15:09:11.79#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.15:09:11.79#ibcon#*before write, iclass 30, count 0 2006.173.15:09:11.79#ibcon#enter sib2, iclass 30, count 0 2006.173.15:09:11.79#ibcon#flushed, iclass 30, count 0 2006.173.15:09:11.79#ibcon#about to write, iclass 30, count 0 2006.173.15:09:11.79#ibcon#wrote, iclass 30, count 0 2006.173.15:09:11.79#ibcon#about to read 3, iclass 30, count 0 2006.173.15:09:11.83#ibcon#read 3, iclass 30, count 0 2006.173.15:09:11.83#ibcon#about to read 4, iclass 30, count 0 2006.173.15:09:11.83#ibcon#read 4, iclass 30, count 0 2006.173.15:09:11.83#ibcon#about to read 5, iclass 30, count 0 2006.173.15:09:11.83#ibcon#read 5, iclass 30, count 0 2006.173.15:09:11.83#ibcon#about to read 6, iclass 30, count 0 2006.173.15:09:11.83#ibcon#read 6, iclass 30, count 0 2006.173.15:09:11.83#ibcon#end of sib2, iclass 30, count 0 2006.173.15:09:11.83#ibcon#*after write, iclass 30, count 0 2006.173.15:09:11.83#ibcon#*before return 0, iclass 30, count 0 2006.173.15:09:11.83#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.15:09:11.83#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.15:09:11.83#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.15:09:11.83#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.15:09:11.83$vck44/va=3,5 2006.173.15:09:11.83#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.173.15:09:11.83#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.173.15:09:11.83#ibcon#ireg 11 cls_cnt 2 2006.173.15:09:11.83#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.15:09:11.89#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.15:09:11.89#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.15:09:11.89#ibcon#enter wrdev, iclass 32, count 2 2006.173.15:09:11.89#ibcon#first serial, iclass 32, count 2 2006.173.15:09:11.89#ibcon#enter sib2, iclass 32, count 2 2006.173.15:09:11.89#ibcon#flushed, iclass 32, count 2 2006.173.15:09:11.89#ibcon#about to write, iclass 32, count 2 2006.173.15:09:11.89#ibcon#wrote, iclass 32, count 2 2006.173.15:09:11.89#ibcon#about to read 3, iclass 32, count 2 2006.173.15:09:11.91#ibcon#read 3, iclass 32, count 2 2006.173.15:09:11.91#ibcon#about to read 4, iclass 32, count 2 2006.173.15:09:11.91#ibcon#read 4, iclass 32, count 2 2006.173.15:09:11.91#ibcon#about to read 5, iclass 32, count 2 2006.173.15:09:11.91#ibcon#read 5, iclass 32, count 2 2006.173.15:09:11.91#ibcon#about to read 6, iclass 32, count 2 2006.173.15:09:11.91#ibcon#read 6, iclass 32, count 2 2006.173.15:09:11.91#ibcon#end of sib2, iclass 32, count 2 2006.173.15:09:11.91#ibcon#*mode == 0, iclass 32, count 2 2006.173.15:09:11.91#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.173.15:09:11.91#ibcon#[25=AT03-05\r\n] 2006.173.15:09:11.91#ibcon#*before write, iclass 32, count 2 2006.173.15:09:11.91#ibcon#enter sib2, iclass 32, count 2 2006.173.15:09:11.91#ibcon#flushed, iclass 32, count 2 2006.173.15:09:11.91#ibcon#about to write, iclass 32, count 2 2006.173.15:09:11.91#ibcon#wrote, iclass 32, count 2 2006.173.15:09:11.91#ibcon#about to read 3, iclass 32, count 2 2006.173.15:09:11.94#ibcon#read 3, iclass 32, count 2 2006.173.15:09:11.94#ibcon#about to read 4, iclass 32, count 2 2006.173.15:09:11.94#ibcon#read 4, iclass 32, count 2 2006.173.15:09:11.94#ibcon#about to read 5, iclass 32, count 2 2006.173.15:09:11.94#ibcon#read 5, iclass 32, count 2 2006.173.15:09:11.94#ibcon#about to read 6, iclass 32, count 2 2006.173.15:09:11.94#ibcon#read 6, iclass 32, count 2 2006.173.15:09:11.94#ibcon#end of sib2, iclass 32, count 2 2006.173.15:09:11.94#ibcon#*after write, iclass 32, count 2 2006.173.15:09:11.94#ibcon#*before return 0, iclass 32, count 2 2006.173.15:09:11.94#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.15:09:11.94#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.173.15:09:11.94#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.173.15:09:11.94#ibcon#ireg 7 cls_cnt 0 2006.173.15:09:11.94#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.15:09:12.06#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.15:09:12.06#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.15:09:12.06#ibcon#enter wrdev, iclass 32, count 0 2006.173.15:09:12.06#ibcon#first serial, iclass 32, count 0 2006.173.15:09:12.06#ibcon#enter sib2, iclass 32, count 0 2006.173.15:09:12.06#ibcon#flushed, iclass 32, count 0 2006.173.15:09:12.06#ibcon#about to write, iclass 32, count 0 2006.173.15:09:12.06#ibcon#wrote, iclass 32, count 0 2006.173.15:09:12.06#ibcon#about to read 3, iclass 32, count 0 2006.173.15:09:12.08#ibcon#read 3, iclass 32, count 0 2006.173.15:09:12.08#ibcon#about to read 4, iclass 32, count 0 2006.173.15:09:12.08#ibcon#read 4, iclass 32, count 0 2006.173.15:09:12.08#ibcon#about to read 5, iclass 32, count 0 2006.173.15:09:12.08#ibcon#read 5, iclass 32, count 0 2006.173.15:09:12.08#ibcon#about to read 6, iclass 32, count 0 2006.173.15:09:12.08#ibcon#read 6, iclass 32, count 0 2006.173.15:09:12.08#ibcon#end of sib2, iclass 32, count 0 2006.173.15:09:12.08#ibcon#*mode == 0, iclass 32, count 0 2006.173.15:09:12.08#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.15:09:12.08#ibcon#[25=USB\r\n] 2006.173.15:09:12.08#ibcon#*before write, iclass 32, count 0 2006.173.15:09:12.08#ibcon#enter sib2, iclass 32, count 0 2006.173.15:09:12.08#ibcon#flushed, iclass 32, count 0 2006.173.15:09:12.08#ibcon#about to write, iclass 32, count 0 2006.173.15:09:12.08#ibcon#wrote, iclass 32, count 0 2006.173.15:09:12.08#ibcon#about to read 3, iclass 32, count 0 2006.173.15:09:12.11#ibcon#read 3, iclass 32, count 0 2006.173.15:09:12.11#ibcon#about to read 4, iclass 32, count 0 2006.173.15:09:12.11#ibcon#read 4, iclass 32, count 0 2006.173.15:09:12.11#ibcon#about to read 5, iclass 32, count 0 2006.173.15:09:12.11#ibcon#read 5, iclass 32, count 0 2006.173.15:09:12.11#ibcon#about to read 6, iclass 32, count 0 2006.173.15:09:12.11#ibcon#read 6, iclass 32, count 0 2006.173.15:09:12.11#ibcon#end of sib2, iclass 32, count 0 2006.173.15:09:12.11#ibcon#*after write, iclass 32, count 0 2006.173.15:09:12.11#ibcon#*before return 0, iclass 32, count 0 2006.173.15:09:12.11#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.15:09:12.11#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.173.15:09:12.11#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.15:09:12.11#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.15:09:12.11$vck44/valo=4,624.99 2006.173.15:09:12.11#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.15:09:12.11#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.15:09:12.11#ibcon#ireg 17 cls_cnt 0 2006.173.15:09:12.11#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.15:09:12.11#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.15:09:12.11#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.15:09:12.11#ibcon#enter wrdev, iclass 34, count 0 2006.173.15:09:12.11#ibcon#first serial, iclass 34, count 0 2006.173.15:09:12.11#ibcon#enter sib2, iclass 34, count 0 2006.173.15:09:12.11#ibcon#flushed, iclass 34, count 0 2006.173.15:09:12.11#ibcon#about to write, iclass 34, count 0 2006.173.15:09:12.11#ibcon#wrote, iclass 34, count 0 2006.173.15:09:12.11#ibcon#about to read 3, iclass 34, count 0 2006.173.15:09:12.13#ibcon#read 3, iclass 34, count 0 2006.173.15:09:12.13#ibcon#about to read 4, iclass 34, count 0 2006.173.15:09:12.13#ibcon#read 4, iclass 34, count 0 2006.173.15:09:12.13#ibcon#about to read 5, iclass 34, count 0 2006.173.15:09:12.13#ibcon#read 5, iclass 34, count 0 2006.173.15:09:12.13#ibcon#about to read 6, iclass 34, count 0 2006.173.15:09:12.13#ibcon#read 6, iclass 34, count 0 2006.173.15:09:12.13#ibcon#end of sib2, iclass 34, count 0 2006.173.15:09:12.13#ibcon#*mode == 0, iclass 34, count 0 2006.173.15:09:12.13#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.15:09:12.13#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.15:09:12.13#ibcon#*before write, iclass 34, count 0 2006.173.15:09:12.13#ibcon#enter sib2, iclass 34, count 0 2006.173.15:09:12.13#ibcon#flushed, iclass 34, count 0 2006.173.15:09:12.13#ibcon#about to write, iclass 34, count 0 2006.173.15:09:12.13#ibcon#wrote, iclass 34, count 0 2006.173.15:09:12.13#ibcon#about to read 3, iclass 34, count 0 2006.173.15:09:12.17#ibcon#read 3, iclass 34, count 0 2006.173.15:09:12.17#ibcon#about to read 4, iclass 34, count 0 2006.173.15:09:12.17#ibcon#read 4, iclass 34, count 0 2006.173.15:09:12.17#ibcon#about to read 5, iclass 34, count 0 2006.173.15:09:12.17#ibcon#read 5, iclass 34, count 0 2006.173.15:09:12.17#ibcon#about to read 6, iclass 34, count 0 2006.173.15:09:12.17#ibcon#read 6, iclass 34, count 0 2006.173.15:09:12.17#ibcon#end of sib2, iclass 34, count 0 2006.173.15:09:12.17#ibcon#*after write, iclass 34, count 0 2006.173.15:09:12.17#ibcon#*before return 0, iclass 34, count 0 2006.173.15:09:12.17#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.15:09:12.17#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.15:09:12.17#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.15:09:12.17#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.15:09:12.17$vck44/va=4,6 2006.173.15:09:12.17#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.15:09:12.17#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.15:09:12.17#ibcon#ireg 11 cls_cnt 2 2006.173.15:09:12.17#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.15:09:12.23#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.15:09:12.23#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.15:09:12.23#ibcon#enter wrdev, iclass 36, count 2 2006.173.15:09:12.23#ibcon#first serial, iclass 36, count 2 2006.173.15:09:12.23#ibcon#enter sib2, iclass 36, count 2 2006.173.15:09:12.23#ibcon#flushed, iclass 36, count 2 2006.173.15:09:12.23#ibcon#about to write, iclass 36, count 2 2006.173.15:09:12.23#ibcon#wrote, iclass 36, count 2 2006.173.15:09:12.23#ibcon#about to read 3, iclass 36, count 2 2006.173.15:09:12.25#ibcon#read 3, iclass 36, count 2 2006.173.15:09:12.25#ibcon#about to read 4, iclass 36, count 2 2006.173.15:09:12.25#ibcon#read 4, iclass 36, count 2 2006.173.15:09:12.25#ibcon#about to read 5, iclass 36, count 2 2006.173.15:09:12.25#ibcon#read 5, iclass 36, count 2 2006.173.15:09:12.25#ibcon#about to read 6, iclass 36, count 2 2006.173.15:09:12.25#ibcon#read 6, iclass 36, count 2 2006.173.15:09:12.25#ibcon#end of sib2, iclass 36, count 2 2006.173.15:09:12.25#ibcon#*mode == 0, iclass 36, count 2 2006.173.15:09:12.25#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.15:09:12.25#ibcon#[25=AT04-06\r\n] 2006.173.15:09:12.25#ibcon#*before write, iclass 36, count 2 2006.173.15:09:12.25#ibcon#enter sib2, iclass 36, count 2 2006.173.15:09:12.25#ibcon#flushed, iclass 36, count 2 2006.173.15:09:12.25#ibcon#about to write, iclass 36, count 2 2006.173.15:09:12.25#ibcon#wrote, iclass 36, count 2 2006.173.15:09:12.25#ibcon#about to read 3, iclass 36, count 2 2006.173.15:09:12.28#ibcon#read 3, iclass 36, count 2 2006.173.15:09:12.28#ibcon#about to read 4, iclass 36, count 2 2006.173.15:09:12.28#ibcon#read 4, iclass 36, count 2 2006.173.15:09:12.28#ibcon#about to read 5, iclass 36, count 2 2006.173.15:09:12.28#ibcon#read 5, iclass 36, count 2 2006.173.15:09:12.28#ibcon#about to read 6, iclass 36, count 2 2006.173.15:09:12.28#ibcon#read 6, iclass 36, count 2 2006.173.15:09:12.28#ibcon#end of sib2, iclass 36, count 2 2006.173.15:09:12.28#ibcon#*after write, iclass 36, count 2 2006.173.15:09:12.28#ibcon#*before return 0, iclass 36, count 2 2006.173.15:09:12.28#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.15:09:12.28#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.15:09:12.28#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.15:09:12.28#ibcon#ireg 7 cls_cnt 0 2006.173.15:09:12.28#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.15:09:12.40#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.15:09:12.40#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.15:09:12.40#ibcon#enter wrdev, iclass 36, count 0 2006.173.15:09:12.40#ibcon#first serial, iclass 36, count 0 2006.173.15:09:12.40#ibcon#enter sib2, iclass 36, count 0 2006.173.15:09:12.40#ibcon#flushed, iclass 36, count 0 2006.173.15:09:12.40#ibcon#about to write, iclass 36, count 0 2006.173.15:09:12.40#ibcon#wrote, iclass 36, count 0 2006.173.15:09:12.40#ibcon#about to read 3, iclass 36, count 0 2006.173.15:09:12.42#ibcon#read 3, iclass 36, count 0 2006.173.15:09:12.42#ibcon#about to read 4, iclass 36, count 0 2006.173.15:09:12.42#ibcon#read 4, iclass 36, count 0 2006.173.15:09:12.42#ibcon#about to read 5, iclass 36, count 0 2006.173.15:09:12.42#ibcon#read 5, iclass 36, count 0 2006.173.15:09:12.42#ibcon#about to read 6, iclass 36, count 0 2006.173.15:09:12.42#ibcon#read 6, iclass 36, count 0 2006.173.15:09:12.42#ibcon#end of sib2, iclass 36, count 0 2006.173.15:09:12.42#ibcon#*mode == 0, iclass 36, count 0 2006.173.15:09:12.42#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.15:09:12.42#ibcon#[25=USB\r\n] 2006.173.15:09:12.42#ibcon#*before write, iclass 36, count 0 2006.173.15:09:12.42#ibcon#enter sib2, iclass 36, count 0 2006.173.15:09:12.42#ibcon#flushed, iclass 36, count 0 2006.173.15:09:12.42#ibcon#about to write, iclass 36, count 0 2006.173.15:09:12.42#ibcon#wrote, iclass 36, count 0 2006.173.15:09:12.42#ibcon#about to read 3, iclass 36, count 0 2006.173.15:09:12.45#ibcon#read 3, iclass 36, count 0 2006.173.15:09:12.45#ibcon#about to read 4, iclass 36, count 0 2006.173.15:09:12.45#ibcon#read 4, iclass 36, count 0 2006.173.15:09:12.45#ibcon#about to read 5, iclass 36, count 0 2006.173.15:09:12.45#ibcon#read 5, iclass 36, count 0 2006.173.15:09:12.45#ibcon#about to read 6, iclass 36, count 0 2006.173.15:09:12.45#ibcon#read 6, iclass 36, count 0 2006.173.15:09:12.45#ibcon#end of sib2, iclass 36, count 0 2006.173.15:09:12.45#ibcon#*after write, iclass 36, count 0 2006.173.15:09:12.45#ibcon#*before return 0, iclass 36, count 0 2006.173.15:09:12.45#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.15:09:12.45#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.15:09:12.45#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.15:09:12.45#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.15:09:12.45$vck44/valo=5,734.99 2006.173.15:09:12.45#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.15:09:12.45#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.15:09:12.45#ibcon#ireg 17 cls_cnt 0 2006.173.15:09:12.45#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.15:09:12.45#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.15:09:12.45#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.15:09:12.45#ibcon#enter wrdev, iclass 38, count 0 2006.173.15:09:12.45#ibcon#first serial, iclass 38, count 0 2006.173.15:09:12.45#ibcon#enter sib2, iclass 38, count 0 2006.173.15:09:12.45#ibcon#flushed, iclass 38, count 0 2006.173.15:09:12.45#ibcon#about to write, iclass 38, count 0 2006.173.15:09:12.45#ibcon#wrote, iclass 38, count 0 2006.173.15:09:12.45#ibcon#about to read 3, iclass 38, count 0 2006.173.15:09:12.47#ibcon#read 3, iclass 38, count 0 2006.173.15:09:12.47#ibcon#about to read 4, iclass 38, count 0 2006.173.15:09:12.47#ibcon#read 4, iclass 38, count 0 2006.173.15:09:12.47#ibcon#about to read 5, iclass 38, count 0 2006.173.15:09:12.47#ibcon#read 5, iclass 38, count 0 2006.173.15:09:12.47#ibcon#about to read 6, iclass 38, count 0 2006.173.15:09:12.47#ibcon#read 6, iclass 38, count 0 2006.173.15:09:12.47#ibcon#end of sib2, iclass 38, count 0 2006.173.15:09:12.47#ibcon#*mode == 0, iclass 38, count 0 2006.173.15:09:12.47#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.15:09:12.47#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.15:09:12.47#ibcon#*before write, iclass 38, count 0 2006.173.15:09:12.47#ibcon#enter sib2, iclass 38, count 0 2006.173.15:09:12.47#ibcon#flushed, iclass 38, count 0 2006.173.15:09:12.47#ibcon#about to write, iclass 38, count 0 2006.173.15:09:12.47#ibcon#wrote, iclass 38, count 0 2006.173.15:09:12.47#ibcon#about to read 3, iclass 38, count 0 2006.173.15:09:12.51#ibcon#read 3, iclass 38, count 0 2006.173.15:09:12.51#ibcon#about to read 4, iclass 38, count 0 2006.173.15:09:12.51#ibcon#read 4, iclass 38, count 0 2006.173.15:09:12.51#ibcon#about to read 5, iclass 38, count 0 2006.173.15:09:12.51#ibcon#read 5, iclass 38, count 0 2006.173.15:09:12.51#ibcon#about to read 6, iclass 38, count 0 2006.173.15:09:12.51#ibcon#read 6, iclass 38, count 0 2006.173.15:09:12.51#ibcon#end of sib2, iclass 38, count 0 2006.173.15:09:12.51#ibcon#*after write, iclass 38, count 0 2006.173.15:09:12.51#ibcon#*before return 0, iclass 38, count 0 2006.173.15:09:12.51#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.15:09:12.51#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.15:09:12.51#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.15:09:12.51#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.15:09:12.51$vck44/va=5,4 2006.173.15:09:12.51#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.15:09:12.51#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.15:09:12.51#ibcon#ireg 11 cls_cnt 2 2006.173.15:09:12.51#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.15:09:12.57#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.15:09:12.57#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.15:09:12.57#ibcon#enter wrdev, iclass 40, count 2 2006.173.15:09:12.57#ibcon#first serial, iclass 40, count 2 2006.173.15:09:12.57#ibcon#enter sib2, iclass 40, count 2 2006.173.15:09:12.57#ibcon#flushed, iclass 40, count 2 2006.173.15:09:12.57#ibcon#about to write, iclass 40, count 2 2006.173.15:09:12.57#ibcon#wrote, iclass 40, count 2 2006.173.15:09:12.57#ibcon#about to read 3, iclass 40, count 2 2006.173.15:09:12.59#ibcon#read 3, iclass 40, count 2 2006.173.15:09:12.59#ibcon#about to read 4, iclass 40, count 2 2006.173.15:09:12.59#ibcon#read 4, iclass 40, count 2 2006.173.15:09:12.59#ibcon#about to read 5, iclass 40, count 2 2006.173.15:09:12.59#ibcon#read 5, iclass 40, count 2 2006.173.15:09:12.59#ibcon#about to read 6, iclass 40, count 2 2006.173.15:09:12.59#ibcon#read 6, iclass 40, count 2 2006.173.15:09:12.59#ibcon#end of sib2, iclass 40, count 2 2006.173.15:09:12.59#ibcon#*mode == 0, iclass 40, count 2 2006.173.15:09:12.59#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.15:09:12.59#ibcon#[25=AT05-04\r\n] 2006.173.15:09:12.59#ibcon#*before write, iclass 40, count 2 2006.173.15:09:12.59#ibcon#enter sib2, iclass 40, count 2 2006.173.15:09:12.59#ibcon#flushed, iclass 40, count 2 2006.173.15:09:12.59#ibcon#about to write, iclass 40, count 2 2006.173.15:09:12.59#ibcon#wrote, iclass 40, count 2 2006.173.15:09:12.59#ibcon#about to read 3, iclass 40, count 2 2006.173.15:09:12.62#ibcon#read 3, iclass 40, count 2 2006.173.15:09:12.62#ibcon#about to read 4, iclass 40, count 2 2006.173.15:09:12.62#ibcon#read 4, iclass 40, count 2 2006.173.15:09:12.62#ibcon#about to read 5, iclass 40, count 2 2006.173.15:09:12.62#ibcon#read 5, iclass 40, count 2 2006.173.15:09:12.62#ibcon#about to read 6, iclass 40, count 2 2006.173.15:09:12.62#ibcon#read 6, iclass 40, count 2 2006.173.15:09:12.62#ibcon#end of sib2, iclass 40, count 2 2006.173.15:09:12.62#ibcon#*after write, iclass 40, count 2 2006.173.15:09:12.62#ibcon#*before return 0, iclass 40, count 2 2006.173.15:09:12.62#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.15:09:12.62#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.15:09:12.62#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.15:09:12.62#ibcon#ireg 7 cls_cnt 0 2006.173.15:09:12.62#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.15:09:12.74#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.15:09:12.74#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.15:09:12.74#ibcon#enter wrdev, iclass 40, count 0 2006.173.15:09:12.74#ibcon#first serial, iclass 40, count 0 2006.173.15:09:12.74#ibcon#enter sib2, iclass 40, count 0 2006.173.15:09:12.74#ibcon#flushed, iclass 40, count 0 2006.173.15:09:12.74#ibcon#about to write, iclass 40, count 0 2006.173.15:09:12.74#ibcon#wrote, iclass 40, count 0 2006.173.15:09:12.74#ibcon#about to read 3, iclass 40, count 0 2006.173.15:09:12.76#ibcon#read 3, iclass 40, count 0 2006.173.15:09:12.76#ibcon#about to read 4, iclass 40, count 0 2006.173.15:09:12.76#ibcon#read 4, iclass 40, count 0 2006.173.15:09:12.76#ibcon#about to read 5, iclass 40, count 0 2006.173.15:09:12.76#ibcon#read 5, iclass 40, count 0 2006.173.15:09:12.76#ibcon#about to read 6, iclass 40, count 0 2006.173.15:09:12.76#ibcon#read 6, iclass 40, count 0 2006.173.15:09:12.76#ibcon#end of sib2, iclass 40, count 0 2006.173.15:09:12.76#ibcon#*mode == 0, iclass 40, count 0 2006.173.15:09:12.76#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.15:09:12.76#ibcon#[25=USB\r\n] 2006.173.15:09:12.76#ibcon#*before write, iclass 40, count 0 2006.173.15:09:12.76#ibcon#enter sib2, iclass 40, count 0 2006.173.15:09:12.76#ibcon#flushed, iclass 40, count 0 2006.173.15:09:12.76#ibcon#about to write, iclass 40, count 0 2006.173.15:09:12.76#ibcon#wrote, iclass 40, count 0 2006.173.15:09:12.76#ibcon#about to read 3, iclass 40, count 0 2006.173.15:09:12.79#ibcon#read 3, iclass 40, count 0 2006.173.15:09:12.79#ibcon#about to read 4, iclass 40, count 0 2006.173.15:09:12.79#ibcon#read 4, iclass 40, count 0 2006.173.15:09:12.79#ibcon#about to read 5, iclass 40, count 0 2006.173.15:09:12.79#ibcon#read 5, iclass 40, count 0 2006.173.15:09:12.79#ibcon#about to read 6, iclass 40, count 0 2006.173.15:09:12.79#ibcon#read 6, iclass 40, count 0 2006.173.15:09:12.79#ibcon#end of sib2, iclass 40, count 0 2006.173.15:09:12.79#ibcon#*after write, iclass 40, count 0 2006.173.15:09:12.79#ibcon#*before return 0, iclass 40, count 0 2006.173.15:09:12.79#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.15:09:12.79#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.15:09:12.79#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.15:09:12.79#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.15:09:12.79$vck44/valo=6,814.99 2006.173.15:09:12.79#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.15:09:12.79#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.15:09:12.79#ibcon#ireg 17 cls_cnt 0 2006.173.15:09:12.79#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.15:09:12.79#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.15:09:12.79#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.15:09:12.79#ibcon#enter wrdev, iclass 5, count 0 2006.173.15:09:12.79#ibcon#first serial, iclass 5, count 0 2006.173.15:09:12.79#ibcon#enter sib2, iclass 5, count 0 2006.173.15:09:12.79#ibcon#flushed, iclass 5, count 0 2006.173.15:09:12.79#ibcon#about to write, iclass 5, count 0 2006.173.15:09:12.79#ibcon#wrote, iclass 5, count 0 2006.173.15:09:12.79#ibcon#about to read 3, iclass 5, count 0 2006.173.15:09:12.81#ibcon#read 3, iclass 5, count 0 2006.173.15:09:12.81#ibcon#about to read 4, iclass 5, count 0 2006.173.15:09:12.81#ibcon#read 4, iclass 5, count 0 2006.173.15:09:12.81#ibcon#about to read 5, iclass 5, count 0 2006.173.15:09:12.81#ibcon#read 5, iclass 5, count 0 2006.173.15:09:12.81#ibcon#about to read 6, iclass 5, count 0 2006.173.15:09:12.81#ibcon#read 6, iclass 5, count 0 2006.173.15:09:12.81#ibcon#end of sib2, iclass 5, count 0 2006.173.15:09:12.81#ibcon#*mode == 0, iclass 5, count 0 2006.173.15:09:12.81#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.15:09:12.81#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.15:09:12.81#ibcon#*before write, iclass 5, count 0 2006.173.15:09:12.81#ibcon#enter sib2, iclass 5, count 0 2006.173.15:09:12.81#ibcon#flushed, iclass 5, count 0 2006.173.15:09:12.81#ibcon#about to write, iclass 5, count 0 2006.173.15:09:12.81#ibcon#wrote, iclass 5, count 0 2006.173.15:09:12.81#ibcon#about to read 3, iclass 5, count 0 2006.173.15:09:12.82#abcon#<5=/06 2.7 4.2 20.971001003.1\r\n> 2006.173.15:09:12.84#abcon#{5=INTERFACE CLEAR} 2006.173.15:09:12.85#ibcon#read 3, iclass 5, count 0 2006.173.15:09:12.85#ibcon#about to read 4, iclass 5, count 0 2006.173.15:09:12.85#ibcon#read 4, iclass 5, count 0 2006.173.15:09:12.85#ibcon#about to read 5, iclass 5, count 0 2006.173.15:09:12.85#ibcon#read 5, iclass 5, count 0 2006.173.15:09:12.85#ibcon#about to read 6, iclass 5, count 0 2006.173.15:09:12.85#ibcon#read 6, iclass 5, count 0 2006.173.15:09:12.85#ibcon#end of sib2, iclass 5, count 0 2006.173.15:09:12.85#ibcon#*after write, iclass 5, count 0 2006.173.15:09:12.85#ibcon#*before return 0, iclass 5, count 0 2006.173.15:09:12.85#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.15:09:12.85#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.15:09:12.85#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.15:09:12.85#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.15:09:12.85$vck44/va=6,3 2006.173.15:09:12.85#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.15:09:12.85#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.15:09:12.85#ibcon#ireg 11 cls_cnt 2 2006.173.15:09:12.85#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.15:09:12.90#abcon#[5=S1D000X0/0*\r\n] 2006.173.15:09:12.91#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.15:09:12.91#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.15:09:12.91#ibcon#enter wrdev, iclass 11, count 2 2006.173.15:09:12.91#ibcon#first serial, iclass 11, count 2 2006.173.15:09:12.91#ibcon#enter sib2, iclass 11, count 2 2006.173.15:09:12.91#ibcon#flushed, iclass 11, count 2 2006.173.15:09:12.91#ibcon#about to write, iclass 11, count 2 2006.173.15:09:12.91#ibcon#wrote, iclass 11, count 2 2006.173.15:09:12.91#ibcon#about to read 3, iclass 11, count 2 2006.173.15:09:12.93#ibcon#read 3, iclass 11, count 2 2006.173.15:09:12.93#ibcon#about to read 4, iclass 11, count 2 2006.173.15:09:12.93#ibcon#read 4, iclass 11, count 2 2006.173.15:09:12.93#ibcon#about to read 5, iclass 11, count 2 2006.173.15:09:12.93#ibcon#read 5, iclass 11, count 2 2006.173.15:09:12.93#ibcon#about to read 6, iclass 11, count 2 2006.173.15:09:12.93#ibcon#read 6, iclass 11, count 2 2006.173.15:09:12.93#ibcon#end of sib2, iclass 11, count 2 2006.173.15:09:12.93#ibcon#*mode == 0, iclass 11, count 2 2006.173.15:09:12.93#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.15:09:12.93#ibcon#[25=AT06-03\r\n] 2006.173.15:09:12.93#ibcon#*before write, iclass 11, count 2 2006.173.15:09:12.93#ibcon#enter sib2, iclass 11, count 2 2006.173.15:09:12.93#ibcon#flushed, iclass 11, count 2 2006.173.15:09:12.93#ibcon#about to write, iclass 11, count 2 2006.173.15:09:12.93#ibcon#wrote, iclass 11, count 2 2006.173.15:09:12.93#ibcon#about to read 3, iclass 11, count 2 2006.173.15:09:12.96#ibcon#read 3, iclass 11, count 2 2006.173.15:09:12.96#ibcon#about to read 4, iclass 11, count 2 2006.173.15:09:12.96#ibcon#read 4, iclass 11, count 2 2006.173.15:09:12.96#ibcon#about to read 5, iclass 11, count 2 2006.173.15:09:12.96#ibcon#read 5, iclass 11, count 2 2006.173.15:09:12.96#ibcon#about to read 6, iclass 11, count 2 2006.173.15:09:12.96#ibcon#read 6, iclass 11, count 2 2006.173.15:09:12.96#ibcon#end of sib2, iclass 11, count 2 2006.173.15:09:12.96#ibcon#*after write, iclass 11, count 2 2006.173.15:09:12.96#ibcon#*before return 0, iclass 11, count 2 2006.173.15:09:12.96#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.15:09:12.96#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.15:09:12.96#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.15:09:12.96#ibcon#ireg 7 cls_cnt 0 2006.173.15:09:12.96#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.15:09:13.08#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.15:09:13.08#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.15:09:13.08#ibcon#enter wrdev, iclass 11, count 0 2006.173.15:09:13.08#ibcon#first serial, iclass 11, count 0 2006.173.15:09:13.08#ibcon#enter sib2, iclass 11, count 0 2006.173.15:09:13.08#ibcon#flushed, iclass 11, count 0 2006.173.15:09:13.08#ibcon#about to write, iclass 11, count 0 2006.173.15:09:13.08#ibcon#wrote, iclass 11, count 0 2006.173.15:09:13.08#ibcon#about to read 3, iclass 11, count 0 2006.173.15:09:13.10#ibcon#read 3, iclass 11, count 0 2006.173.15:09:13.10#ibcon#about to read 4, iclass 11, count 0 2006.173.15:09:13.10#ibcon#read 4, iclass 11, count 0 2006.173.15:09:13.10#ibcon#about to read 5, iclass 11, count 0 2006.173.15:09:13.10#ibcon#read 5, iclass 11, count 0 2006.173.15:09:13.10#ibcon#about to read 6, iclass 11, count 0 2006.173.15:09:13.10#ibcon#read 6, iclass 11, count 0 2006.173.15:09:13.10#ibcon#end of sib2, iclass 11, count 0 2006.173.15:09:13.10#ibcon#*mode == 0, iclass 11, count 0 2006.173.15:09:13.10#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.15:09:13.10#ibcon#[25=USB\r\n] 2006.173.15:09:13.10#ibcon#*before write, iclass 11, count 0 2006.173.15:09:13.10#ibcon#enter sib2, iclass 11, count 0 2006.173.15:09:13.10#ibcon#flushed, iclass 11, count 0 2006.173.15:09:13.10#ibcon#about to write, iclass 11, count 0 2006.173.15:09:13.10#ibcon#wrote, iclass 11, count 0 2006.173.15:09:13.10#ibcon#about to read 3, iclass 11, count 0 2006.173.15:09:13.13#ibcon#read 3, iclass 11, count 0 2006.173.15:09:13.13#ibcon#about to read 4, iclass 11, count 0 2006.173.15:09:13.13#ibcon#read 4, iclass 11, count 0 2006.173.15:09:13.13#ibcon#about to read 5, iclass 11, count 0 2006.173.15:09:13.13#ibcon#read 5, iclass 11, count 0 2006.173.15:09:13.13#ibcon#about to read 6, iclass 11, count 0 2006.173.15:09:13.13#ibcon#read 6, iclass 11, count 0 2006.173.15:09:13.13#ibcon#end of sib2, iclass 11, count 0 2006.173.15:09:13.13#ibcon#*after write, iclass 11, count 0 2006.173.15:09:13.13#ibcon#*before return 0, iclass 11, count 0 2006.173.15:09:13.13#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.15:09:13.13#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.15:09:13.13#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.15:09:13.13#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.15:09:13.13$vck44/valo=7,864.99 2006.173.15:09:13.13#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.15:09:13.13#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.15:09:13.13#ibcon#ireg 17 cls_cnt 0 2006.173.15:09:13.13#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.15:09:13.13#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.15:09:13.13#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.15:09:13.13#ibcon#enter wrdev, iclass 14, count 0 2006.173.15:09:13.13#ibcon#first serial, iclass 14, count 0 2006.173.15:09:13.13#ibcon#enter sib2, iclass 14, count 0 2006.173.15:09:13.13#ibcon#flushed, iclass 14, count 0 2006.173.15:09:13.13#ibcon#about to write, iclass 14, count 0 2006.173.15:09:13.13#ibcon#wrote, iclass 14, count 0 2006.173.15:09:13.13#ibcon#about to read 3, iclass 14, count 0 2006.173.15:09:13.15#ibcon#read 3, iclass 14, count 0 2006.173.15:09:13.15#ibcon#about to read 4, iclass 14, count 0 2006.173.15:09:13.15#ibcon#read 4, iclass 14, count 0 2006.173.15:09:13.15#ibcon#about to read 5, iclass 14, count 0 2006.173.15:09:13.15#ibcon#read 5, iclass 14, count 0 2006.173.15:09:13.15#ibcon#about to read 6, iclass 14, count 0 2006.173.15:09:13.15#ibcon#read 6, iclass 14, count 0 2006.173.15:09:13.15#ibcon#end of sib2, iclass 14, count 0 2006.173.15:09:13.15#ibcon#*mode == 0, iclass 14, count 0 2006.173.15:09:13.15#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.15:09:13.15#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.15:09:13.15#ibcon#*before write, iclass 14, count 0 2006.173.15:09:13.15#ibcon#enter sib2, iclass 14, count 0 2006.173.15:09:13.15#ibcon#flushed, iclass 14, count 0 2006.173.15:09:13.15#ibcon#about to write, iclass 14, count 0 2006.173.15:09:13.15#ibcon#wrote, iclass 14, count 0 2006.173.15:09:13.15#ibcon#about to read 3, iclass 14, count 0 2006.173.15:09:13.19#ibcon#read 3, iclass 14, count 0 2006.173.15:09:13.19#ibcon#about to read 4, iclass 14, count 0 2006.173.15:09:13.19#ibcon#read 4, iclass 14, count 0 2006.173.15:09:13.19#ibcon#about to read 5, iclass 14, count 0 2006.173.15:09:13.19#ibcon#read 5, iclass 14, count 0 2006.173.15:09:13.19#ibcon#about to read 6, iclass 14, count 0 2006.173.15:09:13.19#ibcon#read 6, iclass 14, count 0 2006.173.15:09:13.19#ibcon#end of sib2, iclass 14, count 0 2006.173.15:09:13.19#ibcon#*after write, iclass 14, count 0 2006.173.15:09:13.19#ibcon#*before return 0, iclass 14, count 0 2006.173.15:09:13.19#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.15:09:13.19#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.15:09:13.19#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.15:09:13.19#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.15:09:13.19$vck44/va=7,4 2006.173.15:09:13.19#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.15:09:13.19#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.15:09:13.19#ibcon#ireg 11 cls_cnt 2 2006.173.15:09:13.19#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.15:09:13.25#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.15:09:13.25#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.15:09:13.25#ibcon#enter wrdev, iclass 16, count 2 2006.173.15:09:13.25#ibcon#first serial, iclass 16, count 2 2006.173.15:09:13.25#ibcon#enter sib2, iclass 16, count 2 2006.173.15:09:13.25#ibcon#flushed, iclass 16, count 2 2006.173.15:09:13.25#ibcon#about to write, iclass 16, count 2 2006.173.15:09:13.25#ibcon#wrote, iclass 16, count 2 2006.173.15:09:13.25#ibcon#about to read 3, iclass 16, count 2 2006.173.15:09:13.27#ibcon#read 3, iclass 16, count 2 2006.173.15:09:13.27#ibcon#about to read 4, iclass 16, count 2 2006.173.15:09:13.27#ibcon#read 4, iclass 16, count 2 2006.173.15:09:13.27#ibcon#about to read 5, iclass 16, count 2 2006.173.15:09:13.27#ibcon#read 5, iclass 16, count 2 2006.173.15:09:13.27#ibcon#about to read 6, iclass 16, count 2 2006.173.15:09:13.27#ibcon#read 6, iclass 16, count 2 2006.173.15:09:13.27#ibcon#end of sib2, iclass 16, count 2 2006.173.15:09:13.27#ibcon#*mode == 0, iclass 16, count 2 2006.173.15:09:13.27#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.15:09:13.27#ibcon#[25=AT07-04\r\n] 2006.173.15:09:13.27#ibcon#*before write, iclass 16, count 2 2006.173.15:09:13.27#ibcon#enter sib2, iclass 16, count 2 2006.173.15:09:13.27#ibcon#flushed, iclass 16, count 2 2006.173.15:09:13.27#ibcon#about to write, iclass 16, count 2 2006.173.15:09:13.27#ibcon#wrote, iclass 16, count 2 2006.173.15:09:13.27#ibcon#about to read 3, iclass 16, count 2 2006.173.15:09:13.30#ibcon#read 3, iclass 16, count 2 2006.173.15:09:13.30#ibcon#about to read 4, iclass 16, count 2 2006.173.15:09:13.30#ibcon#read 4, iclass 16, count 2 2006.173.15:09:13.30#ibcon#about to read 5, iclass 16, count 2 2006.173.15:09:13.30#ibcon#read 5, iclass 16, count 2 2006.173.15:09:13.30#ibcon#about to read 6, iclass 16, count 2 2006.173.15:09:13.30#ibcon#read 6, iclass 16, count 2 2006.173.15:09:13.30#ibcon#end of sib2, iclass 16, count 2 2006.173.15:09:13.30#ibcon#*after write, iclass 16, count 2 2006.173.15:09:13.30#ibcon#*before return 0, iclass 16, count 2 2006.173.15:09:13.30#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.15:09:13.30#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.15:09:13.30#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.15:09:13.30#ibcon#ireg 7 cls_cnt 0 2006.173.15:09:13.30#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.15:09:13.42#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.15:09:13.42#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.15:09:13.42#ibcon#enter wrdev, iclass 16, count 0 2006.173.15:09:13.42#ibcon#first serial, iclass 16, count 0 2006.173.15:09:13.42#ibcon#enter sib2, iclass 16, count 0 2006.173.15:09:13.42#ibcon#flushed, iclass 16, count 0 2006.173.15:09:13.42#ibcon#about to write, iclass 16, count 0 2006.173.15:09:13.42#ibcon#wrote, iclass 16, count 0 2006.173.15:09:13.42#ibcon#about to read 3, iclass 16, count 0 2006.173.15:09:13.44#ibcon#read 3, iclass 16, count 0 2006.173.15:09:13.44#ibcon#about to read 4, iclass 16, count 0 2006.173.15:09:13.44#ibcon#read 4, iclass 16, count 0 2006.173.15:09:13.44#ibcon#about to read 5, iclass 16, count 0 2006.173.15:09:13.44#ibcon#read 5, iclass 16, count 0 2006.173.15:09:13.44#ibcon#about to read 6, iclass 16, count 0 2006.173.15:09:13.44#ibcon#read 6, iclass 16, count 0 2006.173.15:09:13.44#ibcon#end of sib2, iclass 16, count 0 2006.173.15:09:13.44#ibcon#*mode == 0, iclass 16, count 0 2006.173.15:09:13.44#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.15:09:13.44#ibcon#[25=USB\r\n] 2006.173.15:09:13.44#ibcon#*before write, iclass 16, count 0 2006.173.15:09:13.44#ibcon#enter sib2, iclass 16, count 0 2006.173.15:09:13.44#ibcon#flushed, iclass 16, count 0 2006.173.15:09:13.44#ibcon#about to write, iclass 16, count 0 2006.173.15:09:13.44#ibcon#wrote, iclass 16, count 0 2006.173.15:09:13.44#ibcon#about to read 3, iclass 16, count 0 2006.173.15:09:13.47#ibcon#read 3, iclass 16, count 0 2006.173.15:09:13.47#ibcon#about to read 4, iclass 16, count 0 2006.173.15:09:13.47#ibcon#read 4, iclass 16, count 0 2006.173.15:09:13.47#ibcon#about to read 5, iclass 16, count 0 2006.173.15:09:13.47#ibcon#read 5, iclass 16, count 0 2006.173.15:09:13.47#ibcon#about to read 6, iclass 16, count 0 2006.173.15:09:13.47#ibcon#read 6, iclass 16, count 0 2006.173.15:09:13.47#ibcon#end of sib2, iclass 16, count 0 2006.173.15:09:13.47#ibcon#*after write, iclass 16, count 0 2006.173.15:09:13.47#ibcon#*before return 0, iclass 16, count 0 2006.173.15:09:13.47#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.15:09:13.47#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.15:09:13.47#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.15:09:13.47#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.15:09:13.47$vck44/valo=8,884.99 2006.173.15:09:13.47#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.15:09:13.47#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.15:09:13.47#ibcon#ireg 17 cls_cnt 0 2006.173.15:09:13.47#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.15:09:13.47#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.15:09:13.47#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.15:09:13.47#ibcon#enter wrdev, iclass 18, count 0 2006.173.15:09:13.47#ibcon#first serial, iclass 18, count 0 2006.173.15:09:13.47#ibcon#enter sib2, iclass 18, count 0 2006.173.15:09:13.47#ibcon#flushed, iclass 18, count 0 2006.173.15:09:13.47#ibcon#about to write, iclass 18, count 0 2006.173.15:09:13.47#ibcon#wrote, iclass 18, count 0 2006.173.15:09:13.47#ibcon#about to read 3, iclass 18, count 0 2006.173.15:09:13.49#ibcon#read 3, iclass 18, count 0 2006.173.15:09:13.49#ibcon#about to read 4, iclass 18, count 0 2006.173.15:09:13.49#ibcon#read 4, iclass 18, count 0 2006.173.15:09:13.49#ibcon#about to read 5, iclass 18, count 0 2006.173.15:09:13.49#ibcon#read 5, iclass 18, count 0 2006.173.15:09:13.49#ibcon#about to read 6, iclass 18, count 0 2006.173.15:09:13.49#ibcon#read 6, iclass 18, count 0 2006.173.15:09:13.49#ibcon#end of sib2, iclass 18, count 0 2006.173.15:09:13.49#ibcon#*mode == 0, iclass 18, count 0 2006.173.15:09:13.49#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.15:09:13.49#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.15:09:13.49#ibcon#*before write, iclass 18, count 0 2006.173.15:09:13.49#ibcon#enter sib2, iclass 18, count 0 2006.173.15:09:13.49#ibcon#flushed, iclass 18, count 0 2006.173.15:09:13.49#ibcon#about to write, iclass 18, count 0 2006.173.15:09:13.49#ibcon#wrote, iclass 18, count 0 2006.173.15:09:13.49#ibcon#about to read 3, iclass 18, count 0 2006.173.15:09:13.53#ibcon#read 3, iclass 18, count 0 2006.173.15:09:13.53#ibcon#about to read 4, iclass 18, count 0 2006.173.15:09:13.53#ibcon#read 4, iclass 18, count 0 2006.173.15:09:13.53#ibcon#about to read 5, iclass 18, count 0 2006.173.15:09:13.53#ibcon#read 5, iclass 18, count 0 2006.173.15:09:13.53#ibcon#about to read 6, iclass 18, count 0 2006.173.15:09:13.53#ibcon#read 6, iclass 18, count 0 2006.173.15:09:13.53#ibcon#end of sib2, iclass 18, count 0 2006.173.15:09:13.53#ibcon#*after write, iclass 18, count 0 2006.173.15:09:13.53#ibcon#*before return 0, iclass 18, count 0 2006.173.15:09:13.53#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.15:09:13.53#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.15:09:13.53#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.15:09:13.53#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.15:09:13.53$vck44/va=8,4 2006.173.15:09:13.53#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.15:09:13.53#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.15:09:13.53#ibcon#ireg 11 cls_cnt 2 2006.173.15:09:13.53#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.15:09:13.59#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.15:09:13.59#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.15:09:13.59#ibcon#enter wrdev, iclass 20, count 2 2006.173.15:09:13.59#ibcon#first serial, iclass 20, count 2 2006.173.15:09:13.59#ibcon#enter sib2, iclass 20, count 2 2006.173.15:09:13.59#ibcon#flushed, iclass 20, count 2 2006.173.15:09:13.59#ibcon#about to write, iclass 20, count 2 2006.173.15:09:13.59#ibcon#wrote, iclass 20, count 2 2006.173.15:09:13.59#ibcon#about to read 3, iclass 20, count 2 2006.173.15:09:13.61#ibcon#read 3, iclass 20, count 2 2006.173.15:09:13.61#ibcon#about to read 4, iclass 20, count 2 2006.173.15:09:13.61#ibcon#read 4, iclass 20, count 2 2006.173.15:09:13.61#ibcon#about to read 5, iclass 20, count 2 2006.173.15:09:13.61#ibcon#read 5, iclass 20, count 2 2006.173.15:09:13.61#ibcon#about to read 6, iclass 20, count 2 2006.173.15:09:13.61#ibcon#read 6, iclass 20, count 2 2006.173.15:09:13.61#ibcon#end of sib2, iclass 20, count 2 2006.173.15:09:13.61#ibcon#*mode == 0, iclass 20, count 2 2006.173.15:09:13.61#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.15:09:13.61#ibcon#[25=AT08-04\r\n] 2006.173.15:09:13.61#ibcon#*before write, iclass 20, count 2 2006.173.15:09:13.61#ibcon#enter sib2, iclass 20, count 2 2006.173.15:09:13.61#ibcon#flushed, iclass 20, count 2 2006.173.15:09:13.61#ibcon#about to write, iclass 20, count 2 2006.173.15:09:13.61#ibcon#wrote, iclass 20, count 2 2006.173.15:09:13.61#ibcon#about to read 3, iclass 20, count 2 2006.173.15:09:13.64#ibcon#read 3, iclass 20, count 2 2006.173.15:09:13.64#ibcon#about to read 4, iclass 20, count 2 2006.173.15:09:13.64#ibcon#read 4, iclass 20, count 2 2006.173.15:09:13.64#ibcon#about to read 5, iclass 20, count 2 2006.173.15:09:13.64#ibcon#read 5, iclass 20, count 2 2006.173.15:09:13.64#ibcon#about to read 6, iclass 20, count 2 2006.173.15:09:13.64#ibcon#read 6, iclass 20, count 2 2006.173.15:09:13.64#ibcon#end of sib2, iclass 20, count 2 2006.173.15:09:13.64#ibcon#*after write, iclass 20, count 2 2006.173.15:09:13.64#ibcon#*before return 0, iclass 20, count 2 2006.173.15:09:13.64#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.15:09:13.64#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.15:09:13.64#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.15:09:13.64#ibcon#ireg 7 cls_cnt 0 2006.173.15:09:13.64#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.15:09:13.76#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.15:09:13.76#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.15:09:13.76#ibcon#enter wrdev, iclass 20, count 0 2006.173.15:09:13.76#ibcon#first serial, iclass 20, count 0 2006.173.15:09:13.76#ibcon#enter sib2, iclass 20, count 0 2006.173.15:09:13.76#ibcon#flushed, iclass 20, count 0 2006.173.15:09:13.76#ibcon#about to write, iclass 20, count 0 2006.173.15:09:13.76#ibcon#wrote, iclass 20, count 0 2006.173.15:09:13.76#ibcon#about to read 3, iclass 20, count 0 2006.173.15:09:13.78#ibcon#read 3, iclass 20, count 0 2006.173.15:09:13.78#ibcon#about to read 4, iclass 20, count 0 2006.173.15:09:13.78#ibcon#read 4, iclass 20, count 0 2006.173.15:09:13.78#ibcon#about to read 5, iclass 20, count 0 2006.173.15:09:13.78#ibcon#read 5, iclass 20, count 0 2006.173.15:09:13.78#ibcon#about to read 6, iclass 20, count 0 2006.173.15:09:13.78#ibcon#read 6, iclass 20, count 0 2006.173.15:09:13.78#ibcon#end of sib2, iclass 20, count 0 2006.173.15:09:13.78#ibcon#*mode == 0, iclass 20, count 0 2006.173.15:09:13.78#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.15:09:13.78#ibcon#[25=USB\r\n] 2006.173.15:09:13.78#ibcon#*before write, iclass 20, count 0 2006.173.15:09:13.78#ibcon#enter sib2, iclass 20, count 0 2006.173.15:09:13.78#ibcon#flushed, iclass 20, count 0 2006.173.15:09:13.78#ibcon#about to write, iclass 20, count 0 2006.173.15:09:13.78#ibcon#wrote, iclass 20, count 0 2006.173.15:09:13.78#ibcon#about to read 3, iclass 20, count 0 2006.173.15:09:13.81#ibcon#read 3, iclass 20, count 0 2006.173.15:09:13.81#ibcon#about to read 4, iclass 20, count 0 2006.173.15:09:13.81#ibcon#read 4, iclass 20, count 0 2006.173.15:09:13.81#ibcon#about to read 5, iclass 20, count 0 2006.173.15:09:13.81#ibcon#read 5, iclass 20, count 0 2006.173.15:09:13.81#ibcon#about to read 6, iclass 20, count 0 2006.173.15:09:13.81#ibcon#read 6, iclass 20, count 0 2006.173.15:09:13.81#ibcon#end of sib2, iclass 20, count 0 2006.173.15:09:13.81#ibcon#*after write, iclass 20, count 0 2006.173.15:09:13.81#ibcon#*before return 0, iclass 20, count 0 2006.173.15:09:13.81#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.15:09:13.81#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.15:09:13.81#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.15:09:13.81#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.15:09:13.81$vck44/vblo=1,629.99 2006.173.15:09:13.81#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.15:09:13.81#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.15:09:13.81#ibcon#ireg 17 cls_cnt 0 2006.173.15:09:13.81#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.15:09:13.81#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.15:09:13.81#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.15:09:13.81#ibcon#enter wrdev, iclass 22, count 0 2006.173.15:09:13.81#ibcon#first serial, iclass 22, count 0 2006.173.15:09:13.81#ibcon#enter sib2, iclass 22, count 0 2006.173.15:09:13.81#ibcon#flushed, iclass 22, count 0 2006.173.15:09:13.81#ibcon#about to write, iclass 22, count 0 2006.173.15:09:13.81#ibcon#wrote, iclass 22, count 0 2006.173.15:09:13.81#ibcon#about to read 3, iclass 22, count 0 2006.173.15:09:13.83#ibcon#read 3, iclass 22, count 0 2006.173.15:09:13.83#ibcon#about to read 4, iclass 22, count 0 2006.173.15:09:13.83#ibcon#read 4, iclass 22, count 0 2006.173.15:09:13.83#ibcon#about to read 5, iclass 22, count 0 2006.173.15:09:13.83#ibcon#read 5, iclass 22, count 0 2006.173.15:09:13.83#ibcon#about to read 6, iclass 22, count 0 2006.173.15:09:13.83#ibcon#read 6, iclass 22, count 0 2006.173.15:09:13.83#ibcon#end of sib2, iclass 22, count 0 2006.173.15:09:13.83#ibcon#*mode == 0, iclass 22, count 0 2006.173.15:09:13.83#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.15:09:13.83#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.15:09:13.83#ibcon#*before write, iclass 22, count 0 2006.173.15:09:13.83#ibcon#enter sib2, iclass 22, count 0 2006.173.15:09:13.83#ibcon#flushed, iclass 22, count 0 2006.173.15:09:13.83#ibcon#about to write, iclass 22, count 0 2006.173.15:09:13.83#ibcon#wrote, iclass 22, count 0 2006.173.15:09:13.83#ibcon#about to read 3, iclass 22, count 0 2006.173.15:09:13.87#ibcon#read 3, iclass 22, count 0 2006.173.15:09:13.87#ibcon#about to read 4, iclass 22, count 0 2006.173.15:09:13.87#ibcon#read 4, iclass 22, count 0 2006.173.15:09:13.87#ibcon#about to read 5, iclass 22, count 0 2006.173.15:09:13.87#ibcon#read 5, iclass 22, count 0 2006.173.15:09:13.87#ibcon#about to read 6, iclass 22, count 0 2006.173.15:09:13.87#ibcon#read 6, iclass 22, count 0 2006.173.15:09:13.87#ibcon#end of sib2, iclass 22, count 0 2006.173.15:09:13.87#ibcon#*after write, iclass 22, count 0 2006.173.15:09:13.87#ibcon#*before return 0, iclass 22, count 0 2006.173.15:09:13.87#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.15:09:13.87#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.15:09:13.87#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.15:09:13.87#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.15:09:13.87$vck44/vb=1,4 2006.173.15:09:13.87#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.15:09:13.87#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.15:09:13.87#ibcon#ireg 11 cls_cnt 2 2006.173.15:09:13.87#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.15:09:13.87#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.15:09:13.87#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.15:09:13.87#ibcon#enter wrdev, iclass 24, count 2 2006.173.15:09:13.87#ibcon#first serial, iclass 24, count 2 2006.173.15:09:13.87#ibcon#enter sib2, iclass 24, count 2 2006.173.15:09:13.87#ibcon#flushed, iclass 24, count 2 2006.173.15:09:13.87#ibcon#about to write, iclass 24, count 2 2006.173.15:09:13.87#ibcon#wrote, iclass 24, count 2 2006.173.15:09:13.87#ibcon#about to read 3, iclass 24, count 2 2006.173.15:09:13.89#ibcon#read 3, iclass 24, count 2 2006.173.15:09:13.89#ibcon#about to read 4, iclass 24, count 2 2006.173.15:09:13.89#ibcon#read 4, iclass 24, count 2 2006.173.15:09:13.89#ibcon#about to read 5, iclass 24, count 2 2006.173.15:09:13.89#ibcon#read 5, iclass 24, count 2 2006.173.15:09:13.89#ibcon#about to read 6, iclass 24, count 2 2006.173.15:09:13.89#ibcon#read 6, iclass 24, count 2 2006.173.15:09:13.89#ibcon#end of sib2, iclass 24, count 2 2006.173.15:09:13.89#ibcon#*mode == 0, iclass 24, count 2 2006.173.15:09:13.89#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.15:09:13.89#ibcon#[27=AT01-04\r\n] 2006.173.15:09:13.89#ibcon#*before write, iclass 24, count 2 2006.173.15:09:13.89#ibcon#enter sib2, iclass 24, count 2 2006.173.15:09:13.89#ibcon#flushed, iclass 24, count 2 2006.173.15:09:13.89#ibcon#about to write, iclass 24, count 2 2006.173.15:09:13.89#ibcon#wrote, iclass 24, count 2 2006.173.15:09:13.89#ibcon#about to read 3, iclass 24, count 2 2006.173.15:09:13.92#ibcon#read 3, iclass 24, count 2 2006.173.15:09:13.92#ibcon#about to read 4, iclass 24, count 2 2006.173.15:09:13.92#ibcon#read 4, iclass 24, count 2 2006.173.15:09:13.92#ibcon#about to read 5, iclass 24, count 2 2006.173.15:09:13.92#ibcon#read 5, iclass 24, count 2 2006.173.15:09:13.92#ibcon#about to read 6, iclass 24, count 2 2006.173.15:09:13.92#ibcon#read 6, iclass 24, count 2 2006.173.15:09:13.92#ibcon#end of sib2, iclass 24, count 2 2006.173.15:09:13.92#ibcon#*after write, iclass 24, count 2 2006.173.15:09:13.92#ibcon#*before return 0, iclass 24, count 2 2006.173.15:09:13.92#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.15:09:13.92#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.15:09:13.92#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.15:09:13.92#ibcon#ireg 7 cls_cnt 0 2006.173.15:09:13.92#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.15:09:14.04#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.15:09:14.04#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.15:09:14.04#ibcon#enter wrdev, iclass 24, count 0 2006.173.15:09:14.04#ibcon#first serial, iclass 24, count 0 2006.173.15:09:14.04#ibcon#enter sib2, iclass 24, count 0 2006.173.15:09:14.04#ibcon#flushed, iclass 24, count 0 2006.173.15:09:14.04#ibcon#about to write, iclass 24, count 0 2006.173.15:09:14.04#ibcon#wrote, iclass 24, count 0 2006.173.15:09:14.04#ibcon#about to read 3, iclass 24, count 0 2006.173.15:09:14.06#ibcon#read 3, iclass 24, count 0 2006.173.15:09:14.06#ibcon#about to read 4, iclass 24, count 0 2006.173.15:09:14.06#ibcon#read 4, iclass 24, count 0 2006.173.15:09:14.06#ibcon#about to read 5, iclass 24, count 0 2006.173.15:09:14.06#ibcon#read 5, iclass 24, count 0 2006.173.15:09:14.06#ibcon#about to read 6, iclass 24, count 0 2006.173.15:09:14.06#ibcon#read 6, iclass 24, count 0 2006.173.15:09:14.06#ibcon#end of sib2, iclass 24, count 0 2006.173.15:09:14.06#ibcon#*mode == 0, iclass 24, count 0 2006.173.15:09:14.06#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.15:09:14.06#ibcon#[27=USB\r\n] 2006.173.15:09:14.06#ibcon#*before write, iclass 24, count 0 2006.173.15:09:14.06#ibcon#enter sib2, iclass 24, count 0 2006.173.15:09:14.06#ibcon#flushed, iclass 24, count 0 2006.173.15:09:14.06#ibcon#about to write, iclass 24, count 0 2006.173.15:09:14.06#ibcon#wrote, iclass 24, count 0 2006.173.15:09:14.06#ibcon#about to read 3, iclass 24, count 0 2006.173.15:09:14.09#ibcon#read 3, iclass 24, count 0 2006.173.15:09:14.09#ibcon#about to read 4, iclass 24, count 0 2006.173.15:09:14.09#ibcon#read 4, iclass 24, count 0 2006.173.15:09:14.09#ibcon#about to read 5, iclass 24, count 0 2006.173.15:09:14.09#ibcon#read 5, iclass 24, count 0 2006.173.15:09:14.09#ibcon#about to read 6, iclass 24, count 0 2006.173.15:09:14.09#ibcon#read 6, iclass 24, count 0 2006.173.15:09:14.09#ibcon#end of sib2, iclass 24, count 0 2006.173.15:09:14.09#ibcon#*after write, iclass 24, count 0 2006.173.15:09:14.09#ibcon#*before return 0, iclass 24, count 0 2006.173.15:09:14.09#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.15:09:14.09#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.15:09:14.09#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.15:09:14.09#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.15:09:14.09$vck44/vblo=2,634.99 2006.173.15:09:14.09#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.15:09:14.09#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.15:09:14.09#ibcon#ireg 17 cls_cnt 0 2006.173.15:09:14.09#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.15:09:14.09#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.15:09:14.09#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.15:09:14.09#ibcon#enter wrdev, iclass 26, count 0 2006.173.15:09:14.09#ibcon#first serial, iclass 26, count 0 2006.173.15:09:14.09#ibcon#enter sib2, iclass 26, count 0 2006.173.15:09:14.09#ibcon#flushed, iclass 26, count 0 2006.173.15:09:14.09#ibcon#about to write, iclass 26, count 0 2006.173.15:09:14.09#ibcon#wrote, iclass 26, count 0 2006.173.15:09:14.09#ibcon#about to read 3, iclass 26, count 0 2006.173.15:09:14.11#ibcon#read 3, iclass 26, count 0 2006.173.15:09:14.11#ibcon#about to read 4, iclass 26, count 0 2006.173.15:09:14.11#ibcon#read 4, iclass 26, count 0 2006.173.15:09:14.11#ibcon#about to read 5, iclass 26, count 0 2006.173.15:09:14.11#ibcon#read 5, iclass 26, count 0 2006.173.15:09:14.11#ibcon#about to read 6, iclass 26, count 0 2006.173.15:09:14.11#ibcon#read 6, iclass 26, count 0 2006.173.15:09:14.11#ibcon#end of sib2, iclass 26, count 0 2006.173.15:09:14.11#ibcon#*mode == 0, iclass 26, count 0 2006.173.15:09:14.11#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.15:09:14.11#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.15:09:14.11#ibcon#*before write, iclass 26, count 0 2006.173.15:09:14.11#ibcon#enter sib2, iclass 26, count 0 2006.173.15:09:14.11#ibcon#flushed, iclass 26, count 0 2006.173.15:09:14.11#ibcon#about to write, iclass 26, count 0 2006.173.15:09:14.11#ibcon#wrote, iclass 26, count 0 2006.173.15:09:14.11#ibcon#about to read 3, iclass 26, count 0 2006.173.15:09:14.15#ibcon#read 3, iclass 26, count 0 2006.173.15:09:14.15#ibcon#about to read 4, iclass 26, count 0 2006.173.15:09:14.15#ibcon#read 4, iclass 26, count 0 2006.173.15:09:14.15#ibcon#about to read 5, iclass 26, count 0 2006.173.15:09:14.15#ibcon#read 5, iclass 26, count 0 2006.173.15:09:14.15#ibcon#about to read 6, iclass 26, count 0 2006.173.15:09:14.15#ibcon#read 6, iclass 26, count 0 2006.173.15:09:14.15#ibcon#end of sib2, iclass 26, count 0 2006.173.15:09:14.15#ibcon#*after write, iclass 26, count 0 2006.173.15:09:14.15#ibcon#*before return 0, iclass 26, count 0 2006.173.15:09:14.15#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.15:09:14.15#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.15:09:14.15#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.15:09:14.15#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.15:09:14.15$vck44/vb=2,4 2006.173.15:09:14.15#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.15:09:14.15#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.15:09:14.15#ibcon#ireg 11 cls_cnt 2 2006.173.15:09:14.15#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.15:09:14.21#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.15:09:14.21#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.15:09:14.21#ibcon#enter wrdev, iclass 28, count 2 2006.173.15:09:14.21#ibcon#first serial, iclass 28, count 2 2006.173.15:09:14.21#ibcon#enter sib2, iclass 28, count 2 2006.173.15:09:14.21#ibcon#flushed, iclass 28, count 2 2006.173.15:09:14.21#ibcon#about to write, iclass 28, count 2 2006.173.15:09:14.21#ibcon#wrote, iclass 28, count 2 2006.173.15:09:14.21#ibcon#about to read 3, iclass 28, count 2 2006.173.15:09:14.23#ibcon#read 3, iclass 28, count 2 2006.173.15:09:14.23#ibcon#about to read 4, iclass 28, count 2 2006.173.15:09:14.23#ibcon#read 4, iclass 28, count 2 2006.173.15:09:14.23#ibcon#about to read 5, iclass 28, count 2 2006.173.15:09:14.23#ibcon#read 5, iclass 28, count 2 2006.173.15:09:14.23#ibcon#about to read 6, iclass 28, count 2 2006.173.15:09:14.23#ibcon#read 6, iclass 28, count 2 2006.173.15:09:14.23#ibcon#end of sib2, iclass 28, count 2 2006.173.15:09:14.23#ibcon#*mode == 0, iclass 28, count 2 2006.173.15:09:14.23#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.15:09:14.23#ibcon#[27=AT02-04\r\n] 2006.173.15:09:14.23#ibcon#*before write, iclass 28, count 2 2006.173.15:09:14.23#ibcon#enter sib2, iclass 28, count 2 2006.173.15:09:14.23#ibcon#flushed, iclass 28, count 2 2006.173.15:09:14.23#ibcon#about to write, iclass 28, count 2 2006.173.15:09:14.23#ibcon#wrote, iclass 28, count 2 2006.173.15:09:14.23#ibcon#about to read 3, iclass 28, count 2 2006.173.15:09:14.26#ibcon#read 3, iclass 28, count 2 2006.173.15:09:14.26#ibcon#about to read 4, iclass 28, count 2 2006.173.15:09:14.26#ibcon#read 4, iclass 28, count 2 2006.173.15:09:14.26#ibcon#about to read 5, iclass 28, count 2 2006.173.15:09:14.26#ibcon#read 5, iclass 28, count 2 2006.173.15:09:14.26#ibcon#about to read 6, iclass 28, count 2 2006.173.15:09:14.26#ibcon#read 6, iclass 28, count 2 2006.173.15:09:14.26#ibcon#end of sib2, iclass 28, count 2 2006.173.15:09:14.26#ibcon#*after write, iclass 28, count 2 2006.173.15:09:14.26#ibcon#*before return 0, iclass 28, count 2 2006.173.15:09:14.26#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.15:09:14.26#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.15:09:14.26#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.15:09:14.26#ibcon#ireg 7 cls_cnt 0 2006.173.15:09:14.26#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.15:09:14.38#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.15:09:14.38#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.15:09:14.38#ibcon#enter wrdev, iclass 28, count 0 2006.173.15:09:14.38#ibcon#first serial, iclass 28, count 0 2006.173.15:09:14.38#ibcon#enter sib2, iclass 28, count 0 2006.173.15:09:14.38#ibcon#flushed, iclass 28, count 0 2006.173.15:09:14.38#ibcon#about to write, iclass 28, count 0 2006.173.15:09:14.38#ibcon#wrote, iclass 28, count 0 2006.173.15:09:14.38#ibcon#about to read 3, iclass 28, count 0 2006.173.15:09:14.40#ibcon#read 3, iclass 28, count 0 2006.173.15:09:14.40#ibcon#about to read 4, iclass 28, count 0 2006.173.15:09:14.40#ibcon#read 4, iclass 28, count 0 2006.173.15:09:14.40#ibcon#about to read 5, iclass 28, count 0 2006.173.15:09:14.40#ibcon#read 5, iclass 28, count 0 2006.173.15:09:14.40#ibcon#about to read 6, iclass 28, count 0 2006.173.15:09:14.40#ibcon#read 6, iclass 28, count 0 2006.173.15:09:14.40#ibcon#end of sib2, iclass 28, count 0 2006.173.15:09:14.40#ibcon#*mode == 0, iclass 28, count 0 2006.173.15:09:14.40#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.15:09:14.40#ibcon#[27=USB\r\n] 2006.173.15:09:14.40#ibcon#*before write, iclass 28, count 0 2006.173.15:09:14.40#ibcon#enter sib2, iclass 28, count 0 2006.173.15:09:14.40#ibcon#flushed, iclass 28, count 0 2006.173.15:09:14.40#ibcon#about to write, iclass 28, count 0 2006.173.15:09:14.40#ibcon#wrote, iclass 28, count 0 2006.173.15:09:14.40#ibcon#about to read 3, iclass 28, count 0 2006.173.15:09:14.43#ibcon#read 3, iclass 28, count 0 2006.173.15:09:14.43#ibcon#about to read 4, iclass 28, count 0 2006.173.15:09:14.43#ibcon#read 4, iclass 28, count 0 2006.173.15:09:14.43#ibcon#about to read 5, iclass 28, count 0 2006.173.15:09:14.43#ibcon#read 5, iclass 28, count 0 2006.173.15:09:14.43#ibcon#about to read 6, iclass 28, count 0 2006.173.15:09:14.43#ibcon#read 6, iclass 28, count 0 2006.173.15:09:14.43#ibcon#end of sib2, iclass 28, count 0 2006.173.15:09:14.43#ibcon#*after write, iclass 28, count 0 2006.173.15:09:14.43#ibcon#*before return 0, iclass 28, count 0 2006.173.15:09:14.43#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.15:09:14.43#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.15:09:14.43#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.15:09:14.43#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.15:09:14.43$vck44/vblo=3,649.99 2006.173.15:09:14.43#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.15:09:14.43#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.15:09:14.43#ibcon#ireg 17 cls_cnt 0 2006.173.15:09:14.43#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.15:09:14.43#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.15:09:14.43#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.15:09:14.43#ibcon#enter wrdev, iclass 30, count 0 2006.173.15:09:14.43#ibcon#first serial, iclass 30, count 0 2006.173.15:09:14.43#ibcon#enter sib2, iclass 30, count 0 2006.173.15:09:14.43#ibcon#flushed, iclass 30, count 0 2006.173.15:09:14.43#ibcon#about to write, iclass 30, count 0 2006.173.15:09:14.43#ibcon#wrote, iclass 30, count 0 2006.173.15:09:14.43#ibcon#about to read 3, iclass 30, count 0 2006.173.15:09:14.45#ibcon#read 3, iclass 30, count 0 2006.173.15:09:14.45#ibcon#about to read 4, iclass 30, count 0 2006.173.15:09:14.45#ibcon#read 4, iclass 30, count 0 2006.173.15:09:14.45#ibcon#about to read 5, iclass 30, count 0 2006.173.15:09:14.45#ibcon#read 5, iclass 30, count 0 2006.173.15:09:14.45#ibcon#about to read 6, iclass 30, count 0 2006.173.15:09:14.45#ibcon#read 6, iclass 30, count 0 2006.173.15:09:14.45#ibcon#end of sib2, iclass 30, count 0 2006.173.15:09:14.45#ibcon#*mode == 0, iclass 30, count 0 2006.173.15:09:14.45#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.15:09:14.45#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.15:09:14.45#ibcon#*before write, iclass 30, count 0 2006.173.15:09:14.45#ibcon#enter sib2, iclass 30, count 0 2006.173.15:09:14.45#ibcon#flushed, iclass 30, count 0 2006.173.15:09:14.45#ibcon#about to write, iclass 30, count 0 2006.173.15:09:14.45#ibcon#wrote, iclass 30, count 0 2006.173.15:09:14.45#ibcon#about to read 3, iclass 30, count 0 2006.173.15:09:14.49#ibcon#read 3, iclass 30, count 0 2006.173.15:09:14.49#ibcon#about to read 4, iclass 30, count 0 2006.173.15:09:14.49#ibcon#read 4, iclass 30, count 0 2006.173.15:09:14.49#ibcon#about to read 5, iclass 30, count 0 2006.173.15:09:14.49#ibcon#read 5, iclass 30, count 0 2006.173.15:09:14.49#ibcon#about to read 6, iclass 30, count 0 2006.173.15:09:14.49#ibcon#read 6, iclass 30, count 0 2006.173.15:09:14.49#ibcon#end of sib2, iclass 30, count 0 2006.173.15:09:14.49#ibcon#*after write, iclass 30, count 0 2006.173.15:09:14.49#ibcon#*before return 0, iclass 30, count 0 2006.173.15:09:14.49#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.15:09:14.49#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.15:09:14.49#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.15:09:14.49#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.15:09:14.49$vck44/vb=3,4 2006.173.15:09:14.49#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.173.15:09:14.49#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.173.15:09:14.49#ibcon#ireg 11 cls_cnt 2 2006.173.15:09:14.49#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.15:09:14.55#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.15:09:14.55#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.15:09:14.55#ibcon#enter wrdev, iclass 32, count 2 2006.173.15:09:14.55#ibcon#first serial, iclass 32, count 2 2006.173.15:09:14.55#ibcon#enter sib2, iclass 32, count 2 2006.173.15:09:14.55#ibcon#flushed, iclass 32, count 2 2006.173.15:09:14.55#ibcon#about to write, iclass 32, count 2 2006.173.15:09:14.55#ibcon#wrote, iclass 32, count 2 2006.173.15:09:14.55#ibcon#about to read 3, iclass 32, count 2 2006.173.15:09:14.57#ibcon#read 3, iclass 32, count 2 2006.173.15:09:14.57#ibcon#about to read 4, iclass 32, count 2 2006.173.15:09:14.57#ibcon#read 4, iclass 32, count 2 2006.173.15:09:14.57#ibcon#about to read 5, iclass 32, count 2 2006.173.15:09:14.57#ibcon#read 5, iclass 32, count 2 2006.173.15:09:14.57#ibcon#about to read 6, iclass 32, count 2 2006.173.15:09:14.57#ibcon#read 6, iclass 32, count 2 2006.173.15:09:14.57#ibcon#end of sib2, iclass 32, count 2 2006.173.15:09:14.57#ibcon#*mode == 0, iclass 32, count 2 2006.173.15:09:14.57#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.173.15:09:14.57#ibcon#[27=AT03-04\r\n] 2006.173.15:09:14.57#ibcon#*before write, iclass 32, count 2 2006.173.15:09:14.57#ibcon#enter sib2, iclass 32, count 2 2006.173.15:09:14.57#ibcon#flushed, iclass 32, count 2 2006.173.15:09:14.57#ibcon#about to write, iclass 32, count 2 2006.173.15:09:14.57#ibcon#wrote, iclass 32, count 2 2006.173.15:09:14.57#ibcon#about to read 3, iclass 32, count 2 2006.173.15:09:14.60#ibcon#read 3, iclass 32, count 2 2006.173.15:09:14.60#ibcon#about to read 4, iclass 32, count 2 2006.173.15:09:14.60#ibcon#read 4, iclass 32, count 2 2006.173.15:09:14.60#ibcon#about to read 5, iclass 32, count 2 2006.173.15:09:14.60#ibcon#read 5, iclass 32, count 2 2006.173.15:09:14.60#ibcon#about to read 6, iclass 32, count 2 2006.173.15:09:14.60#ibcon#read 6, iclass 32, count 2 2006.173.15:09:14.60#ibcon#end of sib2, iclass 32, count 2 2006.173.15:09:14.60#ibcon#*after write, iclass 32, count 2 2006.173.15:09:14.60#ibcon#*before return 0, iclass 32, count 2 2006.173.15:09:14.60#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.15:09:14.60#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.173.15:09:14.60#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.173.15:09:14.60#ibcon#ireg 7 cls_cnt 0 2006.173.15:09:14.60#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.15:09:14.72#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.15:09:14.72#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.15:09:14.72#ibcon#enter wrdev, iclass 32, count 0 2006.173.15:09:14.72#ibcon#first serial, iclass 32, count 0 2006.173.15:09:14.72#ibcon#enter sib2, iclass 32, count 0 2006.173.15:09:14.72#ibcon#flushed, iclass 32, count 0 2006.173.15:09:14.72#ibcon#about to write, iclass 32, count 0 2006.173.15:09:14.72#ibcon#wrote, iclass 32, count 0 2006.173.15:09:14.72#ibcon#about to read 3, iclass 32, count 0 2006.173.15:09:14.74#ibcon#read 3, iclass 32, count 0 2006.173.15:09:14.74#ibcon#about to read 4, iclass 32, count 0 2006.173.15:09:14.74#ibcon#read 4, iclass 32, count 0 2006.173.15:09:14.74#ibcon#about to read 5, iclass 32, count 0 2006.173.15:09:14.74#ibcon#read 5, iclass 32, count 0 2006.173.15:09:14.74#ibcon#about to read 6, iclass 32, count 0 2006.173.15:09:14.74#ibcon#read 6, iclass 32, count 0 2006.173.15:09:14.74#ibcon#end of sib2, iclass 32, count 0 2006.173.15:09:14.74#ibcon#*mode == 0, iclass 32, count 0 2006.173.15:09:14.74#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.15:09:14.74#ibcon#[27=USB\r\n] 2006.173.15:09:14.74#ibcon#*before write, iclass 32, count 0 2006.173.15:09:14.74#ibcon#enter sib2, iclass 32, count 0 2006.173.15:09:14.74#ibcon#flushed, iclass 32, count 0 2006.173.15:09:14.74#ibcon#about to write, iclass 32, count 0 2006.173.15:09:14.74#ibcon#wrote, iclass 32, count 0 2006.173.15:09:14.74#ibcon#about to read 3, iclass 32, count 0 2006.173.15:09:14.77#ibcon#read 3, iclass 32, count 0 2006.173.15:09:14.77#ibcon#about to read 4, iclass 32, count 0 2006.173.15:09:14.77#ibcon#read 4, iclass 32, count 0 2006.173.15:09:14.77#ibcon#about to read 5, iclass 32, count 0 2006.173.15:09:14.77#ibcon#read 5, iclass 32, count 0 2006.173.15:09:14.77#ibcon#about to read 6, iclass 32, count 0 2006.173.15:09:14.77#ibcon#read 6, iclass 32, count 0 2006.173.15:09:14.77#ibcon#end of sib2, iclass 32, count 0 2006.173.15:09:14.77#ibcon#*after write, iclass 32, count 0 2006.173.15:09:14.77#ibcon#*before return 0, iclass 32, count 0 2006.173.15:09:14.77#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.15:09:14.77#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.173.15:09:14.77#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.15:09:14.77#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.15:09:14.77$vck44/vblo=4,679.99 2006.173.15:09:14.77#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.15:09:14.77#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.15:09:14.77#ibcon#ireg 17 cls_cnt 0 2006.173.15:09:14.77#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.15:09:14.77#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.15:09:14.77#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.15:09:14.77#ibcon#enter wrdev, iclass 34, count 0 2006.173.15:09:14.77#ibcon#first serial, iclass 34, count 0 2006.173.15:09:14.77#ibcon#enter sib2, iclass 34, count 0 2006.173.15:09:14.77#ibcon#flushed, iclass 34, count 0 2006.173.15:09:14.77#ibcon#about to write, iclass 34, count 0 2006.173.15:09:14.77#ibcon#wrote, iclass 34, count 0 2006.173.15:09:14.77#ibcon#about to read 3, iclass 34, count 0 2006.173.15:09:14.79#ibcon#read 3, iclass 34, count 0 2006.173.15:09:14.79#ibcon#about to read 4, iclass 34, count 0 2006.173.15:09:14.79#ibcon#read 4, iclass 34, count 0 2006.173.15:09:14.79#ibcon#about to read 5, iclass 34, count 0 2006.173.15:09:14.79#ibcon#read 5, iclass 34, count 0 2006.173.15:09:14.79#ibcon#about to read 6, iclass 34, count 0 2006.173.15:09:14.79#ibcon#read 6, iclass 34, count 0 2006.173.15:09:14.79#ibcon#end of sib2, iclass 34, count 0 2006.173.15:09:14.79#ibcon#*mode == 0, iclass 34, count 0 2006.173.15:09:14.79#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.15:09:14.79#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.15:09:14.79#ibcon#*before write, iclass 34, count 0 2006.173.15:09:14.79#ibcon#enter sib2, iclass 34, count 0 2006.173.15:09:14.79#ibcon#flushed, iclass 34, count 0 2006.173.15:09:14.79#ibcon#about to write, iclass 34, count 0 2006.173.15:09:14.79#ibcon#wrote, iclass 34, count 0 2006.173.15:09:14.79#ibcon#about to read 3, iclass 34, count 0 2006.173.15:09:14.83#ibcon#read 3, iclass 34, count 0 2006.173.15:09:14.83#ibcon#about to read 4, iclass 34, count 0 2006.173.15:09:14.83#ibcon#read 4, iclass 34, count 0 2006.173.15:09:14.83#ibcon#about to read 5, iclass 34, count 0 2006.173.15:09:14.83#ibcon#read 5, iclass 34, count 0 2006.173.15:09:14.83#ibcon#about to read 6, iclass 34, count 0 2006.173.15:09:14.83#ibcon#read 6, iclass 34, count 0 2006.173.15:09:14.83#ibcon#end of sib2, iclass 34, count 0 2006.173.15:09:14.83#ibcon#*after write, iclass 34, count 0 2006.173.15:09:14.83#ibcon#*before return 0, iclass 34, count 0 2006.173.15:09:14.83#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.15:09:14.83#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.15:09:14.83#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.15:09:14.83#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.15:09:14.83$vck44/vb=4,4 2006.173.15:09:14.83#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.15:09:14.83#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.15:09:14.83#ibcon#ireg 11 cls_cnt 2 2006.173.15:09:14.83#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.15:09:14.89#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.15:09:14.89#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.15:09:14.89#ibcon#enter wrdev, iclass 36, count 2 2006.173.15:09:14.89#ibcon#first serial, iclass 36, count 2 2006.173.15:09:14.89#ibcon#enter sib2, iclass 36, count 2 2006.173.15:09:14.89#ibcon#flushed, iclass 36, count 2 2006.173.15:09:14.89#ibcon#about to write, iclass 36, count 2 2006.173.15:09:14.89#ibcon#wrote, iclass 36, count 2 2006.173.15:09:14.89#ibcon#about to read 3, iclass 36, count 2 2006.173.15:09:14.91#ibcon#read 3, iclass 36, count 2 2006.173.15:09:14.91#ibcon#about to read 4, iclass 36, count 2 2006.173.15:09:14.91#ibcon#read 4, iclass 36, count 2 2006.173.15:09:14.91#ibcon#about to read 5, iclass 36, count 2 2006.173.15:09:14.91#ibcon#read 5, iclass 36, count 2 2006.173.15:09:14.91#ibcon#about to read 6, iclass 36, count 2 2006.173.15:09:14.91#ibcon#read 6, iclass 36, count 2 2006.173.15:09:14.91#ibcon#end of sib2, iclass 36, count 2 2006.173.15:09:14.91#ibcon#*mode == 0, iclass 36, count 2 2006.173.15:09:14.91#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.15:09:14.91#ibcon#[27=AT04-04\r\n] 2006.173.15:09:14.91#ibcon#*before write, iclass 36, count 2 2006.173.15:09:14.91#ibcon#enter sib2, iclass 36, count 2 2006.173.15:09:14.91#ibcon#flushed, iclass 36, count 2 2006.173.15:09:14.91#ibcon#about to write, iclass 36, count 2 2006.173.15:09:14.91#ibcon#wrote, iclass 36, count 2 2006.173.15:09:14.91#ibcon#about to read 3, iclass 36, count 2 2006.173.15:09:14.94#ibcon#read 3, iclass 36, count 2 2006.173.15:09:14.94#ibcon#about to read 4, iclass 36, count 2 2006.173.15:09:14.94#ibcon#read 4, iclass 36, count 2 2006.173.15:09:14.94#ibcon#about to read 5, iclass 36, count 2 2006.173.15:09:14.94#ibcon#read 5, iclass 36, count 2 2006.173.15:09:14.94#ibcon#about to read 6, iclass 36, count 2 2006.173.15:09:14.94#ibcon#read 6, iclass 36, count 2 2006.173.15:09:14.94#ibcon#end of sib2, iclass 36, count 2 2006.173.15:09:14.94#ibcon#*after write, iclass 36, count 2 2006.173.15:09:14.94#ibcon#*before return 0, iclass 36, count 2 2006.173.15:09:14.94#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.15:09:14.94#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.15:09:14.94#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.15:09:14.94#ibcon#ireg 7 cls_cnt 0 2006.173.15:09:14.94#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.15:09:15.06#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.15:09:15.06#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.15:09:15.06#ibcon#enter wrdev, iclass 36, count 0 2006.173.15:09:15.06#ibcon#first serial, iclass 36, count 0 2006.173.15:09:15.06#ibcon#enter sib2, iclass 36, count 0 2006.173.15:09:15.06#ibcon#flushed, iclass 36, count 0 2006.173.15:09:15.06#ibcon#about to write, iclass 36, count 0 2006.173.15:09:15.06#ibcon#wrote, iclass 36, count 0 2006.173.15:09:15.06#ibcon#about to read 3, iclass 36, count 0 2006.173.15:09:15.08#ibcon#read 3, iclass 36, count 0 2006.173.15:09:15.08#ibcon#about to read 4, iclass 36, count 0 2006.173.15:09:15.08#ibcon#read 4, iclass 36, count 0 2006.173.15:09:15.08#ibcon#about to read 5, iclass 36, count 0 2006.173.15:09:15.08#ibcon#read 5, iclass 36, count 0 2006.173.15:09:15.08#ibcon#about to read 6, iclass 36, count 0 2006.173.15:09:15.08#ibcon#read 6, iclass 36, count 0 2006.173.15:09:15.08#ibcon#end of sib2, iclass 36, count 0 2006.173.15:09:15.08#ibcon#*mode == 0, iclass 36, count 0 2006.173.15:09:15.08#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.15:09:15.08#ibcon#[27=USB\r\n] 2006.173.15:09:15.08#ibcon#*before write, iclass 36, count 0 2006.173.15:09:15.08#ibcon#enter sib2, iclass 36, count 0 2006.173.15:09:15.08#ibcon#flushed, iclass 36, count 0 2006.173.15:09:15.08#ibcon#about to write, iclass 36, count 0 2006.173.15:09:15.08#ibcon#wrote, iclass 36, count 0 2006.173.15:09:15.08#ibcon#about to read 3, iclass 36, count 0 2006.173.15:09:15.11#ibcon#read 3, iclass 36, count 0 2006.173.15:09:15.11#ibcon#about to read 4, iclass 36, count 0 2006.173.15:09:15.11#ibcon#read 4, iclass 36, count 0 2006.173.15:09:15.11#ibcon#about to read 5, iclass 36, count 0 2006.173.15:09:15.11#ibcon#read 5, iclass 36, count 0 2006.173.15:09:15.11#ibcon#about to read 6, iclass 36, count 0 2006.173.15:09:15.11#ibcon#read 6, iclass 36, count 0 2006.173.15:09:15.11#ibcon#end of sib2, iclass 36, count 0 2006.173.15:09:15.11#ibcon#*after write, iclass 36, count 0 2006.173.15:09:15.11#ibcon#*before return 0, iclass 36, count 0 2006.173.15:09:15.11#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.15:09:15.11#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.15:09:15.11#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.15:09:15.11#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.15:09:15.11$vck44/vblo=5,709.99 2006.173.15:09:15.11#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.15:09:15.11#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.15:09:15.11#ibcon#ireg 17 cls_cnt 0 2006.173.15:09:15.11#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.15:09:15.11#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.15:09:15.11#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.15:09:15.11#ibcon#enter wrdev, iclass 38, count 0 2006.173.15:09:15.11#ibcon#first serial, iclass 38, count 0 2006.173.15:09:15.11#ibcon#enter sib2, iclass 38, count 0 2006.173.15:09:15.11#ibcon#flushed, iclass 38, count 0 2006.173.15:09:15.11#ibcon#about to write, iclass 38, count 0 2006.173.15:09:15.11#ibcon#wrote, iclass 38, count 0 2006.173.15:09:15.11#ibcon#about to read 3, iclass 38, count 0 2006.173.15:09:15.13#ibcon#read 3, iclass 38, count 0 2006.173.15:09:15.13#ibcon#about to read 4, iclass 38, count 0 2006.173.15:09:15.13#ibcon#read 4, iclass 38, count 0 2006.173.15:09:15.13#ibcon#about to read 5, iclass 38, count 0 2006.173.15:09:15.13#ibcon#read 5, iclass 38, count 0 2006.173.15:09:15.13#ibcon#about to read 6, iclass 38, count 0 2006.173.15:09:15.13#ibcon#read 6, iclass 38, count 0 2006.173.15:09:15.13#ibcon#end of sib2, iclass 38, count 0 2006.173.15:09:15.13#ibcon#*mode == 0, iclass 38, count 0 2006.173.15:09:15.13#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.15:09:15.13#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.15:09:15.13#ibcon#*before write, iclass 38, count 0 2006.173.15:09:15.13#ibcon#enter sib2, iclass 38, count 0 2006.173.15:09:15.13#ibcon#flushed, iclass 38, count 0 2006.173.15:09:15.13#ibcon#about to write, iclass 38, count 0 2006.173.15:09:15.13#ibcon#wrote, iclass 38, count 0 2006.173.15:09:15.13#ibcon#about to read 3, iclass 38, count 0 2006.173.15:09:15.17#ibcon#read 3, iclass 38, count 0 2006.173.15:09:15.17#ibcon#about to read 4, iclass 38, count 0 2006.173.15:09:15.17#ibcon#read 4, iclass 38, count 0 2006.173.15:09:15.17#ibcon#about to read 5, iclass 38, count 0 2006.173.15:09:15.17#ibcon#read 5, iclass 38, count 0 2006.173.15:09:15.17#ibcon#about to read 6, iclass 38, count 0 2006.173.15:09:15.17#ibcon#read 6, iclass 38, count 0 2006.173.15:09:15.17#ibcon#end of sib2, iclass 38, count 0 2006.173.15:09:15.17#ibcon#*after write, iclass 38, count 0 2006.173.15:09:15.17#ibcon#*before return 0, iclass 38, count 0 2006.173.15:09:15.17#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.15:09:15.17#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.15:09:15.17#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.15:09:15.17#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.15:09:15.17$vck44/vb=5,4 2006.173.15:09:15.17#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.15:09:15.17#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.15:09:15.17#ibcon#ireg 11 cls_cnt 2 2006.173.15:09:15.17#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.15:09:15.23#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.15:09:15.23#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.15:09:15.23#ibcon#enter wrdev, iclass 40, count 2 2006.173.15:09:15.23#ibcon#first serial, iclass 40, count 2 2006.173.15:09:15.23#ibcon#enter sib2, iclass 40, count 2 2006.173.15:09:15.23#ibcon#flushed, iclass 40, count 2 2006.173.15:09:15.23#ibcon#about to write, iclass 40, count 2 2006.173.15:09:15.23#ibcon#wrote, iclass 40, count 2 2006.173.15:09:15.23#ibcon#about to read 3, iclass 40, count 2 2006.173.15:09:15.25#ibcon#read 3, iclass 40, count 2 2006.173.15:09:15.25#ibcon#about to read 4, iclass 40, count 2 2006.173.15:09:15.25#ibcon#read 4, iclass 40, count 2 2006.173.15:09:15.25#ibcon#about to read 5, iclass 40, count 2 2006.173.15:09:15.25#ibcon#read 5, iclass 40, count 2 2006.173.15:09:15.25#ibcon#about to read 6, iclass 40, count 2 2006.173.15:09:15.25#ibcon#read 6, iclass 40, count 2 2006.173.15:09:15.25#ibcon#end of sib2, iclass 40, count 2 2006.173.15:09:15.25#ibcon#*mode == 0, iclass 40, count 2 2006.173.15:09:15.25#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.15:09:15.25#ibcon#[27=AT05-04\r\n] 2006.173.15:09:15.25#ibcon#*before write, iclass 40, count 2 2006.173.15:09:15.25#ibcon#enter sib2, iclass 40, count 2 2006.173.15:09:15.25#ibcon#flushed, iclass 40, count 2 2006.173.15:09:15.25#ibcon#about to write, iclass 40, count 2 2006.173.15:09:15.25#ibcon#wrote, iclass 40, count 2 2006.173.15:09:15.25#ibcon#about to read 3, iclass 40, count 2 2006.173.15:09:15.28#ibcon#read 3, iclass 40, count 2 2006.173.15:09:15.28#ibcon#about to read 4, iclass 40, count 2 2006.173.15:09:15.28#ibcon#read 4, iclass 40, count 2 2006.173.15:09:15.28#ibcon#about to read 5, iclass 40, count 2 2006.173.15:09:15.28#ibcon#read 5, iclass 40, count 2 2006.173.15:09:15.28#ibcon#about to read 6, iclass 40, count 2 2006.173.15:09:15.28#ibcon#read 6, iclass 40, count 2 2006.173.15:09:15.28#ibcon#end of sib2, iclass 40, count 2 2006.173.15:09:15.28#ibcon#*after write, iclass 40, count 2 2006.173.15:09:15.28#ibcon#*before return 0, iclass 40, count 2 2006.173.15:09:15.28#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.15:09:15.28#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.15:09:15.28#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.15:09:15.28#ibcon#ireg 7 cls_cnt 0 2006.173.15:09:15.28#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.15:09:15.40#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.15:09:15.40#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.15:09:15.40#ibcon#enter wrdev, iclass 40, count 0 2006.173.15:09:15.40#ibcon#first serial, iclass 40, count 0 2006.173.15:09:15.40#ibcon#enter sib2, iclass 40, count 0 2006.173.15:09:15.40#ibcon#flushed, iclass 40, count 0 2006.173.15:09:15.40#ibcon#about to write, iclass 40, count 0 2006.173.15:09:15.40#ibcon#wrote, iclass 40, count 0 2006.173.15:09:15.40#ibcon#about to read 3, iclass 40, count 0 2006.173.15:09:15.42#ibcon#read 3, iclass 40, count 0 2006.173.15:09:15.42#ibcon#about to read 4, iclass 40, count 0 2006.173.15:09:15.42#ibcon#read 4, iclass 40, count 0 2006.173.15:09:15.42#ibcon#about to read 5, iclass 40, count 0 2006.173.15:09:15.42#ibcon#read 5, iclass 40, count 0 2006.173.15:09:15.42#ibcon#about to read 6, iclass 40, count 0 2006.173.15:09:15.42#ibcon#read 6, iclass 40, count 0 2006.173.15:09:15.42#ibcon#end of sib2, iclass 40, count 0 2006.173.15:09:15.42#ibcon#*mode == 0, iclass 40, count 0 2006.173.15:09:15.42#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.15:09:15.42#ibcon#[27=USB\r\n] 2006.173.15:09:15.42#ibcon#*before write, iclass 40, count 0 2006.173.15:09:15.42#ibcon#enter sib2, iclass 40, count 0 2006.173.15:09:15.42#ibcon#flushed, iclass 40, count 0 2006.173.15:09:15.42#ibcon#about to write, iclass 40, count 0 2006.173.15:09:15.42#ibcon#wrote, iclass 40, count 0 2006.173.15:09:15.42#ibcon#about to read 3, iclass 40, count 0 2006.173.15:09:15.45#ibcon#read 3, iclass 40, count 0 2006.173.15:09:15.45#ibcon#about to read 4, iclass 40, count 0 2006.173.15:09:15.45#ibcon#read 4, iclass 40, count 0 2006.173.15:09:15.45#ibcon#about to read 5, iclass 40, count 0 2006.173.15:09:15.45#ibcon#read 5, iclass 40, count 0 2006.173.15:09:15.45#ibcon#about to read 6, iclass 40, count 0 2006.173.15:09:15.45#ibcon#read 6, iclass 40, count 0 2006.173.15:09:15.45#ibcon#end of sib2, iclass 40, count 0 2006.173.15:09:15.45#ibcon#*after write, iclass 40, count 0 2006.173.15:09:15.45#ibcon#*before return 0, iclass 40, count 0 2006.173.15:09:15.45#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.15:09:15.45#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.15:09:15.45#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.15:09:15.45#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.15:09:15.45$vck44/vblo=6,719.99 2006.173.15:09:15.45#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.15:09:15.45#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.15:09:15.45#ibcon#ireg 17 cls_cnt 0 2006.173.15:09:15.45#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.15:09:15.45#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.15:09:15.45#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.15:09:15.45#ibcon#enter wrdev, iclass 4, count 0 2006.173.15:09:15.45#ibcon#first serial, iclass 4, count 0 2006.173.15:09:15.45#ibcon#enter sib2, iclass 4, count 0 2006.173.15:09:15.45#ibcon#flushed, iclass 4, count 0 2006.173.15:09:15.45#ibcon#about to write, iclass 4, count 0 2006.173.15:09:15.45#ibcon#wrote, iclass 4, count 0 2006.173.15:09:15.45#ibcon#about to read 3, iclass 4, count 0 2006.173.15:09:15.47#ibcon#read 3, iclass 4, count 0 2006.173.15:09:15.47#ibcon#about to read 4, iclass 4, count 0 2006.173.15:09:15.47#ibcon#read 4, iclass 4, count 0 2006.173.15:09:15.47#ibcon#about to read 5, iclass 4, count 0 2006.173.15:09:15.47#ibcon#read 5, iclass 4, count 0 2006.173.15:09:15.47#ibcon#about to read 6, iclass 4, count 0 2006.173.15:09:15.47#ibcon#read 6, iclass 4, count 0 2006.173.15:09:15.47#ibcon#end of sib2, iclass 4, count 0 2006.173.15:09:15.47#ibcon#*mode == 0, iclass 4, count 0 2006.173.15:09:15.47#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.15:09:15.47#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.15:09:15.47#ibcon#*before write, iclass 4, count 0 2006.173.15:09:15.47#ibcon#enter sib2, iclass 4, count 0 2006.173.15:09:15.47#ibcon#flushed, iclass 4, count 0 2006.173.15:09:15.47#ibcon#about to write, iclass 4, count 0 2006.173.15:09:15.47#ibcon#wrote, iclass 4, count 0 2006.173.15:09:15.47#ibcon#about to read 3, iclass 4, count 0 2006.173.15:09:15.51#ibcon#read 3, iclass 4, count 0 2006.173.15:09:15.51#ibcon#about to read 4, iclass 4, count 0 2006.173.15:09:15.51#ibcon#read 4, iclass 4, count 0 2006.173.15:09:15.51#ibcon#about to read 5, iclass 4, count 0 2006.173.15:09:15.51#ibcon#read 5, iclass 4, count 0 2006.173.15:09:15.51#ibcon#about to read 6, iclass 4, count 0 2006.173.15:09:15.51#ibcon#read 6, iclass 4, count 0 2006.173.15:09:15.51#ibcon#end of sib2, iclass 4, count 0 2006.173.15:09:15.51#ibcon#*after write, iclass 4, count 0 2006.173.15:09:15.51#ibcon#*before return 0, iclass 4, count 0 2006.173.15:09:15.51#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.15:09:15.51#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.15:09:15.51#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.15:09:15.51#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.15:09:15.51$vck44/vb=6,4 2006.173.15:09:15.51#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.15:09:15.51#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.15:09:15.51#ibcon#ireg 11 cls_cnt 2 2006.173.15:09:15.51#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.15:09:15.57#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.15:09:15.57#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.15:09:15.57#ibcon#enter wrdev, iclass 6, count 2 2006.173.15:09:15.57#ibcon#first serial, iclass 6, count 2 2006.173.15:09:15.57#ibcon#enter sib2, iclass 6, count 2 2006.173.15:09:15.57#ibcon#flushed, iclass 6, count 2 2006.173.15:09:15.57#ibcon#about to write, iclass 6, count 2 2006.173.15:09:15.57#ibcon#wrote, iclass 6, count 2 2006.173.15:09:15.57#ibcon#about to read 3, iclass 6, count 2 2006.173.15:09:15.59#ibcon#read 3, iclass 6, count 2 2006.173.15:09:15.59#ibcon#about to read 4, iclass 6, count 2 2006.173.15:09:15.59#ibcon#read 4, iclass 6, count 2 2006.173.15:09:15.59#ibcon#about to read 5, iclass 6, count 2 2006.173.15:09:15.59#ibcon#read 5, iclass 6, count 2 2006.173.15:09:15.59#ibcon#about to read 6, iclass 6, count 2 2006.173.15:09:15.59#ibcon#read 6, iclass 6, count 2 2006.173.15:09:15.59#ibcon#end of sib2, iclass 6, count 2 2006.173.15:09:15.59#ibcon#*mode == 0, iclass 6, count 2 2006.173.15:09:15.59#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.15:09:15.59#ibcon#[27=AT06-04\r\n] 2006.173.15:09:15.59#ibcon#*before write, iclass 6, count 2 2006.173.15:09:15.59#ibcon#enter sib2, iclass 6, count 2 2006.173.15:09:15.59#ibcon#flushed, iclass 6, count 2 2006.173.15:09:15.59#ibcon#about to write, iclass 6, count 2 2006.173.15:09:15.59#ibcon#wrote, iclass 6, count 2 2006.173.15:09:15.59#ibcon#about to read 3, iclass 6, count 2 2006.173.15:09:15.62#ibcon#read 3, iclass 6, count 2 2006.173.15:09:15.62#ibcon#about to read 4, iclass 6, count 2 2006.173.15:09:15.62#ibcon#read 4, iclass 6, count 2 2006.173.15:09:15.62#ibcon#about to read 5, iclass 6, count 2 2006.173.15:09:15.62#ibcon#read 5, iclass 6, count 2 2006.173.15:09:15.62#ibcon#about to read 6, iclass 6, count 2 2006.173.15:09:15.62#ibcon#read 6, iclass 6, count 2 2006.173.15:09:15.62#ibcon#end of sib2, iclass 6, count 2 2006.173.15:09:15.62#ibcon#*after write, iclass 6, count 2 2006.173.15:09:15.62#ibcon#*before return 0, iclass 6, count 2 2006.173.15:09:15.62#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.15:09:15.62#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.15:09:15.62#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.15:09:15.62#ibcon#ireg 7 cls_cnt 0 2006.173.15:09:15.62#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.15:09:15.74#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.15:09:15.74#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.15:09:15.74#ibcon#enter wrdev, iclass 6, count 0 2006.173.15:09:15.74#ibcon#first serial, iclass 6, count 0 2006.173.15:09:15.74#ibcon#enter sib2, iclass 6, count 0 2006.173.15:09:15.74#ibcon#flushed, iclass 6, count 0 2006.173.15:09:15.74#ibcon#about to write, iclass 6, count 0 2006.173.15:09:15.74#ibcon#wrote, iclass 6, count 0 2006.173.15:09:15.74#ibcon#about to read 3, iclass 6, count 0 2006.173.15:09:15.76#ibcon#read 3, iclass 6, count 0 2006.173.15:09:15.76#ibcon#about to read 4, iclass 6, count 0 2006.173.15:09:15.76#ibcon#read 4, iclass 6, count 0 2006.173.15:09:15.76#ibcon#about to read 5, iclass 6, count 0 2006.173.15:09:15.76#ibcon#read 5, iclass 6, count 0 2006.173.15:09:15.76#ibcon#about to read 6, iclass 6, count 0 2006.173.15:09:15.76#ibcon#read 6, iclass 6, count 0 2006.173.15:09:15.76#ibcon#end of sib2, iclass 6, count 0 2006.173.15:09:15.76#ibcon#*mode == 0, iclass 6, count 0 2006.173.15:09:15.76#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.15:09:15.76#ibcon#[27=USB\r\n] 2006.173.15:09:15.76#ibcon#*before write, iclass 6, count 0 2006.173.15:09:15.76#ibcon#enter sib2, iclass 6, count 0 2006.173.15:09:15.76#ibcon#flushed, iclass 6, count 0 2006.173.15:09:15.76#ibcon#about to write, iclass 6, count 0 2006.173.15:09:15.76#ibcon#wrote, iclass 6, count 0 2006.173.15:09:15.76#ibcon#about to read 3, iclass 6, count 0 2006.173.15:09:15.79#ibcon#read 3, iclass 6, count 0 2006.173.15:09:15.79#ibcon#about to read 4, iclass 6, count 0 2006.173.15:09:15.79#ibcon#read 4, iclass 6, count 0 2006.173.15:09:15.79#ibcon#about to read 5, iclass 6, count 0 2006.173.15:09:15.79#ibcon#read 5, iclass 6, count 0 2006.173.15:09:15.79#ibcon#about to read 6, iclass 6, count 0 2006.173.15:09:15.79#ibcon#read 6, iclass 6, count 0 2006.173.15:09:15.79#ibcon#end of sib2, iclass 6, count 0 2006.173.15:09:15.79#ibcon#*after write, iclass 6, count 0 2006.173.15:09:15.79#ibcon#*before return 0, iclass 6, count 0 2006.173.15:09:15.79#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.15:09:15.79#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.15:09:15.79#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.15:09:15.79#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.15:09:15.79$vck44/vblo=7,734.99 2006.173.15:09:15.79#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.15:09:15.79#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.15:09:15.79#ibcon#ireg 17 cls_cnt 0 2006.173.15:09:15.79#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.15:09:15.79#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.15:09:15.79#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.15:09:15.79#ibcon#enter wrdev, iclass 10, count 0 2006.173.15:09:15.79#ibcon#first serial, iclass 10, count 0 2006.173.15:09:15.79#ibcon#enter sib2, iclass 10, count 0 2006.173.15:09:15.79#ibcon#flushed, iclass 10, count 0 2006.173.15:09:15.79#ibcon#about to write, iclass 10, count 0 2006.173.15:09:15.79#ibcon#wrote, iclass 10, count 0 2006.173.15:09:15.79#ibcon#about to read 3, iclass 10, count 0 2006.173.15:09:15.81#ibcon#read 3, iclass 10, count 0 2006.173.15:09:15.81#ibcon#about to read 4, iclass 10, count 0 2006.173.15:09:15.81#ibcon#read 4, iclass 10, count 0 2006.173.15:09:15.81#ibcon#about to read 5, iclass 10, count 0 2006.173.15:09:15.81#ibcon#read 5, iclass 10, count 0 2006.173.15:09:15.81#ibcon#about to read 6, iclass 10, count 0 2006.173.15:09:15.81#ibcon#read 6, iclass 10, count 0 2006.173.15:09:15.81#ibcon#end of sib2, iclass 10, count 0 2006.173.15:09:15.81#ibcon#*mode == 0, iclass 10, count 0 2006.173.15:09:15.81#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.15:09:15.81#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.15:09:15.81#ibcon#*before write, iclass 10, count 0 2006.173.15:09:15.81#ibcon#enter sib2, iclass 10, count 0 2006.173.15:09:15.81#ibcon#flushed, iclass 10, count 0 2006.173.15:09:15.81#ibcon#about to write, iclass 10, count 0 2006.173.15:09:15.81#ibcon#wrote, iclass 10, count 0 2006.173.15:09:15.81#ibcon#about to read 3, iclass 10, count 0 2006.173.15:09:15.85#ibcon#read 3, iclass 10, count 0 2006.173.15:09:15.85#ibcon#about to read 4, iclass 10, count 0 2006.173.15:09:15.85#ibcon#read 4, iclass 10, count 0 2006.173.15:09:15.85#ibcon#about to read 5, iclass 10, count 0 2006.173.15:09:15.85#ibcon#read 5, iclass 10, count 0 2006.173.15:09:15.85#ibcon#about to read 6, iclass 10, count 0 2006.173.15:09:15.85#ibcon#read 6, iclass 10, count 0 2006.173.15:09:15.85#ibcon#end of sib2, iclass 10, count 0 2006.173.15:09:15.85#ibcon#*after write, iclass 10, count 0 2006.173.15:09:15.85#ibcon#*before return 0, iclass 10, count 0 2006.173.15:09:15.85#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.15:09:15.85#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.15:09:15.85#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.15:09:15.85#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.15:09:15.85$vck44/vb=7,4 2006.173.15:09:15.85#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.15:09:15.85#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.15:09:15.85#ibcon#ireg 11 cls_cnt 2 2006.173.15:09:15.85#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.15:09:15.91#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.15:09:15.91#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.15:09:15.91#ibcon#enter wrdev, iclass 12, count 2 2006.173.15:09:15.91#ibcon#first serial, iclass 12, count 2 2006.173.15:09:15.91#ibcon#enter sib2, iclass 12, count 2 2006.173.15:09:15.91#ibcon#flushed, iclass 12, count 2 2006.173.15:09:15.91#ibcon#about to write, iclass 12, count 2 2006.173.15:09:15.91#ibcon#wrote, iclass 12, count 2 2006.173.15:09:15.91#ibcon#about to read 3, iclass 12, count 2 2006.173.15:09:15.93#ibcon#read 3, iclass 12, count 2 2006.173.15:09:15.93#ibcon#about to read 4, iclass 12, count 2 2006.173.15:09:15.93#ibcon#read 4, iclass 12, count 2 2006.173.15:09:15.93#ibcon#about to read 5, iclass 12, count 2 2006.173.15:09:15.93#ibcon#read 5, iclass 12, count 2 2006.173.15:09:15.93#ibcon#about to read 6, iclass 12, count 2 2006.173.15:09:15.93#ibcon#read 6, iclass 12, count 2 2006.173.15:09:15.93#ibcon#end of sib2, iclass 12, count 2 2006.173.15:09:15.93#ibcon#*mode == 0, iclass 12, count 2 2006.173.15:09:15.93#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.15:09:15.93#ibcon#[27=AT07-04\r\n] 2006.173.15:09:15.93#ibcon#*before write, iclass 12, count 2 2006.173.15:09:15.93#ibcon#enter sib2, iclass 12, count 2 2006.173.15:09:15.93#ibcon#flushed, iclass 12, count 2 2006.173.15:09:15.93#ibcon#about to write, iclass 12, count 2 2006.173.15:09:15.93#ibcon#wrote, iclass 12, count 2 2006.173.15:09:15.93#ibcon#about to read 3, iclass 12, count 2 2006.173.15:09:15.96#ibcon#read 3, iclass 12, count 2 2006.173.15:09:15.96#ibcon#about to read 4, iclass 12, count 2 2006.173.15:09:15.96#ibcon#read 4, iclass 12, count 2 2006.173.15:09:15.96#ibcon#about to read 5, iclass 12, count 2 2006.173.15:09:15.96#ibcon#read 5, iclass 12, count 2 2006.173.15:09:15.96#ibcon#about to read 6, iclass 12, count 2 2006.173.15:09:15.96#ibcon#read 6, iclass 12, count 2 2006.173.15:09:15.96#ibcon#end of sib2, iclass 12, count 2 2006.173.15:09:15.96#ibcon#*after write, iclass 12, count 2 2006.173.15:09:15.96#ibcon#*before return 0, iclass 12, count 2 2006.173.15:09:15.96#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.15:09:15.96#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.15:09:15.96#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.15:09:15.96#ibcon#ireg 7 cls_cnt 0 2006.173.15:09:15.96#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.15:09:16.08#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.15:09:16.08#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.15:09:16.08#ibcon#enter wrdev, iclass 12, count 0 2006.173.15:09:16.08#ibcon#first serial, iclass 12, count 0 2006.173.15:09:16.08#ibcon#enter sib2, iclass 12, count 0 2006.173.15:09:16.08#ibcon#flushed, iclass 12, count 0 2006.173.15:09:16.08#ibcon#about to write, iclass 12, count 0 2006.173.15:09:16.08#ibcon#wrote, iclass 12, count 0 2006.173.15:09:16.08#ibcon#about to read 3, iclass 12, count 0 2006.173.15:09:16.10#ibcon#read 3, iclass 12, count 0 2006.173.15:09:16.10#ibcon#about to read 4, iclass 12, count 0 2006.173.15:09:16.10#ibcon#read 4, iclass 12, count 0 2006.173.15:09:16.10#ibcon#about to read 5, iclass 12, count 0 2006.173.15:09:16.10#ibcon#read 5, iclass 12, count 0 2006.173.15:09:16.10#ibcon#about to read 6, iclass 12, count 0 2006.173.15:09:16.10#ibcon#read 6, iclass 12, count 0 2006.173.15:09:16.10#ibcon#end of sib2, iclass 12, count 0 2006.173.15:09:16.10#ibcon#*mode == 0, iclass 12, count 0 2006.173.15:09:16.10#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.15:09:16.10#ibcon#[27=USB\r\n] 2006.173.15:09:16.10#ibcon#*before write, iclass 12, count 0 2006.173.15:09:16.10#ibcon#enter sib2, iclass 12, count 0 2006.173.15:09:16.10#ibcon#flushed, iclass 12, count 0 2006.173.15:09:16.10#ibcon#about to write, iclass 12, count 0 2006.173.15:09:16.10#ibcon#wrote, iclass 12, count 0 2006.173.15:09:16.10#ibcon#about to read 3, iclass 12, count 0 2006.173.15:09:16.13#ibcon#read 3, iclass 12, count 0 2006.173.15:09:16.13#ibcon#about to read 4, iclass 12, count 0 2006.173.15:09:16.13#ibcon#read 4, iclass 12, count 0 2006.173.15:09:16.13#ibcon#about to read 5, iclass 12, count 0 2006.173.15:09:16.13#ibcon#read 5, iclass 12, count 0 2006.173.15:09:16.13#ibcon#about to read 6, iclass 12, count 0 2006.173.15:09:16.13#ibcon#read 6, iclass 12, count 0 2006.173.15:09:16.13#ibcon#end of sib2, iclass 12, count 0 2006.173.15:09:16.13#ibcon#*after write, iclass 12, count 0 2006.173.15:09:16.13#ibcon#*before return 0, iclass 12, count 0 2006.173.15:09:16.13#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.15:09:16.13#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.15:09:16.13#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.15:09:16.13#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.15:09:16.13$vck44/vblo=8,744.99 2006.173.15:09:16.13#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.15:09:16.13#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.15:09:16.13#ibcon#ireg 17 cls_cnt 0 2006.173.15:09:16.13#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.15:09:16.13#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.15:09:16.13#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.15:09:16.13#ibcon#enter wrdev, iclass 14, count 0 2006.173.15:09:16.13#ibcon#first serial, iclass 14, count 0 2006.173.15:09:16.13#ibcon#enter sib2, iclass 14, count 0 2006.173.15:09:16.13#ibcon#flushed, iclass 14, count 0 2006.173.15:09:16.13#ibcon#about to write, iclass 14, count 0 2006.173.15:09:16.13#ibcon#wrote, iclass 14, count 0 2006.173.15:09:16.13#ibcon#about to read 3, iclass 14, count 0 2006.173.15:09:16.15#ibcon#read 3, iclass 14, count 0 2006.173.15:09:16.15#ibcon#about to read 4, iclass 14, count 0 2006.173.15:09:16.15#ibcon#read 4, iclass 14, count 0 2006.173.15:09:16.15#ibcon#about to read 5, iclass 14, count 0 2006.173.15:09:16.15#ibcon#read 5, iclass 14, count 0 2006.173.15:09:16.15#ibcon#about to read 6, iclass 14, count 0 2006.173.15:09:16.15#ibcon#read 6, iclass 14, count 0 2006.173.15:09:16.15#ibcon#end of sib2, iclass 14, count 0 2006.173.15:09:16.15#ibcon#*mode == 0, iclass 14, count 0 2006.173.15:09:16.15#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.15:09:16.15#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.15:09:16.15#ibcon#*before write, iclass 14, count 0 2006.173.15:09:16.15#ibcon#enter sib2, iclass 14, count 0 2006.173.15:09:16.15#ibcon#flushed, iclass 14, count 0 2006.173.15:09:16.15#ibcon#about to write, iclass 14, count 0 2006.173.15:09:16.15#ibcon#wrote, iclass 14, count 0 2006.173.15:09:16.15#ibcon#about to read 3, iclass 14, count 0 2006.173.15:09:16.19#ibcon#read 3, iclass 14, count 0 2006.173.15:09:16.19#ibcon#about to read 4, iclass 14, count 0 2006.173.15:09:16.19#ibcon#read 4, iclass 14, count 0 2006.173.15:09:16.19#ibcon#about to read 5, iclass 14, count 0 2006.173.15:09:16.19#ibcon#read 5, iclass 14, count 0 2006.173.15:09:16.19#ibcon#about to read 6, iclass 14, count 0 2006.173.15:09:16.19#ibcon#read 6, iclass 14, count 0 2006.173.15:09:16.19#ibcon#end of sib2, iclass 14, count 0 2006.173.15:09:16.19#ibcon#*after write, iclass 14, count 0 2006.173.15:09:16.19#ibcon#*before return 0, iclass 14, count 0 2006.173.15:09:16.19#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.15:09:16.19#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.15:09:16.19#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.15:09:16.19#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.15:09:16.19$vck44/vb=8,4 2006.173.15:09:16.19#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.15:09:16.19#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.15:09:16.19#ibcon#ireg 11 cls_cnt 2 2006.173.15:09:16.19#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.15:09:16.25#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.15:09:16.25#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.15:09:16.25#ibcon#enter wrdev, iclass 16, count 2 2006.173.15:09:16.25#ibcon#first serial, iclass 16, count 2 2006.173.15:09:16.25#ibcon#enter sib2, iclass 16, count 2 2006.173.15:09:16.25#ibcon#flushed, iclass 16, count 2 2006.173.15:09:16.25#ibcon#about to write, iclass 16, count 2 2006.173.15:09:16.25#ibcon#wrote, iclass 16, count 2 2006.173.15:09:16.25#ibcon#about to read 3, iclass 16, count 2 2006.173.15:09:16.27#ibcon#read 3, iclass 16, count 2 2006.173.15:09:16.27#ibcon#about to read 4, iclass 16, count 2 2006.173.15:09:16.27#ibcon#read 4, iclass 16, count 2 2006.173.15:09:16.27#ibcon#about to read 5, iclass 16, count 2 2006.173.15:09:16.27#ibcon#read 5, iclass 16, count 2 2006.173.15:09:16.27#ibcon#about to read 6, iclass 16, count 2 2006.173.15:09:16.27#ibcon#read 6, iclass 16, count 2 2006.173.15:09:16.27#ibcon#end of sib2, iclass 16, count 2 2006.173.15:09:16.27#ibcon#*mode == 0, iclass 16, count 2 2006.173.15:09:16.27#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.15:09:16.27#ibcon#[27=AT08-04\r\n] 2006.173.15:09:16.27#ibcon#*before write, iclass 16, count 2 2006.173.15:09:16.27#ibcon#enter sib2, iclass 16, count 2 2006.173.15:09:16.27#ibcon#flushed, iclass 16, count 2 2006.173.15:09:16.27#ibcon#about to write, iclass 16, count 2 2006.173.15:09:16.27#ibcon#wrote, iclass 16, count 2 2006.173.15:09:16.27#ibcon#about to read 3, iclass 16, count 2 2006.173.15:09:16.30#ibcon#read 3, iclass 16, count 2 2006.173.15:09:16.30#ibcon#about to read 4, iclass 16, count 2 2006.173.15:09:16.30#ibcon#read 4, iclass 16, count 2 2006.173.15:09:16.30#ibcon#about to read 5, iclass 16, count 2 2006.173.15:09:16.30#ibcon#read 5, iclass 16, count 2 2006.173.15:09:16.30#ibcon#about to read 6, iclass 16, count 2 2006.173.15:09:16.30#ibcon#read 6, iclass 16, count 2 2006.173.15:09:16.30#ibcon#end of sib2, iclass 16, count 2 2006.173.15:09:16.30#ibcon#*after write, iclass 16, count 2 2006.173.15:09:16.30#ibcon#*before return 0, iclass 16, count 2 2006.173.15:09:16.30#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.15:09:16.30#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.15:09:16.30#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.15:09:16.30#ibcon#ireg 7 cls_cnt 0 2006.173.15:09:16.30#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.15:09:16.42#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.15:09:16.42#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.15:09:16.42#ibcon#enter wrdev, iclass 16, count 0 2006.173.15:09:16.42#ibcon#first serial, iclass 16, count 0 2006.173.15:09:16.42#ibcon#enter sib2, iclass 16, count 0 2006.173.15:09:16.42#ibcon#flushed, iclass 16, count 0 2006.173.15:09:16.42#ibcon#about to write, iclass 16, count 0 2006.173.15:09:16.42#ibcon#wrote, iclass 16, count 0 2006.173.15:09:16.42#ibcon#about to read 3, iclass 16, count 0 2006.173.15:09:16.44#ibcon#read 3, iclass 16, count 0 2006.173.15:09:16.44#ibcon#about to read 4, iclass 16, count 0 2006.173.15:09:16.44#ibcon#read 4, iclass 16, count 0 2006.173.15:09:16.44#ibcon#about to read 5, iclass 16, count 0 2006.173.15:09:16.44#ibcon#read 5, iclass 16, count 0 2006.173.15:09:16.44#ibcon#about to read 6, iclass 16, count 0 2006.173.15:09:16.44#ibcon#read 6, iclass 16, count 0 2006.173.15:09:16.44#ibcon#end of sib2, iclass 16, count 0 2006.173.15:09:16.44#ibcon#*mode == 0, iclass 16, count 0 2006.173.15:09:16.44#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.15:09:16.44#ibcon#[27=USB\r\n] 2006.173.15:09:16.44#ibcon#*before write, iclass 16, count 0 2006.173.15:09:16.44#ibcon#enter sib2, iclass 16, count 0 2006.173.15:09:16.44#ibcon#flushed, iclass 16, count 0 2006.173.15:09:16.44#ibcon#about to write, iclass 16, count 0 2006.173.15:09:16.44#ibcon#wrote, iclass 16, count 0 2006.173.15:09:16.44#ibcon#about to read 3, iclass 16, count 0 2006.173.15:09:16.47#ibcon#read 3, iclass 16, count 0 2006.173.15:09:16.47#ibcon#about to read 4, iclass 16, count 0 2006.173.15:09:16.47#ibcon#read 4, iclass 16, count 0 2006.173.15:09:16.47#ibcon#about to read 5, iclass 16, count 0 2006.173.15:09:16.47#ibcon#read 5, iclass 16, count 0 2006.173.15:09:16.47#ibcon#about to read 6, iclass 16, count 0 2006.173.15:09:16.47#ibcon#read 6, iclass 16, count 0 2006.173.15:09:16.47#ibcon#end of sib2, iclass 16, count 0 2006.173.15:09:16.47#ibcon#*after write, iclass 16, count 0 2006.173.15:09:16.47#ibcon#*before return 0, iclass 16, count 0 2006.173.15:09:16.47#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.15:09:16.47#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.15:09:16.47#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.15:09:16.47#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.15:09:16.47$vck44/vabw=wide 2006.173.15:09:16.47#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.15:09:16.47#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.15:09:16.47#ibcon#ireg 8 cls_cnt 0 2006.173.15:09:16.47#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.15:09:16.47#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.15:09:16.47#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.15:09:16.47#ibcon#enter wrdev, iclass 18, count 0 2006.173.15:09:16.47#ibcon#first serial, iclass 18, count 0 2006.173.15:09:16.47#ibcon#enter sib2, iclass 18, count 0 2006.173.15:09:16.47#ibcon#flushed, iclass 18, count 0 2006.173.15:09:16.47#ibcon#about to write, iclass 18, count 0 2006.173.15:09:16.47#ibcon#wrote, iclass 18, count 0 2006.173.15:09:16.47#ibcon#about to read 3, iclass 18, count 0 2006.173.15:09:16.49#ibcon#read 3, iclass 18, count 0 2006.173.15:09:16.49#ibcon#about to read 4, iclass 18, count 0 2006.173.15:09:16.49#ibcon#read 4, iclass 18, count 0 2006.173.15:09:16.49#ibcon#about to read 5, iclass 18, count 0 2006.173.15:09:16.49#ibcon#read 5, iclass 18, count 0 2006.173.15:09:16.49#ibcon#about to read 6, iclass 18, count 0 2006.173.15:09:16.49#ibcon#read 6, iclass 18, count 0 2006.173.15:09:16.49#ibcon#end of sib2, iclass 18, count 0 2006.173.15:09:16.49#ibcon#*mode == 0, iclass 18, count 0 2006.173.15:09:16.49#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.15:09:16.49#ibcon#[25=BW32\r\n] 2006.173.15:09:16.49#ibcon#*before write, iclass 18, count 0 2006.173.15:09:16.49#ibcon#enter sib2, iclass 18, count 0 2006.173.15:09:16.49#ibcon#flushed, iclass 18, count 0 2006.173.15:09:16.49#ibcon#about to write, iclass 18, count 0 2006.173.15:09:16.49#ibcon#wrote, iclass 18, count 0 2006.173.15:09:16.49#ibcon#about to read 3, iclass 18, count 0 2006.173.15:09:16.52#ibcon#read 3, iclass 18, count 0 2006.173.15:09:16.52#ibcon#about to read 4, iclass 18, count 0 2006.173.15:09:16.52#ibcon#read 4, iclass 18, count 0 2006.173.15:09:16.52#ibcon#about to read 5, iclass 18, count 0 2006.173.15:09:16.52#ibcon#read 5, iclass 18, count 0 2006.173.15:09:16.52#ibcon#about to read 6, iclass 18, count 0 2006.173.15:09:16.52#ibcon#read 6, iclass 18, count 0 2006.173.15:09:16.52#ibcon#end of sib2, iclass 18, count 0 2006.173.15:09:16.52#ibcon#*after write, iclass 18, count 0 2006.173.15:09:16.52#ibcon#*before return 0, iclass 18, count 0 2006.173.15:09:16.52#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.15:09:16.52#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.15:09:16.52#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.15:09:16.52#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.15:09:16.52$vck44/vbbw=wide 2006.173.15:09:16.52#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.15:09:16.52#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.15:09:16.52#ibcon#ireg 8 cls_cnt 0 2006.173.15:09:16.52#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.15:09:16.59#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.15:09:16.59#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.15:09:16.59#ibcon#enter wrdev, iclass 20, count 0 2006.173.15:09:16.59#ibcon#first serial, iclass 20, count 0 2006.173.15:09:16.59#ibcon#enter sib2, iclass 20, count 0 2006.173.15:09:16.59#ibcon#flushed, iclass 20, count 0 2006.173.15:09:16.59#ibcon#about to write, iclass 20, count 0 2006.173.15:09:16.59#ibcon#wrote, iclass 20, count 0 2006.173.15:09:16.59#ibcon#about to read 3, iclass 20, count 0 2006.173.15:09:16.61#ibcon#read 3, iclass 20, count 0 2006.173.15:09:16.61#ibcon#about to read 4, iclass 20, count 0 2006.173.15:09:16.61#ibcon#read 4, iclass 20, count 0 2006.173.15:09:16.61#ibcon#about to read 5, iclass 20, count 0 2006.173.15:09:16.61#ibcon#read 5, iclass 20, count 0 2006.173.15:09:16.61#ibcon#about to read 6, iclass 20, count 0 2006.173.15:09:16.61#ibcon#read 6, iclass 20, count 0 2006.173.15:09:16.61#ibcon#end of sib2, iclass 20, count 0 2006.173.15:09:16.61#ibcon#*mode == 0, iclass 20, count 0 2006.173.15:09:16.61#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.15:09:16.61#ibcon#[27=BW32\r\n] 2006.173.15:09:16.61#ibcon#*before write, iclass 20, count 0 2006.173.15:09:16.61#ibcon#enter sib2, iclass 20, count 0 2006.173.15:09:16.61#ibcon#flushed, iclass 20, count 0 2006.173.15:09:16.61#ibcon#about to write, iclass 20, count 0 2006.173.15:09:16.61#ibcon#wrote, iclass 20, count 0 2006.173.15:09:16.61#ibcon#about to read 3, iclass 20, count 0 2006.173.15:09:16.64#ibcon#read 3, iclass 20, count 0 2006.173.15:09:16.64#ibcon#about to read 4, iclass 20, count 0 2006.173.15:09:16.64#ibcon#read 4, iclass 20, count 0 2006.173.15:09:16.64#ibcon#about to read 5, iclass 20, count 0 2006.173.15:09:16.64#ibcon#read 5, iclass 20, count 0 2006.173.15:09:16.64#ibcon#about to read 6, iclass 20, count 0 2006.173.15:09:16.64#ibcon#read 6, iclass 20, count 0 2006.173.15:09:16.64#ibcon#end of sib2, iclass 20, count 0 2006.173.15:09:16.64#ibcon#*after write, iclass 20, count 0 2006.173.15:09:16.64#ibcon#*before return 0, iclass 20, count 0 2006.173.15:09:16.64#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.15:09:16.64#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.15:09:16.64#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.15:09:16.64#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.15:09:16.64$setupk4/ifdk4 2006.173.15:09:16.64$ifdk4/lo= 2006.173.15:09:16.64$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.15:09:16.64$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.15:09:16.64$ifdk4/patch= 2006.173.15:09:16.64$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.15:09:16.64$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.15:09:16.64$setupk4/!*+20s 2006.173.15:09:22.99#abcon#<5=/06 2.7 4.2 20.971001003.1\r\n> 2006.173.15:09:23.01#abcon#{5=INTERFACE CLEAR} 2006.173.15:09:23.07#abcon#[5=S1D000X0/0*\r\n] 2006.173.15:09:31.15$setupk4/"tpicd 2006.173.15:09:31.15$setupk4/echo=off 2006.173.15:09:31.15$setupk4/xlog=off 2006.173.15:09:31.15:!2006.173.15:09:54 2006.173.15:09:52.13#trakl#Source acquired 2006.173.15:09:54.00:preob 2006.173.15:09:54.13#flagr#flagr/antenna,acquired 2006.173.15:09:55.13/onsource/TRACKING 2006.173.15:09:55.13:!2006.173.15:10:04 2006.173.15:10:04.00:"tape 2006.173.15:10:04.00:"st=record 2006.173.15:10:04.00:data_valid=on 2006.173.15:10:04.00:midob 2006.173.15:10:04.13/onsource/TRACKING 2006.173.15:10:04.13/wx/20.99,1003.1,100 2006.173.15:10:04.28/cable/+6.5092E-03 2006.173.15:10:05.37/va/01,07,usb,yes,42,45 2006.173.15:10:05.37/va/02,06,usb,yes,41,42 2006.173.15:10:05.37/va/03,05,usb,yes,52,55 2006.173.15:10:05.37/va/04,06,usb,yes,42,45 2006.173.15:10:05.37/va/05,04,usb,yes,33,34 2006.173.15:10:05.37/va/06,03,usb,yes,46,46 2006.173.15:10:05.37/va/07,04,usb,yes,38,39 2006.173.15:10:05.37/va/08,04,usb,yes,32,39 2006.173.15:10:05.60/valo/01,524.99,yes,locked 2006.173.15:10:05.60/valo/02,534.99,yes,locked 2006.173.15:10:05.60/valo/03,564.99,yes,locked 2006.173.15:10:05.60/valo/04,624.99,yes,locked 2006.173.15:10:05.60/valo/05,734.99,yes,locked 2006.173.15:10:05.60/valo/06,814.99,yes,locked 2006.173.15:10:05.60/valo/07,864.99,yes,locked 2006.173.15:10:05.60/valo/08,884.99,yes,locked 2006.173.15:10:06.69/vb/01,04,usb,yes,30,28 2006.173.15:10:06.69/vb/02,04,usb,yes,33,33 2006.173.15:10:06.69/vb/03,04,usb,yes,30,33 2006.173.15:10:06.69/vb/04,04,usb,yes,34,33 2006.173.15:10:06.69/vb/05,04,usb,yes,27,29 2006.173.15:10:06.69/vb/06,04,usb,yes,31,27 2006.173.15:10:06.69/vb/07,04,usb,yes,31,31 2006.173.15:10:06.69/vb/08,04,usb,yes,29,32 2006.173.15:10:06.92/vblo/01,629.99,yes,locked 2006.173.15:10:06.92/vblo/02,634.99,yes,locked 2006.173.15:10:06.92/vblo/03,649.99,yes,locked 2006.173.15:10:06.92/vblo/04,679.99,yes,locked 2006.173.15:10:06.92/vblo/05,709.99,yes,locked 2006.173.15:10:06.92/vblo/06,719.99,yes,locked 2006.173.15:10:06.92/vblo/07,734.99,yes,locked 2006.173.15:10:06.92/vblo/08,744.99,yes,locked 2006.173.15:10:07.07/vabw/8 2006.173.15:10:07.22/vbbw/8 2006.173.15:10:07.31/xfe/off,on,14.7 2006.173.15:10:07.70/ifatt/23,28,28,28 2006.173.15:10:08.07/fmout-gps/S +4.02E-07 2006.173.15:10:08.11:!2006.173.15:10:44 2006.173.15:10:44.00:data_valid=off 2006.173.15:10:44.00:"et 2006.173.15:10:44.00:!+3s 2006.173.15:10:47.01:"tape 2006.173.15:10:47.01:postob 2006.173.15:10:47.12/cable/+6.5080E-03 2006.173.15:10:47.12/wx/20.99,1003.1,100 2006.173.15:10:48.07/fmout-gps/S +4.02E-07 2006.173.15:10:48.07:scan_name=173-1515,jd0606,710 2006.173.15:10:48.07:source=1749+096,175132.82,093900.7,2000.0,cw 2006.173.15:10:49.13#flagr#flagr/antenna,new-source 2006.173.15:10:49.13:checkk5 2006.173.15:10:49.49/chk_autoobs//k5ts1/ autoobs is running! 2006.173.15:10:49.89/chk_autoobs//k5ts2/ autoobs is running! 2006.173.15:10:50.31/chk_autoobs//k5ts3/ autoobs is running! 2006.173.15:10:50.71/chk_autoobs//k5ts4/ autoobs is running! 2006.173.15:10:51.09/chk_obsdata//k5ts1/T1731510??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.15:10:51.48/chk_obsdata//k5ts2/T1731510??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.15:10:51.86/chk_obsdata//k5ts3/T1731510??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.15:10:52.27/chk_obsdata//k5ts4/T1731510??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.15:10:52.99/k5log//k5ts1_log_newline 2006.173.15:10:53.70/k5log//k5ts2_log_newline 2006.173.15:10:54.41/k5log//k5ts3_log_newline 2006.173.15:10:55.11/k5log//k5ts4_log_newline 2006.173.15:10:55.13/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.15:10:55.13:setupk4=1 2006.173.15:10:55.13$setupk4/echo=on 2006.173.15:10:55.13$setupk4/pcalon 2006.173.15:10:55.13$pcalon/"no phase cal control is implemented here 2006.173.15:10:55.13$setupk4/"tpicd=stop 2006.173.15:10:55.13$setupk4/"rec=synch_on 2006.173.15:10:55.13$setupk4/"rec_mode=128 2006.173.15:10:55.14$setupk4/!* 2006.173.15:10:55.14$setupk4/recpk4 2006.173.15:10:55.14$recpk4/recpatch= 2006.173.15:10:55.14$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.15:10:55.14$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.15:10:55.14$setupk4/vck44 2006.173.15:10:55.14$vck44/valo=1,524.99 2006.173.15:10:55.14#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.15:10:55.14#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.15:10:55.14#ibcon#ireg 17 cls_cnt 0 2006.173.15:10:55.14#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.15:10:55.14#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.15:10:55.14#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.15:10:55.14#ibcon#enter wrdev, iclass 29, count 0 2006.173.15:10:55.14#ibcon#first serial, iclass 29, count 0 2006.173.15:10:55.14#ibcon#enter sib2, iclass 29, count 0 2006.173.15:10:55.14#ibcon#flushed, iclass 29, count 0 2006.173.15:10:55.14#ibcon#about to write, iclass 29, count 0 2006.173.15:10:55.14#ibcon#wrote, iclass 29, count 0 2006.173.15:10:55.14#ibcon#about to read 3, iclass 29, count 0 2006.173.15:10:55.16#ibcon#read 3, iclass 29, count 0 2006.173.15:10:55.16#ibcon#about to read 4, iclass 29, count 0 2006.173.15:10:55.16#ibcon#read 4, iclass 29, count 0 2006.173.15:10:55.16#ibcon#about to read 5, iclass 29, count 0 2006.173.15:10:55.16#ibcon#read 5, iclass 29, count 0 2006.173.15:10:55.16#ibcon#about to read 6, iclass 29, count 0 2006.173.15:10:55.16#ibcon#read 6, iclass 29, count 0 2006.173.15:10:55.16#ibcon#end of sib2, iclass 29, count 0 2006.173.15:10:55.16#ibcon#*mode == 0, iclass 29, count 0 2006.173.15:10:55.16#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.15:10:55.16#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.15:10:55.16#ibcon#*before write, iclass 29, count 0 2006.173.15:10:55.16#ibcon#enter sib2, iclass 29, count 0 2006.173.15:10:55.16#ibcon#flushed, iclass 29, count 0 2006.173.15:10:55.16#ibcon#about to write, iclass 29, count 0 2006.173.15:10:55.16#ibcon#wrote, iclass 29, count 0 2006.173.15:10:55.16#ibcon#about to read 3, iclass 29, count 0 2006.173.15:10:55.21#ibcon#read 3, iclass 29, count 0 2006.173.15:10:55.21#ibcon#about to read 4, iclass 29, count 0 2006.173.15:10:55.21#ibcon#read 4, iclass 29, count 0 2006.173.15:10:55.21#ibcon#about to read 5, iclass 29, count 0 2006.173.15:10:55.21#ibcon#read 5, iclass 29, count 0 2006.173.15:10:55.21#ibcon#about to read 6, iclass 29, count 0 2006.173.15:10:55.21#ibcon#read 6, iclass 29, count 0 2006.173.15:10:55.21#ibcon#end of sib2, iclass 29, count 0 2006.173.15:10:55.21#ibcon#*after write, iclass 29, count 0 2006.173.15:10:55.21#ibcon#*before return 0, iclass 29, count 0 2006.173.15:10:55.21#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.15:10:55.21#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.15:10:55.21#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.15:10:55.21#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.15:10:55.21$vck44/va=1,7 2006.173.15:10:55.21#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.15:10:55.21#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.15:10:55.21#ibcon#ireg 11 cls_cnt 2 2006.173.15:10:55.21#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.15:10:55.21#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.15:10:55.21#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.15:10:55.21#ibcon#enter wrdev, iclass 31, count 2 2006.173.15:10:55.21#ibcon#first serial, iclass 31, count 2 2006.173.15:10:55.21#ibcon#enter sib2, iclass 31, count 2 2006.173.15:10:55.21#ibcon#flushed, iclass 31, count 2 2006.173.15:10:55.21#ibcon#about to write, iclass 31, count 2 2006.173.15:10:55.21#ibcon#wrote, iclass 31, count 2 2006.173.15:10:55.21#ibcon#about to read 3, iclass 31, count 2 2006.173.15:10:55.23#ibcon#read 3, iclass 31, count 2 2006.173.15:10:55.23#ibcon#about to read 4, iclass 31, count 2 2006.173.15:10:55.23#ibcon#read 4, iclass 31, count 2 2006.173.15:10:55.23#ibcon#about to read 5, iclass 31, count 2 2006.173.15:10:55.23#ibcon#read 5, iclass 31, count 2 2006.173.15:10:55.23#ibcon#about to read 6, iclass 31, count 2 2006.173.15:10:55.23#ibcon#read 6, iclass 31, count 2 2006.173.15:10:55.23#ibcon#end of sib2, iclass 31, count 2 2006.173.15:10:55.23#ibcon#*mode == 0, iclass 31, count 2 2006.173.15:10:55.23#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.15:10:55.23#ibcon#[25=AT01-07\r\n] 2006.173.15:10:55.23#ibcon#*before write, iclass 31, count 2 2006.173.15:10:55.23#ibcon#enter sib2, iclass 31, count 2 2006.173.15:10:55.23#ibcon#flushed, iclass 31, count 2 2006.173.15:10:55.23#ibcon#about to write, iclass 31, count 2 2006.173.15:10:55.23#ibcon#wrote, iclass 31, count 2 2006.173.15:10:55.23#ibcon#about to read 3, iclass 31, count 2 2006.173.15:10:55.26#ibcon#read 3, iclass 31, count 2 2006.173.15:10:55.26#ibcon#about to read 4, iclass 31, count 2 2006.173.15:10:55.26#ibcon#read 4, iclass 31, count 2 2006.173.15:10:55.26#ibcon#about to read 5, iclass 31, count 2 2006.173.15:10:55.26#ibcon#read 5, iclass 31, count 2 2006.173.15:10:55.26#ibcon#about to read 6, iclass 31, count 2 2006.173.15:10:55.26#ibcon#read 6, iclass 31, count 2 2006.173.15:10:55.26#ibcon#end of sib2, iclass 31, count 2 2006.173.15:10:55.26#ibcon#*after write, iclass 31, count 2 2006.173.15:10:55.26#ibcon#*before return 0, iclass 31, count 2 2006.173.15:10:55.26#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.15:10:55.26#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.15:10:55.26#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.15:10:55.26#ibcon#ireg 7 cls_cnt 0 2006.173.15:10:55.26#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.15:10:55.38#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.15:10:55.38#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.15:10:55.38#ibcon#enter wrdev, iclass 31, count 0 2006.173.15:10:55.38#ibcon#first serial, iclass 31, count 0 2006.173.15:10:55.38#ibcon#enter sib2, iclass 31, count 0 2006.173.15:10:55.38#ibcon#flushed, iclass 31, count 0 2006.173.15:10:55.38#ibcon#about to write, iclass 31, count 0 2006.173.15:10:55.38#ibcon#wrote, iclass 31, count 0 2006.173.15:10:55.38#ibcon#about to read 3, iclass 31, count 0 2006.173.15:10:55.40#ibcon#read 3, iclass 31, count 0 2006.173.15:10:55.40#ibcon#about to read 4, iclass 31, count 0 2006.173.15:10:55.40#ibcon#read 4, iclass 31, count 0 2006.173.15:10:55.40#ibcon#about to read 5, iclass 31, count 0 2006.173.15:10:55.40#ibcon#read 5, iclass 31, count 0 2006.173.15:10:55.40#ibcon#about to read 6, iclass 31, count 0 2006.173.15:10:55.40#ibcon#read 6, iclass 31, count 0 2006.173.15:10:55.40#ibcon#end of sib2, iclass 31, count 0 2006.173.15:10:55.40#ibcon#*mode == 0, iclass 31, count 0 2006.173.15:10:55.40#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.15:10:55.40#ibcon#[25=USB\r\n] 2006.173.15:10:55.40#ibcon#*before write, iclass 31, count 0 2006.173.15:10:55.40#ibcon#enter sib2, iclass 31, count 0 2006.173.15:10:55.40#ibcon#flushed, iclass 31, count 0 2006.173.15:10:55.40#ibcon#about to write, iclass 31, count 0 2006.173.15:10:55.40#ibcon#wrote, iclass 31, count 0 2006.173.15:10:55.40#ibcon#about to read 3, iclass 31, count 0 2006.173.15:10:55.43#ibcon#read 3, iclass 31, count 0 2006.173.15:10:55.43#ibcon#about to read 4, iclass 31, count 0 2006.173.15:10:55.43#ibcon#read 4, iclass 31, count 0 2006.173.15:10:55.43#ibcon#about to read 5, iclass 31, count 0 2006.173.15:10:55.43#ibcon#read 5, iclass 31, count 0 2006.173.15:10:55.43#ibcon#about to read 6, iclass 31, count 0 2006.173.15:10:55.43#ibcon#read 6, iclass 31, count 0 2006.173.15:10:55.43#ibcon#end of sib2, iclass 31, count 0 2006.173.15:10:55.43#ibcon#*after write, iclass 31, count 0 2006.173.15:10:55.43#ibcon#*before return 0, iclass 31, count 0 2006.173.15:10:55.43#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.15:10:55.43#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.15:10:55.43#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.15:10:55.43#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.15:10:55.43$vck44/valo=2,534.99 2006.173.15:10:55.43#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.15:10:55.43#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.15:10:55.43#ibcon#ireg 17 cls_cnt 0 2006.173.15:10:55.43#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.15:10:55.43#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.15:10:55.43#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.15:10:55.43#ibcon#enter wrdev, iclass 33, count 0 2006.173.15:10:55.43#ibcon#first serial, iclass 33, count 0 2006.173.15:10:55.43#ibcon#enter sib2, iclass 33, count 0 2006.173.15:10:55.43#ibcon#flushed, iclass 33, count 0 2006.173.15:10:55.43#ibcon#about to write, iclass 33, count 0 2006.173.15:10:55.43#ibcon#wrote, iclass 33, count 0 2006.173.15:10:55.43#ibcon#about to read 3, iclass 33, count 0 2006.173.15:10:55.45#ibcon#read 3, iclass 33, count 0 2006.173.15:10:55.45#ibcon#about to read 4, iclass 33, count 0 2006.173.15:10:55.45#ibcon#read 4, iclass 33, count 0 2006.173.15:10:55.45#ibcon#about to read 5, iclass 33, count 0 2006.173.15:10:55.45#ibcon#read 5, iclass 33, count 0 2006.173.15:10:55.45#ibcon#about to read 6, iclass 33, count 0 2006.173.15:10:55.45#ibcon#read 6, iclass 33, count 0 2006.173.15:10:55.45#ibcon#end of sib2, iclass 33, count 0 2006.173.15:10:55.45#ibcon#*mode == 0, iclass 33, count 0 2006.173.15:10:55.45#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.15:10:55.45#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.15:10:55.45#ibcon#*before write, iclass 33, count 0 2006.173.15:10:55.45#ibcon#enter sib2, iclass 33, count 0 2006.173.15:10:55.45#ibcon#flushed, iclass 33, count 0 2006.173.15:10:55.45#ibcon#about to write, iclass 33, count 0 2006.173.15:10:55.45#ibcon#wrote, iclass 33, count 0 2006.173.15:10:55.45#ibcon#about to read 3, iclass 33, count 0 2006.173.15:10:55.49#ibcon#read 3, iclass 33, count 0 2006.173.15:10:55.49#ibcon#about to read 4, iclass 33, count 0 2006.173.15:10:55.49#ibcon#read 4, iclass 33, count 0 2006.173.15:10:55.49#ibcon#about to read 5, iclass 33, count 0 2006.173.15:10:55.49#ibcon#read 5, iclass 33, count 0 2006.173.15:10:55.49#ibcon#about to read 6, iclass 33, count 0 2006.173.15:10:55.49#ibcon#read 6, iclass 33, count 0 2006.173.15:10:55.49#ibcon#end of sib2, iclass 33, count 0 2006.173.15:10:55.49#ibcon#*after write, iclass 33, count 0 2006.173.15:10:55.49#ibcon#*before return 0, iclass 33, count 0 2006.173.15:10:55.49#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.15:10:55.49#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.15:10:55.49#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.15:10:55.49#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.15:10:55.49$vck44/va=2,6 2006.173.15:10:55.49#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.15:10:55.49#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.15:10:55.49#ibcon#ireg 11 cls_cnt 2 2006.173.15:10:55.49#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.15:10:55.55#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.15:10:55.55#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.15:10:55.55#ibcon#enter wrdev, iclass 35, count 2 2006.173.15:10:55.55#ibcon#first serial, iclass 35, count 2 2006.173.15:10:55.55#ibcon#enter sib2, iclass 35, count 2 2006.173.15:10:55.55#ibcon#flushed, iclass 35, count 2 2006.173.15:10:55.55#ibcon#about to write, iclass 35, count 2 2006.173.15:10:55.55#ibcon#wrote, iclass 35, count 2 2006.173.15:10:55.55#ibcon#about to read 3, iclass 35, count 2 2006.173.15:10:55.57#ibcon#read 3, iclass 35, count 2 2006.173.15:10:55.57#ibcon#about to read 4, iclass 35, count 2 2006.173.15:10:55.57#ibcon#read 4, iclass 35, count 2 2006.173.15:10:55.57#ibcon#about to read 5, iclass 35, count 2 2006.173.15:10:55.57#ibcon#read 5, iclass 35, count 2 2006.173.15:10:55.57#ibcon#about to read 6, iclass 35, count 2 2006.173.15:10:55.57#ibcon#read 6, iclass 35, count 2 2006.173.15:10:55.57#ibcon#end of sib2, iclass 35, count 2 2006.173.15:10:55.57#ibcon#*mode == 0, iclass 35, count 2 2006.173.15:10:55.57#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.15:10:55.57#ibcon#[25=AT02-06\r\n] 2006.173.15:10:55.57#ibcon#*before write, iclass 35, count 2 2006.173.15:10:55.57#ibcon#enter sib2, iclass 35, count 2 2006.173.15:10:55.57#ibcon#flushed, iclass 35, count 2 2006.173.15:10:55.57#ibcon#about to write, iclass 35, count 2 2006.173.15:10:55.57#ibcon#wrote, iclass 35, count 2 2006.173.15:10:55.57#ibcon#about to read 3, iclass 35, count 2 2006.173.15:10:55.60#ibcon#read 3, iclass 35, count 2 2006.173.15:10:55.60#ibcon#about to read 4, iclass 35, count 2 2006.173.15:10:55.60#ibcon#read 4, iclass 35, count 2 2006.173.15:10:55.60#ibcon#about to read 5, iclass 35, count 2 2006.173.15:10:55.60#ibcon#read 5, iclass 35, count 2 2006.173.15:10:55.60#ibcon#about to read 6, iclass 35, count 2 2006.173.15:10:55.60#ibcon#read 6, iclass 35, count 2 2006.173.15:10:55.60#ibcon#end of sib2, iclass 35, count 2 2006.173.15:10:55.60#ibcon#*after write, iclass 35, count 2 2006.173.15:10:55.60#ibcon#*before return 0, iclass 35, count 2 2006.173.15:10:55.60#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.15:10:55.60#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.15:10:55.60#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.15:10:55.60#ibcon#ireg 7 cls_cnt 0 2006.173.15:10:55.60#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.15:10:55.72#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.15:10:55.72#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.15:10:55.72#ibcon#enter wrdev, iclass 35, count 0 2006.173.15:10:55.72#ibcon#first serial, iclass 35, count 0 2006.173.15:10:55.72#ibcon#enter sib2, iclass 35, count 0 2006.173.15:10:55.72#ibcon#flushed, iclass 35, count 0 2006.173.15:10:55.72#ibcon#about to write, iclass 35, count 0 2006.173.15:10:55.72#ibcon#wrote, iclass 35, count 0 2006.173.15:10:55.72#ibcon#about to read 3, iclass 35, count 0 2006.173.15:10:55.74#ibcon#read 3, iclass 35, count 0 2006.173.15:10:55.74#ibcon#about to read 4, iclass 35, count 0 2006.173.15:10:55.74#ibcon#read 4, iclass 35, count 0 2006.173.15:10:55.74#ibcon#about to read 5, iclass 35, count 0 2006.173.15:10:55.74#ibcon#read 5, iclass 35, count 0 2006.173.15:10:55.74#ibcon#about to read 6, iclass 35, count 0 2006.173.15:10:55.74#ibcon#read 6, iclass 35, count 0 2006.173.15:10:55.74#ibcon#end of sib2, iclass 35, count 0 2006.173.15:10:55.74#ibcon#*mode == 0, iclass 35, count 0 2006.173.15:10:55.74#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.15:10:55.74#ibcon#[25=USB\r\n] 2006.173.15:10:55.74#ibcon#*before write, iclass 35, count 0 2006.173.15:10:55.74#ibcon#enter sib2, iclass 35, count 0 2006.173.15:10:55.74#ibcon#flushed, iclass 35, count 0 2006.173.15:10:55.74#ibcon#about to write, iclass 35, count 0 2006.173.15:10:55.74#ibcon#wrote, iclass 35, count 0 2006.173.15:10:55.74#ibcon#about to read 3, iclass 35, count 0 2006.173.15:10:55.77#ibcon#read 3, iclass 35, count 0 2006.173.15:10:55.77#ibcon#about to read 4, iclass 35, count 0 2006.173.15:10:55.77#ibcon#read 4, iclass 35, count 0 2006.173.15:10:55.77#ibcon#about to read 5, iclass 35, count 0 2006.173.15:10:55.77#ibcon#read 5, iclass 35, count 0 2006.173.15:10:55.77#ibcon#about to read 6, iclass 35, count 0 2006.173.15:10:55.77#ibcon#read 6, iclass 35, count 0 2006.173.15:10:55.77#ibcon#end of sib2, iclass 35, count 0 2006.173.15:10:55.77#ibcon#*after write, iclass 35, count 0 2006.173.15:10:55.77#ibcon#*before return 0, iclass 35, count 0 2006.173.15:10:55.77#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.15:10:55.77#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.15:10:55.77#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.15:10:55.77#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.15:10:55.77$vck44/valo=3,564.99 2006.173.15:10:55.77#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.15:10:55.77#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.15:10:55.77#ibcon#ireg 17 cls_cnt 0 2006.173.15:10:55.77#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.15:10:55.77#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.15:10:55.77#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.15:10:55.77#ibcon#enter wrdev, iclass 37, count 0 2006.173.15:10:55.77#ibcon#first serial, iclass 37, count 0 2006.173.15:10:55.77#ibcon#enter sib2, iclass 37, count 0 2006.173.15:10:55.77#ibcon#flushed, iclass 37, count 0 2006.173.15:10:55.77#ibcon#about to write, iclass 37, count 0 2006.173.15:10:55.77#ibcon#wrote, iclass 37, count 0 2006.173.15:10:55.77#ibcon#about to read 3, iclass 37, count 0 2006.173.15:10:55.79#ibcon#read 3, iclass 37, count 0 2006.173.15:10:55.79#ibcon#about to read 4, iclass 37, count 0 2006.173.15:10:55.79#ibcon#read 4, iclass 37, count 0 2006.173.15:10:55.79#ibcon#about to read 5, iclass 37, count 0 2006.173.15:10:55.79#ibcon#read 5, iclass 37, count 0 2006.173.15:10:55.79#ibcon#about to read 6, iclass 37, count 0 2006.173.15:10:55.79#ibcon#read 6, iclass 37, count 0 2006.173.15:10:55.79#ibcon#end of sib2, iclass 37, count 0 2006.173.15:10:55.79#ibcon#*mode == 0, iclass 37, count 0 2006.173.15:10:55.79#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.15:10:55.79#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.15:10:55.79#ibcon#*before write, iclass 37, count 0 2006.173.15:10:55.79#ibcon#enter sib2, iclass 37, count 0 2006.173.15:10:55.79#ibcon#flushed, iclass 37, count 0 2006.173.15:10:55.79#ibcon#about to write, iclass 37, count 0 2006.173.15:10:55.79#ibcon#wrote, iclass 37, count 0 2006.173.15:10:55.79#ibcon#about to read 3, iclass 37, count 0 2006.173.15:10:55.83#ibcon#read 3, iclass 37, count 0 2006.173.15:10:55.83#ibcon#about to read 4, iclass 37, count 0 2006.173.15:10:55.83#ibcon#read 4, iclass 37, count 0 2006.173.15:10:55.83#ibcon#about to read 5, iclass 37, count 0 2006.173.15:10:55.83#ibcon#read 5, iclass 37, count 0 2006.173.15:10:55.83#ibcon#about to read 6, iclass 37, count 0 2006.173.15:10:55.83#ibcon#read 6, iclass 37, count 0 2006.173.15:10:55.83#ibcon#end of sib2, iclass 37, count 0 2006.173.15:10:55.83#ibcon#*after write, iclass 37, count 0 2006.173.15:10:55.83#ibcon#*before return 0, iclass 37, count 0 2006.173.15:10:55.83#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.15:10:55.83#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.15:10:55.83#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.15:10:55.83#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.15:10:55.83$vck44/va=3,5 2006.173.15:10:55.83#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.15:10:55.83#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.15:10:55.83#ibcon#ireg 11 cls_cnt 2 2006.173.15:10:55.83#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.15:10:55.89#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.15:10:55.89#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.15:10:55.89#ibcon#enter wrdev, iclass 39, count 2 2006.173.15:10:55.89#ibcon#first serial, iclass 39, count 2 2006.173.15:10:55.89#ibcon#enter sib2, iclass 39, count 2 2006.173.15:10:55.89#ibcon#flushed, iclass 39, count 2 2006.173.15:10:55.89#ibcon#about to write, iclass 39, count 2 2006.173.15:10:55.89#ibcon#wrote, iclass 39, count 2 2006.173.15:10:55.89#ibcon#about to read 3, iclass 39, count 2 2006.173.15:10:55.91#ibcon#read 3, iclass 39, count 2 2006.173.15:10:55.91#ibcon#about to read 4, iclass 39, count 2 2006.173.15:10:55.91#ibcon#read 4, iclass 39, count 2 2006.173.15:10:55.91#ibcon#about to read 5, iclass 39, count 2 2006.173.15:10:55.91#ibcon#read 5, iclass 39, count 2 2006.173.15:10:55.91#ibcon#about to read 6, iclass 39, count 2 2006.173.15:10:55.91#ibcon#read 6, iclass 39, count 2 2006.173.15:10:55.91#ibcon#end of sib2, iclass 39, count 2 2006.173.15:10:55.91#ibcon#*mode == 0, iclass 39, count 2 2006.173.15:10:55.91#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.15:10:55.91#ibcon#[25=AT03-05\r\n] 2006.173.15:10:55.91#ibcon#*before write, iclass 39, count 2 2006.173.15:10:55.91#ibcon#enter sib2, iclass 39, count 2 2006.173.15:10:55.91#ibcon#flushed, iclass 39, count 2 2006.173.15:10:55.91#ibcon#about to write, iclass 39, count 2 2006.173.15:10:55.91#ibcon#wrote, iclass 39, count 2 2006.173.15:10:55.91#ibcon#about to read 3, iclass 39, count 2 2006.173.15:10:55.94#ibcon#read 3, iclass 39, count 2 2006.173.15:10:55.94#ibcon#about to read 4, iclass 39, count 2 2006.173.15:10:55.94#ibcon#read 4, iclass 39, count 2 2006.173.15:10:55.94#ibcon#about to read 5, iclass 39, count 2 2006.173.15:10:55.94#ibcon#read 5, iclass 39, count 2 2006.173.15:10:55.94#ibcon#about to read 6, iclass 39, count 2 2006.173.15:10:55.94#ibcon#read 6, iclass 39, count 2 2006.173.15:10:55.94#ibcon#end of sib2, iclass 39, count 2 2006.173.15:10:55.94#ibcon#*after write, iclass 39, count 2 2006.173.15:10:55.94#ibcon#*before return 0, iclass 39, count 2 2006.173.15:10:55.94#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.15:10:55.94#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.15:10:55.94#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.15:10:55.94#ibcon#ireg 7 cls_cnt 0 2006.173.15:10:55.94#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.15:10:56.06#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.15:10:56.06#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.15:10:56.06#ibcon#enter wrdev, iclass 39, count 0 2006.173.15:10:56.06#ibcon#first serial, iclass 39, count 0 2006.173.15:10:56.06#ibcon#enter sib2, iclass 39, count 0 2006.173.15:10:56.06#ibcon#flushed, iclass 39, count 0 2006.173.15:10:56.06#ibcon#about to write, iclass 39, count 0 2006.173.15:10:56.06#ibcon#wrote, iclass 39, count 0 2006.173.15:10:56.06#ibcon#about to read 3, iclass 39, count 0 2006.173.15:10:56.08#ibcon#read 3, iclass 39, count 0 2006.173.15:10:56.08#ibcon#about to read 4, iclass 39, count 0 2006.173.15:10:56.08#ibcon#read 4, iclass 39, count 0 2006.173.15:10:56.08#ibcon#about to read 5, iclass 39, count 0 2006.173.15:10:56.08#ibcon#read 5, iclass 39, count 0 2006.173.15:10:56.08#ibcon#about to read 6, iclass 39, count 0 2006.173.15:10:56.08#ibcon#read 6, iclass 39, count 0 2006.173.15:10:56.08#ibcon#end of sib2, iclass 39, count 0 2006.173.15:10:56.08#ibcon#*mode == 0, iclass 39, count 0 2006.173.15:10:56.08#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.15:10:56.08#ibcon#[25=USB\r\n] 2006.173.15:10:56.08#ibcon#*before write, iclass 39, count 0 2006.173.15:10:56.08#ibcon#enter sib2, iclass 39, count 0 2006.173.15:10:56.08#ibcon#flushed, iclass 39, count 0 2006.173.15:10:56.08#ibcon#about to write, iclass 39, count 0 2006.173.15:10:56.08#ibcon#wrote, iclass 39, count 0 2006.173.15:10:56.08#ibcon#about to read 3, iclass 39, count 0 2006.173.15:10:56.11#ibcon#read 3, iclass 39, count 0 2006.173.15:10:56.11#ibcon#about to read 4, iclass 39, count 0 2006.173.15:10:56.11#ibcon#read 4, iclass 39, count 0 2006.173.15:10:56.11#ibcon#about to read 5, iclass 39, count 0 2006.173.15:10:56.11#ibcon#read 5, iclass 39, count 0 2006.173.15:10:56.11#ibcon#about to read 6, iclass 39, count 0 2006.173.15:10:56.11#ibcon#read 6, iclass 39, count 0 2006.173.15:10:56.11#ibcon#end of sib2, iclass 39, count 0 2006.173.15:10:56.11#ibcon#*after write, iclass 39, count 0 2006.173.15:10:56.11#ibcon#*before return 0, iclass 39, count 0 2006.173.15:10:56.11#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.15:10:56.11#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.15:10:56.11#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.15:10:56.11#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.15:10:56.11$vck44/valo=4,624.99 2006.173.15:10:56.11#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.15:10:56.11#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.15:10:56.11#ibcon#ireg 17 cls_cnt 0 2006.173.15:10:56.11#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.15:10:56.11#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.15:10:56.11#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.15:10:56.11#ibcon#enter wrdev, iclass 3, count 0 2006.173.15:10:56.11#ibcon#first serial, iclass 3, count 0 2006.173.15:10:56.11#ibcon#enter sib2, iclass 3, count 0 2006.173.15:10:56.11#ibcon#flushed, iclass 3, count 0 2006.173.15:10:56.11#ibcon#about to write, iclass 3, count 0 2006.173.15:10:56.11#ibcon#wrote, iclass 3, count 0 2006.173.15:10:56.11#ibcon#about to read 3, iclass 3, count 0 2006.173.15:10:56.13#ibcon#read 3, iclass 3, count 0 2006.173.15:10:56.13#ibcon#about to read 4, iclass 3, count 0 2006.173.15:10:56.13#ibcon#read 4, iclass 3, count 0 2006.173.15:10:56.13#ibcon#about to read 5, iclass 3, count 0 2006.173.15:10:56.13#ibcon#read 5, iclass 3, count 0 2006.173.15:10:56.13#ibcon#about to read 6, iclass 3, count 0 2006.173.15:10:56.13#ibcon#read 6, iclass 3, count 0 2006.173.15:10:56.13#ibcon#end of sib2, iclass 3, count 0 2006.173.15:10:56.13#ibcon#*mode == 0, iclass 3, count 0 2006.173.15:10:56.13#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.15:10:56.13#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.15:10:56.13#ibcon#*before write, iclass 3, count 0 2006.173.15:10:56.13#ibcon#enter sib2, iclass 3, count 0 2006.173.15:10:56.13#ibcon#flushed, iclass 3, count 0 2006.173.15:10:56.13#ibcon#about to write, iclass 3, count 0 2006.173.15:10:56.13#ibcon#wrote, iclass 3, count 0 2006.173.15:10:56.13#ibcon#about to read 3, iclass 3, count 0 2006.173.15:10:56.17#ibcon#read 3, iclass 3, count 0 2006.173.15:10:56.17#ibcon#about to read 4, iclass 3, count 0 2006.173.15:10:56.17#ibcon#read 4, iclass 3, count 0 2006.173.15:10:56.17#ibcon#about to read 5, iclass 3, count 0 2006.173.15:10:56.17#ibcon#read 5, iclass 3, count 0 2006.173.15:10:56.17#ibcon#about to read 6, iclass 3, count 0 2006.173.15:10:56.17#ibcon#read 6, iclass 3, count 0 2006.173.15:10:56.17#ibcon#end of sib2, iclass 3, count 0 2006.173.15:10:56.17#ibcon#*after write, iclass 3, count 0 2006.173.15:10:56.17#ibcon#*before return 0, iclass 3, count 0 2006.173.15:10:56.17#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.15:10:56.17#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.15:10:56.17#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.15:10:56.17#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.15:10:56.17$vck44/va=4,6 2006.173.15:10:56.17#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.15:10:56.17#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.15:10:56.17#ibcon#ireg 11 cls_cnt 2 2006.173.15:10:56.17#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.15:10:56.23#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.15:10:56.23#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.15:10:56.23#ibcon#enter wrdev, iclass 5, count 2 2006.173.15:10:56.23#ibcon#first serial, iclass 5, count 2 2006.173.15:10:56.23#ibcon#enter sib2, iclass 5, count 2 2006.173.15:10:56.23#ibcon#flushed, iclass 5, count 2 2006.173.15:10:56.23#ibcon#about to write, iclass 5, count 2 2006.173.15:10:56.23#ibcon#wrote, iclass 5, count 2 2006.173.15:10:56.23#ibcon#about to read 3, iclass 5, count 2 2006.173.15:10:56.25#ibcon#read 3, iclass 5, count 2 2006.173.15:10:56.25#ibcon#about to read 4, iclass 5, count 2 2006.173.15:10:56.25#ibcon#read 4, iclass 5, count 2 2006.173.15:10:56.25#ibcon#about to read 5, iclass 5, count 2 2006.173.15:10:56.25#ibcon#read 5, iclass 5, count 2 2006.173.15:10:56.25#ibcon#about to read 6, iclass 5, count 2 2006.173.15:10:56.25#ibcon#read 6, iclass 5, count 2 2006.173.15:10:56.25#ibcon#end of sib2, iclass 5, count 2 2006.173.15:10:56.25#ibcon#*mode == 0, iclass 5, count 2 2006.173.15:10:56.25#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.15:10:56.25#ibcon#[25=AT04-06\r\n] 2006.173.15:10:56.25#ibcon#*before write, iclass 5, count 2 2006.173.15:10:56.25#ibcon#enter sib2, iclass 5, count 2 2006.173.15:10:56.25#ibcon#flushed, iclass 5, count 2 2006.173.15:10:56.25#ibcon#about to write, iclass 5, count 2 2006.173.15:10:56.25#ibcon#wrote, iclass 5, count 2 2006.173.15:10:56.25#ibcon#about to read 3, iclass 5, count 2 2006.173.15:10:56.28#ibcon#read 3, iclass 5, count 2 2006.173.15:10:56.28#ibcon#about to read 4, iclass 5, count 2 2006.173.15:10:56.28#ibcon#read 4, iclass 5, count 2 2006.173.15:10:56.28#ibcon#about to read 5, iclass 5, count 2 2006.173.15:10:56.28#ibcon#read 5, iclass 5, count 2 2006.173.15:10:56.28#ibcon#about to read 6, iclass 5, count 2 2006.173.15:10:56.28#ibcon#read 6, iclass 5, count 2 2006.173.15:10:56.28#ibcon#end of sib2, iclass 5, count 2 2006.173.15:10:56.28#ibcon#*after write, iclass 5, count 2 2006.173.15:10:56.28#ibcon#*before return 0, iclass 5, count 2 2006.173.15:10:56.28#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.15:10:56.28#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.15:10:56.28#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.15:10:56.28#ibcon#ireg 7 cls_cnt 0 2006.173.15:10:56.28#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.15:10:56.40#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.15:10:56.40#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.15:10:56.40#ibcon#enter wrdev, iclass 5, count 0 2006.173.15:10:56.40#ibcon#first serial, iclass 5, count 0 2006.173.15:10:56.40#ibcon#enter sib2, iclass 5, count 0 2006.173.15:10:56.40#ibcon#flushed, iclass 5, count 0 2006.173.15:10:56.40#ibcon#about to write, iclass 5, count 0 2006.173.15:10:56.40#ibcon#wrote, iclass 5, count 0 2006.173.15:10:56.40#ibcon#about to read 3, iclass 5, count 0 2006.173.15:10:56.42#ibcon#read 3, iclass 5, count 0 2006.173.15:10:56.42#ibcon#about to read 4, iclass 5, count 0 2006.173.15:10:56.42#ibcon#read 4, iclass 5, count 0 2006.173.15:10:56.42#ibcon#about to read 5, iclass 5, count 0 2006.173.15:10:56.42#ibcon#read 5, iclass 5, count 0 2006.173.15:10:56.42#ibcon#about to read 6, iclass 5, count 0 2006.173.15:10:56.42#ibcon#read 6, iclass 5, count 0 2006.173.15:10:56.42#ibcon#end of sib2, iclass 5, count 0 2006.173.15:10:56.42#ibcon#*mode == 0, iclass 5, count 0 2006.173.15:10:56.42#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.15:10:56.42#ibcon#[25=USB\r\n] 2006.173.15:10:56.42#ibcon#*before write, iclass 5, count 0 2006.173.15:10:56.42#ibcon#enter sib2, iclass 5, count 0 2006.173.15:10:56.42#ibcon#flushed, iclass 5, count 0 2006.173.15:10:56.42#ibcon#about to write, iclass 5, count 0 2006.173.15:10:56.42#ibcon#wrote, iclass 5, count 0 2006.173.15:10:56.42#ibcon#about to read 3, iclass 5, count 0 2006.173.15:10:56.45#ibcon#read 3, iclass 5, count 0 2006.173.15:10:56.45#ibcon#about to read 4, iclass 5, count 0 2006.173.15:10:56.45#ibcon#read 4, iclass 5, count 0 2006.173.15:10:56.45#ibcon#about to read 5, iclass 5, count 0 2006.173.15:10:56.45#ibcon#read 5, iclass 5, count 0 2006.173.15:10:56.45#ibcon#about to read 6, iclass 5, count 0 2006.173.15:10:56.45#ibcon#read 6, iclass 5, count 0 2006.173.15:10:56.45#ibcon#end of sib2, iclass 5, count 0 2006.173.15:10:56.45#ibcon#*after write, iclass 5, count 0 2006.173.15:10:56.45#ibcon#*before return 0, iclass 5, count 0 2006.173.15:10:56.45#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.15:10:56.45#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.15:10:56.45#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.15:10:56.45#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.15:10:56.45$vck44/valo=5,734.99 2006.173.15:10:56.45#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.15:10:56.45#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.15:10:56.45#ibcon#ireg 17 cls_cnt 0 2006.173.15:10:56.45#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.15:10:56.45#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.15:10:56.45#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.15:10:56.45#ibcon#enter wrdev, iclass 7, count 0 2006.173.15:10:56.45#ibcon#first serial, iclass 7, count 0 2006.173.15:10:56.45#ibcon#enter sib2, iclass 7, count 0 2006.173.15:10:56.45#ibcon#flushed, iclass 7, count 0 2006.173.15:10:56.45#ibcon#about to write, iclass 7, count 0 2006.173.15:10:56.45#ibcon#wrote, iclass 7, count 0 2006.173.15:10:56.45#ibcon#about to read 3, iclass 7, count 0 2006.173.15:10:56.47#ibcon#read 3, iclass 7, count 0 2006.173.15:10:56.47#ibcon#about to read 4, iclass 7, count 0 2006.173.15:10:56.47#ibcon#read 4, iclass 7, count 0 2006.173.15:10:56.47#ibcon#about to read 5, iclass 7, count 0 2006.173.15:10:56.47#ibcon#read 5, iclass 7, count 0 2006.173.15:10:56.47#ibcon#about to read 6, iclass 7, count 0 2006.173.15:10:56.47#ibcon#read 6, iclass 7, count 0 2006.173.15:10:56.47#ibcon#end of sib2, iclass 7, count 0 2006.173.15:10:56.47#ibcon#*mode == 0, iclass 7, count 0 2006.173.15:10:56.47#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.15:10:56.47#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.15:10:56.47#ibcon#*before write, iclass 7, count 0 2006.173.15:10:56.47#ibcon#enter sib2, iclass 7, count 0 2006.173.15:10:56.47#ibcon#flushed, iclass 7, count 0 2006.173.15:10:56.47#ibcon#about to write, iclass 7, count 0 2006.173.15:10:56.47#ibcon#wrote, iclass 7, count 0 2006.173.15:10:56.47#ibcon#about to read 3, iclass 7, count 0 2006.173.15:10:56.51#ibcon#read 3, iclass 7, count 0 2006.173.15:10:56.51#ibcon#about to read 4, iclass 7, count 0 2006.173.15:10:56.51#ibcon#read 4, iclass 7, count 0 2006.173.15:10:56.51#ibcon#about to read 5, iclass 7, count 0 2006.173.15:10:56.51#ibcon#read 5, iclass 7, count 0 2006.173.15:10:56.51#ibcon#about to read 6, iclass 7, count 0 2006.173.15:10:56.51#ibcon#read 6, iclass 7, count 0 2006.173.15:10:56.51#ibcon#end of sib2, iclass 7, count 0 2006.173.15:10:56.51#ibcon#*after write, iclass 7, count 0 2006.173.15:10:56.51#ibcon#*before return 0, iclass 7, count 0 2006.173.15:10:56.51#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.15:10:56.51#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.15:10:56.51#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.15:10:56.51#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.15:10:56.51$vck44/va=5,4 2006.173.15:10:56.51#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.15:10:56.51#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.15:10:56.51#ibcon#ireg 11 cls_cnt 2 2006.173.15:10:56.51#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.15:10:56.57#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.15:10:56.57#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.15:10:56.57#ibcon#enter wrdev, iclass 11, count 2 2006.173.15:10:56.57#ibcon#first serial, iclass 11, count 2 2006.173.15:10:56.57#ibcon#enter sib2, iclass 11, count 2 2006.173.15:10:56.57#ibcon#flushed, iclass 11, count 2 2006.173.15:10:56.57#ibcon#about to write, iclass 11, count 2 2006.173.15:10:56.57#ibcon#wrote, iclass 11, count 2 2006.173.15:10:56.57#ibcon#about to read 3, iclass 11, count 2 2006.173.15:10:56.59#ibcon#read 3, iclass 11, count 2 2006.173.15:10:56.59#ibcon#about to read 4, iclass 11, count 2 2006.173.15:10:56.59#ibcon#read 4, iclass 11, count 2 2006.173.15:10:56.59#ibcon#about to read 5, iclass 11, count 2 2006.173.15:10:56.59#ibcon#read 5, iclass 11, count 2 2006.173.15:10:56.59#ibcon#about to read 6, iclass 11, count 2 2006.173.15:10:56.59#ibcon#read 6, iclass 11, count 2 2006.173.15:10:56.59#ibcon#end of sib2, iclass 11, count 2 2006.173.15:10:56.59#ibcon#*mode == 0, iclass 11, count 2 2006.173.15:10:56.59#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.15:10:56.59#ibcon#[25=AT05-04\r\n] 2006.173.15:10:56.59#ibcon#*before write, iclass 11, count 2 2006.173.15:10:56.59#ibcon#enter sib2, iclass 11, count 2 2006.173.15:10:56.59#ibcon#flushed, iclass 11, count 2 2006.173.15:10:56.59#ibcon#about to write, iclass 11, count 2 2006.173.15:10:56.59#ibcon#wrote, iclass 11, count 2 2006.173.15:10:56.59#ibcon#about to read 3, iclass 11, count 2 2006.173.15:10:56.62#ibcon#read 3, iclass 11, count 2 2006.173.15:10:56.62#ibcon#about to read 4, iclass 11, count 2 2006.173.15:10:56.62#ibcon#read 4, iclass 11, count 2 2006.173.15:10:56.62#ibcon#about to read 5, iclass 11, count 2 2006.173.15:10:56.62#ibcon#read 5, iclass 11, count 2 2006.173.15:10:56.62#ibcon#about to read 6, iclass 11, count 2 2006.173.15:10:56.62#ibcon#read 6, iclass 11, count 2 2006.173.15:10:56.62#ibcon#end of sib2, iclass 11, count 2 2006.173.15:10:56.62#ibcon#*after write, iclass 11, count 2 2006.173.15:10:56.62#ibcon#*before return 0, iclass 11, count 2 2006.173.15:10:56.62#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.15:10:56.62#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.15:10:56.62#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.15:10:56.62#ibcon#ireg 7 cls_cnt 0 2006.173.15:10:56.62#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.15:10:56.74#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.15:10:56.74#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.15:10:56.74#ibcon#enter wrdev, iclass 11, count 0 2006.173.15:10:56.74#ibcon#first serial, iclass 11, count 0 2006.173.15:10:56.74#ibcon#enter sib2, iclass 11, count 0 2006.173.15:10:56.74#ibcon#flushed, iclass 11, count 0 2006.173.15:10:56.74#ibcon#about to write, iclass 11, count 0 2006.173.15:10:56.74#ibcon#wrote, iclass 11, count 0 2006.173.15:10:56.74#ibcon#about to read 3, iclass 11, count 0 2006.173.15:10:56.76#ibcon#read 3, iclass 11, count 0 2006.173.15:10:56.76#ibcon#about to read 4, iclass 11, count 0 2006.173.15:10:56.76#ibcon#read 4, iclass 11, count 0 2006.173.15:10:56.76#ibcon#about to read 5, iclass 11, count 0 2006.173.15:10:56.76#ibcon#read 5, iclass 11, count 0 2006.173.15:10:56.76#ibcon#about to read 6, iclass 11, count 0 2006.173.15:10:56.76#ibcon#read 6, iclass 11, count 0 2006.173.15:10:56.76#ibcon#end of sib2, iclass 11, count 0 2006.173.15:10:56.76#ibcon#*mode == 0, iclass 11, count 0 2006.173.15:10:56.76#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.15:10:56.76#ibcon#[25=USB\r\n] 2006.173.15:10:56.76#ibcon#*before write, iclass 11, count 0 2006.173.15:10:56.76#ibcon#enter sib2, iclass 11, count 0 2006.173.15:10:56.76#ibcon#flushed, iclass 11, count 0 2006.173.15:10:56.76#ibcon#about to write, iclass 11, count 0 2006.173.15:10:56.76#ibcon#wrote, iclass 11, count 0 2006.173.15:10:56.76#ibcon#about to read 3, iclass 11, count 0 2006.173.15:10:56.79#ibcon#read 3, iclass 11, count 0 2006.173.15:10:56.79#ibcon#about to read 4, iclass 11, count 0 2006.173.15:10:56.79#ibcon#read 4, iclass 11, count 0 2006.173.15:10:56.79#ibcon#about to read 5, iclass 11, count 0 2006.173.15:10:56.79#ibcon#read 5, iclass 11, count 0 2006.173.15:10:56.79#ibcon#about to read 6, iclass 11, count 0 2006.173.15:10:56.79#ibcon#read 6, iclass 11, count 0 2006.173.15:10:56.79#ibcon#end of sib2, iclass 11, count 0 2006.173.15:10:56.79#ibcon#*after write, iclass 11, count 0 2006.173.15:10:56.79#ibcon#*before return 0, iclass 11, count 0 2006.173.15:10:56.79#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.15:10:56.79#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.15:10:56.79#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.15:10:56.79#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.15:10:56.79$vck44/valo=6,814.99 2006.173.15:10:56.79#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.15:10:56.79#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.15:10:56.79#ibcon#ireg 17 cls_cnt 0 2006.173.15:10:56.79#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.15:10:56.79#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.15:10:56.79#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.15:10:56.79#ibcon#enter wrdev, iclass 13, count 0 2006.173.15:10:56.79#ibcon#first serial, iclass 13, count 0 2006.173.15:10:56.79#ibcon#enter sib2, iclass 13, count 0 2006.173.15:10:56.79#ibcon#flushed, iclass 13, count 0 2006.173.15:10:56.79#ibcon#about to write, iclass 13, count 0 2006.173.15:10:56.79#ibcon#wrote, iclass 13, count 0 2006.173.15:10:56.79#ibcon#about to read 3, iclass 13, count 0 2006.173.15:10:56.81#ibcon#read 3, iclass 13, count 0 2006.173.15:10:56.81#ibcon#about to read 4, iclass 13, count 0 2006.173.15:10:56.81#ibcon#read 4, iclass 13, count 0 2006.173.15:10:56.81#ibcon#about to read 5, iclass 13, count 0 2006.173.15:10:56.81#ibcon#read 5, iclass 13, count 0 2006.173.15:10:56.81#ibcon#about to read 6, iclass 13, count 0 2006.173.15:10:56.81#ibcon#read 6, iclass 13, count 0 2006.173.15:10:56.81#ibcon#end of sib2, iclass 13, count 0 2006.173.15:10:56.81#ibcon#*mode == 0, iclass 13, count 0 2006.173.15:10:56.81#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.15:10:56.81#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.15:10:56.81#ibcon#*before write, iclass 13, count 0 2006.173.15:10:56.81#ibcon#enter sib2, iclass 13, count 0 2006.173.15:10:56.81#ibcon#flushed, iclass 13, count 0 2006.173.15:10:56.81#ibcon#about to write, iclass 13, count 0 2006.173.15:10:56.81#ibcon#wrote, iclass 13, count 0 2006.173.15:10:56.81#ibcon#about to read 3, iclass 13, count 0 2006.173.15:10:56.85#ibcon#read 3, iclass 13, count 0 2006.173.15:10:56.85#ibcon#about to read 4, iclass 13, count 0 2006.173.15:10:56.85#ibcon#read 4, iclass 13, count 0 2006.173.15:10:56.85#ibcon#about to read 5, iclass 13, count 0 2006.173.15:10:56.85#ibcon#read 5, iclass 13, count 0 2006.173.15:10:56.85#ibcon#about to read 6, iclass 13, count 0 2006.173.15:10:56.85#ibcon#read 6, iclass 13, count 0 2006.173.15:10:56.85#ibcon#end of sib2, iclass 13, count 0 2006.173.15:10:56.85#ibcon#*after write, iclass 13, count 0 2006.173.15:10:56.85#ibcon#*before return 0, iclass 13, count 0 2006.173.15:10:56.85#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.15:10:56.85#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.15:10:56.85#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.15:10:56.85#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.15:10:56.85$vck44/va=6,3 2006.173.15:10:56.85#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.15:10:56.85#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.15:10:56.85#ibcon#ireg 11 cls_cnt 2 2006.173.15:10:56.85#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.15:10:56.91#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.15:10:56.91#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.15:10:56.91#ibcon#enter wrdev, iclass 15, count 2 2006.173.15:10:56.91#ibcon#first serial, iclass 15, count 2 2006.173.15:10:56.91#ibcon#enter sib2, iclass 15, count 2 2006.173.15:10:56.91#ibcon#flushed, iclass 15, count 2 2006.173.15:10:56.91#ibcon#about to write, iclass 15, count 2 2006.173.15:10:56.91#ibcon#wrote, iclass 15, count 2 2006.173.15:10:56.91#ibcon#about to read 3, iclass 15, count 2 2006.173.15:10:56.93#ibcon#read 3, iclass 15, count 2 2006.173.15:10:56.93#ibcon#about to read 4, iclass 15, count 2 2006.173.15:10:56.93#ibcon#read 4, iclass 15, count 2 2006.173.15:10:56.93#ibcon#about to read 5, iclass 15, count 2 2006.173.15:10:56.93#ibcon#read 5, iclass 15, count 2 2006.173.15:10:56.93#ibcon#about to read 6, iclass 15, count 2 2006.173.15:10:56.93#ibcon#read 6, iclass 15, count 2 2006.173.15:10:56.93#ibcon#end of sib2, iclass 15, count 2 2006.173.15:10:56.93#ibcon#*mode == 0, iclass 15, count 2 2006.173.15:10:56.93#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.15:10:56.93#ibcon#[25=AT06-03\r\n] 2006.173.15:10:56.93#ibcon#*before write, iclass 15, count 2 2006.173.15:10:56.93#ibcon#enter sib2, iclass 15, count 2 2006.173.15:10:56.93#ibcon#flushed, iclass 15, count 2 2006.173.15:10:56.93#ibcon#about to write, iclass 15, count 2 2006.173.15:10:56.93#ibcon#wrote, iclass 15, count 2 2006.173.15:10:56.93#ibcon#about to read 3, iclass 15, count 2 2006.173.15:10:56.96#ibcon#read 3, iclass 15, count 2 2006.173.15:10:56.96#ibcon#about to read 4, iclass 15, count 2 2006.173.15:10:56.96#ibcon#read 4, iclass 15, count 2 2006.173.15:10:56.96#ibcon#about to read 5, iclass 15, count 2 2006.173.15:10:56.96#ibcon#read 5, iclass 15, count 2 2006.173.15:10:56.96#ibcon#about to read 6, iclass 15, count 2 2006.173.15:10:56.96#ibcon#read 6, iclass 15, count 2 2006.173.15:10:56.96#ibcon#end of sib2, iclass 15, count 2 2006.173.15:10:56.96#ibcon#*after write, iclass 15, count 2 2006.173.15:10:56.96#ibcon#*before return 0, iclass 15, count 2 2006.173.15:10:56.96#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.15:10:56.96#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.15:10:56.96#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.15:10:56.96#ibcon#ireg 7 cls_cnt 0 2006.173.15:10:56.96#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.15:10:57.08#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.15:10:57.08#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.15:10:57.08#ibcon#enter wrdev, iclass 15, count 0 2006.173.15:10:57.08#ibcon#first serial, iclass 15, count 0 2006.173.15:10:57.08#ibcon#enter sib2, iclass 15, count 0 2006.173.15:10:57.08#ibcon#flushed, iclass 15, count 0 2006.173.15:10:57.08#ibcon#about to write, iclass 15, count 0 2006.173.15:10:57.08#ibcon#wrote, iclass 15, count 0 2006.173.15:10:57.08#ibcon#about to read 3, iclass 15, count 0 2006.173.15:10:57.10#ibcon#read 3, iclass 15, count 0 2006.173.15:10:57.10#ibcon#about to read 4, iclass 15, count 0 2006.173.15:10:57.10#ibcon#read 4, iclass 15, count 0 2006.173.15:10:57.10#ibcon#about to read 5, iclass 15, count 0 2006.173.15:10:57.10#ibcon#read 5, iclass 15, count 0 2006.173.15:10:57.10#ibcon#about to read 6, iclass 15, count 0 2006.173.15:10:57.10#ibcon#read 6, iclass 15, count 0 2006.173.15:10:57.10#ibcon#end of sib2, iclass 15, count 0 2006.173.15:10:57.10#ibcon#*mode == 0, iclass 15, count 0 2006.173.15:10:57.10#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.15:10:57.10#ibcon#[25=USB\r\n] 2006.173.15:10:57.10#ibcon#*before write, iclass 15, count 0 2006.173.15:10:57.10#ibcon#enter sib2, iclass 15, count 0 2006.173.15:10:57.10#ibcon#flushed, iclass 15, count 0 2006.173.15:10:57.10#ibcon#about to write, iclass 15, count 0 2006.173.15:10:57.10#ibcon#wrote, iclass 15, count 0 2006.173.15:10:57.10#ibcon#about to read 3, iclass 15, count 0 2006.173.15:10:57.13#ibcon#read 3, iclass 15, count 0 2006.173.15:10:57.13#ibcon#about to read 4, iclass 15, count 0 2006.173.15:10:57.13#ibcon#read 4, iclass 15, count 0 2006.173.15:10:57.13#ibcon#about to read 5, iclass 15, count 0 2006.173.15:10:57.13#ibcon#read 5, iclass 15, count 0 2006.173.15:10:57.13#ibcon#about to read 6, iclass 15, count 0 2006.173.15:10:57.13#ibcon#read 6, iclass 15, count 0 2006.173.15:10:57.13#ibcon#end of sib2, iclass 15, count 0 2006.173.15:10:57.13#ibcon#*after write, iclass 15, count 0 2006.173.15:10:57.13#ibcon#*before return 0, iclass 15, count 0 2006.173.15:10:57.13#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.15:10:57.13#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.15:10:57.13#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.15:10:57.13#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.15:10:57.13$vck44/valo=7,864.99 2006.173.15:10:57.13#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.15:10:57.13#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.15:10:57.13#ibcon#ireg 17 cls_cnt 0 2006.173.15:10:57.13#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.15:10:57.13#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.15:10:57.13#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.15:10:57.13#ibcon#enter wrdev, iclass 17, count 0 2006.173.15:10:57.13#ibcon#first serial, iclass 17, count 0 2006.173.15:10:57.13#ibcon#enter sib2, iclass 17, count 0 2006.173.15:10:57.13#ibcon#flushed, iclass 17, count 0 2006.173.15:10:57.13#ibcon#about to write, iclass 17, count 0 2006.173.15:10:57.13#ibcon#wrote, iclass 17, count 0 2006.173.15:10:57.13#ibcon#about to read 3, iclass 17, count 0 2006.173.15:10:57.15#ibcon#read 3, iclass 17, count 0 2006.173.15:10:57.15#ibcon#about to read 4, iclass 17, count 0 2006.173.15:10:57.15#ibcon#read 4, iclass 17, count 0 2006.173.15:10:57.15#ibcon#about to read 5, iclass 17, count 0 2006.173.15:10:57.15#ibcon#read 5, iclass 17, count 0 2006.173.15:10:57.15#ibcon#about to read 6, iclass 17, count 0 2006.173.15:10:57.15#ibcon#read 6, iclass 17, count 0 2006.173.15:10:57.15#ibcon#end of sib2, iclass 17, count 0 2006.173.15:10:57.15#ibcon#*mode == 0, iclass 17, count 0 2006.173.15:10:57.15#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.15:10:57.15#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.15:10:57.15#ibcon#*before write, iclass 17, count 0 2006.173.15:10:57.15#ibcon#enter sib2, iclass 17, count 0 2006.173.15:10:57.15#ibcon#flushed, iclass 17, count 0 2006.173.15:10:57.15#ibcon#about to write, iclass 17, count 0 2006.173.15:10:57.15#ibcon#wrote, iclass 17, count 0 2006.173.15:10:57.15#ibcon#about to read 3, iclass 17, count 0 2006.173.15:10:57.19#ibcon#read 3, iclass 17, count 0 2006.173.15:10:57.19#ibcon#about to read 4, iclass 17, count 0 2006.173.15:10:57.19#ibcon#read 4, iclass 17, count 0 2006.173.15:10:57.19#ibcon#about to read 5, iclass 17, count 0 2006.173.15:10:57.19#ibcon#read 5, iclass 17, count 0 2006.173.15:10:57.19#ibcon#about to read 6, iclass 17, count 0 2006.173.15:10:57.19#ibcon#read 6, iclass 17, count 0 2006.173.15:10:57.19#ibcon#end of sib2, iclass 17, count 0 2006.173.15:10:57.19#ibcon#*after write, iclass 17, count 0 2006.173.15:10:57.19#ibcon#*before return 0, iclass 17, count 0 2006.173.15:10:57.19#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.15:10:57.19#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.15:10:57.19#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.15:10:57.19#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.15:10:57.19$vck44/va=7,4 2006.173.15:10:57.19#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.15:10:57.19#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.15:10:57.19#ibcon#ireg 11 cls_cnt 2 2006.173.15:10:57.19#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.15:10:57.25#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.15:10:57.25#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.15:10:57.25#ibcon#enter wrdev, iclass 19, count 2 2006.173.15:10:57.25#ibcon#first serial, iclass 19, count 2 2006.173.15:10:57.25#ibcon#enter sib2, iclass 19, count 2 2006.173.15:10:57.25#ibcon#flushed, iclass 19, count 2 2006.173.15:10:57.25#ibcon#about to write, iclass 19, count 2 2006.173.15:10:57.25#ibcon#wrote, iclass 19, count 2 2006.173.15:10:57.25#ibcon#about to read 3, iclass 19, count 2 2006.173.15:10:57.27#ibcon#read 3, iclass 19, count 2 2006.173.15:10:57.27#ibcon#about to read 4, iclass 19, count 2 2006.173.15:10:57.27#ibcon#read 4, iclass 19, count 2 2006.173.15:10:57.27#ibcon#about to read 5, iclass 19, count 2 2006.173.15:10:57.27#ibcon#read 5, iclass 19, count 2 2006.173.15:10:57.27#ibcon#about to read 6, iclass 19, count 2 2006.173.15:10:57.27#ibcon#read 6, iclass 19, count 2 2006.173.15:10:57.27#ibcon#end of sib2, iclass 19, count 2 2006.173.15:10:57.27#ibcon#*mode == 0, iclass 19, count 2 2006.173.15:10:57.27#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.15:10:57.27#ibcon#[25=AT07-04\r\n] 2006.173.15:10:57.27#ibcon#*before write, iclass 19, count 2 2006.173.15:10:57.27#ibcon#enter sib2, iclass 19, count 2 2006.173.15:10:57.27#ibcon#flushed, iclass 19, count 2 2006.173.15:10:57.27#ibcon#about to write, iclass 19, count 2 2006.173.15:10:57.27#ibcon#wrote, iclass 19, count 2 2006.173.15:10:57.27#ibcon#about to read 3, iclass 19, count 2 2006.173.15:10:57.30#ibcon#read 3, iclass 19, count 2 2006.173.15:10:57.30#ibcon#about to read 4, iclass 19, count 2 2006.173.15:10:57.30#ibcon#read 4, iclass 19, count 2 2006.173.15:10:57.30#ibcon#about to read 5, iclass 19, count 2 2006.173.15:10:57.30#ibcon#read 5, iclass 19, count 2 2006.173.15:10:57.30#ibcon#about to read 6, iclass 19, count 2 2006.173.15:10:57.30#ibcon#read 6, iclass 19, count 2 2006.173.15:10:57.30#ibcon#end of sib2, iclass 19, count 2 2006.173.15:10:57.30#ibcon#*after write, iclass 19, count 2 2006.173.15:10:57.30#ibcon#*before return 0, iclass 19, count 2 2006.173.15:10:57.30#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.15:10:57.30#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.15:10:57.30#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.15:10:57.30#ibcon#ireg 7 cls_cnt 0 2006.173.15:10:57.30#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.15:10:57.42#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.15:10:57.42#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.15:10:57.42#ibcon#enter wrdev, iclass 19, count 0 2006.173.15:10:57.42#ibcon#first serial, iclass 19, count 0 2006.173.15:10:57.42#ibcon#enter sib2, iclass 19, count 0 2006.173.15:10:57.42#ibcon#flushed, iclass 19, count 0 2006.173.15:10:57.42#ibcon#about to write, iclass 19, count 0 2006.173.15:10:57.42#ibcon#wrote, iclass 19, count 0 2006.173.15:10:57.42#ibcon#about to read 3, iclass 19, count 0 2006.173.15:10:57.44#ibcon#read 3, iclass 19, count 0 2006.173.15:10:57.44#ibcon#about to read 4, iclass 19, count 0 2006.173.15:10:57.44#ibcon#read 4, iclass 19, count 0 2006.173.15:10:57.44#ibcon#about to read 5, iclass 19, count 0 2006.173.15:10:57.44#ibcon#read 5, iclass 19, count 0 2006.173.15:10:57.44#ibcon#about to read 6, iclass 19, count 0 2006.173.15:10:57.44#ibcon#read 6, iclass 19, count 0 2006.173.15:10:57.44#ibcon#end of sib2, iclass 19, count 0 2006.173.15:10:57.44#ibcon#*mode == 0, iclass 19, count 0 2006.173.15:10:57.44#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.15:10:57.44#ibcon#[25=USB\r\n] 2006.173.15:10:57.44#ibcon#*before write, iclass 19, count 0 2006.173.15:10:57.44#ibcon#enter sib2, iclass 19, count 0 2006.173.15:10:57.44#ibcon#flushed, iclass 19, count 0 2006.173.15:10:57.44#ibcon#about to write, iclass 19, count 0 2006.173.15:10:57.44#ibcon#wrote, iclass 19, count 0 2006.173.15:10:57.44#ibcon#about to read 3, iclass 19, count 0 2006.173.15:10:57.47#ibcon#read 3, iclass 19, count 0 2006.173.15:10:57.47#ibcon#about to read 4, iclass 19, count 0 2006.173.15:10:57.47#ibcon#read 4, iclass 19, count 0 2006.173.15:10:57.47#ibcon#about to read 5, iclass 19, count 0 2006.173.15:10:57.47#ibcon#read 5, iclass 19, count 0 2006.173.15:10:57.47#ibcon#about to read 6, iclass 19, count 0 2006.173.15:10:57.47#ibcon#read 6, iclass 19, count 0 2006.173.15:10:57.47#ibcon#end of sib2, iclass 19, count 0 2006.173.15:10:57.47#ibcon#*after write, iclass 19, count 0 2006.173.15:10:57.47#ibcon#*before return 0, iclass 19, count 0 2006.173.15:10:57.47#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.15:10:57.47#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.15:10:57.47#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.15:10:57.47#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.15:10:57.47$vck44/valo=8,884.99 2006.173.15:10:57.47#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.15:10:57.47#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.15:10:57.47#ibcon#ireg 17 cls_cnt 0 2006.173.15:10:57.47#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.15:10:57.47#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.15:10:57.47#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.15:10:57.47#ibcon#enter wrdev, iclass 21, count 0 2006.173.15:10:57.47#ibcon#first serial, iclass 21, count 0 2006.173.15:10:57.47#ibcon#enter sib2, iclass 21, count 0 2006.173.15:10:57.47#ibcon#flushed, iclass 21, count 0 2006.173.15:10:57.47#ibcon#about to write, iclass 21, count 0 2006.173.15:10:57.47#ibcon#wrote, iclass 21, count 0 2006.173.15:10:57.47#ibcon#about to read 3, iclass 21, count 0 2006.173.15:10:57.49#ibcon#read 3, iclass 21, count 0 2006.173.15:10:57.49#ibcon#about to read 4, iclass 21, count 0 2006.173.15:10:57.49#ibcon#read 4, iclass 21, count 0 2006.173.15:10:57.49#ibcon#about to read 5, iclass 21, count 0 2006.173.15:10:57.49#ibcon#read 5, iclass 21, count 0 2006.173.15:10:57.49#ibcon#about to read 6, iclass 21, count 0 2006.173.15:10:57.49#ibcon#read 6, iclass 21, count 0 2006.173.15:10:57.49#ibcon#end of sib2, iclass 21, count 0 2006.173.15:10:57.49#ibcon#*mode == 0, iclass 21, count 0 2006.173.15:10:57.49#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.15:10:57.49#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.15:10:57.49#ibcon#*before write, iclass 21, count 0 2006.173.15:10:57.49#ibcon#enter sib2, iclass 21, count 0 2006.173.15:10:57.49#ibcon#flushed, iclass 21, count 0 2006.173.15:10:57.49#ibcon#about to write, iclass 21, count 0 2006.173.15:10:57.49#ibcon#wrote, iclass 21, count 0 2006.173.15:10:57.49#ibcon#about to read 3, iclass 21, count 0 2006.173.15:10:57.53#ibcon#read 3, iclass 21, count 0 2006.173.15:10:57.53#ibcon#about to read 4, iclass 21, count 0 2006.173.15:10:57.53#ibcon#read 4, iclass 21, count 0 2006.173.15:10:57.53#ibcon#about to read 5, iclass 21, count 0 2006.173.15:10:57.53#ibcon#read 5, iclass 21, count 0 2006.173.15:10:57.53#ibcon#about to read 6, iclass 21, count 0 2006.173.15:10:57.53#ibcon#read 6, iclass 21, count 0 2006.173.15:10:57.53#ibcon#end of sib2, iclass 21, count 0 2006.173.15:10:57.53#ibcon#*after write, iclass 21, count 0 2006.173.15:10:57.53#ibcon#*before return 0, iclass 21, count 0 2006.173.15:10:57.53#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.15:10:57.53#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.15:10:57.53#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.15:10:57.53#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.15:10:57.53$vck44/va=8,4 2006.173.15:10:57.53#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.15:10:57.53#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.15:10:57.53#ibcon#ireg 11 cls_cnt 2 2006.173.15:10:57.53#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.15:10:57.59#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.15:10:57.59#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.15:10:57.59#ibcon#enter wrdev, iclass 23, count 2 2006.173.15:10:57.59#ibcon#first serial, iclass 23, count 2 2006.173.15:10:57.59#ibcon#enter sib2, iclass 23, count 2 2006.173.15:10:57.59#ibcon#flushed, iclass 23, count 2 2006.173.15:10:57.59#ibcon#about to write, iclass 23, count 2 2006.173.15:10:57.59#ibcon#wrote, iclass 23, count 2 2006.173.15:10:57.59#ibcon#about to read 3, iclass 23, count 2 2006.173.15:10:57.61#ibcon#read 3, iclass 23, count 2 2006.173.15:10:57.61#ibcon#about to read 4, iclass 23, count 2 2006.173.15:10:57.61#ibcon#read 4, iclass 23, count 2 2006.173.15:10:57.61#ibcon#about to read 5, iclass 23, count 2 2006.173.15:10:57.61#ibcon#read 5, iclass 23, count 2 2006.173.15:10:57.61#ibcon#about to read 6, iclass 23, count 2 2006.173.15:10:57.61#ibcon#read 6, iclass 23, count 2 2006.173.15:10:57.61#ibcon#end of sib2, iclass 23, count 2 2006.173.15:10:57.61#ibcon#*mode == 0, iclass 23, count 2 2006.173.15:10:57.61#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.15:10:57.61#ibcon#[25=AT08-04\r\n] 2006.173.15:10:57.61#ibcon#*before write, iclass 23, count 2 2006.173.15:10:57.61#ibcon#enter sib2, iclass 23, count 2 2006.173.15:10:57.61#ibcon#flushed, iclass 23, count 2 2006.173.15:10:57.61#ibcon#about to write, iclass 23, count 2 2006.173.15:10:57.61#ibcon#wrote, iclass 23, count 2 2006.173.15:10:57.61#ibcon#about to read 3, iclass 23, count 2 2006.173.15:10:57.64#ibcon#read 3, iclass 23, count 2 2006.173.15:10:57.64#ibcon#about to read 4, iclass 23, count 2 2006.173.15:10:57.64#ibcon#read 4, iclass 23, count 2 2006.173.15:10:57.64#ibcon#about to read 5, iclass 23, count 2 2006.173.15:10:57.64#ibcon#read 5, iclass 23, count 2 2006.173.15:10:57.64#ibcon#about to read 6, iclass 23, count 2 2006.173.15:10:57.64#ibcon#read 6, iclass 23, count 2 2006.173.15:10:57.64#ibcon#end of sib2, iclass 23, count 2 2006.173.15:10:57.64#ibcon#*after write, iclass 23, count 2 2006.173.15:10:57.64#ibcon#*before return 0, iclass 23, count 2 2006.173.15:10:57.64#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.15:10:57.64#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.15:10:57.64#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.15:10:57.64#ibcon#ireg 7 cls_cnt 0 2006.173.15:10:57.64#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.15:10:57.76#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.15:10:57.76#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.15:10:57.76#ibcon#enter wrdev, iclass 23, count 0 2006.173.15:10:57.76#ibcon#first serial, iclass 23, count 0 2006.173.15:10:57.76#ibcon#enter sib2, iclass 23, count 0 2006.173.15:10:57.76#ibcon#flushed, iclass 23, count 0 2006.173.15:10:57.76#ibcon#about to write, iclass 23, count 0 2006.173.15:10:57.76#ibcon#wrote, iclass 23, count 0 2006.173.15:10:57.76#ibcon#about to read 3, iclass 23, count 0 2006.173.15:10:57.78#ibcon#read 3, iclass 23, count 0 2006.173.15:10:57.78#ibcon#about to read 4, iclass 23, count 0 2006.173.15:10:57.78#ibcon#read 4, iclass 23, count 0 2006.173.15:10:57.78#ibcon#about to read 5, iclass 23, count 0 2006.173.15:10:57.78#ibcon#read 5, iclass 23, count 0 2006.173.15:10:57.78#ibcon#about to read 6, iclass 23, count 0 2006.173.15:10:57.78#ibcon#read 6, iclass 23, count 0 2006.173.15:10:57.78#ibcon#end of sib2, iclass 23, count 0 2006.173.15:10:57.78#ibcon#*mode == 0, iclass 23, count 0 2006.173.15:10:57.78#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.15:10:57.78#ibcon#[25=USB\r\n] 2006.173.15:10:57.78#ibcon#*before write, iclass 23, count 0 2006.173.15:10:57.78#ibcon#enter sib2, iclass 23, count 0 2006.173.15:10:57.78#ibcon#flushed, iclass 23, count 0 2006.173.15:10:57.78#ibcon#about to write, iclass 23, count 0 2006.173.15:10:57.78#ibcon#wrote, iclass 23, count 0 2006.173.15:10:57.78#ibcon#about to read 3, iclass 23, count 0 2006.173.15:10:57.81#ibcon#read 3, iclass 23, count 0 2006.173.15:10:57.81#ibcon#about to read 4, iclass 23, count 0 2006.173.15:10:57.81#ibcon#read 4, iclass 23, count 0 2006.173.15:10:57.81#ibcon#about to read 5, iclass 23, count 0 2006.173.15:10:57.81#ibcon#read 5, iclass 23, count 0 2006.173.15:10:57.81#ibcon#about to read 6, iclass 23, count 0 2006.173.15:10:57.81#ibcon#read 6, iclass 23, count 0 2006.173.15:10:57.81#ibcon#end of sib2, iclass 23, count 0 2006.173.15:10:57.81#ibcon#*after write, iclass 23, count 0 2006.173.15:10:57.81#ibcon#*before return 0, iclass 23, count 0 2006.173.15:10:57.81#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.15:10:57.81#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.15:10:57.81#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.15:10:57.81#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.15:10:57.81$vck44/vblo=1,629.99 2006.173.15:10:57.81#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.15:10:57.81#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.15:10:57.81#ibcon#ireg 17 cls_cnt 0 2006.173.15:10:57.81#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.15:10:57.81#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.15:10:57.81#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.15:10:57.81#ibcon#enter wrdev, iclass 25, count 0 2006.173.15:10:57.81#ibcon#first serial, iclass 25, count 0 2006.173.15:10:57.81#ibcon#enter sib2, iclass 25, count 0 2006.173.15:10:57.81#ibcon#flushed, iclass 25, count 0 2006.173.15:10:57.81#ibcon#about to write, iclass 25, count 0 2006.173.15:10:57.81#ibcon#wrote, iclass 25, count 0 2006.173.15:10:57.81#ibcon#about to read 3, iclass 25, count 0 2006.173.15:10:57.83#ibcon#read 3, iclass 25, count 0 2006.173.15:10:57.83#ibcon#about to read 4, iclass 25, count 0 2006.173.15:10:57.83#ibcon#read 4, iclass 25, count 0 2006.173.15:10:57.83#ibcon#about to read 5, iclass 25, count 0 2006.173.15:10:57.83#ibcon#read 5, iclass 25, count 0 2006.173.15:10:57.83#ibcon#about to read 6, iclass 25, count 0 2006.173.15:10:57.83#ibcon#read 6, iclass 25, count 0 2006.173.15:10:57.83#ibcon#end of sib2, iclass 25, count 0 2006.173.15:10:57.83#ibcon#*mode == 0, iclass 25, count 0 2006.173.15:10:57.83#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.15:10:57.83#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.15:10:57.83#ibcon#*before write, iclass 25, count 0 2006.173.15:10:57.83#ibcon#enter sib2, iclass 25, count 0 2006.173.15:10:57.83#ibcon#flushed, iclass 25, count 0 2006.173.15:10:57.83#ibcon#about to write, iclass 25, count 0 2006.173.15:10:57.83#ibcon#wrote, iclass 25, count 0 2006.173.15:10:57.83#ibcon#about to read 3, iclass 25, count 0 2006.173.15:10:57.87#ibcon#read 3, iclass 25, count 0 2006.173.15:10:57.87#ibcon#about to read 4, iclass 25, count 0 2006.173.15:10:57.87#ibcon#read 4, iclass 25, count 0 2006.173.15:10:57.87#ibcon#about to read 5, iclass 25, count 0 2006.173.15:10:57.87#ibcon#read 5, iclass 25, count 0 2006.173.15:10:57.87#ibcon#about to read 6, iclass 25, count 0 2006.173.15:10:57.87#ibcon#read 6, iclass 25, count 0 2006.173.15:10:57.87#ibcon#end of sib2, iclass 25, count 0 2006.173.15:10:57.87#ibcon#*after write, iclass 25, count 0 2006.173.15:10:57.87#ibcon#*before return 0, iclass 25, count 0 2006.173.15:10:57.87#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.15:10:57.87#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.15:10:57.87#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.15:10:57.87#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.15:10:57.87$vck44/vb=1,4 2006.173.15:10:57.87#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.15:10:57.87#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.15:10:57.87#ibcon#ireg 11 cls_cnt 2 2006.173.15:10:57.87#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.15:10:57.87#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.15:10:57.87#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.15:10:57.87#ibcon#enter wrdev, iclass 27, count 2 2006.173.15:10:57.87#ibcon#first serial, iclass 27, count 2 2006.173.15:10:57.87#ibcon#enter sib2, iclass 27, count 2 2006.173.15:10:57.87#ibcon#flushed, iclass 27, count 2 2006.173.15:10:57.87#ibcon#about to write, iclass 27, count 2 2006.173.15:10:57.87#ibcon#wrote, iclass 27, count 2 2006.173.15:10:57.87#ibcon#about to read 3, iclass 27, count 2 2006.173.15:10:57.89#ibcon#read 3, iclass 27, count 2 2006.173.15:10:57.89#ibcon#about to read 4, iclass 27, count 2 2006.173.15:10:57.89#ibcon#read 4, iclass 27, count 2 2006.173.15:10:57.89#ibcon#about to read 5, iclass 27, count 2 2006.173.15:10:57.89#ibcon#read 5, iclass 27, count 2 2006.173.15:10:57.89#ibcon#about to read 6, iclass 27, count 2 2006.173.15:10:57.89#ibcon#read 6, iclass 27, count 2 2006.173.15:10:57.89#ibcon#end of sib2, iclass 27, count 2 2006.173.15:10:57.89#ibcon#*mode == 0, iclass 27, count 2 2006.173.15:10:57.89#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.15:10:57.89#ibcon#[27=AT01-04\r\n] 2006.173.15:10:57.89#ibcon#*before write, iclass 27, count 2 2006.173.15:10:57.89#ibcon#enter sib2, iclass 27, count 2 2006.173.15:10:57.89#ibcon#flushed, iclass 27, count 2 2006.173.15:10:57.89#ibcon#about to write, iclass 27, count 2 2006.173.15:10:57.89#ibcon#wrote, iclass 27, count 2 2006.173.15:10:57.89#ibcon#about to read 3, iclass 27, count 2 2006.173.15:10:57.92#ibcon#read 3, iclass 27, count 2 2006.173.15:10:57.92#ibcon#about to read 4, iclass 27, count 2 2006.173.15:10:57.92#ibcon#read 4, iclass 27, count 2 2006.173.15:10:57.92#ibcon#about to read 5, iclass 27, count 2 2006.173.15:10:57.92#ibcon#read 5, iclass 27, count 2 2006.173.15:10:57.92#ibcon#about to read 6, iclass 27, count 2 2006.173.15:10:57.92#ibcon#read 6, iclass 27, count 2 2006.173.15:10:57.92#ibcon#end of sib2, iclass 27, count 2 2006.173.15:10:57.92#ibcon#*after write, iclass 27, count 2 2006.173.15:10:57.92#ibcon#*before return 0, iclass 27, count 2 2006.173.15:10:57.92#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.15:10:57.92#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.15:10:57.92#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.15:10:57.92#ibcon#ireg 7 cls_cnt 0 2006.173.15:10:57.92#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.15:10:58.04#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.15:10:58.04#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.15:10:58.04#ibcon#enter wrdev, iclass 27, count 0 2006.173.15:10:58.04#ibcon#first serial, iclass 27, count 0 2006.173.15:10:58.04#ibcon#enter sib2, iclass 27, count 0 2006.173.15:10:58.04#ibcon#flushed, iclass 27, count 0 2006.173.15:10:58.04#ibcon#about to write, iclass 27, count 0 2006.173.15:10:58.04#ibcon#wrote, iclass 27, count 0 2006.173.15:10:58.04#ibcon#about to read 3, iclass 27, count 0 2006.173.15:10:58.06#ibcon#read 3, iclass 27, count 0 2006.173.15:10:58.06#ibcon#about to read 4, iclass 27, count 0 2006.173.15:10:58.06#ibcon#read 4, iclass 27, count 0 2006.173.15:10:58.06#ibcon#about to read 5, iclass 27, count 0 2006.173.15:10:58.06#ibcon#read 5, iclass 27, count 0 2006.173.15:10:58.06#ibcon#about to read 6, iclass 27, count 0 2006.173.15:10:58.06#ibcon#read 6, iclass 27, count 0 2006.173.15:10:58.06#ibcon#end of sib2, iclass 27, count 0 2006.173.15:10:58.06#ibcon#*mode == 0, iclass 27, count 0 2006.173.15:10:58.06#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.15:10:58.06#ibcon#[27=USB\r\n] 2006.173.15:10:58.06#ibcon#*before write, iclass 27, count 0 2006.173.15:10:58.06#ibcon#enter sib2, iclass 27, count 0 2006.173.15:10:58.06#ibcon#flushed, iclass 27, count 0 2006.173.15:10:58.06#ibcon#about to write, iclass 27, count 0 2006.173.15:10:58.06#ibcon#wrote, iclass 27, count 0 2006.173.15:10:58.06#ibcon#about to read 3, iclass 27, count 0 2006.173.15:10:58.09#ibcon#read 3, iclass 27, count 0 2006.173.15:10:58.09#ibcon#about to read 4, iclass 27, count 0 2006.173.15:10:58.09#ibcon#read 4, iclass 27, count 0 2006.173.15:10:58.09#ibcon#about to read 5, iclass 27, count 0 2006.173.15:10:58.09#ibcon#read 5, iclass 27, count 0 2006.173.15:10:58.09#ibcon#about to read 6, iclass 27, count 0 2006.173.15:10:58.09#ibcon#read 6, iclass 27, count 0 2006.173.15:10:58.09#ibcon#end of sib2, iclass 27, count 0 2006.173.15:10:58.09#ibcon#*after write, iclass 27, count 0 2006.173.15:10:58.09#ibcon#*before return 0, iclass 27, count 0 2006.173.15:10:58.09#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.15:10:58.09#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.15:10:58.09#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.15:10:58.09#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.15:10:58.09$vck44/vblo=2,634.99 2006.173.15:10:58.09#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.15:10:58.09#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.15:10:58.09#ibcon#ireg 17 cls_cnt 0 2006.173.15:10:58.09#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.15:10:58.09#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.15:10:58.09#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.15:10:58.09#ibcon#enter wrdev, iclass 29, count 0 2006.173.15:10:58.09#ibcon#first serial, iclass 29, count 0 2006.173.15:10:58.09#ibcon#enter sib2, iclass 29, count 0 2006.173.15:10:58.09#ibcon#flushed, iclass 29, count 0 2006.173.15:10:58.09#ibcon#about to write, iclass 29, count 0 2006.173.15:10:58.09#ibcon#wrote, iclass 29, count 0 2006.173.15:10:58.09#ibcon#about to read 3, iclass 29, count 0 2006.173.15:10:58.11#ibcon#read 3, iclass 29, count 0 2006.173.15:10:58.11#ibcon#about to read 4, iclass 29, count 0 2006.173.15:10:58.11#ibcon#read 4, iclass 29, count 0 2006.173.15:10:58.11#ibcon#about to read 5, iclass 29, count 0 2006.173.15:10:58.11#ibcon#read 5, iclass 29, count 0 2006.173.15:10:58.11#ibcon#about to read 6, iclass 29, count 0 2006.173.15:10:58.11#ibcon#read 6, iclass 29, count 0 2006.173.15:10:58.11#ibcon#end of sib2, iclass 29, count 0 2006.173.15:10:58.11#ibcon#*mode == 0, iclass 29, count 0 2006.173.15:10:58.11#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.15:10:58.11#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.15:10:58.11#ibcon#*before write, iclass 29, count 0 2006.173.15:10:58.11#ibcon#enter sib2, iclass 29, count 0 2006.173.15:10:58.11#ibcon#flushed, iclass 29, count 0 2006.173.15:10:58.11#ibcon#about to write, iclass 29, count 0 2006.173.15:10:58.11#ibcon#wrote, iclass 29, count 0 2006.173.15:10:58.11#ibcon#about to read 3, iclass 29, count 0 2006.173.15:10:58.15#ibcon#read 3, iclass 29, count 0 2006.173.15:10:58.15#ibcon#about to read 4, iclass 29, count 0 2006.173.15:10:58.15#ibcon#read 4, iclass 29, count 0 2006.173.15:10:58.15#ibcon#about to read 5, iclass 29, count 0 2006.173.15:10:58.15#ibcon#read 5, iclass 29, count 0 2006.173.15:10:58.15#ibcon#about to read 6, iclass 29, count 0 2006.173.15:10:58.15#ibcon#read 6, iclass 29, count 0 2006.173.15:10:58.15#ibcon#end of sib2, iclass 29, count 0 2006.173.15:10:58.15#ibcon#*after write, iclass 29, count 0 2006.173.15:10:58.15#ibcon#*before return 0, iclass 29, count 0 2006.173.15:10:58.15#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.15:10:58.15#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.15:10:58.15#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.15:10:58.15#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.15:10:58.15$vck44/vb=2,4 2006.173.15:10:58.15#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.15:10:58.15#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.15:10:58.15#ibcon#ireg 11 cls_cnt 2 2006.173.15:10:58.15#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.15:10:58.21#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.15:10:58.21#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.15:10:58.21#ibcon#enter wrdev, iclass 31, count 2 2006.173.15:10:58.21#ibcon#first serial, iclass 31, count 2 2006.173.15:10:58.21#ibcon#enter sib2, iclass 31, count 2 2006.173.15:10:58.21#ibcon#flushed, iclass 31, count 2 2006.173.15:10:58.21#ibcon#about to write, iclass 31, count 2 2006.173.15:10:58.21#ibcon#wrote, iclass 31, count 2 2006.173.15:10:58.21#ibcon#about to read 3, iclass 31, count 2 2006.173.15:10:58.23#ibcon#read 3, iclass 31, count 2 2006.173.15:10:58.23#ibcon#about to read 4, iclass 31, count 2 2006.173.15:10:58.23#ibcon#read 4, iclass 31, count 2 2006.173.15:10:58.23#ibcon#about to read 5, iclass 31, count 2 2006.173.15:10:58.23#ibcon#read 5, iclass 31, count 2 2006.173.15:10:58.23#ibcon#about to read 6, iclass 31, count 2 2006.173.15:10:58.23#ibcon#read 6, iclass 31, count 2 2006.173.15:10:58.23#ibcon#end of sib2, iclass 31, count 2 2006.173.15:10:58.23#ibcon#*mode == 0, iclass 31, count 2 2006.173.15:10:58.23#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.15:10:58.23#ibcon#[27=AT02-04\r\n] 2006.173.15:10:58.23#ibcon#*before write, iclass 31, count 2 2006.173.15:10:58.23#ibcon#enter sib2, iclass 31, count 2 2006.173.15:10:58.23#ibcon#flushed, iclass 31, count 2 2006.173.15:10:58.23#ibcon#about to write, iclass 31, count 2 2006.173.15:10:58.23#ibcon#wrote, iclass 31, count 2 2006.173.15:10:58.23#ibcon#about to read 3, iclass 31, count 2 2006.173.15:10:58.26#ibcon#read 3, iclass 31, count 2 2006.173.15:10:58.26#ibcon#about to read 4, iclass 31, count 2 2006.173.15:10:58.26#ibcon#read 4, iclass 31, count 2 2006.173.15:10:58.26#ibcon#about to read 5, iclass 31, count 2 2006.173.15:10:58.26#ibcon#read 5, iclass 31, count 2 2006.173.15:10:58.26#ibcon#about to read 6, iclass 31, count 2 2006.173.15:10:58.26#ibcon#read 6, iclass 31, count 2 2006.173.15:10:58.26#ibcon#end of sib2, iclass 31, count 2 2006.173.15:10:58.26#ibcon#*after write, iclass 31, count 2 2006.173.15:10:58.26#ibcon#*before return 0, iclass 31, count 2 2006.173.15:10:58.26#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.15:10:58.26#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.15:10:58.26#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.15:10:58.26#ibcon#ireg 7 cls_cnt 0 2006.173.15:10:58.26#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.15:10:58.38#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.15:10:58.38#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.15:10:58.38#ibcon#enter wrdev, iclass 31, count 0 2006.173.15:10:58.38#ibcon#first serial, iclass 31, count 0 2006.173.15:10:58.38#ibcon#enter sib2, iclass 31, count 0 2006.173.15:10:58.38#ibcon#flushed, iclass 31, count 0 2006.173.15:10:58.38#ibcon#about to write, iclass 31, count 0 2006.173.15:10:58.38#ibcon#wrote, iclass 31, count 0 2006.173.15:10:58.38#ibcon#about to read 3, iclass 31, count 0 2006.173.15:10:58.40#ibcon#read 3, iclass 31, count 0 2006.173.15:10:58.40#ibcon#about to read 4, iclass 31, count 0 2006.173.15:10:58.40#ibcon#read 4, iclass 31, count 0 2006.173.15:10:58.40#ibcon#about to read 5, iclass 31, count 0 2006.173.15:10:58.40#ibcon#read 5, iclass 31, count 0 2006.173.15:10:58.40#ibcon#about to read 6, iclass 31, count 0 2006.173.15:10:58.40#ibcon#read 6, iclass 31, count 0 2006.173.15:10:58.40#ibcon#end of sib2, iclass 31, count 0 2006.173.15:10:58.40#ibcon#*mode == 0, iclass 31, count 0 2006.173.15:10:58.40#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.15:10:58.40#ibcon#[27=USB\r\n] 2006.173.15:10:58.40#ibcon#*before write, iclass 31, count 0 2006.173.15:10:58.40#ibcon#enter sib2, iclass 31, count 0 2006.173.15:10:58.40#ibcon#flushed, iclass 31, count 0 2006.173.15:10:58.40#ibcon#about to write, iclass 31, count 0 2006.173.15:10:58.40#ibcon#wrote, iclass 31, count 0 2006.173.15:10:58.40#ibcon#about to read 3, iclass 31, count 0 2006.173.15:10:58.43#ibcon#read 3, iclass 31, count 0 2006.173.15:10:58.43#ibcon#about to read 4, iclass 31, count 0 2006.173.15:10:58.43#ibcon#read 4, iclass 31, count 0 2006.173.15:10:58.43#ibcon#about to read 5, iclass 31, count 0 2006.173.15:10:58.43#ibcon#read 5, iclass 31, count 0 2006.173.15:10:58.43#ibcon#about to read 6, iclass 31, count 0 2006.173.15:10:58.43#ibcon#read 6, iclass 31, count 0 2006.173.15:10:58.43#ibcon#end of sib2, iclass 31, count 0 2006.173.15:10:58.43#ibcon#*after write, iclass 31, count 0 2006.173.15:10:58.43#ibcon#*before return 0, iclass 31, count 0 2006.173.15:10:58.43#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.15:10:58.43#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.15:10:58.43#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.15:10:58.43#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.15:10:58.43$vck44/vblo=3,649.99 2006.173.15:10:58.43#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.15:10:58.43#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.15:10:58.43#ibcon#ireg 17 cls_cnt 0 2006.173.15:10:58.43#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.15:10:58.43#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.15:10:58.43#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.15:10:58.43#ibcon#enter wrdev, iclass 33, count 0 2006.173.15:10:58.43#ibcon#first serial, iclass 33, count 0 2006.173.15:10:58.43#ibcon#enter sib2, iclass 33, count 0 2006.173.15:10:58.43#ibcon#flushed, iclass 33, count 0 2006.173.15:10:58.43#ibcon#about to write, iclass 33, count 0 2006.173.15:10:58.43#ibcon#wrote, iclass 33, count 0 2006.173.15:10:58.43#ibcon#about to read 3, iclass 33, count 0 2006.173.15:10:58.45#ibcon#read 3, iclass 33, count 0 2006.173.15:10:58.45#ibcon#about to read 4, iclass 33, count 0 2006.173.15:10:58.45#ibcon#read 4, iclass 33, count 0 2006.173.15:10:58.45#ibcon#about to read 5, iclass 33, count 0 2006.173.15:10:58.45#ibcon#read 5, iclass 33, count 0 2006.173.15:10:58.45#ibcon#about to read 6, iclass 33, count 0 2006.173.15:10:58.45#ibcon#read 6, iclass 33, count 0 2006.173.15:10:58.45#ibcon#end of sib2, iclass 33, count 0 2006.173.15:10:58.45#ibcon#*mode == 0, iclass 33, count 0 2006.173.15:10:58.45#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.15:10:58.45#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.15:10:58.45#ibcon#*before write, iclass 33, count 0 2006.173.15:10:58.45#ibcon#enter sib2, iclass 33, count 0 2006.173.15:10:58.45#ibcon#flushed, iclass 33, count 0 2006.173.15:10:58.45#ibcon#about to write, iclass 33, count 0 2006.173.15:10:58.45#ibcon#wrote, iclass 33, count 0 2006.173.15:10:58.45#ibcon#about to read 3, iclass 33, count 0 2006.173.15:10:58.49#ibcon#read 3, iclass 33, count 0 2006.173.15:10:58.49#ibcon#about to read 4, iclass 33, count 0 2006.173.15:10:58.49#ibcon#read 4, iclass 33, count 0 2006.173.15:10:58.49#ibcon#about to read 5, iclass 33, count 0 2006.173.15:10:58.49#ibcon#read 5, iclass 33, count 0 2006.173.15:10:58.49#ibcon#about to read 6, iclass 33, count 0 2006.173.15:10:58.49#ibcon#read 6, iclass 33, count 0 2006.173.15:10:58.49#ibcon#end of sib2, iclass 33, count 0 2006.173.15:10:58.49#ibcon#*after write, iclass 33, count 0 2006.173.15:10:58.49#ibcon#*before return 0, iclass 33, count 0 2006.173.15:10:58.49#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.15:10:58.49#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.15:10:58.49#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.15:10:58.49#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.15:10:58.49$vck44/vb=3,4 2006.173.15:10:58.49#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.15:10:58.49#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.15:10:58.49#ibcon#ireg 11 cls_cnt 2 2006.173.15:10:58.49#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.15:10:58.55#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.15:10:58.55#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.15:10:58.55#ibcon#enter wrdev, iclass 35, count 2 2006.173.15:10:58.55#ibcon#first serial, iclass 35, count 2 2006.173.15:10:58.55#ibcon#enter sib2, iclass 35, count 2 2006.173.15:10:58.55#ibcon#flushed, iclass 35, count 2 2006.173.15:10:58.55#ibcon#about to write, iclass 35, count 2 2006.173.15:10:58.55#ibcon#wrote, iclass 35, count 2 2006.173.15:10:58.55#ibcon#about to read 3, iclass 35, count 2 2006.173.15:10:58.57#ibcon#read 3, iclass 35, count 2 2006.173.15:10:58.57#ibcon#about to read 4, iclass 35, count 2 2006.173.15:10:58.57#ibcon#read 4, iclass 35, count 2 2006.173.15:10:58.57#ibcon#about to read 5, iclass 35, count 2 2006.173.15:10:58.57#ibcon#read 5, iclass 35, count 2 2006.173.15:10:58.57#ibcon#about to read 6, iclass 35, count 2 2006.173.15:10:58.57#ibcon#read 6, iclass 35, count 2 2006.173.15:10:58.57#ibcon#end of sib2, iclass 35, count 2 2006.173.15:10:58.57#ibcon#*mode == 0, iclass 35, count 2 2006.173.15:10:58.57#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.15:10:58.57#ibcon#[27=AT03-04\r\n] 2006.173.15:10:58.57#ibcon#*before write, iclass 35, count 2 2006.173.15:10:58.57#ibcon#enter sib2, iclass 35, count 2 2006.173.15:10:58.57#ibcon#flushed, iclass 35, count 2 2006.173.15:10:58.57#ibcon#about to write, iclass 35, count 2 2006.173.15:10:58.57#ibcon#wrote, iclass 35, count 2 2006.173.15:10:58.57#ibcon#about to read 3, iclass 35, count 2 2006.173.15:10:58.60#ibcon#read 3, iclass 35, count 2 2006.173.15:10:58.60#ibcon#about to read 4, iclass 35, count 2 2006.173.15:10:58.60#ibcon#read 4, iclass 35, count 2 2006.173.15:10:58.60#ibcon#about to read 5, iclass 35, count 2 2006.173.15:10:58.60#ibcon#read 5, iclass 35, count 2 2006.173.15:10:58.60#ibcon#about to read 6, iclass 35, count 2 2006.173.15:10:58.60#ibcon#read 6, iclass 35, count 2 2006.173.15:10:58.60#ibcon#end of sib2, iclass 35, count 2 2006.173.15:10:58.60#ibcon#*after write, iclass 35, count 2 2006.173.15:10:58.60#ibcon#*before return 0, iclass 35, count 2 2006.173.15:10:58.60#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.15:10:58.60#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.15:10:58.60#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.15:10:58.60#ibcon#ireg 7 cls_cnt 0 2006.173.15:10:58.60#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.15:10:58.72#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.15:10:58.72#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.15:10:58.72#ibcon#enter wrdev, iclass 35, count 0 2006.173.15:10:58.72#ibcon#first serial, iclass 35, count 0 2006.173.15:10:58.72#ibcon#enter sib2, iclass 35, count 0 2006.173.15:10:58.72#ibcon#flushed, iclass 35, count 0 2006.173.15:10:58.72#ibcon#about to write, iclass 35, count 0 2006.173.15:10:58.72#ibcon#wrote, iclass 35, count 0 2006.173.15:10:58.72#ibcon#about to read 3, iclass 35, count 0 2006.173.15:10:58.74#ibcon#read 3, iclass 35, count 0 2006.173.15:10:58.74#ibcon#about to read 4, iclass 35, count 0 2006.173.15:10:58.74#ibcon#read 4, iclass 35, count 0 2006.173.15:10:58.74#ibcon#about to read 5, iclass 35, count 0 2006.173.15:10:58.74#ibcon#read 5, iclass 35, count 0 2006.173.15:10:58.74#ibcon#about to read 6, iclass 35, count 0 2006.173.15:10:58.74#ibcon#read 6, iclass 35, count 0 2006.173.15:10:58.74#ibcon#end of sib2, iclass 35, count 0 2006.173.15:10:58.74#ibcon#*mode == 0, iclass 35, count 0 2006.173.15:10:58.74#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.15:10:58.74#ibcon#[27=USB\r\n] 2006.173.15:10:58.74#ibcon#*before write, iclass 35, count 0 2006.173.15:10:58.74#ibcon#enter sib2, iclass 35, count 0 2006.173.15:10:58.74#ibcon#flushed, iclass 35, count 0 2006.173.15:10:58.74#ibcon#about to write, iclass 35, count 0 2006.173.15:10:58.74#ibcon#wrote, iclass 35, count 0 2006.173.15:10:58.74#ibcon#about to read 3, iclass 35, count 0 2006.173.15:10:58.77#ibcon#read 3, iclass 35, count 0 2006.173.15:10:58.77#ibcon#about to read 4, iclass 35, count 0 2006.173.15:10:58.77#ibcon#read 4, iclass 35, count 0 2006.173.15:10:58.77#ibcon#about to read 5, iclass 35, count 0 2006.173.15:10:58.77#ibcon#read 5, iclass 35, count 0 2006.173.15:10:58.77#ibcon#about to read 6, iclass 35, count 0 2006.173.15:10:58.77#ibcon#read 6, iclass 35, count 0 2006.173.15:10:58.77#ibcon#end of sib2, iclass 35, count 0 2006.173.15:10:58.77#ibcon#*after write, iclass 35, count 0 2006.173.15:10:58.77#ibcon#*before return 0, iclass 35, count 0 2006.173.15:10:58.77#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.15:10:58.77#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.15:10:58.77#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.15:10:58.77#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.15:10:58.77$vck44/vblo=4,679.99 2006.173.15:10:58.77#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.15:10:58.77#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.15:10:58.77#ibcon#ireg 17 cls_cnt 0 2006.173.15:10:58.77#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.15:10:58.77#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.15:10:58.77#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.15:10:58.77#ibcon#enter wrdev, iclass 37, count 0 2006.173.15:10:58.77#ibcon#first serial, iclass 37, count 0 2006.173.15:10:58.77#ibcon#enter sib2, iclass 37, count 0 2006.173.15:10:58.77#ibcon#flushed, iclass 37, count 0 2006.173.15:10:58.77#ibcon#about to write, iclass 37, count 0 2006.173.15:10:58.77#ibcon#wrote, iclass 37, count 0 2006.173.15:10:58.77#ibcon#about to read 3, iclass 37, count 0 2006.173.15:10:58.79#ibcon#read 3, iclass 37, count 0 2006.173.15:10:58.79#ibcon#about to read 4, iclass 37, count 0 2006.173.15:10:58.79#ibcon#read 4, iclass 37, count 0 2006.173.15:10:58.79#ibcon#about to read 5, iclass 37, count 0 2006.173.15:10:58.79#ibcon#read 5, iclass 37, count 0 2006.173.15:10:58.79#ibcon#about to read 6, iclass 37, count 0 2006.173.15:10:58.79#ibcon#read 6, iclass 37, count 0 2006.173.15:10:58.79#ibcon#end of sib2, iclass 37, count 0 2006.173.15:10:58.79#ibcon#*mode == 0, iclass 37, count 0 2006.173.15:10:58.79#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.15:10:58.79#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.15:10:58.79#ibcon#*before write, iclass 37, count 0 2006.173.15:10:58.79#ibcon#enter sib2, iclass 37, count 0 2006.173.15:10:58.79#ibcon#flushed, iclass 37, count 0 2006.173.15:10:58.79#ibcon#about to write, iclass 37, count 0 2006.173.15:10:58.79#ibcon#wrote, iclass 37, count 0 2006.173.15:10:58.79#ibcon#about to read 3, iclass 37, count 0 2006.173.15:10:58.83#ibcon#read 3, iclass 37, count 0 2006.173.15:10:58.83#ibcon#about to read 4, iclass 37, count 0 2006.173.15:10:58.83#ibcon#read 4, iclass 37, count 0 2006.173.15:10:58.83#ibcon#about to read 5, iclass 37, count 0 2006.173.15:10:58.83#ibcon#read 5, iclass 37, count 0 2006.173.15:10:58.83#ibcon#about to read 6, iclass 37, count 0 2006.173.15:10:58.83#ibcon#read 6, iclass 37, count 0 2006.173.15:10:58.83#ibcon#end of sib2, iclass 37, count 0 2006.173.15:10:58.83#ibcon#*after write, iclass 37, count 0 2006.173.15:10:58.83#ibcon#*before return 0, iclass 37, count 0 2006.173.15:10:58.83#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.15:10:58.83#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.15:10:58.83#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.15:10:58.83#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.15:10:58.83$vck44/vb=4,4 2006.173.15:10:58.83#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.15:10:58.83#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.15:10:58.83#ibcon#ireg 11 cls_cnt 2 2006.173.15:10:58.83#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.15:10:58.89#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.15:10:58.89#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.15:10:58.89#ibcon#enter wrdev, iclass 39, count 2 2006.173.15:10:58.89#ibcon#first serial, iclass 39, count 2 2006.173.15:10:58.89#ibcon#enter sib2, iclass 39, count 2 2006.173.15:10:58.89#ibcon#flushed, iclass 39, count 2 2006.173.15:10:58.89#ibcon#about to write, iclass 39, count 2 2006.173.15:10:58.89#ibcon#wrote, iclass 39, count 2 2006.173.15:10:58.89#ibcon#about to read 3, iclass 39, count 2 2006.173.15:10:58.91#ibcon#read 3, iclass 39, count 2 2006.173.15:10:58.91#ibcon#about to read 4, iclass 39, count 2 2006.173.15:10:58.91#ibcon#read 4, iclass 39, count 2 2006.173.15:10:58.91#ibcon#about to read 5, iclass 39, count 2 2006.173.15:10:58.91#ibcon#read 5, iclass 39, count 2 2006.173.15:10:58.91#ibcon#about to read 6, iclass 39, count 2 2006.173.15:10:58.91#ibcon#read 6, iclass 39, count 2 2006.173.15:10:58.91#ibcon#end of sib2, iclass 39, count 2 2006.173.15:10:58.91#ibcon#*mode == 0, iclass 39, count 2 2006.173.15:10:58.91#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.15:10:58.91#ibcon#[27=AT04-04\r\n] 2006.173.15:10:58.91#ibcon#*before write, iclass 39, count 2 2006.173.15:10:58.91#ibcon#enter sib2, iclass 39, count 2 2006.173.15:10:58.91#ibcon#flushed, iclass 39, count 2 2006.173.15:10:58.91#ibcon#about to write, iclass 39, count 2 2006.173.15:10:58.91#ibcon#wrote, iclass 39, count 2 2006.173.15:10:58.91#ibcon#about to read 3, iclass 39, count 2 2006.173.15:10:58.94#ibcon#read 3, iclass 39, count 2 2006.173.15:10:58.94#ibcon#about to read 4, iclass 39, count 2 2006.173.15:10:58.94#ibcon#read 4, iclass 39, count 2 2006.173.15:10:58.94#ibcon#about to read 5, iclass 39, count 2 2006.173.15:10:58.94#ibcon#read 5, iclass 39, count 2 2006.173.15:10:58.94#ibcon#about to read 6, iclass 39, count 2 2006.173.15:10:58.94#ibcon#read 6, iclass 39, count 2 2006.173.15:10:58.94#ibcon#end of sib2, iclass 39, count 2 2006.173.15:10:58.94#ibcon#*after write, iclass 39, count 2 2006.173.15:10:58.94#ibcon#*before return 0, iclass 39, count 2 2006.173.15:10:58.94#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.15:10:58.94#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.15:10:58.94#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.15:10:58.94#ibcon#ireg 7 cls_cnt 0 2006.173.15:10:58.94#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.15:10:59.06#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.15:10:59.06#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.15:10:59.06#ibcon#enter wrdev, iclass 39, count 0 2006.173.15:10:59.06#ibcon#first serial, iclass 39, count 0 2006.173.15:10:59.06#ibcon#enter sib2, iclass 39, count 0 2006.173.15:10:59.06#ibcon#flushed, iclass 39, count 0 2006.173.15:10:59.06#ibcon#about to write, iclass 39, count 0 2006.173.15:10:59.06#ibcon#wrote, iclass 39, count 0 2006.173.15:10:59.06#ibcon#about to read 3, iclass 39, count 0 2006.173.15:10:59.08#ibcon#read 3, iclass 39, count 0 2006.173.15:10:59.08#ibcon#about to read 4, iclass 39, count 0 2006.173.15:10:59.08#ibcon#read 4, iclass 39, count 0 2006.173.15:10:59.08#ibcon#about to read 5, iclass 39, count 0 2006.173.15:10:59.08#ibcon#read 5, iclass 39, count 0 2006.173.15:10:59.08#ibcon#about to read 6, iclass 39, count 0 2006.173.15:10:59.08#ibcon#read 6, iclass 39, count 0 2006.173.15:10:59.08#ibcon#end of sib2, iclass 39, count 0 2006.173.15:10:59.08#ibcon#*mode == 0, iclass 39, count 0 2006.173.15:10:59.08#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.15:10:59.08#ibcon#[27=USB\r\n] 2006.173.15:10:59.08#ibcon#*before write, iclass 39, count 0 2006.173.15:10:59.08#ibcon#enter sib2, iclass 39, count 0 2006.173.15:10:59.08#ibcon#flushed, iclass 39, count 0 2006.173.15:10:59.08#ibcon#about to write, iclass 39, count 0 2006.173.15:10:59.08#ibcon#wrote, iclass 39, count 0 2006.173.15:10:59.08#ibcon#about to read 3, iclass 39, count 0 2006.173.15:10:59.11#ibcon#read 3, iclass 39, count 0 2006.173.15:10:59.11#ibcon#about to read 4, iclass 39, count 0 2006.173.15:10:59.11#ibcon#read 4, iclass 39, count 0 2006.173.15:10:59.11#ibcon#about to read 5, iclass 39, count 0 2006.173.15:10:59.11#ibcon#read 5, iclass 39, count 0 2006.173.15:10:59.11#ibcon#about to read 6, iclass 39, count 0 2006.173.15:10:59.11#ibcon#read 6, iclass 39, count 0 2006.173.15:10:59.11#ibcon#end of sib2, iclass 39, count 0 2006.173.15:10:59.11#ibcon#*after write, iclass 39, count 0 2006.173.15:10:59.11#ibcon#*before return 0, iclass 39, count 0 2006.173.15:10:59.11#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.15:10:59.11#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.15:10:59.11#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.15:10:59.11#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.15:10:59.11$vck44/vblo=5,709.99 2006.173.15:10:59.11#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.15:10:59.11#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.15:10:59.11#ibcon#ireg 17 cls_cnt 0 2006.173.15:10:59.11#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.15:10:59.11#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.15:10:59.11#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.15:10:59.11#ibcon#enter wrdev, iclass 3, count 0 2006.173.15:10:59.11#ibcon#first serial, iclass 3, count 0 2006.173.15:10:59.11#ibcon#enter sib2, iclass 3, count 0 2006.173.15:10:59.11#ibcon#flushed, iclass 3, count 0 2006.173.15:10:59.11#ibcon#about to write, iclass 3, count 0 2006.173.15:10:59.11#ibcon#wrote, iclass 3, count 0 2006.173.15:10:59.11#ibcon#about to read 3, iclass 3, count 0 2006.173.15:10:59.13#ibcon#read 3, iclass 3, count 0 2006.173.15:10:59.13#ibcon#about to read 4, iclass 3, count 0 2006.173.15:10:59.13#ibcon#read 4, iclass 3, count 0 2006.173.15:10:59.13#ibcon#about to read 5, iclass 3, count 0 2006.173.15:10:59.13#ibcon#read 5, iclass 3, count 0 2006.173.15:10:59.13#ibcon#about to read 6, iclass 3, count 0 2006.173.15:10:59.13#ibcon#read 6, iclass 3, count 0 2006.173.15:10:59.13#ibcon#end of sib2, iclass 3, count 0 2006.173.15:10:59.13#ibcon#*mode == 0, iclass 3, count 0 2006.173.15:10:59.13#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.15:10:59.13#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.15:10:59.13#ibcon#*before write, iclass 3, count 0 2006.173.15:10:59.13#ibcon#enter sib2, iclass 3, count 0 2006.173.15:10:59.13#ibcon#flushed, iclass 3, count 0 2006.173.15:10:59.13#ibcon#about to write, iclass 3, count 0 2006.173.15:10:59.13#ibcon#wrote, iclass 3, count 0 2006.173.15:10:59.13#ibcon#about to read 3, iclass 3, count 0 2006.173.15:10:59.17#ibcon#read 3, iclass 3, count 0 2006.173.15:10:59.17#ibcon#about to read 4, iclass 3, count 0 2006.173.15:10:59.17#ibcon#read 4, iclass 3, count 0 2006.173.15:10:59.17#ibcon#about to read 5, iclass 3, count 0 2006.173.15:10:59.17#ibcon#read 5, iclass 3, count 0 2006.173.15:10:59.17#ibcon#about to read 6, iclass 3, count 0 2006.173.15:10:59.17#ibcon#read 6, iclass 3, count 0 2006.173.15:10:59.17#ibcon#end of sib2, iclass 3, count 0 2006.173.15:10:59.17#ibcon#*after write, iclass 3, count 0 2006.173.15:10:59.17#ibcon#*before return 0, iclass 3, count 0 2006.173.15:10:59.17#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.15:10:59.17#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.15:10:59.17#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.15:10:59.17#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.15:10:59.17$vck44/vb=5,4 2006.173.15:10:59.17#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.15:10:59.17#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.15:10:59.17#ibcon#ireg 11 cls_cnt 2 2006.173.15:10:59.17#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.15:10:59.23#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.15:10:59.23#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.15:10:59.23#ibcon#enter wrdev, iclass 5, count 2 2006.173.15:10:59.23#ibcon#first serial, iclass 5, count 2 2006.173.15:10:59.23#ibcon#enter sib2, iclass 5, count 2 2006.173.15:10:59.23#ibcon#flushed, iclass 5, count 2 2006.173.15:10:59.23#ibcon#about to write, iclass 5, count 2 2006.173.15:10:59.23#ibcon#wrote, iclass 5, count 2 2006.173.15:10:59.23#ibcon#about to read 3, iclass 5, count 2 2006.173.15:10:59.25#ibcon#read 3, iclass 5, count 2 2006.173.15:10:59.25#ibcon#about to read 4, iclass 5, count 2 2006.173.15:10:59.25#ibcon#read 4, iclass 5, count 2 2006.173.15:10:59.25#ibcon#about to read 5, iclass 5, count 2 2006.173.15:10:59.25#ibcon#read 5, iclass 5, count 2 2006.173.15:10:59.25#ibcon#about to read 6, iclass 5, count 2 2006.173.15:10:59.25#ibcon#read 6, iclass 5, count 2 2006.173.15:10:59.25#ibcon#end of sib2, iclass 5, count 2 2006.173.15:10:59.25#ibcon#*mode == 0, iclass 5, count 2 2006.173.15:10:59.25#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.15:10:59.25#ibcon#[27=AT05-04\r\n] 2006.173.15:10:59.25#ibcon#*before write, iclass 5, count 2 2006.173.15:10:59.25#ibcon#enter sib2, iclass 5, count 2 2006.173.15:10:59.25#ibcon#flushed, iclass 5, count 2 2006.173.15:10:59.25#ibcon#about to write, iclass 5, count 2 2006.173.15:10:59.25#ibcon#wrote, iclass 5, count 2 2006.173.15:10:59.25#ibcon#about to read 3, iclass 5, count 2 2006.173.15:10:59.28#ibcon#read 3, iclass 5, count 2 2006.173.15:10:59.28#ibcon#about to read 4, iclass 5, count 2 2006.173.15:10:59.28#ibcon#read 4, iclass 5, count 2 2006.173.15:10:59.28#ibcon#about to read 5, iclass 5, count 2 2006.173.15:10:59.28#ibcon#read 5, iclass 5, count 2 2006.173.15:10:59.28#ibcon#about to read 6, iclass 5, count 2 2006.173.15:10:59.28#ibcon#read 6, iclass 5, count 2 2006.173.15:10:59.28#ibcon#end of sib2, iclass 5, count 2 2006.173.15:10:59.28#ibcon#*after write, iclass 5, count 2 2006.173.15:10:59.28#ibcon#*before return 0, iclass 5, count 2 2006.173.15:10:59.28#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.15:10:59.28#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.15:10:59.28#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.15:10:59.28#ibcon#ireg 7 cls_cnt 0 2006.173.15:10:59.28#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.15:10:59.40#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.15:10:59.40#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.15:10:59.40#ibcon#enter wrdev, iclass 5, count 0 2006.173.15:10:59.40#ibcon#first serial, iclass 5, count 0 2006.173.15:10:59.40#ibcon#enter sib2, iclass 5, count 0 2006.173.15:10:59.40#ibcon#flushed, iclass 5, count 0 2006.173.15:10:59.40#ibcon#about to write, iclass 5, count 0 2006.173.15:10:59.40#ibcon#wrote, iclass 5, count 0 2006.173.15:10:59.40#ibcon#about to read 3, iclass 5, count 0 2006.173.15:10:59.42#ibcon#read 3, iclass 5, count 0 2006.173.15:10:59.42#ibcon#about to read 4, iclass 5, count 0 2006.173.15:10:59.42#ibcon#read 4, iclass 5, count 0 2006.173.15:10:59.42#ibcon#about to read 5, iclass 5, count 0 2006.173.15:10:59.42#ibcon#read 5, iclass 5, count 0 2006.173.15:10:59.42#ibcon#about to read 6, iclass 5, count 0 2006.173.15:10:59.42#ibcon#read 6, iclass 5, count 0 2006.173.15:10:59.42#ibcon#end of sib2, iclass 5, count 0 2006.173.15:10:59.42#ibcon#*mode == 0, iclass 5, count 0 2006.173.15:10:59.42#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.15:10:59.42#ibcon#[27=USB\r\n] 2006.173.15:10:59.42#ibcon#*before write, iclass 5, count 0 2006.173.15:10:59.42#ibcon#enter sib2, iclass 5, count 0 2006.173.15:10:59.42#ibcon#flushed, iclass 5, count 0 2006.173.15:10:59.42#ibcon#about to write, iclass 5, count 0 2006.173.15:10:59.42#ibcon#wrote, iclass 5, count 0 2006.173.15:10:59.42#ibcon#about to read 3, iclass 5, count 0 2006.173.15:10:59.45#ibcon#read 3, iclass 5, count 0 2006.173.15:10:59.45#ibcon#about to read 4, iclass 5, count 0 2006.173.15:10:59.45#ibcon#read 4, iclass 5, count 0 2006.173.15:10:59.45#ibcon#about to read 5, iclass 5, count 0 2006.173.15:10:59.45#ibcon#read 5, iclass 5, count 0 2006.173.15:10:59.45#ibcon#about to read 6, iclass 5, count 0 2006.173.15:10:59.45#ibcon#read 6, iclass 5, count 0 2006.173.15:10:59.45#ibcon#end of sib2, iclass 5, count 0 2006.173.15:10:59.45#ibcon#*after write, iclass 5, count 0 2006.173.15:10:59.45#ibcon#*before return 0, iclass 5, count 0 2006.173.15:10:59.45#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.15:10:59.45#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.15:10:59.45#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.15:10:59.45#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.15:10:59.45$vck44/vblo=6,719.99 2006.173.15:10:59.45#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.15:10:59.45#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.15:10:59.45#ibcon#ireg 17 cls_cnt 0 2006.173.15:10:59.45#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.15:10:59.45#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.15:10:59.45#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.15:10:59.45#ibcon#enter wrdev, iclass 7, count 0 2006.173.15:10:59.45#ibcon#first serial, iclass 7, count 0 2006.173.15:10:59.45#ibcon#enter sib2, iclass 7, count 0 2006.173.15:10:59.45#ibcon#flushed, iclass 7, count 0 2006.173.15:10:59.45#ibcon#about to write, iclass 7, count 0 2006.173.15:10:59.45#ibcon#wrote, iclass 7, count 0 2006.173.15:10:59.45#ibcon#about to read 3, iclass 7, count 0 2006.173.15:10:59.47#ibcon#read 3, iclass 7, count 0 2006.173.15:10:59.47#ibcon#about to read 4, iclass 7, count 0 2006.173.15:10:59.47#ibcon#read 4, iclass 7, count 0 2006.173.15:10:59.47#ibcon#about to read 5, iclass 7, count 0 2006.173.15:10:59.47#ibcon#read 5, iclass 7, count 0 2006.173.15:10:59.47#ibcon#about to read 6, iclass 7, count 0 2006.173.15:10:59.47#ibcon#read 6, iclass 7, count 0 2006.173.15:10:59.47#ibcon#end of sib2, iclass 7, count 0 2006.173.15:10:59.47#ibcon#*mode == 0, iclass 7, count 0 2006.173.15:10:59.47#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.15:10:59.47#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.15:10:59.47#ibcon#*before write, iclass 7, count 0 2006.173.15:10:59.47#ibcon#enter sib2, iclass 7, count 0 2006.173.15:10:59.47#ibcon#flushed, iclass 7, count 0 2006.173.15:10:59.47#ibcon#about to write, iclass 7, count 0 2006.173.15:10:59.47#ibcon#wrote, iclass 7, count 0 2006.173.15:10:59.47#ibcon#about to read 3, iclass 7, count 0 2006.173.15:10:59.51#ibcon#read 3, iclass 7, count 0 2006.173.15:10:59.51#ibcon#about to read 4, iclass 7, count 0 2006.173.15:10:59.51#ibcon#read 4, iclass 7, count 0 2006.173.15:10:59.51#ibcon#about to read 5, iclass 7, count 0 2006.173.15:10:59.51#ibcon#read 5, iclass 7, count 0 2006.173.15:10:59.51#ibcon#about to read 6, iclass 7, count 0 2006.173.15:10:59.51#ibcon#read 6, iclass 7, count 0 2006.173.15:10:59.51#ibcon#end of sib2, iclass 7, count 0 2006.173.15:10:59.51#ibcon#*after write, iclass 7, count 0 2006.173.15:10:59.51#ibcon#*before return 0, iclass 7, count 0 2006.173.15:10:59.51#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.15:10:59.51#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.15:10:59.51#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.15:10:59.51#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.15:10:59.51$vck44/vb=6,4 2006.173.15:10:59.51#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.15:10:59.51#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.15:10:59.51#ibcon#ireg 11 cls_cnt 2 2006.173.15:10:59.51#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.15:10:59.57#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.15:10:59.57#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.15:10:59.57#ibcon#enter wrdev, iclass 11, count 2 2006.173.15:10:59.57#ibcon#first serial, iclass 11, count 2 2006.173.15:10:59.57#ibcon#enter sib2, iclass 11, count 2 2006.173.15:10:59.57#ibcon#flushed, iclass 11, count 2 2006.173.15:10:59.57#ibcon#about to write, iclass 11, count 2 2006.173.15:10:59.57#ibcon#wrote, iclass 11, count 2 2006.173.15:10:59.57#ibcon#about to read 3, iclass 11, count 2 2006.173.15:10:59.59#ibcon#read 3, iclass 11, count 2 2006.173.15:10:59.59#ibcon#about to read 4, iclass 11, count 2 2006.173.15:10:59.59#ibcon#read 4, iclass 11, count 2 2006.173.15:10:59.59#ibcon#about to read 5, iclass 11, count 2 2006.173.15:10:59.59#ibcon#read 5, iclass 11, count 2 2006.173.15:10:59.59#ibcon#about to read 6, iclass 11, count 2 2006.173.15:10:59.59#ibcon#read 6, iclass 11, count 2 2006.173.15:10:59.59#ibcon#end of sib2, iclass 11, count 2 2006.173.15:10:59.59#ibcon#*mode == 0, iclass 11, count 2 2006.173.15:10:59.59#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.15:10:59.59#ibcon#[27=AT06-04\r\n] 2006.173.15:10:59.59#ibcon#*before write, iclass 11, count 2 2006.173.15:10:59.59#ibcon#enter sib2, iclass 11, count 2 2006.173.15:10:59.59#ibcon#flushed, iclass 11, count 2 2006.173.15:10:59.59#ibcon#about to write, iclass 11, count 2 2006.173.15:10:59.59#ibcon#wrote, iclass 11, count 2 2006.173.15:10:59.59#ibcon#about to read 3, iclass 11, count 2 2006.173.15:10:59.62#ibcon#read 3, iclass 11, count 2 2006.173.15:10:59.62#ibcon#about to read 4, iclass 11, count 2 2006.173.15:10:59.62#ibcon#read 4, iclass 11, count 2 2006.173.15:10:59.62#ibcon#about to read 5, iclass 11, count 2 2006.173.15:10:59.62#ibcon#read 5, iclass 11, count 2 2006.173.15:10:59.62#ibcon#about to read 6, iclass 11, count 2 2006.173.15:10:59.62#ibcon#read 6, iclass 11, count 2 2006.173.15:10:59.62#ibcon#end of sib2, iclass 11, count 2 2006.173.15:10:59.62#ibcon#*after write, iclass 11, count 2 2006.173.15:10:59.62#ibcon#*before return 0, iclass 11, count 2 2006.173.15:10:59.62#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.15:10:59.62#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.15:10:59.62#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.15:10:59.62#ibcon#ireg 7 cls_cnt 0 2006.173.15:10:59.62#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.15:10:59.74#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.15:10:59.74#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.15:10:59.74#ibcon#enter wrdev, iclass 11, count 0 2006.173.15:10:59.74#ibcon#first serial, iclass 11, count 0 2006.173.15:10:59.74#ibcon#enter sib2, iclass 11, count 0 2006.173.15:10:59.74#ibcon#flushed, iclass 11, count 0 2006.173.15:10:59.74#ibcon#about to write, iclass 11, count 0 2006.173.15:10:59.74#ibcon#wrote, iclass 11, count 0 2006.173.15:10:59.74#ibcon#about to read 3, iclass 11, count 0 2006.173.15:10:59.76#ibcon#read 3, iclass 11, count 0 2006.173.15:10:59.76#ibcon#about to read 4, iclass 11, count 0 2006.173.15:10:59.76#ibcon#read 4, iclass 11, count 0 2006.173.15:10:59.76#ibcon#about to read 5, iclass 11, count 0 2006.173.15:10:59.76#ibcon#read 5, iclass 11, count 0 2006.173.15:10:59.76#ibcon#about to read 6, iclass 11, count 0 2006.173.15:10:59.76#ibcon#read 6, iclass 11, count 0 2006.173.15:10:59.76#ibcon#end of sib2, iclass 11, count 0 2006.173.15:10:59.76#ibcon#*mode == 0, iclass 11, count 0 2006.173.15:10:59.76#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.15:10:59.76#ibcon#[27=USB\r\n] 2006.173.15:10:59.76#ibcon#*before write, iclass 11, count 0 2006.173.15:10:59.76#ibcon#enter sib2, iclass 11, count 0 2006.173.15:10:59.76#ibcon#flushed, iclass 11, count 0 2006.173.15:10:59.76#ibcon#about to write, iclass 11, count 0 2006.173.15:10:59.76#ibcon#wrote, iclass 11, count 0 2006.173.15:10:59.76#ibcon#about to read 3, iclass 11, count 0 2006.173.15:10:59.79#ibcon#read 3, iclass 11, count 0 2006.173.15:10:59.79#ibcon#about to read 4, iclass 11, count 0 2006.173.15:10:59.79#ibcon#read 4, iclass 11, count 0 2006.173.15:10:59.79#ibcon#about to read 5, iclass 11, count 0 2006.173.15:10:59.79#ibcon#read 5, iclass 11, count 0 2006.173.15:10:59.79#ibcon#about to read 6, iclass 11, count 0 2006.173.15:10:59.79#ibcon#read 6, iclass 11, count 0 2006.173.15:10:59.79#ibcon#end of sib2, iclass 11, count 0 2006.173.15:10:59.79#ibcon#*after write, iclass 11, count 0 2006.173.15:10:59.79#ibcon#*before return 0, iclass 11, count 0 2006.173.15:10:59.79#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.15:10:59.79#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.15:10:59.79#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.15:10:59.79#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.15:10:59.79$vck44/vblo=7,734.99 2006.173.15:10:59.79#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.15:10:59.79#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.15:10:59.79#ibcon#ireg 17 cls_cnt 0 2006.173.15:10:59.79#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.15:10:59.79#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.15:10:59.79#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.15:10:59.79#ibcon#enter wrdev, iclass 13, count 0 2006.173.15:10:59.79#ibcon#first serial, iclass 13, count 0 2006.173.15:10:59.79#ibcon#enter sib2, iclass 13, count 0 2006.173.15:10:59.79#ibcon#flushed, iclass 13, count 0 2006.173.15:10:59.79#ibcon#about to write, iclass 13, count 0 2006.173.15:10:59.79#ibcon#wrote, iclass 13, count 0 2006.173.15:10:59.79#ibcon#about to read 3, iclass 13, count 0 2006.173.15:10:59.81#ibcon#read 3, iclass 13, count 0 2006.173.15:10:59.81#ibcon#about to read 4, iclass 13, count 0 2006.173.15:10:59.81#ibcon#read 4, iclass 13, count 0 2006.173.15:10:59.81#ibcon#about to read 5, iclass 13, count 0 2006.173.15:10:59.81#ibcon#read 5, iclass 13, count 0 2006.173.15:10:59.81#ibcon#about to read 6, iclass 13, count 0 2006.173.15:10:59.81#ibcon#read 6, iclass 13, count 0 2006.173.15:10:59.81#ibcon#end of sib2, iclass 13, count 0 2006.173.15:10:59.81#ibcon#*mode == 0, iclass 13, count 0 2006.173.15:10:59.81#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.15:10:59.81#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.15:10:59.81#ibcon#*before write, iclass 13, count 0 2006.173.15:10:59.81#ibcon#enter sib2, iclass 13, count 0 2006.173.15:10:59.81#ibcon#flushed, iclass 13, count 0 2006.173.15:10:59.81#ibcon#about to write, iclass 13, count 0 2006.173.15:10:59.81#ibcon#wrote, iclass 13, count 0 2006.173.15:10:59.81#ibcon#about to read 3, iclass 13, count 0 2006.173.15:10:59.85#ibcon#read 3, iclass 13, count 0 2006.173.15:10:59.85#ibcon#about to read 4, iclass 13, count 0 2006.173.15:10:59.85#ibcon#read 4, iclass 13, count 0 2006.173.15:10:59.85#ibcon#about to read 5, iclass 13, count 0 2006.173.15:10:59.85#ibcon#read 5, iclass 13, count 0 2006.173.15:10:59.85#ibcon#about to read 6, iclass 13, count 0 2006.173.15:10:59.85#ibcon#read 6, iclass 13, count 0 2006.173.15:10:59.85#ibcon#end of sib2, iclass 13, count 0 2006.173.15:10:59.85#ibcon#*after write, iclass 13, count 0 2006.173.15:10:59.85#ibcon#*before return 0, iclass 13, count 0 2006.173.15:10:59.85#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.15:10:59.85#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.15:10:59.85#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.15:10:59.85#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.15:10:59.85$vck44/vb=7,4 2006.173.15:10:59.85#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.15:10:59.85#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.15:10:59.85#ibcon#ireg 11 cls_cnt 2 2006.173.15:10:59.85#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.15:10:59.91#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.15:10:59.91#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.15:10:59.91#ibcon#enter wrdev, iclass 15, count 2 2006.173.15:10:59.91#ibcon#first serial, iclass 15, count 2 2006.173.15:10:59.91#ibcon#enter sib2, iclass 15, count 2 2006.173.15:10:59.91#ibcon#flushed, iclass 15, count 2 2006.173.15:10:59.91#ibcon#about to write, iclass 15, count 2 2006.173.15:10:59.91#ibcon#wrote, iclass 15, count 2 2006.173.15:10:59.91#ibcon#about to read 3, iclass 15, count 2 2006.173.15:10:59.93#ibcon#read 3, iclass 15, count 2 2006.173.15:10:59.93#ibcon#about to read 4, iclass 15, count 2 2006.173.15:10:59.93#ibcon#read 4, iclass 15, count 2 2006.173.15:10:59.93#ibcon#about to read 5, iclass 15, count 2 2006.173.15:10:59.93#ibcon#read 5, iclass 15, count 2 2006.173.15:10:59.93#ibcon#about to read 6, iclass 15, count 2 2006.173.15:10:59.93#ibcon#read 6, iclass 15, count 2 2006.173.15:10:59.93#ibcon#end of sib2, iclass 15, count 2 2006.173.15:10:59.93#ibcon#*mode == 0, iclass 15, count 2 2006.173.15:10:59.93#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.15:10:59.93#ibcon#[27=AT07-04\r\n] 2006.173.15:10:59.93#ibcon#*before write, iclass 15, count 2 2006.173.15:10:59.93#ibcon#enter sib2, iclass 15, count 2 2006.173.15:10:59.93#ibcon#flushed, iclass 15, count 2 2006.173.15:10:59.93#ibcon#about to write, iclass 15, count 2 2006.173.15:10:59.93#ibcon#wrote, iclass 15, count 2 2006.173.15:10:59.93#ibcon#about to read 3, iclass 15, count 2 2006.173.15:10:59.96#ibcon#read 3, iclass 15, count 2 2006.173.15:10:59.96#ibcon#about to read 4, iclass 15, count 2 2006.173.15:10:59.96#ibcon#read 4, iclass 15, count 2 2006.173.15:10:59.96#ibcon#about to read 5, iclass 15, count 2 2006.173.15:10:59.96#ibcon#read 5, iclass 15, count 2 2006.173.15:10:59.96#ibcon#about to read 6, iclass 15, count 2 2006.173.15:10:59.96#ibcon#read 6, iclass 15, count 2 2006.173.15:10:59.96#ibcon#end of sib2, iclass 15, count 2 2006.173.15:10:59.96#ibcon#*after write, iclass 15, count 2 2006.173.15:10:59.96#ibcon#*before return 0, iclass 15, count 2 2006.173.15:10:59.96#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.15:10:59.96#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.15:10:59.96#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.15:10:59.96#ibcon#ireg 7 cls_cnt 0 2006.173.15:10:59.96#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.15:11:00.08#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.15:11:00.08#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.15:11:00.08#ibcon#enter wrdev, iclass 15, count 0 2006.173.15:11:00.08#ibcon#first serial, iclass 15, count 0 2006.173.15:11:00.08#ibcon#enter sib2, iclass 15, count 0 2006.173.15:11:00.08#ibcon#flushed, iclass 15, count 0 2006.173.15:11:00.08#ibcon#about to write, iclass 15, count 0 2006.173.15:11:00.08#ibcon#wrote, iclass 15, count 0 2006.173.15:11:00.08#ibcon#about to read 3, iclass 15, count 0 2006.173.15:11:00.10#ibcon#read 3, iclass 15, count 0 2006.173.15:11:00.10#ibcon#about to read 4, iclass 15, count 0 2006.173.15:11:00.10#ibcon#read 4, iclass 15, count 0 2006.173.15:11:00.10#ibcon#about to read 5, iclass 15, count 0 2006.173.15:11:00.10#ibcon#read 5, iclass 15, count 0 2006.173.15:11:00.10#ibcon#about to read 6, iclass 15, count 0 2006.173.15:11:00.10#ibcon#read 6, iclass 15, count 0 2006.173.15:11:00.10#ibcon#end of sib2, iclass 15, count 0 2006.173.15:11:00.10#ibcon#*mode == 0, iclass 15, count 0 2006.173.15:11:00.10#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.15:11:00.10#ibcon#[27=USB\r\n] 2006.173.15:11:00.10#ibcon#*before write, iclass 15, count 0 2006.173.15:11:00.10#ibcon#enter sib2, iclass 15, count 0 2006.173.15:11:00.10#ibcon#flushed, iclass 15, count 0 2006.173.15:11:00.10#ibcon#about to write, iclass 15, count 0 2006.173.15:11:00.10#ibcon#wrote, iclass 15, count 0 2006.173.15:11:00.10#ibcon#about to read 3, iclass 15, count 0 2006.173.15:11:00.13#ibcon#read 3, iclass 15, count 0 2006.173.15:11:00.13#ibcon#about to read 4, iclass 15, count 0 2006.173.15:11:00.13#ibcon#read 4, iclass 15, count 0 2006.173.15:11:00.13#ibcon#about to read 5, iclass 15, count 0 2006.173.15:11:00.13#ibcon#read 5, iclass 15, count 0 2006.173.15:11:00.13#ibcon#about to read 6, iclass 15, count 0 2006.173.15:11:00.13#ibcon#read 6, iclass 15, count 0 2006.173.15:11:00.13#ibcon#end of sib2, iclass 15, count 0 2006.173.15:11:00.13#ibcon#*after write, iclass 15, count 0 2006.173.15:11:00.13#ibcon#*before return 0, iclass 15, count 0 2006.173.15:11:00.13#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.15:11:00.13#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.15:11:00.13#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.15:11:00.13#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.15:11:00.13$vck44/vblo=8,744.99 2006.173.15:11:00.13#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.15:11:00.13#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.15:11:00.13#ibcon#ireg 17 cls_cnt 0 2006.173.15:11:00.13#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.15:11:00.13#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.15:11:00.13#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.15:11:00.13#ibcon#enter wrdev, iclass 17, count 0 2006.173.15:11:00.13#ibcon#first serial, iclass 17, count 0 2006.173.15:11:00.13#ibcon#enter sib2, iclass 17, count 0 2006.173.15:11:00.13#ibcon#flushed, iclass 17, count 0 2006.173.15:11:00.13#ibcon#about to write, iclass 17, count 0 2006.173.15:11:00.13#ibcon#wrote, iclass 17, count 0 2006.173.15:11:00.13#ibcon#about to read 3, iclass 17, count 0 2006.173.15:11:00.15#ibcon#read 3, iclass 17, count 0 2006.173.15:11:00.15#ibcon#about to read 4, iclass 17, count 0 2006.173.15:11:00.15#ibcon#read 4, iclass 17, count 0 2006.173.15:11:00.15#ibcon#about to read 5, iclass 17, count 0 2006.173.15:11:00.15#ibcon#read 5, iclass 17, count 0 2006.173.15:11:00.15#ibcon#about to read 6, iclass 17, count 0 2006.173.15:11:00.15#ibcon#read 6, iclass 17, count 0 2006.173.15:11:00.15#ibcon#end of sib2, iclass 17, count 0 2006.173.15:11:00.15#ibcon#*mode == 0, iclass 17, count 0 2006.173.15:11:00.15#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.15:11:00.15#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.15:11:00.15#ibcon#*before write, iclass 17, count 0 2006.173.15:11:00.15#ibcon#enter sib2, iclass 17, count 0 2006.173.15:11:00.15#ibcon#flushed, iclass 17, count 0 2006.173.15:11:00.15#ibcon#about to write, iclass 17, count 0 2006.173.15:11:00.15#ibcon#wrote, iclass 17, count 0 2006.173.15:11:00.15#ibcon#about to read 3, iclass 17, count 0 2006.173.15:11:00.19#ibcon#read 3, iclass 17, count 0 2006.173.15:11:00.19#ibcon#about to read 4, iclass 17, count 0 2006.173.15:11:00.19#ibcon#read 4, iclass 17, count 0 2006.173.15:11:00.19#ibcon#about to read 5, iclass 17, count 0 2006.173.15:11:00.19#ibcon#read 5, iclass 17, count 0 2006.173.15:11:00.19#ibcon#about to read 6, iclass 17, count 0 2006.173.15:11:00.19#ibcon#read 6, iclass 17, count 0 2006.173.15:11:00.19#ibcon#end of sib2, iclass 17, count 0 2006.173.15:11:00.19#ibcon#*after write, iclass 17, count 0 2006.173.15:11:00.19#ibcon#*before return 0, iclass 17, count 0 2006.173.15:11:00.19#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.15:11:00.19#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.15:11:00.19#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.15:11:00.19#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.15:11:00.19$vck44/vb=8,4 2006.173.15:11:00.19#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.15:11:00.19#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.15:11:00.19#ibcon#ireg 11 cls_cnt 2 2006.173.15:11:00.19#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.15:11:00.25#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.15:11:00.25#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.15:11:00.25#ibcon#enter wrdev, iclass 19, count 2 2006.173.15:11:00.25#ibcon#first serial, iclass 19, count 2 2006.173.15:11:00.25#ibcon#enter sib2, iclass 19, count 2 2006.173.15:11:00.25#ibcon#flushed, iclass 19, count 2 2006.173.15:11:00.25#ibcon#about to write, iclass 19, count 2 2006.173.15:11:00.25#ibcon#wrote, iclass 19, count 2 2006.173.15:11:00.25#ibcon#about to read 3, iclass 19, count 2 2006.173.15:11:00.27#ibcon#read 3, iclass 19, count 2 2006.173.15:11:00.27#ibcon#about to read 4, iclass 19, count 2 2006.173.15:11:00.27#ibcon#read 4, iclass 19, count 2 2006.173.15:11:00.27#ibcon#about to read 5, iclass 19, count 2 2006.173.15:11:00.27#ibcon#read 5, iclass 19, count 2 2006.173.15:11:00.27#ibcon#about to read 6, iclass 19, count 2 2006.173.15:11:00.27#ibcon#read 6, iclass 19, count 2 2006.173.15:11:00.27#ibcon#end of sib2, iclass 19, count 2 2006.173.15:11:00.27#ibcon#*mode == 0, iclass 19, count 2 2006.173.15:11:00.27#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.15:11:00.27#ibcon#[27=AT08-04\r\n] 2006.173.15:11:00.27#ibcon#*before write, iclass 19, count 2 2006.173.15:11:00.27#ibcon#enter sib2, iclass 19, count 2 2006.173.15:11:00.27#ibcon#flushed, iclass 19, count 2 2006.173.15:11:00.27#ibcon#about to write, iclass 19, count 2 2006.173.15:11:00.27#ibcon#wrote, iclass 19, count 2 2006.173.15:11:00.27#ibcon#about to read 3, iclass 19, count 2 2006.173.15:11:00.30#ibcon#read 3, iclass 19, count 2 2006.173.15:11:00.30#ibcon#about to read 4, iclass 19, count 2 2006.173.15:11:00.30#ibcon#read 4, iclass 19, count 2 2006.173.15:11:00.30#ibcon#about to read 5, iclass 19, count 2 2006.173.15:11:00.30#ibcon#read 5, iclass 19, count 2 2006.173.15:11:00.30#ibcon#about to read 6, iclass 19, count 2 2006.173.15:11:00.30#ibcon#read 6, iclass 19, count 2 2006.173.15:11:00.30#ibcon#end of sib2, iclass 19, count 2 2006.173.15:11:00.30#ibcon#*after write, iclass 19, count 2 2006.173.15:11:00.30#ibcon#*before return 0, iclass 19, count 2 2006.173.15:11:00.30#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.15:11:00.30#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.15:11:00.30#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.15:11:00.30#ibcon#ireg 7 cls_cnt 0 2006.173.15:11:00.30#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.15:11:00.42#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.15:11:00.42#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.15:11:00.42#ibcon#enter wrdev, iclass 19, count 0 2006.173.15:11:00.42#ibcon#first serial, iclass 19, count 0 2006.173.15:11:00.42#ibcon#enter sib2, iclass 19, count 0 2006.173.15:11:00.42#ibcon#flushed, iclass 19, count 0 2006.173.15:11:00.42#ibcon#about to write, iclass 19, count 0 2006.173.15:11:00.42#ibcon#wrote, iclass 19, count 0 2006.173.15:11:00.42#ibcon#about to read 3, iclass 19, count 0 2006.173.15:11:00.44#ibcon#read 3, iclass 19, count 0 2006.173.15:11:00.44#ibcon#about to read 4, iclass 19, count 0 2006.173.15:11:00.44#ibcon#read 4, iclass 19, count 0 2006.173.15:11:00.44#ibcon#about to read 5, iclass 19, count 0 2006.173.15:11:00.44#ibcon#read 5, iclass 19, count 0 2006.173.15:11:00.44#ibcon#about to read 6, iclass 19, count 0 2006.173.15:11:00.44#ibcon#read 6, iclass 19, count 0 2006.173.15:11:00.44#ibcon#end of sib2, iclass 19, count 0 2006.173.15:11:00.44#ibcon#*mode == 0, iclass 19, count 0 2006.173.15:11:00.44#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.15:11:00.44#ibcon#[27=USB\r\n] 2006.173.15:11:00.44#ibcon#*before write, iclass 19, count 0 2006.173.15:11:00.44#ibcon#enter sib2, iclass 19, count 0 2006.173.15:11:00.44#ibcon#flushed, iclass 19, count 0 2006.173.15:11:00.44#ibcon#about to write, iclass 19, count 0 2006.173.15:11:00.44#ibcon#wrote, iclass 19, count 0 2006.173.15:11:00.44#ibcon#about to read 3, iclass 19, count 0 2006.173.15:11:00.47#ibcon#read 3, iclass 19, count 0 2006.173.15:11:00.47#ibcon#about to read 4, iclass 19, count 0 2006.173.15:11:00.47#ibcon#read 4, iclass 19, count 0 2006.173.15:11:00.47#ibcon#about to read 5, iclass 19, count 0 2006.173.15:11:00.47#ibcon#read 5, iclass 19, count 0 2006.173.15:11:00.47#ibcon#about to read 6, iclass 19, count 0 2006.173.15:11:00.47#ibcon#read 6, iclass 19, count 0 2006.173.15:11:00.47#ibcon#end of sib2, iclass 19, count 0 2006.173.15:11:00.47#ibcon#*after write, iclass 19, count 0 2006.173.15:11:00.47#ibcon#*before return 0, iclass 19, count 0 2006.173.15:11:00.47#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.15:11:00.47#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.15:11:00.47#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.15:11:00.47#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.15:11:00.47$vck44/vabw=wide 2006.173.15:11:00.47#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.15:11:00.47#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.15:11:00.47#ibcon#ireg 8 cls_cnt 0 2006.173.15:11:00.47#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.15:11:00.47#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.15:11:00.47#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.15:11:00.47#ibcon#enter wrdev, iclass 21, count 0 2006.173.15:11:00.47#ibcon#first serial, iclass 21, count 0 2006.173.15:11:00.47#ibcon#enter sib2, iclass 21, count 0 2006.173.15:11:00.47#ibcon#flushed, iclass 21, count 0 2006.173.15:11:00.47#ibcon#about to write, iclass 21, count 0 2006.173.15:11:00.47#ibcon#wrote, iclass 21, count 0 2006.173.15:11:00.47#ibcon#about to read 3, iclass 21, count 0 2006.173.15:11:00.49#ibcon#read 3, iclass 21, count 0 2006.173.15:11:00.49#ibcon#about to read 4, iclass 21, count 0 2006.173.15:11:00.49#ibcon#read 4, iclass 21, count 0 2006.173.15:11:00.49#ibcon#about to read 5, iclass 21, count 0 2006.173.15:11:00.49#ibcon#read 5, iclass 21, count 0 2006.173.15:11:00.49#ibcon#about to read 6, iclass 21, count 0 2006.173.15:11:00.49#ibcon#read 6, iclass 21, count 0 2006.173.15:11:00.49#ibcon#end of sib2, iclass 21, count 0 2006.173.15:11:00.49#ibcon#*mode == 0, iclass 21, count 0 2006.173.15:11:00.49#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.15:11:00.49#ibcon#[25=BW32\r\n] 2006.173.15:11:00.49#ibcon#*before write, iclass 21, count 0 2006.173.15:11:00.49#ibcon#enter sib2, iclass 21, count 0 2006.173.15:11:00.49#ibcon#flushed, iclass 21, count 0 2006.173.15:11:00.49#ibcon#about to write, iclass 21, count 0 2006.173.15:11:00.49#ibcon#wrote, iclass 21, count 0 2006.173.15:11:00.49#ibcon#about to read 3, iclass 21, count 0 2006.173.15:11:00.52#ibcon#read 3, iclass 21, count 0 2006.173.15:11:00.52#ibcon#about to read 4, iclass 21, count 0 2006.173.15:11:00.52#ibcon#read 4, iclass 21, count 0 2006.173.15:11:00.52#ibcon#about to read 5, iclass 21, count 0 2006.173.15:11:00.52#ibcon#read 5, iclass 21, count 0 2006.173.15:11:00.52#ibcon#about to read 6, iclass 21, count 0 2006.173.15:11:00.52#ibcon#read 6, iclass 21, count 0 2006.173.15:11:00.52#ibcon#end of sib2, iclass 21, count 0 2006.173.15:11:00.52#ibcon#*after write, iclass 21, count 0 2006.173.15:11:00.52#ibcon#*before return 0, iclass 21, count 0 2006.173.15:11:00.52#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.15:11:00.52#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.15:11:00.52#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.15:11:00.52#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.15:11:00.52$vck44/vbbw=wide 2006.173.15:11:00.52#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.15:11:00.52#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.15:11:00.52#ibcon#ireg 8 cls_cnt 0 2006.173.15:11:00.52#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.15:11:00.59#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.15:11:00.59#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.15:11:00.59#ibcon#enter wrdev, iclass 23, count 0 2006.173.15:11:00.59#ibcon#first serial, iclass 23, count 0 2006.173.15:11:00.59#ibcon#enter sib2, iclass 23, count 0 2006.173.15:11:00.59#ibcon#flushed, iclass 23, count 0 2006.173.15:11:00.59#ibcon#about to write, iclass 23, count 0 2006.173.15:11:00.59#ibcon#wrote, iclass 23, count 0 2006.173.15:11:00.59#ibcon#about to read 3, iclass 23, count 0 2006.173.15:11:00.61#ibcon#read 3, iclass 23, count 0 2006.173.15:11:00.61#ibcon#about to read 4, iclass 23, count 0 2006.173.15:11:00.61#ibcon#read 4, iclass 23, count 0 2006.173.15:11:00.61#ibcon#about to read 5, iclass 23, count 0 2006.173.15:11:00.61#ibcon#read 5, iclass 23, count 0 2006.173.15:11:00.61#ibcon#about to read 6, iclass 23, count 0 2006.173.15:11:00.61#ibcon#read 6, iclass 23, count 0 2006.173.15:11:00.61#ibcon#end of sib2, iclass 23, count 0 2006.173.15:11:00.61#ibcon#*mode == 0, iclass 23, count 0 2006.173.15:11:00.61#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.15:11:00.61#ibcon#[27=BW32\r\n] 2006.173.15:11:00.61#ibcon#*before write, iclass 23, count 0 2006.173.15:11:00.61#ibcon#enter sib2, iclass 23, count 0 2006.173.15:11:00.61#ibcon#flushed, iclass 23, count 0 2006.173.15:11:00.61#ibcon#about to write, iclass 23, count 0 2006.173.15:11:00.61#ibcon#wrote, iclass 23, count 0 2006.173.15:11:00.61#ibcon#about to read 3, iclass 23, count 0 2006.173.15:11:00.64#ibcon#read 3, iclass 23, count 0 2006.173.15:11:00.64#ibcon#about to read 4, iclass 23, count 0 2006.173.15:11:00.64#ibcon#read 4, iclass 23, count 0 2006.173.15:11:00.64#ibcon#about to read 5, iclass 23, count 0 2006.173.15:11:00.64#ibcon#read 5, iclass 23, count 0 2006.173.15:11:00.64#ibcon#about to read 6, iclass 23, count 0 2006.173.15:11:00.64#ibcon#read 6, iclass 23, count 0 2006.173.15:11:00.64#ibcon#end of sib2, iclass 23, count 0 2006.173.15:11:00.64#ibcon#*after write, iclass 23, count 0 2006.173.15:11:00.64#ibcon#*before return 0, iclass 23, count 0 2006.173.15:11:00.64#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.15:11:00.64#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.15:11:00.64#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.15:11:00.64#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.15:11:00.64$setupk4/ifdk4 2006.173.15:11:00.64$ifdk4/lo= 2006.173.15:11:00.64$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.15:11:00.64$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.15:11:00.64$ifdk4/patch= 2006.173.15:11:00.64$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.15:11:00.64$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.15:11:00.64$setupk4/!*+20s 2006.173.15:11:04.69#abcon#<5=/06 2.8 4.2 21.001001003.1\r\n> 2006.173.15:11:04.71#abcon#{5=INTERFACE CLEAR} 2006.173.15:11:04.77#abcon#[5=S1D000X0/0*\r\n] 2006.173.15:11:14.86#abcon#<5=/06 2.8 4.2 21.001001003.1\r\n> 2006.173.15:11:14.88#abcon#{5=INTERFACE CLEAR} 2006.173.15:11:14.94#abcon#[5=S1D000X0/0*\r\n] 2006.173.15:11:15.14#trakl#Source acquired 2006.173.15:11:15.15$setupk4/"tpicd 2006.173.15:11:15.15$setupk4/echo=off 2006.173.15:11:15.15$setupk4/xlog=off 2006.173.15:11:15.15:!2006.173.15:15:40 2006.173.15:11:17.14#flagr#flagr/antenna,acquired 2006.173.15:15:40.00:preob 2006.173.15:15:40.14/onsource/TRACKING 2006.173.15:15:40.14:!2006.173.15:15:50 2006.173.15:15:50.00:"tape 2006.173.15:15:50.00:"st=record 2006.173.15:15:50.00:data_valid=on 2006.173.15:15:50.00:midob 2006.173.15:15:50.14/onsource/TRACKING 2006.173.15:15:50.14/wx/21.07,1003.0,100 2006.173.15:15:50.30/cable/+6.5097E-03 2006.173.15:15:51.39/va/01,07,usb,yes,37,39 2006.173.15:15:51.39/va/02,06,usb,yes,36,37 2006.173.15:15:51.39/va/03,05,usb,yes,46,48 2006.173.15:15:51.39/va/04,06,usb,yes,37,39 2006.173.15:15:51.39/va/05,04,usb,yes,29,30 2006.173.15:15:51.39/va/06,03,usb,yes,41,41 2006.173.15:15:51.39/va/07,04,usb,yes,33,35 2006.173.15:15:51.39/va/08,04,usb,yes,28,34 2006.173.15:15:51.62/valo/01,524.99,yes,locked 2006.173.15:15:51.62/valo/02,534.99,yes,locked 2006.173.15:15:51.62/valo/03,564.99,yes,locked 2006.173.15:15:51.62/valo/04,624.99,yes,locked 2006.173.15:15:51.62/valo/05,734.99,yes,locked 2006.173.15:15:51.62/valo/06,814.99,yes,locked 2006.173.15:15:51.62/valo/07,864.99,yes,locked 2006.173.15:15:51.62/valo/08,884.99,yes,locked 2006.173.15:15:52.71/vb/01,04,usb,yes,29,27 2006.173.15:15:52.71/vb/02,04,usb,yes,31,31 2006.173.15:15:52.71/vb/03,04,usb,yes,28,31 2006.173.15:15:52.71/vb/04,04,usb,yes,32,31 2006.173.15:15:52.71/vb/05,04,usb,yes,25,27 2006.173.15:15:52.71/vb/06,04,usb,yes,29,26 2006.173.15:15:52.71/vb/07,04,usb,yes,29,29 2006.173.15:15:52.71/vb/08,04,usb,yes,27,30 2006.173.15:15:52.94/vblo/01,629.99,yes,locked 2006.173.15:15:52.94/vblo/02,634.99,yes,locked 2006.173.15:15:52.94/vblo/03,649.99,yes,locked 2006.173.15:15:52.94/vblo/04,679.99,yes,locked 2006.173.15:15:52.94/vblo/05,709.99,yes,locked 2006.173.15:15:52.94/vblo/06,719.99,yes,locked 2006.173.15:15:52.94/vblo/07,734.99,yes,locked 2006.173.15:15:52.94/vblo/08,744.99,yes,locked 2006.173.15:15:53.09/vabw/8 2006.173.15:15:53.24/vbbw/8 2006.173.15:15:53.33/xfe/off,on,14.7 2006.173.15:15:53.71/ifatt/23,28,28,28 2006.173.15:15:54.08/fmout-gps/S +4.04E-07 2006.173.15:15:54.12:!2006.173.15:27:40 2006.173.15:27:40.00:data_valid=off 2006.173.15:27:40.01:"et 2006.173.15:27:40.01:!+3s 2006.173.15:27:43.03:"tape 2006.173.15:27:43.03:postob 2006.173.15:27:43.12/cable/+6.5081E-03 2006.173.15:27:43.13/wx/21.08,1003.1,100 2006.173.15:27:43.18/fmout-gps/S +3.97E-07 2006.173.15:27:43.19:scan_name=173-1529,jd0606,70 2006.173.15:27:43.19:source=1908-201,191109.65,-200655.1,2000.0,cw 2006.173.15:27:44.14#flagr#flagr/antenna,new-source 2006.173.15:27:44.15:checkk5 2006.173.15:27:44.56/chk_autoobs//k5ts1/ autoobs is running! 2006.173.15:27:44.97/chk_autoobs//k5ts2/ autoobs is running! 2006.173.15:27:45.37/chk_autoobs//k5ts3/ autoobs is running! 2006.173.15:27:45.78/chk_autoobs//k5ts4/ autoobs is running! 2006.173.15:27:46.48/chk_obsdata//k5ts1/T1731515??a.dat file size is correct (nominal:2840MB, actual:2836MB). 2006.173.15:27:47.18/chk_obsdata//k5ts2/T1731515??b.dat file size is correct (nominal:2840MB, actual:2836MB). 2006.173.15:27:47.89/chk_obsdata//k5ts3/T1731515??c.dat file size is correct (nominal:2840MB, actual:2836MB). 2006.173.15:27:48.61/chk_obsdata//k5ts4/T1731515??d.dat file size is correct (nominal:2840MB, actual:2836MB). 2006.173.15:27:49.35/k5log//k5ts1_log_newline 2006.173.15:27:50.06/k5log//k5ts2_log_newline 2006.173.15:27:50.77/k5log//k5ts3_log_newline 2006.173.15:27:51.48/k5log//k5ts4_log_newline 2006.173.15:27:51.51/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.15:27:51.51:setupk4=1 2006.173.15:27:51.51$setupk4/echo=on 2006.173.15:27:51.51$setupk4/pcalon 2006.173.15:27:51.51$pcalon/"no phase cal control is implemented here 2006.173.15:27:51.51$setupk4/"tpicd=stop 2006.173.15:27:51.51$setupk4/"rec=synch_on 2006.173.15:27:51.51$setupk4/"rec_mode=128 2006.173.15:27:51.51$setupk4/!* 2006.173.15:27:51.51$setupk4/recpk4 2006.173.15:27:51.51$recpk4/recpatch= 2006.173.15:27:51.51$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.15:27:51.51$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.15:27:51.51$setupk4/vck44 2006.173.15:27:51.51$vck44/valo=1,524.99 2006.173.15:27:51.51#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.15:27:51.51#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.15:27:51.51#ibcon#ireg 17 cls_cnt 0 2006.173.15:27:51.51#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.15:27:51.51#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.15:27:51.51#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.15:27:51.51#ibcon#enter wrdev, iclass 28, count 0 2006.173.15:27:51.51#ibcon#first serial, iclass 28, count 0 2006.173.15:27:51.51#ibcon#enter sib2, iclass 28, count 0 2006.173.15:27:51.51#ibcon#flushed, iclass 28, count 0 2006.173.15:27:51.51#ibcon#about to write, iclass 28, count 0 2006.173.15:27:51.51#ibcon#wrote, iclass 28, count 0 2006.173.15:27:51.51#ibcon#about to read 3, iclass 28, count 0 2006.173.15:27:51.52#ibcon#read 3, iclass 28, count 0 2006.173.15:27:51.52#ibcon#about to read 4, iclass 28, count 0 2006.173.15:27:51.52#ibcon#read 4, iclass 28, count 0 2006.173.15:27:51.52#ibcon#about to read 5, iclass 28, count 0 2006.173.15:27:51.52#ibcon#read 5, iclass 28, count 0 2006.173.15:27:51.52#ibcon#about to read 6, iclass 28, count 0 2006.173.15:27:51.52#ibcon#read 6, iclass 28, count 0 2006.173.15:27:51.52#ibcon#end of sib2, iclass 28, count 0 2006.173.15:27:51.52#ibcon#*mode == 0, iclass 28, count 0 2006.173.15:27:51.52#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.15:27:51.52#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.15:27:51.52#ibcon#*before write, iclass 28, count 0 2006.173.15:27:51.52#ibcon#enter sib2, iclass 28, count 0 2006.173.15:27:51.52#ibcon#flushed, iclass 28, count 0 2006.173.15:27:51.52#ibcon#about to write, iclass 28, count 0 2006.173.15:27:51.52#ibcon#wrote, iclass 28, count 0 2006.173.15:27:51.52#ibcon#about to read 3, iclass 28, count 0 2006.173.15:27:51.57#ibcon#read 3, iclass 28, count 0 2006.173.15:27:51.57#ibcon#about to read 4, iclass 28, count 0 2006.173.15:27:51.57#ibcon#read 4, iclass 28, count 0 2006.173.15:27:51.57#ibcon#about to read 5, iclass 28, count 0 2006.173.15:27:51.57#ibcon#read 5, iclass 28, count 0 2006.173.15:27:51.57#ibcon#about to read 6, iclass 28, count 0 2006.173.15:27:51.57#ibcon#read 6, iclass 28, count 0 2006.173.15:27:51.57#ibcon#end of sib2, iclass 28, count 0 2006.173.15:27:51.57#ibcon#*after write, iclass 28, count 0 2006.173.15:27:51.57#ibcon#*before return 0, iclass 28, count 0 2006.173.15:27:51.57#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.15:27:51.57#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.15:27:51.57#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.15:27:51.57#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.15:27:51.57$vck44/va=1,7 2006.173.15:27:51.57#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.15:27:51.57#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.15:27:51.57#ibcon#ireg 11 cls_cnt 2 2006.173.15:27:51.57#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.15:27:51.57#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.15:27:51.57#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.15:27:51.57#ibcon#enter wrdev, iclass 30, count 2 2006.173.15:27:51.57#ibcon#first serial, iclass 30, count 2 2006.173.15:27:51.57#ibcon#enter sib2, iclass 30, count 2 2006.173.15:27:51.57#ibcon#flushed, iclass 30, count 2 2006.173.15:27:51.57#ibcon#about to write, iclass 30, count 2 2006.173.15:27:51.58#ibcon#wrote, iclass 30, count 2 2006.173.15:27:51.58#ibcon#about to read 3, iclass 30, count 2 2006.173.15:27:51.59#ibcon#read 3, iclass 30, count 2 2006.173.15:27:51.59#ibcon#about to read 4, iclass 30, count 2 2006.173.15:27:51.59#ibcon#read 4, iclass 30, count 2 2006.173.15:27:51.59#ibcon#about to read 5, iclass 30, count 2 2006.173.15:27:51.59#ibcon#read 5, iclass 30, count 2 2006.173.15:27:51.59#ibcon#about to read 6, iclass 30, count 2 2006.173.15:27:51.59#ibcon#read 6, iclass 30, count 2 2006.173.15:27:51.59#ibcon#end of sib2, iclass 30, count 2 2006.173.15:27:51.59#ibcon#*mode == 0, iclass 30, count 2 2006.173.15:27:51.59#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.15:27:51.59#ibcon#[25=AT01-07\r\n] 2006.173.15:27:51.59#ibcon#*before write, iclass 30, count 2 2006.173.15:27:51.59#ibcon#enter sib2, iclass 30, count 2 2006.173.15:27:51.59#ibcon#flushed, iclass 30, count 2 2006.173.15:27:51.59#ibcon#about to write, iclass 30, count 2 2006.173.15:27:51.59#ibcon#wrote, iclass 30, count 2 2006.173.15:27:51.59#ibcon#about to read 3, iclass 30, count 2 2006.173.15:27:51.62#ibcon#read 3, iclass 30, count 2 2006.173.15:27:51.62#ibcon#about to read 4, iclass 30, count 2 2006.173.15:27:51.62#ibcon#read 4, iclass 30, count 2 2006.173.15:27:51.62#ibcon#about to read 5, iclass 30, count 2 2006.173.15:27:51.62#ibcon#read 5, iclass 30, count 2 2006.173.15:27:51.62#ibcon#about to read 6, iclass 30, count 2 2006.173.15:27:51.62#ibcon#read 6, iclass 30, count 2 2006.173.15:27:51.62#ibcon#end of sib2, iclass 30, count 2 2006.173.15:27:51.62#ibcon#*after write, iclass 30, count 2 2006.173.15:27:51.62#ibcon#*before return 0, iclass 30, count 2 2006.173.15:27:51.62#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.15:27:51.62#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.15:27:51.62#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.15:27:51.62#ibcon#ireg 7 cls_cnt 0 2006.173.15:27:51.62#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.15:27:51.70#abcon#<5=/14 0.8 1.5 21.081001003.1\r\n> 2006.173.15:27:51.72#abcon#{5=INTERFACE CLEAR} 2006.173.15:27:51.74#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.15:27:51.74#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.15:27:51.74#ibcon#enter wrdev, iclass 30, count 0 2006.173.15:27:51.74#ibcon#first serial, iclass 30, count 0 2006.173.15:27:51.74#ibcon#enter sib2, iclass 30, count 0 2006.173.15:27:51.74#ibcon#flushed, iclass 30, count 0 2006.173.15:27:51.74#ibcon#about to write, iclass 30, count 0 2006.173.15:27:51.74#ibcon#wrote, iclass 30, count 0 2006.173.15:27:51.74#ibcon#about to read 3, iclass 30, count 0 2006.173.15:27:51.76#ibcon#read 3, iclass 30, count 0 2006.173.15:27:51.76#ibcon#about to read 4, iclass 30, count 0 2006.173.15:27:51.76#ibcon#read 4, iclass 30, count 0 2006.173.15:27:51.76#ibcon#about to read 5, iclass 30, count 0 2006.173.15:27:51.76#ibcon#read 5, iclass 30, count 0 2006.173.15:27:51.76#ibcon#about to read 6, iclass 30, count 0 2006.173.15:27:51.76#ibcon#read 6, iclass 30, count 0 2006.173.15:27:51.76#ibcon#end of sib2, iclass 30, count 0 2006.173.15:27:51.76#ibcon#*mode == 0, iclass 30, count 0 2006.173.15:27:51.76#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.15:27:51.76#ibcon#[25=USB\r\n] 2006.173.15:27:51.76#ibcon#*before write, iclass 30, count 0 2006.173.15:27:51.76#ibcon#enter sib2, iclass 30, count 0 2006.173.15:27:51.76#ibcon#flushed, iclass 30, count 0 2006.173.15:27:51.76#ibcon#about to write, iclass 30, count 0 2006.173.15:27:51.76#ibcon#wrote, iclass 30, count 0 2006.173.15:27:51.76#ibcon#about to read 3, iclass 30, count 0 2006.173.15:27:51.78#abcon#[5=S1D000X0/0*\r\n] 2006.173.15:27:51.79#ibcon#read 3, iclass 30, count 0 2006.173.15:27:51.79#ibcon#about to read 4, iclass 30, count 0 2006.173.15:27:51.79#ibcon#read 4, iclass 30, count 0 2006.173.15:27:51.79#ibcon#about to read 5, iclass 30, count 0 2006.173.15:27:51.79#ibcon#read 5, iclass 30, count 0 2006.173.15:27:51.79#ibcon#about to read 6, iclass 30, count 0 2006.173.15:27:51.79#ibcon#read 6, iclass 30, count 0 2006.173.15:27:51.79#ibcon#end of sib2, iclass 30, count 0 2006.173.15:27:51.79#ibcon#*after write, iclass 30, count 0 2006.173.15:27:51.79#ibcon#*before return 0, iclass 30, count 0 2006.173.15:27:51.79#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.15:27:51.79#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.15:27:51.79#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.15:27:51.79#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.15:27:51.79$vck44/valo=2,534.99 2006.173.15:27:51.79#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.15:27:51.79#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.15:27:51.79#ibcon#ireg 17 cls_cnt 0 2006.173.15:27:51.79#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.15:27:51.79#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.15:27:51.79#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.15:27:51.79#ibcon#enter wrdev, iclass 36, count 0 2006.173.15:27:51.79#ibcon#first serial, iclass 36, count 0 2006.173.15:27:51.79#ibcon#enter sib2, iclass 36, count 0 2006.173.15:27:51.79#ibcon#flushed, iclass 36, count 0 2006.173.15:27:51.80#ibcon#about to write, iclass 36, count 0 2006.173.15:27:51.80#ibcon#wrote, iclass 36, count 0 2006.173.15:27:51.80#ibcon#about to read 3, iclass 36, count 0 2006.173.15:27:51.81#ibcon#read 3, iclass 36, count 0 2006.173.15:27:51.81#ibcon#about to read 4, iclass 36, count 0 2006.173.15:27:51.81#ibcon#read 4, iclass 36, count 0 2006.173.15:27:51.81#ibcon#about to read 5, iclass 36, count 0 2006.173.15:27:51.81#ibcon#read 5, iclass 36, count 0 2006.173.15:27:51.81#ibcon#about to read 6, iclass 36, count 0 2006.173.15:27:51.81#ibcon#read 6, iclass 36, count 0 2006.173.15:27:51.81#ibcon#end of sib2, iclass 36, count 0 2006.173.15:27:51.81#ibcon#*mode == 0, iclass 36, count 0 2006.173.15:27:51.81#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.15:27:51.81#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.15:27:51.81#ibcon#*before write, iclass 36, count 0 2006.173.15:27:51.81#ibcon#enter sib2, iclass 36, count 0 2006.173.15:27:51.81#ibcon#flushed, iclass 36, count 0 2006.173.15:27:51.81#ibcon#about to write, iclass 36, count 0 2006.173.15:27:51.81#ibcon#wrote, iclass 36, count 0 2006.173.15:27:51.81#ibcon#about to read 3, iclass 36, count 0 2006.173.15:27:51.85#ibcon#read 3, iclass 36, count 0 2006.173.15:27:51.85#ibcon#about to read 4, iclass 36, count 0 2006.173.15:27:51.85#ibcon#read 4, iclass 36, count 0 2006.173.15:27:51.85#ibcon#about to read 5, iclass 36, count 0 2006.173.15:27:51.85#ibcon#read 5, iclass 36, count 0 2006.173.15:27:51.85#ibcon#about to read 6, iclass 36, count 0 2006.173.15:27:51.85#ibcon#read 6, iclass 36, count 0 2006.173.15:27:51.85#ibcon#end of sib2, iclass 36, count 0 2006.173.15:27:51.85#ibcon#*after write, iclass 36, count 0 2006.173.15:27:51.85#ibcon#*before return 0, iclass 36, count 0 2006.173.15:27:51.85#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.15:27:51.85#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.15:27:51.85#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.15:27:51.85#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.15:27:51.85$vck44/va=2,6 2006.173.15:27:51.85#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.15:27:51.85#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.15:27:51.85#ibcon#ireg 11 cls_cnt 2 2006.173.15:27:51.85#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.15:27:51.91#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.15:27:51.91#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.15:27:51.91#ibcon#enter wrdev, iclass 38, count 2 2006.173.15:27:51.91#ibcon#first serial, iclass 38, count 2 2006.173.15:27:51.91#ibcon#enter sib2, iclass 38, count 2 2006.173.15:27:51.91#ibcon#flushed, iclass 38, count 2 2006.173.15:27:51.91#ibcon#about to write, iclass 38, count 2 2006.173.15:27:51.91#ibcon#wrote, iclass 38, count 2 2006.173.15:27:51.91#ibcon#about to read 3, iclass 38, count 2 2006.173.15:27:51.93#ibcon#read 3, iclass 38, count 2 2006.173.15:27:51.93#ibcon#about to read 4, iclass 38, count 2 2006.173.15:27:51.93#ibcon#read 4, iclass 38, count 2 2006.173.15:27:51.93#ibcon#about to read 5, iclass 38, count 2 2006.173.15:27:51.93#ibcon#read 5, iclass 38, count 2 2006.173.15:27:51.93#ibcon#about to read 6, iclass 38, count 2 2006.173.15:27:51.93#ibcon#read 6, iclass 38, count 2 2006.173.15:27:51.93#ibcon#end of sib2, iclass 38, count 2 2006.173.15:27:51.93#ibcon#*mode == 0, iclass 38, count 2 2006.173.15:27:51.93#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.15:27:51.93#ibcon#[25=AT02-06\r\n] 2006.173.15:27:51.93#ibcon#*before write, iclass 38, count 2 2006.173.15:27:51.93#ibcon#enter sib2, iclass 38, count 2 2006.173.15:27:51.93#ibcon#flushed, iclass 38, count 2 2006.173.15:27:51.93#ibcon#about to write, iclass 38, count 2 2006.173.15:27:51.93#ibcon#wrote, iclass 38, count 2 2006.173.15:27:51.93#ibcon#about to read 3, iclass 38, count 2 2006.173.15:27:51.96#ibcon#read 3, iclass 38, count 2 2006.173.15:27:51.96#ibcon#about to read 4, iclass 38, count 2 2006.173.15:27:51.96#ibcon#read 4, iclass 38, count 2 2006.173.15:27:51.96#ibcon#about to read 5, iclass 38, count 2 2006.173.15:27:51.96#ibcon#read 5, iclass 38, count 2 2006.173.15:27:51.96#ibcon#about to read 6, iclass 38, count 2 2006.173.15:27:51.96#ibcon#read 6, iclass 38, count 2 2006.173.15:27:51.96#ibcon#end of sib2, iclass 38, count 2 2006.173.15:27:51.96#ibcon#*after write, iclass 38, count 2 2006.173.15:27:51.96#ibcon#*before return 0, iclass 38, count 2 2006.173.15:27:51.96#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.15:27:51.96#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.15:27:51.96#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.15:27:51.96#ibcon#ireg 7 cls_cnt 0 2006.173.15:27:51.96#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.15:27:52.08#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.15:27:52.08#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.15:27:52.08#ibcon#enter wrdev, iclass 38, count 0 2006.173.15:27:52.08#ibcon#first serial, iclass 38, count 0 2006.173.15:27:52.08#ibcon#enter sib2, iclass 38, count 0 2006.173.15:27:52.08#ibcon#flushed, iclass 38, count 0 2006.173.15:27:52.08#ibcon#about to write, iclass 38, count 0 2006.173.15:27:52.08#ibcon#wrote, iclass 38, count 0 2006.173.15:27:52.08#ibcon#about to read 3, iclass 38, count 0 2006.173.15:27:52.10#ibcon#read 3, iclass 38, count 0 2006.173.15:27:52.10#ibcon#about to read 4, iclass 38, count 0 2006.173.15:27:52.10#ibcon#read 4, iclass 38, count 0 2006.173.15:27:52.10#ibcon#about to read 5, iclass 38, count 0 2006.173.15:27:52.10#ibcon#read 5, iclass 38, count 0 2006.173.15:27:52.10#ibcon#about to read 6, iclass 38, count 0 2006.173.15:27:52.10#ibcon#read 6, iclass 38, count 0 2006.173.15:27:52.10#ibcon#end of sib2, iclass 38, count 0 2006.173.15:27:52.10#ibcon#*mode == 0, iclass 38, count 0 2006.173.15:27:52.10#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.15:27:52.10#ibcon#[25=USB\r\n] 2006.173.15:27:52.10#ibcon#*before write, iclass 38, count 0 2006.173.15:27:52.10#ibcon#enter sib2, iclass 38, count 0 2006.173.15:27:52.10#ibcon#flushed, iclass 38, count 0 2006.173.15:27:52.10#ibcon#about to write, iclass 38, count 0 2006.173.15:27:52.10#ibcon#wrote, iclass 38, count 0 2006.173.15:27:52.10#ibcon#about to read 3, iclass 38, count 0 2006.173.15:27:52.13#ibcon#read 3, iclass 38, count 0 2006.173.15:27:52.13#ibcon#about to read 4, iclass 38, count 0 2006.173.15:27:52.13#ibcon#read 4, iclass 38, count 0 2006.173.15:27:52.13#ibcon#about to read 5, iclass 38, count 0 2006.173.15:27:52.13#ibcon#read 5, iclass 38, count 0 2006.173.15:27:52.13#ibcon#about to read 6, iclass 38, count 0 2006.173.15:27:52.13#ibcon#read 6, iclass 38, count 0 2006.173.15:27:52.13#ibcon#end of sib2, iclass 38, count 0 2006.173.15:27:52.13#ibcon#*after write, iclass 38, count 0 2006.173.15:27:52.13#ibcon#*before return 0, iclass 38, count 0 2006.173.15:27:52.13#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.15:27:52.13#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.15:27:52.13#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.15:27:52.13#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.15:27:52.13$vck44/valo=3,564.99 2006.173.15:27:52.13#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.15:27:52.13#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.15:27:52.13#ibcon#ireg 17 cls_cnt 0 2006.173.15:27:52.13#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.15:27:52.13#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.15:27:52.13#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.15:27:52.13#ibcon#enter wrdev, iclass 40, count 0 2006.173.15:27:52.13#ibcon#first serial, iclass 40, count 0 2006.173.15:27:52.14#ibcon#enter sib2, iclass 40, count 0 2006.173.15:27:52.14#ibcon#flushed, iclass 40, count 0 2006.173.15:27:52.14#ibcon#about to write, iclass 40, count 0 2006.173.15:27:52.14#ibcon#wrote, iclass 40, count 0 2006.173.15:27:52.14#ibcon#about to read 3, iclass 40, count 0 2006.173.15:27:52.15#ibcon#read 3, iclass 40, count 0 2006.173.15:27:52.15#ibcon#about to read 4, iclass 40, count 0 2006.173.15:27:52.15#ibcon#read 4, iclass 40, count 0 2006.173.15:27:52.15#ibcon#about to read 5, iclass 40, count 0 2006.173.15:27:52.15#ibcon#read 5, iclass 40, count 0 2006.173.15:27:52.15#ibcon#about to read 6, iclass 40, count 0 2006.173.15:27:52.15#ibcon#read 6, iclass 40, count 0 2006.173.15:27:52.15#ibcon#end of sib2, iclass 40, count 0 2006.173.15:27:52.15#ibcon#*mode == 0, iclass 40, count 0 2006.173.15:27:52.15#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.15:27:52.15#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.15:27:52.15#ibcon#*before write, iclass 40, count 0 2006.173.15:27:52.15#ibcon#enter sib2, iclass 40, count 0 2006.173.15:27:52.15#ibcon#flushed, iclass 40, count 0 2006.173.15:27:52.15#ibcon#about to write, iclass 40, count 0 2006.173.15:27:52.15#ibcon#wrote, iclass 40, count 0 2006.173.15:27:52.15#ibcon#about to read 3, iclass 40, count 0 2006.173.15:27:52.19#ibcon#read 3, iclass 40, count 0 2006.173.15:27:52.19#ibcon#about to read 4, iclass 40, count 0 2006.173.15:27:52.19#ibcon#read 4, iclass 40, count 0 2006.173.15:27:52.19#ibcon#about to read 5, iclass 40, count 0 2006.173.15:27:52.19#ibcon#read 5, iclass 40, count 0 2006.173.15:27:52.19#ibcon#about to read 6, iclass 40, count 0 2006.173.15:27:52.19#ibcon#read 6, iclass 40, count 0 2006.173.15:27:52.19#ibcon#end of sib2, iclass 40, count 0 2006.173.15:27:52.19#ibcon#*after write, iclass 40, count 0 2006.173.15:27:52.19#ibcon#*before return 0, iclass 40, count 0 2006.173.15:27:52.19#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.15:27:52.19#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.15:27:52.19#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.15:27:52.19#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.15:27:52.19$vck44/va=3,5 2006.173.15:27:52.19#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.15:27:52.19#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.15:27:52.19#ibcon#ireg 11 cls_cnt 2 2006.173.15:27:52.19#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.15:27:52.25#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.15:27:52.25#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.15:27:52.25#ibcon#enter wrdev, iclass 4, count 2 2006.173.15:27:52.25#ibcon#first serial, iclass 4, count 2 2006.173.15:27:52.25#ibcon#enter sib2, iclass 4, count 2 2006.173.15:27:52.25#ibcon#flushed, iclass 4, count 2 2006.173.15:27:52.25#ibcon#about to write, iclass 4, count 2 2006.173.15:27:52.25#ibcon#wrote, iclass 4, count 2 2006.173.15:27:52.25#ibcon#about to read 3, iclass 4, count 2 2006.173.15:27:52.27#ibcon#read 3, iclass 4, count 2 2006.173.15:27:52.27#ibcon#about to read 4, iclass 4, count 2 2006.173.15:27:52.27#ibcon#read 4, iclass 4, count 2 2006.173.15:27:52.27#ibcon#about to read 5, iclass 4, count 2 2006.173.15:27:52.27#ibcon#read 5, iclass 4, count 2 2006.173.15:27:52.27#ibcon#about to read 6, iclass 4, count 2 2006.173.15:27:52.27#ibcon#read 6, iclass 4, count 2 2006.173.15:27:52.27#ibcon#end of sib2, iclass 4, count 2 2006.173.15:27:52.27#ibcon#*mode == 0, iclass 4, count 2 2006.173.15:27:52.27#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.15:27:52.27#ibcon#[25=AT03-05\r\n] 2006.173.15:27:52.27#ibcon#*before write, iclass 4, count 2 2006.173.15:27:52.27#ibcon#enter sib2, iclass 4, count 2 2006.173.15:27:52.27#ibcon#flushed, iclass 4, count 2 2006.173.15:27:52.27#ibcon#about to write, iclass 4, count 2 2006.173.15:27:52.27#ibcon#wrote, iclass 4, count 2 2006.173.15:27:52.27#ibcon#about to read 3, iclass 4, count 2 2006.173.15:27:52.30#ibcon#read 3, iclass 4, count 2 2006.173.15:27:52.30#ibcon#about to read 4, iclass 4, count 2 2006.173.15:27:52.30#ibcon#read 4, iclass 4, count 2 2006.173.15:27:52.30#ibcon#about to read 5, iclass 4, count 2 2006.173.15:27:52.30#ibcon#read 5, iclass 4, count 2 2006.173.15:27:52.30#ibcon#about to read 6, iclass 4, count 2 2006.173.15:27:52.30#ibcon#read 6, iclass 4, count 2 2006.173.15:27:52.30#ibcon#end of sib2, iclass 4, count 2 2006.173.15:27:52.30#ibcon#*after write, iclass 4, count 2 2006.173.15:27:52.30#ibcon#*before return 0, iclass 4, count 2 2006.173.15:27:52.30#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.15:27:52.30#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.15:27:52.30#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.15:27:52.30#ibcon#ireg 7 cls_cnt 0 2006.173.15:27:52.30#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.15:27:52.42#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.15:27:52.42#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.15:27:52.42#ibcon#enter wrdev, iclass 4, count 0 2006.173.15:27:52.42#ibcon#first serial, iclass 4, count 0 2006.173.15:27:52.42#ibcon#enter sib2, iclass 4, count 0 2006.173.15:27:52.42#ibcon#flushed, iclass 4, count 0 2006.173.15:27:52.42#ibcon#about to write, iclass 4, count 0 2006.173.15:27:52.42#ibcon#wrote, iclass 4, count 0 2006.173.15:27:52.42#ibcon#about to read 3, iclass 4, count 0 2006.173.15:27:52.44#ibcon#read 3, iclass 4, count 0 2006.173.15:27:52.44#ibcon#about to read 4, iclass 4, count 0 2006.173.15:27:52.44#ibcon#read 4, iclass 4, count 0 2006.173.15:27:52.44#ibcon#about to read 5, iclass 4, count 0 2006.173.15:27:52.44#ibcon#read 5, iclass 4, count 0 2006.173.15:27:52.44#ibcon#about to read 6, iclass 4, count 0 2006.173.15:27:52.44#ibcon#read 6, iclass 4, count 0 2006.173.15:27:52.44#ibcon#end of sib2, iclass 4, count 0 2006.173.15:27:52.44#ibcon#*mode == 0, iclass 4, count 0 2006.173.15:27:52.44#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.15:27:52.44#ibcon#[25=USB\r\n] 2006.173.15:27:52.44#ibcon#*before write, iclass 4, count 0 2006.173.15:27:52.44#ibcon#enter sib2, iclass 4, count 0 2006.173.15:27:52.44#ibcon#flushed, iclass 4, count 0 2006.173.15:27:52.44#ibcon#about to write, iclass 4, count 0 2006.173.15:27:52.44#ibcon#wrote, iclass 4, count 0 2006.173.15:27:52.44#ibcon#about to read 3, iclass 4, count 0 2006.173.15:27:52.47#ibcon#read 3, iclass 4, count 0 2006.173.15:27:52.47#ibcon#about to read 4, iclass 4, count 0 2006.173.15:27:52.47#ibcon#read 4, iclass 4, count 0 2006.173.15:27:52.47#ibcon#about to read 5, iclass 4, count 0 2006.173.15:27:52.47#ibcon#read 5, iclass 4, count 0 2006.173.15:27:52.47#ibcon#about to read 6, iclass 4, count 0 2006.173.15:27:52.47#ibcon#read 6, iclass 4, count 0 2006.173.15:27:52.47#ibcon#end of sib2, iclass 4, count 0 2006.173.15:27:52.47#ibcon#*after write, iclass 4, count 0 2006.173.15:27:52.47#ibcon#*before return 0, iclass 4, count 0 2006.173.15:27:52.47#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.15:27:52.47#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.15:27:52.47#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.15:27:52.47#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.15:27:52.47$vck44/valo=4,624.99 2006.173.15:27:52.47#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.15:27:52.47#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.15:27:52.47#ibcon#ireg 17 cls_cnt 0 2006.173.15:27:52.47#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.15:27:52.47#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.15:27:52.47#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.15:27:52.47#ibcon#enter wrdev, iclass 6, count 0 2006.173.15:27:52.47#ibcon#first serial, iclass 6, count 0 2006.173.15:27:52.47#ibcon#enter sib2, iclass 6, count 0 2006.173.15:27:52.47#ibcon#flushed, iclass 6, count 0 2006.173.15:27:52.47#ibcon#about to write, iclass 6, count 0 2006.173.15:27:52.48#ibcon#wrote, iclass 6, count 0 2006.173.15:27:52.48#ibcon#about to read 3, iclass 6, count 0 2006.173.15:27:52.49#ibcon#read 3, iclass 6, count 0 2006.173.15:27:52.49#ibcon#about to read 4, iclass 6, count 0 2006.173.15:27:52.49#ibcon#read 4, iclass 6, count 0 2006.173.15:27:52.49#ibcon#about to read 5, iclass 6, count 0 2006.173.15:27:52.49#ibcon#read 5, iclass 6, count 0 2006.173.15:27:52.49#ibcon#about to read 6, iclass 6, count 0 2006.173.15:27:52.49#ibcon#read 6, iclass 6, count 0 2006.173.15:27:52.49#ibcon#end of sib2, iclass 6, count 0 2006.173.15:27:52.49#ibcon#*mode == 0, iclass 6, count 0 2006.173.15:27:52.49#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.15:27:52.49#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.15:27:52.49#ibcon#*before write, iclass 6, count 0 2006.173.15:27:52.49#ibcon#enter sib2, iclass 6, count 0 2006.173.15:27:52.49#ibcon#flushed, iclass 6, count 0 2006.173.15:27:52.49#ibcon#about to write, iclass 6, count 0 2006.173.15:27:52.49#ibcon#wrote, iclass 6, count 0 2006.173.15:27:52.49#ibcon#about to read 3, iclass 6, count 0 2006.173.15:27:52.53#ibcon#read 3, iclass 6, count 0 2006.173.15:27:52.53#ibcon#about to read 4, iclass 6, count 0 2006.173.15:27:52.53#ibcon#read 4, iclass 6, count 0 2006.173.15:27:52.53#ibcon#about to read 5, iclass 6, count 0 2006.173.15:27:52.53#ibcon#read 5, iclass 6, count 0 2006.173.15:27:52.53#ibcon#about to read 6, iclass 6, count 0 2006.173.15:27:52.53#ibcon#read 6, iclass 6, count 0 2006.173.15:27:52.53#ibcon#end of sib2, iclass 6, count 0 2006.173.15:27:52.53#ibcon#*after write, iclass 6, count 0 2006.173.15:27:52.53#ibcon#*before return 0, iclass 6, count 0 2006.173.15:27:52.53#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.15:27:52.53#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.15:27:52.53#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.15:27:52.53#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.15:27:52.53$vck44/va=4,6 2006.173.15:27:52.53#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.15:27:52.53#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.15:27:52.53#ibcon#ireg 11 cls_cnt 2 2006.173.15:27:52.53#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.15:27:52.59#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.15:27:52.59#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.15:27:52.59#ibcon#enter wrdev, iclass 10, count 2 2006.173.15:27:52.59#ibcon#first serial, iclass 10, count 2 2006.173.15:27:52.59#ibcon#enter sib2, iclass 10, count 2 2006.173.15:27:52.59#ibcon#flushed, iclass 10, count 2 2006.173.15:27:52.59#ibcon#about to write, iclass 10, count 2 2006.173.15:27:52.59#ibcon#wrote, iclass 10, count 2 2006.173.15:27:52.59#ibcon#about to read 3, iclass 10, count 2 2006.173.15:27:52.61#ibcon#read 3, iclass 10, count 2 2006.173.15:27:52.61#ibcon#about to read 4, iclass 10, count 2 2006.173.15:27:52.61#ibcon#read 4, iclass 10, count 2 2006.173.15:27:52.61#ibcon#about to read 5, iclass 10, count 2 2006.173.15:27:52.61#ibcon#read 5, iclass 10, count 2 2006.173.15:27:52.61#ibcon#about to read 6, iclass 10, count 2 2006.173.15:27:52.61#ibcon#read 6, iclass 10, count 2 2006.173.15:27:52.61#ibcon#end of sib2, iclass 10, count 2 2006.173.15:27:52.61#ibcon#*mode == 0, iclass 10, count 2 2006.173.15:27:52.61#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.15:27:52.61#ibcon#[25=AT04-06\r\n] 2006.173.15:27:52.61#ibcon#*before write, iclass 10, count 2 2006.173.15:27:52.61#ibcon#enter sib2, iclass 10, count 2 2006.173.15:27:52.61#ibcon#flushed, iclass 10, count 2 2006.173.15:27:52.61#ibcon#about to write, iclass 10, count 2 2006.173.15:27:52.61#ibcon#wrote, iclass 10, count 2 2006.173.15:27:52.61#ibcon#about to read 3, iclass 10, count 2 2006.173.15:27:52.64#ibcon#read 3, iclass 10, count 2 2006.173.15:27:52.64#ibcon#about to read 4, iclass 10, count 2 2006.173.15:27:52.64#ibcon#read 4, iclass 10, count 2 2006.173.15:27:52.64#ibcon#about to read 5, iclass 10, count 2 2006.173.15:27:52.64#ibcon#read 5, iclass 10, count 2 2006.173.15:27:52.64#ibcon#about to read 6, iclass 10, count 2 2006.173.15:27:52.64#ibcon#read 6, iclass 10, count 2 2006.173.15:27:52.64#ibcon#end of sib2, iclass 10, count 2 2006.173.15:27:52.64#ibcon#*after write, iclass 10, count 2 2006.173.15:27:52.64#ibcon#*before return 0, iclass 10, count 2 2006.173.15:27:52.64#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.15:27:52.64#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.15:27:52.64#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.15:27:52.64#ibcon#ireg 7 cls_cnt 0 2006.173.15:27:52.64#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.15:27:52.76#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.15:27:52.76#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.15:27:52.76#ibcon#enter wrdev, iclass 10, count 0 2006.173.15:27:52.76#ibcon#first serial, iclass 10, count 0 2006.173.15:27:52.76#ibcon#enter sib2, iclass 10, count 0 2006.173.15:27:52.76#ibcon#flushed, iclass 10, count 0 2006.173.15:27:52.76#ibcon#about to write, iclass 10, count 0 2006.173.15:27:52.76#ibcon#wrote, iclass 10, count 0 2006.173.15:27:52.76#ibcon#about to read 3, iclass 10, count 0 2006.173.15:27:52.78#ibcon#read 3, iclass 10, count 0 2006.173.15:27:52.78#ibcon#about to read 4, iclass 10, count 0 2006.173.15:27:52.78#ibcon#read 4, iclass 10, count 0 2006.173.15:27:52.78#ibcon#about to read 5, iclass 10, count 0 2006.173.15:27:52.78#ibcon#read 5, iclass 10, count 0 2006.173.15:27:52.78#ibcon#about to read 6, iclass 10, count 0 2006.173.15:27:52.78#ibcon#read 6, iclass 10, count 0 2006.173.15:27:52.78#ibcon#end of sib2, iclass 10, count 0 2006.173.15:27:52.78#ibcon#*mode == 0, iclass 10, count 0 2006.173.15:27:52.78#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.15:27:52.78#ibcon#[25=USB\r\n] 2006.173.15:27:52.78#ibcon#*before write, iclass 10, count 0 2006.173.15:27:52.78#ibcon#enter sib2, iclass 10, count 0 2006.173.15:27:52.78#ibcon#flushed, iclass 10, count 0 2006.173.15:27:52.78#ibcon#about to write, iclass 10, count 0 2006.173.15:27:52.78#ibcon#wrote, iclass 10, count 0 2006.173.15:27:52.78#ibcon#about to read 3, iclass 10, count 0 2006.173.15:27:52.81#ibcon#read 3, iclass 10, count 0 2006.173.15:27:52.81#ibcon#about to read 4, iclass 10, count 0 2006.173.15:27:52.81#ibcon#read 4, iclass 10, count 0 2006.173.15:27:52.81#ibcon#about to read 5, iclass 10, count 0 2006.173.15:27:52.81#ibcon#read 5, iclass 10, count 0 2006.173.15:27:52.81#ibcon#about to read 6, iclass 10, count 0 2006.173.15:27:52.81#ibcon#read 6, iclass 10, count 0 2006.173.15:27:52.81#ibcon#end of sib2, iclass 10, count 0 2006.173.15:27:52.81#ibcon#*after write, iclass 10, count 0 2006.173.15:27:52.81#ibcon#*before return 0, iclass 10, count 0 2006.173.15:27:52.81#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.15:27:52.81#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.15:27:52.81#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.15:27:52.81#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.15:27:52.81$vck44/valo=5,734.99 2006.173.15:27:52.81#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.15:27:52.81#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.15:27:52.81#ibcon#ireg 17 cls_cnt 0 2006.173.15:27:52.81#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.15:27:52.81#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.15:27:52.81#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.15:27:52.81#ibcon#enter wrdev, iclass 12, count 0 2006.173.15:27:52.81#ibcon#first serial, iclass 12, count 0 2006.173.15:27:52.81#ibcon#enter sib2, iclass 12, count 0 2006.173.15:27:52.81#ibcon#flushed, iclass 12, count 0 2006.173.15:27:52.81#ibcon#about to write, iclass 12, count 0 2006.173.15:27:52.81#ibcon#wrote, iclass 12, count 0 2006.173.15:27:52.82#ibcon#about to read 3, iclass 12, count 0 2006.173.15:27:52.83#ibcon#read 3, iclass 12, count 0 2006.173.15:27:52.83#ibcon#about to read 4, iclass 12, count 0 2006.173.15:27:52.83#ibcon#read 4, iclass 12, count 0 2006.173.15:27:52.83#ibcon#about to read 5, iclass 12, count 0 2006.173.15:27:52.83#ibcon#read 5, iclass 12, count 0 2006.173.15:27:52.83#ibcon#about to read 6, iclass 12, count 0 2006.173.15:27:52.83#ibcon#read 6, iclass 12, count 0 2006.173.15:27:52.83#ibcon#end of sib2, iclass 12, count 0 2006.173.15:27:52.83#ibcon#*mode == 0, iclass 12, count 0 2006.173.15:27:52.83#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.15:27:52.83#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.15:27:52.83#ibcon#*before write, iclass 12, count 0 2006.173.15:27:52.83#ibcon#enter sib2, iclass 12, count 0 2006.173.15:27:52.83#ibcon#flushed, iclass 12, count 0 2006.173.15:27:52.83#ibcon#about to write, iclass 12, count 0 2006.173.15:27:52.83#ibcon#wrote, iclass 12, count 0 2006.173.15:27:52.83#ibcon#about to read 3, iclass 12, count 0 2006.173.15:27:52.87#ibcon#read 3, iclass 12, count 0 2006.173.15:27:52.87#ibcon#about to read 4, iclass 12, count 0 2006.173.15:27:52.87#ibcon#read 4, iclass 12, count 0 2006.173.15:27:52.87#ibcon#about to read 5, iclass 12, count 0 2006.173.15:27:52.87#ibcon#read 5, iclass 12, count 0 2006.173.15:27:52.87#ibcon#about to read 6, iclass 12, count 0 2006.173.15:27:52.87#ibcon#read 6, iclass 12, count 0 2006.173.15:27:52.87#ibcon#end of sib2, iclass 12, count 0 2006.173.15:27:52.87#ibcon#*after write, iclass 12, count 0 2006.173.15:27:52.87#ibcon#*before return 0, iclass 12, count 0 2006.173.15:27:52.87#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.15:27:52.87#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.15:27:52.87#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.15:27:52.87#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.15:27:52.87$vck44/va=5,4 2006.173.15:27:52.87#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.15:27:52.87#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.15:27:52.87#ibcon#ireg 11 cls_cnt 2 2006.173.15:27:52.87#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.15:27:52.93#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.15:27:52.93#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.15:27:52.93#ibcon#enter wrdev, iclass 14, count 2 2006.173.15:27:52.93#ibcon#first serial, iclass 14, count 2 2006.173.15:27:52.93#ibcon#enter sib2, iclass 14, count 2 2006.173.15:27:52.93#ibcon#flushed, iclass 14, count 2 2006.173.15:27:52.93#ibcon#about to write, iclass 14, count 2 2006.173.15:27:52.93#ibcon#wrote, iclass 14, count 2 2006.173.15:27:52.93#ibcon#about to read 3, iclass 14, count 2 2006.173.15:27:52.95#ibcon#read 3, iclass 14, count 2 2006.173.15:27:52.95#ibcon#about to read 4, iclass 14, count 2 2006.173.15:27:52.95#ibcon#read 4, iclass 14, count 2 2006.173.15:27:52.95#ibcon#about to read 5, iclass 14, count 2 2006.173.15:27:52.95#ibcon#read 5, iclass 14, count 2 2006.173.15:27:52.95#ibcon#about to read 6, iclass 14, count 2 2006.173.15:27:52.95#ibcon#read 6, iclass 14, count 2 2006.173.15:27:52.95#ibcon#end of sib2, iclass 14, count 2 2006.173.15:27:52.95#ibcon#*mode == 0, iclass 14, count 2 2006.173.15:27:52.95#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.15:27:52.95#ibcon#[25=AT05-04\r\n] 2006.173.15:27:52.95#ibcon#*before write, iclass 14, count 2 2006.173.15:27:52.95#ibcon#enter sib2, iclass 14, count 2 2006.173.15:27:52.95#ibcon#flushed, iclass 14, count 2 2006.173.15:27:52.95#ibcon#about to write, iclass 14, count 2 2006.173.15:27:52.95#ibcon#wrote, iclass 14, count 2 2006.173.15:27:52.95#ibcon#about to read 3, iclass 14, count 2 2006.173.15:27:52.98#ibcon#read 3, iclass 14, count 2 2006.173.15:27:52.98#ibcon#about to read 4, iclass 14, count 2 2006.173.15:27:52.98#ibcon#read 4, iclass 14, count 2 2006.173.15:27:52.98#ibcon#about to read 5, iclass 14, count 2 2006.173.15:27:52.98#ibcon#read 5, iclass 14, count 2 2006.173.15:27:52.98#ibcon#about to read 6, iclass 14, count 2 2006.173.15:27:52.98#ibcon#read 6, iclass 14, count 2 2006.173.15:27:52.98#ibcon#end of sib2, iclass 14, count 2 2006.173.15:27:52.98#ibcon#*after write, iclass 14, count 2 2006.173.15:27:52.98#ibcon#*before return 0, iclass 14, count 2 2006.173.15:27:52.98#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.15:27:52.98#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.15:27:52.98#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.15:27:52.98#ibcon#ireg 7 cls_cnt 0 2006.173.15:27:52.98#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.15:27:53.10#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.15:27:53.10#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.15:27:53.10#ibcon#enter wrdev, iclass 14, count 0 2006.173.15:27:53.10#ibcon#first serial, iclass 14, count 0 2006.173.15:27:53.10#ibcon#enter sib2, iclass 14, count 0 2006.173.15:27:53.10#ibcon#flushed, iclass 14, count 0 2006.173.15:27:53.10#ibcon#about to write, iclass 14, count 0 2006.173.15:27:53.10#ibcon#wrote, iclass 14, count 0 2006.173.15:27:53.10#ibcon#about to read 3, iclass 14, count 0 2006.173.15:27:53.12#ibcon#read 3, iclass 14, count 0 2006.173.15:27:53.12#ibcon#about to read 4, iclass 14, count 0 2006.173.15:27:53.12#ibcon#read 4, iclass 14, count 0 2006.173.15:27:53.12#ibcon#about to read 5, iclass 14, count 0 2006.173.15:27:53.12#ibcon#read 5, iclass 14, count 0 2006.173.15:27:53.12#ibcon#about to read 6, iclass 14, count 0 2006.173.15:27:53.12#ibcon#read 6, iclass 14, count 0 2006.173.15:27:53.12#ibcon#end of sib2, iclass 14, count 0 2006.173.15:27:53.12#ibcon#*mode == 0, iclass 14, count 0 2006.173.15:27:53.12#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.15:27:53.12#ibcon#[25=USB\r\n] 2006.173.15:27:53.12#ibcon#*before write, iclass 14, count 0 2006.173.15:27:53.12#ibcon#enter sib2, iclass 14, count 0 2006.173.15:27:53.12#ibcon#flushed, iclass 14, count 0 2006.173.15:27:53.12#ibcon#about to write, iclass 14, count 0 2006.173.15:27:53.12#ibcon#wrote, iclass 14, count 0 2006.173.15:27:53.12#ibcon#about to read 3, iclass 14, count 0 2006.173.15:27:53.15#ibcon#read 3, iclass 14, count 0 2006.173.15:27:53.15#ibcon#about to read 4, iclass 14, count 0 2006.173.15:27:53.15#ibcon#read 4, iclass 14, count 0 2006.173.15:27:53.15#ibcon#about to read 5, iclass 14, count 0 2006.173.15:27:53.15#ibcon#read 5, iclass 14, count 0 2006.173.15:27:53.15#ibcon#about to read 6, iclass 14, count 0 2006.173.15:27:53.15#ibcon#read 6, iclass 14, count 0 2006.173.15:27:53.15#ibcon#end of sib2, iclass 14, count 0 2006.173.15:27:53.15#ibcon#*after write, iclass 14, count 0 2006.173.15:27:53.15#ibcon#*before return 0, iclass 14, count 0 2006.173.15:27:53.15#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.15:27:53.15#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.15:27:53.15#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.15:27:53.15#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.15:27:53.15$vck44/valo=6,814.99 2006.173.15:27:53.15#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.15:27:53.15#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.15:27:53.15#ibcon#ireg 17 cls_cnt 0 2006.173.15:27:53.15#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.15:27:53.15#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.15:27:53.15#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.15:27:53.15#ibcon#enter wrdev, iclass 16, count 0 2006.173.15:27:53.15#ibcon#first serial, iclass 16, count 0 2006.173.15:27:53.15#ibcon#enter sib2, iclass 16, count 0 2006.173.15:27:53.15#ibcon#flushed, iclass 16, count 0 2006.173.15:27:53.15#ibcon#about to write, iclass 16, count 0 2006.173.15:27:53.16#ibcon#wrote, iclass 16, count 0 2006.173.15:27:53.16#ibcon#about to read 3, iclass 16, count 0 2006.173.15:27:53.17#ibcon#read 3, iclass 16, count 0 2006.173.15:27:53.17#ibcon#about to read 4, iclass 16, count 0 2006.173.15:27:53.17#ibcon#read 4, iclass 16, count 0 2006.173.15:27:53.17#ibcon#about to read 5, iclass 16, count 0 2006.173.15:27:53.17#ibcon#read 5, iclass 16, count 0 2006.173.15:27:53.17#ibcon#about to read 6, iclass 16, count 0 2006.173.15:27:53.17#ibcon#read 6, iclass 16, count 0 2006.173.15:27:53.17#ibcon#end of sib2, iclass 16, count 0 2006.173.15:27:53.17#ibcon#*mode == 0, iclass 16, count 0 2006.173.15:27:53.17#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.15:27:53.17#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.15:27:53.17#ibcon#*before write, iclass 16, count 0 2006.173.15:27:53.17#ibcon#enter sib2, iclass 16, count 0 2006.173.15:27:53.17#ibcon#flushed, iclass 16, count 0 2006.173.15:27:53.17#ibcon#about to write, iclass 16, count 0 2006.173.15:27:53.17#ibcon#wrote, iclass 16, count 0 2006.173.15:27:53.17#ibcon#about to read 3, iclass 16, count 0 2006.173.15:27:53.21#ibcon#read 3, iclass 16, count 0 2006.173.15:27:53.21#ibcon#about to read 4, iclass 16, count 0 2006.173.15:27:53.21#ibcon#read 4, iclass 16, count 0 2006.173.15:27:53.21#ibcon#about to read 5, iclass 16, count 0 2006.173.15:27:53.21#ibcon#read 5, iclass 16, count 0 2006.173.15:27:53.21#ibcon#about to read 6, iclass 16, count 0 2006.173.15:27:53.21#ibcon#read 6, iclass 16, count 0 2006.173.15:27:53.21#ibcon#end of sib2, iclass 16, count 0 2006.173.15:27:53.21#ibcon#*after write, iclass 16, count 0 2006.173.15:27:53.21#ibcon#*before return 0, iclass 16, count 0 2006.173.15:27:53.21#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.15:27:53.21#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.15:27:53.21#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.15:27:53.21#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.15:27:53.21$vck44/va=6,3 2006.173.15:27:53.21#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.15:27:53.21#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.15:27:53.21#ibcon#ireg 11 cls_cnt 2 2006.173.15:27:53.21#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.15:27:53.27#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.15:27:53.27#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.15:27:53.27#ibcon#enter wrdev, iclass 18, count 2 2006.173.15:27:53.27#ibcon#first serial, iclass 18, count 2 2006.173.15:27:53.27#ibcon#enter sib2, iclass 18, count 2 2006.173.15:27:53.27#ibcon#flushed, iclass 18, count 2 2006.173.15:27:53.27#ibcon#about to write, iclass 18, count 2 2006.173.15:27:53.27#ibcon#wrote, iclass 18, count 2 2006.173.15:27:53.27#ibcon#about to read 3, iclass 18, count 2 2006.173.15:27:53.29#ibcon#read 3, iclass 18, count 2 2006.173.15:27:53.29#ibcon#about to read 4, iclass 18, count 2 2006.173.15:27:53.29#ibcon#read 4, iclass 18, count 2 2006.173.15:27:53.29#ibcon#about to read 5, iclass 18, count 2 2006.173.15:27:53.29#ibcon#read 5, iclass 18, count 2 2006.173.15:27:53.29#ibcon#about to read 6, iclass 18, count 2 2006.173.15:27:53.29#ibcon#read 6, iclass 18, count 2 2006.173.15:27:53.29#ibcon#end of sib2, iclass 18, count 2 2006.173.15:27:53.29#ibcon#*mode == 0, iclass 18, count 2 2006.173.15:27:53.29#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.15:27:53.29#ibcon#[25=AT06-03\r\n] 2006.173.15:27:53.29#ibcon#*before write, iclass 18, count 2 2006.173.15:27:53.29#ibcon#enter sib2, iclass 18, count 2 2006.173.15:27:53.29#ibcon#flushed, iclass 18, count 2 2006.173.15:27:53.29#ibcon#about to write, iclass 18, count 2 2006.173.15:27:53.29#ibcon#wrote, iclass 18, count 2 2006.173.15:27:53.29#ibcon#about to read 3, iclass 18, count 2 2006.173.15:27:53.32#ibcon#read 3, iclass 18, count 2 2006.173.15:27:53.32#ibcon#about to read 4, iclass 18, count 2 2006.173.15:27:53.32#ibcon#read 4, iclass 18, count 2 2006.173.15:27:53.32#ibcon#about to read 5, iclass 18, count 2 2006.173.15:27:53.32#ibcon#read 5, iclass 18, count 2 2006.173.15:27:53.32#ibcon#about to read 6, iclass 18, count 2 2006.173.15:27:53.32#ibcon#read 6, iclass 18, count 2 2006.173.15:27:53.32#ibcon#end of sib2, iclass 18, count 2 2006.173.15:27:53.32#ibcon#*after write, iclass 18, count 2 2006.173.15:27:53.32#ibcon#*before return 0, iclass 18, count 2 2006.173.15:27:53.32#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.15:27:53.32#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.15:27:53.32#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.15:27:53.32#ibcon#ireg 7 cls_cnt 0 2006.173.15:27:53.32#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.15:27:53.44#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.15:27:53.44#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.15:27:53.44#ibcon#enter wrdev, iclass 18, count 0 2006.173.15:27:53.44#ibcon#first serial, iclass 18, count 0 2006.173.15:27:53.44#ibcon#enter sib2, iclass 18, count 0 2006.173.15:27:53.44#ibcon#flushed, iclass 18, count 0 2006.173.15:27:53.44#ibcon#about to write, iclass 18, count 0 2006.173.15:27:53.44#ibcon#wrote, iclass 18, count 0 2006.173.15:27:53.44#ibcon#about to read 3, iclass 18, count 0 2006.173.15:27:53.46#ibcon#read 3, iclass 18, count 0 2006.173.15:27:53.46#ibcon#about to read 4, iclass 18, count 0 2006.173.15:27:53.46#ibcon#read 4, iclass 18, count 0 2006.173.15:27:53.46#ibcon#about to read 5, iclass 18, count 0 2006.173.15:27:53.46#ibcon#read 5, iclass 18, count 0 2006.173.15:27:53.46#ibcon#about to read 6, iclass 18, count 0 2006.173.15:27:53.46#ibcon#read 6, iclass 18, count 0 2006.173.15:27:53.46#ibcon#end of sib2, iclass 18, count 0 2006.173.15:27:53.46#ibcon#*mode == 0, iclass 18, count 0 2006.173.15:27:53.46#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.15:27:53.46#ibcon#[25=USB\r\n] 2006.173.15:27:53.46#ibcon#*before write, iclass 18, count 0 2006.173.15:27:53.46#ibcon#enter sib2, iclass 18, count 0 2006.173.15:27:53.46#ibcon#flushed, iclass 18, count 0 2006.173.15:27:53.46#ibcon#about to write, iclass 18, count 0 2006.173.15:27:53.46#ibcon#wrote, iclass 18, count 0 2006.173.15:27:53.46#ibcon#about to read 3, iclass 18, count 0 2006.173.15:27:53.49#ibcon#read 3, iclass 18, count 0 2006.173.15:27:53.49#ibcon#about to read 4, iclass 18, count 0 2006.173.15:27:53.49#ibcon#read 4, iclass 18, count 0 2006.173.15:27:53.49#ibcon#about to read 5, iclass 18, count 0 2006.173.15:27:53.49#ibcon#read 5, iclass 18, count 0 2006.173.15:27:53.49#ibcon#about to read 6, iclass 18, count 0 2006.173.15:27:53.49#ibcon#read 6, iclass 18, count 0 2006.173.15:27:53.49#ibcon#end of sib2, iclass 18, count 0 2006.173.15:27:53.49#ibcon#*after write, iclass 18, count 0 2006.173.15:27:53.49#ibcon#*before return 0, iclass 18, count 0 2006.173.15:27:53.49#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.15:27:53.49#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.15:27:53.49#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.15:27:53.49#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.15:27:53.49$vck44/valo=7,864.99 2006.173.15:27:53.49#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.15:27:53.49#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.15:27:53.49#ibcon#ireg 17 cls_cnt 0 2006.173.15:27:53.49#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.15:27:53.49#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.15:27:53.49#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.15:27:53.49#ibcon#enter wrdev, iclass 20, count 0 2006.173.15:27:53.49#ibcon#first serial, iclass 20, count 0 2006.173.15:27:53.49#ibcon#enter sib2, iclass 20, count 0 2006.173.15:27:53.49#ibcon#flushed, iclass 20, count 0 2006.173.15:27:53.49#ibcon#about to write, iclass 20, count 0 2006.173.15:27:53.49#ibcon#wrote, iclass 20, count 0 2006.173.15:27:53.49#ibcon#about to read 3, iclass 20, count 0 2006.173.15:27:53.51#ibcon#read 3, iclass 20, count 0 2006.173.15:27:53.51#ibcon#about to read 4, iclass 20, count 0 2006.173.15:27:53.51#ibcon#read 4, iclass 20, count 0 2006.173.15:27:53.51#ibcon#about to read 5, iclass 20, count 0 2006.173.15:27:53.51#ibcon#read 5, iclass 20, count 0 2006.173.15:27:53.51#ibcon#about to read 6, iclass 20, count 0 2006.173.15:27:53.51#ibcon#read 6, iclass 20, count 0 2006.173.15:27:53.51#ibcon#end of sib2, iclass 20, count 0 2006.173.15:27:53.51#ibcon#*mode == 0, iclass 20, count 0 2006.173.15:27:53.51#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.15:27:53.51#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.15:27:53.51#ibcon#*before write, iclass 20, count 0 2006.173.15:27:53.51#ibcon#enter sib2, iclass 20, count 0 2006.173.15:27:53.51#ibcon#flushed, iclass 20, count 0 2006.173.15:27:53.51#ibcon#about to write, iclass 20, count 0 2006.173.15:27:53.51#ibcon#wrote, iclass 20, count 0 2006.173.15:27:53.51#ibcon#about to read 3, iclass 20, count 0 2006.173.15:27:53.55#ibcon#read 3, iclass 20, count 0 2006.173.15:27:53.55#ibcon#about to read 4, iclass 20, count 0 2006.173.15:27:53.55#ibcon#read 4, iclass 20, count 0 2006.173.15:27:53.55#ibcon#about to read 5, iclass 20, count 0 2006.173.15:27:53.55#ibcon#read 5, iclass 20, count 0 2006.173.15:27:53.55#ibcon#about to read 6, iclass 20, count 0 2006.173.15:27:53.55#ibcon#read 6, iclass 20, count 0 2006.173.15:27:53.55#ibcon#end of sib2, iclass 20, count 0 2006.173.15:27:53.55#ibcon#*after write, iclass 20, count 0 2006.173.15:27:53.55#ibcon#*before return 0, iclass 20, count 0 2006.173.15:27:53.55#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.15:27:53.55#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.15:27:53.55#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.15:27:53.55#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.15:27:53.55$vck44/va=7,4 2006.173.15:27:53.55#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.15:27:53.55#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.15:27:53.55#ibcon#ireg 11 cls_cnt 2 2006.173.15:27:53.55#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.15:27:53.61#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.15:27:53.61#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.15:27:53.61#ibcon#enter wrdev, iclass 22, count 2 2006.173.15:27:53.61#ibcon#first serial, iclass 22, count 2 2006.173.15:27:53.61#ibcon#enter sib2, iclass 22, count 2 2006.173.15:27:53.61#ibcon#flushed, iclass 22, count 2 2006.173.15:27:53.61#ibcon#about to write, iclass 22, count 2 2006.173.15:27:53.61#ibcon#wrote, iclass 22, count 2 2006.173.15:27:53.61#ibcon#about to read 3, iclass 22, count 2 2006.173.15:27:53.63#ibcon#read 3, iclass 22, count 2 2006.173.15:27:53.63#ibcon#about to read 4, iclass 22, count 2 2006.173.15:27:53.63#ibcon#read 4, iclass 22, count 2 2006.173.15:27:53.63#ibcon#about to read 5, iclass 22, count 2 2006.173.15:27:53.63#ibcon#read 5, iclass 22, count 2 2006.173.15:27:53.63#ibcon#about to read 6, iclass 22, count 2 2006.173.15:27:53.63#ibcon#read 6, iclass 22, count 2 2006.173.15:27:53.63#ibcon#end of sib2, iclass 22, count 2 2006.173.15:27:53.63#ibcon#*mode == 0, iclass 22, count 2 2006.173.15:27:53.63#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.15:27:53.63#ibcon#[25=AT07-04\r\n] 2006.173.15:27:53.63#ibcon#*before write, iclass 22, count 2 2006.173.15:27:53.63#ibcon#enter sib2, iclass 22, count 2 2006.173.15:27:53.63#ibcon#flushed, iclass 22, count 2 2006.173.15:27:53.63#ibcon#about to write, iclass 22, count 2 2006.173.15:27:53.63#ibcon#wrote, iclass 22, count 2 2006.173.15:27:53.63#ibcon#about to read 3, iclass 22, count 2 2006.173.15:27:53.66#ibcon#read 3, iclass 22, count 2 2006.173.15:27:53.66#ibcon#about to read 4, iclass 22, count 2 2006.173.15:27:53.66#ibcon#read 4, iclass 22, count 2 2006.173.15:27:53.66#ibcon#about to read 5, iclass 22, count 2 2006.173.15:27:53.66#ibcon#read 5, iclass 22, count 2 2006.173.15:27:53.66#ibcon#about to read 6, iclass 22, count 2 2006.173.15:27:53.66#ibcon#read 6, iclass 22, count 2 2006.173.15:27:53.66#ibcon#end of sib2, iclass 22, count 2 2006.173.15:27:53.66#ibcon#*after write, iclass 22, count 2 2006.173.15:27:53.66#ibcon#*before return 0, iclass 22, count 2 2006.173.15:27:53.66#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.15:27:53.66#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.15:27:53.66#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.15:27:53.66#ibcon#ireg 7 cls_cnt 0 2006.173.15:27:53.66#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.15:27:53.78#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.15:27:53.78#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.15:27:53.78#ibcon#enter wrdev, iclass 22, count 0 2006.173.15:27:53.78#ibcon#first serial, iclass 22, count 0 2006.173.15:27:53.78#ibcon#enter sib2, iclass 22, count 0 2006.173.15:27:53.78#ibcon#flushed, iclass 22, count 0 2006.173.15:27:53.78#ibcon#about to write, iclass 22, count 0 2006.173.15:27:53.78#ibcon#wrote, iclass 22, count 0 2006.173.15:27:53.78#ibcon#about to read 3, iclass 22, count 0 2006.173.15:27:53.80#ibcon#read 3, iclass 22, count 0 2006.173.15:27:53.80#ibcon#about to read 4, iclass 22, count 0 2006.173.15:27:53.80#ibcon#read 4, iclass 22, count 0 2006.173.15:27:53.80#ibcon#about to read 5, iclass 22, count 0 2006.173.15:27:53.80#ibcon#read 5, iclass 22, count 0 2006.173.15:27:53.80#ibcon#about to read 6, iclass 22, count 0 2006.173.15:27:53.80#ibcon#read 6, iclass 22, count 0 2006.173.15:27:53.80#ibcon#end of sib2, iclass 22, count 0 2006.173.15:27:53.80#ibcon#*mode == 0, iclass 22, count 0 2006.173.15:27:53.80#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.15:27:53.80#ibcon#[25=USB\r\n] 2006.173.15:27:53.80#ibcon#*before write, iclass 22, count 0 2006.173.15:27:53.80#ibcon#enter sib2, iclass 22, count 0 2006.173.15:27:53.80#ibcon#flushed, iclass 22, count 0 2006.173.15:27:53.80#ibcon#about to write, iclass 22, count 0 2006.173.15:27:53.80#ibcon#wrote, iclass 22, count 0 2006.173.15:27:53.80#ibcon#about to read 3, iclass 22, count 0 2006.173.15:27:53.83#ibcon#read 3, iclass 22, count 0 2006.173.15:27:53.83#ibcon#about to read 4, iclass 22, count 0 2006.173.15:27:53.83#ibcon#read 4, iclass 22, count 0 2006.173.15:27:53.83#ibcon#about to read 5, iclass 22, count 0 2006.173.15:27:53.83#ibcon#read 5, iclass 22, count 0 2006.173.15:27:53.83#ibcon#about to read 6, iclass 22, count 0 2006.173.15:27:53.83#ibcon#read 6, iclass 22, count 0 2006.173.15:27:53.83#ibcon#end of sib2, iclass 22, count 0 2006.173.15:27:53.83#ibcon#*after write, iclass 22, count 0 2006.173.15:27:53.83#ibcon#*before return 0, iclass 22, count 0 2006.173.15:27:53.83#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.15:27:53.83#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.15:27:53.83#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.15:27:53.83#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.15:27:53.83$vck44/valo=8,884.99 2006.173.15:27:53.83#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.15:27:53.83#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.15:27:53.83#ibcon#ireg 17 cls_cnt 0 2006.173.15:27:53.83#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.15:27:53.83#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.15:27:53.83#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.15:27:53.83#ibcon#enter wrdev, iclass 24, count 0 2006.173.15:27:53.83#ibcon#first serial, iclass 24, count 0 2006.173.15:27:53.83#ibcon#enter sib2, iclass 24, count 0 2006.173.15:27:53.83#ibcon#flushed, iclass 24, count 0 2006.173.15:27:53.83#ibcon#about to write, iclass 24, count 0 2006.173.15:27:53.84#ibcon#wrote, iclass 24, count 0 2006.173.15:27:53.84#ibcon#about to read 3, iclass 24, count 0 2006.173.15:27:53.85#ibcon#read 3, iclass 24, count 0 2006.173.15:27:53.85#ibcon#about to read 4, iclass 24, count 0 2006.173.15:27:53.85#ibcon#read 4, iclass 24, count 0 2006.173.15:27:53.85#ibcon#about to read 5, iclass 24, count 0 2006.173.15:27:53.85#ibcon#read 5, iclass 24, count 0 2006.173.15:27:53.85#ibcon#about to read 6, iclass 24, count 0 2006.173.15:27:53.85#ibcon#read 6, iclass 24, count 0 2006.173.15:27:53.85#ibcon#end of sib2, iclass 24, count 0 2006.173.15:27:53.85#ibcon#*mode == 0, iclass 24, count 0 2006.173.15:27:53.85#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.15:27:53.85#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.15:27:53.85#ibcon#*before write, iclass 24, count 0 2006.173.15:27:53.85#ibcon#enter sib2, iclass 24, count 0 2006.173.15:27:53.85#ibcon#flushed, iclass 24, count 0 2006.173.15:27:53.85#ibcon#about to write, iclass 24, count 0 2006.173.15:27:53.85#ibcon#wrote, iclass 24, count 0 2006.173.15:27:53.85#ibcon#about to read 3, iclass 24, count 0 2006.173.15:27:53.89#ibcon#read 3, iclass 24, count 0 2006.173.15:27:53.89#ibcon#about to read 4, iclass 24, count 0 2006.173.15:27:53.89#ibcon#read 4, iclass 24, count 0 2006.173.15:27:53.89#ibcon#about to read 5, iclass 24, count 0 2006.173.15:27:53.89#ibcon#read 5, iclass 24, count 0 2006.173.15:27:53.89#ibcon#about to read 6, iclass 24, count 0 2006.173.15:27:53.89#ibcon#read 6, iclass 24, count 0 2006.173.15:27:53.89#ibcon#end of sib2, iclass 24, count 0 2006.173.15:27:53.89#ibcon#*after write, iclass 24, count 0 2006.173.15:27:53.89#ibcon#*before return 0, iclass 24, count 0 2006.173.15:27:53.89#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.15:27:53.89#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.15:27:53.89#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.15:27:53.89#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.15:27:53.89$vck44/va=8,4 2006.173.15:27:53.89#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.15:27:53.89#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.15:27:53.89#ibcon#ireg 11 cls_cnt 2 2006.173.15:27:53.89#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.15:27:53.95#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.15:27:53.95#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.15:27:53.95#ibcon#enter wrdev, iclass 26, count 2 2006.173.15:27:53.95#ibcon#first serial, iclass 26, count 2 2006.173.15:27:53.95#ibcon#enter sib2, iclass 26, count 2 2006.173.15:27:53.95#ibcon#flushed, iclass 26, count 2 2006.173.15:27:53.95#ibcon#about to write, iclass 26, count 2 2006.173.15:27:53.95#ibcon#wrote, iclass 26, count 2 2006.173.15:27:53.95#ibcon#about to read 3, iclass 26, count 2 2006.173.15:27:53.97#ibcon#read 3, iclass 26, count 2 2006.173.15:27:53.97#ibcon#about to read 4, iclass 26, count 2 2006.173.15:27:53.97#ibcon#read 4, iclass 26, count 2 2006.173.15:27:53.97#ibcon#about to read 5, iclass 26, count 2 2006.173.15:27:53.97#ibcon#read 5, iclass 26, count 2 2006.173.15:27:53.97#ibcon#about to read 6, iclass 26, count 2 2006.173.15:27:53.97#ibcon#read 6, iclass 26, count 2 2006.173.15:27:53.97#ibcon#end of sib2, iclass 26, count 2 2006.173.15:27:53.97#ibcon#*mode == 0, iclass 26, count 2 2006.173.15:27:53.97#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.15:27:53.97#ibcon#[25=AT08-04\r\n] 2006.173.15:27:53.97#ibcon#*before write, iclass 26, count 2 2006.173.15:27:53.97#ibcon#enter sib2, iclass 26, count 2 2006.173.15:27:53.97#ibcon#flushed, iclass 26, count 2 2006.173.15:27:53.97#ibcon#about to write, iclass 26, count 2 2006.173.15:27:53.97#ibcon#wrote, iclass 26, count 2 2006.173.15:27:53.97#ibcon#about to read 3, iclass 26, count 2 2006.173.15:27:54.00#ibcon#read 3, iclass 26, count 2 2006.173.15:27:54.00#ibcon#about to read 4, iclass 26, count 2 2006.173.15:27:54.00#ibcon#read 4, iclass 26, count 2 2006.173.15:27:54.00#ibcon#about to read 5, iclass 26, count 2 2006.173.15:27:54.00#ibcon#read 5, iclass 26, count 2 2006.173.15:27:54.00#ibcon#about to read 6, iclass 26, count 2 2006.173.15:27:54.00#ibcon#read 6, iclass 26, count 2 2006.173.15:27:54.00#ibcon#end of sib2, iclass 26, count 2 2006.173.15:27:54.00#ibcon#*after write, iclass 26, count 2 2006.173.15:27:54.00#ibcon#*before return 0, iclass 26, count 2 2006.173.15:27:54.00#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.15:27:54.00#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.15:27:54.00#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.15:27:54.00#ibcon#ireg 7 cls_cnt 0 2006.173.15:27:54.00#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.15:27:54.12#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.15:27:54.12#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.15:27:54.12#ibcon#enter wrdev, iclass 26, count 0 2006.173.15:27:54.12#ibcon#first serial, iclass 26, count 0 2006.173.15:27:54.12#ibcon#enter sib2, iclass 26, count 0 2006.173.15:27:54.12#ibcon#flushed, iclass 26, count 0 2006.173.15:27:54.12#ibcon#about to write, iclass 26, count 0 2006.173.15:27:54.12#ibcon#wrote, iclass 26, count 0 2006.173.15:27:54.12#ibcon#about to read 3, iclass 26, count 0 2006.173.15:27:54.14#ibcon#read 3, iclass 26, count 0 2006.173.15:27:54.14#ibcon#about to read 4, iclass 26, count 0 2006.173.15:27:54.14#ibcon#read 4, iclass 26, count 0 2006.173.15:27:54.14#ibcon#about to read 5, iclass 26, count 0 2006.173.15:27:54.14#ibcon#read 5, iclass 26, count 0 2006.173.15:27:54.14#ibcon#about to read 6, iclass 26, count 0 2006.173.15:27:54.14#ibcon#read 6, iclass 26, count 0 2006.173.15:27:54.14#ibcon#end of sib2, iclass 26, count 0 2006.173.15:27:54.14#ibcon#*mode == 0, iclass 26, count 0 2006.173.15:27:54.14#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.15:27:54.14#ibcon#[25=USB\r\n] 2006.173.15:27:54.14#ibcon#*before write, iclass 26, count 0 2006.173.15:27:54.14#ibcon#enter sib2, iclass 26, count 0 2006.173.15:27:54.14#ibcon#flushed, iclass 26, count 0 2006.173.15:27:54.14#ibcon#about to write, iclass 26, count 0 2006.173.15:27:54.14#ibcon#wrote, iclass 26, count 0 2006.173.15:27:54.14#ibcon#about to read 3, iclass 26, count 0 2006.173.15:27:54.17#ibcon#read 3, iclass 26, count 0 2006.173.15:27:54.17#ibcon#about to read 4, iclass 26, count 0 2006.173.15:27:54.17#ibcon#read 4, iclass 26, count 0 2006.173.15:27:54.17#ibcon#about to read 5, iclass 26, count 0 2006.173.15:27:54.17#ibcon#read 5, iclass 26, count 0 2006.173.15:27:54.17#ibcon#about to read 6, iclass 26, count 0 2006.173.15:27:54.17#ibcon#read 6, iclass 26, count 0 2006.173.15:27:54.17#ibcon#end of sib2, iclass 26, count 0 2006.173.15:27:54.17#ibcon#*after write, iclass 26, count 0 2006.173.15:27:54.17#ibcon#*before return 0, iclass 26, count 0 2006.173.15:27:54.17#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.15:27:54.17#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.15:27:54.17#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.15:27:54.17#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.15:27:54.17$vck44/vblo=1,629.99 2006.173.15:27:54.17#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.15:27:54.17#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.15:27:54.17#ibcon#ireg 17 cls_cnt 0 2006.173.15:27:54.17#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.15:27:54.17#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.15:27:54.17#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.15:27:54.17#ibcon#enter wrdev, iclass 28, count 0 2006.173.15:27:54.17#ibcon#first serial, iclass 28, count 0 2006.173.15:27:54.17#ibcon#enter sib2, iclass 28, count 0 2006.173.15:27:54.17#ibcon#flushed, iclass 28, count 0 2006.173.15:27:54.18#ibcon#about to write, iclass 28, count 0 2006.173.15:27:54.18#ibcon#wrote, iclass 28, count 0 2006.173.15:27:54.18#ibcon#about to read 3, iclass 28, count 0 2006.173.15:27:54.19#ibcon#read 3, iclass 28, count 0 2006.173.15:27:54.19#ibcon#about to read 4, iclass 28, count 0 2006.173.15:27:54.19#ibcon#read 4, iclass 28, count 0 2006.173.15:27:54.19#ibcon#about to read 5, iclass 28, count 0 2006.173.15:27:54.19#ibcon#read 5, iclass 28, count 0 2006.173.15:27:54.19#ibcon#about to read 6, iclass 28, count 0 2006.173.15:27:54.19#ibcon#read 6, iclass 28, count 0 2006.173.15:27:54.19#ibcon#end of sib2, iclass 28, count 0 2006.173.15:27:54.19#ibcon#*mode == 0, iclass 28, count 0 2006.173.15:27:54.19#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.15:27:54.19#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.15:27:54.19#ibcon#*before write, iclass 28, count 0 2006.173.15:27:54.19#ibcon#enter sib2, iclass 28, count 0 2006.173.15:27:54.19#ibcon#flushed, iclass 28, count 0 2006.173.15:27:54.19#ibcon#about to write, iclass 28, count 0 2006.173.15:27:54.19#ibcon#wrote, iclass 28, count 0 2006.173.15:27:54.19#ibcon#about to read 3, iclass 28, count 0 2006.173.15:27:54.23#ibcon#read 3, iclass 28, count 0 2006.173.15:27:54.23#ibcon#about to read 4, iclass 28, count 0 2006.173.15:27:54.23#ibcon#read 4, iclass 28, count 0 2006.173.15:27:54.23#ibcon#about to read 5, iclass 28, count 0 2006.173.15:27:54.23#ibcon#read 5, iclass 28, count 0 2006.173.15:27:54.23#ibcon#about to read 6, iclass 28, count 0 2006.173.15:27:54.23#ibcon#read 6, iclass 28, count 0 2006.173.15:27:54.23#ibcon#end of sib2, iclass 28, count 0 2006.173.15:27:54.23#ibcon#*after write, iclass 28, count 0 2006.173.15:27:54.23#ibcon#*before return 0, iclass 28, count 0 2006.173.15:27:54.23#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.15:27:54.23#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.15:27:54.23#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.15:27:54.23#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.15:27:54.23$vck44/vb=1,4 2006.173.15:27:54.23#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.15:27:54.23#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.15:27:54.23#ibcon#ireg 11 cls_cnt 2 2006.173.15:27:54.23#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.15:27:54.23#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.15:27:54.23#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.15:27:54.23#ibcon#enter wrdev, iclass 30, count 2 2006.173.15:27:54.23#ibcon#first serial, iclass 30, count 2 2006.173.15:27:54.23#ibcon#enter sib2, iclass 30, count 2 2006.173.15:27:54.23#ibcon#flushed, iclass 30, count 2 2006.173.15:27:54.23#ibcon#about to write, iclass 30, count 2 2006.173.15:27:54.23#ibcon#wrote, iclass 30, count 2 2006.173.15:27:54.24#ibcon#about to read 3, iclass 30, count 2 2006.173.15:27:54.25#ibcon#read 3, iclass 30, count 2 2006.173.15:27:54.25#ibcon#about to read 4, iclass 30, count 2 2006.173.15:27:54.25#ibcon#read 4, iclass 30, count 2 2006.173.15:27:54.25#ibcon#about to read 5, iclass 30, count 2 2006.173.15:27:54.25#ibcon#read 5, iclass 30, count 2 2006.173.15:27:54.25#ibcon#about to read 6, iclass 30, count 2 2006.173.15:27:54.25#ibcon#read 6, iclass 30, count 2 2006.173.15:27:54.25#ibcon#end of sib2, iclass 30, count 2 2006.173.15:27:54.25#ibcon#*mode == 0, iclass 30, count 2 2006.173.15:27:54.25#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.15:27:54.25#ibcon#[27=AT01-04\r\n] 2006.173.15:27:54.25#ibcon#*before write, iclass 30, count 2 2006.173.15:27:54.25#ibcon#enter sib2, iclass 30, count 2 2006.173.15:27:54.25#ibcon#flushed, iclass 30, count 2 2006.173.15:27:54.25#ibcon#about to write, iclass 30, count 2 2006.173.15:27:54.25#ibcon#wrote, iclass 30, count 2 2006.173.15:27:54.25#ibcon#about to read 3, iclass 30, count 2 2006.173.15:27:54.28#ibcon#read 3, iclass 30, count 2 2006.173.15:27:54.28#ibcon#about to read 4, iclass 30, count 2 2006.173.15:27:54.28#ibcon#read 4, iclass 30, count 2 2006.173.15:27:54.28#ibcon#about to read 5, iclass 30, count 2 2006.173.15:27:54.28#ibcon#read 5, iclass 30, count 2 2006.173.15:27:54.28#ibcon#about to read 6, iclass 30, count 2 2006.173.15:27:54.28#ibcon#read 6, iclass 30, count 2 2006.173.15:27:54.28#ibcon#end of sib2, iclass 30, count 2 2006.173.15:27:54.28#ibcon#*after write, iclass 30, count 2 2006.173.15:27:54.28#ibcon#*before return 0, iclass 30, count 2 2006.173.15:27:54.28#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.15:27:54.28#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.15:27:54.28#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.15:27:54.28#ibcon#ireg 7 cls_cnt 0 2006.173.15:27:54.28#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.15:27:54.40#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.15:27:54.40#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.15:27:54.40#ibcon#enter wrdev, iclass 30, count 0 2006.173.15:27:54.40#ibcon#first serial, iclass 30, count 0 2006.173.15:27:54.40#ibcon#enter sib2, iclass 30, count 0 2006.173.15:27:54.40#ibcon#flushed, iclass 30, count 0 2006.173.15:27:54.40#ibcon#about to write, iclass 30, count 0 2006.173.15:27:54.40#ibcon#wrote, iclass 30, count 0 2006.173.15:27:54.40#ibcon#about to read 3, iclass 30, count 0 2006.173.15:27:54.42#ibcon#read 3, iclass 30, count 0 2006.173.15:27:54.42#ibcon#about to read 4, iclass 30, count 0 2006.173.15:27:54.42#ibcon#read 4, iclass 30, count 0 2006.173.15:27:54.42#ibcon#about to read 5, iclass 30, count 0 2006.173.15:27:54.42#ibcon#read 5, iclass 30, count 0 2006.173.15:27:54.42#ibcon#about to read 6, iclass 30, count 0 2006.173.15:27:54.42#ibcon#read 6, iclass 30, count 0 2006.173.15:27:54.42#ibcon#end of sib2, iclass 30, count 0 2006.173.15:27:54.42#ibcon#*mode == 0, iclass 30, count 0 2006.173.15:27:54.42#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.15:27:54.42#ibcon#[27=USB\r\n] 2006.173.15:27:54.42#ibcon#*before write, iclass 30, count 0 2006.173.15:27:54.42#ibcon#enter sib2, iclass 30, count 0 2006.173.15:27:54.42#ibcon#flushed, iclass 30, count 0 2006.173.15:27:54.42#ibcon#about to write, iclass 30, count 0 2006.173.15:27:54.42#ibcon#wrote, iclass 30, count 0 2006.173.15:27:54.42#ibcon#about to read 3, iclass 30, count 0 2006.173.15:27:54.45#ibcon#read 3, iclass 30, count 0 2006.173.15:27:54.45#ibcon#about to read 4, iclass 30, count 0 2006.173.15:27:54.45#ibcon#read 4, iclass 30, count 0 2006.173.15:27:54.45#ibcon#about to read 5, iclass 30, count 0 2006.173.15:27:54.45#ibcon#read 5, iclass 30, count 0 2006.173.15:27:54.45#ibcon#about to read 6, iclass 30, count 0 2006.173.15:27:54.45#ibcon#read 6, iclass 30, count 0 2006.173.15:27:54.45#ibcon#end of sib2, iclass 30, count 0 2006.173.15:27:54.45#ibcon#*after write, iclass 30, count 0 2006.173.15:27:54.45#ibcon#*before return 0, iclass 30, count 0 2006.173.15:27:54.45#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.15:27:54.45#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.15:27:54.45#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.15:27:54.45#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.15:27:54.45$vck44/vblo=2,634.99 2006.173.15:27:54.45#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.15:27:54.45#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.15:27:54.45#ibcon#ireg 17 cls_cnt 0 2006.173.15:27:54.45#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.15:27:54.45#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.15:27:54.45#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.15:27:54.45#ibcon#enter wrdev, iclass 32, count 0 2006.173.15:27:54.45#ibcon#first serial, iclass 32, count 0 2006.173.15:27:54.45#ibcon#enter sib2, iclass 32, count 0 2006.173.15:27:54.45#ibcon#flushed, iclass 32, count 0 2006.173.15:27:54.46#ibcon#about to write, iclass 32, count 0 2006.173.15:27:54.46#ibcon#wrote, iclass 32, count 0 2006.173.15:27:54.46#ibcon#about to read 3, iclass 32, count 0 2006.173.15:27:54.47#ibcon#read 3, iclass 32, count 0 2006.173.15:27:54.47#ibcon#about to read 4, iclass 32, count 0 2006.173.15:27:54.47#ibcon#read 4, iclass 32, count 0 2006.173.15:27:54.47#ibcon#about to read 5, iclass 32, count 0 2006.173.15:27:54.47#ibcon#read 5, iclass 32, count 0 2006.173.15:27:54.47#ibcon#about to read 6, iclass 32, count 0 2006.173.15:27:54.47#ibcon#read 6, iclass 32, count 0 2006.173.15:27:54.47#ibcon#end of sib2, iclass 32, count 0 2006.173.15:27:54.47#ibcon#*mode == 0, iclass 32, count 0 2006.173.15:27:54.47#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.15:27:54.47#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.15:27:54.47#ibcon#*before write, iclass 32, count 0 2006.173.15:27:54.47#ibcon#enter sib2, iclass 32, count 0 2006.173.15:27:54.47#ibcon#flushed, iclass 32, count 0 2006.173.15:27:54.47#ibcon#about to write, iclass 32, count 0 2006.173.15:27:54.47#ibcon#wrote, iclass 32, count 0 2006.173.15:27:54.47#ibcon#about to read 3, iclass 32, count 0 2006.173.15:27:54.51#ibcon#read 3, iclass 32, count 0 2006.173.15:27:54.51#ibcon#about to read 4, iclass 32, count 0 2006.173.15:27:54.51#ibcon#read 4, iclass 32, count 0 2006.173.15:27:54.51#ibcon#about to read 5, iclass 32, count 0 2006.173.15:27:54.51#ibcon#read 5, iclass 32, count 0 2006.173.15:27:54.51#ibcon#about to read 6, iclass 32, count 0 2006.173.15:27:54.51#ibcon#read 6, iclass 32, count 0 2006.173.15:27:54.51#ibcon#end of sib2, iclass 32, count 0 2006.173.15:27:54.51#ibcon#*after write, iclass 32, count 0 2006.173.15:27:54.51#ibcon#*before return 0, iclass 32, count 0 2006.173.15:27:54.51#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.15:27:54.51#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.15:27:54.51#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.15:27:54.51#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.15:27:54.51$vck44/vb=2,4 2006.173.15:27:54.51#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.15:27:54.51#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.15:27:54.51#ibcon#ireg 11 cls_cnt 2 2006.173.15:27:54.51#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.15:27:54.57#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.15:27:54.57#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.15:27:54.57#ibcon#enter wrdev, iclass 34, count 2 2006.173.15:27:54.57#ibcon#first serial, iclass 34, count 2 2006.173.15:27:54.57#ibcon#enter sib2, iclass 34, count 2 2006.173.15:27:54.57#ibcon#flushed, iclass 34, count 2 2006.173.15:27:54.57#ibcon#about to write, iclass 34, count 2 2006.173.15:27:54.57#ibcon#wrote, iclass 34, count 2 2006.173.15:27:54.57#ibcon#about to read 3, iclass 34, count 2 2006.173.15:27:54.59#ibcon#read 3, iclass 34, count 2 2006.173.15:27:54.59#ibcon#about to read 4, iclass 34, count 2 2006.173.15:27:54.59#ibcon#read 4, iclass 34, count 2 2006.173.15:27:54.59#ibcon#about to read 5, iclass 34, count 2 2006.173.15:27:54.59#ibcon#read 5, iclass 34, count 2 2006.173.15:27:54.59#ibcon#about to read 6, iclass 34, count 2 2006.173.15:27:54.59#ibcon#read 6, iclass 34, count 2 2006.173.15:27:54.59#ibcon#end of sib2, iclass 34, count 2 2006.173.15:27:54.59#ibcon#*mode == 0, iclass 34, count 2 2006.173.15:27:54.59#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.15:27:54.59#ibcon#[27=AT02-04\r\n] 2006.173.15:27:54.59#ibcon#*before write, iclass 34, count 2 2006.173.15:27:54.59#ibcon#enter sib2, iclass 34, count 2 2006.173.15:27:54.59#ibcon#flushed, iclass 34, count 2 2006.173.15:27:54.59#ibcon#about to write, iclass 34, count 2 2006.173.15:27:54.59#ibcon#wrote, iclass 34, count 2 2006.173.15:27:54.59#ibcon#about to read 3, iclass 34, count 2 2006.173.15:27:54.62#ibcon#read 3, iclass 34, count 2 2006.173.15:27:54.62#ibcon#about to read 4, iclass 34, count 2 2006.173.15:27:54.62#ibcon#read 4, iclass 34, count 2 2006.173.15:27:54.62#ibcon#about to read 5, iclass 34, count 2 2006.173.15:27:54.62#ibcon#read 5, iclass 34, count 2 2006.173.15:27:54.62#ibcon#about to read 6, iclass 34, count 2 2006.173.15:27:54.62#ibcon#read 6, iclass 34, count 2 2006.173.15:27:54.62#ibcon#end of sib2, iclass 34, count 2 2006.173.15:27:54.62#ibcon#*after write, iclass 34, count 2 2006.173.15:27:54.62#ibcon#*before return 0, iclass 34, count 2 2006.173.15:27:54.62#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.15:27:54.62#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.15:27:54.62#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.15:27:54.62#ibcon#ireg 7 cls_cnt 0 2006.173.15:27:54.62#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.15:27:54.74#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.15:27:54.74#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.15:27:54.74#ibcon#enter wrdev, iclass 34, count 0 2006.173.15:27:54.74#ibcon#first serial, iclass 34, count 0 2006.173.15:27:54.74#ibcon#enter sib2, iclass 34, count 0 2006.173.15:27:54.74#ibcon#flushed, iclass 34, count 0 2006.173.15:27:54.74#ibcon#about to write, iclass 34, count 0 2006.173.15:27:54.74#ibcon#wrote, iclass 34, count 0 2006.173.15:27:54.74#ibcon#about to read 3, iclass 34, count 0 2006.173.15:27:54.76#ibcon#read 3, iclass 34, count 0 2006.173.15:27:54.76#ibcon#about to read 4, iclass 34, count 0 2006.173.15:27:54.76#ibcon#read 4, iclass 34, count 0 2006.173.15:27:54.76#ibcon#about to read 5, iclass 34, count 0 2006.173.15:27:54.76#ibcon#read 5, iclass 34, count 0 2006.173.15:27:54.76#ibcon#about to read 6, iclass 34, count 0 2006.173.15:27:54.76#ibcon#read 6, iclass 34, count 0 2006.173.15:27:54.76#ibcon#end of sib2, iclass 34, count 0 2006.173.15:27:54.76#ibcon#*mode == 0, iclass 34, count 0 2006.173.15:27:54.76#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.15:27:54.76#ibcon#[27=USB\r\n] 2006.173.15:27:54.76#ibcon#*before write, iclass 34, count 0 2006.173.15:27:54.76#ibcon#enter sib2, iclass 34, count 0 2006.173.15:27:54.76#ibcon#flushed, iclass 34, count 0 2006.173.15:27:54.76#ibcon#about to write, iclass 34, count 0 2006.173.15:27:54.76#ibcon#wrote, iclass 34, count 0 2006.173.15:27:54.76#ibcon#about to read 3, iclass 34, count 0 2006.173.15:27:54.79#ibcon#read 3, iclass 34, count 0 2006.173.15:27:54.79#ibcon#about to read 4, iclass 34, count 0 2006.173.15:27:54.79#ibcon#read 4, iclass 34, count 0 2006.173.15:27:54.79#ibcon#about to read 5, iclass 34, count 0 2006.173.15:27:54.79#ibcon#read 5, iclass 34, count 0 2006.173.15:27:54.79#ibcon#about to read 6, iclass 34, count 0 2006.173.15:27:54.79#ibcon#read 6, iclass 34, count 0 2006.173.15:27:54.79#ibcon#end of sib2, iclass 34, count 0 2006.173.15:27:54.79#ibcon#*after write, iclass 34, count 0 2006.173.15:27:54.79#ibcon#*before return 0, iclass 34, count 0 2006.173.15:27:54.79#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.15:27:54.79#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.15:27:54.79#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.15:27:54.79#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.15:27:54.79$vck44/vblo=3,649.99 2006.173.15:27:54.79#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.15:27:54.79#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.15:27:54.79#ibcon#ireg 17 cls_cnt 0 2006.173.15:27:54.79#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.15:27:54.79#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.15:27:54.79#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.15:27:54.80#ibcon#enter wrdev, iclass 36, count 0 2006.173.15:27:54.80#ibcon#first serial, iclass 36, count 0 2006.173.15:27:54.80#ibcon#enter sib2, iclass 36, count 0 2006.173.15:27:54.80#ibcon#flushed, iclass 36, count 0 2006.173.15:27:54.80#ibcon#about to write, iclass 36, count 0 2006.173.15:27:54.80#ibcon#wrote, iclass 36, count 0 2006.173.15:27:54.80#ibcon#about to read 3, iclass 36, count 0 2006.173.15:27:54.81#ibcon#read 3, iclass 36, count 0 2006.173.15:27:54.81#ibcon#about to read 4, iclass 36, count 0 2006.173.15:27:54.81#ibcon#read 4, iclass 36, count 0 2006.173.15:27:54.81#ibcon#about to read 5, iclass 36, count 0 2006.173.15:27:54.81#ibcon#read 5, iclass 36, count 0 2006.173.15:27:54.81#ibcon#about to read 6, iclass 36, count 0 2006.173.15:27:54.81#ibcon#read 6, iclass 36, count 0 2006.173.15:27:54.81#ibcon#end of sib2, iclass 36, count 0 2006.173.15:27:54.81#ibcon#*mode == 0, iclass 36, count 0 2006.173.15:27:54.81#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.15:27:54.81#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.15:27:54.81#ibcon#*before write, iclass 36, count 0 2006.173.15:27:54.81#ibcon#enter sib2, iclass 36, count 0 2006.173.15:27:54.81#ibcon#flushed, iclass 36, count 0 2006.173.15:27:54.81#ibcon#about to write, iclass 36, count 0 2006.173.15:27:54.81#ibcon#wrote, iclass 36, count 0 2006.173.15:27:54.81#ibcon#about to read 3, iclass 36, count 0 2006.173.15:27:54.85#ibcon#read 3, iclass 36, count 0 2006.173.15:27:54.85#ibcon#about to read 4, iclass 36, count 0 2006.173.15:27:54.85#ibcon#read 4, iclass 36, count 0 2006.173.15:27:54.85#ibcon#about to read 5, iclass 36, count 0 2006.173.15:27:54.85#ibcon#read 5, iclass 36, count 0 2006.173.15:27:54.85#ibcon#about to read 6, iclass 36, count 0 2006.173.15:27:54.85#ibcon#read 6, iclass 36, count 0 2006.173.15:27:54.85#ibcon#end of sib2, iclass 36, count 0 2006.173.15:27:54.85#ibcon#*after write, iclass 36, count 0 2006.173.15:27:54.85#ibcon#*before return 0, iclass 36, count 0 2006.173.15:27:54.85#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.15:27:54.85#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.15:27:54.85#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.15:27:54.85#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.15:27:54.85$vck44/vb=3,4 2006.173.15:27:54.85#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.15:27:54.85#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.15:27:54.85#ibcon#ireg 11 cls_cnt 2 2006.173.15:27:54.85#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.15:27:54.91#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.15:27:54.91#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.15:27:54.91#ibcon#enter wrdev, iclass 38, count 2 2006.173.15:27:54.91#ibcon#first serial, iclass 38, count 2 2006.173.15:27:54.91#ibcon#enter sib2, iclass 38, count 2 2006.173.15:27:54.91#ibcon#flushed, iclass 38, count 2 2006.173.15:27:54.91#ibcon#about to write, iclass 38, count 2 2006.173.15:27:54.91#ibcon#wrote, iclass 38, count 2 2006.173.15:27:54.91#ibcon#about to read 3, iclass 38, count 2 2006.173.15:27:54.93#ibcon#read 3, iclass 38, count 2 2006.173.15:27:54.93#ibcon#about to read 4, iclass 38, count 2 2006.173.15:27:54.93#ibcon#read 4, iclass 38, count 2 2006.173.15:27:54.93#ibcon#about to read 5, iclass 38, count 2 2006.173.15:27:54.93#ibcon#read 5, iclass 38, count 2 2006.173.15:27:54.93#ibcon#about to read 6, iclass 38, count 2 2006.173.15:27:54.93#ibcon#read 6, iclass 38, count 2 2006.173.15:27:54.93#ibcon#end of sib2, iclass 38, count 2 2006.173.15:27:54.93#ibcon#*mode == 0, iclass 38, count 2 2006.173.15:27:54.93#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.15:27:54.93#ibcon#[27=AT03-04\r\n] 2006.173.15:27:54.93#ibcon#*before write, iclass 38, count 2 2006.173.15:27:54.93#ibcon#enter sib2, iclass 38, count 2 2006.173.15:27:54.93#ibcon#flushed, iclass 38, count 2 2006.173.15:27:54.93#ibcon#about to write, iclass 38, count 2 2006.173.15:27:54.93#ibcon#wrote, iclass 38, count 2 2006.173.15:27:54.93#ibcon#about to read 3, iclass 38, count 2 2006.173.15:27:54.96#ibcon#read 3, iclass 38, count 2 2006.173.15:27:54.96#ibcon#about to read 4, iclass 38, count 2 2006.173.15:27:54.96#ibcon#read 4, iclass 38, count 2 2006.173.15:27:54.96#ibcon#about to read 5, iclass 38, count 2 2006.173.15:27:54.96#ibcon#read 5, iclass 38, count 2 2006.173.15:27:54.96#ibcon#about to read 6, iclass 38, count 2 2006.173.15:27:54.96#ibcon#read 6, iclass 38, count 2 2006.173.15:27:54.96#ibcon#end of sib2, iclass 38, count 2 2006.173.15:27:54.96#ibcon#*after write, iclass 38, count 2 2006.173.15:27:54.96#ibcon#*before return 0, iclass 38, count 2 2006.173.15:27:54.96#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.15:27:54.96#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.15:27:54.96#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.15:27:54.96#ibcon#ireg 7 cls_cnt 0 2006.173.15:27:54.96#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.15:27:55.08#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.15:27:55.08#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.15:27:55.08#ibcon#enter wrdev, iclass 38, count 0 2006.173.15:27:55.08#ibcon#first serial, iclass 38, count 0 2006.173.15:27:55.08#ibcon#enter sib2, iclass 38, count 0 2006.173.15:27:55.08#ibcon#flushed, iclass 38, count 0 2006.173.15:27:55.08#ibcon#about to write, iclass 38, count 0 2006.173.15:27:55.08#ibcon#wrote, iclass 38, count 0 2006.173.15:27:55.08#ibcon#about to read 3, iclass 38, count 0 2006.173.15:27:55.10#ibcon#read 3, iclass 38, count 0 2006.173.15:27:55.10#ibcon#about to read 4, iclass 38, count 0 2006.173.15:27:55.10#ibcon#read 4, iclass 38, count 0 2006.173.15:27:55.10#ibcon#about to read 5, iclass 38, count 0 2006.173.15:27:55.10#ibcon#read 5, iclass 38, count 0 2006.173.15:27:55.10#ibcon#about to read 6, iclass 38, count 0 2006.173.15:27:55.10#ibcon#read 6, iclass 38, count 0 2006.173.15:27:55.10#ibcon#end of sib2, iclass 38, count 0 2006.173.15:27:55.10#ibcon#*mode == 0, iclass 38, count 0 2006.173.15:27:55.10#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.15:27:55.10#ibcon#[27=USB\r\n] 2006.173.15:27:55.10#ibcon#*before write, iclass 38, count 0 2006.173.15:27:55.10#ibcon#enter sib2, iclass 38, count 0 2006.173.15:27:55.10#ibcon#flushed, iclass 38, count 0 2006.173.15:27:55.10#ibcon#about to write, iclass 38, count 0 2006.173.15:27:55.10#ibcon#wrote, iclass 38, count 0 2006.173.15:27:55.10#ibcon#about to read 3, iclass 38, count 0 2006.173.15:27:55.13#ibcon#read 3, iclass 38, count 0 2006.173.15:27:55.13#ibcon#about to read 4, iclass 38, count 0 2006.173.15:27:55.13#ibcon#read 4, iclass 38, count 0 2006.173.15:27:55.13#ibcon#about to read 5, iclass 38, count 0 2006.173.15:27:55.13#ibcon#read 5, iclass 38, count 0 2006.173.15:27:55.13#ibcon#about to read 6, iclass 38, count 0 2006.173.15:27:55.13#ibcon#read 6, iclass 38, count 0 2006.173.15:27:55.13#ibcon#end of sib2, iclass 38, count 0 2006.173.15:27:55.13#ibcon#*after write, iclass 38, count 0 2006.173.15:27:55.13#ibcon#*before return 0, iclass 38, count 0 2006.173.15:27:55.13#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.15:27:55.13#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.15:27:55.13#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.15:27:55.13#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.15:27:55.13$vck44/vblo=4,679.99 2006.173.15:27:55.13#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.15:27:55.13#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.15:27:55.13#ibcon#ireg 17 cls_cnt 0 2006.173.15:27:55.13#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.15:27:55.13#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.15:27:55.13#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.15:27:55.13#ibcon#enter wrdev, iclass 40, count 0 2006.173.15:27:55.13#ibcon#first serial, iclass 40, count 0 2006.173.15:27:55.13#ibcon#enter sib2, iclass 40, count 0 2006.173.15:27:55.13#ibcon#flushed, iclass 40, count 0 2006.173.15:27:55.13#ibcon#about to write, iclass 40, count 0 2006.173.15:27:55.13#ibcon#wrote, iclass 40, count 0 2006.173.15:27:55.13#ibcon#about to read 3, iclass 40, count 0 2006.173.15:27:55.15#ibcon#read 3, iclass 40, count 0 2006.173.15:27:55.15#ibcon#about to read 4, iclass 40, count 0 2006.173.15:27:55.15#ibcon#read 4, iclass 40, count 0 2006.173.15:27:55.15#ibcon#about to read 5, iclass 40, count 0 2006.173.15:27:55.15#ibcon#read 5, iclass 40, count 0 2006.173.15:27:55.15#ibcon#about to read 6, iclass 40, count 0 2006.173.15:27:55.15#ibcon#read 6, iclass 40, count 0 2006.173.15:27:55.15#ibcon#end of sib2, iclass 40, count 0 2006.173.15:27:55.15#ibcon#*mode == 0, iclass 40, count 0 2006.173.15:27:55.15#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.15:27:55.15#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.15:27:55.15#ibcon#*before write, iclass 40, count 0 2006.173.15:27:55.15#ibcon#enter sib2, iclass 40, count 0 2006.173.15:27:55.15#ibcon#flushed, iclass 40, count 0 2006.173.15:27:55.15#ibcon#about to write, iclass 40, count 0 2006.173.15:27:55.15#ibcon#wrote, iclass 40, count 0 2006.173.15:27:55.15#ibcon#about to read 3, iclass 40, count 0 2006.173.15:27:55.19#ibcon#read 3, iclass 40, count 0 2006.173.15:27:55.19#ibcon#about to read 4, iclass 40, count 0 2006.173.15:27:55.19#ibcon#read 4, iclass 40, count 0 2006.173.15:27:55.19#ibcon#about to read 5, iclass 40, count 0 2006.173.15:27:55.19#ibcon#read 5, iclass 40, count 0 2006.173.15:27:55.19#ibcon#about to read 6, iclass 40, count 0 2006.173.15:27:55.19#ibcon#read 6, iclass 40, count 0 2006.173.15:27:55.19#ibcon#end of sib2, iclass 40, count 0 2006.173.15:27:55.19#ibcon#*after write, iclass 40, count 0 2006.173.15:27:55.19#ibcon#*before return 0, iclass 40, count 0 2006.173.15:27:55.19#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.15:27:55.19#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.15:27:55.19#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.15:27:55.19#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.15:27:55.19$vck44/vb=4,4 2006.173.15:27:55.19#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.15:27:55.19#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.15:27:55.19#ibcon#ireg 11 cls_cnt 2 2006.173.15:27:55.19#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.15:27:55.25#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.15:27:55.25#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.15:27:55.25#ibcon#enter wrdev, iclass 4, count 2 2006.173.15:27:55.25#ibcon#first serial, iclass 4, count 2 2006.173.15:27:55.25#ibcon#enter sib2, iclass 4, count 2 2006.173.15:27:55.25#ibcon#flushed, iclass 4, count 2 2006.173.15:27:55.25#ibcon#about to write, iclass 4, count 2 2006.173.15:27:55.25#ibcon#wrote, iclass 4, count 2 2006.173.15:27:55.25#ibcon#about to read 3, iclass 4, count 2 2006.173.15:27:55.27#ibcon#read 3, iclass 4, count 2 2006.173.15:27:55.27#ibcon#about to read 4, iclass 4, count 2 2006.173.15:27:55.27#ibcon#read 4, iclass 4, count 2 2006.173.15:27:55.27#ibcon#about to read 5, iclass 4, count 2 2006.173.15:27:55.27#ibcon#read 5, iclass 4, count 2 2006.173.15:27:55.27#ibcon#about to read 6, iclass 4, count 2 2006.173.15:27:55.27#ibcon#read 6, iclass 4, count 2 2006.173.15:27:55.27#ibcon#end of sib2, iclass 4, count 2 2006.173.15:27:55.27#ibcon#*mode == 0, iclass 4, count 2 2006.173.15:27:55.27#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.15:27:55.27#ibcon#[27=AT04-04\r\n] 2006.173.15:27:55.27#ibcon#*before write, iclass 4, count 2 2006.173.15:27:55.27#ibcon#enter sib2, iclass 4, count 2 2006.173.15:27:55.27#ibcon#flushed, iclass 4, count 2 2006.173.15:27:55.27#ibcon#about to write, iclass 4, count 2 2006.173.15:27:55.27#ibcon#wrote, iclass 4, count 2 2006.173.15:27:55.27#ibcon#about to read 3, iclass 4, count 2 2006.173.15:27:55.30#ibcon#read 3, iclass 4, count 2 2006.173.15:27:55.30#ibcon#about to read 4, iclass 4, count 2 2006.173.15:27:55.30#ibcon#read 4, iclass 4, count 2 2006.173.15:27:55.30#ibcon#about to read 5, iclass 4, count 2 2006.173.15:27:55.30#ibcon#read 5, iclass 4, count 2 2006.173.15:27:55.30#ibcon#about to read 6, iclass 4, count 2 2006.173.15:27:55.30#ibcon#read 6, iclass 4, count 2 2006.173.15:27:55.30#ibcon#end of sib2, iclass 4, count 2 2006.173.15:27:55.30#ibcon#*after write, iclass 4, count 2 2006.173.15:27:55.30#ibcon#*before return 0, iclass 4, count 2 2006.173.15:27:55.30#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.15:27:55.30#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.15:27:55.30#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.15:27:55.30#ibcon#ireg 7 cls_cnt 0 2006.173.15:27:55.30#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.15:27:55.42#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.15:27:55.42#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.15:27:55.42#ibcon#enter wrdev, iclass 4, count 0 2006.173.15:27:55.42#ibcon#first serial, iclass 4, count 0 2006.173.15:27:55.42#ibcon#enter sib2, iclass 4, count 0 2006.173.15:27:55.42#ibcon#flushed, iclass 4, count 0 2006.173.15:27:55.42#ibcon#about to write, iclass 4, count 0 2006.173.15:27:55.42#ibcon#wrote, iclass 4, count 0 2006.173.15:27:55.42#ibcon#about to read 3, iclass 4, count 0 2006.173.15:27:55.44#ibcon#read 3, iclass 4, count 0 2006.173.15:27:55.44#ibcon#about to read 4, iclass 4, count 0 2006.173.15:27:55.44#ibcon#read 4, iclass 4, count 0 2006.173.15:27:55.44#ibcon#about to read 5, iclass 4, count 0 2006.173.15:27:55.44#ibcon#read 5, iclass 4, count 0 2006.173.15:27:55.44#ibcon#about to read 6, iclass 4, count 0 2006.173.15:27:55.44#ibcon#read 6, iclass 4, count 0 2006.173.15:27:55.44#ibcon#end of sib2, iclass 4, count 0 2006.173.15:27:55.44#ibcon#*mode == 0, iclass 4, count 0 2006.173.15:27:55.44#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.15:27:55.44#ibcon#[27=USB\r\n] 2006.173.15:27:55.44#ibcon#*before write, iclass 4, count 0 2006.173.15:27:55.44#ibcon#enter sib2, iclass 4, count 0 2006.173.15:27:55.44#ibcon#flushed, iclass 4, count 0 2006.173.15:27:55.44#ibcon#about to write, iclass 4, count 0 2006.173.15:27:55.44#ibcon#wrote, iclass 4, count 0 2006.173.15:27:55.44#ibcon#about to read 3, iclass 4, count 0 2006.173.15:27:55.47#ibcon#read 3, iclass 4, count 0 2006.173.15:27:55.47#ibcon#about to read 4, iclass 4, count 0 2006.173.15:27:55.47#ibcon#read 4, iclass 4, count 0 2006.173.15:27:55.47#ibcon#about to read 5, iclass 4, count 0 2006.173.15:27:55.47#ibcon#read 5, iclass 4, count 0 2006.173.15:27:55.47#ibcon#about to read 6, iclass 4, count 0 2006.173.15:27:55.47#ibcon#read 6, iclass 4, count 0 2006.173.15:27:55.47#ibcon#end of sib2, iclass 4, count 0 2006.173.15:27:55.47#ibcon#*after write, iclass 4, count 0 2006.173.15:27:55.47#ibcon#*before return 0, iclass 4, count 0 2006.173.15:27:55.47#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.15:27:55.47#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.15:27:55.47#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.15:27:55.47#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.15:27:55.47$vck44/vblo=5,709.99 2006.173.15:27:55.47#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.15:27:55.47#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.15:27:55.47#ibcon#ireg 17 cls_cnt 0 2006.173.15:27:55.47#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.15:27:55.47#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.15:27:55.47#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.15:27:55.47#ibcon#enter wrdev, iclass 6, count 0 2006.173.15:27:55.47#ibcon#first serial, iclass 6, count 0 2006.173.15:27:55.47#ibcon#enter sib2, iclass 6, count 0 2006.173.15:27:55.47#ibcon#flushed, iclass 6, count 0 2006.173.15:27:55.47#ibcon#about to write, iclass 6, count 0 2006.173.15:27:55.47#ibcon#wrote, iclass 6, count 0 2006.173.15:27:55.47#ibcon#about to read 3, iclass 6, count 0 2006.173.15:27:55.49#ibcon#read 3, iclass 6, count 0 2006.173.15:27:55.49#ibcon#about to read 4, iclass 6, count 0 2006.173.15:27:55.49#ibcon#read 4, iclass 6, count 0 2006.173.15:27:55.49#ibcon#about to read 5, iclass 6, count 0 2006.173.15:27:55.49#ibcon#read 5, iclass 6, count 0 2006.173.15:27:55.49#ibcon#about to read 6, iclass 6, count 0 2006.173.15:27:55.49#ibcon#read 6, iclass 6, count 0 2006.173.15:27:55.49#ibcon#end of sib2, iclass 6, count 0 2006.173.15:27:55.49#ibcon#*mode == 0, iclass 6, count 0 2006.173.15:27:55.49#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.15:27:55.49#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.15:27:55.49#ibcon#*before write, iclass 6, count 0 2006.173.15:27:55.49#ibcon#enter sib2, iclass 6, count 0 2006.173.15:27:55.49#ibcon#flushed, iclass 6, count 0 2006.173.15:27:55.49#ibcon#about to write, iclass 6, count 0 2006.173.15:27:55.49#ibcon#wrote, iclass 6, count 0 2006.173.15:27:55.49#ibcon#about to read 3, iclass 6, count 0 2006.173.15:27:55.53#ibcon#read 3, iclass 6, count 0 2006.173.15:27:55.53#ibcon#about to read 4, iclass 6, count 0 2006.173.15:27:55.53#ibcon#read 4, iclass 6, count 0 2006.173.15:27:55.53#ibcon#about to read 5, iclass 6, count 0 2006.173.15:27:55.53#ibcon#read 5, iclass 6, count 0 2006.173.15:27:55.53#ibcon#about to read 6, iclass 6, count 0 2006.173.15:27:55.53#ibcon#read 6, iclass 6, count 0 2006.173.15:27:55.53#ibcon#end of sib2, iclass 6, count 0 2006.173.15:27:55.53#ibcon#*after write, iclass 6, count 0 2006.173.15:27:55.53#ibcon#*before return 0, iclass 6, count 0 2006.173.15:27:55.53#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.15:27:55.53#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.15:27:55.53#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.15:27:55.53#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.15:27:55.53$vck44/vb=5,4 2006.173.15:27:55.53#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.15:27:55.53#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.15:27:55.53#ibcon#ireg 11 cls_cnt 2 2006.173.15:27:55.53#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.15:27:55.59#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.15:27:55.59#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.15:27:55.59#ibcon#enter wrdev, iclass 10, count 2 2006.173.15:27:55.59#ibcon#first serial, iclass 10, count 2 2006.173.15:27:55.59#ibcon#enter sib2, iclass 10, count 2 2006.173.15:27:55.59#ibcon#flushed, iclass 10, count 2 2006.173.15:27:55.59#ibcon#about to write, iclass 10, count 2 2006.173.15:27:55.59#ibcon#wrote, iclass 10, count 2 2006.173.15:27:55.59#ibcon#about to read 3, iclass 10, count 2 2006.173.15:27:55.61#ibcon#read 3, iclass 10, count 2 2006.173.15:27:55.61#ibcon#about to read 4, iclass 10, count 2 2006.173.15:27:55.61#ibcon#read 4, iclass 10, count 2 2006.173.15:27:55.61#ibcon#about to read 5, iclass 10, count 2 2006.173.15:27:55.61#ibcon#read 5, iclass 10, count 2 2006.173.15:27:55.61#ibcon#about to read 6, iclass 10, count 2 2006.173.15:27:55.61#ibcon#read 6, iclass 10, count 2 2006.173.15:27:55.61#ibcon#end of sib2, iclass 10, count 2 2006.173.15:27:55.61#ibcon#*mode == 0, iclass 10, count 2 2006.173.15:27:55.61#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.15:27:55.61#ibcon#[27=AT05-04\r\n] 2006.173.15:27:55.61#ibcon#*before write, iclass 10, count 2 2006.173.15:27:55.61#ibcon#enter sib2, iclass 10, count 2 2006.173.15:27:55.61#ibcon#flushed, iclass 10, count 2 2006.173.15:27:55.61#ibcon#about to write, iclass 10, count 2 2006.173.15:27:55.61#ibcon#wrote, iclass 10, count 2 2006.173.15:27:55.61#ibcon#about to read 3, iclass 10, count 2 2006.173.15:27:55.64#ibcon#read 3, iclass 10, count 2 2006.173.15:27:55.64#ibcon#about to read 4, iclass 10, count 2 2006.173.15:27:55.64#ibcon#read 4, iclass 10, count 2 2006.173.15:27:55.64#ibcon#about to read 5, iclass 10, count 2 2006.173.15:27:55.64#ibcon#read 5, iclass 10, count 2 2006.173.15:27:55.64#ibcon#about to read 6, iclass 10, count 2 2006.173.15:27:55.64#ibcon#read 6, iclass 10, count 2 2006.173.15:27:55.64#ibcon#end of sib2, iclass 10, count 2 2006.173.15:27:55.64#ibcon#*after write, iclass 10, count 2 2006.173.15:27:55.64#ibcon#*before return 0, iclass 10, count 2 2006.173.15:27:55.64#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.15:27:55.64#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.15:27:55.64#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.15:27:55.64#ibcon#ireg 7 cls_cnt 0 2006.173.15:27:55.64#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.15:27:55.76#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.15:27:55.76#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.15:27:55.76#ibcon#enter wrdev, iclass 10, count 0 2006.173.15:27:55.76#ibcon#first serial, iclass 10, count 0 2006.173.15:27:55.76#ibcon#enter sib2, iclass 10, count 0 2006.173.15:27:55.76#ibcon#flushed, iclass 10, count 0 2006.173.15:27:55.76#ibcon#about to write, iclass 10, count 0 2006.173.15:27:55.76#ibcon#wrote, iclass 10, count 0 2006.173.15:27:55.76#ibcon#about to read 3, iclass 10, count 0 2006.173.15:27:55.78#ibcon#read 3, iclass 10, count 0 2006.173.15:27:55.78#ibcon#about to read 4, iclass 10, count 0 2006.173.15:27:55.78#ibcon#read 4, iclass 10, count 0 2006.173.15:27:55.78#ibcon#about to read 5, iclass 10, count 0 2006.173.15:27:55.78#ibcon#read 5, iclass 10, count 0 2006.173.15:27:55.78#ibcon#about to read 6, iclass 10, count 0 2006.173.15:27:55.78#ibcon#read 6, iclass 10, count 0 2006.173.15:27:55.78#ibcon#end of sib2, iclass 10, count 0 2006.173.15:27:55.78#ibcon#*mode == 0, iclass 10, count 0 2006.173.15:27:55.78#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.15:27:55.78#ibcon#[27=USB\r\n] 2006.173.15:27:55.78#ibcon#*before write, iclass 10, count 0 2006.173.15:27:55.78#ibcon#enter sib2, iclass 10, count 0 2006.173.15:27:55.78#ibcon#flushed, iclass 10, count 0 2006.173.15:27:55.78#ibcon#about to write, iclass 10, count 0 2006.173.15:27:55.78#ibcon#wrote, iclass 10, count 0 2006.173.15:27:55.78#ibcon#about to read 3, iclass 10, count 0 2006.173.15:27:55.81#ibcon#read 3, iclass 10, count 0 2006.173.15:27:55.81#ibcon#about to read 4, iclass 10, count 0 2006.173.15:27:55.81#ibcon#read 4, iclass 10, count 0 2006.173.15:27:55.81#ibcon#about to read 5, iclass 10, count 0 2006.173.15:27:55.81#ibcon#read 5, iclass 10, count 0 2006.173.15:27:55.81#ibcon#about to read 6, iclass 10, count 0 2006.173.15:27:55.81#ibcon#read 6, iclass 10, count 0 2006.173.15:27:55.81#ibcon#end of sib2, iclass 10, count 0 2006.173.15:27:55.81#ibcon#*after write, iclass 10, count 0 2006.173.15:27:55.81#ibcon#*before return 0, iclass 10, count 0 2006.173.15:27:55.81#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.15:27:55.81#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.15:27:55.81#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.15:27:55.81#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.15:27:55.81$vck44/vblo=6,719.99 2006.173.15:27:55.81#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.15:27:55.81#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.15:27:55.81#ibcon#ireg 17 cls_cnt 0 2006.173.15:27:55.81#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.15:27:55.81#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.15:27:55.81#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.15:27:55.81#ibcon#enter wrdev, iclass 12, count 0 2006.173.15:27:55.81#ibcon#first serial, iclass 12, count 0 2006.173.15:27:55.81#ibcon#enter sib2, iclass 12, count 0 2006.173.15:27:55.81#ibcon#flushed, iclass 12, count 0 2006.173.15:27:55.81#ibcon#about to write, iclass 12, count 0 2006.173.15:27:55.82#ibcon#wrote, iclass 12, count 0 2006.173.15:27:55.82#ibcon#about to read 3, iclass 12, count 0 2006.173.15:27:55.83#ibcon#read 3, iclass 12, count 0 2006.173.15:27:55.83#ibcon#about to read 4, iclass 12, count 0 2006.173.15:27:55.83#ibcon#read 4, iclass 12, count 0 2006.173.15:27:55.83#ibcon#about to read 5, iclass 12, count 0 2006.173.15:27:55.83#ibcon#read 5, iclass 12, count 0 2006.173.15:27:55.83#ibcon#about to read 6, iclass 12, count 0 2006.173.15:27:55.83#ibcon#read 6, iclass 12, count 0 2006.173.15:27:55.83#ibcon#end of sib2, iclass 12, count 0 2006.173.15:27:55.83#ibcon#*mode == 0, iclass 12, count 0 2006.173.15:27:55.83#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.15:27:55.83#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.15:27:55.83#ibcon#*before write, iclass 12, count 0 2006.173.15:27:55.83#ibcon#enter sib2, iclass 12, count 0 2006.173.15:27:55.83#ibcon#flushed, iclass 12, count 0 2006.173.15:27:55.83#ibcon#about to write, iclass 12, count 0 2006.173.15:27:55.83#ibcon#wrote, iclass 12, count 0 2006.173.15:27:55.83#ibcon#about to read 3, iclass 12, count 0 2006.173.15:27:55.87#ibcon#read 3, iclass 12, count 0 2006.173.15:27:55.87#ibcon#about to read 4, iclass 12, count 0 2006.173.15:27:55.87#ibcon#read 4, iclass 12, count 0 2006.173.15:27:55.87#ibcon#about to read 5, iclass 12, count 0 2006.173.15:27:55.87#ibcon#read 5, iclass 12, count 0 2006.173.15:27:55.87#ibcon#about to read 6, iclass 12, count 0 2006.173.15:27:55.87#ibcon#read 6, iclass 12, count 0 2006.173.15:27:55.87#ibcon#end of sib2, iclass 12, count 0 2006.173.15:27:55.87#ibcon#*after write, iclass 12, count 0 2006.173.15:27:55.87#ibcon#*before return 0, iclass 12, count 0 2006.173.15:27:55.87#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.15:27:55.87#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.15:27:55.87#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.15:27:55.87#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.15:27:55.87$vck44/vb=6,4 2006.173.15:27:55.87#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.15:27:55.87#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.15:27:55.87#ibcon#ireg 11 cls_cnt 2 2006.173.15:27:55.87#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.15:27:55.93#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.15:27:55.93#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.15:27:55.93#ibcon#enter wrdev, iclass 14, count 2 2006.173.15:27:55.93#ibcon#first serial, iclass 14, count 2 2006.173.15:27:55.93#ibcon#enter sib2, iclass 14, count 2 2006.173.15:27:55.93#ibcon#flushed, iclass 14, count 2 2006.173.15:27:55.93#ibcon#about to write, iclass 14, count 2 2006.173.15:27:55.93#ibcon#wrote, iclass 14, count 2 2006.173.15:27:55.93#ibcon#about to read 3, iclass 14, count 2 2006.173.15:27:55.95#ibcon#read 3, iclass 14, count 2 2006.173.15:27:55.95#ibcon#about to read 4, iclass 14, count 2 2006.173.15:27:55.95#ibcon#read 4, iclass 14, count 2 2006.173.15:27:55.95#ibcon#about to read 5, iclass 14, count 2 2006.173.15:27:55.95#ibcon#read 5, iclass 14, count 2 2006.173.15:27:55.95#ibcon#about to read 6, iclass 14, count 2 2006.173.15:27:55.95#ibcon#read 6, iclass 14, count 2 2006.173.15:27:55.95#ibcon#end of sib2, iclass 14, count 2 2006.173.15:27:55.95#ibcon#*mode == 0, iclass 14, count 2 2006.173.15:27:55.95#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.15:27:55.95#ibcon#[27=AT06-04\r\n] 2006.173.15:27:55.95#ibcon#*before write, iclass 14, count 2 2006.173.15:27:55.95#ibcon#enter sib2, iclass 14, count 2 2006.173.15:27:55.95#ibcon#flushed, iclass 14, count 2 2006.173.15:27:55.95#ibcon#about to write, iclass 14, count 2 2006.173.15:27:55.95#ibcon#wrote, iclass 14, count 2 2006.173.15:27:55.95#ibcon#about to read 3, iclass 14, count 2 2006.173.15:27:55.98#ibcon#read 3, iclass 14, count 2 2006.173.15:27:55.98#ibcon#about to read 4, iclass 14, count 2 2006.173.15:27:55.98#ibcon#read 4, iclass 14, count 2 2006.173.15:27:55.98#ibcon#about to read 5, iclass 14, count 2 2006.173.15:27:55.98#ibcon#read 5, iclass 14, count 2 2006.173.15:27:55.98#ibcon#about to read 6, iclass 14, count 2 2006.173.15:27:55.98#ibcon#read 6, iclass 14, count 2 2006.173.15:27:55.98#ibcon#end of sib2, iclass 14, count 2 2006.173.15:27:55.98#ibcon#*after write, iclass 14, count 2 2006.173.15:27:55.98#ibcon#*before return 0, iclass 14, count 2 2006.173.15:27:55.98#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.15:27:55.98#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.15:27:55.98#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.15:27:55.98#ibcon#ireg 7 cls_cnt 0 2006.173.15:27:55.98#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.15:27:56.10#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.15:27:56.10#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.15:27:56.10#ibcon#enter wrdev, iclass 14, count 0 2006.173.15:27:56.10#ibcon#first serial, iclass 14, count 0 2006.173.15:27:56.10#ibcon#enter sib2, iclass 14, count 0 2006.173.15:27:56.10#ibcon#flushed, iclass 14, count 0 2006.173.15:27:56.10#ibcon#about to write, iclass 14, count 0 2006.173.15:27:56.10#ibcon#wrote, iclass 14, count 0 2006.173.15:27:56.10#ibcon#about to read 3, iclass 14, count 0 2006.173.15:27:56.12#ibcon#read 3, iclass 14, count 0 2006.173.15:27:56.12#ibcon#about to read 4, iclass 14, count 0 2006.173.15:27:56.12#ibcon#read 4, iclass 14, count 0 2006.173.15:27:56.12#ibcon#about to read 5, iclass 14, count 0 2006.173.15:27:56.12#ibcon#read 5, iclass 14, count 0 2006.173.15:27:56.12#ibcon#about to read 6, iclass 14, count 0 2006.173.15:27:56.12#ibcon#read 6, iclass 14, count 0 2006.173.15:27:56.12#ibcon#end of sib2, iclass 14, count 0 2006.173.15:27:56.12#ibcon#*mode == 0, iclass 14, count 0 2006.173.15:27:56.12#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.15:27:56.12#ibcon#[27=USB\r\n] 2006.173.15:27:56.12#ibcon#*before write, iclass 14, count 0 2006.173.15:27:56.12#ibcon#enter sib2, iclass 14, count 0 2006.173.15:27:56.12#ibcon#flushed, iclass 14, count 0 2006.173.15:27:56.12#ibcon#about to write, iclass 14, count 0 2006.173.15:27:56.12#ibcon#wrote, iclass 14, count 0 2006.173.15:27:56.12#ibcon#about to read 3, iclass 14, count 0 2006.173.15:27:56.15#ibcon#read 3, iclass 14, count 0 2006.173.15:27:56.15#ibcon#about to read 4, iclass 14, count 0 2006.173.15:27:56.15#ibcon#read 4, iclass 14, count 0 2006.173.15:27:56.15#ibcon#about to read 5, iclass 14, count 0 2006.173.15:27:56.15#ibcon#read 5, iclass 14, count 0 2006.173.15:27:56.15#ibcon#about to read 6, iclass 14, count 0 2006.173.15:27:56.15#ibcon#read 6, iclass 14, count 0 2006.173.15:27:56.15#ibcon#end of sib2, iclass 14, count 0 2006.173.15:27:56.15#ibcon#*after write, iclass 14, count 0 2006.173.15:27:56.15#ibcon#*before return 0, iclass 14, count 0 2006.173.15:27:56.15#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.15:27:56.15#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.15:27:56.15#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.15:27:56.15#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.15:27:56.15$vck44/vblo=7,734.99 2006.173.15:27:56.15#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.15:27:56.15#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.15:27:56.15#ibcon#ireg 17 cls_cnt 0 2006.173.15:27:56.15#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.15:27:56.15#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.15:27:56.15#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.15:27:56.15#ibcon#enter wrdev, iclass 16, count 0 2006.173.15:27:56.15#ibcon#first serial, iclass 16, count 0 2006.173.15:27:56.15#ibcon#enter sib2, iclass 16, count 0 2006.173.15:27:56.15#ibcon#flushed, iclass 16, count 0 2006.173.15:27:56.15#ibcon#about to write, iclass 16, count 0 2006.173.15:27:56.15#ibcon#wrote, iclass 16, count 0 2006.173.15:27:56.15#ibcon#about to read 3, iclass 16, count 0 2006.173.15:27:56.17#ibcon#read 3, iclass 16, count 0 2006.173.15:27:56.17#ibcon#about to read 4, iclass 16, count 0 2006.173.15:27:56.17#ibcon#read 4, iclass 16, count 0 2006.173.15:27:56.17#ibcon#about to read 5, iclass 16, count 0 2006.173.15:27:56.17#ibcon#read 5, iclass 16, count 0 2006.173.15:27:56.17#ibcon#about to read 6, iclass 16, count 0 2006.173.15:27:56.17#ibcon#read 6, iclass 16, count 0 2006.173.15:27:56.17#ibcon#end of sib2, iclass 16, count 0 2006.173.15:27:56.17#ibcon#*mode == 0, iclass 16, count 0 2006.173.15:27:56.17#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.15:27:56.17#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.15:27:56.17#ibcon#*before write, iclass 16, count 0 2006.173.15:27:56.17#ibcon#enter sib2, iclass 16, count 0 2006.173.15:27:56.17#ibcon#flushed, iclass 16, count 0 2006.173.15:27:56.17#ibcon#about to write, iclass 16, count 0 2006.173.15:27:56.17#ibcon#wrote, iclass 16, count 0 2006.173.15:27:56.17#ibcon#about to read 3, iclass 16, count 0 2006.173.15:27:56.21#ibcon#read 3, iclass 16, count 0 2006.173.15:27:56.21#ibcon#about to read 4, iclass 16, count 0 2006.173.15:27:56.21#ibcon#read 4, iclass 16, count 0 2006.173.15:27:56.21#ibcon#about to read 5, iclass 16, count 0 2006.173.15:27:56.21#ibcon#read 5, iclass 16, count 0 2006.173.15:27:56.21#ibcon#about to read 6, iclass 16, count 0 2006.173.15:27:56.21#ibcon#read 6, iclass 16, count 0 2006.173.15:27:56.21#ibcon#end of sib2, iclass 16, count 0 2006.173.15:27:56.21#ibcon#*after write, iclass 16, count 0 2006.173.15:27:56.21#ibcon#*before return 0, iclass 16, count 0 2006.173.15:27:56.21#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.15:27:56.21#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.15:27:56.21#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.15:27:56.21#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.15:27:56.21$vck44/vb=7,4 2006.173.15:27:56.21#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.15:27:56.21#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.15:27:56.21#ibcon#ireg 11 cls_cnt 2 2006.173.15:27:56.21#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.15:27:56.27#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.15:27:56.27#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.15:27:56.27#ibcon#enter wrdev, iclass 18, count 2 2006.173.15:27:56.27#ibcon#first serial, iclass 18, count 2 2006.173.15:27:56.27#ibcon#enter sib2, iclass 18, count 2 2006.173.15:27:56.27#ibcon#flushed, iclass 18, count 2 2006.173.15:27:56.27#ibcon#about to write, iclass 18, count 2 2006.173.15:27:56.27#ibcon#wrote, iclass 18, count 2 2006.173.15:27:56.27#ibcon#about to read 3, iclass 18, count 2 2006.173.15:27:56.29#ibcon#read 3, iclass 18, count 2 2006.173.15:27:56.29#ibcon#about to read 4, iclass 18, count 2 2006.173.15:27:56.29#ibcon#read 4, iclass 18, count 2 2006.173.15:27:56.29#ibcon#about to read 5, iclass 18, count 2 2006.173.15:27:56.29#ibcon#read 5, iclass 18, count 2 2006.173.15:27:56.29#ibcon#about to read 6, iclass 18, count 2 2006.173.15:27:56.29#ibcon#read 6, iclass 18, count 2 2006.173.15:27:56.29#ibcon#end of sib2, iclass 18, count 2 2006.173.15:27:56.29#ibcon#*mode == 0, iclass 18, count 2 2006.173.15:27:56.29#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.15:27:56.29#ibcon#[27=AT07-04\r\n] 2006.173.15:27:56.29#ibcon#*before write, iclass 18, count 2 2006.173.15:27:56.29#ibcon#enter sib2, iclass 18, count 2 2006.173.15:27:56.29#ibcon#flushed, iclass 18, count 2 2006.173.15:27:56.29#ibcon#about to write, iclass 18, count 2 2006.173.15:27:56.29#ibcon#wrote, iclass 18, count 2 2006.173.15:27:56.29#ibcon#about to read 3, iclass 18, count 2 2006.173.15:27:56.32#ibcon#read 3, iclass 18, count 2 2006.173.15:27:56.32#ibcon#about to read 4, iclass 18, count 2 2006.173.15:27:56.32#ibcon#read 4, iclass 18, count 2 2006.173.15:27:56.32#ibcon#about to read 5, iclass 18, count 2 2006.173.15:27:56.32#ibcon#read 5, iclass 18, count 2 2006.173.15:27:56.32#ibcon#about to read 6, iclass 18, count 2 2006.173.15:27:56.32#ibcon#read 6, iclass 18, count 2 2006.173.15:27:56.32#ibcon#end of sib2, iclass 18, count 2 2006.173.15:27:56.32#ibcon#*after write, iclass 18, count 2 2006.173.15:27:56.32#ibcon#*before return 0, iclass 18, count 2 2006.173.15:27:56.32#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.15:27:56.32#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.15:27:56.32#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.15:27:56.32#ibcon#ireg 7 cls_cnt 0 2006.173.15:27:56.32#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.15:27:56.44#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.15:27:56.44#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.15:27:56.44#ibcon#enter wrdev, iclass 18, count 0 2006.173.15:27:56.44#ibcon#first serial, iclass 18, count 0 2006.173.15:27:56.44#ibcon#enter sib2, iclass 18, count 0 2006.173.15:27:56.44#ibcon#flushed, iclass 18, count 0 2006.173.15:27:56.44#ibcon#about to write, iclass 18, count 0 2006.173.15:27:56.44#ibcon#wrote, iclass 18, count 0 2006.173.15:27:56.44#ibcon#about to read 3, iclass 18, count 0 2006.173.15:27:56.46#ibcon#read 3, iclass 18, count 0 2006.173.15:27:56.46#ibcon#about to read 4, iclass 18, count 0 2006.173.15:27:56.46#ibcon#read 4, iclass 18, count 0 2006.173.15:27:56.46#ibcon#about to read 5, iclass 18, count 0 2006.173.15:27:56.46#ibcon#read 5, iclass 18, count 0 2006.173.15:27:56.46#ibcon#about to read 6, iclass 18, count 0 2006.173.15:27:56.46#ibcon#read 6, iclass 18, count 0 2006.173.15:27:56.46#ibcon#end of sib2, iclass 18, count 0 2006.173.15:27:56.46#ibcon#*mode == 0, iclass 18, count 0 2006.173.15:27:56.46#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.15:27:56.46#ibcon#[27=USB\r\n] 2006.173.15:27:56.46#ibcon#*before write, iclass 18, count 0 2006.173.15:27:56.46#ibcon#enter sib2, iclass 18, count 0 2006.173.15:27:56.46#ibcon#flushed, iclass 18, count 0 2006.173.15:27:56.46#ibcon#about to write, iclass 18, count 0 2006.173.15:27:56.46#ibcon#wrote, iclass 18, count 0 2006.173.15:27:56.46#ibcon#about to read 3, iclass 18, count 0 2006.173.15:27:56.49#ibcon#read 3, iclass 18, count 0 2006.173.15:27:56.49#ibcon#about to read 4, iclass 18, count 0 2006.173.15:27:56.49#ibcon#read 4, iclass 18, count 0 2006.173.15:27:56.49#ibcon#about to read 5, iclass 18, count 0 2006.173.15:27:56.49#ibcon#read 5, iclass 18, count 0 2006.173.15:27:56.49#ibcon#about to read 6, iclass 18, count 0 2006.173.15:27:56.49#ibcon#read 6, iclass 18, count 0 2006.173.15:27:56.49#ibcon#end of sib2, iclass 18, count 0 2006.173.15:27:56.49#ibcon#*after write, iclass 18, count 0 2006.173.15:27:56.49#ibcon#*before return 0, iclass 18, count 0 2006.173.15:27:56.49#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.15:27:56.49#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.15:27:56.49#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.15:27:56.49#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.15:27:56.49$vck44/vblo=8,744.99 2006.173.15:27:56.49#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.15:27:56.49#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.15:27:56.49#ibcon#ireg 17 cls_cnt 0 2006.173.15:27:56.49#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.15:27:56.49#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.15:27:56.49#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.15:27:56.49#ibcon#enter wrdev, iclass 20, count 0 2006.173.15:27:56.49#ibcon#first serial, iclass 20, count 0 2006.173.15:27:56.49#ibcon#enter sib2, iclass 20, count 0 2006.173.15:27:56.49#ibcon#flushed, iclass 20, count 0 2006.173.15:27:56.49#ibcon#about to write, iclass 20, count 0 2006.173.15:27:56.50#ibcon#wrote, iclass 20, count 0 2006.173.15:27:56.50#ibcon#about to read 3, iclass 20, count 0 2006.173.15:27:56.51#ibcon#read 3, iclass 20, count 0 2006.173.15:27:56.51#ibcon#about to read 4, iclass 20, count 0 2006.173.15:27:56.51#ibcon#read 4, iclass 20, count 0 2006.173.15:27:56.51#ibcon#about to read 5, iclass 20, count 0 2006.173.15:27:56.51#ibcon#read 5, iclass 20, count 0 2006.173.15:27:56.51#ibcon#about to read 6, iclass 20, count 0 2006.173.15:27:56.51#ibcon#read 6, iclass 20, count 0 2006.173.15:27:56.51#ibcon#end of sib2, iclass 20, count 0 2006.173.15:27:56.51#ibcon#*mode == 0, iclass 20, count 0 2006.173.15:27:56.51#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.15:27:56.51#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.15:27:56.51#ibcon#*before write, iclass 20, count 0 2006.173.15:27:56.51#ibcon#enter sib2, iclass 20, count 0 2006.173.15:27:56.51#ibcon#flushed, iclass 20, count 0 2006.173.15:27:56.51#ibcon#about to write, iclass 20, count 0 2006.173.15:27:56.51#ibcon#wrote, iclass 20, count 0 2006.173.15:27:56.51#ibcon#about to read 3, iclass 20, count 0 2006.173.15:27:56.55#ibcon#read 3, iclass 20, count 0 2006.173.15:27:56.55#ibcon#about to read 4, iclass 20, count 0 2006.173.15:27:56.55#ibcon#read 4, iclass 20, count 0 2006.173.15:27:56.55#ibcon#about to read 5, iclass 20, count 0 2006.173.15:27:56.55#ibcon#read 5, iclass 20, count 0 2006.173.15:27:56.55#ibcon#about to read 6, iclass 20, count 0 2006.173.15:27:56.55#ibcon#read 6, iclass 20, count 0 2006.173.15:27:56.55#ibcon#end of sib2, iclass 20, count 0 2006.173.15:27:56.55#ibcon#*after write, iclass 20, count 0 2006.173.15:27:56.55#ibcon#*before return 0, iclass 20, count 0 2006.173.15:27:56.55#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.15:27:56.55#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.15:27:56.55#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.15:27:56.55#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.15:27:56.55$vck44/vb=8,4 2006.173.15:27:56.55#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.15:27:56.55#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.15:27:56.55#ibcon#ireg 11 cls_cnt 2 2006.173.15:27:56.55#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.15:27:56.61#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.15:27:56.61#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.15:27:56.61#ibcon#enter wrdev, iclass 22, count 2 2006.173.15:27:56.61#ibcon#first serial, iclass 22, count 2 2006.173.15:27:56.61#ibcon#enter sib2, iclass 22, count 2 2006.173.15:27:56.61#ibcon#flushed, iclass 22, count 2 2006.173.15:27:56.61#ibcon#about to write, iclass 22, count 2 2006.173.15:27:56.61#ibcon#wrote, iclass 22, count 2 2006.173.15:27:56.61#ibcon#about to read 3, iclass 22, count 2 2006.173.15:27:56.63#ibcon#read 3, iclass 22, count 2 2006.173.15:27:56.63#ibcon#about to read 4, iclass 22, count 2 2006.173.15:27:56.63#ibcon#read 4, iclass 22, count 2 2006.173.15:27:56.63#ibcon#about to read 5, iclass 22, count 2 2006.173.15:27:56.63#ibcon#read 5, iclass 22, count 2 2006.173.15:27:56.63#ibcon#about to read 6, iclass 22, count 2 2006.173.15:27:56.63#ibcon#read 6, iclass 22, count 2 2006.173.15:27:56.63#ibcon#end of sib2, iclass 22, count 2 2006.173.15:27:56.63#ibcon#*mode == 0, iclass 22, count 2 2006.173.15:27:56.63#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.15:27:56.63#ibcon#[27=AT08-04\r\n] 2006.173.15:27:56.63#ibcon#*before write, iclass 22, count 2 2006.173.15:27:56.63#ibcon#enter sib2, iclass 22, count 2 2006.173.15:27:56.63#ibcon#flushed, iclass 22, count 2 2006.173.15:27:56.63#ibcon#about to write, iclass 22, count 2 2006.173.15:27:56.63#ibcon#wrote, iclass 22, count 2 2006.173.15:27:56.63#ibcon#about to read 3, iclass 22, count 2 2006.173.15:27:56.66#ibcon#read 3, iclass 22, count 2 2006.173.15:27:56.66#ibcon#about to read 4, iclass 22, count 2 2006.173.15:27:56.66#ibcon#read 4, iclass 22, count 2 2006.173.15:27:56.66#ibcon#about to read 5, iclass 22, count 2 2006.173.15:27:56.66#ibcon#read 5, iclass 22, count 2 2006.173.15:27:56.66#ibcon#about to read 6, iclass 22, count 2 2006.173.15:27:56.66#ibcon#read 6, iclass 22, count 2 2006.173.15:27:56.66#ibcon#end of sib2, iclass 22, count 2 2006.173.15:27:56.66#ibcon#*after write, iclass 22, count 2 2006.173.15:27:56.66#ibcon#*before return 0, iclass 22, count 2 2006.173.15:27:56.66#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.15:27:56.66#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.15:27:56.66#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.15:27:56.66#ibcon#ireg 7 cls_cnt 0 2006.173.15:27:56.66#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.15:27:56.78#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.15:27:56.78#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.15:27:56.78#ibcon#enter wrdev, iclass 22, count 0 2006.173.15:27:56.78#ibcon#first serial, iclass 22, count 0 2006.173.15:27:56.78#ibcon#enter sib2, iclass 22, count 0 2006.173.15:27:56.78#ibcon#flushed, iclass 22, count 0 2006.173.15:27:56.78#ibcon#about to write, iclass 22, count 0 2006.173.15:27:56.78#ibcon#wrote, iclass 22, count 0 2006.173.15:27:56.78#ibcon#about to read 3, iclass 22, count 0 2006.173.15:27:56.80#ibcon#read 3, iclass 22, count 0 2006.173.15:27:56.80#ibcon#about to read 4, iclass 22, count 0 2006.173.15:27:56.80#ibcon#read 4, iclass 22, count 0 2006.173.15:27:56.80#ibcon#about to read 5, iclass 22, count 0 2006.173.15:27:56.80#ibcon#read 5, iclass 22, count 0 2006.173.15:27:56.80#ibcon#about to read 6, iclass 22, count 0 2006.173.15:27:56.80#ibcon#read 6, iclass 22, count 0 2006.173.15:27:56.80#ibcon#end of sib2, iclass 22, count 0 2006.173.15:27:56.80#ibcon#*mode == 0, iclass 22, count 0 2006.173.15:27:56.80#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.15:27:56.80#ibcon#[27=USB\r\n] 2006.173.15:27:56.80#ibcon#*before write, iclass 22, count 0 2006.173.15:27:56.80#ibcon#enter sib2, iclass 22, count 0 2006.173.15:27:56.80#ibcon#flushed, iclass 22, count 0 2006.173.15:27:56.80#ibcon#about to write, iclass 22, count 0 2006.173.15:27:56.80#ibcon#wrote, iclass 22, count 0 2006.173.15:27:56.80#ibcon#about to read 3, iclass 22, count 0 2006.173.15:27:56.83#ibcon#read 3, iclass 22, count 0 2006.173.15:27:56.83#ibcon#about to read 4, iclass 22, count 0 2006.173.15:27:56.83#ibcon#read 4, iclass 22, count 0 2006.173.15:27:56.83#ibcon#about to read 5, iclass 22, count 0 2006.173.15:27:56.83#ibcon#read 5, iclass 22, count 0 2006.173.15:27:56.83#ibcon#about to read 6, iclass 22, count 0 2006.173.15:27:56.83#ibcon#read 6, iclass 22, count 0 2006.173.15:27:56.83#ibcon#end of sib2, iclass 22, count 0 2006.173.15:27:56.83#ibcon#*after write, iclass 22, count 0 2006.173.15:27:56.83#ibcon#*before return 0, iclass 22, count 0 2006.173.15:27:56.83#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.15:27:56.83#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.15:27:56.83#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.15:27:56.83#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.15:27:56.83$vck44/vabw=wide 2006.173.15:27:56.83#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.15:27:56.83#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.15:27:56.83#ibcon#ireg 8 cls_cnt 0 2006.173.15:27:56.83#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.15:27:56.83#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.15:27:56.83#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.15:27:56.83#ibcon#enter wrdev, iclass 24, count 0 2006.173.15:27:56.83#ibcon#first serial, iclass 24, count 0 2006.173.15:27:56.83#ibcon#enter sib2, iclass 24, count 0 2006.173.15:27:56.83#ibcon#flushed, iclass 24, count 0 2006.173.15:27:56.83#ibcon#about to write, iclass 24, count 0 2006.173.15:27:56.84#ibcon#wrote, iclass 24, count 0 2006.173.15:27:56.84#ibcon#about to read 3, iclass 24, count 0 2006.173.15:27:56.85#ibcon#read 3, iclass 24, count 0 2006.173.15:27:56.85#ibcon#about to read 4, iclass 24, count 0 2006.173.15:27:56.85#ibcon#read 4, iclass 24, count 0 2006.173.15:27:56.85#ibcon#about to read 5, iclass 24, count 0 2006.173.15:27:56.85#ibcon#read 5, iclass 24, count 0 2006.173.15:27:56.85#ibcon#about to read 6, iclass 24, count 0 2006.173.15:27:56.85#ibcon#read 6, iclass 24, count 0 2006.173.15:27:56.85#ibcon#end of sib2, iclass 24, count 0 2006.173.15:27:56.85#ibcon#*mode == 0, iclass 24, count 0 2006.173.15:27:56.85#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.15:27:56.85#ibcon#[25=BW32\r\n] 2006.173.15:27:56.85#ibcon#*before write, iclass 24, count 0 2006.173.15:27:56.85#ibcon#enter sib2, iclass 24, count 0 2006.173.15:27:56.85#ibcon#flushed, iclass 24, count 0 2006.173.15:27:56.85#ibcon#about to write, iclass 24, count 0 2006.173.15:27:56.85#ibcon#wrote, iclass 24, count 0 2006.173.15:27:56.85#ibcon#about to read 3, iclass 24, count 0 2006.173.15:27:56.88#ibcon#read 3, iclass 24, count 0 2006.173.15:27:56.88#ibcon#about to read 4, iclass 24, count 0 2006.173.15:27:56.88#ibcon#read 4, iclass 24, count 0 2006.173.15:27:56.88#ibcon#about to read 5, iclass 24, count 0 2006.173.15:27:56.88#ibcon#read 5, iclass 24, count 0 2006.173.15:27:56.88#ibcon#about to read 6, iclass 24, count 0 2006.173.15:27:56.88#ibcon#read 6, iclass 24, count 0 2006.173.15:27:56.88#ibcon#end of sib2, iclass 24, count 0 2006.173.15:27:56.88#ibcon#*after write, iclass 24, count 0 2006.173.15:27:56.88#ibcon#*before return 0, iclass 24, count 0 2006.173.15:27:56.88#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.15:27:56.88#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.15:27:56.88#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.15:27:56.88#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.15:27:56.88$vck44/vbbw=wide 2006.173.15:27:56.88#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.15:27:56.88#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.15:27:56.88#ibcon#ireg 8 cls_cnt 0 2006.173.15:27:56.88#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.15:27:56.95#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.15:27:56.95#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.15:27:56.95#ibcon#enter wrdev, iclass 26, count 0 2006.173.15:27:56.95#ibcon#first serial, iclass 26, count 0 2006.173.15:27:56.95#ibcon#enter sib2, iclass 26, count 0 2006.173.15:27:56.95#ibcon#flushed, iclass 26, count 0 2006.173.15:27:56.95#ibcon#about to write, iclass 26, count 0 2006.173.15:27:56.95#ibcon#wrote, iclass 26, count 0 2006.173.15:27:56.95#ibcon#about to read 3, iclass 26, count 0 2006.173.15:27:56.97#ibcon#read 3, iclass 26, count 0 2006.173.15:27:56.97#ibcon#about to read 4, iclass 26, count 0 2006.173.15:27:56.97#ibcon#read 4, iclass 26, count 0 2006.173.15:27:56.97#ibcon#about to read 5, iclass 26, count 0 2006.173.15:27:56.97#ibcon#read 5, iclass 26, count 0 2006.173.15:27:56.97#ibcon#about to read 6, iclass 26, count 0 2006.173.15:27:56.97#ibcon#read 6, iclass 26, count 0 2006.173.15:27:56.97#ibcon#end of sib2, iclass 26, count 0 2006.173.15:27:56.97#ibcon#*mode == 0, iclass 26, count 0 2006.173.15:27:56.97#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.15:27:56.97#ibcon#[27=BW32\r\n] 2006.173.15:27:56.97#ibcon#*before write, iclass 26, count 0 2006.173.15:27:56.97#ibcon#enter sib2, iclass 26, count 0 2006.173.15:27:56.97#ibcon#flushed, iclass 26, count 0 2006.173.15:27:56.97#ibcon#about to write, iclass 26, count 0 2006.173.15:27:56.97#ibcon#wrote, iclass 26, count 0 2006.173.15:27:56.97#ibcon#about to read 3, iclass 26, count 0 2006.173.15:27:57.00#ibcon#read 3, iclass 26, count 0 2006.173.15:27:57.00#ibcon#about to read 4, iclass 26, count 0 2006.173.15:27:57.00#ibcon#read 4, iclass 26, count 0 2006.173.15:27:57.00#ibcon#about to read 5, iclass 26, count 0 2006.173.15:27:57.00#ibcon#read 5, iclass 26, count 0 2006.173.15:27:57.00#ibcon#about to read 6, iclass 26, count 0 2006.173.15:27:57.00#ibcon#read 6, iclass 26, count 0 2006.173.15:27:57.00#ibcon#end of sib2, iclass 26, count 0 2006.173.15:27:57.00#ibcon#*after write, iclass 26, count 0 2006.173.15:27:57.00#ibcon#*before return 0, iclass 26, count 0 2006.173.15:27:57.00#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.15:27:57.00#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.15:27:57.00#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.15:27:57.00#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.15:27:57.00$setupk4/ifdk4 2006.173.15:27:57.00$ifdk4/lo= 2006.173.15:27:57.01$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.15:27:57.01$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.15:27:57.01$ifdk4/patch= 2006.173.15:27:57.01$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.15:27:57.01$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.15:27:57.01$setupk4/!*+20s 2006.173.15:28:01.87#abcon#<5=/14 0.8 1.6 21.081001003.1\r\n> 2006.173.15:28:01.89#abcon#{5=INTERFACE CLEAR} 2006.173.15:28:01.95#abcon#[5=S1D000X0/0*\r\n] 2006.173.15:28:07.14#trakl#Source acquired 2006.173.15:28:09.14#flagr#flagr/antenna,acquired 2006.173.15:28:11.53$setupk4/"tpicd 2006.173.15:28:11.53$setupk4/echo=off 2006.173.15:28:11.53$setupk4/xlog=off 2006.173.15:28:11.53:!2006.173.15:29:20 2006.173.15:29:20.00:preob 2006.173.15:29:20.14/onsource/TRACKING 2006.173.15:29:20.14:!2006.173.15:29:30 2006.173.15:29:30.00:"tape 2006.173.15:29:30.00:"st=record 2006.173.15:29:30.00:data_valid=on 2006.173.15:29:30.00:midob 2006.173.15:29:30.14/onsource/TRACKING 2006.173.15:29:30.15/wx/21.07,1003.1,100 2006.173.15:29:30.23/cable/+6.5090E-03 2006.173.15:29:31.32/va/01,07,usb,yes,38,41 2006.173.15:29:31.32/va/02,06,usb,yes,38,39 2006.173.15:29:31.32/va/03,05,usb,yes,48,50 2006.173.15:29:31.32/va/04,06,usb,yes,39,40 2006.173.15:29:31.32/va/05,04,usb,yes,30,31 2006.173.15:29:31.32/va/06,03,usb,yes,42,42 2006.173.15:29:31.32/va/07,04,usb,yes,34,36 2006.173.15:29:31.32/va/08,04,usb,yes,29,35 2006.173.15:29:31.55/valo/01,524.99,yes,locked 2006.173.15:29:31.55/valo/02,534.99,yes,locked 2006.173.15:29:31.55/valo/03,564.99,yes,locked 2006.173.15:29:31.55/valo/04,624.99,yes,locked 2006.173.15:29:31.55/valo/05,734.99,yes,locked 2006.173.15:29:31.55/valo/06,814.99,yes,locked 2006.173.15:29:31.55/valo/07,864.99,yes,locked 2006.173.15:29:31.55/valo/08,884.99,yes,locked 2006.173.15:29:32.64/vb/01,04,usb,yes,30,27 2006.173.15:29:32.64/vb/02,04,usb,yes,32,32 2006.173.15:29:32.64/vb/03,04,usb,yes,29,32 2006.173.15:29:32.64/vb/04,04,usb,yes,33,32 2006.173.15:29:32.64/vb/05,04,usb,yes,26,28 2006.173.15:29:32.64/vb/06,04,usb,yes,30,26 2006.173.15:29:32.64/vb/07,04,usb,yes,30,29 2006.173.15:29:32.64/vb/08,04,usb,yes,27,31 2006.173.15:29:32.87/vblo/01,629.99,yes,locked 2006.173.15:29:32.87/vblo/02,634.99,yes,locked 2006.173.15:29:32.87/vblo/03,649.99,yes,locked 2006.173.15:29:32.87/vblo/04,679.99,yes,locked 2006.173.15:29:32.87/vblo/05,709.99,yes,locked 2006.173.15:29:32.87/vblo/06,719.99,yes,locked 2006.173.15:29:32.87/vblo/07,734.99,yes,locked 2006.173.15:29:32.87/vblo/08,744.99,yes,locked 2006.173.15:29:33.02/vabw/8 2006.173.15:29:33.17/vbbw/8 2006.173.15:29:33.26/xfe/off,on,15.2 2006.173.15:29:33.64/ifatt/23,28,28,28 2006.173.15:29:34.07/fmout-gps/S +3.95E-07 2006.173.15:29:34.12:!2006.173.15:30:40 2006.173.15:30:40.01:data_valid=off 2006.173.15:30:40.02:"et 2006.173.15:30:40.02:!+3s 2006.173.15:30:43.03:"tape 2006.173.15:30:43.04:postob 2006.173.15:30:43.09/cable/+6.5081E-03 2006.173.15:30:43.10/wx/21.06,1003.1,100 2006.173.15:30:43.15/fmout-gps/S +3.94E-07 2006.173.15:30:43.16:scan_name=173-1533,jd0606,130 2006.173.15:30:43.16:source=2201+315,220314.98,314538.3,2000.0,cw 2006.173.15:30:45.14#flagr#flagr/antenna,new-source 2006.173.15:30:45.15:checkk5 2006.173.15:30:45.57/chk_autoobs//k5ts1/ autoobs is running! 2006.173.15:30:45.96/chk_autoobs//k5ts2/ autoobs is running! 2006.173.15:30:46.36/chk_autoobs//k5ts3/ autoobs is running! 2006.173.15:30:46.77/chk_autoobs//k5ts4/ autoobs is running! 2006.173.15:30:47.15/chk_obsdata//k5ts1/T1731529??a.dat file size is correct (nominal:280MB, actual:280MB). 2006.173.15:30:47.57/chk_obsdata//k5ts2/T1731529??b.dat file size is correct (nominal:280MB, actual:280MB). 2006.173.15:30:47.96/chk_obsdata//k5ts3/T1731529??c.dat file size is correct (nominal:280MB, actual:280MB). 2006.173.15:30:48.35/chk_obsdata//k5ts4/T1731529??d.dat file size is correct (nominal:280MB, actual:280MB). 2006.173.15:30:49.09/k5log//k5ts1_log_newline 2006.173.15:30:49.80/k5log//k5ts2_log_newline 2006.173.15:30:50.50/k5log//k5ts3_log_newline 2006.173.15:30:51.22/k5log//k5ts4_log_newline 2006.173.15:30:51.24/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.15:30:51.24:setupk4=1 2006.173.15:30:51.24$setupk4/echo=on 2006.173.15:30:51.24$setupk4/pcalon 2006.173.15:30:51.24$pcalon/"no phase cal control is implemented here 2006.173.15:30:51.24$setupk4/"tpicd=stop 2006.173.15:30:51.24$setupk4/"rec=synch_on 2006.173.15:30:51.24$setupk4/"rec_mode=128 2006.173.15:30:51.24$setupk4/!* 2006.173.15:30:51.24$setupk4/recpk4 2006.173.15:30:51.24$recpk4/recpatch= 2006.173.15:30:51.25$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.15:30:51.25$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.15:30:51.25$setupk4/vck44 2006.173.15:30:51.25$vck44/valo=1,524.99 2006.173.15:30:51.25#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.15:30:51.25#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.15:30:51.25#ibcon#ireg 17 cls_cnt 0 2006.173.15:30:51.25#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.15:30:51.25#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.15:30:51.25#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.15:30:51.25#ibcon#enter wrdev, iclass 27, count 0 2006.173.15:30:51.25#ibcon#first serial, iclass 27, count 0 2006.173.15:30:51.25#ibcon#enter sib2, iclass 27, count 0 2006.173.15:30:51.25#ibcon#flushed, iclass 27, count 0 2006.173.15:30:51.25#ibcon#about to write, iclass 27, count 0 2006.173.15:30:51.25#ibcon#wrote, iclass 27, count 0 2006.173.15:30:51.25#ibcon#about to read 3, iclass 27, count 0 2006.173.15:30:51.26#ibcon#read 3, iclass 27, count 0 2006.173.15:30:51.26#ibcon#about to read 4, iclass 27, count 0 2006.173.15:30:51.26#ibcon#read 4, iclass 27, count 0 2006.173.15:30:51.26#ibcon#about to read 5, iclass 27, count 0 2006.173.15:30:51.26#ibcon#read 5, iclass 27, count 0 2006.173.15:30:51.26#ibcon#about to read 6, iclass 27, count 0 2006.173.15:30:51.26#ibcon#read 6, iclass 27, count 0 2006.173.15:30:51.26#ibcon#end of sib2, iclass 27, count 0 2006.173.15:30:51.26#ibcon#*mode == 0, iclass 27, count 0 2006.173.15:30:51.26#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.15:30:51.26#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.15:30:51.26#ibcon#*before write, iclass 27, count 0 2006.173.15:30:51.26#ibcon#enter sib2, iclass 27, count 0 2006.173.15:30:51.26#ibcon#flushed, iclass 27, count 0 2006.173.15:30:51.26#ibcon#about to write, iclass 27, count 0 2006.173.15:30:51.26#ibcon#wrote, iclass 27, count 0 2006.173.15:30:51.26#ibcon#about to read 3, iclass 27, count 0 2006.173.15:30:51.31#ibcon#read 3, iclass 27, count 0 2006.173.15:30:51.31#ibcon#about to read 4, iclass 27, count 0 2006.173.15:30:51.31#ibcon#read 4, iclass 27, count 0 2006.173.15:30:51.31#ibcon#about to read 5, iclass 27, count 0 2006.173.15:30:51.31#ibcon#read 5, iclass 27, count 0 2006.173.15:30:51.31#ibcon#about to read 6, iclass 27, count 0 2006.173.15:30:51.31#ibcon#read 6, iclass 27, count 0 2006.173.15:30:51.31#ibcon#end of sib2, iclass 27, count 0 2006.173.15:30:51.31#ibcon#*after write, iclass 27, count 0 2006.173.15:30:51.31#ibcon#*before return 0, iclass 27, count 0 2006.173.15:30:51.31#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.15:30:51.31#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.15:30:51.31#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.15:30:51.31#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.15:30:51.31$vck44/va=1,7 2006.173.15:30:51.31#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.15:30:51.31#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.15:30:51.31#ibcon#ireg 11 cls_cnt 2 2006.173.15:30:51.31#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.15:30:51.31#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.15:30:51.31#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.15:30:51.31#ibcon#enter wrdev, iclass 29, count 2 2006.173.15:30:51.31#ibcon#first serial, iclass 29, count 2 2006.173.15:30:51.31#ibcon#enter sib2, iclass 29, count 2 2006.173.15:30:51.31#ibcon#flushed, iclass 29, count 2 2006.173.15:30:51.31#ibcon#about to write, iclass 29, count 2 2006.173.15:30:51.31#ibcon#wrote, iclass 29, count 2 2006.173.15:30:51.31#ibcon#about to read 3, iclass 29, count 2 2006.173.15:30:51.33#ibcon#read 3, iclass 29, count 2 2006.173.15:30:51.33#ibcon#about to read 4, iclass 29, count 2 2006.173.15:30:51.33#ibcon#read 4, iclass 29, count 2 2006.173.15:30:51.33#ibcon#about to read 5, iclass 29, count 2 2006.173.15:30:51.33#ibcon#read 5, iclass 29, count 2 2006.173.15:30:51.33#ibcon#about to read 6, iclass 29, count 2 2006.173.15:30:51.33#ibcon#read 6, iclass 29, count 2 2006.173.15:30:51.33#ibcon#end of sib2, iclass 29, count 2 2006.173.15:30:51.33#ibcon#*mode == 0, iclass 29, count 2 2006.173.15:30:51.33#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.15:30:51.33#ibcon#[25=AT01-07\r\n] 2006.173.15:30:51.33#ibcon#*before write, iclass 29, count 2 2006.173.15:30:51.33#ibcon#enter sib2, iclass 29, count 2 2006.173.15:30:51.33#ibcon#flushed, iclass 29, count 2 2006.173.15:30:51.33#ibcon#about to write, iclass 29, count 2 2006.173.15:30:51.33#ibcon#wrote, iclass 29, count 2 2006.173.15:30:51.33#ibcon#about to read 3, iclass 29, count 2 2006.173.15:30:51.36#ibcon#read 3, iclass 29, count 2 2006.173.15:30:51.36#ibcon#about to read 4, iclass 29, count 2 2006.173.15:30:51.36#ibcon#read 4, iclass 29, count 2 2006.173.15:30:51.36#ibcon#about to read 5, iclass 29, count 2 2006.173.15:30:51.36#ibcon#read 5, iclass 29, count 2 2006.173.15:30:51.36#ibcon#about to read 6, iclass 29, count 2 2006.173.15:30:51.36#ibcon#read 6, iclass 29, count 2 2006.173.15:30:51.36#ibcon#end of sib2, iclass 29, count 2 2006.173.15:30:51.36#ibcon#*after write, iclass 29, count 2 2006.173.15:30:51.36#ibcon#*before return 0, iclass 29, count 2 2006.173.15:30:51.36#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.15:30:51.36#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.15:30:51.36#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.15:30:51.36#ibcon#ireg 7 cls_cnt 0 2006.173.15:30:51.36#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.15:30:51.48#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.15:30:51.48#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.15:30:51.48#ibcon#enter wrdev, iclass 29, count 0 2006.173.15:30:51.48#ibcon#first serial, iclass 29, count 0 2006.173.15:30:51.48#ibcon#enter sib2, iclass 29, count 0 2006.173.15:30:51.48#ibcon#flushed, iclass 29, count 0 2006.173.15:30:51.48#ibcon#about to write, iclass 29, count 0 2006.173.15:30:51.48#ibcon#wrote, iclass 29, count 0 2006.173.15:30:51.48#ibcon#about to read 3, iclass 29, count 0 2006.173.15:30:51.50#ibcon#read 3, iclass 29, count 0 2006.173.15:30:51.50#ibcon#about to read 4, iclass 29, count 0 2006.173.15:30:51.50#ibcon#read 4, iclass 29, count 0 2006.173.15:30:51.50#ibcon#about to read 5, iclass 29, count 0 2006.173.15:30:51.50#ibcon#read 5, iclass 29, count 0 2006.173.15:30:51.50#ibcon#about to read 6, iclass 29, count 0 2006.173.15:30:51.50#ibcon#read 6, iclass 29, count 0 2006.173.15:30:51.50#ibcon#end of sib2, iclass 29, count 0 2006.173.15:30:51.50#ibcon#*mode == 0, iclass 29, count 0 2006.173.15:30:51.50#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.15:30:51.50#ibcon#[25=USB\r\n] 2006.173.15:30:51.50#ibcon#*before write, iclass 29, count 0 2006.173.15:30:51.50#ibcon#enter sib2, iclass 29, count 0 2006.173.15:30:51.50#ibcon#flushed, iclass 29, count 0 2006.173.15:30:51.50#ibcon#about to write, iclass 29, count 0 2006.173.15:30:51.50#ibcon#wrote, iclass 29, count 0 2006.173.15:30:51.50#ibcon#about to read 3, iclass 29, count 0 2006.173.15:30:51.53#ibcon#read 3, iclass 29, count 0 2006.173.15:30:51.53#ibcon#about to read 4, iclass 29, count 0 2006.173.15:30:51.53#ibcon#read 4, iclass 29, count 0 2006.173.15:30:51.53#ibcon#about to read 5, iclass 29, count 0 2006.173.15:30:51.53#ibcon#read 5, iclass 29, count 0 2006.173.15:30:51.53#ibcon#about to read 6, iclass 29, count 0 2006.173.15:30:51.53#ibcon#read 6, iclass 29, count 0 2006.173.15:30:51.53#ibcon#end of sib2, iclass 29, count 0 2006.173.15:30:51.53#ibcon#*after write, iclass 29, count 0 2006.173.15:30:51.53#ibcon#*before return 0, iclass 29, count 0 2006.173.15:30:51.53#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.15:30:51.53#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.15:30:51.53#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.15:30:51.53#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.15:30:51.53$vck44/valo=2,534.99 2006.173.15:30:51.53#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.15:30:51.53#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.15:30:51.53#ibcon#ireg 17 cls_cnt 0 2006.173.15:30:51.53#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.15:30:51.53#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.15:30:51.53#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.15:30:51.53#ibcon#enter wrdev, iclass 31, count 0 2006.173.15:30:51.53#ibcon#first serial, iclass 31, count 0 2006.173.15:30:51.53#ibcon#enter sib2, iclass 31, count 0 2006.173.15:30:51.53#ibcon#flushed, iclass 31, count 0 2006.173.15:30:51.53#ibcon#about to write, iclass 31, count 0 2006.173.15:30:51.53#ibcon#wrote, iclass 31, count 0 2006.173.15:30:51.53#ibcon#about to read 3, iclass 31, count 0 2006.173.15:30:51.55#ibcon#read 3, iclass 31, count 0 2006.173.15:30:51.55#ibcon#about to read 4, iclass 31, count 0 2006.173.15:30:51.55#ibcon#read 4, iclass 31, count 0 2006.173.15:30:51.55#ibcon#about to read 5, iclass 31, count 0 2006.173.15:30:51.55#ibcon#read 5, iclass 31, count 0 2006.173.15:30:51.55#ibcon#about to read 6, iclass 31, count 0 2006.173.15:30:51.55#ibcon#read 6, iclass 31, count 0 2006.173.15:30:51.55#ibcon#end of sib2, iclass 31, count 0 2006.173.15:30:51.55#ibcon#*mode == 0, iclass 31, count 0 2006.173.15:30:51.55#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.15:30:51.55#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.15:30:51.55#ibcon#*before write, iclass 31, count 0 2006.173.15:30:51.55#ibcon#enter sib2, iclass 31, count 0 2006.173.15:30:51.55#ibcon#flushed, iclass 31, count 0 2006.173.15:30:51.55#ibcon#about to write, iclass 31, count 0 2006.173.15:30:51.55#ibcon#wrote, iclass 31, count 0 2006.173.15:30:51.55#ibcon#about to read 3, iclass 31, count 0 2006.173.15:30:51.59#ibcon#read 3, iclass 31, count 0 2006.173.15:30:51.59#ibcon#about to read 4, iclass 31, count 0 2006.173.15:30:51.59#ibcon#read 4, iclass 31, count 0 2006.173.15:30:51.59#ibcon#about to read 5, iclass 31, count 0 2006.173.15:30:51.59#ibcon#read 5, iclass 31, count 0 2006.173.15:30:51.59#ibcon#about to read 6, iclass 31, count 0 2006.173.15:30:51.59#ibcon#read 6, iclass 31, count 0 2006.173.15:30:51.59#ibcon#end of sib2, iclass 31, count 0 2006.173.15:30:51.59#ibcon#*after write, iclass 31, count 0 2006.173.15:30:51.59#ibcon#*before return 0, iclass 31, count 0 2006.173.15:30:51.59#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.15:30:51.59#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.15:30:51.59#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.15:30:51.59#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.15:30:51.59$vck44/va=2,6 2006.173.15:30:51.59#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.173.15:30:51.59#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.173.15:30:51.59#ibcon#ireg 11 cls_cnt 2 2006.173.15:30:51.59#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.15:30:51.65#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.15:30:51.65#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.15:30:51.65#ibcon#enter wrdev, iclass 33, count 2 2006.173.15:30:51.65#ibcon#first serial, iclass 33, count 2 2006.173.15:30:51.65#ibcon#enter sib2, iclass 33, count 2 2006.173.15:30:51.65#ibcon#flushed, iclass 33, count 2 2006.173.15:30:51.65#ibcon#about to write, iclass 33, count 2 2006.173.15:30:51.65#ibcon#wrote, iclass 33, count 2 2006.173.15:30:51.65#ibcon#about to read 3, iclass 33, count 2 2006.173.15:30:51.67#ibcon#read 3, iclass 33, count 2 2006.173.15:30:51.67#ibcon#about to read 4, iclass 33, count 2 2006.173.15:30:51.67#ibcon#read 4, iclass 33, count 2 2006.173.15:30:51.67#ibcon#about to read 5, iclass 33, count 2 2006.173.15:30:51.67#ibcon#read 5, iclass 33, count 2 2006.173.15:30:51.67#ibcon#about to read 6, iclass 33, count 2 2006.173.15:30:51.67#ibcon#read 6, iclass 33, count 2 2006.173.15:30:51.67#ibcon#end of sib2, iclass 33, count 2 2006.173.15:30:51.67#ibcon#*mode == 0, iclass 33, count 2 2006.173.15:30:51.67#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.173.15:30:51.67#ibcon#[25=AT02-06\r\n] 2006.173.15:30:51.67#ibcon#*before write, iclass 33, count 2 2006.173.15:30:51.67#ibcon#enter sib2, iclass 33, count 2 2006.173.15:30:51.67#ibcon#flushed, iclass 33, count 2 2006.173.15:30:51.67#ibcon#about to write, iclass 33, count 2 2006.173.15:30:51.67#ibcon#wrote, iclass 33, count 2 2006.173.15:30:51.67#ibcon#about to read 3, iclass 33, count 2 2006.173.15:30:51.70#ibcon#read 3, iclass 33, count 2 2006.173.15:30:51.70#ibcon#about to read 4, iclass 33, count 2 2006.173.15:30:51.70#ibcon#read 4, iclass 33, count 2 2006.173.15:30:51.70#ibcon#about to read 5, iclass 33, count 2 2006.173.15:30:51.70#ibcon#read 5, iclass 33, count 2 2006.173.15:30:51.70#ibcon#about to read 6, iclass 33, count 2 2006.173.15:30:51.70#ibcon#read 6, iclass 33, count 2 2006.173.15:30:51.70#ibcon#end of sib2, iclass 33, count 2 2006.173.15:30:51.70#ibcon#*after write, iclass 33, count 2 2006.173.15:30:51.70#ibcon#*before return 0, iclass 33, count 2 2006.173.15:30:51.70#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.15:30:51.70#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.173.15:30:51.70#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.173.15:30:51.70#ibcon#ireg 7 cls_cnt 0 2006.173.15:30:51.70#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.15:30:51.82#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.15:30:51.82#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.15:30:51.82#ibcon#enter wrdev, iclass 33, count 0 2006.173.15:30:51.82#ibcon#first serial, iclass 33, count 0 2006.173.15:30:51.82#ibcon#enter sib2, iclass 33, count 0 2006.173.15:30:51.82#ibcon#flushed, iclass 33, count 0 2006.173.15:30:51.82#ibcon#about to write, iclass 33, count 0 2006.173.15:30:51.82#ibcon#wrote, iclass 33, count 0 2006.173.15:30:51.82#ibcon#about to read 3, iclass 33, count 0 2006.173.15:30:51.84#ibcon#read 3, iclass 33, count 0 2006.173.15:30:51.84#ibcon#about to read 4, iclass 33, count 0 2006.173.15:30:51.84#ibcon#read 4, iclass 33, count 0 2006.173.15:30:51.84#ibcon#about to read 5, iclass 33, count 0 2006.173.15:30:51.84#ibcon#read 5, iclass 33, count 0 2006.173.15:30:51.84#ibcon#about to read 6, iclass 33, count 0 2006.173.15:30:51.84#ibcon#read 6, iclass 33, count 0 2006.173.15:30:51.84#ibcon#end of sib2, iclass 33, count 0 2006.173.15:30:51.84#ibcon#*mode == 0, iclass 33, count 0 2006.173.15:30:51.84#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.15:30:51.84#ibcon#[25=USB\r\n] 2006.173.15:30:51.84#ibcon#*before write, iclass 33, count 0 2006.173.15:30:51.84#ibcon#enter sib2, iclass 33, count 0 2006.173.15:30:51.84#ibcon#flushed, iclass 33, count 0 2006.173.15:30:51.84#ibcon#about to write, iclass 33, count 0 2006.173.15:30:51.84#ibcon#wrote, iclass 33, count 0 2006.173.15:30:51.84#ibcon#about to read 3, iclass 33, count 0 2006.173.15:30:51.87#ibcon#read 3, iclass 33, count 0 2006.173.15:30:51.87#ibcon#about to read 4, iclass 33, count 0 2006.173.15:30:51.87#ibcon#read 4, iclass 33, count 0 2006.173.15:30:51.87#ibcon#about to read 5, iclass 33, count 0 2006.173.15:30:51.87#ibcon#read 5, iclass 33, count 0 2006.173.15:30:51.87#ibcon#about to read 6, iclass 33, count 0 2006.173.15:30:51.87#ibcon#read 6, iclass 33, count 0 2006.173.15:30:51.87#ibcon#end of sib2, iclass 33, count 0 2006.173.15:30:51.87#ibcon#*after write, iclass 33, count 0 2006.173.15:30:51.87#ibcon#*before return 0, iclass 33, count 0 2006.173.15:30:51.87#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.15:30:51.87#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.173.15:30:51.87#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.15:30:51.87#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.15:30:51.87$vck44/valo=3,564.99 2006.173.15:30:51.87#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.15:30:51.87#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.15:30:51.87#ibcon#ireg 17 cls_cnt 0 2006.173.15:30:51.87#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.15:30:51.87#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.15:30:51.87#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.15:30:51.87#ibcon#enter wrdev, iclass 35, count 0 2006.173.15:30:51.87#ibcon#first serial, iclass 35, count 0 2006.173.15:30:51.87#ibcon#enter sib2, iclass 35, count 0 2006.173.15:30:51.87#ibcon#flushed, iclass 35, count 0 2006.173.15:30:51.87#ibcon#about to write, iclass 35, count 0 2006.173.15:30:51.87#ibcon#wrote, iclass 35, count 0 2006.173.15:30:51.87#ibcon#about to read 3, iclass 35, count 0 2006.173.15:30:51.89#ibcon#read 3, iclass 35, count 0 2006.173.15:30:51.89#ibcon#about to read 4, iclass 35, count 0 2006.173.15:30:51.89#ibcon#read 4, iclass 35, count 0 2006.173.15:30:51.89#ibcon#about to read 5, iclass 35, count 0 2006.173.15:30:51.89#ibcon#read 5, iclass 35, count 0 2006.173.15:30:51.89#ibcon#about to read 6, iclass 35, count 0 2006.173.15:30:51.89#ibcon#read 6, iclass 35, count 0 2006.173.15:30:51.89#ibcon#end of sib2, iclass 35, count 0 2006.173.15:30:51.89#ibcon#*mode == 0, iclass 35, count 0 2006.173.15:30:51.89#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.15:30:51.89#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.15:30:51.89#ibcon#*before write, iclass 35, count 0 2006.173.15:30:51.89#ibcon#enter sib2, iclass 35, count 0 2006.173.15:30:51.89#ibcon#flushed, iclass 35, count 0 2006.173.15:30:51.89#ibcon#about to write, iclass 35, count 0 2006.173.15:30:51.89#ibcon#wrote, iclass 35, count 0 2006.173.15:30:51.89#ibcon#about to read 3, iclass 35, count 0 2006.173.15:30:51.93#ibcon#read 3, iclass 35, count 0 2006.173.15:30:51.93#ibcon#about to read 4, iclass 35, count 0 2006.173.15:30:51.93#ibcon#read 4, iclass 35, count 0 2006.173.15:30:51.93#ibcon#about to read 5, iclass 35, count 0 2006.173.15:30:51.93#ibcon#read 5, iclass 35, count 0 2006.173.15:30:51.93#ibcon#about to read 6, iclass 35, count 0 2006.173.15:30:51.93#ibcon#read 6, iclass 35, count 0 2006.173.15:30:51.93#ibcon#end of sib2, iclass 35, count 0 2006.173.15:30:51.93#ibcon#*after write, iclass 35, count 0 2006.173.15:30:51.93#ibcon#*before return 0, iclass 35, count 0 2006.173.15:30:51.93#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.15:30:51.93#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.15:30:51.93#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.15:30:51.93#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.15:30:51.93$vck44/va=3,5 2006.173.15:30:51.93#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.173.15:30:51.93#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.173.15:30:51.93#ibcon#ireg 11 cls_cnt 2 2006.173.15:30:51.93#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.15:30:51.99#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.15:30:51.99#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.15:30:51.99#ibcon#enter wrdev, iclass 37, count 2 2006.173.15:30:51.99#ibcon#first serial, iclass 37, count 2 2006.173.15:30:51.99#ibcon#enter sib2, iclass 37, count 2 2006.173.15:30:51.99#ibcon#flushed, iclass 37, count 2 2006.173.15:30:51.99#ibcon#about to write, iclass 37, count 2 2006.173.15:30:51.99#ibcon#wrote, iclass 37, count 2 2006.173.15:30:51.99#ibcon#about to read 3, iclass 37, count 2 2006.173.15:30:52.01#ibcon#read 3, iclass 37, count 2 2006.173.15:30:52.01#ibcon#about to read 4, iclass 37, count 2 2006.173.15:30:52.01#ibcon#read 4, iclass 37, count 2 2006.173.15:30:52.01#ibcon#about to read 5, iclass 37, count 2 2006.173.15:30:52.01#ibcon#read 5, iclass 37, count 2 2006.173.15:30:52.01#ibcon#about to read 6, iclass 37, count 2 2006.173.15:30:52.01#ibcon#read 6, iclass 37, count 2 2006.173.15:30:52.01#ibcon#end of sib2, iclass 37, count 2 2006.173.15:30:52.01#ibcon#*mode == 0, iclass 37, count 2 2006.173.15:30:52.01#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.173.15:30:52.01#ibcon#[25=AT03-05\r\n] 2006.173.15:30:52.01#ibcon#*before write, iclass 37, count 2 2006.173.15:30:52.01#ibcon#enter sib2, iclass 37, count 2 2006.173.15:30:52.01#ibcon#flushed, iclass 37, count 2 2006.173.15:30:52.01#ibcon#about to write, iclass 37, count 2 2006.173.15:30:52.01#ibcon#wrote, iclass 37, count 2 2006.173.15:30:52.01#ibcon#about to read 3, iclass 37, count 2 2006.173.15:30:52.04#ibcon#read 3, iclass 37, count 2 2006.173.15:30:52.04#ibcon#about to read 4, iclass 37, count 2 2006.173.15:30:52.04#ibcon#read 4, iclass 37, count 2 2006.173.15:30:52.04#ibcon#about to read 5, iclass 37, count 2 2006.173.15:30:52.04#ibcon#read 5, iclass 37, count 2 2006.173.15:30:52.04#ibcon#about to read 6, iclass 37, count 2 2006.173.15:30:52.04#ibcon#read 6, iclass 37, count 2 2006.173.15:30:52.04#ibcon#end of sib2, iclass 37, count 2 2006.173.15:30:52.04#ibcon#*after write, iclass 37, count 2 2006.173.15:30:52.04#ibcon#*before return 0, iclass 37, count 2 2006.173.15:30:52.04#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.15:30:52.04#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.173.15:30:52.04#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.173.15:30:52.04#ibcon#ireg 7 cls_cnt 0 2006.173.15:30:52.04#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.15:30:52.16#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.15:30:52.16#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.15:30:52.16#ibcon#enter wrdev, iclass 37, count 0 2006.173.15:30:52.16#ibcon#first serial, iclass 37, count 0 2006.173.15:30:52.16#ibcon#enter sib2, iclass 37, count 0 2006.173.15:30:52.16#ibcon#flushed, iclass 37, count 0 2006.173.15:30:52.16#ibcon#about to write, iclass 37, count 0 2006.173.15:30:52.16#ibcon#wrote, iclass 37, count 0 2006.173.15:30:52.16#ibcon#about to read 3, iclass 37, count 0 2006.173.15:30:52.18#ibcon#read 3, iclass 37, count 0 2006.173.15:30:52.18#ibcon#about to read 4, iclass 37, count 0 2006.173.15:30:52.18#ibcon#read 4, iclass 37, count 0 2006.173.15:30:52.18#ibcon#about to read 5, iclass 37, count 0 2006.173.15:30:52.18#ibcon#read 5, iclass 37, count 0 2006.173.15:30:52.18#ibcon#about to read 6, iclass 37, count 0 2006.173.15:30:52.18#ibcon#read 6, iclass 37, count 0 2006.173.15:30:52.18#ibcon#end of sib2, iclass 37, count 0 2006.173.15:30:52.18#ibcon#*mode == 0, iclass 37, count 0 2006.173.15:30:52.18#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.15:30:52.18#ibcon#[25=USB\r\n] 2006.173.15:30:52.18#ibcon#*before write, iclass 37, count 0 2006.173.15:30:52.18#ibcon#enter sib2, iclass 37, count 0 2006.173.15:30:52.18#ibcon#flushed, iclass 37, count 0 2006.173.15:30:52.18#ibcon#about to write, iclass 37, count 0 2006.173.15:30:52.18#ibcon#wrote, iclass 37, count 0 2006.173.15:30:52.18#ibcon#about to read 3, iclass 37, count 0 2006.173.15:30:52.21#ibcon#read 3, iclass 37, count 0 2006.173.15:30:52.21#ibcon#about to read 4, iclass 37, count 0 2006.173.15:30:52.21#ibcon#read 4, iclass 37, count 0 2006.173.15:30:52.21#ibcon#about to read 5, iclass 37, count 0 2006.173.15:30:52.21#ibcon#read 5, iclass 37, count 0 2006.173.15:30:52.21#ibcon#about to read 6, iclass 37, count 0 2006.173.15:30:52.21#ibcon#read 6, iclass 37, count 0 2006.173.15:30:52.21#ibcon#end of sib2, iclass 37, count 0 2006.173.15:30:52.21#ibcon#*after write, iclass 37, count 0 2006.173.15:30:52.21#ibcon#*before return 0, iclass 37, count 0 2006.173.15:30:52.21#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.15:30:52.21#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.173.15:30:52.21#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.15:30:52.21#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.15:30:52.21$vck44/valo=4,624.99 2006.173.15:30:52.21#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.15:30:52.21#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.15:30:52.21#ibcon#ireg 17 cls_cnt 0 2006.173.15:30:52.21#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.15:30:52.21#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.15:30:52.21#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.15:30:52.21#ibcon#enter wrdev, iclass 39, count 0 2006.173.15:30:52.21#ibcon#first serial, iclass 39, count 0 2006.173.15:30:52.21#ibcon#enter sib2, iclass 39, count 0 2006.173.15:30:52.21#ibcon#flushed, iclass 39, count 0 2006.173.15:30:52.21#ibcon#about to write, iclass 39, count 0 2006.173.15:30:52.21#ibcon#wrote, iclass 39, count 0 2006.173.15:30:52.21#ibcon#about to read 3, iclass 39, count 0 2006.173.15:30:52.23#ibcon#read 3, iclass 39, count 0 2006.173.15:30:52.23#ibcon#about to read 4, iclass 39, count 0 2006.173.15:30:52.23#ibcon#read 4, iclass 39, count 0 2006.173.15:30:52.23#ibcon#about to read 5, iclass 39, count 0 2006.173.15:30:52.23#ibcon#read 5, iclass 39, count 0 2006.173.15:30:52.23#ibcon#about to read 6, iclass 39, count 0 2006.173.15:30:52.23#ibcon#read 6, iclass 39, count 0 2006.173.15:30:52.23#ibcon#end of sib2, iclass 39, count 0 2006.173.15:30:52.23#ibcon#*mode == 0, iclass 39, count 0 2006.173.15:30:52.23#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.15:30:52.23#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.15:30:52.23#ibcon#*before write, iclass 39, count 0 2006.173.15:30:52.23#ibcon#enter sib2, iclass 39, count 0 2006.173.15:30:52.23#ibcon#flushed, iclass 39, count 0 2006.173.15:30:52.23#ibcon#about to write, iclass 39, count 0 2006.173.15:30:52.23#ibcon#wrote, iclass 39, count 0 2006.173.15:30:52.23#ibcon#about to read 3, iclass 39, count 0 2006.173.15:30:52.27#ibcon#read 3, iclass 39, count 0 2006.173.15:30:52.27#ibcon#about to read 4, iclass 39, count 0 2006.173.15:30:52.27#ibcon#read 4, iclass 39, count 0 2006.173.15:30:52.27#ibcon#about to read 5, iclass 39, count 0 2006.173.15:30:52.27#ibcon#read 5, iclass 39, count 0 2006.173.15:30:52.27#ibcon#about to read 6, iclass 39, count 0 2006.173.15:30:52.27#ibcon#read 6, iclass 39, count 0 2006.173.15:30:52.27#ibcon#end of sib2, iclass 39, count 0 2006.173.15:30:52.27#ibcon#*after write, iclass 39, count 0 2006.173.15:30:52.27#ibcon#*before return 0, iclass 39, count 0 2006.173.15:30:52.27#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.15:30:52.27#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.15:30:52.27#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.15:30:52.27#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.15:30:52.27$vck44/va=4,6 2006.173.15:30:52.27#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.15:30:52.27#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.15:30:52.27#ibcon#ireg 11 cls_cnt 2 2006.173.15:30:52.27#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.15:30:52.33#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.15:30:52.33#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.15:30:52.33#ibcon#enter wrdev, iclass 3, count 2 2006.173.15:30:52.33#ibcon#first serial, iclass 3, count 2 2006.173.15:30:52.33#ibcon#enter sib2, iclass 3, count 2 2006.173.15:30:52.33#ibcon#flushed, iclass 3, count 2 2006.173.15:30:52.33#ibcon#about to write, iclass 3, count 2 2006.173.15:30:52.33#ibcon#wrote, iclass 3, count 2 2006.173.15:30:52.33#ibcon#about to read 3, iclass 3, count 2 2006.173.15:30:52.35#ibcon#read 3, iclass 3, count 2 2006.173.15:30:52.35#ibcon#about to read 4, iclass 3, count 2 2006.173.15:30:52.35#ibcon#read 4, iclass 3, count 2 2006.173.15:30:52.35#ibcon#about to read 5, iclass 3, count 2 2006.173.15:30:52.35#ibcon#read 5, iclass 3, count 2 2006.173.15:30:52.35#ibcon#about to read 6, iclass 3, count 2 2006.173.15:30:52.35#ibcon#read 6, iclass 3, count 2 2006.173.15:30:52.35#ibcon#end of sib2, iclass 3, count 2 2006.173.15:30:52.35#ibcon#*mode == 0, iclass 3, count 2 2006.173.15:30:52.35#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.15:30:52.35#ibcon#[25=AT04-06\r\n] 2006.173.15:30:52.35#ibcon#*before write, iclass 3, count 2 2006.173.15:30:52.35#ibcon#enter sib2, iclass 3, count 2 2006.173.15:30:52.35#ibcon#flushed, iclass 3, count 2 2006.173.15:30:52.35#ibcon#about to write, iclass 3, count 2 2006.173.15:30:52.35#ibcon#wrote, iclass 3, count 2 2006.173.15:30:52.35#ibcon#about to read 3, iclass 3, count 2 2006.173.15:30:52.38#ibcon#read 3, iclass 3, count 2 2006.173.15:30:52.38#ibcon#about to read 4, iclass 3, count 2 2006.173.15:30:52.38#ibcon#read 4, iclass 3, count 2 2006.173.15:30:52.38#ibcon#about to read 5, iclass 3, count 2 2006.173.15:30:52.38#ibcon#read 5, iclass 3, count 2 2006.173.15:30:52.38#ibcon#about to read 6, iclass 3, count 2 2006.173.15:30:52.38#ibcon#read 6, iclass 3, count 2 2006.173.15:30:52.38#ibcon#end of sib2, iclass 3, count 2 2006.173.15:30:52.38#ibcon#*after write, iclass 3, count 2 2006.173.15:30:52.38#ibcon#*before return 0, iclass 3, count 2 2006.173.15:30:52.38#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.15:30:52.38#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.15:30:52.38#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.15:30:52.38#ibcon#ireg 7 cls_cnt 0 2006.173.15:30:52.38#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.15:30:52.50#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.15:30:52.50#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.15:30:52.50#ibcon#enter wrdev, iclass 3, count 0 2006.173.15:30:52.50#ibcon#first serial, iclass 3, count 0 2006.173.15:30:52.50#ibcon#enter sib2, iclass 3, count 0 2006.173.15:30:52.50#ibcon#flushed, iclass 3, count 0 2006.173.15:30:52.50#ibcon#about to write, iclass 3, count 0 2006.173.15:30:52.50#ibcon#wrote, iclass 3, count 0 2006.173.15:30:52.50#ibcon#about to read 3, iclass 3, count 0 2006.173.15:30:52.52#ibcon#read 3, iclass 3, count 0 2006.173.15:30:52.52#ibcon#about to read 4, iclass 3, count 0 2006.173.15:30:52.52#ibcon#read 4, iclass 3, count 0 2006.173.15:30:52.52#ibcon#about to read 5, iclass 3, count 0 2006.173.15:30:52.52#ibcon#read 5, iclass 3, count 0 2006.173.15:30:52.52#ibcon#about to read 6, iclass 3, count 0 2006.173.15:30:52.52#ibcon#read 6, iclass 3, count 0 2006.173.15:30:52.52#ibcon#end of sib2, iclass 3, count 0 2006.173.15:30:52.52#ibcon#*mode == 0, iclass 3, count 0 2006.173.15:30:52.52#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.15:30:52.52#ibcon#[25=USB\r\n] 2006.173.15:30:52.52#ibcon#*before write, iclass 3, count 0 2006.173.15:30:52.52#ibcon#enter sib2, iclass 3, count 0 2006.173.15:30:52.52#ibcon#flushed, iclass 3, count 0 2006.173.15:30:52.52#ibcon#about to write, iclass 3, count 0 2006.173.15:30:52.52#ibcon#wrote, iclass 3, count 0 2006.173.15:30:52.52#ibcon#about to read 3, iclass 3, count 0 2006.173.15:30:52.55#ibcon#read 3, iclass 3, count 0 2006.173.15:30:52.55#ibcon#about to read 4, iclass 3, count 0 2006.173.15:30:52.55#ibcon#read 4, iclass 3, count 0 2006.173.15:30:52.55#ibcon#about to read 5, iclass 3, count 0 2006.173.15:30:52.55#ibcon#read 5, iclass 3, count 0 2006.173.15:30:52.55#ibcon#about to read 6, iclass 3, count 0 2006.173.15:30:52.55#ibcon#read 6, iclass 3, count 0 2006.173.15:30:52.55#ibcon#end of sib2, iclass 3, count 0 2006.173.15:30:52.55#ibcon#*after write, iclass 3, count 0 2006.173.15:30:52.55#ibcon#*before return 0, iclass 3, count 0 2006.173.15:30:52.55#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.15:30:52.55#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.15:30:52.55#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.15:30:52.55#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.15:30:52.55$vck44/valo=5,734.99 2006.173.15:30:52.55#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.15:30:52.55#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.15:30:52.55#ibcon#ireg 17 cls_cnt 0 2006.173.15:30:52.55#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.15:30:52.55#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.15:30:52.55#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.15:30:52.55#ibcon#enter wrdev, iclass 5, count 0 2006.173.15:30:52.55#ibcon#first serial, iclass 5, count 0 2006.173.15:30:52.55#ibcon#enter sib2, iclass 5, count 0 2006.173.15:30:52.55#ibcon#flushed, iclass 5, count 0 2006.173.15:30:52.55#ibcon#about to write, iclass 5, count 0 2006.173.15:30:52.55#ibcon#wrote, iclass 5, count 0 2006.173.15:30:52.55#ibcon#about to read 3, iclass 5, count 0 2006.173.15:30:52.57#ibcon#read 3, iclass 5, count 0 2006.173.15:30:52.57#ibcon#about to read 4, iclass 5, count 0 2006.173.15:30:52.57#ibcon#read 4, iclass 5, count 0 2006.173.15:30:52.57#ibcon#about to read 5, iclass 5, count 0 2006.173.15:30:52.57#ibcon#read 5, iclass 5, count 0 2006.173.15:30:52.57#ibcon#about to read 6, iclass 5, count 0 2006.173.15:30:52.57#ibcon#read 6, iclass 5, count 0 2006.173.15:30:52.57#ibcon#end of sib2, iclass 5, count 0 2006.173.15:30:52.57#ibcon#*mode == 0, iclass 5, count 0 2006.173.15:30:52.57#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.15:30:52.57#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.15:30:52.57#ibcon#*before write, iclass 5, count 0 2006.173.15:30:52.57#ibcon#enter sib2, iclass 5, count 0 2006.173.15:30:52.57#ibcon#flushed, iclass 5, count 0 2006.173.15:30:52.57#ibcon#about to write, iclass 5, count 0 2006.173.15:30:52.57#ibcon#wrote, iclass 5, count 0 2006.173.15:30:52.57#ibcon#about to read 3, iclass 5, count 0 2006.173.15:30:52.61#ibcon#read 3, iclass 5, count 0 2006.173.15:30:52.61#ibcon#about to read 4, iclass 5, count 0 2006.173.15:30:52.61#ibcon#read 4, iclass 5, count 0 2006.173.15:30:52.61#ibcon#about to read 5, iclass 5, count 0 2006.173.15:30:52.61#ibcon#read 5, iclass 5, count 0 2006.173.15:30:52.61#ibcon#about to read 6, iclass 5, count 0 2006.173.15:30:52.61#ibcon#read 6, iclass 5, count 0 2006.173.15:30:52.61#ibcon#end of sib2, iclass 5, count 0 2006.173.15:30:52.61#ibcon#*after write, iclass 5, count 0 2006.173.15:30:52.61#ibcon#*before return 0, iclass 5, count 0 2006.173.15:30:52.61#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.15:30:52.61#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.15:30:52.61#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.15:30:52.61#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.15:30:52.61$vck44/va=5,4 2006.173.15:30:52.61#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.173.15:30:52.61#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.173.15:30:52.61#ibcon#ireg 11 cls_cnt 2 2006.173.15:30:52.61#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.15:30:52.67#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.15:30:52.67#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.15:30:52.67#ibcon#enter wrdev, iclass 7, count 2 2006.173.15:30:52.67#ibcon#first serial, iclass 7, count 2 2006.173.15:30:52.67#ibcon#enter sib2, iclass 7, count 2 2006.173.15:30:52.67#ibcon#flushed, iclass 7, count 2 2006.173.15:30:52.67#ibcon#about to write, iclass 7, count 2 2006.173.15:30:52.67#ibcon#wrote, iclass 7, count 2 2006.173.15:30:52.67#ibcon#about to read 3, iclass 7, count 2 2006.173.15:30:52.69#ibcon#read 3, iclass 7, count 2 2006.173.15:30:52.69#ibcon#about to read 4, iclass 7, count 2 2006.173.15:30:52.69#ibcon#read 4, iclass 7, count 2 2006.173.15:30:52.69#ibcon#about to read 5, iclass 7, count 2 2006.173.15:30:52.69#ibcon#read 5, iclass 7, count 2 2006.173.15:30:52.69#ibcon#about to read 6, iclass 7, count 2 2006.173.15:30:52.69#ibcon#read 6, iclass 7, count 2 2006.173.15:30:52.69#ibcon#end of sib2, iclass 7, count 2 2006.173.15:30:52.69#ibcon#*mode == 0, iclass 7, count 2 2006.173.15:30:52.69#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.173.15:30:52.69#ibcon#[25=AT05-04\r\n] 2006.173.15:30:52.69#ibcon#*before write, iclass 7, count 2 2006.173.15:30:52.69#ibcon#enter sib2, iclass 7, count 2 2006.173.15:30:52.69#ibcon#flushed, iclass 7, count 2 2006.173.15:30:52.69#ibcon#about to write, iclass 7, count 2 2006.173.15:30:52.69#ibcon#wrote, iclass 7, count 2 2006.173.15:30:52.69#ibcon#about to read 3, iclass 7, count 2 2006.173.15:30:52.72#ibcon#read 3, iclass 7, count 2 2006.173.15:30:52.72#ibcon#about to read 4, iclass 7, count 2 2006.173.15:30:52.72#ibcon#read 4, iclass 7, count 2 2006.173.15:30:52.72#ibcon#about to read 5, iclass 7, count 2 2006.173.15:30:52.72#ibcon#read 5, iclass 7, count 2 2006.173.15:30:52.72#ibcon#about to read 6, iclass 7, count 2 2006.173.15:30:52.72#ibcon#read 6, iclass 7, count 2 2006.173.15:30:52.72#ibcon#end of sib2, iclass 7, count 2 2006.173.15:30:52.72#ibcon#*after write, iclass 7, count 2 2006.173.15:30:52.72#ibcon#*before return 0, iclass 7, count 2 2006.173.15:30:52.72#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.15:30:52.72#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.173.15:30:52.72#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.173.15:30:52.72#ibcon#ireg 7 cls_cnt 0 2006.173.15:30:52.72#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.15:30:52.84#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.15:30:52.84#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.15:30:52.84#ibcon#enter wrdev, iclass 7, count 0 2006.173.15:30:52.84#ibcon#first serial, iclass 7, count 0 2006.173.15:30:52.84#ibcon#enter sib2, iclass 7, count 0 2006.173.15:30:52.84#ibcon#flushed, iclass 7, count 0 2006.173.15:30:52.84#ibcon#about to write, iclass 7, count 0 2006.173.15:30:52.84#ibcon#wrote, iclass 7, count 0 2006.173.15:30:52.84#ibcon#about to read 3, iclass 7, count 0 2006.173.15:30:52.86#ibcon#read 3, iclass 7, count 0 2006.173.15:30:52.86#ibcon#about to read 4, iclass 7, count 0 2006.173.15:30:52.86#ibcon#read 4, iclass 7, count 0 2006.173.15:30:52.86#ibcon#about to read 5, iclass 7, count 0 2006.173.15:30:52.86#ibcon#read 5, iclass 7, count 0 2006.173.15:30:52.86#ibcon#about to read 6, iclass 7, count 0 2006.173.15:30:52.86#ibcon#read 6, iclass 7, count 0 2006.173.15:30:52.86#ibcon#end of sib2, iclass 7, count 0 2006.173.15:30:52.86#ibcon#*mode == 0, iclass 7, count 0 2006.173.15:30:52.86#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.15:30:52.86#ibcon#[25=USB\r\n] 2006.173.15:30:52.86#ibcon#*before write, iclass 7, count 0 2006.173.15:30:52.86#ibcon#enter sib2, iclass 7, count 0 2006.173.15:30:52.86#ibcon#flushed, iclass 7, count 0 2006.173.15:30:52.86#ibcon#about to write, iclass 7, count 0 2006.173.15:30:52.86#ibcon#wrote, iclass 7, count 0 2006.173.15:30:52.86#ibcon#about to read 3, iclass 7, count 0 2006.173.15:30:52.89#ibcon#read 3, iclass 7, count 0 2006.173.15:30:52.89#ibcon#about to read 4, iclass 7, count 0 2006.173.15:30:52.89#ibcon#read 4, iclass 7, count 0 2006.173.15:30:52.89#ibcon#about to read 5, iclass 7, count 0 2006.173.15:30:52.89#ibcon#read 5, iclass 7, count 0 2006.173.15:30:52.89#ibcon#about to read 6, iclass 7, count 0 2006.173.15:30:52.89#ibcon#read 6, iclass 7, count 0 2006.173.15:30:52.89#ibcon#end of sib2, iclass 7, count 0 2006.173.15:30:52.89#ibcon#*after write, iclass 7, count 0 2006.173.15:30:52.89#ibcon#*before return 0, iclass 7, count 0 2006.173.15:30:52.89#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.15:30:52.89#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.173.15:30:52.89#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.15:30:52.89#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.15:30:52.89$vck44/valo=6,814.99 2006.173.15:30:52.89#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.15:30:52.89#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.15:30:52.89#ibcon#ireg 17 cls_cnt 0 2006.173.15:30:52.89#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.15:30:52.89#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.15:30:52.89#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.15:30:52.89#ibcon#enter wrdev, iclass 11, count 0 2006.173.15:30:52.89#ibcon#first serial, iclass 11, count 0 2006.173.15:30:52.89#ibcon#enter sib2, iclass 11, count 0 2006.173.15:30:52.89#ibcon#flushed, iclass 11, count 0 2006.173.15:30:52.89#ibcon#about to write, iclass 11, count 0 2006.173.15:30:52.89#ibcon#wrote, iclass 11, count 0 2006.173.15:30:52.89#ibcon#about to read 3, iclass 11, count 0 2006.173.15:30:52.91#ibcon#read 3, iclass 11, count 0 2006.173.15:30:52.91#ibcon#about to read 4, iclass 11, count 0 2006.173.15:30:52.91#ibcon#read 4, iclass 11, count 0 2006.173.15:30:52.91#ibcon#about to read 5, iclass 11, count 0 2006.173.15:30:52.91#ibcon#read 5, iclass 11, count 0 2006.173.15:30:52.91#ibcon#about to read 6, iclass 11, count 0 2006.173.15:30:52.91#ibcon#read 6, iclass 11, count 0 2006.173.15:30:52.91#ibcon#end of sib2, iclass 11, count 0 2006.173.15:30:52.91#ibcon#*mode == 0, iclass 11, count 0 2006.173.15:30:52.91#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.15:30:52.91#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.15:30:52.91#ibcon#*before write, iclass 11, count 0 2006.173.15:30:52.91#ibcon#enter sib2, iclass 11, count 0 2006.173.15:30:52.91#ibcon#flushed, iclass 11, count 0 2006.173.15:30:52.91#ibcon#about to write, iclass 11, count 0 2006.173.15:30:52.91#ibcon#wrote, iclass 11, count 0 2006.173.15:30:52.91#ibcon#about to read 3, iclass 11, count 0 2006.173.15:30:52.95#ibcon#read 3, iclass 11, count 0 2006.173.15:30:52.95#ibcon#about to read 4, iclass 11, count 0 2006.173.15:30:52.95#ibcon#read 4, iclass 11, count 0 2006.173.15:30:52.95#ibcon#about to read 5, iclass 11, count 0 2006.173.15:30:52.95#ibcon#read 5, iclass 11, count 0 2006.173.15:30:52.95#ibcon#about to read 6, iclass 11, count 0 2006.173.15:30:52.95#ibcon#read 6, iclass 11, count 0 2006.173.15:30:52.95#ibcon#end of sib2, iclass 11, count 0 2006.173.15:30:52.95#ibcon#*after write, iclass 11, count 0 2006.173.15:30:52.95#ibcon#*before return 0, iclass 11, count 0 2006.173.15:30:52.95#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.15:30:52.95#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.15:30:52.95#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.15:30:52.95#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.15:30:52.95$vck44/va=6,3 2006.173.15:30:52.95#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.173.15:30:52.95#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.173.15:30:52.95#ibcon#ireg 11 cls_cnt 2 2006.173.15:30:52.95#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.15:30:53.01#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.15:30:53.01#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.15:30:53.01#ibcon#enter wrdev, iclass 13, count 2 2006.173.15:30:53.01#ibcon#first serial, iclass 13, count 2 2006.173.15:30:53.01#ibcon#enter sib2, iclass 13, count 2 2006.173.15:30:53.01#ibcon#flushed, iclass 13, count 2 2006.173.15:30:53.01#ibcon#about to write, iclass 13, count 2 2006.173.15:30:53.01#ibcon#wrote, iclass 13, count 2 2006.173.15:30:53.01#ibcon#about to read 3, iclass 13, count 2 2006.173.15:30:53.03#ibcon#read 3, iclass 13, count 2 2006.173.15:30:53.03#ibcon#about to read 4, iclass 13, count 2 2006.173.15:30:53.03#ibcon#read 4, iclass 13, count 2 2006.173.15:30:53.03#ibcon#about to read 5, iclass 13, count 2 2006.173.15:30:53.03#ibcon#read 5, iclass 13, count 2 2006.173.15:30:53.03#ibcon#about to read 6, iclass 13, count 2 2006.173.15:30:53.03#ibcon#read 6, iclass 13, count 2 2006.173.15:30:53.03#ibcon#end of sib2, iclass 13, count 2 2006.173.15:30:53.03#ibcon#*mode == 0, iclass 13, count 2 2006.173.15:30:53.03#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.173.15:30:53.03#ibcon#[25=AT06-03\r\n] 2006.173.15:30:53.03#ibcon#*before write, iclass 13, count 2 2006.173.15:30:53.03#ibcon#enter sib2, iclass 13, count 2 2006.173.15:30:53.03#ibcon#flushed, iclass 13, count 2 2006.173.15:30:53.03#ibcon#about to write, iclass 13, count 2 2006.173.15:30:53.03#ibcon#wrote, iclass 13, count 2 2006.173.15:30:53.03#ibcon#about to read 3, iclass 13, count 2 2006.173.15:30:53.06#ibcon#read 3, iclass 13, count 2 2006.173.15:30:53.06#ibcon#about to read 4, iclass 13, count 2 2006.173.15:30:53.06#ibcon#read 4, iclass 13, count 2 2006.173.15:30:53.06#ibcon#about to read 5, iclass 13, count 2 2006.173.15:30:53.06#ibcon#read 5, iclass 13, count 2 2006.173.15:30:53.06#ibcon#about to read 6, iclass 13, count 2 2006.173.15:30:53.06#ibcon#read 6, iclass 13, count 2 2006.173.15:30:53.06#ibcon#end of sib2, iclass 13, count 2 2006.173.15:30:53.06#ibcon#*after write, iclass 13, count 2 2006.173.15:30:53.06#ibcon#*before return 0, iclass 13, count 2 2006.173.15:30:53.06#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.15:30:53.06#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.173.15:30:53.06#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.173.15:30:53.06#ibcon#ireg 7 cls_cnt 0 2006.173.15:30:53.06#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.15:30:53.18#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.15:30:53.18#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.15:30:53.18#ibcon#enter wrdev, iclass 13, count 0 2006.173.15:30:53.18#ibcon#first serial, iclass 13, count 0 2006.173.15:30:53.18#ibcon#enter sib2, iclass 13, count 0 2006.173.15:30:53.18#ibcon#flushed, iclass 13, count 0 2006.173.15:30:53.18#ibcon#about to write, iclass 13, count 0 2006.173.15:30:53.18#ibcon#wrote, iclass 13, count 0 2006.173.15:30:53.18#ibcon#about to read 3, iclass 13, count 0 2006.173.15:30:53.20#ibcon#read 3, iclass 13, count 0 2006.173.15:30:53.20#ibcon#about to read 4, iclass 13, count 0 2006.173.15:30:53.20#ibcon#read 4, iclass 13, count 0 2006.173.15:30:53.20#ibcon#about to read 5, iclass 13, count 0 2006.173.15:30:53.20#ibcon#read 5, iclass 13, count 0 2006.173.15:30:53.20#ibcon#about to read 6, iclass 13, count 0 2006.173.15:30:53.20#ibcon#read 6, iclass 13, count 0 2006.173.15:30:53.20#ibcon#end of sib2, iclass 13, count 0 2006.173.15:30:53.20#ibcon#*mode == 0, iclass 13, count 0 2006.173.15:30:53.20#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.15:30:53.20#ibcon#[25=USB\r\n] 2006.173.15:30:53.20#ibcon#*before write, iclass 13, count 0 2006.173.15:30:53.20#ibcon#enter sib2, iclass 13, count 0 2006.173.15:30:53.20#ibcon#flushed, iclass 13, count 0 2006.173.15:30:53.20#ibcon#about to write, iclass 13, count 0 2006.173.15:30:53.20#ibcon#wrote, iclass 13, count 0 2006.173.15:30:53.20#ibcon#about to read 3, iclass 13, count 0 2006.173.15:30:53.23#ibcon#read 3, iclass 13, count 0 2006.173.15:30:53.23#ibcon#about to read 4, iclass 13, count 0 2006.173.15:30:53.23#ibcon#read 4, iclass 13, count 0 2006.173.15:30:53.23#ibcon#about to read 5, iclass 13, count 0 2006.173.15:30:53.23#ibcon#read 5, iclass 13, count 0 2006.173.15:30:53.23#ibcon#about to read 6, iclass 13, count 0 2006.173.15:30:53.23#ibcon#read 6, iclass 13, count 0 2006.173.15:30:53.23#ibcon#end of sib2, iclass 13, count 0 2006.173.15:30:53.23#ibcon#*after write, iclass 13, count 0 2006.173.15:30:53.23#ibcon#*before return 0, iclass 13, count 0 2006.173.15:30:53.23#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.15:30:53.23#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.173.15:30:53.23#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.15:30:53.23#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.15:30:53.23$vck44/valo=7,864.99 2006.173.15:30:53.23#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.15:30:53.23#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.15:30:53.23#ibcon#ireg 17 cls_cnt 0 2006.173.15:30:53.23#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.15:30:53.23#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.15:30:53.23#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.15:30:53.23#ibcon#enter wrdev, iclass 15, count 0 2006.173.15:30:53.23#ibcon#first serial, iclass 15, count 0 2006.173.15:30:53.23#ibcon#enter sib2, iclass 15, count 0 2006.173.15:30:53.23#ibcon#flushed, iclass 15, count 0 2006.173.15:30:53.23#ibcon#about to write, iclass 15, count 0 2006.173.15:30:53.23#ibcon#wrote, iclass 15, count 0 2006.173.15:30:53.23#ibcon#about to read 3, iclass 15, count 0 2006.173.15:30:53.25#ibcon#read 3, iclass 15, count 0 2006.173.15:30:53.25#ibcon#about to read 4, iclass 15, count 0 2006.173.15:30:53.25#ibcon#read 4, iclass 15, count 0 2006.173.15:30:53.25#ibcon#about to read 5, iclass 15, count 0 2006.173.15:30:53.25#ibcon#read 5, iclass 15, count 0 2006.173.15:30:53.25#ibcon#about to read 6, iclass 15, count 0 2006.173.15:30:53.25#ibcon#read 6, iclass 15, count 0 2006.173.15:30:53.25#ibcon#end of sib2, iclass 15, count 0 2006.173.15:30:53.25#ibcon#*mode == 0, iclass 15, count 0 2006.173.15:30:53.25#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.15:30:53.25#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.15:30:53.25#ibcon#*before write, iclass 15, count 0 2006.173.15:30:53.25#ibcon#enter sib2, iclass 15, count 0 2006.173.15:30:53.25#ibcon#flushed, iclass 15, count 0 2006.173.15:30:53.25#ibcon#about to write, iclass 15, count 0 2006.173.15:30:53.25#ibcon#wrote, iclass 15, count 0 2006.173.15:30:53.25#ibcon#about to read 3, iclass 15, count 0 2006.173.15:30:53.29#ibcon#read 3, iclass 15, count 0 2006.173.15:30:53.29#ibcon#about to read 4, iclass 15, count 0 2006.173.15:30:53.29#ibcon#read 4, iclass 15, count 0 2006.173.15:30:53.29#ibcon#about to read 5, iclass 15, count 0 2006.173.15:30:53.29#ibcon#read 5, iclass 15, count 0 2006.173.15:30:53.29#ibcon#about to read 6, iclass 15, count 0 2006.173.15:30:53.29#ibcon#read 6, iclass 15, count 0 2006.173.15:30:53.29#ibcon#end of sib2, iclass 15, count 0 2006.173.15:30:53.29#ibcon#*after write, iclass 15, count 0 2006.173.15:30:53.29#ibcon#*before return 0, iclass 15, count 0 2006.173.15:30:53.29#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.15:30:53.29#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.15:30:53.29#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.15:30:53.29#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.15:30:53.29$vck44/va=7,4 2006.173.15:30:53.29#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.15:30:53.29#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.15:30:53.29#ibcon#ireg 11 cls_cnt 2 2006.173.15:30:53.29#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.15:30:53.35#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.15:30:53.35#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.15:30:53.35#ibcon#enter wrdev, iclass 17, count 2 2006.173.15:30:53.35#ibcon#first serial, iclass 17, count 2 2006.173.15:30:53.35#ibcon#enter sib2, iclass 17, count 2 2006.173.15:30:53.35#ibcon#flushed, iclass 17, count 2 2006.173.15:30:53.35#ibcon#about to write, iclass 17, count 2 2006.173.15:30:53.35#ibcon#wrote, iclass 17, count 2 2006.173.15:30:53.35#ibcon#about to read 3, iclass 17, count 2 2006.173.15:30:53.37#ibcon#read 3, iclass 17, count 2 2006.173.15:30:53.37#ibcon#about to read 4, iclass 17, count 2 2006.173.15:30:53.37#ibcon#read 4, iclass 17, count 2 2006.173.15:30:53.37#ibcon#about to read 5, iclass 17, count 2 2006.173.15:30:53.37#ibcon#read 5, iclass 17, count 2 2006.173.15:30:53.37#ibcon#about to read 6, iclass 17, count 2 2006.173.15:30:53.37#ibcon#read 6, iclass 17, count 2 2006.173.15:30:53.37#ibcon#end of sib2, iclass 17, count 2 2006.173.15:30:53.37#ibcon#*mode == 0, iclass 17, count 2 2006.173.15:30:53.37#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.15:30:53.37#ibcon#[25=AT07-04\r\n] 2006.173.15:30:53.37#ibcon#*before write, iclass 17, count 2 2006.173.15:30:53.37#ibcon#enter sib2, iclass 17, count 2 2006.173.15:30:53.37#ibcon#flushed, iclass 17, count 2 2006.173.15:30:53.37#ibcon#about to write, iclass 17, count 2 2006.173.15:30:53.37#ibcon#wrote, iclass 17, count 2 2006.173.15:30:53.37#ibcon#about to read 3, iclass 17, count 2 2006.173.15:30:53.40#ibcon#read 3, iclass 17, count 2 2006.173.15:30:53.40#ibcon#about to read 4, iclass 17, count 2 2006.173.15:30:53.40#ibcon#read 4, iclass 17, count 2 2006.173.15:30:53.40#ibcon#about to read 5, iclass 17, count 2 2006.173.15:30:53.40#ibcon#read 5, iclass 17, count 2 2006.173.15:30:53.40#ibcon#about to read 6, iclass 17, count 2 2006.173.15:30:53.40#ibcon#read 6, iclass 17, count 2 2006.173.15:30:53.40#ibcon#end of sib2, iclass 17, count 2 2006.173.15:30:53.40#ibcon#*after write, iclass 17, count 2 2006.173.15:30:53.40#ibcon#*before return 0, iclass 17, count 2 2006.173.15:30:53.40#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.15:30:53.40#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.15:30:53.40#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.15:30:53.40#ibcon#ireg 7 cls_cnt 0 2006.173.15:30:53.40#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.15:30:53.52#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.15:30:53.52#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.15:30:53.52#ibcon#enter wrdev, iclass 17, count 0 2006.173.15:30:53.52#ibcon#first serial, iclass 17, count 0 2006.173.15:30:53.52#ibcon#enter sib2, iclass 17, count 0 2006.173.15:30:53.52#ibcon#flushed, iclass 17, count 0 2006.173.15:30:53.52#ibcon#about to write, iclass 17, count 0 2006.173.15:30:53.52#ibcon#wrote, iclass 17, count 0 2006.173.15:30:53.52#ibcon#about to read 3, iclass 17, count 0 2006.173.15:30:53.54#ibcon#read 3, iclass 17, count 0 2006.173.15:30:53.54#ibcon#about to read 4, iclass 17, count 0 2006.173.15:30:53.54#ibcon#read 4, iclass 17, count 0 2006.173.15:30:53.54#ibcon#about to read 5, iclass 17, count 0 2006.173.15:30:53.54#ibcon#read 5, iclass 17, count 0 2006.173.15:30:53.54#ibcon#about to read 6, iclass 17, count 0 2006.173.15:30:53.54#ibcon#read 6, iclass 17, count 0 2006.173.15:30:53.54#ibcon#end of sib2, iclass 17, count 0 2006.173.15:30:53.54#ibcon#*mode == 0, iclass 17, count 0 2006.173.15:30:53.54#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.15:30:53.54#ibcon#[25=USB\r\n] 2006.173.15:30:53.54#ibcon#*before write, iclass 17, count 0 2006.173.15:30:53.54#ibcon#enter sib2, iclass 17, count 0 2006.173.15:30:53.54#ibcon#flushed, iclass 17, count 0 2006.173.15:30:53.54#ibcon#about to write, iclass 17, count 0 2006.173.15:30:53.54#ibcon#wrote, iclass 17, count 0 2006.173.15:30:53.54#ibcon#about to read 3, iclass 17, count 0 2006.173.15:30:53.57#ibcon#read 3, iclass 17, count 0 2006.173.15:30:53.57#ibcon#about to read 4, iclass 17, count 0 2006.173.15:30:53.57#ibcon#read 4, iclass 17, count 0 2006.173.15:30:53.57#ibcon#about to read 5, iclass 17, count 0 2006.173.15:30:53.57#ibcon#read 5, iclass 17, count 0 2006.173.15:30:53.57#ibcon#about to read 6, iclass 17, count 0 2006.173.15:30:53.57#ibcon#read 6, iclass 17, count 0 2006.173.15:30:53.57#ibcon#end of sib2, iclass 17, count 0 2006.173.15:30:53.57#ibcon#*after write, iclass 17, count 0 2006.173.15:30:53.57#ibcon#*before return 0, iclass 17, count 0 2006.173.15:30:53.57#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.15:30:53.57#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.15:30:53.57#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.15:30:53.57#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.15:30:53.57$vck44/valo=8,884.99 2006.173.15:30:53.57#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.15:30:53.57#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.15:30:53.57#ibcon#ireg 17 cls_cnt 0 2006.173.15:30:53.57#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.15:30:53.57#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.15:30:53.57#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.15:30:53.57#ibcon#enter wrdev, iclass 19, count 0 2006.173.15:30:53.57#ibcon#first serial, iclass 19, count 0 2006.173.15:30:53.57#ibcon#enter sib2, iclass 19, count 0 2006.173.15:30:53.57#ibcon#flushed, iclass 19, count 0 2006.173.15:30:53.57#ibcon#about to write, iclass 19, count 0 2006.173.15:30:53.57#ibcon#wrote, iclass 19, count 0 2006.173.15:30:53.57#ibcon#about to read 3, iclass 19, count 0 2006.173.15:30:53.59#ibcon#read 3, iclass 19, count 0 2006.173.15:30:53.59#ibcon#about to read 4, iclass 19, count 0 2006.173.15:30:53.59#ibcon#read 4, iclass 19, count 0 2006.173.15:30:53.59#ibcon#about to read 5, iclass 19, count 0 2006.173.15:30:53.59#ibcon#read 5, iclass 19, count 0 2006.173.15:30:53.59#ibcon#about to read 6, iclass 19, count 0 2006.173.15:30:53.59#ibcon#read 6, iclass 19, count 0 2006.173.15:30:53.59#ibcon#end of sib2, iclass 19, count 0 2006.173.15:30:53.59#ibcon#*mode == 0, iclass 19, count 0 2006.173.15:30:53.59#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.15:30:53.59#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.15:30:53.59#ibcon#*before write, iclass 19, count 0 2006.173.15:30:53.59#ibcon#enter sib2, iclass 19, count 0 2006.173.15:30:53.59#ibcon#flushed, iclass 19, count 0 2006.173.15:30:53.59#ibcon#about to write, iclass 19, count 0 2006.173.15:30:53.59#ibcon#wrote, iclass 19, count 0 2006.173.15:30:53.59#ibcon#about to read 3, iclass 19, count 0 2006.173.15:30:53.63#ibcon#read 3, iclass 19, count 0 2006.173.15:30:53.63#ibcon#about to read 4, iclass 19, count 0 2006.173.15:30:53.63#ibcon#read 4, iclass 19, count 0 2006.173.15:30:53.63#ibcon#about to read 5, iclass 19, count 0 2006.173.15:30:53.63#ibcon#read 5, iclass 19, count 0 2006.173.15:30:53.63#ibcon#about to read 6, iclass 19, count 0 2006.173.15:30:53.63#ibcon#read 6, iclass 19, count 0 2006.173.15:30:53.63#ibcon#end of sib2, iclass 19, count 0 2006.173.15:30:53.63#ibcon#*after write, iclass 19, count 0 2006.173.15:30:53.63#ibcon#*before return 0, iclass 19, count 0 2006.173.15:30:53.63#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.15:30:53.63#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.15:30:53.63#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.15:30:53.63#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.15:30:53.63$vck44/va=8,4 2006.173.15:30:53.63#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.15:30:53.63#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.15:30:53.63#ibcon#ireg 11 cls_cnt 2 2006.173.15:30:53.63#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.15:30:53.69#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.15:30:53.69#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.15:30:53.69#ibcon#enter wrdev, iclass 21, count 2 2006.173.15:30:53.69#ibcon#first serial, iclass 21, count 2 2006.173.15:30:53.69#ibcon#enter sib2, iclass 21, count 2 2006.173.15:30:53.69#ibcon#flushed, iclass 21, count 2 2006.173.15:30:53.69#ibcon#about to write, iclass 21, count 2 2006.173.15:30:53.69#ibcon#wrote, iclass 21, count 2 2006.173.15:30:53.69#ibcon#about to read 3, iclass 21, count 2 2006.173.15:30:53.71#ibcon#read 3, iclass 21, count 2 2006.173.15:30:53.71#ibcon#about to read 4, iclass 21, count 2 2006.173.15:30:53.71#ibcon#read 4, iclass 21, count 2 2006.173.15:30:53.71#ibcon#about to read 5, iclass 21, count 2 2006.173.15:30:53.71#ibcon#read 5, iclass 21, count 2 2006.173.15:30:53.71#ibcon#about to read 6, iclass 21, count 2 2006.173.15:30:53.71#ibcon#read 6, iclass 21, count 2 2006.173.15:30:53.71#ibcon#end of sib2, iclass 21, count 2 2006.173.15:30:53.71#ibcon#*mode == 0, iclass 21, count 2 2006.173.15:30:53.71#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.15:30:53.71#ibcon#[25=AT08-04\r\n] 2006.173.15:30:53.71#ibcon#*before write, iclass 21, count 2 2006.173.15:30:53.71#ibcon#enter sib2, iclass 21, count 2 2006.173.15:30:53.71#ibcon#flushed, iclass 21, count 2 2006.173.15:30:53.71#ibcon#about to write, iclass 21, count 2 2006.173.15:30:53.71#ibcon#wrote, iclass 21, count 2 2006.173.15:30:53.71#ibcon#about to read 3, iclass 21, count 2 2006.173.15:30:53.74#ibcon#read 3, iclass 21, count 2 2006.173.15:30:53.74#ibcon#about to read 4, iclass 21, count 2 2006.173.15:30:53.74#ibcon#read 4, iclass 21, count 2 2006.173.15:30:53.74#ibcon#about to read 5, iclass 21, count 2 2006.173.15:30:53.74#ibcon#read 5, iclass 21, count 2 2006.173.15:30:53.74#ibcon#about to read 6, iclass 21, count 2 2006.173.15:30:53.74#ibcon#read 6, iclass 21, count 2 2006.173.15:30:53.74#ibcon#end of sib2, iclass 21, count 2 2006.173.15:30:53.74#ibcon#*after write, iclass 21, count 2 2006.173.15:30:53.74#ibcon#*before return 0, iclass 21, count 2 2006.173.15:30:53.74#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.15:30:53.74#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.15:30:53.74#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.15:30:53.74#ibcon#ireg 7 cls_cnt 0 2006.173.15:30:53.74#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.15:30:53.86#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.15:30:53.86#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.15:30:53.86#ibcon#enter wrdev, iclass 21, count 0 2006.173.15:30:53.86#ibcon#first serial, iclass 21, count 0 2006.173.15:30:53.86#ibcon#enter sib2, iclass 21, count 0 2006.173.15:30:53.86#ibcon#flushed, iclass 21, count 0 2006.173.15:30:53.86#ibcon#about to write, iclass 21, count 0 2006.173.15:30:53.86#ibcon#wrote, iclass 21, count 0 2006.173.15:30:53.86#ibcon#about to read 3, iclass 21, count 0 2006.173.15:30:53.88#ibcon#read 3, iclass 21, count 0 2006.173.15:30:53.88#ibcon#about to read 4, iclass 21, count 0 2006.173.15:30:53.88#ibcon#read 4, iclass 21, count 0 2006.173.15:30:53.88#ibcon#about to read 5, iclass 21, count 0 2006.173.15:30:53.88#ibcon#read 5, iclass 21, count 0 2006.173.15:30:53.88#ibcon#about to read 6, iclass 21, count 0 2006.173.15:30:53.88#ibcon#read 6, iclass 21, count 0 2006.173.15:30:53.88#ibcon#end of sib2, iclass 21, count 0 2006.173.15:30:53.88#ibcon#*mode == 0, iclass 21, count 0 2006.173.15:30:53.88#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.15:30:53.88#ibcon#[25=USB\r\n] 2006.173.15:30:53.88#ibcon#*before write, iclass 21, count 0 2006.173.15:30:53.88#ibcon#enter sib2, iclass 21, count 0 2006.173.15:30:53.88#ibcon#flushed, iclass 21, count 0 2006.173.15:30:53.88#ibcon#about to write, iclass 21, count 0 2006.173.15:30:53.88#ibcon#wrote, iclass 21, count 0 2006.173.15:30:53.88#ibcon#about to read 3, iclass 21, count 0 2006.173.15:30:53.91#ibcon#read 3, iclass 21, count 0 2006.173.15:30:53.91#ibcon#about to read 4, iclass 21, count 0 2006.173.15:30:53.91#ibcon#read 4, iclass 21, count 0 2006.173.15:30:53.91#ibcon#about to read 5, iclass 21, count 0 2006.173.15:30:53.91#ibcon#read 5, iclass 21, count 0 2006.173.15:30:53.91#ibcon#about to read 6, iclass 21, count 0 2006.173.15:30:53.91#ibcon#read 6, iclass 21, count 0 2006.173.15:30:53.91#ibcon#end of sib2, iclass 21, count 0 2006.173.15:30:53.91#ibcon#*after write, iclass 21, count 0 2006.173.15:30:53.91#ibcon#*before return 0, iclass 21, count 0 2006.173.15:30:53.91#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.15:30:53.91#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.15:30:53.91#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.15:30:53.91#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.15:30:53.91$vck44/vblo=1,629.99 2006.173.15:30:53.91#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.15:30:53.91#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.15:30:53.91#ibcon#ireg 17 cls_cnt 0 2006.173.15:30:53.91#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.15:30:53.91#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.15:30:53.91#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.15:30:53.91#ibcon#enter wrdev, iclass 23, count 0 2006.173.15:30:53.91#ibcon#first serial, iclass 23, count 0 2006.173.15:30:53.91#ibcon#enter sib2, iclass 23, count 0 2006.173.15:30:53.91#ibcon#flushed, iclass 23, count 0 2006.173.15:30:53.91#ibcon#about to write, iclass 23, count 0 2006.173.15:30:53.91#ibcon#wrote, iclass 23, count 0 2006.173.15:30:53.91#ibcon#about to read 3, iclass 23, count 0 2006.173.15:30:53.93#ibcon#read 3, iclass 23, count 0 2006.173.15:30:53.93#ibcon#about to read 4, iclass 23, count 0 2006.173.15:30:53.93#ibcon#read 4, iclass 23, count 0 2006.173.15:30:53.93#ibcon#about to read 5, iclass 23, count 0 2006.173.15:30:53.93#ibcon#read 5, iclass 23, count 0 2006.173.15:30:53.93#ibcon#about to read 6, iclass 23, count 0 2006.173.15:30:53.93#ibcon#read 6, iclass 23, count 0 2006.173.15:30:53.93#ibcon#end of sib2, iclass 23, count 0 2006.173.15:30:53.93#ibcon#*mode == 0, iclass 23, count 0 2006.173.15:30:53.93#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.15:30:53.93#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.15:30:53.93#ibcon#*before write, iclass 23, count 0 2006.173.15:30:53.93#ibcon#enter sib2, iclass 23, count 0 2006.173.15:30:53.93#ibcon#flushed, iclass 23, count 0 2006.173.15:30:53.93#ibcon#about to write, iclass 23, count 0 2006.173.15:30:53.93#ibcon#wrote, iclass 23, count 0 2006.173.15:30:53.93#ibcon#about to read 3, iclass 23, count 0 2006.173.15:30:53.97#ibcon#read 3, iclass 23, count 0 2006.173.15:30:53.97#ibcon#about to read 4, iclass 23, count 0 2006.173.15:30:53.97#ibcon#read 4, iclass 23, count 0 2006.173.15:30:53.97#ibcon#about to read 5, iclass 23, count 0 2006.173.15:30:53.97#ibcon#read 5, iclass 23, count 0 2006.173.15:30:53.97#ibcon#about to read 6, iclass 23, count 0 2006.173.15:30:53.97#ibcon#read 6, iclass 23, count 0 2006.173.15:30:53.97#ibcon#end of sib2, iclass 23, count 0 2006.173.15:30:53.97#ibcon#*after write, iclass 23, count 0 2006.173.15:30:53.97#ibcon#*before return 0, iclass 23, count 0 2006.173.15:30:53.97#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.15:30:53.97#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.15:30:53.97#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.15:30:53.97#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.15:30:53.97$vck44/vb=1,4 2006.173.15:30:53.97#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.15:30:53.97#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.15:30:53.97#ibcon#ireg 11 cls_cnt 2 2006.173.15:30:53.97#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.15:30:53.97#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.15:30:53.97#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.15:30:53.97#ibcon#enter wrdev, iclass 25, count 2 2006.173.15:30:53.97#ibcon#first serial, iclass 25, count 2 2006.173.15:30:53.97#ibcon#enter sib2, iclass 25, count 2 2006.173.15:30:53.97#ibcon#flushed, iclass 25, count 2 2006.173.15:30:53.97#ibcon#about to write, iclass 25, count 2 2006.173.15:30:53.97#ibcon#wrote, iclass 25, count 2 2006.173.15:30:53.97#ibcon#about to read 3, iclass 25, count 2 2006.173.15:30:53.99#ibcon#read 3, iclass 25, count 2 2006.173.15:30:53.99#ibcon#about to read 4, iclass 25, count 2 2006.173.15:30:53.99#ibcon#read 4, iclass 25, count 2 2006.173.15:30:53.99#ibcon#about to read 5, iclass 25, count 2 2006.173.15:30:53.99#ibcon#read 5, iclass 25, count 2 2006.173.15:30:53.99#ibcon#about to read 6, iclass 25, count 2 2006.173.15:30:53.99#ibcon#read 6, iclass 25, count 2 2006.173.15:30:53.99#ibcon#end of sib2, iclass 25, count 2 2006.173.15:30:53.99#ibcon#*mode == 0, iclass 25, count 2 2006.173.15:30:53.99#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.15:30:53.99#ibcon#[27=AT01-04\r\n] 2006.173.15:30:53.99#ibcon#*before write, iclass 25, count 2 2006.173.15:30:53.99#ibcon#enter sib2, iclass 25, count 2 2006.173.15:30:53.99#ibcon#flushed, iclass 25, count 2 2006.173.15:30:53.99#ibcon#about to write, iclass 25, count 2 2006.173.15:30:53.99#ibcon#wrote, iclass 25, count 2 2006.173.15:30:53.99#ibcon#about to read 3, iclass 25, count 2 2006.173.15:30:54.02#ibcon#read 3, iclass 25, count 2 2006.173.15:30:54.02#ibcon#about to read 4, iclass 25, count 2 2006.173.15:30:54.02#ibcon#read 4, iclass 25, count 2 2006.173.15:30:54.02#ibcon#about to read 5, iclass 25, count 2 2006.173.15:30:54.02#ibcon#read 5, iclass 25, count 2 2006.173.15:30:54.02#ibcon#about to read 6, iclass 25, count 2 2006.173.15:30:54.02#ibcon#read 6, iclass 25, count 2 2006.173.15:30:54.02#ibcon#end of sib2, iclass 25, count 2 2006.173.15:30:54.02#ibcon#*after write, iclass 25, count 2 2006.173.15:30:54.02#ibcon#*before return 0, iclass 25, count 2 2006.173.15:30:54.02#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.15:30:54.02#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.15:30:54.02#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.15:30:54.02#ibcon#ireg 7 cls_cnt 0 2006.173.15:30:54.02#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.15:30:54.14#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.15:30:54.14#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.15:30:54.14#ibcon#enter wrdev, iclass 25, count 0 2006.173.15:30:54.14#ibcon#first serial, iclass 25, count 0 2006.173.15:30:54.14#ibcon#enter sib2, iclass 25, count 0 2006.173.15:30:54.14#ibcon#flushed, iclass 25, count 0 2006.173.15:30:54.14#ibcon#about to write, iclass 25, count 0 2006.173.15:30:54.14#ibcon#wrote, iclass 25, count 0 2006.173.15:30:54.14#ibcon#about to read 3, iclass 25, count 0 2006.173.15:30:54.16#ibcon#read 3, iclass 25, count 0 2006.173.15:30:54.16#ibcon#about to read 4, iclass 25, count 0 2006.173.15:30:54.16#ibcon#read 4, iclass 25, count 0 2006.173.15:30:54.16#ibcon#about to read 5, iclass 25, count 0 2006.173.15:30:54.16#ibcon#read 5, iclass 25, count 0 2006.173.15:30:54.16#ibcon#about to read 6, iclass 25, count 0 2006.173.15:30:54.16#ibcon#read 6, iclass 25, count 0 2006.173.15:30:54.16#ibcon#end of sib2, iclass 25, count 0 2006.173.15:30:54.16#ibcon#*mode == 0, iclass 25, count 0 2006.173.15:30:54.16#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.15:30:54.16#ibcon#[27=USB\r\n] 2006.173.15:30:54.16#ibcon#*before write, iclass 25, count 0 2006.173.15:30:54.16#ibcon#enter sib2, iclass 25, count 0 2006.173.15:30:54.16#ibcon#flushed, iclass 25, count 0 2006.173.15:30:54.16#ibcon#about to write, iclass 25, count 0 2006.173.15:30:54.16#ibcon#wrote, iclass 25, count 0 2006.173.15:30:54.16#ibcon#about to read 3, iclass 25, count 0 2006.173.15:30:54.19#ibcon#read 3, iclass 25, count 0 2006.173.15:30:54.19#ibcon#about to read 4, iclass 25, count 0 2006.173.15:30:54.19#ibcon#read 4, iclass 25, count 0 2006.173.15:30:54.19#ibcon#about to read 5, iclass 25, count 0 2006.173.15:30:54.19#ibcon#read 5, iclass 25, count 0 2006.173.15:30:54.19#ibcon#about to read 6, iclass 25, count 0 2006.173.15:30:54.19#ibcon#read 6, iclass 25, count 0 2006.173.15:30:54.19#ibcon#end of sib2, iclass 25, count 0 2006.173.15:30:54.19#ibcon#*after write, iclass 25, count 0 2006.173.15:30:54.19#ibcon#*before return 0, iclass 25, count 0 2006.173.15:30:54.19#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.15:30:54.19#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.15:30:54.19#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.15:30:54.19#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.15:30:54.19$vck44/vblo=2,634.99 2006.173.15:30:54.19#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.15:30:54.19#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.15:30:54.19#ibcon#ireg 17 cls_cnt 0 2006.173.15:30:54.19#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.15:30:54.19#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.15:30:54.19#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.15:30:54.19#ibcon#enter wrdev, iclass 27, count 0 2006.173.15:30:54.19#ibcon#first serial, iclass 27, count 0 2006.173.15:30:54.19#ibcon#enter sib2, iclass 27, count 0 2006.173.15:30:54.19#ibcon#flushed, iclass 27, count 0 2006.173.15:30:54.19#ibcon#about to write, iclass 27, count 0 2006.173.15:30:54.19#ibcon#wrote, iclass 27, count 0 2006.173.15:30:54.19#ibcon#about to read 3, iclass 27, count 0 2006.173.15:30:54.21#ibcon#read 3, iclass 27, count 0 2006.173.15:30:54.21#ibcon#about to read 4, iclass 27, count 0 2006.173.15:30:54.21#ibcon#read 4, iclass 27, count 0 2006.173.15:30:54.21#ibcon#about to read 5, iclass 27, count 0 2006.173.15:30:54.21#ibcon#read 5, iclass 27, count 0 2006.173.15:30:54.21#ibcon#about to read 6, iclass 27, count 0 2006.173.15:30:54.21#ibcon#read 6, iclass 27, count 0 2006.173.15:30:54.21#ibcon#end of sib2, iclass 27, count 0 2006.173.15:30:54.21#ibcon#*mode == 0, iclass 27, count 0 2006.173.15:30:54.21#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.15:30:54.21#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.15:30:54.21#ibcon#*before write, iclass 27, count 0 2006.173.15:30:54.21#ibcon#enter sib2, iclass 27, count 0 2006.173.15:30:54.21#ibcon#flushed, iclass 27, count 0 2006.173.15:30:54.21#ibcon#about to write, iclass 27, count 0 2006.173.15:30:54.21#ibcon#wrote, iclass 27, count 0 2006.173.15:30:54.21#ibcon#about to read 3, iclass 27, count 0 2006.173.15:30:54.25#ibcon#read 3, iclass 27, count 0 2006.173.15:30:54.25#ibcon#about to read 4, iclass 27, count 0 2006.173.15:30:54.25#ibcon#read 4, iclass 27, count 0 2006.173.15:30:54.25#ibcon#about to read 5, iclass 27, count 0 2006.173.15:30:54.25#ibcon#read 5, iclass 27, count 0 2006.173.15:30:54.25#ibcon#about to read 6, iclass 27, count 0 2006.173.15:30:54.25#ibcon#read 6, iclass 27, count 0 2006.173.15:30:54.25#ibcon#end of sib2, iclass 27, count 0 2006.173.15:30:54.25#ibcon#*after write, iclass 27, count 0 2006.173.15:30:54.25#ibcon#*before return 0, iclass 27, count 0 2006.173.15:30:54.25#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.15:30:54.25#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.15:30:54.25#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.15:30:54.25#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.15:30:54.25$vck44/vb=2,4 2006.173.15:30:54.25#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.15:30:54.25#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.15:30:54.25#ibcon#ireg 11 cls_cnt 2 2006.173.15:30:54.25#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.15:30:54.31#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.15:30:54.31#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.15:30:54.31#ibcon#enter wrdev, iclass 29, count 2 2006.173.15:30:54.31#ibcon#first serial, iclass 29, count 2 2006.173.15:30:54.31#ibcon#enter sib2, iclass 29, count 2 2006.173.15:30:54.31#ibcon#flushed, iclass 29, count 2 2006.173.15:30:54.31#ibcon#about to write, iclass 29, count 2 2006.173.15:30:54.31#ibcon#wrote, iclass 29, count 2 2006.173.15:30:54.31#ibcon#about to read 3, iclass 29, count 2 2006.173.15:30:54.33#ibcon#read 3, iclass 29, count 2 2006.173.15:30:54.33#ibcon#about to read 4, iclass 29, count 2 2006.173.15:30:54.33#ibcon#read 4, iclass 29, count 2 2006.173.15:30:54.33#ibcon#about to read 5, iclass 29, count 2 2006.173.15:30:54.33#ibcon#read 5, iclass 29, count 2 2006.173.15:30:54.33#ibcon#about to read 6, iclass 29, count 2 2006.173.15:30:54.33#ibcon#read 6, iclass 29, count 2 2006.173.15:30:54.33#ibcon#end of sib2, iclass 29, count 2 2006.173.15:30:54.33#ibcon#*mode == 0, iclass 29, count 2 2006.173.15:30:54.33#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.15:30:54.33#ibcon#[27=AT02-04\r\n] 2006.173.15:30:54.33#ibcon#*before write, iclass 29, count 2 2006.173.15:30:54.33#ibcon#enter sib2, iclass 29, count 2 2006.173.15:30:54.33#ibcon#flushed, iclass 29, count 2 2006.173.15:30:54.33#ibcon#about to write, iclass 29, count 2 2006.173.15:30:54.33#ibcon#wrote, iclass 29, count 2 2006.173.15:30:54.33#ibcon#about to read 3, iclass 29, count 2 2006.173.15:30:54.36#ibcon#read 3, iclass 29, count 2 2006.173.15:30:54.36#ibcon#about to read 4, iclass 29, count 2 2006.173.15:30:54.36#ibcon#read 4, iclass 29, count 2 2006.173.15:30:54.36#ibcon#about to read 5, iclass 29, count 2 2006.173.15:30:54.36#ibcon#read 5, iclass 29, count 2 2006.173.15:30:54.36#ibcon#about to read 6, iclass 29, count 2 2006.173.15:30:54.36#ibcon#read 6, iclass 29, count 2 2006.173.15:30:54.36#ibcon#end of sib2, iclass 29, count 2 2006.173.15:30:54.36#ibcon#*after write, iclass 29, count 2 2006.173.15:30:54.36#ibcon#*before return 0, iclass 29, count 2 2006.173.15:30:54.36#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.15:30:54.36#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.15:30:54.36#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.15:30:54.36#ibcon#ireg 7 cls_cnt 0 2006.173.15:30:54.36#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.15:30:54.48#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.15:30:54.48#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.15:30:54.48#ibcon#enter wrdev, iclass 29, count 0 2006.173.15:30:54.48#ibcon#first serial, iclass 29, count 0 2006.173.15:30:54.48#ibcon#enter sib2, iclass 29, count 0 2006.173.15:30:54.48#ibcon#flushed, iclass 29, count 0 2006.173.15:30:54.48#ibcon#about to write, iclass 29, count 0 2006.173.15:30:54.48#ibcon#wrote, iclass 29, count 0 2006.173.15:30:54.48#ibcon#about to read 3, iclass 29, count 0 2006.173.15:30:54.50#ibcon#read 3, iclass 29, count 0 2006.173.15:30:54.50#ibcon#about to read 4, iclass 29, count 0 2006.173.15:30:54.50#ibcon#read 4, iclass 29, count 0 2006.173.15:30:54.50#ibcon#about to read 5, iclass 29, count 0 2006.173.15:30:54.50#ibcon#read 5, iclass 29, count 0 2006.173.15:30:54.50#ibcon#about to read 6, iclass 29, count 0 2006.173.15:30:54.50#ibcon#read 6, iclass 29, count 0 2006.173.15:30:54.50#ibcon#end of sib2, iclass 29, count 0 2006.173.15:30:54.50#ibcon#*mode == 0, iclass 29, count 0 2006.173.15:30:54.50#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.15:30:54.50#ibcon#[27=USB\r\n] 2006.173.15:30:54.50#ibcon#*before write, iclass 29, count 0 2006.173.15:30:54.50#ibcon#enter sib2, iclass 29, count 0 2006.173.15:30:54.50#ibcon#flushed, iclass 29, count 0 2006.173.15:30:54.50#ibcon#about to write, iclass 29, count 0 2006.173.15:30:54.50#ibcon#wrote, iclass 29, count 0 2006.173.15:30:54.50#ibcon#about to read 3, iclass 29, count 0 2006.173.15:30:54.53#ibcon#read 3, iclass 29, count 0 2006.173.15:30:54.53#ibcon#about to read 4, iclass 29, count 0 2006.173.15:30:54.53#ibcon#read 4, iclass 29, count 0 2006.173.15:30:54.53#ibcon#about to read 5, iclass 29, count 0 2006.173.15:30:54.53#ibcon#read 5, iclass 29, count 0 2006.173.15:30:54.53#ibcon#about to read 6, iclass 29, count 0 2006.173.15:30:54.53#ibcon#read 6, iclass 29, count 0 2006.173.15:30:54.53#ibcon#end of sib2, iclass 29, count 0 2006.173.15:30:54.53#ibcon#*after write, iclass 29, count 0 2006.173.15:30:54.53#ibcon#*before return 0, iclass 29, count 0 2006.173.15:30:54.53#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.15:30:54.53#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.15:30:54.53#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.15:30:54.53#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.15:30:54.53$vck44/vblo=3,649.99 2006.173.15:30:54.53#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.15:30:54.53#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.15:30:54.53#ibcon#ireg 17 cls_cnt 0 2006.173.15:30:54.53#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.15:30:54.53#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.15:30:54.53#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.15:30:54.53#ibcon#enter wrdev, iclass 31, count 0 2006.173.15:30:54.53#ibcon#first serial, iclass 31, count 0 2006.173.15:30:54.53#ibcon#enter sib2, iclass 31, count 0 2006.173.15:30:54.53#ibcon#flushed, iclass 31, count 0 2006.173.15:30:54.53#ibcon#about to write, iclass 31, count 0 2006.173.15:30:54.53#ibcon#wrote, iclass 31, count 0 2006.173.15:30:54.53#ibcon#about to read 3, iclass 31, count 0 2006.173.15:30:54.55#ibcon#read 3, iclass 31, count 0 2006.173.15:30:54.55#ibcon#about to read 4, iclass 31, count 0 2006.173.15:30:54.55#ibcon#read 4, iclass 31, count 0 2006.173.15:30:54.55#ibcon#about to read 5, iclass 31, count 0 2006.173.15:30:54.55#ibcon#read 5, iclass 31, count 0 2006.173.15:30:54.55#ibcon#about to read 6, iclass 31, count 0 2006.173.15:30:54.55#ibcon#read 6, iclass 31, count 0 2006.173.15:30:54.55#ibcon#end of sib2, iclass 31, count 0 2006.173.15:30:54.55#ibcon#*mode == 0, iclass 31, count 0 2006.173.15:30:54.55#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.15:30:54.55#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.15:30:54.55#ibcon#*before write, iclass 31, count 0 2006.173.15:30:54.55#ibcon#enter sib2, iclass 31, count 0 2006.173.15:30:54.55#ibcon#flushed, iclass 31, count 0 2006.173.15:30:54.55#ibcon#about to write, iclass 31, count 0 2006.173.15:30:54.55#ibcon#wrote, iclass 31, count 0 2006.173.15:30:54.55#ibcon#about to read 3, iclass 31, count 0 2006.173.15:30:54.59#ibcon#read 3, iclass 31, count 0 2006.173.15:30:54.59#ibcon#about to read 4, iclass 31, count 0 2006.173.15:30:54.59#ibcon#read 4, iclass 31, count 0 2006.173.15:30:54.59#ibcon#about to read 5, iclass 31, count 0 2006.173.15:30:54.59#ibcon#read 5, iclass 31, count 0 2006.173.15:30:54.59#ibcon#about to read 6, iclass 31, count 0 2006.173.15:30:54.59#ibcon#read 6, iclass 31, count 0 2006.173.15:30:54.59#ibcon#end of sib2, iclass 31, count 0 2006.173.15:30:54.59#ibcon#*after write, iclass 31, count 0 2006.173.15:30:54.59#ibcon#*before return 0, iclass 31, count 0 2006.173.15:30:54.59#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.15:30:54.59#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.15:30:54.59#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.15:30:54.59#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.15:30:54.59$vck44/vb=3,4 2006.173.15:30:54.59#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.173.15:30:54.59#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.173.15:30:54.59#ibcon#ireg 11 cls_cnt 2 2006.173.15:30:54.59#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.15:30:54.65#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.15:30:54.65#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.15:30:54.65#ibcon#enter wrdev, iclass 33, count 2 2006.173.15:30:54.65#ibcon#first serial, iclass 33, count 2 2006.173.15:30:54.65#ibcon#enter sib2, iclass 33, count 2 2006.173.15:30:54.65#ibcon#flushed, iclass 33, count 2 2006.173.15:30:54.65#ibcon#about to write, iclass 33, count 2 2006.173.15:30:54.65#ibcon#wrote, iclass 33, count 2 2006.173.15:30:54.65#ibcon#about to read 3, iclass 33, count 2 2006.173.15:30:54.67#ibcon#read 3, iclass 33, count 2 2006.173.15:30:54.67#ibcon#about to read 4, iclass 33, count 2 2006.173.15:30:54.67#ibcon#read 4, iclass 33, count 2 2006.173.15:30:54.67#ibcon#about to read 5, iclass 33, count 2 2006.173.15:30:54.67#ibcon#read 5, iclass 33, count 2 2006.173.15:30:54.67#ibcon#about to read 6, iclass 33, count 2 2006.173.15:30:54.67#ibcon#read 6, iclass 33, count 2 2006.173.15:30:54.67#ibcon#end of sib2, iclass 33, count 2 2006.173.15:30:54.67#ibcon#*mode == 0, iclass 33, count 2 2006.173.15:30:54.67#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.173.15:30:54.67#ibcon#[27=AT03-04\r\n] 2006.173.15:30:54.67#ibcon#*before write, iclass 33, count 2 2006.173.15:30:54.67#ibcon#enter sib2, iclass 33, count 2 2006.173.15:30:54.67#ibcon#flushed, iclass 33, count 2 2006.173.15:30:54.67#ibcon#about to write, iclass 33, count 2 2006.173.15:30:54.67#ibcon#wrote, iclass 33, count 2 2006.173.15:30:54.67#ibcon#about to read 3, iclass 33, count 2 2006.173.15:30:54.70#ibcon#read 3, iclass 33, count 2 2006.173.15:30:54.70#ibcon#about to read 4, iclass 33, count 2 2006.173.15:30:54.70#ibcon#read 4, iclass 33, count 2 2006.173.15:30:54.70#ibcon#about to read 5, iclass 33, count 2 2006.173.15:30:54.70#ibcon#read 5, iclass 33, count 2 2006.173.15:30:54.70#ibcon#about to read 6, iclass 33, count 2 2006.173.15:30:54.70#ibcon#read 6, iclass 33, count 2 2006.173.15:30:54.70#ibcon#end of sib2, iclass 33, count 2 2006.173.15:30:54.70#ibcon#*after write, iclass 33, count 2 2006.173.15:30:54.70#ibcon#*before return 0, iclass 33, count 2 2006.173.15:30:54.70#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.15:30:54.70#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.173.15:30:54.70#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.173.15:30:54.70#ibcon#ireg 7 cls_cnt 0 2006.173.15:30:54.70#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.15:30:54.82#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.15:30:54.82#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.15:30:54.82#ibcon#enter wrdev, iclass 33, count 0 2006.173.15:30:54.82#ibcon#first serial, iclass 33, count 0 2006.173.15:30:54.82#ibcon#enter sib2, iclass 33, count 0 2006.173.15:30:54.82#ibcon#flushed, iclass 33, count 0 2006.173.15:30:54.82#ibcon#about to write, iclass 33, count 0 2006.173.15:30:54.82#ibcon#wrote, iclass 33, count 0 2006.173.15:30:54.82#ibcon#about to read 3, iclass 33, count 0 2006.173.15:30:54.84#ibcon#read 3, iclass 33, count 0 2006.173.15:30:54.84#ibcon#about to read 4, iclass 33, count 0 2006.173.15:30:54.84#ibcon#read 4, iclass 33, count 0 2006.173.15:30:54.84#ibcon#about to read 5, iclass 33, count 0 2006.173.15:30:54.84#ibcon#read 5, iclass 33, count 0 2006.173.15:30:54.84#ibcon#about to read 6, iclass 33, count 0 2006.173.15:30:54.84#ibcon#read 6, iclass 33, count 0 2006.173.15:30:54.84#ibcon#end of sib2, iclass 33, count 0 2006.173.15:30:54.84#ibcon#*mode == 0, iclass 33, count 0 2006.173.15:30:54.84#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.15:30:54.84#ibcon#[27=USB\r\n] 2006.173.15:30:54.84#ibcon#*before write, iclass 33, count 0 2006.173.15:30:54.84#ibcon#enter sib2, iclass 33, count 0 2006.173.15:30:54.84#ibcon#flushed, iclass 33, count 0 2006.173.15:30:54.84#ibcon#about to write, iclass 33, count 0 2006.173.15:30:54.84#ibcon#wrote, iclass 33, count 0 2006.173.15:30:54.84#ibcon#about to read 3, iclass 33, count 0 2006.173.15:30:54.87#ibcon#read 3, iclass 33, count 0 2006.173.15:30:54.87#ibcon#about to read 4, iclass 33, count 0 2006.173.15:30:54.87#ibcon#read 4, iclass 33, count 0 2006.173.15:30:54.87#ibcon#about to read 5, iclass 33, count 0 2006.173.15:30:54.87#ibcon#read 5, iclass 33, count 0 2006.173.15:30:54.87#ibcon#about to read 6, iclass 33, count 0 2006.173.15:30:54.87#ibcon#read 6, iclass 33, count 0 2006.173.15:30:54.87#ibcon#end of sib2, iclass 33, count 0 2006.173.15:30:54.87#ibcon#*after write, iclass 33, count 0 2006.173.15:30:54.87#ibcon#*before return 0, iclass 33, count 0 2006.173.15:30:54.87#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.15:30:54.87#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.173.15:30:54.87#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.15:30:54.87#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.15:30:54.87$vck44/vblo=4,679.99 2006.173.15:30:54.87#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.15:30:54.87#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.15:30:54.87#ibcon#ireg 17 cls_cnt 0 2006.173.15:30:54.87#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.15:30:54.87#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.15:30:54.87#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.15:30:54.87#ibcon#enter wrdev, iclass 35, count 0 2006.173.15:30:54.87#ibcon#first serial, iclass 35, count 0 2006.173.15:30:54.87#ibcon#enter sib2, iclass 35, count 0 2006.173.15:30:54.87#ibcon#flushed, iclass 35, count 0 2006.173.15:30:54.87#ibcon#about to write, iclass 35, count 0 2006.173.15:30:54.87#ibcon#wrote, iclass 35, count 0 2006.173.15:30:54.87#ibcon#about to read 3, iclass 35, count 0 2006.173.15:30:54.89#ibcon#read 3, iclass 35, count 0 2006.173.15:30:54.89#ibcon#about to read 4, iclass 35, count 0 2006.173.15:30:54.89#ibcon#read 4, iclass 35, count 0 2006.173.15:30:54.89#ibcon#about to read 5, iclass 35, count 0 2006.173.15:30:54.89#ibcon#read 5, iclass 35, count 0 2006.173.15:30:54.89#ibcon#about to read 6, iclass 35, count 0 2006.173.15:30:54.89#ibcon#read 6, iclass 35, count 0 2006.173.15:30:54.89#ibcon#end of sib2, iclass 35, count 0 2006.173.15:30:54.89#ibcon#*mode == 0, iclass 35, count 0 2006.173.15:30:54.89#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.15:30:54.89#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.15:30:54.89#ibcon#*before write, iclass 35, count 0 2006.173.15:30:54.89#ibcon#enter sib2, iclass 35, count 0 2006.173.15:30:54.89#ibcon#flushed, iclass 35, count 0 2006.173.15:30:54.89#ibcon#about to write, iclass 35, count 0 2006.173.15:30:54.89#ibcon#wrote, iclass 35, count 0 2006.173.15:30:54.89#ibcon#about to read 3, iclass 35, count 0 2006.173.15:30:54.93#ibcon#read 3, iclass 35, count 0 2006.173.15:30:54.93#ibcon#about to read 4, iclass 35, count 0 2006.173.15:30:54.93#ibcon#read 4, iclass 35, count 0 2006.173.15:30:54.93#ibcon#about to read 5, iclass 35, count 0 2006.173.15:30:54.93#ibcon#read 5, iclass 35, count 0 2006.173.15:30:54.93#ibcon#about to read 6, iclass 35, count 0 2006.173.15:30:54.93#ibcon#read 6, iclass 35, count 0 2006.173.15:30:54.93#ibcon#end of sib2, iclass 35, count 0 2006.173.15:30:54.93#ibcon#*after write, iclass 35, count 0 2006.173.15:30:54.93#ibcon#*before return 0, iclass 35, count 0 2006.173.15:30:54.93#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.15:30:54.93#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.15:30:54.93#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.15:30:54.93#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.15:30:54.93$vck44/vb=4,4 2006.173.15:30:54.93#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.173.15:30:54.93#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.173.15:30:54.93#ibcon#ireg 11 cls_cnt 2 2006.173.15:30:54.93#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.15:30:54.99#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.15:30:54.99#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.15:30:54.99#ibcon#enter wrdev, iclass 37, count 2 2006.173.15:30:54.99#ibcon#first serial, iclass 37, count 2 2006.173.15:30:54.99#ibcon#enter sib2, iclass 37, count 2 2006.173.15:30:54.99#ibcon#flushed, iclass 37, count 2 2006.173.15:30:54.99#ibcon#about to write, iclass 37, count 2 2006.173.15:30:54.99#ibcon#wrote, iclass 37, count 2 2006.173.15:30:54.99#ibcon#about to read 3, iclass 37, count 2 2006.173.15:30:55.01#ibcon#read 3, iclass 37, count 2 2006.173.15:30:55.01#ibcon#about to read 4, iclass 37, count 2 2006.173.15:30:55.01#ibcon#read 4, iclass 37, count 2 2006.173.15:30:55.01#ibcon#about to read 5, iclass 37, count 2 2006.173.15:30:55.01#ibcon#read 5, iclass 37, count 2 2006.173.15:30:55.01#ibcon#about to read 6, iclass 37, count 2 2006.173.15:30:55.01#ibcon#read 6, iclass 37, count 2 2006.173.15:30:55.01#ibcon#end of sib2, iclass 37, count 2 2006.173.15:30:55.01#ibcon#*mode == 0, iclass 37, count 2 2006.173.15:30:55.01#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.173.15:30:55.01#ibcon#[27=AT04-04\r\n] 2006.173.15:30:55.01#ibcon#*before write, iclass 37, count 2 2006.173.15:30:55.01#ibcon#enter sib2, iclass 37, count 2 2006.173.15:30:55.01#ibcon#flushed, iclass 37, count 2 2006.173.15:30:55.01#ibcon#about to write, iclass 37, count 2 2006.173.15:30:55.01#ibcon#wrote, iclass 37, count 2 2006.173.15:30:55.01#ibcon#about to read 3, iclass 37, count 2 2006.173.15:30:55.04#ibcon#read 3, iclass 37, count 2 2006.173.15:30:55.04#ibcon#about to read 4, iclass 37, count 2 2006.173.15:30:55.04#ibcon#read 4, iclass 37, count 2 2006.173.15:30:55.04#ibcon#about to read 5, iclass 37, count 2 2006.173.15:30:55.04#ibcon#read 5, iclass 37, count 2 2006.173.15:30:55.04#ibcon#about to read 6, iclass 37, count 2 2006.173.15:30:55.04#ibcon#read 6, iclass 37, count 2 2006.173.15:30:55.04#ibcon#end of sib2, iclass 37, count 2 2006.173.15:30:55.04#ibcon#*after write, iclass 37, count 2 2006.173.15:30:55.04#ibcon#*before return 0, iclass 37, count 2 2006.173.15:30:55.04#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.15:30:55.04#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.173.15:30:55.04#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.173.15:30:55.04#ibcon#ireg 7 cls_cnt 0 2006.173.15:30:55.04#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.15:30:55.05#abcon#<5=/14 1.2 3.4 21.051001003.2\r\n> 2006.173.15:30:55.07#abcon#{5=INTERFACE CLEAR} 2006.173.15:30:55.13#abcon#[5=S1D000X0/0*\r\n] 2006.173.15:30:55.16#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.15:30:55.16#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.15:30:55.16#ibcon#enter wrdev, iclass 37, count 0 2006.173.15:30:55.16#ibcon#first serial, iclass 37, count 0 2006.173.15:30:55.16#ibcon#enter sib2, iclass 37, count 0 2006.173.15:30:55.16#ibcon#flushed, iclass 37, count 0 2006.173.15:30:55.16#ibcon#about to write, iclass 37, count 0 2006.173.15:30:55.16#ibcon#wrote, iclass 37, count 0 2006.173.15:30:55.16#ibcon#about to read 3, iclass 37, count 0 2006.173.15:30:55.18#ibcon#read 3, iclass 37, count 0 2006.173.15:30:55.18#ibcon#about to read 4, iclass 37, count 0 2006.173.15:30:55.18#ibcon#read 4, iclass 37, count 0 2006.173.15:30:55.18#ibcon#about to read 5, iclass 37, count 0 2006.173.15:30:55.18#ibcon#read 5, iclass 37, count 0 2006.173.15:30:55.18#ibcon#about to read 6, iclass 37, count 0 2006.173.15:30:55.18#ibcon#read 6, iclass 37, count 0 2006.173.15:30:55.18#ibcon#end of sib2, iclass 37, count 0 2006.173.15:30:55.18#ibcon#*mode == 0, iclass 37, count 0 2006.173.15:30:55.18#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.15:30:55.18#ibcon#[27=USB\r\n] 2006.173.15:30:55.18#ibcon#*before write, iclass 37, count 0 2006.173.15:30:55.18#ibcon#enter sib2, iclass 37, count 0 2006.173.15:30:55.18#ibcon#flushed, iclass 37, count 0 2006.173.15:30:55.18#ibcon#about to write, iclass 37, count 0 2006.173.15:30:55.18#ibcon#wrote, iclass 37, count 0 2006.173.15:30:55.18#ibcon#about to read 3, iclass 37, count 0 2006.173.15:30:55.21#ibcon#read 3, iclass 37, count 0 2006.173.15:30:55.21#ibcon#about to read 4, iclass 37, count 0 2006.173.15:30:55.21#ibcon#read 4, iclass 37, count 0 2006.173.15:30:55.21#ibcon#about to read 5, iclass 37, count 0 2006.173.15:30:55.21#ibcon#read 5, iclass 37, count 0 2006.173.15:30:55.21#ibcon#about to read 6, iclass 37, count 0 2006.173.15:30:55.21#ibcon#read 6, iclass 37, count 0 2006.173.15:30:55.21#ibcon#end of sib2, iclass 37, count 0 2006.173.15:30:55.21#ibcon#*after write, iclass 37, count 0 2006.173.15:30:55.21#ibcon#*before return 0, iclass 37, count 0 2006.173.15:30:55.21#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.15:30:55.21#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.173.15:30:55.21#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.15:30:55.21#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.15:30:55.21$vck44/vblo=5,709.99 2006.173.15:30:55.21#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.15:30:55.21#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.15:30:55.21#ibcon#ireg 17 cls_cnt 0 2006.173.15:30:55.21#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.15:30:55.21#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.15:30:55.21#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.15:30:55.21#ibcon#enter wrdev, iclass 5, count 0 2006.173.15:30:55.21#ibcon#first serial, iclass 5, count 0 2006.173.15:30:55.21#ibcon#enter sib2, iclass 5, count 0 2006.173.15:30:55.21#ibcon#flushed, iclass 5, count 0 2006.173.15:30:55.21#ibcon#about to write, iclass 5, count 0 2006.173.15:30:55.21#ibcon#wrote, iclass 5, count 0 2006.173.15:30:55.21#ibcon#about to read 3, iclass 5, count 0 2006.173.15:30:55.23#ibcon#read 3, iclass 5, count 0 2006.173.15:30:55.23#ibcon#about to read 4, iclass 5, count 0 2006.173.15:30:55.23#ibcon#read 4, iclass 5, count 0 2006.173.15:30:55.23#ibcon#about to read 5, iclass 5, count 0 2006.173.15:30:55.23#ibcon#read 5, iclass 5, count 0 2006.173.15:30:55.23#ibcon#about to read 6, iclass 5, count 0 2006.173.15:30:55.23#ibcon#read 6, iclass 5, count 0 2006.173.15:30:55.23#ibcon#end of sib2, iclass 5, count 0 2006.173.15:30:55.23#ibcon#*mode == 0, iclass 5, count 0 2006.173.15:30:55.23#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.15:30:55.23#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.15:30:55.23#ibcon#*before write, iclass 5, count 0 2006.173.15:30:55.23#ibcon#enter sib2, iclass 5, count 0 2006.173.15:30:55.23#ibcon#flushed, iclass 5, count 0 2006.173.15:30:55.23#ibcon#about to write, iclass 5, count 0 2006.173.15:30:55.23#ibcon#wrote, iclass 5, count 0 2006.173.15:30:55.23#ibcon#about to read 3, iclass 5, count 0 2006.173.15:30:55.27#ibcon#read 3, iclass 5, count 0 2006.173.15:30:55.27#ibcon#about to read 4, iclass 5, count 0 2006.173.15:30:55.27#ibcon#read 4, iclass 5, count 0 2006.173.15:30:55.27#ibcon#about to read 5, iclass 5, count 0 2006.173.15:30:55.27#ibcon#read 5, iclass 5, count 0 2006.173.15:30:55.27#ibcon#about to read 6, iclass 5, count 0 2006.173.15:30:55.27#ibcon#read 6, iclass 5, count 0 2006.173.15:30:55.27#ibcon#end of sib2, iclass 5, count 0 2006.173.15:30:55.27#ibcon#*after write, iclass 5, count 0 2006.173.15:30:55.27#ibcon#*before return 0, iclass 5, count 0 2006.173.15:30:55.27#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.15:30:55.27#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.15:30:55.27#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.15:30:55.27#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.15:30:55.27$vck44/vb=5,4 2006.173.15:30:55.27#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.173.15:30:55.27#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.173.15:30:55.27#ibcon#ireg 11 cls_cnt 2 2006.173.15:30:55.27#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.15:30:55.33#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.15:30:55.33#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.15:30:55.33#ibcon#enter wrdev, iclass 7, count 2 2006.173.15:30:55.33#ibcon#first serial, iclass 7, count 2 2006.173.15:30:55.33#ibcon#enter sib2, iclass 7, count 2 2006.173.15:30:55.33#ibcon#flushed, iclass 7, count 2 2006.173.15:30:55.33#ibcon#about to write, iclass 7, count 2 2006.173.15:30:55.33#ibcon#wrote, iclass 7, count 2 2006.173.15:30:55.33#ibcon#about to read 3, iclass 7, count 2 2006.173.15:30:55.35#ibcon#read 3, iclass 7, count 2 2006.173.15:30:55.35#ibcon#about to read 4, iclass 7, count 2 2006.173.15:30:55.35#ibcon#read 4, iclass 7, count 2 2006.173.15:30:55.35#ibcon#about to read 5, iclass 7, count 2 2006.173.15:30:55.35#ibcon#read 5, iclass 7, count 2 2006.173.15:30:55.35#ibcon#about to read 6, iclass 7, count 2 2006.173.15:30:55.35#ibcon#read 6, iclass 7, count 2 2006.173.15:30:55.35#ibcon#end of sib2, iclass 7, count 2 2006.173.15:30:55.35#ibcon#*mode == 0, iclass 7, count 2 2006.173.15:30:55.35#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.173.15:30:55.35#ibcon#[27=AT05-04\r\n] 2006.173.15:30:55.35#ibcon#*before write, iclass 7, count 2 2006.173.15:30:55.35#ibcon#enter sib2, iclass 7, count 2 2006.173.15:30:55.35#ibcon#flushed, iclass 7, count 2 2006.173.15:30:55.35#ibcon#about to write, iclass 7, count 2 2006.173.15:30:55.35#ibcon#wrote, iclass 7, count 2 2006.173.15:30:55.35#ibcon#about to read 3, iclass 7, count 2 2006.173.15:30:55.38#ibcon#read 3, iclass 7, count 2 2006.173.15:30:55.38#ibcon#about to read 4, iclass 7, count 2 2006.173.15:30:55.38#ibcon#read 4, iclass 7, count 2 2006.173.15:30:55.38#ibcon#about to read 5, iclass 7, count 2 2006.173.15:30:55.38#ibcon#read 5, iclass 7, count 2 2006.173.15:30:55.38#ibcon#about to read 6, iclass 7, count 2 2006.173.15:30:55.38#ibcon#read 6, iclass 7, count 2 2006.173.15:30:55.38#ibcon#end of sib2, iclass 7, count 2 2006.173.15:30:55.38#ibcon#*after write, iclass 7, count 2 2006.173.15:30:55.38#ibcon#*before return 0, iclass 7, count 2 2006.173.15:30:55.38#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.15:30:55.38#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.173.15:30:55.38#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.173.15:30:55.38#ibcon#ireg 7 cls_cnt 0 2006.173.15:30:55.38#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.15:30:55.50#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.15:30:55.50#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.15:30:55.50#ibcon#enter wrdev, iclass 7, count 0 2006.173.15:30:55.50#ibcon#first serial, iclass 7, count 0 2006.173.15:30:55.50#ibcon#enter sib2, iclass 7, count 0 2006.173.15:30:55.50#ibcon#flushed, iclass 7, count 0 2006.173.15:30:55.50#ibcon#about to write, iclass 7, count 0 2006.173.15:30:55.50#ibcon#wrote, iclass 7, count 0 2006.173.15:30:55.50#ibcon#about to read 3, iclass 7, count 0 2006.173.15:30:55.52#ibcon#read 3, iclass 7, count 0 2006.173.15:30:55.52#ibcon#about to read 4, iclass 7, count 0 2006.173.15:30:55.52#ibcon#read 4, iclass 7, count 0 2006.173.15:30:55.52#ibcon#about to read 5, iclass 7, count 0 2006.173.15:30:55.52#ibcon#read 5, iclass 7, count 0 2006.173.15:30:55.52#ibcon#about to read 6, iclass 7, count 0 2006.173.15:30:55.52#ibcon#read 6, iclass 7, count 0 2006.173.15:30:55.52#ibcon#end of sib2, iclass 7, count 0 2006.173.15:30:55.52#ibcon#*mode == 0, iclass 7, count 0 2006.173.15:30:55.52#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.15:30:55.52#ibcon#[27=USB\r\n] 2006.173.15:30:55.52#ibcon#*before write, iclass 7, count 0 2006.173.15:30:55.52#ibcon#enter sib2, iclass 7, count 0 2006.173.15:30:55.52#ibcon#flushed, iclass 7, count 0 2006.173.15:30:55.52#ibcon#about to write, iclass 7, count 0 2006.173.15:30:55.52#ibcon#wrote, iclass 7, count 0 2006.173.15:30:55.52#ibcon#about to read 3, iclass 7, count 0 2006.173.15:30:55.55#ibcon#read 3, iclass 7, count 0 2006.173.15:30:55.55#ibcon#about to read 4, iclass 7, count 0 2006.173.15:30:55.55#ibcon#read 4, iclass 7, count 0 2006.173.15:30:55.55#ibcon#about to read 5, iclass 7, count 0 2006.173.15:30:55.55#ibcon#read 5, iclass 7, count 0 2006.173.15:30:55.55#ibcon#about to read 6, iclass 7, count 0 2006.173.15:30:55.55#ibcon#read 6, iclass 7, count 0 2006.173.15:30:55.55#ibcon#end of sib2, iclass 7, count 0 2006.173.15:30:55.55#ibcon#*after write, iclass 7, count 0 2006.173.15:30:55.55#ibcon#*before return 0, iclass 7, count 0 2006.173.15:30:55.55#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.15:30:55.55#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.173.15:30:55.55#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.15:30:55.55#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.15:30:55.55$vck44/vblo=6,719.99 2006.173.15:30:55.55#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.15:30:55.55#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.15:30:55.55#ibcon#ireg 17 cls_cnt 0 2006.173.15:30:55.55#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.15:30:55.55#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.15:30:55.55#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.15:30:55.55#ibcon#enter wrdev, iclass 11, count 0 2006.173.15:30:55.55#ibcon#first serial, iclass 11, count 0 2006.173.15:30:55.55#ibcon#enter sib2, iclass 11, count 0 2006.173.15:30:55.55#ibcon#flushed, iclass 11, count 0 2006.173.15:30:55.55#ibcon#about to write, iclass 11, count 0 2006.173.15:30:55.55#ibcon#wrote, iclass 11, count 0 2006.173.15:30:55.55#ibcon#about to read 3, iclass 11, count 0 2006.173.15:30:55.57#ibcon#read 3, iclass 11, count 0 2006.173.15:30:55.57#ibcon#about to read 4, iclass 11, count 0 2006.173.15:30:55.57#ibcon#read 4, iclass 11, count 0 2006.173.15:30:55.57#ibcon#about to read 5, iclass 11, count 0 2006.173.15:30:55.57#ibcon#read 5, iclass 11, count 0 2006.173.15:30:55.57#ibcon#about to read 6, iclass 11, count 0 2006.173.15:30:55.57#ibcon#read 6, iclass 11, count 0 2006.173.15:30:55.57#ibcon#end of sib2, iclass 11, count 0 2006.173.15:30:55.57#ibcon#*mode == 0, iclass 11, count 0 2006.173.15:30:55.57#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.15:30:55.57#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.15:30:55.57#ibcon#*before write, iclass 11, count 0 2006.173.15:30:55.57#ibcon#enter sib2, iclass 11, count 0 2006.173.15:30:55.57#ibcon#flushed, iclass 11, count 0 2006.173.15:30:55.57#ibcon#about to write, iclass 11, count 0 2006.173.15:30:55.57#ibcon#wrote, iclass 11, count 0 2006.173.15:30:55.57#ibcon#about to read 3, iclass 11, count 0 2006.173.15:30:55.61#ibcon#read 3, iclass 11, count 0 2006.173.15:30:55.61#ibcon#about to read 4, iclass 11, count 0 2006.173.15:30:55.61#ibcon#read 4, iclass 11, count 0 2006.173.15:30:55.61#ibcon#about to read 5, iclass 11, count 0 2006.173.15:30:55.61#ibcon#read 5, iclass 11, count 0 2006.173.15:30:55.61#ibcon#about to read 6, iclass 11, count 0 2006.173.15:30:55.61#ibcon#read 6, iclass 11, count 0 2006.173.15:30:55.61#ibcon#end of sib2, iclass 11, count 0 2006.173.15:30:55.61#ibcon#*after write, iclass 11, count 0 2006.173.15:30:55.61#ibcon#*before return 0, iclass 11, count 0 2006.173.15:30:55.61#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.15:30:55.61#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.15:30:55.61#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.15:30:55.61#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.15:30:55.61$vck44/vb=6,4 2006.173.15:30:55.61#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.173.15:30:55.61#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.173.15:30:55.61#ibcon#ireg 11 cls_cnt 2 2006.173.15:30:55.61#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.15:30:55.67#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.15:30:55.67#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.15:30:55.67#ibcon#enter wrdev, iclass 13, count 2 2006.173.15:30:55.67#ibcon#first serial, iclass 13, count 2 2006.173.15:30:55.67#ibcon#enter sib2, iclass 13, count 2 2006.173.15:30:55.67#ibcon#flushed, iclass 13, count 2 2006.173.15:30:55.67#ibcon#about to write, iclass 13, count 2 2006.173.15:30:55.67#ibcon#wrote, iclass 13, count 2 2006.173.15:30:55.67#ibcon#about to read 3, iclass 13, count 2 2006.173.15:30:55.69#ibcon#read 3, iclass 13, count 2 2006.173.15:30:55.69#ibcon#about to read 4, iclass 13, count 2 2006.173.15:30:55.69#ibcon#read 4, iclass 13, count 2 2006.173.15:30:55.69#ibcon#about to read 5, iclass 13, count 2 2006.173.15:30:55.69#ibcon#read 5, iclass 13, count 2 2006.173.15:30:55.69#ibcon#about to read 6, iclass 13, count 2 2006.173.15:30:55.69#ibcon#read 6, iclass 13, count 2 2006.173.15:30:55.69#ibcon#end of sib2, iclass 13, count 2 2006.173.15:30:55.69#ibcon#*mode == 0, iclass 13, count 2 2006.173.15:30:55.69#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.173.15:30:55.69#ibcon#[27=AT06-04\r\n] 2006.173.15:30:55.69#ibcon#*before write, iclass 13, count 2 2006.173.15:30:55.69#ibcon#enter sib2, iclass 13, count 2 2006.173.15:30:55.69#ibcon#flushed, iclass 13, count 2 2006.173.15:30:55.69#ibcon#about to write, iclass 13, count 2 2006.173.15:30:55.69#ibcon#wrote, iclass 13, count 2 2006.173.15:30:55.69#ibcon#about to read 3, iclass 13, count 2 2006.173.15:30:55.72#ibcon#read 3, iclass 13, count 2 2006.173.15:30:55.72#ibcon#about to read 4, iclass 13, count 2 2006.173.15:30:55.72#ibcon#read 4, iclass 13, count 2 2006.173.15:30:55.72#ibcon#about to read 5, iclass 13, count 2 2006.173.15:30:55.72#ibcon#read 5, iclass 13, count 2 2006.173.15:30:55.72#ibcon#about to read 6, iclass 13, count 2 2006.173.15:30:55.72#ibcon#read 6, iclass 13, count 2 2006.173.15:30:55.72#ibcon#end of sib2, iclass 13, count 2 2006.173.15:30:55.72#ibcon#*after write, iclass 13, count 2 2006.173.15:30:55.72#ibcon#*before return 0, iclass 13, count 2 2006.173.15:30:55.72#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.15:30:55.72#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.173.15:30:55.72#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.173.15:30:55.72#ibcon#ireg 7 cls_cnt 0 2006.173.15:30:55.72#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.15:30:55.84#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.15:30:55.84#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.15:30:55.84#ibcon#enter wrdev, iclass 13, count 0 2006.173.15:30:55.84#ibcon#first serial, iclass 13, count 0 2006.173.15:30:55.84#ibcon#enter sib2, iclass 13, count 0 2006.173.15:30:55.84#ibcon#flushed, iclass 13, count 0 2006.173.15:30:55.84#ibcon#about to write, iclass 13, count 0 2006.173.15:30:55.84#ibcon#wrote, iclass 13, count 0 2006.173.15:30:55.84#ibcon#about to read 3, iclass 13, count 0 2006.173.15:30:55.86#ibcon#read 3, iclass 13, count 0 2006.173.15:30:55.86#ibcon#about to read 4, iclass 13, count 0 2006.173.15:30:55.86#ibcon#read 4, iclass 13, count 0 2006.173.15:30:55.86#ibcon#about to read 5, iclass 13, count 0 2006.173.15:30:55.86#ibcon#read 5, iclass 13, count 0 2006.173.15:30:55.86#ibcon#about to read 6, iclass 13, count 0 2006.173.15:30:55.86#ibcon#read 6, iclass 13, count 0 2006.173.15:30:55.86#ibcon#end of sib2, iclass 13, count 0 2006.173.15:30:55.86#ibcon#*mode == 0, iclass 13, count 0 2006.173.15:30:55.86#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.15:30:55.86#ibcon#[27=USB\r\n] 2006.173.15:30:55.86#ibcon#*before write, iclass 13, count 0 2006.173.15:30:55.86#ibcon#enter sib2, iclass 13, count 0 2006.173.15:30:55.86#ibcon#flushed, iclass 13, count 0 2006.173.15:30:55.86#ibcon#about to write, iclass 13, count 0 2006.173.15:30:55.86#ibcon#wrote, iclass 13, count 0 2006.173.15:30:55.86#ibcon#about to read 3, iclass 13, count 0 2006.173.15:30:55.89#ibcon#read 3, iclass 13, count 0 2006.173.15:30:55.89#ibcon#about to read 4, iclass 13, count 0 2006.173.15:30:55.89#ibcon#read 4, iclass 13, count 0 2006.173.15:30:55.89#ibcon#about to read 5, iclass 13, count 0 2006.173.15:30:55.89#ibcon#read 5, iclass 13, count 0 2006.173.15:30:55.89#ibcon#about to read 6, iclass 13, count 0 2006.173.15:30:55.89#ibcon#read 6, iclass 13, count 0 2006.173.15:30:55.89#ibcon#end of sib2, iclass 13, count 0 2006.173.15:30:55.89#ibcon#*after write, iclass 13, count 0 2006.173.15:30:55.89#ibcon#*before return 0, iclass 13, count 0 2006.173.15:30:55.89#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.15:30:55.89#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.173.15:30:55.89#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.15:30:55.89#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.15:30:55.89$vck44/vblo=7,734.99 2006.173.15:30:55.89#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.15:30:55.89#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.15:30:55.89#ibcon#ireg 17 cls_cnt 0 2006.173.15:30:55.89#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.15:30:55.89#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.15:30:55.89#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.15:30:55.89#ibcon#enter wrdev, iclass 15, count 0 2006.173.15:30:55.89#ibcon#first serial, iclass 15, count 0 2006.173.15:30:55.89#ibcon#enter sib2, iclass 15, count 0 2006.173.15:30:55.89#ibcon#flushed, iclass 15, count 0 2006.173.15:30:55.89#ibcon#about to write, iclass 15, count 0 2006.173.15:30:55.89#ibcon#wrote, iclass 15, count 0 2006.173.15:30:55.89#ibcon#about to read 3, iclass 15, count 0 2006.173.15:30:55.91#ibcon#read 3, iclass 15, count 0 2006.173.15:30:55.91#ibcon#about to read 4, iclass 15, count 0 2006.173.15:30:55.91#ibcon#read 4, iclass 15, count 0 2006.173.15:30:55.91#ibcon#about to read 5, iclass 15, count 0 2006.173.15:30:55.91#ibcon#read 5, iclass 15, count 0 2006.173.15:30:55.91#ibcon#about to read 6, iclass 15, count 0 2006.173.15:30:55.91#ibcon#read 6, iclass 15, count 0 2006.173.15:30:55.91#ibcon#end of sib2, iclass 15, count 0 2006.173.15:30:55.91#ibcon#*mode == 0, iclass 15, count 0 2006.173.15:30:55.91#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.15:30:55.91#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.15:30:55.91#ibcon#*before write, iclass 15, count 0 2006.173.15:30:55.91#ibcon#enter sib2, iclass 15, count 0 2006.173.15:30:55.91#ibcon#flushed, iclass 15, count 0 2006.173.15:30:55.91#ibcon#about to write, iclass 15, count 0 2006.173.15:30:55.91#ibcon#wrote, iclass 15, count 0 2006.173.15:30:55.91#ibcon#about to read 3, iclass 15, count 0 2006.173.15:30:55.95#ibcon#read 3, iclass 15, count 0 2006.173.15:30:55.95#ibcon#about to read 4, iclass 15, count 0 2006.173.15:30:55.95#ibcon#read 4, iclass 15, count 0 2006.173.15:30:55.95#ibcon#about to read 5, iclass 15, count 0 2006.173.15:30:55.95#ibcon#read 5, iclass 15, count 0 2006.173.15:30:55.95#ibcon#about to read 6, iclass 15, count 0 2006.173.15:30:55.95#ibcon#read 6, iclass 15, count 0 2006.173.15:30:55.95#ibcon#end of sib2, iclass 15, count 0 2006.173.15:30:55.95#ibcon#*after write, iclass 15, count 0 2006.173.15:30:55.95#ibcon#*before return 0, iclass 15, count 0 2006.173.15:30:55.95#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.15:30:55.95#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.15:30:55.95#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.15:30:55.95#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.15:30:55.95$vck44/vb=7,4 2006.173.15:30:55.95#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.15:30:55.95#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.15:30:55.95#ibcon#ireg 11 cls_cnt 2 2006.173.15:30:55.95#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.15:30:56.01#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.15:30:56.01#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.15:30:56.01#ibcon#enter wrdev, iclass 17, count 2 2006.173.15:30:56.01#ibcon#first serial, iclass 17, count 2 2006.173.15:30:56.01#ibcon#enter sib2, iclass 17, count 2 2006.173.15:30:56.01#ibcon#flushed, iclass 17, count 2 2006.173.15:30:56.01#ibcon#about to write, iclass 17, count 2 2006.173.15:30:56.01#ibcon#wrote, iclass 17, count 2 2006.173.15:30:56.01#ibcon#about to read 3, iclass 17, count 2 2006.173.15:30:56.03#ibcon#read 3, iclass 17, count 2 2006.173.15:30:56.03#ibcon#about to read 4, iclass 17, count 2 2006.173.15:30:56.03#ibcon#read 4, iclass 17, count 2 2006.173.15:30:56.03#ibcon#about to read 5, iclass 17, count 2 2006.173.15:30:56.03#ibcon#read 5, iclass 17, count 2 2006.173.15:30:56.03#ibcon#about to read 6, iclass 17, count 2 2006.173.15:30:56.03#ibcon#read 6, iclass 17, count 2 2006.173.15:30:56.03#ibcon#end of sib2, iclass 17, count 2 2006.173.15:30:56.03#ibcon#*mode == 0, iclass 17, count 2 2006.173.15:30:56.03#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.15:30:56.03#ibcon#[27=AT07-04\r\n] 2006.173.15:30:56.03#ibcon#*before write, iclass 17, count 2 2006.173.15:30:56.03#ibcon#enter sib2, iclass 17, count 2 2006.173.15:30:56.03#ibcon#flushed, iclass 17, count 2 2006.173.15:30:56.03#ibcon#about to write, iclass 17, count 2 2006.173.15:30:56.03#ibcon#wrote, iclass 17, count 2 2006.173.15:30:56.03#ibcon#about to read 3, iclass 17, count 2 2006.173.15:30:56.06#ibcon#read 3, iclass 17, count 2 2006.173.15:30:56.06#ibcon#about to read 4, iclass 17, count 2 2006.173.15:30:56.06#ibcon#read 4, iclass 17, count 2 2006.173.15:30:56.06#ibcon#about to read 5, iclass 17, count 2 2006.173.15:30:56.06#ibcon#read 5, iclass 17, count 2 2006.173.15:30:56.06#ibcon#about to read 6, iclass 17, count 2 2006.173.15:30:56.06#ibcon#read 6, iclass 17, count 2 2006.173.15:30:56.06#ibcon#end of sib2, iclass 17, count 2 2006.173.15:30:56.06#ibcon#*after write, iclass 17, count 2 2006.173.15:30:56.06#ibcon#*before return 0, iclass 17, count 2 2006.173.15:30:56.06#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.15:30:56.06#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.15:30:56.06#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.15:30:56.06#ibcon#ireg 7 cls_cnt 0 2006.173.15:30:56.06#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.15:30:56.18#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.15:30:56.18#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.15:30:56.18#ibcon#enter wrdev, iclass 17, count 0 2006.173.15:30:56.18#ibcon#first serial, iclass 17, count 0 2006.173.15:30:56.18#ibcon#enter sib2, iclass 17, count 0 2006.173.15:30:56.18#ibcon#flushed, iclass 17, count 0 2006.173.15:30:56.18#ibcon#about to write, iclass 17, count 0 2006.173.15:30:56.18#ibcon#wrote, iclass 17, count 0 2006.173.15:30:56.18#ibcon#about to read 3, iclass 17, count 0 2006.173.15:30:56.20#ibcon#read 3, iclass 17, count 0 2006.173.15:30:56.20#ibcon#about to read 4, iclass 17, count 0 2006.173.15:30:56.20#ibcon#read 4, iclass 17, count 0 2006.173.15:30:56.20#ibcon#about to read 5, iclass 17, count 0 2006.173.15:30:56.20#ibcon#read 5, iclass 17, count 0 2006.173.15:30:56.20#ibcon#about to read 6, iclass 17, count 0 2006.173.15:30:56.20#ibcon#read 6, iclass 17, count 0 2006.173.15:30:56.20#ibcon#end of sib2, iclass 17, count 0 2006.173.15:30:56.20#ibcon#*mode == 0, iclass 17, count 0 2006.173.15:30:56.20#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.15:30:56.20#ibcon#[27=USB\r\n] 2006.173.15:30:56.20#ibcon#*before write, iclass 17, count 0 2006.173.15:30:56.20#ibcon#enter sib2, iclass 17, count 0 2006.173.15:30:56.20#ibcon#flushed, iclass 17, count 0 2006.173.15:30:56.20#ibcon#about to write, iclass 17, count 0 2006.173.15:30:56.20#ibcon#wrote, iclass 17, count 0 2006.173.15:30:56.20#ibcon#about to read 3, iclass 17, count 0 2006.173.15:30:56.23#ibcon#read 3, iclass 17, count 0 2006.173.15:30:56.23#ibcon#about to read 4, iclass 17, count 0 2006.173.15:30:56.23#ibcon#read 4, iclass 17, count 0 2006.173.15:30:56.23#ibcon#about to read 5, iclass 17, count 0 2006.173.15:30:56.23#ibcon#read 5, iclass 17, count 0 2006.173.15:30:56.23#ibcon#about to read 6, iclass 17, count 0 2006.173.15:30:56.23#ibcon#read 6, iclass 17, count 0 2006.173.15:30:56.23#ibcon#end of sib2, iclass 17, count 0 2006.173.15:30:56.23#ibcon#*after write, iclass 17, count 0 2006.173.15:30:56.23#ibcon#*before return 0, iclass 17, count 0 2006.173.15:30:56.23#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.15:30:56.23#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.15:30:56.23#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.15:30:56.23#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.15:30:56.23$vck44/vblo=8,744.99 2006.173.15:30:56.23#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.15:30:56.23#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.15:30:56.23#ibcon#ireg 17 cls_cnt 0 2006.173.15:30:56.23#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.15:30:56.23#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.15:30:56.23#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.15:30:56.23#ibcon#enter wrdev, iclass 19, count 0 2006.173.15:30:56.23#ibcon#first serial, iclass 19, count 0 2006.173.15:30:56.23#ibcon#enter sib2, iclass 19, count 0 2006.173.15:30:56.23#ibcon#flushed, iclass 19, count 0 2006.173.15:30:56.23#ibcon#about to write, iclass 19, count 0 2006.173.15:30:56.23#ibcon#wrote, iclass 19, count 0 2006.173.15:30:56.23#ibcon#about to read 3, iclass 19, count 0 2006.173.15:30:56.25#ibcon#read 3, iclass 19, count 0 2006.173.15:30:56.25#ibcon#about to read 4, iclass 19, count 0 2006.173.15:30:56.25#ibcon#read 4, iclass 19, count 0 2006.173.15:30:56.25#ibcon#about to read 5, iclass 19, count 0 2006.173.15:30:56.25#ibcon#read 5, iclass 19, count 0 2006.173.15:30:56.25#ibcon#about to read 6, iclass 19, count 0 2006.173.15:30:56.25#ibcon#read 6, iclass 19, count 0 2006.173.15:30:56.25#ibcon#end of sib2, iclass 19, count 0 2006.173.15:30:56.25#ibcon#*mode == 0, iclass 19, count 0 2006.173.15:30:56.25#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.15:30:56.25#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.15:30:56.25#ibcon#*before write, iclass 19, count 0 2006.173.15:30:56.25#ibcon#enter sib2, iclass 19, count 0 2006.173.15:30:56.25#ibcon#flushed, iclass 19, count 0 2006.173.15:30:56.25#ibcon#about to write, iclass 19, count 0 2006.173.15:30:56.25#ibcon#wrote, iclass 19, count 0 2006.173.15:30:56.25#ibcon#about to read 3, iclass 19, count 0 2006.173.15:30:56.29#ibcon#read 3, iclass 19, count 0 2006.173.15:30:56.29#ibcon#about to read 4, iclass 19, count 0 2006.173.15:30:56.29#ibcon#read 4, iclass 19, count 0 2006.173.15:30:56.29#ibcon#about to read 5, iclass 19, count 0 2006.173.15:30:56.29#ibcon#read 5, iclass 19, count 0 2006.173.15:30:56.29#ibcon#about to read 6, iclass 19, count 0 2006.173.15:30:56.29#ibcon#read 6, iclass 19, count 0 2006.173.15:30:56.29#ibcon#end of sib2, iclass 19, count 0 2006.173.15:30:56.29#ibcon#*after write, iclass 19, count 0 2006.173.15:30:56.29#ibcon#*before return 0, iclass 19, count 0 2006.173.15:30:56.29#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.15:30:56.29#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.15:30:56.29#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.15:30:56.29#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.15:30:56.29$vck44/vb=8,4 2006.173.15:30:56.29#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.15:30:56.29#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.15:30:56.29#ibcon#ireg 11 cls_cnt 2 2006.173.15:30:56.29#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.15:30:56.35#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.15:30:56.35#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.15:30:56.35#ibcon#enter wrdev, iclass 21, count 2 2006.173.15:30:56.35#ibcon#first serial, iclass 21, count 2 2006.173.15:30:56.35#ibcon#enter sib2, iclass 21, count 2 2006.173.15:30:56.35#ibcon#flushed, iclass 21, count 2 2006.173.15:30:56.35#ibcon#about to write, iclass 21, count 2 2006.173.15:30:56.35#ibcon#wrote, iclass 21, count 2 2006.173.15:30:56.35#ibcon#about to read 3, iclass 21, count 2 2006.173.15:30:56.37#ibcon#read 3, iclass 21, count 2 2006.173.15:30:56.37#ibcon#about to read 4, iclass 21, count 2 2006.173.15:30:56.37#ibcon#read 4, iclass 21, count 2 2006.173.15:30:56.37#ibcon#about to read 5, iclass 21, count 2 2006.173.15:30:56.37#ibcon#read 5, iclass 21, count 2 2006.173.15:30:56.37#ibcon#about to read 6, iclass 21, count 2 2006.173.15:30:56.37#ibcon#read 6, iclass 21, count 2 2006.173.15:30:56.37#ibcon#end of sib2, iclass 21, count 2 2006.173.15:30:56.37#ibcon#*mode == 0, iclass 21, count 2 2006.173.15:30:56.37#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.15:30:56.37#ibcon#[27=AT08-04\r\n] 2006.173.15:30:56.37#ibcon#*before write, iclass 21, count 2 2006.173.15:30:56.37#ibcon#enter sib2, iclass 21, count 2 2006.173.15:30:56.37#ibcon#flushed, iclass 21, count 2 2006.173.15:30:56.37#ibcon#about to write, iclass 21, count 2 2006.173.15:30:56.37#ibcon#wrote, iclass 21, count 2 2006.173.15:30:56.37#ibcon#about to read 3, iclass 21, count 2 2006.173.15:30:56.40#ibcon#read 3, iclass 21, count 2 2006.173.15:30:56.40#ibcon#about to read 4, iclass 21, count 2 2006.173.15:30:56.40#ibcon#read 4, iclass 21, count 2 2006.173.15:30:56.40#ibcon#about to read 5, iclass 21, count 2 2006.173.15:30:56.40#ibcon#read 5, iclass 21, count 2 2006.173.15:30:56.40#ibcon#about to read 6, iclass 21, count 2 2006.173.15:30:56.40#ibcon#read 6, iclass 21, count 2 2006.173.15:30:56.40#ibcon#end of sib2, iclass 21, count 2 2006.173.15:30:56.40#ibcon#*after write, iclass 21, count 2 2006.173.15:30:56.40#ibcon#*before return 0, iclass 21, count 2 2006.173.15:30:56.40#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.15:30:56.40#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.15:30:56.40#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.15:30:56.40#ibcon#ireg 7 cls_cnt 0 2006.173.15:30:56.40#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.15:30:56.52#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.15:30:56.52#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.15:30:56.52#ibcon#enter wrdev, iclass 21, count 0 2006.173.15:30:56.52#ibcon#first serial, iclass 21, count 0 2006.173.15:30:56.52#ibcon#enter sib2, iclass 21, count 0 2006.173.15:30:56.52#ibcon#flushed, iclass 21, count 0 2006.173.15:30:56.52#ibcon#about to write, iclass 21, count 0 2006.173.15:30:56.52#ibcon#wrote, iclass 21, count 0 2006.173.15:30:56.52#ibcon#about to read 3, iclass 21, count 0 2006.173.15:30:56.54#ibcon#read 3, iclass 21, count 0 2006.173.15:30:56.54#ibcon#about to read 4, iclass 21, count 0 2006.173.15:30:56.54#ibcon#read 4, iclass 21, count 0 2006.173.15:30:56.54#ibcon#about to read 5, iclass 21, count 0 2006.173.15:30:56.54#ibcon#read 5, iclass 21, count 0 2006.173.15:30:56.54#ibcon#about to read 6, iclass 21, count 0 2006.173.15:30:56.54#ibcon#read 6, iclass 21, count 0 2006.173.15:30:56.54#ibcon#end of sib2, iclass 21, count 0 2006.173.15:30:56.54#ibcon#*mode == 0, iclass 21, count 0 2006.173.15:30:56.54#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.15:30:56.54#ibcon#[27=USB\r\n] 2006.173.15:30:56.54#ibcon#*before write, iclass 21, count 0 2006.173.15:30:56.54#ibcon#enter sib2, iclass 21, count 0 2006.173.15:30:56.54#ibcon#flushed, iclass 21, count 0 2006.173.15:30:56.54#ibcon#about to write, iclass 21, count 0 2006.173.15:30:56.54#ibcon#wrote, iclass 21, count 0 2006.173.15:30:56.54#ibcon#about to read 3, iclass 21, count 0 2006.173.15:30:56.57#ibcon#read 3, iclass 21, count 0 2006.173.15:30:56.57#ibcon#about to read 4, iclass 21, count 0 2006.173.15:30:56.57#ibcon#read 4, iclass 21, count 0 2006.173.15:30:56.57#ibcon#about to read 5, iclass 21, count 0 2006.173.15:30:56.57#ibcon#read 5, iclass 21, count 0 2006.173.15:30:56.57#ibcon#about to read 6, iclass 21, count 0 2006.173.15:30:56.57#ibcon#read 6, iclass 21, count 0 2006.173.15:30:56.57#ibcon#end of sib2, iclass 21, count 0 2006.173.15:30:56.57#ibcon#*after write, iclass 21, count 0 2006.173.15:30:56.57#ibcon#*before return 0, iclass 21, count 0 2006.173.15:30:56.57#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.15:30:56.57#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.15:30:56.57#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.15:30:56.57#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.15:30:56.57$vck44/vabw=wide 2006.173.15:30:56.57#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.15:30:56.57#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.15:30:56.57#ibcon#ireg 8 cls_cnt 0 2006.173.15:30:56.57#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.15:30:56.57#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.15:30:56.57#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.15:30:56.57#ibcon#enter wrdev, iclass 23, count 0 2006.173.15:30:56.57#ibcon#first serial, iclass 23, count 0 2006.173.15:30:56.57#ibcon#enter sib2, iclass 23, count 0 2006.173.15:30:56.57#ibcon#flushed, iclass 23, count 0 2006.173.15:30:56.57#ibcon#about to write, iclass 23, count 0 2006.173.15:30:56.57#ibcon#wrote, iclass 23, count 0 2006.173.15:30:56.57#ibcon#about to read 3, iclass 23, count 0 2006.173.15:30:56.59#ibcon#read 3, iclass 23, count 0 2006.173.15:30:56.59#ibcon#about to read 4, iclass 23, count 0 2006.173.15:30:56.59#ibcon#read 4, iclass 23, count 0 2006.173.15:30:56.59#ibcon#about to read 5, iclass 23, count 0 2006.173.15:30:56.59#ibcon#read 5, iclass 23, count 0 2006.173.15:30:56.59#ibcon#about to read 6, iclass 23, count 0 2006.173.15:30:56.59#ibcon#read 6, iclass 23, count 0 2006.173.15:30:56.59#ibcon#end of sib2, iclass 23, count 0 2006.173.15:30:56.59#ibcon#*mode == 0, iclass 23, count 0 2006.173.15:30:56.59#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.15:30:56.59#ibcon#[25=BW32\r\n] 2006.173.15:30:56.59#ibcon#*before write, iclass 23, count 0 2006.173.15:30:56.59#ibcon#enter sib2, iclass 23, count 0 2006.173.15:30:56.59#ibcon#flushed, iclass 23, count 0 2006.173.15:30:56.59#ibcon#about to write, iclass 23, count 0 2006.173.15:30:56.59#ibcon#wrote, iclass 23, count 0 2006.173.15:30:56.59#ibcon#about to read 3, iclass 23, count 0 2006.173.15:30:56.62#ibcon#read 3, iclass 23, count 0 2006.173.15:30:56.62#ibcon#about to read 4, iclass 23, count 0 2006.173.15:30:56.62#ibcon#read 4, iclass 23, count 0 2006.173.15:30:56.62#ibcon#about to read 5, iclass 23, count 0 2006.173.15:30:56.62#ibcon#read 5, iclass 23, count 0 2006.173.15:30:56.62#ibcon#about to read 6, iclass 23, count 0 2006.173.15:30:56.62#ibcon#read 6, iclass 23, count 0 2006.173.15:30:56.62#ibcon#end of sib2, iclass 23, count 0 2006.173.15:30:56.62#ibcon#*after write, iclass 23, count 0 2006.173.15:30:56.62#ibcon#*before return 0, iclass 23, count 0 2006.173.15:30:56.62#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.15:30:56.62#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.15:30:56.62#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.15:30:56.62#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.15:30:56.62$vck44/vbbw=wide 2006.173.15:30:56.62#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.15:30:56.62#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.15:30:56.62#ibcon#ireg 8 cls_cnt 0 2006.173.15:30:56.62#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.15:30:56.69#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.15:30:56.69#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.15:30:56.69#ibcon#enter wrdev, iclass 25, count 0 2006.173.15:30:56.69#ibcon#first serial, iclass 25, count 0 2006.173.15:30:56.69#ibcon#enter sib2, iclass 25, count 0 2006.173.15:30:56.69#ibcon#flushed, iclass 25, count 0 2006.173.15:30:56.69#ibcon#about to write, iclass 25, count 0 2006.173.15:30:56.69#ibcon#wrote, iclass 25, count 0 2006.173.15:30:56.69#ibcon#about to read 3, iclass 25, count 0 2006.173.15:30:56.71#ibcon#read 3, iclass 25, count 0 2006.173.15:30:56.71#ibcon#about to read 4, iclass 25, count 0 2006.173.15:30:56.71#ibcon#read 4, iclass 25, count 0 2006.173.15:30:56.71#ibcon#about to read 5, iclass 25, count 0 2006.173.15:30:56.71#ibcon#read 5, iclass 25, count 0 2006.173.15:30:56.71#ibcon#about to read 6, iclass 25, count 0 2006.173.15:30:56.71#ibcon#read 6, iclass 25, count 0 2006.173.15:30:56.71#ibcon#end of sib2, iclass 25, count 0 2006.173.15:30:56.71#ibcon#*mode == 0, iclass 25, count 0 2006.173.15:30:56.71#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.15:30:56.71#ibcon#[27=BW32\r\n] 2006.173.15:30:56.71#ibcon#*before write, iclass 25, count 0 2006.173.15:30:56.71#ibcon#enter sib2, iclass 25, count 0 2006.173.15:30:56.71#ibcon#flushed, iclass 25, count 0 2006.173.15:30:56.71#ibcon#about to write, iclass 25, count 0 2006.173.15:30:56.71#ibcon#wrote, iclass 25, count 0 2006.173.15:30:56.71#ibcon#about to read 3, iclass 25, count 0 2006.173.15:30:56.74#ibcon#read 3, iclass 25, count 0 2006.173.15:30:56.74#ibcon#about to read 4, iclass 25, count 0 2006.173.15:30:56.74#ibcon#read 4, iclass 25, count 0 2006.173.15:30:56.74#ibcon#about to read 5, iclass 25, count 0 2006.173.15:30:56.74#ibcon#read 5, iclass 25, count 0 2006.173.15:30:56.74#ibcon#about to read 6, iclass 25, count 0 2006.173.15:30:56.74#ibcon#read 6, iclass 25, count 0 2006.173.15:30:56.74#ibcon#end of sib2, iclass 25, count 0 2006.173.15:30:56.74#ibcon#*after write, iclass 25, count 0 2006.173.15:30:56.74#ibcon#*before return 0, iclass 25, count 0 2006.173.15:30:56.74#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.15:30:56.74#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.15:30:56.74#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.15:30:56.74#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.15:30:56.74$setupk4/ifdk4 2006.173.15:30:56.74$ifdk4/lo= 2006.173.15:30:56.74$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.15:30:56.74$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.15:30:56.74$ifdk4/patch= 2006.173.15:30:56.75$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.15:30:56.75$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.15:30:56.75$setupk4/!*+20s 2006.173.15:31:05.22#abcon#<5=/14 1.2 3.4 21.051001003.2\r\n> 2006.173.15:31:05.24#abcon#{5=INTERFACE CLEAR} 2006.173.15:31:05.30#abcon#[5=S1D000X0/0*\r\n] 2006.173.15:31:11.26$setupk4/"tpicd 2006.173.15:31:11.26$setupk4/echo=off 2006.173.15:31:11.26$setupk4/xlog=off 2006.173.15:31:11.26:!2006.173.15:33:46 2006.173.15:31:23.14#trakl#Source acquired 2006.173.15:31:25.14#flagr#flagr/antenna,acquired 2006.173.15:33:46.00:preob 2006.173.15:33:47.14/onsource/TRACKING 2006.173.15:33:47.14:!2006.173.15:33:56 2006.173.15:33:56.00:"tape 2006.173.15:33:56.00:"st=record 2006.173.15:33:56.00:data_valid=on 2006.173.15:33:56.00:midob 2006.173.15:33:56.14/onsource/TRACKING 2006.173.15:33:56.14/wx/21.03,1003.1,100 2006.173.15:33:56.32/cable/+6.5078E-03 2006.173.15:33:57.41/va/01,07,usb,yes,36,39 2006.173.15:33:57.41/va/02,06,usb,yes,36,37 2006.173.15:33:57.41/va/03,05,usb,yes,46,48 2006.173.15:33:57.41/va/04,06,usb,yes,37,39 2006.173.15:33:57.41/va/05,04,usb,yes,29,30 2006.173.15:33:57.41/va/06,03,usb,yes,41,40 2006.173.15:33:57.41/va/07,04,usb,yes,33,34 2006.173.15:33:57.41/va/08,04,usb,yes,28,34 2006.173.15:33:57.64/valo/01,524.99,yes,locked 2006.173.15:33:57.64/valo/02,534.99,yes,locked 2006.173.15:33:57.64/valo/03,564.99,yes,locked 2006.173.15:33:57.64/valo/04,624.99,yes,locked 2006.173.15:33:57.64/valo/05,734.99,yes,locked 2006.173.15:33:57.64/valo/06,814.99,yes,locked 2006.173.15:33:57.64/valo/07,864.99,yes,locked 2006.173.15:33:57.64/valo/08,884.99,yes,locked 2006.173.15:33:58.73/vb/01,04,usb,yes,29,27 2006.173.15:33:58.73/vb/02,04,usb,yes,31,31 2006.173.15:33:58.73/vb/03,04,usb,yes,28,31 2006.173.15:33:58.73/vb/04,04,usb,yes,32,31 2006.173.15:33:58.73/vb/05,04,usb,yes,25,27 2006.173.15:33:58.73/vb/06,04,usb,yes,29,26 2006.173.15:33:58.73/vb/07,04,usb,yes,29,29 2006.173.15:33:58.73/vb/08,04,usb,yes,27,30 2006.173.15:33:58.96/vblo/01,629.99,yes,locked 2006.173.15:33:58.96/vblo/02,634.99,yes,locked 2006.173.15:33:58.96/vblo/03,649.99,yes,locked 2006.173.15:33:58.96/vblo/04,679.99,yes,locked 2006.173.15:33:58.96/vblo/05,709.99,yes,locked 2006.173.15:33:58.96/vblo/06,719.99,yes,locked 2006.173.15:33:58.96/vblo/07,734.99,yes,locked 2006.173.15:33:58.96/vblo/08,744.99,yes,locked 2006.173.15:33:59.11/vabw/8 2006.173.15:33:59.26/vbbw/8 2006.173.15:33:59.35/xfe/off,on,15.2 2006.173.15:33:59.72/ifatt/23,28,28,28 2006.173.15:34:00.08/fmout-gps/S +3.93E-07 2006.173.15:34:00.12:!2006.173.15:36:06 2006.173.15:36:06.01:data_valid=off 2006.173.15:36:06.01:"et 2006.173.15:36:06.01:!+3s 2006.173.15:36:09.02:"tape 2006.173.15:36:09.02:postob 2006.173.15:36:09.12/cable/+6.5084E-03 2006.173.15:36:09.12/wx/21.01,1003.0,100 2006.173.15:36:09.18/fmout-gps/S +3.94E-07 2006.173.15:36:09.18:scan_name=173-1542,jd0606,80 2006.173.15:36:09.18:source=2136+141,213901.31,142336.0,2000.0,cw 2006.173.15:36:11.14#flagr#flagr/antenna,new-source 2006.173.15:36:11.14:checkk5 2006.173.15:36:11.50/chk_autoobs//k5ts1/ autoobs is running! 2006.173.15:36:11.89/chk_autoobs//k5ts2/ autoobs is running! 2006.173.15:36:12.28/chk_autoobs//k5ts3/ autoobs is running! 2006.173.15:36:12.67/chk_autoobs//k5ts4/ autoobs is running! 2006.173.15:36:13.06/chk_obsdata//k5ts1/T1731533??a.dat file size is correct (nominal:520MB, actual:516MB). 2006.173.15:36:13.45/chk_obsdata//k5ts2/T1731533??b.dat file size is correct (nominal:520MB, actual:516MB). 2006.173.15:36:13.85/chk_obsdata//k5ts3/T1731533??c.dat file size is correct (nominal:520MB, actual:516MB). 2006.173.15:36:14.27/chk_obsdata//k5ts4/T1731533??d.dat file size is correct (nominal:520MB, actual:516MB). 2006.173.15:36:15.00/k5log//k5ts1_log_newline 2006.173.15:36:15.71/k5log//k5ts2_log_newline 2006.173.15:36:16.41/k5log//k5ts3_log_newline 2006.173.15:36:17.13/k5log//k5ts4_log_newline 2006.173.15:36:17.15/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.15:36:17.15:setupk4=1 2006.173.15:36:17.15$setupk4/echo=on 2006.173.15:36:17.15$setupk4/pcalon 2006.173.15:36:17.15$pcalon/"no phase cal control is implemented here 2006.173.15:36:17.15$setupk4/"tpicd=stop 2006.173.15:36:17.15$setupk4/"rec=synch_on 2006.173.15:36:17.15$setupk4/"rec_mode=128 2006.173.15:36:17.15$setupk4/!* 2006.173.15:36:17.15$setupk4/recpk4 2006.173.15:36:17.15$recpk4/recpatch= 2006.173.15:36:17.16$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.15:36:17.16$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.15:36:17.16$setupk4/vck44 2006.173.15:36:17.16$vck44/valo=1,524.99 2006.173.15:36:17.16#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.15:36:17.16#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.15:36:17.16#ibcon#ireg 17 cls_cnt 0 2006.173.15:36:17.16#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.15:36:17.16#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.15:36:17.16#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.15:36:17.16#ibcon#enter wrdev, iclass 10, count 0 2006.173.15:36:17.16#ibcon#first serial, iclass 10, count 0 2006.173.15:36:17.16#ibcon#enter sib2, iclass 10, count 0 2006.173.15:36:17.16#ibcon#flushed, iclass 10, count 0 2006.173.15:36:17.16#ibcon#about to write, iclass 10, count 0 2006.173.15:36:17.16#ibcon#wrote, iclass 10, count 0 2006.173.15:36:17.16#ibcon#about to read 3, iclass 10, count 0 2006.173.15:36:17.17#ibcon#read 3, iclass 10, count 0 2006.173.15:36:17.17#ibcon#about to read 4, iclass 10, count 0 2006.173.15:36:17.17#ibcon#read 4, iclass 10, count 0 2006.173.15:36:17.17#ibcon#about to read 5, iclass 10, count 0 2006.173.15:36:17.17#ibcon#read 5, iclass 10, count 0 2006.173.15:36:17.17#ibcon#about to read 6, iclass 10, count 0 2006.173.15:36:17.17#ibcon#read 6, iclass 10, count 0 2006.173.15:36:17.17#ibcon#end of sib2, iclass 10, count 0 2006.173.15:36:17.17#ibcon#*mode == 0, iclass 10, count 0 2006.173.15:36:17.17#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.15:36:17.17#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.15:36:17.17#ibcon#*before write, iclass 10, count 0 2006.173.15:36:17.17#ibcon#enter sib2, iclass 10, count 0 2006.173.15:36:17.17#ibcon#flushed, iclass 10, count 0 2006.173.15:36:17.17#ibcon#about to write, iclass 10, count 0 2006.173.15:36:17.17#ibcon#wrote, iclass 10, count 0 2006.173.15:36:17.17#ibcon#about to read 3, iclass 10, count 0 2006.173.15:36:17.22#ibcon#read 3, iclass 10, count 0 2006.173.15:36:17.22#ibcon#about to read 4, iclass 10, count 0 2006.173.15:36:17.22#ibcon#read 4, iclass 10, count 0 2006.173.15:36:17.22#ibcon#about to read 5, iclass 10, count 0 2006.173.15:36:17.22#ibcon#read 5, iclass 10, count 0 2006.173.15:36:17.22#ibcon#about to read 6, iclass 10, count 0 2006.173.15:36:17.22#ibcon#read 6, iclass 10, count 0 2006.173.15:36:17.22#ibcon#end of sib2, iclass 10, count 0 2006.173.15:36:17.22#ibcon#*after write, iclass 10, count 0 2006.173.15:36:17.22#ibcon#*before return 0, iclass 10, count 0 2006.173.15:36:17.22#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.15:36:17.22#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.15:36:17.22#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.15:36:17.22#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.15:36:17.22$vck44/va=1,7 2006.173.15:36:17.22#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.15:36:17.22#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.15:36:17.22#ibcon#ireg 11 cls_cnt 2 2006.173.15:36:17.22#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.15:36:17.22#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.15:36:17.22#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.15:36:17.22#ibcon#enter wrdev, iclass 12, count 2 2006.173.15:36:17.22#ibcon#first serial, iclass 12, count 2 2006.173.15:36:17.22#ibcon#enter sib2, iclass 12, count 2 2006.173.15:36:17.22#ibcon#flushed, iclass 12, count 2 2006.173.15:36:17.22#ibcon#about to write, iclass 12, count 2 2006.173.15:36:17.22#ibcon#wrote, iclass 12, count 2 2006.173.15:36:17.22#ibcon#about to read 3, iclass 12, count 2 2006.173.15:36:17.24#ibcon#read 3, iclass 12, count 2 2006.173.15:36:17.24#ibcon#about to read 4, iclass 12, count 2 2006.173.15:36:17.24#ibcon#read 4, iclass 12, count 2 2006.173.15:36:17.24#ibcon#about to read 5, iclass 12, count 2 2006.173.15:36:17.24#ibcon#read 5, iclass 12, count 2 2006.173.15:36:17.24#ibcon#about to read 6, iclass 12, count 2 2006.173.15:36:17.24#ibcon#read 6, iclass 12, count 2 2006.173.15:36:17.24#ibcon#end of sib2, iclass 12, count 2 2006.173.15:36:17.24#ibcon#*mode == 0, iclass 12, count 2 2006.173.15:36:17.24#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.15:36:17.24#ibcon#[25=AT01-07\r\n] 2006.173.15:36:17.24#ibcon#*before write, iclass 12, count 2 2006.173.15:36:17.24#ibcon#enter sib2, iclass 12, count 2 2006.173.15:36:17.24#ibcon#flushed, iclass 12, count 2 2006.173.15:36:17.24#ibcon#about to write, iclass 12, count 2 2006.173.15:36:17.24#ibcon#wrote, iclass 12, count 2 2006.173.15:36:17.24#ibcon#about to read 3, iclass 12, count 2 2006.173.15:36:17.27#ibcon#read 3, iclass 12, count 2 2006.173.15:36:17.27#ibcon#about to read 4, iclass 12, count 2 2006.173.15:36:17.27#ibcon#read 4, iclass 12, count 2 2006.173.15:36:17.27#ibcon#about to read 5, iclass 12, count 2 2006.173.15:36:17.27#ibcon#read 5, iclass 12, count 2 2006.173.15:36:17.27#ibcon#about to read 6, iclass 12, count 2 2006.173.15:36:17.27#ibcon#read 6, iclass 12, count 2 2006.173.15:36:17.27#ibcon#end of sib2, iclass 12, count 2 2006.173.15:36:17.27#ibcon#*after write, iclass 12, count 2 2006.173.15:36:17.27#ibcon#*before return 0, iclass 12, count 2 2006.173.15:36:17.27#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.15:36:17.27#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.15:36:17.27#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.15:36:17.27#ibcon#ireg 7 cls_cnt 0 2006.173.15:36:17.27#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.15:36:17.39#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.15:36:17.39#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.15:36:17.39#ibcon#enter wrdev, iclass 12, count 0 2006.173.15:36:17.39#ibcon#first serial, iclass 12, count 0 2006.173.15:36:17.39#ibcon#enter sib2, iclass 12, count 0 2006.173.15:36:17.39#ibcon#flushed, iclass 12, count 0 2006.173.15:36:17.39#ibcon#about to write, iclass 12, count 0 2006.173.15:36:17.39#ibcon#wrote, iclass 12, count 0 2006.173.15:36:17.39#ibcon#about to read 3, iclass 12, count 0 2006.173.15:36:17.41#ibcon#read 3, iclass 12, count 0 2006.173.15:36:17.41#ibcon#about to read 4, iclass 12, count 0 2006.173.15:36:17.41#ibcon#read 4, iclass 12, count 0 2006.173.15:36:17.41#ibcon#about to read 5, iclass 12, count 0 2006.173.15:36:17.41#ibcon#read 5, iclass 12, count 0 2006.173.15:36:17.41#ibcon#about to read 6, iclass 12, count 0 2006.173.15:36:17.41#ibcon#read 6, iclass 12, count 0 2006.173.15:36:17.41#ibcon#end of sib2, iclass 12, count 0 2006.173.15:36:17.41#ibcon#*mode == 0, iclass 12, count 0 2006.173.15:36:17.41#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.15:36:17.41#ibcon#[25=USB\r\n] 2006.173.15:36:17.41#ibcon#*before write, iclass 12, count 0 2006.173.15:36:17.41#ibcon#enter sib2, iclass 12, count 0 2006.173.15:36:17.41#ibcon#flushed, iclass 12, count 0 2006.173.15:36:17.41#ibcon#about to write, iclass 12, count 0 2006.173.15:36:17.41#ibcon#wrote, iclass 12, count 0 2006.173.15:36:17.41#ibcon#about to read 3, iclass 12, count 0 2006.173.15:36:17.44#ibcon#read 3, iclass 12, count 0 2006.173.15:36:17.44#ibcon#about to read 4, iclass 12, count 0 2006.173.15:36:17.44#ibcon#read 4, iclass 12, count 0 2006.173.15:36:17.44#ibcon#about to read 5, iclass 12, count 0 2006.173.15:36:17.44#ibcon#read 5, iclass 12, count 0 2006.173.15:36:17.44#ibcon#about to read 6, iclass 12, count 0 2006.173.15:36:17.44#ibcon#read 6, iclass 12, count 0 2006.173.15:36:17.44#ibcon#end of sib2, iclass 12, count 0 2006.173.15:36:17.44#ibcon#*after write, iclass 12, count 0 2006.173.15:36:17.44#ibcon#*before return 0, iclass 12, count 0 2006.173.15:36:17.44#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.15:36:17.44#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.15:36:17.44#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.15:36:17.44#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.15:36:17.44$vck44/valo=2,534.99 2006.173.15:36:17.44#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.15:36:17.44#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.15:36:17.44#ibcon#ireg 17 cls_cnt 0 2006.173.15:36:17.44#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.15:36:17.44#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.15:36:17.44#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.15:36:17.44#ibcon#enter wrdev, iclass 14, count 0 2006.173.15:36:17.44#ibcon#first serial, iclass 14, count 0 2006.173.15:36:17.44#ibcon#enter sib2, iclass 14, count 0 2006.173.15:36:17.44#ibcon#flushed, iclass 14, count 0 2006.173.15:36:17.44#ibcon#about to write, iclass 14, count 0 2006.173.15:36:17.44#ibcon#wrote, iclass 14, count 0 2006.173.15:36:17.44#ibcon#about to read 3, iclass 14, count 0 2006.173.15:36:17.46#ibcon#read 3, iclass 14, count 0 2006.173.15:36:17.46#ibcon#about to read 4, iclass 14, count 0 2006.173.15:36:17.46#ibcon#read 4, iclass 14, count 0 2006.173.15:36:17.46#ibcon#about to read 5, iclass 14, count 0 2006.173.15:36:17.46#ibcon#read 5, iclass 14, count 0 2006.173.15:36:17.46#ibcon#about to read 6, iclass 14, count 0 2006.173.15:36:17.46#ibcon#read 6, iclass 14, count 0 2006.173.15:36:17.46#ibcon#end of sib2, iclass 14, count 0 2006.173.15:36:17.46#ibcon#*mode == 0, iclass 14, count 0 2006.173.15:36:17.46#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.15:36:17.46#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.15:36:17.46#ibcon#*before write, iclass 14, count 0 2006.173.15:36:17.46#ibcon#enter sib2, iclass 14, count 0 2006.173.15:36:17.46#ibcon#flushed, iclass 14, count 0 2006.173.15:36:17.46#ibcon#about to write, iclass 14, count 0 2006.173.15:36:17.46#ibcon#wrote, iclass 14, count 0 2006.173.15:36:17.46#ibcon#about to read 3, iclass 14, count 0 2006.173.15:36:17.50#ibcon#read 3, iclass 14, count 0 2006.173.15:36:17.50#ibcon#about to read 4, iclass 14, count 0 2006.173.15:36:17.50#ibcon#read 4, iclass 14, count 0 2006.173.15:36:17.50#ibcon#about to read 5, iclass 14, count 0 2006.173.15:36:17.50#ibcon#read 5, iclass 14, count 0 2006.173.15:36:17.50#ibcon#about to read 6, iclass 14, count 0 2006.173.15:36:17.50#ibcon#read 6, iclass 14, count 0 2006.173.15:36:17.50#ibcon#end of sib2, iclass 14, count 0 2006.173.15:36:17.50#ibcon#*after write, iclass 14, count 0 2006.173.15:36:17.50#ibcon#*before return 0, iclass 14, count 0 2006.173.15:36:17.50#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.15:36:17.50#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.15:36:17.50#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.15:36:17.50#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.15:36:17.50$vck44/va=2,6 2006.173.15:36:17.50#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.15:36:17.50#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.15:36:17.50#ibcon#ireg 11 cls_cnt 2 2006.173.15:36:17.50#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.15:36:17.56#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.15:36:17.56#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.15:36:17.56#ibcon#enter wrdev, iclass 16, count 2 2006.173.15:36:17.56#ibcon#first serial, iclass 16, count 2 2006.173.15:36:17.56#ibcon#enter sib2, iclass 16, count 2 2006.173.15:36:17.56#ibcon#flushed, iclass 16, count 2 2006.173.15:36:17.56#ibcon#about to write, iclass 16, count 2 2006.173.15:36:17.56#ibcon#wrote, iclass 16, count 2 2006.173.15:36:17.56#ibcon#about to read 3, iclass 16, count 2 2006.173.15:36:17.58#ibcon#read 3, iclass 16, count 2 2006.173.15:36:17.58#ibcon#about to read 4, iclass 16, count 2 2006.173.15:36:17.58#ibcon#read 4, iclass 16, count 2 2006.173.15:36:17.58#ibcon#about to read 5, iclass 16, count 2 2006.173.15:36:17.58#ibcon#read 5, iclass 16, count 2 2006.173.15:36:17.58#ibcon#about to read 6, iclass 16, count 2 2006.173.15:36:17.58#ibcon#read 6, iclass 16, count 2 2006.173.15:36:17.58#ibcon#end of sib2, iclass 16, count 2 2006.173.15:36:17.58#ibcon#*mode == 0, iclass 16, count 2 2006.173.15:36:17.58#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.15:36:17.58#ibcon#[25=AT02-06\r\n] 2006.173.15:36:17.58#ibcon#*before write, iclass 16, count 2 2006.173.15:36:17.58#ibcon#enter sib2, iclass 16, count 2 2006.173.15:36:17.58#ibcon#flushed, iclass 16, count 2 2006.173.15:36:17.58#ibcon#about to write, iclass 16, count 2 2006.173.15:36:17.58#ibcon#wrote, iclass 16, count 2 2006.173.15:36:17.58#ibcon#about to read 3, iclass 16, count 2 2006.173.15:36:17.61#ibcon#read 3, iclass 16, count 2 2006.173.15:36:17.61#ibcon#about to read 4, iclass 16, count 2 2006.173.15:36:17.61#ibcon#read 4, iclass 16, count 2 2006.173.15:36:17.61#ibcon#about to read 5, iclass 16, count 2 2006.173.15:36:17.61#ibcon#read 5, iclass 16, count 2 2006.173.15:36:17.61#ibcon#about to read 6, iclass 16, count 2 2006.173.15:36:17.61#ibcon#read 6, iclass 16, count 2 2006.173.15:36:17.61#ibcon#end of sib2, iclass 16, count 2 2006.173.15:36:17.61#ibcon#*after write, iclass 16, count 2 2006.173.15:36:17.61#ibcon#*before return 0, iclass 16, count 2 2006.173.15:36:17.61#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.15:36:17.61#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.15:36:17.61#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.15:36:17.61#ibcon#ireg 7 cls_cnt 0 2006.173.15:36:17.61#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.15:36:17.73#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.15:36:17.73#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.15:36:17.73#ibcon#enter wrdev, iclass 16, count 0 2006.173.15:36:17.73#ibcon#first serial, iclass 16, count 0 2006.173.15:36:17.73#ibcon#enter sib2, iclass 16, count 0 2006.173.15:36:17.73#ibcon#flushed, iclass 16, count 0 2006.173.15:36:17.73#ibcon#about to write, iclass 16, count 0 2006.173.15:36:17.73#ibcon#wrote, iclass 16, count 0 2006.173.15:36:17.73#ibcon#about to read 3, iclass 16, count 0 2006.173.15:36:17.75#ibcon#read 3, iclass 16, count 0 2006.173.15:36:17.75#ibcon#about to read 4, iclass 16, count 0 2006.173.15:36:17.75#ibcon#read 4, iclass 16, count 0 2006.173.15:36:17.75#ibcon#about to read 5, iclass 16, count 0 2006.173.15:36:17.75#ibcon#read 5, iclass 16, count 0 2006.173.15:36:17.75#ibcon#about to read 6, iclass 16, count 0 2006.173.15:36:17.75#ibcon#read 6, iclass 16, count 0 2006.173.15:36:17.75#ibcon#end of sib2, iclass 16, count 0 2006.173.15:36:17.75#ibcon#*mode == 0, iclass 16, count 0 2006.173.15:36:17.75#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.15:36:17.75#ibcon#[25=USB\r\n] 2006.173.15:36:17.75#ibcon#*before write, iclass 16, count 0 2006.173.15:36:17.75#ibcon#enter sib2, iclass 16, count 0 2006.173.15:36:17.75#ibcon#flushed, iclass 16, count 0 2006.173.15:36:17.75#ibcon#about to write, iclass 16, count 0 2006.173.15:36:17.75#ibcon#wrote, iclass 16, count 0 2006.173.15:36:17.75#ibcon#about to read 3, iclass 16, count 0 2006.173.15:36:17.78#ibcon#read 3, iclass 16, count 0 2006.173.15:36:17.78#ibcon#about to read 4, iclass 16, count 0 2006.173.15:36:17.78#ibcon#read 4, iclass 16, count 0 2006.173.15:36:17.78#ibcon#about to read 5, iclass 16, count 0 2006.173.15:36:17.78#ibcon#read 5, iclass 16, count 0 2006.173.15:36:17.78#ibcon#about to read 6, iclass 16, count 0 2006.173.15:36:17.78#ibcon#read 6, iclass 16, count 0 2006.173.15:36:17.78#ibcon#end of sib2, iclass 16, count 0 2006.173.15:36:17.78#ibcon#*after write, iclass 16, count 0 2006.173.15:36:17.78#ibcon#*before return 0, iclass 16, count 0 2006.173.15:36:17.78#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.15:36:17.78#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.15:36:17.78#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.15:36:17.78#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.15:36:17.78$vck44/valo=3,564.99 2006.173.15:36:17.78#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.15:36:17.78#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.15:36:17.78#ibcon#ireg 17 cls_cnt 0 2006.173.15:36:17.78#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.15:36:17.78#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.15:36:17.78#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.15:36:17.78#ibcon#enter wrdev, iclass 18, count 0 2006.173.15:36:17.78#ibcon#first serial, iclass 18, count 0 2006.173.15:36:17.78#ibcon#enter sib2, iclass 18, count 0 2006.173.15:36:17.78#ibcon#flushed, iclass 18, count 0 2006.173.15:36:17.78#ibcon#about to write, iclass 18, count 0 2006.173.15:36:17.78#ibcon#wrote, iclass 18, count 0 2006.173.15:36:17.78#ibcon#about to read 3, iclass 18, count 0 2006.173.15:36:17.80#ibcon#read 3, iclass 18, count 0 2006.173.15:36:17.80#ibcon#about to read 4, iclass 18, count 0 2006.173.15:36:17.80#ibcon#read 4, iclass 18, count 0 2006.173.15:36:17.80#ibcon#about to read 5, iclass 18, count 0 2006.173.15:36:17.80#ibcon#read 5, iclass 18, count 0 2006.173.15:36:17.80#ibcon#about to read 6, iclass 18, count 0 2006.173.15:36:17.80#ibcon#read 6, iclass 18, count 0 2006.173.15:36:17.80#ibcon#end of sib2, iclass 18, count 0 2006.173.15:36:17.80#ibcon#*mode == 0, iclass 18, count 0 2006.173.15:36:17.80#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.15:36:17.80#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.15:36:17.80#ibcon#*before write, iclass 18, count 0 2006.173.15:36:17.80#ibcon#enter sib2, iclass 18, count 0 2006.173.15:36:17.80#ibcon#flushed, iclass 18, count 0 2006.173.15:36:17.80#ibcon#about to write, iclass 18, count 0 2006.173.15:36:17.80#ibcon#wrote, iclass 18, count 0 2006.173.15:36:17.80#ibcon#about to read 3, iclass 18, count 0 2006.173.15:36:17.84#ibcon#read 3, iclass 18, count 0 2006.173.15:36:17.84#ibcon#about to read 4, iclass 18, count 0 2006.173.15:36:17.84#ibcon#read 4, iclass 18, count 0 2006.173.15:36:17.84#ibcon#about to read 5, iclass 18, count 0 2006.173.15:36:17.84#ibcon#read 5, iclass 18, count 0 2006.173.15:36:17.84#ibcon#about to read 6, iclass 18, count 0 2006.173.15:36:17.84#ibcon#read 6, iclass 18, count 0 2006.173.15:36:17.84#ibcon#end of sib2, iclass 18, count 0 2006.173.15:36:17.84#ibcon#*after write, iclass 18, count 0 2006.173.15:36:17.84#ibcon#*before return 0, iclass 18, count 0 2006.173.15:36:17.84#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.15:36:17.84#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.15:36:17.84#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.15:36:17.84#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.15:36:17.84$vck44/va=3,5 2006.173.15:36:17.84#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.15:36:17.84#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.15:36:17.84#ibcon#ireg 11 cls_cnt 2 2006.173.15:36:17.84#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.15:36:17.90#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.15:36:17.90#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.15:36:17.90#ibcon#enter wrdev, iclass 20, count 2 2006.173.15:36:17.90#ibcon#first serial, iclass 20, count 2 2006.173.15:36:17.90#ibcon#enter sib2, iclass 20, count 2 2006.173.15:36:17.90#ibcon#flushed, iclass 20, count 2 2006.173.15:36:17.90#ibcon#about to write, iclass 20, count 2 2006.173.15:36:17.90#ibcon#wrote, iclass 20, count 2 2006.173.15:36:17.90#ibcon#about to read 3, iclass 20, count 2 2006.173.15:36:17.92#ibcon#read 3, iclass 20, count 2 2006.173.15:36:17.92#ibcon#about to read 4, iclass 20, count 2 2006.173.15:36:17.92#ibcon#read 4, iclass 20, count 2 2006.173.15:36:17.92#ibcon#about to read 5, iclass 20, count 2 2006.173.15:36:17.92#ibcon#read 5, iclass 20, count 2 2006.173.15:36:17.92#ibcon#about to read 6, iclass 20, count 2 2006.173.15:36:17.92#ibcon#read 6, iclass 20, count 2 2006.173.15:36:17.92#ibcon#end of sib2, iclass 20, count 2 2006.173.15:36:17.92#ibcon#*mode == 0, iclass 20, count 2 2006.173.15:36:17.92#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.15:36:17.92#ibcon#[25=AT03-05\r\n] 2006.173.15:36:17.92#ibcon#*before write, iclass 20, count 2 2006.173.15:36:17.92#ibcon#enter sib2, iclass 20, count 2 2006.173.15:36:17.92#ibcon#flushed, iclass 20, count 2 2006.173.15:36:17.92#ibcon#about to write, iclass 20, count 2 2006.173.15:36:17.92#ibcon#wrote, iclass 20, count 2 2006.173.15:36:17.92#ibcon#about to read 3, iclass 20, count 2 2006.173.15:36:17.95#ibcon#read 3, iclass 20, count 2 2006.173.15:36:17.95#ibcon#about to read 4, iclass 20, count 2 2006.173.15:36:17.95#ibcon#read 4, iclass 20, count 2 2006.173.15:36:17.95#ibcon#about to read 5, iclass 20, count 2 2006.173.15:36:17.95#ibcon#read 5, iclass 20, count 2 2006.173.15:36:17.95#ibcon#about to read 6, iclass 20, count 2 2006.173.15:36:17.95#ibcon#read 6, iclass 20, count 2 2006.173.15:36:17.95#ibcon#end of sib2, iclass 20, count 2 2006.173.15:36:17.95#ibcon#*after write, iclass 20, count 2 2006.173.15:36:17.95#ibcon#*before return 0, iclass 20, count 2 2006.173.15:36:17.95#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.15:36:17.95#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.15:36:17.95#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.15:36:17.95#ibcon#ireg 7 cls_cnt 0 2006.173.15:36:17.95#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.15:36:18.07#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.15:36:18.07#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.15:36:18.07#ibcon#enter wrdev, iclass 20, count 0 2006.173.15:36:18.07#ibcon#first serial, iclass 20, count 0 2006.173.15:36:18.07#ibcon#enter sib2, iclass 20, count 0 2006.173.15:36:18.07#ibcon#flushed, iclass 20, count 0 2006.173.15:36:18.07#ibcon#about to write, iclass 20, count 0 2006.173.15:36:18.07#ibcon#wrote, iclass 20, count 0 2006.173.15:36:18.07#ibcon#about to read 3, iclass 20, count 0 2006.173.15:36:18.09#ibcon#read 3, iclass 20, count 0 2006.173.15:36:18.09#ibcon#about to read 4, iclass 20, count 0 2006.173.15:36:18.09#ibcon#read 4, iclass 20, count 0 2006.173.15:36:18.09#ibcon#about to read 5, iclass 20, count 0 2006.173.15:36:18.09#ibcon#read 5, iclass 20, count 0 2006.173.15:36:18.09#ibcon#about to read 6, iclass 20, count 0 2006.173.15:36:18.09#ibcon#read 6, iclass 20, count 0 2006.173.15:36:18.09#ibcon#end of sib2, iclass 20, count 0 2006.173.15:36:18.09#ibcon#*mode == 0, iclass 20, count 0 2006.173.15:36:18.09#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.15:36:18.09#ibcon#[25=USB\r\n] 2006.173.15:36:18.09#ibcon#*before write, iclass 20, count 0 2006.173.15:36:18.09#ibcon#enter sib2, iclass 20, count 0 2006.173.15:36:18.09#ibcon#flushed, iclass 20, count 0 2006.173.15:36:18.09#ibcon#about to write, iclass 20, count 0 2006.173.15:36:18.09#ibcon#wrote, iclass 20, count 0 2006.173.15:36:18.09#ibcon#about to read 3, iclass 20, count 0 2006.173.15:36:18.12#ibcon#read 3, iclass 20, count 0 2006.173.15:36:18.12#ibcon#about to read 4, iclass 20, count 0 2006.173.15:36:18.12#ibcon#read 4, iclass 20, count 0 2006.173.15:36:18.12#ibcon#about to read 5, iclass 20, count 0 2006.173.15:36:18.12#ibcon#read 5, iclass 20, count 0 2006.173.15:36:18.12#ibcon#about to read 6, iclass 20, count 0 2006.173.15:36:18.12#ibcon#read 6, iclass 20, count 0 2006.173.15:36:18.12#ibcon#end of sib2, iclass 20, count 0 2006.173.15:36:18.12#ibcon#*after write, iclass 20, count 0 2006.173.15:36:18.12#ibcon#*before return 0, iclass 20, count 0 2006.173.15:36:18.12#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.15:36:18.12#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.15:36:18.12#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.15:36:18.12#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.15:36:18.12$vck44/valo=4,624.99 2006.173.15:36:18.12#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.15:36:18.12#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.15:36:18.12#ibcon#ireg 17 cls_cnt 0 2006.173.15:36:18.12#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.15:36:18.12#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.15:36:18.12#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.15:36:18.12#ibcon#enter wrdev, iclass 22, count 0 2006.173.15:36:18.12#ibcon#first serial, iclass 22, count 0 2006.173.15:36:18.12#ibcon#enter sib2, iclass 22, count 0 2006.173.15:36:18.12#ibcon#flushed, iclass 22, count 0 2006.173.15:36:18.12#ibcon#about to write, iclass 22, count 0 2006.173.15:36:18.12#ibcon#wrote, iclass 22, count 0 2006.173.15:36:18.12#ibcon#about to read 3, iclass 22, count 0 2006.173.15:36:18.14#ibcon#read 3, iclass 22, count 0 2006.173.15:36:18.14#ibcon#about to read 4, iclass 22, count 0 2006.173.15:36:18.14#ibcon#read 4, iclass 22, count 0 2006.173.15:36:18.14#ibcon#about to read 5, iclass 22, count 0 2006.173.15:36:18.14#ibcon#read 5, iclass 22, count 0 2006.173.15:36:18.14#ibcon#about to read 6, iclass 22, count 0 2006.173.15:36:18.14#ibcon#read 6, iclass 22, count 0 2006.173.15:36:18.14#ibcon#end of sib2, iclass 22, count 0 2006.173.15:36:18.14#ibcon#*mode == 0, iclass 22, count 0 2006.173.15:36:18.14#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.15:36:18.14#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.15:36:18.14#ibcon#*before write, iclass 22, count 0 2006.173.15:36:18.14#ibcon#enter sib2, iclass 22, count 0 2006.173.15:36:18.14#ibcon#flushed, iclass 22, count 0 2006.173.15:36:18.14#ibcon#about to write, iclass 22, count 0 2006.173.15:36:18.14#ibcon#wrote, iclass 22, count 0 2006.173.15:36:18.14#ibcon#about to read 3, iclass 22, count 0 2006.173.15:36:18.18#ibcon#read 3, iclass 22, count 0 2006.173.15:36:18.18#ibcon#about to read 4, iclass 22, count 0 2006.173.15:36:18.18#ibcon#read 4, iclass 22, count 0 2006.173.15:36:18.18#ibcon#about to read 5, iclass 22, count 0 2006.173.15:36:18.18#ibcon#read 5, iclass 22, count 0 2006.173.15:36:18.18#ibcon#about to read 6, iclass 22, count 0 2006.173.15:36:18.18#ibcon#read 6, iclass 22, count 0 2006.173.15:36:18.18#ibcon#end of sib2, iclass 22, count 0 2006.173.15:36:18.18#ibcon#*after write, iclass 22, count 0 2006.173.15:36:18.18#ibcon#*before return 0, iclass 22, count 0 2006.173.15:36:18.18#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.15:36:18.18#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.15:36:18.18#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.15:36:18.18#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.15:36:18.18$vck44/va=4,6 2006.173.15:36:18.18#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.15:36:18.18#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.15:36:18.18#ibcon#ireg 11 cls_cnt 2 2006.173.15:36:18.18#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.15:36:18.24#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.15:36:18.24#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.15:36:18.24#ibcon#enter wrdev, iclass 24, count 2 2006.173.15:36:18.24#ibcon#first serial, iclass 24, count 2 2006.173.15:36:18.24#ibcon#enter sib2, iclass 24, count 2 2006.173.15:36:18.24#ibcon#flushed, iclass 24, count 2 2006.173.15:36:18.24#ibcon#about to write, iclass 24, count 2 2006.173.15:36:18.24#ibcon#wrote, iclass 24, count 2 2006.173.15:36:18.24#ibcon#about to read 3, iclass 24, count 2 2006.173.15:36:18.26#ibcon#read 3, iclass 24, count 2 2006.173.15:36:18.26#ibcon#about to read 4, iclass 24, count 2 2006.173.15:36:18.26#ibcon#read 4, iclass 24, count 2 2006.173.15:36:18.26#ibcon#about to read 5, iclass 24, count 2 2006.173.15:36:18.26#ibcon#read 5, iclass 24, count 2 2006.173.15:36:18.26#ibcon#about to read 6, iclass 24, count 2 2006.173.15:36:18.26#ibcon#read 6, iclass 24, count 2 2006.173.15:36:18.26#ibcon#end of sib2, iclass 24, count 2 2006.173.15:36:18.26#ibcon#*mode == 0, iclass 24, count 2 2006.173.15:36:18.26#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.15:36:18.26#ibcon#[25=AT04-06\r\n] 2006.173.15:36:18.26#ibcon#*before write, iclass 24, count 2 2006.173.15:36:18.26#ibcon#enter sib2, iclass 24, count 2 2006.173.15:36:18.26#ibcon#flushed, iclass 24, count 2 2006.173.15:36:18.26#ibcon#about to write, iclass 24, count 2 2006.173.15:36:18.26#ibcon#wrote, iclass 24, count 2 2006.173.15:36:18.26#ibcon#about to read 3, iclass 24, count 2 2006.173.15:36:18.29#ibcon#read 3, iclass 24, count 2 2006.173.15:36:18.29#ibcon#about to read 4, iclass 24, count 2 2006.173.15:36:18.29#ibcon#read 4, iclass 24, count 2 2006.173.15:36:18.29#ibcon#about to read 5, iclass 24, count 2 2006.173.15:36:18.29#ibcon#read 5, iclass 24, count 2 2006.173.15:36:18.29#ibcon#about to read 6, iclass 24, count 2 2006.173.15:36:18.29#ibcon#read 6, iclass 24, count 2 2006.173.15:36:18.29#ibcon#end of sib2, iclass 24, count 2 2006.173.15:36:18.29#ibcon#*after write, iclass 24, count 2 2006.173.15:36:18.29#ibcon#*before return 0, iclass 24, count 2 2006.173.15:36:18.29#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.15:36:18.29#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.15:36:18.29#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.15:36:18.29#ibcon#ireg 7 cls_cnt 0 2006.173.15:36:18.29#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.15:36:18.41#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.15:36:18.41#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.15:36:18.41#ibcon#enter wrdev, iclass 24, count 0 2006.173.15:36:18.41#ibcon#first serial, iclass 24, count 0 2006.173.15:36:18.41#ibcon#enter sib2, iclass 24, count 0 2006.173.15:36:18.41#ibcon#flushed, iclass 24, count 0 2006.173.15:36:18.41#ibcon#about to write, iclass 24, count 0 2006.173.15:36:18.41#ibcon#wrote, iclass 24, count 0 2006.173.15:36:18.41#ibcon#about to read 3, iclass 24, count 0 2006.173.15:36:18.43#ibcon#read 3, iclass 24, count 0 2006.173.15:36:18.43#ibcon#about to read 4, iclass 24, count 0 2006.173.15:36:18.43#ibcon#read 4, iclass 24, count 0 2006.173.15:36:18.43#ibcon#about to read 5, iclass 24, count 0 2006.173.15:36:18.43#ibcon#read 5, iclass 24, count 0 2006.173.15:36:18.43#ibcon#about to read 6, iclass 24, count 0 2006.173.15:36:18.43#ibcon#read 6, iclass 24, count 0 2006.173.15:36:18.43#ibcon#end of sib2, iclass 24, count 0 2006.173.15:36:18.43#ibcon#*mode == 0, iclass 24, count 0 2006.173.15:36:18.43#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.15:36:18.43#ibcon#[25=USB\r\n] 2006.173.15:36:18.43#ibcon#*before write, iclass 24, count 0 2006.173.15:36:18.43#ibcon#enter sib2, iclass 24, count 0 2006.173.15:36:18.43#ibcon#flushed, iclass 24, count 0 2006.173.15:36:18.43#ibcon#about to write, iclass 24, count 0 2006.173.15:36:18.43#ibcon#wrote, iclass 24, count 0 2006.173.15:36:18.43#ibcon#about to read 3, iclass 24, count 0 2006.173.15:36:18.46#ibcon#read 3, iclass 24, count 0 2006.173.15:36:18.46#ibcon#about to read 4, iclass 24, count 0 2006.173.15:36:18.46#ibcon#read 4, iclass 24, count 0 2006.173.15:36:18.46#ibcon#about to read 5, iclass 24, count 0 2006.173.15:36:18.46#ibcon#read 5, iclass 24, count 0 2006.173.15:36:18.46#ibcon#about to read 6, iclass 24, count 0 2006.173.15:36:18.46#ibcon#read 6, iclass 24, count 0 2006.173.15:36:18.46#ibcon#end of sib2, iclass 24, count 0 2006.173.15:36:18.46#ibcon#*after write, iclass 24, count 0 2006.173.15:36:18.46#ibcon#*before return 0, iclass 24, count 0 2006.173.15:36:18.46#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.15:36:18.46#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.15:36:18.46#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.15:36:18.46#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.15:36:18.46$vck44/valo=5,734.99 2006.173.15:36:18.46#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.15:36:18.46#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.15:36:18.46#ibcon#ireg 17 cls_cnt 0 2006.173.15:36:18.46#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.15:36:18.46#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.15:36:18.46#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.15:36:18.46#ibcon#enter wrdev, iclass 26, count 0 2006.173.15:36:18.46#ibcon#first serial, iclass 26, count 0 2006.173.15:36:18.46#ibcon#enter sib2, iclass 26, count 0 2006.173.15:36:18.46#ibcon#flushed, iclass 26, count 0 2006.173.15:36:18.46#ibcon#about to write, iclass 26, count 0 2006.173.15:36:18.46#ibcon#wrote, iclass 26, count 0 2006.173.15:36:18.46#ibcon#about to read 3, iclass 26, count 0 2006.173.15:36:18.48#ibcon#read 3, iclass 26, count 0 2006.173.15:36:18.48#ibcon#about to read 4, iclass 26, count 0 2006.173.15:36:18.48#ibcon#read 4, iclass 26, count 0 2006.173.15:36:18.48#ibcon#about to read 5, iclass 26, count 0 2006.173.15:36:18.48#ibcon#read 5, iclass 26, count 0 2006.173.15:36:18.48#ibcon#about to read 6, iclass 26, count 0 2006.173.15:36:18.48#ibcon#read 6, iclass 26, count 0 2006.173.15:36:18.48#ibcon#end of sib2, iclass 26, count 0 2006.173.15:36:18.48#ibcon#*mode == 0, iclass 26, count 0 2006.173.15:36:18.48#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.15:36:18.48#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.15:36:18.48#ibcon#*before write, iclass 26, count 0 2006.173.15:36:18.48#ibcon#enter sib2, iclass 26, count 0 2006.173.15:36:18.48#ibcon#flushed, iclass 26, count 0 2006.173.15:36:18.48#ibcon#about to write, iclass 26, count 0 2006.173.15:36:18.48#ibcon#wrote, iclass 26, count 0 2006.173.15:36:18.48#ibcon#about to read 3, iclass 26, count 0 2006.173.15:36:18.52#ibcon#read 3, iclass 26, count 0 2006.173.15:36:18.52#ibcon#about to read 4, iclass 26, count 0 2006.173.15:36:18.52#ibcon#read 4, iclass 26, count 0 2006.173.15:36:18.52#ibcon#about to read 5, iclass 26, count 0 2006.173.15:36:18.52#ibcon#read 5, iclass 26, count 0 2006.173.15:36:18.52#ibcon#about to read 6, iclass 26, count 0 2006.173.15:36:18.52#ibcon#read 6, iclass 26, count 0 2006.173.15:36:18.52#ibcon#end of sib2, iclass 26, count 0 2006.173.15:36:18.52#ibcon#*after write, iclass 26, count 0 2006.173.15:36:18.52#ibcon#*before return 0, iclass 26, count 0 2006.173.15:36:18.52#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.15:36:18.52#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.15:36:18.52#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.15:36:18.52#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.15:36:18.52$vck44/va=5,4 2006.173.15:36:18.52#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.15:36:18.52#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.15:36:18.52#ibcon#ireg 11 cls_cnt 2 2006.173.15:36:18.52#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.15:36:18.58#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.15:36:18.58#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.15:36:18.58#ibcon#enter wrdev, iclass 28, count 2 2006.173.15:36:18.58#ibcon#first serial, iclass 28, count 2 2006.173.15:36:18.58#ibcon#enter sib2, iclass 28, count 2 2006.173.15:36:18.58#ibcon#flushed, iclass 28, count 2 2006.173.15:36:18.58#ibcon#about to write, iclass 28, count 2 2006.173.15:36:18.58#ibcon#wrote, iclass 28, count 2 2006.173.15:36:18.58#ibcon#about to read 3, iclass 28, count 2 2006.173.15:36:18.60#ibcon#read 3, iclass 28, count 2 2006.173.15:36:18.60#ibcon#about to read 4, iclass 28, count 2 2006.173.15:36:18.60#ibcon#read 4, iclass 28, count 2 2006.173.15:36:18.60#ibcon#about to read 5, iclass 28, count 2 2006.173.15:36:18.60#ibcon#read 5, iclass 28, count 2 2006.173.15:36:18.60#ibcon#about to read 6, iclass 28, count 2 2006.173.15:36:18.60#ibcon#read 6, iclass 28, count 2 2006.173.15:36:18.60#ibcon#end of sib2, iclass 28, count 2 2006.173.15:36:18.60#ibcon#*mode == 0, iclass 28, count 2 2006.173.15:36:18.60#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.15:36:18.60#ibcon#[25=AT05-04\r\n] 2006.173.15:36:18.60#ibcon#*before write, iclass 28, count 2 2006.173.15:36:18.60#ibcon#enter sib2, iclass 28, count 2 2006.173.15:36:18.60#ibcon#flushed, iclass 28, count 2 2006.173.15:36:18.60#ibcon#about to write, iclass 28, count 2 2006.173.15:36:18.60#ibcon#wrote, iclass 28, count 2 2006.173.15:36:18.60#ibcon#about to read 3, iclass 28, count 2 2006.173.15:36:18.63#ibcon#read 3, iclass 28, count 2 2006.173.15:36:18.63#ibcon#about to read 4, iclass 28, count 2 2006.173.15:36:18.63#ibcon#read 4, iclass 28, count 2 2006.173.15:36:18.63#ibcon#about to read 5, iclass 28, count 2 2006.173.15:36:18.63#ibcon#read 5, iclass 28, count 2 2006.173.15:36:18.63#ibcon#about to read 6, iclass 28, count 2 2006.173.15:36:18.63#ibcon#read 6, iclass 28, count 2 2006.173.15:36:18.63#ibcon#end of sib2, iclass 28, count 2 2006.173.15:36:18.63#ibcon#*after write, iclass 28, count 2 2006.173.15:36:18.63#ibcon#*before return 0, iclass 28, count 2 2006.173.15:36:18.63#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.15:36:18.63#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.15:36:18.63#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.15:36:18.63#ibcon#ireg 7 cls_cnt 0 2006.173.15:36:18.63#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.15:36:18.75#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.15:36:18.75#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.15:36:18.75#ibcon#enter wrdev, iclass 28, count 0 2006.173.15:36:18.75#ibcon#first serial, iclass 28, count 0 2006.173.15:36:18.75#ibcon#enter sib2, iclass 28, count 0 2006.173.15:36:18.75#ibcon#flushed, iclass 28, count 0 2006.173.15:36:18.75#ibcon#about to write, iclass 28, count 0 2006.173.15:36:18.75#ibcon#wrote, iclass 28, count 0 2006.173.15:36:18.75#ibcon#about to read 3, iclass 28, count 0 2006.173.15:36:18.77#ibcon#read 3, iclass 28, count 0 2006.173.15:36:18.77#ibcon#about to read 4, iclass 28, count 0 2006.173.15:36:18.77#ibcon#read 4, iclass 28, count 0 2006.173.15:36:18.77#ibcon#about to read 5, iclass 28, count 0 2006.173.15:36:18.77#ibcon#read 5, iclass 28, count 0 2006.173.15:36:18.77#ibcon#about to read 6, iclass 28, count 0 2006.173.15:36:18.77#ibcon#read 6, iclass 28, count 0 2006.173.15:36:18.77#ibcon#end of sib2, iclass 28, count 0 2006.173.15:36:18.77#ibcon#*mode == 0, iclass 28, count 0 2006.173.15:36:18.77#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.15:36:18.77#ibcon#[25=USB\r\n] 2006.173.15:36:18.77#ibcon#*before write, iclass 28, count 0 2006.173.15:36:18.77#ibcon#enter sib2, iclass 28, count 0 2006.173.15:36:18.77#ibcon#flushed, iclass 28, count 0 2006.173.15:36:18.77#ibcon#about to write, iclass 28, count 0 2006.173.15:36:18.77#ibcon#wrote, iclass 28, count 0 2006.173.15:36:18.77#ibcon#about to read 3, iclass 28, count 0 2006.173.15:36:18.80#ibcon#read 3, iclass 28, count 0 2006.173.15:36:18.80#ibcon#about to read 4, iclass 28, count 0 2006.173.15:36:18.80#ibcon#read 4, iclass 28, count 0 2006.173.15:36:18.80#ibcon#about to read 5, iclass 28, count 0 2006.173.15:36:18.80#ibcon#read 5, iclass 28, count 0 2006.173.15:36:18.80#ibcon#about to read 6, iclass 28, count 0 2006.173.15:36:18.80#ibcon#read 6, iclass 28, count 0 2006.173.15:36:18.80#ibcon#end of sib2, iclass 28, count 0 2006.173.15:36:18.80#ibcon#*after write, iclass 28, count 0 2006.173.15:36:18.80#ibcon#*before return 0, iclass 28, count 0 2006.173.15:36:18.80#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.15:36:18.80#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.15:36:18.80#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.15:36:18.80#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.15:36:18.80$vck44/valo=6,814.99 2006.173.15:36:18.80#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.15:36:18.80#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.15:36:18.80#ibcon#ireg 17 cls_cnt 0 2006.173.15:36:18.80#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.15:36:18.80#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.15:36:18.80#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.15:36:18.80#ibcon#enter wrdev, iclass 30, count 0 2006.173.15:36:18.80#ibcon#first serial, iclass 30, count 0 2006.173.15:36:18.80#ibcon#enter sib2, iclass 30, count 0 2006.173.15:36:18.80#ibcon#flushed, iclass 30, count 0 2006.173.15:36:18.80#ibcon#about to write, iclass 30, count 0 2006.173.15:36:18.80#ibcon#wrote, iclass 30, count 0 2006.173.15:36:18.80#ibcon#about to read 3, iclass 30, count 0 2006.173.15:36:18.82#ibcon#read 3, iclass 30, count 0 2006.173.15:36:18.82#ibcon#about to read 4, iclass 30, count 0 2006.173.15:36:18.82#ibcon#read 4, iclass 30, count 0 2006.173.15:36:18.82#ibcon#about to read 5, iclass 30, count 0 2006.173.15:36:18.82#ibcon#read 5, iclass 30, count 0 2006.173.15:36:18.82#ibcon#about to read 6, iclass 30, count 0 2006.173.15:36:18.82#ibcon#read 6, iclass 30, count 0 2006.173.15:36:18.82#ibcon#end of sib2, iclass 30, count 0 2006.173.15:36:18.82#ibcon#*mode == 0, iclass 30, count 0 2006.173.15:36:18.82#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.15:36:18.82#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.15:36:18.82#ibcon#*before write, iclass 30, count 0 2006.173.15:36:18.82#ibcon#enter sib2, iclass 30, count 0 2006.173.15:36:18.82#ibcon#flushed, iclass 30, count 0 2006.173.15:36:18.82#ibcon#about to write, iclass 30, count 0 2006.173.15:36:18.82#ibcon#wrote, iclass 30, count 0 2006.173.15:36:18.82#ibcon#about to read 3, iclass 30, count 0 2006.173.15:36:18.86#ibcon#read 3, iclass 30, count 0 2006.173.15:36:18.86#ibcon#about to read 4, iclass 30, count 0 2006.173.15:36:18.86#ibcon#read 4, iclass 30, count 0 2006.173.15:36:18.86#ibcon#about to read 5, iclass 30, count 0 2006.173.15:36:18.86#ibcon#read 5, iclass 30, count 0 2006.173.15:36:18.86#ibcon#about to read 6, iclass 30, count 0 2006.173.15:36:18.86#ibcon#read 6, iclass 30, count 0 2006.173.15:36:18.86#ibcon#end of sib2, iclass 30, count 0 2006.173.15:36:18.86#ibcon#*after write, iclass 30, count 0 2006.173.15:36:18.86#ibcon#*before return 0, iclass 30, count 0 2006.173.15:36:18.86#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.15:36:18.86#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.15:36:18.86#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.15:36:18.86#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.15:36:18.86$vck44/va=6,3 2006.173.15:36:18.86#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.173.15:36:18.86#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.173.15:36:18.86#ibcon#ireg 11 cls_cnt 2 2006.173.15:36:18.86#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.15:36:18.92#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.15:36:18.92#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.15:36:18.92#ibcon#enter wrdev, iclass 32, count 2 2006.173.15:36:18.92#ibcon#first serial, iclass 32, count 2 2006.173.15:36:18.92#ibcon#enter sib2, iclass 32, count 2 2006.173.15:36:18.92#ibcon#flushed, iclass 32, count 2 2006.173.15:36:18.92#ibcon#about to write, iclass 32, count 2 2006.173.15:36:18.92#ibcon#wrote, iclass 32, count 2 2006.173.15:36:18.92#ibcon#about to read 3, iclass 32, count 2 2006.173.15:36:18.94#ibcon#read 3, iclass 32, count 2 2006.173.15:36:18.94#ibcon#about to read 4, iclass 32, count 2 2006.173.15:36:18.94#ibcon#read 4, iclass 32, count 2 2006.173.15:36:18.94#ibcon#about to read 5, iclass 32, count 2 2006.173.15:36:18.94#ibcon#read 5, iclass 32, count 2 2006.173.15:36:18.94#ibcon#about to read 6, iclass 32, count 2 2006.173.15:36:18.94#ibcon#read 6, iclass 32, count 2 2006.173.15:36:18.94#ibcon#end of sib2, iclass 32, count 2 2006.173.15:36:18.94#ibcon#*mode == 0, iclass 32, count 2 2006.173.15:36:18.94#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.173.15:36:18.94#ibcon#[25=AT06-03\r\n] 2006.173.15:36:18.94#ibcon#*before write, iclass 32, count 2 2006.173.15:36:18.94#ibcon#enter sib2, iclass 32, count 2 2006.173.15:36:18.94#ibcon#flushed, iclass 32, count 2 2006.173.15:36:18.94#ibcon#about to write, iclass 32, count 2 2006.173.15:36:18.94#ibcon#wrote, iclass 32, count 2 2006.173.15:36:18.94#ibcon#about to read 3, iclass 32, count 2 2006.173.15:36:18.97#ibcon#read 3, iclass 32, count 2 2006.173.15:36:18.97#ibcon#about to read 4, iclass 32, count 2 2006.173.15:36:18.97#ibcon#read 4, iclass 32, count 2 2006.173.15:36:18.97#ibcon#about to read 5, iclass 32, count 2 2006.173.15:36:18.97#ibcon#read 5, iclass 32, count 2 2006.173.15:36:18.97#ibcon#about to read 6, iclass 32, count 2 2006.173.15:36:18.97#ibcon#read 6, iclass 32, count 2 2006.173.15:36:18.97#ibcon#end of sib2, iclass 32, count 2 2006.173.15:36:18.97#ibcon#*after write, iclass 32, count 2 2006.173.15:36:18.97#ibcon#*before return 0, iclass 32, count 2 2006.173.15:36:18.97#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.15:36:18.97#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.173.15:36:18.97#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.173.15:36:18.97#ibcon#ireg 7 cls_cnt 0 2006.173.15:36:18.97#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.15:36:19.09#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.15:36:19.09#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.15:36:19.09#ibcon#enter wrdev, iclass 32, count 0 2006.173.15:36:19.09#ibcon#first serial, iclass 32, count 0 2006.173.15:36:19.09#ibcon#enter sib2, iclass 32, count 0 2006.173.15:36:19.09#ibcon#flushed, iclass 32, count 0 2006.173.15:36:19.09#ibcon#about to write, iclass 32, count 0 2006.173.15:36:19.09#ibcon#wrote, iclass 32, count 0 2006.173.15:36:19.09#ibcon#about to read 3, iclass 32, count 0 2006.173.15:36:19.11#ibcon#read 3, iclass 32, count 0 2006.173.15:36:19.11#ibcon#about to read 4, iclass 32, count 0 2006.173.15:36:19.11#ibcon#read 4, iclass 32, count 0 2006.173.15:36:19.11#ibcon#about to read 5, iclass 32, count 0 2006.173.15:36:19.11#ibcon#read 5, iclass 32, count 0 2006.173.15:36:19.11#ibcon#about to read 6, iclass 32, count 0 2006.173.15:36:19.11#ibcon#read 6, iclass 32, count 0 2006.173.15:36:19.11#ibcon#end of sib2, iclass 32, count 0 2006.173.15:36:19.11#ibcon#*mode == 0, iclass 32, count 0 2006.173.15:36:19.11#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.15:36:19.11#ibcon#[25=USB\r\n] 2006.173.15:36:19.11#ibcon#*before write, iclass 32, count 0 2006.173.15:36:19.11#ibcon#enter sib2, iclass 32, count 0 2006.173.15:36:19.11#ibcon#flushed, iclass 32, count 0 2006.173.15:36:19.11#ibcon#about to write, iclass 32, count 0 2006.173.15:36:19.11#ibcon#wrote, iclass 32, count 0 2006.173.15:36:19.11#ibcon#about to read 3, iclass 32, count 0 2006.173.15:36:19.14#ibcon#read 3, iclass 32, count 0 2006.173.15:36:19.14#ibcon#about to read 4, iclass 32, count 0 2006.173.15:36:19.14#ibcon#read 4, iclass 32, count 0 2006.173.15:36:19.14#ibcon#about to read 5, iclass 32, count 0 2006.173.15:36:19.14#ibcon#read 5, iclass 32, count 0 2006.173.15:36:19.14#ibcon#about to read 6, iclass 32, count 0 2006.173.15:36:19.14#ibcon#read 6, iclass 32, count 0 2006.173.15:36:19.14#ibcon#end of sib2, iclass 32, count 0 2006.173.15:36:19.14#ibcon#*after write, iclass 32, count 0 2006.173.15:36:19.14#ibcon#*before return 0, iclass 32, count 0 2006.173.15:36:19.14#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.15:36:19.14#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.173.15:36:19.14#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.15:36:19.14#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.15:36:19.14$vck44/valo=7,864.99 2006.173.15:36:19.14#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.15:36:19.14#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.15:36:19.14#ibcon#ireg 17 cls_cnt 0 2006.173.15:36:19.14#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.15:36:19.14#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.15:36:19.14#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.15:36:19.14#ibcon#enter wrdev, iclass 34, count 0 2006.173.15:36:19.14#ibcon#first serial, iclass 34, count 0 2006.173.15:36:19.14#ibcon#enter sib2, iclass 34, count 0 2006.173.15:36:19.14#ibcon#flushed, iclass 34, count 0 2006.173.15:36:19.14#ibcon#about to write, iclass 34, count 0 2006.173.15:36:19.14#ibcon#wrote, iclass 34, count 0 2006.173.15:36:19.14#ibcon#about to read 3, iclass 34, count 0 2006.173.15:36:19.16#ibcon#read 3, iclass 34, count 0 2006.173.15:36:19.16#ibcon#about to read 4, iclass 34, count 0 2006.173.15:36:19.16#ibcon#read 4, iclass 34, count 0 2006.173.15:36:19.16#ibcon#about to read 5, iclass 34, count 0 2006.173.15:36:19.16#ibcon#read 5, iclass 34, count 0 2006.173.15:36:19.16#ibcon#about to read 6, iclass 34, count 0 2006.173.15:36:19.16#ibcon#read 6, iclass 34, count 0 2006.173.15:36:19.16#ibcon#end of sib2, iclass 34, count 0 2006.173.15:36:19.16#ibcon#*mode == 0, iclass 34, count 0 2006.173.15:36:19.16#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.15:36:19.16#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.15:36:19.16#ibcon#*before write, iclass 34, count 0 2006.173.15:36:19.16#ibcon#enter sib2, iclass 34, count 0 2006.173.15:36:19.16#ibcon#flushed, iclass 34, count 0 2006.173.15:36:19.16#ibcon#about to write, iclass 34, count 0 2006.173.15:36:19.16#ibcon#wrote, iclass 34, count 0 2006.173.15:36:19.16#ibcon#about to read 3, iclass 34, count 0 2006.173.15:36:19.20#ibcon#read 3, iclass 34, count 0 2006.173.15:36:19.20#ibcon#about to read 4, iclass 34, count 0 2006.173.15:36:19.20#ibcon#read 4, iclass 34, count 0 2006.173.15:36:19.20#ibcon#about to read 5, iclass 34, count 0 2006.173.15:36:19.20#ibcon#read 5, iclass 34, count 0 2006.173.15:36:19.20#ibcon#about to read 6, iclass 34, count 0 2006.173.15:36:19.20#ibcon#read 6, iclass 34, count 0 2006.173.15:36:19.20#ibcon#end of sib2, iclass 34, count 0 2006.173.15:36:19.20#ibcon#*after write, iclass 34, count 0 2006.173.15:36:19.20#ibcon#*before return 0, iclass 34, count 0 2006.173.15:36:19.20#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.15:36:19.20#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.15:36:19.20#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.15:36:19.20#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.15:36:19.20$vck44/va=7,4 2006.173.15:36:19.20#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.15:36:19.20#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.15:36:19.20#ibcon#ireg 11 cls_cnt 2 2006.173.15:36:19.20#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.15:36:19.26#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.15:36:19.26#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.15:36:19.26#ibcon#enter wrdev, iclass 36, count 2 2006.173.15:36:19.26#ibcon#first serial, iclass 36, count 2 2006.173.15:36:19.26#ibcon#enter sib2, iclass 36, count 2 2006.173.15:36:19.26#ibcon#flushed, iclass 36, count 2 2006.173.15:36:19.26#ibcon#about to write, iclass 36, count 2 2006.173.15:36:19.26#ibcon#wrote, iclass 36, count 2 2006.173.15:36:19.26#ibcon#about to read 3, iclass 36, count 2 2006.173.15:36:19.28#ibcon#read 3, iclass 36, count 2 2006.173.15:36:19.28#ibcon#about to read 4, iclass 36, count 2 2006.173.15:36:19.28#ibcon#read 4, iclass 36, count 2 2006.173.15:36:19.28#ibcon#about to read 5, iclass 36, count 2 2006.173.15:36:19.28#ibcon#read 5, iclass 36, count 2 2006.173.15:36:19.28#ibcon#about to read 6, iclass 36, count 2 2006.173.15:36:19.28#ibcon#read 6, iclass 36, count 2 2006.173.15:36:19.28#ibcon#end of sib2, iclass 36, count 2 2006.173.15:36:19.28#ibcon#*mode == 0, iclass 36, count 2 2006.173.15:36:19.28#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.15:36:19.28#ibcon#[25=AT07-04\r\n] 2006.173.15:36:19.28#ibcon#*before write, iclass 36, count 2 2006.173.15:36:19.28#ibcon#enter sib2, iclass 36, count 2 2006.173.15:36:19.28#ibcon#flushed, iclass 36, count 2 2006.173.15:36:19.28#ibcon#about to write, iclass 36, count 2 2006.173.15:36:19.28#ibcon#wrote, iclass 36, count 2 2006.173.15:36:19.28#ibcon#about to read 3, iclass 36, count 2 2006.173.15:36:19.31#ibcon#read 3, iclass 36, count 2 2006.173.15:36:19.31#ibcon#about to read 4, iclass 36, count 2 2006.173.15:36:19.31#ibcon#read 4, iclass 36, count 2 2006.173.15:36:19.31#ibcon#about to read 5, iclass 36, count 2 2006.173.15:36:19.31#ibcon#read 5, iclass 36, count 2 2006.173.15:36:19.31#ibcon#about to read 6, iclass 36, count 2 2006.173.15:36:19.31#ibcon#read 6, iclass 36, count 2 2006.173.15:36:19.31#ibcon#end of sib2, iclass 36, count 2 2006.173.15:36:19.31#ibcon#*after write, iclass 36, count 2 2006.173.15:36:19.31#ibcon#*before return 0, iclass 36, count 2 2006.173.15:36:19.31#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.15:36:19.31#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.15:36:19.31#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.15:36:19.31#ibcon#ireg 7 cls_cnt 0 2006.173.15:36:19.31#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.15:36:19.43#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.15:36:19.43#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.15:36:19.43#ibcon#enter wrdev, iclass 36, count 0 2006.173.15:36:19.43#ibcon#first serial, iclass 36, count 0 2006.173.15:36:19.43#ibcon#enter sib2, iclass 36, count 0 2006.173.15:36:19.43#ibcon#flushed, iclass 36, count 0 2006.173.15:36:19.43#ibcon#about to write, iclass 36, count 0 2006.173.15:36:19.43#ibcon#wrote, iclass 36, count 0 2006.173.15:36:19.43#ibcon#about to read 3, iclass 36, count 0 2006.173.15:36:19.45#ibcon#read 3, iclass 36, count 0 2006.173.15:36:19.45#ibcon#about to read 4, iclass 36, count 0 2006.173.15:36:19.45#ibcon#read 4, iclass 36, count 0 2006.173.15:36:19.45#ibcon#about to read 5, iclass 36, count 0 2006.173.15:36:19.45#ibcon#read 5, iclass 36, count 0 2006.173.15:36:19.45#ibcon#about to read 6, iclass 36, count 0 2006.173.15:36:19.45#ibcon#read 6, iclass 36, count 0 2006.173.15:36:19.45#ibcon#end of sib2, iclass 36, count 0 2006.173.15:36:19.45#ibcon#*mode == 0, iclass 36, count 0 2006.173.15:36:19.45#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.15:36:19.45#ibcon#[25=USB\r\n] 2006.173.15:36:19.45#ibcon#*before write, iclass 36, count 0 2006.173.15:36:19.45#ibcon#enter sib2, iclass 36, count 0 2006.173.15:36:19.45#ibcon#flushed, iclass 36, count 0 2006.173.15:36:19.45#ibcon#about to write, iclass 36, count 0 2006.173.15:36:19.45#ibcon#wrote, iclass 36, count 0 2006.173.15:36:19.45#ibcon#about to read 3, iclass 36, count 0 2006.173.15:36:19.48#ibcon#read 3, iclass 36, count 0 2006.173.15:36:19.48#ibcon#about to read 4, iclass 36, count 0 2006.173.15:36:19.48#ibcon#read 4, iclass 36, count 0 2006.173.15:36:19.48#ibcon#about to read 5, iclass 36, count 0 2006.173.15:36:19.48#ibcon#read 5, iclass 36, count 0 2006.173.15:36:19.48#ibcon#about to read 6, iclass 36, count 0 2006.173.15:36:19.48#ibcon#read 6, iclass 36, count 0 2006.173.15:36:19.48#ibcon#end of sib2, iclass 36, count 0 2006.173.15:36:19.48#ibcon#*after write, iclass 36, count 0 2006.173.15:36:19.48#ibcon#*before return 0, iclass 36, count 0 2006.173.15:36:19.48#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.15:36:19.48#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.15:36:19.48#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.15:36:19.48#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.15:36:19.48$vck44/valo=8,884.99 2006.173.15:36:19.48#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.15:36:19.48#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.15:36:19.48#ibcon#ireg 17 cls_cnt 0 2006.173.15:36:19.48#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.15:36:19.48#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.15:36:19.48#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.15:36:19.48#ibcon#enter wrdev, iclass 38, count 0 2006.173.15:36:19.48#ibcon#first serial, iclass 38, count 0 2006.173.15:36:19.48#ibcon#enter sib2, iclass 38, count 0 2006.173.15:36:19.48#ibcon#flushed, iclass 38, count 0 2006.173.15:36:19.48#ibcon#about to write, iclass 38, count 0 2006.173.15:36:19.48#ibcon#wrote, iclass 38, count 0 2006.173.15:36:19.48#ibcon#about to read 3, iclass 38, count 0 2006.173.15:36:19.50#ibcon#read 3, iclass 38, count 0 2006.173.15:36:19.50#ibcon#about to read 4, iclass 38, count 0 2006.173.15:36:19.50#ibcon#read 4, iclass 38, count 0 2006.173.15:36:19.50#ibcon#about to read 5, iclass 38, count 0 2006.173.15:36:19.50#ibcon#read 5, iclass 38, count 0 2006.173.15:36:19.50#ibcon#about to read 6, iclass 38, count 0 2006.173.15:36:19.50#ibcon#read 6, iclass 38, count 0 2006.173.15:36:19.50#ibcon#end of sib2, iclass 38, count 0 2006.173.15:36:19.50#ibcon#*mode == 0, iclass 38, count 0 2006.173.15:36:19.50#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.15:36:19.50#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.15:36:19.50#ibcon#*before write, iclass 38, count 0 2006.173.15:36:19.50#ibcon#enter sib2, iclass 38, count 0 2006.173.15:36:19.50#ibcon#flushed, iclass 38, count 0 2006.173.15:36:19.50#ibcon#about to write, iclass 38, count 0 2006.173.15:36:19.50#ibcon#wrote, iclass 38, count 0 2006.173.15:36:19.50#ibcon#about to read 3, iclass 38, count 0 2006.173.15:36:19.54#ibcon#read 3, iclass 38, count 0 2006.173.15:36:19.54#ibcon#about to read 4, iclass 38, count 0 2006.173.15:36:19.54#ibcon#read 4, iclass 38, count 0 2006.173.15:36:19.54#ibcon#about to read 5, iclass 38, count 0 2006.173.15:36:19.54#ibcon#read 5, iclass 38, count 0 2006.173.15:36:19.54#ibcon#about to read 6, iclass 38, count 0 2006.173.15:36:19.54#ibcon#read 6, iclass 38, count 0 2006.173.15:36:19.54#ibcon#end of sib2, iclass 38, count 0 2006.173.15:36:19.54#ibcon#*after write, iclass 38, count 0 2006.173.15:36:19.54#ibcon#*before return 0, iclass 38, count 0 2006.173.15:36:19.54#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.15:36:19.54#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.15:36:19.54#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.15:36:19.54#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.15:36:19.54$vck44/va=8,4 2006.173.15:36:19.54#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.15:36:19.54#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.15:36:19.54#ibcon#ireg 11 cls_cnt 2 2006.173.15:36:19.54#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.15:36:19.60#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.15:36:19.60#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.15:36:19.60#ibcon#enter wrdev, iclass 40, count 2 2006.173.15:36:19.60#ibcon#first serial, iclass 40, count 2 2006.173.15:36:19.60#ibcon#enter sib2, iclass 40, count 2 2006.173.15:36:19.60#ibcon#flushed, iclass 40, count 2 2006.173.15:36:19.60#ibcon#about to write, iclass 40, count 2 2006.173.15:36:19.60#ibcon#wrote, iclass 40, count 2 2006.173.15:36:19.60#ibcon#about to read 3, iclass 40, count 2 2006.173.15:36:19.62#ibcon#read 3, iclass 40, count 2 2006.173.15:36:19.62#ibcon#about to read 4, iclass 40, count 2 2006.173.15:36:19.62#ibcon#read 4, iclass 40, count 2 2006.173.15:36:19.62#ibcon#about to read 5, iclass 40, count 2 2006.173.15:36:19.62#ibcon#read 5, iclass 40, count 2 2006.173.15:36:19.62#ibcon#about to read 6, iclass 40, count 2 2006.173.15:36:19.62#ibcon#read 6, iclass 40, count 2 2006.173.15:36:19.62#ibcon#end of sib2, iclass 40, count 2 2006.173.15:36:19.62#ibcon#*mode == 0, iclass 40, count 2 2006.173.15:36:19.62#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.15:36:19.62#ibcon#[25=AT08-04\r\n] 2006.173.15:36:19.62#ibcon#*before write, iclass 40, count 2 2006.173.15:36:19.62#ibcon#enter sib2, iclass 40, count 2 2006.173.15:36:19.62#ibcon#flushed, iclass 40, count 2 2006.173.15:36:19.62#ibcon#about to write, iclass 40, count 2 2006.173.15:36:19.62#ibcon#wrote, iclass 40, count 2 2006.173.15:36:19.62#ibcon#about to read 3, iclass 40, count 2 2006.173.15:36:19.65#ibcon#read 3, iclass 40, count 2 2006.173.15:36:19.65#ibcon#about to read 4, iclass 40, count 2 2006.173.15:36:19.65#ibcon#read 4, iclass 40, count 2 2006.173.15:36:19.65#ibcon#about to read 5, iclass 40, count 2 2006.173.15:36:19.65#ibcon#read 5, iclass 40, count 2 2006.173.15:36:19.65#ibcon#about to read 6, iclass 40, count 2 2006.173.15:36:19.65#ibcon#read 6, iclass 40, count 2 2006.173.15:36:19.65#ibcon#end of sib2, iclass 40, count 2 2006.173.15:36:19.65#ibcon#*after write, iclass 40, count 2 2006.173.15:36:19.65#ibcon#*before return 0, iclass 40, count 2 2006.173.15:36:19.65#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.15:36:19.65#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.15:36:19.65#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.15:36:19.65#ibcon#ireg 7 cls_cnt 0 2006.173.15:36:19.65#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.15:36:19.77#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.15:36:19.77#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.15:36:19.77#ibcon#enter wrdev, iclass 40, count 0 2006.173.15:36:19.77#ibcon#first serial, iclass 40, count 0 2006.173.15:36:19.77#ibcon#enter sib2, iclass 40, count 0 2006.173.15:36:19.77#ibcon#flushed, iclass 40, count 0 2006.173.15:36:19.77#ibcon#about to write, iclass 40, count 0 2006.173.15:36:19.77#ibcon#wrote, iclass 40, count 0 2006.173.15:36:19.77#ibcon#about to read 3, iclass 40, count 0 2006.173.15:36:19.79#ibcon#read 3, iclass 40, count 0 2006.173.15:36:19.79#ibcon#about to read 4, iclass 40, count 0 2006.173.15:36:19.79#ibcon#read 4, iclass 40, count 0 2006.173.15:36:19.79#ibcon#about to read 5, iclass 40, count 0 2006.173.15:36:19.79#ibcon#read 5, iclass 40, count 0 2006.173.15:36:19.79#ibcon#about to read 6, iclass 40, count 0 2006.173.15:36:19.79#ibcon#read 6, iclass 40, count 0 2006.173.15:36:19.79#ibcon#end of sib2, iclass 40, count 0 2006.173.15:36:19.79#ibcon#*mode == 0, iclass 40, count 0 2006.173.15:36:19.79#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.15:36:19.79#ibcon#[25=USB\r\n] 2006.173.15:36:19.79#ibcon#*before write, iclass 40, count 0 2006.173.15:36:19.79#ibcon#enter sib2, iclass 40, count 0 2006.173.15:36:19.79#ibcon#flushed, iclass 40, count 0 2006.173.15:36:19.79#ibcon#about to write, iclass 40, count 0 2006.173.15:36:19.79#ibcon#wrote, iclass 40, count 0 2006.173.15:36:19.79#ibcon#about to read 3, iclass 40, count 0 2006.173.15:36:19.82#ibcon#read 3, iclass 40, count 0 2006.173.15:36:19.82#ibcon#about to read 4, iclass 40, count 0 2006.173.15:36:19.82#ibcon#read 4, iclass 40, count 0 2006.173.15:36:19.82#ibcon#about to read 5, iclass 40, count 0 2006.173.15:36:19.82#ibcon#read 5, iclass 40, count 0 2006.173.15:36:19.82#ibcon#about to read 6, iclass 40, count 0 2006.173.15:36:19.82#ibcon#read 6, iclass 40, count 0 2006.173.15:36:19.82#ibcon#end of sib2, iclass 40, count 0 2006.173.15:36:19.82#ibcon#*after write, iclass 40, count 0 2006.173.15:36:19.82#ibcon#*before return 0, iclass 40, count 0 2006.173.15:36:19.82#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.15:36:19.82#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.15:36:19.82#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.15:36:19.82#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.15:36:19.82$vck44/vblo=1,629.99 2006.173.15:36:19.82#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.15:36:19.82#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.15:36:19.82#ibcon#ireg 17 cls_cnt 0 2006.173.15:36:19.82#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.15:36:19.82#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.15:36:19.82#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.15:36:19.82#ibcon#enter wrdev, iclass 4, count 0 2006.173.15:36:19.82#ibcon#first serial, iclass 4, count 0 2006.173.15:36:19.82#ibcon#enter sib2, iclass 4, count 0 2006.173.15:36:19.82#ibcon#flushed, iclass 4, count 0 2006.173.15:36:19.82#ibcon#about to write, iclass 4, count 0 2006.173.15:36:19.82#ibcon#wrote, iclass 4, count 0 2006.173.15:36:19.82#ibcon#about to read 3, iclass 4, count 0 2006.173.15:36:19.84#ibcon#read 3, iclass 4, count 0 2006.173.15:36:19.84#ibcon#about to read 4, iclass 4, count 0 2006.173.15:36:19.84#ibcon#read 4, iclass 4, count 0 2006.173.15:36:19.84#ibcon#about to read 5, iclass 4, count 0 2006.173.15:36:19.84#ibcon#read 5, iclass 4, count 0 2006.173.15:36:19.84#ibcon#about to read 6, iclass 4, count 0 2006.173.15:36:19.84#ibcon#read 6, iclass 4, count 0 2006.173.15:36:19.84#ibcon#end of sib2, iclass 4, count 0 2006.173.15:36:19.84#ibcon#*mode == 0, iclass 4, count 0 2006.173.15:36:19.84#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.15:36:19.84#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.15:36:19.84#ibcon#*before write, iclass 4, count 0 2006.173.15:36:19.84#ibcon#enter sib2, iclass 4, count 0 2006.173.15:36:19.84#ibcon#flushed, iclass 4, count 0 2006.173.15:36:19.84#ibcon#about to write, iclass 4, count 0 2006.173.15:36:19.84#ibcon#wrote, iclass 4, count 0 2006.173.15:36:19.84#ibcon#about to read 3, iclass 4, count 0 2006.173.15:36:19.88#ibcon#read 3, iclass 4, count 0 2006.173.15:36:19.88#ibcon#about to read 4, iclass 4, count 0 2006.173.15:36:19.88#ibcon#read 4, iclass 4, count 0 2006.173.15:36:19.88#ibcon#about to read 5, iclass 4, count 0 2006.173.15:36:19.88#ibcon#read 5, iclass 4, count 0 2006.173.15:36:19.88#ibcon#about to read 6, iclass 4, count 0 2006.173.15:36:19.88#ibcon#read 6, iclass 4, count 0 2006.173.15:36:19.88#ibcon#end of sib2, iclass 4, count 0 2006.173.15:36:19.88#ibcon#*after write, iclass 4, count 0 2006.173.15:36:19.88#ibcon#*before return 0, iclass 4, count 0 2006.173.15:36:19.88#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.15:36:19.88#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.15:36:19.88#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.15:36:19.88#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.15:36:19.88$vck44/vb=1,4 2006.173.15:36:19.88#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.15:36:19.88#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.15:36:19.88#ibcon#ireg 11 cls_cnt 2 2006.173.15:36:19.88#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.15:36:19.88#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.15:36:19.88#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.15:36:19.88#ibcon#enter wrdev, iclass 6, count 2 2006.173.15:36:19.88#ibcon#first serial, iclass 6, count 2 2006.173.15:36:19.88#ibcon#enter sib2, iclass 6, count 2 2006.173.15:36:19.88#ibcon#flushed, iclass 6, count 2 2006.173.15:36:19.88#ibcon#about to write, iclass 6, count 2 2006.173.15:36:19.88#ibcon#wrote, iclass 6, count 2 2006.173.15:36:19.88#ibcon#about to read 3, iclass 6, count 2 2006.173.15:36:19.90#ibcon#read 3, iclass 6, count 2 2006.173.15:36:19.90#ibcon#about to read 4, iclass 6, count 2 2006.173.15:36:19.90#ibcon#read 4, iclass 6, count 2 2006.173.15:36:19.90#ibcon#about to read 5, iclass 6, count 2 2006.173.15:36:19.90#ibcon#read 5, iclass 6, count 2 2006.173.15:36:19.90#ibcon#about to read 6, iclass 6, count 2 2006.173.15:36:19.90#ibcon#read 6, iclass 6, count 2 2006.173.15:36:19.90#ibcon#end of sib2, iclass 6, count 2 2006.173.15:36:19.90#ibcon#*mode == 0, iclass 6, count 2 2006.173.15:36:19.90#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.15:36:19.90#ibcon#[27=AT01-04\r\n] 2006.173.15:36:19.90#ibcon#*before write, iclass 6, count 2 2006.173.15:36:19.90#ibcon#enter sib2, iclass 6, count 2 2006.173.15:36:19.90#ibcon#flushed, iclass 6, count 2 2006.173.15:36:19.90#ibcon#about to write, iclass 6, count 2 2006.173.15:36:19.90#ibcon#wrote, iclass 6, count 2 2006.173.15:36:19.90#ibcon#about to read 3, iclass 6, count 2 2006.173.15:36:19.93#ibcon#read 3, iclass 6, count 2 2006.173.15:36:19.93#ibcon#about to read 4, iclass 6, count 2 2006.173.15:36:19.93#ibcon#read 4, iclass 6, count 2 2006.173.15:36:19.93#ibcon#about to read 5, iclass 6, count 2 2006.173.15:36:19.93#ibcon#read 5, iclass 6, count 2 2006.173.15:36:19.93#ibcon#about to read 6, iclass 6, count 2 2006.173.15:36:19.93#ibcon#read 6, iclass 6, count 2 2006.173.15:36:19.93#ibcon#end of sib2, iclass 6, count 2 2006.173.15:36:19.93#ibcon#*after write, iclass 6, count 2 2006.173.15:36:19.93#ibcon#*before return 0, iclass 6, count 2 2006.173.15:36:19.93#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.15:36:19.93#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.15:36:19.93#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.15:36:19.93#ibcon#ireg 7 cls_cnt 0 2006.173.15:36:19.93#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.15:36:20.05#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.15:36:20.05#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.15:36:20.05#ibcon#enter wrdev, iclass 6, count 0 2006.173.15:36:20.05#ibcon#first serial, iclass 6, count 0 2006.173.15:36:20.05#ibcon#enter sib2, iclass 6, count 0 2006.173.15:36:20.05#ibcon#flushed, iclass 6, count 0 2006.173.15:36:20.05#ibcon#about to write, iclass 6, count 0 2006.173.15:36:20.05#ibcon#wrote, iclass 6, count 0 2006.173.15:36:20.05#ibcon#about to read 3, iclass 6, count 0 2006.173.15:36:20.07#ibcon#read 3, iclass 6, count 0 2006.173.15:36:20.07#ibcon#about to read 4, iclass 6, count 0 2006.173.15:36:20.07#ibcon#read 4, iclass 6, count 0 2006.173.15:36:20.07#ibcon#about to read 5, iclass 6, count 0 2006.173.15:36:20.07#ibcon#read 5, iclass 6, count 0 2006.173.15:36:20.07#ibcon#about to read 6, iclass 6, count 0 2006.173.15:36:20.07#ibcon#read 6, iclass 6, count 0 2006.173.15:36:20.07#ibcon#end of sib2, iclass 6, count 0 2006.173.15:36:20.07#ibcon#*mode == 0, iclass 6, count 0 2006.173.15:36:20.07#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.15:36:20.07#ibcon#[27=USB\r\n] 2006.173.15:36:20.07#ibcon#*before write, iclass 6, count 0 2006.173.15:36:20.07#ibcon#enter sib2, iclass 6, count 0 2006.173.15:36:20.07#ibcon#flushed, iclass 6, count 0 2006.173.15:36:20.07#ibcon#about to write, iclass 6, count 0 2006.173.15:36:20.07#ibcon#wrote, iclass 6, count 0 2006.173.15:36:20.07#ibcon#about to read 3, iclass 6, count 0 2006.173.15:36:20.10#ibcon#read 3, iclass 6, count 0 2006.173.15:36:20.10#ibcon#about to read 4, iclass 6, count 0 2006.173.15:36:20.10#ibcon#read 4, iclass 6, count 0 2006.173.15:36:20.10#ibcon#about to read 5, iclass 6, count 0 2006.173.15:36:20.10#ibcon#read 5, iclass 6, count 0 2006.173.15:36:20.10#ibcon#about to read 6, iclass 6, count 0 2006.173.15:36:20.10#ibcon#read 6, iclass 6, count 0 2006.173.15:36:20.10#ibcon#end of sib2, iclass 6, count 0 2006.173.15:36:20.10#ibcon#*after write, iclass 6, count 0 2006.173.15:36:20.10#ibcon#*before return 0, iclass 6, count 0 2006.173.15:36:20.10#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.15:36:20.10#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.15:36:20.10#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.15:36:20.10#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.15:36:20.10$vck44/vblo=2,634.99 2006.173.15:36:20.10#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.15:36:20.10#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.15:36:20.10#ibcon#ireg 17 cls_cnt 0 2006.173.15:36:20.10#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.15:36:20.10#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.15:36:20.10#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.15:36:20.10#ibcon#enter wrdev, iclass 10, count 0 2006.173.15:36:20.10#ibcon#first serial, iclass 10, count 0 2006.173.15:36:20.10#ibcon#enter sib2, iclass 10, count 0 2006.173.15:36:20.10#ibcon#flushed, iclass 10, count 0 2006.173.15:36:20.10#ibcon#about to write, iclass 10, count 0 2006.173.15:36:20.10#ibcon#wrote, iclass 10, count 0 2006.173.15:36:20.10#ibcon#about to read 3, iclass 10, count 0 2006.173.15:36:20.12#ibcon#read 3, iclass 10, count 0 2006.173.15:36:20.12#ibcon#about to read 4, iclass 10, count 0 2006.173.15:36:20.12#ibcon#read 4, iclass 10, count 0 2006.173.15:36:20.12#ibcon#about to read 5, iclass 10, count 0 2006.173.15:36:20.12#ibcon#read 5, iclass 10, count 0 2006.173.15:36:20.12#ibcon#about to read 6, iclass 10, count 0 2006.173.15:36:20.12#ibcon#read 6, iclass 10, count 0 2006.173.15:36:20.12#ibcon#end of sib2, iclass 10, count 0 2006.173.15:36:20.12#ibcon#*mode == 0, iclass 10, count 0 2006.173.15:36:20.12#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.15:36:20.12#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.15:36:20.12#ibcon#*before write, iclass 10, count 0 2006.173.15:36:20.12#ibcon#enter sib2, iclass 10, count 0 2006.173.15:36:20.12#ibcon#flushed, iclass 10, count 0 2006.173.15:36:20.12#ibcon#about to write, iclass 10, count 0 2006.173.15:36:20.12#ibcon#wrote, iclass 10, count 0 2006.173.15:36:20.12#ibcon#about to read 3, iclass 10, count 0 2006.173.15:36:20.16#ibcon#read 3, iclass 10, count 0 2006.173.15:36:20.16#ibcon#about to read 4, iclass 10, count 0 2006.173.15:36:20.16#ibcon#read 4, iclass 10, count 0 2006.173.15:36:20.16#ibcon#about to read 5, iclass 10, count 0 2006.173.15:36:20.16#ibcon#read 5, iclass 10, count 0 2006.173.15:36:20.16#ibcon#about to read 6, iclass 10, count 0 2006.173.15:36:20.16#ibcon#read 6, iclass 10, count 0 2006.173.15:36:20.16#ibcon#end of sib2, iclass 10, count 0 2006.173.15:36:20.16#ibcon#*after write, iclass 10, count 0 2006.173.15:36:20.16#ibcon#*before return 0, iclass 10, count 0 2006.173.15:36:20.16#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.15:36:20.16#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.15:36:20.16#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.15:36:20.16#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.15:36:20.16$vck44/vb=2,4 2006.173.15:36:20.16#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.15:36:20.16#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.15:36:20.16#ibcon#ireg 11 cls_cnt 2 2006.173.15:36:20.16#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.15:36:20.22#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.15:36:20.22#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.15:36:20.22#ibcon#enter wrdev, iclass 12, count 2 2006.173.15:36:20.22#ibcon#first serial, iclass 12, count 2 2006.173.15:36:20.22#ibcon#enter sib2, iclass 12, count 2 2006.173.15:36:20.22#ibcon#flushed, iclass 12, count 2 2006.173.15:36:20.22#ibcon#about to write, iclass 12, count 2 2006.173.15:36:20.22#ibcon#wrote, iclass 12, count 2 2006.173.15:36:20.22#ibcon#about to read 3, iclass 12, count 2 2006.173.15:36:20.24#ibcon#read 3, iclass 12, count 2 2006.173.15:36:20.24#ibcon#about to read 4, iclass 12, count 2 2006.173.15:36:20.24#ibcon#read 4, iclass 12, count 2 2006.173.15:36:20.24#ibcon#about to read 5, iclass 12, count 2 2006.173.15:36:20.24#ibcon#read 5, iclass 12, count 2 2006.173.15:36:20.24#ibcon#about to read 6, iclass 12, count 2 2006.173.15:36:20.24#ibcon#read 6, iclass 12, count 2 2006.173.15:36:20.24#ibcon#end of sib2, iclass 12, count 2 2006.173.15:36:20.24#ibcon#*mode == 0, iclass 12, count 2 2006.173.15:36:20.24#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.15:36:20.24#ibcon#[27=AT02-04\r\n] 2006.173.15:36:20.24#ibcon#*before write, iclass 12, count 2 2006.173.15:36:20.24#ibcon#enter sib2, iclass 12, count 2 2006.173.15:36:20.24#ibcon#flushed, iclass 12, count 2 2006.173.15:36:20.24#ibcon#about to write, iclass 12, count 2 2006.173.15:36:20.24#ibcon#wrote, iclass 12, count 2 2006.173.15:36:20.24#ibcon#about to read 3, iclass 12, count 2 2006.173.15:36:20.27#ibcon#read 3, iclass 12, count 2 2006.173.15:36:20.27#ibcon#about to read 4, iclass 12, count 2 2006.173.15:36:20.27#ibcon#read 4, iclass 12, count 2 2006.173.15:36:20.27#ibcon#about to read 5, iclass 12, count 2 2006.173.15:36:20.27#ibcon#read 5, iclass 12, count 2 2006.173.15:36:20.27#ibcon#about to read 6, iclass 12, count 2 2006.173.15:36:20.27#ibcon#read 6, iclass 12, count 2 2006.173.15:36:20.27#ibcon#end of sib2, iclass 12, count 2 2006.173.15:36:20.27#ibcon#*after write, iclass 12, count 2 2006.173.15:36:20.27#ibcon#*before return 0, iclass 12, count 2 2006.173.15:36:20.27#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.15:36:20.27#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.15:36:20.27#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.15:36:20.27#ibcon#ireg 7 cls_cnt 0 2006.173.15:36:20.27#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.15:36:20.39#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.15:36:20.39#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.15:36:20.39#ibcon#enter wrdev, iclass 12, count 0 2006.173.15:36:20.39#ibcon#first serial, iclass 12, count 0 2006.173.15:36:20.39#ibcon#enter sib2, iclass 12, count 0 2006.173.15:36:20.39#ibcon#flushed, iclass 12, count 0 2006.173.15:36:20.39#ibcon#about to write, iclass 12, count 0 2006.173.15:36:20.39#ibcon#wrote, iclass 12, count 0 2006.173.15:36:20.39#ibcon#about to read 3, iclass 12, count 0 2006.173.15:36:20.41#ibcon#read 3, iclass 12, count 0 2006.173.15:36:20.41#ibcon#about to read 4, iclass 12, count 0 2006.173.15:36:20.41#ibcon#read 4, iclass 12, count 0 2006.173.15:36:20.41#ibcon#about to read 5, iclass 12, count 0 2006.173.15:36:20.41#ibcon#read 5, iclass 12, count 0 2006.173.15:36:20.41#ibcon#about to read 6, iclass 12, count 0 2006.173.15:36:20.41#ibcon#read 6, iclass 12, count 0 2006.173.15:36:20.41#ibcon#end of sib2, iclass 12, count 0 2006.173.15:36:20.41#ibcon#*mode == 0, iclass 12, count 0 2006.173.15:36:20.41#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.15:36:20.41#ibcon#[27=USB\r\n] 2006.173.15:36:20.41#ibcon#*before write, iclass 12, count 0 2006.173.15:36:20.41#ibcon#enter sib2, iclass 12, count 0 2006.173.15:36:20.41#ibcon#flushed, iclass 12, count 0 2006.173.15:36:20.41#ibcon#about to write, iclass 12, count 0 2006.173.15:36:20.41#ibcon#wrote, iclass 12, count 0 2006.173.15:36:20.41#ibcon#about to read 3, iclass 12, count 0 2006.173.15:36:20.44#ibcon#read 3, iclass 12, count 0 2006.173.15:36:20.44#ibcon#about to read 4, iclass 12, count 0 2006.173.15:36:20.44#ibcon#read 4, iclass 12, count 0 2006.173.15:36:20.44#ibcon#about to read 5, iclass 12, count 0 2006.173.15:36:20.44#ibcon#read 5, iclass 12, count 0 2006.173.15:36:20.44#ibcon#about to read 6, iclass 12, count 0 2006.173.15:36:20.44#ibcon#read 6, iclass 12, count 0 2006.173.15:36:20.44#ibcon#end of sib2, iclass 12, count 0 2006.173.15:36:20.44#ibcon#*after write, iclass 12, count 0 2006.173.15:36:20.44#ibcon#*before return 0, iclass 12, count 0 2006.173.15:36:20.44#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.15:36:20.44#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.15:36:20.44#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.15:36:20.44#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.15:36:20.44$vck44/vblo=3,649.99 2006.173.15:36:20.44#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.15:36:20.44#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.15:36:20.44#ibcon#ireg 17 cls_cnt 0 2006.173.15:36:20.44#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.15:36:20.44#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.15:36:20.44#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.15:36:20.44#ibcon#enter wrdev, iclass 14, count 0 2006.173.15:36:20.44#ibcon#first serial, iclass 14, count 0 2006.173.15:36:20.44#ibcon#enter sib2, iclass 14, count 0 2006.173.15:36:20.44#ibcon#flushed, iclass 14, count 0 2006.173.15:36:20.44#ibcon#about to write, iclass 14, count 0 2006.173.15:36:20.44#ibcon#wrote, iclass 14, count 0 2006.173.15:36:20.44#ibcon#about to read 3, iclass 14, count 0 2006.173.15:36:20.46#ibcon#read 3, iclass 14, count 0 2006.173.15:36:20.46#ibcon#about to read 4, iclass 14, count 0 2006.173.15:36:20.46#ibcon#read 4, iclass 14, count 0 2006.173.15:36:20.46#ibcon#about to read 5, iclass 14, count 0 2006.173.15:36:20.46#ibcon#read 5, iclass 14, count 0 2006.173.15:36:20.46#ibcon#about to read 6, iclass 14, count 0 2006.173.15:36:20.46#ibcon#read 6, iclass 14, count 0 2006.173.15:36:20.46#ibcon#end of sib2, iclass 14, count 0 2006.173.15:36:20.46#ibcon#*mode == 0, iclass 14, count 0 2006.173.15:36:20.46#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.15:36:20.46#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.15:36:20.46#ibcon#*before write, iclass 14, count 0 2006.173.15:36:20.46#ibcon#enter sib2, iclass 14, count 0 2006.173.15:36:20.46#ibcon#flushed, iclass 14, count 0 2006.173.15:36:20.46#ibcon#about to write, iclass 14, count 0 2006.173.15:36:20.46#ibcon#wrote, iclass 14, count 0 2006.173.15:36:20.46#ibcon#about to read 3, iclass 14, count 0 2006.173.15:36:20.50#ibcon#read 3, iclass 14, count 0 2006.173.15:36:20.50#ibcon#about to read 4, iclass 14, count 0 2006.173.15:36:20.50#ibcon#read 4, iclass 14, count 0 2006.173.15:36:20.50#ibcon#about to read 5, iclass 14, count 0 2006.173.15:36:20.50#ibcon#read 5, iclass 14, count 0 2006.173.15:36:20.50#ibcon#about to read 6, iclass 14, count 0 2006.173.15:36:20.50#ibcon#read 6, iclass 14, count 0 2006.173.15:36:20.50#ibcon#end of sib2, iclass 14, count 0 2006.173.15:36:20.50#ibcon#*after write, iclass 14, count 0 2006.173.15:36:20.50#ibcon#*before return 0, iclass 14, count 0 2006.173.15:36:20.50#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.15:36:20.50#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.15:36:20.50#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.15:36:20.50#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.15:36:20.50$vck44/vb=3,4 2006.173.15:36:20.50#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.15:36:20.50#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.15:36:20.50#ibcon#ireg 11 cls_cnt 2 2006.173.15:36:20.50#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.15:36:20.56#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.15:36:20.56#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.15:36:20.56#ibcon#enter wrdev, iclass 16, count 2 2006.173.15:36:20.56#ibcon#first serial, iclass 16, count 2 2006.173.15:36:20.56#ibcon#enter sib2, iclass 16, count 2 2006.173.15:36:20.56#ibcon#flushed, iclass 16, count 2 2006.173.15:36:20.56#ibcon#about to write, iclass 16, count 2 2006.173.15:36:20.56#ibcon#wrote, iclass 16, count 2 2006.173.15:36:20.56#ibcon#about to read 3, iclass 16, count 2 2006.173.15:36:20.58#ibcon#read 3, iclass 16, count 2 2006.173.15:36:20.58#ibcon#about to read 4, iclass 16, count 2 2006.173.15:36:20.58#ibcon#read 4, iclass 16, count 2 2006.173.15:36:20.58#ibcon#about to read 5, iclass 16, count 2 2006.173.15:36:20.58#ibcon#read 5, iclass 16, count 2 2006.173.15:36:20.58#ibcon#about to read 6, iclass 16, count 2 2006.173.15:36:20.58#ibcon#read 6, iclass 16, count 2 2006.173.15:36:20.58#ibcon#end of sib2, iclass 16, count 2 2006.173.15:36:20.58#ibcon#*mode == 0, iclass 16, count 2 2006.173.15:36:20.58#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.15:36:20.58#ibcon#[27=AT03-04\r\n] 2006.173.15:36:20.58#ibcon#*before write, iclass 16, count 2 2006.173.15:36:20.58#ibcon#enter sib2, iclass 16, count 2 2006.173.15:36:20.58#ibcon#flushed, iclass 16, count 2 2006.173.15:36:20.58#ibcon#about to write, iclass 16, count 2 2006.173.15:36:20.58#ibcon#wrote, iclass 16, count 2 2006.173.15:36:20.58#ibcon#about to read 3, iclass 16, count 2 2006.173.15:36:20.61#ibcon#read 3, iclass 16, count 2 2006.173.15:36:20.61#ibcon#about to read 4, iclass 16, count 2 2006.173.15:36:20.61#ibcon#read 4, iclass 16, count 2 2006.173.15:36:20.61#ibcon#about to read 5, iclass 16, count 2 2006.173.15:36:20.61#ibcon#read 5, iclass 16, count 2 2006.173.15:36:20.61#ibcon#about to read 6, iclass 16, count 2 2006.173.15:36:20.61#ibcon#read 6, iclass 16, count 2 2006.173.15:36:20.61#ibcon#end of sib2, iclass 16, count 2 2006.173.15:36:20.61#ibcon#*after write, iclass 16, count 2 2006.173.15:36:20.61#ibcon#*before return 0, iclass 16, count 2 2006.173.15:36:20.61#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.15:36:20.61#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.15:36:20.61#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.15:36:20.61#ibcon#ireg 7 cls_cnt 0 2006.173.15:36:20.61#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.15:36:20.68#abcon#<5=/14 1.5 3.4 21.001001002.9\r\n> 2006.173.15:36:20.70#abcon#{5=INTERFACE CLEAR} 2006.173.15:36:20.73#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.15:36:20.73#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.15:36:20.73#ibcon#enter wrdev, iclass 16, count 0 2006.173.15:36:20.73#ibcon#first serial, iclass 16, count 0 2006.173.15:36:20.73#ibcon#enter sib2, iclass 16, count 0 2006.173.15:36:20.73#ibcon#flushed, iclass 16, count 0 2006.173.15:36:20.73#ibcon#about to write, iclass 16, count 0 2006.173.15:36:20.73#ibcon#wrote, iclass 16, count 0 2006.173.15:36:20.73#ibcon#about to read 3, iclass 16, count 0 2006.173.15:36:20.75#ibcon#read 3, iclass 16, count 0 2006.173.15:36:20.75#ibcon#about to read 4, iclass 16, count 0 2006.173.15:36:20.75#ibcon#read 4, iclass 16, count 0 2006.173.15:36:20.75#ibcon#about to read 5, iclass 16, count 0 2006.173.15:36:20.75#ibcon#read 5, iclass 16, count 0 2006.173.15:36:20.75#ibcon#about to read 6, iclass 16, count 0 2006.173.15:36:20.75#ibcon#read 6, iclass 16, count 0 2006.173.15:36:20.75#ibcon#end of sib2, iclass 16, count 0 2006.173.15:36:20.75#ibcon#*mode == 0, iclass 16, count 0 2006.173.15:36:20.75#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.15:36:20.75#ibcon#[27=USB\r\n] 2006.173.15:36:20.75#ibcon#*before write, iclass 16, count 0 2006.173.15:36:20.75#ibcon#enter sib2, iclass 16, count 0 2006.173.15:36:20.75#ibcon#flushed, iclass 16, count 0 2006.173.15:36:20.75#ibcon#about to write, iclass 16, count 0 2006.173.15:36:20.75#ibcon#wrote, iclass 16, count 0 2006.173.15:36:20.75#ibcon#about to read 3, iclass 16, count 0 2006.173.15:36:20.76#abcon#[5=S1D000X0/0*\r\n] 2006.173.15:36:20.78#ibcon#read 3, iclass 16, count 0 2006.173.15:36:20.78#ibcon#about to read 4, iclass 16, count 0 2006.173.15:36:20.78#ibcon#read 4, iclass 16, count 0 2006.173.15:36:20.78#ibcon#about to read 5, iclass 16, count 0 2006.173.15:36:20.78#ibcon#read 5, iclass 16, count 0 2006.173.15:36:20.78#ibcon#about to read 6, iclass 16, count 0 2006.173.15:36:20.78#ibcon#read 6, iclass 16, count 0 2006.173.15:36:20.78#ibcon#end of sib2, iclass 16, count 0 2006.173.15:36:20.78#ibcon#*after write, iclass 16, count 0 2006.173.15:36:20.78#ibcon#*before return 0, iclass 16, count 0 2006.173.15:36:20.78#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.15:36:20.78#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.15:36:20.78#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.15:36:20.78#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.15:36:20.78$vck44/vblo=4,679.99 2006.173.15:36:20.78#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.15:36:20.78#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.15:36:20.78#ibcon#ireg 17 cls_cnt 0 2006.173.15:36:20.78#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.15:36:20.78#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.15:36:20.78#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.15:36:20.78#ibcon#enter wrdev, iclass 22, count 0 2006.173.15:36:20.78#ibcon#first serial, iclass 22, count 0 2006.173.15:36:20.78#ibcon#enter sib2, iclass 22, count 0 2006.173.15:36:20.78#ibcon#flushed, iclass 22, count 0 2006.173.15:36:20.78#ibcon#about to write, iclass 22, count 0 2006.173.15:36:20.78#ibcon#wrote, iclass 22, count 0 2006.173.15:36:20.78#ibcon#about to read 3, iclass 22, count 0 2006.173.15:36:20.80#ibcon#read 3, iclass 22, count 0 2006.173.15:36:20.80#ibcon#about to read 4, iclass 22, count 0 2006.173.15:36:20.80#ibcon#read 4, iclass 22, count 0 2006.173.15:36:20.80#ibcon#about to read 5, iclass 22, count 0 2006.173.15:36:20.80#ibcon#read 5, iclass 22, count 0 2006.173.15:36:20.80#ibcon#about to read 6, iclass 22, count 0 2006.173.15:36:20.80#ibcon#read 6, iclass 22, count 0 2006.173.15:36:20.80#ibcon#end of sib2, iclass 22, count 0 2006.173.15:36:20.80#ibcon#*mode == 0, iclass 22, count 0 2006.173.15:36:20.80#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.15:36:20.80#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.15:36:20.80#ibcon#*before write, iclass 22, count 0 2006.173.15:36:20.80#ibcon#enter sib2, iclass 22, count 0 2006.173.15:36:20.80#ibcon#flushed, iclass 22, count 0 2006.173.15:36:20.80#ibcon#about to write, iclass 22, count 0 2006.173.15:36:20.80#ibcon#wrote, iclass 22, count 0 2006.173.15:36:20.80#ibcon#about to read 3, iclass 22, count 0 2006.173.15:36:20.84#ibcon#read 3, iclass 22, count 0 2006.173.15:36:20.84#ibcon#about to read 4, iclass 22, count 0 2006.173.15:36:20.84#ibcon#read 4, iclass 22, count 0 2006.173.15:36:20.84#ibcon#about to read 5, iclass 22, count 0 2006.173.15:36:20.84#ibcon#read 5, iclass 22, count 0 2006.173.15:36:20.84#ibcon#about to read 6, iclass 22, count 0 2006.173.15:36:20.84#ibcon#read 6, iclass 22, count 0 2006.173.15:36:20.84#ibcon#end of sib2, iclass 22, count 0 2006.173.15:36:20.84#ibcon#*after write, iclass 22, count 0 2006.173.15:36:20.84#ibcon#*before return 0, iclass 22, count 0 2006.173.15:36:20.84#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.15:36:20.84#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.15:36:20.84#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.15:36:20.84#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.15:36:20.84$vck44/vb=4,4 2006.173.15:36:20.84#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.15:36:20.84#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.15:36:20.84#ibcon#ireg 11 cls_cnt 2 2006.173.15:36:20.84#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.15:36:20.90#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.15:36:20.90#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.15:36:20.90#ibcon#enter wrdev, iclass 24, count 2 2006.173.15:36:20.90#ibcon#first serial, iclass 24, count 2 2006.173.15:36:20.90#ibcon#enter sib2, iclass 24, count 2 2006.173.15:36:20.90#ibcon#flushed, iclass 24, count 2 2006.173.15:36:20.90#ibcon#about to write, iclass 24, count 2 2006.173.15:36:20.90#ibcon#wrote, iclass 24, count 2 2006.173.15:36:20.90#ibcon#about to read 3, iclass 24, count 2 2006.173.15:36:20.92#ibcon#read 3, iclass 24, count 2 2006.173.15:36:20.92#ibcon#about to read 4, iclass 24, count 2 2006.173.15:36:20.92#ibcon#read 4, iclass 24, count 2 2006.173.15:36:20.92#ibcon#about to read 5, iclass 24, count 2 2006.173.15:36:20.92#ibcon#read 5, iclass 24, count 2 2006.173.15:36:20.92#ibcon#about to read 6, iclass 24, count 2 2006.173.15:36:20.92#ibcon#read 6, iclass 24, count 2 2006.173.15:36:20.92#ibcon#end of sib2, iclass 24, count 2 2006.173.15:36:20.92#ibcon#*mode == 0, iclass 24, count 2 2006.173.15:36:20.92#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.15:36:20.92#ibcon#[27=AT04-04\r\n] 2006.173.15:36:20.92#ibcon#*before write, iclass 24, count 2 2006.173.15:36:20.92#ibcon#enter sib2, iclass 24, count 2 2006.173.15:36:20.92#ibcon#flushed, iclass 24, count 2 2006.173.15:36:20.92#ibcon#about to write, iclass 24, count 2 2006.173.15:36:20.92#ibcon#wrote, iclass 24, count 2 2006.173.15:36:20.92#ibcon#about to read 3, iclass 24, count 2 2006.173.15:36:20.95#ibcon#read 3, iclass 24, count 2 2006.173.15:36:20.95#ibcon#about to read 4, iclass 24, count 2 2006.173.15:36:20.95#ibcon#read 4, iclass 24, count 2 2006.173.15:36:20.95#ibcon#about to read 5, iclass 24, count 2 2006.173.15:36:20.95#ibcon#read 5, iclass 24, count 2 2006.173.15:36:20.95#ibcon#about to read 6, iclass 24, count 2 2006.173.15:36:20.95#ibcon#read 6, iclass 24, count 2 2006.173.15:36:20.95#ibcon#end of sib2, iclass 24, count 2 2006.173.15:36:20.95#ibcon#*after write, iclass 24, count 2 2006.173.15:36:20.95#ibcon#*before return 0, iclass 24, count 2 2006.173.15:36:20.95#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.15:36:20.95#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.15:36:20.95#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.15:36:20.95#ibcon#ireg 7 cls_cnt 0 2006.173.15:36:20.95#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.15:36:21.07#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.15:36:21.07#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.15:36:21.07#ibcon#enter wrdev, iclass 24, count 0 2006.173.15:36:21.07#ibcon#first serial, iclass 24, count 0 2006.173.15:36:21.07#ibcon#enter sib2, iclass 24, count 0 2006.173.15:36:21.07#ibcon#flushed, iclass 24, count 0 2006.173.15:36:21.07#ibcon#about to write, iclass 24, count 0 2006.173.15:36:21.07#ibcon#wrote, iclass 24, count 0 2006.173.15:36:21.07#ibcon#about to read 3, iclass 24, count 0 2006.173.15:36:21.09#ibcon#read 3, iclass 24, count 0 2006.173.15:36:21.09#ibcon#about to read 4, iclass 24, count 0 2006.173.15:36:21.09#ibcon#read 4, iclass 24, count 0 2006.173.15:36:21.09#ibcon#about to read 5, iclass 24, count 0 2006.173.15:36:21.09#ibcon#read 5, iclass 24, count 0 2006.173.15:36:21.09#ibcon#about to read 6, iclass 24, count 0 2006.173.15:36:21.09#ibcon#read 6, iclass 24, count 0 2006.173.15:36:21.09#ibcon#end of sib2, iclass 24, count 0 2006.173.15:36:21.09#ibcon#*mode == 0, iclass 24, count 0 2006.173.15:36:21.09#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.15:36:21.09#ibcon#[27=USB\r\n] 2006.173.15:36:21.09#ibcon#*before write, iclass 24, count 0 2006.173.15:36:21.09#ibcon#enter sib2, iclass 24, count 0 2006.173.15:36:21.09#ibcon#flushed, iclass 24, count 0 2006.173.15:36:21.09#ibcon#about to write, iclass 24, count 0 2006.173.15:36:21.09#ibcon#wrote, iclass 24, count 0 2006.173.15:36:21.09#ibcon#about to read 3, iclass 24, count 0 2006.173.15:36:21.12#ibcon#read 3, iclass 24, count 0 2006.173.15:36:21.12#ibcon#about to read 4, iclass 24, count 0 2006.173.15:36:21.12#ibcon#read 4, iclass 24, count 0 2006.173.15:36:21.12#ibcon#about to read 5, iclass 24, count 0 2006.173.15:36:21.12#ibcon#read 5, iclass 24, count 0 2006.173.15:36:21.12#ibcon#about to read 6, iclass 24, count 0 2006.173.15:36:21.12#ibcon#read 6, iclass 24, count 0 2006.173.15:36:21.12#ibcon#end of sib2, iclass 24, count 0 2006.173.15:36:21.12#ibcon#*after write, iclass 24, count 0 2006.173.15:36:21.12#ibcon#*before return 0, iclass 24, count 0 2006.173.15:36:21.12#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.15:36:21.12#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.15:36:21.12#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.15:36:21.12#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.15:36:21.12$vck44/vblo=5,709.99 2006.173.15:36:21.12#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.15:36:21.12#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.15:36:21.12#ibcon#ireg 17 cls_cnt 0 2006.173.15:36:21.12#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.15:36:21.12#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.15:36:21.12#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.15:36:21.12#ibcon#enter wrdev, iclass 26, count 0 2006.173.15:36:21.12#ibcon#first serial, iclass 26, count 0 2006.173.15:36:21.12#ibcon#enter sib2, iclass 26, count 0 2006.173.15:36:21.12#ibcon#flushed, iclass 26, count 0 2006.173.15:36:21.12#ibcon#about to write, iclass 26, count 0 2006.173.15:36:21.12#ibcon#wrote, iclass 26, count 0 2006.173.15:36:21.12#ibcon#about to read 3, iclass 26, count 0 2006.173.15:36:21.14#ibcon#read 3, iclass 26, count 0 2006.173.15:36:21.14#ibcon#about to read 4, iclass 26, count 0 2006.173.15:36:21.14#ibcon#read 4, iclass 26, count 0 2006.173.15:36:21.14#ibcon#about to read 5, iclass 26, count 0 2006.173.15:36:21.14#ibcon#read 5, iclass 26, count 0 2006.173.15:36:21.14#ibcon#about to read 6, iclass 26, count 0 2006.173.15:36:21.14#ibcon#read 6, iclass 26, count 0 2006.173.15:36:21.14#ibcon#end of sib2, iclass 26, count 0 2006.173.15:36:21.14#ibcon#*mode == 0, iclass 26, count 0 2006.173.15:36:21.14#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.15:36:21.14#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.15:36:21.14#ibcon#*before write, iclass 26, count 0 2006.173.15:36:21.14#ibcon#enter sib2, iclass 26, count 0 2006.173.15:36:21.14#ibcon#flushed, iclass 26, count 0 2006.173.15:36:21.14#ibcon#about to write, iclass 26, count 0 2006.173.15:36:21.14#ibcon#wrote, iclass 26, count 0 2006.173.15:36:21.14#ibcon#about to read 3, iclass 26, count 0 2006.173.15:36:21.18#ibcon#read 3, iclass 26, count 0 2006.173.15:36:21.18#ibcon#about to read 4, iclass 26, count 0 2006.173.15:36:21.18#ibcon#read 4, iclass 26, count 0 2006.173.15:36:21.18#ibcon#about to read 5, iclass 26, count 0 2006.173.15:36:21.18#ibcon#read 5, iclass 26, count 0 2006.173.15:36:21.18#ibcon#about to read 6, iclass 26, count 0 2006.173.15:36:21.18#ibcon#read 6, iclass 26, count 0 2006.173.15:36:21.18#ibcon#end of sib2, iclass 26, count 0 2006.173.15:36:21.18#ibcon#*after write, iclass 26, count 0 2006.173.15:36:21.18#ibcon#*before return 0, iclass 26, count 0 2006.173.15:36:21.18#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.15:36:21.18#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.15:36:21.18#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.15:36:21.18#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.15:36:21.18$vck44/vb=5,4 2006.173.15:36:21.18#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.15:36:21.18#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.15:36:21.18#ibcon#ireg 11 cls_cnt 2 2006.173.15:36:21.18#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.15:36:21.24#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.15:36:21.24#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.15:36:21.24#ibcon#enter wrdev, iclass 28, count 2 2006.173.15:36:21.24#ibcon#first serial, iclass 28, count 2 2006.173.15:36:21.24#ibcon#enter sib2, iclass 28, count 2 2006.173.15:36:21.24#ibcon#flushed, iclass 28, count 2 2006.173.15:36:21.24#ibcon#about to write, iclass 28, count 2 2006.173.15:36:21.24#ibcon#wrote, iclass 28, count 2 2006.173.15:36:21.24#ibcon#about to read 3, iclass 28, count 2 2006.173.15:36:21.26#ibcon#read 3, iclass 28, count 2 2006.173.15:36:21.26#ibcon#about to read 4, iclass 28, count 2 2006.173.15:36:21.26#ibcon#read 4, iclass 28, count 2 2006.173.15:36:21.26#ibcon#about to read 5, iclass 28, count 2 2006.173.15:36:21.26#ibcon#read 5, iclass 28, count 2 2006.173.15:36:21.26#ibcon#about to read 6, iclass 28, count 2 2006.173.15:36:21.26#ibcon#read 6, iclass 28, count 2 2006.173.15:36:21.26#ibcon#end of sib2, iclass 28, count 2 2006.173.15:36:21.26#ibcon#*mode == 0, iclass 28, count 2 2006.173.15:36:21.26#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.15:36:21.26#ibcon#[27=AT05-04\r\n] 2006.173.15:36:21.26#ibcon#*before write, iclass 28, count 2 2006.173.15:36:21.26#ibcon#enter sib2, iclass 28, count 2 2006.173.15:36:21.26#ibcon#flushed, iclass 28, count 2 2006.173.15:36:21.26#ibcon#about to write, iclass 28, count 2 2006.173.15:36:21.26#ibcon#wrote, iclass 28, count 2 2006.173.15:36:21.26#ibcon#about to read 3, iclass 28, count 2 2006.173.15:36:21.29#ibcon#read 3, iclass 28, count 2 2006.173.15:36:21.29#ibcon#about to read 4, iclass 28, count 2 2006.173.15:36:21.29#ibcon#read 4, iclass 28, count 2 2006.173.15:36:21.29#ibcon#about to read 5, iclass 28, count 2 2006.173.15:36:21.29#ibcon#read 5, iclass 28, count 2 2006.173.15:36:21.29#ibcon#about to read 6, iclass 28, count 2 2006.173.15:36:21.29#ibcon#read 6, iclass 28, count 2 2006.173.15:36:21.29#ibcon#end of sib2, iclass 28, count 2 2006.173.15:36:21.29#ibcon#*after write, iclass 28, count 2 2006.173.15:36:21.29#ibcon#*before return 0, iclass 28, count 2 2006.173.15:36:21.29#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.15:36:21.29#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.15:36:21.29#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.15:36:21.29#ibcon#ireg 7 cls_cnt 0 2006.173.15:36:21.29#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.15:36:21.41#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.15:36:21.41#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.15:36:21.41#ibcon#enter wrdev, iclass 28, count 0 2006.173.15:36:21.41#ibcon#first serial, iclass 28, count 0 2006.173.15:36:21.41#ibcon#enter sib2, iclass 28, count 0 2006.173.15:36:21.41#ibcon#flushed, iclass 28, count 0 2006.173.15:36:21.41#ibcon#about to write, iclass 28, count 0 2006.173.15:36:21.41#ibcon#wrote, iclass 28, count 0 2006.173.15:36:21.41#ibcon#about to read 3, iclass 28, count 0 2006.173.15:36:21.43#ibcon#read 3, iclass 28, count 0 2006.173.15:36:21.43#ibcon#about to read 4, iclass 28, count 0 2006.173.15:36:21.43#ibcon#read 4, iclass 28, count 0 2006.173.15:36:21.43#ibcon#about to read 5, iclass 28, count 0 2006.173.15:36:21.43#ibcon#read 5, iclass 28, count 0 2006.173.15:36:21.43#ibcon#about to read 6, iclass 28, count 0 2006.173.15:36:21.43#ibcon#read 6, iclass 28, count 0 2006.173.15:36:21.43#ibcon#end of sib2, iclass 28, count 0 2006.173.15:36:21.43#ibcon#*mode == 0, iclass 28, count 0 2006.173.15:36:21.43#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.15:36:21.43#ibcon#[27=USB\r\n] 2006.173.15:36:21.43#ibcon#*before write, iclass 28, count 0 2006.173.15:36:21.43#ibcon#enter sib2, iclass 28, count 0 2006.173.15:36:21.43#ibcon#flushed, iclass 28, count 0 2006.173.15:36:21.43#ibcon#about to write, iclass 28, count 0 2006.173.15:36:21.43#ibcon#wrote, iclass 28, count 0 2006.173.15:36:21.43#ibcon#about to read 3, iclass 28, count 0 2006.173.15:36:21.46#ibcon#read 3, iclass 28, count 0 2006.173.15:36:21.46#ibcon#about to read 4, iclass 28, count 0 2006.173.15:36:21.46#ibcon#read 4, iclass 28, count 0 2006.173.15:36:21.46#ibcon#about to read 5, iclass 28, count 0 2006.173.15:36:21.46#ibcon#read 5, iclass 28, count 0 2006.173.15:36:21.46#ibcon#about to read 6, iclass 28, count 0 2006.173.15:36:21.46#ibcon#read 6, iclass 28, count 0 2006.173.15:36:21.46#ibcon#end of sib2, iclass 28, count 0 2006.173.15:36:21.46#ibcon#*after write, iclass 28, count 0 2006.173.15:36:21.46#ibcon#*before return 0, iclass 28, count 0 2006.173.15:36:21.46#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.15:36:21.46#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.15:36:21.46#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.15:36:21.46#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.15:36:21.46$vck44/vblo=6,719.99 2006.173.15:36:21.46#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.15:36:21.46#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.15:36:21.46#ibcon#ireg 17 cls_cnt 0 2006.173.15:36:21.46#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.15:36:21.46#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.15:36:21.46#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.15:36:21.46#ibcon#enter wrdev, iclass 30, count 0 2006.173.15:36:21.46#ibcon#first serial, iclass 30, count 0 2006.173.15:36:21.46#ibcon#enter sib2, iclass 30, count 0 2006.173.15:36:21.46#ibcon#flushed, iclass 30, count 0 2006.173.15:36:21.46#ibcon#about to write, iclass 30, count 0 2006.173.15:36:21.46#ibcon#wrote, iclass 30, count 0 2006.173.15:36:21.46#ibcon#about to read 3, iclass 30, count 0 2006.173.15:36:21.48#ibcon#read 3, iclass 30, count 0 2006.173.15:36:21.48#ibcon#about to read 4, iclass 30, count 0 2006.173.15:36:21.48#ibcon#read 4, iclass 30, count 0 2006.173.15:36:21.48#ibcon#about to read 5, iclass 30, count 0 2006.173.15:36:21.48#ibcon#read 5, iclass 30, count 0 2006.173.15:36:21.48#ibcon#about to read 6, iclass 30, count 0 2006.173.15:36:21.48#ibcon#read 6, iclass 30, count 0 2006.173.15:36:21.48#ibcon#end of sib2, iclass 30, count 0 2006.173.15:36:21.48#ibcon#*mode == 0, iclass 30, count 0 2006.173.15:36:21.48#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.15:36:21.48#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.15:36:21.48#ibcon#*before write, iclass 30, count 0 2006.173.15:36:21.48#ibcon#enter sib2, iclass 30, count 0 2006.173.15:36:21.48#ibcon#flushed, iclass 30, count 0 2006.173.15:36:21.48#ibcon#about to write, iclass 30, count 0 2006.173.15:36:21.48#ibcon#wrote, iclass 30, count 0 2006.173.15:36:21.48#ibcon#about to read 3, iclass 30, count 0 2006.173.15:36:21.52#ibcon#read 3, iclass 30, count 0 2006.173.15:36:21.52#ibcon#about to read 4, iclass 30, count 0 2006.173.15:36:21.52#ibcon#read 4, iclass 30, count 0 2006.173.15:36:21.52#ibcon#about to read 5, iclass 30, count 0 2006.173.15:36:21.52#ibcon#read 5, iclass 30, count 0 2006.173.15:36:21.52#ibcon#about to read 6, iclass 30, count 0 2006.173.15:36:21.52#ibcon#read 6, iclass 30, count 0 2006.173.15:36:21.52#ibcon#end of sib2, iclass 30, count 0 2006.173.15:36:21.52#ibcon#*after write, iclass 30, count 0 2006.173.15:36:21.52#ibcon#*before return 0, iclass 30, count 0 2006.173.15:36:21.52#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.15:36:21.52#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.15:36:21.52#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.15:36:21.52#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.15:36:21.52$vck44/vb=6,4 2006.173.15:36:21.52#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.173.15:36:21.52#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.173.15:36:21.52#ibcon#ireg 11 cls_cnt 2 2006.173.15:36:21.52#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.15:36:21.58#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.15:36:21.58#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.15:36:21.58#ibcon#enter wrdev, iclass 32, count 2 2006.173.15:36:21.58#ibcon#first serial, iclass 32, count 2 2006.173.15:36:21.58#ibcon#enter sib2, iclass 32, count 2 2006.173.15:36:21.58#ibcon#flushed, iclass 32, count 2 2006.173.15:36:21.58#ibcon#about to write, iclass 32, count 2 2006.173.15:36:21.58#ibcon#wrote, iclass 32, count 2 2006.173.15:36:21.58#ibcon#about to read 3, iclass 32, count 2 2006.173.15:36:21.60#ibcon#read 3, iclass 32, count 2 2006.173.15:36:21.60#ibcon#about to read 4, iclass 32, count 2 2006.173.15:36:21.60#ibcon#read 4, iclass 32, count 2 2006.173.15:36:21.60#ibcon#about to read 5, iclass 32, count 2 2006.173.15:36:21.60#ibcon#read 5, iclass 32, count 2 2006.173.15:36:21.60#ibcon#about to read 6, iclass 32, count 2 2006.173.15:36:21.60#ibcon#read 6, iclass 32, count 2 2006.173.15:36:21.60#ibcon#end of sib2, iclass 32, count 2 2006.173.15:36:21.60#ibcon#*mode == 0, iclass 32, count 2 2006.173.15:36:21.60#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.173.15:36:21.60#ibcon#[27=AT06-04\r\n] 2006.173.15:36:21.60#ibcon#*before write, iclass 32, count 2 2006.173.15:36:21.60#ibcon#enter sib2, iclass 32, count 2 2006.173.15:36:21.60#ibcon#flushed, iclass 32, count 2 2006.173.15:36:21.60#ibcon#about to write, iclass 32, count 2 2006.173.15:36:21.60#ibcon#wrote, iclass 32, count 2 2006.173.15:36:21.60#ibcon#about to read 3, iclass 32, count 2 2006.173.15:36:21.63#ibcon#read 3, iclass 32, count 2 2006.173.15:36:21.63#ibcon#about to read 4, iclass 32, count 2 2006.173.15:36:21.63#ibcon#read 4, iclass 32, count 2 2006.173.15:36:21.63#ibcon#about to read 5, iclass 32, count 2 2006.173.15:36:21.63#ibcon#read 5, iclass 32, count 2 2006.173.15:36:21.63#ibcon#about to read 6, iclass 32, count 2 2006.173.15:36:21.63#ibcon#read 6, iclass 32, count 2 2006.173.15:36:21.63#ibcon#end of sib2, iclass 32, count 2 2006.173.15:36:21.63#ibcon#*after write, iclass 32, count 2 2006.173.15:36:21.63#ibcon#*before return 0, iclass 32, count 2 2006.173.15:36:21.63#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.15:36:21.63#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.173.15:36:21.63#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.173.15:36:21.63#ibcon#ireg 7 cls_cnt 0 2006.173.15:36:21.63#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.15:36:21.75#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.15:36:21.75#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.15:36:21.75#ibcon#enter wrdev, iclass 32, count 0 2006.173.15:36:21.75#ibcon#first serial, iclass 32, count 0 2006.173.15:36:21.75#ibcon#enter sib2, iclass 32, count 0 2006.173.15:36:21.75#ibcon#flushed, iclass 32, count 0 2006.173.15:36:21.75#ibcon#about to write, iclass 32, count 0 2006.173.15:36:21.75#ibcon#wrote, iclass 32, count 0 2006.173.15:36:21.75#ibcon#about to read 3, iclass 32, count 0 2006.173.15:36:21.77#ibcon#read 3, iclass 32, count 0 2006.173.15:36:21.77#ibcon#about to read 4, iclass 32, count 0 2006.173.15:36:21.77#ibcon#read 4, iclass 32, count 0 2006.173.15:36:21.77#ibcon#about to read 5, iclass 32, count 0 2006.173.15:36:21.77#ibcon#read 5, iclass 32, count 0 2006.173.15:36:21.77#ibcon#about to read 6, iclass 32, count 0 2006.173.15:36:21.77#ibcon#read 6, iclass 32, count 0 2006.173.15:36:21.77#ibcon#end of sib2, iclass 32, count 0 2006.173.15:36:21.77#ibcon#*mode == 0, iclass 32, count 0 2006.173.15:36:21.77#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.15:36:21.77#ibcon#[27=USB\r\n] 2006.173.15:36:21.77#ibcon#*before write, iclass 32, count 0 2006.173.15:36:21.77#ibcon#enter sib2, iclass 32, count 0 2006.173.15:36:21.77#ibcon#flushed, iclass 32, count 0 2006.173.15:36:21.77#ibcon#about to write, iclass 32, count 0 2006.173.15:36:21.77#ibcon#wrote, iclass 32, count 0 2006.173.15:36:21.77#ibcon#about to read 3, iclass 32, count 0 2006.173.15:36:21.80#ibcon#read 3, iclass 32, count 0 2006.173.15:36:21.80#ibcon#about to read 4, iclass 32, count 0 2006.173.15:36:21.80#ibcon#read 4, iclass 32, count 0 2006.173.15:36:21.80#ibcon#about to read 5, iclass 32, count 0 2006.173.15:36:21.80#ibcon#read 5, iclass 32, count 0 2006.173.15:36:21.80#ibcon#about to read 6, iclass 32, count 0 2006.173.15:36:21.80#ibcon#read 6, iclass 32, count 0 2006.173.15:36:21.80#ibcon#end of sib2, iclass 32, count 0 2006.173.15:36:21.80#ibcon#*after write, iclass 32, count 0 2006.173.15:36:21.80#ibcon#*before return 0, iclass 32, count 0 2006.173.15:36:21.80#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.15:36:21.80#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.173.15:36:21.80#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.15:36:21.80#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.15:36:21.80$vck44/vblo=7,734.99 2006.173.15:36:21.80#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.15:36:21.80#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.15:36:21.80#ibcon#ireg 17 cls_cnt 0 2006.173.15:36:21.80#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.15:36:21.80#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.15:36:21.80#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.15:36:21.80#ibcon#enter wrdev, iclass 34, count 0 2006.173.15:36:21.80#ibcon#first serial, iclass 34, count 0 2006.173.15:36:21.80#ibcon#enter sib2, iclass 34, count 0 2006.173.15:36:21.80#ibcon#flushed, iclass 34, count 0 2006.173.15:36:21.80#ibcon#about to write, iclass 34, count 0 2006.173.15:36:21.80#ibcon#wrote, iclass 34, count 0 2006.173.15:36:21.80#ibcon#about to read 3, iclass 34, count 0 2006.173.15:36:21.82#ibcon#read 3, iclass 34, count 0 2006.173.15:36:21.82#ibcon#about to read 4, iclass 34, count 0 2006.173.15:36:21.82#ibcon#read 4, iclass 34, count 0 2006.173.15:36:21.82#ibcon#about to read 5, iclass 34, count 0 2006.173.15:36:21.82#ibcon#read 5, iclass 34, count 0 2006.173.15:36:21.82#ibcon#about to read 6, iclass 34, count 0 2006.173.15:36:21.82#ibcon#read 6, iclass 34, count 0 2006.173.15:36:21.82#ibcon#end of sib2, iclass 34, count 0 2006.173.15:36:21.82#ibcon#*mode == 0, iclass 34, count 0 2006.173.15:36:21.82#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.15:36:21.82#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.15:36:21.82#ibcon#*before write, iclass 34, count 0 2006.173.15:36:21.82#ibcon#enter sib2, iclass 34, count 0 2006.173.15:36:21.82#ibcon#flushed, iclass 34, count 0 2006.173.15:36:21.82#ibcon#about to write, iclass 34, count 0 2006.173.15:36:21.82#ibcon#wrote, iclass 34, count 0 2006.173.15:36:21.82#ibcon#about to read 3, iclass 34, count 0 2006.173.15:36:21.86#ibcon#read 3, iclass 34, count 0 2006.173.15:36:21.86#ibcon#about to read 4, iclass 34, count 0 2006.173.15:36:21.86#ibcon#read 4, iclass 34, count 0 2006.173.15:36:21.86#ibcon#about to read 5, iclass 34, count 0 2006.173.15:36:21.86#ibcon#read 5, iclass 34, count 0 2006.173.15:36:21.86#ibcon#about to read 6, iclass 34, count 0 2006.173.15:36:21.86#ibcon#read 6, iclass 34, count 0 2006.173.15:36:21.86#ibcon#end of sib2, iclass 34, count 0 2006.173.15:36:21.86#ibcon#*after write, iclass 34, count 0 2006.173.15:36:21.86#ibcon#*before return 0, iclass 34, count 0 2006.173.15:36:21.86#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.15:36:21.86#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.15:36:21.86#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.15:36:21.86#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.15:36:21.86$vck44/vb=7,4 2006.173.15:36:21.86#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.15:36:21.86#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.15:36:21.86#ibcon#ireg 11 cls_cnt 2 2006.173.15:36:21.86#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.15:36:21.92#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.15:36:21.92#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.15:36:21.92#ibcon#enter wrdev, iclass 36, count 2 2006.173.15:36:21.92#ibcon#first serial, iclass 36, count 2 2006.173.15:36:21.92#ibcon#enter sib2, iclass 36, count 2 2006.173.15:36:21.92#ibcon#flushed, iclass 36, count 2 2006.173.15:36:21.92#ibcon#about to write, iclass 36, count 2 2006.173.15:36:21.92#ibcon#wrote, iclass 36, count 2 2006.173.15:36:21.92#ibcon#about to read 3, iclass 36, count 2 2006.173.15:36:21.94#ibcon#read 3, iclass 36, count 2 2006.173.15:36:21.94#ibcon#about to read 4, iclass 36, count 2 2006.173.15:36:21.94#ibcon#read 4, iclass 36, count 2 2006.173.15:36:21.94#ibcon#about to read 5, iclass 36, count 2 2006.173.15:36:21.94#ibcon#read 5, iclass 36, count 2 2006.173.15:36:21.94#ibcon#about to read 6, iclass 36, count 2 2006.173.15:36:21.94#ibcon#read 6, iclass 36, count 2 2006.173.15:36:21.94#ibcon#end of sib2, iclass 36, count 2 2006.173.15:36:21.94#ibcon#*mode == 0, iclass 36, count 2 2006.173.15:36:21.94#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.15:36:21.94#ibcon#[27=AT07-04\r\n] 2006.173.15:36:21.94#ibcon#*before write, iclass 36, count 2 2006.173.15:36:21.94#ibcon#enter sib2, iclass 36, count 2 2006.173.15:36:21.94#ibcon#flushed, iclass 36, count 2 2006.173.15:36:21.94#ibcon#about to write, iclass 36, count 2 2006.173.15:36:21.94#ibcon#wrote, iclass 36, count 2 2006.173.15:36:21.94#ibcon#about to read 3, iclass 36, count 2 2006.173.15:36:21.97#ibcon#read 3, iclass 36, count 2 2006.173.15:36:21.97#ibcon#about to read 4, iclass 36, count 2 2006.173.15:36:21.97#ibcon#read 4, iclass 36, count 2 2006.173.15:36:21.97#ibcon#about to read 5, iclass 36, count 2 2006.173.15:36:21.97#ibcon#read 5, iclass 36, count 2 2006.173.15:36:21.97#ibcon#about to read 6, iclass 36, count 2 2006.173.15:36:21.97#ibcon#read 6, iclass 36, count 2 2006.173.15:36:21.97#ibcon#end of sib2, iclass 36, count 2 2006.173.15:36:21.97#ibcon#*after write, iclass 36, count 2 2006.173.15:36:21.97#ibcon#*before return 0, iclass 36, count 2 2006.173.15:36:21.97#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.15:36:21.97#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.15:36:21.97#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.15:36:21.97#ibcon#ireg 7 cls_cnt 0 2006.173.15:36:21.97#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.15:36:22.09#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.15:36:22.09#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.15:36:22.09#ibcon#enter wrdev, iclass 36, count 0 2006.173.15:36:22.09#ibcon#first serial, iclass 36, count 0 2006.173.15:36:22.09#ibcon#enter sib2, iclass 36, count 0 2006.173.15:36:22.09#ibcon#flushed, iclass 36, count 0 2006.173.15:36:22.09#ibcon#about to write, iclass 36, count 0 2006.173.15:36:22.09#ibcon#wrote, iclass 36, count 0 2006.173.15:36:22.09#ibcon#about to read 3, iclass 36, count 0 2006.173.15:36:22.11#ibcon#read 3, iclass 36, count 0 2006.173.15:36:22.11#ibcon#about to read 4, iclass 36, count 0 2006.173.15:36:22.11#ibcon#read 4, iclass 36, count 0 2006.173.15:36:22.11#ibcon#about to read 5, iclass 36, count 0 2006.173.15:36:22.11#ibcon#read 5, iclass 36, count 0 2006.173.15:36:22.11#ibcon#about to read 6, iclass 36, count 0 2006.173.15:36:22.11#ibcon#read 6, iclass 36, count 0 2006.173.15:36:22.11#ibcon#end of sib2, iclass 36, count 0 2006.173.15:36:22.11#ibcon#*mode == 0, iclass 36, count 0 2006.173.15:36:22.11#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.15:36:22.11#ibcon#[27=USB\r\n] 2006.173.15:36:22.11#ibcon#*before write, iclass 36, count 0 2006.173.15:36:22.11#ibcon#enter sib2, iclass 36, count 0 2006.173.15:36:22.11#ibcon#flushed, iclass 36, count 0 2006.173.15:36:22.11#ibcon#about to write, iclass 36, count 0 2006.173.15:36:22.11#ibcon#wrote, iclass 36, count 0 2006.173.15:36:22.11#ibcon#about to read 3, iclass 36, count 0 2006.173.15:36:22.14#ibcon#read 3, iclass 36, count 0 2006.173.15:36:22.14#ibcon#about to read 4, iclass 36, count 0 2006.173.15:36:22.14#ibcon#read 4, iclass 36, count 0 2006.173.15:36:22.14#ibcon#about to read 5, iclass 36, count 0 2006.173.15:36:22.14#ibcon#read 5, iclass 36, count 0 2006.173.15:36:22.14#ibcon#about to read 6, iclass 36, count 0 2006.173.15:36:22.14#ibcon#read 6, iclass 36, count 0 2006.173.15:36:22.14#ibcon#end of sib2, iclass 36, count 0 2006.173.15:36:22.14#ibcon#*after write, iclass 36, count 0 2006.173.15:36:22.14#ibcon#*before return 0, iclass 36, count 0 2006.173.15:36:22.14#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.15:36:22.14#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.15:36:22.14#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.15:36:22.14#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.15:36:22.14$vck44/vblo=8,744.99 2006.173.15:36:22.14#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.15:36:22.14#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.15:36:22.14#ibcon#ireg 17 cls_cnt 0 2006.173.15:36:22.14#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.15:36:22.14#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.15:36:22.14#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.15:36:22.14#ibcon#enter wrdev, iclass 38, count 0 2006.173.15:36:22.14#ibcon#first serial, iclass 38, count 0 2006.173.15:36:22.14#ibcon#enter sib2, iclass 38, count 0 2006.173.15:36:22.14#ibcon#flushed, iclass 38, count 0 2006.173.15:36:22.14#ibcon#about to write, iclass 38, count 0 2006.173.15:36:22.14#ibcon#wrote, iclass 38, count 0 2006.173.15:36:22.14#ibcon#about to read 3, iclass 38, count 0 2006.173.15:36:22.16#ibcon#read 3, iclass 38, count 0 2006.173.15:36:22.16#ibcon#about to read 4, iclass 38, count 0 2006.173.15:36:22.16#ibcon#read 4, iclass 38, count 0 2006.173.15:36:22.16#ibcon#about to read 5, iclass 38, count 0 2006.173.15:36:22.16#ibcon#read 5, iclass 38, count 0 2006.173.15:36:22.16#ibcon#about to read 6, iclass 38, count 0 2006.173.15:36:22.16#ibcon#read 6, iclass 38, count 0 2006.173.15:36:22.16#ibcon#end of sib2, iclass 38, count 0 2006.173.15:36:22.16#ibcon#*mode == 0, iclass 38, count 0 2006.173.15:36:22.16#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.15:36:22.16#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.15:36:22.16#ibcon#*before write, iclass 38, count 0 2006.173.15:36:22.16#ibcon#enter sib2, iclass 38, count 0 2006.173.15:36:22.16#ibcon#flushed, iclass 38, count 0 2006.173.15:36:22.16#ibcon#about to write, iclass 38, count 0 2006.173.15:36:22.16#ibcon#wrote, iclass 38, count 0 2006.173.15:36:22.16#ibcon#about to read 3, iclass 38, count 0 2006.173.15:36:22.20#ibcon#read 3, iclass 38, count 0 2006.173.15:36:22.20#ibcon#about to read 4, iclass 38, count 0 2006.173.15:36:22.20#ibcon#read 4, iclass 38, count 0 2006.173.15:36:22.20#ibcon#about to read 5, iclass 38, count 0 2006.173.15:36:22.20#ibcon#read 5, iclass 38, count 0 2006.173.15:36:22.20#ibcon#about to read 6, iclass 38, count 0 2006.173.15:36:22.20#ibcon#read 6, iclass 38, count 0 2006.173.15:36:22.20#ibcon#end of sib2, iclass 38, count 0 2006.173.15:36:22.20#ibcon#*after write, iclass 38, count 0 2006.173.15:36:22.20#ibcon#*before return 0, iclass 38, count 0 2006.173.15:36:22.20#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.15:36:22.20#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.15:36:22.20#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.15:36:22.20#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.15:36:22.20$vck44/vb=8,4 2006.173.15:36:22.20#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.15:36:22.20#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.15:36:22.20#ibcon#ireg 11 cls_cnt 2 2006.173.15:36:22.20#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.15:36:22.26#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.15:36:22.26#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.15:36:22.26#ibcon#enter wrdev, iclass 40, count 2 2006.173.15:36:22.26#ibcon#first serial, iclass 40, count 2 2006.173.15:36:22.26#ibcon#enter sib2, iclass 40, count 2 2006.173.15:36:22.26#ibcon#flushed, iclass 40, count 2 2006.173.15:36:22.26#ibcon#about to write, iclass 40, count 2 2006.173.15:36:22.26#ibcon#wrote, iclass 40, count 2 2006.173.15:36:22.26#ibcon#about to read 3, iclass 40, count 2 2006.173.15:36:22.28#ibcon#read 3, iclass 40, count 2 2006.173.15:36:22.28#ibcon#about to read 4, iclass 40, count 2 2006.173.15:36:22.28#ibcon#read 4, iclass 40, count 2 2006.173.15:36:22.28#ibcon#about to read 5, iclass 40, count 2 2006.173.15:36:22.28#ibcon#read 5, iclass 40, count 2 2006.173.15:36:22.28#ibcon#about to read 6, iclass 40, count 2 2006.173.15:36:22.28#ibcon#read 6, iclass 40, count 2 2006.173.15:36:22.28#ibcon#end of sib2, iclass 40, count 2 2006.173.15:36:22.28#ibcon#*mode == 0, iclass 40, count 2 2006.173.15:36:22.28#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.15:36:22.28#ibcon#[27=AT08-04\r\n] 2006.173.15:36:22.28#ibcon#*before write, iclass 40, count 2 2006.173.15:36:22.28#ibcon#enter sib2, iclass 40, count 2 2006.173.15:36:22.28#ibcon#flushed, iclass 40, count 2 2006.173.15:36:22.28#ibcon#about to write, iclass 40, count 2 2006.173.15:36:22.28#ibcon#wrote, iclass 40, count 2 2006.173.15:36:22.28#ibcon#about to read 3, iclass 40, count 2 2006.173.15:36:22.31#ibcon#read 3, iclass 40, count 2 2006.173.15:36:22.31#ibcon#about to read 4, iclass 40, count 2 2006.173.15:36:22.31#ibcon#read 4, iclass 40, count 2 2006.173.15:36:22.31#ibcon#about to read 5, iclass 40, count 2 2006.173.15:36:22.31#ibcon#read 5, iclass 40, count 2 2006.173.15:36:22.31#ibcon#about to read 6, iclass 40, count 2 2006.173.15:36:22.31#ibcon#read 6, iclass 40, count 2 2006.173.15:36:22.31#ibcon#end of sib2, iclass 40, count 2 2006.173.15:36:22.31#ibcon#*after write, iclass 40, count 2 2006.173.15:36:22.31#ibcon#*before return 0, iclass 40, count 2 2006.173.15:36:22.31#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.15:36:22.31#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.15:36:22.31#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.15:36:22.31#ibcon#ireg 7 cls_cnt 0 2006.173.15:36:22.31#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.15:36:22.43#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.15:36:22.43#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.15:36:22.43#ibcon#enter wrdev, iclass 40, count 0 2006.173.15:36:22.43#ibcon#first serial, iclass 40, count 0 2006.173.15:36:22.43#ibcon#enter sib2, iclass 40, count 0 2006.173.15:36:22.43#ibcon#flushed, iclass 40, count 0 2006.173.15:36:22.43#ibcon#about to write, iclass 40, count 0 2006.173.15:36:22.43#ibcon#wrote, iclass 40, count 0 2006.173.15:36:22.43#ibcon#about to read 3, iclass 40, count 0 2006.173.15:36:22.45#ibcon#read 3, iclass 40, count 0 2006.173.15:36:22.45#ibcon#about to read 4, iclass 40, count 0 2006.173.15:36:22.45#ibcon#read 4, iclass 40, count 0 2006.173.15:36:22.45#ibcon#about to read 5, iclass 40, count 0 2006.173.15:36:22.45#ibcon#read 5, iclass 40, count 0 2006.173.15:36:22.45#ibcon#about to read 6, iclass 40, count 0 2006.173.15:36:22.45#ibcon#read 6, iclass 40, count 0 2006.173.15:36:22.45#ibcon#end of sib2, iclass 40, count 0 2006.173.15:36:22.45#ibcon#*mode == 0, iclass 40, count 0 2006.173.15:36:22.45#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.15:36:22.45#ibcon#[27=USB\r\n] 2006.173.15:36:22.45#ibcon#*before write, iclass 40, count 0 2006.173.15:36:22.45#ibcon#enter sib2, iclass 40, count 0 2006.173.15:36:22.45#ibcon#flushed, iclass 40, count 0 2006.173.15:36:22.45#ibcon#about to write, iclass 40, count 0 2006.173.15:36:22.45#ibcon#wrote, iclass 40, count 0 2006.173.15:36:22.45#ibcon#about to read 3, iclass 40, count 0 2006.173.15:36:22.48#ibcon#read 3, iclass 40, count 0 2006.173.15:36:22.48#ibcon#about to read 4, iclass 40, count 0 2006.173.15:36:22.48#ibcon#read 4, iclass 40, count 0 2006.173.15:36:22.48#ibcon#about to read 5, iclass 40, count 0 2006.173.15:36:22.48#ibcon#read 5, iclass 40, count 0 2006.173.15:36:22.48#ibcon#about to read 6, iclass 40, count 0 2006.173.15:36:22.48#ibcon#read 6, iclass 40, count 0 2006.173.15:36:22.48#ibcon#end of sib2, iclass 40, count 0 2006.173.15:36:22.48#ibcon#*after write, iclass 40, count 0 2006.173.15:36:22.48#ibcon#*before return 0, iclass 40, count 0 2006.173.15:36:22.48#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.15:36:22.48#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.15:36:22.48#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.15:36:22.48#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.15:36:22.48$vck44/vabw=wide 2006.173.15:36:22.48#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.15:36:22.48#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.15:36:22.48#ibcon#ireg 8 cls_cnt 0 2006.173.15:36:22.48#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.15:36:22.48#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.15:36:22.48#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.15:36:22.48#ibcon#enter wrdev, iclass 4, count 0 2006.173.15:36:22.48#ibcon#first serial, iclass 4, count 0 2006.173.15:36:22.48#ibcon#enter sib2, iclass 4, count 0 2006.173.15:36:22.48#ibcon#flushed, iclass 4, count 0 2006.173.15:36:22.48#ibcon#about to write, iclass 4, count 0 2006.173.15:36:22.48#ibcon#wrote, iclass 4, count 0 2006.173.15:36:22.48#ibcon#about to read 3, iclass 4, count 0 2006.173.15:36:22.50#ibcon#read 3, iclass 4, count 0 2006.173.15:36:22.50#ibcon#about to read 4, iclass 4, count 0 2006.173.15:36:22.50#ibcon#read 4, iclass 4, count 0 2006.173.15:36:22.50#ibcon#about to read 5, iclass 4, count 0 2006.173.15:36:22.50#ibcon#read 5, iclass 4, count 0 2006.173.15:36:22.50#ibcon#about to read 6, iclass 4, count 0 2006.173.15:36:22.50#ibcon#read 6, iclass 4, count 0 2006.173.15:36:22.50#ibcon#end of sib2, iclass 4, count 0 2006.173.15:36:22.50#ibcon#*mode == 0, iclass 4, count 0 2006.173.15:36:22.50#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.15:36:22.50#ibcon#[25=BW32\r\n] 2006.173.15:36:22.50#ibcon#*before write, iclass 4, count 0 2006.173.15:36:22.50#ibcon#enter sib2, iclass 4, count 0 2006.173.15:36:22.50#ibcon#flushed, iclass 4, count 0 2006.173.15:36:22.50#ibcon#about to write, iclass 4, count 0 2006.173.15:36:22.50#ibcon#wrote, iclass 4, count 0 2006.173.15:36:22.50#ibcon#about to read 3, iclass 4, count 0 2006.173.15:36:22.53#ibcon#read 3, iclass 4, count 0 2006.173.15:36:22.53#ibcon#about to read 4, iclass 4, count 0 2006.173.15:36:22.53#ibcon#read 4, iclass 4, count 0 2006.173.15:36:22.53#ibcon#about to read 5, iclass 4, count 0 2006.173.15:36:22.53#ibcon#read 5, iclass 4, count 0 2006.173.15:36:22.53#ibcon#about to read 6, iclass 4, count 0 2006.173.15:36:22.53#ibcon#read 6, iclass 4, count 0 2006.173.15:36:22.53#ibcon#end of sib2, iclass 4, count 0 2006.173.15:36:22.53#ibcon#*after write, iclass 4, count 0 2006.173.15:36:22.53#ibcon#*before return 0, iclass 4, count 0 2006.173.15:36:22.53#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.15:36:22.53#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.15:36:22.53#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.15:36:22.53#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.15:36:22.53$vck44/vbbw=wide 2006.173.15:36:22.53#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.15:36:22.53#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.15:36:22.53#ibcon#ireg 8 cls_cnt 0 2006.173.15:36:22.53#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.15:36:22.60#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.15:36:22.60#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.15:36:22.60#ibcon#enter wrdev, iclass 6, count 0 2006.173.15:36:22.60#ibcon#first serial, iclass 6, count 0 2006.173.15:36:22.60#ibcon#enter sib2, iclass 6, count 0 2006.173.15:36:22.60#ibcon#flushed, iclass 6, count 0 2006.173.15:36:22.60#ibcon#about to write, iclass 6, count 0 2006.173.15:36:22.60#ibcon#wrote, iclass 6, count 0 2006.173.15:36:22.60#ibcon#about to read 3, iclass 6, count 0 2006.173.15:36:22.62#ibcon#read 3, iclass 6, count 0 2006.173.15:36:22.62#ibcon#about to read 4, iclass 6, count 0 2006.173.15:36:22.62#ibcon#read 4, iclass 6, count 0 2006.173.15:36:22.62#ibcon#about to read 5, iclass 6, count 0 2006.173.15:36:22.62#ibcon#read 5, iclass 6, count 0 2006.173.15:36:22.62#ibcon#about to read 6, iclass 6, count 0 2006.173.15:36:22.62#ibcon#read 6, iclass 6, count 0 2006.173.15:36:22.62#ibcon#end of sib2, iclass 6, count 0 2006.173.15:36:22.62#ibcon#*mode == 0, iclass 6, count 0 2006.173.15:36:22.62#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.15:36:22.62#ibcon#[27=BW32\r\n] 2006.173.15:36:22.62#ibcon#*before write, iclass 6, count 0 2006.173.15:36:22.62#ibcon#enter sib2, iclass 6, count 0 2006.173.15:36:22.62#ibcon#flushed, iclass 6, count 0 2006.173.15:36:22.62#ibcon#about to write, iclass 6, count 0 2006.173.15:36:22.62#ibcon#wrote, iclass 6, count 0 2006.173.15:36:22.62#ibcon#about to read 3, iclass 6, count 0 2006.173.15:36:22.65#ibcon#read 3, iclass 6, count 0 2006.173.15:36:22.65#ibcon#about to read 4, iclass 6, count 0 2006.173.15:36:22.65#ibcon#read 4, iclass 6, count 0 2006.173.15:36:22.65#ibcon#about to read 5, iclass 6, count 0 2006.173.15:36:22.65#ibcon#read 5, iclass 6, count 0 2006.173.15:36:22.65#ibcon#about to read 6, iclass 6, count 0 2006.173.15:36:22.65#ibcon#read 6, iclass 6, count 0 2006.173.15:36:22.65#ibcon#end of sib2, iclass 6, count 0 2006.173.15:36:22.65#ibcon#*after write, iclass 6, count 0 2006.173.15:36:22.65#ibcon#*before return 0, iclass 6, count 0 2006.173.15:36:22.65#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.15:36:22.65#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.15:36:22.65#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.15:36:22.65#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.15:36:22.65$setupk4/ifdk4 2006.173.15:36:22.65$ifdk4/lo= 2006.173.15:36:22.65$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.15:36:22.65$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.15:36:22.65$ifdk4/patch= 2006.173.15:36:22.65$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.15:36:22.65$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.15:36:22.65$setupk4/!*+20s 2006.173.15:36:29.14#trakl#Source acquired 2006.173.15:36:30.14#flagr#flagr/antenna,acquired 2006.173.15:36:30.85#abcon#<5=/14 1.5 3.4 21.001001002.9\r\n> 2006.173.15:36:30.87#abcon#{5=INTERFACE CLEAR} 2006.173.15:36:30.93#abcon#[5=S1D000X0/0*\r\n] 2006.173.15:36:37.16$setupk4/"tpicd 2006.173.15:36:37.16$setupk4/echo=off 2006.173.15:36:37.16$setupk4/xlog=off 2006.173.15:36:37.16:!2006.173.15:41:52 2006.173.15:41:52.00:preob 2006.173.15:41:52.14/onsource/TRACKING 2006.173.15:41:52.14:!2006.173.15:42:02 2006.173.15:42:02.00:"tape 2006.173.15:42:02.00:"st=record 2006.173.15:42:02.00:data_valid=on 2006.173.15:42:02.00:midob 2006.173.15:42:03.14/onsource/TRACKING 2006.173.15:42:03.14/wx/20.92,1003.0,100 2006.173.15:42:03.21/cable/+6.5084E-03 2006.173.15:42:04.30/va/01,07,usb,yes,35,38 2006.173.15:42:04.30/va/02,06,usb,yes,35,36 2006.173.15:42:04.30/va/03,05,usb,yes,45,46 2006.173.15:42:04.30/va/04,06,usb,yes,36,38 2006.173.15:42:04.30/va/05,04,usb,yes,28,29 2006.173.15:42:04.30/va/06,03,usb,yes,39,39 2006.173.15:42:04.30/va/07,04,usb,yes,32,33 2006.173.15:42:04.30/va/08,04,usb,yes,27,33 2006.173.15:42:04.53/valo/01,524.99,yes,locked 2006.173.15:42:04.53/valo/02,534.99,yes,locked 2006.173.15:42:04.53/valo/03,564.99,yes,locked 2006.173.15:42:04.53/valo/04,624.99,yes,locked 2006.173.15:42:04.53/valo/05,734.99,yes,locked 2006.173.15:42:04.53/valo/06,814.99,yes,locked 2006.173.15:42:04.53/valo/07,864.99,yes,locked 2006.173.15:42:04.53/valo/08,884.99,yes,locked 2006.173.15:42:05.62/vb/01,04,usb,yes,28,27 2006.173.15:42:05.62/vb/02,04,usb,yes,31,31 2006.173.15:42:05.62/vb/03,04,usb,yes,28,31 2006.173.15:42:05.62/vb/04,04,usb,yes,32,31 2006.173.15:42:05.62/vb/05,04,usb,yes,25,27 2006.173.15:42:05.62/vb/06,04,usb,yes,29,25 2006.173.15:42:05.62/vb/07,04,usb,yes,29,29 2006.173.15:42:05.62/vb/08,04,usb,yes,27,30 2006.173.15:42:05.85/vblo/01,629.99,yes,locked 2006.173.15:42:05.85/vblo/02,634.99,yes,locked 2006.173.15:42:05.85/vblo/03,649.99,yes,locked 2006.173.15:42:05.85/vblo/04,679.99,yes,locked 2006.173.15:42:05.85/vblo/05,709.99,yes,locked 2006.173.15:42:05.85/vblo/06,719.99,yes,locked 2006.173.15:42:05.85/vblo/07,734.99,yes,locked 2006.173.15:42:05.85/vblo/08,744.99,yes,locked 2006.173.15:42:06.00/vabw/8 2006.173.15:42:06.15/vbbw/8 2006.173.15:42:06.29/xfe/off,on,15.0 2006.173.15:42:06.66/ifatt/23,28,28,28 2006.173.15:42:07.07/fmout-gps/S +4.00E-07 2006.173.15:42:07.11:!2006.173.15:43:22 2006.173.15:43:22.00:data_valid=off 2006.173.15:43:22.00:"et 2006.173.15:43:22.00:!+3s 2006.173.15:43:25.01:"tape 2006.173.15:43:25.01:postob 2006.173.15:43:25.13/cable/+6.5093E-03 2006.173.15:43:25.13/wx/20.90,1003.0,100 2006.173.15:43:26.07/fmout-gps/S +4.01E-07 2006.173.15:43:26.07:scan_name=173-1547,jd0606,190 2006.173.15:43:26.07:source=3c446,222547.26,-045701.4,2000.0,cw 2006.173.15:43:27.13#flagr#flagr/antenna,new-source 2006.173.15:43:27.13:checkk5 2006.173.15:43:27.49/chk_autoobs//k5ts1/ autoobs is running! 2006.173.15:43:27.89/chk_autoobs//k5ts2/ autoobs is running! 2006.173.15:43:28.29/chk_autoobs//k5ts3/ autoobs is running! 2006.173.15:43:28.69/chk_autoobs//k5ts4/ autoobs is running! 2006.173.15:43:29.08/chk_obsdata//k5ts1/T1731542??a.dat file size is correct (nominal:320MB, actual:316MB). 2006.173.15:43:29.49/chk_obsdata//k5ts2/T1731542??b.dat file size is correct (nominal:320MB, actual:316MB). 2006.173.15:43:29.88/chk_obsdata//k5ts3/T1731542??c.dat file size is correct (nominal:320MB, actual:316MB). 2006.173.15:43:30.28/chk_obsdata//k5ts4/T1731542??d.dat file size is correct (nominal:320MB, actual:316MB). 2006.173.15:43:31.01/k5log//k5ts1_log_newline 2006.173.15:43:31.72/k5log//k5ts2_log_newline 2006.173.15:43:32.44/k5log//k5ts3_log_newline 2006.173.15:43:33.14/k5log//k5ts4_log_newline 2006.173.15:43:33.16/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.15:43:33.16:setupk4=1 2006.173.15:43:33.16$setupk4/echo=on 2006.173.15:43:33.16$setupk4/pcalon 2006.173.15:43:33.16$pcalon/"no phase cal control is implemented here 2006.173.15:43:33.16$setupk4/"tpicd=stop 2006.173.15:43:33.16$setupk4/"rec=synch_on 2006.173.15:43:33.16$setupk4/"rec_mode=128 2006.173.15:43:33.16$setupk4/!* 2006.173.15:43:33.16$setupk4/recpk4 2006.173.15:43:33.16$recpk4/recpatch= 2006.173.15:43:33.16$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.15:43:33.16$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.15:43:33.16$setupk4/vck44 2006.173.15:43:33.16$vck44/valo=1,524.99 2006.173.15:43:33.16#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.15:43:33.16#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.15:43:33.16#ibcon#ireg 17 cls_cnt 0 2006.173.15:43:33.16#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.15:43:33.16#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.15:43:33.16#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.15:43:33.16#ibcon#enter wrdev, iclass 37, count 0 2006.173.15:43:33.16#ibcon#first serial, iclass 37, count 0 2006.173.15:43:33.16#ibcon#enter sib2, iclass 37, count 0 2006.173.15:43:33.16#ibcon#flushed, iclass 37, count 0 2006.173.15:43:33.16#ibcon#about to write, iclass 37, count 0 2006.173.15:43:33.16#ibcon#wrote, iclass 37, count 0 2006.173.15:43:33.16#ibcon#about to read 3, iclass 37, count 0 2006.173.15:43:33.18#ibcon#read 3, iclass 37, count 0 2006.173.15:43:33.18#ibcon#about to read 4, iclass 37, count 0 2006.173.15:43:33.18#ibcon#read 4, iclass 37, count 0 2006.173.15:43:33.18#ibcon#about to read 5, iclass 37, count 0 2006.173.15:43:33.18#ibcon#read 5, iclass 37, count 0 2006.173.15:43:33.18#ibcon#about to read 6, iclass 37, count 0 2006.173.15:43:33.18#ibcon#read 6, iclass 37, count 0 2006.173.15:43:33.18#ibcon#end of sib2, iclass 37, count 0 2006.173.15:43:33.18#ibcon#*mode == 0, iclass 37, count 0 2006.173.15:43:33.18#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.15:43:33.18#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.15:43:33.18#ibcon#*before write, iclass 37, count 0 2006.173.15:43:33.18#ibcon#enter sib2, iclass 37, count 0 2006.173.15:43:33.18#ibcon#flushed, iclass 37, count 0 2006.173.15:43:33.18#ibcon#about to write, iclass 37, count 0 2006.173.15:43:33.18#ibcon#wrote, iclass 37, count 0 2006.173.15:43:33.18#ibcon#about to read 3, iclass 37, count 0 2006.173.15:43:33.23#ibcon#read 3, iclass 37, count 0 2006.173.15:43:33.23#ibcon#about to read 4, iclass 37, count 0 2006.173.15:43:33.23#ibcon#read 4, iclass 37, count 0 2006.173.15:43:33.23#ibcon#about to read 5, iclass 37, count 0 2006.173.15:43:33.23#ibcon#read 5, iclass 37, count 0 2006.173.15:43:33.23#ibcon#about to read 6, iclass 37, count 0 2006.173.15:43:33.23#ibcon#read 6, iclass 37, count 0 2006.173.15:43:33.23#ibcon#end of sib2, iclass 37, count 0 2006.173.15:43:33.23#ibcon#*after write, iclass 37, count 0 2006.173.15:43:33.23#ibcon#*before return 0, iclass 37, count 0 2006.173.15:43:33.23#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.15:43:33.23#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.15:43:33.23#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.15:43:33.23#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.15:43:33.23$vck44/va=1,7 2006.173.15:43:33.23#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.15:43:33.23#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.15:43:33.23#ibcon#ireg 11 cls_cnt 2 2006.173.15:43:33.23#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.15:43:33.23#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.15:43:33.23#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.15:43:33.23#ibcon#enter wrdev, iclass 39, count 2 2006.173.15:43:33.23#ibcon#first serial, iclass 39, count 2 2006.173.15:43:33.23#ibcon#enter sib2, iclass 39, count 2 2006.173.15:43:33.23#ibcon#flushed, iclass 39, count 2 2006.173.15:43:33.23#ibcon#about to write, iclass 39, count 2 2006.173.15:43:33.23#ibcon#wrote, iclass 39, count 2 2006.173.15:43:33.23#ibcon#about to read 3, iclass 39, count 2 2006.173.15:43:33.25#ibcon#read 3, iclass 39, count 2 2006.173.15:43:33.25#ibcon#about to read 4, iclass 39, count 2 2006.173.15:43:33.25#ibcon#read 4, iclass 39, count 2 2006.173.15:43:33.25#ibcon#about to read 5, iclass 39, count 2 2006.173.15:43:33.25#ibcon#read 5, iclass 39, count 2 2006.173.15:43:33.25#ibcon#about to read 6, iclass 39, count 2 2006.173.15:43:33.25#ibcon#read 6, iclass 39, count 2 2006.173.15:43:33.25#ibcon#end of sib2, iclass 39, count 2 2006.173.15:43:33.25#ibcon#*mode == 0, iclass 39, count 2 2006.173.15:43:33.25#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.15:43:33.25#ibcon#[25=AT01-07\r\n] 2006.173.15:43:33.25#ibcon#*before write, iclass 39, count 2 2006.173.15:43:33.25#ibcon#enter sib2, iclass 39, count 2 2006.173.15:43:33.25#ibcon#flushed, iclass 39, count 2 2006.173.15:43:33.25#ibcon#about to write, iclass 39, count 2 2006.173.15:43:33.25#ibcon#wrote, iclass 39, count 2 2006.173.15:43:33.25#ibcon#about to read 3, iclass 39, count 2 2006.173.15:43:33.28#ibcon#read 3, iclass 39, count 2 2006.173.15:43:33.28#ibcon#about to read 4, iclass 39, count 2 2006.173.15:43:33.28#ibcon#read 4, iclass 39, count 2 2006.173.15:43:33.28#ibcon#about to read 5, iclass 39, count 2 2006.173.15:43:33.28#ibcon#read 5, iclass 39, count 2 2006.173.15:43:33.28#ibcon#about to read 6, iclass 39, count 2 2006.173.15:43:33.28#ibcon#read 6, iclass 39, count 2 2006.173.15:43:33.28#ibcon#end of sib2, iclass 39, count 2 2006.173.15:43:33.28#ibcon#*after write, iclass 39, count 2 2006.173.15:43:33.28#ibcon#*before return 0, iclass 39, count 2 2006.173.15:43:33.28#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.15:43:33.28#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.15:43:33.28#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.15:43:33.28#ibcon#ireg 7 cls_cnt 0 2006.173.15:43:33.28#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.15:43:33.40#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.15:43:33.40#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.15:43:33.40#ibcon#enter wrdev, iclass 39, count 0 2006.173.15:43:33.40#ibcon#first serial, iclass 39, count 0 2006.173.15:43:33.40#ibcon#enter sib2, iclass 39, count 0 2006.173.15:43:33.40#ibcon#flushed, iclass 39, count 0 2006.173.15:43:33.40#ibcon#about to write, iclass 39, count 0 2006.173.15:43:33.40#ibcon#wrote, iclass 39, count 0 2006.173.15:43:33.40#ibcon#about to read 3, iclass 39, count 0 2006.173.15:43:33.42#ibcon#read 3, iclass 39, count 0 2006.173.15:43:33.42#ibcon#about to read 4, iclass 39, count 0 2006.173.15:43:33.42#ibcon#read 4, iclass 39, count 0 2006.173.15:43:33.42#ibcon#about to read 5, iclass 39, count 0 2006.173.15:43:33.42#ibcon#read 5, iclass 39, count 0 2006.173.15:43:33.42#ibcon#about to read 6, iclass 39, count 0 2006.173.15:43:33.42#ibcon#read 6, iclass 39, count 0 2006.173.15:43:33.42#ibcon#end of sib2, iclass 39, count 0 2006.173.15:43:33.42#ibcon#*mode == 0, iclass 39, count 0 2006.173.15:43:33.42#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.15:43:33.42#ibcon#[25=USB\r\n] 2006.173.15:43:33.42#ibcon#*before write, iclass 39, count 0 2006.173.15:43:33.42#ibcon#enter sib2, iclass 39, count 0 2006.173.15:43:33.42#ibcon#flushed, iclass 39, count 0 2006.173.15:43:33.42#ibcon#about to write, iclass 39, count 0 2006.173.15:43:33.42#ibcon#wrote, iclass 39, count 0 2006.173.15:43:33.42#ibcon#about to read 3, iclass 39, count 0 2006.173.15:43:33.45#ibcon#read 3, iclass 39, count 0 2006.173.15:43:33.45#ibcon#about to read 4, iclass 39, count 0 2006.173.15:43:33.45#ibcon#read 4, iclass 39, count 0 2006.173.15:43:33.45#ibcon#about to read 5, iclass 39, count 0 2006.173.15:43:33.45#ibcon#read 5, iclass 39, count 0 2006.173.15:43:33.45#ibcon#about to read 6, iclass 39, count 0 2006.173.15:43:33.45#ibcon#read 6, iclass 39, count 0 2006.173.15:43:33.45#ibcon#end of sib2, iclass 39, count 0 2006.173.15:43:33.45#ibcon#*after write, iclass 39, count 0 2006.173.15:43:33.45#ibcon#*before return 0, iclass 39, count 0 2006.173.15:43:33.45#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.15:43:33.45#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.15:43:33.45#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.15:43:33.45#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.15:43:33.45$vck44/valo=2,534.99 2006.173.15:43:33.45#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.15:43:33.45#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.15:43:33.45#ibcon#ireg 17 cls_cnt 0 2006.173.15:43:33.45#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.15:43:33.45#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.15:43:33.45#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.15:43:33.45#ibcon#enter wrdev, iclass 3, count 0 2006.173.15:43:33.45#ibcon#first serial, iclass 3, count 0 2006.173.15:43:33.45#ibcon#enter sib2, iclass 3, count 0 2006.173.15:43:33.45#ibcon#flushed, iclass 3, count 0 2006.173.15:43:33.45#ibcon#about to write, iclass 3, count 0 2006.173.15:43:33.45#ibcon#wrote, iclass 3, count 0 2006.173.15:43:33.45#ibcon#about to read 3, iclass 3, count 0 2006.173.15:43:33.47#ibcon#read 3, iclass 3, count 0 2006.173.15:43:33.47#ibcon#about to read 4, iclass 3, count 0 2006.173.15:43:33.47#ibcon#read 4, iclass 3, count 0 2006.173.15:43:33.47#ibcon#about to read 5, iclass 3, count 0 2006.173.15:43:33.47#ibcon#read 5, iclass 3, count 0 2006.173.15:43:33.47#ibcon#about to read 6, iclass 3, count 0 2006.173.15:43:33.47#ibcon#read 6, iclass 3, count 0 2006.173.15:43:33.47#ibcon#end of sib2, iclass 3, count 0 2006.173.15:43:33.47#ibcon#*mode == 0, iclass 3, count 0 2006.173.15:43:33.47#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.15:43:33.47#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.15:43:33.47#ibcon#*before write, iclass 3, count 0 2006.173.15:43:33.47#ibcon#enter sib2, iclass 3, count 0 2006.173.15:43:33.47#ibcon#flushed, iclass 3, count 0 2006.173.15:43:33.47#ibcon#about to write, iclass 3, count 0 2006.173.15:43:33.47#ibcon#wrote, iclass 3, count 0 2006.173.15:43:33.47#ibcon#about to read 3, iclass 3, count 0 2006.173.15:43:33.51#ibcon#read 3, iclass 3, count 0 2006.173.15:43:33.51#ibcon#about to read 4, iclass 3, count 0 2006.173.15:43:33.51#ibcon#read 4, iclass 3, count 0 2006.173.15:43:33.51#ibcon#about to read 5, iclass 3, count 0 2006.173.15:43:33.51#ibcon#read 5, iclass 3, count 0 2006.173.15:43:33.51#ibcon#about to read 6, iclass 3, count 0 2006.173.15:43:33.51#ibcon#read 6, iclass 3, count 0 2006.173.15:43:33.51#ibcon#end of sib2, iclass 3, count 0 2006.173.15:43:33.51#ibcon#*after write, iclass 3, count 0 2006.173.15:43:33.51#ibcon#*before return 0, iclass 3, count 0 2006.173.15:43:33.51#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.15:43:33.51#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.15:43:33.51#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.15:43:33.51#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.15:43:33.51$vck44/va=2,6 2006.173.15:43:33.51#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.15:43:33.51#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.15:43:33.51#ibcon#ireg 11 cls_cnt 2 2006.173.15:43:33.51#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.15:43:33.57#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.15:43:33.57#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.15:43:33.57#ibcon#enter wrdev, iclass 5, count 2 2006.173.15:43:33.57#ibcon#first serial, iclass 5, count 2 2006.173.15:43:33.57#ibcon#enter sib2, iclass 5, count 2 2006.173.15:43:33.57#ibcon#flushed, iclass 5, count 2 2006.173.15:43:33.57#ibcon#about to write, iclass 5, count 2 2006.173.15:43:33.57#ibcon#wrote, iclass 5, count 2 2006.173.15:43:33.57#ibcon#about to read 3, iclass 5, count 2 2006.173.15:43:33.59#ibcon#read 3, iclass 5, count 2 2006.173.15:43:33.59#ibcon#about to read 4, iclass 5, count 2 2006.173.15:43:33.59#ibcon#read 4, iclass 5, count 2 2006.173.15:43:33.59#ibcon#about to read 5, iclass 5, count 2 2006.173.15:43:33.59#ibcon#read 5, iclass 5, count 2 2006.173.15:43:33.59#ibcon#about to read 6, iclass 5, count 2 2006.173.15:43:33.59#ibcon#read 6, iclass 5, count 2 2006.173.15:43:33.59#ibcon#end of sib2, iclass 5, count 2 2006.173.15:43:33.59#ibcon#*mode == 0, iclass 5, count 2 2006.173.15:43:33.59#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.15:43:33.59#ibcon#[25=AT02-06\r\n] 2006.173.15:43:33.59#ibcon#*before write, iclass 5, count 2 2006.173.15:43:33.59#ibcon#enter sib2, iclass 5, count 2 2006.173.15:43:33.59#ibcon#flushed, iclass 5, count 2 2006.173.15:43:33.59#ibcon#about to write, iclass 5, count 2 2006.173.15:43:33.59#ibcon#wrote, iclass 5, count 2 2006.173.15:43:33.59#ibcon#about to read 3, iclass 5, count 2 2006.173.15:43:33.62#ibcon#read 3, iclass 5, count 2 2006.173.15:43:33.62#ibcon#about to read 4, iclass 5, count 2 2006.173.15:43:33.62#ibcon#read 4, iclass 5, count 2 2006.173.15:43:33.62#ibcon#about to read 5, iclass 5, count 2 2006.173.15:43:33.62#ibcon#read 5, iclass 5, count 2 2006.173.15:43:33.62#ibcon#about to read 6, iclass 5, count 2 2006.173.15:43:33.62#ibcon#read 6, iclass 5, count 2 2006.173.15:43:33.62#ibcon#end of sib2, iclass 5, count 2 2006.173.15:43:33.62#ibcon#*after write, iclass 5, count 2 2006.173.15:43:33.62#ibcon#*before return 0, iclass 5, count 2 2006.173.15:43:33.62#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.15:43:33.62#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.15:43:33.62#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.15:43:33.62#ibcon#ireg 7 cls_cnt 0 2006.173.15:43:33.62#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.15:43:33.74#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.15:43:33.74#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.15:43:33.74#ibcon#enter wrdev, iclass 5, count 0 2006.173.15:43:33.74#ibcon#first serial, iclass 5, count 0 2006.173.15:43:33.74#ibcon#enter sib2, iclass 5, count 0 2006.173.15:43:33.74#ibcon#flushed, iclass 5, count 0 2006.173.15:43:33.74#ibcon#about to write, iclass 5, count 0 2006.173.15:43:33.74#ibcon#wrote, iclass 5, count 0 2006.173.15:43:33.74#ibcon#about to read 3, iclass 5, count 0 2006.173.15:43:33.76#ibcon#read 3, iclass 5, count 0 2006.173.15:43:33.76#ibcon#about to read 4, iclass 5, count 0 2006.173.15:43:33.76#ibcon#read 4, iclass 5, count 0 2006.173.15:43:33.76#ibcon#about to read 5, iclass 5, count 0 2006.173.15:43:33.76#ibcon#read 5, iclass 5, count 0 2006.173.15:43:33.76#ibcon#about to read 6, iclass 5, count 0 2006.173.15:43:33.76#ibcon#read 6, iclass 5, count 0 2006.173.15:43:33.76#ibcon#end of sib2, iclass 5, count 0 2006.173.15:43:33.76#ibcon#*mode == 0, iclass 5, count 0 2006.173.15:43:33.76#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.15:43:33.76#ibcon#[25=USB\r\n] 2006.173.15:43:33.76#ibcon#*before write, iclass 5, count 0 2006.173.15:43:33.76#ibcon#enter sib2, iclass 5, count 0 2006.173.15:43:33.76#ibcon#flushed, iclass 5, count 0 2006.173.15:43:33.76#ibcon#about to write, iclass 5, count 0 2006.173.15:43:33.76#ibcon#wrote, iclass 5, count 0 2006.173.15:43:33.76#ibcon#about to read 3, iclass 5, count 0 2006.173.15:43:33.79#ibcon#read 3, iclass 5, count 0 2006.173.15:43:33.79#ibcon#about to read 4, iclass 5, count 0 2006.173.15:43:33.79#ibcon#read 4, iclass 5, count 0 2006.173.15:43:33.79#ibcon#about to read 5, iclass 5, count 0 2006.173.15:43:33.79#ibcon#read 5, iclass 5, count 0 2006.173.15:43:33.79#ibcon#about to read 6, iclass 5, count 0 2006.173.15:43:33.79#ibcon#read 6, iclass 5, count 0 2006.173.15:43:33.79#ibcon#end of sib2, iclass 5, count 0 2006.173.15:43:33.79#ibcon#*after write, iclass 5, count 0 2006.173.15:43:33.79#ibcon#*before return 0, iclass 5, count 0 2006.173.15:43:33.79#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.15:43:33.79#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.15:43:33.79#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.15:43:33.79#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.15:43:33.79$vck44/valo=3,564.99 2006.173.15:43:33.79#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.15:43:33.79#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.15:43:33.79#ibcon#ireg 17 cls_cnt 0 2006.173.15:43:33.79#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.15:43:33.79#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.15:43:33.79#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.15:43:33.79#ibcon#enter wrdev, iclass 7, count 0 2006.173.15:43:33.79#ibcon#first serial, iclass 7, count 0 2006.173.15:43:33.79#ibcon#enter sib2, iclass 7, count 0 2006.173.15:43:33.79#ibcon#flushed, iclass 7, count 0 2006.173.15:43:33.79#ibcon#about to write, iclass 7, count 0 2006.173.15:43:33.79#ibcon#wrote, iclass 7, count 0 2006.173.15:43:33.79#ibcon#about to read 3, iclass 7, count 0 2006.173.15:43:33.81#ibcon#read 3, iclass 7, count 0 2006.173.15:43:33.81#ibcon#about to read 4, iclass 7, count 0 2006.173.15:43:33.81#ibcon#read 4, iclass 7, count 0 2006.173.15:43:33.81#ibcon#about to read 5, iclass 7, count 0 2006.173.15:43:33.81#ibcon#read 5, iclass 7, count 0 2006.173.15:43:33.81#ibcon#about to read 6, iclass 7, count 0 2006.173.15:43:33.81#ibcon#read 6, iclass 7, count 0 2006.173.15:43:33.81#ibcon#end of sib2, iclass 7, count 0 2006.173.15:43:33.81#ibcon#*mode == 0, iclass 7, count 0 2006.173.15:43:33.81#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.15:43:33.81#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.15:43:33.81#ibcon#*before write, iclass 7, count 0 2006.173.15:43:33.81#ibcon#enter sib2, iclass 7, count 0 2006.173.15:43:33.81#ibcon#flushed, iclass 7, count 0 2006.173.15:43:33.81#ibcon#about to write, iclass 7, count 0 2006.173.15:43:33.81#ibcon#wrote, iclass 7, count 0 2006.173.15:43:33.81#ibcon#about to read 3, iclass 7, count 0 2006.173.15:43:33.85#ibcon#read 3, iclass 7, count 0 2006.173.15:43:33.85#ibcon#about to read 4, iclass 7, count 0 2006.173.15:43:33.85#ibcon#read 4, iclass 7, count 0 2006.173.15:43:33.85#ibcon#about to read 5, iclass 7, count 0 2006.173.15:43:33.85#ibcon#read 5, iclass 7, count 0 2006.173.15:43:33.85#ibcon#about to read 6, iclass 7, count 0 2006.173.15:43:33.85#ibcon#read 6, iclass 7, count 0 2006.173.15:43:33.85#ibcon#end of sib2, iclass 7, count 0 2006.173.15:43:33.85#ibcon#*after write, iclass 7, count 0 2006.173.15:43:33.85#ibcon#*before return 0, iclass 7, count 0 2006.173.15:43:33.85#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.15:43:33.85#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.15:43:33.85#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.15:43:33.85#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.15:43:33.85$vck44/va=3,5 2006.173.15:43:33.85#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.15:43:33.85#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.15:43:33.85#ibcon#ireg 11 cls_cnt 2 2006.173.15:43:33.85#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.15:43:33.91#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.15:43:33.91#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.15:43:33.91#ibcon#enter wrdev, iclass 11, count 2 2006.173.15:43:33.91#ibcon#first serial, iclass 11, count 2 2006.173.15:43:33.91#ibcon#enter sib2, iclass 11, count 2 2006.173.15:43:33.91#ibcon#flushed, iclass 11, count 2 2006.173.15:43:33.91#ibcon#about to write, iclass 11, count 2 2006.173.15:43:33.91#ibcon#wrote, iclass 11, count 2 2006.173.15:43:33.91#ibcon#about to read 3, iclass 11, count 2 2006.173.15:43:33.93#ibcon#read 3, iclass 11, count 2 2006.173.15:43:33.93#ibcon#about to read 4, iclass 11, count 2 2006.173.15:43:33.93#ibcon#read 4, iclass 11, count 2 2006.173.15:43:33.93#ibcon#about to read 5, iclass 11, count 2 2006.173.15:43:33.93#ibcon#read 5, iclass 11, count 2 2006.173.15:43:33.93#ibcon#about to read 6, iclass 11, count 2 2006.173.15:43:33.93#ibcon#read 6, iclass 11, count 2 2006.173.15:43:33.93#ibcon#end of sib2, iclass 11, count 2 2006.173.15:43:33.93#ibcon#*mode == 0, iclass 11, count 2 2006.173.15:43:33.93#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.15:43:33.93#ibcon#[25=AT03-05\r\n] 2006.173.15:43:33.93#ibcon#*before write, iclass 11, count 2 2006.173.15:43:33.93#ibcon#enter sib2, iclass 11, count 2 2006.173.15:43:33.93#ibcon#flushed, iclass 11, count 2 2006.173.15:43:33.93#ibcon#about to write, iclass 11, count 2 2006.173.15:43:33.93#ibcon#wrote, iclass 11, count 2 2006.173.15:43:33.93#ibcon#about to read 3, iclass 11, count 2 2006.173.15:43:33.96#ibcon#read 3, iclass 11, count 2 2006.173.15:43:33.96#ibcon#about to read 4, iclass 11, count 2 2006.173.15:43:33.96#ibcon#read 4, iclass 11, count 2 2006.173.15:43:33.96#ibcon#about to read 5, iclass 11, count 2 2006.173.15:43:33.96#ibcon#read 5, iclass 11, count 2 2006.173.15:43:33.96#ibcon#about to read 6, iclass 11, count 2 2006.173.15:43:33.96#ibcon#read 6, iclass 11, count 2 2006.173.15:43:33.96#ibcon#end of sib2, iclass 11, count 2 2006.173.15:43:33.96#ibcon#*after write, iclass 11, count 2 2006.173.15:43:33.96#ibcon#*before return 0, iclass 11, count 2 2006.173.15:43:33.96#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.15:43:33.96#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.15:43:33.96#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.15:43:33.96#ibcon#ireg 7 cls_cnt 0 2006.173.15:43:33.96#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.15:43:34.08#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.15:43:34.08#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.15:43:34.08#ibcon#enter wrdev, iclass 11, count 0 2006.173.15:43:34.08#ibcon#first serial, iclass 11, count 0 2006.173.15:43:34.08#ibcon#enter sib2, iclass 11, count 0 2006.173.15:43:34.08#ibcon#flushed, iclass 11, count 0 2006.173.15:43:34.08#ibcon#about to write, iclass 11, count 0 2006.173.15:43:34.08#ibcon#wrote, iclass 11, count 0 2006.173.15:43:34.08#ibcon#about to read 3, iclass 11, count 0 2006.173.15:43:34.10#ibcon#read 3, iclass 11, count 0 2006.173.15:43:34.10#ibcon#about to read 4, iclass 11, count 0 2006.173.15:43:34.10#ibcon#read 4, iclass 11, count 0 2006.173.15:43:34.10#ibcon#about to read 5, iclass 11, count 0 2006.173.15:43:34.10#ibcon#read 5, iclass 11, count 0 2006.173.15:43:34.10#ibcon#about to read 6, iclass 11, count 0 2006.173.15:43:34.10#ibcon#read 6, iclass 11, count 0 2006.173.15:43:34.10#ibcon#end of sib2, iclass 11, count 0 2006.173.15:43:34.10#ibcon#*mode == 0, iclass 11, count 0 2006.173.15:43:34.10#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.15:43:34.10#ibcon#[25=USB\r\n] 2006.173.15:43:34.10#ibcon#*before write, iclass 11, count 0 2006.173.15:43:34.10#ibcon#enter sib2, iclass 11, count 0 2006.173.15:43:34.10#ibcon#flushed, iclass 11, count 0 2006.173.15:43:34.10#ibcon#about to write, iclass 11, count 0 2006.173.15:43:34.10#ibcon#wrote, iclass 11, count 0 2006.173.15:43:34.10#ibcon#about to read 3, iclass 11, count 0 2006.173.15:43:34.13#ibcon#read 3, iclass 11, count 0 2006.173.15:43:34.13#ibcon#about to read 4, iclass 11, count 0 2006.173.15:43:34.13#ibcon#read 4, iclass 11, count 0 2006.173.15:43:34.13#ibcon#about to read 5, iclass 11, count 0 2006.173.15:43:34.13#ibcon#read 5, iclass 11, count 0 2006.173.15:43:34.13#ibcon#about to read 6, iclass 11, count 0 2006.173.15:43:34.13#ibcon#read 6, iclass 11, count 0 2006.173.15:43:34.13#ibcon#end of sib2, iclass 11, count 0 2006.173.15:43:34.13#ibcon#*after write, iclass 11, count 0 2006.173.15:43:34.13#ibcon#*before return 0, iclass 11, count 0 2006.173.15:43:34.13#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.15:43:34.13#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.15:43:34.13#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.15:43:34.13#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.15:43:34.13$vck44/valo=4,624.99 2006.173.15:43:34.13#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.15:43:34.13#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.15:43:34.13#ibcon#ireg 17 cls_cnt 0 2006.173.15:43:34.13#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.15:43:34.13#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.15:43:34.13#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.15:43:34.13#ibcon#enter wrdev, iclass 13, count 0 2006.173.15:43:34.13#ibcon#first serial, iclass 13, count 0 2006.173.15:43:34.13#ibcon#enter sib2, iclass 13, count 0 2006.173.15:43:34.13#ibcon#flushed, iclass 13, count 0 2006.173.15:43:34.13#ibcon#about to write, iclass 13, count 0 2006.173.15:43:34.13#ibcon#wrote, iclass 13, count 0 2006.173.15:43:34.13#ibcon#about to read 3, iclass 13, count 0 2006.173.15:43:34.15#ibcon#read 3, iclass 13, count 0 2006.173.15:43:34.15#ibcon#about to read 4, iclass 13, count 0 2006.173.15:43:34.15#ibcon#read 4, iclass 13, count 0 2006.173.15:43:34.15#ibcon#about to read 5, iclass 13, count 0 2006.173.15:43:34.15#ibcon#read 5, iclass 13, count 0 2006.173.15:43:34.15#ibcon#about to read 6, iclass 13, count 0 2006.173.15:43:34.15#ibcon#read 6, iclass 13, count 0 2006.173.15:43:34.15#ibcon#end of sib2, iclass 13, count 0 2006.173.15:43:34.15#ibcon#*mode == 0, iclass 13, count 0 2006.173.15:43:34.15#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.15:43:34.15#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.15:43:34.15#ibcon#*before write, iclass 13, count 0 2006.173.15:43:34.15#ibcon#enter sib2, iclass 13, count 0 2006.173.15:43:34.15#ibcon#flushed, iclass 13, count 0 2006.173.15:43:34.15#ibcon#about to write, iclass 13, count 0 2006.173.15:43:34.15#ibcon#wrote, iclass 13, count 0 2006.173.15:43:34.15#ibcon#about to read 3, iclass 13, count 0 2006.173.15:43:34.19#ibcon#read 3, iclass 13, count 0 2006.173.15:43:34.19#ibcon#about to read 4, iclass 13, count 0 2006.173.15:43:34.19#ibcon#read 4, iclass 13, count 0 2006.173.15:43:34.19#ibcon#about to read 5, iclass 13, count 0 2006.173.15:43:34.19#ibcon#read 5, iclass 13, count 0 2006.173.15:43:34.19#ibcon#about to read 6, iclass 13, count 0 2006.173.15:43:34.19#ibcon#read 6, iclass 13, count 0 2006.173.15:43:34.19#ibcon#end of sib2, iclass 13, count 0 2006.173.15:43:34.19#ibcon#*after write, iclass 13, count 0 2006.173.15:43:34.19#ibcon#*before return 0, iclass 13, count 0 2006.173.15:43:34.19#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.15:43:34.19#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.15:43:34.19#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.15:43:34.19#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.15:43:34.19$vck44/va=4,6 2006.173.15:43:34.19#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.15:43:34.19#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.15:43:34.19#ibcon#ireg 11 cls_cnt 2 2006.173.15:43:34.19#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.15:43:34.25#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.15:43:34.25#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.15:43:34.25#ibcon#enter wrdev, iclass 15, count 2 2006.173.15:43:34.25#ibcon#first serial, iclass 15, count 2 2006.173.15:43:34.25#ibcon#enter sib2, iclass 15, count 2 2006.173.15:43:34.25#ibcon#flushed, iclass 15, count 2 2006.173.15:43:34.25#ibcon#about to write, iclass 15, count 2 2006.173.15:43:34.25#ibcon#wrote, iclass 15, count 2 2006.173.15:43:34.25#ibcon#about to read 3, iclass 15, count 2 2006.173.15:43:34.27#ibcon#read 3, iclass 15, count 2 2006.173.15:43:34.27#ibcon#about to read 4, iclass 15, count 2 2006.173.15:43:34.27#ibcon#read 4, iclass 15, count 2 2006.173.15:43:34.27#ibcon#about to read 5, iclass 15, count 2 2006.173.15:43:34.27#ibcon#read 5, iclass 15, count 2 2006.173.15:43:34.27#ibcon#about to read 6, iclass 15, count 2 2006.173.15:43:34.27#ibcon#read 6, iclass 15, count 2 2006.173.15:43:34.27#ibcon#end of sib2, iclass 15, count 2 2006.173.15:43:34.27#ibcon#*mode == 0, iclass 15, count 2 2006.173.15:43:34.27#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.15:43:34.27#ibcon#[25=AT04-06\r\n] 2006.173.15:43:34.27#ibcon#*before write, iclass 15, count 2 2006.173.15:43:34.27#ibcon#enter sib2, iclass 15, count 2 2006.173.15:43:34.27#ibcon#flushed, iclass 15, count 2 2006.173.15:43:34.27#ibcon#about to write, iclass 15, count 2 2006.173.15:43:34.27#ibcon#wrote, iclass 15, count 2 2006.173.15:43:34.27#ibcon#about to read 3, iclass 15, count 2 2006.173.15:43:34.30#ibcon#read 3, iclass 15, count 2 2006.173.15:43:34.30#ibcon#about to read 4, iclass 15, count 2 2006.173.15:43:34.30#ibcon#read 4, iclass 15, count 2 2006.173.15:43:34.30#ibcon#about to read 5, iclass 15, count 2 2006.173.15:43:34.30#ibcon#read 5, iclass 15, count 2 2006.173.15:43:34.30#ibcon#about to read 6, iclass 15, count 2 2006.173.15:43:34.30#ibcon#read 6, iclass 15, count 2 2006.173.15:43:34.30#ibcon#end of sib2, iclass 15, count 2 2006.173.15:43:34.30#ibcon#*after write, iclass 15, count 2 2006.173.15:43:34.30#ibcon#*before return 0, iclass 15, count 2 2006.173.15:43:34.30#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.15:43:34.30#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.15:43:34.30#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.15:43:34.30#ibcon#ireg 7 cls_cnt 0 2006.173.15:43:34.30#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.15:43:34.42#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.15:43:34.42#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.15:43:34.42#ibcon#enter wrdev, iclass 15, count 0 2006.173.15:43:34.42#ibcon#first serial, iclass 15, count 0 2006.173.15:43:34.42#ibcon#enter sib2, iclass 15, count 0 2006.173.15:43:34.42#ibcon#flushed, iclass 15, count 0 2006.173.15:43:34.42#ibcon#about to write, iclass 15, count 0 2006.173.15:43:34.42#ibcon#wrote, iclass 15, count 0 2006.173.15:43:34.42#ibcon#about to read 3, iclass 15, count 0 2006.173.15:43:34.44#ibcon#read 3, iclass 15, count 0 2006.173.15:43:34.44#ibcon#about to read 4, iclass 15, count 0 2006.173.15:43:34.44#ibcon#read 4, iclass 15, count 0 2006.173.15:43:34.44#ibcon#about to read 5, iclass 15, count 0 2006.173.15:43:34.44#ibcon#read 5, iclass 15, count 0 2006.173.15:43:34.44#ibcon#about to read 6, iclass 15, count 0 2006.173.15:43:34.44#ibcon#read 6, iclass 15, count 0 2006.173.15:43:34.44#ibcon#end of sib2, iclass 15, count 0 2006.173.15:43:34.44#ibcon#*mode == 0, iclass 15, count 0 2006.173.15:43:34.44#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.15:43:34.44#ibcon#[25=USB\r\n] 2006.173.15:43:34.44#ibcon#*before write, iclass 15, count 0 2006.173.15:43:34.44#ibcon#enter sib2, iclass 15, count 0 2006.173.15:43:34.44#ibcon#flushed, iclass 15, count 0 2006.173.15:43:34.44#ibcon#about to write, iclass 15, count 0 2006.173.15:43:34.44#ibcon#wrote, iclass 15, count 0 2006.173.15:43:34.44#ibcon#about to read 3, iclass 15, count 0 2006.173.15:43:34.47#ibcon#read 3, iclass 15, count 0 2006.173.15:43:34.47#ibcon#about to read 4, iclass 15, count 0 2006.173.15:43:34.47#ibcon#read 4, iclass 15, count 0 2006.173.15:43:34.47#ibcon#about to read 5, iclass 15, count 0 2006.173.15:43:34.47#ibcon#read 5, iclass 15, count 0 2006.173.15:43:34.47#ibcon#about to read 6, iclass 15, count 0 2006.173.15:43:34.47#ibcon#read 6, iclass 15, count 0 2006.173.15:43:34.47#ibcon#end of sib2, iclass 15, count 0 2006.173.15:43:34.47#ibcon#*after write, iclass 15, count 0 2006.173.15:43:34.47#ibcon#*before return 0, iclass 15, count 0 2006.173.15:43:34.47#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.15:43:34.47#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.15:43:34.47#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.15:43:34.47#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.15:43:34.47$vck44/valo=5,734.99 2006.173.15:43:34.47#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.15:43:34.47#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.15:43:34.47#ibcon#ireg 17 cls_cnt 0 2006.173.15:43:34.47#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.15:43:34.47#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.15:43:34.47#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.15:43:34.47#ibcon#enter wrdev, iclass 17, count 0 2006.173.15:43:34.47#ibcon#first serial, iclass 17, count 0 2006.173.15:43:34.47#ibcon#enter sib2, iclass 17, count 0 2006.173.15:43:34.47#ibcon#flushed, iclass 17, count 0 2006.173.15:43:34.47#ibcon#about to write, iclass 17, count 0 2006.173.15:43:34.47#ibcon#wrote, iclass 17, count 0 2006.173.15:43:34.47#ibcon#about to read 3, iclass 17, count 0 2006.173.15:43:34.49#ibcon#read 3, iclass 17, count 0 2006.173.15:43:34.49#ibcon#about to read 4, iclass 17, count 0 2006.173.15:43:34.49#ibcon#read 4, iclass 17, count 0 2006.173.15:43:34.49#ibcon#about to read 5, iclass 17, count 0 2006.173.15:43:34.49#ibcon#read 5, iclass 17, count 0 2006.173.15:43:34.49#ibcon#about to read 6, iclass 17, count 0 2006.173.15:43:34.49#ibcon#read 6, iclass 17, count 0 2006.173.15:43:34.49#ibcon#end of sib2, iclass 17, count 0 2006.173.15:43:34.49#ibcon#*mode == 0, iclass 17, count 0 2006.173.15:43:34.49#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.15:43:34.49#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.15:43:34.49#ibcon#*before write, iclass 17, count 0 2006.173.15:43:34.49#ibcon#enter sib2, iclass 17, count 0 2006.173.15:43:34.49#ibcon#flushed, iclass 17, count 0 2006.173.15:43:34.49#ibcon#about to write, iclass 17, count 0 2006.173.15:43:34.49#ibcon#wrote, iclass 17, count 0 2006.173.15:43:34.49#ibcon#about to read 3, iclass 17, count 0 2006.173.15:43:34.53#ibcon#read 3, iclass 17, count 0 2006.173.15:43:34.53#ibcon#about to read 4, iclass 17, count 0 2006.173.15:43:34.53#ibcon#read 4, iclass 17, count 0 2006.173.15:43:34.53#ibcon#about to read 5, iclass 17, count 0 2006.173.15:43:34.53#ibcon#read 5, iclass 17, count 0 2006.173.15:43:34.53#ibcon#about to read 6, iclass 17, count 0 2006.173.15:43:34.53#ibcon#read 6, iclass 17, count 0 2006.173.15:43:34.53#ibcon#end of sib2, iclass 17, count 0 2006.173.15:43:34.53#ibcon#*after write, iclass 17, count 0 2006.173.15:43:34.53#ibcon#*before return 0, iclass 17, count 0 2006.173.15:43:34.53#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.15:43:34.53#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.15:43:34.53#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.15:43:34.53#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.15:43:34.53$vck44/va=5,4 2006.173.15:43:34.53#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.15:43:34.53#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.15:43:34.53#ibcon#ireg 11 cls_cnt 2 2006.173.15:43:34.53#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.15:43:34.59#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.15:43:34.59#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.15:43:34.59#ibcon#enter wrdev, iclass 19, count 2 2006.173.15:43:34.59#ibcon#first serial, iclass 19, count 2 2006.173.15:43:34.59#ibcon#enter sib2, iclass 19, count 2 2006.173.15:43:34.59#ibcon#flushed, iclass 19, count 2 2006.173.15:43:34.59#ibcon#about to write, iclass 19, count 2 2006.173.15:43:34.59#ibcon#wrote, iclass 19, count 2 2006.173.15:43:34.59#ibcon#about to read 3, iclass 19, count 2 2006.173.15:43:34.61#ibcon#read 3, iclass 19, count 2 2006.173.15:43:34.61#ibcon#about to read 4, iclass 19, count 2 2006.173.15:43:34.61#ibcon#read 4, iclass 19, count 2 2006.173.15:43:34.61#ibcon#about to read 5, iclass 19, count 2 2006.173.15:43:34.61#ibcon#read 5, iclass 19, count 2 2006.173.15:43:34.61#ibcon#about to read 6, iclass 19, count 2 2006.173.15:43:34.61#ibcon#read 6, iclass 19, count 2 2006.173.15:43:34.61#ibcon#end of sib2, iclass 19, count 2 2006.173.15:43:34.61#ibcon#*mode == 0, iclass 19, count 2 2006.173.15:43:34.61#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.15:43:34.61#ibcon#[25=AT05-04\r\n] 2006.173.15:43:34.61#ibcon#*before write, iclass 19, count 2 2006.173.15:43:34.61#ibcon#enter sib2, iclass 19, count 2 2006.173.15:43:34.61#ibcon#flushed, iclass 19, count 2 2006.173.15:43:34.61#ibcon#about to write, iclass 19, count 2 2006.173.15:43:34.61#ibcon#wrote, iclass 19, count 2 2006.173.15:43:34.61#ibcon#about to read 3, iclass 19, count 2 2006.173.15:43:34.64#ibcon#read 3, iclass 19, count 2 2006.173.15:43:34.64#ibcon#about to read 4, iclass 19, count 2 2006.173.15:43:34.64#ibcon#read 4, iclass 19, count 2 2006.173.15:43:34.64#ibcon#about to read 5, iclass 19, count 2 2006.173.15:43:34.64#ibcon#read 5, iclass 19, count 2 2006.173.15:43:34.64#ibcon#about to read 6, iclass 19, count 2 2006.173.15:43:34.64#ibcon#read 6, iclass 19, count 2 2006.173.15:43:34.64#ibcon#end of sib2, iclass 19, count 2 2006.173.15:43:34.64#ibcon#*after write, iclass 19, count 2 2006.173.15:43:34.64#ibcon#*before return 0, iclass 19, count 2 2006.173.15:43:34.64#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.15:43:34.64#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.15:43:34.64#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.15:43:34.64#ibcon#ireg 7 cls_cnt 0 2006.173.15:43:34.64#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.15:43:34.76#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.15:43:34.76#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.15:43:34.76#ibcon#enter wrdev, iclass 19, count 0 2006.173.15:43:34.76#ibcon#first serial, iclass 19, count 0 2006.173.15:43:34.76#ibcon#enter sib2, iclass 19, count 0 2006.173.15:43:34.76#ibcon#flushed, iclass 19, count 0 2006.173.15:43:34.76#ibcon#about to write, iclass 19, count 0 2006.173.15:43:34.76#ibcon#wrote, iclass 19, count 0 2006.173.15:43:34.76#ibcon#about to read 3, iclass 19, count 0 2006.173.15:43:34.78#ibcon#read 3, iclass 19, count 0 2006.173.15:43:34.78#ibcon#about to read 4, iclass 19, count 0 2006.173.15:43:34.78#ibcon#read 4, iclass 19, count 0 2006.173.15:43:34.78#ibcon#about to read 5, iclass 19, count 0 2006.173.15:43:34.78#ibcon#read 5, iclass 19, count 0 2006.173.15:43:34.78#ibcon#about to read 6, iclass 19, count 0 2006.173.15:43:34.78#ibcon#read 6, iclass 19, count 0 2006.173.15:43:34.78#ibcon#end of sib2, iclass 19, count 0 2006.173.15:43:34.78#ibcon#*mode == 0, iclass 19, count 0 2006.173.15:43:34.78#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.15:43:34.78#ibcon#[25=USB\r\n] 2006.173.15:43:34.78#ibcon#*before write, iclass 19, count 0 2006.173.15:43:34.78#ibcon#enter sib2, iclass 19, count 0 2006.173.15:43:34.78#ibcon#flushed, iclass 19, count 0 2006.173.15:43:34.78#ibcon#about to write, iclass 19, count 0 2006.173.15:43:34.78#ibcon#wrote, iclass 19, count 0 2006.173.15:43:34.78#ibcon#about to read 3, iclass 19, count 0 2006.173.15:43:34.81#ibcon#read 3, iclass 19, count 0 2006.173.15:43:34.81#ibcon#about to read 4, iclass 19, count 0 2006.173.15:43:34.81#ibcon#read 4, iclass 19, count 0 2006.173.15:43:34.81#ibcon#about to read 5, iclass 19, count 0 2006.173.15:43:34.81#ibcon#read 5, iclass 19, count 0 2006.173.15:43:34.81#ibcon#about to read 6, iclass 19, count 0 2006.173.15:43:34.81#ibcon#read 6, iclass 19, count 0 2006.173.15:43:34.81#ibcon#end of sib2, iclass 19, count 0 2006.173.15:43:34.81#ibcon#*after write, iclass 19, count 0 2006.173.15:43:34.81#ibcon#*before return 0, iclass 19, count 0 2006.173.15:43:34.81#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.15:43:34.81#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.15:43:34.81#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.15:43:34.81#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.15:43:34.81$vck44/valo=6,814.99 2006.173.15:43:34.81#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.15:43:34.81#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.15:43:34.81#ibcon#ireg 17 cls_cnt 0 2006.173.15:43:34.81#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.15:43:34.81#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.15:43:34.81#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.15:43:34.81#ibcon#enter wrdev, iclass 21, count 0 2006.173.15:43:34.81#ibcon#first serial, iclass 21, count 0 2006.173.15:43:34.81#ibcon#enter sib2, iclass 21, count 0 2006.173.15:43:34.81#ibcon#flushed, iclass 21, count 0 2006.173.15:43:34.81#ibcon#about to write, iclass 21, count 0 2006.173.15:43:34.81#ibcon#wrote, iclass 21, count 0 2006.173.15:43:34.81#ibcon#about to read 3, iclass 21, count 0 2006.173.15:43:34.83#ibcon#read 3, iclass 21, count 0 2006.173.15:43:34.83#ibcon#about to read 4, iclass 21, count 0 2006.173.15:43:34.83#ibcon#read 4, iclass 21, count 0 2006.173.15:43:34.83#ibcon#about to read 5, iclass 21, count 0 2006.173.15:43:34.83#ibcon#read 5, iclass 21, count 0 2006.173.15:43:34.83#ibcon#about to read 6, iclass 21, count 0 2006.173.15:43:34.83#ibcon#read 6, iclass 21, count 0 2006.173.15:43:34.83#ibcon#end of sib2, iclass 21, count 0 2006.173.15:43:34.83#ibcon#*mode == 0, iclass 21, count 0 2006.173.15:43:34.83#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.15:43:34.83#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.15:43:34.83#ibcon#*before write, iclass 21, count 0 2006.173.15:43:34.83#ibcon#enter sib2, iclass 21, count 0 2006.173.15:43:34.83#ibcon#flushed, iclass 21, count 0 2006.173.15:43:34.83#ibcon#about to write, iclass 21, count 0 2006.173.15:43:34.83#ibcon#wrote, iclass 21, count 0 2006.173.15:43:34.83#ibcon#about to read 3, iclass 21, count 0 2006.173.15:43:34.87#ibcon#read 3, iclass 21, count 0 2006.173.15:43:34.87#ibcon#about to read 4, iclass 21, count 0 2006.173.15:43:34.87#ibcon#read 4, iclass 21, count 0 2006.173.15:43:34.87#ibcon#about to read 5, iclass 21, count 0 2006.173.15:43:34.87#ibcon#read 5, iclass 21, count 0 2006.173.15:43:34.87#ibcon#about to read 6, iclass 21, count 0 2006.173.15:43:34.87#ibcon#read 6, iclass 21, count 0 2006.173.15:43:34.87#ibcon#end of sib2, iclass 21, count 0 2006.173.15:43:34.87#ibcon#*after write, iclass 21, count 0 2006.173.15:43:34.87#ibcon#*before return 0, iclass 21, count 0 2006.173.15:43:34.87#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.15:43:34.87#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.15:43:34.87#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.15:43:34.87#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.15:43:34.87$vck44/va=6,3 2006.173.15:43:34.87#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.15:43:34.87#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.15:43:34.87#ibcon#ireg 11 cls_cnt 2 2006.173.15:43:34.87#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.15:43:34.93#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.15:43:34.93#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.15:43:34.93#ibcon#enter wrdev, iclass 23, count 2 2006.173.15:43:34.93#ibcon#first serial, iclass 23, count 2 2006.173.15:43:34.93#ibcon#enter sib2, iclass 23, count 2 2006.173.15:43:34.93#ibcon#flushed, iclass 23, count 2 2006.173.15:43:34.93#ibcon#about to write, iclass 23, count 2 2006.173.15:43:34.93#ibcon#wrote, iclass 23, count 2 2006.173.15:43:34.93#ibcon#about to read 3, iclass 23, count 2 2006.173.15:43:34.95#ibcon#read 3, iclass 23, count 2 2006.173.15:43:34.95#ibcon#about to read 4, iclass 23, count 2 2006.173.15:43:34.95#ibcon#read 4, iclass 23, count 2 2006.173.15:43:34.95#ibcon#about to read 5, iclass 23, count 2 2006.173.15:43:34.95#ibcon#read 5, iclass 23, count 2 2006.173.15:43:34.95#ibcon#about to read 6, iclass 23, count 2 2006.173.15:43:34.95#ibcon#read 6, iclass 23, count 2 2006.173.15:43:34.95#ibcon#end of sib2, iclass 23, count 2 2006.173.15:43:34.95#ibcon#*mode == 0, iclass 23, count 2 2006.173.15:43:34.95#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.15:43:34.95#ibcon#[25=AT06-03\r\n] 2006.173.15:43:34.95#ibcon#*before write, iclass 23, count 2 2006.173.15:43:34.95#ibcon#enter sib2, iclass 23, count 2 2006.173.15:43:34.95#ibcon#flushed, iclass 23, count 2 2006.173.15:43:34.95#ibcon#about to write, iclass 23, count 2 2006.173.15:43:34.95#ibcon#wrote, iclass 23, count 2 2006.173.15:43:34.95#ibcon#about to read 3, iclass 23, count 2 2006.173.15:43:34.98#ibcon#read 3, iclass 23, count 2 2006.173.15:43:34.98#ibcon#about to read 4, iclass 23, count 2 2006.173.15:43:34.98#ibcon#read 4, iclass 23, count 2 2006.173.15:43:34.98#ibcon#about to read 5, iclass 23, count 2 2006.173.15:43:34.98#ibcon#read 5, iclass 23, count 2 2006.173.15:43:34.98#ibcon#about to read 6, iclass 23, count 2 2006.173.15:43:34.98#ibcon#read 6, iclass 23, count 2 2006.173.15:43:34.98#ibcon#end of sib2, iclass 23, count 2 2006.173.15:43:34.98#ibcon#*after write, iclass 23, count 2 2006.173.15:43:34.98#ibcon#*before return 0, iclass 23, count 2 2006.173.15:43:34.98#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.15:43:34.98#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.15:43:34.98#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.15:43:34.98#ibcon#ireg 7 cls_cnt 0 2006.173.15:43:34.98#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.15:43:35.10#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.15:43:35.10#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.15:43:35.10#ibcon#enter wrdev, iclass 23, count 0 2006.173.15:43:35.10#ibcon#first serial, iclass 23, count 0 2006.173.15:43:35.10#ibcon#enter sib2, iclass 23, count 0 2006.173.15:43:35.10#ibcon#flushed, iclass 23, count 0 2006.173.15:43:35.10#ibcon#about to write, iclass 23, count 0 2006.173.15:43:35.10#ibcon#wrote, iclass 23, count 0 2006.173.15:43:35.10#ibcon#about to read 3, iclass 23, count 0 2006.173.15:43:35.12#ibcon#read 3, iclass 23, count 0 2006.173.15:43:35.12#ibcon#about to read 4, iclass 23, count 0 2006.173.15:43:35.12#ibcon#read 4, iclass 23, count 0 2006.173.15:43:35.12#ibcon#about to read 5, iclass 23, count 0 2006.173.15:43:35.12#ibcon#read 5, iclass 23, count 0 2006.173.15:43:35.12#ibcon#about to read 6, iclass 23, count 0 2006.173.15:43:35.12#ibcon#read 6, iclass 23, count 0 2006.173.15:43:35.12#ibcon#end of sib2, iclass 23, count 0 2006.173.15:43:35.12#ibcon#*mode == 0, iclass 23, count 0 2006.173.15:43:35.12#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.15:43:35.12#ibcon#[25=USB\r\n] 2006.173.15:43:35.12#ibcon#*before write, iclass 23, count 0 2006.173.15:43:35.12#ibcon#enter sib2, iclass 23, count 0 2006.173.15:43:35.12#ibcon#flushed, iclass 23, count 0 2006.173.15:43:35.12#ibcon#about to write, iclass 23, count 0 2006.173.15:43:35.12#ibcon#wrote, iclass 23, count 0 2006.173.15:43:35.12#ibcon#about to read 3, iclass 23, count 0 2006.173.15:43:35.15#ibcon#read 3, iclass 23, count 0 2006.173.15:43:35.15#ibcon#about to read 4, iclass 23, count 0 2006.173.15:43:35.15#ibcon#read 4, iclass 23, count 0 2006.173.15:43:35.15#ibcon#about to read 5, iclass 23, count 0 2006.173.15:43:35.15#ibcon#read 5, iclass 23, count 0 2006.173.15:43:35.15#ibcon#about to read 6, iclass 23, count 0 2006.173.15:43:35.15#ibcon#read 6, iclass 23, count 0 2006.173.15:43:35.15#ibcon#end of sib2, iclass 23, count 0 2006.173.15:43:35.15#ibcon#*after write, iclass 23, count 0 2006.173.15:43:35.15#ibcon#*before return 0, iclass 23, count 0 2006.173.15:43:35.15#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.15:43:35.15#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.15:43:35.15#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.15:43:35.15#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.15:43:35.15$vck44/valo=7,864.99 2006.173.15:43:35.15#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.15:43:35.15#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.15:43:35.15#ibcon#ireg 17 cls_cnt 0 2006.173.15:43:35.15#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.15:43:35.15#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.15:43:35.15#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.15:43:35.15#ibcon#enter wrdev, iclass 25, count 0 2006.173.15:43:35.15#ibcon#first serial, iclass 25, count 0 2006.173.15:43:35.15#ibcon#enter sib2, iclass 25, count 0 2006.173.15:43:35.15#ibcon#flushed, iclass 25, count 0 2006.173.15:43:35.15#ibcon#about to write, iclass 25, count 0 2006.173.15:43:35.15#ibcon#wrote, iclass 25, count 0 2006.173.15:43:35.15#ibcon#about to read 3, iclass 25, count 0 2006.173.15:43:35.17#ibcon#read 3, iclass 25, count 0 2006.173.15:43:35.17#ibcon#about to read 4, iclass 25, count 0 2006.173.15:43:35.17#ibcon#read 4, iclass 25, count 0 2006.173.15:43:35.17#ibcon#about to read 5, iclass 25, count 0 2006.173.15:43:35.17#ibcon#read 5, iclass 25, count 0 2006.173.15:43:35.17#ibcon#about to read 6, iclass 25, count 0 2006.173.15:43:35.17#ibcon#read 6, iclass 25, count 0 2006.173.15:43:35.17#ibcon#end of sib2, iclass 25, count 0 2006.173.15:43:35.17#ibcon#*mode == 0, iclass 25, count 0 2006.173.15:43:35.17#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.15:43:35.17#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.15:43:35.17#ibcon#*before write, iclass 25, count 0 2006.173.15:43:35.17#ibcon#enter sib2, iclass 25, count 0 2006.173.15:43:35.17#ibcon#flushed, iclass 25, count 0 2006.173.15:43:35.17#ibcon#about to write, iclass 25, count 0 2006.173.15:43:35.17#ibcon#wrote, iclass 25, count 0 2006.173.15:43:35.17#ibcon#about to read 3, iclass 25, count 0 2006.173.15:43:35.21#ibcon#read 3, iclass 25, count 0 2006.173.15:43:35.21#ibcon#about to read 4, iclass 25, count 0 2006.173.15:43:35.21#ibcon#read 4, iclass 25, count 0 2006.173.15:43:35.21#ibcon#about to read 5, iclass 25, count 0 2006.173.15:43:35.21#ibcon#read 5, iclass 25, count 0 2006.173.15:43:35.21#ibcon#about to read 6, iclass 25, count 0 2006.173.15:43:35.21#ibcon#read 6, iclass 25, count 0 2006.173.15:43:35.21#ibcon#end of sib2, iclass 25, count 0 2006.173.15:43:35.21#ibcon#*after write, iclass 25, count 0 2006.173.15:43:35.21#ibcon#*before return 0, iclass 25, count 0 2006.173.15:43:35.21#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.15:43:35.21#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.15:43:35.21#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.15:43:35.21#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.15:43:35.21$vck44/va=7,4 2006.173.15:43:35.21#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.15:43:35.21#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.15:43:35.21#ibcon#ireg 11 cls_cnt 2 2006.173.15:43:35.21#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.15:43:35.27#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.15:43:35.27#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.15:43:35.27#ibcon#enter wrdev, iclass 27, count 2 2006.173.15:43:35.27#ibcon#first serial, iclass 27, count 2 2006.173.15:43:35.27#ibcon#enter sib2, iclass 27, count 2 2006.173.15:43:35.27#ibcon#flushed, iclass 27, count 2 2006.173.15:43:35.27#ibcon#about to write, iclass 27, count 2 2006.173.15:43:35.27#ibcon#wrote, iclass 27, count 2 2006.173.15:43:35.27#ibcon#about to read 3, iclass 27, count 2 2006.173.15:43:35.29#ibcon#read 3, iclass 27, count 2 2006.173.15:43:35.29#ibcon#about to read 4, iclass 27, count 2 2006.173.15:43:35.29#ibcon#read 4, iclass 27, count 2 2006.173.15:43:35.29#ibcon#about to read 5, iclass 27, count 2 2006.173.15:43:35.29#ibcon#read 5, iclass 27, count 2 2006.173.15:43:35.29#ibcon#about to read 6, iclass 27, count 2 2006.173.15:43:35.29#ibcon#read 6, iclass 27, count 2 2006.173.15:43:35.29#ibcon#end of sib2, iclass 27, count 2 2006.173.15:43:35.29#ibcon#*mode == 0, iclass 27, count 2 2006.173.15:43:35.29#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.15:43:35.29#ibcon#[25=AT07-04\r\n] 2006.173.15:43:35.29#ibcon#*before write, iclass 27, count 2 2006.173.15:43:35.29#ibcon#enter sib2, iclass 27, count 2 2006.173.15:43:35.29#ibcon#flushed, iclass 27, count 2 2006.173.15:43:35.29#ibcon#about to write, iclass 27, count 2 2006.173.15:43:35.29#ibcon#wrote, iclass 27, count 2 2006.173.15:43:35.29#ibcon#about to read 3, iclass 27, count 2 2006.173.15:43:35.32#ibcon#read 3, iclass 27, count 2 2006.173.15:43:35.32#ibcon#about to read 4, iclass 27, count 2 2006.173.15:43:35.32#ibcon#read 4, iclass 27, count 2 2006.173.15:43:35.32#ibcon#about to read 5, iclass 27, count 2 2006.173.15:43:35.32#ibcon#read 5, iclass 27, count 2 2006.173.15:43:35.32#ibcon#about to read 6, iclass 27, count 2 2006.173.15:43:35.32#ibcon#read 6, iclass 27, count 2 2006.173.15:43:35.32#ibcon#end of sib2, iclass 27, count 2 2006.173.15:43:35.32#ibcon#*after write, iclass 27, count 2 2006.173.15:43:35.32#ibcon#*before return 0, iclass 27, count 2 2006.173.15:43:35.32#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.15:43:35.32#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.15:43:35.32#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.15:43:35.32#ibcon#ireg 7 cls_cnt 0 2006.173.15:43:35.32#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.15:43:35.44#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.15:43:35.44#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.15:43:35.44#ibcon#enter wrdev, iclass 27, count 0 2006.173.15:43:35.44#ibcon#first serial, iclass 27, count 0 2006.173.15:43:35.44#ibcon#enter sib2, iclass 27, count 0 2006.173.15:43:35.44#ibcon#flushed, iclass 27, count 0 2006.173.15:43:35.44#ibcon#about to write, iclass 27, count 0 2006.173.15:43:35.44#ibcon#wrote, iclass 27, count 0 2006.173.15:43:35.44#ibcon#about to read 3, iclass 27, count 0 2006.173.15:43:35.46#ibcon#read 3, iclass 27, count 0 2006.173.15:43:35.46#ibcon#about to read 4, iclass 27, count 0 2006.173.15:43:35.46#ibcon#read 4, iclass 27, count 0 2006.173.15:43:35.46#ibcon#about to read 5, iclass 27, count 0 2006.173.15:43:35.46#ibcon#read 5, iclass 27, count 0 2006.173.15:43:35.46#ibcon#about to read 6, iclass 27, count 0 2006.173.15:43:35.46#ibcon#read 6, iclass 27, count 0 2006.173.15:43:35.46#ibcon#end of sib2, iclass 27, count 0 2006.173.15:43:35.46#ibcon#*mode == 0, iclass 27, count 0 2006.173.15:43:35.46#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.15:43:35.46#ibcon#[25=USB\r\n] 2006.173.15:43:35.46#ibcon#*before write, iclass 27, count 0 2006.173.15:43:35.46#ibcon#enter sib2, iclass 27, count 0 2006.173.15:43:35.46#ibcon#flushed, iclass 27, count 0 2006.173.15:43:35.46#ibcon#about to write, iclass 27, count 0 2006.173.15:43:35.46#ibcon#wrote, iclass 27, count 0 2006.173.15:43:35.46#ibcon#about to read 3, iclass 27, count 0 2006.173.15:43:35.49#ibcon#read 3, iclass 27, count 0 2006.173.15:43:35.49#ibcon#about to read 4, iclass 27, count 0 2006.173.15:43:35.49#ibcon#read 4, iclass 27, count 0 2006.173.15:43:35.49#ibcon#about to read 5, iclass 27, count 0 2006.173.15:43:35.49#ibcon#read 5, iclass 27, count 0 2006.173.15:43:35.49#ibcon#about to read 6, iclass 27, count 0 2006.173.15:43:35.49#ibcon#read 6, iclass 27, count 0 2006.173.15:43:35.49#ibcon#end of sib2, iclass 27, count 0 2006.173.15:43:35.49#ibcon#*after write, iclass 27, count 0 2006.173.15:43:35.49#ibcon#*before return 0, iclass 27, count 0 2006.173.15:43:35.49#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.15:43:35.49#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.15:43:35.49#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.15:43:35.49#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.15:43:35.49$vck44/valo=8,884.99 2006.173.15:43:35.49#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.15:43:35.49#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.15:43:35.49#ibcon#ireg 17 cls_cnt 0 2006.173.15:43:35.49#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.15:43:35.49#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.15:43:35.49#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.15:43:35.49#ibcon#enter wrdev, iclass 29, count 0 2006.173.15:43:35.49#ibcon#first serial, iclass 29, count 0 2006.173.15:43:35.49#ibcon#enter sib2, iclass 29, count 0 2006.173.15:43:35.49#ibcon#flushed, iclass 29, count 0 2006.173.15:43:35.49#ibcon#about to write, iclass 29, count 0 2006.173.15:43:35.49#ibcon#wrote, iclass 29, count 0 2006.173.15:43:35.49#ibcon#about to read 3, iclass 29, count 0 2006.173.15:43:35.51#ibcon#read 3, iclass 29, count 0 2006.173.15:43:35.51#ibcon#about to read 4, iclass 29, count 0 2006.173.15:43:35.51#ibcon#read 4, iclass 29, count 0 2006.173.15:43:35.51#ibcon#about to read 5, iclass 29, count 0 2006.173.15:43:35.51#ibcon#read 5, iclass 29, count 0 2006.173.15:43:35.51#ibcon#about to read 6, iclass 29, count 0 2006.173.15:43:35.51#ibcon#read 6, iclass 29, count 0 2006.173.15:43:35.51#ibcon#end of sib2, iclass 29, count 0 2006.173.15:43:35.51#ibcon#*mode == 0, iclass 29, count 0 2006.173.15:43:35.51#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.15:43:35.51#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.15:43:35.51#ibcon#*before write, iclass 29, count 0 2006.173.15:43:35.51#ibcon#enter sib2, iclass 29, count 0 2006.173.15:43:35.51#ibcon#flushed, iclass 29, count 0 2006.173.15:43:35.51#ibcon#about to write, iclass 29, count 0 2006.173.15:43:35.51#ibcon#wrote, iclass 29, count 0 2006.173.15:43:35.51#ibcon#about to read 3, iclass 29, count 0 2006.173.15:43:35.55#ibcon#read 3, iclass 29, count 0 2006.173.15:43:35.55#ibcon#about to read 4, iclass 29, count 0 2006.173.15:43:35.55#ibcon#read 4, iclass 29, count 0 2006.173.15:43:35.55#ibcon#about to read 5, iclass 29, count 0 2006.173.15:43:35.55#ibcon#read 5, iclass 29, count 0 2006.173.15:43:35.55#ibcon#about to read 6, iclass 29, count 0 2006.173.15:43:35.55#ibcon#read 6, iclass 29, count 0 2006.173.15:43:35.55#ibcon#end of sib2, iclass 29, count 0 2006.173.15:43:35.55#ibcon#*after write, iclass 29, count 0 2006.173.15:43:35.55#ibcon#*before return 0, iclass 29, count 0 2006.173.15:43:35.55#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.15:43:35.55#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.15:43:35.55#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.15:43:35.55#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.15:43:35.55$vck44/va=8,4 2006.173.15:43:35.55#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.15:43:35.55#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.15:43:35.55#ibcon#ireg 11 cls_cnt 2 2006.173.15:43:35.55#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.15:43:35.61#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.15:43:35.61#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.15:43:35.61#ibcon#enter wrdev, iclass 31, count 2 2006.173.15:43:35.61#ibcon#first serial, iclass 31, count 2 2006.173.15:43:35.61#ibcon#enter sib2, iclass 31, count 2 2006.173.15:43:35.61#ibcon#flushed, iclass 31, count 2 2006.173.15:43:35.61#ibcon#about to write, iclass 31, count 2 2006.173.15:43:35.61#ibcon#wrote, iclass 31, count 2 2006.173.15:43:35.61#ibcon#about to read 3, iclass 31, count 2 2006.173.15:43:35.63#ibcon#read 3, iclass 31, count 2 2006.173.15:43:35.63#ibcon#about to read 4, iclass 31, count 2 2006.173.15:43:35.63#ibcon#read 4, iclass 31, count 2 2006.173.15:43:35.63#ibcon#about to read 5, iclass 31, count 2 2006.173.15:43:35.63#ibcon#read 5, iclass 31, count 2 2006.173.15:43:35.63#ibcon#about to read 6, iclass 31, count 2 2006.173.15:43:35.63#ibcon#read 6, iclass 31, count 2 2006.173.15:43:35.63#ibcon#end of sib2, iclass 31, count 2 2006.173.15:43:35.63#ibcon#*mode == 0, iclass 31, count 2 2006.173.15:43:35.63#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.15:43:35.63#ibcon#[25=AT08-04\r\n] 2006.173.15:43:35.63#ibcon#*before write, iclass 31, count 2 2006.173.15:43:35.63#ibcon#enter sib2, iclass 31, count 2 2006.173.15:43:35.63#ibcon#flushed, iclass 31, count 2 2006.173.15:43:35.63#ibcon#about to write, iclass 31, count 2 2006.173.15:43:35.63#ibcon#wrote, iclass 31, count 2 2006.173.15:43:35.63#ibcon#about to read 3, iclass 31, count 2 2006.173.15:43:35.66#ibcon#read 3, iclass 31, count 2 2006.173.15:43:35.66#ibcon#about to read 4, iclass 31, count 2 2006.173.15:43:35.66#ibcon#read 4, iclass 31, count 2 2006.173.15:43:35.66#ibcon#about to read 5, iclass 31, count 2 2006.173.15:43:35.66#ibcon#read 5, iclass 31, count 2 2006.173.15:43:35.66#ibcon#about to read 6, iclass 31, count 2 2006.173.15:43:35.66#ibcon#read 6, iclass 31, count 2 2006.173.15:43:35.66#ibcon#end of sib2, iclass 31, count 2 2006.173.15:43:35.66#ibcon#*after write, iclass 31, count 2 2006.173.15:43:35.66#ibcon#*before return 0, iclass 31, count 2 2006.173.15:43:35.66#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.15:43:35.66#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.15:43:35.66#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.15:43:35.66#ibcon#ireg 7 cls_cnt 0 2006.173.15:43:35.66#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.15:43:35.78#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.15:43:35.78#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.15:43:35.78#ibcon#enter wrdev, iclass 31, count 0 2006.173.15:43:35.78#ibcon#first serial, iclass 31, count 0 2006.173.15:43:35.78#ibcon#enter sib2, iclass 31, count 0 2006.173.15:43:35.78#ibcon#flushed, iclass 31, count 0 2006.173.15:43:35.78#ibcon#about to write, iclass 31, count 0 2006.173.15:43:35.78#ibcon#wrote, iclass 31, count 0 2006.173.15:43:35.78#ibcon#about to read 3, iclass 31, count 0 2006.173.15:43:35.80#ibcon#read 3, iclass 31, count 0 2006.173.15:43:35.80#ibcon#about to read 4, iclass 31, count 0 2006.173.15:43:35.80#ibcon#read 4, iclass 31, count 0 2006.173.15:43:35.80#ibcon#about to read 5, iclass 31, count 0 2006.173.15:43:35.80#ibcon#read 5, iclass 31, count 0 2006.173.15:43:35.80#ibcon#about to read 6, iclass 31, count 0 2006.173.15:43:35.80#ibcon#read 6, iclass 31, count 0 2006.173.15:43:35.80#ibcon#end of sib2, iclass 31, count 0 2006.173.15:43:35.80#ibcon#*mode == 0, iclass 31, count 0 2006.173.15:43:35.80#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.15:43:35.80#ibcon#[25=USB\r\n] 2006.173.15:43:35.80#ibcon#*before write, iclass 31, count 0 2006.173.15:43:35.80#ibcon#enter sib2, iclass 31, count 0 2006.173.15:43:35.80#ibcon#flushed, iclass 31, count 0 2006.173.15:43:35.80#ibcon#about to write, iclass 31, count 0 2006.173.15:43:35.80#ibcon#wrote, iclass 31, count 0 2006.173.15:43:35.80#ibcon#about to read 3, iclass 31, count 0 2006.173.15:43:35.83#ibcon#read 3, iclass 31, count 0 2006.173.15:43:35.83#ibcon#about to read 4, iclass 31, count 0 2006.173.15:43:35.83#ibcon#read 4, iclass 31, count 0 2006.173.15:43:35.83#ibcon#about to read 5, iclass 31, count 0 2006.173.15:43:35.83#ibcon#read 5, iclass 31, count 0 2006.173.15:43:35.83#ibcon#about to read 6, iclass 31, count 0 2006.173.15:43:35.83#ibcon#read 6, iclass 31, count 0 2006.173.15:43:35.83#ibcon#end of sib2, iclass 31, count 0 2006.173.15:43:35.83#ibcon#*after write, iclass 31, count 0 2006.173.15:43:35.83#ibcon#*before return 0, iclass 31, count 0 2006.173.15:43:35.83#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.15:43:35.83#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.15:43:35.83#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.15:43:35.83#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.15:43:35.83$vck44/vblo=1,629.99 2006.173.15:43:35.83#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.15:43:35.83#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.15:43:35.83#ibcon#ireg 17 cls_cnt 0 2006.173.15:43:35.83#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.15:43:35.83#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.15:43:35.83#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.15:43:35.83#ibcon#enter wrdev, iclass 33, count 0 2006.173.15:43:35.83#ibcon#first serial, iclass 33, count 0 2006.173.15:43:35.83#ibcon#enter sib2, iclass 33, count 0 2006.173.15:43:35.83#ibcon#flushed, iclass 33, count 0 2006.173.15:43:35.83#ibcon#about to write, iclass 33, count 0 2006.173.15:43:35.83#ibcon#wrote, iclass 33, count 0 2006.173.15:43:35.83#ibcon#about to read 3, iclass 33, count 0 2006.173.15:43:35.85#ibcon#read 3, iclass 33, count 0 2006.173.15:43:35.85#ibcon#about to read 4, iclass 33, count 0 2006.173.15:43:35.85#ibcon#read 4, iclass 33, count 0 2006.173.15:43:35.85#ibcon#about to read 5, iclass 33, count 0 2006.173.15:43:35.85#ibcon#read 5, iclass 33, count 0 2006.173.15:43:35.85#ibcon#about to read 6, iclass 33, count 0 2006.173.15:43:35.85#ibcon#read 6, iclass 33, count 0 2006.173.15:43:35.85#ibcon#end of sib2, iclass 33, count 0 2006.173.15:43:35.85#ibcon#*mode == 0, iclass 33, count 0 2006.173.15:43:35.85#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.15:43:35.85#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.15:43:35.85#ibcon#*before write, iclass 33, count 0 2006.173.15:43:35.85#ibcon#enter sib2, iclass 33, count 0 2006.173.15:43:35.85#ibcon#flushed, iclass 33, count 0 2006.173.15:43:35.85#ibcon#about to write, iclass 33, count 0 2006.173.15:43:35.85#ibcon#wrote, iclass 33, count 0 2006.173.15:43:35.85#ibcon#about to read 3, iclass 33, count 0 2006.173.15:43:35.89#ibcon#read 3, iclass 33, count 0 2006.173.15:43:35.89#ibcon#about to read 4, iclass 33, count 0 2006.173.15:43:35.89#ibcon#read 4, iclass 33, count 0 2006.173.15:43:35.89#ibcon#about to read 5, iclass 33, count 0 2006.173.15:43:35.89#ibcon#read 5, iclass 33, count 0 2006.173.15:43:35.89#ibcon#about to read 6, iclass 33, count 0 2006.173.15:43:35.89#ibcon#read 6, iclass 33, count 0 2006.173.15:43:35.89#ibcon#end of sib2, iclass 33, count 0 2006.173.15:43:35.89#ibcon#*after write, iclass 33, count 0 2006.173.15:43:35.89#ibcon#*before return 0, iclass 33, count 0 2006.173.15:43:35.89#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.15:43:35.89#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.15:43:35.89#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.15:43:35.89#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.15:43:35.89$vck44/vb=1,4 2006.173.15:43:35.89#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.15:43:35.89#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.15:43:35.89#ibcon#ireg 11 cls_cnt 2 2006.173.15:43:35.89#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.15:43:35.89#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.15:43:35.89#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.15:43:35.89#ibcon#enter wrdev, iclass 35, count 2 2006.173.15:43:35.89#ibcon#first serial, iclass 35, count 2 2006.173.15:43:35.89#ibcon#enter sib2, iclass 35, count 2 2006.173.15:43:35.89#ibcon#flushed, iclass 35, count 2 2006.173.15:43:35.89#ibcon#about to write, iclass 35, count 2 2006.173.15:43:35.89#ibcon#wrote, iclass 35, count 2 2006.173.15:43:35.89#ibcon#about to read 3, iclass 35, count 2 2006.173.15:43:35.91#ibcon#read 3, iclass 35, count 2 2006.173.15:43:35.91#ibcon#about to read 4, iclass 35, count 2 2006.173.15:43:35.91#ibcon#read 4, iclass 35, count 2 2006.173.15:43:35.91#ibcon#about to read 5, iclass 35, count 2 2006.173.15:43:35.91#ibcon#read 5, iclass 35, count 2 2006.173.15:43:35.91#ibcon#about to read 6, iclass 35, count 2 2006.173.15:43:35.91#ibcon#read 6, iclass 35, count 2 2006.173.15:43:35.91#ibcon#end of sib2, iclass 35, count 2 2006.173.15:43:35.91#ibcon#*mode == 0, iclass 35, count 2 2006.173.15:43:35.91#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.15:43:35.91#ibcon#[27=AT01-04\r\n] 2006.173.15:43:35.91#ibcon#*before write, iclass 35, count 2 2006.173.15:43:35.91#ibcon#enter sib2, iclass 35, count 2 2006.173.15:43:35.91#ibcon#flushed, iclass 35, count 2 2006.173.15:43:35.91#ibcon#about to write, iclass 35, count 2 2006.173.15:43:35.91#ibcon#wrote, iclass 35, count 2 2006.173.15:43:35.91#ibcon#about to read 3, iclass 35, count 2 2006.173.15:43:35.94#ibcon#read 3, iclass 35, count 2 2006.173.15:43:35.94#ibcon#about to read 4, iclass 35, count 2 2006.173.15:43:35.94#ibcon#read 4, iclass 35, count 2 2006.173.15:43:35.94#ibcon#about to read 5, iclass 35, count 2 2006.173.15:43:35.94#ibcon#read 5, iclass 35, count 2 2006.173.15:43:35.94#ibcon#about to read 6, iclass 35, count 2 2006.173.15:43:35.94#ibcon#read 6, iclass 35, count 2 2006.173.15:43:35.94#ibcon#end of sib2, iclass 35, count 2 2006.173.15:43:35.94#ibcon#*after write, iclass 35, count 2 2006.173.15:43:35.94#ibcon#*before return 0, iclass 35, count 2 2006.173.15:43:35.94#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.15:43:35.94#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.15:43:35.94#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.15:43:35.94#ibcon#ireg 7 cls_cnt 0 2006.173.15:43:35.94#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.15:43:36.06#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.15:43:36.06#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.15:43:36.06#ibcon#enter wrdev, iclass 35, count 0 2006.173.15:43:36.06#ibcon#first serial, iclass 35, count 0 2006.173.15:43:36.06#ibcon#enter sib2, iclass 35, count 0 2006.173.15:43:36.06#ibcon#flushed, iclass 35, count 0 2006.173.15:43:36.06#ibcon#about to write, iclass 35, count 0 2006.173.15:43:36.06#ibcon#wrote, iclass 35, count 0 2006.173.15:43:36.06#ibcon#about to read 3, iclass 35, count 0 2006.173.15:43:36.08#ibcon#read 3, iclass 35, count 0 2006.173.15:43:36.08#ibcon#about to read 4, iclass 35, count 0 2006.173.15:43:36.08#ibcon#read 4, iclass 35, count 0 2006.173.15:43:36.08#ibcon#about to read 5, iclass 35, count 0 2006.173.15:43:36.08#ibcon#read 5, iclass 35, count 0 2006.173.15:43:36.08#ibcon#about to read 6, iclass 35, count 0 2006.173.15:43:36.08#ibcon#read 6, iclass 35, count 0 2006.173.15:43:36.08#ibcon#end of sib2, iclass 35, count 0 2006.173.15:43:36.08#ibcon#*mode == 0, iclass 35, count 0 2006.173.15:43:36.08#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.15:43:36.08#ibcon#[27=USB\r\n] 2006.173.15:43:36.08#ibcon#*before write, iclass 35, count 0 2006.173.15:43:36.08#ibcon#enter sib2, iclass 35, count 0 2006.173.15:43:36.08#ibcon#flushed, iclass 35, count 0 2006.173.15:43:36.08#ibcon#about to write, iclass 35, count 0 2006.173.15:43:36.08#ibcon#wrote, iclass 35, count 0 2006.173.15:43:36.08#ibcon#about to read 3, iclass 35, count 0 2006.173.15:43:36.11#ibcon#read 3, iclass 35, count 0 2006.173.15:43:36.11#ibcon#about to read 4, iclass 35, count 0 2006.173.15:43:36.11#ibcon#read 4, iclass 35, count 0 2006.173.15:43:36.11#ibcon#about to read 5, iclass 35, count 0 2006.173.15:43:36.11#ibcon#read 5, iclass 35, count 0 2006.173.15:43:36.11#ibcon#about to read 6, iclass 35, count 0 2006.173.15:43:36.11#ibcon#read 6, iclass 35, count 0 2006.173.15:43:36.11#ibcon#end of sib2, iclass 35, count 0 2006.173.15:43:36.11#ibcon#*after write, iclass 35, count 0 2006.173.15:43:36.11#ibcon#*before return 0, iclass 35, count 0 2006.173.15:43:36.11#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.15:43:36.11#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.15:43:36.11#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.15:43:36.11#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.15:43:36.11$vck44/vblo=2,634.99 2006.173.15:43:36.11#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.15:43:36.11#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.15:43:36.11#ibcon#ireg 17 cls_cnt 0 2006.173.15:43:36.11#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.15:43:36.11#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.15:43:36.11#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.15:43:36.11#ibcon#enter wrdev, iclass 37, count 0 2006.173.15:43:36.11#ibcon#first serial, iclass 37, count 0 2006.173.15:43:36.11#ibcon#enter sib2, iclass 37, count 0 2006.173.15:43:36.11#ibcon#flushed, iclass 37, count 0 2006.173.15:43:36.11#ibcon#about to write, iclass 37, count 0 2006.173.15:43:36.11#ibcon#wrote, iclass 37, count 0 2006.173.15:43:36.11#ibcon#about to read 3, iclass 37, count 0 2006.173.15:43:36.13#ibcon#read 3, iclass 37, count 0 2006.173.15:43:36.13#ibcon#about to read 4, iclass 37, count 0 2006.173.15:43:36.13#ibcon#read 4, iclass 37, count 0 2006.173.15:43:36.13#ibcon#about to read 5, iclass 37, count 0 2006.173.15:43:36.13#ibcon#read 5, iclass 37, count 0 2006.173.15:43:36.13#ibcon#about to read 6, iclass 37, count 0 2006.173.15:43:36.13#ibcon#read 6, iclass 37, count 0 2006.173.15:43:36.13#ibcon#end of sib2, iclass 37, count 0 2006.173.15:43:36.13#ibcon#*mode == 0, iclass 37, count 0 2006.173.15:43:36.13#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.15:43:36.13#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.15:43:36.13#ibcon#*before write, iclass 37, count 0 2006.173.15:43:36.13#ibcon#enter sib2, iclass 37, count 0 2006.173.15:43:36.13#ibcon#flushed, iclass 37, count 0 2006.173.15:43:36.13#ibcon#about to write, iclass 37, count 0 2006.173.15:43:36.13#ibcon#wrote, iclass 37, count 0 2006.173.15:43:36.13#ibcon#about to read 3, iclass 37, count 0 2006.173.15:43:36.17#ibcon#read 3, iclass 37, count 0 2006.173.15:43:36.17#ibcon#about to read 4, iclass 37, count 0 2006.173.15:43:36.17#ibcon#read 4, iclass 37, count 0 2006.173.15:43:36.17#ibcon#about to read 5, iclass 37, count 0 2006.173.15:43:36.17#ibcon#read 5, iclass 37, count 0 2006.173.15:43:36.17#ibcon#about to read 6, iclass 37, count 0 2006.173.15:43:36.17#ibcon#read 6, iclass 37, count 0 2006.173.15:43:36.17#ibcon#end of sib2, iclass 37, count 0 2006.173.15:43:36.17#ibcon#*after write, iclass 37, count 0 2006.173.15:43:36.17#ibcon#*before return 0, iclass 37, count 0 2006.173.15:43:36.17#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.15:43:36.17#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.15:43:36.17#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.15:43:36.17#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.15:43:36.17$vck44/vb=2,4 2006.173.15:43:36.17#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.15:43:36.17#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.15:43:36.17#ibcon#ireg 11 cls_cnt 2 2006.173.15:43:36.17#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.15:43:36.23#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.15:43:36.23#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.15:43:36.23#ibcon#enter wrdev, iclass 39, count 2 2006.173.15:43:36.23#ibcon#first serial, iclass 39, count 2 2006.173.15:43:36.23#ibcon#enter sib2, iclass 39, count 2 2006.173.15:43:36.23#ibcon#flushed, iclass 39, count 2 2006.173.15:43:36.23#ibcon#about to write, iclass 39, count 2 2006.173.15:43:36.23#ibcon#wrote, iclass 39, count 2 2006.173.15:43:36.23#ibcon#about to read 3, iclass 39, count 2 2006.173.15:43:36.25#ibcon#read 3, iclass 39, count 2 2006.173.15:43:36.25#ibcon#about to read 4, iclass 39, count 2 2006.173.15:43:36.25#ibcon#read 4, iclass 39, count 2 2006.173.15:43:36.25#ibcon#about to read 5, iclass 39, count 2 2006.173.15:43:36.25#ibcon#read 5, iclass 39, count 2 2006.173.15:43:36.25#ibcon#about to read 6, iclass 39, count 2 2006.173.15:43:36.25#ibcon#read 6, iclass 39, count 2 2006.173.15:43:36.25#ibcon#end of sib2, iclass 39, count 2 2006.173.15:43:36.25#ibcon#*mode == 0, iclass 39, count 2 2006.173.15:43:36.25#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.15:43:36.25#ibcon#[27=AT02-04\r\n] 2006.173.15:43:36.25#ibcon#*before write, iclass 39, count 2 2006.173.15:43:36.25#ibcon#enter sib2, iclass 39, count 2 2006.173.15:43:36.25#ibcon#flushed, iclass 39, count 2 2006.173.15:43:36.25#ibcon#about to write, iclass 39, count 2 2006.173.15:43:36.25#ibcon#wrote, iclass 39, count 2 2006.173.15:43:36.25#ibcon#about to read 3, iclass 39, count 2 2006.173.15:43:36.28#ibcon#read 3, iclass 39, count 2 2006.173.15:43:36.28#ibcon#about to read 4, iclass 39, count 2 2006.173.15:43:36.28#ibcon#read 4, iclass 39, count 2 2006.173.15:43:36.28#ibcon#about to read 5, iclass 39, count 2 2006.173.15:43:36.28#ibcon#read 5, iclass 39, count 2 2006.173.15:43:36.28#ibcon#about to read 6, iclass 39, count 2 2006.173.15:43:36.28#ibcon#read 6, iclass 39, count 2 2006.173.15:43:36.28#ibcon#end of sib2, iclass 39, count 2 2006.173.15:43:36.28#ibcon#*after write, iclass 39, count 2 2006.173.15:43:36.28#ibcon#*before return 0, iclass 39, count 2 2006.173.15:43:36.28#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.15:43:36.28#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.15:43:36.28#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.15:43:36.28#ibcon#ireg 7 cls_cnt 0 2006.173.15:43:36.28#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.15:43:36.40#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.15:43:36.40#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.15:43:36.40#ibcon#enter wrdev, iclass 39, count 0 2006.173.15:43:36.40#ibcon#first serial, iclass 39, count 0 2006.173.15:43:36.40#ibcon#enter sib2, iclass 39, count 0 2006.173.15:43:36.40#ibcon#flushed, iclass 39, count 0 2006.173.15:43:36.40#ibcon#about to write, iclass 39, count 0 2006.173.15:43:36.40#ibcon#wrote, iclass 39, count 0 2006.173.15:43:36.40#ibcon#about to read 3, iclass 39, count 0 2006.173.15:43:36.42#ibcon#read 3, iclass 39, count 0 2006.173.15:43:36.42#ibcon#about to read 4, iclass 39, count 0 2006.173.15:43:36.42#ibcon#read 4, iclass 39, count 0 2006.173.15:43:36.42#ibcon#about to read 5, iclass 39, count 0 2006.173.15:43:36.42#ibcon#read 5, iclass 39, count 0 2006.173.15:43:36.42#ibcon#about to read 6, iclass 39, count 0 2006.173.15:43:36.42#ibcon#read 6, iclass 39, count 0 2006.173.15:43:36.42#ibcon#end of sib2, iclass 39, count 0 2006.173.15:43:36.42#ibcon#*mode == 0, iclass 39, count 0 2006.173.15:43:36.42#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.15:43:36.42#ibcon#[27=USB\r\n] 2006.173.15:43:36.42#ibcon#*before write, iclass 39, count 0 2006.173.15:43:36.42#ibcon#enter sib2, iclass 39, count 0 2006.173.15:43:36.42#ibcon#flushed, iclass 39, count 0 2006.173.15:43:36.42#ibcon#about to write, iclass 39, count 0 2006.173.15:43:36.42#ibcon#wrote, iclass 39, count 0 2006.173.15:43:36.42#ibcon#about to read 3, iclass 39, count 0 2006.173.15:43:36.45#ibcon#read 3, iclass 39, count 0 2006.173.15:43:36.45#ibcon#about to read 4, iclass 39, count 0 2006.173.15:43:36.45#ibcon#read 4, iclass 39, count 0 2006.173.15:43:36.45#ibcon#about to read 5, iclass 39, count 0 2006.173.15:43:36.45#ibcon#read 5, iclass 39, count 0 2006.173.15:43:36.45#ibcon#about to read 6, iclass 39, count 0 2006.173.15:43:36.45#ibcon#read 6, iclass 39, count 0 2006.173.15:43:36.45#ibcon#end of sib2, iclass 39, count 0 2006.173.15:43:36.45#ibcon#*after write, iclass 39, count 0 2006.173.15:43:36.45#ibcon#*before return 0, iclass 39, count 0 2006.173.15:43:36.45#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.15:43:36.45#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.15:43:36.45#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.15:43:36.45#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.15:43:36.45$vck44/vblo=3,649.99 2006.173.15:43:36.45#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.15:43:36.45#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.15:43:36.45#ibcon#ireg 17 cls_cnt 0 2006.173.15:43:36.45#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.15:43:36.45#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.15:43:36.45#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.15:43:36.45#ibcon#enter wrdev, iclass 3, count 0 2006.173.15:43:36.45#ibcon#first serial, iclass 3, count 0 2006.173.15:43:36.45#ibcon#enter sib2, iclass 3, count 0 2006.173.15:43:36.45#ibcon#flushed, iclass 3, count 0 2006.173.15:43:36.45#ibcon#about to write, iclass 3, count 0 2006.173.15:43:36.45#ibcon#wrote, iclass 3, count 0 2006.173.15:43:36.45#ibcon#about to read 3, iclass 3, count 0 2006.173.15:43:36.47#ibcon#read 3, iclass 3, count 0 2006.173.15:43:36.47#ibcon#about to read 4, iclass 3, count 0 2006.173.15:43:36.47#ibcon#read 4, iclass 3, count 0 2006.173.15:43:36.47#ibcon#about to read 5, iclass 3, count 0 2006.173.15:43:36.47#ibcon#read 5, iclass 3, count 0 2006.173.15:43:36.47#ibcon#about to read 6, iclass 3, count 0 2006.173.15:43:36.47#ibcon#read 6, iclass 3, count 0 2006.173.15:43:36.47#ibcon#end of sib2, iclass 3, count 0 2006.173.15:43:36.47#ibcon#*mode == 0, iclass 3, count 0 2006.173.15:43:36.47#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.15:43:36.47#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.15:43:36.47#ibcon#*before write, iclass 3, count 0 2006.173.15:43:36.47#ibcon#enter sib2, iclass 3, count 0 2006.173.15:43:36.47#ibcon#flushed, iclass 3, count 0 2006.173.15:43:36.47#ibcon#about to write, iclass 3, count 0 2006.173.15:43:36.47#ibcon#wrote, iclass 3, count 0 2006.173.15:43:36.47#ibcon#about to read 3, iclass 3, count 0 2006.173.15:43:36.51#ibcon#read 3, iclass 3, count 0 2006.173.15:43:36.51#ibcon#about to read 4, iclass 3, count 0 2006.173.15:43:36.51#ibcon#read 4, iclass 3, count 0 2006.173.15:43:36.51#ibcon#about to read 5, iclass 3, count 0 2006.173.15:43:36.51#ibcon#read 5, iclass 3, count 0 2006.173.15:43:36.51#ibcon#about to read 6, iclass 3, count 0 2006.173.15:43:36.51#ibcon#read 6, iclass 3, count 0 2006.173.15:43:36.51#ibcon#end of sib2, iclass 3, count 0 2006.173.15:43:36.51#ibcon#*after write, iclass 3, count 0 2006.173.15:43:36.51#ibcon#*before return 0, iclass 3, count 0 2006.173.15:43:36.51#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.15:43:36.51#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.15:43:36.51#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.15:43:36.51#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.15:43:36.51$vck44/vb=3,4 2006.173.15:43:36.51#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.15:43:36.51#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.15:43:36.51#ibcon#ireg 11 cls_cnt 2 2006.173.15:43:36.51#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.15:43:36.57#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.15:43:36.57#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.15:43:36.57#ibcon#enter wrdev, iclass 5, count 2 2006.173.15:43:36.57#ibcon#first serial, iclass 5, count 2 2006.173.15:43:36.57#ibcon#enter sib2, iclass 5, count 2 2006.173.15:43:36.57#ibcon#flushed, iclass 5, count 2 2006.173.15:43:36.57#ibcon#about to write, iclass 5, count 2 2006.173.15:43:36.57#ibcon#wrote, iclass 5, count 2 2006.173.15:43:36.57#ibcon#about to read 3, iclass 5, count 2 2006.173.15:43:36.59#ibcon#read 3, iclass 5, count 2 2006.173.15:43:36.59#ibcon#about to read 4, iclass 5, count 2 2006.173.15:43:36.59#ibcon#read 4, iclass 5, count 2 2006.173.15:43:36.59#ibcon#about to read 5, iclass 5, count 2 2006.173.15:43:36.59#ibcon#read 5, iclass 5, count 2 2006.173.15:43:36.59#ibcon#about to read 6, iclass 5, count 2 2006.173.15:43:36.59#ibcon#read 6, iclass 5, count 2 2006.173.15:43:36.59#ibcon#end of sib2, iclass 5, count 2 2006.173.15:43:36.59#ibcon#*mode == 0, iclass 5, count 2 2006.173.15:43:36.59#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.15:43:36.59#ibcon#[27=AT03-04\r\n] 2006.173.15:43:36.59#ibcon#*before write, iclass 5, count 2 2006.173.15:43:36.59#ibcon#enter sib2, iclass 5, count 2 2006.173.15:43:36.59#ibcon#flushed, iclass 5, count 2 2006.173.15:43:36.59#ibcon#about to write, iclass 5, count 2 2006.173.15:43:36.59#ibcon#wrote, iclass 5, count 2 2006.173.15:43:36.59#ibcon#about to read 3, iclass 5, count 2 2006.173.15:43:36.62#ibcon#read 3, iclass 5, count 2 2006.173.15:43:36.62#ibcon#about to read 4, iclass 5, count 2 2006.173.15:43:36.62#ibcon#read 4, iclass 5, count 2 2006.173.15:43:36.62#ibcon#about to read 5, iclass 5, count 2 2006.173.15:43:36.62#ibcon#read 5, iclass 5, count 2 2006.173.15:43:36.62#ibcon#about to read 6, iclass 5, count 2 2006.173.15:43:36.62#ibcon#read 6, iclass 5, count 2 2006.173.15:43:36.62#ibcon#end of sib2, iclass 5, count 2 2006.173.15:43:36.62#ibcon#*after write, iclass 5, count 2 2006.173.15:43:36.62#ibcon#*before return 0, iclass 5, count 2 2006.173.15:43:36.62#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.15:43:36.62#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.15:43:36.62#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.15:43:36.62#ibcon#ireg 7 cls_cnt 0 2006.173.15:43:36.62#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.15:43:36.74#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.15:43:36.74#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.15:43:36.74#ibcon#enter wrdev, iclass 5, count 0 2006.173.15:43:36.74#ibcon#first serial, iclass 5, count 0 2006.173.15:43:36.74#ibcon#enter sib2, iclass 5, count 0 2006.173.15:43:36.74#ibcon#flushed, iclass 5, count 0 2006.173.15:43:36.74#ibcon#about to write, iclass 5, count 0 2006.173.15:43:36.74#ibcon#wrote, iclass 5, count 0 2006.173.15:43:36.74#ibcon#about to read 3, iclass 5, count 0 2006.173.15:43:36.76#ibcon#read 3, iclass 5, count 0 2006.173.15:43:36.76#ibcon#about to read 4, iclass 5, count 0 2006.173.15:43:36.76#ibcon#read 4, iclass 5, count 0 2006.173.15:43:36.76#ibcon#about to read 5, iclass 5, count 0 2006.173.15:43:36.76#ibcon#read 5, iclass 5, count 0 2006.173.15:43:36.76#ibcon#about to read 6, iclass 5, count 0 2006.173.15:43:36.76#ibcon#read 6, iclass 5, count 0 2006.173.15:43:36.76#ibcon#end of sib2, iclass 5, count 0 2006.173.15:43:36.76#ibcon#*mode == 0, iclass 5, count 0 2006.173.15:43:36.76#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.15:43:36.76#ibcon#[27=USB\r\n] 2006.173.15:43:36.76#ibcon#*before write, iclass 5, count 0 2006.173.15:43:36.76#ibcon#enter sib2, iclass 5, count 0 2006.173.15:43:36.76#ibcon#flushed, iclass 5, count 0 2006.173.15:43:36.76#ibcon#about to write, iclass 5, count 0 2006.173.15:43:36.76#ibcon#wrote, iclass 5, count 0 2006.173.15:43:36.76#ibcon#about to read 3, iclass 5, count 0 2006.173.15:43:36.79#ibcon#read 3, iclass 5, count 0 2006.173.15:43:36.79#ibcon#about to read 4, iclass 5, count 0 2006.173.15:43:36.79#ibcon#read 4, iclass 5, count 0 2006.173.15:43:36.79#ibcon#about to read 5, iclass 5, count 0 2006.173.15:43:36.79#ibcon#read 5, iclass 5, count 0 2006.173.15:43:36.79#ibcon#about to read 6, iclass 5, count 0 2006.173.15:43:36.79#ibcon#read 6, iclass 5, count 0 2006.173.15:43:36.79#ibcon#end of sib2, iclass 5, count 0 2006.173.15:43:36.79#ibcon#*after write, iclass 5, count 0 2006.173.15:43:36.79#ibcon#*before return 0, iclass 5, count 0 2006.173.15:43:36.79#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.15:43:36.79#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.15:43:36.79#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.15:43:36.79#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.15:43:36.79$vck44/vblo=4,679.99 2006.173.15:43:36.79#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.15:43:36.79#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.15:43:36.79#ibcon#ireg 17 cls_cnt 0 2006.173.15:43:36.79#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.15:43:36.79#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.15:43:36.79#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.15:43:36.79#ibcon#enter wrdev, iclass 7, count 0 2006.173.15:43:36.79#ibcon#first serial, iclass 7, count 0 2006.173.15:43:36.79#ibcon#enter sib2, iclass 7, count 0 2006.173.15:43:36.79#ibcon#flushed, iclass 7, count 0 2006.173.15:43:36.79#ibcon#about to write, iclass 7, count 0 2006.173.15:43:36.79#ibcon#wrote, iclass 7, count 0 2006.173.15:43:36.79#ibcon#about to read 3, iclass 7, count 0 2006.173.15:43:36.81#ibcon#read 3, iclass 7, count 0 2006.173.15:43:36.81#ibcon#about to read 4, iclass 7, count 0 2006.173.15:43:36.81#ibcon#read 4, iclass 7, count 0 2006.173.15:43:36.81#ibcon#about to read 5, iclass 7, count 0 2006.173.15:43:36.81#ibcon#read 5, iclass 7, count 0 2006.173.15:43:36.81#ibcon#about to read 6, iclass 7, count 0 2006.173.15:43:36.81#ibcon#read 6, iclass 7, count 0 2006.173.15:43:36.81#ibcon#end of sib2, iclass 7, count 0 2006.173.15:43:36.81#ibcon#*mode == 0, iclass 7, count 0 2006.173.15:43:36.81#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.15:43:36.81#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.15:43:36.81#ibcon#*before write, iclass 7, count 0 2006.173.15:43:36.81#ibcon#enter sib2, iclass 7, count 0 2006.173.15:43:36.81#ibcon#flushed, iclass 7, count 0 2006.173.15:43:36.81#ibcon#about to write, iclass 7, count 0 2006.173.15:43:36.81#ibcon#wrote, iclass 7, count 0 2006.173.15:43:36.81#ibcon#about to read 3, iclass 7, count 0 2006.173.15:43:36.85#ibcon#read 3, iclass 7, count 0 2006.173.15:43:36.85#ibcon#about to read 4, iclass 7, count 0 2006.173.15:43:36.85#ibcon#read 4, iclass 7, count 0 2006.173.15:43:36.85#ibcon#about to read 5, iclass 7, count 0 2006.173.15:43:36.85#ibcon#read 5, iclass 7, count 0 2006.173.15:43:36.85#ibcon#about to read 6, iclass 7, count 0 2006.173.15:43:36.85#ibcon#read 6, iclass 7, count 0 2006.173.15:43:36.85#ibcon#end of sib2, iclass 7, count 0 2006.173.15:43:36.85#ibcon#*after write, iclass 7, count 0 2006.173.15:43:36.85#ibcon#*before return 0, iclass 7, count 0 2006.173.15:43:36.85#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.15:43:36.85#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.15:43:36.85#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.15:43:36.85#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.15:43:36.85$vck44/vb=4,4 2006.173.15:43:36.85#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.15:43:36.85#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.15:43:36.85#ibcon#ireg 11 cls_cnt 2 2006.173.15:43:36.85#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.15:43:36.91#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.15:43:36.91#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.15:43:36.91#ibcon#enter wrdev, iclass 11, count 2 2006.173.15:43:36.91#ibcon#first serial, iclass 11, count 2 2006.173.15:43:36.91#ibcon#enter sib2, iclass 11, count 2 2006.173.15:43:36.91#ibcon#flushed, iclass 11, count 2 2006.173.15:43:36.91#ibcon#about to write, iclass 11, count 2 2006.173.15:43:36.91#ibcon#wrote, iclass 11, count 2 2006.173.15:43:36.91#ibcon#about to read 3, iclass 11, count 2 2006.173.15:43:36.93#ibcon#read 3, iclass 11, count 2 2006.173.15:43:36.93#ibcon#about to read 4, iclass 11, count 2 2006.173.15:43:36.93#ibcon#read 4, iclass 11, count 2 2006.173.15:43:36.93#ibcon#about to read 5, iclass 11, count 2 2006.173.15:43:36.93#ibcon#read 5, iclass 11, count 2 2006.173.15:43:36.93#ibcon#about to read 6, iclass 11, count 2 2006.173.15:43:36.93#ibcon#read 6, iclass 11, count 2 2006.173.15:43:36.93#ibcon#end of sib2, iclass 11, count 2 2006.173.15:43:36.93#ibcon#*mode == 0, iclass 11, count 2 2006.173.15:43:36.93#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.15:43:36.93#ibcon#[27=AT04-04\r\n] 2006.173.15:43:36.93#ibcon#*before write, iclass 11, count 2 2006.173.15:43:36.93#ibcon#enter sib2, iclass 11, count 2 2006.173.15:43:36.93#ibcon#flushed, iclass 11, count 2 2006.173.15:43:36.93#ibcon#about to write, iclass 11, count 2 2006.173.15:43:36.93#ibcon#wrote, iclass 11, count 2 2006.173.15:43:36.93#ibcon#about to read 3, iclass 11, count 2 2006.173.15:43:36.96#ibcon#read 3, iclass 11, count 2 2006.173.15:43:36.96#ibcon#about to read 4, iclass 11, count 2 2006.173.15:43:36.96#ibcon#read 4, iclass 11, count 2 2006.173.15:43:36.96#ibcon#about to read 5, iclass 11, count 2 2006.173.15:43:36.96#ibcon#read 5, iclass 11, count 2 2006.173.15:43:36.96#ibcon#about to read 6, iclass 11, count 2 2006.173.15:43:36.96#ibcon#read 6, iclass 11, count 2 2006.173.15:43:36.96#ibcon#end of sib2, iclass 11, count 2 2006.173.15:43:36.96#ibcon#*after write, iclass 11, count 2 2006.173.15:43:36.96#ibcon#*before return 0, iclass 11, count 2 2006.173.15:43:36.96#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.15:43:36.96#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.15:43:36.96#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.15:43:36.96#ibcon#ireg 7 cls_cnt 0 2006.173.15:43:36.96#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.15:43:37.08#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.15:43:37.08#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.15:43:37.08#ibcon#enter wrdev, iclass 11, count 0 2006.173.15:43:37.08#ibcon#first serial, iclass 11, count 0 2006.173.15:43:37.08#ibcon#enter sib2, iclass 11, count 0 2006.173.15:43:37.08#ibcon#flushed, iclass 11, count 0 2006.173.15:43:37.08#ibcon#about to write, iclass 11, count 0 2006.173.15:43:37.08#ibcon#wrote, iclass 11, count 0 2006.173.15:43:37.08#ibcon#about to read 3, iclass 11, count 0 2006.173.15:43:37.10#ibcon#read 3, iclass 11, count 0 2006.173.15:43:37.10#ibcon#about to read 4, iclass 11, count 0 2006.173.15:43:37.10#ibcon#read 4, iclass 11, count 0 2006.173.15:43:37.10#ibcon#about to read 5, iclass 11, count 0 2006.173.15:43:37.10#ibcon#read 5, iclass 11, count 0 2006.173.15:43:37.10#ibcon#about to read 6, iclass 11, count 0 2006.173.15:43:37.10#ibcon#read 6, iclass 11, count 0 2006.173.15:43:37.10#ibcon#end of sib2, iclass 11, count 0 2006.173.15:43:37.10#ibcon#*mode == 0, iclass 11, count 0 2006.173.15:43:37.10#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.15:43:37.10#ibcon#[27=USB\r\n] 2006.173.15:43:37.10#ibcon#*before write, iclass 11, count 0 2006.173.15:43:37.10#ibcon#enter sib2, iclass 11, count 0 2006.173.15:43:37.10#ibcon#flushed, iclass 11, count 0 2006.173.15:43:37.10#ibcon#about to write, iclass 11, count 0 2006.173.15:43:37.10#ibcon#wrote, iclass 11, count 0 2006.173.15:43:37.10#ibcon#about to read 3, iclass 11, count 0 2006.173.15:43:37.13#ibcon#read 3, iclass 11, count 0 2006.173.15:43:37.13#ibcon#about to read 4, iclass 11, count 0 2006.173.15:43:37.13#ibcon#read 4, iclass 11, count 0 2006.173.15:43:37.13#ibcon#about to read 5, iclass 11, count 0 2006.173.15:43:37.13#ibcon#read 5, iclass 11, count 0 2006.173.15:43:37.13#ibcon#about to read 6, iclass 11, count 0 2006.173.15:43:37.13#ibcon#read 6, iclass 11, count 0 2006.173.15:43:37.13#ibcon#end of sib2, iclass 11, count 0 2006.173.15:43:37.13#ibcon#*after write, iclass 11, count 0 2006.173.15:43:37.13#ibcon#*before return 0, iclass 11, count 0 2006.173.15:43:37.13#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.15:43:37.13#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.15:43:37.13#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.15:43:37.13#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.15:43:37.13$vck44/vblo=5,709.99 2006.173.15:43:37.13#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.15:43:37.13#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.15:43:37.13#ibcon#ireg 17 cls_cnt 0 2006.173.15:43:37.13#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.15:43:37.13#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.15:43:37.13#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.15:43:37.13#ibcon#enter wrdev, iclass 13, count 0 2006.173.15:43:37.13#ibcon#first serial, iclass 13, count 0 2006.173.15:43:37.13#ibcon#enter sib2, iclass 13, count 0 2006.173.15:43:37.13#ibcon#flushed, iclass 13, count 0 2006.173.15:43:37.13#ibcon#about to write, iclass 13, count 0 2006.173.15:43:37.13#ibcon#wrote, iclass 13, count 0 2006.173.15:43:37.13#ibcon#about to read 3, iclass 13, count 0 2006.173.15:43:37.15#ibcon#read 3, iclass 13, count 0 2006.173.15:43:37.15#ibcon#about to read 4, iclass 13, count 0 2006.173.15:43:37.15#ibcon#read 4, iclass 13, count 0 2006.173.15:43:37.15#ibcon#about to read 5, iclass 13, count 0 2006.173.15:43:37.15#ibcon#read 5, iclass 13, count 0 2006.173.15:43:37.15#ibcon#about to read 6, iclass 13, count 0 2006.173.15:43:37.15#ibcon#read 6, iclass 13, count 0 2006.173.15:43:37.15#ibcon#end of sib2, iclass 13, count 0 2006.173.15:43:37.15#ibcon#*mode == 0, iclass 13, count 0 2006.173.15:43:37.15#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.15:43:37.15#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.15:43:37.15#ibcon#*before write, iclass 13, count 0 2006.173.15:43:37.15#ibcon#enter sib2, iclass 13, count 0 2006.173.15:43:37.15#ibcon#flushed, iclass 13, count 0 2006.173.15:43:37.15#ibcon#about to write, iclass 13, count 0 2006.173.15:43:37.15#ibcon#wrote, iclass 13, count 0 2006.173.15:43:37.15#ibcon#about to read 3, iclass 13, count 0 2006.173.15:43:37.19#ibcon#read 3, iclass 13, count 0 2006.173.15:43:37.19#ibcon#about to read 4, iclass 13, count 0 2006.173.15:43:37.19#ibcon#read 4, iclass 13, count 0 2006.173.15:43:37.19#ibcon#about to read 5, iclass 13, count 0 2006.173.15:43:37.19#ibcon#read 5, iclass 13, count 0 2006.173.15:43:37.19#ibcon#about to read 6, iclass 13, count 0 2006.173.15:43:37.19#ibcon#read 6, iclass 13, count 0 2006.173.15:43:37.19#ibcon#end of sib2, iclass 13, count 0 2006.173.15:43:37.19#ibcon#*after write, iclass 13, count 0 2006.173.15:43:37.19#ibcon#*before return 0, iclass 13, count 0 2006.173.15:43:37.19#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.15:43:37.19#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.15:43:37.19#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.15:43:37.19#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.15:43:37.19$vck44/vb=5,4 2006.173.15:43:37.19#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.15:43:37.19#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.15:43:37.19#ibcon#ireg 11 cls_cnt 2 2006.173.15:43:37.19#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.15:43:37.25#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.15:43:37.25#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.15:43:37.25#ibcon#enter wrdev, iclass 15, count 2 2006.173.15:43:37.25#ibcon#first serial, iclass 15, count 2 2006.173.15:43:37.25#ibcon#enter sib2, iclass 15, count 2 2006.173.15:43:37.25#ibcon#flushed, iclass 15, count 2 2006.173.15:43:37.25#ibcon#about to write, iclass 15, count 2 2006.173.15:43:37.25#ibcon#wrote, iclass 15, count 2 2006.173.15:43:37.25#ibcon#about to read 3, iclass 15, count 2 2006.173.15:43:37.27#ibcon#read 3, iclass 15, count 2 2006.173.15:43:37.27#ibcon#about to read 4, iclass 15, count 2 2006.173.15:43:37.27#ibcon#read 4, iclass 15, count 2 2006.173.15:43:37.27#ibcon#about to read 5, iclass 15, count 2 2006.173.15:43:37.27#ibcon#read 5, iclass 15, count 2 2006.173.15:43:37.27#ibcon#about to read 6, iclass 15, count 2 2006.173.15:43:37.27#ibcon#read 6, iclass 15, count 2 2006.173.15:43:37.27#ibcon#end of sib2, iclass 15, count 2 2006.173.15:43:37.27#ibcon#*mode == 0, iclass 15, count 2 2006.173.15:43:37.27#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.15:43:37.27#ibcon#[27=AT05-04\r\n] 2006.173.15:43:37.27#ibcon#*before write, iclass 15, count 2 2006.173.15:43:37.27#ibcon#enter sib2, iclass 15, count 2 2006.173.15:43:37.27#ibcon#flushed, iclass 15, count 2 2006.173.15:43:37.27#ibcon#about to write, iclass 15, count 2 2006.173.15:43:37.27#ibcon#wrote, iclass 15, count 2 2006.173.15:43:37.27#ibcon#about to read 3, iclass 15, count 2 2006.173.15:43:37.30#ibcon#read 3, iclass 15, count 2 2006.173.15:43:37.30#ibcon#about to read 4, iclass 15, count 2 2006.173.15:43:37.30#ibcon#read 4, iclass 15, count 2 2006.173.15:43:37.30#ibcon#about to read 5, iclass 15, count 2 2006.173.15:43:37.30#ibcon#read 5, iclass 15, count 2 2006.173.15:43:37.30#ibcon#about to read 6, iclass 15, count 2 2006.173.15:43:37.30#ibcon#read 6, iclass 15, count 2 2006.173.15:43:37.30#ibcon#end of sib2, iclass 15, count 2 2006.173.15:43:37.30#ibcon#*after write, iclass 15, count 2 2006.173.15:43:37.30#ibcon#*before return 0, iclass 15, count 2 2006.173.15:43:37.30#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.15:43:37.30#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.15:43:37.30#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.15:43:37.30#ibcon#ireg 7 cls_cnt 0 2006.173.15:43:37.30#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.15:43:37.42#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.15:43:37.42#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.15:43:37.42#ibcon#enter wrdev, iclass 15, count 0 2006.173.15:43:37.42#ibcon#first serial, iclass 15, count 0 2006.173.15:43:37.42#ibcon#enter sib2, iclass 15, count 0 2006.173.15:43:37.42#ibcon#flushed, iclass 15, count 0 2006.173.15:43:37.42#ibcon#about to write, iclass 15, count 0 2006.173.15:43:37.42#ibcon#wrote, iclass 15, count 0 2006.173.15:43:37.42#ibcon#about to read 3, iclass 15, count 0 2006.173.15:43:37.44#ibcon#read 3, iclass 15, count 0 2006.173.15:43:37.44#ibcon#about to read 4, iclass 15, count 0 2006.173.15:43:37.44#ibcon#read 4, iclass 15, count 0 2006.173.15:43:37.44#ibcon#about to read 5, iclass 15, count 0 2006.173.15:43:37.44#ibcon#read 5, iclass 15, count 0 2006.173.15:43:37.44#ibcon#about to read 6, iclass 15, count 0 2006.173.15:43:37.44#ibcon#read 6, iclass 15, count 0 2006.173.15:43:37.44#ibcon#end of sib2, iclass 15, count 0 2006.173.15:43:37.44#ibcon#*mode == 0, iclass 15, count 0 2006.173.15:43:37.44#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.15:43:37.44#ibcon#[27=USB\r\n] 2006.173.15:43:37.44#ibcon#*before write, iclass 15, count 0 2006.173.15:43:37.44#ibcon#enter sib2, iclass 15, count 0 2006.173.15:43:37.44#ibcon#flushed, iclass 15, count 0 2006.173.15:43:37.44#ibcon#about to write, iclass 15, count 0 2006.173.15:43:37.44#ibcon#wrote, iclass 15, count 0 2006.173.15:43:37.44#ibcon#about to read 3, iclass 15, count 0 2006.173.15:43:37.47#ibcon#read 3, iclass 15, count 0 2006.173.15:43:37.47#ibcon#about to read 4, iclass 15, count 0 2006.173.15:43:37.47#ibcon#read 4, iclass 15, count 0 2006.173.15:43:37.47#ibcon#about to read 5, iclass 15, count 0 2006.173.15:43:37.47#ibcon#read 5, iclass 15, count 0 2006.173.15:43:37.47#ibcon#about to read 6, iclass 15, count 0 2006.173.15:43:37.47#ibcon#read 6, iclass 15, count 0 2006.173.15:43:37.47#ibcon#end of sib2, iclass 15, count 0 2006.173.15:43:37.47#ibcon#*after write, iclass 15, count 0 2006.173.15:43:37.47#ibcon#*before return 0, iclass 15, count 0 2006.173.15:43:37.47#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.15:43:37.47#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.15:43:37.47#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.15:43:37.47#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.15:43:37.47$vck44/vblo=6,719.99 2006.173.15:43:37.47#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.15:43:37.47#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.15:43:37.47#ibcon#ireg 17 cls_cnt 0 2006.173.15:43:37.47#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.15:43:37.47#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.15:43:37.47#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.15:43:37.47#ibcon#enter wrdev, iclass 17, count 0 2006.173.15:43:37.47#ibcon#first serial, iclass 17, count 0 2006.173.15:43:37.47#ibcon#enter sib2, iclass 17, count 0 2006.173.15:43:37.47#ibcon#flushed, iclass 17, count 0 2006.173.15:43:37.47#ibcon#about to write, iclass 17, count 0 2006.173.15:43:37.47#ibcon#wrote, iclass 17, count 0 2006.173.15:43:37.47#ibcon#about to read 3, iclass 17, count 0 2006.173.15:43:37.49#ibcon#read 3, iclass 17, count 0 2006.173.15:43:37.49#ibcon#about to read 4, iclass 17, count 0 2006.173.15:43:37.49#ibcon#read 4, iclass 17, count 0 2006.173.15:43:37.49#ibcon#about to read 5, iclass 17, count 0 2006.173.15:43:37.49#ibcon#read 5, iclass 17, count 0 2006.173.15:43:37.49#ibcon#about to read 6, iclass 17, count 0 2006.173.15:43:37.49#ibcon#read 6, iclass 17, count 0 2006.173.15:43:37.49#ibcon#end of sib2, iclass 17, count 0 2006.173.15:43:37.49#ibcon#*mode == 0, iclass 17, count 0 2006.173.15:43:37.49#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.15:43:37.49#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.15:43:37.49#ibcon#*before write, iclass 17, count 0 2006.173.15:43:37.49#ibcon#enter sib2, iclass 17, count 0 2006.173.15:43:37.49#ibcon#flushed, iclass 17, count 0 2006.173.15:43:37.49#ibcon#about to write, iclass 17, count 0 2006.173.15:43:37.49#ibcon#wrote, iclass 17, count 0 2006.173.15:43:37.49#ibcon#about to read 3, iclass 17, count 0 2006.173.15:43:37.53#ibcon#read 3, iclass 17, count 0 2006.173.15:43:37.53#ibcon#about to read 4, iclass 17, count 0 2006.173.15:43:37.53#ibcon#read 4, iclass 17, count 0 2006.173.15:43:37.53#ibcon#about to read 5, iclass 17, count 0 2006.173.15:43:37.53#ibcon#read 5, iclass 17, count 0 2006.173.15:43:37.53#ibcon#about to read 6, iclass 17, count 0 2006.173.15:43:37.53#ibcon#read 6, iclass 17, count 0 2006.173.15:43:37.53#ibcon#end of sib2, iclass 17, count 0 2006.173.15:43:37.53#ibcon#*after write, iclass 17, count 0 2006.173.15:43:37.53#ibcon#*before return 0, iclass 17, count 0 2006.173.15:43:37.53#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.15:43:37.53#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.15:43:37.53#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.15:43:37.53#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.15:43:37.53$vck44/vb=6,4 2006.173.15:43:37.53#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.15:43:37.53#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.15:43:37.53#ibcon#ireg 11 cls_cnt 2 2006.173.15:43:37.53#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.15:43:37.59#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.15:43:37.59#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.15:43:37.59#ibcon#enter wrdev, iclass 19, count 2 2006.173.15:43:37.59#ibcon#first serial, iclass 19, count 2 2006.173.15:43:37.59#ibcon#enter sib2, iclass 19, count 2 2006.173.15:43:37.59#ibcon#flushed, iclass 19, count 2 2006.173.15:43:37.59#ibcon#about to write, iclass 19, count 2 2006.173.15:43:37.59#ibcon#wrote, iclass 19, count 2 2006.173.15:43:37.59#ibcon#about to read 3, iclass 19, count 2 2006.173.15:43:37.61#ibcon#read 3, iclass 19, count 2 2006.173.15:43:37.61#ibcon#about to read 4, iclass 19, count 2 2006.173.15:43:37.61#ibcon#read 4, iclass 19, count 2 2006.173.15:43:37.61#ibcon#about to read 5, iclass 19, count 2 2006.173.15:43:37.61#ibcon#read 5, iclass 19, count 2 2006.173.15:43:37.61#ibcon#about to read 6, iclass 19, count 2 2006.173.15:43:37.61#ibcon#read 6, iclass 19, count 2 2006.173.15:43:37.61#ibcon#end of sib2, iclass 19, count 2 2006.173.15:43:37.61#ibcon#*mode == 0, iclass 19, count 2 2006.173.15:43:37.61#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.15:43:37.61#ibcon#[27=AT06-04\r\n] 2006.173.15:43:37.61#ibcon#*before write, iclass 19, count 2 2006.173.15:43:37.61#ibcon#enter sib2, iclass 19, count 2 2006.173.15:43:37.61#ibcon#flushed, iclass 19, count 2 2006.173.15:43:37.61#ibcon#about to write, iclass 19, count 2 2006.173.15:43:37.61#ibcon#wrote, iclass 19, count 2 2006.173.15:43:37.61#ibcon#about to read 3, iclass 19, count 2 2006.173.15:43:37.64#ibcon#read 3, iclass 19, count 2 2006.173.15:43:37.64#ibcon#about to read 4, iclass 19, count 2 2006.173.15:43:37.64#ibcon#read 4, iclass 19, count 2 2006.173.15:43:37.64#ibcon#about to read 5, iclass 19, count 2 2006.173.15:43:37.64#ibcon#read 5, iclass 19, count 2 2006.173.15:43:37.64#ibcon#about to read 6, iclass 19, count 2 2006.173.15:43:37.64#ibcon#read 6, iclass 19, count 2 2006.173.15:43:37.64#ibcon#end of sib2, iclass 19, count 2 2006.173.15:43:37.64#ibcon#*after write, iclass 19, count 2 2006.173.15:43:37.64#ibcon#*before return 0, iclass 19, count 2 2006.173.15:43:37.64#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.15:43:37.64#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.15:43:37.64#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.15:43:37.64#ibcon#ireg 7 cls_cnt 0 2006.173.15:43:37.64#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.15:43:37.76#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.15:43:37.76#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.15:43:37.76#ibcon#enter wrdev, iclass 19, count 0 2006.173.15:43:37.76#ibcon#first serial, iclass 19, count 0 2006.173.15:43:37.76#ibcon#enter sib2, iclass 19, count 0 2006.173.15:43:37.76#ibcon#flushed, iclass 19, count 0 2006.173.15:43:37.76#ibcon#about to write, iclass 19, count 0 2006.173.15:43:37.76#ibcon#wrote, iclass 19, count 0 2006.173.15:43:37.76#ibcon#about to read 3, iclass 19, count 0 2006.173.15:43:37.78#ibcon#read 3, iclass 19, count 0 2006.173.15:43:37.78#ibcon#about to read 4, iclass 19, count 0 2006.173.15:43:37.78#ibcon#read 4, iclass 19, count 0 2006.173.15:43:37.78#ibcon#about to read 5, iclass 19, count 0 2006.173.15:43:37.78#ibcon#read 5, iclass 19, count 0 2006.173.15:43:37.78#ibcon#about to read 6, iclass 19, count 0 2006.173.15:43:37.78#ibcon#read 6, iclass 19, count 0 2006.173.15:43:37.78#ibcon#end of sib2, iclass 19, count 0 2006.173.15:43:37.78#ibcon#*mode == 0, iclass 19, count 0 2006.173.15:43:37.78#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.15:43:37.78#ibcon#[27=USB\r\n] 2006.173.15:43:37.78#ibcon#*before write, iclass 19, count 0 2006.173.15:43:37.78#ibcon#enter sib2, iclass 19, count 0 2006.173.15:43:37.78#ibcon#flushed, iclass 19, count 0 2006.173.15:43:37.78#ibcon#about to write, iclass 19, count 0 2006.173.15:43:37.78#ibcon#wrote, iclass 19, count 0 2006.173.15:43:37.78#ibcon#about to read 3, iclass 19, count 0 2006.173.15:43:37.81#ibcon#read 3, iclass 19, count 0 2006.173.15:43:37.81#ibcon#about to read 4, iclass 19, count 0 2006.173.15:43:37.81#ibcon#read 4, iclass 19, count 0 2006.173.15:43:37.81#ibcon#about to read 5, iclass 19, count 0 2006.173.15:43:37.81#ibcon#read 5, iclass 19, count 0 2006.173.15:43:37.81#ibcon#about to read 6, iclass 19, count 0 2006.173.15:43:37.81#ibcon#read 6, iclass 19, count 0 2006.173.15:43:37.81#ibcon#end of sib2, iclass 19, count 0 2006.173.15:43:37.81#ibcon#*after write, iclass 19, count 0 2006.173.15:43:37.81#ibcon#*before return 0, iclass 19, count 0 2006.173.15:43:37.81#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.15:43:37.81#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.15:43:37.81#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.15:43:37.81#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.15:43:37.81$vck44/vblo=7,734.99 2006.173.15:43:37.81#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.15:43:37.81#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.15:43:37.81#ibcon#ireg 17 cls_cnt 0 2006.173.15:43:37.81#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.15:43:37.81#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.15:43:37.81#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.15:43:37.81#ibcon#enter wrdev, iclass 21, count 0 2006.173.15:43:37.81#ibcon#first serial, iclass 21, count 0 2006.173.15:43:37.81#ibcon#enter sib2, iclass 21, count 0 2006.173.15:43:37.81#ibcon#flushed, iclass 21, count 0 2006.173.15:43:37.81#ibcon#about to write, iclass 21, count 0 2006.173.15:43:37.81#ibcon#wrote, iclass 21, count 0 2006.173.15:43:37.81#ibcon#about to read 3, iclass 21, count 0 2006.173.15:43:37.83#ibcon#read 3, iclass 21, count 0 2006.173.15:43:37.83#ibcon#about to read 4, iclass 21, count 0 2006.173.15:43:37.83#ibcon#read 4, iclass 21, count 0 2006.173.15:43:37.83#ibcon#about to read 5, iclass 21, count 0 2006.173.15:43:37.83#ibcon#read 5, iclass 21, count 0 2006.173.15:43:37.83#ibcon#about to read 6, iclass 21, count 0 2006.173.15:43:37.83#ibcon#read 6, iclass 21, count 0 2006.173.15:43:37.83#ibcon#end of sib2, iclass 21, count 0 2006.173.15:43:37.83#ibcon#*mode == 0, iclass 21, count 0 2006.173.15:43:37.83#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.15:43:37.83#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.15:43:37.83#ibcon#*before write, iclass 21, count 0 2006.173.15:43:37.83#ibcon#enter sib2, iclass 21, count 0 2006.173.15:43:37.83#ibcon#flushed, iclass 21, count 0 2006.173.15:43:37.83#ibcon#about to write, iclass 21, count 0 2006.173.15:43:37.83#ibcon#wrote, iclass 21, count 0 2006.173.15:43:37.83#ibcon#about to read 3, iclass 21, count 0 2006.173.15:43:37.87#ibcon#read 3, iclass 21, count 0 2006.173.15:43:37.87#ibcon#about to read 4, iclass 21, count 0 2006.173.15:43:37.87#ibcon#read 4, iclass 21, count 0 2006.173.15:43:37.87#ibcon#about to read 5, iclass 21, count 0 2006.173.15:43:37.87#ibcon#read 5, iclass 21, count 0 2006.173.15:43:37.87#ibcon#about to read 6, iclass 21, count 0 2006.173.15:43:37.87#ibcon#read 6, iclass 21, count 0 2006.173.15:43:37.87#ibcon#end of sib2, iclass 21, count 0 2006.173.15:43:37.87#ibcon#*after write, iclass 21, count 0 2006.173.15:43:37.87#ibcon#*before return 0, iclass 21, count 0 2006.173.15:43:37.87#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.15:43:37.87#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.15:43:37.87#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.15:43:37.87#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.15:43:37.87$vck44/vb=7,4 2006.173.15:43:37.87#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.15:43:37.87#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.15:43:37.87#ibcon#ireg 11 cls_cnt 2 2006.173.15:43:37.87#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.15:43:37.93#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.15:43:37.93#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.15:43:37.93#ibcon#enter wrdev, iclass 23, count 2 2006.173.15:43:37.93#ibcon#first serial, iclass 23, count 2 2006.173.15:43:37.93#ibcon#enter sib2, iclass 23, count 2 2006.173.15:43:37.93#ibcon#flushed, iclass 23, count 2 2006.173.15:43:37.93#ibcon#about to write, iclass 23, count 2 2006.173.15:43:37.93#ibcon#wrote, iclass 23, count 2 2006.173.15:43:37.93#ibcon#about to read 3, iclass 23, count 2 2006.173.15:43:37.95#ibcon#read 3, iclass 23, count 2 2006.173.15:43:37.95#ibcon#about to read 4, iclass 23, count 2 2006.173.15:43:37.95#ibcon#read 4, iclass 23, count 2 2006.173.15:43:37.95#ibcon#about to read 5, iclass 23, count 2 2006.173.15:43:37.95#ibcon#read 5, iclass 23, count 2 2006.173.15:43:37.95#ibcon#about to read 6, iclass 23, count 2 2006.173.15:43:37.95#ibcon#read 6, iclass 23, count 2 2006.173.15:43:37.95#ibcon#end of sib2, iclass 23, count 2 2006.173.15:43:37.95#ibcon#*mode == 0, iclass 23, count 2 2006.173.15:43:37.95#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.15:43:37.95#ibcon#[27=AT07-04\r\n] 2006.173.15:43:37.95#ibcon#*before write, iclass 23, count 2 2006.173.15:43:37.95#ibcon#enter sib2, iclass 23, count 2 2006.173.15:43:37.95#ibcon#flushed, iclass 23, count 2 2006.173.15:43:37.95#ibcon#about to write, iclass 23, count 2 2006.173.15:43:37.95#ibcon#wrote, iclass 23, count 2 2006.173.15:43:37.95#ibcon#about to read 3, iclass 23, count 2 2006.173.15:43:37.98#ibcon#read 3, iclass 23, count 2 2006.173.15:43:37.98#ibcon#about to read 4, iclass 23, count 2 2006.173.15:43:37.98#ibcon#read 4, iclass 23, count 2 2006.173.15:43:37.98#ibcon#about to read 5, iclass 23, count 2 2006.173.15:43:37.98#ibcon#read 5, iclass 23, count 2 2006.173.15:43:37.98#ibcon#about to read 6, iclass 23, count 2 2006.173.15:43:37.98#ibcon#read 6, iclass 23, count 2 2006.173.15:43:37.98#ibcon#end of sib2, iclass 23, count 2 2006.173.15:43:37.98#ibcon#*after write, iclass 23, count 2 2006.173.15:43:37.98#ibcon#*before return 0, iclass 23, count 2 2006.173.15:43:37.98#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.15:43:37.98#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.15:43:37.98#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.15:43:37.98#ibcon#ireg 7 cls_cnt 0 2006.173.15:43:37.98#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.15:43:38.10#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.15:43:38.10#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.15:43:38.10#ibcon#enter wrdev, iclass 23, count 0 2006.173.15:43:38.10#ibcon#first serial, iclass 23, count 0 2006.173.15:43:38.10#ibcon#enter sib2, iclass 23, count 0 2006.173.15:43:38.10#ibcon#flushed, iclass 23, count 0 2006.173.15:43:38.10#ibcon#about to write, iclass 23, count 0 2006.173.15:43:38.10#ibcon#wrote, iclass 23, count 0 2006.173.15:43:38.10#ibcon#about to read 3, iclass 23, count 0 2006.173.15:43:38.12#ibcon#read 3, iclass 23, count 0 2006.173.15:43:38.12#ibcon#about to read 4, iclass 23, count 0 2006.173.15:43:38.12#ibcon#read 4, iclass 23, count 0 2006.173.15:43:38.12#ibcon#about to read 5, iclass 23, count 0 2006.173.15:43:38.12#ibcon#read 5, iclass 23, count 0 2006.173.15:43:38.12#ibcon#about to read 6, iclass 23, count 0 2006.173.15:43:38.12#ibcon#read 6, iclass 23, count 0 2006.173.15:43:38.12#ibcon#end of sib2, iclass 23, count 0 2006.173.15:43:38.12#ibcon#*mode == 0, iclass 23, count 0 2006.173.15:43:38.12#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.15:43:38.12#ibcon#[27=USB\r\n] 2006.173.15:43:38.12#ibcon#*before write, iclass 23, count 0 2006.173.15:43:38.12#ibcon#enter sib2, iclass 23, count 0 2006.173.15:43:38.12#ibcon#flushed, iclass 23, count 0 2006.173.15:43:38.12#ibcon#about to write, iclass 23, count 0 2006.173.15:43:38.12#ibcon#wrote, iclass 23, count 0 2006.173.15:43:38.12#ibcon#about to read 3, iclass 23, count 0 2006.173.15:43:38.15#ibcon#read 3, iclass 23, count 0 2006.173.15:43:38.15#ibcon#about to read 4, iclass 23, count 0 2006.173.15:43:38.15#ibcon#read 4, iclass 23, count 0 2006.173.15:43:38.15#ibcon#about to read 5, iclass 23, count 0 2006.173.15:43:38.15#ibcon#read 5, iclass 23, count 0 2006.173.15:43:38.15#ibcon#about to read 6, iclass 23, count 0 2006.173.15:43:38.15#ibcon#read 6, iclass 23, count 0 2006.173.15:43:38.15#ibcon#end of sib2, iclass 23, count 0 2006.173.15:43:38.15#ibcon#*after write, iclass 23, count 0 2006.173.15:43:38.15#ibcon#*before return 0, iclass 23, count 0 2006.173.15:43:38.15#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.15:43:38.15#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.15:43:38.15#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.15:43:38.15#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.15:43:38.15$vck44/vblo=8,744.99 2006.173.15:43:38.15#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.15:43:38.15#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.15:43:38.15#ibcon#ireg 17 cls_cnt 0 2006.173.15:43:38.15#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.15:43:38.15#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.15:43:38.15#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.15:43:38.15#ibcon#enter wrdev, iclass 25, count 0 2006.173.15:43:38.15#ibcon#first serial, iclass 25, count 0 2006.173.15:43:38.15#ibcon#enter sib2, iclass 25, count 0 2006.173.15:43:38.15#ibcon#flushed, iclass 25, count 0 2006.173.15:43:38.15#ibcon#about to write, iclass 25, count 0 2006.173.15:43:38.15#ibcon#wrote, iclass 25, count 0 2006.173.15:43:38.15#ibcon#about to read 3, iclass 25, count 0 2006.173.15:43:38.17#ibcon#read 3, iclass 25, count 0 2006.173.15:43:38.17#ibcon#about to read 4, iclass 25, count 0 2006.173.15:43:38.17#ibcon#read 4, iclass 25, count 0 2006.173.15:43:38.17#ibcon#about to read 5, iclass 25, count 0 2006.173.15:43:38.17#ibcon#read 5, iclass 25, count 0 2006.173.15:43:38.17#ibcon#about to read 6, iclass 25, count 0 2006.173.15:43:38.17#ibcon#read 6, iclass 25, count 0 2006.173.15:43:38.17#ibcon#end of sib2, iclass 25, count 0 2006.173.15:43:38.17#ibcon#*mode == 0, iclass 25, count 0 2006.173.15:43:38.17#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.15:43:38.17#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.15:43:38.17#ibcon#*before write, iclass 25, count 0 2006.173.15:43:38.17#ibcon#enter sib2, iclass 25, count 0 2006.173.15:43:38.17#ibcon#flushed, iclass 25, count 0 2006.173.15:43:38.17#ibcon#about to write, iclass 25, count 0 2006.173.15:43:38.17#ibcon#wrote, iclass 25, count 0 2006.173.15:43:38.17#ibcon#about to read 3, iclass 25, count 0 2006.173.15:43:38.21#ibcon#read 3, iclass 25, count 0 2006.173.15:43:38.21#ibcon#about to read 4, iclass 25, count 0 2006.173.15:43:38.21#ibcon#read 4, iclass 25, count 0 2006.173.15:43:38.21#ibcon#about to read 5, iclass 25, count 0 2006.173.15:43:38.21#ibcon#read 5, iclass 25, count 0 2006.173.15:43:38.21#ibcon#about to read 6, iclass 25, count 0 2006.173.15:43:38.21#ibcon#read 6, iclass 25, count 0 2006.173.15:43:38.21#ibcon#end of sib2, iclass 25, count 0 2006.173.15:43:38.21#ibcon#*after write, iclass 25, count 0 2006.173.15:43:38.21#ibcon#*before return 0, iclass 25, count 0 2006.173.15:43:38.21#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.15:43:38.21#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.15:43:38.21#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.15:43:38.21#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.15:43:38.21$vck44/vb=8,4 2006.173.15:43:38.21#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.15:43:38.21#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.15:43:38.21#ibcon#ireg 11 cls_cnt 2 2006.173.15:43:38.21#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.15:43:38.27#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.15:43:38.27#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.15:43:38.27#ibcon#enter wrdev, iclass 27, count 2 2006.173.15:43:38.27#ibcon#first serial, iclass 27, count 2 2006.173.15:43:38.27#ibcon#enter sib2, iclass 27, count 2 2006.173.15:43:38.27#ibcon#flushed, iclass 27, count 2 2006.173.15:43:38.27#ibcon#about to write, iclass 27, count 2 2006.173.15:43:38.27#ibcon#wrote, iclass 27, count 2 2006.173.15:43:38.27#ibcon#about to read 3, iclass 27, count 2 2006.173.15:43:38.29#ibcon#read 3, iclass 27, count 2 2006.173.15:43:38.29#ibcon#about to read 4, iclass 27, count 2 2006.173.15:43:38.29#ibcon#read 4, iclass 27, count 2 2006.173.15:43:38.29#ibcon#about to read 5, iclass 27, count 2 2006.173.15:43:38.29#ibcon#read 5, iclass 27, count 2 2006.173.15:43:38.29#ibcon#about to read 6, iclass 27, count 2 2006.173.15:43:38.29#ibcon#read 6, iclass 27, count 2 2006.173.15:43:38.29#ibcon#end of sib2, iclass 27, count 2 2006.173.15:43:38.29#ibcon#*mode == 0, iclass 27, count 2 2006.173.15:43:38.29#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.15:43:38.29#ibcon#[27=AT08-04\r\n] 2006.173.15:43:38.29#ibcon#*before write, iclass 27, count 2 2006.173.15:43:38.29#ibcon#enter sib2, iclass 27, count 2 2006.173.15:43:38.29#ibcon#flushed, iclass 27, count 2 2006.173.15:43:38.29#ibcon#about to write, iclass 27, count 2 2006.173.15:43:38.29#ibcon#wrote, iclass 27, count 2 2006.173.15:43:38.29#ibcon#about to read 3, iclass 27, count 2 2006.173.15:43:38.32#ibcon#read 3, iclass 27, count 2 2006.173.15:43:38.32#ibcon#about to read 4, iclass 27, count 2 2006.173.15:43:38.32#ibcon#read 4, iclass 27, count 2 2006.173.15:43:38.32#ibcon#about to read 5, iclass 27, count 2 2006.173.15:43:38.32#ibcon#read 5, iclass 27, count 2 2006.173.15:43:38.32#ibcon#about to read 6, iclass 27, count 2 2006.173.15:43:38.32#ibcon#read 6, iclass 27, count 2 2006.173.15:43:38.32#ibcon#end of sib2, iclass 27, count 2 2006.173.15:43:38.32#ibcon#*after write, iclass 27, count 2 2006.173.15:43:38.32#ibcon#*before return 0, iclass 27, count 2 2006.173.15:43:38.32#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.15:43:38.32#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.15:43:38.32#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.15:43:38.32#ibcon#ireg 7 cls_cnt 0 2006.173.15:43:38.32#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.15:43:38.44#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.15:43:38.44#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.15:43:38.44#ibcon#enter wrdev, iclass 27, count 0 2006.173.15:43:38.44#ibcon#first serial, iclass 27, count 0 2006.173.15:43:38.44#ibcon#enter sib2, iclass 27, count 0 2006.173.15:43:38.44#ibcon#flushed, iclass 27, count 0 2006.173.15:43:38.44#ibcon#about to write, iclass 27, count 0 2006.173.15:43:38.44#ibcon#wrote, iclass 27, count 0 2006.173.15:43:38.44#ibcon#about to read 3, iclass 27, count 0 2006.173.15:43:38.46#ibcon#read 3, iclass 27, count 0 2006.173.15:43:38.46#ibcon#about to read 4, iclass 27, count 0 2006.173.15:43:38.46#ibcon#read 4, iclass 27, count 0 2006.173.15:43:38.46#ibcon#about to read 5, iclass 27, count 0 2006.173.15:43:38.46#ibcon#read 5, iclass 27, count 0 2006.173.15:43:38.46#ibcon#about to read 6, iclass 27, count 0 2006.173.15:43:38.46#ibcon#read 6, iclass 27, count 0 2006.173.15:43:38.46#ibcon#end of sib2, iclass 27, count 0 2006.173.15:43:38.46#ibcon#*mode == 0, iclass 27, count 0 2006.173.15:43:38.46#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.15:43:38.46#ibcon#[27=USB\r\n] 2006.173.15:43:38.46#ibcon#*before write, iclass 27, count 0 2006.173.15:43:38.46#ibcon#enter sib2, iclass 27, count 0 2006.173.15:43:38.46#ibcon#flushed, iclass 27, count 0 2006.173.15:43:38.46#ibcon#about to write, iclass 27, count 0 2006.173.15:43:38.46#ibcon#wrote, iclass 27, count 0 2006.173.15:43:38.46#ibcon#about to read 3, iclass 27, count 0 2006.173.15:43:38.48#abcon#<5=/15 1.0 2.3 20.901001003.0\r\n> 2006.173.15:43:38.49#ibcon#read 3, iclass 27, count 0 2006.173.15:43:38.49#ibcon#about to read 4, iclass 27, count 0 2006.173.15:43:38.49#ibcon#read 4, iclass 27, count 0 2006.173.15:43:38.49#ibcon#about to read 5, iclass 27, count 0 2006.173.15:43:38.49#ibcon#read 5, iclass 27, count 0 2006.173.15:43:38.49#ibcon#about to read 6, iclass 27, count 0 2006.173.15:43:38.49#ibcon#read 6, iclass 27, count 0 2006.173.15:43:38.49#ibcon#end of sib2, iclass 27, count 0 2006.173.15:43:38.49#ibcon#*after write, iclass 27, count 0 2006.173.15:43:38.49#ibcon#*before return 0, iclass 27, count 0 2006.173.15:43:38.49#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.15:43:38.49#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.15:43:38.49#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.15:43:38.49#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.15:43:38.49$vck44/vabw=wide 2006.173.15:43:38.49#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.15:43:38.49#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.15:43:38.49#ibcon#ireg 8 cls_cnt 0 2006.173.15:43:38.49#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.15:43:38.49#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.15:43:38.49#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.15:43:38.49#ibcon#enter wrdev, iclass 32, count 0 2006.173.15:43:38.49#ibcon#first serial, iclass 32, count 0 2006.173.15:43:38.49#ibcon#enter sib2, iclass 32, count 0 2006.173.15:43:38.49#ibcon#flushed, iclass 32, count 0 2006.173.15:43:38.49#ibcon#about to write, iclass 32, count 0 2006.173.15:43:38.49#ibcon#wrote, iclass 32, count 0 2006.173.15:43:38.49#ibcon#about to read 3, iclass 32, count 0 2006.173.15:43:38.50#abcon#{5=INTERFACE CLEAR} 2006.173.15:43:38.51#ibcon#read 3, iclass 32, count 0 2006.173.15:43:38.51#ibcon#about to read 4, iclass 32, count 0 2006.173.15:43:38.51#ibcon#read 4, iclass 32, count 0 2006.173.15:43:38.51#ibcon#about to read 5, iclass 32, count 0 2006.173.15:43:38.51#ibcon#read 5, iclass 32, count 0 2006.173.15:43:38.51#ibcon#about to read 6, iclass 32, count 0 2006.173.15:43:38.51#ibcon#read 6, iclass 32, count 0 2006.173.15:43:38.51#ibcon#end of sib2, iclass 32, count 0 2006.173.15:43:38.51#ibcon#*mode == 0, iclass 32, count 0 2006.173.15:43:38.51#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.15:43:38.51#ibcon#[25=BW32\r\n] 2006.173.15:43:38.51#ibcon#*before write, iclass 32, count 0 2006.173.15:43:38.51#ibcon#enter sib2, iclass 32, count 0 2006.173.15:43:38.51#ibcon#flushed, iclass 32, count 0 2006.173.15:43:38.51#ibcon#about to write, iclass 32, count 0 2006.173.15:43:38.51#ibcon#wrote, iclass 32, count 0 2006.173.15:43:38.51#ibcon#about to read 3, iclass 32, count 0 2006.173.15:43:38.54#ibcon#read 3, iclass 32, count 0 2006.173.15:43:38.54#ibcon#about to read 4, iclass 32, count 0 2006.173.15:43:38.54#ibcon#read 4, iclass 32, count 0 2006.173.15:43:38.54#ibcon#about to read 5, iclass 32, count 0 2006.173.15:43:38.54#ibcon#read 5, iclass 32, count 0 2006.173.15:43:38.54#ibcon#about to read 6, iclass 32, count 0 2006.173.15:43:38.54#ibcon#read 6, iclass 32, count 0 2006.173.15:43:38.54#ibcon#end of sib2, iclass 32, count 0 2006.173.15:43:38.54#ibcon#*after write, iclass 32, count 0 2006.173.15:43:38.54#ibcon#*before return 0, iclass 32, count 0 2006.173.15:43:38.54#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.15:43:38.54#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.15:43:38.54#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.15:43:38.54#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.15:43:38.54$vck44/vbbw=wide 2006.173.15:43:38.54#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.15:43:38.54#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.15:43:38.54#ibcon#ireg 8 cls_cnt 0 2006.173.15:43:38.54#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.15:43:38.56#abcon#[5=S1D000X0/0*\r\n] 2006.173.15:43:38.61#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.15:43:38.61#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.15:43:38.61#ibcon#enter wrdev, iclass 34, count 0 2006.173.15:43:38.61#ibcon#first serial, iclass 34, count 0 2006.173.15:43:38.61#ibcon#enter sib2, iclass 34, count 0 2006.173.15:43:38.61#ibcon#flushed, iclass 34, count 0 2006.173.15:43:38.61#ibcon#about to write, iclass 34, count 0 2006.173.15:43:38.61#ibcon#wrote, iclass 34, count 0 2006.173.15:43:38.61#ibcon#about to read 3, iclass 34, count 0 2006.173.15:43:38.63#ibcon#read 3, iclass 34, count 0 2006.173.15:43:38.63#ibcon#about to read 4, iclass 34, count 0 2006.173.15:43:38.63#ibcon#read 4, iclass 34, count 0 2006.173.15:43:38.63#ibcon#about to read 5, iclass 34, count 0 2006.173.15:43:38.63#ibcon#read 5, iclass 34, count 0 2006.173.15:43:38.63#ibcon#about to read 6, iclass 34, count 0 2006.173.15:43:38.63#ibcon#read 6, iclass 34, count 0 2006.173.15:43:38.63#ibcon#end of sib2, iclass 34, count 0 2006.173.15:43:38.63#ibcon#*mode == 0, iclass 34, count 0 2006.173.15:43:38.63#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.15:43:38.63#ibcon#[27=BW32\r\n] 2006.173.15:43:38.63#ibcon#*before write, iclass 34, count 0 2006.173.15:43:38.63#ibcon#enter sib2, iclass 34, count 0 2006.173.15:43:38.63#ibcon#flushed, iclass 34, count 0 2006.173.15:43:38.63#ibcon#about to write, iclass 34, count 0 2006.173.15:43:38.63#ibcon#wrote, iclass 34, count 0 2006.173.15:43:38.63#ibcon#about to read 3, iclass 34, count 0 2006.173.15:43:38.66#ibcon#read 3, iclass 34, count 0 2006.173.15:43:38.66#ibcon#about to read 4, iclass 34, count 0 2006.173.15:43:38.66#ibcon#read 4, iclass 34, count 0 2006.173.15:43:38.66#ibcon#about to read 5, iclass 34, count 0 2006.173.15:43:38.66#ibcon#read 5, iclass 34, count 0 2006.173.15:43:38.66#ibcon#about to read 6, iclass 34, count 0 2006.173.15:43:38.66#ibcon#read 6, iclass 34, count 0 2006.173.15:43:38.66#ibcon#end of sib2, iclass 34, count 0 2006.173.15:43:38.66#ibcon#*after write, iclass 34, count 0 2006.173.15:43:38.66#ibcon#*before return 0, iclass 34, count 0 2006.173.15:43:38.66#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.15:43:38.66#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.15:43:38.66#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.15:43:38.66#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.15:43:38.66$setupk4/ifdk4 2006.173.15:43:38.66$ifdk4/lo= 2006.173.15:43:38.66$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.15:43:38.66$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.15:43:38.66$ifdk4/patch= 2006.173.15:43:38.66$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.15:43:38.66$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.15:43:38.66$setupk4/!*+20s 2006.173.15:43:47.13#trakl#Source acquired 2006.173.15:43:47.13#flagr#flagr/antenna,acquired 2006.173.15:43:48.65#abcon#<5=/15 1.1 2.3 20.901001003.0\r\n> 2006.173.15:43:48.67#abcon#{5=INTERFACE CLEAR} 2006.173.15:43:48.73#abcon#[5=S1D000X0/0*\r\n] 2006.173.15:43:53.17$setupk4/"tpicd 2006.173.15:43:53.17$setupk4/echo=off 2006.173.15:43:53.17$setupk4/xlog=off 2006.173.15:43:53.17:!2006.173.15:47:08 2006.173.15:47:08.00:preob 2006.173.15:47:09.14/onsource/TRACKING 2006.173.15:47:09.14:!2006.173.15:47:18 2006.173.15:47:18.00:"tape 2006.173.15:47:18.00:"st=record 2006.173.15:47:18.00:data_valid=on 2006.173.15:47:18.00:midob 2006.173.15:47:18.14/onsource/TRACKING 2006.173.15:47:18.14/wx/20.86,1003.0,100 2006.173.15:47:18.24/cable/+6.5112E-03 2006.173.15:47:19.33/va/01,07,usb,yes,37,39 2006.173.15:47:19.33/va/02,06,usb,yes,36,37 2006.173.15:47:19.33/va/03,05,usb,yes,46,48 2006.173.15:47:19.33/va/04,06,usb,yes,37,39 2006.173.15:47:19.33/va/05,04,usb,yes,29,30 2006.173.15:47:19.33/va/06,03,usb,yes,41,41 2006.173.15:47:19.33/va/07,04,usb,yes,33,34 2006.173.15:47:19.33/va/08,04,usb,yes,28,34 2006.173.15:47:19.56/valo/01,524.99,yes,locked 2006.173.15:47:19.56/valo/02,534.99,yes,locked 2006.173.15:47:19.56/valo/03,564.99,yes,locked 2006.173.15:47:19.56/valo/04,624.99,yes,locked 2006.173.15:47:19.56/valo/05,734.99,yes,locked 2006.173.15:47:19.56/valo/06,814.99,yes,locked 2006.173.15:47:19.56/valo/07,864.99,yes,locked 2006.173.15:47:19.56/valo/08,884.99,yes,locked 2006.173.15:47:20.65/vb/01,04,usb,yes,30,27 2006.173.15:47:20.65/vb/02,04,usb,yes,32,32 2006.173.15:47:20.65/vb/03,04,usb,yes,29,32 2006.173.15:47:20.65/vb/04,04,usb,yes,33,32 2006.173.15:47:20.65/vb/05,04,usb,yes,26,28 2006.173.15:47:20.65/vb/06,04,usb,yes,30,26 2006.173.15:47:20.65/vb/07,04,usb,yes,30,30 2006.173.15:47:20.65/vb/08,04,usb,yes,27,31 2006.173.15:47:20.88/vblo/01,629.99,yes,locked 2006.173.15:47:20.88/vblo/02,634.99,yes,locked 2006.173.15:47:20.88/vblo/03,649.99,yes,locked 2006.173.15:47:20.88/vblo/04,679.99,yes,locked 2006.173.15:47:20.88/vblo/05,709.99,yes,locked 2006.173.15:47:20.88/vblo/06,719.99,yes,locked 2006.173.15:47:20.88/vblo/07,734.99,yes,locked 2006.173.15:47:20.88/vblo/08,744.99,yes,locked 2006.173.15:47:21.03/vabw/8 2006.173.15:47:21.18/vbbw/8 2006.173.15:47:21.27/xfe/off,on,14.7 2006.173.15:47:21.64/ifatt/23,28,28,28 2006.173.15:47:22.07/fmout-gps/S +4.00E-07 2006.173.15:47:22.11:!2006.173.15:50:28 2006.173.15:50:28.00:data_valid=off 2006.173.15:50:28.00:"et 2006.173.15:50:28.00:!+3s 2006.173.15:50:31.01:"tape 2006.173.15:50:31.01:postob 2006.173.15:50:31.08/cable/+6.5099E-03 2006.173.15:50:31.08/wx/20.82,1003.1,100 2006.173.15:50:32.08/fmout-gps/S +3.99E-07 2006.173.15:50:32.08:scan_name=173-1553,jd0606,40 2006.173.15:50:32.08:source=1741-038,174358.86,-035004.6,2000.0,cw 2006.173.15:50:33.14#flagr#flagr/antenna,new-source 2006.173.15:50:33.14:checkk5 2006.173.15:50:33.52/chk_autoobs//k5ts1/ autoobs is running! 2006.173.15:50:33.91/chk_autoobs//k5ts2/ autoobs is running! 2006.173.15:50:34.34/chk_autoobs//k5ts3/ autoobs is running! 2006.173.15:50:34.73/chk_autoobs//k5ts4/ autoobs is running! 2006.173.15:50:35.13/chk_obsdata//k5ts1/T1731547??a.dat file size is correct (nominal:760MB, actual:756MB). 2006.173.15:50:35.54/chk_obsdata//k5ts2/T1731547??b.dat file size is correct (nominal:760MB, actual:756MB). 2006.173.15:50:35.93/chk_obsdata//k5ts3/T1731547??c.dat file size is correct (nominal:760MB, actual:756MB). 2006.173.15:50:36.34/chk_obsdata//k5ts4/T1731547??d.dat file size is correct (nominal:760MB, actual:756MB). 2006.173.15:50:37.07/k5log//k5ts1_log_newline 2006.173.15:50:37.78/k5log//k5ts2_log_newline 2006.173.15:50:38.50/k5log//k5ts3_log_newline 2006.173.15:50:39.21/k5log//k5ts4_log_newline 2006.173.15:50:39.23/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.15:50:39.23:setupk4=1 2006.173.15:50:39.23$setupk4/echo=on 2006.173.15:50:39.23$setupk4/pcalon 2006.173.15:50:39.23$pcalon/"no phase cal control is implemented here 2006.173.15:50:39.23$setupk4/"tpicd=stop 2006.173.15:50:39.23$setupk4/"rec=synch_on 2006.173.15:50:39.23$setupk4/"rec_mode=128 2006.173.15:50:39.23$setupk4/!* 2006.173.15:50:39.23$setupk4/recpk4 2006.173.15:50:39.23$recpk4/recpatch= 2006.173.15:50:39.24$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.15:50:39.24$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.15:50:39.24$setupk4/vck44 2006.173.15:50:39.24$vck44/valo=1,524.99 2006.173.15:50:39.24#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.15:50:39.24#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.15:50:39.24#ibcon#ireg 17 cls_cnt 0 2006.173.15:50:39.24#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.15:50:39.24#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.15:50:39.24#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.15:50:39.24#ibcon#enter wrdev, iclass 24, count 0 2006.173.15:50:39.24#ibcon#first serial, iclass 24, count 0 2006.173.15:50:39.24#ibcon#enter sib2, iclass 24, count 0 2006.173.15:50:39.24#ibcon#flushed, iclass 24, count 0 2006.173.15:50:39.24#ibcon#about to write, iclass 24, count 0 2006.173.15:50:39.24#ibcon#wrote, iclass 24, count 0 2006.173.15:50:39.24#ibcon#about to read 3, iclass 24, count 0 2006.173.15:50:39.26#ibcon#read 3, iclass 24, count 0 2006.173.15:50:39.26#ibcon#about to read 4, iclass 24, count 0 2006.173.15:50:39.26#ibcon#read 4, iclass 24, count 0 2006.173.15:50:39.26#ibcon#about to read 5, iclass 24, count 0 2006.173.15:50:39.26#ibcon#read 5, iclass 24, count 0 2006.173.15:50:39.26#ibcon#about to read 6, iclass 24, count 0 2006.173.15:50:39.26#ibcon#read 6, iclass 24, count 0 2006.173.15:50:39.26#ibcon#end of sib2, iclass 24, count 0 2006.173.15:50:39.26#ibcon#*mode == 0, iclass 24, count 0 2006.173.15:50:39.26#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.15:50:39.26#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.15:50:39.26#ibcon#*before write, iclass 24, count 0 2006.173.15:50:39.26#ibcon#enter sib2, iclass 24, count 0 2006.173.15:50:39.26#ibcon#flushed, iclass 24, count 0 2006.173.15:50:39.26#ibcon#about to write, iclass 24, count 0 2006.173.15:50:39.26#ibcon#wrote, iclass 24, count 0 2006.173.15:50:39.26#ibcon#about to read 3, iclass 24, count 0 2006.173.15:50:39.31#ibcon#read 3, iclass 24, count 0 2006.173.15:50:39.31#ibcon#about to read 4, iclass 24, count 0 2006.173.15:50:39.31#ibcon#read 4, iclass 24, count 0 2006.173.15:50:39.31#ibcon#about to read 5, iclass 24, count 0 2006.173.15:50:39.31#ibcon#read 5, iclass 24, count 0 2006.173.15:50:39.31#ibcon#about to read 6, iclass 24, count 0 2006.173.15:50:39.31#ibcon#read 6, iclass 24, count 0 2006.173.15:50:39.31#ibcon#end of sib2, iclass 24, count 0 2006.173.15:50:39.31#ibcon#*after write, iclass 24, count 0 2006.173.15:50:39.31#ibcon#*before return 0, iclass 24, count 0 2006.173.15:50:39.31#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.15:50:39.31#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.15:50:39.31#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.15:50:39.31#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.15:50:39.31$vck44/va=1,7 2006.173.15:50:39.31#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.15:50:39.31#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.15:50:39.31#ibcon#ireg 11 cls_cnt 2 2006.173.15:50:39.31#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.15:50:39.31#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.15:50:39.31#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.15:50:39.31#ibcon#enter wrdev, iclass 26, count 2 2006.173.15:50:39.31#ibcon#first serial, iclass 26, count 2 2006.173.15:50:39.31#ibcon#enter sib2, iclass 26, count 2 2006.173.15:50:39.31#ibcon#flushed, iclass 26, count 2 2006.173.15:50:39.31#ibcon#about to write, iclass 26, count 2 2006.173.15:50:39.31#ibcon#wrote, iclass 26, count 2 2006.173.15:50:39.31#ibcon#about to read 3, iclass 26, count 2 2006.173.15:50:39.33#ibcon#read 3, iclass 26, count 2 2006.173.15:50:39.33#ibcon#about to read 4, iclass 26, count 2 2006.173.15:50:39.33#ibcon#read 4, iclass 26, count 2 2006.173.15:50:39.33#ibcon#about to read 5, iclass 26, count 2 2006.173.15:50:39.33#ibcon#read 5, iclass 26, count 2 2006.173.15:50:39.33#ibcon#about to read 6, iclass 26, count 2 2006.173.15:50:39.33#ibcon#read 6, iclass 26, count 2 2006.173.15:50:39.33#ibcon#end of sib2, iclass 26, count 2 2006.173.15:50:39.33#ibcon#*mode == 0, iclass 26, count 2 2006.173.15:50:39.33#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.15:50:39.33#ibcon#[25=AT01-07\r\n] 2006.173.15:50:39.33#ibcon#*before write, iclass 26, count 2 2006.173.15:50:39.33#ibcon#enter sib2, iclass 26, count 2 2006.173.15:50:39.33#ibcon#flushed, iclass 26, count 2 2006.173.15:50:39.33#ibcon#about to write, iclass 26, count 2 2006.173.15:50:39.33#ibcon#wrote, iclass 26, count 2 2006.173.15:50:39.33#ibcon#about to read 3, iclass 26, count 2 2006.173.15:50:39.36#ibcon#read 3, iclass 26, count 2 2006.173.15:50:39.36#ibcon#about to read 4, iclass 26, count 2 2006.173.15:50:39.36#ibcon#read 4, iclass 26, count 2 2006.173.15:50:39.36#ibcon#about to read 5, iclass 26, count 2 2006.173.15:50:39.36#ibcon#read 5, iclass 26, count 2 2006.173.15:50:39.36#ibcon#about to read 6, iclass 26, count 2 2006.173.15:50:39.36#ibcon#read 6, iclass 26, count 2 2006.173.15:50:39.36#ibcon#end of sib2, iclass 26, count 2 2006.173.15:50:39.36#ibcon#*after write, iclass 26, count 2 2006.173.15:50:39.36#ibcon#*before return 0, iclass 26, count 2 2006.173.15:50:39.36#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.15:50:39.36#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.15:50:39.36#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.15:50:39.36#ibcon#ireg 7 cls_cnt 0 2006.173.15:50:39.36#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.15:50:39.48#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.15:50:39.48#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.15:50:39.48#ibcon#enter wrdev, iclass 26, count 0 2006.173.15:50:39.48#ibcon#first serial, iclass 26, count 0 2006.173.15:50:39.48#ibcon#enter sib2, iclass 26, count 0 2006.173.15:50:39.48#ibcon#flushed, iclass 26, count 0 2006.173.15:50:39.48#ibcon#about to write, iclass 26, count 0 2006.173.15:50:39.48#ibcon#wrote, iclass 26, count 0 2006.173.15:50:39.48#ibcon#about to read 3, iclass 26, count 0 2006.173.15:50:39.50#ibcon#read 3, iclass 26, count 0 2006.173.15:50:39.50#ibcon#about to read 4, iclass 26, count 0 2006.173.15:50:39.50#ibcon#read 4, iclass 26, count 0 2006.173.15:50:39.50#ibcon#about to read 5, iclass 26, count 0 2006.173.15:50:39.50#ibcon#read 5, iclass 26, count 0 2006.173.15:50:39.50#ibcon#about to read 6, iclass 26, count 0 2006.173.15:50:39.50#ibcon#read 6, iclass 26, count 0 2006.173.15:50:39.50#ibcon#end of sib2, iclass 26, count 0 2006.173.15:50:39.50#ibcon#*mode == 0, iclass 26, count 0 2006.173.15:50:39.50#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.15:50:39.50#ibcon#[25=USB\r\n] 2006.173.15:50:39.50#ibcon#*before write, iclass 26, count 0 2006.173.15:50:39.50#ibcon#enter sib2, iclass 26, count 0 2006.173.15:50:39.50#ibcon#flushed, iclass 26, count 0 2006.173.15:50:39.50#ibcon#about to write, iclass 26, count 0 2006.173.15:50:39.50#ibcon#wrote, iclass 26, count 0 2006.173.15:50:39.50#ibcon#about to read 3, iclass 26, count 0 2006.173.15:50:39.53#ibcon#read 3, iclass 26, count 0 2006.173.15:50:39.53#ibcon#about to read 4, iclass 26, count 0 2006.173.15:50:39.53#ibcon#read 4, iclass 26, count 0 2006.173.15:50:39.53#ibcon#about to read 5, iclass 26, count 0 2006.173.15:50:39.53#ibcon#read 5, iclass 26, count 0 2006.173.15:50:39.53#ibcon#about to read 6, iclass 26, count 0 2006.173.15:50:39.53#ibcon#read 6, iclass 26, count 0 2006.173.15:50:39.53#ibcon#end of sib2, iclass 26, count 0 2006.173.15:50:39.53#ibcon#*after write, iclass 26, count 0 2006.173.15:50:39.53#ibcon#*before return 0, iclass 26, count 0 2006.173.15:50:39.53#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.15:50:39.53#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.15:50:39.53#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.15:50:39.53#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.15:50:39.53$vck44/valo=2,534.99 2006.173.15:50:39.53#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.15:50:39.53#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.15:50:39.53#ibcon#ireg 17 cls_cnt 0 2006.173.15:50:39.53#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.15:50:39.53#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.15:50:39.53#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.15:50:39.53#ibcon#enter wrdev, iclass 28, count 0 2006.173.15:50:39.53#ibcon#first serial, iclass 28, count 0 2006.173.15:50:39.53#ibcon#enter sib2, iclass 28, count 0 2006.173.15:50:39.53#ibcon#flushed, iclass 28, count 0 2006.173.15:50:39.53#ibcon#about to write, iclass 28, count 0 2006.173.15:50:39.53#ibcon#wrote, iclass 28, count 0 2006.173.15:50:39.53#ibcon#about to read 3, iclass 28, count 0 2006.173.15:50:39.55#ibcon#read 3, iclass 28, count 0 2006.173.15:50:39.55#ibcon#about to read 4, iclass 28, count 0 2006.173.15:50:39.55#ibcon#read 4, iclass 28, count 0 2006.173.15:50:39.55#ibcon#about to read 5, iclass 28, count 0 2006.173.15:50:39.55#ibcon#read 5, iclass 28, count 0 2006.173.15:50:39.55#ibcon#about to read 6, iclass 28, count 0 2006.173.15:50:39.55#ibcon#read 6, iclass 28, count 0 2006.173.15:50:39.55#ibcon#end of sib2, iclass 28, count 0 2006.173.15:50:39.55#ibcon#*mode == 0, iclass 28, count 0 2006.173.15:50:39.55#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.15:50:39.55#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.15:50:39.55#ibcon#*before write, iclass 28, count 0 2006.173.15:50:39.55#ibcon#enter sib2, iclass 28, count 0 2006.173.15:50:39.55#ibcon#flushed, iclass 28, count 0 2006.173.15:50:39.55#ibcon#about to write, iclass 28, count 0 2006.173.15:50:39.55#ibcon#wrote, iclass 28, count 0 2006.173.15:50:39.55#ibcon#about to read 3, iclass 28, count 0 2006.173.15:50:39.59#ibcon#read 3, iclass 28, count 0 2006.173.15:50:39.59#ibcon#about to read 4, iclass 28, count 0 2006.173.15:50:39.59#ibcon#read 4, iclass 28, count 0 2006.173.15:50:39.59#ibcon#about to read 5, iclass 28, count 0 2006.173.15:50:39.59#ibcon#read 5, iclass 28, count 0 2006.173.15:50:39.59#ibcon#about to read 6, iclass 28, count 0 2006.173.15:50:39.59#ibcon#read 6, iclass 28, count 0 2006.173.15:50:39.59#ibcon#end of sib2, iclass 28, count 0 2006.173.15:50:39.59#ibcon#*after write, iclass 28, count 0 2006.173.15:50:39.59#ibcon#*before return 0, iclass 28, count 0 2006.173.15:50:39.59#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.15:50:39.59#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.15:50:39.59#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.15:50:39.59#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.15:50:39.59$vck44/va=2,6 2006.173.15:50:39.59#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.15:50:39.59#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.15:50:39.59#ibcon#ireg 11 cls_cnt 2 2006.173.15:50:39.59#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.15:50:39.65#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.15:50:39.65#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.15:50:39.65#ibcon#enter wrdev, iclass 30, count 2 2006.173.15:50:39.65#ibcon#first serial, iclass 30, count 2 2006.173.15:50:39.65#ibcon#enter sib2, iclass 30, count 2 2006.173.15:50:39.65#ibcon#flushed, iclass 30, count 2 2006.173.15:50:39.65#ibcon#about to write, iclass 30, count 2 2006.173.15:50:39.65#ibcon#wrote, iclass 30, count 2 2006.173.15:50:39.65#ibcon#about to read 3, iclass 30, count 2 2006.173.15:50:39.67#ibcon#read 3, iclass 30, count 2 2006.173.15:50:39.67#ibcon#about to read 4, iclass 30, count 2 2006.173.15:50:39.67#ibcon#read 4, iclass 30, count 2 2006.173.15:50:39.67#ibcon#about to read 5, iclass 30, count 2 2006.173.15:50:39.67#ibcon#read 5, iclass 30, count 2 2006.173.15:50:39.67#ibcon#about to read 6, iclass 30, count 2 2006.173.15:50:39.67#ibcon#read 6, iclass 30, count 2 2006.173.15:50:39.67#ibcon#end of sib2, iclass 30, count 2 2006.173.15:50:39.67#ibcon#*mode == 0, iclass 30, count 2 2006.173.15:50:39.67#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.15:50:39.67#ibcon#[25=AT02-06\r\n] 2006.173.15:50:39.67#ibcon#*before write, iclass 30, count 2 2006.173.15:50:39.67#ibcon#enter sib2, iclass 30, count 2 2006.173.15:50:39.67#ibcon#flushed, iclass 30, count 2 2006.173.15:50:39.67#ibcon#about to write, iclass 30, count 2 2006.173.15:50:39.67#ibcon#wrote, iclass 30, count 2 2006.173.15:50:39.67#ibcon#about to read 3, iclass 30, count 2 2006.173.15:50:39.70#ibcon#read 3, iclass 30, count 2 2006.173.15:50:39.70#ibcon#about to read 4, iclass 30, count 2 2006.173.15:50:39.70#ibcon#read 4, iclass 30, count 2 2006.173.15:50:39.70#ibcon#about to read 5, iclass 30, count 2 2006.173.15:50:39.70#ibcon#read 5, iclass 30, count 2 2006.173.15:50:39.70#ibcon#about to read 6, iclass 30, count 2 2006.173.15:50:39.70#ibcon#read 6, iclass 30, count 2 2006.173.15:50:39.70#ibcon#end of sib2, iclass 30, count 2 2006.173.15:50:39.70#ibcon#*after write, iclass 30, count 2 2006.173.15:50:39.70#ibcon#*before return 0, iclass 30, count 2 2006.173.15:50:39.70#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.15:50:39.70#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.15:50:39.70#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.15:50:39.70#ibcon#ireg 7 cls_cnt 0 2006.173.15:50:39.70#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.15:50:39.82#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.15:50:39.82#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.15:50:39.82#ibcon#enter wrdev, iclass 30, count 0 2006.173.15:50:39.82#ibcon#first serial, iclass 30, count 0 2006.173.15:50:39.82#ibcon#enter sib2, iclass 30, count 0 2006.173.15:50:39.82#ibcon#flushed, iclass 30, count 0 2006.173.15:50:39.82#ibcon#about to write, iclass 30, count 0 2006.173.15:50:39.82#ibcon#wrote, iclass 30, count 0 2006.173.15:50:39.82#ibcon#about to read 3, iclass 30, count 0 2006.173.15:50:39.84#ibcon#read 3, iclass 30, count 0 2006.173.15:50:39.84#ibcon#about to read 4, iclass 30, count 0 2006.173.15:50:39.84#ibcon#read 4, iclass 30, count 0 2006.173.15:50:39.84#ibcon#about to read 5, iclass 30, count 0 2006.173.15:50:39.84#ibcon#read 5, iclass 30, count 0 2006.173.15:50:39.84#ibcon#about to read 6, iclass 30, count 0 2006.173.15:50:39.84#ibcon#read 6, iclass 30, count 0 2006.173.15:50:39.84#ibcon#end of sib2, iclass 30, count 0 2006.173.15:50:39.84#ibcon#*mode == 0, iclass 30, count 0 2006.173.15:50:39.84#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.15:50:39.84#ibcon#[25=USB\r\n] 2006.173.15:50:39.84#ibcon#*before write, iclass 30, count 0 2006.173.15:50:39.84#ibcon#enter sib2, iclass 30, count 0 2006.173.15:50:39.84#ibcon#flushed, iclass 30, count 0 2006.173.15:50:39.84#ibcon#about to write, iclass 30, count 0 2006.173.15:50:39.84#ibcon#wrote, iclass 30, count 0 2006.173.15:50:39.84#ibcon#about to read 3, iclass 30, count 0 2006.173.15:50:39.87#ibcon#read 3, iclass 30, count 0 2006.173.15:50:39.87#ibcon#about to read 4, iclass 30, count 0 2006.173.15:50:39.87#ibcon#read 4, iclass 30, count 0 2006.173.15:50:39.87#ibcon#about to read 5, iclass 30, count 0 2006.173.15:50:39.87#ibcon#read 5, iclass 30, count 0 2006.173.15:50:39.87#ibcon#about to read 6, iclass 30, count 0 2006.173.15:50:39.87#ibcon#read 6, iclass 30, count 0 2006.173.15:50:39.87#ibcon#end of sib2, iclass 30, count 0 2006.173.15:50:39.87#ibcon#*after write, iclass 30, count 0 2006.173.15:50:39.87#ibcon#*before return 0, iclass 30, count 0 2006.173.15:50:39.87#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.15:50:39.87#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.15:50:39.87#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.15:50:39.87#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.15:50:39.87$vck44/valo=3,564.99 2006.173.15:50:39.87#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.15:50:39.87#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.15:50:39.87#ibcon#ireg 17 cls_cnt 0 2006.173.15:50:39.87#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.15:50:39.87#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.15:50:39.87#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.15:50:39.87#ibcon#enter wrdev, iclass 32, count 0 2006.173.15:50:39.87#ibcon#first serial, iclass 32, count 0 2006.173.15:50:39.87#ibcon#enter sib2, iclass 32, count 0 2006.173.15:50:39.87#ibcon#flushed, iclass 32, count 0 2006.173.15:50:39.87#ibcon#about to write, iclass 32, count 0 2006.173.15:50:39.87#ibcon#wrote, iclass 32, count 0 2006.173.15:50:39.87#ibcon#about to read 3, iclass 32, count 0 2006.173.15:50:39.89#ibcon#read 3, iclass 32, count 0 2006.173.15:50:39.89#ibcon#about to read 4, iclass 32, count 0 2006.173.15:50:39.89#ibcon#read 4, iclass 32, count 0 2006.173.15:50:39.89#ibcon#about to read 5, iclass 32, count 0 2006.173.15:50:39.89#ibcon#read 5, iclass 32, count 0 2006.173.15:50:39.89#ibcon#about to read 6, iclass 32, count 0 2006.173.15:50:39.89#ibcon#read 6, iclass 32, count 0 2006.173.15:50:39.89#ibcon#end of sib2, iclass 32, count 0 2006.173.15:50:39.89#ibcon#*mode == 0, iclass 32, count 0 2006.173.15:50:39.89#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.15:50:39.89#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.15:50:39.89#ibcon#*before write, iclass 32, count 0 2006.173.15:50:39.89#ibcon#enter sib2, iclass 32, count 0 2006.173.15:50:39.89#ibcon#flushed, iclass 32, count 0 2006.173.15:50:39.89#ibcon#about to write, iclass 32, count 0 2006.173.15:50:39.89#ibcon#wrote, iclass 32, count 0 2006.173.15:50:39.89#ibcon#about to read 3, iclass 32, count 0 2006.173.15:50:39.93#ibcon#read 3, iclass 32, count 0 2006.173.15:50:39.93#ibcon#about to read 4, iclass 32, count 0 2006.173.15:50:39.93#ibcon#read 4, iclass 32, count 0 2006.173.15:50:39.93#ibcon#about to read 5, iclass 32, count 0 2006.173.15:50:39.93#ibcon#read 5, iclass 32, count 0 2006.173.15:50:39.93#ibcon#about to read 6, iclass 32, count 0 2006.173.15:50:39.93#ibcon#read 6, iclass 32, count 0 2006.173.15:50:39.93#ibcon#end of sib2, iclass 32, count 0 2006.173.15:50:39.93#ibcon#*after write, iclass 32, count 0 2006.173.15:50:39.93#ibcon#*before return 0, iclass 32, count 0 2006.173.15:50:39.93#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.15:50:39.93#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.15:50:39.93#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.15:50:39.93#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.15:50:39.93$vck44/va=3,5 2006.173.15:50:39.93#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.15:50:39.93#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.15:50:39.93#ibcon#ireg 11 cls_cnt 2 2006.173.15:50:39.93#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.15:50:39.99#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.15:50:39.99#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.15:50:39.99#ibcon#enter wrdev, iclass 34, count 2 2006.173.15:50:39.99#ibcon#first serial, iclass 34, count 2 2006.173.15:50:39.99#ibcon#enter sib2, iclass 34, count 2 2006.173.15:50:39.99#ibcon#flushed, iclass 34, count 2 2006.173.15:50:39.99#ibcon#about to write, iclass 34, count 2 2006.173.15:50:39.99#ibcon#wrote, iclass 34, count 2 2006.173.15:50:39.99#ibcon#about to read 3, iclass 34, count 2 2006.173.15:50:40.01#ibcon#read 3, iclass 34, count 2 2006.173.15:50:40.01#ibcon#about to read 4, iclass 34, count 2 2006.173.15:50:40.01#ibcon#read 4, iclass 34, count 2 2006.173.15:50:40.01#ibcon#about to read 5, iclass 34, count 2 2006.173.15:50:40.01#ibcon#read 5, iclass 34, count 2 2006.173.15:50:40.01#ibcon#about to read 6, iclass 34, count 2 2006.173.15:50:40.01#ibcon#read 6, iclass 34, count 2 2006.173.15:50:40.01#ibcon#end of sib2, iclass 34, count 2 2006.173.15:50:40.01#ibcon#*mode == 0, iclass 34, count 2 2006.173.15:50:40.01#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.15:50:40.01#ibcon#[25=AT03-05\r\n] 2006.173.15:50:40.01#ibcon#*before write, iclass 34, count 2 2006.173.15:50:40.01#ibcon#enter sib2, iclass 34, count 2 2006.173.15:50:40.01#ibcon#flushed, iclass 34, count 2 2006.173.15:50:40.01#ibcon#about to write, iclass 34, count 2 2006.173.15:50:40.01#ibcon#wrote, iclass 34, count 2 2006.173.15:50:40.01#ibcon#about to read 3, iclass 34, count 2 2006.173.15:50:40.04#ibcon#read 3, iclass 34, count 2 2006.173.15:50:40.04#ibcon#about to read 4, iclass 34, count 2 2006.173.15:50:40.04#ibcon#read 4, iclass 34, count 2 2006.173.15:50:40.04#ibcon#about to read 5, iclass 34, count 2 2006.173.15:50:40.04#ibcon#read 5, iclass 34, count 2 2006.173.15:50:40.04#ibcon#about to read 6, iclass 34, count 2 2006.173.15:50:40.04#ibcon#read 6, iclass 34, count 2 2006.173.15:50:40.04#ibcon#end of sib2, iclass 34, count 2 2006.173.15:50:40.04#ibcon#*after write, iclass 34, count 2 2006.173.15:50:40.04#ibcon#*before return 0, iclass 34, count 2 2006.173.15:50:40.04#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.15:50:40.04#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.15:50:40.04#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.15:50:40.04#ibcon#ireg 7 cls_cnt 0 2006.173.15:50:40.04#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.15:50:40.16#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.15:50:40.16#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.15:50:40.16#ibcon#enter wrdev, iclass 34, count 0 2006.173.15:50:40.16#ibcon#first serial, iclass 34, count 0 2006.173.15:50:40.16#ibcon#enter sib2, iclass 34, count 0 2006.173.15:50:40.16#ibcon#flushed, iclass 34, count 0 2006.173.15:50:40.16#ibcon#about to write, iclass 34, count 0 2006.173.15:50:40.16#ibcon#wrote, iclass 34, count 0 2006.173.15:50:40.16#ibcon#about to read 3, iclass 34, count 0 2006.173.15:50:40.18#ibcon#read 3, iclass 34, count 0 2006.173.15:50:40.18#ibcon#about to read 4, iclass 34, count 0 2006.173.15:50:40.18#ibcon#read 4, iclass 34, count 0 2006.173.15:50:40.18#ibcon#about to read 5, iclass 34, count 0 2006.173.15:50:40.18#ibcon#read 5, iclass 34, count 0 2006.173.15:50:40.18#ibcon#about to read 6, iclass 34, count 0 2006.173.15:50:40.18#ibcon#read 6, iclass 34, count 0 2006.173.15:50:40.18#ibcon#end of sib2, iclass 34, count 0 2006.173.15:50:40.18#ibcon#*mode == 0, iclass 34, count 0 2006.173.15:50:40.18#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.15:50:40.18#ibcon#[25=USB\r\n] 2006.173.15:50:40.18#ibcon#*before write, iclass 34, count 0 2006.173.15:50:40.18#ibcon#enter sib2, iclass 34, count 0 2006.173.15:50:40.18#ibcon#flushed, iclass 34, count 0 2006.173.15:50:40.18#ibcon#about to write, iclass 34, count 0 2006.173.15:50:40.18#ibcon#wrote, iclass 34, count 0 2006.173.15:50:40.18#ibcon#about to read 3, iclass 34, count 0 2006.173.15:50:40.21#ibcon#read 3, iclass 34, count 0 2006.173.15:50:40.21#ibcon#about to read 4, iclass 34, count 0 2006.173.15:50:40.21#ibcon#read 4, iclass 34, count 0 2006.173.15:50:40.21#ibcon#about to read 5, iclass 34, count 0 2006.173.15:50:40.21#ibcon#read 5, iclass 34, count 0 2006.173.15:50:40.21#ibcon#about to read 6, iclass 34, count 0 2006.173.15:50:40.21#ibcon#read 6, iclass 34, count 0 2006.173.15:50:40.21#ibcon#end of sib2, iclass 34, count 0 2006.173.15:50:40.21#ibcon#*after write, iclass 34, count 0 2006.173.15:50:40.21#ibcon#*before return 0, iclass 34, count 0 2006.173.15:50:40.21#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.15:50:40.21#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.15:50:40.21#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.15:50:40.21#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.15:50:40.21$vck44/valo=4,624.99 2006.173.15:50:40.21#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.15:50:40.21#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.15:50:40.21#ibcon#ireg 17 cls_cnt 0 2006.173.15:50:40.21#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.15:50:40.21#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.15:50:40.21#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.15:50:40.21#ibcon#enter wrdev, iclass 36, count 0 2006.173.15:50:40.21#ibcon#first serial, iclass 36, count 0 2006.173.15:50:40.21#ibcon#enter sib2, iclass 36, count 0 2006.173.15:50:40.21#ibcon#flushed, iclass 36, count 0 2006.173.15:50:40.21#ibcon#about to write, iclass 36, count 0 2006.173.15:50:40.21#ibcon#wrote, iclass 36, count 0 2006.173.15:50:40.21#ibcon#about to read 3, iclass 36, count 0 2006.173.15:50:40.23#ibcon#read 3, iclass 36, count 0 2006.173.15:50:40.23#ibcon#about to read 4, iclass 36, count 0 2006.173.15:50:40.23#ibcon#read 4, iclass 36, count 0 2006.173.15:50:40.23#ibcon#about to read 5, iclass 36, count 0 2006.173.15:50:40.23#ibcon#read 5, iclass 36, count 0 2006.173.15:50:40.23#ibcon#about to read 6, iclass 36, count 0 2006.173.15:50:40.23#ibcon#read 6, iclass 36, count 0 2006.173.15:50:40.23#ibcon#end of sib2, iclass 36, count 0 2006.173.15:50:40.23#ibcon#*mode == 0, iclass 36, count 0 2006.173.15:50:40.23#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.15:50:40.23#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.15:50:40.23#ibcon#*before write, iclass 36, count 0 2006.173.15:50:40.23#ibcon#enter sib2, iclass 36, count 0 2006.173.15:50:40.23#ibcon#flushed, iclass 36, count 0 2006.173.15:50:40.23#ibcon#about to write, iclass 36, count 0 2006.173.15:50:40.23#ibcon#wrote, iclass 36, count 0 2006.173.15:50:40.23#ibcon#about to read 3, iclass 36, count 0 2006.173.15:50:40.27#ibcon#read 3, iclass 36, count 0 2006.173.15:50:40.27#ibcon#about to read 4, iclass 36, count 0 2006.173.15:50:40.27#ibcon#read 4, iclass 36, count 0 2006.173.15:50:40.27#ibcon#about to read 5, iclass 36, count 0 2006.173.15:50:40.27#ibcon#read 5, iclass 36, count 0 2006.173.15:50:40.27#ibcon#about to read 6, iclass 36, count 0 2006.173.15:50:40.27#ibcon#read 6, iclass 36, count 0 2006.173.15:50:40.27#ibcon#end of sib2, iclass 36, count 0 2006.173.15:50:40.27#ibcon#*after write, iclass 36, count 0 2006.173.15:50:40.27#ibcon#*before return 0, iclass 36, count 0 2006.173.15:50:40.27#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.15:50:40.27#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.15:50:40.27#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.15:50:40.27#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.15:50:40.27$vck44/va=4,6 2006.173.15:50:40.27#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.15:50:40.27#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.15:50:40.27#ibcon#ireg 11 cls_cnt 2 2006.173.15:50:40.27#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.15:50:40.33#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.15:50:40.33#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.15:50:40.33#ibcon#enter wrdev, iclass 38, count 2 2006.173.15:50:40.33#ibcon#first serial, iclass 38, count 2 2006.173.15:50:40.33#ibcon#enter sib2, iclass 38, count 2 2006.173.15:50:40.33#ibcon#flushed, iclass 38, count 2 2006.173.15:50:40.33#ibcon#about to write, iclass 38, count 2 2006.173.15:50:40.33#ibcon#wrote, iclass 38, count 2 2006.173.15:50:40.33#ibcon#about to read 3, iclass 38, count 2 2006.173.15:50:40.35#ibcon#read 3, iclass 38, count 2 2006.173.15:50:40.35#ibcon#about to read 4, iclass 38, count 2 2006.173.15:50:40.35#ibcon#read 4, iclass 38, count 2 2006.173.15:50:40.35#ibcon#about to read 5, iclass 38, count 2 2006.173.15:50:40.35#ibcon#read 5, iclass 38, count 2 2006.173.15:50:40.35#ibcon#about to read 6, iclass 38, count 2 2006.173.15:50:40.35#ibcon#read 6, iclass 38, count 2 2006.173.15:50:40.35#ibcon#end of sib2, iclass 38, count 2 2006.173.15:50:40.35#ibcon#*mode == 0, iclass 38, count 2 2006.173.15:50:40.35#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.15:50:40.35#ibcon#[25=AT04-06\r\n] 2006.173.15:50:40.35#ibcon#*before write, iclass 38, count 2 2006.173.15:50:40.35#ibcon#enter sib2, iclass 38, count 2 2006.173.15:50:40.35#ibcon#flushed, iclass 38, count 2 2006.173.15:50:40.35#ibcon#about to write, iclass 38, count 2 2006.173.15:50:40.35#ibcon#wrote, iclass 38, count 2 2006.173.15:50:40.35#ibcon#about to read 3, iclass 38, count 2 2006.173.15:50:40.38#ibcon#read 3, iclass 38, count 2 2006.173.15:50:40.38#ibcon#about to read 4, iclass 38, count 2 2006.173.15:50:40.38#ibcon#read 4, iclass 38, count 2 2006.173.15:50:40.38#ibcon#about to read 5, iclass 38, count 2 2006.173.15:50:40.38#ibcon#read 5, iclass 38, count 2 2006.173.15:50:40.38#ibcon#about to read 6, iclass 38, count 2 2006.173.15:50:40.38#ibcon#read 6, iclass 38, count 2 2006.173.15:50:40.38#ibcon#end of sib2, iclass 38, count 2 2006.173.15:50:40.38#ibcon#*after write, iclass 38, count 2 2006.173.15:50:40.38#ibcon#*before return 0, iclass 38, count 2 2006.173.15:50:40.38#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.15:50:40.38#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.15:50:40.38#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.15:50:40.38#ibcon#ireg 7 cls_cnt 0 2006.173.15:50:40.38#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.15:50:40.50#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.15:50:40.50#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.15:50:40.50#ibcon#enter wrdev, iclass 38, count 0 2006.173.15:50:40.50#ibcon#first serial, iclass 38, count 0 2006.173.15:50:40.50#ibcon#enter sib2, iclass 38, count 0 2006.173.15:50:40.50#ibcon#flushed, iclass 38, count 0 2006.173.15:50:40.50#ibcon#about to write, iclass 38, count 0 2006.173.15:50:40.50#ibcon#wrote, iclass 38, count 0 2006.173.15:50:40.50#ibcon#about to read 3, iclass 38, count 0 2006.173.15:50:40.52#ibcon#read 3, iclass 38, count 0 2006.173.15:50:40.52#ibcon#about to read 4, iclass 38, count 0 2006.173.15:50:40.52#ibcon#read 4, iclass 38, count 0 2006.173.15:50:40.52#ibcon#about to read 5, iclass 38, count 0 2006.173.15:50:40.52#ibcon#read 5, iclass 38, count 0 2006.173.15:50:40.52#ibcon#about to read 6, iclass 38, count 0 2006.173.15:50:40.52#ibcon#read 6, iclass 38, count 0 2006.173.15:50:40.52#ibcon#end of sib2, iclass 38, count 0 2006.173.15:50:40.52#ibcon#*mode == 0, iclass 38, count 0 2006.173.15:50:40.52#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.15:50:40.52#ibcon#[25=USB\r\n] 2006.173.15:50:40.52#ibcon#*before write, iclass 38, count 0 2006.173.15:50:40.52#ibcon#enter sib2, iclass 38, count 0 2006.173.15:50:40.52#ibcon#flushed, iclass 38, count 0 2006.173.15:50:40.52#ibcon#about to write, iclass 38, count 0 2006.173.15:50:40.52#ibcon#wrote, iclass 38, count 0 2006.173.15:50:40.52#ibcon#about to read 3, iclass 38, count 0 2006.173.15:50:40.55#ibcon#read 3, iclass 38, count 0 2006.173.15:50:40.55#ibcon#about to read 4, iclass 38, count 0 2006.173.15:50:40.55#ibcon#read 4, iclass 38, count 0 2006.173.15:50:40.55#ibcon#about to read 5, iclass 38, count 0 2006.173.15:50:40.55#ibcon#read 5, iclass 38, count 0 2006.173.15:50:40.55#ibcon#about to read 6, iclass 38, count 0 2006.173.15:50:40.55#ibcon#read 6, iclass 38, count 0 2006.173.15:50:40.55#ibcon#end of sib2, iclass 38, count 0 2006.173.15:50:40.55#ibcon#*after write, iclass 38, count 0 2006.173.15:50:40.55#ibcon#*before return 0, iclass 38, count 0 2006.173.15:50:40.55#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.15:50:40.55#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.15:50:40.55#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.15:50:40.55#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.15:50:40.55$vck44/valo=5,734.99 2006.173.15:50:40.55#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.15:50:40.55#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.15:50:40.55#ibcon#ireg 17 cls_cnt 0 2006.173.15:50:40.55#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.15:50:40.55#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.15:50:40.55#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.15:50:40.55#ibcon#enter wrdev, iclass 40, count 0 2006.173.15:50:40.55#ibcon#first serial, iclass 40, count 0 2006.173.15:50:40.55#ibcon#enter sib2, iclass 40, count 0 2006.173.15:50:40.55#ibcon#flushed, iclass 40, count 0 2006.173.15:50:40.55#ibcon#about to write, iclass 40, count 0 2006.173.15:50:40.55#ibcon#wrote, iclass 40, count 0 2006.173.15:50:40.55#ibcon#about to read 3, iclass 40, count 0 2006.173.15:50:40.57#ibcon#read 3, iclass 40, count 0 2006.173.15:50:40.57#ibcon#about to read 4, iclass 40, count 0 2006.173.15:50:40.57#ibcon#read 4, iclass 40, count 0 2006.173.15:50:40.57#ibcon#about to read 5, iclass 40, count 0 2006.173.15:50:40.57#ibcon#read 5, iclass 40, count 0 2006.173.15:50:40.57#ibcon#about to read 6, iclass 40, count 0 2006.173.15:50:40.57#ibcon#read 6, iclass 40, count 0 2006.173.15:50:40.57#ibcon#end of sib2, iclass 40, count 0 2006.173.15:50:40.57#ibcon#*mode == 0, iclass 40, count 0 2006.173.15:50:40.57#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.15:50:40.57#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.15:50:40.57#ibcon#*before write, iclass 40, count 0 2006.173.15:50:40.57#ibcon#enter sib2, iclass 40, count 0 2006.173.15:50:40.57#ibcon#flushed, iclass 40, count 0 2006.173.15:50:40.57#ibcon#about to write, iclass 40, count 0 2006.173.15:50:40.57#ibcon#wrote, iclass 40, count 0 2006.173.15:50:40.57#ibcon#about to read 3, iclass 40, count 0 2006.173.15:50:40.61#ibcon#read 3, iclass 40, count 0 2006.173.15:50:40.61#ibcon#about to read 4, iclass 40, count 0 2006.173.15:50:40.61#ibcon#read 4, iclass 40, count 0 2006.173.15:50:40.61#ibcon#about to read 5, iclass 40, count 0 2006.173.15:50:40.61#ibcon#read 5, iclass 40, count 0 2006.173.15:50:40.61#ibcon#about to read 6, iclass 40, count 0 2006.173.15:50:40.61#ibcon#read 6, iclass 40, count 0 2006.173.15:50:40.61#ibcon#end of sib2, iclass 40, count 0 2006.173.15:50:40.61#ibcon#*after write, iclass 40, count 0 2006.173.15:50:40.61#ibcon#*before return 0, iclass 40, count 0 2006.173.15:50:40.61#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.15:50:40.61#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.15:50:40.61#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.15:50:40.61#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.15:50:40.61$vck44/va=5,4 2006.173.15:50:40.61#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.15:50:40.61#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.15:50:40.61#ibcon#ireg 11 cls_cnt 2 2006.173.15:50:40.61#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.15:50:40.67#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.15:50:40.67#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.15:50:40.67#ibcon#enter wrdev, iclass 4, count 2 2006.173.15:50:40.67#ibcon#first serial, iclass 4, count 2 2006.173.15:50:40.67#ibcon#enter sib2, iclass 4, count 2 2006.173.15:50:40.67#ibcon#flushed, iclass 4, count 2 2006.173.15:50:40.67#ibcon#about to write, iclass 4, count 2 2006.173.15:50:40.67#ibcon#wrote, iclass 4, count 2 2006.173.15:50:40.67#ibcon#about to read 3, iclass 4, count 2 2006.173.15:50:40.69#ibcon#read 3, iclass 4, count 2 2006.173.15:50:40.69#ibcon#about to read 4, iclass 4, count 2 2006.173.15:50:40.69#ibcon#read 4, iclass 4, count 2 2006.173.15:50:40.69#ibcon#about to read 5, iclass 4, count 2 2006.173.15:50:40.69#ibcon#read 5, iclass 4, count 2 2006.173.15:50:40.69#ibcon#about to read 6, iclass 4, count 2 2006.173.15:50:40.69#ibcon#read 6, iclass 4, count 2 2006.173.15:50:40.69#ibcon#end of sib2, iclass 4, count 2 2006.173.15:50:40.69#ibcon#*mode == 0, iclass 4, count 2 2006.173.15:50:40.69#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.15:50:40.69#ibcon#[25=AT05-04\r\n] 2006.173.15:50:40.69#ibcon#*before write, iclass 4, count 2 2006.173.15:50:40.69#ibcon#enter sib2, iclass 4, count 2 2006.173.15:50:40.69#ibcon#flushed, iclass 4, count 2 2006.173.15:50:40.69#ibcon#about to write, iclass 4, count 2 2006.173.15:50:40.69#ibcon#wrote, iclass 4, count 2 2006.173.15:50:40.69#ibcon#about to read 3, iclass 4, count 2 2006.173.15:50:40.72#ibcon#read 3, iclass 4, count 2 2006.173.15:50:40.72#ibcon#about to read 4, iclass 4, count 2 2006.173.15:50:40.72#ibcon#read 4, iclass 4, count 2 2006.173.15:50:40.72#ibcon#about to read 5, iclass 4, count 2 2006.173.15:50:40.72#ibcon#read 5, iclass 4, count 2 2006.173.15:50:40.72#ibcon#about to read 6, iclass 4, count 2 2006.173.15:50:40.72#ibcon#read 6, iclass 4, count 2 2006.173.15:50:40.72#ibcon#end of sib2, iclass 4, count 2 2006.173.15:50:40.72#ibcon#*after write, iclass 4, count 2 2006.173.15:50:40.72#ibcon#*before return 0, iclass 4, count 2 2006.173.15:50:40.72#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.15:50:40.72#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.15:50:40.72#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.15:50:40.72#ibcon#ireg 7 cls_cnt 0 2006.173.15:50:40.72#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.15:50:40.84#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.15:50:40.84#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.15:50:40.84#ibcon#enter wrdev, iclass 4, count 0 2006.173.15:50:40.84#ibcon#first serial, iclass 4, count 0 2006.173.15:50:40.84#ibcon#enter sib2, iclass 4, count 0 2006.173.15:50:40.84#ibcon#flushed, iclass 4, count 0 2006.173.15:50:40.84#ibcon#about to write, iclass 4, count 0 2006.173.15:50:40.84#ibcon#wrote, iclass 4, count 0 2006.173.15:50:40.84#ibcon#about to read 3, iclass 4, count 0 2006.173.15:50:40.86#ibcon#read 3, iclass 4, count 0 2006.173.15:50:40.86#ibcon#about to read 4, iclass 4, count 0 2006.173.15:50:40.86#ibcon#read 4, iclass 4, count 0 2006.173.15:50:40.86#ibcon#about to read 5, iclass 4, count 0 2006.173.15:50:40.86#ibcon#read 5, iclass 4, count 0 2006.173.15:50:40.86#ibcon#about to read 6, iclass 4, count 0 2006.173.15:50:40.86#ibcon#read 6, iclass 4, count 0 2006.173.15:50:40.86#ibcon#end of sib2, iclass 4, count 0 2006.173.15:50:40.86#ibcon#*mode == 0, iclass 4, count 0 2006.173.15:50:40.86#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.15:50:40.86#ibcon#[25=USB\r\n] 2006.173.15:50:40.86#ibcon#*before write, iclass 4, count 0 2006.173.15:50:40.86#ibcon#enter sib2, iclass 4, count 0 2006.173.15:50:40.86#ibcon#flushed, iclass 4, count 0 2006.173.15:50:40.86#ibcon#about to write, iclass 4, count 0 2006.173.15:50:40.86#ibcon#wrote, iclass 4, count 0 2006.173.15:50:40.86#ibcon#about to read 3, iclass 4, count 0 2006.173.15:50:40.89#ibcon#read 3, iclass 4, count 0 2006.173.15:50:40.89#ibcon#about to read 4, iclass 4, count 0 2006.173.15:50:40.89#ibcon#read 4, iclass 4, count 0 2006.173.15:50:40.89#ibcon#about to read 5, iclass 4, count 0 2006.173.15:50:40.89#ibcon#read 5, iclass 4, count 0 2006.173.15:50:40.89#ibcon#about to read 6, iclass 4, count 0 2006.173.15:50:40.89#ibcon#read 6, iclass 4, count 0 2006.173.15:50:40.89#ibcon#end of sib2, iclass 4, count 0 2006.173.15:50:40.89#ibcon#*after write, iclass 4, count 0 2006.173.15:50:40.89#ibcon#*before return 0, iclass 4, count 0 2006.173.15:50:40.89#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.15:50:40.89#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.15:50:40.89#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.15:50:40.89#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.15:50:40.89$vck44/valo=6,814.99 2006.173.15:50:40.89#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.15:50:40.89#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.15:50:40.89#ibcon#ireg 17 cls_cnt 0 2006.173.15:50:40.89#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.15:50:40.89#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.15:50:40.89#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.15:50:40.89#ibcon#enter wrdev, iclass 6, count 0 2006.173.15:50:40.89#ibcon#first serial, iclass 6, count 0 2006.173.15:50:40.89#ibcon#enter sib2, iclass 6, count 0 2006.173.15:50:40.89#ibcon#flushed, iclass 6, count 0 2006.173.15:50:40.89#ibcon#about to write, iclass 6, count 0 2006.173.15:50:40.89#ibcon#wrote, iclass 6, count 0 2006.173.15:50:40.89#ibcon#about to read 3, iclass 6, count 0 2006.173.15:50:40.91#ibcon#read 3, iclass 6, count 0 2006.173.15:50:40.91#ibcon#about to read 4, iclass 6, count 0 2006.173.15:50:40.91#ibcon#read 4, iclass 6, count 0 2006.173.15:50:40.91#ibcon#about to read 5, iclass 6, count 0 2006.173.15:50:40.91#ibcon#read 5, iclass 6, count 0 2006.173.15:50:40.91#ibcon#about to read 6, iclass 6, count 0 2006.173.15:50:40.91#ibcon#read 6, iclass 6, count 0 2006.173.15:50:40.91#ibcon#end of sib2, iclass 6, count 0 2006.173.15:50:40.91#ibcon#*mode == 0, iclass 6, count 0 2006.173.15:50:40.91#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.15:50:40.91#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.15:50:40.91#ibcon#*before write, iclass 6, count 0 2006.173.15:50:40.91#ibcon#enter sib2, iclass 6, count 0 2006.173.15:50:40.91#ibcon#flushed, iclass 6, count 0 2006.173.15:50:40.91#ibcon#about to write, iclass 6, count 0 2006.173.15:50:40.91#ibcon#wrote, iclass 6, count 0 2006.173.15:50:40.91#ibcon#about to read 3, iclass 6, count 0 2006.173.15:50:40.95#ibcon#read 3, iclass 6, count 0 2006.173.15:50:40.95#ibcon#about to read 4, iclass 6, count 0 2006.173.15:50:40.95#ibcon#read 4, iclass 6, count 0 2006.173.15:50:40.95#ibcon#about to read 5, iclass 6, count 0 2006.173.15:50:40.95#ibcon#read 5, iclass 6, count 0 2006.173.15:50:40.95#ibcon#about to read 6, iclass 6, count 0 2006.173.15:50:40.95#ibcon#read 6, iclass 6, count 0 2006.173.15:50:40.95#ibcon#end of sib2, iclass 6, count 0 2006.173.15:50:40.95#ibcon#*after write, iclass 6, count 0 2006.173.15:50:40.95#ibcon#*before return 0, iclass 6, count 0 2006.173.15:50:40.95#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.15:50:40.95#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.15:50:40.95#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.15:50:40.95#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.15:50:40.95$vck44/va=6,3 2006.173.15:50:40.95#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.15:50:40.95#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.15:50:40.95#ibcon#ireg 11 cls_cnt 2 2006.173.15:50:40.95#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.15:50:41.01#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.15:50:41.01#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.15:50:41.01#ibcon#enter wrdev, iclass 10, count 2 2006.173.15:50:41.01#ibcon#first serial, iclass 10, count 2 2006.173.15:50:41.01#ibcon#enter sib2, iclass 10, count 2 2006.173.15:50:41.01#ibcon#flushed, iclass 10, count 2 2006.173.15:50:41.01#ibcon#about to write, iclass 10, count 2 2006.173.15:50:41.01#ibcon#wrote, iclass 10, count 2 2006.173.15:50:41.01#ibcon#about to read 3, iclass 10, count 2 2006.173.15:50:41.03#ibcon#read 3, iclass 10, count 2 2006.173.15:50:41.03#ibcon#about to read 4, iclass 10, count 2 2006.173.15:50:41.03#ibcon#read 4, iclass 10, count 2 2006.173.15:50:41.03#ibcon#about to read 5, iclass 10, count 2 2006.173.15:50:41.03#ibcon#read 5, iclass 10, count 2 2006.173.15:50:41.03#ibcon#about to read 6, iclass 10, count 2 2006.173.15:50:41.03#ibcon#read 6, iclass 10, count 2 2006.173.15:50:41.03#ibcon#end of sib2, iclass 10, count 2 2006.173.15:50:41.03#ibcon#*mode == 0, iclass 10, count 2 2006.173.15:50:41.03#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.15:50:41.03#ibcon#[25=AT06-03\r\n] 2006.173.15:50:41.03#ibcon#*before write, iclass 10, count 2 2006.173.15:50:41.03#ibcon#enter sib2, iclass 10, count 2 2006.173.15:50:41.03#ibcon#flushed, iclass 10, count 2 2006.173.15:50:41.03#ibcon#about to write, iclass 10, count 2 2006.173.15:50:41.03#ibcon#wrote, iclass 10, count 2 2006.173.15:50:41.03#ibcon#about to read 3, iclass 10, count 2 2006.173.15:50:41.06#ibcon#read 3, iclass 10, count 2 2006.173.15:50:41.06#ibcon#about to read 4, iclass 10, count 2 2006.173.15:50:41.06#ibcon#read 4, iclass 10, count 2 2006.173.15:50:41.06#ibcon#about to read 5, iclass 10, count 2 2006.173.15:50:41.06#ibcon#read 5, iclass 10, count 2 2006.173.15:50:41.06#ibcon#about to read 6, iclass 10, count 2 2006.173.15:50:41.06#ibcon#read 6, iclass 10, count 2 2006.173.15:50:41.06#ibcon#end of sib2, iclass 10, count 2 2006.173.15:50:41.06#ibcon#*after write, iclass 10, count 2 2006.173.15:50:41.06#ibcon#*before return 0, iclass 10, count 2 2006.173.15:50:41.06#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.15:50:41.06#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.15:50:41.06#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.15:50:41.06#ibcon#ireg 7 cls_cnt 0 2006.173.15:50:41.06#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.15:50:41.18#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.15:50:41.18#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.15:50:41.18#ibcon#enter wrdev, iclass 10, count 0 2006.173.15:50:41.18#ibcon#first serial, iclass 10, count 0 2006.173.15:50:41.18#ibcon#enter sib2, iclass 10, count 0 2006.173.15:50:41.18#ibcon#flushed, iclass 10, count 0 2006.173.15:50:41.18#ibcon#about to write, iclass 10, count 0 2006.173.15:50:41.18#ibcon#wrote, iclass 10, count 0 2006.173.15:50:41.18#ibcon#about to read 3, iclass 10, count 0 2006.173.15:50:41.20#ibcon#read 3, iclass 10, count 0 2006.173.15:50:41.20#ibcon#about to read 4, iclass 10, count 0 2006.173.15:50:41.20#ibcon#read 4, iclass 10, count 0 2006.173.15:50:41.20#ibcon#about to read 5, iclass 10, count 0 2006.173.15:50:41.20#ibcon#read 5, iclass 10, count 0 2006.173.15:50:41.20#ibcon#about to read 6, iclass 10, count 0 2006.173.15:50:41.20#ibcon#read 6, iclass 10, count 0 2006.173.15:50:41.20#ibcon#end of sib2, iclass 10, count 0 2006.173.15:50:41.20#ibcon#*mode == 0, iclass 10, count 0 2006.173.15:50:41.20#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.15:50:41.20#ibcon#[25=USB\r\n] 2006.173.15:50:41.20#ibcon#*before write, iclass 10, count 0 2006.173.15:50:41.20#ibcon#enter sib2, iclass 10, count 0 2006.173.15:50:41.20#ibcon#flushed, iclass 10, count 0 2006.173.15:50:41.20#ibcon#about to write, iclass 10, count 0 2006.173.15:50:41.20#ibcon#wrote, iclass 10, count 0 2006.173.15:50:41.20#ibcon#about to read 3, iclass 10, count 0 2006.173.15:50:41.23#ibcon#read 3, iclass 10, count 0 2006.173.15:50:41.23#ibcon#about to read 4, iclass 10, count 0 2006.173.15:50:41.23#ibcon#read 4, iclass 10, count 0 2006.173.15:50:41.23#ibcon#about to read 5, iclass 10, count 0 2006.173.15:50:41.23#ibcon#read 5, iclass 10, count 0 2006.173.15:50:41.23#ibcon#about to read 6, iclass 10, count 0 2006.173.15:50:41.23#ibcon#read 6, iclass 10, count 0 2006.173.15:50:41.23#ibcon#end of sib2, iclass 10, count 0 2006.173.15:50:41.23#ibcon#*after write, iclass 10, count 0 2006.173.15:50:41.23#ibcon#*before return 0, iclass 10, count 0 2006.173.15:50:41.23#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.15:50:41.23#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.15:50:41.23#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.15:50:41.23#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.15:50:41.23$vck44/valo=7,864.99 2006.173.15:50:41.23#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.15:50:41.23#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.15:50:41.23#ibcon#ireg 17 cls_cnt 0 2006.173.15:50:41.23#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.15:50:41.23#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.15:50:41.23#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.15:50:41.23#ibcon#enter wrdev, iclass 12, count 0 2006.173.15:50:41.23#ibcon#first serial, iclass 12, count 0 2006.173.15:50:41.23#ibcon#enter sib2, iclass 12, count 0 2006.173.15:50:41.23#ibcon#flushed, iclass 12, count 0 2006.173.15:50:41.23#ibcon#about to write, iclass 12, count 0 2006.173.15:50:41.23#ibcon#wrote, iclass 12, count 0 2006.173.15:50:41.23#ibcon#about to read 3, iclass 12, count 0 2006.173.15:50:41.25#ibcon#read 3, iclass 12, count 0 2006.173.15:50:41.25#ibcon#about to read 4, iclass 12, count 0 2006.173.15:50:41.25#ibcon#read 4, iclass 12, count 0 2006.173.15:50:41.25#ibcon#about to read 5, iclass 12, count 0 2006.173.15:50:41.25#ibcon#read 5, iclass 12, count 0 2006.173.15:50:41.25#ibcon#about to read 6, iclass 12, count 0 2006.173.15:50:41.25#ibcon#read 6, iclass 12, count 0 2006.173.15:50:41.25#ibcon#end of sib2, iclass 12, count 0 2006.173.15:50:41.25#ibcon#*mode == 0, iclass 12, count 0 2006.173.15:50:41.25#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.15:50:41.25#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.15:50:41.25#ibcon#*before write, iclass 12, count 0 2006.173.15:50:41.25#ibcon#enter sib2, iclass 12, count 0 2006.173.15:50:41.25#ibcon#flushed, iclass 12, count 0 2006.173.15:50:41.25#ibcon#about to write, iclass 12, count 0 2006.173.15:50:41.25#ibcon#wrote, iclass 12, count 0 2006.173.15:50:41.25#ibcon#about to read 3, iclass 12, count 0 2006.173.15:50:41.29#ibcon#read 3, iclass 12, count 0 2006.173.15:50:41.29#ibcon#about to read 4, iclass 12, count 0 2006.173.15:50:41.29#ibcon#read 4, iclass 12, count 0 2006.173.15:50:41.29#ibcon#about to read 5, iclass 12, count 0 2006.173.15:50:41.29#ibcon#read 5, iclass 12, count 0 2006.173.15:50:41.29#ibcon#about to read 6, iclass 12, count 0 2006.173.15:50:41.29#ibcon#read 6, iclass 12, count 0 2006.173.15:50:41.29#ibcon#end of sib2, iclass 12, count 0 2006.173.15:50:41.29#ibcon#*after write, iclass 12, count 0 2006.173.15:50:41.29#ibcon#*before return 0, iclass 12, count 0 2006.173.15:50:41.29#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.15:50:41.29#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.15:50:41.29#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.15:50:41.29#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.15:50:41.29$vck44/va=7,4 2006.173.15:50:41.29#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.15:50:41.29#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.15:50:41.29#ibcon#ireg 11 cls_cnt 2 2006.173.15:50:41.29#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.15:50:41.35#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.15:50:41.35#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.15:50:41.35#ibcon#enter wrdev, iclass 14, count 2 2006.173.15:50:41.35#ibcon#first serial, iclass 14, count 2 2006.173.15:50:41.35#ibcon#enter sib2, iclass 14, count 2 2006.173.15:50:41.35#ibcon#flushed, iclass 14, count 2 2006.173.15:50:41.35#ibcon#about to write, iclass 14, count 2 2006.173.15:50:41.35#ibcon#wrote, iclass 14, count 2 2006.173.15:50:41.35#ibcon#about to read 3, iclass 14, count 2 2006.173.15:50:41.37#ibcon#read 3, iclass 14, count 2 2006.173.15:50:41.37#ibcon#about to read 4, iclass 14, count 2 2006.173.15:50:41.37#ibcon#read 4, iclass 14, count 2 2006.173.15:50:41.37#ibcon#about to read 5, iclass 14, count 2 2006.173.15:50:41.37#ibcon#read 5, iclass 14, count 2 2006.173.15:50:41.37#ibcon#about to read 6, iclass 14, count 2 2006.173.15:50:41.37#ibcon#read 6, iclass 14, count 2 2006.173.15:50:41.37#ibcon#end of sib2, iclass 14, count 2 2006.173.15:50:41.37#ibcon#*mode == 0, iclass 14, count 2 2006.173.15:50:41.37#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.15:50:41.37#ibcon#[25=AT07-04\r\n] 2006.173.15:50:41.37#ibcon#*before write, iclass 14, count 2 2006.173.15:50:41.37#ibcon#enter sib2, iclass 14, count 2 2006.173.15:50:41.37#ibcon#flushed, iclass 14, count 2 2006.173.15:50:41.37#ibcon#about to write, iclass 14, count 2 2006.173.15:50:41.37#ibcon#wrote, iclass 14, count 2 2006.173.15:50:41.37#ibcon#about to read 3, iclass 14, count 2 2006.173.15:50:41.40#ibcon#read 3, iclass 14, count 2 2006.173.15:50:41.40#ibcon#about to read 4, iclass 14, count 2 2006.173.15:50:41.40#ibcon#read 4, iclass 14, count 2 2006.173.15:50:41.40#ibcon#about to read 5, iclass 14, count 2 2006.173.15:50:41.40#ibcon#read 5, iclass 14, count 2 2006.173.15:50:41.40#ibcon#about to read 6, iclass 14, count 2 2006.173.15:50:41.40#ibcon#read 6, iclass 14, count 2 2006.173.15:50:41.40#ibcon#end of sib2, iclass 14, count 2 2006.173.15:50:41.40#ibcon#*after write, iclass 14, count 2 2006.173.15:50:41.40#ibcon#*before return 0, iclass 14, count 2 2006.173.15:50:41.40#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.15:50:41.40#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.15:50:41.40#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.15:50:41.40#ibcon#ireg 7 cls_cnt 0 2006.173.15:50:41.40#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.15:50:41.52#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.15:50:41.52#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.15:50:41.52#ibcon#enter wrdev, iclass 14, count 0 2006.173.15:50:41.52#ibcon#first serial, iclass 14, count 0 2006.173.15:50:41.52#ibcon#enter sib2, iclass 14, count 0 2006.173.15:50:41.52#ibcon#flushed, iclass 14, count 0 2006.173.15:50:41.52#ibcon#about to write, iclass 14, count 0 2006.173.15:50:41.52#ibcon#wrote, iclass 14, count 0 2006.173.15:50:41.52#ibcon#about to read 3, iclass 14, count 0 2006.173.15:50:41.54#ibcon#read 3, iclass 14, count 0 2006.173.15:50:41.54#ibcon#about to read 4, iclass 14, count 0 2006.173.15:50:41.54#ibcon#read 4, iclass 14, count 0 2006.173.15:50:41.54#ibcon#about to read 5, iclass 14, count 0 2006.173.15:50:41.54#ibcon#read 5, iclass 14, count 0 2006.173.15:50:41.54#ibcon#about to read 6, iclass 14, count 0 2006.173.15:50:41.54#ibcon#read 6, iclass 14, count 0 2006.173.15:50:41.54#ibcon#end of sib2, iclass 14, count 0 2006.173.15:50:41.54#ibcon#*mode == 0, iclass 14, count 0 2006.173.15:50:41.54#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.15:50:41.54#ibcon#[25=USB\r\n] 2006.173.15:50:41.54#ibcon#*before write, iclass 14, count 0 2006.173.15:50:41.54#ibcon#enter sib2, iclass 14, count 0 2006.173.15:50:41.54#ibcon#flushed, iclass 14, count 0 2006.173.15:50:41.54#ibcon#about to write, iclass 14, count 0 2006.173.15:50:41.54#ibcon#wrote, iclass 14, count 0 2006.173.15:50:41.54#ibcon#about to read 3, iclass 14, count 0 2006.173.15:50:41.57#ibcon#read 3, iclass 14, count 0 2006.173.15:50:41.57#ibcon#about to read 4, iclass 14, count 0 2006.173.15:50:41.57#ibcon#read 4, iclass 14, count 0 2006.173.15:50:41.57#ibcon#about to read 5, iclass 14, count 0 2006.173.15:50:41.57#ibcon#read 5, iclass 14, count 0 2006.173.15:50:41.57#ibcon#about to read 6, iclass 14, count 0 2006.173.15:50:41.57#ibcon#read 6, iclass 14, count 0 2006.173.15:50:41.57#ibcon#end of sib2, iclass 14, count 0 2006.173.15:50:41.57#ibcon#*after write, iclass 14, count 0 2006.173.15:50:41.57#ibcon#*before return 0, iclass 14, count 0 2006.173.15:50:41.57#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.15:50:41.57#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.15:50:41.57#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.15:50:41.57#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.15:50:41.57$vck44/valo=8,884.99 2006.173.15:50:41.57#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.15:50:41.57#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.15:50:41.57#ibcon#ireg 17 cls_cnt 0 2006.173.15:50:41.57#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.15:50:41.57#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.15:50:41.57#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.15:50:41.57#ibcon#enter wrdev, iclass 16, count 0 2006.173.15:50:41.57#ibcon#first serial, iclass 16, count 0 2006.173.15:50:41.57#ibcon#enter sib2, iclass 16, count 0 2006.173.15:50:41.57#ibcon#flushed, iclass 16, count 0 2006.173.15:50:41.57#ibcon#about to write, iclass 16, count 0 2006.173.15:50:41.57#ibcon#wrote, iclass 16, count 0 2006.173.15:50:41.57#ibcon#about to read 3, iclass 16, count 0 2006.173.15:50:41.59#ibcon#read 3, iclass 16, count 0 2006.173.15:50:41.59#ibcon#about to read 4, iclass 16, count 0 2006.173.15:50:41.59#ibcon#read 4, iclass 16, count 0 2006.173.15:50:41.59#ibcon#about to read 5, iclass 16, count 0 2006.173.15:50:41.59#ibcon#read 5, iclass 16, count 0 2006.173.15:50:41.59#ibcon#about to read 6, iclass 16, count 0 2006.173.15:50:41.59#ibcon#read 6, iclass 16, count 0 2006.173.15:50:41.59#ibcon#end of sib2, iclass 16, count 0 2006.173.15:50:41.59#ibcon#*mode == 0, iclass 16, count 0 2006.173.15:50:41.59#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.15:50:41.59#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.15:50:41.59#ibcon#*before write, iclass 16, count 0 2006.173.15:50:41.59#ibcon#enter sib2, iclass 16, count 0 2006.173.15:50:41.59#ibcon#flushed, iclass 16, count 0 2006.173.15:50:41.59#ibcon#about to write, iclass 16, count 0 2006.173.15:50:41.59#ibcon#wrote, iclass 16, count 0 2006.173.15:50:41.59#ibcon#about to read 3, iclass 16, count 0 2006.173.15:50:41.63#ibcon#read 3, iclass 16, count 0 2006.173.15:50:41.63#ibcon#about to read 4, iclass 16, count 0 2006.173.15:50:41.63#ibcon#read 4, iclass 16, count 0 2006.173.15:50:41.63#ibcon#about to read 5, iclass 16, count 0 2006.173.15:50:41.63#ibcon#read 5, iclass 16, count 0 2006.173.15:50:41.63#ibcon#about to read 6, iclass 16, count 0 2006.173.15:50:41.63#ibcon#read 6, iclass 16, count 0 2006.173.15:50:41.63#ibcon#end of sib2, iclass 16, count 0 2006.173.15:50:41.63#ibcon#*after write, iclass 16, count 0 2006.173.15:50:41.63#ibcon#*before return 0, iclass 16, count 0 2006.173.15:50:41.63#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.15:50:41.63#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.15:50:41.63#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.15:50:41.63#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.15:50:41.63$vck44/va=8,4 2006.173.15:50:41.63#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.15:50:41.63#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.15:50:41.63#ibcon#ireg 11 cls_cnt 2 2006.173.15:50:41.63#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.15:50:41.69#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.15:50:41.69#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.15:50:41.69#ibcon#enter wrdev, iclass 18, count 2 2006.173.15:50:41.69#ibcon#first serial, iclass 18, count 2 2006.173.15:50:41.69#ibcon#enter sib2, iclass 18, count 2 2006.173.15:50:41.69#ibcon#flushed, iclass 18, count 2 2006.173.15:50:41.69#ibcon#about to write, iclass 18, count 2 2006.173.15:50:41.69#ibcon#wrote, iclass 18, count 2 2006.173.15:50:41.69#ibcon#about to read 3, iclass 18, count 2 2006.173.15:50:41.71#ibcon#read 3, iclass 18, count 2 2006.173.15:50:41.71#ibcon#about to read 4, iclass 18, count 2 2006.173.15:50:41.71#ibcon#read 4, iclass 18, count 2 2006.173.15:50:41.71#ibcon#about to read 5, iclass 18, count 2 2006.173.15:50:41.71#ibcon#read 5, iclass 18, count 2 2006.173.15:50:41.71#ibcon#about to read 6, iclass 18, count 2 2006.173.15:50:41.71#ibcon#read 6, iclass 18, count 2 2006.173.15:50:41.71#ibcon#end of sib2, iclass 18, count 2 2006.173.15:50:41.71#ibcon#*mode == 0, iclass 18, count 2 2006.173.15:50:41.71#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.15:50:41.71#ibcon#[25=AT08-04\r\n] 2006.173.15:50:41.71#ibcon#*before write, iclass 18, count 2 2006.173.15:50:41.71#ibcon#enter sib2, iclass 18, count 2 2006.173.15:50:41.71#ibcon#flushed, iclass 18, count 2 2006.173.15:50:41.71#ibcon#about to write, iclass 18, count 2 2006.173.15:50:41.71#ibcon#wrote, iclass 18, count 2 2006.173.15:50:41.71#ibcon#about to read 3, iclass 18, count 2 2006.173.15:50:41.74#ibcon#read 3, iclass 18, count 2 2006.173.15:50:41.74#ibcon#about to read 4, iclass 18, count 2 2006.173.15:50:41.74#ibcon#read 4, iclass 18, count 2 2006.173.15:50:41.74#ibcon#about to read 5, iclass 18, count 2 2006.173.15:50:41.74#ibcon#read 5, iclass 18, count 2 2006.173.15:50:41.74#ibcon#about to read 6, iclass 18, count 2 2006.173.15:50:41.74#ibcon#read 6, iclass 18, count 2 2006.173.15:50:41.74#ibcon#end of sib2, iclass 18, count 2 2006.173.15:50:41.74#ibcon#*after write, iclass 18, count 2 2006.173.15:50:41.74#ibcon#*before return 0, iclass 18, count 2 2006.173.15:50:41.74#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.15:50:41.74#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.15:50:41.74#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.15:50:41.74#ibcon#ireg 7 cls_cnt 0 2006.173.15:50:41.74#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.15:50:41.86#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.15:50:41.86#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.15:50:41.86#ibcon#enter wrdev, iclass 18, count 0 2006.173.15:50:41.86#ibcon#first serial, iclass 18, count 0 2006.173.15:50:41.86#ibcon#enter sib2, iclass 18, count 0 2006.173.15:50:41.86#ibcon#flushed, iclass 18, count 0 2006.173.15:50:41.86#ibcon#about to write, iclass 18, count 0 2006.173.15:50:41.86#ibcon#wrote, iclass 18, count 0 2006.173.15:50:41.86#ibcon#about to read 3, iclass 18, count 0 2006.173.15:50:41.88#ibcon#read 3, iclass 18, count 0 2006.173.15:50:41.88#ibcon#about to read 4, iclass 18, count 0 2006.173.15:50:41.88#ibcon#read 4, iclass 18, count 0 2006.173.15:50:41.88#ibcon#about to read 5, iclass 18, count 0 2006.173.15:50:41.88#ibcon#read 5, iclass 18, count 0 2006.173.15:50:41.88#ibcon#about to read 6, iclass 18, count 0 2006.173.15:50:41.88#ibcon#read 6, iclass 18, count 0 2006.173.15:50:41.88#ibcon#end of sib2, iclass 18, count 0 2006.173.15:50:41.88#ibcon#*mode == 0, iclass 18, count 0 2006.173.15:50:41.88#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.15:50:41.88#ibcon#[25=USB\r\n] 2006.173.15:50:41.88#ibcon#*before write, iclass 18, count 0 2006.173.15:50:41.88#ibcon#enter sib2, iclass 18, count 0 2006.173.15:50:41.88#ibcon#flushed, iclass 18, count 0 2006.173.15:50:41.88#ibcon#about to write, iclass 18, count 0 2006.173.15:50:41.88#ibcon#wrote, iclass 18, count 0 2006.173.15:50:41.88#ibcon#about to read 3, iclass 18, count 0 2006.173.15:50:41.91#ibcon#read 3, iclass 18, count 0 2006.173.15:50:41.91#ibcon#about to read 4, iclass 18, count 0 2006.173.15:50:41.91#ibcon#read 4, iclass 18, count 0 2006.173.15:50:41.91#ibcon#about to read 5, iclass 18, count 0 2006.173.15:50:41.91#ibcon#read 5, iclass 18, count 0 2006.173.15:50:41.91#ibcon#about to read 6, iclass 18, count 0 2006.173.15:50:41.91#ibcon#read 6, iclass 18, count 0 2006.173.15:50:41.91#ibcon#end of sib2, iclass 18, count 0 2006.173.15:50:41.91#ibcon#*after write, iclass 18, count 0 2006.173.15:50:41.91#ibcon#*before return 0, iclass 18, count 0 2006.173.15:50:41.91#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.15:50:41.91#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.15:50:41.91#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.15:50:41.91#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.15:50:41.91$vck44/vblo=1,629.99 2006.173.15:50:41.91#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.15:50:41.91#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.15:50:41.91#ibcon#ireg 17 cls_cnt 0 2006.173.15:50:41.91#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.15:50:41.91#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.15:50:41.91#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.15:50:41.91#ibcon#enter wrdev, iclass 20, count 0 2006.173.15:50:41.91#ibcon#first serial, iclass 20, count 0 2006.173.15:50:41.91#ibcon#enter sib2, iclass 20, count 0 2006.173.15:50:41.91#ibcon#flushed, iclass 20, count 0 2006.173.15:50:41.91#ibcon#about to write, iclass 20, count 0 2006.173.15:50:41.91#ibcon#wrote, iclass 20, count 0 2006.173.15:50:41.91#ibcon#about to read 3, iclass 20, count 0 2006.173.15:50:41.93#ibcon#read 3, iclass 20, count 0 2006.173.15:50:41.93#ibcon#about to read 4, iclass 20, count 0 2006.173.15:50:41.93#ibcon#read 4, iclass 20, count 0 2006.173.15:50:41.93#ibcon#about to read 5, iclass 20, count 0 2006.173.15:50:41.93#ibcon#read 5, iclass 20, count 0 2006.173.15:50:41.93#ibcon#about to read 6, iclass 20, count 0 2006.173.15:50:41.93#ibcon#read 6, iclass 20, count 0 2006.173.15:50:41.93#ibcon#end of sib2, iclass 20, count 0 2006.173.15:50:41.93#ibcon#*mode == 0, iclass 20, count 0 2006.173.15:50:41.93#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.15:50:41.93#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.15:50:41.93#ibcon#*before write, iclass 20, count 0 2006.173.15:50:41.93#ibcon#enter sib2, iclass 20, count 0 2006.173.15:50:41.93#ibcon#flushed, iclass 20, count 0 2006.173.15:50:41.93#ibcon#about to write, iclass 20, count 0 2006.173.15:50:41.93#ibcon#wrote, iclass 20, count 0 2006.173.15:50:41.93#ibcon#about to read 3, iclass 20, count 0 2006.173.15:50:41.97#ibcon#read 3, iclass 20, count 0 2006.173.15:50:41.97#ibcon#about to read 4, iclass 20, count 0 2006.173.15:50:41.97#ibcon#read 4, iclass 20, count 0 2006.173.15:50:41.97#ibcon#about to read 5, iclass 20, count 0 2006.173.15:50:41.97#ibcon#read 5, iclass 20, count 0 2006.173.15:50:41.97#ibcon#about to read 6, iclass 20, count 0 2006.173.15:50:41.97#ibcon#read 6, iclass 20, count 0 2006.173.15:50:41.97#ibcon#end of sib2, iclass 20, count 0 2006.173.15:50:41.97#ibcon#*after write, iclass 20, count 0 2006.173.15:50:41.97#ibcon#*before return 0, iclass 20, count 0 2006.173.15:50:41.97#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.15:50:41.97#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.15:50:41.97#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.15:50:41.97#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.15:50:41.97$vck44/vb=1,4 2006.173.15:50:41.97#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.15:50:41.97#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.15:50:41.97#ibcon#ireg 11 cls_cnt 2 2006.173.15:50:41.97#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.15:50:41.97#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.15:50:41.97#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.15:50:41.97#ibcon#enter wrdev, iclass 22, count 2 2006.173.15:50:41.97#ibcon#first serial, iclass 22, count 2 2006.173.15:50:41.97#ibcon#enter sib2, iclass 22, count 2 2006.173.15:50:41.97#ibcon#flushed, iclass 22, count 2 2006.173.15:50:41.97#ibcon#about to write, iclass 22, count 2 2006.173.15:50:41.97#ibcon#wrote, iclass 22, count 2 2006.173.15:50:41.97#ibcon#about to read 3, iclass 22, count 2 2006.173.15:50:41.99#ibcon#read 3, iclass 22, count 2 2006.173.15:50:41.99#ibcon#about to read 4, iclass 22, count 2 2006.173.15:50:41.99#ibcon#read 4, iclass 22, count 2 2006.173.15:50:41.99#ibcon#about to read 5, iclass 22, count 2 2006.173.15:50:41.99#ibcon#read 5, iclass 22, count 2 2006.173.15:50:41.99#ibcon#about to read 6, iclass 22, count 2 2006.173.15:50:41.99#ibcon#read 6, iclass 22, count 2 2006.173.15:50:41.99#ibcon#end of sib2, iclass 22, count 2 2006.173.15:50:41.99#ibcon#*mode == 0, iclass 22, count 2 2006.173.15:50:41.99#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.15:50:41.99#ibcon#[27=AT01-04\r\n] 2006.173.15:50:41.99#ibcon#*before write, iclass 22, count 2 2006.173.15:50:41.99#ibcon#enter sib2, iclass 22, count 2 2006.173.15:50:41.99#ibcon#flushed, iclass 22, count 2 2006.173.15:50:41.99#ibcon#about to write, iclass 22, count 2 2006.173.15:50:41.99#ibcon#wrote, iclass 22, count 2 2006.173.15:50:41.99#ibcon#about to read 3, iclass 22, count 2 2006.173.15:50:42.02#ibcon#read 3, iclass 22, count 2 2006.173.15:50:42.02#ibcon#about to read 4, iclass 22, count 2 2006.173.15:50:42.02#ibcon#read 4, iclass 22, count 2 2006.173.15:50:42.02#ibcon#about to read 5, iclass 22, count 2 2006.173.15:50:42.02#ibcon#read 5, iclass 22, count 2 2006.173.15:50:42.02#ibcon#about to read 6, iclass 22, count 2 2006.173.15:50:42.02#ibcon#read 6, iclass 22, count 2 2006.173.15:50:42.02#ibcon#end of sib2, iclass 22, count 2 2006.173.15:50:42.02#ibcon#*after write, iclass 22, count 2 2006.173.15:50:42.02#ibcon#*before return 0, iclass 22, count 2 2006.173.15:50:42.02#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.15:50:42.02#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.15:50:42.02#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.15:50:42.02#ibcon#ireg 7 cls_cnt 0 2006.173.15:50:42.02#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.15:50:42.14#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.15:50:42.14#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.15:50:42.14#ibcon#enter wrdev, iclass 22, count 0 2006.173.15:50:42.14#ibcon#first serial, iclass 22, count 0 2006.173.15:50:42.14#ibcon#enter sib2, iclass 22, count 0 2006.173.15:50:42.14#ibcon#flushed, iclass 22, count 0 2006.173.15:50:42.14#ibcon#about to write, iclass 22, count 0 2006.173.15:50:42.14#ibcon#wrote, iclass 22, count 0 2006.173.15:50:42.14#ibcon#about to read 3, iclass 22, count 0 2006.173.15:50:42.16#ibcon#read 3, iclass 22, count 0 2006.173.15:50:42.16#ibcon#about to read 4, iclass 22, count 0 2006.173.15:50:42.16#ibcon#read 4, iclass 22, count 0 2006.173.15:50:42.16#ibcon#about to read 5, iclass 22, count 0 2006.173.15:50:42.16#ibcon#read 5, iclass 22, count 0 2006.173.15:50:42.16#ibcon#about to read 6, iclass 22, count 0 2006.173.15:50:42.16#ibcon#read 6, iclass 22, count 0 2006.173.15:50:42.16#ibcon#end of sib2, iclass 22, count 0 2006.173.15:50:42.16#ibcon#*mode == 0, iclass 22, count 0 2006.173.15:50:42.16#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.15:50:42.16#ibcon#[27=USB\r\n] 2006.173.15:50:42.16#ibcon#*before write, iclass 22, count 0 2006.173.15:50:42.16#ibcon#enter sib2, iclass 22, count 0 2006.173.15:50:42.16#ibcon#flushed, iclass 22, count 0 2006.173.15:50:42.16#ibcon#about to write, iclass 22, count 0 2006.173.15:50:42.16#ibcon#wrote, iclass 22, count 0 2006.173.15:50:42.16#ibcon#about to read 3, iclass 22, count 0 2006.173.15:50:42.19#ibcon#read 3, iclass 22, count 0 2006.173.15:50:42.19#ibcon#about to read 4, iclass 22, count 0 2006.173.15:50:42.19#ibcon#read 4, iclass 22, count 0 2006.173.15:50:42.19#ibcon#about to read 5, iclass 22, count 0 2006.173.15:50:42.19#ibcon#read 5, iclass 22, count 0 2006.173.15:50:42.19#ibcon#about to read 6, iclass 22, count 0 2006.173.15:50:42.19#ibcon#read 6, iclass 22, count 0 2006.173.15:50:42.19#ibcon#end of sib2, iclass 22, count 0 2006.173.15:50:42.19#ibcon#*after write, iclass 22, count 0 2006.173.15:50:42.19#ibcon#*before return 0, iclass 22, count 0 2006.173.15:50:42.19#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.15:50:42.19#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.15:50:42.19#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.15:50:42.19#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.15:50:42.19$vck44/vblo=2,634.99 2006.173.15:50:42.19#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.15:50:42.19#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.15:50:42.19#ibcon#ireg 17 cls_cnt 0 2006.173.15:50:42.19#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.15:50:42.19#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.15:50:42.19#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.15:50:42.19#ibcon#enter wrdev, iclass 24, count 0 2006.173.15:50:42.19#ibcon#first serial, iclass 24, count 0 2006.173.15:50:42.19#ibcon#enter sib2, iclass 24, count 0 2006.173.15:50:42.19#ibcon#flushed, iclass 24, count 0 2006.173.15:50:42.19#ibcon#about to write, iclass 24, count 0 2006.173.15:50:42.19#ibcon#wrote, iclass 24, count 0 2006.173.15:50:42.19#ibcon#about to read 3, iclass 24, count 0 2006.173.15:50:42.21#ibcon#read 3, iclass 24, count 0 2006.173.15:50:42.21#ibcon#about to read 4, iclass 24, count 0 2006.173.15:50:42.21#ibcon#read 4, iclass 24, count 0 2006.173.15:50:42.21#ibcon#about to read 5, iclass 24, count 0 2006.173.15:50:42.21#ibcon#read 5, iclass 24, count 0 2006.173.15:50:42.21#ibcon#about to read 6, iclass 24, count 0 2006.173.15:50:42.21#ibcon#read 6, iclass 24, count 0 2006.173.15:50:42.21#ibcon#end of sib2, iclass 24, count 0 2006.173.15:50:42.21#ibcon#*mode == 0, iclass 24, count 0 2006.173.15:50:42.21#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.15:50:42.21#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.15:50:42.21#ibcon#*before write, iclass 24, count 0 2006.173.15:50:42.21#ibcon#enter sib2, iclass 24, count 0 2006.173.15:50:42.21#ibcon#flushed, iclass 24, count 0 2006.173.15:50:42.21#ibcon#about to write, iclass 24, count 0 2006.173.15:50:42.21#ibcon#wrote, iclass 24, count 0 2006.173.15:50:42.21#ibcon#about to read 3, iclass 24, count 0 2006.173.15:50:42.25#ibcon#read 3, iclass 24, count 0 2006.173.15:50:42.25#ibcon#about to read 4, iclass 24, count 0 2006.173.15:50:42.25#ibcon#read 4, iclass 24, count 0 2006.173.15:50:42.25#ibcon#about to read 5, iclass 24, count 0 2006.173.15:50:42.25#ibcon#read 5, iclass 24, count 0 2006.173.15:50:42.25#ibcon#about to read 6, iclass 24, count 0 2006.173.15:50:42.25#ibcon#read 6, iclass 24, count 0 2006.173.15:50:42.25#ibcon#end of sib2, iclass 24, count 0 2006.173.15:50:42.25#ibcon#*after write, iclass 24, count 0 2006.173.15:50:42.25#ibcon#*before return 0, iclass 24, count 0 2006.173.15:50:42.25#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.15:50:42.25#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.15:50:42.25#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.15:50:42.25#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.15:50:42.25$vck44/vb=2,4 2006.173.15:50:42.25#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.15:50:42.25#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.15:50:42.25#ibcon#ireg 11 cls_cnt 2 2006.173.15:50:42.25#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.15:50:42.31#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.15:50:42.31#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.15:50:42.31#ibcon#enter wrdev, iclass 26, count 2 2006.173.15:50:42.31#ibcon#first serial, iclass 26, count 2 2006.173.15:50:42.31#ibcon#enter sib2, iclass 26, count 2 2006.173.15:50:42.31#ibcon#flushed, iclass 26, count 2 2006.173.15:50:42.31#ibcon#about to write, iclass 26, count 2 2006.173.15:50:42.31#ibcon#wrote, iclass 26, count 2 2006.173.15:50:42.31#ibcon#about to read 3, iclass 26, count 2 2006.173.15:50:42.33#ibcon#read 3, iclass 26, count 2 2006.173.15:50:42.33#ibcon#about to read 4, iclass 26, count 2 2006.173.15:50:42.33#ibcon#read 4, iclass 26, count 2 2006.173.15:50:42.33#ibcon#about to read 5, iclass 26, count 2 2006.173.15:50:42.33#ibcon#read 5, iclass 26, count 2 2006.173.15:50:42.33#ibcon#about to read 6, iclass 26, count 2 2006.173.15:50:42.33#ibcon#read 6, iclass 26, count 2 2006.173.15:50:42.33#ibcon#end of sib2, iclass 26, count 2 2006.173.15:50:42.33#ibcon#*mode == 0, iclass 26, count 2 2006.173.15:50:42.33#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.15:50:42.33#ibcon#[27=AT02-04\r\n] 2006.173.15:50:42.33#ibcon#*before write, iclass 26, count 2 2006.173.15:50:42.33#ibcon#enter sib2, iclass 26, count 2 2006.173.15:50:42.33#ibcon#flushed, iclass 26, count 2 2006.173.15:50:42.33#ibcon#about to write, iclass 26, count 2 2006.173.15:50:42.33#ibcon#wrote, iclass 26, count 2 2006.173.15:50:42.33#ibcon#about to read 3, iclass 26, count 2 2006.173.15:50:42.36#ibcon#read 3, iclass 26, count 2 2006.173.15:50:42.36#ibcon#about to read 4, iclass 26, count 2 2006.173.15:50:42.36#ibcon#read 4, iclass 26, count 2 2006.173.15:50:42.36#ibcon#about to read 5, iclass 26, count 2 2006.173.15:50:42.36#ibcon#read 5, iclass 26, count 2 2006.173.15:50:42.36#ibcon#about to read 6, iclass 26, count 2 2006.173.15:50:42.36#ibcon#read 6, iclass 26, count 2 2006.173.15:50:42.36#ibcon#end of sib2, iclass 26, count 2 2006.173.15:50:42.36#ibcon#*after write, iclass 26, count 2 2006.173.15:50:42.36#ibcon#*before return 0, iclass 26, count 2 2006.173.15:50:42.36#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.15:50:42.36#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.15:50:42.36#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.15:50:42.36#ibcon#ireg 7 cls_cnt 0 2006.173.15:50:42.36#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.15:50:42.48#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.15:50:42.48#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.15:50:42.48#ibcon#enter wrdev, iclass 26, count 0 2006.173.15:50:42.48#ibcon#first serial, iclass 26, count 0 2006.173.15:50:42.48#ibcon#enter sib2, iclass 26, count 0 2006.173.15:50:42.48#ibcon#flushed, iclass 26, count 0 2006.173.15:50:42.48#ibcon#about to write, iclass 26, count 0 2006.173.15:50:42.48#ibcon#wrote, iclass 26, count 0 2006.173.15:50:42.48#ibcon#about to read 3, iclass 26, count 0 2006.173.15:50:42.50#ibcon#read 3, iclass 26, count 0 2006.173.15:50:42.50#ibcon#about to read 4, iclass 26, count 0 2006.173.15:50:42.50#ibcon#read 4, iclass 26, count 0 2006.173.15:50:42.50#ibcon#about to read 5, iclass 26, count 0 2006.173.15:50:42.50#ibcon#read 5, iclass 26, count 0 2006.173.15:50:42.50#ibcon#about to read 6, iclass 26, count 0 2006.173.15:50:42.50#ibcon#read 6, iclass 26, count 0 2006.173.15:50:42.50#ibcon#end of sib2, iclass 26, count 0 2006.173.15:50:42.50#ibcon#*mode == 0, iclass 26, count 0 2006.173.15:50:42.50#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.15:50:42.50#ibcon#[27=USB\r\n] 2006.173.15:50:42.50#ibcon#*before write, iclass 26, count 0 2006.173.15:50:42.50#ibcon#enter sib2, iclass 26, count 0 2006.173.15:50:42.50#ibcon#flushed, iclass 26, count 0 2006.173.15:50:42.50#ibcon#about to write, iclass 26, count 0 2006.173.15:50:42.50#ibcon#wrote, iclass 26, count 0 2006.173.15:50:42.50#ibcon#about to read 3, iclass 26, count 0 2006.173.15:50:42.53#ibcon#read 3, iclass 26, count 0 2006.173.15:50:42.53#ibcon#about to read 4, iclass 26, count 0 2006.173.15:50:42.53#ibcon#read 4, iclass 26, count 0 2006.173.15:50:42.53#ibcon#about to read 5, iclass 26, count 0 2006.173.15:50:42.53#ibcon#read 5, iclass 26, count 0 2006.173.15:50:42.53#ibcon#about to read 6, iclass 26, count 0 2006.173.15:50:42.53#ibcon#read 6, iclass 26, count 0 2006.173.15:50:42.53#ibcon#end of sib2, iclass 26, count 0 2006.173.15:50:42.53#ibcon#*after write, iclass 26, count 0 2006.173.15:50:42.53#ibcon#*before return 0, iclass 26, count 0 2006.173.15:50:42.53#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.15:50:42.53#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.15:50:42.53#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.15:50:42.53#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.15:50:42.53$vck44/vblo=3,649.99 2006.173.15:50:42.53#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.15:50:42.53#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.15:50:42.53#ibcon#ireg 17 cls_cnt 0 2006.173.15:50:42.53#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.15:50:42.53#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.15:50:42.53#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.15:50:42.53#ibcon#enter wrdev, iclass 28, count 0 2006.173.15:50:42.53#ibcon#first serial, iclass 28, count 0 2006.173.15:50:42.53#ibcon#enter sib2, iclass 28, count 0 2006.173.15:50:42.53#ibcon#flushed, iclass 28, count 0 2006.173.15:50:42.53#ibcon#about to write, iclass 28, count 0 2006.173.15:50:42.53#ibcon#wrote, iclass 28, count 0 2006.173.15:50:42.53#ibcon#about to read 3, iclass 28, count 0 2006.173.15:50:42.55#ibcon#read 3, iclass 28, count 0 2006.173.15:50:42.55#ibcon#about to read 4, iclass 28, count 0 2006.173.15:50:42.55#ibcon#read 4, iclass 28, count 0 2006.173.15:50:42.55#ibcon#about to read 5, iclass 28, count 0 2006.173.15:50:42.55#ibcon#read 5, iclass 28, count 0 2006.173.15:50:42.55#ibcon#about to read 6, iclass 28, count 0 2006.173.15:50:42.55#ibcon#read 6, iclass 28, count 0 2006.173.15:50:42.55#ibcon#end of sib2, iclass 28, count 0 2006.173.15:50:42.55#ibcon#*mode == 0, iclass 28, count 0 2006.173.15:50:42.55#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.15:50:42.55#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.15:50:42.55#ibcon#*before write, iclass 28, count 0 2006.173.15:50:42.55#ibcon#enter sib2, iclass 28, count 0 2006.173.15:50:42.55#ibcon#flushed, iclass 28, count 0 2006.173.15:50:42.55#ibcon#about to write, iclass 28, count 0 2006.173.15:50:42.55#ibcon#wrote, iclass 28, count 0 2006.173.15:50:42.55#ibcon#about to read 3, iclass 28, count 0 2006.173.15:50:42.59#ibcon#read 3, iclass 28, count 0 2006.173.15:50:42.59#ibcon#about to read 4, iclass 28, count 0 2006.173.15:50:42.59#ibcon#read 4, iclass 28, count 0 2006.173.15:50:42.59#ibcon#about to read 5, iclass 28, count 0 2006.173.15:50:42.59#ibcon#read 5, iclass 28, count 0 2006.173.15:50:42.59#ibcon#about to read 6, iclass 28, count 0 2006.173.15:50:42.59#ibcon#read 6, iclass 28, count 0 2006.173.15:50:42.59#ibcon#end of sib2, iclass 28, count 0 2006.173.15:50:42.59#ibcon#*after write, iclass 28, count 0 2006.173.15:50:42.59#ibcon#*before return 0, iclass 28, count 0 2006.173.15:50:42.59#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.15:50:42.59#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.15:50:42.59#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.15:50:42.59#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.15:50:42.59$vck44/vb=3,4 2006.173.15:50:42.59#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.15:50:42.59#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.15:50:42.59#ibcon#ireg 11 cls_cnt 2 2006.173.15:50:42.59#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.15:50:42.65#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.15:50:42.65#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.15:50:42.65#ibcon#enter wrdev, iclass 30, count 2 2006.173.15:50:42.65#ibcon#first serial, iclass 30, count 2 2006.173.15:50:42.65#ibcon#enter sib2, iclass 30, count 2 2006.173.15:50:42.65#ibcon#flushed, iclass 30, count 2 2006.173.15:50:42.65#ibcon#about to write, iclass 30, count 2 2006.173.15:50:42.65#ibcon#wrote, iclass 30, count 2 2006.173.15:50:42.65#ibcon#about to read 3, iclass 30, count 2 2006.173.15:50:42.67#ibcon#read 3, iclass 30, count 2 2006.173.15:50:42.67#ibcon#about to read 4, iclass 30, count 2 2006.173.15:50:42.67#ibcon#read 4, iclass 30, count 2 2006.173.15:50:42.67#ibcon#about to read 5, iclass 30, count 2 2006.173.15:50:42.67#ibcon#read 5, iclass 30, count 2 2006.173.15:50:42.67#ibcon#about to read 6, iclass 30, count 2 2006.173.15:50:42.67#ibcon#read 6, iclass 30, count 2 2006.173.15:50:42.67#ibcon#end of sib2, iclass 30, count 2 2006.173.15:50:42.67#ibcon#*mode == 0, iclass 30, count 2 2006.173.15:50:42.67#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.15:50:42.67#ibcon#[27=AT03-04\r\n] 2006.173.15:50:42.67#ibcon#*before write, iclass 30, count 2 2006.173.15:50:42.67#ibcon#enter sib2, iclass 30, count 2 2006.173.15:50:42.67#ibcon#flushed, iclass 30, count 2 2006.173.15:50:42.67#ibcon#about to write, iclass 30, count 2 2006.173.15:50:42.67#ibcon#wrote, iclass 30, count 2 2006.173.15:50:42.67#ibcon#about to read 3, iclass 30, count 2 2006.173.15:50:42.70#ibcon#read 3, iclass 30, count 2 2006.173.15:50:42.70#ibcon#about to read 4, iclass 30, count 2 2006.173.15:50:42.70#ibcon#read 4, iclass 30, count 2 2006.173.15:50:42.70#ibcon#about to read 5, iclass 30, count 2 2006.173.15:50:42.70#ibcon#read 5, iclass 30, count 2 2006.173.15:50:42.70#ibcon#about to read 6, iclass 30, count 2 2006.173.15:50:42.70#ibcon#read 6, iclass 30, count 2 2006.173.15:50:42.70#ibcon#end of sib2, iclass 30, count 2 2006.173.15:50:42.70#ibcon#*after write, iclass 30, count 2 2006.173.15:50:42.70#ibcon#*before return 0, iclass 30, count 2 2006.173.15:50:42.70#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.15:50:42.70#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.15:50:42.70#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.15:50:42.70#ibcon#ireg 7 cls_cnt 0 2006.173.15:50:42.70#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.15:50:42.82#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.15:50:42.82#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.15:50:42.82#ibcon#enter wrdev, iclass 30, count 0 2006.173.15:50:42.82#ibcon#first serial, iclass 30, count 0 2006.173.15:50:42.82#ibcon#enter sib2, iclass 30, count 0 2006.173.15:50:42.82#ibcon#flushed, iclass 30, count 0 2006.173.15:50:42.82#ibcon#about to write, iclass 30, count 0 2006.173.15:50:42.82#ibcon#wrote, iclass 30, count 0 2006.173.15:50:42.82#ibcon#about to read 3, iclass 30, count 0 2006.173.15:50:42.84#ibcon#read 3, iclass 30, count 0 2006.173.15:50:42.84#ibcon#about to read 4, iclass 30, count 0 2006.173.15:50:42.84#ibcon#read 4, iclass 30, count 0 2006.173.15:50:42.84#ibcon#about to read 5, iclass 30, count 0 2006.173.15:50:42.84#ibcon#read 5, iclass 30, count 0 2006.173.15:50:42.84#ibcon#about to read 6, iclass 30, count 0 2006.173.15:50:42.84#ibcon#read 6, iclass 30, count 0 2006.173.15:50:42.84#ibcon#end of sib2, iclass 30, count 0 2006.173.15:50:42.84#ibcon#*mode == 0, iclass 30, count 0 2006.173.15:50:42.84#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.15:50:42.84#ibcon#[27=USB\r\n] 2006.173.15:50:42.84#ibcon#*before write, iclass 30, count 0 2006.173.15:50:42.84#ibcon#enter sib2, iclass 30, count 0 2006.173.15:50:42.84#ibcon#flushed, iclass 30, count 0 2006.173.15:50:42.84#ibcon#about to write, iclass 30, count 0 2006.173.15:50:42.84#ibcon#wrote, iclass 30, count 0 2006.173.15:50:42.84#ibcon#about to read 3, iclass 30, count 0 2006.173.15:50:42.87#ibcon#read 3, iclass 30, count 0 2006.173.15:50:42.87#ibcon#about to read 4, iclass 30, count 0 2006.173.15:50:42.87#ibcon#read 4, iclass 30, count 0 2006.173.15:50:42.87#ibcon#about to read 5, iclass 30, count 0 2006.173.15:50:42.87#ibcon#read 5, iclass 30, count 0 2006.173.15:50:42.87#ibcon#about to read 6, iclass 30, count 0 2006.173.15:50:42.87#ibcon#read 6, iclass 30, count 0 2006.173.15:50:42.87#ibcon#end of sib2, iclass 30, count 0 2006.173.15:50:42.87#ibcon#*after write, iclass 30, count 0 2006.173.15:50:42.87#ibcon#*before return 0, iclass 30, count 0 2006.173.15:50:42.87#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.15:50:42.87#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.15:50:42.87#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.15:50:42.87#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.15:50:42.87$vck44/vblo=4,679.99 2006.173.15:50:42.87#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.15:50:42.87#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.15:50:42.87#ibcon#ireg 17 cls_cnt 0 2006.173.15:50:42.87#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.15:50:42.87#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.15:50:42.87#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.15:50:42.87#ibcon#enter wrdev, iclass 32, count 0 2006.173.15:50:42.87#ibcon#first serial, iclass 32, count 0 2006.173.15:50:42.87#ibcon#enter sib2, iclass 32, count 0 2006.173.15:50:42.87#ibcon#flushed, iclass 32, count 0 2006.173.15:50:42.87#ibcon#about to write, iclass 32, count 0 2006.173.15:50:42.87#ibcon#wrote, iclass 32, count 0 2006.173.15:50:42.87#ibcon#about to read 3, iclass 32, count 0 2006.173.15:50:42.89#ibcon#read 3, iclass 32, count 0 2006.173.15:50:42.89#ibcon#about to read 4, iclass 32, count 0 2006.173.15:50:42.89#ibcon#read 4, iclass 32, count 0 2006.173.15:50:42.89#ibcon#about to read 5, iclass 32, count 0 2006.173.15:50:42.89#ibcon#read 5, iclass 32, count 0 2006.173.15:50:42.89#ibcon#about to read 6, iclass 32, count 0 2006.173.15:50:42.89#ibcon#read 6, iclass 32, count 0 2006.173.15:50:42.89#ibcon#end of sib2, iclass 32, count 0 2006.173.15:50:42.89#ibcon#*mode == 0, iclass 32, count 0 2006.173.15:50:42.89#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.15:50:42.89#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.15:50:42.89#ibcon#*before write, iclass 32, count 0 2006.173.15:50:42.89#ibcon#enter sib2, iclass 32, count 0 2006.173.15:50:42.89#ibcon#flushed, iclass 32, count 0 2006.173.15:50:42.89#ibcon#about to write, iclass 32, count 0 2006.173.15:50:42.89#ibcon#wrote, iclass 32, count 0 2006.173.15:50:42.89#ibcon#about to read 3, iclass 32, count 0 2006.173.15:50:42.93#ibcon#read 3, iclass 32, count 0 2006.173.15:50:42.93#ibcon#about to read 4, iclass 32, count 0 2006.173.15:50:42.93#ibcon#read 4, iclass 32, count 0 2006.173.15:50:42.93#ibcon#about to read 5, iclass 32, count 0 2006.173.15:50:42.93#ibcon#read 5, iclass 32, count 0 2006.173.15:50:42.93#ibcon#about to read 6, iclass 32, count 0 2006.173.15:50:42.93#ibcon#read 6, iclass 32, count 0 2006.173.15:50:42.93#ibcon#end of sib2, iclass 32, count 0 2006.173.15:50:42.93#ibcon#*after write, iclass 32, count 0 2006.173.15:50:42.93#ibcon#*before return 0, iclass 32, count 0 2006.173.15:50:42.93#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.15:50:42.93#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.15:50:42.93#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.15:50:42.93#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.15:50:42.93$vck44/vb=4,4 2006.173.15:50:42.93#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.15:50:42.93#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.15:50:42.93#ibcon#ireg 11 cls_cnt 2 2006.173.15:50:42.93#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.15:50:42.99#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.15:50:42.99#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.15:50:42.99#ibcon#enter wrdev, iclass 34, count 2 2006.173.15:50:42.99#ibcon#first serial, iclass 34, count 2 2006.173.15:50:42.99#ibcon#enter sib2, iclass 34, count 2 2006.173.15:50:42.99#ibcon#flushed, iclass 34, count 2 2006.173.15:50:42.99#ibcon#about to write, iclass 34, count 2 2006.173.15:50:42.99#ibcon#wrote, iclass 34, count 2 2006.173.15:50:42.99#ibcon#about to read 3, iclass 34, count 2 2006.173.15:50:43.01#ibcon#read 3, iclass 34, count 2 2006.173.15:50:43.01#ibcon#about to read 4, iclass 34, count 2 2006.173.15:50:43.01#ibcon#read 4, iclass 34, count 2 2006.173.15:50:43.01#ibcon#about to read 5, iclass 34, count 2 2006.173.15:50:43.01#ibcon#read 5, iclass 34, count 2 2006.173.15:50:43.01#ibcon#about to read 6, iclass 34, count 2 2006.173.15:50:43.01#ibcon#read 6, iclass 34, count 2 2006.173.15:50:43.01#ibcon#end of sib2, iclass 34, count 2 2006.173.15:50:43.01#ibcon#*mode == 0, iclass 34, count 2 2006.173.15:50:43.01#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.15:50:43.01#ibcon#[27=AT04-04\r\n] 2006.173.15:50:43.01#ibcon#*before write, iclass 34, count 2 2006.173.15:50:43.01#ibcon#enter sib2, iclass 34, count 2 2006.173.15:50:43.01#ibcon#flushed, iclass 34, count 2 2006.173.15:50:43.01#ibcon#about to write, iclass 34, count 2 2006.173.15:50:43.01#ibcon#wrote, iclass 34, count 2 2006.173.15:50:43.01#ibcon#about to read 3, iclass 34, count 2 2006.173.15:50:43.04#ibcon#read 3, iclass 34, count 2 2006.173.15:50:43.04#ibcon#about to read 4, iclass 34, count 2 2006.173.15:50:43.04#ibcon#read 4, iclass 34, count 2 2006.173.15:50:43.04#ibcon#about to read 5, iclass 34, count 2 2006.173.15:50:43.04#ibcon#read 5, iclass 34, count 2 2006.173.15:50:43.04#ibcon#about to read 6, iclass 34, count 2 2006.173.15:50:43.04#ibcon#read 6, iclass 34, count 2 2006.173.15:50:43.04#ibcon#end of sib2, iclass 34, count 2 2006.173.15:50:43.04#ibcon#*after write, iclass 34, count 2 2006.173.15:50:43.04#ibcon#*before return 0, iclass 34, count 2 2006.173.15:50:43.04#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.15:50:43.04#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.15:50:43.04#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.15:50:43.04#ibcon#ireg 7 cls_cnt 0 2006.173.15:50:43.04#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.15:50:43.16#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.15:50:43.16#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.15:50:43.16#ibcon#enter wrdev, iclass 34, count 0 2006.173.15:50:43.16#ibcon#first serial, iclass 34, count 0 2006.173.15:50:43.16#ibcon#enter sib2, iclass 34, count 0 2006.173.15:50:43.16#ibcon#flushed, iclass 34, count 0 2006.173.15:50:43.16#ibcon#about to write, iclass 34, count 0 2006.173.15:50:43.16#ibcon#wrote, iclass 34, count 0 2006.173.15:50:43.16#ibcon#about to read 3, iclass 34, count 0 2006.173.15:50:43.18#ibcon#read 3, iclass 34, count 0 2006.173.15:50:43.18#ibcon#about to read 4, iclass 34, count 0 2006.173.15:50:43.18#ibcon#read 4, iclass 34, count 0 2006.173.15:50:43.18#ibcon#about to read 5, iclass 34, count 0 2006.173.15:50:43.18#ibcon#read 5, iclass 34, count 0 2006.173.15:50:43.18#ibcon#about to read 6, iclass 34, count 0 2006.173.15:50:43.18#ibcon#read 6, iclass 34, count 0 2006.173.15:50:43.18#ibcon#end of sib2, iclass 34, count 0 2006.173.15:50:43.18#ibcon#*mode == 0, iclass 34, count 0 2006.173.15:50:43.18#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.15:50:43.18#ibcon#[27=USB\r\n] 2006.173.15:50:43.18#ibcon#*before write, iclass 34, count 0 2006.173.15:50:43.18#ibcon#enter sib2, iclass 34, count 0 2006.173.15:50:43.18#ibcon#flushed, iclass 34, count 0 2006.173.15:50:43.18#ibcon#about to write, iclass 34, count 0 2006.173.15:50:43.18#ibcon#wrote, iclass 34, count 0 2006.173.15:50:43.18#ibcon#about to read 3, iclass 34, count 0 2006.173.15:50:43.21#ibcon#read 3, iclass 34, count 0 2006.173.15:50:43.21#ibcon#about to read 4, iclass 34, count 0 2006.173.15:50:43.21#ibcon#read 4, iclass 34, count 0 2006.173.15:50:43.21#ibcon#about to read 5, iclass 34, count 0 2006.173.15:50:43.21#ibcon#read 5, iclass 34, count 0 2006.173.15:50:43.21#ibcon#about to read 6, iclass 34, count 0 2006.173.15:50:43.21#ibcon#read 6, iclass 34, count 0 2006.173.15:50:43.21#ibcon#end of sib2, iclass 34, count 0 2006.173.15:50:43.21#ibcon#*after write, iclass 34, count 0 2006.173.15:50:43.21#ibcon#*before return 0, iclass 34, count 0 2006.173.15:50:43.21#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.15:50:43.21#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.15:50:43.21#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.15:50:43.21#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.15:50:43.21$vck44/vblo=5,709.99 2006.173.15:50:43.21#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.15:50:43.21#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.15:50:43.21#ibcon#ireg 17 cls_cnt 0 2006.173.15:50:43.21#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.15:50:43.21#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.15:50:43.21#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.15:50:43.21#ibcon#enter wrdev, iclass 36, count 0 2006.173.15:50:43.21#ibcon#first serial, iclass 36, count 0 2006.173.15:50:43.21#ibcon#enter sib2, iclass 36, count 0 2006.173.15:50:43.21#ibcon#flushed, iclass 36, count 0 2006.173.15:50:43.21#ibcon#about to write, iclass 36, count 0 2006.173.15:50:43.21#ibcon#wrote, iclass 36, count 0 2006.173.15:50:43.21#ibcon#about to read 3, iclass 36, count 0 2006.173.15:50:43.23#ibcon#read 3, iclass 36, count 0 2006.173.15:50:43.23#ibcon#about to read 4, iclass 36, count 0 2006.173.15:50:43.23#ibcon#read 4, iclass 36, count 0 2006.173.15:50:43.23#ibcon#about to read 5, iclass 36, count 0 2006.173.15:50:43.23#ibcon#read 5, iclass 36, count 0 2006.173.15:50:43.23#ibcon#about to read 6, iclass 36, count 0 2006.173.15:50:43.23#ibcon#read 6, iclass 36, count 0 2006.173.15:50:43.23#ibcon#end of sib2, iclass 36, count 0 2006.173.15:50:43.23#ibcon#*mode == 0, iclass 36, count 0 2006.173.15:50:43.23#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.15:50:43.23#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.15:50:43.23#ibcon#*before write, iclass 36, count 0 2006.173.15:50:43.23#ibcon#enter sib2, iclass 36, count 0 2006.173.15:50:43.23#ibcon#flushed, iclass 36, count 0 2006.173.15:50:43.23#ibcon#about to write, iclass 36, count 0 2006.173.15:50:43.23#ibcon#wrote, iclass 36, count 0 2006.173.15:50:43.23#ibcon#about to read 3, iclass 36, count 0 2006.173.15:50:43.27#ibcon#read 3, iclass 36, count 0 2006.173.15:50:43.27#ibcon#about to read 4, iclass 36, count 0 2006.173.15:50:43.27#ibcon#read 4, iclass 36, count 0 2006.173.15:50:43.27#ibcon#about to read 5, iclass 36, count 0 2006.173.15:50:43.27#ibcon#read 5, iclass 36, count 0 2006.173.15:50:43.27#ibcon#about to read 6, iclass 36, count 0 2006.173.15:50:43.27#ibcon#read 6, iclass 36, count 0 2006.173.15:50:43.27#ibcon#end of sib2, iclass 36, count 0 2006.173.15:50:43.27#ibcon#*after write, iclass 36, count 0 2006.173.15:50:43.27#ibcon#*before return 0, iclass 36, count 0 2006.173.15:50:43.27#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.15:50:43.27#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.15:50:43.27#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.15:50:43.27#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.15:50:43.27$vck44/vb=5,4 2006.173.15:50:43.27#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.15:50:43.27#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.15:50:43.27#ibcon#ireg 11 cls_cnt 2 2006.173.15:50:43.27#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.15:50:43.33#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.15:50:43.33#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.15:50:43.33#ibcon#enter wrdev, iclass 38, count 2 2006.173.15:50:43.33#ibcon#first serial, iclass 38, count 2 2006.173.15:50:43.33#ibcon#enter sib2, iclass 38, count 2 2006.173.15:50:43.33#ibcon#flushed, iclass 38, count 2 2006.173.15:50:43.33#ibcon#about to write, iclass 38, count 2 2006.173.15:50:43.33#ibcon#wrote, iclass 38, count 2 2006.173.15:50:43.33#ibcon#about to read 3, iclass 38, count 2 2006.173.15:50:43.35#ibcon#read 3, iclass 38, count 2 2006.173.15:50:43.35#ibcon#about to read 4, iclass 38, count 2 2006.173.15:50:43.35#ibcon#read 4, iclass 38, count 2 2006.173.15:50:43.35#ibcon#about to read 5, iclass 38, count 2 2006.173.15:50:43.35#ibcon#read 5, iclass 38, count 2 2006.173.15:50:43.35#ibcon#about to read 6, iclass 38, count 2 2006.173.15:50:43.35#ibcon#read 6, iclass 38, count 2 2006.173.15:50:43.35#ibcon#end of sib2, iclass 38, count 2 2006.173.15:50:43.35#ibcon#*mode == 0, iclass 38, count 2 2006.173.15:50:43.35#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.15:50:43.35#ibcon#[27=AT05-04\r\n] 2006.173.15:50:43.35#ibcon#*before write, iclass 38, count 2 2006.173.15:50:43.35#ibcon#enter sib2, iclass 38, count 2 2006.173.15:50:43.35#ibcon#flushed, iclass 38, count 2 2006.173.15:50:43.35#ibcon#about to write, iclass 38, count 2 2006.173.15:50:43.35#ibcon#wrote, iclass 38, count 2 2006.173.15:50:43.35#ibcon#about to read 3, iclass 38, count 2 2006.173.15:50:43.38#ibcon#read 3, iclass 38, count 2 2006.173.15:50:43.38#ibcon#about to read 4, iclass 38, count 2 2006.173.15:50:43.38#ibcon#read 4, iclass 38, count 2 2006.173.15:50:43.38#ibcon#about to read 5, iclass 38, count 2 2006.173.15:50:43.38#ibcon#read 5, iclass 38, count 2 2006.173.15:50:43.38#ibcon#about to read 6, iclass 38, count 2 2006.173.15:50:43.38#ibcon#read 6, iclass 38, count 2 2006.173.15:50:43.38#ibcon#end of sib2, iclass 38, count 2 2006.173.15:50:43.38#ibcon#*after write, iclass 38, count 2 2006.173.15:50:43.38#ibcon#*before return 0, iclass 38, count 2 2006.173.15:50:43.38#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.15:50:43.38#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.15:50:43.38#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.15:50:43.38#ibcon#ireg 7 cls_cnt 0 2006.173.15:50:43.38#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.15:50:43.50#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.15:50:43.50#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.15:50:43.50#ibcon#enter wrdev, iclass 38, count 0 2006.173.15:50:43.50#ibcon#first serial, iclass 38, count 0 2006.173.15:50:43.50#ibcon#enter sib2, iclass 38, count 0 2006.173.15:50:43.50#ibcon#flushed, iclass 38, count 0 2006.173.15:50:43.50#ibcon#about to write, iclass 38, count 0 2006.173.15:50:43.50#ibcon#wrote, iclass 38, count 0 2006.173.15:50:43.50#ibcon#about to read 3, iclass 38, count 0 2006.173.15:50:43.52#ibcon#read 3, iclass 38, count 0 2006.173.15:50:43.52#ibcon#about to read 4, iclass 38, count 0 2006.173.15:50:43.52#ibcon#read 4, iclass 38, count 0 2006.173.15:50:43.52#ibcon#about to read 5, iclass 38, count 0 2006.173.15:50:43.52#ibcon#read 5, iclass 38, count 0 2006.173.15:50:43.52#ibcon#about to read 6, iclass 38, count 0 2006.173.15:50:43.52#ibcon#read 6, iclass 38, count 0 2006.173.15:50:43.52#ibcon#end of sib2, iclass 38, count 0 2006.173.15:50:43.52#ibcon#*mode == 0, iclass 38, count 0 2006.173.15:50:43.52#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.15:50:43.52#ibcon#[27=USB\r\n] 2006.173.15:50:43.52#ibcon#*before write, iclass 38, count 0 2006.173.15:50:43.52#ibcon#enter sib2, iclass 38, count 0 2006.173.15:50:43.52#ibcon#flushed, iclass 38, count 0 2006.173.15:50:43.52#ibcon#about to write, iclass 38, count 0 2006.173.15:50:43.52#ibcon#wrote, iclass 38, count 0 2006.173.15:50:43.52#ibcon#about to read 3, iclass 38, count 0 2006.173.15:50:43.55#ibcon#read 3, iclass 38, count 0 2006.173.15:50:43.55#ibcon#about to read 4, iclass 38, count 0 2006.173.15:50:43.55#ibcon#read 4, iclass 38, count 0 2006.173.15:50:43.55#ibcon#about to read 5, iclass 38, count 0 2006.173.15:50:43.55#ibcon#read 5, iclass 38, count 0 2006.173.15:50:43.55#ibcon#about to read 6, iclass 38, count 0 2006.173.15:50:43.55#ibcon#read 6, iclass 38, count 0 2006.173.15:50:43.55#ibcon#end of sib2, iclass 38, count 0 2006.173.15:50:43.55#ibcon#*after write, iclass 38, count 0 2006.173.15:50:43.55#ibcon#*before return 0, iclass 38, count 0 2006.173.15:50:43.55#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.15:50:43.55#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.15:50:43.55#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.15:50:43.55#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.15:50:43.55$vck44/vblo=6,719.99 2006.173.15:50:43.55#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.15:50:43.55#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.15:50:43.55#ibcon#ireg 17 cls_cnt 0 2006.173.15:50:43.55#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.15:50:43.55#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.15:50:43.55#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.15:50:43.55#ibcon#enter wrdev, iclass 40, count 0 2006.173.15:50:43.55#ibcon#first serial, iclass 40, count 0 2006.173.15:50:43.55#ibcon#enter sib2, iclass 40, count 0 2006.173.15:50:43.55#ibcon#flushed, iclass 40, count 0 2006.173.15:50:43.55#ibcon#about to write, iclass 40, count 0 2006.173.15:50:43.55#ibcon#wrote, iclass 40, count 0 2006.173.15:50:43.55#ibcon#about to read 3, iclass 40, count 0 2006.173.15:50:43.57#ibcon#read 3, iclass 40, count 0 2006.173.15:50:43.57#ibcon#about to read 4, iclass 40, count 0 2006.173.15:50:43.57#ibcon#read 4, iclass 40, count 0 2006.173.15:50:43.57#ibcon#about to read 5, iclass 40, count 0 2006.173.15:50:43.57#ibcon#read 5, iclass 40, count 0 2006.173.15:50:43.57#ibcon#about to read 6, iclass 40, count 0 2006.173.15:50:43.57#ibcon#read 6, iclass 40, count 0 2006.173.15:50:43.57#ibcon#end of sib2, iclass 40, count 0 2006.173.15:50:43.57#ibcon#*mode == 0, iclass 40, count 0 2006.173.15:50:43.57#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.15:50:43.57#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.15:50:43.57#ibcon#*before write, iclass 40, count 0 2006.173.15:50:43.57#ibcon#enter sib2, iclass 40, count 0 2006.173.15:50:43.57#ibcon#flushed, iclass 40, count 0 2006.173.15:50:43.57#ibcon#about to write, iclass 40, count 0 2006.173.15:50:43.57#ibcon#wrote, iclass 40, count 0 2006.173.15:50:43.57#ibcon#about to read 3, iclass 40, count 0 2006.173.15:50:43.61#ibcon#read 3, iclass 40, count 0 2006.173.15:50:43.61#ibcon#about to read 4, iclass 40, count 0 2006.173.15:50:43.61#ibcon#read 4, iclass 40, count 0 2006.173.15:50:43.61#ibcon#about to read 5, iclass 40, count 0 2006.173.15:50:43.61#ibcon#read 5, iclass 40, count 0 2006.173.15:50:43.61#ibcon#about to read 6, iclass 40, count 0 2006.173.15:50:43.61#ibcon#read 6, iclass 40, count 0 2006.173.15:50:43.61#ibcon#end of sib2, iclass 40, count 0 2006.173.15:50:43.61#ibcon#*after write, iclass 40, count 0 2006.173.15:50:43.61#ibcon#*before return 0, iclass 40, count 0 2006.173.15:50:43.61#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.15:50:43.61#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.15:50:43.61#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.15:50:43.61#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.15:50:43.61$vck44/vb=6,4 2006.173.15:50:43.61#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.15:50:43.61#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.15:50:43.61#ibcon#ireg 11 cls_cnt 2 2006.173.15:50:43.61#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.15:50:43.67#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.15:50:43.67#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.15:50:43.67#ibcon#enter wrdev, iclass 4, count 2 2006.173.15:50:43.67#ibcon#first serial, iclass 4, count 2 2006.173.15:50:43.67#ibcon#enter sib2, iclass 4, count 2 2006.173.15:50:43.67#ibcon#flushed, iclass 4, count 2 2006.173.15:50:43.67#ibcon#about to write, iclass 4, count 2 2006.173.15:50:43.67#ibcon#wrote, iclass 4, count 2 2006.173.15:50:43.67#ibcon#about to read 3, iclass 4, count 2 2006.173.15:50:43.69#ibcon#read 3, iclass 4, count 2 2006.173.15:50:43.69#ibcon#about to read 4, iclass 4, count 2 2006.173.15:50:43.69#ibcon#read 4, iclass 4, count 2 2006.173.15:50:43.69#ibcon#about to read 5, iclass 4, count 2 2006.173.15:50:43.69#ibcon#read 5, iclass 4, count 2 2006.173.15:50:43.69#ibcon#about to read 6, iclass 4, count 2 2006.173.15:50:43.69#ibcon#read 6, iclass 4, count 2 2006.173.15:50:43.69#ibcon#end of sib2, iclass 4, count 2 2006.173.15:50:43.69#ibcon#*mode == 0, iclass 4, count 2 2006.173.15:50:43.69#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.15:50:43.69#ibcon#[27=AT06-04\r\n] 2006.173.15:50:43.69#ibcon#*before write, iclass 4, count 2 2006.173.15:50:43.69#ibcon#enter sib2, iclass 4, count 2 2006.173.15:50:43.69#ibcon#flushed, iclass 4, count 2 2006.173.15:50:43.69#ibcon#about to write, iclass 4, count 2 2006.173.15:50:43.69#ibcon#wrote, iclass 4, count 2 2006.173.15:50:43.69#ibcon#about to read 3, iclass 4, count 2 2006.173.15:50:43.72#ibcon#read 3, iclass 4, count 2 2006.173.15:50:43.72#ibcon#about to read 4, iclass 4, count 2 2006.173.15:50:43.72#ibcon#read 4, iclass 4, count 2 2006.173.15:50:43.72#ibcon#about to read 5, iclass 4, count 2 2006.173.15:50:43.72#ibcon#read 5, iclass 4, count 2 2006.173.15:50:43.72#ibcon#about to read 6, iclass 4, count 2 2006.173.15:50:43.72#ibcon#read 6, iclass 4, count 2 2006.173.15:50:43.72#ibcon#end of sib2, iclass 4, count 2 2006.173.15:50:43.72#ibcon#*after write, iclass 4, count 2 2006.173.15:50:43.72#ibcon#*before return 0, iclass 4, count 2 2006.173.15:50:43.72#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.15:50:43.72#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.15:50:43.72#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.15:50:43.72#ibcon#ireg 7 cls_cnt 0 2006.173.15:50:43.72#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.15:50:43.84#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.15:50:43.84#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.15:50:43.84#ibcon#enter wrdev, iclass 4, count 0 2006.173.15:50:43.84#ibcon#first serial, iclass 4, count 0 2006.173.15:50:43.84#ibcon#enter sib2, iclass 4, count 0 2006.173.15:50:43.84#ibcon#flushed, iclass 4, count 0 2006.173.15:50:43.84#ibcon#about to write, iclass 4, count 0 2006.173.15:50:43.84#ibcon#wrote, iclass 4, count 0 2006.173.15:50:43.84#ibcon#about to read 3, iclass 4, count 0 2006.173.15:50:43.86#ibcon#read 3, iclass 4, count 0 2006.173.15:50:43.86#ibcon#about to read 4, iclass 4, count 0 2006.173.15:50:43.86#ibcon#read 4, iclass 4, count 0 2006.173.15:50:43.86#ibcon#about to read 5, iclass 4, count 0 2006.173.15:50:43.86#ibcon#read 5, iclass 4, count 0 2006.173.15:50:43.86#ibcon#about to read 6, iclass 4, count 0 2006.173.15:50:43.86#ibcon#read 6, iclass 4, count 0 2006.173.15:50:43.86#ibcon#end of sib2, iclass 4, count 0 2006.173.15:50:43.86#ibcon#*mode == 0, iclass 4, count 0 2006.173.15:50:43.86#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.15:50:43.86#ibcon#[27=USB\r\n] 2006.173.15:50:43.86#ibcon#*before write, iclass 4, count 0 2006.173.15:50:43.86#ibcon#enter sib2, iclass 4, count 0 2006.173.15:50:43.86#ibcon#flushed, iclass 4, count 0 2006.173.15:50:43.86#ibcon#about to write, iclass 4, count 0 2006.173.15:50:43.86#ibcon#wrote, iclass 4, count 0 2006.173.15:50:43.86#ibcon#about to read 3, iclass 4, count 0 2006.173.15:50:43.89#ibcon#read 3, iclass 4, count 0 2006.173.15:50:43.89#ibcon#about to read 4, iclass 4, count 0 2006.173.15:50:43.89#ibcon#read 4, iclass 4, count 0 2006.173.15:50:43.89#ibcon#about to read 5, iclass 4, count 0 2006.173.15:50:43.89#ibcon#read 5, iclass 4, count 0 2006.173.15:50:43.89#ibcon#about to read 6, iclass 4, count 0 2006.173.15:50:43.89#ibcon#read 6, iclass 4, count 0 2006.173.15:50:43.89#ibcon#end of sib2, iclass 4, count 0 2006.173.15:50:43.89#ibcon#*after write, iclass 4, count 0 2006.173.15:50:43.89#ibcon#*before return 0, iclass 4, count 0 2006.173.15:50:43.89#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.15:50:43.89#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.15:50:43.89#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.15:50:43.89#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.15:50:43.89$vck44/vblo=7,734.99 2006.173.15:50:43.89#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.15:50:43.89#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.15:50:43.89#ibcon#ireg 17 cls_cnt 0 2006.173.15:50:43.89#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.15:50:43.89#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.15:50:43.89#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.15:50:43.89#ibcon#enter wrdev, iclass 6, count 0 2006.173.15:50:43.89#ibcon#first serial, iclass 6, count 0 2006.173.15:50:43.89#ibcon#enter sib2, iclass 6, count 0 2006.173.15:50:43.89#ibcon#flushed, iclass 6, count 0 2006.173.15:50:43.89#ibcon#about to write, iclass 6, count 0 2006.173.15:50:43.89#ibcon#wrote, iclass 6, count 0 2006.173.15:50:43.89#ibcon#about to read 3, iclass 6, count 0 2006.173.15:50:43.91#ibcon#read 3, iclass 6, count 0 2006.173.15:50:43.91#ibcon#about to read 4, iclass 6, count 0 2006.173.15:50:43.91#ibcon#read 4, iclass 6, count 0 2006.173.15:50:43.91#ibcon#about to read 5, iclass 6, count 0 2006.173.15:50:43.91#ibcon#read 5, iclass 6, count 0 2006.173.15:50:43.91#ibcon#about to read 6, iclass 6, count 0 2006.173.15:50:43.91#ibcon#read 6, iclass 6, count 0 2006.173.15:50:43.91#ibcon#end of sib2, iclass 6, count 0 2006.173.15:50:43.91#ibcon#*mode == 0, iclass 6, count 0 2006.173.15:50:43.91#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.15:50:43.91#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.15:50:43.91#ibcon#*before write, iclass 6, count 0 2006.173.15:50:43.91#ibcon#enter sib2, iclass 6, count 0 2006.173.15:50:43.91#ibcon#flushed, iclass 6, count 0 2006.173.15:50:43.91#ibcon#about to write, iclass 6, count 0 2006.173.15:50:43.91#ibcon#wrote, iclass 6, count 0 2006.173.15:50:43.91#ibcon#about to read 3, iclass 6, count 0 2006.173.15:50:43.95#ibcon#read 3, iclass 6, count 0 2006.173.15:50:43.95#ibcon#about to read 4, iclass 6, count 0 2006.173.15:50:43.95#ibcon#read 4, iclass 6, count 0 2006.173.15:50:43.95#ibcon#about to read 5, iclass 6, count 0 2006.173.15:50:43.95#ibcon#read 5, iclass 6, count 0 2006.173.15:50:43.95#ibcon#about to read 6, iclass 6, count 0 2006.173.15:50:43.95#ibcon#read 6, iclass 6, count 0 2006.173.15:50:43.95#ibcon#end of sib2, iclass 6, count 0 2006.173.15:50:43.95#ibcon#*after write, iclass 6, count 0 2006.173.15:50:43.95#ibcon#*before return 0, iclass 6, count 0 2006.173.15:50:43.95#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.15:50:43.95#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.15:50:43.95#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.15:50:43.95#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.15:50:43.95$vck44/vb=7,4 2006.173.15:50:43.95#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.15:50:43.95#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.15:50:43.95#ibcon#ireg 11 cls_cnt 2 2006.173.15:50:43.95#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.15:50:44.01#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.15:50:44.01#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.15:50:44.01#ibcon#enter wrdev, iclass 10, count 2 2006.173.15:50:44.01#ibcon#first serial, iclass 10, count 2 2006.173.15:50:44.01#ibcon#enter sib2, iclass 10, count 2 2006.173.15:50:44.01#ibcon#flushed, iclass 10, count 2 2006.173.15:50:44.01#ibcon#about to write, iclass 10, count 2 2006.173.15:50:44.01#ibcon#wrote, iclass 10, count 2 2006.173.15:50:44.01#ibcon#about to read 3, iclass 10, count 2 2006.173.15:50:44.03#ibcon#read 3, iclass 10, count 2 2006.173.15:50:44.03#ibcon#about to read 4, iclass 10, count 2 2006.173.15:50:44.03#ibcon#read 4, iclass 10, count 2 2006.173.15:50:44.03#ibcon#about to read 5, iclass 10, count 2 2006.173.15:50:44.03#ibcon#read 5, iclass 10, count 2 2006.173.15:50:44.03#ibcon#about to read 6, iclass 10, count 2 2006.173.15:50:44.03#ibcon#read 6, iclass 10, count 2 2006.173.15:50:44.03#ibcon#end of sib2, iclass 10, count 2 2006.173.15:50:44.03#ibcon#*mode == 0, iclass 10, count 2 2006.173.15:50:44.03#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.15:50:44.03#ibcon#[27=AT07-04\r\n] 2006.173.15:50:44.03#ibcon#*before write, iclass 10, count 2 2006.173.15:50:44.03#ibcon#enter sib2, iclass 10, count 2 2006.173.15:50:44.03#ibcon#flushed, iclass 10, count 2 2006.173.15:50:44.03#ibcon#about to write, iclass 10, count 2 2006.173.15:50:44.03#ibcon#wrote, iclass 10, count 2 2006.173.15:50:44.03#ibcon#about to read 3, iclass 10, count 2 2006.173.15:50:44.06#ibcon#read 3, iclass 10, count 2 2006.173.15:50:44.06#ibcon#about to read 4, iclass 10, count 2 2006.173.15:50:44.06#ibcon#read 4, iclass 10, count 2 2006.173.15:50:44.06#ibcon#about to read 5, iclass 10, count 2 2006.173.15:50:44.06#ibcon#read 5, iclass 10, count 2 2006.173.15:50:44.06#ibcon#about to read 6, iclass 10, count 2 2006.173.15:50:44.06#ibcon#read 6, iclass 10, count 2 2006.173.15:50:44.06#ibcon#end of sib2, iclass 10, count 2 2006.173.15:50:44.06#ibcon#*after write, iclass 10, count 2 2006.173.15:50:44.06#ibcon#*before return 0, iclass 10, count 2 2006.173.15:50:44.06#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.15:50:44.06#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.15:50:44.06#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.15:50:44.06#ibcon#ireg 7 cls_cnt 0 2006.173.15:50:44.06#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.15:50:44.18#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.15:50:44.18#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.15:50:44.18#ibcon#enter wrdev, iclass 10, count 0 2006.173.15:50:44.18#ibcon#first serial, iclass 10, count 0 2006.173.15:50:44.18#ibcon#enter sib2, iclass 10, count 0 2006.173.15:50:44.18#ibcon#flushed, iclass 10, count 0 2006.173.15:50:44.18#ibcon#about to write, iclass 10, count 0 2006.173.15:50:44.18#ibcon#wrote, iclass 10, count 0 2006.173.15:50:44.18#ibcon#about to read 3, iclass 10, count 0 2006.173.15:50:44.20#ibcon#read 3, iclass 10, count 0 2006.173.15:50:44.20#ibcon#about to read 4, iclass 10, count 0 2006.173.15:50:44.20#ibcon#read 4, iclass 10, count 0 2006.173.15:50:44.20#ibcon#about to read 5, iclass 10, count 0 2006.173.15:50:44.20#ibcon#read 5, iclass 10, count 0 2006.173.15:50:44.20#ibcon#about to read 6, iclass 10, count 0 2006.173.15:50:44.20#ibcon#read 6, iclass 10, count 0 2006.173.15:50:44.20#ibcon#end of sib2, iclass 10, count 0 2006.173.15:50:44.20#ibcon#*mode == 0, iclass 10, count 0 2006.173.15:50:44.20#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.15:50:44.20#ibcon#[27=USB\r\n] 2006.173.15:50:44.20#ibcon#*before write, iclass 10, count 0 2006.173.15:50:44.20#ibcon#enter sib2, iclass 10, count 0 2006.173.15:50:44.20#ibcon#flushed, iclass 10, count 0 2006.173.15:50:44.20#ibcon#about to write, iclass 10, count 0 2006.173.15:50:44.20#ibcon#wrote, iclass 10, count 0 2006.173.15:50:44.20#ibcon#about to read 3, iclass 10, count 0 2006.173.15:50:44.23#ibcon#read 3, iclass 10, count 0 2006.173.15:50:44.23#ibcon#about to read 4, iclass 10, count 0 2006.173.15:50:44.23#ibcon#read 4, iclass 10, count 0 2006.173.15:50:44.23#ibcon#about to read 5, iclass 10, count 0 2006.173.15:50:44.23#ibcon#read 5, iclass 10, count 0 2006.173.15:50:44.23#ibcon#about to read 6, iclass 10, count 0 2006.173.15:50:44.23#ibcon#read 6, iclass 10, count 0 2006.173.15:50:44.23#ibcon#end of sib2, iclass 10, count 0 2006.173.15:50:44.23#ibcon#*after write, iclass 10, count 0 2006.173.15:50:44.23#ibcon#*before return 0, iclass 10, count 0 2006.173.15:50:44.23#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.15:50:44.23#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.15:50:44.23#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.15:50:44.23#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.15:50:44.23$vck44/vblo=8,744.99 2006.173.15:50:44.23#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.15:50:44.23#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.15:50:44.23#ibcon#ireg 17 cls_cnt 0 2006.173.15:50:44.23#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.15:50:44.23#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.15:50:44.23#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.15:50:44.23#ibcon#enter wrdev, iclass 12, count 0 2006.173.15:50:44.23#ibcon#first serial, iclass 12, count 0 2006.173.15:50:44.23#ibcon#enter sib2, iclass 12, count 0 2006.173.15:50:44.23#ibcon#flushed, iclass 12, count 0 2006.173.15:50:44.23#ibcon#about to write, iclass 12, count 0 2006.173.15:50:44.23#ibcon#wrote, iclass 12, count 0 2006.173.15:50:44.23#ibcon#about to read 3, iclass 12, count 0 2006.173.15:50:44.25#ibcon#read 3, iclass 12, count 0 2006.173.15:50:44.25#ibcon#about to read 4, iclass 12, count 0 2006.173.15:50:44.25#ibcon#read 4, iclass 12, count 0 2006.173.15:50:44.25#ibcon#about to read 5, iclass 12, count 0 2006.173.15:50:44.25#ibcon#read 5, iclass 12, count 0 2006.173.15:50:44.25#ibcon#about to read 6, iclass 12, count 0 2006.173.15:50:44.25#ibcon#read 6, iclass 12, count 0 2006.173.15:50:44.25#ibcon#end of sib2, iclass 12, count 0 2006.173.15:50:44.25#ibcon#*mode == 0, iclass 12, count 0 2006.173.15:50:44.25#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.15:50:44.25#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.15:50:44.25#ibcon#*before write, iclass 12, count 0 2006.173.15:50:44.25#ibcon#enter sib2, iclass 12, count 0 2006.173.15:50:44.25#ibcon#flushed, iclass 12, count 0 2006.173.15:50:44.25#ibcon#about to write, iclass 12, count 0 2006.173.15:50:44.25#ibcon#wrote, iclass 12, count 0 2006.173.15:50:44.25#ibcon#about to read 3, iclass 12, count 0 2006.173.15:50:44.29#ibcon#read 3, iclass 12, count 0 2006.173.15:50:44.29#ibcon#about to read 4, iclass 12, count 0 2006.173.15:50:44.29#ibcon#read 4, iclass 12, count 0 2006.173.15:50:44.29#ibcon#about to read 5, iclass 12, count 0 2006.173.15:50:44.29#ibcon#read 5, iclass 12, count 0 2006.173.15:50:44.29#ibcon#about to read 6, iclass 12, count 0 2006.173.15:50:44.29#ibcon#read 6, iclass 12, count 0 2006.173.15:50:44.29#ibcon#end of sib2, iclass 12, count 0 2006.173.15:50:44.29#ibcon#*after write, iclass 12, count 0 2006.173.15:50:44.29#ibcon#*before return 0, iclass 12, count 0 2006.173.15:50:44.29#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.15:50:44.29#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.15:50:44.29#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.15:50:44.29#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.15:50:44.29$vck44/vb=8,4 2006.173.15:50:44.29#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.15:50:44.29#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.15:50:44.29#ibcon#ireg 11 cls_cnt 2 2006.173.15:50:44.29#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.15:50:44.35#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.15:50:44.35#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.15:50:44.35#ibcon#enter wrdev, iclass 14, count 2 2006.173.15:50:44.35#ibcon#first serial, iclass 14, count 2 2006.173.15:50:44.35#ibcon#enter sib2, iclass 14, count 2 2006.173.15:50:44.35#ibcon#flushed, iclass 14, count 2 2006.173.15:50:44.35#ibcon#about to write, iclass 14, count 2 2006.173.15:50:44.35#ibcon#wrote, iclass 14, count 2 2006.173.15:50:44.35#ibcon#about to read 3, iclass 14, count 2 2006.173.15:50:44.37#ibcon#read 3, iclass 14, count 2 2006.173.15:50:44.37#ibcon#about to read 4, iclass 14, count 2 2006.173.15:50:44.37#ibcon#read 4, iclass 14, count 2 2006.173.15:50:44.37#ibcon#about to read 5, iclass 14, count 2 2006.173.15:50:44.37#ibcon#read 5, iclass 14, count 2 2006.173.15:50:44.37#ibcon#about to read 6, iclass 14, count 2 2006.173.15:50:44.37#ibcon#read 6, iclass 14, count 2 2006.173.15:50:44.37#ibcon#end of sib2, iclass 14, count 2 2006.173.15:50:44.37#ibcon#*mode == 0, iclass 14, count 2 2006.173.15:50:44.37#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.15:50:44.37#ibcon#[27=AT08-04\r\n] 2006.173.15:50:44.37#ibcon#*before write, iclass 14, count 2 2006.173.15:50:44.37#ibcon#enter sib2, iclass 14, count 2 2006.173.15:50:44.37#ibcon#flushed, iclass 14, count 2 2006.173.15:50:44.37#ibcon#about to write, iclass 14, count 2 2006.173.15:50:44.37#ibcon#wrote, iclass 14, count 2 2006.173.15:50:44.37#ibcon#about to read 3, iclass 14, count 2 2006.173.15:50:44.40#ibcon#read 3, iclass 14, count 2 2006.173.15:50:44.40#ibcon#about to read 4, iclass 14, count 2 2006.173.15:50:44.40#ibcon#read 4, iclass 14, count 2 2006.173.15:50:44.40#ibcon#about to read 5, iclass 14, count 2 2006.173.15:50:44.40#ibcon#read 5, iclass 14, count 2 2006.173.15:50:44.40#ibcon#about to read 6, iclass 14, count 2 2006.173.15:50:44.40#ibcon#read 6, iclass 14, count 2 2006.173.15:50:44.40#ibcon#end of sib2, iclass 14, count 2 2006.173.15:50:44.40#ibcon#*after write, iclass 14, count 2 2006.173.15:50:44.40#ibcon#*before return 0, iclass 14, count 2 2006.173.15:50:44.40#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.15:50:44.40#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.15:50:44.40#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.15:50:44.40#ibcon#ireg 7 cls_cnt 0 2006.173.15:50:44.40#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.15:50:44.52#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.15:50:44.52#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.15:50:44.52#ibcon#enter wrdev, iclass 14, count 0 2006.173.15:50:44.52#ibcon#first serial, iclass 14, count 0 2006.173.15:50:44.52#ibcon#enter sib2, iclass 14, count 0 2006.173.15:50:44.52#ibcon#flushed, iclass 14, count 0 2006.173.15:50:44.52#ibcon#about to write, iclass 14, count 0 2006.173.15:50:44.52#ibcon#wrote, iclass 14, count 0 2006.173.15:50:44.52#ibcon#about to read 3, iclass 14, count 0 2006.173.15:50:44.54#ibcon#read 3, iclass 14, count 0 2006.173.15:50:44.54#ibcon#about to read 4, iclass 14, count 0 2006.173.15:50:44.54#ibcon#read 4, iclass 14, count 0 2006.173.15:50:44.54#ibcon#about to read 5, iclass 14, count 0 2006.173.15:50:44.54#ibcon#read 5, iclass 14, count 0 2006.173.15:50:44.54#ibcon#about to read 6, iclass 14, count 0 2006.173.15:50:44.54#ibcon#read 6, iclass 14, count 0 2006.173.15:50:44.54#ibcon#end of sib2, iclass 14, count 0 2006.173.15:50:44.54#ibcon#*mode == 0, iclass 14, count 0 2006.173.15:50:44.54#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.15:50:44.54#ibcon#[27=USB\r\n] 2006.173.15:50:44.54#ibcon#*before write, iclass 14, count 0 2006.173.15:50:44.54#ibcon#enter sib2, iclass 14, count 0 2006.173.15:50:44.54#ibcon#flushed, iclass 14, count 0 2006.173.15:50:44.54#ibcon#about to write, iclass 14, count 0 2006.173.15:50:44.54#ibcon#wrote, iclass 14, count 0 2006.173.15:50:44.54#ibcon#about to read 3, iclass 14, count 0 2006.173.15:50:44.57#ibcon#read 3, iclass 14, count 0 2006.173.15:50:44.57#ibcon#about to read 4, iclass 14, count 0 2006.173.15:50:44.57#ibcon#read 4, iclass 14, count 0 2006.173.15:50:44.57#ibcon#about to read 5, iclass 14, count 0 2006.173.15:50:44.57#ibcon#read 5, iclass 14, count 0 2006.173.15:50:44.57#ibcon#about to read 6, iclass 14, count 0 2006.173.15:50:44.57#ibcon#read 6, iclass 14, count 0 2006.173.15:50:44.57#ibcon#end of sib2, iclass 14, count 0 2006.173.15:50:44.57#ibcon#*after write, iclass 14, count 0 2006.173.15:50:44.57#ibcon#*before return 0, iclass 14, count 0 2006.173.15:50:44.57#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.15:50:44.57#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.15:50:44.57#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.15:50:44.57#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.15:50:44.57$vck44/vabw=wide 2006.173.15:50:44.57#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.15:50:44.57#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.15:50:44.57#ibcon#ireg 8 cls_cnt 0 2006.173.15:50:44.57#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.15:50:44.57#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.15:50:44.57#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.15:50:44.57#ibcon#enter wrdev, iclass 16, count 0 2006.173.15:50:44.57#ibcon#first serial, iclass 16, count 0 2006.173.15:50:44.57#ibcon#enter sib2, iclass 16, count 0 2006.173.15:50:44.57#ibcon#flushed, iclass 16, count 0 2006.173.15:50:44.57#ibcon#about to write, iclass 16, count 0 2006.173.15:50:44.57#ibcon#wrote, iclass 16, count 0 2006.173.15:50:44.57#ibcon#about to read 3, iclass 16, count 0 2006.173.15:50:44.59#ibcon#read 3, iclass 16, count 0 2006.173.15:50:44.59#ibcon#about to read 4, iclass 16, count 0 2006.173.15:50:44.59#ibcon#read 4, iclass 16, count 0 2006.173.15:50:44.59#ibcon#about to read 5, iclass 16, count 0 2006.173.15:50:44.59#ibcon#read 5, iclass 16, count 0 2006.173.15:50:44.59#ibcon#about to read 6, iclass 16, count 0 2006.173.15:50:44.59#ibcon#read 6, iclass 16, count 0 2006.173.15:50:44.59#ibcon#end of sib2, iclass 16, count 0 2006.173.15:50:44.59#ibcon#*mode == 0, iclass 16, count 0 2006.173.15:50:44.59#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.15:50:44.59#ibcon#[25=BW32\r\n] 2006.173.15:50:44.59#ibcon#*before write, iclass 16, count 0 2006.173.15:50:44.59#ibcon#enter sib2, iclass 16, count 0 2006.173.15:50:44.59#ibcon#flushed, iclass 16, count 0 2006.173.15:50:44.59#ibcon#about to write, iclass 16, count 0 2006.173.15:50:44.59#ibcon#wrote, iclass 16, count 0 2006.173.15:50:44.59#ibcon#about to read 3, iclass 16, count 0 2006.173.15:50:44.62#ibcon#read 3, iclass 16, count 0 2006.173.15:50:44.62#ibcon#about to read 4, iclass 16, count 0 2006.173.15:50:44.62#ibcon#read 4, iclass 16, count 0 2006.173.15:50:44.62#ibcon#about to read 5, iclass 16, count 0 2006.173.15:50:44.62#ibcon#read 5, iclass 16, count 0 2006.173.15:50:44.62#ibcon#about to read 6, iclass 16, count 0 2006.173.15:50:44.62#ibcon#read 6, iclass 16, count 0 2006.173.15:50:44.62#ibcon#end of sib2, iclass 16, count 0 2006.173.15:50:44.62#ibcon#*after write, iclass 16, count 0 2006.173.15:50:44.62#ibcon#*before return 0, iclass 16, count 0 2006.173.15:50:44.62#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.15:50:44.62#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.15:50:44.62#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.15:50:44.62#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.15:50:44.62$vck44/vbbw=wide 2006.173.15:50:44.62#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.15:50:44.62#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.15:50:44.62#ibcon#ireg 8 cls_cnt 0 2006.173.15:50:44.62#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.15:50:44.69#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.15:50:44.69#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.15:50:44.69#ibcon#enter wrdev, iclass 18, count 0 2006.173.15:50:44.69#ibcon#first serial, iclass 18, count 0 2006.173.15:50:44.69#ibcon#enter sib2, iclass 18, count 0 2006.173.15:50:44.69#ibcon#flushed, iclass 18, count 0 2006.173.15:50:44.69#ibcon#about to write, iclass 18, count 0 2006.173.15:50:44.69#ibcon#wrote, iclass 18, count 0 2006.173.15:50:44.69#ibcon#about to read 3, iclass 18, count 0 2006.173.15:50:44.71#ibcon#read 3, iclass 18, count 0 2006.173.15:50:44.71#ibcon#about to read 4, iclass 18, count 0 2006.173.15:50:44.71#ibcon#read 4, iclass 18, count 0 2006.173.15:50:44.71#ibcon#about to read 5, iclass 18, count 0 2006.173.15:50:44.71#ibcon#read 5, iclass 18, count 0 2006.173.15:50:44.71#ibcon#about to read 6, iclass 18, count 0 2006.173.15:50:44.71#ibcon#read 6, iclass 18, count 0 2006.173.15:50:44.71#ibcon#end of sib2, iclass 18, count 0 2006.173.15:50:44.71#ibcon#*mode == 0, iclass 18, count 0 2006.173.15:50:44.71#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.15:50:44.71#ibcon#[27=BW32\r\n] 2006.173.15:50:44.71#ibcon#*before write, iclass 18, count 0 2006.173.15:50:44.71#ibcon#enter sib2, iclass 18, count 0 2006.173.15:50:44.71#ibcon#flushed, iclass 18, count 0 2006.173.15:50:44.71#ibcon#about to write, iclass 18, count 0 2006.173.15:50:44.71#ibcon#wrote, iclass 18, count 0 2006.173.15:50:44.71#ibcon#about to read 3, iclass 18, count 0 2006.173.15:50:44.74#ibcon#read 3, iclass 18, count 0 2006.173.15:50:44.74#ibcon#about to read 4, iclass 18, count 0 2006.173.15:50:44.74#ibcon#read 4, iclass 18, count 0 2006.173.15:50:44.74#ibcon#about to read 5, iclass 18, count 0 2006.173.15:50:44.74#ibcon#read 5, iclass 18, count 0 2006.173.15:50:44.74#ibcon#about to read 6, iclass 18, count 0 2006.173.15:50:44.74#ibcon#read 6, iclass 18, count 0 2006.173.15:50:44.74#ibcon#end of sib2, iclass 18, count 0 2006.173.15:50:44.74#ibcon#*after write, iclass 18, count 0 2006.173.15:50:44.74#ibcon#*before return 0, iclass 18, count 0 2006.173.15:50:44.74#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.15:50:44.74#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.15:50:44.74#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.15:50:44.74#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.15:50:44.74$setupk4/ifdk4 2006.173.15:50:44.74$ifdk4/lo= 2006.173.15:50:44.74$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.15:50:44.74$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.15:50:44.74$ifdk4/patch= 2006.173.15:50:44.74$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.15:50:44.74$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.15:50:44.74$setupk4/!*+20s 2006.173.15:50:45.63#abcon#<5=/14 1.1 2.0 20.811001003.1\r\n> 2006.173.15:50:45.65#abcon#{5=INTERFACE CLEAR} 2006.173.15:50:45.71#abcon#[5=S1D000X0/0*\r\n] 2006.173.15:50:55.80#abcon#<5=/14 1.1 2.0 20.811001003.1\r\n> 2006.173.15:50:55.82#abcon#{5=INTERFACE CLEAR} 2006.173.15:50:55.88#abcon#[5=S1D000X0/0*\r\n] 2006.173.15:50:59.24$setupk4/"tpicd 2006.173.15:50:59.24$setupk4/echo=off 2006.173.15:50:59.24$setupk4/xlog=off 2006.173.15:50:59.24:!2006.173.15:52:53 2006.173.15:51:10.13#trakl#Source acquired 2006.173.15:51:10.13#flagr#flagr/antenna,acquired 2006.173.15:52:53.00:preob 2006.173.15:52:53.13/onsource/TRACKING 2006.173.15:52:53.13:!2006.173.15:53:03 2006.173.15:53:03.00:"tape 2006.173.15:53:03.00:"st=record 2006.173.15:53:03.00:data_valid=on 2006.173.15:53:03.00:midob 2006.173.15:53:04.14/onsource/TRACKING 2006.173.15:53:04.14/wx/20.78,1003.1,100 2006.173.15:53:04.29/cable/+6.5102E-03 2006.173.15:53:05.38/va/01,07,usb,yes,35,38 2006.173.15:53:05.38/va/02,06,usb,yes,35,36 2006.173.15:53:05.38/va/03,05,usb,yes,45,47 2006.173.15:53:05.38/va/04,06,usb,yes,36,38 2006.173.15:53:05.38/va/05,04,usb,yes,28,29 2006.173.15:53:05.38/va/06,03,usb,yes,40,39 2006.173.15:53:05.38/va/07,04,usb,yes,32,33 2006.173.15:53:05.38/va/08,04,usb,yes,27,33 2006.173.15:53:05.61/valo/01,524.99,yes,locked 2006.173.15:53:05.61/valo/02,534.99,yes,locked 2006.173.15:53:05.61/valo/03,564.99,yes,locked 2006.173.15:53:05.61/valo/04,624.99,yes,locked 2006.173.15:53:05.61/valo/05,734.99,yes,locked 2006.173.15:53:05.61/valo/06,814.99,yes,locked 2006.173.15:53:05.61/valo/07,864.99,yes,locked 2006.173.15:53:05.61/valo/08,884.99,yes,locked 2006.173.15:53:06.70/vb/01,04,usb,yes,29,27 2006.173.15:53:06.70/vb/02,04,usb,yes,31,31 2006.173.15:53:06.70/vb/03,04,usb,yes,28,31 2006.173.15:53:06.70/vb/04,04,usb,yes,33,32 2006.173.15:53:06.70/vb/05,04,usb,yes,25,28 2006.173.15:53:06.70/vb/06,04,usb,yes,30,26 2006.173.15:53:06.70/vb/07,04,usb,yes,29,29 2006.173.15:53:06.70/vb/08,04,usb,yes,27,30 2006.173.15:53:06.94/vblo/01,629.99,yes,locked 2006.173.15:53:06.94/vblo/02,634.99,yes,locked 2006.173.15:53:06.94/vblo/03,649.99,yes,locked 2006.173.15:53:06.94/vblo/04,679.99,yes,locked 2006.173.15:53:06.94/vblo/05,709.99,yes,locked 2006.173.15:53:06.94/vblo/06,719.99,yes,locked 2006.173.15:53:06.94/vblo/07,734.99,yes,locked 2006.173.15:53:06.94/vblo/08,744.99,yes,locked 2006.173.15:53:07.09/vabw/8 2006.173.15:53:07.24/vbbw/8 2006.173.15:53:07.33/xfe/off,on,15.5 2006.173.15:53:07.70/ifatt/23,28,28,28 2006.173.15:53:08.07/fmout-gps/S +4.00E-07 2006.173.15:53:08.11:!2006.173.15:53:43 2006.173.15:53:43.01:data_valid=off 2006.173.15:53:43.01:"et 2006.173.15:53:43.02:!+3s 2006.173.15:53:46.03:"tape 2006.173.15:53:46.03:postob 2006.173.15:53:46.25/cable/+6.5099E-03 2006.173.15:53:46.25/wx/20.77,1003.0,100 2006.173.15:53:46.31/fmout-gps/S +4.00E-07 2006.173.15:53:46.31:scan_name=173-1556,jd0606,240 2006.173.15:53:46.32:source=1044+719,104827.62,714335.9,2000.0,cw 2006.173.15:53:48.14#flagr#flagr/antenna,new-source 2006.173.15:53:48.14:checkk5 2006.173.15:53:48.54/chk_autoobs//k5ts1/ autoobs is running! 2006.173.15:53:48.95/chk_autoobs//k5ts2/ autoobs is running! 2006.173.15:53:49.37/chk_autoobs//k5ts3/ autoobs is running! 2006.173.15:53:49.76/chk_autoobs//k5ts4/ autoobs is running! 2006.173.15:53:50.16/chk_obsdata//k5ts1/T1731553??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.15:53:50.56/chk_obsdata//k5ts2/T1731553??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.15:53:50.95/chk_obsdata//k5ts3/T1731553??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.15:53:51.35/chk_obsdata//k5ts4/T1731553??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.15:53:52.08/k5log//k5ts1_log_newline 2006.173.15:53:52.80/k5log//k5ts2_log_newline 2006.173.15:53:53.51/k5log//k5ts3_log_newline 2006.173.15:53:54.22/k5log//k5ts4_log_newline 2006.173.15:53:54.24/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.15:53:54.24:setupk4=1 2006.173.15:53:54.24$setupk4/echo=on 2006.173.15:53:54.24$setupk4/pcalon 2006.173.15:53:54.24$pcalon/"no phase cal control is implemented here 2006.173.15:53:54.24$setupk4/"tpicd=stop 2006.173.15:53:54.24$setupk4/"rec=synch_on 2006.173.15:53:54.24$setupk4/"rec_mode=128 2006.173.15:53:54.24$setupk4/!* 2006.173.15:53:54.24$setupk4/recpk4 2006.173.15:53:54.24$recpk4/recpatch= 2006.173.15:53:54.25$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.15:53:54.25$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.15:53:54.25$setupk4/vck44 2006.173.15:53:54.25$vck44/valo=1,524.99 2006.173.15:53:54.25#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.15:53:54.25#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.15:53:54.25#ibcon#ireg 17 cls_cnt 0 2006.173.15:53:54.25#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.15:53:54.25#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.15:53:54.25#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.15:53:54.25#ibcon#enter wrdev, iclass 27, count 0 2006.173.15:53:54.25#ibcon#first serial, iclass 27, count 0 2006.173.15:53:54.25#ibcon#enter sib2, iclass 27, count 0 2006.173.15:53:54.25#ibcon#flushed, iclass 27, count 0 2006.173.15:53:54.25#ibcon#about to write, iclass 27, count 0 2006.173.15:53:54.25#ibcon#wrote, iclass 27, count 0 2006.173.15:53:54.25#ibcon#about to read 3, iclass 27, count 0 2006.173.15:53:54.27#ibcon#read 3, iclass 27, count 0 2006.173.15:53:54.27#ibcon#about to read 4, iclass 27, count 0 2006.173.15:53:54.27#ibcon#read 4, iclass 27, count 0 2006.173.15:53:54.27#ibcon#about to read 5, iclass 27, count 0 2006.173.15:53:54.27#ibcon#read 5, iclass 27, count 0 2006.173.15:53:54.27#ibcon#about to read 6, iclass 27, count 0 2006.173.15:53:54.27#ibcon#read 6, iclass 27, count 0 2006.173.15:53:54.27#ibcon#end of sib2, iclass 27, count 0 2006.173.15:53:54.27#ibcon#*mode == 0, iclass 27, count 0 2006.173.15:53:54.27#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.15:53:54.27#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.15:53:54.27#ibcon#*before write, iclass 27, count 0 2006.173.15:53:54.27#ibcon#enter sib2, iclass 27, count 0 2006.173.15:53:54.27#ibcon#flushed, iclass 27, count 0 2006.173.15:53:54.27#ibcon#about to write, iclass 27, count 0 2006.173.15:53:54.27#ibcon#wrote, iclass 27, count 0 2006.173.15:53:54.27#ibcon#about to read 3, iclass 27, count 0 2006.173.15:53:54.32#ibcon#read 3, iclass 27, count 0 2006.173.15:53:54.32#ibcon#about to read 4, iclass 27, count 0 2006.173.15:53:54.32#ibcon#read 4, iclass 27, count 0 2006.173.15:53:54.32#ibcon#about to read 5, iclass 27, count 0 2006.173.15:53:54.32#ibcon#read 5, iclass 27, count 0 2006.173.15:53:54.32#ibcon#about to read 6, iclass 27, count 0 2006.173.15:53:54.32#ibcon#read 6, iclass 27, count 0 2006.173.15:53:54.32#ibcon#end of sib2, iclass 27, count 0 2006.173.15:53:54.32#ibcon#*after write, iclass 27, count 0 2006.173.15:53:54.32#ibcon#*before return 0, iclass 27, count 0 2006.173.15:53:54.32#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.15:53:54.32#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.15:53:54.32#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.15:53:54.32#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.15:53:54.32$vck44/va=1,7 2006.173.15:53:54.32#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.15:53:54.32#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.15:53:54.32#ibcon#ireg 11 cls_cnt 2 2006.173.15:53:54.32#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.15:53:54.32#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.15:53:54.32#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.15:53:54.32#ibcon#enter wrdev, iclass 29, count 2 2006.173.15:53:54.32#ibcon#first serial, iclass 29, count 2 2006.173.15:53:54.32#ibcon#enter sib2, iclass 29, count 2 2006.173.15:53:54.32#ibcon#flushed, iclass 29, count 2 2006.173.15:53:54.32#ibcon#about to write, iclass 29, count 2 2006.173.15:53:54.32#ibcon#wrote, iclass 29, count 2 2006.173.15:53:54.32#ibcon#about to read 3, iclass 29, count 2 2006.173.15:53:54.34#ibcon#read 3, iclass 29, count 2 2006.173.15:53:54.34#ibcon#about to read 4, iclass 29, count 2 2006.173.15:53:54.34#ibcon#read 4, iclass 29, count 2 2006.173.15:53:54.34#ibcon#about to read 5, iclass 29, count 2 2006.173.15:53:54.34#ibcon#read 5, iclass 29, count 2 2006.173.15:53:54.34#ibcon#about to read 6, iclass 29, count 2 2006.173.15:53:54.34#ibcon#read 6, iclass 29, count 2 2006.173.15:53:54.34#ibcon#end of sib2, iclass 29, count 2 2006.173.15:53:54.34#ibcon#*mode == 0, iclass 29, count 2 2006.173.15:53:54.34#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.15:53:54.34#ibcon#[25=AT01-07\r\n] 2006.173.15:53:54.34#ibcon#*before write, iclass 29, count 2 2006.173.15:53:54.34#ibcon#enter sib2, iclass 29, count 2 2006.173.15:53:54.34#ibcon#flushed, iclass 29, count 2 2006.173.15:53:54.34#ibcon#about to write, iclass 29, count 2 2006.173.15:53:54.34#ibcon#wrote, iclass 29, count 2 2006.173.15:53:54.34#ibcon#about to read 3, iclass 29, count 2 2006.173.15:53:54.37#ibcon#read 3, iclass 29, count 2 2006.173.15:53:54.37#ibcon#about to read 4, iclass 29, count 2 2006.173.15:53:54.37#ibcon#read 4, iclass 29, count 2 2006.173.15:53:54.37#ibcon#about to read 5, iclass 29, count 2 2006.173.15:53:54.37#ibcon#read 5, iclass 29, count 2 2006.173.15:53:54.37#ibcon#about to read 6, iclass 29, count 2 2006.173.15:53:54.37#ibcon#read 6, iclass 29, count 2 2006.173.15:53:54.37#ibcon#end of sib2, iclass 29, count 2 2006.173.15:53:54.37#ibcon#*after write, iclass 29, count 2 2006.173.15:53:54.37#ibcon#*before return 0, iclass 29, count 2 2006.173.15:53:54.37#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.15:53:54.37#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.15:53:54.37#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.15:53:54.37#ibcon#ireg 7 cls_cnt 0 2006.173.15:53:54.37#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.15:53:54.49#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.15:53:54.49#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.15:53:54.49#ibcon#enter wrdev, iclass 29, count 0 2006.173.15:53:54.49#ibcon#first serial, iclass 29, count 0 2006.173.15:53:54.49#ibcon#enter sib2, iclass 29, count 0 2006.173.15:53:54.49#ibcon#flushed, iclass 29, count 0 2006.173.15:53:54.49#ibcon#about to write, iclass 29, count 0 2006.173.15:53:54.49#ibcon#wrote, iclass 29, count 0 2006.173.15:53:54.49#ibcon#about to read 3, iclass 29, count 0 2006.173.15:53:54.51#ibcon#read 3, iclass 29, count 0 2006.173.15:53:54.51#ibcon#about to read 4, iclass 29, count 0 2006.173.15:53:54.51#ibcon#read 4, iclass 29, count 0 2006.173.15:53:54.51#ibcon#about to read 5, iclass 29, count 0 2006.173.15:53:54.51#ibcon#read 5, iclass 29, count 0 2006.173.15:53:54.51#ibcon#about to read 6, iclass 29, count 0 2006.173.15:53:54.51#ibcon#read 6, iclass 29, count 0 2006.173.15:53:54.51#ibcon#end of sib2, iclass 29, count 0 2006.173.15:53:54.51#ibcon#*mode == 0, iclass 29, count 0 2006.173.15:53:54.51#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.15:53:54.51#ibcon#[25=USB\r\n] 2006.173.15:53:54.51#ibcon#*before write, iclass 29, count 0 2006.173.15:53:54.51#ibcon#enter sib2, iclass 29, count 0 2006.173.15:53:54.51#ibcon#flushed, iclass 29, count 0 2006.173.15:53:54.51#ibcon#about to write, iclass 29, count 0 2006.173.15:53:54.51#ibcon#wrote, iclass 29, count 0 2006.173.15:53:54.51#ibcon#about to read 3, iclass 29, count 0 2006.173.15:53:54.54#ibcon#read 3, iclass 29, count 0 2006.173.15:53:54.54#ibcon#about to read 4, iclass 29, count 0 2006.173.15:53:54.54#ibcon#read 4, iclass 29, count 0 2006.173.15:53:54.54#ibcon#about to read 5, iclass 29, count 0 2006.173.15:53:54.54#ibcon#read 5, iclass 29, count 0 2006.173.15:53:54.54#ibcon#about to read 6, iclass 29, count 0 2006.173.15:53:54.54#ibcon#read 6, iclass 29, count 0 2006.173.15:53:54.54#ibcon#end of sib2, iclass 29, count 0 2006.173.15:53:54.54#ibcon#*after write, iclass 29, count 0 2006.173.15:53:54.54#ibcon#*before return 0, iclass 29, count 0 2006.173.15:53:54.54#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.15:53:54.54#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.15:53:54.54#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.15:53:54.54#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.15:53:54.54$vck44/valo=2,534.99 2006.173.15:53:54.54#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.15:53:54.54#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.15:53:54.54#ibcon#ireg 17 cls_cnt 0 2006.173.15:53:54.54#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.15:53:54.54#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.15:53:54.54#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.15:53:54.54#ibcon#enter wrdev, iclass 31, count 0 2006.173.15:53:54.54#ibcon#first serial, iclass 31, count 0 2006.173.15:53:54.54#ibcon#enter sib2, iclass 31, count 0 2006.173.15:53:54.54#ibcon#flushed, iclass 31, count 0 2006.173.15:53:54.54#ibcon#about to write, iclass 31, count 0 2006.173.15:53:54.54#ibcon#wrote, iclass 31, count 0 2006.173.15:53:54.54#ibcon#about to read 3, iclass 31, count 0 2006.173.15:53:54.56#ibcon#read 3, iclass 31, count 0 2006.173.15:53:54.56#ibcon#about to read 4, iclass 31, count 0 2006.173.15:53:54.56#ibcon#read 4, iclass 31, count 0 2006.173.15:53:54.56#ibcon#about to read 5, iclass 31, count 0 2006.173.15:53:54.56#ibcon#read 5, iclass 31, count 0 2006.173.15:53:54.56#ibcon#about to read 6, iclass 31, count 0 2006.173.15:53:54.56#ibcon#read 6, iclass 31, count 0 2006.173.15:53:54.56#ibcon#end of sib2, iclass 31, count 0 2006.173.15:53:54.56#ibcon#*mode == 0, iclass 31, count 0 2006.173.15:53:54.56#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.15:53:54.56#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.15:53:54.56#ibcon#*before write, iclass 31, count 0 2006.173.15:53:54.56#ibcon#enter sib2, iclass 31, count 0 2006.173.15:53:54.56#ibcon#flushed, iclass 31, count 0 2006.173.15:53:54.56#ibcon#about to write, iclass 31, count 0 2006.173.15:53:54.56#ibcon#wrote, iclass 31, count 0 2006.173.15:53:54.56#ibcon#about to read 3, iclass 31, count 0 2006.173.15:53:54.60#ibcon#read 3, iclass 31, count 0 2006.173.15:53:54.60#ibcon#about to read 4, iclass 31, count 0 2006.173.15:53:54.60#ibcon#read 4, iclass 31, count 0 2006.173.15:53:54.60#ibcon#about to read 5, iclass 31, count 0 2006.173.15:53:54.60#ibcon#read 5, iclass 31, count 0 2006.173.15:53:54.60#ibcon#about to read 6, iclass 31, count 0 2006.173.15:53:54.60#ibcon#read 6, iclass 31, count 0 2006.173.15:53:54.60#ibcon#end of sib2, iclass 31, count 0 2006.173.15:53:54.60#ibcon#*after write, iclass 31, count 0 2006.173.15:53:54.60#ibcon#*before return 0, iclass 31, count 0 2006.173.15:53:54.60#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.15:53:54.60#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.15:53:54.60#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.15:53:54.60#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.15:53:54.60$vck44/va=2,6 2006.173.15:53:54.60#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.173.15:53:54.60#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.173.15:53:54.60#ibcon#ireg 11 cls_cnt 2 2006.173.15:53:54.60#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.15:53:54.66#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.15:53:54.66#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.15:53:54.66#ibcon#enter wrdev, iclass 33, count 2 2006.173.15:53:54.66#ibcon#first serial, iclass 33, count 2 2006.173.15:53:54.66#ibcon#enter sib2, iclass 33, count 2 2006.173.15:53:54.66#ibcon#flushed, iclass 33, count 2 2006.173.15:53:54.66#ibcon#about to write, iclass 33, count 2 2006.173.15:53:54.66#ibcon#wrote, iclass 33, count 2 2006.173.15:53:54.66#ibcon#about to read 3, iclass 33, count 2 2006.173.15:53:54.68#ibcon#read 3, iclass 33, count 2 2006.173.15:53:54.68#ibcon#about to read 4, iclass 33, count 2 2006.173.15:53:54.68#ibcon#read 4, iclass 33, count 2 2006.173.15:53:54.68#ibcon#about to read 5, iclass 33, count 2 2006.173.15:53:54.68#ibcon#read 5, iclass 33, count 2 2006.173.15:53:54.68#ibcon#about to read 6, iclass 33, count 2 2006.173.15:53:54.68#ibcon#read 6, iclass 33, count 2 2006.173.15:53:54.68#ibcon#end of sib2, iclass 33, count 2 2006.173.15:53:54.68#ibcon#*mode == 0, iclass 33, count 2 2006.173.15:53:54.68#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.173.15:53:54.68#ibcon#[25=AT02-06\r\n] 2006.173.15:53:54.68#ibcon#*before write, iclass 33, count 2 2006.173.15:53:54.68#ibcon#enter sib2, iclass 33, count 2 2006.173.15:53:54.68#ibcon#flushed, iclass 33, count 2 2006.173.15:53:54.68#ibcon#about to write, iclass 33, count 2 2006.173.15:53:54.68#ibcon#wrote, iclass 33, count 2 2006.173.15:53:54.68#ibcon#about to read 3, iclass 33, count 2 2006.173.15:53:54.71#ibcon#read 3, iclass 33, count 2 2006.173.15:53:54.71#ibcon#about to read 4, iclass 33, count 2 2006.173.15:53:54.71#ibcon#read 4, iclass 33, count 2 2006.173.15:53:54.71#ibcon#about to read 5, iclass 33, count 2 2006.173.15:53:54.71#ibcon#read 5, iclass 33, count 2 2006.173.15:53:54.71#ibcon#about to read 6, iclass 33, count 2 2006.173.15:53:54.71#ibcon#read 6, iclass 33, count 2 2006.173.15:53:54.71#ibcon#end of sib2, iclass 33, count 2 2006.173.15:53:54.71#ibcon#*after write, iclass 33, count 2 2006.173.15:53:54.71#ibcon#*before return 0, iclass 33, count 2 2006.173.15:53:54.71#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.15:53:54.71#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.173.15:53:54.71#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.173.15:53:54.71#ibcon#ireg 7 cls_cnt 0 2006.173.15:53:54.71#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.15:53:54.83#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.15:53:54.83#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.15:53:54.83#ibcon#enter wrdev, iclass 33, count 0 2006.173.15:53:54.83#ibcon#first serial, iclass 33, count 0 2006.173.15:53:54.83#ibcon#enter sib2, iclass 33, count 0 2006.173.15:53:54.83#ibcon#flushed, iclass 33, count 0 2006.173.15:53:54.83#ibcon#about to write, iclass 33, count 0 2006.173.15:53:54.83#ibcon#wrote, iclass 33, count 0 2006.173.15:53:54.83#ibcon#about to read 3, iclass 33, count 0 2006.173.15:53:54.85#ibcon#read 3, iclass 33, count 0 2006.173.15:53:54.85#ibcon#about to read 4, iclass 33, count 0 2006.173.15:53:54.85#ibcon#read 4, iclass 33, count 0 2006.173.15:53:54.85#ibcon#about to read 5, iclass 33, count 0 2006.173.15:53:54.85#ibcon#read 5, iclass 33, count 0 2006.173.15:53:54.85#ibcon#about to read 6, iclass 33, count 0 2006.173.15:53:54.85#ibcon#read 6, iclass 33, count 0 2006.173.15:53:54.85#ibcon#end of sib2, iclass 33, count 0 2006.173.15:53:54.85#ibcon#*mode == 0, iclass 33, count 0 2006.173.15:53:54.85#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.15:53:54.85#ibcon#[25=USB\r\n] 2006.173.15:53:54.85#ibcon#*before write, iclass 33, count 0 2006.173.15:53:54.85#ibcon#enter sib2, iclass 33, count 0 2006.173.15:53:54.85#ibcon#flushed, iclass 33, count 0 2006.173.15:53:54.85#ibcon#about to write, iclass 33, count 0 2006.173.15:53:54.85#ibcon#wrote, iclass 33, count 0 2006.173.15:53:54.85#ibcon#about to read 3, iclass 33, count 0 2006.173.15:53:54.88#ibcon#read 3, iclass 33, count 0 2006.173.15:53:54.88#ibcon#about to read 4, iclass 33, count 0 2006.173.15:53:54.88#ibcon#read 4, iclass 33, count 0 2006.173.15:53:54.88#ibcon#about to read 5, iclass 33, count 0 2006.173.15:53:54.88#ibcon#read 5, iclass 33, count 0 2006.173.15:53:54.88#ibcon#about to read 6, iclass 33, count 0 2006.173.15:53:54.88#ibcon#read 6, iclass 33, count 0 2006.173.15:53:54.88#ibcon#end of sib2, iclass 33, count 0 2006.173.15:53:54.88#ibcon#*after write, iclass 33, count 0 2006.173.15:53:54.88#ibcon#*before return 0, iclass 33, count 0 2006.173.15:53:54.88#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.15:53:54.88#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.173.15:53:54.88#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.15:53:54.88#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.15:53:54.88$vck44/valo=3,564.99 2006.173.15:53:54.88#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.15:53:54.88#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.15:53:54.88#ibcon#ireg 17 cls_cnt 0 2006.173.15:53:54.88#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.15:53:54.88#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.15:53:54.88#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.15:53:54.88#ibcon#enter wrdev, iclass 35, count 0 2006.173.15:53:54.88#ibcon#first serial, iclass 35, count 0 2006.173.15:53:54.88#ibcon#enter sib2, iclass 35, count 0 2006.173.15:53:54.88#ibcon#flushed, iclass 35, count 0 2006.173.15:53:54.88#ibcon#about to write, iclass 35, count 0 2006.173.15:53:54.88#ibcon#wrote, iclass 35, count 0 2006.173.15:53:54.88#ibcon#about to read 3, iclass 35, count 0 2006.173.15:53:54.90#ibcon#read 3, iclass 35, count 0 2006.173.15:53:54.90#ibcon#about to read 4, iclass 35, count 0 2006.173.15:53:54.90#ibcon#read 4, iclass 35, count 0 2006.173.15:53:54.90#ibcon#about to read 5, iclass 35, count 0 2006.173.15:53:54.90#ibcon#read 5, iclass 35, count 0 2006.173.15:53:54.90#ibcon#about to read 6, iclass 35, count 0 2006.173.15:53:54.90#ibcon#read 6, iclass 35, count 0 2006.173.15:53:54.90#ibcon#end of sib2, iclass 35, count 0 2006.173.15:53:54.90#ibcon#*mode == 0, iclass 35, count 0 2006.173.15:53:54.90#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.15:53:54.90#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.15:53:54.90#ibcon#*before write, iclass 35, count 0 2006.173.15:53:54.90#ibcon#enter sib2, iclass 35, count 0 2006.173.15:53:54.90#ibcon#flushed, iclass 35, count 0 2006.173.15:53:54.90#ibcon#about to write, iclass 35, count 0 2006.173.15:53:54.90#ibcon#wrote, iclass 35, count 0 2006.173.15:53:54.90#ibcon#about to read 3, iclass 35, count 0 2006.173.15:53:54.94#ibcon#read 3, iclass 35, count 0 2006.173.15:53:54.94#ibcon#about to read 4, iclass 35, count 0 2006.173.15:53:54.94#ibcon#read 4, iclass 35, count 0 2006.173.15:53:54.94#ibcon#about to read 5, iclass 35, count 0 2006.173.15:53:54.94#ibcon#read 5, iclass 35, count 0 2006.173.15:53:54.94#ibcon#about to read 6, iclass 35, count 0 2006.173.15:53:54.94#ibcon#read 6, iclass 35, count 0 2006.173.15:53:54.94#ibcon#end of sib2, iclass 35, count 0 2006.173.15:53:54.94#ibcon#*after write, iclass 35, count 0 2006.173.15:53:54.94#ibcon#*before return 0, iclass 35, count 0 2006.173.15:53:54.94#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.15:53:54.94#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.15:53:54.94#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.15:53:54.94#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.15:53:54.94$vck44/va=3,5 2006.173.15:53:54.94#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.173.15:53:54.94#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.173.15:53:54.94#ibcon#ireg 11 cls_cnt 2 2006.173.15:53:54.94#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.15:53:55.00#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.15:53:55.00#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.15:53:55.00#ibcon#enter wrdev, iclass 37, count 2 2006.173.15:53:55.00#ibcon#first serial, iclass 37, count 2 2006.173.15:53:55.00#ibcon#enter sib2, iclass 37, count 2 2006.173.15:53:55.00#ibcon#flushed, iclass 37, count 2 2006.173.15:53:55.00#ibcon#about to write, iclass 37, count 2 2006.173.15:53:55.00#ibcon#wrote, iclass 37, count 2 2006.173.15:53:55.00#ibcon#about to read 3, iclass 37, count 2 2006.173.15:53:55.02#ibcon#read 3, iclass 37, count 2 2006.173.15:53:55.02#ibcon#about to read 4, iclass 37, count 2 2006.173.15:53:55.02#ibcon#read 4, iclass 37, count 2 2006.173.15:53:55.02#ibcon#about to read 5, iclass 37, count 2 2006.173.15:53:55.02#ibcon#read 5, iclass 37, count 2 2006.173.15:53:55.02#ibcon#about to read 6, iclass 37, count 2 2006.173.15:53:55.02#ibcon#read 6, iclass 37, count 2 2006.173.15:53:55.02#ibcon#end of sib2, iclass 37, count 2 2006.173.15:53:55.02#ibcon#*mode == 0, iclass 37, count 2 2006.173.15:53:55.02#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.173.15:53:55.02#ibcon#[25=AT03-05\r\n] 2006.173.15:53:55.02#ibcon#*before write, iclass 37, count 2 2006.173.15:53:55.02#ibcon#enter sib2, iclass 37, count 2 2006.173.15:53:55.02#ibcon#flushed, iclass 37, count 2 2006.173.15:53:55.02#ibcon#about to write, iclass 37, count 2 2006.173.15:53:55.02#ibcon#wrote, iclass 37, count 2 2006.173.15:53:55.02#ibcon#about to read 3, iclass 37, count 2 2006.173.15:53:55.05#ibcon#read 3, iclass 37, count 2 2006.173.15:53:55.05#ibcon#about to read 4, iclass 37, count 2 2006.173.15:53:55.05#ibcon#read 4, iclass 37, count 2 2006.173.15:53:55.05#ibcon#about to read 5, iclass 37, count 2 2006.173.15:53:55.05#ibcon#read 5, iclass 37, count 2 2006.173.15:53:55.05#ibcon#about to read 6, iclass 37, count 2 2006.173.15:53:55.05#ibcon#read 6, iclass 37, count 2 2006.173.15:53:55.05#ibcon#end of sib2, iclass 37, count 2 2006.173.15:53:55.05#ibcon#*after write, iclass 37, count 2 2006.173.15:53:55.05#ibcon#*before return 0, iclass 37, count 2 2006.173.15:53:55.05#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.15:53:55.05#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.173.15:53:55.05#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.173.15:53:55.05#ibcon#ireg 7 cls_cnt 0 2006.173.15:53:55.05#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.15:53:55.17#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.15:53:55.17#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.15:53:55.17#ibcon#enter wrdev, iclass 37, count 0 2006.173.15:53:55.17#ibcon#first serial, iclass 37, count 0 2006.173.15:53:55.17#ibcon#enter sib2, iclass 37, count 0 2006.173.15:53:55.17#ibcon#flushed, iclass 37, count 0 2006.173.15:53:55.17#ibcon#about to write, iclass 37, count 0 2006.173.15:53:55.17#ibcon#wrote, iclass 37, count 0 2006.173.15:53:55.17#ibcon#about to read 3, iclass 37, count 0 2006.173.15:53:55.19#ibcon#read 3, iclass 37, count 0 2006.173.15:53:55.19#ibcon#about to read 4, iclass 37, count 0 2006.173.15:53:55.19#ibcon#read 4, iclass 37, count 0 2006.173.15:53:55.19#ibcon#about to read 5, iclass 37, count 0 2006.173.15:53:55.19#ibcon#read 5, iclass 37, count 0 2006.173.15:53:55.19#ibcon#about to read 6, iclass 37, count 0 2006.173.15:53:55.19#ibcon#read 6, iclass 37, count 0 2006.173.15:53:55.19#ibcon#end of sib2, iclass 37, count 0 2006.173.15:53:55.19#ibcon#*mode == 0, iclass 37, count 0 2006.173.15:53:55.19#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.15:53:55.19#ibcon#[25=USB\r\n] 2006.173.15:53:55.19#ibcon#*before write, iclass 37, count 0 2006.173.15:53:55.19#ibcon#enter sib2, iclass 37, count 0 2006.173.15:53:55.19#ibcon#flushed, iclass 37, count 0 2006.173.15:53:55.19#ibcon#about to write, iclass 37, count 0 2006.173.15:53:55.19#ibcon#wrote, iclass 37, count 0 2006.173.15:53:55.19#ibcon#about to read 3, iclass 37, count 0 2006.173.15:53:55.22#ibcon#read 3, iclass 37, count 0 2006.173.15:53:55.22#ibcon#about to read 4, iclass 37, count 0 2006.173.15:53:55.22#ibcon#read 4, iclass 37, count 0 2006.173.15:53:55.22#ibcon#about to read 5, iclass 37, count 0 2006.173.15:53:55.22#ibcon#read 5, iclass 37, count 0 2006.173.15:53:55.22#ibcon#about to read 6, iclass 37, count 0 2006.173.15:53:55.22#ibcon#read 6, iclass 37, count 0 2006.173.15:53:55.22#ibcon#end of sib2, iclass 37, count 0 2006.173.15:53:55.22#ibcon#*after write, iclass 37, count 0 2006.173.15:53:55.22#ibcon#*before return 0, iclass 37, count 0 2006.173.15:53:55.22#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.15:53:55.22#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.173.15:53:55.22#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.15:53:55.22#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.15:53:55.22$vck44/valo=4,624.99 2006.173.15:53:55.22#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.15:53:55.22#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.15:53:55.22#ibcon#ireg 17 cls_cnt 0 2006.173.15:53:55.22#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.15:53:55.22#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.15:53:55.22#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.15:53:55.22#ibcon#enter wrdev, iclass 39, count 0 2006.173.15:53:55.22#ibcon#first serial, iclass 39, count 0 2006.173.15:53:55.22#ibcon#enter sib2, iclass 39, count 0 2006.173.15:53:55.22#ibcon#flushed, iclass 39, count 0 2006.173.15:53:55.22#ibcon#about to write, iclass 39, count 0 2006.173.15:53:55.22#ibcon#wrote, iclass 39, count 0 2006.173.15:53:55.22#ibcon#about to read 3, iclass 39, count 0 2006.173.15:53:55.24#ibcon#read 3, iclass 39, count 0 2006.173.15:53:55.24#ibcon#about to read 4, iclass 39, count 0 2006.173.15:53:55.24#ibcon#read 4, iclass 39, count 0 2006.173.15:53:55.24#ibcon#about to read 5, iclass 39, count 0 2006.173.15:53:55.24#ibcon#read 5, iclass 39, count 0 2006.173.15:53:55.24#ibcon#about to read 6, iclass 39, count 0 2006.173.15:53:55.24#ibcon#read 6, iclass 39, count 0 2006.173.15:53:55.24#ibcon#end of sib2, iclass 39, count 0 2006.173.15:53:55.24#ibcon#*mode == 0, iclass 39, count 0 2006.173.15:53:55.24#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.15:53:55.24#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.15:53:55.24#ibcon#*before write, iclass 39, count 0 2006.173.15:53:55.24#ibcon#enter sib2, iclass 39, count 0 2006.173.15:53:55.24#ibcon#flushed, iclass 39, count 0 2006.173.15:53:55.24#ibcon#about to write, iclass 39, count 0 2006.173.15:53:55.24#ibcon#wrote, iclass 39, count 0 2006.173.15:53:55.24#ibcon#about to read 3, iclass 39, count 0 2006.173.15:53:55.28#ibcon#read 3, iclass 39, count 0 2006.173.15:53:55.28#ibcon#about to read 4, iclass 39, count 0 2006.173.15:53:55.28#ibcon#read 4, iclass 39, count 0 2006.173.15:53:55.28#ibcon#about to read 5, iclass 39, count 0 2006.173.15:53:55.28#ibcon#read 5, iclass 39, count 0 2006.173.15:53:55.28#ibcon#about to read 6, iclass 39, count 0 2006.173.15:53:55.28#ibcon#read 6, iclass 39, count 0 2006.173.15:53:55.28#ibcon#end of sib2, iclass 39, count 0 2006.173.15:53:55.28#ibcon#*after write, iclass 39, count 0 2006.173.15:53:55.28#ibcon#*before return 0, iclass 39, count 0 2006.173.15:53:55.28#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.15:53:55.28#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.15:53:55.28#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.15:53:55.28#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.15:53:55.28$vck44/va=4,6 2006.173.15:53:55.28#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.15:53:55.28#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.15:53:55.28#ibcon#ireg 11 cls_cnt 2 2006.173.15:53:55.28#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.15:53:55.34#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.15:53:55.34#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.15:53:55.34#ibcon#enter wrdev, iclass 3, count 2 2006.173.15:53:55.34#ibcon#first serial, iclass 3, count 2 2006.173.15:53:55.34#ibcon#enter sib2, iclass 3, count 2 2006.173.15:53:55.34#ibcon#flushed, iclass 3, count 2 2006.173.15:53:55.34#ibcon#about to write, iclass 3, count 2 2006.173.15:53:55.34#ibcon#wrote, iclass 3, count 2 2006.173.15:53:55.34#ibcon#about to read 3, iclass 3, count 2 2006.173.15:53:55.36#ibcon#read 3, iclass 3, count 2 2006.173.15:53:55.36#ibcon#about to read 4, iclass 3, count 2 2006.173.15:53:55.36#ibcon#read 4, iclass 3, count 2 2006.173.15:53:55.36#ibcon#about to read 5, iclass 3, count 2 2006.173.15:53:55.36#ibcon#read 5, iclass 3, count 2 2006.173.15:53:55.36#ibcon#about to read 6, iclass 3, count 2 2006.173.15:53:55.36#ibcon#read 6, iclass 3, count 2 2006.173.15:53:55.36#ibcon#end of sib2, iclass 3, count 2 2006.173.15:53:55.36#ibcon#*mode == 0, iclass 3, count 2 2006.173.15:53:55.36#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.15:53:55.36#ibcon#[25=AT04-06\r\n] 2006.173.15:53:55.36#ibcon#*before write, iclass 3, count 2 2006.173.15:53:55.36#ibcon#enter sib2, iclass 3, count 2 2006.173.15:53:55.36#ibcon#flushed, iclass 3, count 2 2006.173.15:53:55.36#ibcon#about to write, iclass 3, count 2 2006.173.15:53:55.36#ibcon#wrote, iclass 3, count 2 2006.173.15:53:55.36#ibcon#about to read 3, iclass 3, count 2 2006.173.15:53:55.39#ibcon#read 3, iclass 3, count 2 2006.173.15:53:55.39#ibcon#about to read 4, iclass 3, count 2 2006.173.15:53:55.39#ibcon#read 4, iclass 3, count 2 2006.173.15:53:55.39#ibcon#about to read 5, iclass 3, count 2 2006.173.15:53:55.39#ibcon#read 5, iclass 3, count 2 2006.173.15:53:55.39#ibcon#about to read 6, iclass 3, count 2 2006.173.15:53:55.39#ibcon#read 6, iclass 3, count 2 2006.173.15:53:55.39#ibcon#end of sib2, iclass 3, count 2 2006.173.15:53:55.39#ibcon#*after write, iclass 3, count 2 2006.173.15:53:55.39#ibcon#*before return 0, iclass 3, count 2 2006.173.15:53:55.39#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.15:53:55.39#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.15:53:55.39#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.15:53:55.39#ibcon#ireg 7 cls_cnt 0 2006.173.15:53:55.39#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.15:53:55.51#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.15:53:55.51#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.15:53:55.51#ibcon#enter wrdev, iclass 3, count 0 2006.173.15:53:55.51#ibcon#first serial, iclass 3, count 0 2006.173.15:53:55.51#ibcon#enter sib2, iclass 3, count 0 2006.173.15:53:55.51#ibcon#flushed, iclass 3, count 0 2006.173.15:53:55.51#ibcon#about to write, iclass 3, count 0 2006.173.15:53:55.51#ibcon#wrote, iclass 3, count 0 2006.173.15:53:55.51#ibcon#about to read 3, iclass 3, count 0 2006.173.15:53:55.53#ibcon#read 3, iclass 3, count 0 2006.173.15:53:55.53#ibcon#about to read 4, iclass 3, count 0 2006.173.15:53:55.53#ibcon#read 4, iclass 3, count 0 2006.173.15:53:55.53#ibcon#about to read 5, iclass 3, count 0 2006.173.15:53:55.53#ibcon#read 5, iclass 3, count 0 2006.173.15:53:55.53#ibcon#about to read 6, iclass 3, count 0 2006.173.15:53:55.53#ibcon#read 6, iclass 3, count 0 2006.173.15:53:55.53#ibcon#end of sib2, iclass 3, count 0 2006.173.15:53:55.53#ibcon#*mode == 0, iclass 3, count 0 2006.173.15:53:55.53#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.15:53:55.53#ibcon#[25=USB\r\n] 2006.173.15:53:55.53#ibcon#*before write, iclass 3, count 0 2006.173.15:53:55.53#ibcon#enter sib2, iclass 3, count 0 2006.173.15:53:55.53#ibcon#flushed, iclass 3, count 0 2006.173.15:53:55.53#ibcon#about to write, iclass 3, count 0 2006.173.15:53:55.53#ibcon#wrote, iclass 3, count 0 2006.173.15:53:55.53#ibcon#about to read 3, iclass 3, count 0 2006.173.15:53:55.56#ibcon#read 3, iclass 3, count 0 2006.173.15:53:55.56#ibcon#about to read 4, iclass 3, count 0 2006.173.15:53:55.56#ibcon#read 4, iclass 3, count 0 2006.173.15:53:55.56#ibcon#about to read 5, iclass 3, count 0 2006.173.15:53:55.56#ibcon#read 5, iclass 3, count 0 2006.173.15:53:55.56#ibcon#about to read 6, iclass 3, count 0 2006.173.15:53:55.56#ibcon#read 6, iclass 3, count 0 2006.173.15:53:55.56#ibcon#end of sib2, iclass 3, count 0 2006.173.15:53:55.56#ibcon#*after write, iclass 3, count 0 2006.173.15:53:55.56#ibcon#*before return 0, iclass 3, count 0 2006.173.15:53:55.56#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.15:53:55.56#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.15:53:55.56#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.15:53:55.56#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.15:53:55.56$vck44/valo=5,734.99 2006.173.15:53:55.56#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.15:53:55.56#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.15:53:55.56#ibcon#ireg 17 cls_cnt 0 2006.173.15:53:55.56#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.15:53:55.56#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.15:53:55.56#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.15:53:55.56#ibcon#enter wrdev, iclass 5, count 0 2006.173.15:53:55.56#ibcon#first serial, iclass 5, count 0 2006.173.15:53:55.56#ibcon#enter sib2, iclass 5, count 0 2006.173.15:53:55.56#ibcon#flushed, iclass 5, count 0 2006.173.15:53:55.56#ibcon#about to write, iclass 5, count 0 2006.173.15:53:55.56#ibcon#wrote, iclass 5, count 0 2006.173.15:53:55.56#ibcon#about to read 3, iclass 5, count 0 2006.173.15:53:55.58#ibcon#read 3, iclass 5, count 0 2006.173.15:53:55.58#ibcon#about to read 4, iclass 5, count 0 2006.173.15:53:55.58#ibcon#read 4, iclass 5, count 0 2006.173.15:53:55.58#ibcon#about to read 5, iclass 5, count 0 2006.173.15:53:55.58#ibcon#read 5, iclass 5, count 0 2006.173.15:53:55.58#ibcon#about to read 6, iclass 5, count 0 2006.173.15:53:55.58#ibcon#read 6, iclass 5, count 0 2006.173.15:53:55.58#ibcon#end of sib2, iclass 5, count 0 2006.173.15:53:55.58#ibcon#*mode == 0, iclass 5, count 0 2006.173.15:53:55.58#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.15:53:55.58#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.15:53:55.58#ibcon#*before write, iclass 5, count 0 2006.173.15:53:55.58#ibcon#enter sib2, iclass 5, count 0 2006.173.15:53:55.58#ibcon#flushed, iclass 5, count 0 2006.173.15:53:55.58#ibcon#about to write, iclass 5, count 0 2006.173.15:53:55.58#ibcon#wrote, iclass 5, count 0 2006.173.15:53:55.58#ibcon#about to read 3, iclass 5, count 0 2006.173.15:53:55.62#ibcon#read 3, iclass 5, count 0 2006.173.15:53:55.62#ibcon#about to read 4, iclass 5, count 0 2006.173.15:53:55.62#ibcon#read 4, iclass 5, count 0 2006.173.15:53:55.62#ibcon#about to read 5, iclass 5, count 0 2006.173.15:53:55.62#ibcon#read 5, iclass 5, count 0 2006.173.15:53:55.62#ibcon#about to read 6, iclass 5, count 0 2006.173.15:53:55.62#ibcon#read 6, iclass 5, count 0 2006.173.15:53:55.62#ibcon#end of sib2, iclass 5, count 0 2006.173.15:53:55.62#ibcon#*after write, iclass 5, count 0 2006.173.15:53:55.62#ibcon#*before return 0, iclass 5, count 0 2006.173.15:53:55.62#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.15:53:55.62#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.15:53:55.62#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.15:53:55.62#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.15:53:55.62$vck44/va=5,4 2006.173.15:53:55.62#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.173.15:53:55.62#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.173.15:53:55.62#ibcon#ireg 11 cls_cnt 2 2006.173.15:53:55.62#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.15:53:55.68#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.15:53:55.68#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.15:53:55.68#ibcon#enter wrdev, iclass 7, count 2 2006.173.15:53:55.68#ibcon#first serial, iclass 7, count 2 2006.173.15:53:55.68#ibcon#enter sib2, iclass 7, count 2 2006.173.15:53:55.68#ibcon#flushed, iclass 7, count 2 2006.173.15:53:55.68#ibcon#about to write, iclass 7, count 2 2006.173.15:53:55.68#ibcon#wrote, iclass 7, count 2 2006.173.15:53:55.68#ibcon#about to read 3, iclass 7, count 2 2006.173.15:53:55.70#ibcon#read 3, iclass 7, count 2 2006.173.15:53:55.70#ibcon#about to read 4, iclass 7, count 2 2006.173.15:53:55.70#ibcon#read 4, iclass 7, count 2 2006.173.15:53:55.70#ibcon#about to read 5, iclass 7, count 2 2006.173.15:53:55.70#ibcon#read 5, iclass 7, count 2 2006.173.15:53:55.70#ibcon#about to read 6, iclass 7, count 2 2006.173.15:53:55.70#ibcon#read 6, iclass 7, count 2 2006.173.15:53:55.70#ibcon#end of sib2, iclass 7, count 2 2006.173.15:53:55.70#ibcon#*mode == 0, iclass 7, count 2 2006.173.15:53:55.70#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.173.15:53:55.70#ibcon#[25=AT05-04\r\n] 2006.173.15:53:55.70#ibcon#*before write, iclass 7, count 2 2006.173.15:53:55.70#ibcon#enter sib2, iclass 7, count 2 2006.173.15:53:55.70#ibcon#flushed, iclass 7, count 2 2006.173.15:53:55.70#ibcon#about to write, iclass 7, count 2 2006.173.15:53:55.70#ibcon#wrote, iclass 7, count 2 2006.173.15:53:55.70#ibcon#about to read 3, iclass 7, count 2 2006.173.15:53:55.73#ibcon#read 3, iclass 7, count 2 2006.173.15:53:55.73#ibcon#about to read 4, iclass 7, count 2 2006.173.15:53:55.73#ibcon#read 4, iclass 7, count 2 2006.173.15:53:55.73#ibcon#about to read 5, iclass 7, count 2 2006.173.15:53:55.73#ibcon#read 5, iclass 7, count 2 2006.173.15:53:55.73#ibcon#about to read 6, iclass 7, count 2 2006.173.15:53:55.73#ibcon#read 6, iclass 7, count 2 2006.173.15:53:55.73#ibcon#end of sib2, iclass 7, count 2 2006.173.15:53:55.73#ibcon#*after write, iclass 7, count 2 2006.173.15:53:55.73#ibcon#*before return 0, iclass 7, count 2 2006.173.15:53:55.73#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.15:53:55.73#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.173.15:53:55.73#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.173.15:53:55.73#ibcon#ireg 7 cls_cnt 0 2006.173.15:53:55.73#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.15:53:55.85#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.15:53:55.85#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.15:53:55.85#ibcon#enter wrdev, iclass 7, count 0 2006.173.15:53:55.85#ibcon#first serial, iclass 7, count 0 2006.173.15:53:55.85#ibcon#enter sib2, iclass 7, count 0 2006.173.15:53:55.85#ibcon#flushed, iclass 7, count 0 2006.173.15:53:55.85#ibcon#about to write, iclass 7, count 0 2006.173.15:53:55.85#ibcon#wrote, iclass 7, count 0 2006.173.15:53:55.85#ibcon#about to read 3, iclass 7, count 0 2006.173.15:53:55.87#ibcon#read 3, iclass 7, count 0 2006.173.15:53:55.87#ibcon#about to read 4, iclass 7, count 0 2006.173.15:53:55.87#ibcon#read 4, iclass 7, count 0 2006.173.15:53:55.87#ibcon#about to read 5, iclass 7, count 0 2006.173.15:53:55.87#ibcon#read 5, iclass 7, count 0 2006.173.15:53:55.87#ibcon#about to read 6, iclass 7, count 0 2006.173.15:53:55.87#ibcon#read 6, iclass 7, count 0 2006.173.15:53:55.87#ibcon#end of sib2, iclass 7, count 0 2006.173.15:53:55.87#ibcon#*mode == 0, iclass 7, count 0 2006.173.15:53:55.87#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.15:53:55.87#ibcon#[25=USB\r\n] 2006.173.15:53:55.87#ibcon#*before write, iclass 7, count 0 2006.173.15:53:55.87#ibcon#enter sib2, iclass 7, count 0 2006.173.15:53:55.87#ibcon#flushed, iclass 7, count 0 2006.173.15:53:55.87#ibcon#about to write, iclass 7, count 0 2006.173.15:53:55.87#ibcon#wrote, iclass 7, count 0 2006.173.15:53:55.87#ibcon#about to read 3, iclass 7, count 0 2006.173.15:53:55.90#ibcon#read 3, iclass 7, count 0 2006.173.15:53:55.90#ibcon#about to read 4, iclass 7, count 0 2006.173.15:53:55.90#ibcon#read 4, iclass 7, count 0 2006.173.15:53:55.90#ibcon#about to read 5, iclass 7, count 0 2006.173.15:53:55.90#ibcon#read 5, iclass 7, count 0 2006.173.15:53:55.90#ibcon#about to read 6, iclass 7, count 0 2006.173.15:53:55.90#ibcon#read 6, iclass 7, count 0 2006.173.15:53:55.90#ibcon#end of sib2, iclass 7, count 0 2006.173.15:53:55.90#ibcon#*after write, iclass 7, count 0 2006.173.15:53:55.90#ibcon#*before return 0, iclass 7, count 0 2006.173.15:53:55.90#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.15:53:55.90#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.173.15:53:55.90#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.15:53:55.90#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.15:53:55.90$vck44/valo=6,814.99 2006.173.15:53:55.90#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.15:53:55.90#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.15:53:55.90#ibcon#ireg 17 cls_cnt 0 2006.173.15:53:55.90#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.15:53:55.90#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.15:53:55.90#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.15:53:55.90#ibcon#enter wrdev, iclass 11, count 0 2006.173.15:53:55.90#ibcon#first serial, iclass 11, count 0 2006.173.15:53:55.90#ibcon#enter sib2, iclass 11, count 0 2006.173.15:53:55.90#ibcon#flushed, iclass 11, count 0 2006.173.15:53:55.90#ibcon#about to write, iclass 11, count 0 2006.173.15:53:55.90#ibcon#wrote, iclass 11, count 0 2006.173.15:53:55.90#ibcon#about to read 3, iclass 11, count 0 2006.173.15:53:55.92#ibcon#read 3, iclass 11, count 0 2006.173.15:53:55.92#ibcon#about to read 4, iclass 11, count 0 2006.173.15:53:55.92#ibcon#read 4, iclass 11, count 0 2006.173.15:53:55.92#ibcon#about to read 5, iclass 11, count 0 2006.173.15:53:55.92#ibcon#read 5, iclass 11, count 0 2006.173.15:53:55.92#ibcon#about to read 6, iclass 11, count 0 2006.173.15:53:55.92#ibcon#read 6, iclass 11, count 0 2006.173.15:53:55.92#ibcon#end of sib2, iclass 11, count 0 2006.173.15:53:55.92#ibcon#*mode == 0, iclass 11, count 0 2006.173.15:53:55.92#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.15:53:55.92#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.15:53:55.92#ibcon#*before write, iclass 11, count 0 2006.173.15:53:55.92#ibcon#enter sib2, iclass 11, count 0 2006.173.15:53:55.92#ibcon#flushed, iclass 11, count 0 2006.173.15:53:55.92#ibcon#about to write, iclass 11, count 0 2006.173.15:53:55.92#ibcon#wrote, iclass 11, count 0 2006.173.15:53:55.92#ibcon#about to read 3, iclass 11, count 0 2006.173.15:53:55.96#ibcon#read 3, iclass 11, count 0 2006.173.15:53:55.96#ibcon#about to read 4, iclass 11, count 0 2006.173.15:53:55.96#ibcon#read 4, iclass 11, count 0 2006.173.15:53:55.96#ibcon#about to read 5, iclass 11, count 0 2006.173.15:53:55.96#ibcon#read 5, iclass 11, count 0 2006.173.15:53:55.96#ibcon#about to read 6, iclass 11, count 0 2006.173.15:53:55.96#ibcon#read 6, iclass 11, count 0 2006.173.15:53:55.96#ibcon#end of sib2, iclass 11, count 0 2006.173.15:53:55.96#ibcon#*after write, iclass 11, count 0 2006.173.15:53:55.96#ibcon#*before return 0, iclass 11, count 0 2006.173.15:53:55.96#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.15:53:55.96#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.15:53:55.96#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.15:53:55.96#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.15:53:55.96$vck44/va=6,3 2006.173.15:53:55.96#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.173.15:53:55.96#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.173.15:53:55.96#ibcon#ireg 11 cls_cnt 2 2006.173.15:53:55.96#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.15:53:56.02#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.15:53:56.02#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.15:53:56.02#ibcon#enter wrdev, iclass 13, count 2 2006.173.15:53:56.02#ibcon#first serial, iclass 13, count 2 2006.173.15:53:56.02#ibcon#enter sib2, iclass 13, count 2 2006.173.15:53:56.02#ibcon#flushed, iclass 13, count 2 2006.173.15:53:56.02#ibcon#about to write, iclass 13, count 2 2006.173.15:53:56.02#ibcon#wrote, iclass 13, count 2 2006.173.15:53:56.02#ibcon#about to read 3, iclass 13, count 2 2006.173.15:53:56.04#ibcon#read 3, iclass 13, count 2 2006.173.15:53:56.04#ibcon#about to read 4, iclass 13, count 2 2006.173.15:53:56.04#ibcon#read 4, iclass 13, count 2 2006.173.15:53:56.04#ibcon#about to read 5, iclass 13, count 2 2006.173.15:53:56.04#ibcon#read 5, iclass 13, count 2 2006.173.15:53:56.04#ibcon#about to read 6, iclass 13, count 2 2006.173.15:53:56.04#ibcon#read 6, iclass 13, count 2 2006.173.15:53:56.04#ibcon#end of sib2, iclass 13, count 2 2006.173.15:53:56.04#ibcon#*mode == 0, iclass 13, count 2 2006.173.15:53:56.04#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.173.15:53:56.04#ibcon#[25=AT06-03\r\n] 2006.173.15:53:56.04#ibcon#*before write, iclass 13, count 2 2006.173.15:53:56.04#ibcon#enter sib2, iclass 13, count 2 2006.173.15:53:56.04#ibcon#flushed, iclass 13, count 2 2006.173.15:53:56.04#ibcon#about to write, iclass 13, count 2 2006.173.15:53:56.04#ibcon#wrote, iclass 13, count 2 2006.173.15:53:56.04#ibcon#about to read 3, iclass 13, count 2 2006.173.15:53:56.07#ibcon#read 3, iclass 13, count 2 2006.173.15:53:56.07#ibcon#about to read 4, iclass 13, count 2 2006.173.15:53:56.07#ibcon#read 4, iclass 13, count 2 2006.173.15:53:56.07#ibcon#about to read 5, iclass 13, count 2 2006.173.15:53:56.07#ibcon#read 5, iclass 13, count 2 2006.173.15:53:56.07#ibcon#about to read 6, iclass 13, count 2 2006.173.15:53:56.07#ibcon#read 6, iclass 13, count 2 2006.173.15:53:56.07#ibcon#end of sib2, iclass 13, count 2 2006.173.15:53:56.07#ibcon#*after write, iclass 13, count 2 2006.173.15:53:56.07#ibcon#*before return 0, iclass 13, count 2 2006.173.15:53:56.07#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.15:53:56.07#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.173.15:53:56.07#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.173.15:53:56.07#ibcon#ireg 7 cls_cnt 0 2006.173.15:53:56.07#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.15:53:56.19#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.15:53:56.19#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.15:53:56.19#ibcon#enter wrdev, iclass 13, count 0 2006.173.15:53:56.19#ibcon#first serial, iclass 13, count 0 2006.173.15:53:56.19#ibcon#enter sib2, iclass 13, count 0 2006.173.15:53:56.19#ibcon#flushed, iclass 13, count 0 2006.173.15:53:56.19#ibcon#about to write, iclass 13, count 0 2006.173.15:53:56.19#ibcon#wrote, iclass 13, count 0 2006.173.15:53:56.19#ibcon#about to read 3, iclass 13, count 0 2006.173.15:53:56.21#ibcon#read 3, iclass 13, count 0 2006.173.15:53:56.21#ibcon#about to read 4, iclass 13, count 0 2006.173.15:53:56.21#ibcon#read 4, iclass 13, count 0 2006.173.15:53:56.21#ibcon#about to read 5, iclass 13, count 0 2006.173.15:53:56.21#ibcon#read 5, iclass 13, count 0 2006.173.15:53:56.21#ibcon#about to read 6, iclass 13, count 0 2006.173.15:53:56.21#ibcon#read 6, iclass 13, count 0 2006.173.15:53:56.21#ibcon#end of sib2, iclass 13, count 0 2006.173.15:53:56.21#ibcon#*mode == 0, iclass 13, count 0 2006.173.15:53:56.21#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.15:53:56.21#ibcon#[25=USB\r\n] 2006.173.15:53:56.21#ibcon#*before write, iclass 13, count 0 2006.173.15:53:56.21#ibcon#enter sib2, iclass 13, count 0 2006.173.15:53:56.21#ibcon#flushed, iclass 13, count 0 2006.173.15:53:56.21#ibcon#about to write, iclass 13, count 0 2006.173.15:53:56.21#ibcon#wrote, iclass 13, count 0 2006.173.15:53:56.21#ibcon#about to read 3, iclass 13, count 0 2006.173.15:53:56.24#ibcon#read 3, iclass 13, count 0 2006.173.15:53:56.24#ibcon#about to read 4, iclass 13, count 0 2006.173.15:53:56.24#ibcon#read 4, iclass 13, count 0 2006.173.15:53:56.24#ibcon#about to read 5, iclass 13, count 0 2006.173.15:53:56.24#ibcon#read 5, iclass 13, count 0 2006.173.15:53:56.24#ibcon#about to read 6, iclass 13, count 0 2006.173.15:53:56.24#ibcon#read 6, iclass 13, count 0 2006.173.15:53:56.24#ibcon#end of sib2, iclass 13, count 0 2006.173.15:53:56.24#ibcon#*after write, iclass 13, count 0 2006.173.15:53:56.24#ibcon#*before return 0, iclass 13, count 0 2006.173.15:53:56.24#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.15:53:56.24#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.173.15:53:56.24#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.15:53:56.24#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.15:53:56.24$vck44/valo=7,864.99 2006.173.15:53:56.24#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.15:53:56.24#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.15:53:56.24#ibcon#ireg 17 cls_cnt 0 2006.173.15:53:56.24#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.15:53:56.24#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.15:53:56.24#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.15:53:56.24#ibcon#enter wrdev, iclass 15, count 0 2006.173.15:53:56.24#ibcon#first serial, iclass 15, count 0 2006.173.15:53:56.24#ibcon#enter sib2, iclass 15, count 0 2006.173.15:53:56.24#ibcon#flushed, iclass 15, count 0 2006.173.15:53:56.24#ibcon#about to write, iclass 15, count 0 2006.173.15:53:56.24#ibcon#wrote, iclass 15, count 0 2006.173.15:53:56.24#ibcon#about to read 3, iclass 15, count 0 2006.173.15:53:56.26#ibcon#read 3, iclass 15, count 0 2006.173.15:53:56.26#ibcon#about to read 4, iclass 15, count 0 2006.173.15:53:56.26#ibcon#read 4, iclass 15, count 0 2006.173.15:53:56.26#ibcon#about to read 5, iclass 15, count 0 2006.173.15:53:56.26#ibcon#read 5, iclass 15, count 0 2006.173.15:53:56.26#ibcon#about to read 6, iclass 15, count 0 2006.173.15:53:56.26#ibcon#read 6, iclass 15, count 0 2006.173.15:53:56.26#ibcon#end of sib2, iclass 15, count 0 2006.173.15:53:56.26#ibcon#*mode == 0, iclass 15, count 0 2006.173.15:53:56.26#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.15:53:56.26#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.15:53:56.26#ibcon#*before write, iclass 15, count 0 2006.173.15:53:56.26#ibcon#enter sib2, iclass 15, count 0 2006.173.15:53:56.26#ibcon#flushed, iclass 15, count 0 2006.173.15:53:56.26#ibcon#about to write, iclass 15, count 0 2006.173.15:53:56.26#ibcon#wrote, iclass 15, count 0 2006.173.15:53:56.26#ibcon#about to read 3, iclass 15, count 0 2006.173.15:53:56.30#ibcon#read 3, iclass 15, count 0 2006.173.15:53:56.30#ibcon#about to read 4, iclass 15, count 0 2006.173.15:53:56.30#ibcon#read 4, iclass 15, count 0 2006.173.15:53:56.30#ibcon#about to read 5, iclass 15, count 0 2006.173.15:53:56.30#ibcon#read 5, iclass 15, count 0 2006.173.15:53:56.30#ibcon#about to read 6, iclass 15, count 0 2006.173.15:53:56.30#ibcon#read 6, iclass 15, count 0 2006.173.15:53:56.30#ibcon#end of sib2, iclass 15, count 0 2006.173.15:53:56.30#ibcon#*after write, iclass 15, count 0 2006.173.15:53:56.30#ibcon#*before return 0, iclass 15, count 0 2006.173.15:53:56.30#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.15:53:56.30#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.15:53:56.30#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.15:53:56.30#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.15:53:56.30$vck44/va=7,4 2006.173.15:53:56.30#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.15:53:56.30#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.15:53:56.30#ibcon#ireg 11 cls_cnt 2 2006.173.15:53:56.30#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.15:53:56.36#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.15:53:56.36#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.15:53:56.36#ibcon#enter wrdev, iclass 17, count 2 2006.173.15:53:56.36#ibcon#first serial, iclass 17, count 2 2006.173.15:53:56.36#ibcon#enter sib2, iclass 17, count 2 2006.173.15:53:56.36#ibcon#flushed, iclass 17, count 2 2006.173.15:53:56.36#ibcon#about to write, iclass 17, count 2 2006.173.15:53:56.36#ibcon#wrote, iclass 17, count 2 2006.173.15:53:56.36#ibcon#about to read 3, iclass 17, count 2 2006.173.15:53:56.38#ibcon#read 3, iclass 17, count 2 2006.173.15:53:56.38#ibcon#about to read 4, iclass 17, count 2 2006.173.15:53:56.38#ibcon#read 4, iclass 17, count 2 2006.173.15:53:56.38#ibcon#about to read 5, iclass 17, count 2 2006.173.15:53:56.38#ibcon#read 5, iclass 17, count 2 2006.173.15:53:56.38#ibcon#about to read 6, iclass 17, count 2 2006.173.15:53:56.38#ibcon#read 6, iclass 17, count 2 2006.173.15:53:56.38#ibcon#end of sib2, iclass 17, count 2 2006.173.15:53:56.38#ibcon#*mode == 0, iclass 17, count 2 2006.173.15:53:56.38#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.15:53:56.38#ibcon#[25=AT07-04\r\n] 2006.173.15:53:56.38#ibcon#*before write, iclass 17, count 2 2006.173.15:53:56.38#ibcon#enter sib2, iclass 17, count 2 2006.173.15:53:56.38#ibcon#flushed, iclass 17, count 2 2006.173.15:53:56.38#ibcon#about to write, iclass 17, count 2 2006.173.15:53:56.38#ibcon#wrote, iclass 17, count 2 2006.173.15:53:56.38#ibcon#about to read 3, iclass 17, count 2 2006.173.15:53:56.41#ibcon#read 3, iclass 17, count 2 2006.173.15:53:56.41#ibcon#about to read 4, iclass 17, count 2 2006.173.15:53:56.41#ibcon#read 4, iclass 17, count 2 2006.173.15:53:56.41#ibcon#about to read 5, iclass 17, count 2 2006.173.15:53:56.41#ibcon#read 5, iclass 17, count 2 2006.173.15:53:56.41#ibcon#about to read 6, iclass 17, count 2 2006.173.15:53:56.41#ibcon#read 6, iclass 17, count 2 2006.173.15:53:56.41#ibcon#end of sib2, iclass 17, count 2 2006.173.15:53:56.41#ibcon#*after write, iclass 17, count 2 2006.173.15:53:56.41#ibcon#*before return 0, iclass 17, count 2 2006.173.15:53:56.41#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.15:53:56.41#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.15:53:56.41#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.15:53:56.41#ibcon#ireg 7 cls_cnt 0 2006.173.15:53:56.41#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.15:53:56.53#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.15:53:56.53#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.15:53:56.53#ibcon#enter wrdev, iclass 17, count 0 2006.173.15:53:56.53#ibcon#first serial, iclass 17, count 0 2006.173.15:53:56.53#ibcon#enter sib2, iclass 17, count 0 2006.173.15:53:56.53#ibcon#flushed, iclass 17, count 0 2006.173.15:53:56.53#ibcon#about to write, iclass 17, count 0 2006.173.15:53:56.53#ibcon#wrote, iclass 17, count 0 2006.173.15:53:56.53#ibcon#about to read 3, iclass 17, count 0 2006.173.15:53:56.55#ibcon#read 3, iclass 17, count 0 2006.173.15:53:56.55#ibcon#about to read 4, iclass 17, count 0 2006.173.15:53:56.55#ibcon#read 4, iclass 17, count 0 2006.173.15:53:56.55#ibcon#about to read 5, iclass 17, count 0 2006.173.15:53:56.55#ibcon#read 5, iclass 17, count 0 2006.173.15:53:56.55#ibcon#about to read 6, iclass 17, count 0 2006.173.15:53:56.55#ibcon#read 6, iclass 17, count 0 2006.173.15:53:56.55#ibcon#end of sib2, iclass 17, count 0 2006.173.15:53:56.55#ibcon#*mode == 0, iclass 17, count 0 2006.173.15:53:56.55#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.15:53:56.55#ibcon#[25=USB\r\n] 2006.173.15:53:56.55#ibcon#*before write, iclass 17, count 0 2006.173.15:53:56.55#ibcon#enter sib2, iclass 17, count 0 2006.173.15:53:56.55#ibcon#flushed, iclass 17, count 0 2006.173.15:53:56.55#ibcon#about to write, iclass 17, count 0 2006.173.15:53:56.55#ibcon#wrote, iclass 17, count 0 2006.173.15:53:56.55#ibcon#about to read 3, iclass 17, count 0 2006.173.15:53:56.58#ibcon#read 3, iclass 17, count 0 2006.173.15:53:56.58#ibcon#about to read 4, iclass 17, count 0 2006.173.15:53:56.58#ibcon#read 4, iclass 17, count 0 2006.173.15:53:56.58#ibcon#about to read 5, iclass 17, count 0 2006.173.15:53:56.58#ibcon#read 5, iclass 17, count 0 2006.173.15:53:56.58#ibcon#about to read 6, iclass 17, count 0 2006.173.15:53:56.58#ibcon#read 6, iclass 17, count 0 2006.173.15:53:56.58#ibcon#end of sib2, iclass 17, count 0 2006.173.15:53:56.58#ibcon#*after write, iclass 17, count 0 2006.173.15:53:56.58#ibcon#*before return 0, iclass 17, count 0 2006.173.15:53:56.58#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.15:53:56.58#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.15:53:56.58#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.15:53:56.58#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.15:53:56.58$vck44/valo=8,884.99 2006.173.15:53:56.58#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.15:53:56.58#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.15:53:56.58#ibcon#ireg 17 cls_cnt 0 2006.173.15:53:56.58#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.15:53:56.58#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.15:53:56.58#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.15:53:56.58#ibcon#enter wrdev, iclass 19, count 0 2006.173.15:53:56.58#ibcon#first serial, iclass 19, count 0 2006.173.15:53:56.58#ibcon#enter sib2, iclass 19, count 0 2006.173.15:53:56.58#ibcon#flushed, iclass 19, count 0 2006.173.15:53:56.58#ibcon#about to write, iclass 19, count 0 2006.173.15:53:56.58#ibcon#wrote, iclass 19, count 0 2006.173.15:53:56.58#ibcon#about to read 3, iclass 19, count 0 2006.173.15:53:56.60#ibcon#read 3, iclass 19, count 0 2006.173.15:53:56.60#ibcon#about to read 4, iclass 19, count 0 2006.173.15:53:56.60#ibcon#read 4, iclass 19, count 0 2006.173.15:53:56.60#ibcon#about to read 5, iclass 19, count 0 2006.173.15:53:56.60#ibcon#read 5, iclass 19, count 0 2006.173.15:53:56.60#ibcon#about to read 6, iclass 19, count 0 2006.173.15:53:56.60#ibcon#read 6, iclass 19, count 0 2006.173.15:53:56.60#ibcon#end of sib2, iclass 19, count 0 2006.173.15:53:56.60#ibcon#*mode == 0, iclass 19, count 0 2006.173.15:53:56.60#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.15:53:56.60#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.15:53:56.60#ibcon#*before write, iclass 19, count 0 2006.173.15:53:56.60#ibcon#enter sib2, iclass 19, count 0 2006.173.15:53:56.60#ibcon#flushed, iclass 19, count 0 2006.173.15:53:56.60#ibcon#about to write, iclass 19, count 0 2006.173.15:53:56.60#ibcon#wrote, iclass 19, count 0 2006.173.15:53:56.60#ibcon#about to read 3, iclass 19, count 0 2006.173.15:53:56.64#ibcon#read 3, iclass 19, count 0 2006.173.15:53:56.64#ibcon#about to read 4, iclass 19, count 0 2006.173.15:53:56.64#ibcon#read 4, iclass 19, count 0 2006.173.15:53:56.64#ibcon#about to read 5, iclass 19, count 0 2006.173.15:53:56.64#ibcon#read 5, iclass 19, count 0 2006.173.15:53:56.64#ibcon#about to read 6, iclass 19, count 0 2006.173.15:53:56.64#ibcon#read 6, iclass 19, count 0 2006.173.15:53:56.64#ibcon#end of sib2, iclass 19, count 0 2006.173.15:53:56.64#ibcon#*after write, iclass 19, count 0 2006.173.15:53:56.64#ibcon#*before return 0, iclass 19, count 0 2006.173.15:53:56.64#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.15:53:56.64#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.15:53:56.64#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.15:53:56.64#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.15:53:56.64$vck44/va=8,4 2006.173.15:53:56.64#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.15:53:56.64#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.15:53:56.64#ibcon#ireg 11 cls_cnt 2 2006.173.15:53:56.64#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.15:53:56.70#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.15:53:56.70#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.15:53:56.70#ibcon#enter wrdev, iclass 21, count 2 2006.173.15:53:56.70#ibcon#first serial, iclass 21, count 2 2006.173.15:53:56.70#ibcon#enter sib2, iclass 21, count 2 2006.173.15:53:56.70#ibcon#flushed, iclass 21, count 2 2006.173.15:53:56.70#ibcon#about to write, iclass 21, count 2 2006.173.15:53:56.70#ibcon#wrote, iclass 21, count 2 2006.173.15:53:56.70#ibcon#about to read 3, iclass 21, count 2 2006.173.15:53:56.72#ibcon#read 3, iclass 21, count 2 2006.173.15:53:56.72#ibcon#about to read 4, iclass 21, count 2 2006.173.15:53:56.72#ibcon#read 4, iclass 21, count 2 2006.173.15:53:56.72#ibcon#about to read 5, iclass 21, count 2 2006.173.15:53:56.72#ibcon#read 5, iclass 21, count 2 2006.173.15:53:56.72#ibcon#about to read 6, iclass 21, count 2 2006.173.15:53:56.72#ibcon#read 6, iclass 21, count 2 2006.173.15:53:56.72#ibcon#end of sib2, iclass 21, count 2 2006.173.15:53:56.72#ibcon#*mode == 0, iclass 21, count 2 2006.173.15:53:56.72#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.15:53:56.72#ibcon#[25=AT08-04\r\n] 2006.173.15:53:56.72#ibcon#*before write, iclass 21, count 2 2006.173.15:53:56.72#ibcon#enter sib2, iclass 21, count 2 2006.173.15:53:56.72#ibcon#flushed, iclass 21, count 2 2006.173.15:53:56.72#ibcon#about to write, iclass 21, count 2 2006.173.15:53:56.72#ibcon#wrote, iclass 21, count 2 2006.173.15:53:56.72#ibcon#about to read 3, iclass 21, count 2 2006.173.15:53:56.75#ibcon#read 3, iclass 21, count 2 2006.173.15:53:56.75#ibcon#about to read 4, iclass 21, count 2 2006.173.15:53:56.75#ibcon#read 4, iclass 21, count 2 2006.173.15:53:56.75#ibcon#about to read 5, iclass 21, count 2 2006.173.15:53:56.75#ibcon#read 5, iclass 21, count 2 2006.173.15:53:56.75#ibcon#about to read 6, iclass 21, count 2 2006.173.15:53:56.75#ibcon#read 6, iclass 21, count 2 2006.173.15:53:56.75#ibcon#end of sib2, iclass 21, count 2 2006.173.15:53:56.75#ibcon#*after write, iclass 21, count 2 2006.173.15:53:56.75#ibcon#*before return 0, iclass 21, count 2 2006.173.15:53:56.75#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.15:53:56.75#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.15:53:56.75#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.15:53:56.75#ibcon#ireg 7 cls_cnt 0 2006.173.15:53:56.75#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.15:53:56.87#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.15:53:56.87#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.15:53:56.87#ibcon#enter wrdev, iclass 21, count 0 2006.173.15:53:56.87#ibcon#first serial, iclass 21, count 0 2006.173.15:53:56.87#ibcon#enter sib2, iclass 21, count 0 2006.173.15:53:56.87#ibcon#flushed, iclass 21, count 0 2006.173.15:53:56.87#ibcon#about to write, iclass 21, count 0 2006.173.15:53:56.87#ibcon#wrote, iclass 21, count 0 2006.173.15:53:56.87#ibcon#about to read 3, iclass 21, count 0 2006.173.15:53:56.89#ibcon#read 3, iclass 21, count 0 2006.173.15:53:56.89#ibcon#about to read 4, iclass 21, count 0 2006.173.15:53:56.89#ibcon#read 4, iclass 21, count 0 2006.173.15:53:56.89#ibcon#about to read 5, iclass 21, count 0 2006.173.15:53:56.89#ibcon#read 5, iclass 21, count 0 2006.173.15:53:56.89#ibcon#about to read 6, iclass 21, count 0 2006.173.15:53:56.89#ibcon#read 6, iclass 21, count 0 2006.173.15:53:56.89#ibcon#end of sib2, iclass 21, count 0 2006.173.15:53:56.89#ibcon#*mode == 0, iclass 21, count 0 2006.173.15:53:56.89#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.15:53:56.89#ibcon#[25=USB\r\n] 2006.173.15:53:56.89#ibcon#*before write, iclass 21, count 0 2006.173.15:53:56.89#ibcon#enter sib2, iclass 21, count 0 2006.173.15:53:56.89#ibcon#flushed, iclass 21, count 0 2006.173.15:53:56.89#ibcon#about to write, iclass 21, count 0 2006.173.15:53:56.89#ibcon#wrote, iclass 21, count 0 2006.173.15:53:56.89#ibcon#about to read 3, iclass 21, count 0 2006.173.15:53:56.92#ibcon#read 3, iclass 21, count 0 2006.173.15:53:56.92#ibcon#about to read 4, iclass 21, count 0 2006.173.15:53:56.92#ibcon#read 4, iclass 21, count 0 2006.173.15:53:56.92#ibcon#about to read 5, iclass 21, count 0 2006.173.15:53:56.92#ibcon#read 5, iclass 21, count 0 2006.173.15:53:56.92#ibcon#about to read 6, iclass 21, count 0 2006.173.15:53:56.92#ibcon#read 6, iclass 21, count 0 2006.173.15:53:56.92#ibcon#end of sib2, iclass 21, count 0 2006.173.15:53:56.92#ibcon#*after write, iclass 21, count 0 2006.173.15:53:56.92#ibcon#*before return 0, iclass 21, count 0 2006.173.15:53:56.92#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.15:53:56.92#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.15:53:56.92#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.15:53:56.92#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.15:53:56.92$vck44/vblo=1,629.99 2006.173.15:53:56.92#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.15:53:56.92#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.15:53:56.92#ibcon#ireg 17 cls_cnt 0 2006.173.15:53:56.92#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.15:53:56.92#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.15:53:56.92#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.15:53:56.92#ibcon#enter wrdev, iclass 23, count 0 2006.173.15:53:56.92#ibcon#first serial, iclass 23, count 0 2006.173.15:53:56.92#ibcon#enter sib2, iclass 23, count 0 2006.173.15:53:56.92#ibcon#flushed, iclass 23, count 0 2006.173.15:53:56.92#ibcon#about to write, iclass 23, count 0 2006.173.15:53:56.92#ibcon#wrote, iclass 23, count 0 2006.173.15:53:56.92#ibcon#about to read 3, iclass 23, count 0 2006.173.15:53:56.94#ibcon#read 3, iclass 23, count 0 2006.173.15:53:56.94#ibcon#about to read 4, iclass 23, count 0 2006.173.15:53:56.94#ibcon#read 4, iclass 23, count 0 2006.173.15:53:56.94#ibcon#about to read 5, iclass 23, count 0 2006.173.15:53:56.94#ibcon#read 5, iclass 23, count 0 2006.173.15:53:56.94#ibcon#about to read 6, iclass 23, count 0 2006.173.15:53:56.94#ibcon#read 6, iclass 23, count 0 2006.173.15:53:56.94#ibcon#end of sib2, iclass 23, count 0 2006.173.15:53:56.94#ibcon#*mode == 0, iclass 23, count 0 2006.173.15:53:56.94#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.15:53:56.94#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.15:53:56.94#ibcon#*before write, iclass 23, count 0 2006.173.15:53:56.94#ibcon#enter sib2, iclass 23, count 0 2006.173.15:53:56.94#ibcon#flushed, iclass 23, count 0 2006.173.15:53:56.94#ibcon#about to write, iclass 23, count 0 2006.173.15:53:56.94#ibcon#wrote, iclass 23, count 0 2006.173.15:53:56.94#ibcon#about to read 3, iclass 23, count 0 2006.173.15:53:56.98#ibcon#read 3, iclass 23, count 0 2006.173.15:53:56.98#ibcon#about to read 4, iclass 23, count 0 2006.173.15:53:56.98#ibcon#read 4, iclass 23, count 0 2006.173.15:53:56.98#ibcon#about to read 5, iclass 23, count 0 2006.173.15:53:56.98#ibcon#read 5, iclass 23, count 0 2006.173.15:53:56.98#ibcon#about to read 6, iclass 23, count 0 2006.173.15:53:56.98#ibcon#read 6, iclass 23, count 0 2006.173.15:53:56.98#ibcon#end of sib2, iclass 23, count 0 2006.173.15:53:56.98#ibcon#*after write, iclass 23, count 0 2006.173.15:53:56.98#ibcon#*before return 0, iclass 23, count 0 2006.173.15:53:56.98#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.15:53:56.98#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.15:53:56.98#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.15:53:56.98#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.15:53:56.98$vck44/vb=1,4 2006.173.15:53:56.98#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.15:53:56.98#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.15:53:56.98#ibcon#ireg 11 cls_cnt 2 2006.173.15:53:56.98#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.15:53:56.98#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.15:53:56.98#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.15:53:56.98#ibcon#enter wrdev, iclass 25, count 2 2006.173.15:53:56.98#ibcon#first serial, iclass 25, count 2 2006.173.15:53:56.98#ibcon#enter sib2, iclass 25, count 2 2006.173.15:53:56.98#ibcon#flushed, iclass 25, count 2 2006.173.15:53:56.98#ibcon#about to write, iclass 25, count 2 2006.173.15:53:56.98#ibcon#wrote, iclass 25, count 2 2006.173.15:53:56.98#ibcon#about to read 3, iclass 25, count 2 2006.173.15:53:57.00#ibcon#read 3, iclass 25, count 2 2006.173.15:53:57.00#ibcon#about to read 4, iclass 25, count 2 2006.173.15:53:57.00#ibcon#read 4, iclass 25, count 2 2006.173.15:53:57.00#ibcon#about to read 5, iclass 25, count 2 2006.173.15:53:57.00#ibcon#read 5, iclass 25, count 2 2006.173.15:53:57.00#ibcon#about to read 6, iclass 25, count 2 2006.173.15:53:57.00#ibcon#read 6, iclass 25, count 2 2006.173.15:53:57.00#ibcon#end of sib2, iclass 25, count 2 2006.173.15:53:57.00#ibcon#*mode == 0, iclass 25, count 2 2006.173.15:53:57.00#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.15:53:57.00#ibcon#[27=AT01-04\r\n] 2006.173.15:53:57.00#ibcon#*before write, iclass 25, count 2 2006.173.15:53:57.00#ibcon#enter sib2, iclass 25, count 2 2006.173.15:53:57.00#ibcon#flushed, iclass 25, count 2 2006.173.15:53:57.00#ibcon#about to write, iclass 25, count 2 2006.173.15:53:57.00#ibcon#wrote, iclass 25, count 2 2006.173.15:53:57.00#ibcon#about to read 3, iclass 25, count 2 2006.173.15:53:57.03#ibcon#read 3, iclass 25, count 2 2006.173.15:53:57.03#ibcon#about to read 4, iclass 25, count 2 2006.173.15:53:57.03#ibcon#read 4, iclass 25, count 2 2006.173.15:53:57.03#ibcon#about to read 5, iclass 25, count 2 2006.173.15:53:57.03#ibcon#read 5, iclass 25, count 2 2006.173.15:53:57.03#ibcon#about to read 6, iclass 25, count 2 2006.173.15:53:57.03#ibcon#read 6, iclass 25, count 2 2006.173.15:53:57.03#ibcon#end of sib2, iclass 25, count 2 2006.173.15:53:57.03#ibcon#*after write, iclass 25, count 2 2006.173.15:53:57.03#ibcon#*before return 0, iclass 25, count 2 2006.173.15:53:57.03#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.15:53:57.03#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.15:53:57.03#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.15:53:57.03#ibcon#ireg 7 cls_cnt 0 2006.173.15:53:57.03#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.15:53:57.15#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.15:53:57.15#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.15:53:57.15#ibcon#enter wrdev, iclass 25, count 0 2006.173.15:53:57.15#ibcon#first serial, iclass 25, count 0 2006.173.15:53:57.15#ibcon#enter sib2, iclass 25, count 0 2006.173.15:53:57.15#ibcon#flushed, iclass 25, count 0 2006.173.15:53:57.15#ibcon#about to write, iclass 25, count 0 2006.173.15:53:57.15#ibcon#wrote, iclass 25, count 0 2006.173.15:53:57.15#ibcon#about to read 3, iclass 25, count 0 2006.173.15:53:57.17#ibcon#read 3, iclass 25, count 0 2006.173.15:53:57.17#ibcon#about to read 4, iclass 25, count 0 2006.173.15:53:57.17#ibcon#read 4, iclass 25, count 0 2006.173.15:53:57.17#ibcon#about to read 5, iclass 25, count 0 2006.173.15:53:57.17#ibcon#read 5, iclass 25, count 0 2006.173.15:53:57.17#ibcon#about to read 6, iclass 25, count 0 2006.173.15:53:57.17#ibcon#read 6, iclass 25, count 0 2006.173.15:53:57.17#ibcon#end of sib2, iclass 25, count 0 2006.173.15:53:57.17#ibcon#*mode == 0, iclass 25, count 0 2006.173.15:53:57.17#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.15:53:57.17#ibcon#[27=USB\r\n] 2006.173.15:53:57.17#ibcon#*before write, iclass 25, count 0 2006.173.15:53:57.17#ibcon#enter sib2, iclass 25, count 0 2006.173.15:53:57.17#ibcon#flushed, iclass 25, count 0 2006.173.15:53:57.17#ibcon#about to write, iclass 25, count 0 2006.173.15:53:57.17#ibcon#wrote, iclass 25, count 0 2006.173.15:53:57.17#ibcon#about to read 3, iclass 25, count 0 2006.173.15:53:57.20#ibcon#read 3, iclass 25, count 0 2006.173.15:53:57.20#ibcon#about to read 4, iclass 25, count 0 2006.173.15:53:57.20#ibcon#read 4, iclass 25, count 0 2006.173.15:53:57.20#ibcon#about to read 5, iclass 25, count 0 2006.173.15:53:57.20#ibcon#read 5, iclass 25, count 0 2006.173.15:53:57.20#ibcon#about to read 6, iclass 25, count 0 2006.173.15:53:57.20#ibcon#read 6, iclass 25, count 0 2006.173.15:53:57.20#ibcon#end of sib2, iclass 25, count 0 2006.173.15:53:57.20#ibcon#*after write, iclass 25, count 0 2006.173.15:53:57.20#ibcon#*before return 0, iclass 25, count 0 2006.173.15:53:57.20#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.15:53:57.20#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.15:53:57.20#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.15:53:57.20#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.15:53:57.20$vck44/vblo=2,634.99 2006.173.15:53:57.20#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.15:53:57.20#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.15:53:57.20#ibcon#ireg 17 cls_cnt 0 2006.173.15:53:57.20#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.15:53:57.20#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.15:53:57.20#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.15:53:57.20#ibcon#enter wrdev, iclass 27, count 0 2006.173.15:53:57.20#ibcon#first serial, iclass 27, count 0 2006.173.15:53:57.20#ibcon#enter sib2, iclass 27, count 0 2006.173.15:53:57.20#ibcon#flushed, iclass 27, count 0 2006.173.15:53:57.20#ibcon#about to write, iclass 27, count 0 2006.173.15:53:57.20#ibcon#wrote, iclass 27, count 0 2006.173.15:53:57.20#ibcon#about to read 3, iclass 27, count 0 2006.173.15:53:57.22#ibcon#read 3, iclass 27, count 0 2006.173.15:53:57.22#ibcon#about to read 4, iclass 27, count 0 2006.173.15:53:57.22#ibcon#read 4, iclass 27, count 0 2006.173.15:53:57.22#ibcon#about to read 5, iclass 27, count 0 2006.173.15:53:57.22#ibcon#read 5, iclass 27, count 0 2006.173.15:53:57.22#ibcon#about to read 6, iclass 27, count 0 2006.173.15:53:57.22#ibcon#read 6, iclass 27, count 0 2006.173.15:53:57.22#ibcon#end of sib2, iclass 27, count 0 2006.173.15:53:57.22#ibcon#*mode == 0, iclass 27, count 0 2006.173.15:53:57.22#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.15:53:57.22#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.15:53:57.22#ibcon#*before write, iclass 27, count 0 2006.173.15:53:57.22#ibcon#enter sib2, iclass 27, count 0 2006.173.15:53:57.22#ibcon#flushed, iclass 27, count 0 2006.173.15:53:57.22#ibcon#about to write, iclass 27, count 0 2006.173.15:53:57.22#ibcon#wrote, iclass 27, count 0 2006.173.15:53:57.22#ibcon#about to read 3, iclass 27, count 0 2006.173.15:53:57.26#ibcon#read 3, iclass 27, count 0 2006.173.15:53:57.26#ibcon#about to read 4, iclass 27, count 0 2006.173.15:53:57.26#ibcon#read 4, iclass 27, count 0 2006.173.15:53:57.26#ibcon#about to read 5, iclass 27, count 0 2006.173.15:53:57.26#ibcon#read 5, iclass 27, count 0 2006.173.15:53:57.26#ibcon#about to read 6, iclass 27, count 0 2006.173.15:53:57.26#ibcon#read 6, iclass 27, count 0 2006.173.15:53:57.26#ibcon#end of sib2, iclass 27, count 0 2006.173.15:53:57.26#ibcon#*after write, iclass 27, count 0 2006.173.15:53:57.26#ibcon#*before return 0, iclass 27, count 0 2006.173.15:53:57.26#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.15:53:57.26#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.15:53:57.26#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.15:53:57.26#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.15:53:57.26$vck44/vb=2,4 2006.173.15:53:57.26#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.15:53:57.26#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.15:53:57.26#ibcon#ireg 11 cls_cnt 2 2006.173.15:53:57.26#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.15:53:57.32#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.15:53:57.32#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.15:53:57.32#ibcon#enter wrdev, iclass 29, count 2 2006.173.15:53:57.32#ibcon#first serial, iclass 29, count 2 2006.173.15:53:57.32#ibcon#enter sib2, iclass 29, count 2 2006.173.15:53:57.32#ibcon#flushed, iclass 29, count 2 2006.173.15:53:57.32#ibcon#about to write, iclass 29, count 2 2006.173.15:53:57.32#ibcon#wrote, iclass 29, count 2 2006.173.15:53:57.32#ibcon#about to read 3, iclass 29, count 2 2006.173.15:53:57.34#ibcon#read 3, iclass 29, count 2 2006.173.15:53:57.34#ibcon#about to read 4, iclass 29, count 2 2006.173.15:53:57.34#ibcon#read 4, iclass 29, count 2 2006.173.15:53:57.34#ibcon#about to read 5, iclass 29, count 2 2006.173.15:53:57.34#ibcon#read 5, iclass 29, count 2 2006.173.15:53:57.34#ibcon#about to read 6, iclass 29, count 2 2006.173.15:53:57.34#ibcon#read 6, iclass 29, count 2 2006.173.15:53:57.34#ibcon#end of sib2, iclass 29, count 2 2006.173.15:53:57.34#ibcon#*mode == 0, iclass 29, count 2 2006.173.15:53:57.34#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.15:53:57.34#ibcon#[27=AT02-04\r\n] 2006.173.15:53:57.34#ibcon#*before write, iclass 29, count 2 2006.173.15:53:57.34#ibcon#enter sib2, iclass 29, count 2 2006.173.15:53:57.34#ibcon#flushed, iclass 29, count 2 2006.173.15:53:57.34#ibcon#about to write, iclass 29, count 2 2006.173.15:53:57.34#ibcon#wrote, iclass 29, count 2 2006.173.15:53:57.34#ibcon#about to read 3, iclass 29, count 2 2006.173.15:53:57.37#ibcon#read 3, iclass 29, count 2 2006.173.15:53:57.37#ibcon#about to read 4, iclass 29, count 2 2006.173.15:53:57.37#ibcon#read 4, iclass 29, count 2 2006.173.15:53:57.37#ibcon#about to read 5, iclass 29, count 2 2006.173.15:53:57.37#ibcon#read 5, iclass 29, count 2 2006.173.15:53:57.37#ibcon#about to read 6, iclass 29, count 2 2006.173.15:53:57.37#ibcon#read 6, iclass 29, count 2 2006.173.15:53:57.37#ibcon#end of sib2, iclass 29, count 2 2006.173.15:53:57.37#ibcon#*after write, iclass 29, count 2 2006.173.15:53:57.37#ibcon#*before return 0, iclass 29, count 2 2006.173.15:53:57.37#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.15:53:57.37#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.15:53:57.37#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.15:53:57.37#ibcon#ireg 7 cls_cnt 0 2006.173.15:53:57.37#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.15:53:57.49#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.15:53:57.49#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.15:53:57.49#ibcon#enter wrdev, iclass 29, count 0 2006.173.15:53:57.49#ibcon#first serial, iclass 29, count 0 2006.173.15:53:57.49#ibcon#enter sib2, iclass 29, count 0 2006.173.15:53:57.49#ibcon#flushed, iclass 29, count 0 2006.173.15:53:57.49#ibcon#about to write, iclass 29, count 0 2006.173.15:53:57.49#ibcon#wrote, iclass 29, count 0 2006.173.15:53:57.49#ibcon#about to read 3, iclass 29, count 0 2006.173.15:53:57.51#ibcon#read 3, iclass 29, count 0 2006.173.15:53:57.51#ibcon#about to read 4, iclass 29, count 0 2006.173.15:53:57.51#ibcon#read 4, iclass 29, count 0 2006.173.15:53:57.51#ibcon#about to read 5, iclass 29, count 0 2006.173.15:53:57.51#ibcon#read 5, iclass 29, count 0 2006.173.15:53:57.51#ibcon#about to read 6, iclass 29, count 0 2006.173.15:53:57.51#ibcon#read 6, iclass 29, count 0 2006.173.15:53:57.51#ibcon#end of sib2, iclass 29, count 0 2006.173.15:53:57.51#ibcon#*mode == 0, iclass 29, count 0 2006.173.15:53:57.51#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.15:53:57.51#ibcon#[27=USB\r\n] 2006.173.15:53:57.51#ibcon#*before write, iclass 29, count 0 2006.173.15:53:57.51#ibcon#enter sib2, iclass 29, count 0 2006.173.15:53:57.51#ibcon#flushed, iclass 29, count 0 2006.173.15:53:57.51#ibcon#about to write, iclass 29, count 0 2006.173.15:53:57.51#ibcon#wrote, iclass 29, count 0 2006.173.15:53:57.51#ibcon#about to read 3, iclass 29, count 0 2006.173.15:53:57.54#ibcon#read 3, iclass 29, count 0 2006.173.15:53:57.54#ibcon#about to read 4, iclass 29, count 0 2006.173.15:53:57.54#ibcon#read 4, iclass 29, count 0 2006.173.15:53:57.54#ibcon#about to read 5, iclass 29, count 0 2006.173.15:53:57.54#ibcon#read 5, iclass 29, count 0 2006.173.15:53:57.54#ibcon#about to read 6, iclass 29, count 0 2006.173.15:53:57.54#ibcon#read 6, iclass 29, count 0 2006.173.15:53:57.54#ibcon#end of sib2, iclass 29, count 0 2006.173.15:53:57.54#ibcon#*after write, iclass 29, count 0 2006.173.15:53:57.54#ibcon#*before return 0, iclass 29, count 0 2006.173.15:53:57.54#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.15:53:57.54#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.15:53:57.54#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.15:53:57.54#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.15:53:57.54$vck44/vblo=3,649.99 2006.173.15:53:57.54#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.15:53:57.54#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.15:53:57.54#ibcon#ireg 17 cls_cnt 0 2006.173.15:53:57.54#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.15:53:57.54#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.15:53:57.54#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.15:53:57.54#ibcon#enter wrdev, iclass 31, count 0 2006.173.15:53:57.54#ibcon#first serial, iclass 31, count 0 2006.173.15:53:57.54#ibcon#enter sib2, iclass 31, count 0 2006.173.15:53:57.54#ibcon#flushed, iclass 31, count 0 2006.173.15:53:57.54#ibcon#about to write, iclass 31, count 0 2006.173.15:53:57.54#ibcon#wrote, iclass 31, count 0 2006.173.15:53:57.54#ibcon#about to read 3, iclass 31, count 0 2006.173.15:53:57.56#ibcon#read 3, iclass 31, count 0 2006.173.15:53:57.56#ibcon#about to read 4, iclass 31, count 0 2006.173.15:53:57.56#ibcon#read 4, iclass 31, count 0 2006.173.15:53:57.56#ibcon#about to read 5, iclass 31, count 0 2006.173.15:53:57.56#ibcon#read 5, iclass 31, count 0 2006.173.15:53:57.56#ibcon#about to read 6, iclass 31, count 0 2006.173.15:53:57.56#ibcon#read 6, iclass 31, count 0 2006.173.15:53:57.56#ibcon#end of sib2, iclass 31, count 0 2006.173.15:53:57.56#ibcon#*mode == 0, iclass 31, count 0 2006.173.15:53:57.56#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.15:53:57.56#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.15:53:57.56#ibcon#*before write, iclass 31, count 0 2006.173.15:53:57.56#ibcon#enter sib2, iclass 31, count 0 2006.173.15:53:57.56#ibcon#flushed, iclass 31, count 0 2006.173.15:53:57.56#ibcon#about to write, iclass 31, count 0 2006.173.15:53:57.56#ibcon#wrote, iclass 31, count 0 2006.173.15:53:57.56#ibcon#about to read 3, iclass 31, count 0 2006.173.15:53:57.60#ibcon#read 3, iclass 31, count 0 2006.173.15:53:57.60#ibcon#about to read 4, iclass 31, count 0 2006.173.15:53:57.60#ibcon#read 4, iclass 31, count 0 2006.173.15:53:57.60#ibcon#about to read 5, iclass 31, count 0 2006.173.15:53:57.60#ibcon#read 5, iclass 31, count 0 2006.173.15:53:57.60#ibcon#about to read 6, iclass 31, count 0 2006.173.15:53:57.60#ibcon#read 6, iclass 31, count 0 2006.173.15:53:57.60#ibcon#end of sib2, iclass 31, count 0 2006.173.15:53:57.60#ibcon#*after write, iclass 31, count 0 2006.173.15:53:57.60#ibcon#*before return 0, iclass 31, count 0 2006.173.15:53:57.60#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.15:53:57.60#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.15:53:57.60#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.15:53:57.60#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.15:53:57.60$vck44/vb=3,4 2006.173.15:53:57.60#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.173.15:53:57.60#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.173.15:53:57.60#ibcon#ireg 11 cls_cnt 2 2006.173.15:53:57.60#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.15:53:57.66#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.15:53:57.66#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.15:53:57.66#ibcon#enter wrdev, iclass 33, count 2 2006.173.15:53:57.66#ibcon#first serial, iclass 33, count 2 2006.173.15:53:57.66#ibcon#enter sib2, iclass 33, count 2 2006.173.15:53:57.66#ibcon#flushed, iclass 33, count 2 2006.173.15:53:57.66#ibcon#about to write, iclass 33, count 2 2006.173.15:53:57.66#ibcon#wrote, iclass 33, count 2 2006.173.15:53:57.66#ibcon#about to read 3, iclass 33, count 2 2006.173.15:53:57.68#ibcon#read 3, iclass 33, count 2 2006.173.15:53:57.68#ibcon#about to read 4, iclass 33, count 2 2006.173.15:53:57.68#ibcon#read 4, iclass 33, count 2 2006.173.15:53:57.68#ibcon#about to read 5, iclass 33, count 2 2006.173.15:53:57.68#ibcon#read 5, iclass 33, count 2 2006.173.15:53:57.68#ibcon#about to read 6, iclass 33, count 2 2006.173.15:53:57.68#ibcon#read 6, iclass 33, count 2 2006.173.15:53:57.68#ibcon#end of sib2, iclass 33, count 2 2006.173.15:53:57.68#ibcon#*mode == 0, iclass 33, count 2 2006.173.15:53:57.68#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.173.15:53:57.68#ibcon#[27=AT03-04\r\n] 2006.173.15:53:57.68#ibcon#*before write, iclass 33, count 2 2006.173.15:53:57.68#ibcon#enter sib2, iclass 33, count 2 2006.173.15:53:57.68#ibcon#flushed, iclass 33, count 2 2006.173.15:53:57.68#ibcon#about to write, iclass 33, count 2 2006.173.15:53:57.68#ibcon#wrote, iclass 33, count 2 2006.173.15:53:57.68#ibcon#about to read 3, iclass 33, count 2 2006.173.15:53:57.71#ibcon#read 3, iclass 33, count 2 2006.173.15:53:57.71#ibcon#about to read 4, iclass 33, count 2 2006.173.15:53:57.71#ibcon#read 4, iclass 33, count 2 2006.173.15:53:57.71#ibcon#about to read 5, iclass 33, count 2 2006.173.15:53:57.71#ibcon#read 5, iclass 33, count 2 2006.173.15:53:57.71#ibcon#about to read 6, iclass 33, count 2 2006.173.15:53:57.71#ibcon#read 6, iclass 33, count 2 2006.173.15:53:57.71#ibcon#end of sib2, iclass 33, count 2 2006.173.15:53:57.71#ibcon#*after write, iclass 33, count 2 2006.173.15:53:57.71#ibcon#*before return 0, iclass 33, count 2 2006.173.15:53:57.71#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.15:53:57.71#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.173.15:53:57.71#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.173.15:53:57.71#ibcon#ireg 7 cls_cnt 0 2006.173.15:53:57.71#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.15:53:57.83#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.15:53:57.83#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.15:53:57.83#ibcon#enter wrdev, iclass 33, count 0 2006.173.15:53:57.83#ibcon#first serial, iclass 33, count 0 2006.173.15:53:57.83#ibcon#enter sib2, iclass 33, count 0 2006.173.15:53:57.83#ibcon#flushed, iclass 33, count 0 2006.173.15:53:57.83#ibcon#about to write, iclass 33, count 0 2006.173.15:53:57.83#ibcon#wrote, iclass 33, count 0 2006.173.15:53:57.83#ibcon#about to read 3, iclass 33, count 0 2006.173.15:53:57.85#ibcon#read 3, iclass 33, count 0 2006.173.15:53:57.85#ibcon#about to read 4, iclass 33, count 0 2006.173.15:53:57.85#ibcon#read 4, iclass 33, count 0 2006.173.15:53:57.85#ibcon#about to read 5, iclass 33, count 0 2006.173.15:53:57.85#ibcon#read 5, iclass 33, count 0 2006.173.15:53:57.85#ibcon#about to read 6, iclass 33, count 0 2006.173.15:53:57.85#ibcon#read 6, iclass 33, count 0 2006.173.15:53:57.85#ibcon#end of sib2, iclass 33, count 0 2006.173.15:53:57.85#ibcon#*mode == 0, iclass 33, count 0 2006.173.15:53:57.85#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.15:53:57.85#ibcon#[27=USB\r\n] 2006.173.15:53:57.85#ibcon#*before write, iclass 33, count 0 2006.173.15:53:57.85#ibcon#enter sib2, iclass 33, count 0 2006.173.15:53:57.85#ibcon#flushed, iclass 33, count 0 2006.173.15:53:57.85#ibcon#about to write, iclass 33, count 0 2006.173.15:53:57.85#ibcon#wrote, iclass 33, count 0 2006.173.15:53:57.85#ibcon#about to read 3, iclass 33, count 0 2006.173.15:53:57.88#ibcon#read 3, iclass 33, count 0 2006.173.15:53:57.88#ibcon#about to read 4, iclass 33, count 0 2006.173.15:53:57.88#ibcon#read 4, iclass 33, count 0 2006.173.15:53:57.88#ibcon#about to read 5, iclass 33, count 0 2006.173.15:53:57.88#ibcon#read 5, iclass 33, count 0 2006.173.15:53:57.88#ibcon#about to read 6, iclass 33, count 0 2006.173.15:53:57.88#ibcon#read 6, iclass 33, count 0 2006.173.15:53:57.88#ibcon#end of sib2, iclass 33, count 0 2006.173.15:53:57.88#ibcon#*after write, iclass 33, count 0 2006.173.15:53:57.88#ibcon#*before return 0, iclass 33, count 0 2006.173.15:53:57.88#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.15:53:57.88#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.173.15:53:57.88#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.15:53:57.88#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.15:53:57.88$vck44/vblo=4,679.99 2006.173.15:53:57.88#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.15:53:57.88#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.15:53:57.88#ibcon#ireg 17 cls_cnt 0 2006.173.15:53:57.88#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.15:53:57.88#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.15:53:57.88#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.15:53:57.88#ibcon#enter wrdev, iclass 35, count 0 2006.173.15:53:57.88#ibcon#first serial, iclass 35, count 0 2006.173.15:53:57.88#ibcon#enter sib2, iclass 35, count 0 2006.173.15:53:57.88#ibcon#flushed, iclass 35, count 0 2006.173.15:53:57.88#ibcon#about to write, iclass 35, count 0 2006.173.15:53:57.88#ibcon#wrote, iclass 35, count 0 2006.173.15:53:57.88#ibcon#about to read 3, iclass 35, count 0 2006.173.15:53:57.90#ibcon#read 3, iclass 35, count 0 2006.173.15:53:57.90#ibcon#about to read 4, iclass 35, count 0 2006.173.15:53:57.90#ibcon#read 4, iclass 35, count 0 2006.173.15:53:57.90#ibcon#about to read 5, iclass 35, count 0 2006.173.15:53:57.90#ibcon#read 5, iclass 35, count 0 2006.173.15:53:57.90#ibcon#about to read 6, iclass 35, count 0 2006.173.15:53:57.90#ibcon#read 6, iclass 35, count 0 2006.173.15:53:57.90#ibcon#end of sib2, iclass 35, count 0 2006.173.15:53:57.90#ibcon#*mode == 0, iclass 35, count 0 2006.173.15:53:57.90#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.15:53:57.90#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.15:53:57.90#ibcon#*before write, iclass 35, count 0 2006.173.15:53:57.90#ibcon#enter sib2, iclass 35, count 0 2006.173.15:53:57.90#ibcon#flushed, iclass 35, count 0 2006.173.15:53:57.90#ibcon#about to write, iclass 35, count 0 2006.173.15:53:57.90#ibcon#wrote, iclass 35, count 0 2006.173.15:53:57.90#ibcon#about to read 3, iclass 35, count 0 2006.173.15:53:57.94#ibcon#read 3, iclass 35, count 0 2006.173.15:53:57.94#ibcon#about to read 4, iclass 35, count 0 2006.173.15:53:57.94#ibcon#read 4, iclass 35, count 0 2006.173.15:53:57.94#ibcon#about to read 5, iclass 35, count 0 2006.173.15:53:57.94#ibcon#read 5, iclass 35, count 0 2006.173.15:53:57.94#ibcon#about to read 6, iclass 35, count 0 2006.173.15:53:57.94#ibcon#read 6, iclass 35, count 0 2006.173.15:53:57.94#ibcon#end of sib2, iclass 35, count 0 2006.173.15:53:57.94#ibcon#*after write, iclass 35, count 0 2006.173.15:53:57.94#ibcon#*before return 0, iclass 35, count 0 2006.173.15:53:57.94#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.15:53:57.94#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.15:53:57.94#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.15:53:57.94#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.15:53:57.94$vck44/vb=4,4 2006.173.15:53:57.94#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.173.15:53:57.94#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.173.15:53:57.94#ibcon#ireg 11 cls_cnt 2 2006.173.15:53:57.94#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.15:53:58.00#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.15:53:58.00#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.15:53:58.00#ibcon#enter wrdev, iclass 37, count 2 2006.173.15:53:58.00#ibcon#first serial, iclass 37, count 2 2006.173.15:53:58.00#ibcon#enter sib2, iclass 37, count 2 2006.173.15:53:58.00#ibcon#flushed, iclass 37, count 2 2006.173.15:53:58.00#ibcon#about to write, iclass 37, count 2 2006.173.15:53:58.00#ibcon#wrote, iclass 37, count 2 2006.173.15:53:58.00#ibcon#about to read 3, iclass 37, count 2 2006.173.15:53:58.02#ibcon#read 3, iclass 37, count 2 2006.173.15:53:58.02#ibcon#about to read 4, iclass 37, count 2 2006.173.15:53:58.02#ibcon#read 4, iclass 37, count 2 2006.173.15:53:58.02#ibcon#about to read 5, iclass 37, count 2 2006.173.15:53:58.02#ibcon#read 5, iclass 37, count 2 2006.173.15:53:58.02#ibcon#about to read 6, iclass 37, count 2 2006.173.15:53:58.02#ibcon#read 6, iclass 37, count 2 2006.173.15:53:58.02#ibcon#end of sib2, iclass 37, count 2 2006.173.15:53:58.02#ibcon#*mode == 0, iclass 37, count 2 2006.173.15:53:58.02#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.173.15:53:58.02#ibcon#[27=AT04-04\r\n] 2006.173.15:53:58.02#ibcon#*before write, iclass 37, count 2 2006.173.15:53:58.02#ibcon#enter sib2, iclass 37, count 2 2006.173.15:53:58.02#ibcon#flushed, iclass 37, count 2 2006.173.15:53:58.02#ibcon#about to write, iclass 37, count 2 2006.173.15:53:58.02#ibcon#wrote, iclass 37, count 2 2006.173.15:53:58.02#ibcon#about to read 3, iclass 37, count 2 2006.173.15:53:58.05#ibcon#read 3, iclass 37, count 2 2006.173.15:53:58.05#ibcon#about to read 4, iclass 37, count 2 2006.173.15:53:58.05#ibcon#read 4, iclass 37, count 2 2006.173.15:53:58.05#ibcon#about to read 5, iclass 37, count 2 2006.173.15:53:58.05#ibcon#read 5, iclass 37, count 2 2006.173.15:53:58.05#ibcon#about to read 6, iclass 37, count 2 2006.173.15:53:58.05#ibcon#read 6, iclass 37, count 2 2006.173.15:53:58.05#ibcon#end of sib2, iclass 37, count 2 2006.173.15:53:58.05#ibcon#*after write, iclass 37, count 2 2006.173.15:53:58.05#ibcon#*before return 0, iclass 37, count 2 2006.173.15:53:58.05#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.15:53:58.05#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.173.15:53:58.05#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.173.15:53:58.05#ibcon#ireg 7 cls_cnt 0 2006.173.15:53:58.05#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.15:53:58.17#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.15:53:58.17#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.15:53:58.17#ibcon#enter wrdev, iclass 37, count 0 2006.173.15:53:58.17#ibcon#first serial, iclass 37, count 0 2006.173.15:53:58.17#ibcon#enter sib2, iclass 37, count 0 2006.173.15:53:58.17#ibcon#flushed, iclass 37, count 0 2006.173.15:53:58.17#ibcon#about to write, iclass 37, count 0 2006.173.15:53:58.17#ibcon#wrote, iclass 37, count 0 2006.173.15:53:58.17#ibcon#about to read 3, iclass 37, count 0 2006.173.15:53:58.19#ibcon#read 3, iclass 37, count 0 2006.173.15:53:58.19#ibcon#about to read 4, iclass 37, count 0 2006.173.15:53:58.19#ibcon#read 4, iclass 37, count 0 2006.173.15:53:58.19#ibcon#about to read 5, iclass 37, count 0 2006.173.15:53:58.19#ibcon#read 5, iclass 37, count 0 2006.173.15:53:58.19#ibcon#about to read 6, iclass 37, count 0 2006.173.15:53:58.19#ibcon#read 6, iclass 37, count 0 2006.173.15:53:58.19#ibcon#end of sib2, iclass 37, count 0 2006.173.15:53:58.19#ibcon#*mode == 0, iclass 37, count 0 2006.173.15:53:58.19#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.15:53:58.19#ibcon#[27=USB\r\n] 2006.173.15:53:58.19#ibcon#*before write, iclass 37, count 0 2006.173.15:53:58.19#ibcon#enter sib2, iclass 37, count 0 2006.173.15:53:58.19#ibcon#flushed, iclass 37, count 0 2006.173.15:53:58.19#ibcon#about to write, iclass 37, count 0 2006.173.15:53:58.19#ibcon#wrote, iclass 37, count 0 2006.173.15:53:58.19#ibcon#about to read 3, iclass 37, count 0 2006.173.15:53:58.22#ibcon#read 3, iclass 37, count 0 2006.173.15:53:58.22#ibcon#about to read 4, iclass 37, count 0 2006.173.15:53:58.22#ibcon#read 4, iclass 37, count 0 2006.173.15:53:58.22#ibcon#about to read 5, iclass 37, count 0 2006.173.15:53:58.22#ibcon#read 5, iclass 37, count 0 2006.173.15:53:58.22#ibcon#about to read 6, iclass 37, count 0 2006.173.15:53:58.22#ibcon#read 6, iclass 37, count 0 2006.173.15:53:58.22#ibcon#end of sib2, iclass 37, count 0 2006.173.15:53:58.22#ibcon#*after write, iclass 37, count 0 2006.173.15:53:58.22#ibcon#*before return 0, iclass 37, count 0 2006.173.15:53:58.22#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.15:53:58.22#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.173.15:53:58.22#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.15:53:58.22#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.15:53:58.22$vck44/vblo=5,709.99 2006.173.15:53:58.22#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.15:53:58.22#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.15:53:58.22#ibcon#ireg 17 cls_cnt 0 2006.173.15:53:58.22#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.15:53:58.22#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.15:53:58.22#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.15:53:58.22#ibcon#enter wrdev, iclass 39, count 0 2006.173.15:53:58.22#ibcon#first serial, iclass 39, count 0 2006.173.15:53:58.22#ibcon#enter sib2, iclass 39, count 0 2006.173.15:53:58.22#ibcon#flushed, iclass 39, count 0 2006.173.15:53:58.22#ibcon#about to write, iclass 39, count 0 2006.173.15:53:58.22#ibcon#wrote, iclass 39, count 0 2006.173.15:53:58.22#ibcon#about to read 3, iclass 39, count 0 2006.173.15:53:58.24#ibcon#read 3, iclass 39, count 0 2006.173.15:53:58.24#ibcon#about to read 4, iclass 39, count 0 2006.173.15:53:58.24#ibcon#read 4, iclass 39, count 0 2006.173.15:53:58.24#ibcon#about to read 5, iclass 39, count 0 2006.173.15:53:58.24#ibcon#read 5, iclass 39, count 0 2006.173.15:53:58.24#ibcon#about to read 6, iclass 39, count 0 2006.173.15:53:58.24#ibcon#read 6, iclass 39, count 0 2006.173.15:53:58.24#ibcon#end of sib2, iclass 39, count 0 2006.173.15:53:58.24#ibcon#*mode == 0, iclass 39, count 0 2006.173.15:53:58.24#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.15:53:58.24#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.15:53:58.24#ibcon#*before write, iclass 39, count 0 2006.173.15:53:58.24#ibcon#enter sib2, iclass 39, count 0 2006.173.15:53:58.24#ibcon#flushed, iclass 39, count 0 2006.173.15:53:58.24#ibcon#about to write, iclass 39, count 0 2006.173.15:53:58.24#ibcon#wrote, iclass 39, count 0 2006.173.15:53:58.24#ibcon#about to read 3, iclass 39, count 0 2006.173.15:53:58.28#ibcon#read 3, iclass 39, count 0 2006.173.15:53:58.28#ibcon#about to read 4, iclass 39, count 0 2006.173.15:53:58.28#ibcon#read 4, iclass 39, count 0 2006.173.15:53:58.28#ibcon#about to read 5, iclass 39, count 0 2006.173.15:53:58.28#ibcon#read 5, iclass 39, count 0 2006.173.15:53:58.28#ibcon#about to read 6, iclass 39, count 0 2006.173.15:53:58.28#ibcon#read 6, iclass 39, count 0 2006.173.15:53:58.28#ibcon#end of sib2, iclass 39, count 0 2006.173.15:53:58.28#ibcon#*after write, iclass 39, count 0 2006.173.15:53:58.28#ibcon#*before return 0, iclass 39, count 0 2006.173.15:53:58.28#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.15:53:58.28#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.15:53:58.28#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.15:53:58.28#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.15:53:58.28$vck44/vb=5,4 2006.173.15:53:58.28#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.15:53:58.28#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.15:53:58.28#ibcon#ireg 11 cls_cnt 2 2006.173.15:53:58.28#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.15:53:58.34#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.15:53:58.34#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.15:53:58.34#ibcon#enter wrdev, iclass 3, count 2 2006.173.15:53:58.34#ibcon#first serial, iclass 3, count 2 2006.173.15:53:58.34#ibcon#enter sib2, iclass 3, count 2 2006.173.15:53:58.34#ibcon#flushed, iclass 3, count 2 2006.173.15:53:58.34#ibcon#about to write, iclass 3, count 2 2006.173.15:53:58.34#ibcon#wrote, iclass 3, count 2 2006.173.15:53:58.34#ibcon#about to read 3, iclass 3, count 2 2006.173.15:53:58.36#ibcon#read 3, iclass 3, count 2 2006.173.15:53:58.36#ibcon#about to read 4, iclass 3, count 2 2006.173.15:53:58.36#ibcon#read 4, iclass 3, count 2 2006.173.15:53:58.36#ibcon#about to read 5, iclass 3, count 2 2006.173.15:53:58.36#ibcon#read 5, iclass 3, count 2 2006.173.15:53:58.36#ibcon#about to read 6, iclass 3, count 2 2006.173.15:53:58.36#ibcon#read 6, iclass 3, count 2 2006.173.15:53:58.36#ibcon#end of sib2, iclass 3, count 2 2006.173.15:53:58.36#ibcon#*mode == 0, iclass 3, count 2 2006.173.15:53:58.36#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.15:53:58.36#ibcon#[27=AT05-04\r\n] 2006.173.15:53:58.36#ibcon#*before write, iclass 3, count 2 2006.173.15:53:58.36#ibcon#enter sib2, iclass 3, count 2 2006.173.15:53:58.36#ibcon#flushed, iclass 3, count 2 2006.173.15:53:58.36#ibcon#about to write, iclass 3, count 2 2006.173.15:53:58.36#ibcon#wrote, iclass 3, count 2 2006.173.15:53:58.36#ibcon#about to read 3, iclass 3, count 2 2006.173.15:53:58.39#ibcon#read 3, iclass 3, count 2 2006.173.15:53:58.39#ibcon#about to read 4, iclass 3, count 2 2006.173.15:53:58.39#ibcon#read 4, iclass 3, count 2 2006.173.15:53:58.39#ibcon#about to read 5, iclass 3, count 2 2006.173.15:53:58.39#ibcon#read 5, iclass 3, count 2 2006.173.15:53:58.39#ibcon#about to read 6, iclass 3, count 2 2006.173.15:53:58.39#ibcon#read 6, iclass 3, count 2 2006.173.15:53:58.39#ibcon#end of sib2, iclass 3, count 2 2006.173.15:53:58.39#ibcon#*after write, iclass 3, count 2 2006.173.15:53:58.39#ibcon#*before return 0, iclass 3, count 2 2006.173.15:53:58.39#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.15:53:58.39#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.15:53:58.39#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.15:53:58.39#ibcon#ireg 7 cls_cnt 0 2006.173.15:53:58.39#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.15:53:58.51#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.15:53:58.51#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.15:53:58.51#ibcon#enter wrdev, iclass 3, count 0 2006.173.15:53:58.51#ibcon#first serial, iclass 3, count 0 2006.173.15:53:58.51#ibcon#enter sib2, iclass 3, count 0 2006.173.15:53:58.51#ibcon#flushed, iclass 3, count 0 2006.173.15:53:58.51#ibcon#about to write, iclass 3, count 0 2006.173.15:53:58.51#ibcon#wrote, iclass 3, count 0 2006.173.15:53:58.51#ibcon#about to read 3, iclass 3, count 0 2006.173.15:53:58.53#ibcon#read 3, iclass 3, count 0 2006.173.15:53:58.53#ibcon#about to read 4, iclass 3, count 0 2006.173.15:53:58.53#ibcon#read 4, iclass 3, count 0 2006.173.15:53:58.53#ibcon#about to read 5, iclass 3, count 0 2006.173.15:53:58.53#ibcon#read 5, iclass 3, count 0 2006.173.15:53:58.53#ibcon#about to read 6, iclass 3, count 0 2006.173.15:53:58.53#ibcon#read 6, iclass 3, count 0 2006.173.15:53:58.53#ibcon#end of sib2, iclass 3, count 0 2006.173.15:53:58.53#ibcon#*mode == 0, iclass 3, count 0 2006.173.15:53:58.53#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.15:53:58.53#ibcon#[27=USB\r\n] 2006.173.15:53:58.53#ibcon#*before write, iclass 3, count 0 2006.173.15:53:58.53#ibcon#enter sib2, iclass 3, count 0 2006.173.15:53:58.53#ibcon#flushed, iclass 3, count 0 2006.173.15:53:58.53#ibcon#about to write, iclass 3, count 0 2006.173.15:53:58.53#ibcon#wrote, iclass 3, count 0 2006.173.15:53:58.53#ibcon#about to read 3, iclass 3, count 0 2006.173.15:53:58.56#ibcon#read 3, iclass 3, count 0 2006.173.15:53:58.56#ibcon#about to read 4, iclass 3, count 0 2006.173.15:53:58.56#ibcon#read 4, iclass 3, count 0 2006.173.15:53:58.56#ibcon#about to read 5, iclass 3, count 0 2006.173.15:53:58.56#ibcon#read 5, iclass 3, count 0 2006.173.15:53:58.56#ibcon#about to read 6, iclass 3, count 0 2006.173.15:53:58.56#ibcon#read 6, iclass 3, count 0 2006.173.15:53:58.56#ibcon#end of sib2, iclass 3, count 0 2006.173.15:53:58.56#ibcon#*after write, iclass 3, count 0 2006.173.15:53:58.56#ibcon#*before return 0, iclass 3, count 0 2006.173.15:53:58.56#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.15:53:58.56#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.15:53:58.56#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.15:53:58.56#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.15:53:58.56$vck44/vblo=6,719.99 2006.173.15:53:58.56#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.15:53:58.56#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.15:53:58.56#ibcon#ireg 17 cls_cnt 0 2006.173.15:53:58.56#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.15:53:58.56#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.15:53:58.56#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.15:53:58.56#ibcon#enter wrdev, iclass 5, count 0 2006.173.15:53:58.56#ibcon#first serial, iclass 5, count 0 2006.173.15:53:58.56#ibcon#enter sib2, iclass 5, count 0 2006.173.15:53:58.56#ibcon#flushed, iclass 5, count 0 2006.173.15:53:58.56#ibcon#about to write, iclass 5, count 0 2006.173.15:53:58.56#ibcon#wrote, iclass 5, count 0 2006.173.15:53:58.56#ibcon#about to read 3, iclass 5, count 0 2006.173.15:53:58.58#ibcon#read 3, iclass 5, count 0 2006.173.15:53:58.58#ibcon#about to read 4, iclass 5, count 0 2006.173.15:53:58.58#ibcon#read 4, iclass 5, count 0 2006.173.15:53:58.58#ibcon#about to read 5, iclass 5, count 0 2006.173.15:53:58.58#ibcon#read 5, iclass 5, count 0 2006.173.15:53:58.58#ibcon#about to read 6, iclass 5, count 0 2006.173.15:53:58.58#ibcon#read 6, iclass 5, count 0 2006.173.15:53:58.58#ibcon#end of sib2, iclass 5, count 0 2006.173.15:53:58.58#ibcon#*mode == 0, iclass 5, count 0 2006.173.15:53:58.58#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.15:53:58.58#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.15:53:58.58#ibcon#*before write, iclass 5, count 0 2006.173.15:53:58.58#ibcon#enter sib2, iclass 5, count 0 2006.173.15:53:58.58#ibcon#flushed, iclass 5, count 0 2006.173.15:53:58.58#ibcon#about to write, iclass 5, count 0 2006.173.15:53:58.58#ibcon#wrote, iclass 5, count 0 2006.173.15:53:58.58#ibcon#about to read 3, iclass 5, count 0 2006.173.15:53:58.62#ibcon#read 3, iclass 5, count 0 2006.173.15:53:58.62#ibcon#about to read 4, iclass 5, count 0 2006.173.15:53:58.62#ibcon#read 4, iclass 5, count 0 2006.173.15:53:58.62#ibcon#about to read 5, iclass 5, count 0 2006.173.15:53:58.62#ibcon#read 5, iclass 5, count 0 2006.173.15:53:58.62#ibcon#about to read 6, iclass 5, count 0 2006.173.15:53:58.62#ibcon#read 6, iclass 5, count 0 2006.173.15:53:58.62#ibcon#end of sib2, iclass 5, count 0 2006.173.15:53:58.62#ibcon#*after write, iclass 5, count 0 2006.173.15:53:58.62#ibcon#*before return 0, iclass 5, count 0 2006.173.15:53:58.62#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.15:53:58.62#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.15:53:58.62#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.15:53:58.62#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.15:53:58.62$vck44/vb=6,4 2006.173.15:53:58.62#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.173.15:53:58.62#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.173.15:53:58.62#ibcon#ireg 11 cls_cnt 2 2006.173.15:53:58.62#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.15:53:58.68#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.15:53:58.68#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.15:53:58.68#ibcon#enter wrdev, iclass 7, count 2 2006.173.15:53:58.68#ibcon#first serial, iclass 7, count 2 2006.173.15:53:58.68#ibcon#enter sib2, iclass 7, count 2 2006.173.15:53:58.68#ibcon#flushed, iclass 7, count 2 2006.173.15:53:58.68#ibcon#about to write, iclass 7, count 2 2006.173.15:53:58.68#ibcon#wrote, iclass 7, count 2 2006.173.15:53:58.68#ibcon#about to read 3, iclass 7, count 2 2006.173.15:53:58.70#ibcon#read 3, iclass 7, count 2 2006.173.15:53:58.70#ibcon#about to read 4, iclass 7, count 2 2006.173.15:53:58.70#ibcon#read 4, iclass 7, count 2 2006.173.15:53:58.70#ibcon#about to read 5, iclass 7, count 2 2006.173.15:53:58.70#ibcon#read 5, iclass 7, count 2 2006.173.15:53:58.70#ibcon#about to read 6, iclass 7, count 2 2006.173.15:53:58.70#ibcon#read 6, iclass 7, count 2 2006.173.15:53:58.70#ibcon#end of sib2, iclass 7, count 2 2006.173.15:53:58.70#ibcon#*mode == 0, iclass 7, count 2 2006.173.15:53:58.70#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.173.15:53:58.70#ibcon#[27=AT06-04\r\n] 2006.173.15:53:58.70#ibcon#*before write, iclass 7, count 2 2006.173.15:53:58.70#ibcon#enter sib2, iclass 7, count 2 2006.173.15:53:58.70#ibcon#flushed, iclass 7, count 2 2006.173.15:53:58.70#ibcon#about to write, iclass 7, count 2 2006.173.15:53:58.70#ibcon#wrote, iclass 7, count 2 2006.173.15:53:58.70#ibcon#about to read 3, iclass 7, count 2 2006.173.15:53:58.73#ibcon#read 3, iclass 7, count 2 2006.173.15:53:58.73#ibcon#about to read 4, iclass 7, count 2 2006.173.15:53:58.73#ibcon#read 4, iclass 7, count 2 2006.173.15:53:58.73#ibcon#about to read 5, iclass 7, count 2 2006.173.15:53:58.73#ibcon#read 5, iclass 7, count 2 2006.173.15:53:58.73#ibcon#about to read 6, iclass 7, count 2 2006.173.15:53:58.73#ibcon#read 6, iclass 7, count 2 2006.173.15:53:58.73#ibcon#end of sib2, iclass 7, count 2 2006.173.15:53:58.73#ibcon#*after write, iclass 7, count 2 2006.173.15:53:58.73#ibcon#*before return 0, iclass 7, count 2 2006.173.15:53:58.73#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.15:53:58.73#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.173.15:53:58.73#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.173.15:53:58.73#ibcon#ireg 7 cls_cnt 0 2006.173.15:53:58.73#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.15:53:58.85#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.15:53:58.85#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.15:53:58.85#ibcon#enter wrdev, iclass 7, count 0 2006.173.15:53:58.85#ibcon#first serial, iclass 7, count 0 2006.173.15:53:58.85#ibcon#enter sib2, iclass 7, count 0 2006.173.15:53:58.85#ibcon#flushed, iclass 7, count 0 2006.173.15:53:58.85#ibcon#about to write, iclass 7, count 0 2006.173.15:53:58.85#ibcon#wrote, iclass 7, count 0 2006.173.15:53:58.85#ibcon#about to read 3, iclass 7, count 0 2006.173.15:53:58.87#ibcon#read 3, iclass 7, count 0 2006.173.15:53:58.87#ibcon#about to read 4, iclass 7, count 0 2006.173.15:53:58.87#ibcon#read 4, iclass 7, count 0 2006.173.15:53:58.87#ibcon#about to read 5, iclass 7, count 0 2006.173.15:53:58.87#ibcon#read 5, iclass 7, count 0 2006.173.15:53:58.87#ibcon#about to read 6, iclass 7, count 0 2006.173.15:53:58.87#ibcon#read 6, iclass 7, count 0 2006.173.15:53:58.87#ibcon#end of sib2, iclass 7, count 0 2006.173.15:53:58.87#ibcon#*mode == 0, iclass 7, count 0 2006.173.15:53:58.87#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.15:53:58.87#ibcon#[27=USB\r\n] 2006.173.15:53:58.87#ibcon#*before write, iclass 7, count 0 2006.173.15:53:58.87#ibcon#enter sib2, iclass 7, count 0 2006.173.15:53:58.87#ibcon#flushed, iclass 7, count 0 2006.173.15:53:58.87#ibcon#about to write, iclass 7, count 0 2006.173.15:53:58.87#ibcon#wrote, iclass 7, count 0 2006.173.15:53:58.87#ibcon#about to read 3, iclass 7, count 0 2006.173.15:53:58.90#ibcon#read 3, iclass 7, count 0 2006.173.15:53:58.90#ibcon#about to read 4, iclass 7, count 0 2006.173.15:53:58.90#ibcon#read 4, iclass 7, count 0 2006.173.15:53:58.90#ibcon#about to read 5, iclass 7, count 0 2006.173.15:53:58.90#ibcon#read 5, iclass 7, count 0 2006.173.15:53:58.90#ibcon#about to read 6, iclass 7, count 0 2006.173.15:53:58.90#ibcon#read 6, iclass 7, count 0 2006.173.15:53:58.90#ibcon#end of sib2, iclass 7, count 0 2006.173.15:53:58.90#ibcon#*after write, iclass 7, count 0 2006.173.15:53:58.90#ibcon#*before return 0, iclass 7, count 0 2006.173.15:53:58.90#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.15:53:58.90#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.173.15:53:58.90#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.15:53:58.90#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.15:53:58.90$vck44/vblo=7,734.99 2006.173.15:53:58.90#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.15:53:58.90#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.15:53:58.90#ibcon#ireg 17 cls_cnt 0 2006.173.15:53:58.90#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.15:53:58.90#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.15:53:58.90#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.15:53:58.90#ibcon#enter wrdev, iclass 11, count 0 2006.173.15:53:58.90#ibcon#first serial, iclass 11, count 0 2006.173.15:53:58.90#ibcon#enter sib2, iclass 11, count 0 2006.173.15:53:58.90#ibcon#flushed, iclass 11, count 0 2006.173.15:53:58.90#ibcon#about to write, iclass 11, count 0 2006.173.15:53:58.90#ibcon#wrote, iclass 11, count 0 2006.173.15:53:58.90#ibcon#about to read 3, iclass 11, count 0 2006.173.15:53:58.92#ibcon#read 3, iclass 11, count 0 2006.173.15:53:58.92#ibcon#about to read 4, iclass 11, count 0 2006.173.15:53:58.92#ibcon#read 4, iclass 11, count 0 2006.173.15:53:58.92#ibcon#about to read 5, iclass 11, count 0 2006.173.15:53:58.92#ibcon#read 5, iclass 11, count 0 2006.173.15:53:58.92#ibcon#about to read 6, iclass 11, count 0 2006.173.15:53:58.92#ibcon#read 6, iclass 11, count 0 2006.173.15:53:58.92#ibcon#end of sib2, iclass 11, count 0 2006.173.15:53:58.92#ibcon#*mode == 0, iclass 11, count 0 2006.173.15:53:58.92#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.15:53:58.92#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.15:53:58.92#ibcon#*before write, iclass 11, count 0 2006.173.15:53:58.92#ibcon#enter sib2, iclass 11, count 0 2006.173.15:53:58.92#ibcon#flushed, iclass 11, count 0 2006.173.15:53:58.92#ibcon#about to write, iclass 11, count 0 2006.173.15:53:58.92#ibcon#wrote, iclass 11, count 0 2006.173.15:53:58.92#ibcon#about to read 3, iclass 11, count 0 2006.173.15:53:58.96#ibcon#read 3, iclass 11, count 0 2006.173.15:53:58.96#ibcon#about to read 4, iclass 11, count 0 2006.173.15:53:58.96#ibcon#read 4, iclass 11, count 0 2006.173.15:53:58.96#ibcon#about to read 5, iclass 11, count 0 2006.173.15:53:58.96#ibcon#read 5, iclass 11, count 0 2006.173.15:53:58.96#ibcon#about to read 6, iclass 11, count 0 2006.173.15:53:58.96#ibcon#read 6, iclass 11, count 0 2006.173.15:53:58.96#ibcon#end of sib2, iclass 11, count 0 2006.173.15:53:58.96#ibcon#*after write, iclass 11, count 0 2006.173.15:53:58.96#ibcon#*before return 0, iclass 11, count 0 2006.173.15:53:58.96#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.15:53:58.96#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.15:53:58.96#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.15:53:58.96#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.15:53:58.96$vck44/vb=7,4 2006.173.15:53:58.96#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.15:53:58.96#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.15:53:58.96#ibcon#ireg 11 cls_cnt 2 2006.173.15:53:58.96#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.15:53:58.99#abcon#<5=/14 1.0 1.9 20.761001003.0\r\n> 2006.173.15:53:59.01#abcon#{5=INTERFACE CLEAR} 2006.173.15:53:59.02#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.15:53:59.02#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.15:53:59.02#ibcon#enter wrdev, iclass 14, count 2 2006.173.15:53:59.02#ibcon#first serial, iclass 14, count 2 2006.173.15:53:59.02#ibcon#enter sib2, iclass 14, count 2 2006.173.15:53:59.02#ibcon#flushed, iclass 14, count 2 2006.173.15:53:59.02#ibcon#about to write, iclass 14, count 2 2006.173.15:53:59.02#ibcon#wrote, iclass 14, count 2 2006.173.15:53:59.02#ibcon#about to read 3, iclass 14, count 2 2006.173.15:53:59.04#ibcon#read 3, iclass 14, count 2 2006.173.15:53:59.04#ibcon#about to read 4, iclass 14, count 2 2006.173.15:53:59.04#ibcon#read 4, iclass 14, count 2 2006.173.15:53:59.04#ibcon#about to read 5, iclass 14, count 2 2006.173.15:53:59.04#ibcon#read 5, iclass 14, count 2 2006.173.15:53:59.04#ibcon#about to read 6, iclass 14, count 2 2006.173.15:53:59.04#ibcon#read 6, iclass 14, count 2 2006.173.15:53:59.04#ibcon#end of sib2, iclass 14, count 2 2006.173.15:53:59.04#ibcon#*mode == 0, iclass 14, count 2 2006.173.15:53:59.04#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.15:53:59.04#ibcon#[27=AT07-04\r\n] 2006.173.15:53:59.04#ibcon#*before write, iclass 14, count 2 2006.173.15:53:59.04#ibcon#enter sib2, iclass 14, count 2 2006.173.15:53:59.04#ibcon#flushed, iclass 14, count 2 2006.173.15:53:59.04#ibcon#about to write, iclass 14, count 2 2006.173.15:53:59.04#ibcon#wrote, iclass 14, count 2 2006.173.15:53:59.04#ibcon#about to read 3, iclass 14, count 2 2006.173.15:53:59.07#abcon#[5=S1D000X0/0*\r\n] 2006.173.15:53:59.07#ibcon#read 3, iclass 14, count 2 2006.173.15:53:59.07#ibcon#about to read 4, iclass 14, count 2 2006.173.15:53:59.07#ibcon#read 4, iclass 14, count 2 2006.173.15:53:59.07#ibcon#about to read 5, iclass 14, count 2 2006.173.15:53:59.07#ibcon#read 5, iclass 14, count 2 2006.173.15:53:59.07#ibcon#about to read 6, iclass 14, count 2 2006.173.15:53:59.07#ibcon#read 6, iclass 14, count 2 2006.173.15:53:59.07#ibcon#end of sib2, iclass 14, count 2 2006.173.15:53:59.07#ibcon#*after write, iclass 14, count 2 2006.173.15:53:59.07#ibcon#*before return 0, iclass 14, count 2 2006.173.15:53:59.07#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.15:53:59.07#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.15:53:59.07#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.15:53:59.07#ibcon#ireg 7 cls_cnt 0 2006.173.15:53:59.07#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.15:53:59.19#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.15:53:59.19#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.15:53:59.19#ibcon#enter wrdev, iclass 14, count 0 2006.173.15:53:59.19#ibcon#first serial, iclass 14, count 0 2006.173.15:53:59.19#ibcon#enter sib2, iclass 14, count 0 2006.173.15:53:59.19#ibcon#flushed, iclass 14, count 0 2006.173.15:53:59.19#ibcon#about to write, iclass 14, count 0 2006.173.15:53:59.19#ibcon#wrote, iclass 14, count 0 2006.173.15:53:59.19#ibcon#about to read 3, iclass 14, count 0 2006.173.15:53:59.21#ibcon#read 3, iclass 14, count 0 2006.173.15:53:59.21#ibcon#about to read 4, iclass 14, count 0 2006.173.15:53:59.21#ibcon#read 4, iclass 14, count 0 2006.173.15:53:59.21#ibcon#about to read 5, iclass 14, count 0 2006.173.15:53:59.21#ibcon#read 5, iclass 14, count 0 2006.173.15:53:59.21#ibcon#about to read 6, iclass 14, count 0 2006.173.15:53:59.21#ibcon#read 6, iclass 14, count 0 2006.173.15:53:59.21#ibcon#end of sib2, iclass 14, count 0 2006.173.15:53:59.21#ibcon#*mode == 0, iclass 14, count 0 2006.173.15:53:59.21#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.15:53:59.21#ibcon#[27=USB\r\n] 2006.173.15:53:59.21#ibcon#*before write, iclass 14, count 0 2006.173.15:53:59.21#ibcon#enter sib2, iclass 14, count 0 2006.173.15:53:59.21#ibcon#flushed, iclass 14, count 0 2006.173.15:53:59.21#ibcon#about to write, iclass 14, count 0 2006.173.15:53:59.21#ibcon#wrote, iclass 14, count 0 2006.173.15:53:59.21#ibcon#about to read 3, iclass 14, count 0 2006.173.15:53:59.24#ibcon#read 3, iclass 14, count 0 2006.173.15:53:59.24#ibcon#about to read 4, iclass 14, count 0 2006.173.15:53:59.24#ibcon#read 4, iclass 14, count 0 2006.173.15:53:59.24#ibcon#about to read 5, iclass 14, count 0 2006.173.15:53:59.24#ibcon#read 5, iclass 14, count 0 2006.173.15:53:59.24#ibcon#about to read 6, iclass 14, count 0 2006.173.15:53:59.24#ibcon#read 6, iclass 14, count 0 2006.173.15:53:59.24#ibcon#end of sib2, iclass 14, count 0 2006.173.15:53:59.24#ibcon#*after write, iclass 14, count 0 2006.173.15:53:59.24#ibcon#*before return 0, iclass 14, count 0 2006.173.15:53:59.24#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.15:53:59.24#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.15:53:59.24#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.15:53:59.24#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.15:53:59.24$vck44/vblo=8,744.99 2006.173.15:53:59.24#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.15:53:59.24#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.15:53:59.24#ibcon#ireg 17 cls_cnt 0 2006.173.15:53:59.24#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.15:53:59.24#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.15:53:59.24#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.15:53:59.24#ibcon#enter wrdev, iclass 19, count 0 2006.173.15:53:59.24#ibcon#first serial, iclass 19, count 0 2006.173.15:53:59.24#ibcon#enter sib2, iclass 19, count 0 2006.173.15:53:59.24#ibcon#flushed, iclass 19, count 0 2006.173.15:53:59.24#ibcon#about to write, iclass 19, count 0 2006.173.15:53:59.24#ibcon#wrote, iclass 19, count 0 2006.173.15:53:59.24#ibcon#about to read 3, iclass 19, count 0 2006.173.15:53:59.26#ibcon#read 3, iclass 19, count 0 2006.173.15:53:59.26#ibcon#about to read 4, iclass 19, count 0 2006.173.15:53:59.26#ibcon#read 4, iclass 19, count 0 2006.173.15:53:59.26#ibcon#about to read 5, iclass 19, count 0 2006.173.15:53:59.26#ibcon#read 5, iclass 19, count 0 2006.173.15:53:59.26#ibcon#about to read 6, iclass 19, count 0 2006.173.15:53:59.26#ibcon#read 6, iclass 19, count 0 2006.173.15:53:59.26#ibcon#end of sib2, iclass 19, count 0 2006.173.15:53:59.26#ibcon#*mode == 0, iclass 19, count 0 2006.173.15:53:59.26#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.15:53:59.26#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.15:53:59.26#ibcon#*before write, iclass 19, count 0 2006.173.15:53:59.26#ibcon#enter sib2, iclass 19, count 0 2006.173.15:53:59.26#ibcon#flushed, iclass 19, count 0 2006.173.15:53:59.26#ibcon#about to write, iclass 19, count 0 2006.173.15:53:59.26#ibcon#wrote, iclass 19, count 0 2006.173.15:53:59.26#ibcon#about to read 3, iclass 19, count 0 2006.173.15:53:59.30#ibcon#read 3, iclass 19, count 0 2006.173.15:53:59.30#ibcon#about to read 4, iclass 19, count 0 2006.173.15:53:59.30#ibcon#read 4, iclass 19, count 0 2006.173.15:53:59.30#ibcon#about to read 5, iclass 19, count 0 2006.173.15:53:59.30#ibcon#read 5, iclass 19, count 0 2006.173.15:53:59.30#ibcon#about to read 6, iclass 19, count 0 2006.173.15:53:59.30#ibcon#read 6, iclass 19, count 0 2006.173.15:53:59.30#ibcon#end of sib2, iclass 19, count 0 2006.173.15:53:59.30#ibcon#*after write, iclass 19, count 0 2006.173.15:53:59.30#ibcon#*before return 0, iclass 19, count 0 2006.173.15:53:59.30#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.15:53:59.30#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.15:53:59.30#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.15:53:59.30#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.15:53:59.30$vck44/vb=8,4 2006.173.15:53:59.30#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.15:53:59.30#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.15:53:59.30#ibcon#ireg 11 cls_cnt 2 2006.173.15:53:59.30#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.15:53:59.36#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.15:53:59.36#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.15:53:59.36#ibcon#enter wrdev, iclass 21, count 2 2006.173.15:53:59.36#ibcon#first serial, iclass 21, count 2 2006.173.15:53:59.36#ibcon#enter sib2, iclass 21, count 2 2006.173.15:53:59.36#ibcon#flushed, iclass 21, count 2 2006.173.15:53:59.36#ibcon#about to write, iclass 21, count 2 2006.173.15:53:59.36#ibcon#wrote, iclass 21, count 2 2006.173.15:53:59.36#ibcon#about to read 3, iclass 21, count 2 2006.173.15:53:59.38#ibcon#read 3, iclass 21, count 2 2006.173.15:53:59.38#ibcon#about to read 4, iclass 21, count 2 2006.173.15:53:59.38#ibcon#read 4, iclass 21, count 2 2006.173.15:53:59.38#ibcon#about to read 5, iclass 21, count 2 2006.173.15:53:59.38#ibcon#read 5, iclass 21, count 2 2006.173.15:53:59.38#ibcon#about to read 6, iclass 21, count 2 2006.173.15:53:59.38#ibcon#read 6, iclass 21, count 2 2006.173.15:53:59.38#ibcon#end of sib2, iclass 21, count 2 2006.173.15:53:59.38#ibcon#*mode == 0, iclass 21, count 2 2006.173.15:53:59.38#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.15:53:59.38#ibcon#[27=AT08-04\r\n] 2006.173.15:53:59.38#ibcon#*before write, iclass 21, count 2 2006.173.15:53:59.38#ibcon#enter sib2, iclass 21, count 2 2006.173.15:53:59.38#ibcon#flushed, iclass 21, count 2 2006.173.15:53:59.38#ibcon#about to write, iclass 21, count 2 2006.173.15:53:59.38#ibcon#wrote, iclass 21, count 2 2006.173.15:53:59.38#ibcon#about to read 3, iclass 21, count 2 2006.173.15:53:59.41#ibcon#read 3, iclass 21, count 2 2006.173.15:53:59.41#ibcon#about to read 4, iclass 21, count 2 2006.173.15:53:59.41#ibcon#read 4, iclass 21, count 2 2006.173.15:53:59.41#ibcon#about to read 5, iclass 21, count 2 2006.173.15:53:59.41#ibcon#read 5, iclass 21, count 2 2006.173.15:53:59.41#ibcon#about to read 6, iclass 21, count 2 2006.173.15:53:59.41#ibcon#read 6, iclass 21, count 2 2006.173.15:53:59.41#ibcon#end of sib2, iclass 21, count 2 2006.173.15:53:59.41#ibcon#*after write, iclass 21, count 2 2006.173.15:53:59.41#ibcon#*before return 0, iclass 21, count 2 2006.173.15:53:59.41#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.15:53:59.41#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.15:53:59.41#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.15:53:59.41#ibcon#ireg 7 cls_cnt 0 2006.173.15:53:59.41#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.15:53:59.53#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.15:53:59.53#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.15:53:59.53#ibcon#enter wrdev, iclass 21, count 0 2006.173.15:53:59.53#ibcon#first serial, iclass 21, count 0 2006.173.15:53:59.53#ibcon#enter sib2, iclass 21, count 0 2006.173.15:53:59.53#ibcon#flushed, iclass 21, count 0 2006.173.15:53:59.53#ibcon#about to write, iclass 21, count 0 2006.173.15:53:59.53#ibcon#wrote, iclass 21, count 0 2006.173.15:53:59.53#ibcon#about to read 3, iclass 21, count 0 2006.173.15:53:59.55#ibcon#read 3, iclass 21, count 0 2006.173.15:53:59.55#ibcon#about to read 4, iclass 21, count 0 2006.173.15:53:59.55#ibcon#read 4, iclass 21, count 0 2006.173.15:53:59.55#ibcon#about to read 5, iclass 21, count 0 2006.173.15:53:59.55#ibcon#read 5, iclass 21, count 0 2006.173.15:53:59.55#ibcon#about to read 6, iclass 21, count 0 2006.173.15:53:59.55#ibcon#read 6, iclass 21, count 0 2006.173.15:53:59.55#ibcon#end of sib2, iclass 21, count 0 2006.173.15:53:59.55#ibcon#*mode == 0, iclass 21, count 0 2006.173.15:53:59.55#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.15:53:59.55#ibcon#[27=USB\r\n] 2006.173.15:53:59.55#ibcon#*before write, iclass 21, count 0 2006.173.15:53:59.55#ibcon#enter sib2, iclass 21, count 0 2006.173.15:53:59.55#ibcon#flushed, iclass 21, count 0 2006.173.15:53:59.55#ibcon#about to write, iclass 21, count 0 2006.173.15:53:59.55#ibcon#wrote, iclass 21, count 0 2006.173.15:53:59.55#ibcon#about to read 3, iclass 21, count 0 2006.173.15:53:59.58#ibcon#read 3, iclass 21, count 0 2006.173.15:53:59.58#ibcon#about to read 4, iclass 21, count 0 2006.173.15:53:59.58#ibcon#read 4, iclass 21, count 0 2006.173.15:53:59.58#ibcon#about to read 5, iclass 21, count 0 2006.173.15:53:59.58#ibcon#read 5, iclass 21, count 0 2006.173.15:53:59.58#ibcon#about to read 6, iclass 21, count 0 2006.173.15:53:59.58#ibcon#read 6, iclass 21, count 0 2006.173.15:53:59.58#ibcon#end of sib2, iclass 21, count 0 2006.173.15:53:59.58#ibcon#*after write, iclass 21, count 0 2006.173.15:53:59.58#ibcon#*before return 0, iclass 21, count 0 2006.173.15:53:59.58#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.15:53:59.58#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.15:53:59.58#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.15:53:59.58#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.15:53:59.58$vck44/vabw=wide 2006.173.15:53:59.58#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.15:53:59.58#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.15:53:59.58#ibcon#ireg 8 cls_cnt 0 2006.173.15:53:59.58#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.15:53:59.58#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.15:53:59.58#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.15:53:59.58#ibcon#enter wrdev, iclass 23, count 0 2006.173.15:53:59.58#ibcon#first serial, iclass 23, count 0 2006.173.15:53:59.58#ibcon#enter sib2, iclass 23, count 0 2006.173.15:53:59.58#ibcon#flushed, iclass 23, count 0 2006.173.15:53:59.58#ibcon#about to write, iclass 23, count 0 2006.173.15:53:59.58#ibcon#wrote, iclass 23, count 0 2006.173.15:53:59.58#ibcon#about to read 3, iclass 23, count 0 2006.173.15:53:59.60#ibcon#read 3, iclass 23, count 0 2006.173.15:53:59.60#ibcon#about to read 4, iclass 23, count 0 2006.173.15:53:59.60#ibcon#read 4, iclass 23, count 0 2006.173.15:53:59.60#ibcon#about to read 5, iclass 23, count 0 2006.173.15:53:59.60#ibcon#read 5, iclass 23, count 0 2006.173.15:53:59.60#ibcon#about to read 6, iclass 23, count 0 2006.173.15:53:59.60#ibcon#read 6, iclass 23, count 0 2006.173.15:53:59.60#ibcon#end of sib2, iclass 23, count 0 2006.173.15:53:59.60#ibcon#*mode == 0, iclass 23, count 0 2006.173.15:53:59.60#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.15:53:59.60#ibcon#[25=BW32\r\n] 2006.173.15:53:59.60#ibcon#*before write, iclass 23, count 0 2006.173.15:53:59.60#ibcon#enter sib2, iclass 23, count 0 2006.173.15:53:59.60#ibcon#flushed, iclass 23, count 0 2006.173.15:53:59.60#ibcon#about to write, iclass 23, count 0 2006.173.15:53:59.60#ibcon#wrote, iclass 23, count 0 2006.173.15:53:59.60#ibcon#about to read 3, iclass 23, count 0 2006.173.15:53:59.63#ibcon#read 3, iclass 23, count 0 2006.173.15:53:59.63#ibcon#about to read 4, iclass 23, count 0 2006.173.15:53:59.63#ibcon#read 4, iclass 23, count 0 2006.173.15:53:59.63#ibcon#about to read 5, iclass 23, count 0 2006.173.15:53:59.63#ibcon#read 5, iclass 23, count 0 2006.173.15:53:59.63#ibcon#about to read 6, iclass 23, count 0 2006.173.15:53:59.63#ibcon#read 6, iclass 23, count 0 2006.173.15:53:59.63#ibcon#end of sib2, iclass 23, count 0 2006.173.15:53:59.63#ibcon#*after write, iclass 23, count 0 2006.173.15:53:59.63#ibcon#*before return 0, iclass 23, count 0 2006.173.15:53:59.63#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.15:53:59.63#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.15:53:59.63#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.15:53:59.63#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.15:53:59.63$vck44/vbbw=wide 2006.173.15:53:59.63#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.15:53:59.63#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.15:53:59.63#ibcon#ireg 8 cls_cnt 0 2006.173.15:53:59.63#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.15:53:59.70#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.15:53:59.70#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.15:53:59.70#ibcon#enter wrdev, iclass 25, count 0 2006.173.15:53:59.70#ibcon#first serial, iclass 25, count 0 2006.173.15:53:59.70#ibcon#enter sib2, iclass 25, count 0 2006.173.15:53:59.70#ibcon#flushed, iclass 25, count 0 2006.173.15:53:59.70#ibcon#about to write, iclass 25, count 0 2006.173.15:53:59.70#ibcon#wrote, iclass 25, count 0 2006.173.15:53:59.70#ibcon#about to read 3, iclass 25, count 0 2006.173.15:53:59.72#ibcon#read 3, iclass 25, count 0 2006.173.15:53:59.72#ibcon#about to read 4, iclass 25, count 0 2006.173.15:53:59.72#ibcon#read 4, iclass 25, count 0 2006.173.15:53:59.72#ibcon#about to read 5, iclass 25, count 0 2006.173.15:53:59.72#ibcon#read 5, iclass 25, count 0 2006.173.15:53:59.72#ibcon#about to read 6, iclass 25, count 0 2006.173.15:53:59.72#ibcon#read 6, iclass 25, count 0 2006.173.15:53:59.72#ibcon#end of sib2, iclass 25, count 0 2006.173.15:53:59.72#ibcon#*mode == 0, iclass 25, count 0 2006.173.15:53:59.72#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.15:53:59.72#ibcon#[27=BW32\r\n] 2006.173.15:53:59.72#ibcon#*before write, iclass 25, count 0 2006.173.15:53:59.72#ibcon#enter sib2, iclass 25, count 0 2006.173.15:53:59.72#ibcon#flushed, iclass 25, count 0 2006.173.15:53:59.72#ibcon#about to write, iclass 25, count 0 2006.173.15:53:59.72#ibcon#wrote, iclass 25, count 0 2006.173.15:53:59.72#ibcon#about to read 3, iclass 25, count 0 2006.173.15:53:59.75#ibcon#read 3, iclass 25, count 0 2006.173.15:53:59.75#ibcon#about to read 4, iclass 25, count 0 2006.173.15:53:59.75#ibcon#read 4, iclass 25, count 0 2006.173.15:53:59.75#ibcon#about to read 5, iclass 25, count 0 2006.173.15:53:59.75#ibcon#read 5, iclass 25, count 0 2006.173.15:53:59.75#ibcon#about to read 6, iclass 25, count 0 2006.173.15:53:59.75#ibcon#read 6, iclass 25, count 0 2006.173.15:53:59.75#ibcon#end of sib2, iclass 25, count 0 2006.173.15:53:59.75#ibcon#*after write, iclass 25, count 0 2006.173.15:53:59.75#ibcon#*before return 0, iclass 25, count 0 2006.173.15:53:59.75#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.15:53:59.75#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.15:53:59.75#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.15:53:59.75#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.15:53:59.75$setupk4/ifdk4 2006.173.15:53:59.75$ifdk4/lo= 2006.173.15:53:59.75$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.15:53:59.75$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.15:53:59.75$ifdk4/patch= 2006.173.15:53:59.75$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.15:53:59.75$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.15:53:59.75$setupk4/!*+20s 2006.173.15:54:09.16#abcon#<5=/14 1.0 1.9 20.761001003.0\r\n> 2006.173.15:54:09.18#abcon#{5=INTERFACE CLEAR} 2006.173.15:54:09.24#abcon#[5=S1D000X0/0*\r\n] 2006.173.15:54:14.25$setupk4/"tpicd 2006.173.15:54:14.25$setupk4/echo=off 2006.173.15:54:14.25$setupk4/xlog=off 2006.173.15:54:14.25:!2006.173.15:55:55 2006.173.15:54:38.14#trakl#Source acquired 2006.173.15:54:40.14#flagr#flagr/antenna,acquired 2006.173.15:55:55.00:preob 2006.173.15:55:56.14/onsource/TRACKING 2006.173.15:55:56.14:!2006.173.15:56:05 2006.173.15:56:05.00:"tape 2006.173.15:56:05.00:"st=record 2006.173.15:56:05.00:data_valid=on 2006.173.15:56:05.00:midob 2006.173.15:56:05.14/onsource/TRACKING 2006.173.15:56:05.14/wx/20.75,1002.9,100 2006.173.15:56:05.30/cable/+6.5103E-03 2006.173.15:56:06.39/va/01,07,usb,yes,37,39 2006.173.15:56:06.39/va/02,06,usb,yes,36,37 2006.173.15:56:06.39/va/03,05,usb,yes,46,48 2006.173.15:56:06.39/va/04,06,usb,yes,37,39 2006.173.15:56:06.39/va/05,04,usb,yes,29,30 2006.173.15:56:06.39/va/06,03,usb,yes,41,41 2006.173.15:56:06.39/va/07,04,usb,yes,33,34 2006.173.15:56:06.39/va/08,04,usb,yes,28,34 2006.173.15:56:06.62/valo/01,524.99,yes,locked 2006.173.15:56:06.62/valo/02,534.99,yes,locked 2006.173.15:56:06.62/valo/03,564.99,yes,locked 2006.173.15:56:06.62/valo/04,624.99,yes,locked 2006.173.15:56:06.62/valo/05,734.99,yes,locked 2006.173.15:56:06.62/valo/06,814.99,yes,locked 2006.173.15:56:06.62/valo/07,864.99,yes,locked 2006.173.15:56:06.62/valo/08,884.99,yes,locked 2006.173.15:56:07.71/vb/01,04,usb,yes,30,28 2006.173.15:56:07.71/vb/02,04,usb,yes,32,32 2006.173.15:56:07.71/vb/03,04,usb,yes,29,32 2006.173.15:56:07.71/vb/04,04,usb,yes,33,32 2006.173.15:56:07.71/vb/05,04,usb,yes,26,28 2006.173.15:56:07.71/vb/06,04,usb,yes,31,27 2006.173.15:56:07.71/vb/07,04,usb,yes,30,30 2006.173.15:56:07.71/vb/08,04,usb,yes,28,31 2006.173.15:56:07.94/vblo/01,629.99,yes,locked 2006.173.15:56:07.94/vblo/02,634.99,yes,locked 2006.173.15:56:07.94/vblo/03,649.99,yes,locked 2006.173.15:56:07.94/vblo/04,679.99,yes,locked 2006.173.15:56:07.94/vblo/05,709.99,yes,locked 2006.173.15:56:07.94/vblo/06,719.99,yes,locked 2006.173.15:56:07.94/vblo/07,734.99,yes,locked 2006.173.15:56:07.94/vblo/08,744.99,yes,locked 2006.173.15:56:08.09/vabw/8 2006.173.15:56:08.24/vbbw/8 2006.173.15:56:08.33/xfe/off,on,15.2 2006.173.15:56:08.71/ifatt/23,28,28,28 2006.173.15:56:09.08/fmout-gps/S +3.99E-07 2006.173.15:56:09.12:!2006.173.16:00:05 2006.173.16:00:05.00:data_valid=off 2006.173.16:00:05.00:"et 2006.173.16:00:05.00:!+3s 2006.173.16:00:08.01:"tape 2006.173.16:00:08.01:postob 2006.173.16:00:08.25/cable/+6.5080E-03 2006.173.16:00:08.25/wx/20.71,1003.0,100 2006.173.16:00:09.08/fmout-gps/S +3.98E-07 2006.173.16:00:09.08:scan_name=173-1604,jd0606,220 2006.173.16:00:09.08:source=0014+813,001708.47,813508.1,2000.0,cw 2006.173.16:00:09.13#flagr#flagr/antenna,new-source 2006.173.16:00:10.13:checkk5 2006.173.16:00:10.47/chk_autoobs//k5ts1/ autoobs is running! 2006.173.16:00:10.87/chk_autoobs//k5ts2/ autoobs is running! 2006.173.16:00:11.29/chk_autoobs//k5ts3/ autoobs is running! 2006.173.16:00:11.69/chk_autoobs//k5ts4/ autoobs is running! 2006.173.16:00:12.09/chk_obsdata//k5ts1/T1731556??a.dat file size is correct (nominal:960MB, actual:956MB). 2006.173.16:00:12.48/chk_obsdata//k5ts2/T1731556??b.dat file size is correct (nominal:960MB, actual:956MB). 2006.173.16:00:12.86/chk_obsdata//k5ts3/T1731556??c.dat file size is correct (nominal:960MB, actual:956MB). 2006.173.16:00:13.28/chk_obsdata//k5ts4/T1731556??d.dat file size is correct (nominal:960MB, actual:956MB). 2006.173.16:00:14.00/k5log//k5ts1_log_newline 2006.173.16:00:14.69/k5log//k5ts2_log_newline 2006.173.16:00:15.41/k5log//k5ts3_log_newline 2006.173.16:00:16.11/k5log//k5ts4_log_newline 2006.173.16:00:16.13/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.16:00:16.13:setupk4=1 2006.173.16:00:16.13$setupk4/echo=on 2006.173.16:00:16.13$setupk4/pcalon 2006.173.16:00:16.13$pcalon/"no phase cal control is implemented here 2006.173.16:00:16.13$setupk4/"tpicd=stop 2006.173.16:00:16.13$setupk4/"rec=synch_on 2006.173.16:00:16.13$setupk4/"rec_mode=128 2006.173.16:00:16.13$setupk4/!* 2006.173.16:00:16.14$setupk4/recpk4 2006.173.16:00:16.14$recpk4/recpatch= 2006.173.16:00:16.14$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.16:00:16.14$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.16:00:16.14$setupk4/vck44 2006.173.16:00:16.14$vck44/valo=1,524.99 2006.173.16:00:16.14#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.16:00:16.14#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.16:00:16.14#ibcon#ireg 17 cls_cnt 0 2006.173.16:00:16.14#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.16:00:16.14#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.16:00:16.14#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.16:00:16.14#ibcon#enter wrdev, iclass 34, count 0 2006.173.16:00:16.14#ibcon#first serial, iclass 34, count 0 2006.173.16:00:16.14#ibcon#enter sib2, iclass 34, count 0 2006.173.16:00:16.14#ibcon#flushed, iclass 34, count 0 2006.173.16:00:16.14#ibcon#about to write, iclass 34, count 0 2006.173.16:00:16.14#ibcon#wrote, iclass 34, count 0 2006.173.16:00:16.14#ibcon#about to read 3, iclass 34, count 0 2006.173.16:00:16.16#ibcon#read 3, iclass 34, count 0 2006.173.16:00:16.16#ibcon#about to read 4, iclass 34, count 0 2006.173.16:00:16.16#ibcon#read 4, iclass 34, count 0 2006.173.16:00:16.16#ibcon#about to read 5, iclass 34, count 0 2006.173.16:00:16.16#ibcon#read 5, iclass 34, count 0 2006.173.16:00:16.16#ibcon#about to read 6, iclass 34, count 0 2006.173.16:00:16.16#ibcon#read 6, iclass 34, count 0 2006.173.16:00:16.16#ibcon#end of sib2, iclass 34, count 0 2006.173.16:00:16.16#ibcon#*mode == 0, iclass 34, count 0 2006.173.16:00:16.16#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.16:00:16.16#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.16:00:16.16#ibcon#*before write, iclass 34, count 0 2006.173.16:00:16.16#ibcon#enter sib2, iclass 34, count 0 2006.173.16:00:16.16#ibcon#flushed, iclass 34, count 0 2006.173.16:00:16.16#ibcon#about to write, iclass 34, count 0 2006.173.16:00:16.16#ibcon#wrote, iclass 34, count 0 2006.173.16:00:16.16#ibcon#about to read 3, iclass 34, count 0 2006.173.16:00:16.21#ibcon#read 3, iclass 34, count 0 2006.173.16:00:16.21#ibcon#about to read 4, iclass 34, count 0 2006.173.16:00:16.21#ibcon#read 4, iclass 34, count 0 2006.173.16:00:16.21#ibcon#about to read 5, iclass 34, count 0 2006.173.16:00:16.21#ibcon#read 5, iclass 34, count 0 2006.173.16:00:16.21#ibcon#about to read 6, iclass 34, count 0 2006.173.16:00:16.21#ibcon#read 6, iclass 34, count 0 2006.173.16:00:16.21#ibcon#end of sib2, iclass 34, count 0 2006.173.16:00:16.21#ibcon#*after write, iclass 34, count 0 2006.173.16:00:16.21#ibcon#*before return 0, iclass 34, count 0 2006.173.16:00:16.21#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.16:00:16.21#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.16:00:16.21#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.16:00:16.21#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.16:00:16.21$vck44/va=1,7 2006.173.16:00:16.21#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.16:00:16.21#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.16:00:16.21#ibcon#ireg 11 cls_cnt 2 2006.173.16:00:16.21#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.16:00:16.21#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.16:00:16.21#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.16:00:16.21#ibcon#enter wrdev, iclass 36, count 2 2006.173.16:00:16.21#ibcon#first serial, iclass 36, count 2 2006.173.16:00:16.21#ibcon#enter sib2, iclass 36, count 2 2006.173.16:00:16.21#ibcon#flushed, iclass 36, count 2 2006.173.16:00:16.21#ibcon#about to write, iclass 36, count 2 2006.173.16:00:16.21#ibcon#wrote, iclass 36, count 2 2006.173.16:00:16.21#ibcon#about to read 3, iclass 36, count 2 2006.173.16:00:16.23#ibcon#read 3, iclass 36, count 2 2006.173.16:00:16.23#ibcon#about to read 4, iclass 36, count 2 2006.173.16:00:16.23#ibcon#read 4, iclass 36, count 2 2006.173.16:00:16.23#ibcon#about to read 5, iclass 36, count 2 2006.173.16:00:16.23#ibcon#read 5, iclass 36, count 2 2006.173.16:00:16.23#ibcon#about to read 6, iclass 36, count 2 2006.173.16:00:16.23#ibcon#read 6, iclass 36, count 2 2006.173.16:00:16.23#ibcon#end of sib2, iclass 36, count 2 2006.173.16:00:16.23#ibcon#*mode == 0, iclass 36, count 2 2006.173.16:00:16.23#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.16:00:16.23#ibcon#[25=AT01-07\r\n] 2006.173.16:00:16.23#ibcon#*before write, iclass 36, count 2 2006.173.16:00:16.23#ibcon#enter sib2, iclass 36, count 2 2006.173.16:00:16.23#ibcon#flushed, iclass 36, count 2 2006.173.16:00:16.23#ibcon#about to write, iclass 36, count 2 2006.173.16:00:16.23#ibcon#wrote, iclass 36, count 2 2006.173.16:00:16.23#ibcon#about to read 3, iclass 36, count 2 2006.173.16:00:16.26#ibcon#read 3, iclass 36, count 2 2006.173.16:00:16.26#ibcon#about to read 4, iclass 36, count 2 2006.173.16:00:16.26#ibcon#read 4, iclass 36, count 2 2006.173.16:00:16.26#ibcon#about to read 5, iclass 36, count 2 2006.173.16:00:16.26#ibcon#read 5, iclass 36, count 2 2006.173.16:00:16.26#ibcon#about to read 6, iclass 36, count 2 2006.173.16:00:16.26#ibcon#read 6, iclass 36, count 2 2006.173.16:00:16.26#ibcon#end of sib2, iclass 36, count 2 2006.173.16:00:16.26#ibcon#*after write, iclass 36, count 2 2006.173.16:00:16.26#ibcon#*before return 0, iclass 36, count 2 2006.173.16:00:16.26#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.16:00:16.26#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.16:00:16.26#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.16:00:16.26#ibcon#ireg 7 cls_cnt 0 2006.173.16:00:16.26#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.16:00:16.38#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.16:00:16.38#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.16:00:16.38#ibcon#enter wrdev, iclass 36, count 0 2006.173.16:00:16.38#ibcon#first serial, iclass 36, count 0 2006.173.16:00:16.38#ibcon#enter sib2, iclass 36, count 0 2006.173.16:00:16.38#ibcon#flushed, iclass 36, count 0 2006.173.16:00:16.38#ibcon#about to write, iclass 36, count 0 2006.173.16:00:16.38#ibcon#wrote, iclass 36, count 0 2006.173.16:00:16.38#ibcon#about to read 3, iclass 36, count 0 2006.173.16:00:16.40#ibcon#read 3, iclass 36, count 0 2006.173.16:00:16.40#ibcon#about to read 4, iclass 36, count 0 2006.173.16:00:16.40#ibcon#read 4, iclass 36, count 0 2006.173.16:00:16.40#ibcon#about to read 5, iclass 36, count 0 2006.173.16:00:16.40#ibcon#read 5, iclass 36, count 0 2006.173.16:00:16.40#ibcon#about to read 6, iclass 36, count 0 2006.173.16:00:16.40#ibcon#read 6, iclass 36, count 0 2006.173.16:00:16.40#ibcon#end of sib2, iclass 36, count 0 2006.173.16:00:16.40#ibcon#*mode == 0, iclass 36, count 0 2006.173.16:00:16.40#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.16:00:16.40#ibcon#[25=USB\r\n] 2006.173.16:00:16.40#ibcon#*before write, iclass 36, count 0 2006.173.16:00:16.40#ibcon#enter sib2, iclass 36, count 0 2006.173.16:00:16.40#ibcon#flushed, iclass 36, count 0 2006.173.16:00:16.40#ibcon#about to write, iclass 36, count 0 2006.173.16:00:16.40#ibcon#wrote, iclass 36, count 0 2006.173.16:00:16.40#ibcon#about to read 3, iclass 36, count 0 2006.173.16:00:16.43#ibcon#read 3, iclass 36, count 0 2006.173.16:00:16.43#ibcon#about to read 4, iclass 36, count 0 2006.173.16:00:16.43#ibcon#read 4, iclass 36, count 0 2006.173.16:00:16.43#ibcon#about to read 5, iclass 36, count 0 2006.173.16:00:16.43#ibcon#read 5, iclass 36, count 0 2006.173.16:00:16.43#ibcon#about to read 6, iclass 36, count 0 2006.173.16:00:16.43#ibcon#read 6, iclass 36, count 0 2006.173.16:00:16.43#ibcon#end of sib2, iclass 36, count 0 2006.173.16:00:16.43#ibcon#*after write, iclass 36, count 0 2006.173.16:00:16.43#ibcon#*before return 0, iclass 36, count 0 2006.173.16:00:16.43#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.16:00:16.43#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.16:00:16.43#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.16:00:16.43#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.16:00:16.43$vck44/valo=2,534.99 2006.173.16:00:16.43#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.16:00:16.43#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.16:00:16.43#ibcon#ireg 17 cls_cnt 0 2006.173.16:00:16.43#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.16:00:16.43#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.16:00:16.43#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.16:00:16.43#ibcon#enter wrdev, iclass 38, count 0 2006.173.16:00:16.43#ibcon#first serial, iclass 38, count 0 2006.173.16:00:16.43#ibcon#enter sib2, iclass 38, count 0 2006.173.16:00:16.43#ibcon#flushed, iclass 38, count 0 2006.173.16:00:16.43#ibcon#about to write, iclass 38, count 0 2006.173.16:00:16.43#ibcon#wrote, iclass 38, count 0 2006.173.16:00:16.43#ibcon#about to read 3, iclass 38, count 0 2006.173.16:00:16.45#ibcon#read 3, iclass 38, count 0 2006.173.16:00:16.45#ibcon#about to read 4, iclass 38, count 0 2006.173.16:00:16.45#ibcon#read 4, iclass 38, count 0 2006.173.16:00:16.45#ibcon#about to read 5, iclass 38, count 0 2006.173.16:00:16.45#ibcon#read 5, iclass 38, count 0 2006.173.16:00:16.45#ibcon#about to read 6, iclass 38, count 0 2006.173.16:00:16.45#ibcon#read 6, iclass 38, count 0 2006.173.16:00:16.45#ibcon#end of sib2, iclass 38, count 0 2006.173.16:00:16.45#ibcon#*mode == 0, iclass 38, count 0 2006.173.16:00:16.45#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.16:00:16.45#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.16:00:16.45#ibcon#*before write, iclass 38, count 0 2006.173.16:00:16.45#ibcon#enter sib2, iclass 38, count 0 2006.173.16:00:16.45#ibcon#flushed, iclass 38, count 0 2006.173.16:00:16.45#ibcon#about to write, iclass 38, count 0 2006.173.16:00:16.45#ibcon#wrote, iclass 38, count 0 2006.173.16:00:16.45#ibcon#about to read 3, iclass 38, count 0 2006.173.16:00:16.49#ibcon#read 3, iclass 38, count 0 2006.173.16:00:16.49#ibcon#about to read 4, iclass 38, count 0 2006.173.16:00:16.49#ibcon#read 4, iclass 38, count 0 2006.173.16:00:16.49#ibcon#about to read 5, iclass 38, count 0 2006.173.16:00:16.49#ibcon#read 5, iclass 38, count 0 2006.173.16:00:16.49#ibcon#about to read 6, iclass 38, count 0 2006.173.16:00:16.49#ibcon#read 6, iclass 38, count 0 2006.173.16:00:16.49#ibcon#end of sib2, iclass 38, count 0 2006.173.16:00:16.49#ibcon#*after write, iclass 38, count 0 2006.173.16:00:16.49#ibcon#*before return 0, iclass 38, count 0 2006.173.16:00:16.49#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.16:00:16.49#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.16:00:16.49#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.16:00:16.49#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.16:00:16.49$vck44/va=2,6 2006.173.16:00:16.49#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.16:00:16.49#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.16:00:16.49#ibcon#ireg 11 cls_cnt 2 2006.173.16:00:16.49#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.16:00:16.55#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.16:00:16.55#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.16:00:16.55#ibcon#enter wrdev, iclass 40, count 2 2006.173.16:00:16.55#ibcon#first serial, iclass 40, count 2 2006.173.16:00:16.55#ibcon#enter sib2, iclass 40, count 2 2006.173.16:00:16.55#ibcon#flushed, iclass 40, count 2 2006.173.16:00:16.55#ibcon#about to write, iclass 40, count 2 2006.173.16:00:16.55#ibcon#wrote, iclass 40, count 2 2006.173.16:00:16.55#ibcon#about to read 3, iclass 40, count 2 2006.173.16:00:16.57#ibcon#read 3, iclass 40, count 2 2006.173.16:00:16.57#ibcon#about to read 4, iclass 40, count 2 2006.173.16:00:16.57#ibcon#read 4, iclass 40, count 2 2006.173.16:00:16.57#ibcon#about to read 5, iclass 40, count 2 2006.173.16:00:16.57#ibcon#read 5, iclass 40, count 2 2006.173.16:00:16.57#ibcon#about to read 6, iclass 40, count 2 2006.173.16:00:16.57#ibcon#read 6, iclass 40, count 2 2006.173.16:00:16.57#ibcon#end of sib2, iclass 40, count 2 2006.173.16:00:16.57#ibcon#*mode == 0, iclass 40, count 2 2006.173.16:00:16.57#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.16:00:16.57#ibcon#[25=AT02-06\r\n] 2006.173.16:00:16.57#ibcon#*before write, iclass 40, count 2 2006.173.16:00:16.57#ibcon#enter sib2, iclass 40, count 2 2006.173.16:00:16.57#ibcon#flushed, iclass 40, count 2 2006.173.16:00:16.57#ibcon#about to write, iclass 40, count 2 2006.173.16:00:16.57#ibcon#wrote, iclass 40, count 2 2006.173.16:00:16.57#ibcon#about to read 3, iclass 40, count 2 2006.173.16:00:16.60#ibcon#read 3, iclass 40, count 2 2006.173.16:00:16.60#ibcon#about to read 4, iclass 40, count 2 2006.173.16:00:16.60#ibcon#read 4, iclass 40, count 2 2006.173.16:00:16.60#ibcon#about to read 5, iclass 40, count 2 2006.173.16:00:16.60#ibcon#read 5, iclass 40, count 2 2006.173.16:00:16.60#ibcon#about to read 6, iclass 40, count 2 2006.173.16:00:16.60#ibcon#read 6, iclass 40, count 2 2006.173.16:00:16.60#ibcon#end of sib2, iclass 40, count 2 2006.173.16:00:16.60#ibcon#*after write, iclass 40, count 2 2006.173.16:00:16.60#ibcon#*before return 0, iclass 40, count 2 2006.173.16:00:16.60#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.16:00:16.60#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.16:00:16.60#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.16:00:16.60#ibcon#ireg 7 cls_cnt 0 2006.173.16:00:16.60#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.16:00:16.72#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.16:00:16.72#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.16:00:16.72#ibcon#enter wrdev, iclass 40, count 0 2006.173.16:00:16.72#ibcon#first serial, iclass 40, count 0 2006.173.16:00:16.72#ibcon#enter sib2, iclass 40, count 0 2006.173.16:00:16.72#ibcon#flushed, iclass 40, count 0 2006.173.16:00:16.72#ibcon#about to write, iclass 40, count 0 2006.173.16:00:16.72#ibcon#wrote, iclass 40, count 0 2006.173.16:00:16.72#ibcon#about to read 3, iclass 40, count 0 2006.173.16:00:16.74#ibcon#read 3, iclass 40, count 0 2006.173.16:00:16.74#ibcon#about to read 4, iclass 40, count 0 2006.173.16:00:16.74#ibcon#read 4, iclass 40, count 0 2006.173.16:00:16.74#ibcon#about to read 5, iclass 40, count 0 2006.173.16:00:16.74#ibcon#read 5, iclass 40, count 0 2006.173.16:00:16.74#ibcon#about to read 6, iclass 40, count 0 2006.173.16:00:16.74#ibcon#read 6, iclass 40, count 0 2006.173.16:00:16.74#ibcon#end of sib2, iclass 40, count 0 2006.173.16:00:16.74#ibcon#*mode == 0, iclass 40, count 0 2006.173.16:00:16.74#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.16:00:16.74#ibcon#[25=USB\r\n] 2006.173.16:00:16.74#ibcon#*before write, iclass 40, count 0 2006.173.16:00:16.74#ibcon#enter sib2, iclass 40, count 0 2006.173.16:00:16.74#ibcon#flushed, iclass 40, count 0 2006.173.16:00:16.74#ibcon#about to write, iclass 40, count 0 2006.173.16:00:16.74#ibcon#wrote, iclass 40, count 0 2006.173.16:00:16.74#ibcon#about to read 3, iclass 40, count 0 2006.173.16:00:16.77#ibcon#read 3, iclass 40, count 0 2006.173.16:00:16.77#ibcon#about to read 4, iclass 40, count 0 2006.173.16:00:16.77#ibcon#read 4, iclass 40, count 0 2006.173.16:00:16.77#ibcon#about to read 5, iclass 40, count 0 2006.173.16:00:16.77#ibcon#read 5, iclass 40, count 0 2006.173.16:00:16.77#ibcon#about to read 6, iclass 40, count 0 2006.173.16:00:16.77#ibcon#read 6, iclass 40, count 0 2006.173.16:00:16.77#ibcon#end of sib2, iclass 40, count 0 2006.173.16:00:16.77#ibcon#*after write, iclass 40, count 0 2006.173.16:00:16.77#ibcon#*before return 0, iclass 40, count 0 2006.173.16:00:16.77#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.16:00:16.77#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.16:00:16.77#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.16:00:16.77#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.16:00:16.77$vck44/valo=3,564.99 2006.173.16:00:16.77#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.16:00:16.77#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.16:00:16.77#ibcon#ireg 17 cls_cnt 0 2006.173.16:00:16.77#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.16:00:16.77#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.16:00:16.77#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.16:00:16.77#ibcon#enter wrdev, iclass 4, count 0 2006.173.16:00:16.77#ibcon#first serial, iclass 4, count 0 2006.173.16:00:16.77#ibcon#enter sib2, iclass 4, count 0 2006.173.16:00:16.77#ibcon#flushed, iclass 4, count 0 2006.173.16:00:16.77#ibcon#about to write, iclass 4, count 0 2006.173.16:00:16.77#ibcon#wrote, iclass 4, count 0 2006.173.16:00:16.77#ibcon#about to read 3, iclass 4, count 0 2006.173.16:00:16.79#ibcon#read 3, iclass 4, count 0 2006.173.16:00:16.79#ibcon#about to read 4, iclass 4, count 0 2006.173.16:00:16.79#ibcon#read 4, iclass 4, count 0 2006.173.16:00:16.79#ibcon#about to read 5, iclass 4, count 0 2006.173.16:00:16.79#ibcon#read 5, iclass 4, count 0 2006.173.16:00:16.79#ibcon#about to read 6, iclass 4, count 0 2006.173.16:00:16.79#ibcon#read 6, iclass 4, count 0 2006.173.16:00:16.79#ibcon#end of sib2, iclass 4, count 0 2006.173.16:00:16.79#ibcon#*mode == 0, iclass 4, count 0 2006.173.16:00:16.79#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.16:00:16.79#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.16:00:16.79#ibcon#*before write, iclass 4, count 0 2006.173.16:00:16.79#ibcon#enter sib2, iclass 4, count 0 2006.173.16:00:16.79#ibcon#flushed, iclass 4, count 0 2006.173.16:00:16.79#ibcon#about to write, iclass 4, count 0 2006.173.16:00:16.79#ibcon#wrote, iclass 4, count 0 2006.173.16:00:16.79#ibcon#about to read 3, iclass 4, count 0 2006.173.16:00:16.83#ibcon#read 3, iclass 4, count 0 2006.173.16:00:16.83#ibcon#about to read 4, iclass 4, count 0 2006.173.16:00:16.83#ibcon#read 4, iclass 4, count 0 2006.173.16:00:16.83#ibcon#about to read 5, iclass 4, count 0 2006.173.16:00:16.83#ibcon#read 5, iclass 4, count 0 2006.173.16:00:16.83#ibcon#about to read 6, iclass 4, count 0 2006.173.16:00:16.83#ibcon#read 6, iclass 4, count 0 2006.173.16:00:16.83#ibcon#end of sib2, iclass 4, count 0 2006.173.16:00:16.83#ibcon#*after write, iclass 4, count 0 2006.173.16:00:16.83#ibcon#*before return 0, iclass 4, count 0 2006.173.16:00:16.83#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.16:00:16.83#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.16:00:16.83#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.16:00:16.83#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.16:00:16.83$vck44/va=3,5 2006.173.16:00:16.83#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.16:00:16.83#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.16:00:16.83#ibcon#ireg 11 cls_cnt 2 2006.173.16:00:16.83#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.16:00:16.89#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.16:00:16.89#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.16:00:16.89#ibcon#enter wrdev, iclass 6, count 2 2006.173.16:00:16.89#ibcon#first serial, iclass 6, count 2 2006.173.16:00:16.89#ibcon#enter sib2, iclass 6, count 2 2006.173.16:00:16.89#ibcon#flushed, iclass 6, count 2 2006.173.16:00:16.89#ibcon#about to write, iclass 6, count 2 2006.173.16:00:16.89#ibcon#wrote, iclass 6, count 2 2006.173.16:00:16.89#ibcon#about to read 3, iclass 6, count 2 2006.173.16:00:16.91#ibcon#read 3, iclass 6, count 2 2006.173.16:00:16.91#ibcon#about to read 4, iclass 6, count 2 2006.173.16:00:16.91#ibcon#read 4, iclass 6, count 2 2006.173.16:00:16.91#ibcon#about to read 5, iclass 6, count 2 2006.173.16:00:16.91#ibcon#read 5, iclass 6, count 2 2006.173.16:00:16.91#ibcon#about to read 6, iclass 6, count 2 2006.173.16:00:16.91#ibcon#read 6, iclass 6, count 2 2006.173.16:00:16.91#ibcon#end of sib2, iclass 6, count 2 2006.173.16:00:16.91#ibcon#*mode == 0, iclass 6, count 2 2006.173.16:00:16.91#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.16:00:16.91#ibcon#[25=AT03-05\r\n] 2006.173.16:00:16.91#ibcon#*before write, iclass 6, count 2 2006.173.16:00:16.91#ibcon#enter sib2, iclass 6, count 2 2006.173.16:00:16.91#ibcon#flushed, iclass 6, count 2 2006.173.16:00:16.91#ibcon#about to write, iclass 6, count 2 2006.173.16:00:16.91#ibcon#wrote, iclass 6, count 2 2006.173.16:00:16.91#ibcon#about to read 3, iclass 6, count 2 2006.173.16:00:16.94#ibcon#read 3, iclass 6, count 2 2006.173.16:00:16.94#ibcon#about to read 4, iclass 6, count 2 2006.173.16:00:16.94#ibcon#read 4, iclass 6, count 2 2006.173.16:00:16.94#ibcon#about to read 5, iclass 6, count 2 2006.173.16:00:16.94#ibcon#read 5, iclass 6, count 2 2006.173.16:00:16.94#ibcon#about to read 6, iclass 6, count 2 2006.173.16:00:16.94#ibcon#read 6, iclass 6, count 2 2006.173.16:00:16.94#ibcon#end of sib2, iclass 6, count 2 2006.173.16:00:16.94#ibcon#*after write, iclass 6, count 2 2006.173.16:00:16.94#ibcon#*before return 0, iclass 6, count 2 2006.173.16:00:16.94#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.16:00:16.94#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.16:00:16.94#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.16:00:16.94#ibcon#ireg 7 cls_cnt 0 2006.173.16:00:16.94#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.16:00:17.06#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.16:00:17.06#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.16:00:17.06#ibcon#enter wrdev, iclass 6, count 0 2006.173.16:00:17.06#ibcon#first serial, iclass 6, count 0 2006.173.16:00:17.06#ibcon#enter sib2, iclass 6, count 0 2006.173.16:00:17.06#ibcon#flushed, iclass 6, count 0 2006.173.16:00:17.06#ibcon#about to write, iclass 6, count 0 2006.173.16:00:17.06#ibcon#wrote, iclass 6, count 0 2006.173.16:00:17.06#ibcon#about to read 3, iclass 6, count 0 2006.173.16:00:17.08#ibcon#read 3, iclass 6, count 0 2006.173.16:00:17.08#ibcon#about to read 4, iclass 6, count 0 2006.173.16:00:17.08#ibcon#read 4, iclass 6, count 0 2006.173.16:00:17.08#ibcon#about to read 5, iclass 6, count 0 2006.173.16:00:17.08#ibcon#read 5, iclass 6, count 0 2006.173.16:00:17.08#ibcon#about to read 6, iclass 6, count 0 2006.173.16:00:17.08#ibcon#read 6, iclass 6, count 0 2006.173.16:00:17.08#ibcon#end of sib2, iclass 6, count 0 2006.173.16:00:17.08#ibcon#*mode == 0, iclass 6, count 0 2006.173.16:00:17.08#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.16:00:17.08#ibcon#[25=USB\r\n] 2006.173.16:00:17.08#ibcon#*before write, iclass 6, count 0 2006.173.16:00:17.08#ibcon#enter sib2, iclass 6, count 0 2006.173.16:00:17.08#ibcon#flushed, iclass 6, count 0 2006.173.16:00:17.08#ibcon#about to write, iclass 6, count 0 2006.173.16:00:17.08#ibcon#wrote, iclass 6, count 0 2006.173.16:00:17.08#ibcon#about to read 3, iclass 6, count 0 2006.173.16:00:17.11#ibcon#read 3, iclass 6, count 0 2006.173.16:00:17.11#ibcon#about to read 4, iclass 6, count 0 2006.173.16:00:17.11#ibcon#read 4, iclass 6, count 0 2006.173.16:00:17.11#ibcon#about to read 5, iclass 6, count 0 2006.173.16:00:17.11#ibcon#read 5, iclass 6, count 0 2006.173.16:00:17.11#ibcon#about to read 6, iclass 6, count 0 2006.173.16:00:17.11#ibcon#read 6, iclass 6, count 0 2006.173.16:00:17.11#ibcon#end of sib2, iclass 6, count 0 2006.173.16:00:17.11#ibcon#*after write, iclass 6, count 0 2006.173.16:00:17.11#ibcon#*before return 0, iclass 6, count 0 2006.173.16:00:17.11#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.16:00:17.11#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.16:00:17.11#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.16:00:17.11#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.16:00:17.11$vck44/valo=4,624.99 2006.173.16:00:17.11#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.16:00:17.11#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.16:00:17.11#ibcon#ireg 17 cls_cnt 0 2006.173.16:00:17.11#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.16:00:17.11#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.16:00:17.11#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.16:00:17.11#ibcon#enter wrdev, iclass 10, count 0 2006.173.16:00:17.11#ibcon#first serial, iclass 10, count 0 2006.173.16:00:17.11#ibcon#enter sib2, iclass 10, count 0 2006.173.16:00:17.11#ibcon#flushed, iclass 10, count 0 2006.173.16:00:17.11#ibcon#about to write, iclass 10, count 0 2006.173.16:00:17.11#ibcon#wrote, iclass 10, count 0 2006.173.16:00:17.11#ibcon#about to read 3, iclass 10, count 0 2006.173.16:00:17.13#ibcon#read 3, iclass 10, count 0 2006.173.16:00:17.13#ibcon#about to read 4, iclass 10, count 0 2006.173.16:00:17.13#ibcon#read 4, iclass 10, count 0 2006.173.16:00:17.13#ibcon#about to read 5, iclass 10, count 0 2006.173.16:00:17.13#ibcon#read 5, iclass 10, count 0 2006.173.16:00:17.13#ibcon#about to read 6, iclass 10, count 0 2006.173.16:00:17.13#ibcon#read 6, iclass 10, count 0 2006.173.16:00:17.13#ibcon#end of sib2, iclass 10, count 0 2006.173.16:00:17.13#ibcon#*mode == 0, iclass 10, count 0 2006.173.16:00:17.13#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.16:00:17.13#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.16:00:17.13#ibcon#*before write, iclass 10, count 0 2006.173.16:00:17.13#ibcon#enter sib2, iclass 10, count 0 2006.173.16:00:17.13#ibcon#flushed, iclass 10, count 0 2006.173.16:00:17.13#ibcon#about to write, iclass 10, count 0 2006.173.16:00:17.13#ibcon#wrote, iclass 10, count 0 2006.173.16:00:17.13#ibcon#about to read 3, iclass 10, count 0 2006.173.16:00:17.17#ibcon#read 3, iclass 10, count 0 2006.173.16:00:17.17#ibcon#about to read 4, iclass 10, count 0 2006.173.16:00:17.17#ibcon#read 4, iclass 10, count 0 2006.173.16:00:17.17#ibcon#about to read 5, iclass 10, count 0 2006.173.16:00:17.17#ibcon#read 5, iclass 10, count 0 2006.173.16:00:17.17#ibcon#about to read 6, iclass 10, count 0 2006.173.16:00:17.17#ibcon#read 6, iclass 10, count 0 2006.173.16:00:17.17#ibcon#end of sib2, iclass 10, count 0 2006.173.16:00:17.17#ibcon#*after write, iclass 10, count 0 2006.173.16:00:17.17#ibcon#*before return 0, iclass 10, count 0 2006.173.16:00:17.17#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.16:00:17.17#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.16:00:17.17#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.16:00:17.17#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.16:00:17.17$vck44/va=4,6 2006.173.16:00:17.17#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.16:00:17.17#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.16:00:17.17#ibcon#ireg 11 cls_cnt 2 2006.173.16:00:17.17#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.16:00:17.23#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.16:00:17.23#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.16:00:17.23#ibcon#enter wrdev, iclass 12, count 2 2006.173.16:00:17.23#ibcon#first serial, iclass 12, count 2 2006.173.16:00:17.23#ibcon#enter sib2, iclass 12, count 2 2006.173.16:00:17.23#ibcon#flushed, iclass 12, count 2 2006.173.16:00:17.23#ibcon#about to write, iclass 12, count 2 2006.173.16:00:17.23#ibcon#wrote, iclass 12, count 2 2006.173.16:00:17.23#ibcon#about to read 3, iclass 12, count 2 2006.173.16:00:17.25#ibcon#read 3, iclass 12, count 2 2006.173.16:00:17.25#ibcon#about to read 4, iclass 12, count 2 2006.173.16:00:17.25#ibcon#read 4, iclass 12, count 2 2006.173.16:00:17.25#ibcon#about to read 5, iclass 12, count 2 2006.173.16:00:17.25#ibcon#read 5, iclass 12, count 2 2006.173.16:00:17.25#ibcon#about to read 6, iclass 12, count 2 2006.173.16:00:17.25#ibcon#read 6, iclass 12, count 2 2006.173.16:00:17.25#ibcon#end of sib2, iclass 12, count 2 2006.173.16:00:17.25#ibcon#*mode == 0, iclass 12, count 2 2006.173.16:00:17.25#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.16:00:17.25#ibcon#[25=AT04-06\r\n] 2006.173.16:00:17.25#ibcon#*before write, iclass 12, count 2 2006.173.16:00:17.25#ibcon#enter sib2, iclass 12, count 2 2006.173.16:00:17.25#ibcon#flushed, iclass 12, count 2 2006.173.16:00:17.25#ibcon#about to write, iclass 12, count 2 2006.173.16:00:17.25#ibcon#wrote, iclass 12, count 2 2006.173.16:00:17.25#ibcon#about to read 3, iclass 12, count 2 2006.173.16:00:17.28#ibcon#read 3, iclass 12, count 2 2006.173.16:00:17.28#ibcon#about to read 4, iclass 12, count 2 2006.173.16:00:17.28#ibcon#read 4, iclass 12, count 2 2006.173.16:00:17.28#ibcon#about to read 5, iclass 12, count 2 2006.173.16:00:17.28#ibcon#read 5, iclass 12, count 2 2006.173.16:00:17.28#ibcon#about to read 6, iclass 12, count 2 2006.173.16:00:17.28#ibcon#read 6, iclass 12, count 2 2006.173.16:00:17.28#ibcon#end of sib2, iclass 12, count 2 2006.173.16:00:17.28#ibcon#*after write, iclass 12, count 2 2006.173.16:00:17.28#ibcon#*before return 0, iclass 12, count 2 2006.173.16:00:17.28#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.16:00:17.28#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.16:00:17.28#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.16:00:17.28#ibcon#ireg 7 cls_cnt 0 2006.173.16:00:17.28#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.16:00:17.40#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.16:00:17.40#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.16:00:17.40#ibcon#enter wrdev, iclass 12, count 0 2006.173.16:00:17.40#ibcon#first serial, iclass 12, count 0 2006.173.16:00:17.40#ibcon#enter sib2, iclass 12, count 0 2006.173.16:00:17.40#ibcon#flushed, iclass 12, count 0 2006.173.16:00:17.40#ibcon#about to write, iclass 12, count 0 2006.173.16:00:17.40#ibcon#wrote, iclass 12, count 0 2006.173.16:00:17.40#ibcon#about to read 3, iclass 12, count 0 2006.173.16:00:17.42#ibcon#read 3, iclass 12, count 0 2006.173.16:00:17.42#ibcon#about to read 4, iclass 12, count 0 2006.173.16:00:17.42#ibcon#read 4, iclass 12, count 0 2006.173.16:00:17.42#ibcon#about to read 5, iclass 12, count 0 2006.173.16:00:17.42#ibcon#read 5, iclass 12, count 0 2006.173.16:00:17.42#ibcon#about to read 6, iclass 12, count 0 2006.173.16:00:17.42#ibcon#read 6, iclass 12, count 0 2006.173.16:00:17.42#ibcon#end of sib2, iclass 12, count 0 2006.173.16:00:17.42#ibcon#*mode == 0, iclass 12, count 0 2006.173.16:00:17.42#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.16:00:17.42#ibcon#[25=USB\r\n] 2006.173.16:00:17.42#ibcon#*before write, iclass 12, count 0 2006.173.16:00:17.42#ibcon#enter sib2, iclass 12, count 0 2006.173.16:00:17.42#ibcon#flushed, iclass 12, count 0 2006.173.16:00:17.42#ibcon#about to write, iclass 12, count 0 2006.173.16:00:17.42#ibcon#wrote, iclass 12, count 0 2006.173.16:00:17.42#ibcon#about to read 3, iclass 12, count 0 2006.173.16:00:17.45#ibcon#read 3, iclass 12, count 0 2006.173.16:00:17.45#ibcon#about to read 4, iclass 12, count 0 2006.173.16:00:17.45#ibcon#read 4, iclass 12, count 0 2006.173.16:00:17.45#ibcon#about to read 5, iclass 12, count 0 2006.173.16:00:17.45#ibcon#read 5, iclass 12, count 0 2006.173.16:00:17.45#ibcon#about to read 6, iclass 12, count 0 2006.173.16:00:17.45#ibcon#read 6, iclass 12, count 0 2006.173.16:00:17.45#ibcon#end of sib2, iclass 12, count 0 2006.173.16:00:17.45#ibcon#*after write, iclass 12, count 0 2006.173.16:00:17.45#ibcon#*before return 0, iclass 12, count 0 2006.173.16:00:17.45#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.16:00:17.45#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.16:00:17.45#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.16:00:17.45#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.16:00:17.45$vck44/valo=5,734.99 2006.173.16:00:17.45#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.16:00:17.45#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.16:00:17.45#ibcon#ireg 17 cls_cnt 0 2006.173.16:00:17.45#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.16:00:17.45#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.16:00:17.45#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.16:00:17.45#ibcon#enter wrdev, iclass 14, count 0 2006.173.16:00:17.45#ibcon#first serial, iclass 14, count 0 2006.173.16:00:17.45#ibcon#enter sib2, iclass 14, count 0 2006.173.16:00:17.45#ibcon#flushed, iclass 14, count 0 2006.173.16:00:17.45#ibcon#about to write, iclass 14, count 0 2006.173.16:00:17.45#ibcon#wrote, iclass 14, count 0 2006.173.16:00:17.45#ibcon#about to read 3, iclass 14, count 0 2006.173.16:00:17.47#ibcon#read 3, iclass 14, count 0 2006.173.16:00:17.47#ibcon#about to read 4, iclass 14, count 0 2006.173.16:00:17.47#ibcon#read 4, iclass 14, count 0 2006.173.16:00:17.47#ibcon#about to read 5, iclass 14, count 0 2006.173.16:00:17.47#ibcon#read 5, iclass 14, count 0 2006.173.16:00:17.47#ibcon#about to read 6, iclass 14, count 0 2006.173.16:00:17.47#ibcon#read 6, iclass 14, count 0 2006.173.16:00:17.47#ibcon#end of sib2, iclass 14, count 0 2006.173.16:00:17.47#ibcon#*mode == 0, iclass 14, count 0 2006.173.16:00:17.47#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.16:00:17.47#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.16:00:17.47#ibcon#*before write, iclass 14, count 0 2006.173.16:00:17.47#ibcon#enter sib2, iclass 14, count 0 2006.173.16:00:17.47#ibcon#flushed, iclass 14, count 0 2006.173.16:00:17.47#ibcon#about to write, iclass 14, count 0 2006.173.16:00:17.47#ibcon#wrote, iclass 14, count 0 2006.173.16:00:17.47#ibcon#about to read 3, iclass 14, count 0 2006.173.16:00:17.51#ibcon#read 3, iclass 14, count 0 2006.173.16:00:17.51#ibcon#about to read 4, iclass 14, count 0 2006.173.16:00:17.51#ibcon#read 4, iclass 14, count 0 2006.173.16:00:17.51#ibcon#about to read 5, iclass 14, count 0 2006.173.16:00:17.51#ibcon#read 5, iclass 14, count 0 2006.173.16:00:17.51#ibcon#about to read 6, iclass 14, count 0 2006.173.16:00:17.51#ibcon#read 6, iclass 14, count 0 2006.173.16:00:17.51#ibcon#end of sib2, iclass 14, count 0 2006.173.16:00:17.51#ibcon#*after write, iclass 14, count 0 2006.173.16:00:17.51#ibcon#*before return 0, iclass 14, count 0 2006.173.16:00:17.51#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.16:00:17.51#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.16:00:17.51#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.16:00:17.51#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.16:00:17.51$vck44/va=5,4 2006.173.16:00:17.51#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.16:00:17.51#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.16:00:17.51#ibcon#ireg 11 cls_cnt 2 2006.173.16:00:17.51#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.16:00:17.57#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.16:00:17.57#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.16:00:17.57#ibcon#enter wrdev, iclass 16, count 2 2006.173.16:00:17.57#ibcon#first serial, iclass 16, count 2 2006.173.16:00:17.57#ibcon#enter sib2, iclass 16, count 2 2006.173.16:00:17.57#ibcon#flushed, iclass 16, count 2 2006.173.16:00:17.57#ibcon#about to write, iclass 16, count 2 2006.173.16:00:17.57#ibcon#wrote, iclass 16, count 2 2006.173.16:00:17.57#ibcon#about to read 3, iclass 16, count 2 2006.173.16:00:17.59#ibcon#read 3, iclass 16, count 2 2006.173.16:00:17.59#ibcon#about to read 4, iclass 16, count 2 2006.173.16:00:17.59#ibcon#read 4, iclass 16, count 2 2006.173.16:00:17.59#ibcon#about to read 5, iclass 16, count 2 2006.173.16:00:17.59#ibcon#read 5, iclass 16, count 2 2006.173.16:00:17.59#ibcon#about to read 6, iclass 16, count 2 2006.173.16:00:17.59#ibcon#read 6, iclass 16, count 2 2006.173.16:00:17.59#ibcon#end of sib2, iclass 16, count 2 2006.173.16:00:17.59#ibcon#*mode == 0, iclass 16, count 2 2006.173.16:00:17.59#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.16:00:17.59#ibcon#[25=AT05-04\r\n] 2006.173.16:00:17.59#ibcon#*before write, iclass 16, count 2 2006.173.16:00:17.59#ibcon#enter sib2, iclass 16, count 2 2006.173.16:00:17.59#ibcon#flushed, iclass 16, count 2 2006.173.16:00:17.59#ibcon#about to write, iclass 16, count 2 2006.173.16:00:17.59#ibcon#wrote, iclass 16, count 2 2006.173.16:00:17.59#ibcon#about to read 3, iclass 16, count 2 2006.173.16:00:17.62#ibcon#read 3, iclass 16, count 2 2006.173.16:00:17.62#ibcon#about to read 4, iclass 16, count 2 2006.173.16:00:17.62#ibcon#read 4, iclass 16, count 2 2006.173.16:00:17.62#ibcon#about to read 5, iclass 16, count 2 2006.173.16:00:17.62#ibcon#read 5, iclass 16, count 2 2006.173.16:00:17.62#ibcon#about to read 6, iclass 16, count 2 2006.173.16:00:17.62#ibcon#read 6, iclass 16, count 2 2006.173.16:00:17.62#ibcon#end of sib2, iclass 16, count 2 2006.173.16:00:17.62#ibcon#*after write, iclass 16, count 2 2006.173.16:00:17.62#ibcon#*before return 0, iclass 16, count 2 2006.173.16:00:17.62#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.16:00:17.62#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.16:00:17.62#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.16:00:17.62#ibcon#ireg 7 cls_cnt 0 2006.173.16:00:17.62#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.16:00:17.74#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.16:00:17.74#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.16:00:17.74#ibcon#enter wrdev, iclass 16, count 0 2006.173.16:00:17.74#ibcon#first serial, iclass 16, count 0 2006.173.16:00:17.74#ibcon#enter sib2, iclass 16, count 0 2006.173.16:00:17.74#ibcon#flushed, iclass 16, count 0 2006.173.16:00:17.74#ibcon#about to write, iclass 16, count 0 2006.173.16:00:17.74#ibcon#wrote, iclass 16, count 0 2006.173.16:00:17.74#ibcon#about to read 3, iclass 16, count 0 2006.173.16:00:17.76#ibcon#read 3, iclass 16, count 0 2006.173.16:00:17.76#ibcon#about to read 4, iclass 16, count 0 2006.173.16:00:17.76#ibcon#read 4, iclass 16, count 0 2006.173.16:00:17.76#ibcon#about to read 5, iclass 16, count 0 2006.173.16:00:17.76#ibcon#read 5, iclass 16, count 0 2006.173.16:00:17.76#ibcon#about to read 6, iclass 16, count 0 2006.173.16:00:17.76#ibcon#read 6, iclass 16, count 0 2006.173.16:00:17.76#ibcon#end of sib2, iclass 16, count 0 2006.173.16:00:17.76#ibcon#*mode == 0, iclass 16, count 0 2006.173.16:00:17.76#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.16:00:17.76#ibcon#[25=USB\r\n] 2006.173.16:00:17.76#ibcon#*before write, iclass 16, count 0 2006.173.16:00:17.76#ibcon#enter sib2, iclass 16, count 0 2006.173.16:00:17.76#ibcon#flushed, iclass 16, count 0 2006.173.16:00:17.76#ibcon#about to write, iclass 16, count 0 2006.173.16:00:17.76#ibcon#wrote, iclass 16, count 0 2006.173.16:00:17.76#ibcon#about to read 3, iclass 16, count 0 2006.173.16:00:17.79#ibcon#read 3, iclass 16, count 0 2006.173.16:00:17.79#ibcon#about to read 4, iclass 16, count 0 2006.173.16:00:17.79#ibcon#read 4, iclass 16, count 0 2006.173.16:00:17.79#ibcon#about to read 5, iclass 16, count 0 2006.173.16:00:17.79#ibcon#read 5, iclass 16, count 0 2006.173.16:00:17.79#ibcon#about to read 6, iclass 16, count 0 2006.173.16:00:17.79#ibcon#read 6, iclass 16, count 0 2006.173.16:00:17.79#ibcon#end of sib2, iclass 16, count 0 2006.173.16:00:17.79#ibcon#*after write, iclass 16, count 0 2006.173.16:00:17.79#ibcon#*before return 0, iclass 16, count 0 2006.173.16:00:17.79#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.16:00:17.79#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.16:00:17.79#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.16:00:17.79#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.16:00:17.79$vck44/valo=6,814.99 2006.173.16:00:17.79#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.16:00:17.79#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.16:00:17.79#ibcon#ireg 17 cls_cnt 0 2006.173.16:00:17.79#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.16:00:17.79#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.16:00:17.79#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.16:00:17.79#ibcon#enter wrdev, iclass 18, count 0 2006.173.16:00:17.79#ibcon#first serial, iclass 18, count 0 2006.173.16:00:17.79#ibcon#enter sib2, iclass 18, count 0 2006.173.16:00:17.79#ibcon#flushed, iclass 18, count 0 2006.173.16:00:17.79#ibcon#about to write, iclass 18, count 0 2006.173.16:00:17.79#ibcon#wrote, iclass 18, count 0 2006.173.16:00:17.79#ibcon#about to read 3, iclass 18, count 0 2006.173.16:00:17.81#ibcon#read 3, iclass 18, count 0 2006.173.16:00:17.81#ibcon#about to read 4, iclass 18, count 0 2006.173.16:00:17.81#ibcon#read 4, iclass 18, count 0 2006.173.16:00:17.81#ibcon#about to read 5, iclass 18, count 0 2006.173.16:00:17.81#ibcon#read 5, iclass 18, count 0 2006.173.16:00:17.81#ibcon#about to read 6, iclass 18, count 0 2006.173.16:00:17.81#ibcon#read 6, iclass 18, count 0 2006.173.16:00:17.81#ibcon#end of sib2, iclass 18, count 0 2006.173.16:00:17.81#ibcon#*mode == 0, iclass 18, count 0 2006.173.16:00:17.81#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.16:00:17.81#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.16:00:17.81#ibcon#*before write, iclass 18, count 0 2006.173.16:00:17.81#ibcon#enter sib2, iclass 18, count 0 2006.173.16:00:17.81#ibcon#flushed, iclass 18, count 0 2006.173.16:00:17.81#ibcon#about to write, iclass 18, count 0 2006.173.16:00:17.81#ibcon#wrote, iclass 18, count 0 2006.173.16:00:17.81#ibcon#about to read 3, iclass 18, count 0 2006.173.16:00:17.85#ibcon#read 3, iclass 18, count 0 2006.173.16:00:17.85#ibcon#about to read 4, iclass 18, count 0 2006.173.16:00:17.85#ibcon#read 4, iclass 18, count 0 2006.173.16:00:17.85#ibcon#about to read 5, iclass 18, count 0 2006.173.16:00:17.85#ibcon#read 5, iclass 18, count 0 2006.173.16:00:17.85#ibcon#about to read 6, iclass 18, count 0 2006.173.16:00:17.85#ibcon#read 6, iclass 18, count 0 2006.173.16:00:17.85#ibcon#end of sib2, iclass 18, count 0 2006.173.16:00:17.85#ibcon#*after write, iclass 18, count 0 2006.173.16:00:17.85#ibcon#*before return 0, iclass 18, count 0 2006.173.16:00:17.85#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.16:00:17.85#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.16:00:17.85#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.16:00:17.85#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.16:00:17.85$vck44/va=6,3 2006.173.16:00:17.85#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.16:00:17.85#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.16:00:17.85#ibcon#ireg 11 cls_cnt 2 2006.173.16:00:17.85#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.16:00:17.91#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.16:00:17.91#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.16:00:17.91#ibcon#enter wrdev, iclass 20, count 2 2006.173.16:00:17.91#ibcon#first serial, iclass 20, count 2 2006.173.16:00:17.91#ibcon#enter sib2, iclass 20, count 2 2006.173.16:00:17.91#ibcon#flushed, iclass 20, count 2 2006.173.16:00:17.91#ibcon#about to write, iclass 20, count 2 2006.173.16:00:17.91#ibcon#wrote, iclass 20, count 2 2006.173.16:00:17.91#ibcon#about to read 3, iclass 20, count 2 2006.173.16:00:17.93#ibcon#read 3, iclass 20, count 2 2006.173.16:00:17.93#ibcon#about to read 4, iclass 20, count 2 2006.173.16:00:17.93#ibcon#read 4, iclass 20, count 2 2006.173.16:00:17.93#ibcon#about to read 5, iclass 20, count 2 2006.173.16:00:17.93#ibcon#read 5, iclass 20, count 2 2006.173.16:00:17.93#ibcon#about to read 6, iclass 20, count 2 2006.173.16:00:17.93#ibcon#read 6, iclass 20, count 2 2006.173.16:00:17.93#ibcon#end of sib2, iclass 20, count 2 2006.173.16:00:17.93#ibcon#*mode == 0, iclass 20, count 2 2006.173.16:00:17.93#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.16:00:17.93#ibcon#[25=AT06-03\r\n] 2006.173.16:00:17.93#ibcon#*before write, iclass 20, count 2 2006.173.16:00:17.93#ibcon#enter sib2, iclass 20, count 2 2006.173.16:00:17.93#ibcon#flushed, iclass 20, count 2 2006.173.16:00:17.93#ibcon#about to write, iclass 20, count 2 2006.173.16:00:17.93#ibcon#wrote, iclass 20, count 2 2006.173.16:00:17.93#ibcon#about to read 3, iclass 20, count 2 2006.173.16:00:17.96#ibcon#read 3, iclass 20, count 2 2006.173.16:00:17.96#ibcon#about to read 4, iclass 20, count 2 2006.173.16:00:17.96#ibcon#read 4, iclass 20, count 2 2006.173.16:00:17.96#ibcon#about to read 5, iclass 20, count 2 2006.173.16:00:17.96#ibcon#read 5, iclass 20, count 2 2006.173.16:00:17.96#ibcon#about to read 6, iclass 20, count 2 2006.173.16:00:17.96#ibcon#read 6, iclass 20, count 2 2006.173.16:00:17.96#ibcon#end of sib2, iclass 20, count 2 2006.173.16:00:17.96#ibcon#*after write, iclass 20, count 2 2006.173.16:00:17.96#ibcon#*before return 0, iclass 20, count 2 2006.173.16:00:17.96#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.16:00:17.96#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.16:00:17.96#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.16:00:17.96#ibcon#ireg 7 cls_cnt 0 2006.173.16:00:17.96#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.16:00:18.08#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.16:00:18.08#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.16:00:18.08#ibcon#enter wrdev, iclass 20, count 0 2006.173.16:00:18.08#ibcon#first serial, iclass 20, count 0 2006.173.16:00:18.08#ibcon#enter sib2, iclass 20, count 0 2006.173.16:00:18.08#ibcon#flushed, iclass 20, count 0 2006.173.16:00:18.08#ibcon#about to write, iclass 20, count 0 2006.173.16:00:18.08#ibcon#wrote, iclass 20, count 0 2006.173.16:00:18.08#ibcon#about to read 3, iclass 20, count 0 2006.173.16:00:18.10#ibcon#read 3, iclass 20, count 0 2006.173.16:00:18.10#ibcon#about to read 4, iclass 20, count 0 2006.173.16:00:18.10#ibcon#read 4, iclass 20, count 0 2006.173.16:00:18.10#ibcon#about to read 5, iclass 20, count 0 2006.173.16:00:18.10#ibcon#read 5, iclass 20, count 0 2006.173.16:00:18.10#ibcon#about to read 6, iclass 20, count 0 2006.173.16:00:18.10#ibcon#read 6, iclass 20, count 0 2006.173.16:00:18.10#ibcon#end of sib2, iclass 20, count 0 2006.173.16:00:18.10#ibcon#*mode == 0, iclass 20, count 0 2006.173.16:00:18.10#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.16:00:18.10#ibcon#[25=USB\r\n] 2006.173.16:00:18.10#ibcon#*before write, iclass 20, count 0 2006.173.16:00:18.10#ibcon#enter sib2, iclass 20, count 0 2006.173.16:00:18.10#ibcon#flushed, iclass 20, count 0 2006.173.16:00:18.10#ibcon#about to write, iclass 20, count 0 2006.173.16:00:18.10#ibcon#wrote, iclass 20, count 0 2006.173.16:00:18.10#ibcon#about to read 3, iclass 20, count 0 2006.173.16:00:18.13#ibcon#read 3, iclass 20, count 0 2006.173.16:00:18.13#ibcon#about to read 4, iclass 20, count 0 2006.173.16:00:18.13#ibcon#read 4, iclass 20, count 0 2006.173.16:00:18.13#ibcon#about to read 5, iclass 20, count 0 2006.173.16:00:18.13#ibcon#read 5, iclass 20, count 0 2006.173.16:00:18.13#ibcon#about to read 6, iclass 20, count 0 2006.173.16:00:18.13#ibcon#read 6, iclass 20, count 0 2006.173.16:00:18.13#ibcon#end of sib2, iclass 20, count 0 2006.173.16:00:18.13#ibcon#*after write, iclass 20, count 0 2006.173.16:00:18.13#ibcon#*before return 0, iclass 20, count 0 2006.173.16:00:18.13#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.16:00:18.13#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.16:00:18.13#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.16:00:18.13#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.16:00:18.13$vck44/valo=7,864.99 2006.173.16:00:18.13#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.16:00:18.13#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.16:00:18.13#ibcon#ireg 17 cls_cnt 0 2006.173.16:00:18.13#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.16:00:18.13#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.16:00:18.13#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.16:00:18.13#ibcon#enter wrdev, iclass 22, count 0 2006.173.16:00:18.13#ibcon#first serial, iclass 22, count 0 2006.173.16:00:18.13#ibcon#enter sib2, iclass 22, count 0 2006.173.16:00:18.13#ibcon#flushed, iclass 22, count 0 2006.173.16:00:18.13#ibcon#about to write, iclass 22, count 0 2006.173.16:00:18.13#ibcon#wrote, iclass 22, count 0 2006.173.16:00:18.13#ibcon#about to read 3, iclass 22, count 0 2006.173.16:00:18.15#ibcon#read 3, iclass 22, count 0 2006.173.16:00:18.15#ibcon#about to read 4, iclass 22, count 0 2006.173.16:00:18.15#ibcon#read 4, iclass 22, count 0 2006.173.16:00:18.15#ibcon#about to read 5, iclass 22, count 0 2006.173.16:00:18.15#ibcon#read 5, iclass 22, count 0 2006.173.16:00:18.15#ibcon#about to read 6, iclass 22, count 0 2006.173.16:00:18.15#ibcon#read 6, iclass 22, count 0 2006.173.16:00:18.15#ibcon#end of sib2, iclass 22, count 0 2006.173.16:00:18.15#ibcon#*mode == 0, iclass 22, count 0 2006.173.16:00:18.15#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.16:00:18.15#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.16:00:18.15#ibcon#*before write, iclass 22, count 0 2006.173.16:00:18.15#ibcon#enter sib2, iclass 22, count 0 2006.173.16:00:18.15#ibcon#flushed, iclass 22, count 0 2006.173.16:00:18.15#ibcon#about to write, iclass 22, count 0 2006.173.16:00:18.15#ibcon#wrote, iclass 22, count 0 2006.173.16:00:18.15#ibcon#about to read 3, iclass 22, count 0 2006.173.16:00:18.19#ibcon#read 3, iclass 22, count 0 2006.173.16:00:18.19#ibcon#about to read 4, iclass 22, count 0 2006.173.16:00:18.19#ibcon#read 4, iclass 22, count 0 2006.173.16:00:18.19#ibcon#about to read 5, iclass 22, count 0 2006.173.16:00:18.19#ibcon#read 5, iclass 22, count 0 2006.173.16:00:18.19#ibcon#about to read 6, iclass 22, count 0 2006.173.16:00:18.19#ibcon#read 6, iclass 22, count 0 2006.173.16:00:18.19#ibcon#end of sib2, iclass 22, count 0 2006.173.16:00:18.19#ibcon#*after write, iclass 22, count 0 2006.173.16:00:18.19#ibcon#*before return 0, iclass 22, count 0 2006.173.16:00:18.19#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.16:00:18.19#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.16:00:18.19#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.16:00:18.19#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.16:00:18.19$vck44/va=7,4 2006.173.16:00:18.19#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.16:00:18.19#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.16:00:18.19#ibcon#ireg 11 cls_cnt 2 2006.173.16:00:18.19#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.16:00:18.25#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.16:00:18.25#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.16:00:18.25#ibcon#enter wrdev, iclass 24, count 2 2006.173.16:00:18.25#ibcon#first serial, iclass 24, count 2 2006.173.16:00:18.25#ibcon#enter sib2, iclass 24, count 2 2006.173.16:00:18.25#ibcon#flushed, iclass 24, count 2 2006.173.16:00:18.25#ibcon#about to write, iclass 24, count 2 2006.173.16:00:18.25#ibcon#wrote, iclass 24, count 2 2006.173.16:00:18.25#ibcon#about to read 3, iclass 24, count 2 2006.173.16:00:18.27#ibcon#read 3, iclass 24, count 2 2006.173.16:00:18.27#ibcon#about to read 4, iclass 24, count 2 2006.173.16:00:18.27#ibcon#read 4, iclass 24, count 2 2006.173.16:00:18.27#ibcon#about to read 5, iclass 24, count 2 2006.173.16:00:18.27#ibcon#read 5, iclass 24, count 2 2006.173.16:00:18.27#ibcon#about to read 6, iclass 24, count 2 2006.173.16:00:18.27#ibcon#read 6, iclass 24, count 2 2006.173.16:00:18.27#ibcon#end of sib2, iclass 24, count 2 2006.173.16:00:18.27#ibcon#*mode == 0, iclass 24, count 2 2006.173.16:00:18.27#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.16:00:18.27#ibcon#[25=AT07-04\r\n] 2006.173.16:00:18.27#ibcon#*before write, iclass 24, count 2 2006.173.16:00:18.27#ibcon#enter sib2, iclass 24, count 2 2006.173.16:00:18.27#ibcon#flushed, iclass 24, count 2 2006.173.16:00:18.27#ibcon#about to write, iclass 24, count 2 2006.173.16:00:18.27#ibcon#wrote, iclass 24, count 2 2006.173.16:00:18.27#ibcon#about to read 3, iclass 24, count 2 2006.173.16:00:18.30#ibcon#read 3, iclass 24, count 2 2006.173.16:00:18.30#ibcon#about to read 4, iclass 24, count 2 2006.173.16:00:18.30#ibcon#read 4, iclass 24, count 2 2006.173.16:00:18.30#ibcon#about to read 5, iclass 24, count 2 2006.173.16:00:18.30#ibcon#read 5, iclass 24, count 2 2006.173.16:00:18.30#ibcon#about to read 6, iclass 24, count 2 2006.173.16:00:18.30#ibcon#read 6, iclass 24, count 2 2006.173.16:00:18.30#ibcon#end of sib2, iclass 24, count 2 2006.173.16:00:18.30#ibcon#*after write, iclass 24, count 2 2006.173.16:00:18.30#ibcon#*before return 0, iclass 24, count 2 2006.173.16:00:18.30#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.16:00:18.30#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.16:00:18.30#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.16:00:18.30#ibcon#ireg 7 cls_cnt 0 2006.173.16:00:18.30#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.16:00:18.42#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.16:00:18.42#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.16:00:18.42#ibcon#enter wrdev, iclass 24, count 0 2006.173.16:00:18.42#ibcon#first serial, iclass 24, count 0 2006.173.16:00:18.42#ibcon#enter sib2, iclass 24, count 0 2006.173.16:00:18.42#ibcon#flushed, iclass 24, count 0 2006.173.16:00:18.42#ibcon#about to write, iclass 24, count 0 2006.173.16:00:18.42#ibcon#wrote, iclass 24, count 0 2006.173.16:00:18.42#ibcon#about to read 3, iclass 24, count 0 2006.173.16:00:18.44#ibcon#read 3, iclass 24, count 0 2006.173.16:00:18.44#ibcon#about to read 4, iclass 24, count 0 2006.173.16:00:18.44#ibcon#read 4, iclass 24, count 0 2006.173.16:00:18.44#ibcon#about to read 5, iclass 24, count 0 2006.173.16:00:18.44#ibcon#read 5, iclass 24, count 0 2006.173.16:00:18.44#ibcon#about to read 6, iclass 24, count 0 2006.173.16:00:18.44#ibcon#read 6, iclass 24, count 0 2006.173.16:00:18.44#ibcon#end of sib2, iclass 24, count 0 2006.173.16:00:18.44#ibcon#*mode == 0, iclass 24, count 0 2006.173.16:00:18.44#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.16:00:18.44#ibcon#[25=USB\r\n] 2006.173.16:00:18.44#ibcon#*before write, iclass 24, count 0 2006.173.16:00:18.44#ibcon#enter sib2, iclass 24, count 0 2006.173.16:00:18.44#ibcon#flushed, iclass 24, count 0 2006.173.16:00:18.44#ibcon#about to write, iclass 24, count 0 2006.173.16:00:18.44#ibcon#wrote, iclass 24, count 0 2006.173.16:00:18.44#ibcon#about to read 3, iclass 24, count 0 2006.173.16:00:18.47#ibcon#read 3, iclass 24, count 0 2006.173.16:00:18.47#ibcon#about to read 4, iclass 24, count 0 2006.173.16:00:18.47#ibcon#read 4, iclass 24, count 0 2006.173.16:00:18.47#ibcon#about to read 5, iclass 24, count 0 2006.173.16:00:18.47#ibcon#read 5, iclass 24, count 0 2006.173.16:00:18.47#ibcon#about to read 6, iclass 24, count 0 2006.173.16:00:18.47#ibcon#read 6, iclass 24, count 0 2006.173.16:00:18.47#ibcon#end of sib2, iclass 24, count 0 2006.173.16:00:18.47#ibcon#*after write, iclass 24, count 0 2006.173.16:00:18.47#ibcon#*before return 0, iclass 24, count 0 2006.173.16:00:18.47#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.16:00:18.47#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.16:00:18.47#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.16:00:18.47#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.16:00:18.47$vck44/valo=8,884.99 2006.173.16:00:18.47#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.16:00:18.47#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.16:00:18.47#ibcon#ireg 17 cls_cnt 0 2006.173.16:00:18.47#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.16:00:18.47#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.16:00:18.47#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.16:00:18.47#ibcon#enter wrdev, iclass 26, count 0 2006.173.16:00:18.47#ibcon#first serial, iclass 26, count 0 2006.173.16:00:18.47#ibcon#enter sib2, iclass 26, count 0 2006.173.16:00:18.47#ibcon#flushed, iclass 26, count 0 2006.173.16:00:18.47#ibcon#about to write, iclass 26, count 0 2006.173.16:00:18.47#ibcon#wrote, iclass 26, count 0 2006.173.16:00:18.47#ibcon#about to read 3, iclass 26, count 0 2006.173.16:00:18.49#ibcon#read 3, iclass 26, count 0 2006.173.16:00:18.49#ibcon#about to read 4, iclass 26, count 0 2006.173.16:00:18.49#ibcon#read 4, iclass 26, count 0 2006.173.16:00:18.49#ibcon#about to read 5, iclass 26, count 0 2006.173.16:00:18.49#ibcon#read 5, iclass 26, count 0 2006.173.16:00:18.49#ibcon#about to read 6, iclass 26, count 0 2006.173.16:00:18.49#ibcon#read 6, iclass 26, count 0 2006.173.16:00:18.49#ibcon#end of sib2, iclass 26, count 0 2006.173.16:00:18.49#ibcon#*mode == 0, iclass 26, count 0 2006.173.16:00:18.49#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.16:00:18.49#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.16:00:18.49#ibcon#*before write, iclass 26, count 0 2006.173.16:00:18.49#ibcon#enter sib2, iclass 26, count 0 2006.173.16:00:18.49#ibcon#flushed, iclass 26, count 0 2006.173.16:00:18.49#ibcon#about to write, iclass 26, count 0 2006.173.16:00:18.49#ibcon#wrote, iclass 26, count 0 2006.173.16:00:18.49#ibcon#about to read 3, iclass 26, count 0 2006.173.16:00:18.53#ibcon#read 3, iclass 26, count 0 2006.173.16:00:18.53#ibcon#about to read 4, iclass 26, count 0 2006.173.16:00:18.53#ibcon#read 4, iclass 26, count 0 2006.173.16:00:18.53#ibcon#about to read 5, iclass 26, count 0 2006.173.16:00:18.53#ibcon#read 5, iclass 26, count 0 2006.173.16:00:18.53#ibcon#about to read 6, iclass 26, count 0 2006.173.16:00:18.53#ibcon#read 6, iclass 26, count 0 2006.173.16:00:18.53#ibcon#end of sib2, iclass 26, count 0 2006.173.16:00:18.53#ibcon#*after write, iclass 26, count 0 2006.173.16:00:18.53#ibcon#*before return 0, iclass 26, count 0 2006.173.16:00:18.53#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.16:00:18.53#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.16:00:18.53#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.16:00:18.53#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.16:00:18.53$vck44/va=8,4 2006.173.16:00:18.53#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.16:00:18.53#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.16:00:18.53#ibcon#ireg 11 cls_cnt 2 2006.173.16:00:18.53#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.16:00:18.59#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.16:00:18.59#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.16:00:18.59#ibcon#enter wrdev, iclass 28, count 2 2006.173.16:00:18.59#ibcon#first serial, iclass 28, count 2 2006.173.16:00:18.59#ibcon#enter sib2, iclass 28, count 2 2006.173.16:00:18.59#ibcon#flushed, iclass 28, count 2 2006.173.16:00:18.59#ibcon#about to write, iclass 28, count 2 2006.173.16:00:18.59#ibcon#wrote, iclass 28, count 2 2006.173.16:00:18.59#ibcon#about to read 3, iclass 28, count 2 2006.173.16:00:18.61#ibcon#read 3, iclass 28, count 2 2006.173.16:00:18.61#ibcon#about to read 4, iclass 28, count 2 2006.173.16:00:18.61#ibcon#read 4, iclass 28, count 2 2006.173.16:00:18.61#ibcon#about to read 5, iclass 28, count 2 2006.173.16:00:18.61#ibcon#read 5, iclass 28, count 2 2006.173.16:00:18.61#ibcon#about to read 6, iclass 28, count 2 2006.173.16:00:18.61#ibcon#read 6, iclass 28, count 2 2006.173.16:00:18.61#ibcon#end of sib2, iclass 28, count 2 2006.173.16:00:18.61#ibcon#*mode == 0, iclass 28, count 2 2006.173.16:00:18.61#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.16:00:18.61#ibcon#[25=AT08-04\r\n] 2006.173.16:00:18.61#ibcon#*before write, iclass 28, count 2 2006.173.16:00:18.61#ibcon#enter sib2, iclass 28, count 2 2006.173.16:00:18.61#ibcon#flushed, iclass 28, count 2 2006.173.16:00:18.61#ibcon#about to write, iclass 28, count 2 2006.173.16:00:18.61#ibcon#wrote, iclass 28, count 2 2006.173.16:00:18.61#ibcon#about to read 3, iclass 28, count 2 2006.173.16:00:18.64#ibcon#read 3, iclass 28, count 2 2006.173.16:00:18.64#ibcon#about to read 4, iclass 28, count 2 2006.173.16:00:18.64#ibcon#read 4, iclass 28, count 2 2006.173.16:00:18.64#ibcon#about to read 5, iclass 28, count 2 2006.173.16:00:18.64#ibcon#read 5, iclass 28, count 2 2006.173.16:00:18.64#ibcon#about to read 6, iclass 28, count 2 2006.173.16:00:18.64#ibcon#read 6, iclass 28, count 2 2006.173.16:00:18.64#ibcon#end of sib2, iclass 28, count 2 2006.173.16:00:18.64#ibcon#*after write, iclass 28, count 2 2006.173.16:00:18.64#ibcon#*before return 0, iclass 28, count 2 2006.173.16:00:18.64#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.16:00:18.64#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.16:00:18.64#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.16:00:18.64#ibcon#ireg 7 cls_cnt 0 2006.173.16:00:18.64#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.16:00:18.76#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.16:00:18.76#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.16:00:18.76#ibcon#enter wrdev, iclass 28, count 0 2006.173.16:00:18.76#ibcon#first serial, iclass 28, count 0 2006.173.16:00:18.76#ibcon#enter sib2, iclass 28, count 0 2006.173.16:00:18.76#ibcon#flushed, iclass 28, count 0 2006.173.16:00:18.76#ibcon#about to write, iclass 28, count 0 2006.173.16:00:18.76#ibcon#wrote, iclass 28, count 0 2006.173.16:00:18.76#ibcon#about to read 3, iclass 28, count 0 2006.173.16:00:18.78#ibcon#read 3, iclass 28, count 0 2006.173.16:00:18.78#ibcon#about to read 4, iclass 28, count 0 2006.173.16:00:18.78#ibcon#read 4, iclass 28, count 0 2006.173.16:00:18.78#ibcon#about to read 5, iclass 28, count 0 2006.173.16:00:18.78#ibcon#read 5, iclass 28, count 0 2006.173.16:00:18.78#ibcon#about to read 6, iclass 28, count 0 2006.173.16:00:18.78#ibcon#read 6, iclass 28, count 0 2006.173.16:00:18.78#ibcon#end of sib2, iclass 28, count 0 2006.173.16:00:18.78#ibcon#*mode == 0, iclass 28, count 0 2006.173.16:00:18.78#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.16:00:18.78#ibcon#[25=USB\r\n] 2006.173.16:00:18.78#ibcon#*before write, iclass 28, count 0 2006.173.16:00:18.78#ibcon#enter sib2, iclass 28, count 0 2006.173.16:00:18.78#ibcon#flushed, iclass 28, count 0 2006.173.16:00:18.78#ibcon#about to write, iclass 28, count 0 2006.173.16:00:18.78#ibcon#wrote, iclass 28, count 0 2006.173.16:00:18.78#ibcon#about to read 3, iclass 28, count 0 2006.173.16:00:18.81#ibcon#read 3, iclass 28, count 0 2006.173.16:00:18.81#ibcon#about to read 4, iclass 28, count 0 2006.173.16:00:18.81#ibcon#read 4, iclass 28, count 0 2006.173.16:00:18.81#ibcon#about to read 5, iclass 28, count 0 2006.173.16:00:18.81#ibcon#read 5, iclass 28, count 0 2006.173.16:00:18.81#ibcon#about to read 6, iclass 28, count 0 2006.173.16:00:18.81#ibcon#read 6, iclass 28, count 0 2006.173.16:00:18.81#ibcon#end of sib2, iclass 28, count 0 2006.173.16:00:18.81#ibcon#*after write, iclass 28, count 0 2006.173.16:00:18.81#ibcon#*before return 0, iclass 28, count 0 2006.173.16:00:18.81#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.16:00:18.81#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.16:00:18.81#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.16:00:18.81#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.16:00:18.81$vck44/vblo=1,629.99 2006.173.16:00:18.81#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.16:00:18.81#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.16:00:18.81#ibcon#ireg 17 cls_cnt 0 2006.173.16:00:18.81#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.16:00:18.81#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.16:00:18.81#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.16:00:18.81#ibcon#enter wrdev, iclass 30, count 0 2006.173.16:00:18.81#ibcon#first serial, iclass 30, count 0 2006.173.16:00:18.81#ibcon#enter sib2, iclass 30, count 0 2006.173.16:00:18.81#ibcon#flushed, iclass 30, count 0 2006.173.16:00:18.81#ibcon#about to write, iclass 30, count 0 2006.173.16:00:18.81#ibcon#wrote, iclass 30, count 0 2006.173.16:00:18.81#ibcon#about to read 3, iclass 30, count 0 2006.173.16:00:18.83#ibcon#read 3, iclass 30, count 0 2006.173.16:00:18.83#ibcon#about to read 4, iclass 30, count 0 2006.173.16:00:18.83#ibcon#read 4, iclass 30, count 0 2006.173.16:00:18.83#ibcon#about to read 5, iclass 30, count 0 2006.173.16:00:18.83#ibcon#read 5, iclass 30, count 0 2006.173.16:00:18.83#ibcon#about to read 6, iclass 30, count 0 2006.173.16:00:18.83#ibcon#read 6, iclass 30, count 0 2006.173.16:00:18.83#ibcon#end of sib2, iclass 30, count 0 2006.173.16:00:18.83#ibcon#*mode == 0, iclass 30, count 0 2006.173.16:00:18.83#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.16:00:18.83#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.16:00:18.83#ibcon#*before write, iclass 30, count 0 2006.173.16:00:18.83#ibcon#enter sib2, iclass 30, count 0 2006.173.16:00:18.83#ibcon#flushed, iclass 30, count 0 2006.173.16:00:18.83#ibcon#about to write, iclass 30, count 0 2006.173.16:00:18.83#ibcon#wrote, iclass 30, count 0 2006.173.16:00:18.83#ibcon#about to read 3, iclass 30, count 0 2006.173.16:00:18.87#ibcon#read 3, iclass 30, count 0 2006.173.16:00:18.87#ibcon#about to read 4, iclass 30, count 0 2006.173.16:00:18.87#ibcon#read 4, iclass 30, count 0 2006.173.16:00:18.87#ibcon#about to read 5, iclass 30, count 0 2006.173.16:00:18.87#ibcon#read 5, iclass 30, count 0 2006.173.16:00:18.87#ibcon#about to read 6, iclass 30, count 0 2006.173.16:00:18.87#ibcon#read 6, iclass 30, count 0 2006.173.16:00:18.87#ibcon#end of sib2, iclass 30, count 0 2006.173.16:00:18.87#ibcon#*after write, iclass 30, count 0 2006.173.16:00:18.87#ibcon#*before return 0, iclass 30, count 0 2006.173.16:00:18.87#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.16:00:18.87#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.16:00:18.87#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.16:00:18.87#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.16:00:18.87$vck44/vb=1,4 2006.173.16:00:18.87#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.173.16:00:18.87#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.173.16:00:18.87#ibcon#ireg 11 cls_cnt 2 2006.173.16:00:18.87#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.16:00:18.87#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.16:00:18.87#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.16:00:18.87#ibcon#enter wrdev, iclass 32, count 2 2006.173.16:00:18.87#ibcon#first serial, iclass 32, count 2 2006.173.16:00:18.87#ibcon#enter sib2, iclass 32, count 2 2006.173.16:00:18.87#ibcon#flushed, iclass 32, count 2 2006.173.16:00:18.87#ibcon#about to write, iclass 32, count 2 2006.173.16:00:18.87#ibcon#wrote, iclass 32, count 2 2006.173.16:00:18.87#ibcon#about to read 3, iclass 32, count 2 2006.173.16:00:18.89#ibcon#read 3, iclass 32, count 2 2006.173.16:00:18.89#ibcon#about to read 4, iclass 32, count 2 2006.173.16:00:18.89#ibcon#read 4, iclass 32, count 2 2006.173.16:00:18.89#ibcon#about to read 5, iclass 32, count 2 2006.173.16:00:18.89#ibcon#read 5, iclass 32, count 2 2006.173.16:00:18.89#ibcon#about to read 6, iclass 32, count 2 2006.173.16:00:18.89#ibcon#read 6, iclass 32, count 2 2006.173.16:00:18.89#ibcon#end of sib2, iclass 32, count 2 2006.173.16:00:18.89#ibcon#*mode == 0, iclass 32, count 2 2006.173.16:00:18.89#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.173.16:00:18.89#ibcon#[27=AT01-04\r\n] 2006.173.16:00:18.89#ibcon#*before write, iclass 32, count 2 2006.173.16:00:18.89#ibcon#enter sib2, iclass 32, count 2 2006.173.16:00:18.89#ibcon#flushed, iclass 32, count 2 2006.173.16:00:18.89#ibcon#about to write, iclass 32, count 2 2006.173.16:00:18.89#ibcon#wrote, iclass 32, count 2 2006.173.16:00:18.89#ibcon#about to read 3, iclass 32, count 2 2006.173.16:00:18.92#ibcon#read 3, iclass 32, count 2 2006.173.16:00:18.92#ibcon#about to read 4, iclass 32, count 2 2006.173.16:00:18.92#ibcon#read 4, iclass 32, count 2 2006.173.16:00:18.92#ibcon#about to read 5, iclass 32, count 2 2006.173.16:00:18.92#ibcon#read 5, iclass 32, count 2 2006.173.16:00:18.92#ibcon#about to read 6, iclass 32, count 2 2006.173.16:00:18.92#ibcon#read 6, iclass 32, count 2 2006.173.16:00:18.92#ibcon#end of sib2, iclass 32, count 2 2006.173.16:00:18.92#ibcon#*after write, iclass 32, count 2 2006.173.16:00:18.92#ibcon#*before return 0, iclass 32, count 2 2006.173.16:00:18.92#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.16:00:18.92#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.173.16:00:18.92#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.173.16:00:18.92#ibcon#ireg 7 cls_cnt 0 2006.173.16:00:18.92#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.16:00:19.04#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.16:00:19.04#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.16:00:19.04#ibcon#enter wrdev, iclass 32, count 0 2006.173.16:00:19.04#ibcon#first serial, iclass 32, count 0 2006.173.16:00:19.04#ibcon#enter sib2, iclass 32, count 0 2006.173.16:00:19.04#ibcon#flushed, iclass 32, count 0 2006.173.16:00:19.04#ibcon#about to write, iclass 32, count 0 2006.173.16:00:19.04#ibcon#wrote, iclass 32, count 0 2006.173.16:00:19.04#ibcon#about to read 3, iclass 32, count 0 2006.173.16:00:19.06#ibcon#read 3, iclass 32, count 0 2006.173.16:00:19.06#ibcon#about to read 4, iclass 32, count 0 2006.173.16:00:19.06#ibcon#read 4, iclass 32, count 0 2006.173.16:00:19.06#ibcon#about to read 5, iclass 32, count 0 2006.173.16:00:19.06#ibcon#read 5, iclass 32, count 0 2006.173.16:00:19.06#ibcon#about to read 6, iclass 32, count 0 2006.173.16:00:19.06#ibcon#read 6, iclass 32, count 0 2006.173.16:00:19.06#ibcon#end of sib2, iclass 32, count 0 2006.173.16:00:19.06#ibcon#*mode == 0, iclass 32, count 0 2006.173.16:00:19.06#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.16:00:19.06#ibcon#[27=USB\r\n] 2006.173.16:00:19.06#ibcon#*before write, iclass 32, count 0 2006.173.16:00:19.06#ibcon#enter sib2, iclass 32, count 0 2006.173.16:00:19.06#ibcon#flushed, iclass 32, count 0 2006.173.16:00:19.06#ibcon#about to write, iclass 32, count 0 2006.173.16:00:19.06#ibcon#wrote, iclass 32, count 0 2006.173.16:00:19.06#ibcon#about to read 3, iclass 32, count 0 2006.173.16:00:19.09#ibcon#read 3, iclass 32, count 0 2006.173.16:00:19.09#ibcon#about to read 4, iclass 32, count 0 2006.173.16:00:19.09#ibcon#read 4, iclass 32, count 0 2006.173.16:00:19.09#ibcon#about to read 5, iclass 32, count 0 2006.173.16:00:19.09#ibcon#read 5, iclass 32, count 0 2006.173.16:00:19.09#ibcon#about to read 6, iclass 32, count 0 2006.173.16:00:19.09#ibcon#read 6, iclass 32, count 0 2006.173.16:00:19.09#ibcon#end of sib2, iclass 32, count 0 2006.173.16:00:19.09#ibcon#*after write, iclass 32, count 0 2006.173.16:00:19.09#ibcon#*before return 0, iclass 32, count 0 2006.173.16:00:19.09#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.16:00:19.09#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.173.16:00:19.09#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.16:00:19.09#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.16:00:19.09$vck44/vblo=2,634.99 2006.173.16:00:19.09#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.16:00:19.09#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.16:00:19.09#ibcon#ireg 17 cls_cnt 0 2006.173.16:00:19.09#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.16:00:19.09#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.16:00:19.09#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.16:00:19.09#ibcon#enter wrdev, iclass 34, count 0 2006.173.16:00:19.09#ibcon#first serial, iclass 34, count 0 2006.173.16:00:19.09#ibcon#enter sib2, iclass 34, count 0 2006.173.16:00:19.09#ibcon#flushed, iclass 34, count 0 2006.173.16:00:19.09#ibcon#about to write, iclass 34, count 0 2006.173.16:00:19.09#ibcon#wrote, iclass 34, count 0 2006.173.16:00:19.09#ibcon#about to read 3, iclass 34, count 0 2006.173.16:00:19.11#ibcon#read 3, iclass 34, count 0 2006.173.16:00:19.11#ibcon#about to read 4, iclass 34, count 0 2006.173.16:00:19.11#ibcon#read 4, iclass 34, count 0 2006.173.16:00:19.11#ibcon#about to read 5, iclass 34, count 0 2006.173.16:00:19.11#ibcon#read 5, iclass 34, count 0 2006.173.16:00:19.11#ibcon#about to read 6, iclass 34, count 0 2006.173.16:00:19.11#ibcon#read 6, iclass 34, count 0 2006.173.16:00:19.11#ibcon#end of sib2, iclass 34, count 0 2006.173.16:00:19.11#ibcon#*mode == 0, iclass 34, count 0 2006.173.16:00:19.11#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.16:00:19.11#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.16:00:19.11#ibcon#*before write, iclass 34, count 0 2006.173.16:00:19.11#ibcon#enter sib2, iclass 34, count 0 2006.173.16:00:19.11#ibcon#flushed, iclass 34, count 0 2006.173.16:00:19.11#ibcon#about to write, iclass 34, count 0 2006.173.16:00:19.11#ibcon#wrote, iclass 34, count 0 2006.173.16:00:19.11#ibcon#about to read 3, iclass 34, count 0 2006.173.16:00:19.15#ibcon#read 3, iclass 34, count 0 2006.173.16:00:19.15#ibcon#about to read 4, iclass 34, count 0 2006.173.16:00:19.15#ibcon#read 4, iclass 34, count 0 2006.173.16:00:19.15#ibcon#about to read 5, iclass 34, count 0 2006.173.16:00:19.15#ibcon#read 5, iclass 34, count 0 2006.173.16:00:19.15#ibcon#about to read 6, iclass 34, count 0 2006.173.16:00:19.15#ibcon#read 6, iclass 34, count 0 2006.173.16:00:19.15#ibcon#end of sib2, iclass 34, count 0 2006.173.16:00:19.15#ibcon#*after write, iclass 34, count 0 2006.173.16:00:19.15#ibcon#*before return 0, iclass 34, count 0 2006.173.16:00:19.15#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.16:00:19.15#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.16:00:19.15#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.16:00:19.15#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.16:00:19.15$vck44/vb=2,4 2006.173.16:00:19.15#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.16:00:19.15#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.16:00:19.15#ibcon#ireg 11 cls_cnt 2 2006.173.16:00:19.15#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.16:00:19.21#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.16:00:19.21#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.16:00:19.21#ibcon#enter wrdev, iclass 36, count 2 2006.173.16:00:19.21#ibcon#first serial, iclass 36, count 2 2006.173.16:00:19.21#ibcon#enter sib2, iclass 36, count 2 2006.173.16:00:19.21#ibcon#flushed, iclass 36, count 2 2006.173.16:00:19.21#ibcon#about to write, iclass 36, count 2 2006.173.16:00:19.21#ibcon#wrote, iclass 36, count 2 2006.173.16:00:19.21#ibcon#about to read 3, iclass 36, count 2 2006.173.16:00:19.23#ibcon#read 3, iclass 36, count 2 2006.173.16:00:19.23#ibcon#about to read 4, iclass 36, count 2 2006.173.16:00:19.23#ibcon#read 4, iclass 36, count 2 2006.173.16:00:19.23#ibcon#about to read 5, iclass 36, count 2 2006.173.16:00:19.23#ibcon#read 5, iclass 36, count 2 2006.173.16:00:19.23#ibcon#about to read 6, iclass 36, count 2 2006.173.16:00:19.23#ibcon#read 6, iclass 36, count 2 2006.173.16:00:19.23#ibcon#end of sib2, iclass 36, count 2 2006.173.16:00:19.23#ibcon#*mode == 0, iclass 36, count 2 2006.173.16:00:19.23#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.16:00:19.23#ibcon#[27=AT02-04\r\n] 2006.173.16:00:19.23#ibcon#*before write, iclass 36, count 2 2006.173.16:00:19.23#ibcon#enter sib2, iclass 36, count 2 2006.173.16:00:19.23#ibcon#flushed, iclass 36, count 2 2006.173.16:00:19.23#ibcon#about to write, iclass 36, count 2 2006.173.16:00:19.23#ibcon#wrote, iclass 36, count 2 2006.173.16:00:19.23#ibcon#about to read 3, iclass 36, count 2 2006.173.16:00:19.26#ibcon#read 3, iclass 36, count 2 2006.173.16:00:19.26#ibcon#about to read 4, iclass 36, count 2 2006.173.16:00:19.26#ibcon#read 4, iclass 36, count 2 2006.173.16:00:19.26#ibcon#about to read 5, iclass 36, count 2 2006.173.16:00:19.26#ibcon#read 5, iclass 36, count 2 2006.173.16:00:19.26#ibcon#about to read 6, iclass 36, count 2 2006.173.16:00:19.26#ibcon#read 6, iclass 36, count 2 2006.173.16:00:19.26#ibcon#end of sib2, iclass 36, count 2 2006.173.16:00:19.26#ibcon#*after write, iclass 36, count 2 2006.173.16:00:19.26#ibcon#*before return 0, iclass 36, count 2 2006.173.16:00:19.26#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.16:00:19.26#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.16:00:19.26#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.16:00:19.26#ibcon#ireg 7 cls_cnt 0 2006.173.16:00:19.26#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.16:00:19.38#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.16:00:19.38#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.16:00:19.38#ibcon#enter wrdev, iclass 36, count 0 2006.173.16:00:19.38#ibcon#first serial, iclass 36, count 0 2006.173.16:00:19.38#ibcon#enter sib2, iclass 36, count 0 2006.173.16:00:19.38#ibcon#flushed, iclass 36, count 0 2006.173.16:00:19.38#ibcon#about to write, iclass 36, count 0 2006.173.16:00:19.38#ibcon#wrote, iclass 36, count 0 2006.173.16:00:19.38#ibcon#about to read 3, iclass 36, count 0 2006.173.16:00:19.40#ibcon#read 3, iclass 36, count 0 2006.173.16:00:19.40#ibcon#about to read 4, iclass 36, count 0 2006.173.16:00:19.40#ibcon#read 4, iclass 36, count 0 2006.173.16:00:19.40#ibcon#about to read 5, iclass 36, count 0 2006.173.16:00:19.40#ibcon#read 5, iclass 36, count 0 2006.173.16:00:19.40#ibcon#about to read 6, iclass 36, count 0 2006.173.16:00:19.40#ibcon#read 6, iclass 36, count 0 2006.173.16:00:19.40#ibcon#end of sib2, iclass 36, count 0 2006.173.16:00:19.40#ibcon#*mode == 0, iclass 36, count 0 2006.173.16:00:19.40#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.16:00:19.40#ibcon#[27=USB\r\n] 2006.173.16:00:19.40#ibcon#*before write, iclass 36, count 0 2006.173.16:00:19.40#ibcon#enter sib2, iclass 36, count 0 2006.173.16:00:19.40#ibcon#flushed, iclass 36, count 0 2006.173.16:00:19.40#ibcon#about to write, iclass 36, count 0 2006.173.16:00:19.40#ibcon#wrote, iclass 36, count 0 2006.173.16:00:19.40#ibcon#about to read 3, iclass 36, count 0 2006.173.16:00:19.43#ibcon#read 3, iclass 36, count 0 2006.173.16:00:19.43#ibcon#about to read 4, iclass 36, count 0 2006.173.16:00:19.43#ibcon#read 4, iclass 36, count 0 2006.173.16:00:19.43#ibcon#about to read 5, iclass 36, count 0 2006.173.16:00:19.43#ibcon#read 5, iclass 36, count 0 2006.173.16:00:19.43#ibcon#about to read 6, iclass 36, count 0 2006.173.16:00:19.43#ibcon#read 6, iclass 36, count 0 2006.173.16:00:19.43#ibcon#end of sib2, iclass 36, count 0 2006.173.16:00:19.43#ibcon#*after write, iclass 36, count 0 2006.173.16:00:19.43#ibcon#*before return 0, iclass 36, count 0 2006.173.16:00:19.43#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.16:00:19.43#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.16:00:19.43#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.16:00:19.43#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.16:00:19.43$vck44/vblo=3,649.99 2006.173.16:00:19.43#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.16:00:19.43#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.16:00:19.43#ibcon#ireg 17 cls_cnt 0 2006.173.16:00:19.43#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.16:00:19.43#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.16:00:19.43#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.16:00:19.43#ibcon#enter wrdev, iclass 38, count 0 2006.173.16:00:19.43#ibcon#first serial, iclass 38, count 0 2006.173.16:00:19.43#ibcon#enter sib2, iclass 38, count 0 2006.173.16:00:19.43#ibcon#flushed, iclass 38, count 0 2006.173.16:00:19.43#ibcon#about to write, iclass 38, count 0 2006.173.16:00:19.43#ibcon#wrote, iclass 38, count 0 2006.173.16:00:19.43#ibcon#about to read 3, iclass 38, count 0 2006.173.16:00:19.45#ibcon#read 3, iclass 38, count 0 2006.173.16:00:19.45#ibcon#about to read 4, iclass 38, count 0 2006.173.16:00:19.45#ibcon#read 4, iclass 38, count 0 2006.173.16:00:19.45#ibcon#about to read 5, iclass 38, count 0 2006.173.16:00:19.45#ibcon#read 5, iclass 38, count 0 2006.173.16:00:19.45#ibcon#about to read 6, iclass 38, count 0 2006.173.16:00:19.45#ibcon#read 6, iclass 38, count 0 2006.173.16:00:19.45#ibcon#end of sib2, iclass 38, count 0 2006.173.16:00:19.45#ibcon#*mode == 0, iclass 38, count 0 2006.173.16:00:19.45#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.16:00:19.45#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.16:00:19.45#ibcon#*before write, iclass 38, count 0 2006.173.16:00:19.45#ibcon#enter sib2, iclass 38, count 0 2006.173.16:00:19.45#ibcon#flushed, iclass 38, count 0 2006.173.16:00:19.45#ibcon#about to write, iclass 38, count 0 2006.173.16:00:19.45#ibcon#wrote, iclass 38, count 0 2006.173.16:00:19.45#ibcon#about to read 3, iclass 38, count 0 2006.173.16:00:19.49#ibcon#read 3, iclass 38, count 0 2006.173.16:00:19.49#ibcon#about to read 4, iclass 38, count 0 2006.173.16:00:19.49#ibcon#read 4, iclass 38, count 0 2006.173.16:00:19.49#ibcon#about to read 5, iclass 38, count 0 2006.173.16:00:19.49#ibcon#read 5, iclass 38, count 0 2006.173.16:00:19.49#ibcon#about to read 6, iclass 38, count 0 2006.173.16:00:19.49#ibcon#read 6, iclass 38, count 0 2006.173.16:00:19.49#ibcon#end of sib2, iclass 38, count 0 2006.173.16:00:19.49#ibcon#*after write, iclass 38, count 0 2006.173.16:00:19.49#ibcon#*before return 0, iclass 38, count 0 2006.173.16:00:19.49#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.16:00:19.49#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.16:00:19.49#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.16:00:19.49#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.16:00:19.49$vck44/vb=3,4 2006.173.16:00:19.49#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.16:00:19.49#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.16:00:19.49#ibcon#ireg 11 cls_cnt 2 2006.173.16:00:19.49#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.16:00:19.55#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.16:00:19.55#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.16:00:19.55#ibcon#enter wrdev, iclass 40, count 2 2006.173.16:00:19.55#ibcon#first serial, iclass 40, count 2 2006.173.16:00:19.55#ibcon#enter sib2, iclass 40, count 2 2006.173.16:00:19.55#ibcon#flushed, iclass 40, count 2 2006.173.16:00:19.55#ibcon#about to write, iclass 40, count 2 2006.173.16:00:19.55#ibcon#wrote, iclass 40, count 2 2006.173.16:00:19.55#ibcon#about to read 3, iclass 40, count 2 2006.173.16:00:19.57#ibcon#read 3, iclass 40, count 2 2006.173.16:00:19.57#ibcon#about to read 4, iclass 40, count 2 2006.173.16:00:19.57#ibcon#read 4, iclass 40, count 2 2006.173.16:00:19.57#ibcon#about to read 5, iclass 40, count 2 2006.173.16:00:19.57#ibcon#read 5, iclass 40, count 2 2006.173.16:00:19.57#ibcon#about to read 6, iclass 40, count 2 2006.173.16:00:19.57#ibcon#read 6, iclass 40, count 2 2006.173.16:00:19.57#ibcon#end of sib2, iclass 40, count 2 2006.173.16:00:19.57#ibcon#*mode == 0, iclass 40, count 2 2006.173.16:00:19.57#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.16:00:19.57#ibcon#[27=AT03-04\r\n] 2006.173.16:00:19.57#ibcon#*before write, iclass 40, count 2 2006.173.16:00:19.57#ibcon#enter sib2, iclass 40, count 2 2006.173.16:00:19.57#ibcon#flushed, iclass 40, count 2 2006.173.16:00:19.57#ibcon#about to write, iclass 40, count 2 2006.173.16:00:19.57#ibcon#wrote, iclass 40, count 2 2006.173.16:00:19.57#ibcon#about to read 3, iclass 40, count 2 2006.173.16:00:19.60#ibcon#read 3, iclass 40, count 2 2006.173.16:00:19.60#ibcon#about to read 4, iclass 40, count 2 2006.173.16:00:19.60#ibcon#read 4, iclass 40, count 2 2006.173.16:00:19.60#ibcon#about to read 5, iclass 40, count 2 2006.173.16:00:19.60#ibcon#read 5, iclass 40, count 2 2006.173.16:00:19.60#ibcon#about to read 6, iclass 40, count 2 2006.173.16:00:19.60#ibcon#read 6, iclass 40, count 2 2006.173.16:00:19.60#ibcon#end of sib2, iclass 40, count 2 2006.173.16:00:19.60#ibcon#*after write, iclass 40, count 2 2006.173.16:00:19.60#ibcon#*before return 0, iclass 40, count 2 2006.173.16:00:19.60#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.16:00:19.60#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.16:00:19.60#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.16:00:19.60#ibcon#ireg 7 cls_cnt 0 2006.173.16:00:19.60#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.16:00:19.72#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.16:00:19.72#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.16:00:19.72#ibcon#enter wrdev, iclass 40, count 0 2006.173.16:00:19.72#ibcon#first serial, iclass 40, count 0 2006.173.16:00:19.72#ibcon#enter sib2, iclass 40, count 0 2006.173.16:00:19.72#ibcon#flushed, iclass 40, count 0 2006.173.16:00:19.72#ibcon#about to write, iclass 40, count 0 2006.173.16:00:19.72#ibcon#wrote, iclass 40, count 0 2006.173.16:00:19.72#ibcon#about to read 3, iclass 40, count 0 2006.173.16:00:19.74#ibcon#read 3, iclass 40, count 0 2006.173.16:00:19.74#ibcon#about to read 4, iclass 40, count 0 2006.173.16:00:19.74#ibcon#read 4, iclass 40, count 0 2006.173.16:00:19.74#ibcon#about to read 5, iclass 40, count 0 2006.173.16:00:19.74#ibcon#read 5, iclass 40, count 0 2006.173.16:00:19.74#ibcon#about to read 6, iclass 40, count 0 2006.173.16:00:19.74#ibcon#read 6, iclass 40, count 0 2006.173.16:00:19.74#ibcon#end of sib2, iclass 40, count 0 2006.173.16:00:19.74#ibcon#*mode == 0, iclass 40, count 0 2006.173.16:00:19.74#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.16:00:19.74#ibcon#[27=USB\r\n] 2006.173.16:00:19.74#ibcon#*before write, iclass 40, count 0 2006.173.16:00:19.74#ibcon#enter sib2, iclass 40, count 0 2006.173.16:00:19.74#ibcon#flushed, iclass 40, count 0 2006.173.16:00:19.74#ibcon#about to write, iclass 40, count 0 2006.173.16:00:19.74#ibcon#wrote, iclass 40, count 0 2006.173.16:00:19.74#ibcon#about to read 3, iclass 40, count 0 2006.173.16:00:19.77#ibcon#read 3, iclass 40, count 0 2006.173.16:00:19.77#ibcon#about to read 4, iclass 40, count 0 2006.173.16:00:19.77#ibcon#read 4, iclass 40, count 0 2006.173.16:00:19.77#ibcon#about to read 5, iclass 40, count 0 2006.173.16:00:19.77#ibcon#read 5, iclass 40, count 0 2006.173.16:00:19.77#ibcon#about to read 6, iclass 40, count 0 2006.173.16:00:19.77#ibcon#read 6, iclass 40, count 0 2006.173.16:00:19.77#ibcon#end of sib2, iclass 40, count 0 2006.173.16:00:19.77#ibcon#*after write, iclass 40, count 0 2006.173.16:00:19.77#ibcon#*before return 0, iclass 40, count 0 2006.173.16:00:19.77#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.16:00:19.77#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.16:00:19.77#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.16:00:19.77#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.16:00:19.77$vck44/vblo=4,679.99 2006.173.16:00:19.77#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.16:00:19.77#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.16:00:19.77#ibcon#ireg 17 cls_cnt 0 2006.173.16:00:19.77#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.16:00:19.77#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.16:00:19.77#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.16:00:19.77#ibcon#enter wrdev, iclass 4, count 0 2006.173.16:00:19.77#ibcon#first serial, iclass 4, count 0 2006.173.16:00:19.77#ibcon#enter sib2, iclass 4, count 0 2006.173.16:00:19.77#ibcon#flushed, iclass 4, count 0 2006.173.16:00:19.77#ibcon#about to write, iclass 4, count 0 2006.173.16:00:19.77#ibcon#wrote, iclass 4, count 0 2006.173.16:00:19.77#ibcon#about to read 3, iclass 4, count 0 2006.173.16:00:19.79#ibcon#read 3, iclass 4, count 0 2006.173.16:00:19.79#ibcon#about to read 4, iclass 4, count 0 2006.173.16:00:19.79#ibcon#read 4, iclass 4, count 0 2006.173.16:00:19.79#ibcon#about to read 5, iclass 4, count 0 2006.173.16:00:19.79#ibcon#read 5, iclass 4, count 0 2006.173.16:00:19.79#ibcon#about to read 6, iclass 4, count 0 2006.173.16:00:19.79#ibcon#read 6, iclass 4, count 0 2006.173.16:00:19.79#ibcon#end of sib2, iclass 4, count 0 2006.173.16:00:19.79#ibcon#*mode == 0, iclass 4, count 0 2006.173.16:00:19.79#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.16:00:19.79#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.16:00:19.79#ibcon#*before write, iclass 4, count 0 2006.173.16:00:19.79#ibcon#enter sib2, iclass 4, count 0 2006.173.16:00:19.79#ibcon#flushed, iclass 4, count 0 2006.173.16:00:19.79#ibcon#about to write, iclass 4, count 0 2006.173.16:00:19.79#ibcon#wrote, iclass 4, count 0 2006.173.16:00:19.79#ibcon#about to read 3, iclass 4, count 0 2006.173.16:00:19.83#ibcon#read 3, iclass 4, count 0 2006.173.16:00:19.83#ibcon#about to read 4, iclass 4, count 0 2006.173.16:00:19.83#ibcon#read 4, iclass 4, count 0 2006.173.16:00:19.83#ibcon#about to read 5, iclass 4, count 0 2006.173.16:00:19.83#ibcon#read 5, iclass 4, count 0 2006.173.16:00:19.83#ibcon#about to read 6, iclass 4, count 0 2006.173.16:00:19.83#ibcon#read 6, iclass 4, count 0 2006.173.16:00:19.83#ibcon#end of sib2, iclass 4, count 0 2006.173.16:00:19.83#ibcon#*after write, iclass 4, count 0 2006.173.16:00:19.83#ibcon#*before return 0, iclass 4, count 0 2006.173.16:00:19.83#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.16:00:19.83#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.16:00:19.83#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.16:00:19.83#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.16:00:19.83$vck44/vb=4,4 2006.173.16:00:19.83#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.16:00:19.83#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.16:00:19.83#ibcon#ireg 11 cls_cnt 2 2006.173.16:00:19.83#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.16:00:19.89#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.16:00:19.89#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.16:00:19.89#ibcon#enter wrdev, iclass 6, count 2 2006.173.16:00:19.89#ibcon#first serial, iclass 6, count 2 2006.173.16:00:19.89#ibcon#enter sib2, iclass 6, count 2 2006.173.16:00:19.89#ibcon#flushed, iclass 6, count 2 2006.173.16:00:19.89#ibcon#about to write, iclass 6, count 2 2006.173.16:00:19.89#ibcon#wrote, iclass 6, count 2 2006.173.16:00:19.89#ibcon#about to read 3, iclass 6, count 2 2006.173.16:00:19.91#ibcon#read 3, iclass 6, count 2 2006.173.16:00:19.91#ibcon#about to read 4, iclass 6, count 2 2006.173.16:00:19.91#ibcon#read 4, iclass 6, count 2 2006.173.16:00:19.91#ibcon#about to read 5, iclass 6, count 2 2006.173.16:00:19.91#ibcon#read 5, iclass 6, count 2 2006.173.16:00:19.91#ibcon#about to read 6, iclass 6, count 2 2006.173.16:00:19.91#ibcon#read 6, iclass 6, count 2 2006.173.16:00:19.91#ibcon#end of sib2, iclass 6, count 2 2006.173.16:00:19.91#ibcon#*mode == 0, iclass 6, count 2 2006.173.16:00:19.91#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.16:00:19.91#ibcon#[27=AT04-04\r\n] 2006.173.16:00:19.91#ibcon#*before write, iclass 6, count 2 2006.173.16:00:19.91#ibcon#enter sib2, iclass 6, count 2 2006.173.16:00:19.91#ibcon#flushed, iclass 6, count 2 2006.173.16:00:19.91#ibcon#about to write, iclass 6, count 2 2006.173.16:00:19.91#ibcon#wrote, iclass 6, count 2 2006.173.16:00:19.91#ibcon#about to read 3, iclass 6, count 2 2006.173.16:00:19.94#ibcon#read 3, iclass 6, count 2 2006.173.16:00:19.94#ibcon#about to read 4, iclass 6, count 2 2006.173.16:00:19.94#ibcon#read 4, iclass 6, count 2 2006.173.16:00:19.94#ibcon#about to read 5, iclass 6, count 2 2006.173.16:00:19.94#ibcon#read 5, iclass 6, count 2 2006.173.16:00:19.94#ibcon#about to read 6, iclass 6, count 2 2006.173.16:00:19.94#ibcon#read 6, iclass 6, count 2 2006.173.16:00:19.94#ibcon#end of sib2, iclass 6, count 2 2006.173.16:00:19.94#ibcon#*after write, iclass 6, count 2 2006.173.16:00:19.94#ibcon#*before return 0, iclass 6, count 2 2006.173.16:00:19.94#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.16:00:19.94#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.16:00:19.94#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.16:00:19.94#ibcon#ireg 7 cls_cnt 0 2006.173.16:00:19.94#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.16:00:20.06#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.16:00:20.06#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.16:00:20.06#ibcon#enter wrdev, iclass 6, count 0 2006.173.16:00:20.06#ibcon#first serial, iclass 6, count 0 2006.173.16:00:20.06#ibcon#enter sib2, iclass 6, count 0 2006.173.16:00:20.06#ibcon#flushed, iclass 6, count 0 2006.173.16:00:20.06#ibcon#about to write, iclass 6, count 0 2006.173.16:00:20.06#ibcon#wrote, iclass 6, count 0 2006.173.16:00:20.06#ibcon#about to read 3, iclass 6, count 0 2006.173.16:00:20.08#ibcon#read 3, iclass 6, count 0 2006.173.16:00:20.08#ibcon#about to read 4, iclass 6, count 0 2006.173.16:00:20.08#ibcon#read 4, iclass 6, count 0 2006.173.16:00:20.08#ibcon#about to read 5, iclass 6, count 0 2006.173.16:00:20.08#ibcon#read 5, iclass 6, count 0 2006.173.16:00:20.08#ibcon#about to read 6, iclass 6, count 0 2006.173.16:00:20.08#ibcon#read 6, iclass 6, count 0 2006.173.16:00:20.08#ibcon#end of sib2, iclass 6, count 0 2006.173.16:00:20.08#ibcon#*mode == 0, iclass 6, count 0 2006.173.16:00:20.08#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.16:00:20.08#ibcon#[27=USB\r\n] 2006.173.16:00:20.08#ibcon#*before write, iclass 6, count 0 2006.173.16:00:20.08#ibcon#enter sib2, iclass 6, count 0 2006.173.16:00:20.08#ibcon#flushed, iclass 6, count 0 2006.173.16:00:20.08#ibcon#about to write, iclass 6, count 0 2006.173.16:00:20.08#ibcon#wrote, iclass 6, count 0 2006.173.16:00:20.08#ibcon#about to read 3, iclass 6, count 0 2006.173.16:00:20.11#ibcon#read 3, iclass 6, count 0 2006.173.16:00:20.11#ibcon#about to read 4, iclass 6, count 0 2006.173.16:00:20.11#ibcon#read 4, iclass 6, count 0 2006.173.16:00:20.11#ibcon#about to read 5, iclass 6, count 0 2006.173.16:00:20.11#ibcon#read 5, iclass 6, count 0 2006.173.16:00:20.11#ibcon#about to read 6, iclass 6, count 0 2006.173.16:00:20.11#ibcon#read 6, iclass 6, count 0 2006.173.16:00:20.11#ibcon#end of sib2, iclass 6, count 0 2006.173.16:00:20.11#ibcon#*after write, iclass 6, count 0 2006.173.16:00:20.11#ibcon#*before return 0, iclass 6, count 0 2006.173.16:00:20.11#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.16:00:20.11#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.16:00:20.11#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.16:00:20.11#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.16:00:20.11$vck44/vblo=5,709.99 2006.173.16:00:20.11#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.16:00:20.11#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.16:00:20.11#ibcon#ireg 17 cls_cnt 0 2006.173.16:00:20.11#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.16:00:20.11#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.16:00:20.11#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.16:00:20.11#ibcon#enter wrdev, iclass 10, count 0 2006.173.16:00:20.11#ibcon#first serial, iclass 10, count 0 2006.173.16:00:20.11#ibcon#enter sib2, iclass 10, count 0 2006.173.16:00:20.11#ibcon#flushed, iclass 10, count 0 2006.173.16:00:20.11#ibcon#about to write, iclass 10, count 0 2006.173.16:00:20.11#ibcon#wrote, iclass 10, count 0 2006.173.16:00:20.11#ibcon#about to read 3, iclass 10, count 0 2006.173.16:00:20.13#ibcon#read 3, iclass 10, count 0 2006.173.16:00:20.13#ibcon#about to read 4, iclass 10, count 0 2006.173.16:00:20.13#ibcon#read 4, iclass 10, count 0 2006.173.16:00:20.13#ibcon#about to read 5, iclass 10, count 0 2006.173.16:00:20.13#ibcon#read 5, iclass 10, count 0 2006.173.16:00:20.13#ibcon#about to read 6, iclass 10, count 0 2006.173.16:00:20.13#ibcon#read 6, iclass 10, count 0 2006.173.16:00:20.13#ibcon#end of sib2, iclass 10, count 0 2006.173.16:00:20.13#ibcon#*mode == 0, iclass 10, count 0 2006.173.16:00:20.13#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.16:00:20.13#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.16:00:20.13#ibcon#*before write, iclass 10, count 0 2006.173.16:00:20.13#ibcon#enter sib2, iclass 10, count 0 2006.173.16:00:20.13#ibcon#flushed, iclass 10, count 0 2006.173.16:00:20.13#ibcon#about to write, iclass 10, count 0 2006.173.16:00:20.13#ibcon#wrote, iclass 10, count 0 2006.173.16:00:20.13#ibcon#about to read 3, iclass 10, count 0 2006.173.16:00:20.17#ibcon#read 3, iclass 10, count 0 2006.173.16:00:20.17#ibcon#about to read 4, iclass 10, count 0 2006.173.16:00:20.17#ibcon#read 4, iclass 10, count 0 2006.173.16:00:20.17#ibcon#about to read 5, iclass 10, count 0 2006.173.16:00:20.17#ibcon#read 5, iclass 10, count 0 2006.173.16:00:20.17#ibcon#about to read 6, iclass 10, count 0 2006.173.16:00:20.17#ibcon#read 6, iclass 10, count 0 2006.173.16:00:20.17#ibcon#end of sib2, iclass 10, count 0 2006.173.16:00:20.17#ibcon#*after write, iclass 10, count 0 2006.173.16:00:20.17#ibcon#*before return 0, iclass 10, count 0 2006.173.16:00:20.17#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.16:00:20.17#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.16:00:20.17#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.16:00:20.17#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.16:00:20.17$vck44/vb=5,4 2006.173.16:00:20.17#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.16:00:20.17#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.16:00:20.17#ibcon#ireg 11 cls_cnt 2 2006.173.16:00:20.17#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.16:00:20.23#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.16:00:20.23#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.16:00:20.23#ibcon#enter wrdev, iclass 12, count 2 2006.173.16:00:20.23#ibcon#first serial, iclass 12, count 2 2006.173.16:00:20.23#ibcon#enter sib2, iclass 12, count 2 2006.173.16:00:20.23#ibcon#flushed, iclass 12, count 2 2006.173.16:00:20.23#ibcon#about to write, iclass 12, count 2 2006.173.16:00:20.23#ibcon#wrote, iclass 12, count 2 2006.173.16:00:20.23#ibcon#about to read 3, iclass 12, count 2 2006.173.16:00:20.25#ibcon#read 3, iclass 12, count 2 2006.173.16:00:20.25#ibcon#about to read 4, iclass 12, count 2 2006.173.16:00:20.25#ibcon#read 4, iclass 12, count 2 2006.173.16:00:20.25#ibcon#about to read 5, iclass 12, count 2 2006.173.16:00:20.25#ibcon#read 5, iclass 12, count 2 2006.173.16:00:20.25#ibcon#about to read 6, iclass 12, count 2 2006.173.16:00:20.25#ibcon#read 6, iclass 12, count 2 2006.173.16:00:20.25#ibcon#end of sib2, iclass 12, count 2 2006.173.16:00:20.25#ibcon#*mode == 0, iclass 12, count 2 2006.173.16:00:20.25#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.16:00:20.25#ibcon#[27=AT05-04\r\n] 2006.173.16:00:20.25#ibcon#*before write, iclass 12, count 2 2006.173.16:00:20.25#ibcon#enter sib2, iclass 12, count 2 2006.173.16:00:20.25#ibcon#flushed, iclass 12, count 2 2006.173.16:00:20.25#ibcon#about to write, iclass 12, count 2 2006.173.16:00:20.25#ibcon#wrote, iclass 12, count 2 2006.173.16:00:20.25#ibcon#about to read 3, iclass 12, count 2 2006.173.16:00:20.28#ibcon#read 3, iclass 12, count 2 2006.173.16:00:20.28#ibcon#about to read 4, iclass 12, count 2 2006.173.16:00:20.28#ibcon#read 4, iclass 12, count 2 2006.173.16:00:20.28#ibcon#about to read 5, iclass 12, count 2 2006.173.16:00:20.28#ibcon#read 5, iclass 12, count 2 2006.173.16:00:20.28#ibcon#about to read 6, iclass 12, count 2 2006.173.16:00:20.28#ibcon#read 6, iclass 12, count 2 2006.173.16:00:20.28#ibcon#end of sib2, iclass 12, count 2 2006.173.16:00:20.28#ibcon#*after write, iclass 12, count 2 2006.173.16:00:20.28#ibcon#*before return 0, iclass 12, count 2 2006.173.16:00:20.28#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.16:00:20.28#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.16:00:20.28#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.16:00:20.28#ibcon#ireg 7 cls_cnt 0 2006.173.16:00:20.28#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.16:00:20.40#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.16:00:20.40#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.16:00:20.40#ibcon#enter wrdev, iclass 12, count 0 2006.173.16:00:20.40#ibcon#first serial, iclass 12, count 0 2006.173.16:00:20.40#ibcon#enter sib2, iclass 12, count 0 2006.173.16:00:20.40#ibcon#flushed, iclass 12, count 0 2006.173.16:00:20.40#ibcon#about to write, iclass 12, count 0 2006.173.16:00:20.40#ibcon#wrote, iclass 12, count 0 2006.173.16:00:20.40#ibcon#about to read 3, iclass 12, count 0 2006.173.16:00:20.42#ibcon#read 3, iclass 12, count 0 2006.173.16:00:20.42#ibcon#about to read 4, iclass 12, count 0 2006.173.16:00:20.42#ibcon#read 4, iclass 12, count 0 2006.173.16:00:20.42#ibcon#about to read 5, iclass 12, count 0 2006.173.16:00:20.42#ibcon#read 5, iclass 12, count 0 2006.173.16:00:20.42#ibcon#about to read 6, iclass 12, count 0 2006.173.16:00:20.42#ibcon#read 6, iclass 12, count 0 2006.173.16:00:20.42#ibcon#end of sib2, iclass 12, count 0 2006.173.16:00:20.42#ibcon#*mode == 0, iclass 12, count 0 2006.173.16:00:20.42#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.16:00:20.42#ibcon#[27=USB\r\n] 2006.173.16:00:20.42#ibcon#*before write, iclass 12, count 0 2006.173.16:00:20.42#ibcon#enter sib2, iclass 12, count 0 2006.173.16:00:20.42#ibcon#flushed, iclass 12, count 0 2006.173.16:00:20.42#ibcon#about to write, iclass 12, count 0 2006.173.16:00:20.42#ibcon#wrote, iclass 12, count 0 2006.173.16:00:20.42#ibcon#about to read 3, iclass 12, count 0 2006.173.16:00:20.45#ibcon#read 3, iclass 12, count 0 2006.173.16:00:20.45#ibcon#about to read 4, iclass 12, count 0 2006.173.16:00:20.45#ibcon#read 4, iclass 12, count 0 2006.173.16:00:20.45#ibcon#about to read 5, iclass 12, count 0 2006.173.16:00:20.45#ibcon#read 5, iclass 12, count 0 2006.173.16:00:20.45#ibcon#about to read 6, iclass 12, count 0 2006.173.16:00:20.45#ibcon#read 6, iclass 12, count 0 2006.173.16:00:20.45#ibcon#end of sib2, iclass 12, count 0 2006.173.16:00:20.45#ibcon#*after write, iclass 12, count 0 2006.173.16:00:20.45#ibcon#*before return 0, iclass 12, count 0 2006.173.16:00:20.45#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.16:00:20.45#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.16:00:20.45#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.16:00:20.45#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.16:00:20.45$vck44/vblo=6,719.99 2006.173.16:00:20.45#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.16:00:20.45#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.16:00:20.45#ibcon#ireg 17 cls_cnt 0 2006.173.16:00:20.45#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.16:00:20.45#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.16:00:20.45#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.16:00:20.45#ibcon#enter wrdev, iclass 14, count 0 2006.173.16:00:20.45#ibcon#first serial, iclass 14, count 0 2006.173.16:00:20.45#ibcon#enter sib2, iclass 14, count 0 2006.173.16:00:20.45#ibcon#flushed, iclass 14, count 0 2006.173.16:00:20.45#ibcon#about to write, iclass 14, count 0 2006.173.16:00:20.45#ibcon#wrote, iclass 14, count 0 2006.173.16:00:20.45#ibcon#about to read 3, iclass 14, count 0 2006.173.16:00:20.47#ibcon#read 3, iclass 14, count 0 2006.173.16:00:20.47#ibcon#about to read 4, iclass 14, count 0 2006.173.16:00:20.47#ibcon#read 4, iclass 14, count 0 2006.173.16:00:20.47#ibcon#about to read 5, iclass 14, count 0 2006.173.16:00:20.47#ibcon#read 5, iclass 14, count 0 2006.173.16:00:20.47#ibcon#about to read 6, iclass 14, count 0 2006.173.16:00:20.47#ibcon#read 6, iclass 14, count 0 2006.173.16:00:20.47#ibcon#end of sib2, iclass 14, count 0 2006.173.16:00:20.47#ibcon#*mode == 0, iclass 14, count 0 2006.173.16:00:20.47#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.16:00:20.47#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.16:00:20.47#ibcon#*before write, iclass 14, count 0 2006.173.16:00:20.47#ibcon#enter sib2, iclass 14, count 0 2006.173.16:00:20.47#ibcon#flushed, iclass 14, count 0 2006.173.16:00:20.47#ibcon#about to write, iclass 14, count 0 2006.173.16:00:20.47#ibcon#wrote, iclass 14, count 0 2006.173.16:00:20.47#ibcon#about to read 3, iclass 14, count 0 2006.173.16:00:20.51#ibcon#read 3, iclass 14, count 0 2006.173.16:00:20.51#ibcon#about to read 4, iclass 14, count 0 2006.173.16:00:20.51#ibcon#read 4, iclass 14, count 0 2006.173.16:00:20.51#ibcon#about to read 5, iclass 14, count 0 2006.173.16:00:20.51#ibcon#read 5, iclass 14, count 0 2006.173.16:00:20.51#ibcon#about to read 6, iclass 14, count 0 2006.173.16:00:20.51#ibcon#read 6, iclass 14, count 0 2006.173.16:00:20.51#ibcon#end of sib2, iclass 14, count 0 2006.173.16:00:20.51#ibcon#*after write, iclass 14, count 0 2006.173.16:00:20.51#ibcon#*before return 0, iclass 14, count 0 2006.173.16:00:20.51#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.16:00:20.51#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.16:00:20.51#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.16:00:20.51#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.16:00:20.51$vck44/vb=6,4 2006.173.16:00:20.51#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.16:00:20.51#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.16:00:20.51#ibcon#ireg 11 cls_cnt 2 2006.173.16:00:20.51#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.16:00:20.57#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.16:00:20.57#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.16:00:20.57#ibcon#enter wrdev, iclass 16, count 2 2006.173.16:00:20.57#ibcon#first serial, iclass 16, count 2 2006.173.16:00:20.57#ibcon#enter sib2, iclass 16, count 2 2006.173.16:00:20.57#ibcon#flushed, iclass 16, count 2 2006.173.16:00:20.57#ibcon#about to write, iclass 16, count 2 2006.173.16:00:20.57#ibcon#wrote, iclass 16, count 2 2006.173.16:00:20.57#ibcon#about to read 3, iclass 16, count 2 2006.173.16:00:20.59#ibcon#read 3, iclass 16, count 2 2006.173.16:00:20.59#ibcon#about to read 4, iclass 16, count 2 2006.173.16:00:20.59#ibcon#read 4, iclass 16, count 2 2006.173.16:00:20.59#ibcon#about to read 5, iclass 16, count 2 2006.173.16:00:20.59#ibcon#read 5, iclass 16, count 2 2006.173.16:00:20.59#ibcon#about to read 6, iclass 16, count 2 2006.173.16:00:20.59#ibcon#read 6, iclass 16, count 2 2006.173.16:00:20.59#ibcon#end of sib2, iclass 16, count 2 2006.173.16:00:20.59#ibcon#*mode == 0, iclass 16, count 2 2006.173.16:00:20.59#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.16:00:20.59#ibcon#[27=AT06-04\r\n] 2006.173.16:00:20.59#ibcon#*before write, iclass 16, count 2 2006.173.16:00:20.59#ibcon#enter sib2, iclass 16, count 2 2006.173.16:00:20.59#ibcon#flushed, iclass 16, count 2 2006.173.16:00:20.59#ibcon#about to write, iclass 16, count 2 2006.173.16:00:20.59#ibcon#wrote, iclass 16, count 2 2006.173.16:00:20.59#ibcon#about to read 3, iclass 16, count 2 2006.173.16:00:20.62#ibcon#read 3, iclass 16, count 2 2006.173.16:00:20.62#ibcon#about to read 4, iclass 16, count 2 2006.173.16:00:20.62#ibcon#read 4, iclass 16, count 2 2006.173.16:00:20.62#ibcon#about to read 5, iclass 16, count 2 2006.173.16:00:20.62#ibcon#read 5, iclass 16, count 2 2006.173.16:00:20.62#ibcon#about to read 6, iclass 16, count 2 2006.173.16:00:20.62#ibcon#read 6, iclass 16, count 2 2006.173.16:00:20.62#ibcon#end of sib2, iclass 16, count 2 2006.173.16:00:20.62#ibcon#*after write, iclass 16, count 2 2006.173.16:00:20.62#ibcon#*before return 0, iclass 16, count 2 2006.173.16:00:20.62#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.16:00:20.62#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.16:00:20.62#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.16:00:20.62#ibcon#ireg 7 cls_cnt 0 2006.173.16:00:20.62#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.16:00:20.74#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.16:00:20.74#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.16:00:20.74#ibcon#enter wrdev, iclass 16, count 0 2006.173.16:00:20.74#ibcon#first serial, iclass 16, count 0 2006.173.16:00:20.74#ibcon#enter sib2, iclass 16, count 0 2006.173.16:00:20.74#ibcon#flushed, iclass 16, count 0 2006.173.16:00:20.74#ibcon#about to write, iclass 16, count 0 2006.173.16:00:20.74#ibcon#wrote, iclass 16, count 0 2006.173.16:00:20.74#ibcon#about to read 3, iclass 16, count 0 2006.173.16:00:20.76#ibcon#read 3, iclass 16, count 0 2006.173.16:00:20.76#ibcon#about to read 4, iclass 16, count 0 2006.173.16:00:20.76#ibcon#read 4, iclass 16, count 0 2006.173.16:00:20.76#ibcon#about to read 5, iclass 16, count 0 2006.173.16:00:20.76#ibcon#read 5, iclass 16, count 0 2006.173.16:00:20.76#ibcon#about to read 6, iclass 16, count 0 2006.173.16:00:20.76#ibcon#read 6, iclass 16, count 0 2006.173.16:00:20.76#ibcon#end of sib2, iclass 16, count 0 2006.173.16:00:20.76#ibcon#*mode == 0, iclass 16, count 0 2006.173.16:00:20.76#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.16:00:20.76#ibcon#[27=USB\r\n] 2006.173.16:00:20.76#ibcon#*before write, iclass 16, count 0 2006.173.16:00:20.76#ibcon#enter sib2, iclass 16, count 0 2006.173.16:00:20.76#ibcon#flushed, iclass 16, count 0 2006.173.16:00:20.76#ibcon#about to write, iclass 16, count 0 2006.173.16:00:20.76#ibcon#wrote, iclass 16, count 0 2006.173.16:00:20.76#ibcon#about to read 3, iclass 16, count 0 2006.173.16:00:20.79#ibcon#read 3, iclass 16, count 0 2006.173.16:00:20.79#ibcon#about to read 4, iclass 16, count 0 2006.173.16:00:20.79#ibcon#read 4, iclass 16, count 0 2006.173.16:00:20.79#ibcon#about to read 5, iclass 16, count 0 2006.173.16:00:20.79#ibcon#read 5, iclass 16, count 0 2006.173.16:00:20.79#ibcon#about to read 6, iclass 16, count 0 2006.173.16:00:20.79#ibcon#read 6, iclass 16, count 0 2006.173.16:00:20.79#ibcon#end of sib2, iclass 16, count 0 2006.173.16:00:20.79#ibcon#*after write, iclass 16, count 0 2006.173.16:00:20.79#ibcon#*before return 0, iclass 16, count 0 2006.173.16:00:20.79#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.16:00:20.79#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.16:00:20.79#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.16:00:20.79#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.16:00:20.79$vck44/vblo=7,734.99 2006.173.16:00:20.79#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.16:00:20.79#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.16:00:20.79#ibcon#ireg 17 cls_cnt 0 2006.173.16:00:20.79#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.16:00:20.79#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.16:00:20.79#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.16:00:20.79#ibcon#enter wrdev, iclass 18, count 0 2006.173.16:00:20.79#ibcon#first serial, iclass 18, count 0 2006.173.16:00:20.79#ibcon#enter sib2, iclass 18, count 0 2006.173.16:00:20.79#ibcon#flushed, iclass 18, count 0 2006.173.16:00:20.79#ibcon#about to write, iclass 18, count 0 2006.173.16:00:20.79#ibcon#wrote, iclass 18, count 0 2006.173.16:00:20.79#ibcon#about to read 3, iclass 18, count 0 2006.173.16:00:20.81#ibcon#read 3, iclass 18, count 0 2006.173.16:00:20.81#ibcon#about to read 4, iclass 18, count 0 2006.173.16:00:20.81#ibcon#read 4, iclass 18, count 0 2006.173.16:00:20.81#ibcon#about to read 5, iclass 18, count 0 2006.173.16:00:20.81#ibcon#read 5, iclass 18, count 0 2006.173.16:00:20.81#ibcon#about to read 6, iclass 18, count 0 2006.173.16:00:20.81#ibcon#read 6, iclass 18, count 0 2006.173.16:00:20.81#ibcon#end of sib2, iclass 18, count 0 2006.173.16:00:20.81#ibcon#*mode == 0, iclass 18, count 0 2006.173.16:00:20.81#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.16:00:20.81#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.16:00:20.81#ibcon#*before write, iclass 18, count 0 2006.173.16:00:20.81#ibcon#enter sib2, iclass 18, count 0 2006.173.16:00:20.81#ibcon#flushed, iclass 18, count 0 2006.173.16:00:20.81#ibcon#about to write, iclass 18, count 0 2006.173.16:00:20.81#ibcon#wrote, iclass 18, count 0 2006.173.16:00:20.81#ibcon#about to read 3, iclass 18, count 0 2006.173.16:00:20.85#ibcon#read 3, iclass 18, count 0 2006.173.16:00:20.85#ibcon#about to read 4, iclass 18, count 0 2006.173.16:00:20.85#ibcon#read 4, iclass 18, count 0 2006.173.16:00:20.85#ibcon#about to read 5, iclass 18, count 0 2006.173.16:00:20.85#ibcon#read 5, iclass 18, count 0 2006.173.16:00:20.85#ibcon#about to read 6, iclass 18, count 0 2006.173.16:00:20.85#ibcon#read 6, iclass 18, count 0 2006.173.16:00:20.85#ibcon#end of sib2, iclass 18, count 0 2006.173.16:00:20.85#ibcon#*after write, iclass 18, count 0 2006.173.16:00:20.85#ibcon#*before return 0, iclass 18, count 0 2006.173.16:00:20.85#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.16:00:20.85#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.16:00:20.85#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.16:00:20.85#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.16:00:20.85$vck44/vb=7,4 2006.173.16:00:20.85#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.16:00:20.85#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.16:00:20.85#ibcon#ireg 11 cls_cnt 2 2006.173.16:00:20.85#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.16:00:20.91#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.16:00:20.91#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.16:00:20.91#ibcon#enter wrdev, iclass 20, count 2 2006.173.16:00:20.91#ibcon#first serial, iclass 20, count 2 2006.173.16:00:20.91#ibcon#enter sib2, iclass 20, count 2 2006.173.16:00:20.91#ibcon#flushed, iclass 20, count 2 2006.173.16:00:20.91#ibcon#about to write, iclass 20, count 2 2006.173.16:00:20.91#ibcon#wrote, iclass 20, count 2 2006.173.16:00:20.91#ibcon#about to read 3, iclass 20, count 2 2006.173.16:00:20.93#ibcon#read 3, iclass 20, count 2 2006.173.16:00:20.93#ibcon#about to read 4, iclass 20, count 2 2006.173.16:00:20.93#ibcon#read 4, iclass 20, count 2 2006.173.16:00:20.93#ibcon#about to read 5, iclass 20, count 2 2006.173.16:00:20.93#ibcon#read 5, iclass 20, count 2 2006.173.16:00:20.93#ibcon#about to read 6, iclass 20, count 2 2006.173.16:00:20.93#ibcon#read 6, iclass 20, count 2 2006.173.16:00:20.93#ibcon#end of sib2, iclass 20, count 2 2006.173.16:00:20.93#ibcon#*mode == 0, iclass 20, count 2 2006.173.16:00:20.93#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.16:00:20.93#ibcon#[27=AT07-04\r\n] 2006.173.16:00:20.93#ibcon#*before write, iclass 20, count 2 2006.173.16:00:20.93#ibcon#enter sib2, iclass 20, count 2 2006.173.16:00:20.93#ibcon#flushed, iclass 20, count 2 2006.173.16:00:20.93#ibcon#about to write, iclass 20, count 2 2006.173.16:00:20.93#ibcon#wrote, iclass 20, count 2 2006.173.16:00:20.93#ibcon#about to read 3, iclass 20, count 2 2006.173.16:00:20.96#ibcon#read 3, iclass 20, count 2 2006.173.16:00:20.96#ibcon#about to read 4, iclass 20, count 2 2006.173.16:00:20.96#ibcon#read 4, iclass 20, count 2 2006.173.16:00:20.96#ibcon#about to read 5, iclass 20, count 2 2006.173.16:00:20.96#ibcon#read 5, iclass 20, count 2 2006.173.16:00:20.96#ibcon#about to read 6, iclass 20, count 2 2006.173.16:00:20.96#ibcon#read 6, iclass 20, count 2 2006.173.16:00:20.96#ibcon#end of sib2, iclass 20, count 2 2006.173.16:00:20.96#ibcon#*after write, iclass 20, count 2 2006.173.16:00:20.96#ibcon#*before return 0, iclass 20, count 2 2006.173.16:00:20.96#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.16:00:20.96#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.16:00:20.96#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.16:00:20.96#ibcon#ireg 7 cls_cnt 0 2006.173.16:00:20.96#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.16:00:21.08#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.16:00:21.08#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.16:00:21.08#ibcon#enter wrdev, iclass 20, count 0 2006.173.16:00:21.08#ibcon#first serial, iclass 20, count 0 2006.173.16:00:21.08#ibcon#enter sib2, iclass 20, count 0 2006.173.16:00:21.08#ibcon#flushed, iclass 20, count 0 2006.173.16:00:21.08#ibcon#about to write, iclass 20, count 0 2006.173.16:00:21.08#ibcon#wrote, iclass 20, count 0 2006.173.16:00:21.08#ibcon#about to read 3, iclass 20, count 0 2006.173.16:00:21.10#ibcon#read 3, iclass 20, count 0 2006.173.16:00:21.10#ibcon#about to read 4, iclass 20, count 0 2006.173.16:00:21.10#ibcon#read 4, iclass 20, count 0 2006.173.16:00:21.10#ibcon#about to read 5, iclass 20, count 0 2006.173.16:00:21.10#ibcon#read 5, iclass 20, count 0 2006.173.16:00:21.10#ibcon#about to read 6, iclass 20, count 0 2006.173.16:00:21.10#ibcon#read 6, iclass 20, count 0 2006.173.16:00:21.10#ibcon#end of sib2, iclass 20, count 0 2006.173.16:00:21.10#ibcon#*mode == 0, iclass 20, count 0 2006.173.16:00:21.10#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.16:00:21.10#ibcon#[27=USB\r\n] 2006.173.16:00:21.10#ibcon#*before write, iclass 20, count 0 2006.173.16:00:21.10#ibcon#enter sib2, iclass 20, count 0 2006.173.16:00:21.10#ibcon#flushed, iclass 20, count 0 2006.173.16:00:21.10#ibcon#about to write, iclass 20, count 0 2006.173.16:00:21.10#ibcon#wrote, iclass 20, count 0 2006.173.16:00:21.10#ibcon#about to read 3, iclass 20, count 0 2006.173.16:00:21.13#ibcon#read 3, iclass 20, count 0 2006.173.16:00:21.13#ibcon#about to read 4, iclass 20, count 0 2006.173.16:00:21.13#ibcon#read 4, iclass 20, count 0 2006.173.16:00:21.13#ibcon#about to read 5, iclass 20, count 0 2006.173.16:00:21.13#ibcon#read 5, iclass 20, count 0 2006.173.16:00:21.13#ibcon#about to read 6, iclass 20, count 0 2006.173.16:00:21.13#ibcon#read 6, iclass 20, count 0 2006.173.16:00:21.13#ibcon#end of sib2, iclass 20, count 0 2006.173.16:00:21.13#ibcon#*after write, iclass 20, count 0 2006.173.16:00:21.13#ibcon#*before return 0, iclass 20, count 0 2006.173.16:00:21.13#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.16:00:21.13#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.16:00:21.13#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.16:00:21.13#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.16:00:21.13$vck44/vblo=8,744.99 2006.173.16:00:21.13#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.16:00:21.13#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.16:00:21.13#ibcon#ireg 17 cls_cnt 0 2006.173.16:00:21.13#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.16:00:21.13#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.16:00:21.13#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.16:00:21.13#ibcon#enter wrdev, iclass 22, count 0 2006.173.16:00:21.13#ibcon#first serial, iclass 22, count 0 2006.173.16:00:21.13#ibcon#enter sib2, iclass 22, count 0 2006.173.16:00:21.13#ibcon#flushed, iclass 22, count 0 2006.173.16:00:21.13#ibcon#about to write, iclass 22, count 0 2006.173.16:00:21.13#ibcon#wrote, iclass 22, count 0 2006.173.16:00:21.13#ibcon#about to read 3, iclass 22, count 0 2006.173.16:00:21.15#ibcon#read 3, iclass 22, count 0 2006.173.16:00:21.15#ibcon#about to read 4, iclass 22, count 0 2006.173.16:00:21.15#ibcon#read 4, iclass 22, count 0 2006.173.16:00:21.15#ibcon#about to read 5, iclass 22, count 0 2006.173.16:00:21.15#ibcon#read 5, iclass 22, count 0 2006.173.16:00:21.15#ibcon#about to read 6, iclass 22, count 0 2006.173.16:00:21.15#ibcon#read 6, iclass 22, count 0 2006.173.16:00:21.15#ibcon#end of sib2, iclass 22, count 0 2006.173.16:00:21.15#ibcon#*mode == 0, iclass 22, count 0 2006.173.16:00:21.15#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.16:00:21.15#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.16:00:21.15#ibcon#*before write, iclass 22, count 0 2006.173.16:00:21.15#ibcon#enter sib2, iclass 22, count 0 2006.173.16:00:21.15#ibcon#flushed, iclass 22, count 0 2006.173.16:00:21.15#ibcon#about to write, iclass 22, count 0 2006.173.16:00:21.15#ibcon#wrote, iclass 22, count 0 2006.173.16:00:21.15#ibcon#about to read 3, iclass 22, count 0 2006.173.16:00:21.19#ibcon#read 3, iclass 22, count 0 2006.173.16:00:21.19#ibcon#about to read 4, iclass 22, count 0 2006.173.16:00:21.19#ibcon#read 4, iclass 22, count 0 2006.173.16:00:21.19#ibcon#about to read 5, iclass 22, count 0 2006.173.16:00:21.19#ibcon#read 5, iclass 22, count 0 2006.173.16:00:21.19#ibcon#about to read 6, iclass 22, count 0 2006.173.16:00:21.19#ibcon#read 6, iclass 22, count 0 2006.173.16:00:21.19#ibcon#end of sib2, iclass 22, count 0 2006.173.16:00:21.19#ibcon#*after write, iclass 22, count 0 2006.173.16:00:21.19#ibcon#*before return 0, iclass 22, count 0 2006.173.16:00:21.19#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.16:00:21.19#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.16:00:21.19#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.16:00:21.19#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.16:00:21.19$vck44/vb=8,4 2006.173.16:00:21.19#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.16:00:21.19#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.16:00:21.19#ibcon#ireg 11 cls_cnt 2 2006.173.16:00:21.19#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.16:00:21.25#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.16:00:21.25#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.16:00:21.25#ibcon#enter wrdev, iclass 24, count 2 2006.173.16:00:21.25#ibcon#first serial, iclass 24, count 2 2006.173.16:00:21.25#ibcon#enter sib2, iclass 24, count 2 2006.173.16:00:21.25#ibcon#flushed, iclass 24, count 2 2006.173.16:00:21.25#ibcon#about to write, iclass 24, count 2 2006.173.16:00:21.25#ibcon#wrote, iclass 24, count 2 2006.173.16:00:21.25#ibcon#about to read 3, iclass 24, count 2 2006.173.16:00:21.27#ibcon#read 3, iclass 24, count 2 2006.173.16:00:21.27#ibcon#about to read 4, iclass 24, count 2 2006.173.16:00:21.27#ibcon#read 4, iclass 24, count 2 2006.173.16:00:21.27#ibcon#about to read 5, iclass 24, count 2 2006.173.16:00:21.27#ibcon#read 5, iclass 24, count 2 2006.173.16:00:21.27#ibcon#about to read 6, iclass 24, count 2 2006.173.16:00:21.27#ibcon#read 6, iclass 24, count 2 2006.173.16:00:21.27#ibcon#end of sib2, iclass 24, count 2 2006.173.16:00:21.27#ibcon#*mode == 0, iclass 24, count 2 2006.173.16:00:21.27#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.16:00:21.27#ibcon#[27=AT08-04\r\n] 2006.173.16:00:21.27#ibcon#*before write, iclass 24, count 2 2006.173.16:00:21.27#ibcon#enter sib2, iclass 24, count 2 2006.173.16:00:21.27#ibcon#flushed, iclass 24, count 2 2006.173.16:00:21.27#ibcon#about to write, iclass 24, count 2 2006.173.16:00:21.27#ibcon#wrote, iclass 24, count 2 2006.173.16:00:21.27#ibcon#about to read 3, iclass 24, count 2 2006.173.16:00:21.30#ibcon#read 3, iclass 24, count 2 2006.173.16:00:21.30#ibcon#about to read 4, iclass 24, count 2 2006.173.16:00:21.30#ibcon#read 4, iclass 24, count 2 2006.173.16:00:21.30#ibcon#about to read 5, iclass 24, count 2 2006.173.16:00:21.30#ibcon#read 5, iclass 24, count 2 2006.173.16:00:21.30#ibcon#about to read 6, iclass 24, count 2 2006.173.16:00:21.30#ibcon#read 6, iclass 24, count 2 2006.173.16:00:21.30#ibcon#end of sib2, iclass 24, count 2 2006.173.16:00:21.30#ibcon#*after write, iclass 24, count 2 2006.173.16:00:21.30#ibcon#*before return 0, iclass 24, count 2 2006.173.16:00:21.30#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.16:00:21.30#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.16:00:21.30#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.16:00:21.30#ibcon#ireg 7 cls_cnt 0 2006.173.16:00:21.30#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.16:00:21.42#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.16:00:21.42#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.16:00:21.42#ibcon#enter wrdev, iclass 24, count 0 2006.173.16:00:21.42#ibcon#first serial, iclass 24, count 0 2006.173.16:00:21.42#ibcon#enter sib2, iclass 24, count 0 2006.173.16:00:21.42#ibcon#flushed, iclass 24, count 0 2006.173.16:00:21.42#ibcon#about to write, iclass 24, count 0 2006.173.16:00:21.42#ibcon#wrote, iclass 24, count 0 2006.173.16:00:21.42#ibcon#about to read 3, iclass 24, count 0 2006.173.16:00:21.44#ibcon#read 3, iclass 24, count 0 2006.173.16:00:21.44#ibcon#about to read 4, iclass 24, count 0 2006.173.16:00:21.44#ibcon#read 4, iclass 24, count 0 2006.173.16:00:21.44#ibcon#about to read 5, iclass 24, count 0 2006.173.16:00:21.44#ibcon#read 5, iclass 24, count 0 2006.173.16:00:21.44#ibcon#about to read 6, iclass 24, count 0 2006.173.16:00:21.44#ibcon#read 6, iclass 24, count 0 2006.173.16:00:21.44#ibcon#end of sib2, iclass 24, count 0 2006.173.16:00:21.44#ibcon#*mode == 0, iclass 24, count 0 2006.173.16:00:21.44#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.16:00:21.44#ibcon#[27=USB\r\n] 2006.173.16:00:21.44#ibcon#*before write, iclass 24, count 0 2006.173.16:00:21.44#ibcon#enter sib2, iclass 24, count 0 2006.173.16:00:21.44#ibcon#flushed, iclass 24, count 0 2006.173.16:00:21.44#ibcon#about to write, iclass 24, count 0 2006.173.16:00:21.44#ibcon#wrote, iclass 24, count 0 2006.173.16:00:21.44#ibcon#about to read 3, iclass 24, count 0 2006.173.16:00:21.47#ibcon#read 3, iclass 24, count 0 2006.173.16:00:21.47#ibcon#about to read 4, iclass 24, count 0 2006.173.16:00:21.47#ibcon#read 4, iclass 24, count 0 2006.173.16:00:21.47#ibcon#about to read 5, iclass 24, count 0 2006.173.16:00:21.47#ibcon#read 5, iclass 24, count 0 2006.173.16:00:21.47#ibcon#about to read 6, iclass 24, count 0 2006.173.16:00:21.47#ibcon#read 6, iclass 24, count 0 2006.173.16:00:21.47#ibcon#end of sib2, iclass 24, count 0 2006.173.16:00:21.47#ibcon#*after write, iclass 24, count 0 2006.173.16:00:21.47#ibcon#*before return 0, iclass 24, count 0 2006.173.16:00:21.47#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.16:00:21.47#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.16:00:21.47#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.16:00:21.47#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.16:00:21.47$vck44/vabw=wide 2006.173.16:00:21.47#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.16:00:21.47#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.16:00:21.47#ibcon#ireg 8 cls_cnt 0 2006.173.16:00:21.47#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.16:00:21.47#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.16:00:21.47#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.16:00:21.47#ibcon#enter wrdev, iclass 26, count 0 2006.173.16:00:21.47#ibcon#first serial, iclass 26, count 0 2006.173.16:00:21.47#ibcon#enter sib2, iclass 26, count 0 2006.173.16:00:21.47#ibcon#flushed, iclass 26, count 0 2006.173.16:00:21.47#ibcon#about to write, iclass 26, count 0 2006.173.16:00:21.47#ibcon#wrote, iclass 26, count 0 2006.173.16:00:21.47#ibcon#about to read 3, iclass 26, count 0 2006.173.16:00:21.49#ibcon#read 3, iclass 26, count 0 2006.173.16:00:21.49#ibcon#about to read 4, iclass 26, count 0 2006.173.16:00:21.49#ibcon#read 4, iclass 26, count 0 2006.173.16:00:21.49#ibcon#about to read 5, iclass 26, count 0 2006.173.16:00:21.49#ibcon#read 5, iclass 26, count 0 2006.173.16:00:21.49#ibcon#about to read 6, iclass 26, count 0 2006.173.16:00:21.49#ibcon#read 6, iclass 26, count 0 2006.173.16:00:21.49#ibcon#end of sib2, iclass 26, count 0 2006.173.16:00:21.49#ibcon#*mode == 0, iclass 26, count 0 2006.173.16:00:21.49#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.16:00:21.49#ibcon#[25=BW32\r\n] 2006.173.16:00:21.49#ibcon#*before write, iclass 26, count 0 2006.173.16:00:21.49#ibcon#enter sib2, iclass 26, count 0 2006.173.16:00:21.49#ibcon#flushed, iclass 26, count 0 2006.173.16:00:21.49#ibcon#about to write, iclass 26, count 0 2006.173.16:00:21.49#ibcon#wrote, iclass 26, count 0 2006.173.16:00:21.49#ibcon#about to read 3, iclass 26, count 0 2006.173.16:00:21.52#ibcon#read 3, iclass 26, count 0 2006.173.16:00:21.52#ibcon#about to read 4, iclass 26, count 0 2006.173.16:00:21.52#ibcon#read 4, iclass 26, count 0 2006.173.16:00:21.52#ibcon#about to read 5, iclass 26, count 0 2006.173.16:00:21.52#ibcon#read 5, iclass 26, count 0 2006.173.16:00:21.52#ibcon#about to read 6, iclass 26, count 0 2006.173.16:00:21.52#ibcon#read 6, iclass 26, count 0 2006.173.16:00:21.52#ibcon#end of sib2, iclass 26, count 0 2006.173.16:00:21.52#ibcon#*after write, iclass 26, count 0 2006.173.16:00:21.52#ibcon#*before return 0, iclass 26, count 0 2006.173.16:00:21.52#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.16:00:21.52#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.16:00:21.52#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.16:00:21.52#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.16:00:21.52$vck44/vbbw=wide 2006.173.16:00:21.52#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.16:00:21.52#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.16:00:21.52#ibcon#ireg 8 cls_cnt 0 2006.173.16:00:21.52#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.16:00:21.59#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.16:00:21.59#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.16:00:21.59#ibcon#enter wrdev, iclass 28, count 0 2006.173.16:00:21.59#ibcon#first serial, iclass 28, count 0 2006.173.16:00:21.59#ibcon#enter sib2, iclass 28, count 0 2006.173.16:00:21.59#ibcon#flushed, iclass 28, count 0 2006.173.16:00:21.59#ibcon#about to write, iclass 28, count 0 2006.173.16:00:21.59#ibcon#wrote, iclass 28, count 0 2006.173.16:00:21.59#ibcon#about to read 3, iclass 28, count 0 2006.173.16:00:21.61#ibcon#read 3, iclass 28, count 0 2006.173.16:00:21.61#ibcon#about to read 4, iclass 28, count 0 2006.173.16:00:21.61#ibcon#read 4, iclass 28, count 0 2006.173.16:00:21.61#ibcon#about to read 5, iclass 28, count 0 2006.173.16:00:21.61#ibcon#read 5, iclass 28, count 0 2006.173.16:00:21.61#ibcon#about to read 6, iclass 28, count 0 2006.173.16:00:21.61#ibcon#read 6, iclass 28, count 0 2006.173.16:00:21.61#ibcon#end of sib2, iclass 28, count 0 2006.173.16:00:21.61#ibcon#*mode == 0, iclass 28, count 0 2006.173.16:00:21.61#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.16:00:21.61#ibcon#[27=BW32\r\n] 2006.173.16:00:21.61#ibcon#*before write, iclass 28, count 0 2006.173.16:00:21.61#ibcon#enter sib2, iclass 28, count 0 2006.173.16:00:21.61#ibcon#flushed, iclass 28, count 0 2006.173.16:00:21.61#ibcon#about to write, iclass 28, count 0 2006.173.16:00:21.61#ibcon#wrote, iclass 28, count 0 2006.173.16:00:21.61#ibcon#about to read 3, iclass 28, count 0 2006.173.16:00:21.64#ibcon#read 3, iclass 28, count 0 2006.173.16:00:21.64#ibcon#about to read 4, iclass 28, count 0 2006.173.16:00:21.64#ibcon#read 4, iclass 28, count 0 2006.173.16:00:21.64#ibcon#about to read 5, iclass 28, count 0 2006.173.16:00:21.64#ibcon#read 5, iclass 28, count 0 2006.173.16:00:21.64#ibcon#about to read 6, iclass 28, count 0 2006.173.16:00:21.64#ibcon#read 6, iclass 28, count 0 2006.173.16:00:21.64#ibcon#end of sib2, iclass 28, count 0 2006.173.16:00:21.64#ibcon#*after write, iclass 28, count 0 2006.173.16:00:21.64#ibcon#*before return 0, iclass 28, count 0 2006.173.16:00:21.64#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.16:00:21.64#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.16:00:21.64#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.16:00:21.64#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.16:00:21.64$setupk4/ifdk4 2006.173.16:00:21.64$ifdk4/lo= 2006.173.16:00:21.64$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.16:00:21.64$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.16:00:21.64$ifdk4/patch= 2006.173.16:00:21.64$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.16:00:21.64$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.16:00:21.64$setupk4/!*+20s 2006.173.16:00:25.45#abcon#<5=/14 0.7 1.6 20.711001003.0\r\n> 2006.173.16:00:25.47#abcon#{5=INTERFACE CLEAR} 2006.173.16:00:25.53#abcon#[5=S1D000X0/0*\r\n] 2006.173.16:00:35.62#abcon#<5=/14 0.7 1.6 20.711001003.0\r\n> 2006.173.16:00:35.64#abcon#{5=INTERFACE CLEAR} 2006.173.16:00:35.70#abcon#[5=S1D000X0/0*\r\n] 2006.173.16:00:36.14$setupk4/"tpicd 2006.173.16:00:36.14$setupk4/echo=off 2006.173.16:00:36.14$setupk4/xlog=off 2006.173.16:00:36.14:!2006.173.16:04:11 2006.173.16:02:02.14#trakl#Source acquired 2006.173.16:02:03.14#flagr#flagr/antenna,acquired 2006.173.16:04:11.02:preob 2006.173.16:04:12.15/onsource/TRACKING 2006.173.16:04:12.15:!2006.173.16:04:21 2006.173.16:04:21.02:"tape 2006.173.16:04:21.02:"st=record 2006.173.16:04:21.02:data_valid=on 2006.173.16:04:21.02:midob 2006.173.16:04:22.15/onsource/TRACKING 2006.173.16:04:22.15/wx/20.70,1003.0,100 2006.173.16:04:22.20/cable/+6.5093E-03 2006.173.16:04:23.29/va/01,07,usb,yes,35,38 2006.173.16:04:23.29/va/02,06,usb,yes,35,36 2006.173.16:04:23.29/va/03,05,usb,yes,44,46 2006.173.16:04:23.29/va/04,06,usb,yes,36,38 2006.173.16:04:23.29/va/05,04,usb,yes,28,28 2006.173.16:04:23.29/va/06,03,usb,yes,39,39 2006.173.16:04:23.29/va/07,04,usb,yes,32,33 2006.173.16:04:23.29/va/08,04,usb,yes,27,32 2006.173.16:04:23.52/valo/01,524.99,yes,locked 2006.173.16:04:23.52/valo/02,534.99,yes,locked 2006.173.16:04:23.52/valo/03,564.99,yes,locked 2006.173.16:04:23.52/valo/04,624.99,yes,locked 2006.173.16:04:23.52/valo/05,734.99,yes,locked 2006.173.16:04:23.52/valo/06,814.99,yes,locked 2006.173.16:04:23.52/valo/07,864.99,yes,locked 2006.173.16:04:23.52/valo/08,884.99,yes,locked 2006.173.16:04:24.61/vb/01,04,usb,yes,29,27 2006.173.16:04:24.61/vb/02,04,usb,yes,31,31 2006.173.16:04:24.61/vb/03,04,usb,yes,28,31 2006.173.16:04:24.61/vb/04,04,usb,yes,32,31 2006.173.16:04:24.61/vb/05,04,usb,yes,25,27 2006.173.16:04:24.61/vb/06,04,usb,yes,29,26 2006.173.16:04:24.61/vb/07,04,usb,yes,29,29 2006.173.16:04:24.61/vb/08,04,usb,yes,27,30 2006.173.16:04:24.84/vblo/01,629.99,yes,locked 2006.173.16:04:24.84/vblo/02,634.99,yes,locked 2006.173.16:04:24.84/vblo/03,649.99,yes,locked 2006.173.16:04:24.84/vblo/04,679.99,yes,locked 2006.173.16:04:24.84/vblo/05,709.99,yes,locked 2006.173.16:04:24.84/vblo/06,719.99,yes,locked 2006.173.16:04:24.84/vblo/07,734.99,yes,locked 2006.173.16:04:24.84/vblo/08,744.99,yes,locked 2006.173.16:04:24.99/vabw/8 2006.173.16:04:25.15/vbbw/8 2006.173.16:04:25.23/xfe/off,on,15.2 2006.173.16:04:25.60/ifatt/23,28,28,28 2006.173.16:04:26.07/fmout-gps/S +3.98E-07 2006.173.16:04:26.12:!2006.173.16:08:01 2006.173.16:08:01.01:data_valid=off 2006.173.16:08:01.01:"et 2006.173.16:08:01.02:!+3s 2006.173.16:08:04.04:"tape 2006.173.16:08:04.04:postob 2006.173.16:08:04.17/cable/+6.5092E-03 2006.173.16:08:04.17/wx/20.63,1002.9,100 2006.173.16:08:04.23/fmout-gps/S +3.94E-07 2006.173.16:08:04.23:scan_name=173-1618,jd0606,520 2006.173.16:08:04.23:source=1308+326,131028.66,322043.8,2000.0,ccw 2006.173.16:08:05.13#flagr#flagr/antenna,new-source 2006.173.16:08:05.14:checkk5 2006.173.16:08:05.55/chk_autoobs//k5ts1/ autoobs is running! 2006.173.16:08:05.94/chk_autoobs//k5ts2/ autoobs is running! 2006.173.16:08:06.35/chk_autoobs//k5ts3/ autoobs is running! 2006.173.16:08:06.75/chk_autoobs//k5ts4/ autoobs is running! 2006.173.16:08:07.14/chk_obsdata//k5ts1/T1731604??a.dat file size is correct (nominal:880MB, actual:876MB). 2006.173.16:08:07.55/chk_obsdata//k5ts2/T1731604??b.dat file size is correct (nominal:880MB, actual:876MB). 2006.173.16:08:07.94/chk_obsdata//k5ts3/T1731604??c.dat file size is correct (nominal:880MB, actual:876MB). 2006.173.16:08:08.32/chk_obsdata//k5ts4/T1731604??d.dat file size is correct (nominal:880MB, actual:876MB). 2006.173.16:08:09.08/k5log//k5ts1_log_newline 2006.173.16:08:09.79/k5log//k5ts2_log_newline 2006.173.16:08:10.50/k5log//k5ts3_log_newline 2006.173.16:08:11.22/k5log//k5ts4_log_newline 2006.173.16:08:11.24/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.16:08:11.24:setupk4=1 2006.173.16:08:11.24$setupk4/echo=on 2006.173.16:08:11.24$setupk4/pcalon 2006.173.16:08:11.24$pcalon/"no phase cal control is implemented here 2006.173.16:08:11.24$setupk4/"tpicd=stop 2006.173.16:08:11.24$setupk4/"rec=synch_on 2006.173.16:08:11.24$setupk4/"rec_mode=128 2006.173.16:08:11.24$setupk4/!* 2006.173.16:08:11.24$setupk4/recpk4 2006.173.16:08:11.24$recpk4/recpatch= 2006.173.16:08:11.24$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.16:08:11.24$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.16:08:11.25$setupk4/vck44 2006.173.16:08:11.25$vck44/valo=1,524.99 2006.173.16:08:11.25#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.16:08:11.25#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.16:08:11.25#ibcon#ireg 17 cls_cnt 0 2006.173.16:08:11.25#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.16:08:11.25#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.16:08:11.25#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.16:08:11.25#ibcon#enter wrdev, iclass 37, count 0 2006.173.16:08:11.25#ibcon#first serial, iclass 37, count 0 2006.173.16:08:11.25#ibcon#enter sib2, iclass 37, count 0 2006.173.16:08:11.25#ibcon#flushed, iclass 37, count 0 2006.173.16:08:11.25#ibcon#about to write, iclass 37, count 0 2006.173.16:08:11.25#ibcon#wrote, iclass 37, count 0 2006.173.16:08:11.25#ibcon#about to read 3, iclass 37, count 0 2006.173.16:08:11.26#ibcon#read 3, iclass 37, count 0 2006.173.16:08:11.26#ibcon#about to read 4, iclass 37, count 0 2006.173.16:08:11.26#ibcon#read 4, iclass 37, count 0 2006.173.16:08:11.26#ibcon#about to read 5, iclass 37, count 0 2006.173.16:08:11.26#ibcon#read 5, iclass 37, count 0 2006.173.16:08:11.26#ibcon#about to read 6, iclass 37, count 0 2006.173.16:08:11.26#ibcon#read 6, iclass 37, count 0 2006.173.16:08:11.26#ibcon#end of sib2, iclass 37, count 0 2006.173.16:08:11.26#ibcon#*mode == 0, iclass 37, count 0 2006.173.16:08:11.26#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.16:08:11.26#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.16:08:11.26#ibcon#*before write, iclass 37, count 0 2006.173.16:08:11.26#ibcon#enter sib2, iclass 37, count 0 2006.173.16:08:11.26#ibcon#flushed, iclass 37, count 0 2006.173.16:08:11.26#ibcon#about to write, iclass 37, count 0 2006.173.16:08:11.26#ibcon#wrote, iclass 37, count 0 2006.173.16:08:11.26#ibcon#about to read 3, iclass 37, count 0 2006.173.16:08:11.31#ibcon#read 3, iclass 37, count 0 2006.173.16:08:11.31#ibcon#about to read 4, iclass 37, count 0 2006.173.16:08:11.31#ibcon#read 4, iclass 37, count 0 2006.173.16:08:11.31#ibcon#about to read 5, iclass 37, count 0 2006.173.16:08:11.31#ibcon#read 5, iclass 37, count 0 2006.173.16:08:11.31#ibcon#about to read 6, iclass 37, count 0 2006.173.16:08:11.31#ibcon#read 6, iclass 37, count 0 2006.173.16:08:11.31#ibcon#end of sib2, iclass 37, count 0 2006.173.16:08:11.31#ibcon#*after write, iclass 37, count 0 2006.173.16:08:11.31#ibcon#*before return 0, iclass 37, count 0 2006.173.16:08:11.31#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.16:08:11.31#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.16:08:11.31#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.16:08:11.31#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.16:08:11.31$vck44/va=1,7 2006.173.16:08:11.31#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.16:08:11.31#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.16:08:11.31#ibcon#ireg 11 cls_cnt 2 2006.173.16:08:11.31#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.16:08:11.31#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.16:08:11.31#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.16:08:11.31#ibcon#enter wrdev, iclass 39, count 2 2006.173.16:08:11.31#ibcon#first serial, iclass 39, count 2 2006.173.16:08:11.31#ibcon#enter sib2, iclass 39, count 2 2006.173.16:08:11.31#ibcon#flushed, iclass 39, count 2 2006.173.16:08:11.31#ibcon#about to write, iclass 39, count 2 2006.173.16:08:11.31#ibcon#wrote, iclass 39, count 2 2006.173.16:08:11.31#ibcon#about to read 3, iclass 39, count 2 2006.173.16:08:11.33#ibcon#read 3, iclass 39, count 2 2006.173.16:08:11.33#ibcon#about to read 4, iclass 39, count 2 2006.173.16:08:11.33#ibcon#read 4, iclass 39, count 2 2006.173.16:08:11.33#ibcon#about to read 5, iclass 39, count 2 2006.173.16:08:11.33#ibcon#read 5, iclass 39, count 2 2006.173.16:08:11.33#ibcon#about to read 6, iclass 39, count 2 2006.173.16:08:11.33#ibcon#read 6, iclass 39, count 2 2006.173.16:08:11.33#ibcon#end of sib2, iclass 39, count 2 2006.173.16:08:11.33#ibcon#*mode == 0, iclass 39, count 2 2006.173.16:08:11.33#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.16:08:11.33#ibcon#[25=AT01-07\r\n] 2006.173.16:08:11.33#ibcon#*before write, iclass 39, count 2 2006.173.16:08:11.33#ibcon#enter sib2, iclass 39, count 2 2006.173.16:08:11.33#ibcon#flushed, iclass 39, count 2 2006.173.16:08:11.33#ibcon#about to write, iclass 39, count 2 2006.173.16:08:11.33#ibcon#wrote, iclass 39, count 2 2006.173.16:08:11.33#ibcon#about to read 3, iclass 39, count 2 2006.173.16:08:11.36#ibcon#read 3, iclass 39, count 2 2006.173.16:08:11.36#ibcon#about to read 4, iclass 39, count 2 2006.173.16:08:11.36#ibcon#read 4, iclass 39, count 2 2006.173.16:08:11.36#ibcon#about to read 5, iclass 39, count 2 2006.173.16:08:11.36#ibcon#read 5, iclass 39, count 2 2006.173.16:08:11.36#ibcon#about to read 6, iclass 39, count 2 2006.173.16:08:11.36#ibcon#read 6, iclass 39, count 2 2006.173.16:08:11.36#ibcon#end of sib2, iclass 39, count 2 2006.173.16:08:11.36#ibcon#*after write, iclass 39, count 2 2006.173.16:08:11.36#ibcon#*before return 0, iclass 39, count 2 2006.173.16:08:11.36#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.16:08:11.36#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.16:08:11.36#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.16:08:11.36#ibcon#ireg 7 cls_cnt 0 2006.173.16:08:11.36#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.16:08:11.48#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.16:08:11.48#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.16:08:11.48#ibcon#enter wrdev, iclass 39, count 0 2006.173.16:08:11.48#ibcon#first serial, iclass 39, count 0 2006.173.16:08:11.48#ibcon#enter sib2, iclass 39, count 0 2006.173.16:08:11.48#ibcon#flushed, iclass 39, count 0 2006.173.16:08:11.48#ibcon#about to write, iclass 39, count 0 2006.173.16:08:11.48#ibcon#wrote, iclass 39, count 0 2006.173.16:08:11.48#ibcon#about to read 3, iclass 39, count 0 2006.173.16:08:11.50#ibcon#read 3, iclass 39, count 0 2006.173.16:08:11.50#ibcon#about to read 4, iclass 39, count 0 2006.173.16:08:11.50#ibcon#read 4, iclass 39, count 0 2006.173.16:08:11.50#ibcon#about to read 5, iclass 39, count 0 2006.173.16:08:11.50#ibcon#read 5, iclass 39, count 0 2006.173.16:08:11.50#ibcon#about to read 6, iclass 39, count 0 2006.173.16:08:11.50#ibcon#read 6, iclass 39, count 0 2006.173.16:08:11.50#ibcon#end of sib2, iclass 39, count 0 2006.173.16:08:11.50#ibcon#*mode == 0, iclass 39, count 0 2006.173.16:08:11.50#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.16:08:11.50#ibcon#[25=USB\r\n] 2006.173.16:08:11.50#ibcon#*before write, iclass 39, count 0 2006.173.16:08:11.50#ibcon#enter sib2, iclass 39, count 0 2006.173.16:08:11.50#ibcon#flushed, iclass 39, count 0 2006.173.16:08:11.50#ibcon#about to write, iclass 39, count 0 2006.173.16:08:11.50#ibcon#wrote, iclass 39, count 0 2006.173.16:08:11.50#ibcon#about to read 3, iclass 39, count 0 2006.173.16:08:11.53#ibcon#read 3, iclass 39, count 0 2006.173.16:08:11.53#ibcon#about to read 4, iclass 39, count 0 2006.173.16:08:11.53#ibcon#read 4, iclass 39, count 0 2006.173.16:08:11.53#ibcon#about to read 5, iclass 39, count 0 2006.173.16:08:11.53#ibcon#read 5, iclass 39, count 0 2006.173.16:08:11.53#ibcon#about to read 6, iclass 39, count 0 2006.173.16:08:11.53#ibcon#read 6, iclass 39, count 0 2006.173.16:08:11.53#ibcon#end of sib2, iclass 39, count 0 2006.173.16:08:11.53#ibcon#*after write, iclass 39, count 0 2006.173.16:08:11.53#ibcon#*before return 0, iclass 39, count 0 2006.173.16:08:11.53#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.16:08:11.53#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.16:08:11.53#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.16:08:11.53#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.16:08:11.53$vck44/valo=2,534.99 2006.173.16:08:11.53#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.16:08:11.53#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.16:08:11.53#ibcon#ireg 17 cls_cnt 0 2006.173.16:08:11.53#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.16:08:11.53#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.16:08:11.53#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.16:08:11.53#ibcon#enter wrdev, iclass 3, count 0 2006.173.16:08:11.53#ibcon#first serial, iclass 3, count 0 2006.173.16:08:11.53#ibcon#enter sib2, iclass 3, count 0 2006.173.16:08:11.53#ibcon#flushed, iclass 3, count 0 2006.173.16:08:11.53#ibcon#about to write, iclass 3, count 0 2006.173.16:08:11.53#ibcon#wrote, iclass 3, count 0 2006.173.16:08:11.53#ibcon#about to read 3, iclass 3, count 0 2006.173.16:08:11.55#ibcon#read 3, iclass 3, count 0 2006.173.16:08:11.55#ibcon#about to read 4, iclass 3, count 0 2006.173.16:08:11.55#ibcon#read 4, iclass 3, count 0 2006.173.16:08:11.55#ibcon#about to read 5, iclass 3, count 0 2006.173.16:08:11.55#ibcon#read 5, iclass 3, count 0 2006.173.16:08:11.55#ibcon#about to read 6, iclass 3, count 0 2006.173.16:08:11.55#ibcon#read 6, iclass 3, count 0 2006.173.16:08:11.55#ibcon#end of sib2, iclass 3, count 0 2006.173.16:08:11.55#ibcon#*mode == 0, iclass 3, count 0 2006.173.16:08:11.55#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.16:08:11.55#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.16:08:11.55#ibcon#*before write, iclass 3, count 0 2006.173.16:08:11.55#ibcon#enter sib2, iclass 3, count 0 2006.173.16:08:11.55#ibcon#flushed, iclass 3, count 0 2006.173.16:08:11.55#ibcon#about to write, iclass 3, count 0 2006.173.16:08:11.55#ibcon#wrote, iclass 3, count 0 2006.173.16:08:11.55#ibcon#about to read 3, iclass 3, count 0 2006.173.16:08:11.59#ibcon#read 3, iclass 3, count 0 2006.173.16:08:11.59#ibcon#about to read 4, iclass 3, count 0 2006.173.16:08:11.59#ibcon#read 4, iclass 3, count 0 2006.173.16:08:11.59#ibcon#about to read 5, iclass 3, count 0 2006.173.16:08:11.59#ibcon#read 5, iclass 3, count 0 2006.173.16:08:11.59#ibcon#about to read 6, iclass 3, count 0 2006.173.16:08:11.59#ibcon#read 6, iclass 3, count 0 2006.173.16:08:11.59#ibcon#end of sib2, iclass 3, count 0 2006.173.16:08:11.59#ibcon#*after write, iclass 3, count 0 2006.173.16:08:11.59#ibcon#*before return 0, iclass 3, count 0 2006.173.16:08:11.59#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.16:08:11.59#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.16:08:11.59#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.16:08:11.59#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.16:08:11.59$vck44/va=2,6 2006.173.16:08:11.59#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.16:08:11.59#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.16:08:11.59#ibcon#ireg 11 cls_cnt 2 2006.173.16:08:11.59#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.16:08:11.65#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.16:08:11.65#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.16:08:11.65#ibcon#enter wrdev, iclass 5, count 2 2006.173.16:08:11.65#ibcon#first serial, iclass 5, count 2 2006.173.16:08:11.65#ibcon#enter sib2, iclass 5, count 2 2006.173.16:08:11.65#ibcon#flushed, iclass 5, count 2 2006.173.16:08:11.65#ibcon#about to write, iclass 5, count 2 2006.173.16:08:11.65#ibcon#wrote, iclass 5, count 2 2006.173.16:08:11.65#ibcon#about to read 3, iclass 5, count 2 2006.173.16:08:11.67#ibcon#read 3, iclass 5, count 2 2006.173.16:08:11.67#ibcon#about to read 4, iclass 5, count 2 2006.173.16:08:11.67#ibcon#read 4, iclass 5, count 2 2006.173.16:08:11.67#ibcon#about to read 5, iclass 5, count 2 2006.173.16:08:11.67#ibcon#read 5, iclass 5, count 2 2006.173.16:08:11.67#ibcon#about to read 6, iclass 5, count 2 2006.173.16:08:11.67#ibcon#read 6, iclass 5, count 2 2006.173.16:08:11.67#ibcon#end of sib2, iclass 5, count 2 2006.173.16:08:11.67#ibcon#*mode == 0, iclass 5, count 2 2006.173.16:08:11.67#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.16:08:11.67#ibcon#[25=AT02-06\r\n] 2006.173.16:08:11.67#ibcon#*before write, iclass 5, count 2 2006.173.16:08:11.67#ibcon#enter sib2, iclass 5, count 2 2006.173.16:08:11.67#ibcon#flushed, iclass 5, count 2 2006.173.16:08:11.67#ibcon#about to write, iclass 5, count 2 2006.173.16:08:11.67#ibcon#wrote, iclass 5, count 2 2006.173.16:08:11.67#ibcon#about to read 3, iclass 5, count 2 2006.173.16:08:11.70#ibcon#read 3, iclass 5, count 2 2006.173.16:08:11.70#ibcon#about to read 4, iclass 5, count 2 2006.173.16:08:11.70#ibcon#read 4, iclass 5, count 2 2006.173.16:08:11.70#ibcon#about to read 5, iclass 5, count 2 2006.173.16:08:11.70#ibcon#read 5, iclass 5, count 2 2006.173.16:08:11.70#ibcon#about to read 6, iclass 5, count 2 2006.173.16:08:11.70#ibcon#read 6, iclass 5, count 2 2006.173.16:08:11.70#ibcon#end of sib2, iclass 5, count 2 2006.173.16:08:11.70#ibcon#*after write, iclass 5, count 2 2006.173.16:08:11.70#ibcon#*before return 0, iclass 5, count 2 2006.173.16:08:11.70#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.16:08:11.70#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.16:08:11.70#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.16:08:11.70#ibcon#ireg 7 cls_cnt 0 2006.173.16:08:11.70#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.16:08:11.82#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.16:08:11.82#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.16:08:11.82#ibcon#enter wrdev, iclass 5, count 0 2006.173.16:08:11.82#ibcon#first serial, iclass 5, count 0 2006.173.16:08:11.82#ibcon#enter sib2, iclass 5, count 0 2006.173.16:08:11.82#ibcon#flushed, iclass 5, count 0 2006.173.16:08:11.82#ibcon#about to write, iclass 5, count 0 2006.173.16:08:11.82#ibcon#wrote, iclass 5, count 0 2006.173.16:08:11.82#ibcon#about to read 3, iclass 5, count 0 2006.173.16:08:11.84#ibcon#read 3, iclass 5, count 0 2006.173.16:08:11.84#ibcon#about to read 4, iclass 5, count 0 2006.173.16:08:11.84#ibcon#read 4, iclass 5, count 0 2006.173.16:08:11.84#ibcon#about to read 5, iclass 5, count 0 2006.173.16:08:11.84#ibcon#read 5, iclass 5, count 0 2006.173.16:08:11.84#ibcon#about to read 6, iclass 5, count 0 2006.173.16:08:11.84#ibcon#read 6, iclass 5, count 0 2006.173.16:08:11.84#ibcon#end of sib2, iclass 5, count 0 2006.173.16:08:11.84#ibcon#*mode == 0, iclass 5, count 0 2006.173.16:08:11.84#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.16:08:11.84#ibcon#[25=USB\r\n] 2006.173.16:08:11.84#ibcon#*before write, iclass 5, count 0 2006.173.16:08:11.84#ibcon#enter sib2, iclass 5, count 0 2006.173.16:08:11.84#ibcon#flushed, iclass 5, count 0 2006.173.16:08:11.84#ibcon#about to write, iclass 5, count 0 2006.173.16:08:11.84#ibcon#wrote, iclass 5, count 0 2006.173.16:08:11.84#ibcon#about to read 3, iclass 5, count 0 2006.173.16:08:11.87#ibcon#read 3, iclass 5, count 0 2006.173.16:08:11.87#ibcon#about to read 4, iclass 5, count 0 2006.173.16:08:11.87#ibcon#read 4, iclass 5, count 0 2006.173.16:08:11.87#ibcon#about to read 5, iclass 5, count 0 2006.173.16:08:11.87#ibcon#read 5, iclass 5, count 0 2006.173.16:08:11.87#ibcon#about to read 6, iclass 5, count 0 2006.173.16:08:11.87#ibcon#read 6, iclass 5, count 0 2006.173.16:08:11.87#ibcon#end of sib2, iclass 5, count 0 2006.173.16:08:11.87#ibcon#*after write, iclass 5, count 0 2006.173.16:08:11.87#ibcon#*before return 0, iclass 5, count 0 2006.173.16:08:11.87#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.16:08:11.87#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.16:08:11.87#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.16:08:11.87#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.16:08:11.87$vck44/valo=3,564.99 2006.173.16:08:11.87#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.16:08:11.87#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.16:08:11.87#ibcon#ireg 17 cls_cnt 0 2006.173.16:08:11.87#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.16:08:11.87#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.16:08:11.87#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.16:08:11.87#ibcon#enter wrdev, iclass 7, count 0 2006.173.16:08:11.87#ibcon#first serial, iclass 7, count 0 2006.173.16:08:11.87#ibcon#enter sib2, iclass 7, count 0 2006.173.16:08:11.87#ibcon#flushed, iclass 7, count 0 2006.173.16:08:11.87#ibcon#about to write, iclass 7, count 0 2006.173.16:08:11.87#ibcon#wrote, iclass 7, count 0 2006.173.16:08:11.87#ibcon#about to read 3, iclass 7, count 0 2006.173.16:08:11.89#ibcon#read 3, iclass 7, count 0 2006.173.16:08:11.89#ibcon#about to read 4, iclass 7, count 0 2006.173.16:08:11.89#ibcon#read 4, iclass 7, count 0 2006.173.16:08:11.89#ibcon#about to read 5, iclass 7, count 0 2006.173.16:08:11.89#ibcon#read 5, iclass 7, count 0 2006.173.16:08:11.89#ibcon#about to read 6, iclass 7, count 0 2006.173.16:08:11.89#ibcon#read 6, iclass 7, count 0 2006.173.16:08:11.89#ibcon#end of sib2, iclass 7, count 0 2006.173.16:08:11.89#ibcon#*mode == 0, iclass 7, count 0 2006.173.16:08:11.89#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.16:08:11.89#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.16:08:11.89#ibcon#*before write, iclass 7, count 0 2006.173.16:08:11.89#ibcon#enter sib2, iclass 7, count 0 2006.173.16:08:11.89#ibcon#flushed, iclass 7, count 0 2006.173.16:08:11.89#ibcon#about to write, iclass 7, count 0 2006.173.16:08:11.89#ibcon#wrote, iclass 7, count 0 2006.173.16:08:11.89#ibcon#about to read 3, iclass 7, count 0 2006.173.16:08:11.93#ibcon#read 3, iclass 7, count 0 2006.173.16:08:11.93#ibcon#about to read 4, iclass 7, count 0 2006.173.16:08:11.93#ibcon#read 4, iclass 7, count 0 2006.173.16:08:11.93#ibcon#about to read 5, iclass 7, count 0 2006.173.16:08:11.93#ibcon#read 5, iclass 7, count 0 2006.173.16:08:11.93#ibcon#about to read 6, iclass 7, count 0 2006.173.16:08:11.93#ibcon#read 6, iclass 7, count 0 2006.173.16:08:11.93#ibcon#end of sib2, iclass 7, count 0 2006.173.16:08:11.93#ibcon#*after write, iclass 7, count 0 2006.173.16:08:11.93#ibcon#*before return 0, iclass 7, count 0 2006.173.16:08:11.93#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.16:08:11.93#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.16:08:11.93#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.16:08:11.93#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.16:08:11.93$vck44/va=3,5 2006.173.16:08:11.93#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.16:08:11.93#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.16:08:11.93#ibcon#ireg 11 cls_cnt 2 2006.173.16:08:11.93#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.16:08:11.99#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.16:08:11.99#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.16:08:11.99#ibcon#enter wrdev, iclass 11, count 2 2006.173.16:08:11.99#ibcon#first serial, iclass 11, count 2 2006.173.16:08:11.99#ibcon#enter sib2, iclass 11, count 2 2006.173.16:08:11.99#ibcon#flushed, iclass 11, count 2 2006.173.16:08:11.99#ibcon#about to write, iclass 11, count 2 2006.173.16:08:11.99#ibcon#wrote, iclass 11, count 2 2006.173.16:08:11.99#ibcon#about to read 3, iclass 11, count 2 2006.173.16:08:12.01#ibcon#read 3, iclass 11, count 2 2006.173.16:08:12.01#ibcon#about to read 4, iclass 11, count 2 2006.173.16:08:12.01#ibcon#read 4, iclass 11, count 2 2006.173.16:08:12.01#ibcon#about to read 5, iclass 11, count 2 2006.173.16:08:12.01#ibcon#read 5, iclass 11, count 2 2006.173.16:08:12.01#ibcon#about to read 6, iclass 11, count 2 2006.173.16:08:12.01#ibcon#read 6, iclass 11, count 2 2006.173.16:08:12.01#ibcon#end of sib2, iclass 11, count 2 2006.173.16:08:12.01#ibcon#*mode == 0, iclass 11, count 2 2006.173.16:08:12.01#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.16:08:12.01#ibcon#[25=AT03-05\r\n] 2006.173.16:08:12.01#ibcon#*before write, iclass 11, count 2 2006.173.16:08:12.01#ibcon#enter sib2, iclass 11, count 2 2006.173.16:08:12.01#ibcon#flushed, iclass 11, count 2 2006.173.16:08:12.01#ibcon#about to write, iclass 11, count 2 2006.173.16:08:12.01#ibcon#wrote, iclass 11, count 2 2006.173.16:08:12.01#ibcon#about to read 3, iclass 11, count 2 2006.173.16:08:12.04#ibcon#read 3, iclass 11, count 2 2006.173.16:08:12.04#ibcon#about to read 4, iclass 11, count 2 2006.173.16:08:12.04#ibcon#read 4, iclass 11, count 2 2006.173.16:08:12.04#ibcon#about to read 5, iclass 11, count 2 2006.173.16:08:12.04#ibcon#read 5, iclass 11, count 2 2006.173.16:08:12.04#ibcon#about to read 6, iclass 11, count 2 2006.173.16:08:12.04#ibcon#read 6, iclass 11, count 2 2006.173.16:08:12.04#ibcon#end of sib2, iclass 11, count 2 2006.173.16:08:12.04#ibcon#*after write, iclass 11, count 2 2006.173.16:08:12.04#ibcon#*before return 0, iclass 11, count 2 2006.173.16:08:12.04#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.16:08:12.04#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.16:08:12.04#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.16:08:12.04#ibcon#ireg 7 cls_cnt 0 2006.173.16:08:12.04#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.16:08:12.16#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.16:08:12.16#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.16:08:12.16#ibcon#enter wrdev, iclass 11, count 0 2006.173.16:08:12.16#ibcon#first serial, iclass 11, count 0 2006.173.16:08:12.16#ibcon#enter sib2, iclass 11, count 0 2006.173.16:08:12.16#ibcon#flushed, iclass 11, count 0 2006.173.16:08:12.16#ibcon#about to write, iclass 11, count 0 2006.173.16:08:12.16#ibcon#wrote, iclass 11, count 0 2006.173.16:08:12.16#ibcon#about to read 3, iclass 11, count 0 2006.173.16:08:12.18#ibcon#read 3, iclass 11, count 0 2006.173.16:08:12.18#ibcon#about to read 4, iclass 11, count 0 2006.173.16:08:12.18#ibcon#read 4, iclass 11, count 0 2006.173.16:08:12.18#ibcon#about to read 5, iclass 11, count 0 2006.173.16:08:12.18#ibcon#read 5, iclass 11, count 0 2006.173.16:08:12.18#ibcon#about to read 6, iclass 11, count 0 2006.173.16:08:12.18#ibcon#read 6, iclass 11, count 0 2006.173.16:08:12.18#ibcon#end of sib2, iclass 11, count 0 2006.173.16:08:12.18#ibcon#*mode == 0, iclass 11, count 0 2006.173.16:08:12.18#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.16:08:12.18#ibcon#[25=USB\r\n] 2006.173.16:08:12.18#ibcon#*before write, iclass 11, count 0 2006.173.16:08:12.18#ibcon#enter sib2, iclass 11, count 0 2006.173.16:08:12.18#ibcon#flushed, iclass 11, count 0 2006.173.16:08:12.18#ibcon#about to write, iclass 11, count 0 2006.173.16:08:12.18#ibcon#wrote, iclass 11, count 0 2006.173.16:08:12.18#ibcon#about to read 3, iclass 11, count 0 2006.173.16:08:12.21#ibcon#read 3, iclass 11, count 0 2006.173.16:08:12.21#ibcon#about to read 4, iclass 11, count 0 2006.173.16:08:12.21#ibcon#read 4, iclass 11, count 0 2006.173.16:08:12.21#ibcon#about to read 5, iclass 11, count 0 2006.173.16:08:12.21#ibcon#read 5, iclass 11, count 0 2006.173.16:08:12.21#ibcon#about to read 6, iclass 11, count 0 2006.173.16:08:12.21#ibcon#read 6, iclass 11, count 0 2006.173.16:08:12.21#ibcon#end of sib2, iclass 11, count 0 2006.173.16:08:12.21#ibcon#*after write, iclass 11, count 0 2006.173.16:08:12.21#ibcon#*before return 0, iclass 11, count 0 2006.173.16:08:12.21#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.16:08:12.21#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.16:08:12.21#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.16:08:12.21#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.16:08:12.21$vck44/valo=4,624.99 2006.173.16:08:12.21#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.16:08:12.21#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.16:08:12.21#ibcon#ireg 17 cls_cnt 0 2006.173.16:08:12.21#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.16:08:12.21#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.16:08:12.21#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.16:08:12.21#ibcon#enter wrdev, iclass 13, count 0 2006.173.16:08:12.21#ibcon#first serial, iclass 13, count 0 2006.173.16:08:12.21#ibcon#enter sib2, iclass 13, count 0 2006.173.16:08:12.21#ibcon#flushed, iclass 13, count 0 2006.173.16:08:12.21#ibcon#about to write, iclass 13, count 0 2006.173.16:08:12.21#ibcon#wrote, iclass 13, count 0 2006.173.16:08:12.21#ibcon#about to read 3, iclass 13, count 0 2006.173.16:08:12.23#ibcon#read 3, iclass 13, count 0 2006.173.16:08:12.23#ibcon#about to read 4, iclass 13, count 0 2006.173.16:08:12.23#ibcon#read 4, iclass 13, count 0 2006.173.16:08:12.23#ibcon#about to read 5, iclass 13, count 0 2006.173.16:08:12.23#ibcon#read 5, iclass 13, count 0 2006.173.16:08:12.23#ibcon#about to read 6, iclass 13, count 0 2006.173.16:08:12.23#ibcon#read 6, iclass 13, count 0 2006.173.16:08:12.23#ibcon#end of sib2, iclass 13, count 0 2006.173.16:08:12.23#ibcon#*mode == 0, iclass 13, count 0 2006.173.16:08:12.23#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.16:08:12.23#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.16:08:12.23#ibcon#*before write, iclass 13, count 0 2006.173.16:08:12.23#ibcon#enter sib2, iclass 13, count 0 2006.173.16:08:12.23#ibcon#flushed, iclass 13, count 0 2006.173.16:08:12.23#ibcon#about to write, iclass 13, count 0 2006.173.16:08:12.23#ibcon#wrote, iclass 13, count 0 2006.173.16:08:12.23#ibcon#about to read 3, iclass 13, count 0 2006.173.16:08:12.27#ibcon#read 3, iclass 13, count 0 2006.173.16:08:12.27#ibcon#about to read 4, iclass 13, count 0 2006.173.16:08:12.27#ibcon#read 4, iclass 13, count 0 2006.173.16:08:12.27#ibcon#about to read 5, iclass 13, count 0 2006.173.16:08:12.27#ibcon#read 5, iclass 13, count 0 2006.173.16:08:12.27#ibcon#about to read 6, iclass 13, count 0 2006.173.16:08:12.27#ibcon#read 6, iclass 13, count 0 2006.173.16:08:12.27#ibcon#end of sib2, iclass 13, count 0 2006.173.16:08:12.27#ibcon#*after write, iclass 13, count 0 2006.173.16:08:12.27#ibcon#*before return 0, iclass 13, count 0 2006.173.16:08:12.27#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.16:08:12.27#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.16:08:12.27#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.16:08:12.27#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.16:08:12.27$vck44/va=4,6 2006.173.16:08:12.27#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.16:08:12.27#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.16:08:12.27#ibcon#ireg 11 cls_cnt 2 2006.173.16:08:12.27#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.16:08:12.33#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.16:08:12.33#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.16:08:12.33#ibcon#enter wrdev, iclass 15, count 2 2006.173.16:08:12.33#ibcon#first serial, iclass 15, count 2 2006.173.16:08:12.33#ibcon#enter sib2, iclass 15, count 2 2006.173.16:08:12.33#ibcon#flushed, iclass 15, count 2 2006.173.16:08:12.33#ibcon#about to write, iclass 15, count 2 2006.173.16:08:12.33#ibcon#wrote, iclass 15, count 2 2006.173.16:08:12.33#ibcon#about to read 3, iclass 15, count 2 2006.173.16:08:12.35#ibcon#read 3, iclass 15, count 2 2006.173.16:08:12.35#ibcon#about to read 4, iclass 15, count 2 2006.173.16:08:12.35#ibcon#read 4, iclass 15, count 2 2006.173.16:08:12.35#ibcon#about to read 5, iclass 15, count 2 2006.173.16:08:12.35#ibcon#read 5, iclass 15, count 2 2006.173.16:08:12.35#ibcon#about to read 6, iclass 15, count 2 2006.173.16:08:12.35#ibcon#read 6, iclass 15, count 2 2006.173.16:08:12.35#ibcon#end of sib2, iclass 15, count 2 2006.173.16:08:12.35#ibcon#*mode == 0, iclass 15, count 2 2006.173.16:08:12.35#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.16:08:12.35#ibcon#[25=AT04-06\r\n] 2006.173.16:08:12.35#ibcon#*before write, iclass 15, count 2 2006.173.16:08:12.35#ibcon#enter sib2, iclass 15, count 2 2006.173.16:08:12.35#ibcon#flushed, iclass 15, count 2 2006.173.16:08:12.35#ibcon#about to write, iclass 15, count 2 2006.173.16:08:12.35#ibcon#wrote, iclass 15, count 2 2006.173.16:08:12.35#ibcon#about to read 3, iclass 15, count 2 2006.173.16:08:12.38#ibcon#read 3, iclass 15, count 2 2006.173.16:08:12.38#ibcon#about to read 4, iclass 15, count 2 2006.173.16:08:12.38#ibcon#read 4, iclass 15, count 2 2006.173.16:08:12.38#ibcon#about to read 5, iclass 15, count 2 2006.173.16:08:12.38#ibcon#read 5, iclass 15, count 2 2006.173.16:08:12.38#ibcon#about to read 6, iclass 15, count 2 2006.173.16:08:12.38#ibcon#read 6, iclass 15, count 2 2006.173.16:08:12.38#ibcon#end of sib2, iclass 15, count 2 2006.173.16:08:12.38#ibcon#*after write, iclass 15, count 2 2006.173.16:08:12.38#ibcon#*before return 0, iclass 15, count 2 2006.173.16:08:12.38#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.16:08:12.38#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.16:08:12.38#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.16:08:12.38#ibcon#ireg 7 cls_cnt 0 2006.173.16:08:12.38#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.16:08:12.50#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.16:08:12.50#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.16:08:12.50#ibcon#enter wrdev, iclass 15, count 0 2006.173.16:08:12.50#ibcon#first serial, iclass 15, count 0 2006.173.16:08:12.50#ibcon#enter sib2, iclass 15, count 0 2006.173.16:08:12.50#ibcon#flushed, iclass 15, count 0 2006.173.16:08:12.50#ibcon#about to write, iclass 15, count 0 2006.173.16:08:12.50#ibcon#wrote, iclass 15, count 0 2006.173.16:08:12.50#ibcon#about to read 3, iclass 15, count 0 2006.173.16:08:12.52#ibcon#read 3, iclass 15, count 0 2006.173.16:08:12.52#ibcon#about to read 4, iclass 15, count 0 2006.173.16:08:12.52#ibcon#read 4, iclass 15, count 0 2006.173.16:08:12.52#ibcon#about to read 5, iclass 15, count 0 2006.173.16:08:12.52#ibcon#read 5, iclass 15, count 0 2006.173.16:08:12.52#ibcon#about to read 6, iclass 15, count 0 2006.173.16:08:12.52#ibcon#read 6, iclass 15, count 0 2006.173.16:08:12.52#ibcon#end of sib2, iclass 15, count 0 2006.173.16:08:12.52#ibcon#*mode == 0, iclass 15, count 0 2006.173.16:08:12.52#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.16:08:12.52#ibcon#[25=USB\r\n] 2006.173.16:08:12.52#ibcon#*before write, iclass 15, count 0 2006.173.16:08:12.52#ibcon#enter sib2, iclass 15, count 0 2006.173.16:08:12.52#ibcon#flushed, iclass 15, count 0 2006.173.16:08:12.52#ibcon#about to write, iclass 15, count 0 2006.173.16:08:12.52#ibcon#wrote, iclass 15, count 0 2006.173.16:08:12.52#ibcon#about to read 3, iclass 15, count 0 2006.173.16:08:12.55#ibcon#read 3, iclass 15, count 0 2006.173.16:08:12.55#ibcon#about to read 4, iclass 15, count 0 2006.173.16:08:12.55#ibcon#read 4, iclass 15, count 0 2006.173.16:08:12.55#ibcon#about to read 5, iclass 15, count 0 2006.173.16:08:12.55#ibcon#read 5, iclass 15, count 0 2006.173.16:08:12.55#ibcon#about to read 6, iclass 15, count 0 2006.173.16:08:12.55#ibcon#read 6, iclass 15, count 0 2006.173.16:08:12.55#ibcon#end of sib2, iclass 15, count 0 2006.173.16:08:12.55#ibcon#*after write, iclass 15, count 0 2006.173.16:08:12.55#ibcon#*before return 0, iclass 15, count 0 2006.173.16:08:12.55#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.16:08:12.55#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.16:08:12.55#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.16:08:12.55#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.16:08:12.55$vck44/valo=5,734.99 2006.173.16:08:12.55#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.16:08:12.55#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.16:08:12.55#ibcon#ireg 17 cls_cnt 0 2006.173.16:08:12.55#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.16:08:12.55#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.16:08:12.55#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.16:08:12.55#ibcon#enter wrdev, iclass 17, count 0 2006.173.16:08:12.55#ibcon#first serial, iclass 17, count 0 2006.173.16:08:12.55#ibcon#enter sib2, iclass 17, count 0 2006.173.16:08:12.55#ibcon#flushed, iclass 17, count 0 2006.173.16:08:12.55#ibcon#about to write, iclass 17, count 0 2006.173.16:08:12.55#ibcon#wrote, iclass 17, count 0 2006.173.16:08:12.55#ibcon#about to read 3, iclass 17, count 0 2006.173.16:08:12.57#ibcon#read 3, iclass 17, count 0 2006.173.16:08:12.57#ibcon#about to read 4, iclass 17, count 0 2006.173.16:08:12.57#ibcon#read 4, iclass 17, count 0 2006.173.16:08:12.57#ibcon#about to read 5, iclass 17, count 0 2006.173.16:08:12.57#ibcon#read 5, iclass 17, count 0 2006.173.16:08:12.57#ibcon#about to read 6, iclass 17, count 0 2006.173.16:08:12.57#ibcon#read 6, iclass 17, count 0 2006.173.16:08:12.57#ibcon#end of sib2, iclass 17, count 0 2006.173.16:08:12.57#ibcon#*mode == 0, iclass 17, count 0 2006.173.16:08:12.57#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.16:08:12.57#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.16:08:12.57#ibcon#*before write, iclass 17, count 0 2006.173.16:08:12.57#ibcon#enter sib2, iclass 17, count 0 2006.173.16:08:12.57#ibcon#flushed, iclass 17, count 0 2006.173.16:08:12.57#ibcon#about to write, iclass 17, count 0 2006.173.16:08:12.57#ibcon#wrote, iclass 17, count 0 2006.173.16:08:12.57#ibcon#about to read 3, iclass 17, count 0 2006.173.16:08:12.61#ibcon#read 3, iclass 17, count 0 2006.173.16:08:12.61#ibcon#about to read 4, iclass 17, count 0 2006.173.16:08:12.61#ibcon#read 4, iclass 17, count 0 2006.173.16:08:12.61#ibcon#about to read 5, iclass 17, count 0 2006.173.16:08:12.61#ibcon#read 5, iclass 17, count 0 2006.173.16:08:12.61#ibcon#about to read 6, iclass 17, count 0 2006.173.16:08:12.61#ibcon#read 6, iclass 17, count 0 2006.173.16:08:12.61#ibcon#end of sib2, iclass 17, count 0 2006.173.16:08:12.61#ibcon#*after write, iclass 17, count 0 2006.173.16:08:12.61#ibcon#*before return 0, iclass 17, count 0 2006.173.16:08:12.61#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.16:08:12.61#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.16:08:12.61#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.16:08:12.61#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.16:08:12.61$vck44/va=5,4 2006.173.16:08:12.61#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.16:08:12.61#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.16:08:12.61#ibcon#ireg 11 cls_cnt 2 2006.173.16:08:12.61#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.16:08:12.67#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.16:08:12.67#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.16:08:12.67#ibcon#enter wrdev, iclass 19, count 2 2006.173.16:08:12.67#ibcon#first serial, iclass 19, count 2 2006.173.16:08:12.67#ibcon#enter sib2, iclass 19, count 2 2006.173.16:08:12.67#ibcon#flushed, iclass 19, count 2 2006.173.16:08:12.67#ibcon#about to write, iclass 19, count 2 2006.173.16:08:12.67#ibcon#wrote, iclass 19, count 2 2006.173.16:08:12.67#ibcon#about to read 3, iclass 19, count 2 2006.173.16:08:12.69#ibcon#read 3, iclass 19, count 2 2006.173.16:08:12.69#ibcon#about to read 4, iclass 19, count 2 2006.173.16:08:12.69#ibcon#read 4, iclass 19, count 2 2006.173.16:08:12.69#ibcon#about to read 5, iclass 19, count 2 2006.173.16:08:12.69#ibcon#read 5, iclass 19, count 2 2006.173.16:08:12.69#ibcon#about to read 6, iclass 19, count 2 2006.173.16:08:12.69#ibcon#read 6, iclass 19, count 2 2006.173.16:08:12.69#ibcon#end of sib2, iclass 19, count 2 2006.173.16:08:12.69#ibcon#*mode == 0, iclass 19, count 2 2006.173.16:08:12.69#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.16:08:12.69#ibcon#[25=AT05-04\r\n] 2006.173.16:08:12.69#ibcon#*before write, iclass 19, count 2 2006.173.16:08:12.69#ibcon#enter sib2, iclass 19, count 2 2006.173.16:08:12.69#ibcon#flushed, iclass 19, count 2 2006.173.16:08:12.69#ibcon#about to write, iclass 19, count 2 2006.173.16:08:12.69#ibcon#wrote, iclass 19, count 2 2006.173.16:08:12.69#ibcon#about to read 3, iclass 19, count 2 2006.173.16:08:12.72#ibcon#read 3, iclass 19, count 2 2006.173.16:08:12.72#ibcon#about to read 4, iclass 19, count 2 2006.173.16:08:12.72#ibcon#read 4, iclass 19, count 2 2006.173.16:08:12.72#ibcon#about to read 5, iclass 19, count 2 2006.173.16:08:12.72#ibcon#read 5, iclass 19, count 2 2006.173.16:08:12.72#ibcon#about to read 6, iclass 19, count 2 2006.173.16:08:12.72#ibcon#read 6, iclass 19, count 2 2006.173.16:08:12.72#ibcon#end of sib2, iclass 19, count 2 2006.173.16:08:12.72#ibcon#*after write, iclass 19, count 2 2006.173.16:08:12.72#ibcon#*before return 0, iclass 19, count 2 2006.173.16:08:12.72#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.16:08:12.72#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.16:08:12.72#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.16:08:12.72#ibcon#ireg 7 cls_cnt 0 2006.173.16:08:12.72#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.16:08:12.84#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.16:08:12.84#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.16:08:12.84#ibcon#enter wrdev, iclass 19, count 0 2006.173.16:08:12.84#ibcon#first serial, iclass 19, count 0 2006.173.16:08:12.84#ibcon#enter sib2, iclass 19, count 0 2006.173.16:08:12.84#ibcon#flushed, iclass 19, count 0 2006.173.16:08:12.84#ibcon#about to write, iclass 19, count 0 2006.173.16:08:12.84#ibcon#wrote, iclass 19, count 0 2006.173.16:08:12.84#ibcon#about to read 3, iclass 19, count 0 2006.173.16:08:12.86#ibcon#read 3, iclass 19, count 0 2006.173.16:08:12.86#ibcon#about to read 4, iclass 19, count 0 2006.173.16:08:12.86#ibcon#read 4, iclass 19, count 0 2006.173.16:08:12.86#ibcon#about to read 5, iclass 19, count 0 2006.173.16:08:12.86#ibcon#read 5, iclass 19, count 0 2006.173.16:08:12.86#ibcon#about to read 6, iclass 19, count 0 2006.173.16:08:12.86#ibcon#read 6, iclass 19, count 0 2006.173.16:08:12.86#ibcon#end of sib2, iclass 19, count 0 2006.173.16:08:12.86#ibcon#*mode == 0, iclass 19, count 0 2006.173.16:08:12.86#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.16:08:12.86#ibcon#[25=USB\r\n] 2006.173.16:08:12.86#ibcon#*before write, iclass 19, count 0 2006.173.16:08:12.86#ibcon#enter sib2, iclass 19, count 0 2006.173.16:08:12.86#ibcon#flushed, iclass 19, count 0 2006.173.16:08:12.86#ibcon#about to write, iclass 19, count 0 2006.173.16:08:12.86#ibcon#wrote, iclass 19, count 0 2006.173.16:08:12.86#ibcon#about to read 3, iclass 19, count 0 2006.173.16:08:12.89#ibcon#read 3, iclass 19, count 0 2006.173.16:08:12.89#ibcon#about to read 4, iclass 19, count 0 2006.173.16:08:12.89#ibcon#read 4, iclass 19, count 0 2006.173.16:08:12.89#ibcon#about to read 5, iclass 19, count 0 2006.173.16:08:12.89#ibcon#read 5, iclass 19, count 0 2006.173.16:08:12.89#ibcon#about to read 6, iclass 19, count 0 2006.173.16:08:12.89#ibcon#read 6, iclass 19, count 0 2006.173.16:08:12.89#ibcon#end of sib2, iclass 19, count 0 2006.173.16:08:12.89#ibcon#*after write, iclass 19, count 0 2006.173.16:08:12.89#ibcon#*before return 0, iclass 19, count 0 2006.173.16:08:12.89#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.16:08:12.89#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.16:08:12.89#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.16:08:12.89#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.16:08:12.89$vck44/valo=6,814.99 2006.173.16:08:12.89#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.16:08:12.89#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.16:08:12.89#ibcon#ireg 17 cls_cnt 0 2006.173.16:08:12.89#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.16:08:12.89#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.16:08:12.89#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.16:08:12.89#ibcon#enter wrdev, iclass 21, count 0 2006.173.16:08:12.89#ibcon#first serial, iclass 21, count 0 2006.173.16:08:12.89#ibcon#enter sib2, iclass 21, count 0 2006.173.16:08:12.89#ibcon#flushed, iclass 21, count 0 2006.173.16:08:12.89#ibcon#about to write, iclass 21, count 0 2006.173.16:08:12.89#ibcon#wrote, iclass 21, count 0 2006.173.16:08:12.89#ibcon#about to read 3, iclass 21, count 0 2006.173.16:08:12.91#ibcon#read 3, iclass 21, count 0 2006.173.16:08:12.91#ibcon#about to read 4, iclass 21, count 0 2006.173.16:08:12.91#ibcon#read 4, iclass 21, count 0 2006.173.16:08:12.91#ibcon#about to read 5, iclass 21, count 0 2006.173.16:08:12.91#ibcon#read 5, iclass 21, count 0 2006.173.16:08:12.91#ibcon#about to read 6, iclass 21, count 0 2006.173.16:08:12.91#ibcon#read 6, iclass 21, count 0 2006.173.16:08:12.91#ibcon#end of sib2, iclass 21, count 0 2006.173.16:08:12.91#ibcon#*mode == 0, iclass 21, count 0 2006.173.16:08:12.91#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.16:08:12.91#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.16:08:12.91#ibcon#*before write, iclass 21, count 0 2006.173.16:08:12.91#ibcon#enter sib2, iclass 21, count 0 2006.173.16:08:12.91#ibcon#flushed, iclass 21, count 0 2006.173.16:08:12.91#ibcon#about to write, iclass 21, count 0 2006.173.16:08:12.91#ibcon#wrote, iclass 21, count 0 2006.173.16:08:12.91#ibcon#about to read 3, iclass 21, count 0 2006.173.16:08:12.95#ibcon#read 3, iclass 21, count 0 2006.173.16:08:12.95#ibcon#about to read 4, iclass 21, count 0 2006.173.16:08:12.95#ibcon#read 4, iclass 21, count 0 2006.173.16:08:12.95#ibcon#about to read 5, iclass 21, count 0 2006.173.16:08:12.95#ibcon#read 5, iclass 21, count 0 2006.173.16:08:12.95#ibcon#about to read 6, iclass 21, count 0 2006.173.16:08:12.95#ibcon#read 6, iclass 21, count 0 2006.173.16:08:12.95#ibcon#end of sib2, iclass 21, count 0 2006.173.16:08:12.95#ibcon#*after write, iclass 21, count 0 2006.173.16:08:12.95#ibcon#*before return 0, iclass 21, count 0 2006.173.16:08:12.95#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.16:08:12.95#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.16:08:12.95#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.16:08:12.95#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.16:08:12.95$vck44/va=6,3 2006.173.16:08:12.95#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.16:08:12.95#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.16:08:12.95#ibcon#ireg 11 cls_cnt 2 2006.173.16:08:12.95#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.16:08:13.01#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.16:08:13.01#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.16:08:13.01#ibcon#enter wrdev, iclass 23, count 2 2006.173.16:08:13.01#ibcon#first serial, iclass 23, count 2 2006.173.16:08:13.01#ibcon#enter sib2, iclass 23, count 2 2006.173.16:08:13.01#ibcon#flushed, iclass 23, count 2 2006.173.16:08:13.01#ibcon#about to write, iclass 23, count 2 2006.173.16:08:13.01#ibcon#wrote, iclass 23, count 2 2006.173.16:08:13.01#ibcon#about to read 3, iclass 23, count 2 2006.173.16:08:13.03#ibcon#read 3, iclass 23, count 2 2006.173.16:08:13.03#ibcon#about to read 4, iclass 23, count 2 2006.173.16:08:13.03#ibcon#read 4, iclass 23, count 2 2006.173.16:08:13.03#ibcon#about to read 5, iclass 23, count 2 2006.173.16:08:13.03#ibcon#read 5, iclass 23, count 2 2006.173.16:08:13.03#ibcon#about to read 6, iclass 23, count 2 2006.173.16:08:13.03#ibcon#read 6, iclass 23, count 2 2006.173.16:08:13.03#ibcon#end of sib2, iclass 23, count 2 2006.173.16:08:13.03#ibcon#*mode == 0, iclass 23, count 2 2006.173.16:08:13.03#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.16:08:13.03#ibcon#[25=AT06-03\r\n] 2006.173.16:08:13.03#ibcon#*before write, iclass 23, count 2 2006.173.16:08:13.03#ibcon#enter sib2, iclass 23, count 2 2006.173.16:08:13.03#ibcon#flushed, iclass 23, count 2 2006.173.16:08:13.03#ibcon#about to write, iclass 23, count 2 2006.173.16:08:13.03#ibcon#wrote, iclass 23, count 2 2006.173.16:08:13.03#ibcon#about to read 3, iclass 23, count 2 2006.173.16:08:13.06#ibcon#read 3, iclass 23, count 2 2006.173.16:08:13.06#ibcon#about to read 4, iclass 23, count 2 2006.173.16:08:13.06#ibcon#read 4, iclass 23, count 2 2006.173.16:08:13.06#ibcon#about to read 5, iclass 23, count 2 2006.173.16:08:13.06#ibcon#read 5, iclass 23, count 2 2006.173.16:08:13.06#ibcon#about to read 6, iclass 23, count 2 2006.173.16:08:13.06#ibcon#read 6, iclass 23, count 2 2006.173.16:08:13.06#ibcon#end of sib2, iclass 23, count 2 2006.173.16:08:13.06#ibcon#*after write, iclass 23, count 2 2006.173.16:08:13.06#ibcon#*before return 0, iclass 23, count 2 2006.173.16:08:13.06#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.16:08:13.06#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.16:08:13.06#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.16:08:13.06#ibcon#ireg 7 cls_cnt 0 2006.173.16:08:13.06#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.16:08:13.18#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.16:08:13.18#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.16:08:13.18#ibcon#enter wrdev, iclass 23, count 0 2006.173.16:08:13.18#ibcon#first serial, iclass 23, count 0 2006.173.16:08:13.18#ibcon#enter sib2, iclass 23, count 0 2006.173.16:08:13.18#ibcon#flushed, iclass 23, count 0 2006.173.16:08:13.18#ibcon#about to write, iclass 23, count 0 2006.173.16:08:13.18#ibcon#wrote, iclass 23, count 0 2006.173.16:08:13.18#ibcon#about to read 3, iclass 23, count 0 2006.173.16:08:13.20#ibcon#read 3, iclass 23, count 0 2006.173.16:08:13.20#ibcon#about to read 4, iclass 23, count 0 2006.173.16:08:13.20#ibcon#read 4, iclass 23, count 0 2006.173.16:08:13.20#ibcon#about to read 5, iclass 23, count 0 2006.173.16:08:13.20#ibcon#read 5, iclass 23, count 0 2006.173.16:08:13.20#ibcon#about to read 6, iclass 23, count 0 2006.173.16:08:13.20#ibcon#read 6, iclass 23, count 0 2006.173.16:08:13.20#ibcon#end of sib2, iclass 23, count 0 2006.173.16:08:13.20#ibcon#*mode == 0, iclass 23, count 0 2006.173.16:08:13.20#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.16:08:13.20#ibcon#[25=USB\r\n] 2006.173.16:08:13.20#ibcon#*before write, iclass 23, count 0 2006.173.16:08:13.20#ibcon#enter sib2, iclass 23, count 0 2006.173.16:08:13.20#ibcon#flushed, iclass 23, count 0 2006.173.16:08:13.20#ibcon#about to write, iclass 23, count 0 2006.173.16:08:13.20#ibcon#wrote, iclass 23, count 0 2006.173.16:08:13.20#ibcon#about to read 3, iclass 23, count 0 2006.173.16:08:13.23#ibcon#read 3, iclass 23, count 0 2006.173.16:08:13.23#ibcon#about to read 4, iclass 23, count 0 2006.173.16:08:13.23#ibcon#read 4, iclass 23, count 0 2006.173.16:08:13.23#ibcon#about to read 5, iclass 23, count 0 2006.173.16:08:13.23#ibcon#read 5, iclass 23, count 0 2006.173.16:08:13.23#ibcon#about to read 6, iclass 23, count 0 2006.173.16:08:13.23#ibcon#read 6, iclass 23, count 0 2006.173.16:08:13.23#ibcon#end of sib2, iclass 23, count 0 2006.173.16:08:13.23#ibcon#*after write, iclass 23, count 0 2006.173.16:08:13.23#ibcon#*before return 0, iclass 23, count 0 2006.173.16:08:13.23#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.16:08:13.23#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.16:08:13.23#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.16:08:13.23#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.16:08:13.23$vck44/valo=7,864.99 2006.173.16:08:13.23#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.16:08:13.23#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.16:08:13.23#ibcon#ireg 17 cls_cnt 0 2006.173.16:08:13.23#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.16:08:13.23#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.16:08:13.23#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.16:08:13.23#ibcon#enter wrdev, iclass 25, count 0 2006.173.16:08:13.23#ibcon#first serial, iclass 25, count 0 2006.173.16:08:13.23#ibcon#enter sib2, iclass 25, count 0 2006.173.16:08:13.23#ibcon#flushed, iclass 25, count 0 2006.173.16:08:13.23#ibcon#about to write, iclass 25, count 0 2006.173.16:08:13.23#ibcon#wrote, iclass 25, count 0 2006.173.16:08:13.23#ibcon#about to read 3, iclass 25, count 0 2006.173.16:08:13.25#ibcon#read 3, iclass 25, count 0 2006.173.16:08:13.25#ibcon#about to read 4, iclass 25, count 0 2006.173.16:08:13.25#ibcon#read 4, iclass 25, count 0 2006.173.16:08:13.25#ibcon#about to read 5, iclass 25, count 0 2006.173.16:08:13.25#ibcon#read 5, iclass 25, count 0 2006.173.16:08:13.25#ibcon#about to read 6, iclass 25, count 0 2006.173.16:08:13.25#ibcon#read 6, iclass 25, count 0 2006.173.16:08:13.25#ibcon#end of sib2, iclass 25, count 0 2006.173.16:08:13.25#ibcon#*mode == 0, iclass 25, count 0 2006.173.16:08:13.25#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.16:08:13.25#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.16:08:13.25#ibcon#*before write, iclass 25, count 0 2006.173.16:08:13.25#ibcon#enter sib2, iclass 25, count 0 2006.173.16:08:13.25#ibcon#flushed, iclass 25, count 0 2006.173.16:08:13.25#ibcon#about to write, iclass 25, count 0 2006.173.16:08:13.25#ibcon#wrote, iclass 25, count 0 2006.173.16:08:13.25#ibcon#about to read 3, iclass 25, count 0 2006.173.16:08:13.29#ibcon#read 3, iclass 25, count 0 2006.173.16:08:13.29#ibcon#about to read 4, iclass 25, count 0 2006.173.16:08:13.29#ibcon#read 4, iclass 25, count 0 2006.173.16:08:13.29#ibcon#about to read 5, iclass 25, count 0 2006.173.16:08:13.29#ibcon#read 5, iclass 25, count 0 2006.173.16:08:13.29#ibcon#about to read 6, iclass 25, count 0 2006.173.16:08:13.29#ibcon#read 6, iclass 25, count 0 2006.173.16:08:13.29#ibcon#end of sib2, iclass 25, count 0 2006.173.16:08:13.29#ibcon#*after write, iclass 25, count 0 2006.173.16:08:13.29#ibcon#*before return 0, iclass 25, count 0 2006.173.16:08:13.29#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.16:08:13.29#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.16:08:13.29#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.16:08:13.29#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.16:08:13.29$vck44/va=7,4 2006.173.16:08:13.29#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.16:08:13.29#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.16:08:13.29#ibcon#ireg 11 cls_cnt 2 2006.173.16:08:13.29#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.16:08:13.35#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.16:08:13.35#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.16:08:13.35#ibcon#enter wrdev, iclass 27, count 2 2006.173.16:08:13.35#ibcon#first serial, iclass 27, count 2 2006.173.16:08:13.35#ibcon#enter sib2, iclass 27, count 2 2006.173.16:08:13.35#ibcon#flushed, iclass 27, count 2 2006.173.16:08:13.35#ibcon#about to write, iclass 27, count 2 2006.173.16:08:13.35#ibcon#wrote, iclass 27, count 2 2006.173.16:08:13.35#ibcon#about to read 3, iclass 27, count 2 2006.173.16:08:13.37#ibcon#read 3, iclass 27, count 2 2006.173.16:08:13.37#ibcon#about to read 4, iclass 27, count 2 2006.173.16:08:13.37#ibcon#read 4, iclass 27, count 2 2006.173.16:08:13.37#ibcon#about to read 5, iclass 27, count 2 2006.173.16:08:13.37#ibcon#read 5, iclass 27, count 2 2006.173.16:08:13.37#ibcon#about to read 6, iclass 27, count 2 2006.173.16:08:13.37#ibcon#read 6, iclass 27, count 2 2006.173.16:08:13.37#ibcon#end of sib2, iclass 27, count 2 2006.173.16:08:13.37#ibcon#*mode == 0, iclass 27, count 2 2006.173.16:08:13.37#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.16:08:13.37#ibcon#[25=AT07-04\r\n] 2006.173.16:08:13.37#ibcon#*before write, iclass 27, count 2 2006.173.16:08:13.37#ibcon#enter sib2, iclass 27, count 2 2006.173.16:08:13.37#ibcon#flushed, iclass 27, count 2 2006.173.16:08:13.37#ibcon#about to write, iclass 27, count 2 2006.173.16:08:13.37#ibcon#wrote, iclass 27, count 2 2006.173.16:08:13.37#ibcon#about to read 3, iclass 27, count 2 2006.173.16:08:13.40#abcon#<5=/14 1.4 2.9 20.631001002.9\r\n> 2006.173.16:08:13.40#ibcon#read 3, iclass 27, count 2 2006.173.16:08:13.40#ibcon#about to read 4, iclass 27, count 2 2006.173.16:08:13.40#ibcon#read 4, iclass 27, count 2 2006.173.16:08:13.40#ibcon#about to read 5, iclass 27, count 2 2006.173.16:08:13.40#ibcon#read 5, iclass 27, count 2 2006.173.16:08:13.40#ibcon#about to read 6, iclass 27, count 2 2006.173.16:08:13.40#ibcon#read 6, iclass 27, count 2 2006.173.16:08:13.40#ibcon#end of sib2, iclass 27, count 2 2006.173.16:08:13.40#ibcon#*after write, iclass 27, count 2 2006.173.16:08:13.40#ibcon#*before return 0, iclass 27, count 2 2006.173.16:08:13.40#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.16:08:13.40#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.16:08:13.40#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.16:08:13.40#ibcon#ireg 7 cls_cnt 0 2006.173.16:08:13.40#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.16:08:13.42#abcon#{5=INTERFACE CLEAR} 2006.173.16:08:13.48#abcon#[5=S1D000X0/0*\r\n] 2006.173.16:08:13.52#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.16:08:13.52#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.16:08:13.52#ibcon#enter wrdev, iclass 27, count 0 2006.173.16:08:13.52#ibcon#first serial, iclass 27, count 0 2006.173.16:08:13.52#ibcon#enter sib2, iclass 27, count 0 2006.173.16:08:13.52#ibcon#flushed, iclass 27, count 0 2006.173.16:08:13.52#ibcon#about to write, iclass 27, count 0 2006.173.16:08:13.52#ibcon#wrote, iclass 27, count 0 2006.173.16:08:13.52#ibcon#about to read 3, iclass 27, count 0 2006.173.16:08:13.54#ibcon#read 3, iclass 27, count 0 2006.173.16:08:13.54#ibcon#about to read 4, iclass 27, count 0 2006.173.16:08:13.54#ibcon#read 4, iclass 27, count 0 2006.173.16:08:13.54#ibcon#about to read 5, iclass 27, count 0 2006.173.16:08:13.54#ibcon#read 5, iclass 27, count 0 2006.173.16:08:13.54#ibcon#about to read 6, iclass 27, count 0 2006.173.16:08:13.54#ibcon#read 6, iclass 27, count 0 2006.173.16:08:13.54#ibcon#end of sib2, iclass 27, count 0 2006.173.16:08:13.54#ibcon#*mode == 0, iclass 27, count 0 2006.173.16:08:13.54#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.16:08:13.54#ibcon#[25=USB\r\n] 2006.173.16:08:13.54#ibcon#*before write, iclass 27, count 0 2006.173.16:08:13.54#ibcon#enter sib2, iclass 27, count 0 2006.173.16:08:13.54#ibcon#flushed, iclass 27, count 0 2006.173.16:08:13.54#ibcon#about to write, iclass 27, count 0 2006.173.16:08:13.54#ibcon#wrote, iclass 27, count 0 2006.173.16:08:13.54#ibcon#about to read 3, iclass 27, count 0 2006.173.16:08:13.57#ibcon#read 3, iclass 27, count 0 2006.173.16:08:13.57#ibcon#about to read 4, iclass 27, count 0 2006.173.16:08:13.57#ibcon#read 4, iclass 27, count 0 2006.173.16:08:13.57#ibcon#about to read 5, iclass 27, count 0 2006.173.16:08:13.57#ibcon#read 5, iclass 27, count 0 2006.173.16:08:13.57#ibcon#about to read 6, iclass 27, count 0 2006.173.16:08:13.57#ibcon#read 6, iclass 27, count 0 2006.173.16:08:13.57#ibcon#end of sib2, iclass 27, count 0 2006.173.16:08:13.57#ibcon#*after write, iclass 27, count 0 2006.173.16:08:13.57#ibcon#*before return 0, iclass 27, count 0 2006.173.16:08:13.57#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.16:08:13.57#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.16:08:13.57#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.16:08:13.57#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.16:08:13.57$vck44/valo=8,884.99 2006.173.16:08:13.57#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.16:08:13.57#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.16:08:13.57#ibcon#ireg 17 cls_cnt 0 2006.173.16:08:13.57#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.16:08:13.57#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.16:08:13.57#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.16:08:13.57#ibcon#enter wrdev, iclass 33, count 0 2006.173.16:08:13.57#ibcon#first serial, iclass 33, count 0 2006.173.16:08:13.57#ibcon#enter sib2, iclass 33, count 0 2006.173.16:08:13.57#ibcon#flushed, iclass 33, count 0 2006.173.16:08:13.57#ibcon#about to write, iclass 33, count 0 2006.173.16:08:13.57#ibcon#wrote, iclass 33, count 0 2006.173.16:08:13.57#ibcon#about to read 3, iclass 33, count 0 2006.173.16:08:13.59#ibcon#read 3, iclass 33, count 0 2006.173.16:08:13.59#ibcon#about to read 4, iclass 33, count 0 2006.173.16:08:13.59#ibcon#read 4, iclass 33, count 0 2006.173.16:08:13.59#ibcon#about to read 5, iclass 33, count 0 2006.173.16:08:13.59#ibcon#read 5, iclass 33, count 0 2006.173.16:08:13.59#ibcon#about to read 6, iclass 33, count 0 2006.173.16:08:13.59#ibcon#read 6, iclass 33, count 0 2006.173.16:08:13.59#ibcon#end of sib2, iclass 33, count 0 2006.173.16:08:13.59#ibcon#*mode == 0, iclass 33, count 0 2006.173.16:08:13.59#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.16:08:13.59#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.16:08:13.59#ibcon#*before write, iclass 33, count 0 2006.173.16:08:13.59#ibcon#enter sib2, iclass 33, count 0 2006.173.16:08:13.59#ibcon#flushed, iclass 33, count 0 2006.173.16:08:13.59#ibcon#about to write, iclass 33, count 0 2006.173.16:08:13.59#ibcon#wrote, iclass 33, count 0 2006.173.16:08:13.59#ibcon#about to read 3, iclass 33, count 0 2006.173.16:08:13.63#ibcon#read 3, iclass 33, count 0 2006.173.16:08:13.63#ibcon#about to read 4, iclass 33, count 0 2006.173.16:08:13.63#ibcon#read 4, iclass 33, count 0 2006.173.16:08:13.63#ibcon#about to read 5, iclass 33, count 0 2006.173.16:08:13.63#ibcon#read 5, iclass 33, count 0 2006.173.16:08:13.63#ibcon#about to read 6, iclass 33, count 0 2006.173.16:08:13.63#ibcon#read 6, iclass 33, count 0 2006.173.16:08:13.63#ibcon#end of sib2, iclass 33, count 0 2006.173.16:08:13.63#ibcon#*after write, iclass 33, count 0 2006.173.16:08:13.63#ibcon#*before return 0, iclass 33, count 0 2006.173.16:08:13.63#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.16:08:13.63#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.16:08:13.63#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.16:08:13.63#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.16:08:13.63$vck44/va=8,4 2006.173.16:08:13.63#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.16:08:13.63#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.16:08:13.63#ibcon#ireg 11 cls_cnt 2 2006.173.16:08:13.63#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.16:08:13.69#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.16:08:13.69#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.16:08:13.69#ibcon#enter wrdev, iclass 35, count 2 2006.173.16:08:13.69#ibcon#first serial, iclass 35, count 2 2006.173.16:08:13.69#ibcon#enter sib2, iclass 35, count 2 2006.173.16:08:13.69#ibcon#flushed, iclass 35, count 2 2006.173.16:08:13.69#ibcon#about to write, iclass 35, count 2 2006.173.16:08:13.69#ibcon#wrote, iclass 35, count 2 2006.173.16:08:13.69#ibcon#about to read 3, iclass 35, count 2 2006.173.16:08:13.71#ibcon#read 3, iclass 35, count 2 2006.173.16:08:13.71#ibcon#about to read 4, iclass 35, count 2 2006.173.16:08:13.71#ibcon#read 4, iclass 35, count 2 2006.173.16:08:13.71#ibcon#about to read 5, iclass 35, count 2 2006.173.16:08:13.71#ibcon#read 5, iclass 35, count 2 2006.173.16:08:13.71#ibcon#about to read 6, iclass 35, count 2 2006.173.16:08:13.71#ibcon#read 6, iclass 35, count 2 2006.173.16:08:13.71#ibcon#end of sib2, iclass 35, count 2 2006.173.16:08:13.71#ibcon#*mode == 0, iclass 35, count 2 2006.173.16:08:13.71#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.16:08:13.71#ibcon#[25=AT08-04\r\n] 2006.173.16:08:13.71#ibcon#*before write, iclass 35, count 2 2006.173.16:08:13.71#ibcon#enter sib2, iclass 35, count 2 2006.173.16:08:13.71#ibcon#flushed, iclass 35, count 2 2006.173.16:08:13.71#ibcon#about to write, iclass 35, count 2 2006.173.16:08:13.71#ibcon#wrote, iclass 35, count 2 2006.173.16:08:13.71#ibcon#about to read 3, iclass 35, count 2 2006.173.16:08:13.74#ibcon#read 3, iclass 35, count 2 2006.173.16:08:13.74#ibcon#about to read 4, iclass 35, count 2 2006.173.16:08:13.74#ibcon#read 4, iclass 35, count 2 2006.173.16:08:13.74#ibcon#about to read 5, iclass 35, count 2 2006.173.16:08:13.74#ibcon#read 5, iclass 35, count 2 2006.173.16:08:13.74#ibcon#about to read 6, iclass 35, count 2 2006.173.16:08:13.74#ibcon#read 6, iclass 35, count 2 2006.173.16:08:13.74#ibcon#end of sib2, iclass 35, count 2 2006.173.16:08:13.74#ibcon#*after write, iclass 35, count 2 2006.173.16:08:13.74#ibcon#*before return 0, iclass 35, count 2 2006.173.16:08:13.74#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.16:08:13.74#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.16:08:13.74#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.16:08:13.74#ibcon#ireg 7 cls_cnt 0 2006.173.16:08:13.74#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.16:08:13.86#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.16:08:13.86#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.16:08:13.86#ibcon#enter wrdev, iclass 35, count 0 2006.173.16:08:13.86#ibcon#first serial, iclass 35, count 0 2006.173.16:08:13.86#ibcon#enter sib2, iclass 35, count 0 2006.173.16:08:13.86#ibcon#flushed, iclass 35, count 0 2006.173.16:08:13.86#ibcon#about to write, iclass 35, count 0 2006.173.16:08:13.86#ibcon#wrote, iclass 35, count 0 2006.173.16:08:13.86#ibcon#about to read 3, iclass 35, count 0 2006.173.16:08:13.88#ibcon#read 3, iclass 35, count 0 2006.173.16:08:13.88#ibcon#about to read 4, iclass 35, count 0 2006.173.16:08:13.88#ibcon#read 4, iclass 35, count 0 2006.173.16:08:13.88#ibcon#about to read 5, iclass 35, count 0 2006.173.16:08:13.88#ibcon#read 5, iclass 35, count 0 2006.173.16:08:13.88#ibcon#about to read 6, iclass 35, count 0 2006.173.16:08:13.88#ibcon#read 6, iclass 35, count 0 2006.173.16:08:13.88#ibcon#end of sib2, iclass 35, count 0 2006.173.16:08:13.88#ibcon#*mode == 0, iclass 35, count 0 2006.173.16:08:13.88#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.16:08:13.88#ibcon#[25=USB\r\n] 2006.173.16:08:13.88#ibcon#*before write, iclass 35, count 0 2006.173.16:08:13.88#ibcon#enter sib2, iclass 35, count 0 2006.173.16:08:13.88#ibcon#flushed, iclass 35, count 0 2006.173.16:08:13.88#ibcon#about to write, iclass 35, count 0 2006.173.16:08:13.88#ibcon#wrote, iclass 35, count 0 2006.173.16:08:13.88#ibcon#about to read 3, iclass 35, count 0 2006.173.16:08:13.91#ibcon#read 3, iclass 35, count 0 2006.173.16:08:13.91#ibcon#about to read 4, iclass 35, count 0 2006.173.16:08:13.91#ibcon#read 4, iclass 35, count 0 2006.173.16:08:13.91#ibcon#about to read 5, iclass 35, count 0 2006.173.16:08:13.91#ibcon#read 5, iclass 35, count 0 2006.173.16:08:13.91#ibcon#about to read 6, iclass 35, count 0 2006.173.16:08:13.91#ibcon#read 6, iclass 35, count 0 2006.173.16:08:13.91#ibcon#end of sib2, iclass 35, count 0 2006.173.16:08:13.91#ibcon#*after write, iclass 35, count 0 2006.173.16:08:13.91#ibcon#*before return 0, iclass 35, count 0 2006.173.16:08:13.91#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.16:08:13.91#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.16:08:13.91#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.16:08:13.91#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.16:08:13.91$vck44/vblo=1,629.99 2006.173.16:08:13.91#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.16:08:13.91#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.16:08:13.91#ibcon#ireg 17 cls_cnt 0 2006.173.16:08:13.91#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.16:08:13.91#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.16:08:13.91#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.16:08:13.91#ibcon#enter wrdev, iclass 37, count 0 2006.173.16:08:13.91#ibcon#first serial, iclass 37, count 0 2006.173.16:08:13.91#ibcon#enter sib2, iclass 37, count 0 2006.173.16:08:13.91#ibcon#flushed, iclass 37, count 0 2006.173.16:08:13.91#ibcon#about to write, iclass 37, count 0 2006.173.16:08:13.91#ibcon#wrote, iclass 37, count 0 2006.173.16:08:13.91#ibcon#about to read 3, iclass 37, count 0 2006.173.16:08:13.93#ibcon#read 3, iclass 37, count 0 2006.173.16:08:13.93#ibcon#about to read 4, iclass 37, count 0 2006.173.16:08:13.93#ibcon#read 4, iclass 37, count 0 2006.173.16:08:13.93#ibcon#about to read 5, iclass 37, count 0 2006.173.16:08:13.93#ibcon#read 5, iclass 37, count 0 2006.173.16:08:13.93#ibcon#about to read 6, iclass 37, count 0 2006.173.16:08:13.93#ibcon#read 6, iclass 37, count 0 2006.173.16:08:13.93#ibcon#end of sib2, iclass 37, count 0 2006.173.16:08:13.93#ibcon#*mode == 0, iclass 37, count 0 2006.173.16:08:13.93#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.16:08:13.93#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.16:08:13.93#ibcon#*before write, iclass 37, count 0 2006.173.16:08:13.93#ibcon#enter sib2, iclass 37, count 0 2006.173.16:08:13.93#ibcon#flushed, iclass 37, count 0 2006.173.16:08:13.93#ibcon#about to write, iclass 37, count 0 2006.173.16:08:13.93#ibcon#wrote, iclass 37, count 0 2006.173.16:08:13.93#ibcon#about to read 3, iclass 37, count 0 2006.173.16:08:13.97#ibcon#read 3, iclass 37, count 0 2006.173.16:08:13.97#ibcon#about to read 4, iclass 37, count 0 2006.173.16:08:13.97#ibcon#read 4, iclass 37, count 0 2006.173.16:08:13.97#ibcon#about to read 5, iclass 37, count 0 2006.173.16:08:13.97#ibcon#read 5, iclass 37, count 0 2006.173.16:08:13.97#ibcon#about to read 6, iclass 37, count 0 2006.173.16:08:13.97#ibcon#read 6, iclass 37, count 0 2006.173.16:08:13.97#ibcon#end of sib2, iclass 37, count 0 2006.173.16:08:13.97#ibcon#*after write, iclass 37, count 0 2006.173.16:08:13.97#ibcon#*before return 0, iclass 37, count 0 2006.173.16:08:13.97#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.16:08:13.97#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.16:08:13.97#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.16:08:13.97#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.16:08:13.97$vck44/vb=1,4 2006.173.16:08:13.97#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.16:08:13.97#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.16:08:13.97#ibcon#ireg 11 cls_cnt 2 2006.173.16:08:13.97#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.16:08:13.97#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.16:08:13.97#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.16:08:13.97#ibcon#enter wrdev, iclass 39, count 2 2006.173.16:08:13.97#ibcon#first serial, iclass 39, count 2 2006.173.16:08:13.97#ibcon#enter sib2, iclass 39, count 2 2006.173.16:08:13.97#ibcon#flushed, iclass 39, count 2 2006.173.16:08:13.97#ibcon#about to write, iclass 39, count 2 2006.173.16:08:13.97#ibcon#wrote, iclass 39, count 2 2006.173.16:08:13.97#ibcon#about to read 3, iclass 39, count 2 2006.173.16:08:13.99#ibcon#read 3, iclass 39, count 2 2006.173.16:08:13.99#ibcon#about to read 4, iclass 39, count 2 2006.173.16:08:13.99#ibcon#read 4, iclass 39, count 2 2006.173.16:08:13.99#ibcon#about to read 5, iclass 39, count 2 2006.173.16:08:13.99#ibcon#read 5, iclass 39, count 2 2006.173.16:08:13.99#ibcon#about to read 6, iclass 39, count 2 2006.173.16:08:13.99#ibcon#read 6, iclass 39, count 2 2006.173.16:08:13.99#ibcon#end of sib2, iclass 39, count 2 2006.173.16:08:13.99#ibcon#*mode == 0, iclass 39, count 2 2006.173.16:08:13.99#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.16:08:13.99#ibcon#[27=AT01-04\r\n] 2006.173.16:08:13.99#ibcon#*before write, iclass 39, count 2 2006.173.16:08:13.99#ibcon#enter sib2, iclass 39, count 2 2006.173.16:08:13.99#ibcon#flushed, iclass 39, count 2 2006.173.16:08:13.99#ibcon#about to write, iclass 39, count 2 2006.173.16:08:13.99#ibcon#wrote, iclass 39, count 2 2006.173.16:08:13.99#ibcon#about to read 3, iclass 39, count 2 2006.173.16:08:14.02#ibcon#read 3, iclass 39, count 2 2006.173.16:08:14.02#ibcon#about to read 4, iclass 39, count 2 2006.173.16:08:14.02#ibcon#read 4, iclass 39, count 2 2006.173.16:08:14.02#ibcon#about to read 5, iclass 39, count 2 2006.173.16:08:14.02#ibcon#read 5, iclass 39, count 2 2006.173.16:08:14.02#ibcon#about to read 6, iclass 39, count 2 2006.173.16:08:14.02#ibcon#read 6, iclass 39, count 2 2006.173.16:08:14.02#ibcon#end of sib2, iclass 39, count 2 2006.173.16:08:14.02#ibcon#*after write, iclass 39, count 2 2006.173.16:08:14.02#ibcon#*before return 0, iclass 39, count 2 2006.173.16:08:14.02#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.16:08:14.02#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.16:08:14.02#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.16:08:14.02#ibcon#ireg 7 cls_cnt 0 2006.173.16:08:14.02#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.16:08:14.14#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.16:08:14.14#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.16:08:14.14#ibcon#enter wrdev, iclass 39, count 0 2006.173.16:08:14.14#ibcon#first serial, iclass 39, count 0 2006.173.16:08:14.14#ibcon#enter sib2, iclass 39, count 0 2006.173.16:08:14.14#ibcon#flushed, iclass 39, count 0 2006.173.16:08:14.14#ibcon#about to write, iclass 39, count 0 2006.173.16:08:14.14#ibcon#wrote, iclass 39, count 0 2006.173.16:08:14.14#ibcon#about to read 3, iclass 39, count 0 2006.173.16:08:14.16#ibcon#read 3, iclass 39, count 0 2006.173.16:08:14.16#ibcon#about to read 4, iclass 39, count 0 2006.173.16:08:14.16#ibcon#read 4, iclass 39, count 0 2006.173.16:08:14.16#ibcon#about to read 5, iclass 39, count 0 2006.173.16:08:14.16#ibcon#read 5, iclass 39, count 0 2006.173.16:08:14.16#ibcon#about to read 6, iclass 39, count 0 2006.173.16:08:14.16#ibcon#read 6, iclass 39, count 0 2006.173.16:08:14.16#ibcon#end of sib2, iclass 39, count 0 2006.173.16:08:14.16#ibcon#*mode == 0, iclass 39, count 0 2006.173.16:08:14.16#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.16:08:14.16#ibcon#[27=USB\r\n] 2006.173.16:08:14.16#ibcon#*before write, iclass 39, count 0 2006.173.16:08:14.16#ibcon#enter sib2, iclass 39, count 0 2006.173.16:08:14.16#ibcon#flushed, iclass 39, count 0 2006.173.16:08:14.16#ibcon#about to write, iclass 39, count 0 2006.173.16:08:14.16#ibcon#wrote, iclass 39, count 0 2006.173.16:08:14.16#ibcon#about to read 3, iclass 39, count 0 2006.173.16:08:14.19#ibcon#read 3, iclass 39, count 0 2006.173.16:08:14.19#ibcon#about to read 4, iclass 39, count 0 2006.173.16:08:14.19#ibcon#read 4, iclass 39, count 0 2006.173.16:08:14.19#ibcon#about to read 5, iclass 39, count 0 2006.173.16:08:14.19#ibcon#read 5, iclass 39, count 0 2006.173.16:08:14.19#ibcon#about to read 6, iclass 39, count 0 2006.173.16:08:14.19#ibcon#read 6, iclass 39, count 0 2006.173.16:08:14.19#ibcon#end of sib2, iclass 39, count 0 2006.173.16:08:14.19#ibcon#*after write, iclass 39, count 0 2006.173.16:08:14.19#ibcon#*before return 0, iclass 39, count 0 2006.173.16:08:14.19#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.16:08:14.19#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.16:08:14.19#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.16:08:14.19#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.16:08:14.19$vck44/vblo=2,634.99 2006.173.16:08:14.19#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.16:08:14.19#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.16:08:14.19#ibcon#ireg 17 cls_cnt 0 2006.173.16:08:14.19#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.16:08:14.19#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.16:08:14.19#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.16:08:14.19#ibcon#enter wrdev, iclass 3, count 0 2006.173.16:08:14.19#ibcon#first serial, iclass 3, count 0 2006.173.16:08:14.19#ibcon#enter sib2, iclass 3, count 0 2006.173.16:08:14.19#ibcon#flushed, iclass 3, count 0 2006.173.16:08:14.19#ibcon#about to write, iclass 3, count 0 2006.173.16:08:14.19#ibcon#wrote, iclass 3, count 0 2006.173.16:08:14.19#ibcon#about to read 3, iclass 3, count 0 2006.173.16:08:14.21#ibcon#read 3, iclass 3, count 0 2006.173.16:08:14.21#ibcon#about to read 4, iclass 3, count 0 2006.173.16:08:14.21#ibcon#read 4, iclass 3, count 0 2006.173.16:08:14.21#ibcon#about to read 5, iclass 3, count 0 2006.173.16:08:14.21#ibcon#read 5, iclass 3, count 0 2006.173.16:08:14.21#ibcon#about to read 6, iclass 3, count 0 2006.173.16:08:14.21#ibcon#read 6, iclass 3, count 0 2006.173.16:08:14.21#ibcon#end of sib2, iclass 3, count 0 2006.173.16:08:14.21#ibcon#*mode == 0, iclass 3, count 0 2006.173.16:08:14.21#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.16:08:14.21#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.16:08:14.21#ibcon#*before write, iclass 3, count 0 2006.173.16:08:14.21#ibcon#enter sib2, iclass 3, count 0 2006.173.16:08:14.21#ibcon#flushed, iclass 3, count 0 2006.173.16:08:14.21#ibcon#about to write, iclass 3, count 0 2006.173.16:08:14.21#ibcon#wrote, iclass 3, count 0 2006.173.16:08:14.21#ibcon#about to read 3, iclass 3, count 0 2006.173.16:08:14.25#ibcon#read 3, iclass 3, count 0 2006.173.16:08:14.25#ibcon#about to read 4, iclass 3, count 0 2006.173.16:08:14.25#ibcon#read 4, iclass 3, count 0 2006.173.16:08:14.25#ibcon#about to read 5, iclass 3, count 0 2006.173.16:08:14.25#ibcon#read 5, iclass 3, count 0 2006.173.16:08:14.25#ibcon#about to read 6, iclass 3, count 0 2006.173.16:08:14.25#ibcon#read 6, iclass 3, count 0 2006.173.16:08:14.25#ibcon#end of sib2, iclass 3, count 0 2006.173.16:08:14.25#ibcon#*after write, iclass 3, count 0 2006.173.16:08:14.25#ibcon#*before return 0, iclass 3, count 0 2006.173.16:08:14.25#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.16:08:14.25#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.16:08:14.25#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.16:08:14.25#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.16:08:14.25$vck44/vb=2,4 2006.173.16:08:14.25#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.16:08:14.25#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.16:08:14.25#ibcon#ireg 11 cls_cnt 2 2006.173.16:08:14.25#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.16:08:14.31#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.16:08:14.31#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.16:08:14.31#ibcon#enter wrdev, iclass 5, count 2 2006.173.16:08:14.31#ibcon#first serial, iclass 5, count 2 2006.173.16:08:14.31#ibcon#enter sib2, iclass 5, count 2 2006.173.16:08:14.31#ibcon#flushed, iclass 5, count 2 2006.173.16:08:14.31#ibcon#about to write, iclass 5, count 2 2006.173.16:08:14.31#ibcon#wrote, iclass 5, count 2 2006.173.16:08:14.31#ibcon#about to read 3, iclass 5, count 2 2006.173.16:08:14.33#ibcon#read 3, iclass 5, count 2 2006.173.16:08:14.33#ibcon#about to read 4, iclass 5, count 2 2006.173.16:08:14.33#ibcon#read 4, iclass 5, count 2 2006.173.16:08:14.33#ibcon#about to read 5, iclass 5, count 2 2006.173.16:08:14.33#ibcon#read 5, iclass 5, count 2 2006.173.16:08:14.33#ibcon#about to read 6, iclass 5, count 2 2006.173.16:08:14.33#ibcon#read 6, iclass 5, count 2 2006.173.16:08:14.33#ibcon#end of sib2, iclass 5, count 2 2006.173.16:08:14.33#ibcon#*mode == 0, iclass 5, count 2 2006.173.16:08:14.33#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.16:08:14.33#ibcon#[27=AT02-04\r\n] 2006.173.16:08:14.33#ibcon#*before write, iclass 5, count 2 2006.173.16:08:14.33#ibcon#enter sib2, iclass 5, count 2 2006.173.16:08:14.33#ibcon#flushed, iclass 5, count 2 2006.173.16:08:14.33#ibcon#about to write, iclass 5, count 2 2006.173.16:08:14.33#ibcon#wrote, iclass 5, count 2 2006.173.16:08:14.33#ibcon#about to read 3, iclass 5, count 2 2006.173.16:08:14.36#ibcon#read 3, iclass 5, count 2 2006.173.16:08:14.36#ibcon#about to read 4, iclass 5, count 2 2006.173.16:08:14.36#ibcon#read 4, iclass 5, count 2 2006.173.16:08:14.36#ibcon#about to read 5, iclass 5, count 2 2006.173.16:08:14.36#ibcon#read 5, iclass 5, count 2 2006.173.16:08:14.36#ibcon#about to read 6, iclass 5, count 2 2006.173.16:08:14.36#ibcon#read 6, iclass 5, count 2 2006.173.16:08:14.36#ibcon#end of sib2, iclass 5, count 2 2006.173.16:08:14.36#ibcon#*after write, iclass 5, count 2 2006.173.16:08:14.36#ibcon#*before return 0, iclass 5, count 2 2006.173.16:08:14.36#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.16:08:14.36#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.16:08:14.36#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.16:08:14.36#ibcon#ireg 7 cls_cnt 0 2006.173.16:08:14.36#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.16:08:14.48#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.16:08:14.48#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.16:08:14.48#ibcon#enter wrdev, iclass 5, count 0 2006.173.16:08:14.48#ibcon#first serial, iclass 5, count 0 2006.173.16:08:14.48#ibcon#enter sib2, iclass 5, count 0 2006.173.16:08:14.48#ibcon#flushed, iclass 5, count 0 2006.173.16:08:14.48#ibcon#about to write, iclass 5, count 0 2006.173.16:08:14.48#ibcon#wrote, iclass 5, count 0 2006.173.16:08:14.48#ibcon#about to read 3, iclass 5, count 0 2006.173.16:08:14.50#ibcon#read 3, iclass 5, count 0 2006.173.16:08:14.50#ibcon#about to read 4, iclass 5, count 0 2006.173.16:08:14.50#ibcon#read 4, iclass 5, count 0 2006.173.16:08:14.50#ibcon#about to read 5, iclass 5, count 0 2006.173.16:08:14.50#ibcon#read 5, iclass 5, count 0 2006.173.16:08:14.50#ibcon#about to read 6, iclass 5, count 0 2006.173.16:08:14.50#ibcon#read 6, iclass 5, count 0 2006.173.16:08:14.50#ibcon#end of sib2, iclass 5, count 0 2006.173.16:08:14.50#ibcon#*mode == 0, iclass 5, count 0 2006.173.16:08:14.50#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.16:08:14.50#ibcon#[27=USB\r\n] 2006.173.16:08:14.50#ibcon#*before write, iclass 5, count 0 2006.173.16:08:14.50#ibcon#enter sib2, iclass 5, count 0 2006.173.16:08:14.50#ibcon#flushed, iclass 5, count 0 2006.173.16:08:14.50#ibcon#about to write, iclass 5, count 0 2006.173.16:08:14.50#ibcon#wrote, iclass 5, count 0 2006.173.16:08:14.50#ibcon#about to read 3, iclass 5, count 0 2006.173.16:08:14.53#ibcon#read 3, iclass 5, count 0 2006.173.16:08:14.53#ibcon#about to read 4, iclass 5, count 0 2006.173.16:08:14.53#ibcon#read 4, iclass 5, count 0 2006.173.16:08:14.53#ibcon#about to read 5, iclass 5, count 0 2006.173.16:08:14.53#ibcon#read 5, iclass 5, count 0 2006.173.16:08:14.53#ibcon#about to read 6, iclass 5, count 0 2006.173.16:08:14.53#ibcon#read 6, iclass 5, count 0 2006.173.16:08:14.53#ibcon#end of sib2, iclass 5, count 0 2006.173.16:08:14.53#ibcon#*after write, iclass 5, count 0 2006.173.16:08:14.53#ibcon#*before return 0, iclass 5, count 0 2006.173.16:08:14.53#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.16:08:14.53#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.16:08:14.53#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.16:08:14.53#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.16:08:14.53$vck44/vblo=3,649.99 2006.173.16:08:14.53#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.16:08:14.53#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.16:08:14.53#ibcon#ireg 17 cls_cnt 0 2006.173.16:08:14.53#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.16:08:14.53#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.16:08:14.53#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.16:08:14.53#ibcon#enter wrdev, iclass 7, count 0 2006.173.16:08:14.53#ibcon#first serial, iclass 7, count 0 2006.173.16:08:14.53#ibcon#enter sib2, iclass 7, count 0 2006.173.16:08:14.53#ibcon#flushed, iclass 7, count 0 2006.173.16:08:14.53#ibcon#about to write, iclass 7, count 0 2006.173.16:08:14.53#ibcon#wrote, iclass 7, count 0 2006.173.16:08:14.53#ibcon#about to read 3, iclass 7, count 0 2006.173.16:08:14.55#ibcon#read 3, iclass 7, count 0 2006.173.16:08:14.55#ibcon#about to read 4, iclass 7, count 0 2006.173.16:08:14.55#ibcon#read 4, iclass 7, count 0 2006.173.16:08:14.55#ibcon#about to read 5, iclass 7, count 0 2006.173.16:08:14.55#ibcon#read 5, iclass 7, count 0 2006.173.16:08:14.55#ibcon#about to read 6, iclass 7, count 0 2006.173.16:08:14.55#ibcon#read 6, iclass 7, count 0 2006.173.16:08:14.55#ibcon#end of sib2, iclass 7, count 0 2006.173.16:08:14.55#ibcon#*mode == 0, iclass 7, count 0 2006.173.16:08:14.55#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.16:08:14.55#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.16:08:14.55#ibcon#*before write, iclass 7, count 0 2006.173.16:08:14.55#ibcon#enter sib2, iclass 7, count 0 2006.173.16:08:14.55#ibcon#flushed, iclass 7, count 0 2006.173.16:08:14.55#ibcon#about to write, iclass 7, count 0 2006.173.16:08:14.55#ibcon#wrote, iclass 7, count 0 2006.173.16:08:14.55#ibcon#about to read 3, iclass 7, count 0 2006.173.16:08:14.59#ibcon#read 3, iclass 7, count 0 2006.173.16:08:14.59#ibcon#about to read 4, iclass 7, count 0 2006.173.16:08:14.59#ibcon#read 4, iclass 7, count 0 2006.173.16:08:14.59#ibcon#about to read 5, iclass 7, count 0 2006.173.16:08:14.59#ibcon#read 5, iclass 7, count 0 2006.173.16:08:14.59#ibcon#about to read 6, iclass 7, count 0 2006.173.16:08:14.59#ibcon#read 6, iclass 7, count 0 2006.173.16:08:14.59#ibcon#end of sib2, iclass 7, count 0 2006.173.16:08:14.59#ibcon#*after write, iclass 7, count 0 2006.173.16:08:14.59#ibcon#*before return 0, iclass 7, count 0 2006.173.16:08:14.59#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.16:08:14.59#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.16:08:14.59#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.16:08:14.66#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.16:08:14.66$vck44/vb=3,4 2006.173.16:08:14.66#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.16:08:14.66#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.16:08:14.66#ibcon#ireg 11 cls_cnt 2 2006.173.16:08:14.66#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.16:08:14.66#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.16:08:14.66#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.16:08:14.66#ibcon#enter wrdev, iclass 11, count 2 2006.173.16:08:14.66#ibcon#first serial, iclass 11, count 2 2006.173.16:08:14.66#ibcon#enter sib2, iclass 11, count 2 2006.173.16:08:14.66#ibcon#flushed, iclass 11, count 2 2006.173.16:08:14.66#ibcon#about to write, iclass 11, count 2 2006.173.16:08:14.66#ibcon#wrote, iclass 11, count 2 2006.173.16:08:14.66#ibcon#about to read 3, iclass 11, count 2 2006.173.16:08:14.67#ibcon#read 3, iclass 11, count 2 2006.173.16:08:14.67#ibcon#about to read 4, iclass 11, count 2 2006.173.16:08:14.67#ibcon#read 4, iclass 11, count 2 2006.173.16:08:14.67#ibcon#about to read 5, iclass 11, count 2 2006.173.16:08:14.67#ibcon#read 5, iclass 11, count 2 2006.173.16:08:14.67#ibcon#about to read 6, iclass 11, count 2 2006.173.16:08:14.67#ibcon#read 6, iclass 11, count 2 2006.173.16:08:14.67#ibcon#end of sib2, iclass 11, count 2 2006.173.16:08:14.67#ibcon#*mode == 0, iclass 11, count 2 2006.173.16:08:14.67#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.16:08:14.67#ibcon#[27=AT03-04\r\n] 2006.173.16:08:14.67#ibcon#*before write, iclass 11, count 2 2006.173.16:08:14.67#ibcon#enter sib2, iclass 11, count 2 2006.173.16:08:14.67#ibcon#flushed, iclass 11, count 2 2006.173.16:08:14.67#ibcon#about to write, iclass 11, count 2 2006.173.16:08:14.67#ibcon#wrote, iclass 11, count 2 2006.173.16:08:14.67#ibcon#about to read 3, iclass 11, count 2 2006.173.16:08:14.70#ibcon#read 3, iclass 11, count 2 2006.173.16:08:14.70#ibcon#about to read 4, iclass 11, count 2 2006.173.16:08:14.70#ibcon#read 4, iclass 11, count 2 2006.173.16:08:14.70#ibcon#about to read 5, iclass 11, count 2 2006.173.16:08:14.70#ibcon#read 5, iclass 11, count 2 2006.173.16:08:14.70#ibcon#about to read 6, iclass 11, count 2 2006.173.16:08:14.70#ibcon#read 6, iclass 11, count 2 2006.173.16:08:14.70#ibcon#end of sib2, iclass 11, count 2 2006.173.16:08:14.70#ibcon#*after write, iclass 11, count 2 2006.173.16:08:14.70#ibcon#*before return 0, iclass 11, count 2 2006.173.16:08:14.70#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.16:08:14.70#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.16:08:14.70#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.16:08:14.70#ibcon#ireg 7 cls_cnt 0 2006.173.16:08:14.70#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.16:08:14.82#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.16:08:14.82#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.16:08:14.82#ibcon#enter wrdev, iclass 11, count 0 2006.173.16:08:14.82#ibcon#first serial, iclass 11, count 0 2006.173.16:08:14.82#ibcon#enter sib2, iclass 11, count 0 2006.173.16:08:14.82#ibcon#flushed, iclass 11, count 0 2006.173.16:08:14.82#ibcon#about to write, iclass 11, count 0 2006.173.16:08:14.82#ibcon#wrote, iclass 11, count 0 2006.173.16:08:14.82#ibcon#about to read 3, iclass 11, count 0 2006.173.16:08:14.84#ibcon#read 3, iclass 11, count 0 2006.173.16:08:14.84#ibcon#about to read 4, iclass 11, count 0 2006.173.16:08:14.84#ibcon#read 4, iclass 11, count 0 2006.173.16:08:14.84#ibcon#about to read 5, iclass 11, count 0 2006.173.16:08:14.84#ibcon#read 5, iclass 11, count 0 2006.173.16:08:14.84#ibcon#about to read 6, iclass 11, count 0 2006.173.16:08:14.84#ibcon#read 6, iclass 11, count 0 2006.173.16:08:14.84#ibcon#end of sib2, iclass 11, count 0 2006.173.16:08:14.84#ibcon#*mode == 0, iclass 11, count 0 2006.173.16:08:14.84#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.16:08:14.84#ibcon#[27=USB\r\n] 2006.173.16:08:14.84#ibcon#*before write, iclass 11, count 0 2006.173.16:08:14.84#ibcon#enter sib2, iclass 11, count 0 2006.173.16:08:14.84#ibcon#flushed, iclass 11, count 0 2006.173.16:08:14.84#ibcon#about to write, iclass 11, count 0 2006.173.16:08:14.84#ibcon#wrote, iclass 11, count 0 2006.173.16:08:14.84#ibcon#about to read 3, iclass 11, count 0 2006.173.16:08:14.87#ibcon#read 3, iclass 11, count 0 2006.173.16:08:14.87#ibcon#about to read 4, iclass 11, count 0 2006.173.16:08:14.87#ibcon#read 4, iclass 11, count 0 2006.173.16:08:14.87#ibcon#about to read 5, iclass 11, count 0 2006.173.16:08:14.87#ibcon#read 5, iclass 11, count 0 2006.173.16:08:14.87#ibcon#about to read 6, iclass 11, count 0 2006.173.16:08:14.87#ibcon#read 6, iclass 11, count 0 2006.173.16:08:14.87#ibcon#end of sib2, iclass 11, count 0 2006.173.16:08:14.87#ibcon#*after write, iclass 11, count 0 2006.173.16:08:14.87#ibcon#*before return 0, iclass 11, count 0 2006.173.16:08:14.87#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.16:08:14.87#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.16:08:14.87#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.16:08:14.87#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.16:08:14.87$vck44/vblo=4,679.99 2006.173.16:08:14.87#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.16:08:14.87#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.16:08:14.87#ibcon#ireg 17 cls_cnt 0 2006.173.16:08:14.87#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.16:08:14.87#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.16:08:14.87#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.16:08:14.87#ibcon#enter wrdev, iclass 13, count 0 2006.173.16:08:14.87#ibcon#first serial, iclass 13, count 0 2006.173.16:08:14.87#ibcon#enter sib2, iclass 13, count 0 2006.173.16:08:14.87#ibcon#flushed, iclass 13, count 0 2006.173.16:08:14.87#ibcon#about to write, iclass 13, count 0 2006.173.16:08:14.87#ibcon#wrote, iclass 13, count 0 2006.173.16:08:14.87#ibcon#about to read 3, iclass 13, count 0 2006.173.16:08:14.89#ibcon#read 3, iclass 13, count 0 2006.173.16:08:14.89#ibcon#about to read 4, iclass 13, count 0 2006.173.16:08:14.89#ibcon#read 4, iclass 13, count 0 2006.173.16:08:14.89#ibcon#about to read 5, iclass 13, count 0 2006.173.16:08:14.89#ibcon#read 5, iclass 13, count 0 2006.173.16:08:14.89#ibcon#about to read 6, iclass 13, count 0 2006.173.16:08:14.89#ibcon#read 6, iclass 13, count 0 2006.173.16:08:14.89#ibcon#end of sib2, iclass 13, count 0 2006.173.16:08:14.89#ibcon#*mode == 0, iclass 13, count 0 2006.173.16:08:14.89#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.16:08:14.89#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.16:08:14.89#ibcon#*before write, iclass 13, count 0 2006.173.16:08:14.89#ibcon#enter sib2, iclass 13, count 0 2006.173.16:08:14.89#ibcon#flushed, iclass 13, count 0 2006.173.16:08:14.89#ibcon#about to write, iclass 13, count 0 2006.173.16:08:14.89#ibcon#wrote, iclass 13, count 0 2006.173.16:08:14.89#ibcon#about to read 3, iclass 13, count 0 2006.173.16:08:14.93#ibcon#read 3, iclass 13, count 0 2006.173.16:08:14.93#ibcon#about to read 4, iclass 13, count 0 2006.173.16:08:14.93#ibcon#read 4, iclass 13, count 0 2006.173.16:08:14.93#ibcon#about to read 5, iclass 13, count 0 2006.173.16:08:14.93#ibcon#read 5, iclass 13, count 0 2006.173.16:08:14.93#ibcon#about to read 6, iclass 13, count 0 2006.173.16:08:14.93#ibcon#read 6, iclass 13, count 0 2006.173.16:08:14.93#ibcon#end of sib2, iclass 13, count 0 2006.173.16:08:14.93#ibcon#*after write, iclass 13, count 0 2006.173.16:08:14.93#ibcon#*before return 0, iclass 13, count 0 2006.173.16:08:14.93#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.16:08:14.93#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.16:08:14.93#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.16:08:14.93#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.16:08:14.93$vck44/vb=4,4 2006.173.16:08:14.93#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.16:08:14.93#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.16:08:14.93#ibcon#ireg 11 cls_cnt 2 2006.173.16:08:14.93#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.16:08:14.99#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.16:08:14.99#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.16:08:14.99#ibcon#enter wrdev, iclass 15, count 2 2006.173.16:08:14.99#ibcon#first serial, iclass 15, count 2 2006.173.16:08:14.99#ibcon#enter sib2, iclass 15, count 2 2006.173.16:08:14.99#ibcon#flushed, iclass 15, count 2 2006.173.16:08:14.99#ibcon#about to write, iclass 15, count 2 2006.173.16:08:14.99#ibcon#wrote, iclass 15, count 2 2006.173.16:08:14.99#ibcon#about to read 3, iclass 15, count 2 2006.173.16:08:15.01#ibcon#read 3, iclass 15, count 2 2006.173.16:08:15.01#ibcon#about to read 4, iclass 15, count 2 2006.173.16:08:15.01#ibcon#read 4, iclass 15, count 2 2006.173.16:08:15.01#ibcon#about to read 5, iclass 15, count 2 2006.173.16:08:15.01#ibcon#read 5, iclass 15, count 2 2006.173.16:08:15.01#ibcon#about to read 6, iclass 15, count 2 2006.173.16:08:15.01#ibcon#read 6, iclass 15, count 2 2006.173.16:08:15.01#ibcon#end of sib2, iclass 15, count 2 2006.173.16:08:15.01#ibcon#*mode == 0, iclass 15, count 2 2006.173.16:08:15.01#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.16:08:15.01#ibcon#[27=AT04-04\r\n] 2006.173.16:08:15.01#ibcon#*before write, iclass 15, count 2 2006.173.16:08:15.01#ibcon#enter sib2, iclass 15, count 2 2006.173.16:08:15.01#ibcon#flushed, iclass 15, count 2 2006.173.16:08:15.01#ibcon#about to write, iclass 15, count 2 2006.173.16:08:15.01#ibcon#wrote, iclass 15, count 2 2006.173.16:08:15.01#ibcon#about to read 3, iclass 15, count 2 2006.173.16:08:15.04#ibcon#read 3, iclass 15, count 2 2006.173.16:08:15.04#ibcon#about to read 4, iclass 15, count 2 2006.173.16:08:15.04#ibcon#read 4, iclass 15, count 2 2006.173.16:08:15.04#ibcon#about to read 5, iclass 15, count 2 2006.173.16:08:15.04#ibcon#read 5, iclass 15, count 2 2006.173.16:08:15.04#ibcon#about to read 6, iclass 15, count 2 2006.173.16:08:15.04#ibcon#read 6, iclass 15, count 2 2006.173.16:08:15.04#ibcon#end of sib2, iclass 15, count 2 2006.173.16:08:15.04#ibcon#*after write, iclass 15, count 2 2006.173.16:08:15.04#ibcon#*before return 0, iclass 15, count 2 2006.173.16:08:15.04#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.16:08:15.04#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.16:08:15.04#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.16:08:15.04#ibcon#ireg 7 cls_cnt 0 2006.173.16:08:15.04#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.16:08:15.16#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.16:08:15.16#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.16:08:15.16#ibcon#enter wrdev, iclass 15, count 0 2006.173.16:08:15.16#ibcon#first serial, iclass 15, count 0 2006.173.16:08:15.16#ibcon#enter sib2, iclass 15, count 0 2006.173.16:08:15.16#ibcon#flushed, iclass 15, count 0 2006.173.16:08:15.16#ibcon#about to write, iclass 15, count 0 2006.173.16:08:15.16#ibcon#wrote, iclass 15, count 0 2006.173.16:08:15.16#ibcon#about to read 3, iclass 15, count 0 2006.173.16:08:15.18#ibcon#read 3, iclass 15, count 0 2006.173.16:08:15.18#ibcon#about to read 4, iclass 15, count 0 2006.173.16:08:15.18#ibcon#read 4, iclass 15, count 0 2006.173.16:08:15.18#ibcon#about to read 5, iclass 15, count 0 2006.173.16:08:15.18#ibcon#read 5, iclass 15, count 0 2006.173.16:08:15.18#ibcon#about to read 6, iclass 15, count 0 2006.173.16:08:15.18#ibcon#read 6, iclass 15, count 0 2006.173.16:08:15.18#ibcon#end of sib2, iclass 15, count 0 2006.173.16:08:15.18#ibcon#*mode == 0, iclass 15, count 0 2006.173.16:08:15.18#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.16:08:15.18#ibcon#[27=USB\r\n] 2006.173.16:08:15.18#ibcon#*before write, iclass 15, count 0 2006.173.16:08:15.18#ibcon#enter sib2, iclass 15, count 0 2006.173.16:08:15.18#ibcon#flushed, iclass 15, count 0 2006.173.16:08:15.18#ibcon#about to write, iclass 15, count 0 2006.173.16:08:15.18#ibcon#wrote, iclass 15, count 0 2006.173.16:08:15.18#ibcon#about to read 3, iclass 15, count 0 2006.173.16:08:15.21#ibcon#read 3, iclass 15, count 0 2006.173.16:08:15.21#ibcon#about to read 4, iclass 15, count 0 2006.173.16:08:15.21#ibcon#read 4, iclass 15, count 0 2006.173.16:08:15.21#ibcon#about to read 5, iclass 15, count 0 2006.173.16:08:15.21#ibcon#read 5, iclass 15, count 0 2006.173.16:08:15.21#ibcon#about to read 6, iclass 15, count 0 2006.173.16:08:15.21#ibcon#read 6, iclass 15, count 0 2006.173.16:08:15.21#ibcon#end of sib2, iclass 15, count 0 2006.173.16:08:15.21#ibcon#*after write, iclass 15, count 0 2006.173.16:08:15.21#ibcon#*before return 0, iclass 15, count 0 2006.173.16:08:15.21#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.16:08:15.21#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.16:08:15.21#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.16:08:15.21#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.16:08:15.21$vck44/vblo=5,709.99 2006.173.16:08:15.21#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.16:08:15.21#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.16:08:15.21#ibcon#ireg 17 cls_cnt 0 2006.173.16:08:15.21#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.16:08:15.21#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.16:08:15.21#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.16:08:15.21#ibcon#enter wrdev, iclass 17, count 0 2006.173.16:08:15.21#ibcon#first serial, iclass 17, count 0 2006.173.16:08:15.21#ibcon#enter sib2, iclass 17, count 0 2006.173.16:08:15.21#ibcon#flushed, iclass 17, count 0 2006.173.16:08:15.21#ibcon#about to write, iclass 17, count 0 2006.173.16:08:15.21#ibcon#wrote, iclass 17, count 0 2006.173.16:08:15.21#ibcon#about to read 3, iclass 17, count 0 2006.173.16:08:15.23#ibcon#read 3, iclass 17, count 0 2006.173.16:08:15.23#ibcon#about to read 4, iclass 17, count 0 2006.173.16:08:15.23#ibcon#read 4, iclass 17, count 0 2006.173.16:08:15.23#ibcon#about to read 5, iclass 17, count 0 2006.173.16:08:15.23#ibcon#read 5, iclass 17, count 0 2006.173.16:08:15.23#ibcon#about to read 6, iclass 17, count 0 2006.173.16:08:15.23#ibcon#read 6, iclass 17, count 0 2006.173.16:08:15.23#ibcon#end of sib2, iclass 17, count 0 2006.173.16:08:15.23#ibcon#*mode == 0, iclass 17, count 0 2006.173.16:08:15.23#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.16:08:15.23#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.16:08:15.23#ibcon#*before write, iclass 17, count 0 2006.173.16:08:15.23#ibcon#enter sib2, iclass 17, count 0 2006.173.16:08:15.23#ibcon#flushed, iclass 17, count 0 2006.173.16:08:15.23#ibcon#about to write, iclass 17, count 0 2006.173.16:08:15.23#ibcon#wrote, iclass 17, count 0 2006.173.16:08:15.23#ibcon#about to read 3, iclass 17, count 0 2006.173.16:08:15.27#ibcon#read 3, iclass 17, count 0 2006.173.16:08:15.27#ibcon#about to read 4, iclass 17, count 0 2006.173.16:08:15.27#ibcon#read 4, iclass 17, count 0 2006.173.16:08:15.27#ibcon#about to read 5, iclass 17, count 0 2006.173.16:08:15.27#ibcon#read 5, iclass 17, count 0 2006.173.16:08:15.27#ibcon#about to read 6, iclass 17, count 0 2006.173.16:08:15.27#ibcon#read 6, iclass 17, count 0 2006.173.16:08:15.27#ibcon#end of sib2, iclass 17, count 0 2006.173.16:08:15.27#ibcon#*after write, iclass 17, count 0 2006.173.16:08:15.27#ibcon#*before return 0, iclass 17, count 0 2006.173.16:08:15.27#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.16:08:15.27#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.16:08:15.27#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.16:08:15.27#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.16:08:15.27$vck44/vb=5,4 2006.173.16:08:15.27#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.16:08:15.27#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.16:08:15.27#ibcon#ireg 11 cls_cnt 2 2006.173.16:08:15.27#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.16:08:15.33#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.16:08:15.33#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.16:08:15.33#ibcon#enter wrdev, iclass 19, count 2 2006.173.16:08:15.33#ibcon#first serial, iclass 19, count 2 2006.173.16:08:15.33#ibcon#enter sib2, iclass 19, count 2 2006.173.16:08:15.33#ibcon#flushed, iclass 19, count 2 2006.173.16:08:15.33#ibcon#about to write, iclass 19, count 2 2006.173.16:08:15.33#ibcon#wrote, iclass 19, count 2 2006.173.16:08:15.33#ibcon#about to read 3, iclass 19, count 2 2006.173.16:08:15.35#ibcon#read 3, iclass 19, count 2 2006.173.16:08:15.35#ibcon#about to read 4, iclass 19, count 2 2006.173.16:08:15.35#ibcon#read 4, iclass 19, count 2 2006.173.16:08:15.35#ibcon#about to read 5, iclass 19, count 2 2006.173.16:08:15.35#ibcon#read 5, iclass 19, count 2 2006.173.16:08:15.35#ibcon#about to read 6, iclass 19, count 2 2006.173.16:08:15.35#ibcon#read 6, iclass 19, count 2 2006.173.16:08:15.35#ibcon#end of sib2, iclass 19, count 2 2006.173.16:08:15.35#ibcon#*mode == 0, iclass 19, count 2 2006.173.16:08:15.35#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.16:08:15.35#ibcon#[27=AT05-04\r\n] 2006.173.16:08:15.35#ibcon#*before write, iclass 19, count 2 2006.173.16:08:15.35#ibcon#enter sib2, iclass 19, count 2 2006.173.16:08:15.35#ibcon#flushed, iclass 19, count 2 2006.173.16:08:15.35#ibcon#about to write, iclass 19, count 2 2006.173.16:08:15.35#ibcon#wrote, iclass 19, count 2 2006.173.16:08:15.35#ibcon#about to read 3, iclass 19, count 2 2006.173.16:08:15.38#ibcon#read 3, iclass 19, count 2 2006.173.16:08:15.38#ibcon#about to read 4, iclass 19, count 2 2006.173.16:08:15.38#ibcon#read 4, iclass 19, count 2 2006.173.16:08:15.38#ibcon#about to read 5, iclass 19, count 2 2006.173.16:08:15.38#ibcon#read 5, iclass 19, count 2 2006.173.16:08:15.38#ibcon#about to read 6, iclass 19, count 2 2006.173.16:08:15.38#ibcon#read 6, iclass 19, count 2 2006.173.16:08:15.38#ibcon#end of sib2, iclass 19, count 2 2006.173.16:08:15.38#ibcon#*after write, iclass 19, count 2 2006.173.16:08:15.38#ibcon#*before return 0, iclass 19, count 2 2006.173.16:08:15.38#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.16:08:15.38#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.16:08:15.38#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.16:08:15.38#ibcon#ireg 7 cls_cnt 0 2006.173.16:08:15.38#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.16:08:15.50#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.16:08:15.50#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.16:08:15.50#ibcon#enter wrdev, iclass 19, count 0 2006.173.16:08:15.50#ibcon#first serial, iclass 19, count 0 2006.173.16:08:15.50#ibcon#enter sib2, iclass 19, count 0 2006.173.16:08:15.50#ibcon#flushed, iclass 19, count 0 2006.173.16:08:15.50#ibcon#about to write, iclass 19, count 0 2006.173.16:08:15.50#ibcon#wrote, iclass 19, count 0 2006.173.16:08:15.50#ibcon#about to read 3, iclass 19, count 0 2006.173.16:08:15.52#ibcon#read 3, iclass 19, count 0 2006.173.16:08:15.52#ibcon#about to read 4, iclass 19, count 0 2006.173.16:08:15.52#ibcon#read 4, iclass 19, count 0 2006.173.16:08:15.52#ibcon#about to read 5, iclass 19, count 0 2006.173.16:08:15.52#ibcon#read 5, iclass 19, count 0 2006.173.16:08:15.52#ibcon#about to read 6, iclass 19, count 0 2006.173.16:08:15.52#ibcon#read 6, iclass 19, count 0 2006.173.16:08:15.52#ibcon#end of sib2, iclass 19, count 0 2006.173.16:08:15.52#ibcon#*mode == 0, iclass 19, count 0 2006.173.16:08:15.52#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.16:08:15.52#ibcon#[27=USB\r\n] 2006.173.16:08:15.52#ibcon#*before write, iclass 19, count 0 2006.173.16:08:15.52#ibcon#enter sib2, iclass 19, count 0 2006.173.16:08:15.52#ibcon#flushed, iclass 19, count 0 2006.173.16:08:15.52#ibcon#about to write, iclass 19, count 0 2006.173.16:08:15.52#ibcon#wrote, iclass 19, count 0 2006.173.16:08:15.52#ibcon#about to read 3, iclass 19, count 0 2006.173.16:08:15.55#ibcon#read 3, iclass 19, count 0 2006.173.16:08:15.55#ibcon#about to read 4, iclass 19, count 0 2006.173.16:08:15.55#ibcon#read 4, iclass 19, count 0 2006.173.16:08:15.55#ibcon#about to read 5, iclass 19, count 0 2006.173.16:08:15.55#ibcon#read 5, iclass 19, count 0 2006.173.16:08:15.55#ibcon#about to read 6, iclass 19, count 0 2006.173.16:08:15.55#ibcon#read 6, iclass 19, count 0 2006.173.16:08:15.55#ibcon#end of sib2, iclass 19, count 0 2006.173.16:08:15.55#ibcon#*after write, iclass 19, count 0 2006.173.16:08:15.55#ibcon#*before return 0, iclass 19, count 0 2006.173.16:08:15.55#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.16:08:15.55#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.16:08:15.55#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.16:08:15.55#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.16:08:15.55$vck44/vblo=6,719.99 2006.173.16:08:15.55#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.16:08:15.55#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.16:08:15.55#ibcon#ireg 17 cls_cnt 0 2006.173.16:08:15.55#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.16:08:15.55#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.16:08:15.55#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.16:08:15.55#ibcon#enter wrdev, iclass 21, count 0 2006.173.16:08:15.55#ibcon#first serial, iclass 21, count 0 2006.173.16:08:15.55#ibcon#enter sib2, iclass 21, count 0 2006.173.16:08:15.55#ibcon#flushed, iclass 21, count 0 2006.173.16:08:15.55#ibcon#about to write, iclass 21, count 0 2006.173.16:08:15.55#ibcon#wrote, iclass 21, count 0 2006.173.16:08:15.55#ibcon#about to read 3, iclass 21, count 0 2006.173.16:08:15.57#ibcon#read 3, iclass 21, count 0 2006.173.16:08:15.57#ibcon#about to read 4, iclass 21, count 0 2006.173.16:08:15.57#ibcon#read 4, iclass 21, count 0 2006.173.16:08:15.57#ibcon#about to read 5, iclass 21, count 0 2006.173.16:08:15.57#ibcon#read 5, iclass 21, count 0 2006.173.16:08:15.57#ibcon#about to read 6, iclass 21, count 0 2006.173.16:08:15.57#ibcon#read 6, iclass 21, count 0 2006.173.16:08:15.57#ibcon#end of sib2, iclass 21, count 0 2006.173.16:08:15.57#ibcon#*mode == 0, iclass 21, count 0 2006.173.16:08:15.57#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.16:08:15.57#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.16:08:15.57#ibcon#*before write, iclass 21, count 0 2006.173.16:08:15.57#ibcon#enter sib2, iclass 21, count 0 2006.173.16:08:15.57#ibcon#flushed, iclass 21, count 0 2006.173.16:08:15.57#ibcon#about to write, iclass 21, count 0 2006.173.16:08:15.57#ibcon#wrote, iclass 21, count 0 2006.173.16:08:15.57#ibcon#about to read 3, iclass 21, count 0 2006.173.16:08:15.61#ibcon#read 3, iclass 21, count 0 2006.173.16:08:15.61#ibcon#about to read 4, iclass 21, count 0 2006.173.16:08:15.61#ibcon#read 4, iclass 21, count 0 2006.173.16:08:15.61#ibcon#about to read 5, iclass 21, count 0 2006.173.16:08:15.61#ibcon#read 5, iclass 21, count 0 2006.173.16:08:15.61#ibcon#about to read 6, iclass 21, count 0 2006.173.16:08:15.61#ibcon#read 6, iclass 21, count 0 2006.173.16:08:15.61#ibcon#end of sib2, iclass 21, count 0 2006.173.16:08:15.61#ibcon#*after write, iclass 21, count 0 2006.173.16:08:15.61#ibcon#*before return 0, iclass 21, count 0 2006.173.16:08:15.61#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.16:08:15.61#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.16:08:15.61#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.16:08:15.61#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.16:08:15.61$vck44/vb=6,4 2006.173.16:08:15.61#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.16:08:15.61#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.16:08:15.61#ibcon#ireg 11 cls_cnt 2 2006.173.16:08:15.61#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.16:08:15.67#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.16:08:15.67#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.16:08:15.67#ibcon#enter wrdev, iclass 23, count 2 2006.173.16:08:15.67#ibcon#first serial, iclass 23, count 2 2006.173.16:08:15.67#ibcon#enter sib2, iclass 23, count 2 2006.173.16:08:15.67#ibcon#flushed, iclass 23, count 2 2006.173.16:08:15.67#ibcon#about to write, iclass 23, count 2 2006.173.16:08:15.67#ibcon#wrote, iclass 23, count 2 2006.173.16:08:15.67#ibcon#about to read 3, iclass 23, count 2 2006.173.16:08:15.69#ibcon#read 3, iclass 23, count 2 2006.173.16:08:15.69#ibcon#about to read 4, iclass 23, count 2 2006.173.16:08:15.69#ibcon#read 4, iclass 23, count 2 2006.173.16:08:15.69#ibcon#about to read 5, iclass 23, count 2 2006.173.16:08:15.69#ibcon#read 5, iclass 23, count 2 2006.173.16:08:15.69#ibcon#about to read 6, iclass 23, count 2 2006.173.16:08:15.69#ibcon#read 6, iclass 23, count 2 2006.173.16:08:15.69#ibcon#end of sib2, iclass 23, count 2 2006.173.16:08:15.69#ibcon#*mode == 0, iclass 23, count 2 2006.173.16:08:15.69#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.16:08:15.69#ibcon#[27=AT06-04\r\n] 2006.173.16:08:15.69#ibcon#*before write, iclass 23, count 2 2006.173.16:08:15.69#ibcon#enter sib2, iclass 23, count 2 2006.173.16:08:15.69#ibcon#flushed, iclass 23, count 2 2006.173.16:08:15.69#ibcon#about to write, iclass 23, count 2 2006.173.16:08:15.69#ibcon#wrote, iclass 23, count 2 2006.173.16:08:15.69#ibcon#about to read 3, iclass 23, count 2 2006.173.16:08:15.72#ibcon#read 3, iclass 23, count 2 2006.173.16:08:15.72#ibcon#about to read 4, iclass 23, count 2 2006.173.16:08:15.72#ibcon#read 4, iclass 23, count 2 2006.173.16:08:15.72#ibcon#about to read 5, iclass 23, count 2 2006.173.16:08:15.72#ibcon#read 5, iclass 23, count 2 2006.173.16:08:15.72#ibcon#about to read 6, iclass 23, count 2 2006.173.16:08:15.72#ibcon#read 6, iclass 23, count 2 2006.173.16:08:15.72#ibcon#end of sib2, iclass 23, count 2 2006.173.16:08:15.72#ibcon#*after write, iclass 23, count 2 2006.173.16:08:15.72#ibcon#*before return 0, iclass 23, count 2 2006.173.16:08:15.72#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.16:08:15.72#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.16:08:15.72#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.16:08:15.72#ibcon#ireg 7 cls_cnt 0 2006.173.16:08:15.72#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.16:08:15.84#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.16:08:15.84#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.16:08:15.84#ibcon#enter wrdev, iclass 23, count 0 2006.173.16:08:15.84#ibcon#first serial, iclass 23, count 0 2006.173.16:08:15.84#ibcon#enter sib2, iclass 23, count 0 2006.173.16:08:15.84#ibcon#flushed, iclass 23, count 0 2006.173.16:08:15.84#ibcon#about to write, iclass 23, count 0 2006.173.16:08:15.84#ibcon#wrote, iclass 23, count 0 2006.173.16:08:15.84#ibcon#about to read 3, iclass 23, count 0 2006.173.16:08:15.86#ibcon#read 3, iclass 23, count 0 2006.173.16:08:15.86#ibcon#about to read 4, iclass 23, count 0 2006.173.16:08:15.86#ibcon#read 4, iclass 23, count 0 2006.173.16:08:15.86#ibcon#about to read 5, iclass 23, count 0 2006.173.16:08:15.86#ibcon#read 5, iclass 23, count 0 2006.173.16:08:15.86#ibcon#about to read 6, iclass 23, count 0 2006.173.16:08:15.86#ibcon#read 6, iclass 23, count 0 2006.173.16:08:15.86#ibcon#end of sib2, iclass 23, count 0 2006.173.16:08:15.86#ibcon#*mode == 0, iclass 23, count 0 2006.173.16:08:15.86#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.16:08:15.86#ibcon#[27=USB\r\n] 2006.173.16:08:15.86#ibcon#*before write, iclass 23, count 0 2006.173.16:08:15.86#ibcon#enter sib2, iclass 23, count 0 2006.173.16:08:15.86#ibcon#flushed, iclass 23, count 0 2006.173.16:08:15.86#ibcon#about to write, iclass 23, count 0 2006.173.16:08:15.86#ibcon#wrote, iclass 23, count 0 2006.173.16:08:15.86#ibcon#about to read 3, iclass 23, count 0 2006.173.16:08:15.89#ibcon#read 3, iclass 23, count 0 2006.173.16:08:15.89#ibcon#about to read 4, iclass 23, count 0 2006.173.16:08:15.89#ibcon#read 4, iclass 23, count 0 2006.173.16:08:15.89#ibcon#about to read 5, iclass 23, count 0 2006.173.16:08:15.89#ibcon#read 5, iclass 23, count 0 2006.173.16:08:15.89#ibcon#about to read 6, iclass 23, count 0 2006.173.16:08:15.89#ibcon#read 6, iclass 23, count 0 2006.173.16:08:15.89#ibcon#end of sib2, iclass 23, count 0 2006.173.16:08:15.89#ibcon#*after write, iclass 23, count 0 2006.173.16:08:15.89#ibcon#*before return 0, iclass 23, count 0 2006.173.16:08:15.89#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.16:08:15.89#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.16:08:15.89#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.16:08:15.89#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.16:08:15.89$vck44/vblo=7,734.99 2006.173.16:08:15.89#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.16:08:15.89#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.16:08:15.89#ibcon#ireg 17 cls_cnt 0 2006.173.16:08:15.89#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.16:08:15.89#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.16:08:15.89#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.16:08:15.89#ibcon#enter wrdev, iclass 25, count 0 2006.173.16:08:15.89#ibcon#first serial, iclass 25, count 0 2006.173.16:08:15.89#ibcon#enter sib2, iclass 25, count 0 2006.173.16:08:15.89#ibcon#flushed, iclass 25, count 0 2006.173.16:08:15.89#ibcon#about to write, iclass 25, count 0 2006.173.16:08:15.89#ibcon#wrote, iclass 25, count 0 2006.173.16:08:15.89#ibcon#about to read 3, iclass 25, count 0 2006.173.16:08:15.91#ibcon#read 3, iclass 25, count 0 2006.173.16:08:15.91#ibcon#about to read 4, iclass 25, count 0 2006.173.16:08:15.91#ibcon#read 4, iclass 25, count 0 2006.173.16:08:15.91#ibcon#about to read 5, iclass 25, count 0 2006.173.16:08:15.91#ibcon#read 5, iclass 25, count 0 2006.173.16:08:15.91#ibcon#about to read 6, iclass 25, count 0 2006.173.16:08:15.91#ibcon#read 6, iclass 25, count 0 2006.173.16:08:15.91#ibcon#end of sib2, iclass 25, count 0 2006.173.16:08:15.91#ibcon#*mode == 0, iclass 25, count 0 2006.173.16:08:15.91#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.16:08:15.91#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.16:08:15.91#ibcon#*before write, iclass 25, count 0 2006.173.16:08:15.91#ibcon#enter sib2, iclass 25, count 0 2006.173.16:08:15.91#ibcon#flushed, iclass 25, count 0 2006.173.16:08:15.91#ibcon#about to write, iclass 25, count 0 2006.173.16:08:15.91#ibcon#wrote, iclass 25, count 0 2006.173.16:08:15.91#ibcon#about to read 3, iclass 25, count 0 2006.173.16:08:15.95#ibcon#read 3, iclass 25, count 0 2006.173.16:08:15.95#ibcon#about to read 4, iclass 25, count 0 2006.173.16:08:15.95#ibcon#read 4, iclass 25, count 0 2006.173.16:08:15.95#ibcon#about to read 5, iclass 25, count 0 2006.173.16:08:15.95#ibcon#read 5, iclass 25, count 0 2006.173.16:08:15.95#ibcon#about to read 6, iclass 25, count 0 2006.173.16:08:15.95#ibcon#read 6, iclass 25, count 0 2006.173.16:08:15.95#ibcon#end of sib2, iclass 25, count 0 2006.173.16:08:15.95#ibcon#*after write, iclass 25, count 0 2006.173.16:08:15.95#ibcon#*before return 0, iclass 25, count 0 2006.173.16:08:15.95#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.16:08:15.95#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.16:08:15.95#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.16:08:15.95#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.16:08:15.95$vck44/vb=7,4 2006.173.16:08:15.95#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.16:08:15.95#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.16:08:15.95#ibcon#ireg 11 cls_cnt 2 2006.173.16:08:15.95#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.16:08:16.01#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.16:08:16.01#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.16:08:16.01#ibcon#enter wrdev, iclass 27, count 2 2006.173.16:08:16.01#ibcon#first serial, iclass 27, count 2 2006.173.16:08:16.01#ibcon#enter sib2, iclass 27, count 2 2006.173.16:08:16.01#ibcon#flushed, iclass 27, count 2 2006.173.16:08:16.01#ibcon#about to write, iclass 27, count 2 2006.173.16:08:16.01#ibcon#wrote, iclass 27, count 2 2006.173.16:08:16.01#ibcon#about to read 3, iclass 27, count 2 2006.173.16:08:16.03#ibcon#read 3, iclass 27, count 2 2006.173.16:08:16.03#ibcon#about to read 4, iclass 27, count 2 2006.173.16:08:16.03#ibcon#read 4, iclass 27, count 2 2006.173.16:08:16.03#ibcon#about to read 5, iclass 27, count 2 2006.173.16:08:16.03#ibcon#read 5, iclass 27, count 2 2006.173.16:08:16.03#ibcon#about to read 6, iclass 27, count 2 2006.173.16:08:16.03#ibcon#read 6, iclass 27, count 2 2006.173.16:08:16.03#ibcon#end of sib2, iclass 27, count 2 2006.173.16:08:16.03#ibcon#*mode == 0, iclass 27, count 2 2006.173.16:08:16.03#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.16:08:16.03#ibcon#[27=AT07-04\r\n] 2006.173.16:08:16.03#ibcon#*before write, iclass 27, count 2 2006.173.16:08:16.03#ibcon#enter sib2, iclass 27, count 2 2006.173.16:08:16.03#ibcon#flushed, iclass 27, count 2 2006.173.16:08:16.03#ibcon#about to write, iclass 27, count 2 2006.173.16:08:16.03#ibcon#wrote, iclass 27, count 2 2006.173.16:08:16.03#ibcon#about to read 3, iclass 27, count 2 2006.173.16:08:16.06#ibcon#read 3, iclass 27, count 2 2006.173.16:08:16.06#ibcon#about to read 4, iclass 27, count 2 2006.173.16:08:16.06#ibcon#read 4, iclass 27, count 2 2006.173.16:08:16.06#ibcon#about to read 5, iclass 27, count 2 2006.173.16:08:16.06#ibcon#read 5, iclass 27, count 2 2006.173.16:08:16.06#ibcon#about to read 6, iclass 27, count 2 2006.173.16:08:16.06#ibcon#read 6, iclass 27, count 2 2006.173.16:08:16.06#ibcon#end of sib2, iclass 27, count 2 2006.173.16:08:16.06#ibcon#*after write, iclass 27, count 2 2006.173.16:08:16.06#ibcon#*before return 0, iclass 27, count 2 2006.173.16:08:16.06#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.16:08:16.06#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.16:08:16.06#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.16:08:16.06#ibcon#ireg 7 cls_cnt 0 2006.173.16:08:16.06#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.16:08:16.18#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.16:08:16.18#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.16:08:16.18#ibcon#enter wrdev, iclass 27, count 0 2006.173.16:08:16.18#ibcon#first serial, iclass 27, count 0 2006.173.16:08:16.18#ibcon#enter sib2, iclass 27, count 0 2006.173.16:08:16.18#ibcon#flushed, iclass 27, count 0 2006.173.16:08:16.18#ibcon#about to write, iclass 27, count 0 2006.173.16:08:16.18#ibcon#wrote, iclass 27, count 0 2006.173.16:08:16.18#ibcon#about to read 3, iclass 27, count 0 2006.173.16:08:16.20#ibcon#read 3, iclass 27, count 0 2006.173.16:08:16.20#ibcon#about to read 4, iclass 27, count 0 2006.173.16:08:16.20#ibcon#read 4, iclass 27, count 0 2006.173.16:08:16.20#ibcon#about to read 5, iclass 27, count 0 2006.173.16:08:16.20#ibcon#read 5, iclass 27, count 0 2006.173.16:08:16.20#ibcon#about to read 6, iclass 27, count 0 2006.173.16:08:16.20#ibcon#read 6, iclass 27, count 0 2006.173.16:08:16.20#ibcon#end of sib2, iclass 27, count 0 2006.173.16:08:16.20#ibcon#*mode == 0, iclass 27, count 0 2006.173.16:08:16.20#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.16:08:16.20#ibcon#[27=USB\r\n] 2006.173.16:08:16.20#ibcon#*before write, iclass 27, count 0 2006.173.16:08:16.20#ibcon#enter sib2, iclass 27, count 0 2006.173.16:08:16.20#ibcon#flushed, iclass 27, count 0 2006.173.16:08:16.20#ibcon#about to write, iclass 27, count 0 2006.173.16:08:16.20#ibcon#wrote, iclass 27, count 0 2006.173.16:08:16.20#ibcon#about to read 3, iclass 27, count 0 2006.173.16:08:16.23#ibcon#read 3, iclass 27, count 0 2006.173.16:08:16.23#ibcon#about to read 4, iclass 27, count 0 2006.173.16:08:16.23#ibcon#read 4, iclass 27, count 0 2006.173.16:08:16.23#ibcon#about to read 5, iclass 27, count 0 2006.173.16:08:16.23#ibcon#read 5, iclass 27, count 0 2006.173.16:08:16.23#ibcon#about to read 6, iclass 27, count 0 2006.173.16:08:16.23#ibcon#read 6, iclass 27, count 0 2006.173.16:08:16.23#ibcon#end of sib2, iclass 27, count 0 2006.173.16:08:16.23#ibcon#*after write, iclass 27, count 0 2006.173.16:08:16.23#ibcon#*before return 0, iclass 27, count 0 2006.173.16:08:16.23#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.16:08:16.23#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.16:08:16.23#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.16:08:16.23#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.16:08:16.23$vck44/vblo=8,744.99 2006.173.16:08:16.23#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.16:08:16.23#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.16:08:16.23#ibcon#ireg 17 cls_cnt 0 2006.173.16:08:16.23#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.16:08:16.23#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.16:08:16.23#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.16:08:16.23#ibcon#enter wrdev, iclass 29, count 0 2006.173.16:08:16.23#ibcon#first serial, iclass 29, count 0 2006.173.16:08:16.23#ibcon#enter sib2, iclass 29, count 0 2006.173.16:08:16.23#ibcon#flushed, iclass 29, count 0 2006.173.16:08:16.23#ibcon#about to write, iclass 29, count 0 2006.173.16:08:16.23#ibcon#wrote, iclass 29, count 0 2006.173.16:08:16.23#ibcon#about to read 3, iclass 29, count 0 2006.173.16:08:16.25#ibcon#read 3, iclass 29, count 0 2006.173.16:08:16.25#ibcon#about to read 4, iclass 29, count 0 2006.173.16:08:16.25#ibcon#read 4, iclass 29, count 0 2006.173.16:08:16.25#ibcon#about to read 5, iclass 29, count 0 2006.173.16:08:16.25#ibcon#read 5, iclass 29, count 0 2006.173.16:08:16.25#ibcon#about to read 6, iclass 29, count 0 2006.173.16:08:16.25#ibcon#read 6, iclass 29, count 0 2006.173.16:08:16.25#ibcon#end of sib2, iclass 29, count 0 2006.173.16:08:16.25#ibcon#*mode == 0, iclass 29, count 0 2006.173.16:08:16.25#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.16:08:16.25#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.16:08:16.25#ibcon#*before write, iclass 29, count 0 2006.173.16:08:16.25#ibcon#enter sib2, iclass 29, count 0 2006.173.16:08:16.25#ibcon#flushed, iclass 29, count 0 2006.173.16:08:16.25#ibcon#about to write, iclass 29, count 0 2006.173.16:08:16.25#ibcon#wrote, iclass 29, count 0 2006.173.16:08:16.25#ibcon#about to read 3, iclass 29, count 0 2006.173.16:08:16.29#ibcon#read 3, iclass 29, count 0 2006.173.16:08:16.29#ibcon#about to read 4, iclass 29, count 0 2006.173.16:08:16.29#ibcon#read 4, iclass 29, count 0 2006.173.16:08:16.29#ibcon#about to read 5, iclass 29, count 0 2006.173.16:08:16.29#ibcon#read 5, iclass 29, count 0 2006.173.16:08:16.29#ibcon#about to read 6, iclass 29, count 0 2006.173.16:08:16.29#ibcon#read 6, iclass 29, count 0 2006.173.16:08:16.29#ibcon#end of sib2, iclass 29, count 0 2006.173.16:08:16.29#ibcon#*after write, iclass 29, count 0 2006.173.16:08:16.29#ibcon#*before return 0, iclass 29, count 0 2006.173.16:08:16.29#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.16:08:16.29#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.16:08:16.29#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.16:08:16.29#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.16:08:16.29$vck44/vb=8,4 2006.173.16:08:16.29#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.16:08:16.29#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.16:08:16.29#ibcon#ireg 11 cls_cnt 2 2006.173.16:08:16.29#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.16:08:16.35#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.16:08:16.35#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.16:08:16.35#ibcon#enter wrdev, iclass 31, count 2 2006.173.16:08:16.35#ibcon#first serial, iclass 31, count 2 2006.173.16:08:16.35#ibcon#enter sib2, iclass 31, count 2 2006.173.16:08:16.35#ibcon#flushed, iclass 31, count 2 2006.173.16:08:16.35#ibcon#about to write, iclass 31, count 2 2006.173.16:08:16.35#ibcon#wrote, iclass 31, count 2 2006.173.16:08:16.35#ibcon#about to read 3, iclass 31, count 2 2006.173.16:08:16.37#ibcon#read 3, iclass 31, count 2 2006.173.16:08:16.37#ibcon#about to read 4, iclass 31, count 2 2006.173.16:08:16.37#ibcon#read 4, iclass 31, count 2 2006.173.16:08:16.37#ibcon#about to read 5, iclass 31, count 2 2006.173.16:08:16.37#ibcon#read 5, iclass 31, count 2 2006.173.16:08:16.37#ibcon#about to read 6, iclass 31, count 2 2006.173.16:08:16.37#ibcon#read 6, iclass 31, count 2 2006.173.16:08:16.37#ibcon#end of sib2, iclass 31, count 2 2006.173.16:08:16.37#ibcon#*mode == 0, iclass 31, count 2 2006.173.16:08:16.37#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.16:08:16.37#ibcon#[27=AT08-04\r\n] 2006.173.16:08:16.37#ibcon#*before write, iclass 31, count 2 2006.173.16:08:16.37#ibcon#enter sib2, iclass 31, count 2 2006.173.16:08:16.37#ibcon#flushed, iclass 31, count 2 2006.173.16:08:16.37#ibcon#about to write, iclass 31, count 2 2006.173.16:08:16.37#ibcon#wrote, iclass 31, count 2 2006.173.16:08:16.37#ibcon#about to read 3, iclass 31, count 2 2006.173.16:08:16.40#ibcon#read 3, iclass 31, count 2 2006.173.16:08:16.40#ibcon#about to read 4, iclass 31, count 2 2006.173.16:08:16.40#ibcon#read 4, iclass 31, count 2 2006.173.16:08:16.40#ibcon#about to read 5, iclass 31, count 2 2006.173.16:08:16.40#ibcon#read 5, iclass 31, count 2 2006.173.16:08:16.40#ibcon#about to read 6, iclass 31, count 2 2006.173.16:08:16.40#ibcon#read 6, iclass 31, count 2 2006.173.16:08:16.40#ibcon#end of sib2, iclass 31, count 2 2006.173.16:08:16.40#ibcon#*after write, iclass 31, count 2 2006.173.16:08:16.40#ibcon#*before return 0, iclass 31, count 2 2006.173.16:08:16.40#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.16:08:16.40#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.16:08:16.40#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.16:08:16.40#ibcon#ireg 7 cls_cnt 0 2006.173.16:08:16.40#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.16:08:16.52#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.16:08:16.52#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.16:08:16.52#ibcon#enter wrdev, iclass 31, count 0 2006.173.16:08:16.52#ibcon#first serial, iclass 31, count 0 2006.173.16:08:16.52#ibcon#enter sib2, iclass 31, count 0 2006.173.16:08:16.52#ibcon#flushed, iclass 31, count 0 2006.173.16:08:16.52#ibcon#about to write, iclass 31, count 0 2006.173.16:08:16.52#ibcon#wrote, iclass 31, count 0 2006.173.16:08:16.52#ibcon#about to read 3, iclass 31, count 0 2006.173.16:08:16.54#ibcon#read 3, iclass 31, count 0 2006.173.16:08:16.54#ibcon#about to read 4, iclass 31, count 0 2006.173.16:08:16.54#ibcon#read 4, iclass 31, count 0 2006.173.16:08:16.54#ibcon#about to read 5, iclass 31, count 0 2006.173.16:08:16.54#ibcon#read 5, iclass 31, count 0 2006.173.16:08:16.54#ibcon#about to read 6, iclass 31, count 0 2006.173.16:08:16.54#ibcon#read 6, iclass 31, count 0 2006.173.16:08:16.54#ibcon#end of sib2, iclass 31, count 0 2006.173.16:08:16.54#ibcon#*mode == 0, iclass 31, count 0 2006.173.16:08:16.54#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.16:08:16.54#ibcon#[27=USB\r\n] 2006.173.16:08:16.54#ibcon#*before write, iclass 31, count 0 2006.173.16:08:16.54#ibcon#enter sib2, iclass 31, count 0 2006.173.16:08:16.54#ibcon#flushed, iclass 31, count 0 2006.173.16:08:16.54#ibcon#about to write, iclass 31, count 0 2006.173.16:08:16.54#ibcon#wrote, iclass 31, count 0 2006.173.16:08:16.54#ibcon#about to read 3, iclass 31, count 0 2006.173.16:08:16.57#ibcon#read 3, iclass 31, count 0 2006.173.16:08:16.57#ibcon#about to read 4, iclass 31, count 0 2006.173.16:08:16.57#ibcon#read 4, iclass 31, count 0 2006.173.16:08:16.57#ibcon#about to read 5, iclass 31, count 0 2006.173.16:08:16.57#ibcon#read 5, iclass 31, count 0 2006.173.16:08:16.57#ibcon#about to read 6, iclass 31, count 0 2006.173.16:08:16.57#ibcon#read 6, iclass 31, count 0 2006.173.16:08:16.57#ibcon#end of sib2, iclass 31, count 0 2006.173.16:08:16.57#ibcon#*after write, iclass 31, count 0 2006.173.16:08:16.57#ibcon#*before return 0, iclass 31, count 0 2006.173.16:08:16.57#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.16:08:16.57#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.16:08:16.57#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.16:08:16.57#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.16:08:16.57$vck44/vabw=wide 2006.173.16:08:16.57#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.16:08:16.57#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.16:08:16.57#ibcon#ireg 8 cls_cnt 0 2006.173.16:08:16.57#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.16:08:16.57#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.16:08:16.57#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.16:08:16.57#ibcon#enter wrdev, iclass 33, count 0 2006.173.16:08:16.57#ibcon#first serial, iclass 33, count 0 2006.173.16:08:16.57#ibcon#enter sib2, iclass 33, count 0 2006.173.16:08:16.57#ibcon#flushed, iclass 33, count 0 2006.173.16:08:16.57#ibcon#about to write, iclass 33, count 0 2006.173.16:08:16.57#ibcon#wrote, iclass 33, count 0 2006.173.16:08:16.57#ibcon#about to read 3, iclass 33, count 0 2006.173.16:08:16.59#ibcon#read 3, iclass 33, count 0 2006.173.16:08:16.59#ibcon#about to read 4, iclass 33, count 0 2006.173.16:08:16.59#ibcon#read 4, iclass 33, count 0 2006.173.16:08:16.59#ibcon#about to read 5, iclass 33, count 0 2006.173.16:08:16.59#ibcon#read 5, iclass 33, count 0 2006.173.16:08:16.59#ibcon#about to read 6, iclass 33, count 0 2006.173.16:08:16.59#ibcon#read 6, iclass 33, count 0 2006.173.16:08:16.59#ibcon#end of sib2, iclass 33, count 0 2006.173.16:08:16.59#ibcon#*mode == 0, iclass 33, count 0 2006.173.16:08:16.59#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.16:08:16.59#ibcon#[25=BW32\r\n] 2006.173.16:08:16.59#ibcon#*before write, iclass 33, count 0 2006.173.16:08:16.59#ibcon#enter sib2, iclass 33, count 0 2006.173.16:08:16.59#ibcon#flushed, iclass 33, count 0 2006.173.16:08:16.59#ibcon#about to write, iclass 33, count 0 2006.173.16:08:16.59#ibcon#wrote, iclass 33, count 0 2006.173.16:08:16.59#ibcon#about to read 3, iclass 33, count 0 2006.173.16:08:16.62#ibcon#read 3, iclass 33, count 0 2006.173.16:08:16.62#ibcon#about to read 4, iclass 33, count 0 2006.173.16:08:16.62#ibcon#read 4, iclass 33, count 0 2006.173.16:08:16.62#ibcon#about to read 5, iclass 33, count 0 2006.173.16:08:16.62#ibcon#read 5, iclass 33, count 0 2006.173.16:08:16.62#ibcon#about to read 6, iclass 33, count 0 2006.173.16:08:16.62#ibcon#read 6, iclass 33, count 0 2006.173.16:08:16.62#ibcon#end of sib2, iclass 33, count 0 2006.173.16:08:16.62#ibcon#*after write, iclass 33, count 0 2006.173.16:08:16.62#ibcon#*before return 0, iclass 33, count 0 2006.173.16:08:16.62#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.16:08:16.62#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.16:08:16.62#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.16:08:16.62#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.16:08:16.62$vck44/vbbw=wide 2006.173.16:08:16.62#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.16:08:16.62#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.16:08:16.62#ibcon#ireg 8 cls_cnt 0 2006.173.16:08:16.62#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.16:08:16.69#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.16:08:16.69#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.16:08:16.69#ibcon#enter wrdev, iclass 35, count 0 2006.173.16:08:16.69#ibcon#first serial, iclass 35, count 0 2006.173.16:08:16.69#ibcon#enter sib2, iclass 35, count 0 2006.173.16:08:16.69#ibcon#flushed, iclass 35, count 0 2006.173.16:08:16.69#ibcon#about to write, iclass 35, count 0 2006.173.16:08:16.69#ibcon#wrote, iclass 35, count 0 2006.173.16:08:16.69#ibcon#about to read 3, iclass 35, count 0 2006.173.16:08:16.71#ibcon#read 3, iclass 35, count 0 2006.173.16:08:16.71#ibcon#about to read 4, iclass 35, count 0 2006.173.16:08:16.71#ibcon#read 4, iclass 35, count 0 2006.173.16:08:16.71#ibcon#about to read 5, iclass 35, count 0 2006.173.16:08:16.71#ibcon#read 5, iclass 35, count 0 2006.173.16:08:16.71#ibcon#about to read 6, iclass 35, count 0 2006.173.16:08:16.71#ibcon#read 6, iclass 35, count 0 2006.173.16:08:16.71#ibcon#end of sib2, iclass 35, count 0 2006.173.16:08:16.71#ibcon#*mode == 0, iclass 35, count 0 2006.173.16:08:16.71#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.16:08:16.71#ibcon#[27=BW32\r\n] 2006.173.16:08:16.71#ibcon#*before write, iclass 35, count 0 2006.173.16:08:16.71#ibcon#enter sib2, iclass 35, count 0 2006.173.16:08:16.71#ibcon#flushed, iclass 35, count 0 2006.173.16:08:16.71#ibcon#about to write, iclass 35, count 0 2006.173.16:08:16.71#ibcon#wrote, iclass 35, count 0 2006.173.16:08:16.71#ibcon#about to read 3, iclass 35, count 0 2006.173.16:08:16.74#ibcon#read 3, iclass 35, count 0 2006.173.16:08:16.74#ibcon#about to read 4, iclass 35, count 0 2006.173.16:08:16.74#ibcon#read 4, iclass 35, count 0 2006.173.16:08:16.74#ibcon#about to read 5, iclass 35, count 0 2006.173.16:08:16.74#ibcon#read 5, iclass 35, count 0 2006.173.16:08:16.74#ibcon#about to read 6, iclass 35, count 0 2006.173.16:08:16.74#ibcon#read 6, iclass 35, count 0 2006.173.16:08:16.74#ibcon#end of sib2, iclass 35, count 0 2006.173.16:08:16.74#ibcon#*after write, iclass 35, count 0 2006.173.16:08:16.74#ibcon#*before return 0, iclass 35, count 0 2006.173.16:08:16.74#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.16:08:16.74#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.16:08:16.74#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.16:08:16.74#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.16:08:16.74$setupk4/ifdk4 2006.173.16:08:16.74$ifdk4/lo= 2006.173.16:08:16.74$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.16:08:16.74$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.16:08:16.74$ifdk4/patch= 2006.173.16:08:16.75$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.16:08:16.75$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.16:08:16.75$setupk4/!*+20s 2006.173.16:08:23.57#abcon#<5=/14 1.4 2.9 20.621001002.9\r\n> 2006.173.16:08:23.59#abcon#{5=INTERFACE CLEAR} 2006.173.16:08:23.65#abcon#[5=S1D000X0/0*\r\n] 2006.173.16:08:31.26$setupk4/"tpicd 2006.173.16:08:31.26$setupk4/echo=off 2006.173.16:08:31.26$setupk4/xlog=off 2006.173.16:08:31.26:!2006.173.16:17:51 2006.173.16:08:36.13#trakl#Source acquired 2006.173.16:08:37.13#flagr#flagr/antenna,acquired 2006.173.16:17:51.00:preob 2006.173.16:17:51.13/onsource/TRACKING 2006.173.16:17:51.13:!2006.173.16:18:01 2006.173.16:18:01.00:"tape 2006.173.16:18:01.00:"st=record 2006.173.16:18:01.00:data_valid=on 2006.173.16:18:01.00:midob 2006.173.16:18:01.13/onsource/TRACKING 2006.173.16:18:01.13/wx/20.50,1003.0,100 2006.173.16:18:01.33/cable/+6.5124E-03 2006.173.16:18:02.42/va/01,07,usb,yes,40,43 2006.173.16:18:02.42/va/02,06,usb,yes,39,40 2006.173.16:18:02.42/va/03,05,usb,yes,50,52 2006.173.16:18:02.42/va/04,06,usb,yes,40,43 2006.173.16:18:02.42/va/05,04,usb,yes,32,32 2006.173.16:18:02.42/va/06,03,usb,yes,44,44 2006.173.16:18:02.42/va/07,04,usb,yes,36,37 2006.173.16:18:02.42/va/08,04,usb,yes,31,37 2006.173.16:18:02.65/valo/01,524.99,yes,locked 2006.173.16:18:02.65/valo/02,534.99,yes,locked 2006.173.16:18:02.65/valo/03,564.99,yes,locked 2006.173.16:18:02.65/valo/04,624.99,yes,locked 2006.173.16:18:02.65/valo/05,734.99,yes,locked 2006.173.16:18:02.65/valo/06,814.99,yes,locked 2006.173.16:18:02.65/valo/07,864.99,yes,locked 2006.173.16:18:02.65/valo/08,884.99,yes,locked 2006.173.16:18:03.74/vb/01,04,usb,yes,31,29 2006.173.16:18:03.74/vb/02,04,usb,yes,34,34 2006.173.16:18:03.74/vb/03,04,usb,yes,31,34 2006.173.16:18:03.74/vb/04,04,usb,yes,35,34 2006.173.16:18:03.74/vb/05,04,usb,yes,28,30 2006.173.16:18:03.74/vb/06,04,usb,yes,32,28 2006.173.16:18:03.74/vb/07,04,usb,yes,32,32 2006.173.16:18:03.74/vb/08,04,usb,yes,29,33 2006.173.16:18:03.98/vblo/01,629.99,yes,locked 2006.173.16:18:03.98/vblo/02,634.99,yes,locked 2006.173.16:18:03.98/vblo/03,649.99,yes,locked 2006.173.16:18:03.98/vblo/04,679.99,yes,locked 2006.173.16:18:03.98/vblo/05,709.99,yes,locked 2006.173.16:18:03.98/vblo/06,719.99,yes,locked 2006.173.16:18:03.98/vblo/07,734.99,yes,locked 2006.173.16:18:03.98/vblo/08,744.99,yes,locked 2006.173.16:18:04.13/vabw/8 2006.173.16:18:04.28/vbbw/8 2006.173.16:18:04.37/xfe/off,on,15.5 2006.173.16:18:04.76/ifatt/23,28,28,28 2006.173.16:18:05.07/fmout-gps/S +3.96E-07 2006.173.16:18:05.11:!2006.173.16:26:41 2006.173.16:26:41.00:data_valid=off 2006.173.16:26:41.00:"et 2006.173.16:26:41.00:!+3s 2006.173.16:26:44.01:"tape 2006.173.16:26:44.01:postob 2006.173.16:26:44.08/cable/+6.5115E-03 2006.173.16:26:44.08/wx/20.46,1002.8,100 2006.173.16:26:45.08/fmout-gps/S +3.98E-07 2006.173.16:26:45.08:scan_name=173-1627,jd0606,40 2006.173.16:26:45.08:source=1954-388,195800.00,-384506.4,2000.0,ccw 2006.173.16:26:46.14#flagr#flagr/antenna,new-source 2006.173.16:26:46.14:checkk5 2006.173.16:26:46.56/chk_autoobs//k5ts1/ autoobs is running! 2006.173.16:26:46.95/chk_autoobs//k5ts2/ autoobs is running! 2006.173.16:26:47.34/chk_autoobs//k5ts3/ autoobs is running! 2006.173.16:26:47.74/chk_autoobs//k5ts4/ autoobs is running! 2006.173.16:26:48.44/chk_obsdata//k5ts1/T1731618??a.dat file size is correct (nominal:2080MB, actual:2076MB). 2006.173.16:26:49.16/chk_obsdata//k5ts2/T1731618??b.dat file size is correct (nominal:2080MB, actual:2076MB). 2006.173.16:26:49.86/chk_obsdata//k5ts3/T1731618??c.dat file size is correct (nominal:2080MB, actual:2076MB). 2006.173.16:26:50.58/chk_obsdata//k5ts4/T1731618??d.dat file size is correct (nominal:2080MB, actual:2076MB). 2006.173.16:26:51.31/k5log//k5ts1_log_newline 2006.173.16:26:52.02/k5log//k5ts2_log_newline 2006.173.16:26:52.74/k5log//k5ts3_log_newline 2006.173.16:26:53.45/k5log//k5ts4_log_newline 2006.173.16:26:53.48/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.16:26:53.48:setupk4=1 2006.173.16:26:53.48$setupk4/echo=on 2006.173.16:26:53.48$setupk4/pcalon 2006.173.16:26:53.48$pcalon/"no phase cal control is implemented here 2006.173.16:26:53.48$setupk4/"tpicd=stop 2006.173.16:26:53.48$setupk4/"rec=synch_on 2006.173.16:26:53.48$setupk4/"rec_mode=128 2006.173.16:26:53.48$setupk4/!* 2006.173.16:26:53.48$setupk4/recpk4 2006.173.16:26:53.48$recpk4/recpatch= 2006.173.16:26:53.48$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.16:26:53.48$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.16:26:53.48$setupk4/vck44 2006.173.16:26:53.48$vck44/valo=1,524.99 2006.173.16:26:53.48#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.16:26:53.48#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.16:26:53.48#ibcon#ireg 17 cls_cnt 0 2006.173.16:26:53.48#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.16:26:53.48#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.16:26:53.48#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.16:26:53.48#ibcon#enter wrdev, iclass 12, count 0 2006.173.16:26:53.48#ibcon#first serial, iclass 12, count 0 2006.173.16:26:53.48#ibcon#enter sib2, iclass 12, count 0 2006.173.16:26:53.48#ibcon#flushed, iclass 12, count 0 2006.173.16:26:53.48#ibcon#about to write, iclass 12, count 0 2006.173.16:26:53.48#ibcon#wrote, iclass 12, count 0 2006.173.16:26:53.48#ibcon#about to read 3, iclass 12, count 0 2006.173.16:26:53.50#ibcon#read 3, iclass 12, count 0 2006.173.16:26:53.50#ibcon#about to read 4, iclass 12, count 0 2006.173.16:26:53.50#ibcon#read 4, iclass 12, count 0 2006.173.16:26:53.50#ibcon#about to read 5, iclass 12, count 0 2006.173.16:26:53.50#ibcon#read 5, iclass 12, count 0 2006.173.16:26:53.50#ibcon#about to read 6, iclass 12, count 0 2006.173.16:26:53.50#ibcon#read 6, iclass 12, count 0 2006.173.16:26:53.50#ibcon#end of sib2, iclass 12, count 0 2006.173.16:26:53.50#ibcon#*mode == 0, iclass 12, count 0 2006.173.16:26:53.50#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.16:26:53.50#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.16:26:53.50#ibcon#*before write, iclass 12, count 0 2006.173.16:26:53.50#ibcon#enter sib2, iclass 12, count 0 2006.173.16:26:53.50#ibcon#flushed, iclass 12, count 0 2006.173.16:26:53.50#ibcon#about to write, iclass 12, count 0 2006.173.16:26:53.50#ibcon#wrote, iclass 12, count 0 2006.173.16:26:53.50#ibcon#about to read 3, iclass 12, count 0 2006.173.16:26:53.55#ibcon#read 3, iclass 12, count 0 2006.173.16:26:53.55#ibcon#about to read 4, iclass 12, count 0 2006.173.16:26:53.55#ibcon#read 4, iclass 12, count 0 2006.173.16:26:53.55#ibcon#about to read 5, iclass 12, count 0 2006.173.16:26:53.55#ibcon#read 5, iclass 12, count 0 2006.173.16:26:53.55#ibcon#about to read 6, iclass 12, count 0 2006.173.16:26:53.55#ibcon#read 6, iclass 12, count 0 2006.173.16:26:53.55#ibcon#end of sib2, iclass 12, count 0 2006.173.16:26:53.55#ibcon#*after write, iclass 12, count 0 2006.173.16:26:53.55#ibcon#*before return 0, iclass 12, count 0 2006.173.16:26:53.55#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.16:26:53.55#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.16:26:53.55#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.16:26:53.55#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.16:26:53.55$vck44/va=1,7 2006.173.16:26:53.55#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.16:26:53.55#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.16:26:53.55#ibcon#ireg 11 cls_cnt 2 2006.173.16:26:53.55#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.16:26:53.55#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.16:26:53.55#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.16:26:53.55#ibcon#enter wrdev, iclass 14, count 2 2006.173.16:26:53.55#ibcon#first serial, iclass 14, count 2 2006.173.16:26:53.55#ibcon#enter sib2, iclass 14, count 2 2006.173.16:26:53.55#ibcon#flushed, iclass 14, count 2 2006.173.16:26:53.55#ibcon#about to write, iclass 14, count 2 2006.173.16:26:53.55#ibcon#wrote, iclass 14, count 2 2006.173.16:26:53.55#ibcon#about to read 3, iclass 14, count 2 2006.173.16:26:53.57#ibcon#read 3, iclass 14, count 2 2006.173.16:26:53.57#ibcon#about to read 4, iclass 14, count 2 2006.173.16:26:53.57#ibcon#read 4, iclass 14, count 2 2006.173.16:26:53.57#ibcon#about to read 5, iclass 14, count 2 2006.173.16:26:53.57#ibcon#read 5, iclass 14, count 2 2006.173.16:26:53.57#ibcon#about to read 6, iclass 14, count 2 2006.173.16:26:53.57#ibcon#read 6, iclass 14, count 2 2006.173.16:26:53.57#ibcon#end of sib2, iclass 14, count 2 2006.173.16:26:53.57#ibcon#*mode == 0, iclass 14, count 2 2006.173.16:26:53.57#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.16:26:53.57#ibcon#[25=AT01-07\r\n] 2006.173.16:26:53.57#ibcon#*before write, iclass 14, count 2 2006.173.16:26:53.57#ibcon#enter sib2, iclass 14, count 2 2006.173.16:26:53.57#ibcon#flushed, iclass 14, count 2 2006.173.16:26:53.57#ibcon#about to write, iclass 14, count 2 2006.173.16:26:53.57#ibcon#wrote, iclass 14, count 2 2006.173.16:26:53.57#ibcon#about to read 3, iclass 14, count 2 2006.173.16:26:53.60#ibcon#read 3, iclass 14, count 2 2006.173.16:26:53.60#ibcon#about to read 4, iclass 14, count 2 2006.173.16:26:53.60#ibcon#read 4, iclass 14, count 2 2006.173.16:26:53.60#ibcon#about to read 5, iclass 14, count 2 2006.173.16:26:53.60#ibcon#read 5, iclass 14, count 2 2006.173.16:26:53.60#ibcon#about to read 6, iclass 14, count 2 2006.173.16:26:53.60#ibcon#read 6, iclass 14, count 2 2006.173.16:26:53.60#ibcon#end of sib2, iclass 14, count 2 2006.173.16:26:53.60#ibcon#*after write, iclass 14, count 2 2006.173.16:26:53.60#ibcon#*before return 0, iclass 14, count 2 2006.173.16:26:53.60#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.16:26:53.60#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.16:26:53.60#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.16:26:53.60#ibcon#ireg 7 cls_cnt 0 2006.173.16:26:53.60#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.16:26:53.72#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.16:26:53.72#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.16:26:53.72#ibcon#enter wrdev, iclass 14, count 0 2006.173.16:26:53.72#ibcon#first serial, iclass 14, count 0 2006.173.16:26:53.72#ibcon#enter sib2, iclass 14, count 0 2006.173.16:26:53.72#ibcon#flushed, iclass 14, count 0 2006.173.16:26:53.72#ibcon#about to write, iclass 14, count 0 2006.173.16:26:53.72#ibcon#wrote, iclass 14, count 0 2006.173.16:26:53.72#ibcon#about to read 3, iclass 14, count 0 2006.173.16:26:53.74#ibcon#read 3, iclass 14, count 0 2006.173.16:26:53.74#ibcon#about to read 4, iclass 14, count 0 2006.173.16:26:53.74#ibcon#read 4, iclass 14, count 0 2006.173.16:26:53.74#ibcon#about to read 5, iclass 14, count 0 2006.173.16:26:53.74#ibcon#read 5, iclass 14, count 0 2006.173.16:26:53.74#ibcon#about to read 6, iclass 14, count 0 2006.173.16:26:53.74#ibcon#read 6, iclass 14, count 0 2006.173.16:26:53.74#ibcon#end of sib2, iclass 14, count 0 2006.173.16:26:53.74#ibcon#*mode == 0, iclass 14, count 0 2006.173.16:26:53.74#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.16:26:53.74#ibcon#[25=USB\r\n] 2006.173.16:26:53.74#ibcon#*before write, iclass 14, count 0 2006.173.16:26:53.74#ibcon#enter sib2, iclass 14, count 0 2006.173.16:26:53.74#ibcon#flushed, iclass 14, count 0 2006.173.16:26:53.74#ibcon#about to write, iclass 14, count 0 2006.173.16:26:53.74#ibcon#wrote, iclass 14, count 0 2006.173.16:26:53.74#ibcon#about to read 3, iclass 14, count 0 2006.173.16:26:53.77#ibcon#read 3, iclass 14, count 0 2006.173.16:26:53.77#ibcon#about to read 4, iclass 14, count 0 2006.173.16:26:53.77#ibcon#read 4, iclass 14, count 0 2006.173.16:26:53.77#ibcon#about to read 5, iclass 14, count 0 2006.173.16:26:53.77#ibcon#read 5, iclass 14, count 0 2006.173.16:26:53.77#ibcon#about to read 6, iclass 14, count 0 2006.173.16:26:53.77#ibcon#read 6, iclass 14, count 0 2006.173.16:26:53.77#ibcon#end of sib2, iclass 14, count 0 2006.173.16:26:53.77#ibcon#*after write, iclass 14, count 0 2006.173.16:26:53.77#ibcon#*before return 0, iclass 14, count 0 2006.173.16:26:53.77#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.16:26:53.77#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.16:26:53.77#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.16:26:53.77#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.16:26:53.77$vck44/valo=2,534.99 2006.173.16:26:53.77#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.16:26:53.77#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.16:26:53.77#ibcon#ireg 17 cls_cnt 0 2006.173.16:26:53.77#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.16:26:53.77#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.16:26:53.77#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.16:26:53.77#ibcon#enter wrdev, iclass 16, count 0 2006.173.16:26:53.77#ibcon#first serial, iclass 16, count 0 2006.173.16:26:53.77#ibcon#enter sib2, iclass 16, count 0 2006.173.16:26:53.77#ibcon#flushed, iclass 16, count 0 2006.173.16:26:53.77#ibcon#about to write, iclass 16, count 0 2006.173.16:26:53.77#ibcon#wrote, iclass 16, count 0 2006.173.16:26:53.77#ibcon#about to read 3, iclass 16, count 0 2006.173.16:26:53.79#ibcon#read 3, iclass 16, count 0 2006.173.16:26:53.79#ibcon#about to read 4, iclass 16, count 0 2006.173.16:26:53.79#ibcon#read 4, iclass 16, count 0 2006.173.16:26:53.79#ibcon#about to read 5, iclass 16, count 0 2006.173.16:26:53.79#ibcon#read 5, iclass 16, count 0 2006.173.16:26:53.79#ibcon#about to read 6, iclass 16, count 0 2006.173.16:26:53.79#ibcon#read 6, iclass 16, count 0 2006.173.16:26:53.79#ibcon#end of sib2, iclass 16, count 0 2006.173.16:26:53.79#ibcon#*mode == 0, iclass 16, count 0 2006.173.16:26:53.79#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.16:26:53.79#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.16:26:53.79#ibcon#*before write, iclass 16, count 0 2006.173.16:26:53.79#ibcon#enter sib2, iclass 16, count 0 2006.173.16:26:53.79#ibcon#flushed, iclass 16, count 0 2006.173.16:26:53.79#ibcon#about to write, iclass 16, count 0 2006.173.16:26:53.79#ibcon#wrote, iclass 16, count 0 2006.173.16:26:53.79#ibcon#about to read 3, iclass 16, count 0 2006.173.16:26:53.83#ibcon#read 3, iclass 16, count 0 2006.173.16:26:53.83#ibcon#about to read 4, iclass 16, count 0 2006.173.16:26:53.83#ibcon#read 4, iclass 16, count 0 2006.173.16:26:53.83#ibcon#about to read 5, iclass 16, count 0 2006.173.16:26:53.83#ibcon#read 5, iclass 16, count 0 2006.173.16:26:53.83#ibcon#about to read 6, iclass 16, count 0 2006.173.16:26:53.83#ibcon#read 6, iclass 16, count 0 2006.173.16:26:53.83#ibcon#end of sib2, iclass 16, count 0 2006.173.16:26:53.83#ibcon#*after write, iclass 16, count 0 2006.173.16:26:53.83#ibcon#*before return 0, iclass 16, count 0 2006.173.16:26:53.83#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.16:26:53.83#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.16:26:53.83#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.16:26:53.83#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.16:26:53.83$vck44/va=2,6 2006.173.16:26:53.83#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.16:26:53.83#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.16:26:53.83#ibcon#ireg 11 cls_cnt 2 2006.173.16:26:53.83#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.16:26:53.89#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.16:26:53.89#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.16:26:53.89#ibcon#enter wrdev, iclass 18, count 2 2006.173.16:26:53.89#ibcon#first serial, iclass 18, count 2 2006.173.16:26:53.89#ibcon#enter sib2, iclass 18, count 2 2006.173.16:26:53.89#ibcon#flushed, iclass 18, count 2 2006.173.16:26:53.89#ibcon#about to write, iclass 18, count 2 2006.173.16:26:53.89#ibcon#wrote, iclass 18, count 2 2006.173.16:26:53.89#ibcon#about to read 3, iclass 18, count 2 2006.173.16:26:53.91#ibcon#read 3, iclass 18, count 2 2006.173.16:26:53.91#ibcon#about to read 4, iclass 18, count 2 2006.173.16:26:53.91#ibcon#read 4, iclass 18, count 2 2006.173.16:26:53.91#ibcon#about to read 5, iclass 18, count 2 2006.173.16:26:53.91#ibcon#read 5, iclass 18, count 2 2006.173.16:26:53.91#ibcon#about to read 6, iclass 18, count 2 2006.173.16:26:53.91#ibcon#read 6, iclass 18, count 2 2006.173.16:26:53.91#ibcon#end of sib2, iclass 18, count 2 2006.173.16:26:53.91#ibcon#*mode == 0, iclass 18, count 2 2006.173.16:26:53.91#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.16:26:53.91#ibcon#[25=AT02-06\r\n] 2006.173.16:26:53.91#ibcon#*before write, iclass 18, count 2 2006.173.16:26:53.91#ibcon#enter sib2, iclass 18, count 2 2006.173.16:26:53.91#ibcon#flushed, iclass 18, count 2 2006.173.16:26:53.91#ibcon#about to write, iclass 18, count 2 2006.173.16:26:53.91#ibcon#wrote, iclass 18, count 2 2006.173.16:26:53.91#ibcon#about to read 3, iclass 18, count 2 2006.173.16:26:53.94#ibcon#read 3, iclass 18, count 2 2006.173.16:26:53.94#ibcon#about to read 4, iclass 18, count 2 2006.173.16:26:53.94#ibcon#read 4, iclass 18, count 2 2006.173.16:26:53.94#ibcon#about to read 5, iclass 18, count 2 2006.173.16:26:53.94#ibcon#read 5, iclass 18, count 2 2006.173.16:26:53.94#ibcon#about to read 6, iclass 18, count 2 2006.173.16:26:53.94#ibcon#read 6, iclass 18, count 2 2006.173.16:26:53.94#ibcon#end of sib2, iclass 18, count 2 2006.173.16:26:53.94#ibcon#*after write, iclass 18, count 2 2006.173.16:26:53.94#ibcon#*before return 0, iclass 18, count 2 2006.173.16:26:53.94#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.16:26:53.94#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.16:26:53.94#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.16:26:53.94#ibcon#ireg 7 cls_cnt 0 2006.173.16:26:53.94#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.16:26:54.06#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.16:26:54.06#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.16:26:54.06#ibcon#enter wrdev, iclass 18, count 0 2006.173.16:26:54.06#ibcon#first serial, iclass 18, count 0 2006.173.16:26:54.06#ibcon#enter sib2, iclass 18, count 0 2006.173.16:26:54.06#ibcon#flushed, iclass 18, count 0 2006.173.16:26:54.06#ibcon#about to write, iclass 18, count 0 2006.173.16:26:54.06#ibcon#wrote, iclass 18, count 0 2006.173.16:26:54.06#ibcon#about to read 3, iclass 18, count 0 2006.173.16:26:54.08#ibcon#read 3, iclass 18, count 0 2006.173.16:26:54.08#ibcon#about to read 4, iclass 18, count 0 2006.173.16:26:54.08#ibcon#read 4, iclass 18, count 0 2006.173.16:26:54.08#ibcon#about to read 5, iclass 18, count 0 2006.173.16:26:54.08#ibcon#read 5, iclass 18, count 0 2006.173.16:26:54.08#ibcon#about to read 6, iclass 18, count 0 2006.173.16:26:54.08#ibcon#read 6, iclass 18, count 0 2006.173.16:26:54.08#ibcon#end of sib2, iclass 18, count 0 2006.173.16:26:54.08#ibcon#*mode == 0, iclass 18, count 0 2006.173.16:26:54.08#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.16:26:54.08#ibcon#[25=USB\r\n] 2006.173.16:26:54.08#ibcon#*before write, iclass 18, count 0 2006.173.16:26:54.08#ibcon#enter sib2, iclass 18, count 0 2006.173.16:26:54.08#ibcon#flushed, iclass 18, count 0 2006.173.16:26:54.08#ibcon#about to write, iclass 18, count 0 2006.173.16:26:54.08#ibcon#wrote, iclass 18, count 0 2006.173.16:26:54.08#ibcon#about to read 3, iclass 18, count 0 2006.173.16:26:54.11#ibcon#read 3, iclass 18, count 0 2006.173.16:26:54.11#ibcon#about to read 4, iclass 18, count 0 2006.173.16:26:54.11#ibcon#read 4, iclass 18, count 0 2006.173.16:26:54.11#ibcon#about to read 5, iclass 18, count 0 2006.173.16:26:54.11#ibcon#read 5, iclass 18, count 0 2006.173.16:26:54.11#ibcon#about to read 6, iclass 18, count 0 2006.173.16:26:54.11#ibcon#read 6, iclass 18, count 0 2006.173.16:26:54.11#ibcon#end of sib2, iclass 18, count 0 2006.173.16:26:54.11#ibcon#*after write, iclass 18, count 0 2006.173.16:26:54.11#ibcon#*before return 0, iclass 18, count 0 2006.173.16:26:54.11#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.16:26:54.11#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.16:26:54.11#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.16:26:54.11#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.16:26:54.11$vck44/valo=3,564.99 2006.173.16:26:54.11#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.16:26:54.11#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.16:26:54.11#ibcon#ireg 17 cls_cnt 0 2006.173.16:26:54.11#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.16:26:54.11#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.16:26:54.11#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.16:26:54.11#ibcon#enter wrdev, iclass 20, count 0 2006.173.16:26:54.11#ibcon#first serial, iclass 20, count 0 2006.173.16:26:54.11#ibcon#enter sib2, iclass 20, count 0 2006.173.16:26:54.11#ibcon#flushed, iclass 20, count 0 2006.173.16:26:54.11#ibcon#about to write, iclass 20, count 0 2006.173.16:26:54.11#ibcon#wrote, iclass 20, count 0 2006.173.16:26:54.11#ibcon#about to read 3, iclass 20, count 0 2006.173.16:26:54.13#ibcon#read 3, iclass 20, count 0 2006.173.16:26:54.13#ibcon#about to read 4, iclass 20, count 0 2006.173.16:26:54.13#ibcon#read 4, iclass 20, count 0 2006.173.16:26:54.13#ibcon#about to read 5, iclass 20, count 0 2006.173.16:26:54.13#ibcon#read 5, iclass 20, count 0 2006.173.16:26:54.13#ibcon#about to read 6, iclass 20, count 0 2006.173.16:26:54.13#ibcon#read 6, iclass 20, count 0 2006.173.16:26:54.13#ibcon#end of sib2, iclass 20, count 0 2006.173.16:26:54.13#ibcon#*mode == 0, iclass 20, count 0 2006.173.16:26:54.13#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.16:26:54.13#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.16:26:54.13#ibcon#*before write, iclass 20, count 0 2006.173.16:26:54.13#ibcon#enter sib2, iclass 20, count 0 2006.173.16:26:54.13#ibcon#flushed, iclass 20, count 0 2006.173.16:26:54.13#ibcon#about to write, iclass 20, count 0 2006.173.16:26:54.13#ibcon#wrote, iclass 20, count 0 2006.173.16:26:54.13#ibcon#about to read 3, iclass 20, count 0 2006.173.16:26:54.17#ibcon#read 3, iclass 20, count 0 2006.173.16:26:54.17#ibcon#about to read 4, iclass 20, count 0 2006.173.16:26:54.17#ibcon#read 4, iclass 20, count 0 2006.173.16:26:54.17#ibcon#about to read 5, iclass 20, count 0 2006.173.16:26:54.17#ibcon#read 5, iclass 20, count 0 2006.173.16:26:54.17#ibcon#about to read 6, iclass 20, count 0 2006.173.16:26:54.17#ibcon#read 6, iclass 20, count 0 2006.173.16:26:54.17#ibcon#end of sib2, iclass 20, count 0 2006.173.16:26:54.17#ibcon#*after write, iclass 20, count 0 2006.173.16:26:54.17#ibcon#*before return 0, iclass 20, count 0 2006.173.16:26:54.17#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.16:26:54.17#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.16:26:54.17#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.16:26:54.17#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.16:26:54.17$vck44/va=3,5 2006.173.16:26:54.17#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.16:26:54.17#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.16:26:54.17#ibcon#ireg 11 cls_cnt 2 2006.173.16:26:54.17#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.16:26:54.23#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.16:26:54.23#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.16:26:54.23#ibcon#enter wrdev, iclass 22, count 2 2006.173.16:26:54.23#ibcon#first serial, iclass 22, count 2 2006.173.16:26:54.23#ibcon#enter sib2, iclass 22, count 2 2006.173.16:26:54.23#ibcon#flushed, iclass 22, count 2 2006.173.16:26:54.23#ibcon#about to write, iclass 22, count 2 2006.173.16:26:54.23#ibcon#wrote, iclass 22, count 2 2006.173.16:26:54.23#ibcon#about to read 3, iclass 22, count 2 2006.173.16:26:54.25#ibcon#read 3, iclass 22, count 2 2006.173.16:26:54.25#ibcon#about to read 4, iclass 22, count 2 2006.173.16:26:54.25#ibcon#read 4, iclass 22, count 2 2006.173.16:26:54.25#ibcon#about to read 5, iclass 22, count 2 2006.173.16:26:54.25#ibcon#read 5, iclass 22, count 2 2006.173.16:26:54.25#ibcon#about to read 6, iclass 22, count 2 2006.173.16:26:54.25#ibcon#read 6, iclass 22, count 2 2006.173.16:26:54.25#ibcon#end of sib2, iclass 22, count 2 2006.173.16:26:54.25#ibcon#*mode == 0, iclass 22, count 2 2006.173.16:26:54.25#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.16:26:54.25#ibcon#[25=AT03-05\r\n] 2006.173.16:26:54.25#ibcon#*before write, iclass 22, count 2 2006.173.16:26:54.25#ibcon#enter sib2, iclass 22, count 2 2006.173.16:26:54.25#ibcon#flushed, iclass 22, count 2 2006.173.16:26:54.25#ibcon#about to write, iclass 22, count 2 2006.173.16:26:54.25#ibcon#wrote, iclass 22, count 2 2006.173.16:26:54.25#ibcon#about to read 3, iclass 22, count 2 2006.173.16:26:54.28#ibcon#read 3, iclass 22, count 2 2006.173.16:26:54.28#ibcon#about to read 4, iclass 22, count 2 2006.173.16:26:54.28#ibcon#read 4, iclass 22, count 2 2006.173.16:26:54.28#ibcon#about to read 5, iclass 22, count 2 2006.173.16:26:54.28#ibcon#read 5, iclass 22, count 2 2006.173.16:26:54.28#ibcon#about to read 6, iclass 22, count 2 2006.173.16:26:54.28#ibcon#read 6, iclass 22, count 2 2006.173.16:26:54.28#ibcon#end of sib2, iclass 22, count 2 2006.173.16:26:54.28#ibcon#*after write, iclass 22, count 2 2006.173.16:26:54.28#ibcon#*before return 0, iclass 22, count 2 2006.173.16:26:54.28#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.16:26:54.28#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.16:26:54.28#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.16:26:54.28#ibcon#ireg 7 cls_cnt 0 2006.173.16:26:54.28#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.16:26:54.40#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.16:26:54.40#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.16:26:54.40#ibcon#enter wrdev, iclass 22, count 0 2006.173.16:26:54.40#ibcon#first serial, iclass 22, count 0 2006.173.16:26:54.40#ibcon#enter sib2, iclass 22, count 0 2006.173.16:26:54.40#ibcon#flushed, iclass 22, count 0 2006.173.16:26:54.40#ibcon#about to write, iclass 22, count 0 2006.173.16:26:54.40#ibcon#wrote, iclass 22, count 0 2006.173.16:26:54.40#ibcon#about to read 3, iclass 22, count 0 2006.173.16:26:54.42#ibcon#read 3, iclass 22, count 0 2006.173.16:26:54.42#ibcon#about to read 4, iclass 22, count 0 2006.173.16:26:54.42#ibcon#read 4, iclass 22, count 0 2006.173.16:26:54.42#ibcon#about to read 5, iclass 22, count 0 2006.173.16:26:54.42#ibcon#read 5, iclass 22, count 0 2006.173.16:26:54.42#ibcon#about to read 6, iclass 22, count 0 2006.173.16:26:54.42#ibcon#read 6, iclass 22, count 0 2006.173.16:26:54.42#ibcon#end of sib2, iclass 22, count 0 2006.173.16:26:54.42#ibcon#*mode == 0, iclass 22, count 0 2006.173.16:26:54.42#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.16:26:54.42#ibcon#[25=USB\r\n] 2006.173.16:26:54.42#ibcon#*before write, iclass 22, count 0 2006.173.16:26:54.42#ibcon#enter sib2, iclass 22, count 0 2006.173.16:26:54.42#ibcon#flushed, iclass 22, count 0 2006.173.16:26:54.42#ibcon#about to write, iclass 22, count 0 2006.173.16:26:54.42#ibcon#wrote, iclass 22, count 0 2006.173.16:26:54.42#ibcon#about to read 3, iclass 22, count 0 2006.173.16:26:54.45#ibcon#read 3, iclass 22, count 0 2006.173.16:26:54.45#ibcon#about to read 4, iclass 22, count 0 2006.173.16:26:54.45#ibcon#read 4, iclass 22, count 0 2006.173.16:26:54.45#ibcon#about to read 5, iclass 22, count 0 2006.173.16:26:54.45#ibcon#read 5, iclass 22, count 0 2006.173.16:26:54.45#ibcon#about to read 6, iclass 22, count 0 2006.173.16:26:54.45#ibcon#read 6, iclass 22, count 0 2006.173.16:26:54.45#ibcon#end of sib2, iclass 22, count 0 2006.173.16:26:54.45#ibcon#*after write, iclass 22, count 0 2006.173.16:26:54.45#ibcon#*before return 0, iclass 22, count 0 2006.173.16:26:54.45#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.16:26:54.45#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.16:26:54.45#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.16:26:54.45#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.16:26:54.45$vck44/valo=4,624.99 2006.173.16:26:54.45#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.16:26:54.45#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.16:26:54.45#ibcon#ireg 17 cls_cnt 0 2006.173.16:26:54.45#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.16:26:54.45#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.16:26:54.45#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.16:26:54.45#ibcon#enter wrdev, iclass 24, count 0 2006.173.16:26:54.45#ibcon#first serial, iclass 24, count 0 2006.173.16:26:54.45#ibcon#enter sib2, iclass 24, count 0 2006.173.16:26:54.45#ibcon#flushed, iclass 24, count 0 2006.173.16:26:54.45#ibcon#about to write, iclass 24, count 0 2006.173.16:26:54.45#ibcon#wrote, iclass 24, count 0 2006.173.16:26:54.45#ibcon#about to read 3, iclass 24, count 0 2006.173.16:26:54.47#ibcon#read 3, iclass 24, count 0 2006.173.16:26:54.47#ibcon#about to read 4, iclass 24, count 0 2006.173.16:26:54.47#ibcon#read 4, iclass 24, count 0 2006.173.16:26:54.47#ibcon#about to read 5, iclass 24, count 0 2006.173.16:26:54.47#ibcon#read 5, iclass 24, count 0 2006.173.16:26:54.47#ibcon#about to read 6, iclass 24, count 0 2006.173.16:26:54.47#ibcon#read 6, iclass 24, count 0 2006.173.16:26:54.47#ibcon#end of sib2, iclass 24, count 0 2006.173.16:26:54.47#ibcon#*mode == 0, iclass 24, count 0 2006.173.16:26:54.47#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.16:26:54.47#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.16:26:54.47#ibcon#*before write, iclass 24, count 0 2006.173.16:26:54.47#ibcon#enter sib2, iclass 24, count 0 2006.173.16:26:54.47#ibcon#flushed, iclass 24, count 0 2006.173.16:26:54.47#ibcon#about to write, iclass 24, count 0 2006.173.16:26:54.47#ibcon#wrote, iclass 24, count 0 2006.173.16:26:54.47#ibcon#about to read 3, iclass 24, count 0 2006.173.16:26:54.51#ibcon#read 3, iclass 24, count 0 2006.173.16:26:54.51#ibcon#about to read 4, iclass 24, count 0 2006.173.16:26:54.51#ibcon#read 4, iclass 24, count 0 2006.173.16:26:54.51#ibcon#about to read 5, iclass 24, count 0 2006.173.16:26:54.51#ibcon#read 5, iclass 24, count 0 2006.173.16:26:54.51#ibcon#about to read 6, iclass 24, count 0 2006.173.16:26:54.51#ibcon#read 6, iclass 24, count 0 2006.173.16:26:54.51#ibcon#end of sib2, iclass 24, count 0 2006.173.16:26:54.51#ibcon#*after write, iclass 24, count 0 2006.173.16:26:54.51#ibcon#*before return 0, iclass 24, count 0 2006.173.16:26:54.51#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.16:26:54.51#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.16:26:54.51#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.16:26:54.51#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.16:26:54.51$vck44/va=4,6 2006.173.16:26:54.51#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.16:26:54.51#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.16:26:54.51#ibcon#ireg 11 cls_cnt 2 2006.173.16:26:54.51#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.16:26:54.57#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.16:26:54.57#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.16:26:54.57#ibcon#enter wrdev, iclass 26, count 2 2006.173.16:26:54.57#ibcon#first serial, iclass 26, count 2 2006.173.16:26:54.57#ibcon#enter sib2, iclass 26, count 2 2006.173.16:26:54.57#ibcon#flushed, iclass 26, count 2 2006.173.16:26:54.57#ibcon#about to write, iclass 26, count 2 2006.173.16:26:54.57#ibcon#wrote, iclass 26, count 2 2006.173.16:26:54.57#ibcon#about to read 3, iclass 26, count 2 2006.173.16:26:54.59#ibcon#read 3, iclass 26, count 2 2006.173.16:26:54.59#ibcon#about to read 4, iclass 26, count 2 2006.173.16:26:54.59#ibcon#read 4, iclass 26, count 2 2006.173.16:26:54.59#ibcon#about to read 5, iclass 26, count 2 2006.173.16:26:54.59#ibcon#read 5, iclass 26, count 2 2006.173.16:26:54.59#ibcon#about to read 6, iclass 26, count 2 2006.173.16:26:54.59#ibcon#read 6, iclass 26, count 2 2006.173.16:26:54.59#ibcon#end of sib2, iclass 26, count 2 2006.173.16:26:54.59#ibcon#*mode == 0, iclass 26, count 2 2006.173.16:26:54.59#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.16:26:54.59#ibcon#[25=AT04-06\r\n] 2006.173.16:26:54.59#ibcon#*before write, iclass 26, count 2 2006.173.16:26:54.59#ibcon#enter sib2, iclass 26, count 2 2006.173.16:26:54.59#ibcon#flushed, iclass 26, count 2 2006.173.16:26:54.59#ibcon#about to write, iclass 26, count 2 2006.173.16:26:54.59#ibcon#wrote, iclass 26, count 2 2006.173.16:26:54.59#ibcon#about to read 3, iclass 26, count 2 2006.173.16:26:54.62#ibcon#read 3, iclass 26, count 2 2006.173.16:26:54.62#ibcon#about to read 4, iclass 26, count 2 2006.173.16:26:54.62#ibcon#read 4, iclass 26, count 2 2006.173.16:26:54.62#ibcon#about to read 5, iclass 26, count 2 2006.173.16:26:54.62#ibcon#read 5, iclass 26, count 2 2006.173.16:26:54.62#ibcon#about to read 6, iclass 26, count 2 2006.173.16:26:54.62#ibcon#read 6, iclass 26, count 2 2006.173.16:26:54.62#ibcon#end of sib2, iclass 26, count 2 2006.173.16:26:54.62#ibcon#*after write, iclass 26, count 2 2006.173.16:26:54.62#ibcon#*before return 0, iclass 26, count 2 2006.173.16:26:54.62#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.16:26:54.62#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.16:26:54.62#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.16:26:54.62#ibcon#ireg 7 cls_cnt 0 2006.173.16:26:54.62#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.16:26:54.74#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.16:26:54.74#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.16:26:54.74#ibcon#enter wrdev, iclass 26, count 0 2006.173.16:26:54.74#ibcon#first serial, iclass 26, count 0 2006.173.16:26:54.74#ibcon#enter sib2, iclass 26, count 0 2006.173.16:26:54.74#ibcon#flushed, iclass 26, count 0 2006.173.16:26:54.74#ibcon#about to write, iclass 26, count 0 2006.173.16:26:54.74#ibcon#wrote, iclass 26, count 0 2006.173.16:26:54.74#ibcon#about to read 3, iclass 26, count 0 2006.173.16:26:54.76#ibcon#read 3, iclass 26, count 0 2006.173.16:26:54.76#ibcon#about to read 4, iclass 26, count 0 2006.173.16:26:54.76#ibcon#read 4, iclass 26, count 0 2006.173.16:26:54.76#ibcon#about to read 5, iclass 26, count 0 2006.173.16:26:54.76#ibcon#read 5, iclass 26, count 0 2006.173.16:26:54.76#ibcon#about to read 6, iclass 26, count 0 2006.173.16:26:54.76#ibcon#read 6, iclass 26, count 0 2006.173.16:26:54.76#ibcon#end of sib2, iclass 26, count 0 2006.173.16:26:54.76#ibcon#*mode == 0, iclass 26, count 0 2006.173.16:26:54.76#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.16:26:54.76#ibcon#[25=USB\r\n] 2006.173.16:26:54.76#ibcon#*before write, iclass 26, count 0 2006.173.16:26:54.76#ibcon#enter sib2, iclass 26, count 0 2006.173.16:26:54.76#ibcon#flushed, iclass 26, count 0 2006.173.16:26:54.76#ibcon#about to write, iclass 26, count 0 2006.173.16:26:54.76#ibcon#wrote, iclass 26, count 0 2006.173.16:26:54.76#ibcon#about to read 3, iclass 26, count 0 2006.173.16:26:54.79#ibcon#read 3, iclass 26, count 0 2006.173.16:26:54.79#ibcon#about to read 4, iclass 26, count 0 2006.173.16:26:54.79#ibcon#read 4, iclass 26, count 0 2006.173.16:26:54.79#ibcon#about to read 5, iclass 26, count 0 2006.173.16:26:54.79#ibcon#read 5, iclass 26, count 0 2006.173.16:26:54.79#ibcon#about to read 6, iclass 26, count 0 2006.173.16:26:54.79#ibcon#read 6, iclass 26, count 0 2006.173.16:26:54.79#ibcon#end of sib2, iclass 26, count 0 2006.173.16:26:54.79#ibcon#*after write, iclass 26, count 0 2006.173.16:26:54.79#ibcon#*before return 0, iclass 26, count 0 2006.173.16:26:54.79#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.16:26:54.79#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.16:26:54.79#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.16:26:54.79#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.16:26:54.79$vck44/valo=5,734.99 2006.173.16:26:54.79#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.16:26:54.79#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.16:26:54.79#ibcon#ireg 17 cls_cnt 0 2006.173.16:26:54.79#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.16:26:54.79#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.16:26:54.79#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.16:26:54.79#ibcon#enter wrdev, iclass 28, count 0 2006.173.16:26:54.79#ibcon#first serial, iclass 28, count 0 2006.173.16:26:54.79#ibcon#enter sib2, iclass 28, count 0 2006.173.16:26:54.79#ibcon#flushed, iclass 28, count 0 2006.173.16:26:54.79#ibcon#about to write, iclass 28, count 0 2006.173.16:26:54.79#ibcon#wrote, iclass 28, count 0 2006.173.16:26:54.79#ibcon#about to read 3, iclass 28, count 0 2006.173.16:26:54.81#ibcon#read 3, iclass 28, count 0 2006.173.16:26:54.81#ibcon#about to read 4, iclass 28, count 0 2006.173.16:26:54.81#ibcon#read 4, iclass 28, count 0 2006.173.16:26:54.81#ibcon#about to read 5, iclass 28, count 0 2006.173.16:26:54.81#ibcon#read 5, iclass 28, count 0 2006.173.16:26:54.81#ibcon#about to read 6, iclass 28, count 0 2006.173.16:26:54.81#ibcon#read 6, iclass 28, count 0 2006.173.16:26:54.81#ibcon#end of sib2, iclass 28, count 0 2006.173.16:26:54.81#ibcon#*mode == 0, iclass 28, count 0 2006.173.16:26:54.81#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.16:26:54.81#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.16:26:54.81#ibcon#*before write, iclass 28, count 0 2006.173.16:26:54.81#ibcon#enter sib2, iclass 28, count 0 2006.173.16:26:54.81#ibcon#flushed, iclass 28, count 0 2006.173.16:26:54.81#ibcon#about to write, iclass 28, count 0 2006.173.16:26:54.81#ibcon#wrote, iclass 28, count 0 2006.173.16:26:54.81#ibcon#about to read 3, iclass 28, count 0 2006.173.16:26:54.85#ibcon#read 3, iclass 28, count 0 2006.173.16:26:54.85#ibcon#about to read 4, iclass 28, count 0 2006.173.16:26:54.85#ibcon#read 4, iclass 28, count 0 2006.173.16:26:54.85#ibcon#about to read 5, iclass 28, count 0 2006.173.16:26:54.85#ibcon#read 5, iclass 28, count 0 2006.173.16:26:54.85#ibcon#about to read 6, iclass 28, count 0 2006.173.16:26:54.85#ibcon#read 6, iclass 28, count 0 2006.173.16:26:54.85#ibcon#end of sib2, iclass 28, count 0 2006.173.16:26:54.85#ibcon#*after write, iclass 28, count 0 2006.173.16:26:54.85#ibcon#*before return 0, iclass 28, count 0 2006.173.16:26:54.85#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.16:26:54.85#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.16:26:54.85#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.16:26:54.85#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.16:26:54.85$vck44/va=5,4 2006.173.16:26:54.85#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.16:26:54.85#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.16:26:54.85#ibcon#ireg 11 cls_cnt 2 2006.173.16:26:54.85#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.16:26:54.91#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.16:26:54.91#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.16:26:54.91#ibcon#enter wrdev, iclass 30, count 2 2006.173.16:26:54.91#ibcon#first serial, iclass 30, count 2 2006.173.16:26:54.91#ibcon#enter sib2, iclass 30, count 2 2006.173.16:26:54.91#ibcon#flushed, iclass 30, count 2 2006.173.16:26:54.91#ibcon#about to write, iclass 30, count 2 2006.173.16:26:54.91#ibcon#wrote, iclass 30, count 2 2006.173.16:26:54.91#ibcon#about to read 3, iclass 30, count 2 2006.173.16:26:54.93#ibcon#read 3, iclass 30, count 2 2006.173.16:26:54.93#ibcon#about to read 4, iclass 30, count 2 2006.173.16:26:54.93#ibcon#read 4, iclass 30, count 2 2006.173.16:26:54.93#ibcon#about to read 5, iclass 30, count 2 2006.173.16:26:54.93#ibcon#read 5, iclass 30, count 2 2006.173.16:26:54.93#ibcon#about to read 6, iclass 30, count 2 2006.173.16:26:54.93#ibcon#read 6, iclass 30, count 2 2006.173.16:26:54.93#ibcon#end of sib2, iclass 30, count 2 2006.173.16:26:54.93#ibcon#*mode == 0, iclass 30, count 2 2006.173.16:26:54.93#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.16:26:54.93#ibcon#[25=AT05-04\r\n] 2006.173.16:26:54.93#ibcon#*before write, iclass 30, count 2 2006.173.16:26:54.93#ibcon#enter sib2, iclass 30, count 2 2006.173.16:26:54.93#ibcon#flushed, iclass 30, count 2 2006.173.16:26:54.93#ibcon#about to write, iclass 30, count 2 2006.173.16:26:54.93#ibcon#wrote, iclass 30, count 2 2006.173.16:26:54.93#ibcon#about to read 3, iclass 30, count 2 2006.173.16:26:54.96#ibcon#read 3, iclass 30, count 2 2006.173.16:26:54.96#ibcon#about to read 4, iclass 30, count 2 2006.173.16:26:54.96#ibcon#read 4, iclass 30, count 2 2006.173.16:26:54.96#ibcon#about to read 5, iclass 30, count 2 2006.173.16:26:54.96#ibcon#read 5, iclass 30, count 2 2006.173.16:26:54.96#ibcon#about to read 6, iclass 30, count 2 2006.173.16:26:54.96#ibcon#read 6, iclass 30, count 2 2006.173.16:26:54.96#ibcon#end of sib2, iclass 30, count 2 2006.173.16:26:54.96#ibcon#*after write, iclass 30, count 2 2006.173.16:26:54.96#ibcon#*before return 0, iclass 30, count 2 2006.173.16:26:54.96#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.16:26:54.96#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.16:26:54.96#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.16:26:54.96#ibcon#ireg 7 cls_cnt 0 2006.173.16:26:54.96#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.16:26:55.08#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.16:26:55.08#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.16:26:55.08#ibcon#enter wrdev, iclass 30, count 0 2006.173.16:26:55.08#ibcon#first serial, iclass 30, count 0 2006.173.16:26:55.08#ibcon#enter sib2, iclass 30, count 0 2006.173.16:26:55.08#ibcon#flushed, iclass 30, count 0 2006.173.16:26:55.08#ibcon#about to write, iclass 30, count 0 2006.173.16:26:55.08#ibcon#wrote, iclass 30, count 0 2006.173.16:26:55.08#ibcon#about to read 3, iclass 30, count 0 2006.173.16:26:55.10#ibcon#read 3, iclass 30, count 0 2006.173.16:26:55.10#ibcon#about to read 4, iclass 30, count 0 2006.173.16:26:55.10#ibcon#read 4, iclass 30, count 0 2006.173.16:26:55.10#ibcon#about to read 5, iclass 30, count 0 2006.173.16:26:55.10#ibcon#read 5, iclass 30, count 0 2006.173.16:26:55.10#ibcon#about to read 6, iclass 30, count 0 2006.173.16:26:55.10#ibcon#read 6, iclass 30, count 0 2006.173.16:26:55.10#ibcon#end of sib2, iclass 30, count 0 2006.173.16:26:55.10#ibcon#*mode == 0, iclass 30, count 0 2006.173.16:26:55.10#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.16:26:55.10#ibcon#[25=USB\r\n] 2006.173.16:26:55.10#ibcon#*before write, iclass 30, count 0 2006.173.16:26:55.10#ibcon#enter sib2, iclass 30, count 0 2006.173.16:26:55.10#ibcon#flushed, iclass 30, count 0 2006.173.16:26:55.10#ibcon#about to write, iclass 30, count 0 2006.173.16:26:55.10#ibcon#wrote, iclass 30, count 0 2006.173.16:26:55.10#ibcon#about to read 3, iclass 30, count 0 2006.173.16:26:55.13#ibcon#read 3, iclass 30, count 0 2006.173.16:26:55.13#ibcon#about to read 4, iclass 30, count 0 2006.173.16:26:55.13#ibcon#read 4, iclass 30, count 0 2006.173.16:26:55.13#ibcon#about to read 5, iclass 30, count 0 2006.173.16:26:55.13#ibcon#read 5, iclass 30, count 0 2006.173.16:26:55.13#ibcon#about to read 6, iclass 30, count 0 2006.173.16:26:55.13#ibcon#read 6, iclass 30, count 0 2006.173.16:26:55.13#ibcon#end of sib2, iclass 30, count 0 2006.173.16:26:55.13#ibcon#*after write, iclass 30, count 0 2006.173.16:26:55.13#ibcon#*before return 0, iclass 30, count 0 2006.173.16:26:55.13#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.16:26:55.13#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.16:26:55.13#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.16:26:55.13#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.16:26:55.13$vck44/valo=6,814.99 2006.173.16:26:55.13#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.16:26:55.13#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.16:26:55.13#ibcon#ireg 17 cls_cnt 0 2006.173.16:26:55.13#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.16:26:55.13#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.16:26:55.13#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.16:26:55.13#ibcon#enter wrdev, iclass 32, count 0 2006.173.16:26:55.13#ibcon#first serial, iclass 32, count 0 2006.173.16:26:55.13#ibcon#enter sib2, iclass 32, count 0 2006.173.16:26:55.13#ibcon#flushed, iclass 32, count 0 2006.173.16:26:55.13#ibcon#about to write, iclass 32, count 0 2006.173.16:26:55.13#ibcon#wrote, iclass 32, count 0 2006.173.16:26:55.13#ibcon#about to read 3, iclass 32, count 0 2006.173.16:26:55.15#ibcon#read 3, iclass 32, count 0 2006.173.16:26:55.15#ibcon#about to read 4, iclass 32, count 0 2006.173.16:26:55.15#ibcon#read 4, iclass 32, count 0 2006.173.16:26:55.15#ibcon#about to read 5, iclass 32, count 0 2006.173.16:26:55.15#ibcon#read 5, iclass 32, count 0 2006.173.16:26:55.15#ibcon#about to read 6, iclass 32, count 0 2006.173.16:26:55.15#ibcon#read 6, iclass 32, count 0 2006.173.16:26:55.15#ibcon#end of sib2, iclass 32, count 0 2006.173.16:26:55.15#ibcon#*mode == 0, iclass 32, count 0 2006.173.16:26:55.15#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.16:26:55.15#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.16:26:55.15#ibcon#*before write, iclass 32, count 0 2006.173.16:26:55.15#ibcon#enter sib2, iclass 32, count 0 2006.173.16:26:55.15#ibcon#flushed, iclass 32, count 0 2006.173.16:26:55.15#ibcon#about to write, iclass 32, count 0 2006.173.16:26:55.15#ibcon#wrote, iclass 32, count 0 2006.173.16:26:55.15#ibcon#about to read 3, iclass 32, count 0 2006.173.16:26:55.19#ibcon#read 3, iclass 32, count 0 2006.173.16:26:55.19#ibcon#about to read 4, iclass 32, count 0 2006.173.16:26:55.19#ibcon#read 4, iclass 32, count 0 2006.173.16:26:55.19#ibcon#about to read 5, iclass 32, count 0 2006.173.16:26:55.19#ibcon#read 5, iclass 32, count 0 2006.173.16:26:55.19#ibcon#about to read 6, iclass 32, count 0 2006.173.16:26:55.19#ibcon#read 6, iclass 32, count 0 2006.173.16:26:55.19#ibcon#end of sib2, iclass 32, count 0 2006.173.16:26:55.19#ibcon#*after write, iclass 32, count 0 2006.173.16:26:55.19#ibcon#*before return 0, iclass 32, count 0 2006.173.16:26:55.19#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.16:26:55.19#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.16:26:55.19#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.16:26:55.19#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.16:26:55.19$vck44/va=6,3 2006.173.16:26:55.19#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.16:26:55.19#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.16:26:55.19#ibcon#ireg 11 cls_cnt 2 2006.173.16:26:55.19#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.16:26:55.25#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.16:26:55.25#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.16:26:55.25#ibcon#enter wrdev, iclass 34, count 2 2006.173.16:26:55.25#ibcon#first serial, iclass 34, count 2 2006.173.16:26:55.25#ibcon#enter sib2, iclass 34, count 2 2006.173.16:26:55.25#ibcon#flushed, iclass 34, count 2 2006.173.16:26:55.25#ibcon#about to write, iclass 34, count 2 2006.173.16:26:55.25#ibcon#wrote, iclass 34, count 2 2006.173.16:26:55.25#ibcon#about to read 3, iclass 34, count 2 2006.173.16:26:55.27#ibcon#read 3, iclass 34, count 2 2006.173.16:26:55.27#ibcon#about to read 4, iclass 34, count 2 2006.173.16:26:55.27#ibcon#read 4, iclass 34, count 2 2006.173.16:26:55.27#ibcon#about to read 5, iclass 34, count 2 2006.173.16:26:55.27#ibcon#read 5, iclass 34, count 2 2006.173.16:26:55.27#ibcon#about to read 6, iclass 34, count 2 2006.173.16:26:55.27#ibcon#read 6, iclass 34, count 2 2006.173.16:26:55.27#ibcon#end of sib2, iclass 34, count 2 2006.173.16:26:55.27#ibcon#*mode == 0, iclass 34, count 2 2006.173.16:26:55.27#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.16:26:55.27#ibcon#[25=AT06-03\r\n] 2006.173.16:26:55.27#ibcon#*before write, iclass 34, count 2 2006.173.16:26:55.27#ibcon#enter sib2, iclass 34, count 2 2006.173.16:26:55.27#ibcon#flushed, iclass 34, count 2 2006.173.16:26:55.27#ibcon#about to write, iclass 34, count 2 2006.173.16:26:55.27#ibcon#wrote, iclass 34, count 2 2006.173.16:26:55.27#ibcon#about to read 3, iclass 34, count 2 2006.173.16:26:55.30#ibcon#read 3, iclass 34, count 2 2006.173.16:26:55.30#ibcon#about to read 4, iclass 34, count 2 2006.173.16:26:55.30#ibcon#read 4, iclass 34, count 2 2006.173.16:26:55.30#ibcon#about to read 5, iclass 34, count 2 2006.173.16:26:55.30#ibcon#read 5, iclass 34, count 2 2006.173.16:26:55.30#ibcon#about to read 6, iclass 34, count 2 2006.173.16:26:55.30#ibcon#read 6, iclass 34, count 2 2006.173.16:26:55.30#ibcon#end of sib2, iclass 34, count 2 2006.173.16:26:55.30#ibcon#*after write, iclass 34, count 2 2006.173.16:26:55.30#ibcon#*before return 0, iclass 34, count 2 2006.173.16:26:55.30#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.16:26:55.30#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.16:26:55.30#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.16:26:55.30#ibcon#ireg 7 cls_cnt 0 2006.173.16:26:55.30#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.16:26:55.42#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.16:26:55.42#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.16:26:55.42#ibcon#enter wrdev, iclass 34, count 0 2006.173.16:26:55.42#ibcon#first serial, iclass 34, count 0 2006.173.16:26:55.42#ibcon#enter sib2, iclass 34, count 0 2006.173.16:26:55.42#ibcon#flushed, iclass 34, count 0 2006.173.16:26:55.42#ibcon#about to write, iclass 34, count 0 2006.173.16:26:55.42#ibcon#wrote, iclass 34, count 0 2006.173.16:26:55.42#ibcon#about to read 3, iclass 34, count 0 2006.173.16:26:55.44#ibcon#read 3, iclass 34, count 0 2006.173.16:26:55.44#ibcon#about to read 4, iclass 34, count 0 2006.173.16:26:55.44#ibcon#read 4, iclass 34, count 0 2006.173.16:26:55.44#ibcon#about to read 5, iclass 34, count 0 2006.173.16:26:55.44#ibcon#read 5, iclass 34, count 0 2006.173.16:26:55.44#ibcon#about to read 6, iclass 34, count 0 2006.173.16:26:55.44#ibcon#read 6, iclass 34, count 0 2006.173.16:26:55.44#ibcon#end of sib2, iclass 34, count 0 2006.173.16:26:55.44#ibcon#*mode == 0, iclass 34, count 0 2006.173.16:26:55.44#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.16:26:55.44#ibcon#[25=USB\r\n] 2006.173.16:26:55.44#ibcon#*before write, iclass 34, count 0 2006.173.16:26:55.44#ibcon#enter sib2, iclass 34, count 0 2006.173.16:26:55.44#ibcon#flushed, iclass 34, count 0 2006.173.16:26:55.44#ibcon#about to write, iclass 34, count 0 2006.173.16:26:55.44#ibcon#wrote, iclass 34, count 0 2006.173.16:26:55.44#ibcon#about to read 3, iclass 34, count 0 2006.173.16:26:55.47#ibcon#read 3, iclass 34, count 0 2006.173.16:26:55.47#ibcon#about to read 4, iclass 34, count 0 2006.173.16:26:55.47#ibcon#read 4, iclass 34, count 0 2006.173.16:26:55.47#ibcon#about to read 5, iclass 34, count 0 2006.173.16:26:55.47#ibcon#read 5, iclass 34, count 0 2006.173.16:26:55.47#ibcon#about to read 6, iclass 34, count 0 2006.173.16:26:55.47#ibcon#read 6, iclass 34, count 0 2006.173.16:26:55.47#ibcon#end of sib2, iclass 34, count 0 2006.173.16:26:55.47#ibcon#*after write, iclass 34, count 0 2006.173.16:26:55.47#ibcon#*before return 0, iclass 34, count 0 2006.173.16:26:55.47#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.16:26:55.47#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.16:26:55.47#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.16:26:55.47#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.16:26:55.47$vck44/valo=7,864.99 2006.173.16:26:55.47#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.16:26:55.47#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.16:26:55.47#ibcon#ireg 17 cls_cnt 0 2006.173.16:26:55.47#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.16:26:55.47#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.16:26:55.47#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.16:26:55.47#ibcon#enter wrdev, iclass 36, count 0 2006.173.16:26:55.47#ibcon#first serial, iclass 36, count 0 2006.173.16:26:55.47#ibcon#enter sib2, iclass 36, count 0 2006.173.16:26:55.47#ibcon#flushed, iclass 36, count 0 2006.173.16:26:55.47#ibcon#about to write, iclass 36, count 0 2006.173.16:26:55.47#ibcon#wrote, iclass 36, count 0 2006.173.16:26:55.47#ibcon#about to read 3, iclass 36, count 0 2006.173.16:26:55.49#ibcon#read 3, iclass 36, count 0 2006.173.16:26:55.49#ibcon#about to read 4, iclass 36, count 0 2006.173.16:26:55.49#ibcon#read 4, iclass 36, count 0 2006.173.16:26:55.49#ibcon#about to read 5, iclass 36, count 0 2006.173.16:26:55.49#ibcon#read 5, iclass 36, count 0 2006.173.16:26:55.49#ibcon#about to read 6, iclass 36, count 0 2006.173.16:26:55.49#ibcon#read 6, iclass 36, count 0 2006.173.16:26:55.49#ibcon#end of sib2, iclass 36, count 0 2006.173.16:26:55.49#ibcon#*mode == 0, iclass 36, count 0 2006.173.16:26:55.49#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.16:26:55.49#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.16:26:55.49#ibcon#*before write, iclass 36, count 0 2006.173.16:26:55.49#ibcon#enter sib2, iclass 36, count 0 2006.173.16:26:55.49#ibcon#flushed, iclass 36, count 0 2006.173.16:26:55.49#ibcon#about to write, iclass 36, count 0 2006.173.16:26:55.49#ibcon#wrote, iclass 36, count 0 2006.173.16:26:55.49#ibcon#about to read 3, iclass 36, count 0 2006.173.16:26:55.53#ibcon#read 3, iclass 36, count 0 2006.173.16:26:55.53#ibcon#about to read 4, iclass 36, count 0 2006.173.16:26:55.53#ibcon#read 4, iclass 36, count 0 2006.173.16:26:55.53#ibcon#about to read 5, iclass 36, count 0 2006.173.16:26:55.53#ibcon#read 5, iclass 36, count 0 2006.173.16:26:55.53#ibcon#about to read 6, iclass 36, count 0 2006.173.16:26:55.53#ibcon#read 6, iclass 36, count 0 2006.173.16:26:55.53#ibcon#end of sib2, iclass 36, count 0 2006.173.16:26:55.53#ibcon#*after write, iclass 36, count 0 2006.173.16:26:55.53#ibcon#*before return 0, iclass 36, count 0 2006.173.16:26:55.53#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.16:26:55.53#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.16:26:55.53#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.16:26:55.53#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.16:26:55.53$vck44/va=7,4 2006.173.16:26:55.53#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.16:26:55.53#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.16:26:55.53#ibcon#ireg 11 cls_cnt 2 2006.173.16:26:55.53#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.16:26:55.59#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.16:26:55.59#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.16:26:55.59#ibcon#enter wrdev, iclass 38, count 2 2006.173.16:26:55.59#ibcon#first serial, iclass 38, count 2 2006.173.16:26:55.59#ibcon#enter sib2, iclass 38, count 2 2006.173.16:26:55.59#ibcon#flushed, iclass 38, count 2 2006.173.16:26:55.59#ibcon#about to write, iclass 38, count 2 2006.173.16:26:55.59#ibcon#wrote, iclass 38, count 2 2006.173.16:26:55.59#ibcon#about to read 3, iclass 38, count 2 2006.173.16:26:55.61#ibcon#read 3, iclass 38, count 2 2006.173.16:26:55.61#ibcon#about to read 4, iclass 38, count 2 2006.173.16:26:55.61#ibcon#read 4, iclass 38, count 2 2006.173.16:26:55.61#ibcon#about to read 5, iclass 38, count 2 2006.173.16:26:55.61#ibcon#read 5, iclass 38, count 2 2006.173.16:26:55.61#ibcon#about to read 6, iclass 38, count 2 2006.173.16:26:55.61#ibcon#read 6, iclass 38, count 2 2006.173.16:26:55.61#ibcon#end of sib2, iclass 38, count 2 2006.173.16:26:55.61#ibcon#*mode == 0, iclass 38, count 2 2006.173.16:26:55.61#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.16:26:55.61#ibcon#[25=AT07-04\r\n] 2006.173.16:26:55.61#ibcon#*before write, iclass 38, count 2 2006.173.16:26:55.61#ibcon#enter sib2, iclass 38, count 2 2006.173.16:26:55.61#ibcon#flushed, iclass 38, count 2 2006.173.16:26:55.61#ibcon#about to write, iclass 38, count 2 2006.173.16:26:55.61#ibcon#wrote, iclass 38, count 2 2006.173.16:26:55.61#ibcon#about to read 3, iclass 38, count 2 2006.173.16:26:55.64#ibcon#read 3, iclass 38, count 2 2006.173.16:26:55.64#ibcon#about to read 4, iclass 38, count 2 2006.173.16:26:55.64#ibcon#read 4, iclass 38, count 2 2006.173.16:26:55.64#ibcon#about to read 5, iclass 38, count 2 2006.173.16:26:55.64#ibcon#read 5, iclass 38, count 2 2006.173.16:26:55.64#ibcon#about to read 6, iclass 38, count 2 2006.173.16:26:55.64#ibcon#read 6, iclass 38, count 2 2006.173.16:26:55.64#ibcon#end of sib2, iclass 38, count 2 2006.173.16:26:55.64#ibcon#*after write, iclass 38, count 2 2006.173.16:26:55.64#ibcon#*before return 0, iclass 38, count 2 2006.173.16:26:55.64#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.16:26:55.64#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.16:26:55.64#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.16:26:55.64#ibcon#ireg 7 cls_cnt 0 2006.173.16:26:55.64#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.16:26:55.76#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.16:26:55.76#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.16:26:55.76#ibcon#enter wrdev, iclass 38, count 0 2006.173.16:26:55.76#ibcon#first serial, iclass 38, count 0 2006.173.16:26:55.76#ibcon#enter sib2, iclass 38, count 0 2006.173.16:26:55.76#ibcon#flushed, iclass 38, count 0 2006.173.16:26:55.76#ibcon#about to write, iclass 38, count 0 2006.173.16:26:55.76#ibcon#wrote, iclass 38, count 0 2006.173.16:26:55.76#ibcon#about to read 3, iclass 38, count 0 2006.173.16:26:55.78#ibcon#read 3, iclass 38, count 0 2006.173.16:26:55.78#ibcon#about to read 4, iclass 38, count 0 2006.173.16:26:55.78#ibcon#read 4, iclass 38, count 0 2006.173.16:26:55.78#ibcon#about to read 5, iclass 38, count 0 2006.173.16:26:55.78#ibcon#read 5, iclass 38, count 0 2006.173.16:26:55.78#ibcon#about to read 6, iclass 38, count 0 2006.173.16:26:55.78#ibcon#read 6, iclass 38, count 0 2006.173.16:26:55.78#ibcon#end of sib2, iclass 38, count 0 2006.173.16:26:55.78#ibcon#*mode == 0, iclass 38, count 0 2006.173.16:26:55.78#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.16:26:55.78#ibcon#[25=USB\r\n] 2006.173.16:26:55.78#ibcon#*before write, iclass 38, count 0 2006.173.16:26:55.78#ibcon#enter sib2, iclass 38, count 0 2006.173.16:26:55.78#ibcon#flushed, iclass 38, count 0 2006.173.16:26:55.78#ibcon#about to write, iclass 38, count 0 2006.173.16:26:55.78#ibcon#wrote, iclass 38, count 0 2006.173.16:26:55.78#ibcon#about to read 3, iclass 38, count 0 2006.173.16:26:55.81#ibcon#read 3, iclass 38, count 0 2006.173.16:26:55.81#ibcon#about to read 4, iclass 38, count 0 2006.173.16:26:55.81#ibcon#read 4, iclass 38, count 0 2006.173.16:26:55.81#ibcon#about to read 5, iclass 38, count 0 2006.173.16:26:55.81#ibcon#read 5, iclass 38, count 0 2006.173.16:26:55.81#ibcon#about to read 6, iclass 38, count 0 2006.173.16:26:55.81#ibcon#read 6, iclass 38, count 0 2006.173.16:26:55.81#ibcon#end of sib2, iclass 38, count 0 2006.173.16:26:55.81#ibcon#*after write, iclass 38, count 0 2006.173.16:26:55.81#ibcon#*before return 0, iclass 38, count 0 2006.173.16:26:55.81#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.16:26:55.81#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.16:26:55.81#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.16:26:55.81#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.16:26:55.81$vck44/valo=8,884.99 2006.173.16:26:55.81#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.16:26:55.81#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.16:26:55.81#ibcon#ireg 17 cls_cnt 0 2006.173.16:26:55.81#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.16:26:55.81#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.16:26:55.81#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.16:26:55.81#ibcon#enter wrdev, iclass 40, count 0 2006.173.16:26:55.81#ibcon#first serial, iclass 40, count 0 2006.173.16:26:55.81#ibcon#enter sib2, iclass 40, count 0 2006.173.16:26:55.81#ibcon#flushed, iclass 40, count 0 2006.173.16:26:55.81#ibcon#about to write, iclass 40, count 0 2006.173.16:26:55.81#ibcon#wrote, iclass 40, count 0 2006.173.16:26:55.81#ibcon#about to read 3, iclass 40, count 0 2006.173.16:26:55.83#ibcon#read 3, iclass 40, count 0 2006.173.16:26:55.83#ibcon#about to read 4, iclass 40, count 0 2006.173.16:26:55.83#ibcon#read 4, iclass 40, count 0 2006.173.16:26:55.83#ibcon#about to read 5, iclass 40, count 0 2006.173.16:26:55.83#ibcon#read 5, iclass 40, count 0 2006.173.16:26:55.83#ibcon#about to read 6, iclass 40, count 0 2006.173.16:26:55.83#ibcon#read 6, iclass 40, count 0 2006.173.16:26:55.83#ibcon#end of sib2, iclass 40, count 0 2006.173.16:26:55.83#ibcon#*mode == 0, iclass 40, count 0 2006.173.16:26:55.83#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.16:26:55.83#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.16:26:55.83#ibcon#*before write, iclass 40, count 0 2006.173.16:26:55.83#ibcon#enter sib2, iclass 40, count 0 2006.173.16:26:55.83#ibcon#flushed, iclass 40, count 0 2006.173.16:26:55.83#ibcon#about to write, iclass 40, count 0 2006.173.16:26:55.83#ibcon#wrote, iclass 40, count 0 2006.173.16:26:55.83#ibcon#about to read 3, iclass 40, count 0 2006.173.16:26:55.87#ibcon#read 3, iclass 40, count 0 2006.173.16:26:55.87#ibcon#about to read 4, iclass 40, count 0 2006.173.16:26:55.87#ibcon#read 4, iclass 40, count 0 2006.173.16:26:55.87#ibcon#about to read 5, iclass 40, count 0 2006.173.16:26:55.87#ibcon#read 5, iclass 40, count 0 2006.173.16:26:55.87#ibcon#about to read 6, iclass 40, count 0 2006.173.16:26:55.87#ibcon#read 6, iclass 40, count 0 2006.173.16:26:55.87#ibcon#end of sib2, iclass 40, count 0 2006.173.16:26:55.87#ibcon#*after write, iclass 40, count 0 2006.173.16:26:55.87#ibcon#*before return 0, iclass 40, count 0 2006.173.16:26:55.87#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.16:26:55.87#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.16:26:55.87#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.16:26:55.87#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.16:26:55.87$vck44/va=8,4 2006.173.16:26:55.87#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.16:26:55.87#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.16:26:55.87#ibcon#ireg 11 cls_cnt 2 2006.173.16:26:55.87#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.16:26:55.93#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.16:26:55.93#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.16:26:55.93#ibcon#enter wrdev, iclass 4, count 2 2006.173.16:26:55.93#ibcon#first serial, iclass 4, count 2 2006.173.16:26:55.93#ibcon#enter sib2, iclass 4, count 2 2006.173.16:26:55.93#ibcon#flushed, iclass 4, count 2 2006.173.16:26:55.93#ibcon#about to write, iclass 4, count 2 2006.173.16:26:55.93#ibcon#wrote, iclass 4, count 2 2006.173.16:26:55.93#ibcon#about to read 3, iclass 4, count 2 2006.173.16:26:55.95#ibcon#read 3, iclass 4, count 2 2006.173.16:26:55.95#ibcon#about to read 4, iclass 4, count 2 2006.173.16:26:55.95#ibcon#read 4, iclass 4, count 2 2006.173.16:26:55.95#ibcon#about to read 5, iclass 4, count 2 2006.173.16:26:55.95#ibcon#read 5, iclass 4, count 2 2006.173.16:26:55.95#ibcon#about to read 6, iclass 4, count 2 2006.173.16:26:55.95#ibcon#read 6, iclass 4, count 2 2006.173.16:26:55.95#ibcon#end of sib2, iclass 4, count 2 2006.173.16:26:55.95#ibcon#*mode == 0, iclass 4, count 2 2006.173.16:26:55.95#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.16:26:55.95#ibcon#[25=AT08-04\r\n] 2006.173.16:26:55.95#ibcon#*before write, iclass 4, count 2 2006.173.16:26:55.95#ibcon#enter sib2, iclass 4, count 2 2006.173.16:26:55.95#ibcon#flushed, iclass 4, count 2 2006.173.16:26:55.95#ibcon#about to write, iclass 4, count 2 2006.173.16:26:55.95#ibcon#wrote, iclass 4, count 2 2006.173.16:26:55.95#ibcon#about to read 3, iclass 4, count 2 2006.173.16:26:55.98#ibcon#read 3, iclass 4, count 2 2006.173.16:26:55.98#ibcon#about to read 4, iclass 4, count 2 2006.173.16:26:55.98#ibcon#read 4, iclass 4, count 2 2006.173.16:26:55.98#ibcon#about to read 5, iclass 4, count 2 2006.173.16:26:55.98#ibcon#read 5, iclass 4, count 2 2006.173.16:26:55.98#ibcon#about to read 6, iclass 4, count 2 2006.173.16:26:55.98#ibcon#read 6, iclass 4, count 2 2006.173.16:26:55.98#ibcon#end of sib2, iclass 4, count 2 2006.173.16:26:55.98#ibcon#*after write, iclass 4, count 2 2006.173.16:26:55.98#ibcon#*before return 0, iclass 4, count 2 2006.173.16:26:55.98#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.16:26:55.98#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.16:26:55.98#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.16:26:55.98#ibcon#ireg 7 cls_cnt 0 2006.173.16:26:55.98#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.16:26:56.10#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.16:26:56.10#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.16:26:56.10#ibcon#enter wrdev, iclass 4, count 0 2006.173.16:26:56.10#ibcon#first serial, iclass 4, count 0 2006.173.16:26:56.10#ibcon#enter sib2, iclass 4, count 0 2006.173.16:26:56.10#ibcon#flushed, iclass 4, count 0 2006.173.16:26:56.10#ibcon#about to write, iclass 4, count 0 2006.173.16:26:56.10#ibcon#wrote, iclass 4, count 0 2006.173.16:26:56.10#ibcon#about to read 3, iclass 4, count 0 2006.173.16:26:56.12#ibcon#read 3, iclass 4, count 0 2006.173.16:26:56.12#ibcon#about to read 4, iclass 4, count 0 2006.173.16:26:56.12#ibcon#read 4, iclass 4, count 0 2006.173.16:26:56.12#ibcon#about to read 5, iclass 4, count 0 2006.173.16:26:56.12#ibcon#read 5, iclass 4, count 0 2006.173.16:26:56.12#ibcon#about to read 6, iclass 4, count 0 2006.173.16:26:56.12#ibcon#read 6, iclass 4, count 0 2006.173.16:26:56.12#ibcon#end of sib2, iclass 4, count 0 2006.173.16:26:56.12#ibcon#*mode == 0, iclass 4, count 0 2006.173.16:26:56.12#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.16:26:56.12#ibcon#[25=USB\r\n] 2006.173.16:26:56.12#ibcon#*before write, iclass 4, count 0 2006.173.16:26:56.12#ibcon#enter sib2, iclass 4, count 0 2006.173.16:26:56.12#ibcon#flushed, iclass 4, count 0 2006.173.16:26:56.12#ibcon#about to write, iclass 4, count 0 2006.173.16:26:56.12#ibcon#wrote, iclass 4, count 0 2006.173.16:26:56.12#ibcon#about to read 3, iclass 4, count 0 2006.173.16:26:56.15#ibcon#read 3, iclass 4, count 0 2006.173.16:26:56.15#ibcon#about to read 4, iclass 4, count 0 2006.173.16:26:56.15#ibcon#read 4, iclass 4, count 0 2006.173.16:26:56.15#ibcon#about to read 5, iclass 4, count 0 2006.173.16:26:56.15#ibcon#read 5, iclass 4, count 0 2006.173.16:26:56.15#ibcon#about to read 6, iclass 4, count 0 2006.173.16:26:56.15#ibcon#read 6, iclass 4, count 0 2006.173.16:26:56.15#ibcon#end of sib2, iclass 4, count 0 2006.173.16:26:56.15#ibcon#*after write, iclass 4, count 0 2006.173.16:26:56.15#ibcon#*before return 0, iclass 4, count 0 2006.173.16:26:56.15#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.16:26:56.15#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.16:26:56.15#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.16:26:56.15#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.16:26:56.15$vck44/vblo=1,629.99 2006.173.16:26:56.15#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.16:26:56.15#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.16:26:56.15#ibcon#ireg 17 cls_cnt 0 2006.173.16:26:56.15#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.16:26:56.15#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.16:26:56.15#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.16:26:56.15#ibcon#enter wrdev, iclass 6, count 0 2006.173.16:26:56.15#ibcon#first serial, iclass 6, count 0 2006.173.16:26:56.15#ibcon#enter sib2, iclass 6, count 0 2006.173.16:26:56.15#ibcon#flushed, iclass 6, count 0 2006.173.16:26:56.15#ibcon#about to write, iclass 6, count 0 2006.173.16:26:56.15#ibcon#wrote, iclass 6, count 0 2006.173.16:26:56.15#ibcon#about to read 3, iclass 6, count 0 2006.173.16:26:56.17#ibcon#read 3, iclass 6, count 0 2006.173.16:26:56.17#ibcon#about to read 4, iclass 6, count 0 2006.173.16:26:56.17#ibcon#read 4, iclass 6, count 0 2006.173.16:26:56.17#ibcon#about to read 5, iclass 6, count 0 2006.173.16:26:56.17#ibcon#read 5, iclass 6, count 0 2006.173.16:26:56.17#ibcon#about to read 6, iclass 6, count 0 2006.173.16:26:56.17#ibcon#read 6, iclass 6, count 0 2006.173.16:26:56.17#ibcon#end of sib2, iclass 6, count 0 2006.173.16:26:56.17#ibcon#*mode == 0, iclass 6, count 0 2006.173.16:26:56.17#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.16:26:56.17#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.16:26:56.17#ibcon#*before write, iclass 6, count 0 2006.173.16:26:56.17#ibcon#enter sib2, iclass 6, count 0 2006.173.16:26:56.17#ibcon#flushed, iclass 6, count 0 2006.173.16:26:56.17#ibcon#about to write, iclass 6, count 0 2006.173.16:26:56.17#ibcon#wrote, iclass 6, count 0 2006.173.16:26:56.17#ibcon#about to read 3, iclass 6, count 0 2006.173.16:26:56.21#ibcon#read 3, iclass 6, count 0 2006.173.16:26:56.21#ibcon#about to read 4, iclass 6, count 0 2006.173.16:26:56.21#ibcon#read 4, iclass 6, count 0 2006.173.16:26:56.21#ibcon#about to read 5, iclass 6, count 0 2006.173.16:26:56.21#ibcon#read 5, iclass 6, count 0 2006.173.16:26:56.21#ibcon#about to read 6, iclass 6, count 0 2006.173.16:26:56.21#ibcon#read 6, iclass 6, count 0 2006.173.16:26:56.21#ibcon#end of sib2, iclass 6, count 0 2006.173.16:26:56.21#ibcon#*after write, iclass 6, count 0 2006.173.16:26:56.21#ibcon#*before return 0, iclass 6, count 0 2006.173.16:26:56.21#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.16:26:56.21#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.16:26:56.21#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.16:26:56.21#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.16:26:56.21$vck44/vb=1,4 2006.173.16:26:56.21#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.16:26:56.21#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.16:26:56.21#ibcon#ireg 11 cls_cnt 2 2006.173.16:26:56.21#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.16:26:56.21#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.16:26:56.21#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.16:26:56.21#ibcon#enter wrdev, iclass 10, count 2 2006.173.16:26:56.21#ibcon#first serial, iclass 10, count 2 2006.173.16:26:56.21#ibcon#enter sib2, iclass 10, count 2 2006.173.16:26:56.21#ibcon#flushed, iclass 10, count 2 2006.173.16:26:56.21#ibcon#about to write, iclass 10, count 2 2006.173.16:26:56.21#ibcon#wrote, iclass 10, count 2 2006.173.16:26:56.21#ibcon#about to read 3, iclass 10, count 2 2006.173.16:26:56.23#ibcon#read 3, iclass 10, count 2 2006.173.16:26:56.23#ibcon#about to read 4, iclass 10, count 2 2006.173.16:26:56.23#ibcon#read 4, iclass 10, count 2 2006.173.16:26:56.23#ibcon#about to read 5, iclass 10, count 2 2006.173.16:26:56.23#ibcon#read 5, iclass 10, count 2 2006.173.16:26:56.23#ibcon#about to read 6, iclass 10, count 2 2006.173.16:26:56.23#ibcon#read 6, iclass 10, count 2 2006.173.16:26:56.23#ibcon#end of sib2, iclass 10, count 2 2006.173.16:26:56.23#ibcon#*mode == 0, iclass 10, count 2 2006.173.16:26:56.23#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.16:26:56.23#ibcon#[27=AT01-04\r\n] 2006.173.16:26:56.23#ibcon#*before write, iclass 10, count 2 2006.173.16:26:56.23#ibcon#enter sib2, iclass 10, count 2 2006.173.16:26:56.23#ibcon#flushed, iclass 10, count 2 2006.173.16:26:56.23#ibcon#about to write, iclass 10, count 2 2006.173.16:26:56.23#ibcon#wrote, iclass 10, count 2 2006.173.16:26:56.23#ibcon#about to read 3, iclass 10, count 2 2006.173.16:26:56.26#ibcon#read 3, iclass 10, count 2 2006.173.16:26:56.26#ibcon#about to read 4, iclass 10, count 2 2006.173.16:26:56.26#ibcon#read 4, iclass 10, count 2 2006.173.16:26:56.26#ibcon#about to read 5, iclass 10, count 2 2006.173.16:26:56.26#ibcon#read 5, iclass 10, count 2 2006.173.16:26:56.26#ibcon#about to read 6, iclass 10, count 2 2006.173.16:26:56.26#ibcon#read 6, iclass 10, count 2 2006.173.16:26:56.26#ibcon#end of sib2, iclass 10, count 2 2006.173.16:26:56.26#ibcon#*after write, iclass 10, count 2 2006.173.16:26:56.26#ibcon#*before return 0, iclass 10, count 2 2006.173.16:26:56.26#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.16:26:56.26#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.16:26:56.26#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.16:26:56.26#ibcon#ireg 7 cls_cnt 0 2006.173.16:26:56.26#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.16:26:56.38#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.16:26:56.38#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.16:26:56.38#ibcon#enter wrdev, iclass 10, count 0 2006.173.16:26:56.38#ibcon#first serial, iclass 10, count 0 2006.173.16:26:56.38#ibcon#enter sib2, iclass 10, count 0 2006.173.16:26:56.38#ibcon#flushed, iclass 10, count 0 2006.173.16:26:56.38#ibcon#about to write, iclass 10, count 0 2006.173.16:26:56.38#ibcon#wrote, iclass 10, count 0 2006.173.16:26:56.38#ibcon#about to read 3, iclass 10, count 0 2006.173.16:26:56.40#ibcon#read 3, iclass 10, count 0 2006.173.16:26:56.40#ibcon#about to read 4, iclass 10, count 0 2006.173.16:26:56.40#ibcon#read 4, iclass 10, count 0 2006.173.16:26:56.40#ibcon#about to read 5, iclass 10, count 0 2006.173.16:26:56.40#ibcon#read 5, iclass 10, count 0 2006.173.16:26:56.40#ibcon#about to read 6, iclass 10, count 0 2006.173.16:26:56.40#ibcon#read 6, iclass 10, count 0 2006.173.16:26:56.40#ibcon#end of sib2, iclass 10, count 0 2006.173.16:26:56.40#ibcon#*mode == 0, iclass 10, count 0 2006.173.16:26:56.40#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.16:26:56.40#ibcon#[27=USB\r\n] 2006.173.16:26:56.40#ibcon#*before write, iclass 10, count 0 2006.173.16:26:56.40#ibcon#enter sib2, iclass 10, count 0 2006.173.16:26:56.40#ibcon#flushed, iclass 10, count 0 2006.173.16:26:56.40#ibcon#about to write, iclass 10, count 0 2006.173.16:26:56.40#ibcon#wrote, iclass 10, count 0 2006.173.16:26:56.40#ibcon#about to read 3, iclass 10, count 0 2006.173.16:26:56.43#ibcon#read 3, iclass 10, count 0 2006.173.16:26:56.43#ibcon#about to read 4, iclass 10, count 0 2006.173.16:26:56.43#ibcon#read 4, iclass 10, count 0 2006.173.16:26:56.43#ibcon#about to read 5, iclass 10, count 0 2006.173.16:26:56.43#ibcon#read 5, iclass 10, count 0 2006.173.16:26:56.43#ibcon#about to read 6, iclass 10, count 0 2006.173.16:26:56.43#ibcon#read 6, iclass 10, count 0 2006.173.16:26:56.43#ibcon#end of sib2, iclass 10, count 0 2006.173.16:26:56.43#ibcon#*after write, iclass 10, count 0 2006.173.16:26:56.43#ibcon#*before return 0, iclass 10, count 0 2006.173.16:26:56.43#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.16:26:56.43#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.16:26:56.43#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.16:26:56.43#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.16:26:56.43$vck44/vblo=2,634.99 2006.173.16:26:56.43#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.16:26:56.43#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.16:26:56.43#ibcon#ireg 17 cls_cnt 0 2006.173.16:26:56.43#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.16:26:56.43#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.16:26:56.43#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.16:26:56.43#ibcon#enter wrdev, iclass 12, count 0 2006.173.16:26:56.43#ibcon#first serial, iclass 12, count 0 2006.173.16:26:56.43#ibcon#enter sib2, iclass 12, count 0 2006.173.16:26:56.43#ibcon#flushed, iclass 12, count 0 2006.173.16:26:56.43#ibcon#about to write, iclass 12, count 0 2006.173.16:26:56.43#ibcon#wrote, iclass 12, count 0 2006.173.16:26:56.43#ibcon#about to read 3, iclass 12, count 0 2006.173.16:26:56.45#ibcon#read 3, iclass 12, count 0 2006.173.16:26:56.45#ibcon#about to read 4, iclass 12, count 0 2006.173.16:26:56.45#ibcon#read 4, iclass 12, count 0 2006.173.16:26:56.45#ibcon#about to read 5, iclass 12, count 0 2006.173.16:26:56.45#ibcon#read 5, iclass 12, count 0 2006.173.16:26:56.45#ibcon#about to read 6, iclass 12, count 0 2006.173.16:26:56.45#ibcon#read 6, iclass 12, count 0 2006.173.16:26:56.45#ibcon#end of sib2, iclass 12, count 0 2006.173.16:26:56.45#ibcon#*mode == 0, iclass 12, count 0 2006.173.16:26:56.45#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.16:26:56.45#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.16:26:56.45#ibcon#*before write, iclass 12, count 0 2006.173.16:26:56.45#ibcon#enter sib2, iclass 12, count 0 2006.173.16:26:56.45#ibcon#flushed, iclass 12, count 0 2006.173.16:26:56.45#ibcon#about to write, iclass 12, count 0 2006.173.16:26:56.45#ibcon#wrote, iclass 12, count 0 2006.173.16:26:56.45#ibcon#about to read 3, iclass 12, count 0 2006.173.16:26:56.49#ibcon#read 3, iclass 12, count 0 2006.173.16:26:56.49#ibcon#about to read 4, iclass 12, count 0 2006.173.16:26:56.49#ibcon#read 4, iclass 12, count 0 2006.173.16:26:56.49#ibcon#about to read 5, iclass 12, count 0 2006.173.16:26:56.49#ibcon#read 5, iclass 12, count 0 2006.173.16:26:56.49#ibcon#about to read 6, iclass 12, count 0 2006.173.16:26:56.49#ibcon#read 6, iclass 12, count 0 2006.173.16:26:56.49#ibcon#end of sib2, iclass 12, count 0 2006.173.16:26:56.49#ibcon#*after write, iclass 12, count 0 2006.173.16:26:56.49#ibcon#*before return 0, iclass 12, count 0 2006.173.16:26:56.49#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.16:26:56.49#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.16:26:56.49#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.16:26:56.49#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.16:26:56.49$vck44/vb=2,4 2006.173.16:26:56.49#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.16:26:56.49#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.16:26:56.49#ibcon#ireg 11 cls_cnt 2 2006.173.16:26:56.49#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.16:26:56.55#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.16:26:56.55#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.16:26:56.55#ibcon#enter wrdev, iclass 14, count 2 2006.173.16:26:56.55#ibcon#first serial, iclass 14, count 2 2006.173.16:26:56.55#ibcon#enter sib2, iclass 14, count 2 2006.173.16:26:56.55#ibcon#flushed, iclass 14, count 2 2006.173.16:26:56.55#ibcon#about to write, iclass 14, count 2 2006.173.16:26:56.55#ibcon#wrote, iclass 14, count 2 2006.173.16:26:56.55#ibcon#about to read 3, iclass 14, count 2 2006.173.16:26:56.57#ibcon#read 3, iclass 14, count 2 2006.173.16:26:56.57#ibcon#about to read 4, iclass 14, count 2 2006.173.16:26:56.57#ibcon#read 4, iclass 14, count 2 2006.173.16:26:56.57#ibcon#about to read 5, iclass 14, count 2 2006.173.16:26:56.57#ibcon#read 5, iclass 14, count 2 2006.173.16:26:56.57#ibcon#about to read 6, iclass 14, count 2 2006.173.16:26:56.57#ibcon#read 6, iclass 14, count 2 2006.173.16:26:56.57#ibcon#end of sib2, iclass 14, count 2 2006.173.16:26:56.57#ibcon#*mode == 0, iclass 14, count 2 2006.173.16:26:56.57#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.16:26:56.57#ibcon#[27=AT02-04\r\n] 2006.173.16:26:56.57#ibcon#*before write, iclass 14, count 2 2006.173.16:26:56.57#ibcon#enter sib2, iclass 14, count 2 2006.173.16:26:56.57#ibcon#flushed, iclass 14, count 2 2006.173.16:26:56.57#ibcon#about to write, iclass 14, count 2 2006.173.16:26:56.57#ibcon#wrote, iclass 14, count 2 2006.173.16:26:56.57#ibcon#about to read 3, iclass 14, count 2 2006.173.16:26:56.60#ibcon#read 3, iclass 14, count 2 2006.173.16:26:56.60#ibcon#about to read 4, iclass 14, count 2 2006.173.16:26:56.60#ibcon#read 4, iclass 14, count 2 2006.173.16:26:56.60#ibcon#about to read 5, iclass 14, count 2 2006.173.16:26:56.60#ibcon#read 5, iclass 14, count 2 2006.173.16:26:56.60#ibcon#about to read 6, iclass 14, count 2 2006.173.16:26:56.60#ibcon#read 6, iclass 14, count 2 2006.173.16:26:56.60#ibcon#end of sib2, iclass 14, count 2 2006.173.16:26:56.60#ibcon#*after write, iclass 14, count 2 2006.173.16:26:56.60#ibcon#*before return 0, iclass 14, count 2 2006.173.16:26:56.60#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.16:26:56.60#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.16:26:56.60#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.16:26:56.60#ibcon#ireg 7 cls_cnt 0 2006.173.16:26:56.60#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.16:26:56.72#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.16:26:56.72#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.16:26:56.72#ibcon#enter wrdev, iclass 14, count 0 2006.173.16:26:56.72#ibcon#first serial, iclass 14, count 0 2006.173.16:26:56.72#ibcon#enter sib2, iclass 14, count 0 2006.173.16:26:56.72#ibcon#flushed, iclass 14, count 0 2006.173.16:26:56.72#ibcon#about to write, iclass 14, count 0 2006.173.16:26:56.72#ibcon#wrote, iclass 14, count 0 2006.173.16:26:56.72#ibcon#about to read 3, iclass 14, count 0 2006.173.16:26:56.74#ibcon#read 3, iclass 14, count 0 2006.173.16:26:56.74#ibcon#about to read 4, iclass 14, count 0 2006.173.16:26:56.74#ibcon#read 4, iclass 14, count 0 2006.173.16:26:56.74#ibcon#about to read 5, iclass 14, count 0 2006.173.16:26:56.74#ibcon#read 5, iclass 14, count 0 2006.173.16:26:56.74#ibcon#about to read 6, iclass 14, count 0 2006.173.16:26:56.74#ibcon#read 6, iclass 14, count 0 2006.173.16:26:56.74#ibcon#end of sib2, iclass 14, count 0 2006.173.16:26:56.74#ibcon#*mode == 0, iclass 14, count 0 2006.173.16:26:56.74#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.16:26:56.74#ibcon#[27=USB\r\n] 2006.173.16:26:56.74#ibcon#*before write, iclass 14, count 0 2006.173.16:26:56.74#ibcon#enter sib2, iclass 14, count 0 2006.173.16:26:56.74#ibcon#flushed, iclass 14, count 0 2006.173.16:26:56.74#ibcon#about to write, iclass 14, count 0 2006.173.16:26:56.74#ibcon#wrote, iclass 14, count 0 2006.173.16:26:56.74#ibcon#about to read 3, iclass 14, count 0 2006.173.16:26:56.77#ibcon#read 3, iclass 14, count 0 2006.173.16:26:56.77#ibcon#about to read 4, iclass 14, count 0 2006.173.16:26:56.77#ibcon#read 4, iclass 14, count 0 2006.173.16:26:56.77#ibcon#about to read 5, iclass 14, count 0 2006.173.16:26:56.77#ibcon#read 5, iclass 14, count 0 2006.173.16:26:56.77#ibcon#about to read 6, iclass 14, count 0 2006.173.16:26:56.77#ibcon#read 6, iclass 14, count 0 2006.173.16:26:56.77#ibcon#end of sib2, iclass 14, count 0 2006.173.16:26:56.77#ibcon#*after write, iclass 14, count 0 2006.173.16:26:56.77#ibcon#*before return 0, iclass 14, count 0 2006.173.16:26:56.77#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.16:26:56.77#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.16:26:56.77#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.16:26:56.77#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.16:26:56.77$vck44/vblo=3,649.99 2006.173.16:26:56.77#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.16:26:56.77#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.16:26:56.77#ibcon#ireg 17 cls_cnt 0 2006.173.16:26:56.77#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.16:26:56.77#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.16:26:56.77#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.16:26:56.77#ibcon#enter wrdev, iclass 16, count 0 2006.173.16:26:56.77#ibcon#first serial, iclass 16, count 0 2006.173.16:26:56.77#ibcon#enter sib2, iclass 16, count 0 2006.173.16:26:56.77#ibcon#flushed, iclass 16, count 0 2006.173.16:26:56.77#ibcon#about to write, iclass 16, count 0 2006.173.16:26:56.77#ibcon#wrote, iclass 16, count 0 2006.173.16:26:56.77#ibcon#about to read 3, iclass 16, count 0 2006.173.16:26:56.79#ibcon#read 3, iclass 16, count 0 2006.173.16:26:56.79#ibcon#about to read 4, iclass 16, count 0 2006.173.16:26:56.79#ibcon#read 4, iclass 16, count 0 2006.173.16:26:56.79#ibcon#about to read 5, iclass 16, count 0 2006.173.16:26:56.79#ibcon#read 5, iclass 16, count 0 2006.173.16:26:56.79#ibcon#about to read 6, iclass 16, count 0 2006.173.16:26:56.79#ibcon#read 6, iclass 16, count 0 2006.173.16:26:56.79#ibcon#end of sib2, iclass 16, count 0 2006.173.16:26:56.79#ibcon#*mode == 0, iclass 16, count 0 2006.173.16:26:56.79#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.16:26:56.79#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.16:26:56.79#ibcon#*before write, iclass 16, count 0 2006.173.16:26:56.79#ibcon#enter sib2, iclass 16, count 0 2006.173.16:26:56.79#ibcon#flushed, iclass 16, count 0 2006.173.16:26:56.79#ibcon#about to write, iclass 16, count 0 2006.173.16:26:56.79#ibcon#wrote, iclass 16, count 0 2006.173.16:26:56.79#ibcon#about to read 3, iclass 16, count 0 2006.173.16:26:56.83#ibcon#read 3, iclass 16, count 0 2006.173.16:26:56.83#ibcon#about to read 4, iclass 16, count 0 2006.173.16:26:56.83#ibcon#read 4, iclass 16, count 0 2006.173.16:26:56.83#ibcon#about to read 5, iclass 16, count 0 2006.173.16:26:56.83#ibcon#read 5, iclass 16, count 0 2006.173.16:26:56.83#ibcon#about to read 6, iclass 16, count 0 2006.173.16:26:56.83#ibcon#read 6, iclass 16, count 0 2006.173.16:26:56.83#ibcon#end of sib2, iclass 16, count 0 2006.173.16:26:56.83#ibcon#*after write, iclass 16, count 0 2006.173.16:26:56.83#ibcon#*before return 0, iclass 16, count 0 2006.173.16:26:56.83#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.16:26:56.83#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.16:26:56.83#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.16:26:56.83#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.16:26:56.83$vck44/vb=3,4 2006.173.16:26:56.83#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.16:26:56.83#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.16:26:56.83#ibcon#ireg 11 cls_cnt 2 2006.173.16:26:56.83#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.16:26:56.89#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.16:26:56.89#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.16:26:56.89#ibcon#enter wrdev, iclass 18, count 2 2006.173.16:26:56.89#ibcon#first serial, iclass 18, count 2 2006.173.16:26:56.89#ibcon#enter sib2, iclass 18, count 2 2006.173.16:26:56.89#ibcon#flushed, iclass 18, count 2 2006.173.16:26:56.89#ibcon#about to write, iclass 18, count 2 2006.173.16:26:56.89#ibcon#wrote, iclass 18, count 2 2006.173.16:26:56.89#ibcon#about to read 3, iclass 18, count 2 2006.173.16:26:56.91#ibcon#read 3, iclass 18, count 2 2006.173.16:26:56.91#ibcon#about to read 4, iclass 18, count 2 2006.173.16:26:56.91#ibcon#read 4, iclass 18, count 2 2006.173.16:26:56.91#ibcon#about to read 5, iclass 18, count 2 2006.173.16:26:56.91#ibcon#read 5, iclass 18, count 2 2006.173.16:26:56.91#ibcon#about to read 6, iclass 18, count 2 2006.173.16:26:56.91#ibcon#read 6, iclass 18, count 2 2006.173.16:26:56.91#ibcon#end of sib2, iclass 18, count 2 2006.173.16:26:56.91#ibcon#*mode == 0, iclass 18, count 2 2006.173.16:26:56.91#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.16:26:56.91#ibcon#[27=AT03-04\r\n] 2006.173.16:26:56.91#ibcon#*before write, iclass 18, count 2 2006.173.16:26:56.91#ibcon#enter sib2, iclass 18, count 2 2006.173.16:26:56.91#ibcon#flushed, iclass 18, count 2 2006.173.16:26:56.91#ibcon#about to write, iclass 18, count 2 2006.173.16:26:56.91#ibcon#wrote, iclass 18, count 2 2006.173.16:26:56.91#ibcon#about to read 3, iclass 18, count 2 2006.173.16:26:56.94#ibcon#read 3, iclass 18, count 2 2006.173.16:26:56.94#ibcon#about to read 4, iclass 18, count 2 2006.173.16:26:56.94#ibcon#read 4, iclass 18, count 2 2006.173.16:26:56.94#ibcon#about to read 5, iclass 18, count 2 2006.173.16:26:56.94#ibcon#read 5, iclass 18, count 2 2006.173.16:26:56.94#ibcon#about to read 6, iclass 18, count 2 2006.173.16:26:56.94#ibcon#read 6, iclass 18, count 2 2006.173.16:26:56.94#ibcon#end of sib2, iclass 18, count 2 2006.173.16:26:56.94#ibcon#*after write, iclass 18, count 2 2006.173.16:26:56.94#ibcon#*before return 0, iclass 18, count 2 2006.173.16:26:56.94#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.16:26:56.94#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.16:26:56.94#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.16:26:56.94#ibcon#ireg 7 cls_cnt 0 2006.173.16:26:56.94#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.16:26:57.06#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.16:26:57.06#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.16:26:57.06#ibcon#enter wrdev, iclass 18, count 0 2006.173.16:26:57.06#ibcon#first serial, iclass 18, count 0 2006.173.16:26:57.06#ibcon#enter sib2, iclass 18, count 0 2006.173.16:26:57.06#ibcon#flushed, iclass 18, count 0 2006.173.16:26:57.06#ibcon#about to write, iclass 18, count 0 2006.173.16:26:57.06#ibcon#wrote, iclass 18, count 0 2006.173.16:26:57.06#ibcon#about to read 3, iclass 18, count 0 2006.173.16:26:57.08#ibcon#read 3, iclass 18, count 0 2006.173.16:26:57.08#ibcon#about to read 4, iclass 18, count 0 2006.173.16:26:57.08#ibcon#read 4, iclass 18, count 0 2006.173.16:26:57.08#ibcon#about to read 5, iclass 18, count 0 2006.173.16:26:57.08#ibcon#read 5, iclass 18, count 0 2006.173.16:26:57.08#ibcon#about to read 6, iclass 18, count 0 2006.173.16:26:57.08#ibcon#read 6, iclass 18, count 0 2006.173.16:26:57.08#ibcon#end of sib2, iclass 18, count 0 2006.173.16:26:57.08#ibcon#*mode == 0, iclass 18, count 0 2006.173.16:26:57.08#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.16:26:57.08#ibcon#[27=USB\r\n] 2006.173.16:26:57.08#ibcon#*before write, iclass 18, count 0 2006.173.16:26:57.08#ibcon#enter sib2, iclass 18, count 0 2006.173.16:26:57.08#ibcon#flushed, iclass 18, count 0 2006.173.16:26:57.08#ibcon#about to write, iclass 18, count 0 2006.173.16:26:57.08#ibcon#wrote, iclass 18, count 0 2006.173.16:26:57.08#ibcon#about to read 3, iclass 18, count 0 2006.173.16:26:57.11#ibcon#read 3, iclass 18, count 0 2006.173.16:26:57.11#ibcon#about to read 4, iclass 18, count 0 2006.173.16:26:57.11#ibcon#read 4, iclass 18, count 0 2006.173.16:26:57.11#ibcon#about to read 5, iclass 18, count 0 2006.173.16:26:57.11#ibcon#read 5, iclass 18, count 0 2006.173.16:26:57.11#ibcon#about to read 6, iclass 18, count 0 2006.173.16:26:57.11#ibcon#read 6, iclass 18, count 0 2006.173.16:26:57.11#ibcon#end of sib2, iclass 18, count 0 2006.173.16:26:57.11#ibcon#*after write, iclass 18, count 0 2006.173.16:26:57.11#ibcon#*before return 0, iclass 18, count 0 2006.173.16:26:57.11#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.16:26:57.11#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.16:26:57.11#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.16:26:57.11#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.16:26:57.11$vck44/vblo=4,679.99 2006.173.16:26:57.11#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.16:26:57.11#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.16:26:57.11#ibcon#ireg 17 cls_cnt 0 2006.173.16:26:57.11#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.16:26:57.11#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.16:26:57.11#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.16:26:57.11#ibcon#enter wrdev, iclass 20, count 0 2006.173.16:26:57.11#ibcon#first serial, iclass 20, count 0 2006.173.16:26:57.11#ibcon#enter sib2, iclass 20, count 0 2006.173.16:26:57.11#ibcon#flushed, iclass 20, count 0 2006.173.16:26:57.11#ibcon#about to write, iclass 20, count 0 2006.173.16:26:57.11#ibcon#wrote, iclass 20, count 0 2006.173.16:26:57.11#ibcon#about to read 3, iclass 20, count 0 2006.173.16:26:57.13#ibcon#read 3, iclass 20, count 0 2006.173.16:26:57.13#ibcon#about to read 4, iclass 20, count 0 2006.173.16:26:57.13#ibcon#read 4, iclass 20, count 0 2006.173.16:26:57.13#ibcon#about to read 5, iclass 20, count 0 2006.173.16:26:57.13#ibcon#read 5, iclass 20, count 0 2006.173.16:26:57.13#ibcon#about to read 6, iclass 20, count 0 2006.173.16:26:57.13#ibcon#read 6, iclass 20, count 0 2006.173.16:26:57.13#ibcon#end of sib2, iclass 20, count 0 2006.173.16:26:57.13#ibcon#*mode == 0, iclass 20, count 0 2006.173.16:26:57.13#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.16:26:57.13#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.16:26:57.13#ibcon#*before write, iclass 20, count 0 2006.173.16:26:57.13#ibcon#enter sib2, iclass 20, count 0 2006.173.16:26:57.13#ibcon#flushed, iclass 20, count 0 2006.173.16:26:57.13#ibcon#about to write, iclass 20, count 0 2006.173.16:26:57.13#ibcon#wrote, iclass 20, count 0 2006.173.16:26:57.13#ibcon#about to read 3, iclass 20, count 0 2006.173.16:26:57.17#ibcon#read 3, iclass 20, count 0 2006.173.16:26:57.17#ibcon#about to read 4, iclass 20, count 0 2006.173.16:26:57.17#ibcon#read 4, iclass 20, count 0 2006.173.16:26:57.17#ibcon#about to read 5, iclass 20, count 0 2006.173.16:26:57.17#ibcon#read 5, iclass 20, count 0 2006.173.16:26:57.17#ibcon#about to read 6, iclass 20, count 0 2006.173.16:26:57.17#ibcon#read 6, iclass 20, count 0 2006.173.16:26:57.17#ibcon#end of sib2, iclass 20, count 0 2006.173.16:26:57.17#ibcon#*after write, iclass 20, count 0 2006.173.16:26:57.17#ibcon#*before return 0, iclass 20, count 0 2006.173.16:26:57.17#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.16:26:57.17#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.16:26:57.17#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.16:26:57.17#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.16:26:57.17$vck44/vb=4,4 2006.173.16:26:57.17#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.16:26:57.17#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.16:26:57.17#ibcon#ireg 11 cls_cnt 2 2006.173.16:26:57.17#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.16:26:57.23#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.16:26:57.23#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.16:26:57.23#ibcon#enter wrdev, iclass 22, count 2 2006.173.16:26:57.23#ibcon#first serial, iclass 22, count 2 2006.173.16:26:57.23#ibcon#enter sib2, iclass 22, count 2 2006.173.16:26:57.23#ibcon#flushed, iclass 22, count 2 2006.173.16:26:57.23#ibcon#about to write, iclass 22, count 2 2006.173.16:26:57.23#ibcon#wrote, iclass 22, count 2 2006.173.16:26:57.23#ibcon#about to read 3, iclass 22, count 2 2006.173.16:26:57.25#ibcon#read 3, iclass 22, count 2 2006.173.16:26:57.25#ibcon#about to read 4, iclass 22, count 2 2006.173.16:26:57.25#ibcon#read 4, iclass 22, count 2 2006.173.16:26:57.25#ibcon#about to read 5, iclass 22, count 2 2006.173.16:26:57.25#ibcon#read 5, iclass 22, count 2 2006.173.16:26:57.25#ibcon#about to read 6, iclass 22, count 2 2006.173.16:26:57.25#ibcon#read 6, iclass 22, count 2 2006.173.16:26:57.25#ibcon#end of sib2, iclass 22, count 2 2006.173.16:26:57.25#ibcon#*mode == 0, iclass 22, count 2 2006.173.16:26:57.25#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.16:26:57.25#ibcon#[27=AT04-04\r\n] 2006.173.16:26:57.25#ibcon#*before write, iclass 22, count 2 2006.173.16:26:57.25#ibcon#enter sib2, iclass 22, count 2 2006.173.16:26:57.25#ibcon#flushed, iclass 22, count 2 2006.173.16:26:57.25#ibcon#about to write, iclass 22, count 2 2006.173.16:26:57.25#ibcon#wrote, iclass 22, count 2 2006.173.16:26:57.25#ibcon#about to read 3, iclass 22, count 2 2006.173.16:26:57.28#ibcon#read 3, iclass 22, count 2 2006.173.16:26:57.28#ibcon#about to read 4, iclass 22, count 2 2006.173.16:26:57.28#ibcon#read 4, iclass 22, count 2 2006.173.16:26:57.28#ibcon#about to read 5, iclass 22, count 2 2006.173.16:26:57.28#ibcon#read 5, iclass 22, count 2 2006.173.16:26:57.28#ibcon#about to read 6, iclass 22, count 2 2006.173.16:26:57.28#ibcon#read 6, iclass 22, count 2 2006.173.16:26:57.28#ibcon#end of sib2, iclass 22, count 2 2006.173.16:26:57.28#ibcon#*after write, iclass 22, count 2 2006.173.16:26:57.28#ibcon#*before return 0, iclass 22, count 2 2006.173.16:26:57.28#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.16:26:57.28#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.16:26:57.28#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.16:26:57.28#ibcon#ireg 7 cls_cnt 0 2006.173.16:26:57.28#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.16:26:57.40#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.16:26:57.40#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.16:26:57.40#ibcon#enter wrdev, iclass 22, count 0 2006.173.16:26:57.40#ibcon#first serial, iclass 22, count 0 2006.173.16:26:57.40#ibcon#enter sib2, iclass 22, count 0 2006.173.16:26:57.40#ibcon#flushed, iclass 22, count 0 2006.173.16:26:57.40#ibcon#about to write, iclass 22, count 0 2006.173.16:26:57.40#ibcon#wrote, iclass 22, count 0 2006.173.16:26:57.40#ibcon#about to read 3, iclass 22, count 0 2006.173.16:26:57.42#ibcon#read 3, iclass 22, count 0 2006.173.16:26:57.42#ibcon#about to read 4, iclass 22, count 0 2006.173.16:26:57.42#ibcon#read 4, iclass 22, count 0 2006.173.16:26:57.42#ibcon#about to read 5, iclass 22, count 0 2006.173.16:26:57.42#ibcon#read 5, iclass 22, count 0 2006.173.16:26:57.42#ibcon#about to read 6, iclass 22, count 0 2006.173.16:26:57.42#ibcon#read 6, iclass 22, count 0 2006.173.16:26:57.42#ibcon#end of sib2, iclass 22, count 0 2006.173.16:26:57.42#ibcon#*mode == 0, iclass 22, count 0 2006.173.16:26:57.42#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.16:26:57.42#ibcon#[27=USB\r\n] 2006.173.16:26:57.42#ibcon#*before write, iclass 22, count 0 2006.173.16:26:57.42#ibcon#enter sib2, iclass 22, count 0 2006.173.16:26:57.42#ibcon#flushed, iclass 22, count 0 2006.173.16:26:57.42#ibcon#about to write, iclass 22, count 0 2006.173.16:26:57.42#ibcon#wrote, iclass 22, count 0 2006.173.16:26:57.42#ibcon#about to read 3, iclass 22, count 0 2006.173.16:26:57.45#ibcon#read 3, iclass 22, count 0 2006.173.16:26:57.45#ibcon#about to read 4, iclass 22, count 0 2006.173.16:26:57.45#ibcon#read 4, iclass 22, count 0 2006.173.16:26:57.45#ibcon#about to read 5, iclass 22, count 0 2006.173.16:26:57.45#ibcon#read 5, iclass 22, count 0 2006.173.16:26:57.45#ibcon#about to read 6, iclass 22, count 0 2006.173.16:26:57.45#ibcon#read 6, iclass 22, count 0 2006.173.16:26:57.45#ibcon#end of sib2, iclass 22, count 0 2006.173.16:26:57.45#ibcon#*after write, iclass 22, count 0 2006.173.16:26:57.45#ibcon#*before return 0, iclass 22, count 0 2006.173.16:26:57.45#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.16:26:57.45#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.16:26:57.45#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.16:26:57.45#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.16:26:57.45$vck44/vblo=5,709.99 2006.173.16:26:57.45#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.16:26:57.45#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.16:26:57.45#ibcon#ireg 17 cls_cnt 0 2006.173.16:26:57.45#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.16:26:57.45#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.16:26:57.45#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.16:26:57.45#ibcon#enter wrdev, iclass 24, count 0 2006.173.16:26:57.45#ibcon#first serial, iclass 24, count 0 2006.173.16:26:57.45#ibcon#enter sib2, iclass 24, count 0 2006.173.16:26:57.45#ibcon#flushed, iclass 24, count 0 2006.173.16:26:57.45#ibcon#about to write, iclass 24, count 0 2006.173.16:26:57.45#ibcon#wrote, iclass 24, count 0 2006.173.16:26:57.45#ibcon#about to read 3, iclass 24, count 0 2006.173.16:26:57.47#ibcon#read 3, iclass 24, count 0 2006.173.16:26:57.47#ibcon#about to read 4, iclass 24, count 0 2006.173.16:26:57.47#ibcon#read 4, iclass 24, count 0 2006.173.16:26:57.47#ibcon#about to read 5, iclass 24, count 0 2006.173.16:26:57.47#ibcon#read 5, iclass 24, count 0 2006.173.16:26:57.47#ibcon#about to read 6, iclass 24, count 0 2006.173.16:26:57.47#ibcon#read 6, iclass 24, count 0 2006.173.16:26:57.47#ibcon#end of sib2, iclass 24, count 0 2006.173.16:26:57.47#ibcon#*mode == 0, iclass 24, count 0 2006.173.16:26:57.47#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.16:26:57.47#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.16:26:57.47#ibcon#*before write, iclass 24, count 0 2006.173.16:26:57.47#ibcon#enter sib2, iclass 24, count 0 2006.173.16:26:57.47#ibcon#flushed, iclass 24, count 0 2006.173.16:26:57.47#ibcon#about to write, iclass 24, count 0 2006.173.16:26:57.47#ibcon#wrote, iclass 24, count 0 2006.173.16:26:57.47#ibcon#about to read 3, iclass 24, count 0 2006.173.16:26:57.51#ibcon#read 3, iclass 24, count 0 2006.173.16:26:57.51#ibcon#about to read 4, iclass 24, count 0 2006.173.16:26:57.51#ibcon#read 4, iclass 24, count 0 2006.173.16:26:57.51#ibcon#about to read 5, iclass 24, count 0 2006.173.16:26:57.51#ibcon#read 5, iclass 24, count 0 2006.173.16:26:57.51#ibcon#about to read 6, iclass 24, count 0 2006.173.16:26:57.51#ibcon#read 6, iclass 24, count 0 2006.173.16:26:57.51#ibcon#end of sib2, iclass 24, count 0 2006.173.16:26:57.51#ibcon#*after write, iclass 24, count 0 2006.173.16:26:57.51#ibcon#*before return 0, iclass 24, count 0 2006.173.16:26:57.51#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.16:26:57.51#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.16:26:57.51#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.16:26:57.51#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.16:26:57.51$vck44/vb=5,4 2006.173.16:26:57.51#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.16:26:57.51#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.16:26:57.51#ibcon#ireg 11 cls_cnt 2 2006.173.16:26:57.51#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.16:26:57.57#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.16:26:57.57#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.16:26:57.57#ibcon#enter wrdev, iclass 26, count 2 2006.173.16:26:57.57#ibcon#first serial, iclass 26, count 2 2006.173.16:26:57.57#ibcon#enter sib2, iclass 26, count 2 2006.173.16:26:57.57#ibcon#flushed, iclass 26, count 2 2006.173.16:26:57.57#ibcon#about to write, iclass 26, count 2 2006.173.16:26:57.57#ibcon#wrote, iclass 26, count 2 2006.173.16:26:57.57#ibcon#about to read 3, iclass 26, count 2 2006.173.16:26:57.59#ibcon#read 3, iclass 26, count 2 2006.173.16:26:57.59#ibcon#about to read 4, iclass 26, count 2 2006.173.16:26:57.59#ibcon#read 4, iclass 26, count 2 2006.173.16:26:57.59#ibcon#about to read 5, iclass 26, count 2 2006.173.16:26:57.59#ibcon#read 5, iclass 26, count 2 2006.173.16:26:57.59#ibcon#about to read 6, iclass 26, count 2 2006.173.16:26:57.59#ibcon#read 6, iclass 26, count 2 2006.173.16:26:57.59#ibcon#end of sib2, iclass 26, count 2 2006.173.16:26:57.59#ibcon#*mode == 0, iclass 26, count 2 2006.173.16:26:57.59#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.16:26:57.59#ibcon#[27=AT05-04\r\n] 2006.173.16:26:57.59#ibcon#*before write, iclass 26, count 2 2006.173.16:26:57.59#ibcon#enter sib2, iclass 26, count 2 2006.173.16:26:57.59#ibcon#flushed, iclass 26, count 2 2006.173.16:26:57.59#ibcon#about to write, iclass 26, count 2 2006.173.16:26:57.59#ibcon#wrote, iclass 26, count 2 2006.173.16:26:57.59#ibcon#about to read 3, iclass 26, count 2 2006.173.16:26:57.62#ibcon#read 3, iclass 26, count 2 2006.173.16:26:57.62#ibcon#about to read 4, iclass 26, count 2 2006.173.16:26:57.62#ibcon#read 4, iclass 26, count 2 2006.173.16:26:57.62#ibcon#about to read 5, iclass 26, count 2 2006.173.16:26:57.62#ibcon#read 5, iclass 26, count 2 2006.173.16:26:57.62#ibcon#about to read 6, iclass 26, count 2 2006.173.16:26:57.62#ibcon#read 6, iclass 26, count 2 2006.173.16:26:57.62#ibcon#end of sib2, iclass 26, count 2 2006.173.16:26:57.62#ibcon#*after write, iclass 26, count 2 2006.173.16:26:57.62#ibcon#*before return 0, iclass 26, count 2 2006.173.16:26:57.62#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.16:26:57.62#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.16:26:57.62#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.16:26:57.62#ibcon#ireg 7 cls_cnt 0 2006.173.16:26:57.62#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.16:26:57.74#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.16:26:57.74#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.16:26:57.74#ibcon#enter wrdev, iclass 26, count 0 2006.173.16:26:57.74#ibcon#first serial, iclass 26, count 0 2006.173.16:26:57.74#ibcon#enter sib2, iclass 26, count 0 2006.173.16:26:57.74#ibcon#flushed, iclass 26, count 0 2006.173.16:26:57.74#ibcon#about to write, iclass 26, count 0 2006.173.16:26:57.74#ibcon#wrote, iclass 26, count 0 2006.173.16:26:57.74#ibcon#about to read 3, iclass 26, count 0 2006.173.16:26:57.76#ibcon#read 3, iclass 26, count 0 2006.173.16:26:57.76#ibcon#about to read 4, iclass 26, count 0 2006.173.16:26:57.76#ibcon#read 4, iclass 26, count 0 2006.173.16:26:57.76#ibcon#about to read 5, iclass 26, count 0 2006.173.16:26:57.76#ibcon#read 5, iclass 26, count 0 2006.173.16:26:57.76#ibcon#about to read 6, iclass 26, count 0 2006.173.16:26:57.76#ibcon#read 6, iclass 26, count 0 2006.173.16:26:57.76#ibcon#end of sib2, iclass 26, count 0 2006.173.16:26:57.76#ibcon#*mode == 0, iclass 26, count 0 2006.173.16:26:57.76#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.16:26:57.76#ibcon#[27=USB\r\n] 2006.173.16:26:57.76#ibcon#*before write, iclass 26, count 0 2006.173.16:26:57.76#ibcon#enter sib2, iclass 26, count 0 2006.173.16:26:57.76#ibcon#flushed, iclass 26, count 0 2006.173.16:26:57.76#ibcon#about to write, iclass 26, count 0 2006.173.16:26:57.76#ibcon#wrote, iclass 26, count 0 2006.173.16:26:57.76#ibcon#about to read 3, iclass 26, count 0 2006.173.16:26:57.79#ibcon#read 3, iclass 26, count 0 2006.173.16:26:57.79#ibcon#about to read 4, iclass 26, count 0 2006.173.16:26:57.79#ibcon#read 4, iclass 26, count 0 2006.173.16:26:57.79#ibcon#about to read 5, iclass 26, count 0 2006.173.16:26:57.79#ibcon#read 5, iclass 26, count 0 2006.173.16:26:57.79#ibcon#about to read 6, iclass 26, count 0 2006.173.16:26:57.79#ibcon#read 6, iclass 26, count 0 2006.173.16:26:57.79#ibcon#end of sib2, iclass 26, count 0 2006.173.16:26:57.79#ibcon#*after write, iclass 26, count 0 2006.173.16:26:57.79#ibcon#*before return 0, iclass 26, count 0 2006.173.16:26:57.79#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.16:26:57.79#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.16:26:57.79#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.16:26:57.79#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.16:26:57.79$vck44/vblo=6,719.99 2006.173.16:26:57.79#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.16:26:57.79#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.16:26:57.79#ibcon#ireg 17 cls_cnt 0 2006.173.16:26:57.79#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.16:26:57.79#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.16:26:57.79#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.16:26:57.79#ibcon#enter wrdev, iclass 28, count 0 2006.173.16:26:57.79#ibcon#first serial, iclass 28, count 0 2006.173.16:26:57.79#ibcon#enter sib2, iclass 28, count 0 2006.173.16:26:57.79#ibcon#flushed, iclass 28, count 0 2006.173.16:26:57.79#ibcon#about to write, iclass 28, count 0 2006.173.16:26:57.79#ibcon#wrote, iclass 28, count 0 2006.173.16:26:57.79#ibcon#about to read 3, iclass 28, count 0 2006.173.16:26:57.81#ibcon#read 3, iclass 28, count 0 2006.173.16:26:57.81#ibcon#about to read 4, iclass 28, count 0 2006.173.16:26:57.81#ibcon#read 4, iclass 28, count 0 2006.173.16:26:57.81#ibcon#about to read 5, iclass 28, count 0 2006.173.16:26:57.81#ibcon#read 5, iclass 28, count 0 2006.173.16:26:57.81#ibcon#about to read 6, iclass 28, count 0 2006.173.16:26:57.81#ibcon#read 6, iclass 28, count 0 2006.173.16:26:57.81#ibcon#end of sib2, iclass 28, count 0 2006.173.16:26:57.81#ibcon#*mode == 0, iclass 28, count 0 2006.173.16:26:57.81#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.16:26:57.81#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.16:26:57.81#ibcon#*before write, iclass 28, count 0 2006.173.16:26:57.81#ibcon#enter sib2, iclass 28, count 0 2006.173.16:26:57.81#ibcon#flushed, iclass 28, count 0 2006.173.16:26:57.81#ibcon#about to write, iclass 28, count 0 2006.173.16:26:57.81#ibcon#wrote, iclass 28, count 0 2006.173.16:26:57.81#ibcon#about to read 3, iclass 28, count 0 2006.173.16:26:57.85#ibcon#read 3, iclass 28, count 0 2006.173.16:26:57.85#ibcon#about to read 4, iclass 28, count 0 2006.173.16:26:57.85#ibcon#read 4, iclass 28, count 0 2006.173.16:26:57.85#ibcon#about to read 5, iclass 28, count 0 2006.173.16:26:57.85#ibcon#read 5, iclass 28, count 0 2006.173.16:26:57.85#ibcon#about to read 6, iclass 28, count 0 2006.173.16:26:57.85#ibcon#read 6, iclass 28, count 0 2006.173.16:26:57.85#ibcon#end of sib2, iclass 28, count 0 2006.173.16:26:57.85#ibcon#*after write, iclass 28, count 0 2006.173.16:26:57.85#ibcon#*before return 0, iclass 28, count 0 2006.173.16:26:57.85#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.16:26:57.85#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.16:26:57.85#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.16:26:57.85#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.16:26:57.85$vck44/vb=6,4 2006.173.16:26:57.85#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.16:26:57.85#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.16:26:57.85#ibcon#ireg 11 cls_cnt 2 2006.173.16:26:57.85#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.16:26:57.91#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.16:26:57.91#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.16:26:57.91#ibcon#enter wrdev, iclass 30, count 2 2006.173.16:26:57.91#ibcon#first serial, iclass 30, count 2 2006.173.16:26:57.91#ibcon#enter sib2, iclass 30, count 2 2006.173.16:26:57.91#ibcon#flushed, iclass 30, count 2 2006.173.16:26:57.91#ibcon#about to write, iclass 30, count 2 2006.173.16:26:57.91#ibcon#wrote, iclass 30, count 2 2006.173.16:26:57.91#ibcon#about to read 3, iclass 30, count 2 2006.173.16:26:57.93#ibcon#read 3, iclass 30, count 2 2006.173.16:26:57.93#ibcon#about to read 4, iclass 30, count 2 2006.173.16:26:57.93#ibcon#read 4, iclass 30, count 2 2006.173.16:26:57.93#ibcon#about to read 5, iclass 30, count 2 2006.173.16:26:57.93#ibcon#read 5, iclass 30, count 2 2006.173.16:26:57.93#ibcon#about to read 6, iclass 30, count 2 2006.173.16:26:57.93#ibcon#read 6, iclass 30, count 2 2006.173.16:26:57.93#ibcon#end of sib2, iclass 30, count 2 2006.173.16:26:57.93#ibcon#*mode == 0, iclass 30, count 2 2006.173.16:26:57.93#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.16:26:57.93#ibcon#[27=AT06-04\r\n] 2006.173.16:26:57.93#ibcon#*before write, iclass 30, count 2 2006.173.16:26:57.93#ibcon#enter sib2, iclass 30, count 2 2006.173.16:26:57.93#ibcon#flushed, iclass 30, count 2 2006.173.16:26:57.93#ibcon#about to write, iclass 30, count 2 2006.173.16:26:57.93#ibcon#wrote, iclass 30, count 2 2006.173.16:26:57.93#ibcon#about to read 3, iclass 30, count 2 2006.173.16:26:57.96#ibcon#read 3, iclass 30, count 2 2006.173.16:26:57.96#ibcon#about to read 4, iclass 30, count 2 2006.173.16:26:57.96#ibcon#read 4, iclass 30, count 2 2006.173.16:26:57.96#ibcon#about to read 5, iclass 30, count 2 2006.173.16:26:57.96#ibcon#read 5, iclass 30, count 2 2006.173.16:26:57.96#ibcon#about to read 6, iclass 30, count 2 2006.173.16:26:57.96#ibcon#read 6, iclass 30, count 2 2006.173.16:26:57.96#ibcon#end of sib2, iclass 30, count 2 2006.173.16:26:57.96#ibcon#*after write, iclass 30, count 2 2006.173.16:26:57.96#ibcon#*before return 0, iclass 30, count 2 2006.173.16:26:57.96#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.16:26:57.96#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.16:26:57.96#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.16:26:57.96#ibcon#ireg 7 cls_cnt 0 2006.173.16:26:57.96#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.16:26:58.08#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.16:26:58.08#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.16:26:58.08#ibcon#enter wrdev, iclass 30, count 0 2006.173.16:26:58.08#ibcon#first serial, iclass 30, count 0 2006.173.16:26:58.08#ibcon#enter sib2, iclass 30, count 0 2006.173.16:26:58.08#ibcon#flushed, iclass 30, count 0 2006.173.16:26:58.08#ibcon#about to write, iclass 30, count 0 2006.173.16:26:58.08#ibcon#wrote, iclass 30, count 0 2006.173.16:26:58.08#ibcon#about to read 3, iclass 30, count 0 2006.173.16:26:58.10#ibcon#read 3, iclass 30, count 0 2006.173.16:26:58.10#ibcon#about to read 4, iclass 30, count 0 2006.173.16:26:58.10#ibcon#read 4, iclass 30, count 0 2006.173.16:26:58.10#ibcon#about to read 5, iclass 30, count 0 2006.173.16:26:58.10#ibcon#read 5, iclass 30, count 0 2006.173.16:26:58.10#ibcon#about to read 6, iclass 30, count 0 2006.173.16:26:58.10#ibcon#read 6, iclass 30, count 0 2006.173.16:26:58.10#ibcon#end of sib2, iclass 30, count 0 2006.173.16:26:58.10#ibcon#*mode == 0, iclass 30, count 0 2006.173.16:26:58.10#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.16:26:58.10#ibcon#[27=USB\r\n] 2006.173.16:26:58.10#ibcon#*before write, iclass 30, count 0 2006.173.16:26:58.10#ibcon#enter sib2, iclass 30, count 0 2006.173.16:26:58.10#ibcon#flushed, iclass 30, count 0 2006.173.16:26:58.10#ibcon#about to write, iclass 30, count 0 2006.173.16:26:58.10#ibcon#wrote, iclass 30, count 0 2006.173.16:26:58.10#ibcon#about to read 3, iclass 30, count 0 2006.173.16:26:58.13#ibcon#read 3, iclass 30, count 0 2006.173.16:26:58.13#ibcon#about to read 4, iclass 30, count 0 2006.173.16:26:58.13#ibcon#read 4, iclass 30, count 0 2006.173.16:26:58.13#ibcon#about to read 5, iclass 30, count 0 2006.173.16:26:58.13#ibcon#read 5, iclass 30, count 0 2006.173.16:26:58.13#ibcon#about to read 6, iclass 30, count 0 2006.173.16:26:58.13#ibcon#read 6, iclass 30, count 0 2006.173.16:26:58.13#ibcon#end of sib2, iclass 30, count 0 2006.173.16:26:58.13#ibcon#*after write, iclass 30, count 0 2006.173.16:26:58.13#ibcon#*before return 0, iclass 30, count 0 2006.173.16:26:58.13#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.16:26:58.13#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.16:26:58.13#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.16:26:58.13#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.16:26:58.13$vck44/vblo=7,734.99 2006.173.16:26:58.13#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.16:26:58.13#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.16:26:58.13#ibcon#ireg 17 cls_cnt 0 2006.173.16:26:58.13#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.16:26:58.13#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.16:26:58.13#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.16:26:58.13#ibcon#enter wrdev, iclass 32, count 0 2006.173.16:26:58.13#ibcon#first serial, iclass 32, count 0 2006.173.16:26:58.13#ibcon#enter sib2, iclass 32, count 0 2006.173.16:26:58.13#ibcon#flushed, iclass 32, count 0 2006.173.16:26:58.13#ibcon#about to write, iclass 32, count 0 2006.173.16:26:58.13#ibcon#wrote, iclass 32, count 0 2006.173.16:26:58.13#ibcon#about to read 3, iclass 32, count 0 2006.173.16:26:58.15#ibcon#read 3, iclass 32, count 0 2006.173.16:26:58.15#ibcon#about to read 4, iclass 32, count 0 2006.173.16:26:58.15#ibcon#read 4, iclass 32, count 0 2006.173.16:26:58.15#ibcon#about to read 5, iclass 32, count 0 2006.173.16:26:58.15#ibcon#read 5, iclass 32, count 0 2006.173.16:26:58.15#ibcon#about to read 6, iclass 32, count 0 2006.173.16:26:58.15#ibcon#read 6, iclass 32, count 0 2006.173.16:26:58.15#ibcon#end of sib2, iclass 32, count 0 2006.173.16:26:58.15#ibcon#*mode == 0, iclass 32, count 0 2006.173.16:26:58.15#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.16:26:58.15#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.16:26:58.15#ibcon#*before write, iclass 32, count 0 2006.173.16:26:58.15#ibcon#enter sib2, iclass 32, count 0 2006.173.16:26:58.15#ibcon#flushed, iclass 32, count 0 2006.173.16:26:58.15#ibcon#about to write, iclass 32, count 0 2006.173.16:26:58.15#ibcon#wrote, iclass 32, count 0 2006.173.16:26:58.15#ibcon#about to read 3, iclass 32, count 0 2006.173.16:26:58.19#ibcon#read 3, iclass 32, count 0 2006.173.16:26:58.19#ibcon#about to read 4, iclass 32, count 0 2006.173.16:26:58.19#ibcon#read 4, iclass 32, count 0 2006.173.16:26:58.19#ibcon#about to read 5, iclass 32, count 0 2006.173.16:26:58.19#ibcon#read 5, iclass 32, count 0 2006.173.16:26:58.19#ibcon#about to read 6, iclass 32, count 0 2006.173.16:26:58.19#ibcon#read 6, iclass 32, count 0 2006.173.16:26:58.19#ibcon#end of sib2, iclass 32, count 0 2006.173.16:26:58.19#ibcon#*after write, iclass 32, count 0 2006.173.16:26:58.19#ibcon#*before return 0, iclass 32, count 0 2006.173.16:26:58.19#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.16:26:58.19#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.16:26:58.19#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.16:26:58.19#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.16:26:58.19$vck44/vb=7,4 2006.173.16:26:58.19#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.16:26:58.19#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.16:26:58.19#ibcon#ireg 11 cls_cnt 2 2006.173.16:26:58.19#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.16:26:58.25#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.16:26:58.25#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.16:26:58.25#ibcon#enter wrdev, iclass 34, count 2 2006.173.16:26:58.25#ibcon#first serial, iclass 34, count 2 2006.173.16:26:58.25#ibcon#enter sib2, iclass 34, count 2 2006.173.16:26:58.25#ibcon#flushed, iclass 34, count 2 2006.173.16:26:58.25#ibcon#about to write, iclass 34, count 2 2006.173.16:26:58.25#ibcon#wrote, iclass 34, count 2 2006.173.16:26:58.25#ibcon#about to read 3, iclass 34, count 2 2006.173.16:26:58.27#ibcon#read 3, iclass 34, count 2 2006.173.16:26:58.27#ibcon#about to read 4, iclass 34, count 2 2006.173.16:26:58.27#ibcon#read 4, iclass 34, count 2 2006.173.16:26:58.27#ibcon#about to read 5, iclass 34, count 2 2006.173.16:26:58.27#ibcon#read 5, iclass 34, count 2 2006.173.16:26:58.27#ibcon#about to read 6, iclass 34, count 2 2006.173.16:26:58.27#ibcon#read 6, iclass 34, count 2 2006.173.16:26:58.27#ibcon#end of sib2, iclass 34, count 2 2006.173.16:26:58.27#ibcon#*mode == 0, iclass 34, count 2 2006.173.16:26:58.27#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.16:26:58.27#ibcon#[27=AT07-04\r\n] 2006.173.16:26:58.27#ibcon#*before write, iclass 34, count 2 2006.173.16:26:58.27#ibcon#enter sib2, iclass 34, count 2 2006.173.16:26:58.27#ibcon#flushed, iclass 34, count 2 2006.173.16:26:58.27#ibcon#about to write, iclass 34, count 2 2006.173.16:26:58.27#ibcon#wrote, iclass 34, count 2 2006.173.16:26:58.27#ibcon#about to read 3, iclass 34, count 2 2006.173.16:26:58.30#ibcon#read 3, iclass 34, count 2 2006.173.16:26:58.30#ibcon#about to read 4, iclass 34, count 2 2006.173.16:26:58.30#ibcon#read 4, iclass 34, count 2 2006.173.16:26:58.30#ibcon#about to read 5, iclass 34, count 2 2006.173.16:26:58.30#ibcon#read 5, iclass 34, count 2 2006.173.16:26:58.30#ibcon#about to read 6, iclass 34, count 2 2006.173.16:26:58.30#ibcon#read 6, iclass 34, count 2 2006.173.16:26:58.30#ibcon#end of sib2, iclass 34, count 2 2006.173.16:26:58.30#ibcon#*after write, iclass 34, count 2 2006.173.16:26:58.30#ibcon#*before return 0, iclass 34, count 2 2006.173.16:26:58.30#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.16:26:58.30#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.16:26:58.30#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.16:26:58.30#ibcon#ireg 7 cls_cnt 0 2006.173.16:26:58.30#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.16:26:58.42#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.16:26:58.42#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.16:26:58.42#ibcon#enter wrdev, iclass 34, count 0 2006.173.16:26:58.42#ibcon#first serial, iclass 34, count 0 2006.173.16:26:58.42#ibcon#enter sib2, iclass 34, count 0 2006.173.16:26:58.42#ibcon#flushed, iclass 34, count 0 2006.173.16:26:58.42#ibcon#about to write, iclass 34, count 0 2006.173.16:26:58.42#ibcon#wrote, iclass 34, count 0 2006.173.16:26:58.42#ibcon#about to read 3, iclass 34, count 0 2006.173.16:26:58.44#ibcon#read 3, iclass 34, count 0 2006.173.16:26:58.44#ibcon#about to read 4, iclass 34, count 0 2006.173.16:26:58.44#ibcon#read 4, iclass 34, count 0 2006.173.16:26:58.44#ibcon#about to read 5, iclass 34, count 0 2006.173.16:26:58.44#ibcon#read 5, iclass 34, count 0 2006.173.16:26:58.44#ibcon#about to read 6, iclass 34, count 0 2006.173.16:26:58.44#ibcon#read 6, iclass 34, count 0 2006.173.16:26:58.44#ibcon#end of sib2, iclass 34, count 0 2006.173.16:26:58.44#ibcon#*mode == 0, iclass 34, count 0 2006.173.16:26:58.44#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.16:26:58.44#ibcon#[27=USB\r\n] 2006.173.16:26:58.44#ibcon#*before write, iclass 34, count 0 2006.173.16:26:58.44#ibcon#enter sib2, iclass 34, count 0 2006.173.16:26:58.44#ibcon#flushed, iclass 34, count 0 2006.173.16:26:58.44#ibcon#about to write, iclass 34, count 0 2006.173.16:26:58.44#ibcon#wrote, iclass 34, count 0 2006.173.16:26:58.44#ibcon#about to read 3, iclass 34, count 0 2006.173.16:26:58.47#ibcon#read 3, iclass 34, count 0 2006.173.16:26:58.47#ibcon#about to read 4, iclass 34, count 0 2006.173.16:26:58.47#ibcon#read 4, iclass 34, count 0 2006.173.16:26:58.47#ibcon#about to read 5, iclass 34, count 0 2006.173.16:26:58.47#ibcon#read 5, iclass 34, count 0 2006.173.16:26:58.47#ibcon#about to read 6, iclass 34, count 0 2006.173.16:26:58.47#ibcon#read 6, iclass 34, count 0 2006.173.16:26:58.47#ibcon#end of sib2, iclass 34, count 0 2006.173.16:26:58.47#ibcon#*after write, iclass 34, count 0 2006.173.16:26:58.47#ibcon#*before return 0, iclass 34, count 0 2006.173.16:26:58.47#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.16:26:58.47#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.16:26:58.47#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.16:26:58.47#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.16:26:58.47$vck44/vblo=8,744.99 2006.173.16:26:58.47#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.16:26:58.47#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.16:26:58.47#ibcon#ireg 17 cls_cnt 0 2006.173.16:26:58.47#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.16:26:58.47#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.16:26:58.47#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.16:26:58.47#ibcon#enter wrdev, iclass 36, count 0 2006.173.16:26:58.47#ibcon#first serial, iclass 36, count 0 2006.173.16:26:58.47#ibcon#enter sib2, iclass 36, count 0 2006.173.16:26:58.47#ibcon#flushed, iclass 36, count 0 2006.173.16:26:58.47#ibcon#about to write, iclass 36, count 0 2006.173.16:26:58.47#ibcon#wrote, iclass 36, count 0 2006.173.16:26:58.47#ibcon#about to read 3, iclass 36, count 0 2006.173.16:26:58.49#ibcon#read 3, iclass 36, count 0 2006.173.16:26:58.49#ibcon#about to read 4, iclass 36, count 0 2006.173.16:26:58.49#ibcon#read 4, iclass 36, count 0 2006.173.16:26:58.49#ibcon#about to read 5, iclass 36, count 0 2006.173.16:26:58.49#ibcon#read 5, iclass 36, count 0 2006.173.16:26:58.49#ibcon#about to read 6, iclass 36, count 0 2006.173.16:26:58.49#ibcon#read 6, iclass 36, count 0 2006.173.16:26:58.49#ibcon#end of sib2, iclass 36, count 0 2006.173.16:26:58.49#ibcon#*mode == 0, iclass 36, count 0 2006.173.16:26:58.49#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.16:26:58.49#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.16:26:58.49#ibcon#*before write, iclass 36, count 0 2006.173.16:26:58.49#ibcon#enter sib2, iclass 36, count 0 2006.173.16:26:58.49#ibcon#flushed, iclass 36, count 0 2006.173.16:26:58.49#ibcon#about to write, iclass 36, count 0 2006.173.16:26:58.49#ibcon#wrote, iclass 36, count 0 2006.173.16:26:58.49#ibcon#about to read 3, iclass 36, count 0 2006.173.16:26:58.53#ibcon#read 3, iclass 36, count 0 2006.173.16:26:58.53#ibcon#about to read 4, iclass 36, count 0 2006.173.16:26:58.53#ibcon#read 4, iclass 36, count 0 2006.173.16:26:58.53#ibcon#about to read 5, iclass 36, count 0 2006.173.16:26:58.53#ibcon#read 5, iclass 36, count 0 2006.173.16:26:58.53#ibcon#about to read 6, iclass 36, count 0 2006.173.16:26:58.53#ibcon#read 6, iclass 36, count 0 2006.173.16:26:58.53#ibcon#end of sib2, iclass 36, count 0 2006.173.16:26:58.53#ibcon#*after write, iclass 36, count 0 2006.173.16:26:58.53#ibcon#*before return 0, iclass 36, count 0 2006.173.16:26:58.53#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.16:26:58.53#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.16:26:58.53#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.16:26:58.53#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.16:26:58.53$vck44/vb=8,4 2006.173.16:26:58.53#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.16:26:58.53#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.16:26:58.53#ibcon#ireg 11 cls_cnt 2 2006.173.16:26:58.53#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.16:26:58.59#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.16:26:58.59#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.16:26:58.59#ibcon#enter wrdev, iclass 38, count 2 2006.173.16:26:58.59#ibcon#first serial, iclass 38, count 2 2006.173.16:26:58.59#ibcon#enter sib2, iclass 38, count 2 2006.173.16:26:58.59#ibcon#flushed, iclass 38, count 2 2006.173.16:26:58.59#ibcon#about to write, iclass 38, count 2 2006.173.16:26:58.59#ibcon#wrote, iclass 38, count 2 2006.173.16:26:58.59#ibcon#about to read 3, iclass 38, count 2 2006.173.16:26:58.61#ibcon#read 3, iclass 38, count 2 2006.173.16:26:58.61#ibcon#about to read 4, iclass 38, count 2 2006.173.16:26:58.61#ibcon#read 4, iclass 38, count 2 2006.173.16:26:58.61#ibcon#about to read 5, iclass 38, count 2 2006.173.16:26:58.61#ibcon#read 5, iclass 38, count 2 2006.173.16:26:58.61#ibcon#about to read 6, iclass 38, count 2 2006.173.16:26:58.61#ibcon#read 6, iclass 38, count 2 2006.173.16:26:58.61#ibcon#end of sib2, iclass 38, count 2 2006.173.16:26:58.61#ibcon#*mode == 0, iclass 38, count 2 2006.173.16:26:58.61#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.16:26:58.61#ibcon#[27=AT08-04\r\n] 2006.173.16:26:58.61#ibcon#*before write, iclass 38, count 2 2006.173.16:26:58.61#ibcon#enter sib2, iclass 38, count 2 2006.173.16:26:58.61#ibcon#flushed, iclass 38, count 2 2006.173.16:26:58.61#ibcon#about to write, iclass 38, count 2 2006.173.16:26:58.61#ibcon#wrote, iclass 38, count 2 2006.173.16:26:58.61#ibcon#about to read 3, iclass 38, count 2 2006.173.16:26:58.64#ibcon#read 3, iclass 38, count 2 2006.173.16:26:58.64#ibcon#about to read 4, iclass 38, count 2 2006.173.16:26:58.64#ibcon#read 4, iclass 38, count 2 2006.173.16:26:58.64#ibcon#about to read 5, iclass 38, count 2 2006.173.16:26:58.64#ibcon#read 5, iclass 38, count 2 2006.173.16:26:58.64#ibcon#about to read 6, iclass 38, count 2 2006.173.16:26:58.64#ibcon#read 6, iclass 38, count 2 2006.173.16:26:58.64#ibcon#end of sib2, iclass 38, count 2 2006.173.16:26:58.64#ibcon#*after write, iclass 38, count 2 2006.173.16:26:58.64#ibcon#*before return 0, iclass 38, count 2 2006.173.16:26:58.64#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.16:26:58.64#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.16:26:58.64#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.16:26:58.64#ibcon#ireg 7 cls_cnt 0 2006.173.16:26:58.64#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.16:26:58.76#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.16:26:58.76#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.16:26:58.76#ibcon#enter wrdev, iclass 38, count 0 2006.173.16:26:58.76#ibcon#first serial, iclass 38, count 0 2006.173.16:26:58.76#ibcon#enter sib2, iclass 38, count 0 2006.173.16:26:58.76#ibcon#flushed, iclass 38, count 0 2006.173.16:26:58.76#ibcon#about to write, iclass 38, count 0 2006.173.16:26:58.76#ibcon#wrote, iclass 38, count 0 2006.173.16:26:58.76#ibcon#about to read 3, iclass 38, count 0 2006.173.16:26:58.78#ibcon#read 3, iclass 38, count 0 2006.173.16:26:58.78#ibcon#about to read 4, iclass 38, count 0 2006.173.16:26:58.78#ibcon#read 4, iclass 38, count 0 2006.173.16:26:58.78#ibcon#about to read 5, iclass 38, count 0 2006.173.16:26:58.78#ibcon#read 5, iclass 38, count 0 2006.173.16:26:58.78#ibcon#about to read 6, iclass 38, count 0 2006.173.16:26:58.78#ibcon#read 6, iclass 38, count 0 2006.173.16:26:58.78#ibcon#end of sib2, iclass 38, count 0 2006.173.16:26:58.78#ibcon#*mode == 0, iclass 38, count 0 2006.173.16:26:58.78#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.16:26:58.78#ibcon#[27=USB\r\n] 2006.173.16:26:58.78#ibcon#*before write, iclass 38, count 0 2006.173.16:26:58.78#ibcon#enter sib2, iclass 38, count 0 2006.173.16:26:58.78#ibcon#flushed, iclass 38, count 0 2006.173.16:26:58.78#ibcon#about to write, iclass 38, count 0 2006.173.16:26:58.78#ibcon#wrote, iclass 38, count 0 2006.173.16:26:58.78#ibcon#about to read 3, iclass 38, count 0 2006.173.16:26:58.81#ibcon#read 3, iclass 38, count 0 2006.173.16:26:58.81#ibcon#about to read 4, iclass 38, count 0 2006.173.16:26:58.81#ibcon#read 4, iclass 38, count 0 2006.173.16:26:58.81#ibcon#about to read 5, iclass 38, count 0 2006.173.16:26:58.81#ibcon#read 5, iclass 38, count 0 2006.173.16:26:58.81#ibcon#about to read 6, iclass 38, count 0 2006.173.16:26:58.81#ibcon#read 6, iclass 38, count 0 2006.173.16:26:58.81#ibcon#end of sib2, iclass 38, count 0 2006.173.16:26:58.81#ibcon#*after write, iclass 38, count 0 2006.173.16:26:58.81#ibcon#*before return 0, iclass 38, count 0 2006.173.16:26:58.81#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.16:26:58.81#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.16:26:58.81#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.16:26:58.81#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.16:26:58.81$vck44/vabw=wide 2006.173.16:26:58.81#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.16:26:58.81#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.16:26:58.81#ibcon#ireg 8 cls_cnt 0 2006.173.16:26:58.81#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.16:26:58.81#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.16:26:58.81#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.16:26:58.81#ibcon#enter wrdev, iclass 40, count 0 2006.173.16:26:58.81#ibcon#first serial, iclass 40, count 0 2006.173.16:26:58.81#ibcon#enter sib2, iclass 40, count 0 2006.173.16:26:58.81#ibcon#flushed, iclass 40, count 0 2006.173.16:26:58.81#ibcon#about to write, iclass 40, count 0 2006.173.16:26:58.81#ibcon#wrote, iclass 40, count 0 2006.173.16:26:58.81#ibcon#about to read 3, iclass 40, count 0 2006.173.16:26:58.83#ibcon#read 3, iclass 40, count 0 2006.173.16:26:58.83#ibcon#about to read 4, iclass 40, count 0 2006.173.16:26:58.83#ibcon#read 4, iclass 40, count 0 2006.173.16:26:58.83#ibcon#about to read 5, iclass 40, count 0 2006.173.16:26:58.83#ibcon#read 5, iclass 40, count 0 2006.173.16:26:58.83#ibcon#about to read 6, iclass 40, count 0 2006.173.16:26:58.83#ibcon#read 6, iclass 40, count 0 2006.173.16:26:58.83#ibcon#end of sib2, iclass 40, count 0 2006.173.16:26:58.83#ibcon#*mode == 0, iclass 40, count 0 2006.173.16:26:58.83#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.16:26:58.83#ibcon#[25=BW32\r\n] 2006.173.16:26:58.83#ibcon#*before write, iclass 40, count 0 2006.173.16:26:58.83#ibcon#enter sib2, iclass 40, count 0 2006.173.16:26:58.83#ibcon#flushed, iclass 40, count 0 2006.173.16:26:58.83#ibcon#about to write, iclass 40, count 0 2006.173.16:26:58.83#ibcon#wrote, iclass 40, count 0 2006.173.16:26:58.83#ibcon#about to read 3, iclass 40, count 0 2006.173.16:26:58.86#ibcon#read 3, iclass 40, count 0 2006.173.16:26:58.86#ibcon#about to read 4, iclass 40, count 0 2006.173.16:26:58.86#ibcon#read 4, iclass 40, count 0 2006.173.16:26:58.86#ibcon#about to read 5, iclass 40, count 0 2006.173.16:26:58.86#ibcon#read 5, iclass 40, count 0 2006.173.16:26:58.86#ibcon#about to read 6, iclass 40, count 0 2006.173.16:26:58.86#ibcon#read 6, iclass 40, count 0 2006.173.16:26:58.86#ibcon#end of sib2, iclass 40, count 0 2006.173.16:26:58.86#ibcon#*after write, iclass 40, count 0 2006.173.16:26:58.86#ibcon#*before return 0, iclass 40, count 0 2006.173.16:26:58.86#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.16:26:58.86#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.16:26:58.86#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.16:26:58.86#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.16:26:58.86$vck44/vbbw=wide 2006.173.16:26:58.86#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.16:26:58.86#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.16:26:58.86#ibcon#ireg 8 cls_cnt 0 2006.173.16:26:58.86#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.16:26:58.93#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.16:26:58.93#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.16:26:58.93#ibcon#enter wrdev, iclass 4, count 0 2006.173.16:26:58.93#ibcon#first serial, iclass 4, count 0 2006.173.16:26:58.93#ibcon#enter sib2, iclass 4, count 0 2006.173.16:26:58.93#ibcon#flushed, iclass 4, count 0 2006.173.16:26:58.93#ibcon#about to write, iclass 4, count 0 2006.173.16:26:58.93#ibcon#wrote, iclass 4, count 0 2006.173.16:26:58.93#ibcon#about to read 3, iclass 4, count 0 2006.173.16:26:58.95#ibcon#read 3, iclass 4, count 0 2006.173.16:26:58.95#ibcon#about to read 4, iclass 4, count 0 2006.173.16:26:58.95#ibcon#read 4, iclass 4, count 0 2006.173.16:26:58.95#ibcon#about to read 5, iclass 4, count 0 2006.173.16:26:58.95#ibcon#read 5, iclass 4, count 0 2006.173.16:26:58.95#ibcon#about to read 6, iclass 4, count 0 2006.173.16:26:58.95#ibcon#read 6, iclass 4, count 0 2006.173.16:26:58.95#ibcon#end of sib2, iclass 4, count 0 2006.173.16:26:58.95#ibcon#*mode == 0, iclass 4, count 0 2006.173.16:26:58.95#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.16:26:58.95#ibcon#[27=BW32\r\n] 2006.173.16:26:58.95#ibcon#*before write, iclass 4, count 0 2006.173.16:26:58.95#ibcon#enter sib2, iclass 4, count 0 2006.173.16:26:58.95#ibcon#flushed, iclass 4, count 0 2006.173.16:26:58.95#ibcon#about to write, iclass 4, count 0 2006.173.16:26:58.95#ibcon#wrote, iclass 4, count 0 2006.173.16:26:58.95#ibcon#about to read 3, iclass 4, count 0 2006.173.16:26:58.98#ibcon#read 3, iclass 4, count 0 2006.173.16:26:58.98#ibcon#about to read 4, iclass 4, count 0 2006.173.16:26:58.98#ibcon#read 4, iclass 4, count 0 2006.173.16:26:58.98#ibcon#about to read 5, iclass 4, count 0 2006.173.16:26:58.98#ibcon#read 5, iclass 4, count 0 2006.173.16:26:58.98#ibcon#about to read 6, iclass 4, count 0 2006.173.16:26:58.98#ibcon#read 6, iclass 4, count 0 2006.173.16:26:58.98#ibcon#end of sib2, iclass 4, count 0 2006.173.16:26:58.98#ibcon#*after write, iclass 4, count 0 2006.173.16:26:58.98#ibcon#*before return 0, iclass 4, count 0 2006.173.16:26:58.98#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.16:26:58.98#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.16:26:58.98#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.16:26:58.98#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.16:26:58.98$setupk4/ifdk4 2006.173.16:26:58.98$ifdk4/lo= 2006.173.16:26:58.98$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.16:26:58.98$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.16:26:58.98$ifdk4/patch= 2006.173.16:26:58.98$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.16:26:58.98$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.16:26:58.98$setupk4/!*+20s 2006.173.16:27:02.74#abcon#<5=/14 0.8 2.4 20.461001002.8\r\n> 2006.173.16:27:02.76#abcon#{5=INTERFACE CLEAR} 2006.173.16:27:02.82#abcon#[5=S1D000X0/0*\r\n] 2006.173.16:27:12.91#abcon#<5=/14 0.8 2.4 20.461001002.8\r\n> 2006.173.16:27:12.93#abcon#{5=INTERFACE CLEAR} 2006.173.16:27:12.99#abcon#[5=S1D000X0/0*\r\n] 2006.173.16:27:13.49$setupk4/"tpicd 2006.173.16:27:13.49$setupk4/echo=off 2006.173.16:27:13.49$setupk4/xlog=off 2006.173.16:27:13.49:!2006.173.16:27:37 2006.173.16:27:34.14#trakl#Source acquired 2006.173.16:27:35.14#flagr#flagr/antenna,acquired 2006.173.16:27:37.00:preob 2006.173.16:27:37.14/onsource/TRACKING 2006.173.16:27:37.14:!2006.173.16:27:47 2006.173.16:27:47.00:"tape 2006.173.16:27:47.00:"st=record 2006.173.16:27:47.00:data_valid=on 2006.173.16:27:47.00:midob 2006.173.16:27:47.14/onsource/TRACKING 2006.173.16:27:47.14/wx/20.45,1002.7,100 2006.173.16:27:47.25/cable/+6.5133E-03 2006.173.16:27:48.34/va/01,07,usb,yes,39,42 2006.173.16:27:48.34/va/02,06,usb,yes,39,39 2006.173.16:27:48.34/va/03,05,usb,yes,49,51 2006.173.16:27:48.34/va/04,06,usb,yes,39,42 2006.173.16:27:48.34/va/05,04,usb,yes,31,32 2006.173.16:27:48.34/va/06,03,usb,yes,43,43 2006.173.16:27:48.34/va/07,04,usb,yes,35,36 2006.173.16:27:48.34/va/08,04,usb,yes,30,36 2006.173.16:27:48.57/valo/01,524.99,yes,locked 2006.173.16:27:48.57/valo/02,534.99,yes,locked 2006.173.16:27:48.57/valo/03,564.99,yes,locked 2006.173.16:27:48.57/valo/04,624.99,yes,locked 2006.173.16:27:48.57/valo/05,734.99,yes,locked 2006.173.16:27:48.57/valo/06,814.99,yes,locked 2006.173.16:27:48.57/valo/07,864.99,yes,locked 2006.173.16:27:48.57/valo/08,884.99,yes,locked 2006.173.16:27:49.66/vb/01,04,usb,yes,31,28 2006.173.16:27:49.66/vb/02,04,usb,yes,33,33 2006.173.16:27:49.66/vb/03,04,usb,yes,30,33 2006.173.16:27:49.66/vb/04,04,usb,yes,34,33 2006.173.16:27:49.66/vb/05,04,usb,yes,27,29 2006.173.16:27:49.66/vb/06,04,usb,yes,31,28 2006.173.16:27:49.66/vb/07,04,usb,yes,31,31 2006.173.16:27:49.66/vb/08,04,usb,yes,29,32 2006.173.16:27:49.89/vblo/01,629.99,yes,locked 2006.173.16:27:49.89/vblo/02,634.99,yes,locked 2006.173.16:27:49.89/vblo/03,649.99,yes,locked 2006.173.16:27:49.89/vblo/04,679.99,yes,locked 2006.173.16:27:49.89/vblo/05,709.99,yes,locked 2006.173.16:27:49.89/vblo/06,719.99,yes,locked 2006.173.16:27:49.89/vblo/07,734.99,yes,locked 2006.173.16:27:49.89/vblo/08,744.99,yes,locked 2006.173.16:27:50.04/vabw/8 2006.173.16:27:50.19/vbbw/8 2006.173.16:27:50.28/xfe/off,on,14.5 2006.173.16:27:50.67/ifatt/23,28,28,28 2006.173.16:27:51.08/fmout-gps/S +3.99E-07 2006.173.16:27:51.12:!2006.173.16:28:27 2006.173.16:28:27.00:data_valid=off 2006.173.16:28:27.00:"et 2006.173.16:28:27.00:!+3s 2006.173.16:28:30.01:"tape 2006.173.16:28:30.01:postob 2006.173.16:28:30.20/cable/+6.5110E-03 2006.173.16:28:30.20/wx/20.45,1002.7,100 2006.173.16:28:31.08/fmout-gps/S +3.99E-07 2006.173.16:28:31.08:scan_name=173-1632,jd0606,70 2006.173.16:28:31.08:source=1908-201,191109.65,-200655.1,2000.0,ccw 2006.173.16:28:32.14#flagr#flagr/antenna,new-source 2006.173.16:28:32.14:checkk5 2006.173.16:28:32.57/chk_autoobs//k5ts1/ autoobs is running! 2006.173.16:28:32.98/chk_autoobs//k5ts2/ autoobs is running! 2006.173.16:28:33.38/chk_autoobs//k5ts3/ autoobs is running! 2006.173.16:28:33.78/chk_autoobs//k5ts4/ autoobs is running! 2006.173.16:28:34.16/chk_obsdata//k5ts1/T1731627??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.16:28:34.57/chk_obsdata//k5ts2/T1731627??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.16:28:34.96/chk_obsdata//k5ts3/T1731627??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.16:28:35.37/chk_obsdata//k5ts4/T1731627??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.16:28:36.09/k5log//k5ts1_log_newline 2006.173.16:28:36.80/k5log//k5ts2_log_newline 2006.173.16:28:37.50/k5log//k5ts3_log_newline 2006.173.16:28:38.21/k5log//k5ts4_log_newline 2006.173.16:28:38.24/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.16:28:38.24:setupk4=1 2006.173.16:28:38.24$setupk4/echo=on 2006.173.16:28:38.24$setupk4/pcalon 2006.173.16:28:38.24$pcalon/"no phase cal control is implemented here 2006.173.16:28:38.24$setupk4/"tpicd=stop 2006.173.16:28:38.24$setupk4/"rec=synch_on 2006.173.16:28:38.24$setupk4/"rec_mode=128 2006.173.16:28:38.24$setupk4/!* 2006.173.16:28:38.24$setupk4/recpk4 2006.173.16:28:38.24$recpk4/recpatch= 2006.173.16:28:38.25$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.16:28:38.25$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.16:28:38.25$setupk4/vck44 2006.173.16:28:38.25$vck44/valo=1,524.99 2006.173.16:28:38.25#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.16:28:38.25#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.16:28:38.25#ibcon#ireg 17 cls_cnt 0 2006.173.16:28:38.25#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.16:28:38.25#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.16:28:38.25#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.16:28:38.25#ibcon#enter wrdev, iclass 15, count 0 2006.173.16:28:38.25#ibcon#first serial, iclass 15, count 0 2006.173.16:28:38.25#ibcon#enter sib2, iclass 15, count 0 2006.173.16:28:38.25#ibcon#flushed, iclass 15, count 0 2006.173.16:28:38.25#ibcon#about to write, iclass 15, count 0 2006.173.16:28:38.25#ibcon#wrote, iclass 15, count 0 2006.173.16:28:38.25#ibcon#about to read 3, iclass 15, count 0 2006.173.16:28:38.27#ibcon#read 3, iclass 15, count 0 2006.173.16:28:38.27#ibcon#about to read 4, iclass 15, count 0 2006.173.16:28:38.27#ibcon#read 4, iclass 15, count 0 2006.173.16:28:38.27#ibcon#about to read 5, iclass 15, count 0 2006.173.16:28:38.27#ibcon#read 5, iclass 15, count 0 2006.173.16:28:38.27#ibcon#about to read 6, iclass 15, count 0 2006.173.16:28:38.27#ibcon#read 6, iclass 15, count 0 2006.173.16:28:38.27#ibcon#end of sib2, iclass 15, count 0 2006.173.16:28:38.27#ibcon#*mode == 0, iclass 15, count 0 2006.173.16:28:38.27#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.16:28:38.27#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.16:28:38.27#ibcon#*before write, iclass 15, count 0 2006.173.16:28:38.27#ibcon#enter sib2, iclass 15, count 0 2006.173.16:28:38.27#ibcon#flushed, iclass 15, count 0 2006.173.16:28:38.27#ibcon#about to write, iclass 15, count 0 2006.173.16:28:38.27#ibcon#wrote, iclass 15, count 0 2006.173.16:28:38.27#ibcon#about to read 3, iclass 15, count 0 2006.173.16:28:38.32#ibcon#read 3, iclass 15, count 0 2006.173.16:28:38.32#ibcon#about to read 4, iclass 15, count 0 2006.173.16:28:38.32#ibcon#read 4, iclass 15, count 0 2006.173.16:28:38.32#ibcon#about to read 5, iclass 15, count 0 2006.173.16:28:38.32#ibcon#read 5, iclass 15, count 0 2006.173.16:28:38.32#ibcon#about to read 6, iclass 15, count 0 2006.173.16:28:38.32#ibcon#read 6, iclass 15, count 0 2006.173.16:28:38.32#ibcon#end of sib2, iclass 15, count 0 2006.173.16:28:38.32#ibcon#*after write, iclass 15, count 0 2006.173.16:28:38.32#ibcon#*before return 0, iclass 15, count 0 2006.173.16:28:38.32#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.16:28:38.32#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.16:28:38.32#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.16:28:38.32#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.16:28:38.32$vck44/va=1,7 2006.173.16:28:38.32#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.16:28:38.32#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.16:28:38.32#ibcon#ireg 11 cls_cnt 2 2006.173.16:28:38.32#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.16:28:38.32#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.16:28:38.32#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.16:28:38.32#ibcon#enter wrdev, iclass 17, count 2 2006.173.16:28:38.32#ibcon#first serial, iclass 17, count 2 2006.173.16:28:38.32#ibcon#enter sib2, iclass 17, count 2 2006.173.16:28:38.32#ibcon#flushed, iclass 17, count 2 2006.173.16:28:38.32#ibcon#about to write, iclass 17, count 2 2006.173.16:28:38.32#ibcon#wrote, iclass 17, count 2 2006.173.16:28:38.32#ibcon#about to read 3, iclass 17, count 2 2006.173.16:28:38.34#ibcon#read 3, iclass 17, count 2 2006.173.16:28:38.34#ibcon#about to read 4, iclass 17, count 2 2006.173.16:28:38.34#ibcon#read 4, iclass 17, count 2 2006.173.16:28:38.34#ibcon#about to read 5, iclass 17, count 2 2006.173.16:28:38.34#ibcon#read 5, iclass 17, count 2 2006.173.16:28:38.34#ibcon#about to read 6, iclass 17, count 2 2006.173.16:28:38.34#ibcon#read 6, iclass 17, count 2 2006.173.16:28:38.34#ibcon#end of sib2, iclass 17, count 2 2006.173.16:28:38.34#ibcon#*mode == 0, iclass 17, count 2 2006.173.16:28:38.34#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.16:28:38.34#ibcon#[25=AT01-07\r\n] 2006.173.16:28:38.34#ibcon#*before write, iclass 17, count 2 2006.173.16:28:38.34#ibcon#enter sib2, iclass 17, count 2 2006.173.16:28:38.34#ibcon#flushed, iclass 17, count 2 2006.173.16:28:38.34#ibcon#about to write, iclass 17, count 2 2006.173.16:28:38.34#ibcon#wrote, iclass 17, count 2 2006.173.16:28:38.34#ibcon#about to read 3, iclass 17, count 2 2006.173.16:28:38.37#ibcon#read 3, iclass 17, count 2 2006.173.16:28:38.37#ibcon#about to read 4, iclass 17, count 2 2006.173.16:28:38.37#ibcon#read 4, iclass 17, count 2 2006.173.16:28:38.37#ibcon#about to read 5, iclass 17, count 2 2006.173.16:28:38.37#ibcon#read 5, iclass 17, count 2 2006.173.16:28:38.37#ibcon#about to read 6, iclass 17, count 2 2006.173.16:28:38.37#ibcon#read 6, iclass 17, count 2 2006.173.16:28:38.37#ibcon#end of sib2, iclass 17, count 2 2006.173.16:28:38.37#ibcon#*after write, iclass 17, count 2 2006.173.16:28:38.37#ibcon#*before return 0, iclass 17, count 2 2006.173.16:28:38.37#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.16:28:38.37#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.16:28:38.37#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.16:28:38.37#ibcon#ireg 7 cls_cnt 0 2006.173.16:28:38.37#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.16:28:38.49#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.16:28:38.49#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.16:28:38.49#ibcon#enter wrdev, iclass 17, count 0 2006.173.16:28:38.49#ibcon#first serial, iclass 17, count 0 2006.173.16:28:38.49#ibcon#enter sib2, iclass 17, count 0 2006.173.16:28:38.49#ibcon#flushed, iclass 17, count 0 2006.173.16:28:38.49#ibcon#about to write, iclass 17, count 0 2006.173.16:28:38.49#ibcon#wrote, iclass 17, count 0 2006.173.16:28:38.49#ibcon#about to read 3, iclass 17, count 0 2006.173.16:28:38.51#ibcon#read 3, iclass 17, count 0 2006.173.16:28:38.51#ibcon#about to read 4, iclass 17, count 0 2006.173.16:28:38.51#ibcon#read 4, iclass 17, count 0 2006.173.16:28:38.51#ibcon#about to read 5, iclass 17, count 0 2006.173.16:28:38.51#ibcon#read 5, iclass 17, count 0 2006.173.16:28:38.51#ibcon#about to read 6, iclass 17, count 0 2006.173.16:28:38.51#ibcon#read 6, iclass 17, count 0 2006.173.16:28:38.51#ibcon#end of sib2, iclass 17, count 0 2006.173.16:28:38.51#ibcon#*mode == 0, iclass 17, count 0 2006.173.16:28:38.51#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.16:28:38.51#ibcon#[25=USB\r\n] 2006.173.16:28:38.51#ibcon#*before write, iclass 17, count 0 2006.173.16:28:38.51#ibcon#enter sib2, iclass 17, count 0 2006.173.16:28:38.51#ibcon#flushed, iclass 17, count 0 2006.173.16:28:38.51#ibcon#about to write, iclass 17, count 0 2006.173.16:28:38.51#ibcon#wrote, iclass 17, count 0 2006.173.16:28:38.51#ibcon#about to read 3, iclass 17, count 0 2006.173.16:28:38.54#ibcon#read 3, iclass 17, count 0 2006.173.16:28:38.54#ibcon#about to read 4, iclass 17, count 0 2006.173.16:28:38.54#ibcon#read 4, iclass 17, count 0 2006.173.16:28:38.54#ibcon#about to read 5, iclass 17, count 0 2006.173.16:28:38.54#ibcon#read 5, iclass 17, count 0 2006.173.16:28:38.54#ibcon#about to read 6, iclass 17, count 0 2006.173.16:28:38.54#ibcon#read 6, iclass 17, count 0 2006.173.16:28:38.54#ibcon#end of sib2, iclass 17, count 0 2006.173.16:28:38.54#ibcon#*after write, iclass 17, count 0 2006.173.16:28:38.54#ibcon#*before return 0, iclass 17, count 0 2006.173.16:28:38.54#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.16:28:38.54#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.16:28:38.54#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.16:28:38.54#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.16:28:38.54$vck44/valo=2,534.99 2006.173.16:28:38.54#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.16:28:38.54#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.16:28:38.54#ibcon#ireg 17 cls_cnt 0 2006.173.16:28:38.54#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.16:28:38.54#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.16:28:38.54#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.16:28:38.54#ibcon#enter wrdev, iclass 19, count 0 2006.173.16:28:38.54#ibcon#first serial, iclass 19, count 0 2006.173.16:28:38.54#ibcon#enter sib2, iclass 19, count 0 2006.173.16:28:38.54#ibcon#flushed, iclass 19, count 0 2006.173.16:28:38.54#ibcon#about to write, iclass 19, count 0 2006.173.16:28:38.54#ibcon#wrote, iclass 19, count 0 2006.173.16:28:38.54#ibcon#about to read 3, iclass 19, count 0 2006.173.16:28:38.56#ibcon#read 3, iclass 19, count 0 2006.173.16:28:38.56#ibcon#about to read 4, iclass 19, count 0 2006.173.16:28:38.56#ibcon#read 4, iclass 19, count 0 2006.173.16:28:38.56#ibcon#about to read 5, iclass 19, count 0 2006.173.16:28:38.56#ibcon#read 5, iclass 19, count 0 2006.173.16:28:38.56#ibcon#about to read 6, iclass 19, count 0 2006.173.16:28:38.56#ibcon#read 6, iclass 19, count 0 2006.173.16:28:38.56#ibcon#end of sib2, iclass 19, count 0 2006.173.16:28:38.56#ibcon#*mode == 0, iclass 19, count 0 2006.173.16:28:38.56#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.16:28:38.56#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.16:28:38.56#ibcon#*before write, iclass 19, count 0 2006.173.16:28:38.56#ibcon#enter sib2, iclass 19, count 0 2006.173.16:28:38.56#ibcon#flushed, iclass 19, count 0 2006.173.16:28:38.56#ibcon#about to write, iclass 19, count 0 2006.173.16:28:38.56#ibcon#wrote, iclass 19, count 0 2006.173.16:28:38.56#ibcon#about to read 3, iclass 19, count 0 2006.173.16:28:38.60#ibcon#read 3, iclass 19, count 0 2006.173.16:28:38.60#ibcon#about to read 4, iclass 19, count 0 2006.173.16:28:38.60#ibcon#read 4, iclass 19, count 0 2006.173.16:28:38.60#ibcon#about to read 5, iclass 19, count 0 2006.173.16:28:38.60#ibcon#read 5, iclass 19, count 0 2006.173.16:28:38.60#ibcon#about to read 6, iclass 19, count 0 2006.173.16:28:38.60#ibcon#read 6, iclass 19, count 0 2006.173.16:28:38.60#ibcon#end of sib2, iclass 19, count 0 2006.173.16:28:38.60#ibcon#*after write, iclass 19, count 0 2006.173.16:28:38.60#ibcon#*before return 0, iclass 19, count 0 2006.173.16:28:38.60#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.16:28:38.60#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.16:28:38.60#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.16:28:38.60#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.16:28:38.60$vck44/va=2,6 2006.173.16:28:38.60#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.16:28:38.60#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.16:28:38.60#ibcon#ireg 11 cls_cnt 2 2006.173.16:28:38.60#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.16:28:38.66#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.16:28:38.66#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.16:28:38.66#ibcon#enter wrdev, iclass 21, count 2 2006.173.16:28:38.66#ibcon#first serial, iclass 21, count 2 2006.173.16:28:38.66#ibcon#enter sib2, iclass 21, count 2 2006.173.16:28:38.66#ibcon#flushed, iclass 21, count 2 2006.173.16:28:38.66#ibcon#about to write, iclass 21, count 2 2006.173.16:28:38.66#ibcon#wrote, iclass 21, count 2 2006.173.16:28:38.66#ibcon#about to read 3, iclass 21, count 2 2006.173.16:28:38.68#ibcon#read 3, iclass 21, count 2 2006.173.16:28:38.68#ibcon#about to read 4, iclass 21, count 2 2006.173.16:28:38.68#ibcon#read 4, iclass 21, count 2 2006.173.16:28:38.68#ibcon#about to read 5, iclass 21, count 2 2006.173.16:28:38.68#ibcon#read 5, iclass 21, count 2 2006.173.16:28:38.68#ibcon#about to read 6, iclass 21, count 2 2006.173.16:28:38.68#ibcon#read 6, iclass 21, count 2 2006.173.16:28:38.68#ibcon#end of sib2, iclass 21, count 2 2006.173.16:28:38.68#ibcon#*mode == 0, iclass 21, count 2 2006.173.16:28:38.68#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.16:28:38.68#ibcon#[25=AT02-06\r\n] 2006.173.16:28:38.68#ibcon#*before write, iclass 21, count 2 2006.173.16:28:38.68#ibcon#enter sib2, iclass 21, count 2 2006.173.16:28:38.68#ibcon#flushed, iclass 21, count 2 2006.173.16:28:38.68#ibcon#about to write, iclass 21, count 2 2006.173.16:28:38.68#ibcon#wrote, iclass 21, count 2 2006.173.16:28:38.68#ibcon#about to read 3, iclass 21, count 2 2006.173.16:28:38.71#ibcon#read 3, iclass 21, count 2 2006.173.16:28:38.71#ibcon#about to read 4, iclass 21, count 2 2006.173.16:28:38.71#ibcon#read 4, iclass 21, count 2 2006.173.16:28:38.71#ibcon#about to read 5, iclass 21, count 2 2006.173.16:28:38.71#ibcon#read 5, iclass 21, count 2 2006.173.16:28:38.71#ibcon#about to read 6, iclass 21, count 2 2006.173.16:28:38.71#ibcon#read 6, iclass 21, count 2 2006.173.16:28:38.71#ibcon#end of sib2, iclass 21, count 2 2006.173.16:28:38.71#ibcon#*after write, iclass 21, count 2 2006.173.16:28:38.71#ibcon#*before return 0, iclass 21, count 2 2006.173.16:28:38.71#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.16:28:38.71#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.16:28:38.71#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.16:28:38.71#ibcon#ireg 7 cls_cnt 0 2006.173.16:28:38.71#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.16:28:38.83#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.16:28:38.83#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.16:28:38.83#ibcon#enter wrdev, iclass 21, count 0 2006.173.16:28:38.83#ibcon#first serial, iclass 21, count 0 2006.173.16:28:38.83#ibcon#enter sib2, iclass 21, count 0 2006.173.16:28:38.83#ibcon#flushed, iclass 21, count 0 2006.173.16:28:38.83#ibcon#about to write, iclass 21, count 0 2006.173.16:28:38.83#ibcon#wrote, iclass 21, count 0 2006.173.16:28:38.83#ibcon#about to read 3, iclass 21, count 0 2006.173.16:28:38.85#ibcon#read 3, iclass 21, count 0 2006.173.16:28:38.85#ibcon#about to read 4, iclass 21, count 0 2006.173.16:28:38.85#ibcon#read 4, iclass 21, count 0 2006.173.16:28:38.85#ibcon#about to read 5, iclass 21, count 0 2006.173.16:28:38.85#ibcon#read 5, iclass 21, count 0 2006.173.16:28:38.85#ibcon#about to read 6, iclass 21, count 0 2006.173.16:28:38.85#ibcon#read 6, iclass 21, count 0 2006.173.16:28:38.85#ibcon#end of sib2, iclass 21, count 0 2006.173.16:28:38.85#ibcon#*mode == 0, iclass 21, count 0 2006.173.16:28:38.85#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.16:28:38.85#ibcon#[25=USB\r\n] 2006.173.16:28:38.85#ibcon#*before write, iclass 21, count 0 2006.173.16:28:38.85#ibcon#enter sib2, iclass 21, count 0 2006.173.16:28:38.85#ibcon#flushed, iclass 21, count 0 2006.173.16:28:38.85#ibcon#about to write, iclass 21, count 0 2006.173.16:28:38.85#ibcon#wrote, iclass 21, count 0 2006.173.16:28:38.85#ibcon#about to read 3, iclass 21, count 0 2006.173.16:28:38.88#ibcon#read 3, iclass 21, count 0 2006.173.16:28:38.88#ibcon#about to read 4, iclass 21, count 0 2006.173.16:28:38.88#ibcon#read 4, iclass 21, count 0 2006.173.16:28:38.88#ibcon#about to read 5, iclass 21, count 0 2006.173.16:28:38.88#ibcon#read 5, iclass 21, count 0 2006.173.16:28:38.88#ibcon#about to read 6, iclass 21, count 0 2006.173.16:28:38.88#ibcon#read 6, iclass 21, count 0 2006.173.16:28:38.88#ibcon#end of sib2, iclass 21, count 0 2006.173.16:28:38.88#ibcon#*after write, iclass 21, count 0 2006.173.16:28:38.88#ibcon#*before return 0, iclass 21, count 0 2006.173.16:28:38.88#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.16:28:38.88#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.16:28:38.88#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.16:28:38.88#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.16:28:38.88$vck44/valo=3,564.99 2006.173.16:28:38.88#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.16:28:38.88#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.16:28:38.88#ibcon#ireg 17 cls_cnt 0 2006.173.16:28:38.88#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.16:28:38.88#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.16:28:38.88#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.16:28:38.88#ibcon#enter wrdev, iclass 23, count 0 2006.173.16:28:38.88#ibcon#first serial, iclass 23, count 0 2006.173.16:28:38.88#ibcon#enter sib2, iclass 23, count 0 2006.173.16:28:38.88#ibcon#flushed, iclass 23, count 0 2006.173.16:28:38.88#ibcon#about to write, iclass 23, count 0 2006.173.16:28:38.88#ibcon#wrote, iclass 23, count 0 2006.173.16:28:38.88#ibcon#about to read 3, iclass 23, count 0 2006.173.16:28:38.90#ibcon#read 3, iclass 23, count 0 2006.173.16:28:38.90#ibcon#about to read 4, iclass 23, count 0 2006.173.16:28:38.90#ibcon#read 4, iclass 23, count 0 2006.173.16:28:38.90#ibcon#about to read 5, iclass 23, count 0 2006.173.16:28:38.90#ibcon#read 5, iclass 23, count 0 2006.173.16:28:38.90#ibcon#about to read 6, iclass 23, count 0 2006.173.16:28:38.90#ibcon#read 6, iclass 23, count 0 2006.173.16:28:38.90#ibcon#end of sib2, iclass 23, count 0 2006.173.16:28:38.90#ibcon#*mode == 0, iclass 23, count 0 2006.173.16:28:38.90#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.16:28:38.90#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.16:28:38.90#ibcon#*before write, iclass 23, count 0 2006.173.16:28:38.90#ibcon#enter sib2, iclass 23, count 0 2006.173.16:28:38.90#ibcon#flushed, iclass 23, count 0 2006.173.16:28:38.90#ibcon#about to write, iclass 23, count 0 2006.173.16:28:38.90#ibcon#wrote, iclass 23, count 0 2006.173.16:28:38.90#ibcon#about to read 3, iclass 23, count 0 2006.173.16:28:38.94#ibcon#read 3, iclass 23, count 0 2006.173.16:28:38.94#ibcon#about to read 4, iclass 23, count 0 2006.173.16:28:38.94#ibcon#read 4, iclass 23, count 0 2006.173.16:28:38.94#ibcon#about to read 5, iclass 23, count 0 2006.173.16:28:38.94#ibcon#read 5, iclass 23, count 0 2006.173.16:28:38.94#ibcon#about to read 6, iclass 23, count 0 2006.173.16:28:38.94#ibcon#read 6, iclass 23, count 0 2006.173.16:28:38.94#ibcon#end of sib2, iclass 23, count 0 2006.173.16:28:38.94#ibcon#*after write, iclass 23, count 0 2006.173.16:28:38.94#ibcon#*before return 0, iclass 23, count 0 2006.173.16:28:38.94#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.16:28:38.94#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.16:28:38.94#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.16:28:38.94#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.16:28:38.94$vck44/va=3,5 2006.173.16:28:38.94#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.16:28:38.94#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.16:28:38.94#ibcon#ireg 11 cls_cnt 2 2006.173.16:28:38.94#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.16:28:39.00#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.16:28:39.00#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.16:28:39.00#ibcon#enter wrdev, iclass 25, count 2 2006.173.16:28:39.00#ibcon#first serial, iclass 25, count 2 2006.173.16:28:39.00#ibcon#enter sib2, iclass 25, count 2 2006.173.16:28:39.00#ibcon#flushed, iclass 25, count 2 2006.173.16:28:39.00#ibcon#about to write, iclass 25, count 2 2006.173.16:28:39.00#ibcon#wrote, iclass 25, count 2 2006.173.16:28:39.00#ibcon#about to read 3, iclass 25, count 2 2006.173.16:28:39.02#ibcon#read 3, iclass 25, count 2 2006.173.16:28:39.02#ibcon#about to read 4, iclass 25, count 2 2006.173.16:28:39.02#ibcon#read 4, iclass 25, count 2 2006.173.16:28:39.02#ibcon#about to read 5, iclass 25, count 2 2006.173.16:28:39.02#ibcon#read 5, iclass 25, count 2 2006.173.16:28:39.02#ibcon#about to read 6, iclass 25, count 2 2006.173.16:28:39.02#ibcon#read 6, iclass 25, count 2 2006.173.16:28:39.02#ibcon#end of sib2, iclass 25, count 2 2006.173.16:28:39.02#ibcon#*mode == 0, iclass 25, count 2 2006.173.16:28:39.02#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.16:28:39.02#ibcon#[25=AT03-05\r\n] 2006.173.16:28:39.02#ibcon#*before write, iclass 25, count 2 2006.173.16:28:39.02#ibcon#enter sib2, iclass 25, count 2 2006.173.16:28:39.02#ibcon#flushed, iclass 25, count 2 2006.173.16:28:39.02#ibcon#about to write, iclass 25, count 2 2006.173.16:28:39.02#ibcon#wrote, iclass 25, count 2 2006.173.16:28:39.02#ibcon#about to read 3, iclass 25, count 2 2006.173.16:28:39.05#ibcon#read 3, iclass 25, count 2 2006.173.16:28:39.05#ibcon#about to read 4, iclass 25, count 2 2006.173.16:28:39.05#ibcon#read 4, iclass 25, count 2 2006.173.16:28:39.05#ibcon#about to read 5, iclass 25, count 2 2006.173.16:28:39.05#ibcon#read 5, iclass 25, count 2 2006.173.16:28:39.05#ibcon#about to read 6, iclass 25, count 2 2006.173.16:28:39.05#ibcon#read 6, iclass 25, count 2 2006.173.16:28:39.05#ibcon#end of sib2, iclass 25, count 2 2006.173.16:28:39.05#ibcon#*after write, iclass 25, count 2 2006.173.16:28:39.05#ibcon#*before return 0, iclass 25, count 2 2006.173.16:28:39.05#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.16:28:39.05#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.16:28:39.05#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.16:28:39.05#ibcon#ireg 7 cls_cnt 0 2006.173.16:28:39.05#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.16:28:39.17#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.16:28:39.17#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.16:28:39.17#ibcon#enter wrdev, iclass 25, count 0 2006.173.16:28:39.17#ibcon#first serial, iclass 25, count 0 2006.173.16:28:39.17#ibcon#enter sib2, iclass 25, count 0 2006.173.16:28:39.17#ibcon#flushed, iclass 25, count 0 2006.173.16:28:39.17#ibcon#about to write, iclass 25, count 0 2006.173.16:28:39.17#ibcon#wrote, iclass 25, count 0 2006.173.16:28:39.17#ibcon#about to read 3, iclass 25, count 0 2006.173.16:28:39.19#ibcon#read 3, iclass 25, count 0 2006.173.16:28:39.19#ibcon#about to read 4, iclass 25, count 0 2006.173.16:28:39.19#ibcon#read 4, iclass 25, count 0 2006.173.16:28:39.19#ibcon#about to read 5, iclass 25, count 0 2006.173.16:28:39.19#ibcon#read 5, iclass 25, count 0 2006.173.16:28:39.19#ibcon#about to read 6, iclass 25, count 0 2006.173.16:28:39.19#ibcon#read 6, iclass 25, count 0 2006.173.16:28:39.19#ibcon#end of sib2, iclass 25, count 0 2006.173.16:28:39.19#ibcon#*mode == 0, iclass 25, count 0 2006.173.16:28:39.19#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.16:28:39.19#ibcon#[25=USB\r\n] 2006.173.16:28:39.19#ibcon#*before write, iclass 25, count 0 2006.173.16:28:39.19#ibcon#enter sib2, iclass 25, count 0 2006.173.16:28:39.19#ibcon#flushed, iclass 25, count 0 2006.173.16:28:39.19#ibcon#about to write, iclass 25, count 0 2006.173.16:28:39.19#ibcon#wrote, iclass 25, count 0 2006.173.16:28:39.19#ibcon#about to read 3, iclass 25, count 0 2006.173.16:28:39.22#ibcon#read 3, iclass 25, count 0 2006.173.16:28:39.22#ibcon#about to read 4, iclass 25, count 0 2006.173.16:28:39.22#ibcon#read 4, iclass 25, count 0 2006.173.16:28:39.22#ibcon#about to read 5, iclass 25, count 0 2006.173.16:28:39.22#ibcon#read 5, iclass 25, count 0 2006.173.16:28:39.22#ibcon#about to read 6, iclass 25, count 0 2006.173.16:28:39.22#ibcon#read 6, iclass 25, count 0 2006.173.16:28:39.22#ibcon#end of sib2, iclass 25, count 0 2006.173.16:28:39.22#ibcon#*after write, iclass 25, count 0 2006.173.16:28:39.22#ibcon#*before return 0, iclass 25, count 0 2006.173.16:28:39.22#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.16:28:39.22#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.16:28:39.22#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.16:28:39.22#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.16:28:39.22$vck44/valo=4,624.99 2006.173.16:28:39.22#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.16:28:39.22#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.16:28:39.22#ibcon#ireg 17 cls_cnt 0 2006.173.16:28:39.22#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.16:28:39.22#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.16:28:39.22#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.16:28:39.22#ibcon#enter wrdev, iclass 27, count 0 2006.173.16:28:39.22#ibcon#first serial, iclass 27, count 0 2006.173.16:28:39.22#ibcon#enter sib2, iclass 27, count 0 2006.173.16:28:39.22#ibcon#flushed, iclass 27, count 0 2006.173.16:28:39.22#ibcon#about to write, iclass 27, count 0 2006.173.16:28:39.22#ibcon#wrote, iclass 27, count 0 2006.173.16:28:39.22#ibcon#about to read 3, iclass 27, count 0 2006.173.16:28:39.24#ibcon#read 3, iclass 27, count 0 2006.173.16:28:39.24#ibcon#about to read 4, iclass 27, count 0 2006.173.16:28:39.24#ibcon#read 4, iclass 27, count 0 2006.173.16:28:39.24#ibcon#about to read 5, iclass 27, count 0 2006.173.16:28:39.24#ibcon#read 5, iclass 27, count 0 2006.173.16:28:39.24#ibcon#about to read 6, iclass 27, count 0 2006.173.16:28:39.24#ibcon#read 6, iclass 27, count 0 2006.173.16:28:39.24#ibcon#end of sib2, iclass 27, count 0 2006.173.16:28:39.24#ibcon#*mode == 0, iclass 27, count 0 2006.173.16:28:39.24#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.16:28:39.24#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.16:28:39.24#ibcon#*before write, iclass 27, count 0 2006.173.16:28:39.24#ibcon#enter sib2, iclass 27, count 0 2006.173.16:28:39.24#ibcon#flushed, iclass 27, count 0 2006.173.16:28:39.24#ibcon#about to write, iclass 27, count 0 2006.173.16:28:39.24#ibcon#wrote, iclass 27, count 0 2006.173.16:28:39.24#ibcon#about to read 3, iclass 27, count 0 2006.173.16:28:39.28#ibcon#read 3, iclass 27, count 0 2006.173.16:28:39.28#ibcon#about to read 4, iclass 27, count 0 2006.173.16:28:39.28#ibcon#read 4, iclass 27, count 0 2006.173.16:28:39.28#ibcon#about to read 5, iclass 27, count 0 2006.173.16:28:39.28#ibcon#read 5, iclass 27, count 0 2006.173.16:28:39.28#ibcon#about to read 6, iclass 27, count 0 2006.173.16:28:39.28#ibcon#read 6, iclass 27, count 0 2006.173.16:28:39.28#ibcon#end of sib2, iclass 27, count 0 2006.173.16:28:39.28#ibcon#*after write, iclass 27, count 0 2006.173.16:28:39.28#ibcon#*before return 0, iclass 27, count 0 2006.173.16:28:39.28#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.16:28:39.28#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.16:28:39.28#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.16:28:39.28#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.16:28:39.28$vck44/va=4,6 2006.173.16:28:39.28#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.16:28:39.28#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.16:28:39.28#ibcon#ireg 11 cls_cnt 2 2006.173.16:28:39.28#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.16:28:39.34#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.16:28:39.34#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.16:28:39.34#ibcon#enter wrdev, iclass 29, count 2 2006.173.16:28:39.34#ibcon#first serial, iclass 29, count 2 2006.173.16:28:39.34#ibcon#enter sib2, iclass 29, count 2 2006.173.16:28:39.34#ibcon#flushed, iclass 29, count 2 2006.173.16:28:39.34#ibcon#about to write, iclass 29, count 2 2006.173.16:28:39.34#ibcon#wrote, iclass 29, count 2 2006.173.16:28:39.34#ibcon#about to read 3, iclass 29, count 2 2006.173.16:28:39.36#ibcon#read 3, iclass 29, count 2 2006.173.16:28:39.36#ibcon#about to read 4, iclass 29, count 2 2006.173.16:28:39.36#ibcon#read 4, iclass 29, count 2 2006.173.16:28:39.36#ibcon#about to read 5, iclass 29, count 2 2006.173.16:28:39.36#ibcon#read 5, iclass 29, count 2 2006.173.16:28:39.36#ibcon#about to read 6, iclass 29, count 2 2006.173.16:28:39.36#ibcon#read 6, iclass 29, count 2 2006.173.16:28:39.36#ibcon#end of sib2, iclass 29, count 2 2006.173.16:28:39.36#ibcon#*mode == 0, iclass 29, count 2 2006.173.16:28:39.36#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.16:28:39.36#ibcon#[25=AT04-06\r\n] 2006.173.16:28:39.36#ibcon#*before write, iclass 29, count 2 2006.173.16:28:39.36#ibcon#enter sib2, iclass 29, count 2 2006.173.16:28:39.36#ibcon#flushed, iclass 29, count 2 2006.173.16:28:39.36#ibcon#about to write, iclass 29, count 2 2006.173.16:28:39.36#ibcon#wrote, iclass 29, count 2 2006.173.16:28:39.36#ibcon#about to read 3, iclass 29, count 2 2006.173.16:28:39.39#ibcon#read 3, iclass 29, count 2 2006.173.16:28:39.39#ibcon#about to read 4, iclass 29, count 2 2006.173.16:28:39.39#ibcon#read 4, iclass 29, count 2 2006.173.16:28:39.39#ibcon#about to read 5, iclass 29, count 2 2006.173.16:28:39.39#ibcon#read 5, iclass 29, count 2 2006.173.16:28:39.39#ibcon#about to read 6, iclass 29, count 2 2006.173.16:28:39.39#ibcon#read 6, iclass 29, count 2 2006.173.16:28:39.39#ibcon#end of sib2, iclass 29, count 2 2006.173.16:28:39.39#ibcon#*after write, iclass 29, count 2 2006.173.16:28:39.39#ibcon#*before return 0, iclass 29, count 2 2006.173.16:28:39.39#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.16:28:39.39#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.16:28:39.39#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.16:28:39.39#ibcon#ireg 7 cls_cnt 0 2006.173.16:28:39.39#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.16:28:39.51#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.16:28:39.51#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.16:28:39.51#ibcon#enter wrdev, iclass 29, count 0 2006.173.16:28:39.51#ibcon#first serial, iclass 29, count 0 2006.173.16:28:39.51#ibcon#enter sib2, iclass 29, count 0 2006.173.16:28:39.51#ibcon#flushed, iclass 29, count 0 2006.173.16:28:39.51#ibcon#about to write, iclass 29, count 0 2006.173.16:28:39.51#ibcon#wrote, iclass 29, count 0 2006.173.16:28:39.51#ibcon#about to read 3, iclass 29, count 0 2006.173.16:28:39.53#ibcon#read 3, iclass 29, count 0 2006.173.16:28:39.53#ibcon#about to read 4, iclass 29, count 0 2006.173.16:28:39.53#ibcon#read 4, iclass 29, count 0 2006.173.16:28:39.53#ibcon#about to read 5, iclass 29, count 0 2006.173.16:28:39.53#ibcon#read 5, iclass 29, count 0 2006.173.16:28:39.53#ibcon#about to read 6, iclass 29, count 0 2006.173.16:28:39.53#ibcon#read 6, iclass 29, count 0 2006.173.16:28:39.53#ibcon#end of sib2, iclass 29, count 0 2006.173.16:28:39.53#ibcon#*mode == 0, iclass 29, count 0 2006.173.16:28:39.53#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.16:28:39.53#ibcon#[25=USB\r\n] 2006.173.16:28:39.53#ibcon#*before write, iclass 29, count 0 2006.173.16:28:39.53#ibcon#enter sib2, iclass 29, count 0 2006.173.16:28:39.53#ibcon#flushed, iclass 29, count 0 2006.173.16:28:39.53#ibcon#about to write, iclass 29, count 0 2006.173.16:28:39.53#ibcon#wrote, iclass 29, count 0 2006.173.16:28:39.53#ibcon#about to read 3, iclass 29, count 0 2006.173.16:28:39.56#ibcon#read 3, iclass 29, count 0 2006.173.16:28:39.56#ibcon#about to read 4, iclass 29, count 0 2006.173.16:28:39.56#ibcon#read 4, iclass 29, count 0 2006.173.16:28:39.56#ibcon#about to read 5, iclass 29, count 0 2006.173.16:28:39.56#ibcon#read 5, iclass 29, count 0 2006.173.16:28:39.56#ibcon#about to read 6, iclass 29, count 0 2006.173.16:28:39.56#ibcon#read 6, iclass 29, count 0 2006.173.16:28:39.56#ibcon#end of sib2, iclass 29, count 0 2006.173.16:28:39.56#ibcon#*after write, iclass 29, count 0 2006.173.16:28:39.56#ibcon#*before return 0, iclass 29, count 0 2006.173.16:28:39.56#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.16:28:39.56#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.16:28:39.56#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.16:28:39.56#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.16:28:39.56$vck44/valo=5,734.99 2006.173.16:28:39.56#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.16:28:39.56#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.16:28:39.56#ibcon#ireg 17 cls_cnt 0 2006.173.16:28:39.56#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.16:28:39.56#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.16:28:39.56#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.16:28:39.56#ibcon#enter wrdev, iclass 31, count 0 2006.173.16:28:39.56#ibcon#first serial, iclass 31, count 0 2006.173.16:28:39.56#ibcon#enter sib2, iclass 31, count 0 2006.173.16:28:39.56#ibcon#flushed, iclass 31, count 0 2006.173.16:28:39.56#ibcon#about to write, iclass 31, count 0 2006.173.16:28:39.56#ibcon#wrote, iclass 31, count 0 2006.173.16:28:39.56#ibcon#about to read 3, iclass 31, count 0 2006.173.16:28:39.58#ibcon#read 3, iclass 31, count 0 2006.173.16:28:39.58#ibcon#about to read 4, iclass 31, count 0 2006.173.16:28:39.58#ibcon#read 4, iclass 31, count 0 2006.173.16:28:39.58#ibcon#about to read 5, iclass 31, count 0 2006.173.16:28:39.58#ibcon#read 5, iclass 31, count 0 2006.173.16:28:39.58#ibcon#about to read 6, iclass 31, count 0 2006.173.16:28:39.58#ibcon#read 6, iclass 31, count 0 2006.173.16:28:39.58#ibcon#end of sib2, iclass 31, count 0 2006.173.16:28:39.58#ibcon#*mode == 0, iclass 31, count 0 2006.173.16:28:39.58#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.16:28:39.58#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.16:28:39.58#ibcon#*before write, iclass 31, count 0 2006.173.16:28:39.58#ibcon#enter sib2, iclass 31, count 0 2006.173.16:28:39.58#ibcon#flushed, iclass 31, count 0 2006.173.16:28:39.58#ibcon#about to write, iclass 31, count 0 2006.173.16:28:39.58#ibcon#wrote, iclass 31, count 0 2006.173.16:28:39.58#ibcon#about to read 3, iclass 31, count 0 2006.173.16:28:39.62#ibcon#read 3, iclass 31, count 0 2006.173.16:28:39.62#ibcon#about to read 4, iclass 31, count 0 2006.173.16:28:39.62#ibcon#read 4, iclass 31, count 0 2006.173.16:28:39.62#ibcon#about to read 5, iclass 31, count 0 2006.173.16:28:39.62#ibcon#read 5, iclass 31, count 0 2006.173.16:28:39.62#ibcon#about to read 6, iclass 31, count 0 2006.173.16:28:39.62#ibcon#read 6, iclass 31, count 0 2006.173.16:28:39.62#ibcon#end of sib2, iclass 31, count 0 2006.173.16:28:39.62#ibcon#*after write, iclass 31, count 0 2006.173.16:28:39.62#ibcon#*before return 0, iclass 31, count 0 2006.173.16:28:39.62#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.16:28:39.62#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.16:28:39.62#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.16:28:39.62#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.16:28:39.62$vck44/va=5,4 2006.173.16:28:39.62#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.173.16:28:39.62#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.173.16:28:39.62#ibcon#ireg 11 cls_cnt 2 2006.173.16:28:39.62#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.16:28:39.68#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.16:28:39.68#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.16:28:39.68#ibcon#enter wrdev, iclass 33, count 2 2006.173.16:28:39.68#ibcon#first serial, iclass 33, count 2 2006.173.16:28:39.68#ibcon#enter sib2, iclass 33, count 2 2006.173.16:28:39.68#ibcon#flushed, iclass 33, count 2 2006.173.16:28:39.68#ibcon#about to write, iclass 33, count 2 2006.173.16:28:39.68#ibcon#wrote, iclass 33, count 2 2006.173.16:28:39.68#ibcon#about to read 3, iclass 33, count 2 2006.173.16:28:39.70#ibcon#read 3, iclass 33, count 2 2006.173.16:28:39.70#ibcon#about to read 4, iclass 33, count 2 2006.173.16:28:39.70#ibcon#read 4, iclass 33, count 2 2006.173.16:28:39.70#ibcon#about to read 5, iclass 33, count 2 2006.173.16:28:39.70#ibcon#read 5, iclass 33, count 2 2006.173.16:28:39.70#ibcon#about to read 6, iclass 33, count 2 2006.173.16:28:39.70#ibcon#read 6, iclass 33, count 2 2006.173.16:28:39.70#ibcon#end of sib2, iclass 33, count 2 2006.173.16:28:39.70#ibcon#*mode == 0, iclass 33, count 2 2006.173.16:28:39.70#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.173.16:28:39.70#ibcon#[25=AT05-04\r\n] 2006.173.16:28:39.70#ibcon#*before write, iclass 33, count 2 2006.173.16:28:39.70#ibcon#enter sib2, iclass 33, count 2 2006.173.16:28:39.70#ibcon#flushed, iclass 33, count 2 2006.173.16:28:39.70#ibcon#about to write, iclass 33, count 2 2006.173.16:28:39.70#ibcon#wrote, iclass 33, count 2 2006.173.16:28:39.70#ibcon#about to read 3, iclass 33, count 2 2006.173.16:28:39.73#ibcon#read 3, iclass 33, count 2 2006.173.16:28:39.73#ibcon#about to read 4, iclass 33, count 2 2006.173.16:28:39.73#ibcon#read 4, iclass 33, count 2 2006.173.16:28:39.73#ibcon#about to read 5, iclass 33, count 2 2006.173.16:28:39.73#ibcon#read 5, iclass 33, count 2 2006.173.16:28:39.73#ibcon#about to read 6, iclass 33, count 2 2006.173.16:28:39.73#ibcon#read 6, iclass 33, count 2 2006.173.16:28:39.73#ibcon#end of sib2, iclass 33, count 2 2006.173.16:28:39.73#ibcon#*after write, iclass 33, count 2 2006.173.16:28:39.73#ibcon#*before return 0, iclass 33, count 2 2006.173.16:28:39.73#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.16:28:39.73#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.173.16:28:39.73#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.173.16:28:39.73#ibcon#ireg 7 cls_cnt 0 2006.173.16:28:39.73#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.16:28:39.85#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.16:28:39.85#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.16:28:39.85#ibcon#enter wrdev, iclass 33, count 0 2006.173.16:28:39.85#ibcon#first serial, iclass 33, count 0 2006.173.16:28:39.85#ibcon#enter sib2, iclass 33, count 0 2006.173.16:28:39.85#ibcon#flushed, iclass 33, count 0 2006.173.16:28:39.85#ibcon#about to write, iclass 33, count 0 2006.173.16:28:39.85#ibcon#wrote, iclass 33, count 0 2006.173.16:28:39.85#ibcon#about to read 3, iclass 33, count 0 2006.173.16:28:39.87#ibcon#read 3, iclass 33, count 0 2006.173.16:28:39.87#ibcon#about to read 4, iclass 33, count 0 2006.173.16:28:39.87#ibcon#read 4, iclass 33, count 0 2006.173.16:28:39.87#ibcon#about to read 5, iclass 33, count 0 2006.173.16:28:39.87#ibcon#read 5, iclass 33, count 0 2006.173.16:28:39.87#ibcon#about to read 6, iclass 33, count 0 2006.173.16:28:39.87#ibcon#read 6, iclass 33, count 0 2006.173.16:28:39.87#ibcon#end of sib2, iclass 33, count 0 2006.173.16:28:39.87#ibcon#*mode == 0, iclass 33, count 0 2006.173.16:28:39.87#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.16:28:39.87#ibcon#[25=USB\r\n] 2006.173.16:28:39.87#ibcon#*before write, iclass 33, count 0 2006.173.16:28:39.87#ibcon#enter sib2, iclass 33, count 0 2006.173.16:28:39.87#ibcon#flushed, iclass 33, count 0 2006.173.16:28:39.87#ibcon#about to write, iclass 33, count 0 2006.173.16:28:39.87#ibcon#wrote, iclass 33, count 0 2006.173.16:28:39.87#ibcon#about to read 3, iclass 33, count 0 2006.173.16:28:39.90#ibcon#read 3, iclass 33, count 0 2006.173.16:28:39.90#ibcon#about to read 4, iclass 33, count 0 2006.173.16:28:39.90#ibcon#read 4, iclass 33, count 0 2006.173.16:28:39.90#ibcon#about to read 5, iclass 33, count 0 2006.173.16:28:39.90#ibcon#read 5, iclass 33, count 0 2006.173.16:28:39.90#ibcon#about to read 6, iclass 33, count 0 2006.173.16:28:39.90#ibcon#read 6, iclass 33, count 0 2006.173.16:28:39.90#ibcon#end of sib2, iclass 33, count 0 2006.173.16:28:39.90#ibcon#*after write, iclass 33, count 0 2006.173.16:28:39.90#ibcon#*before return 0, iclass 33, count 0 2006.173.16:28:39.90#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.16:28:39.90#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.173.16:28:39.90#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.16:28:39.90#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.16:28:39.90$vck44/valo=6,814.99 2006.173.16:28:39.90#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.16:28:39.90#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.16:28:39.90#ibcon#ireg 17 cls_cnt 0 2006.173.16:28:39.90#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.16:28:39.90#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.16:28:39.90#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.16:28:39.90#ibcon#enter wrdev, iclass 35, count 0 2006.173.16:28:39.90#ibcon#first serial, iclass 35, count 0 2006.173.16:28:39.90#ibcon#enter sib2, iclass 35, count 0 2006.173.16:28:39.90#ibcon#flushed, iclass 35, count 0 2006.173.16:28:39.90#ibcon#about to write, iclass 35, count 0 2006.173.16:28:39.90#ibcon#wrote, iclass 35, count 0 2006.173.16:28:39.90#ibcon#about to read 3, iclass 35, count 0 2006.173.16:28:39.92#ibcon#read 3, iclass 35, count 0 2006.173.16:28:39.92#ibcon#about to read 4, iclass 35, count 0 2006.173.16:28:39.92#ibcon#read 4, iclass 35, count 0 2006.173.16:28:39.92#ibcon#about to read 5, iclass 35, count 0 2006.173.16:28:39.92#ibcon#read 5, iclass 35, count 0 2006.173.16:28:39.92#ibcon#about to read 6, iclass 35, count 0 2006.173.16:28:39.92#ibcon#read 6, iclass 35, count 0 2006.173.16:28:39.92#ibcon#end of sib2, iclass 35, count 0 2006.173.16:28:39.92#ibcon#*mode == 0, iclass 35, count 0 2006.173.16:28:39.92#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.16:28:39.92#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.16:28:39.92#ibcon#*before write, iclass 35, count 0 2006.173.16:28:39.92#ibcon#enter sib2, iclass 35, count 0 2006.173.16:28:39.92#ibcon#flushed, iclass 35, count 0 2006.173.16:28:39.92#ibcon#about to write, iclass 35, count 0 2006.173.16:28:39.92#ibcon#wrote, iclass 35, count 0 2006.173.16:28:39.92#ibcon#about to read 3, iclass 35, count 0 2006.173.16:28:39.96#ibcon#read 3, iclass 35, count 0 2006.173.16:28:39.96#ibcon#about to read 4, iclass 35, count 0 2006.173.16:28:39.96#ibcon#read 4, iclass 35, count 0 2006.173.16:28:39.96#ibcon#about to read 5, iclass 35, count 0 2006.173.16:28:39.96#ibcon#read 5, iclass 35, count 0 2006.173.16:28:39.96#ibcon#about to read 6, iclass 35, count 0 2006.173.16:28:39.96#ibcon#read 6, iclass 35, count 0 2006.173.16:28:39.96#ibcon#end of sib2, iclass 35, count 0 2006.173.16:28:39.96#ibcon#*after write, iclass 35, count 0 2006.173.16:28:39.96#ibcon#*before return 0, iclass 35, count 0 2006.173.16:28:39.96#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.16:28:39.96#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.16:28:39.96#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.16:28:39.96#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.16:28:39.96$vck44/va=6,3 2006.173.16:28:39.96#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.173.16:28:39.96#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.173.16:28:39.96#ibcon#ireg 11 cls_cnt 2 2006.173.16:28:39.96#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.16:28:40.02#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.16:28:40.02#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.16:28:40.02#ibcon#enter wrdev, iclass 37, count 2 2006.173.16:28:40.02#ibcon#first serial, iclass 37, count 2 2006.173.16:28:40.02#ibcon#enter sib2, iclass 37, count 2 2006.173.16:28:40.02#ibcon#flushed, iclass 37, count 2 2006.173.16:28:40.02#ibcon#about to write, iclass 37, count 2 2006.173.16:28:40.02#ibcon#wrote, iclass 37, count 2 2006.173.16:28:40.02#ibcon#about to read 3, iclass 37, count 2 2006.173.16:28:40.04#ibcon#read 3, iclass 37, count 2 2006.173.16:28:40.04#ibcon#about to read 4, iclass 37, count 2 2006.173.16:28:40.04#ibcon#read 4, iclass 37, count 2 2006.173.16:28:40.04#ibcon#about to read 5, iclass 37, count 2 2006.173.16:28:40.04#ibcon#read 5, iclass 37, count 2 2006.173.16:28:40.04#ibcon#about to read 6, iclass 37, count 2 2006.173.16:28:40.04#ibcon#read 6, iclass 37, count 2 2006.173.16:28:40.04#ibcon#end of sib2, iclass 37, count 2 2006.173.16:28:40.04#ibcon#*mode == 0, iclass 37, count 2 2006.173.16:28:40.04#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.173.16:28:40.04#ibcon#[25=AT06-03\r\n] 2006.173.16:28:40.04#ibcon#*before write, iclass 37, count 2 2006.173.16:28:40.04#ibcon#enter sib2, iclass 37, count 2 2006.173.16:28:40.04#ibcon#flushed, iclass 37, count 2 2006.173.16:28:40.04#ibcon#about to write, iclass 37, count 2 2006.173.16:28:40.04#ibcon#wrote, iclass 37, count 2 2006.173.16:28:40.04#ibcon#about to read 3, iclass 37, count 2 2006.173.16:28:40.07#ibcon#read 3, iclass 37, count 2 2006.173.16:28:40.07#ibcon#about to read 4, iclass 37, count 2 2006.173.16:28:40.07#ibcon#read 4, iclass 37, count 2 2006.173.16:28:40.07#ibcon#about to read 5, iclass 37, count 2 2006.173.16:28:40.07#ibcon#read 5, iclass 37, count 2 2006.173.16:28:40.07#ibcon#about to read 6, iclass 37, count 2 2006.173.16:28:40.07#ibcon#read 6, iclass 37, count 2 2006.173.16:28:40.07#ibcon#end of sib2, iclass 37, count 2 2006.173.16:28:40.07#ibcon#*after write, iclass 37, count 2 2006.173.16:28:40.07#ibcon#*before return 0, iclass 37, count 2 2006.173.16:28:40.07#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.16:28:40.07#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.173.16:28:40.07#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.173.16:28:40.07#ibcon#ireg 7 cls_cnt 0 2006.173.16:28:40.07#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.16:28:40.19#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.16:28:40.19#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.16:28:40.19#ibcon#enter wrdev, iclass 37, count 0 2006.173.16:28:40.19#ibcon#first serial, iclass 37, count 0 2006.173.16:28:40.19#ibcon#enter sib2, iclass 37, count 0 2006.173.16:28:40.19#ibcon#flushed, iclass 37, count 0 2006.173.16:28:40.19#ibcon#about to write, iclass 37, count 0 2006.173.16:28:40.19#ibcon#wrote, iclass 37, count 0 2006.173.16:28:40.19#ibcon#about to read 3, iclass 37, count 0 2006.173.16:28:40.21#ibcon#read 3, iclass 37, count 0 2006.173.16:28:40.21#ibcon#about to read 4, iclass 37, count 0 2006.173.16:28:40.21#ibcon#read 4, iclass 37, count 0 2006.173.16:28:40.21#ibcon#about to read 5, iclass 37, count 0 2006.173.16:28:40.21#ibcon#read 5, iclass 37, count 0 2006.173.16:28:40.21#ibcon#about to read 6, iclass 37, count 0 2006.173.16:28:40.21#ibcon#read 6, iclass 37, count 0 2006.173.16:28:40.21#ibcon#end of sib2, iclass 37, count 0 2006.173.16:28:40.21#ibcon#*mode == 0, iclass 37, count 0 2006.173.16:28:40.21#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.16:28:40.21#ibcon#[25=USB\r\n] 2006.173.16:28:40.21#ibcon#*before write, iclass 37, count 0 2006.173.16:28:40.21#ibcon#enter sib2, iclass 37, count 0 2006.173.16:28:40.21#ibcon#flushed, iclass 37, count 0 2006.173.16:28:40.21#ibcon#about to write, iclass 37, count 0 2006.173.16:28:40.21#ibcon#wrote, iclass 37, count 0 2006.173.16:28:40.21#ibcon#about to read 3, iclass 37, count 0 2006.173.16:28:40.24#ibcon#read 3, iclass 37, count 0 2006.173.16:28:40.24#ibcon#about to read 4, iclass 37, count 0 2006.173.16:28:40.24#ibcon#read 4, iclass 37, count 0 2006.173.16:28:40.24#ibcon#about to read 5, iclass 37, count 0 2006.173.16:28:40.24#ibcon#read 5, iclass 37, count 0 2006.173.16:28:40.24#ibcon#about to read 6, iclass 37, count 0 2006.173.16:28:40.24#ibcon#read 6, iclass 37, count 0 2006.173.16:28:40.24#ibcon#end of sib2, iclass 37, count 0 2006.173.16:28:40.24#ibcon#*after write, iclass 37, count 0 2006.173.16:28:40.24#ibcon#*before return 0, iclass 37, count 0 2006.173.16:28:40.24#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.16:28:40.24#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.173.16:28:40.24#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.16:28:40.24#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.16:28:40.24$vck44/valo=7,864.99 2006.173.16:28:40.24#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.16:28:40.24#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.16:28:40.24#ibcon#ireg 17 cls_cnt 0 2006.173.16:28:40.24#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.16:28:40.24#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.16:28:40.24#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.16:28:40.24#ibcon#enter wrdev, iclass 39, count 0 2006.173.16:28:40.24#ibcon#first serial, iclass 39, count 0 2006.173.16:28:40.24#ibcon#enter sib2, iclass 39, count 0 2006.173.16:28:40.24#ibcon#flushed, iclass 39, count 0 2006.173.16:28:40.24#ibcon#about to write, iclass 39, count 0 2006.173.16:28:40.24#ibcon#wrote, iclass 39, count 0 2006.173.16:28:40.24#ibcon#about to read 3, iclass 39, count 0 2006.173.16:28:40.26#ibcon#read 3, iclass 39, count 0 2006.173.16:28:40.26#ibcon#about to read 4, iclass 39, count 0 2006.173.16:28:40.26#ibcon#read 4, iclass 39, count 0 2006.173.16:28:40.26#ibcon#about to read 5, iclass 39, count 0 2006.173.16:28:40.26#ibcon#read 5, iclass 39, count 0 2006.173.16:28:40.26#ibcon#about to read 6, iclass 39, count 0 2006.173.16:28:40.26#ibcon#read 6, iclass 39, count 0 2006.173.16:28:40.26#ibcon#end of sib2, iclass 39, count 0 2006.173.16:28:40.26#ibcon#*mode == 0, iclass 39, count 0 2006.173.16:28:40.26#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.16:28:40.26#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.16:28:40.26#ibcon#*before write, iclass 39, count 0 2006.173.16:28:40.26#ibcon#enter sib2, iclass 39, count 0 2006.173.16:28:40.26#ibcon#flushed, iclass 39, count 0 2006.173.16:28:40.26#ibcon#about to write, iclass 39, count 0 2006.173.16:28:40.26#ibcon#wrote, iclass 39, count 0 2006.173.16:28:40.26#ibcon#about to read 3, iclass 39, count 0 2006.173.16:28:40.30#ibcon#read 3, iclass 39, count 0 2006.173.16:28:40.30#ibcon#about to read 4, iclass 39, count 0 2006.173.16:28:40.30#ibcon#read 4, iclass 39, count 0 2006.173.16:28:40.30#ibcon#about to read 5, iclass 39, count 0 2006.173.16:28:40.30#ibcon#read 5, iclass 39, count 0 2006.173.16:28:40.30#ibcon#about to read 6, iclass 39, count 0 2006.173.16:28:40.30#ibcon#read 6, iclass 39, count 0 2006.173.16:28:40.30#ibcon#end of sib2, iclass 39, count 0 2006.173.16:28:40.30#ibcon#*after write, iclass 39, count 0 2006.173.16:28:40.30#ibcon#*before return 0, iclass 39, count 0 2006.173.16:28:40.30#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.16:28:40.30#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.16:28:40.30#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.16:28:40.30#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.16:28:40.30$vck44/va=7,4 2006.173.16:28:40.30#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.16:28:40.30#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.16:28:40.30#ibcon#ireg 11 cls_cnt 2 2006.173.16:28:40.30#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.16:28:40.36#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.16:28:40.36#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.16:28:40.36#ibcon#enter wrdev, iclass 3, count 2 2006.173.16:28:40.36#ibcon#first serial, iclass 3, count 2 2006.173.16:28:40.36#ibcon#enter sib2, iclass 3, count 2 2006.173.16:28:40.36#ibcon#flushed, iclass 3, count 2 2006.173.16:28:40.36#ibcon#about to write, iclass 3, count 2 2006.173.16:28:40.36#ibcon#wrote, iclass 3, count 2 2006.173.16:28:40.36#ibcon#about to read 3, iclass 3, count 2 2006.173.16:28:40.38#ibcon#read 3, iclass 3, count 2 2006.173.16:28:40.38#ibcon#about to read 4, iclass 3, count 2 2006.173.16:28:40.38#ibcon#read 4, iclass 3, count 2 2006.173.16:28:40.38#ibcon#about to read 5, iclass 3, count 2 2006.173.16:28:40.38#ibcon#read 5, iclass 3, count 2 2006.173.16:28:40.38#ibcon#about to read 6, iclass 3, count 2 2006.173.16:28:40.38#ibcon#read 6, iclass 3, count 2 2006.173.16:28:40.38#ibcon#end of sib2, iclass 3, count 2 2006.173.16:28:40.38#ibcon#*mode == 0, iclass 3, count 2 2006.173.16:28:40.38#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.16:28:40.38#ibcon#[25=AT07-04\r\n] 2006.173.16:28:40.38#ibcon#*before write, iclass 3, count 2 2006.173.16:28:40.38#ibcon#enter sib2, iclass 3, count 2 2006.173.16:28:40.38#ibcon#flushed, iclass 3, count 2 2006.173.16:28:40.38#ibcon#about to write, iclass 3, count 2 2006.173.16:28:40.38#ibcon#wrote, iclass 3, count 2 2006.173.16:28:40.38#ibcon#about to read 3, iclass 3, count 2 2006.173.16:28:40.41#ibcon#read 3, iclass 3, count 2 2006.173.16:28:40.41#ibcon#about to read 4, iclass 3, count 2 2006.173.16:28:40.41#ibcon#read 4, iclass 3, count 2 2006.173.16:28:40.41#ibcon#about to read 5, iclass 3, count 2 2006.173.16:28:40.41#ibcon#read 5, iclass 3, count 2 2006.173.16:28:40.41#ibcon#about to read 6, iclass 3, count 2 2006.173.16:28:40.41#ibcon#read 6, iclass 3, count 2 2006.173.16:28:40.41#ibcon#end of sib2, iclass 3, count 2 2006.173.16:28:40.41#ibcon#*after write, iclass 3, count 2 2006.173.16:28:40.41#ibcon#*before return 0, iclass 3, count 2 2006.173.16:28:40.41#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.16:28:40.41#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.16:28:40.41#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.16:28:40.41#ibcon#ireg 7 cls_cnt 0 2006.173.16:28:40.41#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.16:28:40.53#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.16:28:40.53#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.16:28:40.53#ibcon#enter wrdev, iclass 3, count 0 2006.173.16:28:40.53#ibcon#first serial, iclass 3, count 0 2006.173.16:28:40.53#ibcon#enter sib2, iclass 3, count 0 2006.173.16:28:40.53#ibcon#flushed, iclass 3, count 0 2006.173.16:28:40.53#ibcon#about to write, iclass 3, count 0 2006.173.16:28:40.53#ibcon#wrote, iclass 3, count 0 2006.173.16:28:40.53#ibcon#about to read 3, iclass 3, count 0 2006.173.16:28:40.55#ibcon#read 3, iclass 3, count 0 2006.173.16:28:40.55#ibcon#about to read 4, iclass 3, count 0 2006.173.16:28:40.55#ibcon#read 4, iclass 3, count 0 2006.173.16:28:40.55#ibcon#about to read 5, iclass 3, count 0 2006.173.16:28:40.55#ibcon#read 5, iclass 3, count 0 2006.173.16:28:40.55#ibcon#about to read 6, iclass 3, count 0 2006.173.16:28:40.55#ibcon#read 6, iclass 3, count 0 2006.173.16:28:40.55#ibcon#end of sib2, iclass 3, count 0 2006.173.16:28:40.55#ibcon#*mode == 0, iclass 3, count 0 2006.173.16:28:40.55#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.16:28:40.55#ibcon#[25=USB\r\n] 2006.173.16:28:40.55#ibcon#*before write, iclass 3, count 0 2006.173.16:28:40.55#ibcon#enter sib2, iclass 3, count 0 2006.173.16:28:40.55#ibcon#flushed, iclass 3, count 0 2006.173.16:28:40.55#ibcon#about to write, iclass 3, count 0 2006.173.16:28:40.55#ibcon#wrote, iclass 3, count 0 2006.173.16:28:40.55#ibcon#about to read 3, iclass 3, count 0 2006.173.16:28:40.58#ibcon#read 3, iclass 3, count 0 2006.173.16:28:40.58#ibcon#about to read 4, iclass 3, count 0 2006.173.16:28:40.58#ibcon#read 4, iclass 3, count 0 2006.173.16:28:40.58#ibcon#about to read 5, iclass 3, count 0 2006.173.16:28:40.58#ibcon#read 5, iclass 3, count 0 2006.173.16:28:40.58#ibcon#about to read 6, iclass 3, count 0 2006.173.16:28:40.58#ibcon#read 6, iclass 3, count 0 2006.173.16:28:40.58#ibcon#end of sib2, iclass 3, count 0 2006.173.16:28:40.58#ibcon#*after write, iclass 3, count 0 2006.173.16:28:40.58#ibcon#*before return 0, iclass 3, count 0 2006.173.16:28:40.58#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.16:28:40.58#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.16:28:40.58#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.16:28:40.58#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.16:28:40.58$vck44/valo=8,884.99 2006.173.16:28:40.58#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.16:28:40.58#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.16:28:40.58#ibcon#ireg 17 cls_cnt 0 2006.173.16:28:40.58#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.16:28:40.58#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.16:28:40.58#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.16:28:40.58#ibcon#enter wrdev, iclass 5, count 0 2006.173.16:28:40.58#ibcon#first serial, iclass 5, count 0 2006.173.16:28:40.58#ibcon#enter sib2, iclass 5, count 0 2006.173.16:28:40.58#ibcon#flushed, iclass 5, count 0 2006.173.16:28:40.58#ibcon#about to write, iclass 5, count 0 2006.173.16:28:40.58#ibcon#wrote, iclass 5, count 0 2006.173.16:28:40.58#ibcon#about to read 3, iclass 5, count 0 2006.173.16:28:40.60#ibcon#read 3, iclass 5, count 0 2006.173.16:28:40.60#ibcon#about to read 4, iclass 5, count 0 2006.173.16:28:40.60#ibcon#read 4, iclass 5, count 0 2006.173.16:28:40.60#ibcon#about to read 5, iclass 5, count 0 2006.173.16:28:40.60#ibcon#read 5, iclass 5, count 0 2006.173.16:28:40.60#ibcon#about to read 6, iclass 5, count 0 2006.173.16:28:40.60#ibcon#read 6, iclass 5, count 0 2006.173.16:28:40.60#ibcon#end of sib2, iclass 5, count 0 2006.173.16:28:40.60#ibcon#*mode == 0, iclass 5, count 0 2006.173.16:28:40.60#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.16:28:40.60#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.16:28:40.60#ibcon#*before write, iclass 5, count 0 2006.173.16:28:40.60#ibcon#enter sib2, iclass 5, count 0 2006.173.16:28:40.60#ibcon#flushed, iclass 5, count 0 2006.173.16:28:40.60#ibcon#about to write, iclass 5, count 0 2006.173.16:28:40.60#ibcon#wrote, iclass 5, count 0 2006.173.16:28:40.60#ibcon#about to read 3, iclass 5, count 0 2006.173.16:28:40.64#ibcon#read 3, iclass 5, count 0 2006.173.16:28:40.64#ibcon#about to read 4, iclass 5, count 0 2006.173.16:28:40.64#ibcon#read 4, iclass 5, count 0 2006.173.16:28:40.64#ibcon#about to read 5, iclass 5, count 0 2006.173.16:28:40.64#ibcon#read 5, iclass 5, count 0 2006.173.16:28:40.64#ibcon#about to read 6, iclass 5, count 0 2006.173.16:28:40.64#ibcon#read 6, iclass 5, count 0 2006.173.16:28:40.64#ibcon#end of sib2, iclass 5, count 0 2006.173.16:28:40.64#ibcon#*after write, iclass 5, count 0 2006.173.16:28:40.64#ibcon#*before return 0, iclass 5, count 0 2006.173.16:28:40.64#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.16:28:40.64#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.16:28:40.64#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.16:28:40.64#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.16:28:40.64$vck44/va=8,4 2006.173.16:28:40.64#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.173.16:28:40.64#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.173.16:28:40.64#ibcon#ireg 11 cls_cnt 2 2006.173.16:28:40.64#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.16:28:40.70#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.16:28:40.70#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.16:28:40.70#ibcon#enter wrdev, iclass 7, count 2 2006.173.16:28:40.70#ibcon#first serial, iclass 7, count 2 2006.173.16:28:40.70#ibcon#enter sib2, iclass 7, count 2 2006.173.16:28:40.70#ibcon#flushed, iclass 7, count 2 2006.173.16:28:40.70#ibcon#about to write, iclass 7, count 2 2006.173.16:28:40.70#ibcon#wrote, iclass 7, count 2 2006.173.16:28:40.70#ibcon#about to read 3, iclass 7, count 2 2006.173.16:28:40.72#ibcon#read 3, iclass 7, count 2 2006.173.16:28:40.72#ibcon#about to read 4, iclass 7, count 2 2006.173.16:28:40.72#ibcon#read 4, iclass 7, count 2 2006.173.16:28:40.72#ibcon#about to read 5, iclass 7, count 2 2006.173.16:28:40.72#ibcon#read 5, iclass 7, count 2 2006.173.16:28:40.72#ibcon#about to read 6, iclass 7, count 2 2006.173.16:28:40.72#ibcon#read 6, iclass 7, count 2 2006.173.16:28:40.72#ibcon#end of sib2, iclass 7, count 2 2006.173.16:28:40.72#ibcon#*mode == 0, iclass 7, count 2 2006.173.16:28:40.72#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.173.16:28:40.72#ibcon#[25=AT08-04\r\n] 2006.173.16:28:40.72#ibcon#*before write, iclass 7, count 2 2006.173.16:28:40.72#ibcon#enter sib2, iclass 7, count 2 2006.173.16:28:40.72#ibcon#flushed, iclass 7, count 2 2006.173.16:28:40.72#ibcon#about to write, iclass 7, count 2 2006.173.16:28:40.72#ibcon#wrote, iclass 7, count 2 2006.173.16:28:40.72#ibcon#about to read 3, iclass 7, count 2 2006.173.16:28:40.75#ibcon#read 3, iclass 7, count 2 2006.173.16:28:40.75#ibcon#about to read 4, iclass 7, count 2 2006.173.16:28:40.75#ibcon#read 4, iclass 7, count 2 2006.173.16:28:40.75#ibcon#about to read 5, iclass 7, count 2 2006.173.16:28:40.75#ibcon#read 5, iclass 7, count 2 2006.173.16:28:40.75#ibcon#about to read 6, iclass 7, count 2 2006.173.16:28:40.75#ibcon#read 6, iclass 7, count 2 2006.173.16:28:40.75#ibcon#end of sib2, iclass 7, count 2 2006.173.16:28:40.75#ibcon#*after write, iclass 7, count 2 2006.173.16:28:40.75#ibcon#*before return 0, iclass 7, count 2 2006.173.16:28:40.75#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.16:28:40.75#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.173.16:28:40.75#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.173.16:28:40.75#ibcon#ireg 7 cls_cnt 0 2006.173.16:28:40.75#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.16:28:40.87#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.16:28:40.87#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.16:28:40.87#ibcon#enter wrdev, iclass 7, count 0 2006.173.16:28:40.87#ibcon#first serial, iclass 7, count 0 2006.173.16:28:40.87#ibcon#enter sib2, iclass 7, count 0 2006.173.16:28:40.87#ibcon#flushed, iclass 7, count 0 2006.173.16:28:40.87#ibcon#about to write, iclass 7, count 0 2006.173.16:28:40.87#ibcon#wrote, iclass 7, count 0 2006.173.16:28:40.87#ibcon#about to read 3, iclass 7, count 0 2006.173.16:28:40.89#ibcon#read 3, iclass 7, count 0 2006.173.16:28:40.89#ibcon#about to read 4, iclass 7, count 0 2006.173.16:28:40.89#ibcon#read 4, iclass 7, count 0 2006.173.16:28:40.89#ibcon#about to read 5, iclass 7, count 0 2006.173.16:28:40.89#ibcon#read 5, iclass 7, count 0 2006.173.16:28:40.89#ibcon#about to read 6, iclass 7, count 0 2006.173.16:28:40.89#ibcon#read 6, iclass 7, count 0 2006.173.16:28:40.89#ibcon#end of sib2, iclass 7, count 0 2006.173.16:28:40.89#ibcon#*mode == 0, iclass 7, count 0 2006.173.16:28:40.89#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.16:28:40.89#ibcon#[25=USB\r\n] 2006.173.16:28:40.89#ibcon#*before write, iclass 7, count 0 2006.173.16:28:40.89#ibcon#enter sib2, iclass 7, count 0 2006.173.16:28:40.89#ibcon#flushed, iclass 7, count 0 2006.173.16:28:40.89#ibcon#about to write, iclass 7, count 0 2006.173.16:28:40.89#ibcon#wrote, iclass 7, count 0 2006.173.16:28:40.89#ibcon#about to read 3, iclass 7, count 0 2006.173.16:28:40.92#ibcon#read 3, iclass 7, count 0 2006.173.16:28:40.92#ibcon#about to read 4, iclass 7, count 0 2006.173.16:28:40.92#ibcon#read 4, iclass 7, count 0 2006.173.16:28:40.92#ibcon#about to read 5, iclass 7, count 0 2006.173.16:28:40.92#ibcon#read 5, iclass 7, count 0 2006.173.16:28:40.92#ibcon#about to read 6, iclass 7, count 0 2006.173.16:28:40.92#ibcon#read 6, iclass 7, count 0 2006.173.16:28:40.92#ibcon#end of sib2, iclass 7, count 0 2006.173.16:28:40.92#ibcon#*after write, iclass 7, count 0 2006.173.16:28:40.92#ibcon#*before return 0, iclass 7, count 0 2006.173.16:28:40.92#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.16:28:40.92#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.173.16:28:40.92#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.16:28:40.92#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.16:28:40.92$vck44/vblo=1,629.99 2006.173.16:28:40.92#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.16:28:40.92#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.16:28:40.92#ibcon#ireg 17 cls_cnt 0 2006.173.16:28:40.92#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.16:28:40.92#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.16:28:40.92#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.16:28:40.92#ibcon#enter wrdev, iclass 11, count 0 2006.173.16:28:40.92#ibcon#first serial, iclass 11, count 0 2006.173.16:28:40.92#ibcon#enter sib2, iclass 11, count 0 2006.173.16:28:40.92#ibcon#flushed, iclass 11, count 0 2006.173.16:28:40.92#ibcon#about to write, iclass 11, count 0 2006.173.16:28:40.92#ibcon#wrote, iclass 11, count 0 2006.173.16:28:40.92#ibcon#about to read 3, iclass 11, count 0 2006.173.16:28:40.94#ibcon#read 3, iclass 11, count 0 2006.173.16:28:40.94#ibcon#about to read 4, iclass 11, count 0 2006.173.16:28:40.94#ibcon#read 4, iclass 11, count 0 2006.173.16:28:40.94#ibcon#about to read 5, iclass 11, count 0 2006.173.16:28:40.94#ibcon#read 5, iclass 11, count 0 2006.173.16:28:40.94#ibcon#about to read 6, iclass 11, count 0 2006.173.16:28:40.94#ibcon#read 6, iclass 11, count 0 2006.173.16:28:40.94#ibcon#end of sib2, iclass 11, count 0 2006.173.16:28:40.94#ibcon#*mode == 0, iclass 11, count 0 2006.173.16:28:40.94#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.16:28:40.94#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.16:28:40.94#ibcon#*before write, iclass 11, count 0 2006.173.16:28:40.94#ibcon#enter sib2, iclass 11, count 0 2006.173.16:28:40.94#ibcon#flushed, iclass 11, count 0 2006.173.16:28:40.94#ibcon#about to write, iclass 11, count 0 2006.173.16:28:40.94#ibcon#wrote, iclass 11, count 0 2006.173.16:28:40.94#ibcon#about to read 3, iclass 11, count 0 2006.173.16:28:40.98#ibcon#read 3, iclass 11, count 0 2006.173.16:28:40.98#ibcon#about to read 4, iclass 11, count 0 2006.173.16:28:40.98#ibcon#read 4, iclass 11, count 0 2006.173.16:28:40.98#ibcon#about to read 5, iclass 11, count 0 2006.173.16:28:40.98#ibcon#read 5, iclass 11, count 0 2006.173.16:28:40.98#ibcon#about to read 6, iclass 11, count 0 2006.173.16:28:40.98#ibcon#read 6, iclass 11, count 0 2006.173.16:28:40.98#ibcon#end of sib2, iclass 11, count 0 2006.173.16:28:40.98#ibcon#*after write, iclass 11, count 0 2006.173.16:28:40.98#ibcon#*before return 0, iclass 11, count 0 2006.173.16:28:40.98#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.16:28:40.98#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.16:28:40.98#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.16:28:40.98#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.16:28:40.98$vck44/vb=1,4 2006.173.16:28:40.98#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.173.16:28:40.98#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.173.16:28:40.98#ibcon#ireg 11 cls_cnt 2 2006.173.16:28:40.98#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.16:28:40.98#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.16:28:40.98#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.16:28:40.98#ibcon#enter wrdev, iclass 13, count 2 2006.173.16:28:40.98#ibcon#first serial, iclass 13, count 2 2006.173.16:28:40.98#ibcon#enter sib2, iclass 13, count 2 2006.173.16:28:40.98#ibcon#flushed, iclass 13, count 2 2006.173.16:28:40.98#ibcon#about to write, iclass 13, count 2 2006.173.16:28:40.98#ibcon#wrote, iclass 13, count 2 2006.173.16:28:40.98#ibcon#about to read 3, iclass 13, count 2 2006.173.16:28:41.00#ibcon#read 3, iclass 13, count 2 2006.173.16:28:41.00#ibcon#about to read 4, iclass 13, count 2 2006.173.16:28:41.00#ibcon#read 4, iclass 13, count 2 2006.173.16:28:41.00#ibcon#about to read 5, iclass 13, count 2 2006.173.16:28:41.00#ibcon#read 5, iclass 13, count 2 2006.173.16:28:41.00#ibcon#about to read 6, iclass 13, count 2 2006.173.16:28:41.00#ibcon#read 6, iclass 13, count 2 2006.173.16:28:41.00#ibcon#end of sib2, iclass 13, count 2 2006.173.16:28:41.00#ibcon#*mode == 0, iclass 13, count 2 2006.173.16:28:41.00#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.173.16:28:41.00#ibcon#[27=AT01-04\r\n] 2006.173.16:28:41.00#ibcon#*before write, iclass 13, count 2 2006.173.16:28:41.00#ibcon#enter sib2, iclass 13, count 2 2006.173.16:28:41.00#ibcon#flushed, iclass 13, count 2 2006.173.16:28:41.00#ibcon#about to write, iclass 13, count 2 2006.173.16:28:41.00#ibcon#wrote, iclass 13, count 2 2006.173.16:28:41.00#ibcon#about to read 3, iclass 13, count 2 2006.173.16:28:41.03#ibcon#read 3, iclass 13, count 2 2006.173.16:28:41.03#ibcon#about to read 4, iclass 13, count 2 2006.173.16:28:41.03#ibcon#read 4, iclass 13, count 2 2006.173.16:28:41.03#ibcon#about to read 5, iclass 13, count 2 2006.173.16:28:41.03#ibcon#read 5, iclass 13, count 2 2006.173.16:28:41.03#ibcon#about to read 6, iclass 13, count 2 2006.173.16:28:41.03#ibcon#read 6, iclass 13, count 2 2006.173.16:28:41.03#ibcon#end of sib2, iclass 13, count 2 2006.173.16:28:41.03#ibcon#*after write, iclass 13, count 2 2006.173.16:28:41.03#ibcon#*before return 0, iclass 13, count 2 2006.173.16:28:41.03#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.16:28:41.03#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.173.16:28:41.03#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.173.16:28:41.03#ibcon#ireg 7 cls_cnt 0 2006.173.16:28:41.03#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.16:28:41.15#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.16:28:41.15#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.16:28:41.15#ibcon#enter wrdev, iclass 13, count 0 2006.173.16:28:41.15#ibcon#first serial, iclass 13, count 0 2006.173.16:28:41.15#ibcon#enter sib2, iclass 13, count 0 2006.173.16:28:41.15#ibcon#flushed, iclass 13, count 0 2006.173.16:28:41.15#ibcon#about to write, iclass 13, count 0 2006.173.16:28:41.15#ibcon#wrote, iclass 13, count 0 2006.173.16:28:41.15#ibcon#about to read 3, iclass 13, count 0 2006.173.16:28:41.17#ibcon#read 3, iclass 13, count 0 2006.173.16:28:41.17#ibcon#about to read 4, iclass 13, count 0 2006.173.16:28:41.17#ibcon#read 4, iclass 13, count 0 2006.173.16:28:41.17#ibcon#about to read 5, iclass 13, count 0 2006.173.16:28:41.17#ibcon#read 5, iclass 13, count 0 2006.173.16:28:41.17#ibcon#about to read 6, iclass 13, count 0 2006.173.16:28:41.17#ibcon#read 6, iclass 13, count 0 2006.173.16:28:41.17#ibcon#end of sib2, iclass 13, count 0 2006.173.16:28:41.17#ibcon#*mode == 0, iclass 13, count 0 2006.173.16:28:41.17#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.16:28:41.17#ibcon#[27=USB\r\n] 2006.173.16:28:41.17#ibcon#*before write, iclass 13, count 0 2006.173.16:28:41.17#ibcon#enter sib2, iclass 13, count 0 2006.173.16:28:41.17#ibcon#flushed, iclass 13, count 0 2006.173.16:28:41.17#ibcon#about to write, iclass 13, count 0 2006.173.16:28:41.17#ibcon#wrote, iclass 13, count 0 2006.173.16:28:41.17#ibcon#about to read 3, iclass 13, count 0 2006.173.16:28:41.20#ibcon#read 3, iclass 13, count 0 2006.173.16:28:41.20#ibcon#about to read 4, iclass 13, count 0 2006.173.16:28:41.20#ibcon#read 4, iclass 13, count 0 2006.173.16:28:41.20#ibcon#about to read 5, iclass 13, count 0 2006.173.16:28:41.20#ibcon#read 5, iclass 13, count 0 2006.173.16:28:41.20#ibcon#about to read 6, iclass 13, count 0 2006.173.16:28:41.20#ibcon#read 6, iclass 13, count 0 2006.173.16:28:41.20#ibcon#end of sib2, iclass 13, count 0 2006.173.16:28:41.20#ibcon#*after write, iclass 13, count 0 2006.173.16:28:41.20#ibcon#*before return 0, iclass 13, count 0 2006.173.16:28:41.20#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.16:28:41.20#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.173.16:28:41.20#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.16:28:41.20#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.16:28:41.20$vck44/vblo=2,634.99 2006.173.16:28:41.20#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.16:28:41.20#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.16:28:41.20#ibcon#ireg 17 cls_cnt 0 2006.173.16:28:41.20#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.16:28:41.20#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.16:28:41.20#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.16:28:41.20#ibcon#enter wrdev, iclass 15, count 0 2006.173.16:28:41.20#ibcon#first serial, iclass 15, count 0 2006.173.16:28:41.20#ibcon#enter sib2, iclass 15, count 0 2006.173.16:28:41.20#ibcon#flushed, iclass 15, count 0 2006.173.16:28:41.20#ibcon#about to write, iclass 15, count 0 2006.173.16:28:41.20#ibcon#wrote, iclass 15, count 0 2006.173.16:28:41.20#ibcon#about to read 3, iclass 15, count 0 2006.173.16:28:41.22#ibcon#read 3, iclass 15, count 0 2006.173.16:28:41.22#ibcon#about to read 4, iclass 15, count 0 2006.173.16:28:41.22#ibcon#read 4, iclass 15, count 0 2006.173.16:28:41.22#ibcon#about to read 5, iclass 15, count 0 2006.173.16:28:41.22#ibcon#read 5, iclass 15, count 0 2006.173.16:28:41.22#ibcon#about to read 6, iclass 15, count 0 2006.173.16:28:41.22#ibcon#read 6, iclass 15, count 0 2006.173.16:28:41.22#ibcon#end of sib2, iclass 15, count 0 2006.173.16:28:41.22#ibcon#*mode == 0, iclass 15, count 0 2006.173.16:28:41.22#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.16:28:41.22#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.16:28:41.22#ibcon#*before write, iclass 15, count 0 2006.173.16:28:41.22#ibcon#enter sib2, iclass 15, count 0 2006.173.16:28:41.22#ibcon#flushed, iclass 15, count 0 2006.173.16:28:41.22#ibcon#about to write, iclass 15, count 0 2006.173.16:28:41.22#ibcon#wrote, iclass 15, count 0 2006.173.16:28:41.22#ibcon#about to read 3, iclass 15, count 0 2006.173.16:28:41.26#ibcon#read 3, iclass 15, count 0 2006.173.16:28:41.26#ibcon#about to read 4, iclass 15, count 0 2006.173.16:28:41.26#ibcon#read 4, iclass 15, count 0 2006.173.16:28:41.26#ibcon#about to read 5, iclass 15, count 0 2006.173.16:28:41.26#ibcon#read 5, iclass 15, count 0 2006.173.16:28:41.26#ibcon#about to read 6, iclass 15, count 0 2006.173.16:28:41.26#ibcon#read 6, iclass 15, count 0 2006.173.16:28:41.26#ibcon#end of sib2, iclass 15, count 0 2006.173.16:28:41.26#ibcon#*after write, iclass 15, count 0 2006.173.16:28:41.26#ibcon#*before return 0, iclass 15, count 0 2006.173.16:28:41.26#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.16:28:41.26#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.16:28:41.26#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.16:28:41.26#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.16:28:41.26$vck44/vb=2,4 2006.173.16:28:41.26#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.16:28:41.26#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.16:28:41.26#ibcon#ireg 11 cls_cnt 2 2006.173.16:28:41.26#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.16:28:41.32#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.16:28:41.32#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.16:28:41.32#ibcon#enter wrdev, iclass 17, count 2 2006.173.16:28:41.32#ibcon#first serial, iclass 17, count 2 2006.173.16:28:41.32#ibcon#enter sib2, iclass 17, count 2 2006.173.16:28:41.32#ibcon#flushed, iclass 17, count 2 2006.173.16:28:41.32#ibcon#about to write, iclass 17, count 2 2006.173.16:28:41.32#ibcon#wrote, iclass 17, count 2 2006.173.16:28:41.32#ibcon#about to read 3, iclass 17, count 2 2006.173.16:28:41.34#ibcon#read 3, iclass 17, count 2 2006.173.16:28:41.34#ibcon#about to read 4, iclass 17, count 2 2006.173.16:28:41.34#ibcon#read 4, iclass 17, count 2 2006.173.16:28:41.34#ibcon#about to read 5, iclass 17, count 2 2006.173.16:28:41.34#ibcon#read 5, iclass 17, count 2 2006.173.16:28:41.34#ibcon#about to read 6, iclass 17, count 2 2006.173.16:28:41.34#ibcon#read 6, iclass 17, count 2 2006.173.16:28:41.34#ibcon#end of sib2, iclass 17, count 2 2006.173.16:28:41.34#ibcon#*mode == 0, iclass 17, count 2 2006.173.16:28:41.34#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.16:28:41.34#ibcon#[27=AT02-04\r\n] 2006.173.16:28:41.34#ibcon#*before write, iclass 17, count 2 2006.173.16:28:41.34#ibcon#enter sib2, iclass 17, count 2 2006.173.16:28:41.34#ibcon#flushed, iclass 17, count 2 2006.173.16:28:41.34#ibcon#about to write, iclass 17, count 2 2006.173.16:28:41.34#ibcon#wrote, iclass 17, count 2 2006.173.16:28:41.34#ibcon#about to read 3, iclass 17, count 2 2006.173.16:28:41.37#ibcon#read 3, iclass 17, count 2 2006.173.16:28:41.37#ibcon#about to read 4, iclass 17, count 2 2006.173.16:28:41.37#ibcon#read 4, iclass 17, count 2 2006.173.16:28:41.37#ibcon#about to read 5, iclass 17, count 2 2006.173.16:28:41.37#ibcon#read 5, iclass 17, count 2 2006.173.16:28:41.37#ibcon#about to read 6, iclass 17, count 2 2006.173.16:28:41.37#ibcon#read 6, iclass 17, count 2 2006.173.16:28:41.37#ibcon#end of sib2, iclass 17, count 2 2006.173.16:28:41.37#ibcon#*after write, iclass 17, count 2 2006.173.16:28:41.37#ibcon#*before return 0, iclass 17, count 2 2006.173.16:28:41.37#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.16:28:41.37#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.16:28:41.37#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.16:28:41.37#ibcon#ireg 7 cls_cnt 0 2006.173.16:28:41.37#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.16:28:41.49#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.16:28:41.49#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.16:28:41.49#ibcon#enter wrdev, iclass 17, count 0 2006.173.16:28:41.49#ibcon#first serial, iclass 17, count 0 2006.173.16:28:41.49#ibcon#enter sib2, iclass 17, count 0 2006.173.16:28:41.49#ibcon#flushed, iclass 17, count 0 2006.173.16:28:41.49#ibcon#about to write, iclass 17, count 0 2006.173.16:28:41.49#ibcon#wrote, iclass 17, count 0 2006.173.16:28:41.49#ibcon#about to read 3, iclass 17, count 0 2006.173.16:28:41.51#ibcon#read 3, iclass 17, count 0 2006.173.16:28:41.51#ibcon#about to read 4, iclass 17, count 0 2006.173.16:28:41.51#ibcon#read 4, iclass 17, count 0 2006.173.16:28:41.51#ibcon#about to read 5, iclass 17, count 0 2006.173.16:28:41.51#ibcon#read 5, iclass 17, count 0 2006.173.16:28:41.51#ibcon#about to read 6, iclass 17, count 0 2006.173.16:28:41.51#ibcon#read 6, iclass 17, count 0 2006.173.16:28:41.51#ibcon#end of sib2, iclass 17, count 0 2006.173.16:28:41.51#ibcon#*mode == 0, iclass 17, count 0 2006.173.16:28:41.51#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.16:28:41.51#ibcon#[27=USB\r\n] 2006.173.16:28:41.51#ibcon#*before write, iclass 17, count 0 2006.173.16:28:41.51#ibcon#enter sib2, iclass 17, count 0 2006.173.16:28:41.51#ibcon#flushed, iclass 17, count 0 2006.173.16:28:41.51#ibcon#about to write, iclass 17, count 0 2006.173.16:28:41.51#ibcon#wrote, iclass 17, count 0 2006.173.16:28:41.51#ibcon#about to read 3, iclass 17, count 0 2006.173.16:28:41.54#ibcon#read 3, iclass 17, count 0 2006.173.16:28:41.54#ibcon#about to read 4, iclass 17, count 0 2006.173.16:28:41.54#ibcon#read 4, iclass 17, count 0 2006.173.16:28:41.54#ibcon#about to read 5, iclass 17, count 0 2006.173.16:28:41.54#ibcon#read 5, iclass 17, count 0 2006.173.16:28:41.54#ibcon#about to read 6, iclass 17, count 0 2006.173.16:28:41.54#ibcon#read 6, iclass 17, count 0 2006.173.16:28:41.54#ibcon#end of sib2, iclass 17, count 0 2006.173.16:28:41.54#ibcon#*after write, iclass 17, count 0 2006.173.16:28:41.54#ibcon#*before return 0, iclass 17, count 0 2006.173.16:28:41.54#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.16:28:41.54#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.16:28:41.54#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.16:28:41.54#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.16:28:41.54$vck44/vblo=3,649.99 2006.173.16:28:41.54#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.16:28:41.54#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.16:28:41.54#ibcon#ireg 17 cls_cnt 0 2006.173.16:28:41.54#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.16:28:41.54#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.16:28:41.54#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.16:28:41.54#ibcon#enter wrdev, iclass 19, count 0 2006.173.16:28:41.54#ibcon#first serial, iclass 19, count 0 2006.173.16:28:41.54#ibcon#enter sib2, iclass 19, count 0 2006.173.16:28:41.54#ibcon#flushed, iclass 19, count 0 2006.173.16:28:41.54#ibcon#about to write, iclass 19, count 0 2006.173.16:28:41.54#ibcon#wrote, iclass 19, count 0 2006.173.16:28:41.54#ibcon#about to read 3, iclass 19, count 0 2006.173.16:28:41.56#ibcon#read 3, iclass 19, count 0 2006.173.16:28:41.56#ibcon#about to read 4, iclass 19, count 0 2006.173.16:28:41.56#ibcon#read 4, iclass 19, count 0 2006.173.16:28:41.56#ibcon#about to read 5, iclass 19, count 0 2006.173.16:28:41.56#ibcon#read 5, iclass 19, count 0 2006.173.16:28:41.56#ibcon#about to read 6, iclass 19, count 0 2006.173.16:28:41.56#ibcon#read 6, iclass 19, count 0 2006.173.16:28:41.56#ibcon#end of sib2, iclass 19, count 0 2006.173.16:28:41.56#ibcon#*mode == 0, iclass 19, count 0 2006.173.16:28:41.56#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.16:28:41.56#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.16:28:41.56#ibcon#*before write, iclass 19, count 0 2006.173.16:28:41.56#ibcon#enter sib2, iclass 19, count 0 2006.173.16:28:41.56#ibcon#flushed, iclass 19, count 0 2006.173.16:28:41.56#ibcon#about to write, iclass 19, count 0 2006.173.16:28:41.56#ibcon#wrote, iclass 19, count 0 2006.173.16:28:41.56#ibcon#about to read 3, iclass 19, count 0 2006.173.16:28:41.60#ibcon#read 3, iclass 19, count 0 2006.173.16:28:41.60#ibcon#about to read 4, iclass 19, count 0 2006.173.16:28:41.60#ibcon#read 4, iclass 19, count 0 2006.173.16:28:41.60#ibcon#about to read 5, iclass 19, count 0 2006.173.16:28:41.60#ibcon#read 5, iclass 19, count 0 2006.173.16:28:41.60#ibcon#about to read 6, iclass 19, count 0 2006.173.16:28:41.60#ibcon#read 6, iclass 19, count 0 2006.173.16:28:41.60#ibcon#end of sib2, iclass 19, count 0 2006.173.16:28:41.60#ibcon#*after write, iclass 19, count 0 2006.173.16:28:41.60#ibcon#*before return 0, iclass 19, count 0 2006.173.16:28:41.60#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.16:28:41.60#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.16:28:41.60#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.16:28:41.60#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.16:28:41.60$vck44/vb=3,4 2006.173.16:28:41.60#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.16:28:41.60#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.16:28:41.60#ibcon#ireg 11 cls_cnt 2 2006.173.16:28:41.60#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.16:28:41.66#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.16:28:41.66#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.16:28:41.66#ibcon#enter wrdev, iclass 21, count 2 2006.173.16:28:41.66#ibcon#first serial, iclass 21, count 2 2006.173.16:28:41.66#ibcon#enter sib2, iclass 21, count 2 2006.173.16:28:41.66#ibcon#flushed, iclass 21, count 2 2006.173.16:28:41.66#ibcon#about to write, iclass 21, count 2 2006.173.16:28:41.66#ibcon#wrote, iclass 21, count 2 2006.173.16:28:41.66#ibcon#about to read 3, iclass 21, count 2 2006.173.16:28:41.68#ibcon#read 3, iclass 21, count 2 2006.173.16:28:41.68#ibcon#about to read 4, iclass 21, count 2 2006.173.16:28:41.68#ibcon#read 4, iclass 21, count 2 2006.173.16:28:41.68#ibcon#about to read 5, iclass 21, count 2 2006.173.16:28:41.68#ibcon#read 5, iclass 21, count 2 2006.173.16:28:41.68#ibcon#about to read 6, iclass 21, count 2 2006.173.16:28:41.68#ibcon#read 6, iclass 21, count 2 2006.173.16:28:41.68#ibcon#end of sib2, iclass 21, count 2 2006.173.16:28:41.68#ibcon#*mode == 0, iclass 21, count 2 2006.173.16:28:41.68#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.16:28:41.68#ibcon#[27=AT03-04\r\n] 2006.173.16:28:41.68#ibcon#*before write, iclass 21, count 2 2006.173.16:28:41.68#ibcon#enter sib2, iclass 21, count 2 2006.173.16:28:41.68#ibcon#flushed, iclass 21, count 2 2006.173.16:28:41.68#ibcon#about to write, iclass 21, count 2 2006.173.16:28:41.68#ibcon#wrote, iclass 21, count 2 2006.173.16:28:41.68#ibcon#about to read 3, iclass 21, count 2 2006.173.16:28:41.71#ibcon#read 3, iclass 21, count 2 2006.173.16:28:41.71#ibcon#about to read 4, iclass 21, count 2 2006.173.16:28:41.71#ibcon#read 4, iclass 21, count 2 2006.173.16:28:41.71#ibcon#about to read 5, iclass 21, count 2 2006.173.16:28:41.71#ibcon#read 5, iclass 21, count 2 2006.173.16:28:41.71#ibcon#about to read 6, iclass 21, count 2 2006.173.16:28:41.71#ibcon#read 6, iclass 21, count 2 2006.173.16:28:41.71#ibcon#end of sib2, iclass 21, count 2 2006.173.16:28:41.71#ibcon#*after write, iclass 21, count 2 2006.173.16:28:41.71#ibcon#*before return 0, iclass 21, count 2 2006.173.16:28:41.71#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.16:28:41.71#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.16:28:41.71#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.16:28:41.71#ibcon#ireg 7 cls_cnt 0 2006.173.16:28:41.71#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.16:28:41.83#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.16:28:41.83#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.16:28:41.83#ibcon#enter wrdev, iclass 21, count 0 2006.173.16:28:41.83#ibcon#first serial, iclass 21, count 0 2006.173.16:28:41.83#ibcon#enter sib2, iclass 21, count 0 2006.173.16:28:41.83#ibcon#flushed, iclass 21, count 0 2006.173.16:28:41.83#ibcon#about to write, iclass 21, count 0 2006.173.16:28:41.83#ibcon#wrote, iclass 21, count 0 2006.173.16:28:41.83#ibcon#about to read 3, iclass 21, count 0 2006.173.16:28:41.85#ibcon#read 3, iclass 21, count 0 2006.173.16:28:41.85#ibcon#about to read 4, iclass 21, count 0 2006.173.16:28:41.85#ibcon#read 4, iclass 21, count 0 2006.173.16:28:41.85#ibcon#about to read 5, iclass 21, count 0 2006.173.16:28:41.85#ibcon#read 5, iclass 21, count 0 2006.173.16:28:41.85#ibcon#about to read 6, iclass 21, count 0 2006.173.16:28:41.85#ibcon#read 6, iclass 21, count 0 2006.173.16:28:41.85#ibcon#end of sib2, iclass 21, count 0 2006.173.16:28:41.85#ibcon#*mode == 0, iclass 21, count 0 2006.173.16:28:41.85#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.16:28:41.85#ibcon#[27=USB\r\n] 2006.173.16:28:41.85#ibcon#*before write, iclass 21, count 0 2006.173.16:28:41.85#ibcon#enter sib2, iclass 21, count 0 2006.173.16:28:41.85#ibcon#flushed, iclass 21, count 0 2006.173.16:28:41.85#ibcon#about to write, iclass 21, count 0 2006.173.16:28:41.85#ibcon#wrote, iclass 21, count 0 2006.173.16:28:41.85#ibcon#about to read 3, iclass 21, count 0 2006.173.16:28:41.88#ibcon#read 3, iclass 21, count 0 2006.173.16:28:41.88#ibcon#about to read 4, iclass 21, count 0 2006.173.16:28:41.88#ibcon#read 4, iclass 21, count 0 2006.173.16:28:41.88#ibcon#about to read 5, iclass 21, count 0 2006.173.16:28:41.88#ibcon#read 5, iclass 21, count 0 2006.173.16:28:41.88#ibcon#about to read 6, iclass 21, count 0 2006.173.16:28:41.88#ibcon#read 6, iclass 21, count 0 2006.173.16:28:41.88#ibcon#end of sib2, iclass 21, count 0 2006.173.16:28:41.88#ibcon#*after write, iclass 21, count 0 2006.173.16:28:41.88#ibcon#*before return 0, iclass 21, count 0 2006.173.16:28:41.88#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.16:28:41.88#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.16:28:41.88#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.16:28:41.88#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.16:28:41.88$vck44/vblo=4,679.99 2006.173.16:28:41.88#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.16:28:41.88#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.16:28:41.88#ibcon#ireg 17 cls_cnt 0 2006.173.16:28:41.88#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.16:28:41.88#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.16:28:41.88#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.16:28:41.88#ibcon#enter wrdev, iclass 23, count 0 2006.173.16:28:41.88#ibcon#first serial, iclass 23, count 0 2006.173.16:28:41.88#ibcon#enter sib2, iclass 23, count 0 2006.173.16:28:41.88#ibcon#flushed, iclass 23, count 0 2006.173.16:28:41.88#ibcon#about to write, iclass 23, count 0 2006.173.16:28:41.88#ibcon#wrote, iclass 23, count 0 2006.173.16:28:41.88#ibcon#about to read 3, iclass 23, count 0 2006.173.16:28:41.90#ibcon#read 3, iclass 23, count 0 2006.173.16:28:41.90#ibcon#about to read 4, iclass 23, count 0 2006.173.16:28:41.90#ibcon#read 4, iclass 23, count 0 2006.173.16:28:41.90#ibcon#about to read 5, iclass 23, count 0 2006.173.16:28:41.90#ibcon#read 5, iclass 23, count 0 2006.173.16:28:41.90#ibcon#about to read 6, iclass 23, count 0 2006.173.16:28:41.90#ibcon#read 6, iclass 23, count 0 2006.173.16:28:41.90#ibcon#end of sib2, iclass 23, count 0 2006.173.16:28:41.90#ibcon#*mode == 0, iclass 23, count 0 2006.173.16:28:41.90#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.16:28:41.90#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.16:28:41.90#ibcon#*before write, iclass 23, count 0 2006.173.16:28:41.90#ibcon#enter sib2, iclass 23, count 0 2006.173.16:28:41.90#ibcon#flushed, iclass 23, count 0 2006.173.16:28:41.90#ibcon#about to write, iclass 23, count 0 2006.173.16:28:41.90#ibcon#wrote, iclass 23, count 0 2006.173.16:28:41.90#ibcon#about to read 3, iclass 23, count 0 2006.173.16:28:41.94#ibcon#read 3, iclass 23, count 0 2006.173.16:28:41.94#ibcon#about to read 4, iclass 23, count 0 2006.173.16:28:41.94#ibcon#read 4, iclass 23, count 0 2006.173.16:28:41.94#ibcon#about to read 5, iclass 23, count 0 2006.173.16:28:41.94#ibcon#read 5, iclass 23, count 0 2006.173.16:28:41.94#ibcon#about to read 6, iclass 23, count 0 2006.173.16:28:41.94#ibcon#read 6, iclass 23, count 0 2006.173.16:28:41.94#ibcon#end of sib2, iclass 23, count 0 2006.173.16:28:41.94#ibcon#*after write, iclass 23, count 0 2006.173.16:28:41.94#ibcon#*before return 0, iclass 23, count 0 2006.173.16:28:41.94#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.16:28:41.94#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.16:28:41.94#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.16:28:41.94#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.16:28:41.94$vck44/vb=4,4 2006.173.16:28:41.94#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.16:28:41.94#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.16:28:41.94#ibcon#ireg 11 cls_cnt 2 2006.173.16:28:41.94#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.16:28:42.00#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.16:28:42.00#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.16:28:42.00#ibcon#enter wrdev, iclass 25, count 2 2006.173.16:28:42.00#ibcon#first serial, iclass 25, count 2 2006.173.16:28:42.00#ibcon#enter sib2, iclass 25, count 2 2006.173.16:28:42.00#ibcon#flushed, iclass 25, count 2 2006.173.16:28:42.00#ibcon#about to write, iclass 25, count 2 2006.173.16:28:42.00#ibcon#wrote, iclass 25, count 2 2006.173.16:28:42.00#ibcon#about to read 3, iclass 25, count 2 2006.173.16:28:42.02#ibcon#read 3, iclass 25, count 2 2006.173.16:28:42.02#ibcon#about to read 4, iclass 25, count 2 2006.173.16:28:42.02#ibcon#read 4, iclass 25, count 2 2006.173.16:28:42.02#ibcon#about to read 5, iclass 25, count 2 2006.173.16:28:42.02#ibcon#read 5, iclass 25, count 2 2006.173.16:28:42.02#ibcon#about to read 6, iclass 25, count 2 2006.173.16:28:42.02#ibcon#read 6, iclass 25, count 2 2006.173.16:28:42.02#ibcon#end of sib2, iclass 25, count 2 2006.173.16:28:42.02#ibcon#*mode == 0, iclass 25, count 2 2006.173.16:28:42.02#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.16:28:42.02#ibcon#[27=AT04-04\r\n] 2006.173.16:28:42.02#ibcon#*before write, iclass 25, count 2 2006.173.16:28:42.02#ibcon#enter sib2, iclass 25, count 2 2006.173.16:28:42.02#ibcon#flushed, iclass 25, count 2 2006.173.16:28:42.02#ibcon#about to write, iclass 25, count 2 2006.173.16:28:42.02#ibcon#wrote, iclass 25, count 2 2006.173.16:28:42.02#ibcon#about to read 3, iclass 25, count 2 2006.173.16:28:42.05#ibcon#read 3, iclass 25, count 2 2006.173.16:28:42.05#ibcon#about to read 4, iclass 25, count 2 2006.173.16:28:42.05#ibcon#read 4, iclass 25, count 2 2006.173.16:28:42.05#ibcon#about to read 5, iclass 25, count 2 2006.173.16:28:42.05#ibcon#read 5, iclass 25, count 2 2006.173.16:28:42.05#ibcon#about to read 6, iclass 25, count 2 2006.173.16:28:42.05#ibcon#read 6, iclass 25, count 2 2006.173.16:28:42.05#ibcon#end of sib2, iclass 25, count 2 2006.173.16:28:42.05#ibcon#*after write, iclass 25, count 2 2006.173.16:28:42.05#ibcon#*before return 0, iclass 25, count 2 2006.173.16:28:42.05#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.16:28:42.05#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.16:28:42.05#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.16:28:42.05#ibcon#ireg 7 cls_cnt 0 2006.173.16:28:42.05#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.16:28:42.17#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.16:28:42.17#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.16:28:42.17#ibcon#enter wrdev, iclass 25, count 0 2006.173.16:28:42.17#ibcon#first serial, iclass 25, count 0 2006.173.16:28:42.17#ibcon#enter sib2, iclass 25, count 0 2006.173.16:28:42.17#ibcon#flushed, iclass 25, count 0 2006.173.16:28:42.17#ibcon#about to write, iclass 25, count 0 2006.173.16:28:42.17#ibcon#wrote, iclass 25, count 0 2006.173.16:28:42.17#ibcon#about to read 3, iclass 25, count 0 2006.173.16:28:42.19#ibcon#read 3, iclass 25, count 0 2006.173.16:28:42.19#ibcon#about to read 4, iclass 25, count 0 2006.173.16:28:42.19#ibcon#read 4, iclass 25, count 0 2006.173.16:28:42.19#ibcon#about to read 5, iclass 25, count 0 2006.173.16:28:42.19#ibcon#read 5, iclass 25, count 0 2006.173.16:28:42.19#ibcon#about to read 6, iclass 25, count 0 2006.173.16:28:42.19#ibcon#read 6, iclass 25, count 0 2006.173.16:28:42.19#ibcon#end of sib2, iclass 25, count 0 2006.173.16:28:42.19#ibcon#*mode == 0, iclass 25, count 0 2006.173.16:28:42.19#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.16:28:42.19#ibcon#[27=USB\r\n] 2006.173.16:28:42.19#ibcon#*before write, iclass 25, count 0 2006.173.16:28:42.19#ibcon#enter sib2, iclass 25, count 0 2006.173.16:28:42.19#ibcon#flushed, iclass 25, count 0 2006.173.16:28:42.19#ibcon#about to write, iclass 25, count 0 2006.173.16:28:42.19#ibcon#wrote, iclass 25, count 0 2006.173.16:28:42.19#ibcon#about to read 3, iclass 25, count 0 2006.173.16:28:42.22#ibcon#read 3, iclass 25, count 0 2006.173.16:28:42.22#ibcon#about to read 4, iclass 25, count 0 2006.173.16:28:42.22#ibcon#read 4, iclass 25, count 0 2006.173.16:28:42.22#ibcon#about to read 5, iclass 25, count 0 2006.173.16:28:42.22#ibcon#read 5, iclass 25, count 0 2006.173.16:28:42.22#ibcon#about to read 6, iclass 25, count 0 2006.173.16:28:42.22#ibcon#read 6, iclass 25, count 0 2006.173.16:28:42.22#ibcon#end of sib2, iclass 25, count 0 2006.173.16:28:42.22#ibcon#*after write, iclass 25, count 0 2006.173.16:28:42.22#ibcon#*before return 0, iclass 25, count 0 2006.173.16:28:42.22#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.16:28:42.22#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.16:28:42.22#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.16:28:42.22#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.16:28:42.22$vck44/vblo=5,709.99 2006.173.16:28:42.22#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.16:28:42.22#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.16:28:42.22#ibcon#ireg 17 cls_cnt 0 2006.173.16:28:42.22#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.16:28:42.22#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.16:28:42.22#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.16:28:42.22#ibcon#enter wrdev, iclass 27, count 0 2006.173.16:28:42.22#ibcon#first serial, iclass 27, count 0 2006.173.16:28:42.22#ibcon#enter sib2, iclass 27, count 0 2006.173.16:28:42.22#ibcon#flushed, iclass 27, count 0 2006.173.16:28:42.22#ibcon#about to write, iclass 27, count 0 2006.173.16:28:42.22#ibcon#wrote, iclass 27, count 0 2006.173.16:28:42.22#ibcon#about to read 3, iclass 27, count 0 2006.173.16:28:42.24#ibcon#read 3, iclass 27, count 0 2006.173.16:28:42.24#ibcon#about to read 4, iclass 27, count 0 2006.173.16:28:42.24#ibcon#read 4, iclass 27, count 0 2006.173.16:28:42.24#ibcon#about to read 5, iclass 27, count 0 2006.173.16:28:42.24#ibcon#read 5, iclass 27, count 0 2006.173.16:28:42.24#ibcon#about to read 6, iclass 27, count 0 2006.173.16:28:42.24#ibcon#read 6, iclass 27, count 0 2006.173.16:28:42.24#ibcon#end of sib2, iclass 27, count 0 2006.173.16:28:42.24#ibcon#*mode == 0, iclass 27, count 0 2006.173.16:28:42.24#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.16:28:42.24#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.16:28:42.24#ibcon#*before write, iclass 27, count 0 2006.173.16:28:42.24#ibcon#enter sib2, iclass 27, count 0 2006.173.16:28:42.24#ibcon#flushed, iclass 27, count 0 2006.173.16:28:42.24#ibcon#about to write, iclass 27, count 0 2006.173.16:28:42.24#ibcon#wrote, iclass 27, count 0 2006.173.16:28:42.24#ibcon#about to read 3, iclass 27, count 0 2006.173.16:28:42.28#ibcon#read 3, iclass 27, count 0 2006.173.16:28:42.28#ibcon#about to read 4, iclass 27, count 0 2006.173.16:28:42.28#ibcon#read 4, iclass 27, count 0 2006.173.16:28:42.28#ibcon#about to read 5, iclass 27, count 0 2006.173.16:28:42.28#ibcon#read 5, iclass 27, count 0 2006.173.16:28:42.28#ibcon#about to read 6, iclass 27, count 0 2006.173.16:28:42.28#ibcon#read 6, iclass 27, count 0 2006.173.16:28:42.28#ibcon#end of sib2, iclass 27, count 0 2006.173.16:28:42.28#ibcon#*after write, iclass 27, count 0 2006.173.16:28:42.28#ibcon#*before return 0, iclass 27, count 0 2006.173.16:28:42.28#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.16:28:42.28#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.16:28:42.28#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.16:28:42.28#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.16:28:42.28$vck44/vb=5,4 2006.173.16:28:42.28#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.16:28:42.28#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.16:28:42.28#ibcon#ireg 11 cls_cnt 2 2006.173.16:28:42.28#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.16:28:42.34#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.16:28:42.34#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.16:28:42.34#ibcon#enter wrdev, iclass 29, count 2 2006.173.16:28:42.34#ibcon#first serial, iclass 29, count 2 2006.173.16:28:42.34#ibcon#enter sib2, iclass 29, count 2 2006.173.16:28:42.34#ibcon#flushed, iclass 29, count 2 2006.173.16:28:42.34#ibcon#about to write, iclass 29, count 2 2006.173.16:28:42.34#ibcon#wrote, iclass 29, count 2 2006.173.16:28:42.34#ibcon#about to read 3, iclass 29, count 2 2006.173.16:28:42.36#ibcon#read 3, iclass 29, count 2 2006.173.16:28:42.36#ibcon#about to read 4, iclass 29, count 2 2006.173.16:28:42.36#ibcon#read 4, iclass 29, count 2 2006.173.16:28:42.36#ibcon#about to read 5, iclass 29, count 2 2006.173.16:28:42.36#ibcon#read 5, iclass 29, count 2 2006.173.16:28:42.36#ibcon#about to read 6, iclass 29, count 2 2006.173.16:28:42.36#ibcon#read 6, iclass 29, count 2 2006.173.16:28:42.36#ibcon#end of sib2, iclass 29, count 2 2006.173.16:28:42.36#ibcon#*mode == 0, iclass 29, count 2 2006.173.16:28:42.36#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.16:28:42.36#ibcon#[27=AT05-04\r\n] 2006.173.16:28:42.36#ibcon#*before write, iclass 29, count 2 2006.173.16:28:42.36#ibcon#enter sib2, iclass 29, count 2 2006.173.16:28:42.36#ibcon#flushed, iclass 29, count 2 2006.173.16:28:42.36#ibcon#about to write, iclass 29, count 2 2006.173.16:28:42.36#ibcon#wrote, iclass 29, count 2 2006.173.16:28:42.36#ibcon#about to read 3, iclass 29, count 2 2006.173.16:28:42.39#ibcon#read 3, iclass 29, count 2 2006.173.16:28:42.39#ibcon#about to read 4, iclass 29, count 2 2006.173.16:28:42.39#ibcon#read 4, iclass 29, count 2 2006.173.16:28:42.39#ibcon#about to read 5, iclass 29, count 2 2006.173.16:28:42.39#ibcon#read 5, iclass 29, count 2 2006.173.16:28:42.39#ibcon#about to read 6, iclass 29, count 2 2006.173.16:28:42.39#ibcon#read 6, iclass 29, count 2 2006.173.16:28:42.39#ibcon#end of sib2, iclass 29, count 2 2006.173.16:28:42.39#ibcon#*after write, iclass 29, count 2 2006.173.16:28:42.39#ibcon#*before return 0, iclass 29, count 2 2006.173.16:28:42.39#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.16:28:42.39#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.16:28:42.39#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.16:28:42.39#ibcon#ireg 7 cls_cnt 0 2006.173.16:28:42.39#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.16:28:42.51#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.16:28:42.51#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.16:28:42.51#ibcon#enter wrdev, iclass 29, count 0 2006.173.16:28:42.51#ibcon#first serial, iclass 29, count 0 2006.173.16:28:42.51#ibcon#enter sib2, iclass 29, count 0 2006.173.16:28:42.51#ibcon#flushed, iclass 29, count 0 2006.173.16:28:42.51#ibcon#about to write, iclass 29, count 0 2006.173.16:28:42.51#ibcon#wrote, iclass 29, count 0 2006.173.16:28:42.51#ibcon#about to read 3, iclass 29, count 0 2006.173.16:28:42.53#ibcon#read 3, iclass 29, count 0 2006.173.16:28:42.53#ibcon#about to read 4, iclass 29, count 0 2006.173.16:28:42.53#ibcon#read 4, iclass 29, count 0 2006.173.16:28:42.53#ibcon#about to read 5, iclass 29, count 0 2006.173.16:28:42.53#ibcon#read 5, iclass 29, count 0 2006.173.16:28:42.53#ibcon#about to read 6, iclass 29, count 0 2006.173.16:28:42.53#ibcon#read 6, iclass 29, count 0 2006.173.16:28:42.53#ibcon#end of sib2, iclass 29, count 0 2006.173.16:28:42.53#ibcon#*mode == 0, iclass 29, count 0 2006.173.16:28:42.53#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.16:28:42.53#ibcon#[27=USB\r\n] 2006.173.16:28:42.53#ibcon#*before write, iclass 29, count 0 2006.173.16:28:42.53#ibcon#enter sib2, iclass 29, count 0 2006.173.16:28:42.53#ibcon#flushed, iclass 29, count 0 2006.173.16:28:42.53#ibcon#about to write, iclass 29, count 0 2006.173.16:28:42.53#ibcon#wrote, iclass 29, count 0 2006.173.16:28:42.53#ibcon#about to read 3, iclass 29, count 0 2006.173.16:28:42.56#ibcon#read 3, iclass 29, count 0 2006.173.16:28:42.56#ibcon#about to read 4, iclass 29, count 0 2006.173.16:28:42.56#ibcon#read 4, iclass 29, count 0 2006.173.16:28:42.56#ibcon#about to read 5, iclass 29, count 0 2006.173.16:28:42.56#ibcon#read 5, iclass 29, count 0 2006.173.16:28:42.56#ibcon#about to read 6, iclass 29, count 0 2006.173.16:28:42.56#ibcon#read 6, iclass 29, count 0 2006.173.16:28:42.56#ibcon#end of sib2, iclass 29, count 0 2006.173.16:28:42.56#ibcon#*after write, iclass 29, count 0 2006.173.16:28:42.56#ibcon#*before return 0, iclass 29, count 0 2006.173.16:28:42.56#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.16:28:42.56#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.16:28:42.56#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.16:28:42.56#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.16:28:42.56$vck44/vblo=6,719.99 2006.173.16:28:42.56#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.16:28:42.56#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.16:28:42.56#ibcon#ireg 17 cls_cnt 0 2006.173.16:28:42.56#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.16:28:42.56#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.16:28:42.56#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.16:28:42.56#ibcon#enter wrdev, iclass 31, count 0 2006.173.16:28:42.56#ibcon#first serial, iclass 31, count 0 2006.173.16:28:42.56#ibcon#enter sib2, iclass 31, count 0 2006.173.16:28:42.56#ibcon#flushed, iclass 31, count 0 2006.173.16:28:42.56#ibcon#about to write, iclass 31, count 0 2006.173.16:28:42.56#ibcon#wrote, iclass 31, count 0 2006.173.16:28:42.56#ibcon#about to read 3, iclass 31, count 0 2006.173.16:28:42.58#ibcon#read 3, iclass 31, count 0 2006.173.16:28:42.58#ibcon#about to read 4, iclass 31, count 0 2006.173.16:28:42.58#ibcon#read 4, iclass 31, count 0 2006.173.16:28:42.58#ibcon#about to read 5, iclass 31, count 0 2006.173.16:28:42.58#ibcon#read 5, iclass 31, count 0 2006.173.16:28:42.58#ibcon#about to read 6, iclass 31, count 0 2006.173.16:28:42.58#ibcon#read 6, iclass 31, count 0 2006.173.16:28:42.58#ibcon#end of sib2, iclass 31, count 0 2006.173.16:28:42.58#ibcon#*mode == 0, iclass 31, count 0 2006.173.16:28:42.58#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.16:28:42.58#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.16:28:42.58#ibcon#*before write, iclass 31, count 0 2006.173.16:28:42.58#ibcon#enter sib2, iclass 31, count 0 2006.173.16:28:42.58#ibcon#flushed, iclass 31, count 0 2006.173.16:28:42.58#ibcon#about to write, iclass 31, count 0 2006.173.16:28:42.58#ibcon#wrote, iclass 31, count 0 2006.173.16:28:42.58#ibcon#about to read 3, iclass 31, count 0 2006.173.16:28:42.62#ibcon#read 3, iclass 31, count 0 2006.173.16:28:42.62#ibcon#about to read 4, iclass 31, count 0 2006.173.16:28:42.62#ibcon#read 4, iclass 31, count 0 2006.173.16:28:42.62#ibcon#about to read 5, iclass 31, count 0 2006.173.16:28:42.62#ibcon#read 5, iclass 31, count 0 2006.173.16:28:42.62#ibcon#about to read 6, iclass 31, count 0 2006.173.16:28:42.62#ibcon#read 6, iclass 31, count 0 2006.173.16:28:42.62#ibcon#end of sib2, iclass 31, count 0 2006.173.16:28:42.62#ibcon#*after write, iclass 31, count 0 2006.173.16:28:42.62#ibcon#*before return 0, iclass 31, count 0 2006.173.16:28:42.62#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.16:28:42.62#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.16:28:42.62#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.16:28:42.62#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.16:28:42.62$vck44/vb=6,4 2006.173.16:28:42.62#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.173.16:28:42.62#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.173.16:28:42.62#ibcon#ireg 11 cls_cnt 2 2006.173.16:28:42.62#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.16:28:42.68#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.16:28:42.68#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.16:28:42.68#ibcon#enter wrdev, iclass 33, count 2 2006.173.16:28:42.68#ibcon#first serial, iclass 33, count 2 2006.173.16:28:42.68#ibcon#enter sib2, iclass 33, count 2 2006.173.16:28:42.68#ibcon#flushed, iclass 33, count 2 2006.173.16:28:42.68#ibcon#about to write, iclass 33, count 2 2006.173.16:28:42.68#ibcon#wrote, iclass 33, count 2 2006.173.16:28:42.68#ibcon#about to read 3, iclass 33, count 2 2006.173.16:28:42.70#ibcon#read 3, iclass 33, count 2 2006.173.16:28:42.70#ibcon#about to read 4, iclass 33, count 2 2006.173.16:28:42.70#ibcon#read 4, iclass 33, count 2 2006.173.16:28:42.70#ibcon#about to read 5, iclass 33, count 2 2006.173.16:28:42.70#ibcon#read 5, iclass 33, count 2 2006.173.16:28:42.70#ibcon#about to read 6, iclass 33, count 2 2006.173.16:28:42.70#ibcon#read 6, iclass 33, count 2 2006.173.16:28:42.70#ibcon#end of sib2, iclass 33, count 2 2006.173.16:28:42.70#ibcon#*mode == 0, iclass 33, count 2 2006.173.16:28:42.70#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.173.16:28:42.70#ibcon#[27=AT06-04\r\n] 2006.173.16:28:42.70#ibcon#*before write, iclass 33, count 2 2006.173.16:28:42.70#ibcon#enter sib2, iclass 33, count 2 2006.173.16:28:42.70#ibcon#flushed, iclass 33, count 2 2006.173.16:28:42.70#ibcon#about to write, iclass 33, count 2 2006.173.16:28:42.70#ibcon#wrote, iclass 33, count 2 2006.173.16:28:42.70#ibcon#about to read 3, iclass 33, count 2 2006.173.16:28:42.73#ibcon#read 3, iclass 33, count 2 2006.173.16:28:42.73#ibcon#about to read 4, iclass 33, count 2 2006.173.16:28:42.73#ibcon#read 4, iclass 33, count 2 2006.173.16:28:42.73#ibcon#about to read 5, iclass 33, count 2 2006.173.16:28:42.73#ibcon#read 5, iclass 33, count 2 2006.173.16:28:42.73#ibcon#about to read 6, iclass 33, count 2 2006.173.16:28:42.73#ibcon#read 6, iclass 33, count 2 2006.173.16:28:42.73#ibcon#end of sib2, iclass 33, count 2 2006.173.16:28:42.73#ibcon#*after write, iclass 33, count 2 2006.173.16:28:42.73#ibcon#*before return 0, iclass 33, count 2 2006.173.16:28:42.73#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.16:28:42.73#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.173.16:28:42.73#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.173.16:28:42.73#ibcon#ireg 7 cls_cnt 0 2006.173.16:28:42.73#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.16:28:42.85#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.16:28:42.85#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.16:28:42.85#ibcon#enter wrdev, iclass 33, count 0 2006.173.16:28:42.85#ibcon#first serial, iclass 33, count 0 2006.173.16:28:42.85#ibcon#enter sib2, iclass 33, count 0 2006.173.16:28:42.85#ibcon#flushed, iclass 33, count 0 2006.173.16:28:42.85#ibcon#about to write, iclass 33, count 0 2006.173.16:28:42.85#ibcon#wrote, iclass 33, count 0 2006.173.16:28:42.85#ibcon#about to read 3, iclass 33, count 0 2006.173.16:28:42.87#ibcon#read 3, iclass 33, count 0 2006.173.16:28:42.87#ibcon#about to read 4, iclass 33, count 0 2006.173.16:28:42.87#ibcon#read 4, iclass 33, count 0 2006.173.16:28:42.87#ibcon#about to read 5, iclass 33, count 0 2006.173.16:28:42.87#ibcon#read 5, iclass 33, count 0 2006.173.16:28:42.87#ibcon#about to read 6, iclass 33, count 0 2006.173.16:28:42.87#ibcon#read 6, iclass 33, count 0 2006.173.16:28:42.87#ibcon#end of sib2, iclass 33, count 0 2006.173.16:28:42.87#ibcon#*mode == 0, iclass 33, count 0 2006.173.16:28:42.87#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.16:28:42.87#ibcon#[27=USB\r\n] 2006.173.16:28:42.87#ibcon#*before write, iclass 33, count 0 2006.173.16:28:42.87#ibcon#enter sib2, iclass 33, count 0 2006.173.16:28:42.87#ibcon#flushed, iclass 33, count 0 2006.173.16:28:42.87#ibcon#about to write, iclass 33, count 0 2006.173.16:28:42.87#ibcon#wrote, iclass 33, count 0 2006.173.16:28:42.87#ibcon#about to read 3, iclass 33, count 0 2006.173.16:28:42.90#ibcon#read 3, iclass 33, count 0 2006.173.16:28:42.90#ibcon#about to read 4, iclass 33, count 0 2006.173.16:28:42.90#ibcon#read 4, iclass 33, count 0 2006.173.16:28:42.90#ibcon#about to read 5, iclass 33, count 0 2006.173.16:28:42.90#ibcon#read 5, iclass 33, count 0 2006.173.16:28:42.90#ibcon#about to read 6, iclass 33, count 0 2006.173.16:28:42.90#ibcon#read 6, iclass 33, count 0 2006.173.16:28:42.90#ibcon#end of sib2, iclass 33, count 0 2006.173.16:28:42.90#ibcon#*after write, iclass 33, count 0 2006.173.16:28:42.90#ibcon#*before return 0, iclass 33, count 0 2006.173.16:28:42.90#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.16:28:42.90#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.173.16:28:42.90#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.16:28:42.90#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.16:28:42.90$vck44/vblo=7,734.99 2006.173.16:28:42.90#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.16:28:42.90#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.16:28:42.90#ibcon#ireg 17 cls_cnt 0 2006.173.16:28:42.90#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.16:28:42.90#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.16:28:42.90#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.16:28:42.90#ibcon#enter wrdev, iclass 35, count 0 2006.173.16:28:42.90#ibcon#first serial, iclass 35, count 0 2006.173.16:28:42.90#ibcon#enter sib2, iclass 35, count 0 2006.173.16:28:42.90#ibcon#flushed, iclass 35, count 0 2006.173.16:28:42.90#ibcon#about to write, iclass 35, count 0 2006.173.16:28:42.90#ibcon#wrote, iclass 35, count 0 2006.173.16:28:42.90#ibcon#about to read 3, iclass 35, count 0 2006.173.16:28:42.92#ibcon#read 3, iclass 35, count 0 2006.173.16:28:42.92#ibcon#about to read 4, iclass 35, count 0 2006.173.16:28:42.92#ibcon#read 4, iclass 35, count 0 2006.173.16:28:42.92#ibcon#about to read 5, iclass 35, count 0 2006.173.16:28:42.92#ibcon#read 5, iclass 35, count 0 2006.173.16:28:42.92#ibcon#about to read 6, iclass 35, count 0 2006.173.16:28:42.92#ibcon#read 6, iclass 35, count 0 2006.173.16:28:42.92#ibcon#end of sib2, iclass 35, count 0 2006.173.16:28:42.92#ibcon#*mode == 0, iclass 35, count 0 2006.173.16:28:42.92#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.16:28:42.92#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.16:28:42.92#ibcon#*before write, iclass 35, count 0 2006.173.16:28:42.92#ibcon#enter sib2, iclass 35, count 0 2006.173.16:28:42.92#ibcon#flushed, iclass 35, count 0 2006.173.16:28:42.92#ibcon#about to write, iclass 35, count 0 2006.173.16:28:42.92#ibcon#wrote, iclass 35, count 0 2006.173.16:28:42.92#ibcon#about to read 3, iclass 35, count 0 2006.173.16:28:42.96#ibcon#read 3, iclass 35, count 0 2006.173.16:28:42.96#ibcon#about to read 4, iclass 35, count 0 2006.173.16:28:42.96#ibcon#read 4, iclass 35, count 0 2006.173.16:28:42.96#ibcon#about to read 5, iclass 35, count 0 2006.173.16:28:42.96#ibcon#read 5, iclass 35, count 0 2006.173.16:28:42.96#ibcon#about to read 6, iclass 35, count 0 2006.173.16:28:42.96#ibcon#read 6, iclass 35, count 0 2006.173.16:28:42.96#ibcon#end of sib2, iclass 35, count 0 2006.173.16:28:42.96#ibcon#*after write, iclass 35, count 0 2006.173.16:28:42.96#ibcon#*before return 0, iclass 35, count 0 2006.173.16:28:42.96#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.16:28:42.96#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.16:28:42.96#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.16:28:42.96#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.16:28:42.96$vck44/vb=7,4 2006.173.16:28:42.96#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.173.16:28:42.96#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.173.16:28:42.96#ibcon#ireg 11 cls_cnt 2 2006.173.16:28:42.96#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.16:28:43.02#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.16:28:43.02#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.16:28:43.02#ibcon#enter wrdev, iclass 37, count 2 2006.173.16:28:43.02#ibcon#first serial, iclass 37, count 2 2006.173.16:28:43.02#ibcon#enter sib2, iclass 37, count 2 2006.173.16:28:43.02#ibcon#flushed, iclass 37, count 2 2006.173.16:28:43.02#ibcon#about to write, iclass 37, count 2 2006.173.16:28:43.02#ibcon#wrote, iclass 37, count 2 2006.173.16:28:43.02#ibcon#about to read 3, iclass 37, count 2 2006.173.16:28:43.04#ibcon#read 3, iclass 37, count 2 2006.173.16:28:43.04#ibcon#about to read 4, iclass 37, count 2 2006.173.16:28:43.04#ibcon#read 4, iclass 37, count 2 2006.173.16:28:43.04#ibcon#about to read 5, iclass 37, count 2 2006.173.16:28:43.04#ibcon#read 5, iclass 37, count 2 2006.173.16:28:43.04#ibcon#about to read 6, iclass 37, count 2 2006.173.16:28:43.04#ibcon#read 6, iclass 37, count 2 2006.173.16:28:43.04#ibcon#end of sib2, iclass 37, count 2 2006.173.16:28:43.04#ibcon#*mode == 0, iclass 37, count 2 2006.173.16:28:43.04#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.173.16:28:43.04#ibcon#[27=AT07-04\r\n] 2006.173.16:28:43.04#ibcon#*before write, iclass 37, count 2 2006.173.16:28:43.04#ibcon#enter sib2, iclass 37, count 2 2006.173.16:28:43.04#ibcon#flushed, iclass 37, count 2 2006.173.16:28:43.04#ibcon#about to write, iclass 37, count 2 2006.173.16:28:43.04#ibcon#wrote, iclass 37, count 2 2006.173.16:28:43.04#ibcon#about to read 3, iclass 37, count 2 2006.173.16:28:43.07#ibcon#read 3, iclass 37, count 2 2006.173.16:28:43.07#ibcon#about to read 4, iclass 37, count 2 2006.173.16:28:43.07#ibcon#read 4, iclass 37, count 2 2006.173.16:28:43.07#ibcon#about to read 5, iclass 37, count 2 2006.173.16:28:43.07#ibcon#read 5, iclass 37, count 2 2006.173.16:28:43.07#ibcon#about to read 6, iclass 37, count 2 2006.173.16:28:43.07#ibcon#read 6, iclass 37, count 2 2006.173.16:28:43.07#ibcon#end of sib2, iclass 37, count 2 2006.173.16:28:43.07#ibcon#*after write, iclass 37, count 2 2006.173.16:28:43.07#ibcon#*before return 0, iclass 37, count 2 2006.173.16:28:43.07#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.16:28:43.07#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.173.16:28:43.07#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.173.16:28:43.07#ibcon#ireg 7 cls_cnt 0 2006.173.16:28:43.07#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.16:28:43.19#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.16:28:43.19#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.16:28:43.19#ibcon#enter wrdev, iclass 37, count 0 2006.173.16:28:43.19#ibcon#first serial, iclass 37, count 0 2006.173.16:28:43.19#ibcon#enter sib2, iclass 37, count 0 2006.173.16:28:43.19#ibcon#flushed, iclass 37, count 0 2006.173.16:28:43.19#ibcon#about to write, iclass 37, count 0 2006.173.16:28:43.19#ibcon#wrote, iclass 37, count 0 2006.173.16:28:43.19#ibcon#about to read 3, iclass 37, count 0 2006.173.16:28:43.21#ibcon#read 3, iclass 37, count 0 2006.173.16:28:43.21#ibcon#about to read 4, iclass 37, count 0 2006.173.16:28:43.21#ibcon#read 4, iclass 37, count 0 2006.173.16:28:43.21#ibcon#about to read 5, iclass 37, count 0 2006.173.16:28:43.21#ibcon#read 5, iclass 37, count 0 2006.173.16:28:43.21#ibcon#about to read 6, iclass 37, count 0 2006.173.16:28:43.21#ibcon#read 6, iclass 37, count 0 2006.173.16:28:43.21#ibcon#end of sib2, iclass 37, count 0 2006.173.16:28:43.21#ibcon#*mode == 0, iclass 37, count 0 2006.173.16:28:43.21#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.16:28:43.21#ibcon#[27=USB\r\n] 2006.173.16:28:43.21#ibcon#*before write, iclass 37, count 0 2006.173.16:28:43.21#ibcon#enter sib2, iclass 37, count 0 2006.173.16:28:43.21#ibcon#flushed, iclass 37, count 0 2006.173.16:28:43.21#ibcon#about to write, iclass 37, count 0 2006.173.16:28:43.21#ibcon#wrote, iclass 37, count 0 2006.173.16:28:43.21#ibcon#about to read 3, iclass 37, count 0 2006.173.16:28:43.24#ibcon#read 3, iclass 37, count 0 2006.173.16:28:43.24#ibcon#about to read 4, iclass 37, count 0 2006.173.16:28:43.24#ibcon#read 4, iclass 37, count 0 2006.173.16:28:43.24#ibcon#about to read 5, iclass 37, count 0 2006.173.16:28:43.24#ibcon#read 5, iclass 37, count 0 2006.173.16:28:43.24#ibcon#about to read 6, iclass 37, count 0 2006.173.16:28:43.24#ibcon#read 6, iclass 37, count 0 2006.173.16:28:43.24#ibcon#end of sib2, iclass 37, count 0 2006.173.16:28:43.24#ibcon#*after write, iclass 37, count 0 2006.173.16:28:43.24#ibcon#*before return 0, iclass 37, count 0 2006.173.16:28:43.24#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.16:28:43.24#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.173.16:28:43.24#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.16:28:43.24#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.16:28:43.24$vck44/vblo=8,744.99 2006.173.16:28:43.24#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.16:28:43.24#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.16:28:43.24#ibcon#ireg 17 cls_cnt 0 2006.173.16:28:43.24#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.16:28:43.24#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.16:28:43.24#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.16:28:43.24#ibcon#enter wrdev, iclass 39, count 0 2006.173.16:28:43.24#ibcon#first serial, iclass 39, count 0 2006.173.16:28:43.24#ibcon#enter sib2, iclass 39, count 0 2006.173.16:28:43.24#ibcon#flushed, iclass 39, count 0 2006.173.16:28:43.24#ibcon#about to write, iclass 39, count 0 2006.173.16:28:43.24#ibcon#wrote, iclass 39, count 0 2006.173.16:28:43.24#ibcon#about to read 3, iclass 39, count 0 2006.173.16:28:43.26#ibcon#read 3, iclass 39, count 0 2006.173.16:28:43.26#ibcon#about to read 4, iclass 39, count 0 2006.173.16:28:43.26#ibcon#read 4, iclass 39, count 0 2006.173.16:28:43.26#ibcon#about to read 5, iclass 39, count 0 2006.173.16:28:43.26#ibcon#read 5, iclass 39, count 0 2006.173.16:28:43.26#ibcon#about to read 6, iclass 39, count 0 2006.173.16:28:43.26#ibcon#read 6, iclass 39, count 0 2006.173.16:28:43.26#ibcon#end of sib2, iclass 39, count 0 2006.173.16:28:43.26#ibcon#*mode == 0, iclass 39, count 0 2006.173.16:28:43.26#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.16:28:43.26#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.16:28:43.26#ibcon#*before write, iclass 39, count 0 2006.173.16:28:43.26#ibcon#enter sib2, iclass 39, count 0 2006.173.16:28:43.26#ibcon#flushed, iclass 39, count 0 2006.173.16:28:43.26#ibcon#about to write, iclass 39, count 0 2006.173.16:28:43.26#ibcon#wrote, iclass 39, count 0 2006.173.16:28:43.26#ibcon#about to read 3, iclass 39, count 0 2006.173.16:28:43.30#ibcon#read 3, iclass 39, count 0 2006.173.16:28:43.30#ibcon#about to read 4, iclass 39, count 0 2006.173.16:28:43.30#ibcon#read 4, iclass 39, count 0 2006.173.16:28:43.30#ibcon#about to read 5, iclass 39, count 0 2006.173.16:28:43.30#ibcon#read 5, iclass 39, count 0 2006.173.16:28:43.30#ibcon#about to read 6, iclass 39, count 0 2006.173.16:28:43.30#ibcon#read 6, iclass 39, count 0 2006.173.16:28:43.30#ibcon#end of sib2, iclass 39, count 0 2006.173.16:28:43.30#ibcon#*after write, iclass 39, count 0 2006.173.16:28:43.30#ibcon#*before return 0, iclass 39, count 0 2006.173.16:28:43.30#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.16:28:43.30#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.16:28:43.30#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.16:28:43.30#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.16:28:43.30$vck44/vb=8,4 2006.173.16:28:43.30#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.16:28:43.30#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.16:28:43.30#ibcon#ireg 11 cls_cnt 2 2006.173.16:28:43.30#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.16:28:43.36#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.16:28:43.36#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.16:28:43.36#ibcon#enter wrdev, iclass 3, count 2 2006.173.16:28:43.36#ibcon#first serial, iclass 3, count 2 2006.173.16:28:43.36#ibcon#enter sib2, iclass 3, count 2 2006.173.16:28:43.36#ibcon#flushed, iclass 3, count 2 2006.173.16:28:43.36#ibcon#about to write, iclass 3, count 2 2006.173.16:28:43.36#ibcon#wrote, iclass 3, count 2 2006.173.16:28:43.36#ibcon#about to read 3, iclass 3, count 2 2006.173.16:28:43.38#ibcon#read 3, iclass 3, count 2 2006.173.16:28:43.38#ibcon#about to read 4, iclass 3, count 2 2006.173.16:28:43.38#ibcon#read 4, iclass 3, count 2 2006.173.16:28:43.38#ibcon#about to read 5, iclass 3, count 2 2006.173.16:28:43.38#ibcon#read 5, iclass 3, count 2 2006.173.16:28:43.38#ibcon#about to read 6, iclass 3, count 2 2006.173.16:28:43.38#ibcon#read 6, iclass 3, count 2 2006.173.16:28:43.38#ibcon#end of sib2, iclass 3, count 2 2006.173.16:28:43.38#ibcon#*mode == 0, iclass 3, count 2 2006.173.16:28:43.38#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.16:28:43.38#ibcon#[27=AT08-04\r\n] 2006.173.16:28:43.38#ibcon#*before write, iclass 3, count 2 2006.173.16:28:43.38#ibcon#enter sib2, iclass 3, count 2 2006.173.16:28:43.38#ibcon#flushed, iclass 3, count 2 2006.173.16:28:43.38#ibcon#about to write, iclass 3, count 2 2006.173.16:28:43.38#ibcon#wrote, iclass 3, count 2 2006.173.16:28:43.38#ibcon#about to read 3, iclass 3, count 2 2006.173.16:28:43.41#ibcon#read 3, iclass 3, count 2 2006.173.16:28:43.41#ibcon#about to read 4, iclass 3, count 2 2006.173.16:28:43.41#ibcon#read 4, iclass 3, count 2 2006.173.16:28:43.41#ibcon#about to read 5, iclass 3, count 2 2006.173.16:28:43.41#ibcon#read 5, iclass 3, count 2 2006.173.16:28:43.41#ibcon#about to read 6, iclass 3, count 2 2006.173.16:28:43.41#ibcon#read 6, iclass 3, count 2 2006.173.16:28:43.41#ibcon#end of sib2, iclass 3, count 2 2006.173.16:28:43.41#ibcon#*after write, iclass 3, count 2 2006.173.16:28:43.41#ibcon#*before return 0, iclass 3, count 2 2006.173.16:28:43.41#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.16:28:43.41#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.16:28:43.41#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.16:28:43.41#ibcon#ireg 7 cls_cnt 0 2006.173.16:28:43.41#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.16:28:43.53#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.16:28:43.53#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.16:28:43.53#ibcon#enter wrdev, iclass 3, count 0 2006.173.16:28:43.53#ibcon#first serial, iclass 3, count 0 2006.173.16:28:43.53#ibcon#enter sib2, iclass 3, count 0 2006.173.16:28:43.53#ibcon#flushed, iclass 3, count 0 2006.173.16:28:43.53#ibcon#about to write, iclass 3, count 0 2006.173.16:28:43.53#ibcon#wrote, iclass 3, count 0 2006.173.16:28:43.53#ibcon#about to read 3, iclass 3, count 0 2006.173.16:28:43.55#ibcon#read 3, iclass 3, count 0 2006.173.16:28:43.55#ibcon#about to read 4, iclass 3, count 0 2006.173.16:28:43.55#ibcon#read 4, iclass 3, count 0 2006.173.16:28:43.55#ibcon#about to read 5, iclass 3, count 0 2006.173.16:28:43.55#ibcon#read 5, iclass 3, count 0 2006.173.16:28:43.55#ibcon#about to read 6, iclass 3, count 0 2006.173.16:28:43.55#ibcon#read 6, iclass 3, count 0 2006.173.16:28:43.55#ibcon#end of sib2, iclass 3, count 0 2006.173.16:28:43.55#ibcon#*mode == 0, iclass 3, count 0 2006.173.16:28:43.55#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.16:28:43.55#ibcon#[27=USB\r\n] 2006.173.16:28:43.55#ibcon#*before write, iclass 3, count 0 2006.173.16:28:43.55#ibcon#enter sib2, iclass 3, count 0 2006.173.16:28:43.55#ibcon#flushed, iclass 3, count 0 2006.173.16:28:43.55#ibcon#about to write, iclass 3, count 0 2006.173.16:28:43.55#ibcon#wrote, iclass 3, count 0 2006.173.16:28:43.55#ibcon#about to read 3, iclass 3, count 0 2006.173.16:28:43.58#ibcon#read 3, iclass 3, count 0 2006.173.16:28:43.58#ibcon#about to read 4, iclass 3, count 0 2006.173.16:28:43.58#ibcon#read 4, iclass 3, count 0 2006.173.16:28:43.58#ibcon#about to read 5, iclass 3, count 0 2006.173.16:28:43.58#ibcon#read 5, iclass 3, count 0 2006.173.16:28:43.58#ibcon#about to read 6, iclass 3, count 0 2006.173.16:28:43.58#ibcon#read 6, iclass 3, count 0 2006.173.16:28:43.58#ibcon#end of sib2, iclass 3, count 0 2006.173.16:28:43.58#ibcon#*after write, iclass 3, count 0 2006.173.16:28:43.58#ibcon#*before return 0, iclass 3, count 0 2006.173.16:28:43.58#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.16:28:43.58#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.16:28:43.58#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.16:28:43.58#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.16:28:43.58$vck44/vabw=wide 2006.173.16:28:43.58#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.16:28:43.58#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.16:28:43.58#ibcon#ireg 8 cls_cnt 0 2006.173.16:28:43.58#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.16:28:43.58#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.16:28:43.58#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.16:28:43.58#ibcon#enter wrdev, iclass 5, count 0 2006.173.16:28:43.58#ibcon#first serial, iclass 5, count 0 2006.173.16:28:43.58#ibcon#enter sib2, iclass 5, count 0 2006.173.16:28:43.58#ibcon#flushed, iclass 5, count 0 2006.173.16:28:43.58#ibcon#about to write, iclass 5, count 0 2006.173.16:28:43.58#ibcon#wrote, iclass 5, count 0 2006.173.16:28:43.58#ibcon#about to read 3, iclass 5, count 0 2006.173.16:28:43.60#ibcon#read 3, iclass 5, count 0 2006.173.16:28:43.60#ibcon#about to read 4, iclass 5, count 0 2006.173.16:28:43.60#ibcon#read 4, iclass 5, count 0 2006.173.16:28:43.60#ibcon#about to read 5, iclass 5, count 0 2006.173.16:28:43.60#ibcon#read 5, iclass 5, count 0 2006.173.16:28:43.60#ibcon#about to read 6, iclass 5, count 0 2006.173.16:28:43.60#ibcon#read 6, iclass 5, count 0 2006.173.16:28:43.60#ibcon#end of sib2, iclass 5, count 0 2006.173.16:28:43.60#ibcon#*mode == 0, iclass 5, count 0 2006.173.16:28:43.60#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.16:28:43.60#ibcon#[25=BW32\r\n] 2006.173.16:28:43.60#ibcon#*before write, iclass 5, count 0 2006.173.16:28:43.60#ibcon#enter sib2, iclass 5, count 0 2006.173.16:28:43.60#ibcon#flushed, iclass 5, count 0 2006.173.16:28:43.60#ibcon#about to write, iclass 5, count 0 2006.173.16:28:43.60#ibcon#wrote, iclass 5, count 0 2006.173.16:28:43.60#ibcon#about to read 3, iclass 5, count 0 2006.173.16:28:43.63#ibcon#read 3, iclass 5, count 0 2006.173.16:28:43.63#ibcon#about to read 4, iclass 5, count 0 2006.173.16:28:43.63#ibcon#read 4, iclass 5, count 0 2006.173.16:28:43.63#ibcon#about to read 5, iclass 5, count 0 2006.173.16:28:43.63#ibcon#read 5, iclass 5, count 0 2006.173.16:28:43.63#ibcon#about to read 6, iclass 5, count 0 2006.173.16:28:43.63#ibcon#read 6, iclass 5, count 0 2006.173.16:28:43.63#ibcon#end of sib2, iclass 5, count 0 2006.173.16:28:43.63#ibcon#*after write, iclass 5, count 0 2006.173.16:28:43.63#ibcon#*before return 0, iclass 5, count 0 2006.173.16:28:43.63#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.16:28:43.63#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.16:28:43.63#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.16:28:43.63#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.16:28:43.63$vck44/vbbw=wide 2006.173.16:28:43.63#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.16:28:43.63#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.16:28:43.63#ibcon#ireg 8 cls_cnt 0 2006.173.16:28:43.63#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.16:28:43.70#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.16:28:43.70#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.16:28:43.70#ibcon#enter wrdev, iclass 7, count 0 2006.173.16:28:43.70#ibcon#first serial, iclass 7, count 0 2006.173.16:28:43.70#ibcon#enter sib2, iclass 7, count 0 2006.173.16:28:43.70#ibcon#flushed, iclass 7, count 0 2006.173.16:28:43.70#ibcon#about to write, iclass 7, count 0 2006.173.16:28:43.70#ibcon#wrote, iclass 7, count 0 2006.173.16:28:43.70#ibcon#about to read 3, iclass 7, count 0 2006.173.16:28:43.72#ibcon#read 3, iclass 7, count 0 2006.173.16:28:43.72#ibcon#about to read 4, iclass 7, count 0 2006.173.16:28:43.72#ibcon#read 4, iclass 7, count 0 2006.173.16:28:43.72#ibcon#about to read 5, iclass 7, count 0 2006.173.16:28:43.72#ibcon#read 5, iclass 7, count 0 2006.173.16:28:43.72#ibcon#about to read 6, iclass 7, count 0 2006.173.16:28:43.72#ibcon#read 6, iclass 7, count 0 2006.173.16:28:43.72#ibcon#end of sib2, iclass 7, count 0 2006.173.16:28:43.72#ibcon#*mode == 0, iclass 7, count 0 2006.173.16:28:43.72#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.16:28:43.72#ibcon#[27=BW32\r\n] 2006.173.16:28:43.72#ibcon#*before write, iclass 7, count 0 2006.173.16:28:43.72#ibcon#enter sib2, iclass 7, count 0 2006.173.16:28:43.72#ibcon#flushed, iclass 7, count 0 2006.173.16:28:43.72#ibcon#about to write, iclass 7, count 0 2006.173.16:28:43.72#ibcon#wrote, iclass 7, count 0 2006.173.16:28:43.72#ibcon#about to read 3, iclass 7, count 0 2006.173.16:28:43.75#ibcon#read 3, iclass 7, count 0 2006.173.16:28:43.75#ibcon#about to read 4, iclass 7, count 0 2006.173.16:28:43.75#ibcon#read 4, iclass 7, count 0 2006.173.16:28:43.75#ibcon#about to read 5, iclass 7, count 0 2006.173.16:28:43.75#ibcon#read 5, iclass 7, count 0 2006.173.16:28:43.75#ibcon#about to read 6, iclass 7, count 0 2006.173.16:28:43.75#ibcon#read 6, iclass 7, count 0 2006.173.16:28:43.75#ibcon#end of sib2, iclass 7, count 0 2006.173.16:28:43.75#ibcon#*after write, iclass 7, count 0 2006.173.16:28:43.75#ibcon#*before return 0, iclass 7, count 0 2006.173.16:28:43.75#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.16:28:43.75#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.16:28:43.75#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.16:28:43.75#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.16:28:43.75$setupk4/ifdk4 2006.173.16:28:43.75$ifdk4/lo= 2006.173.16:28:43.75$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.16:28:43.75$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.16:28:43.75$ifdk4/patch= 2006.173.16:28:43.75$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.16:28:43.75$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.16:28:43.75$setupk4/!*+20s 2006.173.16:28:44.44#abcon#<5=/14 0.8 2.4 20.451001002.6\r\n> 2006.173.16:28:44.46#abcon#{5=INTERFACE CLEAR} 2006.173.16:28:44.52#abcon#[5=S1D000X0/0*\r\n] 2006.173.16:28:48.14#trakl#Source acquired 2006.173.16:28:48.14#flagr#flagr/antenna,acquired 2006.173.16:28:54.61#abcon#<5=/14 0.8 2.4 20.451001002.6\r\n> 2006.173.16:28:54.63#abcon#{5=INTERFACE CLEAR} 2006.173.16:28:54.69#abcon#[5=S1D000X0/0*\r\n] 2006.173.16:28:58.25$setupk4/"tpicd 2006.173.16:28:58.25$setupk4/echo=off 2006.173.16:28:58.25$setupk4/xlog=off 2006.173.16:28:58.25:!2006.173.16:32:43 2006.173.16:32:43.00:preob 2006.173.16:32:43.14/onsource/TRACKING 2006.173.16:32:43.14:!2006.173.16:32:53 2006.173.16:32:53.00:"tape 2006.173.16:32:53.00:"st=record 2006.173.16:32:53.00:data_valid=on 2006.173.16:32:53.00:midob 2006.173.16:32:54.13/onsource/TRACKING 2006.173.16:32:54.13/wx/20.43,1002.5,100 2006.173.16:32:54.28/cable/+6.5111E-03 2006.173.16:32:55.37/va/01,07,usb,yes,36,38 2006.173.16:32:55.37/va/02,06,usb,yes,35,36 2006.173.16:32:55.37/va/03,05,usb,yes,45,47 2006.173.16:32:55.37/va/04,06,usb,yes,36,38 2006.173.16:32:55.37/va/05,04,usb,yes,28,29 2006.173.16:32:55.37/va/06,03,usb,yes,40,40 2006.173.16:32:55.37/va/07,04,usb,yes,32,33 2006.173.16:32:55.37/va/08,04,usb,yes,27,33 2006.173.16:32:55.60/valo/01,524.99,yes,locked 2006.173.16:32:55.60/valo/02,534.99,yes,locked 2006.173.16:32:55.60/valo/03,564.99,yes,locked 2006.173.16:32:55.60/valo/04,624.99,yes,locked 2006.173.16:32:55.60/valo/05,734.99,yes,locked 2006.173.16:32:55.60/valo/06,814.99,yes,locked 2006.173.16:32:55.60/valo/07,864.99,yes,locked 2006.173.16:32:55.60/valo/08,884.99,yes,locked 2006.173.16:32:56.69/vb/01,04,usb,yes,29,27 2006.173.16:32:56.69/vb/02,04,usb,yes,32,31 2006.173.16:32:56.69/vb/03,04,usb,yes,29,32 2006.173.16:32:56.69/vb/04,04,usb,yes,33,32 2006.173.16:32:56.69/vb/05,04,usb,yes,26,28 2006.173.16:32:56.69/vb/06,04,usb,yes,30,27 2006.173.16:32:56.69/vb/07,04,usb,yes,30,30 2006.173.16:32:56.69/vb/08,04,usb,yes,27,31 2006.173.16:32:56.92/vblo/01,629.99,yes,locked 2006.173.16:32:56.92/vblo/02,634.99,yes,locked 2006.173.16:32:56.92/vblo/03,649.99,yes,locked 2006.173.16:32:56.92/vblo/04,679.99,yes,locked 2006.173.16:32:56.92/vblo/05,709.99,yes,locked 2006.173.16:32:56.92/vblo/06,719.99,yes,locked 2006.173.16:32:56.92/vblo/07,734.99,yes,locked 2006.173.16:32:56.92/vblo/08,744.99,yes,locked 2006.173.16:32:57.07/vabw/8 2006.173.16:32:57.22/vbbw/8 2006.173.16:32:57.31/xfe/off,on,15.2 2006.173.16:32:57.69/ifatt/23,28,28,28 2006.173.16:32:58.08/fmout-gps/S +3.96E-07 2006.173.16:32:58.12:!2006.173.16:34:03 2006.173.16:34:03.00:data_valid=off 2006.173.16:34:03.00:"et 2006.173.16:34:03.00:!+3s 2006.173.16:34:06.01:"tape 2006.173.16:34:06.01:postob 2006.173.16:34:06.13/cable/+6.5131E-03 2006.173.16:34:06.13/wx/20.41,1002.5,100 2006.173.16:34:07.08/fmout-gps/S +3.95E-07 2006.173.16:34:07.08:scan_name=173-1637,jd0606,120 2006.173.16:34:07.08:source=2201+315,220314.98,314538.3,2000.0,ccw 2006.173.16:34:08.13#flagr#flagr/antenna,new-source 2006.173.16:34:08.13:checkk5 2006.173.16:34:08.49/chk_autoobs//k5ts1/ autoobs is running! 2006.173.16:34:08.88/chk_autoobs//k5ts2/ autoobs is running! 2006.173.16:34:09.29/chk_autoobs//k5ts3/ autoobs is running! 2006.173.16:34:09.70/chk_autoobs//k5ts4/ autoobs is running! 2006.173.16:34:10.11/chk_obsdata//k5ts1/T1731632??a.dat file size is correct (nominal:280MB, actual:280MB). 2006.173.16:34:10.52/chk_obsdata//k5ts2/T1731632??b.dat file size is correct (nominal:280MB, actual:280MB). 2006.173.16:34:10.92/chk_obsdata//k5ts3/T1731632??c.dat file size is correct (nominal:280MB, actual:280MB). 2006.173.16:34:11.33/chk_obsdata//k5ts4/T1731632??d.dat file size is correct (nominal:280MB, actual:280MB). 2006.173.16:34:12.06/k5log//k5ts1_log_newline 2006.173.16:34:12.77/k5log//k5ts2_log_newline 2006.173.16:34:13.49/k5log//k5ts3_log_newline 2006.173.16:34:14.19/k5log//k5ts4_log_newline 2006.173.16:34:14.22/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.16:34:14.22:setupk4=1 2006.173.16:34:14.22$setupk4/echo=on 2006.173.16:34:14.22$setupk4/pcalon 2006.173.16:34:14.22$pcalon/"no phase cal control is implemented here 2006.173.16:34:14.22$setupk4/"tpicd=stop 2006.173.16:34:14.22$setupk4/"rec=synch_on 2006.173.16:34:14.22$setupk4/"rec_mode=128 2006.173.16:34:14.22$setupk4/!* 2006.173.16:34:14.22$setupk4/recpk4 2006.173.16:34:14.22$recpk4/recpatch= 2006.173.16:34:14.22$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.16:34:14.22$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.16:34:14.22$setupk4/vck44 2006.173.16:34:14.22$vck44/valo=1,524.99 2006.173.16:34:14.22#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.16:34:14.22#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.16:34:14.22#ibcon#ireg 17 cls_cnt 0 2006.173.16:34:14.22#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.16:34:14.22#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.16:34:14.22#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.16:34:14.22#ibcon#enter wrdev, iclass 33, count 0 2006.173.16:34:14.22#ibcon#first serial, iclass 33, count 0 2006.173.16:34:14.22#ibcon#enter sib2, iclass 33, count 0 2006.173.16:34:14.22#ibcon#flushed, iclass 33, count 0 2006.173.16:34:14.22#ibcon#about to write, iclass 33, count 0 2006.173.16:34:14.22#ibcon#wrote, iclass 33, count 0 2006.173.16:34:14.22#ibcon#about to read 3, iclass 33, count 0 2006.173.16:34:14.24#ibcon#read 3, iclass 33, count 0 2006.173.16:34:14.24#ibcon#about to read 4, iclass 33, count 0 2006.173.16:34:14.24#ibcon#read 4, iclass 33, count 0 2006.173.16:34:14.24#ibcon#about to read 5, iclass 33, count 0 2006.173.16:34:14.24#ibcon#read 5, iclass 33, count 0 2006.173.16:34:14.24#ibcon#about to read 6, iclass 33, count 0 2006.173.16:34:14.24#ibcon#read 6, iclass 33, count 0 2006.173.16:34:14.24#ibcon#end of sib2, iclass 33, count 0 2006.173.16:34:14.24#ibcon#*mode == 0, iclass 33, count 0 2006.173.16:34:14.24#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.16:34:14.24#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.16:34:14.24#ibcon#*before write, iclass 33, count 0 2006.173.16:34:14.24#ibcon#enter sib2, iclass 33, count 0 2006.173.16:34:14.24#ibcon#flushed, iclass 33, count 0 2006.173.16:34:14.24#ibcon#about to write, iclass 33, count 0 2006.173.16:34:14.24#ibcon#wrote, iclass 33, count 0 2006.173.16:34:14.24#ibcon#about to read 3, iclass 33, count 0 2006.173.16:34:14.29#ibcon#read 3, iclass 33, count 0 2006.173.16:34:14.29#ibcon#about to read 4, iclass 33, count 0 2006.173.16:34:14.29#ibcon#read 4, iclass 33, count 0 2006.173.16:34:14.29#ibcon#about to read 5, iclass 33, count 0 2006.173.16:34:14.29#ibcon#read 5, iclass 33, count 0 2006.173.16:34:14.29#ibcon#about to read 6, iclass 33, count 0 2006.173.16:34:14.29#ibcon#read 6, iclass 33, count 0 2006.173.16:34:14.29#ibcon#end of sib2, iclass 33, count 0 2006.173.16:34:14.29#ibcon#*after write, iclass 33, count 0 2006.173.16:34:14.29#ibcon#*before return 0, iclass 33, count 0 2006.173.16:34:14.29#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.16:34:14.29#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.16:34:14.29#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.16:34:14.29#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.16:34:14.29$vck44/va=1,7 2006.173.16:34:14.29#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.16:34:14.29#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.16:34:14.29#ibcon#ireg 11 cls_cnt 2 2006.173.16:34:14.29#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.16:34:14.29#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.16:34:14.29#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.16:34:14.29#ibcon#enter wrdev, iclass 35, count 2 2006.173.16:34:14.29#ibcon#first serial, iclass 35, count 2 2006.173.16:34:14.29#ibcon#enter sib2, iclass 35, count 2 2006.173.16:34:14.29#ibcon#flushed, iclass 35, count 2 2006.173.16:34:14.29#ibcon#about to write, iclass 35, count 2 2006.173.16:34:14.29#ibcon#wrote, iclass 35, count 2 2006.173.16:34:14.29#ibcon#about to read 3, iclass 35, count 2 2006.173.16:34:14.31#ibcon#read 3, iclass 35, count 2 2006.173.16:34:14.31#ibcon#about to read 4, iclass 35, count 2 2006.173.16:34:14.31#ibcon#read 4, iclass 35, count 2 2006.173.16:34:14.31#ibcon#about to read 5, iclass 35, count 2 2006.173.16:34:14.31#ibcon#read 5, iclass 35, count 2 2006.173.16:34:14.31#ibcon#about to read 6, iclass 35, count 2 2006.173.16:34:14.31#ibcon#read 6, iclass 35, count 2 2006.173.16:34:14.31#ibcon#end of sib2, iclass 35, count 2 2006.173.16:34:14.31#ibcon#*mode == 0, iclass 35, count 2 2006.173.16:34:14.31#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.16:34:14.31#ibcon#[25=AT01-07\r\n] 2006.173.16:34:14.31#ibcon#*before write, iclass 35, count 2 2006.173.16:34:14.31#ibcon#enter sib2, iclass 35, count 2 2006.173.16:34:14.31#ibcon#flushed, iclass 35, count 2 2006.173.16:34:14.31#ibcon#about to write, iclass 35, count 2 2006.173.16:34:14.31#ibcon#wrote, iclass 35, count 2 2006.173.16:34:14.31#ibcon#about to read 3, iclass 35, count 2 2006.173.16:34:14.34#ibcon#read 3, iclass 35, count 2 2006.173.16:34:14.34#ibcon#about to read 4, iclass 35, count 2 2006.173.16:34:14.34#ibcon#read 4, iclass 35, count 2 2006.173.16:34:14.34#ibcon#about to read 5, iclass 35, count 2 2006.173.16:34:14.34#ibcon#read 5, iclass 35, count 2 2006.173.16:34:14.34#ibcon#about to read 6, iclass 35, count 2 2006.173.16:34:14.34#ibcon#read 6, iclass 35, count 2 2006.173.16:34:14.34#ibcon#end of sib2, iclass 35, count 2 2006.173.16:34:14.34#ibcon#*after write, iclass 35, count 2 2006.173.16:34:14.34#ibcon#*before return 0, iclass 35, count 2 2006.173.16:34:14.34#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.16:34:14.34#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.16:34:14.34#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.16:34:14.34#ibcon#ireg 7 cls_cnt 0 2006.173.16:34:14.34#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.16:34:14.46#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.16:34:14.46#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.16:34:14.46#ibcon#enter wrdev, iclass 35, count 0 2006.173.16:34:14.46#ibcon#first serial, iclass 35, count 0 2006.173.16:34:14.46#ibcon#enter sib2, iclass 35, count 0 2006.173.16:34:14.46#ibcon#flushed, iclass 35, count 0 2006.173.16:34:14.46#ibcon#about to write, iclass 35, count 0 2006.173.16:34:14.46#ibcon#wrote, iclass 35, count 0 2006.173.16:34:14.46#ibcon#about to read 3, iclass 35, count 0 2006.173.16:34:14.48#ibcon#read 3, iclass 35, count 0 2006.173.16:34:14.48#ibcon#about to read 4, iclass 35, count 0 2006.173.16:34:14.48#ibcon#read 4, iclass 35, count 0 2006.173.16:34:14.48#ibcon#about to read 5, iclass 35, count 0 2006.173.16:34:14.48#ibcon#read 5, iclass 35, count 0 2006.173.16:34:14.48#ibcon#about to read 6, iclass 35, count 0 2006.173.16:34:14.48#ibcon#read 6, iclass 35, count 0 2006.173.16:34:14.48#ibcon#end of sib2, iclass 35, count 0 2006.173.16:34:14.48#ibcon#*mode == 0, iclass 35, count 0 2006.173.16:34:14.48#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.16:34:14.48#ibcon#[25=USB\r\n] 2006.173.16:34:14.48#ibcon#*before write, iclass 35, count 0 2006.173.16:34:14.48#ibcon#enter sib2, iclass 35, count 0 2006.173.16:34:14.48#ibcon#flushed, iclass 35, count 0 2006.173.16:34:14.48#ibcon#about to write, iclass 35, count 0 2006.173.16:34:14.48#ibcon#wrote, iclass 35, count 0 2006.173.16:34:14.48#ibcon#about to read 3, iclass 35, count 0 2006.173.16:34:14.51#ibcon#read 3, iclass 35, count 0 2006.173.16:34:14.51#ibcon#about to read 4, iclass 35, count 0 2006.173.16:34:14.51#ibcon#read 4, iclass 35, count 0 2006.173.16:34:14.51#ibcon#about to read 5, iclass 35, count 0 2006.173.16:34:14.51#ibcon#read 5, iclass 35, count 0 2006.173.16:34:14.51#ibcon#about to read 6, iclass 35, count 0 2006.173.16:34:14.51#ibcon#read 6, iclass 35, count 0 2006.173.16:34:14.51#ibcon#end of sib2, iclass 35, count 0 2006.173.16:34:14.51#ibcon#*after write, iclass 35, count 0 2006.173.16:34:14.51#ibcon#*before return 0, iclass 35, count 0 2006.173.16:34:14.51#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.16:34:14.51#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.16:34:14.51#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.16:34:14.51#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.16:34:14.51$vck44/valo=2,534.99 2006.173.16:34:14.51#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.16:34:14.51#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.16:34:14.51#ibcon#ireg 17 cls_cnt 0 2006.173.16:34:14.51#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.16:34:14.51#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.16:34:14.51#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.16:34:14.51#ibcon#enter wrdev, iclass 37, count 0 2006.173.16:34:14.51#ibcon#first serial, iclass 37, count 0 2006.173.16:34:14.51#ibcon#enter sib2, iclass 37, count 0 2006.173.16:34:14.51#ibcon#flushed, iclass 37, count 0 2006.173.16:34:14.51#ibcon#about to write, iclass 37, count 0 2006.173.16:34:14.51#ibcon#wrote, iclass 37, count 0 2006.173.16:34:14.51#ibcon#about to read 3, iclass 37, count 0 2006.173.16:34:14.53#ibcon#read 3, iclass 37, count 0 2006.173.16:34:14.53#ibcon#about to read 4, iclass 37, count 0 2006.173.16:34:14.53#ibcon#read 4, iclass 37, count 0 2006.173.16:34:14.53#ibcon#about to read 5, iclass 37, count 0 2006.173.16:34:14.53#ibcon#read 5, iclass 37, count 0 2006.173.16:34:14.53#ibcon#about to read 6, iclass 37, count 0 2006.173.16:34:14.53#ibcon#read 6, iclass 37, count 0 2006.173.16:34:14.53#ibcon#end of sib2, iclass 37, count 0 2006.173.16:34:14.53#ibcon#*mode == 0, iclass 37, count 0 2006.173.16:34:14.53#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.16:34:14.53#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.16:34:14.53#ibcon#*before write, iclass 37, count 0 2006.173.16:34:14.53#ibcon#enter sib2, iclass 37, count 0 2006.173.16:34:14.53#ibcon#flushed, iclass 37, count 0 2006.173.16:34:14.53#ibcon#about to write, iclass 37, count 0 2006.173.16:34:14.53#ibcon#wrote, iclass 37, count 0 2006.173.16:34:14.53#ibcon#about to read 3, iclass 37, count 0 2006.173.16:34:14.57#ibcon#read 3, iclass 37, count 0 2006.173.16:34:14.57#ibcon#about to read 4, iclass 37, count 0 2006.173.16:34:14.57#ibcon#read 4, iclass 37, count 0 2006.173.16:34:14.57#ibcon#about to read 5, iclass 37, count 0 2006.173.16:34:14.57#ibcon#read 5, iclass 37, count 0 2006.173.16:34:14.57#ibcon#about to read 6, iclass 37, count 0 2006.173.16:34:14.57#ibcon#read 6, iclass 37, count 0 2006.173.16:34:14.57#ibcon#end of sib2, iclass 37, count 0 2006.173.16:34:14.57#ibcon#*after write, iclass 37, count 0 2006.173.16:34:14.57#ibcon#*before return 0, iclass 37, count 0 2006.173.16:34:14.57#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.16:34:14.57#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.16:34:14.57#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.16:34:14.57#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.16:34:14.57$vck44/va=2,6 2006.173.16:34:14.57#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.16:34:14.57#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.16:34:14.57#ibcon#ireg 11 cls_cnt 2 2006.173.16:34:14.57#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.16:34:14.63#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.16:34:14.63#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.16:34:14.63#ibcon#enter wrdev, iclass 39, count 2 2006.173.16:34:14.63#ibcon#first serial, iclass 39, count 2 2006.173.16:34:14.63#ibcon#enter sib2, iclass 39, count 2 2006.173.16:34:14.63#ibcon#flushed, iclass 39, count 2 2006.173.16:34:14.63#ibcon#about to write, iclass 39, count 2 2006.173.16:34:14.63#ibcon#wrote, iclass 39, count 2 2006.173.16:34:14.63#ibcon#about to read 3, iclass 39, count 2 2006.173.16:34:14.65#ibcon#read 3, iclass 39, count 2 2006.173.16:34:14.65#ibcon#about to read 4, iclass 39, count 2 2006.173.16:34:14.65#ibcon#read 4, iclass 39, count 2 2006.173.16:34:14.65#ibcon#about to read 5, iclass 39, count 2 2006.173.16:34:14.65#ibcon#read 5, iclass 39, count 2 2006.173.16:34:14.65#ibcon#about to read 6, iclass 39, count 2 2006.173.16:34:14.65#ibcon#read 6, iclass 39, count 2 2006.173.16:34:14.65#ibcon#end of sib2, iclass 39, count 2 2006.173.16:34:14.65#ibcon#*mode == 0, iclass 39, count 2 2006.173.16:34:14.65#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.16:34:14.65#ibcon#[25=AT02-06\r\n] 2006.173.16:34:14.65#ibcon#*before write, iclass 39, count 2 2006.173.16:34:14.65#ibcon#enter sib2, iclass 39, count 2 2006.173.16:34:14.65#ibcon#flushed, iclass 39, count 2 2006.173.16:34:14.65#ibcon#about to write, iclass 39, count 2 2006.173.16:34:14.65#ibcon#wrote, iclass 39, count 2 2006.173.16:34:14.65#ibcon#about to read 3, iclass 39, count 2 2006.173.16:34:14.68#ibcon#read 3, iclass 39, count 2 2006.173.16:34:14.68#ibcon#about to read 4, iclass 39, count 2 2006.173.16:34:14.68#ibcon#read 4, iclass 39, count 2 2006.173.16:34:14.68#ibcon#about to read 5, iclass 39, count 2 2006.173.16:34:14.68#ibcon#read 5, iclass 39, count 2 2006.173.16:34:14.68#ibcon#about to read 6, iclass 39, count 2 2006.173.16:34:14.68#ibcon#read 6, iclass 39, count 2 2006.173.16:34:14.68#ibcon#end of sib2, iclass 39, count 2 2006.173.16:34:14.68#ibcon#*after write, iclass 39, count 2 2006.173.16:34:14.68#ibcon#*before return 0, iclass 39, count 2 2006.173.16:34:14.68#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.16:34:14.68#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.16:34:14.68#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.16:34:14.68#ibcon#ireg 7 cls_cnt 0 2006.173.16:34:14.68#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.16:34:14.80#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.16:34:14.80#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.16:34:14.80#ibcon#enter wrdev, iclass 39, count 0 2006.173.16:34:14.80#ibcon#first serial, iclass 39, count 0 2006.173.16:34:14.80#ibcon#enter sib2, iclass 39, count 0 2006.173.16:34:14.80#ibcon#flushed, iclass 39, count 0 2006.173.16:34:14.80#ibcon#about to write, iclass 39, count 0 2006.173.16:34:14.80#ibcon#wrote, iclass 39, count 0 2006.173.16:34:14.80#ibcon#about to read 3, iclass 39, count 0 2006.173.16:34:14.82#ibcon#read 3, iclass 39, count 0 2006.173.16:34:14.82#ibcon#about to read 4, iclass 39, count 0 2006.173.16:34:14.82#ibcon#read 4, iclass 39, count 0 2006.173.16:34:14.82#ibcon#about to read 5, iclass 39, count 0 2006.173.16:34:14.82#ibcon#read 5, iclass 39, count 0 2006.173.16:34:14.82#ibcon#about to read 6, iclass 39, count 0 2006.173.16:34:14.82#ibcon#read 6, iclass 39, count 0 2006.173.16:34:14.82#ibcon#end of sib2, iclass 39, count 0 2006.173.16:34:14.82#ibcon#*mode == 0, iclass 39, count 0 2006.173.16:34:14.82#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.16:34:14.82#ibcon#[25=USB\r\n] 2006.173.16:34:14.82#ibcon#*before write, iclass 39, count 0 2006.173.16:34:14.82#ibcon#enter sib2, iclass 39, count 0 2006.173.16:34:14.82#ibcon#flushed, iclass 39, count 0 2006.173.16:34:14.82#ibcon#about to write, iclass 39, count 0 2006.173.16:34:14.82#ibcon#wrote, iclass 39, count 0 2006.173.16:34:14.82#ibcon#about to read 3, iclass 39, count 0 2006.173.16:34:14.85#ibcon#read 3, iclass 39, count 0 2006.173.16:34:14.85#ibcon#about to read 4, iclass 39, count 0 2006.173.16:34:14.85#ibcon#read 4, iclass 39, count 0 2006.173.16:34:14.85#ibcon#about to read 5, iclass 39, count 0 2006.173.16:34:14.85#ibcon#read 5, iclass 39, count 0 2006.173.16:34:14.85#ibcon#about to read 6, iclass 39, count 0 2006.173.16:34:14.85#ibcon#read 6, iclass 39, count 0 2006.173.16:34:14.85#ibcon#end of sib2, iclass 39, count 0 2006.173.16:34:14.85#ibcon#*after write, iclass 39, count 0 2006.173.16:34:14.85#ibcon#*before return 0, iclass 39, count 0 2006.173.16:34:14.85#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.16:34:14.85#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.16:34:14.85#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.16:34:14.85#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.16:34:14.85$vck44/valo=3,564.99 2006.173.16:34:14.85#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.16:34:14.85#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.16:34:14.85#ibcon#ireg 17 cls_cnt 0 2006.173.16:34:14.85#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.16:34:14.85#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.16:34:14.85#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.16:34:14.85#ibcon#enter wrdev, iclass 3, count 0 2006.173.16:34:14.85#ibcon#first serial, iclass 3, count 0 2006.173.16:34:14.85#ibcon#enter sib2, iclass 3, count 0 2006.173.16:34:14.85#ibcon#flushed, iclass 3, count 0 2006.173.16:34:14.85#ibcon#about to write, iclass 3, count 0 2006.173.16:34:14.85#ibcon#wrote, iclass 3, count 0 2006.173.16:34:14.85#ibcon#about to read 3, iclass 3, count 0 2006.173.16:34:14.87#ibcon#read 3, iclass 3, count 0 2006.173.16:34:14.87#ibcon#about to read 4, iclass 3, count 0 2006.173.16:34:14.87#ibcon#read 4, iclass 3, count 0 2006.173.16:34:14.87#ibcon#about to read 5, iclass 3, count 0 2006.173.16:34:14.87#ibcon#read 5, iclass 3, count 0 2006.173.16:34:14.87#ibcon#about to read 6, iclass 3, count 0 2006.173.16:34:14.87#ibcon#read 6, iclass 3, count 0 2006.173.16:34:14.87#ibcon#end of sib2, iclass 3, count 0 2006.173.16:34:14.87#ibcon#*mode == 0, iclass 3, count 0 2006.173.16:34:14.87#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.16:34:14.87#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.16:34:14.87#ibcon#*before write, iclass 3, count 0 2006.173.16:34:14.87#ibcon#enter sib2, iclass 3, count 0 2006.173.16:34:14.87#ibcon#flushed, iclass 3, count 0 2006.173.16:34:14.87#ibcon#about to write, iclass 3, count 0 2006.173.16:34:14.87#ibcon#wrote, iclass 3, count 0 2006.173.16:34:14.87#ibcon#about to read 3, iclass 3, count 0 2006.173.16:34:14.91#ibcon#read 3, iclass 3, count 0 2006.173.16:34:14.91#ibcon#about to read 4, iclass 3, count 0 2006.173.16:34:14.91#ibcon#read 4, iclass 3, count 0 2006.173.16:34:14.91#ibcon#about to read 5, iclass 3, count 0 2006.173.16:34:14.91#ibcon#read 5, iclass 3, count 0 2006.173.16:34:14.91#ibcon#about to read 6, iclass 3, count 0 2006.173.16:34:14.91#ibcon#read 6, iclass 3, count 0 2006.173.16:34:14.91#ibcon#end of sib2, iclass 3, count 0 2006.173.16:34:14.91#ibcon#*after write, iclass 3, count 0 2006.173.16:34:14.91#ibcon#*before return 0, iclass 3, count 0 2006.173.16:34:14.91#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.16:34:14.91#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.16:34:14.91#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.16:34:14.91#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.16:34:14.91$vck44/va=3,5 2006.173.16:34:14.91#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.16:34:14.91#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.16:34:14.91#ibcon#ireg 11 cls_cnt 2 2006.173.16:34:14.91#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.16:34:14.97#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.16:34:14.97#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.16:34:14.97#ibcon#enter wrdev, iclass 5, count 2 2006.173.16:34:14.97#ibcon#first serial, iclass 5, count 2 2006.173.16:34:14.97#ibcon#enter sib2, iclass 5, count 2 2006.173.16:34:14.97#ibcon#flushed, iclass 5, count 2 2006.173.16:34:14.97#ibcon#about to write, iclass 5, count 2 2006.173.16:34:14.97#ibcon#wrote, iclass 5, count 2 2006.173.16:34:14.97#ibcon#about to read 3, iclass 5, count 2 2006.173.16:34:14.99#ibcon#read 3, iclass 5, count 2 2006.173.16:34:14.99#ibcon#about to read 4, iclass 5, count 2 2006.173.16:34:14.99#ibcon#read 4, iclass 5, count 2 2006.173.16:34:14.99#ibcon#about to read 5, iclass 5, count 2 2006.173.16:34:14.99#ibcon#read 5, iclass 5, count 2 2006.173.16:34:14.99#ibcon#about to read 6, iclass 5, count 2 2006.173.16:34:14.99#ibcon#read 6, iclass 5, count 2 2006.173.16:34:14.99#ibcon#end of sib2, iclass 5, count 2 2006.173.16:34:14.99#ibcon#*mode == 0, iclass 5, count 2 2006.173.16:34:14.99#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.16:34:14.99#ibcon#[25=AT03-05\r\n] 2006.173.16:34:14.99#ibcon#*before write, iclass 5, count 2 2006.173.16:34:14.99#ibcon#enter sib2, iclass 5, count 2 2006.173.16:34:14.99#ibcon#flushed, iclass 5, count 2 2006.173.16:34:14.99#ibcon#about to write, iclass 5, count 2 2006.173.16:34:14.99#ibcon#wrote, iclass 5, count 2 2006.173.16:34:14.99#ibcon#about to read 3, iclass 5, count 2 2006.173.16:34:15.02#ibcon#read 3, iclass 5, count 2 2006.173.16:34:15.02#ibcon#about to read 4, iclass 5, count 2 2006.173.16:34:15.02#ibcon#read 4, iclass 5, count 2 2006.173.16:34:15.02#ibcon#about to read 5, iclass 5, count 2 2006.173.16:34:15.02#ibcon#read 5, iclass 5, count 2 2006.173.16:34:15.02#ibcon#about to read 6, iclass 5, count 2 2006.173.16:34:15.02#ibcon#read 6, iclass 5, count 2 2006.173.16:34:15.02#ibcon#end of sib2, iclass 5, count 2 2006.173.16:34:15.02#ibcon#*after write, iclass 5, count 2 2006.173.16:34:15.02#ibcon#*before return 0, iclass 5, count 2 2006.173.16:34:15.02#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.16:34:15.02#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.16:34:15.02#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.16:34:15.02#ibcon#ireg 7 cls_cnt 0 2006.173.16:34:15.02#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.16:34:15.14#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.16:34:15.14#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.16:34:15.14#ibcon#enter wrdev, iclass 5, count 0 2006.173.16:34:15.14#ibcon#first serial, iclass 5, count 0 2006.173.16:34:15.14#ibcon#enter sib2, iclass 5, count 0 2006.173.16:34:15.14#ibcon#flushed, iclass 5, count 0 2006.173.16:34:15.14#ibcon#about to write, iclass 5, count 0 2006.173.16:34:15.14#ibcon#wrote, iclass 5, count 0 2006.173.16:34:15.14#ibcon#about to read 3, iclass 5, count 0 2006.173.16:34:15.16#ibcon#read 3, iclass 5, count 0 2006.173.16:34:15.16#ibcon#about to read 4, iclass 5, count 0 2006.173.16:34:15.16#ibcon#read 4, iclass 5, count 0 2006.173.16:34:15.16#ibcon#about to read 5, iclass 5, count 0 2006.173.16:34:15.16#ibcon#read 5, iclass 5, count 0 2006.173.16:34:15.16#ibcon#about to read 6, iclass 5, count 0 2006.173.16:34:15.16#ibcon#read 6, iclass 5, count 0 2006.173.16:34:15.16#ibcon#end of sib2, iclass 5, count 0 2006.173.16:34:15.16#ibcon#*mode == 0, iclass 5, count 0 2006.173.16:34:15.16#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.16:34:15.16#ibcon#[25=USB\r\n] 2006.173.16:34:15.16#ibcon#*before write, iclass 5, count 0 2006.173.16:34:15.16#ibcon#enter sib2, iclass 5, count 0 2006.173.16:34:15.16#ibcon#flushed, iclass 5, count 0 2006.173.16:34:15.16#ibcon#about to write, iclass 5, count 0 2006.173.16:34:15.16#ibcon#wrote, iclass 5, count 0 2006.173.16:34:15.16#ibcon#about to read 3, iclass 5, count 0 2006.173.16:34:15.19#ibcon#read 3, iclass 5, count 0 2006.173.16:34:15.19#ibcon#about to read 4, iclass 5, count 0 2006.173.16:34:15.19#ibcon#read 4, iclass 5, count 0 2006.173.16:34:15.19#ibcon#about to read 5, iclass 5, count 0 2006.173.16:34:15.19#ibcon#read 5, iclass 5, count 0 2006.173.16:34:15.19#ibcon#about to read 6, iclass 5, count 0 2006.173.16:34:15.19#ibcon#read 6, iclass 5, count 0 2006.173.16:34:15.19#ibcon#end of sib2, iclass 5, count 0 2006.173.16:34:15.19#ibcon#*after write, iclass 5, count 0 2006.173.16:34:15.19#ibcon#*before return 0, iclass 5, count 0 2006.173.16:34:15.19#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.16:34:15.19#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.16:34:15.19#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.16:34:15.19#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.16:34:15.19$vck44/valo=4,624.99 2006.173.16:34:15.19#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.16:34:15.19#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.16:34:15.19#ibcon#ireg 17 cls_cnt 0 2006.173.16:34:15.19#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.16:34:15.19#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.16:34:15.19#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.16:34:15.19#ibcon#enter wrdev, iclass 7, count 0 2006.173.16:34:15.19#ibcon#first serial, iclass 7, count 0 2006.173.16:34:15.19#ibcon#enter sib2, iclass 7, count 0 2006.173.16:34:15.19#ibcon#flushed, iclass 7, count 0 2006.173.16:34:15.19#ibcon#about to write, iclass 7, count 0 2006.173.16:34:15.19#ibcon#wrote, iclass 7, count 0 2006.173.16:34:15.19#ibcon#about to read 3, iclass 7, count 0 2006.173.16:34:15.21#ibcon#read 3, iclass 7, count 0 2006.173.16:34:15.21#ibcon#about to read 4, iclass 7, count 0 2006.173.16:34:15.21#ibcon#read 4, iclass 7, count 0 2006.173.16:34:15.21#ibcon#about to read 5, iclass 7, count 0 2006.173.16:34:15.21#ibcon#read 5, iclass 7, count 0 2006.173.16:34:15.21#ibcon#about to read 6, iclass 7, count 0 2006.173.16:34:15.21#ibcon#read 6, iclass 7, count 0 2006.173.16:34:15.21#ibcon#end of sib2, iclass 7, count 0 2006.173.16:34:15.21#ibcon#*mode == 0, iclass 7, count 0 2006.173.16:34:15.21#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.16:34:15.21#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.16:34:15.21#ibcon#*before write, iclass 7, count 0 2006.173.16:34:15.21#ibcon#enter sib2, iclass 7, count 0 2006.173.16:34:15.21#ibcon#flushed, iclass 7, count 0 2006.173.16:34:15.21#ibcon#about to write, iclass 7, count 0 2006.173.16:34:15.21#ibcon#wrote, iclass 7, count 0 2006.173.16:34:15.21#ibcon#about to read 3, iclass 7, count 0 2006.173.16:34:15.25#ibcon#read 3, iclass 7, count 0 2006.173.16:34:15.25#ibcon#about to read 4, iclass 7, count 0 2006.173.16:34:15.25#ibcon#read 4, iclass 7, count 0 2006.173.16:34:15.25#ibcon#about to read 5, iclass 7, count 0 2006.173.16:34:15.25#ibcon#read 5, iclass 7, count 0 2006.173.16:34:15.25#ibcon#about to read 6, iclass 7, count 0 2006.173.16:34:15.25#ibcon#read 6, iclass 7, count 0 2006.173.16:34:15.25#ibcon#end of sib2, iclass 7, count 0 2006.173.16:34:15.25#ibcon#*after write, iclass 7, count 0 2006.173.16:34:15.25#ibcon#*before return 0, iclass 7, count 0 2006.173.16:34:15.25#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.16:34:15.25#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.16:34:15.25#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.16:34:15.25#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.16:34:15.25$vck44/va=4,6 2006.173.16:34:15.25#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.16:34:15.25#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.16:34:15.25#ibcon#ireg 11 cls_cnt 2 2006.173.16:34:15.25#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.16:34:15.31#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.16:34:15.31#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.16:34:15.31#ibcon#enter wrdev, iclass 11, count 2 2006.173.16:34:15.31#ibcon#first serial, iclass 11, count 2 2006.173.16:34:15.31#ibcon#enter sib2, iclass 11, count 2 2006.173.16:34:15.31#ibcon#flushed, iclass 11, count 2 2006.173.16:34:15.31#ibcon#about to write, iclass 11, count 2 2006.173.16:34:15.31#ibcon#wrote, iclass 11, count 2 2006.173.16:34:15.31#ibcon#about to read 3, iclass 11, count 2 2006.173.16:34:15.33#ibcon#read 3, iclass 11, count 2 2006.173.16:34:15.33#ibcon#about to read 4, iclass 11, count 2 2006.173.16:34:15.33#ibcon#read 4, iclass 11, count 2 2006.173.16:34:15.33#ibcon#about to read 5, iclass 11, count 2 2006.173.16:34:15.33#ibcon#read 5, iclass 11, count 2 2006.173.16:34:15.33#ibcon#about to read 6, iclass 11, count 2 2006.173.16:34:15.33#ibcon#read 6, iclass 11, count 2 2006.173.16:34:15.33#ibcon#end of sib2, iclass 11, count 2 2006.173.16:34:15.33#ibcon#*mode == 0, iclass 11, count 2 2006.173.16:34:15.33#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.16:34:15.33#ibcon#[25=AT04-06\r\n] 2006.173.16:34:15.33#ibcon#*before write, iclass 11, count 2 2006.173.16:34:15.33#ibcon#enter sib2, iclass 11, count 2 2006.173.16:34:15.33#ibcon#flushed, iclass 11, count 2 2006.173.16:34:15.33#ibcon#about to write, iclass 11, count 2 2006.173.16:34:15.33#ibcon#wrote, iclass 11, count 2 2006.173.16:34:15.33#ibcon#about to read 3, iclass 11, count 2 2006.173.16:34:15.36#ibcon#read 3, iclass 11, count 2 2006.173.16:34:15.36#ibcon#about to read 4, iclass 11, count 2 2006.173.16:34:15.36#ibcon#read 4, iclass 11, count 2 2006.173.16:34:15.36#ibcon#about to read 5, iclass 11, count 2 2006.173.16:34:15.36#ibcon#read 5, iclass 11, count 2 2006.173.16:34:15.36#ibcon#about to read 6, iclass 11, count 2 2006.173.16:34:15.36#ibcon#read 6, iclass 11, count 2 2006.173.16:34:15.36#ibcon#end of sib2, iclass 11, count 2 2006.173.16:34:15.36#ibcon#*after write, iclass 11, count 2 2006.173.16:34:15.36#ibcon#*before return 0, iclass 11, count 2 2006.173.16:34:15.36#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.16:34:15.36#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.16:34:15.36#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.16:34:15.36#ibcon#ireg 7 cls_cnt 0 2006.173.16:34:15.36#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.16:34:15.48#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.16:34:15.48#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.16:34:15.48#ibcon#enter wrdev, iclass 11, count 0 2006.173.16:34:15.48#ibcon#first serial, iclass 11, count 0 2006.173.16:34:15.48#ibcon#enter sib2, iclass 11, count 0 2006.173.16:34:15.48#ibcon#flushed, iclass 11, count 0 2006.173.16:34:15.48#ibcon#about to write, iclass 11, count 0 2006.173.16:34:15.48#ibcon#wrote, iclass 11, count 0 2006.173.16:34:15.48#ibcon#about to read 3, iclass 11, count 0 2006.173.16:34:15.50#ibcon#read 3, iclass 11, count 0 2006.173.16:34:15.50#ibcon#about to read 4, iclass 11, count 0 2006.173.16:34:15.50#ibcon#read 4, iclass 11, count 0 2006.173.16:34:15.50#ibcon#about to read 5, iclass 11, count 0 2006.173.16:34:15.50#ibcon#read 5, iclass 11, count 0 2006.173.16:34:15.50#ibcon#about to read 6, iclass 11, count 0 2006.173.16:34:15.50#ibcon#read 6, iclass 11, count 0 2006.173.16:34:15.50#ibcon#end of sib2, iclass 11, count 0 2006.173.16:34:15.50#ibcon#*mode == 0, iclass 11, count 0 2006.173.16:34:15.50#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.16:34:15.50#ibcon#[25=USB\r\n] 2006.173.16:34:15.50#ibcon#*before write, iclass 11, count 0 2006.173.16:34:15.50#ibcon#enter sib2, iclass 11, count 0 2006.173.16:34:15.50#ibcon#flushed, iclass 11, count 0 2006.173.16:34:15.50#ibcon#about to write, iclass 11, count 0 2006.173.16:34:15.50#ibcon#wrote, iclass 11, count 0 2006.173.16:34:15.50#ibcon#about to read 3, iclass 11, count 0 2006.173.16:34:15.53#ibcon#read 3, iclass 11, count 0 2006.173.16:34:15.53#ibcon#about to read 4, iclass 11, count 0 2006.173.16:34:15.53#ibcon#read 4, iclass 11, count 0 2006.173.16:34:15.53#ibcon#about to read 5, iclass 11, count 0 2006.173.16:34:15.53#ibcon#read 5, iclass 11, count 0 2006.173.16:34:15.53#ibcon#about to read 6, iclass 11, count 0 2006.173.16:34:15.53#ibcon#read 6, iclass 11, count 0 2006.173.16:34:15.53#ibcon#end of sib2, iclass 11, count 0 2006.173.16:34:15.53#ibcon#*after write, iclass 11, count 0 2006.173.16:34:15.53#ibcon#*before return 0, iclass 11, count 0 2006.173.16:34:15.53#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.16:34:15.53#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.16:34:15.53#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.16:34:15.53#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.16:34:15.53$vck44/valo=5,734.99 2006.173.16:34:15.53#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.16:34:15.53#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.16:34:15.53#ibcon#ireg 17 cls_cnt 0 2006.173.16:34:15.53#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.16:34:15.53#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.16:34:15.53#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.16:34:15.53#ibcon#enter wrdev, iclass 13, count 0 2006.173.16:34:15.53#ibcon#first serial, iclass 13, count 0 2006.173.16:34:15.53#ibcon#enter sib2, iclass 13, count 0 2006.173.16:34:15.53#ibcon#flushed, iclass 13, count 0 2006.173.16:34:15.53#ibcon#about to write, iclass 13, count 0 2006.173.16:34:15.53#ibcon#wrote, iclass 13, count 0 2006.173.16:34:15.53#ibcon#about to read 3, iclass 13, count 0 2006.173.16:34:15.55#ibcon#read 3, iclass 13, count 0 2006.173.16:34:15.55#ibcon#about to read 4, iclass 13, count 0 2006.173.16:34:15.55#ibcon#read 4, iclass 13, count 0 2006.173.16:34:15.55#ibcon#about to read 5, iclass 13, count 0 2006.173.16:34:15.55#ibcon#read 5, iclass 13, count 0 2006.173.16:34:15.55#ibcon#about to read 6, iclass 13, count 0 2006.173.16:34:15.55#ibcon#read 6, iclass 13, count 0 2006.173.16:34:15.55#ibcon#end of sib2, iclass 13, count 0 2006.173.16:34:15.55#ibcon#*mode == 0, iclass 13, count 0 2006.173.16:34:15.55#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.16:34:15.55#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.16:34:15.55#ibcon#*before write, iclass 13, count 0 2006.173.16:34:15.55#ibcon#enter sib2, iclass 13, count 0 2006.173.16:34:15.55#ibcon#flushed, iclass 13, count 0 2006.173.16:34:15.55#ibcon#about to write, iclass 13, count 0 2006.173.16:34:15.55#ibcon#wrote, iclass 13, count 0 2006.173.16:34:15.55#ibcon#about to read 3, iclass 13, count 0 2006.173.16:34:15.59#ibcon#read 3, iclass 13, count 0 2006.173.16:34:15.59#ibcon#about to read 4, iclass 13, count 0 2006.173.16:34:15.59#ibcon#read 4, iclass 13, count 0 2006.173.16:34:15.59#ibcon#about to read 5, iclass 13, count 0 2006.173.16:34:15.59#ibcon#read 5, iclass 13, count 0 2006.173.16:34:15.59#ibcon#about to read 6, iclass 13, count 0 2006.173.16:34:15.59#ibcon#read 6, iclass 13, count 0 2006.173.16:34:15.59#ibcon#end of sib2, iclass 13, count 0 2006.173.16:34:15.59#ibcon#*after write, iclass 13, count 0 2006.173.16:34:15.59#ibcon#*before return 0, iclass 13, count 0 2006.173.16:34:15.59#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.16:34:15.59#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.16:34:15.59#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.16:34:15.59#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.16:34:15.59$vck44/va=5,4 2006.173.16:34:15.59#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.16:34:15.59#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.16:34:15.59#ibcon#ireg 11 cls_cnt 2 2006.173.16:34:15.59#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.16:34:15.65#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.16:34:15.65#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.16:34:15.65#ibcon#enter wrdev, iclass 15, count 2 2006.173.16:34:15.65#ibcon#first serial, iclass 15, count 2 2006.173.16:34:15.65#ibcon#enter sib2, iclass 15, count 2 2006.173.16:34:15.65#ibcon#flushed, iclass 15, count 2 2006.173.16:34:15.65#ibcon#about to write, iclass 15, count 2 2006.173.16:34:15.65#ibcon#wrote, iclass 15, count 2 2006.173.16:34:15.65#ibcon#about to read 3, iclass 15, count 2 2006.173.16:34:15.67#ibcon#read 3, iclass 15, count 2 2006.173.16:34:15.67#ibcon#about to read 4, iclass 15, count 2 2006.173.16:34:15.67#ibcon#read 4, iclass 15, count 2 2006.173.16:34:15.67#ibcon#about to read 5, iclass 15, count 2 2006.173.16:34:15.67#ibcon#read 5, iclass 15, count 2 2006.173.16:34:15.67#ibcon#about to read 6, iclass 15, count 2 2006.173.16:34:15.67#ibcon#read 6, iclass 15, count 2 2006.173.16:34:15.67#ibcon#end of sib2, iclass 15, count 2 2006.173.16:34:15.67#ibcon#*mode == 0, iclass 15, count 2 2006.173.16:34:15.67#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.16:34:15.67#ibcon#[25=AT05-04\r\n] 2006.173.16:34:15.67#ibcon#*before write, iclass 15, count 2 2006.173.16:34:15.67#ibcon#enter sib2, iclass 15, count 2 2006.173.16:34:15.67#ibcon#flushed, iclass 15, count 2 2006.173.16:34:15.67#ibcon#about to write, iclass 15, count 2 2006.173.16:34:15.67#ibcon#wrote, iclass 15, count 2 2006.173.16:34:15.67#ibcon#about to read 3, iclass 15, count 2 2006.173.16:34:15.70#ibcon#read 3, iclass 15, count 2 2006.173.16:34:15.70#ibcon#about to read 4, iclass 15, count 2 2006.173.16:34:15.70#ibcon#read 4, iclass 15, count 2 2006.173.16:34:15.70#ibcon#about to read 5, iclass 15, count 2 2006.173.16:34:15.70#ibcon#read 5, iclass 15, count 2 2006.173.16:34:15.70#ibcon#about to read 6, iclass 15, count 2 2006.173.16:34:15.70#ibcon#read 6, iclass 15, count 2 2006.173.16:34:15.70#ibcon#end of sib2, iclass 15, count 2 2006.173.16:34:15.70#ibcon#*after write, iclass 15, count 2 2006.173.16:34:15.70#ibcon#*before return 0, iclass 15, count 2 2006.173.16:34:15.70#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.16:34:15.70#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.16:34:15.70#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.16:34:15.70#ibcon#ireg 7 cls_cnt 0 2006.173.16:34:15.70#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.16:34:15.82#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.16:34:15.82#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.16:34:15.82#ibcon#enter wrdev, iclass 15, count 0 2006.173.16:34:15.82#ibcon#first serial, iclass 15, count 0 2006.173.16:34:15.82#ibcon#enter sib2, iclass 15, count 0 2006.173.16:34:15.82#ibcon#flushed, iclass 15, count 0 2006.173.16:34:15.82#ibcon#about to write, iclass 15, count 0 2006.173.16:34:15.82#ibcon#wrote, iclass 15, count 0 2006.173.16:34:15.82#ibcon#about to read 3, iclass 15, count 0 2006.173.16:34:15.84#ibcon#read 3, iclass 15, count 0 2006.173.16:34:15.84#ibcon#about to read 4, iclass 15, count 0 2006.173.16:34:15.84#ibcon#read 4, iclass 15, count 0 2006.173.16:34:15.84#ibcon#about to read 5, iclass 15, count 0 2006.173.16:34:15.84#ibcon#read 5, iclass 15, count 0 2006.173.16:34:15.84#ibcon#about to read 6, iclass 15, count 0 2006.173.16:34:15.84#ibcon#read 6, iclass 15, count 0 2006.173.16:34:15.84#ibcon#end of sib2, iclass 15, count 0 2006.173.16:34:15.84#ibcon#*mode == 0, iclass 15, count 0 2006.173.16:34:15.84#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.16:34:15.84#ibcon#[25=USB\r\n] 2006.173.16:34:15.84#ibcon#*before write, iclass 15, count 0 2006.173.16:34:15.84#ibcon#enter sib2, iclass 15, count 0 2006.173.16:34:15.84#ibcon#flushed, iclass 15, count 0 2006.173.16:34:15.84#ibcon#about to write, iclass 15, count 0 2006.173.16:34:15.84#ibcon#wrote, iclass 15, count 0 2006.173.16:34:15.84#ibcon#about to read 3, iclass 15, count 0 2006.173.16:34:15.87#ibcon#read 3, iclass 15, count 0 2006.173.16:34:15.87#ibcon#about to read 4, iclass 15, count 0 2006.173.16:34:15.87#ibcon#read 4, iclass 15, count 0 2006.173.16:34:15.87#ibcon#about to read 5, iclass 15, count 0 2006.173.16:34:15.87#ibcon#read 5, iclass 15, count 0 2006.173.16:34:15.87#ibcon#about to read 6, iclass 15, count 0 2006.173.16:34:15.87#ibcon#read 6, iclass 15, count 0 2006.173.16:34:15.87#ibcon#end of sib2, iclass 15, count 0 2006.173.16:34:15.87#ibcon#*after write, iclass 15, count 0 2006.173.16:34:15.87#ibcon#*before return 0, iclass 15, count 0 2006.173.16:34:15.87#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.16:34:15.87#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.16:34:15.87#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.16:34:15.87#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.16:34:15.87$vck44/valo=6,814.99 2006.173.16:34:15.87#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.16:34:15.87#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.16:34:15.87#ibcon#ireg 17 cls_cnt 0 2006.173.16:34:15.87#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.16:34:15.87#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.16:34:15.87#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.16:34:15.87#ibcon#enter wrdev, iclass 17, count 0 2006.173.16:34:15.87#ibcon#first serial, iclass 17, count 0 2006.173.16:34:15.87#ibcon#enter sib2, iclass 17, count 0 2006.173.16:34:15.87#ibcon#flushed, iclass 17, count 0 2006.173.16:34:15.87#ibcon#about to write, iclass 17, count 0 2006.173.16:34:15.87#ibcon#wrote, iclass 17, count 0 2006.173.16:34:15.87#ibcon#about to read 3, iclass 17, count 0 2006.173.16:34:15.89#ibcon#read 3, iclass 17, count 0 2006.173.16:34:15.89#ibcon#about to read 4, iclass 17, count 0 2006.173.16:34:15.89#ibcon#read 4, iclass 17, count 0 2006.173.16:34:15.89#ibcon#about to read 5, iclass 17, count 0 2006.173.16:34:15.89#ibcon#read 5, iclass 17, count 0 2006.173.16:34:15.89#ibcon#about to read 6, iclass 17, count 0 2006.173.16:34:15.89#ibcon#read 6, iclass 17, count 0 2006.173.16:34:15.89#ibcon#end of sib2, iclass 17, count 0 2006.173.16:34:15.89#ibcon#*mode == 0, iclass 17, count 0 2006.173.16:34:15.89#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.16:34:15.89#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.16:34:15.89#ibcon#*before write, iclass 17, count 0 2006.173.16:34:15.89#ibcon#enter sib2, iclass 17, count 0 2006.173.16:34:15.89#ibcon#flushed, iclass 17, count 0 2006.173.16:34:15.89#ibcon#about to write, iclass 17, count 0 2006.173.16:34:15.89#ibcon#wrote, iclass 17, count 0 2006.173.16:34:15.89#ibcon#about to read 3, iclass 17, count 0 2006.173.16:34:15.93#ibcon#read 3, iclass 17, count 0 2006.173.16:34:15.93#ibcon#about to read 4, iclass 17, count 0 2006.173.16:34:15.93#ibcon#read 4, iclass 17, count 0 2006.173.16:34:15.93#ibcon#about to read 5, iclass 17, count 0 2006.173.16:34:15.93#ibcon#read 5, iclass 17, count 0 2006.173.16:34:15.93#ibcon#about to read 6, iclass 17, count 0 2006.173.16:34:15.93#ibcon#read 6, iclass 17, count 0 2006.173.16:34:15.93#ibcon#end of sib2, iclass 17, count 0 2006.173.16:34:15.93#ibcon#*after write, iclass 17, count 0 2006.173.16:34:15.93#ibcon#*before return 0, iclass 17, count 0 2006.173.16:34:15.93#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.16:34:15.93#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.16:34:15.93#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.16:34:15.93#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.16:34:15.93$vck44/va=6,3 2006.173.16:34:15.93#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.16:34:15.93#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.16:34:15.93#ibcon#ireg 11 cls_cnt 2 2006.173.16:34:15.93#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.16:34:15.99#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.16:34:15.99#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.16:34:15.99#ibcon#enter wrdev, iclass 19, count 2 2006.173.16:34:15.99#ibcon#first serial, iclass 19, count 2 2006.173.16:34:15.99#ibcon#enter sib2, iclass 19, count 2 2006.173.16:34:15.99#ibcon#flushed, iclass 19, count 2 2006.173.16:34:15.99#ibcon#about to write, iclass 19, count 2 2006.173.16:34:15.99#ibcon#wrote, iclass 19, count 2 2006.173.16:34:15.99#ibcon#about to read 3, iclass 19, count 2 2006.173.16:34:16.01#ibcon#read 3, iclass 19, count 2 2006.173.16:34:16.01#ibcon#about to read 4, iclass 19, count 2 2006.173.16:34:16.01#ibcon#read 4, iclass 19, count 2 2006.173.16:34:16.01#ibcon#about to read 5, iclass 19, count 2 2006.173.16:34:16.01#ibcon#read 5, iclass 19, count 2 2006.173.16:34:16.01#ibcon#about to read 6, iclass 19, count 2 2006.173.16:34:16.01#ibcon#read 6, iclass 19, count 2 2006.173.16:34:16.01#ibcon#end of sib2, iclass 19, count 2 2006.173.16:34:16.01#ibcon#*mode == 0, iclass 19, count 2 2006.173.16:34:16.01#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.16:34:16.01#ibcon#[25=AT06-03\r\n] 2006.173.16:34:16.01#ibcon#*before write, iclass 19, count 2 2006.173.16:34:16.01#ibcon#enter sib2, iclass 19, count 2 2006.173.16:34:16.01#ibcon#flushed, iclass 19, count 2 2006.173.16:34:16.01#ibcon#about to write, iclass 19, count 2 2006.173.16:34:16.01#ibcon#wrote, iclass 19, count 2 2006.173.16:34:16.01#ibcon#about to read 3, iclass 19, count 2 2006.173.16:34:16.04#ibcon#read 3, iclass 19, count 2 2006.173.16:34:16.04#ibcon#about to read 4, iclass 19, count 2 2006.173.16:34:16.04#ibcon#read 4, iclass 19, count 2 2006.173.16:34:16.04#ibcon#about to read 5, iclass 19, count 2 2006.173.16:34:16.04#ibcon#read 5, iclass 19, count 2 2006.173.16:34:16.04#ibcon#about to read 6, iclass 19, count 2 2006.173.16:34:16.04#ibcon#read 6, iclass 19, count 2 2006.173.16:34:16.04#ibcon#end of sib2, iclass 19, count 2 2006.173.16:34:16.04#ibcon#*after write, iclass 19, count 2 2006.173.16:34:16.04#ibcon#*before return 0, iclass 19, count 2 2006.173.16:34:16.04#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.16:34:16.04#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.16:34:16.04#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.16:34:16.04#ibcon#ireg 7 cls_cnt 0 2006.173.16:34:16.04#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.16:34:16.16#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.16:34:16.16#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.16:34:16.16#ibcon#enter wrdev, iclass 19, count 0 2006.173.16:34:16.16#ibcon#first serial, iclass 19, count 0 2006.173.16:34:16.16#ibcon#enter sib2, iclass 19, count 0 2006.173.16:34:16.16#ibcon#flushed, iclass 19, count 0 2006.173.16:34:16.16#ibcon#about to write, iclass 19, count 0 2006.173.16:34:16.16#ibcon#wrote, iclass 19, count 0 2006.173.16:34:16.16#ibcon#about to read 3, iclass 19, count 0 2006.173.16:34:16.18#ibcon#read 3, iclass 19, count 0 2006.173.16:34:16.18#ibcon#about to read 4, iclass 19, count 0 2006.173.16:34:16.18#ibcon#read 4, iclass 19, count 0 2006.173.16:34:16.18#ibcon#about to read 5, iclass 19, count 0 2006.173.16:34:16.18#ibcon#read 5, iclass 19, count 0 2006.173.16:34:16.18#ibcon#about to read 6, iclass 19, count 0 2006.173.16:34:16.18#ibcon#read 6, iclass 19, count 0 2006.173.16:34:16.18#ibcon#end of sib2, iclass 19, count 0 2006.173.16:34:16.18#ibcon#*mode == 0, iclass 19, count 0 2006.173.16:34:16.18#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.16:34:16.18#ibcon#[25=USB\r\n] 2006.173.16:34:16.18#ibcon#*before write, iclass 19, count 0 2006.173.16:34:16.18#ibcon#enter sib2, iclass 19, count 0 2006.173.16:34:16.18#ibcon#flushed, iclass 19, count 0 2006.173.16:34:16.18#ibcon#about to write, iclass 19, count 0 2006.173.16:34:16.18#ibcon#wrote, iclass 19, count 0 2006.173.16:34:16.18#ibcon#about to read 3, iclass 19, count 0 2006.173.16:34:16.21#ibcon#read 3, iclass 19, count 0 2006.173.16:34:16.21#ibcon#about to read 4, iclass 19, count 0 2006.173.16:34:16.21#ibcon#read 4, iclass 19, count 0 2006.173.16:34:16.21#ibcon#about to read 5, iclass 19, count 0 2006.173.16:34:16.21#ibcon#read 5, iclass 19, count 0 2006.173.16:34:16.21#ibcon#about to read 6, iclass 19, count 0 2006.173.16:34:16.21#ibcon#read 6, iclass 19, count 0 2006.173.16:34:16.21#ibcon#end of sib2, iclass 19, count 0 2006.173.16:34:16.21#ibcon#*after write, iclass 19, count 0 2006.173.16:34:16.21#ibcon#*before return 0, iclass 19, count 0 2006.173.16:34:16.21#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.16:34:16.21#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.16:34:16.21#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.16:34:16.21#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.16:34:16.21$vck44/valo=7,864.99 2006.173.16:34:16.21#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.16:34:16.21#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.16:34:16.21#ibcon#ireg 17 cls_cnt 0 2006.173.16:34:16.21#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.16:34:16.21#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.16:34:16.21#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.16:34:16.21#ibcon#enter wrdev, iclass 21, count 0 2006.173.16:34:16.21#ibcon#first serial, iclass 21, count 0 2006.173.16:34:16.21#ibcon#enter sib2, iclass 21, count 0 2006.173.16:34:16.21#ibcon#flushed, iclass 21, count 0 2006.173.16:34:16.21#ibcon#about to write, iclass 21, count 0 2006.173.16:34:16.21#ibcon#wrote, iclass 21, count 0 2006.173.16:34:16.21#ibcon#about to read 3, iclass 21, count 0 2006.173.16:34:16.23#ibcon#read 3, iclass 21, count 0 2006.173.16:34:16.23#ibcon#about to read 4, iclass 21, count 0 2006.173.16:34:16.23#ibcon#read 4, iclass 21, count 0 2006.173.16:34:16.23#ibcon#about to read 5, iclass 21, count 0 2006.173.16:34:16.23#ibcon#read 5, iclass 21, count 0 2006.173.16:34:16.23#ibcon#about to read 6, iclass 21, count 0 2006.173.16:34:16.23#ibcon#read 6, iclass 21, count 0 2006.173.16:34:16.23#ibcon#end of sib2, iclass 21, count 0 2006.173.16:34:16.23#ibcon#*mode == 0, iclass 21, count 0 2006.173.16:34:16.23#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.16:34:16.23#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.16:34:16.23#ibcon#*before write, iclass 21, count 0 2006.173.16:34:16.23#ibcon#enter sib2, iclass 21, count 0 2006.173.16:34:16.23#ibcon#flushed, iclass 21, count 0 2006.173.16:34:16.23#ibcon#about to write, iclass 21, count 0 2006.173.16:34:16.23#ibcon#wrote, iclass 21, count 0 2006.173.16:34:16.23#ibcon#about to read 3, iclass 21, count 0 2006.173.16:34:16.27#ibcon#read 3, iclass 21, count 0 2006.173.16:34:16.27#ibcon#about to read 4, iclass 21, count 0 2006.173.16:34:16.27#ibcon#read 4, iclass 21, count 0 2006.173.16:34:16.27#ibcon#about to read 5, iclass 21, count 0 2006.173.16:34:16.27#ibcon#read 5, iclass 21, count 0 2006.173.16:34:16.27#ibcon#about to read 6, iclass 21, count 0 2006.173.16:34:16.27#ibcon#read 6, iclass 21, count 0 2006.173.16:34:16.27#ibcon#end of sib2, iclass 21, count 0 2006.173.16:34:16.27#ibcon#*after write, iclass 21, count 0 2006.173.16:34:16.27#ibcon#*before return 0, iclass 21, count 0 2006.173.16:34:16.27#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.16:34:16.27#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.16:34:16.27#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.16:34:16.27#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.16:34:16.27$vck44/va=7,4 2006.173.16:34:16.27#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.16:34:16.27#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.16:34:16.27#ibcon#ireg 11 cls_cnt 2 2006.173.16:34:16.27#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.16:34:16.33#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.16:34:16.33#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.16:34:16.33#ibcon#enter wrdev, iclass 23, count 2 2006.173.16:34:16.33#ibcon#first serial, iclass 23, count 2 2006.173.16:34:16.33#ibcon#enter sib2, iclass 23, count 2 2006.173.16:34:16.33#ibcon#flushed, iclass 23, count 2 2006.173.16:34:16.33#ibcon#about to write, iclass 23, count 2 2006.173.16:34:16.33#ibcon#wrote, iclass 23, count 2 2006.173.16:34:16.33#ibcon#about to read 3, iclass 23, count 2 2006.173.16:34:16.35#ibcon#read 3, iclass 23, count 2 2006.173.16:34:16.35#ibcon#about to read 4, iclass 23, count 2 2006.173.16:34:16.35#ibcon#read 4, iclass 23, count 2 2006.173.16:34:16.35#ibcon#about to read 5, iclass 23, count 2 2006.173.16:34:16.35#ibcon#read 5, iclass 23, count 2 2006.173.16:34:16.35#ibcon#about to read 6, iclass 23, count 2 2006.173.16:34:16.35#ibcon#read 6, iclass 23, count 2 2006.173.16:34:16.35#ibcon#end of sib2, iclass 23, count 2 2006.173.16:34:16.35#ibcon#*mode == 0, iclass 23, count 2 2006.173.16:34:16.35#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.16:34:16.35#ibcon#[25=AT07-04\r\n] 2006.173.16:34:16.35#ibcon#*before write, iclass 23, count 2 2006.173.16:34:16.35#ibcon#enter sib2, iclass 23, count 2 2006.173.16:34:16.35#ibcon#flushed, iclass 23, count 2 2006.173.16:34:16.35#ibcon#about to write, iclass 23, count 2 2006.173.16:34:16.35#ibcon#wrote, iclass 23, count 2 2006.173.16:34:16.35#ibcon#about to read 3, iclass 23, count 2 2006.173.16:34:16.38#ibcon#read 3, iclass 23, count 2 2006.173.16:34:16.38#ibcon#about to read 4, iclass 23, count 2 2006.173.16:34:16.38#ibcon#read 4, iclass 23, count 2 2006.173.16:34:16.38#ibcon#about to read 5, iclass 23, count 2 2006.173.16:34:16.38#ibcon#read 5, iclass 23, count 2 2006.173.16:34:16.38#ibcon#about to read 6, iclass 23, count 2 2006.173.16:34:16.38#ibcon#read 6, iclass 23, count 2 2006.173.16:34:16.38#ibcon#end of sib2, iclass 23, count 2 2006.173.16:34:16.38#ibcon#*after write, iclass 23, count 2 2006.173.16:34:16.38#ibcon#*before return 0, iclass 23, count 2 2006.173.16:34:16.38#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.16:34:16.38#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.16:34:16.38#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.16:34:16.38#ibcon#ireg 7 cls_cnt 0 2006.173.16:34:16.38#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.16:34:16.50#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.16:34:16.50#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.16:34:16.50#ibcon#enter wrdev, iclass 23, count 0 2006.173.16:34:16.50#ibcon#first serial, iclass 23, count 0 2006.173.16:34:16.50#ibcon#enter sib2, iclass 23, count 0 2006.173.16:34:16.50#ibcon#flushed, iclass 23, count 0 2006.173.16:34:16.50#ibcon#about to write, iclass 23, count 0 2006.173.16:34:16.50#ibcon#wrote, iclass 23, count 0 2006.173.16:34:16.50#ibcon#about to read 3, iclass 23, count 0 2006.173.16:34:16.52#ibcon#read 3, iclass 23, count 0 2006.173.16:34:16.52#ibcon#about to read 4, iclass 23, count 0 2006.173.16:34:16.52#ibcon#read 4, iclass 23, count 0 2006.173.16:34:16.52#ibcon#about to read 5, iclass 23, count 0 2006.173.16:34:16.52#ibcon#read 5, iclass 23, count 0 2006.173.16:34:16.52#ibcon#about to read 6, iclass 23, count 0 2006.173.16:34:16.52#ibcon#read 6, iclass 23, count 0 2006.173.16:34:16.52#ibcon#end of sib2, iclass 23, count 0 2006.173.16:34:16.52#ibcon#*mode == 0, iclass 23, count 0 2006.173.16:34:16.52#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.16:34:16.52#ibcon#[25=USB\r\n] 2006.173.16:34:16.52#ibcon#*before write, iclass 23, count 0 2006.173.16:34:16.52#ibcon#enter sib2, iclass 23, count 0 2006.173.16:34:16.52#ibcon#flushed, iclass 23, count 0 2006.173.16:34:16.52#ibcon#about to write, iclass 23, count 0 2006.173.16:34:16.52#ibcon#wrote, iclass 23, count 0 2006.173.16:34:16.52#ibcon#about to read 3, iclass 23, count 0 2006.173.16:34:16.55#ibcon#read 3, iclass 23, count 0 2006.173.16:34:16.55#ibcon#about to read 4, iclass 23, count 0 2006.173.16:34:16.55#ibcon#read 4, iclass 23, count 0 2006.173.16:34:16.55#ibcon#about to read 5, iclass 23, count 0 2006.173.16:34:16.55#ibcon#read 5, iclass 23, count 0 2006.173.16:34:16.55#ibcon#about to read 6, iclass 23, count 0 2006.173.16:34:16.55#ibcon#read 6, iclass 23, count 0 2006.173.16:34:16.55#ibcon#end of sib2, iclass 23, count 0 2006.173.16:34:16.55#ibcon#*after write, iclass 23, count 0 2006.173.16:34:16.55#ibcon#*before return 0, iclass 23, count 0 2006.173.16:34:16.55#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.16:34:16.55#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.16:34:16.55#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.16:34:16.55#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.16:34:16.55$vck44/valo=8,884.99 2006.173.16:34:16.55#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.16:34:16.55#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.16:34:16.55#ibcon#ireg 17 cls_cnt 0 2006.173.16:34:16.55#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.16:34:16.55#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.16:34:16.55#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.16:34:16.55#ibcon#enter wrdev, iclass 25, count 0 2006.173.16:34:16.55#ibcon#first serial, iclass 25, count 0 2006.173.16:34:16.55#ibcon#enter sib2, iclass 25, count 0 2006.173.16:34:16.55#ibcon#flushed, iclass 25, count 0 2006.173.16:34:16.55#ibcon#about to write, iclass 25, count 0 2006.173.16:34:16.55#ibcon#wrote, iclass 25, count 0 2006.173.16:34:16.55#ibcon#about to read 3, iclass 25, count 0 2006.173.16:34:16.57#ibcon#read 3, iclass 25, count 0 2006.173.16:34:16.57#ibcon#about to read 4, iclass 25, count 0 2006.173.16:34:16.57#ibcon#read 4, iclass 25, count 0 2006.173.16:34:16.57#ibcon#about to read 5, iclass 25, count 0 2006.173.16:34:16.57#ibcon#read 5, iclass 25, count 0 2006.173.16:34:16.57#ibcon#about to read 6, iclass 25, count 0 2006.173.16:34:16.57#ibcon#read 6, iclass 25, count 0 2006.173.16:34:16.57#ibcon#end of sib2, iclass 25, count 0 2006.173.16:34:16.57#ibcon#*mode == 0, iclass 25, count 0 2006.173.16:34:16.57#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.16:34:16.57#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.16:34:16.57#ibcon#*before write, iclass 25, count 0 2006.173.16:34:16.57#ibcon#enter sib2, iclass 25, count 0 2006.173.16:34:16.57#ibcon#flushed, iclass 25, count 0 2006.173.16:34:16.57#ibcon#about to write, iclass 25, count 0 2006.173.16:34:16.57#ibcon#wrote, iclass 25, count 0 2006.173.16:34:16.57#ibcon#about to read 3, iclass 25, count 0 2006.173.16:34:16.61#ibcon#read 3, iclass 25, count 0 2006.173.16:34:16.61#ibcon#about to read 4, iclass 25, count 0 2006.173.16:34:16.61#ibcon#read 4, iclass 25, count 0 2006.173.16:34:16.61#ibcon#about to read 5, iclass 25, count 0 2006.173.16:34:16.61#ibcon#read 5, iclass 25, count 0 2006.173.16:34:16.61#ibcon#about to read 6, iclass 25, count 0 2006.173.16:34:16.61#ibcon#read 6, iclass 25, count 0 2006.173.16:34:16.61#ibcon#end of sib2, iclass 25, count 0 2006.173.16:34:16.61#ibcon#*after write, iclass 25, count 0 2006.173.16:34:16.61#ibcon#*before return 0, iclass 25, count 0 2006.173.16:34:16.61#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.16:34:16.61#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.16:34:16.61#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.16:34:16.61#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.16:34:16.61$vck44/va=8,4 2006.173.16:34:16.61#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.16:34:16.61#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.16:34:16.61#ibcon#ireg 11 cls_cnt 2 2006.173.16:34:16.61#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.16:34:16.67#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.16:34:16.67#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.16:34:16.67#ibcon#enter wrdev, iclass 27, count 2 2006.173.16:34:16.67#ibcon#first serial, iclass 27, count 2 2006.173.16:34:16.67#ibcon#enter sib2, iclass 27, count 2 2006.173.16:34:16.67#ibcon#flushed, iclass 27, count 2 2006.173.16:34:16.67#ibcon#about to write, iclass 27, count 2 2006.173.16:34:16.67#ibcon#wrote, iclass 27, count 2 2006.173.16:34:16.67#ibcon#about to read 3, iclass 27, count 2 2006.173.16:34:16.69#ibcon#read 3, iclass 27, count 2 2006.173.16:34:16.69#ibcon#about to read 4, iclass 27, count 2 2006.173.16:34:16.69#ibcon#read 4, iclass 27, count 2 2006.173.16:34:16.69#ibcon#about to read 5, iclass 27, count 2 2006.173.16:34:16.69#ibcon#read 5, iclass 27, count 2 2006.173.16:34:16.69#ibcon#about to read 6, iclass 27, count 2 2006.173.16:34:16.69#ibcon#read 6, iclass 27, count 2 2006.173.16:34:16.69#ibcon#end of sib2, iclass 27, count 2 2006.173.16:34:16.69#ibcon#*mode == 0, iclass 27, count 2 2006.173.16:34:16.69#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.16:34:16.69#ibcon#[25=AT08-04\r\n] 2006.173.16:34:16.69#ibcon#*before write, iclass 27, count 2 2006.173.16:34:16.69#ibcon#enter sib2, iclass 27, count 2 2006.173.16:34:16.69#ibcon#flushed, iclass 27, count 2 2006.173.16:34:16.69#ibcon#about to write, iclass 27, count 2 2006.173.16:34:16.69#ibcon#wrote, iclass 27, count 2 2006.173.16:34:16.69#ibcon#about to read 3, iclass 27, count 2 2006.173.16:34:16.72#ibcon#read 3, iclass 27, count 2 2006.173.16:34:16.72#ibcon#about to read 4, iclass 27, count 2 2006.173.16:34:16.72#ibcon#read 4, iclass 27, count 2 2006.173.16:34:16.72#ibcon#about to read 5, iclass 27, count 2 2006.173.16:34:16.72#ibcon#read 5, iclass 27, count 2 2006.173.16:34:16.72#ibcon#about to read 6, iclass 27, count 2 2006.173.16:34:16.72#ibcon#read 6, iclass 27, count 2 2006.173.16:34:16.72#ibcon#end of sib2, iclass 27, count 2 2006.173.16:34:16.72#ibcon#*after write, iclass 27, count 2 2006.173.16:34:16.72#ibcon#*before return 0, iclass 27, count 2 2006.173.16:34:16.72#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.16:34:16.72#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.16:34:16.72#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.16:34:16.72#ibcon#ireg 7 cls_cnt 0 2006.173.16:34:16.72#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.16:34:16.84#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.16:34:16.84#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.16:34:16.84#ibcon#enter wrdev, iclass 27, count 0 2006.173.16:34:16.84#ibcon#first serial, iclass 27, count 0 2006.173.16:34:16.84#ibcon#enter sib2, iclass 27, count 0 2006.173.16:34:16.84#ibcon#flushed, iclass 27, count 0 2006.173.16:34:16.84#ibcon#about to write, iclass 27, count 0 2006.173.16:34:16.84#ibcon#wrote, iclass 27, count 0 2006.173.16:34:16.84#ibcon#about to read 3, iclass 27, count 0 2006.173.16:34:16.86#ibcon#read 3, iclass 27, count 0 2006.173.16:34:16.86#ibcon#about to read 4, iclass 27, count 0 2006.173.16:34:16.86#ibcon#read 4, iclass 27, count 0 2006.173.16:34:16.86#ibcon#about to read 5, iclass 27, count 0 2006.173.16:34:16.86#ibcon#read 5, iclass 27, count 0 2006.173.16:34:16.86#ibcon#about to read 6, iclass 27, count 0 2006.173.16:34:16.86#ibcon#read 6, iclass 27, count 0 2006.173.16:34:16.86#ibcon#end of sib2, iclass 27, count 0 2006.173.16:34:16.86#ibcon#*mode == 0, iclass 27, count 0 2006.173.16:34:16.86#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.16:34:16.86#ibcon#[25=USB\r\n] 2006.173.16:34:16.86#ibcon#*before write, iclass 27, count 0 2006.173.16:34:16.86#ibcon#enter sib2, iclass 27, count 0 2006.173.16:34:16.86#ibcon#flushed, iclass 27, count 0 2006.173.16:34:16.86#ibcon#about to write, iclass 27, count 0 2006.173.16:34:16.86#ibcon#wrote, iclass 27, count 0 2006.173.16:34:16.86#ibcon#about to read 3, iclass 27, count 0 2006.173.16:34:16.89#ibcon#read 3, iclass 27, count 0 2006.173.16:34:16.89#ibcon#about to read 4, iclass 27, count 0 2006.173.16:34:16.89#ibcon#read 4, iclass 27, count 0 2006.173.16:34:16.89#ibcon#about to read 5, iclass 27, count 0 2006.173.16:34:16.89#ibcon#read 5, iclass 27, count 0 2006.173.16:34:16.89#ibcon#about to read 6, iclass 27, count 0 2006.173.16:34:16.89#ibcon#read 6, iclass 27, count 0 2006.173.16:34:16.89#ibcon#end of sib2, iclass 27, count 0 2006.173.16:34:16.89#ibcon#*after write, iclass 27, count 0 2006.173.16:34:16.89#ibcon#*before return 0, iclass 27, count 0 2006.173.16:34:16.89#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.16:34:16.89#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.16:34:16.89#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.16:34:16.89#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.16:34:16.89$vck44/vblo=1,629.99 2006.173.16:34:16.89#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.16:34:16.89#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.16:34:16.89#ibcon#ireg 17 cls_cnt 0 2006.173.16:34:16.89#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.16:34:16.89#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.16:34:16.89#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.16:34:16.89#ibcon#enter wrdev, iclass 29, count 0 2006.173.16:34:16.89#ibcon#first serial, iclass 29, count 0 2006.173.16:34:16.89#ibcon#enter sib2, iclass 29, count 0 2006.173.16:34:16.89#ibcon#flushed, iclass 29, count 0 2006.173.16:34:16.89#ibcon#about to write, iclass 29, count 0 2006.173.16:34:16.89#ibcon#wrote, iclass 29, count 0 2006.173.16:34:16.89#ibcon#about to read 3, iclass 29, count 0 2006.173.16:34:16.91#ibcon#read 3, iclass 29, count 0 2006.173.16:34:16.91#ibcon#about to read 4, iclass 29, count 0 2006.173.16:34:16.91#ibcon#read 4, iclass 29, count 0 2006.173.16:34:16.91#ibcon#about to read 5, iclass 29, count 0 2006.173.16:34:16.91#ibcon#read 5, iclass 29, count 0 2006.173.16:34:16.91#ibcon#about to read 6, iclass 29, count 0 2006.173.16:34:16.91#ibcon#read 6, iclass 29, count 0 2006.173.16:34:16.91#ibcon#end of sib2, iclass 29, count 0 2006.173.16:34:16.91#ibcon#*mode == 0, iclass 29, count 0 2006.173.16:34:16.91#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.16:34:16.91#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.16:34:16.91#ibcon#*before write, iclass 29, count 0 2006.173.16:34:16.91#ibcon#enter sib2, iclass 29, count 0 2006.173.16:34:16.91#ibcon#flushed, iclass 29, count 0 2006.173.16:34:16.91#ibcon#about to write, iclass 29, count 0 2006.173.16:34:16.91#ibcon#wrote, iclass 29, count 0 2006.173.16:34:16.91#ibcon#about to read 3, iclass 29, count 0 2006.173.16:34:16.95#ibcon#read 3, iclass 29, count 0 2006.173.16:34:16.95#ibcon#about to read 4, iclass 29, count 0 2006.173.16:34:16.95#ibcon#read 4, iclass 29, count 0 2006.173.16:34:16.95#ibcon#about to read 5, iclass 29, count 0 2006.173.16:34:16.95#ibcon#read 5, iclass 29, count 0 2006.173.16:34:16.95#ibcon#about to read 6, iclass 29, count 0 2006.173.16:34:16.95#ibcon#read 6, iclass 29, count 0 2006.173.16:34:16.95#ibcon#end of sib2, iclass 29, count 0 2006.173.16:34:16.95#ibcon#*after write, iclass 29, count 0 2006.173.16:34:16.95#ibcon#*before return 0, iclass 29, count 0 2006.173.16:34:16.95#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.16:34:16.95#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.16:34:16.95#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.16:34:16.95#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.16:34:16.95$vck44/vb=1,4 2006.173.16:34:16.95#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.16:34:16.95#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.16:34:16.95#ibcon#ireg 11 cls_cnt 2 2006.173.16:34:16.95#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.16:34:16.95#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.16:34:16.95#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.16:34:16.95#ibcon#enter wrdev, iclass 31, count 2 2006.173.16:34:16.95#ibcon#first serial, iclass 31, count 2 2006.173.16:34:16.95#ibcon#enter sib2, iclass 31, count 2 2006.173.16:34:16.95#ibcon#flushed, iclass 31, count 2 2006.173.16:34:16.95#ibcon#about to write, iclass 31, count 2 2006.173.16:34:16.95#ibcon#wrote, iclass 31, count 2 2006.173.16:34:16.95#ibcon#about to read 3, iclass 31, count 2 2006.173.16:34:16.97#ibcon#read 3, iclass 31, count 2 2006.173.16:34:16.97#ibcon#about to read 4, iclass 31, count 2 2006.173.16:34:16.97#ibcon#read 4, iclass 31, count 2 2006.173.16:34:16.97#ibcon#about to read 5, iclass 31, count 2 2006.173.16:34:16.97#ibcon#read 5, iclass 31, count 2 2006.173.16:34:16.97#ibcon#about to read 6, iclass 31, count 2 2006.173.16:34:16.97#ibcon#read 6, iclass 31, count 2 2006.173.16:34:16.97#ibcon#end of sib2, iclass 31, count 2 2006.173.16:34:16.97#ibcon#*mode == 0, iclass 31, count 2 2006.173.16:34:16.97#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.16:34:16.97#ibcon#[27=AT01-04\r\n] 2006.173.16:34:16.97#ibcon#*before write, iclass 31, count 2 2006.173.16:34:16.97#ibcon#enter sib2, iclass 31, count 2 2006.173.16:34:16.97#ibcon#flushed, iclass 31, count 2 2006.173.16:34:16.97#ibcon#about to write, iclass 31, count 2 2006.173.16:34:16.97#ibcon#wrote, iclass 31, count 2 2006.173.16:34:16.97#ibcon#about to read 3, iclass 31, count 2 2006.173.16:34:17.00#ibcon#read 3, iclass 31, count 2 2006.173.16:34:17.00#ibcon#about to read 4, iclass 31, count 2 2006.173.16:34:17.00#ibcon#read 4, iclass 31, count 2 2006.173.16:34:17.00#ibcon#about to read 5, iclass 31, count 2 2006.173.16:34:17.00#ibcon#read 5, iclass 31, count 2 2006.173.16:34:17.00#ibcon#about to read 6, iclass 31, count 2 2006.173.16:34:17.00#ibcon#read 6, iclass 31, count 2 2006.173.16:34:17.00#ibcon#end of sib2, iclass 31, count 2 2006.173.16:34:17.00#ibcon#*after write, iclass 31, count 2 2006.173.16:34:17.00#ibcon#*before return 0, iclass 31, count 2 2006.173.16:34:17.00#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.16:34:17.00#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.16:34:17.00#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.16:34:17.00#ibcon#ireg 7 cls_cnt 0 2006.173.16:34:17.00#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.16:34:17.12#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.16:34:17.12#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.16:34:17.12#ibcon#enter wrdev, iclass 31, count 0 2006.173.16:34:17.12#ibcon#first serial, iclass 31, count 0 2006.173.16:34:17.12#ibcon#enter sib2, iclass 31, count 0 2006.173.16:34:17.12#ibcon#flushed, iclass 31, count 0 2006.173.16:34:17.12#ibcon#about to write, iclass 31, count 0 2006.173.16:34:17.12#ibcon#wrote, iclass 31, count 0 2006.173.16:34:17.12#ibcon#about to read 3, iclass 31, count 0 2006.173.16:34:17.14#ibcon#read 3, iclass 31, count 0 2006.173.16:34:17.14#ibcon#about to read 4, iclass 31, count 0 2006.173.16:34:17.14#ibcon#read 4, iclass 31, count 0 2006.173.16:34:17.14#ibcon#about to read 5, iclass 31, count 0 2006.173.16:34:17.14#ibcon#read 5, iclass 31, count 0 2006.173.16:34:17.14#ibcon#about to read 6, iclass 31, count 0 2006.173.16:34:17.14#ibcon#read 6, iclass 31, count 0 2006.173.16:34:17.14#ibcon#end of sib2, iclass 31, count 0 2006.173.16:34:17.14#ibcon#*mode == 0, iclass 31, count 0 2006.173.16:34:17.14#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.16:34:17.14#ibcon#[27=USB\r\n] 2006.173.16:34:17.14#ibcon#*before write, iclass 31, count 0 2006.173.16:34:17.14#ibcon#enter sib2, iclass 31, count 0 2006.173.16:34:17.14#ibcon#flushed, iclass 31, count 0 2006.173.16:34:17.14#ibcon#about to write, iclass 31, count 0 2006.173.16:34:17.14#ibcon#wrote, iclass 31, count 0 2006.173.16:34:17.14#ibcon#about to read 3, iclass 31, count 0 2006.173.16:34:17.17#ibcon#read 3, iclass 31, count 0 2006.173.16:34:17.17#ibcon#about to read 4, iclass 31, count 0 2006.173.16:34:17.17#ibcon#read 4, iclass 31, count 0 2006.173.16:34:17.17#ibcon#about to read 5, iclass 31, count 0 2006.173.16:34:17.17#ibcon#read 5, iclass 31, count 0 2006.173.16:34:17.17#ibcon#about to read 6, iclass 31, count 0 2006.173.16:34:17.17#ibcon#read 6, iclass 31, count 0 2006.173.16:34:17.17#ibcon#end of sib2, iclass 31, count 0 2006.173.16:34:17.17#ibcon#*after write, iclass 31, count 0 2006.173.16:34:17.17#ibcon#*before return 0, iclass 31, count 0 2006.173.16:34:17.17#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.16:34:17.17#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.16:34:17.17#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.16:34:17.17#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.16:34:17.17$vck44/vblo=2,634.99 2006.173.16:34:17.17#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.16:34:17.17#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.16:34:17.17#ibcon#ireg 17 cls_cnt 0 2006.173.16:34:17.17#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.16:34:17.17#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.16:34:17.17#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.16:34:17.17#ibcon#enter wrdev, iclass 33, count 0 2006.173.16:34:17.17#ibcon#first serial, iclass 33, count 0 2006.173.16:34:17.17#ibcon#enter sib2, iclass 33, count 0 2006.173.16:34:17.17#ibcon#flushed, iclass 33, count 0 2006.173.16:34:17.17#ibcon#about to write, iclass 33, count 0 2006.173.16:34:17.17#ibcon#wrote, iclass 33, count 0 2006.173.16:34:17.17#ibcon#about to read 3, iclass 33, count 0 2006.173.16:34:17.19#ibcon#read 3, iclass 33, count 0 2006.173.16:34:17.19#ibcon#about to read 4, iclass 33, count 0 2006.173.16:34:17.19#ibcon#read 4, iclass 33, count 0 2006.173.16:34:17.19#ibcon#about to read 5, iclass 33, count 0 2006.173.16:34:17.19#ibcon#read 5, iclass 33, count 0 2006.173.16:34:17.19#ibcon#about to read 6, iclass 33, count 0 2006.173.16:34:17.19#ibcon#read 6, iclass 33, count 0 2006.173.16:34:17.19#ibcon#end of sib2, iclass 33, count 0 2006.173.16:34:17.19#ibcon#*mode == 0, iclass 33, count 0 2006.173.16:34:17.19#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.16:34:17.19#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.16:34:17.19#ibcon#*before write, iclass 33, count 0 2006.173.16:34:17.19#ibcon#enter sib2, iclass 33, count 0 2006.173.16:34:17.19#ibcon#flushed, iclass 33, count 0 2006.173.16:34:17.19#ibcon#about to write, iclass 33, count 0 2006.173.16:34:17.19#ibcon#wrote, iclass 33, count 0 2006.173.16:34:17.19#ibcon#about to read 3, iclass 33, count 0 2006.173.16:34:17.23#ibcon#read 3, iclass 33, count 0 2006.173.16:34:17.23#ibcon#about to read 4, iclass 33, count 0 2006.173.16:34:17.23#ibcon#read 4, iclass 33, count 0 2006.173.16:34:17.23#ibcon#about to read 5, iclass 33, count 0 2006.173.16:34:17.23#ibcon#read 5, iclass 33, count 0 2006.173.16:34:17.23#ibcon#about to read 6, iclass 33, count 0 2006.173.16:34:17.23#ibcon#read 6, iclass 33, count 0 2006.173.16:34:17.23#ibcon#end of sib2, iclass 33, count 0 2006.173.16:34:17.23#ibcon#*after write, iclass 33, count 0 2006.173.16:34:17.23#ibcon#*before return 0, iclass 33, count 0 2006.173.16:34:17.23#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.16:34:17.23#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.16:34:17.23#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.16:34:17.23#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.16:34:17.23$vck44/vb=2,4 2006.173.16:34:17.23#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.16:34:17.23#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.16:34:17.23#ibcon#ireg 11 cls_cnt 2 2006.173.16:34:17.23#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.16:34:17.29#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.16:34:17.29#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.16:34:17.29#ibcon#enter wrdev, iclass 35, count 2 2006.173.16:34:17.29#ibcon#first serial, iclass 35, count 2 2006.173.16:34:17.29#ibcon#enter sib2, iclass 35, count 2 2006.173.16:34:17.29#ibcon#flushed, iclass 35, count 2 2006.173.16:34:17.29#ibcon#about to write, iclass 35, count 2 2006.173.16:34:17.29#ibcon#wrote, iclass 35, count 2 2006.173.16:34:17.29#ibcon#about to read 3, iclass 35, count 2 2006.173.16:34:17.31#ibcon#read 3, iclass 35, count 2 2006.173.16:34:17.31#ibcon#about to read 4, iclass 35, count 2 2006.173.16:34:17.31#ibcon#read 4, iclass 35, count 2 2006.173.16:34:17.31#ibcon#about to read 5, iclass 35, count 2 2006.173.16:34:17.31#ibcon#read 5, iclass 35, count 2 2006.173.16:34:17.31#ibcon#about to read 6, iclass 35, count 2 2006.173.16:34:17.31#ibcon#read 6, iclass 35, count 2 2006.173.16:34:17.31#ibcon#end of sib2, iclass 35, count 2 2006.173.16:34:17.31#ibcon#*mode == 0, iclass 35, count 2 2006.173.16:34:17.31#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.16:34:17.31#ibcon#[27=AT02-04\r\n] 2006.173.16:34:17.31#ibcon#*before write, iclass 35, count 2 2006.173.16:34:17.31#ibcon#enter sib2, iclass 35, count 2 2006.173.16:34:17.31#ibcon#flushed, iclass 35, count 2 2006.173.16:34:17.31#ibcon#about to write, iclass 35, count 2 2006.173.16:34:17.31#ibcon#wrote, iclass 35, count 2 2006.173.16:34:17.31#ibcon#about to read 3, iclass 35, count 2 2006.173.16:34:17.34#ibcon#read 3, iclass 35, count 2 2006.173.16:34:17.34#ibcon#about to read 4, iclass 35, count 2 2006.173.16:34:17.34#ibcon#read 4, iclass 35, count 2 2006.173.16:34:17.34#ibcon#about to read 5, iclass 35, count 2 2006.173.16:34:17.34#ibcon#read 5, iclass 35, count 2 2006.173.16:34:17.34#ibcon#about to read 6, iclass 35, count 2 2006.173.16:34:17.34#ibcon#read 6, iclass 35, count 2 2006.173.16:34:17.34#ibcon#end of sib2, iclass 35, count 2 2006.173.16:34:17.34#ibcon#*after write, iclass 35, count 2 2006.173.16:34:17.34#ibcon#*before return 0, iclass 35, count 2 2006.173.16:34:17.34#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.16:34:17.34#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.16:34:17.34#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.16:34:17.34#ibcon#ireg 7 cls_cnt 0 2006.173.16:34:17.34#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.16:34:17.46#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.16:34:17.46#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.16:34:17.46#ibcon#enter wrdev, iclass 35, count 0 2006.173.16:34:17.46#ibcon#first serial, iclass 35, count 0 2006.173.16:34:17.46#ibcon#enter sib2, iclass 35, count 0 2006.173.16:34:17.46#ibcon#flushed, iclass 35, count 0 2006.173.16:34:17.46#ibcon#about to write, iclass 35, count 0 2006.173.16:34:17.46#ibcon#wrote, iclass 35, count 0 2006.173.16:34:17.46#ibcon#about to read 3, iclass 35, count 0 2006.173.16:34:17.48#ibcon#read 3, iclass 35, count 0 2006.173.16:34:17.48#ibcon#about to read 4, iclass 35, count 0 2006.173.16:34:17.48#ibcon#read 4, iclass 35, count 0 2006.173.16:34:17.48#ibcon#about to read 5, iclass 35, count 0 2006.173.16:34:17.48#ibcon#read 5, iclass 35, count 0 2006.173.16:34:17.48#ibcon#about to read 6, iclass 35, count 0 2006.173.16:34:17.48#ibcon#read 6, iclass 35, count 0 2006.173.16:34:17.48#ibcon#end of sib2, iclass 35, count 0 2006.173.16:34:17.48#ibcon#*mode == 0, iclass 35, count 0 2006.173.16:34:17.48#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.16:34:17.48#ibcon#[27=USB\r\n] 2006.173.16:34:17.48#ibcon#*before write, iclass 35, count 0 2006.173.16:34:17.48#ibcon#enter sib2, iclass 35, count 0 2006.173.16:34:17.48#ibcon#flushed, iclass 35, count 0 2006.173.16:34:17.48#ibcon#about to write, iclass 35, count 0 2006.173.16:34:17.48#ibcon#wrote, iclass 35, count 0 2006.173.16:34:17.48#ibcon#about to read 3, iclass 35, count 0 2006.173.16:34:17.51#ibcon#read 3, iclass 35, count 0 2006.173.16:34:17.51#ibcon#about to read 4, iclass 35, count 0 2006.173.16:34:17.51#ibcon#read 4, iclass 35, count 0 2006.173.16:34:17.51#ibcon#about to read 5, iclass 35, count 0 2006.173.16:34:17.51#ibcon#read 5, iclass 35, count 0 2006.173.16:34:17.51#ibcon#about to read 6, iclass 35, count 0 2006.173.16:34:17.51#ibcon#read 6, iclass 35, count 0 2006.173.16:34:17.51#ibcon#end of sib2, iclass 35, count 0 2006.173.16:34:17.51#ibcon#*after write, iclass 35, count 0 2006.173.16:34:17.51#ibcon#*before return 0, iclass 35, count 0 2006.173.16:34:17.51#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.16:34:17.51#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.16:34:17.51#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.16:34:17.51#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.16:34:17.51$vck44/vblo=3,649.99 2006.173.16:34:17.51#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.16:34:17.51#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.16:34:17.51#ibcon#ireg 17 cls_cnt 0 2006.173.16:34:17.51#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.16:34:17.51#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.16:34:17.51#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.16:34:17.51#ibcon#enter wrdev, iclass 37, count 0 2006.173.16:34:17.51#ibcon#first serial, iclass 37, count 0 2006.173.16:34:17.51#ibcon#enter sib2, iclass 37, count 0 2006.173.16:34:17.51#ibcon#flushed, iclass 37, count 0 2006.173.16:34:17.51#ibcon#about to write, iclass 37, count 0 2006.173.16:34:17.51#ibcon#wrote, iclass 37, count 0 2006.173.16:34:17.51#ibcon#about to read 3, iclass 37, count 0 2006.173.16:34:17.53#ibcon#read 3, iclass 37, count 0 2006.173.16:34:17.53#ibcon#about to read 4, iclass 37, count 0 2006.173.16:34:17.53#ibcon#read 4, iclass 37, count 0 2006.173.16:34:17.53#ibcon#about to read 5, iclass 37, count 0 2006.173.16:34:17.53#ibcon#read 5, iclass 37, count 0 2006.173.16:34:17.53#ibcon#about to read 6, iclass 37, count 0 2006.173.16:34:17.53#ibcon#read 6, iclass 37, count 0 2006.173.16:34:17.53#ibcon#end of sib2, iclass 37, count 0 2006.173.16:34:17.53#ibcon#*mode == 0, iclass 37, count 0 2006.173.16:34:17.53#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.16:34:17.53#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.16:34:17.53#ibcon#*before write, iclass 37, count 0 2006.173.16:34:17.53#ibcon#enter sib2, iclass 37, count 0 2006.173.16:34:17.53#ibcon#flushed, iclass 37, count 0 2006.173.16:34:17.53#ibcon#about to write, iclass 37, count 0 2006.173.16:34:17.53#ibcon#wrote, iclass 37, count 0 2006.173.16:34:17.53#ibcon#about to read 3, iclass 37, count 0 2006.173.16:34:17.57#ibcon#read 3, iclass 37, count 0 2006.173.16:34:17.57#ibcon#about to read 4, iclass 37, count 0 2006.173.16:34:17.57#ibcon#read 4, iclass 37, count 0 2006.173.16:34:17.57#ibcon#about to read 5, iclass 37, count 0 2006.173.16:34:17.57#ibcon#read 5, iclass 37, count 0 2006.173.16:34:17.57#ibcon#about to read 6, iclass 37, count 0 2006.173.16:34:17.57#ibcon#read 6, iclass 37, count 0 2006.173.16:34:17.57#ibcon#end of sib2, iclass 37, count 0 2006.173.16:34:17.57#ibcon#*after write, iclass 37, count 0 2006.173.16:34:17.57#ibcon#*before return 0, iclass 37, count 0 2006.173.16:34:17.57#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.16:34:17.57#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.16:34:17.57#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.16:34:17.57#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.16:34:17.57$vck44/vb=3,4 2006.173.16:34:17.57#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.16:34:17.57#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.16:34:17.57#ibcon#ireg 11 cls_cnt 2 2006.173.16:34:17.57#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.16:34:17.63#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.16:34:17.63#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.16:34:17.63#ibcon#enter wrdev, iclass 39, count 2 2006.173.16:34:17.63#ibcon#first serial, iclass 39, count 2 2006.173.16:34:17.63#ibcon#enter sib2, iclass 39, count 2 2006.173.16:34:17.63#ibcon#flushed, iclass 39, count 2 2006.173.16:34:17.63#ibcon#about to write, iclass 39, count 2 2006.173.16:34:17.63#ibcon#wrote, iclass 39, count 2 2006.173.16:34:17.63#ibcon#about to read 3, iclass 39, count 2 2006.173.16:34:17.65#ibcon#read 3, iclass 39, count 2 2006.173.16:34:17.65#ibcon#about to read 4, iclass 39, count 2 2006.173.16:34:17.65#ibcon#read 4, iclass 39, count 2 2006.173.16:34:17.65#ibcon#about to read 5, iclass 39, count 2 2006.173.16:34:17.65#ibcon#read 5, iclass 39, count 2 2006.173.16:34:17.65#ibcon#about to read 6, iclass 39, count 2 2006.173.16:34:17.65#ibcon#read 6, iclass 39, count 2 2006.173.16:34:17.65#ibcon#end of sib2, iclass 39, count 2 2006.173.16:34:17.65#ibcon#*mode == 0, iclass 39, count 2 2006.173.16:34:17.65#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.16:34:17.65#ibcon#[27=AT03-04\r\n] 2006.173.16:34:17.65#ibcon#*before write, iclass 39, count 2 2006.173.16:34:17.65#ibcon#enter sib2, iclass 39, count 2 2006.173.16:34:17.65#ibcon#flushed, iclass 39, count 2 2006.173.16:34:17.65#ibcon#about to write, iclass 39, count 2 2006.173.16:34:17.65#ibcon#wrote, iclass 39, count 2 2006.173.16:34:17.65#ibcon#about to read 3, iclass 39, count 2 2006.173.16:34:17.68#ibcon#read 3, iclass 39, count 2 2006.173.16:34:17.68#ibcon#about to read 4, iclass 39, count 2 2006.173.16:34:17.68#ibcon#read 4, iclass 39, count 2 2006.173.16:34:17.68#ibcon#about to read 5, iclass 39, count 2 2006.173.16:34:17.68#ibcon#read 5, iclass 39, count 2 2006.173.16:34:17.68#ibcon#about to read 6, iclass 39, count 2 2006.173.16:34:17.68#ibcon#read 6, iclass 39, count 2 2006.173.16:34:17.68#ibcon#end of sib2, iclass 39, count 2 2006.173.16:34:17.68#ibcon#*after write, iclass 39, count 2 2006.173.16:34:17.68#ibcon#*before return 0, iclass 39, count 2 2006.173.16:34:17.68#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.16:34:17.68#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.16:34:17.68#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.16:34:17.68#ibcon#ireg 7 cls_cnt 0 2006.173.16:34:17.68#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.16:34:17.80#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.16:34:17.80#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.16:34:17.80#ibcon#enter wrdev, iclass 39, count 0 2006.173.16:34:17.80#ibcon#first serial, iclass 39, count 0 2006.173.16:34:17.80#ibcon#enter sib2, iclass 39, count 0 2006.173.16:34:17.80#ibcon#flushed, iclass 39, count 0 2006.173.16:34:17.80#ibcon#about to write, iclass 39, count 0 2006.173.16:34:17.80#ibcon#wrote, iclass 39, count 0 2006.173.16:34:17.80#ibcon#about to read 3, iclass 39, count 0 2006.173.16:34:17.82#ibcon#read 3, iclass 39, count 0 2006.173.16:34:17.82#ibcon#about to read 4, iclass 39, count 0 2006.173.16:34:17.82#ibcon#read 4, iclass 39, count 0 2006.173.16:34:17.82#ibcon#about to read 5, iclass 39, count 0 2006.173.16:34:17.82#ibcon#read 5, iclass 39, count 0 2006.173.16:34:17.82#ibcon#about to read 6, iclass 39, count 0 2006.173.16:34:17.82#ibcon#read 6, iclass 39, count 0 2006.173.16:34:17.82#ibcon#end of sib2, iclass 39, count 0 2006.173.16:34:17.82#ibcon#*mode == 0, iclass 39, count 0 2006.173.16:34:17.82#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.16:34:17.82#ibcon#[27=USB\r\n] 2006.173.16:34:17.82#ibcon#*before write, iclass 39, count 0 2006.173.16:34:17.82#ibcon#enter sib2, iclass 39, count 0 2006.173.16:34:17.82#ibcon#flushed, iclass 39, count 0 2006.173.16:34:17.82#ibcon#about to write, iclass 39, count 0 2006.173.16:34:17.82#ibcon#wrote, iclass 39, count 0 2006.173.16:34:17.82#ibcon#about to read 3, iclass 39, count 0 2006.173.16:34:17.85#ibcon#read 3, iclass 39, count 0 2006.173.16:34:17.85#ibcon#about to read 4, iclass 39, count 0 2006.173.16:34:17.85#ibcon#read 4, iclass 39, count 0 2006.173.16:34:17.85#ibcon#about to read 5, iclass 39, count 0 2006.173.16:34:17.85#ibcon#read 5, iclass 39, count 0 2006.173.16:34:17.85#ibcon#about to read 6, iclass 39, count 0 2006.173.16:34:17.85#ibcon#read 6, iclass 39, count 0 2006.173.16:34:17.85#ibcon#end of sib2, iclass 39, count 0 2006.173.16:34:17.85#ibcon#*after write, iclass 39, count 0 2006.173.16:34:17.85#ibcon#*before return 0, iclass 39, count 0 2006.173.16:34:17.85#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.16:34:17.85#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.16:34:17.85#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.16:34:17.85#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.16:34:17.85$vck44/vblo=4,679.99 2006.173.16:34:17.85#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.16:34:17.85#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.16:34:17.85#ibcon#ireg 17 cls_cnt 0 2006.173.16:34:17.85#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.16:34:17.85#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.16:34:17.85#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.16:34:17.85#ibcon#enter wrdev, iclass 3, count 0 2006.173.16:34:17.85#ibcon#first serial, iclass 3, count 0 2006.173.16:34:17.85#ibcon#enter sib2, iclass 3, count 0 2006.173.16:34:17.85#ibcon#flushed, iclass 3, count 0 2006.173.16:34:17.85#ibcon#about to write, iclass 3, count 0 2006.173.16:34:17.85#ibcon#wrote, iclass 3, count 0 2006.173.16:34:17.85#ibcon#about to read 3, iclass 3, count 0 2006.173.16:34:17.87#ibcon#read 3, iclass 3, count 0 2006.173.16:34:17.87#ibcon#about to read 4, iclass 3, count 0 2006.173.16:34:17.87#ibcon#read 4, iclass 3, count 0 2006.173.16:34:17.87#ibcon#about to read 5, iclass 3, count 0 2006.173.16:34:17.87#ibcon#read 5, iclass 3, count 0 2006.173.16:34:17.87#ibcon#about to read 6, iclass 3, count 0 2006.173.16:34:17.87#ibcon#read 6, iclass 3, count 0 2006.173.16:34:17.87#ibcon#end of sib2, iclass 3, count 0 2006.173.16:34:17.87#ibcon#*mode == 0, iclass 3, count 0 2006.173.16:34:17.87#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.16:34:17.87#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.16:34:17.87#ibcon#*before write, iclass 3, count 0 2006.173.16:34:17.87#ibcon#enter sib2, iclass 3, count 0 2006.173.16:34:17.87#ibcon#flushed, iclass 3, count 0 2006.173.16:34:17.87#ibcon#about to write, iclass 3, count 0 2006.173.16:34:17.87#ibcon#wrote, iclass 3, count 0 2006.173.16:34:17.87#ibcon#about to read 3, iclass 3, count 0 2006.173.16:34:17.91#ibcon#read 3, iclass 3, count 0 2006.173.16:34:17.91#ibcon#about to read 4, iclass 3, count 0 2006.173.16:34:17.91#ibcon#read 4, iclass 3, count 0 2006.173.16:34:17.91#ibcon#about to read 5, iclass 3, count 0 2006.173.16:34:17.91#ibcon#read 5, iclass 3, count 0 2006.173.16:34:17.91#ibcon#about to read 6, iclass 3, count 0 2006.173.16:34:17.91#ibcon#read 6, iclass 3, count 0 2006.173.16:34:17.91#ibcon#end of sib2, iclass 3, count 0 2006.173.16:34:17.91#ibcon#*after write, iclass 3, count 0 2006.173.16:34:17.91#ibcon#*before return 0, iclass 3, count 0 2006.173.16:34:17.91#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.16:34:17.91#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.16:34:17.91#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.16:34:17.91#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.16:34:17.91$vck44/vb=4,4 2006.173.16:34:17.91#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.16:34:17.91#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.16:34:17.91#ibcon#ireg 11 cls_cnt 2 2006.173.16:34:17.91#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.16:34:17.97#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.16:34:17.97#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.16:34:17.97#ibcon#enter wrdev, iclass 5, count 2 2006.173.16:34:17.97#ibcon#first serial, iclass 5, count 2 2006.173.16:34:17.97#ibcon#enter sib2, iclass 5, count 2 2006.173.16:34:17.97#ibcon#flushed, iclass 5, count 2 2006.173.16:34:17.97#ibcon#about to write, iclass 5, count 2 2006.173.16:34:17.97#ibcon#wrote, iclass 5, count 2 2006.173.16:34:17.97#ibcon#about to read 3, iclass 5, count 2 2006.173.16:34:17.99#ibcon#read 3, iclass 5, count 2 2006.173.16:34:17.99#ibcon#about to read 4, iclass 5, count 2 2006.173.16:34:17.99#ibcon#read 4, iclass 5, count 2 2006.173.16:34:17.99#ibcon#about to read 5, iclass 5, count 2 2006.173.16:34:17.99#ibcon#read 5, iclass 5, count 2 2006.173.16:34:17.99#ibcon#about to read 6, iclass 5, count 2 2006.173.16:34:17.99#ibcon#read 6, iclass 5, count 2 2006.173.16:34:17.99#ibcon#end of sib2, iclass 5, count 2 2006.173.16:34:17.99#ibcon#*mode == 0, iclass 5, count 2 2006.173.16:34:17.99#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.16:34:17.99#ibcon#[27=AT04-04\r\n] 2006.173.16:34:17.99#ibcon#*before write, iclass 5, count 2 2006.173.16:34:17.99#ibcon#enter sib2, iclass 5, count 2 2006.173.16:34:17.99#ibcon#flushed, iclass 5, count 2 2006.173.16:34:17.99#ibcon#about to write, iclass 5, count 2 2006.173.16:34:17.99#ibcon#wrote, iclass 5, count 2 2006.173.16:34:17.99#ibcon#about to read 3, iclass 5, count 2 2006.173.16:34:18.02#ibcon#read 3, iclass 5, count 2 2006.173.16:34:18.02#ibcon#about to read 4, iclass 5, count 2 2006.173.16:34:18.02#ibcon#read 4, iclass 5, count 2 2006.173.16:34:18.02#ibcon#about to read 5, iclass 5, count 2 2006.173.16:34:18.02#ibcon#read 5, iclass 5, count 2 2006.173.16:34:18.02#ibcon#about to read 6, iclass 5, count 2 2006.173.16:34:18.02#ibcon#read 6, iclass 5, count 2 2006.173.16:34:18.02#ibcon#end of sib2, iclass 5, count 2 2006.173.16:34:18.02#ibcon#*after write, iclass 5, count 2 2006.173.16:34:18.02#ibcon#*before return 0, iclass 5, count 2 2006.173.16:34:18.02#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.16:34:18.02#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.16:34:18.02#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.16:34:18.02#ibcon#ireg 7 cls_cnt 0 2006.173.16:34:18.02#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.16:34:18.14#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.16:34:18.14#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.16:34:18.14#ibcon#enter wrdev, iclass 5, count 0 2006.173.16:34:18.14#ibcon#first serial, iclass 5, count 0 2006.173.16:34:18.14#ibcon#enter sib2, iclass 5, count 0 2006.173.16:34:18.14#ibcon#flushed, iclass 5, count 0 2006.173.16:34:18.14#ibcon#about to write, iclass 5, count 0 2006.173.16:34:18.14#ibcon#wrote, iclass 5, count 0 2006.173.16:34:18.14#ibcon#about to read 3, iclass 5, count 0 2006.173.16:34:18.16#ibcon#read 3, iclass 5, count 0 2006.173.16:34:18.16#ibcon#about to read 4, iclass 5, count 0 2006.173.16:34:18.16#ibcon#read 4, iclass 5, count 0 2006.173.16:34:18.16#ibcon#about to read 5, iclass 5, count 0 2006.173.16:34:18.16#ibcon#read 5, iclass 5, count 0 2006.173.16:34:18.16#ibcon#about to read 6, iclass 5, count 0 2006.173.16:34:18.16#ibcon#read 6, iclass 5, count 0 2006.173.16:34:18.16#ibcon#end of sib2, iclass 5, count 0 2006.173.16:34:18.16#ibcon#*mode == 0, iclass 5, count 0 2006.173.16:34:18.16#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.16:34:18.16#ibcon#[27=USB\r\n] 2006.173.16:34:18.16#ibcon#*before write, iclass 5, count 0 2006.173.16:34:18.16#ibcon#enter sib2, iclass 5, count 0 2006.173.16:34:18.16#ibcon#flushed, iclass 5, count 0 2006.173.16:34:18.16#ibcon#about to write, iclass 5, count 0 2006.173.16:34:18.16#ibcon#wrote, iclass 5, count 0 2006.173.16:34:18.16#ibcon#about to read 3, iclass 5, count 0 2006.173.16:34:18.19#ibcon#read 3, iclass 5, count 0 2006.173.16:34:18.19#ibcon#about to read 4, iclass 5, count 0 2006.173.16:34:18.19#ibcon#read 4, iclass 5, count 0 2006.173.16:34:18.19#ibcon#about to read 5, iclass 5, count 0 2006.173.16:34:18.19#ibcon#read 5, iclass 5, count 0 2006.173.16:34:18.19#ibcon#about to read 6, iclass 5, count 0 2006.173.16:34:18.19#ibcon#read 6, iclass 5, count 0 2006.173.16:34:18.19#ibcon#end of sib2, iclass 5, count 0 2006.173.16:34:18.19#ibcon#*after write, iclass 5, count 0 2006.173.16:34:18.19#ibcon#*before return 0, iclass 5, count 0 2006.173.16:34:18.19#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.16:34:18.19#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.16:34:18.19#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.16:34:18.19#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.16:34:18.19$vck44/vblo=5,709.99 2006.173.16:34:18.19#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.16:34:18.19#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.16:34:18.19#ibcon#ireg 17 cls_cnt 0 2006.173.16:34:18.19#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.16:34:18.19#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.16:34:18.19#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.16:34:18.19#ibcon#enter wrdev, iclass 7, count 0 2006.173.16:34:18.19#ibcon#first serial, iclass 7, count 0 2006.173.16:34:18.19#ibcon#enter sib2, iclass 7, count 0 2006.173.16:34:18.19#ibcon#flushed, iclass 7, count 0 2006.173.16:34:18.19#ibcon#about to write, iclass 7, count 0 2006.173.16:34:18.19#ibcon#wrote, iclass 7, count 0 2006.173.16:34:18.19#ibcon#about to read 3, iclass 7, count 0 2006.173.16:34:18.21#ibcon#read 3, iclass 7, count 0 2006.173.16:34:18.21#ibcon#about to read 4, iclass 7, count 0 2006.173.16:34:18.21#ibcon#read 4, iclass 7, count 0 2006.173.16:34:18.21#ibcon#about to read 5, iclass 7, count 0 2006.173.16:34:18.21#ibcon#read 5, iclass 7, count 0 2006.173.16:34:18.21#ibcon#about to read 6, iclass 7, count 0 2006.173.16:34:18.21#ibcon#read 6, iclass 7, count 0 2006.173.16:34:18.21#ibcon#end of sib2, iclass 7, count 0 2006.173.16:34:18.21#ibcon#*mode == 0, iclass 7, count 0 2006.173.16:34:18.21#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.16:34:18.21#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.16:34:18.21#ibcon#*before write, iclass 7, count 0 2006.173.16:34:18.21#ibcon#enter sib2, iclass 7, count 0 2006.173.16:34:18.21#ibcon#flushed, iclass 7, count 0 2006.173.16:34:18.21#ibcon#about to write, iclass 7, count 0 2006.173.16:34:18.21#ibcon#wrote, iclass 7, count 0 2006.173.16:34:18.21#ibcon#about to read 3, iclass 7, count 0 2006.173.16:34:18.25#ibcon#read 3, iclass 7, count 0 2006.173.16:34:18.25#ibcon#about to read 4, iclass 7, count 0 2006.173.16:34:18.25#ibcon#read 4, iclass 7, count 0 2006.173.16:34:18.25#ibcon#about to read 5, iclass 7, count 0 2006.173.16:34:18.25#ibcon#read 5, iclass 7, count 0 2006.173.16:34:18.25#ibcon#about to read 6, iclass 7, count 0 2006.173.16:34:18.25#ibcon#read 6, iclass 7, count 0 2006.173.16:34:18.25#ibcon#end of sib2, iclass 7, count 0 2006.173.16:34:18.25#ibcon#*after write, iclass 7, count 0 2006.173.16:34:18.25#ibcon#*before return 0, iclass 7, count 0 2006.173.16:34:18.25#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.16:34:18.25#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.16:34:18.25#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.16:34:18.25#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.16:34:18.25$vck44/vb=5,4 2006.173.16:34:18.25#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.16:34:18.25#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.16:34:18.25#ibcon#ireg 11 cls_cnt 2 2006.173.16:34:18.25#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.16:34:18.31#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.16:34:18.31#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.16:34:18.31#ibcon#enter wrdev, iclass 11, count 2 2006.173.16:34:18.31#ibcon#first serial, iclass 11, count 2 2006.173.16:34:18.31#ibcon#enter sib2, iclass 11, count 2 2006.173.16:34:18.31#ibcon#flushed, iclass 11, count 2 2006.173.16:34:18.31#ibcon#about to write, iclass 11, count 2 2006.173.16:34:18.31#ibcon#wrote, iclass 11, count 2 2006.173.16:34:18.31#ibcon#about to read 3, iclass 11, count 2 2006.173.16:34:18.33#ibcon#read 3, iclass 11, count 2 2006.173.16:34:18.33#ibcon#about to read 4, iclass 11, count 2 2006.173.16:34:18.33#ibcon#read 4, iclass 11, count 2 2006.173.16:34:18.33#ibcon#about to read 5, iclass 11, count 2 2006.173.16:34:18.33#ibcon#read 5, iclass 11, count 2 2006.173.16:34:18.33#ibcon#about to read 6, iclass 11, count 2 2006.173.16:34:18.33#ibcon#read 6, iclass 11, count 2 2006.173.16:34:18.33#ibcon#end of sib2, iclass 11, count 2 2006.173.16:34:18.33#ibcon#*mode == 0, iclass 11, count 2 2006.173.16:34:18.33#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.16:34:18.33#ibcon#[27=AT05-04\r\n] 2006.173.16:34:18.33#ibcon#*before write, iclass 11, count 2 2006.173.16:34:18.33#ibcon#enter sib2, iclass 11, count 2 2006.173.16:34:18.33#ibcon#flushed, iclass 11, count 2 2006.173.16:34:18.33#ibcon#about to write, iclass 11, count 2 2006.173.16:34:18.33#ibcon#wrote, iclass 11, count 2 2006.173.16:34:18.33#ibcon#about to read 3, iclass 11, count 2 2006.173.16:34:18.36#ibcon#read 3, iclass 11, count 2 2006.173.16:34:18.36#ibcon#about to read 4, iclass 11, count 2 2006.173.16:34:18.36#ibcon#read 4, iclass 11, count 2 2006.173.16:34:18.36#ibcon#about to read 5, iclass 11, count 2 2006.173.16:34:18.36#ibcon#read 5, iclass 11, count 2 2006.173.16:34:18.36#ibcon#about to read 6, iclass 11, count 2 2006.173.16:34:18.36#ibcon#read 6, iclass 11, count 2 2006.173.16:34:18.36#ibcon#end of sib2, iclass 11, count 2 2006.173.16:34:18.36#ibcon#*after write, iclass 11, count 2 2006.173.16:34:18.36#ibcon#*before return 0, iclass 11, count 2 2006.173.16:34:18.36#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.16:34:18.36#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.16:34:18.36#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.16:34:18.36#ibcon#ireg 7 cls_cnt 0 2006.173.16:34:18.36#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.16:34:18.48#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.16:34:18.48#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.16:34:18.48#ibcon#enter wrdev, iclass 11, count 0 2006.173.16:34:18.48#ibcon#first serial, iclass 11, count 0 2006.173.16:34:18.48#ibcon#enter sib2, iclass 11, count 0 2006.173.16:34:18.48#ibcon#flushed, iclass 11, count 0 2006.173.16:34:18.48#ibcon#about to write, iclass 11, count 0 2006.173.16:34:18.48#ibcon#wrote, iclass 11, count 0 2006.173.16:34:18.48#ibcon#about to read 3, iclass 11, count 0 2006.173.16:34:18.50#ibcon#read 3, iclass 11, count 0 2006.173.16:34:18.50#ibcon#about to read 4, iclass 11, count 0 2006.173.16:34:18.50#ibcon#read 4, iclass 11, count 0 2006.173.16:34:18.50#ibcon#about to read 5, iclass 11, count 0 2006.173.16:34:18.50#ibcon#read 5, iclass 11, count 0 2006.173.16:34:18.50#ibcon#about to read 6, iclass 11, count 0 2006.173.16:34:18.50#ibcon#read 6, iclass 11, count 0 2006.173.16:34:18.50#ibcon#end of sib2, iclass 11, count 0 2006.173.16:34:18.50#ibcon#*mode == 0, iclass 11, count 0 2006.173.16:34:18.50#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.16:34:18.50#ibcon#[27=USB\r\n] 2006.173.16:34:18.50#ibcon#*before write, iclass 11, count 0 2006.173.16:34:18.50#ibcon#enter sib2, iclass 11, count 0 2006.173.16:34:18.50#ibcon#flushed, iclass 11, count 0 2006.173.16:34:18.50#ibcon#about to write, iclass 11, count 0 2006.173.16:34:18.50#ibcon#wrote, iclass 11, count 0 2006.173.16:34:18.50#ibcon#about to read 3, iclass 11, count 0 2006.173.16:34:18.53#ibcon#read 3, iclass 11, count 0 2006.173.16:34:18.53#ibcon#about to read 4, iclass 11, count 0 2006.173.16:34:18.53#ibcon#read 4, iclass 11, count 0 2006.173.16:34:18.53#ibcon#about to read 5, iclass 11, count 0 2006.173.16:34:18.53#ibcon#read 5, iclass 11, count 0 2006.173.16:34:18.53#ibcon#about to read 6, iclass 11, count 0 2006.173.16:34:18.53#ibcon#read 6, iclass 11, count 0 2006.173.16:34:18.53#ibcon#end of sib2, iclass 11, count 0 2006.173.16:34:18.53#ibcon#*after write, iclass 11, count 0 2006.173.16:34:18.53#ibcon#*before return 0, iclass 11, count 0 2006.173.16:34:18.53#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.16:34:18.53#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.16:34:18.53#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.16:34:18.53#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.16:34:18.53$vck44/vblo=6,719.99 2006.173.16:34:18.53#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.16:34:18.53#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.16:34:18.53#ibcon#ireg 17 cls_cnt 0 2006.173.16:34:18.53#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.16:34:18.53#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.16:34:18.53#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.16:34:18.53#ibcon#enter wrdev, iclass 13, count 0 2006.173.16:34:18.53#ibcon#first serial, iclass 13, count 0 2006.173.16:34:18.53#ibcon#enter sib2, iclass 13, count 0 2006.173.16:34:18.53#ibcon#flushed, iclass 13, count 0 2006.173.16:34:18.53#ibcon#about to write, iclass 13, count 0 2006.173.16:34:18.53#ibcon#wrote, iclass 13, count 0 2006.173.16:34:18.53#ibcon#about to read 3, iclass 13, count 0 2006.173.16:34:18.55#ibcon#read 3, iclass 13, count 0 2006.173.16:34:18.55#ibcon#about to read 4, iclass 13, count 0 2006.173.16:34:18.55#ibcon#read 4, iclass 13, count 0 2006.173.16:34:18.55#ibcon#about to read 5, iclass 13, count 0 2006.173.16:34:18.55#ibcon#read 5, iclass 13, count 0 2006.173.16:34:18.55#ibcon#about to read 6, iclass 13, count 0 2006.173.16:34:18.55#ibcon#read 6, iclass 13, count 0 2006.173.16:34:18.55#ibcon#end of sib2, iclass 13, count 0 2006.173.16:34:18.55#ibcon#*mode == 0, iclass 13, count 0 2006.173.16:34:18.55#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.16:34:18.55#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.16:34:18.55#ibcon#*before write, iclass 13, count 0 2006.173.16:34:18.55#ibcon#enter sib2, iclass 13, count 0 2006.173.16:34:18.55#ibcon#flushed, iclass 13, count 0 2006.173.16:34:18.55#ibcon#about to write, iclass 13, count 0 2006.173.16:34:18.55#ibcon#wrote, iclass 13, count 0 2006.173.16:34:18.55#ibcon#about to read 3, iclass 13, count 0 2006.173.16:34:18.59#ibcon#read 3, iclass 13, count 0 2006.173.16:34:18.59#ibcon#about to read 4, iclass 13, count 0 2006.173.16:34:18.59#ibcon#read 4, iclass 13, count 0 2006.173.16:34:18.59#ibcon#about to read 5, iclass 13, count 0 2006.173.16:34:18.59#ibcon#read 5, iclass 13, count 0 2006.173.16:34:18.59#ibcon#about to read 6, iclass 13, count 0 2006.173.16:34:18.59#ibcon#read 6, iclass 13, count 0 2006.173.16:34:18.59#ibcon#end of sib2, iclass 13, count 0 2006.173.16:34:18.59#ibcon#*after write, iclass 13, count 0 2006.173.16:34:18.59#ibcon#*before return 0, iclass 13, count 0 2006.173.16:34:18.59#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.16:34:18.59#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.16:34:18.59#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.16:34:18.59#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.16:34:18.59$vck44/vb=6,4 2006.173.16:34:18.59#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.16:34:18.59#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.16:34:18.59#ibcon#ireg 11 cls_cnt 2 2006.173.16:34:18.59#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.16:34:18.65#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.16:34:18.65#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.16:34:18.65#ibcon#enter wrdev, iclass 15, count 2 2006.173.16:34:18.65#ibcon#first serial, iclass 15, count 2 2006.173.16:34:18.65#ibcon#enter sib2, iclass 15, count 2 2006.173.16:34:18.65#ibcon#flushed, iclass 15, count 2 2006.173.16:34:18.65#ibcon#about to write, iclass 15, count 2 2006.173.16:34:18.65#ibcon#wrote, iclass 15, count 2 2006.173.16:34:18.65#ibcon#about to read 3, iclass 15, count 2 2006.173.16:34:18.67#ibcon#read 3, iclass 15, count 2 2006.173.16:34:18.67#ibcon#about to read 4, iclass 15, count 2 2006.173.16:34:18.67#ibcon#read 4, iclass 15, count 2 2006.173.16:34:18.67#ibcon#about to read 5, iclass 15, count 2 2006.173.16:34:18.67#ibcon#read 5, iclass 15, count 2 2006.173.16:34:18.67#ibcon#about to read 6, iclass 15, count 2 2006.173.16:34:18.67#ibcon#read 6, iclass 15, count 2 2006.173.16:34:18.67#ibcon#end of sib2, iclass 15, count 2 2006.173.16:34:18.67#ibcon#*mode == 0, iclass 15, count 2 2006.173.16:34:18.67#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.16:34:18.67#ibcon#[27=AT06-04\r\n] 2006.173.16:34:18.67#ibcon#*before write, iclass 15, count 2 2006.173.16:34:18.67#ibcon#enter sib2, iclass 15, count 2 2006.173.16:34:18.67#ibcon#flushed, iclass 15, count 2 2006.173.16:34:18.67#ibcon#about to write, iclass 15, count 2 2006.173.16:34:18.67#ibcon#wrote, iclass 15, count 2 2006.173.16:34:18.67#ibcon#about to read 3, iclass 15, count 2 2006.173.16:34:18.70#ibcon#read 3, iclass 15, count 2 2006.173.16:34:18.70#ibcon#about to read 4, iclass 15, count 2 2006.173.16:34:18.70#ibcon#read 4, iclass 15, count 2 2006.173.16:34:18.70#ibcon#about to read 5, iclass 15, count 2 2006.173.16:34:18.70#ibcon#read 5, iclass 15, count 2 2006.173.16:34:18.70#ibcon#about to read 6, iclass 15, count 2 2006.173.16:34:18.70#ibcon#read 6, iclass 15, count 2 2006.173.16:34:18.70#ibcon#end of sib2, iclass 15, count 2 2006.173.16:34:18.70#ibcon#*after write, iclass 15, count 2 2006.173.16:34:18.70#ibcon#*before return 0, iclass 15, count 2 2006.173.16:34:18.70#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.16:34:18.70#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.16:34:18.70#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.16:34:18.70#ibcon#ireg 7 cls_cnt 0 2006.173.16:34:18.70#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.16:34:18.82#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.16:34:18.82#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.16:34:18.82#ibcon#enter wrdev, iclass 15, count 0 2006.173.16:34:18.82#ibcon#first serial, iclass 15, count 0 2006.173.16:34:18.82#ibcon#enter sib2, iclass 15, count 0 2006.173.16:34:18.82#ibcon#flushed, iclass 15, count 0 2006.173.16:34:18.82#ibcon#about to write, iclass 15, count 0 2006.173.16:34:18.82#ibcon#wrote, iclass 15, count 0 2006.173.16:34:18.82#ibcon#about to read 3, iclass 15, count 0 2006.173.16:34:18.84#ibcon#read 3, iclass 15, count 0 2006.173.16:34:18.84#ibcon#about to read 4, iclass 15, count 0 2006.173.16:34:18.84#ibcon#read 4, iclass 15, count 0 2006.173.16:34:18.84#ibcon#about to read 5, iclass 15, count 0 2006.173.16:34:18.84#ibcon#read 5, iclass 15, count 0 2006.173.16:34:18.84#ibcon#about to read 6, iclass 15, count 0 2006.173.16:34:18.84#ibcon#read 6, iclass 15, count 0 2006.173.16:34:18.84#ibcon#end of sib2, iclass 15, count 0 2006.173.16:34:18.84#ibcon#*mode == 0, iclass 15, count 0 2006.173.16:34:18.84#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.16:34:18.84#ibcon#[27=USB\r\n] 2006.173.16:34:18.84#ibcon#*before write, iclass 15, count 0 2006.173.16:34:18.84#ibcon#enter sib2, iclass 15, count 0 2006.173.16:34:18.84#ibcon#flushed, iclass 15, count 0 2006.173.16:34:18.84#ibcon#about to write, iclass 15, count 0 2006.173.16:34:18.84#ibcon#wrote, iclass 15, count 0 2006.173.16:34:18.84#ibcon#about to read 3, iclass 15, count 0 2006.173.16:34:18.87#ibcon#read 3, iclass 15, count 0 2006.173.16:34:18.87#ibcon#about to read 4, iclass 15, count 0 2006.173.16:34:18.87#ibcon#read 4, iclass 15, count 0 2006.173.16:34:18.87#ibcon#about to read 5, iclass 15, count 0 2006.173.16:34:18.87#ibcon#read 5, iclass 15, count 0 2006.173.16:34:18.87#ibcon#about to read 6, iclass 15, count 0 2006.173.16:34:18.87#ibcon#read 6, iclass 15, count 0 2006.173.16:34:18.87#ibcon#end of sib2, iclass 15, count 0 2006.173.16:34:18.87#ibcon#*after write, iclass 15, count 0 2006.173.16:34:18.87#ibcon#*before return 0, iclass 15, count 0 2006.173.16:34:18.87#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.16:34:18.87#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.16:34:18.87#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.16:34:18.87#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.16:34:18.87$vck44/vblo=7,734.99 2006.173.16:34:18.87#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.16:34:18.87#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.16:34:18.87#ibcon#ireg 17 cls_cnt 0 2006.173.16:34:18.87#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.16:34:18.87#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.16:34:18.87#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.16:34:18.87#ibcon#enter wrdev, iclass 17, count 0 2006.173.16:34:18.87#ibcon#first serial, iclass 17, count 0 2006.173.16:34:18.87#ibcon#enter sib2, iclass 17, count 0 2006.173.16:34:18.87#ibcon#flushed, iclass 17, count 0 2006.173.16:34:18.87#ibcon#about to write, iclass 17, count 0 2006.173.16:34:18.87#ibcon#wrote, iclass 17, count 0 2006.173.16:34:18.87#ibcon#about to read 3, iclass 17, count 0 2006.173.16:34:18.89#ibcon#read 3, iclass 17, count 0 2006.173.16:34:18.89#ibcon#about to read 4, iclass 17, count 0 2006.173.16:34:18.89#ibcon#read 4, iclass 17, count 0 2006.173.16:34:18.89#ibcon#about to read 5, iclass 17, count 0 2006.173.16:34:18.89#ibcon#read 5, iclass 17, count 0 2006.173.16:34:18.89#ibcon#about to read 6, iclass 17, count 0 2006.173.16:34:18.89#ibcon#read 6, iclass 17, count 0 2006.173.16:34:18.89#ibcon#end of sib2, iclass 17, count 0 2006.173.16:34:18.89#ibcon#*mode == 0, iclass 17, count 0 2006.173.16:34:18.89#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.16:34:18.89#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.16:34:18.89#ibcon#*before write, iclass 17, count 0 2006.173.16:34:18.89#ibcon#enter sib2, iclass 17, count 0 2006.173.16:34:18.89#ibcon#flushed, iclass 17, count 0 2006.173.16:34:18.89#ibcon#about to write, iclass 17, count 0 2006.173.16:34:18.89#ibcon#wrote, iclass 17, count 0 2006.173.16:34:18.89#ibcon#about to read 3, iclass 17, count 0 2006.173.16:34:18.93#ibcon#read 3, iclass 17, count 0 2006.173.16:34:18.93#ibcon#about to read 4, iclass 17, count 0 2006.173.16:34:18.93#ibcon#read 4, iclass 17, count 0 2006.173.16:34:18.93#ibcon#about to read 5, iclass 17, count 0 2006.173.16:34:18.93#ibcon#read 5, iclass 17, count 0 2006.173.16:34:18.93#ibcon#about to read 6, iclass 17, count 0 2006.173.16:34:18.93#ibcon#read 6, iclass 17, count 0 2006.173.16:34:18.93#ibcon#end of sib2, iclass 17, count 0 2006.173.16:34:18.93#ibcon#*after write, iclass 17, count 0 2006.173.16:34:18.93#ibcon#*before return 0, iclass 17, count 0 2006.173.16:34:18.93#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.16:34:18.93#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.16:34:18.93#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.16:34:18.93#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.16:34:18.93$vck44/vb=7,4 2006.173.16:34:18.93#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.16:34:18.93#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.16:34:18.93#ibcon#ireg 11 cls_cnt 2 2006.173.16:34:18.93#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.16:34:18.99#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.16:34:18.99#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.16:34:18.99#ibcon#enter wrdev, iclass 19, count 2 2006.173.16:34:18.99#ibcon#first serial, iclass 19, count 2 2006.173.16:34:18.99#ibcon#enter sib2, iclass 19, count 2 2006.173.16:34:18.99#ibcon#flushed, iclass 19, count 2 2006.173.16:34:18.99#ibcon#about to write, iclass 19, count 2 2006.173.16:34:18.99#ibcon#wrote, iclass 19, count 2 2006.173.16:34:18.99#ibcon#about to read 3, iclass 19, count 2 2006.173.16:34:19.01#ibcon#read 3, iclass 19, count 2 2006.173.16:34:19.01#ibcon#about to read 4, iclass 19, count 2 2006.173.16:34:19.01#ibcon#read 4, iclass 19, count 2 2006.173.16:34:19.01#ibcon#about to read 5, iclass 19, count 2 2006.173.16:34:19.01#ibcon#read 5, iclass 19, count 2 2006.173.16:34:19.01#ibcon#about to read 6, iclass 19, count 2 2006.173.16:34:19.01#ibcon#read 6, iclass 19, count 2 2006.173.16:34:19.01#ibcon#end of sib2, iclass 19, count 2 2006.173.16:34:19.01#ibcon#*mode == 0, iclass 19, count 2 2006.173.16:34:19.01#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.16:34:19.01#ibcon#[27=AT07-04\r\n] 2006.173.16:34:19.01#ibcon#*before write, iclass 19, count 2 2006.173.16:34:19.01#ibcon#enter sib2, iclass 19, count 2 2006.173.16:34:19.01#ibcon#flushed, iclass 19, count 2 2006.173.16:34:19.01#ibcon#about to write, iclass 19, count 2 2006.173.16:34:19.01#ibcon#wrote, iclass 19, count 2 2006.173.16:34:19.01#ibcon#about to read 3, iclass 19, count 2 2006.173.16:34:19.04#ibcon#read 3, iclass 19, count 2 2006.173.16:34:19.04#ibcon#about to read 4, iclass 19, count 2 2006.173.16:34:19.04#ibcon#read 4, iclass 19, count 2 2006.173.16:34:19.04#ibcon#about to read 5, iclass 19, count 2 2006.173.16:34:19.04#ibcon#read 5, iclass 19, count 2 2006.173.16:34:19.04#ibcon#about to read 6, iclass 19, count 2 2006.173.16:34:19.04#ibcon#read 6, iclass 19, count 2 2006.173.16:34:19.04#ibcon#end of sib2, iclass 19, count 2 2006.173.16:34:19.04#ibcon#*after write, iclass 19, count 2 2006.173.16:34:19.04#ibcon#*before return 0, iclass 19, count 2 2006.173.16:34:19.04#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.16:34:19.04#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.16:34:19.04#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.16:34:19.04#ibcon#ireg 7 cls_cnt 0 2006.173.16:34:19.04#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.16:34:19.16#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.16:34:19.16#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.16:34:19.16#ibcon#enter wrdev, iclass 19, count 0 2006.173.16:34:19.16#ibcon#first serial, iclass 19, count 0 2006.173.16:34:19.16#ibcon#enter sib2, iclass 19, count 0 2006.173.16:34:19.16#ibcon#flushed, iclass 19, count 0 2006.173.16:34:19.16#ibcon#about to write, iclass 19, count 0 2006.173.16:34:19.16#ibcon#wrote, iclass 19, count 0 2006.173.16:34:19.16#ibcon#about to read 3, iclass 19, count 0 2006.173.16:34:19.18#ibcon#read 3, iclass 19, count 0 2006.173.16:34:19.18#ibcon#about to read 4, iclass 19, count 0 2006.173.16:34:19.18#ibcon#read 4, iclass 19, count 0 2006.173.16:34:19.18#ibcon#about to read 5, iclass 19, count 0 2006.173.16:34:19.18#ibcon#read 5, iclass 19, count 0 2006.173.16:34:19.18#ibcon#about to read 6, iclass 19, count 0 2006.173.16:34:19.18#ibcon#read 6, iclass 19, count 0 2006.173.16:34:19.18#ibcon#end of sib2, iclass 19, count 0 2006.173.16:34:19.18#ibcon#*mode == 0, iclass 19, count 0 2006.173.16:34:19.18#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.16:34:19.18#ibcon#[27=USB\r\n] 2006.173.16:34:19.18#ibcon#*before write, iclass 19, count 0 2006.173.16:34:19.18#ibcon#enter sib2, iclass 19, count 0 2006.173.16:34:19.18#ibcon#flushed, iclass 19, count 0 2006.173.16:34:19.18#ibcon#about to write, iclass 19, count 0 2006.173.16:34:19.18#ibcon#wrote, iclass 19, count 0 2006.173.16:34:19.18#ibcon#about to read 3, iclass 19, count 0 2006.173.16:34:19.21#ibcon#read 3, iclass 19, count 0 2006.173.16:34:19.21#ibcon#about to read 4, iclass 19, count 0 2006.173.16:34:19.21#ibcon#read 4, iclass 19, count 0 2006.173.16:34:19.21#ibcon#about to read 5, iclass 19, count 0 2006.173.16:34:19.21#ibcon#read 5, iclass 19, count 0 2006.173.16:34:19.21#ibcon#about to read 6, iclass 19, count 0 2006.173.16:34:19.21#ibcon#read 6, iclass 19, count 0 2006.173.16:34:19.21#ibcon#end of sib2, iclass 19, count 0 2006.173.16:34:19.21#ibcon#*after write, iclass 19, count 0 2006.173.16:34:19.21#ibcon#*before return 0, iclass 19, count 0 2006.173.16:34:19.21#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.16:34:19.21#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.16:34:19.21#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.16:34:19.21#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.16:34:19.21$vck44/vblo=8,744.99 2006.173.16:34:19.21#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.16:34:19.21#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.16:34:19.21#ibcon#ireg 17 cls_cnt 0 2006.173.16:34:19.21#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.16:34:19.21#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.16:34:19.21#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.16:34:19.21#ibcon#enter wrdev, iclass 21, count 0 2006.173.16:34:19.21#ibcon#first serial, iclass 21, count 0 2006.173.16:34:19.21#ibcon#enter sib2, iclass 21, count 0 2006.173.16:34:19.21#ibcon#flushed, iclass 21, count 0 2006.173.16:34:19.21#ibcon#about to write, iclass 21, count 0 2006.173.16:34:19.21#ibcon#wrote, iclass 21, count 0 2006.173.16:34:19.21#ibcon#about to read 3, iclass 21, count 0 2006.173.16:34:19.23#ibcon#read 3, iclass 21, count 0 2006.173.16:34:19.23#ibcon#about to read 4, iclass 21, count 0 2006.173.16:34:19.23#ibcon#read 4, iclass 21, count 0 2006.173.16:34:19.23#ibcon#about to read 5, iclass 21, count 0 2006.173.16:34:19.23#ibcon#read 5, iclass 21, count 0 2006.173.16:34:19.23#ibcon#about to read 6, iclass 21, count 0 2006.173.16:34:19.23#ibcon#read 6, iclass 21, count 0 2006.173.16:34:19.23#ibcon#end of sib2, iclass 21, count 0 2006.173.16:34:19.23#ibcon#*mode == 0, iclass 21, count 0 2006.173.16:34:19.23#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.16:34:19.23#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.16:34:19.23#ibcon#*before write, iclass 21, count 0 2006.173.16:34:19.23#ibcon#enter sib2, iclass 21, count 0 2006.173.16:34:19.23#ibcon#flushed, iclass 21, count 0 2006.173.16:34:19.23#ibcon#about to write, iclass 21, count 0 2006.173.16:34:19.23#ibcon#wrote, iclass 21, count 0 2006.173.16:34:19.23#ibcon#about to read 3, iclass 21, count 0 2006.173.16:34:19.27#ibcon#read 3, iclass 21, count 0 2006.173.16:34:19.27#ibcon#about to read 4, iclass 21, count 0 2006.173.16:34:19.27#ibcon#read 4, iclass 21, count 0 2006.173.16:34:19.27#ibcon#about to read 5, iclass 21, count 0 2006.173.16:34:19.27#ibcon#read 5, iclass 21, count 0 2006.173.16:34:19.27#ibcon#about to read 6, iclass 21, count 0 2006.173.16:34:19.27#ibcon#read 6, iclass 21, count 0 2006.173.16:34:19.27#ibcon#end of sib2, iclass 21, count 0 2006.173.16:34:19.27#ibcon#*after write, iclass 21, count 0 2006.173.16:34:19.27#ibcon#*before return 0, iclass 21, count 0 2006.173.16:34:19.27#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.16:34:19.27#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.16:34:19.27#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.16:34:19.27#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.16:34:19.27$vck44/vb=8,4 2006.173.16:34:19.27#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.16:34:19.27#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.16:34:19.27#ibcon#ireg 11 cls_cnt 2 2006.173.16:34:19.27#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.16:34:19.33#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.16:34:19.33#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.16:34:19.33#ibcon#enter wrdev, iclass 23, count 2 2006.173.16:34:19.33#ibcon#first serial, iclass 23, count 2 2006.173.16:34:19.33#ibcon#enter sib2, iclass 23, count 2 2006.173.16:34:19.33#ibcon#flushed, iclass 23, count 2 2006.173.16:34:19.33#ibcon#about to write, iclass 23, count 2 2006.173.16:34:19.33#ibcon#wrote, iclass 23, count 2 2006.173.16:34:19.33#ibcon#about to read 3, iclass 23, count 2 2006.173.16:34:19.35#ibcon#read 3, iclass 23, count 2 2006.173.16:34:19.35#ibcon#about to read 4, iclass 23, count 2 2006.173.16:34:19.35#ibcon#read 4, iclass 23, count 2 2006.173.16:34:19.35#ibcon#about to read 5, iclass 23, count 2 2006.173.16:34:19.35#ibcon#read 5, iclass 23, count 2 2006.173.16:34:19.35#ibcon#about to read 6, iclass 23, count 2 2006.173.16:34:19.35#ibcon#read 6, iclass 23, count 2 2006.173.16:34:19.35#ibcon#end of sib2, iclass 23, count 2 2006.173.16:34:19.35#ibcon#*mode == 0, iclass 23, count 2 2006.173.16:34:19.35#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.16:34:19.35#ibcon#[27=AT08-04\r\n] 2006.173.16:34:19.35#ibcon#*before write, iclass 23, count 2 2006.173.16:34:19.35#ibcon#enter sib2, iclass 23, count 2 2006.173.16:34:19.35#ibcon#flushed, iclass 23, count 2 2006.173.16:34:19.35#ibcon#about to write, iclass 23, count 2 2006.173.16:34:19.35#ibcon#wrote, iclass 23, count 2 2006.173.16:34:19.35#ibcon#about to read 3, iclass 23, count 2 2006.173.16:34:19.38#ibcon#read 3, iclass 23, count 2 2006.173.16:34:19.38#ibcon#about to read 4, iclass 23, count 2 2006.173.16:34:19.38#ibcon#read 4, iclass 23, count 2 2006.173.16:34:19.38#ibcon#about to read 5, iclass 23, count 2 2006.173.16:34:19.38#ibcon#read 5, iclass 23, count 2 2006.173.16:34:19.38#ibcon#about to read 6, iclass 23, count 2 2006.173.16:34:19.38#ibcon#read 6, iclass 23, count 2 2006.173.16:34:19.38#ibcon#end of sib2, iclass 23, count 2 2006.173.16:34:19.38#ibcon#*after write, iclass 23, count 2 2006.173.16:34:19.38#ibcon#*before return 0, iclass 23, count 2 2006.173.16:34:19.38#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.16:34:19.38#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.16:34:19.38#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.16:34:19.38#ibcon#ireg 7 cls_cnt 0 2006.173.16:34:19.38#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.16:34:19.50#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.16:34:19.50#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.16:34:19.50#ibcon#enter wrdev, iclass 23, count 0 2006.173.16:34:19.50#ibcon#first serial, iclass 23, count 0 2006.173.16:34:19.50#ibcon#enter sib2, iclass 23, count 0 2006.173.16:34:19.50#ibcon#flushed, iclass 23, count 0 2006.173.16:34:19.50#ibcon#about to write, iclass 23, count 0 2006.173.16:34:19.50#ibcon#wrote, iclass 23, count 0 2006.173.16:34:19.50#ibcon#about to read 3, iclass 23, count 0 2006.173.16:34:19.52#ibcon#read 3, iclass 23, count 0 2006.173.16:34:19.52#ibcon#about to read 4, iclass 23, count 0 2006.173.16:34:19.52#ibcon#read 4, iclass 23, count 0 2006.173.16:34:19.52#ibcon#about to read 5, iclass 23, count 0 2006.173.16:34:19.52#ibcon#read 5, iclass 23, count 0 2006.173.16:34:19.52#ibcon#about to read 6, iclass 23, count 0 2006.173.16:34:19.52#ibcon#read 6, iclass 23, count 0 2006.173.16:34:19.52#ibcon#end of sib2, iclass 23, count 0 2006.173.16:34:19.52#ibcon#*mode == 0, iclass 23, count 0 2006.173.16:34:19.52#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.16:34:19.52#ibcon#[27=USB\r\n] 2006.173.16:34:19.52#ibcon#*before write, iclass 23, count 0 2006.173.16:34:19.52#ibcon#enter sib2, iclass 23, count 0 2006.173.16:34:19.52#ibcon#flushed, iclass 23, count 0 2006.173.16:34:19.52#ibcon#about to write, iclass 23, count 0 2006.173.16:34:19.52#ibcon#wrote, iclass 23, count 0 2006.173.16:34:19.52#ibcon#about to read 3, iclass 23, count 0 2006.173.16:34:19.55#ibcon#read 3, iclass 23, count 0 2006.173.16:34:19.55#ibcon#about to read 4, iclass 23, count 0 2006.173.16:34:19.55#ibcon#read 4, iclass 23, count 0 2006.173.16:34:19.55#ibcon#about to read 5, iclass 23, count 0 2006.173.16:34:19.55#ibcon#read 5, iclass 23, count 0 2006.173.16:34:19.55#ibcon#about to read 6, iclass 23, count 0 2006.173.16:34:19.55#ibcon#read 6, iclass 23, count 0 2006.173.16:34:19.55#ibcon#end of sib2, iclass 23, count 0 2006.173.16:34:19.55#ibcon#*after write, iclass 23, count 0 2006.173.16:34:19.55#ibcon#*before return 0, iclass 23, count 0 2006.173.16:34:19.55#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.16:34:19.55#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.16:34:19.55#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.16:34:19.55#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.16:34:19.55$vck44/vabw=wide 2006.173.16:34:19.55#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.16:34:19.55#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.16:34:19.55#ibcon#ireg 8 cls_cnt 0 2006.173.16:34:19.55#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.16:34:19.55#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.16:34:19.55#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.16:34:19.55#ibcon#enter wrdev, iclass 25, count 0 2006.173.16:34:19.55#ibcon#first serial, iclass 25, count 0 2006.173.16:34:19.55#ibcon#enter sib2, iclass 25, count 0 2006.173.16:34:19.55#ibcon#flushed, iclass 25, count 0 2006.173.16:34:19.55#ibcon#about to write, iclass 25, count 0 2006.173.16:34:19.55#ibcon#wrote, iclass 25, count 0 2006.173.16:34:19.55#ibcon#about to read 3, iclass 25, count 0 2006.173.16:34:19.57#ibcon#read 3, iclass 25, count 0 2006.173.16:34:19.57#ibcon#about to read 4, iclass 25, count 0 2006.173.16:34:19.57#ibcon#read 4, iclass 25, count 0 2006.173.16:34:19.57#ibcon#about to read 5, iclass 25, count 0 2006.173.16:34:19.57#ibcon#read 5, iclass 25, count 0 2006.173.16:34:19.57#ibcon#about to read 6, iclass 25, count 0 2006.173.16:34:19.57#ibcon#read 6, iclass 25, count 0 2006.173.16:34:19.57#ibcon#end of sib2, iclass 25, count 0 2006.173.16:34:19.57#ibcon#*mode == 0, iclass 25, count 0 2006.173.16:34:19.57#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.16:34:19.57#ibcon#[25=BW32\r\n] 2006.173.16:34:19.57#ibcon#*before write, iclass 25, count 0 2006.173.16:34:19.57#ibcon#enter sib2, iclass 25, count 0 2006.173.16:34:19.57#ibcon#flushed, iclass 25, count 0 2006.173.16:34:19.57#ibcon#about to write, iclass 25, count 0 2006.173.16:34:19.57#ibcon#wrote, iclass 25, count 0 2006.173.16:34:19.57#ibcon#about to read 3, iclass 25, count 0 2006.173.16:34:19.60#ibcon#read 3, iclass 25, count 0 2006.173.16:34:19.60#ibcon#about to read 4, iclass 25, count 0 2006.173.16:34:19.60#ibcon#read 4, iclass 25, count 0 2006.173.16:34:19.60#ibcon#about to read 5, iclass 25, count 0 2006.173.16:34:19.60#ibcon#read 5, iclass 25, count 0 2006.173.16:34:19.60#ibcon#about to read 6, iclass 25, count 0 2006.173.16:34:19.60#ibcon#read 6, iclass 25, count 0 2006.173.16:34:19.60#ibcon#end of sib2, iclass 25, count 0 2006.173.16:34:19.60#ibcon#*after write, iclass 25, count 0 2006.173.16:34:19.60#ibcon#*before return 0, iclass 25, count 0 2006.173.16:34:19.60#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.16:34:19.60#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.16:34:19.60#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.16:34:19.60#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.16:34:19.60$vck44/vbbw=wide 2006.173.16:34:19.60#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.16:34:19.60#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.16:34:19.60#ibcon#ireg 8 cls_cnt 0 2006.173.16:34:19.60#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.16:34:19.67#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.16:34:19.67#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.16:34:19.67#ibcon#enter wrdev, iclass 27, count 0 2006.173.16:34:19.67#ibcon#first serial, iclass 27, count 0 2006.173.16:34:19.67#ibcon#enter sib2, iclass 27, count 0 2006.173.16:34:19.67#ibcon#flushed, iclass 27, count 0 2006.173.16:34:19.67#ibcon#about to write, iclass 27, count 0 2006.173.16:34:19.67#ibcon#wrote, iclass 27, count 0 2006.173.16:34:19.67#ibcon#about to read 3, iclass 27, count 0 2006.173.16:34:19.69#ibcon#read 3, iclass 27, count 0 2006.173.16:34:19.69#ibcon#about to read 4, iclass 27, count 0 2006.173.16:34:19.69#ibcon#read 4, iclass 27, count 0 2006.173.16:34:19.69#ibcon#about to read 5, iclass 27, count 0 2006.173.16:34:19.69#ibcon#read 5, iclass 27, count 0 2006.173.16:34:19.69#ibcon#about to read 6, iclass 27, count 0 2006.173.16:34:19.69#ibcon#read 6, iclass 27, count 0 2006.173.16:34:19.69#ibcon#end of sib2, iclass 27, count 0 2006.173.16:34:19.69#ibcon#*mode == 0, iclass 27, count 0 2006.173.16:34:19.69#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.16:34:19.69#ibcon#[27=BW32\r\n] 2006.173.16:34:19.69#ibcon#*before write, iclass 27, count 0 2006.173.16:34:19.69#ibcon#enter sib2, iclass 27, count 0 2006.173.16:34:19.69#ibcon#flushed, iclass 27, count 0 2006.173.16:34:19.69#ibcon#about to write, iclass 27, count 0 2006.173.16:34:19.69#ibcon#wrote, iclass 27, count 0 2006.173.16:34:19.69#ibcon#about to read 3, iclass 27, count 0 2006.173.16:34:19.72#ibcon#read 3, iclass 27, count 0 2006.173.16:34:19.72#ibcon#about to read 4, iclass 27, count 0 2006.173.16:34:19.72#ibcon#read 4, iclass 27, count 0 2006.173.16:34:19.72#ibcon#about to read 5, iclass 27, count 0 2006.173.16:34:19.72#ibcon#read 5, iclass 27, count 0 2006.173.16:34:19.72#ibcon#about to read 6, iclass 27, count 0 2006.173.16:34:19.72#ibcon#read 6, iclass 27, count 0 2006.173.16:34:19.72#ibcon#end of sib2, iclass 27, count 0 2006.173.16:34:19.72#ibcon#*after write, iclass 27, count 0 2006.173.16:34:19.72#ibcon#*before return 0, iclass 27, count 0 2006.173.16:34:19.72#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.16:34:19.72#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.16:34:19.72#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.16:34:19.72#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.16:34:19.72$setupk4/ifdk4 2006.173.16:34:19.72$ifdk4/lo= 2006.173.16:34:19.72$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.16:34:19.72$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.16:34:19.72$ifdk4/patch= 2006.173.16:34:19.72$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.16:34:19.72$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.16:34:19.72$setupk4/!*+20s 2006.173.16:34:22.89#abcon#<5=/13 0.4 1.7 20.411001002.5\r\n> 2006.173.16:34:22.91#abcon#{5=INTERFACE CLEAR} 2006.173.16:34:22.97#abcon#[5=S1D000X0/0*\r\n] 2006.173.16:34:33.06#abcon#<5=/13 0.4 1.7 20.411001002.5\r\n> 2006.173.16:34:33.08#abcon#{5=INTERFACE CLEAR} 2006.173.16:34:33.14#abcon#[5=S1D000X0/0*\r\n] 2006.173.16:34:34.23$setupk4/"tpicd 2006.173.16:34:34.23$setupk4/echo=off 2006.173.16:34:34.23$setupk4/xlog=off 2006.173.16:34:34.23:!2006.173.16:37:15 2006.173.16:34:49.13#trakl#Source acquired 2006.173.16:34:51.13#flagr#flagr/antenna,acquired 2006.173.16:37:15.00:preob 2006.173.16:37:16.14/onsource/TRACKING 2006.173.16:37:16.14:!2006.173.16:37:25 2006.173.16:37:25.00:"tape 2006.173.16:37:25.00:"st=record 2006.173.16:37:25.00:data_valid=on 2006.173.16:37:25.00:midob 2006.173.16:37:25.14/onsource/TRACKING 2006.173.16:37:25.14/wx/20.40,1002.6,100 2006.173.16:37:25.33/cable/+6.5122E-03 2006.173.16:37:26.42/va/01,07,usb,yes,34,37 2006.173.16:37:26.42/va/02,06,usb,yes,34,35 2006.173.16:37:26.42/va/03,05,usb,yes,44,45 2006.173.16:37:26.42/va/04,06,usb,yes,35,37 2006.173.16:37:26.42/va/05,04,usb,yes,27,28 2006.173.16:37:26.42/va/06,03,usb,yes,38,38 2006.173.16:37:26.42/va/07,04,usb,yes,31,32 2006.173.16:37:26.42/va/08,04,usb,yes,26,32 2006.173.16:37:26.65/valo/01,524.99,yes,locked 2006.173.16:37:26.65/valo/02,534.99,yes,locked 2006.173.16:37:26.65/valo/03,564.99,yes,locked 2006.173.16:37:26.65/valo/04,624.99,yes,locked 2006.173.16:37:26.65/valo/05,734.99,yes,locked 2006.173.16:37:26.65/valo/06,814.99,yes,locked 2006.173.16:37:26.65/valo/07,864.99,yes,locked 2006.173.16:37:26.65/valo/08,884.99,yes,locked 2006.173.16:37:27.74/vb/01,04,usb,yes,28,26 2006.173.16:37:27.74/vb/02,04,usb,yes,31,31 2006.173.16:37:27.74/vb/03,04,usb,yes,28,31 2006.173.16:37:27.74/vb/04,04,usb,yes,32,31 2006.173.16:37:27.74/vb/05,04,usb,yes,25,27 2006.173.16:37:27.74/vb/06,04,usb,yes,29,26 2006.173.16:37:27.74/vb/07,04,usb,yes,29,29 2006.173.16:37:27.74/vb/08,04,usb,yes,27,30 2006.173.16:37:27.98/vblo/01,629.99,yes,locked 2006.173.16:37:27.98/vblo/02,634.99,yes,locked 2006.173.16:37:27.98/vblo/03,649.99,yes,locked 2006.173.16:37:27.98/vblo/04,679.99,yes,locked 2006.173.16:37:27.98/vblo/05,709.99,yes,locked 2006.173.16:37:27.98/vblo/06,719.99,yes,locked 2006.173.16:37:27.98/vblo/07,734.99,yes,locked 2006.173.16:37:27.98/vblo/08,744.99,yes,locked 2006.173.16:37:28.13/vabw/8 2006.173.16:37:28.28/vbbw/8 2006.173.16:37:28.37/xfe/off,on,14.5 2006.173.16:37:28.75/ifatt/23,28,28,28 2006.173.16:37:29.08/fmout-gps/S +3.93E-07 2006.173.16:37:29.12:!2006.173.16:39:25 2006.173.16:39:25.00:data_valid=off 2006.173.16:39:25.00:"et 2006.173.16:39:25.00:!+3s 2006.173.16:39:28.02:"tape 2006.173.16:39:28.02:postob 2006.173.16:39:28.16/cable/+6.5133E-03 2006.173.16:39:28.16/wx/20.41,1002.8,100 2006.173.16:39:29.08/fmout-gps/S +3.92E-07 2006.173.16:39:29.08:scan_name=173-1645,jd0606,180 2006.173.16:39:29.08:source=3c446,222547.26,-045701.4,2000.0,ccw 2006.173.16:39:29.14#flagr#flagr/antenna,new-source 2006.173.16:39:30.14:checkk5 2006.173.16:39:30.54/chk_autoobs//k5ts1/ autoobs is running! 2006.173.16:39:30.92/chk_autoobs//k5ts2/ autoobs is running! 2006.173.16:39:31.34/chk_autoobs//k5ts3/ autoobs is running! 2006.173.16:39:31.75/chk_autoobs//k5ts4/ autoobs is running! 2006.173.16:39:32.15/chk_obsdata//k5ts1/T1731637??a.dat file size is correct (nominal:480MB, actual:476MB). 2006.173.16:39:32.55/chk_obsdata//k5ts2/T1731637??b.dat file size is correct (nominal:480MB, actual:476MB). 2006.173.16:39:32.96/chk_obsdata//k5ts3/T1731637??c.dat file size is correct (nominal:480MB, actual:476MB). 2006.173.16:39:33.37/chk_obsdata//k5ts4/T1731637??d.dat file size is correct (nominal:480MB, actual:476MB). 2006.173.16:39:34.06/k5log//k5ts1_log_newline 2006.173.16:39:34.77/k5log//k5ts2_log_newline 2006.173.16:39:35.48/k5log//k5ts3_log_newline 2006.173.16:39:36.19/k5log//k5ts4_log_newline 2006.173.16:39:36.22/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.16:39:36.22:setupk4=1 2006.173.16:39:36.22$setupk4/echo=on 2006.173.16:39:36.22$setupk4/pcalon 2006.173.16:39:36.22$pcalon/"no phase cal control is implemented here 2006.173.16:39:36.22$setupk4/"tpicd=stop 2006.173.16:39:36.22$setupk4/"rec=synch_on 2006.173.16:39:36.22$setupk4/"rec_mode=128 2006.173.16:39:36.22$setupk4/!* 2006.173.16:39:36.22$setupk4/recpk4 2006.173.16:39:36.22$recpk4/recpatch= 2006.173.16:39:36.22$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.16:39:36.23$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.16:39:36.23$setupk4/vck44 2006.173.16:39:36.23$vck44/valo=1,524.99 2006.173.16:39:36.23#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.16:39:36.23#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.16:39:36.23#ibcon#ireg 17 cls_cnt 0 2006.173.16:39:36.23#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.16:39:36.23#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.16:39:36.23#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.16:39:36.23#ibcon#enter wrdev, iclass 12, count 0 2006.173.16:39:36.23#ibcon#first serial, iclass 12, count 0 2006.173.16:39:36.23#ibcon#enter sib2, iclass 12, count 0 2006.173.16:39:36.23#ibcon#flushed, iclass 12, count 0 2006.173.16:39:36.23#ibcon#about to write, iclass 12, count 0 2006.173.16:39:36.23#ibcon#wrote, iclass 12, count 0 2006.173.16:39:36.23#ibcon#about to read 3, iclass 12, count 0 2006.173.16:39:36.25#ibcon#read 3, iclass 12, count 0 2006.173.16:39:36.25#ibcon#about to read 4, iclass 12, count 0 2006.173.16:39:36.25#ibcon#read 4, iclass 12, count 0 2006.173.16:39:36.25#ibcon#about to read 5, iclass 12, count 0 2006.173.16:39:36.25#ibcon#read 5, iclass 12, count 0 2006.173.16:39:36.25#ibcon#about to read 6, iclass 12, count 0 2006.173.16:39:36.25#ibcon#read 6, iclass 12, count 0 2006.173.16:39:36.25#ibcon#end of sib2, iclass 12, count 0 2006.173.16:39:36.25#ibcon#*mode == 0, iclass 12, count 0 2006.173.16:39:36.25#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.16:39:36.25#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.16:39:36.25#ibcon#*before write, iclass 12, count 0 2006.173.16:39:36.25#ibcon#enter sib2, iclass 12, count 0 2006.173.16:39:36.25#ibcon#flushed, iclass 12, count 0 2006.173.16:39:36.25#ibcon#about to write, iclass 12, count 0 2006.173.16:39:36.25#ibcon#wrote, iclass 12, count 0 2006.173.16:39:36.25#ibcon#about to read 3, iclass 12, count 0 2006.173.16:39:36.30#ibcon#read 3, iclass 12, count 0 2006.173.16:39:36.30#ibcon#about to read 4, iclass 12, count 0 2006.173.16:39:36.30#ibcon#read 4, iclass 12, count 0 2006.173.16:39:36.30#ibcon#about to read 5, iclass 12, count 0 2006.173.16:39:36.30#ibcon#read 5, iclass 12, count 0 2006.173.16:39:36.30#ibcon#about to read 6, iclass 12, count 0 2006.173.16:39:36.30#ibcon#read 6, iclass 12, count 0 2006.173.16:39:36.30#ibcon#end of sib2, iclass 12, count 0 2006.173.16:39:36.30#ibcon#*after write, iclass 12, count 0 2006.173.16:39:36.30#ibcon#*before return 0, iclass 12, count 0 2006.173.16:39:36.30#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.16:39:36.30#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.16:39:36.30#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.16:39:36.30#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.16:39:36.30$vck44/va=1,7 2006.173.16:39:36.30#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.16:39:36.30#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.16:39:36.30#ibcon#ireg 11 cls_cnt 2 2006.173.16:39:36.30#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.16:39:36.30#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.16:39:36.30#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.16:39:36.30#ibcon#enter wrdev, iclass 14, count 2 2006.173.16:39:36.30#ibcon#first serial, iclass 14, count 2 2006.173.16:39:36.30#ibcon#enter sib2, iclass 14, count 2 2006.173.16:39:36.30#ibcon#flushed, iclass 14, count 2 2006.173.16:39:36.30#ibcon#about to write, iclass 14, count 2 2006.173.16:39:36.30#ibcon#wrote, iclass 14, count 2 2006.173.16:39:36.30#ibcon#about to read 3, iclass 14, count 2 2006.173.16:39:36.32#ibcon#read 3, iclass 14, count 2 2006.173.16:39:36.32#ibcon#about to read 4, iclass 14, count 2 2006.173.16:39:36.32#ibcon#read 4, iclass 14, count 2 2006.173.16:39:36.32#ibcon#about to read 5, iclass 14, count 2 2006.173.16:39:36.32#ibcon#read 5, iclass 14, count 2 2006.173.16:39:36.32#ibcon#about to read 6, iclass 14, count 2 2006.173.16:39:36.32#ibcon#read 6, iclass 14, count 2 2006.173.16:39:36.32#ibcon#end of sib2, iclass 14, count 2 2006.173.16:39:36.32#ibcon#*mode == 0, iclass 14, count 2 2006.173.16:39:36.32#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.16:39:36.32#ibcon#[25=AT01-07\r\n] 2006.173.16:39:36.32#ibcon#*before write, iclass 14, count 2 2006.173.16:39:36.32#ibcon#enter sib2, iclass 14, count 2 2006.173.16:39:36.32#ibcon#flushed, iclass 14, count 2 2006.173.16:39:36.32#ibcon#about to write, iclass 14, count 2 2006.173.16:39:36.32#ibcon#wrote, iclass 14, count 2 2006.173.16:39:36.32#ibcon#about to read 3, iclass 14, count 2 2006.173.16:39:36.35#ibcon#read 3, iclass 14, count 2 2006.173.16:39:36.35#ibcon#about to read 4, iclass 14, count 2 2006.173.16:39:36.35#ibcon#read 4, iclass 14, count 2 2006.173.16:39:36.35#ibcon#about to read 5, iclass 14, count 2 2006.173.16:39:36.35#ibcon#read 5, iclass 14, count 2 2006.173.16:39:36.35#ibcon#about to read 6, iclass 14, count 2 2006.173.16:39:36.35#ibcon#read 6, iclass 14, count 2 2006.173.16:39:36.35#ibcon#end of sib2, iclass 14, count 2 2006.173.16:39:36.35#ibcon#*after write, iclass 14, count 2 2006.173.16:39:36.35#ibcon#*before return 0, iclass 14, count 2 2006.173.16:39:36.35#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.16:39:36.35#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.16:39:36.35#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.16:39:36.35#ibcon#ireg 7 cls_cnt 0 2006.173.16:39:36.35#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.16:39:36.47#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.16:39:36.47#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.16:39:36.47#ibcon#enter wrdev, iclass 14, count 0 2006.173.16:39:36.47#ibcon#first serial, iclass 14, count 0 2006.173.16:39:36.47#ibcon#enter sib2, iclass 14, count 0 2006.173.16:39:36.47#ibcon#flushed, iclass 14, count 0 2006.173.16:39:36.47#ibcon#about to write, iclass 14, count 0 2006.173.16:39:36.47#ibcon#wrote, iclass 14, count 0 2006.173.16:39:36.47#ibcon#about to read 3, iclass 14, count 0 2006.173.16:39:36.49#ibcon#read 3, iclass 14, count 0 2006.173.16:39:36.49#ibcon#about to read 4, iclass 14, count 0 2006.173.16:39:36.49#ibcon#read 4, iclass 14, count 0 2006.173.16:39:36.49#ibcon#about to read 5, iclass 14, count 0 2006.173.16:39:36.49#ibcon#read 5, iclass 14, count 0 2006.173.16:39:36.49#ibcon#about to read 6, iclass 14, count 0 2006.173.16:39:36.49#ibcon#read 6, iclass 14, count 0 2006.173.16:39:36.49#ibcon#end of sib2, iclass 14, count 0 2006.173.16:39:36.49#ibcon#*mode == 0, iclass 14, count 0 2006.173.16:39:36.49#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.16:39:36.49#ibcon#[25=USB\r\n] 2006.173.16:39:36.49#ibcon#*before write, iclass 14, count 0 2006.173.16:39:36.49#ibcon#enter sib2, iclass 14, count 0 2006.173.16:39:36.49#ibcon#flushed, iclass 14, count 0 2006.173.16:39:36.49#ibcon#about to write, iclass 14, count 0 2006.173.16:39:36.49#ibcon#wrote, iclass 14, count 0 2006.173.16:39:36.49#ibcon#about to read 3, iclass 14, count 0 2006.173.16:39:36.52#ibcon#read 3, iclass 14, count 0 2006.173.16:39:36.52#ibcon#about to read 4, iclass 14, count 0 2006.173.16:39:36.52#ibcon#read 4, iclass 14, count 0 2006.173.16:39:36.52#ibcon#about to read 5, iclass 14, count 0 2006.173.16:39:36.52#ibcon#read 5, iclass 14, count 0 2006.173.16:39:36.52#ibcon#about to read 6, iclass 14, count 0 2006.173.16:39:36.52#ibcon#read 6, iclass 14, count 0 2006.173.16:39:36.52#ibcon#end of sib2, iclass 14, count 0 2006.173.16:39:36.52#ibcon#*after write, iclass 14, count 0 2006.173.16:39:36.52#ibcon#*before return 0, iclass 14, count 0 2006.173.16:39:36.52#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.16:39:36.52#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.16:39:36.52#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.16:39:36.52#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.16:39:36.52$vck44/valo=2,534.99 2006.173.16:39:36.52#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.16:39:36.52#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.16:39:36.52#ibcon#ireg 17 cls_cnt 0 2006.173.16:39:36.52#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.16:39:36.52#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.16:39:36.52#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.16:39:36.52#ibcon#enter wrdev, iclass 16, count 0 2006.173.16:39:36.52#ibcon#first serial, iclass 16, count 0 2006.173.16:39:36.52#ibcon#enter sib2, iclass 16, count 0 2006.173.16:39:36.52#ibcon#flushed, iclass 16, count 0 2006.173.16:39:36.52#ibcon#about to write, iclass 16, count 0 2006.173.16:39:36.52#ibcon#wrote, iclass 16, count 0 2006.173.16:39:36.52#ibcon#about to read 3, iclass 16, count 0 2006.173.16:39:36.54#ibcon#read 3, iclass 16, count 0 2006.173.16:39:36.54#ibcon#about to read 4, iclass 16, count 0 2006.173.16:39:36.54#ibcon#read 4, iclass 16, count 0 2006.173.16:39:36.54#ibcon#about to read 5, iclass 16, count 0 2006.173.16:39:36.54#ibcon#read 5, iclass 16, count 0 2006.173.16:39:36.54#ibcon#about to read 6, iclass 16, count 0 2006.173.16:39:36.54#ibcon#read 6, iclass 16, count 0 2006.173.16:39:36.54#ibcon#end of sib2, iclass 16, count 0 2006.173.16:39:36.54#ibcon#*mode == 0, iclass 16, count 0 2006.173.16:39:36.54#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.16:39:36.54#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.16:39:36.54#ibcon#*before write, iclass 16, count 0 2006.173.16:39:36.54#ibcon#enter sib2, iclass 16, count 0 2006.173.16:39:36.54#ibcon#flushed, iclass 16, count 0 2006.173.16:39:36.54#ibcon#about to write, iclass 16, count 0 2006.173.16:39:36.54#ibcon#wrote, iclass 16, count 0 2006.173.16:39:36.54#ibcon#about to read 3, iclass 16, count 0 2006.173.16:39:36.58#ibcon#read 3, iclass 16, count 0 2006.173.16:39:36.58#ibcon#about to read 4, iclass 16, count 0 2006.173.16:39:36.58#ibcon#read 4, iclass 16, count 0 2006.173.16:39:36.58#ibcon#about to read 5, iclass 16, count 0 2006.173.16:39:36.58#ibcon#read 5, iclass 16, count 0 2006.173.16:39:36.58#ibcon#about to read 6, iclass 16, count 0 2006.173.16:39:36.58#ibcon#read 6, iclass 16, count 0 2006.173.16:39:36.58#ibcon#end of sib2, iclass 16, count 0 2006.173.16:39:36.58#ibcon#*after write, iclass 16, count 0 2006.173.16:39:36.58#ibcon#*before return 0, iclass 16, count 0 2006.173.16:39:36.58#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.16:39:36.58#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.16:39:36.58#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.16:39:36.58#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.16:39:36.58$vck44/va=2,6 2006.173.16:39:36.58#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.16:39:36.58#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.16:39:36.58#ibcon#ireg 11 cls_cnt 2 2006.173.16:39:36.58#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.16:39:36.64#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.16:39:36.64#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.16:39:36.64#ibcon#enter wrdev, iclass 18, count 2 2006.173.16:39:36.64#ibcon#first serial, iclass 18, count 2 2006.173.16:39:36.64#ibcon#enter sib2, iclass 18, count 2 2006.173.16:39:36.64#ibcon#flushed, iclass 18, count 2 2006.173.16:39:36.64#ibcon#about to write, iclass 18, count 2 2006.173.16:39:36.64#ibcon#wrote, iclass 18, count 2 2006.173.16:39:36.64#ibcon#about to read 3, iclass 18, count 2 2006.173.16:39:36.66#ibcon#read 3, iclass 18, count 2 2006.173.16:39:36.66#ibcon#about to read 4, iclass 18, count 2 2006.173.16:39:36.66#ibcon#read 4, iclass 18, count 2 2006.173.16:39:36.66#ibcon#about to read 5, iclass 18, count 2 2006.173.16:39:36.66#ibcon#read 5, iclass 18, count 2 2006.173.16:39:36.66#ibcon#about to read 6, iclass 18, count 2 2006.173.16:39:36.66#ibcon#read 6, iclass 18, count 2 2006.173.16:39:36.66#ibcon#end of sib2, iclass 18, count 2 2006.173.16:39:36.66#ibcon#*mode == 0, iclass 18, count 2 2006.173.16:39:36.66#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.16:39:36.66#ibcon#[25=AT02-06\r\n] 2006.173.16:39:36.66#ibcon#*before write, iclass 18, count 2 2006.173.16:39:36.66#ibcon#enter sib2, iclass 18, count 2 2006.173.16:39:36.66#ibcon#flushed, iclass 18, count 2 2006.173.16:39:36.66#ibcon#about to write, iclass 18, count 2 2006.173.16:39:36.66#ibcon#wrote, iclass 18, count 2 2006.173.16:39:36.66#ibcon#about to read 3, iclass 18, count 2 2006.173.16:39:36.69#ibcon#read 3, iclass 18, count 2 2006.173.16:39:36.69#ibcon#about to read 4, iclass 18, count 2 2006.173.16:39:36.69#ibcon#read 4, iclass 18, count 2 2006.173.16:39:36.69#ibcon#about to read 5, iclass 18, count 2 2006.173.16:39:36.69#ibcon#read 5, iclass 18, count 2 2006.173.16:39:36.69#ibcon#about to read 6, iclass 18, count 2 2006.173.16:39:36.69#ibcon#read 6, iclass 18, count 2 2006.173.16:39:36.69#ibcon#end of sib2, iclass 18, count 2 2006.173.16:39:36.69#ibcon#*after write, iclass 18, count 2 2006.173.16:39:36.69#ibcon#*before return 0, iclass 18, count 2 2006.173.16:39:36.69#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.16:39:36.69#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.16:39:36.69#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.16:39:36.69#ibcon#ireg 7 cls_cnt 0 2006.173.16:39:36.69#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.16:39:36.81#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.16:39:36.81#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.16:39:36.81#ibcon#enter wrdev, iclass 18, count 0 2006.173.16:39:36.81#ibcon#first serial, iclass 18, count 0 2006.173.16:39:36.81#ibcon#enter sib2, iclass 18, count 0 2006.173.16:39:36.81#ibcon#flushed, iclass 18, count 0 2006.173.16:39:36.81#ibcon#about to write, iclass 18, count 0 2006.173.16:39:36.81#ibcon#wrote, iclass 18, count 0 2006.173.16:39:36.81#ibcon#about to read 3, iclass 18, count 0 2006.173.16:39:36.83#ibcon#read 3, iclass 18, count 0 2006.173.16:39:36.83#ibcon#about to read 4, iclass 18, count 0 2006.173.16:39:36.83#ibcon#read 4, iclass 18, count 0 2006.173.16:39:36.83#ibcon#about to read 5, iclass 18, count 0 2006.173.16:39:36.83#ibcon#read 5, iclass 18, count 0 2006.173.16:39:36.83#ibcon#about to read 6, iclass 18, count 0 2006.173.16:39:36.83#ibcon#read 6, iclass 18, count 0 2006.173.16:39:36.83#ibcon#end of sib2, iclass 18, count 0 2006.173.16:39:36.83#ibcon#*mode == 0, iclass 18, count 0 2006.173.16:39:36.83#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.16:39:36.83#ibcon#[25=USB\r\n] 2006.173.16:39:36.83#ibcon#*before write, iclass 18, count 0 2006.173.16:39:36.83#ibcon#enter sib2, iclass 18, count 0 2006.173.16:39:36.83#ibcon#flushed, iclass 18, count 0 2006.173.16:39:36.83#ibcon#about to write, iclass 18, count 0 2006.173.16:39:36.83#ibcon#wrote, iclass 18, count 0 2006.173.16:39:36.83#ibcon#about to read 3, iclass 18, count 0 2006.173.16:39:36.86#ibcon#read 3, iclass 18, count 0 2006.173.16:39:36.86#ibcon#about to read 4, iclass 18, count 0 2006.173.16:39:36.86#ibcon#read 4, iclass 18, count 0 2006.173.16:39:36.86#ibcon#about to read 5, iclass 18, count 0 2006.173.16:39:36.86#ibcon#read 5, iclass 18, count 0 2006.173.16:39:36.86#ibcon#about to read 6, iclass 18, count 0 2006.173.16:39:36.86#ibcon#read 6, iclass 18, count 0 2006.173.16:39:36.86#ibcon#end of sib2, iclass 18, count 0 2006.173.16:39:36.86#ibcon#*after write, iclass 18, count 0 2006.173.16:39:36.86#ibcon#*before return 0, iclass 18, count 0 2006.173.16:39:36.86#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.16:39:36.86#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.16:39:36.86#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.16:39:36.86#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.16:39:36.86$vck44/valo=3,564.99 2006.173.16:39:36.86#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.16:39:36.86#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.16:39:36.86#ibcon#ireg 17 cls_cnt 0 2006.173.16:39:36.86#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.16:39:36.86#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.16:39:36.86#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.16:39:36.86#ibcon#enter wrdev, iclass 20, count 0 2006.173.16:39:36.86#ibcon#first serial, iclass 20, count 0 2006.173.16:39:36.86#ibcon#enter sib2, iclass 20, count 0 2006.173.16:39:36.86#ibcon#flushed, iclass 20, count 0 2006.173.16:39:36.86#ibcon#about to write, iclass 20, count 0 2006.173.16:39:36.86#ibcon#wrote, iclass 20, count 0 2006.173.16:39:36.86#ibcon#about to read 3, iclass 20, count 0 2006.173.16:39:36.88#ibcon#read 3, iclass 20, count 0 2006.173.16:39:36.88#ibcon#about to read 4, iclass 20, count 0 2006.173.16:39:36.88#ibcon#read 4, iclass 20, count 0 2006.173.16:39:36.88#ibcon#about to read 5, iclass 20, count 0 2006.173.16:39:36.88#ibcon#read 5, iclass 20, count 0 2006.173.16:39:36.88#ibcon#about to read 6, iclass 20, count 0 2006.173.16:39:36.88#ibcon#read 6, iclass 20, count 0 2006.173.16:39:36.88#ibcon#end of sib2, iclass 20, count 0 2006.173.16:39:36.88#ibcon#*mode == 0, iclass 20, count 0 2006.173.16:39:36.88#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.16:39:36.88#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.16:39:36.88#ibcon#*before write, iclass 20, count 0 2006.173.16:39:36.88#ibcon#enter sib2, iclass 20, count 0 2006.173.16:39:36.88#ibcon#flushed, iclass 20, count 0 2006.173.16:39:36.88#ibcon#about to write, iclass 20, count 0 2006.173.16:39:36.88#ibcon#wrote, iclass 20, count 0 2006.173.16:39:36.88#ibcon#about to read 3, iclass 20, count 0 2006.173.16:39:36.92#ibcon#read 3, iclass 20, count 0 2006.173.16:39:36.92#ibcon#about to read 4, iclass 20, count 0 2006.173.16:39:36.92#ibcon#read 4, iclass 20, count 0 2006.173.16:39:36.92#ibcon#about to read 5, iclass 20, count 0 2006.173.16:39:36.92#ibcon#read 5, iclass 20, count 0 2006.173.16:39:36.92#ibcon#about to read 6, iclass 20, count 0 2006.173.16:39:36.92#ibcon#read 6, iclass 20, count 0 2006.173.16:39:36.92#ibcon#end of sib2, iclass 20, count 0 2006.173.16:39:36.92#ibcon#*after write, iclass 20, count 0 2006.173.16:39:36.92#ibcon#*before return 0, iclass 20, count 0 2006.173.16:39:36.92#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.16:39:36.92#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.16:39:36.92#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.16:39:36.92#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.16:39:36.92$vck44/va=3,5 2006.173.16:39:36.92#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.16:39:36.92#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.16:39:36.92#ibcon#ireg 11 cls_cnt 2 2006.173.16:39:36.92#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.16:39:36.98#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.16:39:36.98#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.16:39:36.98#ibcon#enter wrdev, iclass 22, count 2 2006.173.16:39:36.98#ibcon#first serial, iclass 22, count 2 2006.173.16:39:36.98#ibcon#enter sib2, iclass 22, count 2 2006.173.16:39:36.98#ibcon#flushed, iclass 22, count 2 2006.173.16:39:36.98#ibcon#about to write, iclass 22, count 2 2006.173.16:39:36.98#ibcon#wrote, iclass 22, count 2 2006.173.16:39:36.98#ibcon#about to read 3, iclass 22, count 2 2006.173.16:39:37.00#ibcon#read 3, iclass 22, count 2 2006.173.16:39:37.00#ibcon#about to read 4, iclass 22, count 2 2006.173.16:39:37.00#ibcon#read 4, iclass 22, count 2 2006.173.16:39:37.00#ibcon#about to read 5, iclass 22, count 2 2006.173.16:39:37.00#ibcon#read 5, iclass 22, count 2 2006.173.16:39:37.00#ibcon#about to read 6, iclass 22, count 2 2006.173.16:39:37.00#ibcon#read 6, iclass 22, count 2 2006.173.16:39:37.00#ibcon#end of sib2, iclass 22, count 2 2006.173.16:39:37.00#ibcon#*mode == 0, iclass 22, count 2 2006.173.16:39:37.00#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.16:39:37.00#ibcon#[25=AT03-05\r\n] 2006.173.16:39:37.00#ibcon#*before write, iclass 22, count 2 2006.173.16:39:37.00#ibcon#enter sib2, iclass 22, count 2 2006.173.16:39:37.00#ibcon#flushed, iclass 22, count 2 2006.173.16:39:37.00#ibcon#about to write, iclass 22, count 2 2006.173.16:39:37.00#ibcon#wrote, iclass 22, count 2 2006.173.16:39:37.00#ibcon#about to read 3, iclass 22, count 2 2006.173.16:39:37.03#ibcon#read 3, iclass 22, count 2 2006.173.16:39:37.03#ibcon#about to read 4, iclass 22, count 2 2006.173.16:39:37.03#ibcon#read 4, iclass 22, count 2 2006.173.16:39:37.03#ibcon#about to read 5, iclass 22, count 2 2006.173.16:39:37.03#ibcon#read 5, iclass 22, count 2 2006.173.16:39:37.03#ibcon#about to read 6, iclass 22, count 2 2006.173.16:39:37.03#ibcon#read 6, iclass 22, count 2 2006.173.16:39:37.03#ibcon#end of sib2, iclass 22, count 2 2006.173.16:39:37.03#ibcon#*after write, iclass 22, count 2 2006.173.16:39:37.03#ibcon#*before return 0, iclass 22, count 2 2006.173.16:39:37.03#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.16:39:37.03#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.16:39:37.03#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.16:39:37.03#ibcon#ireg 7 cls_cnt 0 2006.173.16:39:37.03#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.16:39:37.15#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.16:39:37.15#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.16:39:37.15#ibcon#enter wrdev, iclass 22, count 0 2006.173.16:39:37.15#ibcon#first serial, iclass 22, count 0 2006.173.16:39:37.15#ibcon#enter sib2, iclass 22, count 0 2006.173.16:39:37.15#ibcon#flushed, iclass 22, count 0 2006.173.16:39:37.15#ibcon#about to write, iclass 22, count 0 2006.173.16:39:37.15#ibcon#wrote, iclass 22, count 0 2006.173.16:39:37.15#ibcon#about to read 3, iclass 22, count 0 2006.173.16:39:37.17#ibcon#read 3, iclass 22, count 0 2006.173.16:39:37.17#ibcon#about to read 4, iclass 22, count 0 2006.173.16:39:37.17#ibcon#read 4, iclass 22, count 0 2006.173.16:39:37.17#ibcon#about to read 5, iclass 22, count 0 2006.173.16:39:37.17#ibcon#read 5, iclass 22, count 0 2006.173.16:39:37.17#ibcon#about to read 6, iclass 22, count 0 2006.173.16:39:37.17#ibcon#read 6, iclass 22, count 0 2006.173.16:39:37.17#ibcon#end of sib2, iclass 22, count 0 2006.173.16:39:37.17#ibcon#*mode == 0, iclass 22, count 0 2006.173.16:39:37.17#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.16:39:37.17#ibcon#[25=USB\r\n] 2006.173.16:39:37.17#ibcon#*before write, iclass 22, count 0 2006.173.16:39:37.17#ibcon#enter sib2, iclass 22, count 0 2006.173.16:39:37.17#ibcon#flushed, iclass 22, count 0 2006.173.16:39:37.17#ibcon#about to write, iclass 22, count 0 2006.173.16:39:37.17#ibcon#wrote, iclass 22, count 0 2006.173.16:39:37.17#ibcon#about to read 3, iclass 22, count 0 2006.173.16:39:37.20#ibcon#read 3, iclass 22, count 0 2006.173.16:39:37.20#ibcon#about to read 4, iclass 22, count 0 2006.173.16:39:37.20#ibcon#read 4, iclass 22, count 0 2006.173.16:39:37.20#ibcon#about to read 5, iclass 22, count 0 2006.173.16:39:37.20#ibcon#read 5, iclass 22, count 0 2006.173.16:39:37.20#ibcon#about to read 6, iclass 22, count 0 2006.173.16:39:37.20#ibcon#read 6, iclass 22, count 0 2006.173.16:39:37.20#ibcon#end of sib2, iclass 22, count 0 2006.173.16:39:37.20#ibcon#*after write, iclass 22, count 0 2006.173.16:39:37.20#ibcon#*before return 0, iclass 22, count 0 2006.173.16:39:37.20#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.16:39:37.20#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.16:39:37.20#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.16:39:37.20#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.16:39:37.20$vck44/valo=4,624.99 2006.173.16:39:37.20#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.16:39:37.20#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.16:39:37.20#ibcon#ireg 17 cls_cnt 0 2006.173.16:39:37.20#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.16:39:37.20#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.16:39:37.20#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.16:39:37.20#ibcon#enter wrdev, iclass 24, count 0 2006.173.16:39:37.20#ibcon#first serial, iclass 24, count 0 2006.173.16:39:37.20#ibcon#enter sib2, iclass 24, count 0 2006.173.16:39:37.20#ibcon#flushed, iclass 24, count 0 2006.173.16:39:37.20#ibcon#about to write, iclass 24, count 0 2006.173.16:39:37.20#ibcon#wrote, iclass 24, count 0 2006.173.16:39:37.20#ibcon#about to read 3, iclass 24, count 0 2006.173.16:39:37.22#ibcon#read 3, iclass 24, count 0 2006.173.16:39:37.22#ibcon#about to read 4, iclass 24, count 0 2006.173.16:39:37.22#ibcon#read 4, iclass 24, count 0 2006.173.16:39:37.22#ibcon#about to read 5, iclass 24, count 0 2006.173.16:39:37.22#ibcon#read 5, iclass 24, count 0 2006.173.16:39:37.22#ibcon#about to read 6, iclass 24, count 0 2006.173.16:39:37.22#ibcon#read 6, iclass 24, count 0 2006.173.16:39:37.22#ibcon#end of sib2, iclass 24, count 0 2006.173.16:39:37.22#ibcon#*mode == 0, iclass 24, count 0 2006.173.16:39:37.22#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.16:39:37.22#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.16:39:37.22#ibcon#*before write, iclass 24, count 0 2006.173.16:39:37.22#ibcon#enter sib2, iclass 24, count 0 2006.173.16:39:37.22#ibcon#flushed, iclass 24, count 0 2006.173.16:39:37.22#ibcon#about to write, iclass 24, count 0 2006.173.16:39:37.22#ibcon#wrote, iclass 24, count 0 2006.173.16:39:37.22#ibcon#about to read 3, iclass 24, count 0 2006.173.16:39:37.26#ibcon#read 3, iclass 24, count 0 2006.173.16:39:37.26#ibcon#about to read 4, iclass 24, count 0 2006.173.16:39:37.26#ibcon#read 4, iclass 24, count 0 2006.173.16:39:37.26#ibcon#about to read 5, iclass 24, count 0 2006.173.16:39:37.26#ibcon#read 5, iclass 24, count 0 2006.173.16:39:37.26#ibcon#about to read 6, iclass 24, count 0 2006.173.16:39:37.26#ibcon#read 6, iclass 24, count 0 2006.173.16:39:37.26#ibcon#end of sib2, iclass 24, count 0 2006.173.16:39:37.26#ibcon#*after write, iclass 24, count 0 2006.173.16:39:37.26#ibcon#*before return 0, iclass 24, count 0 2006.173.16:39:37.26#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.16:39:37.26#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.16:39:37.26#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.16:39:37.26#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.16:39:37.26$vck44/va=4,6 2006.173.16:39:37.26#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.16:39:37.26#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.16:39:37.26#ibcon#ireg 11 cls_cnt 2 2006.173.16:39:37.26#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.16:39:37.32#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.16:39:37.32#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.16:39:37.32#ibcon#enter wrdev, iclass 26, count 2 2006.173.16:39:37.32#ibcon#first serial, iclass 26, count 2 2006.173.16:39:37.32#ibcon#enter sib2, iclass 26, count 2 2006.173.16:39:37.32#ibcon#flushed, iclass 26, count 2 2006.173.16:39:37.32#ibcon#about to write, iclass 26, count 2 2006.173.16:39:37.32#ibcon#wrote, iclass 26, count 2 2006.173.16:39:37.32#ibcon#about to read 3, iclass 26, count 2 2006.173.16:39:37.34#ibcon#read 3, iclass 26, count 2 2006.173.16:39:37.34#ibcon#about to read 4, iclass 26, count 2 2006.173.16:39:37.34#ibcon#read 4, iclass 26, count 2 2006.173.16:39:37.34#ibcon#about to read 5, iclass 26, count 2 2006.173.16:39:37.34#ibcon#read 5, iclass 26, count 2 2006.173.16:39:37.34#ibcon#about to read 6, iclass 26, count 2 2006.173.16:39:37.34#ibcon#read 6, iclass 26, count 2 2006.173.16:39:37.34#ibcon#end of sib2, iclass 26, count 2 2006.173.16:39:37.34#ibcon#*mode == 0, iclass 26, count 2 2006.173.16:39:37.34#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.16:39:37.34#ibcon#[25=AT04-06\r\n] 2006.173.16:39:37.34#ibcon#*before write, iclass 26, count 2 2006.173.16:39:37.34#ibcon#enter sib2, iclass 26, count 2 2006.173.16:39:37.34#ibcon#flushed, iclass 26, count 2 2006.173.16:39:37.34#ibcon#about to write, iclass 26, count 2 2006.173.16:39:37.34#ibcon#wrote, iclass 26, count 2 2006.173.16:39:37.34#ibcon#about to read 3, iclass 26, count 2 2006.173.16:39:37.37#ibcon#read 3, iclass 26, count 2 2006.173.16:39:37.37#ibcon#about to read 4, iclass 26, count 2 2006.173.16:39:37.37#ibcon#read 4, iclass 26, count 2 2006.173.16:39:37.37#ibcon#about to read 5, iclass 26, count 2 2006.173.16:39:37.37#ibcon#read 5, iclass 26, count 2 2006.173.16:39:37.37#ibcon#about to read 6, iclass 26, count 2 2006.173.16:39:37.37#ibcon#read 6, iclass 26, count 2 2006.173.16:39:37.37#ibcon#end of sib2, iclass 26, count 2 2006.173.16:39:37.37#ibcon#*after write, iclass 26, count 2 2006.173.16:39:37.37#ibcon#*before return 0, iclass 26, count 2 2006.173.16:39:37.37#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.16:39:37.37#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.16:39:37.37#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.16:39:37.37#ibcon#ireg 7 cls_cnt 0 2006.173.16:39:37.37#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.16:39:37.49#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.16:39:37.49#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.16:39:37.49#ibcon#enter wrdev, iclass 26, count 0 2006.173.16:39:37.49#ibcon#first serial, iclass 26, count 0 2006.173.16:39:37.49#ibcon#enter sib2, iclass 26, count 0 2006.173.16:39:37.49#ibcon#flushed, iclass 26, count 0 2006.173.16:39:37.49#ibcon#about to write, iclass 26, count 0 2006.173.16:39:37.49#ibcon#wrote, iclass 26, count 0 2006.173.16:39:37.49#ibcon#about to read 3, iclass 26, count 0 2006.173.16:39:37.51#ibcon#read 3, iclass 26, count 0 2006.173.16:39:37.51#ibcon#about to read 4, iclass 26, count 0 2006.173.16:39:37.51#ibcon#read 4, iclass 26, count 0 2006.173.16:39:37.51#ibcon#about to read 5, iclass 26, count 0 2006.173.16:39:37.51#ibcon#read 5, iclass 26, count 0 2006.173.16:39:37.51#ibcon#about to read 6, iclass 26, count 0 2006.173.16:39:37.51#ibcon#read 6, iclass 26, count 0 2006.173.16:39:37.51#ibcon#end of sib2, iclass 26, count 0 2006.173.16:39:37.51#ibcon#*mode == 0, iclass 26, count 0 2006.173.16:39:37.51#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.16:39:37.51#ibcon#[25=USB\r\n] 2006.173.16:39:37.51#ibcon#*before write, iclass 26, count 0 2006.173.16:39:37.51#ibcon#enter sib2, iclass 26, count 0 2006.173.16:39:37.51#ibcon#flushed, iclass 26, count 0 2006.173.16:39:37.51#ibcon#about to write, iclass 26, count 0 2006.173.16:39:37.51#ibcon#wrote, iclass 26, count 0 2006.173.16:39:37.51#ibcon#about to read 3, iclass 26, count 0 2006.173.16:39:37.54#ibcon#read 3, iclass 26, count 0 2006.173.16:39:37.54#ibcon#about to read 4, iclass 26, count 0 2006.173.16:39:37.54#ibcon#read 4, iclass 26, count 0 2006.173.16:39:37.54#ibcon#about to read 5, iclass 26, count 0 2006.173.16:39:37.54#ibcon#read 5, iclass 26, count 0 2006.173.16:39:37.54#ibcon#about to read 6, iclass 26, count 0 2006.173.16:39:37.54#ibcon#read 6, iclass 26, count 0 2006.173.16:39:37.54#ibcon#end of sib2, iclass 26, count 0 2006.173.16:39:37.54#ibcon#*after write, iclass 26, count 0 2006.173.16:39:37.54#ibcon#*before return 0, iclass 26, count 0 2006.173.16:39:37.54#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.16:39:37.54#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.16:39:37.54#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.16:39:37.54#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.16:39:37.54$vck44/valo=5,734.99 2006.173.16:39:37.54#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.16:39:37.54#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.16:39:37.54#ibcon#ireg 17 cls_cnt 0 2006.173.16:39:37.54#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.16:39:37.54#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.16:39:37.54#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.16:39:37.54#ibcon#enter wrdev, iclass 28, count 0 2006.173.16:39:37.54#ibcon#first serial, iclass 28, count 0 2006.173.16:39:37.54#ibcon#enter sib2, iclass 28, count 0 2006.173.16:39:37.54#ibcon#flushed, iclass 28, count 0 2006.173.16:39:37.54#ibcon#about to write, iclass 28, count 0 2006.173.16:39:37.54#ibcon#wrote, iclass 28, count 0 2006.173.16:39:37.54#ibcon#about to read 3, iclass 28, count 0 2006.173.16:39:37.56#ibcon#read 3, iclass 28, count 0 2006.173.16:39:37.56#ibcon#about to read 4, iclass 28, count 0 2006.173.16:39:37.56#ibcon#read 4, iclass 28, count 0 2006.173.16:39:37.56#ibcon#about to read 5, iclass 28, count 0 2006.173.16:39:37.56#ibcon#read 5, iclass 28, count 0 2006.173.16:39:37.56#ibcon#about to read 6, iclass 28, count 0 2006.173.16:39:37.56#ibcon#read 6, iclass 28, count 0 2006.173.16:39:37.56#ibcon#end of sib2, iclass 28, count 0 2006.173.16:39:37.56#ibcon#*mode == 0, iclass 28, count 0 2006.173.16:39:37.56#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.16:39:37.56#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.16:39:37.56#ibcon#*before write, iclass 28, count 0 2006.173.16:39:37.56#ibcon#enter sib2, iclass 28, count 0 2006.173.16:39:37.56#ibcon#flushed, iclass 28, count 0 2006.173.16:39:37.56#ibcon#about to write, iclass 28, count 0 2006.173.16:39:37.56#ibcon#wrote, iclass 28, count 0 2006.173.16:39:37.56#ibcon#about to read 3, iclass 28, count 0 2006.173.16:39:37.60#ibcon#read 3, iclass 28, count 0 2006.173.16:39:37.60#ibcon#about to read 4, iclass 28, count 0 2006.173.16:39:37.60#ibcon#read 4, iclass 28, count 0 2006.173.16:39:37.60#ibcon#about to read 5, iclass 28, count 0 2006.173.16:39:37.60#ibcon#read 5, iclass 28, count 0 2006.173.16:39:37.60#ibcon#about to read 6, iclass 28, count 0 2006.173.16:39:37.60#ibcon#read 6, iclass 28, count 0 2006.173.16:39:37.60#ibcon#end of sib2, iclass 28, count 0 2006.173.16:39:37.60#ibcon#*after write, iclass 28, count 0 2006.173.16:39:37.60#ibcon#*before return 0, iclass 28, count 0 2006.173.16:39:37.60#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.16:39:37.60#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.16:39:37.60#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.16:39:37.60#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.16:39:37.60$vck44/va=5,4 2006.173.16:39:37.60#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.16:39:37.60#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.16:39:37.60#ibcon#ireg 11 cls_cnt 2 2006.173.16:39:37.60#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.16:39:37.66#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.16:39:37.66#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.16:39:37.66#ibcon#enter wrdev, iclass 30, count 2 2006.173.16:39:37.66#ibcon#first serial, iclass 30, count 2 2006.173.16:39:37.66#ibcon#enter sib2, iclass 30, count 2 2006.173.16:39:37.66#ibcon#flushed, iclass 30, count 2 2006.173.16:39:37.66#ibcon#about to write, iclass 30, count 2 2006.173.16:39:37.66#ibcon#wrote, iclass 30, count 2 2006.173.16:39:37.66#ibcon#about to read 3, iclass 30, count 2 2006.173.16:39:37.68#ibcon#read 3, iclass 30, count 2 2006.173.16:39:37.68#ibcon#about to read 4, iclass 30, count 2 2006.173.16:39:37.68#ibcon#read 4, iclass 30, count 2 2006.173.16:39:37.68#ibcon#about to read 5, iclass 30, count 2 2006.173.16:39:37.68#ibcon#read 5, iclass 30, count 2 2006.173.16:39:37.68#ibcon#about to read 6, iclass 30, count 2 2006.173.16:39:37.68#ibcon#read 6, iclass 30, count 2 2006.173.16:39:37.68#ibcon#end of sib2, iclass 30, count 2 2006.173.16:39:37.68#ibcon#*mode == 0, iclass 30, count 2 2006.173.16:39:37.68#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.16:39:37.68#ibcon#[25=AT05-04\r\n] 2006.173.16:39:37.68#ibcon#*before write, iclass 30, count 2 2006.173.16:39:37.68#ibcon#enter sib2, iclass 30, count 2 2006.173.16:39:37.68#ibcon#flushed, iclass 30, count 2 2006.173.16:39:37.68#ibcon#about to write, iclass 30, count 2 2006.173.16:39:37.68#ibcon#wrote, iclass 30, count 2 2006.173.16:39:37.68#ibcon#about to read 3, iclass 30, count 2 2006.173.16:39:37.71#ibcon#read 3, iclass 30, count 2 2006.173.16:39:37.71#ibcon#about to read 4, iclass 30, count 2 2006.173.16:39:37.71#ibcon#read 4, iclass 30, count 2 2006.173.16:39:37.71#ibcon#about to read 5, iclass 30, count 2 2006.173.16:39:37.71#ibcon#read 5, iclass 30, count 2 2006.173.16:39:37.71#ibcon#about to read 6, iclass 30, count 2 2006.173.16:39:37.71#ibcon#read 6, iclass 30, count 2 2006.173.16:39:37.71#ibcon#end of sib2, iclass 30, count 2 2006.173.16:39:37.71#ibcon#*after write, iclass 30, count 2 2006.173.16:39:37.71#ibcon#*before return 0, iclass 30, count 2 2006.173.16:39:37.71#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.16:39:37.71#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.16:39:37.71#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.16:39:37.71#ibcon#ireg 7 cls_cnt 0 2006.173.16:39:37.71#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.16:39:37.83#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.16:39:37.83#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.16:39:37.83#ibcon#enter wrdev, iclass 30, count 0 2006.173.16:39:37.83#ibcon#first serial, iclass 30, count 0 2006.173.16:39:37.83#ibcon#enter sib2, iclass 30, count 0 2006.173.16:39:37.83#ibcon#flushed, iclass 30, count 0 2006.173.16:39:37.83#ibcon#about to write, iclass 30, count 0 2006.173.16:39:37.83#ibcon#wrote, iclass 30, count 0 2006.173.16:39:37.83#ibcon#about to read 3, iclass 30, count 0 2006.173.16:39:37.85#ibcon#read 3, iclass 30, count 0 2006.173.16:39:37.85#ibcon#about to read 4, iclass 30, count 0 2006.173.16:39:37.85#ibcon#read 4, iclass 30, count 0 2006.173.16:39:37.85#ibcon#about to read 5, iclass 30, count 0 2006.173.16:39:37.85#ibcon#read 5, iclass 30, count 0 2006.173.16:39:37.85#ibcon#about to read 6, iclass 30, count 0 2006.173.16:39:37.85#ibcon#read 6, iclass 30, count 0 2006.173.16:39:37.85#ibcon#end of sib2, iclass 30, count 0 2006.173.16:39:37.85#ibcon#*mode == 0, iclass 30, count 0 2006.173.16:39:37.85#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.16:39:37.85#ibcon#[25=USB\r\n] 2006.173.16:39:37.85#ibcon#*before write, iclass 30, count 0 2006.173.16:39:37.85#ibcon#enter sib2, iclass 30, count 0 2006.173.16:39:37.85#ibcon#flushed, iclass 30, count 0 2006.173.16:39:37.85#ibcon#about to write, iclass 30, count 0 2006.173.16:39:37.85#ibcon#wrote, iclass 30, count 0 2006.173.16:39:37.85#ibcon#about to read 3, iclass 30, count 0 2006.173.16:39:37.88#ibcon#read 3, iclass 30, count 0 2006.173.16:39:37.88#ibcon#about to read 4, iclass 30, count 0 2006.173.16:39:37.88#ibcon#read 4, iclass 30, count 0 2006.173.16:39:37.88#ibcon#about to read 5, iclass 30, count 0 2006.173.16:39:37.88#ibcon#read 5, iclass 30, count 0 2006.173.16:39:37.88#ibcon#about to read 6, iclass 30, count 0 2006.173.16:39:37.88#ibcon#read 6, iclass 30, count 0 2006.173.16:39:37.88#ibcon#end of sib2, iclass 30, count 0 2006.173.16:39:37.88#ibcon#*after write, iclass 30, count 0 2006.173.16:39:37.88#ibcon#*before return 0, iclass 30, count 0 2006.173.16:39:37.88#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.16:39:37.88#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.16:39:37.88#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.16:39:37.88#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.16:39:37.88$vck44/valo=6,814.99 2006.173.16:39:37.88#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.16:39:37.88#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.16:39:37.88#ibcon#ireg 17 cls_cnt 0 2006.173.16:39:37.88#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.16:39:37.88#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.16:39:37.88#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.16:39:37.88#ibcon#enter wrdev, iclass 32, count 0 2006.173.16:39:37.88#ibcon#first serial, iclass 32, count 0 2006.173.16:39:37.88#ibcon#enter sib2, iclass 32, count 0 2006.173.16:39:37.88#ibcon#flushed, iclass 32, count 0 2006.173.16:39:37.88#ibcon#about to write, iclass 32, count 0 2006.173.16:39:37.88#ibcon#wrote, iclass 32, count 0 2006.173.16:39:37.88#ibcon#about to read 3, iclass 32, count 0 2006.173.16:39:37.90#ibcon#read 3, iclass 32, count 0 2006.173.16:39:37.90#ibcon#about to read 4, iclass 32, count 0 2006.173.16:39:37.90#ibcon#read 4, iclass 32, count 0 2006.173.16:39:37.90#ibcon#about to read 5, iclass 32, count 0 2006.173.16:39:37.90#ibcon#read 5, iclass 32, count 0 2006.173.16:39:37.90#ibcon#about to read 6, iclass 32, count 0 2006.173.16:39:37.90#ibcon#read 6, iclass 32, count 0 2006.173.16:39:37.90#ibcon#end of sib2, iclass 32, count 0 2006.173.16:39:37.90#ibcon#*mode == 0, iclass 32, count 0 2006.173.16:39:37.90#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.16:39:37.90#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.16:39:37.90#ibcon#*before write, iclass 32, count 0 2006.173.16:39:37.90#ibcon#enter sib2, iclass 32, count 0 2006.173.16:39:37.90#ibcon#flushed, iclass 32, count 0 2006.173.16:39:37.90#ibcon#about to write, iclass 32, count 0 2006.173.16:39:37.90#ibcon#wrote, iclass 32, count 0 2006.173.16:39:37.90#ibcon#about to read 3, iclass 32, count 0 2006.173.16:39:37.94#ibcon#read 3, iclass 32, count 0 2006.173.16:39:37.94#ibcon#about to read 4, iclass 32, count 0 2006.173.16:39:37.94#ibcon#read 4, iclass 32, count 0 2006.173.16:39:37.94#ibcon#about to read 5, iclass 32, count 0 2006.173.16:39:37.94#ibcon#read 5, iclass 32, count 0 2006.173.16:39:37.94#ibcon#about to read 6, iclass 32, count 0 2006.173.16:39:37.94#ibcon#read 6, iclass 32, count 0 2006.173.16:39:37.94#ibcon#end of sib2, iclass 32, count 0 2006.173.16:39:37.94#ibcon#*after write, iclass 32, count 0 2006.173.16:39:37.94#ibcon#*before return 0, iclass 32, count 0 2006.173.16:39:37.94#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.16:39:37.94#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.16:39:37.94#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.16:39:37.94#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.16:39:37.94$vck44/va=6,3 2006.173.16:39:37.94#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.16:39:37.94#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.16:39:37.94#ibcon#ireg 11 cls_cnt 2 2006.173.16:39:37.94#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.16:39:38.00#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.16:39:38.00#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.16:39:38.00#ibcon#enter wrdev, iclass 34, count 2 2006.173.16:39:38.00#ibcon#first serial, iclass 34, count 2 2006.173.16:39:38.00#ibcon#enter sib2, iclass 34, count 2 2006.173.16:39:38.00#ibcon#flushed, iclass 34, count 2 2006.173.16:39:38.00#ibcon#about to write, iclass 34, count 2 2006.173.16:39:38.00#ibcon#wrote, iclass 34, count 2 2006.173.16:39:38.00#ibcon#about to read 3, iclass 34, count 2 2006.173.16:39:38.02#ibcon#read 3, iclass 34, count 2 2006.173.16:39:38.02#ibcon#about to read 4, iclass 34, count 2 2006.173.16:39:38.02#ibcon#read 4, iclass 34, count 2 2006.173.16:39:38.02#ibcon#about to read 5, iclass 34, count 2 2006.173.16:39:38.02#ibcon#read 5, iclass 34, count 2 2006.173.16:39:38.02#ibcon#about to read 6, iclass 34, count 2 2006.173.16:39:38.02#ibcon#read 6, iclass 34, count 2 2006.173.16:39:38.02#ibcon#end of sib2, iclass 34, count 2 2006.173.16:39:38.02#ibcon#*mode == 0, iclass 34, count 2 2006.173.16:39:38.02#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.16:39:38.02#ibcon#[25=AT06-03\r\n] 2006.173.16:39:38.02#ibcon#*before write, iclass 34, count 2 2006.173.16:39:38.02#ibcon#enter sib2, iclass 34, count 2 2006.173.16:39:38.02#ibcon#flushed, iclass 34, count 2 2006.173.16:39:38.02#ibcon#about to write, iclass 34, count 2 2006.173.16:39:38.02#ibcon#wrote, iclass 34, count 2 2006.173.16:39:38.02#ibcon#about to read 3, iclass 34, count 2 2006.173.16:39:38.05#ibcon#read 3, iclass 34, count 2 2006.173.16:39:38.05#ibcon#about to read 4, iclass 34, count 2 2006.173.16:39:38.05#ibcon#read 4, iclass 34, count 2 2006.173.16:39:38.05#ibcon#about to read 5, iclass 34, count 2 2006.173.16:39:38.05#ibcon#read 5, iclass 34, count 2 2006.173.16:39:38.05#ibcon#about to read 6, iclass 34, count 2 2006.173.16:39:38.05#ibcon#read 6, iclass 34, count 2 2006.173.16:39:38.05#ibcon#end of sib2, iclass 34, count 2 2006.173.16:39:38.05#ibcon#*after write, iclass 34, count 2 2006.173.16:39:38.05#ibcon#*before return 0, iclass 34, count 2 2006.173.16:39:38.05#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.16:39:38.05#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.16:39:38.05#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.16:39:38.05#ibcon#ireg 7 cls_cnt 0 2006.173.16:39:38.05#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.16:39:38.17#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.16:39:38.17#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.16:39:38.17#ibcon#enter wrdev, iclass 34, count 0 2006.173.16:39:38.17#ibcon#first serial, iclass 34, count 0 2006.173.16:39:38.17#ibcon#enter sib2, iclass 34, count 0 2006.173.16:39:38.17#ibcon#flushed, iclass 34, count 0 2006.173.16:39:38.17#ibcon#about to write, iclass 34, count 0 2006.173.16:39:38.17#ibcon#wrote, iclass 34, count 0 2006.173.16:39:38.17#ibcon#about to read 3, iclass 34, count 0 2006.173.16:39:38.19#ibcon#read 3, iclass 34, count 0 2006.173.16:39:38.19#ibcon#about to read 4, iclass 34, count 0 2006.173.16:39:38.19#ibcon#read 4, iclass 34, count 0 2006.173.16:39:38.19#ibcon#about to read 5, iclass 34, count 0 2006.173.16:39:38.19#ibcon#read 5, iclass 34, count 0 2006.173.16:39:38.19#ibcon#about to read 6, iclass 34, count 0 2006.173.16:39:38.19#ibcon#read 6, iclass 34, count 0 2006.173.16:39:38.19#ibcon#end of sib2, iclass 34, count 0 2006.173.16:39:38.19#ibcon#*mode == 0, iclass 34, count 0 2006.173.16:39:38.19#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.16:39:38.19#ibcon#[25=USB\r\n] 2006.173.16:39:38.19#ibcon#*before write, iclass 34, count 0 2006.173.16:39:38.19#ibcon#enter sib2, iclass 34, count 0 2006.173.16:39:38.19#ibcon#flushed, iclass 34, count 0 2006.173.16:39:38.19#ibcon#about to write, iclass 34, count 0 2006.173.16:39:38.19#ibcon#wrote, iclass 34, count 0 2006.173.16:39:38.19#ibcon#about to read 3, iclass 34, count 0 2006.173.16:39:38.22#ibcon#read 3, iclass 34, count 0 2006.173.16:39:38.22#ibcon#about to read 4, iclass 34, count 0 2006.173.16:39:38.22#ibcon#read 4, iclass 34, count 0 2006.173.16:39:38.22#ibcon#about to read 5, iclass 34, count 0 2006.173.16:39:38.22#ibcon#read 5, iclass 34, count 0 2006.173.16:39:38.22#ibcon#about to read 6, iclass 34, count 0 2006.173.16:39:38.22#ibcon#read 6, iclass 34, count 0 2006.173.16:39:38.22#ibcon#end of sib2, iclass 34, count 0 2006.173.16:39:38.22#ibcon#*after write, iclass 34, count 0 2006.173.16:39:38.22#ibcon#*before return 0, iclass 34, count 0 2006.173.16:39:38.22#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.16:39:38.22#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.16:39:38.22#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.16:39:38.22#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.16:39:38.22$vck44/valo=7,864.99 2006.173.16:39:38.22#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.16:39:38.22#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.16:39:38.22#ibcon#ireg 17 cls_cnt 0 2006.173.16:39:38.22#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.16:39:38.22#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.16:39:38.22#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.16:39:38.22#ibcon#enter wrdev, iclass 36, count 0 2006.173.16:39:38.22#ibcon#first serial, iclass 36, count 0 2006.173.16:39:38.22#ibcon#enter sib2, iclass 36, count 0 2006.173.16:39:38.22#ibcon#flushed, iclass 36, count 0 2006.173.16:39:38.22#ibcon#about to write, iclass 36, count 0 2006.173.16:39:38.22#ibcon#wrote, iclass 36, count 0 2006.173.16:39:38.22#ibcon#about to read 3, iclass 36, count 0 2006.173.16:39:38.24#ibcon#read 3, iclass 36, count 0 2006.173.16:39:38.24#ibcon#about to read 4, iclass 36, count 0 2006.173.16:39:38.24#ibcon#read 4, iclass 36, count 0 2006.173.16:39:38.24#ibcon#about to read 5, iclass 36, count 0 2006.173.16:39:38.24#ibcon#read 5, iclass 36, count 0 2006.173.16:39:38.24#ibcon#about to read 6, iclass 36, count 0 2006.173.16:39:38.24#ibcon#read 6, iclass 36, count 0 2006.173.16:39:38.24#ibcon#end of sib2, iclass 36, count 0 2006.173.16:39:38.24#ibcon#*mode == 0, iclass 36, count 0 2006.173.16:39:38.24#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.16:39:38.24#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.16:39:38.24#ibcon#*before write, iclass 36, count 0 2006.173.16:39:38.24#ibcon#enter sib2, iclass 36, count 0 2006.173.16:39:38.24#ibcon#flushed, iclass 36, count 0 2006.173.16:39:38.24#ibcon#about to write, iclass 36, count 0 2006.173.16:39:38.24#ibcon#wrote, iclass 36, count 0 2006.173.16:39:38.24#ibcon#about to read 3, iclass 36, count 0 2006.173.16:39:38.28#ibcon#read 3, iclass 36, count 0 2006.173.16:39:38.28#ibcon#about to read 4, iclass 36, count 0 2006.173.16:39:38.28#ibcon#read 4, iclass 36, count 0 2006.173.16:39:38.28#ibcon#about to read 5, iclass 36, count 0 2006.173.16:39:38.28#ibcon#read 5, iclass 36, count 0 2006.173.16:39:38.28#ibcon#about to read 6, iclass 36, count 0 2006.173.16:39:38.28#ibcon#read 6, iclass 36, count 0 2006.173.16:39:38.28#ibcon#end of sib2, iclass 36, count 0 2006.173.16:39:38.28#ibcon#*after write, iclass 36, count 0 2006.173.16:39:38.28#ibcon#*before return 0, iclass 36, count 0 2006.173.16:39:38.28#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.16:39:38.28#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.16:39:38.28#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.16:39:38.28#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.16:39:38.28$vck44/va=7,4 2006.173.16:39:38.28#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.16:39:38.28#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.16:39:38.28#ibcon#ireg 11 cls_cnt 2 2006.173.16:39:38.28#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.16:39:38.31#abcon#<5=/13 0.4 1.1 20.411001002.8\r\n> 2006.173.16:39:38.33#abcon#{5=INTERFACE CLEAR} 2006.173.16:39:38.34#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.16:39:38.34#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.16:39:38.34#ibcon#enter wrdev, iclass 39, count 2 2006.173.16:39:38.34#ibcon#first serial, iclass 39, count 2 2006.173.16:39:38.34#ibcon#enter sib2, iclass 39, count 2 2006.173.16:39:38.34#ibcon#flushed, iclass 39, count 2 2006.173.16:39:38.34#ibcon#about to write, iclass 39, count 2 2006.173.16:39:38.34#ibcon#wrote, iclass 39, count 2 2006.173.16:39:38.34#ibcon#about to read 3, iclass 39, count 2 2006.173.16:39:38.36#ibcon#read 3, iclass 39, count 2 2006.173.16:39:38.36#ibcon#about to read 4, iclass 39, count 2 2006.173.16:39:38.36#ibcon#read 4, iclass 39, count 2 2006.173.16:39:38.36#ibcon#about to read 5, iclass 39, count 2 2006.173.16:39:38.36#ibcon#read 5, iclass 39, count 2 2006.173.16:39:38.36#ibcon#about to read 6, iclass 39, count 2 2006.173.16:39:38.36#ibcon#read 6, iclass 39, count 2 2006.173.16:39:38.36#ibcon#end of sib2, iclass 39, count 2 2006.173.16:39:38.36#ibcon#*mode == 0, iclass 39, count 2 2006.173.16:39:38.36#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.16:39:38.36#ibcon#[25=AT07-04\r\n] 2006.173.16:39:38.36#ibcon#*before write, iclass 39, count 2 2006.173.16:39:38.36#ibcon#enter sib2, iclass 39, count 2 2006.173.16:39:38.36#ibcon#flushed, iclass 39, count 2 2006.173.16:39:38.36#ibcon#about to write, iclass 39, count 2 2006.173.16:39:38.36#ibcon#wrote, iclass 39, count 2 2006.173.16:39:38.36#ibcon#about to read 3, iclass 39, count 2 2006.173.16:39:38.39#abcon#[5=S1D000X0/0*\r\n] 2006.173.16:39:38.39#ibcon#read 3, iclass 39, count 2 2006.173.16:39:38.39#ibcon#about to read 4, iclass 39, count 2 2006.173.16:39:38.39#ibcon#read 4, iclass 39, count 2 2006.173.16:39:38.39#ibcon#about to read 5, iclass 39, count 2 2006.173.16:39:38.39#ibcon#read 5, iclass 39, count 2 2006.173.16:39:38.39#ibcon#about to read 6, iclass 39, count 2 2006.173.16:39:38.39#ibcon#read 6, iclass 39, count 2 2006.173.16:39:38.39#ibcon#end of sib2, iclass 39, count 2 2006.173.16:39:38.39#ibcon#*after write, iclass 39, count 2 2006.173.16:39:38.39#ibcon#*before return 0, iclass 39, count 2 2006.173.16:39:38.39#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.16:39:38.39#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.16:39:38.39#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.16:39:38.39#ibcon#ireg 7 cls_cnt 0 2006.173.16:39:38.39#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.16:39:38.51#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.16:39:38.51#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.16:39:38.51#ibcon#enter wrdev, iclass 39, count 0 2006.173.16:39:38.51#ibcon#first serial, iclass 39, count 0 2006.173.16:39:38.51#ibcon#enter sib2, iclass 39, count 0 2006.173.16:39:38.51#ibcon#flushed, iclass 39, count 0 2006.173.16:39:38.51#ibcon#about to write, iclass 39, count 0 2006.173.16:39:38.51#ibcon#wrote, iclass 39, count 0 2006.173.16:39:38.51#ibcon#about to read 3, iclass 39, count 0 2006.173.16:39:38.53#ibcon#read 3, iclass 39, count 0 2006.173.16:39:38.53#ibcon#about to read 4, iclass 39, count 0 2006.173.16:39:38.53#ibcon#read 4, iclass 39, count 0 2006.173.16:39:38.53#ibcon#about to read 5, iclass 39, count 0 2006.173.16:39:38.53#ibcon#read 5, iclass 39, count 0 2006.173.16:39:38.53#ibcon#about to read 6, iclass 39, count 0 2006.173.16:39:38.53#ibcon#read 6, iclass 39, count 0 2006.173.16:39:38.53#ibcon#end of sib2, iclass 39, count 0 2006.173.16:39:38.53#ibcon#*mode == 0, iclass 39, count 0 2006.173.16:39:38.53#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.16:39:38.53#ibcon#[25=USB\r\n] 2006.173.16:39:38.53#ibcon#*before write, iclass 39, count 0 2006.173.16:39:38.53#ibcon#enter sib2, iclass 39, count 0 2006.173.16:39:38.53#ibcon#flushed, iclass 39, count 0 2006.173.16:39:38.53#ibcon#about to write, iclass 39, count 0 2006.173.16:39:38.53#ibcon#wrote, iclass 39, count 0 2006.173.16:39:38.53#ibcon#about to read 3, iclass 39, count 0 2006.173.16:39:38.56#ibcon#read 3, iclass 39, count 0 2006.173.16:39:38.56#ibcon#about to read 4, iclass 39, count 0 2006.173.16:39:38.56#ibcon#read 4, iclass 39, count 0 2006.173.16:39:38.56#ibcon#about to read 5, iclass 39, count 0 2006.173.16:39:38.56#ibcon#read 5, iclass 39, count 0 2006.173.16:39:38.56#ibcon#about to read 6, iclass 39, count 0 2006.173.16:39:38.56#ibcon#read 6, iclass 39, count 0 2006.173.16:39:38.56#ibcon#end of sib2, iclass 39, count 0 2006.173.16:39:38.56#ibcon#*after write, iclass 39, count 0 2006.173.16:39:38.56#ibcon#*before return 0, iclass 39, count 0 2006.173.16:39:38.56#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.16:39:38.56#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.16:39:38.56#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.16:39:38.56#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.16:39:38.56$vck44/valo=8,884.99 2006.173.16:39:38.56#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.16:39:38.56#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.16:39:38.56#ibcon#ireg 17 cls_cnt 0 2006.173.16:39:38.56#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.16:39:38.56#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.16:39:38.56#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.16:39:38.56#ibcon#enter wrdev, iclass 6, count 0 2006.173.16:39:38.56#ibcon#first serial, iclass 6, count 0 2006.173.16:39:38.56#ibcon#enter sib2, iclass 6, count 0 2006.173.16:39:38.56#ibcon#flushed, iclass 6, count 0 2006.173.16:39:38.56#ibcon#about to write, iclass 6, count 0 2006.173.16:39:38.56#ibcon#wrote, iclass 6, count 0 2006.173.16:39:38.56#ibcon#about to read 3, iclass 6, count 0 2006.173.16:39:38.58#ibcon#read 3, iclass 6, count 0 2006.173.16:39:38.58#ibcon#about to read 4, iclass 6, count 0 2006.173.16:39:38.58#ibcon#read 4, iclass 6, count 0 2006.173.16:39:38.58#ibcon#about to read 5, iclass 6, count 0 2006.173.16:39:38.58#ibcon#read 5, iclass 6, count 0 2006.173.16:39:38.58#ibcon#about to read 6, iclass 6, count 0 2006.173.16:39:38.58#ibcon#read 6, iclass 6, count 0 2006.173.16:39:38.58#ibcon#end of sib2, iclass 6, count 0 2006.173.16:39:38.58#ibcon#*mode == 0, iclass 6, count 0 2006.173.16:39:38.58#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.16:39:38.58#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.16:39:38.58#ibcon#*before write, iclass 6, count 0 2006.173.16:39:38.58#ibcon#enter sib2, iclass 6, count 0 2006.173.16:39:38.58#ibcon#flushed, iclass 6, count 0 2006.173.16:39:38.58#ibcon#about to write, iclass 6, count 0 2006.173.16:39:38.58#ibcon#wrote, iclass 6, count 0 2006.173.16:39:38.58#ibcon#about to read 3, iclass 6, count 0 2006.173.16:39:38.62#ibcon#read 3, iclass 6, count 0 2006.173.16:39:38.62#ibcon#about to read 4, iclass 6, count 0 2006.173.16:39:38.62#ibcon#read 4, iclass 6, count 0 2006.173.16:39:38.62#ibcon#about to read 5, iclass 6, count 0 2006.173.16:39:38.62#ibcon#read 5, iclass 6, count 0 2006.173.16:39:38.62#ibcon#about to read 6, iclass 6, count 0 2006.173.16:39:38.62#ibcon#read 6, iclass 6, count 0 2006.173.16:39:38.62#ibcon#end of sib2, iclass 6, count 0 2006.173.16:39:38.62#ibcon#*after write, iclass 6, count 0 2006.173.16:39:38.62#ibcon#*before return 0, iclass 6, count 0 2006.173.16:39:38.62#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.16:39:38.62#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.16:39:38.62#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.16:39:38.62#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.16:39:38.62$vck44/va=8,4 2006.173.16:39:38.62#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.16:39:38.62#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.16:39:38.62#ibcon#ireg 11 cls_cnt 2 2006.173.16:39:38.62#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.16:39:38.68#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.16:39:38.68#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.16:39:38.68#ibcon#enter wrdev, iclass 10, count 2 2006.173.16:39:38.68#ibcon#first serial, iclass 10, count 2 2006.173.16:39:38.68#ibcon#enter sib2, iclass 10, count 2 2006.173.16:39:38.68#ibcon#flushed, iclass 10, count 2 2006.173.16:39:38.68#ibcon#about to write, iclass 10, count 2 2006.173.16:39:38.68#ibcon#wrote, iclass 10, count 2 2006.173.16:39:38.68#ibcon#about to read 3, iclass 10, count 2 2006.173.16:39:38.70#ibcon#read 3, iclass 10, count 2 2006.173.16:39:38.70#ibcon#about to read 4, iclass 10, count 2 2006.173.16:39:38.70#ibcon#read 4, iclass 10, count 2 2006.173.16:39:38.70#ibcon#about to read 5, iclass 10, count 2 2006.173.16:39:38.70#ibcon#read 5, iclass 10, count 2 2006.173.16:39:38.70#ibcon#about to read 6, iclass 10, count 2 2006.173.16:39:38.70#ibcon#read 6, iclass 10, count 2 2006.173.16:39:38.70#ibcon#end of sib2, iclass 10, count 2 2006.173.16:39:38.70#ibcon#*mode == 0, iclass 10, count 2 2006.173.16:39:38.70#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.16:39:38.70#ibcon#[25=AT08-04\r\n] 2006.173.16:39:38.70#ibcon#*before write, iclass 10, count 2 2006.173.16:39:38.70#ibcon#enter sib2, iclass 10, count 2 2006.173.16:39:38.70#ibcon#flushed, iclass 10, count 2 2006.173.16:39:38.70#ibcon#about to write, iclass 10, count 2 2006.173.16:39:38.70#ibcon#wrote, iclass 10, count 2 2006.173.16:39:38.70#ibcon#about to read 3, iclass 10, count 2 2006.173.16:39:38.73#ibcon#read 3, iclass 10, count 2 2006.173.16:39:38.73#ibcon#about to read 4, iclass 10, count 2 2006.173.16:39:38.73#ibcon#read 4, iclass 10, count 2 2006.173.16:39:38.73#ibcon#about to read 5, iclass 10, count 2 2006.173.16:39:38.73#ibcon#read 5, iclass 10, count 2 2006.173.16:39:38.73#ibcon#about to read 6, iclass 10, count 2 2006.173.16:39:38.73#ibcon#read 6, iclass 10, count 2 2006.173.16:39:38.73#ibcon#end of sib2, iclass 10, count 2 2006.173.16:39:38.73#ibcon#*after write, iclass 10, count 2 2006.173.16:39:38.73#ibcon#*before return 0, iclass 10, count 2 2006.173.16:39:38.73#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.16:39:38.73#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.16:39:38.73#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.16:39:38.73#ibcon#ireg 7 cls_cnt 0 2006.173.16:39:38.73#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.16:39:38.85#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.16:39:38.85#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.16:39:38.85#ibcon#enter wrdev, iclass 10, count 0 2006.173.16:39:38.85#ibcon#first serial, iclass 10, count 0 2006.173.16:39:38.85#ibcon#enter sib2, iclass 10, count 0 2006.173.16:39:38.85#ibcon#flushed, iclass 10, count 0 2006.173.16:39:38.85#ibcon#about to write, iclass 10, count 0 2006.173.16:39:38.85#ibcon#wrote, iclass 10, count 0 2006.173.16:39:38.85#ibcon#about to read 3, iclass 10, count 0 2006.173.16:39:38.87#ibcon#read 3, iclass 10, count 0 2006.173.16:39:38.87#ibcon#about to read 4, iclass 10, count 0 2006.173.16:39:38.87#ibcon#read 4, iclass 10, count 0 2006.173.16:39:38.87#ibcon#about to read 5, iclass 10, count 0 2006.173.16:39:38.87#ibcon#read 5, iclass 10, count 0 2006.173.16:39:38.87#ibcon#about to read 6, iclass 10, count 0 2006.173.16:39:38.87#ibcon#read 6, iclass 10, count 0 2006.173.16:39:38.87#ibcon#end of sib2, iclass 10, count 0 2006.173.16:39:38.87#ibcon#*mode == 0, iclass 10, count 0 2006.173.16:39:38.87#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.16:39:38.87#ibcon#[25=USB\r\n] 2006.173.16:39:38.87#ibcon#*before write, iclass 10, count 0 2006.173.16:39:38.87#ibcon#enter sib2, iclass 10, count 0 2006.173.16:39:38.87#ibcon#flushed, iclass 10, count 0 2006.173.16:39:38.87#ibcon#about to write, iclass 10, count 0 2006.173.16:39:38.87#ibcon#wrote, iclass 10, count 0 2006.173.16:39:38.87#ibcon#about to read 3, iclass 10, count 0 2006.173.16:39:38.90#ibcon#read 3, iclass 10, count 0 2006.173.16:39:38.90#ibcon#about to read 4, iclass 10, count 0 2006.173.16:39:38.90#ibcon#read 4, iclass 10, count 0 2006.173.16:39:38.90#ibcon#about to read 5, iclass 10, count 0 2006.173.16:39:38.90#ibcon#read 5, iclass 10, count 0 2006.173.16:39:38.90#ibcon#about to read 6, iclass 10, count 0 2006.173.16:39:38.90#ibcon#read 6, iclass 10, count 0 2006.173.16:39:38.90#ibcon#end of sib2, iclass 10, count 0 2006.173.16:39:38.90#ibcon#*after write, iclass 10, count 0 2006.173.16:39:38.90#ibcon#*before return 0, iclass 10, count 0 2006.173.16:39:38.90#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.16:39:38.90#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.16:39:38.90#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.16:39:38.90#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.16:39:38.90$vck44/vblo=1,629.99 2006.173.16:39:38.90#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.16:39:38.90#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.16:39:38.90#ibcon#ireg 17 cls_cnt 0 2006.173.16:39:38.90#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.16:39:38.90#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.16:39:38.90#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.16:39:38.90#ibcon#enter wrdev, iclass 12, count 0 2006.173.16:39:38.90#ibcon#first serial, iclass 12, count 0 2006.173.16:39:38.90#ibcon#enter sib2, iclass 12, count 0 2006.173.16:39:38.90#ibcon#flushed, iclass 12, count 0 2006.173.16:39:38.90#ibcon#about to write, iclass 12, count 0 2006.173.16:39:38.90#ibcon#wrote, iclass 12, count 0 2006.173.16:39:38.90#ibcon#about to read 3, iclass 12, count 0 2006.173.16:39:38.92#ibcon#read 3, iclass 12, count 0 2006.173.16:39:38.92#ibcon#about to read 4, iclass 12, count 0 2006.173.16:39:38.92#ibcon#read 4, iclass 12, count 0 2006.173.16:39:38.92#ibcon#about to read 5, iclass 12, count 0 2006.173.16:39:38.92#ibcon#read 5, iclass 12, count 0 2006.173.16:39:38.92#ibcon#about to read 6, iclass 12, count 0 2006.173.16:39:38.92#ibcon#read 6, iclass 12, count 0 2006.173.16:39:38.92#ibcon#end of sib2, iclass 12, count 0 2006.173.16:39:38.92#ibcon#*mode == 0, iclass 12, count 0 2006.173.16:39:38.92#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.16:39:38.92#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.16:39:38.92#ibcon#*before write, iclass 12, count 0 2006.173.16:39:38.92#ibcon#enter sib2, iclass 12, count 0 2006.173.16:39:38.92#ibcon#flushed, iclass 12, count 0 2006.173.16:39:38.92#ibcon#about to write, iclass 12, count 0 2006.173.16:39:38.92#ibcon#wrote, iclass 12, count 0 2006.173.16:39:38.92#ibcon#about to read 3, iclass 12, count 0 2006.173.16:39:38.96#ibcon#read 3, iclass 12, count 0 2006.173.16:39:38.96#ibcon#about to read 4, iclass 12, count 0 2006.173.16:39:38.96#ibcon#read 4, iclass 12, count 0 2006.173.16:39:39.12#ibcon#about to read 5, iclass 12, count 0 2006.173.16:39:39.12#ibcon#read 5, iclass 12, count 0 2006.173.16:39:39.12#ibcon#about to read 6, iclass 12, count 0 2006.173.16:39:39.12#ibcon#read 6, iclass 12, count 0 2006.173.16:39:39.12#ibcon#end of sib2, iclass 12, count 0 2006.173.16:39:39.12#ibcon#*after write, iclass 12, count 0 2006.173.16:39:39.12#ibcon#*before return 0, iclass 12, count 0 2006.173.16:39:39.12#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.16:39:39.12#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.16:39:39.12#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.16:39:39.12#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.16:39:39.12$vck44/vb=1,4 2006.173.16:39:39.12#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.16:39:39.12#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.16:39:39.12#ibcon#ireg 11 cls_cnt 2 2006.173.16:39:39.12#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.16:39:39.12#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.16:39:39.12#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.16:39:39.12#ibcon#enter wrdev, iclass 14, count 2 2006.173.16:39:39.12#ibcon#first serial, iclass 14, count 2 2006.173.16:39:39.12#ibcon#enter sib2, iclass 14, count 2 2006.173.16:39:39.12#ibcon#flushed, iclass 14, count 2 2006.173.16:39:39.12#ibcon#about to write, iclass 14, count 2 2006.173.16:39:39.12#ibcon#wrote, iclass 14, count 2 2006.173.16:39:39.12#ibcon#about to read 3, iclass 14, count 2 2006.173.16:39:39.14#ibcon#read 3, iclass 14, count 2 2006.173.16:39:39.14#ibcon#about to read 4, iclass 14, count 2 2006.173.16:39:39.14#ibcon#read 4, iclass 14, count 2 2006.173.16:39:39.14#ibcon#about to read 5, iclass 14, count 2 2006.173.16:39:39.14#ibcon#read 5, iclass 14, count 2 2006.173.16:39:39.14#ibcon#about to read 6, iclass 14, count 2 2006.173.16:39:39.14#ibcon#read 6, iclass 14, count 2 2006.173.16:39:39.14#ibcon#end of sib2, iclass 14, count 2 2006.173.16:39:39.14#ibcon#*mode == 0, iclass 14, count 2 2006.173.16:39:39.14#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.16:39:39.14#ibcon#[27=AT01-04\r\n] 2006.173.16:39:39.14#ibcon#*before write, iclass 14, count 2 2006.173.16:39:39.14#ibcon#enter sib2, iclass 14, count 2 2006.173.16:39:39.14#ibcon#flushed, iclass 14, count 2 2006.173.16:39:39.14#ibcon#about to write, iclass 14, count 2 2006.173.16:39:39.14#ibcon#wrote, iclass 14, count 2 2006.173.16:39:39.14#ibcon#about to read 3, iclass 14, count 2 2006.173.16:39:39.17#ibcon#read 3, iclass 14, count 2 2006.173.16:39:39.17#ibcon#about to read 4, iclass 14, count 2 2006.173.16:39:39.17#ibcon#read 4, iclass 14, count 2 2006.173.16:39:39.17#ibcon#about to read 5, iclass 14, count 2 2006.173.16:39:39.17#ibcon#read 5, iclass 14, count 2 2006.173.16:39:39.17#ibcon#about to read 6, iclass 14, count 2 2006.173.16:39:39.17#ibcon#read 6, iclass 14, count 2 2006.173.16:39:39.17#ibcon#end of sib2, iclass 14, count 2 2006.173.16:39:39.17#ibcon#*after write, iclass 14, count 2 2006.173.16:39:39.17#ibcon#*before return 0, iclass 14, count 2 2006.173.16:39:39.17#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.16:39:39.17#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.16:39:39.17#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.16:39:39.17#ibcon#ireg 7 cls_cnt 0 2006.173.16:39:39.17#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.16:39:39.29#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.16:39:39.29#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.16:39:39.29#ibcon#enter wrdev, iclass 14, count 0 2006.173.16:39:39.29#ibcon#first serial, iclass 14, count 0 2006.173.16:39:39.29#ibcon#enter sib2, iclass 14, count 0 2006.173.16:39:39.29#ibcon#flushed, iclass 14, count 0 2006.173.16:39:39.29#ibcon#about to write, iclass 14, count 0 2006.173.16:39:39.29#ibcon#wrote, iclass 14, count 0 2006.173.16:39:39.29#ibcon#about to read 3, iclass 14, count 0 2006.173.16:39:39.31#ibcon#read 3, iclass 14, count 0 2006.173.16:39:39.31#ibcon#about to read 4, iclass 14, count 0 2006.173.16:39:39.31#ibcon#read 4, iclass 14, count 0 2006.173.16:39:39.31#ibcon#about to read 5, iclass 14, count 0 2006.173.16:39:39.31#ibcon#read 5, iclass 14, count 0 2006.173.16:39:39.31#ibcon#about to read 6, iclass 14, count 0 2006.173.16:39:39.31#ibcon#read 6, iclass 14, count 0 2006.173.16:39:39.31#ibcon#end of sib2, iclass 14, count 0 2006.173.16:39:39.31#ibcon#*mode == 0, iclass 14, count 0 2006.173.16:39:39.31#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.16:39:39.31#ibcon#[27=USB\r\n] 2006.173.16:39:39.31#ibcon#*before write, iclass 14, count 0 2006.173.16:39:39.31#ibcon#enter sib2, iclass 14, count 0 2006.173.16:39:39.31#ibcon#flushed, iclass 14, count 0 2006.173.16:39:39.31#ibcon#about to write, iclass 14, count 0 2006.173.16:39:39.31#ibcon#wrote, iclass 14, count 0 2006.173.16:39:39.31#ibcon#about to read 3, iclass 14, count 0 2006.173.16:39:39.34#ibcon#read 3, iclass 14, count 0 2006.173.16:39:39.34#ibcon#about to read 4, iclass 14, count 0 2006.173.16:39:39.34#ibcon#read 4, iclass 14, count 0 2006.173.16:39:39.34#ibcon#about to read 5, iclass 14, count 0 2006.173.16:39:39.34#ibcon#read 5, iclass 14, count 0 2006.173.16:39:39.34#ibcon#about to read 6, iclass 14, count 0 2006.173.16:39:39.34#ibcon#read 6, iclass 14, count 0 2006.173.16:39:39.34#ibcon#end of sib2, iclass 14, count 0 2006.173.16:39:39.34#ibcon#*after write, iclass 14, count 0 2006.173.16:39:39.34#ibcon#*before return 0, iclass 14, count 0 2006.173.16:39:39.34#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.16:39:39.34#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.16:39:39.34#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.16:39:39.34#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.16:39:39.34$vck44/vblo=2,634.99 2006.173.16:39:39.34#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.16:39:39.34#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.16:39:39.34#ibcon#ireg 17 cls_cnt 0 2006.173.16:39:39.34#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.16:39:39.34#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.16:39:39.34#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.16:39:39.34#ibcon#enter wrdev, iclass 16, count 0 2006.173.16:39:39.34#ibcon#first serial, iclass 16, count 0 2006.173.16:39:39.34#ibcon#enter sib2, iclass 16, count 0 2006.173.16:39:39.34#ibcon#flushed, iclass 16, count 0 2006.173.16:39:39.34#ibcon#about to write, iclass 16, count 0 2006.173.16:39:39.34#ibcon#wrote, iclass 16, count 0 2006.173.16:39:39.34#ibcon#about to read 3, iclass 16, count 0 2006.173.16:39:39.36#ibcon#read 3, iclass 16, count 0 2006.173.16:39:39.36#ibcon#about to read 4, iclass 16, count 0 2006.173.16:39:39.36#ibcon#read 4, iclass 16, count 0 2006.173.16:39:39.36#ibcon#about to read 5, iclass 16, count 0 2006.173.16:39:39.36#ibcon#read 5, iclass 16, count 0 2006.173.16:39:39.36#ibcon#about to read 6, iclass 16, count 0 2006.173.16:39:39.36#ibcon#read 6, iclass 16, count 0 2006.173.16:39:39.36#ibcon#end of sib2, iclass 16, count 0 2006.173.16:39:39.36#ibcon#*mode == 0, iclass 16, count 0 2006.173.16:39:39.36#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.16:39:39.36#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.16:39:39.36#ibcon#*before write, iclass 16, count 0 2006.173.16:39:39.36#ibcon#enter sib2, iclass 16, count 0 2006.173.16:39:39.36#ibcon#flushed, iclass 16, count 0 2006.173.16:39:39.36#ibcon#about to write, iclass 16, count 0 2006.173.16:39:39.36#ibcon#wrote, iclass 16, count 0 2006.173.16:39:39.36#ibcon#about to read 3, iclass 16, count 0 2006.173.16:39:39.40#ibcon#read 3, iclass 16, count 0 2006.173.16:39:39.40#ibcon#about to read 4, iclass 16, count 0 2006.173.16:39:39.40#ibcon#read 4, iclass 16, count 0 2006.173.16:39:39.40#ibcon#about to read 5, iclass 16, count 0 2006.173.16:39:39.40#ibcon#read 5, iclass 16, count 0 2006.173.16:39:39.40#ibcon#about to read 6, iclass 16, count 0 2006.173.16:39:39.40#ibcon#read 6, iclass 16, count 0 2006.173.16:39:39.40#ibcon#end of sib2, iclass 16, count 0 2006.173.16:39:39.40#ibcon#*after write, iclass 16, count 0 2006.173.16:39:39.40#ibcon#*before return 0, iclass 16, count 0 2006.173.16:39:39.40#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.16:39:39.40#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.16:39:39.40#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.16:39:39.40#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.16:39:39.40$vck44/vb=2,4 2006.173.16:39:39.40#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.16:39:39.40#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.16:39:39.40#ibcon#ireg 11 cls_cnt 2 2006.173.16:39:39.40#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.16:39:39.46#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.16:39:39.46#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.16:39:39.46#ibcon#enter wrdev, iclass 18, count 2 2006.173.16:39:39.46#ibcon#first serial, iclass 18, count 2 2006.173.16:39:39.46#ibcon#enter sib2, iclass 18, count 2 2006.173.16:39:39.46#ibcon#flushed, iclass 18, count 2 2006.173.16:39:39.46#ibcon#about to write, iclass 18, count 2 2006.173.16:39:39.46#ibcon#wrote, iclass 18, count 2 2006.173.16:39:39.46#ibcon#about to read 3, iclass 18, count 2 2006.173.16:39:39.48#ibcon#read 3, iclass 18, count 2 2006.173.16:39:39.48#ibcon#about to read 4, iclass 18, count 2 2006.173.16:39:39.48#ibcon#read 4, iclass 18, count 2 2006.173.16:39:39.48#ibcon#about to read 5, iclass 18, count 2 2006.173.16:39:39.48#ibcon#read 5, iclass 18, count 2 2006.173.16:39:39.48#ibcon#about to read 6, iclass 18, count 2 2006.173.16:39:39.48#ibcon#read 6, iclass 18, count 2 2006.173.16:39:39.48#ibcon#end of sib2, iclass 18, count 2 2006.173.16:39:39.48#ibcon#*mode == 0, iclass 18, count 2 2006.173.16:39:39.48#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.16:39:39.48#ibcon#[27=AT02-04\r\n] 2006.173.16:39:39.48#ibcon#*before write, iclass 18, count 2 2006.173.16:39:39.48#ibcon#enter sib2, iclass 18, count 2 2006.173.16:39:39.48#ibcon#flushed, iclass 18, count 2 2006.173.16:39:39.48#ibcon#about to write, iclass 18, count 2 2006.173.16:39:39.48#ibcon#wrote, iclass 18, count 2 2006.173.16:39:39.48#ibcon#about to read 3, iclass 18, count 2 2006.173.16:39:39.51#ibcon#read 3, iclass 18, count 2 2006.173.16:39:39.51#ibcon#about to read 4, iclass 18, count 2 2006.173.16:39:39.51#ibcon#read 4, iclass 18, count 2 2006.173.16:39:39.51#ibcon#about to read 5, iclass 18, count 2 2006.173.16:39:39.51#ibcon#read 5, iclass 18, count 2 2006.173.16:39:39.51#ibcon#about to read 6, iclass 18, count 2 2006.173.16:39:39.51#ibcon#read 6, iclass 18, count 2 2006.173.16:39:39.51#ibcon#end of sib2, iclass 18, count 2 2006.173.16:39:39.51#ibcon#*after write, iclass 18, count 2 2006.173.16:39:39.51#ibcon#*before return 0, iclass 18, count 2 2006.173.16:39:39.51#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.16:39:39.51#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.16:39:39.51#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.16:39:39.51#ibcon#ireg 7 cls_cnt 0 2006.173.16:39:39.51#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.16:39:39.63#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.16:39:39.63#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.16:39:39.63#ibcon#enter wrdev, iclass 18, count 0 2006.173.16:39:39.63#ibcon#first serial, iclass 18, count 0 2006.173.16:39:39.63#ibcon#enter sib2, iclass 18, count 0 2006.173.16:39:39.63#ibcon#flushed, iclass 18, count 0 2006.173.16:39:39.63#ibcon#about to write, iclass 18, count 0 2006.173.16:39:39.63#ibcon#wrote, iclass 18, count 0 2006.173.16:39:39.63#ibcon#about to read 3, iclass 18, count 0 2006.173.16:39:39.65#ibcon#read 3, iclass 18, count 0 2006.173.16:39:39.65#ibcon#about to read 4, iclass 18, count 0 2006.173.16:39:39.65#ibcon#read 4, iclass 18, count 0 2006.173.16:39:39.65#ibcon#about to read 5, iclass 18, count 0 2006.173.16:39:39.65#ibcon#read 5, iclass 18, count 0 2006.173.16:39:39.65#ibcon#about to read 6, iclass 18, count 0 2006.173.16:39:39.65#ibcon#read 6, iclass 18, count 0 2006.173.16:39:39.65#ibcon#end of sib2, iclass 18, count 0 2006.173.16:39:39.65#ibcon#*mode == 0, iclass 18, count 0 2006.173.16:39:39.65#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.16:39:39.65#ibcon#[27=USB\r\n] 2006.173.16:39:39.65#ibcon#*before write, iclass 18, count 0 2006.173.16:39:39.65#ibcon#enter sib2, iclass 18, count 0 2006.173.16:39:39.65#ibcon#flushed, iclass 18, count 0 2006.173.16:39:39.65#ibcon#about to write, iclass 18, count 0 2006.173.16:39:39.65#ibcon#wrote, iclass 18, count 0 2006.173.16:39:39.65#ibcon#about to read 3, iclass 18, count 0 2006.173.16:39:39.68#ibcon#read 3, iclass 18, count 0 2006.173.16:39:39.68#ibcon#about to read 4, iclass 18, count 0 2006.173.16:39:39.68#ibcon#read 4, iclass 18, count 0 2006.173.16:39:39.68#ibcon#about to read 5, iclass 18, count 0 2006.173.16:39:39.68#ibcon#read 5, iclass 18, count 0 2006.173.16:39:39.68#ibcon#about to read 6, iclass 18, count 0 2006.173.16:39:39.68#ibcon#read 6, iclass 18, count 0 2006.173.16:39:39.68#ibcon#end of sib2, iclass 18, count 0 2006.173.16:39:39.68#ibcon#*after write, iclass 18, count 0 2006.173.16:39:39.68#ibcon#*before return 0, iclass 18, count 0 2006.173.16:39:39.68#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.16:39:39.68#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.16:39:39.68#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.16:39:39.68#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.16:39:39.68$vck44/vblo=3,649.99 2006.173.16:39:39.68#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.16:39:39.68#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.16:39:39.68#ibcon#ireg 17 cls_cnt 0 2006.173.16:39:39.68#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.16:39:39.68#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.16:39:39.68#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.16:39:39.68#ibcon#enter wrdev, iclass 20, count 0 2006.173.16:39:39.68#ibcon#first serial, iclass 20, count 0 2006.173.16:39:39.68#ibcon#enter sib2, iclass 20, count 0 2006.173.16:39:39.68#ibcon#flushed, iclass 20, count 0 2006.173.16:39:39.68#ibcon#about to write, iclass 20, count 0 2006.173.16:39:39.68#ibcon#wrote, iclass 20, count 0 2006.173.16:39:39.68#ibcon#about to read 3, iclass 20, count 0 2006.173.16:39:39.70#ibcon#read 3, iclass 20, count 0 2006.173.16:39:39.70#ibcon#about to read 4, iclass 20, count 0 2006.173.16:39:39.70#ibcon#read 4, iclass 20, count 0 2006.173.16:39:39.70#ibcon#about to read 5, iclass 20, count 0 2006.173.16:39:39.70#ibcon#read 5, iclass 20, count 0 2006.173.16:39:39.70#ibcon#about to read 6, iclass 20, count 0 2006.173.16:39:39.70#ibcon#read 6, iclass 20, count 0 2006.173.16:39:39.70#ibcon#end of sib2, iclass 20, count 0 2006.173.16:39:39.70#ibcon#*mode == 0, iclass 20, count 0 2006.173.16:39:39.70#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.16:39:39.70#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.16:39:39.70#ibcon#*before write, iclass 20, count 0 2006.173.16:39:39.70#ibcon#enter sib2, iclass 20, count 0 2006.173.16:39:39.70#ibcon#flushed, iclass 20, count 0 2006.173.16:39:39.70#ibcon#about to write, iclass 20, count 0 2006.173.16:39:39.70#ibcon#wrote, iclass 20, count 0 2006.173.16:39:39.70#ibcon#about to read 3, iclass 20, count 0 2006.173.16:39:39.74#ibcon#read 3, iclass 20, count 0 2006.173.16:39:39.74#ibcon#about to read 4, iclass 20, count 0 2006.173.16:39:39.74#ibcon#read 4, iclass 20, count 0 2006.173.16:39:39.74#ibcon#about to read 5, iclass 20, count 0 2006.173.16:39:39.74#ibcon#read 5, iclass 20, count 0 2006.173.16:39:39.74#ibcon#about to read 6, iclass 20, count 0 2006.173.16:39:39.74#ibcon#read 6, iclass 20, count 0 2006.173.16:39:39.74#ibcon#end of sib2, iclass 20, count 0 2006.173.16:39:39.74#ibcon#*after write, iclass 20, count 0 2006.173.16:39:39.74#ibcon#*before return 0, iclass 20, count 0 2006.173.16:39:39.74#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.16:39:39.74#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.16:39:39.74#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.16:39:39.74#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.16:39:39.74$vck44/vb=3,4 2006.173.16:39:39.74#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.16:39:39.74#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.16:39:39.74#ibcon#ireg 11 cls_cnt 2 2006.173.16:39:39.74#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.16:39:39.80#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.16:39:39.80#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.16:39:39.80#ibcon#enter wrdev, iclass 22, count 2 2006.173.16:39:39.80#ibcon#first serial, iclass 22, count 2 2006.173.16:39:39.80#ibcon#enter sib2, iclass 22, count 2 2006.173.16:39:39.80#ibcon#flushed, iclass 22, count 2 2006.173.16:39:39.80#ibcon#about to write, iclass 22, count 2 2006.173.16:39:39.80#ibcon#wrote, iclass 22, count 2 2006.173.16:39:39.80#ibcon#about to read 3, iclass 22, count 2 2006.173.16:39:39.82#ibcon#read 3, iclass 22, count 2 2006.173.16:39:39.82#ibcon#about to read 4, iclass 22, count 2 2006.173.16:39:39.82#ibcon#read 4, iclass 22, count 2 2006.173.16:39:39.82#ibcon#about to read 5, iclass 22, count 2 2006.173.16:39:39.82#ibcon#read 5, iclass 22, count 2 2006.173.16:39:39.82#ibcon#about to read 6, iclass 22, count 2 2006.173.16:39:39.82#ibcon#read 6, iclass 22, count 2 2006.173.16:39:39.82#ibcon#end of sib2, iclass 22, count 2 2006.173.16:39:39.82#ibcon#*mode == 0, iclass 22, count 2 2006.173.16:39:39.82#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.16:39:39.82#ibcon#[27=AT03-04\r\n] 2006.173.16:39:39.82#ibcon#*before write, iclass 22, count 2 2006.173.16:39:39.82#ibcon#enter sib2, iclass 22, count 2 2006.173.16:39:39.82#ibcon#flushed, iclass 22, count 2 2006.173.16:39:39.82#ibcon#about to write, iclass 22, count 2 2006.173.16:39:39.82#ibcon#wrote, iclass 22, count 2 2006.173.16:39:39.82#ibcon#about to read 3, iclass 22, count 2 2006.173.16:39:39.85#ibcon#read 3, iclass 22, count 2 2006.173.16:39:39.85#ibcon#about to read 4, iclass 22, count 2 2006.173.16:39:39.85#ibcon#read 4, iclass 22, count 2 2006.173.16:39:39.85#ibcon#about to read 5, iclass 22, count 2 2006.173.16:39:39.85#ibcon#read 5, iclass 22, count 2 2006.173.16:39:39.85#ibcon#about to read 6, iclass 22, count 2 2006.173.16:39:39.85#ibcon#read 6, iclass 22, count 2 2006.173.16:39:39.85#ibcon#end of sib2, iclass 22, count 2 2006.173.16:39:39.85#ibcon#*after write, iclass 22, count 2 2006.173.16:39:39.85#ibcon#*before return 0, iclass 22, count 2 2006.173.16:39:39.85#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.16:39:39.85#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.16:39:39.85#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.16:39:39.85#ibcon#ireg 7 cls_cnt 0 2006.173.16:39:39.85#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.16:39:39.97#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.16:39:39.97#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.16:39:39.97#ibcon#enter wrdev, iclass 22, count 0 2006.173.16:39:39.97#ibcon#first serial, iclass 22, count 0 2006.173.16:39:39.97#ibcon#enter sib2, iclass 22, count 0 2006.173.16:39:39.97#ibcon#flushed, iclass 22, count 0 2006.173.16:39:39.97#ibcon#about to write, iclass 22, count 0 2006.173.16:39:39.97#ibcon#wrote, iclass 22, count 0 2006.173.16:39:39.97#ibcon#about to read 3, iclass 22, count 0 2006.173.16:39:39.99#ibcon#read 3, iclass 22, count 0 2006.173.16:39:39.99#ibcon#about to read 4, iclass 22, count 0 2006.173.16:39:39.99#ibcon#read 4, iclass 22, count 0 2006.173.16:39:39.99#ibcon#about to read 5, iclass 22, count 0 2006.173.16:39:39.99#ibcon#read 5, iclass 22, count 0 2006.173.16:39:39.99#ibcon#about to read 6, iclass 22, count 0 2006.173.16:39:39.99#ibcon#read 6, iclass 22, count 0 2006.173.16:39:39.99#ibcon#end of sib2, iclass 22, count 0 2006.173.16:39:39.99#ibcon#*mode == 0, iclass 22, count 0 2006.173.16:39:39.99#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.16:39:39.99#ibcon#[27=USB\r\n] 2006.173.16:39:39.99#ibcon#*before write, iclass 22, count 0 2006.173.16:39:39.99#ibcon#enter sib2, iclass 22, count 0 2006.173.16:39:39.99#ibcon#flushed, iclass 22, count 0 2006.173.16:39:39.99#ibcon#about to write, iclass 22, count 0 2006.173.16:39:39.99#ibcon#wrote, iclass 22, count 0 2006.173.16:39:39.99#ibcon#about to read 3, iclass 22, count 0 2006.173.16:39:40.02#ibcon#read 3, iclass 22, count 0 2006.173.16:39:40.02#ibcon#about to read 4, iclass 22, count 0 2006.173.16:39:40.02#ibcon#read 4, iclass 22, count 0 2006.173.16:39:40.02#ibcon#about to read 5, iclass 22, count 0 2006.173.16:39:40.02#ibcon#read 5, iclass 22, count 0 2006.173.16:39:40.02#ibcon#about to read 6, iclass 22, count 0 2006.173.16:39:40.02#ibcon#read 6, iclass 22, count 0 2006.173.16:39:40.02#ibcon#end of sib2, iclass 22, count 0 2006.173.16:39:40.02#ibcon#*after write, iclass 22, count 0 2006.173.16:39:40.02#ibcon#*before return 0, iclass 22, count 0 2006.173.16:39:40.02#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.16:39:40.02#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.16:39:40.02#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.16:39:40.02#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.16:39:40.02$vck44/vblo=4,679.99 2006.173.16:39:40.02#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.16:39:40.02#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.16:39:40.02#ibcon#ireg 17 cls_cnt 0 2006.173.16:39:40.02#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.16:39:40.02#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.16:39:40.02#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.16:39:40.02#ibcon#enter wrdev, iclass 24, count 0 2006.173.16:39:40.02#ibcon#first serial, iclass 24, count 0 2006.173.16:39:40.02#ibcon#enter sib2, iclass 24, count 0 2006.173.16:39:40.02#ibcon#flushed, iclass 24, count 0 2006.173.16:39:40.02#ibcon#about to write, iclass 24, count 0 2006.173.16:39:40.02#ibcon#wrote, iclass 24, count 0 2006.173.16:39:40.02#ibcon#about to read 3, iclass 24, count 0 2006.173.16:39:40.04#ibcon#read 3, iclass 24, count 0 2006.173.16:39:40.04#ibcon#about to read 4, iclass 24, count 0 2006.173.16:39:40.04#ibcon#read 4, iclass 24, count 0 2006.173.16:39:40.04#ibcon#about to read 5, iclass 24, count 0 2006.173.16:39:40.04#ibcon#read 5, iclass 24, count 0 2006.173.16:39:40.04#ibcon#about to read 6, iclass 24, count 0 2006.173.16:39:40.04#ibcon#read 6, iclass 24, count 0 2006.173.16:39:40.04#ibcon#end of sib2, iclass 24, count 0 2006.173.16:39:40.04#ibcon#*mode == 0, iclass 24, count 0 2006.173.16:39:40.04#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.16:39:40.04#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.16:39:40.04#ibcon#*before write, iclass 24, count 0 2006.173.16:39:40.04#ibcon#enter sib2, iclass 24, count 0 2006.173.16:39:40.04#ibcon#flushed, iclass 24, count 0 2006.173.16:39:40.04#ibcon#about to write, iclass 24, count 0 2006.173.16:39:40.04#ibcon#wrote, iclass 24, count 0 2006.173.16:39:40.04#ibcon#about to read 3, iclass 24, count 0 2006.173.16:39:40.08#ibcon#read 3, iclass 24, count 0 2006.173.16:39:40.08#ibcon#about to read 4, iclass 24, count 0 2006.173.16:39:40.08#ibcon#read 4, iclass 24, count 0 2006.173.16:39:40.08#ibcon#about to read 5, iclass 24, count 0 2006.173.16:39:40.08#ibcon#read 5, iclass 24, count 0 2006.173.16:39:40.08#ibcon#about to read 6, iclass 24, count 0 2006.173.16:39:40.08#ibcon#read 6, iclass 24, count 0 2006.173.16:39:40.08#ibcon#end of sib2, iclass 24, count 0 2006.173.16:39:40.08#ibcon#*after write, iclass 24, count 0 2006.173.16:39:40.08#ibcon#*before return 0, iclass 24, count 0 2006.173.16:39:40.08#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.16:39:40.08#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.16:39:40.08#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.16:39:40.08#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.16:39:40.08$vck44/vb=4,4 2006.173.16:39:40.08#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.16:39:40.08#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.16:39:40.08#ibcon#ireg 11 cls_cnt 2 2006.173.16:39:40.08#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.16:39:40.14#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.16:39:40.14#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.16:39:40.14#ibcon#enter wrdev, iclass 26, count 2 2006.173.16:39:40.14#ibcon#first serial, iclass 26, count 2 2006.173.16:39:40.14#ibcon#enter sib2, iclass 26, count 2 2006.173.16:39:40.14#ibcon#flushed, iclass 26, count 2 2006.173.16:39:40.14#ibcon#about to write, iclass 26, count 2 2006.173.16:39:40.14#ibcon#wrote, iclass 26, count 2 2006.173.16:39:40.14#ibcon#about to read 3, iclass 26, count 2 2006.173.16:39:40.16#ibcon#read 3, iclass 26, count 2 2006.173.16:39:40.16#ibcon#about to read 4, iclass 26, count 2 2006.173.16:39:40.16#ibcon#read 4, iclass 26, count 2 2006.173.16:39:40.16#ibcon#about to read 5, iclass 26, count 2 2006.173.16:39:40.16#ibcon#read 5, iclass 26, count 2 2006.173.16:39:40.16#ibcon#about to read 6, iclass 26, count 2 2006.173.16:39:40.16#ibcon#read 6, iclass 26, count 2 2006.173.16:39:40.16#ibcon#end of sib2, iclass 26, count 2 2006.173.16:39:40.16#ibcon#*mode == 0, iclass 26, count 2 2006.173.16:39:40.16#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.16:39:40.16#ibcon#[27=AT04-04\r\n] 2006.173.16:39:40.16#ibcon#*before write, iclass 26, count 2 2006.173.16:39:40.16#ibcon#enter sib2, iclass 26, count 2 2006.173.16:39:40.16#ibcon#flushed, iclass 26, count 2 2006.173.16:39:40.16#ibcon#about to write, iclass 26, count 2 2006.173.16:39:40.16#ibcon#wrote, iclass 26, count 2 2006.173.16:39:40.16#ibcon#about to read 3, iclass 26, count 2 2006.173.16:39:40.19#ibcon#read 3, iclass 26, count 2 2006.173.16:39:40.19#ibcon#about to read 4, iclass 26, count 2 2006.173.16:39:40.19#ibcon#read 4, iclass 26, count 2 2006.173.16:39:40.19#ibcon#about to read 5, iclass 26, count 2 2006.173.16:39:40.19#ibcon#read 5, iclass 26, count 2 2006.173.16:39:40.19#ibcon#about to read 6, iclass 26, count 2 2006.173.16:39:40.19#ibcon#read 6, iclass 26, count 2 2006.173.16:39:40.19#ibcon#end of sib2, iclass 26, count 2 2006.173.16:39:40.19#ibcon#*after write, iclass 26, count 2 2006.173.16:39:40.19#ibcon#*before return 0, iclass 26, count 2 2006.173.16:39:40.19#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.16:39:40.19#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.16:39:40.19#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.16:39:40.19#ibcon#ireg 7 cls_cnt 0 2006.173.16:39:40.19#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.16:39:40.31#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.16:39:40.31#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.16:39:40.31#ibcon#enter wrdev, iclass 26, count 0 2006.173.16:39:40.31#ibcon#first serial, iclass 26, count 0 2006.173.16:39:40.31#ibcon#enter sib2, iclass 26, count 0 2006.173.16:39:40.31#ibcon#flushed, iclass 26, count 0 2006.173.16:39:40.31#ibcon#about to write, iclass 26, count 0 2006.173.16:39:40.31#ibcon#wrote, iclass 26, count 0 2006.173.16:39:40.31#ibcon#about to read 3, iclass 26, count 0 2006.173.16:39:40.33#ibcon#read 3, iclass 26, count 0 2006.173.16:39:40.33#ibcon#about to read 4, iclass 26, count 0 2006.173.16:39:40.33#ibcon#read 4, iclass 26, count 0 2006.173.16:39:40.33#ibcon#about to read 5, iclass 26, count 0 2006.173.16:39:40.33#ibcon#read 5, iclass 26, count 0 2006.173.16:39:40.33#ibcon#about to read 6, iclass 26, count 0 2006.173.16:39:40.33#ibcon#read 6, iclass 26, count 0 2006.173.16:39:40.33#ibcon#end of sib2, iclass 26, count 0 2006.173.16:39:40.33#ibcon#*mode == 0, iclass 26, count 0 2006.173.16:39:40.33#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.16:39:40.33#ibcon#[27=USB\r\n] 2006.173.16:39:40.33#ibcon#*before write, iclass 26, count 0 2006.173.16:39:40.33#ibcon#enter sib2, iclass 26, count 0 2006.173.16:39:40.33#ibcon#flushed, iclass 26, count 0 2006.173.16:39:40.33#ibcon#about to write, iclass 26, count 0 2006.173.16:39:40.33#ibcon#wrote, iclass 26, count 0 2006.173.16:39:40.33#ibcon#about to read 3, iclass 26, count 0 2006.173.16:39:40.36#ibcon#read 3, iclass 26, count 0 2006.173.16:39:40.36#ibcon#about to read 4, iclass 26, count 0 2006.173.16:39:40.36#ibcon#read 4, iclass 26, count 0 2006.173.16:39:40.36#ibcon#about to read 5, iclass 26, count 0 2006.173.16:39:40.36#ibcon#read 5, iclass 26, count 0 2006.173.16:39:40.36#ibcon#about to read 6, iclass 26, count 0 2006.173.16:39:40.36#ibcon#read 6, iclass 26, count 0 2006.173.16:39:40.36#ibcon#end of sib2, iclass 26, count 0 2006.173.16:39:40.36#ibcon#*after write, iclass 26, count 0 2006.173.16:39:40.36#ibcon#*before return 0, iclass 26, count 0 2006.173.16:39:40.36#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.16:39:40.36#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.16:39:40.36#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.16:39:40.36#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.16:39:40.36$vck44/vblo=5,709.99 2006.173.16:39:40.36#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.16:39:40.36#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.16:39:40.36#ibcon#ireg 17 cls_cnt 0 2006.173.16:39:40.36#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.16:39:40.36#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.16:39:40.36#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.16:39:40.36#ibcon#enter wrdev, iclass 28, count 0 2006.173.16:39:40.36#ibcon#first serial, iclass 28, count 0 2006.173.16:39:40.36#ibcon#enter sib2, iclass 28, count 0 2006.173.16:39:40.36#ibcon#flushed, iclass 28, count 0 2006.173.16:39:40.36#ibcon#about to write, iclass 28, count 0 2006.173.16:39:40.36#ibcon#wrote, iclass 28, count 0 2006.173.16:39:40.36#ibcon#about to read 3, iclass 28, count 0 2006.173.16:39:40.38#ibcon#read 3, iclass 28, count 0 2006.173.16:39:40.38#ibcon#about to read 4, iclass 28, count 0 2006.173.16:39:40.38#ibcon#read 4, iclass 28, count 0 2006.173.16:39:40.38#ibcon#about to read 5, iclass 28, count 0 2006.173.16:39:40.38#ibcon#read 5, iclass 28, count 0 2006.173.16:39:40.38#ibcon#about to read 6, iclass 28, count 0 2006.173.16:39:40.38#ibcon#read 6, iclass 28, count 0 2006.173.16:39:40.38#ibcon#end of sib2, iclass 28, count 0 2006.173.16:39:40.38#ibcon#*mode == 0, iclass 28, count 0 2006.173.16:39:40.38#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.16:39:40.38#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.16:39:40.38#ibcon#*before write, iclass 28, count 0 2006.173.16:39:40.38#ibcon#enter sib2, iclass 28, count 0 2006.173.16:39:40.38#ibcon#flushed, iclass 28, count 0 2006.173.16:39:40.38#ibcon#about to write, iclass 28, count 0 2006.173.16:39:40.38#ibcon#wrote, iclass 28, count 0 2006.173.16:39:40.38#ibcon#about to read 3, iclass 28, count 0 2006.173.16:39:40.42#ibcon#read 3, iclass 28, count 0 2006.173.16:39:40.42#ibcon#about to read 4, iclass 28, count 0 2006.173.16:39:40.42#ibcon#read 4, iclass 28, count 0 2006.173.16:39:40.42#ibcon#about to read 5, iclass 28, count 0 2006.173.16:39:40.42#ibcon#read 5, iclass 28, count 0 2006.173.16:39:40.60#ibcon#about to read 6, iclass 28, count 0 2006.173.16:39:40.60#ibcon#read 6, iclass 28, count 0 2006.173.16:39:40.60#ibcon#end of sib2, iclass 28, count 0 2006.173.16:39:40.60#ibcon#*after write, iclass 28, count 0 2006.173.16:39:40.60#ibcon#*before return 0, iclass 28, count 0 2006.173.16:39:40.60#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.16:39:40.60#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.16:39:40.60#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.16:39:40.60#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.16:39:40.60$vck44/vb=5,4 2006.173.16:39:40.60#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.16:39:40.60#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.16:39:40.60#ibcon#ireg 11 cls_cnt 2 2006.173.16:39:40.60#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.16:39:40.60#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.16:39:40.60#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.16:39:40.60#ibcon#enter wrdev, iclass 30, count 2 2006.173.16:39:40.60#ibcon#first serial, iclass 30, count 2 2006.173.16:39:40.60#ibcon#enter sib2, iclass 30, count 2 2006.173.16:39:40.60#ibcon#flushed, iclass 30, count 2 2006.173.16:39:40.60#ibcon#about to write, iclass 30, count 2 2006.173.16:39:40.60#ibcon#wrote, iclass 30, count 2 2006.173.16:39:40.60#ibcon#about to read 3, iclass 30, count 2 2006.173.16:39:40.62#ibcon#read 3, iclass 30, count 2 2006.173.16:39:40.62#ibcon#about to read 4, iclass 30, count 2 2006.173.16:39:40.62#ibcon#read 4, iclass 30, count 2 2006.173.16:39:40.62#ibcon#about to read 5, iclass 30, count 2 2006.173.16:39:40.62#ibcon#read 5, iclass 30, count 2 2006.173.16:39:40.62#ibcon#about to read 6, iclass 30, count 2 2006.173.16:39:40.62#ibcon#read 6, iclass 30, count 2 2006.173.16:39:40.62#ibcon#end of sib2, iclass 30, count 2 2006.173.16:39:40.62#ibcon#*mode == 0, iclass 30, count 2 2006.173.16:39:40.62#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.16:39:40.62#ibcon#[27=AT05-04\r\n] 2006.173.16:39:40.62#ibcon#*before write, iclass 30, count 2 2006.173.16:39:40.62#ibcon#enter sib2, iclass 30, count 2 2006.173.16:39:40.62#ibcon#flushed, iclass 30, count 2 2006.173.16:39:40.62#ibcon#about to write, iclass 30, count 2 2006.173.16:39:40.62#ibcon#wrote, iclass 30, count 2 2006.173.16:39:40.62#ibcon#about to read 3, iclass 30, count 2 2006.173.16:39:40.65#ibcon#read 3, iclass 30, count 2 2006.173.16:39:40.65#ibcon#about to read 4, iclass 30, count 2 2006.173.16:39:40.65#ibcon#read 4, iclass 30, count 2 2006.173.16:39:40.65#ibcon#about to read 5, iclass 30, count 2 2006.173.16:39:40.65#ibcon#read 5, iclass 30, count 2 2006.173.16:39:40.65#ibcon#about to read 6, iclass 30, count 2 2006.173.16:39:40.65#ibcon#read 6, iclass 30, count 2 2006.173.16:39:40.65#ibcon#end of sib2, iclass 30, count 2 2006.173.16:39:40.65#ibcon#*after write, iclass 30, count 2 2006.173.16:39:40.65#ibcon#*before return 0, iclass 30, count 2 2006.173.16:39:40.65#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.16:39:40.65#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.16:39:40.65#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.16:39:40.65#ibcon#ireg 7 cls_cnt 0 2006.173.16:39:40.65#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.16:39:40.77#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.16:39:40.77#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.16:39:40.77#ibcon#enter wrdev, iclass 30, count 0 2006.173.16:39:40.77#ibcon#first serial, iclass 30, count 0 2006.173.16:39:40.77#ibcon#enter sib2, iclass 30, count 0 2006.173.16:39:40.77#ibcon#flushed, iclass 30, count 0 2006.173.16:39:40.77#ibcon#about to write, iclass 30, count 0 2006.173.16:39:40.77#ibcon#wrote, iclass 30, count 0 2006.173.16:39:40.77#ibcon#about to read 3, iclass 30, count 0 2006.173.16:39:40.79#ibcon#read 3, iclass 30, count 0 2006.173.16:39:40.79#ibcon#about to read 4, iclass 30, count 0 2006.173.16:39:40.79#ibcon#read 4, iclass 30, count 0 2006.173.16:39:40.79#ibcon#about to read 5, iclass 30, count 0 2006.173.16:39:40.79#ibcon#read 5, iclass 30, count 0 2006.173.16:39:40.79#ibcon#about to read 6, iclass 30, count 0 2006.173.16:39:40.79#ibcon#read 6, iclass 30, count 0 2006.173.16:39:40.79#ibcon#end of sib2, iclass 30, count 0 2006.173.16:39:40.79#ibcon#*mode == 0, iclass 30, count 0 2006.173.16:39:40.79#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.16:39:40.79#ibcon#[27=USB\r\n] 2006.173.16:39:40.79#ibcon#*before write, iclass 30, count 0 2006.173.16:39:40.79#ibcon#enter sib2, iclass 30, count 0 2006.173.16:39:40.79#ibcon#flushed, iclass 30, count 0 2006.173.16:39:40.79#ibcon#about to write, iclass 30, count 0 2006.173.16:39:40.79#ibcon#wrote, iclass 30, count 0 2006.173.16:39:40.79#ibcon#about to read 3, iclass 30, count 0 2006.173.16:39:40.82#ibcon#read 3, iclass 30, count 0 2006.173.16:39:40.82#ibcon#about to read 4, iclass 30, count 0 2006.173.16:39:40.82#ibcon#read 4, iclass 30, count 0 2006.173.16:39:40.82#ibcon#about to read 5, iclass 30, count 0 2006.173.16:39:40.82#ibcon#read 5, iclass 30, count 0 2006.173.16:39:40.82#ibcon#about to read 6, iclass 30, count 0 2006.173.16:39:40.82#ibcon#read 6, iclass 30, count 0 2006.173.16:39:40.82#ibcon#end of sib2, iclass 30, count 0 2006.173.16:39:40.82#ibcon#*after write, iclass 30, count 0 2006.173.16:39:40.82#ibcon#*before return 0, iclass 30, count 0 2006.173.16:39:40.82#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.16:39:40.82#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.16:39:40.82#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.16:39:40.82#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.16:39:40.82$vck44/vblo=6,719.99 2006.173.16:39:40.82#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.16:39:40.82#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.16:39:40.82#ibcon#ireg 17 cls_cnt 0 2006.173.16:39:40.82#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.16:39:40.82#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.16:39:40.82#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.16:39:40.82#ibcon#enter wrdev, iclass 32, count 0 2006.173.16:39:40.82#ibcon#first serial, iclass 32, count 0 2006.173.16:39:40.82#ibcon#enter sib2, iclass 32, count 0 2006.173.16:39:40.82#ibcon#flushed, iclass 32, count 0 2006.173.16:39:40.82#ibcon#about to write, iclass 32, count 0 2006.173.16:39:40.82#ibcon#wrote, iclass 32, count 0 2006.173.16:39:40.82#ibcon#about to read 3, iclass 32, count 0 2006.173.16:39:40.84#ibcon#read 3, iclass 32, count 0 2006.173.16:39:40.84#ibcon#about to read 4, iclass 32, count 0 2006.173.16:39:40.84#ibcon#read 4, iclass 32, count 0 2006.173.16:39:40.84#ibcon#about to read 5, iclass 32, count 0 2006.173.16:39:40.84#ibcon#read 5, iclass 32, count 0 2006.173.16:39:40.84#ibcon#about to read 6, iclass 32, count 0 2006.173.16:39:40.84#ibcon#read 6, iclass 32, count 0 2006.173.16:39:40.84#ibcon#end of sib2, iclass 32, count 0 2006.173.16:39:40.84#ibcon#*mode == 0, iclass 32, count 0 2006.173.16:39:40.84#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.16:39:40.84#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.16:39:40.84#ibcon#*before write, iclass 32, count 0 2006.173.16:39:40.84#ibcon#enter sib2, iclass 32, count 0 2006.173.16:39:40.84#ibcon#flushed, iclass 32, count 0 2006.173.16:39:40.84#ibcon#about to write, iclass 32, count 0 2006.173.16:39:40.84#ibcon#wrote, iclass 32, count 0 2006.173.16:39:40.84#ibcon#about to read 3, iclass 32, count 0 2006.173.16:39:40.88#ibcon#read 3, iclass 32, count 0 2006.173.16:39:40.88#ibcon#about to read 4, iclass 32, count 0 2006.173.16:39:40.88#ibcon#read 4, iclass 32, count 0 2006.173.16:39:40.88#ibcon#about to read 5, iclass 32, count 0 2006.173.16:39:40.88#ibcon#read 5, iclass 32, count 0 2006.173.16:39:40.88#ibcon#about to read 6, iclass 32, count 0 2006.173.16:39:40.88#ibcon#read 6, iclass 32, count 0 2006.173.16:39:40.88#ibcon#end of sib2, iclass 32, count 0 2006.173.16:39:40.88#ibcon#*after write, iclass 32, count 0 2006.173.16:39:40.88#ibcon#*before return 0, iclass 32, count 0 2006.173.16:39:40.88#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.16:39:40.88#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.16:39:40.88#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.16:39:40.88#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.16:39:40.88$vck44/vb=6,4 2006.173.16:39:40.88#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.16:39:40.88#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.16:39:40.88#ibcon#ireg 11 cls_cnt 2 2006.173.16:39:40.88#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.16:39:40.94#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.16:39:40.94#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.16:39:40.94#ibcon#enter wrdev, iclass 34, count 2 2006.173.16:39:40.94#ibcon#first serial, iclass 34, count 2 2006.173.16:39:40.94#ibcon#enter sib2, iclass 34, count 2 2006.173.16:39:40.94#ibcon#flushed, iclass 34, count 2 2006.173.16:39:40.94#ibcon#about to write, iclass 34, count 2 2006.173.16:39:40.94#ibcon#wrote, iclass 34, count 2 2006.173.16:39:40.94#ibcon#about to read 3, iclass 34, count 2 2006.173.16:39:40.96#ibcon#read 3, iclass 34, count 2 2006.173.16:39:40.96#ibcon#about to read 4, iclass 34, count 2 2006.173.16:39:40.96#ibcon#read 4, iclass 34, count 2 2006.173.16:39:40.96#ibcon#about to read 5, iclass 34, count 2 2006.173.16:39:40.96#ibcon#read 5, iclass 34, count 2 2006.173.16:39:40.96#ibcon#about to read 6, iclass 34, count 2 2006.173.16:39:40.96#ibcon#read 6, iclass 34, count 2 2006.173.16:39:40.96#ibcon#end of sib2, iclass 34, count 2 2006.173.16:39:40.96#ibcon#*mode == 0, iclass 34, count 2 2006.173.16:39:40.96#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.16:39:40.96#ibcon#[27=AT06-04\r\n] 2006.173.16:39:40.96#ibcon#*before write, iclass 34, count 2 2006.173.16:39:40.96#ibcon#enter sib2, iclass 34, count 2 2006.173.16:39:40.96#ibcon#flushed, iclass 34, count 2 2006.173.16:39:40.96#ibcon#about to write, iclass 34, count 2 2006.173.16:39:40.96#ibcon#wrote, iclass 34, count 2 2006.173.16:39:40.96#ibcon#about to read 3, iclass 34, count 2 2006.173.16:39:40.99#ibcon#read 3, iclass 34, count 2 2006.173.16:39:40.99#ibcon#about to read 4, iclass 34, count 2 2006.173.16:39:40.99#ibcon#read 4, iclass 34, count 2 2006.173.16:39:40.99#ibcon#about to read 5, iclass 34, count 2 2006.173.16:39:40.99#ibcon#read 5, iclass 34, count 2 2006.173.16:39:40.99#ibcon#about to read 6, iclass 34, count 2 2006.173.16:39:40.99#ibcon#read 6, iclass 34, count 2 2006.173.16:39:40.99#ibcon#end of sib2, iclass 34, count 2 2006.173.16:39:40.99#ibcon#*after write, iclass 34, count 2 2006.173.16:39:40.99#ibcon#*before return 0, iclass 34, count 2 2006.173.16:39:40.99#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.16:39:40.99#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.16:39:40.99#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.16:39:40.99#ibcon#ireg 7 cls_cnt 0 2006.173.16:39:40.99#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.16:39:41.11#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.16:39:41.11#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.16:39:41.11#ibcon#enter wrdev, iclass 34, count 0 2006.173.16:39:41.11#ibcon#first serial, iclass 34, count 0 2006.173.16:39:41.11#ibcon#enter sib2, iclass 34, count 0 2006.173.16:39:41.11#ibcon#flushed, iclass 34, count 0 2006.173.16:39:41.11#ibcon#about to write, iclass 34, count 0 2006.173.16:39:41.11#ibcon#wrote, iclass 34, count 0 2006.173.16:39:41.11#ibcon#about to read 3, iclass 34, count 0 2006.173.16:39:41.13#ibcon#read 3, iclass 34, count 0 2006.173.16:39:41.13#ibcon#about to read 4, iclass 34, count 0 2006.173.16:39:41.13#ibcon#read 4, iclass 34, count 0 2006.173.16:39:41.13#ibcon#about to read 5, iclass 34, count 0 2006.173.16:39:41.13#ibcon#read 5, iclass 34, count 0 2006.173.16:39:41.13#ibcon#about to read 6, iclass 34, count 0 2006.173.16:39:41.13#ibcon#read 6, iclass 34, count 0 2006.173.16:39:41.13#ibcon#end of sib2, iclass 34, count 0 2006.173.16:39:41.13#ibcon#*mode == 0, iclass 34, count 0 2006.173.16:39:41.13#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.16:39:41.13#ibcon#[27=USB\r\n] 2006.173.16:39:41.13#ibcon#*before write, iclass 34, count 0 2006.173.16:39:41.13#ibcon#enter sib2, iclass 34, count 0 2006.173.16:39:41.13#ibcon#flushed, iclass 34, count 0 2006.173.16:39:41.13#ibcon#about to write, iclass 34, count 0 2006.173.16:39:41.13#ibcon#wrote, iclass 34, count 0 2006.173.16:39:41.13#ibcon#about to read 3, iclass 34, count 0 2006.173.16:39:41.16#ibcon#read 3, iclass 34, count 0 2006.173.16:39:41.16#ibcon#about to read 4, iclass 34, count 0 2006.173.16:39:41.16#ibcon#read 4, iclass 34, count 0 2006.173.16:39:41.16#ibcon#about to read 5, iclass 34, count 0 2006.173.16:39:41.16#ibcon#read 5, iclass 34, count 0 2006.173.16:39:41.16#ibcon#about to read 6, iclass 34, count 0 2006.173.16:39:41.16#ibcon#read 6, iclass 34, count 0 2006.173.16:39:41.16#ibcon#end of sib2, iclass 34, count 0 2006.173.16:39:41.16#ibcon#*after write, iclass 34, count 0 2006.173.16:39:41.16#ibcon#*before return 0, iclass 34, count 0 2006.173.16:39:41.16#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.16:39:41.16#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.16:39:41.16#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.16:39:41.16#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.16:39:41.16$vck44/vblo=7,734.99 2006.173.16:39:41.16#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.16:39:41.16#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.16:39:41.16#ibcon#ireg 17 cls_cnt 0 2006.173.16:39:41.16#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.16:39:41.16#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.16:39:41.16#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.16:39:41.16#ibcon#enter wrdev, iclass 36, count 0 2006.173.16:39:41.16#ibcon#first serial, iclass 36, count 0 2006.173.16:39:41.16#ibcon#enter sib2, iclass 36, count 0 2006.173.16:39:41.16#ibcon#flushed, iclass 36, count 0 2006.173.16:39:41.16#ibcon#about to write, iclass 36, count 0 2006.173.16:39:41.16#ibcon#wrote, iclass 36, count 0 2006.173.16:39:41.16#ibcon#about to read 3, iclass 36, count 0 2006.173.16:39:41.18#ibcon#read 3, iclass 36, count 0 2006.173.16:39:41.18#ibcon#about to read 4, iclass 36, count 0 2006.173.16:39:41.18#ibcon#read 4, iclass 36, count 0 2006.173.16:39:41.18#ibcon#about to read 5, iclass 36, count 0 2006.173.16:39:41.18#ibcon#read 5, iclass 36, count 0 2006.173.16:39:41.18#ibcon#about to read 6, iclass 36, count 0 2006.173.16:39:41.18#ibcon#read 6, iclass 36, count 0 2006.173.16:39:41.18#ibcon#end of sib2, iclass 36, count 0 2006.173.16:39:41.18#ibcon#*mode == 0, iclass 36, count 0 2006.173.16:39:41.18#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.16:39:41.18#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.16:39:41.18#ibcon#*before write, iclass 36, count 0 2006.173.16:39:41.18#ibcon#enter sib2, iclass 36, count 0 2006.173.16:39:41.18#ibcon#flushed, iclass 36, count 0 2006.173.16:39:41.18#ibcon#about to write, iclass 36, count 0 2006.173.16:39:41.18#ibcon#wrote, iclass 36, count 0 2006.173.16:39:41.18#ibcon#about to read 3, iclass 36, count 0 2006.173.16:39:41.22#ibcon#read 3, iclass 36, count 0 2006.173.16:39:41.22#ibcon#about to read 4, iclass 36, count 0 2006.173.16:39:41.22#ibcon#read 4, iclass 36, count 0 2006.173.16:39:41.22#ibcon#about to read 5, iclass 36, count 0 2006.173.16:39:41.22#ibcon#read 5, iclass 36, count 0 2006.173.16:39:41.22#ibcon#about to read 6, iclass 36, count 0 2006.173.16:39:41.22#ibcon#read 6, iclass 36, count 0 2006.173.16:39:41.22#ibcon#end of sib2, iclass 36, count 0 2006.173.16:39:41.22#ibcon#*after write, iclass 36, count 0 2006.173.16:39:41.22#ibcon#*before return 0, iclass 36, count 0 2006.173.16:39:41.22#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.16:39:41.22#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.16:39:41.22#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.16:39:41.22#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.16:39:41.22$vck44/vb=7,4 2006.173.16:39:41.22#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.16:39:41.22#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.16:39:41.22#ibcon#ireg 11 cls_cnt 2 2006.173.16:39:41.22#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.16:39:41.28#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.16:39:41.28#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.16:39:41.28#ibcon#enter wrdev, iclass 38, count 2 2006.173.16:39:41.28#ibcon#first serial, iclass 38, count 2 2006.173.16:39:41.28#ibcon#enter sib2, iclass 38, count 2 2006.173.16:39:41.28#ibcon#flushed, iclass 38, count 2 2006.173.16:39:41.28#ibcon#about to write, iclass 38, count 2 2006.173.16:39:41.28#ibcon#wrote, iclass 38, count 2 2006.173.16:39:41.28#ibcon#about to read 3, iclass 38, count 2 2006.173.16:39:41.30#ibcon#read 3, iclass 38, count 2 2006.173.16:39:41.30#ibcon#about to read 4, iclass 38, count 2 2006.173.16:39:41.30#ibcon#read 4, iclass 38, count 2 2006.173.16:39:41.30#ibcon#about to read 5, iclass 38, count 2 2006.173.16:39:41.30#ibcon#read 5, iclass 38, count 2 2006.173.16:39:41.30#ibcon#about to read 6, iclass 38, count 2 2006.173.16:39:41.30#ibcon#read 6, iclass 38, count 2 2006.173.16:39:41.30#ibcon#end of sib2, iclass 38, count 2 2006.173.16:39:41.30#ibcon#*mode == 0, iclass 38, count 2 2006.173.16:39:41.30#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.16:39:41.30#ibcon#[27=AT07-04\r\n] 2006.173.16:39:41.30#ibcon#*before write, iclass 38, count 2 2006.173.16:39:41.30#ibcon#enter sib2, iclass 38, count 2 2006.173.16:39:41.30#ibcon#flushed, iclass 38, count 2 2006.173.16:39:41.30#ibcon#about to write, iclass 38, count 2 2006.173.16:39:41.30#ibcon#wrote, iclass 38, count 2 2006.173.16:39:41.30#ibcon#about to read 3, iclass 38, count 2 2006.173.16:39:41.33#ibcon#read 3, iclass 38, count 2 2006.173.16:39:41.33#ibcon#about to read 4, iclass 38, count 2 2006.173.16:39:41.33#ibcon#read 4, iclass 38, count 2 2006.173.16:39:41.33#ibcon#about to read 5, iclass 38, count 2 2006.173.16:39:41.33#ibcon#read 5, iclass 38, count 2 2006.173.16:39:41.33#ibcon#about to read 6, iclass 38, count 2 2006.173.16:39:41.33#ibcon#read 6, iclass 38, count 2 2006.173.16:39:41.33#ibcon#end of sib2, iclass 38, count 2 2006.173.16:39:41.33#ibcon#*after write, iclass 38, count 2 2006.173.16:39:41.33#ibcon#*before return 0, iclass 38, count 2 2006.173.16:39:41.33#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.16:39:41.33#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.16:39:41.33#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.16:39:41.33#ibcon#ireg 7 cls_cnt 0 2006.173.16:39:41.33#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.16:39:41.45#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.16:39:41.45#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.16:39:41.45#ibcon#enter wrdev, iclass 38, count 0 2006.173.16:39:41.45#ibcon#first serial, iclass 38, count 0 2006.173.16:39:41.45#ibcon#enter sib2, iclass 38, count 0 2006.173.16:39:41.45#ibcon#flushed, iclass 38, count 0 2006.173.16:39:41.45#ibcon#about to write, iclass 38, count 0 2006.173.16:39:41.45#ibcon#wrote, iclass 38, count 0 2006.173.16:39:41.45#ibcon#about to read 3, iclass 38, count 0 2006.173.16:39:41.47#ibcon#read 3, iclass 38, count 0 2006.173.16:39:41.47#ibcon#about to read 4, iclass 38, count 0 2006.173.16:39:41.47#ibcon#read 4, iclass 38, count 0 2006.173.16:39:41.47#ibcon#about to read 5, iclass 38, count 0 2006.173.16:39:41.47#ibcon#read 5, iclass 38, count 0 2006.173.16:39:41.47#ibcon#about to read 6, iclass 38, count 0 2006.173.16:39:41.47#ibcon#read 6, iclass 38, count 0 2006.173.16:39:41.47#ibcon#end of sib2, iclass 38, count 0 2006.173.16:39:41.47#ibcon#*mode == 0, iclass 38, count 0 2006.173.16:39:41.47#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.16:39:41.47#ibcon#[27=USB\r\n] 2006.173.16:39:41.47#ibcon#*before write, iclass 38, count 0 2006.173.16:39:41.47#ibcon#enter sib2, iclass 38, count 0 2006.173.16:39:41.47#ibcon#flushed, iclass 38, count 0 2006.173.16:39:41.47#ibcon#about to write, iclass 38, count 0 2006.173.16:39:41.47#ibcon#wrote, iclass 38, count 0 2006.173.16:39:41.47#ibcon#about to read 3, iclass 38, count 0 2006.173.16:39:41.50#ibcon#read 3, iclass 38, count 0 2006.173.16:39:41.50#ibcon#about to read 4, iclass 38, count 0 2006.173.16:39:41.50#ibcon#read 4, iclass 38, count 0 2006.173.16:39:41.50#ibcon#about to read 5, iclass 38, count 0 2006.173.16:39:41.50#ibcon#read 5, iclass 38, count 0 2006.173.16:39:41.50#ibcon#about to read 6, iclass 38, count 0 2006.173.16:39:41.50#ibcon#read 6, iclass 38, count 0 2006.173.16:39:41.50#ibcon#end of sib2, iclass 38, count 0 2006.173.16:39:41.50#ibcon#*after write, iclass 38, count 0 2006.173.16:39:41.50#ibcon#*before return 0, iclass 38, count 0 2006.173.16:39:41.50#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.16:39:41.50#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.16:39:41.50#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.16:39:41.50#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.16:39:41.50$vck44/vblo=8,744.99 2006.173.16:39:41.50#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.16:39:41.50#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.16:39:41.50#ibcon#ireg 17 cls_cnt 0 2006.173.16:39:41.50#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.16:39:41.50#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.16:39:41.50#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.16:39:41.50#ibcon#enter wrdev, iclass 40, count 0 2006.173.16:39:41.50#ibcon#first serial, iclass 40, count 0 2006.173.16:39:41.50#ibcon#enter sib2, iclass 40, count 0 2006.173.16:39:41.50#ibcon#flushed, iclass 40, count 0 2006.173.16:39:41.50#ibcon#about to write, iclass 40, count 0 2006.173.16:39:41.50#ibcon#wrote, iclass 40, count 0 2006.173.16:39:41.50#ibcon#about to read 3, iclass 40, count 0 2006.173.16:39:41.52#ibcon#read 3, iclass 40, count 0 2006.173.16:39:41.52#ibcon#about to read 4, iclass 40, count 0 2006.173.16:39:41.52#ibcon#read 4, iclass 40, count 0 2006.173.16:39:41.52#ibcon#about to read 5, iclass 40, count 0 2006.173.16:39:41.52#ibcon#read 5, iclass 40, count 0 2006.173.16:39:41.52#ibcon#about to read 6, iclass 40, count 0 2006.173.16:39:41.52#ibcon#read 6, iclass 40, count 0 2006.173.16:39:41.52#ibcon#end of sib2, iclass 40, count 0 2006.173.16:39:41.52#ibcon#*mode == 0, iclass 40, count 0 2006.173.16:39:41.52#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.16:39:41.52#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.16:39:41.52#ibcon#*before write, iclass 40, count 0 2006.173.16:39:41.52#ibcon#enter sib2, iclass 40, count 0 2006.173.16:39:41.52#ibcon#flushed, iclass 40, count 0 2006.173.16:39:41.52#ibcon#about to write, iclass 40, count 0 2006.173.16:39:41.52#ibcon#wrote, iclass 40, count 0 2006.173.16:39:41.52#ibcon#about to read 3, iclass 40, count 0 2006.173.16:39:41.56#ibcon#read 3, iclass 40, count 0 2006.173.16:39:41.56#ibcon#about to read 4, iclass 40, count 0 2006.173.16:39:41.56#ibcon#read 4, iclass 40, count 0 2006.173.16:39:41.56#ibcon#about to read 5, iclass 40, count 0 2006.173.16:39:41.56#ibcon#read 5, iclass 40, count 0 2006.173.16:39:41.56#ibcon#about to read 6, iclass 40, count 0 2006.173.16:39:41.56#ibcon#read 6, iclass 40, count 0 2006.173.16:39:41.56#ibcon#end of sib2, iclass 40, count 0 2006.173.16:39:41.56#ibcon#*after write, iclass 40, count 0 2006.173.16:39:41.56#ibcon#*before return 0, iclass 40, count 0 2006.173.16:39:41.56#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.16:39:41.56#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.16:39:41.56#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.16:39:41.56#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.16:39:41.56$vck44/vb=8,4 2006.173.16:39:41.56#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.16:39:41.56#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.16:39:41.56#ibcon#ireg 11 cls_cnt 2 2006.173.16:39:41.56#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.16:39:41.62#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.16:39:41.62#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.16:39:41.62#ibcon#enter wrdev, iclass 4, count 2 2006.173.16:39:41.62#ibcon#first serial, iclass 4, count 2 2006.173.16:39:41.62#ibcon#enter sib2, iclass 4, count 2 2006.173.16:39:41.62#ibcon#flushed, iclass 4, count 2 2006.173.16:39:41.62#ibcon#about to write, iclass 4, count 2 2006.173.16:39:41.62#ibcon#wrote, iclass 4, count 2 2006.173.16:39:41.62#ibcon#about to read 3, iclass 4, count 2 2006.173.16:39:41.64#ibcon#read 3, iclass 4, count 2 2006.173.16:39:41.64#ibcon#about to read 4, iclass 4, count 2 2006.173.16:39:41.64#ibcon#read 4, iclass 4, count 2 2006.173.16:39:41.64#ibcon#about to read 5, iclass 4, count 2 2006.173.16:39:41.64#ibcon#read 5, iclass 4, count 2 2006.173.16:39:41.64#ibcon#about to read 6, iclass 4, count 2 2006.173.16:39:41.64#ibcon#read 6, iclass 4, count 2 2006.173.16:39:41.64#ibcon#end of sib2, iclass 4, count 2 2006.173.16:39:41.64#ibcon#*mode == 0, iclass 4, count 2 2006.173.16:39:41.64#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.16:39:41.64#ibcon#[27=AT08-04\r\n] 2006.173.16:39:41.64#ibcon#*before write, iclass 4, count 2 2006.173.16:39:41.64#ibcon#enter sib2, iclass 4, count 2 2006.173.16:39:41.64#ibcon#flushed, iclass 4, count 2 2006.173.16:39:41.64#ibcon#about to write, iclass 4, count 2 2006.173.16:39:41.64#ibcon#wrote, iclass 4, count 2 2006.173.16:39:41.64#ibcon#about to read 3, iclass 4, count 2 2006.173.16:39:41.67#ibcon#read 3, iclass 4, count 2 2006.173.16:39:41.67#ibcon#about to read 4, iclass 4, count 2 2006.173.16:39:41.67#ibcon#read 4, iclass 4, count 2 2006.173.16:39:41.67#ibcon#about to read 5, iclass 4, count 2 2006.173.16:39:41.67#ibcon#read 5, iclass 4, count 2 2006.173.16:39:41.67#ibcon#about to read 6, iclass 4, count 2 2006.173.16:39:41.67#ibcon#read 6, iclass 4, count 2 2006.173.16:39:41.67#ibcon#end of sib2, iclass 4, count 2 2006.173.16:39:41.67#ibcon#*after write, iclass 4, count 2 2006.173.16:39:41.67#ibcon#*before return 0, iclass 4, count 2 2006.173.16:39:41.67#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.16:39:41.67#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.16:39:41.67#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.16:39:41.67#ibcon#ireg 7 cls_cnt 0 2006.173.16:39:41.67#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.16:39:41.79#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.16:39:41.79#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.16:39:41.79#ibcon#enter wrdev, iclass 4, count 0 2006.173.16:39:41.79#ibcon#first serial, iclass 4, count 0 2006.173.16:39:41.79#ibcon#enter sib2, iclass 4, count 0 2006.173.16:39:41.79#ibcon#flushed, iclass 4, count 0 2006.173.16:39:41.79#ibcon#about to write, iclass 4, count 0 2006.173.16:39:41.79#ibcon#wrote, iclass 4, count 0 2006.173.16:39:41.79#ibcon#about to read 3, iclass 4, count 0 2006.173.16:39:41.81#ibcon#read 3, iclass 4, count 0 2006.173.16:39:41.81#ibcon#about to read 4, iclass 4, count 0 2006.173.16:39:41.81#ibcon#read 4, iclass 4, count 0 2006.173.16:39:41.81#ibcon#about to read 5, iclass 4, count 0 2006.173.16:39:41.81#ibcon#read 5, iclass 4, count 0 2006.173.16:39:41.81#ibcon#about to read 6, iclass 4, count 0 2006.173.16:39:41.81#ibcon#read 6, iclass 4, count 0 2006.173.16:39:41.81#ibcon#end of sib2, iclass 4, count 0 2006.173.16:39:41.81#ibcon#*mode == 0, iclass 4, count 0 2006.173.16:39:41.81#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.16:39:41.81#ibcon#[27=USB\r\n] 2006.173.16:39:41.81#ibcon#*before write, iclass 4, count 0 2006.173.16:39:41.81#ibcon#enter sib2, iclass 4, count 0 2006.173.16:39:41.81#ibcon#flushed, iclass 4, count 0 2006.173.16:39:41.81#ibcon#about to write, iclass 4, count 0 2006.173.16:39:41.81#ibcon#wrote, iclass 4, count 0 2006.173.16:39:41.81#ibcon#about to read 3, iclass 4, count 0 2006.173.16:39:41.84#ibcon#read 3, iclass 4, count 0 2006.173.16:39:41.84#ibcon#about to read 4, iclass 4, count 0 2006.173.16:39:41.84#ibcon#read 4, iclass 4, count 0 2006.173.16:39:41.84#ibcon#about to read 5, iclass 4, count 0 2006.173.16:39:41.84#ibcon#read 5, iclass 4, count 0 2006.173.16:39:41.84#ibcon#about to read 6, iclass 4, count 0 2006.173.16:39:41.84#ibcon#read 6, iclass 4, count 0 2006.173.16:39:41.84#ibcon#end of sib2, iclass 4, count 0 2006.173.16:39:41.84#ibcon#*after write, iclass 4, count 0 2006.173.16:39:41.84#ibcon#*before return 0, iclass 4, count 0 2006.173.16:39:41.84#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.16:39:41.84#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.16:39:41.84#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.16:39:41.84#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.16:39:41.93$vck44/vabw=wide 2006.173.16:39:41.93#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.16:39:41.93#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.16:39:41.93#ibcon#ireg 8 cls_cnt 0 2006.173.16:39:41.93#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.16:39:41.93#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.16:39:41.93#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.16:39:41.93#ibcon#enter wrdev, iclass 6, count 0 2006.173.16:39:41.93#ibcon#first serial, iclass 6, count 0 2006.173.16:39:41.93#ibcon#enter sib2, iclass 6, count 0 2006.173.16:39:41.93#ibcon#flushed, iclass 6, count 0 2006.173.16:39:41.93#ibcon#about to write, iclass 6, count 0 2006.173.16:39:41.93#ibcon#wrote, iclass 6, count 0 2006.173.16:39:41.93#ibcon#about to read 3, iclass 6, count 0 2006.173.16:39:41.95#ibcon#read 3, iclass 6, count 0 2006.173.16:39:41.95#ibcon#about to read 4, iclass 6, count 0 2006.173.16:39:41.95#ibcon#read 4, iclass 6, count 0 2006.173.16:39:41.95#ibcon#about to read 5, iclass 6, count 0 2006.173.16:39:41.95#ibcon#read 5, iclass 6, count 0 2006.173.16:39:41.95#ibcon#about to read 6, iclass 6, count 0 2006.173.16:39:41.95#ibcon#read 6, iclass 6, count 0 2006.173.16:39:41.95#ibcon#end of sib2, iclass 6, count 0 2006.173.16:39:41.95#ibcon#*mode == 0, iclass 6, count 0 2006.173.16:39:41.95#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.16:39:41.95#ibcon#[25=BW32\r\n] 2006.173.16:39:41.95#ibcon#*before write, iclass 6, count 0 2006.173.16:39:41.95#ibcon#enter sib2, iclass 6, count 0 2006.173.16:39:41.95#ibcon#flushed, iclass 6, count 0 2006.173.16:39:41.95#ibcon#about to write, iclass 6, count 0 2006.173.16:39:41.95#ibcon#wrote, iclass 6, count 0 2006.173.16:39:41.95#ibcon#about to read 3, iclass 6, count 0 2006.173.16:39:41.98#ibcon#read 3, iclass 6, count 0 2006.173.16:39:41.98#ibcon#about to read 4, iclass 6, count 0 2006.173.16:39:41.98#ibcon#read 4, iclass 6, count 0 2006.173.16:39:41.98#ibcon#about to read 5, iclass 6, count 0 2006.173.16:39:41.98#ibcon#read 5, iclass 6, count 0 2006.173.16:39:41.98#ibcon#about to read 6, iclass 6, count 0 2006.173.16:39:41.98#ibcon#read 6, iclass 6, count 0 2006.173.16:39:41.98#ibcon#end of sib2, iclass 6, count 0 2006.173.16:39:41.98#ibcon#*after write, iclass 6, count 0 2006.173.16:39:41.98#ibcon#*before return 0, iclass 6, count 0 2006.173.16:39:41.98#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.16:39:41.98#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.16:39:41.98#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.16:39:41.98#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.16:39:41.98$vck44/vbbw=wide 2006.173.16:39:41.98#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.16:39:41.98#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.16:39:41.98#ibcon#ireg 8 cls_cnt 0 2006.173.16:39:41.98#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.16:39:41.98#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.16:39:41.98#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.16:39:41.98#ibcon#enter wrdev, iclass 10, count 0 2006.173.16:39:41.98#ibcon#first serial, iclass 10, count 0 2006.173.16:39:41.98#ibcon#enter sib2, iclass 10, count 0 2006.173.16:39:41.98#ibcon#flushed, iclass 10, count 0 2006.173.16:39:41.98#ibcon#about to write, iclass 10, count 0 2006.173.16:39:41.98#ibcon#wrote, iclass 10, count 0 2006.173.16:39:41.98#ibcon#about to read 3, iclass 10, count 0 2006.173.16:39:42.00#ibcon#read 3, iclass 10, count 0 2006.173.16:39:42.00#ibcon#about to read 4, iclass 10, count 0 2006.173.16:39:42.00#ibcon#read 4, iclass 10, count 0 2006.173.16:39:42.00#ibcon#about to read 5, iclass 10, count 0 2006.173.16:39:42.00#ibcon#read 5, iclass 10, count 0 2006.173.16:39:42.00#ibcon#about to read 6, iclass 10, count 0 2006.173.16:39:42.00#ibcon#read 6, iclass 10, count 0 2006.173.16:39:42.00#ibcon#end of sib2, iclass 10, count 0 2006.173.16:39:42.00#ibcon#*mode == 0, iclass 10, count 0 2006.173.16:39:42.00#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.16:39:42.00#ibcon#[27=BW32\r\n] 2006.173.16:39:42.00#ibcon#*before write, iclass 10, count 0 2006.173.16:39:42.00#ibcon#enter sib2, iclass 10, count 0 2006.173.16:39:42.00#ibcon#flushed, iclass 10, count 0 2006.173.16:39:42.00#ibcon#about to write, iclass 10, count 0 2006.173.16:39:42.00#ibcon#wrote, iclass 10, count 0 2006.173.16:39:42.00#ibcon#about to read 3, iclass 10, count 0 2006.173.16:39:42.03#ibcon#read 3, iclass 10, count 0 2006.173.16:39:42.03#ibcon#about to read 4, iclass 10, count 0 2006.173.16:39:42.03#ibcon#read 4, iclass 10, count 0 2006.173.16:39:42.03#ibcon#about to read 5, iclass 10, count 0 2006.173.16:39:42.03#ibcon#read 5, iclass 10, count 0 2006.173.16:39:42.03#ibcon#about to read 6, iclass 10, count 0 2006.173.16:39:42.03#ibcon#read 6, iclass 10, count 0 2006.173.16:39:42.03#ibcon#end of sib2, iclass 10, count 0 2006.173.16:39:42.03#ibcon#*after write, iclass 10, count 0 2006.173.16:39:42.03#ibcon#*before return 0, iclass 10, count 0 2006.173.16:39:42.03#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.16:39:42.03#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.16:39:42.03#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.16:39:42.03#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.16:39:42.03$setupk4/ifdk4 2006.173.16:39:42.03$ifdk4/lo= 2006.173.16:39:42.03$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.16:39:42.03$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.16:39:42.03$ifdk4/patch= 2006.173.16:39:42.03$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.16:39:42.03$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.16:39:42.03$setupk4/!*+20s 2006.173.16:39:48.48#abcon#<5=/13 0.4 1.0 20.411001002.8\r\n> 2006.173.16:39:48.50#abcon#{5=INTERFACE CLEAR} 2006.173.16:39:48.56#abcon#[5=S1D000X0/0*\r\n] 2006.173.16:39:53.14#trakl#Source acquired 2006.173.16:39:53.14#flagr#flagr/antenna,acquired 2006.173.16:39:56.23$setupk4/"tpicd 2006.173.16:39:56.23$setupk4/echo=off 2006.173.16:39:56.23$setupk4/xlog=off 2006.173.16:39:56.23:!2006.173.16:44:51 2006.173.16:44:51.01:preob 2006.173.16:44:52.14/onsource/TRACKING 2006.173.16:44:52.14:!2006.173.16:45:01 2006.173.16:45:01.00:"tape 2006.173.16:45:01.00:"st=record 2006.173.16:45:01.00:data_valid=on 2006.173.16:45:01.00:midob 2006.173.16:45:01.14/onsource/TRACKING 2006.173.16:45:01.15/wx/20.42,1002.9,100 2006.173.16:45:01.24/cable/+6.5137E-03 2006.173.16:45:02.33/va/01,07,usb,yes,35,38 2006.173.16:45:02.33/va/02,06,usb,yes,35,36 2006.173.16:45:02.33/va/03,05,usb,yes,45,47 2006.173.16:45:02.33/va/04,06,usb,yes,36,38 2006.173.16:45:02.33/va/05,04,usb,yes,28,29 2006.173.16:45:02.33/va/06,03,usb,yes,39,39 2006.173.16:45:02.33/va/07,04,usb,yes,32,33 2006.173.16:45:02.33/va/08,04,usb,yes,27,33 2006.173.16:45:02.56/valo/01,524.99,yes,locked 2006.173.16:45:02.56/valo/02,534.99,yes,locked 2006.173.16:45:02.56/valo/03,564.99,yes,locked 2006.173.16:45:02.56/valo/04,624.99,yes,locked 2006.173.16:45:02.56/valo/05,734.99,yes,locked 2006.173.16:45:02.56/valo/06,814.99,yes,locked 2006.173.16:45:02.56/valo/07,864.99,yes,locked 2006.173.16:45:02.56/valo/08,884.99,yes,locked 2006.173.16:45:03.65/vb/01,04,usb,yes,29,27 2006.173.16:45:03.65/vb/02,04,usb,yes,31,31 2006.173.16:45:03.65/vb/03,04,usb,yes,28,31 2006.173.16:45:03.65/vb/04,04,usb,yes,33,32 2006.173.16:45:03.65/vb/05,04,usb,yes,25,28 2006.173.16:45:03.65/vb/06,04,usb,yes,30,26 2006.173.16:45:03.65/vb/07,04,usb,yes,29,29 2006.173.16:45:03.65/vb/08,04,usb,yes,27,30 2006.173.16:45:03.89/vblo/01,629.99,yes,locked 2006.173.16:45:03.89/vblo/02,634.99,yes,locked 2006.173.16:45:03.89/vblo/03,649.99,yes,locked 2006.173.16:45:03.89/vblo/04,679.99,yes,locked 2006.173.16:45:03.89/vblo/05,709.99,yes,locked 2006.173.16:45:03.89/vblo/06,719.99,yes,locked 2006.173.16:45:03.89/vblo/07,734.99,yes,locked 2006.173.16:45:03.89/vblo/08,744.99,yes,locked 2006.173.16:45:04.04/vabw/8 2006.173.16:45:04.19/vbbw/8 2006.173.16:45:04.28/xfe/off,on,15.2 2006.173.16:45:04.67/ifatt/23,28,28,28 2006.173.16:45:05.07/fmout-gps/S +3.93E-07 2006.173.16:45:05.12:!2006.173.16:48:01 2006.173.16:48:01.01:data_valid=off 2006.173.16:48:01.01:"et 2006.173.16:48:01.01:!+3s 2006.173.16:48:04.02:"tape 2006.173.16:48:04.02:postob 2006.173.16:48:04.08/cable/+6.5112E-03 2006.173.16:48:04.08/wx/20.43,1002.6,100 2006.173.16:48:04.14/fmout-gps/S +3.94E-07 2006.173.16:48:04.14:scan_name=173-1650,jd0606,40 2006.173.16:48:04.15:source=1741-038,174358.86,-035004.6,2000.0,ccw 2006.173.16:48:06.14#flagr#flagr/antenna,new-source 2006.173.16:48:06.14:checkk5 2006.173.16:48:06.56/chk_autoobs//k5ts1/ autoobs is running! 2006.173.16:48:06.97/chk_autoobs//k5ts2/ autoobs is running! 2006.173.16:48:07.36/chk_autoobs//k5ts3/ autoobs is running! 2006.173.16:48:07.75/chk_autoobs//k5ts4/ autoobs is running! 2006.173.16:48:08.14/chk_obsdata//k5ts1/T1731645??a.dat file size is correct (nominal:720MB, actual:716MB). 2006.173.16:48:08.55/chk_obsdata//k5ts2/T1731645??b.dat file size is correct (nominal:720MB, actual:716MB). 2006.173.16:48:08.95/chk_obsdata//k5ts3/T1731645??c.dat file size is correct (nominal:720MB, actual:716MB). 2006.173.16:48:09.35/chk_obsdata//k5ts4/T1731645??d.dat file size is correct (nominal:720MB, actual:716MB). 2006.173.16:48:10.05/k5log//k5ts1_log_newline 2006.173.16:48:10.76/k5log//k5ts2_log_newline 2006.173.16:48:11.48/k5log//k5ts3_log_newline 2006.173.16:48:12.18/k5log//k5ts4_log_newline 2006.173.16:48:12.21/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.16:48:12.21:setupk4=1 2006.173.16:48:12.21$setupk4/echo=on 2006.173.16:48:12.21$setupk4/pcalon 2006.173.16:48:12.21$pcalon/"no phase cal control is implemented here 2006.173.16:48:12.21$setupk4/"tpicd=stop 2006.173.16:48:12.21$setupk4/"rec=synch_on 2006.173.16:48:12.21$setupk4/"rec_mode=128 2006.173.16:48:12.21$setupk4/!* 2006.173.16:48:12.21$setupk4/recpk4 2006.173.16:48:12.21$recpk4/recpatch= 2006.173.16:48:12.22$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.16:48:12.22$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.16:48:12.22$setupk4/vck44 2006.173.16:48:12.22$vck44/valo=1,524.99 2006.173.16:48:12.22#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.16:48:12.22#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.16:48:12.22#ibcon#ireg 17 cls_cnt 0 2006.173.16:48:12.22#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.16:48:12.22#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.16:48:12.22#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.16:48:12.22#ibcon#enter wrdev, iclass 35, count 0 2006.173.16:48:12.22#ibcon#first serial, iclass 35, count 0 2006.173.16:48:12.22#ibcon#enter sib2, iclass 35, count 0 2006.173.16:48:12.22#ibcon#flushed, iclass 35, count 0 2006.173.16:48:12.22#ibcon#about to write, iclass 35, count 0 2006.173.16:48:12.22#ibcon#wrote, iclass 35, count 0 2006.173.16:48:12.22#ibcon#about to read 3, iclass 35, count 0 2006.173.16:48:12.23#ibcon#read 3, iclass 35, count 0 2006.173.16:48:12.23#ibcon#about to read 4, iclass 35, count 0 2006.173.16:48:12.23#ibcon#read 4, iclass 35, count 0 2006.173.16:48:12.23#ibcon#about to read 5, iclass 35, count 0 2006.173.16:48:12.23#ibcon#read 5, iclass 35, count 0 2006.173.16:48:12.23#ibcon#about to read 6, iclass 35, count 0 2006.173.16:48:12.23#ibcon#read 6, iclass 35, count 0 2006.173.16:48:12.23#ibcon#end of sib2, iclass 35, count 0 2006.173.16:48:12.23#ibcon#*mode == 0, iclass 35, count 0 2006.173.16:48:12.23#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.16:48:12.23#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.16:48:12.23#ibcon#*before write, iclass 35, count 0 2006.173.16:48:12.23#ibcon#enter sib2, iclass 35, count 0 2006.173.16:48:12.23#ibcon#flushed, iclass 35, count 0 2006.173.16:48:12.23#ibcon#about to write, iclass 35, count 0 2006.173.16:48:12.23#ibcon#wrote, iclass 35, count 0 2006.173.16:48:12.23#ibcon#about to read 3, iclass 35, count 0 2006.173.16:48:12.28#ibcon#read 3, iclass 35, count 0 2006.173.16:48:12.28#ibcon#about to read 4, iclass 35, count 0 2006.173.16:48:12.28#ibcon#read 4, iclass 35, count 0 2006.173.16:48:12.28#ibcon#about to read 5, iclass 35, count 0 2006.173.16:48:12.28#ibcon#read 5, iclass 35, count 0 2006.173.16:48:12.28#ibcon#about to read 6, iclass 35, count 0 2006.173.16:48:12.28#ibcon#read 6, iclass 35, count 0 2006.173.16:48:12.28#ibcon#end of sib2, iclass 35, count 0 2006.173.16:48:12.28#ibcon#*after write, iclass 35, count 0 2006.173.16:48:12.28#ibcon#*before return 0, iclass 35, count 0 2006.173.16:48:12.28#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.16:48:12.28#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.16:48:12.28#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.16:48:12.28#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.16:48:12.28$vck44/va=1,7 2006.173.16:48:12.28#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.173.16:48:12.28#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.173.16:48:12.28#ibcon#ireg 11 cls_cnt 2 2006.173.16:48:12.28#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.16:48:12.28#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.16:48:12.28#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.16:48:12.28#ibcon#enter wrdev, iclass 37, count 2 2006.173.16:48:12.28#ibcon#first serial, iclass 37, count 2 2006.173.16:48:12.28#ibcon#enter sib2, iclass 37, count 2 2006.173.16:48:12.28#ibcon#flushed, iclass 37, count 2 2006.173.16:48:12.28#ibcon#about to write, iclass 37, count 2 2006.173.16:48:12.28#ibcon#wrote, iclass 37, count 2 2006.173.16:48:12.28#ibcon#about to read 3, iclass 37, count 2 2006.173.16:48:12.30#ibcon#read 3, iclass 37, count 2 2006.173.16:48:12.30#ibcon#about to read 4, iclass 37, count 2 2006.173.16:48:12.30#ibcon#read 4, iclass 37, count 2 2006.173.16:48:12.30#ibcon#about to read 5, iclass 37, count 2 2006.173.16:48:12.30#ibcon#read 5, iclass 37, count 2 2006.173.16:48:12.30#ibcon#about to read 6, iclass 37, count 2 2006.173.16:48:12.30#ibcon#read 6, iclass 37, count 2 2006.173.16:48:12.30#ibcon#end of sib2, iclass 37, count 2 2006.173.16:48:12.30#ibcon#*mode == 0, iclass 37, count 2 2006.173.16:48:12.30#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.173.16:48:12.30#ibcon#[25=AT01-07\r\n] 2006.173.16:48:12.30#ibcon#*before write, iclass 37, count 2 2006.173.16:48:12.30#ibcon#enter sib2, iclass 37, count 2 2006.173.16:48:12.30#ibcon#flushed, iclass 37, count 2 2006.173.16:48:12.30#ibcon#about to write, iclass 37, count 2 2006.173.16:48:12.30#ibcon#wrote, iclass 37, count 2 2006.173.16:48:12.30#ibcon#about to read 3, iclass 37, count 2 2006.173.16:48:12.33#ibcon#read 3, iclass 37, count 2 2006.173.16:48:12.33#ibcon#about to read 4, iclass 37, count 2 2006.173.16:48:12.33#ibcon#read 4, iclass 37, count 2 2006.173.16:48:12.33#ibcon#about to read 5, iclass 37, count 2 2006.173.16:48:12.33#ibcon#read 5, iclass 37, count 2 2006.173.16:48:12.33#ibcon#about to read 6, iclass 37, count 2 2006.173.16:48:12.33#ibcon#read 6, iclass 37, count 2 2006.173.16:48:12.33#ibcon#end of sib2, iclass 37, count 2 2006.173.16:48:12.33#ibcon#*after write, iclass 37, count 2 2006.173.16:48:12.33#ibcon#*before return 0, iclass 37, count 2 2006.173.16:48:12.33#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.16:48:12.33#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.173.16:48:12.33#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.173.16:48:12.33#ibcon#ireg 7 cls_cnt 0 2006.173.16:48:12.33#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.16:48:12.45#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.16:48:12.45#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.16:48:12.45#ibcon#enter wrdev, iclass 37, count 0 2006.173.16:48:12.45#ibcon#first serial, iclass 37, count 0 2006.173.16:48:12.45#ibcon#enter sib2, iclass 37, count 0 2006.173.16:48:12.45#ibcon#flushed, iclass 37, count 0 2006.173.16:48:12.45#ibcon#about to write, iclass 37, count 0 2006.173.16:48:12.45#ibcon#wrote, iclass 37, count 0 2006.173.16:48:12.45#ibcon#about to read 3, iclass 37, count 0 2006.173.16:48:12.47#ibcon#read 3, iclass 37, count 0 2006.173.16:48:12.47#ibcon#about to read 4, iclass 37, count 0 2006.173.16:48:12.47#ibcon#read 4, iclass 37, count 0 2006.173.16:48:12.47#ibcon#about to read 5, iclass 37, count 0 2006.173.16:48:12.47#ibcon#read 5, iclass 37, count 0 2006.173.16:48:12.47#ibcon#about to read 6, iclass 37, count 0 2006.173.16:48:12.47#ibcon#read 6, iclass 37, count 0 2006.173.16:48:12.47#ibcon#end of sib2, iclass 37, count 0 2006.173.16:48:12.47#ibcon#*mode == 0, iclass 37, count 0 2006.173.16:48:12.47#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.16:48:12.47#ibcon#[25=USB\r\n] 2006.173.16:48:12.47#ibcon#*before write, iclass 37, count 0 2006.173.16:48:12.47#ibcon#enter sib2, iclass 37, count 0 2006.173.16:48:12.47#ibcon#flushed, iclass 37, count 0 2006.173.16:48:12.47#ibcon#about to write, iclass 37, count 0 2006.173.16:48:12.47#ibcon#wrote, iclass 37, count 0 2006.173.16:48:12.47#ibcon#about to read 3, iclass 37, count 0 2006.173.16:48:12.50#ibcon#read 3, iclass 37, count 0 2006.173.16:48:12.50#ibcon#about to read 4, iclass 37, count 0 2006.173.16:48:12.50#ibcon#read 4, iclass 37, count 0 2006.173.16:48:12.50#ibcon#about to read 5, iclass 37, count 0 2006.173.16:48:12.50#ibcon#read 5, iclass 37, count 0 2006.173.16:48:12.50#ibcon#about to read 6, iclass 37, count 0 2006.173.16:48:12.50#ibcon#read 6, iclass 37, count 0 2006.173.16:48:12.50#ibcon#end of sib2, iclass 37, count 0 2006.173.16:48:12.50#ibcon#*after write, iclass 37, count 0 2006.173.16:48:12.50#ibcon#*before return 0, iclass 37, count 0 2006.173.16:48:12.50#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.16:48:12.50#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.173.16:48:12.50#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.16:48:12.50#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.16:48:12.50$vck44/valo=2,534.99 2006.173.16:48:12.50#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.16:48:12.50#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.16:48:12.50#ibcon#ireg 17 cls_cnt 0 2006.173.16:48:12.50#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.16:48:12.50#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.16:48:12.50#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.16:48:12.50#ibcon#enter wrdev, iclass 39, count 0 2006.173.16:48:12.50#ibcon#first serial, iclass 39, count 0 2006.173.16:48:12.50#ibcon#enter sib2, iclass 39, count 0 2006.173.16:48:12.50#ibcon#flushed, iclass 39, count 0 2006.173.16:48:12.50#ibcon#about to write, iclass 39, count 0 2006.173.16:48:12.50#ibcon#wrote, iclass 39, count 0 2006.173.16:48:12.50#ibcon#about to read 3, iclass 39, count 0 2006.173.16:48:12.52#ibcon#read 3, iclass 39, count 0 2006.173.16:48:12.52#ibcon#about to read 4, iclass 39, count 0 2006.173.16:48:12.52#ibcon#read 4, iclass 39, count 0 2006.173.16:48:12.52#ibcon#about to read 5, iclass 39, count 0 2006.173.16:48:12.52#ibcon#read 5, iclass 39, count 0 2006.173.16:48:12.52#ibcon#about to read 6, iclass 39, count 0 2006.173.16:48:12.52#ibcon#read 6, iclass 39, count 0 2006.173.16:48:12.52#ibcon#end of sib2, iclass 39, count 0 2006.173.16:48:12.52#ibcon#*mode == 0, iclass 39, count 0 2006.173.16:48:12.52#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.16:48:12.52#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.16:48:12.52#ibcon#*before write, iclass 39, count 0 2006.173.16:48:12.52#ibcon#enter sib2, iclass 39, count 0 2006.173.16:48:12.52#ibcon#flushed, iclass 39, count 0 2006.173.16:48:12.52#ibcon#about to write, iclass 39, count 0 2006.173.16:48:12.52#ibcon#wrote, iclass 39, count 0 2006.173.16:48:12.52#ibcon#about to read 3, iclass 39, count 0 2006.173.16:48:12.56#ibcon#read 3, iclass 39, count 0 2006.173.16:48:12.56#ibcon#about to read 4, iclass 39, count 0 2006.173.16:48:12.56#ibcon#read 4, iclass 39, count 0 2006.173.16:48:12.56#ibcon#about to read 5, iclass 39, count 0 2006.173.16:48:12.56#ibcon#read 5, iclass 39, count 0 2006.173.16:48:12.56#ibcon#about to read 6, iclass 39, count 0 2006.173.16:48:12.56#ibcon#read 6, iclass 39, count 0 2006.173.16:48:12.56#ibcon#end of sib2, iclass 39, count 0 2006.173.16:48:12.56#ibcon#*after write, iclass 39, count 0 2006.173.16:48:12.56#ibcon#*before return 0, iclass 39, count 0 2006.173.16:48:12.56#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.16:48:12.56#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.16:48:12.56#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.16:48:12.56#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.16:48:12.56$vck44/va=2,6 2006.173.16:48:12.56#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.16:48:12.56#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.16:48:12.56#ibcon#ireg 11 cls_cnt 2 2006.173.16:48:12.56#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.16:48:12.62#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.16:48:12.62#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.16:48:12.62#ibcon#enter wrdev, iclass 3, count 2 2006.173.16:48:12.62#ibcon#first serial, iclass 3, count 2 2006.173.16:48:12.62#ibcon#enter sib2, iclass 3, count 2 2006.173.16:48:12.62#ibcon#flushed, iclass 3, count 2 2006.173.16:48:12.62#ibcon#about to write, iclass 3, count 2 2006.173.16:48:12.62#ibcon#wrote, iclass 3, count 2 2006.173.16:48:12.62#ibcon#about to read 3, iclass 3, count 2 2006.173.16:48:12.64#ibcon#read 3, iclass 3, count 2 2006.173.16:48:12.64#ibcon#about to read 4, iclass 3, count 2 2006.173.16:48:12.64#ibcon#read 4, iclass 3, count 2 2006.173.16:48:12.64#ibcon#about to read 5, iclass 3, count 2 2006.173.16:48:12.64#ibcon#read 5, iclass 3, count 2 2006.173.16:48:12.64#ibcon#about to read 6, iclass 3, count 2 2006.173.16:48:12.64#ibcon#read 6, iclass 3, count 2 2006.173.16:48:12.64#ibcon#end of sib2, iclass 3, count 2 2006.173.16:48:12.64#ibcon#*mode == 0, iclass 3, count 2 2006.173.16:48:12.64#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.16:48:12.64#ibcon#[25=AT02-06\r\n] 2006.173.16:48:12.64#ibcon#*before write, iclass 3, count 2 2006.173.16:48:12.64#ibcon#enter sib2, iclass 3, count 2 2006.173.16:48:12.64#ibcon#flushed, iclass 3, count 2 2006.173.16:48:12.64#ibcon#about to write, iclass 3, count 2 2006.173.16:48:12.64#ibcon#wrote, iclass 3, count 2 2006.173.16:48:12.64#ibcon#about to read 3, iclass 3, count 2 2006.173.16:48:12.67#ibcon#read 3, iclass 3, count 2 2006.173.16:48:12.67#ibcon#about to read 4, iclass 3, count 2 2006.173.16:48:12.67#ibcon#read 4, iclass 3, count 2 2006.173.16:48:12.67#ibcon#about to read 5, iclass 3, count 2 2006.173.16:48:12.67#ibcon#read 5, iclass 3, count 2 2006.173.16:48:12.67#ibcon#about to read 6, iclass 3, count 2 2006.173.16:48:12.67#ibcon#read 6, iclass 3, count 2 2006.173.16:48:12.67#ibcon#end of sib2, iclass 3, count 2 2006.173.16:48:12.67#ibcon#*after write, iclass 3, count 2 2006.173.16:48:12.67#ibcon#*before return 0, iclass 3, count 2 2006.173.16:48:12.67#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.16:48:12.67#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.16:48:12.67#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.16:48:12.67#ibcon#ireg 7 cls_cnt 0 2006.173.16:48:12.67#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.16:48:12.79#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.16:48:12.79#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.16:48:12.79#ibcon#enter wrdev, iclass 3, count 0 2006.173.16:48:12.79#ibcon#first serial, iclass 3, count 0 2006.173.16:48:12.79#ibcon#enter sib2, iclass 3, count 0 2006.173.16:48:12.79#ibcon#flushed, iclass 3, count 0 2006.173.16:48:12.79#ibcon#about to write, iclass 3, count 0 2006.173.16:48:12.79#ibcon#wrote, iclass 3, count 0 2006.173.16:48:12.79#ibcon#about to read 3, iclass 3, count 0 2006.173.16:48:12.81#ibcon#read 3, iclass 3, count 0 2006.173.16:48:12.81#ibcon#about to read 4, iclass 3, count 0 2006.173.16:48:12.81#ibcon#read 4, iclass 3, count 0 2006.173.16:48:12.81#ibcon#about to read 5, iclass 3, count 0 2006.173.16:48:12.81#ibcon#read 5, iclass 3, count 0 2006.173.16:48:12.81#ibcon#about to read 6, iclass 3, count 0 2006.173.16:48:12.81#ibcon#read 6, iclass 3, count 0 2006.173.16:48:12.81#ibcon#end of sib2, iclass 3, count 0 2006.173.16:48:12.81#ibcon#*mode == 0, iclass 3, count 0 2006.173.16:48:12.81#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.16:48:12.81#ibcon#[25=USB\r\n] 2006.173.16:48:12.81#ibcon#*before write, iclass 3, count 0 2006.173.16:48:12.81#ibcon#enter sib2, iclass 3, count 0 2006.173.16:48:12.81#ibcon#flushed, iclass 3, count 0 2006.173.16:48:12.81#ibcon#about to write, iclass 3, count 0 2006.173.16:48:12.81#ibcon#wrote, iclass 3, count 0 2006.173.16:48:12.81#ibcon#about to read 3, iclass 3, count 0 2006.173.16:48:12.84#ibcon#read 3, iclass 3, count 0 2006.173.16:48:12.84#ibcon#about to read 4, iclass 3, count 0 2006.173.16:48:12.84#ibcon#read 4, iclass 3, count 0 2006.173.16:48:12.84#ibcon#about to read 5, iclass 3, count 0 2006.173.16:48:12.84#ibcon#read 5, iclass 3, count 0 2006.173.16:48:12.84#ibcon#about to read 6, iclass 3, count 0 2006.173.16:48:12.84#ibcon#read 6, iclass 3, count 0 2006.173.16:48:12.84#ibcon#end of sib2, iclass 3, count 0 2006.173.16:48:12.84#ibcon#*after write, iclass 3, count 0 2006.173.16:48:12.84#ibcon#*before return 0, iclass 3, count 0 2006.173.16:48:12.84#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.16:48:12.84#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.16:48:12.84#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.16:48:12.84#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.16:48:12.84$vck44/valo=3,564.99 2006.173.16:48:12.84#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.16:48:12.84#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.16:48:12.84#ibcon#ireg 17 cls_cnt 0 2006.173.16:48:12.84#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.16:48:12.84#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.16:48:12.84#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.16:48:12.84#ibcon#enter wrdev, iclass 5, count 0 2006.173.16:48:12.84#ibcon#first serial, iclass 5, count 0 2006.173.16:48:12.84#ibcon#enter sib2, iclass 5, count 0 2006.173.16:48:12.84#ibcon#flushed, iclass 5, count 0 2006.173.16:48:12.84#ibcon#about to write, iclass 5, count 0 2006.173.16:48:12.84#ibcon#wrote, iclass 5, count 0 2006.173.16:48:12.84#ibcon#about to read 3, iclass 5, count 0 2006.173.16:48:12.86#ibcon#read 3, iclass 5, count 0 2006.173.16:48:12.86#ibcon#about to read 4, iclass 5, count 0 2006.173.16:48:12.86#ibcon#read 4, iclass 5, count 0 2006.173.16:48:12.86#ibcon#about to read 5, iclass 5, count 0 2006.173.16:48:12.86#ibcon#read 5, iclass 5, count 0 2006.173.16:48:12.86#ibcon#about to read 6, iclass 5, count 0 2006.173.16:48:12.86#ibcon#read 6, iclass 5, count 0 2006.173.16:48:12.86#ibcon#end of sib2, iclass 5, count 0 2006.173.16:48:12.86#ibcon#*mode == 0, iclass 5, count 0 2006.173.16:48:12.86#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.16:48:12.86#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.16:48:12.86#ibcon#*before write, iclass 5, count 0 2006.173.16:48:12.86#ibcon#enter sib2, iclass 5, count 0 2006.173.16:48:12.86#ibcon#flushed, iclass 5, count 0 2006.173.16:48:12.86#ibcon#about to write, iclass 5, count 0 2006.173.16:48:12.86#ibcon#wrote, iclass 5, count 0 2006.173.16:48:12.86#ibcon#about to read 3, iclass 5, count 0 2006.173.16:48:12.90#ibcon#read 3, iclass 5, count 0 2006.173.16:48:12.90#ibcon#about to read 4, iclass 5, count 0 2006.173.16:48:12.90#ibcon#read 4, iclass 5, count 0 2006.173.16:48:12.90#ibcon#about to read 5, iclass 5, count 0 2006.173.16:48:12.90#ibcon#read 5, iclass 5, count 0 2006.173.16:48:12.90#ibcon#about to read 6, iclass 5, count 0 2006.173.16:48:12.90#ibcon#read 6, iclass 5, count 0 2006.173.16:48:12.90#ibcon#end of sib2, iclass 5, count 0 2006.173.16:48:12.90#ibcon#*after write, iclass 5, count 0 2006.173.16:48:12.90#ibcon#*before return 0, iclass 5, count 0 2006.173.16:48:12.90#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.16:48:12.90#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.16:48:12.90#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.16:48:12.90#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.16:48:12.90$vck44/va=3,5 2006.173.16:48:12.90#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.173.16:48:12.90#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.173.16:48:12.90#ibcon#ireg 11 cls_cnt 2 2006.173.16:48:12.90#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.16:48:12.96#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.16:48:12.96#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.16:48:12.96#ibcon#enter wrdev, iclass 7, count 2 2006.173.16:48:12.96#ibcon#first serial, iclass 7, count 2 2006.173.16:48:12.96#ibcon#enter sib2, iclass 7, count 2 2006.173.16:48:12.96#ibcon#flushed, iclass 7, count 2 2006.173.16:48:12.96#ibcon#about to write, iclass 7, count 2 2006.173.16:48:12.96#ibcon#wrote, iclass 7, count 2 2006.173.16:48:12.96#ibcon#about to read 3, iclass 7, count 2 2006.173.16:48:12.98#ibcon#read 3, iclass 7, count 2 2006.173.16:48:12.98#ibcon#about to read 4, iclass 7, count 2 2006.173.16:48:12.98#ibcon#read 4, iclass 7, count 2 2006.173.16:48:12.98#ibcon#about to read 5, iclass 7, count 2 2006.173.16:48:12.98#ibcon#read 5, iclass 7, count 2 2006.173.16:48:12.98#ibcon#about to read 6, iclass 7, count 2 2006.173.16:48:12.98#ibcon#read 6, iclass 7, count 2 2006.173.16:48:12.98#ibcon#end of sib2, iclass 7, count 2 2006.173.16:48:12.98#ibcon#*mode == 0, iclass 7, count 2 2006.173.16:48:12.98#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.173.16:48:12.98#ibcon#[25=AT03-05\r\n] 2006.173.16:48:12.98#ibcon#*before write, iclass 7, count 2 2006.173.16:48:12.98#ibcon#enter sib2, iclass 7, count 2 2006.173.16:48:12.98#ibcon#flushed, iclass 7, count 2 2006.173.16:48:12.98#ibcon#about to write, iclass 7, count 2 2006.173.16:48:12.98#ibcon#wrote, iclass 7, count 2 2006.173.16:48:12.98#ibcon#about to read 3, iclass 7, count 2 2006.173.16:48:13.01#ibcon#read 3, iclass 7, count 2 2006.173.16:48:13.01#ibcon#about to read 4, iclass 7, count 2 2006.173.16:48:13.01#ibcon#read 4, iclass 7, count 2 2006.173.16:48:13.01#ibcon#about to read 5, iclass 7, count 2 2006.173.16:48:13.01#ibcon#read 5, iclass 7, count 2 2006.173.16:48:13.01#ibcon#about to read 6, iclass 7, count 2 2006.173.16:48:13.01#ibcon#read 6, iclass 7, count 2 2006.173.16:48:13.01#ibcon#end of sib2, iclass 7, count 2 2006.173.16:48:13.01#ibcon#*after write, iclass 7, count 2 2006.173.16:48:13.01#ibcon#*before return 0, iclass 7, count 2 2006.173.16:48:13.01#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.16:48:13.01#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.173.16:48:13.01#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.173.16:48:13.01#ibcon#ireg 7 cls_cnt 0 2006.173.16:48:13.01#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.16:48:13.13#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.16:48:13.13#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.16:48:13.13#ibcon#enter wrdev, iclass 7, count 0 2006.173.16:48:13.13#ibcon#first serial, iclass 7, count 0 2006.173.16:48:13.13#ibcon#enter sib2, iclass 7, count 0 2006.173.16:48:13.13#ibcon#flushed, iclass 7, count 0 2006.173.16:48:13.13#ibcon#about to write, iclass 7, count 0 2006.173.16:48:13.13#ibcon#wrote, iclass 7, count 0 2006.173.16:48:13.13#ibcon#about to read 3, iclass 7, count 0 2006.173.16:48:13.15#ibcon#read 3, iclass 7, count 0 2006.173.16:48:13.15#ibcon#about to read 4, iclass 7, count 0 2006.173.16:48:13.15#ibcon#read 4, iclass 7, count 0 2006.173.16:48:13.15#ibcon#about to read 5, iclass 7, count 0 2006.173.16:48:13.15#ibcon#read 5, iclass 7, count 0 2006.173.16:48:13.15#ibcon#about to read 6, iclass 7, count 0 2006.173.16:48:13.15#ibcon#read 6, iclass 7, count 0 2006.173.16:48:13.15#ibcon#end of sib2, iclass 7, count 0 2006.173.16:48:13.15#ibcon#*mode == 0, iclass 7, count 0 2006.173.16:48:13.15#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.16:48:13.15#ibcon#[25=USB\r\n] 2006.173.16:48:13.15#ibcon#*before write, iclass 7, count 0 2006.173.16:48:13.15#ibcon#enter sib2, iclass 7, count 0 2006.173.16:48:13.15#ibcon#flushed, iclass 7, count 0 2006.173.16:48:13.15#ibcon#about to write, iclass 7, count 0 2006.173.16:48:13.15#ibcon#wrote, iclass 7, count 0 2006.173.16:48:13.15#ibcon#about to read 3, iclass 7, count 0 2006.173.16:48:13.18#ibcon#read 3, iclass 7, count 0 2006.173.16:48:13.18#ibcon#about to read 4, iclass 7, count 0 2006.173.16:48:13.18#ibcon#read 4, iclass 7, count 0 2006.173.16:48:13.18#ibcon#about to read 5, iclass 7, count 0 2006.173.16:48:13.18#ibcon#read 5, iclass 7, count 0 2006.173.16:48:13.18#ibcon#about to read 6, iclass 7, count 0 2006.173.16:48:13.18#ibcon#read 6, iclass 7, count 0 2006.173.16:48:13.18#ibcon#end of sib2, iclass 7, count 0 2006.173.16:48:13.18#ibcon#*after write, iclass 7, count 0 2006.173.16:48:13.18#ibcon#*before return 0, iclass 7, count 0 2006.173.16:48:13.18#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.16:48:13.18#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.173.16:48:13.18#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.16:48:13.18#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.16:48:13.18$vck44/valo=4,624.99 2006.173.16:48:13.18#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.16:48:13.18#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.16:48:13.18#ibcon#ireg 17 cls_cnt 0 2006.173.16:48:13.18#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.16:48:13.18#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.16:48:13.18#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.16:48:13.18#ibcon#enter wrdev, iclass 11, count 0 2006.173.16:48:13.18#ibcon#first serial, iclass 11, count 0 2006.173.16:48:13.18#ibcon#enter sib2, iclass 11, count 0 2006.173.16:48:13.18#ibcon#flushed, iclass 11, count 0 2006.173.16:48:13.18#ibcon#about to write, iclass 11, count 0 2006.173.16:48:13.18#ibcon#wrote, iclass 11, count 0 2006.173.16:48:13.18#ibcon#about to read 3, iclass 11, count 0 2006.173.16:48:13.20#ibcon#read 3, iclass 11, count 0 2006.173.16:48:13.20#ibcon#about to read 4, iclass 11, count 0 2006.173.16:48:13.20#ibcon#read 4, iclass 11, count 0 2006.173.16:48:13.20#ibcon#about to read 5, iclass 11, count 0 2006.173.16:48:13.20#ibcon#read 5, iclass 11, count 0 2006.173.16:48:13.20#ibcon#about to read 6, iclass 11, count 0 2006.173.16:48:13.20#ibcon#read 6, iclass 11, count 0 2006.173.16:48:13.20#ibcon#end of sib2, iclass 11, count 0 2006.173.16:48:13.20#ibcon#*mode == 0, iclass 11, count 0 2006.173.16:48:13.20#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.16:48:13.20#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.16:48:13.20#ibcon#*before write, iclass 11, count 0 2006.173.16:48:13.20#ibcon#enter sib2, iclass 11, count 0 2006.173.16:48:13.20#ibcon#flushed, iclass 11, count 0 2006.173.16:48:13.20#ibcon#about to write, iclass 11, count 0 2006.173.16:48:13.20#ibcon#wrote, iclass 11, count 0 2006.173.16:48:13.20#ibcon#about to read 3, iclass 11, count 0 2006.173.16:48:13.24#ibcon#read 3, iclass 11, count 0 2006.173.16:48:13.24#ibcon#about to read 4, iclass 11, count 0 2006.173.16:48:13.24#ibcon#read 4, iclass 11, count 0 2006.173.16:48:13.24#ibcon#about to read 5, iclass 11, count 0 2006.173.16:48:13.24#ibcon#read 5, iclass 11, count 0 2006.173.16:48:13.24#ibcon#about to read 6, iclass 11, count 0 2006.173.16:48:13.24#ibcon#read 6, iclass 11, count 0 2006.173.16:48:13.24#ibcon#end of sib2, iclass 11, count 0 2006.173.16:48:13.24#ibcon#*after write, iclass 11, count 0 2006.173.16:48:13.24#ibcon#*before return 0, iclass 11, count 0 2006.173.16:48:13.24#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.16:48:13.24#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.16:48:13.24#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.16:48:13.24#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.16:48:13.24$vck44/va=4,6 2006.173.16:48:13.24#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.173.16:48:13.24#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.173.16:48:13.24#ibcon#ireg 11 cls_cnt 2 2006.173.16:48:13.24#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.16:48:13.30#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.16:48:13.30#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.16:48:13.30#ibcon#enter wrdev, iclass 13, count 2 2006.173.16:48:13.30#ibcon#first serial, iclass 13, count 2 2006.173.16:48:13.30#ibcon#enter sib2, iclass 13, count 2 2006.173.16:48:13.30#ibcon#flushed, iclass 13, count 2 2006.173.16:48:13.30#ibcon#about to write, iclass 13, count 2 2006.173.16:48:13.30#ibcon#wrote, iclass 13, count 2 2006.173.16:48:13.30#ibcon#about to read 3, iclass 13, count 2 2006.173.16:48:13.32#ibcon#read 3, iclass 13, count 2 2006.173.16:48:13.32#ibcon#about to read 4, iclass 13, count 2 2006.173.16:48:13.32#ibcon#read 4, iclass 13, count 2 2006.173.16:48:13.32#ibcon#about to read 5, iclass 13, count 2 2006.173.16:48:13.32#ibcon#read 5, iclass 13, count 2 2006.173.16:48:13.32#ibcon#about to read 6, iclass 13, count 2 2006.173.16:48:13.32#ibcon#read 6, iclass 13, count 2 2006.173.16:48:13.32#ibcon#end of sib2, iclass 13, count 2 2006.173.16:48:13.32#ibcon#*mode == 0, iclass 13, count 2 2006.173.16:48:13.32#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.173.16:48:13.32#ibcon#[25=AT04-06\r\n] 2006.173.16:48:13.32#ibcon#*before write, iclass 13, count 2 2006.173.16:48:13.32#ibcon#enter sib2, iclass 13, count 2 2006.173.16:48:13.32#ibcon#flushed, iclass 13, count 2 2006.173.16:48:13.32#ibcon#about to write, iclass 13, count 2 2006.173.16:48:13.32#ibcon#wrote, iclass 13, count 2 2006.173.16:48:13.32#ibcon#about to read 3, iclass 13, count 2 2006.173.16:48:13.35#ibcon#read 3, iclass 13, count 2 2006.173.16:48:13.35#ibcon#about to read 4, iclass 13, count 2 2006.173.16:48:13.35#ibcon#read 4, iclass 13, count 2 2006.173.16:48:13.35#ibcon#about to read 5, iclass 13, count 2 2006.173.16:48:13.35#ibcon#read 5, iclass 13, count 2 2006.173.16:48:13.35#ibcon#about to read 6, iclass 13, count 2 2006.173.16:48:13.35#ibcon#read 6, iclass 13, count 2 2006.173.16:48:13.35#ibcon#end of sib2, iclass 13, count 2 2006.173.16:48:13.35#ibcon#*after write, iclass 13, count 2 2006.173.16:48:13.35#ibcon#*before return 0, iclass 13, count 2 2006.173.16:48:13.35#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.16:48:13.35#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.173.16:48:13.35#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.173.16:48:13.35#ibcon#ireg 7 cls_cnt 0 2006.173.16:48:13.35#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.16:48:13.47#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.16:48:13.47#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.16:48:13.47#ibcon#enter wrdev, iclass 13, count 0 2006.173.16:48:13.47#ibcon#first serial, iclass 13, count 0 2006.173.16:48:13.47#ibcon#enter sib2, iclass 13, count 0 2006.173.16:48:13.47#ibcon#flushed, iclass 13, count 0 2006.173.16:48:13.47#ibcon#about to write, iclass 13, count 0 2006.173.16:48:13.47#ibcon#wrote, iclass 13, count 0 2006.173.16:48:13.47#ibcon#about to read 3, iclass 13, count 0 2006.173.16:48:13.49#ibcon#read 3, iclass 13, count 0 2006.173.16:48:13.49#ibcon#about to read 4, iclass 13, count 0 2006.173.16:48:13.49#ibcon#read 4, iclass 13, count 0 2006.173.16:48:13.49#ibcon#about to read 5, iclass 13, count 0 2006.173.16:48:13.49#ibcon#read 5, iclass 13, count 0 2006.173.16:48:13.49#ibcon#about to read 6, iclass 13, count 0 2006.173.16:48:13.49#ibcon#read 6, iclass 13, count 0 2006.173.16:48:13.49#ibcon#end of sib2, iclass 13, count 0 2006.173.16:48:13.49#ibcon#*mode == 0, iclass 13, count 0 2006.173.16:48:13.49#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.16:48:13.49#ibcon#[25=USB\r\n] 2006.173.16:48:13.49#ibcon#*before write, iclass 13, count 0 2006.173.16:48:13.49#ibcon#enter sib2, iclass 13, count 0 2006.173.16:48:13.49#ibcon#flushed, iclass 13, count 0 2006.173.16:48:13.49#ibcon#about to write, iclass 13, count 0 2006.173.16:48:13.49#ibcon#wrote, iclass 13, count 0 2006.173.16:48:13.49#ibcon#about to read 3, iclass 13, count 0 2006.173.16:48:13.52#ibcon#read 3, iclass 13, count 0 2006.173.16:48:13.52#ibcon#about to read 4, iclass 13, count 0 2006.173.16:48:13.52#ibcon#read 4, iclass 13, count 0 2006.173.16:48:13.52#ibcon#about to read 5, iclass 13, count 0 2006.173.16:48:13.52#ibcon#read 5, iclass 13, count 0 2006.173.16:48:13.52#ibcon#about to read 6, iclass 13, count 0 2006.173.16:48:13.52#ibcon#read 6, iclass 13, count 0 2006.173.16:48:13.52#ibcon#end of sib2, iclass 13, count 0 2006.173.16:48:13.52#ibcon#*after write, iclass 13, count 0 2006.173.16:48:13.52#ibcon#*before return 0, iclass 13, count 0 2006.173.16:48:13.52#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.16:48:13.52#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.173.16:48:13.52#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.16:48:13.52#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.16:48:13.52$vck44/valo=5,734.99 2006.173.16:48:13.52#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.16:48:13.52#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.16:48:13.52#ibcon#ireg 17 cls_cnt 0 2006.173.16:48:13.52#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.16:48:13.52#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.16:48:13.52#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.16:48:13.52#ibcon#enter wrdev, iclass 15, count 0 2006.173.16:48:13.52#ibcon#first serial, iclass 15, count 0 2006.173.16:48:13.52#ibcon#enter sib2, iclass 15, count 0 2006.173.16:48:13.52#ibcon#flushed, iclass 15, count 0 2006.173.16:48:13.52#ibcon#about to write, iclass 15, count 0 2006.173.16:48:13.52#ibcon#wrote, iclass 15, count 0 2006.173.16:48:13.52#ibcon#about to read 3, iclass 15, count 0 2006.173.16:48:13.54#ibcon#read 3, iclass 15, count 0 2006.173.16:48:13.54#ibcon#about to read 4, iclass 15, count 0 2006.173.16:48:13.54#ibcon#read 4, iclass 15, count 0 2006.173.16:48:13.54#ibcon#about to read 5, iclass 15, count 0 2006.173.16:48:13.54#ibcon#read 5, iclass 15, count 0 2006.173.16:48:13.54#ibcon#about to read 6, iclass 15, count 0 2006.173.16:48:13.54#ibcon#read 6, iclass 15, count 0 2006.173.16:48:13.54#ibcon#end of sib2, iclass 15, count 0 2006.173.16:48:13.54#ibcon#*mode == 0, iclass 15, count 0 2006.173.16:48:13.54#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.16:48:13.54#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.16:48:13.54#ibcon#*before write, iclass 15, count 0 2006.173.16:48:13.54#ibcon#enter sib2, iclass 15, count 0 2006.173.16:48:13.54#ibcon#flushed, iclass 15, count 0 2006.173.16:48:13.54#ibcon#about to write, iclass 15, count 0 2006.173.16:48:13.54#ibcon#wrote, iclass 15, count 0 2006.173.16:48:13.54#ibcon#about to read 3, iclass 15, count 0 2006.173.16:48:13.58#ibcon#read 3, iclass 15, count 0 2006.173.16:48:13.58#ibcon#about to read 4, iclass 15, count 0 2006.173.16:48:13.58#ibcon#read 4, iclass 15, count 0 2006.173.16:48:13.58#ibcon#about to read 5, iclass 15, count 0 2006.173.16:48:13.58#ibcon#read 5, iclass 15, count 0 2006.173.16:48:13.58#ibcon#about to read 6, iclass 15, count 0 2006.173.16:48:13.58#ibcon#read 6, iclass 15, count 0 2006.173.16:48:13.58#ibcon#end of sib2, iclass 15, count 0 2006.173.16:48:13.58#ibcon#*after write, iclass 15, count 0 2006.173.16:48:13.58#ibcon#*before return 0, iclass 15, count 0 2006.173.16:48:13.58#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.16:48:13.58#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.16:48:13.58#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.16:48:13.58#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.16:48:13.58$vck44/va=5,4 2006.173.16:48:13.58#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.16:48:13.58#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.16:48:13.58#ibcon#ireg 11 cls_cnt 2 2006.173.16:48:13.58#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.16:48:13.64#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.16:48:13.64#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.16:48:13.64#ibcon#enter wrdev, iclass 17, count 2 2006.173.16:48:13.64#ibcon#first serial, iclass 17, count 2 2006.173.16:48:13.64#ibcon#enter sib2, iclass 17, count 2 2006.173.16:48:13.64#ibcon#flushed, iclass 17, count 2 2006.173.16:48:13.64#ibcon#about to write, iclass 17, count 2 2006.173.16:48:13.64#ibcon#wrote, iclass 17, count 2 2006.173.16:48:13.64#ibcon#about to read 3, iclass 17, count 2 2006.173.16:48:13.66#ibcon#read 3, iclass 17, count 2 2006.173.16:48:13.66#ibcon#about to read 4, iclass 17, count 2 2006.173.16:48:13.66#ibcon#read 4, iclass 17, count 2 2006.173.16:48:13.66#ibcon#about to read 5, iclass 17, count 2 2006.173.16:48:13.66#ibcon#read 5, iclass 17, count 2 2006.173.16:48:13.66#ibcon#about to read 6, iclass 17, count 2 2006.173.16:48:13.66#ibcon#read 6, iclass 17, count 2 2006.173.16:48:13.66#ibcon#end of sib2, iclass 17, count 2 2006.173.16:48:13.66#ibcon#*mode == 0, iclass 17, count 2 2006.173.16:48:13.66#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.16:48:13.66#ibcon#[25=AT05-04\r\n] 2006.173.16:48:13.66#ibcon#*before write, iclass 17, count 2 2006.173.16:48:13.66#ibcon#enter sib2, iclass 17, count 2 2006.173.16:48:13.66#ibcon#flushed, iclass 17, count 2 2006.173.16:48:13.66#ibcon#about to write, iclass 17, count 2 2006.173.16:48:13.66#ibcon#wrote, iclass 17, count 2 2006.173.16:48:13.66#ibcon#about to read 3, iclass 17, count 2 2006.173.16:48:13.69#ibcon#read 3, iclass 17, count 2 2006.173.16:48:13.69#ibcon#about to read 4, iclass 17, count 2 2006.173.16:48:13.69#ibcon#read 4, iclass 17, count 2 2006.173.16:48:13.69#ibcon#about to read 5, iclass 17, count 2 2006.173.16:48:13.69#ibcon#read 5, iclass 17, count 2 2006.173.16:48:13.69#ibcon#about to read 6, iclass 17, count 2 2006.173.16:48:13.69#ibcon#read 6, iclass 17, count 2 2006.173.16:48:13.69#ibcon#end of sib2, iclass 17, count 2 2006.173.16:48:13.69#ibcon#*after write, iclass 17, count 2 2006.173.16:48:13.69#ibcon#*before return 0, iclass 17, count 2 2006.173.16:48:13.69#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.16:48:13.69#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.16:48:13.69#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.16:48:13.69#ibcon#ireg 7 cls_cnt 0 2006.173.16:48:13.69#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.16:48:13.81#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.16:48:13.81#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.16:48:13.81#ibcon#enter wrdev, iclass 17, count 0 2006.173.16:48:13.81#ibcon#first serial, iclass 17, count 0 2006.173.16:48:13.81#ibcon#enter sib2, iclass 17, count 0 2006.173.16:48:13.81#ibcon#flushed, iclass 17, count 0 2006.173.16:48:13.81#ibcon#about to write, iclass 17, count 0 2006.173.16:48:13.81#ibcon#wrote, iclass 17, count 0 2006.173.16:48:13.81#ibcon#about to read 3, iclass 17, count 0 2006.173.16:48:13.83#ibcon#read 3, iclass 17, count 0 2006.173.16:48:13.83#ibcon#about to read 4, iclass 17, count 0 2006.173.16:48:13.83#ibcon#read 4, iclass 17, count 0 2006.173.16:48:13.83#ibcon#about to read 5, iclass 17, count 0 2006.173.16:48:13.83#ibcon#read 5, iclass 17, count 0 2006.173.16:48:13.83#ibcon#about to read 6, iclass 17, count 0 2006.173.16:48:13.83#ibcon#read 6, iclass 17, count 0 2006.173.16:48:13.83#ibcon#end of sib2, iclass 17, count 0 2006.173.16:48:13.83#ibcon#*mode == 0, iclass 17, count 0 2006.173.16:48:13.83#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.16:48:13.83#ibcon#[25=USB\r\n] 2006.173.16:48:13.83#ibcon#*before write, iclass 17, count 0 2006.173.16:48:13.83#ibcon#enter sib2, iclass 17, count 0 2006.173.16:48:13.83#ibcon#flushed, iclass 17, count 0 2006.173.16:48:13.83#ibcon#about to write, iclass 17, count 0 2006.173.16:48:13.83#ibcon#wrote, iclass 17, count 0 2006.173.16:48:13.83#ibcon#about to read 3, iclass 17, count 0 2006.173.16:48:13.86#ibcon#read 3, iclass 17, count 0 2006.173.16:48:13.86#ibcon#about to read 4, iclass 17, count 0 2006.173.16:48:13.86#ibcon#read 4, iclass 17, count 0 2006.173.16:48:13.86#ibcon#about to read 5, iclass 17, count 0 2006.173.16:48:13.86#ibcon#read 5, iclass 17, count 0 2006.173.16:48:13.86#ibcon#about to read 6, iclass 17, count 0 2006.173.16:48:13.86#ibcon#read 6, iclass 17, count 0 2006.173.16:48:13.86#ibcon#end of sib2, iclass 17, count 0 2006.173.16:48:13.86#ibcon#*after write, iclass 17, count 0 2006.173.16:48:13.86#ibcon#*before return 0, iclass 17, count 0 2006.173.16:48:13.86#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.16:48:13.86#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.16:48:13.86#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.16:48:13.86#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.16:48:13.86$vck44/valo=6,814.99 2006.173.16:48:13.86#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.16:48:13.86#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.16:48:13.86#ibcon#ireg 17 cls_cnt 0 2006.173.16:48:13.86#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.16:48:13.86#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.16:48:13.86#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.16:48:13.86#ibcon#enter wrdev, iclass 19, count 0 2006.173.16:48:13.86#ibcon#first serial, iclass 19, count 0 2006.173.16:48:13.86#ibcon#enter sib2, iclass 19, count 0 2006.173.16:48:13.86#ibcon#flushed, iclass 19, count 0 2006.173.16:48:13.86#ibcon#about to write, iclass 19, count 0 2006.173.16:48:13.86#ibcon#wrote, iclass 19, count 0 2006.173.16:48:13.86#ibcon#about to read 3, iclass 19, count 0 2006.173.16:48:13.88#ibcon#read 3, iclass 19, count 0 2006.173.16:48:13.88#ibcon#about to read 4, iclass 19, count 0 2006.173.16:48:13.88#ibcon#read 4, iclass 19, count 0 2006.173.16:48:13.88#ibcon#about to read 5, iclass 19, count 0 2006.173.16:48:13.88#ibcon#read 5, iclass 19, count 0 2006.173.16:48:13.88#ibcon#about to read 6, iclass 19, count 0 2006.173.16:48:13.88#ibcon#read 6, iclass 19, count 0 2006.173.16:48:13.88#ibcon#end of sib2, iclass 19, count 0 2006.173.16:48:13.88#ibcon#*mode == 0, iclass 19, count 0 2006.173.16:48:13.88#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.16:48:13.88#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.16:48:13.88#ibcon#*before write, iclass 19, count 0 2006.173.16:48:13.88#ibcon#enter sib2, iclass 19, count 0 2006.173.16:48:13.88#ibcon#flushed, iclass 19, count 0 2006.173.16:48:13.88#ibcon#about to write, iclass 19, count 0 2006.173.16:48:13.88#ibcon#wrote, iclass 19, count 0 2006.173.16:48:13.88#ibcon#about to read 3, iclass 19, count 0 2006.173.16:48:13.92#ibcon#read 3, iclass 19, count 0 2006.173.16:48:13.92#ibcon#about to read 4, iclass 19, count 0 2006.173.16:48:13.92#ibcon#read 4, iclass 19, count 0 2006.173.16:48:13.92#ibcon#about to read 5, iclass 19, count 0 2006.173.16:48:13.92#ibcon#read 5, iclass 19, count 0 2006.173.16:48:13.92#ibcon#about to read 6, iclass 19, count 0 2006.173.16:48:13.92#ibcon#read 6, iclass 19, count 0 2006.173.16:48:13.92#ibcon#end of sib2, iclass 19, count 0 2006.173.16:48:13.92#ibcon#*after write, iclass 19, count 0 2006.173.16:48:13.92#ibcon#*before return 0, iclass 19, count 0 2006.173.16:48:13.92#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.16:48:13.92#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.16:48:13.92#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.16:48:13.92#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.16:48:13.92$vck44/va=6,3 2006.173.16:48:13.92#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.16:48:13.92#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.16:48:13.92#ibcon#ireg 11 cls_cnt 2 2006.173.16:48:13.92#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.16:48:13.98#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.16:48:13.98#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.16:48:13.98#ibcon#enter wrdev, iclass 21, count 2 2006.173.16:48:13.98#ibcon#first serial, iclass 21, count 2 2006.173.16:48:13.98#ibcon#enter sib2, iclass 21, count 2 2006.173.16:48:13.98#ibcon#flushed, iclass 21, count 2 2006.173.16:48:13.98#ibcon#about to write, iclass 21, count 2 2006.173.16:48:13.98#ibcon#wrote, iclass 21, count 2 2006.173.16:48:13.98#ibcon#about to read 3, iclass 21, count 2 2006.173.16:48:14.00#ibcon#read 3, iclass 21, count 2 2006.173.16:48:14.00#ibcon#about to read 4, iclass 21, count 2 2006.173.16:48:14.00#ibcon#read 4, iclass 21, count 2 2006.173.16:48:14.00#ibcon#about to read 5, iclass 21, count 2 2006.173.16:48:14.00#ibcon#read 5, iclass 21, count 2 2006.173.16:48:14.00#ibcon#about to read 6, iclass 21, count 2 2006.173.16:48:14.00#ibcon#read 6, iclass 21, count 2 2006.173.16:48:14.00#ibcon#end of sib2, iclass 21, count 2 2006.173.16:48:14.00#ibcon#*mode == 0, iclass 21, count 2 2006.173.16:48:14.00#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.16:48:14.00#ibcon#[25=AT06-03\r\n] 2006.173.16:48:14.00#ibcon#*before write, iclass 21, count 2 2006.173.16:48:14.00#ibcon#enter sib2, iclass 21, count 2 2006.173.16:48:14.00#ibcon#flushed, iclass 21, count 2 2006.173.16:48:14.00#ibcon#about to write, iclass 21, count 2 2006.173.16:48:14.00#ibcon#wrote, iclass 21, count 2 2006.173.16:48:14.00#ibcon#about to read 3, iclass 21, count 2 2006.173.16:48:14.03#ibcon#read 3, iclass 21, count 2 2006.173.16:48:14.03#ibcon#about to read 4, iclass 21, count 2 2006.173.16:48:14.03#ibcon#read 4, iclass 21, count 2 2006.173.16:48:14.03#ibcon#about to read 5, iclass 21, count 2 2006.173.16:48:14.03#ibcon#read 5, iclass 21, count 2 2006.173.16:48:14.03#ibcon#about to read 6, iclass 21, count 2 2006.173.16:48:14.03#ibcon#read 6, iclass 21, count 2 2006.173.16:48:14.03#ibcon#end of sib2, iclass 21, count 2 2006.173.16:48:14.03#ibcon#*after write, iclass 21, count 2 2006.173.16:48:14.03#ibcon#*before return 0, iclass 21, count 2 2006.173.16:48:14.03#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.16:48:14.03#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.16:48:14.03#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.16:48:14.03#ibcon#ireg 7 cls_cnt 0 2006.173.16:48:14.03#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.16:48:14.15#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.16:48:14.15#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.16:48:14.15#ibcon#enter wrdev, iclass 21, count 0 2006.173.16:48:14.15#ibcon#first serial, iclass 21, count 0 2006.173.16:48:14.15#ibcon#enter sib2, iclass 21, count 0 2006.173.16:48:14.15#ibcon#flushed, iclass 21, count 0 2006.173.16:48:14.15#ibcon#about to write, iclass 21, count 0 2006.173.16:48:14.15#ibcon#wrote, iclass 21, count 0 2006.173.16:48:14.15#ibcon#about to read 3, iclass 21, count 0 2006.173.16:48:14.17#ibcon#read 3, iclass 21, count 0 2006.173.16:48:14.17#ibcon#about to read 4, iclass 21, count 0 2006.173.16:48:14.17#ibcon#read 4, iclass 21, count 0 2006.173.16:48:14.17#ibcon#about to read 5, iclass 21, count 0 2006.173.16:48:14.17#ibcon#read 5, iclass 21, count 0 2006.173.16:48:14.17#ibcon#about to read 6, iclass 21, count 0 2006.173.16:48:14.17#ibcon#read 6, iclass 21, count 0 2006.173.16:48:14.17#ibcon#end of sib2, iclass 21, count 0 2006.173.16:48:14.17#ibcon#*mode == 0, iclass 21, count 0 2006.173.16:48:14.17#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.16:48:14.17#ibcon#[25=USB\r\n] 2006.173.16:48:14.17#ibcon#*before write, iclass 21, count 0 2006.173.16:48:14.17#ibcon#enter sib2, iclass 21, count 0 2006.173.16:48:14.17#ibcon#flushed, iclass 21, count 0 2006.173.16:48:14.17#ibcon#about to write, iclass 21, count 0 2006.173.16:48:14.17#ibcon#wrote, iclass 21, count 0 2006.173.16:48:14.17#ibcon#about to read 3, iclass 21, count 0 2006.173.16:48:14.20#ibcon#read 3, iclass 21, count 0 2006.173.16:48:14.20#ibcon#about to read 4, iclass 21, count 0 2006.173.16:48:14.20#ibcon#read 4, iclass 21, count 0 2006.173.16:48:14.20#ibcon#about to read 5, iclass 21, count 0 2006.173.16:48:14.20#ibcon#read 5, iclass 21, count 0 2006.173.16:48:14.20#ibcon#about to read 6, iclass 21, count 0 2006.173.16:48:14.20#ibcon#read 6, iclass 21, count 0 2006.173.16:48:14.20#ibcon#end of sib2, iclass 21, count 0 2006.173.16:48:14.20#ibcon#*after write, iclass 21, count 0 2006.173.16:48:14.20#ibcon#*before return 0, iclass 21, count 0 2006.173.16:48:14.20#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.16:48:14.20#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.16:48:14.20#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.16:48:14.20#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.16:48:14.20$vck44/valo=7,864.99 2006.173.16:48:14.20#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.16:48:14.20#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.16:48:14.20#ibcon#ireg 17 cls_cnt 0 2006.173.16:48:14.20#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.16:48:14.20#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.16:48:14.20#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.16:48:14.20#ibcon#enter wrdev, iclass 23, count 0 2006.173.16:48:14.20#ibcon#first serial, iclass 23, count 0 2006.173.16:48:14.20#ibcon#enter sib2, iclass 23, count 0 2006.173.16:48:14.20#ibcon#flushed, iclass 23, count 0 2006.173.16:48:14.20#ibcon#about to write, iclass 23, count 0 2006.173.16:48:14.20#ibcon#wrote, iclass 23, count 0 2006.173.16:48:14.20#ibcon#about to read 3, iclass 23, count 0 2006.173.16:48:14.22#ibcon#read 3, iclass 23, count 0 2006.173.16:48:14.22#ibcon#about to read 4, iclass 23, count 0 2006.173.16:48:14.22#ibcon#read 4, iclass 23, count 0 2006.173.16:48:14.22#ibcon#about to read 5, iclass 23, count 0 2006.173.16:48:14.22#ibcon#read 5, iclass 23, count 0 2006.173.16:48:14.22#ibcon#about to read 6, iclass 23, count 0 2006.173.16:48:14.22#ibcon#read 6, iclass 23, count 0 2006.173.16:48:14.22#ibcon#end of sib2, iclass 23, count 0 2006.173.16:48:14.22#ibcon#*mode == 0, iclass 23, count 0 2006.173.16:48:14.22#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.16:48:14.22#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.16:48:14.22#ibcon#*before write, iclass 23, count 0 2006.173.16:48:14.22#ibcon#enter sib2, iclass 23, count 0 2006.173.16:48:14.22#ibcon#flushed, iclass 23, count 0 2006.173.16:48:14.22#ibcon#about to write, iclass 23, count 0 2006.173.16:48:14.22#ibcon#wrote, iclass 23, count 0 2006.173.16:48:14.22#ibcon#about to read 3, iclass 23, count 0 2006.173.16:48:14.26#ibcon#read 3, iclass 23, count 0 2006.173.16:48:14.26#ibcon#about to read 4, iclass 23, count 0 2006.173.16:48:14.26#ibcon#read 4, iclass 23, count 0 2006.173.16:48:14.26#ibcon#about to read 5, iclass 23, count 0 2006.173.16:48:14.26#ibcon#read 5, iclass 23, count 0 2006.173.16:48:14.26#ibcon#about to read 6, iclass 23, count 0 2006.173.16:48:14.26#ibcon#read 6, iclass 23, count 0 2006.173.16:48:14.26#ibcon#end of sib2, iclass 23, count 0 2006.173.16:48:14.26#ibcon#*after write, iclass 23, count 0 2006.173.16:48:14.26#ibcon#*before return 0, iclass 23, count 0 2006.173.16:48:14.26#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.16:48:14.26#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.16:48:14.26#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.16:48:14.26#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.16:48:14.26$vck44/va=7,4 2006.173.16:48:14.26#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.16:48:14.26#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.16:48:14.26#ibcon#ireg 11 cls_cnt 2 2006.173.16:48:14.26#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.16:48:14.32#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.16:48:14.32#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.16:48:14.32#ibcon#enter wrdev, iclass 25, count 2 2006.173.16:48:14.32#ibcon#first serial, iclass 25, count 2 2006.173.16:48:14.32#ibcon#enter sib2, iclass 25, count 2 2006.173.16:48:14.32#ibcon#flushed, iclass 25, count 2 2006.173.16:48:14.32#ibcon#about to write, iclass 25, count 2 2006.173.16:48:14.32#ibcon#wrote, iclass 25, count 2 2006.173.16:48:14.32#ibcon#about to read 3, iclass 25, count 2 2006.173.16:48:14.34#ibcon#read 3, iclass 25, count 2 2006.173.16:48:14.34#ibcon#about to read 4, iclass 25, count 2 2006.173.16:48:14.34#ibcon#read 4, iclass 25, count 2 2006.173.16:48:14.34#ibcon#about to read 5, iclass 25, count 2 2006.173.16:48:14.34#ibcon#read 5, iclass 25, count 2 2006.173.16:48:14.34#ibcon#about to read 6, iclass 25, count 2 2006.173.16:48:14.34#ibcon#read 6, iclass 25, count 2 2006.173.16:48:14.34#ibcon#end of sib2, iclass 25, count 2 2006.173.16:48:14.34#ibcon#*mode == 0, iclass 25, count 2 2006.173.16:48:14.34#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.16:48:14.34#ibcon#[25=AT07-04\r\n] 2006.173.16:48:14.34#ibcon#*before write, iclass 25, count 2 2006.173.16:48:14.34#ibcon#enter sib2, iclass 25, count 2 2006.173.16:48:14.34#ibcon#flushed, iclass 25, count 2 2006.173.16:48:14.34#ibcon#about to write, iclass 25, count 2 2006.173.16:48:14.34#ibcon#wrote, iclass 25, count 2 2006.173.16:48:14.34#ibcon#about to read 3, iclass 25, count 2 2006.173.16:48:14.37#ibcon#read 3, iclass 25, count 2 2006.173.16:48:14.37#ibcon#about to read 4, iclass 25, count 2 2006.173.16:48:14.37#ibcon#read 4, iclass 25, count 2 2006.173.16:48:14.37#ibcon#about to read 5, iclass 25, count 2 2006.173.16:48:14.37#ibcon#read 5, iclass 25, count 2 2006.173.16:48:14.37#ibcon#about to read 6, iclass 25, count 2 2006.173.16:48:14.37#ibcon#read 6, iclass 25, count 2 2006.173.16:48:14.37#ibcon#end of sib2, iclass 25, count 2 2006.173.16:48:14.37#ibcon#*after write, iclass 25, count 2 2006.173.16:48:14.37#ibcon#*before return 0, iclass 25, count 2 2006.173.16:48:14.37#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.16:48:14.37#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.16:48:14.37#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.16:48:14.37#ibcon#ireg 7 cls_cnt 0 2006.173.16:48:14.37#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.16:48:14.49#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.16:48:14.49#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.16:48:14.49#ibcon#enter wrdev, iclass 25, count 0 2006.173.16:48:14.49#ibcon#first serial, iclass 25, count 0 2006.173.16:48:14.49#ibcon#enter sib2, iclass 25, count 0 2006.173.16:48:14.49#ibcon#flushed, iclass 25, count 0 2006.173.16:48:14.49#ibcon#about to write, iclass 25, count 0 2006.173.16:48:14.49#ibcon#wrote, iclass 25, count 0 2006.173.16:48:14.49#ibcon#about to read 3, iclass 25, count 0 2006.173.16:48:14.51#ibcon#read 3, iclass 25, count 0 2006.173.16:48:14.51#ibcon#about to read 4, iclass 25, count 0 2006.173.16:48:14.51#ibcon#read 4, iclass 25, count 0 2006.173.16:48:14.51#ibcon#about to read 5, iclass 25, count 0 2006.173.16:48:14.51#ibcon#read 5, iclass 25, count 0 2006.173.16:48:14.51#ibcon#about to read 6, iclass 25, count 0 2006.173.16:48:14.51#ibcon#read 6, iclass 25, count 0 2006.173.16:48:14.51#ibcon#end of sib2, iclass 25, count 0 2006.173.16:48:14.51#ibcon#*mode == 0, iclass 25, count 0 2006.173.16:48:14.51#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.16:48:14.51#ibcon#[25=USB\r\n] 2006.173.16:48:14.51#ibcon#*before write, iclass 25, count 0 2006.173.16:48:14.51#ibcon#enter sib2, iclass 25, count 0 2006.173.16:48:14.51#ibcon#flushed, iclass 25, count 0 2006.173.16:48:14.51#ibcon#about to write, iclass 25, count 0 2006.173.16:48:14.51#ibcon#wrote, iclass 25, count 0 2006.173.16:48:14.51#ibcon#about to read 3, iclass 25, count 0 2006.173.16:48:14.54#ibcon#read 3, iclass 25, count 0 2006.173.16:48:14.54#ibcon#about to read 4, iclass 25, count 0 2006.173.16:48:14.54#ibcon#read 4, iclass 25, count 0 2006.173.16:48:14.54#ibcon#about to read 5, iclass 25, count 0 2006.173.16:48:14.54#ibcon#read 5, iclass 25, count 0 2006.173.16:48:14.54#ibcon#about to read 6, iclass 25, count 0 2006.173.16:48:14.54#ibcon#read 6, iclass 25, count 0 2006.173.16:48:14.54#ibcon#end of sib2, iclass 25, count 0 2006.173.16:48:14.54#ibcon#*after write, iclass 25, count 0 2006.173.16:48:14.54#ibcon#*before return 0, iclass 25, count 0 2006.173.16:48:14.54#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.16:48:14.54#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.16:48:14.54#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.16:48:14.54#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.16:48:14.54$vck44/valo=8,884.99 2006.173.16:48:14.54#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.16:48:14.54#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.16:48:14.54#ibcon#ireg 17 cls_cnt 0 2006.173.16:48:14.54#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.16:48:14.54#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.16:48:14.54#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.16:48:14.54#ibcon#enter wrdev, iclass 27, count 0 2006.173.16:48:14.54#ibcon#first serial, iclass 27, count 0 2006.173.16:48:14.54#ibcon#enter sib2, iclass 27, count 0 2006.173.16:48:14.54#ibcon#flushed, iclass 27, count 0 2006.173.16:48:14.54#ibcon#about to write, iclass 27, count 0 2006.173.16:48:14.54#ibcon#wrote, iclass 27, count 0 2006.173.16:48:14.54#ibcon#about to read 3, iclass 27, count 0 2006.173.16:48:14.56#ibcon#read 3, iclass 27, count 0 2006.173.16:48:14.56#ibcon#about to read 4, iclass 27, count 0 2006.173.16:48:14.56#ibcon#read 4, iclass 27, count 0 2006.173.16:48:14.56#ibcon#about to read 5, iclass 27, count 0 2006.173.16:48:14.56#ibcon#read 5, iclass 27, count 0 2006.173.16:48:14.56#ibcon#about to read 6, iclass 27, count 0 2006.173.16:48:14.56#ibcon#read 6, iclass 27, count 0 2006.173.16:48:14.56#ibcon#end of sib2, iclass 27, count 0 2006.173.16:48:14.56#ibcon#*mode == 0, iclass 27, count 0 2006.173.16:48:14.56#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.16:48:14.56#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.16:48:14.56#ibcon#*before write, iclass 27, count 0 2006.173.16:48:14.56#ibcon#enter sib2, iclass 27, count 0 2006.173.16:48:14.56#ibcon#flushed, iclass 27, count 0 2006.173.16:48:14.56#ibcon#about to write, iclass 27, count 0 2006.173.16:48:14.56#ibcon#wrote, iclass 27, count 0 2006.173.16:48:14.56#ibcon#about to read 3, iclass 27, count 0 2006.173.16:48:14.60#ibcon#read 3, iclass 27, count 0 2006.173.16:48:14.60#ibcon#about to read 4, iclass 27, count 0 2006.173.16:48:14.60#ibcon#read 4, iclass 27, count 0 2006.173.16:48:14.60#ibcon#about to read 5, iclass 27, count 0 2006.173.16:48:14.60#ibcon#read 5, iclass 27, count 0 2006.173.16:48:14.60#ibcon#about to read 6, iclass 27, count 0 2006.173.16:48:14.60#ibcon#read 6, iclass 27, count 0 2006.173.16:48:14.60#ibcon#end of sib2, iclass 27, count 0 2006.173.16:48:14.60#ibcon#*after write, iclass 27, count 0 2006.173.16:48:14.60#ibcon#*before return 0, iclass 27, count 0 2006.173.16:48:14.60#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.16:48:14.60#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.16:48:14.60#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.16:48:14.60#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.16:48:14.60$vck44/va=8,4 2006.173.16:48:14.60#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.16:48:14.60#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.16:48:14.60#ibcon#ireg 11 cls_cnt 2 2006.173.16:48:14.60#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.16:48:14.66#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.16:48:14.66#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.16:48:14.66#ibcon#enter wrdev, iclass 29, count 2 2006.173.16:48:14.66#ibcon#first serial, iclass 29, count 2 2006.173.16:48:14.66#ibcon#enter sib2, iclass 29, count 2 2006.173.16:48:14.66#ibcon#flushed, iclass 29, count 2 2006.173.16:48:14.66#ibcon#about to write, iclass 29, count 2 2006.173.16:48:14.66#ibcon#wrote, iclass 29, count 2 2006.173.16:48:14.66#ibcon#about to read 3, iclass 29, count 2 2006.173.16:48:14.68#ibcon#read 3, iclass 29, count 2 2006.173.16:48:14.68#ibcon#about to read 4, iclass 29, count 2 2006.173.16:48:14.68#ibcon#read 4, iclass 29, count 2 2006.173.16:48:14.68#ibcon#about to read 5, iclass 29, count 2 2006.173.16:48:14.68#ibcon#read 5, iclass 29, count 2 2006.173.16:48:14.68#ibcon#about to read 6, iclass 29, count 2 2006.173.16:48:14.68#ibcon#read 6, iclass 29, count 2 2006.173.16:48:14.68#ibcon#end of sib2, iclass 29, count 2 2006.173.16:48:14.68#ibcon#*mode == 0, iclass 29, count 2 2006.173.16:48:14.68#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.16:48:14.68#ibcon#[25=AT08-04\r\n] 2006.173.16:48:14.68#ibcon#*before write, iclass 29, count 2 2006.173.16:48:14.68#ibcon#enter sib2, iclass 29, count 2 2006.173.16:48:14.68#ibcon#flushed, iclass 29, count 2 2006.173.16:48:14.68#ibcon#about to write, iclass 29, count 2 2006.173.16:48:14.68#ibcon#wrote, iclass 29, count 2 2006.173.16:48:14.68#ibcon#about to read 3, iclass 29, count 2 2006.173.16:48:14.71#ibcon#read 3, iclass 29, count 2 2006.173.16:48:14.71#ibcon#about to read 4, iclass 29, count 2 2006.173.16:48:14.71#ibcon#read 4, iclass 29, count 2 2006.173.16:48:14.71#ibcon#about to read 5, iclass 29, count 2 2006.173.16:48:14.71#ibcon#read 5, iclass 29, count 2 2006.173.16:48:14.71#ibcon#about to read 6, iclass 29, count 2 2006.173.16:48:14.71#ibcon#read 6, iclass 29, count 2 2006.173.16:48:14.71#ibcon#end of sib2, iclass 29, count 2 2006.173.16:48:14.71#ibcon#*after write, iclass 29, count 2 2006.173.16:48:14.71#ibcon#*before return 0, iclass 29, count 2 2006.173.16:48:14.71#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.16:48:14.71#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.16:48:14.71#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.16:48:14.71#ibcon#ireg 7 cls_cnt 0 2006.173.16:48:14.71#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.16:48:14.83#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.16:48:14.83#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.16:48:14.83#ibcon#enter wrdev, iclass 29, count 0 2006.173.16:48:14.83#ibcon#first serial, iclass 29, count 0 2006.173.16:48:14.83#ibcon#enter sib2, iclass 29, count 0 2006.173.16:48:14.83#ibcon#flushed, iclass 29, count 0 2006.173.16:48:14.83#ibcon#about to write, iclass 29, count 0 2006.173.16:48:14.83#ibcon#wrote, iclass 29, count 0 2006.173.16:48:14.83#ibcon#about to read 3, iclass 29, count 0 2006.173.16:48:14.85#ibcon#read 3, iclass 29, count 0 2006.173.16:48:14.85#ibcon#about to read 4, iclass 29, count 0 2006.173.16:48:14.85#ibcon#read 4, iclass 29, count 0 2006.173.16:48:14.85#ibcon#about to read 5, iclass 29, count 0 2006.173.16:48:14.85#ibcon#read 5, iclass 29, count 0 2006.173.16:48:14.85#ibcon#about to read 6, iclass 29, count 0 2006.173.16:48:14.85#ibcon#read 6, iclass 29, count 0 2006.173.16:48:14.85#ibcon#end of sib2, iclass 29, count 0 2006.173.16:48:14.85#ibcon#*mode == 0, iclass 29, count 0 2006.173.16:48:14.85#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.16:48:14.85#ibcon#[25=USB\r\n] 2006.173.16:48:14.85#ibcon#*before write, iclass 29, count 0 2006.173.16:48:14.85#ibcon#enter sib2, iclass 29, count 0 2006.173.16:48:14.85#ibcon#flushed, iclass 29, count 0 2006.173.16:48:14.85#ibcon#about to write, iclass 29, count 0 2006.173.16:48:14.85#ibcon#wrote, iclass 29, count 0 2006.173.16:48:14.85#ibcon#about to read 3, iclass 29, count 0 2006.173.16:48:14.88#ibcon#read 3, iclass 29, count 0 2006.173.16:48:14.88#ibcon#about to read 4, iclass 29, count 0 2006.173.16:48:14.88#ibcon#read 4, iclass 29, count 0 2006.173.16:48:14.88#ibcon#about to read 5, iclass 29, count 0 2006.173.16:48:14.88#ibcon#read 5, iclass 29, count 0 2006.173.16:48:14.88#ibcon#about to read 6, iclass 29, count 0 2006.173.16:48:14.88#ibcon#read 6, iclass 29, count 0 2006.173.16:48:14.88#ibcon#end of sib2, iclass 29, count 0 2006.173.16:48:14.88#ibcon#*after write, iclass 29, count 0 2006.173.16:48:14.88#ibcon#*before return 0, iclass 29, count 0 2006.173.16:48:14.88#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.16:48:14.88#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.16:48:14.88#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.16:48:14.88#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.16:48:14.88$vck44/vblo=1,629.99 2006.173.16:48:14.88#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.16:48:14.88#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.16:48:14.88#ibcon#ireg 17 cls_cnt 0 2006.173.16:48:14.88#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.16:48:14.88#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.16:48:14.88#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.16:48:14.88#ibcon#enter wrdev, iclass 31, count 0 2006.173.16:48:14.88#ibcon#first serial, iclass 31, count 0 2006.173.16:48:14.88#ibcon#enter sib2, iclass 31, count 0 2006.173.16:48:14.88#ibcon#flushed, iclass 31, count 0 2006.173.16:48:14.88#ibcon#about to write, iclass 31, count 0 2006.173.16:48:14.88#ibcon#wrote, iclass 31, count 0 2006.173.16:48:14.88#ibcon#about to read 3, iclass 31, count 0 2006.173.16:48:14.90#ibcon#read 3, iclass 31, count 0 2006.173.16:48:14.90#ibcon#about to read 4, iclass 31, count 0 2006.173.16:48:14.90#ibcon#read 4, iclass 31, count 0 2006.173.16:48:14.90#ibcon#about to read 5, iclass 31, count 0 2006.173.16:48:14.90#ibcon#read 5, iclass 31, count 0 2006.173.16:48:14.90#ibcon#about to read 6, iclass 31, count 0 2006.173.16:48:14.90#ibcon#read 6, iclass 31, count 0 2006.173.16:48:14.90#ibcon#end of sib2, iclass 31, count 0 2006.173.16:48:14.90#ibcon#*mode == 0, iclass 31, count 0 2006.173.16:48:14.90#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.16:48:14.90#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.16:48:14.90#ibcon#*before write, iclass 31, count 0 2006.173.16:48:14.90#ibcon#enter sib2, iclass 31, count 0 2006.173.16:48:14.90#ibcon#flushed, iclass 31, count 0 2006.173.16:48:14.90#ibcon#about to write, iclass 31, count 0 2006.173.16:48:14.90#ibcon#wrote, iclass 31, count 0 2006.173.16:48:14.90#ibcon#about to read 3, iclass 31, count 0 2006.173.16:48:14.94#ibcon#read 3, iclass 31, count 0 2006.173.16:48:14.94#ibcon#about to read 4, iclass 31, count 0 2006.173.16:48:14.94#ibcon#read 4, iclass 31, count 0 2006.173.16:48:14.94#ibcon#about to read 5, iclass 31, count 0 2006.173.16:48:14.94#ibcon#read 5, iclass 31, count 0 2006.173.16:48:14.94#ibcon#about to read 6, iclass 31, count 0 2006.173.16:48:14.94#ibcon#read 6, iclass 31, count 0 2006.173.16:48:14.94#ibcon#end of sib2, iclass 31, count 0 2006.173.16:48:14.94#ibcon#*after write, iclass 31, count 0 2006.173.16:48:14.94#ibcon#*before return 0, iclass 31, count 0 2006.173.16:48:14.94#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.16:48:14.94#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.16:48:14.94#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.16:48:14.94#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.16:48:14.94$vck44/vb=1,4 2006.173.16:48:14.94#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.173.16:48:14.94#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.173.16:48:14.94#ibcon#ireg 11 cls_cnt 2 2006.173.16:48:14.94#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.16:48:14.94#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.16:48:14.94#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.16:48:14.94#ibcon#enter wrdev, iclass 33, count 2 2006.173.16:48:14.94#ibcon#first serial, iclass 33, count 2 2006.173.16:48:14.94#ibcon#enter sib2, iclass 33, count 2 2006.173.16:48:14.94#ibcon#flushed, iclass 33, count 2 2006.173.16:48:14.94#ibcon#about to write, iclass 33, count 2 2006.173.16:48:14.94#ibcon#wrote, iclass 33, count 2 2006.173.16:48:14.94#ibcon#about to read 3, iclass 33, count 2 2006.173.16:48:14.96#ibcon#read 3, iclass 33, count 2 2006.173.16:48:14.96#ibcon#about to read 4, iclass 33, count 2 2006.173.16:48:14.96#ibcon#read 4, iclass 33, count 2 2006.173.16:48:14.96#ibcon#about to read 5, iclass 33, count 2 2006.173.16:48:14.96#ibcon#read 5, iclass 33, count 2 2006.173.16:48:14.96#ibcon#about to read 6, iclass 33, count 2 2006.173.16:48:14.96#ibcon#read 6, iclass 33, count 2 2006.173.16:48:14.96#ibcon#end of sib2, iclass 33, count 2 2006.173.16:48:14.96#ibcon#*mode == 0, iclass 33, count 2 2006.173.16:48:14.96#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.173.16:48:14.96#ibcon#[27=AT01-04\r\n] 2006.173.16:48:14.96#ibcon#*before write, iclass 33, count 2 2006.173.16:48:14.96#ibcon#enter sib2, iclass 33, count 2 2006.173.16:48:14.96#ibcon#flushed, iclass 33, count 2 2006.173.16:48:14.96#ibcon#about to write, iclass 33, count 2 2006.173.16:48:14.96#ibcon#wrote, iclass 33, count 2 2006.173.16:48:14.96#ibcon#about to read 3, iclass 33, count 2 2006.173.16:48:14.99#ibcon#read 3, iclass 33, count 2 2006.173.16:48:14.99#ibcon#about to read 4, iclass 33, count 2 2006.173.16:48:14.99#ibcon#read 4, iclass 33, count 2 2006.173.16:48:14.99#ibcon#about to read 5, iclass 33, count 2 2006.173.16:48:14.99#ibcon#read 5, iclass 33, count 2 2006.173.16:48:14.99#ibcon#about to read 6, iclass 33, count 2 2006.173.16:48:14.99#ibcon#read 6, iclass 33, count 2 2006.173.16:48:14.99#ibcon#end of sib2, iclass 33, count 2 2006.173.16:48:14.99#ibcon#*after write, iclass 33, count 2 2006.173.16:48:14.99#ibcon#*before return 0, iclass 33, count 2 2006.173.16:48:14.99#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.16:48:14.99#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.173.16:48:14.99#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.173.16:48:14.99#ibcon#ireg 7 cls_cnt 0 2006.173.16:48:14.99#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.16:48:15.11#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.16:48:15.11#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.16:48:15.11#ibcon#enter wrdev, iclass 33, count 0 2006.173.16:48:15.11#ibcon#first serial, iclass 33, count 0 2006.173.16:48:15.11#ibcon#enter sib2, iclass 33, count 0 2006.173.16:48:15.11#ibcon#flushed, iclass 33, count 0 2006.173.16:48:15.11#ibcon#about to write, iclass 33, count 0 2006.173.16:48:15.11#ibcon#wrote, iclass 33, count 0 2006.173.16:48:15.11#ibcon#about to read 3, iclass 33, count 0 2006.173.16:48:15.13#ibcon#read 3, iclass 33, count 0 2006.173.16:48:15.13#ibcon#about to read 4, iclass 33, count 0 2006.173.16:48:15.13#ibcon#read 4, iclass 33, count 0 2006.173.16:48:15.13#ibcon#about to read 5, iclass 33, count 0 2006.173.16:48:15.13#ibcon#read 5, iclass 33, count 0 2006.173.16:48:15.13#ibcon#about to read 6, iclass 33, count 0 2006.173.16:48:15.13#ibcon#read 6, iclass 33, count 0 2006.173.16:48:15.13#ibcon#end of sib2, iclass 33, count 0 2006.173.16:48:15.13#ibcon#*mode == 0, iclass 33, count 0 2006.173.16:48:15.13#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.16:48:15.13#ibcon#[27=USB\r\n] 2006.173.16:48:15.13#ibcon#*before write, iclass 33, count 0 2006.173.16:48:15.13#ibcon#enter sib2, iclass 33, count 0 2006.173.16:48:15.13#ibcon#flushed, iclass 33, count 0 2006.173.16:48:15.13#ibcon#about to write, iclass 33, count 0 2006.173.16:48:15.13#ibcon#wrote, iclass 33, count 0 2006.173.16:48:15.13#ibcon#about to read 3, iclass 33, count 0 2006.173.16:48:15.16#ibcon#read 3, iclass 33, count 0 2006.173.16:48:15.16#ibcon#about to read 4, iclass 33, count 0 2006.173.16:48:15.16#ibcon#read 4, iclass 33, count 0 2006.173.16:48:15.16#ibcon#about to read 5, iclass 33, count 0 2006.173.16:48:15.16#ibcon#read 5, iclass 33, count 0 2006.173.16:48:15.16#ibcon#about to read 6, iclass 33, count 0 2006.173.16:48:15.16#ibcon#read 6, iclass 33, count 0 2006.173.16:48:15.16#ibcon#end of sib2, iclass 33, count 0 2006.173.16:48:15.16#ibcon#*after write, iclass 33, count 0 2006.173.16:48:15.16#ibcon#*before return 0, iclass 33, count 0 2006.173.16:48:15.16#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.16:48:15.16#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.173.16:48:15.16#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.16:48:15.16#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.16:48:15.16$vck44/vblo=2,634.99 2006.173.16:48:15.16#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.16:48:15.16#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.16:48:15.16#ibcon#ireg 17 cls_cnt 0 2006.173.16:48:15.16#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.16:48:15.16#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.16:48:15.16#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.16:48:15.16#ibcon#enter wrdev, iclass 35, count 0 2006.173.16:48:15.16#ibcon#first serial, iclass 35, count 0 2006.173.16:48:15.16#ibcon#enter sib2, iclass 35, count 0 2006.173.16:48:15.16#ibcon#flushed, iclass 35, count 0 2006.173.16:48:15.16#ibcon#about to write, iclass 35, count 0 2006.173.16:48:15.16#ibcon#wrote, iclass 35, count 0 2006.173.16:48:15.16#ibcon#about to read 3, iclass 35, count 0 2006.173.16:48:15.18#ibcon#read 3, iclass 35, count 0 2006.173.16:48:15.18#ibcon#about to read 4, iclass 35, count 0 2006.173.16:48:15.18#ibcon#read 4, iclass 35, count 0 2006.173.16:48:15.18#ibcon#about to read 5, iclass 35, count 0 2006.173.16:48:15.18#ibcon#read 5, iclass 35, count 0 2006.173.16:48:15.18#ibcon#about to read 6, iclass 35, count 0 2006.173.16:48:15.18#ibcon#read 6, iclass 35, count 0 2006.173.16:48:15.18#ibcon#end of sib2, iclass 35, count 0 2006.173.16:48:15.18#ibcon#*mode == 0, iclass 35, count 0 2006.173.16:48:15.18#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.16:48:15.18#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.16:48:15.18#ibcon#*before write, iclass 35, count 0 2006.173.16:48:15.18#ibcon#enter sib2, iclass 35, count 0 2006.173.16:48:15.18#ibcon#flushed, iclass 35, count 0 2006.173.16:48:15.18#ibcon#about to write, iclass 35, count 0 2006.173.16:48:15.18#ibcon#wrote, iclass 35, count 0 2006.173.16:48:15.18#ibcon#about to read 3, iclass 35, count 0 2006.173.16:48:15.22#ibcon#read 3, iclass 35, count 0 2006.173.16:48:15.22#ibcon#about to read 4, iclass 35, count 0 2006.173.16:48:15.22#ibcon#read 4, iclass 35, count 0 2006.173.16:48:15.22#ibcon#about to read 5, iclass 35, count 0 2006.173.16:48:15.22#ibcon#read 5, iclass 35, count 0 2006.173.16:48:15.22#ibcon#about to read 6, iclass 35, count 0 2006.173.16:48:15.22#ibcon#read 6, iclass 35, count 0 2006.173.16:48:15.22#ibcon#end of sib2, iclass 35, count 0 2006.173.16:48:15.22#ibcon#*after write, iclass 35, count 0 2006.173.16:48:15.22#ibcon#*before return 0, iclass 35, count 0 2006.173.16:48:15.22#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.16:48:15.22#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.16:48:15.22#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.16:48:15.22#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.16:48:15.22$vck44/vb=2,4 2006.173.16:48:15.22#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.173.16:48:15.22#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.173.16:48:15.22#ibcon#ireg 11 cls_cnt 2 2006.173.16:48:15.22#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.16:48:15.28#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.16:48:15.28#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.16:48:15.28#ibcon#enter wrdev, iclass 37, count 2 2006.173.16:48:15.28#ibcon#first serial, iclass 37, count 2 2006.173.16:48:15.28#ibcon#enter sib2, iclass 37, count 2 2006.173.16:48:15.28#ibcon#flushed, iclass 37, count 2 2006.173.16:48:15.28#ibcon#about to write, iclass 37, count 2 2006.173.16:48:15.28#ibcon#wrote, iclass 37, count 2 2006.173.16:48:15.28#ibcon#about to read 3, iclass 37, count 2 2006.173.16:48:15.30#ibcon#read 3, iclass 37, count 2 2006.173.16:48:15.30#ibcon#about to read 4, iclass 37, count 2 2006.173.16:48:15.30#ibcon#read 4, iclass 37, count 2 2006.173.16:48:15.30#ibcon#about to read 5, iclass 37, count 2 2006.173.16:48:15.30#ibcon#read 5, iclass 37, count 2 2006.173.16:48:15.30#ibcon#about to read 6, iclass 37, count 2 2006.173.16:48:15.30#ibcon#read 6, iclass 37, count 2 2006.173.16:48:15.30#ibcon#end of sib2, iclass 37, count 2 2006.173.16:48:15.30#ibcon#*mode == 0, iclass 37, count 2 2006.173.16:48:15.30#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.173.16:48:15.30#ibcon#[27=AT02-04\r\n] 2006.173.16:48:15.30#ibcon#*before write, iclass 37, count 2 2006.173.16:48:15.30#ibcon#enter sib2, iclass 37, count 2 2006.173.16:48:15.30#ibcon#flushed, iclass 37, count 2 2006.173.16:48:15.30#ibcon#about to write, iclass 37, count 2 2006.173.16:48:15.30#ibcon#wrote, iclass 37, count 2 2006.173.16:48:15.30#ibcon#about to read 3, iclass 37, count 2 2006.173.16:48:15.33#ibcon#read 3, iclass 37, count 2 2006.173.16:48:15.33#ibcon#about to read 4, iclass 37, count 2 2006.173.16:48:15.33#ibcon#read 4, iclass 37, count 2 2006.173.16:48:15.33#ibcon#about to read 5, iclass 37, count 2 2006.173.16:48:15.33#ibcon#read 5, iclass 37, count 2 2006.173.16:48:15.33#ibcon#about to read 6, iclass 37, count 2 2006.173.16:48:15.33#ibcon#read 6, iclass 37, count 2 2006.173.16:48:15.33#ibcon#end of sib2, iclass 37, count 2 2006.173.16:48:15.33#ibcon#*after write, iclass 37, count 2 2006.173.16:48:15.33#ibcon#*before return 0, iclass 37, count 2 2006.173.16:48:15.33#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.16:48:15.33#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.173.16:48:15.33#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.173.16:48:15.33#ibcon#ireg 7 cls_cnt 0 2006.173.16:48:15.33#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.16:48:15.45#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.16:48:15.45#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.16:48:15.45#ibcon#enter wrdev, iclass 37, count 0 2006.173.16:48:15.45#ibcon#first serial, iclass 37, count 0 2006.173.16:48:15.45#ibcon#enter sib2, iclass 37, count 0 2006.173.16:48:15.45#ibcon#flushed, iclass 37, count 0 2006.173.16:48:15.45#ibcon#about to write, iclass 37, count 0 2006.173.16:48:15.45#ibcon#wrote, iclass 37, count 0 2006.173.16:48:15.45#ibcon#about to read 3, iclass 37, count 0 2006.173.16:48:15.47#ibcon#read 3, iclass 37, count 0 2006.173.16:48:15.47#ibcon#about to read 4, iclass 37, count 0 2006.173.16:48:15.47#ibcon#read 4, iclass 37, count 0 2006.173.16:48:15.47#ibcon#about to read 5, iclass 37, count 0 2006.173.16:48:15.47#ibcon#read 5, iclass 37, count 0 2006.173.16:48:15.47#ibcon#about to read 6, iclass 37, count 0 2006.173.16:48:15.47#ibcon#read 6, iclass 37, count 0 2006.173.16:48:15.47#ibcon#end of sib2, iclass 37, count 0 2006.173.16:48:15.47#ibcon#*mode == 0, iclass 37, count 0 2006.173.16:48:15.47#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.16:48:15.47#ibcon#[27=USB\r\n] 2006.173.16:48:15.47#ibcon#*before write, iclass 37, count 0 2006.173.16:48:15.47#ibcon#enter sib2, iclass 37, count 0 2006.173.16:48:15.47#ibcon#flushed, iclass 37, count 0 2006.173.16:48:15.47#ibcon#about to write, iclass 37, count 0 2006.173.16:48:15.47#ibcon#wrote, iclass 37, count 0 2006.173.16:48:15.47#ibcon#about to read 3, iclass 37, count 0 2006.173.16:48:15.50#ibcon#read 3, iclass 37, count 0 2006.173.16:48:15.50#ibcon#about to read 4, iclass 37, count 0 2006.173.16:48:15.50#ibcon#read 4, iclass 37, count 0 2006.173.16:48:15.50#ibcon#about to read 5, iclass 37, count 0 2006.173.16:48:15.50#ibcon#read 5, iclass 37, count 0 2006.173.16:48:15.50#ibcon#about to read 6, iclass 37, count 0 2006.173.16:48:15.50#ibcon#read 6, iclass 37, count 0 2006.173.16:48:15.50#ibcon#end of sib2, iclass 37, count 0 2006.173.16:48:15.50#ibcon#*after write, iclass 37, count 0 2006.173.16:48:15.50#ibcon#*before return 0, iclass 37, count 0 2006.173.16:48:15.50#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.16:48:15.50#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.173.16:48:15.50#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.16:48:15.50#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.16:48:15.50$vck44/vblo=3,649.99 2006.173.16:48:15.50#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.16:48:15.50#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.16:48:15.50#ibcon#ireg 17 cls_cnt 0 2006.173.16:48:15.50#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.16:48:15.50#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.16:48:15.50#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.16:48:15.50#ibcon#enter wrdev, iclass 39, count 0 2006.173.16:48:15.50#ibcon#first serial, iclass 39, count 0 2006.173.16:48:15.50#ibcon#enter sib2, iclass 39, count 0 2006.173.16:48:15.50#ibcon#flushed, iclass 39, count 0 2006.173.16:48:15.50#ibcon#about to write, iclass 39, count 0 2006.173.16:48:15.50#ibcon#wrote, iclass 39, count 0 2006.173.16:48:15.50#ibcon#about to read 3, iclass 39, count 0 2006.173.16:48:15.52#ibcon#read 3, iclass 39, count 0 2006.173.16:48:15.52#ibcon#about to read 4, iclass 39, count 0 2006.173.16:48:15.52#ibcon#read 4, iclass 39, count 0 2006.173.16:48:15.52#ibcon#about to read 5, iclass 39, count 0 2006.173.16:48:15.52#ibcon#read 5, iclass 39, count 0 2006.173.16:48:15.52#ibcon#about to read 6, iclass 39, count 0 2006.173.16:48:15.52#ibcon#read 6, iclass 39, count 0 2006.173.16:48:15.52#ibcon#end of sib2, iclass 39, count 0 2006.173.16:48:15.52#ibcon#*mode == 0, iclass 39, count 0 2006.173.16:48:15.52#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.16:48:15.52#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.16:48:15.52#ibcon#*before write, iclass 39, count 0 2006.173.16:48:15.52#ibcon#enter sib2, iclass 39, count 0 2006.173.16:48:15.52#ibcon#flushed, iclass 39, count 0 2006.173.16:48:15.52#ibcon#about to write, iclass 39, count 0 2006.173.16:48:15.52#ibcon#wrote, iclass 39, count 0 2006.173.16:48:15.52#ibcon#about to read 3, iclass 39, count 0 2006.173.16:48:15.56#ibcon#read 3, iclass 39, count 0 2006.173.16:48:15.56#ibcon#about to read 4, iclass 39, count 0 2006.173.16:48:15.56#ibcon#read 4, iclass 39, count 0 2006.173.16:48:15.56#ibcon#about to read 5, iclass 39, count 0 2006.173.16:48:15.56#ibcon#read 5, iclass 39, count 0 2006.173.16:48:15.56#ibcon#about to read 6, iclass 39, count 0 2006.173.16:48:15.56#ibcon#read 6, iclass 39, count 0 2006.173.16:48:15.56#ibcon#end of sib2, iclass 39, count 0 2006.173.16:48:15.56#ibcon#*after write, iclass 39, count 0 2006.173.16:48:15.56#ibcon#*before return 0, iclass 39, count 0 2006.173.16:48:15.56#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.16:48:15.56#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.16:48:15.56#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.16:48:15.56#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.16:48:15.56$vck44/vb=3,4 2006.173.16:48:15.56#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.16:48:15.56#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.16:48:15.56#ibcon#ireg 11 cls_cnt 2 2006.173.16:48:15.56#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.16:48:15.62#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.16:48:15.62#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.16:48:15.62#ibcon#enter wrdev, iclass 3, count 2 2006.173.16:48:15.62#ibcon#first serial, iclass 3, count 2 2006.173.16:48:15.62#ibcon#enter sib2, iclass 3, count 2 2006.173.16:48:15.62#ibcon#flushed, iclass 3, count 2 2006.173.16:48:15.62#ibcon#about to write, iclass 3, count 2 2006.173.16:48:15.62#ibcon#wrote, iclass 3, count 2 2006.173.16:48:15.62#ibcon#about to read 3, iclass 3, count 2 2006.173.16:48:15.64#ibcon#read 3, iclass 3, count 2 2006.173.16:48:15.64#ibcon#about to read 4, iclass 3, count 2 2006.173.16:48:15.64#ibcon#read 4, iclass 3, count 2 2006.173.16:48:15.64#ibcon#about to read 5, iclass 3, count 2 2006.173.16:48:15.64#ibcon#read 5, iclass 3, count 2 2006.173.16:48:15.64#ibcon#about to read 6, iclass 3, count 2 2006.173.16:48:15.64#ibcon#read 6, iclass 3, count 2 2006.173.16:48:15.64#ibcon#end of sib2, iclass 3, count 2 2006.173.16:48:15.64#ibcon#*mode == 0, iclass 3, count 2 2006.173.16:48:15.64#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.16:48:15.64#ibcon#[27=AT03-04\r\n] 2006.173.16:48:15.64#ibcon#*before write, iclass 3, count 2 2006.173.16:48:15.64#ibcon#enter sib2, iclass 3, count 2 2006.173.16:48:15.64#ibcon#flushed, iclass 3, count 2 2006.173.16:48:15.64#ibcon#about to write, iclass 3, count 2 2006.173.16:48:15.64#ibcon#wrote, iclass 3, count 2 2006.173.16:48:15.64#ibcon#about to read 3, iclass 3, count 2 2006.173.16:48:15.67#ibcon#read 3, iclass 3, count 2 2006.173.16:48:15.67#ibcon#about to read 4, iclass 3, count 2 2006.173.16:48:15.67#ibcon#read 4, iclass 3, count 2 2006.173.16:48:15.67#ibcon#about to read 5, iclass 3, count 2 2006.173.16:48:15.67#ibcon#read 5, iclass 3, count 2 2006.173.16:48:15.67#ibcon#about to read 6, iclass 3, count 2 2006.173.16:48:15.67#ibcon#read 6, iclass 3, count 2 2006.173.16:48:15.67#ibcon#end of sib2, iclass 3, count 2 2006.173.16:48:15.67#ibcon#*after write, iclass 3, count 2 2006.173.16:48:15.67#ibcon#*before return 0, iclass 3, count 2 2006.173.16:48:15.67#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.16:48:15.67#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.16:48:15.67#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.16:48:15.67#ibcon#ireg 7 cls_cnt 0 2006.173.16:48:15.67#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.16:48:15.79#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.16:48:15.79#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.16:48:15.79#ibcon#enter wrdev, iclass 3, count 0 2006.173.16:48:15.79#ibcon#first serial, iclass 3, count 0 2006.173.16:48:15.79#ibcon#enter sib2, iclass 3, count 0 2006.173.16:48:15.79#ibcon#flushed, iclass 3, count 0 2006.173.16:48:15.79#ibcon#about to write, iclass 3, count 0 2006.173.16:48:15.79#ibcon#wrote, iclass 3, count 0 2006.173.16:48:15.79#ibcon#about to read 3, iclass 3, count 0 2006.173.16:48:15.81#ibcon#read 3, iclass 3, count 0 2006.173.16:48:15.81#ibcon#about to read 4, iclass 3, count 0 2006.173.16:48:15.81#ibcon#read 4, iclass 3, count 0 2006.173.16:48:15.81#ibcon#about to read 5, iclass 3, count 0 2006.173.16:48:15.81#ibcon#read 5, iclass 3, count 0 2006.173.16:48:15.81#ibcon#about to read 6, iclass 3, count 0 2006.173.16:48:15.81#ibcon#read 6, iclass 3, count 0 2006.173.16:48:15.81#ibcon#end of sib2, iclass 3, count 0 2006.173.16:48:15.81#ibcon#*mode == 0, iclass 3, count 0 2006.173.16:48:15.81#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.16:48:15.81#ibcon#[27=USB\r\n] 2006.173.16:48:15.81#ibcon#*before write, iclass 3, count 0 2006.173.16:48:15.81#ibcon#enter sib2, iclass 3, count 0 2006.173.16:48:15.81#ibcon#flushed, iclass 3, count 0 2006.173.16:48:15.81#ibcon#about to write, iclass 3, count 0 2006.173.16:48:15.81#ibcon#wrote, iclass 3, count 0 2006.173.16:48:15.81#ibcon#about to read 3, iclass 3, count 0 2006.173.16:48:15.84#ibcon#read 3, iclass 3, count 0 2006.173.16:48:15.84#ibcon#about to read 4, iclass 3, count 0 2006.173.16:48:15.84#ibcon#read 4, iclass 3, count 0 2006.173.16:48:15.84#ibcon#about to read 5, iclass 3, count 0 2006.173.16:48:15.84#ibcon#read 5, iclass 3, count 0 2006.173.16:48:15.84#ibcon#about to read 6, iclass 3, count 0 2006.173.16:48:15.84#ibcon#read 6, iclass 3, count 0 2006.173.16:48:15.84#ibcon#end of sib2, iclass 3, count 0 2006.173.16:48:15.84#ibcon#*after write, iclass 3, count 0 2006.173.16:48:15.84#ibcon#*before return 0, iclass 3, count 0 2006.173.16:48:15.84#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.16:48:15.84#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.16:48:15.84#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.16:48:15.84#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.16:48:15.84$vck44/vblo=4,679.99 2006.173.16:48:15.84#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.16:48:15.84#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.16:48:15.84#ibcon#ireg 17 cls_cnt 0 2006.173.16:48:15.84#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.16:48:15.84#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.16:48:15.84#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.16:48:15.84#ibcon#enter wrdev, iclass 5, count 0 2006.173.16:48:15.84#ibcon#first serial, iclass 5, count 0 2006.173.16:48:15.84#ibcon#enter sib2, iclass 5, count 0 2006.173.16:48:15.84#ibcon#flushed, iclass 5, count 0 2006.173.16:48:15.84#ibcon#about to write, iclass 5, count 0 2006.173.16:48:15.84#ibcon#wrote, iclass 5, count 0 2006.173.16:48:15.84#ibcon#about to read 3, iclass 5, count 0 2006.173.16:48:15.86#ibcon#read 3, iclass 5, count 0 2006.173.16:48:15.86#ibcon#about to read 4, iclass 5, count 0 2006.173.16:48:15.86#ibcon#read 4, iclass 5, count 0 2006.173.16:48:15.86#ibcon#about to read 5, iclass 5, count 0 2006.173.16:48:15.86#ibcon#read 5, iclass 5, count 0 2006.173.16:48:15.86#ibcon#about to read 6, iclass 5, count 0 2006.173.16:48:15.86#ibcon#read 6, iclass 5, count 0 2006.173.16:48:15.86#ibcon#end of sib2, iclass 5, count 0 2006.173.16:48:15.86#ibcon#*mode == 0, iclass 5, count 0 2006.173.16:48:15.86#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.16:48:15.86#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.16:48:15.86#ibcon#*before write, iclass 5, count 0 2006.173.16:48:15.86#ibcon#enter sib2, iclass 5, count 0 2006.173.16:48:15.86#ibcon#flushed, iclass 5, count 0 2006.173.16:48:15.86#ibcon#about to write, iclass 5, count 0 2006.173.16:48:15.86#ibcon#wrote, iclass 5, count 0 2006.173.16:48:15.86#ibcon#about to read 3, iclass 5, count 0 2006.173.16:48:15.90#ibcon#read 3, iclass 5, count 0 2006.173.16:48:15.90#ibcon#about to read 4, iclass 5, count 0 2006.173.16:48:15.90#ibcon#read 4, iclass 5, count 0 2006.173.16:48:15.90#ibcon#about to read 5, iclass 5, count 0 2006.173.16:48:15.90#ibcon#read 5, iclass 5, count 0 2006.173.16:48:15.90#ibcon#about to read 6, iclass 5, count 0 2006.173.16:48:15.90#ibcon#read 6, iclass 5, count 0 2006.173.16:48:15.90#ibcon#end of sib2, iclass 5, count 0 2006.173.16:48:15.90#ibcon#*after write, iclass 5, count 0 2006.173.16:48:15.90#ibcon#*before return 0, iclass 5, count 0 2006.173.16:48:15.90#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.16:48:15.90#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.16:48:15.90#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.16:48:15.90#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.16:48:15.90$vck44/vb=4,4 2006.173.16:48:15.90#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.173.16:48:15.90#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.173.16:48:15.90#ibcon#ireg 11 cls_cnt 2 2006.173.16:48:15.90#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.16:48:15.96#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.16:48:15.96#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.16:48:15.96#ibcon#enter wrdev, iclass 7, count 2 2006.173.16:48:15.96#ibcon#first serial, iclass 7, count 2 2006.173.16:48:15.96#ibcon#enter sib2, iclass 7, count 2 2006.173.16:48:15.96#ibcon#flushed, iclass 7, count 2 2006.173.16:48:15.96#ibcon#about to write, iclass 7, count 2 2006.173.16:48:15.96#ibcon#wrote, iclass 7, count 2 2006.173.16:48:15.96#ibcon#about to read 3, iclass 7, count 2 2006.173.16:48:15.98#ibcon#read 3, iclass 7, count 2 2006.173.16:48:15.98#ibcon#about to read 4, iclass 7, count 2 2006.173.16:48:15.98#ibcon#read 4, iclass 7, count 2 2006.173.16:48:15.98#ibcon#about to read 5, iclass 7, count 2 2006.173.16:48:15.98#ibcon#read 5, iclass 7, count 2 2006.173.16:48:15.98#ibcon#about to read 6, iclass 7, count 2 2006.173.16:48:15.98#ibcon#read 6, iclass 7, count 2 2006.173.16:48:15.98#ibcon#end of sib2, iclass 7, count 2 2006.173.16:48:15.98#ibcon#*mode == 0, iclass 7, count 2 2006.173.16:48:15.98#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.173.16:48:15.98#ibcon#[27=AT04-04\r\n] 2006.173.16:48:15.98#ibcon#*before write, iclass 7, count 2 2006.173.16:48:15.98#ibcon#enter sib2, iclass 7, count 2 2006.173.16:48:15.98#ibcon#flushed, iclass 7, count 2 2006.173.16:48:15.98#ibcon#about to write, iclass 7, count 2 2006.173.16:48:15.98#ibcon#wrote, iclass 7, count 2 2006.173.16:48:15.98#ibcon#about to read 3, iclass 7, count 2 2006.173.16:48:16.01#ibcon#read 3, iclass 7, count 2 2006.173.16:48:16.01#ibcon#about to read 4, iclass 7, count 2 2006.173.16:48:16.01#ibcon#read 4, iclass 7, count 2 2006.173.16:48:16.01#ibcon#about to read 5, iclass 7, count 2 2006.173.16:48:16.01#ibcon#read 5, iclass 7, count 2 2006.173.16:48:16.01#ibcon#about to read 6, iclass 7, count 2 2006.173.16:48:16.01#ibcon#read 6, iclass 7, count 2 2006.173.16:48:16.01#ibcon#end of sib2, iclass 7, count 2 2006.173.16:48:16.01#ibcon#*after write, iclass 7, count 2 2006.173.16:48:16.01#ibcon#*before return 0, iclass 7, count 2 2006.173.16:48:16.01#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.16:48:16.01#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.173.16:48:16.01#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.173.16:48:16.01#ibcon#ireg 7 cls_cnt 0 2006.173.16:48:16.01#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.16:48:16.13#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.16:48:16.13#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.16:48:16.13#ibcon#enter wrdev, iclass 7, count 0 2006.173.16:48:16.13#ibcon#first serial, iclass 7, count 0 2006.173.16:48:16.13#ibcon#enter sib2, iclass 7, count 0 2006.173.16:48:16.13#ibcon#flushed, iclass 7, count 0 2006.173.16:48:16.13#ibcon#about to write, iclass 7, count 0 2006.173.16:48:16.13#ibcon#wrote, iclass 7, count 0 2006.173.16:48:16.13#ibcon#about to read 3, iclass 7, count 0 2006.173.16:48:16.15#ibcon#read 3, iclass 7, count 0 2006.173.16:48:16.15#ibcon#about to read 4, iclass 7, count 0 2006.173.16:48:16.15#ibcon#read 4, iclass 7, count 0 2006.173.16:48:16.15#ibcon#about to read 5, iclass 7, count 0 2006.173.16:48:16.15#ibcon#read 5, iclass 7, count 0 2006.173.16:48:16.15#ibcon#about to read 6, iclass 7, count 0 2006.173.16:48:16.15#ibcon#read 6, iclass 7, count 0 2006.173.16:48:16.15#ibcon#end of sib2, iclass 7, count 0 2006.173.16:48:16.15#ibcon#*mode == 0, iclass 7, count 0 2006.173.16:48:16.15#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.16:48:16.15#ibcon#[27=USB\r\n] 2006.173.16:48:16.15#ibcon#*before write, iclass 7, count 0 2006.173.16:48:16.15#ibcon#enter sib2, iclass 7, count 0 2006.173.16:48:16.15#ibcon#flushed, iclass 7, count 0 2006.173.16:48:16.15#ibcon#about to write, iclass 7, count 0 2006.173.16:48:16.15#ibcon#wrote, iclass 7, count 0 2006.173.16:48:16.15#ibcon#about to read 3, iclass 7, count 0 2006.173.16:48:16.18#ibcon#read 3, iclass 7, count 0 2006.173.16:48:16.18#ibcon#about to read 4, iclass 7, count 0 2006.173.16:48:16.18#ibcon#read 4, iclass 7, count 0 2006.173.16:48:16.18#ibcon#about to read 5, iclass 7, count 0 2006.173.16:48:16.18#ibcon#read 5, iclass 7, count 0 2006.173.16:48:16.18#ibcon#about to read 6, iclass 7, count 0 2006.173.16:48:16.18#ibcon#read 6, iclass 7, count 0 2006.173.16:48:16.18#ibcon#end of sib2, iclass 7, count 0 2006.173.16:48:16.18#ibcon#*after write, iclass 7, count 0 2006.173.16:48:16.18#ibcon#*before return 0, iclass 7, count 0 2006.173.16:48:16.18#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.16:48:16.18#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.173.16:48:16.18#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.16:48:16.18#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.16:48:16.18$vck44/vblo=5,709.99 2006.173.16:48:16.18#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.16:48:16.18#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.16:48:16.18#ibcon#ireg 17 cls_cnt 0 2006.173.16:48:16.18#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.16:48:16.18#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.16:48:16.18#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.16:48:16.18#ibcon#enter wrdev, iclass 11, count 0 2006.173.16:48:16.18#ibcon#first serial, iclass 11, count 0 2006.173.16:48:16.18#ibcon#enter sib2, iclass 11, count 0 2006.173.16:48:16.18#ibcon#flushed, iclass 11, count 0 2006.173.16:48:16.18#ibcon#about to write, iclass 11, count 0 2006.173.16:48:16.18#ibcon#wrote, iclass 11, count 0 2006.173.16:48:16.18#ibcon#about to read 3, iclass 11, count 0 2006.173.16:48:16.20#ibcon#read 3, iclass 11, count 0 2006.173.16:48:16.20#ibcon#about to read 4, iclass 11, count 0 2006.173.16:48:16.20#ibcon#read 4, iclass 11, count 0 2006.173.16:48:16.20#ibcon#about to read 5, iclass 11, count 0 2006.173.16:48:16.20#ibcon#read 5, iclass 11, count 0 2006.173.16:48:16.20#ibcon#about to read 6, iclass 11, count 0 2006.173.16:48:16.20#ibcon#read 6, iclass 11, count 0 2006.173.16:48:16.20#ibcon#end of sib2, iclass 11, count 0 2006.173.16:48:16.20#ibcon#*mode == 0, iclass 11, count 0 2006.173.16:48:16.20#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.16:48:16.20#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.16:48:16.20#ibcon#*before write, iclass 11, count 0 2006.173.16:48:16.20#ibcon#enter sib2, iclass 11, count 0 2006.173.16:48:16.20#ibcon#flushed, iclass 11, count 0 2006.173.16:48:16.20#ibcon#about to write, iclass 11, count 0 2006.173.16:48:16.20#ibcon#wrote, iclass 11, count 0 2006.173.16:48:16.20#ibcon#about to read 3, iclass 11, count 0 2006.173.16:48:16.24#ibcon#read 3, iclass 11, count 0 2006.173.16:48:16.24#ibcon#about to read 4, iclass 11, count 0 2006.173.16:48:16.24#ibcon#read 4, iclass 11, count 0 2006.173.16:48:16.24#ibcon#about to read 5, iclass 11, count 0 2006.173.16:48:16.24#ibcon#read 5, iclass 11, count 0 2006.173.16:48:16.24#ibcon#about to read 6, iclass 11, count 0 2006.173.16:48:16.24#ibcon#read 6, iclass 11, count 0 2006.173.16:48:16.24#ibcon#end of sib2, iclass 11, count 0 2006.173.16:48:16.24#ibcon#*after write, iclass 11, count 0 2006.173.16:48:16.24#ibcon#*before return 0, iclass 11, count 0 2006.173.16:48:16.24#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.16:48:16.24#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.16:48:16.24#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.16:48:16.24#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.16:48:16.24$vck44/vb=5,4 2006.173.16:48:16.24#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.173.16:48:16.24#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.173.16:48:16.24#ibcon#ireg 11 cls_cnt 2 2006.173.16:48:16.24#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.16:48:16.30#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.16:48:16.30#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.16:48:16.30#ibcon#enter wrdev, iclass 13, count 2 2006.173.16:48:16.30#ibcon#first serial, iclass 13, count 2 2006.173.16:48:16.30#ibcon#enter sib2, iclass 13, count 2 2006.173.16:48:16.30#ibcon#flushed, iclass 13, count 2 2006.173.16:48:16.30#ibcon#about to write, iclass 13, count 2 2006.173.16:48:16.30#ibcon#wrote, iclass 13, count 2 2006.173.16:48:16.30#ibcon#about to read 3, iclass 13, count 2 2006.173.16:48:16.32#ibcon#read 3, iclass 13, count 2 2006.173.16:48:16.32#ibcon#about to read 4, iclass 13, count 2 2006.173.16:48:16.32#ibcon#read 4, iclass 13, count 2 2006.173.16:48:16.32#ibcon#about to read 5, iclass 13, count 2 2006.173.16:48:16.32#ibcon#read 5, iclass 13, count 2 2006.173.16:48:16.32#ibcon#about to read 6, iclass 13, count 2 2006.173.16:48:16.32#ibcon#read 6, iclass 13, count 2 2006.173.16:48:16.32#ibcon#end of sib2, iclass 13, count 2 2006.173.16:48:16.32#ibcon#*mode == 0, iclass 13, count 2 2006.173.16:48:16.32#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.173.16:48:16.32#ibcon#[27=AT05-04\r\n] 2006.173.16:48:16.32#ibcon#*before write, iclass 13, count 2 2006.173.16:48:16.32#ibcon#enter sib2, iclass 13, count 2 2006.173.16:48:16.32#ibcon#flushed, iclass 13, count 2 2006.173.16:48:16.32#ibcon#about to write, iclass 13, count 2 2006.173.16:48:16.32#ibcon#wrote, iclass 13, count 2 2006.173.16:48:16.32#ibcon#about to read 3, iclass 13, count 2 2006.173.16:48:16.35#ibcon#read 3, iclass 13, count 2 2006.173.16:48:16.35#ibcon#about to read 4, iclass 13, count 2 2006.173.16:48:16.35#ibcon#read 4, iclass 13, count 2 2006.173.16:48:16.35#ibcon#about to read 5, iclass 13, count 2 2006.173.16:48:16.35#ibcon#read 5, iclass 13, count 2 2006.173.16:48:16.35#ibcon#about to read 6, iclass 13, count 2 2006.173.16:48:16.35#ibcon#read 6, iclass 13, count 2 2006.173.16:48:16.35#ibcon#end of sib2, iclass 13, count 2 2006.173.16:48:16.35#ibcon#*after write, iclass 13, count 2 2006.173.16:48:16.35#ibcon#*before return 0, iclass 13, count 2 2006.173.16:48:16.35#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.16:48:16.35#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.173.16:48:16.35#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.173.16:48:16.35#ibcon#ireg 7 cls_cnt 0 2006.173.16:48:16.35#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.16:48:16.47#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.16:48:16.47#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.16:48:16.47#ibcon#enter wrdev, iclass 13, count 0 2006.173.16:48:16.47#ibcon#first serial, iclass 13, count 0 2006.173.16:48:16.47#ibcon#enter sib2, iclass 13, count 0 2006.173.16:48:16.47#ibcon#flushed, iclass 13, count 0 2006.173.16:48:16.47#ibcon#about to write, iclass 13, count 0 2006.173.16:48:16.47#ibcon#wrote, iclass 13, count 0 2006.173.16:48:16.47#ibcon#about to read 3, iclass 13, count 0 2006.173.16:48:16.49#ibcon#read 3, iclass 13, count 0 2006.173.16:48:16.49#ibcon#about to read 4, iclass 13, count 0 2006.173.16:48:16.49#ibcon#read 4, iclass 13, count 0 2006.173.16:48:16.49#ibcon#about to read 5, iclass 13, count 0 2006.173.16:48:16.49#ibcon#read 5, iclass 13, count 0 2006.173.16:48:16.49#ibcon#about to read 6, iclass 13, count 0 2006.173.16:48:16.49#ibcon#read 6, iclass 13, count 0 2006.173.16:48:16.49#ibcon#end of sib2, iclass 13, count 0 2006.173.16:48:16.49#ibcon#*mode == 0, iclass 13, count 0 2006.173.16:48:16.49#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.16:48:16.49#ibcon#[27=USB\r\n] 2006.173.16:48:16.49#ibcon#*before write, iclass 13, count 0 2006.173.16:48:16.49#ibcon#enter sib2, iclass 13, count 0 2006.173.16:48:16.49#ibcon#flushed, iclass 13, count 0 2006.173.16:48:16.49#ibcon#about to write, iclass 13, count 0 2006.173.16:48:16.49#ibcon#wrote, iclass 13, count 0 2006.173.16:48:16.49#ibcon#about to read 3, iclass 13, count 0 2006.173.16:48:16.52#ibcon#read 3, iclass 13, count 0 2006.173.16:48:16.52#ibcon#about to read 4, iclass 13, count 0 2006.173.16:48:16.52#ibcon#read 4, iclass 13, count 0 2006.173.16:48:16.52#ibcon#about to read 5, iclass 13, count 0 2006.173.16:48:16.52#ibcon#read 5, iclass 13, count 0 2006.173.16:48:16.52#ibcon#about to read 6, iclass 13, count 0 2006.173.16:48:16.52#ibcon#read 6, iclass 13, count 0 2006.173.16:48:16.52#ibcon#end of sib2, iclass 13, count 0 2006.173.16:48:16.52#ibcon#*after write, iclass 13, count 0 2006.173.16:48:16.52#ibcon#*before return 0, iclass 13, count 0 2006.173.16:48:16.52#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.16:48:16.52#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.173.16:48:16.52#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.16:48:16.52#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.16:48:16.52$vck44/vblo=6,719.99 2006.173.16:48:16.52#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.16:48:16.52#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.16:48:16.52#ibcon#ireg 17 cls_cnt 0 2006.173.16:48:16.52#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.16:48:16.52#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.16:48:16.52#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.16:48:16.52#ibcon#enter wrdev, iclass 15, count 0 2006.173.16:48:16.52#ibcon#first serial, iclass 15, count 0 2006.173.16:48:16.52#ibcon#enter sib2, iclass 15, count 0 2006.173.16:48:16.52#ibcon#flushed, iclass 15, count 0 2006.173.16:48:16.52#ibcon#about to write, iclass 15, count 0 2006.173.16:48:16.52#ibcon#wrote, iclass 15, count 0 2006.173.16:48:16.52#ibcon#about to read 3, iclass 15, count 0 2006.173.16:48:16.54#ibcon#read 3, iclass 15, count 0 2006.173.16:48:16.54#ibcon#about to read 4, iclass 15, count 0 2006.173.16:48:16.54#ibcon#read 4, iclass 15, count 0 2006.173.16:48:16.54#ibcon#about to read 5, iclass 15, count 0 2006.173.16:48:16.54#ibcon#read 5, iclass 15, count 0 2006.173.16:48:16.54#ibcon#about to read 6, iclass 15, count 0 2006.173.16:48:16.54#ibcon#read 6, iclass 15, count 0 2006.173.16:48:16.54#ibcon#end of sib2, iclass 15, count 0 2006.173.16:48:16.54#ibcon#*mode == 0, iclass 15, count 0 2006.173.16:48:16.54#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.16:48:16.54#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.16:48:16.54#ibcon#*before write, iclass 15, count 0 2006.173.16:48:16.54#ibcon#enter sib2, iclass 15, count 0 2006.173.16:48:16.54#ibcon#flushed, iclass 15, count 0 2006.173.16:48:16.54#ibcon#about to write, iclass 15, count 0 2006.173.16:48:16.54#ibcon#wrote, iclass 15, count 0 2006.173.16:48:16.54#ibcon#about to read 3, iclass 15, count 0 2006.173.16:48:16.58#ibcon#read 3, iclass 15, count 0 2006.173.16:48:16.58#ibcon#about to read 4, iclass 15, count 0 2006.173.16:48:16.58#ibcon#read 4, iclass 15, count 0 2006.173.16:48:16.58#ibcon#about to read 5, iclass 15, count 0 2006.173.16:48:16.58#ibcon#read 5, iclass 15, count 0 2006.173.16:48:16.58#ibcon#about to read 6, iclass 15, count 0 2006.173.16:48:16.58#ibcon#read 6, iclass 15, count 0 2006.173.16:48:16.58#ibcon#end of sib2, iclass 15, count 0 2006.173.16:48:16.58#ibcon#*after write, iclass 15, count 0 2006.173.16:48:16.58#ibcon#*before return 0, iclass 15, count 0 2006.173.16:48:16.58#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.16:48:16.58#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.16:48:16.58#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.16:48:16.58#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.16:48:16.58$vck44/vb=6,4 2006.173.16:48:16.58#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.16:48:16.58#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.16:48:16.58#ibcon#ireg 11 cls_cnt 2 2006.173.16:48:16.58#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.16:48:16.64#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.16:48:16.64#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.16:48:16.64#ibcon#enter wrdev, iclass 17, count 2 2006.173.16:48:16.64#ibcon#first serial, iclass 17, count 2 2006.173.16:48:16.64#ibcon#enter sib2, iclass 17, count 2 2006.173.16:48:16.64#ibcon#flushed, iclass 17, count 2 2006.173.16:48:16.64#ibcon#about to write, iclass 17, count 2 2006.173.16:48:16.64#ibcon#wrote, iclass 17, count 2 2006.173.16:48:16.64#ibcon#about to read 3, iclass 17, count 2 2006.173.16:48:16.66#ibcon#read 3, iclass 17, count 2 2006.173.16:48:16.66#ibcon#about to read 4, iclass 17, count 2 2006.173.16:48:16.66#ibcon#read 4, iclass 17, count 2 2006.173.16:48:16.66#ibcon#about to read 5, iclass 17, count 2 2006.173.16:48:16.66#ibcon#read 5, iclass 17, count 2 2006.173.16:48:16.66#ibcon#about to read 6, iclass 17, count 2 2006.173.16:48:16.66#ibcon#read 6, iclass 17, count 2 2006.173.16:48:16.66#ibcon#end of sib2, iclass 17, count 2 2006.173.16:48:16.66#ibcon#*mode == 0, iclass 17, count 2 2006.173.16:48:16.66#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.16:48:16.66#ibcon#[27=AT06-04\r\n] 2006.173.16:48:16.66#ibcon#*before write, iclass 17, count 2 2006.173.16:48:16.66#ibcon#enter sib2, iclass 17, count 2 2006.173.16:48:16.66#ibcon#flushed, iclass 17, count 2 2006.173.16:48:16.66#ibcon#about to write, iclass 17, count 2 2006.173.16:48:16.66#ibcon#wrote, iclass 17, count 2 2006.173.16:48:16.66#ibcon#about to read 3, iclass 17, count 2 2006.173.16:48:16.69#ibcon#read 3, iclass 17, count 2 2006.173.16:48:16.69#ibcon#about to read 4, iclass 17, count 2 2006.173.16:48:16.69#ibcon#read 4, iclass 17, count 2 2006.173.16:48:16.69#ibcon#about to read 5, iclass 17, count 2 2006.173.16:48:16.69#ibcon#read 5, iclass 17, count 2 2006.173.16:48:16.69#ibcon#about to read 6, iclass 17, count 2 2006.173.16:48:16.69#ibcon#read 6, iclass 17, count 2 2006.173.16:48:16.69#ibcon#end of sib2, iclass 17, count 2 2006.173.16:48:16.69#ibcon#*after write, iclass 17, count 2 2006.173.16:48:16.69#ibcon#*before return 0, iclass 17, count 2 2006.173.16:48:16.69#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.16:48:16.69#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.16:48:16.69#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.16:48:16.69#ibcon#ireg 7 cls_cnt 0 2006.173.16:48:16.69#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.16:48:16.81#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.16:48:16.81#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.16:48:16.81#ibcon#enter wrdev, iclass 17, count 0 2006.173.16:48:16.81#ibcon#first serial, iclass 17, count 0 2006.173.16:48:16.81#ibcon#enter sib2, iclass 17, count 0 2006.173.16:48:16.81#ibcon#flushed, iclass 17, count 0 2006.173.16:48:16.81#ibcon#about to write, iclass 17, count 0 2006.173.16:48:16.81#ibcon#wrote, iclass 17, count 0 2006.173.16:48:16.81#ibcon#about to read 3, iclass 17, count 0 2006.173.16:48:16.83#ibcon#read 3, iclass 17, count 0 2006.173.16:48:16.83#ibcon#about to read 4, iclass 17, count 0 2006.173.16:48:16.83#ibcon#read 4, iclass 17, count 0 2006.173.16:48:16.83#ibcon#about to read 5, iclass 17, count 0 2006.173.16:48:16.83#ibcon#read 5, iclass 17, count 0 2006.173.16:48:16.83#ibcon#about to read 6, iclass 17, count 0 2006.173.16:48:16.83#ibcon#read 6, iclass 17, count 0 2006.173.16:48:16.83#ibcon#end of sib2, iclass 17, count 0 2006.173.16:48:16.83#ibcon#*mode == 0, iclass 17, count 0 2006.173.16:48:16.83#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.16:48:16.83#ibcon#[27=USB\r\n] 2006.173.16:48:16.83#ibcon#*before write, iclass 17, count 0 2006.173.16:48:16.83#ibcon#enter sib2, iclass 17, count 0 2006.173.16:48:16.83#ibcon#flushed, iclass 17, count 0 2006.173.16:48:16.83#ibcon#about to write, iclass 17, count 0 2006.173.16:48:16.83#ibcon#wrote, iclass 17, count 0 2006.173.16:48:16.83#ibcon#about to read 3, iclass 17, count 0 2006.173.16:48:16.86#ibcon#read 3, iclass 17, count 0 2006.173.16:48:16.86#ibcon#about to read 4, iclass 17, count 0 2006.173.16:48:16.86#ibcon#read 4, iclass 17, count 0 2006.173.16:48:16.86#ibcon#about to read 5, iclass 17, count 0 2006.173.16:48:16.86#ibcon#read 5, iclass 17, count 0 2006.173.16:48:16.86#ibcon#about to read 6, iclass 17, count 0 2006.173.16:48:16.86#ibcon#read 6, iclass 17, count 0 2006.173.16:48:16.86#ibcon#end of sib2, iclass 17, count 0 2006.173.16:48:16.86#ibcon#*after write, iclass 17, count 0 2006.173.16:48:16.86#ibcon#*before return 0, iclass 17, count 0 2006.173.16:48:16.86#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.16:48:16.86#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.16:48:16.86#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.16:48:16.86#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.16:48:16.86$vck44/vblo=7,734.99 2006.173.16:48:16.86#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.16:48:16.86#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.16:48:16.86#ibcon#ireg 17 cls_cnt 0 2006.173.16:48:16.86#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.16:48:16.86#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.16:48:16.86#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.16:48:16.86#ibcon#enter wrdev, iclass 19, count 0 2006.173.16:48:16.86#ibcon#first serial, iclass 19, count 0 2006.173.16:48:16.86#ibcon#enter sib2, iclass 19, count 0 2006.173.16:48:16.86#ibcon#flushed, iclass 19, count 0 2006.173.16:48:16.86#ibcon#about to write, iclass 19, count 0 2006.173.16:48:16.86#ibcon#wrote, iclass 19, count 0 2006.173.16:48:16.86#ibcon#about to read 3, iclass 19, count 0 2006.173.16:48:16.88#ibcon#read 3, iclass 19, count 0 2006.173.16:48:16.88#ibcon#about to read 4, iclass 19, count 0 2006.173.16:48:16.88#ibcon#read 4, iclass 19, count 0 2006.173.16:48:16.88#ibcon#about to read 5, iclass 19, count 0 2006.173.16:48:16.88#ibcon#read 5, iclass 19, count 0 2006.173.16:48:16.88#ibcon#about to read 6, iclass 19, count 0 2006.173.16:48:16.88#ibcon#read 6, iclass 19, count 0 2006.173.16:48:16.88#ibcon#end of sib2, iclass 19, count 0 2006.173.16:48:16.88#ibcon#*mode == 0, iclass 19, count 0 2006.173.16:48:16.88#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.16:48:16.88#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.16:48:16.88#ibcon#*before write, iclass 19, count 0 2006.173.16:48:16.88#ibcon#enter sib2, iclass 19, count 0 2006.173.16:48:16.88#ibcon#flushed, iclass 19, count 0 2006.173.16:48:16.88#ibcon#about to write, iclass 19, count 0 2006.173.16:48:16.88#ibcon#wrote, iclass 19, count 0 2006.173.16:48:16.88#ibcon#about to read 3, iclass 19, count 0 2006.173.16:48:16.92#ibcon#read 3, iclass 19, count 0 2006.173.16:48:16.92#ibcon#about to read 4, iclass 19, count 0 2006.173.16:48:16.92#ibcon#read 4, iclass 19, count 0 2006.173.16:48:16.92#ibcon#about to read 5, iclass 19, count 0 2006.173.16:48:16.92#ibcon#read 5, iclass 19, count 0 2006.173.16:48:16.92#ibcon#about to read 6, iclass 19, count 0 2006.173.16:48:16.92#ibcon#read 6, iclass 19, count 0 2006.173.16:48:16.92#ibcon#end of sib2, iclass 19, count 0 2006.173.16:48:16.92#ibcon#*after write, iclass 19, count 0 2006.173.16:48:16.92#ibcon#*before return 0, iclass 19, count 0 2006.173.16:48:16.92#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.16:48:16.92#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.16:48:16.92#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.16:48:16.92#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.16:48:16.92$vck44/vb=7,4 2006.173.16:48:16.92#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.16:48:16.92#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.16:48:16.92#ibcon#ireg 11 cls_cnt 2 2006.173.16:48:16.92#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.16:48:16.98#abcon#<5=/13 0.5 1.6 20.431001002.6\r\n> 2006.173.16:48:16.98#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.16:48:16.98#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.16:48:16.98#ibcon#enter wrdev, iclass 21, count 2 2006.173.16:48:16.98#ibcon#first serial, iclass 21, count 2 2006.173.16:48:16.98#ibcon#enter sib2, iclass 21, count 2 2006.173.16:48:16.98#ibcon#flushed, iclass 21, count 2 2006.173.16:48:16.98#ibcon#about to write, iclass 21, count 2 2006.173.16:48:16.98#ibcon#wrote, iclass 21, count 2 2006.173.16:48:16.98#ibcon#about to read 3, iclass 21, count 2 2006.173.16:48:17.00#ibcon#read 3, iclass 21, count 2 2006.173.16:48:17.00#ibcon#about to read 4, iclass 21, count 2 2006.173.16:48:17.00#ibcon#read 4, iclass 21, count 2 2006.173.16:48:17.00#ibcon#about to read 5, iclass 21, count 2 2006.173.16:48:17.00#ibcon#read 5, iclass 21, count 2 2006.173.16:48:17.00#ibcon#about to read 6, iclass 21, count 2 2006.173.16:48:17.00#ibcon#read 6, iclass 21, count 2 2006.173.16:48:17.00#ibcon#end of sib2, iclass 21, count 2 2006.173.16:48:17.00#ibcon#*mode == 0, iclass 21, count 2 2006.173.16:48:17.00#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.16:48:17.00#ibcon#[27=AT07-04\r\n] 2006.173.16:48:17.00#ibcon#*before write, iclass 21, count 2 2006.173.16:48:17.00#ibcon#enter sib2, iclass 21, count 2 2006.173.16:48:17.00#ibcon#flushed, iclass 21, count 2 2006.173.16:48:17.00#ibcon#about to write, iclass 21, count 2 2006.173.16:48:17.00#ibcon#wrote, iclass 21, count 2 2006.173.16:48:17.00#ibcon#about to read 3, iclass 21, count 2 2006.173.16:48:17.00#abcon#{5=INTERFACE CLEAR} 2006.173.16:48:17.03#ibcon#read 3, iclass 21, count 2 2006.173.16:48:17.03#ibcon#about to read 4, iclass 21, count 2 2006.173.16:48:17.03#ibcon#read 4, iclass 21, count 2 2006.173.16:48:17.03#ibcon#about to read 5, iclass 21, count 2 2006.173.16:48:17.03#ibcon#read 5, iclass 21, count 2 2006.173.16:48:17.03#ibcon#about to read 6, iclass 21, count 2 2006.173.16:48:17.03#ibcon#read 6, iclass 21, count 2 2006.173.16:48:17.03#ibcon#end of sib2, iclass 21, count 2 2006.173.16:48:17.03#ibcon#*after write, iclass 21, count 2 2006.173.16:48:17.03#ibcon#*before return 0, iclass 21, count 2 2006.173.16:48:17.03#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.16:48:17.03#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.16:48:17.03#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.16:48:17.03#ibcon#ireg 7 cls_cnt 0 2006.173.16:48:17.03#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.16:48:17.06#abcon#[5=S1D000X0/0*\r\n] 2006.173.16:48:17.15#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.16:48:17.15#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.16:48:17.15#ibcon#enter wrdev, iclass 21, count 0 2006.173.16:48:17.15#ibcon#first serial, iclass 21, count 0 2006.173.16:48:17.15#ibcon#enter sib2, iclass 21, count 0 2006.173.16:48:17.15#ibcon#flushed, iclass 21, count 0 2006.173.16:48:17.15#ibcon#about to write, iclass 21, count 0 2006.173.16:48:17.15#ibcon#wrote, iclass 21, count 0 2006.173.16:48:17.15#ibcon#about to read 3, iclass 21, count 0 2006.173.16:48:17.17#ibcon#read 3, iclass 21, count 0 2006.173.16:48:17.17#ibcon#about to read 4, iclass 21, count 0 2006.173.16:48:17.17#ibcon#read 4, iclass 21, count 0 2006.173.16:48:17.17#ibcon#about to read 5, iclass 21, count 0 2006.173.16:48:17.17#ibcon#read 5, iclass 21, count 0 2006.173.16:48:17.17#ibcon#about to read 6, iclass 21, count 0 2006.173.16:48:17.17#ibcon#read 6, iclass 21, count 0 2006.173.16:48:17.17#ibcon#end of sib2, iclass 21, count 0 2006.173.16:48:17.17#ibcon#*mode == 0, iclass 21, count 0 2006.173.16:48:17.17#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.16:48:17.17#ibcon#[27=USB\r\n] 2006.173.16:48:17.17#ibcon#*before write, iclass 21, count 0 2006.173.16:48:17.17#ibcon#enter sib2, iclass 21, count 0 2006.173.16:48:17.17#ibcon#flushed, iclass 21, count 0 2006.173.16:48:17.17#ibcon#about to write, iclass 21, count 0 2006.173.16:48:17.17#ibcon#wrote, iclass 21, count 0 2006.173.16:48:17.17#ibcon#about to read 3, iclass 21, count 0 2006.173.16:48:17.20#ibcon#read 3, iclass 21, count 0 2006.173.16:48:17.20#ibcon#about to read 4, iclass 21, count 0 2006.173.16:48:17.20#ibcon#read 4, iclass 21, count 0 2006.173.16:48:17.20#ibcon#about to read 5, iclass 21, count 0 2006.173.16:48:17.20#ibcon#read 5, iclass 21, count 0 2006.173.16:48:17.20#ibcon#about to read 6, iclass 21, count 0 2006.173.16:48:17.20#ibcon#read 6, iclass 21, count 0 2006.173.16:48:17.20#ibcon#end of sib2, iclass 21, count 0 2006.173.16:48:17.20#ibcon#*after write, iclass 21, count 0 2006.173.16:48:17.20#ibcon#*before return 0, iclass 21, count 0 2006.173.16:48:17.20#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.16:48:17.20#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.16:48:17.20#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.16:48:17.20#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.16:48:17.20$vck44/vblo=8,744.99 2006.173.16:48:17.20#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.16:48:17.20#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.16:48:17.20#ibcon#ireg 17 cls_cnt 0 2006.173.16:48:17.20#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.16:48:17.20#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.16:48:17.20#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.16:48:17.20#ibcon#enter wrdev, iclass 27, count 0 2006.173.16:48:17.20#ibcon#first serial, iclass 27, count 0 2006.173.16:48:17.20#ibcon#enter sib2, iclass 27, count 0 2006.173.16:48:17.20#ibcon#flushed, iclass 27, count 0 2006.173.16:48:17.20#ibcon#about to write, iclass 27, count 0 2006.173.16:48:17.20#ibcon#wrote, iclass 27, count 0 2006.173.16:48:17.20#ibcon#about to read 3, iclass 27, count 0 2006.173.16:48:17.22#ibcon#read 3, iclass 27, count 0 2006.173.16:48:17.22#ibcon#about to read 4, iclass 27, count 0 2006.173.16:48:17.22#ibcon#read 4, iclass 27, count 0 2006.173.16:48:17.22#ibcon#about to read 5, iclass 27, count 0 2006.173.16:48:17.22#ibcon#read 5, iclass 27, count 0 2006.173.16:48:17.22#ibcon#about to read 6, iclass 27, count 0 2006.173.16:48:17.22#ibcon#read 6, iclass 27, count 0 2006.173.16:48:17.22#ibcon#end of sib2, iclass 27, count 0 2006.173.16:48:17.22#ibcon#*mode == 0, iclass 27, count 0 2006.173.16:48:17.22#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.16:48:17.22#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.16:48:17.22#ibcon#*before write, iclass 27, count 0 2006.173.16:48:17.22#ibcon#enter sib2, iclass 27, count 0 2006.173.16:48:17.22#ibcon#flushed, iclass 27, count 0 2006.173.16:48:17.22#ibcon#about to write, iclass 27, count 0 2006.173.16:48:17.22#ibcon#wrote, iclass 27, count 0 2006.173.16:48:17.22#ibcon#about to read 3, iclass 27, count 0 2006.173.16:48:17.26#ibcon#read 3, iclass 27, count 0 2006.173.16:48:17.26#ibcon#about to read 4, iclass 27, count 0 2006.173.16:48:17.26#ibcon#read 4, iclass 27, count 0 2006.173.16:48:17.26#ibcon#about to read 5, iclass 27, count 0 2006.173.16:48:17.26#ibcon#read 5, iclass 27, count 0 2006.173.16:48:17.26#ibcon#about to read 6, iclass 27, count 0 2006.173.16:48:17.26#ibcon#read 6, iclass 27, count 0 2006.173.16:48:17.26#ibcon#end of sib2, iclass 27, count 0 2006.173.16:48:17.26#ibcon#*after write, iclass 27, count 0 2006.173.16:48:17.26#ibcon#*before return 0, iclass 27, count 0 2006.173.16:48:17.26#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.16:48:17.26#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.16:48:17.26#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.16:48:17.26#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.16:48:17.26$vck44/vb=8,4 2006.173.16:48:17.26#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.16:48:17.26#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.16:48:17.26#ibcon#ireg 11 cls_cnt 2 2006.173.16:48:17.26#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.16:48:17.32#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.16:48:17.32#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.16:48:17.32#ibcon#enter wrdev, iclass 29, count 2 2006.173.16:48:17.32#ibcon#first serial, iclass 29, count 2 2006.173.16:48:17.32#ibcon#enter sib2, iclass 29, count 2 2006.173.16:48:17.32#ibcon#flushed, iclass 29, count 2 2006.173.16:48:17.32#ibcon#about to write, iclass 29, count 2 2006.173.16:48:17.32#ibcon#wrote, iclass 29, count 2 2006.173.16:48:17.32#ibcon#about to read 3, iclass 29, count 2 2006.173.16:48:17.34#ibcon#read 3, iclass 29, count 2 2006.173.16:48:17.34#ibcon#about to read 4, iclass 29, count 2 2006.173.16:48:17.34#ibcon#read 4, iclass 29, count 2 2006.173.16:48:17.34#ibcon#about to read 5, iclass 29, count 2 2006.173.16:48:17.34#ibcon#read 5, iclass 29, count 2 2006.173.16:48:17.34#ibcon#about to read 6, iclass 29, count 2 2006.173.16:48:17.34#ibcon#read 6, iclass 29, count 2 2006.173.16:48:17.34#ibcon#end of sib2, iclass 29, count 2 2006.173.16:48:17.34#ibcon#*mode == 0, iclass 29, count 2 2006.173.16:48:17.34#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.16:48:17.34#ibcon#[27=AT08-04\r\n] 2006.173.16:48:17.34#ibcon#*before write, iclass 29, count 2 2006.173.16:48:17.34#ibcon#enter sib2, iclass 29, count 2 2006.173.16:48:17.34#ibcon#flushed, iclass 29, count 2 2006.173.16:48:17.34#ibcon#about to write, iclass 29, count 2 2006.173.16:48:17.34#ibcon#wrote, iclass 29, count 2 2006.173.16:48:17.34#ibcon#about to read 3, iclass 29, count 2 2006.173.16:48:17.37#ibcon#read 3, iclass 29, count 2 2006.173.16:48:17.37#ibcon#about to read 4, iclass 29, count 2 2006.173.16:48:17.37#ibcon#read 4, iclass 29, count 2 2006.173.16:48:17.37#ibcon#about to read 5, iclass 29, count 2 2006.173.16:48:17.37#ibcon#read 5, iclass 29, count 2 2006.173.16:48:17.37#ibcon#about to read 6, iclass 29, count 2 2006.173.16:48:17.37#ibcon#read 6, iclass 29, count 2 2006.173.16:48:17.37#ibcon#end of sib2, iclass 29, count 2 2006.173.16:48:17.37#ibcon#*after write, iclass 29, count 2 2006.173.16:48:17.37#ibcon#*before return 0, iclass 29, count 2 2006.173.16:48:17.37#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.16:48:17.37#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.16:48:17.37#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.16:48:17.37#ibcon#ireg 7 cls_cnt 0 2006.173.16:48:17.37#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.16:48:17.49#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.16:48:17.49#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.16:48:17.49#ibcon#enter wrdev, iclass 29, count 0 2006.173.16:48:17.49#ibcon#first serial, iclass 29, count 0 2006.173.16:48:17.49#ibcon#enter sib2, iclass 29, count 0 2006.173.16:48:17.49#ibcon#flushed, iclass 29, count 0 2006.173.16:48:17.49#ibcon#about to write, iclass 29, count 0 2006.173.16:48:17.49#ibcon#wrote, iclass 29, count 0 2006.173.16:48:17.49#ibcon#about to read 3, iclass 29, count 0 2006.173.16:48:17.51#ibcon#read 3, iclass 29, count 0 2006.173.16:48:17.51#ibcon#about to read 4, iclass 29, count 0 2006.173.16:48:17.51#ibcon#read 4, iclass 29, count 0 2006.173.16:48:17.51#ibcon#about to read 5, iclass 29, count 0 2006.173.16:48:17.51#ibcon#read 5, iclass 29, count 0 2006.173.16:48:17.51#ibcon#about to read 6, iclass 29, count 0 2006.173.16:48:17.51#ibcon#read 6, iclass 29, count 0 2006.173.16:48:17.51#ibcon#end of sib2, iclass 29, count 0 2006.173.16:48:17.51#ibcon#*mode == 0, iclass 29, count 0 2006.173.16:48:17.51#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.16:48:17.51#ibcon#[27=USB\r\n] 2006.173.16:48:17.51#ibcon#*before write, iclass 29, count 0 2006.173.16:48:17.51#ibcon#enter sib2, iclass 29, count 0 2006.173.16:48:17.51#ibcon#flushed, iclass 29, count 0 2006.173.16:48:17.51#ibcon#about to write, iclass 29, count 0 2006.173.16:48:17.51#ibcon#wrote, iclass 29, count 0 2006.173.16:48:17.51#ibcon#about to read 3, iclass 29, count 0 2006.173.16:48:17.54#ibcon#read 3, iclass 29, count 0 2006.173.16:48:17.54#ibcon#about to read 4, iclass 29, count 0 2006.173.16:48:17.54#ibcon#read 4, iclass 29, count 0 2006.173.16:48:17.54#ibcon#about to read 5, iclass 29, count 0 2006.173.16:48:17.54#ibcon#read 5, iclass 29, count 0 2006.173.16:48:17.54#ibcon#about to read 6, iclass 29, count 0 2006.173.16:48:17.54#ibcon#read 6, iclass 29, count 0 2006.173.16:48:17.54#ibcon#end of sib2, iclass 29, count 0 2006.173.16:48:17.54#ibcon#*after write, iclass 29, count 0 2006.173.16:48:17.54#ibcon#*before return 0, iclass 29, count 0 2006.173.16:48:17.54#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.16:48:17.54#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.16:48:17.54#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.16:48:17.54#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.16:48:17.54$vck44/vabw=wide 2006.173.16:48:17.54#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.16:48:17.54#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.16:48:17.54#ibcon#ireg 8 cls_cnt 0 2006.173.16:48:17.54#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.16:48:17.54#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.16:48:17.54#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.16:48:17.54#ibcon#enter wrdev, iclass 31, count 0 2006.173.16:48:17.54#ibcon#first serial, iclass 31, count 0 2006.173.16:48:17.54#ibcon#enter sib2, iclass 31, count 0 2006.173.16:48:17.54#ibcon#flushed, iclass 31, count 0 2006.173.16:48:17.54#ibcon#about to write, iclass 31, count 0 2006.173.16:48:17.54#ibcon#wrote, iclass 31, count 0 2006.173.16:48:17.54#ibcon#about to read 3, iclass 31, count 0 2006.173.16:48:17.56#ibcon#read 3, iclass 31, count 0 2006.173.16:48:17.56#ibcon#about to read 4, iclass 31, count 0 2006.173.16:48:17.56#ibcon#read 4, iclass 31, count 0 2006.173.16:48:17.56#ibcon#about to read 5, iclass 31, count 0 2006.173.16:48:17.56#ibcon#read 5, iclass 31, count 0 2006.173.16:48:17.56#ibcon#about to read 6, iclass 31, count 0 2006.173.16:48:17.56#ibcon#read 6, iclass 31, count 0 2006.173.16:48:17.56#ibcon#end of sib2, iclass 31, count 0 2006.173.16:48:17.56#ibcon#*mode == 0, iclass 31, count 0 2006.173.16:48:17.56#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.16:48:17.56#ibcon#[25=BW32\r\n] 2006.173.16:48:17.56#ibcon#*before write, iclass 31, count 0 2006.173.16:48:17.56#ibcon#enter sib2, iclass 31, count 0 2006.173.16:48:17.56#ibcon#flushed, iclass 31, count 0 2006.173.16:48:17.56#ibcon#about to write, iclass 31, count 0 2006.173.16:48:17.56#ibcon#wrote, iclass 31, count 0 2006.173.16:48:17.56#ibcon#about to read 3, iclass 31, count 0 2006.173.16:48:17.59#ibcon#read 3, iclass 31, count 0 2006.173.16:48:17.59#ibcon#about to read 4, iclass 31, count 0 2006.173.16:48:17.59#ibcon#read 4, iclass 31, count 0 2006.173.16:48:17.59#ibcon#about to read 5, iclass 31, count 0 2006.173.16:48:17.59#ibcon#read 5, iclass 31, count 0 2006.173.16:48:17.59#ibcon#about to read 6, iclass 31, count 0 2006.173.16:48:17.59#ibcon#read 6, iclass 31, count 0 2006.173.16:48:17.59#ibcon#end of sib2, iclass 31, count 0 2006.173.16:48:17.59#ibcon#*after write, iclass 31, count 0 2006.173.16:48:17.59#ibcon#*before return 0, iclass 31, count 0 2006.173.16:48:17.59#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.16:48:17.59#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.16:48:17.59#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.16:48:17.59#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.16:48:17.59$vck44/vbbw=wide 2006.173.16:48:17.59#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.16:48:17.59#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.16:48:17.59#ibcon#ireg 8 cls_cnt 0 2006.173.16:48:17.59#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.16:48:17.66#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.16:48:17.66#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.16:48:17.66#ibcon#enter wrdev, iclass 33, count 0 2006.173.16:48:17.66#ibcon#first serial, iclass 33, count 0 2006.173.16:48:17.66#ibcon#enter sib2, iclass 33, count 0 2006.173.16:48:17.66#ibcon#flushed, iclass 33, count 0 2006.173.16:48:17.66#ibcon#about to write, iclass 33, count 0 2006.173.16:48:17.66#ibcon#wrote, iclass 33, count 0 2006.173.16:48:17.66#ibcon#about to read 3, iclass 33, count 0 2006.173.16:48:17.68#ibcon#read 3, iclass 33, count 0 2006.173.16:48:17.68#ibcon#about to read 4, iclass 33, count 0 2006.173.16:48:17.68#ibcon#read 4, iclass 33, count 0 2006.173.16:48:17.68#ibcon#about to read 5, iclass 33, count 0 2006.173.16:48:17.68#ibcon#read 5, iclass 33, count 0 2006.173.16:48:17.68#ibcon#about to read 6, iclass 33, count 0 2006.173.16:48:17.68#ibcon#read 6, iclass 33, count 0 2006.173.16:48:17.68#ibcon#end of sib2, iclass 33, count 0 2006.173.16:48:17.68#ibcon#*mode == 0, iclass 33, count 0 2006.173.16:48:17.68#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.16:48:17.68#ibcon#[27=BW32\r\n] 2006.173.16:48:17.68#ibcon#*before write, iclass 33, count 0 2006.173.16:48:17.68#ibcon#enter sib2, iclass 33, count 0 2006.173.16:48:17.68#ibcon#flushed, iclass 33, count 0 2006.173.16:48:17.68#ibcon#about to write, iclass 33, count 0 2006.173.16:48:17.68#ibcon#wrote, iclass 33, count 0 2006.173.16:48:17.68#ibcon#about to read 3, iclass 33, count 0 2006.173.16:48:17.71#ibcon#read 3, iclass 33, count 0 2006.173.16:48:17.71#ibcon#about to read 4, iclass 33, count 0 2006.173.16:48:17.71#ibcon#read 4, iclass 33, count 0 2006.173.16:48:17.71#ibcon#about to read 5, iclass 33, count 0 2006.173.16:48:17.71#ibcon#read 5, iclass 33, count 0 2006.173.16:48:17.71#ibcon#about to read 6, iclass 33, count 0 2006.173.16:48:17.71#ibcon#read 6, iclass 33, count 0 2006.173.16:48:17.71#ibcon#end of sib2, iclass 33, count 0 2006.173.16:48:17.71#ibcon#*after write, iclass 33, count 0 2006.173.16:48:17.71#ibcon#*before return 0, iclass 33, count 0 2006.173.16:48:17.71#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.16:48:17.71#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.16:48:17.71#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.16:48:17.71#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.16:48:17.71$setupk4/ifdk4 2006.173.16:48:17.71$ifdk4/lo= 2006.173.16:48:17.71$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.16:48:17.71$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.16:48:17.71$ifdk4/patch= 2006.173.16:48:17.71$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.16:48:17.71$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.16:48:17.71$setupk4/!*+20s 2006.173.16:48:27.15#abcon#<5=/13 0.5 1.6 20.431001002.6\r\n> 2006.173.16:48:27.17#abcon#{5=INTERFACE CLEAR} 2006.173.16:48:27.23#abcon#[5=S1D000X0/0*\r\n] 2006.173.16:48:32.22$setupk4/"tpicd 2006.173.16:48:32.22$setupk4/echo=off 2006.173.16:48:32.22$setupk4/xlog=off 2006.173.16:48:32.22:!2006.173.16:50:27 2006.173.16:48:44.14#trakl#Source acquired 2006.173.16:48:46.14#flagr#flagr/antenna,acquired 2006.173.16:50:27.00:preob 2006.173.16:50:27.13/onsource/TRACKING 2006.173.16:50:27.13:!2006.173.16:50:37 2006.173.16:50:37.00:"tape 2006.173.16:50:37.00:"st=record 2006.173.16:50:37.00:data_valid=on 2006.173.16:50:37.00:midob 2006.173.16:50:37.13/onsource/TRACKING 2006.173.16:50:37.13/wx/20.43,1002.8,100 2006.173.16:50:37.24/cable/+6.5136E-03 2006.173.16:50:38.33/va/01,07,usb,yes,36,38 2006.173.16:50:38.33/va/02,06,usb,yes,35,36 2006.173.16:50:38.33/va/03,05,usb,yes,45,47 2006.173.16:50:38.33/va/04,06,usb,yes,36,38 2006.173.16:50:38.33/va/05,04,usb,yes,28,29 2006.173.16:50:38.33/va/06,03,usb,yes,40,39 2006.173.16:50:38.33/va/07,04,usb,yes,32,33 2006.173.16:50:38.33/va/08,04,usb,yes,27,33 2006.173.16:50:38.56/valo/01,524.99,yes,locked 2006.173.16:50:38.56/valo/02,534.99,yes,locked 2006.173.16:50:38.56/valo/03,564.99,yes,locked 2006.173.16:50:38.56/valo/04,624.99,yes,locked 2006.173.16:50:38.56/valo/05,734.99,yes,locked 2006.173.16:50:38.56/valo/06,814.99,yes,locked 2006.173.16:50:38.56/valo/07,864.99,yes,locked 2006.173.16:50:38.56/valo/08,884.99,yes,locked 2006.173.16:50:39.65/vb/01,04,usb,yes,30,27 2006.173.16:50:39.65/vb/02,04,usb,yes,32,32 2006.173.16:50:39.65/vb/03,04,usb,yes,29,32 2006.173.16:50:39.65/vb/04,04,usb,yes,33,32 2006.173.16:50:39.65/vb/05,04,usb,yes,26,28 2006.173.16:50:39.65/vb/06,04,usb,yes,30,26 2006.173.16:50:39.65/vb/07,04,usb,yes,30,29 2006.173.16:50:39.65/vb/08,04,usb,yes,27,31 2006.173.16:50:39.88/vblo/01,629.99,yes,locked 2006.173.16:50:39.88/vblo/02,634.99,yes,locked 2006.173.16:50:39.88/vblo/03,649.99,yes,locked 2006.173.16:50:39.88/vblo/04,679.99,yes,locked 2006.173.16:50:39.88/vblo/05,709.99,yes,locked 2006.173.16:50:39.88/vblo/06,719.99,yes,locked 2006.173.16:50:39.88/vblo/07,734.99,yes,locked 2006.173.16:50:39.88/vblo/08,744.99,yes,locked 2006.173.16:50:40.03/vabw/8 2006.173.16:50:40.18/vbbw/8 2006.173.16:50:40.27/xfe/off,on,15.0 2006.173.16:50:40.66/ifatt/23,28,28,28 2006.173.16:50:41.07/fmout-gps/S +3.94E-07 2006.173.16:50:41.11:!2006.173.16:51:17 2006.173.16:51:17.01:data_valid=off 2006.173.16:51:17.01:"et 2006.173.16:51:17.01:!+3s 2006.173.16:51:20.02:"tape 2006.173.16:51:20.02:postob 2006.173.16:51:20.16/cable/+6.5131E-03 2006.173.16:51:20.16/wx/20.43,1002.8,100 2006.173.16:51:20.22/fmout-gps/S +3.94E-07 2006.173.16:51:20.22:scan_name=173-1652,jd0606,40 2006.173.16:51:20.22:source=2134+00,213638.59,004154.2,2000.0,ccw 2006.173.16:51:22.13#flagr#flagr/antenna,new-source 2006.173.16:51:22.13:checkk5 2006.173.16:51:22.53/chk_autoobs//k5ts1/ autoobs is running! 2006.173.16:51:22.91/chk_autoobs//k5ts2/ autoobs is running! 2006.173.16:51:23.31/chk_autoobs//k5ts3/ autoobs is running! 2006.173.16:51:23.70/chk_autoobs//k5ts4/ autoobs is running! 2006.173.16:51:24.08/chk_obsdata//k5ts1/T1731650??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.16:51:24.50/chk_obsdata//k5ts2/T1731650??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.16:51:24.89/chk_obsdata//k5ts3/T1731650??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.16:51:25.32/chk_obsdata//k5ts4/T1731650??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.16:51:26.03/k5log//k5ts1_log_newline 2006.173.16:51:26.73/k5log//k5ts2_log_newline 2006.173.16:51:27.43/k5log//k5ts3_log_newline 2006.173.16:51:28.14/k5log//k5ts4_log_newline 2006.173.16:51:28.16/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.16:51:28.16:setupk4=1 2006.173.16:51:28.16$setupk4/echo=on 2006.173.16:51:28.16$setupk4/pcalon 2006.173.16:51:28.16$pcalon/"no phase cal control is implemented here 2006.173.16:51:28.16$setupk4/"tpicd=stop 2006.173.16:51:28.16$setupk4/"rec=synch_on 2006.173.16:51:28.16$setupk4/"rec_mode=128 2006.173.16:51:28.16$setupk4/!* 2006.173.16:51:28.16$setupk4/recpk4 2006.173.16:51:28.16$recpk4/recpatch= 2006.173.16:51:28.17$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.16:51:28.17$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.16:51:28.17$setupk4/vck44 2006.173.16:51:28.17$vck44/valo=1,524.99 2006.173.16:51:28.17#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.16:51:28.17#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.16:51:28.17#ibcon#ireg 17 cls_cnt 0 2006.173.16:51:28.17#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.16:51:28.17#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.16:51:28.17#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.16:51:28.17#ibcon#enter wrdev, iclass 38, count 0 2006.173.16:51:28.17#ibcon#first serial, iclass 38, count 0 2006.173.16:51:28.17#ibcon#enter sib2, iclass 38, count 0 2006.173.16:51:28.17#ibcon#flushed, iclass 38, count 0 2006.173.16:51:28.17#ibcon#about to write, iclass 38, count 0 2006.173.16:51:28.17#ibcon#wrote, iclass 38, count 0 2006.173.16:51:28.17#ibcon#about to read 3, iclass 38, count 0 2006.173.16:51:28.19#ibcon#read 3, iclass 38, count 0 2006.173.16:51:28.19#ibcon#about to read 4, iclass 38, count 0 2006.173.16:51:28.19#ibcon#read 4, iclass 38, count 0 2006.173.16:51:28.19#ibcon#about to read 5, iclass 38, count 0 2006.173.16:51:28.19#ibcon#read 5, iclass 38, count 0 2006.173.16:51:28.19#ibcon#about to read 6, iclass 38, count 0 2006.173.16:51:28.19#ibcon#read 6, iclass 38, count 0 2006.173.16:51:28.19#ibcon#end of sib2, iclass 38, count 0 2006.173.16:51:28.19#ibcon#*mode == 0, iclass 38, count 0 2006.173.16:51:28.19#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.16:51:28.19#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.16:51:28.19#ibcon#*before write, iclass 38, count 0 2006.173.16:51:28.19#ibcon#enter sib2, iclass 38, count 0 2006.173.16:51:28.19#ibcon#flushed, iclass 38, count 0 2006.173.16:51:28.19#ibcon#about to write, iclass 38, count 0 2006.173.16:51:28.19#ibcon#wrote, iclass 38, count 0 2006.173.16:51:28.19#ibcon#about to read 3, iclass 38, count 0 2006.173.16:51:28.24#ibcon#read 3, iclass 38, count 0 2006.173.16:51:28.24#ibcon#about to read 4, iclass 38, count 0 2006.173.16:51:28.24#ibcon#read 4, iclass 38, count 0 2006.173.16:51:28.24#ibcon#about to read 5, iclass 38, count 0 2006.173.16:51:28.24#ibcon#read 5, iclass 38, count 0 2006.173.16:51:28.24#ibcon#about to read 6, iclass 38, count 0 2006.173.16:51:28.24#ibcon#read 6, iclass 38, count 0 2006.173.16:51:28.24#ibcon#end of sib2, iclass 38, count 0 2006.173.16:51:28.24#ibcon#*after write, iclass 38, count 0 2006.173.16:51:28.24#ibcon#*before return 0, iclass 38, count 0 2006.173.16:51:28.24#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.16:51:28.24#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.16:51:28.24#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.16:51:28.24#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.16:51:28.25$vck44/va=1,7 2006.173.16:51:28.25#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.16:51:28.25#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.16:51:28.25#ibcon#ireg 11 cls_cnt 2 2006.173.16:51:28.25#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.16:51:28.25#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.16:51:28.25#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.16:51:28.25#ibcon#enter wrdev, iclass 40, count 2 2006.173.16:51:28.25#ibcon#first serial, iclass 40, count 2 2006.173.16:51:28.25#ibcon#enter sib2, iclass 40, count 2 2006.173.16:51:28.25#ibcon#flushed, iclass 40, count 2 2006.173.16:51:28.25#ibcon#about to write, iclass 40, count 2 2006.173.16:51:28.25#ibcon#wrote, iclass 40, count 2 2006.173.16:51:28.25#ibcon#about to read 3, iclass 40, count 2 2006.173.16:51:28.27#ibcon#read 3, iclass 40, count 2 2006.173.16:51:28.27#ibcon#about to read 4, iclass 40, count 2 2006.173.16:51:28.27#ibcon#read 4, iclass 40, count 2 2006.173.16:51:28.27#ibcon#about to read 5, iclass 40, count 2 2006.173.16:51:28.27#ibcon#read 5, iclass 40, count 2 2006.173.16:51:28.27#ibcon#about to read 6, iclass 40, count 2 2006.173.16:51:28.27#ibcon#read 6, iclass 40, count 2 2006.173.16:51:28.27#ibcon#end of sib2, iclass 40, count 2 2006.173.16:51:28.27#ibcon#*mode == 0, iclass 40, count 2 2006.173.16:51:28.27#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.16:51:28.27#ibcon#[25=AT01-07\r\n] 2006.173.16:51:28.27#ibcon#*before write, iclass 40, count 2 2006.173.16:51:28.27#ibcon#enter sib2, iclass 40, count 2 2006.173.16:51:28.27#ibcon#flushed, iclass 40, count 2 2006.173.16:51:28.27#ibcon#about to write, iclass 40, count 2 2006.173.16:51:28.27#ibcon#wrote, iclass 40, count 2 2006.173.16:51:28.27#ibcon#about to read 3, iclass 40, count 2 2006.173.16:51:28.30#ibcon#read 3, iclass 40, count 2 2006.173.16:51:28.30#ibcon#about to read 4, iclass 40, count 2 2006.173.16:51:28.30#ibcon#read 4, iclass 40, count 2 2006.173.16:51:28.30#ibcon#about to read 5, iclass 40, count 2 2006.173.16:51:28.30#ibcon#read 5, iclass 40, count 2 2006.173.16:51:28.30#ibcon#about to read 6, iclass 40, count 2 2006.173.16:51:28.30#ibcon#read 6, iclass 40, count 2 2006.173.16:51:28.30#ibcon#end of sib2, iclass 40, count 2 2006.173.16:51:28.30#ibcon#*after write, iclass 40, count 2 2006.173.16:51:28.30#ibcon#*before return 0, iclass 40, count 2 2006.173.16:51:28.30#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.16:51:28.30#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.16:51:28.30#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.16:51:28.30#ibcon#ireg 7 cls_cnt 0 2006.173.16:51:28.30#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.16:51:28.42#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.16:51:28.42#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.16:51:28.42#ibcon#enter wrdev, iclass 40, count 0 2006.173.16:51:28.42#ibcon#first serial, iclass 40, count 0 2006.173.16:51:28.42#ibcon#enter sib2, iclass 40, count 0 2006.173.16:51:28.42#ibcon#flushed, iclass 40, count 0 2006.173.16:51:28.42#ibcon#about to write, iclass 40, count 0 2006.173.16:51:28.42#ibcon#wrote, iclass 40, count 0 2006.173.16:51:28.42#ibcon#about to read 3, iclass 40, count 0 2006.173.16:51:28.44#ibcon#read 3, iclass 40, count 0 2006.173.16:51:28.44#ibcon#about to read 4, iclass 40, count 0 2006.173.16:51:28.44#ibcon#read 4, iclass 40, count 0 2006.173.16:51:28.44#ibcon#about to read 5, iclass 40, count 0 2006.173.16:51:28.44#ibcon#read 5, iclass 40, count 0 2006.173.16:51:28.44#ibcon#about to read 6, iclass 40, count 0 2006.173.16:51:28.44#ibcon#read 6, iclass 40, count 0 2006.173.16:51:28.44#ibcon#end of sib2, iclass 40, count 0 2006.173.16:51:28.44#ibcon#*mode == 0, iclass 40, count 0 2006.173.16:51:28.44#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.16:51:28.44#ibcon#[25=USB\r\n] 2006.173.16:51:28.44#ibcon#*before write, iclass 40, count 0 2006.173.16:51:28.44#ibcon#enter sib2, iclass 40, count 0 2006.173.16:51:28.44#ibcon#flushed, iclass 40, count 0 2006.173.16:51:28.44#ibcon#about to write, iclass 40, count 0 2006.173.16:51:28.44#ibcon#wrote, iclass 40, count 0 2006.173.16:51:28.44#ibcon#about to read 3, iclass 40, count 0 2006.173.16:51:28.47#ibcon#read 3, iclass 40, count 0 2006.173.16:51:28.47#ibcon#about to read 4, iclass 40, count 0 2006.173.16:51:28.47#ibcon#read 4, iclass 40, count 0 2006.173.16:51:28.47#ibcon#about to read 5, iclass 40, count 0 2006.173.16:51:28.47#ibcon#read 5, iclass 40, count 0 2006.173.16:51:28.47#ibcon#about to read 6, iclass 40, count 0 2006.173.16:51:28.47#ibcon#read 6, iclass 40, count 0 2006.173.16:51:28.47#ibcon#end of sib2, iclass 40, count 0 2006.173.16:51:28.47#ibcon#*after write, iclass 40, count 0 2006.173.16:51:28.47#ibcon#*before return 0, iclass 40, count 0 2006.173.16:51:28.47#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.16:51:28.47#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.16:51:28.47#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.16:51:28.47#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.16:51:28.47$vck44/valo=2,534.99 2006.173.16:51:28.47#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.16:51:28.47#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.16:51:28.47#ibcon#ireg 17 cls_cnt 0 2006.173.16:51:28.47#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.16:51:28.47#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.16:51:28.47#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.16:51:28.47#ibcon#enter wrdev, iclass 4, count 0 2006.173.16:51:28.47#ibcon#first serial, iclass 4, count 0 2006.173.16:51:28.47#ibcon#enter sib2, iclass 4, count 0 2006.173.16:51:28.47#ibcon#flushed, iclass 4, count 0 2006.173.16:51:28.47#ibcon#about to write, iclass 4, count 0 2006.173.16:51:28.47#ibcon#wrote, iclass 4, count 0 2006.173.16:51:28.47#ibcon#about to read 3, iclass 4, count 0 2006.173.16:51:28.49#ibcon#read 3, iclass 4, count 0 2006.173.16:51:28.49#ibcon#about to read 4, iclass 4, count 0 2006.173.16:51:28.49#ibcon#read 4, iclass 4, count 0 2006.173.16:51:28.49#ibcon#about to read 5, iclass 4, count 0 2006.173.16:51:28.49#ibcon#read 5, iclass 4, count 0 2006.173.16:51:28.49#ibcon#about to read 6, iclass 4, count 0 2006.173.16:51:28.49#ibcon#read 6, iclass 4, count 0 2006.173.16:51:28.49#ibcon#end of sib2, iclass 4, count 0 2006.173.16:51:28.49#ibcon#*mode == 0, iclass 4, count 0 2006.173.16:51:28.49#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.16:51:28.49#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.16:51:28.49#ibcon#*before write, iclass 4, count 0 2006.173.16:51:28.49#ibcon#enter sib2, iclass 4, count 0 2006.173.16:51:28.49#ibcon#flushed, iclass 4, count 0 2006.173.16:51:28.49#ibcon#about to write, iclass 4, count 0 2006.173.16:51:28.49#ibcon#wrote, iclass 4, count 0 2006.173.16:51:28.49#ibcon#about to read 3, iclass 4, count 0 2006.173.16:51:28.53#ibcon#read 3, iclass 4, count 0 2006.173.16:51:28.53#ibcon#about to read 4, iclass 4, count 0 2006.173.16:51:28.53#ibcon#read 4, iclass 4, count 0 2006.173.16:51:28.53#ibcon#about to read 5, iclass 4, count 0 2006.173.16:51:28.53#ibcon#read 5, iclass 4, count 0 2006.173.16:51:28.53#ibcon#about to read 6, iclass 4, count 0 2006.173.16:51:28.53#ibcon#read 6, iclass 4, count 0 2006.173.16:51:28.53#ibcon#end of sib2, iclass 4, count 0 2006.173.16:51:28.53#ibcon#*after write, iclass 4, count 0 2006.173.16:51:28.53#ibcon#*before return 0, iclass 4, count 0 2006.173.16:51:28.53#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.16:51:28.53#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.16:51:28.53#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.16:51:28.53#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.16:51:28.53$vck44/va=2,6 2006.173.16:51:28.53#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.16:51:28.53#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.16:51:28.53#ibcon#ireg 11 cls_cnt 2 2006.173.16:51:28.53#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.16:51:28.59#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.16:51:28.59#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.16:51:28.59#ibcon#enter wrdev, iclass 6, count 2 2006.173.16:51:28.59#ibcon#first serial, iclass 6, count 2 2006.173.16:51:28.59#ibcon#enter sib2, iclass 6, count 2 2006.173.16:51:28.59#ibcon#flushed, iclass 6, count 2 2006.173.16:51:28.59#ibcon#about to write, iclass 6, count 2 2006.173.16:51:28.59#ibcon#wrote, iclass 6, count 2 2006.173.16:51:28.59#ibcon#about to read 3, iclass 6, count 2 2006.173.16:51:28.61#ibcon#read 3, iclass 6, count 2 2006.173.16:51:28.61#ibcon#about to read 4, iclass 6, count 2 2006.173.16:51:28.61#ibcon#read 4, iclass 6, count 2 2006.173.16:51:28.61#ibcon#about to read 5, iclass 6, count 2 2006.173.16:51:28.61#ibcon#read 5, iclass 6, count 2 2006.173.16:51:28.61#ibcon#about to read 6, iclass 6, count 2 2006.173.16:51:28.61#ibcon#read 6, iclass 6, count 2 2006.173.16:51:28.61#ibcon#end of sib2, iclass 6, count 2 2006.173.16:51:28.61#ibcon#*mode == 0, iclass 6, count 2 2006.173.16:51:28.61#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.16:51:28.61#ibcon#[25=AT02-06\r\n] 2006.173.16:51:28.61#ibcon#*before write, iclass 6, count 2 2006.173.16:51:28.61#ibcon#enter sib2, iclass 6, count 2 2006.173.16:51:28.61#ibcon#flushed, iclass 6, count 2 2006.173.16:51:28.61#ibcon#about to write, iclass 6, count 2 2006.173.16:51:28.61#ibcon#wrote, iclass 6, count 2 2006.173.16:51:28.61#ibcon#about to read 3, iclass 6, count 2 2006.173.16:51:28.64#ibcon#read 3, iclass 6, count 2 2006.173.16:51:28.64#ibcon#about to read 4, iclass 6, count 2 2006.173.16:51:28.64#ibcon#read 4, iclass 6, count 2 2006.173.16:51:28.64#ibcon#about to read 5, iclass 6, count 2 2006.173.16:51:28.64#ibcon#read 5, iclass 6, count 2 2006.173.16:51:28.64#ibcon#about to read 6, iclass 6, count 2 2006.173.16:51:28.64#ibcon#read 6, iclass 6, count 2 2006.173.16:51:28.64#ibcon#end of sib2, iclass 6, count 2 2006.173.16:51:28.64#ibcon#*after write, iclass 6, count 2 2006.173.16:51:28.64#ibcon#*before return 0, iclass 6, count 2 2006.173.16:51:28.64#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.16:51:28.64#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.16:51:28.64#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.16:51:28.64#ibcon#ireg 7 cls_cnt 0 2006.173.16:51:28.64#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.16:51:28.76#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.16:51:28.76#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.16:51:28.76#ibcon#enter wrdev, iclass 6, count 0 2006.173.16:51:28.76#ibcon#first serial, iclass 6, count 0 2006.173.16:51:28.76#ibcon#enter sib2, iclass 6, count 0 2006.173.16:51:28.76#ibcon#flushed, iclass 6, count 0 2006.173.16:51:28.76#ibcon#about to write, iclass 6, count 0 2006.173.16:51:28.76#ibcon#wrote, iclass 6, count 0 2006.173.16:51:28.76#ibcon#about to read 3, iclass 6, count 0 2006.173.16:51:28.78#ibcon#read 3, iclass 6, count 0 2006.173.16:51:28.78#ibcon#about to read 4, iclass 6, count 0 2006.173.16:51:28.78#ibcon#read 4, iclass 6, count 0 2006.173.16:51:28.78#ibcon#about to read 5, iclass 6, count 0 2006.173.16:51:28.78#ibcon#read 5, iclass 6, count 0 2006.173.16:51:28.78#ibcon#about to read 6, iclass 6, count 0 2006.173.16:51:28.78#ibcon#read 6, iclass 6, count 0 2006.173.16:51:28.78#ibcon#end of sib2, iclass 6, count 0 2006.173.16:51:28.78#ibcon#*mode == 0, iclass 6, count 0 2006.173.16:51:28.78#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.16:51:28.78#ibcon#[25=USB\r\n] 2006.173.16:51:28.78#ibcon#*before write, iclass 6, count 0 2006.173.16:51:28.78#ibcon#enter sib2, iclass 6, count 0 2006.173.16:51:28.78#ibcon#flushed, iclass 6, count 0 2006.173.16:51:28.78#ibcon#about to write, iclass 6, count 0 2006.173.16:51:28.78#ibcon#wrote, iclass 6, count 0 2006.173.16:51:28.78#ibcon#about to read 3, iclass 6, count 0 2006.173.16:51:28.81#ibcon#read 3, iclass 6, count 0 2006.173.16:51:28.81#ibcon#about to read 4, iclass 6, count 0 2006.173.16:51:28.81#ibcon#read 4, iclass 6, count 0 2006.173.16:51:28.81#ibcon#about to read 5, iclass 6, count 0 2006.173.16:51:28.81#ibcon#read 5, iclass 6, count 0 2006.173.16:51:28.81#ibcon#about to read 6, iclass 6, count 0 2006.173.16:51:28.81#ibcon#read 6, iclass 6, count 0 2006.173.16:51:28.81#ibcon#end of sib2, iclass 6, count 0 2006.173.16:51:28.81#ibcon#*after write, iclass 6, count 0 2006.173.16:51:28.81#ibcon#*before return 0, iclass 6, count 0 2006.173.16:51:28.81#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.16:51:28.81#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.16:51:28.81#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.16:51:28.81#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.16:51:28.81$vck44/valo=3,564.99 2006.173.16:51:28.81#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.16:51:28.81#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.16:51:28.81#ibcon#ireg 17 cls_cnt 0 2006.173.16:51:28.81#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.16:51:28.81#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.16:51:28.81#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.16:51:28.81#ibcon#enter wrdev, iclass 10, count 0 2006.173.16:51:28.81#ibcon#first serial, iclass 10, count 0 2006.173.16:51:28.81#ibcon#enter sib2, iclass 10, count 0 2006.173.16:51:28.81#ibcon#flushed, iclass 10, count 0 2006.173.16:51:28.81#ibcon#about to write, iclass 10, count 0 2006.173.16:51:28.81#ibcon#wrote, iclass 10, count 0 2006.173.16:51:28.81#ibcon#about to read 3, iclass 10, count 0 2006.173.16:51:28.83#ibcon#read 3, iclass 10, count 0 2006.173.16:51:28.83#ibcon#about to read 4, iclass 10, count 0 2006.173.16:51:28.83#ibcon#read 4, iclass 10, count 0 2006.173.16:51:28.83#ibcon#about to read 5, iclass 10, count 0 2006.173.16:51:28.83#ibcon#read 5, iclass 10, count 0 2006.173.16:51:28.83#ibcon#about to read 6, iclass 10, count 0 2006.173.16:51:28.83#ibcon#read 6, iclass 10, count 0 2006.173.16:51:28.83#ibcon#end of sib2, iclass 10, count 0 2006.173.16:51:28.83#ibcon#*mode == 0, iclass 10, count 0 2006.173.16:51:28.83#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.16:51:28.83#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.16:51:28.83#ibcon#*before write, iclass 10, count 0 2006.173.16:51:28.83#ibcon#enter sib2, iclass 10, count 0 2006.173.16:51:28.83#ibcon#flushed, iclass 10, count 0 2006.173.16:51:28.83#ibcon#about to write, iclass 10, count 0 2006.173.16:51:28.83#ibcon#wrote, iclass 10, count 0 2006.173.16:51:28.83#ibcon#about to read 3, iclass 10, count 0 2006.173.16:51:28.87#ibcon#read 3, iclass 10, count 0 2006.173.16:51:28.87#ibcon#about to read 4, iclass 10, count 0 2006.173.16:51:28.87#ibcon#read 4, iclass 10, count 0 2006.173.16:51:28.87#ibcon#about to read 5, iclass 10, count 0 2006.173.16:51:28.87#ibcon#read 5, iclass 10, count 0 2006.173.16:51:28.87#ibcon#about to read 6, iclass 10, count 0 2006.173.16:51:28.87#ibcon#read 6, iclass 10, count 0 2006.173.16:51:28.87#ibcon#end of sib2, iclass 10, count 0 2006.173.16:51:28.87#ibcon#*after write, iclass 10, count 0 2006.173.16:51:28.87#ibcon#*before return 0, iclass 10, count 0 2006.173.16:51:28.87#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.16:51:28.87#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.16:51:28.87#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.16:51:28.87#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.16:51:28.87$vck44/va=3,5 2006.173.16:51:28.87#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.16:51:28.87#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.16:51:28.87#ibcon#ireg 11 cls_cnt 2 2006.173.16:51:28.87#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.16:51:28.93#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.16:51:28.93#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.16:51:28.93#ibcon#enter wrdev, iclass 12, count 2 2006.173.16:51:28.93#ibcon#first serial, iclass 12, count 2 2006.173.16:51:28.93#ibcon#enter sib2, iclass 12, count 2 2006.173.16:51:28.93#ibcon#flushed, iclass 12, count 2 2006.173.16:51:28.93#ibcon#about to write, iclass 12, count 2 2006.173.16:51:28.93#ibcon#wrote, iclass 12, count 2 2006.173.16:51:28.93#ibcon#about to read 3, iclass 12, count 2 2006.173.16:51:28.95#ibcon#read 3, iclass 12, count 2 2006.173.16:51:28.95#ibcon#about to read 4, iclass 12, count 2 2006.173.16:51:28.95#ibcon#read 4, iclass 12, count 2 2006.173.16:51:28.95#ibcon#about to read 5, iclass 12, count 2 2006.173.16:51:28.95#ibcon#read 5, iclass 12, count 2 2006.173.16:51:28.95#ibcon#about to read 6, iclass 12, count 2 2006.173.16:51:28.95#ibcon#read 6, iclass 12, count 2 2006.173.16:51:28.95#ibcon#end of sib2, iclass 12, count 2 2006.173.16:51:28.95#ibcon#*mode == 0, iclass 12, count 2 2006.173.16:51:28.95#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.16:51:28.95#ibcon#[25=AT03-05\r\n] 2006.173.16:51:28.95#ibcon#*before write, iclass 12, count 2 2006.173.16:51:28.95#ibcon#enter sib2, iclass 12, count 2 2006.173.16:51:28.95#ibcon#flushed, iclass 12, count 2 2006.173.16:51:28.95#ibcon#about to write, iclass 12, count 2 2006.173.16:51:28.95#ibcon#wrote, iclass 12, count 2 2006.173.16:51:28.95#ibcon#about to read 3, iclass 12, count 2 2006.173.16:51:28.98#ibcon#read 3, iclass 12, count 2 2006.173.16:51:28.98#ibcon#about to read 4, iclass 12, count 2 2006.173.16:51:28.98#ibcon#read 4, iclass 12, count 2 2006.173.16:51:28.98#ibcon#about to read 5, iclass 12, count 2 2006.173.16:51:28.98#ibcon#read 5, iclass 12, count 2 2006.173.16:51:28.98#ibcon#about to read 6, iclass 12, count 2 2006.173.16:51:28.98#ibcon#read 6, iclass 12, count 2 2006.173.16:51:28.98#ibcon#end of sib2, iclass 12, count 2 2006.173.16:51:28.98#ibcon#*after write, iclass 12, count 2 2006.173.16:51:28.98#ibcon#*before return 0, iclass 12, count 2 2006.173.16:51:28.98#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.16:51:28.98#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.16:51:28.98#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.16:51:28.98#ibcon#ireg 7 cls_cnt 0 2006.173.16:51:28.98#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.16:51:29.10#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.16:51:29.10#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.16:51:29.10#ibcon#enter wrdev, iclass 12, count 0 2006.173.16:51:29.10#ibcon#first serial, iclass 12, count 0 2006.173.16:51:29.10#ibcon#enter sib2, iclass 12, count 0 2006.173.16:51:29.10#ibcon#flushed, iclass 12, count 0 2006.173.16:51:29.10#ibcon#about to write, iclass 12, count 0 2006.173.16:51:29.10#ibcon#wrote, iclass 12, count 0 2006.173.16:51:29.10#ibcon#about to read 3, iclass 12, count 0 2006.173.16:51:29.12#ibcon#read 3, iclass 12, count 0 2006.173.16:51:29.12#ibcon#about to read 4, iclass 12, count 0 2006.173.16:51:29.12#ibcon#read 4, iclass 12, count 0 2006.173.16:51:29.12#ibcon#about to read 5, iclass 12, count 0 2006.173.16:51:29.12#ibcon#read 5, iclass 12, count 0 2006.173.16:51:29.12#ibcon#about to read 6, iclass 12, count 0 2006.173.16:51:29.12#ibcon#read 6, iclass 12, count 0 2006.173.16:51:29.12#ibcon#end of sib2, iclass 12, count 0 2006.173.16:51:29.12#ibcon#*mode == 0, iclass 12, count 0 2006.173.16:51:29.12#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.16:51:29.12#ibcon#[25=USB\r\n] 2006.173.16:51:29.12#ibcon#*before write, iclass 12, count 0 2006.173.16:51:29.12#ibcon#enter sib2, iclass 12, count 0 2006.173.16:51:29.12#ibcon#flushed, iclass 12, count 0 2006.173.16:51:29.12#ibcon#about to write, iclass 12, count 0 2006.173.16:51:29.12#ibcon#wrote, iclass 12, count 0 2006.173.16:51:29.12#ibcon#about to read 3, iclass 12, count 0 2006.173.16:51:29.15#ibcon#read 3, iclass 12, count 0 2006.173.16:51:29.15#ibcon#about to read 4, iclass 12, count 0 2006.173.16:51:29.15#ibcon#read 4, iclass 12, count 0 2006.173.16:51:29.15#ibcon#about to read 5, iclass 12, count 0 2006.173.16:51:29.15#ibcon#read 5, iclass 12, count 0 2006.173.16:51:29.15#ibcon#about to read 6, iclass 12, count 0 2006.173.16:51:29.15#ibcon#read 6, iclass 12, count 0 2006.173.16:51:29.15#ibcon#end of sib2, iclass 12, count 0 2006.173.16:51:29.15#ibcon#*after write, iclass 12, count 0 2006.173.16:51:29.15#ibcon#*before return 0, iclass 12, count 0 2006.173.16:51:29.15#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.16:51:29.15#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.16:51:29.15#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.16:51:29.15#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.16:51:29.15$vck44/valo=4,624.99 2006.173.16:51:29.15#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.16:51:29.15#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.16:51:29.15#ibcon#ireg 17 cls_cnt 0 2006.173.16:51:29.15#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.16:51:29.15#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.16:51:29.15#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.16:51:29.15#ibcon#enter wrdev, iclass 14, count 0 2006.173.16:51:29.15#ibcon#first serial, iclass 14, count 0 2006.173.16:51:29.15#ibcon#enter sib2, iclass 14, count 0 2006.173.16:51:29.15#ibcon#flushed, iclass 14, count 0 2006.173.16:51:29.15#ibcon#about to write, iclass 14, count 0 2006.173.16:51:29.15#ibcon#wrote, iclass 14, count 0 2006.173.16:51:29.15#ibcon#about to read 3, iclass 14, count 0 2006.173.16:51:29.17#ibcon#read 3, iclass 14, count 0 2006.173.16:51:29.17#ibcon#about to read 4, iclass 14, count 0 2006.173.16:51:29.17#ibcon#read 4, iclass 14, count 0 2006.173.16:51:29.17#ibcon#about to read 5, iclass 14, count 0 2006.173.16:51:29.17#ibcon#read 5, iclass 14, count 0 2006.173.16:51:29.17#ibcon#about to read 6, iclass 14, count 0 2006.173.16:51:29.17#ibcon#read 6, iclass 14, count 0 2006.173.16:51:29.17#ibcon#end of sib2, iclass 14, count 0 2006.173.16:51:29.17#ibcon#*mode == 0, iclass 14, count 0 2006.173.16:51:29.17#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.16:51:29.17#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.16:51:29.17#ibcon#*before write, iclass 14, count 0 2006.173.16:51:29.17#ibcon#enter sib2, iclass 14, count 0 2006.173.16:51:29.17#ibcon#flushed, iclass 14, count 0 2006.173.16:51:29.17#ibcon#about to write, iclass 14, count 0 2006.173.16:51:29.17#ibcon#wrote, iclass 14, count 0 2006.173.16:51:29.17#ibcon#about to read 3, iclass 14, count 0 2006.173.16:51:29.21#ibcon#read 3, iclass 14, count 0 2006.173.16:51:29.21#ibcon#about to read 4, iclass 14, count 0 2006.173.16:51:29.21#ibcon#read 4, iclass 14, count 0 2006.173.16:51:29.21#ibcon#about to read 5, iclass 14, count 0 2006.173.16:51:29.21#ibcon#read 5, iclass 14, count 0 2006.173.16:51:29.21#ibcon#about to read 6, iclass 14, count 0 2006.173.16:51:29.21#ibcon#read 6, iclass 14, count 0 2006.173.16:51:29.21#ibcon#end of sib2, iclass 14, count 0 2006.173.16:51:29.21#ibcon#*after write, iclass 14, count 0 2006.173.16:51:29.21#ibcon#*before return 0, iclass 14, count 0 2006.173.16:51:29.21#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.16:51:29.21#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.16:51:29.21#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.16:51:29.21#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.16:51:29.21$vck44/va=4,6 2006.173.16:51:29.21#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.16:51:29.21#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.16:51:29.21#ibcon#ireg 11 cls_cnt 2 2006.173.16:51:29.21#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.16:51:29.27#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.16:51:29.27#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.16:51:29.27#ibcon#enter wrdev, iclass 16, count 2 2006.173.16:51:29.27#ibcon#first serial, iclass 16, count 2 2006.173.16:51:29.27#ibcon#enter sib2, iclass 16, count 2 2006.173.16:51:29.27#ibcon#flushed, iclass 16, count 2 2006.173.16:51:29.27#ibcon#about to write, iclass 16, count 2 2006.173.16:51:29.27#ibcon#wrote, iclass 16, count 2 2006.173.16:51:29.27#ibcon#about to read 3, iclass 16, count 2 2006.173.16:51:29.29#ibcon#read 3, iclass 16, count 2 2006.173.16:51:29.29#ibcon#about to read 4, iclass 16, count 2 2006.173.16:51:29.29#ibcon#read 4, iclass 16, count 2 2006.173.16:51:29.29#ibcon#about to read 5, iclass 16, count 2 2006.173.16:51:29.29#ibcon#read 5, iclass 16, count 2 2006.173.16:51:29.29#ibcon#about to read 6, iclass 16, count 2 2006.173.16:51:29.29#ibcon#read 6, iclass 16, count 2 2006.173.16:51:29.29#ibcon#end of sib2, iclass 16, count 2 2006.173.16:51:29.29#ibcon#*mode == 0, iclass 16, count 2 2006.173.16:51:29.29#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.16:51:29.29#ibcon#[25=AT04-06\r\n] 2006.173.16:51:29.29#ibcon#*before write, iclass 16, count 2 2006.173.16:51:29.29#ibcon#enter sib2, iclass 16, count 2 2006.173.16:51:29.29#ibcon#flushed, iclass 16, count 2 2006.173.16:51:29.29#ibcon#about to write, iclass 16, count 2 2006.173.16:51:29.29#ibcon#wrote, iclass 16, count 2 2006.173.16:51:29.29#ibcon#about to read 3, iclass 16, count 2 2006.173.16:51:29.32#ibcon#read 3, iclass 16, count 2 2006.173.16:51:29.32#ibcon#about to read 4, iclass 16, count 2 2006.173.16:51:29.32#ibcon#read 4, iclass 16, count 2 2006.173.16:51:29.32#ibcon#about to read 5, iclass 16, count 2 2006.173.16:51:29.32#ibcon#read 5, iclass 16, count 2 2006.173.16:51:29.32#ibcon#about to read 6, iclass 16, count 2 2006.173.16:51:29.32#ibcon#read 6, iclass 16, count 2 2006.173.16:51:29.32#ibcon#end of sib2, iclass 16, count 2 2006.173.16:51:29.32#ibcon#*after write, iclass 16, count 2 2006.173.16:51:29.32#ibcon#*before return 0, iclass 16, count 2 2006.173.16:51:29.32#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.16:51:29.32#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.16:51:29.32#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.16:51:29.32#ibcon#ireg 7 cls_cnt 0 2006.173.16:51:29.32#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.16:51:29.44#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.16:51:29.44#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.16:51:29.44#ibcon#enter wrdev, iclass 16, count 0 2006.173.16:51:29.44#ibcon#first serial, iclass 16, count 0 2006.173.16:51:29.44#ibcon#enter sib2, iclass 16, count 0 2006.173.16:51:29.44#ibcon#flushed, iclass 16, count 0 2006.173.16:51:29.44#ibcon#about to write, iclass 16, count 0 2006.173.16:51:29.44#ibcon#wrote, iclass 16, count 0 2006.173.16:51:29.44#ibcon#about to read 3, iclass 16, count 0 2006.173.16:51:29.46#ibcon#read 3, iclass 16, count 0 2006.173.16:51:29.46#ibcon#about to read 4, iclass 16, count 0 2006.173.16:51:29.46#ibcon#read 4, iclass 16, count 0 2006.173.16:51:29.46#ibcon#about to read 5, iclass 16, count 0 2006.173.16:51:29.46#ibcon#read 5, iclass 16, count 0 2006.173.16:51:29.46#ibcon#about to read 6, iclass 16, count 0 2006.173.16:51:29.46#ibcon#read 6, iclass 16, count 0 2006.173.16:51:29.46#ibcon#end of sib2, iclass 16, count 0 2006.173.16:51:29.46#ibcon#*mode == 0, iclass 16, count 0 2006.173.16:51:29.46#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.16:51:29.46#ibcon#[25=USB\r\n] 2006.173.16:51:29.46#ibcon#*before write, iclass 16, count 0 2006.173.16:51:29.46#ibcon#enter sib2, iclass 16, count 0 2006.173.16:51:29.46#ibcon#flushed, iclass 16, count 0 2006.173.16:51:29.46#ibcon#about to write, iclass 16, count 0 2006.173.16:51:29.46#ibcon#wrote, iclass 16, count 0 2006.173.16:51:29.46#ibcon#about to read 3, iclass 16, count 0 2006.173.16:51:29.49#ibcon#read 3, iclass 16, count 0 2006.173.16:51:29.49#ibcon#about to read 4, iclass 16, count 0 2006.173.16:51:29.49#ibcon#read 4, iclass 16, count 0 2006.173.16:51:29.49#ibcon#about to read 5, iclass 16, count 0 2006.173.16:51:29.49#ibcon#read 5, iclass 16, count 0 2006.173.16:51:29.49#ibcon#about to read 6, iclass 16, count 0 2006.173.16:51:29.49#ibcon#read 6, iclass 16, count 0 2006.173.16:51:29.49#ibcon#end of sib2, iclass 16, count 0 2006.173.16:51:29.49#ibcon#*after write, iclass 16, count 0 2006.173.16:51:29.49#ibcon#*before return 0, iclass 16, count 0 2006.173.16:51:29.49#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.16:51:29.49#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.16:51:29.49#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.16:51:29.49#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.16:51:29.49$vck44/valo=5,734.99 2006.173.16:51:29.49#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.16:51:29.49#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.16:51:29.49#ibcon#ireg 17 cls_cnt 0 2006.173.16:51:29.49#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.16:51:29.49#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.16:51:29.49#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.16:51:29.49#ibcon#enter wrdev, iclass 18, count 0 2006.173.16:51:29.49#ibcon#first serial, iclass 18, count 0 2006.173.16:51:29.49#ibcon#enter sib2, iclass 18, count 0 2006.173.16:51:29.49#ibcon#flushed, iclass 18, count 0 2006.173.16:51:29.49#ibcon#about to write, iclass 18, count 0 2006.173.16:51:29.49#ibcon#wrote, iclass 18, count 0 2006.173.16:51:29.49#ibcon#about to read 3, iclass 18, count 0 2006.173.16:51:29.51#ibcon#read 3, iclass 18, count 0 2006.173.16:51:29.51#ibcon#about to read 4, iclass 18, count 0 2006.173.16:51:29.51#ibcon#read 4, iclass 18, count 0 2006.173.16:51:29.51#ibcon#about to read 5, iclass 18, count 0 2006.173.16:51:29.51#ibcon#read 5, iclass 18, count 0 2006.173.16:51:29.51#ibcon#about to read 6, iclass 18, count 0 2006.173.16:51:29.51#ibcon#read 6, iclass 18, count 0 2006.173.16:51:29.51#ibcon#end of sib2, iclass 18, count 0 2006.173.16:51:29.51#ibcon#*mode == 0, iclass 18, count 0 2006.173.16:51:29.51#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.16:51:29.51#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.16:51:29.51#ibcon#*before write, iclass 18, count 0 2006.173.16:51:29.51#ibcon#enter sib2, iclass 18, count 0 2006.173.16:51:29.51#ibcon#flushed, iclass 18, count 0 2006.173.16:51:29.51#ibcon#about to write, iclass 18, count 0 2006.173.16:51:29.51#ibcon#wrote, iclass 18, count 0 2006.173.16:51:29.51#ibcon#about to read 3, iclass 18, count 0 2006.173.16:51:29.55#ibcon#read 3, iclass 18, count 0 2006.173.16:51:29.55#ibcon#about to read 4, iclass 18, count 0 2006.173.16:51:29.55#ibcon#read 4, iclass 18, count 0 2006.173.16:51:29.55#ibcon#about to read 5, iclass 18, count 0 2006.173.16:51:29.55#ibcon#read 5, iclass 18, count 0 2006.173.16:51:29.55#ibcon#about to read 6, iclass 18, count 0 2006.173.16:51:29.55#ibcon#read 6, iclass 18, count 0 2006.173.16:51:29.55#ibcon#end of sib2, iclass 18, count 0 2006.173.16:51:29.55#ibcon#*after write, iclass 18, count 0 2006.173.16:51:29.55#ibcon#*before return 0, iclass 18, count 0 2006.173.16:51:29.55#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.16:51:29.55#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.16:51:29.55#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.16:51:29.55#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.16:51:29.55$vck44/va=5,4 2006.173.16:51:29.55#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.16:51:29.55#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.16:51:29.55#ibcon#ireg 11 cls_cnt 2 2006.173.16:51:29.55#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.16:51:29.61#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.16:51:29.61#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.16:51:29.61#ibcon#enter wrdev, iclass 20, count 2 2006.173.16:51:29.61#ibcon#first serial, iclass 20, count 2 2006.173.16:51:29.61#ibcon#enter sib2, iclass 20, count 2 2006.173.16:51:29.61#ibcon#flushed, iclass 20, count 2 2006.173.16:51:29.61#ibcon#about to write, iclass 20, count 2 2006.173.16:51:29.61#ibcon#wrote, iclass 20, count 2 2006.173.16:51:29.61#ibcon#about to read 3, iclass 20, count 2 2006.173.16:51:29.63#ibcon#read 3, iclass 20, count 2 2006.173.16:51:29.63#ibcon#about to read 4, iclass 20, count 2 2006.173.16:51:29.63#ibcon#read 4, iclass 20, count 2 2006.173.16:51:29.63#ibcon#about to read 5, iclass 20, count 2 2006.173.16:51:29.63#ibcon#read 5, iclass 20, count 2 2006.173.16:51:29.63#ibcon#about to read 6, iclass 20, count 2 2006.173.16:51:29.63#ibcon#read 6, iclass 20, count 2 2006.173.16:51:29.63#ibcon#end of sib2, iclass 20, count 2 2006.173.16:51:29.63#ibcon#*mode == 0, iclass 20, count 2 2006.173.16:51:29.63#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.16:51:29.63#ibcon#[25=AT05-04\r\n] 2006.173.16:51:29.63#ibcon#*before write, iclass 20, count 2 2006.173.16:51:29.63#ibcon#enter sib2, iclass 20, count 2 2006.173.16:51:29.63#ibcon#flushed, iclass 20, count 2 2006.173.16:51:29.63#ibcon#about to write, iclass 20, count 2 2006.173.16:51:29.63#ibcon#wrote, iclass 20, count 2 2006.173.16:51:29.63#ibcon#about to read 3, iclass 20, count 2 2006.173.16:51:29.66#ibcon#read 3, iclass 20, count 2 2006.173.16:51:29.66#ibcon#about to read 4, iclass 20, count 2 2006.173.16:51:29.66#ibcon#read 4, iclass 20, count 2 2006.173.16:51:29.66#ibcon#about to read 5, iclass 20, count 2 2006.173.16:51:29.66#ibcon#read 5, iclass 20, count 2 2006.173.16:51:29.66#ibcon#about to read 6, iclass 20, count 2 2006.173.16:51:29.66#ibcon#read 6, iclass 20, count 2 2006.173.16:51:29.66#ibcon#end of sib2, iclass 20, count 2 2006.173.16:51:29.66#ibcon#*after write, iclass 20, count 2 2006.173.16:51:29.66#ibcon#*before return 0, iclass 20, count 2 2006.173.16:51:29.66#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.16:51:29.66#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.16:51:29.66#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.16:51:29.66#ibcon#ireg 7 cls_cnt 0 2006.173.16:51:29.66#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.16:51:29.78#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.16:51:29.78#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.16:51:29.78#ibcon#enter wrdev, iclass 20, count 0 2006.173.16:51:29.78#ibcon#first serial, iclass 20, count 0 2006.173.16:51:29.78#ibcon#enter sib2, iclass 20, count 0 2006.173.16:51:29.78#ibcon#flushed, iclass 20, count 0 2006.173.16:51:29.78#ibcon#about to write, iclass 20, count 0 2006.173.16:51:29.78#ibcon#wrote, iclass 20, count 0 2006.173.16:51:29.78#ibcon#about to read 3, iclass 20, count 0 2006.173.16:51:29.80#ibcon#read 3, iclass 20, count 0 2006.173.16:51:29.80#ibcon#about to read 4, iclass 20, count 0 2006.173.16:51:29.80#ibcon#read 4, iclass 20, count 0 2006.173.16:51:29.80#ibcon#about to read 5, iclass 20, count 0 2006.173.16:51:29.80#ibcon#read 5, iclass 20, count 0 2006.173.16:51:29.80#ibcon#about to read 6, iclass 20, count 0 2006.173.16:51:29.80#ibcon#read 6, iclass 20, count 0 2006.173.16:51:29.80#ibcon#end of sib2, iclass 20, count 0 2006.173.16:51:29.80#ibcon#*mode == 0, iclass 20, count 0 2006.173.16:51:29.80#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.16:51:29.80#ibcon#[25=USB\r\n] 2006.173.16:51:29.80#ibcon#*before write, iclass 20, count 0 2006.173.16:51:29.80#ibcon#enter sib2, iclass 20, count 0 2006.173.16:51:29.80#ibcon#flushed, iclass 20, count 0 2006.173.16:51:29.80#ibcon#about to write, iclass 20, count 0 2006.173.16:51:29.80#ibcon#wrote, iclass 20, count 0 2006.173.16:51:29.80#ibcon#about to read 3, iclass 20, count 0 2006.173.16:51:29.83#ibcon#read 3, iclass 20, count 0 2006.173.16:51:29.83#ibcon#about to read 4, iclass 20, count 0 2006.173.16:51:29.83#ibcon#read 4, iclass 20, count 0 2006.173.16:51:29.83#ibcon#about to read 5, iclass 20, count 0 2006.173.16:51:29.83#ibcon#read 5, iclass 20, count 0 2006.173.16:51:29.83#ibcon#about to read 6, iclass 20, count 0 2006.173.16:51:29.83#ibcon#read 6, iclass 20, count 0 2006.173.16:51:29.83#ibcon#end of sib2, iclass 20, count 0 2006.173.16:51:29.83#ibcon#*after write, iclass 20, count 0 2006.173.16:51:29.83#ibcon#*before return 0, iclass 20, count 0 2006.173.16:51:29.83#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.16:51:29.83#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.16:51:29.83#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.16:51:29.83#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.16:51:29.83$vck44/valo=6,814.99 2006.173.16:51:29.83#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.16:51:29.83#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.16:51:29.83#ibcon#ireg 17 cls_cnt 0 2006.173.16:51:29.83#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.16:51:29.83#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.16:51:29.83#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.16:51:29.83#ibcon#enter wrdev, iclass 22, count 0 2006.173.16:51:29.83#ibcon#first serial, iclass 22, count 0 2006.173.16:51:29.83#ibcon#enter sib2, iclass 22, count 0 2006.173.16:51:29.83#ibcon#flushed, iclass 22, count 0 2006.173.16:51:29.83#ibcon#about to write, iclass 22, count 0 2006.173.16:51:29.83#ibcon#wrote, iclass 22, count 0 2006.173.16:51:29.83#ibcon#about to read 3, iclass 22, count 0 2006.173.16:51:29.85#ibcon#read 3, iclass 22, count 0 2006.173.16:51:29.85#ibcon#about to read 4, iclass 22, count 0 2006.173.16:51:29.85#ibcon#read 4, iclass 22, count 0 2006.173.16:51:29.85#ibcon#about to read 5, iclass 22, count 0 2006.173.16:51:29.85#ibcon#read 5, iclass 22, count 0 2006.173.16:51:29.85#ibcon#about to read 6, iclass 22, count 0 2006.173.16:51:29.85#ibcon#read 6, iclass 22, count 0 2006.173.16:51:29.85#ibcon#end of sib2, iclass 22, count 0 2006.173.16:51:29.85#ibcon#*mode == 0, iclass 22, count 0 2006.173.16:51:29.85#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.16:51:29.85#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.16:51:29.85#ibcon#*before write, iclass 22, count 0 2006.173.16:51:29.85#ibcon#enter sib2, iclass 22, count 0 2006.173.16:51:29.85#ibcon#flushed, iclass 22, count 0 2006.173.16:51:29.85#ibcon#about to write, iclass 22, count 0 2006.173.16:51:29.85#ibcon#wrote, iclass 22, count 0 2006.173.16:51:29.85#ibcon#about to read 3, iclass 22, count 0 2006.173.16:51:29.89#ibcon#read 3, iclass 22, count 0 2006.173.16:51:29.89#ibcon#about to read 4, iclass 22, count 0 2006.173.16:51:29.89#ibcon#read 4, iclass 22, count 0 2006.173.16:51:29.89#ibcon#about to read 5, iclass 22, count 0 2006.173.16:51:29.89#ibcon#read 5, iclass 22, count 0 2006.173.16:51:29.89#ibcon#about to read 6, iclass 22, count 0 2006.173.16:51:29.89#ibcon#read 6, iclass 22, count 0 2006.173.16:51:29.89#ibcon#end of sib2, iclass 22, count 0 2006.173.16:51:29.89#ibcon#*after write, iclass 22, count 0 2006.173.16:51:29.89#ibcon#*before return 0, iclass 22, count 0 2006.173.16:51:29.89#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.16:51:29.89#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.16:51:29.89#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.16:51:29.89#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.16:51:29.89$vck44/va=6,3 2006.173.16:51:29.89#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.16:51:29.89#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.16:51:29.89#ibcon#ireg 11 cls_cnt 2 2006.173.16:51:29.89#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.16:51:29.95#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.16:51:29.95#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.16:51:29.95#ibcon#enter wrdev, iclass 24, count 2 2006.173.16:51:29.95#ibcon#first serial, iclass 24, count 2 2006.173.16:51:29.95#ibcon#enter sib2, iclass 24, count 2 2006.173.16:51:29.95#ibcon#flushed, iclass 24, count 2 2006.173.16:51:29.95#ibcon#about to write, iclass 24, count 2 2006.173.16:51:29.95#ibcon#wrote, iclass 24, count 2 2006.173.16:51:29.95#ibcon#about to read 3, iclass 24, count 2 2006.173.16:51:29.97#ibcon#read 3, iclass 24, count 2 2006.173.16:51:29.97#ibcon#about to read 4, iclass 24, count 2 2006.173.16:51:29.97#ibcon#read 4, iclass 24, count 2 2006.173.16:51:29.97#ibcon#about to read 5, iclass 24, count 2 2006.173.16:51:29.97#ibcon#read 5, iclass 24, count 2 2006.173.16:51:29.97#ibcon#about to read 6, iclass 24, count 2 2006.173.16:51:29.97#ibcon#read 6, iclass 24, count 2 2006.173.16:51:29.97#ibcon#end of sib2, iclass 24, count 2 2006.173.16:51:29.97#ibcon#*mode == 0, iclass 24, count 2 2006.173.16:51:29.97#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.16:51:29.97#ibcon#[25=AT06-03\r\n] 2006.173.16:51:29.97#ibcon#*before write, iclass 24, count 2 2006.173.16:51:29.97#ibcon#enter sib2, iclass 24, count 2 2006.173.16:51:29.97#ibcon#flushed, iclass 24, count 2 2006.173.16:51:29.97#ibcon#about to write, iclass 24, count 2 2006.173.16:51:29.97#ibcon#wrote, iclass 24, count 2 2006.173.16:51:29.97#ibcon#about to read 3, iclass 24, count 2 2006.173.16:51:30.00#ibcon#read 3, iclass 24, count 2 2006.173.16:51:30.00#ibcon#about to read 4, iclass 24, count 2 2006.173.16:51:30.00#ibcon#read 4, iclass 24, count 2 2006.173.16:51:30.00#ibcon#about to read 5, iclass 24, count 2 2006.173.16:51:30.00#ibcon#read 5, iclass 24, count 2 2006.173.16:51:30.00#ibcon#about to read 6, iclass 24, count 2 2006.173.16:51:30.00#ibcon#read 6, iclass 24, count 2 2006.173.16:51:30.00#ibcon#end of sib2, iclass 24, count 2 2006.173.16:51:30.00#ibcon#*after write, iclass 24, count 2 2006.173.16:51:30.00#ibcon#*before return 0, iclass 24, count 2 2006.173.16:51:30.00#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.16:51:30.00#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.16:51:30.00#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.16:51:30.00#ibcon#ireg 7 cls_cnt 0 2006.173.16:51:30.00#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.16:51:30.12#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.16:51:30.12#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.16:51:30.12#ibcon#enter wrdev, iclass 24, count 0 2006.173.16:51:30.12#ibcon#first serial, iclass 24, count 0 2006.173.16:51:30.12#ibcon#enter sib2, iclass 24, count 0 2006.173.16:51:30.12#ibcon#flushed, iclass 24, count 0 2006.173.16:51:30.12#ibcon#about to write, iclass 24, count 0 2006.173.16:51:30.12#ibcon#wrote, iclass 24, count 0 2006.173.16:51:30.12#ibcon#about to read 3, iclass 24, count 0 2006.173.16:51:30.14#ibcon#read 3, iclass 24, count 0 2006.173.16:51:30.14#ibcon#about to read 4, iclass 24, count 0 2006.173.16:51:30.14#ibcon#read 4, iclass 24, count 0 2006.173.16:51:30.14#ibcon#about to read 5, iclass 24, count 0 2006.173.16:51:30.14#ibcon#read 5, iclass 24, count 0 2006.173.16:51:30.14#ibcon#about to read 6, iclass 24, count 0 2006.173.16:51:30.14#ibcon#read 6, iclass 24, count 0 2006.173.16:51:30.14#ibcon#end of sib2, iclass 24, count 0 2006.173.16:51:30.14#ibcon#*mode == 0, iclass 24, count 0 2006.173.16:51:30.14#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.16:51:30.14#ibcon#[25=USB\r\n] 2006.173.16:51:30.14#ibcon#*before write, iclass 24, count 0 2006.173.16:51:30.14#ibcon#enter sib2, iclass 24, count 0 2006.173.16:51:30.14#ibcon#flushed, iclass 24, count 0 2006.173.16:51:30.14#ibcon#about to write, iclass 24, count 0 2006.173.16:51:30.14#ibcon#wrote, iclass 24, count 0 2006.173.16:51:30.14#ibcon#about to read 3, iclass 24, count 0 2006.173.16:51:30.17#ibcon#read 3, iclass 24, count 0 2006.173.16:51:30.17#ibcon#about to read 4, iclass 24, count 0 2006.173.16:51:30.17#ibcon#read 4, iclass 24, count 0 2006.173.16:51:30.17#ibcon#about to read 5, iclass 24, count 0 2006.173.16:51:30.17#ibcon#read 5, iclass 24, count 0 2006.173.16:51:30.17#ibcon#about to read 6, iclass 24, count 0 2006.173.16:51:30.17#ibcon#read 6, iclass 24, count 0 2006.173.16:51:30.17#ibcon#end of sib2, iclass 24, count 0 2006.173.16:51:30.17#ibcon#*after write, iclass 24, count 0 2006.173.16:51:30.17#ibcon#*before return 0, iclass 24, count 0 2006.173.16:51:30.17#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.16:51:30.17#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.16:51:30.17#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.16:51:30.17#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.16:51:30.17$vck44/valo=7,864.99 2006.173.16:51:30.17#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.16:51:30.17#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.16:51:30.17#ibcon#ireg 17 cls_cnt 0 2006.173.16:51:30.17#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.16:51:30.17#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.16:51:30.17#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.16:51:30.17#ibcon#enter wrdev, iclass 26, count 0 2006.173.16:51:30.17#ibcon#first serial, iclass 26, count 0 2006.173.16:51:30.17#ibcon#enter sib2, iclass 26, count 0 2006.173.16:51:30.17#ibcon#flushed, iclass 26, count 0 2006.173.16:51:30.17#ibcon#about to write, iclass 26, count 0 2006.173.16:51:30.17#ibcon#wrote, iclass 26, count 0 2006.173.16:51:30.17#ibcon#about to read 3, iclass 26, count 0 2006.173.16:51:30.19#ibcon#read 3, iclass 26, count 0 2006.173.16:51:30.19#ibcon#about to read 4, iclass 26, count 0 2006.173.16:51:30.19#ibcon#read 4, iclass 26, count 0 2006.173.16:51:30.19#ibcon#about to read 5, iclass 26, count 0 2006.173.16:51:30.19#ibcon#read 5, iclass 26, count 0 2006.173.16:51:30.19#ibcon#about to read 6, iclass 26, count 0 2006.173.16:51:30.19#ibcon#read 6, iclass 26, count 0 2006.173.16:51:30.19#ibcon#end of sib2, iclass 26, count 0 2006.173.16:51:30.19#ibcon#*mode == 0, iclass 26, count 0 2006.173.16:51:30.19#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.16:51:30.19#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.16:51:30.19#ibcon#*before write, iclass 26, count 0 2006.173.16:51:30.19#ibcon#enter sib2, iclass 26, count 0 2006.173.16:51:30.19#ibcon#flushed, iclass 26, count 0 2006.173.16:51:30.19#ibcon#about to write, iclass 26, count 0 2006.173.16:51:30.19#ibcon#wrote, iclass 26, count 0 2006.173.16:51:30.19#ibcon#about to read 3, iclass 26, count 0 2006.173.16:51:30.23#ibcon#read 3, iclass 26, count 0 2006.173.16:51:30.23#ibcon#about to read 4, iclass 26, count 0 2006.173.16:51:30.23#ibcon#read 4, iclass 26, count 0 2006.173.16:51:30.23#ibcon#about to read 5, iclass 26, count 0 2006.173.16:51:30.23#ibcon#read 5, iclass 26, count 0 2006.173.16:51:30.23#ibcon#about to read 6, iclass 26, count 0 2006.173.16:51:30.23#ibcon#read 6, iclass 26, count 0 2006.173.16:51:30.23#ibcon#end of sib2, iclass 26, count 0 2006.173.16:51:30.23#ibcon#*after write, iclass 26, count 0 2006.173.16:51:30.23#ibcon#*before return 0, iclass 26, count 0 2006.173.16:51:30.23#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.16:51:30.23#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.16:51:30.23#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.16:51:30.23#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.16:51:30.23$vck44/va=7,4 2006.173.16:51:30.23#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.16:51:30.23#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.16:51:30.23#ibcon#ireg 11 cls_cnt 2 2006.173.16:51:30.23#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.16:51:30.29#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.16:51:30.29#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.16:51:30.29#ibcon#enter wrdev, iclass 28, count 2 2006.173.16:51:30.29#ibcon#first serial, iclass 28, count 2 2006.173.16:51:30.29#ibcon#enter sib2, iclass 28, count 2 2006.173.16:51:30.29#ibcon#flushed, iclass 28, count 2 2006.173.16:51:30.29#ibcon#about to write, iclass 28, count 2 2006.173.16:51:30.29#ibcon#wrote, iclass 28, count 2 2006.173.16:51:30.29#ibcon#about to read 3, iclass 28, count 2 2006.173.16:51:30.31#ibcon#read 3, iclass 28, count 2 2006.173.16:51:30.31#ibcon#about to read 4, iclass 28, count 2 2006.173.16:51:30.31#ibcon#read 4, iclass 28, count 2 2006.173.16:51:30.31#ibcon#about to read 5, iclass 28, count 2 2006.173.16:51:30.31#ibcon#read 5, iclass 28, count 2 2006.173.16:51:30.31#ibcon#about to read 6, iclass 28, count 2 2006.173.16:51:30.31#ibcon#read 6, iclass 28, count 2 2006.173.16:51:30.31#ibcon#end of sib2, iclass 28, count 2 2006.173.16:51:30.31#ibcon#*mode == 0, iclass 28, count 2 2006.173.16:51:30.31#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.16:51:30.31#ibcon#[25=AT07-04\r\n] 2006.173.16:51:30.31#ibcon#*before write, iclass 28, count 2 2006.173.16:51:30.31#ibcon#enter sib2, iclass 28, count 2 2006.173.16:51:30.31#ibcon#flushed, iclass 28, count 2 2006.173.16:51:30.31#ibcon#about to write, iclass 28, count 2 2006.173.16:51:30.31#ibcon#wrote, iclass 28, count 2 2006.173.16:51:30.31#ibcon#about to read 3, iclass 28, count 2 2006.173.16:51:30.34#abcon#<5=/14 0.4 1.6 20.431001002.8\r\n> 2006.173.16:51:30.34#ibcon#read 3, iclass 28, count 2 2006.173.16:51:30.34#ibcon#about to read 4, iclass 28, count 2 2006.173.16:51:30.34#ibcon#read 4, iclass 28, count 2 2006.173.16:51:30.34#ibcon#about to read 5, iclass 28, count 2 2006.173.16:51:30.34#ibcon#read 5, iclass 28, count 2 2006.173.16:51:30.34#ibcon#about to read 6, iclass 28, count 2 2006.173.16:51:30.34#ibcon#read 6, iclass 28, count 2 2006.173.16:51:30.34#ibcon#end of sib2, iclass 28, count 2 2006.173.16:51:30.34#ibcon#*after write, iclass 28, count 2 2006.173.16:51:30.34#ibcon#*before return 0, iclass 28, count 2 2006.173.16:51:30.34#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.16:51:30.34#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.16:51:30.34#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.16:51:30.34#ibcon#ireg 7 cls_cnt 0 2006.173.16:51:30.34#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.16:51:30.36#abcon#{5=INTERFACE CLEAR} 2006.173.16:51:30.42#abcon#[5=S1D000X0/0*\r\n] 2006.173.16:51:30.46#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.16:51:30.46#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.16:51:30.46#ibcon#enter wrdev, iclass 28, count 0 2006.173.16:51:30.46#ibcon#first serial, iclass 28, count 0 2006.173.16:51:30.46#ibcon#enter sib2, iclass 28, count 0 2006.173.16:51:30.46#ibcon#flushed, iclass 28, count 0 2006.173.16:51:30.46#ibcon#about to write, iclass 28, count 0 2006.173.16:51:30.46#ibcon#wrote, iclass 28, count 0 2006.173.16:51:30.46#ibcon#about to read 3, iclass 28, count 0 2006.173.16:51:30.48#ibcon#read 3, iclass 28, count 0 2006.173.16:51:30.48#ibcon#about to read 4, iclass 28, count 0 2006.173.16:51:30.48#ibcon#read 4, iclass 28, count 0 2006.173.16:51:30.48#ibcon#about to read 5, iclass 28, count 0 2006.173.16:51:30.48#ibcon#read 5, iclass 28, count 0 2006.173.16:51:30.48#ibcon#about to read 6, iclass 28, count 0 2006.173.16:51:30.48#ibcon#read 6, iclass 28, count 0 2006.173.16:51:30.48#ibcon#end of sib2, iclass 28, count 0 2006.173.16:51:30.48#ibcon#*mode == 0, iclass 28, count 0 2006.173.16:51:30.48#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.16:51:30.48#ibcon#[25=USB\r\n] 2006.173.16:51:30.48#ibcon#*before write, iclass 28, count 0 2006.173.16:51:30.48#ibcon#enter sib2, iclass 28, count 0 2006.173.16:51:30.48#ibcon#flushed, iclass 28, count 0 2006.173.16:51:30.48#ibcon#about to write, iclass 28, count 0 2006.173.16:51:30.48#ibcon#wrote, iclass 28, count 0 2006.173.16:51:30.48#ibcon#about to read 3, iclass 28, count 0 2006.173.16:51:30.51#ibcon#read 3, iclass 28, count 0 2006.173.16:51:30.51#ibcon#about to read 4, iclass 28, count 0 2006.173.16:51:30.51#ibcon#read 4, iclass 28, count 0 2006.173.16:51:30.51#ibcon#about to read 5, iclass 28, count 0 2006.173.16:51:30.51#ibcon#read 5, iclass 28, count 0 2006.173.16:51:30.51#ibcon#about to read 6, iclass 28, count 0 2006.173.16:51:30.51#ibcon#read 6, iclass 28, count 0 2006.173.16:51:30.51#ibcon#end of sib2, iclass 28, count 0 2006.173.16:51:30.51#ibcon#*after write, iclass 28, count 0 2006.173.16:51:30.51#ibcon#*before return 0, iclass 28, count 0 2006.173.16:51:30.51#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.16:51:30.51#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.16:51:30.51#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.16:51:30.51#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.16:51:30.51$vck44/valo=8,884.99 2006.173.16:51:30.51#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.16:51:30.51#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.16:51:30.51#ibcon#ireg 17 cls_cnt 0 2006.173.16:51:30.51#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.16:51:30.51#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.16:51:30.51#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.16:51:30.51#ibcon#enter wrdev, iclass 34, count 0 2006.173.16:51:30.51#ibcon#first serial, iclass 34, count 0 2006.173.16:51:30.51#ibcon#enter sib2, iclass 34, count 0 2006.173.16:51:30.51#ibcon#flushed, iclass 34, count 0 2006.173.16:51:30.51#ibcon#about to write, iclass 34, count 0 2006.173.16:51:30.51#ibcon#wrote, iclass 34, count 0 2006.173.16:51:30.51#ibcon#about to read 3, iclass 34, count 0 2006.173.16:51:30.53#ibcon#read 3, iclass 34, count 0 2006.173.16:51:30.53#ibcon#about to read 4, iclass 34, count 0 2006.173.16:51:30.53#ibcon#read 4, iclass 34, count 0 2006.173.16:51:30.53#ibcon#about to read 5, iclass 34, count 0 2006.173.16:51:30.53#ibcon#read 5, iclass 34, count 0 2006.173.16:51:30.53#ibcon#about to read 6, iclass 34, count 0 2006.173.16:51:30.53#ibcon#read 6, iclass 34, count 0 2006.173.16:51:30.53#ibcon#end of sib2, iclass 34, count 0 2006.173.16:51:30.53#ibcon#*mode == 0, iclass 34, count 0 2006.173.16:51:30.53#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.16:51:30.53#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.16:51:30.53#ibcon#*before write, iclass 34, count 0 2006.173.16:51:30.53#ibcon#enter sib2, iclass 34, count 0 2006.173.16:51:30.53#ibcon#flushed, iclass 34, count 0 2006.173.16:51:30.53#ibcon#about to write, iclass 34, count 0 2006.173.16:51:30.53#ibcon#wrote, iclass 34, count 0 2006.173.16:51:30.53#ibcon#about to read 3, iclass 34, count 0 2006.173.16:51:30.57#ibcon#read 3, iclass 34, count 0 2006.173.16:51:30.57#ibcon#about to read 4, iclass 34, count 0 2006.173.16:51:30.57#ibcon#read 4, iclass 34, count 0 2006.173.16:51:30.57#ibcon#about to read 5, iclass 34, count 0 2006.173.16:51:30.57#ibcon#read 5, iclass 34, count 0 2006.173.16:51:30.57#ibcon#about to read 6, iclass 34, count 0 2006.173.16:51:30.57#ibcon#read 6, iclass 34, count 0 2006.173.16:51:30.57#ibcon#end of sib2, iclass 34, count 0 2006.173.16:51:30.57#ibcon#*after write, iclass 34, count 0 2006.173.16:51:30.57#ibcon#*before return 0, iclass 34, count 0 2006.173.16:51:30.57#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.16:51:30.57#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.16:51:30.57#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.16:51:30.57#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.16:51:30.57$vck44/va=8,4 2006.173.16:51:30.57#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.16:51:30.57#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.16:51:30.57#ibcon#ireg 11 cls_cnt 2 2006.173.16:51:30.57#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.16:51:30.63#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.16:51:30.63#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.16:51:30.63#ibcon#enter wrdev, iclass 36, count 2 2006.173.16:51:30.63#ibcon#first serial, iclass 36, count 2 2006.173.16:51:30.63#ibcon#enter sib2, iclass 36, count 2 2006.173.16:51:30.63#ibcon#flushed, iclass 36, count 2 2006.173.16:51:30.63#ibcon#about to write, iclass 36, count 2 2006.173.16:51:30.63#ibcon#wrote, iclass 36, count 2 2006.173.16:51:30.63#ibcon#about to read 3, iclass 36, count 2 2006.173.16:51:30.65#ibcon#read 3, iclass 36, count 2 2006.173.16:51:30.65#ibcon#about to read 4, iclass 36, count 2 2006.173.16:51:30.65#ibcon#read 4, iclass 36, count 2 2006.173.16:51:30.65#ibcon#about to read 5, iclass 36, count 2 2006.173.16:51:30.65#ibcon#read 5, iclass 36, count 2 2006.173.16:51:30.65#ibcon#about to read 6, iclass 36, count 2 2006.173.16:51:30.65#ibcon#read 6, iclass 36, count 2 2006.173.16:51:30.65#ibcon#end of sib2, iclass 36, count 2 2006.173.16:51:30.65#ibcon#*mode == 0, iclass 36, count 2 2006.173.16:51:30.65#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.16:51:30.65#ibcon#[25=AT08-04\r\n] 2006.173.16:51:30.65#ibcon#*before write, iclass 36, count 2 2006.173.16:51:30.65#ibcon#enter sib2, iclass 36, count 2 2006.173.16:51:30.65#ibcon#flushed, iclass 36, count 2 2006.173.16:51:30.65#ibcon#about to write, iclass 36, count 2 2006.173.16:51:30.65#ibcon#wrote, iclass 36, count 2 2006.173.16:51:30.65#ibcon#about to read 3, iclass 36, count 2 2006.173.16:51:30.68#ibcon#read 3, iclass 36, count 2 2006.173.16:51:30.68#ibcon#about to read 4, iclass 36, count 2 2006.173.16:51:30.68#ibcon#read 4, iclass 36, count 2 2006.173.16:51:30.68#ibcon#about to read 5, iclass 36, count 2 2006.173.16:51:30.68#ibcon#read 5, iclass 36, count 2 2006.173.16:51:30.68#ibcon#about to read 6, iclass 36, count 2 2006.173.16:51:30.68#ibcon#read 6, iclass 36, count 2 2006.173.16:51:30.68#ibcon#end of sib2, iclass 36, count 2 2006.173.16:51:30.68#ibcon#*after write, iclass 36, count 2 2006.173.16:51:30.68#ibcon#*before return 0, iclass 36, count 2 2006.173.16:51:30.68#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.16:51:30.68#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.16:51:30.68#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.16:51:30.68#ibcon#ireg 7 cls_cnt 0 2006.173.16:51:30.68#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.16:51:30.80#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.16:51:30.80#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.16:51:30.80#ibcon#enter wrdev, iclass 36, count 0 2006.173.16:51:30.80#ibcon#first serial, iclass 36, count 0 2006.173.16:51:30.80#ibcon#enter sib2, iclass 36, count 0 2006.173.16:51:30.80#ibcon#flushed, iclass 36, count 0 2006.173.16:51:30.80#ibcon#about to write, iclass 36, count 0 2006.173.16:51:30.80#ibcon#wrote, iclass 36, count 0 2006.173.16:51:30.80#ibcon#about to read 3, iclass 36, count 0 2006.173.16:51:30.82#ibcon#read 3, iclass 36, count 0 2006.173.16:51:30.82#ibcon#about to read 4, iclass 36, count 0 2006.173.16:51:30.82#ibcon#read 4, iclass 36, count 0 2006.173.16:51:30.82#ibcon#about to read 5, iclass 36, count 0 2006.173.16:51:30.82#ibcon#read 5, iclass 36, count 0 2006.173.16:51:30.82#ibcon#about to read 6, iclass 36, count 0 2006.173.16:51:30.82#ibcon#read 6, iclass 36, count 0 2006.173.16:51:30.82#ibcon#end of sib2, iclass 36, count 0 2006.173.16:51:30.82#ibcon#*mode == 0, iclass 36, count 0 2006.173.16:51:30.82#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.16:51:30.82#ibcon#[25=USB\r\n] 2006.173.16:51:30.82#ibcon#*before write, iclass 36, count 0 2006.173.16:51:30.82#ibcon#enter sib2, iclass 36, count 0 2006.173.16:51:30.82#ibcon#flushed, iclass 36, count 0 2006.173.16:51:30.82#ibcon#about to write, iclass 36, count 0 2006.173.16:51:30.82#ibcon#wrote, iclass 36, count 0 2006.173.16:51:30.82#ibcon#about to read 3, iclass 36, count 0 2006.173.16:51:30.85#ibcon#read 3, iclass 36, count 0 2006.173.16:51:30.85#ibcon#about to read 4, iclass 36, count 0 2006.173.16:51:30.85#ibcon#read 4, iclass 36, count 0 2006.173.16:51:30.85#ibcon#about to read 5, iclass 36, count 0 2006.173.16:51:30.85#ibcon#read 5, iclass 36, count 0 2006.173.16:51:30.85#ibcon#about to read 6, iclass 36, count 0 2006.173.16:51:30.85#ibcon#read 6, iclass 36, count 0 2006.173.16:51:30.85#ibcon#end of sib2, iclass 36, count 0 2006.173.16:51:30.85#ibcon#*after write, iclass 36, count 0 2006.173.16:51:30.85#ibcon#*before return 0, iclass 36, count 0 2006.173.16:51:30.85#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.16:51:30.85#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.16:51:30.85#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.16:51:30.85#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.16:51:30.85$vck44/vblo=1,629.99 2006.173.16:51:30.85#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.16:51:30.85#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.16:51:30.85#ibcon#ireg 17 cls_cnt 0 2006.173.16:51:30.85#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.16:51:30.85#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.16:51:30.85#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.16:51:30.85#ibcon#enter wrdev, iclass 38, count 0 2006.173.16:51:30.85#ibcon#first serial, iclass 38, count 0 2006.173.16:51:30.85#ibcon#enter sib2, iclass 38, count 0 2006.173.16:51:30.85#ibcon#flushed, iclass 38, count 0 2006.173.16:51:30.85#ibcon#about to write, iclass 38, count 0 2006.173.16:51:30.85#ibcon#wrote, iclass 38, count 0 2006.173.16:51:30.85#ibcon#about to read 3, iclass 38, count 0 2006.173.16:51:30.87#ibcon#read 3, iclass 38, count 0 2006.173.16:51:30.87#ibcon#about to read 4, iclass 38, count 0 2006.173.16:51:30.87#ibcon#read 4, iclass 38, count 0 2006.173.16:51:30.87#ibcon#about to read 5, iclass 38, count 0 2006.173.16:51:30.87#ibcon#read 5, iclass 38, count 0 2006.173.16:51:30.87#ibcon#about to read 6, iclass 38, count 0 2006.173.16:51:30.87#ibcon#read 6, iclass 38, count 0 2006.173.16:51:30.87#ibcon#end of sib2, iclass 38, count 0 2006.173.16:51:30.87#ibcon#*mode == 0, iclass 38, count 0 2006.173.16:51:30.87#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.16:51:30.87#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.16:51:30.87#ibcon#*before write, iclass 38, count 0 2006.173.16:51:30.87#ibcon#enter sib2, iclass 38, count 0 2006.173.16:51:30.87#ibcon#flushed, iclass 38, count 0 2006.173.16:51:30.87#ibcon#about to write, iclass 38, count 0 2006.173.16:51:30.87#ibcon#wrote, iclass 38, count 0 2006.173.16:51:30.87#ibcon#about to read 3, iclass 38, count 0 2006.173.16:51:30.91#ibcon#read 3, iclass 38, count 0 2006.173.16:51:30.91#ibcon#about to read 4, iclass 38, count 0 2006.173.16:51:30.91#ibcon#read 4, iclass 38, count 0 2006.173.16:51:30.91#ibcon#about to read 5, iclass 38, count 0 2006.173.16:51:30.91#ibcon#read 5, iclass 38, count 0 2006.173.16:51:30.91#ibcon#about to read 6, iclass 38, count 0 2006.173.16:51:30.91#ibcon#read 6, iclass 38, count 0 2006.173.16:51:30.91#ibcon#end of sib2, iclass 38, count 0 2006.173.16:51:30.91#ibcon#*after write, iclass 38, count 0 2006.173.16:51:30.91#ibcon#*before return 0, iclass 38, count 0 2006.173.16:51:30.91#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.16:51:30.91#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.16:51:30.91#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.16:51:30.91#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.16:51:30.91$vck44/vb=1,4 2006.173.16:51:30.91#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.16:51:30.91#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.16:51:30.91#ibcon#ireg 11 cls_cnt 2 2006.173.16:51:30.91#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.16:51:30.91#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.16:51:30.91#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.16:51:30.91#ibcon#enter wrdev, iclass 40, count 2 2006.173.16:51:30.91#ibcon#first serial, iclass 40, count 2 2006.173.16:51:30.91#ibcon#enter sib2, iclass 40, count 2 2006.173.16:51:30.91#ibcon#flushed, iclass 40, count 2 2006.173.16:51:30.91#ibcon#about to write, iclass 40, count 2 2006.173.16:51:30.91#ibcon#wrote, iclass 40, count 2 2006.173.16:51:30.91#ibcon#about to read 3, iclass 40, count 2 2006.173.16:51:30.93#ibcon#read 3, iclass 40, count 2 2006.173.16:51:30.93#ibcon#about to read 4, iclass 40, count 2 2006.173.16:51:30.93#ibcon#read 4, iclass 40, count 2 2006.173.16:51:30.93#ibcon#about to read 5, iclass 40, count 2 2006.173.16:51:30.93#ibcon#read 5, iclass 40, count 2 2006.173.16:51:30.93#ibcon#about to read 6, iclass 40, count 2 2006.173.16:51:30.93#ibcon#read 6, iclass 40, count 2 2006.173.16:51:30.93#ibcon#end of sib2, iclass 40, count 2 2006.173.16:51:30.93#ibcon#*mode == 0, iclass 40, count 2 2006.173.16:51:30.93#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.16:51:30.93#ibcon#[27=AT01-04\r\n] 2006.173.16:51:30.93#ibcon#*before write, iclass 40, count 2 2006.173.16:51:30.93#ibcon#enter sib2, iclass 40, count 2 2006.173.16:51:30.93#ibcon#flushed, iclass 40, count 2 2006.173.16:51:30.93#ibcon#about to write, iclass 40, count 2 2006.173.16:51:30.93#ibcon#wrote, iclass 40, count 2 2006.173.16:51:30.93#ibcon#about to read 3, iclass 40, count 2 2006.173.16:51:30.96#ibcon#read 3, iclass 40, count 2 2006.173.16:51:30.96#ibcon#about to read 4, iclass 40, count 2 2006.173.16:51:30.96#ibcon#read 4, iclass 40, count 2 2006.173.16:51:30.96#ibcon#about to read 5, iclass 40, count 2 2006.173.16:51:30.96#ibcon#read 5, iclass 40, count 2 2006.173.16:51:30.96#ibcon#about to read 6, iclass 40, count 2 2006.173.16:51:30.96#ibcon#read 6, iclass 40, count 2 2006.173.16:51:30.96#ibcon#end of sib2, iclass 40, count 2 2006.173.16:51:30.96#ibcon#*after write, iclass 40, count 2 2006.173.16:51:30.96#ibcon#*before return 0, iclass 40, count 2 2006.173.16:51:30.96#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.16:51:30.96#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.16:51:30.96#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.16:51:30.96#ibcon#ireg 7 cls_cnt 0 2006.173.16:51:30.96#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.16:51:31.08#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.16:51:31.08#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.16:51:31.08#ibcon#enter wrdev, iclass 40, count 0 2006.173.16:51:31.08#ibcon#first serial, iclass 40, count 0 2006.173.16:51:31.08#ibcon#enter sib2, iclass 40, count 0 2006.173.16:51:31.08#ibcon#flushed, iclass 40, count 0 2006.173.16:51:31.08#ibcon#about to write, iclass 40, count 0 2006.173.16:51:31.08#ibcon#wrote, iclass 40, count 0 2006.173.16:51:31.08#ibcon#about to read 3, iclass 40, count 0 2006.173.16:51:31.10#ibcon#read 3, iclass 40, count 0 2006.173.16:51:31.10#ibcon#about to read 4, iclass 40, count 0 2006.173.16:51:31.10#ibcon#read 4, iclass 40, count 0 2006.173.16:51:31.10#ibcon#about to read 5, iclass 40, count 0 2006.173.16:51:31.10#ibcon#read 5, iclass 40, count 0 2006.173.16:51:31.10#ibcon#about to read 6, iclass 40, count 0 2006.173.16:51:31.10#ibcon#read 6, iclass 40, count 0 2006.173.16:51:31.10#ibcon#end of sib2, iclass 40, count 0 2006.173.16:51:31.10#ibcon#*mode == 0, iclass 40, count 0 2006.173.16:51:31.10#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.16:51:31.10#ibcon#[27=USB\r\n] 2006.173.16:51:31.10#ibcon#*before write, iclass 40, count 0 2006.173.16:51:31.10#ibcon#enter sib2, iclass 40, count 0 2006.173.16:51:31.10#ibcon#flushed, iclass 40, count 0 2006.173.16:51:31.10#ibcon#about to write, iclass 40, count 0 2006.173.16:51:31.10#ibcon#wrote, iclass 40, count 0 2006.173.16:51:31.10#ibcon#about to read 3, iclass 40, count 0 2006.173.16:51:31.13#ibcon#read 3, iclass 40, count 0 2006.173.16:51:31.13#ibcon#about to read 4, iclass 40, count 0 2006.173.16:51:31.13#ibcon#read 4, iclass 40, count 0 2006.173.16:51:31.13#ibcon#about to read 5, iclass 40, count 0 2006.173.16:51:31.13#ibcon#read 5, iclass 40, count 0 2006.173.16:51:31.13#ibcon#about to read 6, iclass 40, count 0 2006.173.16:51:31.13#ibcon#read 6, iclass 40, count 0 2006.173.16:51:31.13#ibcon#end of sib2, iclass 40, count 0 2006.173.16:51:31.13#ibcon#*after write, iclass 40, count 0 2006.173.16:51:31.13#ibcon#*before return 0, iclass 40, count 0 2006.173.16:51:31.13#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.16:51:31.13#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.16:51:31.13#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.16:51:31.13#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.16:51:31.13$vck44/vblo=2,634.99 2006.173.16:51:31.13#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.16:51:31.13#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.16:51:31.13#ibcon#ireg 17 cls_cnt 0 2006.173.16:51:31.13#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.16:51:31.13#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.16:51:31.13#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.16:51:31.13#ibcon#enter wrdev, iclass 4, count 0 2006.173.16:51:31.13#ibcon#first serial, iclass 4, count 0 2006.173.16:51:31.13#ibcon#enter sib2, iclass 4, count 0 2006.173.16:51:31.13#ibcon#flushed, iclass 4, count 0 2006.173.16:51:31.13#ibcon#about to write, iclass 4, count 0 2006.173.16:51:31.13#ibcon#wrote, iclass 4, count 0 2006.173.16:51:31.13#ibcon#about to read 3, iclass 4, count 0 2006.173.16:51:31.15#ibcon#read 3, iclass 4, count 0 2006.173.16:51:31.15#ibcon#about to read 4, iclass 4, count 0 2006.173.16:51:31.15#ibcon#read 4, iclass 4, count 0 2006.173.16:51:31.15#ibcon#about to read 5, iclass 4, count 0 2006.173.16:51:31.15#ibcon#read 5, iclass 4, count 0 2006.173.16:51:31.15#ibcon#about to read 6, iclass 4, count 0 2006.173.16:51:31.15#ibcon#read 6, iclass 4, count 0 2006.173.16:51:31.15#ibcon#end of sib2, iclass 4, count 0 2006.173.16:51:31.15#ibcon#*mode == 0, iclass 4, count 0 2006.173.16:51:31.15#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.16:51:31.15#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.16:51:31.15#ibcon#*before write, iclass 4, count 0 2006.173.16:51:31.15#ibcon#enter sib2, iclass 4, count 0 2006.173.16:51:31.15#ibcon#flushed, iclass 4, count 0 2006.173.16:51:31.15#ibcon#about to write, iclass 4, count 0 2006.173.16:51:31.15#ibcon#wrote, iclass 4, count 0 2006.173.16:51:31.15#ibcon#about to read 3, iclass 4, count 0 2006.173.16:51:31.19#ibcon#read 3, iclass 4, count 0 2006.173.16:51:31.19#ibcon#about to read 4, iclass 4, count 0 2006.173.16:51:31.19#ibcon#read 4, iclass 4, count 0 2006.173.16:51:31.19#ibcon#about to read 5, iclass 4, count 0 2006.173.16:51:31.19#ibcon#read 5, iclass 4, count 0 2006.173.16:51:31.19#ibcon#about to read 6, iclass 4, count 0 2006.173.16:51:31.19#ibcon#read 6, iclass 4, count 0 2006.173.16:51:31.19#ibcon#end of sib2, iclass 4, count 0 2006.173.16:51:31.19#ibcon#*after write, iclass 4, count 0 2006.173.16:51:31.19#ibcon#*before return 0, iclass 4, count 0 2006.173.16:51:31.19#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.16:51:31.19#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.16:51:31.19#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.16:51:31.19#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.16:51:31.19$vck44/vb=2,4 2006.173.16:51:31.19#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.16:51:31.19#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.16:51:31.19#ibcon#ireg 11 cls_cnt 2 2006.173.16:51:31.19#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.16:51:31.25#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.16:51:31.25#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.16:51:31.25#ibcon#enter wrdev, iclass 6, count 2 2006.173.16:51:31.25#ibcon#first serial, iclass 6, count 2 2006.173.16:51:31.25#ibcon#enter sib2, iclass 6, count 2 2006.173.16:51:31.25#ibcon#flushed, iclass 6, count 2 2006.173.16:51:31.25#ibcon#about to write, iclass 6, count 2 2006.173.16:51:31.25#ibcon#wrote, iclass 6, count 2 2006.173.16:51:31.25#ibcon#about to read 3, iclass 6, count 2 2006.173.16:51:31.27#ibcon#read 3, iclass 6, count 2 2006.173.16:51:31.27#ibcon#about to read 4, iclass 6, count 2 2006.173.16:51:31.27#ibcon#read 4, iclass 6, count 2 2006.173.16:51:31.27#ibcon#about to read 5, iclass 6, count 2 2006.173.16:51:31.27#ibcon#read 5, iclass 6, count 2 2006.173.16:51:31.27#ibcon#about to read 6, iclass 6, count 2 2006.173.16:51:31.27#ibcon#read 6, iclass 6, count 2 2006.173.16:51:31.27#ibcon#end of sib2, iclass 6, count 2 2006.173.16:51:31.27#ibcon#*mode == 0, iclass 6, count 2 2006.173.16:51:31.27#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.16:51:31.27#ibcon#[27=AT02-04\r\n] 2006.173.16:51:31.27#ibcon#*before write, iclass 6, count 2 2006.173.16:51:31.27#ibcon#enter sib2, iclass 6, count 2 2006.173.16:51:31.27#ibcon#flushed, iclass 6, count 2 2006.173.16:51:31.27#ibcon#about to write, iclass 6, count 2 2006.173.16:51:31.27#ibcon#wrote, iclass 6, count 2 2006.173.16:51:31.27#ibcon#about to read 3, iclass 6, count 2 2006.173.16:51:31.30#ibcon#read 3, iclass 6, count 2 2006.173.16:51:31.30#ibcon#about to read 4, iclass 6, count 2 2006.173.16:51:31.30#ibcon#read 4, iclass 6, count 2 2006.173.16:51:31.30#ibcon#about to read 5, iclass 6, count 2 2006.173.16:51:31.30#ibcon#read 5, iclass 6, count 2 2006.173.16:51:31.30#ibcon#about to read 6, iclass 6, count 2 2006.173.16:51:31.30#ibcon#read 6, iclass 6, count 2 2006.173.16:51:31.30#ibcon#end of sib2, iclass 6, count 2 2006.173.16:51:31.30#ibcon#*after write, iclass 6, count 2 2006.173.16:51:31.30#ibcon#*before return 0, iclass 6, count 2 2006.173.16:51:31.30#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.16:51:31.30#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.16:51:31.30#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.16:51:31.30#ibcon#ireg 7 cls_cnt 0 2006.173.16:51:31.30#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.16:51:31.42#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.16:51:31.42#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.16:51:31.42#ibcon#enter wrdev, iclass 6, count 0 2006.173.16:51:31.42#ibcon#first serial, iclass 6, count 0 2006.173.16:51:31.42#ibcon#enter sib2, iclass 6, count 0 2006.173.16:51:31.42#ibcon#flushed, iclass 6, count 0 2006.173.16:51:31.42#ibcon#about to write, iclass 6, count 0 2006.173.16:51:31.42#ibcon#wrote, iclass 6, count 0 2006.173.16:51:31.42#ibcon#about to read 3, iclass 6, count 0 2006.173.16:51:31.44#ibcon#read 3, iclass 6, count 0 2006.173.16:51:31.44#ibcon#about to read 4, iclass 6, count 0 2006.173.16:51:31.44#ibcon#read 4, iclass 6, count 0 2006.173.16:51:31.44#ibcon#about to read 5, iclass 6, count 0 2006.173.16:51:31.44#ibcon#read 5, iclass 6, count 0 2006.173.16:51:31.44#ibcon#about to read 6, iclass 6, count 0 2006.173.16:51:31.44#ibcon#read 6, iclass 6, count 0 2006.173.16:51:31.44#ibcon#end of sib2, iclass 6, count 0 2006.173.16:51:31.44#ibcon#*mode == 0, iclass 6, count 0 2006.173.16:51:31.44#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.16:51:31.44#ibcon#[27=USB\r\n] 2006.173.16:51:31.44#ibcon#*before write, iclass 6, count 0 2006.173.16:51:31.44#ibcon#enter sib2, iclass 6, count 0 2006.173.16:51:31.44#ibcon#flushed, iclass 6, count 0 2006.173.16:51:31.44#ibcon#about to write, iclass 6, count 0 2006.173.16:51:31.44#ibcon#wrote, iclass 6, count 0 2006.173.16:51:31.44#ibcon#about to read 3, iclass 6, count 0 2006.173.16:51:31.47#ibcon#read 3, iclass 6, count 0 2006.173.16:51:31.47#ibcon#about to read 4, iclass 6, count 0 2006.173.16:51:31.47#ibcon#read 4, iclass 6, count 0 2006.173.16:51:31.47#ibcon#about to read 5, iclass 6, count 0 2006.173.16:51:31.47#ibcon#read 5, iclass 6, count 0 2006.173.16:51:31.47#ibcon#about to read 6, iclass 6, count 0 2006.173.16:51:31.47#ibcon#read 6, iclass 6, count 0 2006.173.16:51:31.47#ibcon#end of sib2, iclass 6, count 0 2006.173.16:51:31.47#ibcon#*after write, iclass 6, count 0 2006.173.16:51:31.47#ibcon#*before return 0, iclass 6, count 0 2006.173.16:51:31.47#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.16:51:31.47#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.16:51:31.47#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.16:51:31.47#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.16:51:31.47$vck44/vblo=3,649.99 2006.173.16:51:31.47#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.16:51:31.47#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.16:51:31.47#ibcon#ireg 17 cls_cnt 0 2006.173.16:51:31.47#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.16:51:31.47#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.16:51:31.47#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.16:51:31.47#ibcon#enter wrdev, iclass 10, count 0 2006.173.16:51:31.47#ibcon#first serial, iclass 10, count 0 2006.173.16:51:31.47#ibcon#enter sib2, iclass 10, count 0 2006.173.16:51:31.47#ibcon#flushed, iclass 10, count 0 2006.173.16:51:31.47#ibcon#about to write, iclass 10, count 0 2006.173.16:51:31.47#ibcon#wrote, iclass 10, count 0 2006.173.16:51:31.47#ibcon#about to read 3, iclass 10, count 0 2006.173.16:51:31.49#ibcon#read 3, iclass 10, count 0 2006.173.16:51:31.49#ibcon#about to read 4, iclass 10, count 0 2006.173.16:51:31.49#ibcon#read 4, iclass 10, count 0 2006.173.16:51:31.49#ibcon#about to read 5, iclass 10, count 0 2006.173.16:51:31.49#ibcon#read 5, iclass 10, count 0 2006.173.16:51:31.49#ibcon#about to read 6, iclass 10, count 0 2006.173.16:51:31.49#ibcon#read 6, iclass 10, count 0 2006.173.16:51:31.49#ibcon#end of sib2, iclass 10, count 0 2006.173.16:51:31.49#ibcon#*mode == 0, iclass 10, count 0 2006.173.16:51:31.49#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.16:51:31.49#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.16:51:31.49#ibcon#*before write, iclass 10, count 0 2006.173.16:51:31.49#ibcon#enter sib2, iclass 10, count 0 2006.173.16:51:31.49#ibcon#flushed, iclass 10, count 0 2006.173.16:51:31.49#ibcon#about to write, iclass 10, count 0 2006.173.16:51:31.49#ibcon#wrote, iclass 10, count 0 2006.173.16:51:31.49#ibcon#about to read 3, iclass 10, count 0 2006.173.16:51:31.53#ibcon#read 3, iclass 10, count 0 2006.173.16:51:31.53#ibcon#about to read 4, iclass 10, count 0 2006.173.16:51:31.53#ibcon#read 4, iclass 10, count 0 2006.173.16:51:31.53#ibcon#about to read 5, iclass 10, count 0 2006.173.16:51:31.53#ibcon#read 5, iclass 10, count 0 2006.173.16:51:31.53#ibcon#about to read 6, iclass 10, count 0 2006.173.16:51:31.53#ibcon#read 6, iclass 10, count 0 2006.173.16:51:31.53#ibcon#end of sib2, iclass 10, count 0 2006.173.16:51:31.53#ibcon#*after write, iclass 10, count 0 2006.173.16:51:31.53#ibcon#*before return 0, iclass 10, count 0 2006.173.16:51:31.53#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.16:51:31.53#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.16:51:31.53#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.16:51:31.53#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.16:51:31.53$vck44/vb=3,4 2006.173.16:51:31.53#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.16:51:31.53#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.16:51:31.53#ibcon#ireg 11 cls_cnt 2 2006.173.16:51:31.53#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.16:51:31.59#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.16:51:31.59#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.16:51:31.59#ibcon#enter wrdev, iclass 12, count 2 2006.173.16:51:31.59#ibcon#first serial, iclass 12, count 2 2006.173.16:51:31.59#ibcon#enter sib2, iclass 12, count 2 2006.173.16:51:31.59#ibcon#flushed, iclass 12, count 2 2006.173.16:51:31.59#ibcon#about to write, iclass 12, count 2 2006.173.16:51:31.59#ibcon#wrote, iclass 12, count 2 2006.173.16:51:31.59#ibcon#about to read 3, iclass 12, count 2 2006.173.16:51:31.61#ibcon#read 3, iclass 12, count 2 2006.173.16:51:31.61#ibcon#about to read 4, iclass 12, count 2 2006.173.16:51:31.61#ibcon#read 4, iclass 12, count 2 2006.173.16:51:31.61#ibcon#about to read 5, iclass 12, count 2 2006.173.16:51:31.61#ibcon#read 5, iclass 12, count 2 2006.173.16:51:31.61#ibcon#about to read 6, iclass 12, count 2 2006.173.16:51:31.61#ibcon#read 6, iclass 12, count 2 2006.173.16:51:31.61#ibcon#end of sib2, iclass 12, count 2 2006.173.16:51:31.61#ibcon#*mode == 0, iclass 12, count 2 2006.173.16:51:31.61#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.16:51:31.61#ibcon#[27=AT03-04\r\n] 2006.173.16:51:31.61#ibcon#*before write, iclass 12, count 2 2006.173.16:51:31.61#ibcon#enter sib2, iclass 12, count 2 2006.173.16:51:31.61#ibcon#flushed, iclass 12, count 2 2006.173.16:51:31.61#ibcon#about to write, iclass 12, count 2 2006.173.16:51:31.61#ibcon#wrote, iclass 12, count 2 2006.173.16:51:31.61#ibcon#about to read 3, iclass 12, count 2 2006.173.16:51:31.64#ibcon#read 3, iclass 12, count 2 2006.173.16:51:31.64#ibcon#about to read 4, iclass 12, count 2 2006.173.16:51:31.64#ibcon#read 4, iclass 12, count 2 2006.173.16:51:31.64#ibcon#about to read 5, iclass 12, count 2 2006.173.16:51:31.64#ibcon#read 5, iclass 12, count 2 2006.173.16:51:31.64#ibcon#about to read 6, iclass 12, count 2 2006.173.16:51:31.64#ibcon#read 6, iclass 12, count 2 2006.173.16:51:31.64#ibcon#end of sib2, iclass 12, count 2 2006.173.16:51:31.64#ibcon#*after write, iclass 12, count 2 2006.173.16:51:31.64#ibcon#*before return 0, iclass 12, count 2 2006.173.16:51:31.64#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.16:51:31.64#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.16:51:31.64#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.16:51:31.64#ibcon#ireg 7 cls_cnt 0 2006.173.16:51:31.64#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.16:51:31.76#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.16:51:31.76#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.16:51:31.76#ibcon#enter wrdev, iclass 12, count 0 2006.173.16:51:31.76#ibcon#first serial, iclass 12, count 0 2006.173.16:51:31.76#ibcon#enter sib2, iclass 12, count 0 2006.173.16:51:31.76#ibcon#flushed, iclass 12, count 0 2006.173.16:51:31.76#ibcon#about to write, iclass 12, count 0 2006.173.16:51:31.76#ibcon#wrote, iclass 12, count 0 2006.173.16:51:31.76#ibcon#about to read 3, iclass 12, count 0 2006.173.16:51:31.78#ibcon#read 3, iclass 12, count 0 2006.173.16:51:31.78#ibcon#about to read 4, iclass 12, count 0 2006.173.16:51:31.78#ibcon#read 4, iclass 12, count 0 2006.173.16:51:31.78#ibcon#about to read 5, iclass 12, count 0 2006.173.16:51:31.78#ibcon#read 5, iclass 12, count 0 2006.173.16:51:31.78#ibcon#about to read 6, iclass 12, count 0 2006.173.16:51:31.78#ibcon#read 6, iclass 12, count 0 2006.173.16:51:31.78#ibcon#end of sib2, iclass 12, count 0 2006.173.16:51:31.78#ibcon#*mode == 0, iclass 12, count 0 2006.173.16:51:31.78#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.16:51:31.78#ibcon#[27=USB\r\n] 2006.173.16:51:31.78#ibcon#*before write, iclass 12, count 0 2006.173.16:51:31.78#ibcon#enter sib2, iclass 12, count 0 2006.173.16:51:31.78#ibcon#flushed, iclass 12, count 0 2006.173.16:51:31.78#ibcon#about to write, iclass 12, count 0 2006.173.16:51:31.78#ibcon#wrote, iclass 12, count 0 2006.173.16:51:31.78#ibcon#about to read 3, iclass 12, count 0 2006.173.16:51:31.81#ibcon#read 3, iclass 12, count 0 2006.173.16:51:31.81#ibcon#about to read 4, iclass 12, count 0 2006.173.16:51:31.81#ibcon#read 4, iclass 12, count 0 2006.173.16:51:31.81#ibcon#about to read 5, iclass 12, count 0 2006.173.16:51:31.81#ibcon#read 5, iclass 12, count 0 2006.173.16:51:31.81#ibcon#about to read 6, iclass 12, count 0 2006.173.16:51:31.81#ibcon#read 6, iclass 12, count 0 2006.173.16:51:31.81#ibcon#end of sib2, iclass 12, count 0 2006.173.16:51:31.81#ibcon#*after write, iclass 12, count 0 2006.173.16:51:31.81#ibcon#*before return 0, iclass 12, count 0 2006.173.16:51:31.81#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.16:51:31.81#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.16:51:31.81#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.16:51:31.81#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.16:51:31.81$vck44/vblo=4,679.99 2006.173.16:51:31.81#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.16:51:31.81#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.16:51:31.81#ibcon#ireg 17 cls_cnt 0 2006.173.16:51:31.81#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.16:51:31.81#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.16:51:31.81#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.16:51:31.81#ibcon#enter wrdev, iclass 14, count 0 2006.173.16:51:31.81#ibcon#first serial, iclass 14, count 0 2006.173.16:51:31.81#ibcon#enter sib2, iclass 14, count 0 2006.173.16:51:31.81#ibcon#flushed, iclass 14, count 0 2006.173.16:51:31.81#ibcon#about to write, iclass 14, count 0 2006.173.16:51:31.81#ibcon#wrote, iclass 14, count 0 2006.173.16:51:31.81#ibcon#about to read 3, iclass 14, count 0 2006.173.16:51:31.83#ibcon#read 3, iclass 14, count 0 2006.173.16:51:31.83#ibcon#about to read 4, iclass 14, count 0 2006.173.16:51:31.83#ibcon#read 4, iclass 14, count 0 2006.173.16:51:31.83#ibcon#about to read 5, iclass 14, count 0 2006.173.16:51:31.83#ibcon#read 5, iclass 14, count 0 2006.173.16:51:31.83#ibcon#about to read 6, iclass 14, count 0 2006.173.16:51:31.83#ibcon#read 6, iclass 14, count 0 2006.173.16:51:31.83#ibcon#end of sib2, iclass 14, count 0 2006.173.16:51:31.83#ibcon#*mode == 0, iclass 14, count 0 2006.173.16:51:31.83#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.16:51:31.83#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.16:51:31.83#ibcon#*before write, iclass 14, count 0 2006.173.16:51:31.83#ibcon#enter sib2, iclass 14, count 0 2006.173.16:51:31.83#ibcon#flushed, iclass 14, count 0 2006.173.16:51:31.83#ibcon#about to write, iclass 14, count 0 2006.173.16:51:31.83#ibcon#wrote, iclass 14, count 0 2006.173.16:51:31.83#ibcon#about to read 3, iclass 14, count 0 2006.173.16:51:31.87#ibcon#read 3, iclass 14, count 0 2006.173.16:51:31.87#ibcon#about to read 4, iclass 14, count 0 2006.173.16:51:31.87#ibcon#read 4, iclass 14, count 0 2006.173.16:51:31.87#ibcon#about to read 5, iclass 14, count 0 2006.173.16:51:31.87#ibcon#read 5, iclass 14, count 0 2006.173.16:51:31.87#ibcon#about to read 6, iclass 14, count 0 2006.173.16:51:31.87#ibcon#read 6, iclass 14, count 0 2006.173.16:51:31.87#ibcon#end of sib2, iclass 14, count 0 2006.173.16:51:31.87#ibcon#*after write, iclass 14, count 0 2006.173.16:51:31.87#ibcon#*before return 0, iclass 14, count 0 2006.173.16:51:31.87#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.16:51:31.87#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.16:51:31.87#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.16:51:31.87#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.16:51:31.87$vck44/vb=4,4 2006.173.16:51:31.87#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.16:51:31.87#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.16:51:31.87#ibcon#ireg 11 cls_cnt 2 2006.173.16:51:31.87#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.16:51:31.93#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.16:51:31.93#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.16:51:31.93#ibcon#enter wrdev, iclass 16, count 2 2006.173.16:51:31.93#ibcon#first serial, iclass 16, count 2 2006.173.16:51:31.93#ibcon#enter sib2, iclass 16, count 2 2006.173.16:51:31.93#ibcon#flushed, iclass 16, count 2 2006.173.16:51:31.93#ibcon#about to write, iclass 16, count 2 2006.173.16:51:31.93#ibcon#wrote, iclass 16, count 2 2006.173.16:51:31.93#ibcon#about to read 3, iclass 16, count 2 2006.173.16:51:31.95#ibcon#read 3, iclass 16, count 2 2006.173.16:51:31.95#ibcon#about to read 4, iclass 16, count 2 2006.173.16:51:31.95#ibcon#read 4, iclass 16, count 2 2006.173.16:51:31.95#ibcon#about to read 5, iclass 16, count 2 2006.173.16:51:31.95#ibcon#read 5, iclass 16, count 2 2006.173.16:51:31.95#ibcon#about to read 6, iclass 16, count 2 2006.173.16:51:31.95#ibcon#read 6, iclass 16, count 2 2006.173.16:51:31.95#ibcon#end of sib2, iclass 16, count 2 2006.173.16:51:31.95#ibcon#*mode == 0, iclass 16, count 2 2006.173.16:51:31.95#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.16:51:31.95#ibcon#[27=AT04-04\r\n] 2006.173.16:51:31.95#ibcon#*before write, iclass 16, count 2 2006.173.16:51:31.95#ibcon#enter sib2, iclass 16, count 2 2006.173.16:51:31.95#ibcon#flushed, iclass 16, count 2 2006.173.16:51:31.95#ibcon#about to write, iclass 16, count 2 2006.173.16:51:31.95#ibcon#wrote, iclass 16, count 2 2006.173.16:51:31.95#ibcon#about to read 3, iclass 16, count 2 2006.173.16:51:31.98#ibcon#read 3, iclass 16, count 2 2006.173.16:51:31.98#ibcon#about to read 4, iclass 16, count 2 2006.173.16:51:31.98#ibcon#read 4, iclass 16, count 2 2006.173.16:51:31.98#ibcon#about to read 5, iclass 16, count 2 2006.173.16:51:31.98#ibcon#read 5, iclass 16, count 2 2006.173.16:51:31.98#ibcon#about to read 6, iclass 16, count 2 2006.173.16:51:31.98#ibcon#read 6, iclass 16, count 2 2006.173.16:51:31.98#ibcon#end of sib2, iclass 16, count 2 2006.173.16:51:31.98#ibcon#*after write, iclass 16, count 2 2006.173.16:51:31.98#ibcon#*before return 0, iclass 16, count 2 2006.173.16:51:31.98#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.16:51:31.98#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.16:51:31.98#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.16:51:31.98#ibcon#ireg 7 cls_cnt 0 2006.173.16:51:31.98#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.16:51:32.10#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.16:51:32.10#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.16:51:32.10#ibcon#enter wrdev, iclass 16, count 0 2006.173.16:51:32.10#ibcon#first serial, iclass 16, count 0 2006.173.16:51:32.10#ibcon#enter sib2, iclass 16, count 0 2006.173.16:51:32.10#ibcon#flushed, iclass 16, count 0 2006.173.16:51:32.10#ibcon#about to write, iclass 16, count 0 2006.173.16:51:32.10#ibcon#wrote, iclass 16, count 0 2006.173.16:51:32.10#ibcon#about to read 3, iclass 16, count 0 2006.173.16:51:32.12#ibcon#read 3, iclass 16, count 0 2006.173.16:51:32.12#ibcon#about to read 4, iclass 16, count 0 2006.173.16:51:32.12#ibcon#read 4, iclass 16, count 0 2006.173.16:51:32.12#ibcon#about to read 5, iclass 16, count 0 2006.173.16:51:32.12#ibcon#read 5, iclass 16, count 0 2006.173.16:51:32.12#ibcon#about to read 6, iclass 16, count 0 2006.173.16:51:32.12#ibcon#read 6, iclass 16, count 0 2006.173.16:51:32.12#ibcon#end of sib2, iclass 16, count 0 2006.173.16:51:32.12#ibcon#*mode == 0, iclass 16, count 0 2006.173.16:51:32.12#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.16:51:32.12#ibcon#[27=USB\r\n] 2006.173.16:51:32.12#ibcon#*before write, iclass 16, count 0 2006.173.16:51:32.12#ibcon#enter sib2, iclass 16, count 0 2006.173.16:51:32.12#ibcon#flushed, iclass 16, count 0 2006.173.16:51:32.12#ibcon#about to write, iclass 16, count 0 2006.173.16:51:32.12#ibcon#wrote, iclass 16, count 0 2006.173.16:51:32.12#ibcon#about to read 3, iclass 16, count 0 2006.173.16:51:32.15#ibcon#read 3, iclass 16, count 0 2006.173.16:51:32.15#ibcon#about to read 4, iclass 16, count 0 2006.173.16:51:32.15#ibcon#read 4, iclass 16, count 0 2006.173.16:51:32.15#ibcon#about to read 5, iclass 16, count 0 2006.173.16:51:32.15#ibcon#read 5, iclass 16, count 0 2006.173.16:51:32.15#ibcon#about to read 6, iclass 16, count 0 2006.173.16:51:32.15#ibcon#read 6, iclass 16, count 0 2006.173.16:51:32.15#ibcon#end of sib2, iclass 16, count 0 2006.173.16:51:32.15#ibcon#*after write, iclass 16, count 0 2006.173.16:51:32.15#ibcon#*before return 0, iclass 16, count 0 2006.173.16:51:32.15#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.16:51:32.15#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.16:51:32.15#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.16:51:32.15#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.16:51:32.15$vck44/vblo=5,709.99 2006.173.16:51:32.15#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.16:51:32.15#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.16:51:32.15#ibcon#ireg 17 cls_cnt 0 2006.173.16:51:32.15#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.16:51:32.15#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.16:51:32.15#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.16:51:32.15#ibcon#enter wrdev, iclass 18, count 0 2006.173.16:51:32.15#ibcon#first serial, iclass 18, count 0 2006.173.16:51:32.15#ibcon#enter sib2, iclass 18, count 0 2006.173.16:51:32.15#ibcon#flushed, iclass 18, count 0 2006.173.16:51:32.15#ibcon#about to write, iclass 18, count 0 2006.173.16:51:32.15#ibcon#wrote, iclass 18, count 0 2006.173.16:51:32.15#ibcon#about to read 3, iclass 18, count 0 2006.173.16:51:32.17#ibcon#read 3, iclass 18, count 0 2006.173.16:51:32.17#ibcon#about to read 4, iclass 18, count 0 2006.173.16:51:32.17#ibcon#read 4, iclass 18, count 0 2006.173.16:51:32.17#ibcon#about to read 5, iclass 18, count 0 2006.173.16:51:32.17#ibcon#read 5, iclass 18, count 0 2006.173.16:51:32.17#ibcon#about to read 6, iclass 18, count 0 2006.173.16:51:32.17#ibcon#read 6, iclass 18, count 0 2006.173.16:51:32.17#ibcon#end of sib2, iclass 18, count 0 2006.173.16:51:32.17#ibcon#*mode == 0, iclass 18, count 0 2006.173.16:51:32.17#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.16:51:32.17#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.16:51:32.17#ibcon#*before write, iclass 18, count 0 2006.173.16:51:32.17#ibcon#enter sib2, iclass 18, count 0 2006.173.16:51:32.17#ibcon#flushed, iclass 18, count 0 2006.173.16:51:32.17#ibcon#about to write, iclass 18, count 0 2006.173.16:51:32.17#ibcon#wrote, iclass 18, count 0 2006.173.16:51:32.17#ibcon#about to read 3, iclass 18, count 0 2006.173.16:51:32.21#ibcon#read 3, iclass 18, count 0 2006.173.16:51:32.21#ibcon#about to read 4, iclass 18, count 0 2006.173.16:51:32.21#ibcon#read 4, iclass 18, count 0 2006.173.16:51:32.21#ibcon#about to read 5, iclass 18, count 0 2006.173.16:51:32.21#ibcon#read 5, iclass 18, count 0 2006.173.16:51:32.21#ibcon#about to read 6, iclass 18, count 0 2006.173.16:51:32.21#ibcon#read 6, iclass 18, count 0 2006.173.16:51:32.21#ibcon#end of sib2, iclass 18, count 0 2006.173.16:51:32.21#ibcon#*after write, iclass 18, count 0 2006.173.16:51:32.21#ibcon#*before return 0, iclass 18, count 0 2006.173.16:51:32.21#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.16:51:32.21#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.16:51:32.21#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.16:51:32.21#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.16:51:32.21$vck44/vb=5,4 2006.173.16:51:32.21#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.16:51:32.21#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.16:51:32.21#ibcon#ireg 11 cls_cnt 2 2006.173.16:51:32.21#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.16:51:32.27#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.16:51:32.27#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.16:51:32.27#ibcon#enter wrdev, iclass 20, count 2 2006.173.16:51:32.27#ibcon#first serial, iclass 20, count 2 2006.173.16:51:32.27#ibcon#enter sib2, iclass 20, count 2 2006.173.16:51:32.27#ibcon#flushed, iclass 20, count 2 2006.173.16:51:32.27#ibcon#about to write, iclass 20, count 2 2006.173.16:51:32.27#ibcon#wrote, iclass 20, count 2 2006.173.16:51:32.27#ibcon#about to read 3, iclass 20, count 2 2006.173.16:51:32.29#ibcon#read 3, iclass 20, count 2 2006.173.16:51:32.29#ibcon#about to read 4, iclass 20, count 2 2006.173.16:51:32.29#ibcon#read 4, iclass 20, count 2 2006.173.16:51:32.29#ibcon#about to read 5, iclass 20, count 2 2006.173.16:51:32.29#ibcon#read 5, iclass 20, count 2 2006.173.16:51:32.29#ibcon#about to read 6, iclass 20, count 2 2006.173.16:51:32.29#ibcon#read 6, iclass 20, count 2 2006.173.16:51:32.29#ibcon#end of sib2, iclass 20, count 2 2006.173.16:51:32.29#ibcon#*mode == 0, iclass 20, count 2 2006.173.16:51:32.29#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.16:51:32.29#ibcon#[27=AT05-04\r\n] 2006.173.16:51:32.29#ibcon#*before write, iclass 20, count 2 2006.173.16:51:32.29#ibcon#enter sib2, iclass 20, count 2 2006.173.16:51:32.29#ibcon#flushed, iclass 20, count 2 2006.173.16:51:32.29#ibcon#about to write, iclass 20, count 2 2006.173.16:51:32.29#ibcon#wrote, iclass 20, count 2 2006.173.16:51:32.29#ibcon#about to read 3, iclass 20, count 2 2006.173.16:51:32.32#ibcon#read 3, iclass 20, count 2 2006.173.16:51:32.32#ibcon#about to read 4, iclass 20, count 2 2006.173.16:51:32.32#ibcon#read 4, iclass 20, count 2 2006.173.16:51:32.32#ibcon#about to read 5, iclass 20, count 2 2006.173.16:51:32.32#ibcon#read 5, iclass 20, count 2 2006.173.16:51:32.32#ibcon#about to read 6, iclass 20, count 2 2006.173.16:51:32.32#ibcon#read 6, iclass 20, count 2 2006.173.16:51:32.32#ibcon#end of sib2, iclass 20, count 2 2006.173.16:51:32.32#ibcon#*after write, iclass 20, count 2 2006.173.16:51:32.32#ibcon#*before return 0, iclass 20, count 2 2006.173.16:51:32.32#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.16:51:32.32#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.16:51:32.32#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.16:51:32.32#ibcon#ireg 7 cls_cnt 0 2006.173.16:51:32.32#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.16:51:32.44#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.16:51:32.44#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.16:51:32.44#ibcon#enter wrdev, iclass 20, count 0 2006.173.16:51:32.44#ibcon#first serial, iclass 20, count 0 2006.173.16:51:32.44#ibcon#enter sib2, iclass 20, count 0 2006.173.16:51:32.44#ibcon#flushed, iclass 20, count 0 2006.173.16:51:32.44#ibcon#about to write, iclass 20, count 0 2006.173.16:51:32.44#ibcon#wrote, iclass 20, count 0 2006.173.16:51:32.44#ibcon#about to read 3, iclass 20, count 0 2006.173.16:51:32.46#ibcon#read 3, iclass 20, count 0 2006.173.16:51:32.46#ibcon#about to read 4, iclass 20, count 0 2006.173.16:51:32.46#ibcon#read 4, iclass 20, count 0 2006.173.16:51:32.46#ibcon#about to read 5, iclass 20, count 0 2006.173.16:51:32.46#ibcon#read 5, iclass 20, count 0 2006.173.16:51:32.46#ibcon#about to read 6, iclass 20, count 0 2006.173.16:51:32.46#ibcon#read 6, iclass 20, count 0 2006.173.16:51:32.46#ibcon#end of sib2, iclass 20, count 0 2006.173.16:51:32.46#ibcon#*mode == 0, iclass 20, count 0 2006.173.16:51:32.46#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.16:51:32.46#ibcon#[27=USB\r\n] 2006.173.16:51:32.46#ibcon#*before write, iclass 20, count 0 2006.173.16:51:32.46#ibcon#enter sib2, iclass 20, count 0 2006.173.16:51:32.46#ibcon#flushed, iclass 20, count 0 2006.173.16:51:32.46#ibcon#about to write, iclass 20, count 0 2006.173.16:51:32.46#ibcon#wrote, iclass 20, count 0 2006.173.16:51:32.46#ibcon#about to read 3, iclass 20, count 0 2006.173.16:51:32.49#ibcon#read 3, iclass 20, count 0 2006.173.16:51:32.49#ibcon#about to read 4, iclass 20, count 0 2006.173.16:51:32.49#ibcon#read 4, iclass 20, count 0 2006.173.16:51:32.49#ibcon#about to read 5, iclass 20, count 0 2006.173.16:51:32.49#ibcon#read 5, iclass 20, count 0 2006.173.16:51:32.49#ibcon#about to read 6, iclass 20, count 0 2006.173.16:51:32.49#ibcon#read 6, iclass 20, count 0 2006.173.16:51:32.49#ibcon#end of sib2, iclass 20, count 0 2006.173.16:51:32.49#ibcon#*after write, iclass 20, count 0 2006.173.16:51:32.49#ibcon#*before return 0, iclass 20, count 0 2006.173.16:51:32.49#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.16:51:32.49#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.16:51:32.49#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.16:51:32.49#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.16:51:32.49$vck44/vblo=6,719.99 2006.173.16:51:32.49#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.16:51:32.49#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.16:51:32.49#ibcon#ireg 17 cls_cnt 0 2006.173.16:51:32.49#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.16:51:32.49#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.16:51:32.49#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.16:51:32.49#ibcon#enter wrdev, iclass 22, count 0 2006.173.16:51:32.49#ibcon#first serial, iclass 22, count 0 2006.173.16:51:32.49#ibcon#enter sib2, iclass 22, count 0 2006.173.16:51:32.49#ibcon#flushed, iclass 22, count 0 2006.173.16:51:32.49#ibcon#about to write, iclass 22, count 0 2006.173.16:51:32.49#ibcon#wrote, iclass 22, count 0 2006.173.16:51:32.49#ibcon#about to read 3, iclass 22, count 0 2006.173.16:51:32.51#ibcon#read 3, iclass 22, count 0 2006.173.16:51:32.51#ibcon#about to read 4, iclass 22, count 0 2006.173.16:51:32.51#ibcon#read 4, iclass 22, count 0 2006.173.16:51:32.51#ibcon#about to read 5, iclass 22, count 0 2006.173.16:51:32.51#ibcon#read 5, iclass 22, count 0 2006.173.16:51:32.51#ibcon#about to read 6, iclass 22, count 0 2006.173.16:51:32.51#ibcon#read 6, iclass 22, count 0 2006.173.16:51:32.51#ibcon#end of sib2, iclass 22, count 0 2006.173.16:51:32.51#ibcon#*mode == 0, iclass 22, count 0 2006.173.16:51:32.51#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.16:51:32.51#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.16:51:32.51#ibcon#*before write, iclass 22, count 0 2006.173.16:51:32.51#ibcon#enter sib2, iclass 22, count 0 2006.173.16:51:32.51#ibcon#flushed, iclass 22, count 0 2006.173.16:51:32.51#ibcon#about to write, iclass 22, count 0 2006.173.16:51:32.51#ibcon#wrote, iclass 22, count 0 2006.173.16:51:32.51#ibcon#about to read 3, iclass 22, count 0 2006.173.16:51:32.55#ibcon#read 3, iclass 22, count 0 2006.173.16:51:32.55#ibcon#about to read 4, iclass 22, count 0 2006.173.16:51:32.55#ibcon#read 4, iclass 22, count 0 2006.173.16:51:32.55#ibcon#about to read 5, iclass 22, count 0 2006.173.16:51:32.55#ibcon#read 5, iclass 22, count 0 2006.173.16:51:32.55#ibcon#about to read 6, iclass 22, count 0 2006.173.16:51:32.55#ibcon#read 6, iclass 22, count 0 2006.173.16:51:32.55#ibcon#end of sib2, iclass 22, count 0 2006.173.16:51:32.55#ibcon#*after write, iclass 22, count 0 2006.173.16:51:32.55#ibcon#*before return 0, iclass 22, count 0 2006.173.16:51:32.55#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.16:51:32.55#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.16:51:32.55#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.16:51:32.55#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.16:51:32.55$vck44/vb=6,4 2006.173.16:51:32.55#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.16:51:32.55#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.16:51:32.55#ibcon#ireg 11 cls_cnt 2 2006.173.16:51:32.55#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.16:51:32.61#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.16:51:32.61#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.16:51:32.61#ibcon#enter wrdev, iclass 24, count 2 2006.173.16:51:32.61#ibcon#first serial, iclass 24, count 2 2006.173.16:51:32.61#ibcon#enter sib2, iclass 24, count 2 2006.173.16:51:32.61#ibcon#flushed, iclass 24, count 2 2006.173.16:51:32.61#ibcon#about to write, iclass 24, count 2 2006.173.16:51:32.61#ibcon#wrote, iclass 24, count 2 2006.173.16:51:32.61#ibcon#about to read 3, iclass 24, count 2 2006.173.16:51:32.63#ibcon#read 3, iclass 24, count 2 2006.173.16:51:32.63#ibcon#about to read 4, iclass 24, count 2 2006.173.16:51:32.63#ibcon#read 4, iclass 24, count 2 2006.173.16:51:32.63#ibcon#about to read 5, iclass 24, count 2 2006.173.16:51:32.63#ibcon#read 5, iclass 24, count 2 2006.173.16:51:32.63#ibcon#about to read 6, iclass 24, count 2 2006.173.16:51:32.63#ibcon#read 6, iclass 24, count 2 2006.173.16:51:32.63#ibcon#end of sib2, iclass 24, count 2 2006.173.16:51:32.63#ibcon#*mode == 0, iclass 24, count 2 2006.173.16:51:32.63#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.16:51:32.63#ibcon#[27=AT06-04\r\n] 2006.173.16:51:32.63#ibcon#*before write, iclass 24, count 2 2006.173.16:51:32.63#ibcon#enter sib2, iclass 24, count 2 2006.173.16:51:32.63#ibcon#flushed, iclass 24, count 2 2006.173.16:51:32.63#ibcon#about to write, iclass 24, count 2 2006.173.16:51:32.63#ibcon#wrote, iclass 24, count 2 2006.173.16:51:32.63#ibcon#about to read 3, iclass 24, count 2 2006.173.16:51:32.66#ibcon#read 3, iclass 24, count 2 2006.173.16:51:32.66#ibcon#about to read 4, iclass 24, count 2 2006.173.16:51:32.66#ibcon#read 4, iclass 24, count 2 2006.173.16:51:32.66#ibcon#about to read 5, iclass 24, count 2 2006.173.16:51:32.66#ibcon#read 5, iclass 24, count 2 2006.173.16:51:32.66#ibcon#about to read 6, iclass 24, count 2 2006.173.16:51:32.66#ibcon#read 6, iclass 24, count 2 2006.173.16:51:32.66#ibcon#end of sib2, iclass 24, count 2 2006.173.16:51:32.66#ibcon#*after write, iclass 24, count 2 2006.173.16:51:32.66#ibcon#*before return 0, iclass 24, count 2 2006.173.16:51:32.66#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.16:51:32.66#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.16:51:32.66#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.16:51:32.66#ibcon#ireg 7 cls_cnt 0 2006.173.16:51:32.66#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.16:51:32.78#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.16:51:32.78#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.16:51:32.78#ibcon#enter wrdev, iclass 24, count 0 2006.173.16:51:32.78#ibcon#first serial, iclass 24, count 0 2006.173.16:51:32.78#ibcon#enter sib2, iclass 24, count 0 2006.173.16:51:32.78#ibcon#flushed, iclass 24, count 0 2006.173.16:51:32.78#ibcon#about to write, iclass 24, count 0 2006.173.16:51:32.78#ibcon#wrote, iclass 24, count 0 2006.173.16:51:32.78#ibcon#about to read 3, iclass 24, count 0 2006.173.16:51:32.80#ibcon#read 3, iclass 24, count 0 2006.173.16:51:32.80#ibcon#about to read 4, iclass 24, count 0 2006.173.16:51:32.80#ibcon#read 4, iclass 24, count 0 2006.173.16:51:32.80#ibcon#about to read 5, iclass 24, count 0 2006.173.16:51:32.80#ibcon#read 5, iclass 24, count 0 2006.173.16:51:32.80#ibcon#about to read 6, iclass 24, count 0 2006.173.16:51:32.80#ibcon#read 6, iclass 24, count 0 2006.173.16:51:32.80#ibcon#end of sib2, iclass 24, count 0 2006.173.16:51:32.80#ibcon#*mode == 0, iclass 24, count 0 2006.173.16:51:32.80#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.16:51:32.80#ibcon#[27=USB\r\n] 2006.173.16:51:32.80#ibcon#*before write, iclass 24, count 0 2006.173.16:51:32.80#ibcon#enter sib2, iclass 24, count 0 2006.173.16:51:32.80#ibcon#flushed, iclass 24, count 0 2006.173.16:51:32.80#ibcon#about to write, iclass 24, count 0 2006.173.16:51:32.80#ibcon#wrote, iclass 24, count 0 2006.173.16:51:32.80#ibcon#about to read 3, iclass 24, count 0 2006.173.16:51:32.83#ibcon#read 3, iclass 24, count 0 2006.173.16:51:32.83#ibcon#about to read 4, iclass 24, count 0 2006.173.16:51:32.83#ibcon#read 4, iclass 24, count 0 2006.173.16:51:32.83#ibcon#about to read 5, iclass 24, count 0 2006.173.16:51:32.83#ibcon#read 5, iclass 24, count 0 2006.173.16:51:32.83#ibcon#about to read 6, iclass 24, count 0 2006.173.16:51:32.83#ibcon#read 6, iclass 24, count 0 2006.173.16:51:32.83#ibcon#end of sib2, iclass 24, count 0 2006.173.16:51:32.83#ibcon#*after write, iclass 24, count 0 2006.173.16:51:32.83#ibcon#*before return 0, iclass 24, count 0 2006.173.16:51:32.83#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.16:51:32.83#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.16:51:32.83#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.16:51:32.83#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.16:51:32.83$vck44/vblo=7,734.99 2006.173.16:51:32.83#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.16:51:32.83#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.16:51:32.83#ibcon#ireg 17 cls_cnt 0 2006.173.16:51:32.83#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.16:51:32.83#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.16:51:32.83#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.16:51:32.83#ibcon#enter wrdev, iclass 26, count 0 2006.173.16:51:32.83#ibcon#first serial, iclass 26, count 0 2006.173.16:51:32.83#ibcon#enter sib2, iclass 26, count 0 2006.173.16:51:32.83#ibcon#flushed, iclass 26, count 0 2006.173.16:51:32.83#ibcon#about to write, iclass 26, count 0 2006.173.16:51:32.83#ibcon#wrote, iclass 26, count 0 2006.173.16:51:32.83#ibcon#about to read 3, iclass 26, count 0 2006.173.16:51:32.85#ibcon#read 3, iclass 26, count 0 2006.173.16:51:32.85#ibcon#about to read 4, iclass 26, count 0 2006.173.16:51:32.85#ibcon#read 4, iclass 26, count 0 2006.173.16:51:32.85#ibcon#about to read 5, iclass 26, count 0 2006.173.16:51:32.85#ibcon#read 5, iclass 26, count 0 2006.173.16:51:32.85#ibcon#about to read 6, iclass 26, count 0 2006.173.16:51:32.85#ibcon#read 6, iclass 26, count 0 2006.173.16:51:32.85#ibcon#end of sib2, iclass 26, count 0 2006.173.16:51:32.85#ibcon#*mode == 0, iclass 26, count 0 2006.173.16:51:32.85#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.16:51:32.85#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.16:51:32.85#ibcon#*before write, iclass 26, count 0 2006.173.16:51:32.85#ibcon#enter sib2, iclass 26, count 0 2006.173.16:51:32.85#ibcon#flushed, iclass 26, count 0 2006.173.16:51:32.85#ibcon#about to write, iclass 26, count 0 2006.173.16:51:32.85#ibcon#wrote, iclass 26, count 0 2006.173.16:51:32.85#ibcon#about to read 3, iclass 26, count 0 2006.173.16:51:32.89#ibcon#read 3, iclass 26, count 0 2006.173.16:51:32.89#ibcon#about to read 4, iclass 26, count 0 2006.173.16:51:32.89#ibcon#read 4, iclass 26, count 0 2006.173.16:51:32.89#ibcon#about to read 5, iclass 26, count 0 2006.173.16:51:32.89#ibcon#read 5, iclass 26, count 0 2006.173.16:51:32.89#ibcon#about to read 6, iclass 26, count 0 2006.173.16:51:32.89#ibcon#read 6, iclass 26, count 0 2006.173.16:51:32.89#ibcon#end of sib2, iclass 26, count 0 2006.173.16:51:32.89#ibcon#*after write, iclass 26, count 0 2006.173.16:51:32.89#ibcon#*before return 0, iclass 26, count 0 2006.173.16:51:32.89#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.16:51:32.89#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.16:51:32.89#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.16:51:32.89#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.16:51:32.89$vck44/vb=7,4 2006.173.16:51:32.89#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.16:51:32.89#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.16:51:32.89#ibcon#ireg 11 cls_cnt 2 2006.173.16:51:32.89#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.16:51:32.95#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.16:51:32.95#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.16:51:32.95#ibcon#enter wrdev, iclass 28, count 2 2006.173.16:51:32.95#ibcon#first serial, iclass 28, count 2 2006.173.16:51:32.95#ibcon#enter sib2, iclass 28, count 2 2006.173.16:51:32.95#ibcon#flushed, iclass 28, count 2 2006.173.16:51:32.95#ibcon#about to write, iclass 28, count 2 2006.173.16:51:32.95#ibcon#wrote, iclass 28, count 2 2006.173.16:51:32.95#ibcon#about to read 3, iclass 28, count 2 2006.173.16:51:32.97#ibcon#read 3, iclass 28, count 2 2006.173.16:51:32.97#ibcon#about to read 4, iclass 28, count 2 2006.173.16:51:32.97#ibcon#read 4, iclass 28, count 2 2006.173.16:51:32.97#ibcon#about to read 5, iclass 28, count 2 2006.173.16:51:32.97#ibcon#read 5, iclass 28, count 2 2006.173.16:51:32.97#ibcon#about to read 6, iclass 28, count 2 2006.173.16:51:32.97#ibcon#read 6, iclass 28, count 2 2006.173.16:51:32.97#ibcon#end of sib2, iclass 28, count 2 2006.173.16:51:32.97#ibcon#*mode == 0, iclass 28, count 2 2006.173.16:51:32.97#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.16:51:32.97#ibcon#[27=AT07-04\r\n] 2006.173.16:51:32.97#ibcon#*before write, iclass 28, count 2 2006.173.16:51:32.97#ibcon#enter sib2, iclass 28, count 2 2006.173.16:51:32.97#ibcon#flushed, iclass 28, count 2 2006.173.16:51:32.97#ibcon#about to write, iclass 28, count 2 2006.173.16:51:32.97#ibcon#wrote, iclass 28, count 2 2006.173.16:51:32.97#ibcon#about to read 3, iclass 28, count 2 2006.173.16:51:33.00#ibcon#read 3, iclass 28, count 2 2006.173.16:51:33.00#ibcon#about to read 4, iclass 28, count 2 2006.173.16:51:33.00#ibcon#read 4, iclass 28, count 2 2006.173.16:51:33.00#ibcon#about to read 5, iclass 28, count 2 2006.173.16:51:33.00#ibcon#read 5, iclass 28, count 2 2006.173.16:51:33.00#ibcon#about to read 6, iclass 28, count 2 2006.173.16:51:33.00#ibcon#read 6, iclass 28, count 2 2006.173.16:51:33.00#ibcon#end of sib2, iclass 28, count 2 2006.173.16:51:33.00#ibcon#*after write, iclass 28, count 2 2006.173.16:51:33.00#ibcon#*before return 0, iclass 28, count 2 2006.173.16:51:33.00#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.16:51:33.00#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.16:51:33.00#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.16:51:33.00#ibcon#ireg 7 cls_cnt 0 2006.173.16:51:33.00#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.16:51:33.12#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.16:51:33.12#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.16:51:33.12#ibcon#enter wrdev, iclass 28, count 0 2006.173.16:51:33.12#ibcon#first serial, iclass 28, count 0 2006.173.16:51:33.12#ibcon#enter sib2, iclass 28, count 0 2006.173.16:51:33.12#ibcon#flushed, iclass 28, count 0 2006.173.16:51:33.12#ibcon#about to write, iclass 28, count 0 2006.173.16:51:33.12#ibcon#wrote, iclass 28, count 0 2006.173.16:51:33.12#ibcon#about to read 3, iclass 28, count 0 2006.173.16:51:33.14#ibcon#read 3, iclass 28, count 0 2006.173.16:51:33.14#ibcon#about to read 4, iclass 28, count 0 2006.173.16:51:33.14#ibcon#read 4, iclass 28, count 0 2006.173.16:51:33.14#ibcon#about to read 5, iclass 28, count 0 2006.173.16:51:33.14#ibcon#read 5, iclass 28, count 0 2006.173.16:51:33.14#ibcon#about to read 6, iclass 28, count 0 2006.173.16:51:33.14#ibcon#read 6, iclass 28, count 0 2006.173.16:51:33.14#ibcon#end of sib2, iclass 28, count 0 2006.173.16:51:33.14#ibcon#*mode == 0, iclass 28, count 0 2006.173.16:51:33.14#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.16:51:33.14#ibcon#[27=USB\r\n] 2006.173.16:51:33.14#ibcon#*before write, iclass 28, count 0 2006.173.16:51:33.14#ibcon#enter sib2, iclass 28, count 0 2006.173.16:51:33.14#ibcon#flushed, iclass 28, count 0 2006.173.16:51:33.14#ibcon#about to write, iclass 28, count 0 2006.173.16:51:33.14#ibcon#wrote, iclass 28, count 0 2006.173.16:51:33.14#ibcon#about to read 3, iclass 28, count 0 2006.173.16:51:33.17#ibcon#read 3, iclass 28, count 0 2006.173.16:51:33.17#ibcon#about to read 4, iclass 28, count 0 2006.173.16:51:33.17#ibcon#read 4, iclass 28, count 0 2006.173.16:51:33.17#ibcon#about to read 5, iclass 28, count 0 2006.173.16:51:33.17#ibcon#read 5, iclass 28, count 0 2006.173.16:51:33.17#ibcon#about to read 6, iclass 28, count 0 2006.173.16:51:33.17#ibcon#read 6, iclass 28, count 0 2006.173.16:51:33.17#ibcon#end of sib2, iclass 28, count 0 2006.173.16:51:33.17#ibcon#*after write, iclass 28, count 0 2006.173.16:51:33.17#ibcon#*before return 0, iclass 28, count 0 2006.173.16:51:33.17#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.16:51:33.17#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.16:51:33.17#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.16:51:33.17#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.16:51:33.17$vck44/vblo=8,744.99 2006.173.16:51:33.17#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.16:51:33.17#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.16:51:33.17#ibcon#ireg 17 cls_cnt 0 2006.173.16:51:33.17#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.16:51:33.17#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.16:51:33.17#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.16:51:33.17#ibcon#enter wrdev, iclass 30, count 0 2006.173.16:51:33.17#ibcon#first serial, iclass 30, count 0 2006.173.16:51:33.17#ibcon#enter sib2, iclass 30, count 0 2006.173.16:51:33.17#ibcon#flushed, iclass 30, count 0 2006.173.16:51:33.17#ibcon#about to write, iclass 30, count 0 2006.173.16:51:33.17#ibcon#wrote, iclass 30, count 0 2006.173.16:51:33.17#ibcon#about to read 3, iclass 30, count 0 2006.173.16:51:33.19#ibcon#read 3, iclass 30, count 0 2006.173.16:51:33.19#ibcon#about to read 4, iclass 30, count 0 2006.173.16:51:33.19#ibcon#read 4, iclass 30, count 0 2006.173.16:51:33.19#ibcon#about to read 5, iclass 30, count 0 2006.173.16:51:33.19#ibcon#read 5, iclass 30, count 0 2006.173.16:51:33.19#ibcon#about to read 6, iclass 30, count 0 2006.173.16:51:33.19#ibcon#read 6, iclass 30, count 0 2006.173.16:51:33.19#ibcon#end of sib2, iclass 30, count 0 2006.173.16:51:33.19#ibcon#*mode == 0, iclass 30, count 0 2006.173.16:51:33.19#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.16:51:33.19#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.16:51:33.19#ibcon#*before write, iclass 30, count 0 2006.173.16:51:33.19#ibcon#enter sib2, iclass 30, count 0 2006.173.16:51:33.19#ibcon#flushed, iclass 30, count 0 2006.173.16:51:33.19#ibcon#about to write, iclass 30, count 0 2006.173.16:51:33.19#ibcon#wrote, iclass 30, count 0 2006.173.16:51:33.19#ibcon#about to read 3, iclass 30, count 0 2006.173.16:51:33.23#ibcon#read 3, iclass 30, count 0 2006.173.16:51:33.23#ibcon#about to read 4, iclass 30, count 0 2006.173.16:51:33.23#ibcon#read 4, iclass 30, count 0 2006.173.16:51:33.23#ibcon#about to read 5, iclass 30, count 0 2006.173.16:51:33.23#ibcon#read 5, iclass 30, count 0 2006.173.16:51:33.23#ibcon#about to read 6, iclass 30, count 0 2006.173.16:51:33.23#ibcon#read 6, iclass 30, count 0 2006.173.16:51:33.23#ibcon#end of sib2, iclass 30, count 0 2006.173.16:51:33.23#ibcon#*after write, iclass 30, count 0 2006.173.16:51:33.23#ibcon#*before return 0, iclass 30, count 0 2006.173.16:51:33.23#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.16:51:33.23#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.16:51:33.23#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.16:51:33.23#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.16:51:33.23$vck44/vb=8,4 2006.173.16:51:33.23#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.173.16:51:33.23#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.173.16:51:33.23#ibcon#ireg 11 cls_cnt 2 2006.173.16:51:33.23#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.16:51:33.29#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.16:51:33.29#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.16:51:33.29#ibcon#enter wrdev, iclass 32, count 2 2006.173.16:51:33.29#ibcon#first serial, iclass 32, count 2 2006.173.16:51:33.29#ibcon#enter sib2, iclass 32, count 2 2006.173.16:51:33.29#ibcon#flushed, iclass 32, count 2 2006.173.16:51:33.29#ibcon#about to write, iclass 32, count 2 2006.173.16:51:33.29#ibcon#wrote, iclass 32, count 2 2006.173.16:51:33.29#ibcon#about to read 3, iclass 32, count 2 2006.173.16:51:33.31#ibcon#read 3, iclass 32, count 2 2006.173.16:51:33.31#ibcon#about to read 4, iclass 32, count 2 2006.173.16:51:33.31#ibcon#read 4, iclass 32, count 2 2006.173.16:51:33.31#ibcon#about to read 5, iclass 32, count 2 2006.173.16:51:33.31#ibcon#read 5, iclass 32, count 2 2006.173.16:51:33.31#ibcon#about to read 6, iclass 32, count 2 2006.173.16:51:33.31#ibcon#read 6, iclass 32, count 2 2006.173.16:51:33.31#ibcon#end of sib2, iclass 32, count 2 2006.173.16:51:33.31#ibcon#*mode == 0, iclass 32, count 2 2006.173.16:51:33.31#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.173.16:51:33.31#ibcon#[27=AT08-04\r\n] 2006.173.16:51:33.31#ibcon#*before write, iclass 32, count 2 2006.173.16:51:33.31#ibcon#enter sib2, iclass 32, count 2 2006.173.16:51:33.31#ibcon#flushed, iclass 32, count 2 2006.173.16:51:33.31#ibcon#about to write, iclass 32, count 2 2006.173.16:51:33.31#ibcon#wrote, iclass 32, count 2 2006.173.16:51:33.31#ibcon#about to read 3, iclass 32, count 2 2006.173.16:51:33.34#ibcon#read 3, iclass 32, count 2 2006.173.16:51:33.34#ibcon#about to read 4, iclass 32, count 2 2006.173.16:51:33.34#ibcon#read 4, iclass 32, count 2 2006.173.16:51:33.34#ibcon#about to read 5, iclass 32, count 2 2006.173.16:51:33.34#ibcon#read 5, iclass 32, count 2 2006.173.16:51:33.34#ibcon#about to read 6, iclass 32, count 2 2006.173.16:51:33.34#ibcon#read 6, iclass 32, count 2 2006.173.16:51:33.34#ibcon#end of sib2, iclass 32, count 2 2006.173.16:51:33.34#ibcon#*after write, iclass 32, count 2 2006.173.16:51:33.34#ibcon#*before return 0, iclass 32, count 2 2006.173.16:51:33.34#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.16:51:33.34#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.173.16:51:33.34#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.173.16:51:33.34#ibcon#ireg 7 cls_cnt 0 2006.173.16:51:33.34#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.16:51:33.46#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.16:51:33.46#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.16:51:33.46#ibcon#enter wrdev, iclass 32, count 0 2006.173.16:51:33.46#ibcon#first serial, iclass 32, count 0 2006.173.16:51:33.46#ibcon#enter sib2, iclass 32, count 0 2006.173.16:51:33.46#ibcon#flushed, iclass 32, count 0 2006.173.16:51:33.46#ibcon#about to write, iclass 32, count 0 2006.173.16:51:33.46#ibcon#wrote, iclass 32, count 0 2006.173.16:51:33.46#ibcon#about to read 3, iclass 32, count 0 2006.173.16:51:33.48#ibcon#read 3, iclass 32, count 0 2006.173.16:51:33.48#ibcon#about to read 4, iclass 32, count 0 2006.173.16:51:33.48#ibcon#read 4, iclass 32, count 0 2006.173.16:51:33.48#ibcon#about to read 5, iclass 32, count 0 2006.173.16:51:33.48#ibcon#read 5, iclass 32, count 0 2006.173.16:51:33.48#ibcon#about to read 6, iclass 32, count 0 2006.173.16:51:33.48#ibcon#read 6, iclass 32, count 0 2006.173.16:51:33.48#ibcon#end of sib2, iclass 32, count 0 2006.173.16:51:33.48#ibcon#*mode == 0, iclass 32, count 0 2006.173.16:51:33.48#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.16:51:33.48#ibcon#[27=USB\r\n] 2006.173.16:51:33.48#ibcon#*before write, iclass 32, count 0 2006.173.16:51:33.48#ibcon#enter sib2, iclass 32, count 0 2006.173.16:51:33.48#ibcon#flushed, iclass 32, count 0 2006.173.16:51:33.48#ibcon#about to write, iclass 32, count 0 2006.173.16:51:33.48#ibcon#wrote, iclass 32, count 0 2006.173.16:51:33.48#ibcon#about to read 3, iclass 32, count 0 2006.173.16:51:33.51#ibcon#read 3, iclass 32, count 0 2006.173.16:51:33.51#ibcon#about to read 4, iclass 32, count 0 2006.173.16:51:33.51#ibcon#read 4, iclass 32, count 0 2006.173.16:51:33.51#ibcon#about to read 5, iclass 32, count 0 2006.173.16:51:33.51#ibcon#read 5, iclass 32, count 0 2006.173.16:51:33.51#ibcon#about to read 6, iclass 32, count 0 2006.173.16:51:33.51#ibcon#read 6, iclass 32, count 0 2006.173.16:51:33.51#ibcon#end of sib2, iclass 32, count 0 2006.173.16:51:33.51#ibcon#*after write, iclass 32, count 0 2006.173.16:51:33.51#ibcon#*before return 0, iclass 32, count 0 2006.173.16:51:33.51#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.16:51:33.51#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.173.16:51:33.51#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.16:51:33.51#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.16:51:33.51$vck44/vabw=wide 2006.173.16:51:33.51#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.16:51:33.51#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.16:51:33.51#ibcon#ireg 8 cls_cnt 0 2006.173.16:51:33.51#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.16:51:33.51#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.16:51:33.51#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.16:51:33.51#ibcon#enter wrdev, iclass 34, count 0 2006.173.16:51:33.51#ibcon#first serial, iclass 34, count 0 2006.173.16:51:33.51#ibcon#enter sib2, iclass 34, count 0 2006.173.16:51:33.51#ibcon#flushed, iclass 34, count 0 2006.173.16:51:33.51#ibcon#about to write, iclass 34, count 0 2006.173.16:51:33.51#ibcon#wrote, iclass 34, count 0 2006.173.16:51:33.51#ibcon#about to read 3, iclass 34, count 0 2006.173.16:51:33.53#ibcon#read 3, iclass 34, count 0 2006.173.16:51:33.53#ibcon#about to read 4, iclass 34, count 0 2006.173.16:51:33.53#ibcon#read 4, iclass 34, count 0 2006.173.16:51:33.53#ibcon#about to read 5, iclass 34, count 0 2006.173.16:51:33.53#ibcon#read 5, iclass 34, count 0 2006.173.16:51:33.53#ibcon#about to read 6, iclass 34, count 0 2006.173.16:51:33.53#ibcon#read 6, iclass 34, count 0 2006.173.16:51:33.53#ibcon#end of sib2, iclass 34, count 0 2006.173.16:51:33.53#ibcon#*mode == 0, iclass 34, count 0 2006.173.16:51:33.53#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.16:51:33.53#ibcon#[25=BW32\r\n] 2006.173.16:51:33.53#ibcon#*before write, iclass 34, count 0 2006.173.16:51:33.53#ibcon#enter sib2, iclass 34, count 0 2006.173.16:51:33.53#ibcon#flushed, iclass 34, count 0 2006.173.16:51:33.53#ibcon#about to write, iclass 34, count 0 2006.173.16:51:33.53#ibcon#wrote, iclass 34, count 0 2006.173.16:51:33.53#ibcon#about to read 3, iclass 34, count 0 2006.173.16:51:33.56#ibcon#read 3, iclass 34, count 0 2006.173.16:51:33.56#ibcon#about to read 4, iclass 34, count 0 2006.173.16:51:33.56#ibcon#read 4, iclass 34, count 0 2006.173.16:51:33.56#ibcon#about to read 5, iclass 34, count 0 2006.173.16:51:33.56#ibcon#read 5, iclass 34, count 0 2006.173.16:51:33.56#ibcon#about to read 6, iclass 34, count 0 2006.173.16:51:33.56#ibcon#read 6, iclass 34, count 0 2006.173.16:51:33.56#ibcon#end of sib2, iclass 34, count 0 2006.173.16:51:33.56#ibcon#*after write, iclass 34, count 0 2006.173.16:51:33.56#ibcon#*before return 0, iclass 34, count 0 2006.173.16:51:33.56#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.16:51:33.56#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.16:51:33.56#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.16:51:33.56#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.16:51:33.56$vck44/vbbw=wide 2006.173.16:51:33.56#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.16:51:33.56#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.16:51:33.56#ibcon#ireg 8 cls_cnt 0 2006.173.16:51:33.56#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.16:51:33.63#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.16:51:33.63#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.16:51:33.63#ibcon#enter wrdev, iclass 36, count 0 2006.173.16:51:33.63#ibcon#first serial, iclass 36, count 0 2006.173.16:51:33.63#ibcon#enter sib2, iclass 36, count 0 2006.173.16:51:33.63#ibcon#flushed, iclass 36, count 0 2006.173.16:51:33.63#ibcon#about to write, iclass 36, count 0 2006.173.16:51:33.63#ibcon#wrote, iclass 36, count 0 2006.173.16:51:33.63#ibcon#about to read 3, iclass 36, count 0 2006.173.16:51:33.65#ibcon#read 3, iclass 36, count 0 2006.173.16:51:33.65#ibcon#about to read 4, iclass 36, count 0 2006.173.16:51:33.65#ibcon#read 4, iclass 36, count 0 2006.173.16:51:33.65#ibcon#about to read 5, iclass 36, count 0 2006.173.16:51:33.65#ibcon#read 5, iclass 36, count 0 2006.173.16:51:33.65#ibcon#about to read 6, iclass 36, count 0 2006.173.16:51:33.65#ibcon#read 6, iclass 36, count 0 2006.173.16:51:33.65#ibcon#end of sib2, iclass 36, count 0 2006.173.16:51:33.65#ibcon#*mode == 0, iclass 36, count 0 2006.173.16:51:33.65#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.16:51:33.65#ibcon#[27=BW32\r\n] 2006.173.16:51:33.65#ibcon#*before write, iclass 36, count 0 2006.173.16:51:33.65#ibcon#enter sib2, iclass 36, count 0 2006.173.16:51:33.65#ibcon#flushed, iclass 36, count 0 2006.173.16:51:33.65#ibcon#about to write, iclass 36, count 0 2006.173.16:51:33.65#ibcon#wrote, iclass 36, count 0 2006.173.16:51:33.65#ibcon#about to read 3, iclass 36, count 0 2006.173.16:51:33.68#ibcon#read 3, iclass 36, count 0 2006.173.16:51:33.68#ibcon#about to read 4, iclass 36, count 0 2006.173.16:51:33.68#ibcon#read 4, iclass 36, count 0 2006.173.16:51:33.68#ibcon#about to read 5, iclass 36, count 0 2006.173.16:51:33.68#ibcon#read 5, iclass 36, count 0 2006.173.16:51:33.68#ibcon#about to read 6, iclass 36, count 0 2006.173.16:51:33.68#ibcon#read 6, iclass 36, count 0 2006.173.16:51:33.68#ibcon#end of sib2, iclass 36, count 0 2006.173.16:51:33.68#ibcon#*after write, iclass 36, count 0 2006.173.16:51:33.68#ibcon#*before return 0, iclass 36, count 0 2006.173.16:51:33.68#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.16:51:33.68#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.16:51:33.68#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.16:51:33.68#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.16:51:33.68$setupk4/ifdk4 2006.173.16:51:33.68$ifdk4/lo= 2006.173.16:51:33.68$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.16:51:33.68$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.16:51:33.68$ifdk4/patch= 2006.173.16:51:33.68$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.16:51:33.68$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.16:51:33.68$setupk4/!*+20s 2006.173.16:51:40.51#abcon#<5=/14 0.3 1.6 20.431001002.9\r\n> 2006.173.16:51:40.53#abcon#{5=INTERFACE CLEAR} 2006.173.16:51:40.59#abcon#[5=S1D000X0/0*\r\n] 2006.173.16:51:48.17$setupk4/"tpicd 2006.173.16:51:48.17$setupk4/echo=off 2006.173.16:51:48.17$setupk4/xlog=off 2006.173.16:51:48.17:!2006.173.16:52:31 2006.173.16:51:57.14#trakl#Source acquired 2006.173.16:51:59.14#flagr#flagr/antenna,acquired 2006.173.16:52:31.00:preob 2006.173.16:52:31.14/onsource/TRACKING 2006.173.16:52:31.14:!2006.173.16:52:41 2006.173.16:52:41.00:"tape 2006.173.16:52:41.00:"st=record 2006.173.16:52:41.00:data_valid=on 2006.173.16:52:41.00:midob 2006.173.16:52:41.14/onsource/TRACKING 2006.173.16:52:41.14/wx/20.42,1002.9,100 2006.173.16:52:41.29/cable/+6.5143E-03 2006.173.16:52:42.38/va/01,07,usb,yes,35,38 2006.173.16:52:42.38/va/02,06,usb,yes,35,36 2006.173.16:52:42.38/va/03,05,usb,yes,44,46 2006.173.16:52:42.38/va/04,06,usb,yes,36,37 2006.173.16:52:42.38/va/05,04,usb,yes,28,28 2006.173.16:52:42.38/va/06,03,usb,yes,39,39 2006.173.16:52:42.38/va/07,04,usb,yes,32,33 2006.173.16:52:42.38/va/08,04,usb,yes,27,32 2006.173.16:52:42.61/valo/01,524.99,yes,locked 2006.173.16:52:42.61/valo/02,534.99,yes,locked 2006.173.16:52:42.61/valo/03,564.99,yes,locked 2006.173.16:52:42.61/valo/04,624.99,yes,locked 2006.173.16:52:42.61/valo/05,734.99,yes,locked 2006.173.16:52:42.61/valo/06,814.99,yes,locked 2006.173.16:52:42.61/valo/07,864.99,yes,locked 2006.173.16:52:42.61/valo/08,884.99,yes,locked 2006.173.16:52:43.70/vb/01,04,usb,yes,29,27 2006.173.16:52:43.70/vb/02,04,usb,yes,31,31 2006.173.16:52:43.70/vb/03,04,usb,yes,28,31 2006.173.16:52:43.70/vb/04,04,usb,yes,33,31 2006.173.16:52:43.70/vb/05,04,usb,yes,25,28 2006.173.16:52:43.70/vb/06,04,usb,yes,30,26 2006.173.16:52:43.70/vb/07,04,usb,yes,29,29 2006.173.16:52:43.70/vb/08,04,usb,yes,27,30 2006.173.16:52:43.94/vblo/01,629.99,yes,locked 2006.173.16:52:43.94/vblo/02,634.99,yes,locked 2006.173.16:52:43.94/vblo/03,649.99,yes,locked 2006.173.16:52:43.94/vblo/04,679.99,yes,locked 2006.173.16:52:43.94/vblo/05,709.99,yes,locked 2006.173.16:52:43.94/vblo/06,719.99,yes,locked 2006.173.16:52:43.94/vblo/07,734.99,yes,locked 2006.173.16:52:43.94/vblo/08,744.99,yes,locked 2006.173.16:52:44.09/vabw/8 2006.173.16:52:44.24/vbbw/8 2006.173.16:52:44.33/xfe/off,on,14.7 2006.173.16:52:44.71/ifatt/23,28,28,28 2006.173.16:52:45.07/fmout-gps/S +3.95E-07 2006.173.16:52:45.11:!2006.173.16:53:21 2006.173.16:53:21.01:data_valid=off 2006.173.16:53:21.01:"et 2006.173.16:53:21.01:!+3s 2006.173.16:53:24.02:"tape 2006.173.16:53:24.02:postob 2006.173.16:53:24.16/cable/+6.5117E-03 2006.173.16:53:24.16/wx/20.41,1002.9,100 2006.173.16:53:24.22/fmout-gps/S +3.96E-07 2006.173.16:53:24.22:scan_name=173-1655,jd0606,220 2006.173.16:53:24.22:source=0059+581,010245.76,582411.1,2000.0,ccw 2006.173.16:53:26.14#flagr#flagr/antenna,new-source 2006.173.16:53:26.14:checkk5 2006.173.16:53:26.54/chk_autoobs//k5ts1/ autoobs is running! 2006.173.16:53:26.93/chk_autoobs//k5ts2/ autoobs is running! 2006.173.16:53:27.35/chk_autoobs//k5ts3/ autoobs is running! 2006.173.16:53:27.73/chk_autoobs//k5ts4/ autoobs is running! 2006.173.16:53:28.15/chk_obsdata//k5ts1/T1731652??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.16:53:28.53/chk_obsdata//k5ts2/T1731652??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.16:53:28.93/chk_obsdata//k5ts3/T1731652??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.16:53:29.33/chk_obsdata//k5ts4/T1731652??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.16:53:30.06/k5log//k5ts1_log_newline 2006.173.16:53:30.77/k5log//k5ts2_log_newline 2006.173.16:53:31.49/k5log//k5ts3_log_newline 2006.173.16:53:32.21/k5log//k5ts4_log_newline 2006.173.16:53:32.23/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.16:53:32.23:setupk4=1 2006.173.16:53:32.23$setupk4/echo=on 2006.173.16:53:32.23$setupk4/pcalon 2006.173.16:53:32.23$pcalon/"no phase cal control is implemented here 2006.173.16:53:32.23$setupk4/"tpicd=stop 2006.173.16:53:32.23$setupk4/"rec=synch_on 2006.173.16:53:32.23$setupk4/"rec_mode=128 2006.173.16:53:32.23$setupk4/!* 2006.173.16:53:32.23$setupk4/recpk4 2006.173.16:53:32.23$recpk4/recpatch= 2006.173.16:53:32.24$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.16:53:32.24$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.16:53:32.24$setupk4/vck44 2006.173.16:53:32.24$vck44/valo=1,524.99 2006.173.16:53:32.24#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.16:53:32.24#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.16:53:32.24#ibcon#ireg 17 cls_cnt 0 2006.173.16:53:32.24#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.16:53:32.24#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.16:53:32.24#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.16:53:32.24#ibcon#enter wrdev, iclass 13, count 0 2006.173.16:53:32.24#ibcon#first serial, iclass 13, count 0 2006.173.16:53:32.24#ibcon#enter sib2, iclass 13, count 0 2006.173.16:53:32.24#ibcon#flushed, iclass 13, count 0 2006.173.16:53:32.24#ibcon#about to write, iclass 13, count 0 2006.173.16:53:32.24#ibcon#wrote, iclass 13, count 0 2006.173.16:53:32.24#ibcon#about to read 3, iclass 13, count 0 2006.173.16:53:32.25#ibcon#read 3, iclass 13, count 0 2006.173.16:53:32.25#ibcon#about to read 4, iclass 13, count 0 2006.173.16:53:32.25#ibcon#read 4, iclass 13, count 0 2006.173.16:53:32.25#ibcon#about to read 5, iclass 13, count 0 2006.173.16:53:32.25#ibcon#read 5, iclass 13, count 0 2006.173.16:53:32.25#ibcon#about to read 6, iclass 13, count 0 2006.173.16:53:32.25#ibcon#read 6, iclass 13, count 0 2006.173.16:53:32.25#ibcon#end of sib2, iclass 13, count 0 2006.173.16:53:32.25#ibcon#*mode == 0, iclass 13, count 0 2006.173.16:53:32.25#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.16:53:32.25#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.16:53:32.25#ibcon#*before write, iclass 13, count 0 2006.173.16:53:32.25#ibcon#enter sib2, iclass 13, count 0 2006.173.16:53:32.25#ibcon#flushed, iclass 13, count 0 2006.173.16:53:32.25#ibcon#about to write, iclass 13, count 0 2006.173.16:53:32.25#ibcon#wrote, iclass 13, count 0 2006.173.16:53:32.25#ibcon#about to read 3, iclass 13, count 0 2006.173.16:53:32.30#ibcon#read 3, iclass 13, count 0 2006.173.16:53:32.30#ibcon#about to read 4, iclass 13, count 0 2006.173.16:53:32.30#ibcon#read 4, iclass 13, count 0 2006.173.16:53:32.30#ibcon#about to read 5, iclass 13, count 0 2006.173.16:53:32.30#ibcon#read 5, iclass 13, count 0 2006.173.16:53:32.30#ibcon#about to read 6, iclass 13, count 0 2006.173.16:53:32.30#ibcon#read 6, iclass 13, count 0 2006.173.16:53:32.30#ibcon#end of sib2, iclass 13, count 0 2006.173.16:53:32.30#ibcon#*after write, iclass 13, count 0 2006.173.16:53:32.30#ibcon#*before return 0, iclass 13, count 0 2006.173.16:53:32.30#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.16:53:32.30#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.16:53:32.30#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.16:53:32.30#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.16:53:32.30$vck44/va=1,7 2006.173.16:53:32.30#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.16:53:32.30#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.16:53:32.30#ibcon#ireg 11 cls_cnt 2 2006.173.16:53:32.30#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.16:53:32.30#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.16:53:32.30#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.16:53:32.30#ibcon#enter wrdev, iclass 15, count 2 2006.173.16:53:32.30#ibcon#first serial, iclass 15, count 2 2006.173.16:53:32.30#ibcon#enter sib2, iclass 15, count 2 2006.173.16:53:32.30#ibcon#flushed, iclass 15, count 2 2006.173.16:53:32.30#ibcon#about to write, iclass 15, count 2 2006.173.16:53:32.30#ibcon#wrote, iclass 15, count 2 2006.173.16:53:32.30#ibcon#about to read 3, iclass 15, count 2 2006.173.16:53:32.32#ibcon#read 3, iclass 15, count 2 2006.173.16:53:32.32#ibcon#about to read 4, iclass 15, count 2 2006.173.16:53:32.32#ibcon#read 4, iclass 15, count 2 2006.173.16:53:32.32#ibcon#about to read 5, iclass 15, count 2 2006.173.16:53:32.32#ibcon#read 5, iclass 15, count 2 2006.173.16:53:32.32#ibcon#about to read 6, iclass 15, count 2 2006.173.16:53:32.32#ibcon#read 6, iclass 15, count 2 2006.173.16:53:32.32#ibcon#end of sib2, iclass 15, count 2 2006.173.16:53:32.32#ibcon#*mode == 0, iclass 15, count 2 2006.173.16:53:32.32#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.16:53:32.32#ibcon#[25=AT01-07\r\n] 2006.173.16:53:32.32#ibcon#*before write, iclass 15, count 2 2006.173.16:53:32.32#ibcon#enter sib2, iclass 15, count 2 2006.173.16:53:32.32#ibcon#flushed, iclass 15, count 2 2006.173.16:53:32.32#ibcon#about to write, iclass 15, count 2 2006.173.16:53:32.32#ibcon#wrote, iclass 15, count 2 2006.173.16:53:32.32#ibcon#about to read 3, iclass 15, count 2 2006.173.16:53:32.35#ibcon#read 3, iclass 15, count 2 2006.173.16:53:32.35#ibcon#about to read 4, iclass 15, count 2 2006.173.16:53:32.35#ibcon#read 4, iclass 15, count 2 2006.173.16:53:32.35#ibcon#about to read 5, iclass 15, count 2 2006.173.16:53:32.35#ibcon#read 5, iclass 15, count 2 2006.173.16:53:32.35#ibcon#about to read 6, iclass 15, count 2 2006.173.16:53:32.35#ibcon#read 6, iclass 15, count 2 2006.173.16:53:32.35#ibcon#end of sib2, iclass 15, count 2 2006.173.16:53:32.35#ibcon#*after write, iclass 15, count 2 2006.173.16:53:32.35#ibcon#*before return 0, iclass 15, count 2 2006.173.16:53:32.35#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.16:53:32.35#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.16:53:32.35#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.16:53:32.35#ibcon#ireg 7 cls_cnt 0 2006.173.16:53:32.35#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.16:53:32.38#abcon#<5=/14 0.5 1.8 20.411001002.9\r\n> 2006.173.16:53:32.40#abcon#{5=INTERFACE CLEAR} 2006.173.16:53:32.46#abcon#[5=S1D000X0/0*\r\n] 2006.173.16:53:32.47#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.16:53:32.47#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.16:53:32.47#ibcon#enter wrdev, iclass 15, count 0 2006.173.16:53:32.47#ibcon#first serial, iclass 15, count 0 2006.173.16:53:32.47#ibcon#enter sib2, iclass 15, count 0 2006.173.16:53:32.47#ibcon#flushed, iclass 15, count 0 2006.173.16:53:32.47#ibcon#about to write, iclass 15, count 0 2006.173.16:53:32.47#ibcon#wrote, iclass 15, count 0 2006.173.16:53:32.47#ibcon#about to read 3, iclass 15, count 0 2006.173.16:53:32.49#ibcon#read 3, iclass 15, count 0 2006.173.16:53:32.49#ibcon#about to read 4, iclass 15, count 0 2006.173.16:53:32.49#ibcon#read 4, iclass 15, count 0 2006.173.16:53:32.49#ibcon#about to read 5, iclass 15, count 0 2006.173.16:53:32.49#ibcon#read 5, iclass 15, count 0 2006.173.16:53:32.49#ibcon#about to read 6, iclass 15, count 0 2006.173.16:53:32.49#ibcon#read 6, iclass 15, count 0 2006.173.16:53:32.49#ibcon#end of sib2, iclass 15, count 0 2006.173.16:53:32.49#ibcon#*mode == 0, iclass 15, count 0 2006.173.16:53:32.49#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.16:53:32.49#ibcon#[25=USB\r\n] 2006.173.16:53:32.49#ibcon#*before write, iclass 15, count 0 2006.173.16:53:32.49#ibcon#enter sib2, iclass 15, count 0 2006.173.16:53:32.49#ibcon#flushed, iclass 15, count 0 2006.173.16:53:32.49#ibcon#about to write, iclass 15, count 0 2006.173.16:53:32.49#ibcon#wrote, iclass 15, count 0 2006.173.16:53:32.49#ibcon#about to read 3, iclass 15, count 0 2006.173.16:53:32.52#ibcon#read 3, iclass 15, count 0 2006.173.16:53:32.52#ibcon#about to read 4, iclass 15, count 0 2006.173.16:53:32.52#ibcon#read 4, iclass 15, count 0 2006.173.16:53:32.52#ibcon#about to read 5, iclass 15, count 0 2006.173.16:53:32.52#ibcon#read 5, iclass 15, count 0 2006.173.16:53:32.52#ibcon#about to read 6, iclass 15, count 0 2006.173.16:53:32.52#ibcon#read 6, iclass 15, count 0 2006.173.16:53:32.52#ibcon#end of sib2, iclass 15, count 0 2006.173.16:53:32.52#ibcon#*after write, iclass 15, count 0 2006.173.16:53:32.52#ibcon#*before return 0, iclass 15, count 0 2006.173.16:53:32.52#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.16:53:32.52#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.16:53:32.52#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.16:53:32.52#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.16:53:32.52$vck44/valo=2,534.99 2006.173.16:53:32.52#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.16:53:32.52#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.16:53:32.52#ibcon#ireg 17 cls_cnt 0 2006.173.16:53:32.52#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.16:53:32.52#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.16:53:32.52#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.16:53:32.52#ibcon#enter wrdev, iclass 21, count 0 2006.173.16:53:32.52#ibcon#first serial, iclass 21, count 0 2006.173.16:53:32.52#ibcon#enter sib2, iclass 21, count 0 2006.173.16:53:32.52#ibcon#flushed, iclass 21, count 0 2006.173.16:53:32.52#ibcon#about to write, iclass 21, count 0 2006.173.16:53:32.52#ibcon#wrote, iclass 21, count 0 2006.173.16:53:32.52#ibcon#about to read 3, iclass 21, count 0 2006.173.16:53:32.54#ibcon#read 3, iclass 21, count 0 2006.173.16:53:32.54#ibcon#about to read 4, iclass 21, count 0 2006.173.16:53:32.54#ibcon#read 4, iclass 21, count 0 2006.173.16:53:32.54#ibcon#about to read 5, iclass 21, count 0 2006.173.16:53:32.54#ibcon#read 5, iclass 21, count 0 2006.173.16:53:32.54#ibcon#about to read 6, iclass 21, count 0 2006.173.16:53:32.54#ibcon#read 6, iclass 21, count 0 2006.173.16:53:32.54#ibcon#end of sib2, iclass 21, count 0 2006.173.16:53:32.54#ibcon#*mode == 0, iclass 21, count 0 2006.173.16:53:32.54#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.16:53:32.54#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.16:53:32.54#ibcon#*before write, iclass 21, count 0 2006.173.16:53:32.54#ibcon#enter sib2, iclass 21, count 0 2006.173.16:53:32.54#ibcon#flushed, iclass 21, count 0 2006.173.16:53:32.54#ibcon#about to write, iclass 21, count 0 2006.173.16:53:32.54#ibcon#wrote, iclass 21, count 0 2006.173.16:53:32.54#ibcon#about to read 3, iclass 21, count 0 2006.173.16:53:32.58#ibcon#read 3, iclass 21, count 0 2006.173.16:53:32.58#ibcon#about to read 4, iclass 21, count 0 2006.173.16:53:32.58#ibcon#read 4, iclass 21, count 0 2006.173.16:53:32.58#ibcon#about to read 5, iclass 21, count 0 2006.173.16:53:32.58#ibcon#read 5, iclass 21, count 0 2006.173.16:53:32.58#ibcon#about to read 6, iclass 21, count 0 2006.173.16:53:32.58#ibcon#read 6, iclass 21, count 0 2006.173.16:53:32.58#ibcon#end of sib2, iclass 21, count 0 2006.173.16:53:32.58#ibcon#*after write, iclass 21, count 0 2006.173.16:53:32.58#ibcon#*before return 0, iclass 21, count 0 2006.173.16:53:32.58#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.16:53:32.58#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.16:53:32.58#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.16:53:32.58#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.16:53:32.58$vck44/va=2,6 2006.173.16:53:32.58#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.16:53:32.58#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.16:53:32.58#ibcon#ireg 11 cls_cnt 2 2006.173.16:53:32.58#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.16:53:32.64#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.16:53:32.64#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.16:53:32.64#ibcon#enter wrdev, iclass 23, count 2 2006.173.16:53:32.64#ibcon#first serial, iclass 23, count 2 2006.173.16:53:32.64#ibcon#enter sib2, iclass 23, count 2 2006.173.16:53:32.64#ibcon#flushed, iclass 23, count 2 2006.173.16:53:32.64#ibcon#about to write, iclass 23, count 2 2006.173.16:53:32.64#ibcon#wrote, iclass 23, count 2 2006.173.16:53:32.64#ibcon#about to read 3, iclass 23, count 2 2006.173.16:53:32.66#ibcon#read 3, iclass 23, count 2 2006.173.16:53:32.66#ibcon#about to read 4, iclass 23, count 2 2006.173.16:53:32.66#ibcon#read 4, iclass 23, count 2 2006.173.16:53:32.66#ibcon#about to read 5, iclass 23, count 2 2006.173.16:53:32.66#ibcon#read 5, iclass 23, count 2 2006.173.16:53:32.66#ibcon#about to read 6, iclass 23, count 2 2006.173.16:53:32.66#ibcon#read 6, iclass 23, count 2 2006.173.16:53:32.66#ibcon#end of sib2, iclass 23, count 2 2006.173.16:53:32.66#ibcon#*mode == 0, iclass 23, count 2 2006.173.16:53:32.66#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.16:53:32.66#ibcon#[25=AT02-06\r\n] 2006.173.16:53:32.66#ibcon#*before write, iclass 23, count 2 2006.173.16:53:32.66#ibcon#enter sib2, iclass 23, count 2 2006.173.16:53:32.66#ibcon#flushed, iclass 23, count 2 2006.173.16:53:32.66#ibcon#about to write, iclass 23, count 2 2006.173.16:53:32.66#ibcon#wrote, iclass 23, count 2 2006.173.16:53:32.66#ibcon#about to read 3, iclass 23, count 2 2006.173.16:53:32.69#ibcon#read 3, iclass 23, count 2 2006.173.16:53:32.69#ibcon#about to read 4, iclass 23, count 2 2006.173.16:53:32.69#ibcon#read 4, iclass 23, count 2 2006.173.16:53:32.69#ibcon#about to read 5, iclass 23, count 2 2006.173.16:53:32.69#ibcon#read 5, iclass 23, count 2 2006.173.16:53:32.69#ibcon#about to read 6, iclass 23, count 2 2006.173.16:53:32.69#ibcon#read 6, iclass 23, count 2 2006.173.16:53:32.69#ibcon#end of sib2, iclass 23, count 2 2006.173.16:53:32.69#ibcon#*after write, iclass 23, count 2 2006.173.16:53:32.69#ibcon#*before return 0, iclass 23, count 2 2006.173.16:53:32.69#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.16:53:32.69#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.16:53:32.69#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.16:53:32.69#ibcon#ireg 7 cls_cnt 0 2006.173.16:53:32.69#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.16:53:32.81#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.16:53:32.81#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.16:53:32.81#ibcon#enter wrdev, iclass 23, count 0 2006.173.16:53:32.81#ibcon#first serial, iclass 23, count 0 2006.173.16:53:32.81#ibcon#enter sib2, iclass 23, count 0 2006.173.16:53:32.81#ibcon#flushed, iclass 23, count 0 2006.173.16:53:32.81#ibcon#about to write, iclass 23, count 0 2006.173.16:53:32.81#ibcon#wrote, iclass 23, count 0 2006.173.16:53:32.81#ibcon#about to read 3, iclass 23, count 0 2006.173.16:53:32.83#ibcon#read 3, iclass 23, count 0 2006.173.16:53:32.83#ibcon#about to read 4, iclass 23, count 0 2006.173.16:53:32.83#ibcon#read 4, iclass 23, count 0 2006.173.16:53:32.83#ibcon#about to read 5, iclass 23, count 0 2006.173.16:53:32.83#ibcon#read 5, iclass 23, count 0 2006.173.16:53:32.83#ibcon#about to read 6, iclass 23, count 0 2006.173.16:53:32.83#ibcon#read 6, iclass 23, count 0 2006.173.16:53:32.83#ibcon#end of sib2, iclass 23, count 0 2006.173.16:53:32.83#ibcon#*mode == 0, iclass 23, count 0 2006.173.16:53:32.83#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.16:53:32.83#ibcon#[25=USB\r\n] 2006.173.16:53:32.83#ibcon#*before write, iclass 23, count 0 2006.173.16:53:32.83#ibcon#enter sib2, iclass 23, count 0 2006.173.16:53:32.83#ibcon#flushed, iclass 23, count 0 2006.173.16:53:32.83#ibcon#about to write, iclass 23, count 0 2006.173.16:53:32.83#ibcon#wrote, iclass 23, count 0 2006.173.16:53:32.83#ibcon#about to read 3, iclass 23, count 0 2006.173.16:53:32.86#ibcon#read 3, iclass 23, count 0 2006.173.16:53:32.86#ibcon#about to read 4, iclass 23, count 0 2006.173.16:53:32.86#ibcon#read 4, iclass 23, count 0 2006.173.16:53:32.86#ibcon#about to read 5, iclass 23, count 0 2006.173.16:53:32.86#ibcon#read 5, iclass 23, count 0 2006.173.16:53:32.86#ibcon#about to read 6, iclass 23, count 0 2006.173.16:53:32.86#ibcon#read 6, iclass 23, count 0 2006.173.16:53:32.86#ibcon#end of sib2, iclass 23, count 0 2006.173.16:53:32.86#ibcon#*after write, iclass 23, count 0 2006.173.16:53:32.86#ibcon#*before return 0, iclass 23, count 0 2006.173.16:53:32.86#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.16:53:32.86#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.16:53:32.86#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.16:53:32.86#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.16:53:32.86$vck44/valo=3,564.99 2006.173.16:53:32.86#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.16:53:32.86#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.16:53:32.86#ibcon#ireg 17 cls_cnt 0 2006.173.16:53:32.86#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.16:53:32.86#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.16:53:32.86#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.16:53:32.86#ibcon#enter wrdev, iclass 25, count 0 2006.173.16:53:32.86#ibcon#first serial, iclass 25, count 0 2006.173.16:53:32.86#ibcon#enter sib2, iclass 25, count 0 2006.173.16:53:32.86#ibcon#flushed, iclass 25, count 0 2006.173.16:53:32.86#ibcon#about to write, iclass 25, count 0 2006.173.16:53:32.86#ibcon#wrote, iclass 25, count 0 2006.173.16:53:32.86#ibcon#about to read 3, iclass 25, count 0 2006.173.16:53:32.88#ibcon#read 3, iclass 25, count 0 2006.173.16:53:32.88#ibcon#about to read 4, iclass 25, count 0 2006.173.16:53:32.88#ibcon#read 4, iclass 25, count 0 2006.173.16:53:32.88#ibcon#about to read 5, iclass 25, count 0 2006.173.16:53:32.88#ibcon#read 5, iclass 25, count 0 2006.173.16:53:32.88#ibcon#about to read 6, iclass 25, count 0 2006.173.16:53:32.88#ibcon#read 6, iclass 25, count 0 2006.173.16:53:32.88#ibcon#end of sib2, iclass 25, count 0 2006.173.16:53:32.88#ibcon#*mode == 0, iclass 25, count 0 2006.173.16:53:32.88#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.16:53:32.88#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.16:53:32.88#ibcon#*before write, iclass 25, count 0 2006.173.16:53:32.88#ibcon#enter sib2, iclass 25, count 0 2006.173.16:53:32.88#ibcon#flushed, iclass 25, count 0 2006.173.16:53:32.88#ibcon#about to write, iclass 25, count 0 2006.173.16:53:32.88#ibcon#wrote, iclass 25, count 0 2006.173.16:53:32.88#ibcon#about to read 3, iclass 25, count 0 2006.173.16:53:32.92#ibcon#read 3, iclass 25, count 0 2006.173.16:53:32.92#ibcon#about to read 4, iclass 25, count 0 2006.173.16:53:32.92#ibcon#read 4, iclass 25, count 0 2006.173.16:53:32.92#ibcon#about to read 5, iclass 25, count 0 2006.173.16:53:32.92#ibcon#read 5, iclass 25, count 0 2006.173.16:53:32.92#ibcon#about to read 6, iclass 25, count 0 2006.173.16:53:32.92#ibcon#read 6, iclass 25, count 0 2006.173.16:53:32.92#ibcon#end of sib2, iclass 25, count 0 2006.173.16:53:32.92#ibcon#*after write, iclass 25, count 0 2006.173.16:53:32.92#ibcon#*before return 0, iclass 25, count 0 2006.173.16:53:32.92#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.16:53:32.92#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.16:53:32.92#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.16:53:32.92#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.16:53:32.92$vck44/va=3,5 2006.173.16:53:32.92#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.16:53:32.92#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.16:53:32.92#ibcon#ireg 11 cls_cnt 2 2006.173.16:53:32.92#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.16:53:32.98#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.16:53:32.98#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.16:53:32.98#ibcon#enter wrdev, iclass 27, count 2 2006.173.16:53:32.98#ibcon#first serial, iclass 27, count 2 2006.173.16:53:32.98#ibcon#enter sib2, iclass 27, count 2 2006.173.16:53:32.98#ibcon#flushed, iclass 27, count 2 2006.173.16:53:32.98#ibcon#about to write, iclass 27, count 2 2006.173.16:53:32.98#ibcon#wrote, iclass 27, count 2 2006.173.16:53:32.98#ibcon#about to read 3, iclass 27, count 2 2006.173.16:53:33.00#ibcon#read 3, iclass 27, count 2 2006.173.16:53:33.00#ibcon#about to read 4, iclass 27, count 2 2006.173.16:53:33.00#ibcon#read 4, iclass 27, count 2 2006.173.16:53:33.00#ibcon#about to read 5, iclass 27, count 2 2006.173.16:53:33.00#ibcon#read 5, iclass 27, count 2 2006.173.16:53:33.00#ibcon#about to read 6, iclass 27, count 2 2006.173.16:53:33.00#ibcon#read 6, iclass 27, count 2 2006.173.16:53:33.00#ibcon#end of sib2, iclass 27, count 2 2006.173.16:53:33.00#ibcon#*mode == 0, iclass 27, count 2 2006.173.16:53:33.00#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.16:53:33.00#ibcon#[25=AT03-05\r\n] 2006.173.16:53:33.00#ibcon#*before write, iclass 27, count 2 2006.173.16:53:33.00#ibcon#enter sib2, iclass 27, count 2 2006.173.16:53:33.00#ibcon#flushed, iclass 27, count 2 2006.173.16:53:33.00#ibcon#about to write, iclass 27, count 2 2006.173.16:53:33.00#ibcon#wrote, iclass 27, count 2 2006.173.16:53:33.00#ibcon#about to read 3, iclass 27, count 2 2006.173.16:53:33.03#ibcon#read 3, iclass 27, count 2 2006.173.16:53:33.03#ibcon#about to read 4, iclass 27, count 2 2006.173.16:53:33.03#ibcon#read 4, iclass 27, count 2 2006.173.16:53:33.03#ibcon#about to read 5, iclass 27, count 2 2006.173.16:53:33.03#ibcon#read 5, iclass 27, count 2 2006.173.16:53:33.03#ibcon#about to read 6, iclass 27, count 2 2006.173.16:53:33.03#ibcon#read 6, iclass 27, count 2 2006.173.16:53:33.03#ibcon#end of sib2, iclass 27, count 2 2006.173.16:53:33.03#ibcon#*after write, iclass 27, count 2 2006.173.16:53:33.03#ibcon#*before return 0, iclass 27, count 2 2006.173.16:53:33.03#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.16:53:33.03#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.16:53:33.03#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.16:53:33.03#ibcon#ireg 7 cls_cnt 0 2006.173.16:53:33.03#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.16:53:33.15#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.16:53:33.15#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.16:53:33.15#ibcon#enter wrdev, iclass 27, count 0 2006.173.16:53:33.15#ibcon#first serial, iclass 27, count 0 2006.173.16:53:33.15#ibcon#enter sib2, iclass 27, count 0 2006.173.16:53:33.15#ibcon#flushed, iclass 27, count 0 2006.173.16:53:33.15#ibcon#about to write, iclass 27, count 0 2006.173.16:53:33.15#ibcon#wrote, iclass 27, count 0 2006.173.16:53:33.15#ibcon#about to read 3, iclass 27, count 0 2006.173.16:53:33.17#ibcon#read 3, iclass 27, count 0 2006.173.16:53:33.17#ibcon#about to read 4, iclass 27, count 0 2006.173.16:53:33.17#ibcon#read 4, iclass 27, count 0 2006.173.16:53:33.17#ibcon#about to read 5, iclass 27, count 0 2006.173.16:53:33.17#ibcon#read 5, iclass 27, count 0 2006.173.16:53:33.17#ibcon#about to read 6, iclass 27, count 0 2006.173.16:53:33.17#ibcon#read 6, iclass 27, count 0 2006.173.16:53:33.17#ibcon#end of sib2, iclass 27, count 0 2006.173.16:53:33.17#ibcon#*mode == 0, iclass 27, count 0 2006.173.16:53:33.17#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.16:53:33.17#ibcon#[25=USB\r\n] 2006.173.16:53:33.17#ibcon#*before write, iclass 27, count 0 2006.173.16:53:33.17#ibcon#enter sib2, iclass 27, count 0 2006.173.16:53:33.17#ibcon#flushed, iclass 27, count 0 2006.173.16:53:33.17#ibcon#about to write, iclass 27, count 0 2006.173.16:53:33.17#ibcon#wrote, iclass 27, count 0 2006.173.16:53:33.17#ibcon#about to read 3, iclass 27, count 0 2006.173.16:53:33.20#ibcon#read 3, iclass 27, count 0 2006.173.16:53:33.20#ibcon#about to read 4, iclass 27, count 0 2006.173.16:53:33.20#ibcon#read 4, iclass 27, count 0 2006.173.16:53:33.20#ibcon#about to read 5, iclass 27, count 0 2006.173.16:53:33.20#ibcon#read 5, iclass 27, count 0 2006.173.16:53:33.20#ibcon#about to read 6, iclass 27, count 0 2006.173.16:53:33.20#ibcon#read 6, iclass 27, count 0 2006.173.16:53:33.20#ibcon#end of sib2, iclass 27, count 0 2006.173.16:53:33.20#ibcon#*after write, iclass 27, count 0 2006.173.16:53:33.20#ibcon#*before return 0, iclass 27, count 0 2006.173.16:53:33.20#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.16:53:33.20#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.16:53:33.20#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.16:53:33.20#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.16:53:33.20$vck44/valo=4,624.99 2006.173.16:53:33.20#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.16:53:33.20#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.16:53:33.20#ibcon#ireg 17 cls_cnt 0 2006.173.16:53:33.20#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.16:53:33.20#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.16:53:33.20#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.16:53:33.20#ibcon#enter wrdev, iclass 29, count 0 2006.173.16:53:33.20#ibcon#first serial, iclass 29, count 0 2006.173.16:53:33.20#ibcon#enter sib2, iclass 29, count 0 2006.173.16:53:33.20#ibcon#flushed, iclass 29, count 0 2006.173.16:53:33.20#ibcon#about to write, iclass 29, count 0 2006.173.16:53:33.20#ibcon#wrote, iclass 29, count 0 2006.173.16:53:33.20#ibcon#about to read 3, iclass 29, count 0 2006.173.16:53:33.22#ibcon#read 3, iclass 29, count 0 2006.173.16:53:33.22#ibcon#about to read 4, iclass 29, count 0 2006.173.16:53:33.22#ibcon#read 4, iclass 29, count 0 2006.173.16:53:33.22#ibcon#about to read 5, iclass 29, count 0 2006.173.16:53:33.22#ibcon#read 5, iclass 29, count 0 2006.173.16:53:33.22#ibcon#about to read 6, iclass 29, count 0 2006.173.16:53:33.22#ibcon#read 6, iclass 29, count 0 2006.173.16:53:33.22#ibcon#end of sib2, iclass 29, count 0 2006.173.16:53:33.22#ibcon#*mode == 0, iclass 29, count 0 2006.173.16:53:33.22#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.16:53:33.22#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.16:53:33.22#ibcon#*before write, iclass 29, count 0 2006.173.16:53:33.22#ibcon#enter sib2, iclass 29, count 0 2006.173.16:53:33.22#ibcon#flushed, iclass 29, count 0 2006.173.16:53:33.22#ibcon#about to write, iclass 29, count 0 2006.173.16:53:33.22#ibcon#wrote, iclass 29, count 0 2006.173.16:53:33.22#ibcon#about to read 3, iclass 29, count 0 2006.173.16:53:33.26#ibcon#read 3, iclass 29, count 0 2006.173.16:53:33.26#ibcon#about to read 4, iclass 29, count 0 2006.173.16:53:33.26#ibcon#read 4, iclass 29, count 0 2006.173.16:53:33.26#ibcon#about to read 5, iclass 29, count 0 2006.173.16:53:33.26#ibcon#read 5, iclass 29, count 0 2006.173.16:53:33.26#ibcon#about to read 6, iclass 29, count 0 2006.173.16:53:33.26#ibcon#read 6, iclass 29, count 0 2006.173.16:53:33.26#ibcon#end of sib2, iclass 29, count 0 2006.173.16:53:33.26#ibcon#*after write, iclass 29, count 0 2006.173.16:53:33.26#ibcon#*before return 0, iclass 29, count 0 2006.173.16:53:33.26#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.16:53:33.26#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.16:53:33.26#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.16:53:33.26#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.16:53:33.26$vck44/va=4,6 2006.173.16:53:33.26#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.16:53:33.26#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.16:53:33.26#ibcon#ireg 11 cls_cnt 2 2006.173.16:53:33.26#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.16:53:33.32#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.16:53:33.32#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.16:53:33.32#ibcon#enter wrdev, iclass 31, count 2 2006.173.16:53:33.32#ibcon#first serial, iclass 31, count 2 2006.173.16:53:33.32#ibcon#enter sib2, iclass 31, count 2 2006.173.16:53:33.32#ibcon#flushed, iclass 31, count 2 2006.173.16:53:33.32#ibcon#about to write, iclass 31, count 2 2006.173.16:53:33.32#ibcon#wrote, iclass 31, count 2 2006.173.16:53:33.32#ibcon#about to read 3, iclass 31, count 2 2006.173.16:53:33.34#ibcon#read 3, iclass 31, count 2 2006.173.16:53:33.34#ibcon#about to read 4, iclass 31, count 2 2006.173.16:53:33.34#ibcon#read 4, iclass 31, count 2 2006.173.16:53:33.34#ibcon#about to read 5, iclass 31, count 2 2006.173.16:53:33.34#ibcon#read 5, iclass 31, count 2 2006.173.16:53:33.34#ibcon#about to read 6, iclass 31, count 2 2006.173.16:53:33.34#ibcon#read 6, iclass 31, count 2 2006.173.16:53:33.34#ibcon#end of sib2, iclass 31, count 2 2006.173.16:53:33.34#ibcon#*mode == 0, iclass 31, count 2 2006.173.16:53:33.34#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.16:53:33.34#ibcon#[25=AT04-06\r\n] 2006.173.16:53:33.34#ibcon#*before write, iclass 31, count 2 2006.173.16:53:33.34#ibcon#enter sib2, iclass 31, count 2 2006.173.16:53:33.34#ibcon#flushed, iclass 31, count 2 2006.173.16:53:33.34#ibcon#about to write, iclass 31, count 2 2006.173.16:53:33.34#ibcon#wrote, iclass 31, count 2 2006.173.16:53:33.34#ibcon#about to read 3, iclass 31, count 2 2006.173.16:53:33.37#ibcon#read 3, iclass 31, count 2 2006.173.16:53:33.37#ibcon#about to read 4, iclass 31, count 2 2006.173.16:53:33.37#ibcon#read 4, iclass 31, count 2 2006.173.16:53:33.37#ibcon#about to read 5, iclass 31, count 2 2006.173.16:53:33.37#ibcon#read 5, iclass 31, count 2 2006.173.16:53:33.37#ibcon#about to read 6, iclass 31, count 2 2006.173.16:53:33.37#ibcon#read 6, iclass 31, count 2 2006.173.16:53:33.37#ibcon#end of sib2, iclass 31, count 2 2006.173.16:53:33.37#ibcon#*after write, iclass 31, count 2 2006.173.16:53:33.37#ibcon#*before return 0, iclass 31, count 2 2006.173.16:53:33.37#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.16:53:33.37#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.16:53:33.37#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.16:53:33.37#ibcon#ireg 7 cls_cnt 0 2006.173.16:53:33.37#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.16:53:33.49#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.16:53:33.49#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.16:53:33.49#ibcon#enter wrdev, iclass 31, count 0 2006.173.16:53:33.49#ibcon#first serial, iclass 31, count 0 2006.173.16:53:33.49#ibcon#enter sib2, iclass 31, count 0 2006.173.16:53:33.49#ibcon#flushed, iclass 31, count 0 2006.173.16:53:33.49#ibcon#about to write, iclass 31, count 0 2006.173.16:53:33.49#ibcon#wrote, iclass 31, count 0 2006.173.16:53:33.49#ibcon#about to read 3, iclass 31, count 0 2006.173.16:53:33.51#ibcon#read 3, iclass 31, count 0 2006.173.16:53:33.51#ibcon#about to read 4, iclass 31, count 0 2006.173.16:53:33.51#ibcon#read 4, iclass 31, count 0 2006.173.16:53:33.51#ibcon#about to read 5, iclass 31, count 0 2006.173.16:53:33.51#ibcon#read 5, iclass 31, count 0 2006.173.16:53:33.51#ibcon#about to read 6, iclass 31, count 0 2006.173.16:53:33.51#ibcon#read 6, iclass 31, count 0 2006.173.16:53:33.51#ibcon#end of sib2, iclass 31, count 0 2006.173.16:53:33.51#ibcon#*mode == 0, iclass 31, count 0 2006.173.16:53:33.51#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.16:53:33.51#ibcon#[25=USB\r\n] 2006.173.16:53:33.51#ibcon#*before write, iclass 31, count 0 2006.173.16:53:33.51#ibcon#enter sib2, iclass 31, count 0 2006.173.16:53:33.51#ibcon#flushed, iclass 31, count 0 2006.173.16:53:33.51#ibcon#about to write, iclass 31, count 0 2006.173.16:53:33.51#ibcon#wrote, iclass 31, count 0 2006.173.16:53:33.51#ibcon#about to read 3, iclass 31, count 0 2006.173.16:53:33.54#ibcon#read 3, iclass 31, count 0 2006.173.16:53:33.54#ibcon#about to read 4, iclass 31, count 0 2006.173.16:53:33.54#ibcon#read 4, iclass 31, count 0 2006.173.16:53:33.54#ibcon#about to read 5, iclass 31, count 0 2006.173.16:53:33.54#ibcon#read 5, iclass 31, count 0 2006.173.16:53:33.54#ibcon#about to read 6, iclass 31, count 0 2006.173.16:53:33.54#ibcon#read 6, iclass 31, count 0 2006.173.16:53:33.54#ibcon#end of sib2, iclass 31, count 0 2006.173.16:53:33.54#ibcon#*after write, iclass 31, count 0 2006.173.16:53:33.54#ibcon#*before return 0, iclass 31, count 0 2006.173.16:53:33.54#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.16:53:33.54#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.16:53:33.54#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.16:53:33.54#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.16:53:33.54$vck44/valo=5,734.99 2006.173.16:53:33.54#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.16:53:33.54#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.16:53:33.54#ibcon#ireg 17 cls_cnt 0 2006.173.16:53:33.54#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.16:53:33.54#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.16:53:33.54#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.16:53:33.54#ibcon#enter wrdev, iclass 33, count 0 2006.173.16:53:33.54#ibcon#first serial, iclass 33, count 0 2006.173.16:53:33.54#ibcon#enter sib2, iclass 33, count 0 2006.173.16:53:33.54#ibcon#flushed, iclass 33, count 0 2006.173.16:53:33.54#ibcon#about to write, iclass 33, count 0 2006.173.16:53:33.54#ibcon#wrote, iclass 33, count 0 2006.173.16:53:33.54#ibcon#about to read 3, iclass 33, count 0 2006.173.16:53:33.56#ibcon#read 3, iclass 33, count 0 2006.173.16:53:33.56#ibcon#about to read 4, iclass 33, count 0 2006.173.16:53:33.56#ibcon#read 4, iclass 33, count 0 2006.173.16:53:33.56#ibcon#about to read 5, iclass 33, count 0 2006.173.16:53:33.56#ibcon#read 5, iclass 33, count 0 2006.173.16:53:33.56#ibcon#about to read 6, iclass 33, count 0 2006.173.16:53:33.56#ibcon#read 6, iclass 33, count 0 2006.173.16:53:33.56#ibcon#end of sib2, iclass 33, count 0 2006.173.16:53:33.56#ibcon#*mode == 0, iclass 33, count 0 2006.173.16:53:33.56#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.16:53:33.56#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.16:53:33.56#ibcon#*before write, iclass 33, count 0 2006.173.16:53:33.56#ibcon#enter sib2, iclass 33, count 0 2006.173.16:53:33.56#ibcon#flushed, iclass 33, count 0 2006.173.16:53:33.56#ibcon#about to write, iclass 33, count 0 2006.173.16:53:33.56#ibcon#wrote, iclass 33, count 0 2006.173.16:53:33.56#ibcon#about to read 3, iclass 33, count 0 2006.173.16:53:33.60#ibcon#read 3, iclass 33, count 0 2006.173.16:53:33.60#ibcon#about to read 4, iclass 33, count 0 2006.173.16:53:33.60#ibcon#read 4, iclass 33, count 0 2006.173.16:53:33.60#ibcon#about to read 5, iclass 33, count 0 2006.173.16:53:33.60#ibcon#read 5, iclass 33, count 0 2006.173.16:53:33.60#ibcon#about to read 6, iclass 33, count 0 2006.173.16:53:33.60#ibcon#read 6, iclass 33, count 0 2006.173.16:53:33.60#ibcon#end of sib2, iclass 33, count 0 2006.173.16:53:33.60#ibcon#*after write, iclass 33, count 0 2006.173.16:53:33.60#ibcon#*before return 0, iclass 33, count 0 2006.173.16:53:33.60#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.16:53:33.60#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.16:53:33.60#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.16:53:33.60#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.16:53:33.60$vck44/va=5,4 2006.173.16:53:33.60#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.16:53:33.60#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.16:53:33.60#ibcon#ireg 11 cls_cnt 2 2006.173.16:53:33.60#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.16:53:33.66#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.16:53:33.66#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.16:53:33.66#ibcon#enter wrdev, iclass 35, count 2 2006.173.16:53:33.66#ibcon#first serial, iclass 35, count 2 2006.173.16:53:33.66#ibcon#enter sib2, iclass 35, count 2 2006.173.16:53:33.66#ibcon#flushed, iclass 35, count 2 2006.173.16:53:33.66#ibcon#about to write, iclass 35, count 2 2006.173.16:53:33.66#ibcon#wrote, iclass 35, count 2 2006.173.16:53:33.66#ibcon#about to read 3, iclass 35, count 2 2006.173.16:53:33.68#ibcon#read 3, iclass 35, count 2 2006.173.16:53:33.68#ibcon#about to read 4, iclass 35, count 2 2006.173.16:53:33.68#ibcon#read 4, iclass 35, count 2 2006.173.16:53:33.68#ibcon#about to read 5, iclass 35, count 2 2006.173.16:53:33.68#ibcon#read 5, iclass 35, count 2 2006.173.16:53:33.68#ibcon#about to read 6, iclass 35, count 2 2006.173.16:53:33.68#ibcon#read 6, iclass 35, count 2 2006.173.16:53:33.68#ibcon#end of sib2, iclass 35, count 2 2006.173.16:53:33.68#ibcon#*mode == 0, iclass 35, count 2 2006.173.16:53:33.68#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.16:53:33.68#ibcon#[25=AT05-04\r\n] 2006.173.16:53:33.68#ibcon#*before write, iclass 35, count 2 2006.173.16:53:33.68#ibcon#enter sib2, iclass 35, count 2 2006.173.16:53:33.68#ibcon#flushed, iclass 35, count 2 2006.173.16:53:33.68#ibcon#about to write, iclass 35, count 2 2006.173.16:53:33.68#ibcon#wrote, iclass 35, count 2 2006.173.16:53:33.68#ibcon#about to read 3, iclass 35, count 2 2006.173.16:53:33.71#ibcon#read 3, iclass 35, count 2 2006.173.16:53:33.71#ibcon#about to read 4, iclass 35, count 2 2006.173.16:53:33.71#ibcon#read 4, iclass 35, count 2 2006.173.16:53:33.71#ibcon#about to read 5, iclass 35, count 2 2006.173.16:53:33.71#ibcon#read 5, iclass 35, count 2 2006.173.16:53:33.71#ibcon#about to read 6, iclass 35, count 2 2006.173.16:53:33.71#ibcon#read 6, iclass 35, count 2 2006.173.16:53:33.71#ibcon#end of sib2, iclass 35, count 2 2006.173.16:53:33.71#ibcon#*after write, iclass 35, count 2 2006.173.16:53:33.71#ibcon#*before return 0, iclass 35, count 2 2006.173.16:53:33.71#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.16:53:33.71#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.16:53:33.71#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.16:53:33.71#ibcon#ireg 7 cls_cnt 0 2006.173.16:53:33.71#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.16:53:33.83#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.16:53:33.83#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.16:53:33.83#ibcon#enter wrdev, iclass 35, count 0 2006.173.16:53:33.83#ibcon#first serial, iclass 35, count 0 2006.173.16:53:33.83#ibcon#enter sib2, iclass 35, count 0 2006.173.16:53:33.83#ibcon#flushed, iclass 35, count 0 2006.173.16:53:33.83#ibcon#about to write, iclass 35, count 0 2006.173.16:53:33.83#ibcon#wrote, iclass 35, count 0 2006.173.16:53:33.83#ibcon#about to read 3, iclass 35, count 0 2006.173.16:53:33.85#ibcon#read 3, iclass 35, count 0 2006.173.16:53:33.85#ibcon#about to read 4, iclass 35, count 0 2006.173.16:53:33.85#ibcon#read 4, iclass 35, count 0 2006.173.16:53:33.85#ibcon#about to read 5, iclass 35, count 0 2006.173.16:53:33.85#ibcon#read 5, iclass 35, count 0 2006.173.16:53:33.85#ibcon#about to read 6, iclass 35, count 0 2006.173.16:53:33.85#ibcon#read 6, iclass 35, count 0 2006.173.16:53:33.85#ibcon#end of sib2, iclass 35, count 0 2006.173.16:53:33.85#ibcon#*mode == 0, iclass 35, count 0 2006.173.16:53:33.85#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.16:53:33.85#ibcon#[25=USB\r\n] 2006.173.16:53:33.85#ibcon#*before write, iclass 35, count 0 2006.173.16:53:33.85#ibcon#enter sib2, iclass 35, count 0 2006.173.16:53:33.85#ibcon#flushed, iclass 35, count 0 2006.173.16:53:33.85#ibcon#about to write, iclass 35, count 0 2006.173.16:53:33.85#ibcon#wrote, iclass 35, count 0 2006.173.16:53:33.85#ibcon#about to read 3, iclass 35, count 0 2006.173.16:53:33.88#ibcon#read 3, iclass 35, count 0 2006.173.16:53:33.88#ibcon#about to read 4, iclass 35, count 0 2006.173.16:53:33.88#ibcon#read 4, iclass 35, count 0 2006.173.16:53:33.88#ibcon#about to read 5, iclass 35, count 0 2006.173.16:53:33.88#ibcon#read 5, iclass 35, count 0 2006.173.16:53:33.88#ibcon#about to read 6, iclass 35, count 0 2006.173.16:53:33.88#ibcon#read 6, iclass 35, count 0 2006.173.16:53:33.88#ibcon#end of sib2, iclass 35, count 0 2006.173.16:53:33.88#ibcon#*after write, iclass 35, count 0 2006.173.16:53:33.88#ibcon#*before return 0, iclass 35, count 0 2006.173.16:53:33.88#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.16:53:33.88#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.16:53:33.88#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.16:53:33.88#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.16:53:33.88$vck44/valo=6,814.99 2006.173.16:53:33.88#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.16:53:33.88#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.16:53:33.88#ibcon#ireg 17 cls_cnt 0 2006.173.16:53:33.88#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.16:53:33.88#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.16:53:33.88#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.16:53:33.88#ibcon#enter wrdev, iclass 37, count 0 2006.173.16:53:33.88#ibcon#first serial, iclass 37, count 0 2006.173.16:53:33.88#ibcon#enter sib2, iclass 37, count 0 2006.173.16:53:33.88#ibcon#flushed, iclass 37, count 0 2006.173.16:53:33.88#ibcon#about to write, iclass 37, count 0 2006.173.16:53:33.88#ibcon#wrote, iclass 37, count 0 2006.173.16:53:33.88#ibcon#about to read 3, iclass 37, count 0 2006.173.16:53:33.90#ibcon#read 3, iclass 37, count 0 2006.173.16:53:33.90#ibcon#about to read 4, iclass 37, count 0 2006.173.16:53:33.90#ibcon#read 4, iclass 37, count 0 2006.173.16:53:33.90#ibcon#about to read 5, iclass 37, count 0 2006.173.16:53:33.90#ibcon#read 5, iclass 37, count 0 2006.173.16:53:33.90#ibcon#about to read 6, iclass 37, count 0 2006.173.16:53:33.90#ibcon#read 6, iclass 37, count 0 2006.173.16:53:33.90#ibcon#end of sib2, iclass 37, count 0 2006.173.16:53:33.90#ibcon#*mode == 0, iclass 37, count 0 2006.173.16:53:33.90#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.16:53:33.90#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.16:53:33.90#ibcon#*before write, iclass 37, count 0 2006.173.16:53:33.90#ibcon#enter sib2, iclass 37, count 0 2006.173.16:53:33.90#ibcon#flushed, iclass 37, count 0 2006.173.16:53:33.90#ibcon#about to write, iclass 37, count 0 2006.173.16:53:33.90#ibcon#wrote, iclass 37, count 0 2006.173.16:53:33.90#ibcon#about to read 3, iclass 37, count 0 2006.173.16:53:33.94#ibcon#read 3, iclass 37, count 0 2006.173.16:53:33.94#ibcon#about to read 4, iclass 37, count 0 2006.173.16:53:33.94#ibcon#read 4, iclass 37, count 0 2006.173.16:53:33.94#ibcon#about to read 5, iclass 37, count 0 2006.173.16:53:33.94#ibcon#read 5, iclass 37, count 0 2006.173.16:53:33.94#ibcon#about to read 6, iclass 37, count 0 2006.173.16:53:33.94#ibcon#read 6, iclass 37, count 0 2006.173.16:53:33.94#ibcon#end of sib2, iclass 37, count 0 2006.173.16:53:33.94#ibcon#*after write, iclass 37, count 0 2006.173.16:53:33.94#ibcon#*before return 0, iclass 37, count 0 2006.173.16:53:33.94#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.16:53:33.94#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.16:53:33.94#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.16:53:33.94#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.16:53:33.94$vck44/va=6,3 2006.173.16:53:33.94#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.16:53:33.94#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.16:53:33.94#ibcon#ireg 11 cls_cnt 2 2006.173.16:53:33.94#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.16:53:34.00#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.16:53:34.00#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.16:53:34.00#ibcon#enter wrdev, iclass 39, count 2 2006.173.16:53:34.00#ibcon#first serial, iclass 39, count 2 2006.173.16:53:34.00#ibcon#enter sib2, iclass 39, count 2 2006.173.16:53:34.00#ibcon#flushed, iclass 39, count 2 2006.173.16:53:34.00#ibcon#about to write, iclass 39, count 2 2006.173.16:53:34.00#ibcon#wrote, iclass 39, count 2 2006.173.16:53:34.00#ibcon#about to read 3, iclass 39, count 2 2006.173.16:53:34.02#ibcon#read 3, iclass 39, count 2 2006.173.16:53:34.02#ibcon#about to read 4, iclass 39, count 2 2006.173.16:53:34.02#ibcon#read 4, iclass 39, count 2 2006.173.16:53:34.02#ibcon#about to read 5, iclass 39, count 2 2006.173.16:53:34.02#ibcon#read 5, iclass 39, count 2 2006.173.16:53:34.02#ibcon#about to read 6, iclass 39, count 2 2006.173.16:53:34.02#ibcon#read 6, iclass 39, count 2 2006.173.16:53:34.02#ibcon#end of sib2, iclass 39, count 2 2006.173.16:53:34.02#ibcon#*mode == 0, iclass 39, count 2 2006.173.16:53:34.02#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.16:53:34.02#ibcon#[25=AT06-03\r\n] 2006.173.16:53:34.02#ibcon#*before write, iclass 39, count 2 2006.173.16:53:34.02#ibcon#enter sib2, iclass 39, count 2 2006.173.16:53:34.02#ibcon#flushed, iclass 39, count 2 2006.173.16:53:34.02#ibcon#about to write, iclass 39, count 2 2006.173.16:53:34.02#ibcon#wrote, iclass 39, count 2 2006.173.16:53:34.02#ibcon#about to read 3, iclass 39, count 2 2006.173.16:53:34.05#ibcon#read 3, iclass 39, count 2 2006.173.16:53:34.05#ibcon#about to read 4, iclass 39, count 2 2006.173.16:53:34.05#ibcon#read 4, iclass 39, count 2 2006.173.16:53:34.05#ibcon#about to read 5, iclass 39, count 2 2006.173.16:53:34.05#ibcon#read 5, iclass 39, count 2 2006.173.16:53:34.05#ibcon#about to read 6, iclass 39, count 2 2006.173.16:53:34.05#ibcon#read 6, iclass 39, count 2 2006.173.16:53:34.05#ibcon#end of sib2, iclass 39, count 2 2006.173.16:53:34.05#ibcon#*after write, iclass 39, count 2 2006.173.16:53:34.05#ibcon#*before return 0, iclass 39, count 2 2006.173.16:53:34.05#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.16:53:34.05#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.16:53:34.05#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.16:53:34.05#ibcon#ireg 7 cls_cnt 0 2006.173.16:53:34.05#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.16:53:34.17#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.16:53:34.17#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.16:53:34.17#ibcon#enter wrdev, iclass 39, count 0 2006.173.16:53:34.17#ibcon#first serial, iclass 39, count 0 2006.173.16:53:34.17#ibcon#enter sib2, iclass 39, count 0 2006.173.16:53:34.17#ibcon#flushed, iclass 39, count 0 2006.173.16:53:34.17#ibcon#about to write, iclass 39, count 0 2006.173.16:53:34.17#ibcon#wrote, iclass 39, count 0 2006.173.16:53:34.17#ibcon#about to read 3, iclass 39, count 0 2006.173.16:53:34.19#ibcon#read 3, iclass 39, count 0 2006.173.16:53:34.19#ibcon#about to read 4, iclass 39, count 0 2006.173.16:53:34.19#ibcon#read 4, iclass 39, count 0 2006.173.16:53:34.19#ibcon#about to read 5, iclass 39, count 0 2006.173.16:53:34.19#ibcon#read 5, iclass 39, count 0 2006.173.16:53:34.19#ibcon#about to read 6, iclass 39, count 0 2006.173.16:53:34.19#ibcon#read 6, iclass 39, count 0 2006.173.16:53:34.19#ibcon#end of sib2, iclass 39, count 0 2006.173.16:53:34.19#ibcon#*mode == 0, iclass 39, count 0 2006.173.16:53:34.19#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.16:53:34.19#ibcon#[25=USB\r\n] 2006.173.16:53:34.19#ibcon#*before write, iclass 39, count 0 2006.173.16:53:34.19#ibcon#enter sib2, iclass 39, count 0 2006.173.16:53:34.19#ibcon#flushed, iclass 39, count 0 2006.173.16:53:34.19#ibcon#about to write, iclass 39, count 0 2006.173.16:53:34.19#ibcon#wrote, iclass 39, count 0 2006.173.16:53:34.19#ibcon#about to read 3, iclass 39, count 0 2006.173.16:53:34.22#ibcon#read 3, iclass 39, count 0 2006.173.16:53:34.22#ibcon#about to read 4, iclass 39, count 0 2006.173.16:53:34.22#ibcon#read 4, iclass 39, count 0 2006.173.16:53:34.22#ibcon#about to read 5, iclass 39, count 0 2006.173.16:53:34.22#ibcon#read 5, iclass 39, count 0 2006.173.16:53:34.22#ibcon#about to read 6, iclass 39, count 0 2006.173.16:53:34.22#ibcon#read 6, iclass 39, count 0 2006.173.16:53:34.22#ibcon#end of sib2, iclass 39, count 0 2006.173.16:53:34.22#ibcon#*after write, iclass 39, count 0 2006.173.16:53:34.22#ibcon#*before return 0, iclass 39, count 0 2006.173.16:53:34.22#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.16:53:34.22#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.16:53:34.22#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.16:53:34.22#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.16:53:34.22$vck44/valo=7,864.99 2006.173.16:53:34.22#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.16:53:34.22#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.16:53:34.22#ibcon#ireg 17 cls_cnt 0 2006.173.16:53:34.22#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.16:53:34.22#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.16:53:34.22#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.16:53:34.22#ibcon#enter wrdev, iclass 3, count 0 2006.173.16:53:34.22#ibcon#first serial, iclass 3, count 0 2006.173.16:53:34.22#ibcon#enter sib2, iclass 3, count 0 2006.173.16:53:34.22#ibcon#flushed, iclass 3, count 0 2006.173.16:53:34.22#ibcon#about to write, iclass 3, count 0 2006.173.16:53:34.22#ibcon#wrote, iclass 3, count 0 2006.173.16:53:34.22#ibcon#about to read 3, iclass 3, count 0 2006.173.16:53:34.24#ibcon#read 3, iclass 3, count 0 2006.173.16:53:34.24#ibcon#about to read 4, iclass 3, count 0 2006.173.16:53:34.24#ibcon#read 4, iclass 3, count 0 2006.173.16:53:34.24#ibcon#about to read 5, iclass 3, count 0 2006.173.16:53:34.24#ibcon#read 5, iclass 3, count 0 2006.173.16:53:34.24#ibcon#about to read 6, iclass 3, count 0 2006.173.16:53:34.24#ibcon#read 6, iclass 3, count 0 2006.173.16:53:34.24#ibcon#end of sib2, iclass 3, count 0 2006.173.16:53:34.24#ibcon#*mode == 0, iclass 3, count 0 2006.173.16:53:34.24#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.16:53:34.24#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.16:53:34.24#ibcon#*before write, iclass 3, count 0 2006.173.16:53:34.24#ibcon#enter sib2, iclass 3, count 0 2006.173.16:53:34.24#ibcon#flushed, iclass 3, count 0 2006.173.16:53:34.24#ibcon#about to write, iclass 3, count 0 2006.173.16:53:34.24#ibcon#wrote, iclass 3, count 0 2006.173.16:53:34.24#ibcon#about to read 3, iclass 3, count 0 2006.173.16:53:34.28#ibcon#read 3, iclass 3, count 0 2006.173.16:53:34.28#ibcon#about to read 4, iclass 3, count 0 2006.173.16:53:34.28#ibcon#read 4, iclass 3, count 0 2006.173.16:53:34.28#ibcon#about to read 5, iclass 3, count 0 2006.173.16:53:34.28#ibcon#read 5, iclass 3, count 0 2006.173.16:53:34.28#ibcon#about to read 6, iclass 3, count 0 2006.173.16:53:34.28#ibcon#read 6, iclass 3, count 0 2006.173.16:53:34.28#ibcon#end of sib2, iclass 3, count 0 2006.173.16:53:34.28#ibcon#*after write, iclass 3, count 0 2006.173.16:53:34.28#ibcon#*before return 0, iclass 3, count 0 2006.173.16:53:34.28#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.16:53:34.28#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.16:53:34.28#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.16:53:34.28#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.16:53:34.28$vck44/va=7,4 2006.173.16:53:34.28#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.16:53:34.28#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.16:53:34.28#ibcon#ireg 11 cls_cnt 2 2006.173.16:53:34.28#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.16:53:34.34#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.16:53:34.34#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.16:53:34.34#ibcon#enter wrdev, iclass 5, count 2 2006.173.16:53:34.34#ibcon#first serial, iclass 5, count 2 2006.173.16:53:34.34#ibcon#enter sib2, iclass 5, count 2 2006.173.16:53:34.34#ibcon#flushed, iclass 5, count 2 2006.173.16:53:34.34#ibcon#about to write, iclass 5, count 2 2006.173.16:53:34.34#ibcon#wrote, iclass 5, count 2 2006.173.16:53:34.34#ibcon#about to read 3, iclass 5, count 2 2006.173.16:53:34.36#ibcon#read 3, iclass 5, count 2 2006.173.16:53:34.36#ibcon#about to read 4, iclass 5, count 2 2006.173.16:53:34.36#ibcon#read 4, iclass 5, count 2 2006.173.16:53:34.36#ibcon#about to read 5, iclass 5, count 2 2006.173.16:53:34.36#ibcon#read 5, iclass 5, count 2 2006.173.16:53:34.36#ibcon#about to read 6, iclass 5, count 2 2006.173.16:53:34.36#ibcon#read 6, iclass 5, count 2 2006.173.16:53:34.36#ibcon#end of sib2, iclass 5, count 2 2006.173.16:53:34.36#ibcon#*mode == 0, iclass 5, count 2 2006.173.16:53:34.36#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.16:53:34.36#ibcon#[25=AT07-04\r\n] 2006.173.16:53:34.36#ibcon#*before write, iclass 5, count 2 2006.173.16:53:34.36#ibcon#enter sib2, iclass 5, count 2 2006.173.16:53:34.36#ibcon#flushed, iclass 5, count 2 2006.173.16:53:34.36#ibcon#about to write, iclass 5, count 2 2006.173.16:53:34.36#ibcon#wrote, iclass 5, count 2 2006.173.16:53:34.36#ibcon#about to read 3, iclass 5, count 2 2006.173.16:53:34.39#ibcon#read 3, iclass 5, count 2 2006.173.16:53:34.39#ibcon#about to read 4, iclass 5, count 2 2006.173.16:53:34.39#ibcon#read 4, iclass 5, count 2 2006.173.16:53:34.39#ibcon#about to read 5, iclass 5, count 2 2006.173.16:53:34.39#ibcon#read 5, iclass 5, count 2 2006.173.16:53:34.39#ibcon#about to read 6, iclass 5, count 2 2006.173.16:53:34.39#ibcon#read 6, iclass 5, count 2 2006.173.16:53:34.39#ibcon#end of sib2, iclass 5, count 2 2006.173.16:53:34.39#ibcon#*after write, iclass 5, count 2 2006.173.16:53:34.39#ibcon#*before return 0, iclass 5, count 2 2006.173.16:53:34.39#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.16:53:34.39#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.16:53:34.39#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.16:53:34.39#ibcon#ireg 7 cls_cnt 0 2006.173.16:53:34.39#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.16:53:34.51#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.16:53:34.51#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.16:53:34.51#ibcon#enter wrdev, iclass 5, count 0 2006.173.16:53:34.51#ibcon#first serial, iclass 5, count 0 2006.173.16:53:34.51#ibcon#enter sib2, iclass 5, count 0 2006.173.16:53:34.51#ibcon#flushed, iclass 5, count 0 2006.173.16:53:34.51#ibcon#about to write, iclass 5, count 0 2006.173.16:53:34.51#ibcon#wrote, iclass 5, count 0 2006.173.16:53:34.51#ibcon#about to read 3, iclass 5, count 0 2006.173.16:53:34.53#ibcon#read 3, iclass 5, count 0 2006.173.16:53:34.53#ibcon#about to read 4, iclass 5, count 0 2006.173.16:53:34.53#ibcon#read 4, iclass 5, count 0 2006.173.16:53:34.53#ibcon#about to read 5, iclass 5, count 0 2006.173.16:53:34.53#ibcon#read 5, iclass 5, count 0 2006.173.16:53:34.53#ibcon#about to read 6, iclass 5, count 0 2006.173.16:53:34.53#ibcon#read 6, iclass 5, count 0 2006.173.16:53:34.53#ibcon#end of sib2, iclass 5, count 0 2006.173.16:53:34.53#ibcon#*mode == 0, iclass 5, count 0 2006.173.16:53:34.53#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.16:53:34.53#ibcon#[25=USB\r\n] 2006.173.16:53:34.53#ibcon#*before write, iclass 5, count 0 2006.173.16:53:34.53#ibcon#enter sib2, iclass 5, count 0 2006.173.16:53:34.53#ibcon#flushed, iclass 5, count 0 2006.173.16:53:34.53#ibcon#about to write, iclass 5, count 0 2006.173.16:53:34.53#ibcon#wrote, iclass 5, count 0 2006.173.16:53:34.53#ibcon#about to read 3, iclass 5, count 0 2006.173.16:53:34.56#ibcon#read 3, iclass 5, count 0 2006.173.16:53:34.56#ibcon#about to read 4, iclass 5, count 0 2006.173.16:53:34.56#ibcon#read 4, iclass 5, count 0 2006.173.16:53:34.56#ibcon#about to read 5, iclass 5, count 0 2006.173.16:53:34.56#ibcon#read 5, iclass 5, count 0 2006.173.16:53:34.56#ibcon#about to read 6, iclass 5, count 0 2006.173.16:53:34.56#ibcon#read 6, iclass 5, count 0 2006.173.16:53:34.56#ibcon#end of sib2, iclass 5, count 0 2006.173.16:53:34.56#ibcon#*after write, iclass 5, count 0 2006.173.16:53:34.56#ibcon#*before return 0, iclass 5, count 0 2006.173.16:53:34.56#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.16:53:34.56#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.16:53:34.56#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.16:53:34.56#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.16:53:34.56$vck44/valo=8,884.99 2006.173.16:53:34.56#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.16:53:34.56#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.16:53:34.56#ibcon#ireg 17 cls_cnt 0 2006.173.16:53:34.56#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.16:53:34.56#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.16:53:34.56#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.16:53:34.56#ibcon#enter wrdev, iclass 7, count 0 2006.173.16:53:34.56#ibcon#first serial, iclass 7, count 0 2006.173.16:53:34.56#ibcon#enter sib2, iclass 7, count 0 2006.173.16:53:34.56#ibcon#flushed, iclass 7, count 0 2006.173.16:53:34.56#ibcon#about to write, iclass 7, count 0 2006.173.16:53:34.56#ibcon#wrote, iclass 7, count 0 2006.173.16:53:34.56#ibcon#about to read 3, iclass 7, count 0 2006.173.16:53:34.58#ibcon#read 3, iclass 7, count 0 2006.173.16:53:34.58#ibcon#about to read 4, iclass 7, count 0 2006.173.16:53:34.58#ibcon#read 4, iclass 7, count 0 2006.173.16:53:34.58#ibcon#about to read 5, iclass 7, count 0 2006.173.16:53:34.58#ibcon#read 5, iclass 7, count 0 2006.173.16:53:34.58#ibcon#about to read 6, iclass 7, count 0 2006.173.16:53:34.58#ibcon#read 6, iclass 7, count 0 2006.173.16:53:34.58#ibcon#end of sib2, iclass 7, count 0 2006.173.16:53:34.58#ibcon#*mode == 0, iclass 7, count 0 2006.173.16:53:34.58#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.16:53:34.58#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.16:53:34.58#ibcon#*before write, iclass 7, count 0 2006.173.16:53:34.58#ibcon#enter sib2, iclass 7, count 0 2006.173.16:53:34.58#ibcon#flushed, iclass 7, count 0 2006.173.16:53:34.58#ibcon#about to write, iclass 7, count 0 2006.173.16:53:34.58#ibcon#wrote, iclass 7, count 0 2006.173.16:53:34.58#ibcon#about to read 3, iclass 7, count 0 2006.173.16:53:34.62#ibcon#read 3, iclass 7, count 0 2006.173.16:53:34.62#ibcon#about to read 4, iclass 7, count 0 2006.173.16:53:34.62#ibcon#read 4, iclass 7, count 0 2006.173.16:53:34.62#ibcon#about to read 5, iclass 7, count 0 2006.173.16:53:34.62#ibcon#read 5, iclass 7, count 0 2006.173.16:53:34.62#ibcon#about to read 6, iclass 7, count 0 2006.173.16:53:34.62#ibcon#read 6, iclass 7, count 0 2006.173.16:53:34.62#ibcon#end of sib2, iclass 7, count 0 2006.173.16:53:34.62#ibcon#*after write, iclass 7, count 0 2006.173.16:53:34.62#ibcon#*before return 0, iclass 7, count 0 2006.173.16:53:34.62#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.16:53:34.62#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.16:53:34.62#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.16:53:34.62#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.16:53:34.62$vck44/va=8,4 2006.173.16:53:34.62#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.16:53:34.62#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.16:53:34.62#ibcon#ireg 11 cls_cnt 2 2006.173.16:53:34.62#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.16:53:34.68#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.16:53:34.68#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.16:53:34.68#ibcon#enter wrdev, iclass 11, count 2 2006.173.16:53:34.68#ibcon#first serial, iclass 11, count 2 2006.173.16:53:34.68#ibcon#enter sib2, iclass 11, count 2 2006.173.16:53:34.68#ibcon#flushed, iclass 11, count 2 2006.173.16:53:34.68#ibcon#about to write, iclass 11, count 2 2006.173.16:53:34.68#ibcon#wrote, iclass 11, count 2 2006.173.16:53:34.68#ibcon#about to read 3, iclass 11, count 2 2006.173.16:53:34.70#ibcon#read 3, iclass 11, count 2 2006.173.16:53:34.70#ibcon#about to read 4, iclass 11, count 2 2006.173.16:53:34.70#ibcon#read 4, iclass 11, count 2 2006.173.16:53:34.70#ibcon#about to read 5, iclass 11, count 2 2006.173.16:53:34.70#ibcon#read 5, iclass 11, count 2 2006.173.16:53:34.70#ibcon#about to read 6, iclass 11, count 2 2006.173.16:53:34.70#ibcon#read 6, iclass 11, count 2 2006.173.16:53:34.70#ibcon#end of sib2, iclass 11, count 2 2006.173.16:53:34.70#ibcon#*mode == 0, iclass 11, count 2 2006.173.16:53:34.70#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.16:53:34.70#ibcon#[25=AT08-04\r\n] 2006.173.16:53:34.70#ibcon#*before write, iclass 11, count 2 2006.173.16:53:34.70#ibcon#enter sib2, iclass 11, count 2 2006.173.16:53:34.70#ibcon#flushed, iclass 11, count 2 2006.173.16:53:34.70#ibcon#about to write, iclass 11, count 2 2006.173.16:53:34.70#ibcon#wrote, iclass 11, count 2 2006.173.16:53:34.70#ibcon#about to read 3, iclass 11, count 2 2006.173.16:53:34.73#ibcon#read 3, iclass 11, count 2 2006.173.16:53:34.73#ibcon#about to read 4, iclass 11, count 2 2006.173.16:53:34.73#ibcon#read 4, iclass 11, count 2 2006.173.16:53:34.73#ibcon#about to read 5, iclass 11, count 2 2006.173.16:53:34.73#ibcon#read 5, iclass 11, count 2 2006.173.16:53:34.73#ibcon#about to read 6, iclass 11, count 2 2006.173.16:53:34.73#ibcon#read 6, iclass 11, count 2 2006.173.16:53:34.73#ibcon#end of sib2, iclass 11, count 2 2006.173.16:53:34.73#ibcon#*after write, iclass 11, count 2 2006.173.16:53:34.73#ibcon#*before return 0, iclass 11, count 2 2006.173.16:53:34.73#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.16:53:34.73#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.16:53:34.73#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.16:53:34.73#ibcon#ireg 7 cls_cnt 0 2006.173.16:53:34.73#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.16:53:34.85#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.16:53:34.85#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.16:53:34.85#ibcon#enter wrdev, iclass 11, count 0 2006.173.16:53:34.85#ibcon#first serial, iclass 11, count 0 2006.173.16:53:34.85#ibcon#enter sib2, iclass 11, count 0 2006.173.16:53:34.85#ibcon#flushed, iclass 11, count 0 2006.173.16:53:34.85#ibcon#about to write, iclass 11, count 0 2006.173.16:53:34.85#ibcon#wrote, iclass 11, count 0 2006.173.16:53:34.85#ibcon#about to read 3, iclass 11, count 0 2006.173.16:53:34.87#ibcon#read 3, iclass 11, count 0 2006.173.16:53:34.87#ibcon#about to read 4, iclass 11, count 0 2006.173.16:53:34.87#ibcon#read 4, iclass 11, count 0 2006.173.16:53:34.87#ibcon#about to read 5, iclass 11, count 0 2006.173.16:53:34.87#ibcon#read 5, iclass 11, count 0 2006.173.16:53:34.87#ibcon#about to read 6, iclass 11, count 0 2006.173.16:53:34.87#ibcon#read 6, iclass 11, count 0 2006.173.16:53:34.87#ibcon#end of sib2, iclass 11, count 0 2006.173.16:53:34.87#ibcon#*mode == 0, iclass 11, count 0 2006.173.16:53:34.87#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.16:53:34.87#ibcon#[25=USB\r\n] 2006.173.16:53:34.87#ibcon#*before write, iclass 11, count 0 2006.173.16:53:34.87#ibcon#enter sib2, iclass 11, count 0 2006.173.16:53:34.87#ibcon#flushed, iclass 11, count 0 2006.173.16:53:34.87#ibcon#about to write, iclass 11, count 0 2006.173.16:53:34.87#ibcon#wrote, iclass 11, count 0 2006.173.16:53:34.87#ibcon#about to read 3, iclass 11, count 0 2006.173.16:53:34.90#ibcon#read 3, iclass 11, count 0 2006.173.16:53:34.90#ibcon#about to read 4, iclass 11, count 0 2006.173.16:53:34.90#ibcon#read 4, iclass 11, count 0 2006.173.16:53:34.90#ibcon#about to read 5, iclass 11, count 0 2006.173.16:53:34.90#ibcon#read 5, iclass 11, count 0 2006.173.16:53:34.90#ibcon#about to read 6, iclass 11, count 0 2006.173.16:53:34.90#ibcon#read 6, iclass 11, count 0 2006.173.16:53:34.90#ibcon#end of sib2, iclass 11, count 0 2006.173.16:53:34.90#ibcon#*after write, iclass 11, count 0 2006.173.16:53:34.90#ibcon#*before return 0, iclass 11, count 0 2006.173.16:53:34.90#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.16:53:34.90#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.16:53:34.90#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.16:53:34.90#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.16:53:34.90$vck44/vblo=1,629.99 2006.173.16:53:34.90#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.16:53:34.90#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.16:53:34.90#ibcon#ireg 17 cls_cnt 0 2006.173.16:53:34.90#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.16:53:34.90#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.16:53:34.90#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.16:53:34.90#ibcon#enter wrdev, iclass 13, count 0 2006.173.16:53:34.90#ibcon#first serial, iclass 13, count 0 2006.173.16:53:34.90#ibcon#enter sib2, iclass 13, count 0 2006.173.16:53:34.90#ibcon#flushed, iclass 13, count 0 2006.173.16:53:34.90#ibcon#about to write, iclass 13, count 0 2006.173.16:53:34.90#ibcon#wrote, iclass 13, count 0 2006.173.16:53:34.90#ibcon#about to read 3, iclass 13, count 0 2006.173.16:53:34.92#ibcon#read 3, iclass 13, count 0 2006.173.16:53:34.92#ibcon#about to read 4, iclass 13, count 0 2006.173.16:53:34.92#ibcon#read 4, iclass 13, count 0 2006.173.16:53:34.92#ibcon#about to read 5, iclass 13, count 0 2006.173.16:53:34.92#ibcon#read 5, iclass 13, count 0 2006.173.16:53:34.92#ibcon#about to read 6, iclass 13, count 0 2006.173.16:53:34.92#ibcon#read 6, iclass 13, count 0 2006.173.16:53:34.92#ibcon#end of sib2, iclass 13, count 0 2006.173.16:53:34.92#ibcon#*mode == 0, iclass 13, count 0 2006.173.16:53:34.92#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.16:53:34.92#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.16:53:34.92#ibcon#*before write, iclass 13, count 0 2006.173.16:53:34.92#ibcon#enter sib2, iclass 13, count 0 2006.173.16:53:34.92#ibcon#flushed, iclass 13, count 0 2006.173.16:53:34.92#ibcon#about to write, iclass 13, count 0 2006.173.16:53:34.92#ibcon#wrote, iclass 13, count 0 2006.173.16:53:34.92#ibcon#about to read 3, iclass 13, count 0 2006.173.16:53:34.96#ibcon#read 3, iclass 13, count 0 2006.173.16:53:34.96#ibcon#about to read 4, iclass 13, count 0 2006.173.16:53:34.96#ibcon#read 4, iclass 13, count 0 2006.173.16:53:34.96#ibcon#about to read 5, iclass 13, count 0 2006.173.16:53:34.96#ibcon#read 5, iclass 13, count 0 2006.173.16:53:34.96#ibcon#about to read 6, iclass 13, count 0 2006.173.16:53:34.96#ibcon#read 6, iclass 13, count 0 2006.173.16:53:34.96#ibcon#end of sib2, iclass 13, count 0 2006.173.16:53:34.96#ibcon#*after write, iclass 13, count 0 2006.173.16:53:34.96#ibcon#*before return 0, iclass 13, count 0 2006.173.16:53:34.96#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.16:53:34.96#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.16:53:34.96#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.16:53:34.96#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.16:53:34.96$vck44/vb=1,4 2006.173.16:53:34.96#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.16:53:34.96#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.16:53:34.96#ibcon#ireg 11 cls_cnt 2 2006.173.16:53:34.96#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.16:53:34.96#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.16:53:34.96#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.16:53:34.96#ibcon#enter wrdev, iclass 15, count 2 2006.173.16:53:34.96#ibcon#first serial, iclass 15, count 2 2006.173.16:53:34.96#ibcon#enter sib2, iclass 15, count 2 2006.173.16:53:34.96#ibcon#flushed, iclass 15, count 2 2006.173.16:53:34.96#ibcon#about to write, iclass 15, count 2 2006.173.16:53:34.96#ibcon#wrote, iclass 15, count 2 2006.173.16:53:34.96#ibcon#about to read 3, iclass 15, count 2 2006.173.16:53:34.98#ibcon#read 3, iclass 15, count 2 2006.173.16:53:34.98#ibcon#about to read 4, iclass 15, count 2 2006.173.16:53:34.98#ibcon#read 4, iclass 15, count 2 2006.173.16:53:34.98#ibcon#about to read 5, iclass 15, count 2 2006.173.16:53:34.98#ibcon#read 5, iclass 15, count 2 2006.173.16:53:34.98#ibcon#about to read 6, iclass 15, count 2 2006.173.16:53:34.98#ibcon#read 6, iclass 15, count 2 2006.173.16:53:34.98#ibcon#end of sib2, iclass 15, count 2 2006.173.16:53:34.98#ibcon#*mode == 0, iclass 15, count 2 2006.173.16:53:34.98#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.16:53:34.98#ibcon#[27=AT01-04\r\n] 2006.173.16:53:34.98#ibcon#*before write, iclass 15, count 2 2006.173.16:53:34.98#ibcon#enter sib2, iclass 15, count 2 2006.173.16:53:34.98#ibcon#flushed, iclass 15, count 2 2006.173.16:53:34.98#ibcon#about to write, iclass 15, count 2 2006.173.16:53:34.98#ibcon#wrote, iclass 15, count 2 2006.173.16:53:34.98#ibcon#about to read 3, iclass 15, count 2 2006.173.16:53:35.01#ibcon#read 3, iclass 15, count 2 2006.173.16:53:35.01#ibcon#about to read 4, iclass 15, count 2 2006.173.16:53:35.01#ibcon#read 4, iclass 15, count 2 2006.173.16:53:35.01#ibcon#about to read 5, iclass 15, count 2 2006.173.16:53:35.01#ibcon#read 5, iclass 15, count 2 2006.173.16:53:35.01#ibcon#about to read 6, iclass 15, count 2 2006.173.16:53:35.01#ibcon#read 6, iclass 15, count 2 2006.173.16:53:35.01#ibcon#end of sib2, iclass 15, count 2 2006.173.16:53:35.01#ibcon#*after write, iclass 15, count 2 2006.173.16:53:35.01#ibcon#*before return 0, iclass 15, count 2 2006.173.16:53:35.01#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.16:53:35.01#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.16:53:35.01#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.16:53:35.01#ibcon#ireg 7 cls_cnt 0 2006.173.16:53:35.01#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.16:53:35.13#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.16:53:35.13#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.16:53:35.13#ibcon#enter wrdev, iclass 15, count 0 2006.173.16:53:35.13#ibcon#first serial, iclass 15, count 0 2006.173.16:53:35.13#ibcon#enter sib2, iclass 15, count 0 2006.173.16:53:35.13#ibcon#flushed, iclass 15, count 0 2006.173.16:53:35.13#ibcon#about to write, iclass 15, count 0 2006.173.16:53:35.13#ibcon#wrote, iclass 15, count 0 2006.173.16:53:35.13#ibcon#about to read 3, iclass 15, count 0 2006.173.16:53:35.15#ibcon#read 3, iclass 15, count 0 2006.173.16:53:35.15#ibcon#about to read 4, iclass 15, count 0 2006.173.16:53:35.15#ibcon#read 4, iclass 15, count 0 2006.173.16:53:35.15#ibcon#about to read 5, iclass 15, count 0 2006.173.16:53:35.15#ibcon#read 5, iclass 15, count 0 2006.173.16:53:35.15#ibcon#about to read 6, iclass 15, count 0 2006.173.16:53:35.15#ibcon#read 6, iclass 15, count 0 2006.173.16:53:35.15#ibcon#end of sib2, iclass 15, count 0 2006.173.16:53:35.15#ibcon#*mode == 0, iclass 15, count 0 2006.173.16:53:35.15#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.16:53:35.15#ibcon#[27=USB\r\n] 2006.173.16:53:35.15#ibcon#*before write, iclass 15, count 0 2006.173.16:53:35.15#ibcon#enter sib2, iclass 15, count 0 2006.173.16:53:35.15#ibcon#flushed, iclass 15, count 0 2006.173.16:53:35.15#ibcon#about to write, iclass 15, count 0 2006.173.16:53:35.15#ibcon#wrote, iclass 15, count 0 2006.173.16:53:35.15#ibcon#about to read 3, iclass 15, count 0 2006.173.16:53:35.18#ibcon#read 3, iclass 15, count 0 2006.173.16:53:35.18#ibcon#about to read 4, iclass 15, count 0 2006.173.16:53:35.18#ibcon#read 4, iclass 15, count 0 2006.173.16:53:35.18#ibcon#about to read 5, iclass 15, count 0 2006.173.16:53:35.18#ibcon#read 5, iclass 15, count 0 2006.173.16:53:35.18#ibcon#about to read 6, iclass 15, count 0 2006.173.16:53:35.18#ibcon#read 6, iclass 15, count 0 2006.173.16:53:35.18#ibcon#end of sib2, iclass 15, count 0 2006.173.16:53:35.18#ibcon#*after write, iclass 15, count 0 2006.173.16:53:35.18#ibcon#*before return 0, iclass 15, count 0 2006.173.16:53:35.18#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.16:53:35.18#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.16:53:35.18#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.16:53:35.18#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.16:53:35.18$vck44/vblo=2,634.99 2006.173.16:53:35.18#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.16:53:35.18#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.16:53:35.18#ibcon#ireg 17 cls_cnt 0 2006.173.16:53:35.18#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.16:53:35.18#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.16:53:35.18#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.16:53:35.18#ibcon#enter wrdev, iclass 17, count 0 2006.173.16:53:35.18#ibcon#first serial, iclass 17, count 0 2006.173.16:53:35.18#ibcon#enter sib2, iclass 17, count 0 2006.173.16:53:35.18#ibcon#flushed, iclass 17, count 0 2006.173.16:53:35.18#ibcon#about to write, iclass 17, count 0 2006.173.16:53:35.18#ibcon#wrote, iclass 17, count 0 2006.173.16:53:35.18#ibcon#about to read 3, iclass 17, count 0 2006.173.16:53:35.20#ibcon#read 3, iclass 17, count 0 2006.173.16:53:35.20#ibcon#about to read 4, iclass 17, count 0 2006.173.16:53:35.20#ibcon#read 4, iclass 17, count 0 2006.173.16:53:35.20#ibcon#about to read 5, iclass 17, count 0 2006.173.16:53:35.20#ibcon#read 5, iclass 17, count 0 2006.173.16:53:35.20#ibcon#about to read 6, iclass 17, count 0 2006.173.16:53:35.20#ibcon#read 6, iclass 17, count 0 2006.173.16:53:35.20#ibcon#end of sib2, iclass 17, count 0 2006.173.16:53:35.20#ibcon#*mode == 0, iclass 17, count 0 2006.173.16:53:35.20#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.16:53:35.20#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.16:53:35.20#ibcon#*before write, iclass 17, count 0 2006.173.16:53:35.20#ibcon#enter sib2, iclass 17, count 0 2006.173.16:53:35.20#ibcon#flushed, iclass 17, count 0 2006.173.16:53:35.20#ibcon#about to write, iclass 17, count 0 2006.173.16:53:35.20#ibcon#wrote, iclass 17, count 0 2006.173.16:53:35.20#ibcon#about to read 3, iclass 17, count 0 2006.173.16:53:35.24#ibcon#read 3, iclass 17, count 0 2006.173.16:53:35.24#ibcon#about to read 4, iclass 17, count 0 2006.173.16:53:35.24#ibcon#read 4, iclass 17, count 0 2006.173.16:53:35.24#ibcon#about to read 5, iclass 17, count 0 2006.173.16:53:35.24#ibcon#read 5, iclass 17, count 0 2006.173.16:53:35.24#ibcon#about to read 6, iclass 17, count 0 2006.173.16:53:35.24#ibcon#read 6, iclass 17, count 0 2006.173.16:53:35.24#ibcon#end of sib2, iclass 17, count 0 2006.173.16:53:35.24#ibcon#*after write, iclass 17, count 0 2006.173.16:53:35.24#ibcon#*before return 0, iclass 17, count 0 2006.173.16:53:35.24#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.16:53:35.24#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.16:53:35.24#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.16:53:35.24#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.16:53:35.24$vck44/vb=2,4 2006.173.16:53:35.24#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.16:53:35.24#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.16:53:35.24#ibcon#ireg 11 cls_cnt 2 2006.173.16:53:35.24#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.16:53:35.30#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.16:53:35.30#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.16:53:35.30#ibcon#enter wrdev, iclass 19, count 2 2006.173.16:53:35.30#ibcon#first serial, iclass 19, count 2 2006.173.16:53:35.30#ibcon#enter sib2, iclass 19, count 2 2006.173.16:53:35.30#ibcon#flushed, iclass 19, count 2 2006.173.16:53:35.30#ibcon#about to write, iclass 19, count 2 2006.173.16:53:35.30#ibcon#wrote, iclass 19, count 2 2006.173.16:53:35.30#ibcon#about to read 3, iclass 19, count 2 2006.173.16:53:35.32#ibcon#read 3, iclass 19, count 2 2006.173.16:53:35.32#ibcon#about to read 4, iclass 19, count 2 2006.173.16:53:35.32#ibcon#read 4, iclass 19, count 2 2006.173.16:53:35.32#ibcon#about to read 5, iclass 19, count 2 2006.173.16:53:35.32#ibcon#read 5, iclass 19, count 2 2006.173.16:53:35.32#ibcon#about to read 6, iclass 19, count 2 2006.173.16:53:35.32#ibcon#read 6, iclass 19, count 2 2006.173.16:53:35.32#ibcon#end of sib2, iclass 19, count 2 2006.173.16:53:35.32#ibcon#*mode == 0, iclass 19, count 2 2006.173.16:53:35.32#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.16:53:35.32#ibcon#[27=AT02-04\r\n] 2006.173.16:53:35.32#ibcon#*before write, iclass 19, count 2 2006.173.16:53:35.32#ibcon#enter sib2, iclass 19, count 2 2006.173.16:53:35.32#ibcon#flushed, iclass 19, count 2 2006.173.16:53:35.32#ibcon#about to write, iclass 19, count 2 2006.173.16:53:35.32#ibcon#wrote, iclass 19, count 2 2006.173.16:53:35.32#ibcon#about to read 3, iclass 19, count 2 2006.173.16:53:35.35#ibcon#read 3, iclass 19, count 2 2006.173.16:53:35.35#ibcon#about to read 4, iclass 19, count 2 2006.173.16:53:35.35#ibcon#read 4, iclass 19, count 2 2006.173.16:53:35.35#ibcon#about to read 5, iclass 19, count 2 2006.173.16:53:35.35#ibcon#read 5, iclass 19, count 2 2006.173.16:53:35.35#ibcon#about to read 6, iclass 19, count 2 2006.173.16:53:35.35#ibcon#read 6, iclass 19, count 2 2006.173.16:53:35.35#ibcon#end of sib2, iclass 19, count 2 2006.173.16:53:35.35#ibcon#*after write, iclass 19, count 2 2006.173.16:53:35.35#ibcon#*before return 0, iclass 19, count 2 2006.173.16:53:35.35#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.16:53:35.35#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.16:53:35.35#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.16:53:35.35#ibcon#ireg 7 cls_cnt 0 2006.173.16:53:35.35#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.16:53:35.47#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.16:53:35.47#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.16:53:35.47#ibcon#enter wrdev, iclass 19, count 0 2006.173.16:53:35.47#ibcon#first serial, iclass 19, count 0 2006.173.16:53:35.47#ibcon#enter sib2, iclass 19, count 0 2006.173.16:53:35.47#ibcon#flushed, iclass 19, count 0 2006.173.16:53:35.47#ibcon#about to write, iclass 19, count 0 2006.173.16:53:35.47#ibcon#wrote, iclass 19, count 0 2006.173.16:53:35.47#ibcon#about to read 3, iclass 19, count 0 2006.173.16:53:35.49#ibcon#read 3, iclass 19, count 0 2006.173.16:53:35.49#ibcon#about to read 4, iclass 19, count 0 2006.173.16:53:35.49#ibcon#read 4, iclass 19, count 0 2006.173.16:53:35.49#ibcon#about to read 5, iclass 19, count 0 2006.173.16:53:35.49#ibcon#read 5, iclass 19, count 0 2006.173.16:53:35.49#ibcon#about to read 6, iclass 19, count 0 2006.173.16:53:35.49#ibcon#read 6, iclass 19, count 0 2006.173.16:53:35.49#ibcon#end of sib2, iclass 19, count 0 2006.173.16:53:35.49#ibcon#*mode == 0, iclass 19, count 0 2006.173.16:53:35.49#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.16:53:35.49#ibcon#[27=USB\r\n] 2006.173.16:53:35.49#ibcon#*before write, iclass 19, count 0 2006.173.16:53:35.49#ibcon#enter sib2, iclass 19, count 0 2006.173.16:53:35.49#ibcon#flushed, iclass 19, count 0 2006.173.16:53:35.49#ibcon#about to write, iclass 19, count 0 2006.173.16:53:35.49#ibcon#wrote, iclass 19, count 0 2006.173.16:53:35.49#ibcon#about to read 3, iclass 19, count 0 2006.173.16:53:35.52#ibcon#read 3, iclass 19, count 0 2006.173.16:53:35.52#ibcon#about to read 4, iclass 19, count 0 2006.173.16:53:35.52#ibcon#read 4, iclass 19, count 0 2006.173.16:53:35.52#ibcon#about to read 5, iclass 19, count 0 2006.173.16:53:35.52#ibcon#read 5, iclass 19, count 0 2006.173.16:53:35.52#ibcon#about to read 6, iclass 19, count 0 2006.173.16:53:35.52#ibcon#read 6, iclass 19, count 0 2006.173.16:53:35.52#ibcon#end of sib2, iclass 19, count 0 2006.173.16:53:35.52#ibcon#*after write, iclass 19, count 0 2006.173.16:53:35.52#ibcon#*before return 0, iclass 19, count 0 2006.173.16:53:35.52#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.16:53:35.52#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.16:53:35.52#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.16:53:35.52#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.16:53:35.52$vck44/vblo=3,649.99 2006.173.16:53:35.52#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.16:53:35.52#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.16:53:35.52#ibcon#ireg 17 cls_cnt 0 2006.173.16:53:35.52#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.16:53:35.52#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.16:53:35.52#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.16:53:35.52#ibcon#enter wrdev, iclass 21, count 0 2006.173.16:53:35.52#ibcon#first serial, iclass 21, count 0 2006.173.16:53:35.52#ibcon#enter sib2, iclass 21, count 0 2006.173.16:53:35.52#ibcon#flushed, iclass 21, count 0 2006.173.16:53:35.52#ibcon#about to write, iclass 21, count 0 2006.173.16:53:35.52#ibcon#wrote, iclass 21, count 0 2006.173.16:53:35.52#ibcon#about to read 3, iclass 21, count 0 2006.173.16:53:35.54#ibcon#read 3, iclass 21, count 0 2006.173.16:53:35.54#ibcon#about to read 4, iclass 21, count 0 2006.173.16:53:35.54#ibcon#read 4, iclass 21, count 0 2006.173.16:53:35.54#ibcon#about to read 5, iclass 21, count 0 2006.173.16:53:35.54#ibcon#read 5, iclass 21, count 0 2006.173.16:53:35.54#ibcon#about to read 6, iclass 21, count 0 2006.173.16:53:35.54#ibcon#read 6, iclass 21, count 0 2006.173.16:53:35.54#ibcon#end of sib2, iclass 21, count 0 2006.173.16:53:35.54#ibcon#*mode == 0, iclass 21, count 0 2006.173.16:53:35.54#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.16:53:35.54#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.16:53:35.54#ibcon#*before write, iclass 21, count 0 2006.173.16:53:35.54#ibcon#enter sib2, iclass 21, count 0 2006.173.16:53:35.54#ibcon#flushed, iclass 21, count 0 2006.173.16:53:35.54#ibcon#about to write, iclass 21, count 0 2006.173.16:53:35.54#ibcon#wrote, iclass 21, count 0 2006.173.16:53:35.54#ibcon#about to read 3, iclass 21, count 0 2006.173.16:53:35.58#ibcon#read 3, iclass 21, count 0 2006.173.16:53:35.58#ibcon#about to read 4, iclass 21, count 0 2006.173.16:53:35.58#ibcon#read 4, iclass 21, count 0 2006.173.16:53:35.58#ibcon#about to read 5, iclass 21, count 0 2006.173.16:53:35.58#ibcon#read 5, iclass 21, count 0 2006.173.16:53:35.58#ibcon#about to read 6, iclass 21, count 0 2006.173.16:53:35.58#ibcon#read 6, iclass 21, count 0 2006.173.16:53:35.58#ibcon#end of sib2, iclass 21, count 0 2006.173.16:53:35.58#ibcon#*after write, iclass 21, count 0 2006.173.16:53:35.58#ibcon#*before return 0, iclass 21, count 0 2006.173.16:53:35.58#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.16:53:35.58#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.16:53:35.58#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.16:53:35.58#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.16:53:35.58$vck44/vb=3,4 2006.173.16:53:35.58#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.16:53:35.58#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.16:53:35.58#ibcon#ireg 11 cls_cnt 2 2006.173.16:53:35.58#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.16:53:35.64#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.16:53:35.64#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.16:53:35.64#ibcon#enter wrdev, iclass 23, count 2 2006.173.16:53:35.64#ibcon#first serial, iclass 23, count 2 2006.173.16:53:35.64#ibcon#enter sib2, iclass 23, count 2 2006.173.16:53:35.64#ibcon#flushed, iclass 23, count 2 2006.173.16:53:35.64#ibcon#about to write, iclass 23, count 2 2006.173.16:53:35.64#ibcon#wrote, iclass 23, count 2 2006.173.16:53:35.64#ibcon#about to read 3, iclass 23, count 2 2006.173.16:53:35.66#ibcon#read 3, iclass 23, count 2 2006.173.16:53:35.66#ibcon#about to read 4, iclass 23, count 2 2006.173.16:53:35.66#ibcon#read 4, iclass 23, count 2 2006.173.16:53:35.66#ibcon#about to read 5, iclass 23, count 2 2006.173.16:53:35.66#ibcon#read 5, iclass 23, count 2 2006.173.16:53:35.66#ibcon#about to read 6, iclass 23, count 2 2006.173.16:53:35.66#ibcon#read 6, iclass 23, count 2 2006.173.16:53:35.66#ibcon#end of sib2, iclass 23, count 2 2006.173.16:53:35.66#ibcon#*mode == 0, iclass 23, count 2 2006.173.16:53:35.66#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.16:53:35.66#ibcon#[27=AT03-04\r\n] 2006.173.16:53:35.66#ibcon#*before write, iclass 23, count 2 2006.173.16:53:35.66#ibcon#enter sib2, iclass 23, count 2 2006.173.16:53:35.66#ibcon#flushed, iclass 23, count 2 2006.173.16:53:35.66#ibcon#about to write, iclass 23, count 2 2006.173.16:53:35.66#ibcon#wrote, iclass 23, count 2 2006.173.16:53:35.66#ibcon#about to read 3, iclass 23, count 2 2006.173.16:53:35.69#ibcon#read 3, iclass 23, count 2 2006.173.16:53:35.69#ibcon#about to read 4, iclass 23, count 2 2006.173.16:53:35.69#ibcon#read 4, iclass 23, count 2 2006.173.16:53:35.69#ibcon#about to read 5, iclass 23, count 2 2006.173.16:53:35.69#ibcon#read 5, iclass 23, count 2 2006.173.16:53:35.69#ibcon#about to read 6, iclass 23, count 2 2006.173.16:53:35.69#ibcon#read 6, iclass 23, count 2 2006.173.16:53:35.69#ibcon#end of sib2, iclass 23, count 2 2006.173.16:53:35.69#ibcon#*after write, iclass 23, count 2 2006.173.16:53:35.69#ibcon#*before return 0, iclass 23, count 2 2006.173.16:53:35.69#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.16:53:35.69#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.16:53:35.69#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.16:53:35.69#ibcon#ireg 7 cls_cnt 0 2006.173.16:53:35.69#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.16:53:35.81#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.16:53:35.81#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.16:53:35.81#ibcon#enter wrdev, iclass 23, count 0 2006.173.16:53:35.81#ibcon#first serial, iclass 23, count 0 2006.173.16:53:35.81#ibcon#enter sib2, iclass 23, count 0 2006.173.16:53:35.81#ibcon#flushed, iclass 23, count 0 2006.173.16:53:35.81#ibcon#about to write, iclass 23, count 0 2006.173.16:53:35.81#ibcon#wrote, iclass 23, count 0 2006.173.16:53:35.81#ibcon#about to read 3, iclass 23, count 0 2006.173.16:53:35.83#ibcon#read 3, iclass 23, count 0 2006.173.16:53:35.83#ibcon#about to read 4, iclass 23, count 0 2006.173.16:53:35.83#ibcon#read 4, iclass 23, count 0 2006.173.16:53:35.83#ibcon#about to read 5, iclass 23, count 0 2006.173.16:53:35.83#ibcon#read 5, iclass 23, count 0 2006.173.16:53:35.83#ibcon#about to read 6, iclass 23, count 0 2006.173.16:53:35.83#ibcon#read 6, iclass 23, count 0 2006.173.16:53:35.83#ibcon#end of sib2, iclass 23, count 0 2006.173.16:53:35.83#ibcon#*mode == 0, iclass 23, count 0 2006.173.16:53:35.83#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.16:53:35.83#ibcon#[27=USB\r\n] 2006.173.16:53:35.83#ibcon#*before write, iclass 23, count 0 2006.173.16:53:35.83#ibcon#enter sib2, iclass 23, count 0 2006.173.16:53:35.83#ibcon#flushed, iclass 23, count 0 2006.173.16:53:35.83#ibcon#about to write, iclass 23, count 0 2006.173.16:53:35.83#ibcon#wrote, iclass 23, count 0 2006.173.16:53:35.83#ibcon#about to read 3, iclass 23, count 0 2006.173.16:53:35.86#ibcon#read 3, iclass 23, count 0 2006.173.16:53:35.86#ibcon#about to read 4, iclass 23, count 0 2006.173.16:53:35.86#ibcon#read 4, iclass 23, count 0 2006.173.16:53:35.86#ibcon#about to read 5, iclass 23, count 0 2006.173.16:53:35.86#ibcon#read 5, iclass 23, count 0 2006.173.16:53:35.86#ibcon#about to read 6, iclass 23, count 0 2006.173.16:53:35.86#ibcon#read 6, iclass 23, count 0 2006.173.16:53:35.86#ibcon#end of sib2, iclass 23, count 0 2006.173.16:53:35.86#ibcon#*after write, iclass 23, count 0 2006.173.16:53:35.86#ibcon#*before return 0, iclass 23, count 0 2006.173.16:53:35.86#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.16:53:35.86#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.16:53:35.86#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.16:53:35.86#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.16:53:35.86$vck44/vblo=4,679.99 2006.173.16:53:35.86#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.16:53:35.86#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.16:53:35.86#ibcon#ireg 17 cls_cnt 0 2006.173.16:53:35.86#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.16:53:35.86#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.16:53:35.86#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.16:53:35.86#ibcon#enter wrdev, iclass 25, count 0 2006.173.16:53:35.86#ibcon#first serial, iclass 25, count 0 2006.173.16:53:35.86#ibcon#enter sib2, iclass 25, count 0 2006.173.16:53:35.86#ibcon#flushed, iclass 25, count 0 2006.173.16:53:35.86#ibcon#about to write, iclass 25, count 0 2006.173.16:53:35.86#ibcon#wrote, iclass 25, count 0 2006.173.16:53:35.86#ibcon#about to read 3, iclass 25, count 0 2006.173.16:53:35.88#ibcon#read 3, iclass 25, count 0 2006.173.16:53:35.88#ibcon#about to read 4, iclass 25, count 0 2006.173.16:53:35.88#ibcon#read 4, iclass 25, count 0 2006.173.16:53:35.88#ibcon#about to read 5, iclass 25, count 0 2006.173.16:53:35.88#ibcon#read 5, iclass 25, count 0 2006.173.16:53:35.88#ibcon#about to read 6, iclass 25, count 0 2006.173.16:53:35.88#ibcon#read 6, iclass 25, count 0 2006.173.16:53:35.88#ibcon#end of sib2, iclass 25, count 0 2006.173.16:53:35.88#ibcon#*mode == 0, iclass 25, count 0 2006.173.16:53:35.88#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.16:53:35.88#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.16:53:35.88#ibcon#*before write, iclass 25, count 0 2006.173.16:53:35.88#ibcon#enter sib2, iclass 25, count 0 2006.173.16:53:35.88#ibcon#flushed, iclass 25, count 0 2006.173.16:53:35.88#ibcon#about to write, iclass 25, count 0 2006.173.16:53:35.88#ibcon#wrote, iclass 25, count 0 2006.173.16:53:35.88#ibcon#about to read 3, iclass 25, count 0 2006.173.16:53:35.92#ibcon#read 3, iclass 25, count 0 2006.173.16:53:35.92#ibcon#about to read 4, iclass 25, count 0 2006.173.16:53:35.92#ibcon#read 4, iclass 25, count 0 2006.173.16:53:35.92#ibcon#about to read 5, iclass 25, count 0 2006.173.16:53:35.92#ibcon#read 5, iclass 25, count 0 2006.173.16:53:35.92#ibcon#about to read 6, iclass 25, count 0 2006.173.16:53:35.92#ibcon#read 6, iclass 25, count 0 2006.173.16:53:35.92#ibcon#end of sib2, iclass 25, count 0 2006.173.16:53:35.92#ibcon#*after write, iclass 25, count 0 2006.173.16:53:35.92#ibcon#*before return 0, iclass 25, count 0 2006.173.16:53:35.92#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.16:53:35.92#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.16:53:35.92#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.16:53:35.92#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.16:53:35.92$vck44/vb=4,4 2006.173.16:53:35.92#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.16:53:35.92#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.16:53:35.92#ibcon#ireg 11 cls_cnt 2 2006.173.16:53:35.92#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.16:53:35.98#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.16:53:35.98#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.16:53:35.98#ibcon#enter wrdev, iclass 27, count 2 2006.173.16:53:35.98#ibcon#first serial, iclass 27, count 2 2006.173.16:53:35.98#ibcon#enter sib2, iclass 27, count 2 2006.173.16:53:35.98#ibcon#flushed, iclass 27, count 2 2006.173.16:53:35.98#ibcon#about to write, iclass 27, count 2 2006.173.16:53:35.98#ibcon#wrote, iclass 27, count 2 2006.173.16:53:35.98#ibcon#about to read 3, iclass 27, count 2 2006.173.16:53:36.00#ibcon#read 3, iclass 27, count 2 2006.173.16:53:36.00#ibcon#about to read 4, iclass 27, count 2 2006.173.16:53:36.00#ibcon#read 4, iclass 27, count 2 2006.173.16:53:36.00#ibcon#about to read 5, iclass 27, count 2 2006.173.16:53:36.00#ibcon#read 5, iclass 27, count 2 2006.173.16:53:36.00#ibcon#about to read 6, iclass 27, count 2 2006.173.16:53:36.00#ibcon#read 6, iclass 27, count 2 2006.173.16:53:36.00#ibcon#end of sib2, iclass 27, count 2 2006.173.16:53:36.00#ibcon#*mode == 0, iclass 27, count 2 2006.173.16:53:36.00#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.16:53:36.00#ibcon#[27=AT04-04\r\n] 2006.173.16:53:36.00#ibcon#*before write, iclass 27, count 2 2006.173.16:53:36.00#ibcon#enter sib2, iclass 27, count 2 2006.173.16:53:36.00#ibcon#flushed, iclass 27, count 2 2006.173.16:53:36.00#ibcon#about to write, iclass 27, count 2 2006.173.16:53:36.00#ibcon#wrote, iclass 27, count 2 2006.173.16:53:36.00#ibcon#about to read 3, iclass 27, count 2 2006.173.16:53:36.03#ibcon#read 3, iclass 27, count 2 2006.173.16:53:36.03#ibcon#about to read 4, iclass 27, count 2 2006.173.16:53:36.03#ibcon#read 4, iclass 27, count 2 2006.173.16:53:36.03#ibcon#about to read 5, iclass 27, count 2 2006.173.16:53:36.03#ibcon#read 5, iclass 27, count 2 2006.173.16:53:36.03#ibcon#about to read 6, iclass 27, count 2 2006.173.16:53:36.03#ibcon#read 6, iclass 27, count 2 2006.173.16:53:36.03#ibcon#end of sib2, iclass 27, count 2 2006.173.16:53:36.03#ibcon#*after write, iclass 27, count 2 2006.173.16:53:36.03#ibcon#*before return 0, iclass 27, count 2 2006.173.16:53:36.03#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.16:53:36.03#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.16:53:36.03#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.16:53:36.03#ibcon#ireg 7 cls_cnt 0 2006.173.16:53:36.03#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.16:53:36.15#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.16:53:36.15#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.16:53:36.15#ibcon#enter wrdev, iclass 27, count 0 2006.173.16:53:36.15#ibcon#first serial, iclass 27, count 0 2006.173.16:53:36.15#ibcon#enter sib2, iclass 27, count 0 2006.173.16:53:36.15#ibcon#flushed, iclass 27, count 0 2006.173.16:53:36.15#ibcon#about to write, iclass 27, count 0 2006.173.16:53:36.15#ibcon#wrote, iclass 27, count 0 2006.173.16:53:36.15#ibcon#about to read 3, iclass 27, count 0 2006.173.16:53:36.17#ibcon#read 3, iclass 27, count 0 2006.173.16:53:36.17#ibcon#about to read 4, iclass 27, count 0 2006.173.16:53:36.17#ibcon#read 4, iclass 27, count 0 2006.173.16:53:36.17#ibcon#about to read 5, iclass 27, count 0 2006.173.16:53:36.17#ibcon#read 5, iclass 27, count 0 2006.173.16:53:36.17#ibcon#about to read 6, iclass 27, count 0 2006.173.16:53:36.17#ibcon#read 6, iclass 27, count 0 2006.173.16:53:36.17#ibcon#end of sib2, iclass 27, count 0 2006.173.16:53:36.17#ibcon#*mode == 0, iclass 27, count 0 2006.173.16:53:36.17#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.16:53:36.17#ibcon#[27=USB\r\n] 2006.173.16:53:36.17#ibcon#*before write, iclass 27, count 0 2006.173.16:53:36.17#ibcon#enter sib2, iclass 27, count 0 2006.173.16:53:36.17#ibcon#flushed, iclass 27, count 0 2006.173.16:53:36.17#ibcon#about to write, iclass 27, count 0 2006.173.16:53:36.17#ibcon#wrote, iclass 27, count 0 2006.173.16:53:36.17#ibcon#about to read 3, iclass 27, count 0 2006.173.16:53:36.20#ibcon#read 3, iclass 27, count 0 2006.173.16:53:36.20#ibcon#about to read 4, iclass 27, count 0 2006.173.16:53:36.20#ibcon#read 4, iclass 27, count 0 2006.173.16:53:36.20#ibcon#about to read 5, iclass 27, count 0 2006.173.16:53:36.20#ibcon#read 5, iclass 27, count 0 2006.173.16:53:36.20#ibcon#about to read 6, iclass 27, count 0 2006.173.16:53:36.20#ibcon#read 6, iclass 27, count 0 2006.173.16:53:36.20#ibcon#end of sib2, iclass 27, count 0 2006.173.16:53:36.20#ibcon#*after write, iclass 27, count 0 2006.173.16:53:36.20#ibcon#*before return 0, iclass 27, count 0 2006.173.16:53:36.20#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.16:53:36.20#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.16:53:36.20#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.16:53:36.20#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.16:53:36.20$vck44/vblo=5,709.99 2006.173.16:53:36.20#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.16:53:36.20#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.16:53:36.20#ibcon#ireg 17 cls_cnt 0 2006.173.16:53:36.20#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.16:53:36.20#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.16:53:36.20#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.16:53:36.20#ibcon#enter wrdev, iclass 29, count 0 2006.173.16:53:36.20#ibcon#first serial, iclass 29, count 0 2006.173.16:53:36.20#ibcon#enter sib2, iclass 29, count 0 2006.173.16:53:36.20#ibcon#flushed, iclass 29, count 0 2006.173.16:53:36.20#ibcon#about to write, iclass 29, count 0 2006.173.16:53:36.20#ibcon#wrote, iclass 29, count 0 2006.173.16:53:36.20#ibcon#about to read 3, iclass 29, count 0 2006.173.16:53:36.22#ibcon#read 3, iclass 29, count 0 2006.173.16:53:36.22#ibcon#about to read 4, iclass 29, count 0 2006.173.16:53:36.22#ibcon#read 4, iclass 29, count 0 2006.173.16:53:36.22#ibcon#about to read 5, iclass 29, count 0 2006.173.16:53:36.22#ibcon#read 5, iclass 29, count 0 2006.173.16:53:36.22#ibcon#about to read 6, iclass 29, count 0 2006.173.16:53:36.22#ibcon#read 6, iclass 29, count 0 2006.173.16:53:36.22#ibcon#end of sib2, iclass 29, count 0 2006.173.16:53:36.22#ibcon#*mode == 0, iclass 29, count 0 2006.173.16:53:36.22#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.16:53:36.22#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.16:53:36.22#ibcon#*before write, iclass 29, count 0 2006.173.16:53:36.22#ibcon#enter sib2, iclass 29, count 0 2006.173.16:53:36.22#ibcon#flushed, iclass 29, count 0 2006.173.16:53:36.22#ibcon#about to write, iclass 29, count 0 2006.173.16:53:36.22#ibcon#wrote, iclass 29, count 0 2006.173.16:53:36.22#ibcon#about to read 3, iclass 29, count 0 2006.173.16:53:36.26#ibcon#read 3, iclass 29, count 0 2006.173.16:53:36.26#ibcon#about to read 4, iclass 29, count 0 2006.173.16:53:36.26#ibcon#read 4, iclass 29, count 0 2006.173.16:53:36.26#ibcon#about to read 5, iclass 29, count 0 2006.173.16:53:36.26#ibcon#read 5, iclass 29, count 0 2006.173.16:53:36.26#ibcon#about to read 6, iclass 29, count 0 2006.173.16:53:36.26#ibcon#read 6, iclass 29, count 0 2006.173.16:53:36.26#ibcon#end of sib2, iclass 29, count 0 2006.173.16:53:36.26#ibcon#*after write, iclass 29, count 0 2006.173.16:53:36.26#ibcon#*before return 0, iclass 29, count 0 2006.173.16:53:36.26#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.16:53:36.26#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.16:53:36.26#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.16:53:36.26#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.16:53:36.26$vck44/vb=5,4 2006.173.16:53:36.26#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.16:53:36.26#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.16:53:36.26#ibcon#ireg 11 cls_cnt 2 2006.173.16:53:36.26#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.16:53:36.32#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.16:53:36.32#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.16:53:36.32#ibcon#enter wrdev, iclass 31, count 2 2006.173.16:53:36.32#ibcon#first serial, iclass 31, count 2 2006.173.16:53:36.32#ibcon#enter sib2, iclass 31, count 2 2006.173.16:53:36.32#ibcon#flushed, iclass 31, count 2 2006.173.16:53:36.32#ibcon#about to write, iclass 31, count 2 2006.173.16:53:36.32#ibcon#wrote, iclass 31, count 2 2006.173.16:53:36.32#ibcon#about to read 3, iclass 31, count 2 2006.173.16:53:36.34#ibcon#read 3, iclass 31, count 2 2006.173.16:53:36.34#ibcon#about to read 4, iclass 31, count 2 2006.173.16:53:36.34#ibcon#read 4, iclass 31, count 2 2006.173.16:53:36.34#ibcon#about to read 5, iclass 31, count 2 2006.173.16:53:36.34#ibcon#read 5, iclass 31, count 2 2006.173.16:53:36.34#ibcon#about to read 6, iclass 31, count 2 2006.173.16:53:36.34#ibcon#read 6, iclass 31, count 2 2006.173.16:53:36.34#ibcon#end of sib2, iclass 31, count 2 2006.173.16:53:36.34#ibcon#*mode == 0, iclass 31, count 2 2006.173.16:53:36.34#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.16:53:36.34#ibcon#[27=AT05-04\r\n] 2006.173.16:53:36.34#ibcon#*before write, iclass 31, count 2 2006.173.16:53:36.34#ibcon#enter sib2, iclass 31, count 2 2006.173.16:53:36.34#ibcon#flushed, iclass 31, count 2 2006.173.16:53:36.34#ibcon#about to write, iclass 31, count 2 2006.173.16:53:36.34#ibcon#wrote, iclass 31, count 2 2006.173.16:53:36.34#ibcon#about to read 3, iclass 31, count 2 2006.173.16:53:36.37#ibcon#read 3, iclass 31, count 2 2006.173.16:53:36.37#ibcon#about to read 4, iclass 31, count 2 2006.173.16:53:36.37#ibcon#read 4, iclass 31, count 2 2006.173.16:53:36.37#ibcon#about to read 5, iclass 31, count 2 2006.173.16:53:36.37#ibcon#read 5, iclass 31, count 2 2006.173.16:53:36.37#ibcon#about to read 6, iclass 31, count 2 2006.173.16:53:36.37#ibcon#read 6, iclass 31, count 2 2006.173.16:53:36.37#ibcon#end of sib2, iclass 31, count 2 2006.173.16:53:36.37#ibcon#*after write, iclass 31, count 2 2006.173.16:53:36.37#ibcon#*before return 0, iclass 31, count 2 2006.173.16:53:36.37#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.16:53:36.37#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.16:53:36.37#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.16:53:36.37#ibcon#ireg 7 cls_cnt 0 2006.173.16:53:36.37#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.16:53:36.49#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.16:53:36.49#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.16:53:36.49#ibcon#enter wrdev, iclass 31, count 0 2006.173.16:53:36.49#ibcon#first serial, iclass 31, count 0 2006.173.16:53:36.49#ibcon#enter sib2, iclass 31, count 0 2006.173.16:53:36.49#ibcon#flushed, iclass 31, count 0 2006.173.16:53:36.49#ibcon#about to write, iclass 31, count 0 2006.173.16:53:36.49#ibcon#wrote, iclass 31, count 0 2006.173.16:53:36.49#ibcon#about to read 3, iclass 31, count 0 2006.173.16:53:36.51#ibcon#read 3, iclass 31, count 0 2006.173.16:53:36.51#ibcon#about to read 4, iclass 31, count 0 2006.173.16:53:36.51#ibcon#read 4, iclass 31, count 0 2006.173.16:53:36.51#ibcon#about to read 5, iclass 31, count 0 2006.173.16:53:36.51#ibcon#read 5, iclass 31, count 0 2006.173.16:53:36.51#ibcon#about to read 6, iclass 31, count 0 2006.173.16:53:36.51#ibcon#read 6, iclass 31, count 0 2006.173.16:53:36.51#ibcon#end of sib2, iclass 31, count 0 2006.173.16:53:36.51#ibcon#*mode == 0, iclass 31, count 0 2006.173.16:53:36.51#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.16:53:36.51#ibcon#[27=USB\r\n] 2006.173.16:53:36.51#ibcon#*before write, iclass 31, count 0 2006.173.16:53:36.51#ibcon#enter sib2, iclass 31, count 0 2006.173.16:53:36.51#ibcon#flushed, iclass 31, count 0 2006.173.16:53:36.51#ibcon#about to write, iclass 31, count 0 2006.173.16:53:36.51#ibcon#wrote, iclass 31, count 0 2006.173.16:53:36.51#ibcon#about to read 3, iclass 31, count 0 2006.173.16:53:36.54#ibcon#read 3, iclass 31, count 0 2006.173.16:53:36.54#ibcon#about to read 4, iclass 31, count 0 2006.173.16:53:36.54#ibcon#read 4, iclass 31, count 0 2006.173.16:53:36.54#ibcon#about to read 5, iclass 31, count 0 2006.173.16:53:36.54#ibcon#read 5, iclass 31, count 0 2006.173.16:53:36.54#ibcon#about to read 6, iclass 31, count 0 2006.173.16:53:36.54#ibcon#read 6, iclass 31, count 0 2006.173.16:53:36.54#ibcon#end of sib2, iclass 31, count 0 2006.173.16:53:36.54#ibcon#*after write, iclass 31, count 0 2006.173.16:53:36.54#ibcon#*before return 0, iclass 31, count 0 2006.173.16:53:36.54#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.16:53:36.54#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.16:53:36.54#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.16:53:36.54#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.16:53:36.54$vck44/vblo=6,719.99 2006.173.16:53:36.54#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.16:53:36.54#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.16:53:36.54#ibcon#ireg 17 cls_cnt 0 2006.173.16:53:36.54#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.16:53:36.54#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.16:53:36.54#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.16:53:36.54#ibcon#enter wrdev, iclass 33, count 0 2006.173.16:53:36.54#ibcon#first serial, iclass 33, count 0 2006.173.16:53:36.54#ibcon#enter sib2, iclass 33, count 0 2006.173.16:53:36.54#ibcon#flushed, iclass 33, count 0 2006.173.16:53:36.54#ibcon#about to write, iclass 33, count 0 2006.173.16:53:36.54#ibcon#wrote, iclass 33, count 0 2006.173.16:53:36.54#ibcon#about to read 3, iclass 33, count 0 2006.173.16:53:36.56#ibcon#read 3, iclass 33, count 0 2006.173.16:53:36.56#ibcon#about to read 4, iclass 33, count 0 2006.173.16:53:36.56#ibcon#read 4, iclass 33, count 0 2006.173.16:53:36.56#ibcon#about to read 5, iclass 33, count 0 2006.173.16:53:36.56#ibcon#read 5, iclass 33, count 0 2006.173.16:53:36.56#ibcon#about to read 6, iclass 33, count 0 2006.173.16:53:36.56#ibcon#read 6, iclass 33, count 0 2006.173.16:53:36.56#ibcon#end of sib2, iclass 33, count 0 2006.173.16:53:36.56#ibcon#*mode == 0, iclass 33, count 0 2006.173.16:53:36.56#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.16:53:36.56#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.16:53:36.56#ibcon#*before write, iclass 33, count 0 2006.173.16:53:36.56#ibcon#enter sib2, iclass 33, count 0 2006.173.16:53:36.56#ibcon#flushed, iclass 33, count 0 2006.173.16:53:36.56#ibcon#about to write, iclass 33, count 0 2006.173.16:53:36.56#ibcon#wrote, iclass 33, count 0 2006.173.16:53:36.56#ibcon#about to read 3, iclass 33, count 0 2006.173.16:53:36.60#ibcon#read 3, iclass 33, count 0 2006.173.16:53:36.60#ibcon#about to read 4, iclass 33, count 0 2006.173.16:53:36.60#ibcon#read 4, iclass 33, count 0 2006.173.16:53:36.60#ibcon#about to read 5, iclass 33, count 0 2006.173.16:53:36.60#ibcon#read 5, iclass 33, count 0 2006.173.16:53:36.60#ibcon#about to read 6, iclass 33, count 0 2006.173.16:53:36.60#ibcon#read 6, iclass 33, count 0 2006.173.16:53:36.60#ibcon#end of sib2, iclass 33, count 0 2006.173.16:53:36.60#ibcon#*after write, iclass 33, count 0 2006.173.16:53:36.60#ibcon#*before return 0, iclass 33, count 0 2006.173.16:53:36.60#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.16:53:36.60#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.16:53:36.60#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.16:53:36.60#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.16:53:36.60$vck44/vb=6,4 2006.173.16:53:36.60#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.16:53:36.60#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.16:53:36.60#ibcon#ireg 11 cls_cnt 2 2006.173.16:53:36.60#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.16:53:36.66#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.16:53:36.66#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.16:53:36.66#ibcon#enter wrdev, iclass 35, count 2 2006.173.16:53:36.66#ibcon#first serial, iclass 35, count 2 2006.173.16:53:36.66#ibcon#enter sib2, iclass 35, count 2 2006.173.16:53:36.66#ibcon#flushed, iclass 35, count 2 2006.173.16:53:36.66#ibcon#about to write, iclass 35, count 2 2006.173.16:53:36.66#ibcon#wrote, iclass 35, count 2 2006.173.16:53:36.66#ibcon#about to read 3, iclass 35, count 2 2006.173.16:53:36.68#ibcon#read 3, iclass 35, count 2 2006.173.16:53:36.68#ibcon#about to read 4, iclass 35, count 2 2006.173.16:53:36.68#ibcon#read 4, iclass 35, count 2 2006.173.16:53:36.68#ibcon#about to read 5, iclass 35, count 2 2006.173.16:53:36.68#ibcon#read 5, iclass 35, count 2 2006.173.16:53:36.68#ibcon#about to read 6, iclass 35, count 2 2006.173.16:53:36.68#ibcon#read 6, iclass 35, count 2 2006.173.16:53:36.68#ibcon#end of sib2, iclass 35, count 2 2006.173.16:53:36.68#ibcon#*mode == 0, iclass 35, count 2 2006.173.16:53:36.68#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.16:53:36.68#ibcon#[27=AT06-04\r\n] 2006.173.16:53:36.68#ibcon#*before write, iclass 35, count 2 2006.173.16:53:36.68#ibcon#enter sib2, iclass 35, count 2 2006.173.16:53:36.68#ibcon#flushed, iclass 35, count 2 2006.173.16:53:36.68#ibcon#about to write, iclass 35, count 2 2006.173.16:53:36.68#ibcon#wrote, iclass 35, count 2 2006.173.16:53:36.68#ibcon#about to read 3, iclass 35, count 2 2006.173.16:53:36.71#ibcon#read 3, iclass 35, count 2 2006.173.16:53:36.71#ibcon#about to read 4, iclass 35, count 2 2006.173.16:53:36.71#ibcon#read 4, iclass 35, count 2 2006.173.16:53:36.71#ibcon#about to read 5, iclass 35, count 2 2006.173.16:53:36.71#ibcon#read 5, iclass 35, count 2 2006.173.16:53:36.71#ibcon#about to read 6, iclass 35, count 2 2006.173.16:53:36.71#ibcon#read 6, iclass 35, count 2 2006.173.16:53:36.71#ibcon#end of sib2, iclass 35, count 2 2006.173.16:53:36.71#ibcon#*after write, iclass 35, count 2 2006.173.16:53:36.71#ibcon#*before return 0, iclass 35, count 2 2006.173.16:53:36.71#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.16:53:36.71#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.16:53:36.71#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.16:53:36.71#ibcon#ireg 7 cls_cnt 0 2006.173.16:53:36.71#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.16:53:36.83#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.16:53:36.83#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.16:53:36.83#ibcon#enter wrdev, iclass 35, count 0 2006.173.16:53:36.83#ibcon#first serial, iclass 35, count 0 2006.173.16:53:36.83#ibcon#enter sib2, iclass 35, count 0 2006.173.16:53:36.83#ibcon#flushed, iclass 35, count 0 2006.173.16:53:36.83#ibcon#about to write, iclass 35, count 0 2006.173.16:53:36.83#ibcon#wrote, iclass 35, count 0 2006.173.16:53:36.83#ibcon#about to read 3, iclass 35, count 0 2006.173.16:53:36.85#ibcon#read 3, iclass 35, count 0 2006.173.16:53:36.85#ibcon#about to read 4, iclass 35, count 0 2006.173.16:53:36.85#ibcon#read 4, iclass 35, count 0 2006.173.16:53:36.85#ibcon#about to read 5, iclass 35, count 0 2006.173.16:53:36.85#ibcon#read 5, iclass 35, count 0 2006.173.16:53:36.85#ibcon#about to read 6, iclass 35, count 0 2006.173.16:53:36.85#ibcon#read 6, iclass 35, count 0 2006.173.16:53:36.85#ibcon#end of sib2, iclass 35, count 0 2006.173.16:53:36.85#ibcon#*mode == 0, iclass 35, count 0 2006.173.16:53:36.85#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.16:53:36.85#ibcon#[27=USB\r\n] 2006.173.16:53:36.85#ibcon#*before write, iclass 35, count 0 2006.173.16:53:36.85#ibcon#enter sib2, iclass 35, count 0 2006.173.16:53:36.85#ibcon#flushed, iclass 35, count 0 2006.173.16:53:36.85#ibcon#about to write, iclass 35, count 0 2006.173.16:53:36.85#ibcon#wrote, iclass 35, count 0 2006.173.16:53:36.85#ibcon#about to read 3, iclass 35, count 0 2006.173.16:53:36.88#ibcon#read 3, iclass 35, count 0 2006.173.16:53:36.88#ibcon#about to read 4, iclass 35, count 0 2006.173.16:53:36.88#ibcon#read 4, iclass 35, count 0 2006.173.16:53:36.88#ibcon#about to read 5, iclass 35, count 0 2006.173.16:53:36.88#ibcon#read 5, iclass 35, count 0 2006.173.16:53:36.88#ibcon#about to read 6, iclass 35, count 0 2006.173.16:53:36.88#ibcon#read 6, iclass 35, count 0 2006.173.16:53:36.88#ibcon#end of sib2, iclass 35, count 0 2006.173.16:53:36.88#ibcon#*after write, iclass 35, count 0 2006.173.16:53:36.88#ibcon#*before return 0, iclass 35, count 0 2006.173.16:53:36.88#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.16:53:36.88#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.16:53:36.88#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.16:53:36.88#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.16:53:36.88$vck44/vblo=7,734.99 2006.173.16:53:36.88#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.16:53:36.88#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.16:53:36.88#ibcon#ireg 17 cls_cnt 0 2006.173.16:53:36.88#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.16:53:36.88#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.16:53:36.88#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.16:53:36.88#ibcon#enter wrdev, iclass 37, count 0 2006.173.16:53:36.88#ibcon#first serial, iclass 37, count 0 2006.173.16:53:36.88#ibcon#enter sib2, iclass 37, count 0 2006.173.16:53:36.88#ibcon#flushed, iclass 37, count 0 2006.173.16:53:36.88#ibcon#about to write, iclass 37, count 0 2006.173.16:53:36.88#ibcon#wrote, iclass 37, count 0 2006.173.16:53:36.88#ibcon#about to read 3, iclass 37, count 0 2006.173.16:53:36.90#ibcon#read 3, iclass 37, count 0 2006.173.16:53:36.90#ibcon#about to read 4, iclass 37, count 0 2006.173.16:53:36.90#ibcon#read 4, iclass 37, count 0 2006.173.16:53:36.90#ibcon#about to read 5, iclass 37, count 0 2006.173.16:53:36.90#ibcon#read 5, iclass 37, count 0 2006.173.16:53:36.90#ibcon#about to read 6, iclass 37, count 0 2006.173.16:53:36.90#ibcon#read 6, iclass 37, count 0 2006.173.16:53:36.90#ibcon#end of sib2, iclass 37, count 0 2006.173.16:53:36.90#ibcon#*mode == 0, iclass 37, count 0 2006.173.16:53:36.90#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.16:53:36.90#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.16:53:36.90#ibcon#*before write, iclass 37, count 0 2006.173.16:53:36.90#ibcon#enter sib2, iclass 37, count 0 2006.173.16:53:36.90#ibcon#flushed, iclass 37, count 0 2006.173.16:53:36.90#ibcon#about to write, iclass 37, count 0 2006.173.16:53:36.90#ibcon#wrote, iclass 37, count 0 2006.173.16:53:36.90#ibcon#about to read 3, iclass 37, count 0 2006.173.16:53:36.94#ibcon#read 3, iclass 37, count 0 2006.173.16:53:36.94#ibcon#about to read 4, iclass 37, count 0 2006.173.16:53:36.94#ibcon#read 4, iclass 37, count 0 2006.173.16:53:36.94#ibcon#about to read 5, iclass 37, count 0 2006.173.16:53:36.94#ibcon#read 5, iclass 37, count 0 2006.173.16:53:36.94#ibcon#about to read 6, iclass 37, count 0 2006.173.16:53:36.94#ibcon#read 6, iclass 37, count 0 2006.173.16:53:36.94#ibcon#end of sib2, iclass 37, count 0 2006.173.16:53:36.94#ibcon#*after write, iclass 37, count 0 2006.173.16:53:36.94#ibcon#*before return 0, iclass 37, count 0 2006.173.16:53:36.94#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.16:53:36.94#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.16:53:36.94#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.16:53:36.94#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.16:53:36.94$vck44/vb=7,4 2006.173.16:53:36.94#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.16:53:36.94#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.16:53:36.94#ibcon#ireg 11 cls_cnt 2 2006.173.16:53:36.94#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.16:53:37.00#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.16:53:37.00#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.16:53:37.00#ibcon#enter wrdev, iclass 39, count 2 2006.173.16:53:37.00#ibcon#first serial, iclass 39, count 2 2006.173.16:53:37.00#ibcon#enter sib2, iclass 39, count 2 2006.173.16:53:37.00#ibcon#flushed, iclass 39, count 2 2006.173.16:53:37.00#ibcon#about to write, iclass 39, count 2 2006.173.16:53:37.00#ibcon#wrote, iclass 39, count 2 2006.173.16:53:37.00#ibcon#about to read 3, iclass 39, count 2 2006.173.16:53:37.02#ibcon#read 3, iclass 39, count 2 2006.173.16:53:37.02#ibcon#about to read 4, iclass 39, count 2 2006.173.16:53:37.02#ibcon#read 4, iclass 39, count 2 2006.173.16:53:37.02#ibcon#about to read 5, iclass 39, count 2 2006.173.16:53:37.02#ibcon#read 5, iclass 39, count 2 2006.173.16:53:37.02#ibcon#about to read 6, iclass 39, count 2 2006.173.16:53:37.02#ibcon#read 6, iclass 39, count 2 2006.173.16:53:37.02#ibcon#end of sib2, iclass 39, count 2 2006.173.16:53:37.02#ibcon#*mode == 0, iclass 39, count 2 2006.173.16:53:37.02#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.16:53:37.02#ibcon#[27=AT07-04\r\n] 2006.173.16:53:37.02#ibcon#*before write, iclass 39, count 2 2006.173.16:53:37.02#ibcon#enter sib2, iclass 39, count 2 2006.173.16:53:37.02#ibcon#flushed, iclass 39, count 2 2006.173.16:53:37.02#ibcon#about to write, iclass 39, count 2 2006.173.16:53:37.02#ibcon#wrote, iclass 39, count 2 2006.173.16:53:37.02#ibcon#about to read 3, iclass 39, count 2 2006.173.16:53:37.05#ibcon#read 3, iclass 39, count 2 2006.173.16:53:37.05#ibcon#about to read 4, iclass 39, count 2 2006.173.16:53:37.05#ibcon#read 4, iclass 39, count 2 2006.173.16:53:37.05#ibcon#about to read 5, iclass 39, count 2 2006.173.16:53:37.05#ibcon#read 5, iclass 39, count 2 2006.173.16:53:37.05#ibcon#about to read 6, iclass 39, count 2 2006.173.16:53:37.05#ibcon#read 6, iclass 39, count 2 2006.173.16:53:37.05#ibcon#end of sib2, iclass 39, count 2 2006.173.16:53:37.05#ibcon#*after write, iclass 39, count 2 2006.173.16:53:37.05#ibcon#*before return 0, iclass 39, count 2 2006.173.16:53:37.05#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.16:53:37.05#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.16:53:37.05#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.16:53:37.05#ibcon#ireg 7 cls_cnt 0 2006.173.16:53:37.05#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.16:53:37.17#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.16:53:37.17#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.16:53:37.17#ibcon#enter wrdev, iclass 39, count 0 2006.173.16:53:37.17#ibcon#first serial, iclass 39, count 0 2006.173.16:53:37.17#ibcon#enter sib2, iclass 39, count 0 2006.173.16:53:37.17#ibcon#flushed, iclass 39, count 0 2006.173.16:53:37.17#ibcon#about to write, iclass 39, count 0 2006.173.16:53:37.17#ibcon#wrote, iclass 39, count 0 2006.173.16:53:37.17#ibcon#about to read 3, iclass 39, count 0 2006.173.16:53:37.19#ibcon#read 3, iclass 39, count 0 2006.173.16:53:37.19#ibcon#about to read 4, iclass 39, count 0 2006.173.16:53:37.19#ibcon#read 4, iclass 39, count 0 2006.173.16:53:37.19#ibcon#about to read 5, iclass 39, count 0 2006.173.16:53:37.19#ibcon#read 5, iclass 39, count 0 2006.173.16:53:37.19#ibcon#about to read 6, iclass 39, count 0 2006.173.16:53:37.19#ibcon#read 6, iclass 39, count 0 2006.173.16:53:37.19#ibcon#end of sib2, iclass 39, count 0 2006.173.16:53:37.19#ibcon#*mode == 0, iclass 39, count 0 2006.173.16:53:37.19#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.16:53:37.19#ibcon#[27=USB\r\n] 2006.173.16:53:37.19#ibcon#*before write, iclass 39, count 0 2006.173.16:53:37.19#ibcon#enter sib2, iclass 39, count 0 2006.173.16:53:37.19#ibcon#flushed, iclass 39, count 0 2006.173.16:53:37.19#ibcon#about to write, iclass 39, count 0 2006.173.16:53:37.19#ibcon#wrote, iclass 39, count 0 2006.173.16:53:37.19#ibcon#about to read 3, iclass 39, count 0 2006.173.16:53:37.22#ibcon#read 3, iclass 39, count 0 2006.173.16:53:37.22#ibcon#about to read 4, iclass 39, count 0 2006.173.16:53:37.22#ibcon#read 4, iclass 39, count 0 2006.173.16:53:37.22#ibcon#about to read 5, iclass 39, count 0 2006.173.16:53:37.22#ibcon#read 5, iclass 39, count 0 2006.173.16:53:37.22#ibcon#about to read 6, iclass 39, count 0 2006.173.16:53:37.22#ibcon#read 6, iclass 39, count 0 2006.173.16:53:37.22#ibcon#end of sib2, iclass 39, count 0 2006.173.16:53:37.22#ibcon#*after write, iclass 39, count 0 2006.173.16:53:37.22#ibcon#*before return 0, iclass 39, count 0 2006.173.16:53:37.22#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.16:53:37.22#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.16:53:37.22#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.16:53:37.22#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.16:53:37.22$vck44/vblo=8,744.99 2006.173.16:53:37.22#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.16:53:37.22#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.16:53:37.22#ibcon#ireg 17 cls_cnt 0 2006.173.16:53:37.22#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.16:53:37.22#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.16:53:37.22#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.16:53:37.22#ibcon#enter wrdev, iclass 3, count 0 2006.173.16:53:37.22#ibcon#first serial, iclass 3, count 0 2006.173.16:53:37.22#ibcon#enter sib2, iclass 3, count 0 2006.173.16:53:37.22#ibcon#flushed, iclass 3, count 0 2006.173.16:53:37.22#ibcon#about to write, iclass 3, count 0 2006.173.16:53:37.22#ibcon#wrote, iclass 3, count 0 2006.173.16:53:37.22#ibcon#about to read 3, iclass 3, count 0 2006.173.16:53:37.24#ibcon#read 3, iclass 3, count 0 2006.173.16:53:37.24#ibcon#about to read 4, iclass 3, count 0 2006.173.16:53:37.24#ibcon#read 4, iclass 3, count 0 2006.173.16:53:37.24#ibcon#about to read 5, iclass 3, count 0 2006.173.16:53:37.24#ibcon#read 5, iclass 3, count 0 2006.173.16:53:37.24#ibcon#about to read 6, iclass 3, count 0 2006.173.16:53:37.24#ibcon#read 6, iclass 3, count 0 2006.173.16:53:37.24#ibcon#end of sib2, iclass 3, count 0 2006.173.16:53:37.24#ibcon#*mode == 0, iclass 3, count 0 2006.173.16:53:37.24#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.16:53:37.24#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.16:53:37.24#ibcon#*before write, iclass 3, count 0 2006.173.16:53:37.24#ibcon#enter sib2, iclass 3, count 0 2006.173.16:53:37.24#ibcon#flushed, iclass 3, count 0 2006.173.16:53:37.24#ibcon#about to write, iclass 3, count 0 2006.173.16:53:37.24#ibcon#wrote, iclass 3, count 0 2006.173.16:53:37.24#ibcon#about to read 3, iclass 3, count 0 2006.173.16:53:37.28#ibcon#read 3, iclass 3, count 0 2006.173.16:53:37.28#ibcon#about to read 4, iclass 3, count 0 2006.173.16:53:37.28#ibcon#read 4, iclass 3, count 0 2006.173.16:53:37.28#ibcon#about to read 5, iclass 3, count 0 2006.173.16:53:37.28#ibcon#read 5, iclass 3, count 0 2006.173.16:53:37.28#ibcon#about to read 6, iclass 3, count 0 2006.173.16:53:37.28#ibcon#read 6, iclass 3, count 0 2006.173.16:53:37.28#ibcon#end of sib2, iclass 3, count 0 2006.173.16:53:37.28#ibcon#*after write, iclass 3, count 0 2006.173.16:53:37.28#ibcon#*before return 0, iclass 3, count 0 2006.173.16:53:37.28#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.16:53:37.28#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.16:53:37.28#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.16:53:37.28#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.16:53:37.28$vck44/vb=8,4 2006.173.16:53:37.28#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.16:53:37.28#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.16:53:37.28#ibcon#ireg 11 cls_cnt 2 2006.173.16:53:37.28#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.16:53:37.34#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.16:53:37.34#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.16:53:37.34#ibcon#enter wrdev, iclass 5, count 2 2006.173.16:53:37.34#ibcon#first serial, iclass 5, count 2 2006.173.16:53:37.34#ibcon#enter sib2, iclass 5, count 2 2006.173.16:53:37.34#ibcon#flushed, iclass 5, count 2 2006.173.16:53:37.34#ibcon#about to write, iclass 5, count 2 2006.173.16:53:37.34#ibcon#wrote, iclass 5, count 2 2006.173.16:53:37.34#ibcon#about to read 3, iclass 5, count 2 2006.173.16:53:37.36#ibcon#read 3, iclass 5, count 2 2006.173.16:53:37.36#ibcon#about to read 4, iclass 5, count 2 2006.173.16:53:37.36#ibcon#read 4, iclass 5, count 2 2006.173.16:53:37.36#ibcon#about to read 5, iclass 5, count 2 2006.173.16:53:37.36#ibcon#read 5, iclass 5, count 2 2006.173.16:53:37.36#ibcon#about to read 6, iclass 5, count 2 2006.173.16:53:37.36#ibcon#read 6, iclass 5, count 2 2006.173.16:53:37.36#ibcon#end of sib2, iclass 5, count 2 2006.173.16:53:37.36#ibcon#*mode == 0, iclass 5, count 2 2006.173.16:53:37.36#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.16:53:37.36#ibcon#[27=AT08-04\r\n] 2006.173.16:53:37.36#ibcon#*before write, iclass 5, count 2 2006.173.16:53:37.36#ibcon#enter sib2, iclass 5, count 2 2006.173.16:53:37.36#ibcon#flushed, iclass 5, count 2 2006.173.16:53:37.36#ibcon#about to write, iclass 5, count 2 2006.173.16:53:37.36#ibcon#wrote, iclass 5, count 2 2006.173.16:53:37.36#ibcon#about to read 3, iclass 5, count 2 2006.173.16:53:37.39#ibcon#read 3, iclass 5, count 2 2006.173.16:53:37.39#ibcon#about to read 4, iclass 5, count 2 2006.173.16:53:37.39#ibcon#read 4, iclass 5, count 2 2006.173.16:53:37.39#ibcon#about to read 5, iclass 5, count 2 2006.173.16:53:37.39#ibcon#read 5, iclass 5, count 2 2006.173.16:53:37.39#ibcon#about to read 6, iclass 5, count 2 2006.173.16:53:37.39#ibcon#read 6, iclass 5, count 2 2006.173.16:53:37.39#ibcon#end of sib2, iclass 5, count 2 2006.173.16:53:37.39#ibcon#*after write, iclass 5, count 2 2006.173.16:53:37.39#ibcon#*before return 0, iclass 5, count 2 2006.173.16:53:37.39#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.16:53:37.39#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.16:53:37.39#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.16:53:37.39#ibcon#ireg 7 cls_cnt 0 2006.173.16:53:37.39#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.16:53:37.51#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.16:53:37.51#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.16:53:37.51#ibcon#enter wrdev, iclass 5, count 0 2006.173.16:53:37.51#ibcon#first serial, iclass 5, count 0 2006.173.16:53:37.51#ibcon#enter sib2, iclass 5, count 0 2006.173.16:53:37.51#ibcon#flushed, iclass 5, count 0 2006.173.16:53:37.51#ibcon#about to write, iclass 5, count 0 2006.173.16:53:37.51#ibcon#wrote, iclass 5, count 0 2006.173.16:53:37.51#ibcon#about to read 3, iclass 5, count 0 2006.173.16:53:37.53#ibcon#read 3, iclass 5, count 0 2006.173.16:53:37.53#ibcon#about to read 4, iclass 5, count 0 2006.173.16:53:37.53#ibcon#read 4, iclass 5, count 0 2006.173.16:53:37.53#ibcon#about to read 5, iclass 5, count 0 2006.173.16:53:37.53#ibcon#read 5, iclass 5, count 0 2006.173.16:53:37.53#ibcon#about to read 6, iclass 5, count 0 2006.173.16:53:37.53#ibcon#read 6, iclass 5, count 0 2006.173.16:53:37.53#ibcon#end of sib2, iclass 5, count 0 2006.173.16:53:37.53#ibcon#*mode == 0, iclass 5, count 0 2006.173.16:53:37.53#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.16:53:37.53#ibcon#[27=USB\r\n] 2006.173.16:53:37.53#ibcon#*before write, iclass 5, count 0 2006.173.16:53:37.53#ibcon#enter sib2, iclass 5, count 0 2006.173.16:53:37.53#ibcon#flushed, iclass 5, count 0 2006.173.16:53:37.53#ibcon#about to write, iclass 5, count 0 2006.173.16:53:37.53#ibcon#wrote, iclass 5, count 0 2006.173.16:53:37.53#ibcon#about to read 3, iclass 5, count 0 2006.173.16:53:37.56#ibcon#read 3, iclass 5, count 0 2006.173.16:53:37.56#ibcon#about to read 4, iclass 5, count 0 2006.173.16:53:37.56#ibcon#read 4, iclass 5, count 0 2006.173.16:53:37.56#ibcon#about to read 5, iclass 5, count 0 2006.173.16:53:37.56#ibcon#read 5, iclass 5, count 0 2006.173.16:53:37.56#ibcon#about to read 6, iclass 5, count 0 2006.173.16:53:37.56#ibcon#read 6, iclass 5, count 0 2006.173.16:53:37.56#ibcon#end of sib2, iclass 5, count 0 2006.173.16:53:37.56#ibcon#*after write, iclass 5, count 0 2006.173.16:53:37.56#ibcon#*before return 0, iclass 5, count 0 2006.173.16:53:37.56#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.16:53:37.56#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.16:53:37.56#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.16:53:37.56#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.16:53:37.56$vck44/vabw=wide 2006.173.16:53:37.56#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.16:53:37.56#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.16:53:37.56#ibcon#ireg 8 cls_cnt 0 2006.173.16:53:37.56#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.16:53:37.56#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.16:53:37.56#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.16:53:37.56#ibcon#enter wrdev, iclass 7, count 0 2006.173.16:53:37.56#ibcon#first serial, iclass 7, count 0 2006.173.16:53:37.56#ibcon#enter sib2, iclass 7, count 0 2006.173.16:53:37.56#ibcon#flushed, iclass 7, count 0 2006.173.16:53:37.56#ibcon#about to write, iclass 7, count 0 2006.173.16:53:37.56#ibcon#wrote, iclass 7, count 0 2006.173.16:53:37.56#ibcon#about to read 3, iclass 7, count 0 2006.173.16:53:37.58#ibcon#read 3, iclass 7, count 0 2006.173.16:53:37.58#ibcon#about to read 4, iclass 7, count 0 2006.173.16:53:37.58#ibcon#read 4, iclass 7, count 0 2006.173.16:53:37.58#ibcon#about to read 5, iclass 7, count 0 2006.173.16:53:37.58#ibcon#read 5, iclass 7, count 0 2006.173.16:53:37.58#ibcon#about to read 6, iclass 7, count 0 2006.173.16:53:37.58#ibcon#read 6, iclass 7, count 0 2006.173.16:53:37.58#ibcon#end of sib2, iclass 7, count 0 2006.173.16:53:37.58#ibcon#*mode == 0, iclass 7, count 0 2006.173.16:53:37.58#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.16:53:37.58#ibcon#[25=BW32\r\n] 2006.173.16:53:37.58#ibcon#*before write, iclass 7, count 0 2006.173.16:53:37.58#ibcon#enter sib2, iclass 7, count 0 2006.173.16:53:37.58#ibcon#flushed, iclass 7, count 0 2006.173.16:53:37.58#ibcon#about to write, iclass 7, count 0 2006.173.16:53:37.58#ibcon#wrote, iclass 7, count 0 2006.173.16:53:37.58#ibcon#about to read 3, iclass 7, count 0 2006.173.16:53:37.61#ibcon#read 3, iclass 7, count 0 2006.173.16:53:37.61#ibcon#about to read 4, iclass 7, count 0 2006.173.16:53:37.61#ibcon#read 4, iclass 7, count 0 2006.173.16:53:37.61#ibcon#about to read 5, iclass 7, count 0 2006.173.16:53:37.61#ibcon#read 5, iclass 7, count 0 2006.173.16:53:37.61#ibcon#about to read 6, iclass 7, count 0 2006.173.16:53:37.61#ibcon#read 6, iclass 7, count 0 2006.173.16:53:37.61#ibcon#end of sib2, iclass 7, count 0 2006.173.16:53:37.61#ibcon#*after write, iclass 7, count 0 2006.173.16:53:37.61#ibcon#*before return 0, iclass 7, count 0 2006.173.16:53:37.61#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.16:53:37.61#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.16:53:37.61#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.16:53:37.61#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.16:53:37.61$vck44/vbbw=wide 2006.173.16:53:37.61#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.16:53:37.61#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.16:53:37.61#ibcon#ireg 8 cls_cnt 0 2006.173.16:53:37.61#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.16:53:37.68#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.16:53:37.68#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.16:53:37.68#ibcon#enter wrdev, iclass 11, count 0 2006.173.16:53:37.68#ibcon#first serial, iclass 11, count 0 2006.173.16:53:37.68#ibcon#enter sib2, iclass 11, count 0 2006.173.16:53:37.68#ibcon#flushed, iclass 11, count 0 2006.173.16:53:37.68#ibcon#about to write, iclass 11, count 0 2006.173.16:53:37.68#ibcon#wrote, iclass 11, count 0 2006.173.16:53:37.68#ibcon#about to read 3, iclass 11, count 0 2006.173.16:53:37.70#ibcon#read 3, iclass 11, count 0 2006.173.16:53:37.70#ibcon#about to read 4, iclass 11, count 0 2006.173.16:53:37.70#ibcon#read 4, iclass 11, count 0 2006.173.16:53:37.70#ibcon#about to read 5, iclass 11, count 0 2006.173.16:53:37.70#ibcon#read 5, iclass 11, count 0 2006.173.16:53:37.70#ibcon#about to read 6, iclass 11, count 0 2006.173.16:53:37.70#ibcon#read 6, iclass 11, count 0 2006.173.16:53:37.70#ibcon#end of sib2, iclass 11, count 0 2006.173.16:53:37.70#ibcon#*mode == 0, iclass 11, count 0 2006.173.16:53:37.70#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.16:53:37.70#ibcon#[27=BW32\r\n] 2006.173.16:53:37.70#ibcon#*before write, iclass 11, count 0 2006.173.16:53:37.70#ibcon#enter sib2, iclass 11, count 0 2006.173.16:53:37.70#ibcon#flushed, iclass 11, count 0 2006.173.16:53:37.70#ibcon#about to write, iclass 11, count 0 2006.173.16:53:37.70#ibcon#wrote, iclass 11, count 0 2006.173.16:53:37.70#ibcon#about to read 3, iclass 11, count 0 2006.173.16:53:37.73#ibcon#read 3, iclass 11, count 0 2006.173.16:53:37.73#ibcon#about to read 4, iclass 11, count 0 2006.173.16:53:37.73#ibcon#read 4, iclass 11, count 0 2006.173.16:53:37.73#ibcon#about to read 5, iclass 11, count 0 2006.173.16:53:37.73#ibcon#read 5, iclass 11, count 0 2006.173.16:53:37.73#ibcon#about to read 6, iclass 11, count 0 2006.173.16:53:37.73#ibcon#read 6, iclass 11, count 0 2006.173.16:53:37.73#ibcon#end of sib2, iclass 11, count 0 2006.173.16:53:37.73#ibcon#*after write, iclass 11, count 0 2006.173.16:53:37.73#ibcon#*before return 0, iclass 11, count 0 2006.173.16:53:37.73#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.16:53:37.73#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.16:53:37.73#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.16:53:37.73#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.16:53:37.73$setupk4/ifdk4 2006.173.16:53:37.73$ifdk4/lo= 2006.173.16:53:37.73$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.16:53:37.73$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.16:53:37.73$ifdk4/patch= 2006.173.16:53:37.73$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.16:53:37.73$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.16:53:37.73$setupk4/!*+20s 2006.173.16:53:42.55#abcon#<5=/14 0.5 1.8 20.411001002.9\r\n> 2006.173.16:53:42.57#abcon#{5=INTERFACE CLEAR} 2006.173.16:53:42.63#abcon#[5=S1D000X0/0*\r\n] 2006.173.16:53:52.24$setupk4/"tpicd 2006.173.16:53:52.24$setupk4/echo=off 2006.173.16:53:52.24$setupk4/xlog=off 2006.173.16:53:52.24:!2006.173.16:55:11 2006.173.16:54:09.14#trakl#Source acquired 2006.173.16:54:09.14#flagr#flagr/antenna,acquired 2006.173.16:55:11.00:preob 2006.173.16:55:11.14/onsource/TRACKING 2006.173.16:55:11.14:!2006.173.16:55:21 2006.173.16:55:21.00:"tape 2006.173.16:55:21.00:"st=record 2006.173.16:55:21.00:data_valid=on 2006.173.16:55:21.00:midob 2006.173.16:55:21.14/onsource/TRACKING 2006.173.16:55:21.14/wx/20.39,1002.8,100 2006.173.16:55:21.25/cable/+6.5118E-03 2006.173.16:55:22.34/va/01,07,usb,yes,35,38 2006.173.16:55:22.34/va/02,06,usb,yes,35,36 2006.173.16:55:22.34/va/03,05,usb,yes,44,46 2006.173.16:55:22.34/va/04,06,usb,yes,36,38 2006.173.16:55:22.34/va/05,04,usb,yes,28,28 2006.173.16:55:22.34/va/06,03,usb,yes,39,39 2006.173.16:55:22.34/va/07,04,usb,yes,32,33 2006.173.16:55:22.34/va/08,04,usb,yes,27,32 2006.173.16:55:22.57/valo/01,524.99,yes,locked 2006.173.16:55:22.57/valo/02,534.99,yes,locked 2006.173.16:55:22.57/valo/03,564.99,yes,locked 2006.173.16:55:22.57/valo/04,624.99,yes,locked 2006.173.16:55:22.57/valo/05,734.99,yes,locked 2006.173.16:55:22.57/valo/06,814.99,yes,locked 2006.173.16:55:22.57/valo/07,864.99,yes,locked 2006.173.16:55:22.57/valo/08,884.99,yes,locked 2006.173.16:55:23.66/vb/01,04,usb,yes,29,27 2006.173.16:55:23.66/vb/02,04,usb,yes,31,31 2006.173.16:55:23.66/vb/03,04,usb,yes,28,31 2006.173.16:55:23.66/vb/04,04,usb,yes,32,31 2006.173.16:55:23.66/vb/05,04,usb,yes,25,27 2006.173.16:55:23.66/vb/06,04,usb,yes,29,26 2006.173.16:55:23.66/vb/07,04,usb,yes,29,29 2006.173.16:55:23.66/vb/08,04,usb,yes,27,30 2006.173.16:55:23.89/vblo/01,629.99,yes,locked 2006.173.16:55:23.89/vblo/02,634.99,yes,locked 2006.173.16:55:23.89/vblo/03,649.99,yes,locked 2006.173.16:55:23.89/vblo/04,679.99,yes,locked 2006.173.16:55:23.89/vblo/05,709.99,yes,locked 2006.173.16:55:23.89/vblo/06,719.99,yes,locked 2006.173.16:55:23.89/vblo/07,734.99,yes,locked 2006.173.16:55:23.89/vblo/08,744.99,yes,locked 2006.173.16:55:24.04/vabw/8 2006.173.16:55:24.19/vbbw/8 2006.173.16:55:24.28/xfe/off,on,15.2 2006.173.16:55:24.72/ifatt/23,28,28,28 2006.173.16:55:25.07/fmout-gps/S +3.98E-07 2006.173.16:55:25.11:!2006.173.16:59:01 2006.173.16:59:01.00:data_valid=off 2006.173.16:59:01.00:"et 2006.173.16:59:01.00:!+3s 2006.173.16:59:04.01:"tape 2006.173.16:59:04.01:postob 2006.173.16:59:04.20/cable/+6.5124E-03 2006.173.16:59:04.20/wx/20.34,1002.8,100 2006.173.16:59:05.07/fmout-gps/S +4.01E-07 2006.173.16:59:05.07:scan_name=173-1703,jd0606,40 2006.173.16:59:05.07:source=3c345,164258.81,394837.0,2000.0,ccw 2006.173.16:59:06.13#flagr#flagr/antenna,new-source 2006.173.16:59:06.13:checkk5 2006.173.16:59:06.54/chk_autoobs//k5ts1/ autoobs is running! 2006.173.16:59:06.93/chk_autoobs//k5ts2/ autoobs is running! 2006.173.16:59:07.33/chk_autoobs//k5ts3/ autoobs is running! 2006.173.16:59:07.73/chk_autoobs//k5ts4/ autoobs is running! 2006.173.16:59:08.11/chk_obsdata//k5ts1/T1731655??a.dat file size is correct (nominal:880MB, actual:876MB). 2006.173.16:59:08.52/chk_obsdata//k5ts2/T1731655??b.dat file size is correct (nominal:880MB, actual:876MB). 2006.173.16:59:08.93/chk_obsdata//k5ts3/T1731655??c.dat file size is correct (nominal:880MB, actual:876MB). 2006.173.16:59:09.34/chk_obsdata//k5ts4/T1731655??d.dat file size is correct (nominal:880MB, actual:876MB). 2006.173.16:59:10.06/k5log//k5ts1_log_newline 2006.173.16:59:10.77/k5log//k5ts2_log_newline 2006.173.16:59:11.48/k5log//k5ts3_log_newline 2006.173.16:59:12.19/k5log//k5ts4_log_newline 2006.173.16:59:12.22/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.16:59:12.22:setupk4=1 2006.173.16:59:12.22$setupk4/echo=on 2006.173.16:59:12.22$setupk4/pcalon 2006.173.16:59:12.22$pcalon/"no phase cal control is implemented here 2006.173.16:59:12.22$setupk4/"tpicd=stop 2006.173.16:59:12.22$setupk4/"rec=synch_on 2006.173.16:59:12.22$setupk4/"rec_mode=128 2006.173.16:59:12.22$setupk4/!* 2006.173.16:59:12.22$setupk4/recpk4 2006.173.16:59:12.22$recpk4/recpatch= 2006.173.16:59:12.22$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.16:59:12.22$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.16:59:12.22$setupk4/vck44 2006.173.16:59:12.22$vck44/valo=1,524.99 2006.173.16:59:12.22#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.16:59:12.22#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.16:59:12.22#ibcon#ireg 17 cls_cnt 0 2006.173.16:59:12.22#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.16:59:12.22#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.16:59:12.22#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.16:59:12.22#ibcon#enter wrdev, iclass 40, count 0 2006.173.16:59:12.22#ibcon#first serial, iclass 40, count 0 2006.173.16:59:12.22#ibcon#enter sib2, iclass 40, count 0 2006.173.16:59:12.22#ibcon#flushed, iclass 40, count 0 2006.173.16:59:12.22#ibcon#about to write, iclass 40, count 0 2006.173.16:59:12.22#ibcon#wrote, iclass 40, count 0 2006.173.16:59:12.22#ibcon#about to read 3, iclass 40, count 0 2006.173.16:59:12.24#ibcon#read 3, iclass 40, count 0 2006.173.16:59:12.24#ibcon#about to read 4, iclass 40, count 0 2006.173.16:59:12.24#ibcon#read 4, iclass 40, count 0 2006.173.16:59:12.24#ibcon#about to read 5, iclass 40, count 0 2006.173.16:59:12.24#ibcon#read 5, iclass 40, count 0 2006.173.16:59:12.24#ibcon#about to read 6, iclass 40, count 0 2006.173.16:59:12.24#ibcon#read 6, iclass 40, count 0 2006.173.16:59:12.24#ibcon#end of sib2, iclass 40, count 0 2006.173.16:59:12.24#ibcon#*mode == 0, iclass 40, count 0 2006.173.16:59:12.24#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.16:59:12.24#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.16:59:12.24#ibcon#*before write, iclass 40, count 0 2006.173.16:59:12.24#ibcon#enter sib2, iclass 40, count 0 2006.173.16:59:12.24#ibcon#flushed, iclass 40, count 0 2006.173.16:59:12.24#ibcon#about to write, iclass 40, count 0 2006.173.16:59:12.24#ibcon#wrote, iclass 40, count 0 2006.173.16:59:12.24#ibcon#about to read 3, iclass 40, count 0 2006.173.16:59:12.29#ibcon#read 3, iclass 40, count 0 2006.173.16:59:12.29#ibcon#about to read 4, iclass 40, count 0 2006.173.16:59:12.29#ibcon#read 4, iclass 40, count 0 2006.173.16:59:12.29#ibcon#about to read 5, iclass 40, count 0 2006.173.16:59:12.29#ibcon#read 5, iclass 40, count 0 2006.173.16:59:12.29#ibcon#about to read 6, iclass 40, count 0 2006.173.16:59:12.29#ibcon#read 6, iclass 40, count 0 2006.173.16:59:12.29#ibcon#end of sib2, iclass 40, count 0 2006.173.16:59:12.29#ibcon#*after write, iclass 40, count 0 2006.173.16:59:12.29#ibcon#*before return 0, iclass 40, count 0 2006.173.16:59:12.29#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.16:59:12.29#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.16:59:12.29#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.16:59:12.29#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.16:59:12.29$vck44/va=1,7 2006.173.16:59:12.29#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.16:59:12.29#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.16:59:12.29#ibcon#ireg 11 cls_cnt 2 2006.173.16:59:12.29#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.16:59:12.29#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.16:59:12.29#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.16:59:12.29#ibcon#enter wrdev, iclass 4, count 2 2006.173.16:59:12.29#ibcon#first serial, iclass 4, count 2 2006.173.16:59:12.29#ibcon#enter sib2, iclass 4, count 2 2006.173.16:59:12.29#ibcon#flushed, iclass 4, count 2 2006.173.16:59:12.29#ibcon#about to write, iclass 4, count 2 2006.173.16:59:12.29#ibcon#wrote, iclass 4, count 2 2006.173.16:59:12.29#ibcon#about to read 3, iclass 4, count 2 2006.173.16:59:12.31#ibcon#read 3, iclass 4, count 2 2006.173.16:59:12.31#ibcon#about to read 4, iclass 4, count 2 2006.173.16:59:12.31#ibcon#read 4, iclass 4, count 2 2006.173.16:59:12.31#ibcon#about to read 5, iclass 4, count 2 2006.173.16:59:12.31#ibcon#read 5, iclass 4, count 2 2006.173.16:59:12.31#ibcon#about to read 6, iclass 4, count 2 2006.173.16:59:12.31#ibcon#read 6, iclass 4, count 2 2006.173.16:59:12.31#ibcon#end of sib2, iclass 4, count 2 2006.173.16:59:12.31#ibcon#*mode == 0, iclass 4, count 2 2006.173.16:59:12.31#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.16:59:12.31#ibcon#[25=AT01-07\r\n] 2006.173.16:59:12.31#ibcon#*before write, iclass 4, count 2 2006.173.16:59:12.31#ibcon#enter sib2, iclass 4, count 2 2006.173.16:59:12.31#ibcon#flushed, iclass 4, count 2 2006.173.16:59:12.31#ibcon#about to write, iclass 4, count 2 2006.173.16:59:12.31#ibcon#wrote, iclass 4, count 2 2006.173.16:59:12.31#ibcon#about to read 3, iclass 4, count 2 2006.173.16:59:12.34#ibcon#read 3, iclass 4, count 2 2006.173.16:59:12.34#ibcon#about to read 4, iclass 4, count 2 2006.173.16:59:12.34#ibcon#read 4, iclass 4, count 2 2006.173.16:59:12.34#ibcon#about to read 5, iclass 4, count 2 2006.173.16:59:12.34#ibcon#read 5, iclass 4, count 2 2006.173.16:59:12.34#ibcon#about to read 6, iclass 4, count 2 2006.173.16:59:12.34#ibcon#read 6, iclass 4, count 2 2006.173.16:59:12.34#ibcon#end of sib2, iclass 4, count 2 2006.173.16:59:12.34#ibcon#*after write, iclass 4, count 2 2006.173.16:59:12.34#ibcon#*before return 0, iclass 4, count 2 2006.173.16:59:12.34#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.16:59:12.34#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.16:59:12.34#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.16:59:12.34#ibcon#ireg 7 cls_cnt 0 2006.173.16:59:12.34#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.16:59:12.46#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.16:59:12.46#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.16:59:12.46#ibcon#enter wrdev, iclass 4, count 0 2006.173.16:59:12.46#ibcon#first serial, iclass 4, count 0 2006.173.16:59:12.46#ibcon#enter sib2, iclass 4, count 0 2006.173.16:59:12.46#ibcon#flushed, iclass 4, count 0 2006.173.16:59:12.46#ibcon#about to write, iclass 4, count 0 2006.173.16:59:12.46#ibcon#wrote, iclass 4, count 0 2006.173.16:59:12.46#ibcon#about to read 3, iclass 4, count 0 2006.173.16:59:12.48#ibcon#read 3, iclass 4, count 0 2006.173.16:59:12.48#ibcon#about to read 4, iclass 4, count 0 2006.173.16:59:12.48#ibcon#read 4, iclass 4, count 0 2006.173.16:59:12.48#ibcon#about to read 5, iclass 4, count 0 2006.173.16:59:12.48#ibcon#read 5, iclass 4, count 0 2006.173.16:59:12.48#ibcon#about to read 6, iclass 4, count 0 2006.173.16:59:12.48#ibcon#read 6, iclass 4, count 0 2006.173.16:59:12.48#ibcon#end of sib2, iclass 4, count 0 2006.173.16:59:12.48#ibcon#*mode == 0, iclass 4, count 0 2006.173.16:59:12.48#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.16:59:12.48#ibcon#[25=USB\r\n] 2006.173.16:59:12.48#ibcon#*before write, iclass 4, count 0 2006.173.16:59:12.48#ibcon#enter sib2, iclass 4, count 0 2006.173.16:59:12.48#ibcon#flushed, iclass 4, count 0 2006.173.16:59:12.48#ibcon#about to write, iclass 4, count 0 2006.173.16:59:12.48#ibcon#wrote, iclass 4, count 0 2006.173.16:59:12.48#ibcon#about to read 3, iclass 4, count 0 2006.173.16:59:12.51#ibcon#read 3, iclass 4, count 0 2006.173.16:59:12.51#ibcon#about to read 4, iclass 4, count 0 2006.173.16:59:12.51#ibcon#read 4, iclass 4, count 0 2006.173.16:59:12.51#ibcon#about to read 5, iclass 4, count 0 2006.173.16:59:12.51#ibcon#read 5, iclass 4, count 0 2006.173.16:59:12.51#ibcon#about to read 6, iclass 4, count 0 2006.173.16:59:12.51#ibcon#read 6, iclass 4, count 0 2006.173.16:59:12.51#ibcon#end of sib2, iclass 4, count 0 2006.173.16:59:12.51#ibcon#*after write, iclass 4, count 0 2006.173.16:59:12.51#ibcon#*before return 0, iclass 4, count 0 2006.173.16:59:12.51#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.16:59:12.51#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.16:59:12.51#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.16:59:12.51#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.16:59:12.51$vck44/valo=2,534.99 2006.173.16:59:12.51#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.16:59:12.51#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.16:59:12.51#ibcon#ireg 17 cls_cnt 0 2006.173.16:59:12.51#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.16:59:12.51#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.16:59:12.51#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.16:59:12.51#ibcon#enter wrdev, iclass 6, count 0 2006.173.16:59:12.51#ibcon#first serial, iclass 6, count 0 2006.173.16:59:12.51#ibcon#enter sib2, iclass 6, count 0 2006.173.16:59:12.51#ibcon#flushed, iclass 6, count 0 2006.173.16:59:12.51#ibcon#about to write, iclass 6, count 0 2006.173.16:59:12.51#ibcon#wrote, iclass 6, count 0 2006.173.16:59:12.51#ibcon#about to read 3, iclass 6, count 0 2006.173.16:59:12.53#ibcon#read 3, iclass 6, count 0 2006.173.16:59:12.53#ibcon#about to read 4, iclass 6, count 0 2006.173.16:59:12.53#ibcon#read 4, iclass 6, count 0 2006.173.16:59:12.53#ibcon#about to read 5, iclass 6, count 0 2006.173.16:59:12.53#ibcon#read 5, iclass 6, count 0 2006.173.16:59:12.53#ibcon#about to read 6, iclass 6, count 0 2006.173.16:59:12.53#ibcon#read 6, iclass 6, count 0 2006.173.16:59:12.53#ibcon#end of sib2, iclass 6, count 0 2006.173.16:59:12.53#ibcon#*mode == 0, iclass 6, count 0 2006.173.16:59:12.53#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.16:59:12.53#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.16:59:12.53#ibcon#*before write, iclass 6, count 0 2006.173.16:59:12.53#ibcon#enter sib2, iclass 6, count 0 2006.173.16:59:12.53#ibcon#flushed, iclass 6, count 0 2006.173.16:59:12.53#ibcon#about to write, iclass 6, count 0 2006.173.16:59:12.53#ibcon#wrote, iclass 6, count 0 2006.173.16:59:12.53#ibcon#about to read 3, iclass 6, count 0 2006.173.16:59:12.57#ibcon#read 3, iclass 6, count 0 2006.173.16:59:12.57#ibcon#about to read 4, iclass 6, count 0 2006.173.16:59:12.57#ibcon#read 4, iclass 6, count 0 2006.173.16:59:12.57#ibcon#about to read 5, iclass 6, count 0 2006.173.16:59:12.57#ibcon#read 5, iclass 6, count 0 2006.173.16:59:12.57#ibcon#about to read 6, iclass 6, count 0 2006.173.16:59:12.57#ibcon#read 6, iclass 6, count 0 2006.173.16:59:12.57#ibcon#end of sib2, iclass 6, count 0 2006.173.16:59:12.57#ibcon#*after write, iclass 6, count 0 2006.173.16:59:12.57#ibcon#*before return 0, iclass 6, count 0 2006.173.16:59:12.57#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.16:59:12.57#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.16:59:12.57#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.16:59:12.57#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.16:59:12.57$vck44/va=2,6 2006.173.16:59:12.57#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.16:59:12.57#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.16:59:12.57#ibcon#ireg 11 cls_cnt 2 2006.173.16:59:12.57#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.16:59:12.63#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.16:59:12.63#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.16:59:12.63#ibcon#enter wrdev, iclass 10, count 2 2006.173.16:59:12.63#ibcon#first serial, iclass 10, count 2 2006.173.16:59:12.63#ibcon#enter sib2, iclass 10, count 2 2006.173.16:59:12.63#ibcon#flushed, iclass 10, count 2 2006.173.16:59:12.63#ibcon#about to write, iclass 10, count 2 2006.173.16:59:12.63#ibcon#wrote, iclass 10, count 2 2006.173.16:59:12.63#ibcon#about to read 3, iclass 10, count 2 2006.173.16:59:12.65#ibcon#read 3, iclass 10, count 2 2006.173.16:59:12.65#ibcon#about to read 4, iclass 10, count 2 2006.173.16:59:12.65#ibcon#read 4, iclass 10, count 2 2006.173.16:59:12.65#ibcon#about to read 5, iclass 10, count 2 2006.173.16:59:12.65#ibcon#read 5, iclass 10, count 2 2006.173.16:59:12.65#ibcon#about to read 6, iclass 10, count 2 2006.173.16:59:12.65#ibcon#read 6, iclass 10, count 2 2006.173.16:59:12.65#ibcon#end of sib2, iclass 10, count 2 2006.173.16:59:12.65#ibcon#*mode == 0, iclass 10, count 2 2006.173.16:59:12.65#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.16:59:12.65#ibcon#[25=AT02-06\r\n] 2006.173.16:59:12.65#ibcon#*before write, iclass 10, count 2 2006.173.16:59:12.65#ibcon#enter sib2, iclass 10, count 2 2006.173.16:59:12.65#ibcon#flushed, iclass 10, count 2 2006.173.16:59:12.65#ibcon#about to write, iclass 10, count 2 2006.173.16:59:12.65#ibcon#wrote, iclass 10, count 2 2006.173.16:59:12.65#ibcon#about to read 3, iclass 10, count 2 2006.173.16:59:12.68#ibcon#read 3, iclass 10, count 2 2006.173.16:59:12.68#ibcon#about to read 4, iclass 10, count 2 2006.173.16:59:12.68#ibcon#read 4, iclass 10, count 2 2006.173.16:59:12.68#ibcon#about to read 5, iclass 10, count 2 2006.173.16:59:12.68#ibcon#read 5, iclass 10, count 2 2006.173.16:59:12.68#ibcon#about to read 6, iclass 10, count 2 2006.173.16:59:12.68#ibcon#read 6, iclass 10, count 2 2006.173.16:59:12.68#ibcon#end of sib2, iclass 10, count 2 2006.173.16:59:12.68#ibcon#*after write, iclass 10, count 2 2006.173.16:59:12.68#ibcon#*before return 0, iclass 10, count 2 2006.173.16:59:12.68#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.16:59:12.68#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.16:59:12.68#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.16:59:12.68#ibcon#ireg 7 cls_cnt 0 2006.173.16:59:12.68#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.16:59:12.80#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.16:59:12.80#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.16:59:12.80#ibcon#enter wrdev, iclass 10, count 0 2006.173.16:59:12.80#ibcon#first serial, iclass 10, count 0 2006.173.16:59:12.80#ibcon#enter sib2, iclass 10, count 0 2006.173.16:59:12.80#ibcon#flushed, iclass 10, count 0 2006.173.16:59:12.80#ibcon#about to write, iclass 10, count 0 2006.173.16:59:12.80#ibcon#wrote, iclass 10, count 0 2006.173.16:59:12.80#ibcon#about to read 3, iclass 10, count 0 2006.173.16:59:12.82#ibcon#read 3, iclass 10, count 0 2006.173.16:59:12.82#ibcon#about to read 4, iclass 10, count 0 2006.173.16:59:12.82#ibcon#read 4, iclass 10, count 0 2006.173.16:59:12.82#ibcon#about to read 5, iclass 10, count 0 2006.173.16:59:12.82#ibcon#read 5, iclass 10, count 0 2006.173.16:59:12.82#ibcon#about to read 6, iclass 10, count 0 2006.173.16:59:12.82#ibcon#read 6, iclass 10, count 0 2006.173.16:59:12.82#ibcon#end of sib2, iclass 10, count 0 2006.173.16:59:12.82#ibcon#*mode == 0, iclass 10, count 0 2006.173.16:59:12.82#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.16:59:12.82#ibcon#[25=USB\r\n] 2006.173.16:59:12.82#ibcon#*before write, iclass 10, count 0 2006.173.16:59:12.82#ibcon#enter sib2, iclass 10, count 0 2006.173.16:59:12.82#ibcon#flushed, iclass 10, count 0 2006.173.16:59:12.82#ibcon#about to write, iclass 10, count 0 2006.173.16:59:12.82#ibcon#wrote, iclass 10, count 0 2006.173.16:59:12.82#ibcon#about to read 3, iclass 10, count 0 2006.173.16:59:12.85#ibcon#read 3, iclass 10, count 0 2006.173.16:59:12.85#ibcon#about to read 4, iclass 10, count 0 2006.173.16:59:12.85#ibcon#read 4, iclass 10, count 0 2006.173.16:59:12.85#ibcon#about to read 5, iclass 10, count 0 2006.173.16:59:12.85#ibcon#read 5, iclass 10, count 0 2006.173.16:59:12.85#ibcon#about to read 6, iclass 10, count 0 2006.173.16:59:12.85#ibcon#read 6, iclass 10, count 0 2006.173.16:59:12.85#ibcon#end of sib2, iclass 10, count 0 2006.173.16:59:12.85#ibcon#*after write, iclass 10, count 0 2006.173.16:59:12.85#ibcon#*before return 0, iclass 10, count 0 2006.173.16:59:12.85#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.16:59:12.85#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.16:59:12.85#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.16:59:12.85#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.16:59:12.85$vck44/valo=3,564.99 2006.173.16:59:12.85#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.16:59:12.85#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.16:59:12.85#ibcon#ireg 17 cls_cnt 0 2006.173.16:59:12.85#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.16:59:12.85#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.16:59:12.85#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.16:59:12.85#ibcon#enter wrdev, iclass 12, count 0 2006.173.16:59:12.85#ibcon#first serial, iclass 12, count 0 2006.173.16:59:12.85#ibcon#enter sib2, iclass 12, count 0 2006.173.16:59:12.85#ibcon#flushed, iclass 12, count 0 2006.173.16:59:12.85#ibcon#about to write, iclass 12, count 0 2006.173.16:59:12.85#ibcon#wrote, iclass 12, count 0 2006.173.16:59:12.85#ibcon#about to read 3, iclass 12, count 0 2006.173.16:59:12.87#ibcon#read 3, iclass 12, count 0 2006.173.16:59:12.87#ibcon#about to read 4, iclass 12, count 0 2006.173.16:59:12.87#ibcon#read 4, iclass 12, count 0 2006.173.16:59:12.87#ibcon#about to read 5, iclass 12, count 0 2006.173.16:59:12.87#ibcon#read 5, iclass 12, count 0 2006.173.16:59:12.87#ibcon#about to read 6, iclass 12, count 0 2006.173.16:59:12.87#ibcon#read 6, iclass 12, count 0 2006.173.16:59:12.87#ibcon#end of sib2, iclass 12, count 0 2006.173.16:59:12.87#ibcon#*mode == 0, iclass 12, count 0 2006.173.16:59:12.87#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.16:59:12.87#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.16:59:12.87#ibcon#*before write, iclass 12, count 0 2006.173.16:59:12.87#ibcon#enter sib2, iclass 12, count 0 2006.173.16:59:12.87#ibcon#flushed, iclass 12, count 0 2006.173.16:59:12.87#ibcon#about to write, iclass 12, count 0 2006.173.16:59:12.87#ibcon#wrote, iclass 12, count 0 2006.173.16:59:12.87#ibcon#about to read 3, iclass 12, count 0 2006.173.16:59:12.91#ibcon#read 3, iclass 12, count 0 2006.173.16:59:12.91#ibcon#about to read 4, iclass 12, count 0 2006.173.16:59:12.91#ibcon#read 4, iclass 12, count 0 2006.173.16:59:12.91#ibcon#about to read 5, iclass 12, count 0 2006.173.16:59:12.91#ibcon#read 5, iclass 12, count 0 2006.173.16:59:12.91#ibcon#about to read 6, iclass 12, count 0 2006.173.16:59:12.91#ibcon#read 6, iclass 12, count 0 2006.173.16:59:12.91#ibcon#end of sib2, iclass 12, count 0 2006.173.16:59:12.91#ibcon#*after write, iclass 12, count 0 2006.173.16:59:12.91#ibcon#*before return 0, iclass 12, count 0 2006.173.16:59:12.91#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.16:59:12.91#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.16:59:12.91#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.16:59:12.91#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.16:59:12.91$vck44/va=3,5 2006.173.16:59:12.91#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.16:59:12.91#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.16:59:12.91#ibcon#ireg 11 cls_cnt 2 2006.173.16:59:12.91#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.16:59:12.97#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.16:59:12.97#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.16:59:12.97#ibcon#enter wrdev, iclass 14, count 2 2006.173.16:59:12.97#ibcon#first serial, iclass 14, count 2 2006.173.16:59:12.97#ibcon#enter sib2, iclass 14, count 2 2006.173.16:59:12.97#ibcon#flushed, iclass 14, count 2 2006.173.16:59:12.97#ibcon#about to write, iclass 14, count 2 2006.173.16:59:12.97#ibcon#wrote, iclass 14, count 2 2006.173.16:59:12.97#ibcon#about to read 3, iclass 14, count 2 2006.173.16:59:12.99#ibcon#read 3, iclass 14, count 2 2006.173.16:59:12.99#ibcon#about to read 4, iclass 14, count 2 2006.173.16:59:12.99#ibcon#read 4, iclass 14, count 2 2006.173.16:59:12.99#ibcon#about to read 5, iclass 14, count 2 2006.173.16:59:12.99#ibcon#read 5, iclass 14, count 2 2006.173.16:59:12.99#ibcon#about to read 6, iclass 14, count 2 2006.173.16:59:12.99#ibcon#read 6, iclass 14, count 2 2006.173.16:59:12.99#ibcon#end of sib2, iclass 14, count 2 2006.173.16:59:12.99#ibcon#*mode == 0, iclass 14, count 2 2006.173.16:59:12.99#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.16:59:12.99#ibcon#[25=AT03-05\r\n] 2006.173.16:59:12.99#ibcon#*before write, iclass 14, count 2 2006.173.16:59:12.99#ibcon#enter sib2, iclass 14, count 2 2006.173.16:59:12.99#ibcon#flushed, iclass 14, count 2 2006.173.16:59:12.99#ibcon#about to write, iclass 14, count 2 2006.173.16:59:12.99#ibcon#wrote, iclass 14, count 2 2006.173.16:59:12.99#ibcon#about to read 3, iclass 14, count 2 2006.173.16:59:13.02#ibcon#read 3, iclass 14, count 2 2006.173.16:59:13.02#ibcon#about to read 4, iclass 14, count 2 2006.173.16:59:13.02#ibcon#read 4, iclass 14, count 2 2006.173.16:59:13.02#ibcon#about to read 5, iclass 14, count 2 2006.173.16:59:13.02#ibcon#read 5, iclass 14, count 2 2006.173.16:59:13.02#ibcon#about to read 6, iclass 14, count 2 2006.173.16:59:13.02#ibcon#read 6, iclass 14, count 2 2006.173.16:59:13.02#ibcon#end of sib2, iclass 14, count 2 2006.173.16:59:13.02#ibcon#*after write, iclass 14, count 2 2006.173.16:59:13.02#ibcon#*before return 0, iclass 14, count 2 2006.173.16:59:13.02#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.16:59:13.02#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.16:59:13.02#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.16:59:13.02#ibcon#ireg 7 cls_cnt 0 2006.173.16:59:13.02#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.16:59:13.14#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.16:59:13.14#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.16:59:13.14#ibcon#enter wrdev, iclass 14, count 0 2006.173.16:59:13.14#ibcon#first serial, iclass 14, count 0 2006.173.16:59:13.14#ibcon#enter sib2, iclass 14, count 0 2006.173.16:59:13.14#ibcon#flushed, iclass 14, count 0 2006.173.16:59:13.14#ibcon#about to write, iclass 14, count 0 2006.173.16:59:13.14#ibcon#wrote, iclass 14, count 0 2006.173.16:59:13.14#ibcon#about to read 3, iclass 14, count 0 2006.173.16:59:13.16#ibcon#read 3, iclass 14, count 0 2006.173.16:59:13.16#ibcon#about to read 4, iclass 14, count 0 2006.173.16:59:13.16#ibcon#read 4, iclass 14, count 0 2006.173.16:59:13.16#ibcon#about to read 5, iclass 14, count 0 2006.173.16:59:13.16#ibcon#read 5, iclass 14, count 0 2006.173.16:59:13.16#ibcon#about to read 6, iclass 14, count 0 2006.173.16:59:13.16#ibcon#read 6, iclass 14, count 0 2006.173.16:59:13.16#ibcon#end of sib2, iclass 14, count 0 2006.173.16:59:13.16#ibcon#*mode == 0, iclass 14, count 0 2006.173.16:59:13.16#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.16:59:13.16#ibcon#[25=USB\r\n] 2006.173.16:59:13.16#ibcon#*before write, iclass 14, count 0 2006.173.16:59:13.16#ibcon#enter sib2, iclass 14, count 0 2006.173.16:59:13.16#ibcon#flushed, iclass 14, count 0 2006.173.16:59:13.16#ibcon#about to write, iclass 14, count 0 2006.173.16:59:13.16#ibcon#wrote, iclass 14, count 0 2006.173.16:59:13.16#ibcon#about to read 3, iclass 14, count 0 2006.173.16:59:13.19#ibcon#read 3, iclass 14, count 0 2006.173.16:59:13.19#ibcon#about to read 4, iclass 14, count 0 2006.173.16:59:13.19#ibcon#read 4, iclass 14, count 0 2006.173.16:59:13.19#ibcon#about to read 5, iclass 14, count 0 2006.173.16:59:13.19#ibcon#read 5, iclass 14, count 0 2006.173.16:59:13.19#ibcon#about to read 6, iclass 14, count 0 2006.173.16:59:13.19#ibcon#read 6, iclass 14, count 0 2006.173.16:59:13.19#ibcon#end of sib2, iclass 14, count 0 2006.173.16:59:13.19#ibcon#*after write, iclass 14, count 0 2006.173.16:59:13.19#ibcon#*before return 0, iclass 14, count 0 2006.173.16:59:13.19#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.16:59:13.19#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.16:59:13.19#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.16:59:13.19#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.16:59:13.19$vck44/valo=4,624.99 2006.173.16:59:13.19#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.16:59:13.19#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.16:59:13.19#ibcon#ireg 17 cls_cnt 0 2006.173.16:59:13.19#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.16:59:13.19#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.16:59:13.19#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.16:59:13.19#ibcon#enter wrdev, iclass 16, count 0 2006.173.16:59:13.19#ibcon#first serial, iclass 16, count 0 2006.173.16:59:13.19#ibcon#enter sib2, iclass 16, count 0 2006.173.16:59:13.19#ibcon#flushed, iclass 16, count 0 2006.173.16:59:13.19#ibcon#about to write, iclass 16, count 0 2006.173.16:59:13.19#ibcon#wrote, iclass 16, count 0 2006.173.16:59:13.19#ibcon#about to read 3, iclass 16, count 0 2006.173.16:59:13.21#ibcon#read 3, iclass 16, count 0 2006.173.16:59:13.21#ibcon#about to read 4, iclass 16, count 0 2006.173.16:59:13.21#ibcon#read 4, iclass 16, count 0 2006.173.16:59:13.21#ibcon#about to read 5, iclass 16, count 0 2006.173.16:59:13.21#ibcon#read 5, iclass 16, count 0 2006.173.16:59:13.21#ibcon#about to read 6, iclass 16, count 0 2006.173.16:59:13.21#ibcon#read 6, iclass 16, count 0 2006.173.16:59:13.21#ibcon#end of sib2, iclass 16, count 0 2006.173.16:59:13.21#ibcon#*mode == 0, iclass 16, count 0 2006.173.16:59:13.21#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.16:59:13.21#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.16:59:13.21#ibcon#*before write, iclass 16, count 0 2006.173.16:59:13.21#ibcon#enter sib2, iclass 16, count 0 2006.173.16:59:13.21#ibcon#flushed, iclass 16, count 0 2006.173.16:59:13.21#ibcon#about to write, iclass 16, count 0 2006.173.16:59:13.21#ibcon#wrote, iclass 16, count 0 2006.173.16:59:13.21#ibcon#about to read 3, iclass 16, count 0 2006.173.16:59:13.25#ibcon#read 3, iclass 16, count 0 2006.173.16:59:13.25#ibcon#about to read 4, iclass 16, count 0 2006.173.16:59:13.25#ibcon#read 4, iclass 16, count 0 2006.173.16:59:13.25#ibcon#about to read 5, iclass 16, count 0 2006.173.16:59:13.25#ibcon#read 5, iclass 16, count 0 2006.173.16:59:13.25#ibcon#about to read 6, iclass 16, count 0 2006.173.16:59:13.25#ibcon#read 6, iclass 16, count 0 2006.173.16:59:13.25#ibcon#end of sib2, iclass 16, count 0 2006.173.16:59:13.25#ibcon#*after write, iclass 16, count 0 2006.173.16:59:13.25#ibcon#*before return 0, iclass 16, count 0 2006.173.16:59:13.25#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.16:59:13.25#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.16:59:13.25#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.16:59:13.25#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.16:59:13.25$vck44/va=4,6 2006.173.16:59:13.25#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.16:59:13.25#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.16:59:13.25#ibcon#ireg 11 cls_cnt 2 2006.173.16:59:13.25#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.16:59:13.31#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.16:59:13.31#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.16:59:13.31#ibcon#enter wrdev, iclass 18, count 2 2006.173.16:59:13.31#ibcon#first serial, iclass 18, count 2 2006.173.16:59:13.31#ibcon#enter sib2, iclass 18, count 2 2006.173.16:59:13.31#ibcon#flushed, iclass 18, count 2 2006.173.16:59:13.31#ibcon#about to write, iclass 18, count 2 2006.173.16:59:13.31#ibcon#wrote, iclass 18, count 2 2006.173.16:59:13.31#ibcon#about to read 3, iclass 18, count 2 2006.173.16:59:13.33#ibcon#read 3, iclass 18, count 2 2006.173.16:59:13.33#ibcon#about to read 4, iclass 18, count 2 2006.173.16:59:13.33#ibcon#read 4, iclass 18, count 2 2006.173.16:59:13.33#ibcon#about to read 5, iclass 18, count 2 2006.173.16:59:13.33#ibcon#read 5, iclass 18, count 2 2006.173.16:59:13.33#ibcon#about to read 6, iclass 18, count 2 2006.173.16:59:13.33#ibcon#read 6, iclass 18, count 2 2006.173.16:59:13.33#ibcon#end of sib2, iclass 18, count 2 2006.173.16:59:13.33#ibcon#*mode == 0, iclass 18, count 2 2006.173.16:59:13.33#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.16:59:13.33#ibcon#[25=AT04-06\r\n] 2006.173.16:59:13.33#ibcon#*before write, iclass 18, count 2 2006.173.16:59:13.33#ibcon#enter sib2, iclass 18, count 2 2006.173.16:59:13.33#ibcon#flushed, iclass 18, count 2 2006.173.16:59:13.33#ibcon#about to write, iclass 18, count 2 2006.173.16:59:13.33#ibcon#wrote, iclass 18, count 2 2006.173.16:59:13.33#ibcon#about to read 3, iclass 18, count 2 2006.173.16:59:13.36#ibcon#read 3, iclass 18, count 2 2006.173.16:59:13.36#ibcon#about to read 4, iclass 18, count 2 2006.173.16:59:13.36#ibcon#read 4, iclass 18, count 2 2006.173.16:59:13.36#ibcon#about to read 5, iclass 18, count 2 2006.173.16:59:13.36#ibcon#read 5, iclass 18, count 2 2006.173.16:59:13.36#ibcon#about to read 6, iclass 18, count 2 2006.173.16:59:13.36#ibcon#read 6, iclass 18, count 2 2006.173.16:59:13.36#ibcon#end of sib2, iclass 18, count 2 2006.173.16:59:13.36#ibcon#*after write, iclass 18, count 2 2006.173.16:59:13.36#ibcon#*before return 0, iclass 18, count 2 2006.173.16:59:13.36#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.16:59:13.36#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.16:59:13.36#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.16:59:13.36#ibcon#ireg 7 cls_cnt 0 2006.173.16:59:13.36#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.16:59:13.48#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.16:59:13.48#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.16:59:13.48#ibcon#enter wrdev, iclass 18, count 0 2006.173.16:59:13.48#ibcon#first serial, iclass 18, count 0 2006.173.16:59:13.48#ibcon#enter sib2, iclass 18, count 0 2006.173.16:59:13.48#ibcon#flushed, iclass 18, count 0 2006.173.16:59:13.48#ibcon#about to write, iclass 18, count 0 2006.173.16:59:13.48#ibcon#wrote, iclass 18, count 0 2006.173.16:59:13.48#ibcon#about to read 3, iclass 18, count 0 2006.173.16:59:13.50#ibcon#read 3, iclass 18, count 0 2006.173.16:59:13.50#ibcon#about to read 4, iclass 18, count 0 2006.173.16:59:13.50#ibcon#read 4, iclass 18, count 0 2006.173.16:59:13.50#ibcon#about to read 5, iclass 18, count 0 2006.173.16:59:13.50#ibcon#read 5, iclass 18, count 0 2006.173.16:59:13.50#ibcon#about to read 6, iclass 18, count 0 2006.173.16:59:13.50#ibcon#read 6, iclass 18, count 0 2006.173.16:59:13.50#ibcon#end of sib2, iclass 18, count 0 2006.173.16:59:13.50#ibcon#*mode == 0, iclass 18, count 0 2006.173.16:59:13.50#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.16:59:13.50#ibcon#[25=USB\r\n] 2006.173.16:59:13.50#ibcon#*before write, iclass 18, count 0 2006.173.16:59:13.50#ibcon#enter sib2, iclass 18, count 0 2006.173.16:59:13.50#ibcon#flushed, iclass 18, count 0 2006.173.16:59:13.50#ibcon#about to write, iclass 18, count 0 2006.173.16:59:13.50#ibcon#wrote, iclass 18, count 0 2006.173.16:59:13.50#ibcon#about to read 3, iclass 18, count 0 2006.173.16:59:13.53#ibcon#read 3, iclass 18, count 0 2006.173.16:59:13.53#ibcon#about to read 4, iclass 18, count 0 2006.173.16:59:13.53#ibcon#read 4, iclass 18, count 0 2006.173.16:59:13.53#ibcon#about to read 5, iclass 18, count 0 2006.173.16:59:13.53#ibcon#read 5, iclass 18, count 0 2006.173.16:59:13.53#ibcon#about to read 6, iclass 18, count 0 2006.173.16:59:13.53#ibcon#read 6, iclass 18, count 0 2006.173.16:59:13.53#ibcon#end of sib2, iclass 18, count 0 2006.173.16:59:13.53#ibcon#*after write, iclass 18, count 0 2006.173.16:59:13.53#ibcon#*before return 0, iclass 18, count 0 2006.173.16:59:13.53#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.16:59:13.53#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.16:59:13.53#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.16:59:13.53#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.16:59:13.53$vck44/valo=5,734.99 2006.173.16:59:13.53#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.16:59:13.53#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.16:59:13.53#ibcon#ireg 17 cls_cnt 0 2006.173.16:59:13.53#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.16:59:13.53#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.16:59:13.53#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.16:59:13.53#ibcon#enter wrdev, iclass 20, count 0 2006.173.16:59:13.53#ibcon#first serial, iclass 20, count 0 2006.173.16:59:13.53#ibcon#enter sib2, iclass 20, count 0 2006.173.16:59:13.53#ibcon#flushed, iclass 20, count 0 2006.173.16:59:13.53#ibcon#about to write, iclass 20, count 0 2006.173.16:59:13.53#ibcon#wrote, iclass 20, count 0 2006.173.16:59:13.53#ibcon#about to read 3, iclass 20, count 0 2006.173.16:59:13.55#ibcon#read 3, iclass 20, count 0 2006.173.16:59:13.55#ibcon#about to read 4, iclass 20, count 0 2006.173.16:59:13.55#ibcon#read 4, iclass 20, count 0 2006.173.16:59:13.55#ibcon#about to read 5, iclass 20, count 0 2006.173.16:59:13.55#ibcon#read 5, iclass 20, count 0 2006.173.16:59:13.55#ibcon#about to read 6, iclass 20, count 0 2006.173.16:59:13.55#ibcon#read 6, iclass 20, count 0 2006.173.16:59:13.55#ibcon#end of sib2, iclass 20, count 0 2006.173.16:59:13.55#ibcon#*mode == 0, iclass 20, count 0 2006.173.16:59:13.55#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.16:59:13.55#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.16:59:13.55#ibcon#*before write, iclass 20, count 0 2006.173.16:59:13.55#ibcon#enter sib2, iclass 20, count 0 2006.173.16:59:13.55#ibcon#flushed, iclass 20, count 0 2006.173.16:59:13.55#ibcon#about to write, iclass 20, count 0 2006.173.16:59:13.55#ibcon#wrote, iclass 20, count 0 2006.173.16:59:13.55#ibcon#about to read 3, iclass 20, count 0 2006.173.16:59:13.59#ibcon#read 3, iclass 20, count 0 2006.173.16:59:13.59#ibcon#about to read 4, iclass 20, count 0 2006.173.16:59:13.59#ibcon#read 4, iclass 20, count 0 2006.173.16:59:13.59#ibcon#about to read 5, iclass 20, count 0 2006.173.16:59:13.59#ibcon#read 5, iclass 20, count 0 2006.173.16:59:13.59#ibcon#about to read 6, iclass 20, count 0 2006.173.16:59:13.59#ibcon#read 6, iclass 20, count 0 2006.173.16:59:13.59#ibcon#end of sib2, iclass 20, count 0 2006.173.16:59:13.59#ibcon#*after write, iclass 20, count 0 2006.173.16:59:13.59#ibcon#*before return 0, iclass 20, count 0 2006.173.16:59:13.59#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.16:59:13.59#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.16:59:13.59#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.16:59:13.59#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.16:59:13.59$vck44/va=5,4 2006.173.16:59:13.59#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.16:59:13.59#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.16:59:13.59#ibcon#ireg 11 cls_cnt 2 2006.173.16:59:13.59#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.16:59:13.65#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.16:59:13.65#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.16:59:13.65#ibcon#enter wrdev, iclass 22, count 2 2006.173.16:59:13.65#ibcon#first serial, iclass 22, count 2 2006.173.16:59:13.65#ibcon#enter sib2, iclass 22, count 2 2006.173.16:59:13.65#ibcon#flushed, iclass 22, count 2 2006.173.16:59:13.65#ibcon#about to write, iclass 22, count 2 2006.173.16:59:13.65#ibcon#wrote, iclass 22, count 2 2006.173.16:59:13.65#ibcon#about to read 3, iclass 22, count 2 2006.173.16:59:13.67#ibcon#read 3, iclass 22, count 2 2006.173.16:59:13.67#ibcon#about to read 4, iclass 22, count 2 2006.173.16:59:13.67#ibcon#read 4, iclass 22, count 2 2006.173.16:59:13.67#ibcon#about to read 5, iclass 22, count 2 2006.173.16:59:13.67#ibcon#read 5, iclass 22, count 2 2006.173.16:59:13.67#ibcon#about to read 6, iclass 22, count 2 2006.173.16:59:13.67#ibcon#read 6, iclass 22, count 2 2006.173.16:59:13.67#ibcon#end of sib2, iclass 22, count 2 2006.173.16:59:13.67#ibcon#*mode == 0, iclass 22, count 2 2006.173.16:59:13.67#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.16:59:13.67#ibcon#[25=AT05-04\r\n] 2006.173.16:59:13.67#ibcon#*before write, iclass 22, count 2 2006.173.16:59:13.67#ibcon#enter sib2, iclass 22, count 2 2006.173.16:59:13.67#ibcon#flushed, iclass 22, count 2 2006.173.16:59:13.67#ibcon#about to write, iclass 22, count 2 2006.173.16:59:13.67#ibcon#wrote, iclass 22, count 2 2006.173.16:59:13.67#ibcon#about to read 3, iclass 22, count 2 2006.173.16:59:13.70#ibcon#read 3, iclass 22, count 2 2006.173.16:59:13.70#ibcon#about to read 4, iclass 22, count 2 2006.173.16:59:13.70#ibcon#read 4, iclass 22, count 2 2006.173.16:59:13.70#ibcon#about to read 5, iclass 22, count 2 2006.173.16:59:13.70#ibcon#read 5, iclass 22, count 2 2006.173.16:59:13.70#ibcon#about to read 6, iclass 22, count 2 2006.173.16:59:13.70#ibcon#read 6, iclass 22, count 2 2006.173.16:59:13.70#ibcon#end of sib2, iclass 22, count 2 2006.173.16:59:13.70#ibcon#*after write, iclass 22, count 2 2006.173.16:59:13.70#ibcon#*before return 0, iclass 22, count 2 2006.173.16:59:13.70#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.16:59:13.70#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.16:59:13.70#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.16:59:13.70#ibcon#ireg 7 cls_cnt 0 2006.173.16:59:13.70#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.16:59:13.82#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.16:59:13.82#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.16:59:13.82#ibcon#enter wrdev, iclass 22, count 0 2006.173.16:59:13.82#ibcon#first serial, iclass 22, count 0 2006.173.16:59:13.82#ibcon#enter sib2, iclass 22, count 0 2006.173.16:59:13.82#ibcon#flushed, iclass 22, count 0 2006.173.16:59:13.82#ibcon#about to write, iclass 22, count 0 2006.173.16:59:13.82#ibcon#wrote, iclass 22, count 0 2006.173.16:59:13.82#ibcon#about to read 3, iclass 22, count 0 2006.173.16:59:13.84#ibcon#read 3, iclass 22, count 0 2006.173.16:59:13.84#ibcon#about to read 4, iclass 22, count 0 2006.173.16:59:13.84#ibcon#read 4, iclass 22, count 0 2006.173.16:59:13.84#ibcon#about to read 5, iclass 22, count 0 2006.173.16:59:13.84#ibcon#read 5, iclass 22, count 0 2006.173.16:59:13.84#ibcon#about to read 6, iclass 22, count 0 2006.173.16:59:13.84#ibcon#read 6, iclass 22, count 0 2006.173.16:59:13.84#ibcon#end of sib2, iclass 22, count 0 2006.173.16:59:13.84#ibcon#*mode == 0, iclass 22, count 0 2006.173.16:59:13.84#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.16:59:13.84#ibcon#[25=USB\r\n] 2006.173.16:59:13.84#ibcon#*before write, iclass 22, count 0 2006.173.16:59:13.84#ibcon#enter sib2, iclass 22, count 0 2006.173.16:59:13.84#ibcon#flushed, iclass 22, count 0 2006.173.16:59:13.84#ibcon#about to write, iclass 22, count 0 2006.173.16:59:13.84#ibcon#wrote, iclass 22, count 0 2006.173.16:59:13.84#ibcon#about to read 3, iclass 22, count 0 2006.173.16:59:13.87#ibcon#read 3, iclass 22, count 0 2006.173.16:59:13.87#ibcon#about to read 4, iclass 22, count 0 2006.173.16:59:13.87#ibcon#read 4, iclass 22, count 0 2006.173.16:59:13.87#ibcon#about to read 5, iclass 22, count 0 2006.173.16:59:13.87#ibcon#read 5, iclass 22, count 0 2006.173.16:59:13.87#ibcon#about to read 6, iclass 22, count 0 2006.173.16:59:13.87#ibcon#read 6, iclass 22, count 0 2006.173.16:59:13.87#ibcon#end of sib2, iclass 22, count 0 2006.173.16:59:13.87#ibcon#*after write, iclass 22, count 0 2006.173.16:59:13.87#ibcon#*before return 0, iclass 22, count 0 2006.173.16:59:13.87#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.16:59:13.87#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.16:59:13.87#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.16:59:13.87#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.16:59:13.87$vck44/valo=6,814.99 2006.173.16:59:13.87#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.16:59:13.87#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.16:59:13.87#ibcon#ireg 17 cls_cnt 0 2006.173.16:59:13.87#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.16:59:13.87#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.16:59:13.87#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.16:59:13.87#ibcon#enter wrdev, iclass 24, count 0 2006.173.16:59:13.87#ibcon#first serial, iclass 24, count 0 2006.173.16:59:13.87#ibcon#enter sib2, iclass 24, count 0 2006.173.16:59:13.87#ibcon#flushed, iclass 24, count 0 2006.173.16:59:13.87#ibcon#about to write, iclass 24, count 0 2006.173.16:59:13.87#ibcon#wrote, iclass 24, count 0 2006.173.16:59:13.87#ibcon#about to read 3, iclass 24, count 0 2006.173.16:59:13.89#ibcon#read 3, iclass 24, count 0 2006.173.16:59:13.89#ibcon#about to read 4, iclass 24, count 0 2006.173.16:59:13.89#ibcon#read 4, iclass 24, count 0 2006.173.16:59:13.89#ibcon#about to read 5, iclass 24, count 0 2006.173.16:59:13.89#ibcon#read 5, iclass 24, count 0 2006.173.16:59:13.89#ibcon#about to read 6, iclass 24, count 0 2006.173.16:59:13.89#ibcon#read 6, iclass 24, count 0 2006.173.16:59:13.89#ibcon#end of sib2, iclass 24, count 0 2006.173.16:59:13.89#ibcon#*mode == 0, iclass 24, count 0 2006.173.16:59:13.89#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.16:59:13.89#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.16:59:13.89#ibcon#*before write, iclass 24, count 0 2006.173.16:59:13.89#ibcon#enter sib2, iclass 24, count 0 2006.173.16:59:13.89#ibcon#flushed, iclass 24, count 0 2006.173.16:59:13.89#ibcon#about to write, iclass 24, count 0 2006.173.16:59:13.89#ibcon#wrote, iclass 24, count 0 2006.173.16:59:13.89#ibcon#about to read 3, iclass 24, count 0 2006.173.16:59:13.93#ibcon#read 3, iclass 24, count 0 2006.173.16:59:13.93#ibcon#about to read 4, iclass 24, count 0 2006.173.16:59:13.93#ibcon#read 4, iclass 24, count 0 2006.173.16:59:13.93#ibcon#about to read 5, iclass 24, count 0 2006.173.16:59:13.93#ibcon#read 5, iclass 24, count 0 2006.173.16:59:13.93#ibcon#about to read 6, iclass 24, count 0 2006.173.16:59:13.93#ibcon#read 6, iclass 24, count 0 2006.173.16:59:13.93#ibcon#end of sib2, iclass 24, count 0 2006.173.16:59:13.93#ibcon#*after write, iclass 24, count 0 2006.173.16:59:13.93#ibcon#*before return 0, iclass 24, count 0 2006.173.16:59:13.93#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.16:59:13.93#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.16:59:13.93#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.16:59:13.93#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.16:59:13.93$vck44/va=6,3 2006.173.16:59:13.93#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.16:59:13.93#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.16:59:13.93#ibcon#ireg 11 cls_cnt 2 2006.173.16:59:13.93#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.16:59:13.99#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.16:59:13.99#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.16:59:13.99#ibcon#enter wrdev, iclass 26, count 2 2006.173.16:59:13.99#ibcon#first serial, iclass 26, count 2 2006.173.16:59:13.99#ibcon#enter sib2, iclass 26, count 2 2006.173.16:59:13.99#ibcon#flushed, iclass 26, count 2 2006.173.16:59:13.99#ibcon#about to write, iclass 26, count 2 2006.173.16:59:13.99#ibcon#wrote, iclass 26, count 2 2006.173.16:59:13.99#ibcon#about to read 3, iclass 26, count 2 2006.173.16:59:14.01#ibcon#read 3, iclass 26, count 2 2006.173.16:59:14.01#ibcon#about to read 4, iclass 26, count 2 2006.173.16:59:14.01#ibcon#read 4, iclass 26, count 2 2006.173.16:59:14.01#ibcon#about to read 5, iclass 26, count 2 2006.173.16:59:14.01#ibcon#read 5, iclass 26, count 2 2006.173.16:59:14.01#ibcon#about to read 6, iclass 26, count 2 2006.173.16:59:14.01#ibcon#read 6, iclass 26, count 2 2006.173.16:59:14.01#ibcon#end of sib2, iclass 26, count 2 2006.173.16:59:14.01#ibcon#*mode == 0, iclass 26, count 2 2006.173.16:59:14.01#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.16:59:14.01#ibcon#[25=AT06-03\r\n] 2006.173.16:59:14.01#ibcon#*before write, iclass 26, count 2 2006.173.16:59:14.01#ibcon#enter sib2, iclass 26, count 2 2006.173.16:59:14.01#ibcon#flushed, iclass 26, count 2 2006.173.16:59:14.01#ibcon#about to write, iclass 26, count 2 2006.173.16:59:14.01#ibcon#wrote, iclass 26, count 2 2006.173.16:59:14.01#ibcon#about to read 3, iclass 26, count 2 2006.173.16:59:14.04#ibcon#read 3, iclass 26, count 2 2006.173.16:59:14.04#ibcon#about to read 4, iclass 26, count 2 2006.173.16:59:14.04#ibcon#read 4, iclass 26, count 2 2006.173.16:59:14.04#ibcon#about to read 5, iclass 26, count 2 2006.173.16:59:14.04#ibcon#read 5, iclass 26, count 2 2006.173.16:59:14.04#ibcon#about to read 6, iclass 26, count 2 2006.173.16:59:14.04#ibcon#read 6, iclass 26, count 2 2006.173.16:59:14.04#ibcon#end of sib2, iclass 26, count 2 2006.173.16:59:14.04#ibcon#*after write, iclass 26, count 2 2006.173.16:59:14.04#ibcon#*before return 0, iclass 26, count 2 2006.173.16:59:14.04#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.16:59:14.04#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.16:59:14.04#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.16:59:14.04#ibcon#ireg 7 cls_cnt 0 2006.173.16:59:14.04#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.16:59:14.16#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.16:59:14.16#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.16:59:14.16#ibcon#enter wrdev, iclass 26, count 0 2006.173.16:59:14.16#ibcon#first serial, iclass 26, count 0 2006.173.16:59:14.16#ibcon#enter sib2, iclass 26, count 0 2006.173.16:59:14.16#ibcon#flushed, iclass 26, count 0 2006.173.16:59:14.16#ibcon#about to write, iclass 26, count 0 2006.173.16:59:14.16#ibcon#wrote, iclass 26, count 0 2006.173.16:59:14.16#ibcon#about to read 3, iclass 26, count 0 2006.173.16:59:14.18#ibcon#read 3, iclass 26, count 0 2006.173.16:59:14.18#ibcon#about to read 4, iclass 26, count 0 2006.173.16:59:14.18#ibcon#read 4, iclass 26, count 0 2006.173.16:59:14.18#ibcon#about to read 5, iclass 26, count 0 2006.173.16:59:14.18#ibcon#read 5, iclass 26, count 0 2006.173.16:59:14.18#ibcon#about to read 6, iclass 26, count 0 2006.173.16:59:14.18#ibcon#read 6, iclass 26, count 0 2006.173.16:59:14.18#ibcon#end of sib2, iclass 26, count 0 2006.173.16:59:14.18#ibcon#*mode == 0, iclass 26, count 0 2006.173.16:59:14.18#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.16:59:14.18#ibcon#[25=USB\r\n] 2006.173.16:59:14.18#ibcon#*before write, iclass 26, count 0 2006.173.16:59:14.18#ibcon#enter sib2, iclass 26, count 0 2006.173.16:59:14.18#ibcon#flushed, iclass 26, count 0 2006.173.16:59:14.18#ibcon#about to write, iclass 26, count 0 2006.173.16:59:14.18#ibcon#wrote, iclass 26, count 0 2006.173.16:59:14.18#ibcon#about to read 3, iclass 26, count 0 2006.173.16:59:14.21#ibcon#read 3, iclass 26, count 0 2006.173.16:59:14.21#ibcon#about to read 4, iclass 26, count 0 2006.173.16:59:14.21#ibcon#read 4, iclass 26, count 0 2006.173.16:59:14.21#ibcon#about to read 5, iclass 26, count 0 2006.173.16:59:14.21#ibcon#read 5, iclass 26, count 0 2006.173.16:59:14.21#ibcon#about to read 6, iclass 26, count 0 2006.173.16:59:14.21#ibcon#read 6, iclass 26, count 0 2006.173.16:59:14.21#ibcon#end of sib2, iclass 26, count 0 2006.173.16:59:14.21#ibcon#*after write, iclass 26, count 0 2006.173.16:59:14.21#ibcon#*before return 0, iclass 26, count 0 2006.173.16:59:14.21#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.16:59:14.21#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.16:59:14.21#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.16:59:14.21#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.16:59:14.21$vck44/valo=7,864.99 2006.173.16:59:14.21#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.16:59:14.21#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.16:59:14.21#ibcon#ireg 17 cls_cnt 0 2006.173.16:59:14.21#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.16:59:14.21#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.16:59:14.21#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.16:59:14.21#ibcon#enter wrdev, iclass 28, count 0 2006.173.16:59:14.21#ibcon#first serial, iclass 28, count 0 2006.173.16:59:14.21#ibcon#enter sib2, iclass 28, count 0 2006.173.16:59:14.21#ibcon#flushed, iclass 28, count 0 2006.173.16:59:14.21#ibcon#about to write, iclass 28, count 0 2006.173.16:59:14.21#ibcon#wrote, iclass 28, count 0 2006.173.16:59:14.21#ibcon#about to read 3, iclass 28, count 0 2006.173.16:59:14.23#ibcon#read 3, iclass 28, count 0 2006.173.16:59:14.23#ibcon#about to read 4, iclass 28, count 0 2006.173.16:59:14.23#ibcon#read 4, iclass 28, count 0 2006.173.16:59:14.23#ibcon#about to read 5, iclass 28, count 0 2006.173.16:59:14.23#ibcon#read 5, iclass 28, count 0 2006.173.16:59:14.23#ibcon#about to read 6, iclass 28, count 0 2006.173.16:59:14.23#ibcon#read 6, iclass 28, count 0 2006.173.16:59:14.23#ibcon#end of sib2, iclass 28, count 0 2006.173.16:59:14.23#ibcon#*mode == 0, iclass 28, count 0 2006.173.16:59:14.23#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.16:59:14.23#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.16:59:14.23#ibcon#*before write, iclass 28, count 0 2006.173.16:59:14.23#ibcon#enter sib2, iclass 28, count 0 2006.173.16:59:14.23#ibcon#flushed, iclass 28, count 0 2006.173.16:59:14.23#ibcon#about to write, iclass 28, count 0 2006.173.16:59:14.23#ibcon#wrote, iclass 28, count 0 2006.173.16:59:14.23#ibcon#about to read 3, iclass 28, count 0 2006.173.16:59:14.27#ibcon#read 3, iclass 28, count 0 2006.173.16:59:14.27#ibcon#about to read 4, iclass 28, count 0 2006.173.16:59:14.27#ibcon#read 4, iclass 28, count 0 2006.173.16:59:14.27#ibcon#about to read 5, iclass 28, count 0 2006.173.16:59:14.27#ibcon#read 5, iclass 28, count 0 2006.173.16:59:14.27#ibcon#about to read 6, iclass 28, count 0 2006.173.16:59:14.27#ibcon#read 6, iclass 28, count 0 2006.173.16:59:14.27#ibcon#end of sib2, iclass 28, count 0 2006.173.16:59:14.27#ibcon#*after write, iclass 28, count 0 2006.173.16:59:14.27#ibcon#*before return 0, iclass 28, count 0 2006.173.16:59:14.27#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.16:59:14.27#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.16:59:14.27#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.16:59:14.27#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.16:59:14.27$vck44/va=7,4 2006.173.16:59:14.27#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.16:59:14.27#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.16:59:14.27#ibcon#ireg 11 cls_cnt 2 2006.173.16:59:14.27#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.16:59:14.33#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.16:59:14.33#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.16:59:14.33#ibcon#enter wrdev, iclass 30, count 2 2006.173.16:59:14.33#ibcon#first serial, iclass 30, count 2 2006.173.16:59:14.33#ibcon#enter sib2, iclass 30, count 2 2006.173.16:59:14.33#ibcon#flushed, iclass 30, count 2 2006.173.16:59:14.33#ibcon#about to write, iclass 30, count 2 2006.173.16:59:14.33#ibcon#wrote, iclass 30, count 2 2006.173.16:59:14.33#ibcon#about to read 3, iclass 30, count 2 2006.173.16:59:14.35#ibcon#read 3, iclass 30, count 2 2006.173.16:59:14.35#ibcon#about to read 4, iclass 30, count 2 2006.173.16:59:14.35#ibcon#read 4, iclass 30, count 2 2006.173.16:59:14.35#ibcon#about to read 5, iclass 30, count 2 2006.173.16:59:14.35#ibcon#read 5, iclass 30, count 2 2006.173.16:59:14.35#ibcon#about to read 6, iclass 30, count 2 2006.173.16:59:14.35#ibcon#read 6, iclass 30, count 2 2006.173.16:59:14.35#ibcon#end of sib2, iclass 30, count 2 2006.173.16:59:14.35#ibcon#*mode == 0, iclass 30, count 2 2006.173.16:59:14.35#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.16:59:14.35#ibcon#[25=AT07-04\r\n] 2006.173.16:59:14.35#ibcon#*before write, iclass 30, count 2 2006.173.16:59:14.35#ibcon#enter sib2, iclass 30, count 2 2006.173.16:59:14.35#ibcon#flushed, iclass 30, count 2 2006.173.16:59:14.35#ibcon#about to write, iclass 30, count 2 2006.173.16:59:14.35#ibcon#wrote, iclass 30, count 2 2006.173.16:59:14.35#ibcon#about to read 3, iclass 30, count 2 2006.173.16:59:14.38#ibcon#read 3, iclass 30, count 2 2006.173.16:59:14.38#ibcon#about to read 4, iclass 30, count 2 2006.173.16:59:14.38#ibcon#read 4, iclass 30, count 2 2006.173.16:59:14.38#ibcon#about to read 5, iclass 30, count 2 2006.173.16:59:14.38#ibcon#read 5, iclass 30, count 2 2006.173.16:59:14.38#ibcon#about to read 6, iclass 30, count 2 2006.173.16:59:14.38#ibcon#read 6, iclass 30, count 2 2006.173.16:59:14.38#ibcon#end of sib2, iclass 30, count 2 2006.173.16:59:14.38#ibcon#*after write, iclass 30, count 2 2006.173.16:59:14.38#ibcon#*before return 0, iclass 30, count 2 2006.173.16:59:14.38#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.16:59:14.38#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.16:59:14.38#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.16:59:14.38#ibcon#ireg 7 cls_cnt 0 2006.173.16:59:14.38#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.16:59:14.50#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.16:59:14.50#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.16:59:14.50#ibcon#enter wrdev, iclass 30, count 0 2006.173.16:59:14.50#ibcon#first serial, iclass 30, count 0 2006.173.16:59:14.50#ibcon#enter sib2, iclass 30, count 0 2006.173.16:59:14.50#ibcon#flushed, iclass 30, count 0 2006.173.16:59:14.50#ibcon#about to write, iclass 30, count 0 2006.173.16:59:14.50#ibcon#wrote, iclass 30, count 0 2006.173.16:59:14.50#ibcon#about to read 3, iclass 30, count 0 2006.173.16:59:14.52#ibcon#read 3, iclass 30, count 0 2006.173.16:59:14.52#ibcon#about to read 4, iclass 30, count 0 2006.173.16:59:14.52#ibcon#read 4, iclass 30, count 0 2006.173.16:59:14.52#ibcon#about to read 5, iclass 30, count 0 2006.173.16:59:14.52#ibcon#read 5, iclass 30, count 0 2006.173.16:59:14.52#ibcon#about to read 6, iclass 30, count 0 2006.173.16:59:14.52#ibcon#read 6, iclass 30, count 0 2006.173.16:59:14.52#ibcon#end of sib2, iclass 30, count 0 2006.173.16:59:14.52#ibcon#*mode == 0, iclass 30, count 0 2006.173.16:59:14.52#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.16:59:14.52#ibcon#[25=USB\r\n] 2006.173.16:59:14.52#ibcon#*before write, iclass 30, count 0 2006.173.16:59:14.52#ibcon#enter sib2, iclass 30, count 0 2006.173.16:59:14.52#ibcon#flushed, iclass 30, count 0 2006.173.16:59:14.52#ibcon#about to write, iclass 30, count 0 2006.173.16:59:14.52#ibcon#wrote, iclass 30, count 0 2006.173.16:59:14.52#ibcon#about to read 3, iclass 30, count 0 2006.173.16:59:14.55#ibcon#read 3, iclass 30, count 0 2006.173.16:59:14.55#ibcon#about to read 4, iclass 30, count 0 2006.173.16:59:14.55#ibcon#read 4, iclass 30, count 0 2006.173.16:59:14.55#ibcon#about to read 5, iclass 30, count 0 2006.173.16:59:14.55#ibcon#read 5, iclass 30, count 0 2006.173.16:59:14.55#ibcon#about to read 6, iclass 30, count 0 2006.173.16:59:14.55#ibcon#read 6, iclass 30, count 0 2006.173.16:59:14.55#ibcon#end of sib2, iclass 30, count 0 2006.173.16:59:14.55#ibcon#*after write, iclass 30, count 0 2006.173.16:59:14.55#ibcon#*before return 0, iclass 30, count 0 2006.173.16:59:14.55#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.16:59:14.55#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.16:59:14.55#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.16:59:14.55#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.16:59:14.55$vck44/valo=8,884.99 2006.173.16:59:14.55#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.16:59:14.55#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.16:59:14.55#ibcon#ireg 17 cls_cnt 0 2006.173.16:59:14.55#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.16:59:14.55#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.16:59:14.55#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.16:59:14.55#ibcon#enter wrdev, iclass 32, count 0 2006.173.16:59:14.55#ibcon#first serial, iclass 32, count 0 2006.173.16:59:14.55#ibcon#enter sib2, iclass 32, count 0 2006.173.16:59:14.55#ibcon#flushed, iclass 32, count 0 2006.173.16:59:14.55#ibcon#about to write, iclass 32, count 0 2006.173.16:59:14.55#ibcon#wrote, iclass 32, count 0 2006.173.16:59:14.55#ibcon#about to read 3, iclass 32, count 0 2006.173.16:59:14.57#ibcon#read 3, iclass 32, count 0 2006.173.16:59:14.57#ibcon#about to read 4, iclass 32, count 0 2006.173.16:59:14.57#ibcon#read 4, iclass 32, count 0 2006.173.16:59:14.57#ibcon#about to read 5, iclass 32, count 0 2006.173.16:59:14.57#ibcon#read 5, iclass 32, count 0 2006.173.16:59:14.57#ibcon#about to read 6, iclass 32, count 0 2006.173.16:59:14.57#ibcon#read 6, iclass 32, count 0 2006.173.16:59:14.57#ibcon#end of sib2, iclass 32, count 0 2006.173.16:59:14.57#ibcon#*mode == 0, iclass 32, count 0 2006.173.16:59:14.57#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.16:59:14.57#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.16:59:14.57#ibcon#*before write, iclass 32, count 0 2006.173.16:59:14.57#ibcon#enter sib2, iclass 32, count 0 2006.173.16:59:14.57#ibcon#flushed, iclass 32, count 0 2006.173.16:59:14.57#ibcon#about to write, iclass 32, count 0 2006.173.16:59:14.57#ibcon#wrote, iclass 32, count 0 2006.173.16:59:14.57#ibcon#about to read 3, iclass 32, count 0 2006.173.16:59:14.61#ibcon#read 3, iclass 32, count 0 2006.173.16:59:14.61#ibcon#about to read 4, iclass 32, count 0 2006.173.16:59:14.61#ibcon#read 4, iclass 32, count 0 2006.173.16:59:14.61#ibcon#about to read 5, iclass 32, count 0 2006.173.16:59:14.61#ibcon#read 5, iclass 32, count 0 2006.173.16:59:14.61#ibcon#about to read 6, iclass 32, count 0 2006.173.16:59:14.61#ibcon#read 6, iclass 32, count 0 2006.173.16:59:14.61#ibcon#end of sib2, iclass 32, count 0 2006.173.16:59:14.61#ibcon#*after write, iclass 32, count 0 2006.173.16:59:14.61#ibcon#*before return 0, iclass 32, count 0 2006.173.16:59:14.61#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.16:59:14.61#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.16:59:14.61#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.16:59:14.61#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.16:59:14.61$vck44/va=8,4 2006.173.16:59:14.61#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.16:59:14.61#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.16:59:14.61#ibcon#ireg 11 cls_cnt 2 2006.173.16:59:14.61#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.16:59:14.67#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.16:59:14.67#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.16:59:14.67#ibcon#enter wrdev, iclass 34, count 2 2006.173.16:59:14.67#ibcon#first serial, iclass 34, count 2 2006.173.16:59:14.67#ibcon#enter sib2, iclass 34, count 2 2006.173.16:59:14.67#ibcon#flushed, iclass 34, count 2 2006.173.16:59:14.67#ibcon#about to write, iclass 34, count 2 2006.173.16:59:14.67#ibcon#wrote, iclass 34, count 2 2006.173.16:59:14.67#ibcon#about to read 3, iclass 34, count 2 2006.173.16:59:14.69#ibcon#read 3, iclass 34, count 2 2006.173.16:59:14.69#ibcon#about to read 4, iclass 34, count 2 2006.173.16:59:14.69#ibcon#read 4, iclass 34, count 2 2006.173.16:59:14.69#ibcon#about to read 5, iclass 34, count 2 2006.173.16:59:14.69#ibcon#read 5, iclass 34, count 2 2006.173.16:59:14.69#ibcon#about to read 6, iclass 34, count 2 2006.173.16:59:14.69#ibcon#read 6, iclass 34, count 2 2006.173.16:59:14.69#ibcon#end of sib2, iclass 34, count 2 2006.173.16:59:14.69#ibcon#*mode == 0, iclass 34, count 2 2006.173.16:59:14.69#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.16:59:14.69#ibcon#[25=AT08-04\r\n] 2006.173.16:59:14.69#ibcon#*before write, iclass 34, count 2 2006.173.16:59:14.69#ibcon#enter sib2, iclass 34, count 2 2006.173.16:59:14.69#ibcon#flushed, iclass 34, count 2 2006.173.16:59:14.69#ibcon#about to write, iclass 34, count 2 2006.173.16:59:14.69#ibcon#wrote, iclass 34, count 2 2006.173.16:59:14.69#ibcon#about to read 3, iclass 34, count 2 2006.173.16:59:14.72#ibcon#read 3, iclass 34, count 2 2006.173.16:59:14.72#ibcon#about to read 4, iclass 34, count 2 2006.173.16:59:14.72#ibcon#read 4, iclass 34, count 2 2006.173.16:59:14.72#ibcon#about to read 5, iclass 34, count 2 2006.173.16:59:14.72#ibcon#read 5, iclass 34, count 2 2006.173.16:59:14.72#ibcon#about to read 6, iclass 34, count 2 2006.173.16:59:14.72#ibcon#read 6, iclass 34, count 2 2006.173.16:59:14.72#ibcon#end of sib2, iclass 34, count 2 2006.173.16:59:14.72#ibcon#*after write, iclass 34, count 2 2006.173.16:59:14.72#ibcon#*before return 0, iclass 34, count 2 2006.173.16:59:14.72#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.16:59:14.72#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.16:59:14.72#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.16:59:14.72#ibcon#ireg 7 cls_cnt 0 2006.173.16:59:14.72#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.16:59:14.84#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.16:59:14.84#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.16:59:14.84#ibcon#enter wrdev, iclass 34, count 0 2006.173.16:59:14.84#ibcon#first serial, iclass 34, count 0 2006.173.16:59:14.84#ibcon#enter sib2, iclass 34, count 0 2006.173.16:59:14.84#ibcon#flushed, iclass 34, count 0 2006.173.16:59:14.84#ibcon#about to write, iclass 34, count 0 2006.173.16:59:14.84#ibcon#wrote, iclass 34, count 0 2006.173.16:59:14.84#ibcon#about to read 3, iclass 34, count 0 2006.173.16:59:14.86#ibcon#read 3, iclass 34, count 0 2006.173.16:59:14.86#ibcon#about to read 4, iclass 34, count 0 2006.173.16:59:14.86#ibcon#read 4, iclass 34, count 0 2006.173.16:59:14.86#ibcon#about to read 5, iclass 34, count 0 2006.173.16:59:14.86#ibcon#read 5, iclass 34, count 0 2006.173.16:59:14.86#ibcon#about to read 6, iclass 34, count 0 2006.173.16:59:14.86#ibcon#read 6, iclass 34, count 0 2006.173.16:59:14.86#ibcon#end of sib2, iclass 34, count 0 2006.173.16:59:14.86#ibcon#*mode == 0, iclass 34, count 0 2006.173.16:59:14.86#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.16:59:14.86#ibcon#[25=USB\r\n] 2006.173.16:59:14.86#ibcon#*before write, iclass 34, count 0 2006.173.16:59:14.86#ibcon#enter sib2, iclass 34, count 0 2006.173.16:59:14.86#ibcon#flushed, iclass 34, count 0 2006.173.16:59:14.86#ibcon#about to write, iclass 34, count 0 2006.173.16:59:14.86#ibcon#wrote, iclass 34, count 0 2006.173.16:59:14.86#ibcon#about to read 3, iclass 34, count 0 2006.173.16:59:14.89#ibcon#read 3, iclass 34, count 0 2006.173.16:59:14.89#ibcon#about to read 4, iclass 34, count 0 2006.173.16:59:14.89#ibcon#read 4, iclass 34, count 0 2006.173.16:59:14.89#ibcon#about to read 5, iclass 34, count 0 2006.173.16:59:14.89#ibcon#read 5, iclass 34, count 0 2006.173.16:59:14.89#ibcon#about to read 6, iclass 34, count 0 2006.173.16:59:14.89#ibcon#read 6, iclass 34, count 0 2006.173.16:59:14.89#ibcon#end of sib2, iclass 34, count 0 2006.173.16:59:14.89#ibcon#*after write, iclass 34, count 0 2006.173.16:59:14.89#ibcon#*before return 0, iclass 34, count 0 2006.173.16:59:14.89#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.16:59:14.89#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.16:59:14.89#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.16:59:14.89#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.16:59:14.89$vck44/vblo=1,629.99 2006.173.16:59:14.89#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.16:59:14.89#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.16:59:14.89#ibcon#ireg 17 cls_cnt 0 2006.173.16:59:14.89#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.16:59:14.89#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.16:59:14.89#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.16:59:14.89#ibcon#enter wrdev, iclass 36, count 0 2006.173.16:59:14.89#ibcon#first serial, iclass 36, count 0 2006.173.16:59:14.89#ibcon#enter sib2, iclass 36, count 0 2006.173.16:59:14.89#ibcon#flushed, iclass 36, count 0 2006.173.16:59:14.89#ibcon#about to write, iclass 36, count 0 2006.173.16:59:14.89#ibcon#wrote, iclass 36, count 0 2006.173.16:59:14.89#ibcon#about to read 3, iclass 36, count 0 2006.173.16:59:14.91#ibcon#read 3, iclass 36, count 0 2006.173.16:59:14.91#ibcon#about to read 4, iclass 36, count 0 2006.173.16:59:14.91#ibcon#read 4, iclass 36, count 0 2006.173.16:59:14.91#ibcon#about to read 5, iclass 36, count 0 2006.173.16:59:14.91#ibcon#read 5, iclass 36, count 0 2006.173.16:59:14.91#ibcon#about to read 6, iclass 36, count 0 2006.173.16:59:14.91#ibcon#read 6, iclass 36, count 0 2006.173.16:59:14.91#ibcon#end of sib2, iclass 36, count 0 2006.173.16:59:14.91#ibcon#*mode == 0, iclass 36, count 0 2006.173.16:59:14.91#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.16:59:14.91#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.16:59:14.91#ibcon#*before write, iclass 36, count 0 2006.173.16:59:14.91#ibcon#enter sib2, iclass 36, count 0 2006.173.16:59:14.91#ibcon#flushed, iclass 36, count 0 2006.173.16:59:14.91#ibcon#about to write, iclass 36, count 0 2006.173.16:59:14.91#ibcon#wrote, iclass 36, count 0 2006.173.16:59:14.91#ibcon#about to read 3, iclass 36, count 0 2006.173.16:59:14.95#ibcon#read 3, iclass 36, count 0 2006.173.16:59:14.95#ibcon#about to read 4, iclass 36, count 0 2006.173.16:59:14.95#ibcon#read 4, iclass 36, count 0 2006.173.16:59:14.95#ibcon#about to read 5, iclass 36, count 0 2006.173.16:59:14.95#ibcon#read 5, iclass 36, count 0 2006.173.16:59:14.95#ibcon#about to read 6, iclass 36, count 0 2006.173.16:59:14.95#ibcon#read 6, iclass 36, count 0 2006.173.16:59:14.95#ibcon#end of sib2, iclass 36, count 0 2006.173.16:59:14.95#ibcon#*after write, iclass 36, count 0 2006.173.16:59:14.95#ibcon#*before return 0, iclass 36, count 0 2006.173.16:59:14.95#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.16:59:14.95#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.16:59:14.95#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.16:59:14.95#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.16:59:14.95$vck44/vb=1,4 2006.173.16:59:14.95#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.16:59:14.95#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.16:59:14.95#ibcon#ireg 11 cls_cnt 2 2006.173.16:59:14.95#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.16:59:14.95#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.16:59:14.95#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.16:59:14.95#ibcon#enter wrdev, iclass 38, count 2 2006.173.16:59:14.95#ibcon#first serial, iclass 38, count 2 2006.173.16:59:14.95#ibcon#enter sib2, iclass 38, count 2 2006.173.16:59:14.95#ibcon#flushed, iclass 38, count 2 2006.173.16:59:14.95#ibcon#about to write, iclass 38, count 2 2006.173.16:59:14.95#ibcon#wrote, iclass 38, count 2 2006.173.16:59:14.95#ibcon#about to read 3, iclass 38, count 2 2006.173.16:59:14.97#ibcon#read 3, iclass 38, count 2 2006.173.16:59:14.97#ibcon#about to read 4, iclass 38, count 2 2006.173.16:59:14.97#ibcon#read 4, iclass 38, count 2 2006.173.16:59:14.97#ibcon#about to read 5, iclass 38, count 2 2006.173.16:59:14.97#ibcon#read 5, iclass 38, count 2 2006.173.16:59:14.97#ibcon#about to read 6, iclass 38, count 2 2006.173.16:59:14.97#ibcon#read 6, iclass 38, count 2 2006.173.16:59:14.97#ibcon#end of sib2, iclass 38, count 2 2006.173.16:59:14.97#ibcon#*mode == 0, iclass 38, count 2 2006.173.16:59:14.97#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.16:59:14.97#ibcon#[27=AT01-04\r\n] 2006.173.16:59:14.97#ibcon#*before write, iclass 38, count 2 2006.173.16:59:14.97#ibcon#enter sib2, iclass 38, count 2 2006.173.16:59:14.97#ibcon#flushed, iclass 38, count 2 2006.173.16:59:14.97#ibcon#about to write, iclass 38, count 2 2006.173.16:59:14.97#ibcon#wrote, iclass 38, count 2 2006.173.16:59:14.97#ibcon#about to read 3, iclass 38, count 2 2006.173.16:59:15.00#ibcon#read 3, iclass 38, count 2 2006.173.16:59:15.00#ibcon#about to read 4, iclass 38, count 2 2006.173.16:59:15.00#ibcon#read 4, iclass 38, count 2 2006.173.16:59:15.00#ibcon#about to read 5, iclass 38, count 2 2006.173.16:59:15.00#ibcon#read 5, iclass 38, count 2 2006.173.16:59:15.00#ibcon#about to read 6, iclass 38, count 2 2006.173.16:59:15.00#ibcon#read 6, iclass 38, count 2 2006.173.16:59:15.00#ibcon#end of sib2, iclass 38, count 2 2006.173.16:59:15.00#ibcon#*after write, iclass 38, count 2 2006.173.16:59:15.00#ibcon#*before return 0, iclass 38, count 2 2006.173.16:59:15.00#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.16:59:15.00#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.16:59:15.00#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.16:59:15.00#ibcon#ireg 7 cls_cnt 0 2006.173.16:59:15.00#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.16:59:15.12#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.16:59:15.12#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.16:59:15.12#ibcon#enter wrdev, iclass 38, count 0 2006.173.16:59:15.12#ibcon#first serial, iclass 38, count 0 2006.173.16:59:15.12#ibcon#enter sib2, iclass 38, count 0 2006.173.16:59:15.12#ibcon#flushed, iclass 38, count 0 2006.173.16:59:15.12#ibcon#about to write, iclass 38, count 0 2006.173.16:59:15.12#ibcon#wrote, iclass 38, count 0 2006.173.16:59:15.12#ibcon#about to read 3, iclass 38, count 0 2006.173.16:59:15.14#ibcon#read 3, iclass 38, count 0 2006.173.16:59:15.14#ibcon#about to read 4, iclass 38, count 0 2006.173.16:59:15.14#ibcon#read 4, iclass 38, count 0 2006.173.16:59:15.14#ibcon#about to read 5, iclass 38, count 0 2006.173.16:59:15.14#ibcon#read 5, iclass 38, count 0 2006.173.16:59:15.14#ibcon#about to read 6, iclass 38, count 0 2006.173.16:59:15.14#ibcon#read 6, iclass 38, count 0 2006.173.16:59:15.14#ibcon#end of sib2, iclass 38, count 0 2006.173.16:59:15.14#ibcon#*mode == 0, iclass 38, count 0 2006.173.16:59:15.14#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.16:59:15.14#ibcon#[27=USB\r\n] 2006.173.16:59:15.14#ibcon#*before write, iclass 38, count 0 2006.173.16:59:15.14#ibcon#enter sib2, iclass 38, count 0 2006.173.16:59:15.14#ibcon#flushed, iclass 38, count 0 2006.173.16:59:15.14#ibcon#about to write, iclass 38, count 0 2006.173.16:59:15.14#ibcon#wrote, iclass 38, count 0 2006.173.16:59:15.14#ibcon#about to read 3, iclass 38, count 0 2006.173.16:59:15.17#ibcon#read 3, iclass 38, count 0 2006.173.16:59:15.17#ibcon#about to read 4, iclass 38, count 0 2006.173.16:59:15.17#ibcon#read 4, iclass 38, count 0 2006.173.16:59:15.17#ibcon#about to read 5, iclass 38, count 0 2006.173.16:59:15.17#ibcon#read 5, iclass 38, count 0 2006.173.16:59:15.17#ibcon#about to read 6, iclass 38, count 0 2006.173.16:59:15.17#ibcon#read 6, iclass 38, count 0 2006.173.16:59:15.17#ibcon#end of sib2, iclass 38, count 0 2006.173.16:59:15.17#ibcon#*after write, iclass 38, count 0 2006.173.16:59:15.17#ibcon#*before return 0, iclass 38, count 0 2006.173.16:59:15.17#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.16:59:15.17#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.16:59:15.17#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.16:59:15.17#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.16:59:15.17$vck44/vblo=2,634.99 2006.173.16:59:15.17#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.16:59:15.17#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.16:59:15.17#ibcon#ireg 17 cls_cnt 0 2006.173.16:59:15.17#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.16:59:15.17#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.16:59:15.17#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.16:59:15.17#ibcon#enter wrdev, iclass 40, count 0 2006.173.16:59:15.17#ibcon#first serial, iclass 40, count 0 2006.173.16:59:15.17#ibcon#enter sib2, iclass 40, count 0 2006.173.16:59:15.17#ibcon#flushed, iclass 40, count 0 2006.173.16:59:15.17#ibcon#about to write, iclass 40, count 0 2006.173.16:59:15.17#ibcon#wrote, iclass 40, count 0 2006.173.16:59:15.17#ibcon#about to read 3, iclass 40, count 0 2006.173.16:59:15.19#ibcon#read 3, iclass 40, count 0 2006.173.16:59:15.19#ibcon#about to read 4, iclass 40, count 0 2006.173.16:59:15.19#ibcon#read 4, iclass 40, count 0 2006.173.16:59:15.19#ibcon#about to read 5, iclass 40, count 0 2006.173.16:59:15.19#ibcon#read 5, iclass 40, count 0 2006.173.16:59:15.19#ibcon#about to read 6, iclass 40, count 0 2006.173.16:59:15.19#ibcon#read 6, iclass 40, count 0 2006.173.16:59:15.19#ibcon#end of sib2, iclass 40, count 0 2006.173.16:59:15.19#ibcon#*mode == 0, iclass 40, count 0 2006.173.16:59:15.19#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.16:59:15.19#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.16:59:15.19#ibcon#*before write, iclass 40, count 0 2006.173.16:59:15.19#ibcon#enter sib2, iclass 40, count 0 2006.173.16:59:15.19#ibcon#flushed, iclass 40, count 0 2006.173.16:59:15.19#ibcon#about to write, iclass 40, count 0 2006.173.16:59:15.19#ibcon#wrote, iclass 40, count 0 2006.173.16:59:15.19#ibcon#about to read 3, iclass 40, count 0 2006.173.16:59:15.23#ibcon#read 3, iclass 40, count 0 2006.173.16:59:15.23#ibcon#about to read 4, iclass 40, count 0 2006.173.16:59:15.23#ibcon#read 4, iclass 40, count 0 2006.173.16:59:15.23#ibcon#about to read 5, iclass 40, count 0 2006.173.16:59:15.23#ibcon#read 5, iclass 40, count 0 2006.173.16:59:15.23#ibcon#about to read 6, iclass 40, count 0 2006.173.16:59:15.23#ibcon#read 6, iclass 40, count 0 2006.173.16:59:15.23#ibcon#end of sib2, iclass 40, count 0 2006.173.16:59:15.23#ibcon#*after write, iclass 40, count 0 2006.173.16:59:15.23#ibcon#*before return 0, iclass 40, count 0 2006.173.16:59:15.23#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.16:59:15.23#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.16:59:15.23#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.16:59:15.23#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.16:59:15.23$vck44/vb=2,4 2006.173.16:59:15.23#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.16:59:15.23#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.16:59:15.23#ibcon#ireg 11 cls_cnt 2 2006.173.16:59:15.23#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.16:59:15.29#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.16:59:15.29#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.16:59:15.29#ibcon#enter wrdev, iclass 4, count 2 2006.173.16:59:15.29#ibcon#first serial, iclass 4, count 2 2006.173.16:59:15.29#ibcon#enter sib2, iclass 4, count 2 2006.173.16:59:15.29#ibcon#flushed, iclass 4, count 2 2006.173.16:59:15.29#ibcon#about to write, iclass 4, count 2 2006.173.16:59:15.29#ibcon#wrote, iclass 4, count 2 2006.173.16:59:15.29#ibcon#about to read 3, iclass 4, count 2 2006.173.16:59:15.31#ibcon#read 3, iclass 4, count 2 2006.173.16:59:15.31#ibcon#about to read 4, iclass 4, count 2 2006.173.16:59:15.31#ibcon#read 4, iclass 4, count 2 2006.173.16:59:15.31#ibcon#about to read 5, iclass 4, count 2 2006.173.16:59:15.31#ibcon#read 5, iclass 4, count 2 2006.173.16:59:15.31#ibcon#about to read 6, iclass 4, count 2 2006.173.16:59:15.31#ibcon#read 6, iclass 4, count 2 2006.173.16:59:15.31#ibcon#end of sib2, iclass 4, count 2 2006.173.16:59:15.31#ibcon#*mode == 0, iclass 4, count 2 2006.173.16:59:15.31#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.16:59:15.31#ibcon#[27=AT02-04\r\n] 2006.173.16:59:15.31#ibcon#*before write, iclass 4, count 2 2006.173.16:59:15.31#ibcon#enter sib2, iclass 4, count 2 2006.173.16:59:15.31#ibcon#flushed, iclass 4, count 2 2006.173.16:59:15.31#ibcon#about to write, iclass 4, count 2 2006.173.16:59:15.31#ibcon#wrote, iclass 4, count 2 2006.173.16:59:15.31#ibcon#about to read 3, iclass 4, count 2 2006.173.16:59:15.34#ibcon#read 3, iclass 4, count 2 2006.173.16:59:15.34#ibcon#about to read 4, iclass 4, count 2 2006.173.16:59:15.34#ibcon#read 4, iclass 4, count 2 2006.173.16:59:15.34#ibcon#about to read 5, iclass 4, count 2 2006.173.16:59:15.34#ibcon#read 5, iclass 4, count 2 2006.173.16:59:15.34#ibcon#about to read 6, iclass 4, count 2 2006.173.16:59:15.34#ibcon#read 6, iclass 4, count 2 2006.173.16:59:15.34#ibcon#end of sib2, iclass 4, count 2 2006.173.16:59:15.34#ibcon#*after write, iclass 4, count 2 2006.173.16:59:15.34#ibcon#*before return 0, iclass 4, count 2 2006.173.16:59:15.34#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.16:59:15.34#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.16:59:15.34#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.16:59:15.34#ibcon#ireg 7 cls_cnt 0 2006.173.16:59:15.34#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.16:59:15.46#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.16:59:15.46#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.16:59:15.46#ibcon#enter wrdev, iclass 4, count 0 2006.173.16:59:15.46#ibcon#first serial, iclass 4, count 0 2006.173.16:59:15.46#ibcon#enter sib2, iclass 4, count 0 2006.173.16:59:15.46#ibcon#flushed, iclass 4, count 0 2006.173.16:59:15.46#ibcon#about to write, iclass 4, count 0 2006.173.16:59:15.46#ibcon#wrote, iclass 4, count 0 2006.173.16:59:15.46#ibcon#about to read 3, iclass 4, count 0 2006.173.16:59:15.48#ibcon#read 3, iclass 4, count 0 2006.173.16:59:15.48#ibcon#about to read 4, iclass 4, count 0 2006.173.16:59:15.48#ibcon#read 4, iclass 4, count 0 2006.173.16:59:15.48#ibcon#about to read 5, iclass 4, count 0 2006.173.16:59:15.48#ibcon#read 5, iclass 4, count 0 2006.173.16:59:15.48#ibcon#about to read 6, iclass 4, count 0 2006.173.16:59:15.48#ibcon#read 6, iclass 4, count 0 2006.173.16:59:15.48#ibcon#end of sib2, iclass 4, count 0 2006.173.16:59:15.48#ibcon#*mode == 0, iclass 4, count 0 2006.173.16:59:15.48#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.16:59:15.48#ibcon#[27=USB\r\n] 2006.173.16:59:15.48#ibcon#*before write, iclass 4, count 0 2006.173.16:59:15.48#ibcon#enter sib2, iclass 4, count 0 2006.173.16:59:15.48#ibcon#flushed, iclass 4, count 0 2006.173.16:59:15.48#ibcon#about to write, iclass 4, count 0 2006.173.16:59:15.48#ibcon#wrote, iclass 4, count 0 2006.173.16:59:15.48#ibcon#about to read 3, iclass 4, count 0 2006.173.16:59:15.51#ibcon#read 3, iclass 4, count 0 2006.173.16:59:15.51#ibcon#about to read 4, iclass 4, count 0 2006.173.16:59:15.51#ibcon#read 4, iclass 4, count 0 2006.173.16:59:15.51#ibcon#about to read 5, iclass 4, count 0 2006.173.16:59:15.51#ibcon#read 5, iclass 4, count 0 2006.173.16:59:15.51#ibcon#about to read 6, iclass 4, count 0 2006.173.16:59:15.51#ibcon#read 6, iclass 4, count 0 2006.173.16:59:15.51#ibcon#end of sib2, iclass 4, count 0 2006.173.16:59:15.51#ibcon#*after write, iclass 4, count 0 2006.173.16:59:15.51#ibcon#*before return 0, iclass 4, count 0 2006.173.16:59:15.51#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.16:59:15.51#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.16:59:15.51#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.16:59:15.51#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.16:59:15.51$vck44/vblo=3,649.99 2006.173.16:59:15.51#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.16:59:15.51#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.16:59:15.51#ibcon#ireg 17 cls_cnt 0 2006.173.16:59:15.51#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.16:59:15.51#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.16:59:15.51#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.16:59:15.51#ibcon#enter wrdev, iclass 6, count 0 2006.173.16:59:15.51#ibcon#first serial, iclass 6, count 0 2006.173.16:59:15.51#ibcon#enter sib2, iclass 6, count 0 2006.173.16:59:15.51#ibcon#flushed, iclass 6, count 0 2006.173.16:59:15.51#ibcon#about to write, iclass 6, count 0 2006.173.16:59:15.51#ibcon#wrote, iclass 6, count 0 2006.173.16:59:15.51#ibcon#about to read 3, iclass 6, count 0 2006.173.16:59:15.53#ibcon#read 3, iclass 6, count 0 2006.173.16:59:15.53#ibcon#about to read 4, iclass 6, count 0 2006.173.16:59:15.53#ibcon#read 4, iclass 6, count 0 2006.173.16:59:15.53#ibcon#about to read 5, iclass 6, count 0 2006.173.16:59:15.53#ibcon#read 5, iclass 6, count 0 2006.173.16:59:15.53#ibcon#about to read 6, iclass 6, count 0 2006.173.16:59:15.53#ibcon#read 6, iclass 6, count 0 2006.173.16:59:15.53#ibcon#end of sib2, iclass 6, count 0 2006.173.16:59:15.53#ibcon#*mode == 0, iclass 6, count 0 2006.173.16:59:15.53#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.16:59:15.53#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.16:59:15.53#ibcon#*before write, iclass 6, count 0 2006.173.16:59:15.53#ibcon#enter sib2, iclass 6, count 0 2006.173.16:59:15.53#ibcon#flushed, iclass 6, count 0 2006.173.16:59:15.53#ibcon#about to write, iclass 6, count 0 2006.173.16:59:15.53#ibcon#wrote, iclass 6, count 0 2006.173.16:59:15.53#ibcon#about to read 3, iclass 6, count 0 2006.173.16:59:15.57#ibcon#read 3, iclass 6, count 0 2006.173.16:59:15.57#ibcon#about to read 4, iclass 6, count 0 2006.173.16:59:15.57#ibcon#read 4, iclass 6, count 0 2006.173.16:59:15.57#ibcon#about to read 5, iclass 6, count 0 2006.173.16:59:15.57#ibcon#read 5, iclass 6, count 0 2006.173.16:59:15.57#ibcon#about to read 6, iclass 6, count 0 2006.173.16:59:15.57#ibcon#read 6, iclass 6, count 0 2006.173.16:59:15.57#ibcon#end of sib2, iclass 6, count 0 2006.173.16:59:15.57#ibcon#*after write, iclass 6, count 0 2006.173.16:59:15.57#ibcon#*before return 0, iclass 6, count 0 2006.173.16:59:15.57#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.16:59:15.57#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.16:59:15.57#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.16:59:15.57#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.16:59:15.57$vck44/vb=3,4 2006.173.16:59:15.57#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.16:59:15.57#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.16:59:15.57#ibcon#ireg 11 cls_cnt 2 2006.173.16:59:15.57#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.16:59:15.63#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.16:59:15.63#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.16:59:15.63#ibcon#enter wrdev, iclass 10, count 2 2006.173.16:59:15.63#ibcon#first serial, iclass 10, count 2 2006.173.16:59:15.63#ibcon#enter sib2, iclass 10, count 2 2006.173.16:59:15.63#ibcon#flushed, iclass 10, count 2 2006.173.16:59:15.63#ibcon#about to write, iclass 10, count 2 2006.173.16:59:15.63#ibcon#wrote, iclass 10, count 2 2006.173.16:59:15.63#ibcon#about to read 3, iclass 10, count 2 2006.173.16:59:15.65#ibcon#read 3, iclass 10, count 2 2006.173.16:59:15.65#ibcon#about to read 4, iclass 10, count 2 2006.173.16:59:15.65#ibcon#read 4, iclass 10, count 2 2006.173.16:59:15.65#ibcon#about to read 5, iclass 10, count 2 2006.173.16:59:15.65#ibcon#read 5, iclass 10, count 2 2006.173.16:59:15.65#ibcon#about to read 6, iclass 10, count 2 2006.173.16:59:15.65#ibcon#read 6, iclass 10, count 2 2006.173.16:59:15.65#ibcon#end of sib2, iclass 10, count 2 2006.173.16:59:15.65#ibcon#*mode == 0, iclass 10, count 2 2006.173.16:59:15.65#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.16:59:15.65#ibcon#[27=AT03-04\r\n] 2006.173.16:59:15.65#ibcon#*before write, iclass 10, count 2 2006.173.16:59:15.65#ibcon#enter sib2, iclass 10, count 2 2006.173.16:59:15.65#ibcon#flushed, iclass 10, count 2 2006.173.16:59:15.65#ibcon#about to write, iclass 10, count 2 2006.173.16:59:15.65#ibcon#wrote, iclass 10, count 2 2006.173.16:59:15.65#ibcon#about to read 3, iclass 10, count 2 2006.173.16:59:15.68#ibcon#read 3, iclass 10, count 2 2006.173.16:59:15.68#ibcon#about to read 4, iclass 10, count 2 2006.173.16:59:15.68#ibcon#read 4, iclass 10, count 2 2006.173.16:59:15.68#ibcon#about to read 5, iclass 10, count 2 2006.173.16:59:15.68#ibcon#read 5, iclass 10, count 2 2006.173.16:59:15.68#ibcon#about to read 6, iclass 10, count 2 2006.173.16:59:15.68#ibcon#read 6, iclass 10, count 2 2006.173.16:59:15.68#ibcon#end of sib2, iclass 10, count 2 2006.173.16:59:15.68#ibcon#*after write, iclass 10, count 2 2006.173.16:59:15.68#ibcon#*before return 0, iclass 10, count 2 2006.173.16:59:15.68#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.16:59:15.68#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.16:59:15.68#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.16:59:15.68#ibcon#ireg 7 cls_cnt 0 2006.173.16:59:15.68#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.16:59:15.80#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.16:59:15.80#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.16:59:15.80#ibcon#enter wrdev, iclass 10, count 0 2006.173.16:59:15.80#ibcon#first serial, iclass 10, count 0 2006.173.16:59:15.80#ibcon#enter sib2, iclass 10, count 0 2006.173.16:59:15.80#ibcon#flushed, iclass 10, count 0 2006.173.16:59:15.80#ibcon#about to write, iclass 10, count 0 2006.173.16:59:15.80#ibcon#wrote, iclass 10, count 0 2006.173.16:59:15.80#ibcon#about to read 3, iclass 10, count 0 2006.173.16:59:15.82#ibcon#read 3, iclass 10, count 0 2006.173.16:59:15.82#ibcon#about to read 4, iclass 10, count 0 2006.173.16:59:15.82#ibcon#read 4, iclass 10, count 0 2006.173.16:59:15.82#ibcon#about to read 5, iclass 10, count 0 2006.173.16:59:15.82#ibcon#read 5, iclass 10, count 0 2006.173.16:59:15.82#ibcon#about to read 6, iclass 10, count 0 2006.173.16:59:15.82#ibcon#read 6, iclass 10, count 0 2006.173.16:59:15.82#ibcon#end of sib2, iclass 10, count 0 2006.173.16:59:15.82#ibcon#*mode == 0, iclass 10, count 0 2006.173.16:59:15.82#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.16:59:15.82#ibcon#[27=USB\r\n] 2006.173.16:59:15.82#ibcon#*before write, iclass 10, count 0 2006.173.16:59:15.82#ibcon#enter sib2, iclass 10, count 0 2006.173.16:59:15.82#ibcon#flushed, iclass 10, count 0 2006.173.16:59:15.82#ibcon#about to write, iclass 10, count 0 2006.173.16:59:15.82#ibcon#wrote, iclass 10, count 0 2006.173.16:59:15.82#ibcon#about to read 3, iclass 10, count 0 2006.173.16:59:15.85#ibcon#read 3, iclass 10, count 0 2006.173.16:59:15.85#ibcon#about to read 4, iclass 10, count 0 2006.173.16:59:15.85#ibcon#read 4, iclass 10, count 0 2006.173.16:59:15.85#ibcon#about to read 5, iclass 10, count 0 2006.173.16:59:15.85#ibcon#read 5, iclass 10, count 0 2006.173.16:59:15.85#ibcon#about to read 6, iclass 10, count 0 2006.173.16:59:15.85#ibcon#read 6, iclass 10, count 0 2006.173.16:59:15.85#ibcon#end of sib2, iclass 10, count 0 2006.173.16:59:15.85#ibcon#*after write, iclass 10, count 0 2006.173.16:59:15.85#ibcon#*before return 0, iclass 10, count 0 2006.173.16:59:15.85#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.16:59:15.85#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.16:59:15.85#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.16:59:15.85#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.16:59:15.85$vck44/vblo=4,679.99 2006.173.16:59:15.85#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.16:59:15.85#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.16:59:15.85#ibcon#ireg 17 cls_cnt 0 2006.173.16:59:15.85#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.16:59:15.85#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.16:59:15.85#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.16:59:15.85#ibcon#enter wrdev, iclass 12, count 0 2006.173.16:59:15.85#ibcon#first serial, iclass 12, count 0 2006.173.16:59:15.85#ibcon#enter sib2, iclass 12, count 0 2006.173.16:59:15.85#ibcon#flushed, iclass 12, count 0 2006.173.16:59:15.85#ibcon#about to write, iclass 12, count 0 2006.173.16:59:15.85#ibcon#wrote, iclass 12, count 0 2006.173.16:59:15.85#ibcon#about to read 3, iclass 12, count 0 2006.173.16:59:15.87#ibcon#read 3, iclass 12, count 0 2006.173.16:59:15.87#ibcon#about to read 4, iclass 12, count 0 2006.173.16:59:15.87#ibcon#read 4, iclass 12, count 0 2006.173.16:59:15.87#ibcon#about to read 5, iclass 12, count 0 2006.173.16:59:15.87#ibcon#read 5, iclass 12, count 0 2006.173.16:59:15.87#ibcon#about to read 6, iclass 12, count 0 2006.173.16:59:15.87#ibcon#read 6, iclass 12, count 0 2006.173.16:59:15.87#ibcon#end of sib2, iclass 12, count 0 2006.173.16:59:15.87#ibcon#*mode == 0, iclass 12, count 0 2006.173.16:59:15.87#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.16:59:15.87#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.16:59:15.87#ibcon#*before write, iclass 12, count 0 2006.173.16:59:15.87#ibcon#enter sib2, iclass 12, count 0 2006.173.16:59:15.87#ibcon#flushed, iclass 12, count 0 2006.173.16:59:15.87#ibcon#about to write, iclass 12, count 0 2006.173.16:59:15.87#ibcon#wrote, iclass 12, count 0 2006.173.16:59:15.87#ibcon#about to read 3, iclass 12, count 0 2006.173.16:59:15.91#ibcon#read 3, iclass 12, count 0 2006.173.16:59:15.91#ibcon#about to read 4, iclass 12, count 0 2006.173.16:59:15.91#ibcon#read 4, iclass 12, count 0 2006.173.16:59:15.91#ibcon#about to read 5, iclass 12, count 0 2006.173.16:59:15.91#ibcon#read 5, iclass 12, count 0 2006.173.16:59:15.91#ibcon#about to read 6, iclass 12, count 0 2006.173.16:59:15.91#ibcon#read 6, iclass 12, count 0 2006.173.16:59:15.91#ibcon#end of sib2, iclass 12, count 0 2006.173.16:59:15.91#ibcon#*after write, iclass 12, count 0 2006.173.16:59:15.91#ibcon#*before return 0, iclass 12, count 0 2006.173.16:59:15.91#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.16:59:15.91#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.16:59:15.91#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.16:59:15.91#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.16:59:15.91$vck44/vb=4,4 2006.173.16:59:15.91#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.16:59:15.91#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.16:59:15.91#ibcon#ireg 11 cls_cnt 2 2006.173.16:59:15.91#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.16:59:15.97#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.16:59:15.97#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.16:59:15.97#ibcon#enter wrdev, iclass 14, count 2 2006.173.16:59:15.97#ibcon#first serial, iclass 14, count 2 2006.173.16:59:15.97#ibcon#enter sib2, iclass 14, count 2 2006.173.16:59:15.97#ibcon#flushed, iclass 14, count 2 2006.173.16:59:15.97#ibcon#about to write, iclass 14, count 2 2006.173.16:59:15.97#ibcon#wrote, iclass 14, count 2 2006.173.16:59:15.97#ibcon#about to read 3, iclass 14, count 2 2006.173.16:59:15.99#ibcon#read 3, iclass 14, count 2 2006.173.16:59:15.99#ibcon#about to read 4, iclass 14, count 2 2006.173.16:59:15.99#ibcon#read 4, iclass 14, count 2 2006.173.16:59:15.99#ibcon#about to read 5, iclass 14, count 2 2006.173.16:59:15.99#ibcon#read 5, iclass 14, count 2 2006.173.16:59:15.99#ibcon#about to read 6, iclass 14, count 2 2006.173.16:59:15.99#ibcon#read 6, iclass 14, count 2 2006.173.16:59:15.99#ibcon#end of sib2, iclass 14, count 2 2006.173.16:59:15.99#ibcon#*mode == 0, iclass 14, count 2 2006.173.16:59:15.99#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.16:59:15.99#ibcon#[27=AT04-04\r\n] 2006.173.16:59:15.99#ibcon#*before write, iclass 14, count 2 2006.173.16:59:15.99#ibcon#enter sib2, iclass 14, count 2 2006.173.16:59:15.99#ibcon#flushed, iclass 14, count 2 2006.173.16:59:15.99#ibcon#about to write, iclass 14, count 2 2006.173.16:59:15.99#ibcon#wrote, iclass 14, count 2 2006.173.16:59:15.99#ibcon#about to read 3, iclass 14, count 2 2006.173.16:59:16.02#ibcon#read 3, iclass 14, count 2 2006.173.16:59:16.02#ibcon#about to read 4, iclass 14, count 2 2006.173.16:59:16.02#ibcon#read 4, iclass 14, count 2 2006.173.16:59:16.02#ibcon#about to read 5, iclass 14, count 2 2006.173.16:59:16.02#ibcon#read 5, iclass 14, count 2 2006.173.16:59:16.02#ibcon#about to read 6, iclass 14, count 2 2006.173.16:59:16.02#ibcon#read 6, iclass 14, count 2 2006.173.16:59:16.02#ibcon#end of sib2, iclass 14, count 2 2006.173.16:59:16.02#ibcon#*after write, iclass 14, count 2 2006.173.16:59:16.02#ibcon#*before return 0, iclass 14, count 2 2006.173.16:59:16.02#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.16:59:16.02#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.16:59:16.02#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.16:59:16.02#ibcon#ireg 7 cls_cnt 0 2006.173.16:59:16.02#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.16:59:16.14#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.16:59:16.14#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.16:59:16.14#ibcon#enter wrdev, iclass 14, count 0 2006.173.16:59:16.14#ibcon#first serial, iclass 14, count 0 2006.173.16:59:16.14#ibcon#enter sib2, iclass 14, count 0 2006.173.16:59:16.14#ibcon#flushed, iclass 14, count 0 2006.173.16:59:16.14#ibcon#about to write, iclass 14, count 0 2006.173.16:59:16.14#ibcon#wrote, iclass 14, count 0 2006.173.16:59:16.14#ibcon#about to read 3, iclass 14, count 0 2006.173.16:59:16.16#ibcon#read 3, iclass 14, count 0 2006.173.16:59:16.16#ibcon#about to read 4, iclass 14, count 0 2006.173.16:59:16.16#ibcon#read 4, iclass 14, count 0 2006.173.16:59:16.16#ibcon#about to read 5, iclass 14, count 0 2006.173.16:59:16.16#ibcon#read 5, iclass 14, count 0 2006.173.16:59:16.16#ibcon#about to read 6, iclass 14, count 0 2006.173.16:59:16.16#ibcon#read 6, iclass 14, count 0 2006.173.16:59:16.16#ibcon#end of sib2, iclass 14, count 0 2006.173.16:59:16.16#ibcon#*mode == 0, iclass 14, count 0 2006.173.16:59:16.16#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.16:59:16.16#ibcon#[27=USB\r\n] 2006.173.16:59:16.16#ibcon#*before write, iclass 14, count 0 2006.173.16:59:16.16#ibcon#enter sib2, iclass 14, count 0 2006.173.16:59:16.16#ibcon#flushed, iclass 14, count 0 2006.173.16:59:16.16#ibcon#about to write, iclass 14, count 0 2006.173.16:59:16.16#ibcon#wrote, iclass 14, count 0 2006.173.16:59:16.16#ibcon#about to read 3, iclass 14, count 0 2006.173.16:59:16.19#ibcon#read 3, iclass 14, count 0 2006.173.16:59:16.19#ibcon#about to read 4, iclass 14, count 0 2006.173.16:59:16.19#ibcon#read 4, iclass 14, count 0 2006.173.16:59:16.19#ibcon#about to read 5, iclass 14, count 0 2006.173.16:59:16.19#ibcon#read 5, iclass 14, count 0 2006.173.16:59:16.19#ibcon#about to read 6, iclass 14, count 0 2006.173.16:59:16.19#ibcon#read 6, iclass 14, count 0 2006.173.16:59:16.19#ibcon#end of sib2, iclass 14, count 0 2006.173.16:59:16.19#ibcon#*after write, iclass 14, count 0 2006.173.16:59:16.19#ibcon#*before return 0, iclass 14, count 0 2006.173.16:59:16.19#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.16:59:16.19#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.16:59:16.19#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.16:59:16.19#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.16:59:16.19$vck44/vblo=5,709.99 2006.173.16:59:16.19#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.16:59:16.19#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.16:59:16.19#ibcon#ireg 17 cls_cnt 0 2006.173.16:59:16.19#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.16:59:16.19#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.16:59:16.19#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.16:59:16.19#ibcon#enter wrdev, iclass 16, count 0 2006.173.16:59:16.19#ibcon#first serial, iclass 16, count 0 2006.173.16:59:16.19#ibcon#enter sib2, iclass 16, count 0 2006.173.16:59:16.19#ibcon#flushed, iclass 16, count 0 2006.173.16:59:16.19#ibcon#about to write, iclass 16, count 0 2006.173.16:59:16.19#ibcon#wrote, iclass 16, count 0 2006.173.16:59:16.19#ibcon#about to read 3, iclass 16, count 0 2006.173.16:59:16.21#ibcon#read 3, iclass 16, count 0 2006.173.16:59:16.21#ibcon#about to read 4, iclass 16, count 0 2006.173.16:59:16.21#ibcon#read 4, iclass 16, count 0 2006.173.16:59:16.21#ibcon#about to read 5, iclass 16, count 0 2006.173.16:59:16.21#ibcon#read 5, iclass 16, count 0 2006.173.16:59:16.21#ibcon#about to read 6, iclass 16, count 0 2006.173.16:59:16.21#ibcon#read 6, iclass 16, count 0 2006.173.16:59:16.21#ibcon#end of sib2, iclass 16, count 0 2006.173.16:59:16.21#ibcon#*mode == 0, iclass 16, count 0 2006.173.16:59:16.21#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.16:59:16.21#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.16:59:16.21#ibcon#*before write, iclass 16, count 0 2006.173.16:59:16.21#ibcon#enter sib2, iclass 16, count 0 2006.173.16:59:16.21#ibcon#flushed, iclass 16, count 0 2006.173.16:59:16.21#ibcon#about to write, iclass 16, count 0 2006.173.16:59:16.21#ibcon#wrote, iclass 16, count 0 2006.173.16:59:16.21#ibcon#about to read 3, iclass 16, count 0 2006.173.16:59:16.25#ibcon#read 3, iclass 16, count 0 2006.173.16:59:16.25#ibcon#about to read 4, iclass 16, count 0 2006.173.16:59:16.25#ibcon#read 4, iclass 16, count 0 2006.173.16:59:16.25#ibcon#about to read 5, iclass 16, count 0 2006.173.16:59:16.25#ibcon#read 5, iclass 16, count 0 2006.173.16:59:16.25#ibcon#about to read 6, iclass 16, count 0 2006.173.16:59:16.25#ibcon#read 6, iclass 16, count 0 2006.173.16:59:16.25#ibcon#end of sib2, iclass 16, count 0 2006.173.16:59:16.25#ibcon#*after write, iclass 16, count 0 2006.173.16:59:16.25#ibcon#*before return 0, iclass 16, count 0 2006.173.16:59:16.25#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.16:59:16.25#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.16:59:16.25#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.16:59:16.25#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.16:59:16.25$vck44/vb=5,4 2006.173.16:59:16.25#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.16:59:16.25#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.16:59:16.25#ibcon#ireg 11 cls_cnt 2 2006.173.16:59:16.25#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.16:59:16.31#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.16:59:16.31#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.16:59:16.31#ibcon#enter wrdev, iclass 18, count 2 2006.173.16:59:16.31#ibcon#first serial, iclass 18, count 2 2006.173.16:59:16.31#ibcon#enter sib2, iclass 18, count 2 2006.173.16:59:16.31#ibcon#flushed, iclass 18, count 2 2006.173.16:59:16.31#ibcon#about to write, iclass 18, count 2 2006.173.16:59:16.31#ibcon#wrote, iclass 18, count 2 2006.173.16:59:16.31#ibcon#about to read 3, iclass 18, count 2 2006.173.16:59:16.33#ibcon#read 3, iclass 18, count 2 2006.173.16:59:16.33#ibcon#about to read 4, iclass 18, count 2 2006.173.16:59:16.33#ibcon#read 4, iclass 18, count 2 2006.173.16:59:16.33#ibcon#about to read 5, iclass 18, count 2 2006.173.16:59:16.33#ibcon#read 5, iclass 18, count 2 2006.173.16:59:16.33#ibcon#about to read 6, iclass 18, count 2 2006.173.16:59:16.33#ibcon#read 6, iclass 18, count 2 2006.173.16:59:16.33#ibcon#end of sib2, iclass 18, count 2 2006.173.16:59:16.33#ibcon#*mode == 0, iclass 18, count 2 2006.173.16:59:16.33#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.16:59:16.33#ibcon#[27=AT05-04\r\n] 2006.173.16:59:16.33#ibcon#*before write, iclass 18, count 2 2006.173.16:59:16.33#ibcon#enter sib2, iclass 18, count 2 2006.173.16:59:16.33#ibcon#flushed, iclass 18, count 2 2006.173.16:59:16.33#ibcon#about to write, iclass 18, count 2 2006.173.16:59:16.33#ibcon#wrote, iclass 18, count 2 2006.173.16:59:16.33#ibcon#about to read 3, iclass 18, count 2 2006.173.16:59:16.36#ibcon#read 3, iclass 18, count 2 2006.173.16:59:16.36#ibcon#about to read 4, iclass 18, count 2 2006.173.16:59:16.36#ibcon#read 4, iclass 18, count 2 2006.173.16:59:16.36#ibcon#about to read 5, iclass 18, count 2 2006.173.16:59:16.36#ibcon#read 5, iclass 18, count 2 2006.173.16:59:16.36#ibcon#about to read 6, iclass 18, count 2 2006.173.16:59:16.36#ibcon#read 6, iclass 18, count 2 2006.173.16:59:16.36#ibcon#end of sib2, iclass 18, count 2 2006.173.16:59:16.36#ibcon#*after write, iclass 18, count 2 2006.173.16:59:16.36#ibcon#*before return 0, iclass 18, count 2 2006.173.16:59:16.36#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.16:59:16.36#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.16:59:16.36#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.16:59:16.36#ibcon#ireg 7 cls_cnt 0 2006.173.16:59:16.36#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.16:59:16.48#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.16:59:16.48#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.16:59:16.48#ibcon#enter wrdev, iclass 18, count 0 2006.173.16:59:16.48#ibcon#first serial, iclass 18, count 0 2006.173.16:59:16.48#ibcon#enter sib2, iclass 18, count 0 2006.173.16:59:16.48#ibcon#flushed, iclass 18, count 0 2006.173.16:59:16.48#ibcon#about to write, iclass 18, count 0 2006.173.16:59:16.48#ibcon#wrote, iclass 18, count 0 2006.173.16:59:16.48#ibcon#about to read 3, iclass 18, count 0 2006.173.16:59:16.50#ibcon#read 3, iclass 18, count 0 2006.173.16:59:16.50#ibcon#about to read 4, iclass 18, count 0 2006.173.16:59:16.50#ibcon#read 4, iclass 18, count 0 2006.173.16:59:16.50#ibcon#about to read 5, iclass 18, count 0 2006.173.16:59:16.50#ibcon#read 5, iclass 18, count 0 2006.173.16:59:16.50#ibcon#about to read 6, iclass 18, count 0 2006.173.16:59:16.50#ibcon#read 6, iclass 18, count 0 2006.173.16:59:16.50#ibcon#end of sib2, iclass 18, count 0 2006.173.16:59:16.50#ibcon#*mode == 0, iclass 18, count 0 2006.173.16:59:16.50#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.16:59:16.50#ibcon#[27=USB\r\n] 2006.173.16:59:16.50#ibcon#*before write, iclass 18, count 0 2006.173.16:59:16.50#ibcon#enter sib2, iclass 18, count 0 2006.173.16:59:16.50#ibcon#flushed, iclass 18, count 0 2006.173.16:59:16.50#ibcon#about to write, iclass 18, count 0 2006.173.16:59:16.50#ibcon#wrote, iclass 18, count 0 2006.173.16:59:16.50#ibcon#about to read 3, iclass 18, count 0 2006.173.16:59:16.53#ibcon#read 3, iclass 18, count 0 2006.173.16:59:16.53#ibcon#about to read 4, iclass 18, count 0 2006.173.16:59:16.53#ibcon#read 4, iclass 18, count 0 2006.173.16:59:16.53#ibcon#about to read 5, iclass 18, count 0 2006.173.16:59:16.53#ibcon#read 5, iclass 18, count 0 2006.173.16:59:16.53#ibcon#about to read 6, iclass 18, count 0 2006.173.16:59:16.53#ibcon#read 6, iclass 18, count 0 2006.173.16:59:16.53#ibcon#end of sib2, iclass 18, count 0 2006.173.16:59:16.53#ibcon#*after write, iclass 18, count 0 2006.173.16:59:16.53#ibcon#*before return 0, iclass 18, count 0 2006.173.16:59:16.53#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.16:59:16.53#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.16:59:16.53#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.16:59:16.53#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.16:59:16.53$vck44/vblo=6,719.99 2006.173.16:59:16.53#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.16:59:16.53#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.16:59:16.53#ibcon#ireg 17 cls_cnt 0 2006.173.16:59:16.53#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.16:59:16.53#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.16:59:16.53#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.16:59:16.53#ibcon#enter wrdev, iclass 20, count 0 2006.173.16:59:16.53#ibcon#first serial, iclass 20, count 0 2006.173.16:59:16.53#ibcon#enter sib2, iclass 20, count 0 2006.173.16:59:16.53#ibcon#flushed, iclass 20, count 0 2006.173.16:59:16.53#ibcon#about to write, iclass 20, count 0 2006.173.16:59:16.53#ibcon#wrote, iclass 20, count 0 2006.173.16:59:16.53#ibcon#about to read 3, iclass 20, count 0 2006.173.16:59:16.55#ibcon#read 3, iclass 20, count 0 2006.173.16:59:16.55#ibcon#about to read 4, iclass 20, count 0 2006.173.16:59:16.55#ibcon#read 4, iclass 20, count 0 2006.173.16:59:16.55#ibcon#about to read 5, iclass 20, count 0 2006.173.16:59:16.55#ibcon#read 5, iclass 20, count 0 2006.173.16:59:16.55#ibcon#about to read 6, iclass 20, count 0 2006.173.16:59:16.55#ibcon#read 6, iclass 20, count 0 2006.173.16:59:16.55#ibcon#end of sib2, iclass 20, count 0 2006.173.16:59:16.55#ibcon#*mode == 0, iclass 20, count 0 2006.173.16:59:16.55#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.16:59:16.55#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.16:59:16.55#ibcon#*before write, iclass 20, count 0 2006.173.16:59:16.55#ibcon#enter sib2, iclass 20, count 0 2006.173.16:59:16.55#ibcon#flushed, iclass 20, count 0 2006.173.16:59:16.55#ibcon#about to write, iclass 20, count 0 2006.173.16:59:16.55#ibcon#wrote, iclass 20, count 0 2006.173.16:59:16.55#ibcon#about to read 3, iclass 20, count 0 2006.173.16:59:16.59#ibcon#read 3, iclass 20, count 0 2006.173.16:59:16.59#ibcon#about to read 4, iclass 20, count 0 2006.173.16:59:16.59#ibcon#read 4, iclass 20, count 0 2006.173.16:59:16.59#ibcon#about to read 5, iclass 20, count 0 2006.173.16:59:16.59#ibcon#read 5, iclass 20, count 0 2006.173.16:59:16.59#ibcon#about to read 6, iclass 20, count 0 2006.173.16:59:16.59#ibcon#read 6, iclass 20, count 0 2006.173.16:59:16.59#ibcon#end of sib2, iclass 20, count 0 2006.173.16:59:16.59#ibcon#*after write, iclass 20, count 0 2006.173.16:59:16.59#ibcon#*before return 0, iclass 20, count 0 2006.173.16:59:16.59#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.16:59:16.59#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.16:59:16.59#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.16:59:16.59#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.16:59:16.59$vck44/vb=6,4 2006.173.16:59:16.59#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.16:59:16.59#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.16:59:16.59#ibcon#ireg 11 cls_cnt 2 2006.173.16:59:16.59#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.16:59:16.65#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.16:59:16.65#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.16:59:16.65#ibcon#enter wrdev, iclass 22, count 2 2006.173.16:59:16.65#ibcon#first serial, iclass 22, count 2 2006.173.16:59:16.65#ibcon#enter sib2, iclass 22, count 2 2006.173.16:59:16.65#ibcon#flushed, iclass 22, count 2 2006.173.16:59:16.65#ibcon#about to write, iclass 22, count 2 2006.173.16:59:16.65#ibcon#wrote, iclass 22, count 2 2006.173.16:59:16.65#ibcon#about to read 3, iclass 22, count 2 2006.173.16:59:16.67#ibcon#read 3, iclass 22, count 2 2006.173.16:59:16.67#ibcon#about to read 4, iclass 22, count 2 2006.173.16:59:16.67#ibcon#read 4, iclass 22, count 2 2006.173.16:59:16.67#ibcon#about to read 5, iclass 22, count 2 2006.173.16:59:16.67#ibcon#read 5, iclass 22, count 2 2006.173.16:59:16.67#ibcon#about to read 6, iclass 22, count 2 2006.173.16:59:16.67#ibcon#read 6, iclass 22, count 2 2006.173.16:59:16.67#ibcon#end of sib2, iclass 22, count 2 2006.173.16:59:16.67#ibcon#*mode == 0, iclass 22, count 2 2006.173.16:59:16.67#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.16:59:16.67#ibcon#[27=AT06-04\r\n] 2006.173.16:59:16.67#ibcon#*before write, iclass 22, count 2 2006.173.16:59:16.67#ibcon#enter sib2, iclass 22, count 2 2006.173.16:59:16.67#ibcon#flushed, iclass 22, count 2 2006.173.16:59:16.67#ibcon#about to write, iclass 22, count 2 2006.173.16:59:16.67#ibcon#wrote, iclass 22, count 2 2006.173.16:59:16.67#ibcon#about to read 3, iclass 22, count 2 2006.173.16:59:16.70#ibcon#read 3, iclass 22, count 2 2006.173.16:59:16.70#ibcon#about to read 4, iclass 22, count 2 2006.173.16:59:16.70#ibcon#read 4, iclass 22, count 2 2006.173.16:59:16.70#ibcon#about to read 5, iclass 22, count 2 2006.173.16:59:16.70#ibcon#read 5, iclass 22, count 2 2006.173.16:59:16.70#ibcon#about to read 6, iclass 22, count 2 2006.173.16:59:16.70#ibcon#read 6, iclass 22, count 2 2006.173.16:59:16.70#ibcon#end of sib2, iclass 22, count 2 2006.173.16:59:16.70#ibcon#*after write, iclass 22, count 2 2006.173.16:59:16.70#ibcon#*before return 0, iclass 22, count 2 2006.173.16:59:16.70#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.16:59:16.70#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.16:59:16.70#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.16:59:16.70#ibcon#ireg 7 cls_cnt 0 2006.173.16:59:16.70#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.16:59:16.82#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.16:59:16.82#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.16:59:16.82#ibcon#enter wrdev, iclass 22, count 0 2006.173.16:59:16.82#ibcon#first serial, iclass 22, count 0 2006.173.16:59:16.82#ibcon#enter sib2, iclass 22, count 0 2006.173.16:59:16.82#ibcon#flushed, iclass 22, count 0 2006.173.16:59:16.82#ibcon#about to write, iclass 22, count 0 2006.173.16:59:16.82#ibcon#wrote, iclass 22, count 0 2006.173.16:59:16.82#ibcon#about to read 3, iclass 22, count 0 2006.173.16:59:16.84#ibcon#read 3, iclass 22, count 0 2006.173.16:59:16.84#ibcon#about to read 4, iclass 22, count 0 2006.173.16:59:16.84#ibcon#read 4, iclass 22, count 0 2006.173.16:59:16.84#ibcon#about to read 5, iclass 22, count 0 2006.173.16:59:16.84#ibcon#read 5, iclass 22, count 0 2006.173.16:59:16.84#ibcon#about to read 6, iclass 22, count 0 2006.173.16:59:16.84#ibcon#read 6, iclass 22, count 0 2006.173.16:59:16.84#ibcon#end of sib2, iclass 22, count 0 2006.173.16:59:16.84#ibcon#*mode == 0, iclass 22, count 0 2006.173.16:59:16.84#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.16:59:16.84#ibcon#[27=USB\r\n] 2006.173.16:59:16.84#ibcon#*before write, iclass 22, count 0 2006.173.16:59:16.84#ibcon#enter sib2, iclass 22, count 0 2006.173.16:59:16.84#ibcon#flushed, iclass 22, count 0 2006.173.16:59:16.84#ibcon#about to write, iclass 22, count 0 2006.173.16:59:16.84#ibcon#wrote, iclass 22, count 0 2006.173.16:59:16.84#ibcon#about to read 3, iclass 22, count 0 2006.173.16:59:16.87#ibcon#read 3, iclass 22, count 0 2006.173.16:59:16.87#ibcon#about to read 4, iclass 22, count 0 2006.173.16:59:16.87#ibcon#read 4, iclass 22, count 0 2006.173.16:59:16.87#ibcon#about to read 5, iclass 22, count 0 2006.173.16:59:16.87#ibcon#read 5, iclass 22, count 0 2006.173.16:59:16.87#ibcon#about to read 6, iclass 22, count 0 2006.173.16:59:16.87#ibcon#read 6, iclass 22, count 0 2006.173.16:59:16.87#ibcon#end of sib2, iclass 22, count 0 2006.173.16:59:16.87#ibcon#*after write, iclass 22, count 0 2006.173.16:59:16.87#ibcon#*before return 0, iclass 22, count 0 2006.173.16:59:16.87#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.16:59:16.87#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.16:59:16.87#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.16:59:16.87#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.16:59:16.87$vck44/vblo=7,734.99 2006.173.16:59:16.87#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.16:59:16.87#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.16:59:16.87#ibcon#ireg 17 cls_cnt 0 2006.173.16:59:16.87#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.16:59:16.87#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.16:59:16.87#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.16:59:16.87#ibcon#enter wrdev, iclass 24, count 0 2006.173.16:59:16.87#ibcon#first serial, iclass 24, count 0 2006.173.16:59:16.87#ibcon#enter sib2, iclass 24, count 0 2006.173.16:59:16.87#ibcon#flushed, iclass 24, count 0 2006.173.16:59:16.87#ibcon#about to write, iclass 24, count 0 2006.173.16:59:16.87#ibcon#wrote, iclass 24, count 0 2006.173.16:59:16.87#ibcon#about to read 3, iclass 24, count 0 2006.173.16:59:16.89#ibcon#read 3, iclass 24, count 0 2006.173.16:59:16.89#ibcon#about to read 4, iclass 24, count 0 2006.173.16:59:16.89#ibcon#read 4, iclass 24, count 0 2006.173.16:59:16.89#ibcon#about to read 5, iclass 24, count 0 2006.173.16:59:16.89#ibcon#read 5, iclass 24, count 0 2006.173.16:59:16.89#ibcon#about to read 6, iclass 24, count 0 2006.173.16:59:16.89#ibcon#read 6, iclass 24, count 0 2006.173.16:59:16.89#ibcon#end of sib2, iclass 24, count 0 2006.173.16:59:16.89#ibcon#*mode == 0, iclass 24, count 0 2006.173.16:59:16.89#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.16:59:16.89#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.16:59:16.89#ibcon#*before write, iclass 24, count 0 2006.173.16:59:16.89#ibcon#enter sib2, iclass 24, count 0 2006.173.16:59:16.89#ibcon#flushed, iclass 24, count 0 2006.173.16:59:16.89#ibcon#about to write, iclass 24, count 0 2006.173.16:59:16.89#ibcon#wrote, iclass 24, count 0 2006.173.16:59:16.89#ibcon#about to read 3, iclass 24, count 0 2006.173.16:59:16.93#ibcon#read 3, iclass 24, count 0 2006.173.16:59:16.93#ibcon#about to read 4, iclass 24, count 0 2006.173.16:59:16.93#ibcon#read 4, iclass 24, count 0 2006.173.16:59:16.93#ibcon#about to read 5, iclass 24, count 0 2006.173.16:59:16.93#ibcon#read 5, iclass 24, count 0 2006.173.16:59:16.93#ibcon#about to read 6, iclass 24, count 0 2006.173.16:59:16.93#ibcon#read 6, iclass 24, count 0 2006.173.16:59:16.93#ibcon#end of sib2, iclass 24, count 0 2006.173.16:59:16.93#ibcon#*after write, iclass 24, count 0 2006.173.16:59:16.93#ibcon#*before return 0, iclass 24, count 0 2006.173.16:59:16.93#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.16:59:16.93#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.16:59:16.93#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.16:59:16.93#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.16:59:16.93$vck44/vb=7,4 2006.173.16:59:16.93#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.16:59:16.93#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.16:59:16.93#ibcon#ireg 11 cls_cnt 2 2006.173.16:59:16.93#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.16:59:16.99#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.16:59:16.99#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.16:59:16.99#ibcon#enter wrdev, iclass 26, count 2 2006.173.16:59:16.99#ibcon#first serial, iclass 26, count 2 2006.173.16:59:16.99#ibcon#enter sib2, iclass 26, count 2 2006.173.16:59:16.99#ibcon#flushed, iclass 26, count 2 2006.173.16:59:16.99#ibcon#about to write, iclass 26, count 2 2006.173.16:59:16.99#ibcon#wrote, iclass 26, count 2 2006.173.16:59:16.99#ibcon#about to read 3, iclass 26, count 2 2006.173.16:59:17.01#ibcon#read 3, iclass 26, count 2 2006.173.16:59:17.01#ibcon#about to read 4, iclass 26, count 2 2006.173.16:59:17.01#ibcon#read 4, iclass 26, count 2 2006.173.16:59:17.01#ibcon#about to read 5, iclass 26, count 2 2006.173.16:59:17.01#ibcon#read 5, iclass 26, count 2 2006.173.16:59:17.01#ibcon#about to read 6, iclass 26, count 2 2006.173.16:59:17.01#ibcon#read 6, iclass 26, count 2 2006.173.16:59:17.01#ibcon#end of sib2, iclass 26, count 2 2006.173.16:59:17.01#ibcon#*mode == 0, iclass 26, count 2 2006.173.16:59:17.01#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.16:59:17.01#ibcon#[27=AT07-04\r\n] 2006.173.16:59:17.01#ibcon#*before write, iclass 26, count 2 2006.173.16:59:17.01#ibcon#enter sib2, iclass 26, count 2 2006.173.16:59:17.01#ibcon#flushed, iclass 26, count 2 2006.173.16:59:17.01#ibcon#about to write, iclass 26, count 2 2006.173.16:59:17.01#ibcon#wrote, iclass 26, count 2 2006.173.16:59:17.01#ibcon#about to read 3, iclass 26, count 2 2006.173.16:59:17.04#ibcon#read 3, iclass 26, count 2 2006.173.16:59:17.04#ibcon#about to read 4, iclass 26, count 2 2006.173.16:59:17.04#ibcon#read 4, iclass 26, count 2 2006.173.16:59:17.04#ibcon#about to read 5, iclass 26, count 2 2006.173.16:59:17.04#ibcon#read 5, iclass 26, count 2 2006.173.16:59:17.04#ibcon#about to read 6, iclass 26, count 2 2006.173.16:59:17.04#ibcon#read 6, iclass 26, count 2 2006.173.16:59:17.04#ibcon#end of sib2, iclass 26, count 2 2006.173.16:59:17.04#ibcon#*after write, iclass 26, count 2 2006.173.16:59:17.04#ibcon#*before return 0, iclass 26, count 2 2006.173.16:59:17.04#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.16:59:17.04#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.16:59:17.04#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.16:59:17.04#ibcon#ireg 7 cls_cnt 0 2006.173.16:59:17.04#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.16:59:17.16#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.16:59:17.16#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.16:59:17.16#ibcon#enter wrdev, iclass 26, count 0 2006.173.16:59:17.16#ibcon#first serial, iclass 26, count 0 2006.173.16:59:17.16#ibcon#enter sib2, iclass 26, count 0 2006.173.16:59:17.16#ibcon#flushed, iclass 26, count 0 2006.173.16:59:17.16#ibcon#about to write, iclass 26, count 0 2006.173.16:59:17.16#ibcon#wrote, iclass 26, count 0 2006.173.16:59:17.16#ibcon#about to read 3, iclass 26, count 0 2006.173.16:59:17.18#ibcon#read 3, iclass 26, count 0 2006.173.16:59:17.18#ibcon#about to read 4, iclass 26, count 0 2006.173.16:59:17.18#ibcon#read 4, iclass 26, count 0 2006.173.16:59:17.18#ibcon#about to read 5, iclass 26, count 0 2006.173.16:59:17.18#ibcon#read 5, iclass 26, count 0 2006.173.16:59:17.18#ibcon#about to read 6, iclass 26, count 0 2006.173.16:59:17.18#ibcon#read 6, iclass 26, count 0 2006.173.16:59:17.18#ibcon#end of sib2, iclass 26, count 0 2006.173.16:59:17.18#ibcon#*mode == 0, iclass 26, count 0 2006.173.16:59:17.18#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.16:59:17.18#ibcon#[27=USB\r\n] 2006.173.16:59:17.18#ibcon#*before write, iclass 26, count 0 2006.173.16:59:17.18#ibcon#enter sib2, iclass 26, count 0 2006.173.16:59:17.18#ibcon#flushed, iclass 26, count 0 2006.173.16:59:17.18#ibcon#about to write, iclass 26, count 0 2006.173.16:59:17.18#ibcon#wrote, iclass 26, count 0 2006.173.16:59:17.18#ibcon#about to read 3, iclass 26, count 0 2006.173.16:59:17.21#ibcon#read 3, iclass 26, count 0 2006.173.16:59:17.21#ibcon#about to read 4, iclass 26, count 0 2006.173.16:59:17.21#ibcon#read 4, iclass 26, count 0 2006.173.16:59:17.21#ibcon#about to read 5, iclass 26, count 0 2006.173.16:59:17.21#ibcon#read 5, iclass 26, count 0 2006.173.16:59:17.21#ibcon#about to read 6, iclass 26, count 0 2006.173.16:59:17.21#ibcon#read 6, iclass 26, count 0 2006.173.16:59:17.21#ibcon#end of sib2, iclass 26, count 0 2006.173.16:59:17.21#ibcon#*after write, iclass 26, count 0 2006.173.16:59:17.21#ibcon#*before return 0, iclass 26, count 0 2006.173.16:59:17.21#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.16:59:17.21#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.16:59:17.21#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.16:59:17.21#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.16:59:17.21$vck44/vblo=8,744.99 2006.173.16:59:17.21#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.16:59:17.21#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.16:59:17.21#ibcon#ireg 17 cls_cnt 0 2006.173.16:59:17.21#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.16:59:17.21#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.16:59:17.21#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.16:59:17.21#ibcon#enter wrdev, iclass 28, count 0 2006.173.16:59:17.21#ibcon#first serial, iclass 28, count 0 2006.173.16:59:17.21#ibcon#enter sib2, iclass 28, count 0 2006.173.16:59:17.21#ibcon#flushed, iclass 28, count 0 2006.173.16:59:17.21#ibcon#about to write, iclass 28, count 0 2006.173.16:59:17.21#ibcon#wrote, iclass 28, count 0 2006.173.16:59:17.21#ibcon#about to read 3, iclass 28, count 0 2006.173.16:59:17.23#ibcon#read 3, iclass 28, count 0 2006.173.16:59:17.23#ibcon#about to read 4, iclass 28, count 0 2006.173.16:59:17.23#ibcon#read 4, iclass 28, count 0 2006.173.16:59:17.23#ibcon#about to read 5, iclass 28, count 0 2006.173.16:59:17.23#ibcon#read 5, iclass 28, count 0 2006.173.16:59:17.23#ibcon#about to read 6, iclass 28, count 0 2006.173.16:59:17.23#ibcon#read 6, iclass 28, count 0 2006.173.16:59:17.23#ibcon#end of sib2, iclass 28, count 0 2006.173.16:59:17.23#ibcon#*mode == 0, iclass 28, count 0 2006.173.16:59:17.23#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.16:59:17.23#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.16:59:17.23#ibcon#*before write, iclass 28, count 0 2006.173.16:59:17.23#ibcon#enter sib2, iclass 28, count 0 2006.173.16:59:17.23#ibcon#flushed, iclass 28, count 0 2006.173.16:59:17.23#ibcon#about to write, iclass 28, count 0 2006.173.16:59:17.23#ibcon#wrote, iclass 28, count 0 2006.173.16:59:17.23#ibcon#about to read 3, iclass 28, count 0 2006.173.16:59:17.27#ibcon#read 3, iclass 28, count 0 2006.173.16:59:17.27#ibcon#about to read 4, iclass 28, count 0 2006.173.16:59:17.27#ibcon#read 4, iclass 28, count 0 2006.173.16:59:17.27#ibcon#about to read 5, iclass 28, count 0 2006.173.16:59:17.27#ibcon#read 5, iclass 28, count 0 2006.173.16:59:17.27#ibcon#about to read 6, iclass 28, count 0 2006.173.16:59:17.27#ibcon#read 6, iclass 28, count 0 2006.173.16:59:17.27#ibcon#end of sib2, iclass 28, count 0 2006.173.16:59:17.27#ibcon#*after write, iclass 28, count 0 2006.173.16:59:17.27#ibcon#*before return 0, iclass 28, count 0 2006.173.16:59:17.27#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.16:59:17.27#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.16:59:17.27#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.16:59:17.27#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.16:59:17.27$vck44/vb=8,4 2006.173.16:59:17.27#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.16:59:17.27#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.16:59:17.27#ibcon#ireg 11 cls_cnt 2 2006.173.16:59:17.27#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.16:59:17.33#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.16:59:17.33#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.16:59:17.33#ibcon#enter wrdev, iclass 30, count 2 2006.173.16:59:17.33#ibcon#first serial, iclass 30, count 2 2006.173.16:59:17.33#ibcon#enter sib2, iclass 30, count 2 2006.173.16:59:17.33#ibcon#flushed, iclass 30, count 2 2006.173.16:59:17.33#ibcon#about to write, iclass 30, count 2 2006.173.16:59:17.33#ibcon#wrote, iclass 30, count 2 2006.173.16:59:17.33#ibcon#about to read 3, iclass 30, count 2 2006.173.16:59:17.35#ibcon#read 3, iclass 30, count 2 2006.173.16:59:17.35#ibcon#about to read 4, iclass 30, count 2 2006.173.16:59:17.35#ibcon#read 4, iclass 30, count 2 2006.173.16:59:17.35#ibcon#about to read 5, iclass 30, count 2 2006.173.16:59:17.35#ibcon#read 5, iclass 30, count 2 2006.173.16:59:17.35#ibcon#about to read 6, iclass 30, count 2 2006.173.16:59:17.35#ibcon#read 6, iclass 30, count 2 2006.173.16:59:17.35#ibcon#end of sib2, iclass 30, count 2 2006.173.16:59:17.35#ibcon#*mode == 0, iclass 30, count 2 2006.173.16:59:17.35#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.16:59:17.35#ibcon#[27=AT08-04\r\n] 2006.173.16:59:17.35#ibcon#*before write, iclass 30, count 2 2006.173.16:59:17.35#ibcon#enter sib2, iclass 30, count 2 2006.173.16:59:17.35#ibcon#flushed, iclass 30, count 2 2006.173.16:59:17.35#ibcon#about to write, iclass 30, count 2 2006.173.16:59:17.35#ibcon#wrote, iclass 30, count 2 2006.173.16:59:17.35#ibcon#about to read 3, iclass 30, count 2 2006.173.16:59:17.38#ibcon#read 3, iclass 30, count 2 2006.173.16:59:17.38#ibcon#about to read 4, iclass 30, count 2 2006.173.16:59:17.38#ibcon#read 4, iclass 30, count 2 2006.173.16:59:17.38#ibcon#about to read 5, iclass 30, count 2 2006.173.16:59:17.38#ibcon#read 5, iclass 30, count 2 2006.173.16:59:17.38#ibcon#about to read 6, iclass 30, count 2 2006.173.16:59:17.38#ibcon#read 6, iclass 30, count 2 2006.173.16:59:17.38#ibcon#end of sib2, iclass 30, count 2 2006.173.16:59:17.38#ibcon#*after write, iclass 30, count 2 2006.173.16:59:17.38#ibcon#*before return 0, iclass 30, count 2 2006.173.16:59:17.38#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.16:59:17.38#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.16:59:17.38#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.16:59:17.38#ibcon#ireg 7 cls_cnt 0 2006.173.16:59:17.38#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.16:59:17.50#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.16:59:17.50#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.16:59:17.50#ibcon#enter wrdev, iclass 30, count 0 2006.173.16:59:17.50#ibcon#first serial, iclass 30, count 0 2006.173.16:59:17.50#ibcon#enter sib2, iclass 30, count 0 2006.173.16:59:17.50#ibcon#flushed, iclass 30, count 0 2006.173.16:59:17.50#ibcon#about to write, iclass 30, count 0 2006.173.16:59:17.50#ibcon#wrote, iclass 30, count 0 2006.173.16:59:17.50#ibcon#about to read 3, iclass 30, count 0 2006.173.16:59:17.52#ibcon#read 3, iclass 30, count 0 2006.173.16:59:17.52#ibcon#about to read 4, iclass 30, count 0 2006.173.16:59:17.52#ibcon#read 4, iclass 30, count 0 2006.173.16:59:17.52#ibcon#about to read 5, iclass 30, count 0 2006.173.16:59:17.52#ibcon#read 5, iclass 30, count 0 2006.173.16:59:17.52#ibcon#about to read 6, iclass 30, count 0 2006.173.16:59:17.52#ibcon#read 6, iclass 30, count 0 2006.173.16:59:17.52#ibcon#end of sib2, iclass 30, count 0 2006.173.16:59:17.52#ibcon#*mode == 0, iclass 30, count 0 2006.173.16:59:17.52#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.16:59:17.52#ibcon#[27=USB\r\n] 2006.173.16:59:17.52#ibcon#*before write, iclass 30, count 0 2006.173.16:59:17.52#ibcon#enter sib2, iclass 30, count 0 2006.173.16:59:17.52#ibcon#flushed, iclass 30, count 0 2006.173.16:59:17.52#ibcon#about to write, iclass 30, count 0 2006.173.16:59:17.52#ibcon#wrote, iclass 30, count 0 2006.173.16:59:17.52#ibcon#about to read 3, iclass 30, count 0 2006.173.16:59:17.55#ibcon#read 3, iclass 30, count 0 2006.173.16:59:17.55#ibcon#about to read 4, iclass 30, count 0 2006.173.16:59:17.55#ibcon#read 4, iclass 30, count 0 2006.173.16:59:17.55#ibcon#about to read 5, iclass 30, count 0 2006.173.16:59:17.55#ibcon#read 5, iclass 30, count 0 2006.173.16:59:17.55#ibcon#about to read 6, iclass 30, count 0 2006.173.16:59:17.55#ibcon#read 6, iclass 30, count 0 2006.173.16:59:17.55#ibcon#end of sib2, iclass 30, count 0 2006.173.16:59:17.55#ibcon#*after write, iclass 30, count 0 2006.173.16:59:17.55#ibcon#*before return 0, iclass 30, count 0 2006.173.16:59:17.55#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.16:59:17.55#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.16:59:17.55#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.16:59:17.55#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.16:59:17.55$vck44/vabw=wide 2006.173.16:59:17.55#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.16:59:17.55#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.16:59:17.55#ibcon#ireg 8 cls_cnt 0 2006.173.16:59:17.55#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.16:59:17.55#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.16:59:17.55#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.16:59:17.55#ibcon#enter wrdev, iclass 32, count 0 2006.173.16:59:17.55#ibcon#first serial, iclass 32, count 0 2006.173.16:59:17.55#ibcon#enter sib2, iclass 32, count 0 2006.173.16:59:17.55#ibcon#flushed, iclass 32, count 0 2006.173.16:59:17.55#ibcon#about to write, iclass 32, count 0 2006.173.16:59:17.55#ibcon#wrote, iclass 32, count 0 2006.173.16:59:17.55#ibcon#about to read 3, iclass 32, count 0 2006.173.16:59:17.57#ibcon#read 3, iclass 32, count 0 2006.173.16:59:17.57#ibcon#about to read 4, iclass 32, count 0 2006.173.16:59:17.57#ibcon#read 4, iclass 32, count 0 2006.173.16:59:17.57#ibcon#about to read 5, iclass 32, count 0 2006.173.16:59:17.57#ibcon#read 5, iclass 32, count 0 2006.173.16:59:17.57#ibcon#about to read 6, iclass 32, count 0 2006.173.16:59:17.57#ibcon#read 6, iclass 32, count 0 2006.173.16:59:17.57#ibcon#end of sib2, iclass 32, count 0 2006.173.16:59:17.57#ibcon#*mode == 0, iclass 32, count 0 2006.173.16:59:17.57#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.16:59:17.57#ibcon#[25=BW32\r\n] 2006.173.16:59:17.57#ibcon#*before write, iclass 32, count 0 2006.173.16:59:17.57#ibcon#enter sib2, iclass 32, count 0 2006.173.16:59:17.57#ibcon#flushed, iclass 32, count 0 2006.173.16:59:17.57#ibcon#about to write, iclass 32, count 0 2006.173.16:59:17.57#ibcon#wrote, iclass 32, count 0 2006.173.16:59:17.57#ibcon#about to read 3, iclass 32, count 0 2006.173.16:59:17.60#ibcon#read 3, iclass 32, count 0 2006.173.16:59:17.60#ibcon#about to read 4, iclass 32, count 0 2006.173.16:59:17.60#ibcon#read 4, iclass 32, count 0 2006.173.16:59:17.60#ibcon#about to read 5, iclass 32, count 0 2006.173.16:59:17.60#ibcon#read 5, iclass 32, count 0 2006.173.16:59:17.60#ibcon#about to read 6, iclass 32, count 0 2006.173.16:59:17.60#ibcon#read 6, iclass 32, count 0 2006.173.16:59:17.60#ibcon#end of sib2, iclass 32, count 0 2006.173.16:59:17.60#ibcon#*after write, iclass 32, count 0 2006.173.16:59:17.60#ibcon#*before return 0, iclass 32, count 0 2006.173.16:59:17.60#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.16:59:17.60#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.16:59:17.60#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.16:59:17.60#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.16:59:17.60$vck44/vbbw=wide 2006.173.16:59:17.60#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.16:59:17.60#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.16:59:17.60#ibcon#ireg 8 cls_cnt 0 2006.173.16:59:17.60#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.16:59:17.67#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.16:59:17.67#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.16:59:17.67#ibcon#enter wrdev, iclass 34, count 0 2006.173.16:59:17.67#ibcon#first serial, iclass 34, count 0 2006.173.16:59:17.67#ibcon#enter sib2, iclass 34, count 0 2006.173.16:59:17.67#ibcon#flushed, iclass 34, count 0 2006.173.16:59:17.67#ibcon#about to write, iclass 34, count 0 2006.173.16:59:17.67#ibcon#wrote, iclass 34, count 0 2006.173.16:59:17.67#ibcon#about to read 3, iclass 34, count 0 2006.173.16:59:17.69#ibcon#read 3, iclass 34, count 0 2006.173.16:59:17.69#ibcon#about to read 4, iclass 34, count 0 2006.173.16:59:17.69#ibcon#read 4, iclass 34, count 0 2006.173.16:59:17.69#ibcon#about to read 5, iclass 34, count 0 2006.173.16:59:17.69#ibcon#read 5, iclass 34, count 0 2006.173.16:59:17.69#ibcon#about to read 6, iclass 34, count 0 2006.173.16:59:17.69#ibcon#read 6, iclass 34, count 0 2006.173.16:59:17.69#ibcon#end of sib2, iclass 34, count 0 2006.173.16:59:17.69#ibcon#*mode == 0, iclass 34, count 0 2006.173.16:59:17.69#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.16:59:17.69#ibcon#[27=BW32\r\n] 2006.173.16:59:17.69#ibcon#*before write, iclass 34, count 0 2006.173.16:59:17.69#ibcon#enter sib2, iclass 34, count 0 2006.173.16:59:17.69#ibcon#flushed, iclass 34, count 0 2006.173.16:59:17.69#ibcon#about to write, iclass 34, count 0 2006.173.16:59:17.69#ibcon#wrote, iclass 34, count 0 2006.173.16:59:17.69#ibcon#about to read 3, iclass 34, count 0 2006.173.16:59:17.72#ibcon#read 3, iclass 34, count 0 2006.173.16:59:17.72#ibcon#about to read 4, iclass 34, count 0 2006.173.16:59:17.72#ibcon#read 4, iclass 34, count 0 2006.173.16:59:17.72#ibcon#about to read 5, iclass 34, count 0 2006.173.16:59:17.72#ibcon#read 5, iclass 34, count 0 2006.173.16:59:17.72#ibcon#about to read 6, iclass 34, count 0 2006.173.16:59:17.72#ibcon#read 6, iclass 34, count 0 2006.173.16:59:17.72#ibcon#end of sib2, iclass 34, count 0 2006.173.16:59:17.72#ibcon#*after write, iclass 34, count 0 2006.173.16:59:17.72#ibcon#*before return 0, iclass 34, count 0 2006.173.16:59:17.72#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.16:59:17.72#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.16:59:17.72#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.16:59:17.72#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.16:59:17.72$setupk4/ifdk4 2006.173.16:59:17.72$ifdk4/lo= 2006.173.16:59:17.72$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.16:59:17.72$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.16:59:17.72$ifdk4/patch= 2006.173.16:59:17.72$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.16:59:17.72$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.16:59:17.72$setupk4/!*+20s 2006.173.16:59:18.81#abcon#<5=/14 0.9 2.3 20.331001002.8\r\n> 2006.173.16:59:18.83#abcon#{5=INTERFACE CLEAR} 2006.173.16:59:18.89#abcon#[5=S1D000X0/0*\r\n] 2006.173.16:59:28.98#abcon#<5=/14 0.9 2.3 20.331001002.8\r\n> 2006.173.16:59:29.00#abcon#{5=INTERFACE CLEAR} 2006.173.16:59:29.06#abcon#[5=S1D000X0/0*\r\n] 2006.173.16:59:32.23$setupk4/"tpicd 2006.173.16:59:32.23$setupk4/echo=off 2006.173.16:59:32.23$setupk4/xlog=off 2006.173.16:59:32.23:!2006.173.17:03:27 2006.173.17:00:33.14#trakl#Source acquired 2006.173.17:00:34.14#flagr#flagr/antenna,acquired 2006.173.17:03:27.00:preob 2006.173.17:03:27.14/onsource/TRACKING 2006.173.17:03:27.14:!2006.173.17:03:37 2006.173.17:03:37.00:"tape 2006.173.17:03:37.00:"st=record 2006.173.17:03:37.00:data_valid=on 2006.173.17:03:37.00:midob 2006.173.17:03:37.14/onsource/TRACKING 2006.173.17:03:37.14/wx/20.30,1002.8,100 2006.173.17:03:37.24/cable/+6.5124E-03 2006.173.17:03:38.33/va/01,07,usb,yes,35,38 2006.173.17:03:38.33/va/02,06,usb,yes,35,36 2006.173.17:03:38.33/va/03,05,usb,yes,44,46 2006.173.17:03:38.33/va/04,06,usb,yes,36,38 2006.173.17:03:38.33/va/05,04,usb,yes,28,28 2006.173.17:03:38.33/va/06,03,usb,yes,39,39 2006.173.17:03:38.33/va/07,04,usb,yes,32,33 2006.173.17:03:38.33/va/08,04,usb,yes,27,32 2006.173.17:03:38.56/valo/01,524.99,yes,locked 2006.173.17:03:38.56/valo/02,534.99,yes,locked 2006.173.17:03:38.56/valo/03,564.99,yes,locked 2006.173.17:03:38.56/valo/04,624.99,yes,locked 2006.173.17:03:38.56/valo/05,734.99,yes,locked 2006.173.17:03:38.56/valo/06,814.99,yes,locked 2006.173.17:03:38.56/valo/07,864.99,yes,locked 2006.173.17:03:38.56/valo/08,884.99,yes,locked 2006.173.17:03:39.65/vb/01,04,usb,yes,29,27 2006.173.17:03:39.65/vb/02,04,usb,yes,32,31 2006.173.17:03:39.65/vb/03,04,usb,yes,29,31 2006.173.17:03:39.65/vb/04,04,usb,yes,33,32 2006.173.17:03:39.65/vb/05,04,usb,yes,26,28 2006.173.17:03:39.65/vb/06,04,usb,yes,30,26 2006.173.17:03:39.65/vb/07,04,usb,yes,30,29 2006.173.17:03:39.65/vb/08,04,usb,yes,27,30 2006.173.17:03:39.88/vblo/01,629.99,yes,locked 2006.173.17:03:39.88/vblo/02,634.99,yes,locked 2006.173.17:03:39.88/vblo/03,649.99,yes,locked 2006.173.17:03:39.88/vblo/04,679.99,yes,locked 2006.173.17:03:39.88/vblo/05,709.99,yes,locked 2006.173.17:03:39.88/vblo/06,719.99,yes,locked 2006.173.17:03:39.88/vblo/07,734.99,yes,locked 2006.173.17:03:39.88/vblo/08,744.99,yes,locked 2006.173.17:03:40.03/vabw/8 2006.173.17:03:40.18/vbbw/8 2006.173.17:03:40.35/xfe/off,on,14.5 2006.173.17:03:40.74/ifatt/23,28,28,28 2006.173.17:03:41.07/fmout-gps/S +4.03E-07 2006.173.17:03:41.11:!2006.173.17:04:17 2006.173.17:04:17.01:data_valid=off 2006.173.17:04:17.01:"et 2006.173.17:04:17.02:!+3s 2006.173.17:04:20.03:"tape 2006.173.17:04:20.03:postob 2006.173.17:04:20.20/cable/+6.5132E-03 2006.173.17:04:20.20/wx/20.29,1002.8,100 2006.173.17:04:20.26/fmout-gps/S +4.02E-07 2006.173.17:04:20.26:scan_name=173-1705,jd0606,40 2006.173.17:04:20.27:source=1921-293,192451.06,-291430.1,2000.0,ccw 2006.173.17:04:22.14#flagr#flagr/antenna,new-source 2006.173.17:04:22.14:checkk5 2006.173.17:04:22.53/chk_autoobs//k5ts1/ autoobs is running! 2006.173.17:04:22.93/chk_autoobs//k5ts2/ autoobs is running! 2006.173.17:04:23.34/chk_autoobs//k5ts3/ autoobs is running! 2006.173.17:04:23.72/chk_autoobs//k5ts4/ autoobs is running! 2006.173.17:04:24.08/chk_obsdata//k5ts1/T1731703??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.17:04:24.47/chk_obsdata//k5ts2/T1731703??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.17:04:24.87/chk_obsdata//k5ts3/T1731703??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.17:04:25.26/chk_obsdata//k5ts4/T1731703??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.17:04:25.97/k5log//k5ts1_log_newline 2006.173.17:04:26.68/k5log//k5ts2_log_newline 2006.173.17:04:27.39/k5log//k5ts3_log_newline 2006.173.17:04:28.07/k5log//k5ts4_log_newline 2006.173.17:04:28.09/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.17:04:28.09:setupk4=1 2006.173.17:04:28.09$setupk4/echo=on 2006.173.17:04:28.09$setupk4/pcalon 2006.173.17:04:28.09$pcalon/"no phase cal control is implemented here 2006.173.17:04:28.09$setupk4/"tpicd=stop 2006.173.17:04:28.09$setupk4/"rec=synch_on 2006.173.17:04:28.09$setupk4/"rec_mode=128 2006.173.17:04:28.09$setupk4/!* 2006.173.17:04:28.09$setupk4/recpk4 2006.173.17:04:28.09$recpk4/recpatch= 2006.173.17:04:28.09$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.17:04:28.09$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.17:04:28.09$setupk4/vck44 2006.173.17:04:28.09$vck44/valo=1,524.99 2006.173.17:04:28.09#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.17:04:28.09#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.17:04:28.09#ibcon#ireg 17 cls_cnt 0 2006.173.17:04:28.09#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.17:04:28.09#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.17:04:28.09#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.17:04:28.09#ibcon#enter wrdev, iclass 19, count 0 2006.173.17:04:28.09#ibcon#first serial, iclass 19, count 0 2006.173.17:04:28.09#ibcon#enter sib2, iclass 19, count 0 2006.173.17:04:28.09#ibcon#flushed, iclass 19, count 0 2006.173.17:04:28.09#ibcon#about to write, iclass 19, count 0 2006.173.17:04:28.09#ibcon#wrote, iclass 19, count 0 2006.173.17:04:28.09#ibcon#about to read 3, iclass 19, count 0 2006.173.17:04:28.11#ibcon#read 3, iclass 19, count 0 2006.173.17:04:28.11#ibcon#about to read 4, iclass 19, count 0 2006.173.17:04:28.11#ibcon#read 4, iclass 19, count 0 2006.173.17:04:28.11#ibcon#about to read 5, iclass 19, count 0 2006.173.17:04:28.11#ibcon#read 5, iclass 19, count 0 2006.173.17:04:28.11#ibcon#about to read 6, iclass 19, count 0 2006.173.17:04:28.11#ibcon#read 6, iclass 19, count 0 2006.173.17:04:28.11#ibcon#end of sib2, iclass 19, count 0 2006.173.17:04:28.11#ibcon#*mode == 0, iclass 19, count 0 2006.173.17:04:28.11#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.17:04:28.11#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.17:04:28.11#ibcon#*before write, iclass 19, count 0 2006.173.17:04:28.11#ibcon#enter sib2, iclass 19, count 0 2006.173.17:04:28.11#ibcon#flushed, iclass 19, count 0 2006.173.17:04:28.11#ibcon#about to write, iclass 19, count 0 2006.173.17:04:28.11#ibcon#wrote, iclass 19, count 0 2006.173.17:04:28.11#ibcon#about to read 3, iclass 19, count 0 2006.173.17:04:28.16#ibcon#read 3, iclass 19, count 0 2006.173.17:04:28.16#ibcon#about to read 4, iclass 19, count 0 2006.173.17:04:28.16#ibcon#read 4, iclass 19, count 0 2006.173.17:04:28.16#ibcon#about to read 5, iclass 19, count 0 2006.173.17:04:28.16#ibcon#read 5, iclass 19, count 0 2006.173.17:04:28.16#ibcon#about to read 6, iclass 19, count 0 2006.173.17:04:28.16#ibcon#read 6, iclass 19, count 0 2006.173.17:04:28.16#ibcon#end of sib2, iclass 19, count 0 2006.173.17:04:28.16#ibcon#*after write, iclass 19, count 0 2006.173.17:04:28.16#ibcon#*before return 0, iclass 19, count 0 2006.173.17:04:28.16#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.17:04:28.16#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.17:04:28.16#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.17:04:28.16#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.17:04:28.16$vck44/va=1,7 2006.173.17:04:28.16#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.17:04:28.16#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.17:04:28.16#ibcon#ireg 11 cls_cnt 2 2006.173.17:04:28.16#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.17:04:28.16#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.17:04:28.16#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.17:04:28.16#ibcon#enter wrdev, iclass 21, count 2 2006.173.17:04:28.16#ibcon#first serial, iclass 21, count 2 2006.173.17:04:28.16#ibcon#enter sib2, iclass 21, count 2 2006.173.17:04:28.16#ibcon#flushed, iclass 21, count 2 2006.173.17:04:28.16#ibcon#about to write, iclass 21, count 2 2006.173.17:04:28.16#ibcon#wrote, iclass 21, count 2 2006.173.17:04:28.16#ibcon#about to read 3, iclass 21, count 2 2006.173.17:04:28.18#ibcon#read 3, iclass 21, count 2 2006.173.17:04:28.18#ibcon#about to read 4, iclass 21, count 2 2006.173.17:04:28.18#ibcon#read 4, iclass 21, count 2 2006.173.17:04:28.18#ibcon#about to read 5, iclass 21, count 2 2006.173.17:04:28.18#ibcon#read 5, iclass 21, count 2 2006.173.17:04:28.18#ibcon#about to read 6, iclass 21, count 2 2006.173.17:04:28.18#ibcon#read 6, iclass 21, count 2 2006.173.17:04:28.18#ibcon#end of sib2, iclass 21, count 2 2006.173.17:04:28.18#ibcon#*mode == 0, iclass 21, count 2 2006.173.17:04:28.18#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.17:04:28.18#ibcon#[25=AT01-07\r\n] 2006.173.17:04:28.18#ibcon#*before write, iclass 21, count 2 2006.173.17:04:28.18#ibcon#enter sib2, iclass 21, count 2 2006.173.17:04:28.18#ibcon#flushed, iclass 21, count 2 2006.173.17:04:28.18#ibcon#about to write, iclass 21, count 2 2006.173.17:04:28.18#ibcon#wrote, iclass 21, count 2 2006.173.17:04:28.18#ibcon#about to read 3, iclass 21, count 2 2006.173.17:04:28.21#ibcon#read 3, iclass 21, count 2 2006.173.17:04:28.21#ibcon#about to read 4, iclass 21, count 2 2006.173.17:04:28.21#ibcon#read 4, iclass 21, count 2 2006.173.17:04:28.21#ibcon#about to read 5, iclass 21, count 2 2006.173.17:04:28.21#ibcon#read 5, iclass 21, count 2 2006.173.17:04:28.21#ibcon#about to read 6, iclass 21, count 2 2006.173.17:04:28.21#ibcon#read 6, iclass 21, count 2 2006.173.17:04:28.21#ibcon#end of sib2, iclass 21, count 2 2006.173.17:04:28.21#ibcon#*after write, iclass 21, count 2 2006.173.17:04:28.21#ibcon#*before return 0, iclass 21, count 2 2006.173.17:04:28.21#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.17:04:28.21#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.17:04:28.21#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.17:04:28.21#ibcon#ireg 7 cls_cnt 0 2006.173.17:04:28.21#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.17:04:28.33#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.17:04:28.33#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.17:04:28.33#ibcon#enter wrdev, iclass 21, count 0 2006.173.17:04:28.33#ibcon#first serial, iclass 21, count 0 2006.173.17:04:28.33#ibcon#enter sib2, iclass 21, count 0 2006.173.17:04:28.33#ibcon#flushed, iclass 21, count 0 2006.173.17:04:28.33#ibcon#about to write, iclass 21, count 0 2006.173.17:04:28.33#ibcon#wrote, iclass 21, count 0 2006.173.17:04:28.33#ibcon#about to read 3, iclass 21, count 0 2006.173.17:04:28.35#ibcon#read 3, iclass 21, count 0 2006.173.17:04:28.35#ibcon#about to read 4, iclass 21, count 0 2006.173.17:04:28.35#ibcon#read 4, iclass 21, count 0 2006.173.17:04:28.35#ibcon#about to read 5, iclass 21, count 0 2006.173.17:04:28.35#ibcon#read 5, iclass 21, count 0 2006.173.17:04:28.35#ibcon#about to read 6, iclass 21, count 0 2006.173.17:04:28.35#ibcon#read 6, iclass 21, count 0 2006.173.17:04:28.35#ibcon#end of sib2, iclass 21, count 0 2006.173.17:04:28.35#ibcon#*mode == 0, iclass 21, count 0 2006.173.17:04:28.35#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.17:04:28.35#ibcon#[25=USB\r\n] 2006.173.17:04:28.35#ibcon#*before write, iclass 21, count 0 2006.173.17:04:28.35#ibcon#enter sib2, iclass 21, count 0 2006.173.17:04:28.35#ibcon#flushed, iclass 21, count 0 2006.173.17:04:28.35#ibcon#about to write, iclass 21, count 0 2006.173.17:04:28.35#ibcon#wrote, iclass 21, count 0 2006.173.17:04:28.35#ibcon#about to read 3, iclass 21, count 0 2006.173.17:04:28.38#ibcon#read 3, iclass 21, count 0 2006.173.17:04:28.38#ibcon#about to read 4, iclass 21, count 0 2006.173.17:04:28.38#ibcon#read 4, iclass 21, count 0 2006.173.17:04:28.38#ibcon#about to read 5, iclass 21, count 0 2006.173.17:04:28.38#ibcon#read 5, iclass 21, count 0 2006.173.17:04:28.38#ibcon#about to read 6, iclass 21, count 0 2006.173.17:04:28.38#ibcon#read 6, iclass 21, count 0 2006.173.17:04:28.38#ibcon#end of sib2, iclass 21, count 0 2006.173.17:04:28.38#ibcon#*after write, iclass 21, count 0 2006.173.17:04:28.38#ibcon#*before return 0, iclass 21, count 0 2006.173.17:04:28.38#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.17:04:28.38#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.17:04:28.38#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.17:04:28.38#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.17:04:28.38$vck44/valo=2,534.99 2006.173.17:04:28.38#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.17:04:28.38#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.17:04:28.38#ibcon#ireg 17 cls_cnt 0 2006.173.17:04:28.38#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.17:04:28.38#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.17:04:28.38#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.17:04:28.38#ibcon#enter wrdev, iclass 23, count 0 2006.173.17:04:28.38#ibcon#first serial, iclass 23, count 0 2006.173.17:04:28.38#ibcon#enter sib2, iclass 23, count 0 2006.173.17:04:28.38#ibcon#flushed, iclass 23, count 0 2006.173.17:04:28.38#ibcon#about to write, iclass 23, count 0 2006.173.17:04:28.38#ibcon#wrote, iclass 23, count 0 2006.173.17:04:28.38#ibcon#about to read 3, iclass 23, count 0 2006.173.17:04:28.40#ibcon#read 3, iclass 23, count 0 2006.173.17:04:28.40#ibcon#about to read 4, iclass 23, count 0 2006.173.17:04:28.40#ibcon#read 4, iclass 23, count 0 2006.173.17:04:28.40#ibcon#about to read 5, iclass 23, count 0 2006.173.17:04:28.40#ibcon#read 5, iclass 23, count 0 2006.173.17:04:28.40#ibcon#about to read 6, iclass 23, count 0 2006.173.17:04:28.40#ibcon#read 6, iclass 23, count 0 2006.173.17:04:28.40#ibcon#end of sib2, iclass 23, count 0 2006.173.17:04:28.40#ibcon#*mode == 0, iclass 23, count 0 2006.173.17:04:28.40#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.17:04:28.40#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.17:04:28.40#ibcon#*before write, iclass 23, count 0 2006.173.17:04:28.40#ibcon#enter sib2, iclass 23, count 0 2006.173.17:04:28.40#ibcon#flushed, iclass 23, count 0 2006.173.17:04:28.40#ibcon#about to write, iclass 23, count 0 2006.173.17:04:28.40#ibcon#wrote, iclass 23, count 0 2006.173.17:04:28.40#ibcon#about to read 3, iclass 23, count 0 2006.173.17:04:28.44#ibcon#read 3, iclass 23, count 0 2006.173.17:04:28.44#ibcon#about to read 4, iclass 23, count 0 2006.173.17:04:28.44#ibcon#read 4, iclass 23, count 0 2006.173.17:04:28.44#ibcon#about to read 5, iclass 23, count 0 2006.173.17:04:28.44#ibcon#read 5, iclass 23, count 0 2006.173.17:04:28.44#ibcon#about to read 6, iclass 23, count 0 2006.173.17:04:28.44#ibcon#read 6, iclass 23, count 0 2006.173.17:04:28.44#ibcon#end of sib2, iclass 23, count 0 2006.173.17:04:28.44#ibcon#*after write, iclass 23, count 0 2006.173.17:04:28.44#ibcon#*before return 0, iclass 23, count 0 2006.173.17:04:28.44#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.17:04:28.44#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.17:04:28.44#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.17:04:28.44#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.17:04:28.44$vck44/va=2,6 2006.173.17:04:28.44#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.17:04:28.44#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.17:04:28.44#ibcon#ireg 11 cls_cnt 2 2006.173.17:04:28.44#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.17:04:28.50#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.17:04:28.50#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.17:04:28.50#ibcon#enter wrdev, iclass 25, count 2 2006.173.17:04:28.50#ibcon#first serial, iclass 25, count 2 2006.173.17:04:28.50#ibcon#enter sib2, iclass 25, count 2 2006.173.17:04:28.50#ibcon#flushed, iclass 25, count 2 2006.173.17:04:28.50#ibcon#about to write, iclass 25, count 2 2006.173.17:04:28.50#ibcon#wrote, iclass 25, count 2 2006.173.17:04:28.50#ibcon#about to read 3, iclass 25, count 2 2006.173.17:04:28.52#ibcon#read 3, iclass 25, count 2 2006.173.17:04:28.52#ibcon#about to read 4, iclass 25, count 2 2006.173.17:04:28.52#ibcon#read 4, iclass 25, count 2 2006.173.17:04:28.52#ibcon#about to read 5, iclass 25, count 2 2006.173.17:04:28.52#ibcon#read 5, iclass 25, count 2 2006.173.17:04:28.52#ibcon#about to read 6, iclass 25, count 2 2006.173.17:04:28.52#ibcon#read 6, iclass 25, count 2 2006.173.17:04:28.52#ibcon#end of sib2, iclass 25, count 2 2006.173.17:04:28.52#ibcon#*mode == 0, iclass 25, count 2 2006.173.17:04:28.52#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.17:04:28.52#ibcon#[25=AT02-06\r\n] 2006.173.17:04:28.52#ibcon#*before write, iclass 25, count 2 2006.173.17:04:28.52#ibcon#enter sib2, iclass 25, count 2 2006.173.17:04:28.52#ibcon#flushed, iclass 25, count 2 2006.173.17:04:28.52#ibcon#about to write, iclass 25, count 2 2006.173.17:04:28.52#ibcon#wrote, iclass 25, count 2 2006.173.17:04:28.52#ibcon#about to read 3, iclass 25, count 2 2006.173.17:04:28.55#ibcon#read 3, iclass 25, count 2 2006.173.17:04:28.55#ibcon#about to read 4, iclass 25, count 2 2006.173.17:04:28.55#ibcon#read 4, iclass 25, count 2 2006.173.17:04:28.55#ibcon#about to read 5, iclass 25, count 2 2006.173.17:04:28.55#ibcon#read 5, iclass 25, count 2 2006.173.17:04:28.55#ibcon#about to read 6, iclass 25, count 2 2006.173.17:04:28.55#ibcon#read 6, iclass 25, count 2 2006.173.17:04:28.55#ibcon#end of sib2, iclass 25, count 2 2006.173.17:04:28.55#ibcon#*after write, iclass 25, count 2 2006.173.17:04:28.55#ibcon#*before return 0, iclass 25, count 2 2006.173.17:04:28.55#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.17:04:28.55#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.17:04:28.55#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.17:04:28.55#ibcon#ireg 7 cls_cnt 0 2006.173.17:04:28.55#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.17:04:28.67#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.17:04:28.67#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.17:04:28.67#ibcon#enter wrdev, iclass 25, count 0 2006.173.17:04:28.67#ibcon#first serial, iclass 25, count 0 2006.173.17:04:28.67#ibcon#enter sib2, iclass 25, count 0 2006.173.17:04:28.67#ibcon#flushed, iclass 25, count 0 2006.173.17:04:28.67#ibcon#about to write, iclass 25, count 0 2006.173.17:04:28.67#ibcon#wrote, iclass 25, count 0 2006.173.17:04:28.67#ibcon#about to read 3, iclass 25, count 0 2006.173.17:04:28.69#ibcon#read 3, iclass 25, count 0 2006.173.17:04:28.69#ibcon#about to read 4, iclass 25, count 0 2006.173.17:04:28.69#ibcon#read 4, iclass 25, count 0 2006.173.17:04:28.69#ibcon#about to read 5, iclass 25, count 0 2006.173.17:04:28.69#ibcon#read 5, iclass 25, count 0 2006.173.17:04:28.69#ibcon#about to read 6, iclass 25, count 0 2006.173.17:04:28.69#ibcon#read 6, iclass 25, count 0 2006.173.17:04:28.69#ibcon#end of sib2, iclass 25, count 0 2006.173.17:04:28.69#ibcon#*mode == 0, iclass 25, count 0 2006.173.17:04:28.69#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.17:04:28.69#ibcon#[25=USB\r\n] 2006.173.17:04:28.69#ibcon#*before write, iclass 25, count 0 2006.173.17:04:28.69#ibcon#enter sib2, iclass 25, count 0 2006.173.17:04:28.69#ibcon#flushed, iclass 25, count 0 2006.173.17:04:28.69#ibcon#about to write, iclass 25, count 0 2006.173.17:04:28.69#ibcon#wrote, iclass 25, count 0 2006.173.17:04:28.69#ibcon#about to read 3, iclass 25, count 0 2006.173.17:04:28.72#ibcon#read 3, iclass 25, count 0 2006.173.17:04:28.72#ibcon#about to read 4, iclass 25, count 0 2006.173.17:04:28.72#ibcon#read 4, iclass 25, count 0 2006.173.17:04:28.72#ibcon#about to read 5, iclass 25, count 0 2006.173.17:04:28.72#ibcon#read 5, iclass 25, count 0 2006.173.17:04:28.72#ibcon#about to read 6, iclass 25, count 0 2006.173.17:04:28.72#ibcon#read 6, iclass 25, count 0 2006.173.17:04:28.72#ibcon#end of sib2, iclass 25, count 0 2006.173.17:04:28.72#ibcon#*after write, iclass 25, count 0 2006.173.17:04:28.72#ibcon#*before return 0, iclass 25, count 0 2006.173.17:04:28.72#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.17:04:28.72#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.17:04:28.72#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.17:04:28.72#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.17:04:28.72$vck44/valo=3,564.99 2006.173.17:04:28.72#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.17:04:28.72#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.17:04:28.72#ibcon#ireg 17 cls_cnt 0 2006.173.17:04:28.72#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.17:04:28.72#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.17:04:28.72#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.17:04:28.72#ibcon#enter wrdev, iclass 27, count 0 2006.173.17:04:28.72#ibcon#first serial, iclass 27, count 0 2006.173.17:04:28.72#ibcon#enter sib2, iclass 27, count 0 2006.173.17:04:28.72#ibcon#flushed, iclass 27, count 0 2006.173.17:04:28.72#ibcon#about to write, iclass 27, count 0 2006.173.17:04:28.72#ibcon#wrote, iclass 27, count 0 2006.173.17:04:28.72#ibcon#about to read 3, iclass 27, count 0 2006.173.17:04:28.74#ibcon#read 3, iclass 27, count 0 2006.173.17:04:28.74#ibcon#about to read 4, iclass 27, count 0 2006.173.17:04:28.74#ibcon#read 4, iclass 27, count 0 2006.173.17:04:28.74#ibcon#about to read 5, iclass 27, count 0 2006.173.17:04:28.74#ibcon#read 5, iclass 27, count 0 2006.173.17:04:28.74#ibcon#about to read 6, iclass 27, count 0 2006.173.17:04:28.74#ibcon#read 6, iclass 27, count 0 2006.173.17:04:28.74#ibcon#end of sib2, iclass 27, count 0 2006.173.17:04:28.74#ibcon#*mode == 0, iclass 27, count 0 2006.173.17:04:28.74#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.17:04:28.74#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.17:04:28.74#ibcon#*before write, iclass 27, count 0 2006.173.17:04:28.74#ibcon#enter sib2, iclass 27, count 0 2006.173.17:04:28.74#ibcon#flushed, iclass 27, count 0 2006.173.17:04:28.74#ibcon#about to write, iclass 27, count 0 2006.173.17:04:28.74#ibcon#wrote, iclass 27, count 0 2006.173.17:04:28.74#ibcon#about to read 3, iclass 27, count 0 2006.173.17:04:28.78#ibcon#read 3, iclass 27, count 0 2006.173.17:04:28.78#ibcon#about to read 4, iclass 27, count 0 2006.173.17:04:28.78#ibcon#read 4, iclass 27, count 0 2006.173.17:04:28.78#ibcon#about to read 5, iclass 27, count 0 2006.173.17:04:28.78#ibcon#read 5, iclass 27, count 0 2006.173.17:04:28.78#ibcon#about to read 6, iclass 27, count 0 2006.173.17:04:28.78#ibcon#read 6, iclass 27, count 0 2006.173.17:04:28.78#ibcon#end of sib2, iclass 27, count 0 2006.173.17:04:28.78#ibcon#*after write, iclass 27, count 0 2006.173.17:04:28.78#ibcon#*before return 0, iclass 27, count 0 2006.173.17:04:28.78#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.17:04:28.78#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.17:04:28.78#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.17:04:28.78#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.17:04:28.78$vck44/va=3,5 2006.173.17:04:28.78#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.17:04:28.78#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.17:04:28.78#ibcon#ireg 11 cls_cnt 2 2006.173.17:04:28.78#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.17:04:28.84#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.17:04:28.84#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.17:04:28.84#ibcon#enter wrdev, iclass 29, count 2 2006.173.17:04:28.84#ibcon#first serial, iclass 29, count 2 2006.173.17:04:28.84#ibcon#enter sib2, iclass 29, count 2 2006.173.17:04:28.84#ibcon#flushed, iclass 29, count 2 2006.173.17:04:28.84#ibcon#about to write, iclass 29, count 2 2006.173.17:04:28.84#ibcon#wrote, iclass 29, count 2 2006.173.17:04:28.84#ibcon#about to read 3, iclass 29, count 2 2006.173.17:04:28.86#ibcon#read 3, iclass 29, count 2 2006.173.17:04:28.86#ibcon#about to read 4, iclass 29, count 2 2006.173.17:04:28.86#ibcon#read 4, iclass 29, count 2 2006.173.17:04:28.86#ibcon#about to read 5, iclass 29, count 2 2006.173.17:04:28.86#ibcon#read 5, iclass 29, count 2 2006.173.17:04:28.86#ibcon#about to read 6, iclass 29, count 2 2006.173.17:04:28.86#ibcon#read 6, iclass 29, count 2 2006.173.17:04:28.86#ibcon#end of sib2, iclass 29, count 2 2006.173.17:04:28.86#ibcon#*mode == 0, iclass 29, count 2 2006.173.17:04:28.86#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.17:04:28.86#ibcon#[25=AT03-05\r\n] 2006.173.17:04:28.86#ibcon#*before write, iclass 29, count 2 2006.173.17:04:28.86#ibcon#enter sib2, iclass 29, count 2 2006.173.17:04:28.86#ibcon#flushed, iclass 29, count 2 2006.173.17:04:28.86#ibcon#about to write, iclass 29, count 2 2006.173.17:04:28.86#ibcon#wrote, iclass 29, count 2 2006.173.17:04:28.86#ibcon#about to read 3, iclass 29, count 2 2006.173.17:04:28.89#ibcon#read 3, iclass 29, count 2 2006.173.17:04:28.89#ibcon#about to read 4, iclass 29, count 2 2006.173.17:04:28.89#ibcon#read 4, iclass 29, count 2 2006.173.17:04:28.89#ibcon#about to read 5, iclass 29, count 2 2006.173.17:04:28.89#ibcon#read 5, iclass 29, count 2 2006.173.17:04:28.89#ibcon#about to read 6, iclass 29, count 2 2006.173.17:04:28.89#ibcon#read 6, iclass 29, count 2 2006.173.17:04:28.89#ibcon#end of sib2, iclass 29, count 2 2006.173.17:04:28.89#ibcon#*after write, iclass 29, count 2 2006.173.17:04:28.89#ibcon#*before return 0, iclass 29, count 2 2006.173.17:04:28.89#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.17:04:28.89#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.17:04:28.89#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.17:04:28.89#ibcon#ireg 7 cls_cnt 0 2006.173.17:04:28.89#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.17:04:29.01#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.17:04:29.01#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.17:04:29.01#ibcon#enter wrdev, iclass 29, count 0 2006.173.17:04:29.01#ibcon#first serial, iclass 29, count 0 2006.173.17:04:29.01#ibcon#enter sib2, iclass 29, count 0 2006.173.17:04:29.01#ibcon#flushed, iclass 29, count 0 2006.173.17:04:29.01#ibcon#about to write, iclass 29, count 0 2006.173.17:04:29.01#ibcon#wrote, iclass 29, count 0 2006.173.17:04:29.01#ibcon#about to read 3, iclass 29, count 0 2006.173.17:04:29.03#ibcon#read 3, iclass 29, count 0 2006.173.17:04:29.03#ibcon#about to read 4, iclass 29, count 0 2006.173.17:04:29.03#ibcon#read 4, iclass 29, count 0 2006.173.17:04:29.03#ibcon#about to read 5, iclass 29, count 0 2006.173.17:04:29.03#ibcon#read 5, iclass 29, count 0 2006.173.17:04:29.03#ibcon#about to read 6, iclass 29, count 0 2006.173.17:04:29.03#ibcon#read 6, iclass 29, count 0 2006.173.17:04:29.03#ibcon#end of sib2, iclass 29, count 0 2006.173.17:04:29.03#ibcon#*mode == 0, iclass 29, count 0 2006.173.17:04:29.03#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.17:04:29.03#ibcon#[25=USB\r\n] 2006.173.17:04:29.03#ibcon#*before write, iclass 29, count 0 2006.173.17:04:29.03#ibcon#enter sib2, iclass 29, count 0 2006.173.17:04:29.03#ibcon#flushed, iclass 29, count 0 2006.173.17:04:29.03#ibcon#about to write, iclass 29, count 0 2006.173.17:04:29.03#ibcon#wrote, iclass 29, count 0 2006.173.17:04:29.03#ibcon#about to read 3, iclass 29, count 0 2006.173.17:04:29.06#ibcon#read 3, iclass 29, count 0 2006.173.17:04:29.06#ibcon#about to read 4, iclass 29, count 0 2006.173.17:04:29.06#ibcon#read 4, iclass 29, count 0 2006.173.17:04:29.06#ibcon#about to read 5, iclass 29, count 0 2006.173.17:04:29.06#ibcon#read 5, iclass 29, count 0 2006.173.17:04:29.06#ibcon#about to read 6, iclass 29, count 0 2006.173.17:04:29.06#ibcon#read 6, iclass 29, count 0 2006.173.17:04:29.06#ibcon#end of sib2, iclass 29, count 0 2006.173.17:04:29.06#ibcon#*after write, iclass 29, count 0 2006.173.17:04:29.06#ibcon#*before return 0, iclass 29, count 0 2006.173.17:04:29.06#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.17:04:29.06#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.17:04:29.06#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.17:04:29.06#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.17:04:29.06$vck44/valo=4,624.99 2006.173.17:04:29.06#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.17:04:29.06#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.17:04:29.06#ibcon#ireg 17 cls_cnt 0 2006.173.17:04:29.06#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.17:04:29.06#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.17:04:29.06#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.17:04:29.06#ibcon#enter wrdev, iclass 31, count 0 2006.173.17:04:29.06#ibcon#first serial, iclass 31, count 0 2006.173.17:04:29.06#ibcon#enter sib2, iclass 31, count 0 2006.173.17:04:29.06#ibcon#flushed, iclass 31, count 0 2006.173.17:04:29.06#ibcon#about to write, iclass 31, count 0 2006.173.17:04:29.06#ibcon#wrote, iclass 31, count 0 2006.173.17:04:29.06#ibcon#about to read 3, iclass 31, count 0 2006.173.17:04:29.08#ibcon#read 3, iclass 31, count 0 2006.173.17:04:29.08#ibcon#about to read 4, iclass 31, count 0 2006.173.17:04:29.08#ibcon#read 4, iclass 31, count 0 2006.173.17:04:29.08#ibcon#about to read 5, iclass 31, count 0 2006.173.17:04:29.08#ibcon#read 5, iclass 31, count 0 2006.173.17:04:29.08#ibcon#about to read 6, iclass 31, count 0 2006.173.17:04:29.08#ibcon#read 6, iclass 31, count 0 2006.173.17:04:29.08#ibcon#end of sib2, iclass 31, count 0 2006.173.17:04:29.08#ibcon#*mode == 0, iclass 31, count 0 2006.173.17:04:29.08#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.17:04:29.08#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.17:04:29.08#ibcon#*before write, iclass 31, count 0 2006.173.17:04:29.08#ibcon#enter sib2, iclass 31, count 0 2006.173.17:04:29.08#ibcon#flushed, iclass 31, count 0 2006.173.17:04:29.08#ibcon#about to write, iclass 31, count 0 2006.173.17:04:29.08#ibcon#wrote, iclass 31, count 0 2006.173.17:04:29.08#ibcon#about to read 3, iclass 31, count 0 2006.173.17:04:29.12#ibcon#read 3, iclass 31, count 0 2006.173.17:04:29.12#ibcon#about to read 4, iclass 31, count 0 2006.173.17:04:29.12#ibcon#read 4, iclass 31, count 0 2006.173.17:04:29.12#ibcon#about to read 5, iclass 31, count 0 2006.173.17:04:29.12#ibcon#read 5, iclass 31, count 0 2006.173.17:04:29.12#ibcon#about to read 6, iclass 31, count 0 2006.173.17:04:29.12#ibcon#read 6, iclass 31, count 0 2006.173.17:04:29.12#ibcon#end of sib2, iclass 31, count 0 2006.173.17:04:29.12#ibcon#*after write, iclass 31, count 0 2006.173.17:04:29.12#ibcon#*before return 0, iclass 31, count 0 2006.173.17:04:29.12#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.17:04:29.12#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.17:04:29.12#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.17:04:29.12#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.17:04:29.12$vck44/va=4,6 2006.173.17:04:29.12#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.173.17:04:29.12#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.173.17:04:29.12#ibcon#ireg 11 cls_cnt 2 2006.173.17:04:29.12#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.17:04:29.18#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.17:04:29.18#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.17:04:29.18#ibcon#enter wrdev, iclass 33, count 2 2006.173.17:04:29.18#ibcon#first serial, iclass 33, count 2 2006.173.17:04:29.18#ibcon#enter sib2, iclass 33, count 2 2006.173.17:04:29.18#ibcon#flushed, iclass 33, count 2 2006.173.17:04:29.18#ibcon#about to write, iclass 33, count 2 2006.173.17:04:29.18#ibcon#wrote, iclass 33, count 2 2006.173.17:04:29.18#ibcon#about to read 3, iclass 33, count 2 2006.173.17:04:29.20#ibcon#read 3, iclass 33, count 2 2006.173.17:04:29.20#ibcon#about to read 4, iclass 33, count 2 2006.173.17:04:29.20#ibcon#read 4, iclass 33, count 2 2006.173.17:04:29.20#ibcon#about to read 5, iclass 33, count 2 2006.173.17:04:29.20#ibcon#read 5, iclass 33, count 2 2006.173.17:04:29.20#ibcon#about to read 6, iclass 33, count 2 2006.173.17:04:29.20#ibcon#read 6, iclass 33, count 2 2006.173.17:04:29.20#ibcon#end of sib2, iclass 33, count 2 2006.173.17:04:29.20#ibcon#*mode == 0, iclass 33, count 2 2006.173.17:04:29.20#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.173.17:04:29.20#ibcon#[25=AT04-06\r\n] 2006.173.17:04:29.20#ibcon#*before write, iclass 33, count 2 2006.173.17:04:29.20#ibcon#enter sib2, iclass 33, count 2 2006.173.17:04:29.20#ibcon#flushed, iclass 33, count 2 2006.173.17:04:29.20#ibcon#about to write, iclass 33, count 2 2006.173.17:04:29.20#ibcon#wrote, iclass 33, count 2 2006.173.17:04:29.20#ibcon#about to read 3, iclass 33, count 2 2006.173.17:04:29.23#ibcon#read 3, iclass 33, count 2 2006.173.17:04:29.23#ibcon#about to read 4, iclass 33, count 2 2006.173.17:04:29.23#ibcon#read 4, iclass 33, count 2 2006.173.17:04:29.23#ibcon#about to read 5, iclass 33, count 2 2006.173.17:04:29.23#ibcon#read 5, iclass 33, count 2 2006.173.17:04:29.23#ibcon#about to read 6, iclass 33, count 2 2006.173.17:04:29.23#ibcon#read 6, iclass 33, count 2 2006.173.17:04:29.23#ibcon#end of sib2, iclass 33, count 2 2006.173.17:04:29.23#ibcon#*after write, iclass 33, count 2 2006.173.17:04:29.23#ibcon#*before return 0, iclass 33, count 2 2006.173.17:04:29.23#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.17:04:29.23#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.173.17:04:29.23#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.173.17:04:29.23#ibcon#ireg 7 cls_cnt 0 2006.173.17:04:29.23#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.17:04:29.35#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.17:04:29.35#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.17:04:29.35#ibcon#enter wrdev, iclass 33, count 0 2006.173.17:04:29.35#ibcon#first serial, iclass 33, count 0 2006.173.17:04:29.35#ibcon#enter sib2, iclass 33, count 0 2006.173.17:04:29.35#ibcon#flushed, iclass 33, count 0 2006.173.17:04:29.35#ibcon#about to write, iclass 33, count 0 2006.173.17:04:29.35#ibcon#wrote, iclass 33, count 0 2006.173.17:04:29.35#ibcon#about to read 3, iclass 33, count 0 2006.173.17:04:29.37#ibcon#read 3, iclass 33, count 0 2006.173.17:04:29.37#ibcon#about to read 4, iclass 33, count 0 2006.173.17:04:29.37#ibcon#read 4, iclass 33, count 0 2006.173.17:04:29.37#ibcon#about to read 5, iclass 33, count 0 2006.173.17:04:29.37#ibcon#read 5, iclass 33, count 0 2006.173.17:04:29.37#ibcon#about to read 6, iclass 33, count 0 2006.173.17:04:29.37#ibcon#read 6, iclass 33, count 0 2006.173.17:04:29.37#ibcon#end of sib2, iclass 33, count 0 2006.173.17:04:29.37#ibcon#*mode == 0, iclass 33, count 0 2006.173.17:04:29.37#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.17:04:29.37#ibcon#[25=USB\r\n] 2006.173.17:04:29.37#ibcon#*before write, iclass 33, count 0 2006.173.17:04:29.37#ibcon#enter sib2, iclass 33, count 0 2006.173.17:04:29.37#ibcon#flushed, iclass 33, count 0 2006.173.17:04:29.37#ibcon#about to write, iclass 33, count 0 2006.173.17:04:29.37#ibcon#wrote, iclass 33, count 0 2006.173.17:04:29.37#ibcon#about to read 3, iclass 33, count 0 2006.173.17:04:29.40#ibcon#read 3, iclass 33, count 0 2006.173.17:04:29.40#ibcon#about to read 4, iclass 33, count 0 2006.173.17:04:29.40#ibcon#read 4, iclass 33, count 0 2006.173.17:04:29.40#ibcon#about to read 5, iclass 33, count 0 2006.173.17:04:29.40#ibcon#read 5, iclass 33, count 0 2006.173.17:04:29.40#ibcon#about to read 6, iclass 33, count 0 2006.173.17:04:29.40#ibcon#read 6, iclass 33, count 0 2006.173.17:04:29.40#ibcon#end of sib2, iclass 33, count 0 2006.173.17:04:29.40#ibcon#*after write, iclass 33, count 0 2006.173.17:04:29.40#ibcon#*before return 0, iclass 33, count 0 2006.173.17:04:29.40#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.17:04:29.40#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.173.17:04:29.40#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.17:04:29.40#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.17:04:29.40$vck44/valo=5,734.99 2006.173.17:04:29.40#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.17:04:29.40#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.17:04:29.40#ibcon#ireg 17 cls_cnt 0 2006.173.17:04:29.40#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.17:04:29.40#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.17:04:29.40#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.17:04:29.40#ibcon#enter wrdev, iclass 35, count 0 2006.173.17:04:29.40#ibcon#first serial, iclass 35, count 0 2006.173.17:04:29.40#ibcon#enter sib2, iclass 35, count 0 2006.173.17:04:29.40#ibcon#flushed, iclass 35, count 0 2006.173.17:04:29.40#ibcon#about to write, iclass 35, count 0 2006.173.17:04:29.40#ibcon#wrote, iclass 35, count 0 2006.173.17:04:29.40#ibcon#about to read 3, iclass 35, count 0 2006.173.17:04:29.42#ibcon#read 3, iclass 35, count 0 2006.173.17:04:29.42#ibcon#about to read 4, iclass 35, count 0 2006.173.17:04:29.42#ibcon#read 4, iclass 35, count 0 2006.173.17:04:29.42#ibcon#about to read 5, iclass 35, count 0 2006.173.17:04:29.42#ibcon#read 5, iclass 35, count 0 2006.173.17:04:29.42#ibcon#about to read 6, iclass 35, count 0 2006.173.17:04:29.42#ibcon#read 6, iclass 35, count 0 2006.173.17:04:29.42#ibcon#end of sib2, iclass 35, count 0 2006.173.17:04:29.42#ibcon#*mode == 0, iclass 35, count 0 2006.173.17:04:29.42#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.17:04:29.42#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.17:04:29.42#ibcon#*before write, iclass 35, count 0 2006.173.17:04:29.42#ibcon#enter sib2, iclass 35, count 0 2006.173.17:04:29.42#ibcon#flushed, iclass 35, count 0 2006.173.17:04:29.42#ibcon#about to write, iclass 35, count 0 2006.173.17:04:29.42#ibcon#wrote, iclass 35, count 0 2006.173.17:04:29.42#ibcon#about to read 3, iclass 35, count 0 2006.173.17:04:29.46#ibcon#read 3, iclass 35, count 0 2006.173.17:04:29.46#ibcon#about to read 4, iclass 35, count 0 2006.173.17:04:29.46#ibcon#read 4, iclass 35, count 0 2006.173.17:04:29.46#ibcon#about to read 5, iclass 35, count 0 2006.173.17:04:29.46#ibcon#read 5, iclass 35, count 0 2006.173.17:04:29.46#ibcon#about to read 6, iclass 35, count 0 2006.173.17:04:29.46#ibcon#read 6, iclass 35, count 0 2006.173.17:04:29.46#ibcon#end of sib2, iclass 35, count 0 2006.173.17:04:29.46#ibcon#*after write, iclass 35, count 0 2006.173.17:04:29.46#ibcon#*before return 0, iclass 35, count 0 2006.173.17:04:29.46#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.17:04:29.46#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.17:04:29.46#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.17:04:29.46#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.17:04:29.46$vck44/va=5,4 2006.173.17:04:29.46#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.173.17:04:29.46#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.173.17:04:29.46#ibcon#ireg 11 cls_cnt 2 2006.173.17:04:29.46#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.17:04:29.52#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.17:04:29.52#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.17:04:29.52#ibcon#enter wrdev, iclass 37, count 2 2006.173.17:04:29.52#ibcon#first serial, iclass 37, count 2 2006.173.17:04:29.52#ibcon#enter sib2, iclass 37, count 2 2006.173.17:04:29.52#ibcon#flushed, iclass 37, count 2 2006.173.17:04:29.52#ibcon#about to write, iclass 37, count 2 2006.173.17:04:29.52#ibcon#wrote, iclass 37, count 2 2006.173.17:04:29.52#ibcon#about to read 3, iclass 37, count 2 2006.173.17:04:29.54#ibcon#read 3, iclass 37, count 2 2006.173.17:04:29.54#ibcon#about to read 4, iclass 37, count 2 2006.173.17:04:29.54#ibcon#read 4, iclass 37, count 2 2006.173.17:04:29.54#ibcon#about to read 5, iclass 37, count 2 2006.173.17:04:29.54#ibcon#read 5, iclass 37, count 2 2006.173.17:04:29.54#ibcon#about to read 6, iclass 37, count 2 2006.173.17:04:29.54#ibcon#read 6, iclass 37, count 2 2006.173.17:04:29.54#ibcon#end of sib2, iclass 37, count 2 2006.173.17:04:29.54#ibcon#*mode == 0, iclass 37, count 2 2006.173.17:04:29.54#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.173.17:04:29.54#ibcon#[25=AT05-04\r\n] 2006.173.17:04:29.54#ibcon#*before write, iclass 37, count 2 2006.173.17:04:29.54#ibcon#enter sib2, iclass 37, count 2 2006.173.17:04:29.54#ibcon#flushed, iclass 37, count 2 2006.173.17:04:29.54#ibcon#about to write, iclass 37, count 2 2006.173.17:04:29.54#ibcon#wrote, iclass 37, count 2 2006.173.17:04:29.54#ibcon#about to read 3, iclass 37, count 2 2006.173.17:04:29.57#ibcon#read 3, iclass 37, count 2 2006.173.17:04:29.57#ibcon#about to read 4, iclass 37, count 2 2006.173.17:04:29.57#ibcon#read 4, iclass 37, count 2 2006.173.17:04:29.57#ibcon#about to read 5, iclass 37, count 2 2006.173.17:04:29.57#ibcon#read 5, iclass 37, count 2 2006.173.17:04:29.57#ibcon#about to read 6, iclass 37, count 2 2006.173.17:04:29.57#ibcon#read 6, iclass 37, count 2 2006.173.17:04:29.57#ibcon#end of sib2, iclass 37, count 2 2006.173.17:04:29.57#ibcon#*after write, iclass 37, count 2 2006.173.17:04:29.57#ibcon#*before return 0, iclass 37, count 2 2006.173.17:04:29.57#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.17:04:29.57#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.173.17:04:29.57#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.173.17:04:29.57#ibcon#ireg 7 cls_cnt 0 2006.173.17:04:29.57#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.17:04:29.69#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.17:04:29.69#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.17:04:29.69#ibcon#enter wrdev, iclass 37, count 0 2006.173.17:04:29.69#ibcon#first serial, iclass 37, count 0 2006.173.17:04:29.69#ibcon#enter sib2, iclass 37, count 0 2006.173.17:04:29.69#ibcon#flushed, iclass 37, count 0 2006.173.17:04:29.69#ibcon#about to write, iclass 37, count 0 2006.173.17:04:29.69#ibcon#wrote, iclass 37, count 0 2006.173.17:04:29.69#ibcon#about to read 3, iclass 37, count 0 2006.173.17:04:29.71#ibcon#read 3, iclass 37, count 0 2006.173.17:04:29.71#ibcon#about to read 4, iclass 37, count 0 2006.173.17:04:29.71#ibcon#read 4, iclass 37, count 0 2006.173.17:04:29.71#ibcon#about to read 5, iclass 37, count 0 2006.173.17:04:29.71#ibcon#read 5, iclass 37, count 0 2006.173.17:04:29.71#ibcon#about to read 6, iclass 37, count 0 2006.173.17:04:29.71#ibcon#read 6, iclass 37, count 0 2006.173.17:04:29.71#ibcon#end of sib2, iclass 37, count 0 2006.173.17:04:29.71#ibcon#*mode == 0, iclass 37, count 0 2006.173.17:04:29.71#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.17:04:29.71#ibcon#[25=USB\r\n] 2006.173.17:04:29.71#ibcon#*before write, iclass 37, count 0 2006.173.17:04:29.71#ibcon#enter sib2, iclass 37, count 0 2006.173.17:04:29.71#ibcon#flushed, iclass 37, count 0 2006.173.17:04:29.71#ibcon#about to write, iclass 37, count 0 2006.173.17:04:29.71#ibcon#wrote, iclass 37, count 0 2006.173.17:04:29.71#ibcon#about to read 3, iclass 37, count 0 2006.173.17:04:29.74#ibcon#read 3, iclass 37, count 0 2006.173.17:04:29.74#ibcon#about to read 4, iclass 37, count 0 2006.173.17:04:29.74#ibcon#read 4, iclass 37, count 0 2006.173.17:04:29.74#ibcon#about to read 5, iclass 37, count 0 2006.173.17:04:29.74#ibcon#read 5, iclass 37, count 0 2006.173.17:04:29.74#ibcon#about to read 6, iclass 37, count 0 2006.173.17:04:29.74#ibcon#read 6, iclass 37, count 0 2006.173.17:04:29.74#ibcon#end of sib2, iclass 37, count 0 2006.173.17:04:29.74#ibcon#*after write, iclass 37, count 0 2006.173.17:04:29.74#ibcon#*before return 0, iclass 37, count 0 2006.173.17:04:29.74#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.17:04:29.74#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.173.17:04:29.74#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.17:04:29.74#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.17:04:29.74$vck44/valo=6,814.99 2006.173.17:04:29.74#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.17:04:29.74#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.17:04:29.74#ibcon#ireg 17 cls_cnt 0 2006.173.17:04:29.74#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.17:04:29.74#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.17:04:29.74#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.17:04:29.74#ibcon#enter wrdev, iclass 39, count 0 2006.173.17:04:29.74#ibcon#first serial, iclass 39, count 0 2006.173.17:04:29.74#ibcon#enter sib2, iclass 39, count 0 2006.173.17:04:29.74#ibcon#flushed, iclass 39, count 0 2006.173.17:04:29.74#ibcon#about to write, iclass 39, count 0 2006.173.17:04:29.74#ibcon#wrote, iclass 39, count 0 2006.173.17:04:29.74#ibcon#about to read 3, iclass 39, count 0 2006.173.17:04:29.76#ibcon#read 3, iclass 39, count 0 2006.173.17:04:29.76#ibcon#about to read 4, iclass 39, count 0 2006.173.17:04:29.76#ibcon#read 4, iclass 39, count 0 2006.173.17:04:29.76#ibcon#about to read 5, iclass 39, count 0 2006.173.17:04:29.76#ibcon#read 5, iclass 39, count 0 2006.173.17:04:29.76#ibcon#about to read 6, iclass 39, count 0 2006.173.17:04:29.76#ibcon#read 6, iclass 39, count 0 2006.173.17:04:29.76#ibcon#end of sib2, iclass 39, count 0 2006.173.17:04:29.76#ibcon#*mode == 0, iclass 39, count 0 2006.173.17:04:29.76#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.17:04:29.76#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.17:04:29.76#ibcon#*before write, iclass 39, count 0 2006.173.17:04:29.76#ibcon#enter sib2, iclass 39, count 0 2006.173.17:04:29.76#ibcon#flushed, iclass 39, count 0 2006.173.17:04:29.76#ibcon#about to write, iclass 39, count 0 2006.173.17:04:29.76#ibcon#wrote, iclass 39, count 0 2006.173.17:04:29.76#ibcon#about to read 3, iclass 39, count 0 2006.173.17:04:29.80#ibcon#read 3, iclass 39, count 0 2006.173.17:04:29.80#ibcon#about to read 4, iclass 39, count 0 2006.173.17:04:29.80#ibcon#read 4, iclass 39, count 0 2006.173.17:04:29.80#ibcon#about to read 5, iclass 39, count 0 2006.173.17:04:29.80#ibcon#read 5, iclass 39, count 0 2006.173.17:04:29.80#ibcon#about to read 6, iclass 39, count 0 2006.173.17:04:29.80#ibcon#read 6, iclass 39, count 0 2006.173.17:04:29.80#ibcon#end of sib2, iclass 39, count 0 2006.173.17:04:29.80#ibcon#*after write, iclass 39, count 0 2006.173.17:04:29.80#ibcon#*before return 0, iclass 39, count 0 2006.173.17:04:29.80#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.17:04:29.80#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.17:04:29.80#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.17:04:29.80#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.17:04:29.80$vck44/va=6,3 2006.173.17:04:29.80#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.17:04:29.80#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.17:04:29.80#ibcon#ireg 11 cls_cnt 2 2006.173.17:04:29.80#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.17:04:29.86#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.17:04:29.86#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.17:04:29.86#ibcon#enter wrdev, iclass 3, count 2 2006.173.17:04:29.86#ibcon#first serial, iclass 3, count 2 2006.173.17:04:29.86#ibcon#enter sib2, iclass 3, count 2 2006.173.17:04:29.86#ibcon#flushed, iclass 3, count 2 2006.173.17:04:29.86#ibcon#about to write, iclass 3, count 2 2006.173.17:04:29.86#ibcon#wrote, iclass 3, count 2 2006.173.17:04:29.86#ibcon#about to read 3, iclass 3, count 2 2006.173.17:04:29.88#ibcon#read 3, iclass 3, count 2 2006.173.17:04:29.88#ibcon#about to read 4, iclass 3, count 2 2006.173.17:04:29.88#ibcon#read 4, iclass 3, count 2 2006.173.17:04:29.88#ibcon#about to read 5, iclass 3, count 2 2006.173.17:04:29.88#ibcon#read 5, iclass 3, count 2 2006.173.17:04:29.88#ibcon#about to read 6, iclass 3, count 2 2006.173.17:04:29.88#ibcon#read 6, iclass 3, count 2 2006.173.17:04:29.88#ibcon#end of sib2, iclass 3, count 2 2006.173.17:04:29.88#ibcon#*mode == 0, iclass 3, count 2 2006.173.17:04:29.88#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.17:04:29.88#ibcon#[25=AT06-03\r\n] 2006.173.17:04:29.88#ibcon#*before write, iclass 3, count 2 2006.173.17:04:29.88#ibcon#enter sib2, iclass 3, count 2 2006.173.17:04:29.88#ibcon#flushed, iclass 3, count 2 2006.173.17:04:29.88#ibcon#about to write, iclass 3, count 2 2006.173.17:04:29.88#ibcon#wrote, iclass 3, count 2 2006.173.17:04:29.88#ibcon#about to read 3, iclass 3, count 2 2006.173.17:04:29.91#ibcon#read 3, iclass 3, count 2 2006.173.17:04:29.91#ibcon#about to read 4, iclass 3, count 2 2006.173.17:04:29.91#ibcon#read 4, iclass 3, count 2 2006.173.17:04:29.91#ibcon#about to read 5, iclass 3, count 2 2006.173.17:04:29.91#ibcon#read 5, iclass 3, count 2 2006.173.17:04:29.91#ibcon#about to read 6, iclass 3, count 2 2006.173.17:04:29.91#ibcon#read 6, iclass 3, count 2 2006.173.17:04:29.91#ibcon#end of sib2, iclass 3, count 2 2006.173.17:04:29.91#ibcon#*after write, iclass 3, count 2 2006.173.17:04:29.91#ibcon#*before return 0, iclass 3, count 2 2006.173.17:04:29.91#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.17:04:29.91#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.17:04:29.91#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.17:04:29.91#ibcon#ireg 7 cls_cnt 0 2006.173.17:04:29.91#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.17:04:30.03#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.17:04:30.03#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.17:04:30.03#ibcon#enter wrdev, iclass 3, count 0 2006.173.17:04:30.03#ibcon#first serial, iclass 3, count 0 2006.173.17:04:30.03#ibcon#enter sib2, iclass 3, count 0 2006.173.17:04:30.03#ibcon#flushed, iclass 3, count 0 2006.173.17:04:30.03#ibcon#about to write, iclass 3, count 0 2006.173.17:04:30.03#ibcon#wrote, iclass 3, count 0 2006.173.17:04:30.03#ibcon#about to read 3, iclass 3, count 0 2006.173.17:04:30.05#ibcon#read 3, iclass 3, count 0 2006.173.17:04:30.05#ibcon#about to read 4, iclass 3, count 0 2006.173.17:04:30.05#ibcon#read 4, iclass 3, count 0 2006.173.17:04:30.05#ibcon#about to read 5, iclass 3, count 0 2006.173.17:04:30.05#ibcon#read 5, iclass 3, count 0 2006.173.17:04:30.05#ibcon#about to read 6, iclass 3, count 0 2006.173.17:04:30.05#ibcon#read 6, iclass 3, count 0 2006.173.17:04:30.05#ibcon#end of sib2, iclass 3, count 0 2006.173.17:04:30.05#ibcon#*mode == 0, iclass 3, count 0 2006.173.17:04:30.05#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.17:04:30.05#ibcon#[25=USB\r\n] 2006.173.17:04:30.05#ibcon#*before write, iclass 3, count 0 2006.173.17:04:30.05#ibcon#enter sib2, iclass 3, count 0 2006.173.17:04:30.05#ibcon#flushed, iclass 3, count 0 2006.173.17:04:30.05#ibcon#about to write, iclass 3, count 0 2006.173.17:04:30.05#ibcon#wrote, iclass 3, count 0 2006.173.17:04:30.05#ibcon#about to read 3, iclass 3, count 0 2006.173.17:04:30.08#ibcon#read 3, iclass 3, count 0 2006.173.17:04:30.08#ibcon#about to read 4, iclass 3, count 0 2006.173.17:04:30.08#ibcon#read 4, iclass 3, count 0 2006.173.17:04:30.08#ibcon#about to read 5, iclass 3, count 0 2006.173.17:04:30.08#ibcon#read 5, iclass 3, count 0 2006.173.17:04:30.08#ibcon#about to read 6, iclass 3, count 0 2006.173.17:04:30.08#ibcon#read 6, iclass 3, count 0 2006.173.17:04:30.08#ibcon#end of sib2, iclass 3, count 0 2006.173.17:04:30.08#ibcon#*after write, iclass 3, count 0 2006.173.17:04:30.08#ibcon#*before return 0, iclass 3, count 0 2006.173.17:04:30.08#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.17:04:30.08#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.17:04:30.08#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.17:04:30.08#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.17:04:30.08$vck44/valo=7,864.99 2006.173.17:04:30.08#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.17:04:30.08#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.17:04:30.08#ibcon#ireg 17 cls_cnt 0 2006.173.17:04:30.08#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.17:04:30.08#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.17:04:30.08#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.17:04:30.08#ibcon#enter wrdev, iclass 5, count 0 2006.173.17:04:30.08#ibcon#first serial, iclass 5, count 0 2006.173.17:04:30.08#ibcon#enter sib2, iclass 5, count 0 2006.173.17:04:30.08#ibcon#flushed, iclass 5, count 0 2006.173.17:04:30.08#ibcon#about to write, iclass 5, count 0 2006.173.17:04:30.08#ibcon#wrote, iclass 5, count 0 2006.173.17:04:30.08#ibcon#about to read 3, iclass 5, count 0 2006.173.17:04:30.10#ibcon#read 3, iclass 5, count 0 2006.173.17:04:30.10#ibcon#about to read 4, iclass 5, count 0 2006.173.17:04:30.10#ibcon#read 4, iclass 5, count 0 2006.173.17:04:30.10#ibcon#about to read 5, iclass 5, count 0 2006.173.17:04:30.10#ibcon#read 5, iclass 5, count 0 2006.173.17:04:30.10#ibcon#about to read 6, iclass 5, count 0 2006.173.17:04:30.10#ibcon#read 6, iclass 5, count 0 2006.173.17:04:30.10#ibcon#end of sib2, iclass 5, count 0 2006.173.17:04:30.10#ibcon#*mode == 0, iclass 5, count 0 2006.173.17:04:30.10#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.17:04:30.10#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.17:04:30.10#ibcon#*before write, iclass 5, count 0 2006.173.17:04:30.10#ibcon#enter sib2, iclass 5, count 0 2006.173.17:04:30.10#ibcon#flushed, iclass 5, count 0 2006.173.17:04:30.10#ibcon#about to write, iclass 5, count 0 2006.173.17:04:30.10#ibcon#wrote, iclass 5, count 0 2006.173.17:04:30.10#ibcon#about to read 3, iclass 5, count 0 2006.173.17:04:30.14#ibcon#read 3, iclass 5, count 0 2006.173.17:04:30.14#ibcon#about to read 4, iclass 5, count 0 2006.173.17:04:30.14#ibcon#read 4, iclass 5, count 0 2006.173.17:04:30.14#ibcon#about to read 5, iclass 5, count 0 2006.173.17:04:30.14#ibcon#read 5, iclass 5, count 0 2006.173.17:04:30.14#ibcon#about to read 6, iclass 5, count 0 2006.173.17:04:30.14#ibcon#read 6, iclass 5, count 0 2006.173.17:04:30.14#ibcon#end of sib2, iclass 5, count 0 2006.173.17:04:30.14#ibcon#*after write, iclass 5, count 0 2006.173.17:04:30.14#ibcon#*before return 0, iclass 5, count 0 2006.173.17:04:30.14#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.17:04:30.14#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.17:04:30.14#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.17:04:30.14#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.17:04:30.14$vck44/va=7,4 2006.173.17:04:30.14#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.173.17:04:30.14#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.173.17:04:30.14#ibcon#ireg 11 cls_cnt 2 2006.173.17:04:30.14#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.17:04:30.20#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.17:04:30.20#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.17:04:30.20#ibcon#enter wrdev, iclass 7, count 2 2006.173.17:04:30.20#ibcon#first serial, iclass 7, count 2 2006.173.17:04:30.20#ibcon#enter sib2, iclass 7, count 2 2006.173.17:04:30.20#ibcon#flushed, iclass 7, count 2 2006.173.17:04:30.20#ibcon#about to write, iclass 7, count 2 2006.173.17:04:30.20#ibcon#wrote, iclass 7, count 2 2006.173.17:04:30.20#ibcon#about to read 3, iclass 7, count 2 2006.173.17:04:30.22#ibcon#read 3, iclass 7, count 2 2006.173.17:04:30.22#ibcon#about to read 4, iclass 7, count 2 2006.173.17:04:30.22#ibcon#read 4, iclass 7, count 2 2006.173.17:04:30.22#ibcon#about to read 5, iclass 7, count 2 2006.173.17:04:30.22#ibcon#read 5, iclass 7, count 2 2006.173.17:04:30.22#ibcon#about to read 6, iclass 7, count 2 2006.173.17:04:30.22#ibcon#read 6, iclass 7, count 2 2006.173.17:04:30.22#ibcon#end of sib2, iclass 7, count 2 2006.173.17:04:30.22#ibcon#*mode == 0, iclass 7, count 2 2006.173.17:04:30.22#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.173.17:04:30.22#ibcon#[25=AT07-04\r\n] 2006.173.17:04:30.22#ibcon#*before write, iclass 7, count 2 2006.173.17:04:30.22#ibcon#enter sib2, iclass 7, count 2 2006.173.17:04:30.22#ibcon#flushed, iclass 7, count 2 2006.173.17:04:30.22#ibcon#about to write, iclass 7, count 2 2006.173.17:04:30.22#ibcon#wrote, iclass 7, count 2 2006.173.17:04:30.22#ibcon#about to read 3, iclass 7, count 2 2006.173.17:04:30.25#ibcon#read 3, iclass 7, count 2 2006.173.17:04:30.25#ibcon#about to read 4, iclass 7, count 2 2006.173.17:04:30.25#ibcon#read 4, iclass 7, count 2 2006.173.17:04:30.25#ibcon#about to read 5, iclass 7, count 2 2006.173.17:04:30.25#ibcon#read 5, iclass 7, count 2 2006.173.17:04:30.25#ibcon#about to read 6, iclass 7, count 2 2006.173.17:04:30.25#ibcon#read 6, iclass 7, count 2 2006.173.17:04:30.25#ibcon#end of sib2, iclass 7, count 2 2006.173.17:04:30.25#ibcon#*after write, iclass 7, count 2 2006.173.17:04:30.25#ibcon#*before return 0, iclass 7, count 2 2006.173.17:04:30.25#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.17:04:30.25#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.173.17:04:30.25#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.173.17:04:30.25#ibcon#ireg 7 cls_cnt 0 2006.173.17:04:30.25#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.17:04:30.37#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.17:04:30.37#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.17:04:30.37#ibcon#enter wrdev, iclass 7, count 0 2006.173.17:04:30.37#ibcon#first serial, iclass 7, count 0 2006.173.17:04:30.37#ibcon#enter sib2, iclass 7, count 0 2006.173.17:04:30.37#ibcon#flushed, iclass 7, count 0 2006.173.17:04:30.37#ibcon#about to write, iclass 7, count 0 2006.173.17:04:30.37#ibcon#wrote, iclass 7, count 0 2006.173.17:04:30.37#ibcon#about to read 3, iclass 7, count 0 2006.173.17:04:30.39#ibcon#read 3, iclass 7, count 0 2006.173.17:04:30.39#ibcon#about to read 4, iclass 7, count 0 2006.173.17:04:30.39#ibcon#read 4, iclass 7, count 0 2006.173.17:04:30.39#ibcon#about to read 5, iclass 7, count 0 2006.173.17:04:30.39#ibcon#read 5, iclass 7, count 0 2006.173.17:04:30.39#ibcon#about to read 6, iclass 7, count 0 2006.173.17:04:30.39#ibcon#read 6, iclass 7, count 0 2006.173.17:04:30.39#ibcon#end of sib2, iclass 7, count 0 2006.173.17:04:30.39#ibcon#*mode == 0, iclass 7, count 0 2006.173.17:04:30.39#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.17:04:30.39#ibcon#[25=USB\r\n] 2006.173.17:04:30.39#ibcon#*before write, iclass 7, count 0 2006.173.17:04:30.39#ibcon#enter sib2, iclass 7, count 0 2006.173.17:04:30.39#ibcon#flushed, iclass 7, count 0 2006.173.17:04:30.39#ibcon#about to write, iclass 7, count 0 2006.173.17:04:30.39#ibcon#wrote, iclass 7, count 0 2006.173.17:04:30.39#ibcon#about to read 3, iclass 7, count 0 2006.173.17:04:30.42#ibcon#read 3, iclass 7, count 0 2006.173.17:04:30.42#ibcon#about to read 4, iclass 7, count 0 2006.173.17:04:30.42#ibcon#read 4, iclass 7, count 0 2006.173.17:04:30.42#ibcon#about to read 5, iclass 7, count 0 2006.173.17:04:30.42#ibcon#read 5, iclass 7, count 0 2006.173.17:04:30.42#ibcon#about to read 6, iclass 7, count 0 2006.173.17:04:30.42#ibcon#read 6, iclass 7, count 0 2006.173.17:04:30.42#ibcon#end of sib2, iclass 7, count 0 2006.173.17:04:30.42#ibcon#*after write, iclass 7, count 0 2006.173.17:04:30.42#ibcon#*before return 0, iclass 7, count 0 2006.173.17:04:30.42#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.17:04:30.42#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.173.17:04:30.42#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.17:04:30.42#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.17:04:30.42$vck44/valo=8,884.99 2006.173.17:04:30.42#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.17:04:30.42#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.17:04:30.42#ibcon#ireg 17 cls_cnt 0 2006.173.17:04:30.42#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.17:04:30.42#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.17:04:30.42#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.17:04:30.42#ibcon#enter wrdev, iclass 11, count 0 2006.173.17:04:30.42#ibcon#first serial, iclass 11, count 0 2006.173.17:04:30.42#ibcon#enter sib2, iclass 11, count 0 2006.173.17:04:30.42#ibcon#flushed, iclass 11, count 0 2006.173.17:04:30.42#ibcon#about to write, iclass 11, count 0 2006.173.17:04:30.42#ibcon#wrote, iclass 11, count 0 2006.173.17:04:30.42#ibcon#about to read 3, iclass 11, count 0 2006.173.17:04:30.44#ibcon#read 3, iclass 11, count 0 2006.173.17:04:30.44#ibcon#about to read 4, iclass 11, count 0 2006.173.17:04:30.44#ibcon#read 4, iclass 11, count 0 2006.173.17:04:30.44#ibcon#about to read 5, iclass 11, count 0 2006.173.17:04:30.44#ibcon#read 5, iclass 11, count 0 2006.173.17:04:30.44#ibcon#about to read 6, iclass 11, count 0 2006.173.17:04:30.44#ibcon#read 6, iclass 11, count 0 2006.173.17:04:30.44#ibcon#end of sib2, iclass 11, count 0 2006.173.17:04:30.44#ibcon#*mode == 0, iclass 11, count 0 2006.173.17:04:30.44#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.17:04:30.44#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.17:04:30.44#ibcon#*before write, iclass 11, count 0 2006.173.17:04:30.44#ibcon#enter sib2, iclass 11, count 0 2006.173.17:04:30.44#ibcon#flushed, iclass 11, count 0 2006.173.17:04:30.44#ibcon#about to write, iclass 11, count 0 2006.173.17:04:30.44#ibcon#wrote, iclass 11, count 0 2006.173.17:04:30.44#ibcon#about to read 3, iclass 11, count 0 2006.173.17:04:30.48#ibcon#read 3, iclass 11, count 0 2006.173.17:04:30.48#ibcon#about to read 4, iclass 11, count 0 2006.173.17:04:30.48#ibcon#read 4, iclass 11, count 0 2006.173.17:04:30.48#ibcon#about to read 5, iclass 11, count 0 2006.173.17:04:30.48#ibcon#read 5, iclass 11, count 0 2006.173.17:04:30.48#ibcon#about to read 6, iclass 11, count 0 2006.173.17:04:30.48#ibcon#read 6, iclass 11, count 0 2006.173.17:04:30.48#ibcon#end of sib2, iclass 11, count 0 2006.173.17:04:30.48#ibcon#*after write, iclass 11, count 0 2006.173.17:04:30.48#ibcon#*before return 0, iclass 11, count 0 2006.173.17:04:30.48#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.17:04:30.48#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.17:04:30.48#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.17:04:30.48#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.17:04:30.48$vck44/va=8,4 2006.173.17:04:30.48#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.173.17:04:30.48#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.173.17:04:30.48#ibcon#ireg 11 cls_cnt 2 2006.173.17:04:30.48#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.17:04:30.54#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.17:04:30.54#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.17:04:30.54#ibcon#enter wrdev, iclass 13, count 2 2006.173.17:04:30.54#ibcon#first serial, iclass 13, count 2 2006.173.17:04:30.54#ibcon#enter sib2, iclass 13, count 2 2006.173.17:04:30.54#ibcon#flushed, iclass 13, count 2 2006.173.17:04:30.54#ibcon#about to write, iclass 13, count 2 2006.173.17:04:30.54#ibcon#wrote, iclass 13, count 2 2006.173.17:04:30.54#ibcon#about to read 3, iclass 13, count 2 2006.173.17:04:30.56#ibcon#read 3, iclass 13, count 2 2006.173.17:04:30.56#ibcon#about to read 4, iclass 13, count 2 2006.173.17:04:30.56#ibcon#read 4, iclass 13, count 2 2006.173.17:04:30.56#ibcon#about to read 5, iclass 13, count 2 2006.173.17:04:30.56#ibcon#read 5, iclass 13, count 2 2006.173.17:04:30.56#ibcon#about to read 6, iclass 13, count 2 2006.173.17:04:30.56#ibcon#read 6, iclass 13, count 2 2006.173.17:04:30.56#ibcon#end of sib2, iclass 13, count 2 2006.173.17:04:30.56#ibcon#*mode == 0, iclass 13, count 2 2006.173.17:04:30.56#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.173.17:04:30.56#ibcon#[25=AT08-04\r\n] 2006.173.17:04:30.56#ibcon#*before write, iclass 13, count 2 2006.173.17:04:30.56#ibcon#enter sib2, iclass 13, count 2 2006.173.17:04:30.56#ibcon#flushed, iclass 13, count 2 2006.173.17:04:30.56#ibcon#about to write, iclass 13, count 2 2006.173.17:04:30.56#ibcon#wrote, iclass 13, count 2 2006.173.17:04:30.56#ibcon#about to read 3, iclass 13, count 2 2006.173.17:04:30.59#ibcon#read 3, iclass 13, count 2 2006.173.17:04:30.59#ibcon#about to read 4, iclass 13, count 2 2006.173.17:04:30.59#ibcon#read 4, iclass 13, count 2 2006.173.17:04:30.59#ibcon#about to read 5, iclass 13, count 2 2006.173.17:04:30.59#ibcon#read 5, iclass 13, count 2 2006.173.17:04:30.59#ibcon#about to read 6, iclass 13, count 2 2006.173.17:04:30.59#ibcon#read 6, iclass 13, count 2 2006.173.17:04:30.59#ibcon#end of sib2, iclass 13, count 2 2006.173.17:04:30.59#ibcon#*after write, iclass 13, count 2 2006.173.17:04:30.59#ibcon#*before return 0, iclass 13, count 2 2006.173.17:04:30.59#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.17:04:30.59#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.173.17:04:30.59#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.173.17:04:30.59#ibcon#ireg 7 cls_cnt 0 2006.173.17:04:30.59#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.17:04:30.71#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.17:04:30.71#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.17:04:30.71#ibcon#enter wrdev, iclass 13, count 0 2006.173.17:04:30.71#ibcon#first serial, iclass 13, count 0 2006.173.17:04:30.71#ibcon#enter sib2, iclass 13, count 0 2006.173.17:04:30.71#ibcon#flushed, iclass 13, count 0 2006.173.17:04:30.71#ibcon#about to write, iclass 13, count 0 2006.173.17:04:30.71#ibcon#wrote, iclass 13, count 0 2006.173.17:04:30.71#ibcon#about to read 3, iclass 13, count 0 2006.173.17:04:30.73#ibcon#read 3, iclass 13, count 0 2006.173.17:04:30.73#ibcon#about to read 4, iclass 13, count 0 2006.173.17:04:30.73#ibcon#read 4, iclass 13, count 0 2006.173.17:04:30.73#ibcon#about to read 5, iclass 13, count 0 2006.173.17:04:30.73#ibcon#read 5, iclass 13, count 0 2006.173.17:04:30.73#ibcon#about to read 6, iclass 13, count 0 2006.173.17:04:30.73#ibcon#read 6, iclass 13, count 0 2006.173.17:04:30.73#ibcon#end of sib2, iclass 13, count 0 2006.173.17:04:30.73#ibcon#*mode == 0, iclass 13, count 0 2006.173.17:04:30.73#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.17:04:30.73#ibcon#[25=USB\r\n] 2006.173.17:04:30.73#ibcon#*before write, iclass 13, count 0 2006.173.17:04:30.73#ibcon#enter sib2, iclass 13, count 0 2006.173.17:04:30.73#ibcon#flushed, iclass 13, count 0 2006.173.17:04:30.73#ibcon#about to write, iclass 13, count 0 2006.173.17:04:30.73#ibcon#wrote, iclass 13, count 0 2006.173.17:04:30.73#ibcon#about to read 3, iclass 13, count 0 2006.173.17:04:30.76#ibcon#read 3, iclass 13, count 0 2006.173.17:04:30.76#ibcon#about to read 4, iclass 13, count 0 2006.173.17:04:30.76#ibcon#read 4, iclass 13, count 0 2006.173.17:04:30.76#ibcon#about to read 5, iclass 13, count 0 2006.173.17:04:30.76#ibcon#read 5, iclass 13, count 0 2006.173.17:04:30.76#ibcon#about to read 6, iclass 13, count 0 2006.173.17:04:30.76#ibcon#read 6, iclass 13, count 0 2006.173.17:04:30.76#ibcon#end of sib2, iclass 13, count 0 2006.173.17:04:30.76#ibcon#*after write, iclass 13, count 0 2006.173.17:04:30.76#ibcon#*before return 0, iclass 13, count 0 2006.173.17:04:30.76#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.17:04:30.76#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.173.17:04:30.76#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.17:04:30.76#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.17:04:30.76$vck44/vblo=1,629.99 2006.173.17:04:30.76#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.17:04:30.76#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.17:04:30.76#ibcon#ireg 17 cls_cnt 0 2006.173.17:04:30.76#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.17:04:30.76#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.17:04:30.76#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.17:04:30.76#ibcon#enter wrdev, iclass 15, count 0 2006.173.17:04:30.76#ibcon#first serial, iclass 15, count 0 2006.173.17:04:30.76#ibcon#enter sib2, iclass 15, count 0 2006.173.17:04:30.76#ibcon#flushed, iclass 15, count 0 2006.173.17:04:30.76#ibcon#about to write, iclass 15, count 0 2006.173.17:04:30.76#ibcon#wrote, iclass 15, count 0 2006.173.17:04:30.76#ibcon#about to read 3, iclass 15, count 0 2006.173.17:04:30.78#ibcon#read 3, iclass 15, count 0 2006.173.17:04:30.78#ibcon#about to read 4, iclass 15, count 0 2006.173.17:04:30.78#ibcon#read 4, iclass 15, count 0 2006.173.17:04:30.78#ibcon#about to read 5, iclass 15, count 0 2006.173.17:04:30.78#ibcon#read 5, iclass 15, count 0 2006.173.17:04:30.78#ibcon#about to read 6, iclass 15, count 0 2006.173.17:04:30.78#ibcon#read 6, iclass 15, count 0 2006.173.17:04:30.78#ibcon#end of sib2, iclass 15, count 0 2006.173.17:04:30.78#ibcon#*mode == 0, iclass 15, count 0 2006.173.17:04:30.78#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.17:04:30.78#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.17:04:30.78#ibcon#*before write, iclass 15, count 0 2006.173.17:04:30.78#ibcon#enter sib2, iclass 15, count 0 2006.173.17:04:30.78#ibcon#flushed, iclass 15, count 0 2006.173.17:04:30.78#ibcon#about to write, iclass 15, count 0 2006.173.17:04:30.78#ibcon#wrote, iclass 15, count 0 2006.173.17:04:30.78#ibcon#about to read 3, iclass 15, count 0 2006.173.17:04:30.82#ibcon#read 3, iclass 15, count 0 2006.173.17:04:30.82#ibcon#about to read 4, iclass 15, count 0 2006.173.17:04:30.82#ibcon#read 4, iclass 15, count 0 2006.173.17:04:30.82#ibcon#about to read 5, iclass 15, count 0 2006.173.17:04:30.82#ibcon#read 5, iclass 15, count 0 2006.173.17:04:30.82#ibcon#about to read 6, iclass 15, count 0 2006.173.17:04:30.82#ibcon#read 6, iclass 15, count 0 2006.173.17:04:30.82#ibcon#end of sib2, iclass 15, count 0 2006.173.17:04:30.82#ibcon#*after write, iclass 15, count 0 2006.173.17:04:30.82#ibcon#*before return 0, iclass 15, count 0 2006.173.17:04:30.82#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.17:04:30.82#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.17:04:30.82#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.17:04:30.82#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.17:04:30.82$vck44/vb=1,4 2006.173.17:04:30.82#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.17:04:30.82#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.17:04:30.82#ibcon#ireg 11 cls_cnt 2 2006.173.17:04:30.82#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.17:04:30.82#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.17:04:30.82#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.17:04:30.82#ibcon#enter wrdev, iclass 17, count 2 2006.173.17:04:30.82#ibcon#first serial, iclass 17, count 2 2006.173.17:04:30.82#ibcon#enter sib2, iclass 17, count 2 2006.173.17:04:30.82#ibcon#flushed, iclass 17, count 2 2006.173.17:04:30.82#ibcon#about to write, iclass 17, count 2 2006.173.17:04:30.82#ibcon#wrote, iclass 17, count 2 2006.173.17:04:30.82#ibcon#about to read 3, iclass 17, count 2 2006.173.17:04:30.84#ibcon#read 3, iclass 17, count 2 2006.173.17:04:30.84#ibcon#about to read 4, iclass 17, count 2 2006.173.17:04:30.84#ibcon#read 4, iclass 17, count 2 2006.173.17:04:30.84#ibcon#about to read 5, iclass 17, count 2 2006.173.17:04:30.84#ibcon#read 5, iclass 17, count 2 2006.173.17:04:30.84#ibcon#about to read 6, iclass 17, count 2 2006.173.17:04:30.84#ibcon#read 6, iclass 17, count 2 2006.173.17:04:30.84#ibcon#end of sib2, iclass 17, count 2 2006.173.17:04:30.84#ibcon#*mode == 0, iclass 17, count 2 2006.173.17:04:30.84#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.17:04:30.84#ibcon#[27=AT01-04\r\n] 2006.173.17:04:30.84#ibcon#*before write, iclass 17, count 2 2006.173.17:04:30.84#ibcon#enter sib2, iclass 17, count 2 2006.173.17:04:30.84#ibcon#flushed, iclass 17, count 2 2006.173.17:04:30.84#ibcon#about to write, iclass 17, count 2 2006.173.17:04:30.84#ibcon#wrote, iclass 17, count 2 2006.173.17:04:30.84#ibcon#about to read 3, iclass 17, count 2 2006.173.17:04:30.87#ibcon#read 3, iclass 17, count 2 2006.173.17:04:30.87#ibcon#about to read 4, iclass 17, count 2 2006.173.17:04:30.87#ibcon#read 4, iclass 17, count 2 2006.173.17:04:30.87#ibcon#about to read 5, iclass 17, count 2 2006.173.17:04:30.87#ibcon#read 5, iclass 17, count 2 2006.173.17:04:30.87#ibcon#about to read 6, iclass 17, count 2 2006.173.17:04:30.87#ibcon#read 6, iclass 17, count 2 2006.173.17:04:30.87#ibcon#end of sib2, iclass 17, count 2 2006.173.17:04:30.87#ibcon#*after write, iclass 17, count 2 2006.173.17:04:30.87#ibcon#*before return 0, iclass 17, count 2 2006.173.17:04:30.87#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.17:04:30.87#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.17:04:30.87#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.17:04:30.87#ibcon#ireg 7 cls_cnt 0 2006.173.17:04:30.87#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.17:04:30.99#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.17:04:30.99#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.17:04:30.99#ibcon#enter wrdev, iclass 17, count 0 2006.173.17:04:30.99#ibcon#first serial, iclass 17, count 0 2006.173.17:04:30.99#ibcon#enter sib2, iclass 17, count 0 2006.173.17:04:30.99#ibcon#flushed, iclass 17, count 0 2006.173.17:04:30.99#ibcon#about to write, iclass 17, count 0 2006.173.17:04:30.99#ibcon#wrote, iclass 17, count 0 2006.173.17:04:30.99#ibcon#about to read 3, iclass 17, count 0 2006.173.17:04:31.01#ibcon#read 3, iclass 17, count 0 2006.173.17:04:31.01#ibcon#about to read 4, iclass 17, count 0 2006.173.17:04:31.01#ibcon#read 4, iclass 17, count 0 2006.173.17:04:31.01#ibcon#about to read 5, iclass 17, count 0 2006.173.17:04:31.01#ibcon#read 5, iclass 17, count 0 2006.173.17:04:31.01#ibcon#about to read 6, iclass 17, count 0 2006.173.17:04:31.01#ibcon#read 6, iclass 17, count 0 2006.173.17:04:31.01#ibcon#end of sib2, iclass 17, count 0 2006.173.17:04:31.01#ibcon#*mode == 0, iclass 17, count 0 2006.173.17:04:31.01#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.17:04:31.01#ibcon#[27=USB\r\n] 2006.173.17:04:31.01#ibcon#*before write, iclass 17, count 0 2006.173.17:04:31.01#ibcon#enter sib2, iclass 17, count 0 2006.173.17:04:31.01#ibcon#flushed, iclass 17, count 0 2006.173.17:04:31.01#ibcon#about to write, iclass 17, count 0 2006.173.17:04:31.01#ibcon#wrote, iclass 17, count 0 2006.173.17:04:31.01#ibcon#about to read 3, iclass 17, count 0 2006.173.17:04:31.04#ibcon#read 3, iclass 17, count 0 2006.173.17:04:31.04#ibcon#about to read 4, iclass 17, count 0 2006.173.17:04:31.04#ibcon#read 4, iclass 17, count 0 2006.173.17:04:31.04#ibcon#about to read 5, iclass 17, count 0 2006.173.17:04:31.04#ibcon#read 5, iclass 17, count 0 2006.173.17:04:31.04#ibcon#about to read 6, iclass 17, count 0 2006.173.17:04:31.04#ibcon#read 6, iclass 17, count 0 2006.173.17:04:31.04#ibcon#end of sib2, iclass 17, count 0 2006.173.17:04:31.04#ibcon#*after write, iclass 17, count 0 2006.173.17:04:31.04#ibcon#*before return 0, iclass 17, count 0 2006.173.17:04:31.04#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.17:04:31.04#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.17:04:31.04#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.17:04:31.04#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.17:04:31.04$vck44/vblo=2,634.99 2006.173.17:04:31.04#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.17:04:31.04#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.17:04:31.04#ibcon#ireg 17 cls_cnt 0 2006.173.17:04:31.04#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.17:04:31.04#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.17:04:31.04#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.17:04:31.04#ibcon#enter wrdev, iclass 19, count 0 2006.173.17:04:31.04#ibcon#first serial, iclass 19, count 0 2006.173.17:04:31.04#ibcon#enter sib2, iclass 19, count 0 2006.173.17:04:31.04#ibcon#flushed, iclass 19, count 0 2006.173.17:04:31.04#ibcon#about to write, iclass 19, count 0 2006.173.17:04:31.04#ibcon#wrote, iclass 19, count 0 2006.173.17:04:31.04#ibcon#about to read 3, iclass 19, count 0 2006.173.17:04:31.06#ibcon#read 3, iclass 19, count 0 2006.173.17:04:31.06#ibcon#about to read 4, iclass 19, count 0 2006.173.17:04:31.06#ibcon#read 4, iclass 19, count 0 2006.173.17:04:31.06#ibcon#about to read 5, iclass 19, count 0 2006.173.17:04:31.06#ibcon#read 5, iclass 19, count 0 2006.173.17:04:31.06#ibcon#about to read 6, iclass 19, count 0 2006.173.17:04:31.06#ibcon#read 6, iclass 19, count 0 2006.173.17:04:31.06#ibcon#end of sib2, iclass 19, count 0 2006.173.17:04:31.06#ibcon#*mode == 0, iclass 19, count 0 2006.173.17:04:31.06#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.17:04:31.06#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.17:04:31.06#ibcon#*before write, iclass 19, count 0 2006.173.17:04:31.06#ibcon#enter sib2, iclass 19, count 0 2006.173.17:04:31.06#ibcon#flushed, iclass 19, count 0 2006.173.17:04:31.06#ibcon#about to write, iclass 19, count 0 2006.173.17:04:31.06#ibcon#wrote, iclass 19, count 0 2006.173.17:04:31.06#ibcon#about to read 3, iclass 19, count 0 2006.173.17:04:31.10#ibcon#read 3, iclass 19, count 0 2006.173.17:04:31.10#ibcon#about to read 4, iclass 19, count 0 2006.173.17:04:31.10#ibcon#read 4, iclass 19, count 0 2006.173.17:04:31.10#ibcon#about to read 5, iclass 19, count 0 2006.173.17:04:31.10#ibcon#read 5, iclass 19, count 0 2006.173.17:04:31.10#ibcon#about to read 6, iclass 19, count 0 2006.173.17:04:31.10#ibcon#read 6, iclass 19, count 0 2006.173.17:04:31.10#ibcon#end of sib2, iclass 19, count 0 2006.173.17:04:31.10#ibcon#*after write, iclass 19, count 0 2006.173.17:04:31.10#ibcon#*before return 0, iclass 19, count 0 2006.173.17:04:31.10#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.17:04:31.10#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.17:04:31.10#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.17:04:31.10#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.17:04:31.10$vck44/vb=2,4 2006.173.17:04:31.10#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.17:04:31.10#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.17:04:31.10#ibcon#ireg 11 cls_cnt 2 2006.173.17:04:31.10#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.17:04:31.16#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.17:04:31.16#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.17:04:31.16#ibcon#enter wrdev, iclass 21, count 2 2006.173.17:04:31.16#ibcon#first serial, iclass 21, count 2 2006.173.17:04:31.16#ibcon#enter sib2, iclass 21, count 2 2006.173.17:04:31.16#ibcon#flushed, iclass 21, count 2 2006.173.17:04:31.16#ibcon#about to write, iclass 21, count 2 2006.173.17:04:31.16#ibcon#wrote, iclass 21, count 2 2006.173.17:04:31.16#ibcon#about to read 3, iclass 21, count 2 2006.173.17:04:31.18#ibcon#read 3, iclass 21, count 2 2006.173.17:04:31.18#ibcon#about to read 4, iclass 21, count 2 2006.173.17:04:31.18#ibcon#read 4, iclass 21, count 2 2006.173.17:04:31.18#ibcon#about to read 5, iclass 21, count 2 2006.173.17:04:31.18#ibcon#read 5, iclass 21, count 2 2006.173.17:04:31.18#ibcon#about to read 6, iclass 21, count 2 2006.173.17:04:31.18#ibcon#read 6, iclass 21, count 2 2006.173.17:04:31.18#ibcon#end of sib2, iclass 21, count 2 2006.173.17:04:31.18#ibcon#*mode == 0, iclass 21, count 2 2006.173.17:04:31.18#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.17:04:31.18#ibcon#[27=AT02-04\r\n] 2006.173.17:04:31.18#ibcon#*before write, iclass 21, count 2 2006.173.17:04:31.18#ibcon#enter sib2, iclass 21, count 2 2006.173.17:04:31.18#ibcon#flushed, iclass 21, count 2 2006.173.17:04:31.18#ibcon#about to write, iclass 21, count 2 2006.173.17:04:31.18#ibcon#wrote, iclass 21, count 2 2006.173.17:04:31.18#ibcon#about to read 3, iclass 21, count 2 2006.173.17:04:31.21#ibcon#read 3, iclass 21, count 2 2006.173.17:04:31.21#ibcon#about to read 4, iclass 21, count 2 2006.173.17:04:31.21#ibcon#read 4, iclass 21, count 2 2006.173.17:04:31.21#ibcon#about to read 5, iclass 21, count 2 2006.173.17:04:31.21#ibcon#read 5, iclass 21, count 2 2006.173.17:04:31.21#ibcon#about to read 6, iclass 21, count 2 2006.173.17:04:31.21#ibcon#read 6, iclass 21, count 2 2006.173.17:04:31.21#ibcon#end of sib2, iclass 21, count 2 2006.173.17:04:31.21#ibcon#*after write, iclass 21, count 2 2006.173.17:04:31.21#ibcon#*before return 0, iclass 21, count 2 2006.173.17:04:31.21#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.17:04:31.21#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.17:04:31.21#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.17:04:31.21#ibcon#ireg 7 cls_cnt 0 2006.173.17:04:31.21#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.17:04:31.33#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.17:04:31.33#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.17:04:31.33#ibcon#enter wrdev, iclass 21, count 0 2006.173.17:04:31.33#ibcon#first serial, iclass 21, count 0 2006.173.17:04:31.33#ibcon#enter sib2, iclass 21, count 0 2006.173.17:04:31.33#ibcon#flushed, iclass 21, count 0 2006.173.17:04:31.33#ibcon#about to write, iclass 21, count 0 2006.173.17:04:31.33#ibcon#wrote, iclass 21, count 0 2006.173.17:04:31.33#ibcon#about to read 3, iclass 21, count 0 2006.173.17:04:31.35#ibcon#read 3, iclass 21, count 0 2006.173.17:04:31.35#ibcon#about to read 4, iclass 21, count 0 2006.173.17:04:31.35#ibcon#read 4, iclass 21, count 0 2006.173.17:04:31.35#ibcon#about to read 5, iclass 21, count 0 2006.173.17:04:31.35#ibcon#read 5, iclass 21, count 0 2006.173.17:04:31.35#ibcon#about to read 6, iclass 21, count 0 2006.173.17:04:31.35#ibcon#read 6, iclass 21, count 0 2006.173.17:04:31.35#ibcon#end of sib2, iclass 21, count 0 2006.173.17:04:31.35#ibcon#*mode == 0, iclass 21, count 0 2006.173.17:04:31.35#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.17:04:31.35#ibcon#[27=USB\r\n] 2006.173.17:04:31.35#ibcon#*before write, iclass 21, count 0 2006.173.17:04:31.35#ibcon#enter sib2, iclass 21, count 0 2006.173.17:04:31.35#ibcon#flushed, iclass 21, count 0 2006.173.17:04:31.35#ibcon#about to write, iclass 21, count 0 2006.173.17:04:31.35#ibcon#wrote, iclass 21, count 0 2006.173.17:04:31.35#ibcon#about to read 3, iclass 21, count 0 2006.173.17:04:31.38#ibcon#read 3, iclass 21, count 0 2006.173.17:04:31.38#ibcon#about to read 4, iclass 21, count 0 2006.173.17:04:31.38#ibcon#read 4, iclass 21, count 0 2006.173.17:04:31.38#ibcon#about to read 5, iclass 21, count 0 2006.173.17:04:31.38#ibcon#read 5, iclass 21, count 0 2006.173.17:04:31.38#ibcon#about to read 6, iclass 21, count 0 2006.173.17:04:31.38#ibcon#read 6, iclass 21, count 0 2006.173.17:04:31.38#ibcon#end of sib2, iclass 21, count 0 2006.173.17:04:31.38#ibcon#*after write, iclass 21, count 0 2006.173.17:04:31.38#ibcon#*before return 0, iclass 21, count 0 2006.173.17:04:31.38#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.17:04:31.38#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.17:04:31.38#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.17:04:31.38#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.17:04:31.38$vck44/vblo=3,649.99 2006.173.17:04:31.38#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.17:04:31.38#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.17:04:31.38#ibcon#ireg 17 cls_cnt 0 2006.173.17:04:31.38#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.17:04:31.38#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.17:04:31.38#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.17:04:31.38#ibcon#enter wrdev, iclass 23, count 0 2006.173.17:04:31.38#ibcon#first serial, iclass 23, count 0 2006.173.17:04:31.38#ibcon#enter sib2, iclass 23, count 0 2006.173.17:04:31.38#ibcon#flushed, iclass 23, count 0 2006.173.17:04:31.38#ibcon#about to write, iclass 23, count 0 2006.173.17:04:31.38#ibcon#wrote, iclass 23, count 0 2006.173.17:04:31.38#ibcon#about to read 3, iclass 23, count 0 2006.173.17:04:31.40#ibcon#read 3, iclass 23, count 0 2006.173.17:04:31.40#ibcon#about to read 4, iclass 23, count 0 2006.173.17:04:31.40#ibcon#read 4, iclass 23, count 0 2006.173.17:04:31.40#ibcon#about to read 5, iclass 23, count 0 2006.173.17:04:31.40#ibcon#read 5, iclass 23, count 0 2006.173.17:04:31.40#ibcon#about to read 6, iclass 23, count 0 2006.173.17:04:31.40#ibcon#read 6, iclass 23, count 0 2006.173.17:04:31.40#ibcon#end of sib2, iclass 23, count 0 2006.173.17:04:31.40#ibcon#*mode == 0, iclass 23, count 0 2006.173.17:04:31.40#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.17:04:31.40#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.17:04:31.40#ibcon#*before write, iclass 23, count 0 2006.173.17:04:31.40#ibcon#enter sib2, iclass 23, count 0 2006.173.17:04:31.40#ibcon#flushed, iclass 23, count 0 2006.173.17:04:31.40#ibcon#about to write, iclass 23, count 0 2006.173.17:04:31.40#ibcon#wrote, iclass 23, count 0 2006.173.17:04:31.40#ibcon#about to read 3, iclass 23, count 0 2006.173.17:04:31.44#ibcon#read 3, iclass 23, count 0 2006.173.17:04:31.44#ibcon#about to read 4, iclass 23, count 0 2006.173.17:04:31.44#ibcon#read 4, iclass 23, count 0 2006.173.17:04:31.44#ibcon#about to read 5, iclass 23, count 0 2006.173.17:04:31.44#ibcon#read 5, iclass 23, count 0 2006.173.17:04:31.44#ibcon#about to read 6, iclass 23, count 0 2006.173.17:04:31.44#ibcon#read 6, iclass 23, count 0 2006.173.17:04:31.44#ibcon#end of sib2, iclass 23, count 0 2006.173.17:04:31.44#ibcon#*after write, iclass 23, count 0 2006.173.17:04:31.44#ibcon#*before return 0, iclass 23, count 0 2006.173.17:04:31.44#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.17:04:31.44#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.17:04:31.44#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.17:04:31.44#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.17:04:31.44$vck44/vb=3,4 2006.173.17:04:31.44#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.17:04:31.44#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.17:04:31.44#ibcon#ireg 11 cls_cnt 2 2006.173.17:04:31.44#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.17:04:31.50#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.17:04:31.50#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.17:04:31.50#ibcon#enter wrdev, iclass 25, count 2 2006.173.17:04:31.50#ibcon#first serial, iclass 25, count 2 2006.173.17:04:31.50#ibcon#enter sib2, iclass 25, count 2 2006.173.17:04:31.50#ibcon#flushed, iclass 25, count 2 2006.173.17:04:31.50#ibcon#about to write, iclass 25, count 2 2006.173.17:04:31.50#ibcon#wrote, iclass 25, count 2 2006.173.17:04:31.50#ibcon#about to read 3, iclass 25, count 2 2006.173.17:04:31.52#ibcon#read 3, iclass 25, count 2 2006.173.17:04:31.52#ibcon#about to read 4, iclass 25, count 2 2006.173.17:04:31.52#ibcon#read 4, iclass 25, count 2 2006.173.17:04:31.52#ibcon#about to read 5, iclass 25, count 2 2006.173.17:04:31.52#ibcon#read 5, iclass 25, count 2 2006.173.17:04:31.52#ibcon#about to read 6, iclass 25, count 2 2006.173.17:04:31.52#ibcon#read 6, iclass 25, count 2 2006.173.17:04:31.52#ibcon#end of sib2, iclass 25, count 2 2006.173.17:04:31.52#ibcon#*mode == 0, iclass 25, count 2 2006.173.17:04:31.52#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.17:04:31.52#ibcon#[27=AT03-04\r\n] 2006.173.17:04:31.52#ibcon#*before write, iclass 25, count 2 2006.173.17:04:31.52#ibcon#enter sib2, iclass 25, count 2 2006.173.17:04:31.52#ibcon#flushed, iclass 25, count 2 2006.173.17:04:31.52#ibcon#about to write, iclass 25, count 2 2006.173.17:04:31.52#ibcon#wrote, iclass 25, count 2 2006.173.17:04:31.52#ibcon#about to read 3, iclass 25, count 2 2006.173.17:04:31.55#ibcon#read 3, iclass 25, count 2 2006.173.17:04:31.55#ibcon#about to read 4, iclass 25, count 2 2006.173.17:04:31.55#ibcon#read 4, iclass 25, count 2 2006.173.17:04:31.55#ibcon#about to read 5, iclass 25, count 2 2006.173.17:04:31.55#ibcon#read 5, iclass 25, count 2 2006.173.17:04:31.55#ibcon#about to read 6, iclass 25, count 2 2006.173.17:04:31.55#ibcon#read 6, iclass 25, count 2 2006.173.17:04:31.55#ibcon#end of sib2, iclass 25, count 2 2006.173.17:04:31.55#ibcon#*after write, iclass 25, count 2 2006.173.17:04:31.55#ibcon#*before return 0, iclass 25, count 2 2006.173.17:04:31.55#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.17:04:31.55#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.17:04:31.55#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.17:04:31.55#ibcon#ireg 7 cls_cnt 0 2006.173.17:04:31.55#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.17:04:31.67#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.17:04:31.67#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.17:04:31.67#ibcon#enter wrdev, iclass 25, count 0 2006.173.17:04:31.67#ibcon#first serial, iclass 25, count 0 2006.173.17:04:31.67#ibcon#enter sib2, iclass 25, count 0 2006.173.17:04:31.67#ibcon#flushed, iclass 25, count 0 2006.173.17:04:31.67#ibcon#about to write, iclass 25, count 0 2006.173.17:04:31.67#ibcon#wrote, iclass 25, count 0 2006.173.17:04:31.67#ibcon#about to read 3, iclass 25, count 0 2006.173.17:04:31.69#ibcon#read 3, iclass 25, count 0 2006.173.17:04:31.69#ibcon#about to read 4, iclass 25, count 0 2006.173.17:04:31.69#ibcon#read 4, iclass 25, count 0 2006.173.17:04:31.69#ibcon#about to read 5, iclass 25, count 0 2006.173.17:04:31.69#ibcon#read 5, iclass 25, count 0 2006.173.17:04:31.69#ibcon#about to read 6, iclass 25, count 0 2006.173.17:04:31.69#ibcon#read 6, iclass 25, count 0 2006.173.17:04:31.69#ibcon#end of sib2, iclass 25, count 0 2006.173.17:04:31.69#ibcon#*mode == 0, iclass 25, count 0 2006.173.17:04:31.69#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.17:04:31.69#ibcon#[27=USB\r\n] 2006.173.17:04:31.69#ibcon#*before write, iclass 25, count 0 2006.173.17:04:31.69#ibcon#enter sib2, iclass 25, count 0 2006.173.17:04:31.69#ibcon#flushed, iclass 25, count 0 2006.173.17:04:31.69#ibcon#about to write, iclass 25, count 0 2006.173.17:04:31.69#ibcon#wrote, iclass 25, count 0 2006.173.17:04:31.69#ibcon#about to read 3, iclass 25, count 0 2006.173.17:04:31.72#ibcon#read 3, iclass 25, count 0 2006.173.17:04:31.72#ibcon#about to read 4, iclass 25, count 0 2006.173.17:04:31.72#ibcon#read 4, iclass 25, count 0 2006.173.17:04:31.72#ibcon#about to read 5, iclass 25, count 0 2006.173.17:04:31.72#ibcon#read 5, iclass 25, count 0 2006.173.17:04:31.72#ibcon#about to read 6, iclass 25, count 0 2006.173.17:04:31.72#ibcon#read 6, iclass 25, count 0 2006.173.17:04:31.72#ibcon#end of sib2, iclass 25, count 0 2006.173.17:04:31.72#ibcon#*after write, iclass 25, count 0 2006.173.17:04:31.72#ibcon#*before return 0, iclass 25, count 0 2006.173.17:04:31.72#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.17:04:31.72#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.17:04:31.72#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.17:04:31.72#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.17:04:31.72$vck44/vblo=4,679.99 2006.173.17:04:31.72#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.17:04:31.72#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.17:04:31.72#ibcon#ireg 17 cls_cnt 0 2006.173.17:04:31.72#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.17:04:31.72#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.17:04:31.72#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.17:04:31.72#ibcon#enter wrdev, iclass 27, count 0 2006.173.17:04:31.72#ibcon#first serial, iclass 27, count 0 2006.173.17:04:31.72#ibcon#enter sib2, iclass 27, count 0 2006.173.17:04:31.72#ibcon#flushed, iclass 27, count 0 2006.173.17:04:31.72#ibcon#about to write, iclass 27, count 0 2006.173.17:04:31.72#ibcon#wrote, iclass 27, count 0 2006.173.17:04:31.72#ibcon#about to read 3, iclass 27, count 0 2006.173.17:04:31.74#ibcon#read 3, iclass 27, count 0 2006.173.17:04:31.74#ibcon#about to read 4, iclass 27, count 0 2006.173.17:04:31.74#ibcon#read 4, iclass 27, count 0 2006.173.17:04:31.74#ibcon#about to read 5, iclass 27, count 0 2006.173.17:04:31.74#ibcon#read 5, iclass 27, count 0 2006.173.17:04:31.74#ibcon#about to read 6, iclass 27, count 0 2006.173.17:04:31.74#ibcon#read 6, iclass 27, count 0 2006.173.17:04:31.74#ibcon#end of sib2, iclass 27, count 0 2006.173.17:04:31.74#ibcon#*mode == 0, iclass 27, count 0 2006.173.17:04:31.74#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.17:04:31.74#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.17:04:31.74#ibcon#*before write, iclass 27, count 0 2006.173.17:04:31.74#ibcon#enter sib2, iclass 27, count 0 2006.173.17:04:31.74#ibcon#flushed, iclass 27, count 0 2006.173.17:04:31.74#ibcon#about to write, iclass 27, count 0 2006.173.17:04:31.74#ibcon#wrote, iclass 27, count 0 2006.173.17:04:31.74#ibcon#about to read 3, iclass 27, count 0 2006.173.17:04:31.78#ibcon#read 3, iclass 27, count 0 2006.173.17:04:31.78#ibcon#about to read 4, iclass 27, count 0 2006.173.17:04:31.78#ibcon#read 4, iclass 27, count 0 2006.173.17:04:31.78#ibcon#about to read 5, iclass 27, count 0 2006.173.17:04:31.78#ibcon#read 5, iclass 27, count 0 2006.173.17:04:31.78#ibcon#about to read 6, iclass 27, count 0 2006.173.17:04:31.78#ibcon#read 6, iclass 27, count 0 2006.173.17:04:31.78#ibcon#end of sib2, iclass 27, count 0 2006.173.17:04:31.78#ibcon#*after write, iclass 27, count 0 2006.173.17:04:31.78#ibcon#*before return 0, iclass 27, count 0 2006.173.17:04:31.78#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.17:04:31.78#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.17:04:31.78#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.17:04:31.78#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.17:04:31.78$vck44/vb=4,4 2006.173.17:04:31.78#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.17:04:31.78#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.17:04:31.78#ibcon#ireg 11 cls_cnt 2 2006.173.17:04:31.78#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.17:04:31.84#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.17:04:31.84#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.17:04:31.84#ibcon#enter wrdev, iclass 29, count 2 2006.173.17:04:31.84#ibcon#first serial, iclass 29, count 2 2006.173.17:04:31.84#ibcon#enter sib2, iclass 29, count 2 2006.173.17:04:31.84#ibcon#flushed, iclass 29, count 2 2006.173.17:04:31.84#ibcon#about to write, iclass 29, count 2 2006.173.17:04:31.84#ibcon#wrote, iclass 29, count 2 2006.173.17:04:31.84#ibcon#about to read 3, iclass 29, count 2 2006.173.17:04:31.86#ibcon#read 3, iclass 29, count 2 2006.173.17:04:31.86#ibcon#about to read 4, iclass 29, count 2 2006.173.17:04:31.86#ibcon#read 4, iclass 29, count 2 2006.173.17:04:31.86#ibcon#about to read 5, iclass 29, count 2 2006.173.17:04:31.86#ibcon#read 5, iclass 29, count 2 2006.173.17:04:31.86#ibcon#about to read 6, iclass 29, count 2 2006.173.17:04:31.86#ibcon#read 6, iclass 29, count 2 2006.173.17:04:31.86#ibcon#end of sib2, iclass 29, count 2 2006.173.17:04:31.86#ibcon#*mode == 0, iclass 29, count 2 2006.173.17:04:31.86#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.17:04:31.86#ibcon#[27=AT04-04\r\n] 2006.173.17:04:31.86#ibcon#*before write, iclass 29, count 2 2006.173.17:04:31.86#ibcon#enter sib2, iclass 29, count 2 2006.173.17:04:31.86#ibcon#flushed, iclass 29, count 2 2006.173.17:04:31.86#ibcon#about to write, iclass 29, count 2 2006.173.17:04:31.86#ibcon#wrote, iclass 29, count 2 2006.173.17:04:31.86#ibcon#about to read 3, iclass 29, count 2 2006.173.17:04:31.89#ibcon#read 3, iclass 29, count 2 2006.173.17:04:31.89#ibcon#about to read 4, iclass 29, count 2 2006.173.17:04:31.89#ibcon#read 4, iclass 29, count 2 2006.173.17:04:31.89#ibcon#about to read 5, iclass 29, count 2 2006.173.17:04:31.89#ibcon#read 5, iclass 29, count 2 2006.173.17:04:31.89#ibcon#about to read 6, iclass 29, count 2 2006.173.17:04:31.89#ibcon#read 6, iclass 29, count 2 2006.173.17:04:31.89#ibcon#end of sib2, iclass 29, count 2 2006.173.17:04:31.89#ibcon#*after write, iclass 29, count 2 2006.173.17:04:31.89#ibcon#*before return 0, iclass 29, count 2 2006.173.17:04:31.89#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.17:04:31.89#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.17:04:31.89#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.17:04:31.89#ibcon#ireg 7 cls_cnt 0 2006.173.17:04:31.89#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.17:04:32.01#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.17:04:32.01#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.17:04:32.01#ibcon#enter wrdev, iclass 29, count 0 2006.173.17:04:32.01#ibcon#first serial, iclass 29, count 0 2006.173.17:04:32.01#ibcon#enter sib2, iclass 29, count 0 2006.173.17:04:32.01#ibcon#flushed, iclass 29, count 0 2006.173.17:04:32.01#ibcon#about to write, iclass 29, count 0 2006.173.17:04:32.01#ibcon#wrote, iclass 29, count 0 2006.173.17:04:32.01#ibcon#about to read 3, iclass 29, count 0 2006.173.17:04:32.03#ibcon#read 3, iclass 29, count 0 2006.173.17:04:32.03#ibcon#about to read 4, iclass 29, count 0 2006.173.17:04:32.03#ibcon#read 4, iclass 29, count 0 2006.173.17:04:32.03#ibcon#about to read 5, iclass 29, count 0 2006.173.17:04:32.03#ibcon#read 5, iclass 29, count 0 2006.173.17:04:32.03#ibcon#about to read 6, iclass 29, count 0 2006.173.17:04:32.03#ibcon#read 6, iclass 29, count 0 2006.173.17:04:32.03#ibcon#end of sib2, iclass 29, count 0 2006.173.17:04:32.03#ibcon#*mode == 0, iclass 29, count 0 2006.173.17:04:32.03#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.17:04:32.03#ibcon#[27=USB\r\n] 2006.173.17:04:32.03#ibcon#*before write, iclass 29, count 0 2006.173.17:04:32.03#ibcon#enter sib2, iclass 29, count 0 2006.173.17:04:32.03#ibcon#flushed, iclass 29, count 0 2006.173.17:04:32.03#ibcon#about to write, iclass 29, count 0 2006.173.17:04:32.03#ibcon#wrote, iclass 29, count 0 2006.173.17:04:32.03#ibcon#about to read 3, iclass 29, count 0 2006.173.17:04:32.06#ibcon#read 3, iclass 29, count 0 2006.173.17:04:32.06#ibcon#about to read 4, iclass 29, count 0 2006.173.17:04:32.06#ibcon#read 4, iclass 29, count 0 2006.173.17:04:32.06#ibcon#about to read 5, iclass 29, count 0 2006.173.17:04:32.06#ibcon#read 5, iclass 29, count 0 2006.173.17:04:32.06#ibcon#about to read 6, iclass 29, count 0 2006.173.17:04:32.06#ibcon#read 6, iclass 29, count 0 2006.173.17:04:32.06#ibcon#end of sib2, iclass 29, count 0 2006.173.17:04:32.06#ibcon#*after write, iclass 29, count 0 2006.173.17:04:32.06#ibcon#*before return 0, iclass 29, count 0 2006.173.17:04:32.06#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.17:04:32.06#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.17:04:32.06#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.17:04:32.06#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.17:04:32.06$vck44/vblo=5,709.99 2006.173.17:04:32.06#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.17:04:32.06#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.17:04:32.06#ibcon#ireg 17 cls_cnt 0 2006.173.17:04:32.06#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.17:04:32.06#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.17:04:32.06#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.17:04:32.06#ibcon#enter wrdev, iclass 31, count 0 2006.173.17:04:32.06#ibcon#first serial, iclass 31, count 0 2006.173.17:04:32.06#ibcon#enter sib2, iclass 31, count 0 2006.173.17:04:32.06#ibcon#flushed, iclass 31, count 0 2006.173.17:04:32.06#ibcon#about to write, iclass 31, count 0 2006.173.17:04:32.06#ibcon#wrote, iclass 31, count 0 2006.173.17:04:32.06#ibcon#about to read 3, iclass 31, count 0 2006.173.17:04:32.08#ibcon#read 3, iclass 31, count 0 2006.173.17:04:32.08#ibcon#about to read 4, iclass 31, count 0 2006.173.17:04:32.08#ibcon#read 4, iclass 31, count 0 2006.173.17:04:32.08#ibcon#about to read 5, iclass 31, count 0 2006.173.17:04:32.08#ibcon#read 5, iclass 31, count 0 2006.173.17:04:32.08#ibcon#about to read 6, iclass 31, count 0 2006.173.17:04:32.08#ibcon#read 6, iclass 31, count 0 2006.173.17:04:32.08#ibcon#end of sib2, iclass 31, count 0 2006.173.17:04:32.08#ibcon#*mode == 0, iclass 31, count 0 2006.173.17:04:32.08#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.17:04:32.08#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.17:04:32.08#ibcon#*before write, iclass 31, count 0 2006.173.17:04:32.08#ibcon#enter sib2, iclass 31, count 0 2006.173.17:04:32.08#ibcon#flushed, iclass 31, count 0 2006.173.17:04:32.08#ibcon#about to write, iclass 31, count 0 2006.173.17:04:32.08#ibcon#wrote, iclass 31, count 0 2006.173.17:04:32.08#ibcon#about to read 3, iclass 31, count 0 2006.173.17:04:32.12#ibcon#read 3, iclass 31, count 0 2006.173.17:04:32.12#ibcon#about to read 4, iclass 31, count 0 2006.173.17:04:32.12#ibcon#read 4, iclass 31, count 0 2006.173.17:04:32.12#ibcon#about to read 5, iclass 31, count 0 2006.173.17:04:32.12#ibcon#read 5, iclass 31, count 0 2006.173.17:04:32.12#ibcon#about to read 6, iclass 31, count 0 2006.173.17:04:32.12#ibcon#read 6, iclass 31, count 0 2006.173.17:04:32.12#ibcon#end of sib2, iclass 31, count 0 2006.173.17:04:32.12#ibcon#*after write, iclass 31, count 0 2006.173.17:04:32.12#ibcon#*before return 0, iclass 31, count 0 2006.173.17:04:32.12#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.17:04:32.12#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.17:04:32.12#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.17:04:32.12#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.17:04:32.12$vck44/vb=5,4 2006.173.17:04:32.12#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.173.17:04:32.12#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.173.17:04:32.12#ibcon#ireg 11 cls_cnt 2 2006.173.17:04:32.12#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.17:04:32.18#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.17:04:32.18#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.17:04:32.18#ibcon#enter wrdev, iclass 33, count 2 2006.173.17:04:32.18#ibcon#first serial, iclass 33, count 2 2006.173.17:04:32.18#ibcon#enter sib2, iclass 33, count 2 2006.173.17:04:32.18#ibcon#flushed, iclass 33, count 2 2006.173.17:04:32.18#ibcon#about to write, iclass 33, count 2 2006.173.17:04:32.18#ibcon#wrote, iclass 33, count 2 2006.173.17:04:32.18#ibcon#about to read 3, iclass 33, count 2 2006.173.17:04:32.20#ibcon#read 3, iclass 33, count 2 2006.173.17:04:32.20#ibcon#about to read 4, iclass 33, count 2 2006.173.17:04:32.20#ibcon#read 4, iclass 33, count 2 2006.173.17:04:32.20#ibcon#about to read 5, iclass 33, count 2 2006.173.17:04:32.20#ibcon#read 5, iclass 33, count 2 2006.173.17:04:32.20#ibcon#about to read 6, iclass 33, count 2 2006.173.17:04:32.20#ibcon#read 6, iclass 33, count 2 2006.173.17:04:32.20#ibcon#end of sib2, iclass 33, count 2 2006.173.17:04:32.20#ibcon#*mode == 0, iclass 33, count 2 2006.173.17:04:32.20#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.173.17:04:32.20#ibcon#[27=AT05-04\r\n] 2006.173.17:04:32.20#ibcon#*before write, iclass 33, count 2 2006.173.17:04:32.20#ibcon#enter sib2, iclass 33, count 2 2006.173.17:04:32.20#ibcon#flushed, iclass 33, count 2 2006.173.17:04:32.20#ibcon#about to write, iclass 33, count 2 2006.173.17:04:32.20#ibcon#wrote, iclass 33, count 2 2006.173.17:04:32.20#ibcon#about to read 3, iclass 33, count 2 2006.173.17:04:32.23#ibcon#read 3, iclass 33, count 2 2006.173.17:04:32.23#ibcon#about to read 4, iclass 33, count 2 2006.173.17:04:32.23#ibcon#read 4, iclass 33, count 2 2006.173.17:04:32.23#ibcon#about to read 5, iclass 33, count 2 2006.173.17:04:32.23#ibcon#read 5, iclass 33, count 2 2006.173.17:04:32.23#ibcon#about to read 6, iclass 33, count 2 2006.173.17:04:32.23#ibcon#read 6, iclass 33, count 2 2006.173.17:04:32.23#ibcon#end of sib2, iclass 33, count 2 2006.173.17:04:32.23#ibcon#*after write, iclass 33, count 2 2006.173.17:04:32.23#ibcon#*before return 0, iclass 33, count 2 2006.173.17:04:32.23#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.17:04:32.23#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.173.17:04:32.23#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.173.17:04:32.23#ibcon#ireg 7 cls_cnt 0 2006.173.17:04:32.23#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.17:04:32.35#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.17:04:32.35#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.17:04:32.35#ibcon#enter wrdev, iclass 33, count 0 2006.173.17:04:32.35#ibcon#first serial, iclass 33, count 0 2006.173.17:04:32.35#ibcon#enter sib2, iclass 33, count 0 2006.173.17:04:32.35#ibcon#flushed, iclass 33, count 0 2006.173.17:04:32.35#ibcon#about to write, iclass 33, count 0 2006.173.17:04:32.35#ibcon#wrote, iclass 33, count 0 2006.173.17:04:32.35#ibcon#about to read 3, iclass 33, count 0 2006.173.17:04:32.37#ibcon#read 3, iclass 33, count 0 2006.173.17:04:32.37#ibcon#about to read 4, iclass 33, count 0 2006.173.17:04:32.37#ibcon#read 4, iclass 33, count 0 2006.173.17:04:32.37#ibcon#about to read 5, iclass 33, count 0 2006.173.17:04:32.37#ibcon#read 5, iclass 33, count 0 2006.173.17:04:32.37#ibcon#about to read 6, iclass 33, count 0 2006.173.17:04:32.37#ibcon#read 6, iclass 33, count 0 2006.173.17:04:32.37#ibcon#end of sib2, iclass 33, count 0 2006.173.17:04:32.37#ibcon#*mode == 0, iclass 33, count 0 2006.173.17:04:32.37#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.17:04:32.37#ibcon#[27=USB\r\n] 2006.173.17:04:32.37#ibcon#*before write, iclass 33, count 0 2006.173.17:04:32.37#ibcon#enter sib2, iclass 33, count 0 2006.173.17:04:32.37#ibcon#flushed, iclass 33, count 0 2006.173.17:04:32.37#ibcon#about to write, iclass 33, count 0 2006.173.17:04:32.37#ibcon#wrote, iclass 33, count 0 2006.173.17:04:32.37#ibcon#about to read 3, iclass 33, count 0 2006.173.17:04:32.40#ibcon#read 3, iclass 33, count 0 2006.173.17:04:32.40#ibcon#about to read 4, iclass 33, count 0 2006.173.17:04:32.40#ibcon#read 4, iclass 33, count 0 2006.173.17:04:32.40#ibcon#about to read 5, iclass 33, count 0 2006.173.17:04:32.40#ibcon#read 5, iclass 33, count 0 2006.173.17:04:32.40#ibcon#about to read 6, iclass 33, count 0 2006.173.17:04:32.40#ibcon#read 6, iclass 33, count 0 2006.173.17:04:32.40#ibcon#end of sib2, iclass 33, count 0 2006.173.17:04:32.40#ibcon#*after write, iclass 33, count 0 2006.173.17:04:32.40#ibcon#*before return 0, iclass 33, count 0 2006.173.17:04:32.40#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.17:04:32.40#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.173.17:04:32.40#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.17:04:32.40#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.17:04:32.40$vck44/vblo=6,719.99 2006.173.17:04:32.40#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.17:04:32.40#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.17:04:32.40#ibcon#ireg 17 cls_cnt 0 2006.173.17:04:32.40#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.17:04:32.40#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.17:04:32.40#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.17:04:32.40#ibcon#enter wrdev, iclass 35, count 0 2006.173.17:04:32.40#ibcon#first serial, iclass 35, count 0 2006.173.17:04:32.40#ibcon#enter sib2, iclass 35, count 0 2006.173.17:04:32.40#ibcon#flushed, iclass 35, count 0 2006.173.17:04:32.40#ibcon#about to write, iclass 35, count 0 2006.173.17:04:32.40#ibcon#wrote, iclass 35, count 0 2006.173.17:04:32.40#ibcon#about to read 3, iclass 35, count 0 2006.173.17:04:32.42#ibcon#read 3, iclass 35, count 0 2006.173.17:04:32.42#ibcon#about to read 4, iclass 35, count 0 2006.173.17:04:32.42#ibcon#read 4, iclass 35, count 0 2006.173.17:04:32.42#ibcon#about to read 5, iclass 35, count 0 2006.173.17:04:32.42#ibcon#read 5, iclass 35, count 0 2006.173.17:04:32.42#ibcon#about to read 6, iclass 35, count 0 2006.173.17:04:32.42#ibcon#read 6, iclass 35, count 0 2006.173.17:04:32.42#ibcon#end of sib2, iclass 35, count 0 2006.173.17:04:32.42#ibcon#*mode == 0, iclass 35, count 0 2006.173.17:04:32.42#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.17:04:32.42#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.17:04:32.42#ibcon#*before write, iclass 35, count 0 2006.173.17:04:32.42#ibcon#enter sib2, iclass 35, count 0 2006.173.17:04:32.42#ibcon#flushed, iclass 35, count 0 2006.173.17:04:32.42#ibcon#about to write, iclass 35, count 0 2006.173.17:04:32.42#ibcon#wrote, iclass 35, count 0 2006.173.17:04:32.42#ibcon#about to read 3, iclass 35, count 0 2006.173.17:04:32.46#ibcon#read 3, iclass 35, count 0 2006.173.17:04:32.46#ibcon#about to read 4, iclass 35, count 0 2006.173.17:04:32.46#ibcon#read 4, iclass 35, count 0 2006.173.17:04:32.46#ibcon#about to read 5, iclass 35, count 0 2006.173.17:04:32.46#ibcon#read 5, iclass 35, count 0 2006.173.17:04:32.46#ibcon#about to read 6, iclass 35, count 0 2006.173.17:04:32.46#ibcon#read 6, iclass 35, count 0 2006.173.17:04:32.46#ibcon#end of sib2, iclass 35, count 0 2006.173.17:04:32.46#ibcon#*after write, iclass 35, count 0 2006.173.17:04:32.46#ibcon#*before return 0, iclass 35, count 0 2006.173.17:04:32.46#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.17:04:32.46#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.17:04:32.46#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.17:04:32.46#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.17:04:32.46$vck44/vb=6,4 2006.173.17:04:32.46#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.173.17:04:32.46#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.173.17:04:32.46#ibcon#ireg 11 cls_cnt 2 2006.173.17:04:32.46#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.17:04:32.52#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.17:04:32.52#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.17:04:32.52#ibcon#enter wrdev, iclass 37, count 2 2006.173.17:04:32.52#ibcon#first serial, iclass 37, count 2 2006.173.17:04:32.52#ibcon#enter sib2, iclass 37, count 2 2006.173.17:04:32.52#ibcon#flushed, iclass 37, count 2 2006.173.17:04:32.52#ibcon#about to write, iclass 37, count 2 2006.173.17:04:32.52#ibcon#wrote, iclass 37, count 2 2006.173.17:04:32.52#ibcon#about to read 3, iclass 37, count 2 2006.173.17:04:32.54#ibcon#read 3, iclass 37, count 2 2006.173.17:04:32.54#ibcon#about to read 4, iclass 37, count 2 2006.173.17:04:32.54#ibcon#read 4, iclass 37, count 2 2006.173.17:04:32.54#ibcon#about to read 5, iclass 37, count 2 2006.173.17:04:32.54#ibcon#read 5, iclass 37, count 2 2006.173.17:04:32.54#ibcon#about to read 6, iclass 37, count 2 2006.173.17:04:32.54#ibcon#read 6, iclass 37, count 2 2006.173.17:04:32.54#ibcon#end of sib2, iclass 37, count 2 2006.173.17:04:32.54#ibcon#*mode == 0, iclass 37, count 2 2006.173.17:04:32.54#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.173.17:04:32.54#ibcon#[27=AT06-04\r\n] 2006.173.17:04:32.54#ibcon#*before write, iclass 37, count 2 2006.173.17:04:32.54#ibcon#enter sib2, iclass 37, count 2 2006.173.17:04:32.54#ibcon#flushed, iclass 37, count 2 2006.173.17:04:32.54#ibcon#about to write, iclass 37, count 2 2006.173.17:04:32.54#ibcon#wrote, iclass 37, count 2 2006.173.17:04:32.54#ibcon#about to read 3, iclass 37, count 2 2006.173.17:04:32.57#ibcon#read 3, iclass 37, count 2 2006.173.17:04:32.57#ibcon#about to read 4, iclass 37, count 2 2006.173.17:04:32.57#ibcon#read 4, iclass 37, count 2 2006.173.17:04:32.57#ibcon#about to read 5, iclass 37, count 2 2006.173.17:04:32.57#ibcon#read 5, iclass 37, count 2 2006.173.17:04:32.57#ibcon#about to read 6, iclass 37, count 2 2006.173.17:04:32.57#ibcon#read 6, iclass 37, count 2 2006.173.17:04:32.57#ibcon#end of sib2, iclass 37, count 2 2006.173.17:04:32.57#ibcon#*after write, iclass 37, count 2 2006.173.17:04:32.57#ibcon#*before return 0, iclass 37, count 2 2006.173.17:04:32.57#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.17:04:32.57#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.173.17:04:32.57#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.173.17:04:32.57#ibcon#ireg 7 cls_cnt 0 2006.173.17:04:32.57#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.17:04:32.69#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.17:04:32.69#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.17:04:32.69#ibcon#enter wrdev, iclass 37, count 0 2006.173.17:04:32.69#ibcon#first serial, iclass 37, count 0 2006.173.17:04:32.69#ibcon#enter sib2, iclass 37, count 0 2006.173.17:04:32.69#ibcon#flushed, iclass 37, count 0 2006.173.17:04:32.69#ibcon#about to write, iclass 37, count 0 2006.173.17:04:32.69#ibcon#wrote, iclass 37, count 0 2006.173.17:04:32.69#ibcon#about to read 3, iclass 37, count 0 2006.173.17:04:32.71#ibcon#read 3, iclass 37, count 0 2006.173.17:04:32.71#ibcon#about to read 4, iclass 37, count 0 2006.173.17:04:32.71#ibcon#read 4, iclass 37, count 0 2006.173.17:04:32.71#ibcon#about to read 5, iclass 37, count 0 2006.173.17:04:32.71#ibcon#read 5, iclass 37, count 0 2006.173.17:04:32.71#ibcon#about to read 6, iclass 37, count 0 2006.173.17:04:32.71#ibcon#read 6, iclass 37, count 0 2006.173.17:04:32.71#ibcon#end of sib2, iclass 37, count 0 2006.173.17:04:32.71#ibcon#*mode == 0, iclass 37, count 0 2006.173.17:04:32.71#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.17:04:32.71#ibcon#[27=USB\r\n] 2006.173.17:04:32.71#ibcon#*before write, iclass 37, count 0 2006.173.17:04:32.71#ibcon#enter sib2, iclass 37, count 0 2006.173.17:04:32.71#ibcon#flushed, iclass 37, count 0 2006.173.17:04:32.71#ibcon#about to write, iclass 37, count 0 2006.173.17:04:32.71#ibcon#wrote, iclass 37, count 0 2006.173.17:04:32.71#ibcon#about to read 3, iclass 37, count 0 2006.173.17:04:32.74#ibcon#read 3, iclass 37, count 0 2006.173.17:04:32.74#ibcon#about to read 4, iclass 37, count 0 2006.173.17:04:32.74#ibcon#read 4, iclass 37, count 0 2006.173.17:04:32.74#ibcon#about to read 5, iclass 37, count 0 2006.173.17:04:32.74#ibcon#read 5, iclass 37, count 0 2006.173.17:04:32.74#ibcon#about to read 6, iclass 37, count 0 2006.173.17:04:32.74#ibcon#read 6, iclass 37, count 0 2006.173.17:04:32.74#ibcon#end of sib2, iclass 37, count 0 2006.173.17:04:32.74#ibcon#*after write, iclass 37, count 0 2006.173.17:04:32.74#ibcon#*before return 0, iclass 37, count 0 2006.173.17:04:32.74#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.17:04:32.74#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.173.17:04:32.74#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.17:04:32.74#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.17:04:32.74$vck44/vblo=7,734.99 2006.173.17:04:32.74#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.17:04:32.74#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.17:04:32.74#ibcon#ireg 17 cls_cnt 0 2006.173.17:04:32.74#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.17:04:32.74#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.17:04:32.74#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.17:04:32.74#ibcon#enter wrdev, iclass 39, count 0 2006.173.17:04:32.74#ibcon#first serial, iclass 39, count 0 2006.173.17:04:32.74#ibcon#enter sib2, iclass 39, count 0 2006.173.17:04:32.74#ibcon#flushed, iclass 39, count 0 2006.173.17:04:32.74#ibcon#about to write, iclass 39, count 0 2006.173.17:04:32.74#ibcon#wrote, iclass 39, count 0 2006.173.17:04:32.74#ibcon#about to read 3, iclass 39, count 0 2006.173.17:04:32.76#ibcon#read 3, iclass 39, count 0 2006.173.17:04:32.76#ibcon#about to read 4, iclass 39, count 0 2006.173.17:04:32.76#ibcon#read 4, iclass 39, count 0 2006.173.17:04:32.76#ibcon#about to read 5, iclass 39, count 0 2006.173.17:04:32.76#ibcon#read 5, iclass 39, count 0 2006.173.17:04:32.76#ibcon#about to read 6, iclass 39, count 0 2006.173.17:04:32.76#ibcon#read 6, iclass 39, count 0 2006.173.17:04:32.76#ibcon#end of sib2, iclass 39, count 0 2006.173.17:04:32.76#ibcon#*mode == 0, iclass 39, count 0 2006.173.17:04:32.76#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.17:04:32.76#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.17:04:32.76#ibcon#*before write, iclass 39, count 0 2006.173.17:04:32.76#ibcon#enter sib2, iclass 39, count 0 2006.173.17:04:32.76#ibcon#flushed, iclass 39, count 0 2006.173.17:04:32.76#ibcon#about to write, iclass 39, count 0 2006.173.17:04:32.76#ibcon#wrote, iclass 39, count 0 2006.173.17:04:32.76#ibcon#about to read 3, iclass 39, count 0 2006.173.17:04:32.80#ibcon#read 3, iclass 39, count 0 2006.173.17:04:32.80#ibcon#about to read 4, iclass 39, count 0 2006.173.17:04:32.80#ibcon#read 4, iclass 39, count 0 2006.173.17:04:32.80#ibcon#about to read 5, iclass 39, count 0 2006.173.17:04:32.80#ibcon#read 5, iclass 39, count 0 2006.173.17:04:32.80#ibcon#about to read 6, iclass 39, count 0 2006.173.17:04:32.80#ibcon#read 6, iclass 39, count 0 2006.173.17:04:32.80#ibcon#end of sib2, iclass 39, count 0 2006.173.17:04:32.80#ibcon#*after write, iclass 39, count 0 2006.173.17:04:32.80#ibcon#*before return 0, iclass 39, count 0 2006.173.17:04:32.80#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.17:04:32.80#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.17:04:32.80#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.17:04:32.80#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.17:04:32.80$vck44/vb=7,4 2006.173.17:04:32.80#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.17:04:32.80#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.17:04:32.80#ibcon#ireg 11 cls_cnt 2 2006.173.17:04:32.80#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.17:04:32.86#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.17:04:32.86#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.17:04:32.86#ibcon#enter wrdev, iclass 3, count 2 2006.173.17:04:32.86#ibcon#first serial, iclass 3, count 2 2006.173.17:04:32.86#ibcon#enter sib2, iclass 3, count 2 2006.173.17:04:32.86#ibcon#flushed, iclass 3, count 2 2006.173.17:04:32.86#ibcon#about to write, iclass 3, count 2 2006.173.17:04:32.86#ibcon#wrote, iclass 3, count 2 2006.173.17:04:32.86#ibcon#about to read 3, iclass 3, count 2 2006.173.17:04:32.88#ibcon#read 3, iclass 3, count 2 2006.173.17:04:32.88#ibcon#about to read 4, iclass 3, count 2 2006.173.17:04:32.88#ibcon#read 4, iclass 3, count 2 2006.173.17:04:32.88#ibcon#about to read 5, iclass 3, count 2 2006.173.17:04:32.88#ibcon#read 5, iclass 3, count 2 2006.173.17:04:32.88#ibcon#about to read 6, iclass 3, count 2 2006.173.17:04:32.88#ibcon#read 6, iclass 3, count 2 2006.173.17:04:32.88#ibcon#end of sib2, iclass 3, count 2 2006.173.17:04:32.88#ibcon#*mode == 0, iclass 3, count 2 2006.173.17:04:32.88#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.17:04:32.88#ibcon#[27=AT07-04\r\n] 2006.173.17:04:32.88#ibcon#*before write, iclass 3, count 2 2006.173.17:04:32.88#ibcon#enter sib2, iclass 3, count 2 2006.173.17:04:32.88#ibcon#flushed, iclass 3, count 2 2006.173.17:04:32.88#ibcon#about to write, iclass 3, count 2 2006.173.17:04:32.88#ibcon#wrote, iclass 3, count 2 2006.173.17:04:32.88#ibcon#about to read 3, iclass 3, count 2 2006.173.17:04:32.91#ibcon#read 3, iclass 3, count 2 2006.173.17:04:32.91#ibcon#about to read 4, iclass 3, count 2 2006.173.17:04:32.91#ibcon#read 4, iclass 3, count 2 2006.173.17:04:32.91#ibcon#about to read 5, iclass 3, count 2 2006.173.17:04:32.91#ibcon#read 5, iclass 3, count 2 2006.173.17:04:32.91#ibcon#about to read 6, iclass 3, count 2 2006.173.17:04:32.91#ibcon#read 6, iclass 3, count 2 2006.173.17:04:32.91#ibcon#end of sib2, iclass 3, count 2 2006.173.17:04:32.91#ibcon#*after write, iclass 3, count 2 2006.173.17:04:32.91#ibcon#*before return 0, iclass 3, count 2 2006.173.17:04:32.91#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.17:04:32.91#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.17:04:32.91#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.17:04:32.91#ibcon#ireg 7 cls_cnt 0 2006.173.17:04:32.91#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.17:04:33.03#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.17:04:33.03#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.17:04:33.03#ibcon#enter wrdev, iclass 3, count 0 2006.173.17:04:33.03#ibcon#first serial, iclass 3, count 0 2006.173.17:04:33.03#ibcon#enter sib2, iclass 3, count 0 2006.173.17:04:33.03#ibcon#flushed, iclass 3, count 0 2006.173.17:04:33.03#ibcon#about to write, iclass 3, count 0 2006.173.17:04:33.03#ibcon#wrote, iclass 3, count 0 2006.173.17:04:33.03#ibcon#about to read 3, iclass 3, count 0 2006.173.17:04:33.05#ibcon#read 3, iclass 3, count 0 2006.173.17:04:33.05#ibcon#about to read 4, iclass 3, count 0 2006.173.17:04:33.05#ibcon#read 4, iclass 3, count 0 2006.173.17:04:33.05#ibcon#about to read 5, iclass 3, count 0 2006.173.17:04:33.05#ibcon#read 5, iclass 3, count 0 2006.173.17:04:33.05#ibcon#about to read 6, iclass 3, count 0 2006.173.17:04:33.05#ibcon#read 6, iclass 3, count 0 2006.173.17:04:33.05#ibcon#end of sib2, iclass 3, count 0 2006.173.17:04:33.05#ibcon#*mode == 0, iclass 3, count 0 2006.173.17:04:33.05#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.17:04:33.05#ibcon#[27=USB\r\n] 2006.173.17:04:33.05#ibcon#*before write, iclass 3, count 0 2006.173.17:04:33.05#ibcon#enter sib2, iclass 3, count 0 2006.173.17:04:33.05#ibcon#flushed, iclass 3, count 0 2006.173.17:04:33.05#ibcon#about to write, iclass 3, count 0 2006.173.17:04:33.05#ibcon#wrote, iclass 3, count 0 2006.173.17:04:33.05#ibcon#about to read 3, iclass 3, count 0 2006.173.17:04:33.08#ibcon#read 3, iclass 3, count 0 2006.173.17:04:33.08#ibcon#about to read 4, iclass 3, count 0 2006.173.17:04:33.08#ibcon#read 4, iclass 3, count 0 2006.173.17:04:33.08#ibcon#about to read 5, iclass 3, count 0 2006.173.17:04:33.08#ibcon#read 5, iclass 3, count 0 2006.173.17:04:33.08#ibcon#about to read 6, iclass 3, count 0 2006.173.17:04:33.08#ibcon#read 6, iclass 3, count 0 2006.173.17:04:33.08#ibcon#end of sib2, iclass 3, count 0 2006.173.17:04:33.08#ibcon#*after write, iclass 3, count 0 2006.173.17:04:33.08#ibcon#*before return 0, iclass 3, count 0 2006.173.17:04:33.08#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.17:04:33.08#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.17:04:33.08#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.17:04:33.08#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.17:04:33.08$vck44/vblo=8,744.99 2006.173.17:04:33.08#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.17:04:33.08#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.17:04:33.08#ibcon#ireg 17 cls_cnt 0 2006.173.17:04:33.08#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.17:04:33.08#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.17:04:33.08#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.17:04:33.08#ibcon#enter wrdev, iclass 5, count 0 2006.173.17:04:33.08#ibcon#first serial, iclass 5, count 0 2006.173.17:04:33.08#ibcon#enter sib2, iclass 5, count 0 2006.173.17:04:33.08#ibcon#flushed, iclass 5, count 0 2006.173.17:04:33.08#ibcon#about to write, iclass 5, count 0 2006.173.17:04:33.08#ibcon#wrote, iclass 5, count 0 2006.173.17:04:33.08#ibcon#about to read 3, iclass 5, count 0 2006.173.17:04:33.10#ibcon#read 3, iclass 5, count 0 2006.173.17:04:33.10#ibcon#about to read 4, iclass 5, count 0 2006.173.17:04:33.10#ibcon#read 4, iclass 5, count 0 2006.173.17:04:33.10#ibcon#about to read 5, iclass 5, count 0 2006.173.17:04:33.10#ibcon#read 5, iclass 5, count 0 2006.173.17:04:33.10#ibcon#about to read 6, iclass 5, count 0 2006.173.17:04:33.10#ibcon#read 6, iclass 5, count 0 2006.173.17:04:33.10#ibcon#end of sib2, iclass 5, count 0 2006.173.17:04:33.10#ibcon#*mode == 0, iclass 5, count 0 2006.173.17:04:33.10#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.17:04:33.10#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.17:04:33.10#ibcon#*before write, iclass 5, count 0 2006.173.17:04:33.10#ibcon#enter sib2, iclass 5, count 0 2006.173.17:04:33.10#ibcon#flushed, iclass 5, count 0 2006.173.17:04:33.10#ibcon#about to write, iclass 5, count 0 2006.173.17:04:33.10#ibcon#wrote, iclass 5, count 0 2006.173.17:04:33.10#ibcon#about to read 3, iclass 5, count 0 2006.173.17:04:33.14#ibcon#read 3, iclass 5, count 0 2006.173.17:04:33.14#ibcon#about to read 4, iclass 5, count 0 2006.173.17:04:33.14#ibcon#read 4, iclass 5, count 0 2006.173.17:04:33.14#ibcon#about to read 5, iclass 5, count 0 2006.173.17:04:33.14#ibcon#read 5, iclass 5, count 0 2006.173.17:04:33.14#ibcon#about to read 6, iclass 5, count 0 2006.173.17:04:33.14#ibcon#read 6, iclass 5, count 0 2006.173.17:04:33.14#ibcon#end of sib2, iclass 5, count 0 2006.173.17:04:33.14#ibcon#*after write, iclass 5, count 0 2006.173.17:04:33.14#ibcon#*before return 0, iclass 5, count 0 2006.173.17:04:33.14#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.17:04:33.14#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.17:04:33.14#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.17:04:33.14#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.17:04:33.14$vck44/vb=8,4 2006.173.17:04:33.14#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.173.17:04:33.14#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.173.17:04:33.14#ibcon#ireg 11 cls_cnt 2 2006.173.17:04:33.14#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.17:04:33.20#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.17:04:33.20#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.17:04:33.20#ibcon#enter wrdev, iclass 7, count 2 2006.173.17:04:33.20#ibcon#first serial, iclass 7, count 2 2006.173.17:04:33.20#ibcon#enter sib2, iclass 7, count 2 2006.173.17:04:33.20#ibcon#flushed, iclass 7, count 2 2006.173.17:04:33.20#ibcon#about to write, iclass 7, count 2 2006.173.17:04:33.20#ibcon#wrote, iclass 7, count 2 2006.173.17:04:33.20#ibcon#about to read 3, iclass 7, count 2 2006.173.17:04:33.22#ibcon#read 3, iclass 7, count 2 2006.173.17:04:33.22#ibcon#about to read 4, iclass 7, count 2 2006.173.17:04:33.22#ibcon#read 4, iclass 7, count 2 2006.173.17:04:33.22#ibcon#about to read 5, iclass 7, count 2 2006.173.17:04:33.22#ibcon#read 5, iclass 7, count 2 2006.173.17:04:33.22#ibcon#about to read 6, iclass 7, count 2 2006.173.17:04:33.22#ibcon#read 6, iclass 7, count 2 2006.173.17:04:33.22#ibcon#end of sib2, iclass 7, count 2 2006.173.17:04:33.22#ibcon#*mode == 0, iclass 7, count 2 2006.173.17:04:33.22#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.173.17:04:33.22#ibcon#[27=AT08-04\r\n] 2006.173.17:04:33.22#ibcon#*before write, iclass 7, count 2 2006.173.17:04:33.22#ibcon#enter sib2, iclass 7, count 2 2006.173.17:04:33.22#ibcon#flushed, iclass 7, count 2 2006.173.17:04:33.22#ibcon#about to write, iclass 7, count 2 2006.173.17:04:33.22#ibcon#wrote, iclass 7, count 2 2006.173.17:04:33.22#ibcon#about to read 3, iclass 7, count 2 2006.173.17:04:33.25#ibcon#read 3, iclass 7, count 2 2006.173.17:04:33.25#ibcon#about to read 4, iclass 7, count 2 2006.173.17:04:33.25#ibcon#read 4, iclass 7, count 2 2006.173.17:04:33.25#ibcon#about to read 5, iclass 7, count 2 2006.173.17:04:33.25#ibcon#read 5, iclass 7, count 2 2006.173.17:04:33.25#ibcon#about to read 6, iclass 7, count 2 2006.173.17:04:33.25#ibcon#read 6, iclass 7, count 2 2006.173.17:04:33.25#ibcon#end of sib2, iclass 7, count 2 2006.173.17:04:33.25#ibcon#*after write, iclass 7, count 2 2006.173.17:04:33.25#ibcon#*before return 0, iclass 7, count 2 2006.173.17:04:33.25#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.17:04:33.25#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.173.17:04:33.25#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.173.17:04:33.25#ibcon#ireg 7 cls_cnt 0 2006.173.17:04:33.25#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.17:04:33.37#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.17:04:33.37#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.17:04:33.37#ibcon#enter wrdev, iclass 7, count 0 2006.173.17:04:33.37#ibcon#first serial, iclass 7, count 0 2006.173.17:04:33.37#ibcon#enter sib2, iclass 7, count 0 2006.173.17:04:33.37#ibcon#flushed, iclass 7, count 0 2006.173.17:04:33.37#ibcon#about to write, iclass 7, count 0 2006.173.17:04:33.37#ibcon#wrote, iclass 7, count 0 2006.173.17:04:33.37#ibcon#about to read 3, iclass 7, count 0 2006.173.17:04:33.39#ibcon#read 3, iclass 7, count 0 2006.173.17:04:33.39#ibcon#about to read 4, iclass 7, count 0 2006.173.17:04:33.39#ibcon#read 4, iclass 7, count 0 2006.173.17:04:33.39#ibcon#about to read 5, iclass 7, count 0 2006.173.17:04:33.39#ibcon#read 5, iclass 7, count 0 2006.173.17:04:33.39#ibcon#about to read 6, iclass 7, count 0 2006.173.17:04:33.39#ibcon#read 6, iclass 7, count 0 2006.173.17:04:33.39#ibcon#end of sib2, iclass 7, count 0 2006.173.17:04:33.39#ibcon#*mode == 0, iclass 7, count 0 2006.173.17:04:33.39#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.17:04:33.39#ibcon#[27=USB\r\n] 2006.173.17:04:33.39#ibcon#*before write, iclass 7, count 0 2006.173.17:04:33.39#ibcon#enter sib2, iclass 7, count 0 2006.173.17:04:33.39#ibcon#flushed, iclass 7, count 0 2006.173.17:04:33.39#ibcon#about to write, iclass 7, count 0 2006.173.17:04:33.39#ibcon#wrote, iclass 7, count 0 2006.173.17:04:33.39#ibcon#about to read 3, iclass 7, count 0 2006.173.17:04:33.42#ibcon#read 3, iclass 7, count 0 2006.173.17:04:33.42#ibcon#about to read 4, iclass 7, count 0 2006.173.17:04:33.42#ibcon#read 4, iclass 7, count 0 2006.173.17:04:33.42#ibcon#about to read 5, iclass 7, count 0 2006.173.17:04:33.42#ibcon#read 5, iclass 7, count 0 2006.173.17:04:33.42#ibcon#about to read 6, iclass 7, count 0 2006.173.17:04:33.42#ibcon#read 6, iclass 7, count 0 2006.173.17:04:33.42#ibcon#end of sib2, iclass 7, count 0 2006.173.17:04:33.42#ibcon#*after write, iclass 7, count 0 2006.173.17:04:33.42#ibcon#*before return 0, iclass 7, count 0 2006.173.17:04:33.42#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.17:04:33.42#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.173.17:04:33.42#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.17:04:33.42#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.17:04:33.42$vck44/vabw=wide 2006.173.17:04:33.42#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.17:04:33.42#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.17:04:33.42#ibcon#ireg 8 cls_cnt 0 2006.173.17:04:33.42#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.17:04:33.42#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.17:04:33.42#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.17:04:33.42#ibcon#enter wrdev, iclass 11, count 0 2006.173.17:04:33.42#ibcon#first serial, iclass 11, count 0 2006.173.17:04:33.42#ibcon#enter sib2, iclass 11, count 0 2006.173.17:04:33.42#ibcon#flushed, iclass 11, count 0 2006.173.17:04:33.42#ibcon#about to write, iclass 11, count 0 2006.173.17:04:33.42#ibcon#wrote, iclass 11, count 0 2006.173.17:04:33.42#ibcon#about to read 3, iclass 11, count 0 2006.173.17:04:33.44#ibcon#read 3, iclass 11, count 0 2006.173.17:04:33.44#ibcon#about to read 4, iclass 11, count 0 2006.173.17:04:33.44#ibcon#read 4, iclass 11, count 0 2006.173.17:04:33.44#ibcon#about to read 5, iclass 11, count 0 2006.173.17:04:33.44#ibcon#read 5, iclass 11, count 0 2006.173.17:04:33.44#ibcon#about to read 6, iclass 11, count 0 2006.173.17:04:33.44#ibcon#read 6, iclass 11, count 0 2006.173.17:04:33.44#ibcon#end of sib2, iclass 11, count 0 2006.173.17:04:33.44#ibcon#*mode == 0, iclass 11, count 0 2006.173.17:04:33.44#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.17:04:33.44#ibcon#[25=BW32\r\n] 2006.173.17:04:33.44#ibcon#*before write, iclass 11, count 0 2006.173.17:04:33.44#ibcon#enter sib2, iclass 11, count 0 2006.173.17:04:33.44#ibcon#flushed, iclass 11, count 0 2006.173.17:04:33.44#ibcon#about to write, iclass 11, count 0 2006.173.17:04:33.44#ibcon#wrote, iclass 11, count 0 2006.173.17:04:33.44#ibcon#about to read 3, iclass 11, count 0 2006.173.17:04:33.47#ibcon#read 3, iclass 11, count 0 2006.173.17:04:33.47#ibcon#about to read 4, iclass 11, count 0 2006.173.17:04:33.47#ibcon#read 4, iclass 11, count 0 2006.173.17:04:33.47#ibcon#about to read 5, iclass 11, count 0 2006.173.17:04:33.47#ibcon#read 5, iclass 11, count 0 2006.173.17:04:33.47#ibcon#about to read 6, iclass 11, count 0 2006.173.17:04:33.47#ibcon#read 6, iclass 11, count 0 2006.173.17:04:33.47#ibcon#end of sib2, iclass 11, count 0 2006.173.17:04:33.47#ibcon#*after write, iclass 11, count 0 2006.173.17:04:33.47#ibcon#*before return 0, iclass 11, count 0 2006.173.17:04:33.47#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.17:04:33.47#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.17:04:33.47#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.17:04:33.47#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.17:04:33.47$vck44/vbbw=wide 2006.173.17:04:33.47#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.17:04:33.47#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.17:04:33.47#ibcon#ireg 8 cls_cnt 0 2006.173.17:04:33.47#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.17:04:33.54#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.17:04:33.54#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.17:04:33.54#ibcon#enter wrdev, iclass 13, count 0 2006.173.17:04:33.54#ibcon#first serial, iclass 13, count 0 2006.173.17:04:33.54#ibcon#enter sib2, iclass 13, count 0 2006.173.17:04:33.54#ibcon#flushed, iclass 13, count 0 2006.173.17:04:33.54#ibcon#about to write, iclass 13, count 0 2006.173.17:04:33.54#ibcon#wrote, iclass 13, count 0 2006.173.17:04:33.54#ibcon#about to read 3, iclass 13, count 0 2006.173.17:04:33.56#ibcon#read 3, iclass 13, count 0 2006.173.17:04:33.56#ibcon#about to read 4, iclass 13, count 0 2006.173.17:04:33.56#ibcon#read 4, iclass 13, count 0 2006.173.17:04:33.56#ibcon#about to read 5, iclass 13, count 0 2006.173.17:04:33.56#ibcon#read 5, iclass 13, count 0 2006.173.17:04:33.56#ibcon#about to read 6, iclass 13, count 0 2006.173.17:04:33.56#ibcon#read 6, iclass 13, count 0 2006.173.17:04:33.56#ibcon#end of sib2, iclass 13, count 0 2006.173.17:04:33.56#ibcon#*mode == 0, iclass 13, count 0 2006.173.17:04:33.56#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.17:04:33.56#ibcon#[27=BW32\r\n] 2006.173.17:04:33.56#ibcon#*before write, iclass 13, count 0 2006.173.17:04:33.56#ibcon#enter sib2, iclass 13, count 0 2006.173.17:04:33.56#ibcon#flushed, iclass 13, count 0 2006.173.17:04:33.56#ibcon#about to write, iclass 13, count 0 2006.173.17:04:33.56#ibcon#wrote, iclass 13, count 0 2006.173.17:04:33.56#ibcon#about to read 3, iclass 13, count 0 2006.173.17:04:33.59#ibcon#read 3, iclass 13, count 0 2006.173.17:04:33.59#ibcon#about to read 4, iclass 13, count 0 2006.173.17:04:33.59#ibcon#read 4, iclass 13, count 0 2006.173.17:04:33.59#ibcon#about to read 5, iclass 13, count 0 2006.173.17:04:33.59#ibcon#read 5, iclass 13, count 0 2006.173.17:04:33.59#ibcon#about to read 6, iclass 13, count 0 2006.173.17:04:33.59#ibcon#read 6, iclass 13, count 0 2006.173.17:04:33.59#ibcon#end of sib2, iclass 13, count 0 2006.173.17:04:33.59#ibcon#*after write, iclass 13, count 0 2006.173.17:04:33.59#ibcon#*before return 0, iclass 13, count 0 2006.173.17:04:33.59#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.17:04:33.59#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.17:04:33.59#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.17:04:33.59#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.17:04:33.59$setupk4/ifdk4 2006.173.17:04:33.59$ifdk4/lo= 2006.173.17:04:33.59$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.17:04:33.59$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.17:04:33.59$ifdk4/patch= 2006.173.17:04:33.59$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.17:04:33.59$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.17:04:33.59$setupk4/!*+20s 2006.173.17:04:34.08#abcon#<5=/14 1.1 3.0 20.291001002.8\r\n> 2006.173.17:04:34.10#abcon#{5=INTERFACE CLEAR} 2006.173.17:04:34.16#abcon#[5=S1D000X0/0*\r\n] 2006.173.17:04:44.25#abcon#<5=/14 1.2 3.0 20.291001002.8\r\n> 2006.173.17:04:44.27#abcon#{5=INTERFACE CLEAR} 2006.173.17:04:44.33#abcon#[5=S1D000X0/0*\r\n] 2006.173.17:04:48.10$setupk4/"tpicd 2006.173.17:04:48.10$setupk4/echo=off 2006.173.17:04:48.10$setupk4/xlog=off 2006.173.17:04:48.10:!2006.173.17:05:47 2006.173.17:05:02.14#trakl#Source acquired 2006.173.17:05:02.14#flagr#flagr/antenna,acquired 2006.173.17:05:47.00:preob 2006.173.17:05:48.14/onsource/TRACKING 2006.173.17:05:48.14:!2006.173.17:05:57 2006.173.17:05:57.00:"tape 2006.173.17:05:57.00:"st=record 2006.173.17:05:57.00:data_valid=on 2006.173.17:05:57.00:midob 2006.173.17:05:57.14/onsource/TRACKING 2006.173.17:05:57.14/wx/20.28,1002.8,100 2006.173.17:05:57.33/cable/+6.5140E-03 2006.173.17:05:58.42/va/01,07,usb,yes,37,40 2006.173.17:05:58.42/va/02,06,usb,yes,37,38 2006.173.17:05:58.42/va/03,05,usb,yes,47,49 2006.173.17:05:58.42/va/04,06,usb,yes,38,40 2006.173.17:05:58.42/va/05,04,usb,yes,30,30 2006.173.17:05:58.42/va/06,03,usb,yes,42,42 2006.173.17:05:58.42/va/07,04,usb,yes,34,35 2006.173.17:05:58.42/va/08,04,usb,yes,29,35 2006.173.17:05:58.65/valo/01,524.99,yes,locked 2006.173.17:05:58.65/valo/02,534.99,yes,locked 2006.173.17:05:58.65/valo/03,564.99,yes,locked 2006.173.17:05:58.65/valo/04,624.99,yes,locked 2006.173.17:05:58.65/valo/05,734.99,yes,locked 2006.173.17:05:58.65/valo/06,814.99,yes,locked 2006.173.17:05:58.65/valo/07,864.99,yes,locked 2006.173.17:05:58.65/valo/08,884.99,yes,locked 2006.173.17:05:59.74/vb/01,04,usb,yes,30,28 2006.173.17:05:59.74/vb/02,04,usb,yes,33,32 2006.173.17:05:59.74/vb/03,04,usb,yes,29,32 2006.173.17:05:59.74/vb/04,04,usb,yes,34,33 2006.173.17:05:59.74/vb/05,04,usb,yes,27,29 2006.173.17:05:59.74/vb/06,04,usb,yes,31,27 2006.173.17:05:59.74/vb/07,04,usb,yes,31,31 2006.173.17:05:59.74/vb/08,04,usb,yes,28,32 2006.173.17:05:59.97/vblo/01,629.99,yes,locked 2006.173.17:05:59.97/vblo/02,634.99,yes,locked 2006.173.17:05:59.97/vblo/03,649.99,yes,locked 2006.173.17:05:59.97/vblo/04,679.99,yes,locked 2006.173.17:05:59.97/vblo/05,709.99,yes,locked 2006.173.17:05:59.97/vblo/06,719.99,yes,locked 2006.173.17:05:59.97/vblo/07,734.99,yes,locked 2006.173.17:05:59.97/vblo/08,744.99,yes,locked 2006.173.17:06:00.12/vabw/8 2006.173.17:06:00.27/vbbw/8 2006.173.17:06:00.36/xfe/off,on,14.5 2006.173.17:06:00.75/ifatt/23,28,28,28 2006.173.17:06:01.07/fmout-gps/S +4.04E-07 2006.173.17:06:01.11:!2006.173.17:06:37 2006.173.17:06:37.01:data_valid=off 2006.173.17:06:37.01:"et 2006.173.17:06:37.02:!+3s 2006.173.17:06:40.03:"tape 2006.173.17:06:40.03:postob 2006.173.17:06:40.16/cable/+6.5136E-03 2006.173.17:06:40.16/wx/20.28,1002.8,100 2006.173.17:06:40.22/fmout-gps/S +4.03E-07 2006.173.17:06:40.22:scan_name=173-1707,jd0606,730 2006.173.17:06:40.22:source=1749+096,175132.82,093900.7,2000.0,ccw 2006.173.17:06:42.13#flagr#flagr/antenna,new-source 2006.173.17:06:42.13:checkk5 2006.173.17:06:42.49/chk_autoobs//k5ts1/ autoobs is running! 2006.173.17:06:42.88/chk_autoobs//k5ts2/ autoobs is running! 2006.173.17:06:43.30/chk_autoobs//k5ts3/ autoobs is running! 2006.173.17:06:43.70/chk_autoobs//k5ts4/ autoobs is running! 2006.173.17:06:44.09/chk_obsdata//k5ts1/T1731705??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.173.17:06:44.48/chk_obsdata//k5ts2/T1731705??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.173.17:06:44.86/chk_obsdata//k5ts3/T1731705??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.173.17:06:45.26/chk_obsdata//k5ts4/T1731705??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.173.17:06:46.00/k5log//k5ts1_log_newline 2006.173.17:06:46.70/k5log//k5ts2_log_newline 2006.173.17:06:47.41/k5log//k5ts3_log_newline 2006.173.17:06:48.12/k5log//k5ts4_log_newline 2006.173.17:06:48.14/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.17:06:48.15:setupk4=1 2006.173.17:06:48.15$setupk4/echo=on 2006.173.17:06:48.15$setupk4/pcalon 2006.173.17:06:48.15$pcalon/"no phase cal control is implemented here 2006.173.17:06:48.15$setupk4/"tpicd=stop 2006.173.17:06:48.15$setupk4/"rec=synch_on 2006.173.17:06:48.15$setupk4/"rec_mode=128 2006.173.17:06:48.15$setupk4/!* 2006.173.17:06:48.15$setupk4/recpk4 2006.173.17:06:48.15$recpk4/recpatch= 2006.173.17:06:48.15$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.17:06:48.15$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.17:06:48.15$setupk4/vck44 2006.173.17:06:48.15$vck44/valo=1,524.99 2006.173.17:06:48.15#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.17:06:48.15#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.17:06:48.15#ibcon#ireg 17 cls_cnt 0 2006.173.17:06:48.15#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.17:06:48.15#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.17:06:48.15#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.17:06:48.15#ibcon#enter wrdev, iclass 38, count 0 2006.173.17:06:48.15#ibcon#first serial, iclass 38, count 0 2006.173.17:06:48.15#ibcon#enter sib2, iclass 38, count 0 2006.173.17:06:48.15#ibcon#flushed, iclass 38, count 0 2006.173.17:06:48.15#ibcon#about to write, iclass 38, count 0 2006.173.17:06:48.15#ibcon#wrote, iclass 38, count 0 2006.173.17:06:48.15#ibcon#about to read 3, iclass 38, count 0 2006.173.17:06:48.17#ibcon#read 3, iclass 38, count 0 2006.173.17:06:48.17#ibcon#about to read 4, iclass 38, count 0 2006.173.17:06:48.17#ibcon#read 4, iclass 38, count 0 2006.173.17:06:48.17#ibcon#about to read 5, iclass 38, count 0 2006.173.17:06:48.17#ibcon#read 5, iclass 38, count 0 2006.173.17:06:48.17#ibcon#about to read 6, iclass 38, count 0 2006.173.17:06:48.17#ibcon#read 6, iclass 38, count 0 2006.173.17:06:48.17#ibcon#end of sib2, iclass 38, count 0 2006.173.17:06:48.17#ibcon#*mode == 0, iclass 38, count 0 2006.173.17:06:48.17#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.17:06:48.17#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.17:06:48.17#ibcon#*before write, iclass 38, count 0 2006.173.17:06:48.17#ibcon#enter sib2, iclass 38, count 0 2006.173.17:06:48.17#ibcon#flushed, iclass 38, count 0 2006.173.17:06:48.17#ibcon#about to write, iclass 38, count 0 2006.173.17:06:48.17#ibcon#wrote, iclass 38, count 0 2006.173.17:06:48.17#ibcon#about to read 3, iclass 38, count 0 2006.173.17:06:48.22#ibcon#read 3, iclass 38, count 0 2006.173.17:06:48.22#ibcon#about to read 4, iclass 38, count 0 2006.173.17:06:48.22#ibcon#read 4, iclass 38, count 0 2006.173.17:06:48.22#ibcon#about to read 5, iclass 38, count 0 2006.173.17:06:48.22#ibcon#read 5, iclass 38, count 0 2006.173.17:06:48.22#ibcon#about to read 6, iclass 38, count 0 2006.173.17:06:48.22#ibcon#read 6, iclass 38, count 0 2006.173.17:06:48.22#ibcon#end of sib2, iclass 38, count 0 2006.173.17:06:48.22#ibcon#*after write, iclass 38, count 0 2006.173.17:06:48.22#ibcon#*before return 0, iclass 38, count 0 2006.173.17:06:48.22#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.17:06:48.22#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.17:06:48.22#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.17:06:48.22#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.17:06:48.22$vck44/va=1,7 2006.173.17:06:48.22#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.17:06:48.22#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.17:06:48.22#ibcon#ireg 11 cls_cnt 2 2006.173.17:06:48.22#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.17:06:48.22#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.17:06:48.22#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.17:06:48.22#ibcon#enter wrdev, iclass 40, count 2 2006.173.17:06:48.22#ibcon#first serial, iclass 40, count 2 2006.173.17:06:48.22#ibcon#enter sib2, iclass 40, count 2 2006.173.17:06:48.22#ibcon#flushed, iclass 40, count 2 2006.173.17:06:48.22#ibcon#about to write, iclass 40, count 2 2006.173.17:06:48.22#ibcon#wrote, iclass 40, count 2 2006.173.17:06:48.22#ibcon#about to read 3, iclass 40, count 2 2006.173.17:06:48.24#ibcon#read 3, iclass 40, count 2 2006.173.17:06:48.24#ibcon#about to read 4, iclass 40, count 2 2006.173.17:06:48.24#ibcon#read 4, iclass 40, count 2 2006.173.17:06:48.24#ibcon#about to read 5, iclass 40, count 2 2006.173.17:06:48.24#ibcon#read 5, iclass 40, count 2 2006.173.17:06:48.24#ibcon#about to read 6, iclass 40, count 2 2006.173.17:06:48.24#ibcon#read 6, iclass 40, count 2 2006.173.17:06:48.24#ibcon#end of sib2, iclass 40, count 2 2006.173.17:06:48.24#ibcon#*mode == 0, iclass 40, count 2 2006.173.17:06:48.24#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.17:06:48.24#ibcon#[25=AT01-07\r\n] 2006.173.17:06:48.24#ibcon#*before write, iclass 40, count 2 2006.173.17:06:48.24#ibcon#enter sib2, iclass 40, count 2 2006.173.17:06:48.24#ibcon#flushed, iclass 40, count 2 2006.173.17:06:48.24#ibcon#about to write, iclass 40, count 2 2006.173.17:06:48.24#ibcon#wrote, iclass 40, count 2 2006.173.17:06:48.24#ibcon#about to read 3, iclass 40, count 2 2006.173.17:06:48.27#ibcon#read 3, iclass 40, count 2 2006.173.17:06:48.27#ibcon#about to read 4, iclass 40, count 2 2006.173.17:06:48.27#ibcon#read 4, iclass 40, count 2 2006.173.17:06:48.27#ibcon#about to read 5, iclass 40, count 2 2006.173.17:06:48.27#ibcon#read 5, iclass 40, count 2 2006.173.17:06:48.27#ibcon#about to read 6, iclass 40, count 2 2006.173.17:06:48.27#ibcon#read 6, iclass 40, count 2 2006.173.17:06:48.27#ibcon#end of sib2, iclass 40, count 2 2006.173.17:06:48.27#ibcon#*after write, iclass 40, count 2 2006.173.17:06:48.27#ibcon#*before return 0, iclass 40, count 2 2006.173.17:06:48.27#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.17:06:48.27#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.17:06:48.27#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.17:06:48.27#ibcon#ireg 7 cls_cnt 0 2006.173.17:06:48.27#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.17:06:48.39#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.17:06:48.39#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.17:06:48.39#ibcon#enter wrdev, iclass 40, count 0 2006.173.17:06:48.39#ibcon#first serial, iclass 40, count 0 2006.173.17:06:48.39#ibcon#enter sib2, iclass 40, count 0 2006.173.17:06:48.39#ibcon#flushed, iclass 40, count 0 2006.173.17:06:48.39#ibcon#about to write, iclass 40, count 0 2006.173.17:06:48.39#ibcon#wrote, iclass 40, count 0 2006.173.17:06:48.39#ibcon#about to read 3, iclass 40, count 0 2006.173.17:06:48.41#ibcon#read 3, iclass 40, count 0 2006.173.17:06:48.41#ibcon#about to read 4, iclass 40, count 0 2006.173.17:06:48.41#ibcon#read 4, iclass 40, count 0 2006.173.17:06:48.41#ibcon#about to read 5, iclass 40, count 0 2006.173.17:06:48.41#ibcon#read 5, iclass 40, count 0 2006.173.17:06:48.41#ibcon#about to read 6, iclass 40, count 0 2006.173.17:06:48.41#ibcon#read 6, iclass 40, count 0 2006.173.17:06:48.41#ibcon#end of sib2, iclass 40, count 0 2006.173.17:06:48.41#ibcon#*mode == 0, iclass 40, count 0 2006.173.17:06:48.41#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.17:06:48.41#ibcon#[25=USB\r\n] 2006.173.17:06:48.41#ibcon#*before write, iclass 40, count 0 2006.173.17:06:48.41#ibcon#enter sib2, iclass 40, count 0 2006.173.17:06:48.41#ibcon#flushed, iclass 40, count 0 2006.173.17:06:48.41#ibcon#about to write, iclass 40, count 0 2006.173.17:06:48.41#ibcon#wrote, iclass 40, count 0 2006.173.17:06:48.41#ibcon#about to read 3, iclass 40, count 0 2006.173.17:06:48.44#ibcon#read 3, iclass 40, count 0 2006.173.17:06:48.44#ibcon#about to read 4, iclass 40, count 0 2006.173.17:06:48.44#ibcon#read 4, iclass 40, count 0 2006.173.17:06:48.44#ibcon#about to read 5, iclass 40, count 0 2006.173.17:06:48.44#ibcon#read 5, iclass 40, count 0 2006.173.17:06:48.44#ibcon#about to read 6, iclass 40, count 0 2006.173.17:06:48.44#ibcon#read 6, iclass 40, count 0 2006.173.17:06:48.44#ibcon#end of sib2, iclass 40, count 0 2006.173.17:06:48.44#ibcon#*after write, iclass 40, count 0 2006.173.17:06:48.44#ibcon#*before return 0, iclass 40, count 0 2006.173.17:06:48.44#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.17:06:48.44#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.17:06:48.44#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.17:06:48.44#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.17:06:48.44$vck44/valo=2,534.99 2006.173.17:06:48.44#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.17:06:48.44#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.17:06:48.44#ibcon#ireg 17 cls_cnt 0 2006.173.17:06:48.44#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.17:06:48.44#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.17:06:48.44#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.17:06:48.44#ibcon#enter wrdev, iclass 4, count 0 2006.173.17:06:48.44#ibcon#first serial, iclass 4, count 0 2006.173.17:06:48.44#ibcon#enter sib2, iclass 4, count 0 2006.173.17:06:48.44#ibcon#flushed, iclass 4, count 0 2006.173.17:06:48.44#ibcon#about to write, iclass 4, count 0 2006.173.17:06:48.44#ibcon#wrote, iclass 4, count 0 2006.173.17:06:48.44#ibcon#about to read 3, iclass 4, count 0 2006.173.17:06:48.46#ibcon#read 3, iclass 4, count 0 2006.173.17:06:48.46#ibcon#about to read 4, iclass 4, count 0 2006.173.17:06:48.46#ibcon#read 4, iclass 4, count 0 2006.173.17:06:48.46#ibcon#about to read 5, iclass 4, count 0 2006.173.17:06:48.46#ibcon#read 5, iclass 4, count 0 2006.173.17:06:48.46#ibcon#about to read 6, iclass 4, count 0 2006.173.17:06:48.46#ibcon#read 6, iclass 4, count 0 2006.173.17:06:48.46#ibcon#end of sib2, iclass 4, count 0 2006.173.17:06:48.46#ibcon#*mode == 0, iclass 4, count 0 2006.173.17:06:48.46#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.17:06:48.46#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.17:06:48.46#ibcon#*before write, iclass 4, count 0 2006.173.17:06:48.46#ibcon#enter sib2, iclass 4, count 0 2006.173.17:06:48.46#ibcon#flushed, iclass 4, count 0 2006.173.17:06:48.46#ibcon#about to write, iclass 4, count 0 2006.173.17:06:48.46#ibcon#wrote, iclass 4, count 0 2006.173.17:06:48.46#ibcon#about to read 3, iclass 4, count 0 2006.173.17:06:48.50#ibcon#read 3, iclass 4, count 0 2006.173.17:06:48.50#ibcon#about to read 4, iclass 4, count 0 2006.173.17:06:48.50#ibcon#read 4, iclass 4, count 0 2006.173.17:06:48.50#ibcon#about to read 5, iclass 4, count 0 2006.173.17:06:48.50#ibcon#read 5, iclass 4, count 0 2006.173.17:06:48.50#ibcon#about to read 6, iclass 4, count 0 2006.173.17:06:48.50#ibcon#read 6, iclass 4, count 0 2006.173.17:06:48.50#ibcon#end of sib2, iclass 4, count 0 2006.173.17:06:48.50#ibcon#*after write, iclass 4, count 0 2006.173.17:06:48.50#ibcon#*before return 0, iclass 4, count 0 2006.173.17:06:48.50#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.17:06:48.50#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.17:06:48.50#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.17:06:48.50#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.17:06:48.50$vck44/va=2,6 2006.173.17:06:48.50#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.17:06:48.50#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.17:06:48.50#ibcon#ireg 11 cls_cnt 2 2006.173.17:06:48.50#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.17:06:48.56#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.17:06:48.56#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.17:06:48.56#ibcon#enter wrdev, iclass 6, count 2 2006.173.17:06:48.56#ibcon#first serial, iclass 6, count 2 2006.173.17:06:48.56#ibcon#enter sib2, iclass 6, count 2 2006.173.17:06:48.56#ibcon#flushed, iclass 6, count 2 2006.173.17:06:48.56#ibcon#about to write, iclass 6, count 2 2006.173.17:06:48.56#ibcon#wrote, iclass 6, count 2 2006.173.17:06:48.56#ibcon#about to read 3, iclass 6, count 2 2006.173.17:06:48.58#ibcon#read 3, iclass 6, count 2 2006.173.17:06:48.58#ibcon#about to read 4, iclass 6, count 2 2006.173.17:06:48.58#ibcon#read 4, iclass 6, count 2 2006.173.17:06:48.58#ibcon#about to read 5, iclass 6, count 2 2006.173.17:06:48.58#ibcon#read 5, iclass 6, count 2 2006.173.17:06:48.58#ibcon#about to read 6, iclass 6, count 2 2006.173.17:06:48.58#ibcon#read 6, iclass 6, count 2 2006.173.17:06:48.58#ibcon#end of sib2, iclass 6, count 2 2006.173.17:06:48.58#ibcon#*mode == 0, iclass 6, count 2 2006.173.17:06:48.58#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.17:06:48.58#ibcon#[25=AT02-06\r\n] 2006.173.17:06:48.58#ibcon#*before write, iclass 6, count 2 2006.173.17:06:48.58#ibcon#enter sib2, iclass 6, count 2 2006.173.17:06:48.58#ibcon#flushed, iclass 6, count 2 2006.173.17:06:48.58#ibcon#about to write, iclass 6, count 2 2006.173.17:06:48.58#ibcon#wrote, iclass 6, count 2 2006.173.17:06:48.58#ibcon#about to read 3, iclass 6, count 2 2006.173.17:06:48.61#ibcon#read 3, iclass 6, count 2 2006.173.17:06:48.61#ibcon#about to read 4, iclass 6, count 2 2006.173.17:06:48.61#ibcon#read 4, iclass 6, count 2 2006.173.17:06:48.61#ibcon#about to read 5, iclass 6, count 2 2006.173.17:06:48.61#ibcon#read 5, iclass 6, count 2 2006.173.17:06:48.61#ibcon#about to read 6, iclass 6, count 2 2006.173.17:06:48.61#ibcon#read 6, iclass 6, count 2 2006.173.17:06:48.61#ibcon#end of sib2, iclass 6, count 2 2006.173.17:06:48.61#ibcon#*after write, iclass 6, count 2 2006.173.17:06:48.61#ibcon#*before return 0, iclass 6, count 2 2006.173.17:06:48.61#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.17:06:48.61#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.17:06:48.61#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.17:06:48.61#ibcon#ireg 7 cls_cnt 0 2006.173.17:06:48.61#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.17:06:48.73#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.17:06:48.73#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.17:06:48.73#ibcon#enter wrdev, iclass 6, count 0 2006.173.17:06:48.73#ibcon#first serial, iclass 6, count 0 2006.173.17:06:48.73#ibcon#enter sib2, iclass 6, count 0 2006.173.17:06:48.73#ibcon#flushed, iclass 6, count 0 2006.173.17:06:48.73#ibcon#about to write, iclass 6, count 0 2006.173.17:06:48.73#ibcon#wrote, iclass 6, count 0 2006.173.17:06:48.73#ibcon#about to read 3, iclass 6, count 0 2006.173.17:06:48.75#ibcon#read 3, iclass 6, count 0 2006.173.17:06:48.75#ibcon#about to read 4, iclass 6, count 0 2006.173.17:06:48.75#ibcon#read 4, iclass 6, count 0 2006.173.17:06:48.75#ibcon#about to read 5, iclass 6, count 0 2006.173.17:06:48.75#ibcon#read 5, iclass 6, count 0 2006.173.17:06:48.75#ibcon#about to read 6, iclass 6, count 0 2006.173.17:06:48.75#ibcon#read 6, iclass 6, count 0 2006.173.17:06:48.75#ibcon#end of sib2, iclass 6, count 0 2006.173.17:06:48.75#ibcon#*mode == 0, iclass 6, count 0 2006.173.17:06:48.75#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.17:06:48.75#ibcon#[25=USB\r\n] 2006.173.17:06:48.75#ibcon#*before write, iclass 6, count 0 2006.173.17:06:48.75#ibcon#enter sib2, iclass 6, count 0 2006.173.17:06:48.75#ibcon#flushed, iclass 6, count 0 2006.173.17:06:48.75#ibcon#about to write, iclass 6, count 0 2006.173.17:06:48.75#ibcon#wrote, iclass 6, count 0 2006.173.17:06:48.75#ibcon#about to read 3, iclass 6, count 0 2006.173.17:06:48.78#ibcon#read 3, iclass 6, count 0 2006.173.17:06:48.78#ibcon#about to read 4, iclass 6, count 0 2006.173.17:06:48.78#ibcon#read 4, iclass 6, count 0 2006.173.17:06:48.78#ibcon#about to read 5, iclass 6, count 0 2006.173.17:06:48.78#ibcon#read 5, iclass 6, count 0 2006.173.17:06:48.78#ibcon#about to read 6, iclass 6, count 0 2006.173.17:06:48.78#ibcon#read 6, iclass 6, count 0 2006.173.17:06:48.78#ibcon#end of sib2, iclass 6, count 0 2006.173.17:06:48.78#ibcon#*after write, iclass 6, count 0 2006.173.17:06:48.78#ibcon#*before return 0, iclass 6, count 0 2006.173.17:06:48.78#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.17:06:48.78#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.17:06:48.78#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.17:06:48.78#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.17:06:48.78$vck44/valo=3,564.99 2006.173.17:06:48.78#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.17:06:48.78#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.17:06:48.78#ibcon#ireg 17 cls_cnt 0 2006.173.17:06:48.78#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.17:06:48.78#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.17:06:48.78#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.17:06:48.78#ibcon#enter wrdev, iclass 10, count 0 2006.173.17:06:48.78#ibcon#first serial, iclass 10, count 0 2006.173.17:06:48.78#ibcon#enter sib2, iclass 10, count 0 2006.173.17:06:48.78#ibcon#flushed, iclass 10, count 0 2006.173.17:06:48.78#ibcon#about to write, iclass 10, count 0 2006.173.17:06:48.78#ibcon#wrote, iclass 10, count 0 2006.173.17:06:48.78#ibcon#about to read 3, iclass 10, count 0 2006.173.17:06:48.80#ibcon#read 3, iclass 10, count 0 2006.173.17:06:48.80#ibcon#about to read 4, iclass 10, count 0 2006.173.17:06:48.80#ibcon#read 4, iclass 10, count 0 2006.173.17:06:48.80#ibcon#about to read 5, iclass 10, count 0 2006.173.17:06:48.80#ibcon#read 5, iclass 10, count 0 2006.173.17:06:48.80#ibcon#about to read 6, iclass 10, count 0 2006.173.17:06:48.80#ibcon#read 6, iclass 10, count 0 2006.173.17:06:48.80#ibcon#end of sib2, iclass 10, count 0 2006.173.17:06:48.80#ibcon#*mode == 0, iclass 10, count 0 2006.173.17:06:48.80#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.17:06:48.80#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.17:06:48.80#ibcon#*before write, iclass 10, count 0 2006.173.17:06:48.80#ibcon#enter sib2, iclass 10, count 0 2006.173.17:06:48.80#ibcon#flushed, iclass 10, count 0 2006.173.17:06:48.80#ibcon#about to write, iclass 10, count 0 2006.173.17:06:48.80#ibcon#wrote, iclass 10, count 0 2006.173.17:06:48.80#ibcon#about to read 3, iclass 10, count 0 2006.173.17:06:48.84#ibcon#read 3, iclass 10, count 0 2006.173.17:06:48.84#ibcon#about to read 4, iclass 10, count 0 2006.173.17:06:48.84#ibcon#read 4, iclass 10, count 0 2006.173.17:06:48.84#ibcon#about to read 5, iclass 10, count 0 2006.173.17:06:48.84#ibcon#read 5, iclass 10, count 0 2006.173.17:06:48.84#ibcon#about to read 6, iclass 10, count 0 2006.173.17:06:48.84#ibcon#read 6, iclass 10, count 0 2006.173.17:06:48.84#ibcon#end of sib2, iclass 10, count 0 2006.173.17:06:48.84#ibcon#*after write, iclass 10, count 0 2006.173.17:06:48.84#ibcon#*before return 0, iclass 10, count 0 2006.173.17:06:48.84#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.17:06:48.84#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.17:06:48.84#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.17:06:48.84#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.17:06:48.84$vck44/va=3,5 2006.173.17:06:48.84#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.17:06:48.84#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.17:06:48.84#ibcon#ireg 11 cls_cnt 2 2006.173.17:06:48.84#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.17:06:48.90#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.17:06:48.90#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.17:06:48.90#ibcon#enter wrdev, iclass 12, count 2 2006.173.17:06:48.90#ibcon#first serial, iclass 12, count 2 2006.173.17:06:48.90#ibcon#enter sib2, iclass 12, count 2 2006.173.17:06:48.90#ibcon#flushed, iclass 12, count 2 2006.173.17:06:48.90#ibcon#about to write, iclass 12, count 2 2006.173.17:06:48.90#ibcon#wrote, iclass 12, count 2 2006.173.17:06:48.90#ibcon#about to read 3, iclass 12, count 2 2006.173.17:06:48.92#ibcon#read 3, iclass 12, count 2 2006.173.17:06:48.92#ibcon#about to read 4, iclass 12, count 2 2006.173.17:06:48.92#ibcon#read 4, iclass 12, count 2 2006.173.17:06:48.92#ibcon#about to read 5, iclass 12, count 2 2006.173.17:06:48.92#ibcon#read 5, iclass 12, count 2 2006.173.17:06:48.92#ibcon#about to read 6, iclass 12, count 2 2006.173.17:06:48.92#ibcon#read 6, iclass 12, count 2 2006.173.17:06:48.92#ibcon#end of sib2, iclass 12, count 2 2006.173.17:06:48.92#ibcon#*mode == 0, iclass 12, count 2 2006.173.17:06:48.92#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.17:06:48.92#ibcon#[25=AT03-05\r\n] 2006.173.17:06:48.92#ibcon#*before write, iclass 12, count 2 2006.173.17:06:48.92#ibcon#enter sib2, iclass 12, count 2 2006.173.17:06:48.92#ibcon#flushed, iclass 12, count 2 2006.173.17:06:48.92#ibcon#about to write, iclass 12, count 2 2006.173.17:06:48.92#ibcon#wrote, iclass 12, count 2 2006.173.17:06:48.92#ibcon#about to read 3, iclass 12, count 2 2006.173.17:06:48.95#ibcon#read 3, iclass 12, count 2 2006.173.17:06:48.95#ibcon#about to read 4, iclass 12, count 2 2006.173.17:06:48.95#ibcon#read 4, iclass 12, count 2 2006.173.17:06:48.95#ibcon#about to read 5, iclass 12, count 2 2006.173.17:06:48.95#ibcon#read 5, iclass 12, count 2 2006.173.17:06:48.95#ibcon#about to read 6, iclass 12, count 2 2006.173.17:06:48.95#ibcon#read 6, iclass 12, count 2 2006.173.17:06:48.95#ibcon#end of sib2, iclass 12, count 2 2006.173.17:06:48.95#ibcon#*after write, iclass 12, count 2 2006.173.17:06:48.95#ibcon#*before return 0, iclass 12, count 2 2006.173.17:06:48.95#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.17:06:48.95#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.17:06:48.95#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.17:06:48.95#ibcon#ireg 7 cls_cnt 0 2006.173.17:06:48.95#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.17:06:49.07#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.17:06:49.07#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.17:06:49.07#ibcon#enter wrdev, iclass 12, count 0 2006.173.17:06:49.07#ibcon#first serial, iclass 12, count 0 2006.173.17:06:49.07#ibcon#enter sib2, iclass 12, count 0 2006.173.17:06:49.07#ibcon#flushed, iclass 12, count 0 2006.173.17:06:49.07#ibcon#about to write, iclass 12, count 0 2006.173.17:06:49.07#ibcon#wrote, iclass 12, count 0 2006.173.17:06:49.07#ibcon#about to read 3, iclass 12, count 0 2006.173.17:06:49.09#ibcon#read 3, iclass 12, count 0 2006.173.17:06:49.09#ibcon#about to read 4, iclass 12, count 0 2006.173.17:06:49.09#ibcon#read 4, iclass 12, count 0 2006.173.17:06:49.09#ibcon#about to read 5, iclass 12, count 0 2006.173.17:06:49.09#ibcon#read 5, iclass 12, count 0 2006.173.17:06:49.09#ibcon#about to read 6, iclass 12, count 0 2006.173.17:06:49.09#ibcon#read 6, iclass 12, count 0 2006.173.17:06:49.09#ibcon#end of sib2, iclass 12, count 0 2006.173.17:06:49.09#ibcon#*mode == 0, iclass 12, count 0 2006.173.17:06:49.09#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.17:06:49.09#ibcon#[25=USB\r\n] 2006.173.17:06:49.09#ibcon#*before write, iclass 12, count 0 2006.173.17:06:49.09#ibcon#enter sib2, iclass 12, count 0 2006.173.17:06:49.09#ibcon#flushed, iclass 12, count 0 2006.173.17:06:49.09#ibcon#about to write, iclass 12, count 0 2006.173.17:06:49.09#ibcon#wrote, iclass 12, count 0 2006.173.17:06:49.09#ibcon#about to read 3, iclass 12, count 0 2006.173.17:06:49.12#ibcon#read 3, iclass 12, count 0 2006.173.17:06:49.12#ibcon#about to read 4, iclass 12, count 0 2006.173.17:06:49.12#ibcon#read 4, iclass 12, count 0 2006.173.17:06:49.12#ibcon#about to read 5, iclass 12, count 0 2006.173.17:06:49.12#ibcon#read 5, iclass 12, count 0 2006.173.17:06:49.12#ibcon#about to read 6, iclass 12, count 0 2006.173.17:06:49.12#ibcon#read 6, iclass 12, count 0 2006.173.17:06:49.12#ibcon#end of sib2, iclass 12, count 0 2006.173.17:06:49.12#ibcon#*after write, iclass 12, count 0 2006.173.17:06:49.12#ibcon#*before return 0, iclass 12, count 0 2006.173.17:06:49.12#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.17:06:49.12#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.17:06:49.12#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.17:06:49.12#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.17:06:49.12$vck44/valo=4,624.99 2006.173.17:06:49.12#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.17:06:49.12#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.17:06:49.12#ibcon#ireg 17 cls_cnt 0 2006.173.17:06:49.12#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.17:06:49.12#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.17:06:49.12#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.17:06:49.12#ibcon#enter wrdev, iclass 14, count 0 2006.173.17:06:49.12#ibcon#first serial, iclass 14, count 0 2006.173.17:06:49.12#ibcon#enter sib2, iclass 14, count 0 2006.173.17:06:49.12#ibcon#flushed, iclass 14, count 0 2006.173.17:06:49.12#ibcon#about to write, iclass 14, count 0 2006.173.17:06:49.12#ibcon#wrote, iclass 14, count 0 2006.173.17:06:49.12#ibcon#about to read 3, iclass 14, count 0 2006.173.17:06:49.14#ibcon#read 3, iclass 14, count 0 2006.173.17:06:49.14#ibcon#about to read 4, iclass 14, count 0 2006.173.17:06:49.14#ibcon#read 4, iclass 14, count 0 2006.173.17:06:49.14#ibcon#about to read 5, iclass 14, count 0 2006.173.17:06:49.14#ibcon#read 5, iclass 14, count 0 2006.173.17:06:49.14#ibcon#about to read 6, iclass 14, count 0 2006.173.17:06:49.14#ibcon#read 6, iclass 14, count 0 2006.173.17:06:49.14#ibcon#end of sib2, iclass 14, count 0 2006.173.17:06:49.14#ibcon#*mode == 0, iclass 14, count 0 2006.173.17:06:49.14#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.17:06:49.14#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.17:06:49.14#ibcon#*before write, iclass 14, count 0 2006.173.17:06:49.14#ibcon#enter sib2, iclass 14, count 0 2006.173.17:06:49.14#ibcon#flushed, iclass 14, count 0 2006.173.17:06:49.14#ibcon#about to write, iclass 14, count 0 2006.173.17:06:49.14#ibcon#wrote, iclass 14, count 0 2006.173.17:06:49.14#ibcon#about to read 3, iclass 14, count 0 2006.173.17:06:49.18#ibcon#read 3, iclass 14, count 0 2006.173.17:06:49.18#ibcon#about to read 4, iclass 14, count 0 2006.173.17:06:49.18#ibcon#read 4, iclass 14, count 0 2006.173.17:06:49.18#ibcon#about to read 5, iclass 14, count 0 2006.173.17:06:49.18#ibcon#read 5, iclass 14, count 0 2006.173.17:06:49.18#ibcon#about to read 6, iclass 14, count 0 2006.173.17:06:49.18#ibcon#read 6, iclass 14, count 0 2006.173.17:06:49.18#ibcon#end of sib2, iclass 14, count 0 2006.173.17:06:49.18#ibcon#*after write, iclass 14, count 0 2006.173.17:06:49.18#ibcon#*before return 0, iclass 14, count 0 2006.173.17:06:49.18#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.17:06:49.18#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.17:06:49.18#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.17:06:49.18#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.17:06:49.18$vck44/va=4,6 2006.173.17:06:49.18#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.17:06:49.18#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.17:06:49.18#ibcon#ireg 11 cls_cnt 2 2006.173.17:06:49.18#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.17:06:49.24#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.17:06:49.24#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.17:06:49.24#ibcon#enter wrdev, iclass 16, count 2 2006.173.17:06:49.24#ibcon#first serial, iclass 16, count 2 2006.173.17:06:49.24#ibcon#enter sib2, iclass 16, count 2 2006.173.17:06:49.24#ibcon#flushed, iclass 16, count 2 2006.173.17:06:49.24#ibcon#about to write, iclass 16, count 2 2006.173.17:06:49.24#ibcon#wrote, iclass 16, count 2 2006.173.17:06:49.24#ibcon#about to read 3, iclass 16, count 2 2006.173.17:06:49.26#ibcon#read 3, iclass 16, count 2 2006.173.17:06:49.26#ibcon#about to read 4, iclass 16, count 2 2006.173.17:06:49.26#ibcon#read 4, iclass 16, count 2 2006.173.17:06:49.26#ibcon#about to read 5, iclass 16, count 2 2006.173.17:06:49.26#ibcon#read 5, iclass 16, count 2 2006.173.17:06:49.26#ibcon#about to read 6, iclass 16, count 2 2006.173.17:06:49.26#ibcon#read 6, iclass 16, count 2 2006.173.17:06:49.26#ibcon#end of sib2, iclass 16, count 2 2006.173.17:06:49.26#ibcon#*mode == 0, iclass 16, count 2 2006.173.17:06:49.26#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.17:06:49.26#ibcon#[25=AT04-06\r\n] 2006.173.17:06:49.26#ibcon#*before write, iclass 16, count 2 2006.173.17:06:49.26#ibcon#enter sib2, iclass 16, count 2 2006.173.17:06:49.26#ibcon#flushed, iclass 16, count 2 2006.173.17:06:49.26#ibcon#about to write, iclass 16, count 2 2006.173.17:06:49.26#ibcon#wrote, iclass 16, count 2 2006.173.17:06:49.26#ibcon#about to read 3, iclass 16, count 2 2006.173.17:06:49.29#ibcon#read 3, iclass 16, count 2 2006.173.17:06:49.29#ibcon#about to read 4, iclass 16, count 2 2006.173.17:06:49.29#ibcon#read 4, iclass 16, count 2 2006.173.17:06:49.29#ibcon#about to read 5, iclass 16, count 2 2006.173.17:06:49.29#ibcon#read 5, iclass 16, count 2 2006.173.17:06:49.29#ibcon#about to read 6, iclass 16, count 2 2006.173.17:06:49.29#ibcon#read 6, iclass 16, count 2 2006.173.17:06:49.29#ibcon#end of sib2, iclass 16, count 2 2006.173.17:06:49.29#ibcon#*after write, iclass 16, count 2 2006.173.17:06:49.29#ibcon#*before return 0, iclass 16, count 2 2006.173.17:06:49.29#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.17:06:49.29#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.17:06:49.29#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.17:06:49.29#ibcon#ireg 7 cls_cnt 0 2006.173.17:06:49.29#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.17:06:49.41#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.17:06:49.41#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.17:06:49.41#ibcon#enter wrdev, iclass 16, count 0 2006.173.17:06:49.41#ibcon#first serial, iclass 16, count 0 2006.173.17:06:49.41#ibcon#enter sib2, iclass 16, count 0 2006.173.17:06:49.41#ibcon#flushed, iclass 16, count 0 2006.173.17:06:49.41#ibcon#about to write, iclass 16, count 0 2006.173.17:06:49.41#ibcon#wrote, iclass 16, count 0 2006.173.17:06:49.41#ibcon#about to read 3, iclass 16, count 0 2006.173.17:06:49.43#ibcon#read 3, iclass 16, count 0 2006.173.17:06:49.43#ibcon#about to read 4, iclass 16, count 0 2006.173.17:06:49.43#ibcon#read 4, iclass 16, count 0 2006.173.17:06:49.43#ibcon#about to read 5, iclass 16, count 0 2006.173.17:06:49.43#ibcon#read 5, iclass 16, count 0 2006.173.17:06:49.43#ibcon#about to read 6, iclass 16, count 0 2006.173.17:06:49.43#ibcon#read 6, iclass 16, count 0 2006.173.17:06:49.43#ibcon#end of sib2, iclass 16, count 0 2006.173.17:06:49.43#ibcon#*mode == 0, iclass 16, count 0 2006.173.17:06:49.43#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.17:06:49.43#ibcon#[25=USB\r\n] 2006.173.17:06:49.43#ibcon#*before write, iclass 16, count 0 2006.173.17:06:49.43#ibcon#enter sib2, iclass 16, count 0 2006.173.17:06:49.43#ibcon#flushed, iclass 16, count 0 2006.173.17:06:49.43#ibcon#about to write, iclass 16, count 0 2006.173.17:06:49.43#ibcon#wrote, iclass 16, count 0 2006.173.17:06:49.43#ibcon#about to read 3, iclass 16, count 0 2006.173.17:06:49.46#ibcon#read 3, iclass 16, count 0 2006.173.17:06:49.46#ibcon#about to read 4, iclass 16, count 0 2006.173.17:06:49.46#ibcon#read 4, iclass 16, count 0 2006.173.17:06:49.46#ibcon#about to read 5, iclass 16, count 0 2006.173.17:06:49.46#ibcon#read 5, iclass 16, count 0 2006.173.17:06:49.46#ibcon#about to read 6, iclass 16, count 0 2006.173.17:06:49.46#ibcon#read 6, iclass 16, count 0 2006.173.17:06:49.46#ibcon#end of sib2, iclass 16, count 0 2006.173.17:06:49.46#ibcon#*after write, iclass 16, count 0 2006.173.17:06:49.46#ibcon#*before return 0, iclass 16, count 0 2006.173.17:06:49.46#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.17:06:49.46#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.17:06:49.46#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.17:06:49.46#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.17:06:49.46$vck44/valo=5,734.99 2006.173.17:06:49.46#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.17:06:49.46#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.17:06:49.46#ibcon#ireg 17 cls_cnt 0 2006.173.17:06:49.46#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.17:06:49.46#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.17:06:49.46#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.17:06:49.46#ibcon#enter wrdev, iclass 18, count 0 2006.173.17:06:49.46#ibcon#first serial, iclass 18, count 0 2006.173.17:06:49.46#ibcon#enter sib2, iclass 18, count 0 2006.173.17:06:49.46#ibcon#flushed, iclass 18, count 0 2006.173.17:06:49.46#ibcon#about to write, iclass 18, count 0 2006.173.17:06:49.46#ibcon#wrote, iclass 18, count 0 2006.173.17:06:49.46#ibcon#about to read 3, iclass 18, count 0 2006.173.17:06:49.48#ibcon#read 3, iclass 18, count 0 2006.173.17:06:49.48#ibcon#about to read 4, iclass 18, count 0 2006.173.17:06:49.48#ibcon#read 4, iclass 18, count 0 2006.173.17:06:49.48#ibcon#about to read 5, iclass 18, count 0 2006.173.17:06:49.48#ibcon#read 5, iclass 18, count 0 2006.173.17:06:49.48#ibcon#about to read 6, iclass 18, count 0 2006.173.17:06:49.48#ibcon#read 6, iclass 18, count 0 2006.173.17:06:49.48#ibcon#end of sib2, iclass 18, count 0 2006.173.17:06:49.48#ibcon#*mode == 0, iclass 18, count 0 2006.173.17:06:49.48#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.17:06:49.48#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.17:06:49.48#ibcon#*before write, iclass 18, count 0 2006.173.17:06:49.48#ibcon#enter sib2, iclass 18, count 0 2006.173.17:06:49.48#ibcon#flushed, iclass 18, count 0 2006.173.17:06:49.48#ibcon#about to write, iclass 18, count 0 2006.173.17:06:49.48#ibcon#wrote, iclass 18, count 0 2006.173.17:06:49.48#ibcon#about to read 3, iclass 18, count 0 2006.173.17:06:49.52#ibcon#read 3, iclass 18, count 0 2006.173.17:06:49.52#ibcon#about to read 4, iclass 18, count 0 2006.173.17:06:49.52#ibcon#read 4, iclass 18, count 0 2006.173.17:06:49.52#ibcon#about to read 5, iclass 18, count 0 2006.173.17:06:49.52#ibcon#read 5, iclass 18, count 0 2006.173.17:06:49.52#ibcon#about to read 6, iclass 18, count 0 2006.173.17:06:49.52#ibcon#read 6, iclass 18, count 0 2006.173.17:06:49.52#ibcon#end of sib2, iclass 18, count 0 2006.173.17:06:49.52#ibcon#*after write, iclass 18, count 0 2006.173.17:06:49.52#ibcon#*before return 0, iclass 18, count 0 2006.173.17:06:49.52#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.17:06:49.52#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.17:06:49.52#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.17:06:49.52#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.17:06:49.52$vck44/va=5,4 2006.173.17:06:49.52#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.17:06:49.52#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.17:06:49.52#ibcon#ireg 11 cls_cnt 2 2006.173.17:06:49.52#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.17:06:49.58#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.17:06:49.58#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.17:06:49.58#ibcon#enter wrdev, iclass 20, count 2 2006.173.17:06:49.58#ibcon#first serial, iclass 20, count 2 2006.173.17:06:49.58#ibcon#enter sib2, iclass 20, count 2 2006.173.17:06:49.58#ibcon#flushed, iclass 20, count 2 2006.173.17:06:49.58#ibcon#about to write, iclass 20, count 2 2006.173.17:06:49.58#ibcon#wrote, iclass 20, count 2 2006.173.17:06:49.58#ibcon#about to read 3, iclass 20, count 2 2006.173.17:06:49.60#ibcon#read 3, iclass 20, count 2 2006.173.17:06:49.60#ibcon#about to read 4, iclass 20, count 2 2006.173.17:06:49.60#ibcon#read 4, iclass 20, count 2 2006.173.17:06:49.60#ibcon#about to read 5, iclass 20, count 2 2006.173.17:06:49.60#ibcon#read 5, iclass 20, count 2 2006.173.17:06:49.60#ibcon#about to read 6, iclass 20, count 2 2006.173.17:06:49.60#ibcon#read 6, iclass 20, count 2 2006.173.17:06:49.60#ibcon#end of sib2, iclass 20, count 2 2006.173.17:06:49.60#ibcon#*mode == 0, iclass 20, count 2 2006.173.17:06:49.60#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.17:06:49.60#ibcon#[25=AT05-04\r\n] 2006.173.17:06:49.60#ibcon#*before write, iclass 20, count 2 2006.173.17:06:49.60#ibcon#enter sib2, iclass 20, count 2 2006.173.17:06:49.60#ibcon#flushed, iclass 20, count 2 2006.173.17:06:49.60#ibcon#about to write, iclass 20, count 2 2006.173.17:06:49.60#ibcon#wrote, iclass 20, count 2 2006.173.17:06:49.60#ibcon#about to read 3, iclass 20, count 2 2006.173.17:06:49.63#ibcon#read 3, iclass 20, count 2 2006.173.17:06:49.63#ibcon#about to read 4, iclass 20, count 2 2006.173.17:06:49.63#ibcon#read 4, iclass 20, count 2 2006.173.17:06:49.63#ibcon#about to read 5, iclass 20, count 2 2006.173.17:06:49.63#ibcon#read 5, iclass 20, count 2 2006.173.17:06:49.63#ibcon#about to read 6, iclass 20, count 2 2006.173.17:06:49.63#ibcon#read 6, iclass 20, count 2 2006.173.17:06:49.63#ibcon#end of sib2, iclass 20, count 2 2006.173.17:06:49.63#ibcon#*after write, iclass 20, count 2 2006.173.17:06:49.63#ibcon#*before return 0, iclass 20, count 2 2006.173.17:06:49.63#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.17:06:49.63#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.17:06:49.63#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.17:06:49.63#ibcon#ireg 7 cls_cnt 0 2006.173.17:06:49.63#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.17:06:49.75#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.17:06:49.75#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.17:06:49.75#ibcon#enter wrdev, iclass 20, count 0 2006.173.17:06:49.75#ibcon#first serial, iclass 20, count 0 2006.173.17:06:49.75#ibcon#enter sib2, iclass 20, count 0 2006.173.17:06:49.75#ibcon#flushed, iclass 20, count 0 2006.173.17:06:49.75#ibcon#about to write, iclass 20, count 0 2006.173.17:06:49.75#ibcon#wrote, iclass 20, count 0 2006.173.17:06:49.75#ibcon#about to read 3, iclass 20, count 0 2006.173.17:06:49.77#ibcon#read 3, iclass 20, count 0 2006.173.17:06:49.77#ibcon#about to read 4, iclass 20, count 0 2006.173.17:06:49.77#ibcon#read 4, iclass 20, count 0 2006.173.17:06:49.77#ibcon#about to read 5, iclass 20, count 0 2006.173.17:06:49.77#ibcon#read 5, iclass 20, count 0 2006.173.17:06:49.77#ibcon#about to read 6, iclass 20, count 0 2006.173.17:06:49.77#ibcon#read 6, iclass 20, count 0 2006.173.17:06:49.77#ibcon#end of sib2, iclass 20, count 0 2006.173.17:06:49.77#ibcon#*mode == 0, iclass 20, count 0 2006.173.17:06:49.77#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.17:06:49.77#ibcon#[25=USB\r\n] 2006.173.17:06:49.77#ibcon#*before write, iclass 20, count 0 2006.173.17:06:49.77#ibcon#enter sib2, iclass 20, count 0 2006.173.17:06:49.77#ibcon#flushed, iclass 20, count 0 2006.173.17:06:49.77#ibcon#about to write, iclass 20, count 0 2006.173.17:06:49.77#ibcon#wrote, iclass 20, count 0 2006.173.17:06:49.77#ibcon#about to read 3, iclass 20, count 0 2006.173.17:06:49.80#ibcon#read 3, iclass 20, count 0 2006.173.17:06:49.80#ibcon#about to read 4, iclass 20, count 0 2006.173.17:06:49.80#ibcon#read 4, iclass 20, count 0 2006.173.17:06:49.80#ibcon#about to read 5, iclass 20, count 0 2006.173.17:06:49.80#ibcon#read 5, iclass 20, count 0 2006.173.17:06:49.80#ibcon#about to read 6, iclass 20, count 0 2006.173.17:06:49.80#ibcon#read 6, iclass 20, count 0 2006.173.17:06:49.80#ibcon#end of sib2, iclass 20, count 0 2006.173.17:06:49.80#ibcon#*after write, iclass 20, count 0 2006.173.17:06:49.80#ibcon#*before return 0, iclass 20, count 0 2006.173.17:06:49.80#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.17:06:49.80#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.17:06:49.80#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.17:06:49.80#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.17:06:49.80$vck44/valo=6,814.99 2006.173.17:06:49.80#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.17:06:49.80#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.17:06:49.80#ibcon#ireg 17 cls_cnt 0 2006.173.17:06:49.80#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.17:06:49.80#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.17:06:49.80#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.17:06:49.80#ibcon#enter wrdev, iclass 22, count 0 2006.173.17:06:49.80#ibcon#first serial, iclass 22, count 0 2006.173.17:06:49.80#ibcon#enter sib2, iclass 22, count 0 2006.173.17:06:49.80#ibcon#flushed, iclass 22, count 0 2006.173.17:06:49.80#ibcon#about to write, iclass 22, count 0 2006.173.17:06:49.80#ibcon#wrote, iclass 22, count 0 2006.173.17:06:49.80#ibcon#about to read 3, iclass 22, count 0 2006.173.17:06:49.82#ibcon#read 3, iclass 22, count 0 2006.173.17:06:49.82#ibcon#about to read 4, iclass 22, count 0 2006.173.17:06:49.82#ibcon#read 4, iclass 22, count 0 2006.173.17:06:49.82#ibcon#about to read 5, iclass 22, count 0 2006.173.17:06:49.82#ibcon#read 5, iclass 22, count 0 2006.173.17:06:49.82#ibcon#about to read 6, iclass 22, count 0 2006.173.17:06:49.82#ibcon#read 6, iclass 22, count 0 2006.173.17:06:49.82#ibcon#end of sib2, iclass 22, count 0 2006.173.17:06:49.82#ibcon#*mode == 0, iclass 22, count 0 2006.173.17:06:49.82#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.17:06:49.82#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.17:06:49.82#ibcon#*before write, iclass 22, count 0 2006.173.17:06:49.82#ibcon#enter sib2, iclass 22, count 0 2006.173.17:06:49.82#ibcon#flushed, iclass 22, count 0 2006.173.17:06:49.82#ibcon#about to write, iclass 22, count 0 2006.173.17:06:49.82#ibcon#wrote, iclass 22, count 0 2006.173.17:06:49.82#ibcon#about to read 3, iclass 22, count 0 2006.173.17:06:49.86#ibcon#read 3, iclass 22, count 0 2006.173.17:06:49.86#ibcon#about to read 4, iclass 22, count 0 2006.173.17:06:49.86#ibcon#read 4, iclass 22, count 0 2006.173.17:06:49.86#ibcon#about to read 5, iclass 22, count 0 2006.173.17:06:49.86#ibcon#read 5, iclass 22, count 0 2006.173.17:06:49.86#ibcon#about to read 6, iclass 22, count 0 2006.173.17:06:49.86#ibcon#read 6, iclass 22, count 0 2006.173.17:06:49.86#ibcon#end of sib2, iclass 22, count 0 2006.173.17:06:49.86#ibcon#*after write, iclass 22, count 0 2006.173.17:06:49.86#ibcon#*before return 0, iclass 22, count 0 2006.173.17:06:49.86#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.17:06:49.86#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.17:06:49.86#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.17:06:49.86#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.17:06:49.86$vck44/va=6,3 2006.173.17:06:49.86#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.17:06:49.86#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.17:06:49.86#ibcon#ireg 11 cls_cnt 2 2006.173.17:06:49.86#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.17:06:49.92#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.17:06:49.92#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.17:06:49.92#ibcon#enter wrdev, iclass 24, count 2 2006.173.17:06:49.92#ibcon#first serial, iclass 24, count 2 2006.173.17:06:49.92#ibcon#enter sib2, iclass 24, count 2 2006.173.17:06:49.92#ibcon#flushed, iclass 24, count 2 2006.173.17:06:49.92#ibcon#about to write, iclass 24, count 2 2006.173.17:06:49.92#ibcon#wrote, iclass 24, count 2 2006.173.17:06:49.92#ibcon#about to read 3, iclass 24, count 2 2006.173.17:06:49.94#ibcon#read 3, iclass 24, count 2 2006.173.17:06:49.94#ibcon#about to read 4, iclass 24, count 2 2006.173.17:06:49.94#ibcon#read 4, iclass 24, count 2 2006.173.17:06:49.94#ibcon#about to read 5, iclass 24, count 2 2006.173.17:06:49.94#ibcon#read 5, iclass 24, count 2 2006.173.17:06:49.94#ibcon#about to read 6, iclass 24, count 2 2006.173.17:06:49.94#ibcon#read 6, iclass 24, count 2 2006.173.17:06:49.94#ibcon#end of sib2, iclass 24, count 2 2006.173.17:06:49.94#ibcon#*mode == 0, iclass 24, count 2 2006.173.17:06:49.94#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.17:06:49.94#ibcon#[25=AT06-03\r\n] 2006.173.17:06:49.94#ibcon#*before write, iclass 24, count 2 2006.173.17:06:49.94#ibcon#enter sib2, iclass 24, count 2 2006.173.17:06:49.94#ibcon#flushed, iclass 24, count 2 2006.173.17:06:49.94#ibcon#about to write, iclass 24, count 2 2006.173.17:06:49.94#ibcon#wrote, iclass 24, count 2 2006.173.17:06:49.94#ibcon#about to read 3, iclass 24, count 2 2006.173.17:06:49.97#ibcon#read 3, iclass 24, count 2 2006.173.17:06:49.97#ibcon#about to read 4, iclass 24, count 2 2006.173.17:06:49.97#ibcon#read 4, iclass 24, count 2 2006.173.17:06:49.97#ibcon#about to read 5, iclass 24, count 2 2006.173.17:06:49.97#ibcon#read 5, iclass 24, count 2 2006.173.17:06:49.97#ibcon#about to read 6, iclass 24, count 2 2006.173.17:06:49.97#ibcon#read 6, iclass 24, count 2 2006.173.17:06:49.97#ibcon#end of sib2, iclass 24, count 2 2006.173.17:06:49.97#ibcon#*after write, iclass 24, count 2 2006.173.17:06:49.97#ibcon#*before return 0, iclass 24, count 2 2006.173.17:06:49.97#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.17:06:49.97#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.17:06:49.97#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.17:06:49.97#ibcon#ireg 7 cls_cnt 0 2006.173.17:06:49.97#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.17:06:50.09#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.17:06:50.09#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.17:06:50.09#ibcon#enter wrdev, iclass 24, count 0 2006.173.17:06:50.09#ibcon#first serial, iclass 24, count 0 2006.173.17:06:50.09#ibcon#enter sib2, iclass 24, count 0 2006.173.17:06:50.09#ibcon#flushed, iclass 24, count 0 2006.173.17:06:50.09#ibcon#about to write, iclass 24, count 0 2006.173.17:06:50.09#ibcon#wrote, iclass 24, count 0 2006.173.17:06:50.09#ibcon#about to read 3, iclass 24, count 0 2006.173.17:06:50.11#ibcon#read 3, iclass 24, count 0 2006.173.17:06:50.11#ibcon#about to read 4, iclass 24, count 0 2006.173.17:06:50.11#ibcon#read 4, iclass 24, count 0 2006.173.17:06:50.11#ibcon#about to read 5, iclass 24, count 0 2006.173.17:06:50.11#ibcon#read 5, iclass 24, count 0 2006.173.17:06:50.11#ibcon#about to read 6, iclass 24, count 0 2006.173.17:06:50.11#ibcon#read 6, iclass 24, count 0 2006.173.17:06:50.11#ibcon#end of sib2, iclass 24, count 0 2006.173.17:06:50.11#ibcon#*mode == 0, iclass 24, count 0 2006.173.17:06:50.11#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.17:06:50.11#ibcon#[25=USB\r\n] 2006.173.17:06:50.11#ibcon#*before write, iclass 24, count 0 2006.173.17:06:50.11#ibcon#enter sib2, iclass 24, count 0 2006.173.17:06:50.11#ibcon#flushed, iclass 24, count 0 2006.173.17:06:50.11#ibcon#about to write, iclass 24, count 0 2006.173.17:06:50.11#ibcon#wrote, iclass 24, count 0 2006.173.17:06:50.11#ibcon#about to read 3, iclass 24, count 0 2006.173.17:06:50.14#ibcon#read 3, iclass 24, count 0 2006.173.17:06:50.14#ibcon#about to read 4, iclass 24, count 0 2006.173.17:06:50.14#ibcon#read 4, iclass 24, count 0 2006.173.17:06:50.14#ibcon#about to read 5, iclass 24, count 0 2006.173.17:06:50.14#ibcon#read 5, iclass 24, count 0 2006.173.17:06:50.14#ibcon#about to read 6, iclass 24, count 0 2006.173.17:06:50.14#ibcon#read 6, iclass 24, count 0 2006.173.17:06:50.14#ibcon#end of sib2, iclass 24, count 0 2006.173.17:06:50.14#ibcon#*after write, iclass 24, count 0 2006.173.17:06:50.14#ibcon#*before return 0, iclass 24, count 0 2006.173.17:06:50.14#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.17:06:50.14#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.17:06:50.14#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.17:06:50.14#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.17:06:50.14$vck44/valo=7,864.99 2006.173.17:06:50.14#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.17:06:50.14#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.17:06:50.14#ibcon#ireg 17 cls_cnt 0 2006.173.17:06:50.14#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.17:06:50.14#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.17:06:50.14#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.17:06:50.14#ibcon#enter wrdev, iclass 26, count 0 2006.173.17:06:50.14#ibcon#first serial, iclass 26, count 0 2006.173.17:06:50.14#ibcon#enter sib2, iclass 26, count 0 2006.173.17:06:50.14#ibcon#flushed, iclass 26, count 0 2006.173.17:06:50.14#ibcon#about to write, iclass 26, count 0 2006.173.17:06:50.14#ibcon#wrote, iclass 26, count 0 2006.173.17:06:50.14#ibcon#about to read 3, iclass 26, count 0 2006.173.17:06:50.16#ibcon#read 3, iclass 26, count 0 2006.173.17:06:50.16#ibcon#about to read 4, iclass 26, count 0 2006.173.17:06:50.16#ibcon#read 4, iclass 26, count 0 2006.173.17:06:50.16#ibcon#about to read 5, iclass 26, count 0 2006.173.17:06:50.16#ibcon#read 5, iclass 26, count 0 2006.173.17:06:50.16#ibcon#about to read 6, iclass 26, count 0 2006.173.17:06:50.16#ibcon#read 6, iclass 26, count 0 2006.173.17:06:50.16#ibcon#end of sib2, iclass 26, count 0 2006.173.17:06:50.16#ibcon#*mode == 0, iclass 26, count 0 2006.173.17:06:50.16#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.17:06:50.16#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.17:06:50.16#ibcon#*before write, iclass 26, count 0 2006.173.17:06:50.16#ibcon#enter sib2, iclass 26, count 0 2006.173.17:06:50.16#ibcon#flushed, iclass 26, count 0 2006.173.17:06:50.16#ibcon#about to write, iclass 26, count 0 2006.173.17:06:50.16#ibcon#wrote, iclass 26, count 0 2006.173.17:06:50.16#ibcon#about to read 3, iclass 26, count 0 2006.173.17:06:50.20#ibcon#read 3, iclass 26, count 0 2006.173.17:06:50.20#ibcon#about to read 4, iclass 26, count 0 2006.173.17:06:50.20#ibcon#read 4, iclass 26, count 0 2006.173.17:06:50.20#ibcon#about to read 5, iclass 26, count 0 2006.173.17:06:50.20#ibcon#read 5, iclass 26, count 0 2006.173.17:06:50.20#ibcon#about to read 6, iclass 26, count 0 2006.173.17:06:50.20#ibcon#read 6, iclass 26, count 0 2006.173.17:06:50.20#ibcon#end of sib2, iclass 26, count 0 2006.173.17:06:50.20#ibcon#*after write, iclass 26, count 0 2006.173.17:06:50.20#ibcon#*before return 0, iclass 26, count 0 2006.173.17:06:50.20#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.17:06:50.20#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.17:06:50.20#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.17:06:50.20#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.17:06:50.20$vck44/va=7,4 2006.173.17:06:50.20#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.17:06:50.20#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.17:06:50.20#ibcon#ireg 11 cls_cnt 2 2006.173.17:06:50.20#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.17:06:50.26#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.17:06:50.26#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.17:06:50.26#ibcon#enter wrdev, iclass 28, count 2 2006.173.17:06:50.26#ibcon#first serial, iclass 28, count 2 2006.173.17:06:50.26#ibcon#enter sib2, iclass 28, count 2 2006.173.17:06:50.26#ibcon#flushed, iclass 28, count 2 2006.173.17:06:50.26#ibcon#about to write, iclass 28, count 2 2006.173.17:06:50.26#ibcon#wrote, iclass 28, count 2 2006.173.17:06:50.26#ibcon#about to read 3, iclass 28, count 2 2006.173.17:06:50.28#ibcon#read 3, iclass 28, count 2 2006.173.17:06:50.28#ibcon#about to read 4, iclass 28, count 2 2006.173.17:06:50.28#ibcon#read 4, iclass 28, count 2 2006.173.17:06:50.28#ibcon#about to read 5, iclass 28, count 2 2006.173.17:06:50.28#ibcon#read 5, iclass 28, count 2 2006.173.17:06:50.28#ibcon#about to read 6, iclass 28, count 2 2006.173.17:06:50.28#ibcon#read 6, iclass 28, count 2 2006.173.17:06:50.28#ibcon#end of sib2, iclass 28, count 2 2006.173.17:06:50.28#ibcon#*mode == 0, iclass 28, count 2 2006.173.17:06:50.28#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.17:06:50.28#ibcon#[25=AT07-04\r\n] 2006.173.17:06:50.28#ibcon#*before write, iclass 28, count 2 2006.173.17:06:50.28#ibcon#enter sib2, iclass 28, count 2 2006.173.17:06:50.28#ibcon#flushed, iclass 28, count 2 2006.173.17:06:50.28#ibcon#about to write, iclass 28, count 2 2006.173.17:06:50.28#ibcon#wrote, iclass 28, count 2 2006.173.17:06:50.28#ibcon#about to read 3, iclass 28, count 2 2006.173.17:06:50.31#ibcon#read 3, iclass 28, count 2 2006.173.17:06:50.31#ibcon#about to read 4, iclass 28, count 2 2006.173.17:06:50.31#ibcon#read 4, iclass 28, count 2 2006.173.17:06:50.31#ibcon#about to read 5, iclass 28, count 2 2006.173.17:06:50.31#ibcon#read 5, iclass 28, count 2 2006.173.17:06:50.31#ibcon#about to read 6, iclass 28, count 2 2006.173.17:06:50.31#ibcon#read 6, iclass 28, count 2 2006.173.17:06:50.31#ibcon#end of sib2, iclass 28, count 2 2006.173.17:06:50.31#ibcon#*after write, iclass 28, count 2 2006.173.17:06:50.31#ibcon#*before return 0, iclass 28, count 2 2006.173.17:06:50.31#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.17:06:50.31#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.17:06:50.31#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.17:06:50.31#ibcon#ireg 7 cls_cnt 0 2006.173.17:06:50.31#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.17:06:50.43#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.17:06:50.43#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.17:06:50.43#ibcon#enter wrdev, iclass 28, count 0 2006.173.17:06:50.43#ibcon#first serial, iclass 28, count 0 2006.173.17:06:50.43#ibcon#enter sib2, iclass 28, count 0 2006.173.17:06:50.43#ibcon#flushed, iclass 28, count 0 2006.173.17:06:50.43#ibcon#about to write, iclass 28, count 0 2006.173.17:06:50.43#ibcon#wrote, iclass 28, count 0 2006.173.17:06:50.43#ibcon#about to read 3, iclass 28, count 0 2006.173.17:06:50.45#ibcon#read 3, iclass 28, count 0 2006.173.17:06:50.45#ibcon#about to read 4, iclass 28, count 0 2006.173.17:06:50.45#ibcon#read 4, iclass 28, count 0 2006.173.17:06:50.45#ibcon#about to read 5, iclass 28, count 0 2006.173.17:06:50.45#ibcon#read 5, iclass 28, count 0 2006.173.17:06:50.45#ibcon#about to read 6, iclass 28, count 0 2006.173.17:06:50.45#ibcon#read 6, iclass 28, count 0 2006.173.17:06:50.45#ibcon#end of sib2, iclass 28, count 0 2006.173.17:06:50.45#ibcon#*mode == 0, iclass 28, count 0 2006.173.17:06:50.45#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.17:06:50.45#ibcon#[25=USB\r\n] 2006.173.17:06:50.45#ibcon#*before write, iclass 28, count 0 2006.173.17:06:50.45#ibcon#enter sib2, iclass 28, count 0 2006.173.17:06:50.45#ibcon#flushed, iclass 28, count 0 2006.173.17:06:50.45#ibcon#about to write, iclass 28, count 0 2006.173.17:06:50.45#ibcon#wrote, iclass 28, count 0 2006.173.17:06:50.45#ibcon#about to read 3, iclass 28, count 0 2006.173.17:06:50.48#ibcon#read 3, iclass 28, count 0 2006.173.17:06:50.48#ibcon#about to read 4, iclass 28, count 0 2006.173.17:06:50.48#ibcon#read 4, iclass 28, count 0 2006.173.17:06:50.48#ibcon#about to read 5, iclass 28, count 0 2006.173.17:06:50.48#ibcon#read 5, iclass 28, count 0 2006.173.17:06:50.48#ibcon#about to read 6, iclass 28, count 0 2006.173.17:06:50.48#ibcon#read 6, iclass 28, count 0 2006.173.17:06:50.48#ibcon#end of sib2, iclass 28, count 0 2006.173.17:06:50.48#ibcon#*after write, iclass 28, count 0 2006.173.17:06:50.48#ibcon#*before return 0, iclass 28, count 0 2006.173.17:06:50.48#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.17:06:50.48#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.17:06:50.48#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.17:06:50.48#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.17:06:50.48$vck44/valo=8,884.99 2006.173.17:06:50.48#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.17:06:50.48#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.17:06:50.48#ibcon#ireg 17 cls_cnt 0 2006.173.17:06:50.48#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.17:06:50.48#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.17:06:50.48#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.17:06:50.48#ibcon#enter wrdev, iclass 30, count 0 2006.173.17:06:50.48#ibcon#first serial, iclass 30, count 0 2006.173.17:06:50.48#ibcon#enter sib2, iclass 30, count 0 2006.173.17:06:50.48#ibcon#flushed, iclass 30, count 0 2006.173.17:06:50.48#ibcon#about to write, iclass 30, count 0 2006.173.17:06:50.48#ibcon#wrote, iclass 30, count 0 2006.173.17:06:50.48#ibcon#about to read 3, iclass 30, count 0 2006.173.17:06:50.50#ibcon#read 3, iclass 30, count 0 2006.173.17:06:50.50#ibcon#about to read 4, iclass 30, count 0 2006.173.17:06:50.50#ibcon#read 4, iclass 30, count 0 2006.173.17:06:50.50#ibcon#about to read 5, iclass 30, count 0 2006.173.17:06:50.50#ibcon#read 5, iclass 30, count 0 2006.173.17:06:50.50#ibcon#about to read 6, iclass 30, count 0 2006.173.17:06:50.50#ibcon#read 6, iclass 30, count 0 2006.173.17:06:50.50#ibcon#end of sib2, iclass 30, count 0 2006.173.17:06:50.50#ibcon#*mode == 0, iclass 30, count 0 2006.173.17:06:50.50#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.17:06:50.50#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.17:06:50.50#ibcon#*before write, iclass 30, count 0 2006.173.17:06:50.50#ibcon#enter sib2, iclass 30, count 0 2006.173.17:06:50.50#ibcon#flushed, iclass 30, count 0 2006.173.17:06:50.50#ibcon#about to write, iclass 30, count 0 2006.173.17:06:50.50#ibcon#wrote, iclass 30, count 0 2006.173.17:06:50.50#ibcon#about to read 3, iclass 30, count 0 2006.173.17:06:50.54#ibcon#read 3, iclass 30, count 0 2006.173.17:06:50.54#ibcon#about to read 4, iclass 30, count 0 2006.173.17:06:50.54#ibcon#read 4, iclass 30, count 0 2006.173.17:06:50.54#ibcon#about to read 5, iclass 30, count 0 2006.173.17:06:50.54#ibcon#read 5, iclass 30, count 0 2006.173.17:06:50.54#ibcon#about to read 6, iclass 30, count 0 2006.173.17:06:50.54#ibcon#read 6, iclass 30, count 0 2006.173.17:06:50.54#ibcon#end of sib2, iclass 30, count 0 2006.173.17:06:50.54#ibcon#*after write, iclass 30, count 0 2006.173.17:06:50.54#ibcon#*before return 0, iclass 30, count 0 2006.173.17:06:50.54#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.17:06:50.54#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.17:06:50.54#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.17:06:50.54#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.17:06:50.54$vck44/va=8,4 2006.173.17:06:50.54#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.173.17:06:50.54#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.173.17:06:50.54#ibcon#ireg 11 cls_cnt 2 2006.173.17:06:50.54#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.17:06:50.60#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.17:06:50.60#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.17:06:50.60#ibcon#enter wrdev, iclass 32, count 2 2006.173.17:06:50.60#ibcon#first serial, iclass 32, count 2 2006.173.17:06:50.60#ibcon#enter sib2, iclass 32, count 2 2006.173.17:06:50.60#ibcon#flushed, iclass 32, count 2 2006.173.17:06:50.60#ibcon#about to write, iclass 32, count 2 2006.173.17:06:50.60#ibcon#wrote, iclass 32, count 2 2006.173.17:06:50.60#ibcon#about to read 3, iclass 32, count 2 2006.173.17:06:50.62#ibcon#read 3, iclass 32, count 2 2006.173.17:06:50.62#ibcon#about to read 4, iclass 32, count 2 2006.173.17:06:50.62#ibcon#read 4, iclass 32, count 2 2006.173.17:06:50.62#ibcon#about to read 5, iclass 32, count 2 2006.173.17:06:50.62#ibcon#read 5, iclass 32, count 2 2006.173.17:06:50.62#ibcon#about to read 6, iclass 32, count 2 2006.173.17:06:50.62#ibcon#read 6, iclass 32, count 2 2006.173.17:06:50.62#ibcon#end of sib2, iclass 32, count 2 2006.173.17:06:50.62#ibcon#*mode == 0, iclass 32, count 2 2006.173.17:06:50.62#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.173.17:06:50.62#ibcon#[25=AT08-04\r\n] 2006.173.17:06:50.62#ibcon#*before write, iclass 32, count 2 2006.173.17:06:50.62#ibcon#enter sib2, iclass 32, count 2 2006.173.17:06:50.62#ibcon#flushed, iclass 32, count 2 2006.173.17:06:50.62#ibcon#about to write, iclass 32, count 2 2006.173.17:06:50.62#ibcon#wrote, iclass 32, count 2 2006.173.17:06:50.62#ibcon#about to read 3, iclass 32, count 2 2006.173.17:06:50.65#ibcon#read 3, iclass 32, count 2 2006.173.17:06:50.65#ibcon#about to read 4, iclass 32, count 2 2006.173.17:06:50.65#ibcon#read 4, iclass 32, count 2 2006.173.17:06:50.65#ibcon#about to read 5, iclass 32, count 2 2006.173.17:06:50.65#ibcon#read 5, iclass 32, count 2 2006.173.17:06:50.65#ibcon#about to read 6, iclass 32, count 2 2006.173.17:06:50.65#ibcon#read 6, iclass 32, count 2 2006.173.17:06:50.65#ibcon#end of sib2, iclass 32, count 2 2006.173.17:06:50.65#ibcon#*after write, iclass 32, count 2 2006.173.17:06:50.65#ibcon#*before return 0, iclass 32, count 2 2006.173.17:06:50.65#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.17:06:50.65#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.173.17:06:50.65#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.173.17:06:50.65#ibcon#ireg 7 cls_cnt 0 2006.173.17:06:50.65#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.17:06:50.77#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.17:06:50.77#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.17:06:50.77#ibcon#enter wrdev, iclass 32, count 0 2006.173.17:06:50.77#ibcon#first serial, iclass 32, count 0 2006.173.17:06:50.77#ibcon#enter sib2, iclass 32, count 0 2006.173.17:06:50.77#ibcon#flushed, iclass 32, count 0 2006.173.17:06:50.77#ibcon#about to write, iclass 32, count 0 2006.173.17:06:50.77#ibcon#wrote, iclass 32, count 0 2006.173.17:06:50.77#ibcon#about to read 3, iclass 32, count 0 2006.173.17:06:50.79#ibcon#read 3, iclass 32, count 0 2006.173.17:06:50.79#ibcon#about to read 4, iclass 32, count 0 2006.173.17:06:50.79#ibcon#read 4, iclass 32, count 0 2006.173.17:06:50.79#ibcon#about to read 5, iclass 32, count 0 2006.173.17:06:50.79#ibcon#read 5, iclass 32, count 0 2006.173.17:06:50.79#ibcon#about to read 6, iclass 32, count 0 2006.173.17:06:50.79#ibcon#read 6, iclass 32, count 0 2006.173.17:06:50.79#ibcon#end of sib2, iclass 32, count 0 2006.173.17:06:50.79#ibcon#*mode == 0, iclass 32, count 0 2006.173.17:06:50.79#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.17:06:50.79#ibcon#[25=USB\r\n] 2006.173.17:06:50.79#ibcon#*before write, iclass 32, count 0 2006.173.17:06:50.79#ibcon#enter sib2, iclass 32, count 0 2006.173.17:06:50.79#ibcon#flushed, iclass 32, count 0 2006.173.17:06:50.79#ibcon#about to write, iclass 32, count 0 2006.173.17:06:50.79#ibcon#wrote, iclass 32, count 0 2006.173.17:06:50.79#ibcon#about to read 3, iclass 32, count 0 2006.173.17:06:50.82#ibcon#read 3, iclass 32, count 0 2006.173.17:06:50.82#ibcon#about to read 4, iclass 32, count 0 2006.173.17:06:50.82#ibcon#read 4, iclass 32, count 0 2006.173.17:06:50.82#ibcon#about to read 5, iclass 32, count 0 2006.173.17:06:50.82#ibcon#read 5, iclass 32, count 0 2006.173.17:06:50.82#ibcon#about to read 6, iclass 32, count 0 2006.173.17:06:50.82#ibcon#read 6, iclass 32, count 0 2006.173.17:06:50.82#ibcon#end of sib2, iclass 32, count 0 2006.173.17:06:50.82#ibcon#*after write, iclass 32, count 0 2006.173.17:06:50.82#ibcon#*before return 0, iclass 32, count 0 2006.173.17:06:50.82#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.17:06:50.82#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.173.17:06:50.82#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.17:06:50.82#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.17:06:50.82$vck44/vblo=1,629.99 2006.173.17:06:50.82#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.17:06:50.82#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.17:06:50.82#ibcon#ireg 17 cls_cnt 0 2006.173.17:06:50.82#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.17:06:50.82#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.17:06:50.82#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.17:06:50.82#ibcon#enter wrdev, iclass 34, count 0 2006.173.17:06:50.82#ibcon#first serial, iclass 34, count 0 2006.173.17:06:50.82#ibcon#enter sib2, iclass 34, count 0 2006.173.17:06:50.82#ibcon#flushed, iclass 34, count 0 2006.173.17:06:50.82#ibcon#about to write, iclass 34, count 0 2006.173.17:06:50.82#ibcon#wrote, iclass 34, count 0 2006.173.17:06:50.82#ibcon#about to read 3, iclass 34, count 0 2006.173.17:06:50.84#ibcon#read 3, iclass 34, count 0 2006.173.17:06:50.84#ibcon#about to read 4, iclass 34, count 0 2006.173.17:06:50.84#ibcon#read 4, iclass 34, count 0 2006.173.17:06:50.84#ibcon#about to read 5, iclass 34, count 0 2006.173.17:06:50.84#ibcon#read 5, iclass 34, count 0 2006.173.17:06:50.84#ibcon#about to read 6, iclass 34, count 0 2006.173.17:06:50.84#ibcon#read 6, iclass 34, count 0 2006.173.17:06:50.84#ibcon#end of sib2, iclass 34, count 0 2006.173.17:06:50.84#ibcon#*mode == 0, iclass 34, count 0 2006.173.17:06:50.84#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.17:06:50.84#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.17:06:50.84#ibcon#*before write, iclass 34, count 0 2006.173.17:06:50.84#ibcon#enter sib2, iclass 34, count 0 2006.173.17:06:50.84#ibcon#flushed, iclass 34, count 0 2006.173.17:06:50.84#ibcon#about to write, iclass 34, count 0 2006.173.17:06:50.84#ibcon#wrote, iclass 34, count 0 2006.173.17:06:50.84#ibcon#about to read 3, iclass 34, count 0 2006.173.17:06:50.88#ibcon#read 3, iclass 34, count 0 2006.173.17:06:50.88#ibcon#about to read 4, iclass 34, count 0 2006.173.17:06:50.88#ibcon#read 4, iclass 34, count 0 2006.173.17:06:50.88#ibcon#about to read 5, iclass 34, count 0 2006.173.17:06:50.88#ibcon#read 5, iclass 34, count 0 2006.173.17:06:50.88#ibcon#about to read 6, iclass 34, count 0 2006.173.17:06:50.88#ibcon#read 6, iclass 34, count 0 2006.173.17:06:50.88#ibcon#end of sib2, iclass 34, count 0 2006.173.17:06:50.88#ibcon#*after write, iclass 34, count 0 2006.173.17:06:50.88#ibcon#*before return 0, iclass 34, count 0 2006.173.17:06:50.88#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.17:06:50.88#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.17:06:50.88#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.17:06:50.88#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.17:06:50.88$vck44/vb=1,4 2006.173.17:06:50.88#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.17:06:50.88#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.17:06:50.88#ibcon#ireg 11 cls_cnt 2 2006.173.17:06:50.88#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.17:06:50.88#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.17:06:50.88#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.17:06:50.88#ibcon#enter wrdev, iclass 36, count 2 2006.173.17:06:50.88#ibcon#first serial, iclass 36, count 2 2006.173.17:06:50.88#ibcon#enter sib2, iclass 36, count 2 2006.173.17:06:50.88#ibcon#flushed, iclass 36, count 2 2006.173.17:06:50.88#ibcon#about to write, iclass 36, count 2 2006.173.17:06:50.88#ibcon#wrote, iclass 36, count 2 2006.173.17:06:50.88#ibcon#about to read 3, iclass 36, count 2 2006.173.17:06:50.90#ibcon#read 3, iclass 36, count 2 2006.173.17:06:50.90#ibcon#about to read 4, iclass 36, count 2 2006.173.17:06:50.90#ibcon#read 4, iclass 36, count 2 2006.173.17:06:50.90#ibcon#about to read 5, iclass 36, count 2 2006.173.17:06:50.90#ibcon#read 5, iclass 36, count 2 2006.173.17:06:50.90#ibcon#about to read 6, iclass 36, count 2 2006.173.17:06:50.90#ibcon#read 6, iclass 36, count 2 2006.173.17:06:50.90#ibcon#end of sib2, iclass 36, count 2 2006.173.17:06:50.90#ibcon#*mode == 0, iclass 36, count 2 2006.173.17:06:50.90#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.17:06:50.90#ibcon#[27=AT01-04\r\n] 2006.173.17:06:50.90#ibcon#*before write, iclass 36, count 2 2006.173.17:06:50.90#ibcon#enter sib2, iclass 36, count 2 2006.173.17:06:50.90#ibcon#flushed, iclass 36, count 2 2006.173.17:06:50.90#ibcon#about to write, iclass 36, count 2 2006.173.17:06:50.90#ibcon#wrote, iclass 36, count 2 2006.173.17:06:50.90#ibcon#about to read 3, iclass 36, count 2 2006.173.17:06:50.93#ibcon#read 3, iclass 36, count 2 2006.173.17:06:50.93#ibcon#about to read 4, iclass 36, count 2 2006.173.17:06:50.93#ibcon#read 4, iclass 36, count 2 2006.173.17:06:50.93#ibcon#about to read 5, iclass 36, count 2 2006.173.17:06:50.93#ibcon#read 5, iclass 36, count 2 2006.173.17:06:50.93#ibcon#about to read 6, iclass 36, count 2 2006.173.17:06:50.93#ibcon#read 6, iclass 36, count 2 2006.173.17:06:50.93#ibcon#end of sib2, iclass 36, count 2 2006.173.17:06:50.93#ibcon#*after write, iclass 36, count 2 2006.173.17:06:50.93#ibcon#*before return 0, iclass 36, count 2 2006.173.17:06:50.93#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.17:06:50.93#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.17:06:50.93#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.17:06:50.93#ibcon#ireg 7 cls_cnt 0 2006.173.17:06:50.93#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.17:06:51.05#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.17:06:51.05#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.17:06:51.05#ibcon#enter wrdev, iclass 36, count 0 2006.173.17:06:51.05#ibcon#first serial, iclass 36, count 0 2006.173.17:06:51.05#ibcon#enter sib2, iclass 36, count 0 2006.173.17:06:51.05#ibcon#flushed, iclass 36, count 0 2006.173.17:06:51.05#ibcon#about to write, iclass 36, count 0 2006.173.17:06:51.05#ibcon#wrote, iclass 36, count 0 2006.173.17:06:51.05#ibcon#about to read 3, iclass 36, count 0 2006.173.17:06:51.07#ibcon#read 3, iclass 36, count 0 2006.173.17:06:51.07#ibcon#about to read 4, iclass 36, count 0 2006.173.17:06:51.07#ibcon#read 4, iclass 36, count 0 2006.173.17:06:51.07#ibcon#about to read 5, iclass 36, count 0 2006.173.17:06:51.07#ibcon#read 5, iclass 36, count 0 2006.173.17:06:51.07#ibcon#about to read 6, iclass 36, count 0 2006.173.17:06:51.07#ibcon#read 6, iclass 36, count 0 2006.173.17:06:51.07#ibcon#end of sib2, iclass 36, count 0 2006.173.17:06:51.07#ibcon#*mode == 0, iclass 36, count 0 2006.173.17:06:51.07#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.17:06:51.07#ibcon#[27=USB\r\n] 2006.173.17:06:51.07#ibcon#*before write, iclass 36, count 0 2006.173.17:06:51.07#ibcon#enter sib2, iclass 36, count 0 2006.173.17:06:51.07#ibcon#flushed, iclass 36, count 0 2006.173.17:06:51.07#ibcon#about to write, iclass 36, count 0 2006.173.17:06:51.07#ibcon#wrote, iclass 36, count 0 2006.173.17:06:51.07#ibcon#about to read 3, iclass 36, count 0 2006.173.17:06:51.10#ibcon#read 3, iclass 36, count 0 2006.173.17:06:51.10#ibcon#about to read 4, iclass 36, count 0 2006.173.17:06:51.10#ibcon#read 4, iclass 36, count 0 2006.173.17:06:51.10#ibcon#about to read 5, iclass 36, count 0 2006.173.17:06:51.10#ibcon#read 5, iclass 36, count 0 2006.173.17:06:51.10#ibcon#about to read 6, iclass 36, count 0 2006.173.17:06:51.10#ibcon#read 6, iclass 36, count 0 2006.173.17:06:51.10#ibcon#end of sib2, iclass 36, count 0 2006.173.17:06:51.10#ibcon#*after write, iclass 36, count 0 2006.173.17:06:51.10#ibcon#*before return 0, iclass 36, count 0 2006.173.17:06:51.10#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.17:06:51.10#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.17:06:51.10#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.17:06:51.10#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.17:06:51.10$vck44/vblo=2,634.99 2006.173.17:06:51.10#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.17:06:51.10#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.17:06:51.10#ibcon#ireg 17 cls_cnt 0 2006.173.17:06:51.10#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.17:06:51.10#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.17:06:51.10#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.17:06:51.10#ibcon#enter wrdev, iclass 38, count 0 2006.173.17:06:51.10#ibcon#first serial, iclass 38, count 0 2006.173.17:06:51.10#ibcon#enter sib2, iclass 38, count 0 2006.173.17:06:51.10#ibcon#flushed, iclass 38, count 0 2006.173.17:06:51.10#ibcon#about to write, iclass 38, count 0 2006.173.17:06:51.10#ibcon#wrote, iclass 38, count 0 2006.173.17:06:51.10#ibcon#about to read 3, iclass 38, count 0 2006.173.17:06:51.12#ibcon#read 3, iclass 38, count 0 2006.173.17:06:51.12#ibcon#about to read 4, iclass 38, count 0 2006.173.17:06:51.12#ibcon#read 4, iclass 38, count 0 2006.173.17:06:51.12#ibcon#about to read 5, iclass 38, count 0 2006.173.17:06:51.12#ibcon#read 5, iclass 38, count 0 2006.173.17:06:51.12#ibcon#about to read 6, iclass 38, count 0 2006.173.17:06:51.12#ibcon#read 6, iclass 38, count 0 2006.173.17:06:51.12#ibcon#end of sib2, iclass 38, count 0 2006.173.17:06:51.12#ibcon#*mode == 0, iclass 38, count 0 2006.173.17:06:51.12#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.17:06:51.12#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.17:06:51.12#ibcon#*before write, iclass 38, count 0 2006.173.17:06:51.12#ibcon#enter sib2, iclass 38, count 0 2006.173.17:06:51.12#ibcon#flushed, iclass 38, count 0 2006.173.17:06:51.12#ibcon#about to write, iclass 38, count 0 2006.173.17:06:51.12#ibcon#wrote, iclass 38, count 0 2006.173.17:06:51.12#ibcon#about to read 3, iclass 38, count 0 2006.173.17:06:51.16#ibcon#read 3, iclass 38, count 0 2006.173.17:06:51.16#ibcon#about to read 4, iclass 38, count 0 2006.173.17:06:51.16#ibcon#read 4, iclass 38, count 0 2006.173.17:06:51.16#ibcon#about to read 5, iclass 38, count 0 2006.173.17:06:51.16#ibcon#read 5, iclass 38, count 0 2006.173.17:06:51.16#ibcon#about to read 6, iclass 38, count 0 2006.173.17:06:51.16#ibcon#read 6, iclass 38, count 0 2006.173.17:06:51.16#ibcon#end of sib2, iclass 38, count 0 2006.173.17:06:51.16#ibcon#*after write, iclass 38, count 0 2006.173.17:06:51.16#ibcon#*before return 0, iclass 38, count 0 2006.173.17:06:51.16#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.17:06:51.16#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.17:06:51.16#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.17:06:51.16#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.17:06:51.16$vck44/vb=2,4 2006.173.17:06:51.16#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.17:06:51.16#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.17:06:51.16#ibcon#ireg 11 cls_cnt 2 2006.173.17:06:51.16#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.17:06:51.22#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.17:06:51.22#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.17:06:51.22#ibcon#enter wrdev, iclass 40, count 2 2006.173.17:06:51.22#ibcon#first serial, iclass 40, count 2 2006.173.17:06:51.22#ibcon#enter sib2, iclass 40, count 2 2006.173.17:06:51.22#ibcon#flushed, iclass 40, count 2 2006.173.17:06:51.22#ibcon#about to write, iclass 40, count 2 2006.173.17:06:51.22#ibcon#wrote, iclass 40, count 2 2006.173.17:06:51.22#ibcon#about to read 3, iclass 40, count 2 2006.173.17:06:51.24#ibcon#read 3, iclass 40, count 2 2006.173.17:06:51.24#ibcon#about to read 4, iclass 40, count 2 2006.173.17:06:51.24#ibcon#read 4, iclass 40, count 2 2006.173.17:06:51.24#ibcon#about to read 5, iclass 40, count 2 2006.173.17:06:51.24#ibcon#read 5, iclass 40, count 2 2006.173.17:06:51.24#ibcon#about to read 6, iclass 40, count 2 2006.173.17:06:51.24#ibcon#read 6, iclass 40, count 2 2006.173.17:06:51.24#ibcon#end of sib2, iclass 40, count 2 2006.173.17:06:51.24#ibcon#*mode == 0, iclass 40, count 2 2006.173.17:06:51.24#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.17:06:51.24#ibcon#[27=AT02-04\r\n] 2006.173.17:06:51.24#ibcon#*before write, iclass 40, count 2 2006.173.17:06:51.24#ibcon#enter sib2, iclass 40, count 2 2006.173.17:06:51.24#ibcon#flushed, iclass 40, count 2 2006.173.17:06:51.24#ibcon#about to write, iclass 40, count 2 2006.173.17:06:51.24#ibcon#wrote, iclass 40, count 2 2006.173.17:06:51.24#ibcon#about to read 3, iclass 40, count 2 2006.173.17:06:51.27#ibcon#read 3, iclass 40, count 2 2006.173.17:06:51.27#ibcon#about to read 4, iclass 40, count 2 2006.173.17:06:51.27#ibcon#read 4, iclass 40, count 2 2006.173.17:06:51.27#ibcon#about to read 5, iclass 40, count 2 2006.173.17:06:51.27#ibcon#read 5, iclass 40, count 2 2006.173.17:06:51.27#ibcon#about to read 6, iclass 40, count 2 2006.173.17:06:51.27#ibcon#read 6, iclass 40, count 2 2006.173.17:06:51.27#ibcon#end of sib2, iclass 40, count 2 2006.173.17:06:51.27#ibcon#*after write, iclass 40, count 2 2006.173.17:06:51.27#ibcon#*before return 0, iclass 40, count 2 2006.173.17:06:51.27#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.17:06:51.27#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.17:06:51.27#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.17:06:51.27#ibcon#ireg 7 cls_cnt 0 2006.173.17:06:51.27#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.17:06:51.39#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.17:06:51.39#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.17:06:51.39#ibcon#enter wrdev, iclass 40, count 0 2006.173.17:06:51.39#ibcon#first serial, iclass 40, count 0 2006.173.17:06:51.39#ibcon#enter sib2, iclass 40, count 0 2006.173.17:06:51.39#ibcon#flushed, iclass 40, count 0 2006.173.17:06:51.39#ibcon#about to write, iclass 40, count 0 2006.173.17:06:51.39#ibcon#wrote, iclass 40, count 0 2006.173.17:06:51.39#ibcon#about to read 3, iclass 40, count 0 2006.173.17:06:51.41#ibcon#read 3, iclass 40, count 0 2006.173.17:06:51.41#ibcon#about to read 4, iclass 40, count 0 2006.173.17:06:51.41#ibcon#read 4, iclass 40, count 0 2006.173.17:06:51.41#ibcon#about to read 5, iclass 40, count 0 2006.173.17:06:51.41#ibcon#read 5, iclass 40, count 0 2006.173.17:06:51.41#ibcon#about to read 6, iclass 40, count 0 2006.173.17:06:51.41#ibcon#read 6, iclass 40, count 0 2006.173.17:06:51.41#ibcon#end of sib2, iclass 40, count 0 2006.173.17:06:51.41#ibcon#*mode == 0, iclass 40, count 0 2006.173.17:06:51.41#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.17:06:51.41#ibcon#[27=USB\r\n] 2006.173.17:06:51.41#ibcon#*before write, iclass 40, count 0 2006.173.17:06:51.41#ibcon#enter sib2, iclass 40, count 0 2006.173.17:06:51.41#ibcon#flushed, iclass 40, count 0 2006.173.17:06:51.41#ibcon#about to write, iclass 40, count 0 2006.173.17:06:51.41#ibcon#wrote, iclass 40, count 0 2006.173.17:06:51.41#ibcon#about to read 3, iclass 40, count 0 2006.173.17:06:51.44#ibcon#read 3, iclass 40, count 0 2006.173.17:06:51.44#ibcon#about to read 4, iclass 40, count 0 2006.173.17:06:51.44#ibcon#read 4, iclass 40, count 0 2006.173.17:06:51.44#ibcon#about to read 5, iclass 40, count 0 2006.173.17:06:51.44#ibcon#read 5, iclass 40, count 0 2006.173.17:06:51.44#ibcon#about to read 6, iclass 40, count 0 2006.173.17:06:51.44#ibcon#read 6, iclass 40, count 0 2006.173.17:06:51.44#ibcon#end of sib2, iclass 40, count 0 2006.173.17:06:51.44#ibcon#*after write, iclass 40, count 0 2006.173.17:06:51.44#ibcon#*before return 0, iclass 40, count 0 2006.173.17:06:51.44#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.17:06:51.44#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.17:06:51.44#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.17:06:51.44#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.17:06:51.44$vck44/vblo=3,649.99 2006.173.17:06:51.44#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.17:06:51.44#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.17:06:51.44#ibcon#ireg 17 cls_cnt 0 2006.173.17:06:51.44#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.17:06:51.44#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.17:06:51.44#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.17:06:51.44#ibcon#enter wrdev, iclass 4, count 0 2006.173.17:06:51.44#ibcon#first serial, iclass 4, count 0 2006.173.17:06:51.44#ibcon#enter sib2, iclass 4, count 0 2006.173.17:06:51.44#ibcon#flushed, iclass 4, count 0 2006.173.17:06:51.44#ibcon#about to write, iclass 4, count 0 2006.173.17:06:51.44#ibcon#wrote, iclass 4, count 0 2006.173.17:06:51.44#ibcon#about to read 3, iclass 4, count 0 2006.173.17:06:51.46#ibcon#read 3, iclass 4, count 0 2006.173.17:06:51.46#ibcon#about to read 4, iclass 4, count 0 2006.173.17:06:51.46#ibcon#read 4, iclass 4, count 0 2006.173.17:06:51.46#ibcon#about to read 5, iclass 4, count 0 2006.173.17:06:51.46#ibcon#read 5, iclass 4, count 0 2006.173.17:06:51.46#ibcon#about to read 6, iclass 4, count 0 2006.173.17:06:51.46#ibcon#read 6, iclass 4, count 0 2006.173.17:06:51.46#ibcon#end of sib2, iclass 4, count 0 2006.173.17:06:51.46#ibcon#*mode == 0, iclass 4, count 0 2006.173.17:06:51.46#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.17:06:51.46#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.17:06:51.46#ibcon#*before write, iclass 4, count 0 2006.173.17:06:51.46#ibcon#enter sib2, iclass 4, count 0 2006.173.17:06:51.46#ibcon#flushed, iclass 4, count 0 2006.173.17:06:51.46#ibcon#about to write, iclass 4, count 0 2006.173.17:06:51.46#ibcon#wrote, iclass 4, count 0 2006.173.17:06:51.46#ibcon#about to read 3, iclass 4, count 0 2006.173.17:06:51.50#ibcon#read 3, iclass 4, count 0 2006.173.17:06:51.50#ibcon#about to read 4, iclass 4, count 0 2006.173.17:06:51.50#ibcon#read 4, iclass 4, count 0 2006.173.17:06:51.50#ibcon#about to read 5, iclass 4, count 0 2006.173.17:06:51.50#ibcon#read 5, iclass 4, count 0 2006.173.17:06:51.50#ibcon#about to read 6, iclass 4, count 0 2006.173.17:06:51.50#ibcon#read 6, iclass 4, count 0 2006.173.17:06:51.50#ibcon#end of sib2, iclass 4, count 0 2006.173.17:06:51.50#ibcon#*after write, iclass 4, count 0 2006.173.17:06:51.50#ibcon#*before return 0, iclass 4, count 0 2006.173.17:06:51.50#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.17:06:51.50#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.17:06:51.50#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.17:06:51.50#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.17:06:51.50$vck44/vb=3,4 2006.173.17:06:51.50#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.17:06:51.50#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.17:06:51.50#ibcon#ireg 11 cls_cnt 2 2006.173.17:06:51.50#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.17:06:51.56#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.17:06:51.56#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.17:06:51.56#ibcon#enter wrdev, iclass 6, count 2 2006.173.17:06:51.56#ibcon#first serial, iclass 6, count 2 2006.173.17:06:51.56#ibcon#enter sib2, iclass 6, count 2 2006.173.17:06:51.56#ibcon#flushed, iclass 6, count 2 2006.173.17:06:51.56#ibcon#about to write, iclass 6, count 2 2006.173.17:06:51.56#ibcon#wrote, iclass 6, count 2 2006.173.17:06:51.56#ibcon#about to read 3, iclass 6, count 2 2006.173.17:06:51.58#ibcon#read 3, iclass 6, count 2 2006.173.17:06:51.58#ibcon#about to read 4, iclass 6, count 2 2006.173.17:06:51.58#ibcon#read 4, iclass 6, count 2 2006.173.17:06:51.58#ibcon#about to read 5, iclass 6, count 2 2006.173.17:06:51.58#ibcon#read 5, iclass 6, count 2 2006.173.17:06:51.58#ibcon#about to read 6, iclass 6, count 2 2006.173.17:06:51.58#ibcon#read 6, iclass 6, count 2 2006.173.17:06:51.58#ibcon#end of sib2, iclass 6, count 2 2006.173.17:06:51.58#ibcon#*mode == 0, iclass 6, count 2 2006.173.17:06:51.58#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.17:06:51.58#ibcon#[27=AT03-04\r\n] 2006.173.17:06:51.58#ibcon#*before write, iclass 6, count 2 2006.173.17:06:51.58#ibcon#enter sib2, iclass 6, count 2 2006.173.17:06:51.58#ibcon#flushed, iclass 6, count 2 2006.173.17:06:51.58#ibcon#about to write, iclass 6, count 2 2006.173.17:06:51.58#ibcon#wrote, iclass 6, count 2 2006.173.17:06:51.58#ibcon#about to read 3, iclass 6, count 2 2006.173.17:06:51.61#ibcon#read 3, iclass 6, count 2 2006.173.17:06:51.61#ibcon#about to read 4, iclass 6, count 2 2006.173.17:06:51.61#ibcon#read 4, iclass 6, count 2 2006.173.17:06:51.61#ibcon#about to read 5, iclass 6, count 2 2006.173.17:06:51.61#ibcon#read 5, iclass 6, count 2 2006.173.17:06:51.61#ibcon#about to read 6, iclass 6, count 2 2006.173.17:06:51.61#ibcon#read 6, iclass 6, count 2 2006.173.17:06:51.61#ibcon#end of sib2, iclass 6, count 2 2006.173.17:06:51.61#ibcon#*after write, iclass 6, count 2 2006.173.17:06:51.61#ibcon#*before return 0, iclass 6, count 2 2006.173.17:06:51.61#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.17:06:51.61#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.17:06:51.61#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.17:06:51.61#ibcon#ireg 7 cls_cnt 0 2006.173.17:06:51.61#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.17:06:51.73#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.17:06:51.73#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.17:06:51.73#ibcon#enter wrdev, iclass 6, count 0 2006.173.17:06:51.73#ibcon#first serial, iclass 6, count 0 2006.173.17:06:51.73#ibcon#enter sib2, iclass 6, count 0 2006.173.17:06:51.73#ibcon#flushed, iclass 6, count 0 2006.173.17:06:51.73#ibcon#about to write, iclass 6, count 0 2006.173.17:06:51.73#ibcon#wrote, iclass 6, count 0 2006.173.17:06:51.73#ibcon#about to read 3, iclass 6, count 0 2006.173.17:06:51.75#ibcon#read 3, iclass 6, count 0 2006.173.17:06:51.75#ibcon#about to read 4, iclass 6, count 0 2006.173.17:06:51.75#ibcon#read 4, iclass 6, count 0 2006.173.17:06:51.75#ibcon#about to read 5, iclass 6, count 0 2006.173.17:06:51.75#ibcon#read 5, iclass 6, count 0 2006.173.17:06:51.75#ibcon#about to read 6, iclass 6, count 0 2006.173.17:06:51.75#ibcon#read 6, iclass 6, count 0 2006.173.17:06:51.75#ibcon#end of sib2, iclass 6, count 0 2006.173.17:06:51.75#ibcon#*mode == 0, iclass 6, count 0 2006.173.17:06:51.75#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.17:06:51.75#ibcon#[27=USB\r\n] 2006.173.17:06:51.75#ibcon#*before write, iclass 6, count 0 2006.173.17:06:51.75#ibcon#enter sib2, iclass 6, count 0 2006.173.17:06:51.75#ibcon#flushed, iclass 6, count 0 2006.173.17:06:51.75#ibcon#about to write, iclass 6, count 0 2006.173.17:06:51.75#ibcon#wrote, iclass 6, count 0 2006.173.17:06:51.75#ibcon#about to read 3, iclass 6, count 0 2006.173.17:06:51.78#ibcon#read 3, iclass 6, count 0 2006.173.17:06:51.78#ibcon#about to read 4, iclass 6, count 0 2006.173.17:06:51.78#ibcon#read 4, iclass 6, count 0 2006.173.17:06:51.78#ibcon#about to read 5, iclass 6, count 0 2006.173.17:06:51.78#ibcon#read 5, iclass 6, count 0 2006.173.17:06:51.78#ibcon#about to read 6, iclass 6, count 0 2006.173.17:06:51.78#ibcon#read 6, iclass 6, count 0 2006.173.17:06:51.78#ibcon#end of sib2, iclass 6, count 0 2006.173.17:06:51.78#ibcon#*after write, iclass 6, count 0 2006.173.17:06:51.78#ibcon#*before return 0, iclass 6, count 0 2006.173.17:06:51.78#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.17:06:51.78#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.17:06:51.78#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.17:06:51.78#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.17:06:51.78$vck44/vblo=4,679.99 2006.173.17:06:51.78#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.17:06:51.78#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.17:06:51.78#ibcon#ireg 17 cls_cnt 0 2006.173.17:06:51.78#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.17:06:51.78#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.17:06:51.78#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.17:06:51.78#ibcon#enter wrdev, iclass 10, count 0 2006.173.17:06:51.78#ibcon#first serial, iclass 10, count 0 2006.173.17:06:51.78#ibcon#enter sib2, iclass 10, count 0 2006.173.17:06:51.78#ibcon#flushed, iclass 10, count 0 2006.173.17:06:51.78#ibcon#about to write, iclass 10, count 0 2006.173.17:06:51.78#ibcon#wrote, iclass 10, count 0 2006.173.17:06:51.78#ibcon#about to read 3, iclass 10, count 0 2006.173.17:06:51.80#ibcon#read 3, iclass 10, count 0 2006.173.17:06:51.80#ibcon#about to read 4, iclass 10, count 0 2006.173.17:06:51.80#ibcon#read 4, iclass 10, count 0 2006.173.17:06:51.80#ibcon#about to read 5, iclass 10, count 0 2006.173.17:06:51.80#ibcon#read 5, iclass 10, count 0 2006.173.17:06:51.80#ibcon#about to read 6, iclass 10, count 0 2006.173.17:06:51.80#ibcon#read 6, iclass 10, count 0 2006.173.17:06:51.80#ibcon#end of sib2, iclass 10, count 0 2006.173.17:06:51.80#ibcon#*mode == 0, iclass 10, count 0 2006.173.17:06:51.80#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.17:06:51.80#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.17:06:51.80#ibcon#*before write, iclass 10, count 0 2006.173.17:06:51.80#ibcon#enter sib2, iclass 10, count 0 2006.173.17:06:51.80#ibcon#flushed, iclass 10, count 0 2006.173.17:06:51.80#ibcon#about to write, iclass 10, count 0 2006.173.17:06:51.80#ibcon#wrote, iclass 10, count 0 2006.173.17:06:51.80#ibcon#about to read 3, iclass 10, count 0 2006.173.17:06:51.84#ibcon#read 3, iclass 10, count 0 2006.173.17:06:51.84#ibcon#about to read 4, iclass 10, count 0 2006.173.17:06:51.84#ibcon#read 4, iclass 10, count 0 2006.173.17:06:51.84#ibcon#about to read 5, iclass 10, count 0 2006.173.17:06:51.84#ibcon#read 5, iclass 10, count 0 2006.173.17:06:51.84#ibcon#about to read 6, iclass 10, count 0 2006.173.17:06:51.84#ibcon#read 6, iclass 10, count 0 2006.173.17:06:51.84#ibcon#end of sib2, iclass 10, count 0 2006.173.17:06:51.84#ibcon#*after write, iclass 10, count 0 2006.173.17:06:51.84#ibcon#*before return 0, iclass 10, count 0 2006.173.17:06:51.84#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.17:06:51.84#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.17:06:51.84#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.17:06:51.84#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.17:06:51.84$vck44/vb=4,4 2006.173.17:06:51.84#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.17:06:51.84#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.17:06:51.84#ibcon#ireg 11 cls_cnt 2 2006.173.17:06:51.84#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.17:06:51.90#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.17:06:51.90#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.17:06:51.90#ibcon#enter wrdev, iclass 12, count 2 2006.173.17:06:51.90#ibcon#first serial, iclass 12, count 2 2006.173.17:06:51.90#ibcon#enter sib2, iclass 12, count 2 2006.173.17:06:51.90#ibcon#flushed, iclass 12, count 2 2006.173.17:06:51.90#ibcon#about to write, iclass 12, count 2 2006.173.17:06:51.90#ibcon#wrote, iclass 12, count 2 2006.173.17:06:51.90#ibcon#about to read 3, iclass 12, count 2 2006.173.17:06:51.92#ibcon#read 3, iclass 12, count 2 2006.173.17:06:51.92#ibcon#about to read 4, iclass 12, count 2 2006.173.17:06:51.92#ibcon#read 4, iclass 12, count 2 2006.173.17:06:51.92#ibcon#about to read 5, iclass 12, count 2 2006.173.17:06:51.92#ibcon#read 5, iclass 12, count 2 2006.173.17:06:51.92#ibcon#about to read 6, iclass 12, count 2 2006.173.17:06:51.92#ibcon#read 6, iclass 12, count 2 2006.173.17:06:51.92#ibcon#end of sib2, iclass 12, count 2 2006.173.17:06:51.92#ibcon#*mode == 0, iclass 12, count 2 2006.173.17:06:51.92#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.17:06:51.92#ibcon#[27=AT04-04\r\n] 2006.173.17:06:51.92#ibcon#*before write, iclass 12, count 2 2006.173.17:06:51.92#ibcon#enter sib2, iclass 12, count 2 2006.173.17:06:51.92#ibcon#flushed, iclass 12, count 2 2006.173.17:06:51.92#ibcon#about to write, iclass 12, count 2 2006.173.17:06:51.92#ibcon#wrote, iclass 12, count 2 2006.173.17:06:51.92#ibcon#about to read 3, iclass 12, count 2 2006.173.17:06:51.95#ibcon#read 3, iclass 12, count 2 2006.173.17:06:51.95#ibcon#about to read 4, iclass 12, count 2 2006.173.17:06:51.95#ibcon#read 4, iclass 12, count 2 2006.173.17:06:51.95#ibcon#about to read 5, iclass 12, count 2 2006.173.17:06:51.95#ibcon#read 5, iclass 12, count 2 2006.173.17:06:51.95#ibcon#about to read 6, iclass 12, count 2 2006.173.17:06:51.95#ibcon#read 6, iclass 12, count 2 2006.173.17:06:51.95#ibcon#end of sib2, iclass 12, count 2 2006.173.17:06:51.95#ibcon#*after write, iclass 12, count 2 2006.173.17:06:51.95#ibcon#*before return 0, iclass 12, count 2 2006.173.17:06:51.95#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.17:06:51.95#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.17:06:51.95#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.17:06:51.95#ibcon#ireg 7 cls_cnt 0 2006.173.17:06:51.95#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.17:06:52.07#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.17:06:52.07#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.17:06:52.07#ibcon#enter wrdev, iclass 12, count 0 2006.173.17:06:52.07#ibcon#first serial, iclass 12, count 0 2006.173.17:06:52.07#ibcon#enter sib2, iclass 12, count 0 2006.173.17:06:52.07#ibcon#flushed, iclass 12, count 0 2006.173.17:06:52.07#ibcon#about to write, iclass 12, count 0 2006.173.17:06:52.07#ibcon#wrote, iclass 12, count 0 2006.173.17:06:52.07#ibcon#about to read 3, iclass 12, count 0 2006.173.17:06:52.09#ibcon#read 3, iclass 12, count 0 2006.173.17:06:52.09#ibcon#about to read 4, iclass 12, count 0 2006.173.17:06:52.09#ibcon#read 4, iclass 12, count 0 2006.173.17:06:52.09#ibcon#about to read 5, iclass 12, count 0 2006.173.17:06:52.09#ibcon#read 5, iclass 12, count 0 2006.173.17:06:52.09#ibcon#about to read 6, iclass 12, count 0 2006.173.17:06:52.09#ibcon#read 6, iclass 12, count 0 2006.173.17:06:52.09#ibcon#end of sib2, iclass 12, count 0 2006.173.17:06:52.09#ibcon#*mode == 0, iclass 12, count 0 2006.173.17:06:52.09#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.17:06:52.09#ibcon#[27=USB\r\n] 2006.173.17:06:52.09#ibcon#*before write, iclass 12, count 0 2006.173.17:06:52.09#ibcon#enter sib2, iclass 12, count 0 2006.173.17:06:52.09#ibcon#flushed, iclass 12, count 0 2006.173.17:06:52.09#ibcon#about to write, iclass 12, count 0 2006.173.17:06:52.09#ibcon#wrote, iclass 12, count 0 2006.173.17:06:52.09#ibcon#about to read 3, iclass 12, count 0 2006.173.17:06:52.12#ibcon#read 3, iclass 12, count 0 2006.173.17:06:52.12#ibcon#about to read 4, iclass 12, count 0 2006.173.17:06:52.12#ibcon#read 4, iclass 12, count 0 2006.173.17:06:52.12#ibcon#about to read 5, iclass 12, count 0 2006.173.17:06:52.12#ibcon#read 5, iclass 12, count 0 2006.173.17:06:52.12#ibcon#about to read 6, iclass 12, count 0 2006.173.17:06:52.12#ibcon#read 6, iclass 12, count 0 2006.173.17:06:52.12#ibcon#end of sib2, iclass 12, count 0 2006.173.17:06:52.12#ibcon#*after write, iclass 12, count 0 2006.173.17:06:52.12#ibcon#*before return 0, iclass 12, count 0 2006.173.17:06:52.12#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.17:06:52.12#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.17:06:52.12#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.17:06:52.12#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.17:06:52.12$vck44/vblo=5,709.99 2006.173.17:06:52.12#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.17:06:52.12#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.17:06:52.12#ibcon#ireg 17 cls_cnt 0 2006.173.17:06:52.12#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.17:06:52.12#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.17:06:52.12#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.17:06:52.12#ibcon#enter wrdev, iclass 14, count 0 2006.173.17:06:52.12#ibcon#first serial, iclass 14, count 0 2006.173.17:06:52.12#ibcon#enter sib2, iclass 14, count 0 2006.173.17:06:52.12#ibcon#flushed, iclass 14, count 0 2006.173.17:06:52.12#ibcon#about to write, iclass 14, count 0 2006.173.17:06:52.12#ibcon#wrote, iclass 14, count 0 2006.173.17:06:52.12#ibcon#about to read 3, iclass 14, count 0 2006.173.17:06:52.14#ibcon#read 3, iclass 14, count 0 2006.173.17:06:52.14#ibcon#about to read 4, iclass 14, count 0 2006.173.17:06:52.14#ibcon#read 4, iclass 14, count 0 2006.173.17:06:52.14#ibcon#about to read 5, iclass 14, count 0 2006.173.17:06:52.14#ibcon#read 5, iclass 14, count 0 2006.173.17:06:52.14#ibcon#about to read 6, iclass 14, count 0 2006.173.17:06:52.14#ibcon#read 6, iclass 14, count 0 2006.173.17:06:52.14#ibcon#end of sib2, iclass 14, count 0 2006.173.17:06:52.14#ibcon#*mode == 0, iclass 14, count 0 2006.173.17:06:52.14#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.17:06:52.14#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.17:06:52.14#ibcon#*before write, iclass 14, count 0 2006.173.17:06:52.14#ibcon#enter sib2, iclass 14, count 0 2006.173.17:06:52.14#ibcon#flushed, iclass 14, count 0 2006.173.17:06:52.14#ibcon#about to write, iclass 14, count 0 2006.173.17:06:52.14#ibcon#wrote, iclass 14, count 0 2006.173.17:06:52.14#ibcon#about to read 3, iclass 14, count 0 2006.173.17:06:52.18#ibcon#read 3, iclass 14, count 0 2006.173.17:06:52.18#ibcon#about to read 4, iclass 14, count 0 2006.173.17:06:52.18#ibcon#read 4, iclass 14, count 0 2006.173.17:06:52.18#ibcon#about to read 5, iclass 14, count 0 2006.173.17:06:52.18#ibcon#read 5, iclass 14, count 0 2006.173.17:06:52.18#ibcon#about to read 6, iclass 14, count 0 2006.173.17:06:52.18#ibcon#read 6, iclass 14, count 0 2006.173.17:06:52.18#ibcon#end of sib2, iclass 14, count 0 2006.173.17:06:52.18#ibcon#*after write, iclass 14, count 0 2006.173.17:06:52.18#ibcon#*before return 0, iclass 14, count 0 2006.173.17:06:52.18#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.17:06:52.18#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.17:06:52.18#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.17:06:52.18#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.17:06:52.18$vck44/vb=5,4 2006.173.17:06:52.18#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.17:06:52.18#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.17:06:52.18#ibcon#ireg 11 cls_cnt 2 2006.173.17:06:52.18#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.17:06:52.24#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.17:06:52.24#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.17:06:52.24#ibcon#enter wrdev, iclass 16, count 2 2006.173.17:06:52.24#ibcon#first serial, iclass 16, count 2 2006.173.17:06:52.24#ibcon#enter sib2, iclass 16, count 2 2006.173.17:06:52.24#ibcon#flushed, iclass 16, count 2 2006.173.17:06:52.24#ibcon#about to write, iclass 16, count 2 2006.173.17:06:52.24#ibcon#wrote, iclass 16, count 2 2006.173.17:06:52.24#ibcon#about to read 3, iclass 16, count 2 2006.173.17:06:52.26#ibcon#read 3, iclass 16, count 2 2006.173.17:06:52.26#ibcon#about to read 4, iclass 16, count 2 2006.173.17:06:52.26#ibcon#read 4, iclass 16, count 2 2006.173.17:06:52.26#ibcon#about to read 5, iclass 16, count 2 2006.173.17:06:52.26#ibcon#read 5, iclass 16, count 2 2006.173.17:06:52.26#ibcon#about to read 6, iclass 16, count 2 2006.173.17:06:52.26#ibcon#read 6, iclass 16, count 2 2006.173.17:06:52.26#ibcon#end of sib2, iclass 16, count 2 2006.173.17:06:52.26#ibcon#*mode == 0, iclass 16, count 2 2006.173.17:06:52.26#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.17:06:52.26#ibcon#[27=AT05-04\r\n] 2006.173.17:06:52.26#ibcon#*before write, iclass 16, count 2 2006.173.17:06:52.26#ibcon#enter sib2, iclass 16, count 2 2006.173.17:06:52.26#ibcon#flushed, iclass 16, count 2 2006.173.17:06:52.26#ibcon#about to write, iclass 16, count 2 2006.173.17:06:52.26#ibcon#wrote, iclass 16, count 2 2006.173.17:06:52.26#ibcon#about to read 3, iclass 16, count 2 2006.173.17:06:52.29#ibcon#read 3, iclass 16, count 2 2006.173.17:06:52.29#ibcon#about to read 4, iclass 16, count 2 2006.173.17:06:52.29#ibcon#read 4, iclass 16, count 2 2006.173.17:06:52.29#ibcon#about to read 5, iclass 16, count 2 2006.173.17:06:52.29#ibcon#read 5, iclass 16, count 2 2006.173.17:06:52.29#ibcon#about to read 6, iclass 16, count 2 2006.173.17:06:52.29#ibcon#read 6, iclass 16, count 2 2006.173.17:06:52.29#ibcon#end of sib2, iclass 16, count 2 2006.173.17:06:52.29#ibcon#*after write, iclass 16, count 2 2006.173.17:06:52.29#ibcon#*before return 0, iclass 16, count 2 2006.173.17:06:52.29#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.17:06:52.29#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.17:06:52.29#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.17:06:52.29#ibcon#ireg 7 cls_cnt 0 2006.173.17:06:52.29#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.17:06:52.41#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.17:06:52.41#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.17:06:52.41#ibcon#enter wrdev, iclass 16, count 0 2006.173.17:06:52.41#ibcon#first serial, iclass 16, count 0 2006.173.17:06:52.41#ibcon#enter sib2, iclass 16, count 0 2006.173.17:06:52.41#ibcon#flushed, iclass 16, count 0 2006.173.17:06:52.41#ibcon#about to write, iclass 16, count 0 2006.173.17:06:52.41#ibcon#wrote, iclass 16, count 0 2006.173.17:06:52.41#ibcon#about to read 3, iclass 16, count 0 2006.173.17:06:52.43#ibcon#read 3, iclass 16, count 0 2006.173.17:06:52.43#ibcon#about to read 4, iclass 16, count 0 2006.173.17:06:52.43#ibcon#read 4, iclass 16, count 0 2006.173.17:06:52.43#ibcon#about to read 5, iclass 16, count 0 2006.173.17:06:52.43#ibcon#read 5, iclass 16, count 0 2006.173.17:06:52.43#ibcon#about to read 6, iclass 16, count 0 2006.173.17:06:52.43#ibcon#read 6, iclass 16, count 0 2006.173.17:06:52.43#ibcon#end of sib2, iclass 16, count 0 2006.173.17:06:52.43#ibcon#*mode == 0, iclass 16, count 0 2006.173.17:06:52.43#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.17:06:52.43#ibcon#[27=USB\r\n] 2006.173.17:06:52.43#ibcon#*before write, iclass 16, count 0 2006.173.17:06:52.43#ibcon#enter sib2, iclass 16, count 0 2006.173.17:06:52.43#ibcon#flushed, iclass 16, count 0 2006.173.17:06:52.43#ibcon#about to write, iclass 16, count 0 2006.173.17:06:52.43#ibcon#wrote, iclass 16, count 0 2006.173.17:06:52.43#ibcon#about to read 3, iclass 16, count 0 2006.173.17:06:52.46#ibcon#read 3, iclass 16, count 0 2006.173.17:06:52.46#ibcon#about to read 4, iclass 16, count 0 2006.173.17:06:52.46#ibcon#read 4, iclass 16, count 0 2006.173.17:06:52.46#ibcon#about to read 5, iclass 16, count 0 2006.173.17:06:52.46#ibcon#read 5, iclass 16, count 0 2006.173.17:06:52.46#ibcon#about to read 6, iclass 16, count 0 2006.173.17:06:52.46#ibcon#read 6, iclass 16, count 0 2006.173.17:06:52.46#ibcon#end of sib2, iclass 16, count 0 2006.173.17:06:52.46#ibcon#*after write, iclass 16, count 0 2006.173.17:06:52.46#ibcon#*before return 0, iclass 16, count 0 2006.173.17:06:52.46#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.17:06:52.46#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.17:06:52.46#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.17:06:52.46#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.17:06:52.46$vck44/vblo=6,719.99 2006.173.17:06:52.46#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.17:06:52.46#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.17:06:52.46#ibcon#ireg 17 cls_cnt 0 2006.173.17:06:52.46#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.17:06:52.46#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.17:06:52.46#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.17:06:52.46#ibcon#enter wrdev, iclass 18, count 0 2006.173.17:06:52.46#ibcon#first serial, iclass 18, count 0 2006.173.17:06:52.46#ibcon#enter sib2, iclass 18, count 0 2006.173.17:06:52.46#ibcon#flushed, iclass 18, count 0 2006.173.17:06:52.46#ibcon#about to write, iclass 18, count 0 2006.173.17:06:52.46#ibcon#wrote, iclass 18, count 0 2006.173.17:06:52.46#ibcon#about to read 3, iclass 18, count 0 2006.173.17:06:52.48#ibcon#read 3, iclass 18, count 0 2006.173.17:06:52.48#ibcon#about to read 4, iclass 18, count 0 2006.173.17:06:52.48#ibcon#read 4, iclass 18, count 0 2006.173.17:06:52.48#ibcon#about to read 5, iclass 18, count 0 2006.173.17:06:52.48#ibcon#read 5, iclass 18, count 0 2006.173.17:06:52.48#ibcon#about to read 6, iclass 18, count 0 2006.173.17:06:52.48#ibcon#read 6, iclass 18, count 0 2006.173.17:06:52.48#ibcon#end of sib2, iclass 18, count 0 2006.173.17:06:52.48#ibcon#*mode == 0, iclass 18, count 0 2006.173.17:06:52.48#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.17:06:52.48#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.17:06:52.48#ibcon#*before write, iclass 18, count 0 2006.173.17:06:52.48#ibcon#enter sib2, iclass 18, count 0 2006.173.17:06:52.48#ibcon#flushed, iclass 18, count 0 2006.173.17:06:52.48#ibcon#about to write, iclass 18, count 0 2006.173.17:06:52.48#ibcon#wrote, iclass 18, count 0 2006.173.17:06:52.48#ibcon#about to read 3, iclass 18, count 0 2006.173.17:06:52.52#ibcon#read 3, iclass 18, count 0 2006.173.17:06:52.52#ibcon#about to read 4, iclass 18, count 0 2006.173.17:06:52.52#ibcon#read 4, iclass 18, count 0 2006.173.17:06:52.52#ibcon#about to read 5, iclass 18, count 0 2006.173.17:06:52.52#ibcon#read 5, iclass 18, count 0 2006.173.17:06:52.52#ibcon#about to read 6, iclass 18, count 0 2006.173.17:06:52.52#ibcon#read 6, iclass 18, count 0 2006.173.17:06:52.52#ibcon#end of sib2, iclass 18, count 0 2006.173.17:06:52.52#ibcon#*after write, iclass 18, count 0 2006.173.17:06:52.52#ibcon#*before return 0, iclass 18, count 0 2006.173.17:06:52.52#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.17:06:52.52#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.17:06:52.52#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.17:06:52.52#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.17:06:52.52$vck44/vb=6,4 2006.173.17:06:52.52#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.17:06:52.52#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.17:06:52.52#ibcon#ireg 11 cls_cnt 2 2006.173.17:06:52.52#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.17:06:52.58#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.17:06:52.58#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.17:06:52.58#ibcon#enter wrdev, iclass 20, count 2 2006.173.17:06:52.58#ibcon#first serial, iclass 20, count 2 2006.173.17:06:52.58#ibcon#enter sib2, iclass 20, count 2 2006.173.17:06:52.58#ibcon#flushed, iclass 20, count 2 2006.173.17:06:52.58#ibcon#about to write, iclass 20, count 2 2006.173.17:06:52.58#ibcon#wrote, iclass 20, count 2 2006.173.17:06:52.58#ibcon#about to read 3, iclass 20, count 2 2006.173.17:06:52.60#ibcon#read 3, iclass 20, count 2 2006.173.17:06:52.60#ibcon#about to read 4, iclass 20, count 2 2006.173.17:06:52.60#ibcon#read 4, iclass 20, count 2 2006.173.17:06:52.60#ibcon#about to read 5, iclass 20, count 2 2006.173.17:06:52.60#ibcon#read 5, iclass 20, count 2 2006.173.17:06:52.60#ibcon#about to read 6, iclass 20, count 2 2006.173.17:06:52.60#ibcon#read 6, iclass 20, count 2 2006.173.17:06:52.60#ibcon#end of sib2, iclass 20, count 2 2006.173.17:06:52.60#ibcon#*mode == 0, iclass 20, count 2 2006.173.17:06:52.60#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.17:06:52.60#ibcon#[27=AT06-04\r\n] 2006.173.17:06:52.60#ibcon#*before write, iclass 20, count 2 2006.173.17:06:52.60#ibcon#enter sib2, iclass 20, count 2 2006.173.17:06:52.60#ibcon#flushed, iclass 20, count 2 2006.173.17:06:52.60#ibcon#about to write, iclass 20, count 2 2006.173.17:06:52.60#ibcon#wrote, iclass 20, count 2 2006.173.17:06:52.60#ibcon#about to read 3, iclass 20, count 2 2006.173.17:06:52.63#ibcon#read 3, iclass 20, count 2 2006.173.17:06:52.63#ibcon#about to read 4, iclass 20, count 2 2006.173.17:06:52.63#ibcon#read 4, iclass 20, count 2 2006.173.17:06:52.63#ibcon#about to read 5, iclass 20, count 2 2006.173.17:06:52.63#ibcon#read 5, iclass 20, count 2 2006.173.17:06:52.63#ibcon#about to read 6, iclass 20, count 2 2006.173.17:06:52.63#ibcon#read 6, iclass 20, count 2 2006.173.17:06:52.63#ibcon#end of sib2, iclass 20, count 2 2006.173.17:06:52.63#ibcon#*after write, iclass 20, count 2 2006.173.17:06:52.63#ibcon#*before return 0, iclass 20, count 2 2006.173.17:06:52.63#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.17:06:52.63#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.17:06:52.63#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.17:06:52.63#ibcon#ireg 7 cls_cnt 0 2006.173.17:06:52.63#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.17:06:52.75#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.17:06:52.75#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.17:06:52.75#ibcon#enter wrdev, iclass 20, count 0 2006.173.17:06:52.75#ibcon#first serial, iclass 20, count 0 2006.173.17:06:52.75#ibcon#enter sib2, iclass 20, count 0 2006.173.17:06:52.75#ibcon#flushed, iclass 20, count 0 2006.173.17:06:52.75#ibcon#about to write, iclass 20, count 0 2006.173.17:06:52.75#ibcon#wrote, iclass 20, count 0 2006.173.17:06:52.75#ibcon#about to read 3, iclass 20, count 0 2006.173.17:06:52.77#ibcon#read 3, iclass 20, count 0 2006.173.17:06:52.77#ibcon#about to read 4, iclass 20, count 0 2006.173.17:06:52.77#ibcon#read 4, iclass 20, count 0 2006.173.17:06:52.77#ibcon#about to read 5, iclass 20, count 0 2006.173.17:06:52.77#ibcon#read 5, iclass 20, count 0 2006.173.17:06:52.77#ibcon#about to read 6, iclass 20, count 0 2006.173.17:06:52.77#ibcon#read 6, iclass 20, count 0 2006.173.17:06:52.77#ibcon#end of sib2, iclass 20, count 0 2006.173.17:06:52.77#ibcon#*mode == 0, iclass 20, count 0 2006.173.17:06:52.77#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.17:06:52.77#ibcon#[27=USB\r\n] 2006.173.17:06:52.77#ibcon#*before write, iclass 20, count 0 2006.173.17:06:52.77#ibcon#enter sib2, iclass 20, count 0 2006.173.17:06:52.77#ibcon#flushed, iclass 20, count 0 2006.173.17:06:52.77#ibcon#about to write, iclass 20, count 0 2006.173.17:06:52.77#ibcon#wrote, iclass 20, count 0 2006.173.17:06:52.77#ibcon#about to read 3, iclass 20, count 0 2006.173.17:06:52.80#ibcon#read 3, iclass 20, count 0 2006.173.17:06:52.80#ibcon#about to read 4, iclass 20, count 0 2006.173.17:06:52.80#ibcon#read 4, iclass 20, count 0 2006.173.17:06:52.80#ibcon#about to read 5, iclass 20, count 0 2006.173.17:06:52.80#ibcon#read 5, iclass 20, count 0 2006.173.17:06:52.80#ibcon#about to read 6, iclass 20, count 0 2006.173.17:06:52.80#ibcon#read 6, iclass 20, count 0 2006.173.17:06:52.80#ibcon#end of sib2, iclass 20, count 0 2006.173.17:06:52.80#ibcon#*after write, iclass 20, count 0 2006.173.17:06:52.80#ibcon#*before return 0, iclass 20, count 0 2006.173.17:06:52.80#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.17:06:52.80#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.17:06:52.80#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.17:06:52.80#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.17:06:52.80$vck44/vblo=7,734.99 2006.173.17:06:52.80#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.17:06:52.80#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.17:06:52.80#ibcon#ireg 17 cls_cnt 0 2006.173.17:06:52.80#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.17:06:52.80#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.17:06:52.80#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.17:06:52.80#ibcon#enter wrdev, iclass 22, count 0 2006.173.17:06:52.80#ibcon#first serial, iclass 22, count 0 2006.173.17:06:52.80#ibcon#enter sib2, iclass 22, count 0 2006.173.17:06:52.80#ibcon#flushed, iclass 22, count 0 2006.173.17:06:52.80#ibcon#about to write, iclass 22, count 0 2006.173.17:06:52.80#ibcon#wrote, iclass 22, count 0 2006.173.17:06:52.80#ibcon#about to read 3, iclass 22, count 0 2006.173.17:06:52.82#ibcon#read 3, iclass 22, count 0 2006.173.17:06:52.82#ibcon#about to read 4, iclass 22, count 0 2006.173.17:06:52.82#ibcon#read 4, iclass 22, count 0 2006.173.17:06:52.82#ibcon#about to read 5, iclass 22, count 0 2006.173.17:06:52.82#ibcon#read 5, iclass 22, count 0 2006.173.17:06:52.82#ibcon#about to read 6, iclass 22, count 0 2006.173.17:06:52.82#ibcon#read 6, iclass 22, count 0 2006.173.17:06:52.82#ibcon#end of sib2, iclass 22, count 0 2006.173.17:06:52.82#ibcon#*mode == 0, iclass 22, count 0 2006.173.17:06:52.82#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.17:06:52.82#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.17:06:52.82#ibcon#*before write, iclass 22, count 0 2006.173.17:06:52.82#ibcon#enter sib2, iclass 22, count 0 2006.173.17:06:52.82#ibcon#flushed, iclass 22, count 0 2006.173.17:06:52.82#ibcon#about to write, iclass 22, count 0 2006.173.17:06:52.82#ibcon#wrote, iclass 22, count 0 2006.173.17:06:52.82#ibcon#about to read 3, iclass 22, count 0 2006.173.17:06:52.86#ibcon#read 3, iclass 22, count 0 2006.173.17:06:52.86#ibcon#about to read 4, iclass 22, count 0 2006.173.17:06:52.86#ibcon#read 4, iclass 22, count 0 2006.173.17:06:52.86#ibcon#about to read 5, iclass 22, count 0 2006.173.17:06:52.86#ibcon#read 5, iclass 22, count 0 2006.173.17:06:52.86#ibcon#about to read 6, iclass 22, count 0 2006.173.17:06:52.86#ibcon#read 6, iclass 22, count 0 2006.173.17:06:52.86#ibcon#end of sib2, iclass 22, count 0 2006.173.17:06:52.86#ibcon#*after write, iclass 22, count 0 2006.173.17:06:52.86#ibcon#*before return 0, iclass 22, count 0 2006.173.17:06:52.86#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.17:06:52.86#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.17:06:52.86#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.17:06:52.86#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.17:06:52.86$vck44/vb=7,4 2006.173.17:06:52.86#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.17:06:52.86#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.17:06:52.86#ibcon#ireg 11 cls_cnt 2 2006.173.17:06:52.86#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.17:06:52.92#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.17:06:52.92#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.17:06:52.92#ibcon#enter wrdev, iclass 24, count 2 2006.173.17:06:52.92#ibcon#first serial, iclass 24, count 2 2006.173.17:06:52.92#ibcon#enter sib2, iclass 24, count 2 2006.173.17:06:52.92#ibcon#flushed, iclass 24, count 2 2006.173.17:06:52.92#ibcon#about to write, iclass 24, count 2 2006.173.17:06:52.92#ibcon#wrote, iclass 24, count 2 2006.173.17:06:52.92#ibcon#about to read 3, iclass 24, count 2 2006.173.17:06:52.94#ibcon#read 3, iclass 24, count 2 2006.173.17:06:52.94#ibcon#about to read 4, iclass 24, count 2 2006.173.17:06:52.94#ibcon#read 4, iclass 24, count 2 2006.173.17:06:52.94#ibcon#about to read 5, iclass 24, count 2 2006.173.17:06:52.94#ibcon#read 5, iclass 24, count 2 2006.173.17:06:52.94#ibcon#about to read 6, iclass 24, count 2 2006.173.17:06:52.94#ibcon#read 6, iclass 24, count 2 2006.173.17:06:52.94#ibcon#end of sib2, iclass 24, count 2 2006.173.17:06:52.94#ibcon#*mode == 0, iclass 24, count 2 2006.173.17:06:52.94#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.17:06:52.94#ibcon#[27=AT07-04\r\n] 2006.173.17:06:52.94#ibcon#*before write, iclass 24, count 2 2006.173.17:06:52.94#ibcon#enter sib2, iclass 24, count 2 2006.173.17:06:52.94#ibcon#flushed, iclass 24, count 2 2006.173.17:06:52.94#ibcon#about to write, iclass 24, count 2 2006.173.17:06:52.94#ibcon#wrote, iclass 24, count 2 2006.173.17:06:52.94#ibcon#about to read 3, iclass 24, count 2 2006.173.17:06:52.97#ibcon#read 3, iclass 24, count 2 2006.173.17:06:52.97#ibcon#about to read 4, iclass 24, count 2 2006.173.17:06:52.97#ibcon#read 4, iclass 24, count 2 2006.173.17:06:52.97#ibcon#about to read 5, iclass 24, count 2 2006.173.17:06:52.97#ibcon#read 5, iclass 24, count 2 2006.173.17:06:52.97#ibcon#about to read 6, iclass 24, count 2 2006.173.17:06:52.97#ibcon#read 6, iclass 24, count 2 2006.173.17:06:52.97#ibcon#end of sib2, iclass 24, count 2 2006.173.17:06:52.97#ibcon#*after write, iclass 24, count 2 2006.173.17:06:52.97#ibcon#*before return 0, iclass 24, count 2 2006.173.17:06:52.97#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.17:06:52.97#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.17:06:52.97#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.17:06:52.97#ibcon#ireg 7 cls_cnt 0 2006.173.17:06:52.97#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.17:06:53.09#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.17:06:53.09#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.17:06:53.09#ibcon#enter wrdev, iclass 24, count 0 2006.173.17:06:53.09#ibcon#first serial, iclass 24, count 0 2006.173.17:06:53.09#ibcon#enter sib2, iclass 24, count 0 2006.173.17:06:53.09#ibcon#flushed, iclass 24, count 0 2006.173.17:06:53.09#ibcon#about to write, iclass 24, count 0 2006.173.17:06:53.09#ibcon#wrote, iclass 24, count 0 2006.173.17:06:53.09#ibcon#about to read 3, iclass 24, count 0 2006.173.17:06:53.11#ibcon#read 3, iclass 24, count 0 2006.173.17:06:53.11#ibcon#about to read 4, iclass 24, count 0 2006.173.17:06:53.11#ibcon#read 4, iclass 24, count 0 2006.173.17:06:53.11#ibcon#about to read 5, iclass 24, count 0 2006.173.17:06:53.11#ibcon#read 5, iclass 24, count 0 2006.173.17:06:53.11#ibcon#about to read 6, iclass 24, count 0 2006.173.17:06:53.11#ibcon#read 6, iclass 24, count 0 2006.173.17:06:53.11#ibcon#end of sib2, iclass 24, count 0 2006.173.17:06:53.11#ibcon#*mode == 0, iclass 24, count 0 2006.173.17:06:53.11#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.17:06:53.11#ibcon#[27=USB\r\n] 2006.173.17:06:53.11#ibcon#*before write, iclass 24, count 0 2006.173.17:06:53.11#ibcon#enter sib2, iclass 24, count 0 2006.173.17:06:53.11#ibcon#flushed, iclass 24, count 0 2006.173.17:06:53.11#ibcon#about to write, iclass 24, count 0 2006.173.17:06:53.11#ibcon#wrote, iclass 24, count 0 2006.173.17:06:53.11#ibcon#about to read 3, iclass 24, count 0 2006.173.17:06:53.14#ibcon#read 3, iclass 24, count 0 2006.173.17:06:53.14#ibcon#about to read 4, iclass 24, count 0 2006.173.17:06:53.14#ibcon#read 4, iclass 24, count 0 2006.173.17:06:53.14#ibcon#about to read 5, iclass 24, count 0 2006.173.17:06:53.14#ibcon#read 5, iclass 24, count 0 2006.173.17:06:53.14#ibcon#about to read 6, iclass 24, count 0 2006.173.17:06:53.14#ibcon#read 6, iclass 24, count 0 2006.173.17:06:53.14#ibcon#end of sib2, iclass 24, count 0 2006.173.17:06:53.14#ibcon#*after write, iclass 24, count 0 2006.173.17:06:53.14#ibcon#*before return 0, iclass 24, count 0 2006.173.17:06:53.14#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.17:06:53.14#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.17:06:53.14#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.17:06:53.14#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.17:06:53.14$vck44/vblo=8,744.99 2006.173.17:06:53.14#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.17:06:53.14#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.17:06:53.14#ibcon#ireg 17 cls_cnt 0 2006.173.17:06:53.14#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.17:06:53.14#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.17:06:53.14#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.17:06:53.14#ibcon#enter wrdev, iclass 26, count 0 2006.173.17:06:53.14#ibcon#first serial, iclass 26, count 0 2006.173.17:06:53.14#ibcon#enter sib2, iclass 26, count 0 2006.173.17:06:53.14#ibcon#flushed, iclass 26, count 0 2006.173.17:06:53.14#ibcon#about to write, iclass 26, count 0 2006.173.17:06:53.14#ibcon#wrote, iclass 26, count 0 2006.173.17:06:53.14#ibcon#about to read 3, iclass 26, count 0 2006.173.17:06:53.16#ibcon#read 3, iclass 26, count 0 2006.173.17:06:53.16#ibcon#about to read 4, iclass 26, count 0 2006.173.17:06:53.16#ibcon#read 4, iclass 26, count 0 2006.173.17:06:53.16#ibcon#about to read 5, iclass 26, count 0 2006.173.17:06:53.16#ibcon#read 5, iclass 26, count 0 2006.173.17:06:53.16#ibcon#about to read 6, iclass 26, count 0 2006.173.17:06:53.16#ibcon#read 6, iclass 26, count 0 2006.173.17:06:53.16#ibcon#end of sib2, iclass 26, count 0 2006.173.17:06:53.16#ibcon#*mode == 0, iclass 26, count 0 2006.173.17:06:53.16#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.17:06:53.16#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.17:06:53.16#ibcon#*before write, iclass 26, count 0 2006.173.17:06:53.16#ibcon#enter sib2, iclass 26, count 0 2006.173.17:06:53.16#ibcon#flushed, iclass 26, count 0 2006.173.17:06:53.16#ibcon#about to write, iclass 26, count 0 2006.173.17:06:53.16#ibcon#wrote, iclass 26, count 0 2006.173.17:06:53.16#ibcon#about to read 3, iclass 26, count 0 2006.173.17:06:53.20#ibcon#read 3, iclass 26, count 0 2006.173.17:06:53.20#ibcon#about to read 4, iclass 26, count 0 2006.173.17:06:53.20#ibcon#read 4, iclass 26, count 0 2006.173.17:06:53.20#ibcon#about to read 5, iclass 26, count 0 2006.173.17:06:53.20#ibcon#read 5, iclass 26, count 0 2006.173.17:06:53.20#ibcon#about to read 6, iclass 26, count 0 2006.173.17:06:53.20#ibcon#read 6, iclass 26, count 0 2006.173.17:06:53.20#ibcon#end of sib2, iclass 26, count 0 2006.173.17:06:53.20#ibcon#*after write, iclass 26, count 0 2006.173.17:06:53.20#ibcon#*before return 0, iclass 26, count 0 2006.173.17:06:53.20#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.17:06:53.20#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.17:06:53.20#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.17:06:53.20#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.17:06:53.20$vck44/vb=8,4 2006.173.17:06:53.20#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.17:06:53.20#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.17:06:53.20#ibcon#ireg 11 cls_cnt 2 2006.173.17:06:53.20#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.17:06:53.26#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.17:06:53.26#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.17:06:53.26#ibcon#enter wrdev, iclass 28, count 2 2006.173.17:06:53.26#ibcon#first serial, iclass 28, count 2 2006.173.17:06:53.26#ibcon#enter sib2, iclass 28, count 2 2006.173.17:06:53.26#ibcon#flushed, iclass 28, count 2 2006.173.17:06:53.26#ibcon#about to write, iclass 28, count 2 2006.173.17:06:53.26#ibcon#wrote, iclass 28, count 2 2006.173.17:06:53.26#ibcon#about to read 3, iclass 28, count 2 2006.173.17:06:53.28#ibcon#read 3, iclass 28, count 2 2006.173.17:06:53.28#ibcon#about to read 4, iclass 28, count 2 2006.173.17:06:53.28#ibcon#read 4, iclass 28, count 2 2006.173.17:06:53.28#ibcon#about to read 5, iclass 28, count 2 2006.173.17:06:53.28#ibcon#read 5, iclass 28, count 2 2006.173.17:06:53.28#ibcon#about to read 6, iclass 28, count 2 2006.173.17:06:53.28#ibcon#read 6, iclass 28, count 2 2006.173.17:06:53.28#ibcon#end of sib2, iclass 28, count 2 2006.173.17:06:53.28#ibcon#*mode == 0, iclass 28, count 2 2006.173.17:06:53.28#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.17:06:53.28#ibcon#[27=AT08-04\r\n] 2006.173.17:06:53.28#ibcon#*before write, iclass 28, count 2 2006.173.17:06:53.28#ibcon#enter sib2, iclass 28, count 2 2006.173.17:06:53.28#ibcon#flushed, iclass 28, count 2 2006.173.17:06:53.28#ibcon#about to write, iclass 28, count 2 2006.173.17:06:53.28#ibcon#wrote, iclass 28, count 2 2006.173.17:06:53.28#ibcon#about to read 3, iclass 28, count 2 2006.173.17:06:53.31#ibcon#read 3, iclass 28, count 2 2006.173.17:06:53.31#ibcon#about to read 4, iclass 28, count 2 2006.173.17:06:53.31#ibcon#read 4, iclass 28, count 2 2006.173.17:06:53.31#ibcon#about to read 5, iclass 28, count 2 2006.173.17:06:53.31#ibcon#read 5, iclass 28, count 2 2006.173.17:06:53.31#ibcon#about to read 6, iclass 28, count 2 2006.173.17:06:53.31#ibcon#read 6, iclass 28, count 2 2006.173.17:06:53.31#ibcon#end of sib2, iclass 28, count 2 2006.173.17:06:53.31#ibcon#*after write, iclass 28, count 2 2006.173.17:06:53.31#ibcon#*before return 0, iclass 28, count 2 2006.173.17:06:53.31#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.17:06:53.31#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.17:06:53.31#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.17:06:53.31#ibcon#ireg 7 cls_cnt 0 2006.173.17:06:53.31#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.17:06:53.43#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.17:06:53.43#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.17:06:53.43#ibcon#enter wrdev, iclass 28, count 0 2006.173.17:06:53.43#ibcon#first serial, iclass 28, count 0 2006.173.17:06:53.43#ibcon#enter sib2, iclass 28, count 0 2006.173.17:06:53.43#ibcon#flushed, iclass 28, count 0 2006.173.17:06:53.43#ibcon#about to write, iclass 28, count 0 2006.173.17:06:53.43#ibcon#wrote, iclass 28, count 0 2006.173.17:06:53.43#ibcon#about to read 3, iclass 28, count 0 2006.173.17:06:53.45#ibcon#read 3, iclass 28, count 0 2006.173.17:06:53.45#ibcon#about to read 4, iclass 28, count 0 2006.173.17:06:53.45#ibcon#read 4, iclass 28, count 0 2006.173.17:06:53.45#ibcon#about to read 5, iclass 28, count 0 2006.173.17:06:53.45#ibcon#read 5, iclass 28, count 0 2006.173.17:06:53.45#ibcon#about to read 6, iclass 28, count 0 2006.173.17:06:53.45#ibcon#read 6, iclass 28, count 0 2006.173.17:06:53.45#ibcon#end of sib2, iclass 28, count 0 2006.173.17:06:53.45#ibcon#*mode == 0, iclass 28, count 0 2006.173.17:06:53.45#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.17:06:53.45#ibcon#[27=USB\r\n] 2006.173.17:06:53.45#ibcon#*before write, iclass 28, count 0 2006.173.17:06:53.45#ibcon#enter sib2, iclass 28, count 0 2006.173.17:06:53.45#ibcon#flushed, iclass 28, count 0 2006.173.17:06:53.45#ibcon#about to write, iclass 28, count 0 2006.173.17:06:53.45#ibcon#wrote, iclass 28, count 0 2006.173.17:06:53.45#ibcon#about to read 3, iclass 28, count 0 2006.173.17:06:53.48#ibcon#read 3, iclass 28, count 0 2006.173.17:06:53.48#ibcon#about to read 4, iclass 28, count 0 2006.173.17:06:53.48#ibcon#read 4, iclass 28, count 0 2006.173.17:06:53.48#ibcon#about to read 5, iclass 28, count 0 2006.173.17:06:53.48#ibcon#read 5, iclass 28, count 0 2006.173.17:06:53.48#ibcon#about to read 6, iclass 28, count 0 2006.173.17:06:53.48#ibcon#read 6, iclass 28, count 0 2006.173.17:06:53.48#ibcon#end of sib2, iclass 28, count 0 2006.173.17:06:53.48#ibcon#*after write, iclass 28, count 0 2006.173.17:06:53.48#ibcon#*before return 0, iclass 28, count 0 2006.173.17:06:53.48#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.17:06:53.48#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.17:06:53.48#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.17:06:53.48#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.17:06:53.48$vck44/vabw=wide 2006.173.17:06:53.48#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.17:06:53.48#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.17:06:53.48#ibcon#ireg 8 cls_cnt 0 2006.173.17:06:53.48#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.17:06:53.48#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.17:06:53.48#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.17:06:53.48#ibcon#enter wrdev, iclass 30, count 0 2006.173.17:06:53.48#ibcon#first serial, iclass 30, count 0 2006.173.17:06:53.48#ibcon#enter sib2, iclass 30, count 0 2006.173.17:06:53.48#ibcon#flushed, iclass 30, count 0 2006.173.17:06:53.48#ibcon#about to write, iclass 30, count 0 2006.173.17:06:53.48#ibcon#wrote, iclass 30, count 0 2006.173.17:06:53.48#ibcon#about to read 3, iclass 30, count 0 2006.173.17:06:53.50#ibcon#read 3, iclass 30, count 0 2006.173.17:06:53.50#ibcon#about to read 4, iclass 30, count 0 2006.173.17:06:53.50#ibcon#read 4, iclass 30, count 0 2006.173.17:06:53.50#ibcon#about to read 5, iclass 30, count 0 2006.173.17:06:53.50#ibcon#read 5, iclass 30, count 0 2006.173.17:06:53.50#ibcon#about to read 6, iclass 30, count 0 2006.173.17:06:53.50#ibcon#read 6, iclass 30, count 0 2006.173.17:06:53.50#ibcon#end of sib2, iclass 30, count 0 2006.173.17:06:53.50#ibcon#*mode == 0, iclass 30, count 0 2006.173.17:06:53.50#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.17:06:53.50#ibcon#[25=BW32\r\n] 2006.173.17:06:53.50#ibcon#*before write, iclass 30, count 0 2006.173.17:06:53.50#ibcon#enter sib2, iclass 30, count 0 2006.173.17:06:53.50#ibcon#flushed, iclass 30, count 0 2006.173.17:06:53.50#ibcon#about to write, iclass 30, count 0 2006.173.17:06:53.50#ibcon#wrote, iclass 30, count 0 2006.173.17:06:53.50#ibcon#about to read 3, iclass 30, count 0 2006.173.17:06:53.53#ibcon#read 3, iclass 30, count 0 2006.173.17:06:53.53#ibcon#about to read 4, iclass 30, count 0 2006.173.17:06:53.53#ibcon#read 4, iclass 30, count 0 2006.173.17:06:53.53#ibcon#about to read 5, iclass 30, count 0 2006.173.17:06:53.53#ibcon#read 5, iclass 30, count 0 2006.173.17:06:53.53#ibcon#about to read 6, iclass 30, count 0 2006.173.17:06:53.53#ibcon#read 6, iclass 30, count 0 2006.173.17:06:53.53#ibcon#end of sib2, iclass 30, count 0 2006.173.17:06:53.53#ibcon#*after write, iclass 30, count 0 2006.173.17:06:53.53#ibcon#*before return 0, iclass 30, count 0 2006.173.17:06:53.53#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.17:06:53.53#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.17:06:53.53#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.17:06:53.53#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.17:06:53.53$vck44/vbbw=wide 2006.173.17:06:53.53#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.17:06:53.53#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.17:06:53.53#ibcon#ireg 8 cls_cnt 0 2006.173.17:06:53.53#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.17:06:53.60#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.17:06:53.60#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.17:06:53.60#ibcon#enter wrdev, iclass 32, count 0 2006.173.17:06:53.60#ibcon#first serial, iclass 32, count 0 2006.173.17:06:53.60#ibcon#enter sib2, iclass 32, count 0 2006.173.17:06:53.60#ibcon#flushed, iclass 32, count 0 2006.173.17:06:53.60#ibcon#about to write, iclass 32, count 0 2006.173.17:06:53.60#ibcon#wrote, iclass 32, count 0 2006.173.17:06:53.60#ibcon#about to read 3, iclass 32, count 0 2006.173.17:06:53.62#ibcon#read 3, iclass 32, count 0 2006.173.17:06:53.62#ibcon#about to read 4, iclass 32, count 0 2006.173.17:06:53.62#ibcon#read 4, iclass 32, count 0 2006.173.17:06:53.62#ibcon#about to read 5, iclass 32, count 0 2006.173.17:06:53.62#ibcon#read 5, iclass 32, count 0 2006.173.17:06:53.62#ibcon#about to read 6, iclass 32, count 0 2006.173.17:06:53.62#ibcon#read 6, iclass 32, count 0 2006.173.17:06:53.62#ibcon#end of sib2, iclass 32, count 0 2006.173.17:06:53.62#ibcon#*mode == 0, iclass 32, count 0 2006.173.17:06:53.62#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.17:06:53.62#ibcon#[27=BW32\r\n] 2006.173.17:06:53.62#ibcon#*before write, iclass 32, count 0 2006.173.17:06:53.62#ibcon#enter sib2, iclass 32, count 0 2006.173.17:06:53.62#ibcon#flushed, iclass 32, count 0 2006.173.17:06:53.62#ibcon#about to write, iclass 32, count 0 2006.173.17:06:53.62#ibcon#wrote, iclass 32, count 0 2006.173.17:06:53.62#ibcon#about to read 3, iclass 32, count 0 2006.173.17:06:53.65#ibcon#read 3, iclass 32, count 0 2006.173.17:06:53.65#ibcon#about to read 4, iclass 32, count 0 2006.173.17:06:53.65#ibcon#read 4, iclass 32, count 0 2006.173.17:06:53.65#ibcon#about to read 5, iclass 32, count 0 2006.173.17:06:53.65#ibcon#read 5, iclass 32, count 0 2006.173.17:06:53.65#ibcon#about to read 6, iclass 32, count 0 2006.173.17:06:53.65#ibcon#read 6, iclass 32, count 0 2006.173.17:06:53.65#ibcon#end of sib2, iclass 32, count 0 2006.173.17:06:53.65#ibcon#*after write, iclass 32, count 0 2006.173.17:06:53.65#ibcon#*before return 0, iclass 32, count 0 2006.173.17:06:53.65#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.17:06:53.65#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.17:06:53.65#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.17:06:53.65#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.17:06:53.65$setupk4/ifdk4 2006.173.17:06:53.65$ifdk4/lo= 2006.173.17:06:53.65$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.17:06:53.65$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.17:06:53.65$ifdk4/patch= 2006.173.17:06:53.65$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.17:06:53.65$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.17:06:53.65$setupk4/!*+20s 2006.173.17:06:56.46#abcon#<5=/14 1.2 3.0 20.281001002.8\r\n> 2006.173.17:06:56.48#abcon#{5=INTERFACE CLEAR} 2006.173.17:06:56.54#abcon#[5=S1D000X0/0*\r\n] 2006.173.17:07:06.13#trakl#Source acquired 2006.173.17:07:06.63#abcon#<5=/14 1.2 3.0 20.281001002.8\r\n> 2006.173.17:07:06.65#abcon#{5=INTERFACE CLEAR} 2006.173.17:07:06.71#abcon#[5=S1D000X0/0*\r\n] 2006.173.17:07:07.13#flagr#flagr/antenna,acquired 2006.173.17:07:08.16$setupk4/"tpicd 2006.173.17:07:08.16$setupk4/echo=off 2006.173.17:07:08.16$setupk4/xlog=off 2006.173.17:07:08.16:!2006.173.17:07:21 2006.173.17:07:21.00:preob 2006.173.17:07:21.13/onsource/TRACKING 2006.173.17:07:21.13:!2006.173.17:07:31 2006.173.17:07:31.00:"tape 2006.173.17:07:31.00:"st=record 2006.173.17:07:31.00:data_valid=on 2006.173.17:07:31.00:midob 2006.173.17:07:31.13/onsource/TRACKING 2006.173.17:07:31.13/wx/20.28,1002.8,100 2006.173.17:07:31.22/cable/+6.5151E-03 2006.173.17:07:32.31/va/01,07,usb,yes,35,38 2006.173.17:07:32.31/va/02,06,usb,yes,35,36 2006.173.17:07:32.31/va/03,05,usb,yes,44,46 2006.173.17:07:32.31/va/04,06,usb,yes,35,37 2006.173.17:07:32.31/va/05,04,usb,yes,28,28 2006.173.17:07:32.31/va/06,03,usb,yes,39,39 2006.173.17:07:32.31/va/07,04,usb,yes,31,33 2006.173.17:07:32.31/va/08,04,usb,yes,27,32 2006.173.17:07:32.54/valo/01,524.99,yes,locked 2006.173.17:07:32.54/valo/02,534.99,yes,locked 2006.173.17:07:32.54/valo/03,564.99,yes,locked 2006.173.17:07:32.54/valo/04,624.99,yes,locked 2006.173.17:07:32.54/valo/05,734.99,yes,locked 2006.173.17:07:32.54/valo/06,814.99,yes,locked 2006.173.17:07:32.54/valo/07,864.99,yes,locked 2006.173.17:07:32.54/valo/08,884.99,yes,locked 2006.173.17:07:33.63/vb/01,04,usb,yes,28,26 2006.173.17:07:33.63/vb/02,04,usb,yes,31,31 2006.173.17:07:33.63/vb/03,04,usb,yes,28,31 2006.173.17:07:33.63/vb/04,04,usb,yes,32,31 2006.173.17:07:33.63/vb/05,04,usb,yes,25,27 2006.173.17:07:33.63/vb/06,04,usb,yes,29,26 2006.173.17:07:33.63/vb/07,04,usb,yes,29,29 2006.173.17:07:33.63/vb/08,04,usb,yes,27,30 2006.173.17:07:33.86/vblo/01,629.99,yes,locked 2006.173.17:07:33.86/vblo/02,634.99,yes,locked 2006.173.17:07:33.86/vblo/03,649.99,yes,locked 2006.173.17:07:33.86/vblo/04,679.99,yes,locked 2006.173.17:07:33.86/vblo/05,709.99,yes,locked 2006.173.17:07:33.86/vblo/06,719.99,yes,locked 2006.173.17:07:33.86/vblo/07,734.99,yes,locked 2006.173.17:07:33.86/vblo/08,744.99,yes,locked 2006.173.17:07:34.01/vabw/8 2006.173.17:07:34.16/vbbw/8 2006.173.17:07:34.25/xfe/off,on,14.0 2006.173.17:07:34.63/ifatt/23,28,28,28 2006.173.17:07:35.08/fmout-gps/S +4.02E-07 2006.173.17:07:35.12:!2006.173.17:19:41 2006.173.17:19:41.02:data_valid=off 2006.173.17:19:41.02:"et 2006.173.17:19:41.02:!+3s 2006.173.17:19:44.04:"tape 2006.173.17:19:44.05:postob 2006.173.17:19:44.12/cable/+6.5136E-03 2006.173.17:19:44.13/wx/20.27,1002.7,100 2006.173.17:19:44.18/fmout-gps/S +4.01E-07 2006.173.17:19:44.19:scan_name=173-1721,jd0606,70 2006.173.17:19:44.19:source=1908-201,191109.65,-200655.1,2000.0,ccw 2006.173.17:19:46.15#flagr#flagr/antenna,new-source 2006.173.17:19:46.15:checkk5 2006.173.17:19:46.56/chk_autoobs//k5ts1/ autoobs is running! 2006.173.17:19:46.97/chk_autoobs//k5ts2/ autoobs is running! 2006.173.17:19:47.37/chk_autoobs//k5ts3/ autoobs is running! 2006.173.17:19:47.77/chk_autoobs//k5ts4/ autoobs is running! 2006.173.17:19:48.44/chk_obsdata//k5ts1/T1731707??a.dat file size is correct (nominal:2920MB, actual:2916MB). 2006.173.17:19:49.15/chk_obsdata//k5ts2/T1731707??b.dat file size is correct (nominal:2920MB, actual:2916MB). 2006.173.17:19:49.86/chk_obsdata//k5ts3/T1731707??c.dat file size is correct (nominal:2920MB, actual:2916MB). 2006.173.17:19:50.57/chk_obsdata//k5ts4/T1731707??d.dat file size is correct (nominal:2920MB, actual:2916MB). 2006.173.17:19:51.29/k5log//k5ts1_log_newline 2006.173.17:19:52.00/k5log//k5ts2_log_newline 2006.173.17:19:52.72/k5log//k5ts3_log_newline 2006.173.17:19:53.43/k5log//k5ts4_log_newline 2006.173.17:19:53.45/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.17:19:53.45:setupk4=1 2006.173.17:19:53.45$setupk4/echo=on 2006.173.17:19:53.45$setupk4/pcalon 2006.173.17:19:53.45$pcalon/"no phase cal control is implemented here 2006.173.17:19:53.45$setupk4/"tpicd=stop 2006.173.17:19:53.45$setupk4/"rec=synch_on 2006.173.17:19:53.45$setupk4/"rec_mode=128 2006.173.17:19:53.45$setupk4/!* 2006.173.17:19:53.45$setupk4/recpk4 2006.173.17:19:53.45$recpk4/recpatch= 2006.173.17:19:53.46$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.17:19:53.46$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.17:19:53.46$setupk4/vck44 2006.173.17:19:53.46$vck44/valo=1,524.99 2006.173.17:19:53.46#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.17:19:53.46#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.17:19:53.46#ibcon#ireg 17 cls_cnt 0 2006.173.17:19:53.46#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.17:19:53.46#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.17:19:53.46#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.17:19:53.46#ibcon#enter wrdev, iclass 21, count 0 2006.173.17:19:53.46#ibcon#first serial, iclass 21, count 0 2006.173.17:19:53.46#ibcon#enter sib2, iclass 21, count 0 2006.173.17:19:53.46#ibcon#flushed, iclass 21, count 0 2006.173.17:19:53.46#ibcon#about to write, iclass 21, count 0 2006.173.17:19:53.46#ibcon#wrote, iclass 21, count 0 2006.173.17:19:53.46#ibcon#about to read 3, iclass 21, count 0 2006.173.17:19:53.47#ibcon#read 3, iclass 21, count 0 2006.173.17:19:53.47#ibcon#about to read 4, iclass 21, count 0 2006.173.17:19:53.47#ibcon#read 4, iclass 21, count 0 2006.173.17:19:53.47#ibcon#about to read 5, iclass 21, count 0 2006.173.17:19:53.47#ibcon#read 5, iclass 21, count 0 2006.173.17:19:53.47#ibcon#about to read 6, iclass 21, count 0 2006.173.17:19:53.47#ibcon#read 6, iclass 21, count 0 2006.173.17:19:53.47#ibcon#end of sib2, iclass 21, count 0 2006.173.17:19:53.47#ibcon#*mode == 0, iclass 21, count 0 2006.173.17:19:53.47#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.17:19:53.47#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.17:19:53.47#ibcon#*before write, iclass 21, count 0 2006.173.17:19:53.47#ibcon#enter sib2, iclass 21, count 0 2006.173.17:19:53.47#ibcon#flushed, iclass 21, count 0 2006.173.17:19:53.47#ibcon#about to write, iclass 21, count 0 2006.173.17:19:53.47#ibcon#wrote, iclass 21, count 0 2006.173.17:19:53.47#ibcon#about to read 3, iclass 21, count 0 2006.173.17:19:53.52#ibcon#read 3, iclass 21, count 0 2006.173.17:19:53.52#ibcon#about to read 4, iclass 21, count 0 2006.173.17:19:53.52#ibcon#read 4, iclass 21, count 0 2006.173.17:19:53.52#ibcon#about to read 5, iclass 21, count 0 2006.173.17:19:53.52#ibcon#read 5, iclass 21, count 0 2006.173.17:19:53.52#ibcon#about to read 6, iclass 21, count 0 2006.173.17:19:53.52#ibcon#read 6, iclass 21, count 0 2006.173.17:19:53.52#ibcon#end of sib2, iclass 21, count 0 2006.173.17:19:53.52#ibcon#*after write, iclass 21, count 0 2006.173.17:19:53.52#ibcon#*before return 0, iclass 21, count 0 2006.173.17:19:53.52#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.17:19:53.52#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.17:19:53.52#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.17:19:53.53#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.17:19:53.53$vck44/va=1,7 2006.173.17:19:53.53#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.17:19:53.53#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.17:19:53.53#ibcon#ireg 11 cls_cnt 2 2006.173.17:19:53.53#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.17:19:53.53#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.17:19:53.53#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.17:19:53.53#ibcon#enter wrdev, iclass 23, count 2 2006.173.17:19:53.53#ibcon#first serial, iclass 23, count 2 2006.173.17:19:53.53#ibcon#enter sib2, iclass 23, count 2 2006.173.17:19:53.53#ibcon#flushed, iclass 23, count 2 2006.173.17:19:53.53#ibcon#about to write, iclass 23, count 2 2006.173.17:19:53.53#ibcon#wrote, iclass 23, count 2 2006.173.17:19:53.53#ibcon#about to read 3, iclass 23, count 2 2006.173.17:19:53.54#ibcon#read 3, iclass 23, count 2 2006.173.17:19:53.54#ibcon#about to read 4, iclass 23, count 2 2006.173.17:19:53.54#ibcon#read 4, iclass 23, count 2 2006.173.17:19:53.54#ibcon#about to read 5, iclass 23, count 2 2006.173.17:19:53.54#ibcon#read 5, iclass 23, count 2 2006.173.17:19:53.54#ibcon#about to read 6, iclass 23, count 2 2006.173.17:19:53.54#ibcon#read 6, iclass 23, count 2 2006.173.17:19:53.54#ibcon#end of sib2, iclass 23, count 2 2006.173.17:19:53.54#ibcon#*mode == 0, iclass 23, count 2 2006.173.17:19:53.54#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.17:19:53.54#ibcon#[25=AT01-07\r\n] 2006.173.17:19:53.54#ibcon#*before write, iclass 23, count 2 2006.173.17:19:53.54#ibcon#enter sib2, iclass 23, count 2 2006.173.17:19:53.54#ibcon#flushed, iclass 23, count 2 2006.173.17:19:53.54#ibcon#about to write, iclass 23, count 2 2006.173.17:19:53.54#ibcon#wrote, iclass 23, count 2 2006.173.17:19:53.54#ibcon#about to read 3, iclass 23, count 2 2006.173.17:19:53.57#ibcon#read 3, iclass 23, count 2 2006.173.17:19:53.57#ibcon#about to read 4, iclass 23, count 2 2006.173.17:19:53.57#ibcon#read 4, iclass 23, count 2 2006.173.17:19:53.57#ibcon#about to read 5, iclass 23, count 2 2006.173.17:19:53.57#ibcon#read 5, iclass 23, count 2 2006.173.17:19:53.57#ibcon#about to read 6, iclass 23, count 2 2006.173.17:19:53.57#ibcon#read 6, iclass 23, count 2 2006.173.17:19:53.57#ibcon#end of sib2, iclass 23, count 2 2006.173.17:19:53.57#ibcon#*after write, iclass 23, count 2 2006.173.17:19:53.57#ibcon#*before return 0, iclass 23, count 2 2006.173.17:19:53.57#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.17:19:53.57#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.17:19:53.57#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.17:19:53.57#ibcon#ireg 7 cls_cnt 0 2006.173.17:19:53.57#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.17:19:53.69#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.17:19:53.69#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.17:19:53.69#ibcon#enter wrdev, iclass 23, count 0 2006.173.17:19:53.69#ibcon#first serial, iclass 23, count 0 2006.173.17:19:53.69#ibcon#enter sib2, iclass 23, count 0 2006.173.17:19:53.69#ibcon#flushed, iclass 23, count 0 2006.173.17:19:53.69#ibcon#about to write, iclass 23, count 0 2006.173.17:19:53.69#ibcon#wrote, iclass 23, count 0 2006.173.17:19:53.69#ibcon#about to read 3, iclass 23, count 0 2006.173.17:19:53.71#ibcon#read 3, iclass 23, count 0 2006.173.17:19:53.71#ibcon#about to read 4, iclass 23, count 0 2006.173.17:19:53.71#ibcon#read 4, iclass 23, count 0 2006.173.17:19:53.71#ibcon#about to read 5, iclass 23, count 0 2006.173.17:19:53.71#ibcon#read 5, iclass 23, count 0 2006.173.17:19:53.71#ibcon#about to read 6, iclass 23, count 0 2006.173.17:19:53.71#ibcon#read 6, iclass 23, count 0 2006.173.17:19:53.71#ibcon#end of sib2, iclass 23, count 0 2006.173.17:19:53.71#ibcon#*mode == 0, iclass 23, count 0 2006.173.17:19:53.71#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.17:19:53.71#ibcon#[25=USB\r\n] 2006.173.17:19:53.71#ibcon#*before write, iclass 23, count 0 2006.173.17:19:53.71#ibcon#enter sib2, iclass 23, count 0 2006.173.17:19:53.71#ibcon#flushed, iclass 23, count 0 2006.173.17:19:53.71#ibcon#about to write, iclass 23, count 0 2006.173.17:19:53.72#ibcon#wrote, iclass 23, count 0 2006.173.17:19:53.72#ibcon#about to read 3, iclass 23, count 0 2006.173.17:19:53.74#ibcon#read 3, iclass 23, count 0 2006.173.17:19:53.74#ibcon#about to read 4, iclass 23, count 0 2006.173.17:19:53.74#ibcon#read 4, iclass 23, count 0 2006.173.17:19:53.74#ibcon#about to read 5, iclass 23, count 0 2006.173.17:19:53.74#ibcon#read 5, iclass 23, count 0 2006.173.17:19:53.74#ibcon#about to read 6, iclass 23, count 0 2006.173.17:19:53.74#ibcon#read 6, iclass 23, count 0 2006.173.17:19:53.74#ibcon#end of sib2, iclass 23, count 0 2006.173.17:19:53.74#ibcon#*after write, iclass 23, count 0 2006.173.17:19:53.74#ibcon#*before return 0, iclass 23, count 0 2006.173.17:19:53.74#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.17:19:53.74#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.17:19:53.74#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.17:19:53.74#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.17:19:53.75$vck44/valo=2,534.99 2006.173.17:19:53.75#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.17:19:53.75#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.17:19:53.75#ibcon#ireg 17 cls_cnt 0 2006.173.17:19:53.75#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.17:19:53.75#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.17:19:53.75#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.17:19:53.75#ibcon#enter wrdev, iclass 25, count 0 2006.173.17:19:53.75#ibcon#first serial, iclass 25, count 0 2006.173.17:19:53.75#ibcon#enter sib2, iclass 25, count 0 2006.173.17:19:53.75#ibcon#flushed, iclass 25, count 0 2006.173.17:19:53.75#ibcon#about to write, iclass 25, count 0 2006.173.17:19:53.75#ibcon#wrote, iclass 25, count 0 2006.173.17:19:53.75#ibcon#about to read 3, iclass 25, count 0 2006.173.17:19:53.76#ibcon#read 3, iclass 25, count 0 2006.173.17:19:53.76#ibcon#about to read 4, iclass 25, count 0 2006.173.17:19:53.76#ibcon#read 4, iclass 25, count 0 2006.173.17:19:53.76#ibcon#about to read 5, iclass 25, count 0 2006.173.17:19:53.76#ibcon#read 5, iclass 25, count 0 2006.173.17:19:53.76#ibcon#about to read 6, iclass 25, count 0 2006.173.17:19:53.76#ibcon#read 6, iclass 25, count 0 2006.173.17:19:53.76#ibcon#end of sib2, iclass 25, count 0 2006.173.17:19:53.76#ibcon#*mode == 0, iclass 25, count 0 2006.173.17:19:53.76#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.17:19:53.76#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.17:19:53.76#ibcon#*before write, iclass 25, count 0 2006.173.17:19:53.76#ibcon#enter sib2, iclass 25, count 0 2006.173.17:19:53.76#ibcon#flushed, iclass 25, count 0 2006.173.17:19:53.76#ibcon#about to write, iclass 25, count 0 2006.173.17:19:53.76#ibcon#wrote, iclass 25, count 0 2006.173.17:19:53.76#ibcon#about to read 3, iclass 25, count 0 2006.173.17:19:53.80#ibcon#read 3, iclass 25, count 0 2006.173.17:19:53.80#ibcon#about to read 4, iclass 25, count 0 2006.173.17:19:53.80#ibcon#read 4, iclass 25, count 0 2006.173.17:19:53.80#ibcon#about to read 5, iclass 25, count 0 2006.173.17:19:53.80#ibcon#read 5, iclass 25, count 0 2006.173.17:19:53.80#ibcon#about to read 6, iclass 25, count 0 2006.173.17:19:53.80#ibcon#read 6, iclass 25, count 0 2006.173.17:19:53.80#ibcon#end of sib2, iclass 25, count 0 2006.173.17:19:53.80#ibcon#*after write, iclass 25, count 0 2006.173.17:19:53.80#ibcon#*before return 0, iclass 25, count 0 2006.173.17:19:53.80#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.17:19:53.80#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.17:19:53.80#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.17:19:53.80#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.17:19:53.81$vck44/va=2,6 2006.173.17:19:53.81#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.17:19:53.81#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.17:19:53.81#ibcon#ireg 11 cls_cnt 2 2006.173.17:19:53.81#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.17:19:53.85#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.17:19:53.85#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.17:19:53.85#ibcon#enter wrdev, iclass 27, count 2 2006.173.17:19:53.85#ibcon#first serial, iclass 27, count 2 2006.173.17:19:53.85#ibcon#enter sib2, iclass 27, count 2 2006.173.17:19:53.85#ibcon#flushed, iclass 27, count 2 2006.173.17:19:53.85#ibcon#about to write, iclass 27, count 2 2006.173.17:19:53.85#ibcon#wrote, iclass 27, count 2 2006.173.17:19:53.85#ibcon#about to read 3, iclass 27, count 2 2006.173.17:19:53.87#ibcon#read 3, iclass 27, count 2 2006.173.17:19:53.87#ibcon#about to read 4, iclass 27, count 2 2006.173.17:19:53.87#ibcon#read 4, iclass 27, count 2 2006.173.17:19:53.87#ibcon#about to read 5, iclass 27, count 2 2006.173.17:19:53.87#ibcon#read 5, iclass 27, count 2 2006.173.17:19:53.87#ibcon#about to read 6, iclass 27, count 2 2006.173.17:19:53.87#ibcon#read 6, iclass 27, count 2 2006.173.17:19:53.87#ibcon#end of sib2, iclass 27, count 2 2006.173.17:19:53.87#ibcon#*mode == 0, iclass 27, count 2 2006.173.17:19:53.87#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.17:19:53.87#ibcon#[25=AT02-06\r\n] 2006.173.17:19:53.87#ibcon#*before write, iclass 27, count 2 2006.173.17:19:53.87#ibcon#enter sib2, iclass 27, count 2 2006.173.17:19:53.87#ibcon#flushed, iclass 27, count 2 2006.173.17:19:53.87#ibcon#about to write, iclass 27, count 2 2006.173.17:19:53.87#ibcon#wrote, iclass 27, count 2 2006.173.17:19:53.87#ibcon#about to read 3, iclass 27, count 2 2006.173.17:19:53.90#ibcon#read 3, iclass 27, count 2 2006.173.17:19:53.90#ibcon#about to read 4, iclass 27, count 2 2006.173.17:19:53.90#ibcon#read 4, iclass 27, count 2 2006.173.17:19:53.90#ibcon#about to read 5, iclass 27, count 2 2006.173.17:19:53.90#ibcon#read 5, iclass 27, count 2 2006.173.17:19:53.90#ibcon#about to read 6, iclass 27, count 2 2006.173.17:19:53.90#ibcon#read 6, iclass 27, count 2 2006.173.17:19:53.90#ibcon#end of sib2, iclass 27, count 2 2006.173.17:19:53.90#ibcon#*after write, iclass 27, count 2 2006.173.17:19:53.90#ibcon#*before return 0, iclass 27, count 2 2006.173.17:19:53.90#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.17:19:53.90#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.17:19:53.90#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.17:19:53.90#ibcon#ireg 7 cls_cnt 0 2006.173.17:19:53.90#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.17:19:54.02#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.17:19:54.02#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.17:19:54.02#ibcon#enter wrdev, iclass 27, count 0 2006.173.17:19:54.02#ibcon#first serial, iclass 27, count 0 2006.173.17:19:54.02#ibcon#enter sib2, iclass 27, count 0 2006.173.17:19:54.02#ibcon#flushed, iclass 27, count 0 2006.173.17:19:54.02#ibcon#about to write, iclass 27, count 0 2006.173.17:19:54.02#ibcon#wrote, iclass 27, count 0 2006.173.17:19:54.02#ibcon#about to read 3, iclass 27, count 0 2006.173.17:19:54.04#ibcon#read 3, iclass 27, count 0 2006.173.17:19:54.04#ibcon#about to read 4, iclass 27, count 0 2006.173.17:19:54.04#ibcon#read 4, iclass 27, count 0 2006.173.17:19:54.04#ibcon#about to read 5, iclass 27, count 0 2006.173.17:19:54.04#ibcon#read 5, iclass 27, count 0 2006.173.17:19:54.04#ibcon#about to read 6, iclass 27, count 0 2006.173.17:19:54.04#ibcon#read 6, iclass 27, count 0 2006.173.17:19:54.04#ibcon#end of sib2, iclass 27, count 0 2006.173.17:19:54.04#ibcon#*mode == 0, iclass 27, count 0 2006.173.17:19:54.04#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.17:19:54.04#ibcon#[25=USB\r\n] 2006.173.17:19:54.04#ibcon#*before write, iclass 27, count 0 2006.173.17:19:54.04#ibcon#enter sib2, iclass 27, count 0 2006.173.17:19:54.04#ibcon#flushed, iclass 27, count 0 2006.173.17:19:54.04#ibcon#about to write, iclass 27, count 0 2006.173.17:19:54.04#ibcon#wrote, iclass 27, count 0 2006.173.17:19:54.04#ibcon#about to read 3, iclass 27, count 0 2006.173.17:19:54.07#ibcon#read 3, iclass 27, count 0 2006.173.17:19:54.07#ibcon#about to read 4, iclass 27, count 0 2006.173.17:19:54.07#ibcon#read 4, iclass 27, count 0 2006.173.17:19:54.07#ibcon#about to read 5, iclass 27, count 0 2006.173.17:19:54.07#ibcon#read 5, iclass 27, count 0 2006.173.17:19:54.07#ibcon#about to read 6, iclass 27, count 0 2006.173.17:19:54.07#ibcon#read 6, iclass 27, count 0 2006.173.17:19:54.07#ibcon#end of sib2, iclass 27, count 0 2006.173.17:19:54.07#ibcon#*after write, iclass 27, count 0 2006.173.17:19:54.07#ibcon#*before return 0, iclass 27, count 0 2006.173.17:19:54.07#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.17:19:54.07#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.17:19:54.07#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.17:19:54.07#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.17:19:54.08$vck44/valo=3,564.99 2006.173.17:19:54.08#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.17:19:54.08#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.17:19:54.08#ibcon#ireg 17 cls_cnt 0 2006.173.17:19:54.08#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.17:19:54.08#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.17:19:54.08#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.17:19:54.08#ibcon#enter wrdev, iclass 29, count 0 2006.173.17:19:54.08#ibcon#first serial, iclass 29, count 0 2006.173.17:19:54.08#ibcon#enter sib2, iclass 29, count 0 2006.173.17:19:54.08#ibcon#flushed, iclass 29, count 0 2006.173.17:19:54.08#ibcon#about to write, iclass 29, count 0 2006.173.17:19:54.08#ibcon#wrote, iclass 29, count 0 2006.173.17:19:54.08#ibcon#about to read 3, iclass 29, count 0 2006.173.17:19:54.09#ibcon#read 3, iclass 29, count 0 2006.173.17:19:54.09#ibcon#about to read 4, iclass 29, count 0 2006.173.17:19:54.09#ibcon#read 4, iclass 29, count 0 2006.173.17:19:54.09#ibcon#about to read 5, iclass 29, count 0 2006.173.17:19:54.09#ibcon#read 5, iclass 29, count 0 2006.173.17:19:54.09#ibcon#about to read 6, iclass 29, count 0 2006.173.17:19:54.09#ibcon#read 6, iclass 29, count 0 2006.173.17:19:54.09#ibcon#end of sib2, iclass 29, count 0 2006.173.17:19:54.09#ibcon#*mode == 0, iclass 29, count 0 2006.173.17:19:54.09#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.17:19:54.09#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.17:19:54.09#ibcon#*before write, iclass 29, count 0 2006.173.17:19:54.09#ibcon#enter sib2, iclass 29, count 0 2006.173.17:19:54.09#ibcon#flushed, iclass 29, count 0 2006.173.17:19:54.09#ibcon#about to write, iclass 29, count 0 2006.173.17:19:54.09#ibcon#wrote, iclass 29, count 0 2006.173.17:19:54.09#ibcon#about to read 3, iclass 29, count 0 2006.173.17:19:54.13#ibcon#read 3, iclass 29, count 0 2006.173.17:19:54.13#ibcon#about to read 4, iclass 29, count 0 2006.173.17:19:54.13#ibcon#read 4, iclass 29, count 0 2006.173.17:19:54.13#ibcon#about to read 5, iclass 29, count 0 2006.173.17:19:54.13#ibcon#read 5, iclass 29, count 0 2006.173.17:19:54.13#ibcon#about to read 6, iclass 29, count 0 2006.173.17:19:54.13#ibcon#read 6, iclass 29, count 0 2006.173.17:19:54.13#ibcon#end of sib2, iclass 29, count 0 2006.173.17:19:54.13#ibcon#*after write, iclass 29, count 0 2006.173.17:19:54.13#ibcon#*before return 0, iclass 29, count 0 2006.173.17:19:54.13#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.17:19:54.13#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.17:19:54.13#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.17:19:54.13#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.17:19:54.14$vck44/va=3,5 2006.173.17:19:54.14#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.17:19:54.14#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.17:19:54.14#ibcon#ireg 11 cls_cnt 2 2006.173.17:19:54.14#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.17:19:54.18#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.17:19:54.18#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.17:19:54.18#ibcon#enter wrdev, iclass 31, count 2 2006.173.17:19:54.18#ibcon#first serial, iclass 31, count 2 2006.173.17:19:54.18#ibcon#enter sib2, iclass 31, count 2 2006.173.17:19:54.18#ibcon#flushed, iclass 31, count 2 2006.173.17:19:54.18#ibcon#about to write, iclass 31, count 2 2006.173.17:19:54.18#ibcon#wrote, iclass 31, count 2 2006.173.17:19:54.18#ibcon#about to read 3, iclass 31, count 2 2006.173.17:19:54.20#ibcon#read 3, iclass 31, count 2 2006.173.17:19:54.20#ibcon#about to read 4, iclass 31, count 2 2006.173.17:19:54.20#ibcon#read 4, iclass 31, count 2 2006.173.17:19:54.20#ibcon#about to read 5, iclass 31, count 2 2006.173.17:19:54.20#ibcon#read 5, iclass 31, count 2 2006.173.17:19:54.20#ibcon#about to read 6, iclass 31, count 2 2006.173.17:19:54.20#ibcon#read 6, iclass 31, count 2 2006.173.17:19:54.20#ibcon#end of sib2, iclass 31, count 2 2006.173.17:19:54.20#ibcon#*mode == 0, iclass 31, count 2 2006.173.17:19:54.20#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.17:19:54.20#ibcon#[25=AT03-05\r\n] 2006.173.17:19:54.20#ibcon#*before write, iclass 31, count 2 2006.173.17:19:54.20#ibcon#enter sib2, iclass 31, count 2 2006.173.17:19:54.20#ibcon#flushed, iclass 31, count 2 2006.173.17:19:54.20#ibcon#about to write, iclass 31, count 2 2006.173.17:19:54.20#ibcon#wrote, iclass 31, count 2 2006.173.17:19:54.20#ibcon#about to read 3, iclass 31, count 2 2006.173.17:19:54.23#ibcon#read 3, iclass 31, count 2 2006.173.17:19:54.23#ibcon#about to read 4, iclass 31, count 2 2006.173.17:19:54.23#ibcon#read 4, iclass 31, count 2 2006.173.17:19:54.23#ibcon#about to read 5, iclass 31, count 2 2006.173.17:19:54.23#ibcon#read 5, iclass 31, count 2 2006.173.17:19:54.23#ibcon#about to read 6, iclass 31, count 2 2006.173.17:19:54.23#ibcon#read 6, iclass 31, count 2 2006.173.17:19:54.23#ibcon#end of sib2, iclass 31, count 2 2006.173.17:19:54.23#ibcon#*after write, iclass 31, count 2 2006.173.17:19:54.23#ibcon#*before return 0, iclass 31, count 2 2006.173.17:19:54.23#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.17:19:54.23#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.17:19:54.23#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.17:19:54.23#ibcon#ireg 7 cls_cnt 0 2006.173.17:19:54.23#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.17:19:54.35#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.17:19:54.35#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.17:19:54.35#ibcon#enter wrdev, iclass 31, count 0 2006.173.17:19:54.35#ibcon#first serial, iclass 31, count 0 2006.173.17:19:54.35#ibcon#enter sib2, iclass 31, count 0 2006.173.17:19:54.35#ibcon#flushed, iclass 31, count 0 2006.173.17:19:54.35#ibcon#about to write, iclass 31, count 0 2006.173.17:19:54.35#ibcon#wrote, iclass 31, count 0 2006.173.17:19:54.35#ibcon#about to read 3, iclass 31, count 0 2006.173.17:19:54.37#ibcon#read 3, iclass 31, count 0 2006.173.17:19:54.37#ibcon#about to read 4, iclass 31, count 0 2006.173.17:19:54.37#ibcon#read 4, iclass 31, count 0 2006.173.17:19:54.37#ibcon#about to read 5, iclass 31, count 0 2006.173.17:19:54.37#ibcon#read 5, iclass 31, count 0 2006.173.17:19:54.37#ibcon#about to read 6, iclass 31, count 0 2006.173.17:19:54.37#ibcon#read 6, iclass 31, count 0 2006.173.17:19:54.37#ibcon#end of sib2, iclass 31, count 0 2006.173.17:19:54.37#ibcon#*mode == 0, iclass 31, count 0 2006.173.17:19:54.37#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.17:19:54.37#ibcon#[25=USB\r\n] 2006.173.17:19:54.37#ibcon#*before write, iclass 31, count 0 2006.173.17:19:54.37#ibcon#enter sib2, iclass 31, count 0 2006.173.17:19:54.37#ibcon#flushed, iclass 31, count 0 2006.173.17:19:54.37#ibcon#about to write, iclass 31, count 0 2006.173.17:19:54.37#ibcon#wrote, iclass 31, count 0 2006.173.17:19:54.37#ibcon#about to read 3, iclass 31, count 0 2006.173.17:19:54.40#ibcon#read 3, iclass 31, count 0 2006.173.17:19:54.40#ibcon#about to read 4, iclass 31, count 0 2006.173.17:19:54.40#ibcon#read 4, iclass 31, count 0 2006.173.17:19:54.40#ibcon#about to read 5, iclass 31, count 0 2006.173.17:19:54.40#ibcon#read 5, iclass 31, count 0 2006.173.17:19:54.40#ibcon#about to read 6, iclass 31, count 0 2006.173.17:19:54.40#ibcon#read 6, iclass 31, count 0 2006.173.17:19:54.40#ibcon#end of sib2, iclass 31, count 0 2006.173.17:19:54.40#ibcon#*after write, iclass 31, count 0 2006.173.17:19:54.40#ibcon#*before return 0, iclass 31, count 0 2006.173.17:19:54.40#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.17:19:54.40#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.17:19:54.40#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.17:19:54.40#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.17:19:54.41$vck44/valo=4,624.99 2006.173.17:19:54.41#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.17:19:54.41#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.17:19:54.41#ibcon#ireg 17 cls_cnt 0 2006.173.17:19:54.41#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.17:19:54.41#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.17:19:54.41#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.17:19:54.41#ibcon#enter wrdev, iclass 33, count 0 2006.173.17:19:54.41#ibcon#first serial, iclass 33, count 0 2006.173.17:19:54.41#ibcon#enter sib2, iclass 33, count 0 2006.173.17:19:54.41#ibcon#flushed, iclass 33, count 0 2006.173.17:19:54.41#ibcon#about to write, iclass 33, count 0 2006.173.17:19:54.41#ibcon#wrote, iclass 33, count 0 2006.173.17:19:54.41#ibcon#about to read 3, iclass 33, count 0 2006.173.17:19:54.42#ibcon#read 3, iclass 33, count 0 2006.173.17:19:54.42#ibcon#about to read 4, iclass 33, count 0 2006.173.17:19:54.42#ibcon#read 4, iclass 33, count 0 2006.173.17:19:54.42#ibcon#about to read 5, iclass 33, count 0 2006.173.17:19:54.42#ibcon#read 5, iclass 33, count 0 2006.173.17:19:54.42#ibcon#about to read 6, iclass 33, count 0 2006.173.17:19:54.42#ibcon#read 6, iclass 33, count 0 2006.173.17:19:54.42#ibcon#end of sib2, iclass 33, count 0 2006.173.17:19:54.42#ibcon#*mode == 0, iclass 33, count 0 2006.173.17:19:54.42#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.17:19:54.42#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.17:19:54.42#ibcon#*before write, iclass 33, count 0 2006.173.17:19:54.42#ibcon#enter sib2, iclass 33, count 0 2006.173.17:19:54.42#ibcon#flushed, iclass 33, count 0 2006.173.17:19:54.42#ibcon#about to write, iclass 33, count 0 2006.173.17:19:54.42#ibcon#wrote, iclass 33, count 0 2006.173.17:19:54.42#ibcon#about to read 3, iclass 33, count 0 2006.173.17:19:54.46#ibcon#read 3, iclass 33, count 0 2006.173.17:19:54.46#ibcon#about to read 4, iclass 33, count 0 2006.173.17:19:54.46#ibcon#read 4, iclass 33, count 0 2006.173.17:19:54.46#ibcon#about to read 5, iclass 33, count 0 2006.173.17:19:54.46#ibcon#read 5, iclass 33, count 0 2006.173.17:19:54.46#ibcon#about to read 6, iclass 33, count 0 2006.173.17:19:54.46#ibcon#read 6, iclass 33, count 0 2006.173.17:19:54.46#ibcon#end of sib2, iclass 33, count 0 2006.173.17:19:54.46#ibcon#*after write, iclass 33, count 0 2006.173.17:19:54.46#ibcon#*before return 0, iclass 33, count 0 2006.173.17:19:54.46#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.17:19:54.46#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.17:19:54.46#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.17:19:54.46#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.17:19:54.47$vck44/va=4,6 2006.173.17:19:54.47#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.17:19:54.47#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.17:19:54.47#ibcon#ireg 11 cls_cnt 2 2006.173.17:19:54.47#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.17:19:54.51#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.17:19:54.51#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.17:19:54.51#ibcon#enter wrdev, iclass 35, count 2 2006.173.17:19:54.51#ibcon#first serial, iclass 35, count 2 2006.173.17:19:54.51#ibcon#enter sib2, iclass 35, count 2 2006.173.17:19:54.51#ibcon#flushed, iclass 35, count 2 2006.173.17:19:54.51#ibcon#about to write, iclass 35, count 2 2006.173.17:19:54.51#ibcon#wrote, iclass 35, count 2 2006.173.17:19:54.51#ibcon#about to read 3, iclass 35, count 2 2006.173.17:19:54.53#ibcon#read 3, iclass 35, count 2 2006.173.17:19:54.53#ibcon#about to read 4, iclass 35, count 2 2006.173.17:19:54.53#ibcon#read 4, iclass 35, count 2 2006.173.17:19:54.53#ibcon#about to read 5, iclass 35, count 2 2006.173.17:19:54.53#ibcon#read 5, iclass 35, count 2 2006.173.17:19:54.53#ibcon#about to read 6, iclass 35, count 2 2006.173.17:19:54.53#ibcon#read 6, iclass 35, count 2 2006.173.17:19:54.53#ibcon#end of sib2, iclass 35, count 2 2006.173.17:19:54.53#ibcon#*mode == 0, iclass 35, count 2 2006.173.17:19:54.53#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.17:19:54.53#ibcon#[25=AT04-06\r\n] 2006.173.17:19:54.53#ibcon#*before write, iclass 35, count 2 2006.173.17:19:54.53#ibcon#enter sib2, iclass 35, count 2 2006.173.17:19:54.53#ibcon#flushed, iclass 35, count 2 2006.173.17:19:54.53#ibcon#about to write, iclass 35, count 2 2006.173.17:19:54.53#ibcon#wrote, iclass 35, count 2 2006.173.17:19:54.53#ibcon#about to read 3, iclass 35, count 2 2006.173.17:19:54.56#ibcon#read 3, iclass 35, count 2 2006.173.17:19:54.56#ibcon#about to read 4, iclass 35, count 2 2006.173.17:19:54.56#ibcon#read 4, iclass 35, count 2 2006.173.17:19:54.56#ibcon#about to read 5, iclass 35, count 2 2006.173.17:19:54.56#ibcon#read 5, iclass 35, count 2 2006.173.17:19:54.56#ibcon#about to read 6, iclass 35, count 2 2006.173.17:19:54.56#ibcon#read 6, iclass 35, count 2 2006.173.17:19:54.56#ibcon#end of sib2, iclass 35, count 2 2006.173.17:19:54.56#ibcon#*after write, iclass 35, count 2 2006.173.17:19:54.56#ibcon#*before return 0, iclass 35, count 2 2006.173.17:19:54.56#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.17:19:54.56#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.17:19:54.56#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.17:19:54.56#ibcon#ireg 7 cls_cnt 0 2006.173.17:19:54.56#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.17:19:54.68#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.17:19:54.68#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.17:19:54.68#ibcon#enter wrdev, iclass 35, count 0 2006.173.17:19:54.68#ibcon#first serial, iclass 35, count 0 2006.173.17:19:54.68#ibcon#enter sib2, iclass 35, count 0 2006.173.17:19:54.68#ibcon#flushed, iclass 35, count 0 2006.173.17:19:54.68#ibcon#about to write, iclass 35, count 0 2006.173.17:19:54.68#ibcon#wrote, iclass 35, count 0 2006.173.17:19:54.68#ibcon#about to read 3, iclass 35, count 0 2006.173.17:19:54.70#ibcon#read 3, iclass 35, count 0 2006.173.17:19:54.70#ibcon#about to read 4, iclass 35, count 0 2006.173.17:19:54.70#ibcon#read 4, iclass 35, count 0 2006.173.17:19:54.70#ibcon#about to read 5, iclass 35, count 0 2006.173.17:19:54.70#ibcon#read 5, iclass 35, count 0 2006.173.17:19:54.70#ibcon#about to read 6, iclass 35, count 0 2006.173.17:19:54.70#ibcon#read 6, iclass 35, count 0 2006.173.17:19:54.70#ibcon#end of sib2, iclass 35, count 0 2006.173.17:19:54.70#ibcon#*mode == 0, iclass 35, count 0 2006.173.17:19:54.70#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.17:19:54.70#ibcon#[25=USB\r\n] 2006.173.17:19:54.70#ibcon#*before write, iclass 35, count 0 2006.173.17:19:54.70#ibcon#enter sib2, iclass 35, count 0 2006.173.17:19:54.70#ibcon#flushed, iclass 35, count 0 2006.173.17:19:54.70#ibcon#about to write, iclass 35, count 0 2006.173.17:19:54.70#ibcon#wrote, iclass 35, count 0 2006.173.17:19:54.71#ibcon#about to read 3, iclass 35, count 0 2006.173.17:19:54.73#ibcon#read 3, iclass 35, count 0 2006.173.17:19:54.73#ibcon#about to read 4, iclass 35, count 0 2006.173.17:19:54.73#ibcon#read 4, iclass 35, count 0 2006.173.17:19:54.73#ibcon#about to read 5, iclass 35, count 0 2006.173.17:19:54.73#ibcon#read 5, iclass 35, count 0 2006.173.17:19:54.73#ibcon#about to read 6, iclass 35, count 0 2006.173.17:19:54.73#ibcon#read 6, iclass 35, count 0 2006.173.17:19:54.73#ibcon#end of sib2, iclass 35, count 0 2006.173.17:19:54.73#ibcon#*after write, iclass 35, count 0 2006.173.17:19:54.73#ibcon#*before return 0, iclass 35, count 0 2006.173.17:19:54.73#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.17:19:54.73#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.17:19:54.73#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.17:19:54.73#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.17:19:54.74$vck44/valo=5,734.99 2006.173.17:19:54.74#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.17:19:54.74#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.17:19:54.74#ibcon#ireg 17 cls_cnt 0 2006.173.17:19:54.74#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.17:19:54.74#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.17:19:54.74#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.17:19:54.74#ibcon#enter wrdev, iclass 37, count 0 2006.173.17:19:54.74#ibcon#first serial, iclass 37, count 0 2006.173.17:19:54.74#ibcon#enter sib2, iclass 37, count 0 2006.173.17:19:54.74#ibcon#flushed, iclass 37, count 0 2006.173.17:19:54.74#ibcon#about to write, iclass 37, count 0 2006.173.17:19:54.74#ibcon#wrote, iclass 37, count 0 2006.173.17:19:54.74#ibcon#about to read 3, iclass 37, count 0 2006.173.17:19:54.75#ibcon#read 3, iclass 37, count 0 2006.173.17:19:54.75#ibcon#about to read 4, iclass 37, count 0 2006.173.17:19:54.75#ibcon#read 4, iclass 37, count 0 2006.173.17:19:54.75#ibcon#about to read 5, iclass 37, count 0 2006.173.17:19:54.75#ibcon#read 5, iclass 37, count 0 2006.173.17:19:54.75#ibcon#about to read 6, iclass 37, count 0 2006.173.17:19:54.75#ibcon#read 6, iclass 37, count 0 2006.173.17:19:54.75#ibcon#end of sib2, iclass 37, count 0 2006.173.17:19:54.75#ibcon#*mode == 0, iclass 37, count 0 2006.173.17:19:54.75#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.17:19:54.75#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.17:19:54.75#ibcon#*before write, iclass 37, count 0 2006.173.17:19:54.75#ibcon#enter sib2, iclass 37, count 0 2006.173.17:19:54.75#ibcon#flushed, iclass 37, count 0 2006.173.17:19:54.75#ibcon#about to write, iclass 37, count 0 2006.173.17:19:54.76#ibcon#wrote, iclass 37, count 0 2006.173.17:19:54.76#ibcon#about to read 3, iclass 37, count 0 2006.173.17:19:54.79#ibcon#read 3, iclass 37, count 0 2006.173.17:19:54.79#ibcon#about to read 4, iclass 37, count 0 2006.173.17:19:54.79#ibcon#read 4, iclass 37, count 0 2006.173.17:19:54.79#ibcon#about to read 5, iclass 37, count 0 2006.173.17:19:54.79#ibcon#read 5, iclass 37, count 0 2006.173.17:19:54.79#ibcon#about to read 6, iclass 37, count 0 2006.173.17:19:54.79#ibcon#read 6, iclass 37, count 0 2006.173.17:19:54.79#ibcon#end of sib2, iclass 37, count 0 2006.173.17:19:54.79#ibcon#*after write, iclass 37, count 0 2006.173.17:19:54.79#ibcon#*before return 0, iclass 37, count 0 2006.173.17:19:54.79#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.17:19:54.79#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.17:19:54.79#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.17:19:54.79#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.17:19:54.80$vck44/va=5,4 2006.173.17:19:54.80#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.17:19:54.80#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.17:19:54.80#ibcon#ireg 11 cls_cnt 2 2006.173.17:19:54.80#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.17:19:54.84#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.17:19:54.84#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.17:19:54.84#ibcon#enter wrdev, iclass 39, count 2 2006.173.17:19:54.84#ibcon#first serial, iclass 39, count 2 2006.173.17:19:54.84#ibcon#enter sib2, iclass 39, count 2 2006.173.17:19:54.84#ibcon#flushed, iclass 39, count 2 2006.173.17:19:54.84#ibcon#about to write, iclass 39, count 2 2006.173.17:19:54.84#ibcon#wrote, iclass 39, count 2 2006.173.17:19:54.84#ibcon#about to read 3, iclass 39, count 2 2006.173.17:19:54.86#ibcon#read 3, iclass 39, count 2 2006.173.17:19:54.86#ibcon#about to read 4, iclass 39, count 2 2006.173.17:19:54.86#ibcon#read 4, iclass 39, count 2 2006.173.17:19:54.86#ibcon#about to read 5, iclass 39, count 2 2006.173.17:19:54.86#ibcon#read 5, iclass 39, count 2 2006.173.17:19:54.86#ibcon#about to read 6, iclass 39, count 2 2006.173.17:19:54.86#ibcon#read 6, iclass 39, count 2 2006.173.17:19:54.86#ibcon#end of sib2, iclass 39, count 2 2006.173.17:19:54.86#ibcon#*mode == 0, iclass 39, count 2 2006.173.17:19:54.86#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.17:19:54.86#ibcon#[25=AT05-04\r\n] 2006.173.17:19:54.86#ibcon#*before write, iclass 39, count 2 2006.173.17:19:54.86#ibcon#enter sib2, iclass 39, count 2 2006.173.17:19:54.86#ibcon#flushed, iclass 39, count 2 2006.173.17:19:54.86#ibcon#about to write, iclass 39, count 2 2006.173.17:19:54.86#ibcon#wrote, iclass 39, count 2 2006.173.17:19:54.86#ibcon#about to read 3, iclass 39, count 2 2006.173.17:19:54.89#ibcon#read 3, iclass 39, count 2 2006.173.17:19:54.89#ibcon#about to read 4, iclass 39, count 2 2006.173.17:19:54.89#ibcon#read 4, iclass 39, count 2 2006.173.17:19:54.89#ibcon#about to read 5, iclass 39, count 2 2006.173.17:19:54.89#ibcon#read 5, iclass 39, count 2 2006.173.17:19:54.89#ibcon#about to read 6, iclass 39, count 2 2006.173.17:19:54.89#ibcon#read 6, iclass 39, count 2 2006.173.17:19:54.89#ibcon#end of sib2, iclass 39, count 2 2006.173.17:19:54.89#ibcon#*after write, iclass 39, count 2 2006.173.17:19:54.89#ibcon#*before return 0, iclass 39, count 2 2006.173.17:19:54.89#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.17:19:54.89#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.17:19:54.89#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.17:19:54.89#ibcon#ireg 7 cls_cnt 0 2006.173.17:19:54.89#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.17:19:55.01#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.17:19:55.02#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.17:19:55.02#ibcon#enter wrdev, iclass 39, count 0 2006.173.17:19:55.02#ibcon#first serial, iclass 39, count 0 2006.173.17:19:55.02#ibcon#enter sib2, iclass 39, count 0 2006.173.17:19:55.02#ibcon#flushed, iclass 39, count 0 2006.173.17:19:55.02#ibcon#about to write, iclass 39, count 0 2006.173.17:19:55.02#ibcon#wrote, iclass 39, count 0 2006.173.17:19:55.02#ibcon#about to read 3, iclass 39, count 0 2006.173.17:19:55.03#ibcon#read 3, iclass 39, count 0 2006.173.17:19:55.03#ibcon#about to read 4, iclass 39, count 0 2006.173.17:19:55.03#ibcon#read 4, iclass 39, count 0 2006.173.17:19:55.03#ibcon#about to read 5, iclass 39, count 0 2006.173.17:19:55.03#ibcon#read 5, iclass 39, count 0 2006.173.17:19:55.03#ibcon#about to read 6, iclass 39, count 0 2006.173.17:19:55.03#ibcon#read 6, iclass 39, count 0 2006.173.17:19:55.03#ibcon#end of sib2, iclass 39, count 0 2006.173.17:19:55.03#ibcon#*mode == 0, iclass 39, count 0 2006.173.17:19:55.03#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.17:19:55.03#ibcon#[25=USB\r\n] 2006.173.17:19:55.03#ibcon#*before write, iclass 39, count 0 2006.173.17:19:55.03#ibcon#enter sib2, iclass 39, count 0 2006.173.17:19:55.03#ibcon#flushed, iclass 39, count 0 2006.173.17:19:55.03#ibcon#about to write, iclass 39, count 0 2006.173.17:19:55.03#ibcon#wrote, iclass 39, count 0 2006.173.17:19:55.03#ibcon#about to read 3, iclass 39, count 0 2006.173.17:19:55.06#ibcon#read 3, iclass 39, count 0 2006.173.17:19:55.06#ibcon#about to read 4, iclass 39, count 0 2006.173.17:19:55.06#ibcon#read 4, iclass 39, count 0 2006.173.17:19:55.06#ibcon#about to read 5, iclass 39, count 0 2006.173.17:19:55.06#ibcon#read 5, iclass 39, count 0 2006.173.17:19:55.06#ibcon#about to read 6, iclass 39, count 0 2006.173.17:19:55.06#ibcon#read 6, iclass 39, count 0 2006.173.17:19:55.06#ibcon#end of sib2, iclass 39, count 0 2006.173.17:19:55.06#ibcon#*after write, iclass 39, count 0 2006.173.17:19:55.06#ibcon#*before return 0, iclass 39, count 0 2006.173.17:19:55.06#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.17:19:55.06#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.17:19:55.06#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.17:19:55.06#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.17:19:55.07$vck44/valo=6,814.99 2006.173.17:19:55.07#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.17:19:55.07#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.17:19:55.07#ibcon#ireg 17 cls_cnt 0 2006.173.17:19:55.07#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.17:19:55.07#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.17:19:55.07#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.17:19:55.07#ibcon#enter wrdev, iclass 3, count 0 2006.173.17:19:55.07#ibcon#first serial, iclass 3, count 0 2006.173.17:19:55.07#ibcon#enter sib2, iclass 3, count 0 2006.173.17:19:55.07#ibcon#flushed, iclass 3, count 0 2006.173.17:19:55.07#ibcon#about to write, iclass 3, count 0 2006.173.17:19:55.07#ibcon#wrote, iclass 3, count 0 2006.173.17:19:55.07#ibcon#about to read 3, iclass 3, count 0 2006.173.17:19:55.08#ibcon#read 3, iclass 3, count 0 2006.173.17:19:55.08#ibcon#about to read 4, iclass 3, count 0 2006.173.17:19:55.08#ibcon#read 4, iclass 3, count 0 2006.173.17:19:55.08#ibcon#about to read 5, iclass 3, count 0 2006.173.17:19:55.08#ibcon#read 5, iclass 3, count 0 2006.173.17:19:55.08#ibcon#about to read 6, iclass 3, count 0 2006.173.17:19:55.08#ibcon#read 6, iclass 3, count 0 2006.173.17:19:55.08#ibcon#end of sib2, iclass 3, count 0 2006.173.17:19:55.08#ibcon#*mode == 0, iclass 3, count 0 2006.173.17:19:55.08#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.17:19:55.08#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.17:19:55.08#ibcon#*before write, iclass 3, count 0 2006.173.17:19:55.08#ibcon#enter sib2, iclass 3, count 0 2006.173.17:19:55.08#ibcon#flushed, iclass 3, count 0 2006.173.17:19:55.08#ibcon#about to write, iclass 3, count 0 2006.173.17:19:55.08#ibcon#wrote, iclass 3, count 0 2006.173.17:19:55.08#ibcon#about to read 3, iclass 3, count 0 2006.173.17:19:55.12#ibcon#read 3, iclass 3, count 0 2006.173.17:19:55.12#ibcon#about to read 4, iclass 3, count 0 2006.173.17:19:55.12#ibcon#read 4, iclass 3, count 0 2006.173.17:19:55.12#ibcon#about to read 5, iclass 3, count 0 2006.173.17:19:55.12#ibcon#read 5, iclass 3, count 0 2006.173.17:19:55.12#ibcon#about to read 6, iclass 3, count 0 2006.173.17:19:55.12#ibcon#read 6, iclass 3, count 0 2006.173.17:19:55.12#ibcon#end of sib2, iclass 3, count 0 2006.173.17:19:55.12#ibcon#*after write, iclass 3, count 0 2006.173.17:19:55.12#ibcon#*before return 0, iclass 3, count 0 2006.173.17:19:55.12#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.17:19:55.12#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.17:19:55.12#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.17:19:55.12#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.17:19:55.13$vck44/va=6,3 2006.173.17:19:55.13#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.17:19:55.13#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.17:19:55.13#ibcon#ireg 11 cls_cnt 2 2006.173.17:19:55.13#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.17:19:55.17#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.17:19:55.17#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.17:19:55.17#ibcon#enter wrdev, iclass 5, count 2 2006.173.17:19:55.17#ibcon#first serial, iclass 5, count 2 2006.173.17:19:55.17#ibcon#enter sib2, iclass 5, count 2 2006.173.17:19:55.17#ibcon#flushed, iclass 5, count 2 2006.173.17:19:55.17#ibcon#about to write, iclass 5, count 2 2006.173.17:19:55.17#ibcon#wrote, iclass 5, count 2 2006.173.17:19:55.17#ibcon#about to read 3, iclass 5, count 2 2006.173.17:19:55.19#ibcon#read 3, iclass 5, count 2 2006.173.17:19:55.19#ibcon#about to read 4, iclass 5, count 2 2006.173.17:19:55.19#ibcon#read 4, iclass 5, count 2 2006.173.17:19:55.19#ibcon#about to read 5, iclass 5, count 2 2006.173.17:19:55.19#ibcon#read 5, iclass 5, count 2 2006.173.17:19:55.19#ibcon#about to read 6, iclass 5, count 2 2006.173.17:19:55.19#ibcon#read 6, iclass 5, count 2 2006.173.17:19:55.19#ibcon#end of sib2, iclass 5, count 2 2006.173.17:19:55.19#ibcon#*mode == 0, iclass 5, count 2 2006.173.17:19:55.19#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.17:19:55.19#ibcon#[25=AT06-03\r\n] 2006.173.17:19:55.19#ibcon#*before write, iclass 5, count 2 2006.173.17:19:55.19#ibcon#enter sib2, iclass 5, count 2 2006.173.17:19:55.19#ibcon#flushed, iclass 5, count 2 2006.173.17:19:55.19#ibcon#about to write, iclass 5, count 2 2006.173.17:19:55.19#ibcon#wrote, iclass 5, count 2 2006.173.17:19:55.19#ibcon#about to read 3, iclass 5, count 2 2006.173.17:19:55.22#ibcon#read 3, iclass 5, count 2 2006.173.17:19:55.22#ibcon#about to read 4, iclass 5, count 2 2006.173.17:19:55.22#ibcon#read 4, iclass 5, count 2 2006.173.17:19:55.22#ibcon#about to read 5, iclass 5, count 2 2006.173.17:19:55.22#ibcon#read 5, iclass 5, count 2 2006.173.17:19:55.22#ibcon#about to read 6, iclass 5, count 2 2006.173.17:19:55.22#ibcon#read 6, iclass 5, count 2 2006.173.17:19:55.22#ibcon#end of sib2, iclass 5, count 2 2006.173.17:19:55.22#ibcon#*after write, iclass 5, count 2 2006.173.17:19:55.22#ibcon#*before return 0, iclass 5, count 2 2006.173.17:19:55.22#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.17:19:55.22#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.17:19:55.22#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.17:19:55.22#ibcon#ireg 7 cls_cnt 0 2006.173.17:19:55.22#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.17:19:55.34#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.17:19:55.34#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.17:19:55.34#ibcon#enter wrdev, iclass 5, count 0 2006.173.17:19:55.34#ibcon#first serial, iclass 5, count 0 2006.173.17:19:55.34#ibcon#enter sib2, iclass 5, count 0 2006.173.17:19:55.34#ibcon#flushed, iclass 5, count 0 2006.173.17:19:55.34#ibcon#about to write, iclass 5, count 0 2006.173.17:19:55.34#ibcon#wrote, iclass 5, count 0 2006.173.17:19:55.34#ibcon#about to read 3, iclass 5, count 0 2006.173.17:19:55.36#ibcon#read 3, iclass 5, count 0 2006.173.17:19:55.36#ibcon#about to read 4, iclass 5, count 0 2006.173.17:19:55.36#ibcon#read 4, iclass 5, count 0 2006.173.17:19:55.36#ibcon#about to read 5, iclass 5, count 0 2006.173.17:19:55.36#ibcon#read 5, iclass 5, count 0 2006.173.17:19:55.36#ibcon#about to read 6, iclass 5, count 0 2006.173.17:19:55.36#ibcon#read 6, iclass 5, count 0 2006.173.17:19:55.36#ibcon#end of sib2, iclass 5, count 0 2006.173.17:19:55.36#ibcon#*mode == 0, iclass 5, count 0 2006.173.17:19:55.36#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.17:19:55.36#ibcon#[25=USB\r\n] 2006.173.17:19:55.36#ibcon#*before write, iclass 5, count 0 2006.173.17:19:55.36#ibcon#enter sib2, iclass 5, count 0 2006.173.17:19:55.36#ibcon#flushed, iclass 5, count 0 2006.173.17:19:55.36#ibcon#about to write, iclass 5, count 0 2006.173.17:19:55.36#ibcon#wrote, iclass 5, count 0 2006.173.17:19:55.36#ibcon#about to read 3, iclass 5, count 0 2006.173.17:19:55.39#ibcon#read 3, iclass 5, count 0 2006.173.17:19:55.39#ibcon#about to read 4, iclass 5, count 0 2006.173.17:19:55.39#ibcon#read 4, iclass 5, count 0 2006.173.17:19:55.39#ibcon#about to read 5, iclass 5, count 0 2006.173.17:19:55.39#ibcon#read 5, iclass 5, count 0 2006.173.17:19:55.39#ibcon#about to read 6, iclass 5, count 0 2006.173.17:19:55.39#ibcon#read 6, iclass 5, count 0 2006.173.17:19:55.39#ibcon#end of sib2, iclass 5, count 0 2006.173.17:19:55.39#ibcon#*after write, iclass 5, count 0 2006.173.17:19:55.39#ibcon#*before return 0, iclass 5, count 0 2006.173.17:19:55.39#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.17:19:55.39#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.17:19:55.39#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.17:19:55.39#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.17:19:55.40$vck44/valo=7,864.99 2006.173.17:19:55.40#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.17:19:55.40#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.17:19:55.40#ibcon#ireg 17 cls_cnt 0 2006.173.17:19:55.40#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.17:19:55.40#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.17:19:55.40#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.17:19:55.40#ibcon#enter wrdev, iclass 7, count 0 2006.173.17:19:55.40#ibcon#first serial, iclass 7, count 0 2006.173.17:19:55.40#ibcon#enter sib2, iclass 7, count 0 2006.173.17:19:55.40#ibcon#flushed, iclass 7, count 0 2006.173.17:19:55.40#ibcon#about to write, iclass 7, count 0 2006.173.17:19:55.40#ibcon#wrote, iclass 7, count 0 2006.173.17:19:55.40#ibcon#about to read 3, iclass 7, count 0 2006.173.17:19:55.41#ibcon#read 3, iclass 7, count 0 2006.173.17:19:55.41#ibcon#about to read 4, iclass 7, count 0 2006.173.17:19:55.41#ibcon#read 4, iclass 7, count 0 2006.173.17:19:55.41#ibcon#about to read 5, iclass 7, count 0 2006.173.17:19:55.41#ibcon#read 5, iclass 7, count 0 2006.173.17:19:55.41#ibcon#about to read 6, iclass 7, count 0 2006.173.17:19:55.41#ibcon#read 6, iclass 7, count 0 2006.173.17:19:55.41#ibcon#end of sib2, iclass 7, count 0 2006.173.17:19:55.41#ibcon#*mode == 0, iclass 7, count 0 2006.173.17:19:55.41#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.17:19:55.41#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.17:19:55.41#ibcon#*before write, iclass 7, count 0 2006.173.17:19:55.41#ibcon#enter sib2, iclass 7, count 0 2006.173.17:19:55.41#ibcon#flushed, iclass 7, count 0 2006.173.17:19:55.41#ibcon#about to write, iclass 7, count 0 2006.173.17:19:55.41#ibcon#wrote, iclass 7, count 0 2006.173.17:19:55.41#ibcon#about to read 3, iclass 7, count 0 2006.173.17:19:55.45#ibcon#read 3, iclass 7, count 0 2006.173.17:19:55.45#ibcon#about to read 4, iclass 7, count 0 2006.173.17:19:55.45#ibcon#read 4, iclass 7, count 0 2006.173.17:19:55.45#ibcon#about to read 5, iclass 7, count 0 2006.173.17:19:55.45#ibcon#read 5, iclass 7, count 0 2006.173.17:19:55.45#ibcon#about to read 6, iclass 7, count 0 2006.173.17:19:55.45#ibcon#read 6, iclass 7, count 0 2006.173.17:19:55.45#ibcon#end of sib2, iclass 7, count 0 2006.173.17:19:55.45#ibcon#*after write, iclass 7, count 0 2006.173.17:19:55.45#ibcon#*before return 0, iclass 7, count 0 2006.173.17:19:55.45#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.17:19:55.45#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.17:19:55.45#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.17:19:55.45#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.17:19:55.46$vck44/va=7,4 2006.173.17:19:55.46#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.17:19:55.46#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.17:19:55.46#ibcon#ireg 11 cls_cnt 2 2006.173.17:19:55.46#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.17:19:55.50#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.17:19:55.50#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.17:19:55.50#ibcon#enter wrdev, iclass 11, count 2 2006.173.17:19:55.50#ibcon#first serial, iclass 11, count 2 2006.173.17:19:55.50#ibcon#enter sib2, iclass 11, count 2 2006.173.17:19:55.50#ibcon#flushed, iclass 11, count 2 2006.173.17:19:55.50#ibcon#about to write, iclass 11, count 2 2006.173.17:19:55.50#ibcon#wrote, iclass 11, count 2 2006.173.17:19:55.50#ibcon#about to read 3, iclass 11, count 2 2006.173.17:19:55.52#ibcon#read 3, iclass 11, count 2 2006.173.17:19:55.52#ibcon#about to read 4, iclass 11, count 2 2006.173.17:19:55.52#ibcon#read 4, iclass 11, count 2 2006.173.17:19:55.52#ibcon#about to read 5, iclass 11, count 2 2006.173.17:19:55.52#ibcon#read 5, iclass 11, count 2 2006.173.17:19:55.52#ibcon#about to read 6, iclass 11, count 2 2006.173.17:19:55.52#ibcon#read 6, iclass 11, count 2 2006.173.17:19:55.52#ibcon#end of sib2, iclass 11, count 2 2006.173.17:19:55.52#ibcon#*mode == 0, iclass 11, count 2 2006.173.17:19:55.52#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.17:19:55.52#ibcon#[25=AT07-04\r\n] 2006.173.17:19:55.52#ibcon#*before write, iclass 11, count 2 2006.173.17:19:55.52#ibcon#enter sib2, iclass 11, count 2 2006.173.17:19:55.52#ibcon#flushed, iclass 11, count 2 2006.173.17:19:55.52#ibcon#about to write, iclass 11, count 2 2006.173.17:19:55.52#ibcon#wrote, iclass 11, count 2 2006.173.17:19:55.52#ibcon#about to read 3, iclass 11, count 2 2006.173.17:19:55.55#ibcon#read 3, iclass 11, count 2 2006.173.17:19:55.55#ibcon#about to read 4, iclass 11, count 2 2006.173.17:19:55.55#ibcon#read 4, iclass 11, count 2 2006.173.17:19:55.55#ibcon#about to read 5, iclass 11, count 2 2006.173.17:19:55.55#ibcon#read 5, iclass 11, count 2 2006.173.17:19:55.55#ibcon#about to read 6, iclass 11, count 2 2006.173.17:19:55.55#ibcon#read 6, iclass 11, count 2 2006.173.17:19:55.55#ibcon#end of sib2, iclass 11, count 2 2006.173.17:19:55.55#ibcon#*after write, iclass 11, count 2 2006.173.17:19:55.55#ibcon#*before return 0, iclass 11, count 2 2006.173.17:19:55.55#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.17:19:55.55#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.17:19:55.55#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.17:19:55.55#ibcon#ireg 7 cls_cnt 0 2006.173.17:19:55.55#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.17:19:55.67#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.17:19:55.67#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.17:19:55.67#ibcon#enter wrdev, iclass 11, count 0 2006.173.17:19:55.67#ibcon#first serial, iclass 11, count 0 2006.173.17:19:55.67#ibcon#enter sib2, iclass 11, count 0 2006.173.17:19:55.67#ibcon#flushed, iclass 11, count 0 2006.173.17:19:55.67#ibcon#about to write, iclass 11, count 0 2006.173.17:19:55.67#ibcon#wrote, iclass 11, count 0 2006.173.17:19:55.67#ibcon#about to read 3, iclass 11, count 0 2006.173.17:19:55.69#ibcon#read 3, iclass 11, count 0 2006.173.17:19:55.69#ibcon#about to read 4, iclass 11, count 0 2006.173.17:19:55.69#ibcon#read 4, iclass 11, count 0 2006.173.17:19:55.69#ibcon#about to read 5, iclass 11, count 0 2006.173.17:19:55.69#ibcon#read 5, iclass 11, count 0 2006.173.17:19:55.69#ibcon#about to read 6, iclass 11, count 0 2006.173.17:19:55.69#ibcon#read 6, iclass 11, count 0 2006.173.17:19:55.69#ibcon#end of sib2, iclass 11, count 0 2006.173.17:19:55.69#ibcon#*mode == 0, iclass 11, count 0 2006.173.17:19:55.69#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.17:19:55.69#ibcon#[25=USB\r\n] 2006.173.17:19:55.69#ibcon#*before write, iclass 11, count 0 2006.173.17:19:55.69#ibcon#enter sib2, iclass 11, count 0 2006.173.17:19:55.69#ibcon#flushed, iclass 11, count 0 2006.173.17:19:55.69#ibcon#about to write, iclass 11, count 0 2006.173.17:19:55.70#ibcon#wrote, iclass 11, count 0 2006.173.17:19:55.70#ibcon#about to read 3, iclass 11, count 0 2006.173.17:19:55.72#ibcon#read 3, iclass 11, count 0 2006.173.17:19:55.72#ibcon#about to read 4, iclass 11, count 0 2006.173.17:19:55.72#ibcon#read 4, iclass 11, count 0 2006.173.17:19:55.72#ibcon#about to read 5, iclass 11, count 0 2006.173.17:19:55.72#ibcon#read 5, iclass 11, count 0 2006.173.17:19:55.72#ibcon#about to read 6, iclass 11, count 0 2006.173.17:19:55.72#ibcon#read 6, iclass 11, count 0 2006.173.17:19:55.72#ibcon#end of sib2, iclass 11, count 0 2006.173.17:19:55.72#ibcon#*after write, iclass 11, count 0 2006.173.17:19:55.72#ibcon#*before return 0, iclass 11, count 0 2006.173.17:19:55.72#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.17:19:55.72#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.17:19:55.72#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.17:19:55.72#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.17:19:55.73$vck44/valo=8,884.99 2006.173.17:19:55.73#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.17:19:55.73#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.17:19:55.73#ibcon#ireg 17 cls_cnt 0 2006.173.17:19:55.73#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.17:19:55.73#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.17:19:55.73#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.17:19:55.73#ibcon#enter wrdev, iclass 13, count 0 2006.173.17:19:55.73#ibcon#first serial, iclass 13, count 0 2006.173.17:19:55.73#ibcon#enter sib2, iclass 13, count 0 2006.173.17:19:55.73#ibcon#flushed, iclass 13, count 0 2006.173.17:19:55.73#ibcon#about to write, iclass 13, count 0 2006.173.17:19:55.73#ibcon#wrote, iclass 13, count 0 2006.173.17:19:55.73#ibcon#about to read 3, iclass 13, count 0 2006.173.17:19:55.74#ibcon#read 3, iclass 13, count 0 2006.173.17:19:55.74#ibcon#about to read 4, iclass 13, count 0 2006.173.17:19:55.74#ibcon#read 4, iclass 13, count 0 2006.173.17:19:55.74#ibcon#about to read 5, iclass 13, count 0 2006.173.17:19:55.74#ibcon#read 5, iclass 13, count 0 2006.173.17:19:55.74#ibcon#about to read 6, iclass 13, count 0 2006.173.17:19:55.74#ibcon#read 6, iclass 13, count 0 2006.173.17:19:55.74#ibcon#end of sib2, iclass 13, count 0 2006.173.17:19:55.74#ibcon#*mode == 0, iclass 13, count 0 2006.173.17:19:55.74#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.17:19:55.74#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.17:19:55.74#ibcon#*before write, iclass 13, count 0 2006.173.17:19:55.74#ibcon#enter sib2, iclass 13, count 0 2006.173.17:19:55.74#ibcon#flushed, iclass 13, count 0 2006.173.17:19:55.74#ibcon#about to write, iclass 13, count 0 2006.173.17:19:55.74#ibcon#wrote, iclass 13, count 0 2006.173.17:19:55.75#ibcon#about to read 3, iclass 13, count 0 2006.173.17:19:55.78#ibcon#read 3, iclass 13, count 0 2006.173.17:19:55.78#ibcon#about to read 4, iclass 13, count 0 2006.173.17:19:55.78#ibcon#read 4, iclass 13, count 0 2006.173.17:19:55.78#ibcon#about to read 5, iclass 13, count 0 2006.173.17:19:55.78#ibcon#read 5, iclass 13, count 0 2006.173.17:19:55.78#ibcon#about to read 6, iclass 13, count 0 2006.173.17:19:55.78#ibcon#read 6, iclass 13, count 0 2006.173.17:19:55.78#ibcon#end of sib2, iclass 13, count 0 2006.173.17:19:55.78#ibcon#*after write, iclass 13, count 0 2006.173.17:19:55.78#ibcon#*before return 0, iclass 13, count 0 2006.173.17:19:55.78#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.17:19:55.78#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.17:19:55.78#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.17:19:55.78#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.17:19:55.79$vck44/va=8,4 2006.173.17:19:55.79#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.17:19:55.79#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.17:19:55.79#ibcon#ireg 11 cls_cnt 2 2006.173.17:19:55.79#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.17:19:55.83#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.17:19:55.83#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.17:19:55.83#ibcon#enter wrdev, iclass 15, count 2 2006.173.17:19:55.83#ibcon#first serial, iclass 15, count 2 2006.173.17:19:55.83#ibcon#enter sib2, iclass 15, count 2 2006.173.17:19:55.83#ibcon#flushed, iclass 15, count 2 2006.173.17:19:55.83#ibcon#about to write, iclass 15, count 2 2006.173.17:19:55.83#ibcon#wrote, iclass 15, count 2 2006.173.17:19:55.83#ibcon#about to read 3, iclass 15, count 2 2006.173.17:19:55.85#ibcon#read 3, iclass 15, count 2 2006.173.17:19:55.85#ibcon#about to read 4, iclass 15, count 2 2006.173.17:19:55.85#ibcon#read 4, iclass 15, count 2 2006.173.17:19:55.85#ibcon#about to read 5, iclass 15, count 2 2006.173.17:19:55.85#ibcon#read 5, iclass 15, count 2 2006.173.17:19:55.85#ibcon#about to read 6, iclass 15, count 2 2006.173.17:19:55.85#ibcon#read 6, iclass 15, count 2 2006.173.17:19:55.85#ibcon#end of sib2, iclass 15, count 2 2006.173.17:19:55.85#ibcon#*mode == 0, iclass 15, count 2 2006.173.17:19:55.85#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.17:19:55.85#ibcon#[25=AT08-04\r\n] 2006.173.17:19:55.85#ibcon#*before write, iclass 15, count 2 2006.173.17:19:55.85#ibcon#enter sib2, iclass 15, count 2 2006.173.17:19:55.85#ibcon#flushed, iclass 15, count 2 2006.173.17:19:55.85#ibcon#about to write, iclass 15, count 2 2006.173.17:19:55.85#ibcon#wrote, iclass 15, count 2 2006.173.17:19:55.85#ibcon#about to read 3, iclass 15, count 2 2006.173.17:19:55.88#ibcon#read 3, iclass 15, count 2 2006.173.17:19:55.88#ibcon#about to read 4, iclass 15, count 2 2006.173.17:19:55.88#ibcon#read 4, iclass 15, count 2 2006.173.17:19:55.88#ibcon#about to read 5, iclass 15, count 2 2006.173.17:19:55.88#ibcon#read 5, iclass 15, count 2 2006.173.17:19:55.88#ibcon#about to read 6, iclass 15, count 2 2006.173.17:19:55.88#ibcon#read 6, iclass 15, count 2 2006.173.17:19:55.88#ibcon#end of sib2, iclass 15, count 2 2006.173.17:19:55.88#ibcon#*after write, iclass 15, count 2 2006.173.17:19:55.88#ibcon#*before return 0, iclass 15, count 2 2006.173.17:19:55.88#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.17:19:55.88#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.17:19:55.88#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.17:19:55.88#ibcon#ireg 7 cls_cnt 0 2006.173.17:19:55.88#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.17:19:56.00#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.17:19:56.00#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.17:19:56.00#ibcon#enter wrdev, iclass 15, count 0 2006.173.17:19:56.00#ibcon#first serial, iclass 15, count 0 2006.173.17:19:56.00#ibcon#enter sib2, iclass 15, count 0 2006.173.17:19:56.00#ibcon#flushed, iclass 15, count 0 2006.173.17:19:56.00#ibcon#about to write, iclass 15, count 0 2006.173.17:19:56.00#ibcon#wrote, iclass 15, count 0 2006.173.17:19:56.00#ibcon#about to read 3, iclass 15, count 0 2006.173.17:19:56.02#ibcon#read 3, iclass 15, count 0 2006.173.17:19:56.02#ibcon#about to read 4, iclass 15, count 0 2006.173.17:19:56.02#ibcon#read 4, iclass 15, count 0 2006.173.17:19:56.02#ibcon#about to read 5, iclass 15, count 0 2006.173.17:19:56.02#ibcon#read 5, iclass 15, count 0 2006.173.17:19:56.02#ibcon#about to read 6, iclass 15, count 0 2006.173.17:19:56.02#ibcon#read 6, iclass 15, count 0 2006.173.17:19:56.02#ibcon#end of sib2, iclass 15, count 0 2006.173.17:19:56.02#ibcon#*mode == 0, iclass 15, count 0 2006.173.17:19:56.02#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.17:19:56.02#ibcon#[25=USB\r\n] 2006.173.17:19:56.02#ibcon#*before write, iclass 15, count 0 2006.173.17:19:56.02#ibcon#enter sib2, iclass 15, count 0 2006.173.17:19:56.02#ibcon#flushed, iclass 15, count 0 2006.173.17:19:56.02#ibcon#about to write, iclass 15, count 0 2006.173.17:19:56.02#ibcon#wrote, iclass 15, count 0 2006.173.17:19:56.02#ibcon#about to read 3, iclass 15, count 0 2006.173.17:19:56.05#ibcon#read 3, iclass 15, count 0 2006.173.17:19:56.05#ibcon#about to read 4, iclass 15, count 0 2006.173.17:19:56.05#ibcon#read 4, iclass 15, count 0 2006.173.17:19:56.05#ibcon#about to read 5, iclass 15, count 0 2006.173.17:19:56.05#ibcon#read 5, iclass 15, count 0 2006.173.17:19:56.05#ibcon#about to read 6, iclass 15, count 0 2006.173.17:19:56.05#ibcon#read 6, iclass 15, count 0 2006.173.17:19:56.05#ibcon#end of sib2, iclass 15, count 0 2006.173.17:19:56.05#ibcon#*after write, iclass 15, count 0 2006.173.17:19:56.05#ibcon#*before return 0, iclass 15, count 0 2006.173.17:19:56.05#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.17:19:56.05#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.17:19:56.05#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.17:19:56.05#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.17:19:56.06$vck44/vblo=1,629.99 2006.173.17:19:56.06#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.17:19:56.06#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.17:19:56.06#ibcon#ireg 17 cls_cnt 0 2006.173.17:19:56.06#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.17:19:56.06#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.17:19:56.06#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.17:19:56.06#ibcon#enter wrdev, iclass 17, count 0 2006.173.17:19:56.06#ibcon#first serial, iclass 17, count 0 2006.173.17:19:56.06#ibcon#enter sib2, iclass 17, count 0 2006.173.17:19:56.06#ibcon#flushed, iclass 17, count 0 2006.173.17:19:56.06#ibcon#about to write, iclass 17, count 0 2006.173.17:19:56.06#ibcon#wrote, iclass 17, count 0 2006.173.17:19:56.06#ibcon#about to read 3, iclass 17, count 0 2006.173.17:19:56.07#ibcon#read 3, iclass 17, count 0 2006.173.17:19:56.07#ibcon#about to read 4, iclass 17, count 0 2006.173.17:19:56.07#ibcon#read 4, iclass 17, count 0 2006.173.17:19:56.07#ibcon#about to read 5, iclass 17, count 0 2006.173.17:19:56.07#ibcon#read 5, iclass 17, count 0 2006.173.17:19:56.07#ibcon#about to read 6, iclass 17, count 0 2006.173.17:19:56.07#ibcon#read 6, iclass 17, count 0 2006.173.17:19:56.07#ibcon#end of sib2, iclass 17, count 0 2006.173.17:19:56.07#ibcon#*mode == 0, iclass 17, count 0 2006.173.17:19:56.07#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.17:19:56.07#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.17:19:56.07#ibcon#*before write, iclass 17, count 0 2006.173.17:19:56.07#ibcon#enter sib2, iclass 17, count 0 2006.173.17:19:56.07#ibcon#flushed, iclass 17, count 0 2006.173.17:19:56.07#ibcon#about to write, iclass 17, count 0 2006.173.17:19:56.07#ibcon#wrote, iclass 17, count 0 2006.173.17:19:56.07#ibcon#about to read 3, iclass 17, count 0 2006.173.17:19:56.11#ibcon#read 3, iclass 17, count 0 2006.173.17:19:56.11#ibcon#about to read 4, iclass 17, count 0 2006.173.17:19:56.11#ibcon#read 4, iclass 17, count 0 2006.173.17:19:56.11#ibcon#about to read 5, iclass 17, count 0 2006.173.17:19:56.11#ibcon#read 5, iclass 17, count 0 2006.173.17:19:56.11#ibcon#about to read 6, iclass 17, count 0 2006.173.17:19:56.12#ibcon#read 6, iclass 17, count 0 2006.173.17:19:56.12#ibcon#end of sib2, iclass 17, count 0 2006.173.17:19:56.12#ibcon#*after write, iclass 17, count 0 2006.173.17:19:56.12#ibcon#*before return 0, iclass 17, count 0 2006.173.17:19:56.12#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.17:19:56.12#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.17:19:56.12#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.17:19:56.12#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.17:19:56.12$vck44/vb=1,4 2006.173.17:19:56.12#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.17:19:56.12#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.17:19:56.12#ibcon#ireg 11 cls_cnt 2 2006.173.17:19:56.12#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.17:19:56.12#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.17:19:56.12#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.17:19:56.12#ibcon#enter wrdev, iclass 19, count 2 2006.173.17:19:56.12#ibcon#first serial, iclass 19, count 2 2006.173.17:19:56.12#ibcon#enter sib2, iclass 19, count 2 2006.173.17:19:56.12#ibcon#flushed, iclass 19, count 2 2006.173.17:19:56.12#ibcon#about to write, iclass 19, count 2 2006.173.17:19:56.12#ibcon#wrote, iclass 19, count 2 2006.173.17:19:56.12#ibcon#about to read 3, iclass 19, count 2 2006.173.17:19:56.13#ibcon#read 3, iclass 19, count 2 2006.173.17:19:56.13#ibcon#about to read 4, iclass 19, count 2 2006.173.17:19:56.13#ibcon#read 4, iclass 19, count 2 2006.173.17:19:56.13#ibcon#about to read 5, iclass 19, count 2 2006.173.17:19:56.13#ibcon#read 5, iclass 19, count 2 2006.173.17:19:56.13#ibcon#about to read 6, iclass 19, count 2 2006.173.17:19:56.13#ibcon#read 6, iclass 19, count 2 2006.173.17:19:56.13#ibcon#end of sib2, iclass 19, count 2 2006.173.17:19:56.13#ibcon#*mode == 0, iclass 19, count 2 2006.173.17:19:56.13#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.17:19:56.13#ibcon#[27=AT01-04\r\n] 2006.173.17:19:56.13#ibcon#*before write, iclass 19, count 2 2006.173.17:19:56.13#ibcon#enter sib2, iclass 19, count 2 2006.173.17:19:56.13#ibcon#flushed, iclass 19, count 2 2006.173.17:19:56.13#ibcon#about to write, iclass 19, count 2 2006.173.17:19:56.13#ibcon#wrote, iclass 19, count 2 2006.173.17:19:56.13#ibcon#about to read 3, iclass 19, count 2 2006.173.17:19:56.16#ibcon#read 3, iclass 19, count 2 2006.173.17:19:56.16#ibcon#about to read 4, iclass 19, count 2 2006.173.17:19:56.16#ibcon#read 4, iclass 19, count 2 2006.173.17:19:56.16#ibcon#about to read 5, iclass 19, count 2 2006.173.17:19:56.16#ibcon#read 5, iclass 19, count 2 2006.173.17:19:56.16#ibcon#about to read 6, iclass 19, count 2 2006.173.17:19:56.16#ibcon#read 6, iclass 19, count 2 2006.173.17:19:56.16#ibcon#end of sib2, iclass 19, count 2 2006.173.17:19:56.16#ibcon#*after write, iclass 19, count 2 2006.173.17:19:56.16#ibcon#*before return 0, iclass 19, count 2 2006.173.17:19:56.16#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.17:19:56.16#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.17:19:56.16#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.17:19:56.16#ibcon#ireg 7 cls_cnt 0 2006.173.17:19:56.16#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.17:19:56.28#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.17:19:56.28#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.17:19:56.28#ibcon#enter wrdev, iclass 19, count 0 2006.173.17:19:56.28#ibcon#first serial, iclass 19, count 0 2006.173.17:19:56.28#ibcon#enter sib2, iclass 19, count 0 2006.173.17:19:56.28#ibcon#flushed, iclass 19, count 0 2006.173.17:19:56.28#ibcon#about to write, iclass 19, count 0 2006.173.17:19:56.28#ibcon#wrote, iclass 19, count 0 2006.173.17:19:56.28#ibcon#about to read 3, iclass 19, count 0 2006.173.17:19:56.30#ibcon#read 3, iclass 19, count 0 2006.173.17:19:56.30#ibcon#about to read 4, iclass 19, count 0 2006.173.17:19:56.30#ibcon#read 4, iclass 19, count 0 2006.173.17:19:56.30#ibcon#about to read 5, iclass 19, count 0 2006.173.17:19:56.30#ibcon#read 5, iclass 19, count 0 2006.173.17:19:56.30#ibcon#about to read 6, iclass 19, count 0 2006.173.17:19:56.30#ibcon#read 6, iclass 19, count 0 2006.173.17:19:56.30#ibcon#end of sib2, iclass 19, count 0 2006.173.17:19:56.30#ibcon#*mode == 0, iclass 19, count 0 2006.173.17:19:56.30#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.17:19:56.30#ibcon#[27=USB\r\n] 2006.173.17:19:56.30#ibcon#*before write, iclass 19, count 0 2006.173.17:19:56.30#ibcon#enter sib2, iclass 19, count 0 2006.173.17:19:56.30#ibcon#flushed, iclass 19, count 0 2006.173.17:19:56.30#ibcon#about to write, iclass 19, count 0 2006.173.17:19:56.30#ibcon#wrote, iclass 19, count 0 2006.173.17:19:56.30#ibcon#about to read 3, iclass 19, count 0 2006.173.17:19:56.33#ibcon#read 3, iclass 19, count 0 2006.173.17:19:56.33#ibcon#about to read 4, iclass 19, count 0 2006.173.17:19:56.33#ibcon#read 4, iclass 19, count 0 2006.173.17:19:56.33#ibcon#about to read 5, iclass 19, count 0 2006.173.17:19:56.33#ibcon#read 5, iclass 19, count 0 2006.173.17:19:56.33#ibcon#about to read 6, iclass 19, count 0 2006.173.17:19:56.33#ibcon#read 6, iclass 19, count 0 2006.173.17:19:56.33#ibcon#end of sib2, iclass 19, count 0 2006.173.17:19:56.33#ibcon#*after write, iclass 19, count 0 2006.173.17:19:56.33#ibcon#*before return 0, iclass 19, count 0 2006.173.17:19:56.33#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.17:19:56.33#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.17:19:56.33#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.17:19:56.33#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.17:19:56.34$vck44/vblo=2,634.99 2006.173.17:19:56.34#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.17:19:56.34#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.17:19:56.34#ibcon#ireg 17 cls_cnt 0 2006.173.17:19:56.34#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.17:19:56.34#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.17:19:56.34#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.17:19:56.34#ibcon#enter wrdev, iclass 21, count 0 2006.173.17:19:56.34#ibcon#first serial, iclass 21, count 0 2006.173.17:19:56.34#ibcon#enter sib2, iclass 21, count 0 2006.173.17:19:56.34#ibcon#flushed, iclass 21, count 0 2006.173.17:19:56.34#ibcon#about to write, iclass 21, count 0 2006.173.17:19:56.34#ibcon#wrote, iclass 21, count 0 2006.173.17:19:56.34#ibcon#about to read 3, iclass 21, count 0 2006.173.17:19:56.35#ibcon#read 3, iclass 21, count 0 2006.173.17:19:56.35#ibcon#about to read 4, iclass 21, count 0 2006.173.17:19:56.35#ibcon#read 4, iclass 21, count 0 2006.173.17:19:56.35#ibcon#about to read 5, iclass 21, count 0 2006.173.17:19:56.35#ibcon#read 5, iclass 21, count 0 2006.173.17:19:56.35#ibcon#about to read 6, iclass 21, count 0 2006.173.17:19:56.35#ibcon#read 6, iclass 21, count 0 2006.173.17:19:56.35#ibcon#end of sib2, iclass 21, count 0 2006.173.17:19:56.35#ibcon#*mode == 0, iclass 21, count 0 2006.173.17:19:56.35#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.17:19:56.35#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.17:19:56.35#ibcon#*before write, iclass 21, count 0 2006.173.17:19:56.35#ibcon#enter sib2, iclass 21, count 0 2006.173.17:19:56.35#ibcon#flushed, iclass 21, count 0 2006.173.17:19:56.35#ibcon#about to write, iclass 21, count 0 2006.173.17:19:56.35#ibcon#wrote, iclass 21, count 0 2006.173.17:19:56.35#ibcon#about to read 3, iclass 21, count 0 2006.173.17:19:56.39#ibcon#read 3, iclass 21, count 0 2006.173.17:19:56.39#ibcon#about to read 4, iclass 21, count 0 2006.173.17:19:56.39#ibcon#read 4, iclass 21, count 0 2006.173.17:19:56.39#ibcon#about to read 5, iclass 21, count 0 2006.173.17:19:56.39#ibcon#read 5, iclass 21, count 0 2006.173.17:19:56.39#ibcon#about to read 6, iclass 21, count 0 2006.173.17:19:56.39#ibcon#read 6, iclass 21, count 0 2006.173.17:19:56.39#ibcon#end of sib2, iclass 21, count 0 2006.173.17:19:56.39#ibcon#*after write, iclass 21, count 0 2006.173.17:19:56.39#ibcon#*before return 0, iclass 21, count 0 2006.173.17:19:56.39#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.17:19:56.39#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.17:19:56.39#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.17:19:56.40#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.17:19:56.40$vck44/vb=2,4 2006.173.17:19:56.40#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.17:19:56.40#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.17:19:56.40#ibcon#ireg 11 cls_cnt 2 2006.173.17:19:56.40#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.17:19:56.44#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.17:19:56.44#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.17:19:56.44#ibcon#enter wrdev, iclass 23, count 2 2006.173.17:19:56.44#ibcon#first serial, iclass 23, count 2 2006.173.17:19:56.44#ibcon#enter sib2, iclass 23, count 2 2006.173.17:19:56.44#ibcon#flushed, iclass 23, count 2 2006.173.17:19:56.44#ibcon#about to write, iclass 23, count 2 2006.173.17:19:56.44#ibcon#wrote, iclass 23, count 2 2006.173.17:19:56.44#ibcon#about to read 3, iclass 23, count 2 2006.173.17:19:56.46#ibcon#read 3, iclass 23, count 2 2006.173.17:19:56.46#ibcon#about to read 4, iclass 23, count 2 2006.173.17:19:56.46#ibcon#read 4, iclass 23, count 2 2006.173.17:19:56.46#ibcon#about to read 5, iclass 23, count 2 2006.173.17:19:56.46#ibcon#read 5, iclass 23, count 2 2006.173.17:19:56.46#ibcon#about to read 6, iclass 23, count 2 2006.173.17:19:56.46#ibcon#read 6, iclass 23, count 2 2006.173.17:19:56.46#ibcon#end of sib2, iclass 23, count 2 2006.173.17:19:56.46#ibcon#*mode == 0, iclass 23, count 2 2006.173.17:19:56.46#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.17:19:56.46#ibcon#[27=AT02-04\r\n] 2006.173.17:19:56.46#ibcon#*before write, iclass 23, count 2 2006.173.17:19:56.46#ibcon#enter sib2, iclass 23, count 2 2006.173.17:19:56.46#ibcon#flushed, iclass 23, count 2 2006.173.17:19:56.46#ibcon#about to write, iclass 23, count 2 2006.173.17:19:56.46#ibcon#wrote, iclass 23, count 2 2006.173.17:19:56.46#ibcon#about to read 3, iclass 23, count 2 2006.173.17:19:56.49#ibcon#read 3, iclass 23, count 2 2006.173.17:19:56.49#ibcon#about to read 4, iclass 23, count 2 2006.173.17:19:56.49#ibcon#read 4, iclass 23, count 2 2006.173.17:19:56.49#ibcon#about to read 5, iclass 23, count 2 2006.173.17:19:56.49#ibcon#read 5, iclass 23, count 2 2006.173.17:19:56.49#ibcon#about to read 6, iclass 23, count 2 2006.173.17:19:56.49#ibcon#read 6, iclass 23, count 2 2006.173.17:19:56.49#ibcon#end of sib2, iclass 23, count 2 2006.173.17:19:56.49#ibcon#*after write, iclass 23, count 2 2006.173.17:19:56.49#ibcon#*before return 0, iclass 23, count 2 2006.173.17:19:56.49#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.17:19:56.49#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.17:19:56.49#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.17:19:56.49#ibcon#ireg 7 cls_cnt 0 2006.173.17:19:56.49#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.17:19:56.61#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.17:19:56.61#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.17:19:56.61#ibcon#enter wrdev, iclass 23, count 0 2006.173.17:19:56.61#ibcon#first serial, iclass 23, count 0 2006.173.17:19:56.61#ibcon#enter sib2, iclass 23, count 0 2006.173.17:19:56.61#ibcon#flushed, iclass 23, count 0 2006.173.17:19:56.61#ibcon#about to write, iclass 23, count 0 2006.173.17:19:56.61#ibcon#wrote, iclass 23, count 0 2006.173.17:19:56.61#ibcon#about to read 3, iclass 23, count 0 2006.173.17:19:56.63#ibcon#read 3, iclass 23, count 0 2006.173.17:19:56.63#ibcon#about to read 4, iclass 23, count 0 2006.173.17:19:56.63#ibcon#read 4, iclass 23, count 0 2006.173.17:19:56.63#ibcon#about to read 5, iclass 23, count 0 2006.173.17:19:56.63#ibcon#read 5, iclass 23, count 0 2006.173.17:19:56.63#ibcon#about to read 6, iclass 23, count 0 2006.173.17:19:56.63#ibcon#read 6, iclass 23, count 0 2006.173.17:19:56.63#ibcon#end of sib2, iclass 23, count 0 2006.173.17:19:56.63#ibcon#*mode == 0, iclass 23, count 0 2006.173.17:19:56.63#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.17:19:56.63#ibcon#[27=USB\r\n] 2006.173.17:19:56.63#ibcon#*before write, iclass 23, count 0 2006.173.17:19:56.63#ibcon#enter sib2, iclass 23, count 0 2006.173.17:19:56.63#ibcon#flushed, iclass 23, count 0 2006.173.17:19:56.63#ibcon#about to write, iclass 23, count 0 2006.173.17:19:56.63#ibcon#wrote, iclass 23, count 0 2006.173.17:19:56.63#ibcon#about to read 3, iclass 23, count 0 2006.173.17:19:56.66#ibcon#read 3, iclass 23, count 0 2006.173.17:19:56.66#ibcon#about to read 4, iclass 23, count 0 2006.173.17:19:56.66#ibcon#read 4, iclass 23, count 0 2006.173.17:19:56.66#ibcon#about to read 5, iclass 23, count 0 2006.173.17:19:56.66#ibcon#read 5, iclass 23, count 0 2006.173.17:19:56.66#ibcon#about to read 6, iclass 23, count 0 2006.173.17:19:56.66#ibcon#read 6, iclass 23, count 0 2006.173.17:19:56.66#ibcon#end of sib2, iclass 23, count 0 2006.173.17:19:56.66#ibcon#*after write, iclass 23, count 0 2006.173.17:19:56.66#ibcon#*before return 0, iclass 23, count 0 2006.173.17:19:56.66#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.17:19:56.66#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.17:19:56.66#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.17:19:56.66#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.17:19:56.67$vck44/vblo=3,649.99 2006.173.17:19:56.67#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.17:19:56.67#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.17:19:56.67#ibcon#ireg 17 cls_cnt 0 2006.173.17:19:56.67#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.17:19:56.67#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.17:19:56.67#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.17:19:56.67#ibcon#enter wrdev, iclass 25, count 0 2006.173.17:19:56.67#ibcon#first serial, iclass 25, count 0 2006.173.17:19:56.67#ibcon#enter sib2, iclass 25, count 0 2006.173.17:19:56.67#ibcon#flushed, iclass 25, count 0 2006.173.17:19:56.67#ibcon#about to write, iclass 25, count 0 2006.173.17:19:56.67#ibcon#wrote, iclass 25, count 0 2006.173.17:19:56.67#ibcon#about to read 3, iclass 25, count 0 2006.173.17:19:56.68#ibcon#read 3, iclass 25, count 0 2006.173.17:19:56.68#ibcon#about to read 4, iclass 25, count 0 2006.173.17:19:56.68#ibcon#read 4, iclass 25, count 0 2006.173.17:19:56.68#ibcon#about to read 5, iclass 25, count 0 2006.173.17:19:56.68#ibcon#read 5, iclass 25, count 0 2006.173.17:19:56.68#ibcon#about to read 6, iclass 25, count 0 2006.173.17:19:56.68#ibcon#read 6, iclass 25, count 0 2006.173.17:19:56.68#ibcon#end of sib2, iclass 25, count 0 2006.173.17:19:56.68#ibcon#*mode == 0, iclass 25, count 0 2006.173.17:19:56.68#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.17:19:56.68#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.17:19:56.68#ibcon#*before write, iclass 25, count 0 2006.173.17:19:56.68#ibcon#enter sib2, iclass 25, count 0 2006.173.17:19:56.68#ibcon#flushed, iclass 25, count 0 2006.173.17:19:56.68#ibcon#about to write, iclass 25, count 0 2006.173.17:19:56.68#ibcon#wrote, iclass 25, count 0 2006.173.17:19:56.68#ibcon#about to read 3, iclass 25, count 0 2006.173.17:19:56.72#ibcon#read 3, iclass 25, count 0 2006.173.17:19:56.72#ibcon#about to read 4, iclass 25, count 0 2006.173.17:19:56.72#ibcon#read 4, iclass 25, count 0 2006.173.17:19:56.72#ibcon#about to read 5, iclass 25, count 0 2006.173.17:19:56.72#ibcon#read 5, iclass 25, count 0 2006.173.17:19:56.72#ibcon#about to read 6, iclass 25, count 0 2006.173.17:19:56.72#ibcon#read 6, iclass 25, count 0 2006.173.17:19:56.72#ibcon#end of sib2, iclass 25, count 0 2006.173.17:19:56.72#ibcon#*after write, iclass 25, count 0 2006.173.17:19:56.72#ibcon#*before return 0, iclass 25, count 0 2006.173.17:19:56.72#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.17:19:56.72#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.17:19:56.72#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.17:19:56.72#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.17:19:56.73$vck44/vb=3,4 2006.173.17:19:56.73#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.17:19:56.73#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.17:19:56.73#ibcon#ireg 11 cls_cnt 2 2006.173.17:19:56.73#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.17:19:56.77#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.17:19:56.77#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.17:19:56.77#ibcon#enter wrdev, iclass 27, count 2 2006.173.17:19:56.77#ibcon#first serial, iclass 27, count 2 2006.173.17:19:56.77#ibcon#enter sib2, iclass 27, count 2 2006.173.17:19:56.77#ibcon#flushed, iclass 27, count 2 2006.173.17:19:56.77#ibcon#about to write, iclass 27, count 2 2006.173.17:19:56.77#ibcon#wrote, iclass 27, count 2 2006.173.17:19:56.77#ibcon#about to read 3, iclass 27, count 2 2006.173.17:19:56.79#ibcon#read 3, iclass 27, count 2 2006.173.17:19:56.79#ibcon#about to read 4, iclass 27, count 2 2006.173.17:19:56.79#ibcon#read 4, iclass 27, count 2 2006.173.17:19:56.79#ibcon#about to read 5, iclass 27, count 2 2006.173.17:19:56.79#ibcon#read 5, iclass 27, count 2 2006.173.17:19:56.79#ibcon#about to read 6, iclass 27, count 2 2006.173.17:19:56.79#ibcon#read 6, iclass 27, count 2 2006.173.17:19:56.79#ibcon#end of sib2, iclass 27, count 2 2006.173.17:19:56.79#ibcon#*mode == 0, iclass 27, count 2 2006.173.17:19:56.79#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.17:19:56.79#ibcon#[27=AT03-04\r\n] 2006.173.17:19:56.79#ibcon#*before write, iclass 27, count 2 2006.173.17:19:56.79#ibcon#enter sib2, iclass 27, count 2 2006.173.17:19:56.79#ibcon#flushed, iclass 27, count 2 2006.173.17:19:56.79#ibcon#about to write, iclass 27, count 2 2006.173.17:19:56.79#ibcon#wrote, iclass 27, count 2 2006.173.17:19:56.80#ibcon#about to read 3, iclass 27, count 2 2006.173.17:19:56.82#ibcon#read 3, iclass 27, count 2 2006.173.17:19:56.82#ibcon#about to read 4, iclass 27, count 2 2006.173.17:19:56.82#ibcon#read 4, iclass 27, count 2 2006.173.17:19:56.82#ibcon#about to read 5, iclass 27, count 2 2006.173.17:19:56.82#ibcon#read 5, iclass 27, count 2 2006.173.17:19:56.82#ibcon#about to read 6, iclass 27, count 2 2006.173.17:19:56.82#ibcon#read 6, iclass 27, count 2 2006.173.17:19:56.82#ibcon#end of sib2, iclass 27, count 2 2006.173.17:19:56.82#ibcon#*after write, iclass 27, count 2 2006.173.17:19:56.82#ibcon#*before return 0, iclass 27, count 2 2006.173.17:19:56.82#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.17:19:56.82#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.17:19:56.82#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.17:19:56.82#ibcon#ireg 7 cls_cnt 0 2006.173.17:19:56.82#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.17:19:56.94#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.17:19:56.94#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.17:19:56.94#ibcon#enter wrdev, iclass 27, count 0 2006.173.17:19:56.94#ibcon#first serial, iclass 27, count 0 2006.173.17:19:56.94#ibcon#enter sib2, iclass 27, count 0 2006.173.17:19:56.94#ibcon#flushed, iclass 27, count 0 2006.173.17:19:56.94#ibcon#about to write, iclass 27, count 0 2006.173.17:19:56.94#ibcon#wrote, iclass 27, count 0 2006.173.17:19:56.94#ibcon#about to read 3, iclass 27, count 0 2006.173.17:19:56.96#ibcon#read 3, iclass 27, count 0 2006.173.17:19:56.96#ibcon#about to read 4, iclass 27, count 0 2006.173.17:19:56.96#ibcon#read 4, iclass 27, count 0 2006.173.17:19:56.96#ibcon#about to read 5, iclass 27, count 0 2006.173.17:19:56.96#ibcon#read 5, iclass 27, count 0 2006.173.17:19:56.96#ibcon#about to read 6, iclass 27, count 0 2006.173.17:19:56.96#ibcon#read 6, iclass 27, count 0 2006.173.17:19:56.96#ibcon#end of sib2, iclass 27, count 0 2006.173.17:19:56.96#ibcon#*mode == 0, iclass 27, count 0 2006.173.17:19:56.96#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.17:19:56.96#ibcon#[27=USB\r\n] 2006.173.17:19:56.96#ibcon#*before write, iclass 27, count 0 2006.173.17:19:56.96#ibcon#enter sib2, iclass 27, count 0 2006.173.17:19:56.96#ibcon#flushed, iclass 27, count 0 2006.173.17:19:56.96#ibcon#about to write, iclass 27, count 0 2006.173.17:19:56.96#ibcon#wrote, iclass 27, count 0 2006.173.17:19:56.96#ibcon#about to read 3, iclass 27, count 0 2006.173.17:19:56.99#ibcon#read 3, iclass 27, count 0 2006.173.17:19:56.99#ibcon#about to read 4, iclass 27, count 0 2006.173.17:19:56.99#ibcon#read 4, iclass 27, count 0 2006.173.17:19:56.99#ibcon#about to read 5, iclass 27, count 0 2006.173.17:19:56.99#ibcon#read 5, iclass 27, count 0 2006.173.17:19:56.99#ibcon#about to read 6, iclass 27, count 0 2006.173.17:19:56.99#ibcon#read 6, iclass 27, count 0 2006.173.17:19:56.99#ibcon#end of sib2, iclass 27, count 0 2006.173.17:19:56.99#ibcon#*after write, iclass 27, count 0 2006.173.17:19:56.99#ibcon#*before return 0, iclass 27, count 0 2006.173.17:19:56.99#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.17:19:56.99#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.17:19:56.99#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.17:19:56.99#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.17:19:57.00$vck44/vblo=4,679.99 2006.173.17:19:57.00#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.17:19:57.00#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.17:19:57.00#ibcon#ireg 17 cls_cnt 0 2006.173.17:19:57.00#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.17:19:57.00#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.17:19:57.00#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.17:19:57.00#ibcon#enter wrdev, iclass 29, count 0 2006.173.17:19:57.00#ibcon#first serial, iclass 29, count 0 2006.173.17:19:57.00#ibcon#enter sib2, iclass 29, count 0 2006.173.17:19:57.00#ibcon#flushed, iclass 29, count 0 2006.173.17:19:57.00#ibcon#about to write, iclass 29, count 0 2006.173.17:19:57.00#ibcon#wrote, iclass 29, count 0 2006.173.17:19:57.00#ibcon#about to read 3, iclass 29, count 0 2006.173.17:19:57.01#ibcon#read 3, iclass 29, count 0 2006.173.17:19:57.01#ibcon#about to read 4, iclass 29, count 0 2006.173.17:19:57.01#ibcon#read 4, iclass 29, count 0 2006.173.17:19:57.01#ibcon#about to read 5, iclass 29, count 0 2006.173.17:19:57.01#ibcon#read 5, iclass 29, count 0 2006.173.17:19:57.01#ibcon#about to read 6, iclass 29, count 0 2006.173.17:19:57.01#ibcon#read 6, iclass 29, count 0 2006.173.17:19:57.01#ibcon#end of sib2, iclass 29, count 0 2006.173.17:19:57.01#ibcon#*mode == 0, iclass 29, count 0 2006.173.17:19:57.01#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.17:19:57.01#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.17:19:57.01#ibcon#*before write, iclass 29, count 0 2006.173.17:19:57.01#ibcon#enter sib2, iclass 29, count 0 2006.173.17:19:57.01#ibcon#flushed, iclass 29, count 0 2006.173.17:19:57.01#ibcon#about to write, iclass 29, count 0 2006.173.17:19:57.01#ibcon#wrote, iclass 29, count 0 2006.173.17:19:57.01#ibcon#about to read 3, iclass 29, count 0 2006.173.17:19:57.05#ibcon#read 3, iclass 29, count 0 2006.173.17:19:57.05#ibcon#about to read 4, iclass 29, count 0 2006.173.17:19:57.05#ibcon#read 4, iclass 29, count 0 2006.173.17:19:57.05#ibcon#about to read 5, iclass 29, count 0 2006.173.17:19:57.05#ibcon#read 5, iclass 29, count 0 2006.173.17:19:57.05#ibcon#about to read 6, iclass 29, count 0 2006.173.17:19:57.05#ibcon#read 6, iclass 29, count 0 2006.173.17:19:57.05#ibcon#end of sib2, iclass 29, count 0 2006.173.17:19:57.05#ibcon#*after write, iclass 29, count 0 2006.173.17:19:57.05#ibcon#*before return 0, iclass 29, count 0 2006.173.17:19:57.05#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.17:19:57.05#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.17:19:57.05#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.17:19:57.05#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.17:19:57.06$vck44/vb=4,4 2006.173.17:19:57.06#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.17:19:57.06#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.17:19:57.06#ibcon#ireg 11 cls_cnt 2 2006.173.17:19:57.06#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.17:19:57.10#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.17:19:57.10#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.17:19:57.10#ibcon#enter wrdev, iclass 31, count 2 2006.173.17:19:57.10#ibcon#first serial, iclass 31, count 2 2006.173.17:19:57.10#ibcon#enter sib2, iclass 31, count 2 2006.173.17:19:57.10#ibcon#flushed, iclass 31, count 2 2006.173.17:19:57.10#ibcon#about to write, iclass 31, count 2 2006.173.17:19:57.10#ibcon#wrote, iclass 31, count 2 2006.173.17:19:57.10#ibcon#about to read 3, iclass 31, count 2 2006.173.17:19:57.12#ibcon#read 3, iclass 31, count 2 2006.173.17:19:57.12#ibcon#about to read 4, iclass 31, count 2 2006.173.17:19:57.12#ibcon#read 4, iclass 31, count 2 2006.173.17:19:57.12#ibcon#about to read 5, iclass 31, count 2 2006.173.17:19:57.12#ibcon#read 5, iclass 31, count 2 2006.173.17:19:57.12#ibcon#about to read 6, iclass 31, count 2 2006.173.17:19:57.12#ibcon#read 6, iclass 31, count 2 2006.173.17:19:57.12#ibcon#end of sib2, iclass 31, count 2 2006.173.17:19:57.12#ibcon#*mode == 0, iclass 31, count 2 2006.173.17:19:57.12#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.17:19:57.12#ibcon#[27=AT04-04\r\n] 2006.173.17:19:57.12#ibcon#*before write, iclass 31, count 2 2006.173.17:19:57.12#ibcon#enter sib2, iclass 31, count 2 2006.173.17:19:57.12#ibcon#flushed, iclass 31, count 2 2006.173.17:19:57.12#ibcon#about to write, iclass 31, count 2 2006.173.17:19:57.12#ibcon#wrote, iclass 31, count 2 2006.173.17:19:57.12#ibcon#about to read 3, iclass 31, count 2 2006.173.17:19:57.15#ibcon#read 3, iclass 31, count 2 2006.173.17:19:57.15#ibcon#about to read 4, iclass 31, count 2 2006.173.17:19:57.15#ibcon#read 4, iclass 31, count 2 2006.173.17:19:57.15#ibcon#about to read 5, iclass 31, count 2 2006.173.17:19:57.15#ibcon#read 5, iclass 31, count 2 2006.173.17:19:57.15#ibcon#about to read 6, iclass 31, count 2 2006.173.17:19:57.15#ibcon#read 6, iclass 31, count 2 2006.173.17:19:57.15#ibcon#end of sib2, iclass 31, count 2 2006.173.17:19:57.15#ibcon#*after write, iclass 31, count 2 2006.173.17:19:57.15#ibcon#*before return 0, iclass 31, count 2 2006.173.17:19:57.15#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.17:19:57.15#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.17:19:57.15#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.17:19:57.15#ibcon#ireg 7 cls_cnt 0 2006.173.17:19:57.15#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.17:19:57.27#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.17:19:57.27#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.17:19:57.27#ibcon#enter wrdev, iclass 31, count 0 2006.173.17:19:57.27#ibcon#first serial, iclass 31, count 0 2006.173.17:19:57.27#ibcon#enter sib2, iclass 31, count 0 2006.173.17:19:57.27#ibcon#flushed, iclass 31, count 0 2006.173.17:19:57.27#ibcon#about to write, iclass 31, count 0 2006.173.17:19:57.27#ibcon#wrote, iclass 31, count 0 2006.173.17:19:57.27#ibcon#about to read 3, iclass 31, count 0 2006.173.17:19:57.29#ibcon#read 3, iclass 31, count 0 2006.173.17:19:57.29#ibcon#about to read 4, iclass 31, count 0 2006.173.17:19:57.29#ibcon#read 4, iclass 31, count 0 2006.173.17:19:57.29#ibcon#about to read 5, iclass 31, count 0 2006.173.17:19:57.29#ibcon#read 5, iclass 31, count 0 2006.173.17:19:57.29#ibcon#about to read 6, iclass 31, count 0 2006.173.17:19:57.29#ibcon#read 6, iclass 31, count 0 2006.173.17:19:57.29#ibcon#end of sib2, iclass 31, count 0 2006.173.17:19:57.29#ibcon#*mode == 0, iclass 31, count 0 2006.173.17:19:57.29#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.17:19:57.29#ibcon#[27=USB\r\n] 2006.173.17:19:57.29#ibcon#*before write, iclass 31, count 0 2006.173.17:19:57.29#ibcon#enter sib2, iclass 31, count 0 2006.173.17:19:57.29#ibcon#flushed, iclass 31, count 0 2006.173.17:19:57.29#ibcon#about to write, iclass 31, count 0 2006.173.17:19:57.29#ibcon#wrote, iclass 31, count 0 2006.173.17:19:57.29#ibcon#about to read 3, iclass 31, count 0 2006.173.17:19:57.32#ibcon#read 3, iclass 31, count 0 2006.173.17:19:57.32#ibcon#about to read 4, iclass 31, count 0 2006.173.17:19:57.32#ibcon#read 4, iclass 31, count 0 2006.173.17:19:57.32#ibcon#about to read 5, iclass 31, count 0 2006.173.17:19:57.32#ibcon#read 5, iclass 31, count 0 2006.173.17:19:57.32#ibcon#about to read 6, iclass 31, count 0 2006.173.17:19:57.32#ibcon#read 6, iclass 31, count 0 2006.173.17:19:57.32#ibcon#end of sib2, iclass 31, count 0 2006.173.17:19:57.32#ibcon#*after write, iclass 31, count 0 2006.173.17:19:57.32#ibcon#*before return 0, iclass 31, count 0 2006.173.17:19:57.32#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.17:19:57.32#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.17:19:57.32#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.17:19:57.32#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.17:19:57.33$vck44/vblo=5,709.99 2006.173.17:19:57.33#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.17:19:57.33#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.17:19:57.33#ibcon#ireg 17 cls_cnt 0 2006.173.17:19:57.33#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.17:19:57.33#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.17:19:57.33#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.17:19:57.33#ibcon#enter wrdev, iclass 33, count 0 2006.173.17:19:57.33#ibcon#first serial, iclass 33, count 0 2006.173.17:19:57.33#ibcon#enter sib2, iclass 33, count 0 2006.173.17:19:57.33#ibcon#flushed, iclass 33, count 0 2006.173.17:19:57.33#ibcon#about to write, iclass 33, count 0 2006.173.17:19:57.33#ibcon#wrote, iclass 33, count 0 2006.173.17:19:57.33#ibcon#about to read 3, iclass 33, count 0 2006.173.17:19:57.34#ibcon#read 3, iclass 33, count 0 2006.173.17:19:57.34#ibcon#about to read 4, iclass 33, count 0 2006.173.17:19:57.34#ibcon#read 4, iclass 33, count 0 2006.173.17:19:57.34#ibcon#about to read 5, iclass 33, count 0 2006.173.17:19:57.34#ibcon#read 5, iclass 33, count 0 2006.173.17:19:57.34#ibcon#about to read 6, iclass 33, count 0 2006.173.17:19:57.34#ibcon#read 6, iclass 33, count 0 2006.173.17:19:57.34#ibcon#end of sib2, iclass 33, count 0 2006.173.17:19:57.34#ibcon#*mode == 0, iclass 33, count 0 2006.173.17:19:57.34#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.17:19:57.34#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.17:19:57.34#ibcon#*before write, iclass 33, count 0 2006.173.17:19:57.34#ibcon#enter sib2, iclass 33, count 0 2006.173.17:19:57.34#ibcon#flushed, iclass 33, count 0 2006.173.17:19:57.34#ibcon#about to write, iclass 33, count 0 2006.173.17:19:57.34#ibcon#wrote, iclass 33, count 0 2006.173.17:19:57.34#ibcon#about to read 3, iclass 33, count 0 2006.173.17:19:57.38#ibcon#read 3, iclass 33, count 0 2006.173.17:19:57.38#ibcon#about to read 4, iclass 33, count 0 2006.173.17:19:57.38#ibcon#read 4, iclass 33, count 0 2006.173.17:19:57.38#ibcon#about to read 5, iclass 33, count 0 2006.173.17:19:57.38#ibcon#read 5, iclass 33, count 0 2006.173.17:19:57.38#ibcon#about to read 6, iclass 33, count 0 2006.173.17:19:57.38#ibcon#read 6, iclass 33, count 0 2006.173.17:19:57.38#ibcon#end of sib2, iclass 33, count 0 2006.173.17:19:57.38#ibcon#*after write, iclass 33, count 0 2006.173.17:19:57.38#ibcon#*before return 0, iclass 33, count 0 2006.173.17:19:57.38#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.17:19:57.38#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.17:19:57.38#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.17:19:57.38#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.17:19:57.39$vck44/vb=5,4 2006.173.17:19:57.39#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.17:19:57.39#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.17:19:57.39#ibcon#ireg 11 cls_cnt 2 2006.173.17:19:57.39#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.17:19:57.43#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.17:19:57.43#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.17:19:57.43#ibcon#enter wrdev, iclass 35, count 2 2006.173.17:19:57.43#ibcon#first serial, iclass 35, count 2 2006.173.17:19:57.43#ibcon#enter sib2, iclass 35, count 2 2006.173.17:19:57.43#ibcon#flushed, iclass 35, count 2 2006.173.17:19:57.43#ibcon#about to write, iclass 35, count 2 2006.173.17:19:57.43#ibcon#wrote, iclass 35, count 2 2006.173.17:19:57.43#ibcon#about to read 3, iclass 35, count 2 2006.173.17:19:57.45#ibcon#read 3, iclass 35, count 2 2006.173.17:19:57.45#ibcon#about to read 4, iclass 35, count 2 2006.173.17:19:57.45#ibcon#read 4, iclass 35, count 2 2006.173.17:19:57.45#ibcon#about to read 5, iclass 35, count 2 2006.173.17:19:57.45#ibcon#read 5, iclass 35, count 2 2006.173.17:19:57.45#ibcon#about to read 6, iclass 35, count 2 2006.173.17:19:57.45#ibcon#read 6, iclass 35, count 2 2006.173.17:19:57.45#ibcon#end of sib2, iclass 35, count 2 2006.173.17:19:57.45#ibcon#*mode == 0, iclass 35, count 2 2006.173.17:19:57.45#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.17:19:57.45#ibcon#[27=AT05-04\r\n] 2006.173.17:19:57.45#ibcon#*before write, iclass 35, count 2 2006.173.17:19:57.45#ibcon#enter sib2, iclass 35, count 2 2006.173.17:19:57.45#ibcon#flushed, iclass 35, count 2 2006.173.17:19:57.45#ibcon#about to write, iclass 35, count 2 2006.173.17:19:57.45#ibcon#wrote, iclass 35, count 2 2006.173.17:19:57.45#ibcon#about to read 3, iclass 35, count 2 2006.173.17:19:57.48#ibcon#read 3, iclass 35, count 2 2006.173.17:19:57.48#ibcon#about to read 4, iclass 35, count 2 2006.173.17:19:57.48#ibcon#read 4, iclass 35, count 2 2006.173.17:19:57.48#ibcon#about to read 5, iclass 35, count 2 2006.173.17:19:57.48#ibcon#read 5, iclass 35, count 2 2006.173.17:19:57.48#ibcon#about to read 6, iclass 35, count 2 2006.173.17:19:57.48#ibcon#read 6, iclass 35, count 2 2006.173.17:19:57.48#ibcon#end of sib2, iclass 35, count 2 2006.173.17:19:57.48#ibcon#*after write, iclass 35, count 2 2006.173.17:19:57.48#ibcon#*before return 0, iclass 35, count 2 2006.173.17:19:57.48#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.17:19:57.48#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.17:19:57.48#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.17:19:57.48#ibcon#ireg 7 cls_cnt 0 2006.173.17:19:57.48#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.17:19:57.60#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.17:19:57.60#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.17:19:57.60#ibcon#enter wrdev, iclass 35, count 0 2006.173.17:19:57.60#ibcon#first serial, iclass 35, count 0 2006.173.17:19:57.60#ibcon#enter sib2, iclass 35, count 0 2006.173.17:19:57.60#ibcon#flushed, iclass 35, count 0 2006.173.17:19:57.60#ibcon#about to write, iclass 35, count 0 2006.173.17:19:57.60#ibcon#wrote, iclass 35, count 0 2006.173.17:19:57.60#ibcon#about to read 3, iclass 35, count 0 2006.173.17:19:57.62#ibcon#read 3, iclass 35, count 0 2006.173.17:19:57.62#ibcon#about to read 4, iclass 35, count 0 2006.173.17:19:57.62#ibcon#read 4, iclass 35, count 0 2006.173.17:19:57.62#ibcon#about to read 5, iclass 35, count 0 2006.173.17:19:57.62#ibcon#read 5, iclass 35, count 0 2006.173.17:19:57.62#ibcon#about to read 6, iclass 35, count 0 2006.173.17:19:57.62#ibcon#read 6, iclass 35, count 0 2006.173.17:19:57.62#ibcon#end of sib2, iclass 35, count 0 2006.173.17:19:57.62#ibcon#*mode == 0, iclass 35, count 0 2006.173.17:19:57.62#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.17:19:57.62#ibcon#[27=USB\r\n] 2006.173.17:19:57.62#ibcon#*before write, iclass 35, count 0 2006.173.17:19:57.62#ibcon#enter sib2, iclass 35, count 0 2006.173.17:19:57.62#ibcon#flushed, iclass 35, count 0 2006.173.17:19:57.62#ibcon#about to write, iclass 35, count 0 2006.173.17:19:57.62#ibcon#wrote, iclass 35, count 0 2006.173.17:19:57.62#ibcon#about to read 3, iclass 35, count 0 2006.173.17:19:57.65#ibcon#read 3, iclass 35, count 0 2006.173.17:19:57.65#ibcon#about to read 4, iclass 35, count 0 2006.173.17:19:57.65#ibcon#read 4, iclass 35, count 0 2006.173.17:19:57.65#ibcon#about to read 5, iclass 35, count 0 2006.173.17:19:57.65#ibcon#read 5, iclass 35, count 0 2006.173.17:19:57.65#ibcon#about to read 6, iclass 35, count 0 2006.173.17:19:57.65#ibcon#read 6, iclass 35, count 0 2006.173.17:19:57.65#ibcon#end of sib2, iclass 35, count 0 2006.173.17:19:57.65#ibcon#*after write, iclass 35, count 0 2006.173.17:19:57.65#ibcon#*before return 0, iclass 35, count 0 2006.173.17:19:57.65#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.17:19:57.65#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.17:19:57.65#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.17:19:57.65#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.17:19:57.66$vck44/vblo=6,719.99 2006.173.17:19:57.66#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.17:19:57.66#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.17:19:57.66#ibcon#ireg 17 cls_cnt 0 2006.173.17:19:57.66#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.17:19:57.66#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.17:19:57.66#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.17:19:57.66#ibcon#enter wrdev, iclass 37, count 0 2006.173.17:19:57.66#ibcon#first serial, iclass 37, count 0 2006.173.17:19:57.66#ibcon#enter sib2, iclass 37, count 0 2006.173.17:19:57.66#ibcon#flushed, iclass 37, count 0 2006.173.17:19:57.66#ibcon#about to write, iclass 37, count 0 2006.173.17:19:57.66#ibcon#wrote, iclass 37, count 0 2006.173.17:19:57.66#ibcon#about to read 3, iclass 37, count 0 2006.173.17:19:57.67#ibcon#read 3, iclass 37, count 0 2006.173.17:19:57.67#ibcon#about to read 4, iclass 37, count 0 2006.173.17:19:57.67#ibcon#read 4, iclass 37, count 0 2006.173.17:19:57.67#ibcon#about to read 5, iclass 37, count 0 2006.173.17:19:57.67#ibcon#read 5, iclass 37, count 0 2006.173.17:19:57.67#ibcon#about to read 6, iclass 37, count 0 2006.173.17:19:57.67#ibcon#read 6, iclass 37, count 0 2006.173.17:19:57.67#ibcon#end of sib2, iclass 37, count 0 2006.173.17:19:57.67#ibcon#*mode == 0, iclass 37, count 0 2006.173.17:19:57.67#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.17:19:57.67#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.17:19:57.67#ibcon#*before write, iclass 37, count 0 2006.173.17:19:57.67#ibcon#enter sib2, iclass 37, count 0 2006.173.17:19:57.67#ibcon#flushed, iclass 37, count 0 2006.173.17:19:57.67#ibcon#about to write, iclass 37, count 0 2006.173.17:19:57.67#ibcon#wrote, iclass 37, count 0 2006.173.17:19:57.67#ibcon#about to read 3, iclass 37, count 0 2006.173.17:19:57.71#ibcon#read 3, iclass 37, count 0 2006.173.17:19:57.71#ibcon#about to read 4, iclass 37, count 0 2006.173.17:19:57.71#ibcon#read 4, iclass 37, count 0 2006.173.17:19:57.71#ibcon#about to read 5, iclass 37, count 0 2006.173.17:19:57.71#ibcon#read 5, iclass 37, count 0 2006.173.17:19:57.71#ibcon#about to read 6, iclass 37, count 0 2006.173.17:19:57.71#ibcon#read 6, iclass 37, count 0 2006.173.17:19:57.71#ibcon#end of sib2, iclass 37, count 0 2006.173.17:19:57.71#ibcon#*after write, iclass 37, count 0 2006.173.17:19:57.71#ibcon#*before return 0, iclass 37, count 0 2006.173.17:19:57.71#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.17:19:57.71#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.17:19:57.71#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.17:19:57.71#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.17:19:57.72$vck44/vb=6,4 2006.173.17:19:57.72#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.17:19:57.72#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.17:19:57.72#ibcon#ireg 11 cls_cnt 2 2006.173.17:19:57.72#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.17:19:57.76#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.17:19:57.76#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.17:19:57.76#ibcon#enter wrdev, iclass 39, count 2 2006.173.17:19:57.76#ibcon#first serial, iclass 39, count 2 2006.173.17:19:57.76#ibcon#enter sib2, iclass 39, count 2 2006.173.17:19:57.76#ibcon#flushed, iclass 39, count 2 2006.173.17:19:57.76#ibcon#about to write, iclass 39, count 2 2006.173.17:19:57.76#ibcon#wrote, iclass 39, count 2 2006.173.17:19:57.76#ibcon#about to read 3, iclass 39, count 2 2006.173.17:19:57.78#ibcon#read 3, iclass 39, count 2 2006.173.17:19:57.78#ibcon#about to read 4, iclass 39, count 2 2006.173.17:19:57.78#ibcon#read 4, iclass 39, count 2 2006.173.17:19:57.78#ibcon#about to read 5, iclass 39, count 2 2006.173.17:19:57.78#ibcon#read 5, iclass 39, count 2 2006.173.17:19:57.78#ibcon#about to read 6, iclass 39, count 2 2006.173.17:19:57.78#ibcon#read 6, iclass 39, count 2 2006.173.17:19:57.78#ibcon#end of sib2, iclass 39, count 2 2006.173.17:19:57.78#ibcon#*mode == 0, iclass 39, count 2 2006.173.17:19:57.78#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.17:19:57.78#ibcon#[27=AT06-04\r\n] 2006.173.17:19:57.78#ibcon#*before write, iclass 39, count 2 2006.173.17:19:57.78#ibcon#enter sib2, iclass 39, count 2 2006.173.17:19:57.78#ibcon#flushed, iclass 39, count 2 2006.173.17:19:57.78#ibcon#about to write, iclass 39, count 2 2006.173.17:19:57.78#ibcon#wrote, iclass 39, count 2 2006.173.17:19:57.78#ibcon#about to read 3, iclass 39, count 2 2006.173.17:19:57.81#ibcon#read 3, iclass 39, count 2 2006.173.17:19:57.81#ibcon#about to read 4, iclass 39, count 2 2006.173.17:19:57.81#ibcon#read 4, iclass 39, count 2 2006.173.17:19:57.81#ibcon#about to read 5, iclass 39, count 2 2006.173.17:19:57.81#ibcon#read 5, iclass 39, count 2 2006.173.17:19:57.81#ibcon#about to read 6, iclass 39, count 2 2006.173.17:19:57.81#ibcon#read 6, iclass 39, count 2 2006.173.17:19:57.81#ibcon#end of sib2, iclass 39, count 2 2006.173.17:19:57.81#ibcon#*after write, iclass 39, count 2 2006.173.17:19:57.81#ibcon#*before return 0, iclass 39, count 2 2006.173.17:19:57.81#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.17:19:57.81#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.17:19:57.81#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.17:19:57.81#ibcon#ireg 7 cls_cnt 0 2006.173.17:19:57.81#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.17:19:57.93#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.17:19:57.93#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.17:19:57.93#ibcon#enter wrdev, iclass 39, count 0 2006.173.17:19:57.93#ibcon#first serial, iclass 39, count 0 2006.173.17:19:57.93#ibcon#enter sib2, iclass 39, count 0 2006.173.17:19:57.93#ibcon#flushed, iclass 39, count 0 2006.173.17:19:57.93#ibcon#about to write, iclass 39, count 0 2006.173.17:19:57.93#ibcon#wrote, iclass 39, count 0 2006.173.17:19:57.93#ibcon#about to read 3, iclass 39, count 0 2006.173.17:19:57.95#ibcon#read 3, iclass 39, count 0 2006.173.17:19:57.95#ibcon#about to read 4, iclass 39, count 0 2006.173.17:19:57.95#ibcon#read 4, iclass 39, count 0 2006.173.17:19:57.95#ibcon#about to read 5, iclass 39, count 0 2006.173.17:19:57.95#ibcon#read 5, iclass 39, count 0 2006.173.17:19:57.95#ibcon#about to read 6, iclass 39, count 0 2006.173.17:19:57.95#ibcon#read 6, iclass 39, count 0 2006.173.17:19:57.95#ibcon#end of sib2, iclass 39, count 0 2006.173.17:19:57.95#ibcon#*mode == 0, iclass 39, count 0 2006.173.17:19:57.95#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.17:19:57.95#ibcon#[27=USB\r\n] 2006.173.17:19:57.95#ibcon#*before write, iclass 39, count 0 2006.173.17:19:57.95#ibcon#enter sib2, iclass 39, count 0 2006.173.17:19:57.95#ibcon#flushed, iclass 39, count 0 2006.173.17:19:57.95#ibcon#about to write, iclass 39, count 0 2006.173.17:19:57.95#ibcon#wrote, iclass 39, count 0 2006.173.17:19:57.95#ibcon#about to read 3, iclass 39, count 0 2006.173.17:19:57.98#ibcon#read 3, iclass 39, count 0 2006.173.17:19:57.98#ibcon#about to read 4, iclass 39, count 0 2006.173.17:19:57.98#ibcon#read 4, iclass 39, count 0 2006.173.17:19:57.98#ibcon#about to read 5, iclass 39, count 0 2006.173.17:19:57.98#ibcon#read 5, iclass 39, count 0 2006.173.17:19:57.98#ibcon#about to read 6, iclass 39, count 0 2006.173.17:19:57.98#ibcon#read 6, iclass 39, count 0 2006.173.17:19:57.98#ibcon#end of sib2, iclass 39, count 0 2006.173.17:19:57.98#ibcon#*after write, iclass 39, count 0 2006.173.17:19:57.98#ibcon#*before return 0, iclass 39, count 0 2006.173.17:19:57.98#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.17:19:57.98#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.17:19:57.98#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.17:19:57.98#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.17:19:57.99$vck44/vblo=7,734.99 2006.173.17:19:57.99#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.17:19:57.99#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.17:19:57.99#ibcon#ireg 17 cls_cnt 0 2006.173.17:19:57.99#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.17:19:57.99#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.17:19:57.99#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.17:19:57.99#ibcon#enter wrdev, iclass 3, count 0 2006.173.17:19:57.99#ibcon#first serial, iclass 3, count 0 2006.173.17:19:57.99#ibcon#enter sib2, iclass 3, count 0 2006.173.17:19:57.99#ibcon#flushed, iclass 3, count 0 2006.173.17:19:57.99#ibcon#about to write, iclass 3, count 0 2006.173.17:19:57.99#ibcon#wrote, iclass 3, count 0 2006.173.17:19:57.99#ibcon#about to read 3, iclass 3, count 0 2006.173.17:19:58.00#ibcon#read 3, iclass 3, count 0 2006.173.17:19:58.00#ibcon#about to read 4, iclass 3, count 0 2006.173.17:19:58.00#ibcon#read 4, iclass 3, count 0 2006.173.17:19:58.00#ibcon#about to read 5, iclass 3, count 0 2006.173.17:19:58.00#ibcon#read 5, iclass 3, count 0 2006.173.17:19:58.00#ibcon#about to read 6, iclass 3, count 0 2006.173.17:19:58.00#ibcon#read 6, iclass 3, count 0 2006.173.17:19:58.00#ibcon#end of sib2, iclass 3, count 0 2006.173.17:19:58.00#ibcon#*mode == 0, iclass 3, count 0 2006.173.17:19:58.00#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.17:19:58.00#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.17:19:58.00#ibcon#*before write, iclass 3, count 0 2006.173.17:19:58.00#ibcon#enter sib2, iclass 3, count 0 2006.173.17:19:58.00#ibcon#flushed, iclass 3, count 0 2006.173.17:19:58.00#ibcon#about to write, iclass 3, count 0 2006.173.17:19:58.00#ibcon#wrote, iclass 3, count 0 2006.173.17:19:58.00#ibcon#about to read 3, iclass 3, count 0 2006.173.17:19:58.04#ibcon#read 3, iclass 3, count 0 2006.173.17:19:58.04#ibcon#about to read 4, iclass 3, count 0 2006.173.17:19:58.04#ibcon#read 4, iclass 3, count 0 2006.173.17:19:58.04#ibcon#about to read 5, iclass 3, count 0 2006.173.17:19:58.04#ibcon#read 5, iclass 3, count 0 2006.173.17:19:58.04#ibcon#about to read 6, iclass 3, count 0 2006.173.17:19:58.04#ibcon#read 6, iclass 3, count 0 2006.173.17:19:58.04#ibcon#end of sib2, iclass 3, count 0 2006.173.17:19:58.04#ibcon#*after write, iclass 3, count 0 2006.173.17:19:58.04#ibcon#*before return 0, iclass 3, count 0 2006.173.17:19:58.04#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.17:19:58.04#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.17:19:58.04#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.17:19:58.04#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.17:19:58.05$vck44/vb=7,4 2006.173.17:19:58.05#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.17:19:58.05#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.17:19:58.05#ibcon#ireg 11 cls_cnt 2 2006.173.17:19:58.05#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.17:19:58.09#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.17:19:58.09#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.17:19:58.09#ibcon#enter wrdev, iclass 5, count 2 2006.173.17:19:58.09#ibcon#first serial, iclass 5, count 2 2006.173.17:19:58.09#ibcon#enter sib2, iclass 5, count 2 2006.173.17:19:58.09#ibcon#flushed, iclass 5, count 2 2006.173.17:19:58.09#ibcon#about to write, iclass 5, count 2 2006.173.17:19:58.09#ibcon#wrote, iclass 5, count 2 2006.173.17:19:58.09#ibcon#about to read 3, iclass 5, count 2 2006.173.17:19:58.11#ibcon#read 3, iclass 5, count 2 2006.173.17:19:58.11#ibcon#about to read 4, iclass 5, count 2 2006.173.17:19:58.11#ibcon#read 4, iclass 5, count 2 2006.173.17:19:58.11#ibcon#about to read 5, iclass 5, count 2 2006.173.17:19:58.11#ibcon#read 5, iclass 5, count 2 2006.173.17:19:58.11#ibcon#about to read 6, iclass 5, count 2 2006.173.17:19:58.11#ibcon#read 6, iclass 5, count 2 2006.173.17:19:58.11#ibcon#end of sib2, iclass 5, count 2 2006.173.17:19:58.11#ibcon#*mode == 0, iclass 5, count 2 2006.173.17:19:58.11#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.17:19:58.11#ibcon#[27=AT07-04\r\n] 2006.173.17:19:58.11#ibcon#*before write, iclass 5, count 2 2006.173.17:19:58.11#ibcon#enter sib2, iclass 5, count 2 2006.173.17:19:58.11#ibcon#flushed, iclass 5, count 2 2006.173.17:19:58.11#ibcon#about to write, iclass 5, count 2 2006.173.17:19:58.11#ibcon#wrote, iclass 5, count 2 2006.173.17:19:58.11#ibcon#about to read 3, iclass 5, count 2 2006.173.17:19:58.15#ibcon#read 3, iclass 5, count 2 2006.173.17:19:58.15#ibcon#about to read 4, iclass 5, count 2 2006.173.17:19:58.15#ibcon#read 4, iclass 5, count 2 2006.173.17:19:58.15#ibcon#about to read 5, iclass 5, count 2 2006.173.17:19:58.15#ibcon#read 5, iclass 5, count 2 2006.173.17:19:58.15#ibcon#about to read 6, iclass 5, count 2 2006.173.17:19:58.15#ibcon#read 6, iclass 5, count 2 2006.173.17:19:58.15#ibcon#end of sib2, iclass 5, count 2 2006.173.17:19:58.15#ibcon#*after write, iclass 5, count 2 2006.173.17:19:58.15#ibcon#*before return 0, iclass 5, count 2 2006.173.17:19:58.15#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.17:19:58.15#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.17:19:58.15#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.17:19:58.15#ibcon#ireg 7 cls_cnt 0 2006.173.17:19:58.15#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.17:19:58.26#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.17:19:58.26#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.17:19:58.26#ibcon#enter wrdev, iclass 5, count 0 2006.173.17:19:58.26#ibcon#first serial, iclass 5, count 0 2006.173.17:19:58.26#ibcon#enter sib2, iclass 5, count 0 2006.173.17:19:58.26#ibcon#flushed, iclass 5, count 0 2006.173.17:19:58.26#ibcon#about to write, iclass 5, count 0 2006.173.17:19:58.26#ibcon#wrote, iclass 5, count 0 2006.173.17:19:58.26#ibcon#about to read 3, iclass 5, count 0 2006.173.17:19:58.28#ibcon#read 3, iclass 5, count 0 2006.173.17:19:58.28#ibcon#about to read 4, iclass 5, count 0 2006.173.17:19:58.28#ibcon#read 4, iclass 5, count 0 2006.173.17:19:58.28#ibcon#about to read 5, iclass 5, count 0 2006.173.17:19:58.28#ibcon#read 5, iclass 5, count 0 2006.173.17:19:58.28#ibcon#about to read 6, iclass 5, count 0 2006.173.17:19:58.28#ibcon#read 6, iclass 5, count 0 2006.173.17:19:58.28#ibcon#end of sib2, iclass 5, count 0 2006.173.17:19:58.28#ibcon#*mode == 0, iclass 5, count 0 2006.173.17:19:58.28#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.17:19:58.28#ibcon#[27=USB\r\n] 2006.173.17:19:58.28#ibcon#*before write, iclass 5, count 0 2006.173.17:19:58.28#ibcon#enter sib2, iclass 5, count 0 2006.173.17:19:58.28#ibcon#flushed, iclass 5, count 0 2006.173.17:19:58.28#ibcon#about to write, iclass 5, count 0 2006.173.17:19:58.28#ibcon#wrote, iclass 5, count 0 2006.173.17:19:58.28#ibcon#about to read 3, iclass 5, count 0 2006.173.17:19:58.31#ibcon#read 3, iclass 5, count 0 2006.173.17:19:58.31#ibcon#about to read 4, iclass 5, count 0 2006.173.17:19:58.31#ibcon#read 4, iclass 5, count 0 2006.173.17:19:58.31#ibcon#about to read 5, iclass 5, count 0 2006.173.17:19:58.31#ibcon#read 5, iclass 5, count 0 2006.173.17:19:58.31#ibcon#about to read 6, iclass 5, count 0 2006.173.17:19:58.31#ibcon#read 6, iclass 5, count 0 2006.173.17:19:58.31#ibcon#end of sib2, iclass 5, count 0 2006.173.17:19:58.31#ibcon#*after write, iclass 5, count 0 2006.173.17:19:58.31#ibcon#*before return 0, iclass 5, count 0 2006.173.17:19:58.31#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.17:19:58.31#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.17:19:58.31#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.17:19:58.31#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.17:19:58.32$vck44/vblo=8,744.99 2006.173.17:19:58.32#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.17:19:58.32#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.17:19:58.32#ibcon#ireg 17 cls_cnt 0 2006.173.17:19:58.32#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.17:19:58.32#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.17:19:58.32#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.17:19:58.32#ibcon#enter wrdev, iclass 7, count 0 2006.173.17:19:58.32#ibcon#first serial, iclass 7, count 0 2006.173.17:19:58.32#ibcon#enter sib2, iclass 7, count 0 2006.173.17:19:58.32#ibcon#flushed, iclass 7, count 0 2006.173.17:19:58.32#ibcon#about to write, iclass 7, count 0 2006.173.17:19:58.32#ibcon#wrote, iclass 7, count 0 2006.173.17:19:58.32#ibcon#about to read 3, iclass 7, count 0 2006.173.17:19:58.33#ibcon#read 3, iclass 7, count 0 2006.173.17:19:58.33#ibcon#about to read 4, iclass 7, count 0 2006.173.17:19:58.33#ibcon#read 4, iclass 7, count 0 2006.173.17:19:58.33#ibcon#about to read 5, iclass 7, count 0 2006.173.17:19:58.33#ibcon#read 5, iclass 7, count 0 2006.173.17:19:58.33#ibcon#about to read 6, iclass 7, count 0 2006.173.17:19:58.33#ibcon#read 6, iclass 7, count 0 2006.173.17:19:58.33#ibcon#end of sib2, iclass 7, count 0 2006.173.17:19:58.33#ibcon#*mode == 0, iclass 7, count 0 2006.173.17:19:58.33#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.17:19:58.33#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.17:19:58.33#ibcon#*before write, iclass 7, count 0 2006.173.17:19:58.33#ibcon#enter sib2, iclass 7, count 0 2006.173.17:19:58.33#ibcon#flushed, iclass 7, count 0 2006.173.17:19:58.33#ibcon#about to write, iclass 7, count 0 2006.173.17:19:58.33#ibcon#wrote, iclass 7, count 0 2006.173.17:19:58.33#ibcon#about to read 3, iclass 7, count 0 2006.173.17:19:58.37#ibcon#read 3, iclass 7, count 0 2006.173.17:19:58.37#ibcon#about to read 4, iclass 7, count 0 2006.173.17:19:58.37#ibcon#read 4, iclass 7, count 0 2006.173.17:19:58.37#ibcon#about to read 5, iclass 7, count 0 2006.173.17:19:58.37#ibcon#read 5, iclass 7, count 0 2006.173.17:19:58.37#ibcon#about to read 6, iclass 7, count 0 2006.173.17:19:58.37#ibcon#read 6, iclass 7, count 0 2006.173.17:19:58.37#ibcon#end of sib2, iclass 7, count 0 2006.173.17:19:58.37#ibcon#*after write, iclass 7, count 0 2006.173.17:19:58.37#ibcon#*before return 0, iclass 7, count 0 2006.173.17:19:58.37#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.17:19:58.37#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.17:19:58.37#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.17:19:58.37#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.17:19:58.38$vck44/vb=8,4 2006.173.17:19:58.38#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.17:19:58.38#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.17:19:58.38#ibcon#ireg 11 cls_cnt 2 2006.173.17:19:58.38#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.17:19:58.42#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.17:19:58.42#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.17:19:58.42#ibcon#enter wrdev, iclass 11, count 2 2006.173.17:19:58.42#ibcon#first serial, iclass 11, count 2 2006.173.17:19:58.42#ibcon#enter sib2, iclass 11, count 2 2006.173.17:19:58.42#ibcon#flushed, iclass 11, count 2 2006.173.17:19:58.42#ibcon#about to write, iclass 11, count 2 2006.173.17:19:58.42#ibcon#wrote, iclass 11, count 2 2006.173.17:19:58.42#ibcon#about to read 3, iclass 11, count 2 2006.173.17:19:58.44#ibcon#read 3, iclass 11, count 2 2006.173.17:19:58.44#ibcon#about to read 4, iclass 11, count 2 2006.173.17:19:58.44#ibcon#read 4, iclass 11, count 2 2006.173.17:19:58.44#ibcon#about to read 5, iclass 11, count 2 2006.173.17:19:58.44#ibcon#read 5, iclass 11, count 2 2006.173.17:19:58.44#ibcon#about to read 6, iclass 11, count 2 2006.173.17:19:58.44#ibcon#read 6, iclass 11, count 2 2006.173.17:19:58.44#ibcon#end of sib2, iclass 11, count 2 2006.173.17:19:58.44#ibcon#*mode == 0, iclass 11, count 2 2006.173.17:19:58.44#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.17:19:58.44#ibcon#[27=AT08-04\r\n] 2006.173.17:19:58.44#ibcon#*before write, iclass 11, count 2 2006.173.17:19:58.44#ibcon#enter sib2, iclass 11, count 2 2006.173.17:19:58.44#ibcon#flushed, iclass 11, count 2 2006.173.17:19:58.44#ibcon#about to write, iclass 11, count 2 2006.173.17:19:58.44#ibcon#wrote, iclass 11, count 2 2006.173.17:19:58.44#ibcon#about to read 3, iclass 11, count 2 2006.173.17:19:58.47#ibcon#read 3, iclass 11, count 2 2006.173.17:19:58.47#ibcon#about to read 4, iclass 11, count 2 2006.173.17:19:58.47#ibcon#read 4, iclass 11, count 2 2006.173.17:19:58.47#ibcon#about to read 5, iclass 11, count 2 2006.173.17:19:58.47#ibcon#read 5, iclass 11, count 2 2006.173.17:19:58.47#ibcon#about to read 6, iclass 11, count 2 2006.173.17:19:58.47#ibcon#read 6, iclass 11, count 2 2006.173.17:19:58.47#ibcon#end of sib2, iclass 11, count 2 2006.173.17:19:58.47#ibcon#*after write, iclass 11, count 2 2006.173.17:19:58.47#ibcon#*before return 0, iclass 11, count 2 2006.173.17:19:58.47#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.17:19:58.47#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.17:19:58.47#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.17:19:58.47#ibcon#ireg 7 cls_cnt 0 2006.173.17:19:58.47#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.17:19:58.59#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.17:19:58.59#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.17:19:58.59#ibcon#enter wrdev, iclass 11, count 0 2006.173.17:19:58.59#ibcon#first serial, iclass 11, count 0 2006.173.17:19:58.59#ibcon#enter sib2, iclass 11, count 0 2006.173.17:19:58.59#ibcon#flushed, iclass 11, count 0 2006.173.17:19:58.59#ibcon#about to write, iclass 11, count 0 2006.173.17:19:58.59#ibcon#wrote, iclass 11, count 0 2006.173.17:19:58.59#ibcon#about to read 3, iclass 11, count 0 2006.173.17:19:58.61#ibcon#read 3, iclass 11, count 0 2006.173.17:19:58.61#ibcon#about to read 4, iclass 11, count 0 2006.173.17:19:58.61#ibcon#read 4, iclass 11, count 0 2006.173.17:19:58.61#ibcon#about to read 5, iclass 11, count 0 2006.173.17:19:58.61#ibcon#read 5, iclass 11, count 0 2006.173.17:19:58.61#ibcon#about to read 6, iclass 11, count 0 2006.173.17:19:58.61#ibcon#read 6, iclass 11, count 0 2006.173.17:19:58.61#ibcon#end of sib2, iclass 11, count 0 2006.173.17:19:58.61#ibcon#*mode == 0, iclass 11, count 0 2006.173.17:19:58.61#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.17:19:58.61#ibcon#[27=USB\r\n] 2006.173.17:19:58.61#ibcon#*before write, iclass 11, count 0 2006.173.17:19:58.61#ibcon#enter sib2, iclass 11, count 0 2006.173.17:19:58.61#ibcon#flushed, iclass 11, count 0 2006.173.17:19:58.61#ibcon#about to write, iclass 11, count 0 2006.173.17:19:58.61#ibcon#wrote, iclass 11, count 0 2006.173.17:19:58.61#ibcon#about to read 3, iclass 11, count 0 2006.173.17:19:58.64#ibcon#read 3, iclass 11, count 0 2006.173.17:19:58.64#ibcon#about to read 4, iclass 11, count 0 2006.173.17:19:58.64#ibcon#read 4, iclass 11, count 0 2006.173.17:19:58.64#ibcon#about to read 5, iclass 11, count 0 2006.173.17:19:58.64#ibcon#read 5, iclass 11, count 0 2006.173.17:19:58.64#ibcon#about to read 6, iclass 11, count 0 2006.173.17:19:58.64#ibcon#read 6, iclass 11, count 0 2006.173.17:19:58.64#ibcon#end of sib2, iclass 11, count 0 2006.173.17:19:58.64#ibcon#*after write, iclass 11, count 0 2006.173.17:19:58.64#ibcon#*before return 0, iclass 11, count 0 2006.173.17:19:58.64#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.17:19:58.64#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.17:19:58.64#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.17:19:58.64#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.17:19:58.65$vck44/vabw=wide 2006.173.17:19:58.65#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.17:19:58.65#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.17:19:58.65#ibcon#ireg 8 cls_cnt 0 2006.173.17:19:58.65#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.17:19:58.65#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.17:19:58.65#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.17:19:58.65#ibcon#enter wrdev, iclass 13, count 0 2006.173.17:19:58.65#ibcon#first serial, iclass 13, count 0 2006.173.17:19:58.65#ibcon#enter sib2, iclass 13, count 0 2006.173.17:19:58.65#ibcon#flushed, iclass 13, count 0 2006.173.17:19:58.65#ibcon#about to write, iclass 13, count 0 2006.173.17:19:58.65#ibcon#wrote, iclass 13, count 0 2006.173.17:19:58.65#ibcon#about to read 3, iclass 13, count 0 2006.173.17:19:58.66#ibcon#read 3, iclass 13, count 0 2006.173.17:19:58.66#ibcon#about to read 4, iclass 13, count 0 2006.173.17:19:58.66#ibcon#read 4, iclass 13, count 0 2006.173.17:19:58.66#ibcon#about to read 5, iclass 13, count 0 2006.173.17:19:58.66#ibcon#read 5, iclass 13, count 0 2006.173.17:19:58.66#ibcon#about to read 6, iclass 13, count 0 2006.173.17:19:58.66#ibcon#read 6, iclass 13, count 0 2006.173.17:19:58.66#ibcon#end of sib2, iclass 13, count 0 2006.173.17:19:58.66#ibcon#*mode == 0, iclass 13, count 0 2006.173.17:19:58.66#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.17:19:58.66#ibcon#[25=BW32\r\n] 2006.173.17:19:58.66#ibcon#*before write, iclass 13, count 0 2006.173.17:19:58.66#ibcon#enter sib2, iclass 13, count 0 2006.173.17:19:58.66#ibcon#flushed, iclass 13, count 0 2006.173.17:19:58.66#ibcon#about to write, iclass 13, count 0 2006.173.17:19:58.66#ibcon#wrote, iclass 13, count 0 2006.173.17:19:58.66#ibcon#about to read 3, iclass 13, count 0 2006.173.17:19:58.69#ibcon#read 3, iclass 13, count 0 2006.173.17:19:58.69#ibcon#about to read 4, iclass 13, count 0 2006.173.17:19:58.69#ibcon#read 4, iclass 13, count 0 2006.173.17:19:58.69#ibcon#about to read 5, iclass 13, count 0 2006.173.17:19:58.69#ibcon#read 5, iclass 13, count 0 2006.173.17:19:58.69#ibcon#about to read 6, iclass 13, count 0 2006.173.17:19:58.69#ibcon#read 6, iclass 13, count 0 2006.173.17:19:58.69#ibcon#end of sib2, iclass 13, count 0 2006.173.17:19:58.69#ibcon#*after write, iclass 13, count 0 2006.173.17:19:58.69#ibcon#*before return 0, iclass 13, count 0 2006.173.17:19:58.69#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.17:19:58.69#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.17:19:58.69#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.17:19:58.69#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.17:19:58.70$vck44/vbbw=wide 2006.173.17:19:58.70#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.17:19:58.70#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.17:19:58.70#ibcon#ireg 8 cls_cnt 0 2006.173.17:19:58.70#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.17:19:58.75#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.17:19:58.75#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.17:19:58.75#ibcon#enter wrdev, iclass 15, count 0 2006.173.17:19:58.75#ibcon#first serial, iclass 15, count 0 2006.173.17:19:58.75#ibcon#enter sib2, iclass 15, count 0 2006.173.17:19:58.75#ibcon#flushed, iclass 15, count 0 2006.173.17:19:58.75#ibcon#about to write, iclass 15, count 0 2006.173.17:19:58.75#ibcon#wrote, iclass 15, count 0 2006.173.17:19:58.75#ibcon#about to read 3, iclass 15, count 0 2006.173.17:19:58.77#ibcon#read 3, iclass 15, count 0 2006.173.17:19:58.77#ibcon#about to read 4, iclass 15, count 0 2006.173.17:19:58.77#ibcon#read 4, iclass 15, count 0 2006.173.17:19:58.77#ibcon#about to read 5, iclass 15, count 0 2006.173.17:19:58.77#ibcon#read 5, iclass 15, count 0 2006.173.17:19:58.77#ibcon#about to read 6, iclass 15, count 0 2006.173.17:19:58.77#ibcon#read 6, iclass 15, count 0 2006.173.17:19:58.77#ibcon#end of sib2, iclass 15, count 0 2006.173.17:19:58.77#ibcon#*mode == 0, iclass 15, count 0 2006.173.17:19:58.77#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.17:19:58.77#ibcon#[27=BW32\r\n] 2006.173.17:19:58.77#ibcon#*before write, iclass 15, count 0 2006.173.17:19:58.77#ibcon#enter sib2, iclass 15, count 0 2006.173.17:19:58.77#ibcon#flushed, iclass 15, count 0 2006.173.17:19:58.77#ibcon#about to write, iclass 15, count 0 2006.173.17:19:58.77#ibcon#wrote, iclass 15, count 0 2006.173.17:19:58.77#ibcon#about to read 3, iclass 15, count 0 2006.173.17:19:58.80#ibcon#read 3, iclass 15, count 0 2006.173.17:19:58.80#ibcon#about to read 4, iclass 15, count 0 2006.173.17:19:58.80#ibcon#read 4, iclass 15, count 0 2006.173.17:19:58.80#ibcon#about to read 5, iclass 15, count 0 2006.173.17:19:58.80#ibcon#read 5, iclass 15, count 0 2006.173.17:19:58.80#ibcon#about to read 6, iclass 15, count 0 2006.173.17:19:58.80#ibcon#read 6, iclass 15, count 0 2006.173.17:19:58.80#ibcon#end of sib2, iclass 15, count 0 2006.173.17:19:58.80#ibcon#*after write, iclass 15, count 0 2006.173.17:19:58.80#ibcon#*before return 0, iclass 15, count 0 2006.173.17:19:58.80#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.17:19:58.80#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.17:19:58.80#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.17:19:58.80#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.17:19:58.81$setupk4/ifdk4 2006.173.17:19:58.81$ifdk4/lo= 2006.173.17:19:58.81$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.17:19:58.81$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.17:19:58.81$ifdk4/patch= 2006.173.17:19:58.81$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.17:19:58.81$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.17:19:58.81$setupk4/!*+20s 2006.173.17:19:59.92#abcon#<5=/14 0.9 2.3 20.271001002.7\r\n> 2006.173.17:19:59.94#abcon#{5=INTERFACE CLEAR} 2006.173.17:20:00.00#abcon#[5=S1D000X0/0*\r\n] 2006.173.17:20:10.09#abcon#<5=/14 0.9 2.3 20.271001002.7\r\n> 2006.173.17:20:10.11#abcon#{5=INTERFACE CLEAR} 2006.173.17:20:10.17#abcon#[5=S1D000X0/0*\r\n] 2006.173.17:20:11.14#trakl#Source acquired 2006.173.17:20:11.15#flagr#flagr/antenna,acquired 2006.173.17:20:13.47$setupk4/"tpicd 2006.173.17:20:13.47$setupk4/echo=off 2006.173.17:20:13.47$setupk4/xlog=off 2006.173.17:20:13.48:!2006.173.17:21:01 2006.173.17:21:01.02:preob 2006.173.17:21:02.15/onsource/TRACKING 2006.173.17:21:02.15:!2006.173.17:21:11 2006.173.17:21:11.01:"tape 2006.173.17:21:11.02:"st=record 2006.173.17:21:11.02:data_valid=on 2006.173.17:21:11.02:midob 2006.173.17:21:12.15/onsource/TRACKING 2006.173.17:21:12.15/wx/20.26,1002.7,100 2006.173.17:21:12.32/cable/+6.5144E-03 2006.173.17:21:13.41/va/01,07,usb,yes,36,39 2006.173.17:21:13.41/va/02,06,usb,yes,36,37 2006.173.17:21:13.41/va/03,05,usb,yes,45,47 2006.173.17:21:13.41/va/04,06,usb,yes,36,38 2006.173.17:21:13.41/va/05,04,usb,yes,29,29 2006.173.17:21:13.41/va/06,03,usb,yes,40,40 2006.173.17:21:13.41/va/07,04,usb,yes,32,34 2006.173.17:21:13.41/va/08,04,usb,yes,28,33 2006.173.17:21:13.64/valo/01,524.99,yes,locked 2006.173.17:21:13.64/valo/02,534.99,yes,locked 2006.173.17:21:13.64/valo/03,564.99,yes,locked 2006.173.17:21:13.64/valo/04,624.99,yes,locked 2006.173.17:21:13.64/valo/05,734.99,yes,locked 2006.173.17:21:13.64/valo/06,814.99,yes,locked 2006.173.17:21:13.64/valo/07,864.99,yes,locked 2006.173.17:21:13.64/valo/08,884.99,yes,locked 2006.173.17:21:14.73/vb/01,04,usb,yes,30,27 2006.173.17:21:14.73/vb/02,04,usb,yes,32,32 2006.173.17:21:14.73/vb/03,04,usb,yes,29,32 2006.173.17:21:14.73/vb/04,04,usb,yes,33,32 2006.173.17:21:14.73/vb/05,04,usb,yes,26,28 2006.173.17:21:14.73/vb/06,04,usb,yes,30,27 2006.173.17:21:14.73/vb/07,04,usb,yes,30,30 2006.173.17:21:14.73/vb/08,04,usb,yes,27,31 2006.173.17:21:14.96/vblo/01,629.99,yes,locked 2006.173.17:21:14.96/vblo/02,634.99,yes,locked 2006.173.17:21:14.96/vblo/03,649.99,yes,locked 2006.173.17:21:14.96/vblo/04,679.99,yes,locked 2006.173.17:21:14.96/vblo/05,709.99,yes,locked 2006.173.17:21:14.96/vblo/06,719.99,yes,locked 2006.173.17:21:14.96/vblo/07,734.99,yes,locked 2006.173.17:21:14.96/vblo/08,744.99,yes,locked 2006.173.17:21:15.11/vabw/8 2006.173.17:21:15.26/vbbw/8 2006.173.17:21:15.35/xfe/off,on,15.2 2006.173.17:21:15.74/ifatt/23,28,28,28 2006.173.17:21:16.07/fmout-gps/S +4.02E-07 2006.173.17:21:16.12:!2006.173.17:22:21 2006.173.17:22:21.01:data_valid=off 2006.173.17:22:21.02:"et 2006.173.17:22:21.02:!+3s 2006.173.17:22:24.05:"tape 2006.173.17:22:24.06:postob 2006.173.17:22:24.21/cable/+6.5146E-03 2006.173.17:22:24.22/wx/20.26,1002.6,100 2006.173.17:22:24.27/fmout-gps/S +4.01E-07 2006.173.17:22:24.28:scan_name=173-1725,jd0606,40 2006.173.17:22:24.28:source=1954-388,195800.00,-384506.4,2000.0,ccw 2006.173.17:22:25.14#flagr#flagr/antenna,new-source 2006.173.17:22:25.15:checkk5 2006.173.17:22:25.56/chk_autoobs//k5ts1/ autoobs is running! 2006.173.17:22:25.96/chk_autoobs//k5ts2/ autoobs is running! 2006.173.17:22:26.36/chk_autoobs//k5ts3/ autoobs is running! 2006.173.17:22:26.76/chk_autoobs//k5ts4/ autoobs is running! 2006.173.17:22:27.15/chk_obsdata//k5ts1/T1731721??a.dat file size is correct (nominal:280MB, actual:276MB). 2006.173.17:22:27.55/chk_obsdata//k5ts2/T1731721??b.dat file size is correct (nominal:280MB, actual:276MB). 2006.173.17:22:27.95/chk_obsdata//k5ts3/T1731721??c.dat file size is correct (nominal:280MB, actual:276MB). 2006.173.17:22:28.36/chk_obsdata//k5ts4/T1731721??d.dat file size is correct (nominal:280MB, actual:276MB). 2006.173.17:22:29.09/k5log//k5ts1_log_newline 2006.173.17:22:29.80/k5log//k5ts2_log_newline 2006.173.17:22:30.51/k5log//k5ts3_log_newline 2006.173.17:22:31.20/k5log//k5ts4_log_newline 2006.173.17:22:31.23/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.17:22:31.23:setupk4=1 2006.173.17:22:31.23$setupk4/echo=on 2006.173.17:22:31.23$setupk4/pcalon 2006.173.17:22:31.23$pcalon/"no phase cal control is implemented here 2006.173.17:22:31.23$setupk4/"tpicd=stop 2006.173.17:22:31.23$setupk4/"rec=synch_on 2006.173.17:22:31.23$setupk4/"rec_mode=128 2006.173.17:22:31.23$setupk4/!* 2006.173.17:22:31.23$setupk4/recpk4 2006.173.17:22:31.23$recpk4/recpatch= 2006.173.17:22:31.24$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.17:22:31.24$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.17:22:31.24$setupk4/vck44 2006.173.17:22:31.24$vck44/valo=1,524.99 2006.173.17:22:31.24#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.17:22:31.24#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.17:22:31.24#ibcon#ireg 17 cls_cnt 0 2006.173.17:22:31.24#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.17:22:31.24#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.17:22:31.24#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.17:22:31.24#ibcon#enter wrdev, iclass 6, count 0 2006.173.17:22:31.24#ibcon#first serial, iclass 6, count 0 2006.173.17:22:31.24#ibcon#enter sib2, iclass 6, count 0 2006.173.17:22:31.24#ibcon#flushed, iclass 6, count 0 2006.173.17:22:31.24#ibcon#about to write, iclass 6, count 0 2006.173.17:22:31.24#ibcon#wrote, iclass 6, count 0 2006.173.17:22:31.24#ibcon#about to read 3, iclass 6, count 0 2006.173.17:22:31.25#ibcon#read 3, iclass 6, count 0 2006.173.17:22:31.25#ibcon#about to read 4, iclass 6, count 0 2006.173.17:22:31.25#ibcon#read 4, iclass 6, count 0 2006.173.17:22:31.25#ibcon#about to read 5, iclass 6, count 0 2006.173.17:22:31.25#ibcon#read 5, iclass 6, count 0 2006.173.17:22:31.25#ibcon#about to read 6, iclass 6, count 0 2006.173.17:22:31.25#ibcon#read 6, iclass 6, count 0 2006.173.17:22:31.25#ibcon#end of sib2, iclass 6, count 0 2006.173.17:22:31.25#ibcon#*mode == 0, iclass 6, count 0 2006.173.17:22:31.25#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.17:22:31.25#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.17:22:31.25#ibcon#*before write, iclass 6, count 0 2006.173.17:22:31.25#ibcon#enter sib2, iclass 6, count 0 2006.173.17:22:31.25#ibcon#flushed, iclass 6, count 0 2006.173.17:22:31.25#ibcon#about to write, iclass 6, count 0 2006.173.17:22:31.25#ibcon#wrote, iclass 6, count 0 2006.173.17:22:31.25#ibcon#about to read 3, iclass 6, count 0 2006.173.17:22:31.30#ibcon#read 3, iclass 6, count 0 2006.173.17:22:31.30#ibcon#about to read 4, iclass 6, count 0 2006.173.17:22:31.30#ibcon#read 4, iclass 6, count 0 2006.173.17:22:31.30#ibcon#about to read 5, iclass 6, count 0 2006.173.17:22:31.30#ibcon#read 5, iclass 6, count 0 2006.173.17:22:31.30#ibcon#about to read 6, iclass 6, count 0 2006.173.17:22:31.30#ibcon#read 6, iclass 6, count 0 2006.173.17:22:31.30#ibcon#end of sib2, iclass 6, count 0 2006.173.17:22:31.30#ibcon#*after write, iclass 6, count 0 2006.173.17:22:31.30#ibcon#*before return 0, iclass 6, count 0 2006.173.17:22:31.30#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.17:22:31.30#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.17:22:31.30#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.17:22:31.30#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.17:22:31.30$vck44/va=1,7 2006.173.17:22:31.30#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.17:22:31.30#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.17:22:31.30#ibcon#ireg 11 cls_cnt 2 2006.173.17:22:31.30#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.17:22:31.30#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.17:22:31.30#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.17:22:31.30#ibcon#enter wrdev, iclass 10, count 2 2006.173.17:22:31.30#ibcon#first serial, iclass 10, count 2 2006.173.17:22:31.30#ibcon#enter sib2, iclass 10, count 2 2006.173.17:22:31.30#ibcon#flushed, iclass 10, count 2 2006.173.17:22:31.30#ibcon#about to write, iclass 10, count 2 2006.173.17:22:31.30#ibcon#wrote, iclass 10, count 2 2006.173.17:22:31.30#ibcon#about to read 3, iclass 10, count 2 2006.173.17:22:31.32#ibcon#read 3, iclass 10, count 2 2006.173.17:22:31.32#ibcon#about to read 4, iclass 10, count 2 2006.173.17:22:31.32#ibcon#read 4, iclass 10, count 2 2006.173.17:22:31.32#ibcon#about to read 5, iclass 10, count 2 2006.173.17:22:31.32#ibcon#read 5, iclass 10, count 2 2006.173.17:22:31.32#ibcon#about to read 6, iclass 10, count 2 2006.173.17:22:31.32#ibcon#read 6, iclass 10, count 2 2006.173.17:22:31.32#ibcon#end of sib2, iclass 10, count 2 2006.173.17:22:31.32#ibcon#*mode == 0, iclass 10, count 2 2006.173.17:22:31.32#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.17:22:31.32#ibcon#[25=AT01-07\r\n] 2006.173.17:22:31.32#ibcon#*before write, iclass 10, count 2 2006.173.17:22:31.32#ibcon#enter sib2, iclass 10, count 2 2006.173.17:22:31.32#ibcon#flushed, iclass 10, count 2 2006.173.17:22:31.32#ibcon#about to write, iclass 10, count 2 2006.173.17:22:31.32#ibcon#wrote, iclass 10, count 2 2006.173.17:22:31.32#ibcon#about to read 3, iclass 10, count 2 2006.173.17:22:31.35#ibcon#read 3, iclass 10, count 2 2006.173.17:22:31.35#ibcon#about to read 4, iclass 10, count 2 2006.173.17:22:31.35#ibcon#read 4, iclass 10, count 2 2006.173.17:22:31.35#ibcon#about to read 5, iclass 10, count 2 2006.173.17:22:31.35#ibcon#read 5, iclass 10, count 2 2006.173.17:22:31.35#ibcon#about to read 6, iclass 10, count 2 2006.173.17:22:31.35#ibcon#read 6, iclass 10, count 2 2006.173.17:22:31.35#ibcon#end of sib2, iclass 10, count 2 2006.173.17:22:31.35#ibcon#*after write, iclass 10, count 2 2006.173.17:22:31.35#ibcon#*before return 0, iclass 10, count 2 2006.173.17:22:31.35#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.17:22:31.35#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.17:22:31.35#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.17:22:31.35#ibcon#ireg 7 cls_cnt 0 2006.173.17:22:31.35#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.17:22:31.47#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.17:22:31.47#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.17:22:31.47#ibcon#enter wrdev, iclass 10, count 0 2006.173.17:22:31.47#ibcon#first serial, iclass 10, count 0 2006.173.17:22:31.47#ibcon#enter sib2, iclass 10, count 0 2006.173.17:22:31.47#ibcon#flushed, iclass 10, count 0 2006.173.17:22:31.47#ibcon#about to write, iclass 10, count 0 2006.173.17:22:31.47#ibcon#wrote, iclass 10, count 0 2006.173.17:22:31.47#ibcon#about to read 3, iclass 10, count 0 2006.173.17:22:31.49#ibcon#read 3, iclass 10, count 0 2006.173.17:22:31.49#ibcon#about to read 4, iclass 10, count 0 2006.173.17:22:31.49#ibcon#read 4, iclass 10, count 0 2006.173.17:22:31.49#ibcon#about to read 5, iclass 10, count 0 2006.173.17:22:31.49#ibcon#read 5, iclass 10, count 0 2006.173.17:22:31.49#ibcon#about to read 6, iclass 10, count 0 2006.173.17:22:31.49#ibcon#read 6, iclass 10, count 0 2006.173.17:22:31.49#ibcon#end of sib2, iclass 10, count 0 2006.173.17:22:31.49#ibcon#*mode == 0, iclass 10, count 0 2006.173.17:22:31.49#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.17:22:31.49#ibcon#[25=USB\r\n] 2006.173.17:22:31.49#ibcon#*before write, iclass 10, count 0 2006.173.17:22:31.49#ibcon#enter sib2, iclass 10, count 0 2006.173.17:22:31.49#ibcon#flushed, iclass 10, count 0 2006.173.17:22:31.49#ibcon#about to write, iclass 10, count 0 2006.173.17:22:31.49#ibcon#wrote, iclass 10, count 0 2006.173.17:22:31.49#ibcon#about to read 3, iclass 10, count 0 2006.173.17:22:31.52#ibcon#read 3, iclass 10, count 0 2006.173.17:22:31.52#ibcon#about to read 4, iclass 10, count 0 2006.173.17:22:31.52#ibcon#read 4, iclass 10, count 0 2006.173.17:22:31.52#ibcon#about to read 5, iclass 10, count 0 2006.173.17:22:31.52#ibcon#read 5, iclass 10, count 0 2006.173.17:22:31.52#ibcon#about to read 6, iclass 10, count 0 2006.173.17:22:31.52#ibcon#read 6, iclass 10, count 0 2006.173.17:22:31.52#ibcon#end of sib2, iclass 10, count 0 2006.173.17:22:31.52#ibcon#*after write, iclass 10, count 0 2006.173.17:22:31.52#ibcon#*before return 0, iclass 10, count 0 2006.173.17:22:31.52#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.17:22:31.52#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.17:22:31.52#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.17:22:31.52#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.17:22:31.52$vck44/valo=2,534.99 2006.173.17:22:31.52#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.17:22:31.52#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.17:22:31.52#ibcon#ireg 17 cls_cnt 0 2006.173.17:22:31.52#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.17:22:31.52#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.17:22:31.52#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.17:22:31.52#ibcon#enter wrdev, iclass 12, count 0 2006.173.17:22:31.52#ibcon#first serial, iclass 12, count 0 2006.173.17:22:31.52#ibcon#enter sib2, iclass 12, count 0 2006.173.17:22:31.52#ibcon#flushed, iclass 12, count 0 2006.173.17:22:31.52#ibcon#about to write, iclass 12, count 0 2006.173.17:22:31.52#ibcon#wrote, iclass 12, count 0 2006.173.17:22:31.52#ibcon#about to read 3, iclass 12, count 0 2006.173.17:22:31.54#ibcon#read 3, iclass 12, count 0 2006.173.17:22:31.54#ibcon#about to read 4, iclass 12, count 0 2006.173.17:22:31.54#ibcon#read 4, iclass 12, count 0 2006.173.17:22:31.54#ibcon#about to read 5, iclass 12, count 0 2006.173.17:22:31.54#ibcon#read 5, iclass 12, count 0 2006.173.17:22:31.54#ibcon#about to read 6, iclass 12, count 0 2006.173.17:22:31.54#ibcon#read 6, iclass 12, count 0 2006.173.17:22:31.54#ibcon#end of sib2, iclass 12, count 0 2006.173.17:22:31.54#ibcon#*mode == 0, iclass 12, count 0 2006.173.17:22:31.54#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.17:22:31.54#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.17:22:31.54#ibcon#*before write, iclass 12, count 0 2006.173.17:22:31.54#ibcon#enter sib2, iclass 12, count 0 2006.173.17:22:31.54#ibcon#flushed, iclass 12, count 0 2006.173.17:22:31.54#ibcon#about to write, iclass 12, count 0 2006.173.17:22:31.54#ibcon#wrote, iclass 12, count 0 2006.173.17:22:31.54#ibcon#about to read 3, iclass 12, count 0 2006.173.17:22:31.58#ibcon#read 3, iclass 12, count 0 2006.173.17:22:31.58#ibcon#about to read 4, iclass 12, count 0 2006.173.17:22:31.58#ibcon#read 4, iclass 12, count 0 2006.173.17:22:31.58#ibcon#about to read 5, iclass 12, count 0 2006.173.17:22:31.58#ibcon#read 5, iclass 12, count 0 2006.173.17:22:31.58#ibcon#about to read 6, iclass 12, count 0 2006.173.17:22:31.58#ibcon#read 6, iclass 12, count 0 2006.173.17:22:31.58#ibcon#end of sib2, iclass 12, count 0 2006.173.17:22:31.58#ibcon#*after write, iclass 12, count 0 2006.173.17:22:31.58#ibcon#*before return 0, iclass 12, count 0 2006.173.17:22:31.58#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.17:22:31.58#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.17:22:31.58#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.17:22:31.58#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.17:22:31.58$vck44/va=2,6 2006.173.17:22:31.58#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.17:22:31.58#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.17:22:31.58#ibcon#ireg 11 cls_cnt 2 2006.173.17:22:31.58#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.17:22:31.64#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.17:22:31.64#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.17:22:31.64#ibcon#enter wrdev, iclass 14, count 2 2006.173.17:22:31.64#ibcon#first serial, iclass 14, count 2 2006.173.17:22:31.64#ibcon#enter sib2, iclass 14, count 2 2006.173.17:22:31.64#ibcon#flushed, iclass 14, count 2 2006.173.17:22:31.64#ibcon#about to write, iclass 14, count 2 2006.173.17:22:31.64#ibcon#wrote, iclass 14, count 2 2006.173.17:22:31.64#ibcon#about to read 3, iclass 14, count 2 2006.173.17:22:31.66#ibcon#read 3, iclass 14, count 2 2006.173.17:22:31.66#ibcon#about to read 4, iclass 14, count 2 2006.173.17:22:31.66#ibcon#read 4, iclass 14, count 2 2006.173.17:22:31.66#ibcon#about to read 5, iclass 14, count 2 2006.173.17:22:31.66#ibcon#read 5, iclass 14, count 2 2006.173.17:22:31.66#ibcon#about to read 6, iclass 14, count 2 2006.173.17:22:31.66#ibcon#read 6, iclass 14, count 2 2006.173.17:22:31.66#ibcon#end of sib2, iclass 14, count 2 2006.173.17:22:31.66#ibcon#*mode == 0, iclass 14, count 2 2006.173.17:22:31.66#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.17:22:31.66#ibcon#[25=AT02-06\r\n] 2006.173.17:22:31.66#ibcon#*before write, iclass 14, count 2 2006.173.17:22:31.66#ibcon#enter sib2, iclass 14, count 2 2006.173.17:22:31.66#ibcon#flushed, iclass 14, count 2 2006.173.17:22:31.66#ibcon#about to write, iclass 14, count 2 2006.173.17:22:31.66#ibcon#wrote, iclass 14, count 2 2006.173.17:22:31.66#ibcon#about to read 3, iclass 14, count 2 2006.173.17:22:31.69#ibcon#read 3, iclass 14, count 2 2006.173.17:22:31.69#ibcon#about to read 4, iclass 14, count 2 2006.173.17:22:31.69#ibcon#read 4, iclass 14, count 2 2006.173.17:22:31.69#ibcon#about to read 5, iclass 14, count 2 2006.173.17:22:31.69#ibcon#read 5, iclass 14, count 2 2006.173.17:22:31.69#ibcon#about to read 6, iclass 14, count 2 2006.173.17:22:31.69#ibcon#read 6, iclass 14, count 2 2006.173.17:22:31.69#ibcon#end of sib2, iclass 14, count 2 2006.173.17:22:31.69#ibcon#*after write, iclass 14, count 2 2006.173.17:22:31.69#ibcon#*before return 0, iclass 14, count 2 2006.173.17:22:31.69#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.17:22:31.69#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.17:22:31.69#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.17:22:31.69#ibcon#ireg 7 cls_cnt 0 2006.173.17:22:31.69#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.17:22:31.81#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.17:22:31.81#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.17:22:31.81#ibcon#enter wrdev, iclass 14, count 0 2006.173.17:22:31.81#ibcon#first serial, iclass 14, count 0 2006.173.17:22:31.81#ibcon#enter sib2, iclass 14, count 0 2006.173.17:22:31.81#ibcon#flushed, iclass 14, count 0 2006.173.17:22:31.81#ibcon#about to write, iclass 14, count 0 2006.173.17:22:31.81#ibcon#wrote, iclass 14, count 0 2006.173.17:22:31.81#ibcon#about to read 3, iclass 14, count 0 2006.173.17:22:31.83#ibcon#read 3, iclass 14, count 0 2006.173.17:22:31.83#ibcon#about to read 4, iclass 14, count 0 2006.173.17:22:31.83#ibcon#read 4, iclass 14, count 0 2006.173.17:22:31.83#ibcon#about to read 5, iclass 14, count 0 2006.173.17:22:31.83#ibcon#read 5, iclass 14, count 0 2006.173.17:22:31.83#ibcon#about to read 6, iclass 14, count 0 2006.173.17:22:31.83#ibcon#read 6, iclass 14, count 0 2006.173.17:22:31.83#ibcon#end of sib2, iclass 14, count 0 2006.173.17:22:31.83#ibcon#*mode == 0, iclass 14, count 0 2006.173.17:22:31.83#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.17:22:31.83#ibcon#[25=USB\r\n] 2006.173.17:22:31.83#ibcon#*before write, iclass 14, count 0 2006.173.17:22:31.83#ibcon#enter sib2, iclass 14, count 0 2006.173.17:22:31.83#ibcon#flushed, iclass 14, count 0 2006.173.17:22:31.83#ibcon#about to write, iclass 14, count 0 2006.173.17:22:31.83#ibcon#wrote, iclass 14, count 0 2006.173.17:22:31.83#ibcon#about to read 3, iclass 14, count 0 2006.173.17:22:31.86#ibcon#read 3, iclass 14, count 0 2006.173.17:22:31.86#ibcon#about to read 4, iclass 14, count 0 2006.173.17:22:31.86#ibcon#read 4, iclass 14, count 0 2006.173.17:22:31.86#ibcon#about to read 5, iclass 14, count 0 2006.173.17:22:31.86#ibcon#read 5, iclass 14, count 0 2006.173.17:22:31.86#ibcon#about to read 6, iclass 14, count 0 2006.173.17:22:31.86#ibcon#read 6, iclass 14, count 0 2006.173.17:22:31.86#ibcon#end of sib2, iclass 14, count 0 2006.173.17:22:31.86#ibcon#*after write, iclass 14, count 0 2006.173.17:22:31.86#ibcon#*before return 0, iclass 14, count 0 2006.173.17:22:31.86#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.17:22:31.86#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.17:22:31.86#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.17:22:31.86#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.17:22:31.86$vck44/valo=3,564.99 2006.173.17:22:31.86#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.17:22:31.86#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.17:22:31.86#ibcon#ireg 17 cls_cnt 0 2006.173.17:22:31.86#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.17:22:31.86#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.17:22:31.86#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.17:22:31.86#ibcon#enter wrdev, iclass 16, count 0 2006.173.17:22:31.86#ibcon#first serial, iclass 16, count 0 2006.173.17:22:31.86#ibcon#enter sib2, iclass 16, count 0 2006.173.17:22:31.86#ibcon#flushed, iclass 16, count 0 2006.173.17:22:31.86#ibcon#about to write, iclass 16, count 0 2006.173.17:22:31.86#ibcon#wrote, iclass 16, count 0 2006.173.17:22:31.86#ibcon#about to read 3, iclass 16, count 0 2006.173.17:22:31.88#ibcon#read 3, iclass 16, count 0 2006.173.17:22:31.88#ibcon#about to read 4, iclass 16, count 0 2006.173.17:22:31.88#ibcon#read 4, iclass 16, count 0 2006.173.17:22:31.88#ibcon#about to read 5, iclass 16, count 0 2006.173.17:22:31.88#ibcon#read 5, iclass 16, count 0 2006.173.17:22:31.88#ibcon#about to read 6, iclass 16, count 0 2006.173.17:22:31.88#ibcon#read 6, iclass 16, count 0 2006.173.17:22:31.88#ibcon#end of sib2, iclass 16, count 0 2006.173.17:22:31.88#ibcon#*mode == 0, iclass 16, count 0 2006.173.17:22:31.88#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.17:22:31.88#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.17:22:31.88#ibcon#*before write, iclass 16, count 0 2006.173.17:22:31.88#ibcon#enter sib2, iclass 16, count 0 2006.173.17:22:31.88#ibcon#flushed, iclass 16, count 0 2006.173.17:22:31.88#ibcon#about to write, iclass 16, count 0 2006.173.17:22:31.88#ibcon#wrote, iclass 16, count 0 2006.173.17:22:31.88#ibcon#about to read 3, iclass 16, count 0 2006.173.17:22:31.92#ibcon#read 3, iclass 16, count 0 2006.173.17:22:31.92#ibcon#about to read 4, iclass 16, count 0 2006.173.17:22:31.92#ibcon#read 4, iclass 16, count 0 2006.173.17:22:31.92#ibcon#about to read 5, iclass 16, count 0 2006.173.17:22:31.92#ibcon#read 5, iclass 16, count 0 2006.173.17:22:31.92#ibcon#about to read 6, iclass 16, count 0 2006.173.17:22:31.92#ibcon#read 6, iclass 16, count 0 2006.173.17:22:31.92#ibcon#end of sib2, iclass 16, count 0 2006.173.17:22:31.92#ibcon#*after write, iclass 16, count 0 2006.173.17:22:31.92#ibcon#*before return 0, iclass 16, count 0 2006.173.17:22:31.92#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.17:22:31.92#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.17:22:31.92#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.17:22:31.92#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.17:22:31.92$vck44/va=3,5 2006.173.17:22:31.92#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.17:22:31.92#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.17:22:31.92#ibcon#ireg 11 cls_cnt 2 2006.173.17:22:31.92#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.17:22:31.98#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.17:22:31.98#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.17:22:31.98#ibcon#enter wrdev, iclass 18, count 2 2006.173.17:22:31.98#ibcon#first serial, iclass 18, count 2 2006.173.17:22:31.98#ibcon#enter sib2, iclass 18, count 2 2006.173.17:22:31.98#ibcon#flushed, iclass 18, count 2 2006.173.17:22:31.98#ibcon#about to write, iclass 18, count 2 2006.173.17:22:31.98#ibcon#wrote, iclass 18, count 2 2006.173.17:22:31.98#ibcon#about to read 3, iclass 18, count 2 2006.173.17:22:32.00#ibcon#read 3, iclass 18, count 2 2006.173.17:22:32.00#ibcon#about to read 4, iclass 18, count 2 2006.173.17:22:32.00#ibcon#read 4, iclass 18, count 2 2006.173.17:22:32.00#ibcon#about to read 5, iclass 18, count 2 2006.173.17:22:32.00#ibcon#read 5, iclass 18, count 2 2006.173.17:22:32.00#ibcon#about to read 6, iclass 18, count 2 2006.173.17:22:32.00#ibcon#read 6, iclass 18, count 2 2006.173.17:22:32.00#ibcon#end of sib2, iclass 18, count 2 2006.173.17:22:32.00#ibcon#*mode == 0, iclass 18, count 2 2006.173.17:22:32.00#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.17:22:32.00#ibcon#[25=AT03-05\r\n] 2006.173.17:22:32.00#ibcon#*before write, iclass 18, count 2 2006.173.17:22:32.00#ibcon#enter sib2, iclass 18, count 2 2006.173.17:22:32.00#ibcon#flushed, iclass 18, count 2 2006.173.17:22:32.00#ibcon#about to write, iclass 18, count 2 2006.173.17:22:32.00#ibcon#wrote, iclass 18, count 2 2006.173.17:22:32.00#ibcon#about to read 3, iclass 18, count 2 2006.173.17:22:32.03#ibcon#read 3, iclass 18, count 2 2006.173.17:22:32.03#ibcon#about to read 4, iclass 18, count 2 2006.173.17:22:32.03#ibcon#read 4, iclass 18, count 2 2006.173.17:22:32.03#ibcon#about to read 5, iclass 18, count 2 2006.173.17:22:32.03#ibcon#read 5, iclass 18, count 2 2006.173.17:22:32.03#ibcon#about to read 6, iclass 18, count 2 2006.173.17:22:32.03#ibcon#read 6, iclass 18, count 2 2006.173.17:22:32.03#ibcon#end of sib2, iclass 18, count 2 2006.173.17:22:32.03#ibcon#*after write, iclass 18, count 2 2006.173.17:22:32.03#ibcon#*before return 0, iclass 18, count 2 2006.173.17:22:32.03#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.17:22:32.03#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.17:22:32.03#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.17:22:32.03#ibcon#ireg 7 cls_cnt 0 2006.173.17:22:32.03#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.17:22:32.15#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.17:22:32.15#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.17:22:32.15#ibcon#enter wrdev, iclass 18, count 0 2006.173.17:22:32.15#ibcon#first serial, iclass 18, count 0 2006.173.17:22:32.15#ibcon#enter sib2, iclass 18, count 0 2006.173.17:22:32.15#ibcon#flushed, iclass 18, count 0 2006.173.17:22:32.15#ibcon#about to write, iclass 18, count 0 2006.173.17:22:32.15#ibcon#wrote, iclass 18, count 0 2006.173.17:22:32.15#ibcon#about to read 3, iclass 18, count 0 2006.173.17:22:32.18#ibcon#read 3, iclass 18, count 0 2006.173.17:22:32.18#ibcon#about to read 4, iclass 18, count 0 2006.173.17:22:32.18#ibcon#read 4, iclass 18, count 0 2006.173.17:22:32.18#ibcon#about to read 5, iclass 18, count 0 2006.173.17:22:32.18#ibcon#read 5, iclass 18, count 0 2006.173.17:22:32.18#ibcon#about to read 6, iclass 18, count 0 2006.173.17:22:32.18#ibcon#read 6, iclass 18, count 0 2006.173.17:22:32.18#ibcon#end of sib2, iclass 18, count 0 2006.173.17:22:32.18#ibcon#*mode == 0, iclass 18, count 0 2006.173.17:22:32.18#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.17:22:32.18#ibcon#[25=USB\r\n] 2006.173.17:22:32.18#ibcon#*before write, iclass 18, count 0 2006.173.17:22:32.18#ibcon#enter sib2, iclass 18, count 0 2006.173.17:22:32.18#ibcon#flushed, iclass 18, count 0 2006.173.17:22:32.18#ibcon#about to write, iclass 18, count 0 2006.173.17:22:32.18#ibcon#wrote, iclass 18, count 0 2006.173.17:22:32.18#ibcon#about to read 3, iclass 18, count 0 2006.173.17:22:32.20#ibcon#read 3, iclass 18, count 0 2006.173.17:22:32.20#ibcon#about to read 4, iclass 18, count 0 2006.173.17:22:32.20#ibcon#read 4, iclass 18, count 0 2006.173.17:22:32.20#ibcon#about to read 5, iclass 18, count 0 2006.173.17:22:32.20#ibcon#read 5, iclass 18, count 0 2006.173.17:22:32.20#ibcon#about to read 6, iclass 18, count 0 2006.173.17:22:32.20#ibcon#read 6, iclass 18, count 0 2006.173.17:22:32.20#ibcon#end of sib2, iclass 18, count 0 2006.173.17:22:32.20#ibcon#*after write, iclass 18, count 0 2006.173.17:22:32.20#ibcon#*before return 0, iclass 18, count 0 2006.173.17:22:32.20#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.17:22:32.20#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.17:22:32.20#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.17:22:32.20#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.17:22:32.20$vck44/valo=4,624.99 2006.173.17:22:32.20#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.17:22:32.20#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.17:22:32.20#ibcon#ireg 17 cls_cnt 0 2006.173.17:22:32.20#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.17:22:32.20#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.17:22:32.20#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.17:22:32.20#ibcon#enter wrdev, iclass 20, count 0 2006.173.17:22:32.20#ibcon#first serial, iclass 20, count 0 2006.173.17:22:32.20#ibcon#enter sib2, iclass 20, count 0 2006.173.17:22:32.20#ibcon#flushed, iclass 20, count 0 2006.173.17:22:32.20#ibcon#about to write, iclass 20, count 0 2006.173.17:22:32.20#ibcon#wrote, iclass 20, count 0 2006.173.17:22:32.20#ibcon#about to read 3, iclass 20, count 0 2006.173.17:22:32.22#ibcon#read 3, iclass 20, count 0 2006.173.17:22:32.22#ibcon#about to read 4, iclass 20, count 0 2006.173.17:22:32.22#ibcon#read 4, iclass 20, count 0 2006.173.17:22:32.22#ibcon#about to read 5, iclass 20, count 0 2006.173.17:22:32.22#ibcon#read 5, iclass 20, count 0 2006.173.17:22:32.22#ibcon#about to read 6, iclass 20, count 0 2006.173.17:22:32.22#ibcon#read 6, iclass 20, count 0 2006.173.17:22:32.22#ibcon#end of sib2, iclass 20, count 0 2006.173.17:22:32.22#ibcon#*mode == 0, iclass 20, count 0 2006.173.17:22:32.22#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.17:22:32.22#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.17:22:32.22#ibcon#*before write, iclass 20, count 0 2006.173.17:22:32.22#ibcon#enter sib2, iclass 20, count 0 2006.173.17:22:32.22#ibcon#flushed, iclass 20, count 0 2006.173.17:22:32.22#ibcon#about to write, iclass 20, count 0 2006.173.17:22:32.22#ibcon#wrote, iclass 20, count 0 2006.173.17:22:32.22#ibcon#about to read 3, iclass 20, count 0 2006.173.17:22:32.26#ibcon#read 3, iclass 20, count 0 2006.173.17:22:32.26#ibcon#about to read 4, iclass 20, count 0 2006.173.17:22:32.26#ibcon#read 4, iclass 20, count 0 2006.173.17:22:32.26#ibcon#about to read 5, iclass 20, count 0 2006.173.17:22:32.26#ibcon#read 5, iclass 20, count 0 2006.173.17:22:32.26#ibcon#about to read 6, iclass 20, count 0 2006.173.17:22:32.26#ibcon#read 6, iclass 20, count 0 2006.173.17:22:32.26#ibcon#end of sib2, iclass 20, count 0 2006.173.17:22:32.26#ibcon#*after write, iclass 20, count 0 2006.173.17:22:32.26#ibcon#*before return 0, iclass 20, count 0 2006.173.17:22:32.26#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.17:22:32.26#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.17:22:32.26#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.17:22:32.26#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.17:22:32.26$vck44/va=4,6 2006.173.17:22:32.26#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.17:22:32.26#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.17:22:32.26#ibcon#ireg 11 cls_cnt 2 2006.173.17:22:32.26#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.17:22:32.32#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.17:22:32.32#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.17:22:32.32#ibcon#enter wrdev, iclass 22, count 2 2006.173.17:22:32.32#ibcon#first serial, iclass 22, count 2 2006.173.17:22:32.32#ibcon#enter sib2, iclass 22, count 2 2006.173.17:22:32.32#ibcon#flushed, iclass 22, count 2 2006.173.17:22:32.32#ibcon#about to write, iclass 22, count 2 2006.173.17:22:32.32#ibcon#wrote, iclass 22, count 2 2006.173.17:22:32.32#ibcon#about to read 3, iclass 22, count 2 2006.173.17:22:32.34#ibcon#read 3, iclass 22, count 2 2006.173.17:22:32.34#ibcon#about to read 4, iclass 22, count 2 2006.173.17:22:32.34#ibcon#read 4, iclass 22, count 2 2006.173.17:22:32.34#ibcon#about to read 5, iclass 22, count 2 2006.173.17:22:32.34#ibcon#read 5, iclass 22, count 2 2006.173.17:22:32.34#ibcon#about to read 6, iclass 22, count 2 2006.173.17:22:32.34#ibcon#read 6, iclass 22, count 2 2006.173.17:22:32.34#ibcon#end of sib2, iclass 22, count 2 2006.173.17:22:32.34#ibcon#*mode == 0, iclass 22, count 2 2006.173.17:22:32.34#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.17:22:32.34#ibcon#[25=AT04-06\r\n] 2006.173.17:22:32.34#ibcon#*before write, iclass 22, count 2 2006.173.17:22:32.34#ibcon#enter sib2, iclass 22, count 2 2006.173.17:22:32.34#ibcon#flushed, iclass 22, count 2 2006.173.17:22:32.34#ibcon#about to write, iclass 22, count 2 2006.173.17:22:32.34#ibcon#wrote, iclass 22, count 2 2006.173.17:22:32.34#ibcon#about to read 3, iclass 22, count 2 2006.173.17:22:32.37#ibcon#read 3, iclass 22, count 2 2006.173.17:22:32.37#ibcon#about to read 4, iclass 22, count 2 2006.173.17:22:32.37#ibcon#read 4, iclass 22, count 2 2006.173.17:22:32.37#ibcon#about to read 5, iclass 22, count 2 2006.173.17:22:32.37#ibcon#read 5, iclass 22, count 2 2006.173.17:22:32.37#ibcon#about to read 6, iclass 22, count 2 2006.173.17:22:32.37#ibcon#read 6, iclass 22, count 2 2006.173.17:22:32.37#ibcon#end of sib2, iclass 22, count 2 2006.173.17:22:32.37#ibcon#*after write, iclass 22, count 2 2006.173.17:22:32.37#ibcon#*before return 0, iclass 22, count 2 2006.173.17:22:32.37#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.17:22:32.37#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.17:22:32.37#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.17:22:32.37#ibcon#ireg 7 cls_cnt 0 2006.173.17:22:32.37#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.17:22:32.47#abcon#<5=/14 1.1 2.6 20.261001002.6\r\n> 2006.173.17:22:32.49#abcon#{5=INTERFACE CLEAR} 2006.173.17:22:32.49#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.17:22:32.49#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.17:22:32.49#ibcon#enter wrdev, iclass 22, count 0 2006.173.17:22:32.49#ibcon#first serial, iclass 22, count 0 2006.173.17:22:32.49#ibcon#enter sib2, iclass 22, count 0 2006.173.17:22:32.49#ibcon#flushed, iclass 22, count 0 2006.173.17:22:32.49#ibcon#about to write, iclass 22, count 0 2006.173.17:22:32.49#ibcon#wrote, iclass 22, count 0 2006.173.17:22:32.49#ibcon#about to read 3, iclass 22, count 0 2006.173.17:22:32.51#ibcon#read 3, iclass 22, count 0 2006.173.17:22:32.51#ibcon#about to read 4, iclass 22, count 0 2006.173.17:22:32.51#ibcon#read 4, iclass 22, count 0 2006.173.17:22:32.51#ibcon#about to read 5, iclass 22, count 0 2006.173.17:22:32.51#ibcon#read 5, iclass 22, count 0 2006.173.17:22:32.51#ibcon#about to read 6, iclass 22, count 0 2006.173.17:22:32.51#ibcon#read 6, iclass 22, count 0 2006.173.17:22:32.51#ibcon#end of sib2, iclass 22, count 0 2006.173.17:22:32.51#ibcon#*mode == 0, iclass 22, count 0 2006.173.17:22:32.51#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.17:22:32.51#ibcon#[25=USB\r\n] 2006.173.17:22:32.51#ibcon#*before write, iclass 22, count 0 2006.173.17:22:32.51#ibcon#enter sib2, iclass 22, count 0 2006.173.17:22:32.51#ibcon#flushed, iclass 22, count 0 2006.173.17:22:32.51#ibcon#about to write, iclass 22, count 0 2006.173.17:22:32.51#ibcon#wrote, iclass 22, count 0 2006.173.17:22:32.51#ibcon#about to read 3, iclass 22, count 0 2006.173.17:22:32.54#ibcon#read 3, iclass 22, count 0 2006.173.17:22:32.54#ibcon#about to read 4, iclass 22, count 0 2006.173.17:22:32.54#ibcon#read 4, iclass 22, count 0 2006.173.17:22:32.54#ibcon#about to read 5, iclass 22, count 0 2006.173.17:22:32.54#ibcon#read 5, iclass 22, count 0 2006.173.17:22:32.54#ibcon#about to read 6, iclass 22, count 0 2006.173.17:22:32.54#ibcon#read 6, iclass 22, count 0 2006.173.17:22:32.54#ibcon#end of sib2, iclass 22, count 0 2006.173.17:22:32.54#ibcon#*after write, iclass 22, count 0 2006.173.17:22:32.54#ibcon#*before return 0, iclass 22, count 0 2006.173.17:22:32.54#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.17:22:32.54#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.17:22:32.54#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.17:22:32.54#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.17:22:32.54$vck44/valo=5,734.99 2006.173.17:22:32.54#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.17:22:32.54#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.17:22:32.54#ibcon#ireg 17 cls_cnt 0 2006.173.17:22:32.54#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.17:22:32.54#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.17:22:32.54#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.17:22:32.54#ibcon#enter wrdev, iclass 28, count 0 2006.173.17:22:32.54#ibcon#first serial, iclass 28, count 0 2006.173.17:22:32.54#ibcon#enter sib2, iclass 28, count 0 2006.173.17:22:32.54#ibcon#flushed, iclass 28, count 0 2006.173.17:22:32.54#ibcon#about to write, iclass 28, count 0 2006.173.17:22:32.54#ibcon#wrote, iclass 28, count 0 2006.173.17:22:32.54#ibcon#about to read 3, iclass 28, count 0 2006.173.17:22:32.55#abcon#[5=S1D000X0/0*\r\n] 2006.173.17:22:32.56#ibcon#read 3, iclass 28, count 0 2006.173.17:22:32.56#ibcon#about to read 4, iclass 28, count 0 2006.173.17:22:32.56#ibcon#read 4, iclass 28, count 0 2006.173.17:22:32.56#ibcon#about to read 5, iclass 28, count 0 2006.173.17:22:32.56#ibcon#read 5, iclass 28, count 0 2006.173.17:22:32.56#ibcon#about to read 6, iclass 28, count 0 2006.173.17:22:32.56#ibcon#read 6, iclass 28, count 0 2006.173.17:22:32.56#ibcon#end of sib2, iclass 28, count 0 2006.173.17:22:32.56#ibcon#*mode == 0, iclass 28, count 0 2006.173.17:22:32.56#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.17:22:32.56#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.17:22:32.56#ibcon#*before write, iclass 28, count 0 2006.173.17:22:32.56#ibcon#enter sib2, iclass 28, count 0 2006.173.17:22:32.56#ibcon#flushed, iclass 28, count 0 2006.173.17:22:32.56#ibcon#about to write, iclass 28, count 0 2006.173.17:22:32.56#ibcon#wrote, iclass 28, count 0 2006.173.17:22:32.56#ibcon#about to read 3, iclass 28, count 0 2006.173.17:22:32.60#ibcon#read 3, iclass 28, count 0 2006.173.17:22:32.60#ibcon#about to read 4, iclass 28, count 0 2006.173.17:22:32.60#ibcon#read 4, iclass 28, count 0 2006.173.17:22:32.60#ibcon#about to read 5, iclass 28, count 0 2006.173.17:22:32.60#ibcon#read 5, iclass 28, count 0 2006.173.17:22:32.60#ibcon#about to read 6, iclass 28, count 0 2006.173.17:22:32.60#ibcon#read 6, iclass 28, count 0 2006.173.17:22:32.60#ibcon#end of sib2, iclass 28, count 0 2006.173.17:22:32.60#ibcon#*after write, iclass 28, count 0 2006.173.17:22:32.60#ibcon#*before return 0, iclass 28, count 0 2006.173.17:22:32.60#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.17:22:32.60#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.17:22:32.60#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.17:22:32.60#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.17:22:32.60$vck44/va=5,4 2006.173.17:22:32.60#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.17:22:32.60#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.17:22:32.60#ibcon#ireg 11 cls_cnt 2 2006.173.17:22:32.60#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.17:22:32.66#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.17:22:32.66#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.17:22:32.66#ibcon#enter wrdev, iclass 30, count 2 2006.173.17:22:32.66#ibcon#first serial, iclass 30, count 2 2006.173.17:22:32.66#ibcon#enter sib2, iclass 30, count 2 2006.173.17:22:32.66#ibcon#flushed, iclass 30, count 2 2006.173.17:22:32.66#ibcon#about to write, iclass 30, count 2 2006.173.17:22:32.66#ibcon#wrote, iclass 30, count 2 2006.173.17:22:32.66#ibcon#about to read 3, iclass 30, count 2 2006.173.17:22:32.68#ibcon#read 3, iclass 30, count 2 2006.173.17:22:32.68#ibcon#about to read 4, iclass 30, count 2 2006.173.17:22:32.68#ibcon#read 4, iclass 30, count 2 2006.173.17:22:32.68#ibcon#about to read 5, iclass 30, count 2 2006.173.17:22:32.68#ibcon#read 5, iclass 30, count 2 2006.173.17:22:32.68#ibcon#about to read 6, iclass 30, count 2 2006.173.17:22:32.68#ibcon#read 6, iclass 30, count 2 2006.173.17:22:32.68#ibcon#end of sib2, iclass 30, count 2 2006.173.17:22:32.68#ibcon#*mode == 0, iclass 30, count 2 2006.173.17:22:32.68#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.17:22:32.68#ibcon#[25=AT05-04\r\n] 2006.173.17:22:32.68#ibcon#*before write, iclass 30, count 2 2006.173.17:22:32.68#ibcon#enter sib2, iclass 30, count 2 2006.173.17:22:32.68#ibcon#flushed, iclass 30, count 2 2006.173.17:22:32.68#ibcon#about to write, iclass 30, count 2 2006.173.17:22:32.68#ibcon#wrote, iclass 30, count 2 2006.173.17:22:32.68#ibcon#about to read 3, iclass 30, count 2 2006.173.17:22:32.71#ibcon#read 3, iclass 30, count 2 2006.173.17:22:32.71#ibcon#about to read 4, iclass 30, count 2 2006.173.17:22:32.71#ibcon#read 4, iclass 30, count 2 2006.173.17:22:32.71#ibcon#about to read 5, iclass 30, count 2 2006.173.17:22:32.71#ibcon#read 5, iclass 30, count 2 2006.173.17:22:32.71#ibcon#about to read 6, iclass 30, count 2 2006.173.17:22:32.71#ibcon#read 6, iclass 30, count 2 2006.173.17:22:32.71#ibcon#end of sib2, iclass 30, count 2 2006.173.17:22:32.71#ibcon#*after write, iclass 30, count 2 2006.173.17:22:32.71#ibcon#*before return 0, iclass 30, count 2 2006.173.17:22:32.71#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.17:22:32.71#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.17:22:32.71#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.17:22:32.71#ibcon#ireg 7 cls_cnt 0 2006.173.17:22:32.71#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.17:22:32.83#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.17:22:32.83#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.17:22:32.83#ibcon#enter wrdev, iclass 30, count 0 2006.173.17:22:32.83#ibcon#first serial, iclass 30, count 0 2006.173.17:22:32.83#ibcon#enter sib2, iclass 30, count 0 2006.173.17:22:32.83#ibcon#flushed, iclass 30, count 0 2006.173.17:22:32.83#ibcon#about to write, iclass 30, count 0 2006.173.17:22:32.83#ibcon#wrote, iclass 30, count 0 2006.173.17:22:32.83#ibcon#about to read 3, iclass 30, count 0 2006.173.17:22:32.85#ibcon#read 3, iclass 30, count 0 2006.173.17:22:32.85#ibcon#about to read 4, iclass 30, count 0 2006.173.17:22:32.85#ibcon#read 4, iclass 30, count 0 2006.173.17:22:32.85#ibcon#about to read 5, iclass 30, count 0 2006.173.17:22:32.85#ibcon#read 5, iclass 30, count 0 2006.173.17:22:32.85#ibcon#about to read 6, iclass 30, count 0 2006.173.17:22:32.85#ibcon#read 6, iclass 30, count 0 2006.173.17:22:32.85#ibcon#end of sib2, iclass 30, count 0 2006.173.17:22:32.85#ibcon#*mode == 0, iclass 30, count 0 2006.173.17:22:32.85#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.17:22:32.85#ibcon#[25=USB\r\n] 2006.173.17:22:32.85#ibcon#*before write, iclass 30, count 0 2006.173.17:22:32.85#ibcon#enter sib2, iclass 30, count 0 2006.173.17:22:32.85#ibcon#flushed, iclass 30, count 0 2006.173.17:22:32.85#ibcon#about to write, iclass 30, count 0 2006.173.17:22:32.85#ibcon#wrote, iclass 30, count 0 2006.173.17:22:32.85#ibcon#about to read 3, iclass 30, count 0 2006.173.17:22:32.88#ibcon#read 3, iclass 30, count 0 2006.173.17:22:32.88#ibcon#about to read 4, iclass 30, count 0 2006.173.17:22:32.88#ibcon#read 4, iclass 30, count 0 2006.173.17:22:32.88#ibcon#about to read 5, iclass 30, count 0 2006.173.17:22:32.88#ibcon#read 5, iclass 30, count 0 2006.173.17:22:32.88#ibcon#about to read 6, iclass 30, count 0 2006.173.17:22:32.88#ibcon#read 6, iclass 30, count 0 2006.173.17:22:32.88#ibcon#end of sib2, iclass 30, count 0 2006.173.17:22:32.88#ibcon#*after write, iclass 30, count 0 2006.173.17:22:32.88#ibcon#*before return 0, iclass 30, count 0 2006.173.17:22:32.88#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.17:22:32.88#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.17:22:32.88#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.17:22:32.88#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.17:22:32.88$vck44/valo=6,814.99 2006.173.17:22:32.88#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.17:22:32.88#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.17:22:32.88#ibcon#ireg 17 cls_cnt 0 2006.173.17:22:32.88#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.17:22:32.88#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.17:22:32.88#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.17:22:32.88#ibcon#enter wrdev, iclass 32, count 0 2006.173.17:22:32.88#ibcon#first serial, iclass 32, count 0 2006.173.17:22:32.88#ibcon#enter sib2, iclass 32, count 0 2006.173.17:22:32.88#ibcon#flushed, iclass 32, count 0 2006.173.17:22:32.88#ibcon#about to write, iclass 32, count 0 2006.173.17:22:32.88#ibcon#wrote, iclass 32, count 0 2006.173.17:22:32.88#ibcon#about to read 3, iclass 32, count 0 2006.173.17:22:32.90#ibcon#read 3, iclass 32, count 0 2006.173.17:22:32.90#ibcon#about to read 4, iclass 32, count 0 2006.173.17:22:32.90#ibcon#read 4, iclass 32, count 0 2006.173.17:22:32.90#ibcon#about to read 5, iclass 32, count 0 2006.173.17:22:32.90#ibcon#read 5, iclass 32, count 0 2006.173.17:22:32.90#ibcon#about to read 6, iclass 32, count 0 2006.173.17:22:32.90#ibcon#read 6, iclass 32, count 0 2006.173.17:22:32.90#ibcon#end of sib2, iclass 32, count 0 2006.173.17:22:32.90#ibcon#*mode == 0, iclass 32, count 0 2006.173.17:22:32.90#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.17:22:32.90#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.17:22:32.90#ibcon#*before write, iclass 32, count 0 2006.173.17:22:32.90#ibcon#enter sib2, iclass 32, count 0 2006.173.17:22:32.90#ibcon#flushed, iclass 32, count 0 2006.173.17:22:32.90#ibcon#about to write, iclass 32, count 0 2006.173.17:22:32.90#ibcon#wrote, iclass 32, count 0 2006.173.17:22:32.90#ibcon#about to read 3, iclass 32, count 0 2006.173.17:22:32.94#ibcon#read 3, iclass 32, count 0 2006.173.17:22:32.94#ibcon#about to read 4, iclass 32, count 0 2006.173.17:22:32.94#ibcon#read 4, iclass 32, count 0 2006.173.17:22:32.94#ibcon#about to read 5, iclass 32, count 0 2006.173.17:22:32.94#ibcon#read 5, iclass 32, count 0 2006.173.17:22:32.94#ibcon#about to read 6, iclass 32, count 0 2006.173.17:22:32.94#ibcon#read 6, iclass 32, count 0 2006.173.17:22:32.94#ibcon#end of sib2, iclass 32, count 0 2006.173.17:22:32.94#ibcon#*after write, iclass 32, count 0 2006.173.17:22:32.94#ibcon#*before return 0, iclass 32, count 0 2006.173.17:22:32.94#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.17:22:32.94#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.17:22:32.94#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.17:22:32.94#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.17:22:32.94$vck44/va=6,3 2006.173.17:22:32.94#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.17:22:32.94#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.17:22:32.94#ibcon#ireg 11 cls_cnt 2 2006.173.17:22:32.94#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.17:22:33.00#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.17:22:33.00#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.17:22:33.00#ibcon#enter wrdev, iclass 34, count 2 2006.173.17:22:33.00#ibcon#first serial, iclass 34, count 2 2006.173.17:22:33.00#ibcon#enter sib2, iclass 34, count 2 2006.173.17:22:33.00#ibcon#flushed, iclass 34, count 2 2006.173.17:22:33.00#ibcon#about to write, iclass 34, count 2 2006.173.17:22:33.00#ibcon#wrote, iclass 34, count 2 2006.173.17:22:33.00#ibcon#about to read 3, iclass 34, count 2 2006.173.17:22:33.02#ibcon#read 3, iclass 34, count 2 2006.173.17:22:33.02#ibcon#about to read 4, iclass 34, count 2 2006.173.17:22:33.02#ibcon#read 4, iclass 34, count 2 2006.173.17:22:33.02#ibcon#about to read 5, iclass 34, count 2 2006.173.17:22:33.02#ibcon#read 5, iclass 34, count 2 2006.173.17:22:33.02#ibcon#about to read 6, iclass 34, count 2 2006.173.17:22:33.02#ibcon#read 6, iclass 34, count 2 2006.173.17:22:33.02#ibcon#end of sib2, iclass 34, count 2 2006.173.17:22:33.02#ibcon#*mode == 0, iclass 34, count 2 2006.173.17:22:33.02#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.17:22:33.02#ibcon#[25=AT06-03\r\n] 2006.173.17:22:33.02#ibcon#*before write, iclass 34, count 2 2006.173.17:22:33.02#ibcon#enter sib2, iclass 34, count 2 2006.173.17:22:33.02#ibcon#flushed, iclass 34, count 2 2006.173.17:22:33.02#ibcon#about to write, iclass 34, count 2 2006.173.17:22:33.02#ibcon#wrote, iclass 34, count 2 2006.173.17:22:33.02#ibcon#about to read 3, iclass 34, count 2 2006.173.17:22:33.05#ibcon#read 3, iclass 34, count 2 2006.173.17:22:33.05#ibcon#about to read 4, iclass 34, count 2 2006.173.17:22:33.05#ibcon#read 4, iclass 34, count 2 2006.173.17:22:33.05#ibcon#about to read 5, iclass 34, count 2 2006.173.17:22:33.05#ibcon#read 5, iclass 34, count 2 2006.173.17:22:33.05#ibcon#about to read 6, iclass 34, count 2 2006.173.17:22:33.05#ibcon#read 6, iclass 34, count 2 2006.173.17:22:33.05#ibcon#end of sib2, iclass 34, count 2 2006.173.17:22:33.05#ibcon#*after write, iclass 34, count 2 2006.173.17:22:33.05#ibcon#*before return 0, iclass 34, count 2 2006.173.17:22:33.05#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.17:22:33.05#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.17:22:33.05#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.17:22:33.05#ibcon#ireg 7 cls_cnt 0 2006.173.17:22:33.05#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.17:22:33.17#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.17:22:33.17#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.17:22:33.17#ibcon#enter wrdev, iclass 34, count 0 2006.173.17:22:33.17#ibcon#first serial, iclass 34, count 0 2006.173.17:22:33.17#ibcon#enter sib2, iclass 34, count 0 2006.173.17:22:33.17#ibcon#flushed, iclass 34, count 0 2006.173.17:22:33.17#ibcon#about to write, iclass 34, count 0 2006.173.17:22:33.17#ibcon#wrote, iclass 34, count 0 2006.173.17:22:33.17#ibcon#about to read 3, iclass 34, count 0 2006.173.17:22:33.19#ibcon#read 3, iclass 34, count 0 2006.173.17:22:33.19#ibcon#about to read 4, iclass 34, count 0 2006.173.17:22:33.19#ibcon#read 4, iclass 34, count 0 2006.173.17:22:33.19#ibcon#about to read 5, iclass 34, count 0 2006.173.17:22:33.19#ibcon#read 5, iclass 34, count 0 2006.173.17:22:33.19#ibcon#about to read 6, iclass 34, count 0 2006.173.17:22:33.19#ibcon#read 6, iclass 34, count 0 2006.173.17:22:33.19#ibcon#end of sib2, iclass 34, count 0 2006.173.17:22:33.19#ibcon#*mode == 0, iclass 34, count 0 2006.173.17:22:33.19#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.17:22:33.19#ibcon#[25=USB\r\n] 2006.173.17:22:33.19#ibcon#*before write, iclass 34, count 0 2006.173.17:22:33.19#ibcon#enter sib2, iclass 34, count 0 2006.173.17:22:33.19#ibcon#flushed, iclass 34, count 0 2006.173.17:22:33.19#ibcon#about to write, iclass 34, count 0 2006.173.17:22:33.19#ibcon#wrote, iclass 34, count 0 2006.173.17:22:33.19#ibcon#about to read 3, iclass 34, count 0 2006.173.17:22:33.22#ibcon#read 3, iclass 34, count 0 2006.173.17:22:33.22#ibcon#about to read 4, iclass 34, count 0 2006.173.17:22:33.22#ibcon#read 4, iclass 34, count 0 2006.173.17:22:33.22#ibcon#about to read 5, iclass 34, count 0 2006.173.17:22:33.22#ibcon#read 5, iclass 34, count 0 2006.173.17:22:33.22#ibcon#about to read 6, iclass 34, count 0 2006.173.17:22:33.22#ibcon#read 6, iclass 34, count 0 2006.173.17:22:33.22#ibcon#end of sib2, iclass 34, count 0 2006.173.17:22:33.22#ibcon#*after write, iclass 34, count 0 2006.173.17:22:33.22#ibcon#*before return 0, iclass 34, count 0 2006.173.17:22:33.22#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.17:22:33.22#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.17:22:33.22#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.17:22:33.22#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.17:22:33.22$vck44/valo=7,864.99 2006.173.17:22:33.22#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.17:22:33.22#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.17:22:33.22#ibcon#ireg 17 cls_cnt 0 2006.173.17:22:33.22#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.17:22:33.22#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.17:22:33.22#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.17:22:33.22#ibcon#enter wrdev, iclass 36, count 0 2006.173.17:22:33.22#ibcon#first serial, iclass 36, count 0 2006.173.17:22:33.22#ibcon#enter sib2, iclass 36, count 0 2006.173.17:22:33.22#ibcon#flushed, iclass 36, count 0 2006.173.17:22:33.22#ibcon#about to write, iclass 36, count 0 2006.173.17:22:33.22#ibcon#wrote, iclass 36, count 0 2006.173.17:22:33.22#ibcon#about to read 3, iclass 36, count 0 2006.173.17:22:33.24#ibcon#read 3, iclass 36, count 0 2006.173.17:22:33.24#ibcon#about to read 4, iclass 36, count 0 2006.173.17:22:33.24#ibcon#read 4, iclass 36, count 0 2006.173.17:22:33.24#ibcon#about to read 5, iclass 36, count 0 2006.173.17:22:33.24#ibcon#read 5, iclass 36, count 0 2006.173.17:22:33.24#ibcon#about to read 6, iclass 36, count 0 2006.173.17:22:33.24#ibcon#read 6, iclass 36, count 0 2006.173.17:22:33.24#ibcon#end of sib2, iclass 36, count 0 2006.173.17:22:33.24#ibcon#*mode == 0, iclass 36, count 0 2006.173.17:22:33.24#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.17:22:33.24#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.17:22:33.24#ibcon#*before write, iclass 36, count 0 2006.173.17:22:33.24#ibcon#enter sib2, iclass 36, count 0 2006.173.17:22:33.24#ibcon#flushed, iclass 36, count 0 2006.173.17:22:33.24#ibcon#about to write, iclass 36, count 0 2006.173.17:22:33.24#ibcon#wrote, iclass 36, count 0 2006.173.17:22:33.24#ibcon#about to read 3, iclass 36, count 0 2006.173.17:22:33.28#ibcon#read 3, iclass 36, count 0 2006.173.17:22:33.28#ibcon#about to read 4, iclass 36, count 0 2006.173.17:22:33.28#ibcon#read 4, iclass 36, count 0 2006.173.17:22:33.28#ibcon#about to read 5, iclass 36, count 0 2006.173.17:22:33.28#ibcon#read 5, iclass 36, count 0 2006.173.17:22:33.28#ibcon#about to read 6, iclass 36, count 0 2006.173.17:22:33.28#ibcon#read 6, iclass 36, count 0 2006.173.17:22:33.28#ibcon#end of sib2, iclass 36, count 0 2006.173.17:22:33.28#ibcon#*after write, iclass 36, count 0 2006.173.17:22:33.28#ibcon#*before return 0, iclass 36, count 0 2006.173.17:22:33.28#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.17:22:33.28#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.17:22:33.28#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.17:22:33.28#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.17:22:33.28$vck44/va=7,4 2006.173.17:22:33.28#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.17:22:33.28#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.17:22:33.28#ibcon#ireg 11 cls_cnt 2 2006.173.17:22:33.28#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.17:22:33.34#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.17:22:33.34#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.17:22:33.34#ibcon#enter wrdev, iclass 38, count 2 2006.173.17:22:33.34#ibcon#first serial, iclass 38, count 2 2006.173.17:22:33.34#ibcon#enter sib2, iclass 38, count 2 2006.173.17:22:33.34#ibcon#flushed, iclass 38, count 2 2006.173.17:22:33.34#ibcon#about to write, iclass 38, count 2 2006.173.17:22:33.34#ibcon#wrote, iclass 38, count 2 2006.173.17:22:33.34#ibcon#about to read 3, iclass 38, count 2 2006.173.17:22:33.36#ibcon#read 3, iclass 38, count 2 2006.173.17:22:33.36#ibcon#about to read 4, iclass 38, count 2 2006.173.17:22:33.36#ibcon#read 4, iclass 38, count 2 2006.173.17:22:33.36#ibcon#about to read 5, iclass 38, count 2 2006.173.17:22:33.36#ibcon#read 5, iclass 38, count 2 2006.173.17:22:33.36#ibcon#about to read 6, iclass 38, count 2 2006.173.17:22:33.36#ibcon#read 6, iclass 38, count 2 2006.173.17:22:33.36#ibcon#end of sib2, iclass 38, count 2 2006.173.17:22:33.36#ibcon#*mode == 0, iclass 38, count 2 2006.173.17:22:33.36#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.17:22:33.36#ibcon#[25=AT07-04\r\n] 2006.173.17:22:33.36#ibcon#*before write, iclass 38, count 2 2006.173.17:22:33.36#ibcon#enter sib2, iclass 38, count 2 2006.173.17:22:33.36#ibcon#flushed, iclass 38, count 2 2006.173.17:22:33.36#ibcon#about to write, iclass 38, count 2 2006.173.17:22:33.36#ibcon#wrote, iclass 38, count 2 2006.173.17:22:33.36#ibcon#about to read 3, iclass 38, count 2 2006.173.17:22:33.39#ibcon#read 3, iclass 38, count 2 2006.173.17:22:33.39#ibcon#about to read 4, iclass 38, count 2 2006.173.17:22:33.39#ibcon#read 4, iclass 38, count 2 2006.173.17:22:33.39#ibcon#about to read 5, iclass 38, count 2 2006.173.17:22:33.39#ibcon#read 5, iclass 38, count 2 2006.173.17:22:33.39#ibcon#about to read 6, iclass 38, count 2 2006.173.17:22:33.39#ibcon#read 6, iclass 38, count 2 2006.173.17:22:33.39#ibcon#end of sib2, iclass 38, count 2 2006.173.17:22:33.39#ibcon#*after write, iclass 38, count 2 2006.173.17:22:33.39#ibcon#*before return 0, iclass 38, count 2 2006.173.17:22:33.39#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.17:22:33.39#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.17:22:33.39#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.17:22:33.39#ibcon#ireg 7 cls_cnt 0 2006.173.17:22:33.39#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.17:22:33.51#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.17:22:33.51#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.17:22:33.51#ibcon#enter wrdev, iclass 38, count 0 2006.173.17:22:33.51#ibcon#first serial, iclass 38, count 0 2006.173.17:22:33.51#ibcon#enter sib2, iclass 38, count 0 2006.173.17:22:33.51#ibcon#flushed, iclass 38, count 0 2006.173.17:22:33.51#ibcon#about to write, iclass 38, count 0 2006.173.17:22:33.51#ibcon#wrote, iclass 38, count 0 2006.173.17:22:33.51#ibcon#about to read 3, iclass 38, count 0 2006.173.17:22:33.53#ibcon#read 3, iclass 38, count 0 2006.173.17:22:33.53#ibcon#about to read 4, iclass 38, count 0 2006.173.17:22:33.53#ibcon#read 4, iclass 38, count 0 2006.173.17:22:33.53#ibcon#about to read 5, iclass 38, count 0 2006.173.17:22:33.53#ibcon#read 5, iclass 38, count 0 2006.173.17:22:33.53#ibcon#about to read 6, iclass 38, count 0 2006.173.17:22:33.53#ibcon#read 6, iclass 38, count 0 2006.173.17:22:33.53#ibcon#end of sib2, iclass 38, count 0 2006.173.17:22:33.53#ibcon#*mode == 0, iclass 38, count 0 2006.173.17:22:33.53#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.17:22:33.53#ibcon#[25=USB\r\n] 2006.173.17:22:33.53#ibcon#*before write, iclass 38, count 0 2006.173.17:22:33.53#ibcon#enter sib2, iclass 38, count 0 2006.173.17:22:33.53#ibcon#flushed, iclass 38, count 0 2006.173.17:22:33.53#ibcon#about to write, iclass 38, count 0 2006.173.17:22:33.53#ibcon#wrote, iclass 38, count 0 2006.173.17:22:33.53#ibcon#about to read 3, iclass 38, count 0 2006.173.17:22:33.56#ibcon#read 3, iclass 38, count 0 2006.173.17:22:33.56#ibcon#about to read 4, iclass 38, count 0 2006.173.17:22:33.56#ibcon#read 4, iclass 38, count 0 2006.173.17:22:33.56#ibcon#about to read 5, iclass 38, count 0 2006.173.17:22:33.56#ibcon#read 5, iclass 38, count 0 2006.173.17:22:33.56#ibcon#about to read 6, iclass 38, count 0 2006.173.17:22:33.56#ibcon#read 6, iclass 38, count 0 2006.173.17:22:33.56#ibcon#end of sib2, iclass 38, count 0 2006.173.17:22:33.56#ibcon#*after write, iclass 38, count 0 2006.173.17:22:33.56#ibcon#*before return 0, iclass 38, count 0 2006.173.17:22:33.56#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.17:22:33.56#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.17:22:33.56#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.17:22:33.56#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.17:22:33.56$vck44/valo=8,884.99 2006.173.17:22:33.56#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.17:22:33.56#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.17:22:33.56#ibcon#ireg 17 cls_cnt 0 2006.173.17:22:33.56#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.17:22:33.56#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.17:22:33.56#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.17:22:33.56#ibcon#enter wrdev, iclass 40, count 0 2006.173.17:22:33.56#ibcon#first serial, iclass 40, count 0 2006.173.17:22:33.56#ibcon#enter sib2, iclass 40, count 0 2006.173.17:22:33.56#ibcon#flushed, iclass 40, count 0 2006.173.17:22:33.56#ibcon#about to write, iclass 40, count 0 2006.173.17:22:33.56#ibcon#wrote, iclass 40, count 0 2006.173.17:22:33.56#ibcon#about to read 3, iclass 40, count 0 2006.173.17:22:33.58#ibcon#read 3, iclass 40, count 0 2006.173.17:22:33.58#ibcon#about to read 4, iclass 40, count 0 2006.173.17:22:33.58#ibcon#read 4, iclass 40, count 0 2006.173.17:22:33.58#ibcon#about to read 5, iclass 40, count 0 2006.173.17:22:33.58#ibcon#read 5, iclass 40, count 0 2006.173.17:22:33.58#ibcon#about to read 6, iclass 40, count 0 2006.173.17:22:33.58#ibcon#read 6, iclass 40, count 0 2006.173.17:22:33.58#ibcon#end of sib2, iclass 40, count 0 2006.173.17:22:33.58#ibcon#*mode == 0, iclass 40, count 0 2006.173.17:22:33.58#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.17:22:33.58#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.17:22:33.58#ibcon#*before write, iclass 40, count 0 2006.173.17:22:33.58#ibcon#enter sib2, iclass 40, count 0 2006.173.17:22:33.58#ibcon#flushed, iclass 40, count 0 2006.173.17:22:33.58#ibcon#about to write, iclass 40, count 0 2006.173.17:22:33.58#ibcon#wrote, iclass 40, count 0 2006.173.17:22:33.58#ibcon#about to read 3, iclass 40, count 0 2006.173.17:22:33.62#ibcon#read 3, iclass 40, count 0 2006.173.17:22:33.62#ibcon#about to read 4, iclass 40, count 0 2006.173.17:22:33.62#ibcon#read 4, iclass 40, count 0 2006.173.17:22:33.62#ibcon#about to read 5, iclass 40, count 0 2006.173.17:22:33.62#ibcon#read 5, iclass 40, count 0 2006.173.17:22:33.62#ibcon#about to read 6, iclass 40, count 0 2006.173.17:22:33.62#ibcon#read 6, iclass 40, count 0 2006.173.17:22:33.62#ibcon#end of sib2, iclass 40, count 0 2006.173.17:22:33.62#ibcon#*after write, iclass 40, count 0 2006.173.17:22:33.62#ibcon#*before return 0, iclass 40, count 0 2006.173.17:22:33.62#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.17:22:33.62#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.17:22:33.62#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.17:22:33.62#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.17:22:33.62$vck44/va=8,4 2006.173.17:22:33.62#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.17:22:33.62#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.17:22:33.62#ibcon#ireg 11 cls_cnt 2 2006.173.17:22:33.62#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.17:22:33.68#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.17:22:33.68#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.17:22:33.68#ibcon#enter wrdev, iclass 4, count 2 2006.173.17:22:33.68#ibcon#first serial, iclass 4, count 2 2006.173.17:22:33.68#ibcon#enter sib2, iclass 4, count 2 2006.173.17:22:33.68#ibcon#flushed, iclass 4, count 2 2006.173.17:22:33.68#ibcon#about to write, iclass 4, count 2 2006.173.17:22:33.68#ibcon#wrote, iclass 4, count 2 2006.173.17:22:33.68#ibcon#about to read 3, iclass 4, count 2 2006.173.17:22:33.70#ibcon#read 3, iclass 4, count 2 2006.173.17:22:33.70#ibcon#about to read 4, iclass 4, count 2 2006.173.17:22:33.70#ibcon#read 4, iclass 4, count 2 2006.173.17:22:33.70#ibcon#about to read 5, iclass 4, count 2 2006.173.17:22:33.70#ibcon#read 5, iclass 4, count 2 2006.173.17:22:33.70#ibcon#about to read 6, iclass 4, count 2 2006.173.17:22:33.70#ibcon#read 6, iclass 4, count 2 2006.173.17:22:33.70#ibcon#end of sib2, iclass 4, count 2 2006.173.17:22:33.70#ibcon#*mode == 0, iclass 4, count 2 2006.173.17:22:33.70#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.17:22:33.70#ibcon#[25=AT08-04\r\n] 2006.173.17:22:33.70#ibcon#*before write, iclass 4, count 2 2006.173.17:22:33.70#ibcon#enter sib2, iclass 4, count 2 2006.173.17:22:33.70#ibcon#flushed, iclass 4, count 2 2006.173.17:22:33.70#ibcon#about to write, iclass 4, count 2 2006.173.17:22:33.70#ibcon#wrote, iclass 4, count 2 2006.173.17:22:33.70#ibcon#about to read 3, iclass 4, count 2 2006.173.17:22:33.73#ibcon#read 3, iclass 4, count 2 2006.173.17:22:33.73#ibcon#about to read 4, iclass 4, count 2 2006.173.17:22:33.73#ibcon#read 4, iclass 4, count 2 2006.173.17:22:33.73#ibcon#about to read 5, iclass 4, count 2 2006.173.17:22:33.73#ibcon#read 5, iclass 4, count 2 2006.173.17:22:33.73#ibcon#about to read 6, iclass 4, count 2 2006.173.17:22:33.73#ibcon#read 6, iclass 4, count 2 2006.173.17:22:33.73#ibcon#end of sib2, iclass 4, count 2 2006.173.17:22:33.73#ibcon#*after write, iclass 4, count 2 2006.173.17:22:33.73#ibcon#*before return 0, iclass 4, count 2 2006.173.17:22:33.73#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.17:22:33.73#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.17:22:33.73#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.17:22:33.73#ibcon#ireg 7 cls_cnt 0 2006.173.17:22:33.73#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.17:22:33.85#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.17:22:33.85#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.17:22:33.85#ibcon#enter wrdev, iclass 4, count 0 2006.173.17:22:33.85#ibcon#first serial, iclass 4, count 0 2006.173.17:22:33.85#ibcon#enter sib2, iclass 4, count 0 2006.173.17:22:33.85#ibcon#flushed, iclass 4, count 0 2006.173.17:22:33.85#ibcon#about to write, iclass 4, count 0 2006.173.17:22:33.85#ibcon#wrote, iclass 4, count 0 2006.173.17:22:33.85#ibcon#about to read 3, iclass 4, count 0 2006.173.17:22:33.87#ibcon#read 3, iclass 4, count 0 2006.173.17:22:33.87#ibcon#about to read 4, iclass 4, count 0 2006.173.17:22:33.87#ibcon#read 4, iclass 4, count 0 2006.173.17:22:33.87#ibcon#about to read 5, iclass 4, count 0 2006.173.17:22:33.87#ibcon#read 5, iclass 4, count 0 2006.173.17:22:33.87#ibcon#about to read 6, iclass 4, count 0 2006.173.17:22:33.87#ibcon#read 6, iclass 4, count 0 2006.173.17:22:33.87#ibcon#end of sib2, iclass 4, count 0 2006.173.17:22:33.87#ibcon#*mode == 0, iclass 4, count 0 2006.173.17:22:33.87#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.17:22:33.87#ibcon#[25=USB\r\n] 2006.173.17:22:33.87#ibcon#*before write, iclass 4, count 0 2006.173.17:22:33.87#ibcon#enter sib2, iclass 4, count 0 2006.173.17:22:33.87#ibcon#flushed, iclass 4, count 0 2006.173.17:22:33.87#ibcon#about to write, iclass 4, count 0 2006.173.17:22:33.87#ibcon#wrote, iclass 4, count 0 2006.173.17:22:33.87#ibcon#about to read 3, iclass 4, count 0 2006.173.17:22:33.90#ibcon#read 3, iclass 4, count 0 2006.173.17:22:33.90#ibcon#about to read 4, iclass 4, count 0 2006.173.17:22:33.90#ibcon#read 4, iclass 4, count 0 2006.173.17:22:33.90#ibcon#about to read 5, iclass 4, count 0 2006.173.17:22:33.90#ibcon#read 5, iclass 4, count 0 2006.173.17:22:33.90#ibcon#about to read 6, iclass 4, count 0 2006.173.17:22:33.90#ibcon#read 6, iclass 4, count 0 2006.173.17:22:33.90#ibcon#end of sib2, iclass 4, count 0 2006.173.17:22:33.90#ibcon#*after write, iclass 4, count 0 2006.173.17:22:33.90#ibcon#*before return 0, iclass 4, count 0 2006.173.17:22:33.90#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.17:22:33.90#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.17:22:33.90#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.17:22:33.90#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.17:22:33.90$vck44/vblo=1,629.99 2006.173.17:22:33.90#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.17:22:33.90#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.17:22:33.90#ibcon#ireg 17 cls_cnt 0 2006.173.17:22:33.90#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.17:22:33.90#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.17:22:33.90#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.17:22:33.90#ibcon#enter wrdev, iclass 6, count 0 2006.173.17:22:33.90#ibcon#first serial, iclass 6, count 0 2006.173.17:22:33.90#ibcon#enter sib2, iclass 6, count 0 2006.173.17:22:33.90#ibcon#flushed, iclass 6, count 0 2006.173.17:22:33.90#ibcon#about to write, iclass 6, count 0 2006.173.17:22:33.90#ibcon#wrote, iclass 6, count 0 2006.173.17:22:33.90#ibcon#about to read 3, iclass 6, count 0 2006.173.17:22:33.92#ibcon#read 3, iclass 6, count 0 2006.173.17:22:33.92#ibcon#about to read 4, iclass 6, count 0 2006.173.17:22:33.92#ibcon#read 4, iclass 6, count 0 2006.173.17:22:33.92#ibcon#about to read 5, iclass 6, count 0 2006.173.17:22:33.92#ibcon#read 5, iclass 6, count 0 2006.173.17:22:33.92#ibcon#about to read 6, iclass 6, count 0 2006.173.17:22:33.92#ibcon#read 6, iclass 6, count 0 2006.173.17:22:33.92#ibcon#end of sib2, iclass 6, count 0 2006.173.17:22:33.92#ibcon#*mode == 0, iclass 6, count 0 2006.173.17:22:33.92#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.17:22:33.92#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.17:22:33.92#ibcon#*before write, iclass 6, count 0 2006.173.17:22:33.92#ibcon#enter sib2, iclass 6, count 0 2006.173.17:22:33.92#ibcon#flushed, iclass 6, count 0 2006.173.17:22:33.92#ibcon#about to write, iclass 6, count 0 2006.173.17:22:33.92#ibcon#wrote, iclass 6, count 0 2006.173.17:22:33.92#ibcon#about to read 3, iclass 6, count 0 2006.173.17:22:33.96#ibcon#read 3, iclass 6, count 0 2006.173.17:22:33.96#ibcon#about to read 4, iclass 6, count 0 2006.173.17:22:33.96#ibcon#read 4, iclass 6, count 0 2006.173.17:22:33.96#ibcon#about to read 5, iclass 6, count 0 2006.173.17:22:33.96#ibcon#read 5, iclass 6, count 0 2006.173.17:22:33.96#ibcon#about to read 6, iclass 6, count 0 2006.173.17:22:33.96#ibcon#read 6, iclass 6, count 0 2006.173.17:22:33.96#ibcon#end of sib2, iclass 6, count 0 2006.173.17:22:33.96#ibcon#*after write, iclass 6, count 0 2006.173.17:22:33.96#ibcon#*before return 0, iclass 6, count 0 2006.173.17:22:33.96#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.17:22:33.96#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.17:22:33.96#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.17:22:33.96#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.17:22:33.96$vck44/vb=1,4 2006.173.17:22:33.96#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.17:22:33.96#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.17:22:33.96#ibcon#ireg 11 cls_cnt 2 2006.173.17:22:33.96#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.17:22:33.96#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.17:22:33.96#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.17:22:33.96#ibcon#enter wrdev, iclass 10, count 2 2006.173.17:22:33.96#ibcon#first serial, iclass 10, count 2 2006.173.17:22:33.96#ibcon#enter sib2, iclass 10, count 2 2006.173.17:22:33.96#ibcon#flushed, iclass 10, count 2 2006.173.17:22:33.96#ibcon#about to write, iclass 10, count 2 2006.173.17:22:33.96#ibcon#wrote, iclass 10, count 2 2006.173.17:22:33.96#ibcon#about to read 3, iclass 10, count 2 2006.173.17:22:33.98#ibcon#read 3, iclass 10, count 2 2006.173.17:22:33.98#ibcon#about to read 4, iclass 10, count 2 2006.173.17:22:33.98#ibcon#read 4, iclass 10, count 2 2006.173.17:22:33.98#ibcon#about to read 5, iclass 10, count 2 2006.173.17:22:33.98#ibcon#read 5, iclass 10, count 2 2006.173.17:22:33.98#ibcon#about to read 6, iclass 10, count 2 2006.173.17:22:33.98#ibcon#read 6, iclass 10, count 2 2006.173.17:22:33.98#ibcon#end of sib2, iclass 10, count 2 2006.173.17:22:33.98#ibcon#*mode == 0, iclass 10, count 2 2006.173.17:22:33.98#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.17:22:33.98#ibcon#[27=AT01-04\r\n] 2006.173.17:22:33.98#ibcon#*before write, iclass 10, count 2 2006.173.17:22:33.98#ibcon#enter sib2, iclass 10, count 2 2006.173.17:22:33.98#ibcon#flushed, iclass 10, count 2 2006.173.17:22:33.98#ibcon#about to write, iclass 10, count 2 2006.173.17:22:33.98#ibcon#wrote, iclass 10, count 2 2006.173.17:22:33.98#ibcon#about to read 3, iclass 10, count 2 2006.173.17:22:34.01#ibcon#read 3, iclass 10, count 2 2006.173.17:22:34.01#ibcon#about to read 4, iclass 10, count 2 2006.173.17:22:34.01#ibcon#read 4, iclass 10, count 2 2006.173.17:22:34.01#ibcon#about to read 5, iclass 10, count 2 2006.173.17:22:34.01#ibcon#read 5, iclass 10, count 2 2006.173.17:22:34.01#ibcon#about to read 6, iclass 10, count 2 2006.173.17:22:34.01#ibcon#read 6, iclass 10, count 2 2006.173.17:22:34.01#ibcon#end of sib2, iclass 10, count 2 2006.173.17:22:34.01#ibcon#*after write, iclass 10, count 2 2006.173.17:22:34.01#ibcon#*before return 0, iclass 10, count 2 2006.173.17:22:34.01#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.17:22:34.01#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.17:22:34.01#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.17:22:34.01#ibcon#ireg 7 cls_cnt 0 2006.173.17:22:34.01#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.17:22:34.13#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.17:22:34.13#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.17:22:34.13#ibcon#enter wrdev, iclass 10, count 0 2006.173.17:22:34.13#ibcon#first serial, iclass 10, count 0 2006.173.17:22:34.13#ibcon#enter sib2, iclass 10, count 0 2006.173.17:22:34.13#ibcon#flushed, iclass 10, count 0 2006.173.17:22:34.13#ibcon#about to write, iclass 10, count 0 2006.173.17:22:34.13#ibcon#wrote, iclass 10, count 0 2006.173.17:22:34.13#ibcon#about to read 3, iclass 10, count 0 2006.173.17:22:34.15#ibcon#read 3, iclass 10, count 0 2006.173.17:22:34.15#ibcon#about to read 4, iclass 10, count 0 2006.173.17:22:34.15#ibcon#read 4, iclass 10, count 0 2006.173.17:22:34.15#ibcon#about to read 5, iclass 10, count 0 2006.173.17:22:34.15#ibcon#read 5, iclass 10, count 0 2006.173.17:22:34.15#ibcon#about to read 6, iclass 10, count 0 2006.173.17:22:34.15#ibcon#read 6, iclass 10, count 0 2006.173.17:22:34.15#ibcon#end of sib2, iclass 10, count 0 2006.173.17:22:34.15#ibcon#*mode == 0, iclass 10, count 0 2006.173.17:22:34.15#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.17:22:34.15#ibcon#[27=USB\r\n] 2006.173.17:22:34.15#ibcon#*before write, iclass 10, count 0 2006.173.17:22:34.15#ibcon#enter sib2, iclass 10, count 0 2006.173.17:22:34.15#ibcon#flushed, iclass 10, count 0 2006.173.17:22:34.15#ibcon#about to write, iclass 10, count 0 2006.173.17:22:34.15#ibcon#wrote, iclass 10, count 0 2006.173.17:22:34.15#ibcon#about to read 3, iclass 10, count 0 2006.173.17:22:34.18#ibcon#read 3, iclass 10, count 0 2006.173.17:22:34.18#ibcon#about to read 4, iclass 10, count 0 2006.173.17:22:34.18#ibcon#read 4, iclass 10, count 0 2006.173.17:22:34.18#ibcon#about to read 5, iclass 10, count 0 2006.173.17:22:34.18#ibcon#read 5, iclass 10, count 0 2006.173.17:22:34.18#ibcon#about to read 6, iclass 10, count 0 2006.173.17:22:34.18#ibcon#read 6, iclass 10, count 0 2006.173.17:22:34.18#ibcon#end of sib2, iclass 10, count 0 2006.173.17:22:34.18#ibcon#*after write, iclass 10, count 0 2006.173.17:22:34.18#ibcon#*before return 0, iclass 10, count 0 2006.173.17:22:34.18#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.17:22:34.18#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.17:22:34.18#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.17:22:34.18#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.17:22:34.18$vck44/vblo=2,634.99 2006.173.17:22:34.18#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.17:22:34.18#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.17:22:34.18#ibcon#ireg 17 cls_cnt 0 2006.173.17:22:34.18#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.17:22:34.18#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.17:22:34.18#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.17:22:34.18#ibcon#enter wrdev, iclass 12, count 0 2006.173.17:22:34.18#ibcon#first serial, iclass 12, count 0 2006.173.17:22:34.18#ibcon#enter sib2, iclass 12, count 0 2006.173.17:22:34.18#ibcon#flushed, iclass 12, count 0 2006.173.17:22:34.18#ibcon#about to write, iclass 12, count 0 2006.173.17:22:34.18#ibcon#wrote, iclass 12, count 0 2006.173.17:22:34.18#ibcon#about to read 3, iclass 12, count 0 2006.173.17:22:34.20#ibcon#read 3, iclass 12, count 0 2006.173.17:22:34.20#ibcon#about to read 4, iclass 12, count 0 2006.173.17:22:34.20#ibcon#read 4, iclass 12, count 0 2006.173.17:22:34.20#ibcon#about to read 5, iclass 12, count 0 2006.173.17:22:34.20#ibcon#read 5, iclass 12, count 0 2006.173.17:22:34.20#ibcon#about to read 6, iclass 12, count 0 2006.173.17:22:34.20#ibcon#read 6, iclass 12, count 0 2006.173.17:22:34.20#ibcon#end of sib2, iclass 12, count 0 2006.173.17:22:34.20#ibcon#*mode == 0, iclass 12, count 0 2006.173.17:22:34.20#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.17:22:34.20#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.17:22:34.20#ibcon#*before write, iclass 12, count 0 2006.173.17:22:34.20#ibcon#enter sib2, iclass 12, count 0 2006.173.17:22:34.20#ibcon#flushed, iclass 12, count 0 2006.173.17:22:34.20#ibcon#about to write, iclass 12, count 0 2006.173.17:22:34.20#ibcon#wrote, iclass 12, count 0 2006.173.17:22:34.20#ibcon#about to read 3, iclass 12, count 0 2006.173.17:22:34.24#ibcon#read 3, iclass 12, count 0 2006.173.17:22:34.24#ibcon#about to read 4, iclass 12, count 0 2006.173.17:22:34.24#ibcon#read 4, iclass 12, count 0 2006.173.17:22:34.24#ibcon#about to read 5, iclass 12, count 0 2006.173.17:22:34.24#ibcon#read 5, iclass 12, count 0 2006.173.17:22:34.24#ibcon#about to read 6, iclass 12, count 0 2006.173.17:22:34.24#ibcon#read 6, iclass 12, count 0 2006.173.17:22:34.24#ibcon#end of sib2, iclass 12, count 0 2006.173.17:22:34.24#ibcon#*after write, iclass 12, count 0 2006.173.17:22:34.24#ibcon#*before return 0, iclass 12, count 0 2006.173.17:22:34.24#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.17:22:34.24#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.17:22:34.24#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.17:22:34.24#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.17:22:34.24$vck44/vb=2,4 2006.173.17:22:34.24#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.17:22:34.24#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.17:22:34.24#ibcon#ireg 11 cls_cnt 2 2006.173.17:22:34.24#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.17:22:34.30#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.17:22:34.30#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.17:22:34.30#ibcon#enter wrdev, iclass 14, count 2 2006.173.17:22:34.30#ibcon#first serial, iclass 14, count 2 2006.173.17:22:34.30#ibcon#enter sib2, iclass 14, count 2 2006.173.17:22:34.30#ibcon#flushed, iclass 14, count 2 2006.173.17:22:34.30#ibcon#about to write, iclass 14, count 2 2006.173.17:22:34.30#ibcon#wrote, iclass 14, count 2 2006.173.17:22:34.30#ibcon#about to read 3, iclass 14, count 2 2006.173.17:22:34.32#ibcon#read 3, iclass 14, count 2 2006.173.17:22:34.32#ibcon#about to read 4, iclass 14, count 2 2006.173.17:22:34.32#ibcon#read 4, iclass 14, count 2 2006.173.17:22:34.32#ibcon#about to read 5, iclass 14, count 2 2006.173.17:22:34.32#ibcon#read 5, iclass 14, count 2 2006.173.17:22:34.32#ibcon#about to read 6, iclass 14, count 2 2006.173.17:22:34.32#ibcon#read 6, iclass 14, count 2 2006.173.17:22:34.32#ibcon#end of sib2, iclass 14, count 2 2006.173.17:22:34.32#ibcon#*mode == 0, iclass 14, count 2 2006.173.17:22:34.32#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.17:22:34.32#ibcon#[27=AT02-04\r\n] 2006.173.17:22:34.32#ibcon#*before write, iclass 14, count 2 2006.173.17:22:34.32#ibcon#enter sib2, iclass 14, count 2 2006.173.17:22:34.32#ibcon#flushed, iclass 14, count 2 2006.173.17:22:34.32#ibcon#about to write, iclass 14, count 2 2006.173.17:22:34.32#ibcon#wrote, iclass 14, count 2 2006.173.17:22:34.32#ibcon#about to read 3, iclass 14, count 2 2006.173.17:22:34.35#ibcon#read 3, iclass 14, count 2 2006.173.17:22:34.35#ibcon#about to read 4, iclass 14, count 2 2006.173.17:22:34.35#ibcon#read 4, iclass 14, count 2 2006.173.17:22:34.35#ibcon#about to read 5, iclass 14, count 2 2006.173.17:22:34.35#ibcon#read 5, iclass 14, count 2 2006.173.17:22:34.35#ibcon#about to read 6, iclass 14, count 2 2006.173.17:22:34.35#ibcon#read 6, iclass 14, count 2 2006.173.17:22:34.35#ibcon#end of sib2, iclass 14, count 2 2006.173.17:22:34.35#ibcon#*after write, iclass 14, count 2 2006.173.17:22:34.35#ibcon#*before return 0, iclass 14, count 2 2006.173.17:22:34.35#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.17:22:34.35#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.17:22:34.35#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.17:22:34.35#ibcon#ireg 7 cls_cnt 0 2006.173.17:22:34.35#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.17:22:34.47#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.17:22:34.47#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.17:22:34.47#ibcon#enter wrdev, iclass 14, count 0 2006.173.17:22:34.47#ibcon#first serial, iclass 14, count 0 2006.173.17:22:34.47#ibcon#enter sib2, iclass 14, count 0 2006.173.17:22:34.47#ibcon#flushed, iclass 14, count 0 2006.173.17:22:34.47#ibcon#about to write, iclass 14, count 0 2006.173.17:22:34.47#ibcon#wrote, iclass 14, count 0 2006.173.17:22:34.47#ibcon#about to read 3, iclass 14, count 0 2006.173.17:22:34.49#ibcon#read 3, iclass 14, count 0 2006.173.17:22:34.49#ibcon#about to read 4, iclass 14, count 0 2006.173.17:22:34.49#ibcon#read 4, iclass 14, count 0 2006.173.17:22:34.49#ibcon#about to read 5, iclass 14, count 0 2006.173.17:22:34.49#ibcon#read 5, iclass 14, count 0 2006.173.17:22:34.49#ibcon#about to read 6, iclass 14, count 0 2006.173.17:22:34.49#ibcon#read 6, iclass 14, count 0 2006.173.17:22:34.49#ibcon#end of sib2, iclass 14, count 0 2006.173.17:22:34.49#ibcon#*mode == 0, iclass 14, count 0 2006.173.17:22:34.49#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.17:22:34.49#ibcon#[27=USB\r\n] 2006.173.17:22:34.49#ibcon#*before write, iclass 14, count 0 2006.173.17:22:34.49#ibcon#enter sib2, iclass 14, count 0 2006.173.17:22:34.49#ibcon#flushed, iclass 14, count 0 2006.173.17:22:34.49#ibcon#about to write, iclass 14, count 0 2006.173.17:22:34.49#ibcon#wrote, iclass 14, count 0 2006.173.17:22:34.49#ibcon#about to read 3, iclass 14, count 0 2006.173.17:22:34.52#ibcon#read 3, iclass 14, count 0 2006.173.17:22:34.52#ibcon#about to read 4, iclass 14, count 0 2006.173.17:22:34.52#ibcon#read 4, iclass 14, count 0 2006.173.17:22:34.52#ibcon#about to read 5, iclass 14, count 0 2006.173.17:22:34.52#ibcon#read 5, iclass 14, count 0 2006.173.17:22:34.52#ibcon#about to read 6, iclass 14, count 0 2006.173.17:22:34.52#ibcon#read 6, iclass 14, count 0 2006.173.17:22:34.52#ibcon#end of sib2, iclass 14, count 0 2006.173.17:22:34.52#ibcon#*after write, iclass 14, count 0 2006.173.17:22:34.52#ibcon#*before return 0, iclass 14, count 0 2006.173.17:22:34.52#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.17:22:34.52#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.17:22:34.52#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.17:22:34.52#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.17:22:34.52$vck44/vblo=3,649.99 2006.173.17:22:34.52#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.17:22:34.52#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.17:22:34.52#ibcon#ireg 17 cls_cnt 0 2006.173.17:22:34.52#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.17:22:34.52#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.17:22:34.52#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.17:22:34.52#ibcon#enter wrdev, iclass 16, count 0 2006.173.17:22:34.52#ibcon#first serial, iclass 16, count 0 2006.173.17:22:34.52#ibcon#enter sib2, iclass 16, count 0 2006.173.17:22:34.52#ibcon#flushed, iclass 16, count 0 2006.173.17:22:34.52#ibcon#about to write, iclass 16, count 0 2006.173.17:22:34.52#ibcon#wrote, iclass 16, count 0 2006.173.17:22:34.52#ibcon#about to read 3, iclass 16, count 0 2006.173.17:22:34.54#ibcon#read 3, iclass 16, count 0 2006.173.17:22:34.54#ibcon#about to read 4, iclass 16, count 0 2006.173.17:22:34.54#ibcon#read 4, iclass 16, count 0 2006.173.17:22:34.54#ibcon#about to read 5, iclass 16, count 0 2006.173.17:22:34.54#ibcon#read 5, iclass 16, count 0 2006.173.17:22:34.54#ibcon#about to read 6, iclass 16, count 0 2006.173.17:22:34.54#ibcon#read 6, iclass 16, count 0 2006.173.17:22:34.54#ibcon#end of sib2, iclass 16, count 0 2006.173.17:22:34.54#ibcon#*mode == 0, iclass 16, count 0 2006.173.17:22:34.54#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.17:22:34.54#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.17:22:34.54#ibcon#*before write, iclass 16, count 0 2006.173.17:22:34.54#ibcon#enter sib2, iclass 16, count 0 2006.173.17:22:34.54#ibcon#flushed, iclass 16, count 0 2006.173.17:22:34.54#ibcon#about to write, iclass 16, count 0 2006.173.17:22:34.54#ibcon#wrote, iclass 16, count 0 2006.173.17:22:34.54#ibcon#about to read 3, iclass 16, count 0 2006.173.17:22:34.58#ibcon#read 3, iclass 16, count 0 2006.173.17:22:34.58#ibcon#about to read 4, iclass 16, count 0 2006.173.17:22:34.58#ibcon#read 4, iclass 16, count 0 2006.173.17:22:34.58#ibcon#about to read 5, iclass 16, count 0 2006.173.17:22:34.58#ibcon#read 5, iclass 16, count 0 2006.173.17:22:34.58#ibcon#about to read 6, iclass 16, count 0 2006.173.17:22:34.58#ibcon#read 6, iclass 16, count 0 2006.173.17:22:34.58#ibcon#end of sib2, iclass 16, count 0 2006.173.17:22:34.58#ibcon#*after write, iclass 16, count 0 2006.173.17:22:34.58#ibcon#*before return 0, iclass 16, count 0 2006.173.17:22:34.58#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.17:22:34.58#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.17:22:34.58#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.17:22:34.58#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.17:22:34.58$vck44/vb=3,4 2006.173.17:22:34.58#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.17:22:34.58#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.17:22:34.58#ibcon#ireg 11 cls_cnt 2 2006.173.17:22:34.58#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.17:22:34.64#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.17:22:34.64#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.17:22:34.64#ibcon#enter wrdev, iclass 18, count 2 2006.173.17:22:34.64#ibcon#first serial, iclass 18, count 2 2006.173.17:22:34.64#ibcon#enter sib2, iclass 18, count 2 2006.173.17:22:34.64#ibcon#flushed, iclass 18, count 2 2006.173.17:22:34.64#ibcon#about to write, iclass 18, count 2 2006.173.17:22:34.64#ibcon#wrote, iclass 18, count 2 2006.173.17:22:34.64#ibcon#about to read 3, iclass 18, count 2 2006.173.17:22:34.66#ibcon#read 3, iclass 18, count 2 2006.173.17:22:34.66#ibcon#about to read 4, iclass 18, count 2 2006.173.17:22:34.66#ibcon#read 4, iclass 18, count 2 2006.173.17:22:34.66#ibcon#about to read 5, iclass 18, count 2 2006.173.17:22:34.66#ibcon#read 5, iclass 18, count 2 2006.173.17:22:34.66#ibcon#about to read 6, iclass 18, count 2 2006.173.17:22:34.66#ibcon#read 6, iclass 18, count 2 2006.173.17:22:34.66#ibcon#end of sib2, iclass 18, count 2 2006.173.17:22:34.66#ibcon#*mode == 0, iclass 18, count 2 2006.173.17:22:34.66#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.17:22:34.66#ibcon#[27=AT03-04\r\n] 2006.173.17:22:34.66#ibcon#*before write, iclass 18, count 2 2006.173.17:22:34.66#ibcon#enter sib2, iclass 18, count 2 2006.173.17:22:34.66#ibcon#flushed, iclass 18, count 2 2006.173.17:22:34.66#ibcon#about to write, iclass 18, count 2 2006.173.17:22:34.66#ibcon#wrote, iclass 18, count 2 2006.173.17:22:34.66#ibcon#about to read 3, iclass 18, count 2 2006.173.17:22:34.69#ibcon#read 3, iclass 18, count 2 2006.173.17:22:34.69#ibcon#about to read 4, iclass 18, count 2 2006.173.17:22:34.69#ibcon#read 4, iclass 18, count 2 2006.173.17:22:34.69#ibcon#about to read 5, iclass 18, count 2 2006.173.17:22:34.69#ibcon#read 5, iclass 18, count 2 2006.173.17:22:34.69#ibcon#about to read 6, iclass 18, count 2 2006.173.17:22:34.69#ibcon#read 6, iclass 18, count 2 2006.173.17:22:34.69#ibcon#end of sib2, iclass 18, count 2 2006.173.17:22:34.69#ibcon#*after write, iclass 18, count 2 2006.173.17:22:34.69#ibcon#*before return 0, iclass 18, count 2 2006.173.17:22:34.69#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.17:22:34.69#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.17:22:34.69#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.17:22:34.69#ibcon#ireg 7 cls_cnt 0 2006.173.17:22:34.69#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.17:22:34.81#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.17:22:34.81#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.17:22:34.81#ibcon#enter wrdev, iclass 18, count 0 2006.173.17:22:34.81#ibcon#first serial, iclass 18, count 0 2006.173.17:22:34.81#ibcon#enter sib2, iclass 18, count 0 2006.173.17:22:34.81#ibcon#flushed, iclass 18, count 0 2006.173.17:22:34.81#ibcon#about to write, iclass 18, count 0 2006.173.17:22:34.81#ibcon#wrote, iclass 18, count 0 2006.173.17:22:34.81#ibcon#about to read 3, iclass 18, count 0 2006.173.17:22:34.83#ibcon#read 3, iclass 18, count 0 2006.173.17:22:34.83#ibcon#about to read 4, iclass 18, count 0 2006.173.17:22:34.83#ibcon#read 4, iclass 18, count 0 2006.173.17:22:34.83#ibcon#about to read 5, iclass 18, count 0 2006.173.17:22:34.83#ibcon#read 5, iclass 18, count 0 2006.173.17:22:34.83#ibcon#about to read 6, iclass 18, count 0 2006.173.17:22:34.83#ibcon#read 6, iclass 18, count 0 2006.173.17:22:34.83#ibcon#end of sib2, iclass 18, count 0 2006.173.17:22:34.83#ibcon#*mode == 0, iclass 18, count 0 2006.173.17:22:34.83#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.17:22:34.83#ibcon#[27=USB\r\n] 2006.173.17:22:34.83#ibcon#*before write, iclass 18, count 0 2006.173.17:22:34.83#ibcon#enter sib2, iclass 18, count 0 2006.173.17:22:34.83#ibcon#flushed, iclass 18, count 0 2006.173.17:22:34.83#ibcon#about to write, iclass 18, count 0 2006.173.17:22:34.83#ibcon#wrote, iclass 18, count 0 2006.173.17:22:34.83#ibcon#about to read 3, iclass 18, count 0 2006.173.17:22:34.86#ibcon#read 3, iclass 18, count 0 2006.173.17:22:34.86#ibcon#about to read 4, iclass 18, count 0 2006.173.17:22:34.86#ibcon#read 4, iclass 18, count 0 2006.173.17:22:34.86#ibcon#about to read 5, iclass 18, count 0 2006.173.17:22:34.86#ibcon#read 5, iclass 18, count 0 2006.173.17:22:34.86#ibcon#about to read 6, iclass 18, count 0 2006.173.17:22:34.86#ibcon#read 6, iclass 18, count 0 2006.173.17:22:34.86#ibcon#end of sib2, iclass 18, count 0 2006.173.17:22:34.86#ibcon#*after write, iclass 18, count 0 2006.173.17:22:34.86#ibcon#*before return 0, iclass 18, count 0 2006.173.17:22:34.86#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.17:22:34.86#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.17:22:34.86#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.17:22:34.86#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.17:22:34.86$vck44/vblo=4,679.99 2006.173.17:22:34.86#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.17:22:34.86#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.17:22:34.86#ibcon#ireg 17 cls_cnt 0 2006.173.17:22:34.86#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.17:22:34.86#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.17:22:34.86#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.17:22:34.86#ibcon#enter wrdev, iclass 20, count 0 2006.173.17:22:34.86#ibcon#first serial, iclass 20, count 0 2006.173.17:22:34.86#ibcon#enter sib2, iclass 20, count 0 2006.173.17:22:34.86#ibcon#flushed, iclass 20, count 0 2006.173.17:22:34.86#ibcon#about to write, iclass 20, count 0 2006.173.17:22:34.86#ibcon#wrote, iclass 20, count 0 2006.173.17:22:34.86#ibcon#about to read 3, iclass 20, count 0 2006.173.17:22:34.88#ibcon#read 3, iclass 20, count 0 2006.173.17:22:34.88#ibcon#about to read 4, iclass 20, count 0 2006.173.17:22:34.88#ibcon#read 4, iclass 20, count 0 2006.173.17:22:34.88#ibcon#about to read 5, iclass 20, count 0 2006.173.17:22:34.88#ibcon#read 5, iclass 20, count 0 2006.173.17:22:34.88#ibcon#about to read 6, iclass 20, count 0 2006.173.17:22:34.88#ibcon#read 6, iclass 20, count 0 2006.173.17:22:34.88#ibcon#end of sib2, iclass 20, count 0 2006.173.17:22:34.88#ibcon#*mode == 0, iclass 20, count 0 2006.173.17:22:34.88#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.17:22:34.88#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.17:22:34.88#ibcon#*before write, iclass 20, count 0 2006.173.17:22:34.88#ibcon#enter sib2, iclass 20, count 0 2006.173.17:22:34.88#ibcon#flushed, iclass 20, count 0 2006.173.17:22:34.88#ibcon#about to write, iclass 20, count 0 2006.173.17:22:34.88#ibcon#wrote, iclass 20, count 0 2006.173.17:22:34.88#ibcon#about to read 3, iclass 20, count 0 2006.173.17:22:34.92#ibcon#read 3, iclass 20, count 0 2006.173.17:22:34.92#ibcon#about to read 4, iclass 20, count 0 2006.173.17:22:34.92#ibcon#read 4, iclass 20, count 0 2006.173.17:22:34.92#ibcon#about to read 5, iclass 20, count 0 2006.173.17:22:34.92#ibcon#read 5, iclass 20, count 0 2006.173.17:22:34.92#ibcon#about to read 6, iclass 20, count 0 2006.173.17:22:34.92#ibcon#read 6, iclass 20, count 0 2006.173.17:22:34.92#ibcon#end of sib2, iclass 20, count 0 2006.173.17:22:34.92#ibcon#*after write, iclass 20, count 0 2006.173.17:22:34.92#ibcon#*before return 0, iclass 20, count 0 2006.173.17:22:34.92#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.17:22:34.92#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.17:22:34.92#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.17:22:34.92#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.17:22:34.92$vck44/vb=4,4 2006.173.17:22:34.92#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.17:22:34.92#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.17:22:34.92#ibcon#ireg 11 cls_cnt 2 2006.173.17:22:34.92#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.17:22:34.98#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.17:22:34.98#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.17:22:34.98#ibcon#enter wrdev, iclass 22, count 2 2006.173.17:22:34.98#ibcon#first serial, iclass 22, count 2 2006.173.17:22:34.98#ibcon#enter sib2, iclass 22, count 2 2006.173.17:22:34.98#ibcon#flushed, iclass 22, count 2 2006.173.17:22:34.98#ibcon#about to write, iclass 22, count 2 2006.173.17:22:34.98#ibcon#wrote, iclass 22, count 2 2006.173.17:22:34.98#ibcon#about to read 3, iclass 22, count 2 2006.173.17:22:35.00#ibcon#read 3, iclass 22, count 2 2006.173.17:22:35.00#ibcon#about to read 4, iclass 22, count 2 2006.173.17:22:35.00#ibcon#read 4, iclass 22, count 2 2006.173.17:22:35.00#ibcon#about to read 5, iclass 22, count 2 2006.173.17:22:35.00#ibcon#read 5, iclass 22, count 2 2006.173.17:22:35.00#ibcon#about to read 6, iclass 22, count 2 2006.173.17:22:35.00#ibcon#read 6, iclass 22, count 2 2006.173.17:22:35.00#ibcon#end of sib2, iclass 22, count 2 2006.173.17:22:35.00#ibcon#*mode == 0, iclass 22, count 2 2006.173.17:22:35.00#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.17:22:35.00#ibcon#[27=AT04-04\r\n] 2006.173.17:22:35.00#ibcon#*before write, iclass 22, count 2 2006.173.17:22:35.00#ibcon#enter sib2, iclass 22, count 2 2006.173.17:22:35.00#ibcon#flushed, iclass 22, count 2 2006.173.17:22:35.00#ibcon#about to write, iclass 22, count 2 2006.173.17:22:35.00#ibcon#wrote, iclass 22, count 2 2006.173.17:22:35.00#ibcon#about to read 3, iclass 22, count 2 2006.173.17:22:35.03#ibcon#read 3, iclass 22, count 2 2006.173.17:22:35.03#ibcon#about to read 4, iclass 22, count 2 2006.173.17:22:35.03#ibcon#read 4, iclass 22, count 2 2006.173.17:22:35.03#ibcon#about to read 5, iclass 22, count 2 2006.173.17:22:35.03#ibcon#read 5, iclass 22, count 2 2006.173.17:22:35.03#ibcon#about to read 6, iclass 22, count 2 2006.173.17:22:35.03#ibcon#read 6, iclass 22, count 2 2006.173.17:22:35.03#ibcon#end of sib2, iclass 22, count 2 2006.173.17:22:35.03#ibcon#*after write, iclass 22, count 2 2006.173.17:22:35.03#ibcon#*before return 0, iclass 22, count 2 2006.173.17:22:35.03#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.17:22:35.03#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.17:22:35.03#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.17:22:35.03#ibcon#ireg 7 cls_cnt 0 2006.173.17:22:35.03#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.17:22:35.15#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.17:22:35.15#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.17:22:35.15#ibcon#enter wrdev, iclass 22, count 0 2006.173.17:22:35.15#ibcon#first serial, iclass 22, count 0 2006.173.17:22:35.15#ibcon#enter sib2, iclass 22, count 0 2006.173.17:22:35.15#ibcon#flushed, iclass 22, count 0 2006.173.17:22:35.15#ibcon#about to write, iclass 22, count 0 2006.173.17:22:35.15#ibcon#wrote, iclass 22, count 0 2006.173.17:22:35.15#ibcon#about to read 3, iclass 22, count 0 2006.173.17:22:35.17#ibcon#read 3, iclass 22, count 0 2006.173.17:22:35.17#ibcon#about to read 4, iclass 22, count 0 2006.173.17:22:35.17#ibcon#read 4, iclass 22, count 0 2006.173.17:22:35.17#ibcon#about to read 5, iclass 22, count 0 2006.173.17:22:35.17#ibcon#read 5, iclass 22, count 0 2006.173.17:22:35.17#ibcon#about to read 6, iclass 22, count 0 2006.173.17:22:35.17#ibcon#read 6, iclass 22, count 0 2006.173.17:22:35.17#ibcon#end of sib2, iclass 22, count 0 2006.173.17:22:35.17#ibcon#*mode == 0, iclass 22, count 0 2006.173.17:22:35.17#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.17:22:35.17#ibcon#[27=USB\r\n] 2006.173.17:22:35.17#ibcon#*before write, iclass 22, count 0 2006.173.17:22:35.17#ibcon#enter sib2, iclass 22, count 0 2006.173.17:22:35.17#ibcon#flushed, iclass 22, count 0 2006.173.17:22:35.17#ibcon#about to write, iclass 22, count 0 2006.173.17:22:35.17#ibcon#wrote, iclass 22, count 0 2006.173.17:22:35.17#ibcon#about to read 3, iclass 22, count 0 2006.173.17:22:35.20#ibcon#read 3, iclass 22, count 0 2006.173.17:22:35.20#ibcon#about to read 4, iclass 22, count 0 2006.173.17:22:35.20#ibcon#read 4, iclass 22, count 0 2006.173.17:22:35.20#ibcon#about to read 5, iclass 22, count 0 2006.173.17:22:35.20#ibcon#read 5, iclass 22, count 0 2006.173.17:22:35.20#ibcon#about to read 6, iclass 22, count 0 2006.173.17:22:35.20#ibcon#read 6, iclass 22, count 0 2006.173.17:22:35.20#ibcon#end of sib2, iclass 22, count 0 2006.173.17:22:35.20#ibcon#*after write, iclass 22, count 0 2006.173.17:22:35.20#ibcon#*before return 0, iclass 22, count 0 2006.173.17:22:35.20#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.17:22:35.20#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.17:22:35.20#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.17:22:35.20#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.17:22:35.20$vck44/vblo=5,709.99 2006.173.17:22:35.20#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.17:22:35.20#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.17:22:35.20#ibcon#ireg 17 cls_cnt 0 2006.173.17:22:35.20#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.17:22:35.20#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.17:22:35.20#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.17:22:35.20#ibcon#enter wrdev, iclass 24, count 0 2006.173.17:22:35.20#ibcon#first serial, iclass 24, count 0 2006.173.17:22:35.20#ibcon#enter sib2, iclass 24, count 0 2006.173.17:22:35.20#ibcon#flushed, iclass 24, count 0 2006.173.17:22:35.20#ibcon#about to write, iclass 24, count 0 2006.173.17:22:35.20#ibcon#wrote, iclass 24, count 0 2006.173.17:22:35.20#ibcon#about to read 3, iclass 24, count 0 2006.173.17:22:35.22#ibcon#read 3, iclass 24, count 0 2006.173.17:22:35.22#ibcon#about to read 4, iclass 24, count 0 2006.173.17:22:35.22#ibcon#read 4, iclass 24, count 0 2006.173.17:22:35.22#ibcon#about to read 5, iclass 24, count 0 2006.173.17:22:35.22#ibcon#read 5, iclass 24, count 0 2006.173.17:22:35.22#ibcon#about to read 6, iclass 24, count 0 2006.173.17:22:35.22#ibcon#read 6, iclass 24, count 0 2006.173.17:22:35.22#ibcon#end of sib2, iclass 24, count 0 2006.173.17:22:35.22#ibcon#*mode == 0, iclass 24, count 0 2006.173.17:22:35.22#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.17:22:35.22#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.17:22:35.22#ibcon#*before write, iclass 24, count 0 2006.173.17:22:35.22#ibcon#enter sib2, iclass 24, count 0 2006.173.17:22:35.22#ibcon#flushed, iclass 24, count 0 2006.173.17:22:35.22#ibcon#about to write, iclass 24, count 0 2006.173.17:22:35.22#ibcon#wrote, iclass 24, count 0 2006.173.17:22:35.22#ibcon#about to read 3, iclass 24, count 0 2006.173.17:22:35.26#ibcon#read 3, iclass 24, count 0 2006.173.17:22:35.26#ibcon#about to read 4, iclass 24, count 0 2006.173.17:22:35.26#ibcon#read 4, iclass 24, count 0 2006.173.17:22:35.26#ibcon#about to read 5, iclass 24, count 0 2006.173.17:22:35.26#ibcon#read 5, iclass 24, count 0 2006.173.17:22:35.26#ibcon#about to read 6, iclass 24, count 0 2006.173.17:22:35.26#ibcon#read 6, iclass 24, count 0 2006.173.17:22:35.26#ibcon#end of sib2, iclass 24, count 0 2006.173.17:22:35.26#ibcon#*after write, iclass 24, count 0 2006.173.17:22:35.26#ibcon#*before return 0, iclass 24, count 0 2006.173.17:22:35.26#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.17:22:35.26#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.17:22:35.26#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.17:22:35.26#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.17:22:35.26$vck44/vb=5,4 2006.173.17:22:35.26#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.17:22:35.26#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.17:22:35.26#ibcon#ireg 11 cls_cnt 2 2006.173.17:22:35.26#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.17:22:35.32#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.17:22:35.32#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.17:22:35.32#ibcon#enter wrdev, iclass 26, count 2 2006.173.17:22:35.32#ibcon#first serial, iclass 26, count 2 2006.173.17:22:35.32#ibcon#enter sib2, iclass 26, count 2 2006.173.17:22:35.32#ibcon#flushed, iclass 26, count 2 2006.173.17:22:35.32#ibcon#about to write, iclass 26, count 2 2006.173.17:22:35.32#ibcon#wrote, iclass 26, count 2 2006.173.17:22:35.32#ibcon#about to read 3, iclass 26, count 2 2006.173.17:22:35.34#ibcon#read 3, iclass 26, count 2 2006.173.17:22:35.34#ibcon#about to read 4, iclass 26, count 2 2006.173.17:22:35.34#ibcon#read 4, iclass 26, count 2 2006.173.17:22:35.34#ibcon#about to read 5, iclass 26, count 2 2006.173.17:22:35.34#ibcon#read 5, iclass 26, count 2 2006.173.17:22:35.34#ibcon#about to read 6, iclass 26, count 2 2006.173.17:22:35.34#ibcon#read 6, iclass 26, count 2 2006.173.17:22:35.34#ibcon#end of sib2, iclass 26, count 2 2006.173.17:22:35.34#ibcon#*mode == 0, iclass 26, count 2 2006.173.17:22:35.34#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.17:22:35.34#ibcon#[27=AT05-04\r\n] 2006.173.17:22:35.34#ibcon#*before write, iclass 26, count 2 2006.173.17:22:35.34#ibcon#enter sib2, iclass 26, count 2 2006.173.17:22:35.34#ibcon#flushed, iclass 26, count 2 2006.173.17:22:35.34#ibcon#about to write, iclass 26, count 2 2006.173.17:22:35.34#ibcon#wrote, iclass 26, count 2 2006.173.17:22:35.34#ibcon#about to read 3, iclass 26, count 2 2006.173.17:22:35.37#ibcon#read 3, iclass 26, count 2 2006.173.17:22:35.37#ibcon#about to read 4, iclass 26, count 2 2006.173.17:22:35.37#ibcon#read 4, iclass 26, count 2 2006.173.17:22:35.37#ibcon#about to read 5, iclass 26, count 2 2006.173.17:22:35.37#ibcon#read 5, iclass 26, count 2 2006.173.17:22:35.37#ibcon#about to read 6, iclass 26, count 2 2006.173.17:22:35.37#ibcon#read 6, iclass 26, count 2 2006.173.17:22:35.37#ibcon#end of sib2, iclass 26, count 2 2006.173.17:22:35.37#ibcon#*after write, iclass 26, count 2 2006.173.17:22:35.37#ibcon#*before return 0, iclass 26, count 2 2006.173.17:22:35.37#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.17:22:35.37#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.17:22:35.37#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.17:22:35.37#ibcon#ireg 7 cls_cnt 0 2006.173.17:22:35.37#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.17:22:35.49#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.17:22:35.49#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.17:22:35.49#ibcon#enter wrdev, iclass 26, count 0 2006.173.17:22:35.49#ibcon#first serial, iclass 26, count 0 2006.173.17:22:35.49#ibcon#enter sib2, iclass 26, count 0 2006.173.17:22:35.49#ibcon#flushed, iclass 26, count 0 2006.173.17:22:35.49#ibcon#about to write, iclass 26, count 0 2006.173.17:22:35.49#ibcon#wrote, iclass 26, count 0 2006.173.17:22:35.49#ibcon#about to read 3, iclass 26, count 0 2006.173.17:22:35.51#ibcon#read 3, iclass 26, count 0 2006.173.17:22:35.51#ibcon#about to read 4, iclass 26, count 0 2006.173.17:22:35.51#ibcon#read 4, iclass 26, count 0 2006.173.17:22:35.51#ibcon#about to read 5, iclass 26, count 0 2006.173.17:22:35.51#ibcon#read 5, iclass 26, count 0 2006.173.17:22:35.51#ibcon#about to read 6, iclass 26, count 0 2006.173.17:22:35.51#ibcon#read 6, iclass 26, count 0 2006.173.17:22:35.51#ibcon#end of sib2, iclass 26, count 0 2006.173.17:22:35.51#ibcon#*mode == 0, iclass 26, count 0 2006.173.17:22:35.51#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.17:22:35.51#ibcon#[27=USB\r\n] 2006.173.17:22:35.51#ibcon#*before write, iclass 26, count 0 2006.173.17:22:35.51#ibcon#enter sib2, iclass 26, count 0 2006.173.17:22:35.51#ibcon#flushed, iclass 26, count 0 2006.173.17:22:35.51#ibcon#about to write, iclass 26, count 0 2006.173.17:22:35.51#ibcon#wrote, iclass 26, count 0 2006.173.17:22:35.51#ibcon#about to read 3, iclass 26, count 0 2006.173.17:22:35.54#ibcon#read 3, iclass 26, count 0 2006.173.17:22:35.54#ibcon#about to read 4, iclass 26, count 0 2006.173.17:22:35.54#ibcon#read 4, iclass 26, count 0 2006.173.17:22:35.54#ibcon#about to read 5, iclass 26, count 0 2006.173.17:22:35.54#ibcon#read 5, iclass 26, count 0 2006.173.17:22:35.54#ibcon#about to read 6, iclass 26, count 0 2006.173.17:22:35.54#ibcon#read 6, iclass 26, count 0 2006.173.17:22:35.54#ibcon#end of sib2, iclass 26, count 0 2006.173.17:22:35.54#ibcon#*after write, iclass 26, count 0 2006.173.17:22:35.54#ibcon#*before return 0, iclass 26, count 0 2006.173.17:22:35.54#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.17:22:35.54#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.17:22:35.54#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.17:22:35.54#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.17:22:35.54$vck44/vblo=6,719.99 2006.173.17:22:35.54#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.17:22:35.54#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.17:22:35.54#ibcon#ireg 17 cls_cnt 0 2006.173.17:22:35.54#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.17:22:35.54#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.17:22:35.54#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.17:22:35.54#ibcon#enter wrdev, iclass 28, count 0 2006.173.17:22:35.54#ibcon#first serial, iclass 28, count 0 2006.173.17:22:35.54#ibcon#enter sib2, iclass 28, count 0 2006.173.17:22:35.54#ibcon#flushed, iclass 28, count 0 2006.173.17:22:35.54#ibcon#about to write, iclass 28, count 0 2006.173.17:22:35.54#ibcon#wrote, iclass 28, count 0 2006.173.17:22:35.54#ibcon#about to read 3, iclass 28, count 0 2006.173.17:22:35.56#ibcon#read 3, iclass 28, count 0 2006.173.17:22:35.56#ibcon#about to read 4, iclass 28, count 0 2006.173.17:22:35.56#ibcon#read 4, iclass 28, count 0 2006.173.17:22:35.56#ibcon#about to read 5, iclass 28, count 0 2006.173.17:22:35.56#ibcon#read 5, iclass 28, count 0 2006.173.17:22:35.56#ibcon#about to read 6, iclass 28, count 0 2006.173.17:22:35.56#ibcon#read 6, iclass 28, count 0 2006.173.17:22:35.56#ibcon#end of sib2, iclass 28, count 0 2006.173.17:22:35.56#ibcon#*mode == 0, iclass 28, count 0 2006.173.17:22:35.56#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.17:22:35.56#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.17:22:35.56#ibcon#*before write, iclass 28, count 0 2006.173.17:22:35.56#ibcon#enter sib2, iclass 28, count 0 2006.173.17:22:35.56#ibcon#flushed, iclass 28, count 0 2006.173.17:22:35.56#ibcon#about to write, iclass 28, count 0 2006.173.17:22:35.56#ibcon#wrote, iclass 28, count 0 2006.173.17:22:35.56#ibcon#about to read 3, iclass 28, count 0 2006.173.17:22:35.60#ibcon#read 3, iclass 28, count 0 2006.173.17:22:35.60#ibcon#about to read 4, iclass 28, count 0 2006.173.17:22:35.60#ibcon#read 4, iclass 28, count 0 2006.173.17:22:35.60#ibcon#about to read 5, iclass 28, count 0 2006.173.17:22:35.60#ibcon#read 5, iclass 28, count 0 2006.173.17:22:35.60#ibcon#about to read 6, iclass 28, count 0 2006.173.17:22:35.60#ibcon#read 6, iclass 28, count 0 2006.173.17:22:35.60#ibcon#end of sib2, iclass 28, count 0 2006.173.17:22:35.60#ibcon#*after write, iclass 28, count 0 2006.173.17:22:35.60#ibcon#*before return 0, iclass 28, count 0 2006.173.17:22:35.60#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.17:22:35.60#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.17:22:35.60#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.17:22:35.60#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.17:22:35.60$vck44/vb=6,4 2006.173.17:22:35.60#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.17:22:35.60#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.17:22:35.60#ibcon#ireg 11 cls_cnt 2 2006.173.17:22:35.60#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.17:22:35.66#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.17:22:35.66#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.17:22:35.66#ibcon#enter wrdev, iclass 30, count 2 2006.173.17:22:35.66#ibcon#first serial, iclass 30, count 2 2006.173.17:22:35.66#ibcon#enter sib2, iclass 30, count 2 2006.173.17:22:35.66#ibcon#flushed, iclass 30, count 2 2006.173.17:22:35.66#ibcon#about to write, iclass 30, count 2 2006.173.17:22:35.66#ibcon#wrote, iclass 30, count 2 2006.173.17:22:35.66#ibcon#about to read 3, iclass 30, count 2 2006.173.17:22:35.68#ibcon#read 3, iclass 30, count 2 2006.173.17:22:35.68#ibcon#about to read 4, iclass 30, count 2 2006.173.17:22:35.68#ibcon#read 4, iclass 30, count 2 2006.173.17:22:35.68#ibcon#about to read 5, iclass 30, count 2 2006.173.17:22:35.68#ibcon#read 5, iclass 30, count 2 2006.173.17:22:35.68#ibcon#about to read 6, iclass 30, count 2 2006.173.17:22:35.68#ibcon#read 6, iclass 30, count 2 2006.173.17:22:35.68#ibcon#end of sib2, iclass 30, count 2 2006.173.17:22:35.68#ibcon#*mode == 0, iclass 30, count 2 2006.173.17:22:35.68#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.17:22:35.68#ibcon#[27=AT06-04\r\n] 2006.173.17:22:35.68#ibcon#*before write, iclass 30, count 2 2006.173.17:22:35.68#ibcon#enter sib2, iclass 30, count 2 2006.173.17:22:35.68#ibcon#flushed, iclass 30, count 2 2006.173.17:22:35.68#ibcon#about to write, iclass 30, count 2 2006.173.17:22:35.68#ibcon#wrote, iclass 30, count 2 2006.173.17:22:35.68#ibcon#about to read 3, iclass 30, count 2 2006.173.17:22:35.71#ibcon#read 3, iclass 30, count 2 2006.173.17:22:35.71#ibcon#about to read 4, iclass 30, count 2 2006.173.17:22:35.71#ibcon#read 4, iclass 30, count 2 2006.173.17:22:35.71#ibcon#about to read 5, iclass 30, count 2 2006.173.17:22:35.71#ibcon#read 5, iclass 30, count 2 2006.173.17:22:35.71#ibcon#about to read 6, iclass 30, count 2 2006.173.17:22:35.71#ibcon#read 6, iclass 30, count 2 2006.173.17:22:35.71#ibcon#end of sib2, iclass 30, count 2 2006.173.17:22:35.71#ibcon#*after write, iclass 30, count 2 2006.173.17:22:35.71#ibcon#*before return 0, iclass 30, count 2 2006.173.17:22:35.71#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.17:22:35.71#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.17:22:35.71#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.17:22:35.71#ibcon#ireg 7 cls_cnt 0 2006.173.17:22:35.71#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.17:22:35.83#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.17:22:35.83#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.17:22:35.83#ibcon#enter wrdev, iclass 30, count 0 2006.173.17:22:35.83#ibcon#first serial, iclass 30, count 0 2006.173.17:22:35.83#ibcon#enter sib2, iclass 30, count 0 2006.173.17:22:35.83#ibcon#flushed, iclass 30, count 0 2006.173.17:22:35.83#ibcon#about to write, iclass 30, count 0 2006.173.17:22:35.83#ibcon#wrote, iclass 30, count 0 2006.173.17:22:35.83#ibcon#about to read 3, iclass 30, count 0 2006.173.17:22:35.85#ibcon#read 3, iclass 30, count 0 2006.173.17:22:35.85#ibcon#about to read 4, iclass 30, count 0 2006.173.17:22:35.85#ibcon#read 4, iclass 30, count 0 2006.173.17:22:35.85#ibcon#about to read 5, iclass 30, count 0 2006.173.17:22:35.85#ibcon#read 5, iclass 30, count 0 2006.173.17:22:35.85#ibcon#about to read 6, iclass 30, count 0 2006.173.17:22:35.85#ibcon#read 6, iclass 30, count 0 2006.173.17:22:35.85#ibcon#end of sib2, iclass 30, count 0 2006.173.17:22:35.85#ibcon#*mode == 0, iclass 30, count 0 2006.173.17:22:35.85#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.17:22:35.85#ibcon#[27=USB\r\n] 2006.173.17:22:35.85#ibcon#*before write, iclass 30, count 0 2006.173.17:22:35.85#ibcon#enter sib2, iclass 30, count 0 2006.173.17:22:35.85#ibcon#flushed, iclass 30, count 0 2006.173.17:22:35.85#ibcon#about to write, iclass 30, count 0 2006.173.17:22:35.85#ibcon#wrote, iclass 30, count 0 2006.173.17:22:35.85#ibcon#about to read 3, iclass 30, count 0 2006.173.17:22:35.88#ibcon#read 3, iclass 30, count 0 2006.173.17:22:35.88#ibcon#about to read 4, iclass 30, count 0 2006.173.17:22:35.88#ibcon#read 4, iclass 30, count 0 2006.173.17:22:35.88#ibcon#about to read 5, iclass 30, count 0 2006.173.17:22:35.88#ibcon#read 5, iclass 30, count 0 2006.173.17:22:35.88#ibcon#about to read 6, iclass 30, count 0 2006.173.17:22:35.88#ibcon#read 6, iclass 30, count 0 2006.173.17:22:35.88#ibcon#end of sib2, iclass 30, count 0 2006.173.17:22:35.88#ibcon#*after write, iclass 30, count 0 2006.173.17:22:35.88#ibcon#*before return 0, iclass 30, count 0 2006.173.17:22:35.88#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.17:22:35.88#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.17:22:35.88#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.17:22:35.88#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.17:22:35.88$vck44/vblo=7,734.99 2006.173.17:22:35.88#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.17:22:35.88#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.17:22:35.88#ibcon#ireg 17 cls_cnt 0 2006.173.17:22:35.88#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.17:22:35.88#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.17:22:35.88#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.17:22:35.88#ibcon#enter wrdev, iclass 32, count 0 2006.173.17:22:35.88#ibcon#first serial, iclass 32, count 0 2006.173.17:22:35.88#ibcon#enter sib2, iclass 32, count 0 2006.173.17:22:35.88#ibcon#flushed, iclass 32, count 0 2006.173.17:22:35.88#ibcon#about to write, iclass 32, count 0 2006.173.17:22:35.88#ibcon#wrote, iclass 32, count 0 2006.173.17:22:35.88#ibcon#about to read 3, iclass 32, count 0 2006.173.17:22:35.90#ibcon#read 3, iclass 32, count 0 2006.173.17:22:35.90#ibcon#about to read 4, iclass 32, count 0 2006.173.17:22:35.90#ibcon#read 4, iclass 32, count 0 2006.173.17:22:35.90#ibcon#about to read 5, iclass 32, count 0 2006.173.17:22:35.90#ibcon#read 5, iclass 32, count 0 2006.173.17:22:35.90#ibcon#about to read 6, iclass 32, count 0 2006.173.17:22:35.90#ibcon#read 6, iclass 32, count 0 2006.173.17:22:35.90#ibcon#end of sib2, iclass 32, count 0 2006.173.17:22:35.90#ibcon#*mode == 0, iclass 32, count 0 2006.173.17:22:35.90#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.17:22:35.90#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.17:22:35.90#ibcon#*before write, iclass 32, count 0 2006.173.17:22:35.90#ibcon#enter sib2, iclass 32, count 0 2006.173.17:22:35.90#ibcon#flushed, iclass 32, count 0 2006.173.17:22:35.90#ibcon#about to write, iclass 32, count 0 2006.173.17:22:35.90#ibcon#wrote, iclass 32, count 0 2006.173.17:22:35.90#ibcon#about to read 3, iclass 32, count 0 2006.173.17:22:35.94#ibcon#read 3, iclass 32, count 0 2006.173.17:22:35.94#ibcon#about to read 4, iclass 32, count 0 2006.173.17:22:35.94#ibcon#read 4, iclass 32, count 0 2006.173.17:22:35.94#ibcon#about to read 5, iclass 32, count 0 2006.173.17:22:35.94#ibcon#read 5, iclass 32, count 0 2006.173.17:22:35.94#ibcon#about to read 6, iclass 32, count 0 2006.173.17:22:35.94#ibcon#read 6, iclass 32, count 0 2006.173.17:22:35.94#ibcon#end of sib2, iclass 32, count 0 2006.173.17:22:35.94#ibcon#*after write, iclass 32, count 0 2006.173.17:22:35.94#ibcon#*before return 0, iclass 32, count 0 2006.173.17:22:35.94#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.17:22:35.94#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.17:22:35.94#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.17:22:35.94#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.17:22:35.94$vck44/vb=7,4 2006.173.17:22:35.94#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.17:22:35.94#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.17:22:35.94#ibcon#ireg 11 cls_cnt 2 2006.173.17:22:35.94#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.17:22:36.00#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.17:22:36.00#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.17:22:36.00#ibcon#enter wrdev, iclass 34, count 2 2006.173.17:22:36.00#ibcon#first serial, iclass 34, count 2 2006.173.17:22:36.00#ibcon#enter sib2, iclass 34, count 2 2006.173.17:22:36.00#ibcon#flushed, iclass 34, count 2 2006.173.17:22:36.00#ibcon#about to write, iclass 34, count 2 2006.173.17:22:36.00#ibcon#wrote, iclass 34, count 2 2006.173.17:22:36.00#ibcon#about to read 3, iclass 34, count 2 2006.173.17:22:36.02#ibcon#read 3, iclass 34, count 2 2006.173.17:22:36.02#ibcon#about to read 4, iclass 34, count 2 2006.173.17:22:36.02#ibcon#read 4, iclass 34, count 2 2006.173.17:22:36.02#ibcon#about to read 5, iclass 34, count 2 2006.173.17:22:36.02#ibcon#read 5, iclass 34, count 2 2006.173.17:22:36.02#ibcon#about to read 6, iclass 34, count 2 2006.173.17:22:36.02#ibcon#read 6, iclass 34, count 2 2006.173.17:22:36.02#ibcon#end of sib2, iclass 34, count 2 2006.173.17:22:36.02#ibcon#*mode == 0, iclass 34, count 2 2006.173.17:22:36.02#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.17:22:36.02#ibcon#[27=AT07-04\r\n] 2006.173.17:22:36.02#ibcon#*before write, iclass 34, count 2 2006.173.17:22:36.02#ibcon#enter sib2, iclass 34, count 2 2006.173.17:22:36.02#ibcon#flushed, iclass 34, count 2 2006.173.17:22:36.02#ibcon#about to write, iclass 34, count 2 2006.173.17:22:36.02#ibcon#wrote, iclass 34, count 2 2006.173.17:22:36.02#ibcon#about to read 3, iclass 34, count 2 2006.173.17:22:36.05#ibcon#read 3, iclass 34, count 2 2006.173.17:22:36.05#ibcon#about to read 4, iclass 34, count 2 2006.173.17:22:36.05#ibcon#read 4, iclass 34, count 2 2006.173.17:22:36.05#ibcon#about to read 5, iclass 34, count 2 2006.173.17:22:36.05#ibcon#read 5, iclass 34, count 2 2006.173.17:22:36.05#ibcon#about to read 6, iclass 34, count 2 2006.173.17:22:36.05#ibcon#read 6, iclass 34, count 2 2006.173.17:22:36.05#ibcon#end of sib2, iclass 34, count 2 2006.173.17:22:36.05#ibcon#*after write, iclass 34, count 2 2006.173.17:22:36.05#ibcon#*before return 0, iclass 34, count 2 2006.173.17:22:36.05#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.17:22:36.05#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.17:22:36.05#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.17:22:36.05#ibcon#ireg 7 cls_cnt 0 2006.173.17:22:36.05#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.17:22:36.17#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.17:22:36.17#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.17:22:36.17#ibcon#enter wrdev, iclass 34, count 0 2006.173.17:22:36.17#ibcon#first serial, iclass 34, count 0 2006.173.17:22:36.17#ibcon#enter sib2, iclass 34, count 0 2006.173.17:22:36.17#ibcon#flushed, iclass 34, count 0 2006.173.17:22:36.17#ibcon#about to write, iclass 34, count 0 2006.173.17:22:36.17#ibcon#wrote, iclass 34, count 0 2006.173.17:22:36.17#ibcon#about to read 3, iclass 34, count 0 2006.173.17:22:36.19#ibcon#read 3, iclass 34, count 0 2006.173.17:22:36.19#ibcon#about to read 4, iclass 34, count 0 2006.173.17:22:36.19#ibcon#read 4, iclass 34, count 0 2006.173.17:22:36.19#ibcon#about to read 5, iclass 34, count 0 2006.173.17:22:36.19#ibcon#read 5, iclass 34, count 0 2006.173.17:22:36.19#ibcon#about to read 6, iclass 34, count 0 2006.173.17:22:36.19#ibcon#read 6, iclass 34, count 0 2006.173.17:22:36.19#ibcon#end of sib2, iclass 34, count 0 2006.173.17:22:36.19#ibcon#*mode == 0, iclass 34, count 0 2006.173.17:22:36.19#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.17:22:36.19#ibcon#[27=USB\r\n] 2006.173.17:22:36.19#ibcon#*before write, iclass 34, count 0 2006.173.17:22:36.19#ibcon#enter sib2, iclass 34, count 0 2006.173.17:22:36.19#ibcon#flushed, iclass 34, count 0 2006.173.17:22:36.19#ibcon#about to write, iclass 34, count 0 2006.173.17:22:36.19#ibcon#wrote, iclass 34, count 0 2006.173.17:22:36.19#ibcon#about to read 3, iclass 34, count 0 2006.173.17:22:36.22#ibcon#read 3, iclass 34, count 0 2006.173.17:22:36.22#ibcon#about to read 4, iclass 34, count 0 2006.173.17:22:36.22#ibcon#read 4, iclass 34, count 0 2006.173.17:22:36.22#ibcon#about to read 5, iclass 34, count 0 2006.173.17:22:36.22#ibcon#read 5, iclass 34, count 0 2006.173.17:22:36.22#ibcon#about to read 6, iclass 34, count 0 2006.173.17:22:36.22#ibcon#read 6, iclass 34, count 0 2006.173.17:22:36.22#ibcon#end of sib2, iclass 34, count 0 2006.173.17:22:36.22#ibcon#*after write, iclass 34, count 0 2006.173.17:22:36.22#ibcon#*before return 0, iclass 34, count 0 2006.173.17:22:36.22#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.17:22:36.22#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.17:22:36.22#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.17:22:36.22#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.17:22:36.22$vck44/vblo=8,744.99 2006.173.17:22:36.22#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.17:22:36.22#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.17:22:36.22#ibcon#ireg 17 cls_cnt 0 2006.173.17:22:36.22#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.17:22:36.22#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.17:22:36.22#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.17:22:36.22#ibcon#enter wrdev, iclass 36, count 0 2006.173.17:22:36.22#ibcon#first serial, iclass 36, count 0 2006.173.17:22:36.22#ibcon#enter sib2, iclass 36, count 0 2006.173.17:22:36.22#ibcon#flushed, iclass 36, count 0 2006.173.17:22:36.22#ibcon#about to write, iclass 36, count 0 2006.173.17:22:36.22#ibcon#wrote, iclass 36, count 0 2006.173.17:22:36.22#ibcon#about to read 3, iclass 36, count 0 2006.173.17:22:36.24#ibcon#read 3, iclass 36, count 0 2006.173.17:22:36.24#ibcon#about to read 4, iclass 36, count 0 2006.173.17:22:36.24#ibcon#read 4, iclass 36, count 0 2006.173.17:22:36.24#ibcon#about to read 5, iclass 36, count 0 2006.173.17:22:36.24#ibcon#read 5, iclass 36, count 0 2006.173.17:22:36.24#ibcon#about to read 6, iclass 36, count 0 2006.173.17:22:36.24#ibcon#read 6, iclass 36, count 0 2006.173.17:22:36.24#ibcon#end of sib2, iclass 36, count 0 2006.173.17:22:36.24#ibcon#*mode == 0, iclass 36, count 0 2006.173.17:22:36.24#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.17:22:36.24#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.17:22:36.24#ibcon#*before write, iclass 36, count 0 2006.173.17:22:36.24#ibcon#enter sib2, iclass 36, count 0 2006.173.17:22:36.24#ibcon#flushed, iclass 36, count 0 2006.173.17:22:36.24#ibcon#about to write, iclass 36, count 0 2006.173.17:22:36.24#ibcon#wrote, iclass 36, count 0 2006.173.17:22:36.24#ibcon#about to read 3, iclass 36, count 0 2006.173.17:22:36.28#ibcon#read 3, iclass 36, count 0 2006.173.17:22:36.28#ibcon#about to read 4, iclass 36, count 0 2006.173.17:22:36.28#ibcon#read 4, iclass 36, count 0 2006.173.17:22:36.28#ibcon#about to read 5, iclass 36, count 0 2006.173.17:22:36.28#ibcon#read 5, iclass 36, count 0 2006.173.17:22:36.28#ibcon#about to read 6, iclass 36, count 0 2006.173.17:22:36.28#ibcon#read 6, iclass 36, count 0 2006.173.17:22:36.28#ibcon#end of sib2, iclass 36, count 0 2006.173.17:22:36.28#ibcon#*after write, iclass 36, count 0 2006.173.17:22:36.28#ibcon#*before return 0, iclass 36, count 0 2006.173.17:22:36.28#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.17:22:36.28#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.17:22:36.28#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.17:22:36.28#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.17:22:36.28$vck44/vb=8,4 2006.173.17:22:36.28#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.17:22:36.28#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.17:22:36.28#ibcon#ireg 11 cls_cnt 2 2006.173.17:22:36.28#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.17:22:36.34#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.17:22:36.34#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.17:22:36.34#ibcon#enter wrdev, iclass 38, count 2 2006.173.17:22:36.34#ibcon#first serial, iclass 38, count 2 2006.173.17:22:36.34#ibcon#enter sib2, iclass 38, count 2 2006.173.17:22:36.34#ibcon#flushed, iclass 38, count 2 2006.173.17:22:36.34#ibcon#about to write, iclass 38, count 2 2006.173.17:22:36.34#ibcon#wrote, iclass 38, count 2 2006.173.17:22:36.34#ibcon#about to read 3, iclass 38, count 2 2006.173.17:22:36.36#ibcon#read 3, iclass 38, count 2 2006.173.17:22:36.36#ibcon#about to read 4, iclass 38, count 2 2006.173.17:22:36.36#ibcon#read 4, iclass 38, count 2 2006.173.17:22:36.36#ibcon#about to read 5, iclass 38, count 2 2006.173.17:22:36.36#ibcon#read 5, iclass 38, count 2 2006.173.17:22:36.36#ibcon#about to read 6, iclass 38, count 2 2006.173.17:22:36.36#ibcon#read 6, iclass 38, count 2 2006.173.17:22:36.36#ibcon#end of sib2, iclass 38, count 2 2006.173.17:22:36.36#ibcon#*mode == 0, iclass 38, count 2 2006.173.17:22:36.36#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.17:22:36.36#ibcon#[27=AT08-04\r\n] 2006.173.17:22:36.36#ibcon#*before write, iclass 38, count 2 2006.173.17:22:36.36#ibcon#enter sib2, iclass 38, count 2 2006.173.17:22:36.36#ibcon#flushed, iclass 38, count 2 2006.173.17:22:36.36#ibcon#about to write, iclass 38, count 2 2006.173.17:22:36.36#ibcon#wrote, iclass 38, count 2 2006.173.17:22:36.36#ibcon#about to read 3, iclass 38, count 2 2006.173.17:22:36.39#ibcon#read 3, iclass 38, count 2 2006.173.17:22:36.39#ibcon#about to read 4, iclass 38, count 2 2006.173.17:22:36.39#ibcon#read 4, iclass 38, count 2 2006.173.17:22:36.39#ibcon#about to read 5, iclass 38, count 2 2006.173.17:22:36.39#ibcon#read 5, iclass 38, count 2 2006.173.17:22:36.39#ibcon#about to read 6, iclass 38, count 2 2006.173.17:22:36.39#ibcon#read 6, iclass 38, count 2 2006.173.17:22:36.39#ibcon#end of sib2, iclass 38, count 2 2006.173.17:22:36.39#ibcon#*after write, iclass 38, count 2 2006.173.17:22:36.39#ibcon#*before return 0, iclass 38, count 2 2006.173.17:22:36.39#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.17:22:36.39#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.17:22:36.39#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.17:22:36.39#ibcon#ireg 7 cls_cnt 0 2006.173.17:22:36.39#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.17:22:36.51#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.17:22:36.51#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.17:22:36.51#ibcon#enter wrdev, iclass 38, count 0 2006.173.17:22:36.51#ibcon#first serial, iclass 38, count 0 2006.173.17:22:36.51#ibcon#enter sib2, iclass 38, count 0 2006.173.17:22:36.51#ibcon#flushed, iclass 38, count 0 2006.173.17:22:36.51#ibcon#about to write, iclass 38, count 0 2006.173.17:22:36.51#ibcon#wrote, iclass 38, count 0 2006.173.17:22:36.51#ibcon#about to read 3, iclass 38, count 0 2006.173.17:22:36.53#ibcon#read 3, iclass 38, count 0 2006.173.17:22:36.53#ibcon#about to read 4, iclass 38, count 0 2006.173.17:22:36.53#ibcon#read 4, iclass 38, count 0 2006.173.17:22:36.53#ibcon#about to read 5, iclass 38, count 0 2006.173.17:22:36.53#ibcon#read 5, iclass 38, count 0 2006.173.17:22:36.53#ibcon#about to read 6, iclass 38, count 0 2006.173.17:22:36.53#ibcon#read 6, iclass 38, count 0 2006.173.17:22:36.53#ibcon#end of sib2, iclass 38, count 0 2006.173.17:22:36.53#ibcon#*mode == 0, iclass 38, count 0 2006.173.17:22:36.53#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.17:22:36.53#ibcon#[27=USB\r\n] 2006.173.17:22:36.53#ibcon#*before write, iclass 38, count 0 2006.173.17:22:36.53#ibcon#enter sib2, iclass 38, count 0 2006.173.17:22:36.53#ibcon#flushed, iclass 38, count 0 2006.173.17:22:36.53#ibcon#about to write, iclass 38, count 0 2006.173.17:22:36.53#ibcon#wrote, iclass 38, count 0 2006.173.17:22:36.53#ibcon#about to read 3, iclass 38, count 0 2006.173.17:22:36.56#ibcon#read 3, iclass 38, count 0 2006.173.17:22:36.56#ibcon#about to read 4, iclass 38, count 0 2006.173.17:22:36.56#ibcon#read 4, iclass 38, count 0 2006.173.17:22:36.56#ibcon#about to read 5, iclass 38, count 0 2006.173.17:22:36.56#ibcon#read 5, iclass 38, count 0 2006.173.17:22:36.56#ibcon#about to read 6, iclass 38, count 0 2006.173.17:22:36.56#ibcon#read 6, iclass 38, count 0 2006.173.17:22:36.56#ibcon#end of sib2, iclass 38, count 0 2006.173.17:22:36.56#ibcon#*after write, iclass 38, count 0 2006.173.17:22:36.56#ibcon#*before return 0, iclass 38, count 0 2006.173.17:22:36.56#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.17:22:36.56#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.17:22:36.56#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.17:22:36.56#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.17:22:36.56$vck44/vabw=wide 2006.173.17:22:36.56#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.17:22:36.56#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.17:22:36.56#ibcon#ireg 8 cls_cnt 0 2006.173.17:22:36.56#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.17:22:36.56#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.17:22:36.56#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.17:22:36.56#ibcon#enter wrdev, iclass 40, count 0 2006.173.17:22:36.56#ibcon#first serial, iclass 40, count 0 2006.173.17:22:36.56#ibcon#enter sib2, iclass 40, count 0 2006.173.17:22:36.56#ibcon#flushed, iclass 40, count 0 2006.173.17:22:36.56#ibcon#about to write, iclass 40, count 0 2006.173.17:22:36.56#ibcon#wrote, iclass 40, count 0 2006.173.17:22:36.56#ibcon#about to read 3, iclass 40, count 0 2006.173.17:22:36.58#ibcon#read 3, iclass 40, count 0 2006.173.17:22:36.58#ibcon#about to read 4, iclass 40, count 0 2006.173.17:22:36.58#ibcon#read 4, iclass 40, count 0 2006.173.17:22:36.58#ibcon#about to read 5, iclass 40, count 0 2006.173.17:22:36.58#ibcon#read 5, iclass 40, count 0 2006.173.17:22:36.58#ibcon#about to read 6, iclass 40, count 0 2006.173.17:22:36.58#ibcon#read 6, iclass 40, count 0 2006.173.17:22:36.58#ibcon#end of sib2, iclass 40, count 0 2006.173.17:22:36.58#ibcon#*mode == 0, iclass 40, count 0 2006.173.17:22:36.58#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.17:22:36.58#ibcon#[25=BW32\r\n] 2006.173.17:22:36.58#ibcon#*before write, iclass 40, count 0 2006.173.17:22:36.58#ibcon#enter sib2, iclass 40, count 0 2006.173.17:22:36.58#ibcon#flushed, iclass 40, count 0 2006.173.17:22:36.58#ibcon#about to write, iclass 40, count 0 2006.173.17:22:36.58#ibcon#wrote, iclass 40, count 0 2006.173.17:22:36.58#ibcon#about to read 3, iclass 40, count 0 2006.173.17:22:36.61#ibcon#read 3, iclass 40, count 0 2006.173.17:22:36.61#ibcon#about to read 4, iclass 40, count 0 2006.173.17:22:36.61#ibcon#read 4, iclass 40, count 0 2006.173.17:22:36.61#ibcon#about to read 5, iclass 40, count 0 2006.173.17:22:36.61#ibcon#read 5, iclass 40, count 0 2006.173.17:22:36.61#ibcon#about to read 6, iclass 40, count 0 2006.173.17:22:36.61#ibcon#read 6, iclass 40, count 0 2006.173.17:22:36.61#ibcon#end of sib2, iclass 40, count 0 2006.173.17:22:36.61#ibcon#*after write, iclass 40, count 0 2006.173.17:22:36.61#ibcon#*before return 0, iclass 40, count 0 2006.173.17:22:36.61#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.17:22:36.61#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.17:22:36.61#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.17:22:36.61#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.17:22:36.61$vck44/vbbw=wide 2006.173.17:22:36.61#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.17:22:36.61#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.17:22:36.61#ibcon#ireg 8 cls_cnt 0 2006.173.17:22:36.61#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.17:22:36.68#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.17:22:36.68#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.17:22:36.68#ibcon#enter wrdev, iclass 4, count 0 2006.173.17:22:36.68#ibcon#first serial, iclass 4, count 0 2006.173.17:22:36.68#ibcon#enter sib2, iclass 4, count 0 2006.173.17:22:36.68#ibcon#flushed, iclass 4, count 0 2006.173.17:22:36.68#ibcon#about to write, iclass 4, count 0 2006.173.17:22:36.68#ibcon#wrote, iclass 4, count 0 2006.173.17:22:36.68#ibcon#about to read 3, iclass 4, count 0 2006.173.17:22:36.70#ibcon#read 3, iclass 4, count 0 2006.173.17:22:36.70#ibcon#about to read 4, iclass 4, count 0 2006.173.17:22:36.70#ibcon#read 4, iclass 4, count 0 2006.173.17:22:36.70#ibcon#about to read 5, iclass 4, count 0 2006.173.17:22:36.70#ibcon#read 5, iclass 4, count 0 2006.173.17:22:36.70#ibcon#about to read 6, iclass 4, count 0 2006.173.17:22:36.70#ibcon#read 6, iclass 4, count 0 2006.173.17:22:36.70#ibcon#end of sib2, iclass 4, count 0 2006.173.17:22:36.70#ibcon#*mode == 0, iclass 4, count 0 2006.173.17:22:36.70#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.17:22:36.70#ibcon#[27=BW32\r\n] 2006.173.17:22:36.70#ibcon#*before write, iclass 4, count 0 2006.173.17:22:36.70#ibcon#enter sib2, iclass 4, count 0 2006.173.17:22:36.70#ibcon#flushed, iclass 4, count 0 2006.173.17:22:36.70#ibcon#about to write, iclass 4, count 0 2006.173.17:22:36.70#ibcon#wrote, iclass 4, count 0 2006.173.17:22:36.70#ibcon#about to read 3, iclass 4, count 0 2006.173.17:22:36.73#ibcon#read 3, iclass 4, count 0 2006.173.17:22:36.73#ibcon#about to read 4, iclass 4, count 0 2006.173.17:22:36.73#ibcon#read 4, iclass 4, count 0 2006.173.17:22:36.73#ibcon#about to read 5, iclass 4, count 0 2006.173.17:22:36.73#ibcon#read 5, iclass 4, count 0 2006.173.17:22:36.73#ibcon#about to read 6, iclass 4, count 0 2006.173.17:22:36.73#ibcon#read 6, iclass 4, count 0 2006.173.17:22:36.73#ibcon#end of sib2, iclass 4, count 0 2006.173.17:22:36.73#ibcon#*after write, iclass 4, count 0 2006.173.17:22:36.73#ibcon#*before return 0, iclass 4, count 0 2006.173.17:22:36.73#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.17:22:36.73#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.17:22:36.73#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.17:22:36.73#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.17:22:36.73$setupk4/ifdk4 2006.173.17:22:36.73$ifdk4/lo= 2006.173.17:22:36.73$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.17:22:36.74$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.17:22:36.74$ifdk4/patch= 2006.173.17:22:36.74$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.17:22:36.74$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.17:22:36.74$setupk4/!*+20s 2006.173.17:22:42.64#abcon#<5=/14 1.1 2.6 20.261001002.6\r\n> 2006.173.17:22:42.66#abcon#{5=INTERFACE CLEAR} 2006.173.17:22:42.72#abcon#[5=S1D000X0/0*\r\n] 2006.173.17:22:43.14#trakl#Source acquired 2006.173.17:22:45.14#flagr#flagr/antenna,acquired 2006.173.17:22:51.25$setupk4/"tpicd 2006.173.17:22:51.25$setupk4/echo=off 2006.173.17:22:51.25$setupk4/xlog=off 2006.173.17:22:51.25:!2006.173.17:25:27 2006.173.17:25:27.00:preob 2006.173.17:25:28.14/onsource/TRACKING 2006.173.17:25:28.14:!2006.173.17:25:37 2006.173.17:25:37.00:"tape 2006.173.17:25:37.00:"st=record 2006.173.17:25:37.00:data_valid=on 2006.173.17:25:37.00:midob 2006.173.17:25:37.14/onsource/TRACKING 2006.173.17:25:37.14/wx/20.26,1002.5,100 2006.173.17:25:37.20/cable/+6.5132E-03 2006.173.17:25:38.29/va/01,07,usb,yes,39,42 2006.173.17:25:38.29/va/02,06,usb,yes,39,40 2006.173.17:25:38.29/va/03,05,usb,yes,49,51 2006.173.17:25:38.29/va/04,06,usb,yes,40,42 2006.173.17:25:38.29/va/05,04,usb,yes,31,32 2006.173.17:25:38.29/va/06,03,usb,yes,43,43 2006.173.17:25:38.29/va/07,04,usb,yes,35,37 2006.173.17:25:38.29/va/08,04,usb,yes,30,36 2006.173.17:25:38.52/valo/01,524.99,yes,locked 2006.173.17:25:38.52/valo/02,534.99,yes,locked 2006.173.17:25:38.52/valo/03,564.99,yes,locked 2006.173.17:25:38.52/valo/04,624.99,yes,locked 2006.173.17:25:38.52/valo/05,734.99,yes,locked 2006.173.17:25:38.52/valo/06,814.99,yes,locked 2006.173.17:25:38.52/valo/07,864.99,yes,locked 2006.173.17:25:38.52/valo/08,884.99,yes,locked 2006.173.17:25:39.61/vb/01,04,usb,yes,31,29 2006.173.17:25:39.61/vb/02,04,usb,yes,33,33 2006.173.17:25:39.61/vb/03,04,usb,yes,30,33 2006.173.17:25:39.61/vb/04,04,usb,yes,35,34 2006.173.17:25:39.61/vb/05,04,usb,yes,28,30 2006.173.17:25:39.61/vb/06,04,usb,yes,32,28 2006.173.17:25:39.61/vb/07,04,usb,yes,31,31 2006.173.17:25:39.61/vb/08,04,usb,yes,29,32 2006.173.17:25:39.84/vblo/01,629.99,yes,locked 2006.173.17:25:39.84/vblo/02,634.99,yes,locked 2006.173.17:25:39.84/vblo/03,649.99,yes,locked 2006.173.17:25:39.84/vblo/04,679.99,yes,locked 2006.173.17:25:39.84/vblo/05,709.99,yes,locked 2006.173.17:25:39.84/vblo/06,719.99,yes,locked 2006.173.17:25:39.84/vblo/07,734.99,yes,locked 2006.173.17:25:39.84/vblo/08,744.99,yes,locked 2006.173.17:25:39.99/vabw/8 2006.173.17:25:40.14/vbbw/8 2006.173.17:25:40.23/xfe/off,on,15.2 2006.173.17:25:40.60/ifatt/23,28,28,28 2006.173.17:25:41.07/fmout-gps/S +4.00E-07 2006.173.17:25:41.12:!2006.173.17:26:17 2006.173.17:26:17.01:data_valid=off 2006.173.17:26:17.02:"et 2006.173.17:26:17.02:!+3s 2006.173.17:26:20.03:"tape 2006.173.17:26:20.04:postob 2006.173.17:26:20.21/cable/+6.5149E-03 2006.173.17:26:20.22/wx/20.26,1002.4,100 2006.173.17:26:20.27/fmout-gps/S +3.99E-07 2006.173.17:26:20.28:scan_name=173-1730,jd0606,80 2006.173.17:26:20.28:source=2136+141,213901.31,142336.0,2000.0,ccw 2006.173.17:26:22.14#flagr#flagr/antenna,new-source 2006.173.17:26:22.15:checkk5 2006.173.17:26:22.57/chk_autoobs//k5ts1/ autoobs is running! 2006.173.17:26:22.98/chk_autoobs//k5ts2/ autoobs is running! 2006.173.17:26:23.39/chk_autoobs//k5ts3/ autoobs is running! 2006.173.17:26:23.79/chk_autoobs//k5ts4/ autoobs is running! 2006.173.17:26:24.17/chk_obsdata//k5ts1/T1731725??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.173.17:26:24.56/chk_obsdata//k5ts2/T1731725??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.173.17:26:24.96/chk_obsdata//k5ts3/T1731725??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.173.17:26:25.37/chk_obsdata//k5ts4/T1731725??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.173.17:26:26.10/k5log//k5ts1_log_newline 2006.173.17:26:26.81/k5log//k5ts2_log_newline 2006.173.17:26:27.52/k5log//k5ts3_log_newline 2006.173.17:26:28.22/k5log//k5ts4_log_newline 2006.173.17:26:28.25/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.17:26:28.25:setupk4=1 2006.173.17:26:28.25$setupk4/echo=on 2006.173.17:26:28.25$setupk4/pcalon 2006.173.17:26:28.25$pcalon/"no phase cal control is implemented here 2006.173.17:26:28.25$setupk4/"tpicd=stop 2006.173.17:26:28.25$setupk4/"rec=synch_on 2006.173.17:26:28.25$setupk4/"rec_mode=128 2006.173.17:26:28.25$setupk4/!* 2006.173.17:26:28.25$setupk4/recpk4 2006.173.17:26:28.25$recpk4/recpatch= 2006.173.17:26:28.26$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.17:26:28.26$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.17:26:28.26$setupk4/vck44 2006.173.17:26:28.26$vck44/valo=1,524.99 2006.173.17:26:28.26#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.17:26:28.26#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.17:26:28.26#ibcon#ireg 17 cls_cnt 0 2006.173.17:26:28.26#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.17:26:28.26#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.17:26:28.26#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.17:26:28.26#ibcon#enter wrdev, iclass 31, count 0 2006.173.17:26:28.26#ibcon#first serial, iclass 31, count 0 2006.173.17:26:28.26#ibcon#enter sib2, iclass 31, count 0 2006.173.17:26:28.26#ibcon#flushed, iclass 31, count 0 2006.173.17:26:28.26#ibcon#about to write, iclass 31, count 0 2006.173.17:26:28.26#ibcon#wrote, iclass 31, count 0 2006.173.17:26:28.26#ibcon#about to read 3, iclass 31, count 0 2006.173.17:26:28.27#ibcon#read 3, iclass 31, count 0 2006.173.17:26:28.27#ibcon#about to read 4, iclass 31, count 0 2006.173.17:26:28.27#ibcon#read 4, iclass 31, count 0 2006.173.17:26:28.27#ibcon#about to read 5, iclass 31, count 0 2006.173.17:26:28.27#ibcon#read 5, iclass 31, count 0 2006.173.17:26:28.27#ibcon#about to read 6, iclass 31, count 0 2006.173.17:26:28.27#ibcon#read 6, iclass 31, count 0 2006.173.17:26:28.27#ibcon#end of sib2, iclass 31, count 0 2006.173.17:26:28.27#ibcon#*mode == 0, iclass 31, count 0 2006.173.17:26:28.27#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.17:26:28.27#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.17:26:28.27#ibcon#*before write, iclass 31, count 0 2006.173.17:26:28.27#ibcon#enter sib2, iclass 31, count 0 2006.173.17:26:28.27#ibcon#flushed, iclass 31, count 0 2006.173.17:26:28.27#ibcon#about to write, iclass 31, count 0 2006.173.17:26:28.27#ibcon#wrote, iclass 31, count 0 2006.173.17:26:28.27#ibcon#about to read 3, iclass 31, count 0 2006.173.17:26:28.32#ibcon#read 3, iclass 31, count 0 2006.173.17:26:28.32#ibcon#about to read 4, iclass 31, count 0 2006.173.17:26:28.32#ibcon#read 4, iclass 31, count 0 2006.173.17:26:28.32#ibcon#about to read 5, iclass 31, count 0 2006.173.17:26:28.32#ibcon#read 5, iclass 31, count 0 2006.173.17:26:28.32#ibcon#about to read 6, iclass 31, count 0 2006.173.17:26:28.32#ibcon#read 6, iclass 31, count 0 2006.173.17:26:28.32#ibcon#end of sib2, iclass 31, count 0 2006.173.17:26:28.32#ibcon#*after write, iclass 31, count 0 2006.173.17:26:28.32#ibcon#*before return 0, iclass 31, count 0 2006.173.17:26:28.32#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.17:26:28.32#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.17:26:28.32#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.17:26:28.32#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.17:26:28.32$vck44/va=1,7 2006.173.17:26:28.32#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.173.17:26:28.32#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.173.17:26:28.32#ibcon#ireg 11 cls_cnt 2 2006.173.17:26:28.32#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.17:26:28.32#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.17:26:28.32#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.17:26:28.32#ibcon#enter wrdev, iclass 33, count 2 2006.173.17:26:28.32#ibcon#first serial, iclass 33, count 2 2006.173.17:26:28.32#ibcon#enter sib2, iclass 33, count 2 2006.173.17:26:28.32#ibcon#flushed, iclass 33, count 2 2006.173.17:26:28.32#ibcon#about to write, iclass 33, count 2 2006.173.17:26:28.32#ibcon#wrote, iclass 33, count 2 2006.173.17:26:28.32#ibcon#about to read 3, iclass 33, count 2 2006.173.17:26:28.34#ibcon#read 3, iclass 33, count 2 2006.173.17:26:28.34#ibcon#about to read 4, iclass 33, count 2 2006.173.17:26:28.34#ibcon#read 4, iclass 33, count 2 2006.173.17:26:28.34#ibcon#about to read 5, iclass 33, count 2 2006.173.17:26:28.34#ibcon#read 5, iclass 33, count 2 2006.173.17:26:28.34#ibcon#about to read 6, iclass 33, count 2 2006.173.17:26:28.34#ibcon#read 6, iclass 33, count 2 2006.173.17:26:28.34#ibcon#end of sib2, iclass 33, count 2 2006.173.17:26:28.34#ibcon#*mode == 0, iclass 33, count 2 2006.173.17:26:28.34#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.173.17:26:28.34#ibcon#[25=AT01-07\r\n] 2006.173.17:26:28.34#ibcon#*before write, iclass 33, count 2 2006.173.17:26:28.34#ibcon#enter sib2, iclass 33, count 2 2006.173.17:26:28.34#ibcon#flushed, iclass 33, count 2 2006.173.17:26:28.34#ibcon#about to write, iclass 33, count 2 2006.173.17:26:28.34#ibcon#wrote, iclass 33, count 2 2006.173.17:26:28.34#ibcon#about to read 3, iclass 33, count 2 2006.173.17:26:28.37#ibcon#read 3, iclass 33, count 2 2006.173.17:26:28.37#ibcon#about to read 4, iclass 33, count 2 2006.173.17:26:28.37#ibcon#read 4, iclass 33, count 2 2006.173.17:26:28.37#ibcon#about to read 5, iclass 33, count 2 2006.173.17:26:28.37#ibcon#read 5, iclass 33, count 2 2006.173.17:26:28.37#ibcon#about to read 6, iclass 33, count 2 2006.173.17:26:28.37#ibcon#read 6, iclass 33, count 2 2006.173.17:26:28.37#ibcon#end of sib2, iclass 33, count 2 2006.173.17:26:28.37#ibcon#*after write, iclass 33, count 2 2006.173.17:26:28.37#ibcon#*before return 0, iclass 33, count 2 2006.173.17:26:28.37#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.17:26:28.37#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.173.17:26:28.37#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.173.17:26:28.37#ibcon#ireg 7 cls_cnt 0 2006.173.17:26:28.37#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.17:26:28.49#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.17:26:28.49#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.17:26:28.49#ibcon#enter wrdev, iclass 33, count 0 2006.173.17:26:28.49#ibcon#first serial, iclass 33, count 0 2006.173.17:26:28.49#ibcon#enter sib2, iclass 33, count 0 2006.173.17:26:28.49#ibcon#flushed, iclass 33, count 0 2006.173.17:26:28.49#ibcon#about to write, iclass 33, count 0 2006.173.17:26:28.49#ibcon#wrote, iclass 33, count 0 2006.173.17:26:28.49#ibcon#about to read 3, iclass 33, count 0 2006.173.17:26:28.51#ibcon#read 3, iclass 33, count 0 2006.173.17:26:28.51#ibcon#about to read 4, iclass 33, count 0 2006.173.17:26:28.51#ibcon#read 4, iclass 33, count 0 2006.173.17:26:28.51#ibcon#about to read 5, iclass 33, count 0 2006.173.17:26:28.51#ibcon#read 5, iclass 33, count 0 2006.173.17:26:28.51#ibcon#about to read 6, iclass 33, count 0 2006.173.17:26:28.51#ibcon#read 6, iclass 33, count 0 2006.173.17:26:28.51#ibcon#end of sib2, iclass 33, count 0 2006.173.17:26:28.51#ibcon#*mode == 0, iclass 33, count 0 2006.173.17:26:28.51#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.17:26:28.51#ibcon#[25=USB\r\n] 2006.173.17:26:28.51#ibcon#*before write, iclass 33, count 0 2006.173.17:26:28.51#ibcon#enter sib2, iclass 33, count 0 2006.173.17:26:28.51#ibcon#flushed, iclass 33, count 0 2006.173.17:26:28.51#ibcon#about to write, iclass 33, count 0 2006.173.17:26:28.51#ibcon#wrote, iclass 33, count 0 2006.173.17:26:28.51#ibcon#about to read 3, iclass 33, count 0 2006.173.17:26:28.54#ibcon#read 3, iclass 33, count 0 2006.173.17:26:28.54#ibcon#about to read 4, iclass 33, count 0 2006.173.17:26:28.54#ibcon#read 4, iclass 33, count 0 2006.173.17:26:28.54#ibcon#about to read 5, iclass 33, count 0 2006.173.17:26:28.54#ibcon#read 5, iclass 33, count 0 2006.173.17:26:28.54#ibcon#about to read 6, iclass 33, count 0 2006.173.17:26:28.54#ibcon#read 6, iclass 33, count 0 2006.173.17:26:28.54#ibcon#end of sib2, iclass 33, count 0 2006.173.17:26:28.54#ibcon#*after write, iclass 33, count 0 2006.173.17:26:28.54#ibcon#*before return 0, iclass 33, count 0 2006.173.17:26:28.54#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.17:26:28.54#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.173.17:26:28.54#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.17:26:28.54#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.17:26:28.54$vck44/valo=2,534.99 2006.173.17:26:28.54#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.17:26:28.54#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.17:26:28.54#ibcon#ireg 17 cls_cnt 0 2006.173.17:26:28.54#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.17:26:28.54#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.17:26:28.54#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.17:26:28.54#ibcon#enter wrdev, iclass 35, count 0 2006.173.17:26:28.54#ibcon#first serial, iclass 35, count 0 2006.173.17:26:28.54#ibcon#enter sib2, iclass 35, count 0 2006.173.17:26:28.54#ibcon#flushed, iclass 35, count 0 2006.173.17:26:28.54#ibcon#about to write, iclass 35, count 0 2006.173.17:26:28.54#ibcon#wrote, iclass 35, count 0 2006.173.17:26:28.54#ibcon#about to read 3, iclass 35, count 0 2006.173.17:26:28.56#ibcon#read 3, iclass 35, count 0 2006.173.17:26:28.56#ibcon#about to read 4, iclass 35, count 0 2006.173.17:26:28.56#ibcon#read 4, iclass 35, count 0 2006.173.17:26:28.56#ibcon#about to read 5, iclass 35, count 0 2006.173.17:26:28.56#ibcon#read 5, iclass 35, count 0 2006.173.17:26:28.56#ibcon#about to read 6, iclass 35, count 0 2006.173.17:26:28.56#ibcon#read 6, iclass 35, count 0 2006.173.17:26:28.56#ibcon#end of sib2, iclass 35, count 0 2006.173.17:26:28.56#ibcon#*mode == 0, iclass 35, count 0 2006.173.17:26:28.56#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.17:26:28.56#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.17:26:28.56#ibcon#*before write, iclass 35, count 0 2006.173.17:26:28.56#ibcon#enter sib2, iclass 35, count 0 2006.173.17:26:28.56#ibcon#flushed, iclass 35, count 0 2006.173.17:26:28.56#ibcon#about to write, iclass 35, count 0 2006.173.17:26:28.56#ibcon#wrote, iclass 35, count 0 2006.173.17:26:28.56#ibcon#about to read 3, iclass 35, count 0 2006.173.17:26:28.60#ibcon#read 3, iclass 35, count 0 2006.173.17:26:28.60#ibcon#about to read 4, iclass 35, count 0 2006.173.17:26:28.60#ibcon#read 4, iclass 35, count 0 2006.173.17:26:28.60#ibcon#about to read 5, iclass 35, count 0 2006.173.17:26:28.60#ibcon#read 5, iclass 35, count 0 2006.173.17:26:28.60#ibcon#about to read 6, iclass 35, count 0 2006.173.17:26:28.60#ibcon#read 6, iclass 35, count 0 2006.173.17:26:28.60#ibcon#end of sib2, iclass 35, count 0 2006.173.17:26:28.60#ibcon#*after write, iclass 35, count 0 2006.173.17:26:28.60#ibcon#*before return 0, iclass 35, count 0 2006.173.17:26:28.60#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.17:26:28.60#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.17:26:28.60#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.17:26:28.60#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.17:26:28.60$vck44/va=2,6 2006.173.17:26:28.60#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.173.17:26:28.60#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.173.17:26:28.60#ibcon#ireg 11 cls_cnt 2 2006.173.17:26:28.60#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.17:26:28.66#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.17:26:28.66#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.17:26:28.66#ibcon#enter wrdev, iclass 37, count 2 2006.173.17:26:28.66#ibcon#first serial, iclass 37, count 2 2006.173.17:26:28.66#ibcon#enter sib2, iclass 37, count 2 2006.173.17:26:28.66#ibcon#flushed, iclass 37, count 2 2006.173.17:26:28.66#ibcon#about to write, iclass 37, count 2 2006.173.17:26:28.66#ibcon#wrote, iclass 37, count 2 2006.173.17:26:28.66#ibcon#about to read 3, iclass 37, count 2 2006.173.17:26:28.68#ibcon#read 3, iclass 37, count 2 2006.173.17:26:28.68#ibcon#about to read 4, iclass 37, count 2 2006.173.17:26:28.68#ibcon#read 4, iclass 37, count 2 2006.173.17:26:28.68#ibcon#about to read 5, iclass 37, count 2 2006.173.17:26:28.68#ibcon#read 5, iclass 37, count 2 2006.173.17:26:28.68#ibcon#about to read 6, iclass 37, count 2 2006.173.17:26:28.68#ibcon#read 6, iclass 37, count 2 2006.173.17:26:28.68#ibcon#end of sib2, iclass 37, count 2 2006.173.17:26:28.68#ibcon#*mode == 0, iclass 37, count 2 2006.173.17:26:28.68#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.173.17:26:28.68#ibcon#[25=AT02-06\r\n] 2006.173.17:26:28.68#ibcon#*before write, iclass 37, count 2 2006.173.17:26:28.68#ibcon#enter sib2, iclass 37, count 2 2006.173.17:26:28.68#ibcon#flushed, iclass 37, count 2 2006.173.17:26:28.68#ibcon#about to write, iclass 37, count 2 2006.173.17:26:28.68#ibcon#wrote, iclass 37, count 2 2006.173.17:26:28.68#ibcon#about to read 3, iclass 37, count 2 2006.173.17:26:28.71#ibcon#read 3, iclass 37, count 2 2006.173.17:26:28.71#ibcon#about to read 4, iclass 37, count 2 2006.173.17:26:28.71#ibcon#read 4, iclass 37, count 2 2006.173.17:26:28.71#ibcon#about to read 5, iclass 37, count 2 2006.173.17:26:28.71#ibcon#read 5, iclass 37, count 2 2006.173.17:26:28.71#ibcon#about to read 6, iclass 37, count 2 2006.173.17:26:28.71#ibcon#read 6, iclass 37, count 2 2006.173.17:26:28.71#ibcon#end of sib2, iclass 37, count 2 2006.173.17:26:28.71#ibcon#*after write, iclass 37, count 2 2006.173.17:26:28.71#ibcon#*before return 0, iclass 37, count 2 2006.173.17:26:28.71#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.17:26:28.71#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.173.17:26:28.71#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.173.17:26:28.71#ibcon#ireg 7 cls_cnt 0 2006.173.17:26:28.71#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.17:26:28.83#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.17:26:28.83#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.17:26:28.83#ibcon#enter wrdev, iclass 37, count 0 2006.173.17:26:28.83#ibcon#first serial, iclass 37, count 0 2006.173.17:26:28.83#ibcon#enter sib2, iclass 37, count 0 2006.173.17:26:28.83#ibcon#flushed, iclass 37, count 0 2006.173.17:26:28.83#ibcon#about to write, iclass 37, count 0 2006.173.17:26:28.83#ibcon#wrote, iclass 37, count 0 2006.173.17:26:28.83#ibcon#about to read 3, iclass 37, count 0 2006.173.17:26:28.85#ibcon#read 3, iclass 37, count 0 2006.173.17:26:28.85#ibcon#about to read 4, iclass 37, count 0 2006.173.17:26:28.85#ibcon#read 4, iclass 37, count 0 2006.173.17:26:28.85#ibcon#about to read 5, iclass 37, count 0 2006.173.17:26:28.85#ibcon#read 5, iclass 37, count 0 2006.173.17:26:28.85#ibcon#about to read 6, iclass 37, count 0 2006.173.17:26:28.85#ibcon#read 6, iclass 37, count 0 2006.173.17:26:28.85#ibcon#end of sib2, iclass 37, count 0 2006.173.17:26:28.85#ibcon#*mode == 0, iclass 37, count 0 2006.173.17:26:28.85#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.17:26:28.85#ibcon#[25=USB\r\n] 2006.173.17:26:28.85#ibcon#*before write, iclass 37, count 0 2006.173.17:26:28.85#ibcon#enter sib2, iclass 37, count 0 2006.173.17:26:28.85#ibcon#flushed, iclass 37, count 0 2006.173.17:26:28.85#ibcon#about to write, iclass 37, count 0 2006.173.17:26:28.85#ibcon#wrote, iclass 37, count 0 2006.173.17:26:28.85#ibcon#about to read 3, iclass 37, count 0 2006.173.17:26:28.88#ibcon#read 3, iclass 37, count 0 2006.173.17:26:28.88#ibcon#about to read 4, iclass 37, count 0 2006.173.17:26:28.88#ibcon#read 4, iclass 37, count 0 2006.173.17:26:28.88#ibcon#about to read 5, iclass 37, count 0 2006.173.17:26:28.88#ibcon#read 5, iclass 37, count 0 2006.173.17:26:28.88#ibcon#about to read 6, iclass 37, count 0 2006.173.17:26:28.88#ibcon#read 6, iclass 37, count 0 2006.173.17:26:28.88#ibcon#end of sib2, iclass 37, count 0 2006.173.17:26:28.88#ibcon#*after write, iclass 37, count 0 2006.173.17:26:28.88#ibcon#*before return 0, iclass 37, count 0 2006.173.17:26:28.88#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.17:26:28.88#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.173.17:26:28.88#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.17:26:28.88#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.17:26:28.88$vck44/valo=3,564.99 2006.173.17:26:28.88#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.17:26:28.88#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.17:26:28.88#ibcon#ireg 17 cls_cnt 0 2006.173.17:26:28.88#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.17:26:28.88#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.17:26:28.88#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.17:26:28.88#ibcon#enter wrdev, iclass 39, count 0 2006.173.17:26:28.88#ibcon#first serial, iclass 39, count 0 2006.173.17:26:28.88#ibcon#enter sib2, iclass 39, count 0 2006.173.17:26:28.88#ibcon#flushed, iclass 39, count 0 2006.173.17:26:28.88#ibcon#about to write, iclass 39, count 0 2006.173.17:26:28.88#ibcon#wrote, iclass 39, count 0 2006.173.17:26:28.88#ibcon#about to read 3, iclass 39, count 0 2006.173.17:26:28.90#ibcon#read 3, iclass 39, count 0 2006.173.17:26:28.90#ibcon#about to read 4, iclass 39, count 0 2006.173.17:26:28.90#ibcon#read 4, iclass 39, count 0 2006.173.17:26:28.90#ibcon#about to read 5, iclass 39, count 0 2006.173.17:26:28.90#ibcon#read 5, iclass 39, count 0 2006.173.17:26:28.90#ibcon#about to read 6, iclass 39, count 0 2006.173.17:26:28.90#ibcon#read 6, iclass 39, count 0 2006.173.17:26:28.90#ibcon#end of sib2, iclass 39, count 0 2006.173.17:26:28.90#ibcon#*mode == 0, iclass 39, count 0 2006.173.17:26:28.90#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.17:26:28.90#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.17:26:28.90#ibcon#*before write, iclass 39, count 0 2006.173.17:26:28.90#ibcon#enter sib2, iclass 39, count 0 2006.173.17:26:28.90#ibcon#flushed, iclass 39, count 0 2006.173.17:26:28.90#ibcon#about to write, iclass 39, count 0 2006.173.17:26:28.90#ibcon#wrote, iclass 39, count 0 2006.173.17:26:28.90#ibcon#about to read 3, iclass 39, count 0 2006.173.17:26:28.94#ibcon#read 3, iclass 39, count 0 2006.173.17:26:28.94#ibcon#about to read 4, iclass 39, count 0 2006.173.17:26:28.94#ibcon#read 4, iclass 39, count 0 2006.173.17:26:28.94#ibcon#about to read 5, iclass 39, count 0 2006.173.17:26:28.94#ibcon#read 5, iclass 39, count 0 2006.173.17:26:28.94#ibcon#about to read 6, iclass 39, count 0 2006.173.17:26:28.94#ibcon#read 6, iclass 39, count 0 2006.173.17:26:28.94#ibcon#end of sib2, iclass 39, count 0 2006.173.17:26:28.94#ibcon#*after write, iclass 39, count 0 2006.173.17:26:28.94#ibcon#*before return 0, iclass 39, count 0 2006.173.17:26:28.94#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.17:26:28.94#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.17:26:28.94#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.17:26:28.94#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.17:26:28.94$vck44/va=3,5 2006.173.17:26:28.94#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.17:26:28.94#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.17:26:28.94#ibcon#ireg 11 cls_cnt 2 2006.173.17:26:28.94#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.17:26:29.00#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.17:26:29.00#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.17:26:29.00#ibcon#enter wrdev, iclass 3, count 2 2006.173.17:26:29.00#ibcon#first serial, iclass 3, count 2 2006.173.17:26:29.00#ibcon#enter sib2, iclass 3, count 2 2006.173.17:26:29.00#ibcon#flushed, iclass 3, count 2 2006.173.17:26:29.00#ibcon#about to write, iclass 3, count 2 2006.173.17:26:29.00#ibcon#wrote, iclass 3, count 2 2006.173.17:26:29.00#ibcon#about to read 3, iclass 3, count 2 2006.173.17:26:29.02#ibcon#read 3, iclass 3, count 2 2006.173.17:26:29.02#ibcon#about to read 4, iclass 3, count 2 2006.173.17:26:29.02#ibcon#read 4, iclass 3, count 2 2006.173.17:26:29.02#ibcon#about to read 5, iclass 3, count 2 2006.173.17:26:29.02#ibcon#read 5, iclass 3, count 2 2006.173.17:26:29.02#ibcon#about to read 6, iclass 3, count 2 2006.173.17:26:29.02#ibcon#read 6, iclass 3, count 2 2006.173.17:26:29.02#ibcon#end of sib2, iclass 3, count 2 2006.173.17:26:29.02#ibcon#*mode == 0, iclass 3, count 2 2006.173.17:26:29.02#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.17:26:29.02#ibcon#[25=AT03-05\r\n] 2006.173.17:26:29.02#ibcon#*before write, iclass 3, count 2 2006.173.17:26:29.02#ibcon#enter sib2, iclass 3, count 2 2006.173.17:26:29.02#ibcon#flushed, iclass 3, count 2 2006.173.17:26:29.02#ibcon#about to write, iclass 3, count 2 2006.173.17:26:29.02#ibcon#wrote, iclass 3, count 2 2006.173.17:26:29.02#ibcon#about to read 3, iclass 3, count 2 2006.173.17:26:29.05#ibcon#read 3, iclass 3, count 2 2006.173.17:26:29.05#ibcon#about to read 4, iclass 3, count 2 2006.173.17:26:29.05#ibcon#read 4, iclass 3, count 2 2006.173.17:26:29.05#ibcon#about to read 5, iclass 3, count 2 2006.173.17:26:29.05#ibcon#read 5, iclass 3, count 2 2006.173.17:26:29.05#ibcon#about to read 6, iclass 3, count 2 2006.173.17:26:29.05#ibcon#read 6, iclass 3, count 2 2006.173.17:26:29.05#ibcon#end of sib2, iclass 3, count 2 2006.173.17:26:29.05#ibcon#*after write, iclass 3, count 2 2006.173.17:26:29.05#ibcon#*before return 0, iclass 3, count 2 2006.173.17:26:29.05#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.17:26:29.05#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.17:26:29.05#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.17:26:29.05#ibcon#ireg 7 cls_cnt 0 2006.173.17:26:29.05#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.17:26:29.17#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.17:26:29.17#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.17:26:29.17#ibcon#enter wrdev, iclass 3, count 0 2006.173.17:26:29.17#ibcon#first serial, iclass 3, count 0 2006.173.17:26:29.17#ibcon#enter sib2, iclass 3, count 0 2006.173.17:26:29.17#ibcon#flushed, iclass 3, count 0 2006.173.17:26:29.17#ibcon#about to write, iclass 3, count 0 2006.173.17:26:29.17#ibcon#wrote, iclass 3, count 0 2006.173.17:26:29.17#ibcon#about to read 3, iclass 3, count 0 2006.173.17:26:29.19#ibcon#read 3, iclass 3, count 0 2006.173.17:26:29.19#ibcon#about to read 4, iclass 3, count 0 2006.173.17:26:29.19#ibcon#read 4, iclass 3, count 0 2006.173.17:26:29.19#ibcon#about to read 5, iclass 3, count 0 2006.173.17:26:29.19#ibcon#read 5, iclass 3, count 0 2006.173.17:26:29.19#ibcon#about to read 6, iclass 3, count 0 2006.173.17:26:29.19#ibcon#read 6, iclass 3, count 0 2006.173.17:26:29.19#ibcon#end of sib2, iclass 3, count 0 2006.173.17:26:29.19#ibcon#*mode == 0, iclass 3, count 0 2006.173.17:26:29.19#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.17:26:29.19#ibcon#[25=USB\r\n] 2006.173.17:26:29.19#ibcon#*before write, iclass 3, count 0 2006.173.17:26:29.19#ibcon#enter sib2, iclass 3, count 0 2006.173.17:26:29.19#ibcon#flushed, iclass 3, count 0 2006.173.17:26:29.19#ibcon#about to write, iclass 3, count 0 2006.173.17:26:29.19#ibcon#wrote, iclass 3, count 0 2006.173.17:26:29.19#ibcon#about to read 3, iclass 3, count 0 2006.173.17:26:29.22#ibcon#read 3, iclass 3, count 0 2006.173.17:26:29.22#ibcon#about to read 4, iclass 3, count 0 2006.173.17:26:29.22#ibcon#read 4, iclass 3, count 0 2006.173.17:26:29.22#ibcon#about to read 5, iclass 3, count 0 2006.173.17:26:29.22#ibcon#read 5, iclass 3, count 0 2006.173.17:26:29.22#ibcon#about to read 6, iclass 3, count 0 2006.173.17:26:29.22#ibcon#read 6, iclass 3, count 0 2006.173.17:26:29.22#ibcon#end of sib2, iclass 3, count 0 2006.173.17:26:29.22#ibcon#*after write, iclass 3, count 0 2006.173.17:26:29.22#ibcon#*before return 0, iclass 3, count 0 2006.173.17:26:29.22#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.17:26:29.22#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.17:26:29.22#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.17:26:29.22#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.17:26:29.22$vck44/valo=4,624.99 2006.173.17:26:29.22#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.17:26:29.22#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.17:26:29.22#ibcon#ireg 17 cls_cnt 0 2006.173.17:26:29.22#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.17:26:29.22#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.17:26:29.22#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.17:26:29.22#ibcon#enter wrdev, iclass 5, count 0 2006.173.17:26:29.22#ibcon#first serial, iclass 5, count 0 2006.173.17:26:29.22#ibcon#enter sib2, iclass 5, count 0 2006.173.17:26:29.22#ibcon#flushed, iclass 5, count 0 2006.173.17:26:29.22#ibcon#about to write, iclass 5, count 0 2006.173.17:26:29.22#ibcon#wrote, iclass 5, count 0 2006.173.17:26:29.22#ibcon#about to read 3, iclass 5, count 0 2006.173.17:26:29.24#ibcon#read 3, iclass 5, count 0 2006.173.17:26:29.24#ibcon#about to read 4, iclass 5, count 0 2006.173.17:26:29.24#ibcon#read 4, iclass 5, count 0 2006.173.17:26:29.24#ibcon#about to read 5, iclass 5, count 0 2006.173.17:26:29.24#ibcon#read 5, iclass 5, count 0 2006.173.17:26:29.24#ibcon#about to read 6, iclass 5, count 0 2006.173.17:26:29.24#ibcon#read 6, iclass 5, count 0 2006.173.17:26:29.24#ibcon#end of sib2, iclass 5, count 0 2006.173.17:26:29.24#ibcon#*mode == 0, iclass 5, count 0 2006.173.17:26:29.24#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.17:26:29.24#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.17:26:29.24#ibcon#*before write, iclass 5, count 0 2006.173.17:26:29.24#ibcon#enter sib2, iclass 5, count 0 2006.173.17:26:29.24#ibcon#flushed, iclass 5, count 0 2006.173.17:26:29.24#ibcon#about to write, iclass 5, count 0 2006.173.17:26:29.24#ibcon#wrote, iclass 5, count 0 2006.173.17:26:29.24#ibcon#about to read 3, iclass 5, count 0 2006.173.17:26:29.28#ibcon#read 3, iclass 5, count 0 2006.173.17:26:29.28#ibcon#about to read 4, iclass 5, count 0 2006.173.17:26:29.28#ibcon#read 4, iclass 5, count 0 2006.173.17:26:29.28#ibcon#about to read 5, iclass 5, count 0 2006.173.17:26:29.28#ibcon#read 5, iclass 5, count 0 2006.173.17:26:29.28#ibcon#about to read 6, iclass 5, count 0 2006.173.17:26:29.28#ibcon#read 6, iclass 5, count 0 2006.173.17:26:29.28#ibcon#end of sib2, iclass 5, count 0 2006.173.17:26:29.28#ibcon#*after write, iclass 5, count 0 2006.173.17:26:29.28#ibcon#*before return 0, iclass 5, count 0 2006.173.17:26:29.28#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.17:26:29.28#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.17:26:29.28#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.17:26:29.28#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.17:26:29.28$vck44/va=4,6 2006.173.17:26:29.28#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.173.17:26:29.28#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.173.17:26:29.28#ibcon#ireg 11 cls_cnt 2 2006.173.17:26:29.28#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.17:26:29.34#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.17:26:29.34#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.17:26:29.34#ibcon#enter wrdev, iclass 7, count 2 2006.173.17:26:29.34#ibcon#first serial, iclass 7, count 2 2006.173.17:26:29.34#ibcon#enter sib2, iclass 7, count 2 2006.173.17:26:29.34#ibcon#flushed, iclass 7, count 2 2006.173.17:26:29.34#ibcon#about to write, iclass 7, count 2 2006.173.17:26:29.34#ibcon#wrote, iclass 7, count 2 2006.173.17:26:29.34#ibcon#about to read 3, iclass 7, count 2 2006.173.17:26:29.36#ibcon#read 3, iclass 7, count 2 2006.173.17:26:29.36#ibcon#about to read 4, iclass 7, count 2 2006.173.17:26:29.36#ibcon#read 4, iclass 7, count 2 2006.173.17:26:29.36#ibcon#about to read 5, iclass 7, count 2 2006.173.17:26:29.36#ibcon#read 5, iclass 7, count 2 2006.173.17:26:29.36#ibcon#about to read 6, iclass 7, count 2 2006.173.17:26:29.36#ibcon#read 6, iclass 7, count 2 2006.173.17:26:29.36#ibcon#end of sib2, iclass 7, count 2 2006.173.17:26:29.36#ibcon#*mode == 0, iclass 7, count 2 2006.173.17:26:29.36#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.173.17:26:29.36#ibcon#[25=AT04-06\r\n] 2006.173.17:26:29.36#ibcon#*before write, iclass 7, count 2 2006.173.17:26:29.36#ibcon#enter sib2, iclass 7, count 2 2006.173.17:26:29.36#ibcon#flushed, iclass 7, count 2 2006.173.17:26:29.36#ibcon#about to write, iclass 7, count 2 2006.173.17:26:29.36#ibcon#wrote, iclass 7, count 2 2006.173.17:26:29.36#ibcon#about to read 3, iclass 7, count 2 2006.173.17:26:29.39#ibcon#read 3, iclass 7, count 2 2006.173.17:26:29.39#ibcon#about to read 4, iclass 7, count 2 2006.173.17:26:29.39#ibcon#read 4, iclass 7, count 2 2006.173.17:26:29.39#ibcon#about to read 5, iclass 7, count 2 2006.173.17:26:29.39#ibcon#read 5, iclass 7, count 2 2006.173.17:26:29.39#ibcon#about to read 6, iclass 7, count 2 2006.173.17:26:29.39#ibcon#read 6, iclass 7, count 2 2006.173.17:26:29.39#ibcon#end of sib2, iclass 7, count 2 2006.173.17:26:29.39#ibcon#*after write, iclass 7, count 2 2006.173.17:26:29.39#ibcon#*before return 0, iclass 7, count 2 2006.173.17:26:29.39#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.17:26:29.39#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.173.17:26:29.39#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.173.17:26:29.39#ibcon#ireg 7 cls_cnt 0 2006.173.17:26:29.39#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.17:26:29.51#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.17:26:29.51#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.17:26:29.51#ibcon#enter wrdev, iclass 7, count 0 2006.173.17:26:29.51#ibcon#first serial, iclass 7, count 0 2006.173.17:26:29.51#ibcon#enter sib2, iclass 7, count 0 2006.173.17:26:29.51#ibcon#flushed, iclass 7, count 0 2006.173.17:26:29.51#ibcon#about to write, iclass 7, count 0 2006.173.17:26:29.51#ibcon#wrote, iclass 7, count 0 2006.173.17:26:29.51#ibcon#about to read 3, iclass 7, count 0 2006.173.17:26:29.53#ibcon#read 3, iclass 7, count 0 2006.173.17:26:29.53#ibcon#about to read 4, iclass 7, count 0 2006.173.17:26:29.53#ibcon#read 4, iclass 7, count 0 2006.173.17:26:29.53#ibcon#about to read 5, iclass 7, count 0 2006.173.17:26:29.53#ibcon#read 5, iclass 7, count 0 2006.173.17:26:29.53#ibcon#about to read 6, iclass 7, count 0 2006.173.17:26:29.53#ibcon#read 6, iclass 7, count 0 2006.173.17:26:29.53#ibcon#end of sib2, iclass 7, count 0 2006.173.17:26:29.53#ibcon#*mode == 0, iclass 7, count 0 2006.173.17:26:29.53#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.17:26:29.53#ibcon#[25=USB\r\n] 2006.173.17:26:29.53#ibcon#*before write, iclass 7, count 0 2006.173.17:26:29.53#ibcon#enter sib2, iclass 7, count 0 2006.173.17:26:29.53#ibcon#flushed, iclass 7, count 0 2006.173.17:26:29.53#ibcon#about to write, iclass 7, count 0 2006.173.17:26:29.53#ibcon#wrote, iclass 7, count 0 2006.173.17:26:29.53#ibcon#about to read 3, iclass 7, count 0 2006.173.17:26:29.56#ibcon#read 3, iclass 7, count 0 2006.173.17:26:29.56#ibcon#about to read 4, iclass 7, count 0 2006.173.17:26:29.56#ibcon#read 4, iclass 7, count 0 2006.173.17:26:29.56#ibcon#about to read 5, iclass 7, count 0 2006.173.17:26:29.56#ibcon#read 5, iclass 7, count 0 2006.173.17:26:29.56#ibcon#about to read 6, iclass 7, count 0 2006.173.17:26:29.56#ibcon#read 6, iclass 7, count 0 2006.173.17:26:29.56#ibcon#end of sib2, iclass 7, count 0 2006.173.17:26:29.56#ibcon#*after write, iclass 7, count 0 2006.173.17:26:29.56#ibcon#*before return 0, iclass 7, count 0 2006.173.17:26:29.56#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.17:26:29.56#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.173.17:26:29.56#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.17:26:29.56#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.17:26:29.56$vck44/valo=5,734.99 2006.173.17:26:29.56#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.17:26:29.56#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.17:26:29.56#ibcon#ireg 17 cls_cnt 0 2006.173.17:26:29.56#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.17:26:29.56#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.17:26:29.56#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.17:26:29.56#ibcon#enter wrdev, iclass 11, count 0 2006.173.17:26:29.56#ibcon#first serial, iclass 11, count 0 2006.173.17:26:29.56#ibcon#enter sib2, iclass 11, count 0 2006.173.17:26:29.56#ibcon#flushed, iclass 11, count 0 2006.173.17:26:29.56#ibcon#about to write, iclass 11, count 0 2006.173.17:26:29.56#ibcon#wrote, iclass 11, count 0 2006.173.17:26:29.56#ibcon#about to read 3, iclass 11, count 0 2006.173.17:26:29.58#ibcon#read 3, iclass 11, count 0 2006.173.17:26:29.58#ibcon#about to read 4, iclass 11, count 0 2006.173.17:26:29.58#ibcon#read 4, iclass 11, count 0 2006.173.17:26:29.58#ibcon#about to read 5, iclass 11, count 0 2006.173.17:26:29.58#ibcon#read 5, iclass 11, count 0 2006.173.17:26:29.58#ibcon#about to read 6, iclass 11, count 0 2006.173.17:26:29.58#ibcon#read 6, iclass 11, count 0 2006.173.17:26:29.58#ibcon#end of sib2, iclass 11, count 0 2006.173.17:26:29.58#ibcon#*mode == 0, iclass 11, count 0 2006.173.17:26:29.58#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.17:26:29.58#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.17:26:29.58#ibcon#*before write, iclass 11, count 0 2006.173.17:26:29.58#ibcon#enter sib2, iclass 11, count 0 2006.173.17:26:29.58#ibcon#flushed, iclass 11, count 0 2006.173.17:26:29.58#ibcon#about to write, iclass 11, count 0 2006.173.17:26:29.58#ibcon#wrote, iclass 11, count 0 2006.173.17:26:29.58#ibcon#about to read 3, iclass 11, count 0 2006.173.17:26:29.62#ibcon#read 3, iclass 11, count 0 2006.173.17:26:29.62#ibcon#about to read 4, iclass 11, count 0 2006.173.17:26:29.62#ibcon#read 4, iclass 11, count 0 2006.173.17:26:29.62#ibcon#about to read 5, iclass 11, count 0 2006.173.17:26:29.62#ibcon#read 5, iclass 11, count 0 2006.173.17:26:29.62#ibcon#about to read 6, iclass 11, count 0 2006.173.17:26:29.62#ibcon#read 6, iclass 11, count 0 2006.173.17:26:29.62#ibcon#end of sib2, iclass 11, count 0 2006.173.17:26:29.62#ibcon#*after write, iclass 11, count 0 2006.173.17:26:29.62#ibcon#*before return 0, iclass 11, count 0 2006.173.17:26:29.62#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.17:26:29.62#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.17:26:29.62#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.17:26:29.62#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.17:26:29.62$vck44/va=5,4 2006.173.17:26:29.62#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.173.17:26:29.62#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.173.17:26:29.62#ibcon#ireg 11 cls_cnt 2 2006.173.17:26:29.62#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.17:26:29.68#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.17:26:29.68#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.17:26:29.68#ibcon#enter wrdev, iclass 13, count 2 2006.173.17:26:29.68#ibcon#first serial, iclass 13, count 2 2006.173.17:26:29.68#ibcon#enter sib2, iclass 13, count 2 2006.173.17:26:29.68#ibcon#flushed, iclass 13, count 2 2006.173.17:26:29.68#ibcon#about to write, iclass 13, count 2 2006.173.17:26:29.68#ibcon#wrote, iclass 13, count 2 2006.173.17:26:29.68#ibcon#about to read 3, iclass 13, count 2 2006.173.17:26:29.70#ibcon#read 3, iclass 13, count 2 2006.173.17:26:29.70#ibcon#about to read 4, iclass 13, count 2 2006.173.17:26:29.70#ibcon#read 4, iclass 13, count 2 2006.173.17:26:29.70#ibcon#about to read 5, iclass 13, count 2 2006.173.17:26:29.70#ibcon#read 5, iclass 13, count 2 2006.173.17:26:29.70#ibcon#about to read 6, iclass 13, count 2 2006.173.17:26:29.70#ibcon#read 6, iclass 13, count 2 2006.173.17:26:29.70#ibcon#end of sib2, iclass 13, count 2 2006.173.17:26:29.70#ibcon#*mode == 0, iclass 13, count 2 2006.173.17:26:29.70#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.173.17:26:29.70#ibcon#[25=AT05-04\r\n] 2006.173.17:26:29.70#ibcon#*before write, iclass 13, count 2 2006.173.17:26:29.70#ibcon#enter sib2, iclass 13, count 2 2006.173.17:26:29.70#ibcon#flushed, iclass 13, count 2 2006.173.17:26:29.70#ibcon#about to write, iclass 13, count 2 2006.173.17:26:29.70#ibcon#wrote, iclass 13, count 2 2006.173.17:26:29.70#ibcon#about to read 3, iclass 13, count 2 2006.173.17:26:29.73#ibcon#read 3, iclass 13, count 2 2006.173.17:26:29.73#ibcon#about to read 4, iclass 13, count 2 2006.173.17:26:29.73#ibcon#read 4, iclass 13, count 2 2006.173.17:26:29.73#ibcon#about to read 5, iclass 13, count 2 2006.173.17:26:29.73#ibcon#read 5, iclass 13, count 2 2006.173.17:26:29.73#ibcon#about to read 6, iclass 13, count 2 2006.173.17:26:29.73#ibcon#read 6, iclass 13, count 2 2006.173.17:26:29.73#ibcon#end of sib2, iclass 13, count 2 2006.173.17:26:29.73#ibcon#*after write, iclass 13, count 2 2006.173.17:26:29.73#ibcon#*before return 0, iclass 13, count 2 2006.173.17:26:29.73#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.17:26:29.73#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.173.17:26:29.73#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.173.17:26:29.73#ibcon#ireg 7 cls_cnt 0 2006.173.17:26:29.73#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.17:26:29.85#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.17:26:29.85#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.17:26:29.85#ibcon#enter wrdev, iclass 13, count 0 2006.173.17:26:29.85#ibcon#first serial, iclass 13, count 0 2006.173.17:26:29.85#ibcon#enter sib2, iclass 13, count 0 2006.173.17:26:29.85#ibcon#flushed, iclass 13, count 0 2006.173.17:26:29.85#ibcon#about to write, iclass 13, count 0 2006.173.17:26:29.85#ibcon#wrote, iclass 13, count 0 2006.173.17:26:29.85#ibcon#about to read 3, iclass 13, count 0 2006.173.17:26:29.87#ibcon#read 3, iclass 13, count 0 2006.173.17:26:29.87#ibcon#about to read 4, iclass 13, count 0 2006.173.17:26:29.87#ibcon#read 4, iclass 13, count 0 2006.173.17:26:29.87#ibcon#about to read 5, iclass 13, count 0 2006.173.17:26:29.87#ibcon#read 5, iclass 13, count 0 2006.173.17:26:29.87#ibcon#about to read 6, iclass 13, count 0 2006.173.17:26:29.87#ibcon#read 6, iclass 13, count 0 2006.173.17:26:29.87#ibcon#end of sib2, iclass 13, count 0 2006.173.17:26:29.87#ibcon#*mode == 0, iclass 13, count 0 2006.173.17:26:29.87#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.17:26:29.87#ibcon#[25=USB\r\n] 2006.173.17:26:29.87#ibcon#*before write, iclass 13, count 0 2006.173.17:26:29.87#ibcon#enter sib2, iclass 13, count 0 2006.173.17:26:29.87#ibcon#flushed, iclass 13, count 0 2006.173.17:26:29.87#ibcon#about to write, iclass 13, count 0 2006.173.17:26:29.87#ibcon#wrote, iclass 13, count 0 2006.173.17:26:29.87#ibcon#about to read 3, iclass 13, count 0 2006.173.17:26:29.90#ibcon#read 3, iclass 13, count 0 2006.173.17:26:29.90#ibcon#about to read 4, iclass 13, count 0 2006.173.17:26:29.90#ibcon#read 4, iclass 13, count 0 2006.173.17:26:29.90#ibcon#about to read 5, iclass 13, count 0 2006.173.17:26:29.90#ibcon#read 5, iclass 13, count 0 2006.173.17:26:29.90#ibcon#about to read 6, iclass 13, count 0 2006.173.17:26:29.90#ibcon#read 6, iclass 13, count 0 2006.173.17:26:29.90#ibcon#end of sib2, iclass 13, count 0 2006.173.17:26:29.90#ibcon#*after write, iclass 13, count 0 2006.173.17:26:29.90#ibcon#*before return 0, iclass 13, count 0 2006.173.17:26:29.90#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.17:26:29.90#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.173.17:26:29.90#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.17:26:29.90#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.17:26:29.90$vck44/valo=6,814.99 2006.173.17:26:29.90#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.17:26:29.90#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.17:26:29.90#ibcon#ireg 17 cls_cnt 0 2006.173.17:26:29.90#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.17:26:29.90#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.17:26:29.90#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.17:26:29.90#ibcon#enter wrdev, iclass 15, count 0 2006.173.17:26:29.90#ibcon#first serial, iclass 15, count 0 2006.173.17:26:29.90#ibcon#enter sib2, iclass 15, count 0 2006.173.17:26:29.90#ibcon#flushed, iclass 15, count 0 2006.173.17:26:29.90#ibcon#about to write, iclass 15, count 0 2006.173.17:26:29.90#ibcon#wrote, iclass 15, count 0 2006.173.17:26:29.90#ibcon#about to read 3, iclass 15, count 0 2006.173.17:26:29.92#ibcon#read 3, iclass 15, count 0 2006.173.17:26:29.92#ibcon#about to read 4, iclass 15, count 0 2006.173.17:26:29.92#ibcon#read 4, iclass 15, count 0 2006.173.17:26:29.92#ibcon#about to read 5, iclass 15, count 0 2006.173.17:26:29.92#ibcon#read 5, iclass 15, count 0 2006.173.17:26:29.92#ibcon#about to read 6, iclass 15, count 0 2006.173.17:26:29.92#ibcon#read 6, iclass 15, count 0 2006.173.17:26:29.92#ibcon#end of sib2, iclass 15, count 0 2006.173.17:26:29.92#ibcon#*mode == 0, iclass 15, count 0 2006.173.17:26:29.92#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.17:26:29.92#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.17:26:29.92#ibcon#*before write, iclass 15, count 0 2006.173.17:26:29.92#ibcon#enter sib2, iclass 15, count 0 2006.173.17:26:29.92#ibcon#flushed, iclass 15, count 0 2006.173.17:26:29.92#ibcon#about to write, iclass 15, count 0 2006.173.17:26:29.92#ibcon#wrote, iclass 15, count 0 2006.173.17:26:29.92#ibcon#about to read 3, iclass 15, count 0 2006.173.17:26:29.96#ibcon#read 3, iclass 15, count 0 2006.173.17:26:29.96#ibcon#about to read 4, iclass 15, count 0 2006.173.17:26:29.96#ibcon#read 4, iclass 15, count 0 2006.173.17:26:29.96#ibcon#about to read 5, iclass 15, count 0 2006.173.17:26:29.96#ibcon#read 5, iclass 15, count 0 2006.173.17:26:29.96#ibcon#about to read 6, iclass 15, count 0 2006.173.17:26:29.96#ibcon#read 6, iclass 15, count 0 2006.173.17:26:29.96#ibcon#end of sib2, iclass 15, count 0 2006.173.17:26:29.96#ibcon#*after write, iclass 15, count 0 2006.173.17:26:29.96#ibcon#*before return 0, iclass 15, count 0 2006.173.17:26:29.96#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.17:26:29.96#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.17:26:29.96#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.17:26:29.96#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.17:26:29.96$vck44/va=6,3 2006.173.17:26:29.96#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.17:26:29.96#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.17:26:29.96#ibcon#ireg 11 cls_cnt 2 2006.173.17:26:29.96#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.17:26:30.02#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.17:26:30.02#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.17:26:30.02#ibcon#enter wrdev, iclass 17, count 2 2006.173.17:26:30.02#ibcon#first serial, iclass 17, count 2 2006.173.17:26:30.02#ibcon#enter sib2, iclass 17, count 2 2006.173.17:26:30.02#ibcon#flushed, iclass 17, count 2 2006.173.17:26:30.02#ibcon#about to write, iclass 17, count 2 2006.173.17:26:30.02#ibcon#wrote, iclass 17, count 2 2006.173.17:26:30.02#ibcon#about to read 3, iclass 17, count 2 2006.173.17:26:30.04#ibcon#read 3, iclass 17, count 2 2006.173.17:26:30.04#ibcon#about to read 4, iclass 17, count 2 2006.173.17:26:30.04#ibcon#read 4, iclass 17, count 2 2006.173.17:26:30.04#ibcon#about to read 5, iclass 17, count 2 2006.173.17:26:30.04#ibcon#read 5, iclass 17, count 2 2006.173.17:26:30.04#ibcon#about to read 6, iclass 17, count 2 2006.173.17:26:30.04#ibcon#read 6, iclass 17, count 2 2006.173.17:26:30.04#ibcon#end of sib2, iclass 17, count 2 2006.173.17:26:30.04#ibcon#*mode == 0, iclass 17, count 2 2006.173.17:26:30.04#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.17:26:30.04#ibcon#[25=AT06-03\r\n] 2006.173.17:26:30.04#ibcon#*before write, iclass 17, count 2 2006.173.17:26:30.04#ibcon#enter sib2, iclass 17, count 2 2006.173.17:26:30.04#ibcon#flushed, iclass 17, count 2 2006.173.17:26:30.04#ibcon#about to write, iclass 17, count 2 2006.173.17:26:30.04#ibcon#wrote, iclass 17, count 2 2006.173.17:26:30.04#ibcon#about to read 3, iclass 17, count 2 2006.173.17:26:30.07#ibcon#read 3, iclass 17, count 2 2006.173.17:26:30.07#ibcon#about to read 4, iclass 17, count 2 2006.173.17:26:30.07#ibcon#read 4, iclass 17, count 2 2006.173.17:26:30.07#ibcon#about to read 5, iclass 17, count 2 2006.173.17:26:30.07#ibcon#read 5, iclass 17, count 2 2006.173.17:26:30.07#ibcon#about to read 6, iclass 17, count 2 2006.173.17:26:30.07#ibcon#read 6, iclass 17, count 2 2006.173.17:26:30.07#ibcon#end of sib2, iclass 17, count 2 2006.173.17:26:30.07#ibcon#*after write, iclass 17, count 2 2006.173.17:26:30.07#ibcon#*before return 0, iclass 17, count 2 2006.173.17:26:30.07#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.17:26:30.07#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.17:26:30.07#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.17:26:30.07#ibcon#ireg 7 cls_cnt 0 2006.173.17:26:30.07#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.17:26:30.19#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.17:26:30.19#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.17:26:30.19#ibcon#enter wrdev, iclass 17, count 0 2006.173.17:26:30.19#ibcon#first serial, iclass 17, count 0 2006.173.17:26:30.19#ibcon#enter sib2, iclass 17, count 0 2006.173.17:26:30.19#ibcon#flushed, iclass 17, count 0 2006.173.17:26:30.19#ibcon#about to write, iclass 17, count 0 2006.173.17:26:30.19#ibcon#wrote, iclass 17, count 0 2006.173.17:26:30.19#ibcon#about to read 3, iclass 17, count 0 2006.173.17:26:30.21#ibcon#read 3, iclass 17, count 0 2006.173.17:26:30.21#ibcon#about to read 4, iclass 17, count 0 2006.173.17:26:30.21#ibcon#read 4, iclass 17, count 0 2006.173.17:26:30.21#ibcon#about to read 5, iclass 17, count 0 2006.173.17:26:30.21#ibcon#read 5, iclass 17, count 0 2006.173.17:26:30.21#ibcon#about to read 6, iclass 17, count 0 2006.173.17:26:30.21#ibcon#read 6, iclass 17, count 0 2006.173.17:26:30.21#ibcon#end of sib2, iclass 17, count 0 2006.173.17:26:30.21#ibcon#*mode == 0, iclass 17, count 0 2006.173.17:26:30.21#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.17:26:30.21#ibcon#[25=USB\r\n] 2006.173.17:26:30.21#ibcon#*before write, iclass 17, count 0 2006.173.17:26:30.21#ibcon#enter sib2, iclass 17, count 0 2006.173.17:26:30.21#ibcon#flushed, iclass 17, count 0 2006.173.17:26:30.21#ibcon#about to write, iclass 17, count 0 2006.173.17:26:30.21#ibcon#wrote, iclass 17, count 0 2006.173.17:26:30.21#ibcon#about to read 3, iclass 17, count 0 2006.173.17:26:30.24#ibcon#read 3, iclass 17, count 0 2006.173.17:26:30.24#ibcon#about to read 4, iclass 17, count 0 2006.173.17:26:30.24#ibcon#read 4, iclass 17, count 0 2006.173.17:26:30.24#ibcon#about to read 5, iclass 17, count 0 2006.173.17:26:30.24#ibcon#read 5, iclass 17, count 0 2006.173.17:26:30.24#ibcon#about to read 6, iclass 17, count 0 2006.173.17:26:30.24#ibcon#read 6, iclass 17, count 0 2006.173.17:26:30.24#ibcon#end of sib2, iclass 17, count 0 2006.173.17:26:30.24#ibcon#*after write, iclass 17, count 0 2006.173.17:26:30.24#ibcon#*before return 0, iclass 17, count 0 2006.173.17:26:30.24#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.17:26:30.24#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.17:26:30.24#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.17:26:30.24#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.17:26:30.24$vck44/valo=7,864.99 2006.173.17:26:30.24#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.17:26:30.24#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.17:26:30.24#ibcon#ireg 17 cls_cnt 0 2006.173.17:26:30.24#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.17:26:30.24#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.17:26:30.24#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.17:26:30.24#ibcon#enter wrdev, iclass 19, count 0 2006.173.17:26:30.24#ibcon#first serial, iclass 19, count 0 2006.173.17:26:30.24#ibcon#enter sib2, iclass 19, count 0 2006.173.17:26:30.24#ibcon#flushed, iclass 19, count 0 2006.173.17:26:30.24#ibcon#about to write, iclass 19, count 0 2006.173.17:26:30.24#ibcon#wrote, iclass 19, count 0 2006.173.17:26:30.24#ibcon#about to read 3, iclass 19, count 0 2006.173.17:26:30.26#ibcon#read 3, iclass 19, count 0 2006.173.17:26:30.26#ibcon#about to read 4, iclass 19, count 0 2006.173.17:26:30.26#ibcon#read 4, iclass 19, count 0 2006.173.17:26:30.26#ibcon#about to read 5, iclass 19, count 0 2006.173.17:26:30.26#ibcon#read 5, iclass 19, count 0 2006.173.17:26:30.26#ibcon#about to read 6, iclass 19, count 0 2006.173.17:26:30.26#ibcon#read 6, iclass 19, count 0 2006.173.17:26:30.26#ibcon#end of sib2, iclass 19, count 0 2006.173.17:26:30.26#ibcon#*mode == 0, iclass 19, count 0 2006.173.17:26:30.26#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.17:26:30.26#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.17:26:30.26#ibcon#*before write, iclass 19, count 0 2006.173.17:26:30.26#ibcon#enter sib2, iclass 19, count 0 2006.173.17:26:30.26#ibcon#flushed, iclass 19, count 0 2006.173.17:26:30.26#ibcon#about to write, iclass 19, count 0 2006.173.17:26:30.26#ibcon#wrote, iclass 19, count 0 2006.173.17:26:30.26#ibcon#about to read 3, iclass 19, count 0 2006.173.17:26:30.30#ibcon#read 3, iclass 19, count 0 2006.173.17:26:30.30#ibcon#about to read 4, iclass 19, count 0 2006.173.17:26:30.30#ibcon#read 4, iclass 19, count 0 2006.173.17:26:30.30#ibcon#about to read 5, iclass 19, count 0 2006.173.17:26:30.30#ibcon#read 5, iclass 19, count 0 2006.173.17:26:30.30#ibcon#about to read 6, iclass 19, count 0 2006.173.17:26:30.30#ibcon#read 6, iclass 19, count 0 2006.173.17:26:30.30#ibcon#end of sib2, iclass 19, count 0 2006.173.17:26:30.30#ibcon#*after write, iclass 19, count 0 2006.173.17:26:30.30#ibcon#*before return 0, iclass 19, count 0 2006.173.17:26:30.30#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.17:26:30.30#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.17:26:30.30#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.17:26:30.30#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.17:26:30.30$vck44/va=7,4 2006.173.17:26:30.30#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.17:26:30.30#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.17:26:30.30#ibcon#ireg 11 cls_cnt 2 2006.173.17:26:30.30#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.17:26:30.36#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.17:26:30.36#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.17:26:30.36#ibcon#enter wrdev, iclass 21, count 2 2006.173.17:26:30.36#ibcon#first serial, iclass 21, count 2 2006.173.17:26:30.36#ibcon#enter sib2, iclass 21, count 2 2006.173.17:26:30.36#ibcon#flushed, iclass 21, count 2 2006.173.17:26:30.36#ibcon#about to write, iclass 21, count 2 2006.173.17:26:30.36#ibcon#wrote, iclass 21, count 2 2006.173.17:26:30.36#ibcon#about to read 3, iclass 21, count 2 2006.173.17:26:30.38#ibcon#read 3, iclass 21, count 2 2006.173.17:26:30.38#ibcon#about to read 4, iclass 21, count 2 2006.173.17:26:30.38#ibcon#read 4, iclass 21, count 2 2006.173.17:26:30.38#ibcon#about to read 5, iclass 21, count 2 2006.173.17:26:30.38#ibcon#read 5, iclass 21, count 2 2006.173.17:26:30.38#ibcon#about to read 6, iclass 21, count 2 2006.173.17:26:30.38#ibcon#read 6, iclass 21, count 2 2006.173.17:26:30.38#ibcon#end of sib2, iclass 21, count 2 2006.173.17:26:30.38#ibcon#*mode == 0, iclass 21, count 2 2006.173.17:26:30.38#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.17:26:30.38#ibcon#[25=AT07-04\r\n] 2006.173.17:26:30.38#ibcon#*before write, iclass 21, count 2 2006.173.17:26:30.38#ibcon#enter sib2, iclass 21, count 2 2006.173.17:26:30.38#ibcon#flushed, iclass 21, count 2 2006.173.17:26:30.38#ibcon#about to write, iclass 21, count 2 2006.173.17:26:30.38#ibcon#wrote, iclass 21, count 2 2006.173.17:26:30.38#ibcon#about to read 3, iclass 21, count 2 2006.173.17:26:30.41#ibcon#read 3, iclass 21, count 2 2006.173.17:26:30.41#ibcon#about to read 4, iclass 21, count 2 2006.173.17:26:30.41#ibcon#read 4, iclass 21, count 2 2006.173.17:26:30.41#ibcon#about to read 5, iclass 21, count 2 2006.173.17:26:30.41#ibcon#read 5, iclass 21, count 2 2006.173.17:26:30.41#ibcon#about to read 6, iclass 21, count 2 2006.173.17:26:30.41#ibcon#read 6, iclass 21, count 2 2006.173.17:26:30.41#ibcon#end of sib2, iclass 21, count 2 2006.173.17:26:30.41#ibcon#*after write, iclass 21, count 2 2006.173.17:26:30.41#ibcon#*before return 0, iclass 21, count 2 2006.173.17:26:30.41#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.17:26:30.41#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.17:26:30.41#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.17:26:30.41#ibcon#ireg 7 cls_cnt 0 2006.173.17:26:30.41#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.17:26:30.53#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.17:26:30.53#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.17:26:30.53#ibcon#enter wrdev, iclass 21, count 0 2006.173.17:26:30.53#ibcon#first serial, iclass 21, count 0 2006.173.17:26:30.53#ibcon#enter sib2, iclass 21, count 0 2006.173.17:26:30.53#ibcon#flushed, iclass 21, count 0 2006.173.17:26:30.53#ibcon#about to write, iclass 21, count 0 2006.173.17:26:30.53#ibcon#wrote, iclass 21, count 0 2006.173.17:26:30.53#ibcon#about to read 3, iclass 21, count 0 2006.173.17:26:30.55#ibcon#read 3, iclass 21, count 0 2006.173.17:26:30.55#ibcon#about to read 4, iclass 21, count 0 2006.173.17:26:30.55#ibcon#read 4, iclass 21, count 0 2006.173.17:26:30.55#ibcon#about to read 5, iclass 21, count 0 2006.173.17:26:30.55#ibcon#read 5, iclass 21, count 0 2006.173.17:26:30.55#ibcon#about to read 6, iclass 21, count 0 2006.173.17:26:30.55#ibcon#read 6, iclass 21, count 0 2006.173.17:26:30.55#ibcon#end of sib2, iclass 21, count 0 2006.173.17:26:30.55#ibcon#*mode == 0, iclass 21, count 0 2006.173.17:26:30.55#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.17:26:30.55#ibcon#[25=USB\r\n] 2006.173.17:26:30.55#ibcon#*before write, iclass 21, count 0 2006.173.17:26:30.55#ibcon#enter sib2, iclass 21, count 0 2006.173.17:26:30.55#ibcon#flushed, iclass 21, count 0 2006.173.17:26:30.55#ibcon#about to write, iclass 21, count 0 2006.173.17:26:30.55#ibcon#wrote, iclass 21, count 0 2006.173.17:26:30.55#ibcon#about to read 3, iclass 21, count 0 2006.173.17:26:30.58#ibcon#read 3, iclass 21, count 0 2006.173.17:26:30.58#ibcon#about to read 4, iclass 21, count 0 2006.173.17:26:30.58#ibcon#read 4, iclass 21, count 0 2006.173.17:26:30.58#ibcon#about to read 5, iclass 21, count 0 2006.173.17:26:30.58#ibcon#read 5, iclass 21, count 0 2006.173.17:26:30.58#ibcon#about to read 6, iclass 21, count 0 2006.173.17:26:30.58#ibcon#read 6, iclass 21, count 0 2006.173.17:26:30.58#ibcon#end of sib2, iclass 21, count 0 2006.173.17:26:30.58#ibcon#*after write, iclass 21, count 0 2006.173.17:26:30.58#ibcon#*before return 0, iclass 21, count 0 2006.173.17:26:30.58#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.17:26:30.58#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.17:26:30.58#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.17:26:30.58#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.17:26:30.58$vck44/valo=8,884.99 2006.173.17:26:30.58#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.17:26:30.58#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.17:26:30.58#ibcon#ireg 17 cls_cnt 0 2006.173.17:26:30.58#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.17:26:30.58#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.17:26:30.58#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.17:26:30.58#ibcon#enter wrdev, iclass 23, count 0 2006.173.17:26:30.58#ibcon#first serial, iclass 23, count 0 2006.173.17:26:30.58#ibcon#enter sib2, iclass 23, count 0 2006.173.17:26:30.58#ibcon#flushed, iclass 23, count 0 2006.173.17:26:30.58#ibcon#about to write, iclass 23, count 0 2006.173.17:26:30.58#ibcon#wrote, iclass 23, count 0 2006.173.17:26:30.58#ibcon#about to read 3, iclass 23, count 0 2006.173.17:26:30.60#ibcon#read 3, iclass 23, count 0 2006.173.17:26:30.60#ibcon#about to read 4, iclass 23, count 0 2006.173.17:26:30.60#ibcon#read 4, iclass 23, count 0 2006.173.17:26:30.60#ibcon#about to read 5, iclass 23, count 0 2006.173.17:26:30.60#ibcon#read 5, iclass 23, count 0 2006.173.17:26:30.60#ibcon#about to read 6, iclass 23, count 0 2006.173.17:26:30.60#ibcon#read 6, iclass 23, count 0 2006.173.17:26:30.60#ibcon#end of sib2, iclass 23, count 0 2006.173.17:26:30.60#ibcon#*mode == 0, iclass 23, count 0 2006.173.17:26:30.60#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.17:26:30.60#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.17:26:30.60#ibcon#*before write, iclass 23, count 0 2006.173.17:26:30.60#ibcon#enter sib2, iclass 23, count 0 2006.173.17:26:30.60#ibcon#flushed, iclass 23, count 0 2006.173.17:26:30.60#ibcon#about to write, iclass 23, count 0 2006.173.17:26:30.60#ibcon#wrote, iclass 23, count 0 2006.173.17:26:30.60#ibcon#about to read 3, iclass 23, count 0 2006.173.17:26:30.64#ibcon#read 3, iclass 23, count 0 2006.173.17:26:30.64#ibcon#about to read 4, iclass 23, count 0 2006.173.17:26:30.64#ibcon#read 4, iclass 23, count 0 2006.173.17:26:30.64#ibcon#about to read 5, iclass 23, count 0 2006.173.17:26:30.64#ibcon#read 5, iclass 23, count 0 2006.173.17:26:30.64#ibcon#about to read 6, iclass 23, count 0 2006.173.17:26:30.64#ibcon#read 6, iclass 23, count 0 2006.173.17:26:30.64#ibcon#end of sib2, iclass 23, count 0 2006.173.17:26:30.64#ibcon#*after write, iclass 23, count 0 2006.173.17:26:30.64#ibcon#*before return 0, iclass 23, count 0 2006.173.17:26:30.64#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.17:26:30.64#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.17:26:30.64#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.17:26:30.64#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.17:26:30.64$vck44/va=8,4 2006.173.17:26:30.64#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.17:26:30.64#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.17:26:30.64#ibcon#ireg 11 cls_cnt 2 2006.173.17:26:30.64#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.17:26:30.70#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.17:26:30.70#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.17:26:30.70#ibcon#enter wrdev, iclass 25, count 2 2006.173.17:26:30.70#ibcon#first serial, iclass 25, count 2 2006.173.17:26:30.70#ibcon#enter sib2, iclass 25, count 2 2006.173.17:26:30.70#ibcon#flushed, iclass 25, count 2 2006.173.17:26:30.70#ibcon#about to write, iclass 25, count 2 2006.173.17:26:30.70#ibcon#wrote, iclass 25, count 2 2006.173.17:26:30.70#ibcon#about to read 3, iclass 25, count 2 2006.173.17:26:30.72#ibcon#read 3, iclass 25, count 2 2006.173.17:26:30.72#ibcon#about to read 4, iclass 25, count 2 2006.173.17:26:30.72#ibcon#read 4, iclass 25, count 2 2006.173.17:26:30.72#ibcon#about to read 5, iclass 25, count 2 2006.173.17:26:30.72#ibcon#read 5, iclass 25, count 2 2006.173.17:26:30.72#ibcon#about to read 6, iclass 25, count 2 2006.173.17:26:30.72#ibcon#read 6, iclass 25, count 2 2006.173.17:26:30.72#ibcon#end of sib2, iclass 25, count 2 2006.173.17:26:30.72#ibcon#*mode == 0, iclass 25, count 2 2006.173.17:26:30.72#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.17:26:30.72#ibcon#[25=AT08-04\r\n] 2006.173.17:26:30.72#ibcon#*before write, iclass 25, count 2 2006.173.17:26:30.72#ibcon#enter sib2, iclass 25, count 2 2006.173.17:26:30.72#ibcon#flushed, iclass 25, count 2 2006.173.17:26:30.72#ibcon#about to write, iclass 25, count 2 2006.173.17:26:30.72#ibcon#wrote, iclass 25, count 2 2006.173.17:26:30.72#ibcon#about to read 3, iclass 25, count 2 2006.173.17:26:30.75#ibcon#read 3, iclass 25, count 2 2006.173.17:26:30.75#ibcon#about to read 4, iclass 25, count 2 2006.173.17:26:30.75#ibcon#read 4, iclass 25, count 2 2006.173.17:26:30.75#ibcon#about to read 5, iclass 25, count 2 2006.173.17:26:30.75#ibcon#read 5, iclass 25, count 2 2006.173.17:26:30.75#ibcon#about to read 6, iclass 25, count 2 2006.173.17:26:30.75#ibcon#read 6, iclass 25, count 2 2006.173.17:26:30.75#ibcon#end of sib2, iclass 25, count 2 2006.173.17:26:30.75#ibcon#*after write, iclass 25, count 2 2006.173.17:26:30.75#ibcon#*before return 0, iclass 25, count 2 2006.173.17:26:30.75#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.17:26:30.75#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.17:26:30.75#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.17:26:30.75#ibcon#ireg 7 cls_cnt 0 2006.173.17:26:30.75#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.17:26:30.87#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.17:26:30.87#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.17:26:30.87#ibcon#enter wrdev, iclass 25, count 0 2006.173.17:26:30.87#ibcon#first serial, iclass 25, count 0 2006.173.17:26:30.87#ibcon#enter sib2, iclass 25, count 0 2006.173.17:26:30.87#ibcon#flushed, iclass 25, count 0 2006.173.17:26:30.87#ibcon#about to write, iclass 25, count 0 2006.173.17:26:30.87#ibcon#wrote, iclass 25, count 0 2006.173.17:26:30.87#ibcon#about to read 3, iclass 25, count 0 2006.173.17:26:30.89#ibcon#read 3, iclass 25, count 0 2006.173.17:26:30.89#ibcon#about to read 4, iclass 25, count 0 2006.173.17:26:30.89#ibcon#read 4, iclass 25, count 0 2006.173.17:26:30.89#ibcon#about to read 5, iclass 25, count 0 2006.173.17:26:30.89#ibcon#read 5, iclass 25, count 0 2006.173.17:26:30.89#ibcon#about to read 6, iclass 25, count 0 2006.173.17:26:30.89#ibcon#read 6, iclass 25, count 0 2006.173.17:26:30.89#ibcon#end of sib2, iclass 25, count 0 2006.173.17:26:30.89#ibcon#*mode == 0, iclass 25, count 0 2006.173.17:26:30.89#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.17:26:30.89#ibcon#[25=USB\r\n] 2006.173.17:26:30.89#ibcon#*before write, iclass 25, count 0 2006.173.17:26:30.89#ibcon#enter sib2, iclass 25, count 0 2006.173.17:26:30.89#ibcon#flushed, iclass 25, count 0 2006.173.17:26:30.89#ibcon#about to write, iclass 25, count 0 2006.173.17:26:30.89#ibcon#wrote, iclass 25, count 0 2006.173.17:26:30.89#ibcon#about to read 3, iclass 25, count 0 2006.173.17:26:30.92#ibcon#read 3, iclass 25, count 0 2006.173.17:26:30.92#ibcon#about to read 4, iclass 25, count 0 2006.173.17:26:30.92#ibcon#read 4, iclass 25, count 0 2006.173.17:26:30.92#ibcon#about to read 5, iclass 25, count 0 2006.173.17:26:30.92#ibcon#read 5, iclass 25, count 0 2006.173.17:26:30.92#ibcon#about to read 6, iclass 25, count 0 2006.173.17:26:30.92#ibcon#read 6, iclass 25, count 0 2006.173.17:26:30.92#ibcon#end of sib2, iclass 25, count 0 2006.173.17:26:30.92#ibcon#*after write, iclass 25, count 0 2006.173.17:26:30.92#ibcon#*before return 0, iclass 25, count 0 2006.173.17:26:30.92#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.17:26:30.92#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.17:26:30.92#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.17:26:30.92#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.17:26:30.92$vck44/vblo=1,629.99 2006.173.17:26:30.92#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.17:26:30.92#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.17:26:30.92#ibcon#ireg 17 cls_cnt 0 2006.173.17:26:30.92#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.17:26:30.92#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.17:26:30.92#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.17:26:30.92#ibcon#enter wrdev, iclass 27, count 0 2006.173.17:26:30.92#ibcon#first serial, iclass 27, count 0 2006.173.17:26:30.92#ibcon#enter sib2, iclass 27, count 0 2006.173.17:26:30.92#ibcon#flushed, iclass 27, count 0 2006.173.17:26:30.92#ibcon#about to write, iclass 27, count 0 2006.173.17:26:30.92#ibcon#wrote, iclass 27, count 0 2006.173.17:26:30.92#ibcon#about to read 3, iclass 27, count 0 2006.173.17:26:30.94#ibcon#read 3, iclass 27, count 0 2006.173.17:26:30.94#ibcon#about to read 4, iclass 27, count 0 2006.173.17:26:30.94#ibcon#read 4, iclass 27, count 0 2006.173.17:26:30.94#ibcon#about to read 5, iclass 27, count 0 2006.173.17:26:30.94#ibcon#read 5, iclass 27, count 0 2006.173.17:26:30.94#ibcon#about to read 6, iclass 27, count 0 2006.173.17:26:30.94#ibcon#read 6, iclass 27, count 0 2006.173.17:26:30.94#ibcon#end of sib2, iclass 27, count 0 2006.173.17:26:30.94#ibcon#*mode == 0, iclass 27, count 0 2006.173.17:26:30.94#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.17:26:30.94#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.17:26:30.94#ibcon#*before write, iclass 27, count 0 2006.173.17:26:30.94#ibcon#enter sib2, iclass 27, count 0 2006.173.17:26:30.94#ibcon#flushed, iclass 27, count 0 2006.173.17:26:30.94#ibcon#about to write, iclass 27, count 0 2006.173.17:26:30.94#ibcon#wrote, iclass 27, count 0 2006.173.17:26:30.94#ibcon#about to read 3, iclass 27, count 0 2006.173.17:26:30.98#ibcon#read 3, iclass 27, count 0 2006.173.17:26:30.98#ibcon#about to read 4, iclass 27, count 0 2006.173.17:26:30.98#ibcon#read 4, iclass 27, count 0 2006.173.17:26:30.98#ibcon#about to read 5, iclass 27, count 0 2006.173.17:26:30.98#ibcon#read 5, iclass 27, count 0 2006.173.17:26:30.98#ibcon#about to read 6, iclass 27, count 0 2006.173.17:26:30.98#ibcon#read 6, iclass 27, count 0 2006.173.17:26:30.98#ibcon#end of sib2, iclass 27, count 0 2006.173.17:26:30.98#ibcon#*after write, iclass 27, count 0 2006.173.17:26:30.98#ibcon#*before return 0, iclass 27, count 0 2006.173.17:26:30.98#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.17:26:30.98#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.17:26:30.98#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.17:26:30.98#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.17:26:30.98$vck44/vb=1,4 2006.173.17:26:30.98#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.17:26:30.98#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.17:26:30.98#ibcon#ireg 11 cls_cnt 2 2006.173.17:26:30.98#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.17:26:30.98#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.17:26:30.98#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.17:26:30.98#ibcon#enter wrdev, iclass 29, count 2 2006.173.17:26:30.98#ibcon#first serial, iclass 29, count 2 2006.173.17:26:30.98#ibcon#enter sib2, iclass 29, count 2 2006.173.17:26:30.98#ibcon#flushed, iclass 29, count 2 2006.173.17:26:30.98#ibcon#about to write, iclass 29, count 2 2006.173.17:26:30.98#ibcon#wrote, iclass 29, count 2 2006.173.17:26:30.98#ibcon#about to read 3, iclass 29, count 2 2006.173.17:26:31.00#ibcon#read 3, iclass 29, count 2 2006.173.17:26:31.00#ibcon#about to read 4, iclass 29, count 2 2006.173.17:26:31.00#ibcon#read 4, iclass 29, count 2 2006.173.17:26:31.00#ibcon#about to read 5, iclass 29, count 2 2006.173.17:26:31.00#ibcon#read 5, iclass 29, count 2 2006.173.17:26:31.00#ibcon#about to read 6, iclass 29, count 2 2006.173.17:26:31.00#ibcon#read 6, iclass 29, count 2 2006.173.17:26:31.00#ibcon#end of sib2, iclass 29, count 2 2006.173.17:26:31.00#ibcon#*mode == 0, iclass 29, count 2 2006.173.17:26:31.00#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.17:26:31.00#ibcon#[27=AT01-04\r\n] 2006.173.17:26:31.00#ibcon#*before write, iclass 29, count 2 2006.173.17:26:31.00#ibcon#enter sib2, iclass 29, count 2 2006.173.17:26:31.00#ibcon#flushed, iclass 29, count 2 2006.173.17:26:31.00#ibcon#about to write, iclass 29, count 2 2006.173.17:26:31.00#ibcon#wrote, iclass 29, count 2 2006.173.17:26:31.00#ibcon#about to read 3, iclass 29, count 2 2006.173.17:26:31.03#ibcon#read 3, iclass 29, count 2 2006.173.17:26:31.03#ibcon#about to read 4, iclass 29, count 2 2006.173.17:26:31.03#ibcon#read 4, iclass 29, count 2 2006.173.17:26:31.03#ibcon#about to read 5, iclass 29, count 2 2006.173.17:26:31.03#ibcon#read 5, iclass 29, count 2 2006.173.17:26:31.03#ibcon#about to read 6, iclass 29, count 2 2006.173.17:26:31.03#ibcon#read 6, iclass 29, count 2 2006.173.17:26:31.03#ibcon#end of sib2, iclass 29, count 2 2006.173.17:26:31.03#ibcon#*after write, iclass 29, count 2 2006.173.17:26:31.03#ibcon#*before return 0, iclass 29, count 2 2006.173.17:26:31.03#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.17:26:31.03#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.17:26:31.03#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.17:26:31.03#ibcon#ireg 7 cls_cnt 0 2006.173.17:26:31.03#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.17:26:31.15#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.17:26:31.15#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.17:26:31.15#ibcon#enter wrdev, iclass 29, count 0 2006.173.17:26:31.15#ibcon#first serial, iclass 29, count 0 2006.173.17:26:31.15#ibcon#enter sib2, iclass 29, count 0 2006.173.17:26:31.15#ibcon#flushed, iclass 29, count 0 2006.173.17:26:31.15#ibcon#about to write, iclass 29, count 0 2006.173.17:26:31.15#ibcon#wrote, iclass 29, count 0 2006.173.17:26:31.15#ibcon#about to read 3, iclass 29, count 0 2006.173.17:26:31.17#ibcon#read 3, iclass 29, count 0 2006.173.17:26:31.17#ibcon#about to read 4, iclass 29, count 0 2006.173.17:26:31.17#ibcon#read 4, iclass 29, count 0 2006.173.17:26:31.17#ibcon#about to read 5, iclass 29, count 0 2006.173.17:26:31.17#ibcon#read 5, iclass 29, count 0 2006.173.17:26:31.17#ibcon#about to read 6, iclass 29, count 0 2006.173.17:26:31.17#ibcon#read 6, iclass 29, count 0 2006.173.17:26:31.17#ibcon#end of sib2, iclass 29, count 0 2006.173.17:26:31.17#ibcon#*mode == 0, iclass 29, count 0 2006.173.17:26:31.17#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.17:26:31.17#ibcon#[27=USB\r\n] 2006.173.17:26:31.17#ibcon#*before write, iclass 29, count 0 2006.173.17:26:31.17#ibcon#enter sib2, iclass 29, count 0 2006.173.17:26:31.17#ibcon#flushed, iclass 29, count 0 2006.173.17:26:31.17#ibcon#about to write, iclass 29, count 0 2006.173.17:26:31.17#ibcon#wrote, iclass 29, count 0 2006.173.17:26:31.17#ibcon#about to read 3, iclass 29, count 0 2006.173.17:26:31.20#ibcon#read 3, iclass 29, count 0 2006.173.17:26:31.20#ibcon#about to read 4, iclass 29, count 0 2006.173.17:26:31.20#ibcon#read 4, iclass 29, count 0 2006.173.17:26:31.20#ibcon#about to read 5, iclass 29, count 0 2006.173.17:26:31.20#ibcon#read 5, iclass 29, count 0 2006.173.17:26:31.20#ibcon#about to read 6, iclass 29, count 0 2006.173.17:26:31.20#ibcon#read 6, iclass 29, count 0 2006.173.17:26:31.20#ibcon#end of sib2, iclass 29, count 0 2006.173.17:26:31.20#ibcon#*after write, iclass 29, count 0 2006.173.17:26:31.20#ibcon#*before return 0, iclass 29, count 0 2006.173.17:26:31.20#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.17:26:31.20#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.17:26:31.20#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.17:26:31.20#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.17:26:31.20$vck44/vblo=2,634.99 2006.173.17:26:31.20#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.17:26:31.20#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.17:26:31.20#ibcon#ireg 17 cls_cnt 0 2006.173.17:26:31.20#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.17:26:31.20#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.17:26:31.20#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.17:26:31.20#ibcon#enter wrdev, iclass 31, count 0 2006.173.17:26:31.20#ibcon#first serial, iclass 31, count 0 2006.173.17:26:31.20#ibcon#enter sib2, iclass 31, count 0 2006.173.17:26:31.20#ibcon#flushed, iclass 31, count 0 2006.173.17:26:31.20#ibcon#about to write, iclass 31, count 0 2006.173.17:26:31.20#ibcon#wrote, iclass 31, count 0 2006.173.17:26:31.20#ibcon#about to read 3, iclass 31, count 0 2006.173.17:26:31.22#ibcon#read 3, iclass 31, count 0 2006.173.17:26:31.22#ibcon#about to read 4, iclass 31, count 0 2006.173.17:26:31.22#ibcon#read 4, iclass 31, count 0 2006.173.17:26:31.22#ibcon#about to read 5, iclass 31, count 0 2006.173.17:26:31.22#ibcon#read 5, iclass 31, count 0 2006.173.17:26:31.22#ibcon#about to read 6, iclass 31, count 0 2006.173.17:26:31.22#ibcon#read 6, iclass 31, count 0 2006.173.17:26:31.22#ibcon#end of sib2, iclass 31, count 0 2006.173.17:26:31.22#ibcon#*mode == 0, iclass 31, count 0 2006.173.17:26:31.22#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.17:26:31.22#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.17:26:31.22#ibcon#*before write, iclass 31, count 0 2006.173.17:26:31.22#ibcon#enter sib2, iclass 31, count 0 2006.173.17:26:31.22#ibcon#flushed, iclass 31, count 0 2006.173.17:26:31.22#ibcon#about to write, iclass 31, count 0 2006.173.17:26:31.22#ibcon#wrote, iclass 31, count 0 2006.173.17:26:31.22#ibcon#about to read 3, iclass 31, count 0 2006.173.17:26:31.26#ibcon#read 3, iclass 31, count 0 2006.173.17:26:31.26#ibcon#about to read 4, iclass 31, count 0 2006.173.17:26:31.26#ibcon#read 4, iclass 31, count 0 2006.173.17:26:31.26#ibcon#about to read 5, iclass 31, count 0 2006.173.17:26:31.26#ibcon#read 5, iclass 31, count 0 2006.173.17:26:31.26#ibcon#about to read 6, iclass 31, count 0 2006.173.17:26:31.26#ibcon#read 6, iclass 31, count 0 2006.173.17:26:31.26#ibcon#end of sib2, iclass 31, count 0 2006.173.17:26:31.26#ibcon#*after write, iclass 31, count 0 2006.173.17:26:31.26#ibcon#*before return 0, iclass 31, count 0 2006.173.17:26:31.26#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.17:26:31.26#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.17:26:31.26#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.17:26:31.26#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.17:26:31.26$vck44/vb=2,4 2006.173.17:26:31.26#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.173.17:26:31.26#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.173.17:26:31.26#ibcon#ireg 11 cls_cnt 2 2006.173.17:26:31.26#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.17:26:31.32#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.17:26:31.32#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.17:26:31.32#ibcon#enter wrdev, iclass 33, count 2 2006.173.17:26:31.32#ibcon#first serial, iclass 33, count 2 2006.173.17:26:31.32#ibcon#enter sib2, iclass 33, count 2 2006.173.17:26:31.32#ibcon#flushed, iclass 33, count 2 2006.173.17:26:31.32#ibcon#about to write, iclass 33, count 2 2006.173.17:26:31.32#ibcon#wrote, iclass 33, count 2 2006.173.17:26:31.32#ibcon#about to read 3, iclass 33, count 2 2006.173.17:26:31.34#ibcon#read 3, iclass 33, count 2 2006.173.17:26:31.34#ibcon#about to read 4, iclass 33, count 2 2006.173.17:26:31.34#ibcon#read 4, iclass 33, count 2 2006.173.17:26:31.34#ibcon#about to read 5, iclass 33, count 2 2006.173.17:26:31.34#ibcon#read 5, iclass 33, count 2 2006.173.17:26:31.34#ibcon#about to read 6, iclass 33, count 2 2006.173.17:26:31.34#ibcon#read 6, iclass 33, count 2 2006.173.17:26:31.34#ibcon#end of sib2, iclass 33, count 2 2006.173.17:26:31.34#ibcon#*mode == 0, iclass 33, count 2 2006.173.17:26:31.34#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.173.17:26:31.34#ibcon#[27=AT02-04\r\n] 2006.173.17:26:31.34#ibcon#*before write, iclass 33, count 2 2006.173.17:26:31.34#ibcon#enter sib2, iclass 33, count 2 2006.173.17:26:31.34#ibcon#flushed, iclass 33, count 2 2006.173.17:26:31.34#ibcon#about to write, iclass 33, count 2 2006.173.17:26:31.34#ibcon#wrote, iclass 33, count 2 2006.173.17:26:31.34#ibcon#about to read 3, iclass 33, count 2 2006.173.17:26:31.37#ibcon#read 3, iclass 33, count 2 2006.173.17:26:31.37#ibcon#about to read 4, iclass 33, count 2 2006.173.17:26:31.37#ibcon#read 4, iclass 33, count 2 2006.173.17:26:31.37#ibcon#about to read 5, iclass 33, count 2 2006.173.17:26:31.37#ibcon#read 5, iclass 33, count 2 2006.173.17:26:31.37#ibcon#about to read 6, iclass 33, count 2 2006.173.17:26:31.37#ibcon#read 6, iclass 33, count 2 2006.173.17:26:31.37#ibcon#end of sib2, iclass 33, count 2 2006.173.17:26:31.37#ibcon#*after write, iclass 33, count 2 2006.173.17:26:31.37#ibcon#*before return 0, iclass 33, count 2 2006.173.17:26:31.37#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.17:26:31.37#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.173.17:26:31.37#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.173.17:26:31.37#ibcon#ireg 7 cls_cnt 0 2006.173.17:26:31.37#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.17:26:31.49#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.17:26:31.49#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.17:26:31.49#ibcon#enter wrdev, iclass 33, count 0 2006.173.17:26:31.49#ibcon#first serial, iclass 33, count 0 2006.173.17:26:31.49#ibcon#enter sib2, iclass 33, count 0 2006.173.17:26:31.49#ibcon#flushed, iclass 33, count 0 2006.173.17:26:31.49#ibcon#about to write, iclass 33, count 0 2006.173.17:26:31.49#ibcon#wrote, iclass 33, count 0 2006.173.17:26:31.49#ibcon#about to read 3, iclass 33, count 0 2006.173.17:26:31.51#ibcon#read 3, iclass 33, count 0 2006.173.17:26:31.51#ibcon#about to read 4, iclass 33, count 0 2006.173.17:26:31.51#ibcon#read 4, iclass 33, count 0 2006.173.17:26:31.51#ibcon#about to read 5, iclass 33, count 0 2006.173.17:26:31.51#ibcon#read 5, iclass 33, count 0 2006.173.17:26:31.51#ibcon#about to read 6, iclass 33, count 0 2006.173.17:26:31.51#ibcon#read 6, iclass 33, count 0 2006.173.17:26:31.51#ibcon#end of sib2, iclass 33, count 0 2006.173.17:26:31.51#ibcon#*mode == 0, iclass 33, count 0 2006.173.17:26:31.51#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.17:26:31.51#ibcon#[27=USB\r\n] 2006.173.17:26:31.51#ibcon#*before write, iclass 33, count 0 2006.173.17:26:31.51#ibcon#enter sib2, iclass 33, count 0 2006.173.17:26:31.51#ibcon#flushed, iclass 33, count 0 2006.173.17:26:31.51#ibcon#about to write, iclass 33, count 0 2006.173.17:26:31.51#ibcon#wrote, iclass 33, count 0 2006.173.17:26:31.51#ibcon#about to read 3, iclass 33, count 0 2006.173.17:26:31.54#ibcon#read 3, iclass 33, count 0 2006.173.17:26:31.54#ibcon#about to read 4, iclass 33, count 0 2006.173.17:26:31.54#ibcon#read 4, iclass 33, count 0 2006.173.17:26:31.54#ibcon#about to read 5, iclass 33, count 0 2006.173.17:26:31.54#ibcon#read 5, iclass 33, count 0 2006.173.17:26:31.54#ibcon#about to read 6, iclass 33, count 0 2006.173.17:26:31.54#ibcon#read 6, iclass 33, count 0 2006.173.17:26:31.54#ibcon#end of sib2, iclass 33, count 0 2006.173.17:26:31.54#ibcon#*after write, iclass 33, count 0 2006.173.17:26:31.54#ibcon#*before return 0, iclass 33, count 0 2006.173.17:26:31.54#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.17:26:31.54#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.173.17:26:31.54#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.17:26:31.54#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.17:26:31.54$vck44/vblo=3,649.99 2006.173.17:26:31.54#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.17:26:31.54#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.17:26:31.54#ibcon#ireg 17 cls_cnt 0 2006.173.17:26:31.54#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.17:26:31.54#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.17:26:31.54#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.17:26:31.54#ibcon#enter wrdev, iclass 35, count 0 2006.173.17:26:31.54#ibcon#first serial, iclass 35, count 0 2006.173.17:26:31.54#ibcon#enter sib2, iclass 35, count 0 2006.173.17:26:31.54#ibcon#flushed, iclass 35, count 0 2006.173.17:26:31.54#ibcon#about to write, iclass 35, count 0 2006.173.17:26:31.54#ibcon#wrote, iclass 35, count 0 2006.173.17:26:31.54#ibcon#about to read 3, iclass 35, count 0 2006.173.17:26:31.56#ibcon#read 3, iclass 35, count 0 2006.173.17:26:31.56#ibcon#about to read 4, iclass 35, count 0 2006.173.17:26:31.56#ibcon#read 4, iclass 35, count 0 2006.173.17:26:31.56#ibcon#about to read 5, iclass 35, count 0 2006.173.17:26:31.56#ibcon#read 5, iclass 35, count 0 2006.173.17:26:31.56#ibcon#about to read 6, iclass 35, count 0 2006.173.17:26:31.56#ibcon#read 6, iclass 35, count 0 2006.173.17:26:31.56#ibcon#end of sib2, iclass 35, count 0 2006.173.17:26:31.56#ibcon#*mode == 0, iclass 35, count 0 2006.173.17:26:31.56#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.17:26:31.56#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.17:26:31.56#ibcon#*before write, iclass 35, count 0 2006.173.17:26:31.56#ibcon#enter sib2, iclass 35, count 0 2006.173.17:26:31.56#ibcon#flushed, iclass 35, count 0 2006.173.17:26:31.56#ibcon#about to write, iclass 35, count 0 2006.173.17:26:31.56#ibcon#wrote, iclass 35, count 0 2006.173.17:26:31.56#ibcon#about to read 3, iclass 35, count 0 2006.173.17:26:31.60#ibcon#read 3, iclass 35, count 0 2006.173.17:26:31.60#ibcon#about to read 4, iclass 35, count 0 2006.173.17:26:31.60#ibcon#read 4, iclass 35, count 0 2006.173.17:26:31.60#ibcon#about to read 5, iclass 35, count 0 2006.173.17:26:31.60#ibcon#read 5, iclass 35, count 0 2006.173.17:26:31.60#ibcon#about to read 6, iclass 35, count 0 2006.173.17:26:31.60#ibcon#read 6, iclass 35, count 0 2006.173.17:26:31.60#ibcon#end of sib2, iclass 35, count 0 2006.173.17:26:31.60#ibcon#*after write, iclass 35, count 0 2006.173.17:26:31.60#ibcon#*before return 0, iclass 35, count 0 2006.173.17:26:31.60#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.17:26:31.60#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.17:26:31.60#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.17:26:31.60#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.17:26:31.60$vck44/vb=3,4 2006.173.17:26:31.60#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.173.17:26:31.60#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.173.17:26:31.60#ibcon#ireg 11 cls_cnt 2 2006.173.17:26:31.60#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.17:26:31.66#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.17:26:31.66#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.17:26:31.66#ibcon#enter wrdev, iclass 37, count 2 2006.173.17:26:31.66#ibcon#first serial, iclass 37, count 2 2006.173.17:26:31.66#ibcon#enter sib2, iclass 37, count 2 2006.173.17:26:31.66#ibcon#flushed, iclass 37, count 2 2006.173.17:26:31.66#ibcon#about to write, iclass 37, count 2 2006.173.17:26:31.66#ibcon#wrote, iclass 37, count 2 2006.173.17:26:31.66#ibcon#about to read 3, iclass 37, count 2 2006.173.17:26:31.68#ibcon#read 3, iclass 37, count 2 2006.173.17:26:31.68#ibcon#about to read 4, iclass 37, count 2 2006.173.17:26:31.68#ibcon#read 4, iclass 37, count 2 2006.173.17:26:31.68#ibcon#about to read 5, iclass 37, count 2 2006.173.17:26:31.68#ibcon#read 5, iclass 37, count 2 2006.173.17:26:31.68#ibcon#about to read 6, iclass 37, count 2 2006.173.17:26:31.68#ibcon#read 6, iclass 37, count 2 2006.173.17:26:31.68#ibcon#end of sib2, iclass 37, count 2 2006.173.17:26:31.68#ibcon#*mode == 0, iclass 37, count 2 2006.173.17:26:31.68#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.173.17:26:31.68#ibcon#[27=AT03-04\r\n] 2006.173.17:26:31.68#ibcon#*before write, iclass 37, count 2 2006.173.17:26:31.68#ibcon#enter sib2, iclass 37, count 2 2006.173.17:26:31.68#ibcon#flushed, iclass 37, count 2 2006.173.17:26:31.68#ibcon#about to write, iclass 37, count 2 2006.173.17:26:31.68#ibcon#wrote, iclass 37, count 2 2006.173.17:26:31.68#ibcon#about to read 3, iclass 37, count 2 2006.173.17:26:31.71#ibcon#read 3, iclass 37, count 2 2006.173.17:26:31.71#ibcon#about to read 4, iclass 37, count 2 2006.173.17:26:31.71#ibcon#read 4, iclass 37, count 2 2006.173.17:26:31.71#ibcon#about to read 5, iclass 37, count 2 2006.173.17:26:31.71#ibcon#read 5, iclass 37, count 2 2006.173.17:26:31.71#ibcon#about to read 6, iclass 37, count 2 2006.173.17:26:31.71#ibcon#read 6, iclass 37, count 2 2006.173.17:26:31.71#ibcon#end of sib2, iclass 37, count 2 2006.173.17:26:31.71#ibcon#*after write, iclass 37, count 2 2006.173.17:26:31.71#ibcon#*before return 0, iclass 37, count 2 2006.173.17:26:31.71#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.17:26:31.71#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.173.17:26:31.71#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.173.17:26:31.71#ibcon#ireg 7 cls_cnt 0 2006.173.17:26:31.71#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.17:26:31.83#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.17:26:31.83#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.17:26:31.83#ibcon#enter wrdev, iclass 37, count 0 2006.173.17:26:31.83#ibcon#first serial, iclass 37, count 0 2006.173.17:26:31.83#ibcon#enter sib2, iclass 37, count 0 2006.173.17:26:31.83#ibcon#flushed, iclass 37, count 0 2006.173.17:26:31.83#ibcon#about to write, iclass 37, count 0 2006.173.17:26:31.83#ibcon#wrote, iclass 37, count 0 2006.173.17:26:31.83#ibcon#about to read 3, iclass 37, count 0 2006.173.17:26:31.85#ibcon#read 3, iclass 37, count 0 2006.173.17:26:31.85#ibcon#about to read 4, iclass 37, count 0 2006.173.17:26:31.85#ibcon#read 4, iclass 37, count 0 2006.173.17:26:31.85#ibcon#about to read 5, iclass 37, count 0 2006.173.17:26:31.85#ibcon#read 5, iclass 37, count 0 2006.173.17:26:31.85#ibcon#about to read 6, iclass 37, count 0 2006.173.17:26:31.85#ibcon#read 6, iclass 37, count 0 2006.173.17:26:31.85#ibcon#end of sib2, iclass 37, count 0 2006.173.17:26:31.85#ibcon#*mode == 0, iclass 37, count 0 2006.173.17:26:31.85#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.17:26:31.85#ibcon#[27=USB\r\n] 2006.173.17:26:31.85#ibcon#*before write, iclass 37, count 0 2006.173.17:26:31.85#ibcon#enter sib2, iclass 37, count 0 2006.173.17:26:31.85#ibcon#flushed, iclass 37, count 0 2006.173.17:26:31.85#ibcon#about to write, iclass 37, count 0 2006.173.17:26:31.85#ibcon#wrote, iclass 37, count 0 2006.173.17:26:31.85#ibcon#about to read 3, iclass 37, count 0 2006.173.17:26:31.88#ibcon#read 3, iclass 37, count 0 2006.173.17:26:31.88#ibcon#about to read 4, iclass 37, count 0 2006.173.17:26:31.88#ibcon#read 4, iclass 37, count 0 2006.173.17:26:31.88#ibcon#about to read 5, iclass 37, count 0 2006.173.17:26:31.88#ibcon#read 5, iclass 37, count 0 2006.173.17:26:31.88#ibcon#about to read 6, iclass 37, count 0 2006.173.17:26:31.88#ibcon#read 6, iclass 37, count 0 2006.173.17:26:31.88#ibcon#end of sib2, iclass 37, count 0 2006.173.17:26:31.88#ibcon#*after write, iclass 37, count 0 2006.173.17:26:31.88#ibcon#*before return 0, iclass 37, count 0 2006.173.17:26:31.88#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.17:26:31.88#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.173.17:26:31.88#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.17:26:31.88#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.17:26:31.88$vck44/vblo=4,679.99 2006.173.17:26:31.88#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.17:26:31.88#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.17:26:31.88#ibcon#ireg 17 cls_cnt 0 2006.173.17:26:31.88#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.17:26:31.88#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.17:26:31.88#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.17:26:31.88#ibcon#enter wrdev, iclass 39, count 0 2006.173.17:26:31.88#ibcon#first serial, iclass 39, count 0 2006.173.17:26:31.88#ibcon#enter sib2, iclass 39, count 0 2006.173.17:26:31.88#ibcon#flushed, iclass 39, count 0 2006.173.17:26:31.88#ibcon#about to write, iclass 39, count 0 2006.173.17:26:31.88#ibcon#wrote, iclass 39, count 0 2006.173.17:26:31.88#ibcon#about to read 3, iclass 39, count 0 2006.173.17:26:31.90#ibcon#read 3, iclass 39, count 0 2006.173.17:26:31.90#ibcon#about to read 4, iclass 39, count 0 2006.173.17:26:31.90#ibcon#read 4, iclass 39, count 0 2006.173.17:26:31.90#ibcon#about to read 5, iclass 39, count 0 2006.173.17:26:31.90#ibcon#read 5, iclass 39, count 0 2006.173.17:26:31.90#ibcon#about to read 6, iclass 39, count 0 2006.173.17:26:31.90#ibcon#read 6, iclass 39, count 0 2006.173.17:26:31.90#ibcon#end of sib2, iclass 39, count 0 2006.173.17:26:31.90#ibcon#*mode == 0, iclass 39, count 0 2006.173.17:26:31.90#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.17:26:31.90#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.17:26:31.90#ibcon#*before write, iclass 39, count 0 2006.173.17:26:31.90#ibcon#enter sib2, iclass 39, count 0 2006.173.17:26:31.90#ibcon#flushed, iclass 39, count 0 2006.173.17:26:31.90#ibcon#about to write, iclass 39, count 0 2006.173.17:26:31.90#ibcon#wrote, iclass 39, count 0 2006.173.17:26:31.90#ibcon#about to read 3, iclass 39, count 0 2006.173.17:26:31.94#ibcon#read 3, iclass 39, count 0 2006.173.17:26:31.94#ibcon#about to read 4, iclass 39, count 0 2006.173.17:26:31.94#ibcon#read 4, iclass 39, count 0 2006.173.17:26:31.94#ibcon#about to read 5, iclass 39, count 0 2006.173.17:26:31.94#ibcon#read 5, iclass 39, count 0 2006.173.17:26:31.94#ibcon#about to read 6, iclass 39, count 0 2006.173.17:26:31.94#ibcon#read 6, iclass 39, count 0 2006.173.17:26:31.94#ibcon#end of sib2, iclass 39, count 0 2006.173.17:26:31.94#ibcon#*after write, iclass 39, count 0 2006.173.17:26:31.94#ibcon#*before return 0, iclass 39, count 0 2006.173.17:26:31.94#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.17:26:31.94#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.17:26:31.94#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.17:26:31.94#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.17:26:31.94$vck44/vb=4,4 2006.173.17:26:31.94#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.17:26:31.94#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.17:26:31.94#ibcon#ireg 11 cls_cnt 2 2006.173.17:26:31.94#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.17:26:32.00#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.17:26:32.00#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.17:26:32.00#ibcon#enter wrdev, iclass 3, count 2 2006.173.17:26:32.00#ibcon#first serial, iclass 3, count 2 2006.173.17:26:32.00#ibcon#enter sib2, iclass 3, count 2 2006.173.17:26:32.00#ibcon#flushed, iclass 3, count 2 2006.173.17:26:32.00#ibcon#about to write, iclass 3, count 2 2006.173.17:26:32.00#ibcon#wrote, iclass 3, count 2 2006.173.17:26:32.00#ibcon#about to read 3, iclass 3, count 2 2006.173.17:26:32.02#ibcon#read 3, iclass 3, count 2 2006.173.17:26:32.02#ibcon#about to read 4, iclass 3, count 2 2006.173.17:26:32.02#ibcon#read 4, iclass 3, count 2 2006.173.17:26:32.02#ibcon#about to read 5, iclass 3, count 2 2006.173.17:26:32.02#ibcon#read 5, iclass 3, count 2 2006.173.17:26:32.02#ibcon#about to read 6, iclass 3, count 2 2006.173.17:26:32.02#ibcon#read 6, iclass 3, count 2 2006.173.17:26:32.02#ibcon#end of sib2, iclass 3, count 2 2006.173.17:26:32.02#ibcon#*mode == 0, iclass 3, count 2 2006.173.17:26:32.02#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.17:26:32.02#ibcon#[27=AT04-04\r\n] 2006.173.17:26:32.02#ibcon#*before write, iclass 3, count 2 2006.173.17:26:32.02#ibcon#enter sib2, iclass 3, count 2 2006.173.17:26:32.02#ibcon#flushed, iclass 3, count 2 2006.173.17:26:32.02#ibcon#about to write, iclass 3, count 2 2006.173.17:26:32.02#ibcon#wrote, iclass 3, count 2 2006.173.17:26:32.02#ibcon#about to read 3, iclass 3, count 2 2006.173.17:26:32.05#ibcon#read 3, iclass 3, count 2 2006.173.17:26:32.05#ibcon#about to read 4, iclass 3, count 2 2006.173.17:26:32.05#ibcon#read 4, iclass 3, count 2 2006.173.17:26:32.05#ibcon#about to read 5, iclass 3, count 2 2006.173.17:26:32.05#ibcon#read 5, iclass 3, count 2 2006.173.17:26:32.05#ibcon#about to read 6, iclass 3, count 2 2006.173.17:26:32.05#ibcon#read 6, iclass 3, count 2 2006.173.17:26:32.05#ibcon#end of sib2, iclass 3, count 2 2006.173.17:26:32.05#ibcon#*after write, iclass 3, count 2 2006.173.17:26:32.05#ibcon#*before return 0, iclass 3, count 2 2006.173.17:26:32.05#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.17:26:32.05#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.17:26:32.05#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.17:26:32.05#ibcon#ireg 7 cls_cnt 0 2006.173.17:26:32.05#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.17:26:32.17#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.17:26:32.17#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.17:26:32.17#ibcon#enter wrdev, iclass 3, count 0 2006.173.17:26:32.17#ibcon#first serial, iclass 3, count 0 2006.173.17:26:32.17#ibcon#enter sib2, iclass 3, count 0 2006.173.17:26:32.17#ibcon#flushed, iclass 3, count 0 2006.173.17:26:32.17#ibcon#about to write, iclass 3, count 0 2006.173.17:26:32.17#ibcon#wrote, iclass 3, count 0 2006.173.17:26:32.17#ibcon#about to read 3, iclass 3, count 0 2006.173.17:26:32.19#ibcon#read 3, iclass 3, count 0 2006.173.17:26:32.19#ibcon#about to read 4, iclass 3, count 0 2006.173.17:26:32.19#ibcon#read 4, iclass 3, count 0 2006.173.17:26:32.19#ibcon#about to read 5, iclass 3, count 0 2006.173.17:26:32.19#ibcon#read 5, iclass 3, count 0 2006.173.17:26:32.19#ibcon#about to read 6, iclass 3, count 0 2006.173.17:26:32.19#ibcon#read 6, iclass 3, count 0 2006.173.17:26:32.19#ibcon#end of sib2, iclass 3, count 0 2006.173.17:26:32.19#ibcon#*mode == 0, iclass 3, count 0 2006.173.17:26:32.19#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.17:26:32.19#ibcon#[27=USB\r\n] 2006.173.17:26:32.19#ibcon#*before write, iclass 3, count 0 2006.173.17:26:32.19#ibcon#enter sib2, iclass 3, count 0 2006.173.17:26:32.19#ibcon#flushed, iclass 3, count 0 2006.173.17:26:32.19#ibcon#about to write, iclass 3, count 0 2006.173.17:26:32.19#ibcon#wrote, iclass 3, count 0 2006.173.17:26:32.19#ibcon#about to read 3, iclass 3, count 0 2006.173.17:26:32.22#ibcon#read 3, iclass 3, count 0 2006.173.17:26:32.22#ibcon#about to read 4, iclass 3, count 0 2006.173.17:26:32.22#ibcon#read 4, iclass 3, count 0 2006.173.17:26:32.22#ibcon#about to read 5, iclass 3, count 0 2006.173.17:26:32.22#ibcon#read 5, iclass 3, count 0 2006.173.17:26:32.22#ibcon#about to read 6, iclass 3, count 0 2006.173.17:26:32.22#ibcon#read 6, iclass 3, count 0 2006.173.17:26:32.22#ibcon#end of sib2, iclass 3, count 0 2006.173.17:26:32.22#ibcon#*after write, iclass 3, count 0 2006.173.17:26:32.22#ibcon#*before return 0, iclass 3, count 0 2006.173.17:26:32.22#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.17:26:32.22#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.17:26:32.22#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.17:26:32.22#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.17:26:32.22$vck44/vblo=5,709.99 2006.173.17:26:32.22#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.17:26:32.22#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.17:26:32.22#ibcon#ireg 17 cls_cnt 0 2006.173.17:26:32.22#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.17:26:32.22#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.17:26:32.22#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.17:26:32.22#ibcon#enter wrdev, iclass 5, count 0 2006.173.17:26:32.22#ibcon#first serial, iclass 5, count 0 2006.173.17:26:32.22#ibcon#enter sib2, iclass 5, count 0 2006.173.17:26:32.22#ibcon#flushed, iclass 5, count 0 2006.173.17:26:32.22#ibcon#about to write, iclass 5, count 0 2006.173.17:26:32.22#ibcon#wrote, iclass 5, count 0 2006.173.17:26:32.22#ibcon#about to read 3, iclass 5, count 0 2006.173.17:26:32.24#ibcon#read 3, iclass 5, count 0 2006.173.17:26:32.24#ibcon#about to read 4, iclass 5, count 0 2006.173.17:26:32.24#ibcon#read 4, iclass 5, count 0 2006.173.17:26:32.24#ibcon#about to read 5, iclass 5, count 0 2006.173.17:26:32.24#ibcon#read 5, iclass 5, count 0 2006.173.17:26:32.24#ibcon#about to read 6, iclass 5, count 0 2006.173.17:26:32.24#ibcon#read 6, iclass 5, count 0 2006.173.17:26:32.24#ibcon#end of sib2, iclass 5, count 0 2006.173.17:26:32.24#ibcon#*mode == 0, iclass 5, count 0 2006.173.17:26:32.24#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.17:26:32.24#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.17:26:32.24#ibcon#*before write, iclass 5, count 0 2006.173.17:26:32.24#ibcon#enter sib2, iclass 5, count 0 2006.173.17:26:32.24#ibcon#flushed, iclass 5, count 0 2006.173.17:26:32.24#ibcon#about to write, iclass 5, count 0 2006.173.17:26:32.24#ibcon#wrote, iclass 5, count 0 2006.173.17:26:32.24#ibcon#about to read 3, iclass 5, count 0 2006.173.17:26:32.28#ibcon#read 3, iclass 5, count 0 2006.173.17:26:32.28#ibcon#about to read 4, iclass 5, count 0 2006.173.17:26:32.28#ibcon#read 4, iclass 5, count 0 2006.173.17:26:32.28#ibcon#about to read 5, iclass 5, count 0 2006.173.17:26:32.28#ibcon#read 5, iclass 5, count 0 2006.173.17:26:32.28#ibcon#about to read 6, iclass 5, count 0 2006.173.17:26:32.28#ibcon#read 6, iclass 5, count 0 2006.173.17:26:32.28#ibcon#end of sib2, iclass 5, count 0 2006.173.17:26:32.28#ibcon#*after write, iclass 5, count 0 2006.173.17:26:32.28#ibcon#*before return 0, iclass 5, count 0 2006.173.17:26:32.28#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.17:26:32.28#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.17:26:32.28#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.17:26:32.28#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.17:26:32.28$vck44/vb=5,4 2006.173.17:26:32.28#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.173.17:26:32.28#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.173.17:26:32.28#ibcon#ireg 11 cls_cnt 2 2006.173.17:26:32.28#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.17:26:32.34#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.17:26:32.34#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.17:26:32.34#ibcon#enter wrdev, iclass 7, count 2 2006.173.17:26:32.34#ibcon#first serial, iclass 7, count 2 2006.173.17:26:32.34#ibcon#enter sib2, iclass 7, count 2 2006.173.17:26:32.34#ibcon#flushed, iclass 7, count 2 2006.173.17:26:32.34#ibcon#about to write, iclass 7, count 2 2006.173.17:26:32.34#ibcon#wrote, iclass 7, count 2 2006.173.17:26:32.34#ibcon#about to read 3, iclass 7, count 2 2006.173.17:26:32.36#ibcon#read 3, iclass 7, count 2 2006.173.17:26:32.36#ibcon#about to read 4, iclass 7, count 2 2006.173.17:26:32.36#ibcon#read 4, iclass 7, count 2 2006.173.17:26:32.36#ibcon#about to read 5, iclass 7, count 2 2006.173.17:26:32.36#ibcon#read 5, iclass 7, count 2 2006.173.17:26:32.36#ibcon#about to read 6, iclass 7, count 2 2006.173.17:26:32.36#ibcon#read 6, iclass 7, count 2 2006.173.17:26:32.36#ibcon#end of sib2, iclass 7, count 2 2006.173.17:26:32.36#ibcon#*mode == 0, iclass 7, count 2 2006.173.17:26:32.36#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.173.17:26:32.36#ibcon#[27=AT05-04\r\n] 2006.173.17:26:32.36#ibcon#*before write, iclass 7, count 2 2006.173.17:26:32.36#ibcon#enter sib2, iclass 7, count 2 2006.173.17:26:32.36#ibcon#flushed, iclass 7, count 2 2006.173.17:26:32.36#ibcon#about to write, iclass 7, count 2 2006.173.17:26:32.36#ibcon#wrote, iclass 7, count 2 2006.173.17:26:32.36#ibcon#about to read 3, iclass 7, count 2 2006.173.17:26:32.39#ibcon#read 3, iclass 7, count 2 2006.173.17:26:32.39#ibcon#about to read 4, iclass 7, count 2 2006.173.17:26:32.39#ibcon#read 4, iclass 7, count 2 2006.173.17:26:32.39#ibcon#about to read 5, iclass 7, count 2 2006.173.17:26:32.39#ibcon#read 5, iclass 7, count 2 2006.173.17:26:32.39#ibcon#about to read 6, iclass 7, count 2 2006.173.17:26:32.39#ibcon#read 6, iclass 7, count 2 2006.173.17:26:32.39#ibcon#end of sib2, iclass 7, count 2 2006.173.17:26:32.39#ibcon#*after write, iclass 7, count 2 2006.173.17:26:32.39#ibcon#*before return 0, iclass 7, count 2 2006.173.17:26:32.39#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.17:26:32.39#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.173.17:26:32.39#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.173.17:26:32.39#ibcon#ireg 7 cls_cnt 0 2006.173.17:26:32.39#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.17:26:32.51#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.17:26:32.51#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.17:26:32.51#ibcon#enter wrdev, iclass 7, count 0 2006.173.17:26:32.51#ibcon#first serial, iclass 7, count 0 2006.173.17:26:32.51#ibcon#enter sib2, iclass 7, count 0 2006.173.17:26:32.51#ibcon#flushed, iclass 7, count 0 2006.173.17:26:32.51#ibcon#about to write, iclass 7, count 0 2006.173.17:26:32.51#ibcon#wrote, iclass 7, count 0 2006.173.17:26:32.51#ibcon#about to read 3, iclass 7, count 0 2006.173.17:26:32.53#ibcon#read 3, iclass 7, count 0 2006.173.17:26:32.53#ibcon#about to read 4, iclass 7, count 0 2006.173.17:26:32.53#ibcon#read 4, iclass 7, count 0 2006.173.17:26:32.53#ibcon#about to read 5, iclass 7, count 0 2006.173.17:26:32.53#ibcon#read 5, iclass 7, count 0 2006.173.17:26:32.53#ibcon#about to read 6, iclass 7, count 0 2006.173.17:26:32.53#ibcon#read 6, iclass 7, count 0 2006.173.17:26:32.53#ibcon#end of sib2, iclass 7, count 0 2006.173.17:26:32.53#ibcon#*mode == 0, iclass 7, count 0 2006.173.17:26:32.53#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.17:26:32.53#ibcon#[27=USB\r\n] 2006.173.17:26:32.53#ibcon#*before write, iclass 7, count 0 2006.173.17:26:32.53#ibcon#enter sib2, iclass 7, count 0 2006.173.17:26:32.53#ibcon#flushed, iclass 7, count 0 2006.173.17:26:32.53#ibcon#about to write, iclass 7, count 0 2006.173.17:26:32.53#ibcon#wrote, iclass 7, count 0 2006.173.17:26:32.53#ibcon#about to read 3, iclass 7, count 0 2006.173.17:26:32.56#ibcon#read 3, iclass 7, count 0 2006.173.17:26:32.56#ibcon#about to read 4, iclass 7, count 0 2006.173.17:26:32.56#ibcon#read 4, iclass 7, count 0 2006.173.17:26:32.56#ibcon#about to read 5, iclass 7, count 0 2006.173.17:26:32.56#ibcon#read 5, iclass 7, count 0 2006.173.17:26:32.56#ibcon#about to read 6, iclass 7, count 0 2006.173.17:26:32.56#ibcon#read 6, iclass 7, count 0 2006.173.17:26:32.56#ibcon#end of sib2, iclass 7, count 0 2006.173.17:26:32.56#ibcon#*after write, iclass 7, count 0 2006.173.17:26:32.56#ibcon#*before return 0, iclass 7, count 0 2006.173.17:26:32.56#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.17:26:32.56#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.173.17:26:32.56#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.17:26:32.56#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.17:26:32.56$vck44/vblo=6,719.99 2006.173.17:26:32.56#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.17:26:32.56#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.17:26:32.56#ibcon#ireg 17 cls_cnt 0 2006.173.17:26:32.56#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.17:26:32.56#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.17:26:32.56#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.17:26:32.56#ibcon#enter wrdev, iclass 11, count 0 2006.173.17:26:32.56#ibcon#first serial, iclass 11, count 0 2006.173.17:26:32.56#ibcon#enter sib2, iclass 11, count 0 2006.173.17:26:32.56#ibcon#flushed, iclass 11, count 0 2006.173.17:26:32.56#ibcon#about to write, iclass 11, count 0 2006.173.17:26:32.56#ibcon#wrote, iclass 11, count 0 2006.173.17:26:32.56#ibcon#about to read 3, iclass 11, count 0 2006.173.17:26:32.58#ibcon#read 3, iclass 11, count 0 2006.173.17:26:32.58#ibcon#about to read 4, iclass 11, count 0 2006.173.17:26:32.58#ibcon#read 4, iclass 11, count 0 2006.173.17:26:32.58#ibcon#about to read 5, iclass 11, count 0 2006.173.17:26:32.58#ibcon#read 5, iclass 11, count 0 2006.173.17:26:32.58#ibcon#about to read 6, iclass 11, count 0 2006.173.17:26:32.58#ibcon#read 6, iclass 11, count 0 2006.173.17:26:32.58#ibcon#end of sib2, iclass 11, count 0 2006.173.17:26:32.58#ibcon#*mode == 0, iclass 11, count 0 2006.173.17:26:32.58#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.17:26:32.58#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.17:26:32.58#ibcon#*before write, iclass 11, count 0 2006.173.17:26:32.58#ibcon#enter sib2, iclass 11, count 0 2006.173.17:26:32.58#ibcon#flushed, iclass 11, count 0 2006.173.17:26:32.58#ibcon#about to write, iclass 11, count 0 2006.173.17:26:32.58#ibcon#wrote, iclass 11, count 0 2006.173.17:26:32.58#ibcon#about to read 3, iclass 11, count 0 2006.173.17:26:32.62#ibcon#read 3, iclass 11, count 0 2006.173.17:26:32.62#ibcon#about to read 4, iclass 11, count 0 2006.173.17:26:32.62#ibcon#read 4, iclass 11, count 0 2006.173.17:26:32.62#ibcon#about to read 5, iclass 11, count 0 2006.173.17:26:32.62#ibcon#read 5, iclass 11, count 0 2006.173.17:26:32.62#ibcon#about to read 6, iclass 11, count 0 2006.173.17:26:32.62#ibcon#read 6, iclass 11, count 0 2006.173.17:26:32.62#ibcon#end of sib2, iclass 11, count 0 2006.173.17:26:32.62#ibcon#*after write, iclass 11, count 0 2006.173.17:26:32.62#ibcon#*before return 0, iclass 11, count 0 2006.173.17:26:32.62#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.17:26:32.62#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.17:26:32.62#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.17:26:32.62#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.17:26:32.62$vck44/vb=6,4 2006.173.17:26:32.62#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.173.17:26:32.62#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.173.17:26:32.62#ibcon#ireg 11 cls_cnt 2 2006.173.17:26:32.62#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.17:26:32.68#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.17:26:32.68#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.17:26:32.68#ibcon#enter wrdev, iclass 13, count 2 2006.173.17:26:32.68#ibcon#first serial, iclass 13, count 2 2006.173.17:26:32.68#ibcon#enter sib2, iclass 13, count 2 2006.173.17:26:32.68#ibcon#flushed, iclass 13, count 2 2006.173.17:26:32.68#ibcon#about to write, iclass 13, count 2 2006.173.17:26:32.68#ibcon#wrote, iclass 13, count 2 2006.173.17:26:32.68#ibcon#about to read 3, iclass 13, count 2 2006.173.17:26:32.70#ibcon#read 3, iclass 13, count 2 2006.173.17:26:32.70#ibcon#about to read 4, iclass 13, count 2 2006.173.17:26:32.70#ibcon#read 4, iclass 13, count 2 2006.173.17:26:32.70#ibcon#about to read 5, iclass 13, count 2 2006.173.17:26:32.70#ibcon#read 5, iclass 13, count 2 2006.173.17:26:32.70#ibcon#about to read 6, iclass 13, count 2 2006.173.17:26:32.70#ibcon#read 6, iclass 13, count 2 2006.173.17:26:32.70#ibcon#end of sib2, iclass 13, count 2 2006.173.17:26:32.70#ibcon#*mode == 0, iclass 13, count 2 2006.173.17:26:32.70#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.173.17:26:32.70#ibcon#[27=AT06-04\r\n] 2006.173.17:26:32.70#ibcon#*before write, iclass 13, count 2 2006.173.17:26:32.70#ibcon#enter sib2, iclass 13, count 2 2006.173.17:26:32.70#ibcon#flushed, iclass 13, count 2 2006.173.17:26:32.70#ibcon#about to write, iclass 13, count 2 2006.173.17:26:32.70#ibcon#wrote, iclass 13, count 2 2006.173.17:26:32.70#ibcon#about to read 3, iclass 13, count 2 2006.173.17:26:32.73#ibcon#read 3, iclass 13, count 2 2006.173.17:26:32.73#ibcon#about to read 4, iclass 13, count 2 2006.173.17:26:32.73#ibcon#read 4, iclass 13, count 2 2006.173.17:26:32.73#ibcon#about to read 5, iclass 13, count 2 2006.173.17:26:32.73#ibcon#read 5, iclass 13, count 2 2006.173.17:26:32.73#ibcon#about to read 6, iclass 13, count 2 2006.173.17:26:32.73#ibcon#read 6, iclass 13, count 2 2006.173.17:26:32.73#ibcon#end of sib2, iclass 13, count 2 2006.173.17:26:32.73#ibcon#*after write, iclass 13, count 2 2006.173.17:26:32.73#ibcon#*before return 0, iclass 13, count 2 2006.173.17:26:32.73#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.17:26:32.73#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.173.17:26:32.73#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.173.17:26:32.73#ibcon#ireg 7 cls_cnt 0 2006.173.17:26:32.73#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.17:26:32.85#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.17:26:32.85#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.17:26:32.85#ibcon#enter wrdev, iclass 13, count 0 2006.173.17:26:32.85#ibcon#first serial, iclass 13, count 0 2006.173.17:26:32.85#ibcon#enter sib2, iclass 13, count 0 2006.173.17:26:32.85#ibcon#flushed, iclass 13, count 0 2006.173.17:26:32.85#ibcon#about to write, iclass 13, count 0 2006.173.17:26:32.85#ibcon#wrote, iclass 13, count 0 2006.173.17:26:32.85#ibcon#about to read 3, iclass 13, count 0 2006.173.17:26:32.87#ibcon#read 3, iclass 13, count 0 2006.173.17:26:32.87#ibcon#about to read 4, iclass 13, count 0 2006.173.17:26:32.87#ibcon#read 4, iclass 13, count 0 2006.173.17:26:32.87#ibcon#about to read 5, iclass 13, count 0 2006.173.17:26:32.87#ibcon#read 5, iclass 13, count 0 2006.173.17:26:32.87#ibcon#about to read 6, iclass 13, count 0 2006.173.17:26:32.87#ibcon#read 6, iclass 13, count 0 2006.173.17:26:32.87#ibcon#end of sib2, iclass 13, count 0 2006.173.17:26:32.87#ibcon#*mode == 0, iclass 13, count 0 2006.173.17:26:32.87#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.17:26:32.87#ibcon#[27=USB\r\n] 2006.173.17:26:32.87#ibcon#*before write, iclass 13, count 0 2006.173.17:26:32.87#ibcon#enter sib2, iclass 13, count 0 2006.173.17:26:32.87#ibcon#flushed, iclass 13, count 0 2006.173.17:26:32.87#ibcon#about to write, iclass 13, count 0 2006.173.17:26:32.87#ibcon#wrote, iclass 13, count 0 2006.173.17:26:32.87#ibcon#about to read 3, iclass 13, count 0 2006.173.17:26:32.90#ibcon#read 3, iclass 13, count 0 2006.173.17:26:32.90#ibcon#about to read 4, iclass 13, count 0 2006.173.17:26:32.90#ibcon#read 4, iclass 13, count 0 2006.173.17:26:32.90#ibcon#about to read 5, iclass 13, count 0 2006.173.17:26:32.90#ibcon#read 5, iclass 13, count 0 2006.173.17:26:32.90#ibcon#about to read 6, iclass 13, count 0 2006.173.17:26:32.90#ibcon#read 6, iclass 13, count 0 2006.173.17:26:32.90#ibcon#end of sib2, iclass 13, count 0 2006.173.17:26:32.90#ibcon#*after write, iclass 13, count 0 2006.173.17:26:32.90#ibcon#*before return 0, iclass 13, count 0 2006.173.17:26:32.90#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.17:26:32.90#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.173.17:26:32.90#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.17:26:32.90#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.17:26:32.90$vck44/vblo=7,734.99 2006.173.17:26:32.90#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.17:26:32.90#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.17:26:32.90#ibcon#ireg 17 cls_cnt 0 2006.173.17:26:32.90#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.17:26:32.90#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.17:26:32.90#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.17:26:32.90#ibcon#enter wrdev, iclass 15, count 0 2006.173.17:26:32.90#ibcon#first serial, iclass 15, count 0 2006.173.17:26:32.90#ibcon#enter sib2, iclass 15, count 0 2006.173.17:26:32.90#ibcon#flushed, iclass 15, count 0 2006.173.17:26:32.90#ibcon#about to write, iclass 15, count 0 2006.173.17:26:32.90#ibcon#wrote, iclass 15, count 0 2006.173.17:26:32.90#ibcon#about to read 3, iclass 15, count 0 2006.173.17:26:32.92#ibcon#read 3, iclass 15, count 0 2006.173.17:26:32.92#ibcon#about to read 4, iclass 15, count 0 2006.173.17:26:32.92#ibcon#read 4, iclass 15, count 0 2006.173.17:26:32.92#ibcon#about to read 5, iclass 15, count 0 2006.173.17:26:32.92#ibcon#read 5, iclass 15, count 0 2006.173.17:26:32.92#ibcon#about to read 6, iclass 15, count 0 2006.173.17:26:32.92#ibcon#read 6, iclass 15, count 0 2006.173.17:26:32.92#ibcon#end of sib2, iclass 15, count 0 2006.173.17:26:32.92#ibcon#*mode == 0, iclass 15, count 0 2006.173.17:26:32.92#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.17:26:32.92#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.17:26:32.92#ibcon#*before write, iclass 15, count 0 2006.173.17:26:32.92#ibcon#enter sib2, iclass 15, count 0 2006.173.17:26:32.92#ibcon#flushed, iclass 15, count 0 2006.173.17:26:32.92#ibcon#about to write, iclass 15, count 0 2006.173.17:26:32.92#ibcon#wrote, iclass 15, count 0 2006.173.17:26:32.92#ibcon#about to read 3, iclass 15, count 0 2006.173.17:26:32.96#ibcon#read 3, iclass 15, count 0 2006.173.17:26:32.96#ibcon#about to read 4, iclass 15, count 0 2006.173.17:26:32.96#ibcon#read 4, iclass 15, count 0 2006.173.17:26:32.96#ibcon#about to read 5, iclass 15, count 0 2006.173.17:26:32.96#ibcon#read 5, iclass 15, count 0 2006.173.17:26:32.96#ibcon#about to read 6, iclass 15, count 0 2006.173.17:26:32.96#ibcon#read 6, iclass 15, count 0 2006.173.17:26:32.96#ibcon#end of sib2, iclass 15, count 0 2006.173.17:26:32.96#ibcon#*after write, iclass 15, count 0 2006.173.17:26:32.96#ibcon#*before return 0, iclass 15, count 0 2006.173.17:26:32.96#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.17:26:32.96#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.17:26:32.96#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.17:26:32.96#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.17:26:32.96$vck44/vb=7,4 2006.173.17:26:32.96#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.17:26:32.96#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.17:26:32.96#ibcon#ireg 11 cls_cnt 2 2006.173.17:26:32.96#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.17:26:33.02#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.17:26:33.02#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.17:26:33.02#ibcon#enter wrdev, iclass 17, count 2 2006.173.17:26:33.02#ibcon#first serial, iclass 17, count 2 2006.173.17:26:33.02#ibcon#enter sib2, iclass 17, count 2 2006.173.17:26:33.02#ibcon#flushed, iclass 17, count 2 2006.173.17:26:33.02#ibcon#about to write, iclass 17, count 2 2006.173.17:26:33.02#ibcon#wrote, iclass 17, count 2 2006.173.17:26:33.02#ibcon#about to read 3, iclass 17, count 2 2006.173.17:26:33.04#ibcon#read 3, iclass 17, count 2 2006.173.17:26:33.04#ibcon#about to read 4, iclass 17, count 2 2006.173.17:26:33.04#ibcon#read 4, iclass 17, count 2 2006.173.17:26:33.04#ibcon#about to read 5, iclass 17, count 2 2006.173.17:26:33.04#ibcon#read 5, iclass 17, count 2 2006.173.17:26:33.04#ibcon#about to read 6, iclass 17, count 2 2006.173.17:26:33.04#ibcon#read 6, iclass 17, count 2 2006.173.17:26:33.04#ibcon#end of sib2, iclass 17, count 2 2006.173.17:26:33.04#ibcon#*mode == 0, iclass 17, count 2 2006.173.17:26:33.04#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.17:26:33.04#ibcon#[27=AT07-04\r\n] 2006.173.17:26:33.04#ibcon#*before write, iclass 17, count 2 2006.173.17:26:33.04#ibcon#enter sib2, iclass 17, count 2 2006.173.17:26:33.04#ibcon#flushed, iclass 17, count 2 2006.173.17:26:33.04#ibcon#about to write, iclass 17, count 2 2006.173.17:26:33.04#ibcon#wrote, iclass 17, count 2 2006.173.17:26:33.04#ibcon#about to read 3, iclass 17, count 2 2006.173.17:26:33.07#ibcon#read 3, iclass 17, count 2 2006.173.17:26:33.07#ibcon#about to read 4, iclass 17, count 2 2006.173.17:26:33.07#ibcon#read 4, iclass 17, count 2 2006.173.17:26:33.07#ibcon#about to read 5, iclass 17, count 2 2006.173.17:26:33.07#ibcon#read 5, iclass 17, count 2 2006.173.17:26:33.07#ibcon#about to read 6, iclass 17, count 2 2006.173.17:26:33.07#ibcon#read 6, iclass 17, count 2 2006.173.17:26:33.07#ibcon#end of sib2, iclass 17, count 2 2006.173.17:26:33.07#ibcon#*after write, iclass 17, count 2 2006.173.17:26:33.07#ibcon#*before return 0, iclass 17, count 2 2006.173.17:26:33.07#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.17:26:33.07#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.17:26:33.07#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.17:26:33.07#ibcon#ireg 7 cls_cnt 0 2006.173.17:26:33.07#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.17:26:33.19#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.17:26:33.19#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.17:26:33.19#ibcon#enter wrdev, iclass 17, count 0 2006.173.17:26:33.19#ibcon#first serial, iclass 17, count 0 2006.173.17:26:33.19#ibcon#enter sib2, iclass 17, count 0 2006.173.17:26:33.19#ibcon#flushed, iclass 17, count 0 2006.173.17:26:33.19#ibcon#about to write, iclass 17, count 0 2006.173.17:26:33.19#ibcon#wrote, iclass 17, count 0 2006.173.17:26:33.19#ibcon#about to read 3, iclass 17, count 0 2006.173.17:26:33.21#ibcon#read 3, iclass 17, count 0 2006.173.17:26:33.21#ibcon#about to read 4, iclass 17, count 0 2006.173.17:26:33.21#ibcon#read 4, iclass 17, count 0 2006.173.17:26:33.21#ibcon#about to read 5, iclass 17, count 0 2006.173.17:26:33.21#ibcon#read 5, iclass 17, count 0 2006.173.17:26:33.21#ibcon#about to read 6, iclass 17, count 0 2006.173.17:26:33.21#ibcon#read 6, iclass 17, count 0 2006.173.17:26:33.21#ibcon#end of sib2, iclass 17, count 0 2006.173.17:26:33.21#ibcon#*mode == 0, iclass 17, count 0 2006.173.17:26:33.21#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.17:26:33.21#ibcon#[27=USB\r\n] 2006.173.17:26:33.21#ibcon#*before write, iclass 17, count 0 2006.173.17:26:33.21#ibcon#enter sib2, iclass 17, count 0 2006.173.17:26:33.21#ibcon#flushed, iclass 17, count 0 2006.173.17:26:33.21#ibcon#about to write, iclass 17, count 0 2006.173.17:26:33.21#ibcon#wrote, iclass 17, count 0 2006.173.17:26:33.21#ibcon#about to read 3, iclass 17, count 0 2006.173.17:26:33.24#ibcon#read 3, iclass 17, count 0 2006.173.17:26:33.24#ibcon#about to read 4, iclass 17, count 0 2006.173.17:26:33.24#ibcon#read 4, iclass 17, count 0 2006.173.17:26:33.24#ibcon#about to read 5, iclass 17, count 0 2006.173.17:26:33.24#ibcon#read 5, iclass 17, count 0 2006.173.17:26:33.24#ibcon#about to read 6, iclass 17, count 0 2006.173.17:26:33.24#ibcon#read 6, iclass 17, count 0 2006.173.17:26:33.24#ibcon#end of sib2, iclass 17, count 0 2006.173.17:26:33.24#ibcon#*after write, iclass 17, count 0 2006.173.17:26:33.24#ibcon#*before return 0, iclass 17, count 0 2006.173.17:26:33.24#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.17:26:33.24#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.17:26:33.24#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.17:26:33.24#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.17:26:33.24$vck44/vblo=8,744.99 2006.173.17:26:33.24#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.17:26:33.24#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.17:26:33.24#ibcon#ireg 17 cls_cnt 0 2006.173.17:26:33.24#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.17:26:33.24#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.17:26:33.24#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.17:26:33.24#ibcon#enter wrdev, iclass 19, count 0 2006.173.17:26:33.24#ibcon#first serial, iclass 19, count 0 2006.173.17:26:33.24#ibcon#enter sib2, iclass 19, count 0 2006.173.17:26:33.24#ibcon#flushed, iclass 19, count 0 2006.173.17:26:33.24#ibcon#about to write, iclass 19, count 0 2006.173.17:26:33.24#ibcon#wrote, iclass 19, count 0 2006.173.17:26:33.24#ibcon#about to read 3, iclass 19, count 0 2006.173.17:26:33.26#ibcon#read 3, iclass 19, count 0 2006.173.17:26:33.26#ibcon#about to read 4, iclass 19, count 0 2006.173.17:26:33.26#ibcon#read 4, iclass 19, count 0 2006.173.17:26:33.26#ibcon#about to read 5, iclass 19, count 0 2006.173.17:26:33.26#ibcon#read 5, iclass 19, count 0 2006.173.17:26:33.26#ibcon#about to read 6, iclass 19, count 0 2006.173.17:26:33.26#ibcon#read 6, iclass 19, count 0 2006.173.17:26:33.26#ibcon#end of sib2, iclass 19, count 0 2006.173.17:26:33.26#ibcon#*mode == 0, iclass 19, count 0 2006.173.17:26:33.26#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.17:26:33.26#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.17:26:33.26#ibcon#*before write, iclass 19, count 0 2006.173.17:26:33.26#ibcon#enter sib2, iclass 19, count 0 2006.173.17:26:33.26#ibcon#flushed, iclass 19, count 0 2006.173.17:26:33.26#ibcon#about to write, iclass 19, count 0 2006.173.17:26:33.26#ibcon#wrote, iclass 19, count 0 2006.173.17:26:33.26#ibcon#about to read 3, iclass 19, count 0 2006.173.17:26:33.30#ibcon#read 3, iclass 19, count 0 2006.173.17:26:33.30#ibcon#about to read 4, iclass 19, count 0 2006.173.17:26:33.30#ibcon#read 4, iclass 19, count 0 2006.173.17:26:33.30#ibcon#about to read 5, iclass 19, count 0 2006.173.17:26:33.30#ibcon#read 5, iclass 19, count 0 2006.173.17:26:33.30#ibcon#about to read 6, iclass 19, count 0 2006.173.17:26:33.30#ibcon#read 6, iclass 19, count 0 2006.173.17:26:33.30#ibcon#end of sib2, iclass 19, count 0 2006.173.17:26:33.30#ibcon#*after write, iclass 19, count 0 2006.173.17:26:33.30#ibcon#*before return 0, iclass 19, count 0 2006.173.17:26:33.30#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.17:26:33.30#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.17:26:33.30#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.17:26:33.30#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.17:26:33.30$vck44/vb=8,4 2006.173.17:26:33.30#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.17:26:33.30#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.17:26:33.30#ibcon#ireg 11 cls_cnt 2 2006.173.17:26:33.30#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.17:26:33.36#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.17:26:33.36#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.17:26:33.36#ibcon#enter wrdev, iclass 21, count 2 2006.173.17:26:33.36#ibcon#first serial, iclass 21, count 2 2006.173.17:26:33.36#ibcon#enter sib2, iclass 21, count 2 2006.173.17:26:33.36#ibcon#flushed, iclass 21, count 2 2006.173.17:26:33.36#ibcon#about to write, iclass 21, count 2 2006.173.17:26:33.36#ibcon#wrote, iclass 21, count 2 2006.173.17:26:33.36#ibcon#about to read 3, iclass 21, count 2 2006.173.17:26:33.38#ibcon#read 3, iclass 21, count 2 2006.173.17:26:33.38#ibcon#about to read 4, iclass 21, count 2 2006.173.17:26:33.38#ibcon#read 4, iclass 21, count 2 2006.173.17:26:33.38#ibcon#about to read 5, iclass 21, count 2 2006.173.17:26:33.38#ibcon#read 5, iclass 21, count 2 2006.173.17:26:33.38#ibcon#about to read 6, iclass 21, count 2 2006.173.17:26:33.38#ibcon#read 6, iclass 21, count 2 2006.173.17:26:33.38#ibcon#end of sib2, iclass 21, count 2 2006.173.17:26:33.38#ibcon#*mode == 0, iclass 21, count 2 2006.173.17:26:33.38#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.17:26:33.38#ibcon#[27=AT08-04\r\n] 2006.173.17:26:33.38#ibcon#*before write, iclass 21, count 2 2006.173.17:26:33.38#ibcon#enter sib2, iclass 21, count 2 2006.173.17:26:33.38#ibcon#flushed, iclass 21, count 2 2006.173.17:26:33.38#ibcon#about to write, iclass 21, count 2 2006.173.17:26:33.38#ibcon#wrote, iclass 21, count 2 2006.173.17:26:33.38#ibcon#about to read 3, iclass 21, count 2 2006.173.17:26:33.41#ibcon#read 3, iclass 21, count 2 2006.173.17:26:33.41#ibcon#about to read 4, iclass 21, count 2 2006.173.17:26:33.41#ibcon#read 4, iclass 21, count 2 2006.173.17:26:33.41#ibcon#about to read 5, iclass 21, count 2 2006.173.17:26:33.41#ibcon#read 5, iclass 21, count 2 2006.173.17:26:33.41#ibcon#about to read 6, iclass 21, count 2 2006.173.17:26:33.41#ibcon#read 6, iclass 21, count 2 2006.173.17:26:33.41#ibcon#end of sib2, iclass 21, count 2 2006.173.17:26:33.41#ibcon#*after write, iclass 21, count 2 2006.173.17:26:33.41#ibcon#*before return 0, iclass 21, count 2 2006.173.17:26:33.41#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.17:26:33.41#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.17:26:33.41#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.17:26:33.41#ibcon#ireg 7 cls_cnt 0 2006.173.17:26:33.41#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.17:26:33.53#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.17:26:33.53#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.17:26:33.53#ibcon#enter wrdev, iclass 21, count 0 2006.173.17:26:33.53#ibcon#first serial, iclass 21, count 0 2006.173.17:26:33.53#ibcon#enter sib2, iclass 21, count 0 2006.173.17:26:33.53#ibcon#flushed, iclass 21, count 0 2006.173.17:26:33.53#ibcon#about to write, iclass 21, count 0 2006.173.17:26:33.53#ibcon#wrote, iclass 21, count 0 2006.173.17:26:33.53#ibcon#about to read 3, iclass 21, count 0 2006.173.17:26:33.55#ibcon#read 3, iclass 21, count 0 2006.173.17:26:33.55#ibcon#about to read 4, iclass 21, count 0 2006.173.17:26:33.55#ibcon#read 4, iclass 21, count 0 2006.173.17:26:33.55#ibcon#about to read 5, iclass 21, count 0 2006.173.17:26:33.55#ibcon#read 5, iclass 21, count 0 2006.173.17:26:33.55#ibcon#about to read 6, iclass 21, count 0 2006.173.17:26:33.55#ibcon#read 6, iclass 21, count 0 2006.173.17:26:33.55#ibcon#end of sib2, iclass 21, count 0 2006.173.17:26:33.55#ibcon#*mode == 0, iclass 21, count 0 2006.173.17:26:33.55#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.17:26:33.55#ibcon#[27=USB\r\n] 2006.173.17:26:33.55#ibcon#*before write, iclass 21, count 0 2006.173.17:26:33.55#ibcon#enter sib2, iclass 21, count 0 2006.173.17:26:33.55#ibcon#flushed, iclass 21, count 0 2006.173.17:26:33.55#ibcon#about to write, iclass 21, count 0 2006.173.17:26:33.55#ibcon#wrote, iclass 21, count 0 2006.173.17:26:33.55#ibcon#about to read 3, iclass 21, count 0 2006.173.17:26:33.58#ibcon#read 3, iclass 21, count 0 2006.173.17:26:33.58#ibcon#about to read 4, iclass 21, count 0 2006.173.17:26:33.58#ibcon#read 4, iclass 21, count 0 2006.173.17:26:33.58#ibcon#about to read 5, iclass 21, count 0 2006.173.17:26:33.58#ibcon#read 5, iclass 21, count 0 2006.173.17:26:33.58#ibcon#about to read 6, iclass 21, count 0 2006.173.17:26:33.58#ibcon#read 6, iclass 21, count 0 2006.173.17:26:33.58#ibcon#end of sib2, iclass 21, count 0 2006.173.17:26:33.58#ibcon#*after write, iclass 21, count 0 2006.173.17:26:33.58#ibcon#*before return 0, iclass 21, count 0 2006.173.17:26:33.58#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.17:26:33.58#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.17:26:33.58#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.17:26:33.58#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.17:26:33.58$vck44/vabw=wide 2006.173.17:26:33.58#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.17:26:33.58#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.17:26:33.58#ibcon#ireg 8 cls_cnt 0 2006.173.17:26:33.58#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.17:26:33.58#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.17:26:33.58#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.17:26:33.58#ibcon#enter wrdev, iclass 23, count 0 2006.173.17:26:33.58#ibcon#first serial, iclass 23, count 0 2006.173.17:26:33.58#ibcon#enter sib2, iclass 23, count 0 2006.173.17:26:33.58#ibcon#flushed, iclass 23, count 0 2006.173.17:26:33.58#ibcon#about to write, iclass 23, count 0 2006.173.17:26:33.58#ibcon#wrote, iclass 23, count 0 2006.173.17:26:33.58#ibcon#about to read 3, iclass 23, count 0 2006.173.17:26:33.60#ibcon#read 3, iclass 23, count 0 2006.173.17:26:33.60#ibcon#about to read 4, iclass 23, count 0 2006.173.17:26:33.60#ibcon#read 4, iclass 23, count 0 2006.173.17:26:33.60#ibcon#about to read 5, iclass 23, count 0 2006.173.17:26:33.60#ibcon#read 5, iclass 23, count 0 2006.173.17:26:33.60#ibcon#about to read 6, iclass 23, count 0 2006.173.17:26:33.60#ibcon#read 6, iclass 23, count 0 2006.173.17:26:33.60#ibcon#end of sib2, iclass 23, count 0 2006.173.17:26:33.60#ibcon#*mode == 0, iclass 23, count 0 2006.173.17:26:33.60#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.17:26:33.60#ibcon#[25=BW32\r\n] 2006.173.17:26:33.60#ibcon#*before write, iclass 23, count 0 2006.173.17:26:33.60#ibcon#enter sib2, iclass 23, count 0 2006.173.17:26:33.60#ibcon#flushed, iclass 23, count 0 2006.173.17:26:33.60#ibcon#about to write, iclass 23, count 0 2006.173.17:26:33.60#ibcon#wrote, iclass 23, count 0 2006.173.17:26:33.60#ibcon#about to read 3, iclass 23, count 0 2006.173.17:26:33.63#ibcon#read 3, iclass 23, count 0 2006.173.17:26:33.63#ibcon#about to read 4, iclass 23, count 0 2006.173.17:26:33.63#ibcon#read 4, iclass 23, count 0 2006.173.17:26:33.63#ibcon#about to read 5, iclass 23, count 0 2006.173.17:26:33.63#ibcon#read 5, iclass 23, count 0 2006.173.17:26:33.63#ibcon#about to read 6, iclass 23, count 0 2006.173.17:26:33.63#ibcon#read 6, iclass 23, count 0 2006.173.17:26:33.63#ibcon#end of sib2, iclass 23, count 0 2006.173.17:26:33.63#ibcon#*after write, iclass 23, count 0 2006.173.17:26:33.63#ibcon#*before return 0, iclass 23, count 0 2006.173.17:26:33.63#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.17:26:33.63#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.17:26:33.63#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.17:26:33.63#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.17:26:33.63$vck44/vbbw=wide 2006.173.17:26:33.63#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.17:26:33.63#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.17:26:33.63#ibcon#ireg 8 cls_cnt 0 2006.173.17:26:33.63#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.17:26:33.70#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.17:26:33.70#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.17:26:33.70#ibcon#enter wrdev, iclass 25, count 0 2006.173.17:26:33.70#ibcon#first serial, iclass 25, count 0 2006.173.17:26:33.70#ibcon#enter sib2, iclass 25, count 0 2006.173.17:26:33.70#ibcon#flushed, iclass 25, count 0 2006.173.17:26:33.70#ibcon#about to write, iclass 25, count 0 2006.173.17:26:33.70#ibcon#wrote, iclass 25, count 0 2006.173.17:26:33.70#ibcon#about to read 3, iclass 25, count 0 2006.173.17:26:33.72#ibcon#read 3, iclass 25, count 0 2006.173.17:26:33.72#ibcon#about to read 4, iclass 25, count 0 2006.173.17:26:33.72#ibcon#read 4, iclass 25, count 0 2006.173.17:26:33.72#ibcon#about to read 5, iclass 25, count 0 2006.173.17:26:33.72#ibcon#read 5, iclass 25, count 0 2006.173.17:26:33.72#ibcon#about to read 6, iclass 25, count 0 2006.173.17:26:33.72#ibcon#read 6, iclass 25, count 0 2006.173.17:26:33.72#ibcon#end of sib2, iclass 25, count 0 2006.173.17:26:33.72#ibcon#*mode == 0, iclass 25, count 0 2006.173.17:26:33.72#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.17:26:33.72#ibcon#[27=BW32\r\n] 2006.173.17:26:33.72#ibcon#*before write, iclass 25, count 0 2006.173.17:26:33.72#ibcon#enter sib2, iclass 25, count 0 2006.173.17:26:33.72#ibcon#flushed, iclass 25, count 0 2006.173.17:26:33.72#ibcon#about to write, iclass 25, count 0 2006.173.17:26:33.72#ibcon#wrote, iclass 25, count 0 2006.173.17:26:33.72#ibcon#about to read 3, iclass 25, count 0 2006.173.17:26:33.75#ibcon#read 3, iclass 25, count 0 2006.173.17:26:33.75#ibcon#about to read 4, iclass 25, count 0 2006.173.17:26:33.75#ibcon#read 4, iclass 25, count 0 2006.173.17:26:33.75#ibcon#about to read 5, iclass 25, count 0 2006.173.17:26:33.75#ibcon#read 5, iclass 25, count 0 2006.173.17:26:33.75#ibcon#about to read 6, iclass 25, count 0 2006.173.17:26:33.75#ibcon#read 6, iclass 25, count 0 2006.173.17:26:33.75#ibcon#end of sib2, iclass 25, count 0 2006.173.17:26:33.75#ibcon#*after write, iclass 25, count 0 2006.173.17:26:33.75#ibcon#*before return 0, iclass 25, count 0 2006.173.17:26:33.75#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.17:26:33.75#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.17:26:33.75#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.17:26:33.75#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.17:26:33.75$setupk4/ifdk4 2006.173.17:26:33.75$ifdk4/lo= 2006.173.17:26:33.75$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.17:26:33.75$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.17:26:33.75$ifdk4/patch= 2006.173.17:26:33.75$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.17:26:33.75$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.17:26:33.76$setupk4/!*+20s 2006.173.17:26:36.55#abcon#<5=/14 1.1 2.6 20.261001002.4\r\n> 2006.173.17:26:36.57#abcon#{5=INTERFACE CLEAR} 2006.173.17:26:36.63#abcon#[5=S1D000X0/0*\r\n] 2006.173.17:26:46.72#abcon#<5=/14 1.1 2.6 20.271001002.3\r\n> 2006.173.17:26:46.74#abcon#{5=INTERFACE CLEAR} 2006.173.17:26:46.80#abcon#[5=S1D000X0/0*\r\n] 2006.173.17:26:48.27$setupk4/"tpicd 2006.173.17:26:48.27$setupk4/echo=off 2006.173.17:26:48.27$setupk4/xlog=off 2006.173.17:26:48.27:!2006.173.17:30:33 2006.173.17:26:49.14#trakl#Source acquired 2006.173.17:26:50.14#flagr#flagr/antenna,acquired 2006.173.17:30:33.00:preob 2006.173.17:30:33.14/onsource/TRACKING 2006.173.17:30:33.14:!2006.173.17:30:43 2006.173.17:30:43.00:"tape 2006.173.17:30:43.00:"st=record 2006.173.17:30:43.00:data_valid=on 2006.173.17:30:43.00:midob 2006.173.17:30:44.14/onsource/TRACKING 2006.173.17:30:44.14/wx/20.29,1002.1,100 2006.173.17:30:44.20/cable/+6.5137E-03 2006.173.17:30:45.29/va/01,07,usb,yes,34,37 2006.173.17:30:45.29/va/02,06,usb,yes,34,35 2006.173.17:30:45.29/va/03,05,usb,yes,43,45 2006.173.17:30:45.29/va/04,06,usb,yes,35,36 2006.173.17:30:45.29/va/05,04,usb,yes,27,27 2006.173.17:30:45.29/va/06,03,usb,yes,38,38 2006.173.17:30:45.29/va/07,04,usb,yes,31,32 2006.173.17:30:45.29/va/08,04,usb,yes,26,31 2006.173.17:30:45.52/valo/01,524.99,yes,locked 2006.173.17:30:45.52/valo/02,534.99,yes,locked 2006.173.17:30:45.52/valo/03,564.99,yes,locked 2006.173.17:30:45.52/valo/04,624.99,yes,locked 2006.173.17:30:45.52/valo/05,734.99,yes,locked 2006.173.17:30:45.52/valo/06,814.99,yes,locked 2006.173.17:30:45.52/valo/07,864.99,yes,locked 2006.173.17:30:45.52/valo/08,884.99,yes,locked 2006.173.17:30:46.61/vb/01,04,usb,yes,28,26 2006.173.17:30:46.61/vb/02,04,usb,yes,31,31 2006.173.17:30:46.61/vb/03,04,usb,yes,28,31 2006.173.17:30:46.61/vb/04,04,usb,yes,32,31 2006.173.17:30:46.61/vb/05,04,usb,yes,25,27 2006.173.17:30:46.61/vb/06,04,usb,yes,29,25 2006.173.17:30:46.61/vb/07,04,usb,yes,29,29 2006.173.17:30:46.61/vb/08,04,usb,yes,27,30 2006.173.17:30:46.84/vblo/01,629.99,yes,locked 2006.173.17:30:46.84/vblo/02,634.99,yes,locked 2006.173.17:30:46.84/vblo/03,649.99,yes,locked 2006.173.17:30:46.84/vblo/04,679.99,yes,locked 2006.173.17:30:46.84/vblo/05,709.99,yes,locked 2006.173.17:30:46.84/vblo/06,719.99,yes,locked 2006.173.17:30:46.84/vblo/07,734.99,yes,locked 2006.173.17:30:46.84/vblo/08,744.99,yes,locked 2006.173.17:30:46.99/vabw/8 2006.173.17:30:47.14/vbbw/8 2006.173.17:30:47.24/xfe/off,on,14.2 2006.173.17:30:47.62/ifatt/23,28,28,28 2006.173.17:30:48.07/fmout-gps/S +3.99E-07 2006.173.17:30:48.11:!2006.173.17:32:03 2006.173.17:32:03.00:data_valid=off 2006.173.17:32:03.00:"et 2006.173.17:32:03.00:!+3s 2006.173.17:32:06.01:"tape 2006.173.17:32:06.01:postob 2006.173.17:32:06.17/cable/+6.5128E-03 2006.173.17:32:06.17/wx/20.28,1002.1,100 2006.173.17:32:07.08/fmout-gps/S +3.99E-07 2006.173.17:32:07.08:scan_name=173-1735,jd0606,40 2006.173.17:32:07.08:source=1741-038,174358.86,-035004.6,2000.0,ccw 2006.173.17:32:08.13#flagr#flagr/antenna,new-source 2006.173.17:32:08.13:checkk5 2006.173.17:32:08.50/chk_autoobs//k5ts1/ autoobs is running! 2006.173.17:32:08.89/chk_autoobs//k5ts2/ autoobs is running! 2006.173.17:32:09.31/chk_autoobs//k5ts3/ autoobs is running! 2006.173.17:32:09.71/chk_autoobs//k5ts4/ autoobs is running! 2006.173.17:32:10.10/chk_obsdata//k5ts1/T1731730??a.dat file size is correct (nominal:320MB, actual:316MB). 2006.173.17:32:10.50/chk_obsdata//k5ts2/T1731730??b.dat file size is correct (nominal:320MB, actual:316MB). 2006.173.17:32:10.90/chk_obsdata//k5ts3/T1731730??c.dat file size is correct (nominal:320MB, actual:316MB). 2006.173.17:32:11.32/chk_obsdata//k5ts4/T1731730??d.dat file size is correct (nominal:320MB, actual:316MB). 2006.173.17:32:12.04/k5log//k5ts1_log_newline 2006.173.17:32:12.74/k5log//k5ts2_log_newline 2006.173.17:32:13.45/k5log//k5ts3_log_newline 2006.173.17:32:14.15/k5log//k5ts4_log_newline 2006.173.17:32:14.18/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.17:32:14.18:setupk4=1 2006.173.17:32:14.18$setupk4/echo=on 2006.173.17:32:14.18$setupk4/pcalon 2006.173.17:32:14.18$pcalon/"no phase cal control is implemented here 2006.173.17:32:14.18$setupk4/"tpicd=stop 2006.173.17:32:14.18$setupk4/"rec=synch_on 2006.173.17:32:14.18$setupk4/"rec_mode=128 2006.173.17:32:14.18$setupk4/!* 2006.173.17:32:14.18$setupk4/recpk4 2006.173.17:32:14.18$recpk4/recpatch= 2006.173.17:32:14.19$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.17:32:14.19$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.17:32:14.19$setupk4/vck44 2006.173.17:32:14.19$vck44/valo=1,524.99 2006.173.17:32:14.19#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.17:32:14.19#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.17:32:14.19#ibcon#ireg 17 cls_cnt 0 2006.173.17:32:14.19#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.17:32:14.19#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.17:32:14.19#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.17:32:14.19#ibcon#enter wrdev, iclass 22, count 0 2006.173.17:32:14.19#ibcon#first serial, iclass 22, count 0 2006.173.17:32:14.19#ibcon#enter sib2, iclass 22, count 0 2006.173.17:32:14.19#ibcon#flushed, iclass 22, count 0 2006.173.17:32:14.19#ibcon#about to write, iclass 22, count 0 2006.173.17:32:14.19#ibcon#wrote, iclass 22, count 0 2006.173.17:32:14.19#ibcon#about to read 3, iclass 22, count 0 2006.173.17:32:14.20#ibcon#read 3, iclass 22, count 0 2006.173.17:32:14.20#ibcon#about to read 4, iclass 22, count 0 2006.173.17:32:14.20#ibcon#read 4, iclass 22, count 0 2006.173.17:32:14.20#ibcon#about to read 5, iclass 22, count 0 2006.173.17:32:14.20#ibcon#read 5, iclass 22, count 0 2006.173.17:32:14.20#ibcon#about to read 6, iclass 22, count 0 2006.173.17:32:14.20#ibcon#read 6, iclass 22, count 0 2006.173.17:32:14.20#ibcon#end of sib2, iclass 22, count 0 2006.173.17:32:14.20#ibcon#*mode == 0, iclass 22, count 0 2006.173.17:32:14.20#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.17:32:14.20#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.17:32:14.20#ibcon#*before write, iclass 22, count 0 2006.173.17:32:14.20#ibcon#enter sib2, iclass 22, count 0 2006.173.17:32:14.20#ibcon#flushed, iclass 22, count 0 2006.173.17:32:14.20#ibcon#about to write, iclass 22, count 0 2006.173.17:32:14.20#ibcon#wrote, iclass 22, count 0 2006.173.17:32:14.20#ibcon#about to read 3, iclass 22, count 0 2006.173.17:32:14.25#ibcon#read 3, iclass 22, count 0 2006.173.17:32:14.25#ibcon#about to read 4, iclass 22, count 0 2006.173.17:32:14.25#ibcon#read 4, iclass 22, count 0 2006.173.17:32:14.25#ibcon#about to read 5, iclass 22, count 0 2006.173.17:32:14.25#ibcon#read 5, iclass 22, count 0 2006.173.17:32:14.25#ibcon#about to read 6, iclass 22, count 0 2006.173.17:32:14.25#ibcon#read 6, iclass 22, count 0 2006.173.17:32:14.25#ibcon#end of sib2, iclass 22, count 0 2006.173.17:32:14.25#ibcon#*after write, iclass 22, count 0 2006.173.17:32:14.25#ibcon#*before return 0, iclass 22, count 0 2006.173.17:32:14.25#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.17:32:14.25#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.17:32:14.25#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.17:32:14.25#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.17:32:14.25$vck44/va=1,7 2006.173.17:32:14.25#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.17:32:14.25#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.17:32:14.25#ibcon#ireg 11 cls_cnt 2 2006.173.17:32:14.25#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.17:32:14.25#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.17:32:14.25#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.17:32:14.25#ibcon#enter wrdev, iclass 24, count 2 2006.173.17:32:14.25#ibcon#first serial, iclass 24, count 2 2006.173.17:32:14.25#ibcon#enter sib2, iclass 24, count 2 2006.173.17:32:14.25#ibcon#flushed, iclass 24, count 2 2006.173.17:32:14.25#ibcon#about to write, iclass 24, count 2 2006.173.17:32:14.25#ibcon#wrote, iclass 24, count 2 2006.173.17:32:14.25#ibcon#about to read 3, iclass 24, count 2 2006.173.17:32:14.27#ibcon#read 3, iclass 24, count 2 2006.173.17:32:14.27#ibcon#about to read 4, iclass 24, count 2 2006.173.17:32:14.27#ibcon#read 4, iclass 24, count 2 2006.173.17:32:14.27#ibcon#about to read 5, iclass 24, count 2 2006.173.17:32:14.27#ibcon#read 5, iclass 24, count 2 2006.173.17:32:14.27#ibcon#about to read 6, iclass 24, count 2 2006.173.17:32:14.27#ibcon#read 6, iclass 24, count 2 2006.173.17:32:14.27#ibcon#end of sib2, iclass 24, count 2 2006.173.17:32:14.27#ibcon#*mode == 0, iclass 24, count 2 2006.173.17:32:14.27#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.17:32:14.27#ibcon#[25=AT01-07\r\n] 2006.173.17:32:14.27#ibcon#*before write, iclass 24, count 2 2006.173.17:32:14.27#ibcon#enter sib2, iclass 24, count 2 2006.173.17:32:14.27#ibcon#flushed, iclass 24, count 2 2006.173.17:32:14.27#ibcon#about to write, iclass 24, count 2 2006.173.17:32:14.27#ibcon#wrote, iclass 24, count 2 2006.173.17:32:14.27#ibcon#about to read 3, iclass 24, count 2 2006.173.17:32:14.30#ibcon#read 3, iclass 24, count 2 2006.173.17:32:14.30#ibcon#about to read 4, iclass 24, count 2 2006.173.17:32:14.30#ibcon#read 4, iclass 24, count 2 2006.173.17:32:14.30#ibcon#about to read 5, iclass 24, count 2 2006.173.17:32:14.30#ibcon#read 5, iclass 24, count 2 2006.173.17:32:14.30#ibcon#about to read 6, iclass 24, count 2 2006.173.17:32:14.30#ibcon#read 6, iclass 24, count 2 2006.173.17:32:14.30#ibcon#end of sib2, iclass 24, count 2 2006.173.17:32:14.30#ibcon#*after write, iclass 24, count 2 2006.173.17:32:14.30#ibcon#*before return 0, iclass 24, count 2 2006.173.17:32:14.30#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.17:32:14.30#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.17:32:14.30#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.17:32:14.30#ibcon#ireg 7 cls_cnt 0 2006.173.17:32:14.30#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.17:32:14.42#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.17:32:14.42#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.17:32:14.42#ibcon#enter wrdev, iclass 24, count 0 2006.173.17:32:14.42#ibcon#first serial, iclass 24, count 0 2006.173.17:32:14.42#ibcon#enter sib2, iclass 24, count 0 2006.173.17:32:14.42#ibcon#flushed, iclass 24, count 0 2006.173.17:32:14.42#ibcon#about to write, iclass 24, count 0 2006.173.17:32:14.42#ibcon#wrote, iclass 24, count 0 2006.173.17:32:14.42#ibcon#about to read 3, iclass 24, count 0 2006.173.17:32:14.44#ibcon#read 3, iclass 24, count 0 2006.173.17:32:14.44#ibcon#about to read 4, iclass 24, count 0 2006.173.17:32:14.44#ibcon#read 4, iclass 24, count 0 2006.173.17:32:14.44#ibcon#about to read 5, iclass 24, count 0 2006.173.17:32:14.44#ibcon#read 5, iclass 24, count 0 2006.173.17:32:14.44#ibcon#about to read 6, iclass 24, count 0 2006.173.17:32:14.44#ibcon#read 6, iclass 24, count 0 2006.173.17:32:14.44#ibcon#end of sib2, iclass 24, count 0 2006.173.17:32:14.44#ibcon#*mode == 0, iclass 24, count 0 2006.173.17:32:14.44#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.17:32:14.44#ibcon#[25=USB\r\n] 2006.173.17:32:14.44#ibcon#*before write, iclass 24, count 0 2006.173.17:32:14.44#ibcon#enter sib2, iclass 24, count 0 2006.173.17:32:14.44#ibcon#flushed, iclass 24, count 0 2006.173.17:32:14.44#ibcon#about to write, iclass 24, count 0 2006.173.17:32:14.44#ibcon#wrote, iclass 24, count 0 2006.173.17:32:14.44#ibcon#about to read 3, iclass 24, count 0 2006.173.17:32:14.47#ibcon#read 3, iclass 24, count 0 2006.173.17:32:14.47#ibcon#about to read 4, iclass 24, count 0 2006.173.17:32:14.47#ibcon#read 4, iclass 24, count 0 2006.173.17:32:14.47#ibcon#about to read 5, iclass 24, count 0 2006.173.17:32:14.47#ibcon#read 5, iclass 24, count 0 2006.173.17:32:14.47#ibcon#about to read 6, iclass 24, count 0 2006.173.17:32:14.47#ibcon#read 6, iclass 24, count 0 2006.173.17:32:14.47#ibcon#end of sib2, iclass 24, count 0 2006.173.17:32:14.47#ibcon#*after write, iclass 24, count 0 2006.173.17:32:14.47#ibcon#*before return 0, iclass 24, count 0 2006.173.17:32:14.47#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.17:32:14.47#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.17:32:14.47#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.17:32:14.47#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.17:32:14.47$vck44/valo=2,534.99 2006.173.17:32:14.47#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.17:32:14.47#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.17:32:14.47#ibcon#ireg 17 cls_cnt 0 2006.173.17:32:14.47#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.17:32:14.47#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.17:32:14.47#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.17:32:14.47#ibcon#enter wrdev, iclass 26, count 0 2006.173.17:32:14.47#ibcon#first serial, iclass 26, count 0 2006.173.17:32:14.47#ibcon#enter sib2, iclass 26, count 0 2006.173.17:32:14.47#ibcon#flushed, iclass 26, count 0 2006.173.17:32:14.47#ibcon#about to write, iclass 26, count 0 2006.173.17:32:14.47#ibcon#wrote, iclass 26, count 0 2006.173.17:32:14.47#ibcon#about to read 3, iclass 26, count 0 2006.173.17:32:14.49#ibcon#read 3, iclass 26, count 0 2006.173.17:32:14.49#ibcon#about to read 4, iclass 26, count 0 2006.173.17:32:14.49#ibcon#read 4, iclass 26, count 0 2006.173.17:32:14.49#ibcon#about to read 5, iclass 26, count 0 2006.173.17:32:14.49#ibcon#read 5, iclass 26, count 0 2006.173.17:32:14.49#ibcon#about to read 6, iclass 26, count 0 2006.173.17:32:14.49#ibcon#read 6, iclass 26, count 0 2006.173.17:32:14.49#ibcon#end of sib2, iclass 26, count 0 2006.173.17:32:14.49#ibcon#*mode == 0, iclass 26, count 0 2006.173.17:32:14.49#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.17:32:14.49#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.17:32:14.49#ibcon#*before write, iclass 26, count 0 2006.173.17:32:14.49#ibcon#enter sib2, iclass 26, count 0 2006.173.17:32:14.49#ibcon#flushed, iclass 26, count 0 2006.173.17:32:14.49#ibcon#about to write, iclass 26, count 0 2006.173.17:32:14.49#ibcon#wrote, iclass 26, count 0 2006.173.17:32:14.49#ibcon#about to read 3, iclass 26, count 0 2006.173.17:32:14.53#ibcon#read 3, iclass 26, count 0 2006.173.17:32:14.53#ibcon#about to read 4, iclass 26, count 0 2006.173.17:32:14.53#ibcon#read 4, iclass 26, count 0 2006.173.17:32:14.53#ibcon#about to read 5, iclass 26, count 0 2006.173.17:32:14.53#ibcon#read 5, iclass 26, count 0 2006.173.17:32:14.53#ibcon#about to read 6, iclass 26, count 0 2006.173.17:32:14.53#ibcon#read 6, iclass 26, count 0 2006.173.17:32:14.53#ibcon#end of sib2, iclass 26, count 0 2006.173.17:32:14.53#ibcon#*after write, iclass 26, count 0 2006.173.17:32:14.53#ibcon#*before return 0, iclass 26, count 0 2006.173.17:32:14.53#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.17:32:14.53#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.17:32:14.53#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.17:32:14.53#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.17:32:14.53$vck44/va=2,6 2006.173.17:32:14.53#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.17:32:14.53#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.17:32:14.53#ibcon#ireg 11 cls_cnt 2 2006.173.17:32:14.53#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.17:32:14.59#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.17:32:14.59#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.17:32:14.59#ibcon#enter wrdev, iclass 28, count 2 2006.173.17:32:14.59#ibcon#first serial, iclass 28, count 2 2006.173.17:32:14.59#ibcon#enter sib2, iclass 28, count 2 2006.173.17:32:14.59#ibcon#flushed, iclass 28, count 2 2006.173.17:32:14.59#ibcon#about to write, iclass 28, count 2 2006.173.17:32:14.59#ibcon#wrote, iclass 28, count 2 2006.173.17:32:14.59#ibcon#about to read 3, iclass 28, count 2 2006.173.17:32:14.61#ibcon#read 3, iclass 28, count 2 2006.173.17:32:14.61#ibcon#about to read 4, iclass 28, count 2 2006.173.17:32:14.61#ibcon#read 4, iclass 28, count 2 2006.173.17:32:14.61#ibcon#about to read 5, iclass 28, count 2 2006.173.17:32:14.61#ibcon#read 5, iclass 28, count 2 2006.173.17:32:14.61#ibcon#about to read 6, iclass 28, count 2 2006.173.17:32:14.61#ibcon#read 6, iclass 28, count 2 2006.173.17:32:14.61#ibcon#end of sib2, iclass 28, count 2 2006.173.17:32:14.61#ibcon#*mode == 0, iclass 28, count 2 2006.173.17:32:14.61#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.17:32:14.61#ibcon#[25=AT02-06\r\n] 2006.173.17:32:14.61#ibcon#*before write, iclass 28, count 2 2006.173.17:32:14.61#ibcon#enter sib2, iclass 28, count 2 2006.173.17:32:14.61#ibcon#flushed, iclass 28, count 2 2006.173.17:32:14.61#ibcon#about to write, iclass 28, count 2 2006.173.17:32:14.61#ibcon#wrote, iclass 28, count 2 2006.173.17:32:14.61#ibcon#about to read 3, iclass 28, count 2 2006.173.17:32:14.64#ibcon#read 3, iclass 28, count 2 2006.173.17:32:14.64#ibcon#about to read 4, iclass 28, count 2 2006.173.17:32:14.64#ibcon#read 4, iclass 28, count 2 2006.173.17:32:14.64#ibcon#about to read 5, iclass 28, count 2 2006.173.17:32:14.64#ibcon#read 5, iclass 28, count 2 2006.173.17:32:14.64#ibcon#about to read 6, iclass 28, count 2 2006.173.17:32:14.64#ibcon#read 6, iclass 28, count 2 2006.173.17:32:14.64#ibcon#end of sib2, iclass 28, count 2 2006.173.17:32:14.64#ibcon#*after write, iclass 28, count 2 2006.173.17:32:14.64#ibcon#*before return 0, iclass 28, count 2 2006.173.17:32:14.64#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.17:32:14.64#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.17:32:14.64#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.17:32:14.64#ibcon#ireg 7 cls_cnt 0 2006.173.17:32:14.64#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.17:32:14.76#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.17:32:14.76#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.17:32:14.76#ibcon#enter wrdev, iclass 28, count 0 2006.173.17:32:14.76#ibcon#first serial, iclass 28, count 0 2006.173.17:32:14.76#ibcon#enter sib2, iclass 28, count 0 2006.173.17:32:14.76#ibcon#flushed, iclass 28, count 0 2006.173.17:32:14.76#ibcon#about to write, iclass 28, count 0 2006.173.17:32:14.76#ibcon#wrote, iclass 28, count 0 2006.173.17:32:14.76#ibcon#about to read 3, iclass 28, count 0 2006.173.17:32:14.78#ibcon#read 3, iclass 28, count 0 2006.173.17:32:14.78#ibcon#about to read 4, iclass 28, count 0 2006.173.17:32:14.78#ibcon#read 4, iclass 28, count 0 2006.173.17:32:14.78#ibcon#about to read 5, iclass 28, count 0 2006.173.17:32:14.78#ibcon#read 5, iclass 28, count 0 2006.173.17:32:14.78#ibcon#about to read 6, iclass 28, count 0 2006.173.17:32:14.78#ibcon#read 6, iclass 28, count 0 2006.173.17:32:14.78#ibcon#end of sib2, iclass 28, count 0 2006.173.17:32:14.78#ibcon#*mode == 0, iclass 28, count 0 2006.173.17:32:14.78#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.17:32:14.78#ibcon#[25=USB\r\n] 2006.173.17:32:14.78#ibcon#*before write, iclass 28, count 0 2006.173.17:32:14.78#ibcon#enter sib2, iclass 28, count 0 2006.173.17:32:14.78#ibcon#flushed, iclass 28, count 0 2006.173.17:32:14.78#ibcon#about to write, iclass 28, count 0 2006.173.17:32:14.78#ibcon#wrote, iclass 28, count 0 2006.173.17:32:14.78#ibcon#about to read 3, iclass 28, count 0 2006.173.17:32:14.81#ibcon#read 3, iclass 28, count 0 2006.173.17:32:14.81#ibcon#about to read 4, iclass 28, count 0 2006.173.17:32:14.81#ibcon#read 4, iclass 28, count 0 2006.173.17:32:14.81#ibcon#about to read 5, iclass 28, count 0 2006.173.17:32:14.81#ibcon#read 5, iclass 28, count 0 2006.173.17:32:14.81#ibcon#about to read 6, iclass 28, count 0 2006.173.17:32:14.81#ibcon#read 6, iclass 28, count 0 2006.173.17:32:14.81#ibcon#end of sib2, iclass 28, count 0 2006.173.17:32:14.81#ibcon#*after write, iclass 28, count 0 2006.173.17:32:14.81#ibcon#*before return 0, iclass 28, count 0 2006.173.17:32:14.81#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.17:32:14.81#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.17:32:14.81#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.17:32:14.81#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.17:32:14.81$vck44/valo=3,564.99 2006.173.17:32:14.81#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.17:32:14.81#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.17:32:14.81#ibcon#ireg 17 cls_cnt 0 2006.173.17:32:14.81#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.17:32:14.81#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.17:32:14.81#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.17:32:14.81#ibcon#enter wrdev, iclass 30, count 0 2006.173.17:32:14.81#ibcon#first serial, iclass 30, count 0 2006.173.17:32:14.81#ibcon#enter sib2, iclass 30, count 0 2006.173.17:32:14.81#ibcon#flushed, iclass 30, count 0 2006.173.17:32:14.81#ibcon#about to write, iclass 30, count 0 2006.173.17:32:14.81#ibcon#wrote, iclass 30, count 0 2006.173.17:32:14.81#ibcon#about to read 3, iclass 30, count 0 2006.173.17:32:14.83#ibcon#read 3, iclass 30, count 0 2006.173.17:32:14.83#ibcon#about to read 4, iclass 30, count 0 2006.173.17:32:14.83#ibcon#read 4, iclass 30, count 0 2006.173.17:32:14.83#ibcon#about to read 5, iclass 30, count 0 2006.173.17:32:14.83#ibcon#read 5, iclass 30, count 0 2006.173.17:32:14.83#ibcon#about to read 6, iclass 30, count 0 2006.173.17:32:14.83#ibcon#read 6, iclass 30, count 0 2006.173.17:32:14.83#ibcon#end of sib2, iclass 30, count 0 2006.173.17:32:14.83#ibcon#*mode == 0, iclass 30, count 0 2006.173.17:32:14.83#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.17:32:14.83#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.17:32:14.83#ibcon#*before write, iclass 30, count 0 2006.173.17:32:14.83#ibcon#enter sib2, iclass 30, count 0 2006.173.17:32:14.83#ibcon#flushed, iclass 30, count 0 2006.173.17:32:14.83#ibcon#about to write, iclass 30, count 0 2006.173.17:32:14.83#ibcon#wrote, iclass 30, count 0 2006.173.17:32:14.83#ibcon#about to read 3, iclass 30, count 0 2006.173.17:32:14.87#ibcon#read 3, iclass 30, count 0 2006.173.17:32:14.87#ibcon#about to read 4, iclass 30, count 0 2006.173.17:32:14.87#ibcon#read 4, iclass 30, count 0 2006.173.17:32:14.87#ibcon#about to read 5, iclass 30, count 0 2006.173.17:32:14.87#ibcon#read 5, iclass 30, count 0 2006.173.17:32:14.87#ibcon#about to read 6, iclass 30, count 0 2006.173.17:32:14.87#ibcon#read 6, iclass 30, count 0 2006.173.17:32:14.87#ibcon#end of sib2, iclass 30, count 0 2006.173.17:32:14.87#ibcon#*after write, iclass 30, count 0 2006.173.17:32:14.87#ibcon#*before return 0, iclass 30, count 0 2006.173.17:32:14.87#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.17:32:14.87#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.17:32:14.87#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.17:32:14.87#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.17:32:14.87$vck44/va=3,5 2006.173.17:32:14.87#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.173.17:32:14.87#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.173.17:32:14.87#ibcon#ireg 11 cls_cnt 2 2006.173.17:32:14.87#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.17:32:14.93#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.17:32:14.93#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.17:32:14.93#ibcon#enter wrdev, iclass 32, count 2 2006.173.17:32:14.93#ibcon#first serial, iclass 32, count 2 2006.173.17:32:14.93#ibcon#enter sib2, iclass 32, count 2 2006.173.17:32:14.93#ibcon#flushed, iclass 32, count 2 2006.173.17:32:14.93#ibcon#about to write, iclass 32, count 2 2006.173.17:32:14.93#ibcon#wrote, iclass 32, count 2 2006.173.17:32:14.93#ibcon#about to read 3, iclass 32, count 2 2006.173.17:32:14.95#ibcon#read 3, iclass 32, count 2 2006.173.17:32:14.95#ibcon#about to read 4, iclass 32, count 2 2006.173.17:32:14.95#ibcon#read 4, iclass 32, count 2 2006.173.17:32:14.95#ibcon#about to read 5, iclass 32, count 2 2006.173.17:32:14.95#ibcon#read 5, iclass 32, count 2 2006.173.17:32:14.95#ibcon#about to read 6, iclass 32, count 2 2006.173.17:32:14.95#ibcon#read 6, iclass 32, count 2 2006.173.17:32:14.95#ibcon#end of sib2, iclass 32, count 2 2006.173.17:32:14.95#ibcon#*mode == 0, iclass 32, count 2 2006.173.17:32:14.95#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.173.17:32:14.95#ibcon#[25=AT03-05\r\n] 2006.173.17:32:14.95#ibcon#*before write, iclass 32, count 2 2006.173.17:32:14.95#ibcon#enter sib2, iclass 32, count 2 2006.173.17:32:14.95#ibcon#flushed, iclass 32, count 2 2006.173.17:32:14.95#ibcon#about to write, iclass 32, count 2 2006.173.17:32:14.95#ibcon#wrote, iclass 32, count 2 2006.173.17:32:14.95#ibcon#about to read 3, iclass 32, count 2 2006.173.17:32:14.98#ibcon#read 3, iclass 32, count 2 2006.173.17:32:14.98#ibcon#about to read 4, iclass 32, count 2 2006.173.17:32:14.98#ibcon#read 4, iclass 32, count 2 2006.173.17:32:14.98#ibcon#about to read 5, iclass 32, count 2 2006.173.17:32:14.98#ibcon#read 5, iclass 32, count 2 2006.173.17:32:14.98#ibcon#about to read 6, iclass 32, count 2 2006.173.17:32:14.98#ibcon#read 6, iclass 32, count 2 2006.173.17:32:14.98#ibcon#end of sib2, iclass 32, count 2 2006.173.17:32:14.98#ibcon#*after write, iclass 32, count 2 2006.173.17:32:14.98#ibcon#*before return 0, iclass 32, count 2 2006.173.17:32:14.98#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.17:32:14.98#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.173.17:32:14.98#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.173.17:32:14.98#ibcon#ireg 7 cls_cnt 0 2006.173.17:32:14.98#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.17:32:15.10#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.17:32:15.10#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.17:32:15.10#ibcon#enter wrdev, iclass 32, count 0 2006.173.17:32:15.10#ibcon#first serial, iclass 32, count 0 2006.173.17:32:15.10#ibcon#enter sib2, iclass 32, count 0 2006.173.17:32:15.10#ibcon#flushed, iclass 32, count 0 2006.173.17:32:15.10#ibcon#about to write, iclass 32, count 0 2006.173.17:32:15.10#ibcon#wrote, iclass 32, count 0 2006.173.17:32:15.10#ibcon#about to read 3, iclass 32, count 0 2006.173.17:32:15.12#ibcon#read 3, iclass 32, count 0 2006.173.17:32:15.12#ibcon#about to read 4, iclass 32, count 0 2006.173.17:32:15.12#ibcon#read 4, iclass 32, count 0 2006.173.17:32:15.12#ibcon#about to read 5, iclass 32, count 0 2006.173.17:32:15.12#ibcon#read 5, iclass 32, count 0 2006.173.17:32:15.12#ibcon#about to read 6, iclass 32, count 0 2006.173.17:32:15.12#ibcon#read 6, iclass 32, count 0 2006.173.17:32:15.12#ibcon#end of sib2, iclass 32, count 0 2006.173.17:32:15.12#ibcon#*mode == 0, iclass 32, count 0 2006.173.17:32:15.12#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.17:32:15.12#ibcon#[25=USB\r\n] 2006.173.17:32:15.12#ibcon#*before write, iclass 32, count 0 2006.173.17:32:15.12#ibcon#enter sib2, iclass 32, count 0 2006.173.17:32:15.12#ibcon#flushed, iclass 32, count 0 2006.173.17:32:15.12#ibcon#about to write, iclass 32, count 0 2006.173.17:32:15.12#ibcon#wrote, iclass 32, count 0 2006.173.17:32:15.12#ibcon#about to read 3, iclass 32, count 0 2006.173.17:32:15.15#ibcon#read 3, iclass 32, count 0 2006.173.17:32:15.15#ibcon#about to read 4, iclass 32, count 0 2006.173.17:32:15.15#ibcon#read 4, iclass 32, count 0 2006.173.17:32:15.15#ibcon#about to read 5, iclass 32, count 0 2006.173.17:32:15.15#ibcon#read 5, iclass 32, count 0 2006.173.17:32:15.15#ibcon#about to read 6, iclass 32, count 0 2006.173.17:32:15.15#ibcon#read 6, iclass 32, count 0 2006.173.17:32:15.15#ibcon#end of sib2, iclass 32, count 0 2006.173.17:32:15.15#ibcon#*after write, iclass 32, count 0 2006.173.17:32:15.15#ibcon#*before return 0, iclass 32, count 0 2006.173.17:32:15.15#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.17:32:15.15#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.173.17:32:15.15#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.17:32:15.15#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.17:32:15.15$vck44/valo=4,624.99 2006.173.17:32:15.15#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.17:32:15.15#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.17:32:15.15#ibcon#ireg 17 cls_cnt 0 2006.173.17:32:15.15#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.17:32:15.15#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.17:32:15.15#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.17:32:15.15#ibcon#enter wrdev, iclass 34, count 0 2006.173.17:32:15.15#ibcon#first serial, iclass 34, count 0 2006.173.17:32:15.15#ibcon#enter sib2, iclass 34, count 0 2006.173.17:32:15.15#ibcon#flushed, iclass 34, count 0 2006.173.17:32:15.15#ibcon#about to write, iclass 34, count 0 2006.173.17:32:15.15#ibcon#wrote, iclass 34, count 0 2006.173.17:32:15.15#ibcon#about to read 3, iclass 34, count 0 2006.173.17:32:15.17#ibcon#read 3, iclass 34, count 0 2006.173.17:32:15.17#ibcon#about to read 4, iclass 34, count 0 2006.173.17:32:15.17#ibcon#read 4, iclass 34, count 0 2006.173.17:32:15.17#ibcon#about to read 5, iclass 34, count 0 2006.173.17:32:15.17#ibcon#read 5, iclass 34, count 0 2006.173.17:32:15.17#ibcon#about to read 6, iclass 34, count 0 2006.173.17:32:15.17#ibcon#read 6, iclass 34, count 0 2006.173.17:32:15.17#ibcon#end of sib2, iclass 34, count 0 2006.173.17:32:15.17#ibcon#*mode == 0, iclass 34, count 0 2006.173.17:32:15.17#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.17:32:15.17#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.17:32:15.17#ibcon#*before write, iclass 34, count 0 2006.173.17:32:15.17#ibcon#enter sib2, iclass 34, count 0 2006.173.17:32:15.17#ibcon#flushed, iclass 34, count 0 2006.173.17:32:15.17#ibcon#about to write, iclass 34, count 0 2006.173.17:32:15.17#ibcon#wrote, iclass 34, count 0 2006.173.17:32:15.17#ibcon#about to read 3, iclass 34, count 0 2006.173.17:32:15.21#ibcon#read 3, iclass 34, count 0 2006.173.17:32:15.21#ibcon#about to read 4, iclass 34, count 0 2006.173.17:32:15.21#ibcon#read 4, iclass 34, count 0 2006.173.17:32:15.21#ibcon#about to read 5, iclass 34, count 0 2006.173.17:32:15.21#ibcon#read 5, iclass 34, count 0 2006.173.17:32:15.21#ibcon#about to read 6, iclass 34, count 0 2006.173.17:32:15.21#ibcon#read 6, iclass 34, count 0 2006.173.17:32:15.21#ibcon#end of sib2, iclass 34, count 0 2006.173.17:32:15.21#ibcon#*after write, iclass 34, count 0 2006.173.17:32:15.21#ibcon#*before return 0, iclass 34, count 0 2006.173.17:32:15.21#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.17:32:15.21#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.17:32:15.21#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.17:32:15.21#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.17:32:15.21$vck44/va=4,6 2006.173.17:32:15.21#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.17:32:15.21#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.17:32:15.21#ibcon#ireg 11 cls_cnt 2 2006.173.17:32:15.21#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.17:32:15.27#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.17:32:15.27#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.17:32:15.27#ibcon#enter wrdev, iclass 36, count 2 2006.173.17:32:15.27#ibcon#first serial, iclass 36, count 2 2006.173.17:32:15.27#ibcon#enter sib2, iclass 36, count 2 2006.173.17:32:15.27#ibcon#flushed, iclass 36, count 2 2006.173.17:32:15.27#ibcon#about to write, iclass 36, count 2 2006.173.17:32:15.27#ibcon#wrote, iclass 36, count 2 2006.173.17:32:15.27#ibcon#about to read 3, iclass 36, count 2 2006.173.17:32:15.29#ibcon#read 3, iclass 36, count 2 2006.173.17:32:15.29#ibcon#about to read 4, iclass 36, count 2 2006.173.17:32:15.29#ibcon#read 4, iclass 36, count 2 2006.173.17:32:15.29#ibcon#about to read 5, iclass 36, count 2 2006.173.17:32:15.29#ibcon#read 5, iclass 36, count 2 2006.173.17:32:15.29#ibcon#about to read 6, iclass 36, count 2 2006.173.17:32:15.29#ibcon#read 6, iclass 36, count 2 2006.173.17:32:15.29#ibcon#end of sib2, iclass 36, count 2 2006.173.17:32:15.29#ibcon#*mode == 0, iclass 36, count 2 2006.173.17:32:15.29#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.17:32:15.29#ibcon#[25=AT04-06\r\n] 2006.173.17:32:15.29#ibcon#*before write, iclass 36, count 2 2006.173.17:32:15.29#ibcon#enter sib2, iclass 36, count 2 2006.173.17:32:15.29#ibcon#flushed, iclass 36, count 2 2006.173.17:32:15.29#ibcon#about to write, iclass 36, count 2 2006.173.17:32:15.29#ibcon#wrote, iclass 36, count 2 2006.173.17:32:15.29#ibcon#about to read 3, iclass 36, count 2 2006.173.17:32:15.32#ibcon#read 3, iclass 36, count 2 2006.173.17:32:15.32#ibcon#about to read 4, iclass 36, count 2 2006.173.17:32:15.32#ibcon#read 4, iclass 36, count 2 2006.173.17:32:15.32#ibcon#about to read 5, iclass 36, count 2 2006.173.17:32:15.32#ibcon#read 5, iclass 36, count 2 2006.173.17:32:15.32#ibcon#about to read 6, iclass 36, count 2 2006.173.17:32:15.32#ibcon#read 6, iclass 36, count 2 2006.173.17:32:15.32#ibcon#end of sib2, iclass 36, count 2 2006.173.17:32:15.32#ibcon#*after write, iclass 36, count 2 2006.173.17:32:15.32#ibcon#*before return 0, iclass 36, count 2 2006.173.17:32:15.32#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.17:32:15.32#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.17:32:15.32#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.17:32:15.32#ibcon#ireg 7 cls_cnt 0 2006.173.17:32:15.32#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.17:32:15.44#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.17:32:15.44#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.17:32:15.44#ibcon#enter wrdev, iclass 36, count 0 2006.173.17:32:15.44#ibcon#first serial, iclass 36, count 0 2006.173.17:32:15.44#ibcon#enter sib2, iclass 36, count 0 2006.173.17:32:15.44#ibcon#flushed, iclass 36, count 0 2006.173.17:32:15.44#ibcon#about to write, iclass 36, count 0 2006.173.17:32:15.44#ibcon#wrote, iclass 36, count 0 2006.173.17:32:15.44#ibcon#about to read 3, iclass 36, count 0 2006.173.17:32:15.46#ibcon#read 3, iclass 36, count 0 2006.173.17:32:15.46#ibcon#about to read 4, iclass 36, count 0 2006.173.17:32:15.46#ibcon#read 4, iclass 36, count 0 2006.173.17:32:15.46#ibcon#about to read 5, iclass 36, count 0 2006.173.17:32:15.46#ibcon#read 5, iclass 36, count 0 2006.173.17:32:15.46#ibcon#about to read 6, iclass 36, count 0 2006.173.17:32:15.46#ibcon#read 6, iclass 36, count 0 2006.173.17:32:15.46#ibcon#end of sib2, iclass 36, count 0 2006.173.17:32:15.46#ibcon#*mode == 0, iclass 36, count 0 2006.173.17:32:15.46#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.17:32:15.46#ibcon#[25=USB\r\n] 2006.173.17:32:15.46#ibcon#*before write, iclass 36, count 0 2006.173.17:32:15.46#ibcon#enter sib2, iclass 36, count 0 2006.173.17:32:15.46#ibcon#flushed, iclass 36, count 0 2006.173.17:32:15.46#ibcon#about to write, iclass 36, count 0 2006.173.17:32:15.46#ibcon#wrote, iclass 36, count 0 2006.173.17:32:15.46#ibcon#about to read 3, iclass 36, count 0 2006.173.17:32:15.49#ibcon#read 3, iclass 36, count 0 2006.173.17:32:15.49#ibcon#about to read 4, iclass 36, count 0 2006.173.17:32:15.49#ibcon#read 4, iclass 36, count 0 2006.173.17:32:15.49#ibcon#about to read 5, iclass 36, count 0 2006.173.17:32:15.49#ibcon#read 5, iclass 36, count 0 2006.173.17:32:15.49#ibcon#about to read 6, iclass 36, count 0 2006.173.17:32:15.49#ibcon#read 6, iclass 36, count 0 2006.173.17:32:15.49#ibcon#end of sib2, iclass 36, count 0 2006.173.17:32:15.49#ibcon#*after write, iclass 36, count 0 2006.173.17:32:15.49#ibcon#*before return 0, iclass 36, count 0 2006.173.17:32:15.49#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.17:32:15.49#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.17:32:15.49#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.17:32:15.49#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.17:32:15.49$vck44/valo=5,734.99 2006.173.17:32:15.49#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.17:32:15.49#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.17:32:15.49#ibcon#ireg 17 cls_cnt 0 2006.173.17:32:15.49#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.17:32:15.49#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.17:32:15.49#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.17:32:15.49#ibcon#enter wrdev, iclass 38, count 0 2006.173.17:32:15.49#ibcon#first serial, iclass 38, count 0 2006.173.17:32:15.49#ibcon#enter sib2, iclass 38, count 0 2006.173.17:32:15.49#ibcon#flushed, iclass 38, count 0 2006.173.17:32:15.49#ibcon#about to write, iclass 38, count 0 2006.173.17:32:15.49#ibcon#wrote, iclass 38, count 0 2006.173.17:32:15.49#ibcon#about to read 3, iclass 38, count 0 2006.173.17:32:15.51#ibcon#read 3, iclass 38, count 0 2006.173.17:32:15.51#ibcon#about to read 4, iclass 38, count 0 2006.173.17:32:15.51#ibcon#read 4, iclass 38, count 0 2006.173.17:32:15.51#ibcon#about to read 5, iclass 38, count 0 2006.173.17:32:15.51#ibcon#read 5, iclass 38, count 0 2006.173.17:32:15.51#ibcon#about to read 6, iclass 38, count 0 2006.173.17:32:15.51#ibcon#read 6, iclass 38, count 0 2006.173.17:32:15.51#ibcon#end of sib2, iclass 38, count 0 2006.173.17:32:15.51#ibcon#*mode == 0, iclass 38, count 0 2006.173.17:32:15.51#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.17:32:15.51#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.17:32:15.51#ibcon#*before write, iclass 38, count 0 2006.173.17:32:15.51#ibcon#enter sib2, iclass 38, count 0 2006.173.17:32:15.51#ibcon#flushed, iclass 38, count 0 2006.173.17:32:15.51#ibcon#about to write, iclass 38, count 0 2006.173.17:32:15.51#ibcon#wrote, iclass 38, count 0 2006.173.17:32:15.51#ibcon#about to read 3, iclass 38, count 0 2006.173.17:32:15.55#ibcon#read 3, iclass 38, count 0 2006.173.17:32:15.55#ibcon#about to read 4, iclass 38, count 0 2006.173.17:32:15.55#ibcon#read 4, iclass 38, count 0 2006.173.17:32:15.55#ibcon#about to read 5, iclass 38, count 0 2006.173.17:32:15.55#ibcon#read 5, iclass 38, count 0 2006.173.17:32:15.55#ibcon#about to read 6, iclass 38, count 0 2006.173.17:32:15.55#ibcon#read 6, iclass 38, count 0 2006.173.17:32:15.55#ibcon#end of sib2, iclass 38, count 0 2006.173.17:32:15.55#ibcon#*after write, iclass 38, count 0 2006.173.17:32:15.55#ibcon#*before return 0, iclass 38, count 0 2006.173.17:32:15.55#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.17:32:15.55#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.17:32:15.55#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.17:32:15.55#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.17:32:15.55$vck44/va=5,4 2006.173.17:32:15.55#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.17:32:15.55#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.17:32:15.55#ibcon#ireg 11 cls_cnt 2 2006.173.17:32:15.55#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.17:32:15.61#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.17:32:15.61#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.17:32:15.61#ibcon#enter wrdev, iclass 40, count 2 2006.173.17:32:15.61#ibcon#first serial, iclass 40, count 2 2006.173.17:32:15.61#ibcon#enter sib2, iclass 40, count 2 2006.173.17:32:15.61#ibcon#flushed, iclass 40, count 2 2006.173.17:32:15.61#ibcon#about to write, iclass 40, count 2 2006.173.17:32:15.61#ibcon#wrote, iclass 40, count 2 2006.173.17:32:15.61#ibcon#about to read 3, iclass 40, count 2 2006.173.17:32:15.63#ibcon#read 3, iclass 40, count 2 2006.173.17:32:15.63#ibcon#about to read 4, iclass 40, count 2 2006.173.17:32:15.63#ibcon#read 4, iclass 40, count 2 2006.173.17:32:15.63#ibcon#about to read 5, iclass 40, count 2 2006.173.17:32:15.63#ibcon#read 5, iclass 40, count 2 2006.173.17:32:15.63#ibcon#about to read 6, iclass 40, count 2 2006.173.17:32:15.63#ibcon#read 6, iclass 40, count 2 2006.173.17:32:15.63#ibcon#end of sib2, iclass 40, count 2 2006.173.17:32:15.63#ibcon#*mode == 0, iclass 40, count 2 2006.173.17:32:15.63#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.17:32:15.63#ibcon#[25=AT05-04\r\n] 2006.173.17:32:15.63#ibcon#*before write, iclass 40, count 2 2006.173.17:32:15.63#ibcon#enter sib2, iclass 40, count 2 2006.173.17:32:15.63#ibcon#flushed, iclass 40, count 2 2006.173.17:32:15.63#ibcon#about to write, iclass 40, count 2 2006.173.17:32:15.63#ibcon#wrote, iclass 40, count 2 2006.173.17:32:15.63#ibcon#about to read 3, iclass 40, count 2 2006.173.17:32:15.66#ibcon#read 3, iclass 40, count 2 2006.173.17:32:15.66#ibcon#about to read 4, iclass 40, count 2 2006.173.17:32:15.66#ibcon#read 4, iclass 40, count 2 2006.173.17:32:15.66#ibcon#about to read 5, iclass 40, count 2 2006.173.17:32:15.66#ibcon#read 5, iclass 40, count 2 2006.173.17:32:15.66#ibcon#about to read 6, iclass 40, count 2 2006.173.17:32:15.66#ibcon#read 6, iclass 40, count 2 2006.173.17:32:15.66#ibcon#end of sib2, iclass 40, count 2 2006.173.17:32:15.66#ibcon#*after write, iclass 40, count 2 2006.173.17:32:15.66#ibcon#*before return 0, iclass 40, count 2 2006.173.17:32:15.66#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.17:32:15.66#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.17:32:15.66#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.17:32:15.66#ibcon#ireg 7 cls_cnt 0 2006.173.17:32:15.66#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.17:32:15.78#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.17:32:15.78#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.17:32:15.78#ibcon#enter wrdev, iclass 40, count 0 2006.173.17:32:15.78#ibcon#first serial, iclass 40, count 0 2006.173.17:32:15.78#ibcon#enter sib2, iclass 40, count 0 2006.173.17:32:15.78#ibcon#flushed, iclass 40, count 0 2006.173.17:32:15.78#ibcon#about to write, iclass 40, count 0 2006.173.17:32:15.78#ibcon#wrote, iclass 40, count 0 2006.173.17:32:15.78#ibcon#about to read 3, iclass 40, count 0 2006.173.17:32:15.80#ibcon#read 3, iclass 40, count 0 2006.173.17:32:15.80#ibcon#about to read 4, iclass 40, count 0 2006.173.17:32:15.80#ibcon#read 4, iclass 40, count 0 2006.173.17:32:15.80#ibcon#about to read 5, iclass 40, count 0 2006.173.17:32:15.80#ibcon#read 5, iclass 40, count 0 2006.173.17:32:15.80#ibcon#about to read 6, iclass 40, count 0 2006.173.17:32:15.80#ibcon#read 6, iclass 40, count 0 2006.173.17:32:15.80#ibcon#end of sib2, iclass 40, count 0 2006.173.17:32:15.80#ibcon#*mode == 0, iclass 40, count 0 2006.173.17:32:15.80#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.17:32:15.80#ibcon#[25=USB\r\n] 2006.173.17:32:15.80#ibcon#*before write, iclass 40, count 0 2006.173.17:32:15.80#ibcon#enter sib2, iclass 40, count 0 2006.173.17:32:15.80#ibcon#flushed, iclass 40, count 0 2006.173.17:32:15.80#ibcon#about to write, iclass 40, count 0 2006.173.17:32:15.80#ibcon#wrote, iclass 40, count 0 2006.173.17:32:15.80#ibcon#about to read 3, iclass 40, count 0 2006.173.17:32:15.83#ibcon#read 3, iclass 40, count 0 2006.173.17:32:15.83#ibcon#about to read 4, iclass 40, count 0 2006.173.17:32:15.83#ibcon#read 4, iclass 40, count 0 2006.173.17:32:15.83#ibcon#about to read 5, iclass 40, count 0 2006.173.17:32:15.83#ibcon#read 5, iclass 40, count 0 2006.173.17:32:15.83#ibcon#about to read 6, iclass 40, count 0 2006.173.17:32:15.83#ibcon#read 6, iclass 40, count 0 2006.173.17:32:15.83#ibcon#end of sib2, iclass 40, count 0 2006.173.17:32:15.83#ibcon#*after write, iclass 40, count 0 2006.173.17:32:15.83#ibcon#*before return 0, iclass 40, count 0 2006.173.17:32:15.83#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.17:32:15.83#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.17:32:15.83#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.17:32:15.83#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.17:32:15.83$vck44/valo=6,814.99 2006.173.17:32:15.83#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.17:32:15.83#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.17:32:15.83#ibcon#ireg 17 cls_cnt 0 2006.173.17:32:15.83#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.17:32:15.83#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.17:32:15.83#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.17:32:15.83#ibcon#enter wrdev, iclass 4, count 0 2006.173.17:32:15.83#ibcon#first serial, iclass 4, count 0 2006.173.17:32:15.83#ibcon#enter sib2, iclass 4, count 0 2006.173.17:32:15.83#ibcon#flushed, iclass 4, count 0 2006.173.17:32:15.83#ibcon#about to write, iclass 4, count 0 2006.173.17:32:15.83#ibcon#wrote, iclass 4, count 0 2006.173.17:32:15.83#ibcon#about to read 3, iclass 4, count 0 2006.173.17:32:15.85#ibcon#read 3, iclass 4, count 0 2006.173.17:32:15.85#ibcon#about to read 4, iclass 4, count 0 2006.173.17:32:15.85#ibcon#read 4, iclass 4, count 0 2006.173.17:32:15.85#ibcon#about to read 5, iclass 4, count 0 2006.173.17:32:15.85#ibcon#read 5, iclass 4, count 0 2006.173.17:32:15.85#ibcon#about to read 6, iclass 4, count 0 2006.173.17:32:15.85#ibcon#read 6, iclass 4, count 0 2006.173.17:32:15.85#ibcon#end of sib2, iclass 4, count 0 2006.173.17:32:15.85#ibcon#*mode == 0, iclass 4, count 0 2006.173.17:32:15.85#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.17:32:15.85#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.17:32:15.85#ibcon#*before write, iclass 4, count 0 2006.173.17:32:15.85#ibcon#enter sib2, iclass 4, count 0 2006.173.17:32:15.85#ibcon#flushed, iclass 4, count 0 2006.173.17:32:15.85#ibcon#about to write, iclass 4, count 0 2006.173.17:32:15.85#ibcon#wrote, iclass 4, count 0 2006.173.17:32:15.85#ibcon#about to read 3, iclass 4, count 0 2006.173.17:32:15.89#ibcon#read 3, iclass 4, count 0 2006.173.17:32:15.89#ibcon#about to read 4, iclass 4, count 0 2006.173.17:32:15.89#ibcon#read 4, iclass 4, count 0 2006.173.17:32:15.89#ibcon#about to read 5, iclass 4, count 0 2006.173.17:32:15.89#ibcon#read 5, iclass 4, count 0 2006.173.17:32:15.89#ibcon#about to read 6, iclass 4, count 0 2006.173.17:32:15.89#ibcon#read 6, iclass 4, count 0 2006.173.17:32:15.89#ibcon#end of sib2, iclass 4, count 0 2006.173.17:32:15.89#ibcon#*after write, iclass 4, count 0 2006.173.17:32:15.89#ibcon#*before return 0, iclass 4, count 0 2006.173.17:32:15.89#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.17:32:15.89#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.17:32:15.89#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.17:32:15.89#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.17:32:15.89$vck44/va=6,3 2006.173.17:32:15.89#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.17:32:15.89#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.17:32:15.89#ibcon#ireg 11 cls_cnt 2 2006.173.17:32:15.89#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.17:32:15.95#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.17:32:15.95#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.17:32:15.95#ibcon#enter wrdev, iclass 6, count 2 2006.173.17:32:15.95#ibcon#first serial, iclass 6, count 2 2006.173.17:32:15.95#ibcon#enter sib2, iclass 6, count 2 2006.173.17:32:15.95#ibcon#flushed, iclass 6, count 2 2006.173.17:32:15.95#ibcon#about to write, iclass 6, count 2 2006.173.17:32:15.95#ibcon#wrote, iclass 6, count 2 2006.173.17:32:15.95#ibcon#about to read 3, iclass 6, count 2 2006.173.17:32:15.97#ibcon#read 3, iclass 6, count 2 2006.173.17:32:15.97#ibcon#about to read 4, iclass 6, count 2 2006.173.17:32:15.97#ibcon#read 4, iclass 6, count 2 2006.173.17:32:15.97#ibcon#about to read 5, iclass 6, count 2 2006.173.17:32:15.97#ibcon#read 5, iclass 6, count 2 2006.173.17:32:15.97#ibcon#about to read 6, iclass 6, count 2 2006.173.17:32:15.97#ibcon#read 6, iclass 6, count 2 2006.173.17:32:15.97#ibcon#end of sib2, iclass 6, count 2 2006.173.17:32:15.97#ibcon#*mode == 0, iclass 6, count 2 2006.173.17:32:15.97#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.17:32:15.97#ibcon#[25=AT06-03\r\n] 2006.173.17:32:15.97#ibcon#*before write, iclass 6, count 2 2006.173.17:32:15.97#ibcon#enter sib2, iclass 6, count 2 2006.173.17:32:15.97#ibcon#flushed, iclass 6, count 2 2006.173.17:32:15.97#ibcon#about to write, iclass 6, count 2 2006.173.17:32:15.97#ibcon#wrote, iclass 6, count 2 2006.173.17:32:15.97#ibcon#about to read 3, iclass 6, count 2 2006.173.17:32:16.00#ibcon#read 3, iclass 6, count 2 2006.173.17:32:16.00#ibcon#about to read 4, iclass 6, count 2 2006.173.17:32:16.00#ibcon#read 4, iclass 6, count 2 2006.173.17:32:16.00#ibcon#about to read 5, iclass 6, count 2 2006.173.17:32:16.00#ibcon#read 5, iclass 6, count 2 2006.173.17:32:16.00#ibcon#about to read 6, iclass 6, count 2 2006.173.17:32:16.00#ibcon#read 6, iclass 6, count 2 2006.173.17:32:16.00#ibcon#end of sib2, iclass 6, count 2 2006.173.17:32:16.00#ibcon#*after write, iclass 6, count 2 2006.173.17:32:16.00#ibcon#*before return 0, iclass 6, count 2 2006.173.17:32:16.00#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.17:32:16.00#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.17:32:16.00#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.17:32:16.00#ibcon#ireg 7 cls_cnt 0 2006.173.17:32:16.00#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.17:32:16.12#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.17:32:16.12#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.17:32:16.12#ibcon#enter wrdev, iclass 6, count 0 2006.173.17:32:16.12#ibcon#first serial, iclass 6, count 0 2006.173.17:32:16.12#ibcon#enter sib2, iclass 6, count 0 2006.173.17:32:16.12#ibcon#flushed, iclass 6, count 0 2006.173.17:32:16.12#ibcon#about to write, iclass 6, count 0 2006.173.17:32:16.12#ibcon#wrote, iclass 6, count 0 2006.173.17:32:16.12#ibcon#about to read 3, iclass 6, count 0 2006.173.17:32:16.14#ibcon#read 3, iclass 6, count 0 2006.173.17:32:16.14#ibcon#about to read 4, iclass 6, count 0 2006.173.17:32:16.14#ibcon#read 4, iclass 6, count 0 2006.173.17:32:16.14#ibcon#about to read 5, iclass 6, count 0 2006.173.17:32:16.14#ibcon#read 5, iclass 6, count 0 2006.173.17:32:16.14#ibcon#about to read 6, iclass 6, count 0 2006.173.17:32:16.14#ibcon#read 6, iclass 6, count 0 2006.173.17:32:16.14#ibcon#end of sib2, iclass 6, count 0 2006.173.17:32:16.14#ibcon#*mode == 0, iclass 6, count 0 2006.173.17:32:16.14#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.17:32:16.14#ibcon#[25=USB\r\n] 2006.173.17:32:16.14#ibcon#*before write, iclass 6, count 0 2006.173.17:32:16.14#ibcon#enter sib2, iclass 6, count 0 2006.173.17:32:16.14#ibcon#flushed, iclass 6, count 0 2006.173.17:32:16.14#ibcon#about to write, iclass 6, count 0 2006.173.17:32:16.14#ibcon#wrote, iclass 6, count 0 2006.173.17:32:16.14#ibcon#about to read 3, iclass 6, count 0 2006.173.17:32:16.17#ibcon#read 3, iclass 6, count 0 2006.173.17:32:16.17#ibcon#about to read 4, iclass 6, count 0 2006.173.17:32:16.17#ibcon#read 4, iclass 6, count 0 2006.173.17:32:16.17#ibcon#about to read 5, iclass 6, count 0 2006.173.17:32:16.17#ibcon#read 5, iclass 6, count 0 2006.173.17:32:16.17#ibcon#about to read 6, iclass 6, count 0 2006.173.17:32:16.17#ibcon#read 6, iclass 6, count 0 2006.173.17:32:16.17#ibcon#end of sib2, iclass 6, count 0 2006.173.17:32:16.17#ibcon#*after write, iclass 6, count 0 2006.173.17:32:16.17#ibcon#*before return 0, iclass 6, count 0 2006.173.17:32:16.17#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.17:32:16.17#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.17:32:16.17#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.17:32:16.17#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.17:32:16.17$vck44/valo=7,864.99 2006.173.17:32:16.17#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.17:32:16.17#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.17:32:16.17#ibcon#ireg 17 cls_cnt 0 2006.173.17:32:16.17#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.17:32:16.17#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.17:32:16.17#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.17:32:16.17#ibcon#enter wrdev, iclass 10, count 0 2006.173.17:32:16.17#ibcon#first serial, iclass 10, count 0 2006.173.17:32:16.17#ibcon#enter sib2, iclass 10, count 0 2006.173.17:32:16.17#ibcon#flushed, iclass 10, count 0 2006.173.17:32:16.17#ibcon#about to write, iclass 10, count 0 2006.173.17:32:16.17#ibcon#wrote, iclass 10, count 0 2006.173.17:32:16.17#ibcon#about to read 3, iclass 10, count 0 2006.173.17:32:16.19#ibcon#read 3, iclass 10, count 0 2006.173.17:32:16.19#ibcon#about to read 4, iclass 10, count 0 2006.173.17:32:16.19#ibcon#read 4, iclass 10, count 0 2006.173.17:32:16.19#ibcon#about to read 5, iclass 10, count 0 2006.173.17:32:16.19#ibcon#read 5, iclass 10, count 0 2006.173.17:32:16.19#ibcon#about to read 6, iclass 10, count 0 2006.173.17:32:16.19#ibcon#read 6, iclass 10, count 0 2006.173.17:32:16.19#ibcon#end of sib2, iclass 10, count 0 2006.173.17:32:16.19#ibcon#*mode == 0, iclass 10, count 0 2006.173.17:32:16.19#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.17:32:16.19#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.17:32:16.19#ibcon#*before write, iclass 10, count 0 2006.173.17:32:16.19#ibcon#enter sib2, iclass 10, count 0 2006.173.17:32:16.19#ibcon#flushed, iclass 10, count 0 2006.173.17:32:16.19#ibcon#about to write, iclass 10, count 0 2006.173.17:32:16.19#ibcon#wrote, iclass 10, count 0 2006.173.17:32:16.19#ibcon#about to read 3, iclass 10, count 0 2006.173.17:32:16.23#ibcon#read 3, iclass 10, count 0 2006.173.17:32:16.23#ibcon#about to read 4, iclass 10, count 0 2006.173.17:32:16.23#ibcon#read 4, iclass 10, count 0 2006.173.17:32:16.23#ibcon#about to read 5, iclass 10, count 0 2006.173.17:32:16.23#ibcon#read 5, iclass 10, count 0 2006.173.17:32:16.23#ibcon#about to read 6, iclass 10, count 0 2006.173.17:32:16.23#ibcon#read 6, iclass 10, count 0 2006.173.17:32:16.23#ibcon#end of sib2, iclass 10, count 0 2006.173.17:32:16.23#ibcon#*after write, iclass 10, count 0 2006.173.17:32:16.23#ibcon#*before return 0, iclass 10, count 0 2006.173.17:32:16.23#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.17:32:16.23#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.17:32:16.23#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.17:32:16.23#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.17:32:16.23$vck44/va=7,4 2006.173.17:32:16.23#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.17:32:16.23#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.17:32:16.23#ibcon#ireg 11 cls_cnt 2 2006.173.17:32:16.23#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.17:32:16.29#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.17:32:16.29#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.17:32:16.29#ibcon#enter wrdev, iclass 12, count 2 2006.173.17:32:16.29#ibcon#first serial, iclass 12, count 2 2006.173.17:32:16.29#ibcon#enter sib2, iclass 12, count 2 2006.173.17:32:16.29#ibcon#flushed, iclass 12, count 2 2006.173.17:32:16.29#ibcon#about to write, iclass 12, count 2 2006.173.17:32:16.29#ibcon#wrote, iclass 12, count 2 2006.173.17:32:16.29#ibcon#about to read 3, iclass 12, count 2 2006.173.17:32:16.31#ibcon#read 3, iclass 12, count 2 2006.173.17:32:16.31#ibcon#about to read 4, iclass 12, count 2 2006.173.17:32:16.31#ibcon#read 4, iclass 12, count 2 2006.173.17:32:16.31#ibcon#about to read 5, iclass 12, count 2 2006.173.17:32:16.31#ibcon#read 5, iclass 12, count 2 2006.173.17:32:16.31#ibcon#about to read 6, iclass 12, count 2 2006.173.17:32:16.31#ibcon#read 6, iclass 12, count 2 2006.173.17:32:16.31#ibcon#end of sib2, iclass 12, count 2 2006.173.17:32:16.31#ibcon#*mode == 0, iclass 12, count 2 2006.173.17:32:16.31#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.17:32:16.31#ibcon#[25=AT07-04\r\n] 2006.173.17:32:16.31#ibcon#*before write, iclass 12, count 2 2006.173.17:32:16.31#ibcon#enter sib2, iclass 12, count 2 2006.173.17:32:16.31#ibcon#flushed, iclass 12, count 2 2006.173.17:32:16.31#ibcon#about to write, iclass 12, count 2 2006.173.17:32:16.31#ibcon#wrote, iclass 12, count 2 2006.173.17:32:16.31#ibcon#about to read 3, iclass 12, count 2 2006.173.17:32:16.34#ibcon#read 3, iclass 12, count 2 2006.173.17:32:16.34#ibcon#about to read 4, iclass 12, count 2 2006.173.17:32:16.34#ibcon#read 4, iclass 12, count 2 2006.173.17:32:16.34#ibcon#about to read 5, iclass 12, count 2 2006.173.17:32:16.34#ibcon#read 5, iclass 12, count 2 2006.173.17:32:16.34#ibcon#about to read 6, iclass 12, count 2 2006.173.17:32:16.34#ibcon#read 6, iclass 12, count 2 2006.173.17:32:16.34#ibcon#end of sib2, iclass 12, count 2 2006.173.17:32:16.34#ibcon#*after write, iclass 12, count 2 2006.173.17:32:16.34#ibcon#*before return 0, iclass 12, count 2 2006.173.17:32:16.34#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.17:32:16.34#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.17:32:16.34#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.17:32:16.34#ibcon#ireg 7 cls_cnt 0 2006.173.17:32:16.34#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.17:32:16.46#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.17:32:16.46#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.17:32:16.46#ibcon#enter wrdev, iclass 12, count 0 2006.173.17:32:16.46#ibcon#first serial, iclass 12, count 0 2006.173.17:32:16.46#ibcon#enter sib2, iclass 12, count 0 2006.173.17:32:16.46#ibcon#flushed, iclass 12, count 0 2006.173.17:32:16.46#ibcon#about to write, iclass 12, count 0 2006.173.17:32:16.46#ibcon#wrote, iclass 12, count 0 2006.173.17:32:16.46#ibcon#about to read 3, iclass 12, count 0 2006.173.17:32:16.48#ibcon#read 3, iclass 12, count 0 2006.173.17:32:16.48#ibcon#about to read 4, iclass 12, count 0 2006.173.17:32:16.48#ibcon#read 4, iclass 12, count 0 2006.173.17:32:16.48#ibcon#about to read 5, iclass 12, count 0 2006.173.17:32:16.48#ibcon#read 5, iclass 12, count 0 2006.173.17:32:16.48#ibcon#about to read 6, iclass 12, count 0 2006.173.17:32:16.48#ibcon#read 6, iclass 12, count 0 2006.173.17:32:16.48#ibcon#end of sib2, iclass 12, count 0 2006.173.17:32:16.48#ibcon#*mode == 0, iclass 12, count 0 2006.173.17:32:16.48#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.17:32:16.48#ibcon#[25=USB\r\n] 2006.173.17:32:16.48#ibcon#*before write, iclass 12, count 0 2006.173.17:32:16.48#ibcon#enter sib2, iclass 12, count 0 2006.173.17:32:16.48#ibcon#flushed, iclass 12, count 0 2006.173.17:32:16.48#ibcon#about to write, iclass 12, count 0 2006.173.17:32:16.48#ibcon#wrote, iclass 12, count 0 2006.173.17:32:16.48#ibcon#about to read 3, iclass 12, count 0 2006.173.17:32:16.51#ibcon#read 3, iclass 12, count 0 2006.173.17:32:16.51#ibcon#about to read 4, iclass 12, count 0 2006.173.17:32:16.51#ibcon#read 4, iclass 12, count 0 2006.173.17:32:16.51#ibcon#about to read 5, iclass 12, count 0 2006.173.17:32:16.51#ibcon#read 5, iclass 12, count 0 2006.173.17:32:16.51#ibcon#about to read 6, iclass 12, count 0 2006.173.17:32:16.51#ibcon#read 6, iclass 12, count 0 2006.173.17:32:16.51#ibcon#end of sib2, iclass 12, count 0 2006.173.17:32:16.51#ibcon#*after write, iclass 12, count 0 2006.173.17:32:16.51#ibcon#*before return 0, iclass 12, count 0 2006.173.17:32:16.51#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.17:32:16.51#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.17:32:16.51#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.17:32:16.51#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.17:32:16.51$vck44/valo=8,884.99 2006.173.17:32:16.51#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.17:32:16.51#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.17:32:16.51#ibcon#ireg 17 cls_cnt 0 2006.173.17:32:16.51#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.17:32:16.51#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.17:32:16.51#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.17:32:16.51#ibcon#enter wrdev, iclass 14, count 0 2006.173.17:32:16.51#ibcon#first serial, iclass 14, count 0 2006.173.17:32:16.51#ibcon#enter sib2, iclass 14, count 0 2006.173.17:32:16.51#ibcon#flushed, iclass 14, count 0 2006.173.17:32:16.51#ibcon#about to write, iclass 14, count 0 2006.173.17:32:16.51#ibcon#wrote, iclass 14, count 0 2006.173.17:32:16.51#ibcon#about to read 3, iclass 14, count 0 2006.173.17:32:16.53#ibcon#read 3, iclass 14, count 0 2006.173.17:32:16.53#ibcon#about to read 4, iclass 14, count 0 2006.173.17:32:16.53#ibcon#read 4, iclass 14, count 0 2006.173.17:32:16.53#ibcon#about to read 5, iclass 14, count 0 2006.173.17:32:16.53#ibcon#read 5, iclass 14, count 0 2006.173.17:32:16.53#ibcon#about to read 6, iclass 14, count 0 2006.173.17:32:16.53#ibcon#read 6, iclass 14, count 0 2006.173.17:32:16.53#ibcon#end of sib2, iclass 14, count 0 2006.173.17:32:16.53#ibcon#*mode == 0, iclass 14, count 0 2006.173.17:32:16.53#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.17:32:16.53#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.17:32:16.53#ibcon#*before write, iclass 14, count 0 2006.173.17:32:16.53#ibcon#enter sib2, iclass 14, count 0 2006.173.17:32:16.53#ibcon#flushed, iclass 14, count 0 2006.173.17:32:16.53#ibcon#about to write, iclass 14, count 0 2006.173.17:32:16.53#ibcon#wrote, iclass 14, count 0 2006.173.17:32:16.53#ibcon#about to read 3, iclass 14, count 0 2006.173.17:32:16.57#ibcon#read 3, iclass 14, count 0 2006.173.17:32:16.57#ibcon#about to read 4, iclass 14, count 0 2006.173.17:32:16.57#ibcon#read 4, iclass 14, count 0 2006.173.17:32:16.57#ibcon#about to read 5, iclass 14, count 0 2006.173.17:32:16.57#ibcon#read 5, iclass 14, count 0 2006.173.17:32:16.57#ibcon#about to read 6, iclass 14, count 0 2006.173.17:32:16.57#ibcon#read 6, iclass 14, count 0 2006.173.17:32:16.57#ibcon#end of sib2, iclass 14, count 0 2006.173.17:32:16.57#ibcon#*after write, iclass 14, count 0 2006.173.17:32:16.57#ibcon#*before return 0, iclass 14, count 0 2006.173.17:32:16.57#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.17:32:16.57#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.17:32:16.57#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.17:32:16.57#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.17:32:16.57$vck44/va=8,4 2006.173.17:32:16.57#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.17:32:16.57#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.17:32:16.57#ibcon#ireg 11 cls_cnt 2 2006.173.17:32:16.57#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.17:32:16.63#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.17:32:16.63#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.17:32:16.63#ibcon#enter wrdev, iclass 16, count 2 2006.173.17:32:16.63#ibcon#first serial, iclass 16, count 2 2006.173.17:32:16.63#ibcon#enter sib2, iclass 16, count 2 2006.173.17:32:16.63#ibcon#flushed, iclass 16, count 2 2006.173.17:32:16.63#ibcon#about to write, iclass 16, count 2 2006.173.17:32:16.63#ibcon#wrote, iclass 16, count 2 2006.173.17:32:16.63#ibcon#about to read 3, iclass 16, count 2 2006.173.17:32:16.65#ibcon#read 3, iclass 16, count 2 2006.173.17:32:16.65#ibcon#about to read 4, iclass 16, count 2 2006.173.17:32:16.65#ibcon#read 4, iclass 16, count 2 2006.173.17:32:16.65#ibcon#about to read 5, iclass 16, count 2 2006.173.17:32:16.65#ibcon#read 5, iclass 16, count 2 2006.173.17:32:16.65#ibcon#about to read 6, iclass 16, count 2 2006.173.17:32:16.65#ibcon#read 6, iclass 16, count 2 2006.173.17:32:16.65#ibcon#end of sib2, iclass 16, count 2 2006.173.17:32:16.65#ibcon#*mode == 0, iclass 16, count 2 2006.173.17:32:16.65#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.17:32:16.65#ibcon#[25=AT08-04\r\n] 2006.173.17:32:16.65#ibcon#*before write, iclass 16, count 2 2006.173.17:32:16.65#ibcon#enter sib2, iclass 16, count 2 2006.173.17:32:16.65#ibcon#flushed, iclass 16, count 2 2006.173.17:32:16.65#ibcon#about to write, iclass 16, count 2 2006.173.17:32:16.65#ibcon#wrote, iclass 16, count 2 2006.173.17:32:16.65#ibcon#about to read 3, iclass 16, count 2 2006.173.17:32:16.68#ibcon#read 3, iclass 16, count 2 2006.173.17:32:16.68#ibcon#about to read 4, iclass 16, count 2 2006.173.17:32:16.68#ibcon#read 4, iclass 16, count 2 2006.173.17:32:16.68#ibcon#about to read 5, iclass 16, count 2 2006.173.17:32:16.68#ibcon#read 5, iclass 16, count 2 2006.173.17:32:16.68#ibcon#about to read 6, iclass 16, count 2 2006.173.17:32:16.68#ibcon#read 6, iclass 16, count 2 2006.173.17:32:16.68#ibcon#end of sib2, iclass 16, count 2 2006.173.17:32:16.68#ibcon#*after write, iclass 16, count 2 2006.173.17:32:16.68#ibcon#*before return 0, iclass 16, count 2 2006.173.17:32:16.68#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.17:32:16.68#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.17:32:16.68#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.17:32:16.68#ibcon#ireg 7 cls_cnt 0 2006.173.17:32:16.68#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.17:32:16.80#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.17:32:16.80#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.17:32:16.80#ibcon#enter wrdev, iclass 16, count 0 2006.173.17:32:16.80#ibcon#first serial, iclass 16, count 0 2006.173.17:32:16.80#ibcon#enter sib2, iclass 16, count 0 2006.173.17:32:16.80#ibcon#flushed, iclass 16, count 0 2006.173.17:32:16.80#ibcon#about to write, iclass 16, count 0 2006.173.17:32:16.80#ibcon#wrote, iclass 16, count 0 2006.173.17:32:16.80#ibcon#about to read 3, iclass 16, count 0 2006.173.17:32:16.82#ibcon#read 3, iclass 16, count 0 2006.173.17:32:16.82#ibcon#about to read 4, iclass 16, count 0 2006.173.17:32:16.82#ibcon#read 4, iclass 16, count 0 2006.173.17:32:16.82#ibcon#about to read 5, iclass 16, count 0 2006.173.17:32:16.82#ibcon#read 5, iclass 16, count 0 2006.173.17:32:16.82#ibcon#about to read 6, iclass 16, count 0 2006.173.17:32:16.82#ibcon#read 6, iclass 16, count 0 2006.173.17:32:16.82#ibcon#end of sib2, iclass 16, count 0 2006.173.17:32:16.82#ibcon#*mode == 0, iclass 16, count 0 2006.173.17:32:16.82#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.17:32:16.82#ibcon#[25=USB\r\n] 2006.173.17:32:16.82#ibcon#*before write, iclass 16, count 0 2006.173.17:32:16.82#ibcon#enter sib2, iclass 16, count 0 2006.173.17:32:16.82#ibcon#flushed, iclass 16, count 0 2006.173.17:32:16.82#ibcon#about to write, iclass 16, count 0 2006.173.17:32:16.82#ibcon#wrote, iclass 16, count 0 2006.173.17:32:16.82#ibcon#about to read 3, iclass 16, count 0 2006.173.17:32:16.85#ibcon#read 3, iclass 16, count 0 2006.173.17:32:16.85#ibcon#about to read 4, iclass 16, count 0 2006.173.17:32:16.85#ibcon#read 4, iclass 16, count 0 2006.173.17:32:16.85#ibcon#about to read 5, iclass 16, count 0 2006.173.17:32:16.85#ibcon#read 5, iclass 16, count 0 2006.173.17:32:16.85#ibcon#about to read 6, iclass 16, count 0 2006.173.17:32:16.85#ibcon#read 6, iclass 16, count 0 2006.173.17:32:16.85#ibcon#end of sib2, iclass 16, count 0 2006.173.17:32:16.85#ibcon#*after write, iclass 16, count 0 2006.173.17:32:16.85#ibcon#*before return 0, iclass 16, count 0 2006.173.17:32:16.85#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.17:32:16.85#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.17:32:16.85#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.17:32:16.85#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.17:32:16.85$vck44/vblo=1,629.99 2006.173.17:32:16.85#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.17:32:16.85#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.17:32:16.85#ibcon#ireg 17 cls_cnt 0 2006.173.17:32:16.85#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.17:32:16.85#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.17:32:16.85#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.17:32:16.85#ibcon#enter wrdev, iclass 18, count 0 2006.173.17:32:16.85#ibcon#first serial, iclass 18, count 0 2006.173.17:32:16.85#ibcon#enter sib2, iclass 18, count 0 2006.173.17:32:16.85#ibcon#flushed, iclass 18, count 0 2006.173.17:32:16.85#ibcon#about to write, iclass 18, count 0 2006.173.17:32:16.85#ibcon#wrote, iclass 18, count 0 2006.173.17:32:16.85#ibcon#about to read 3, iclass 18, count 0 2006.173.17:32:16.87#ibcon#read 3, iclass 18, count 0 2006.173.17:32:16.87#ibcon#about to read 4, iclass 18, count 0 2006.173.17:32:16.87#ibcon#read 4, iclass 18, count 0 2006.173.17:32:16.87#ibcon#about to read 5, iclass 18, count 0 2006.173.17:32:16.87#ibcon#read 5, iclass 18, count 0 2006.173.17:32:16.87#ibcon#about to read 6, iclass 18, count 0 2006.173.17:32:16.87#ibcon#read 6, iclass 18, count 0 2006.173.17:32:16.87#ibcon#end of sib2, iclass 18, count 0 2006.173.17:32:16.87#ibcon#*mode == 0, iclass 18, count 0 2006.173.17:32:16.87#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.17:32:16.87#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.17:32:16.87#ibcon#*before write, iclass 18, count 0 2006.173.17:32:16.87#ibcon#enter sib2, iclass 18, count 0 2006.173.17:32:16.87#ibcon#flushed, iclass 18, count 0 2006.173.17:32:16.87#ibcon#about to write, iclass 18, count 0 2006.173.17:32:16.87#ibcon#wrote, iclass 18, count 0 2006.173.17:32:16.87#ibcon#about to read 3, iclass 18, count 0 2006.173.17:32:16.91#ibcon#read 3, iclass 18, count 0 2006.173.17:32:16.91#ibcon#about to read 4, iclass 18, count 0 2006.173.17:32:16.91#ibcon#read 4, iclass 18, count 0 2006.173.17:32:16.91#ibcon#about to read 5, iclass 18, count 0 2006.173.17:32:16.91#ibcon#read 5, iclass 18, count 0 2006.173.17:32:16.91#ibcon#about to read 6, iclass 18, count 0 2006.173.17:32:16.91#ibcon#read 6, iclass 18, count 0 2006.173.17:32:16.91#ibcon#end of sib2, iclass 18, count 0 2006.173.17:32:16.91#ibcon#*after write, iclass 18, count 0 2006.173.17:32:16.91#ibcon#*before return 0, iclass 18, count 0 2006.173.17:32:16.91#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.17:32:16.91#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.17:32:16.91#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.17:32:16.91#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.17:32:16.91$vck44/vb=1,4 2006.173.17:32:16.91#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.17:32:16.91#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.17:32:16.91#ibcon#ireg 11 cls_cnt 2 2006.173.17:32:16.91#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.17:32:16.91#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.17:32:16.91#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.17:32:16.91#ibcon#enter wrdev, iclass 20, count 2 2006.173.17:32:16.91#ibcon#first serial, iclass 20, count 2 2006.173.17:32:16.91#ibcon#enter sib2, iclass 20, count 2 2006.173.17:32:16.91#ibcon#flushed, iclass 20, count 2 2006.173.17:32:16.91#ibcon#about to write, iclass 20, count 2 2006.173.17:32:16.91#ibcon#wrote, iclass 20, count 2 2006.173.17:32:16.91#ibcon#about to read 3, iclass 20, count 2 2006.173.17:32:16.93#ibcon#read 3, iclass 20, count 2 2006.173.17:32:16.93#ibcon#about to read 4, iclass 20, count 2 2006.173.17:32:16.93#ibcon#read 4, iclass 20, count 2 2006.173.17:32:16.93#ibcon#about to read 5, iclass 20, count 2 2006.173.17:32:16.93#ibcon#read 5, iclass 20, count 2 2006.173.17:32:16.93#ibcon#about to read 6, iclass 20, count 2 2006.173.17:32:16.93#ibcon#read 6, iclass 20, count 2 2006.173.17:32:16.93#ibcon#end of sib2, iclass 20, count 2 2006.173.17:32:16.93#ibcon#*mode == 0, iclass 20, count 2 2006.173.17:32:16.93#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.17:32:16.93#ibcon#[27=AT01-04\r\n] 2006.173.17:32:16.93#ibcon#*before write, iclass 20, count 2 2006.173.17:32:16.93#ibcon#enter sib2, iclass 20, count 2 2006.173.17:32:16.93#ibcon#flushed, iclass 20, count 2 2006.173.17:32:16.93#ibcon#about to write, iclass 20, count 2 2006.173.17:32:16.93#ibcon#wrote, iclass 20, count 2 2006.173.17:32:16.93#ibcon#about to read 3, iclass 20, count 2 2006.173.17:32:16.96#ibcon#read 3, iclass 20, count 2 2006.173.17:32:16.96#ibcon#about to read 4, iclass 20, count 2 2006.173.17:32:16.96#ibcon#read 4, iclass 20, count 2 2006.173.17:32:16.96#ibcon#about to read 5, iclass 20, count 2 2006.173.17:32:16.96#ibcon#read 5, iclass 20, count 2 2006.173.17:32:16.96#ibcon#about to read 6, iclass 20, count 2 2006.173.17:32:16.96#ibcon#read 6, iclass 20, count 2 2006.173.17:32:16.96#ibcon#end of sib2, iclass 20, count 2 2006.173.17:32:16.96#ibcon#*after write, iclass 20, count 2 2006.173.17:32:16.96#ibcon#*before return 0, iclass 20, count 2 2006.173.17:32:16.96#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.17:32:16.96#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.17:32:16.96#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.17:32:16.96#ibcon#ireg 7 cls_cnt 0 2006.173.17:32:16.96#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.17:32:17.08#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.17:32:17.08#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.17:32:17.08#ibcon#enter wrdev, iclass 20, count 0 2006.173.17:32:17.08#ibcon#first serial, iclass 20, count 0 2006.173.17:32:17.08#ibcon#enter sib2, iclass 20, count 0 2006.173.17:32:17.08#ibcon#flushed, iclass 20, count 0 2006.173.17:32:17.08#ibcon#about to write, iclass 20, count 0 2006.173.17:32:17.08#ibcon#wrote, iclass 20, count 0 2006.173.17:32:17.08#ibcon#about to read 3, iclass 20, count 0 2006.173.17:32:17.10#ibcon#read 3, iclass 20, count 0 2006.173.17:32:17.10#ibcon#about to read 4, iclass 20, count 0 2006.173.17:32:17.10#ibcon#read 4, iclass 20, count 0 2006.173.17:32:17.10#ibcon#about to read 5, iclass 20, count 0 2006.173.17:32:17.10#ibcon#read 5, iclass 20, count 0 2006.173.17:32:17.10#ibcon#about to read 6, iclass 20, count 0 2006.173.17:32:17.10#ibcon#read 6, iclass 20, count 0 2006.173.17:32:17.10#ibcon#end of sib2, iclass 20, count 0 2006.173.17:32:17.10#ibcon#*mode == 0, iclass 20, count 0 2006.173.17:32:17.10#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.17:32:17.10#ibcon#[27=USB\r\n] 2006.173.17:32:17.10#ibcon#*before write, iclass 20, count 0 2006.173.17:32:17.10#ibcon#enter sib2, iclass 20, count 0 2006.173.17:32:17.10#ibcon#flushed, iclass 20, count 0 2006.173.17:32:17.10#ibcon#about to write, iclass 20, count 0 2006.173.17:32:17.10#ibcon#wrote, iclass 20, count 0 2006.173.17:32:17.10#ibcon#about to read 3, iclass 20, count 0 2006.173.17:32:17.13#ibcon#read 3, iclass 20, count 0 2006.173.17:32:17.13#ibcon#about to read 4, iclass 20, count 0 2006.173.17:32:17.13#ibcon#read 4, iclass 20, count 0 2006.173.17:32:17.13#ibcon#about to read 5, iclass 20, count 0 2006.173.17:32:17.13#ibcon#read 5, iclass 20, count 0 2006.173.17:32:17.13#ibcon#about to read 6, iclass 20, count 0 2006.173.17:32:17.13#ibcon#read 6, iclass 20, count 0 2006.173.17:32:17.13#ibcon#end of sib2, iclass 20, count 0 2006.173.17:32:17.13#ibcon#*after write, iclass 20, count 0 2006.173.17:32:17.13#ibcon#*before return 0, iclass 20, count 0 2006.173.17:32:17.13#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.17:32:17.13#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.17:32:17.13#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.17:32:17.13#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.17:32:17.13$vck44/vblo=2,634.99 2006.173.17:32:17.13#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.17:32:17.13#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.17:32:17.13#ibcon#ireg 17 cls_cnt 0 2006.173.17:32:17.13#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.17:32:17.13#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.17:32:17.13#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.17:32:17.13#ibcon#enter wrdev, iclass 22, count 0 2006.173.17:32:17.13#ibcon#first serial, iclass 22, count 0 2006.173.17:32:17.13#ibcon#enter sib2, iclass 22, count 0 2006.173.17:32:17.13#ibcon#flushed, iclass 22, count 0 2006.173.17:32:17.13#ibcon#about to write, iclass 22, count 0 2006.173.17:32:17.13#ibcon#wrote, iclass 22, count 0 2006.173.17:32:17.13#ibcon#about to read 3, iclass 22, count 0 2006.173.17:32:17.15#ibcon#read 3, iclass 22, count 0 2006.173.17:32:17.15#ibcon#about to read 4, iclass 22, count 0 2006.173.17:32:17.15#ibcon#read 4, iclass 22, count 0 2006.173.17:32:17.15#ibcon#about to read 5, iclass 22, count 0 2006.173.17:32:17.15#ibcon#read 5, iclass 22, count 0 2006.173.17:32:17.15#ibcon#about to read 6, iclass 22, count 0 2006.173.17:32:17.15#ibcon#read 6, iclass 22, count 0 2006.173.17:32:17.15#ibcon#end of sib2, iclass 22, count 0 2006.173.17:32:17.15#ibcon#*mode == 0, iclass 22, count 0 2006.173.17:32:17.15#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.17:32:17.15#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.17:32:17.15#ibcon#*before write, iclass 22, count 0 2006.173.17:32:17.15#ibcon#enter sib2, iclass 22, count 0 2006.173.17:32:17.15#ibcon#flushed, iclass 22, count 0 2006.173.17:32:17.15#ibcon#about to write, iclass 22, count 0 2006.173.17:32:17.15#ibcon#wrote, iclass 22, count 0 2006.173.17:32:17.15#ibcon#about to read 3, iclass 22, count 0 2006.173.17:32:17.19#ibcon#read 3, iclass 22, count 0 2006.173.17:32:17.19#ibcon#about to read 4, iclass 22, count 0 2006.173.17:32:17.19#ibcon#read 4, iclass 22, count 0 2006.173.17:32:17.19#ibcon#about to read 5, iclass 22, count 0 2006.173.17:32:17.19#ibcon#read 5, iclass 22, count 0 2006.173.17:32:17.19#ibcon#about to read 6, iclass 22, count 0 2006.173.17:32:17.19#ibcon#read 6, iclass 22, count 0 2006.173.17:32:17.19#ibcon#end of sib2, iclass 22, count 0 2006.173.17:32:17.19#ibcon#*after write, iclass 22, count 0 2006.173.17:32:17.19#ibcon#*before return 0, iclass 22, count 0 2006.173.17:32:17.19#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.17:32:17.19#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.17:32:17.19#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.17:32:17.19#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.17:32:17.19$vck44/vb=2,4 2006.173.17:32:17.19#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.17:32:17.19#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.17:32:17.19#ibcon#ireg 11 cls_cnt 2 2006.173.17:32:17.19#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.17:32:17.25#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.17:32:17.25#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.17:32:17.25#ibcon#enter wrdev, iclass 24, count 2 2006.173.17:32:17.25#ibcon#first serial, iclass 24, count 2 2006.173.17:32:17.25#ibcon#enter sib2, iclass 24, count 2 2006.173.17:32:17.25#ibcon#flushed, iclass 24, count 2 2006.173.17:32:17.25#ibcon#about to write, iclass 24, count 2 2006.173.17:32:17.25#ibcon#wrote, iclass 24, count 2 2006.173.17:32:17.25#ibcon#about to read 3, iclass 24, count 2 2006.173.17:32:17.27#ibcon#read 3, iclass 24, count 2 2006.173.17:32:17.27#ibcon#about to read 4, iclass 24, count 2 2006.173.17:32:17.27#ibcon#read 4, iclass 24, count 2 2006.173.17:32:17.27#ibcon#about to read 5, iclass 24, count 2 2006.173.17:32:17.27#ibcon#read 5, iclass 24, count 2 2006.173.17:32:17.27#ibcon#about to read 6, iclass 24, count 2 2006.173.17:32:17.27#ibcon#read 6, iclass 24, count 2 2006.173.17:32:17.27#ibcon#end of sib2, iclass 24, count 2 2006.173.17:32:17.27#ibcon#*mode == 0, iclass 24, count 2 2006.173.17:32:17.27#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.17:32:17.27#ibcon#[27=AT02-04\r\n] 2006.173.17:32:17.27#ibcon#*before write, iclass 24, count 2 2006.173.17:32:17.27#ibcon#enter sib2, iclass 24, count 2 2006.173.17:32:17.27#ibcon#flushed, iclass 24, count 2 2006.173.17:32:17.27#ibcon#about to write, iclass 24, count 2 2006.173.17:32:17.27#ibcon#wrote, iclass 24, count 2 2006.173.17:32:17.27#ibcon#about to read 3, iclass 24, count 2 2006.173.17:32:17.30#ibcon#read 3, iclass 24, count 2 2006.173.17:32:17.30#ibcon#about to read 4, iclass 24, count 2 2006.173.17:32:17.30#ibcon#read 4, iclass 24, count 2 2006.173.17:32:17.30#ibcon#about to read 5, iclass 24, count 2 2006.173.17:32:17.30#ibcon#read 5, iclass 24, count 2 2006.173.17:32:17.30#ibcon#about to read 6, iclass 24, count 2 2006.173.17:32:17.30#ibcon#read 6, iclass 24, count 2 2006.173.17:32:17.30#ibcon#end of sib2, iclass 24, count 2 2006.173.17:32:17.30#ibcon#*after write, iclass 24, count 2 2006.173.17:32:17.30#ibcon#*before return 0, iclass 24, count 2 2006.173.17:32:17.30#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.17:32:17.30#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.17:32:17.30#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.17:32:17.30#ibcon#ireg 7 cls_cnt 0 2006.173.17:32:17.30#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.17:32:17.42#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.17:32:17.42#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.17:32:17.42#ibcon#enter wrdev, iclass 24, count 0 2006.173.17:32:17.42#ibcon#first serial, iclass 24, count 0 2006.173.17:32:17.42#ibcon#enter sib2, iclass 24, count 0 2006.173.17:32:17.42#ibcon#flushed, iclass 24, count 0 2006.173.17:32:17.42#ibcon#about to write, iclass 24, count 0 2006.173.17:32:17.42#ibcon#wrote, iclass 24, count 0 2006.173.17:32:17.42#ibcon#about to read 3, iclass 24, count 0 2006.173.17:32:17.44#ibcon#read 3, iclass 24, count 0 2006.173.17:32:17.44#ibcon#about to read 4, iclass 24, count 0 2006.173.17:32:17.44#ibcon#read 4, iclass 24, count 0 2006.173.17:32:17.44#ibcon#about to read 5, iclass 24, count 0 2006.173.17:32:17.44#ibcon#read 5, iclass 24, count 0 2006.173.17:32:17.44#ibcon#about to read 6, iclass 24, count 0 2006.173.17:32:17.44#ibcon#read 6, iclass 24, count 0 2006.173.17:32:17.44#ibcon#end of sib2, iclass 24, count 0 2006.173.17:32:17.44#ibcon#*mode == 0, iclass 24, count 0 2006.173.17:32:17.44#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.17:32:17.44#ibcon#[27=USB\r\n] 2006.173.17:32:17.44#ibcon#*before write, iclass 24, count 0 2006.173.17:32:17.44#ibcon#enter sib2, iclass 24, count 0 2006.173.17:32:17.44#ibcon#flushed, iclass 24, count 0 2006.173.17:32:17.44#ibcon#about to write, iclass 24, count 0 2006.173.17:32:17.44#ibcon#wrote, iclass 24, count 0 2006.173.17:32:17.44#ibcon#about to read 3, iclass 24, count 0 2006.173.17:32:17.47#ibcon#read 3, iclass 24, count 0 2006.173.17:32:17.47#ibcon#about to read 4, iclass 24, count 0 2006.173.17:32:17.47#ibcon#read 4, iclass 24, count 0 2006.173.17:32:17.47#ibcon#about to read 5, iclass 24, count 0 2006.173.17:32:17.47#ibcon#read 5, iclass 24, count 0 2006.173.17:32:17.47#ibcon#about to read 6, iclass 24, count 0 2006.173.17:32:17.47#ibcon#read 6, iclass 24, count 0 2006.173.17:32:17.47#ibcon#end of sib2, iclass 24, count 0 2006.173.17:32:17.47#ibcon#*after write, iclass 24, count 0 2006.173.17:32:17.47#ibcon#*before return 0, iclass 24, count 0 2006.173.17:32:17.47#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.17:32:17.47#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.17:32:17.47#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.17:32:17.47#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.17:32:17.47$vck44/vblo=3,649.99 2006.173.17:32:17.47#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.17:32:17.47#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.17:32:17.47#ibcon#ireg 17 cls_cnt 0 2006.173.17:32:17.47#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.17:32:17.47#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.17:32:17.47#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.17:32:17.47#ibcon#enter wrdev, iclass 26, count 0 2006.173.17:32:17.47#ibcon#first serial, iclass 26, count 0 2006.173.17:32:17.47#ibcon#enter sib2, iclass 26, count 0 2006.173.17:32:17.47#ibcon#flushed, iclass 26, count 0 2006.173.17:32:17.47#ibcon#about to write, iclass 26, count 0 2006.173.17:32:17.47#ibcon#wrote, iclass 26, count 0 2006.173.17:32:17.47#ibcon#about to read 3, iclass 26, count 0 2006.173.17:32:17.49#ibcon#read 3, iclass 26, count 0 2006.173.17:32:17.49#ibcon#about to read 4, iclass 26, count 0 2006.173.17:32:17.49#ibcon#read 4, iclass 26, count 0 2006.173.17:32:17.49#ibcon#about to read 5, iclass 26, count 0 2006.173.17:32:17.49#ibcon#read 5, iclass 26, count 0 2006.173.17:32:17.49#ibcon#about to read 6, iclass 26, count 0 2006.173.17:32:17.49#ibcon#read 6, iclass 26, count 0 2006.173.17:32:17.49#ibcon#end of sib2, iclass 26, count 0 2006.173.17:32:17.49#ibcon#*mode == 0, iclass 26, count 0 2006.173.17:32:17.49#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.17:32:17.49#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.17:32:17.49#ibcon#*before write, iclass 26, count 0 2006.173.17:32:17.49#ibcon#enter sib2, iclass 26, count 0 2006.173.17:32:17.49#ibcon#flushed, iclass 26, count 0 2006.173.17:32:17.49#ibcon#about to write, iclass 26, count 0 2006.173.17:32:17.49#ibcon#wrote, iclass 26, count 0 2006.173.17:32:17.49#ibcon#about to read 3, iclass 26, count 0 2006.173.17:32:17.53#ibcon#read 3, iclass 26, count 0 2006.173.17:32:17.53#ibcon#about to read 4, iclass 26, count 0 2006.173.17:32:17.53#ibcon#read 4, iclass 26, count 0 2006.173.17:32:17.53#ibcon#about to read 5, iclass 26, count 0 2006.173.17:32:17.53#ibcon#read 5, iclass 26, count 0 2006.173.17:32:17.53#ibcon#about to read 6, iclass 26, count 0 2006.173.17:32:17.53#ibcon#read 6, iclass 26, count 0 2006.173.17:32:17.53#ibcon#end of sib2, iclass 26, count 0 2006.173.17:32:17.53#ibcon#*after write, iclass 26, count 0 2006.173.17:32:17.53#ibcon#*before return 0, iclass 26, count 0 2006.173.17:32:17.53#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.17:32:17.53#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.17:32:17.53#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.17:32:17.53#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.17:32:17.53$vck44/vb=3,4 2006.173.17:32:17.53#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.17:32:17.53#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.17:32:17.53#ibcon#ireg 11 cls_cnt 2 2006.173.17:32:17.53#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.17:32:17.59#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.17:32:17.59#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.17:32:17.59#ibcon#enter wrdev, iclass 28, count 2 2006.173.17:32:17.59#ibcon#first serial, iclass 28, count 2 2006.173.17:32:17.59#ibcon#enter sib2, iclass 28, count 2 2006.173.17:32:17.59#ibcon#flushed, iclass 28, count 2 2006.173.17:32:17.59#ibcon#about to write, iclass 28, count 2 2006.173.17:32:17.59#ibcon#wrote, iclass 28, count 2 2006.173.17:32:17.59#ibcon#about to read 3, iclass 28, count 2 2006.173.17:32:17.61#ibcon#read 3, iclass 28, count 2 2006.173.17:32:17.61#ibcon#about to read 4, iclass 28, count 2 2006.173.17:32:17.61#ibcon#read 4, iclass 28, count 2 2006.173.17:32:17.61#ibcon#about to read 5, iclass 28, count 2 2006.173.17:32:17.61#ibcon#read 5, iclass 28, count 2 2006.173.17:32:17.61#ibcon#about to read 6, iclass 28, count 2 2006.173.17:32:17.61#ibcon#read 6, iclass 28, count 2 2006.173.17:32:17.61#ibcon#end of sib2, iclass 28, count 2 2006.173.17:32:17.61#ibcon#*mode == 0, iclass 28, count 2 2006.173.17:32:17.61#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.17:32:17.61#ibcon#[27=AT03-04\r\n] 2006.173.17:32:17.61#ibcon#*before write, iclass 28, count 2 2006.173.17:32:17.61#ibcon#enter sib2, iclass 28, count 2 2006.173.17:32:17.61#ibcon#flushed, iclass 28, count 2 2006.173.17:32:17.61#ibcon#about to write, iclass 28, count 2 2006.173.17:32:17.61#ibcon#wrote, iclass 28, count 2 2006.173.17:32:17.61#ibcon#about to read 3, iclass 28, count 2 2006.173.17:32:17.64#ibcon#read 3, iclass 28, count 2 2006.173.17:32:17.64#ibcon#about to read 4, iclass 28, count 2 2006.173.17:32:17.64#ibcon#read 4, iclass 28, count 2 2006.173.17:32:17.64#ibcon#about to read 5, iclass 28, count 2 2006.173.17:32:17.64#ibcon#read 5, iclass 28, count 2 2006.173.17:32:17.64#ibcon#about to read 6, iclass 28, count 2 2006.173.17:32:17.64#ibcon#read 6, iclass 28, count 2 2006.173.17:32:17.64#ibcon#end of sib2, iclass 28, count 2 2006.173.17:32:17.64#ibcon#*after write, iclass 28, count 2 2006.173.17:32:17.64#ibcon#*before return 0, iclass 28, count 2 2006.173.17:32:17.64#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.17:32:17.64#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.17:32:17.64#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.17:32:17.64#ibcon#ireg 7 cls_cnt 0 2006.173.17:32:17.64#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.17:32:17.76#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.17:32:17.76#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.17:32:17.76#ibcon#enter wrdev, iclass 28, count 0 2006.173.17:32:17.76#ibcon#first serial, iclass 28, count 0 2006.173.17:32:17.76#ibcon#enter sib2, iclass 28, count 0 2006.173.17:32:17.76#ibcon#flushed, iclass 28, count 0 2006.173.17:32:17.76#ibcon#about to write, iclass 28, count 0 2006.173.17:32:17.76#ibcon#wrote, iclass 28, count 0 2006.173.17:32:17.76#ibcon#about to read 3, iclass 28, count 0 2006.173.17:32:17.78#ibcon#read 3, iclass 28, count 0 2006.173.17:32:17.78#ibcon#about to read 4, iclass 28, count 0 2006.173.17:32:17.78#ibcon#read 4, iclass 28, count 0 2006.173.17:32:17.78#ibcon#about to read 5, iclass 28, count 0 2006.173.17:32:17.78#ibcon#read 5, iclass 28, count 0 2006.173.17:32:17.78#ibcon#about to read 6, iclass 28, count 0 2006.173.17:32:17.78#ibcon#read 6, iclass 28, count 0 2006.173.17:32:17.78#ibcon#end of sib2, iclass 28, count 0 2006.173.17:32:17.78#ibcon#*mode == 0, iclass 28, count 0 2006.173.17:32:17.78#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.17:32:17.78#ibcon#[27=USB\r\n] 2006.173.17:32:17.78#ibcon#*before write, iclass 28, count 0 2006.173.17:32:17.78#ibcon#enter sib2, iclass 28, count 0 2006.173.17:32:17.78#ibcon#flushed, iclass 28, count 0 2006.173.17:32:17.78#ibcon#about to write, iclass 28, count 0 2006.173.17:32:17.78#ibcon#wrote, iclass 28, count 0 2006.173.17:32:17.78#ibcon#about to read 3, iclass 28, count 0 2006.173.17:32:17.81#ibcon#read 3, iclass 28, count 0 2006.173.17:32:17.81#ibcon#about to read 4, iclass 28, count 0 2006.173.17:32:17.81#ibcon#read 4, iclass 28, count 0 2006.173.17:32:17.81#ibcon#about to read 5, iclass 28, count 0 2006.173.17:32:17.81#ibcon#read 5, iclass 28, count 0 2006.173.17:32:17.81#ibcon#about to read 6, iclass 28, count 0 2006.173.17:32:17.81#ibcon#read 6, iclass 28, count 0 2006.173.17:32:17.81#ibcon#end of sib2, iclass 28, count 0 2006.173.17:32:17.81#ibcon#*after write, iclass 28, count 0 2006.173.17:32:17.81#ibcon#*before return 0, iclass 28, count 0 2006.173.17:32:17.81#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.17:32:17.81#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.17:32:17.81#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.17:32:17.81#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.17:32:17.81$vck44/vblo=4,679.99 2006.173.17:32:17.81#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.17:32:17.81#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.17:32:17.81#ibcon#ireg 17 cls_cnt 0 2006.173.17:32:17.81#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.17:32:17.81#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.17:32:17.81#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.17:32:17.81#ibcon#enter wrdev, iclass 30, count 0 2006.173.17:32:17.81#ibcon#first serial, iclass 30, count 0 2006.173.17:32:17.81#ibcon#enter sib2, iclass 30, count 0 2006.173.17:32:17.81#ibcon#flushed, iclass 30, count 0 2006.173.17:32:17.81#ibcon#about to write, iclass 30, count 0 2006.173.17:32:17.81#ibcon#wrote, iclass 30, count 0 2006.173.17:32:17.81#ibcon#about to read 3, iclass 30, count 0 2006.173.17:32:17.83#ibcon#read 3, iclass 30, count 0 2006.173.17:32:17.83#ibcon#about to read 4, iclass 30, count 0 2006.173.17:32:17.83#ibcon#read 4, iclass 30, count 0 2006.173.17:32:17.83#ibcon#about to read 5, iclass 30, count 0 2006.173.17:32:17.83#ibcon#read 5, iclass 30, count 0 2006.173.17:32:17.83#ibcon#about to read 6, iclass 30, count 0 2006.173.17:32:17.83#ibcon#read 6, iclass 30, count 0 2006.173.17:32:17.83#ibcon#end of sib2, iclass 30, count 0 2006.173.17:32:17.83#ibcon#*mode == 0, iclass 30, count 0 2006.173.17:32:17.83#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.17:32:17.83#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.17:32:17.83#ibcon#*before write, iclass 30, count 0 2006.173.17:32:17.83#ibcon#enter sib2, iclass 30, count 0 2006.173.17:32:17.83#ibcon#flushed, iclass 30, count 0 2006.173.17:32:17.83#ibcon#about to write, iclass 30, count 0 2006.173.17:32:17.83#ibcon#wrote, iclass 30, count 0 2006.173.17:32:17.83#ibcon#about to read 3, iclass 30, count 0 2006.173.17:32:17.87#ibcon#read 3, iclass 30, count 0 2006.173.17:32:17.87#ibcon#about to read 4, iclass 30, count 0 2006.173.17:32:17.87#ibcon#read 4, iclass 30, count 0 2006.173.17:32:17.87#ibcon#about to read 5, iclass 30, count 0 2006.173.17:32:17.87#ibcon#read 5, iclass 30, count 0 2006.173.17:32:17.87#ibcon#about to read 6, iclass 30, count 0 2006.173.17:32:17.87#ibcon#read 6, iclass 30, count 0 2006.173.17:32:17.87#ibcon#end of sib2, iclass 30, count 0 2006.173.17:32:17.87#ibcon#*after write, iclass 30, count 0 2006.173.17:32:17.87#ibcon#*before return 0, iclass 30, count 0 2006.173.17:32:17.87#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.17:32:17.87#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.17:32:17.87#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.17:32:17.87#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.17:32:17.87$vck44/vb=4,4 2006.173.17:32:17.87#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.173.17:32:17.87#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.173.17:32:17.87#ibcon#ireg 11 cls_cnt 2 2006.173.17:32:17.87#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.17:32:17.93#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.17:32:17.93#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.17:32:17.93#ibcon#enter wrdev, iclass 32, count 2 2006.173.17:32:17.93#ibcon#first serial, iclass 32, count 2 2006.173.17:32:17.93#ibcon#enter sib2, iclass 32, count 2 2006.173.17:32:17.93#ibcon#flushed, iclass 32, count 2 2006.173.17:32:17.93#ibcon#about to write, iclass 32, count 2 2006.173.17:32:17.93#ibcon#wrote, iclass 32, count 2 2006.173.17:32:17.93#ibcon#about to read 3, iclass 32, count 2 2006.173.17:32:17.95#ibcon#read 3, iclass 32, count 2 2006.173.17:32:17.95#ibcon#about to read 4, iclass 32, count 2 2006.173.17:32:17.95#ibcon#read 4, iclass 32, count 2 2006.173.17:32:17.95#ibcon#about to read 5, iclass 32, count 2 2006.173.17:32:17.95#ibcon#read 5, iclass 32, count 2 2006.173.17:32:17.95#ibcon#about to read 6, iclass 32, count 2 2006.173.17:32:17.95#ibcon#read 6, iclass 32, count 2 2006.173.17:32:17.95#ibcon#end of sib2, iclass 32, count 2 2006.173.17:32:17.95#ibcon#*mode == 0, iclass 32, count 2 2006.173.17:32:17.95#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.173.17:32:17.95#ibcon#[27=AT04-04\r\n] 2006.173.17:32:17.95#ibcon#*before write, iclass 32, count 2 2006.173.17:32:17.95#ibcon#enter sib2, iclass 32, count 2 2006.173.17:32:17.95#ibcon#flushed, iclass 32, count 2 2006.173.17:32:17.95#ibcon#about to write, iclass 32, count 2 2006.173.17:32:17.95#ibcon#wrote, iclass 32, count 2 2006.173.17:32:17.95#ibcon#about to read 3, iclass 32, count 2 2006.173.17:32:17.98#ibcon#read 3, iclass 32, count 2 2006.173.17:32:17.98#ibcon#about to read 4, iclass 32, count 2 2006.173.17:32:17.98#ibcon#read 4, iclass 32, count 2 2006.173.17:32:17.98#ibcon#about to read 5, iclass 32, count 2 2006.173.17:32:17.98#ibcon#read 5, iclass 32, count 2 2006.173.17:32:17.98#ibcon#about to read 6, iclass 32, count 2 2006.173.17:32:17.98#ibcon#read 6, iclass 32, count 2 2006.173.17:32:17.98#ibcon#end of sib2, iclass 32, count 2 2006.173.17:32:17.98#ibcon#*after write, iclass 32, count 2 2006.173.17:32:17.98#ibcon#*before return 0, iclass 32, count 2 2006.173.17:32:17.98#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.17:32:17.98#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.173.17:32:17.98#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.173.17:32:17.98#ibcon#ireg 7 cls_cnt 0 2006.173.17:32:17.98#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.17:32:18.10#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.17:32:18.10#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.17:32:18.10#ibcon#enter wrdev, iclass 32, count 0 2006.173.17:32:18.10#ibcon#first serial, iclass 32, count 0 2006.173.17:32:18.10#ibcon#enter sib2, iclass 32, count 0 2006.173.17:32:18.10#ibcon#flushed, iclass 32, count 0 2006.173.17:32:18.10#ibcon#about to write, iclass 32, count 0 2006.173.17:32:18.10#ibcon#wrote, iclass 32, count 0 2006.173.17:32:18.10#ibcon#about to read 3, iclass 32, count 0 2006.173.17:32:18.12#ibcon#read 3, iclass 32, count 0 2006.173.17:32:18.12#ibcon#about to read 4, iclass 32, count 0 2006.173.17:32:18.12#ibcon#read 4, iclass 32, count 0 2006.173.17:32:18.12#ibcon#about to read 5, iclass 32, count 0 2006.173.17:32:18.12#ibcon#read 5, iclass 32, count 0 2006.173.17:32:18.12#ibcon#about to read 6, iclass 32, count 0 2006.173.17:32:18.12#ibcon#read 6, iclass 32, count 0 2006.173.17:32:18.12#ibcon#end of sib2, iclass 32, count 0 2006.173.17:32:18.12#ibcon#*mode == 0, iclass 32, count 0 2006.173.17:32:18.12#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.17:32:18.12#ibcon#[27=USB\r\n] 2006.173.17:32:18.12#ibcon#*before write, iclass 32, count 0 2006.173.17:32:18.12#ibcon#enter sib2, iclass 32, count 0 2006.173.17:32:18.12#ibcon#flushed, iclass 32, count 0 2006.173.17:32:18.12#ibcon#about to write, iclass 32, count 0 2006.173.17:32:18.12#ibcon#wrote, iclass 32, count 0 2006.173.17:32:18.12#ibcon#about to read 3, iclass 32, count 0 2006.173.17:32:18.15#ibcon#read 3, iclass 32, count 0 2006.173.17:32:18.15#ibcon#about to read 4, iclass 32, count 0 2006.173.17:32:18.15#ibcon#read 4, iclass 32, count 0 2006.173.17:32:18.15#ibcon#about to read 5, iclass 32, count 0 2006.173.17:32:18.15#ibcon#read 5, iclass 32, count 0 2006.173.17:32:18.15#ibcon#about to read 6, iclass 32, count 0 2006.173.17:32:18.15#ibcon#read 6, iclass 32, count 0 2006.173.17:32:18.15#ibcon#end of sib2, iclass 32, count 0 2006.173.17:32:18.15#ibcon#*after write, iclass 32, count 0 2006.173.17:32:18.15#ibcon#*before return 0, iclass 32, count 0 2006.173.17:32:18.15#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.17:32:18.15#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.173.17:32:18.15#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.17:32:18.15#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.17:32:18.15$vck44/vblo=5,709.99 2006.173.17:32:18.15#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.17:32:18.15#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.17:32:18.15#ibcon#ireg 17 cls_cnt 0 2006.173.17:32:18.15#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.17:32:18.15#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.17:32:18.15#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.17:32:18.15#ibcon#enter wrdev, iclass 34, count 0 2006.173.17:32:18.15#ibcon#first serial, iclass 34, count 0 2006.173.17:32:18.15#ibcon#enter sib2, iclass 34, count 0 2006.173.17:32:18.15#ibcon#flushed, iclass 34, count 0 2006.173.17:32:18.15#ibcon#about to write, iclass 34, count 0 2006.173.17:32:18.15#ibcon#wrote, iclass 34, count 0 2006.173.17:32:18.15#ibcon#about to read 3, iclass 34, count 0 2006.173.17:32:18.17#ibcon#read 3, iclass 34, count 0 2006.173.17:32:18.17#ibcon#about to read 4, iclass 34, count 0 2006.173.17:32:18.17#ibcon#read 4, iclass 34, count 0 2006.173.17:32:18.17#ibcon#about to read 5, iclass 34, count 0 2006.173.17:32:18.17#ibcon#read 5, iclass 34, count 0 2006.173.17:32:18.17#ibcon#about to read 6, iclass 34, count 0 2006.173.17:32:18.17#ibcon#read 6, iclass 34, count 0 2006.173.17:32:18.17#ibcon#end of sib2, iclass 34, count 0 2006.173.17:32:18.17#ibcon#*mode == 0, iclass 34, count 0 2006.173.17:32:18.17#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.17:32:18.17#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.17:32:18.17#ibcon#*before write, iclass 34, count 0 2006.173.17:32:18.17#ibcon#enter sib2, iclass 34, count 0 2006.173.17:32:18.17#ibcon#flushed, iclass 34, count 0 2006.173.17:32:18.17#ibcon#about to write, iclass 34, count 0 2006.173.17:32:18.17#ibcon#wrote, iclass 34, count 0 2006.173.17:32:18.17#ibcon#about to read 3, iclass 34, count 0 2006.173.17:32:18.21#ibcon#read 3, iclass 34, count 0 2006.173.17:32:18.21#ibcon#about to read 4, iclass 34, count 0 2006.173.17:32:18.21#ibcon#read 4, iclass 34, count 0 2006.173.17:32:18.21#ibcon#about to read 5, iclass 34, count 0 2006.173.17:32:18.21#ibcon#read 5, iclass 34, count 0 2006.173.17:32:18.21#ibcon#about to read 6, iclass 34, count 0 2006.173.17:32:18.21#ibcon#read 6, iclass 34, count 0 2006.173.17:32:18.21#ibcon#end of sib2, iclass 34, count 0 2006.173.17:32:18.21#ibcon#*after write, iclass 34, count 0 2006.173.17:32:18.21#ibcon#*before return 0, iclass 34, count 0 2006.173.17:32:18.21#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.17:32:18.21#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.17:32:18.21#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.17:32:18.21#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.17:32:18.21$vck44/vb=5,4 2006.173.17:32:18.21#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.17:32:18.21#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.17:32:18.21#ibcon#ireg 11 cls_cnt 2 2006.173.17:32:18.21#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.17:32:18.27#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.17:32:18.27#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.17:32:18.27#ibcon#enter wrdev, iclass 36, count 2 2006.173.17:32:18.27#ibcon#first serial, iclass 36, count 2 2006.173.17:32:18.27#ibcon#enter sib2, iclass 36, count 2 2006.173.17:32:18.27#ibcon#flushed, iclass 36, count 2 2006.173.17:32:18.27#ibcon#about to write, iclass 36, count 2 2006.173.17:32:18.27#ibcon#wrote, iclass 36, count 2 2006.173.17:32:18.27#ibcon#about to read 3, iclass 36, count 2 2006.173.17:32:18.29#ibcon#read 3, iclass 36, count 2 2006.173.17:32:18.29#ibcon#about to read 4, iclass 36, count 2 2006.173.17:32:18.29#ibcon#read 4, iclass 36, count 2 2006.173.17:32:18.29#ibcon#about to read 5, iclass 36, count 2 2006.173.17:32:18.29#ibcon#read 5, iclass 36, count 2 2006.173.17:32:18.29#ibcon#about to read 6, iclass 36, count 2 2006.173.17:32:18.29#ibcon#read 6, iclass 36, count 2 2006.173.17:32:18.29#ibcon#end of sib2, iclass 36, count 2 2006.173.17:32:18.29#ibcon#*mode == 0, iclass 36, count 2 2006.173.17:32:18.29#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.17:32:18.29#ibcon#[27=AT05-04\r\n] 2006.173.17:32:18.29#ibcon#*before write, iclass 36, count 2 2006.173.17:32:18.29#ibcon#enter sib2, iclass 36, count 2 2006.173.17:32:18.29#ibcon#flushed, iclass 36, count 2 2006.173.17:32:18.29#ibcon#about to write, iclass 36, count 2 2006.173.17:32:18.29#ibcon#wrote, iclass 36, count 2 2006.173.17:32:18.29#ibcon#about to read 3, iclass 36, count 2 2006.173.17:32:18.32#ibcon#read 3, iclass 36, count 2 2006.173.17:32:18.32#ibcon#about to read 4, iclass 36, count 2 2006.173.17:32:18.32#ibcon#read 4, iclass 36, count 2 2006.173.17:32:18.32#ibcon#about to read 5, iclass 36, count 2 2006.173.17:32:18.32#ibcon#read 5, iclass 36, count 2 2006.173.17:32:18.32#ibcon#about to read 6, iclass 36, count 2 2006.173.17:32:18.32#ibcon#read 6, iclass 36, count 2 2006.173.17:32:18.32#ibcon#end of sib2, iclass 36, count 2 2006.173.17:32:18.32#ibcon#*after write, iclass 36, count 2 2006.173.17:32:18.32#ibcon#*before return 0, iclass 36, count 2 2006.173.17:32:18.32#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.17:32:18.32#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.17:32:18.32#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.17:32:18.32#ibcon#ireg 7 cls_cnt 0 2006.173.17:32:18.32#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.17:32:18.44#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.17:32:18.44#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.17:32:18.44#ibcon#enter wrdev, iclass 36, count 0 2006.173.17:32:18.44#ibcon#first serial, iclass 36, count 0 2006.173.17:32:18.44#ibcon#enter sib2, iclass 36, count 0 2006.173.17:32:18.44#ibcon#flushed, iclass 36, count 0 2006.173.17:32:18.44#ibcon#about to write, iclass 36, count 0 2006.173.17:32:18.44#ibcon#wrote, iclass 36, count 0 2006.173.17:32:18.44#ibcon#about to read 3, iclass 36, count 0 2006.173.17:32:18.46#ibcon#read 3, iclass 36, count 0 2006.173.17:32:18.46#ibcon#about to read 4, iclass 36, count 0 2006.173.17:32:18.46#ibcon#read 4, iclass 36, count 0 2006.173.17:32:18.46#ibcon#about to read 5, iclass 36, count 0 2006.173.17:32:18.46#ibcon#read 5, iclass 36, count 0 2006.173.17:32:18.46#ibcon#about to read 6, iclass 36, count 0 2006.173.17:32:18.46#ibcon#read 6, iclass 36, count 0 2006.173.17:32:18.46#ibcon#end of sib2, iclass 36, count 0 2006.173.17:32:18.46#ibcon#*mode == 0, iclass 36, count 0 2006.173.17:32:18.46#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.17:32:18.46#ibcon#[27=USB\r\n] 2006.173.17:32:18.46#ibcon#*before write, iclass 36, count 0 2006.173.17:32:18.46#ibcon#enter sib2, iclass 36, count 0 2006.173.17:32:18.46#ibcon#flushed, iclass 36, count 0 2006.173.17:32:18.46#ibcon#about to write, iclass 36, count 0 2006.173.17:32:18.46#ibcon#wrote, iclass 36, count 0 2006.173.17:32:18.46#ibcon#about to read 3, iclass 36, count 0 2006.173.17:32:18.49#ibcon#read 3, iclass 36, count 0 2006.173.17:32:18.49#ibcon#about to read 4, iclass 36, count 0 2006.173.17:32:18.49#ibcon#read 4, iclass 36, count 0 2006.173.17:32:18.49#ibcon#about to read 5, iclass 36, count 0 2006.173.17:32:18.49#ibcon#read 5, iclass 36, count 0 2006.173.17:32:18.49#ibcon#about to read 6, iclass 36, count 0 2006.173.17:32:18.49#ibcon#read 6, iclass 36, count 0 2006.173.17:32:18.49#ibcon#end of sib2, iclass 36, count 0 2006.173.17:32:18.49#ibcon#*after write, iclass 36, count 0 2006.173.17:32:18.49#ibcon#*before return 0, iclass 36, count 0 2006.173.17:32:18.49#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.17:32:18.49#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.17:32:18.49#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.17:32:18.49#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.17:32:18.49$vck44/vblo=6,719.99 2006.173.17:32:18.49#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.17:32:18.49#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.17:32:18.49#ibcon#ireg 17 cls_cnt 0 2006.173.17:32:18.49#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.17:32:18.49#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.17:32:18.49#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.17:32:18.49#ibcon#enter wrdev, iclass 38, count 0 2006.173.17:32:18.49#ibcon#first serial, iclass 38, count 0 2006.173.17:32:18.49#ibcon#enter sib2, iclass 38, count 0 2006.173.17:32:18.49#ibcon#flushed, iclass 38, count 0 2006.173.17:32:18.49#ibcon#about to write, iclass 38, count 0 2006.173.17:32:18.49#ibcon#wrote, iclass 38, count 0 2006.173.17:32:18.49#ibcon#about to read 3, iclass 38, count 0 2006.173.17:32:18.51#ibcon#read 3, iclass 38, count 0 2006.173.17:32:18.51#ibcon#about to read 4, iclass 38, count 0 2006.173.17:32:18.51#ibcon#read 4, iclass 38, count 0 2006.173.17:32:18.51#ibcon#about to read 5, iclass 38, count 0 2006.173.17:32:18.51#ibcon#read 5, iclass 38, count 0 2006.173.17:32:18.51#ibcon#about to read 6, iclass 38, count 0 2006.173.17:32:18.51#ibcon#read 6, iclass 38, count 0 2006.173.17:32:18.51#ibcon#end of sib2, iclass 38, count 0 2006.173.17:32:18.51#ibcon#*mode == 0, iclass 38, count 0 2006.173.17:32:18.51#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.17:32:18.51#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.17:32:18.51#ibcon#*before write, iclass 38, count 0 2006.173.17:32:18.51#ibcon#enter sib2, iclass 38, count 0 2006.173.17:32:18.51#ibcon#flushed, iclass 38, count 0 2006.173.17:32:18.51#ibcon#about to write, iclass 38, count 0 2006.173.17:32:18.51#ibcon#wrote, iclass 38, count 0 2006.173.17:32:18.51#ibcon#about to read 3, iclass 38, count 0 2006.173.17:32:18.55#ibcon#read 3, iclass 38, count 0 2006.173.17:32:18.55#ibcon#about to read 4, iclass 38, count 0 2006.173.17:32:18.55#ibcon#read 4, iclass 38, count 0 2006.173.17:32:18.55#ibcon#about to read 5, iclass 38, count 0 2006.173.17:32:18.55#ibcon#read 5, iclass 38, count 0 2006.173.17:32:18.55#ibcon#about to read 6, iclass 38, count 0 2006.173.17:32:18.55#ibcon#read 6, iclass 38, count 0 2006.173.17:32:18.55#ibcon#end of sib2, iclass 38, count 0 2006.173.17:32:18.55#ibcon#*after write, iclass 38, count 0 2006.173.17:32:18.55#ibcon#*before return 0, iclass 38, count 0 2006.173.17:32:18.55#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.17:32:18.55#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.17:32:18.55#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.17:32:18.55#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.17:32:18.55$vck44/vb=6,4 2006.173.17:32:18.55#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.17:32:18.55#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.17:32:18.55#ibcon#ireg 11 cls_cnt 2 2006.173.17:32:18.55#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.17:32:18.61#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.17:32:18.61#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.17:32:18.61#ibcon#enter wrdev, iclass 40, count 2 2006.173.17:32:18.61#ibcon#first serial, iclass 40, count 2 2006.173.17:32:18.61#ibcon#enter sib2, iclass 40, count 2 2006.173.17:32:18.61#ibcon#flushed, iclass 40, count 2 2006.173.17:32:18.61#ibcon#about to write, iclass 40, count 2 2006.173.17:32:18.61#ibcon#wrote, iclass 40, count 2 2006.173.17:32:18.61#ibcon#about to read 3, iclass 40, count 2 2006.173.17:32:18.63#ibcon#read 3, iclass 40, count 2 2006.173.17:32:18.63#ibcon#about to read 4, iclass 40, count 2 2006.173.17:32:18.63#ibcon#read 4, iclass 40, count 2 2006.173.17:32:18.63#ibcon#about to read 5, iclass 40, count 2 2006.173.17:32:18.63#ibcon#read 5, iclass 40, count 2 2006.173.17:32:18.63#ibcon#about to read 6, iclass 40, count 2 2006.173.17:32:18.63#ibcon#read 6, iclass 40, count 2 2006.173.17:32:18.63#ibcon#end of sib2, iclass 40, count 2 2006.173.17:32:18.63#ibcon#*mode == 0, iclass 40, count 2 2006.173.17:32:18.63#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.17:32:18.63#ibcon#[27=AT06-04\r\n] 2006.173.17:32:18.63#ibcon#*before write, iclass 40, count 2 2006.173.17:32:18.63#ibcon#enter sib2, iclass 40, count 2 2006.173.17:32:18.63#ibcon#flushed, iclass 40, count 2 2006.173.17:32:18.63#ibcon#about to write, iclass 40, count 2 2006.173.17:32:18.63#ibcon#wrote, iclass 40, count 2 2006.173.17:32:18.63#ibcon#about to read 3, iclass 40, count 2 2006.173.17:32:18.66#ibcon#read 3, iclass 40, count 2 2006.173.17:32:18.66#ibcon#about to read 4, iclass 40, count 2 2006.173.17:32:18.66#ibcon#read 4, iclass 40, count 2 2006.173.17:32:18.66#ibcon#about to read 5, iclass 40, count 2 2006.173.17:32:18.66#ibcon#read 5, iclass 40, count 2 2006.173.17:32:18.66#ibcon#about to read 6, iclass 40, count 2 2006.173.17:32:18.66#ibcon#read 6, iclass 40, count 2 2006.173.17:32:18.66#ibcon#end of sib2, iclass 40, count 2 2006.173.17:32:18.66#ibcon#*after write, iclass 40, count 2 2006.173.17:32:18.66#ibcon#*before return 0, iclass 40, count 2 2006.173.17:32:18.66#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.17:32:18.66#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.17:32:18.66#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.17:32:18.66#ibcon#ireg 7 cls_cnt 0 2006.173.17:32:18.66#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.17:32:18.78#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.17:32:18.78#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.17:32:18.78#ibcon#enter wrdev, iclass 40, count 0 2006.173.17:32:18.78#ibcon#first serial, iclass 40, count 0 2006.173.17:32:18.78#ibcon#enter sib2, iclass 40, count 0 2006.173.17:32:18.78#ibcon#flushed, iclass 40, count 0 2006.173.17:32:18.78#ibcon#about to write, iclass 40, count 0 2006.173.17:32:18.78#ibcon#wrote, iclass 40, count 0 2006.173.17:32:18.78#ibcon#about to read 3, iclass 40, count 0 2006.173.17:32:18.80#ibcon#read 3, iclass 40, count 0 2006.173.17:32:18.80#ibcon#about to read 4, iclass 40, count 0 2006.173.17:32:18.80#ibcon#read 4, iclass 40, count 0 2006.173.17:32:18.80#ibcon#about to read 5, iclass 40, count 0 2006.173.17:32:18.80#ibcon#read 5, iclass 40, count 0 2006.173.17:32:18.80#ibcon#about to read 6, iclass 40, count 0 2006.173.17:32:18.80#ibcon#read 6, iclass 40, count 0 2006.173.17:32:18.80#ibcon#end of sib2, iclass 40, count 0 2006.173.17:32:18.80#ibcon#*mode == 0, iclass 40, count 0 2006.173.17:32:18.80#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.17:32:18.80#ibcon#[27=USB\r\n] 2006.173.17:32:18.80#ibcon#*before write, iclass 40, count 0 2006.173.17:32:18.80#ibcon#enter sib2, iclass 40, count 0 2006.173.17:32:18.80#ibcon#flushed, iclass 40, count 0 2006.173.17:32:18.80#ibcon#about to write, iclass 40, count 0 2006.173.17:32:18.80#ibcon#wrote, iclass 40, count 0 2006.173.17:32:18.80#ibcon#about to read 3, iclass 40, count 0 2006.173.17:32:18.83#ibcon#read 3, iclass 40, count 0 2006.173.17:32:18.83#ibcon#about to read 4, iclass 40, count 0 2006.173.17:32:18.83#ibcon#read 4, iclass 40, count 0 2006.173.17:32:18.83#ibcon#about to read 5, iclass 40, count 0 2006.173.17:32:18.83#ibcon#read 5, iclass 40, count 0 2006.173.17:32:18.83#ibcon#about to read 6, iclass 40, count 0 2006.173.17:32:18.83#ibcon#read 6, iclass 40, count 0 2006.173.17:32:18.83#ibcon#end of sib2, iclass 40, count 0 2006.173.17:32:18.83#ibcon#*after write, iclass 40, count 0 2006.173.17:32:18.83#ibcon#*before return 0, iclass 40, count 0 2006.173.17:32:18.83#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.17:32:18.83#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.17:32:18.83#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.17:32:18.83#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.17:32:18.83$vck44/vblo=7,734.99 2006.173.17:32:18.83#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.17:32:18.83#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.17:32:18.83#ibcon#ireg 17 cls_cnt 0 2006.173.17:32:18.83#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.17:32:18.83#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.17:32:18.83#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.17:32:18.83#ibcon#enter wrdev, iclass 4, count 0 2006.173.17:32:18.83#ibcon#first serial, iclass 4, count 0 2006.173.17:32:18.83#ibcon#enter sib2, iclass 4, count 0 2006.173.17:32:18.83#ibcon#flushed, iclass 4, count 0 2006.173.17:32:18.83#ibcon#about to write, iclass 4, count 0 2006.173.17:32:18.83#ibcon#wrote, iclass 4, count 0 2006.173.17:32:18.83#ibcon#about to read 3, iclass 4, count 0 2006.173.17:32:18.85#ibcon#read 3, iclass 4, count 0 2006.173.17:32:18.85#ibcon#about to read 4, iclass 4, count 0 2006.173.17:32:18.85#ibcon#read 4, iclass 4, count 0 2006.173.17:32:18.85#ibcon#about to read 5, iclass 4, count 0 2006.173.17:32:18.85#ibcon#read 5, iclass 4, count 0 2006.173.17:32:18.85#ibcon#about to read 6, iclass 4, count 0 2006.173.17:32:18.85#ibcon#read 6, iclass 4, count 0 2006.173.17:32:18.85#ibcon#end of sib2, iclass 4, count 0 2006.173.17:32:18.85#ibcon#*mode == 0, iclass 4, count 0 2006.173.17:32:18.85#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.17:32:18.85#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.17:32:18.85#ibcon#*before write, iclass 4, count 0 2006.173.17:32:18.85#ibcon#enter sib2, iclass 4, count 0 2006.173.17:32:18.85#ibcon#flushed, iclass 4, count 0 2006.173.17:32:18.85#ibcon#about to write, iclass 4, count 0 2006.173.17:32:18.85#ibcon#wrote, iclass 4, count 0 2006.173.17:32:18.85#ibcon#about to read 3, iclass 4, count 0 2006.173.17:32:18.89#ibcon#read 3, iclass 4, count 0 2006.173.17:32:18.89#ibcon#about to read 4, iclass 4, count 0 2006.173.17:32:18.89#ibcon#read 4, iclass 4, count 0 2006.173.17:32:18.89#ibcon#about to read 5, iclass 4, count 0 2006.173.17:32:18.89#ibcon#read 5, iclass 4, count 0 2006.173.17:32:18.89#ibcon#about to read 6, iclass 4, count 0 2006.173.17:32:18.89#ibcon#read 6, iclass 4, count 0 2006.173.17:32:18.89#ibcon#end of sib2, iclass 4, count 0 2006.173.17:32:18.89#ibcon#*after write, iclass 4, count 0 2006.173.17:32:18.89#ibcon#*before return 0, iclass 4, count 0 2006.173.17:32:18.89#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.17:32:18.89#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.17:32:18.89#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.17:32:18.89#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.17:32:18.89$vck44/vb=7,4 2006.173.17:32:18.89#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.17:32:18.89#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.17:32:18.89#ibcon#ireg 11 cls_cnt 2 2006.173.17:32:18.89#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.17:32:18.95#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.17:32:18.95#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.17:32:18.95#ibcon#enter wrdev, iclass 6, count 2 2006.173.17:32:18.95#ibcon#first serial, iclass 6, count 2 2006.173.17:32:18.95#ibcon#enter sib2, iclass 6, count 2 2006.173.17:32:18.95#ibcon#flushed, iclass 6, count 2 2006.173.17:32:18.95#ibcon#about to write, iclass 6, count 2 2006.173.17:32:18.95#ibcon#wrote, iclass 6, count 2 2006.173.17:32:18.95#ibcon#about to read 3, iclass 6, count 2 2006.173.17:32:18.97#ibcon#read 3, iclass 6, count 2 2006.173.17:32:18.97#ibcon#about to read 4, iclass 6, count 2 2006.173.17:32:18.97#ibcon#read 4, iclass 6, count 2 2006.173.17:32:18.97#ibcon#about to read 5, iclass 6, count 2 2006.173.17:32:18.97#ibcon#read 5, iclass 6, count 2 2006.173.17:32:18.97#ibcon#about to read 6, iclass 6, count 2 2006.173.17:32:18.97#ibcon#read 6, iclass 6, count 2 2006.173.17:32:18.97#ibcon#end of sib2, iclass 6, count 2 2006.173.17:32:18.97#ibcon#*mode == 0, iclass 6, count 2 2006.173.17:32:18.97#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.17:32:18.97#ibcon#[27=AT07-04\r\n] 2006.173.17:32:18.97#ibcon#*before write, iclass 6, count 2 2006.173.17:32:18.97#ibcon#enter sib2, iclass 6, count 2 2006.173.17:32:18.97#ibcon#flushed, iclass 6, count 2 2006.173.17:32:18.97#ibcon#about to write, iclass 6, count 2 2006.173.17:32:18.97#ibcon#wrote, iclass 6, count 2 2006.173.17:32:18.97#ibcon#about to read 3, iclass 6, count 2 2006.173.17:32:19.00#ibcon#read 3, iclass 6, count 2 2006.173.17:32:19.00#ibcon#about to read 4, iclass 6, count 2 2006.173.17:32:19.00#ibcon#read 4, iclass 6, count 2 2006.173.17:32:19.00#ibcon#about to read 5, iclass 6, count 2 2006.173.17:32:19.00#ibcon#read 5, iclass 6, count 2 2006.173.17:32:19.00#ibcon#about to read 6, iclass 6, count 2 2006.173.17:32:19.00#ibcon#read 6, iclass 6, count 2 2006.173.17:32:19.00#ibcon#end of sib2, iclass 6, count 2 2006.173.17:32:19.00#ibcon#*after write, iclass 6, count 2 2006.173.17:32:19.00#ibcon#*before return 0, iclass 6, count 2 2006.173.17:32:19.00#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.17:32:19.00#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.17:32:19.00#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.17:32:19.00#ibcon#ireg 7 cls_cnt 0 2006.173.17:32:19.00#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.17:32:19.12#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.17:32:19.12#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.17:32:19.12#ibcon#enter wrdev, iclass 6, count 0 2006.173.17:32:19.12#ibcon#first serial, iclass 6, count 0 2006.173.17:32:19.12#ibcon#enter sib2, iclass 6, count 0 2006.173.17:32:19.12#ibcon#flushed, iclass 6, count 0 2006.173.17:32:19.12#ibcon#about to write, iclass 6, count 0 2006.173.17:32:19.12#ibcon#wrote, iclass 6, count 0 2006.173.17:32:19.12#ibcon#about to read 3, iclass 6, count 0 2006.173.17:32:19.14#ibcon#read 3, iclass 6, count 0 2006.173.17:32:19.14#ibcon#about to read 4, iclass 6, count 0 2006.173.17:32:19.14#ibcon#read 4, iclass 6, count 0 2006.173.17:32:19.14#ibcon#about to read 5, iclass 6, count 0 2006.173.17:32:19.14#ibcon#read 5, iclass 6, count 0 2006.173.17:32:19.14#ibcon#about to read 6, iclass 6, count 0 2006.173.17:32:19.14#ibcon#read 6, iclass 6, count 0 2006.173.17:32:19.14#ibcon#end of sib2, iclass 6, count 0 2006.173.17:32:19.14#ibcon#*mode == 0, iclass 6, count 0 2006.173.17:32:19.14#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.17:32:19.14#ibcon#[27=USB\r\n] 2006.173.17:32:19.14#ibcon#*before write, iclass 6, count 0 2006.173.17:32:19.14#ibcon#enter sib2, iclass 6, count 0 2006.173.17:32:19.14#ibcon#flushed, iclass 6, count 0 2006.173.17:32:19.14#ibcon#about to write, iclass 6, count 0 2006.173.17:32:19.14#ibcon#wrote, iclass 6, count 0 2006.173.17:32:19.14#ibcon#about to read 3, iclass 6, count 0 2006.173.17:32:19.17#ibcon#read 3, iclass 6, count 0 2006.173.17:32:19.17#ibcon#about to read 4, iclass 6, count 0 2006.173.17:32:19.17#ibcon#read 4, iclass 6, count 0 2006.173.17:32:19.17#ibcon#about to read 5, iclass 6, count 0 2006.173.17:32:19.17#ibcon#read 5, iclass 6, count 0 2006.173.17:32:19.17#ibcon#about to read 6, iclass 6, count 0 2006.173.17:32:19.17#ibcon#read 6, iclass 6, count 0 2006.173.17:32:19.17#ibcon#end of sib2, iclass 6, count 0 2006.173.17:32:19.17#ibcon#*after write, iclass 6, count 0 2006.173.17:32:19.17#ibcon#*before return 0, iclass 6, count 0 2006.173.17:32:19.17#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.17:32:19.17#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.17:32:19.17#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.17:32:19.17#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.17:32:19.17$vck44/vblo=8,744.99 2006.173.17:32:19.17#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.17:32:19.17#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.17:32:19.17#ibcon#ireg 17 cls_cnt 0 2006.173.17:32:19.17#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.17:32:19.17#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.17:32:19.17#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.17:32:19.17#ibcon#enter wrdev, iclass 10, count 0 2006.173.17:32:19.17#ibcon#first serial, iclass 10, count 0 2006.173.17:32:19.17#ibcon#enter sib2, iclass 10, count 0 2006.173.17:32:19.17#ibcon#flushed, iclass 10, count 0 2006.173.17:32:19.17#ibcon#about to write, iclass 10, count 0 2006.173.17:32:19.17#ibcon#wrote, iclass 10, count 0 2006.173.17:32:19.17#ibcon#about to read 3, iclass 10, count 0 2006.173.17:32:19.19#ibcon#read 3, iclass 10, count 0 2006.173.17:32:19.19#ibcon#about to read 4, iclass 10, count 0 2006.173.17:32:19.19#ibcon#read 4, iclass 10, count 0 2006.173.17:32:19.19#ibcon#about to read 5, iclass 10, count 0 2006.173.17:32:19.19#ibcon#read 5, iclass 10, count 0 2006.173.17:32:19.19#ibcon#about to read 6, iclass 10, count 0 2006.173.17:32:19.19#ibcon#read 6, iclass 10, count 0 2006.173.17:32:19.19#ibcon#end of sib2, iclass 10, count 0 2006.173.17:32:19.19#ibcon#*mode == 0, iclass 10, count 0 2006.173.17:32:19.19#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.17:32:19.19#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.17:32:19.19#ibcon#*before write, iclass 10, count 0 2006.173.17:32:19.19#ibcon#enter sib2, iclass 10, count 0 2006.173.17:32:19.19#ibcon#flushed, iclass 10, count 0 2006.173.17:32:19.19#ibcon#about to write, iclass 10, count 0 2006.173.17:32:19.19#ibcon#wrote, iclass 10, count 0 2006.173.17:32:19.19#ibcon#about to read 3, iclass 10, count 0 2006.173.17:32:19.23#ibcon#read 3, iclass 10, count 0 2006.173.17:32:19.23#ibcon#about to read 4, iclass 10, count 0 2006.173.17:32:19.23#ibcon#read 4, iclass 10, count 0 2006.173.17:32:19.23#ibcon#about to read 5, iclass 10, count 0 2006.173.17:32:19.23#ibcon#read 5, iclass 10, count 0 2006.173.17:32:19.23#ibcon#about to read 6, iclass 10, count 0 2006.173.17:32:19.23#ibcon#read 6, iclass 10, count 0 2006.173.17:32:19.23#ibcon#end of sib2, iclass 10, count 0 2006.173.17:32:19.23#ibcon#*after write, iclass 10, count 0 2006.173.17:32:19.23#ibcon#*before return 0, iclass 10, count 0 2006.173.17:32:19.23#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.17:32:19.23#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.17:32:19.23#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.17:32:19.23#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.17:32:19.23$vck44/vb=8,4 2006.173.17:32:19.23#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.17:32:19.23#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.17:32:19.23#ibcon#ireg 11 cls_cnt 2 2006.173.17:32:19.23#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.17:32:19.29#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.17:32:19.29#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.17:32:19.29#ibcon#enter wrdev, iclass 12, count 2 2006.173.17:32:19.29#ibcon#first serial, iclass 12, count 2 2006.173.17:32:19.29#ibcon#enter sib2, iclass 12, count 2 2006.173.17:32:19.29#ibcon#flushed, iclass 12, count 2 2006.173.17:32:19.29#ibcon#about to write, iclass 12, count 2 2006.173.17:32:19.29#ibcon#wrote, iclass 12, count 2 2006.173.17:32:19.29#ibcon#about to read 3, iclass 12, count 2 2006.173.17:32:19.31#ibcon#read 3, iclass 12, count 2 2006.173.17:32:19.31#ibcon#about to read 4, iclass 12, count 2 2006.173.17:32:19.31#ibcon#read 4, iclass 12, count 2 2006.173.17:32:19.31#ibcon#about to read 5, iclass 12, count 2 2006.173.17:32:19.31#ibcon#read 5, iclass 12, count 2 2006.173.17:32:19.31#ibcon#about to read 6, iclass 12, count 2 2006.173.17:32:19.31#ibcon#read 6, iclass 12, count 2 2006.173.17:32:19.31#ibcon#end of sib2, iclass 12, count 2 2006.173.17:32:19.31#ibcon#*mode == 0, iclass 12, count 2 2006.173.17:32:19.31#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.17:32:19.31#ibcon#[27=AT08-04\r\n] 2006.173.17:32:19.31#ibcon#*before write, iclass 12, count 2 2006.173.17:32:19.31#ibcon#enter sib2, iclass 12, count 2 2006.173.17:32:19.31#ibcon#flushed, iclass 12, count 2 2006.173.17:32:19.31#ibcon#about to write, iclass 12, count 2 2006.173.17:32:19.31#ibcon#wrote, iclass 12, count 2 2006.173.17:32:19.31#ibcon#about to read 3, iclass 12, count 2 2006.173.17:32:19.34#ibcon#read 3, iclass 12, count 2 2006.173.17:32:19.34#ibcon#about to read 4, iclass 12, count 2 2006.173.17:32:19.34#ibcon#read 4, iclass 12, count 2 2006.173.17:32:19.34#ibcon#about to read 5, iclass 12, count 2 2006.173.17:32:19.34#ibcon#read 5, iclass 12, count 2 2006.173.17:32:19.34#ibcon#about to read 6, iclass 12, count 2 2006.173.17:32:19.34#ibcon#read 6, iclass 12, count 2 2006.173.17:32:19.34#ibcon#end of sib2, iclass 12, count 2 2006.173.17:32:19.34#ibcon#*after write, iclass 12, count 2 2006.173.17:32:19.34#ibcon#*before return 0, iclass 12, count 2 2006.173.17:32:19.34#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.17:32:19.34#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.17:32:19.34#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.17:32:19.34#ibcon#ireg 7 cls_cnt 0 2006.173.17:32:19.34#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.17:32:19.46#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.17:32:19.46#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.17:32:19.46#ibcon#enter wrdev, iclass 12, count 0 2006.173.17:32:19.46#ibcon#first serial, iclass 12, count 0 2006.173.17:32:19.46#ibcon#enter sib2, iclass 12, count 0 2006.173.17:32:19.46#ibcon#flushed, iclass 12, count 0 2006.173.17:32:19.46#ibcon#about to write, iclass 12, count 0 2006.173.17:32:19.46#ibcon#wrote, iclass 12, count 0 2006.173.17:32:19.46#ibcon#about to read 3, iclass 12, count 0 2006.173.17:32:19.48#ibcon#read 3, iclass 12, count 0 2006.173.17:32:19.48#ibcon#about to read 4, iclass 12, count 0 2006.173.17:32:19.48#ibcon#read 4, iclass 12, count 0 2006.173.17:32:19.48#ibcon#about to read 5, iclass 12, count 0 2006.173.17:32:19.48#ibcon#read 5, iclass 12, count 0 2006.173.17:32:19.48#ibcon#about to read 6, iclass 12, count 0 2006.173.17:32:19.48#ibcon#read 6, iclass 12, count 0 2006.173.17:32:19.48#ibcon#end of sib2, iclass 12, count 0 2006.173.17:32:19.48#ibcon#*mode == 0, iclass 12, count 0 2006.173.17:32:19.48#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.17:32:19.48#ibcon#[27=USB\r\n] 2006.173.17:32:19.48#ibcon#*before write, iclass 12, count 0 2006.173.17:32:19.48#ibcon#enter sib2, iclass 12, count 0 2006.173.17:32:19.48#ibcon#flushed, iclass 12, count 0 2006.173.17:32:19.48#ibcon#about to write, iclass 12, count 0 2006.173.17:32:19.48#ibcon#wrote, iclass 12, count 0 2006.173.17:32:19.48#ibcon#about to read 3, iclass 12, count 0 2006.173.17:32:19.51#ibcon#read 3, iclass 12, count 0 2006.173.17:32:19.51#ibcon#about to read 4, iclass 12, count 0 2006.173.17:32:19.51#ibcon#read 4, iclass 12, count 0 2006.173.17:32:19.51#ibcon#about to read 5, iclass 12, count 0 2006.173.17:32:19.51#ibcon#read 5, iclass 12, count 0 2006.173.17:32:19.51#ibcon#about to read 6, iclass 12, count 0 2006.173.17:32:19.51#ibcon#read 6, iclass 12, count 0 2006.173.17:32:19.51#ibcon#end of sib2, iclass 12, count 0 2006.173.17:32:19.51#ibcon#*after write, iclass 12, count 0 2006.173.17:32:19.51#ibcon#*before return 0, iclass 12, count 0 2006.173.17:32:19.51#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.17:32:19.51#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.17:32:19.51#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.17:32:19.51#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.17:32:19.51$vck44/vabw=wide 2006.173.17:32:19.51#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.17:32:19.51#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.17:32:19.51#ibcon#ireg 8 cls_cnt 0 2006.173.17:32:19.51#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.17:32:19.51#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.17:32:19.51#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.17:32:19.51#ibcon#enter wrdev, iclass 14, count 0 2006.173.17:32:19.51#ibcon#first serial, iclass 14, count 0 2006.173.17:32:19.51#ibcon#enter sib2, iclass 14, count 0 2006.173.17:32:19.51#ibcon#flushed, iclass 14, count 0 2006.173.17:32:19.51#ibcon#about to write, iclass 14, count 0 2006.173.17:32:19.51#ibcon#wrote, iclass 14, count 0 2006.173.17:32:19.51#ibcon#about to read 3, iclass 14, count 0 2006.173.17:32:19.53#ibcon#read 3, iclass 14, count 0 2006.173.17:32:19.53#ibcon#about to read 4, iclass 14, count 0 2006.173.17:32:19.53#ibcon#read 4, iclass 14, count 0 2006.173.17:32:19.53#ibcon#about to read 5, iclass 14, count 0 2006.173.17:32:19.53#ibcon#read 5, iclass 14, count 0 2006.173.17:32:19.53#ibcon#about to read 6, iclass 14, count 0 2006.173.17:32:19.53#ibcon#read 6, iclass 14, count 0 2006.173.17:32:19.53#ibcon#end of sib2, iclass 14, count 0 2006.173.17:32:19.53#ibcon#*mode == 0, iclass 14, count 0 2006.173.17:32:19.53#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.17:32:19.53#ibcon#[25=BW32\r\n] 2006.173.17:32:19.53#ibcon#*before write, iclass 14, count 0 2006.173.17:32:19.53#ibcon#enter sib2, iclass 14, count 0 2006.173.17:32:19.53#ibcon#flushed, iclass 14, count 0 2006.173.17:32:19.53#ibcon#about to write, iclass 14, count 0 2006.173.17:32:19.53#ibcon#wrote, iclass 14, count 0 2006.173.17:32:19.53#ibcon#about to read 3, iclass 14, count 0 2006.173.17:32:19.56#ibcon#read 3, iclass 14, count 0 2006.173.17:32:19.56#ibcon#about to read 4, iclass 14, count 0 2006.173.17:32:19.56#ibcon#read 4, iclass 14, count 0 2006.173.17:32:19.56#ibcon#about to read 5, iclass 14, count 0 2006.173.17:32:19.56#ibcon#read 5, iclass 14, count 0 2006.173.17:32:19.56#ibcon#about to read 6, iclass 14, count 0 2006.173.17:32:19.56#ibcon#read 6, iclass 14, count 0 2006.173.17:32:19.56#ibcon#end of sib2, iclass 14, count 0 2006.173.17:32:19.56#ibcon#*after write, iclass 14, count 0 2006.173.17:32:19.56#ibcon#*before return 0, iclass 14, count 0 2006.173.17:32:19.56#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.17:32:19.56#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.17:32:19.56#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.17:32:19.56#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.17:32:19.56$vck44/vbbw=wide 2006.173.17:32:19.56#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.17:32:19.56#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.17:32:19.56#ibcon#ireg 8 cls_cnt 0 2006.173.17:32:19.56#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.17:32:19.63#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.17:32:19.63#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.17:32:19.63#ibcon#enter wrdev, iclass 16, count 0 2006.173.17:32:19.63#ibcon#first serial, iclass 16, count 0 2006.173.17:32:19.63#ibcon#enter sib2, iclass 16, count 0 2006.173.17:32:19.63#ibcon#flushed, iclass 16, count 0 2006.173.17:32:19.63#ibcon#about to write, iclass 16, count 0 2006.173.17:32:19.63#ibcon#wrote, iclass 16, count 0 2006.173.17:32:19.63#ibcon#about to read 3, iclass 16, count 0 2006.173.17:32:19.65#ibcon#read 3, iclass 16, count 0 2006.173.17:32:19.65#ibcon#about to read 4, iclass 16, count 0 2006.173.17:32:19.65#ibcon#read 4, iclass 16, count 0 2006.173.17:32:19.65#ibcon#about to read 5, iclass 16, count 0 2006.173.17:32:19.65#ibcon#read 5, iclass 16, count 0 2006.173.17:32:19.65#ibcon#about to read 6, iclass 16, count 0 2006.173.17:32:19.65#ibcon#read 6, iclass 16, count 0 2006.173.17:32:19.65#ibcon#end of sib2, iclass 16, count 0 2006.173.17:32:19.65#ibcon#*mode == 0, iclass 16, count 0 2006.173.17:32:19.65#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.17:32:19.65#ibcon#[27=BW32\r\n] 2006.173.17:32:19.65#ibcon#*before write, iclass 16, count 0 2006.173.17:32:19.65#ibcon#enter sib2, iclass 16, count 0 2006.173.17:32:19.65#ibcon#flushed, iclass 16, count 0 2006.173.17:32:19.65#ibcon#about to write, iclass 16, count 0 2006.173.17:32:19.65#ibcon#wrote, iclass 16, count 0 2006.173.17:32:19.65#ibcon#about to read 3, iclass 16, count 0 2006.173.17:32:19.68#ibcon#read 3, iclass 16, count 0 2006.173.17:32:19.68#ibcon#about to read 4, iclass 16, count 0 2006.173.17:32:19.68#ibcon#read 4, iclass 16, count 0 2006.173.17:32:19.68#ibcon#about to read 5, iclass 16, count 0 2006.173.17:32:19.68#ibcon#read 5, iclass 16, count 0 2006.173.17:32:19.68#ibcon#about to read 6, iclass 16, count 0 2006.173.17:32:19.68#ibcon#read 6, iclass 16, count 0 2006.173.17:32:19.68#ibcon#end of sib2, iclass 16, count 0 2006.173.17:32:19.68#ibcon#*after write, iclass 16, count 0 2006.173.17:32:19.68#ibcon#*before return 0, iclass 16, count 0 2006.173.17:32:19.68#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.17:32:19.68#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.17:32:19.68#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.17:32:19.68#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.17:32:19.68$setupk4/ifdk4 2006.173.17:32:19.68$ifdk4/lo= 2006.173.17:32:19.68$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.17:32:19.68$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.17:32:19.68$ifdk4/patch= 2006.173.17:32:19.68$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.17:32:19.68$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.17:32:19.68$setupk4/!*+20s 2006.173.17:32:22.37#abcon#<5=/14 0.6 2.0 20.281001002.1\r\n> 2006.173.17:32:22.39#abcon#{5=INTERFACE CLEAR} 2006.173.17:32:22.45#abcon#[5=S1D000X0/0*\r\n] 2006.173.17:32:32.54#abcon#<5=/14 0.6 1.9 20.271001002.1\r\n> 2006.173.17:32:32.56#abcon#{5=INTERFACE CLEAR} 2006.173.17:32:32.62#abcon#[5=S1D000X0/0*\r\n] 2006.173.17:32:34.19$setupk4/"tpicd 2006.173.17:32:34.19$setupk4/echo=off 2006.173.17:32:34.19$setupk4/xlog=off 2006.173.17:32:34.19:!2006.173.17:35:38 2006.173.17:32:44.13#trakl#Source acquired 2006.173.17:32:46.13#flagr#flagr/antenna,acquired 2006.173.17:35:38.00:preob 2006.173.17:35:38.14/onsource/TRACKING 2006.173.17:35:38.14:!2006.173.17:35:48 2006.173.17:35:48.00:"tape 2006.173.17:35:48.00:"st=record 2006.173.17:35:48.00:data_valid=on 2006.173.17:35:48.00:midob 2006.173.17:35:49.14/onsource/TRACKING 2006.173.17:35:49.14/wx/20.24,1002.3,100 2006.173.17:35:49.20/cable/+6.5137E-03 2006.173.17:35:50.29/va/01,07,usb,yes,36,39 2006.173.17:35:50.29/va/02,06,usb,yes,36,37 2006.173.17:35:50.29/va/03,05,usb,yes,45,47 2006.173.17:35:50.29/va/04,06,usb,yes,36,38 2006.173.17:35:50.29/va/05,04,usb,yes,29,29 2006.173.17:35:50.29/va/06,03,usb,yes,40,40 2006.173.17:35:50.29/va/07,04,usb,yes,32,34 2006.173.17:35:50.29/va/08,04,usb,yes,28,33 2006.173.17:35:50.52/valo/01,524.99,yes,locked 2006.173.17:35:50.52/valo/02,534.99,yes,locked 2006.173.17:35:50.52/valo/03,564.99,yes,locked 2006.173.17:35:50.52/valo/04,624.99,yes,locked 2006.173.17:35:50.52/valo/05,734.99,yes,locked 2006.173.17:35:50.52/valo/06,814.99,yes,locked 2006.173.17:35:50.52/valo/07,864.99,yes,locked 2006.173.17:35:50.52/valo/08,884.99,yes,locked 2006.173.17:35:51.61/vb/01,04,usb,yes,30,28 2006.173.17:35:51.61/vb/02,04,usb,yes,32,32 2006.173.17:35:51.61/vb/03,04,usb,yes,29,32 2006.173.17:35:51.61/vb/04,04,usb,yes,33,32 2006.173.17:35:51.61/vb/05,04,usb,yes,26,28 2006.173.17:35:51.61/vb/06,04,usb,yes,30,27 2006.173.17:35:51.61/vb/07,04,usb,yes,30,30 2006.173.17:35:51.61/vb/08,04,usb,yes,28,31 2006.173.17:35:51.84/vblo/01,629.99,yes,locked 2006.173.17:35:51.84/vblo/02,634.99,yes,locked 2006.173.17:35:51.84/vblo/03,649.99,yes,locked 2006.173.17:35:51.84/vblo/04,679.99,yes,locked 2006.173.17:35:51.84/vblo/05,709.99,yes,locked 2006.173.17:35:51.84/vblo/06,719.99,yes,locked 2006.173.17:35:51.84/vblo/07,734.99,yes,locked 2006.173.17:35:51.84/vblo/08,744.99,yes,locked 2006.173.17:35:51.99/vabw/8 2006.173.17:35:52.14/vbbw/8 2006.173.17:35:52.23/xfe/off,on,15.5 2006.173.17:35:52.61/ifatt/23,28,28,28 2006.173.17:35:53.08/fmout-gps/S +3.99E-07 2006.173.17:35:53.12:!2006.173.17:36:28 2006.173.17:36:28.01:data_valid=off 2006.173.17:36:28.01:"et 2006.173.17:36:28.02:!+3s 2006.173.17:36:31.03:"tape 2006.173.17:36:31.03:postob 2006.173.17:36:31.20/cable/+6.5144E-03 2006.173.17:36:31.20/wx/20.23,1002.3,100 2006.173.17:36:31.26/fmout-gps/S +3.98E-07 2006.173.17:36:31.26:scan_name=173-1737,jd0606,70 2006.173.17:36:31.27:source=2121+053,212344.52,053522.1,2000.0,ccw 2006.173.17:36:33.14#flagr#flagr/antenna,new-source 2006.173.17:36:33.14:checkk5 2006.173.17:36:33.56/chk_autoobs//k5ts1/ autoobs is running! 2006.173.17:36:33.96/chk_autoobs//k5ts2/ autoobs is running! 2006.173.17:36:34.37/chk_autoobs//k5ts3/ autoobs is running! 2006.173.17:36:34.75/chk_autoobs//k5ts4/ autoobs is running! 2006.173.17:36:35.15/chk_obsdata//k5ts1/T1731735??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.17:36:35.57/chk_obsdata//k5ts2/T1731735??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.17:36:35.97/chk_obsdata//k5ts3/T1731735??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.17:36:36.37/chk_obsdata//k5ts4/T1731735??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.17:36:37.09/k5log//k5ts1_log_newline 2006.173.17:36:37.81/k5log//k5ts2_log_newline 2006.173.17:36:38.52/k5log//k5ts3_log_newline 2006.173.17:36:39.22/k5log//k5ts4_log_newline 2006.173.17:36:39.25/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.17:36:39.25:setupk4=1 2006.173.17:36:39.25$setupk4/echo=on 2006.173.17:36:39.25$setupk4/pcalon 2006.173.17:36:39.25$pcalon/"no phase cal control is implemented here 2006.173.17:36:39.25$setupk4/"tpicd=stop 2006.173.17:36:39.25$setupk4/"rec=synch_on 2006.173.17:36:39.25$setupk4/"rec_mode=128 2006.173.17:36:39.25$setupk4/!* 2006.173.17:36:39.25$setupk4/recpk4 2006.173.17:36:39.25$recpk4/recpatch= 2006.173.17:36:39.25$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.17:36:39.25$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.17:36:39.25$setupk4/vck44 2006.173.17:36:39.25$vck44/valo=1,524.99 2006.173.17:36:39.25#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.17:36:39.25#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.17:36:39.25#ibcon#ireg 17 cls_cnt 0 2006.173.17:36:39.25#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.17:36:39.25#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.17:36:39.25#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.17:36:39.25#ibcon#enter wrdev, iclass 17, count 0 2006.173.17:36:39.25#ibcon#first serial, iclass 17, count 0 2006.173.17:36:39.25#ibcon#enter sib2, iclass 17, count 0 2006.173.17:36:39.25#ibcon#flushed, iclass 17, count 0 2006.173.17:36:39.25#ibcon#about to write, iclass 17, count 0 2006.173.17:36:39.25#ibcon#wrote, iclass 17, count 0 2006.173.17:36:39.25#ibcon#about to read 3, iclass 17, count 0 2006.173.17:36:39.27#ibcon#read 3, iclass 17, count 0 2006.173.17:36:39.27#ibcon#about to read 4, iclass 17, count 0 2006.173.17:36:39.27#ibcon#read 4, iclass 17, count 0 2006.173.17:36:39.27#ibcon#about to read 5, iclass 17, count 0 2006.173.17:36:39.27#ibcon#read 5, iclass 17, count 0 2006.173.17:36:39.27#ibcon#about to read 6, iclass 17, count 0 2006.173.17:36:39.27#ibcon#read 6, iclass 17, count 0 2006.173.17:36:39.27#ibcon#end of sib2, iclass 17, count 0 2006.173.17:36:39.27#ibcon#*mode == 0, iclass 17, count 0 2006.173.17:36:39.27#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.17:36:39.27#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.17:36:39.27#ibcon#*before write, iclass 17, count 0 2006.173.17:36:39.27#ibcon#enter sib2, iclass 17, count 0 2006.173.17:36:39.27#ibcon#flushed, iclass 17, count 0 2006.173.17:36:39.27#ibcon#about to write, iclass 17, count 0 2006.173.17:36:39.27#ibcon#wrote, iclass 17, count 0 2006.173.17:36:39.27#ibcon#about to read 3, iclass 17, count 0 2006.173.17:36:39.32#ibcon#read 3, iclass 17, count 0 2006.173.17:36:39.32#ibcon#about to read 4, iclass 17, count 0 2006.173.17:36:39.32#ibcon#read 4, iclass 17, count 0 2006.173.17:36:39.32#ibcon#about to read 5, iclass 17, count 0 2006.173.17:36:39.32#ibcon#read 5, iclass 17, count 0 2006.173.17:36:39.32#ibcon#about to read 6, iclass 17, count 0 2006.173.17:36:39.32#ibcon#read 6, iclass 17, count 0 2006.173.17:36:39.32#ibcon#end of sib2, iclass 17, count 0 2006.173.17:36:39.32#ibcon#*after write, iclass 17, count 0 2006.173.17:36:39.32#ibcon#*before return 0, iclass 17, count 0 2006.173.17:36:39.32#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.17:36:39.32#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.17:36:39.32#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.17:36:39.32#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.17:36:39.32$vck44/va=1,7 2006.173.17:36:39.32#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.17:36:39.32#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.17:36:39.32#ibcon#ireg 11 cls_cnt 2 2006.173.17:36:39.32#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.17:36:39.32#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.17:36:39.32#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.17:36:39.32#ibcon#enter wrdev, iclass 19, count 2 2006.173.17:36:39.32#ibcon#first serial, iclass 19, count 2 2006.173.17:36:39.32#ibcon#enter sib2, iclass 19, count 2 2006.173.17:36:39.32#ibcon#flushed, iclass 19, count 2 2006.173.17:36:39.32#ibcon#about to write, iclass 19, count 2 2006.173.17:36:39.32#ibcon#wrote, iclass 19, count 2 2006.173.17:36:39.32#ibcon#about to read 3, iclass 19, count 2 2006.173.17:36:39.34#ibcon#read 3, iclass 19, count 2 2006.173.17:36:39.34#ibcon#about to read 4, iclass 19, count 2 2006.173.17:36:39.34#ibcon#read 4, iclass 19, count 2 2006.173.17:36:39.34#ibcon#about to read 5, iclass 19, count 2 2006.173.17:36:39.34#ibcon#read 5, iclass 19, count 2 2006.173.17:36:39.34#ibcon#about to read 6, iclass 19, count 2 2006.173.17:36:39.34#ibcon#read 6, iclass 19, count 2 2006.173.17:36:39.34#ibcon#end of sib2, iclass 19, count 2 2006.173.17:36:39.34#ibcon#*mode == 0, iclass 19, count 2 2006.173.17:36:39.34#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.17:36:39.34#ibcon#[25=AT01-07\r\n] 2006.173.17:36:39.34#ibcon#*before write, iclass 19, count 2 2006.173.17:36:39.34#ibcon#enter sib2, iclass 19, count 2 2006.173.17:36:39.34#ibcon#flushed, iclass 19, count 2 2006.173.17:36:39.34#ibcon#about to write, iclass 19, count 2 2006.173.17:36:39.34#ibcon#wrote, iclass 19, count 2 2006.173.17:36:39.34#ibcon#about to read 3, iclass 19, count 2 2006.173.17:36:39.37#ibcon#read 3, iclass 19, count 2 2006.173.17:36:39.37#ibcon#about to read 4, iclass 19, count 2 2006.173.17:36:39.37#ibcon#read 4, iclass 19, count 2 2006.173.17:36:39.37#ibcon#about to read 5, iclass 19, count 2 2006.173.17:36:39.37#ibcon#read 5, iclass 19, count 2 2006.173.17:36:39.37#ibcon#about to read 6, iclass 19, count 2 2006.173.17:36:39.37#ibcon#read 6, iclass 19, count 2 2006.173.17:36:39.37#ibcon#end of sib2, iclass 19, count 2 2006.173.17:36:39.37#ibcon#*after write, iclass 19, count 2 2006.173.17:36:39.37#ibcon#*before return 0, iclass 19, count 2 2006.173.17:36:39.37#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.17:36:39.37#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.17:36:39.37#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.17:36:39.37#ibcon#ireg 7 cls_cnt 0 2006.173.17:36:39.37#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.17:36:39.49#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.17:36:39.49#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.17:36:39.49#ibcon#enter wrdev, iclass 19, count 0 2006.173.17:36:39.49#ibcon#first serial, iclass 19, count 0 2006.173.17:36:39.49#ibcon#enter sib2, iclass 19, count 0 2006.173.17:36:39.49#ibcon#flushed, iclass 19, count 0 2006.173.17:36:39.49#ibcon#about to write, iclass 19, count 0 2006.173.17:36:39.49#ibcon#wrote, iclass 19, count 0 2006.173.17:36:39.49#ibcon#about to read 3, iclass 19, count 0 2006.173.17:36:39.51#ibcon#read 3, iclass 19, count 0 2006.173.17:36:39.51#ibcon#about to read 4, iclass 19, count 0 2006.173.17:36:39.51#ibcon#read 4, iclass 19, count 0 2006.173.17:36:39.51#ibcon#about to read 5, iclass 19, count 0 2006.173.17:36:39.51#ibcon#read 5, iclass 19, count 0 2006.173.17:36:39.51#ibcon#about to read 6, iclass 19, count 0 2006.173.17:36:39.51#ibcon#read 6, iclass 19, count 0 2006.173.17:36:39.51#ibcon#end of sib2, iclass 19, count 0 2006.173.17:36:39.51#ibcon#*mode == 0, iclass 19, count 0 2006.173.17:36:39.51#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.17:36:39.51#ibcon#[25=USB\r\n] 2006.173.17:36:39.51#ibcon#*before write, iclass 19, count 0 2006.173.17:36:39.51#ibcon#enter sib2, iclass 19, count 0 2006.173.17:36:39.51#ibcon#flushed, iclass 19, count 0 2006.173.17:36:39.51#ibcon#about to write, iclass 19, count 0 2006.173.17:36:39.51#ibcon#wrote, iclass 19, count 0 2006.173.17:36:39.51#ibcon#about to read 3, iclass 19, count 0 2006.173.17:36:39.54#ibcon#read 3, iclass 19, count 0 2006.173.17:36:39.54#ibcon#about to read 4, iclass 19, count 0 2006.173.17:36:39.54#ibcon#read 4, iclass 19, count 0 2006.173.17:36:39.54#ibcon#about to read 5, iclass 19, count 0 2006.173.17:36:39.54#ibcon#read 5, iclass 19, count 0 2006.173.17:36:39.54#ibcon#about to read 6, iclass 19, count 0 2006.173.17:36:39.54#ibcon#read 6, iclass 19, count 0 2006.173.17:36:39.54#ibcon#end of sib2, iclass 19, count 0 2006.173.17:36:39.54#ibcon#*after write, iclass 19, count 0 2006.173.17:36:39.54#ibcon#*before return 0, iclass 19, count 0 2006.173.17:36:39.54#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.17:36:39.54#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.17:36:39.54#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.17:36:39.54#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.17:36:39.54$vck44/valo=2,534.99 2006.173.17:36:39.54#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.17:36:39.54#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.17:36:39.54#ibcon#ireg 17 cls_cnt 0 2006.173.17:36:39.54#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.17:36:39.54#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.17:36:39.54#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.17:36:39.54#ibcon#enter wrdev, iclass 21, count 0 2006.173.17:36:39.54#ibcon#first serial, iclass 21, count 0 2006.173.17:36:39.54#ibcon#enter sib2, iclass 21, count 0 2006.173.17:36:39.54#ibcon#flushed, iclass 21, count 0 2006.173.17:36:39.54#ibcon#about to write, iclass 21, count 0 2006.173.17:36:39.54#ibcon#wrote, iclass 21, count 0 2006.173.17:36:39.54#ibcon#about to read 3, iclass 21, count 0 2006.173.17:36:39.56#ibcon#read 3, iclass 21, count 0 2006.173.17:36:39.56#ibcon#about to read 4, iclass 21, count 0 2006.173.17:36:39.56#ibcon#read 4, iclass 21, count 0 2006.173.17:36:39.56#ibcon#about to read 5, iclass 21, count 0 2006.173.17:36:39.56#ibcon#read 5, iclass 21, count 0 2006.173.17:36:39.56#ibcon#about to read 6, iclass 21, count 0 2006.173.17:36:39.56#ibcon#read 6, iclass 21, count 0 2006.173.17:36:39.56#ibcon#end of sib2, iclass 21, count 0 2006.173.17:36:39.56#ibcon#*mode == 0, iclass 21, count 0 2006.173.17:36:39.56#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.17:36:39.56#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.17:36:39.56#ibcon#*before write, iclass 21, count 0 2006.173.17:36:39.56#ibcon#enter sib2, iclass 21, count 0 2006.173.17:36:39.56#ibcon#flushed, iclass 21, count 0 2006.173.17:36:39.56#ibcon#about to write, iclass 21, count 0 2006.173.17:36:39.56#ibcon#wrote, iclass 21, count 0 2006.173.17:36:39.56#ibcon#about to read 3, iclass 21, count 0 2006.173.17:36:39.61#ibcon#read 3, iclass 21, count 0 2006.173.17:36:39.61#ibcon#about to read 4, iclass 21, count 0 2006.173.17:36:39.61#ibcon#read 4, iclass 21, count 0 2006.173.17:36:39.61#ibcon#about to read 5, iclass 21, count 0 2006.173.17:36:39.61#ibcon#read 5, iclass 21, count 0 2006.173.17:36:39.61#ibcon#about to read 6, iclass 21, count 0 2006.173.17:36:39.61#ibcon#read 6, iclass 21, count 0 2006.173.17:36:39.61#ibcon#end of sib2, iclass 21, count 0 2006.173.17:36:39.61#ibcon#*after write, iclass 21, count 0 2006.173.17:36:39.61#ibcon#*before return 0, iclass 21, count 0 2006.173.17:36:39.61#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.17:36:39.61#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.17:36:39.61#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.17:36:39.61#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.17:36:39.61$vck44/va=2,6 2006.173.17:36:39.61#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.17:36:39.61#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.17:36:39.61#ibcon#ireg 11 cls_cnt 2 2006.173.17:36:39.61#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.17:36:39.65#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.17:36:39.65#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.17:36:39.65#ibcon#enter wrdev, iclass 23, count 2 2006.173.17:36:39.65#ibcon#first serial, iclass 23, count 2 2006.173.17:36:39.65#ibcon#enter sib2, iclass 23, count 2 2006.173.17:36:39.65#ibcon#flushed, iclass 23, count 2 2006.173.17:36:39.65#ibcon#about to write, iclass 23, count 2 2006.173.17:36:39.65#ibcon#wrote, iclass 23, count 2 2006.173.17:36:39.65#ibcon#about to read 3, iclass 23, count 2 2006.173.17:36:39.67#ibcon#read 3, iclass 23, count 2 2006.173.17:36:39.67#ibcon#about to read 4, iclass 23, count 2 2006.173.17:36:39.67#ibcon#read 4, iclass 23, count 2 2006.173.17:36:39.67#ibcon#about to read 5, iclass 23, count 2 2006.173.17:36:39.67#ibcon#read 5, iclass 23, count 2 2006.173.17:36:39.67#ibcon#about to read 6, iclass 23, count 2 2006.173.17:36:39.67#ibcon#read 6, iclass 23, count 2 2006.173.17:36:39.67#ibcon#end of sib2, iclass 23, count 2 2006.173.17:36:39.67#ibcon#*mode == 0, iclass 23, count 2 2006.173.17:36:39.67#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.17:36:39.67#ibcon#[25=AT02-06\r\n] 2006.173.17:36:39.67#ibcon#*before write, iclass 23, count 2 2006.173.17:36:39.67#ibcon#enter sib2, iclass 23, count 2 2006.173.17:36:39.67#ibcon#flushed, iclass 23, count 2 2006.173.17:36:39.67#ibcon#about to write, iclass 23, count 2 2006.173.17:36:39.67#ibcon#wrote, iclass 23, count 2 2006.173.17:36:39.67#ibcon#about to read 3, iclass 23, count 2 2006.173.17:36:39.70#ibcon#read 3, iclass 23, count 2 2006.173.17:36:39.70#ibcon#about to read 4, iclass 23, count 2 2006.173.17:36:39.70#ibcon#read 4, iclass 23, count 2 2006.173.17:36:39.70#ibcon#about to read 5, iclass 23, count 2 2006.173.17:36:39.70#ibcon#read 5, iclass 23, count 2 2006.173.17:36:39.70#ibcon#about to read 6, iclass 23, count 2 2006.173.17:36:39.70#ibcon#read 6, iclass 23, count 2 2006.173.17:36:39.70#ibcon#end of sib2, iclass 23, count 2 2006.173.17:36:39.70#ibcon#*after write, iclass 23, count 2 2006.173.17:36:39.70#ibcon#*before return 0, iclass 23, count 2 2006.173.17:36:39.70#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.17:36:39.70#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.17:36:39.70#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.17:36:39.70#ibcon#ireg 7 cls_cnt 0 2006.173.17:36:39.70#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.17:36:39.82#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.17:36:39.82#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.17:36:39.82#ibcon#enter wrdev, iclass 23, count 0 2006.173.17:36:39.82#ibcon#first serial, iclass 23, count 0 2006.173.17:36:39.82#ibcon#enter sib2, iclass 23, count 0 2006.173.17:36:39.82#ibcon#flushed, iclass 23, count 0 2006.173.17:36:39.82#ibcon#about to write, iclass 23, count 0 2006.173.17:36:39.82#ibcon#wrote, iclass 23, count 0 2006.173.17:36:39.82#ibcon#about to read 3, iclass 23, count 0 2006.173.17:36:39.84#ibcon#read 3, iclass 23, count 0 2006.173.17:36:39.84#ibcon#about to read 4, iclass 23, count 0 2006.173.17:36:39.84#ibcon#read 4, iclass 23, count 0 2006.173.17:36:39.84#ibcon#about to read 5, iclass 23, count 0 2006.173.17:36:39.84#ibcon#read 5, iclass 23, count 0 2006.173.17:36:39.84#ibcon#about to read 6, iclass 23, count 0 2006.173.17:36:39.84#ibcon#read 6, iclass 23, count 0 2006.173.17:36:39.84#ibcon#end of sib2, iclass 23, count 0 2006.173.17:36:39.84#ibcon#*mode == 0, iclass 23, count 0 2006.173.17:36:39.84#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.17:36:39.84#ibcon#[25=USB\r\n] 2006.173.17:36:39.84#ibcon#*before write, iclass 23, count 0 2006.173.17:36:39.84#ibcon#enter sib2, iclass 23, count 0 2006.173.17:36:39.84#ibcon#flushed, iclass 23, count 0 2006.173.17:36:39.84#ibcon#about to write, iclass 23, count 0 2006.173.17:36:39.84#ibcon#wrote, iclass 23, count 0 2006.173.17:36:39.84#ibcon#about to read 3, iclass 23, count 0 2006.173.17:36:39.87#ibcon#read 3, iclass 23, count 0 2006.173.17:36:39.87#ibcon#about to read 4, iclass 23, count 0 2006.173.17:36:39.87#ibcon#read 4, iclass 23, count 0 2006.173.17:36:39.87#ibcon#about to read 5, iclass 23, count 0 2006.173.17:36:39.87#ibcon#read 5, iclass 23, count 0 2006.173.17:36:39.87#ibcon#about to read 6, iclass 23, count 0 2006.173.17:36:39.87#ibcon#read 6, iclass 23, count 0 2006.173.17:36:39.87#ibcon#end of sib2, iclass 23, count 0 2006.173.17:36:39.87#ibcon#*after write, iclass 23, count 0 2006.173.17:36:39.87#ibcon#*before return 0, iclass 23, count 0 2006.173.17:36:39.87#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.17:36:39.87#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.17:36:39.87#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.17:36:39.87#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.17:36:39.87$vck44/valo=3,564.99 2006.173.17:36:39.87#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.17:36:39.87#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.17:36:39.87#ibcon#ireg 17 cls_cnt 0 2006.173.17:36:39.87#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.17:36:39.87#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.17:36:39.87#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.17:36:39.87#ibcon#enter wrdev, iclass 25, count 0 2006.173.17:36:39.87#ibcon#first serial, iclass 25, count 0 2006.173.17:36:39.87#ibcon#enter sib2, iclass 25, count 0 2006.173.17:36:39.87#ibcon#flushed, iclass 25, count 0 2006.173.17:36:39.87#ibcon#about to write, iclass 25, count 0 2006.173.17:36:39.87#ibcon#wrote, iclass 25, count 0 2006.173.17:36:39.87#ibcon#about to read 3, iclass 25, count 0 2006.173.17:36:39.89#ibcon#read 3, iclass 25, count 0 2006.173.17:36:39.89#ibcon#about to read 4, iclass 25, count 0 2006.173.17:36:39.89#ibcon#read 4, iclass 25, count 0 2006.173.17:36:39.89#ibcon#about to read 5, iclass 25, count 0 2006.173.17:36:39.89#ibcon#read 5, iclass 25, count 0 2006.173.17:36:39.89#ibcon#about to read 6, iclass 25, count 0 2006.173.17:36:39.89#ibcon#read 6, iclass 25, count 0 2006.173.17:36:39.89#ibcon#end of sib2, iclass 25, count 0 2006.173.17:36:39.89#ibcon#*mode == 0, iclass 25, count 0 2006.173.17:36:39.89#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.17:36:39.89#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.17:36:39.89#ibcon#*before write, iclass 25, count 0 2006.173.17:36:39.89#ibcon#enter sib2, iclass 25, count 0 2006.173.17:36:39.89#ibcon#flushed, iclass 25, count 0 2006.173.17:36:39.89#ibcon#about to write, iclass 25, count 0 2006.173.17:36:39.89#ibcon#wrote, iclass 25, count 0 2006.173.17:36:39.89#ibcon#about to read 3, iclass 25, count 0 2006.173.17:36:39.93#ibcon#read 3, iclass 25, count 0 2006.173.17:36:39.93#ibcon#about to read 4, iclass 25, count 0 2006.173.17:36:39.93#ibcon#read 4, iclass 25, count 0 2006.173.17:36:39.93#ibcon#about to read 5, iclass 25, count 0 2006.173.17:36:39.93#ibcon#read 5, iclass 25, count 0 2006.173.17:36:39.93#ibcon#about to read 6, iclass 25, count 0 2006.173.17:36:39.93#ibcon#read 6, iclass 25, count 0 2006.173.17:36:39.93#ibcon#end of sib2, iclass 25, count 0 2006.173.17:36:39.93#ibcon#*after write, iclass 25, count 0 2006.173.17:36:39.93#ibcon#*before return 0, iclass 25, count 0 2006.173.17:36:39.93#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.17:36:39.93#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.17:36:39.93#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.17:36:39.93#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.17:36:39.93$vck44/va=3,5 2006.173.17:36:39.93#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.17:36:39.93#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.17:36:39.93#ibcon#ireg 11 cls_cnt 2 2006.173.17:36:39.93#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.17:36:39.99#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.17:36:39.99#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.17:36:39.99#ibcon#enter wrdev, iclass 27, count 2 2006.173.17:36:39.99#ibcon#first serial, iclass 27, count 2 2006.173.17:36:39.99#ibcon#enter sib2, iclass 27, count 2 2006.173.17:36:39.99#ibcon#flushed, iclass 27, count 2 2006.173.17:36:39.99#ibcon#about to write, iclass 27, count 2 2006.173.17:36:39.99#ibcon#wrote, iclass 27, count 2 2006.173.17:36:39.99#ibcon#about to read 3, iclass 27, count 2 2006.173.17:36:40.01#ibcon#read 3, iclass 27, count 2 2006.173.17:36:40.01#ibcon#about to read 4, iclass 27, count 2 2006.173.17:36:40.01#ibcon#read 4, iclass 27, count 2 2006.173.17:36:40.01#ibcon#about to read 5, iclass 27, count 2 2006.173.17:36:40.01#ibcon#read 5, iclass 27, count 2 2006.173.17:36:40.01#ibcon#about to read 6, iclass 27, count 2 2006.173.17:36:40.01#ibcon#read 6, iclass 27, count 2 2006.173.17:36:40.01#ibcon#end of sib2, iclass 27, count 2 2006.173.17:36:40.01#ibcon#*mode == 0, iclass 27, count 2 2006.173.17:36:40.01#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.17:36:40.01#ibcon#[25=AT03-05\r\n] 2006.173.17:36:40.01#ibcon#*before write, iclass 27, count 2 2006.173.17:36:40.01#ibcon#enter sib2, iclass 27, count 2 2006.173.17:36:40.01#ibcon#flushed, iclass 27, count 2 2006.173.17:36:40.01#ibcon#about to write, iclass 27, count 2 2006.173.17:36:40.01#ibcon#wrote, iclass 27, count 2 2006.173.17:36:40.01#ibcon#about to read 3, iclass 27, count 2 2006.173.17:36:40.04#ibcon#read 3, iclass 27, count 2 2006.173.17:36:40.04#ibcon#about to read 4, iclass 27, count 2 2006.173.17:36:40.04#ibcon#read 4, iclass 27, count 2 2006.173.17:36:40.04#ibcon#about to read 5, iclass 27, count 2 2006.173.17:36:40.04#ibcon#read 5, iclass 27, count 2 2006.173.17:36:40.04#ibcon#about to read 6, iclass 27, count 2 2006.173.17:36:40.04#ibcon#read 6, iclass 27, count 2 2006.173.17:36:40.04#ibcon#end of sib2, iclass 27, count 2 2006.173.17:36:40.04#ibcon#*after write, iclass 27, count 2 2006.173.17:36:40.04#ibcon#*before return 0, iclass 27, count 2 2006.173.17:36:40.04#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.17:36:40.04#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.17:36:40.04#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.17:36:40.04#ibcon#ireg 7 cls_cnt 0 2006.173.17:36:40.04#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.17:36:40.16#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.17:36:40.16#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.17:36:40.16#ibcon#enter wrdev, iclass 27, count 0 2006.173.17:36:40.16#ibcon#first serial, iclass 27, count 0 2006.173.17:36:40.16#ibcon#enter sib2, iclass 27, count 0 2006.173.17:36:40.16#ibcon#flushed, iclass 27, count 0 2006.173.17:36:40.16#ibcon#about to write, iclass 27, count 0 2006.173.17:36:40.16#ibcon#wrote, iclass 27, count 0 2006.173.17:36:40.16#ibcon#about to read 3, iclass 27, count 0 2006.173.17:36:40.18#ibcon#read 3, iclass 27, count 0 2006.173.17:36:40.18#ibcon#about to read 4, iclass 27, count 0 2006.173.17:36:40.18#ibcon#read 4, iclass 27, count 0 2006.173.17:36:40.18#ibcon#about to read 5, iclass 27, count 0 2006.173.17:36:40.18#ibcon#read 5, iclass 27, count 0 2006.173.17:36:40.18#ibcon#about to read 6, iclass 27, count 0 2006.173.17:36:40.18#ibcon#read 6, iclass 27, count 0 2006.173.17:36:40.18#ibcon#end of sib2, iclass 27, count 0 2006.173.17:36:40.18#ibcon#*mode == 0, iclass 27, count 0 2006.173.17:36:40.18#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.17:36:40.18#ibcon#[25=USB\r\n] 2006.173.17:36:40.18#ibcon#*before write, iclass 27, count 0 2006.173.17:36:40.18#ibcon#enter sib2, iclass 27, count 0 2006.173.17:36:40.18#ibcon#flushed, iclass 27, count 0 2006.173.17:36:40.18#ibcon#about to write, iclass 27, count 0 2006.173.17:36:40.18#ibcon#wrote, iclass 27, count 0 2006.173.17:36:40.18#ibcon#about to read 3, iclass 27, count 0 2006.173.17:36:40.21#ibcon#read 3, iclass 27, count 0 2006.173.17:36:40.21#ibcon#about to read 4, iclass 27, count 0 2006.173.17:36:40.21#ibcon#read 4, iclass 27, count 0 2006.173.17:36:40.21#ibcon#about to read 5, iclass 27, count 0 2006.173.17:36:40.21#ibcon#read 5, iclass 27, count 0 2006.173.17:36:40.21#ibcon#about to read 6, iclass 27, count 0 2006.173.17:36:40.21#ibcon#read 6, iclass 27, count 0 2006.173.17:36:40.21#ibcon#end of sib2, iclass 27, count 0 2006.173.17:36:40.21#ibcon#*after write, iclass 27, count 0 2006.173.17:36:40.21#ibcon#*before return 0, iclass 27, count 0 2006.173.17:36:40.21#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.17:36:40.21#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.17:36:40.21#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.17:36:40.21#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.17:36:40.21$vck44/valo=4,624.99 2006.173.17:36:40.21#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.17:36:40.21#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.17:36:40.21#ibcon#ireg 17 cls_cnt 0 2006.173.17:36:40.21#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.17:36:40.21#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.17:36:40.21#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.17:36:40.21#ibcon#enter wrdev, iclass 29, count 0 2006.173.17:36:40.21#ibcon#first serial, iclass 29, count 0 2006.173.17:36:40.21#ibcon#enter sib2, iclass 29, count 0 2006.173.17:36:40.21#ibcon#flushed, iclass 29, count 0 2006.173.17:36:40.21#ibcon#about to write, iclass 29, count 0 2006.173.17:36:40.21#ibcon#wrote, iclass 29, count 0 2006.173.17:36:40.21#ibcon#about to read 3, iclass 29, count 0 2006.173.17:36:40.23#ibcon#read 3, iclass 29, count 0 2006.173.17:36:40.23#ibcon#about to read 4, iclass 29, count 0 2006.173.17:36:40.23#ibcon#read 4, iclass 29, count 0 2006.173.17:36:40.23#ibcon#about to read 5, iclass 29, count 0 2006.173.17:36:40.23#ibcon#read 5, iclass 29, count 0 2006.173.17:36:40.23#ibcon#about to read 6, iclass 29, count 0 2006.173.17:36:40.23#ibcon#read 6, iclass 29, count 0 2006.173.17:36:40.23#ibcon#end of sib2, iclass 29, count 0 2006.173.17:36:40.23#ibcon#*mode == 0, iclass 29, count 0 2006.173.17:36:40.23#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.17:36:40.23#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.17:36:40.23#ibcon#*before write, iclass 29, count 0 2006.173.17:36:40.23#ibcon#enter sib2, iclass 29, count 0 2006.173.17:36:40.23#ibcon#flushed, iclass 29, count 0 2006.173.17:36:40.23#ibcon#about to write, iclass 29, count 0 2006.173.17:36:40.23#ibcon#wrote, iclass 29, count 0 2006.173.17:36:40.23#ibcon#about to read 3, iclass 29, count 0 2006.173.17:36:40.27#ibcon#read 3, iclass 29, count 0 2006.173.17:36:40.27#ibcon#about to read 4, iclass 29, count 0 2006.173.17:36:40.27#ibcon#read 4, iclass 29, count 0 2006.173.17:36:40.27#ibcon#about to read 5, iclass 29, count 0 2006.173.17:36:40.27#ibcon#read 5, iclass 29, count 0 2006.173.17:36:40.27#ibcon#about to read 6, iclass 29, count 0 2006.173.17:36:40.27#ibcon#read 6, iclass 29, count 0 2006.173.17:36:40.27#ibcon#end of sib2, iclass 29, count 0 2006.173.17:36:40.27#ibcon#*after write, iclass 29, count 0 2006.173.17:36:40.27#ibcon#*before return 0, iclass 29, count 0 2006.173.17:36:40.27#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.17:36:40.27#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.17:36:40.27#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.17:36:40.27#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.17:36:40.27$vck44/va=4,6 2006.173.17:36:40.27#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.17:36:40.27#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.17:36:40.27#ibcon#ireg 11 cls_cnt 2 2006.173.17:36:40.27#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.17:36:40.33#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.17:36:40.33#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.17:36:40.33#ibcon#enter wrdev, iclass 31, count 2 2006.173.17:36:40.33#ibcon#first serial, iclass 31, count 2 2006.173.17:36:40.33#ibcon#enter sib2, iclass 31, count 2 2006.173.17:36:40.33#ibcon#flushed, iclass 31, count 2 2006.173.17:36:40.33#ibcon#about to write, iclass 31, count 2 2006.173.17:36:40.33#ibcon#wrote, iclass 31, count 2 2006.173.17:36:40.33#ibcon#about to read 3, iclass 31, count 2 2006.173.17:36:40.35#ibcon#read 3, iclass 31, count 2 2006.173.17:36:40.35#ibcon#about to read 4, iclass 31, count 2 2006.173.17:36:40.35#ibcon#read 4, iclass 31, count 2 2006.173.17:36:40.35#ibcon#about to read 5, iclass 31, count 2 2006.173.17:36:40.35#ibcon#read 5, iclass 31, count 2 2006.173.17:36:40.35#ibcon#about to read 6, iclass 31, count 2 2006.173.17:36:40.35#ibcon#read 6, iclass 31, count 2 2006.173.17:36:40.35#ibcon#end of sib2, iclass 31, count 2 2006.173.17:36:40.35#ibcon#*mode == 0, iclass 31, count 2 2006.173.17:36:40.35#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.17:36:40.35#ibcon#[25=AT04-06\r\n] 2006.173.17:36:40.35#ibcon#*before write, iclass 31, count 2 2006.173.17:36:40.35#ibcon#enter sib2, iclass 31, count 2 2006.173.17:36:40.35#ibcon#flushed, iclass 31, count 2 2006.173.17:36:40.35#ibcon#about to write, iclass 31, count 2 2006.173.17:36:40.35#ibcon#wrote, iclass 31, count 2 2006.173.17:36:40.35#ibcon#about to read 3, iclass 31, count 2 2006.173.17:36:40.38#ibcon#read 3, iclass 31, count 2 2006.173.17:36:40.38#ibcon#about to read 4, iclass 31, count 2 2006.173.17:36:40.38#ibcon#read 4, iclass 31, count 2 2006.173.17:36:40.38#ibcon#about to read 5, iclass 31, count 2 2006.173.17:36:40.38#ibcon#read 5, iclass 31, count 2 2006.173.17:36:40.38#ibcon#about to read 6, iclass 31, count 2 2006.173.17:36:40.38#ibcon#read 6, iclass 31, count 2 2006.173.17:36:40.38#ibcon#end of sib2, iclass 31, count 2 2006.173.17:36:40.38#ibcon#*after write, iclass 31, count 2 2006.173.17:36:40.38#ibcon#*before return 0, iclass 31, count 2 2006.173.17:36:40.38#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.17:36:40.38#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.17:36:40.38#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.17:36:40.38#ibcon#ireg 7 cls_cnt 0 2006.173.17:36:40.38#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.17:36:40.50#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.17:36:40.50#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.17:36:40.50#ibcon#enter wrdev, iclass 31, count 0 2006.173.17:36:40.50#ibcon#first serial, iclass 31, count 0 2006.173.17:36:40.50#ibcon#enter sib2, iclass 31, count 0 2006.173.17:36:40.50#ibcon#flushed, iclass 31, count 0 2006.173.17:36:40.50#ibcon#about to write, iclass 31, count 0 2006.173.17:36:40.50#ibcon#wrote, iclass 31, count 0 2006.173.17:36:40.50#ibcon#about to read 3, iclass 31, count 0 2006.173.17:36:40.52#ibcon#read 3, iclass 31, count 0 2006.173.17:36:40.52#ibcon#about to read 4, iclass 31, count 0 2006.173.17:36:40.52#ibcon#read 4, iclass 31, count 0 2006.173.17:36:40.52#ibcon#about to read 5, iclass 31, count 0 2006.173.17:36:40.52#ibcon#read 5, iclass 31, count 0 2006.173.17:36:40.52#ibcon#about to read 6, iclass 31, count 0 2006.173.17:36:40.52#ibcon#read 6, iclass 31, count 0 2006.173.17:36:40.52#ibcon#end of sib2, iclass 31, count 0 2006.173.17:36:40.52#ibcon#*mode == 0, iclass 31, count 0 2006.173.17:36:40.52#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.17:36:40.52#ibcon#[25=USB\r\n] 2006.173.17:36:40.52#ibcon#*before write, iclass 31, count 0 2006.173.17:36:40.52#ibcon#enter sib2, iclass 31, count 0 2006.173.17:36:40.52#ibcon#flushed, iclass 31, count 0 2006.173.17:36:40.52#ibcon#about to write, iclass 31, count 0 2006.173.17:36:40.52#ibcon#wrote, iclass 31, count 0 2006.173.17:36:40.52#ibcon#about to read 3, iclass 31, count 0 2006.173.17:36:40.55#ibcon#read 3, iclass 31, count 0 2006.173.17:36:40.55#ibcon#about to read 4, iclass 31, count 0 2006.173.17:36:40.55#ibcon#read 4, iclass 31, count 0 2006.173.17:36:40.55#ibcon#about to read 5, iclass 31, count 0 2006.173.17:36:40.55#ibcon#read 5, iclass 31, count 0 2006.173.17:36:40.55#ibcon#about to read 6, iclass 31, count 0 2006.173.17:36:40.55#ibcon#read 6, iclass 31, count 0 2006.173.17:36:40.55#ibcon#end of sib2, iclass 31, count 0 2006.173.17:36:40.55#ibcon#*after write, iclass 31, count 0 2006.173.17:36:40.55#ibcon#*before return 0, iclass 31, count 0 2006.173.17:36:40.55#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.17:36:40.55#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.17:36:40.55#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.17:36:40.55#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.17:36:40.55$vck44/valo=5,734.99 2006.173.17:36:40.55#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.17:36:40.55#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.17:36:40.55#ibcon#ireg 17 cls_cnt 0 2006.173.17:36:40.55#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.17:36:40.55#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.17:36:40.55#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.17:36:40.55#ibcon#enter wrdev, iclass 33, count 0 2006.173.17:36:40.55#ibcon#first serial, iclass 33, count 0 2006.173.17:36:40.55#ibcon#enter sib2, iclass 33, count 0 2006.173.17:36:40.55#ibcon#flushed, iclass 33, count 0 2006.173.17:36:40.55#ibcon#about to write, iclass 33, count 0 2006.173.17:36:40.55#ibcon#wrote, iclass 33, count 0 2006.173.17:36:40.55#ibcon#about to read 3, iclass 33, count 0 2006.173.17:36:40.57#ibcon#read 3, iclass 33, count 0 2006.173.17:36:40.57#ibcon#about to read 4, iclass 33, count 0 2006.173.17:36:40.57#ibcon#read 4, iclass 33, count 0 2006.173.17:36:40.57#ibcon#about to read 5, iclass 33, count 0 2006.173.17:36:40.57#ibcon#read 5, iclass 33, count 0 2006.173.17:36:40.57#ibcon#about to read 6, iclass 33, count 0 2006.173.17:36:40.57#ibcon#read 6, iclass 33, count 0 2006.173.17:36:40.57#ibcon#end of sib2, iclass 33, count 0 2006.173.17:36:40.57#ibcon#*mode == 0, iclass 33, count 0 2006.173.17:36:40.57#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.17:36:40.57#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.17:36:40.57#ibcon#*before write, iclass 33, count 0 2006.173.17:36:40.57#ibcon#enter sib2, iclass 33, count 0 2006.173.17:36:40.57#ibcon#flushed, iclass 33, count 0 2006.173.17:36:40.57#ibcon#about to write, iclass 33, count 0 2006.173.17:36:40.57#ibcon#wrote, iclass 33, count 0 2006.173.17:36:40.57#ibcon#about to read 3, iclass 33, count 0 2006.173.17:36:40.61#ibcon#read 3, iclass 33, count 0 2006.173.17:36:40.61#ibcon#about to read 4, iclass 33, count 0 2006.173.17:36:40.61#ibcon#read 4, iclass 33, count 0 2006.173.17:36:40.61#ibcon#about to read 5, iclass 33, count 0 2006.173.17:36:40.61#ibcon#read 5, iclass 33, count 0 2006.173.17:36:40.61#ibcon#about to read 6, iclass 33, count 0 2006.173.17:36:40.61#ibcon#read 6, iclass 33, count 0 2006.173.17:36:40.61#ibcon#end of sib2, iclass 33, count 0 2006.173.17:36:40.61#ibcon#*after write, iclass 33, count 0 2006.173.17:36:40.61#ibcon#*before return 0, iclass 33, count 0 2006.173.17:36:40.61#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.17:36:40.61#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.17:36:40.61#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.17:36:40.61#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.17:36:40.61$vck44/va=5,4 2006.173.17:36:40.61#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.17:36:40.61#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.17:36:40.61#ibcon#ireg 11 cls_cnt 2 2006.173.17:36:40.61#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.17:36:40.67#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.17:36:40.67#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.17:36:40.67#ibcon#enter wrdev, iclass 35, count 2 2006.173.17:36:40.67#ibcon#first serial, iclass 35, count 2 2006.173.17:36:40.67#ibcon#enter sib2, iclass 35, count 2 2006.173.17:36:40.67#ibcon#flushed, iclass 35, count 2 2006.173.17:36:40.67#ibcon#about to write, iclass 35, count 2 2006.173.17:36:40.67#ibcon#wrote, iclass 35, count 2 2006.173.17:36:40.67#ibcon#about to read 3, iclass 35, count 2 2006.173.17:36:40.69#ibcon#read 3, iclass 35, count 2 2006.173.17:36:40.69#ibcon#about to read 4, iclass 35, count 2 2006.173.17:36:40.69#ibcon#read 4, iclass 35, count 2 2006.173.17:36:40.69#ibcon#about to read 5, iclass 35, count 2 2006.173.17:36:40.69#ibcon#read 5, iclass 35, count 2 2006.173.17:36:40.69#ibcon#about to read 6, iclass 35, count 2 2006.173.17:36:40.69#ibcon#read 6, iclass 35, count 2 2006.173.17:36:40.69#ibcon#end of sib2, iclass 35, count 2 2006.173.17:36:40.69#ibcon#*mode == 0, iclass 35, count 2 2006.173.17:36:40.69#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.17:36:40.69#ibcon#[25=AT05-04\r\n] 2006.173.17:36:40.69#ibcon#*before write, iclass 35, count 2 2006.173.17:36:40.69#ibcon#enter sib2, iclass 35, count 2 2006.173.17:36:40.69#ibcon#flushed, iclass 35, count 2 2006.173.17:36:40.69#ibcon#about to write, iclass 35, count 2 2006.173.17:36:40.69#ibcon#wrote, iclass 35, count 2 2006.173.17:36:40.69#ibcon#about to read 3, iclass 35, count 2 2006.173.17:36:40.72#ibcon#read 3, iclass 35, count 2 2006.173.17:36:40.72#ibcon#about to read 4, iclass 35, count 2 2006.173.17:36:40.72#ibcon#read 4, iclass 35, count 2 2006.173.17:36:40.72#ibcon#about to read 5, iclass 35, count 2 2006.173.17:36:40.72#ibcon#read 5, iclass 35, count 2 2006.173.17:36:40.72#ibcon#about to read 6, iclass 35, count 2 2006.173.17:36:40.72#ibcon#read 6, iclass 35, count 2 2006.173.17:36:40.72#ibcon#end of sib2, iclass 35, count 2 2006.173.17:36:40.72#ibcon#*after write, iclass 35, count 2 2006.173.17:36:40.72#ibcon#*before return 0, iclass 35, count 2 2006.173.17:36:40.72#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.17:36:40.72#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.17:36:40.72#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.17:36:40.72#ibcon#ireg 7 cls_cnt 0 2006.173.17:36:40.72#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.17:36:40.84#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.17:36:40.84#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.17:36:40.84#ibcon#enter wrdev, iclass 35, count 0 2006.173.17:36:40.84#ibcon#first serial, iclass 35, count 0 2006.173.17:36:40.84#ibcon#enter sib2, iclass 35, count 0 2006.173.17:36:40.84#ibcon#flushed, iclass 35, count 0 2006.173.17:36:40.84#ibcon#about to write, iclass 35, count 0 2006.173.17:36:40.84#ibcon#wrote, iclass 35, count 0 2006.173.17:36:40.84#ibcon#about to read 3, iclass 35, count 0 2006.173.17:36:40.86#ibcon#read 3, iclass 35, count 0 2006.173.17:36:40.86#ibcon#about to read 4, iclass 35, count 0 2006.173.17:36:40.86#ibcon#read 4, iclass 35, count 0 2006.173.17:36:40.86#ibcon#about to read 5, iclass 35, count 0 2006.173.17:36:40.86#ibcon#read 5, iclass 35, count 0 2006.173.17:36:40.86#ibcon#about to read 6, iclass 35, count 0 2006.173.17:36:40.86#ibcon#read 6, iclass 35, count 0 2006.173.17:36:40.86#ibcon#end of sib2, iclass 35, count 0 2006.173.17:36:40.86#ibcon#*mode == 0, iclass 35, count 0 2006.173.17:36:40.86#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.17:36:40.86#ibcon#[25=USB\r\n] 2006.173.17:36:40.86#ibcon#*before write, iclass 35, count 0 2006.173.17:36:40.86#ibcon#enter sib2, iclass 35, count 0 2006.173.17:36:40.86#ibcon#flushed, iclass 35, count 0 2006.173.17:36:40.86#ibcon#about to write, iclass 35, count 0 2006.173.17:36:40.86#ibcon#wrote, iclass 35, count 0 2006.173.17:36:40.86#ibcon#about to read 3, iclass 35, count 0 2006.173.17:36:40.89#ibcon#read 3, iclass 35, count 0 2006.173.17:36:40.89#ibcon#about to read 4, iclass 35, count 0 2006.173.17:36:40.89#ibcon#read 4, iclass 35, count 0 2006.173.17:36:40.89#ibcon#about to read 5, iclass 35, count 0 2006.173.17:36:40.89#ibcon#read 5, iclass 35, count 0 2006.173.17:36:40.89#ibcon#about to read 6, iclass 35, count 0 2006.173.17:36:40.89#ibcon#read 6, iclass 35, count 0 2006.173.17:36:40.89#ibcon#end of sib2, iclass 35, count 0 2006.173.17:36:40.89#ibcon#*after write, iclass 35, count 0 2006.173.17:36:40.89#ibcon#*before return 0, iclass 35, count 0 2006.173.17:36:40.89#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.17:36:40.89#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.17:36:40.89#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.17:36:40.89#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.17:36:40.89$vck44/valo=6,814.99 2006.173.17:36:40.89#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.17:36:40.89#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.17:36:40.89#ibcon#ireg 17 cls_cnt 0 2006.173.17:36:40.89#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.17:36:40.89#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.17:36:40.89#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.17:36:40.89#ibcon#enter wrdev, iclass 37, count 0 2006.173.17:36:40.89#ibcon#first serial, iclass 37, count 0 2006.173.17:36:40.89#ibcon#enter sib2, iclass 37, count 0 2006.173.17:36:40.89#ibcon#flushed, iclass 37, count 0 2006.173.17:36:40.89#ibcon#about to write, iclass 37, count 0 2006.173.17:36:40.89#ibcon#wrote, iclass 37, count 0 2006.173.17:36:40.89#ibcon#about to read 3, iclass 37, count 0 2006.173.17:36:40.91#ibcon#read 3, iclass 37, count 0 2006.173.17:36:40.91#ibcon#about to read 4, iclass 37, count 0 2006.173.17:36:40.91#ibcon#read 4, iclass 37, count 0 2006.173.17:36:40.91#ibcon#about to read 5, iclass 37, count 0 2006.173.17:36:40.91#ibcon#read 5, iclass 37, count 0 2006.173.17:36:40.91#ibcon#about to read 6, iclass 37, count 0 2006.173.17:36:40.91#ibcon#read 6, iclass 37, count 0 2006.173.17:36:40.91#ibcon#end of sib2, iclass 37, count 0 2006.173.17:36:40.91#ibcon#*mode == 0, iclass 37, count 0 2006.173.17:36:40.91#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.17:36:40.91#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.17:36:40.91#ibcon#*before write, iclass 37, count 0 2006.173.17:36:40.91#ibcon#enter sib2, iclass 37, count 0 2006.173.17:36:40.91#ibcon#flushed, iclass 37, count 0 2006.173.17:36:40.91#ibcon#about to write, iclass 37, count 0 2006.173.17:36:40.91#ibcon#wrote, iclass 37, count 0 2006.173.17:36:40.91#ibcon#about to read 3, iclass 37, count 0 2006.173.17:36:40.95#ibcon#read 3, iclass 37, count 0 2006.173.17:36:40.95#ibcon#about to read 4, iclass 37, count 0 2006.173.17:36:40.95#ibcon#read 4, iclass 37, count 0 2006.173.17:36:40.95#ibcon#about to read 5, iclass 37, count 0 2006.173.17:36:40.95#ibcon#read 5, iclass 37, count 0 2006.173.17:36:40.95#ibcon#about to read 6, iclass 37, count 0 2006.173.17:36:40.95#ibcon#read 6, iclass 37, count 0 2006.173.17:36:40.95#ibcon#end of sib2, iclass 37, count 0 2006.173.17:36:40.95#ibcon#*after write, iclass 37, count 0 2006.173.17:36:40.95#ibcon#*before return 0, iclass 37, count 0 2006.173.17:36:40.95#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.17:36:40.95#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.17:36:40.95#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.17:36:40.95#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.17:36:40.95$vck44/va=6,3 2006.173.17:36:40.95#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.17:36:40.95#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.17:36:40.95#ibcon#ireg 11 cls_cnt 2 2006.173.17:36:40.95#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.17:36:41.01#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.17:36:41.01#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.17:36:41.01#ibcon#enter wrdev, iclass 39, count 2 2006.173.17:36:41.01#ibcon#first serial, iclass 39, count 2 2006.173.17:36:41.01#ibcon#enter sib2, iclass 39, count 2 2006.173.17:36:41.01#ibcon#flushed, iclass 39, count 2 2006.173.17:36:41.01#ibcon#about to write, iclass 39, count 2 2006.173.17:36:41.01#ibcon#wrote, iclass 39, count 2 2006.173.17:36:41.01#ibcon#about to read 3, iclass 39, count 2 2006.173.17:36:41.03#ibcon#read 3, iclass 39, count 2 2006.173.17:36:41.03#ibcon#about to read 4, iclass 39, count 2 2006.173.17:36:41.03#ibcon#read 4, iclass 39, count 2 2006.173.17:36:41.03#ibcon#about to read 5, iclass 39, count 2 2006.173.17:36:41.03#ibcon#read 5, iclass 39, count 2 2006.173.17:36:41.03#ibcon#about to read 6, iclass 39, count 2 2006.173.17:36:41.03#ibcon#read 6, iclass 39, count 2 2006.173.17:36:41.03#ibcon#end of sib2, iclass 39, count 2 2006.173.17:36:41.03#ibcon#*mode == 0, iclass 39, count 2 2006.173.17:36:41.03#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.17:36:41.03#ibcon#[25=AT06-03\r\n] 2006.173.17:36:41.03#ibcon#*before write, iclass 39, count 2 2006.173.17:36:41.03#ibcon#enter sib2, iclass 39, count 2 2006.173.17:36:41.03#ibcon#flushed, iclass 39, count 2 2006.173.17:36:41.03#ibcon#about to write, iclass 39, count 2 2006.173.17:36:41.03#ibcon#wrote, iclass 39, count 2 2006.173.17:36:41.03#ibcon#about to read 3, iclass 39, count 2 2006.173.17:36:41.06#ibcon#read 3, iclass 39, count 2 2006.173.17:36:41.06#ibcon#about to read 4, iclass 39, count 2 2006.173.17:36:41.06#ibcon#read 4, iclass 39, count 2 2006.173.17:36:41.06#ibcon#about to read 5, iclass 39, count 2 2006.173.17:36:41.06#ibcon#read 5, iclass 39, count 2 2006.173.17:36:41.06#ibcon#about to read 6, iclass 39, count 2 2006.173.17:36:41.06#ibcon#read 6, iclass 39, count 2 2006.173.17:36:41.06#ibcon#end of sib2, iclass 39, count 2 2006.173.17:36:41.06#ibcon#*after write, iclass 39, count 2 2006.173.17:36:41.06#ibcon#*before return 0, iclass 39, count 2 2006.173.17:36:41.06#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.17:36:41.06#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.17:36:41.06#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.17:36:41.06#ibcon#ireg 7 cls_cnt 0 2006.173.17:36:41.06#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.17:36:41.18#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.17:36:41.18#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.17:36:41.18#ibcon#enter wrdev, iclass 39, count 0 2006.173.17:36:41.18#ibcon#first serial, iclass 39, count 0 2006.173.17:36:41.18#ibcon#enter sib2, iclass 39, count 0 2006.173.17:36:41.18#ibcon#flushed, iclass 39, count 0 2006.173.17:36:41.18#ibcon#about to write, iclass 39, count 0 2006.173.17:36:41.18#ibcon#wrote, iclass 39, count 0 2006.173.17:36:41.18#ibcon#about to read 3, iclass 39, count 0 2006.173.17:36:41.20#ibcon#read 3, iclass 39, count 0 2006.173.17:36:41.20#ibcon#about to read 4, iclass 39, count 0 2006.173.17:36:41.20#ibcon#read 4, iclass 39, count 0 2006.173.17:36:41.20#ibcon#about to read 5, iclass 39, count 0 2006.173.17:36:41.20#ibcon#read 5, iclass 39, count 0 2006.173.17:36:41.20#ibcon#about to read 6, iclass 39, count 0 2006.173.17:36:41.20#ibcon#read 6, iclass 39, count 0 2006.173.17:36:41.20#ibcon#end of sib2, iclass 39, count 0 2006.173.17:36:41.20#ibcon#*mode == 0, iclass 39, count 0 2006.173.17:36:41.20#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.17:36:41.20#ibcon#[25=USB\r\n] 2006.173.17:36:41.20#ibcon#*before write, iclass 39, count 0 2006.173.17:36:41.20#ibcon#enter sib2, iclass 39, count 0 2006.173.17:36:41.20#ibcon#flushed, iclass 39, count 0 2006.173.17:36:41.20#ibcon#about to write, iclass 39, count 0 2006.173.17:36:41.20#ibcon#wrote, iclass 39, count 0 2006.173.17:36:41.20#ibcon#about to read 3, iclass 39, count 0 2006.173.17:36:41.23#ibcon#read 3, iclass 39, count 0 2006.173.17:36:41.23#ibcon#about to read 4, iclass 39, count 0 2006.173.17:36:41.23#ibcon#read 4, iclass 39, count 0 2006.173.17:36:41.23#ibcon#about to read 5, iclass 39, count 0 2006.173.17:36:41.23#ibcon#read 5, iclass 39, count 0 2006.173.17:36:41.23#ibcon#about to read 6, iclass 39, count 0 2006.173.17:36:41.23#ibcon#read 6, iclass 39, count 0 2006.173.17:36:41.23#ibcon#end of sib2, iclass 39, count 0 2006.173.17:36:41.23#ibcon#*after write, iclass 39, count 0 2006.173.17:36:41.23#ibcon#*before return 0, iclass 39, count 0 2006.173.17:36:41.23#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.17:36:41.23#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.17:36:41.23#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.17:36:41.23#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.17:36:41.23$vck44/valo=7,864.99 2006.173.17:36:41.23#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.17:36:41.23#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.17:36:41.23#ibcon#ireg 17 cls_cnt 0 2006.173.17:36:41.23#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.17:36:41.23#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.17:36:41.23#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.17:36:41.23#ibcon#enter wrdev, iclass 3, count 0 2006.173.17:36:41.23#ibcon#first serial, iclass 3, count 0 2006.173.17:36:41.23#ibcon#enter sib2, iclass 3, count 0 2006.173.17:36:41.23#ibcon#flushed, iclass 3, count 0 2006.173.17:36:41.23#ibcon#about to write, iclass 3, count 0 2006.173.17:36:41.23#ibcon#wrote, iclass 3, count 0 2006.173.17:36:41.23#ibcon#about to read 3, iclass 3, count 0 2006.173.17:36:41.25#ibcon#read 3, iclass 3, count 0 2006.173.17:36:41.25#ibcon#about to read 4, iclass 3, count 0 2006.173.17:36:41.25#ibcon#read 4, iclass 3, count 0 2006.173.17:36:41.25#ibcon#about to read 5, iclass 3, count 0 2006.173.17:36:41.25#ibcon#read 5, iclass 3, count 0 2006.173.17:36:41.25#ibcon#about to read 6, iclass 3, count 0 2006.173.17:36:41.25#ibcon#read 6, iclass 3, count 0 2006.173.17:36:41.25#ibcon#end of sib2, iclass 3, count 0 2006.173.17:36:41.25#ibcon#*mode == 0, iclass 3, count 0 2006.173.17:36:41.25#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.17:36:41.25#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.17:36:41.25#ibcon#*before write, iclass 3, count 0 2006.173.17:36:41.25#ibcon#enter sib2, iclass 3, count 0 2006.173.17:36:41.25#ibcon#flushed, iclass 3, count 0 2006.173.17:36:41.25#ibcon#about to write, iclass 3, count 0 2006.173.17:36:41.25#ibcon#wrote, iclass 3, count 0 2006.173.17:36:41.25#ibcon#about to read 3, iclass 3, count 0 2006.173.17:36:41.29#ibcon#read 3, iclass 3, count 0 2006.173.17:36:41.29#ibcon#about to read 4, iclass 3, count 0 2006.173.17:36:41.29#ibcon#read 4, iclass 3, count 0 2006.173.17:36:41.29#ibcon#about to read 5, iclass 3, count 0 2006.173.17:36:41.29#ibcon#read 5, iclass 3, count 0 2006.173.17:36:41.29#ibcon#about to read 6, iclass 3, count 0 2006.173.17:36:41.29#ibcon#read 6, iclass 3, count 0 2006.173.17:36:41.29#ibcon#end of sib2, iclass 3, count 0 2006.173.17:36:41.29#ibcon#*after write, iclass 3, count 0 2006.173.17:36:41.29#ibcon#*before return 0, iclass 3, count 0 2006.173.17:36:41.29#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.17:36:41.29#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.17:36:41.29#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.17:36:41.29#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.17:36:41.29$vck44/va=7,4 2006.173.17:36:41.29#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.17:36:41.29#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.17:36:41.29#ibcon#ireg 11 cls_cnt 2 2006.173.17:36:41.29#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.17:36:41.35#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.17:36:41.35#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.17:36:41.35#ibcon#enter wrdev, iclass 5, count 2 2006.173.17:36:41.35#ibcon#first serial, iclass 5, count 2 2006.173.17:36:41.35#ibcon#enter sib2, iclass 5, count 2 2006.173.17:36:41.35#ibcon#flushed, iclass 5, count 2 2006.173.17:36:41.35#ibcon#about to write, iclass 5, count 2 2006.173.17:36:41.35#ibcon#wrote, iclass 5, count 2 2006.173.17:36:41.35#ibcon#about to read 3, iclass 5, count 2 2006.173.17:36:41.37#ibcon#read 3, iclass 5, count 2 2006.173.17:36:41.37#ibcon#about to read 4, iclass 5, count 2 2006.173.17:36:41.37#ibcon#read 4, iclass 5, count 2 2006.173.17:36:41.37#ibcon#about to read 5, iclass 5, count 2 2006.173.17:36:41.37#ibcon#read 5, iclass 5, count 2 2006.173.17:36:41.37#ibcon#about to read 6, iclass 5, count 2 2006.173.17:36:41.37#ibcon#read 6, iclass 5, count 2 2006.173.17:36:41.37#ibcon#end of sib2, iclass 5, count 2 2006.173.17:36:41.37#ibcon#*mode == 0, iclass 5, count 2 2006.173.17:36:41.37#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.17:36:41.37#ibcon#[25=AT07-04\r\n] 2006.173.17:36:41.37#ibcon#*before write, iclass 5, count 2 2006.173.17:36:41.37#ibcon#enter sib2, iclass 5, count 2 2006.173.17:36:41.37#ibcon#flushed, iclass 5, count 2 2006.173.17:36:41.37#ibcon#about to write, iclass 5, count 2 2006.173.17:36:41.37#ibcon#wrote, iclass 5, count 2 2006.173.17:36:41.37#ibcon#about to read 3, iclass 5, count 2 2006.173.17:36:41.40#ibcon#read 3, iclass 5, count 2 2006.173.17:36:41.40#ibcon#about to read 4, iclass 5, count 2 2006.173.17:36:41.40#ibcon#read 4, iclass 5, count 2 2006.173.17:36:41.40#ibcon#about to read 5, iclass 5, count 2 2006.173.17:36:41.40#ibcon#read 5, iclass 5, count 2 2006.173.17:36:41.40#ibcon#about to read 6, iclass 5, count 2 2006.173.17:36:41.40#ibcon#read 6, iclass 5, count 2 2006.173.17:36:41.40#ibcon#end of sib2, iclass 5, count 2 2006.173.17:36:41.40#ibcon#*after write, iclass 5, count 2 2006.173.17:36:41.40#ibcon#*before return 0, iclass 5, count 2 2006.173.17:36:41.40#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.17:36:41.40#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.17:36:41.40#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.17:36:41.40#ibcon#ireg 7 cls_cnt 0 2006.173.17:36:41.40#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.17:36:41.52#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.17:36:41.52#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.17:36:41.52#ibcon#enter wrdev, iclass 5, count 0 2006.173.17:36:41.52#ibcon#first serial, iclass 5, count 0 2006.173.17:36:41.52#ibcon#enter sib2, iclass 5, count 0 2006.173.17:36:41.52#ibcon#flushed, iclass 5, count 0 2006.173.17:36:41.52#ibcon#about to write, iclass 5, count 0 2006.173.17:36:41.52#ibcon#wrote, iclass 5, count 0 2006.173.17:36:41.52#ibcon#about to read 3, iclass 5, count 0 2006.173.17:36:41.54#ibcon#read 3, iclass 5, count 0 2006.173.17:36:41.54#ibcon#about to read 4, iclass 5, count 0 2006.173.17:36:41.54#ibcon#read 4, iclass 5, count 0 2006.173.17:36:41.54#ibcon#about to read 5, iclass 5, count 0 2006.173.17:36:41.54#ibcon#read 5, iclass 5, count 0 2006.173.17:36:41.54#ibcon#about to read 6, iclass 5, count 0 2006.173.17:36:41.54#ibcon#read 6, iclass 5, count 0 2006.173.17:36:41.54#ibcon#end of sib2, iclass 5, count 0 2006.173.17:36:41.54#ibcon#*mode == 0, iclass 5, count 0 2006.173.17:36:41.54#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.17:36:41.54#ibcon#[25=USB\r\n] 2006.173.17:36:41.54#ibcon#*before write, iclass 5, count 0 2006.173.17:36:41.54#ibcon#enter sib2, iclass 5, count 0 2006.173.17:36:41.54#ibcon#flushed, iclass 5, count 0 2006.173.17:36:41.54#ibcon#about to write, iclass 5, count 0 2006.173.17:36:41.54#ibcon#wrote, iclass 5, count 0 2006.173.17:36:41.54#ibcon#about to read 3, iclass 5, count 0 2006.173.17:36:41.57#ibcon#read 3, iclass 5, count 0 2006.173.17:36:41.57#ibcon#about to read 4, iclass 5, count 0 2006.173.17:36:41.57#ibcon#read 4, iclass 5, count 0 2006.173.17:36:41.57#ibcon#about to read 5, iclass 5, count 0 2006.173.17:36:41.57#ibcon#read 5, iclass 5, count 0 2006.173.17:36:41.57#ibcon#about to read 6, iclass 5, count 0 2006.173.17:36:41.57#ibcon#read 6, iclass 5, count 0 2006.173.17:36:41.57#ibcon#end of sib2, iclass 5, count 0 2006.173.17:36:41.57#ibcon#*after write, iclass 5, count 0 2006.173.17:36:41.57#ibcon#*before return 0, iclass 5, count 0 2006.173.17:36:41.57#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.17:36:41.57#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.17:36:41.57#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.17:36:41.57#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.17:36:41.57$vck44/valo=8,884.99 2006.173.17:36:41.57#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.17:36:41.57#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.17:36:41.57#ibcon#ireg 17 cls_cnt 0 2006.173.17:36:41.57#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.17:36:41.57#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.17:36:41.57#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.17:36:41.57#ibcon#enter wrdev, iclass 7, count 0 2006.173.17:36:41.57#ibcon#first serial, iclass 7, count 0 2006.173.17:36:41.57#ibcon#enter sib2, iclass 7, count 0 2006.173.17:36:41.57#ibcon#flushed, iclass 7, count 0 2006.173.17:36:41.57#ibcon#about to write, iclass 7, count 0 2006.173.17:36:41.57#ibcon#wrote, iclass 7, count 0 2006.173.17:36:41.57#ibcon#about to read 3, iclass 7, count 0 2006.173.17:36:41.59#ibcon#read 3, iclass 7, count 0 2006.173.17:36:41.59#ibcon#about to read 4, iclass 7, count 0 2006.173.17:36:41.59#ibcon#read 4, iclass 7, count 0 2006.173.17:36:41.59#ibcon#about to read 5, iclass 7, count 0 2006.173.17:36:41.59#ibcon#read 5, iclass 7, count 0 2006.173.17:36:41.59#ibcon#about to read 6, iclass 7, count 0 2006.173.17:36:41.59#ibcon#read 6, iclass 7, count 0 2006.173.17:36:41.59#ibcon#end of sib2, iclass 7, count 0 2006.173.17:36:41.59#ibcon#*mode == 0, iclass 7, count 0 2006.173.17:36:41.59#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.17:36:41.59#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.17:36:41.59#ibcon#*before write, iclass 7, count 0 2006.173.17:36:41.59#ibcon#enter sib2, iclass 7, count 0 2006.173.17:36:41.59#ibcon#flushed, iclass 7, count 0 2006.173.17:36:41.59#ibcon#about to write, iclass 7, count 0 2006.173.17:36:41.59#ibcon#wrote, iclass 7, count 0 2006.173.17:36:41.59#ibcon#about to read 3, iclass 7, count 0 2006.173.17:36:41.63#ibcon#read 3, iclass 7, count 0 2006.173.17:36:41.63#ibcon#about to read 4, iclass 7, count 0 2006.173.17:36:41.63#ibcon#read 4, iclass 7, count 0 2006.173.17:36:41.63#ibcon#about to read 5, iclass 7, count 0 2006.173.17:36:41.63#ibcon#read 5, iclass 7, count 0 2006.173.17:36:41.63#ibcon#about to read 6, iclass 7, count 0 2006.173.17:36:41.63#ibcon#read 6, iclass 7, count 0 2006.173.17:36:41.63#ibcon#end of sib2, iclass 7, count 0 2006.173.17:36:41.63#ibcon#*after write, iclass 7, count 0 2006.173.17:36:41.63#ibcon#*before return 0, iclass 7, count 0 2006.173.17:36:41.63#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.17:36:41.63#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.17:36:41.63#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.17:36:41.63#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.17:36:41.63$vck44/va=8,4 2006.173.17:36:41.63#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.17:36:41.63#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.17:36:41.63#ibcon#ireg 11 cls_cnt 2 2006.173.17:36:41.63#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.17:36:41.69#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.17:36:41.69#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.17:36:41.69#ibcon#enter wrdev, iclass 11, count 2 2006.173.17:36:41.69#ibcon#first serial, iclass 11, count 2 2006.173.17:36:41.69#ibcon#enter sib2, iclass 11, count 2 2006.173.17:36:41.69#ibcon#flushed, iclass 11, count 2 2006.173.17:36:41.69#ibcon#about to write, iclass 11, count 2 2006.173.17:36:41.69#ibcon#wrote, iclass 11, count 2 2006.173.17:36:41.69#ibcon#about to read 3, iclass 11, count 2 2006.173.17:36:41.71#ibcon#read 3, iclass 11, count 2 2006.173.17:36:41.71#ibcon#about to read 4, iclass 11, count 2 2006.173.17:36:41.71#ibcon#read 4, iclass 11, count 2 2006.173.17:36:41.71#ibcon#about to read 5, iclass 11, count 2 2006.173.17:36:41.71#ibcon#read 5, iclass 11, count 2 2006.173.17:36:41.71#ibcon#about to read 6, iclass 11, count 2 2006.173.17:36:41.71#ibcon#read 6, iclass 11, count 2 2006.173.17:36:41.71#ibcon#end of sib2, iclass 11, count 2 2006.173.17:36:41.71#ibcon#*mode == 0, iclass 11, count 2 2006.173.17:36:41.71#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.17:36:41.71#ibcon#[25=AT08-04\r\n] 2006.173.17:36:41.71#ibcon#*before write, iclass 11, count 2 2006.173.17:36:41.71#ibcon#enter sib2, iclass 11, count 2 2006.173.17:36:41.71#ibcon#flushed, iclass 11, count 2 2006.173.17:36:41.71#ibcon#about to write, iclass 11, count 2 2006.173.17:36:41.71#ibcon#wrote, iclass 11, count 2 2006.173.17:36:41.71#ibcon#about to read 3, iclass 11, count 2 2006.173.17:36:41.74#ibcon#read 3, iclass 11, count 2 2006.173.17:36:41.74#ibcon#about to read 4, iclass 11, count 2 2006.173.17:36:41.74#ibcon#read 4, iclass 11, count 2 2006.173.17:36:41.74#ibcon#about to read 5, iclass 11, count 2 2006.173.17:36:41.74#ibcon#read 5, iclass 11, count 2 2006.173.17:36:41.74#ibcon#about to read 6, iclass 11, count 2 2006.173.17:36:41.74#ibcon#read 6, iclass 11, count 2 2006.173.17:36:41.74#ibcon#end of sib2, iclass 11, count 2 2006.173.17:36:41.74#ibcon#*after write, iclass 11, count 2 2006.173.17:36:41.74#ibcon#*before return 0, iclass 11, count 2 2006.173.17:36:41.74#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.17:36:41.74#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.17:36:41.74#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.17:36:41.74#ibcon#ireg 7 cls_cnt 0 2006.173.17:36:41.74#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.17:36:41.86#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.17:36:41.86#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.17:36:41.86#ibcon#enter wrdev, iclass 11, count 0 2006.173.17:36:41.86#ibcon#first serial, iclass 11, count 0 2006.173.17:36:41.86#ibcon#enter sib2, iclass 11, count 0 2006.173.17:36:41.86#ibcon#flushed, iclass 11, count 0 2006.173.17:36:41.86#ibcon#about to write, iclass 11, count 0 2006.173.17:36:41.86#ibcon#wrote, iclass 11, count 0 2006.173.17:36:41.86#ibcon#about to read 3, iclass 11, count 0 2006.173.17:36:41.88#ibcon#read 3, iclass 11, count 0 2006.173.17:36:41.88#ibcon#about to read 4, iclass 11, count 0 2006.173.17:36:41.88#ibcon#read 4, iclass 11, count 0 2006.173.17:36:41.88#ibcon#about to read 5, iclass 11, count 0 2006.173.17:36:41.88#ibcon#read 5, iclass 11, count 0 2006.173.17:36:41.88#ibcon#about to read 6, iclass 11, count 0 2006.173.17:36:41.88#ibcon#read 6, iclass 11, count 0 2006.173.17:36:41.88#ibcon#end of sib2, iclass 11, count 0 2006.173.17:36:41.88#ibcon#*mode == 0, iclass 11, count 0 2006.173.17:36:41.88#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.17:36:41.88#ibcon#[25=USB\r\n] 2006.173.17:36:41.88#ibcon#*before write, iclass 11, count 0 2006.173.17:36:41.88#ibcon#enter sib2, iclass 11, count 0 2006.173.17:36:41.88#ibcon#flushed, iclass 11, count 0 2006.173.17:36:41.88#ibcon#about to write, iclass 11, count 0 2006.173.17:36:41.88#ibcon#wrote, iclass 11, count 0 2006.173.17:36:41.88#ibcon#about to read 3, iclass 11, count 0 2006.173.17:36:41.91#ibcon#read 3, iclass 11, count 0 2006.173.17:36:41.91#ibcon#about to read 4, iclass 11, count 0 2006.173.17:36:41.91#ibcon#read 4, iclass 11, count 0 2006.173.17:36:41.91#ibcon#about to read 5, iclass 11, count 0 2006.173.17:36:41.91#ibcon#read 5, iclass 11, count 0 2006.173.17:36:41.91#ibcon#about to read 6, iclass 11, count 0 2006.173.17:36:41.91#ibcon#read 6, iclass 11, count 0 2006.173.17:36:41.91#ibcon#end of sib2, iclass 11, count 0 2006.173.17:36:41.91#ibcon#*after write, iclass 11, count 0 2006.173.17:36:41.91#ibcon#*before return 0, iclass 11, count 0 2006.173.17:36:41.91#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.17:36:41.91#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.17:36:41.91#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.17:36:41.91#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.17:36:41.91$vck44/vblo=1,629.99 2006.173.17:36:41.91#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.17:36:41.91#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.17:36:41.91#ibcon#ireg 17 cls_cnt 0 2006.173.17:36:41.91#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.17:36:41.91#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.17:36:41.91#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.17:36:41.91#ibcon#enter wrdev, iclass 13, count 0 2006.173.17:36:41.91#ibcon#first serial, iclass 13, count 0 2006.173.17:36:41.91#ibcon#enter sib2, iclass 13, count 0 2006.173.17:36:41.91#ibcon#flushed, iclass 13, count 0 2006.173.17:36:41.91#ibcon#about to write, iclass 13, count 0 2006.173.17:36:41.91#ibcon#wrote, iclass 13, count 0 2006.173.17:36:41.91#ibcon#about to read 3, iclass 13, count 0 2006.173.17:36:41.93#ibcon#read 3, iclass 13, count 0 2006.173.17:36:41.93#ibcon#about to read 4, iclass 13, count 0 2006.173.17:36:41.93#ibcon#read 4, iclass 13, count 0 2006.173.17:36:41.93#ibcon#about to read 5, iclass 13, count 0 2006.173.17:36:41.93#ibcon#read 5, iclass 13, count 0 2006.173.17:36:41.93#ibcon#about to read 6, iclass 13, count 0 2006.173.17:36:41.93#ibcon#read 6, iclass 13, count 0 2006.173.17:36:41.93#ibcon#end of sib2, iclass 13, count 0 2006.173.17:36:41.93#ibcon#*mode == 0, iclass 13, count 0 2006.173.17:36:41.93#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.17:36:41.93#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.17:36:41.93#ibcon#*before write, iclass 13, count 0 2006.173.17:36:41.93#ibcon#enter sib2, iclass 13, count 0 2006.173.17:36:41.93#ibcon#flushed, iclass 13, count 0 2006.173.17:36:41.93#ibcon#about to write, iclass 13, count 0 2006.173.17:36:41.93#ibcon#wrote, iclass 13, count 0 2006.173.17:36:41.93#ibcon#about to read 3, iclass 13, count 0 2006.173.17:36:41.97#ibcon#read 3, iclass 13, count 0 2006.173.17:36:41.97#ibcon#about to read 4, iclass 13, count 0 2006.173.17:36:41.97#ibcon#read 4, iclass 13, count 0 2006.173.17:36:41.97#ibcon#about to read 5, iclass 13, count 0 2006.173.17:36:41.97#ibcon#read 5, iclass 13, count 0 2006.173.17:36:41.97#ibcon#about to read 6, iclass 13, count 0 2006.173.17:36:41.97#ibcon#read 6, iclass 13, count 0 2006.173.17:36:41.97#ibcon#end of sib2, iclass 13, count 0 2006.173.17:36:41.97#ibcon#*after write, iclass 13, count 0 2006.173.17:36:41.97#ibcon#*before return 0, iclass 13, count 0 2006.173.17:36:41.97#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.17:36:41.97#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.17:36:41.97#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.17:36:41.97#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.17:36:41.97$vck44/vb=1,4 2006.173.17:36:41.97#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.17:36:41.97#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.17:36:41.97#ibcon#ireg 11 cls_cnt 2 2006.173.17:36:41.97#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.17:36:41.97#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.17:36:41.97#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.17:36:41.97#ibcon#enter wrdev, iclass 15, count 2 2006.173.17:36:41.97#ibcon#first serial, iclass 15, count 2 2006.173.17:36:41.97#ibcon#enter sib2, iclass 15, count 2 2006.173.17:36:41.97#ibcon#flushed, iclass 15, count 2 2006.173.17:36:41.97#ibcon#about to write, iclass 15, count 2 2006.173.17:36:41.97#ibcon#wrote, iclass 15, count 2 2006.173.17:36:41.97#ibcon#about to read 3, iclass 15, count 2 2006.173.17:36:41.99#ibcon#read 3, iclass 15, count 2 2006.173.17:36:41.99#ibcon#about to read 4, iclass 15, count 2 2006.173.17:36:41.99#ibcon#read 4, iclass 15, count 2 2006.173.17:36:41.99#ibcon#about to read 5, iclass 15, count 2 2006.173.17:36:41.99#ibcon#read 5, iclass 15, count 2 2006.173.17:36:41.99#ibcon#about to read 6, iclass 15, count 2 2006.173.17:36:41.99#ibcon#read 6, iclass 15, count 2 2006.173.17:36:41.99#ibcon#end of sib2, iclass 15, count 2 2006.173.17:36:41.99#ibcon#*mode == 0, iclass 15, count 2 2006.173.17:36:41.99#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.17:36:41.99#ibcon#[27=AT01-04\r\n] 2006.173.17:36:41.99#ibcon#*before write, iclass 15, count 2 2006.173.17:36:41.99#ibcon#enter sib2, iclass 15, count 2 2006.173.17:36:41.99#ibcon#flushed, iclass 15, count 2 2006.173.17:36:41.99#ibcon#about to write, iclass 15, count 2 2006.173.17:36:41.99#ibcon#wrote, iclass 15, count 2 2006.173.17:36:41.99#ibcon#about to read 3, iclass 15, count 2 2006.173.17:36:42.02#ibcon#read 3, iclass 15, count 2 2006.173.17:36:42.02#ibcon#about to read 4, iclass 15, count 2 2006.173.17:36:42.02#ibcon#read 4, iclass 15, count 2 2006.173.17:36:42.02#ibcon#about to read 5, iclass 15, count 2 2006.173.17:36:42.02#ibcon#read 5, iclass 15, count 2 2006.173.17:36:42.02#ibcon#about to read 6, iclass 15, count 2 2006.173.17:36:42.02#ibcon#read 6, iclass 15, count 2 2006.173.17:36:42.02#ibcon#end of sib2, iclass 15, count 2 2006.173.17:36:42.02#ibcon#*after write, iclass 15, count 2 2006.173.17:36:42.02#ibcon#*before return 0, iclass 15, count 2 2006.173.17:36:42.02#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.17:36:42.02#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.17:36:42.02#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.17:36:42.02#ibcon#ireg 7 cls_cnt 0 2006.173.17:36:42.02#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.17:36:42.14#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.17:36:42.14#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.17:36:42.14#ibcon#enter wrdev, iclass 15, count 0 2006.173.17:36:42.14#ibcon#first serial, iclass 15, count 0 2006.173.17:36:42.14#ibcon#enter sib2, iclass 15, count 0 2006.173.17:36:42.14#ibcon#flushed, iclass 15, count 0 2006.173.17:36:42.14#ibcon#about to write, iclass 15, count 0 2006.173.17:36:42.14#ibcon#wrote, iclass 15, count 0 2006.173.17:36:42.14#ibcon#about to read 3, iclass 15, count 0 2006.173.17:36:42.16#ibcon#read 3, iclass 15, count 0 2006.173.17:36:42.16#ibcon#about to read 4, iclass 15, count 0 2006.173.17:36:42.16#ibcon#read 4, iclass 15, count 0 2006.173.17:36:42.16#ibcon#about to read 5, iclass 15, count 0 2006.173.17:36:42.16#ibcon#read 5, iclass 15, count 0 2006.173.17:36:42.16#ibcon#about to read 6, iclass 15, count 0 2006.173.17:36:42.16#ibcon#read 6, iclass 15, count 0 2006.173.17:36:42.16#ibcon#end of sib2, iclass 15, count 0 2006.173.17:36:42.16#ibcon#*mode == 0, iclass 15, count 0 2006.173.17:36:42.16#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.17:36:42.16#ibcon#[27=USB\r\n] 2006.173.17:36:42.16#ibcon#*before write, iclass 15, count 0 2006.173.17:36:42.16#ibcon#enter sib2, iclass 15, count 0 2006.173.17:36:42.16#ibcon#flushed, iclass 15, count 0 2006.173.17:36:42.16#ibcon#about to write, iclass 15, count 0 2006.173.17:36:42.16#ibcon#wrote, iclass 15, count 0 2006.173.17:36:42.16#ibcon#about to read 3, iclass 15, count 0 2006.173.17:36:42.19#ibcon#read 3, iclass 15, count 0 2006.173.17:36:42.19#ibcon#about to read 4, iclass 15, count 0 2006.173.17:36:42.19#ibcon#read 4, iclass 15, count 0 2006.173.17:36:42.19#ibcon#about to read 5, iclass 15, count 0 2006.173.17:36:42.19#ibcon#read 5, iclass 15, count 0 2006.173.17:36:42.19#ibcon#about to read 6, iclass 15, count 0 2006.173.17:36:42.19#ibcon#read 6, iclass 15, count 0 2006.173.17:36:42.19#ibcon#end of sib2, iclass 15, count 0 2006.173.17:36:42.19#ibcon#*after write, iclass 15, count 0 2006.173.17:36:42.19#ibcon#*before return 0, iclass 15, count 0 2006.173.17:36:42.19#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.17:36:42.19#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.17:36:42.19#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.17:36:42.19#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.17:36:42.19$vck44/vblo=2,634.99 2006.173.17:36:42.19#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.17:36:42.19#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.17:36:42.19#ibcon#ireg 17 cls_cnt 0 2006.173.17:36:42.19#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.17:36:42.19#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.17:36:42.19#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.17:36:42.19#ibcon#enter wrdev, iclass 17, count 0 2006.173.17:36:42.19#ibcon#first serial, iclass 17, count 0 2006.173.17:36:42.19#ibcon#enter sib2, iclass 17, count 0 2006.173.17:36:42.19#ibcon#flushed, iclass 17, count 0 2006.173.17:36:42.19#ibcon#about to write, iclass 17, count 0 2006.173.17:36:42.19#ibcon#wrote, iclass 17, count 0 2006.173.17:36:42.19#ibcon#about to read 3, iclass 17, count 0 2006.173.17:36:42.21#ibcon#read 3, iclass 17, count 0 2006.173.17:36:42.21#ibcon#about to read 4, iclass 17, count 0 2006.173.17:36:42.21#ibcon#read 4, iclass 17, count 0 2006.173.17:36:42.21#ibcon#about to read 5, iclass 17, count 0 2006.173.17:36:42.21#ibcon#read 5, iclass 17, count 0 2006.173.17:36:42.21#ibcon#about to read 6, iclass 17, count 0 2006.173.17:36:42.21#ibcon#read 6, iclass 17, count 0 2006.173.17:36:42.21#ibcon#end of sib2, iclass 17, count 0 2006.173.17:36:42.21#ibcon#*mode == 0, iclass 17, count 0 2006.173.17:36:42.21#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.17:36:42.21#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.17:36:42.21#ibcon#*before write, iclass 17, count 0 2006.173.17:36:42.21#ibcon#enter sib2, iclass 17, count 0 2006.173.17:36:42.21#ibcon#flushed, iclass 17, count 0 2006.173.17:36:42.21#ibcon#about to write, iclass 17, count 0 2006.173.17:36:42.21#ibcon#wrote, iclass 17, count 0 2006.173.17:36:42.21#ibcon#about to read 3, iclass 17, count 0 2006.173.17:36:42.25#ibcon#read 3, iclass 17, count 0 2006.173.17:36:42.25#ibcon#about to read 4, iclass 17, count 0 2006.173.17:36:42.25#ibcon#read 4, iclass 17, count 0 2006.173.17:36:42.25#ibcon#about to read 5, iclass 17, count 0 2006.173.17:36:42.25#ibcon#read 5, iclass 17, count 0 2006.173.17:36:42.25#ibcon#about to read 6, iclass 17, count 0 2006.173.17:36:42.25#ibcon#read 6, iclass 17, count 0 2006.173.17:36:42.25#ibcon#end of sib2, iclass 17, count 0 2006.173.17:36:42.25#ibcon#*after write, iclass 17, count 0 2006.173.17:36:42.25#ibcon#*before return 0, iclass 17, count 0 2006.173.17:36:42.25#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.17:36:42.25#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.17:36:42.25#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.17:36:42.25#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.17:36:42.25$vck44/vb=2,4 2006.173.17:36:42.25#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.17:36:42.25#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.17:36:42.25#ibcon#ireg 11 cls_cnt 2 2006.173.17:36:42.25#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.17:36:42.31#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.17:36:42.31#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.17:36:42.31#ibcon#enter wrdev, iclass 19, count 2 2006.173.17:36:42.31#ibcon#first serial, iclass 19, count 2 2006.173.17:36:42.31#ibcon#enter sib2, iclass 19, count 2 2006.173.17:36:42.31#ibcon#flushed, iclass 19, count 2 2006.173.17:36:42.31#ibcon#about to write, iclass 19, count 2 2006.173.17:36:42.31#ibcon#wrote, iclass 19, count 2 2006.173.17:36:42.31#ibcon#about to read 3, iclass 19, count 2 2006.173.17:36:42.33#ibcon#read 3, iclass 19, count 2 2006.173.17:36:42.33#ibcon#about to read 4, iclass 19, count 2 2006.173.17:36:42.33#ibcon#read 4, iclass 19, count 2 2006.173.17:36:42.33#ibcon#about to read 5, iclass 19, count 2 2006.173.17:36:42.33#ibcon#read 5, iclass 19, count 2 2006.173.17:36:42.33#ibcon#about to read 6, iclass 19, count 2 2006.173.17:36:42.33#ibcon#read 6, iclass 19, count 2 2006.173.17:36:42.33#ibcon#end of sib2, iclass 19, count 2 2006.173.17:36:42.33#ibcon#*mode == 0, iclass 19, count 2 2006.173.17:36:42.33#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.17:36:42.33#ibcon#[27=AT02-04\r\n] 2006.173.17:36:42.33#ibcon#*before write, iclass 19, count 2 2006.173.17:36:42.33#ibcon#enter sib2, iclass 19, count 2 2006.173.17:36:42.33#ibcon#flushed, iclass 19, count 2 2006.173.17:36:42.33#ibcon#about to write, iclass 19, count 2 2006.173.17:36:42.33#ibcon#wrote, iclass 19, count 2 2006.173.17:36:42.33#ibcon#about to read 3, iclass 19, count 2 2006.173.17:36:42.36#ibcon#read 3, iclass 19, count 2 2006.173.17:36:42.36#ibcon#about to read 4, iclass 19, count 2 2006.173.17:36:42.36#ibcon#read 4, iclass 19, count 2 2006.173.17:36:42.36#ibcon#about to read 5, iclass 19, count 2 2006.173.17:36:42.36#ibcon#read 5, iclass 19, count 2 2006.173.17:36:42.36#ibcon#about to read 6, iclass 19, count 2 2006.173.17:36:42.36#ibcon#read 6, iclass 19, count 2 2006.173.17:36:42.36#ibcon#end of sib2, iclass 19, count 2 2006.173.17:36:42.36#ibcon#*after write, iclass 19, count 2 2006.173.17:36:42.36#ibcon#*before return 0, iclass 19, count 2 2006.173.17:36:42.36#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.17:36:42.36#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.17:36:42.36#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.17:36:42.36#ibcon#ireg 7 cls_cnt 0 2006.173.17:36:42.36#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.17:36:42.48#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.17:36:42.48#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.17:36:42.48#ibcon#enter wrdev, iclass 19, count 0 2006.173.17:36:42.48#ibcon#first serial, iclass 19, count 0 2006.173.17:36:42.48#ibcon#enter sib2, iclass 19, count 0 2006.173.17:36:42.48#ibcon#flushed, iclass 19, count 0 2006.173.17:36:42.48#ibcon#about to write, iclass 19, count 0 2006.173.17:36:42.48#ibcon#wrote, iclass 19, count 0 2006.173.17:36:42.48#ibcon#about to read 3, iclass 19, count 0 2006.173.17:36:42.50#ibcon#read 3, iclass 19, count 0 2006.173.17:36:42.50#ibcon#about to read 4, iclass 19, count 0 2006.173.17:36:42.50#ibcon#read 4, iclass 19, count 0 2006.173.17:36:42.50#ibcon#about to read 5, iclass 19, count 0 2006.173.17:36:42.50#ibcon#read 5, iclass 19, count 0 2006.173.17:36:42.50#ibcon#about to read 6, iclass 19, count 0 2006.173.17:36:42.50#ibcon#read 6, iclass 19, count 0 2006.173.17:36:42.50#ibcon#end of sib2, iclass 19, count 0 2006.173.17:36:42.50#ibcon#*mode == 0, iclass 19, count 0 2006.173.17:36:42.50#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.17:36:42.50#ibcon#[27=USB\r\n] 2006.173.17:36:42.50#ibcon#*before write, iclass 19, count 0 2006.173.17:36:42.50#ibcon#enter sib2, iclass 19, count 0 2006.173.17:36:42.50#ibcon#flushed, iclass 19, count 0 2006.173.17:36:42.50#ibcon#about to write, iclass 19, count 0 2006.173.17:36:42.50#ibcon#wrote, iclass 19, count 0 2006.173.17:36:42.50#ibcon#about to read 3, iclass 19, count 0 2006.173.17:36:42.53#ibcon#read 3, iclass 19, count 0 2006.173.17:36:42.53#ibcon#about to read 4, iclass 19, count 0 2006.173.17:36:42.53#ibcon#read 4, iclass 19, count 0 2006.173.17:36:42.53#ibcon#about to read 5, iclass 19, count 0 2006.173.17:36:42.53#ibcon#read 5, iclass 19, count 0 2006.173.17:36:42.53#ibcon#about to read 6, iclass 19, count 0 2006.173.17:36:42.53#ibcon#read 6, iclass 19, count 0 2006.173.17:36:42.53#ibcon#end of sib2, iclass 19, count 0 2006.173.17:36:42.53#ibcon#*after write, iclass 19, count 0 2006.173.17:36:42.53#ibcon#*before return 0, iclass 19, count 0 2006.173.17:36:42.53#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.17:36:42.53#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.17:36:42.53#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.17:36:42.53#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.17:36:42.53$vck44/vblo=3,649.99 2006.173.17:36:42.53#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.17:36:42.53#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.17:36:42.53#ibcon#ireg 17 cls_cnt 0 2006.173.17:36:42.53#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.17:36:42.53#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.17:36:42.53#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.17:36:42.53#ibcon#enter wrdev, iclass 21, count 0 2006.173.17:36:42.53#ibcon#first serial, iclass 21, count 0 2006.173.17:36:42.53#ibcon#enter sib2, iclass 21, count 0 2006.173.17:36:42.53#ibcon#flushed, iclass 21, count 0 2006.173.17:36:42.53#ibcon#about to write, iclass 21, count 0 2006.173.17:36:42.53#ibcon#wrote, iclass 21, count 0 2006.173.17:36:42.53#ibcon#about to read 3, iclass 21, count 0 2006.173.17:36:42.55#ibcon#read 3, iclass 21, count 0 2006.173.17:36:42.55#ibcon#about to read 4, iclass 21, count 0 2006.173.17:36:42.55#ibcon#read 4, iclass 21, count 0 2006.173.17:36:42.55#ibcon#about to read 5, iclass 21, count 0 2006.173.17:36:42.55#ibcon#read 5, iclass 21, count 0 2006.173.17:36:42.55#ibcon#about to read 6, iclass 21, count 0 2006.173.17:36:42.55#ibcon#read 6, iclass 21, count 0 2006.173.17:36:42.55#ibcon#end of sib2, iclass 21, count 0 2006.173.17:36:42.55#ibcon#*mode == 0, iclass 21, count 0 2006.173.17:36:42.55#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.17:36:42.55#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.17:36:42.55#ibcon#*before write, iclass 21, count 0 2006.173.17:36:42.55#ibcon#enter sib2, iclass 21, count 0 2006.173.17:36:42.55#ibcon#flushed, iclass 21, count 0 2006.173.17:36:42.55#ibcon#about to write, iclass 21, count 0 2006.173.17:36:42.55#ibcon#wrote, iclass 21, count 0 2006.173.17:36:42.55#ibcon#about to read 3, iclass 21, count 0 2006.173.17:36:42.59#ibcon#read 3, iclass 21, count 0 2006.173.17:36:42.59#ibcon#about to read 4, iclass 21, count 0 2006.173.17:36:42.59#ibcon#read 4, iclass 21, count 0 2006.173.17:36:42.59#ibcon#about to read 5, iclass 21, count 0 2006.173.17:36:42.59#ibcon#read 5, iclass 21, count 0 2006.173.17:36:42.59#ibcon#about to read 6, iclass 21, count 0 2006.173.17:36:42.59#ibcon#read 6, iclass 21, count 0 2006.173.17:36:42.59#ibcon#end of sib2, iclass 21, count 0 2006.173.17:36:42.59#ibcon#*after write, iclass 21, count 0 2006.173.17:36:42.59#ibcon#*before return 0, iclass 21, count 0 2006.173.17:36:42.59#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.17:36:42.59#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.17:36:42.59#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.17:36:42.59#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.17:36:42.59$vck44/vb=3,4 2006.173.17:36:42.59#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.17:36:42.59#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.17:36:42.59#ibcon#ireg 11 cls_cnt 2 2006.173.17:36:42.59#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.17:36:42.65#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.17:36:42.65#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.17:36:42.65#ibcon#enter wrdev, iclass 23, count 2 2006.173.17:36:42.65#ibcon#first serial, iclass 23, count 2 2006.173.17:36:42.65#ibcon#enter sib2, iclass 23, count 2 2006.173.17:36:42.65#ibcon#flushed, iclass 23, count 2 2006.173.17:36:42.65#ibcon#about to write, iclass 23, count 2 2006.173.17:36:42.65#ibcon#wrote, iclass 23, count 2 2006.173.17:36:42.65#ibcon#about to read 3, iclass 23, count 2 2006.173.17:36:42.67#ibcon#read 3, iclass 23, count 2 2006.173.17:36:42.67#ibcon#about to read 4, iclass 23, count 2 2006.173.17:36:42.67#ibcon#read 4, iclass 23, count 2 2006.173.17:36:42.67#ibcon#about to read 5, iclass 23, count 2 2006.173.17:36:42.67#ibcon#read 5, iclass 23, count 2 2006.173.17:36:42.67#ibcon#about to read 6, iclass 23, count 2 2006.173.17:36:42.67#ibcon#read 6, iclass 23, count 2 2006.173.17:36:42.67#ibcon#end of sib2, iclass 23, count 2 2006.173.17:36:42.67#ibcon#*mode == 0, iclass 23, count 2 2006.173.17:36:42.67#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.17:36:42.67#ibcon#[27=AT03-04\r\n] 2006.173.17:36:42.67#ibcon#*before write, iclass 23, count 2 2006.173.17:36:42.67#ibcon#enter sib2, iclass 23, count 2 2006.173.17:36:42.67#ibcon#flushed, iclass 23, count 2 2006.173.17:36:42.67#ibcon#about to write, iclass 23, count 2 2006.173.17:36:42.67#ibcon#wrote, iclass 23, count 2 2006.173.17:36:42.67#ibcon#about to read 3, iclass 23, count 2 2006.173.17:36:42.70#ibcon#read 3, iclass 23, count 2 2006.173.17:36:42.70#ibcon#about to read 4, iclass 23, count 2 2006.173.17:36:42.70#ibcon#read 4, iclass 23, count 2 2006.173.17:36:42.70#ibcon#about to read 5, iclass 23, count 2 2006.173.17:36:42.70#ibcon#read 5, iclass 23, count 2 2006.173.17:36:42.70#ibcon#about to read 6, iclass 23, count 2 2006.173.17:36:42.70#ibcon#read 6, iclass 23, count 2 2006.173.17:36:42.70#ibcon#end of sib2, iclass 23, count 2 2006.173.17:36:42.70#ibcon#*after write, iclass 23, count 2 2006.173.17:36:42.70#ibcon#*before return 0, iclass 23, count 2 2006.173.17:36:42.70#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.17:36:42.70#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.17:36:42.70#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.17:36:42.70#ibcon#ireg 7 cls_cnt 0 2006.173.17:36:42.70#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.17:36:42.82#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.17:36:42.82#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.17:36:42.82#ibcon#enter wrdev, iclass 23, count 0 2006.173.17:36:42.82#ibcon#first serial, iclass 23, count 0 2006.173.17:36:42.82#ibcon#enter sib2, iclass 23, count 0 2006.173.17:36:42.82#ibcon#flushed, iclass 23, count 0 2006.173.17:36:42.82#ibcon#about to write, iclass 23, count 0 2006.173.17:36:42.82#ibcon#wrote, iclass 23, count 0 2006.173.17:36:42.82#ibcon#about to read 3, iclass 23, count 0 2006.173.17:36:42.84#ibcon#read 3, iclass 23, count 0 2006.173.17:36:42.84#ibcon#about to read 4, iclass 23, count 0 2006.173.17:36:42.84#ibcon#read 4, iclass 23, count 0 2006.173.17:36:42.84#ibcon#about to read 5, iclass 23, count 0 2006.173.17:36:42.84#ibcon#read 5, iclass 23, count 0 2006.173.17:36:42.84#ibcon#about to read 6, iclass 23, count 0 2006.173.17:36:42.84#ibcon#read 6, iclass 23, count 0 2006.173.17:36:42.84#ibcon#end of sib2, iclass 23, count 0 2006.173.17:36:42.84#ibcon#*mode == 0, iclass 23, count 0 2006.173.17:36:42.84#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.17:36:42.84#ibcon#[27=USB\r\n] 2006.173.17:36:42.84#ibcon#*before write, iclass 23, count 0 2006.173.17:36:42.84#ibcon#enter sib2, iclass 23, count 0 2006.173.17:36:42.84#ibcon#flushed, iclass 23, count 0 2006.173.17:36:42.84#ibcon#about to write, iclass 23, count 0 2006.173.17:36:42.84#ibcon#wrote, iclass 23, count 0 2006.173.17:36:42.84#ibcon#about to read 3, iclass 23, count 0 2006.173.17:36:42.87#ibcon#read 3, iclass 23, count 0 2006.173.17:36:42.87#ibcon#about to read 4, iclass 23, count 0 2006.173.17:36:42.87#ibcon#read 4, iclass 23, count 0 2006.173.17:36:42.87#ibcon#about to read 5, iclass 23, count 0 2006.173.17:36:42.87#ibcon#read 5, iclass 23, count 0 2006.173.17:36:42.87#ibcon#about to read 6, iclass 23, count 0 2006.173.17:36:42.87#ibcon#read 6, iclass 23, count 0 2006.173.17:36:42.87#ibcon#end of sib2, iclass 23, count 0 2006.173.17:36:42.87#ibcon#*after write, iclass 23, count 0 2006.173.17:36:42.87#ibcon#*before return 0, iclass 23, count 0 2006.173.17:36:42.87#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.17:36:42.87#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.17:36:42.87#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.17:36:42.87#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.17:36:42.87$vck44/vblo=4,679.99 2006.173.17:36:42.87#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.17:36:42.87#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.17:36:42.87#ibcon#ireg 17 cls_cnt 0 2006.173.17:36:42.87#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.17:36:42.87#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.17:36:42.87#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.17:36:42.87#ibcon#enter wrdev, iclass 25, count 0 2006.173.17:36:42.87#ibcon#first serial, iclass 25, count 0 2006.173.17:36:42.87#ibcon#enter sib2, iclass 25, count 0 2006.173.17:36:42.87#ibcon#flushed, iclass 25, count 0 2006.173.17:36:42.87#ibcon#about to write, iclass 25, count 0 2006.173.17:36:42.87#ibcon#wrote, iclass 25, count 0 2006.173.17:36:42.87#ibcon#about to read 3, iclass 25, count 0 2006.173.17:36:42.89#ibcon#read 3, iclass 25, count 0 2006.173.17:36:42.89#ibcon#about to read 4, iclass 25, count 0 2006.173.17:36:42.89#ibcon#read 4, iclass 25, count 0 2006.173.17:36:42.89#ibcon#about to read 5, iclass 25, count 0 2006.173.17:36:42.89#ibcon#read 5, iclass 25, count 0 2006.173.17:36:42.89#ibcon#about to read 6, iclass 25, count 0 2006.173.17:36:42.89#ibcon#read 6, iclass 25, count 0 2006.173.17:36:42.89#ibcon#end of sib2, iclass 25, count 0 2006.173.17:36:42.89#ibcon#*mode == 0, iclass 25, count 0 2006.173.17:36:42.89#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.17:36:42.89#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.17:36:42.89#ibcon#*before write, iclass 25, count 0 2006.173.17:36:42.89#ibcon#enter sib2, iclass 25, count 0 2006.173.17:36:42.89#ibcon#flushed, iclass 25, count 0 2006.173.17:36:42.89#ibcon#about to write, iclass 25, count 0 2006.173.17:36:42.89#ibcon#wrote, iclass 25, count 0 2006.173.17:36:42.89#ibcon#about to read 3, iclass 25, count 0 2006.173.17:36:42.93#ibcon#read 3, iclass 25, count 0 2006.173.17:36:42.93#ibcon#about to read 4, iclass 25, count 0 2006.173.17:36:42.93#ibcon#read 4, iclass 25, count 0 2006.173.17:36:42.93#ibcon#about to read 5, iclass 25, count 0 2006.173.17:36:42.93#ibcon#read 5, iclass 25, count 0 2006.173.17:36:42.93#ibcon#about to read 6, iclass 25, count 0 2006.173.17:36:42.93#ibcon#read 6, iclass 25, count 0 2006.173.17:36:42.93#ibcon#end of sib2, iclass 25, count 0 2006.173.17:36:42.93#ibcon#*after write, iclass 25, count 0 2006.173.17:36:42.93#ibcon#*before return 0, iclass 25, count 0 2006.173.17:36:42.93#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.17:36:42.93#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.17:36:42.93#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.17:36:42.93#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.17:36:42.93$vck44/vb=4,4 2006.173.17:36:42.93#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.17:36:42.93#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.17:36:42.93#ibcon#ireg 11 cls_cnt 2 2006.173.17:36:42.93#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.17:36:42.99#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.17:36:42.99#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.17:36:42.99#ibcon#enter wrdev, iclass 27, count 2 2006.173.17:36:42.99#ibcon#first serial, iclass 27, count 2 2006.173.17:36:42.99#ibcon#enter sib2, iclass 27, count 2 2006.173.17:36:42.99#ibcon#flushed, iclass 27, count 2 2006.173.17:36:42.99#ibcon#about to write, iclass 27, count 2 2006.173.17:36:42.99#ibcon#wrote, iclass 27, count 2 2006.173.17:36:42.99#ibcon#about to read 3, iclass 27, count 2 2006.173.17:36:43.01#ibcon#read 3, iclass 27, count 2 2006.173.17:36:43.01#ibcon#about to read 4, iclass 27, count 2 2006.173.17:36:43.01#ibcon#read 4, iclass 27, count 2 2006.173.17:36:43.01#ibcon#about to read 5, iclass 27, count 2 2006.173.17:36:43.01#ibcon#read 5, iclass 27, count 2 2006.173.17:36:43.01#ibcon#about to read 6, iclass 27, count 2 2006.173.17:36:43.01#ibcon#read 6, iclass 27, count 2 2006.173.17:36:43.01#ibcon#end of sib2, iclass 27, count 2 2006.173.17:36:43.01#ibcon#*mode == 0, iclass 27, count 2 2006.173.17:36:43.01#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.17:36:43.01#ibcon#[27=AT04-04\r\n] 2006.173.17:36:43.01#ibcon#*before write, iclass 27, count 2 2006.173.17:36:43.01#ibcon#enter sib2, iclass 27, count 2 2006.173.17:36:43.01#ibcon#flushed, iclass 27, count 2 2006.173.17:36:43.01#ibcon#about to write, iclass 27, count 2 2006.173.17:36:43.01#ibcon#wrote, iclass 27, count 2 2006.173.17:36:43.01#ibcon#about to read 3, iclass 27, count 2 2006.173.17:36:43.04#ibcon#read 3, iclass 27, count 2 2006.173.17:36:43.04#ibcon#about to read 4, iclass 27, count 2 2006.173.17:36:43.04#ibcon#read 4, iclass 27, count 2 2006.173.17:36:43.04#ibcon#about to read 5, iclass 27, count 2 2006.173.17:36:43.04#ibcon#read 5, iclass 27, count 2 2006.173.17:36:43.04#ibcon#about to read 6, iclass 27, count 2 2006.173.17:36:43.04#ibcon#read 6, iclass 27, count 2 2006.173.17:36:43.04#ibcon#end of sib2, iclass 27, count 2 2006.173.17:36:43.04#ibcon#*after write, iclass 27, count 2 2006.173.17:36:43.04#ibcon#*before return 0, iclass 27, count 2 2006.173.17:36:43.04#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.17:36:43.04#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.17:36:43.04#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.17:36:43.04#ibcon#ireg 7 cls_cnt 0 2006.173.17:36:43.04#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.17:36:43.16#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.17:36:43.16#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.17:36:43.16#ibcon#enter wrdev, iclass 27, count 0 2006.173.17:36:43.16#ibcon#first serial, iclass 27, count 0 2006.173.17:36:43.16#ibcon#enter sib2, iclass 27, count 0 2006.173.17:36:43.16#ibcon#flushed, iclass 27, count 0 2006.173.17:36:43.16#ibcon#about to write, iclass 27, count 0 2006.173.17:36:43.16#ibcon#wrote, iclass 27, count 0 2006.173.17:36:43.16#ibcon#about to read 3, iclass 27, count 0 2006.173.17:36:43.18#ibcon#read 3, iclass 27, count 0 2006.173.17:36:43.18#ibcon#about to read 4, iclass 27, count 0 2006.173.17:36:43.18#ibcon#read 4, iclass 27, count 0 2006.173.17:36:43.18#ibcon#about to read 5, iclass 27, count 0 2006.173.17:36:43.18#ibcon#read 5, iclass 27, count 0 2006.173.17:36:43.18#ibcon#about to read 6, iclass 27, count 0 2006.173.17:36:43.18#ibcon#read 6, iclass 27, count 0 2006.173.17:36:43.18#ibcon#end of sib2, iclass 27, count 0 2006.173.17:36:43.18#ibcon#*mode == 0, iclass 27, count 0 2006.173.17:36:43.18#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.17:36:43.18#ibcon#[27=USB\r\n] 2006.173.17:36:43.18#ibcon#*before write, iclass 27, count 0 2006.173.17:36:43.18#ibcon#enter sib2, iclass 27, count 0 2006.173.17:36:43.18#ibcon#flushed, iclass 27, count 0 2006.173.17:36:43.18#ibcon#about to write, iclass 27, count 0 2006.173.17:36:43.18#ibcon#wrote, iclass 27, count 0 2006.173.17:36:43.18#ibcon#about to read 3, iclass 27, count 0 2006.173.17:36:43.21#ibcon#read 3, iclass 27, count 0 2006.173.17:36:43.21#ibcon#about to read 4, iclass 27, count 0 2006.173.17:36:43.21#ibcon#read 4, iclass 27, count 0 2006.173.17:36:43.21#ibcon#about to read 5, iclass 27, count 0 2006.173.17:36:43.21#ibcon#read 5, iclass 27, count 0 2006.173.17:36:43.21#ibcon#about to read 6, iclass 27, count 0 2006.173.17:36:43.21#ibcon#read 6, iclass 27, count 0 2006.173.17:36:43.21#ibcon#end of sib2, iclass 27, count 0 2006.173.17:36:43.21#ibcon#*after write, iclass 27, count 0 2006.173.17:36:43.21#ibcon#*before return 0, iclass 27, count 0 2006.173.17:36:43.21#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.17:36:43.21#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.17:36:43.21#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.17:36:43.21#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.17:36:43.21$vck44/vblo=5,709.99 2006.173.17:36:43.21#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.17:36:43.21#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.17:36:43.21#ibcon#ireg 17 cls_cnt 0 2006.173.17:36:43.21#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.17:36:43.21#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.17:36:43.21#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.17:36:43.21#ibcon#enter wrdev, iclass 29, count 0 2006.173.17:36:43.21#ibcon#first serial, iclass 29, count 0 2006.173.17:36:43.21#ibcon#enter sib2, iclass 29, count 0 2006.173.17:36:43.21#ibcon#flushed, iclass 29, count 0 2006.173.17:36:43.21#ibcon#about to write, iclass 29, count 0 2006.173.17:36:43.21#ibcon#wrote, iclass 29, count 0 2006.173.17:36:43.21#ibcon#about to read 3, iclass 29, count 0 2006.173.17:36:43.23#ibcon#read 3, iclass 29, count 0 2006.173.17:36:43.23#ibcon#about to read 4, iclass 29, count 0 2006.173.17:36:43.23#ibcon#read 4, iclass 29, count 0 2006.173.17:36:43.23#ibcon#about to read 5, iclass 29, count 0 2006.173.17:36:43.23#ibcon#read 5, iclass 29, count 0 2006.173.17:36:43.23#ibcon#about to read 6, iclass 29, count 0 2006.173.17:36:43.23#ibcon#read 6, iclass 29, count 0 2006.173.17:36:43.23#ibcon#end of sib2, iclass 29, count 0 2006.173.17:36:43.23#ibcon#*mode == 0, iclass 29, count 0 2006.173.17:36:43.23#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.17:36:43.23#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.17:36:43.23#ibcon#*before write, iclass 29, count 0 2006.173.17:36:43.23#ibcon#enter sib2, iclass 29, count 0 2006.173.17:36:43.23#ibcon#flushed, iclass 29, count 0 2006.173.17:36:43.23#ibcon#about to write, iclass 29, count 0 2006.173.17:36:43.23#ibcon#wrote, iclass 29, count 0 2006.173.17:36:43.23#ibcon#about to read 3, iclass 29, count 0 2006.173.17:36:43.27#ibcon#read 3, iclass 29, count 0 2006.173.17:36:43.27#ibcon#about to read 4, iclass 29, count 0 2006.173.17:36:43.27#ibcon#read 4, iclass 29, count 0 2006.173.17:36:43.27#ibcon#about to read 5, iclass 29, count 0 2006.173.17:36:43.27#ibcon#read 5, iclass 29, count 0 2006.173.17:36:43.27#ibcon#about to read 6, iclass 29, count 0 2006.173.17:36:43.27#ibcon#read 6, iclass 29, count 0 2006.173.17:36:43.27#ibcon#end of sib2, iclass 29, count 0 2006.173.17:36:43.27#ibcon#*after write, iclass 29, count 0 2006.173.17:36:43.27#ibcon#*before return 0, iclass 29, count 0 2006.173.17:36:43.27#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.17:36:43.27#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.17:36:43.27#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.17:36:43.27#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.17:36:43.27$vck44/vb=5,4 2006.173.17:36:43.27#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.17:36:43.27#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.17:36:43.27#ibcon#ireg 11 cls_cnt 2 2006.173.17:36:43.27#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.17:36:43.33#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.17:36:43.33#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.17:36:43.33#ibcon#enter wrdev, iclass 31, count 2 2006.173.17:36:43.33#ibcon#first serial, iclass 31, count 2 2006.173.17:36:43.33#ibcon#enter sib2, iclass 31, count 2 2006.173.17:36:43.33#ibcon#flushed, iclass 31, count 2 2006.173.17:36:43.33#ibcon#about to write, iclass 31, count 2 2006.173.17:36:43.33#ibcon#wrote, iclass 31, count 2 2006.173.17:36:43.33#ibcon#about to read 3, iclass 31, count 2 2006.173.17:36:43.35#ibcon#read 3, iclass 31, count 2 2006.173.17:36:43.35#ibcon#about to read 4, iclass 31, count 2 2006.173.17:36:43.35#ibcon#read 4, iclass 31, count 2 2006.173.17:36:43.35#ibcon#about to read 5, iclass 31, count 2 2006.173.17:36:43.35#ibcon#read 5, iclass 31, count 2 2006.173.17:36:43.35#ibcon#about to read 6, iclass 31, count 2 2006.173.17:36:43.35#ibcon#read 6, iclass 31, count 2 2006.173.17:36:43.35#ibcon#end of sib2, iclass 31, count 2 2006.173.17:36:43.35#ibcon#*mode == 0, iclass 31, count 2 2006.173.17:36:43.35#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.17:36:43.35#ibcon#[27=AT05-04\r\n] 2006.173.17:36:43.35#ibcon#*before write, iclass 31, count 2 2006.173.17:36:43.35#ibcon#enter sib2, iclass 31, count 2 2006.173.17:36:43.35#ibcon#flushed, iclass 31, count 2 2006.173.17:36:43.35#ibcon#about to write, iclass 31, count 2 2006.173.17:36:43.35#ibcon#wrote, iclass 31, count 2 2006.173.17:36:43.35#ibcon#about to read 3, iclass 31, count 2 2006.173.17:36:43.38#ibcon#read 3, iclass 31, count 2 2006.173.17:36:43.38#ibcon#about to read 4, iclass 31, count 2 2006.173.17:36:43.38#ibcon#read 4, iclass 31, count 2 2006.173.17:36:43.38#ibcon#about to read 5, iclass 31, count 2 2006.173.17:36:43.38#ibcon#read 5, iclass 31, count 2 2006.173.17:36:43.38#ibcon#about to read 6, iclass 31, count 2 2006.173.17:36:43.38#ibcon#read 6, iclass 31, count 2 2006.173.17:36:43.38#ibcon#end of sib2, iclass 31, count 2 2006.173.17:36:43.38#ibcon#*after write, iclass 31, count 2 2006.173.17:36:43.38#ibcon#*before return 0, iclass 31, count 2 2006.173.17:36:43.38#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.17:36:43.38#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.17:36:43.38#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.17:36:43.38#ibcon#ireg 7 cls_cnt 0 2006.173.17:36:43.38#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.17:36:43.50#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.17:36:43.50#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.17:36:43.50#ibcon#enter wrdev, iclass 31, count 0 2006.173.17:36:43.50#ibcon#first serial, iclass 31, count 0 2006.173.17:36:43.50#ibcon#enter sib2, iclass 31, count 0 2006.173.17:36:43.50#ibcon#flushed, iclass 31, count 0 2006.173.17:36:43.50#ibcon#about to write, iclass 31, count 0 2006.173.17:36:43.50#ibcon#wrote, iclass 31, count 0 2006.173.17:36:43.50#ibcon#about to read 3, iclass 31, count 0 2006.173.17:36:43.52#ibcon#read 3, iclass 31, count 0 2006.173.17:36:43.52#ibcon#about to read 4, iclass 31, count 0 2006.173.17:36:43.52#ibcon#read 4, iclass 31, count 0 2006.173.17:36:43.52#ibcon#about to read 5, iclass 31, count 0 2006.173.17:36:43.52#ibcon#read 5, iclass 31, count 0 2006.173.17:36:43.52#ibcon#about to read 6, iclass 31, count 0 2006.173.17:36:43.52#ibcon#read 6, iclass 31, count 0 2006.173.17:36:43.52#ibcon#end of sib2, iclass 31, count 0 2006.173.17:36:43.52#ibcon#*mode == 0, iclass 31, count 0 2006.173.17:36:43.52#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.17:36:43.52#ibcon#[27=USB\r\n] 2006.173.17:36:43.52#ibcon#*before write, iclass 31, count 0 2006.173.17:36:43.52#ibcon#enter sib2, iclass 31, count 0 2006.173.17:36:43.52#ibcon#flushed, iclass 31, count 0 2006.173.17:36:43.52#ibcon#about to write, iclass 31, count 0 2006.173.17:36:43.52#ibcon#wrote, iclass 31, count 0 2006.173.17:36:43.52#ibcon#about to read 3, iclass 31, count 0 2006.173.17:36:43.55#ibcon#read 3, iclass 31, count 0 2006.173.17:36:43.55#ibcon#about to read 4, iclass 31, count 0 2006.173.17:36:43.55#ibcon#read 4, iclass 31, count 0 2006.173.17:36:43.55#ibcon#about to read 5, iclass 31, count 0 2006.173.17:36:43.55#ibcon#read 5, iclass 31, count 0 2006.173.17:36:43.55#ibcon#about to read 6, iclass 31, count 0 2006.173.17:36:43.55#ibcon#read 6, iclass 31, count 0 2006.173.17:36:43.55#ibcon#end of sib2, iclass 31, count 0 2006.173.17:36:43.55#ibcon#*after write, iclass 31, count 0 2006.173.17:36:43.55#ibcon#*before return 0, iclass 31, count 0 2006.173.17:36:43.55#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.17:36:43.55#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.17:36:43.55#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.17:36:43.55#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.17:36:43.55$vck44/vblo=6,719.99 2006.173.17:36:43.55#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.17:36:43.55#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.17:36:43.55#ibcon#ireg 17 cls_cnt 0 2006.173.17:36:43.55#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.17:36:43.55#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.17:36:43.55#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.17:36:43.55#ibcon#enter wrdev, iclass 33, count 0 2006.173.17:36:43.55#ibcon#first serial, iclass 33, count 0 2006.173.17:36:43.55#ibcon#enter sib2, iclass 33, count 0 2006.173.17:36:43.55#ibcon#flushed, iclass 33, count 0 2006.173.17:36:43.55#ibcon#about to write, iclass 33, count 0 2006.173.17:36:43.55#ibcon#wrote, iclass 33, count 0 2006.173.17:36:43.55#ibcon#about to read 3, iclass 33, count 0 2006.173.17:36:43.57#ibcon#read 3, iclass 33, count 0 2006.173.17:36:43.57#ibcon#about to read 4, iclass 33, count 0 2006.173.17:36:43.57#ibcon#read 4, iclass 33, count 0 2006.173.17:36:43.57#ibcon#about to read 5, iclass 33, count 0 2006.173.17:36:43.57#ibcon#read 5, iclass 33, count 0 2006.173.17:36:43.57#ibcon#about to read 6, iclass 33, count 0 2006.173.17:36:43.57#ibcon#read 6, iclass 33, count 0 2006.173.17:36:43.57#ibcon#end of sib2, iclass 33, count 0 2006.173.17:36:43.57#ibcon#*mode == 0, iclass 33, count 0 2006.173.17:36:43.57#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.17:36:43.57#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.17:36:43.57#ibcon#*before write, iclass 33, count 0 2006.173.17:36:43.57#ibcon#enter sib2, iclass 33, count 0 2006.173.17:36:43.57#ibcon#flushed, iclass 33, count 0 2006.173.17:36:43.57#ibcon#about to write, iclass 33, count 0 2006.173.17:36:43.57#ibcon#wrote, iclass 33, count 0 2006.173.17:36:43.57#ibcon#about to read 3, iclass 33, count 0 2006.173.17:36:43.61#ibcon#read 3, iclass 33, count 0 2006.173.17:36:43.61#ibcon#about to read 4, iclass 33, count 0 2006.173.17:36:43.61#ibcon#read 4, iclass 33, count 0 2006.173.17:36:43.61#ibcon#about to read 5, iclass 33, count 0 2006.173.17:36:43.61#ibcon#read 5, iclass 33, count 0 2006.173.17:36:43.61#ibcon#about to read 6, iclass 33, count 0 2006.173.17:36:43.61#ibcon#read 6, iclass 33, count 0 2006.173.17:36:43.61#ibcon#end of sib2, iclass 33, count 0 2006.173.17:36:43.61#ibcon#*after write, iclass 33, count 0 2006.173.17:36:43.61#ibcon#*before return 0, iclass 33, count 0 2006.173.17:36:43.61#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.17:36:43.61#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.17:36:43.61#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.17:36:43.61#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.17:36:43.61$vck44/vb=6,4 2006.173.17:36:43.61#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.17:36:43.61#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.17:36:43.61#ibcon#ireg 11 cls_cnt 2 2006.173.17:36:43.61#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.17:36:43.67#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.17:36:43.67#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.17:36:43.67#ibcon#enter wrdev, iclass 35, count 2 2006.173.17:36:43.67#ibcon#first serial, iclass 35, count 2 2006.173.17:36:43.67#ibcon#enter sib2, iclass 35, count 2 2006.173.17:36:43.67#ibcon#flushed, iclass 35, count 2 2006.173.17:36:43.67#ibcon#about to write, iclass 35, count 2 2006.173.17:36:43.67#ibcon#wrote, iclass 35, count 2 2006.173.17:36:43.67#ibcon#about to read 3, iclass 35, count 2 2006.173.17:36:43.69#ibcon#read 3, iclass 35, count 2 2006.173.17:36:43.69#ibcon#about to read 4, iclass 35, count 2 2006.173.17:36:43.69#ibcon#read 4, iclass 35, count 2 2006.173.17:36:43.69#ibcon#about to read 5, iclass 35, count 2 2006.173.17:36:43.69#ibcon#read 5, iclass 35, count 2 2006.173.17:36:43.69#ibcon#about to read 6, iclass 35, count 2 2006.173.17:36:43.69#ibcon#read 6, iclass 35, count 2 2006.173.17:36:43.69#ibcon#end of sib2, iclass 35, count 2 2006.173.17:36:43.69#ibcon#*mode == 0, iclass 35, count 2 2006.173.17:36:43.69#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.17:36:43.69#ibcon#[27=AT06-04\r\n] 2006.173.17:36:43.69#ibcon#*before write, iclass 35, count 2 2006.173.17:36:43.69#ibcon#enter sib2, iclass 35, count 2 2006.173.17:36:43.69#ibcon#flushed, iclass 35, count 2 2006.173.17:36:43.69#ibcon#about to write, iclass 35, count 2 2006.173.17:36:43.69#ibcon#wrote, iclass 35, count 2 2006.173.17:36:43.69#ibcon#about to read 3, iclass 35, count 2 2006.173.17:36:43.72#ibcon#read 3, iclass 35, count 2 2006.173.17:36:43.72#ibcon#about to read 4, iclass 35, count 2 2006.173.17:36:43.72#ibcon#read 4, iclass 35, count 2 2006.173.17:36:43.72#ibcon#about to read 5, iclass 35, count 2 2006.173.17:36:43.72#ibcon#read 5, iclass 35, count 2 2006.173.17:36:43.72#ibcon#about to read 6, iclass 35, count 2 2006.173.17:36:43.72#ibcon#read 6, iclass 35, count 2 2006.173.17:36:43.72#ibcon#end of sib2, iclass 35, count 2 2006.173.17:36:43.72#ibcon#*after write, iclass 35, count 2 2006.173.17:36:43.72#ibcon#*before return 0, iclass 35, count 2 2006.173.17:36:43.72#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.17:36:43.72#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.17:36:43.72#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.17:36:43.72#ibcon#ireg 7 cls_cnt 0 2006.173.17:36:43.72#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.17:36:43.84#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.17:36:43.84#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.17:36:43.84#ibcon#enter wrdev, iclass 35, count 0 2006.173.17:36:43.84#ibcon#first serial, iclass 35, count 0 2006.173.17:36:43.84#ibcon#enter sib2, iclass 35, count 0 2006.173.17:36:43.84#ibcon#flushed, iclass 35, count 0 2006.173.17:36:43.84#ibcon#about to write, iclass 35, count 0 2006.173.17:36:43.84#ibcon#wrote, iclass 35, count 0 2006.173.17:36:43.84#ibcon#about to read 3, iclass 35, count 0 2006.173.17:36:43.86#ibcon#read 3, iclass 35, count 0 2006.173.17:36:43.86#ibcon#about to read 4, iclass 35, count 0 2006.173.17:36:43.86#ibcon#read 4, iclass 35, count 0 2006.173.17:36:43.86#ibcon#about to read 5, iclass 35, count 0 2006.173.17:36:43.86#ibcon#read 5, iclass 35, count 0 2006.173.17:36:43.86#ibcon#about to read 6, iclass 35, count 0 2006.173.17:36:43.86#ibcon#read 6, iclass 35, count 0 2006.173.17:36:43.86#ibcon#end of sib2, iclass 35, count 0 2006.173.17:36:43.86#ibcon#*mode == 0, iclass 35, count 0 2006.173.17:36:43.86#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.17:36:43.86#ibcon#[27=USB\r\n] 2006.173.17:36:43.86#ibcon#*before write, iclass 35, count 0 2006.173.17:36:43.86#ibcon#enter sib2, iclass 35, count 0 2006.173.17:36:43.86#ibcon#flushed, iclass 35, count 0 2006.173.17:36:43.86#ibcon#about to write, iclass 35, count 0 2006.173.17:36:43.86#ibcon#wrote, iclass 35, count 0 2006.173.17:36:43.86#ibcon#about to read 3, iclass 35, count 0 2006.173.17:36:43.89#ibcon#read 3, iclass 35, count 0 2006.173.17:36:43.89#ibcon#about to read 4, iclass 35, count 0 2006.173.17:36:43.89#ibcon#read 4, iclass 35, count 0 2006.173.17:36:43.89#ibcon#about to read 5, iclass 35, count 0 2006.173.17:36:43.89#ibcon#read 5, iclass 35, count 0 2006.173.17:36:43.89#ibcon#about to read 6, iclass 35, count 0 2006.173.17:36:43.89#ibcon#read 6, iclass 35, count 0 2006.173.17:36:43.89#ibcon#end of sib2, iclass 35, count 0 2006.173.17:36:43.89#ibcon#*after write, iclass 35, count 0 2006.173.17:36:43.89#ibcon#*before return 0, iclass 35, count 0 2006.173.17:36:43.89#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.17:36:43.89#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.17:36:43.89#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.17:36:43.89#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.17:36:43.89$vck44/vblo=7,734.99 2006.173.17:36:43.89#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.17:36:43.89#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.17:36:43.89#ibcon#ireg 17 cls_cnt 0 2006.173.17:36:43.89#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.17:36:43.89#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.17:36:43.89#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.17:36:43.89#ibcon#enter wrdev, iclass 37, count 0 2006.173.17:36:43.89#ibcon#first serial, iclass 37, count 0 2006.173.17:36:43.89#ibcon#enter sib2, iclass 37, count 0 2006.173.17:36:43.89#ibcon#flushed, iclass 37, count 0 2006.173.17:36:43.89#ibcon#about to write, iclass 37, count 0 2006.173.17:36:43.89#ibcon#wrote, iclass 37, count 0 2006.173.17:36:43.89#ibcon#about to read 3, iclass 37, count 0 2006.173.17:36:43.91#ibcon#read 3, iclass 37, count 0 2006.173.17:36:43.91#ibcon#about to read 4, iclass 37, count 0 2006.173.17:36:43.91#ibcon#read 4, iclass 37, count 0 2006.173.17:36:43.91#ibcon#about to read 5, iclass 37, count 0 2006.173.17:36:43.91#ibcon#read 5, iclass 37, count 0 2006.173.17:36:43.91#ibcon#about to read 6, iclass 37, count 0 2006.173.17:36:43.91#ibcon#read 6, iclass 37, count 0 2006.173.17:36:43.91#ibcon#end of sib2, iclass 37, count 0 2006.173.17:36:43.91#ibcon#*mode == 0, iclass 37, count 0 2006.173.17:36:43.91#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.17:36:43.91#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.17:36:43.91#ibcon#*before write, iclass 37, count 0 2006.173.17:36:43.91#ibcon#enter sib2, iclass 37, count 0 2006.173.17:36:43.91#ibcon#flushed, iclass 37, count 0 2006.173.17:36:43.91#ibcon#about to write, iclass 37, count 0 2006.173.17:36:43.91#ibcon#wrote, iclass 37, count 0 2006.173.17:36:43.91#ibcon#about to read 3, iclass 37, count 0 2006.173.17:36:43.95#ibcon#read 3, iclass 37, count 0 2006.173.17:36:43.95#ibcon#about to read 4, iclass 37, count 0 2006.173.17:36:43.95#ibcon#read 4, iclass 37, count 0 2006.173.17:36:43.95#ibcon#about to read 5, iclass 37, count 0 2006.173.17:36:43.95#ibcon#read 5, iclass 37, count 0 2006.173.17:36:43.95#ibcon#about to read 6, iclass 37, count 0 2006.173.17:36:43.95#ibcon#read 6, iclass 37, count 0 2006.173.17:36:43.95#ibcon#end of sib2, iclass 37, count 0 2006.173.17:36:43.95#ibcon#*after write, iclass 37, count 0 2006.173.17:36:43.95#ibcon#*before return 0, iclass 37, count 0 2006.173.17:36:43.95#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.17:36:43.95#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.17:36:43.95#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.17:36:43.95#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.17:36:43.95$vck44/vb=7,4 2006.173.17:36:43.95#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.17:36:43.95#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.17:36:43.95#ibcon#ireg 11 cls_cnt 2 2006.173.17:36:43.95#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.17:36:44.01#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.17:36:44.01#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.17:36:44.01#ibcon#enter wrdev, iclass 39, count 2 2006.173.17:36:44.01#ibcon#first serial, iclass 39, count 2 2006.173.17:36:44.01#ibcon#enter sib2, iclass 39, count 2 2006.173.17:36:44.01#ibcon#flushed, iclass 39, count 2 2006.173.17:36:44.01#ibcon#about to write, iclass 39, count 2 2006.173.17:36:44.01#ibcon#wrote, iclass 39, count 2 2006.173.17:36:44.01#ibcon#about to read 3, iclass 39, count 2 2006.173.17:36:44.03#ibcon#read 3, iclass 39, count 2 2006.173.17:36:44.03#ibcon#about to read 4, iclass 39, count 2 2006.173.17:36:44.03#ibcon#read 4, iclass 39, count 2 2006.173.17:36:44.03#ibcon#about to read 5, iclass 39, count 2 2006.173.17:36:44.03#ibcon#read 5, iclass 39, count 2 2006.173.17:36:44.03#ibcon#about to read 6, iclass 39, count 2 2006.173.17:36:44.03#ibcon#read 6, iclass 39, count 2 2006.173.17:36:44.03#ibcon#end of sib2, iclass 39, count 2 2006.173.17:36:44.03#ibcon#*mode == 0, iclass 39, count 2 2006.173.17:36:44.03#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.17:36:44.03#ibcon#[27=AT07-04\r\n] 2006.173.17:36:44.03#ibcon#*before write, iclass 39, count 2 2006.173.17:36:44.03#ibcon#enter sib2, iclass 39, count 2 2006.173.17:36:44.03#ibcon#flushed, iclass 39, count 2 2006.173.17:36:44.03#ibcon#about to write, iclass 39, count 2 2006.173.17:36:44.03#ibcon#wrote, iclass 39, count 2 2006.173.17:36:44.03#ibcon#about to read 3, iclass 39, count 2 2006.173.17:36:44.06#ibcon#read 3, iclass 39, count 2 2006.173.17:36:44.06#ibcon#about to read 4, iclass 39, count 2 2006.173.17:36:44.06#ibcon#read 4, iclass 39, count 2 2006.173.17:36:44.06#ibcon#about to read 5, iclass 39, count 2 2006.173.17:36:44.06#ibcon#read 5, iclass 39, count 2 2006.173.17:36:44.06#ibcon#about to read 6, iclass 39, count 2 2006.173.17:36:44.06#ibcon#read 6, iclass 39, count 2 2006.173.17:36:44.06#ibcon#end of sib2, iclass 39, count 2 2006.173.17:36:44.06#ibcon#*after write, iclass 39, count 2 2006.173.17:36:44.06#ibcon#*before return 0, iclass 39, count 2 2006.173.17:36:44.06#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.17:36:44.06#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.17:36:44.06#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.17:36:44.06#ibcon#ireg 7 cls_cnt 0 2006.173.17:36:44.06#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.17:36:44.18#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.17:36:44.18#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.17:36:44.18#ibcon#enter wrdev, iclass 39, count 0 2006.173.17:36:44.18#ibcon#first serial, iclass 39, count 0 2006.173.17:36:44.18#ibcon#enter sib2, iclass 39, count 0 2006.173.17:36:44.18#ibcon#flushed, iclass 39, count 0 2006.173.17:36:44.18#ibcon#about to write, iclass 39, count 0 2006.173.17:36:44.18#ibcon#wrote, iclass 39, count 0 2006.173.17:36:44.18#ibcon#about to read 3, iclass 39, count 0 2006.173.17:36:44.20#ibcon#read 3, iclass 39, count 0 2006.173.17:36:44.20#ibcon#about to read 4, iclass 39, count 0 2006.173.17:36:44.20#ibcon#read 4, iclass 39, count 0 2006.173.17:36:44.20#ibcon#about to read 5, iclass 39, count 0 2006.173.17:36:44.20#ibcon#read 5, iclass 39, count 0 2006.173.17:36:44.20#ibcon#about to read 6, iclass 39, count 0 2006.173.17:36:44.20#ibcon#read 6, iclass 39, count 0 2006.173.17:36:44.20#ibcon#end of sib2, iclass 39, count 0 2006.173.17:36:44.20#ibcon#*mode == 0, iclass 39, count 0 2006.173.17:36:44.20#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.17:36:44.20#ibcon#[27=USB\r\n] 2006.173.17:36:44.20#ibcon#*before write, iclass 39, count 0 2006.173.17:36:44.20#ibcon#enter sib2, iclass 39, count 0 2006.173.17:36:44.20#ibcon#flushed, iclass 39, count 0 2006.173.17:36:44.20#ibcon#about to write, iclass 39, count 0 2006.173.17:36:44.20#ibcon#wrote, iclass 39, count 0 2006.173.17:36:44.20#ibcon#about to read 3, iclass 39, count 0 2006.173.17:36:44.23#ibcon#read 3, iclass 39, count 0 2006.173.17:36:44.23#ibcon#about to read 4, iclass 39, count 0 2006.173.17:36:44.23#ibcon#read 4, iclass 39, count 0 2006.173.17:36:44.23#ibcon#about to read 5, iclass 39, count 0 2006.173.17:36:44.23#ibcon#read 5, iclass 39, count 0 2006.173.17:36:44.23#ibcon#about to read 6, iclass 39, count 0 2006.173.17:36:44.23#ibcon#read 6, iclass 39, count 0 2006.173.17:36:44.23#ibcon#end of sib2, iclass 39, count 0 2006.173.17:36:44.23#ibcon#*after write, iclass 39, count 0 2006.173.17:36:44.23#ibcon#*before return 0, iclass 39, count 0 2006.173.17:36:44.23#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.17:36:44.23#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.17:36:44.23#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.17:36:44.23#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.17:36:44.23$vck44/vblo=8,744.99 2006.173.17:36:44.23#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.17:36:44.23#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.17:36:44.23#ibcon#ireg 17 cls_cnt 0 2006.173.17:36:44.23#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.17:36:44.23#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.17:36:44.23#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.17:36:44.23#ibcon#enter wrdev, iclass 3, count 0 2006.173.17:36:44.23#ibcon#first serial, iclass 3, count 0 2006.173.17:36:44.23#ibcon#enter sib2, iclass 3, count 0 2006.173.17:36:44.23#ibcon#flushed, iclass 3, count 0 2006.173.17:36:44.23#ibcon#about to write, iclass 3, count 0 2006.173.17:36:44.23#ibcon#wrote, iclass 3, count 0 2006.173.17:36:44.23#ibcon#about to read 3, iclass 3, count 0 2006.173.17:36:44.25#ibcon#read 3, iclass 3, count 0 2006.173.17:36:44.25#ibcon#about to read 4, iclass 3, count 0 2006.173.17:36:44.25#ibcon#read 4, iclass 3, count 0 2006.173.17:36:44.25#ibcon#about to read 5, iclass 3, count 0 2006.173.17:36:44.25#ibcon#read 5, iclass 3, count 0 2006.173.17:36:44.25#ibcon#about to read 6, iclass 3, count 0 2006.173.17:36:44.25#ibcon#read 6, iclass 3, count 0 2006.173.17:36:44.25#ibcon#end of sib2, iclass 3, count 0 2006.173.17:36:44.25#ibcon#*mode == 0, iclass 3, count 0 2006.173.17:36:44.25#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.17:36:44.25#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.17:36:44.25#ibcon#*before write, iclass 3, count 0 2006.173.17:36:44.25#ibcon#enter sib2, iclass 3, count 0 2006.173.17:36:44.25#ibcon#flushed, iclass 3, count 0 2006.173.17:36:44.25#ibcon#about to write, iclass 3, count 0 2006.173.17:36:44.25#ibcon#wrote, iclass 3, count 0 2006.173.17:36:44.25#ibcon#about to read 3, iclass 3, count 0 2006.173.17:36:44.29#ibcon#read 3, iclass 3, count 0 2006.173.17:36:44.29#ibcon#about to read 4, iclass 3, count 0 2006.173.17:36:44.29#ibcon#read 4, iclass 3, count 0 2006.173.17:36:44.29#ibcon#about to read 5, iclass 3, count 0 2006.173.17:36:44.29#ibcon#read 5, iclass 3, count 0 2006.173.17:36:44.29#ibcon#about to read 6, iclass 3, count 0 2006.173.17:36:44.29#ibcon#read 6, iclass 3, count 0 2006.173.17:36:44.29#ibcon#end of sib2, iclass 3, count 0 2006.173.17:36:44.29#ibcon#*after write, iclass 3, count 0 2006.173.17:36:44.29#ibcon#*before return 0, iclass 3, count 0 2006.173.17:36:44.29#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.17:36:44.29#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.17:36:44.29#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.17:36:44.29#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.17:36:44.29$vck44/vb=8,4 2006.173.17:36:44.29#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.17:36:44.29#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.17:36:44.29#ibcon#ireg 11 cls_cnt 2 2006.173.17:36:44.29#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.17:36:44.35#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.17:36:44.35#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.17:36:44.35#ibcon#enter wrdev, iclass 5, count 2 2006.173.17:36:44.35#ibcon#first serial, iclass 5, count 2 2006.173.17:36:44.35#ibcon#enter sib2, iclass 5, count 2 2006.173.17:36:44.35#ibcon#flushed, iclass 5, count 2 2006.173.17:36:44.35#ibcon#about to write, iclass 5, count 2 2006.173.17:36:44.35#ibcon#wrote, iclass 5, count 2 2006.173.17:36:44.35#ibcon#about to read 3, iclass 5, count 2 2006.173.17:36:44.37#ibcon#read 3, iclass 5, count 2 2006.173.17:36:44.37#ibcon#about to read 4, iclass 5, count 2 2006.173.17:36:44.37#ibcon#read 4, iclass 5, count 2 2006.173.17:36:44.37#ibcon#about to read 5, iclass 5, count 2 2006.173.17:36:44.37#ibcon#read 5, iclass 5, count 2 2006.173.17:36:44.37#ibcon#about to read 6, iclass 5, count 2 2006.173.17:36:44.37#ibcon#read 6, iclass 5, count 2 2006.173.17:36:44.37#ibcon#end of sib2, iclass 5, count 2 2006.173.17:36:44.37#ibcon#*mode == 0, iclass 5, count 2 2006.173.17:36:44.37#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.17:36:44.37#ibcon#[27=AT08-04\r\n] 2006.173.17:36:44.37#ibcon#*before write, iclass 5, count 2 2006.173.17:36:44.37#ibcon#enter sib2, iclass 5, count 2 2006.173.17:36:44.37#ibcon#flushed, iclass 5, count 2 2006.173.17:36:44.37#ibcon#about to write, iclass 5, count 2 2006.173.17:36:44.37#ibcon#wrote, iclass 5, count 2 2006.173.17:36:44.37#ibcon#about to read 3, iclass 5, count 2 2006.173.17:36:44.40#ibcon#read 3, iclass 5, count 2 2006.173.17:36:44.40#ibcon#about to read 4, iclass 5, count 2 2006.173.17:36:44.40#ibcon#read 4, iclass 5, count 2 2006.173.17:36:44.40#ibcon#about to read 5, iclass 5, count 2 2006.173.17:36:44.40#ibcon#read 5, iclass 5, count 2 2006.173.17:36:44.40#ibcon#about to read 6, iclass 5, count 2 2006.173.17:36:44.40#ibcon#read 6, iclass 5, count 2 2006.173.17:36:44.40#ibcon#end of sib2, iclass 5, count 2 2006.173.17:36:44.40#ibcon#*after write, iclass 5, count 2 2006.173.17:36:44.40#ibcon#*before return 0, iclass 5, count 2 2006.173.17:36:44.40#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.17:36:44.40#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.17:36:44.40#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.17:36:44.40#ibcon#ireg 7 cls_cnt 0 2006.173.17:36:44.40#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.17:36:44.52#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.17:36:44.52#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.17:36:44.52#ibcon#enter wrdev, iclass 5, count 0 2006.173.17:36:44.52#ibcon#first serial, iclass 5, count 0 2006.173.17:36:44.52#ibcon#enter sib2, iclass 5, count 0 2006.173.17:36:44.52#ibcon#flushed, iclass 5, count 0 2006.173.17:36:44.52#ibcon#about to write, iclass 5, count 0 2006.173.17:36:44.52#ibcon#wrote, iclass 5, count 0 2006.173.17:36:44.52#ibcon#about to read 3, iclass 5, count 0 2006.173.17:36:44.54#ibcon#read 3, iclass 5, count 0 2006.173.17:36:44.54#ibcon#about to read 4, iclass 5, count 0 2006.173.17:36:44.54#ibcon#read 4, iclass 5, count 0 2006.173.17:36:44.54#ibcon#about to read 5, iclass 5, count 0 2006.173.17:36:44.54#ibcon#read 5, iclass 5, count 0 2006.173.17:36:44.54#ibcon#about to read 6, iclass 5, count 0 2006.173.17:36:44.54#ibcon#read 6, iclass 5, count 0 2006.173.17:36:44.54#ibcon#end of sib2, iclass 5, count 0 2006.173.17:36:44.54#ibcon#*mode == 0, iclass 5, count 0 2006.173.17:36:44.54#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.17:36:44.54#ibcon#[27=USB\r\n] 2006.173.17:36:44.54#ibcon#*before write, iclass 5, count 0 2006.173.17:36:44.54#ibcon#enter sib2, iclass 5, count 0 2006.173.17:36:44.54#ibcon#flushed, iclass 5, count 0 2006.173.17:36:44.54#ibcon#about to write, iclass 5, count 0 2006.173.17:36:44.54#ibcon#wrote, iclass 5, count 0 2006.173.17:36:44.54#ibcon#about to read 3, iclass 5, count 0 2006.173.17:36:44.57#ibcon#read 3, iclass 5, count 0 2006.173.17:36:44.57#ibcon#about to read 4, iclass 5, count 0 2006.173.17:36:44.57#ibcon#read 4, iclass 5, count 0 2006.173.17:36:44.57#ibcon#about to read 5, iclass 5, count 0 2006.173.17:36:44.57#ibcon#read 5, iclass 5, count 0 2006.173.17:36:44.57#ibcon#about to read 6, iclass 5, count 0 2006.173.17:36:44.57#ibcon#read 6, iclass 5, count 0 2006.173.17:36:44.57#ibcon#end of sib2, iclass 5, count 0 2006.173.17:36:44.57#ibcon#*after write, iclass 5, count 0 2006.173.17:36:44.57#ibcon#*before return 0, iclass 5, count 0 2006.173.17:36:44.57#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.17:36:44.57#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.17:36:44.57#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.17:36:44.57#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.17:36:44.57$vck44/vabw=wide 2006.173.17:36:44.57#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.17:36:44.57#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.17:36:44.57#ibcon#ireg 8 cls_cnt 0 2006.173.17:36:44.57#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.17:36:44.57#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.17:36:44.57#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.17:36:44.57#ibcon#enter wrdev, iclass 7, count 0 2006.173.17:36:44.57#ibcon#first serial, iclass 7, count 0 2006.173.17:36:44.57#ibcon#enter sib2, iclass 7, count 0 2006.173.17:36:44.57#ibcon#flushed, iclass 7, count 0 2006.173.17:36:44.57#ibcon#about to write, iclass 7, count 0 2006.173.17:36:44.57#ibcon#wrote, iclass 7, count 0 2006.173.17:36:44.57#ibcon#about to read 3, iclass 7, count 0 2006.173.17:36:44.59#ibcon#read 3, iclass 7, count 0 2006.173.17:36:44.59#ibcon#about to read 4, iclass 7, count 0 2006.173.17:36:44.59#ibcon#read 4, iclass 7, count 0 2006.173.17:36:44.59#ibcon#about to read 5, iclass 7, count 0 2006.173.17:36:44.59#ibcon#read 5, iclass 7, count 0 2006.173.17:36:44.59#ibcon#about to read 6, iclass 7, count 0 2006.173.17:36:44.59#ibcon#read 6, iclass 7, count 0 2006.173.17:36:44.59#ibcon#end of sib2, iclass 7, count 0 2006.173.17:36:44.59#ibcon#*mode == 0, iclass 7, count 0 2006.173.17:36:44.59#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.17:36:44.59#ibcon#[25=BW32\r\n] 2006.173.17:36:44.59#ibcon#*before write, iclass 7, count 0 2006.173.17:36:44.59#ibcon#enter sib2, iclass 7, count 0 2006.173.17:36:44.59#ibcon#flushed, iclass 7, count 0 2006.173.17:36:44.59#ibcon#about to write, iclass 7, count 0 2006.173.17:36:44.59#ibcon#wrote, iclass 7, count 0 2006.173.17:36:44.59#ibcon#about to read 3, iclass 7, count 0 2006.173.17:36:44.62#ibcon#read 3, iclass 7, count 0 2006.173.17:36:44.62#ibcon#about to read 4, iclass 7, count 0 2006.173.17:36:44.62#ibcon#read 4, iclass 7, count 0 2006.173.17:36:44.62#ibcon#about to read 5, iclass 7, count 0 2006.173.17:36:44.62#ibcon#read 5, iclass 7, count 0 2006.173.17:36:44.62#ibcon#about to read 6, iclass 7, count 0 2006.173.17:36:44.62#ibcon#read 6, iclass 7, count 0 2006.173.17:36:44.62#ibcon#end of sib2, iclass 7, count 0 2006.173.17:36:44.62#ibcon#*after write, iclass 7, count 0 2006.173.17:36:44.62#ibcon#*before return 0, iclass 7, count 0 2006.173.17:36:44.62#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.17:36:44.62#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.17:36:44.62#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.17:36:44.62#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.17:36:44.62$vck44/vbbw=wide 2006.173.17:36:44.62#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.17:36:44.62#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.17:36:44.62#ibcon#ireg 8 cls_cnt 0 2006.173.17:36:44.62#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.17:36:44.69#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.17:36:44.69#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.17:36:44.69#ibcon#enter wrdev, iclass 11, count 0 2006.173.17:36:44.69#ibcon#first serial, iclass 11, count 0 2006.173.17:36:44.69#ibcon#enter sib2, iclass 11, count 0 2006.173.17:36:44.69#ibcon#flushed, iclass 11, count 0 2006.173.17:36:44.69#ibcon#about to write, iclass 11, count 0 2006.173.17:36:44.69#ibcon#wrote, iclass 11, count 0 2006.173.17:36:44.69#ibcon#about to read 3, iclass 11, count 0 2006.173.17:36:44.71#ibcon#read 3, iclass 11, count 0 2006.173.17:36:44.71#ibcon#about to read 4, iclass 11, count 0 2006.173.17:36:44.71#ibcon#read 4, iclass 11, count 0 2006.173.17:36:44.71#ibcon#about to read 5, iclass 11, count 0 2006.173.17:36:44.71#ibcon#read 5, iclass 11, count 0 2006.173.17:36:44.71#ibcon#about to read 6, iclass 11, count 0 2006.173.17:36:44.71#ibcon#read 6, iclass 11, count 0 2006.173.17:36:44.71#ibcon#end of sib2, iclass 11, count 0 2006.173.17:36:44.71#ibcon#*mode == 0, iclass 11, count 0 2006.173.17:36:44.71#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.17:36:44.71#ibcon#[27=BW32\r\n] 2006.173.17:36:44.71#ibcon#*before write, iclass 11, count 0 2006.173.17:36:44.71#ibcon#enter sib2, iclass 11, count 0 2006.173.17:36:44.71#ibcon#flushed, iclass 11, count 0 2006.173.17:36:44.71#ibcon#about to write, iclass 11, count 0 2006.173.17:36:44.71#ibcon#wrote, iclass 11, count 0 2006.173.17:36:44.71#ibcon#about to read 3, iclass 11, count 0 2006.173.17:36:44.74#ibcon#read 3, iclass 11, count 0 2006.173.17:36:44.74#ibcon#about to read 4, iclass 11, count 0 2006.173.17:36:44.74#ibcon#read 4, iclass 11, count 0 2006.173.17:36:44.74#ibcon#about to read 5, iclass 11, count 0 2006.173.17:36:44.74#ibcon#read 5, iclass 11, count 0 2006.173.17:36:44.74#ibcon#about to read 6, iclass 11, count 0 2006.173.17:36:44.74#ibcon#read 6, iclass 11, count 0 2006.173.17:36:44.74#ibcon#end of sib2, iclass 11, count 0 2006.173.17:36:44.74#ibcon#*after write, iclass 11, count 0 2006.173.17:36:44.74#ibcon#*before return 0, iclass 11, count 0 2006.173.17:36:44.74#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.17:36:44.74#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.17:36:44.74#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.17:36:44.74#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.17:36:44.74$setupk4/ifdk4 2006.173.17:36:44.74$ifdk4/lo= 2006.173.17:36:44.74$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.17:36:44.74$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.17:36:44.74$ifdk4/patch= 2006.173.17:36:44.74$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.17:36:44.74$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.17:36:44.74$setupk4/!*+20s 2006.173.17:36:46.79#abcon#<5=/14 0.8 1.9 20.231001002.3\r\n> 2006.173.17:36:46.81#abcon#{5=INTERFACE CLEAR} 2006.173.17:36:46.87#abcon#[5=S1D000X0/0*\r\n] 2006.173.17:36:56.96#abcon#<5=/14 0.8 1.9 20.231001002.3\r\n> 2006.173.17:36:56.98#abcon#{5=INTERFACE CLEAR} 2006.173.17:36:57.04#abcon#[5=S1D000X0/0*\r\n] 2006.173.17:36:59.26$setupk4/"tpicd 2006.173.17:36:59.26$setupk4/echo=off 2006.173.17:36:59.26$setupk4/xlog=off 2006.173.17:36:59.26:!2006.173.17:37:37 2006.173.17:37:05.14#trakl#Source acquired 2006.173.17:37:07.14#flagr#flagr/antenna,acquired 2006.173.17:37:37.00:preob 2006.173.17:37:38.14/onsource/TRACKING 2006.173.17:37:38.14:!2006.173.17:37:47 2006.173.17:37:47.00:"tape 2006.173.17:37:47.00:"st=record 2006.173.17:37:47.00:data_valid=on 2006.173.17:37:47.00:midob 2006.173.17:37:47.14/onsource/TRACKING 2006.173.17:37:47.14/wx/20.22,1002.4,100 2006.173.17:37:47.33/cable/+6.5138E-03 2006.173.17:37:48.42/va/01,07,usb,yes,34,37 2006.173.17:37:48.42/va/02,06,usb,yes,34,35 2006.173.17:37:48.42/va/03,05,usb,yes,43,45 2006.173.17:37:48.42/va/04,06,usb,yes,35,37 2006.173.17:37:48.42/va/05,04,usb,yes,27,28 2006.173.17:37:48.42/va/06,03,usb,yes,38,38 2006.173.17:37:48.42/va/07,04,usb,yes,31,32 2006.173.17:37:48.42/va/08,04,usb,yes,26,32 2006.173.17:37:48.65/valo/01,524.99,yes,locked 2006.173.17:37:48.65/valo/02,534.99,yes,locked 2006.173.17:37:48.65/valo/03,564.99,yes,locked 2006.173.17:37:48.65/valo/04,624.99,yes,locked 2006.173.17:37:48.65/valo/05,734.99,yes,locked 2006.173.17:37:48.65/valo/06,814.99,yes,locked 2006.173.17:37:48.65/valo/07,864.99,yes,locked 2006.173.17:37:48.65/valo/08,884.99,yes,locked 2006.173.17:37:49.74/vb/01,04,usb,yes,28,27 2006.173.17:37:49.74/vb/02,04,usb,yes,31,31 2006.173.17:37:49.74/vb/03,04,usb,yes,28,31 2006.173.17:37:49.74/vb/04,04,usb,yes,32,31 2006.173.17:37:49.74/vb/05,04,usb,yes,25,27 2006.173.17:37:49.74/vb/06,04,usb,yes,29,25 2006.173.17:37:49.74/vb/07,04,usb,yes,29,29 2006.173.17:37:49.74/vb/08,04,usb,yes,27,30 2006.173.17:37:49.97/vblo/01,629.99,yes,locked 2006.173.17:37:49.97/vblo/02,634.99,yes,locked 2006.173.17:37:49.97/vblo/03,649.99,yes,locked 2006.173.17:37:49.97/vblo/04,679.99,yes,locked 2006.173.17:37:49.97/vblo/05,709.99,yes,locked 2006.173.17:37:49.97/vblo/06,719.99,yes,locked 2006.173.17:37:49.97/vblo/07,734.99,yes,locked 2006.173.17:37:49.97/vblo/08,744.99,yes,locked 2006.173.17:37:50.12/vabw/8 2006.173.17:37:50.27/vbbw/8 2006.173.17:37:50.36/xfe/off,on,15.2 2006.173.17:37:50.74/ifatt/23,28,28,28 2006.173.17:37:51.08/fmout-gps/S +3.97E-07 2006.173.17:37:51.12:!2006.173.17:38:57 2006.173.17:38:57.00:data_valid=off 2006.173.17:38:57.00:"et 2006.173.17:38:57.00:!+3s 2006.173.17:39:00.01:"tape 2006.173.17:39:00.01:postob 2006.173.17:39:00.17/cable/+6.5136E-03 2006.173.17:39:00.17/wx/20.21,1002.3,100 2006.173.17:39:01.08/fmout-gps/S +3.98E-07 2006.173.17:39:01.08:scan_name=173-1741,jd0606,40 2006.173.17:39:01.08:source=3c454.3,225357.75,160853.6,2000.0,ccw 2006.173.17:39:02.14#flagr#flagr/antenna,new-source 2006.173.17:39:02.14:checkk5 2006.173.17:39:02.57/chk_autoobs//k5ts1/ autoobs is running! 2006.173.17:39:02.94/chk_autoobs//k5ts2/ autoobs is running! 2006.173.17:39:03.34/chk_autoobs//k5ts3/ autoobs is running! 2006.173.17:39:03.74/chk_autoobs//k5ts4/ autoobs is running! 2006.173.17:39:04.12/chk_obsdata//k5ts1/T1731737??a.dat file size is correct (nominal:280MB, actual:276MB). 2006.173.17:39:04.52/chk_obsdata//k5ts2/T1731737??b.dat file size is correct (nominal:280MB, actual:276MB). 2006.173.17:39:04.93/chk_obsdata//k5ts3/T1731737??c.dat file size is correct (nominal:280MB, actual:276MB). 2006.173.17:39:05.33/chk_obsdata//k5ts4/T1731737??d.dat file size is correct (nominal:280MB, actual:276MB). 2006.173.17:39:06.06/k5log//k5ts1_log_newline 2006.173.17:39:06.77/k5log//k5ts2_log_newline 2006.173.17:39:07.50/k5log//k5ts3_log_newline 2006.173.17:39:08.21/k5log//k5ts4_log_newline 2006.173.17:39:08.24/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.17:39:08.24:setupk4=1 2006.173.17:39:08.24$setupk4/echo=on 2006.173.17:39:08.24$setupk4/pcalon 2006.173.17:39:08.24$pcalon/"no phase cal control is implemented here 2006.173.17:39:08.24$setupk4/"tpicd=stop 2006.173.17:39:08.24$setupk4/"rec=synch_on 2006.173.17:39:08.24$setupk4/"rec_mode=128 2006.173.17:39:08.24$setupk4/!* 2006.173.17:39:08.24$setupk4/recpk4 2006.173.17:39:08.24$recpk4/recpatch= 2006.173.17:39:08.25$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.17:39:08.25$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.17:39:08.25$setupk4/vck44 2006.173.17:39:08.25$vck44/valo=1,524.99 2006.173.17:39:08.25#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.17:39:08.25#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.17:39:08.25#ibcon#ireg 17 cls_cnt 0 2006.173.17:39:08.25#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.17:39:08.25#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.17:39:08.25#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.17:39:08.25#ibcon#enter wrdev, iclass 36, count 0 2006.173.17:39:08.25#ibcon#first serial, iclass 36, count 0 2006.173.17:39:08.25#ibcon#enter sib2, iclass 36, count 0 2006.173.17:39:08.25#ibcon#flushed, iclass 36, count 0 2006.173.17:39:08.25#ibcon#about to write, iclass 36, count 0 2006.173.17:39:08.25#ibcon#wrote, iclass 36, count 0 2006.173.17:39:08.25#ibcon#about to read 3, iclass 36, count 0 2006.173.17:39:08.26#ibcon#read 3, iclass 36, count 0 2006.173.17:39:08.26#ibcon#about to read 4, iclass 36, count 0 2006.173.17:39:08.26#ibcon#read 4, iclass 36, count 0 2006.173.17:39:08.26#ibcon#about to read 5, iclass 36, count 0 2006.173.17:39:08.26#ibcon#read 5, iclass 36, count 0 2006.173.17:39:08.26#ibcon#about to read 6, iclass 36, count 0 2006.173.17:39:08.26#ibcon#read 6, iclass 36, count 0 2006.173.17:39:08.26#ibcon#end of sib2, iclass 36, count 0 2006.173.17:39:08.26#ibcon#*mode == 0, iclass 36, count 0 2006.173.17:39:08.26#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.17:39:08.26#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.17:39:08.26#ibcon#*before write, iclass 36, count 0 2006.173.17:39:08.26#ibcon#enter sib2, iclass 36, count 0 2006.173.17:39:08.26#ibcon#flushed, iclass 36, count 0 2006.173.17:39:08.26#ibcon#about to write, iclass 36, count 0 2006.173.17:39:08.26#ibcon#wrote, iclass 36, count 0 2006.173.17:39:08.26#ibcon#about to read 3, iclass 36, count 0 2006.173.17:39:08.31#ibcon#read 3, iclass 36, count 0 2006.173.17:39:08.31#ibcon#about to read 4, iclass 36, count 0 2006.173.17:39:08.31#ibcon#read 4, iclass 36, count 0 2006.173.17:39:08.31#ibcon#about to read 5, iclass 36, count 0 2006.173.17:39:08.31#ibcon#read 5, iclass 36, count 0 2006.173.17:39:08.31#ibcon#about to read 6, iclass 36, count 0 2006.173.17:39:08.31#ibcon#read 6, iclass 36, count 0 2006.173.17:39:08.31#ibcon#end of sib2, iclass 36, count 0 2006.173.17:39:08.31#ibcon#*after write, iclass 36, count 0 2006.173.17:39:08.31#ibcon#*before return 0, iclass 36, count 0 2006.173.17:39:08.31#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.17:39:08.31#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.17:39:08.31#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.17:39:08.31#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.17:39:08.31$vck44/va=1,7 2006.173.17:39:08.31#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.17:39:08.31#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.17:39:08.31#ibcon#ireg 11 cls_cnt 2 2006.173.17:39:08.31#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.17:39:08.31#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.17:39:08.31#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.17:39:08.31#ibcon#enter wrdev, iclass 38, count 2 2006.173.17:39:08.31#ibcon#first serial, iclass 38, count 2 2006.173.17:39:08.31#ibcon#enter sib2, iclass 38, count 2 2006.173.17:39:08.31#ibcon#flushed, iclass 38, count 2 2006.173.17:39:08.31#ibcon#about to write, iclass 38, count 2 2006.173.17:39:08.31#ibcon#wrote, iclass 38, count 2 2006.173.17:39:08.31#ibcon#about to read 3, iclass 38, count 2 2006.173.17:39:08.33#ibcon#read 3, iclass 38, count 2 2006.173.17:39:08.33#ibcon#about to read 4, iclass 38, count 2 2006.173.17:39:08.33#ibcon#read 4, iclass 38, count 2 2006.173.17:39:08.33#ibcon#about to read 5, iclass 38, count 2 2006.173.17:39:08.33#ibcon#read 5, iclass 38, count 2 2006.173.17:39:08.33#ibcon#about to read 6, iclass 38, count 2 2006.173.17:39:08.33#ibcon#read 6, iclass 38, count 2 2006.173.17:39:08.33#ibcon#end of sib2, iclass 38, count 2 2006.173.17:39:08.33#ibcon#*mode == 0, iclass 38, count 2 2006.173.17:39:08.33#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.17:39:08.33#ibcon#[25=AT01-07\r\n] 2006.173.17:39:08.33#ibcon#*before write, iclass 38, count 2 2006.173.17:39:08.33#ibcon#enter sib2, iclass 38, count 2 2006.173.17:39:08.33#ibcon#flushed, iclass 38, count 2 2006.173.17:39:08.33#ibcon#about to write, iclass 38, count 2 2006.173.17:39:08.33#ibcon#wrote, iclass 38, count 2 2006.173.17:39:08.33#ibcon#about to read 3, iclass 38, count 2 2006.173.17:39:08.36#ibcon#read 3, iclass 38, count 2 2006.173.17:39:08.36#ibcon#about to read 4, iclass 38, count 2 2006.173.17:39:08.36#ibcon#read 4, iclass 38, count 2 2006.173.17:39:08.36#ibcon#about to read 5, iclass 38, count 2 2006.173.17:39:08.36#ibcon#read 5, iclass 38, count 2 2006.173.17:39:08.36#ibcon#about to read 6, iclass 38, count 2 2006.173.17:39:08.36#ibcon#read 6, iclass 38, count 2 2006.173.17:39:08.36#ibcon#end of sib2, iclass 38, count 2 2006.173.17:39:08.36#ibcon#*after write, iclass 38, count 2 2006.173.17:39:08.36#ibcon#*before return 0, iclass 38, count 2 2006.173.17:39:08.36#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.17:39:08.36#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.17:39:08.36#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.17:39:08.36#ibcon#ireg 7 cls_cnt 0 2006.173.17:39:08.36#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.17:39:08.48#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.17:39:08.48#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.17:39:08.48#ibcon#enter wrdev, iclass 38, count 0 2006.173.17:39:08.48#ibcon#first serial, iclass 38, count 0 2006.173.17:39:08.48#ibcon#enter sib2, iclass 38, count 0 2006.173.17:39:08.48#ibcon#flushed, iclass 38, count 0 2006.173.17:39:08.48#ibcon#about to write, iclass 38, count 0 2006.173.17:39:08.48#ibcon#wrote, iclass 38, count 0 2006.173.17:39:08.48#ibcon#about to read 3, iclass 38, count 0 2006.173.17:39:08.50#ibcon#read 3, iclass 38, count 0 2006.173.17:39:08.50#ibcon#about to read 4, iclass 38, count 0 2006.173.17:39:08.50#ibcon#read 4, iclass 38, count 0 2006.173.17:39:08.50#ibcon#about to read 5, iclass 38, count 0 2006.173.17:39:08.50#ibcon#read 5, iclass 38, count 0 2006.173.17:39:08.50#ibcon#about to read 6, iclass 38, count 0 2006.173.17:39:08.50#ibcon#read 6, iclass 38, count 0 2006.173.17:39:08.50#ibcon#end of sib2, iclass 38, count 0 2006.173.17:39:08.50#ibcon#*mode == 0, iclass 38, count 0 2006.173.17:39:08.50#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.17:39:08.50#ibcon#[25=USB\r\n] 2006.173.17:39:08.50#ibcon#*before write, iclass 38, count 0 2006.173.17:39:08.50#ibcon#enter sib2, iclass 38, count 0 2006.173.17:39:08.50#ibcon#flushed, iclass 38, count 0 2006.173.17:39:08.50#ibcon#about to write, iclass 38, count 0 2006.173.17:39:08.50#ibcon#wrote, iclass 38, count 0 2006.173.17:39:08.50#ibcon#about to read 3, iclass 38, count 0 2006.173.17:39:08.53#ibcon#read 3, iclass 38, count 0 2006.173.17:39:08.53#ibcon#about to read 4, iclass 38, count 0 2006.173.17:39:08.53#ibcon#read 4, iclass 38, count 0 2006.173.17:39:08.53#ibcon#about to read 5, iclass 38, count 0 2006.173.17:39:08.53#ibcon#read 5, iclass 38, count 0 2006.173.17:39:08.53#ibcon#about to read 6, iclass 38, count 0 2006.173.17:39:08.53#ibcon#read 6, iclass 38, count 0 2006.173.17:39:08.53#ibcon#end of sib2, iclass 38, count 0 2006.173.17:39:08.53#ibcon#*after write, iclass 38, count 0 2006.173.17:39:08.53#ibcon#*before return 0, iclass 38, count 0 2006.173.17:39:08.53#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.17:39:08.53#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.17:39:08.53#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.17:39:08.53#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.17:39:08.53$vck44/valo=2,534.99 2006.173.17:39:08.53#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.17:39:08.53#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.17:39:08.53#ibcon#ireg 17 cls_cnt 0 2006.173.17:39:08.53#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.17:39:08.53#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.17:39:08.53#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.17:39:08.53#ibcon#enter wrdev, iclass 40, count 0 2006.173.17:39:08.53#ibcon#first serial, iclass 40, count 0 2006.173.17:39:08.53#ibcon#enter sib2, iclass 40, count 0 2006.173.17:39:08.53#ibcon#flushed, iclass 40, count 0 2006.173.17:39:08.53#ibcon#about to write, iclass 40, count 0 2006.173.17:39:08.53#ibcon#wrote, iclass 40, count 0 2006.173.17:39:08.53#ibcon#about to read 3, iclass 40, count 0 2006.173.17:39:08.55#ibcon#read 3, iclass 40, count 0 2006.173.17:39:08.55#ibcon#about to read 4, iclass 40, count 0 2006.173.17:39:08.55#ibcon#read 4, iclass 40, count 0 2006.173.17:39:08.55#ibcon#about to read 5, iclass 40, count 0 2006.173.17:39:08.55#ibcon#read 5, iclass 40, count 0 2006.173.17:39:08.55#ibcon#about to read 6, iclass 40, count 0 2006.173.17:39:08.55#ibcon#read 6, iclass 40, count 0 2006.173.17:39:08.55#ibcon#end of sib2, iclass 40, count 0 2006.173.17:39:08.55#ibcon#*mode == 0, iclass 40, count 0 2006.173.17:39:08.55#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.17:39:08.55#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.17:39:08.55#ibcon#*before write, iclass 40, count 0 2006.173.17:39:08.55#ibcon#enter sib2, iclass 40, count 0 2006.173.17:39:08.55#ibcon#flushed, iclass 40, count 0 2006.173.17:39:08.55#ibcon#about to write, iclass 40, count 0 2006.173.17:39:08.55#ibcon#wrote, iclass 40, count 0 2006.173.17:39:08.55#ibcon#about to read 3, iclass 40, count 0 2006.173.17:39:08.59#ibcon#read 3, iclass 40, count 0 2006.173.17:39:08.59#ibcon#about to read 4, iclass 40, count 0 2006.173.17:39:08.59#ibcon#read 4, iclass 40, count 0 2006.173.17:39:08.59#ibcon#about to read 5, iclass 40, count 0 2006.173.17:39:08.59#ibcon#read 5, iclass 40, count 0 2006.173.17:39:08.59#ibcon#about to read 6, iclass 40, count 0 2006.173.17:39:08.59#ibcon#read 6, iclass 40, count 0 2006.173.17:39:08.59#ibcon#end of sib2, iclass 40, count 0 2006.173.17:39:08.59#ibcon#*after write, iclass 40, count 0 2006.173.17:39:08.59#ibcon#*before return 0, iclass 40, count 0 2006.173.17:39:08.59#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.17:39:08.59#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.17:39:08.59#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.17:39:08.59#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.17:39:08.59$vck44/va=2,6 2006.173.17:39:08.59#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.17:39:08.59#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.17:39:08.59#ibcon#ireg 11 cls_cnt 2 2006.173.17:39:08.59#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.17:39:08.65#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.17:39:08.65#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.17:39:08.65#ibcon#enter wrdev, iclass 4, count 2 2006.173.17:39:08.65#ibcon#first serial, iclass 4, count 2 2006.173.17:39:08.65#ibcon#enter sib2, iclass 4, count 2 2006.173.17:39:08.65#ibcon#flushed, iclass 4, count 2 2006.173.17:39:08.65#ibcon#about to write, iclass 4, count 2 2006.173.17:39:08.65#ibcon#wrote, iclass 4, count 2 2006.173.17:39:08.65#ibcon#about to read 3, iclass 4, count 2 2006.173.17:39:08.67#ibcon#read 3, iclass 4, count 2 2006.173.17:39:08.67#ibcon#about to read 4, iclass 4, count 2 2006.173.17:39:08.67#ibcon#read 4, iclass 4, count 2 2006.173.17:39:08.67#ibcon#about to read 5, iclass 4, count 2 2006.173.17:39:08.67#ibcon#read 5, iclass 4, count 2 2006.173.17:39:08.67#ibcon#about to read 6, iclass 4, count 2 2006.173.17:39:08.67#ibcon#read 6, iclass 4, count 2 2006.173.17:39:08.67#ibcon#end of sib2, iclass 4, count 2 2006.173.17:39:08.67#ibcon#*mode == 0, iclass 4, count 2 2006.173.17:39:08.67#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.17:39:08.67#ibcon#[25=AT02-06\r\n] 2006.173.17:39:08.67#ibcon#*before write, iclass 4, count 2 2006.173.17:39:08.67#ibcon#enter sib2, iclass 4, count 2 2006.173.17:39:08.67#ibcon#flushed, iclass 4, count 2 2006.173.17:39:08.67#ibcon#about to write, iclass 4, count 2 2006.173.17:39:08.67#ibcon#wrote, iclass 4, count 2 2006.173.17:39:08.67#ibcon#about to read 3, iclass 4, count 2 2006.173.17:39:08.70#ibcon#read 3, iclass 4, count 2 2006.173.17:39:08.70#ibcon#about to read 4, iclass 4, count 2 2006.173.17:39:08.70#ibcon#read 4, iclass 4, count 2 2006.173.17:39:08.70#ibcon#about to read 5, iclass 4, count 2 2006.173.17:39:08.70#ibcon#read 5, iclass 4, count 2 2006.173.17:39:08.70#ibcon#about to read 6, iclass 4, count 2 2006.173.17:39:08.70#ibcon#read 6, iclass 4, count 2 2006.173.17:39:08.70#ibcon#end of sib2, iclass 4, count 2 2006.173.17:39:08.70#ibcon#*after write, iclass 4, count 2 2006.173.17:39:08.70#ibcon#*before return 0, iclass 4, count 2 2006.173.17:39:08.70#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.17:39:08.70#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.17:39:08.70#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.17:39:08.70#ibcon#ireg 7 cls_cnt 0 2006.173.17:39:08.70#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.17:39:08.82#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.17:39:08.82#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.17:39:08.82#ibcon#enter wrdev, iclass 4, count 0 2006.173.17:39:08.82#ibcon#first serial, iclass 4, count 0 2006.173.17:39:08.82#ibcon#enter sib2, iclass 4, count 0 2006.173.17:39:08.82#ibcon#flushed, iclass 4, count 0 2006.173.17:39:08.82#ibcon#about to write, iclass 4, count 0 2006.173.17:39:08.82#ibcon#wrote, iclass 4, count 0 2006.173.17:39:08.82#ibcon#about to read 3, iclass 4, count 0 2006.173.17:39:08.84#ibcon#read 3, iclass 4, count 0 2006.173.17:39:08.84#ibcon#about to read 4, iclass 4, count 0 2006.173.17:39:08.84#ibcon#read 4, iclass 4, count 0 2006.173.17:39:08.84#ibcon#about to read 5, iclass 4, count 0 2006.173.17:39:08.84#ibcon#read 5, iclass 4, count 0 2006.173.17:39:08.84#ibcon#about to read 6, iclass 4, count 0 2006.173.17:39:08.84#ibcon#read 6, iclass 4, count 0 2006.173.17:39:08.84#ibcon#end of sib2, iclass 4, count 0 2006.173.17:39:08.84#ibcon#*mode == 0, iclass 4, count 0 2006.173.17:39:08.84#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.17:39:08.84#ibcon#[25=USB\r\n] 2006.173.17:39:08.84#ibcon#*before write, iclass 4, count 0 2006.173.17:39:08.84#ibcon#enter sib2, iclass 4, count 0 2006.173.17:39:08.84#ibcon#flushed, iclass 4, count 0 2006.173.17:39:08.84#ibcon#about to write, iclass 4, count 0 2006.173.17:39:08.84#ibcon#wrote, iclass 4, count 0 2006.173.17:39:08.84#ibcon#about to read 3, iclass 4, count 0 2006.173.17:39:08.87#ibcon#read 3, iclass 4, count 0 2006.173.17:39:08.87#ibcon#about to read 4, iclass 4, count 0 2006.173.17:39:08.87#ibcon#read 4, iclass 4, count 0 2006.173.17:39:08.87#ibcon#about to read 5, iclass 4, count 0 2006.173.17:39:08.87#ibcon#read 5, iclass 4, count 0 2006.173.17:39:08.87#ibcon#about to read 6, iclass 4, count 0 2006.173.17:39:08.87#ibcon#read 6, iclass 4, count 0 2006.173.17:39:08.87#ibcon#end of sib2, iclass 4, count 0 2006.173.17:39:08.87#ibcon#*after write, iclass 4, count 0 2006.173.17:39:08.87#ibcon#*before return 0, iclass 4, count 0 2006.173.17:39:08.87#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.17:39:08.87#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.17:39:08.87#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.17:39:08.87#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.17:39:08.87$vck44/valo=3,564.99 2006.173.17:39:08.87#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.17:39:08.87#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.17:39:08.87#ibcon#ireg 17 cls_cnt 0 2006.173.17:39:08.87#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.17:39:08.87#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.17:39:08.87#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.17:39:08.87#ibcon#enter wrdev, iclass 6, count 0 2006.173.17:39:08.87#ibcon#first serial, iclass 6, count 0 2006.173.17:39:08.87#ibcon#enter sib2, iclass 6, count 0 2006.173.17:39:08.87#ibcon#flushed, iclass 6, count 0 2006.173.17:39:08.87#ibcon#about to write, iclass 6, count 0 2006.173.17:39:08.87#ibcon#wrote, iclass 6, count 0 2006.173.17:39:08.87#ibcon#about to read 3, iclass 6, count 0 2006.173.17:39:08.89#ibcon#read 3, iclass 6, count 0 2006.173.17:39:08.89#ibcon#about to read 4, iclass 6, count 0 2006.173.17:39:08.89#ibcon#read 4, iclass 6, count 0 2006.173.17:39:08.89#ibcon#about to read 5, iclass 6, count 0 2006.173.17:39:08.89#ibcon#read 5, iclass 6, count 0 2006.173.17:39:08.89#ibcon#about to read 6, iclass 6, count 0 2006.173.17:39:08.89#ibcon#read 6, iclass 6, count 0 2006.173.17:39:08.89#ibcon#end of sib2, iclass 6, count 0 2006.173.17:39:08.89#ibcon#*mode == 0, iclass 6, count 0 2006.173.17:39:08.89#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.17:39:08.89#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.17:39:08.89#ibcon#*before write, iclass 6, count 0 2006.173.17:39:08.89#ibcon#enter sib2, iclass 6, count 0 2006.173.17:39:08.89#ibcon#flushed, iclass 6, count 0 2006.173.17:39:08.89#ibcon#about to write, iclass 6, count 0 2006.173.17:39:08.89#ibcon#wrote, iclass 6, count 0 2006.173.17:39:08.89#ibcon#about to read 3, iclass 6, count 0 2006.173.17:39:08.93#ibcon#read 3, iclass 6, count 0 2006.173.17:39:08.93#ibcon#about to read 4, iclass 6, count 0 2006.173.17:39:08.93#ibcon#read 4, iclass 6, count 0 2006.173.17:39:08.93#ibcon#about to read 5, iclass 6, count 0 2006.173.17:39:08.93#ibcon#read 5, iclass 6, count 0 2006.173.17:39:08.93#ibcon#about to read 6, iclass 6, count 0 2006.173.17:39:08.93#ibcon#read 6, iclass 6, count 0 2006.173.17:39:08.93#ibcon#end of sib2, iclass 6, count 0 2006.173.17:39:08.93#ibcon#*after write, iclass 6, count 0 2006.173.17:39:08.93#ibcon#*before return 0, iclass 6, count 0 2006.173.17:39:08.93#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.17:39:08.93#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.17:39:08.93#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.17:39:08.93#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.17:39:08.93$vck44/va=3,5 2006.173.17:39:08.93#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.17:39:08.93#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.17:39:08.93#ibcon#ireg 11 cls_cnt 2 2006.173.17:39:08.93#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.17:39:08.99#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.17:39:08.99#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.17:39:08.99#ibcon#enter wrdev, iclass 10, count 2 2006.173.17:39:08.99#ibcon#first serial, iclass 10, count 2 2006.173.17:39:08.99#ibcon#enter sib2, iclass 10, count 2 2006.173.17:39:08.99#ibcon#flushed, iclass 10, count 2 2006.173.17:39:08.99#ibcon#about to write, iclass 10, count 2 2006.173.17:39:08.99#ibcon#wrote, iclass 10, count 2 2006.173.17:39:08.99#ibcon#about to read 3, iclass 10, count 2 2006.173.17:39:09.01#ibcon#read 3, iclass 10, count 2 2006.173.17:39:09.01#ibcon#about to read 4, iclass 10, count 2 2006.173.17:39:09.01#ibcon#read 4, iclass 10, count 2 2006.173.17:39:09.01#ibcon#about to read 5, iclass 10, count 2 2006.173.17:39:09.01#ibcon#read 5, iclass 10, count 2 2006.173.17:39:09.01#ibcon#about to read 6, iclass 10, count 2 2006.173.17:39:09.01#ibcon#read 6, iclass 10, count 2 2006.173.17:39:09.01#ibcon#end of sib2, iclass 10, count 2 2006.173.17:39:09.01#ibcon#*mode == 0, iclass 10, count 2 2006.173.17:39:09.01#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.17:39:09.01#ibcon#[25=AT03-05\r\n] 2006.173.17:39:09.01#ibcon#*before write, iclass 10, count 2 2006.173.17:39:09.01#ibcon#enter sib2, iclass 10, count 2 2006.173.17:39:09.01#ibcon#flushed, iclass 10, count 2 2006.173.17:39:09.01#ibcon#about to write, iclass 10, count 2 2006.173.17:39:09.01#ibcon#wrote, iclass 10, count 2 2006.173.17:39:09.01#ibcon#about to read 3, iclass 10, count 2 2006.173.17:39:09.04#ibcon#read 3, iclass 10, count 2 2006.173.17:39:09.04#ibcon#about to read 4, iclass 10, count 2 2006.173.17:39:09.04#ibcon#read 4, iclass 10, count 2 2006.173.17:39:09.04#ibcon#about to read 5, iclass 10, count 2 2006.173.17:39:09.04#ibcon#read 5, iclass 10, count 2 2006.173.17:39:09.04#ibcon#about to read 6, iclass 10, count 2 2006.173.17:39:09.04#ibcon#read 6, iclass 10, count 2 2006.173.17:39:09.04#ibcon#end of sib2, iclass 10, count 2 2006.173.17:39:09.04#ibcon#*after write, iclass 10, count 2 2006.173.17:39:09.04#ibcon#*before return 0, iclass 10, count 2 2006.173.17:39:09.04#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.17:39:09.04#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.17:39:09.04#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.17:39:09.04#ibcon#ireg 7 cls_cnt 0 2006.173.17:39:09.04#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.17:39:09.16#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.17:39:09.16#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.17:39:09.16#ibcon#enter wrdev, iclass 10, count 0 2006.173.17:39:09.16#ibcon#first serial, iclass 10, count 0 2006.173.17:39:09.16#ibcon#enter sib2, iclass 10, count 0 2006.173.17:39:09.16#ibcon#flushed, iclass 10, count 0 2006.173.17:39:09.16#ibcon#about to write, iclass 10, count 0 2006.173.17:39:09.16#ibcon#wrote, iclass 10, count 0 2006.173.17:39:09.16#ibcon#about to read 3, iclass 10, count 0 2006.173.17:39:09.18#ibcon#read 3, iclass 10, count 0 2006.173.17:39:09.18#ibcon#about to read 4, iclass 10, count 0 2006.173.17:39:09.18#ibcon#read 4, iclass 10, count 0 2006.173.17:39:09.18#ibcon#about to read 5, iclass 10, count 0 2006.173.17:39:09.18#ibcon#read 5, iclass 10, count 0 2006.173.17:39:09.18#ibcon#about to read 6, iclass 10, count 0 2006.173.17:39:09.18#ibcon#read 6, iclass 10, count 0 2006.173.17:39:09.18#ibcon#end of sib2, iclass 10, count 0 2006.173.17:39:09.18#ibcon#*mode == 0, iclass 10, count 0 2006.173.17:39:09.18#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.17:39:09.18#ibcon#[25=USB\r\n] 2006.173.17:39:09.18#ibcon#*before write, iclass 10, count 0 2006.173.17:39:09.18#ibcon#enter sib2, iclass 10, count 0 2006.173.17:39:09.18#ibcon#flushed, iclass 10, count 0 2006.173.17:39:09.18#ibcon#about to write, iclass 10, count 0 2006.173.17:39:09.18#ibcon#wrote, iclass 10, count 0 2006.173.17:39:09.18#ibcon#about to read 3, iclass 10, count 0 2006.173.17:39:09.21#ibcon#read 3, iclass 10, count 0 2006.173.17:39:09.21#ibcon#about to read 4, iclass 10, count 0 2006.173.17:39:09.21#ibcon#read 4, iclass 10, count 0 2006.173.17:39:09.21#ibcon#about to read 5, iclass 10, count 0 2006.173.17:39:09.21#ibcon#read 5, iclass 10, count 0 2006.173.17:39:09.21#ibcon#about to read 6, iclass 10, count 0 2006.173.17:39:09.21#ibcon#read 6, iclass 10, count 0 2006.173.17:39:09.21#ibcon#end of sib2, iclass 10, count 0 2006.173.17:39:09.21#ibcon#*after write, iclass 10, count 0 2006.173.17:39:09.21#ibcon#*before return 0, iclass 10, count 0 2006.173.17:39:09.21#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.17:39:09.21#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.17:39:09.21#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.17:39:09.21#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.17:39:09.21$vck44/valo=4,624.99 2006.173.17:39:09.21#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.17:39:09.21#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.17:39:09.21#ibcon#ireg 17 cls_cnt 0 2006.173.17:39:09.21#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.17:39:09.21#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.17:39:09.21#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.17:39:09.21#ibcon#enter wrdev, iclass 12, count 0 2006.173.17:39:09.21#ibcon#first serial, iclass 12, count 0 2006.173.17:39:09.21#ibcon#enter sib2, iclass 12, count 0 2006.173.17:39:09.21#ibcon#flushed, iclass 12, count 0 2006.173.17:39:09.21#ibcon#about to write, iclass 12, count 0 2006.173.17:39:09.21#ibcon#wrote, iclass 12, count 0 2006.173.17:39:09.21#ibcon#about to read 3, iclass 12, count 0 2006.173.17:39:09.23#ibcon#read 3, iclass 12, count 0 2006.173.17:39:09.23#ibcon#about to read 4, iclass 12, count 0 2006.173.17:39:09.23#ibcon#read 4, iclass 12, count 0 2006.173.17:39:09.23#ibcon#about to read 5, iclass 12, count 0 2006.173.17:39:09.23#ibcon#read 5, iclass 12, count 0 2006.173.17:39:09.23#ibcon#about to read 6, iclass 12, count 0 2006.173.17:39:09.23#ibcon#read 6, iclass 12, count 0 2006.173.17:39:09.23#ibcon#end of sib2, iclass 12, count 0 2006.173.17:39:09.23#ibcon#*mode == 0, iclass 12, count 0 2006.173.17:39:09.23#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.17:39:09.23#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.17:39:09.23#ibcon#*before write, iclass 12, count 0 2006.173.17:39:09.23#ibcon#enter sib2, iclass 12, count 0 2006.173.17:39:09.23#ibcon#flushed, iclass 12, count 0 2006.173.17:39:09.23#ibcon#about to write, iclass 12, count 0 2006.173.17:39:09.23#ibcon#wrote, iclass 12, count 0 2006.173.17:39:09.23#ibcon#about to read 3, iclass 12, count 0 2006.173.17:39:09.27#ibcon#read 3, iclass 12, count 0 2006.173.17:39:09.27#ibcon#about to read 4, iclass 12, count 0 2006.173.17:39:09.27#ibcon#read 4, iclass 12, count 0 2006.173.17:39:09.27#ibcon#about to read 5, iclass 12, count 0 2006.173.17:39:09.27#ibcon#read 5, iclass 12, count 0 2006.173.17:39:09.27#ibcon#about to read 6, iclass 12, count 0 2006.173.17:39:09.27#ibcon#read 6, iclass 12, count 0 2006.173.17:39:09.27#ibcon#end of sib2, iclass 12, count 0 2006.173.17:39:09.27#ibcon#*after write, iclass 12, count 0 2006.173.17:39:09.27#ibcon#*before return 0, iclass 12, count 0 2006.173.17:39:09.27#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.17:39:09.27#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.17:39:09.27#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.17:39:09.27#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.17:39:09.27$vck44/va=4,6 2006.173.17:39:09.27#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.17:39:09.27#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.17:39:09.27#ibcon#ireg 11 cls_cnt 2 2006.173.17:39:09.27#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.17:39:09.32#abcon#<5=/14 1.0 2.3 20.211001002.3\r\n> 2006.173.17:39:09.33#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.17:39:09.33#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.17:39:09.33#ibcon#enter wrdev, iclass 15, count 2 2006.173.17:39:09.33#ibcon#first serial, iclass 15, count 2 2006.173.17:39:09.33#ibcon#enter sib2, iclass 15, count 2 2006.173.17:39:09.33#ibcon#flushed, iclass 15, count 2 2006.173.17:39:09.33#ibcon#about to write, iclass 15, count 2 2006.173.17:39:09.33#ibcon#wrote, iclass 15, count 2 2006.173.17:39:09.33#ibcon#about to read 3, iclass 15, count 2 2006.173.17:39:09.34#abcon#{5=INTERFACE CLEAR} 2006.173.17:39:09.35#ibcon#read 3, iclass 15, count 2 2006.173.17:39:09.35#ibcon#about to read 4, iclass 15, count 2 2006.173.17:39:09.35#ibcon#read 4, iclass 15, count 2 2006.173.17:39:09.35#ibcon#about to read 5, iclass 15, count 2 2006.173.17:39:09.35#ibcon#read 5, iclass 15, count 2 2006.173.17:39:09.35#ibcon#about to read 6, iclass 15, count 2 2006.173.17:39:09.35#ibcon#read 6, iclass 15, count 2 2006.173.17:39:09.35#ibcon#end of sib2, iclass 15, count 2 2006.173.17:39:09.35#ibcon#*mode == 0, iclass 15, count 2 2006.173.17:39:09.35#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.17:39:09.35#ibcon#[25=AT04-06\r\n] 2006.173.17:39:09.35#ibcon#*before write, iclass 15, count 2 2006.173.17:39:09.35#ibcon#enter sib2, iclass 15, count 2 2006.173.17:39:09.35#ibcon#flushed, iclass 15, count 2 2006.173.17:39:09.35#ibcon#about to write, iclass 15, count 2 2006.173.17:39:09.35#ibcon#wrote, iclass 15, count 2 2006.173.17:39:09.35#ibcon#about to read 3, iclass 15, count 2 2006.173.17:39:09.38#ibcon#read 3, iclass 15, count 2 2006.173.17:39:09.38#ibcon#about to read 4, iclass 15, count 2 2006.173.17:39:09.38#ibcon#read 4, iclass 15, count 2 2006.173.17:39:09.38#ibcon#about to read 5, iclass 15, count 2 2006.173.17:39:09.38#ibcon#read 5, iclass 15, count 2 2006.173.17:39:09.38#ibcon#about to read 6, iclass 15, count 2 2006.173.17:39:09.38#ibcon#read 6, iclass 15, count 2 2006.173.17:39:09.38#ibcon#end of sib2, iclass 15, count 2 2006.173.17:39:09.38#ibcon#*after write, iclass 15, count 2 2006.173.17:39:09.38#ibcon#*before return 0, iclass 15, count 2 2006.173.17:39:09.38#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.17:39:09.38#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.17:39:09.38#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.17:39:09.38#ibcon#ireg 7 cls_cnt 0 2006.173.17:39:09.38#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.17:39:09.40#abcon#[5=S1D000X0/0*\r\n] 2006.173.17:39:09.50#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.17:39:09.50#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.17:39:09.50#ibcon#enter wrdev, iclass 15, count 0 2006.173.17:39:09.50#ibcon#first serial, iclass 15, count 0 2006.173.17:39:09.50#ibcon#enter sib2, iclass 15, count 0 2006.173.17:39:09.50#ibcon#flushed, iclass 15, count 0 2006.173.17:39:09.50#ibcon#about to write, iclass 15, count 0 2006.173.17:39:09.50#ibcon#wrote, iclass 15, count 0 2006.173.17:39:09.50#ibcon#about to read 3, iclass 15, count 0 2006.173.17:39:09.52#ibcon#read 3, iclass 15, count 0 2006.173.17:39:09.52#ibcon#about to read 4, iclass 15, count 0 2006.173.17:39:09.52#ibcon#read 4, iclass 15, count 0 2006.173.17:39:09.52#ibcon#about to read 5, iclass 15, count 0 2006.173.17:39:09.52#ibcon#read 5, iclass 15, count 0 2006.173.17:39:09.52#ibcon#about to read 6, iclass 15, count 0 2006.173.17:39:09.52#ibcon#read 6, iclass 15, count 0 2006.173.17:39:09.52#ibcon#end of sib2, iclass 15, count 0 2006.173.17:39:09.52#ibcon#*mode == 0, iclass 15, count 0 2006.173.17:39:09.52#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.17:39:09.52#ibcon#[25=USB\r\n] 2006.173.17:39:09.52#ibcon#*before write, iclass 15, count 0 2006.173.17:39:09.52#ibcon#enter sib2, iclass 15, count 0 2006.173.17:39:09.52#ibcon#flushed, iclass 15, count 0 2006.173.17:39:09.52#ibcon#about to write, iclass 15, count 0 2006.173.17:39:09.52#ibcon#wrote, iclass 15, count 0 2006.173.17:39:09.52#ibcon#about to read 3, iclass 15, count 0 2006.173.17:39:09.55#ibcon#read 3, iclass 15, count 0 2006.173.17:39:09.55#ibcon#about to read 4, iclass 15, count 0 2006.173.17:39:09.55#ibcon#read 4, iclass 15, count 0 2006.173.17:39:09.55#ibcon#about to read 5, iclass 15, count 0 2006.173.17:39:09.55#ibcon#read 5, iclass 15, count 0 2006.173.17:39:09.55#ibcon#about to read 6, iclass 15, count 0 2006.173.17:39:09.55#ibcon#read 6, iclass 15, count 0 2006.173.17:39:09.55#ibcon#end of sib2, iclass 15, count 0 2006.173.17:39:09.55#ibcon#*after write, iclass 15, count 0 2006.173.17:39:09.55#ibcon#*before return 0, iclass 15, count 0 2006.173.17:39:09.55#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.17:39:09.55#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.17:39:09.55#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.17:39:09.55#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.17:39:09.55$vck44/valo=5,734.99 2006.173.17:39:09.55#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.17:39:09.55#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.17:39:09.55#ibcon#ireg 17 cls_cnt 0 2006.173.17:39:09.55#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.17:39:09.55#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.17:39:09.55#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.17:39:09.55#ibcon#enter wrdev, iclass 20, count 0 2006.173.17:39:09.55#ibcon#first serial, iclass 20, count 0 2006.173.17:39:09.55#ibcon#enter sib2, iclass 20, count 0 2006.173.17:39:09.55#ibcon#flushed, iclass 20, count 0 2006.173.17:39:09.55#ibcon#about to write, iclass 20, count 0 2006.173.17:39:09.55#ibcon#wrote, iclass 20, count 0 2006.173.17:39:09.55#ibcon#about to read 3, iclass 20, count 0 2006.173.17:39:09.57#ibcon#read 3, iclass 20, count 0 2006.173.17:39:09.57#ibcon#about to read 4, iclass 20, count 0 2006.173.17:39:09.57#ibcon#read 4, iclass 20, count 0 2006.173.17:39:09.57#ibcon#about to read 5, iclass 20, count 0 2006.173.17:39:09.57#ibcon#read 5, iclass 20, count 0 2006.173.17:39:09.57#ibcon#about to read 6, iclass 20, count 0 2006.173.17:39:09.57#ibcon#read 6, iclass 20, count 0 2006.173.17:39:09.57#ibcon#end of sib2, iclass 20, count 0 2006.173.17:39:09.57#ibcon#*mode == 0, iclass 20, count 0 2006.173.17:39:09.57#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.17:39:09.57#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.17:39:09.57#ibcon#*before write, iclass 20, count 0 2006.173.17:39:09.57#ibcon#enter sib2, iclass 20, count 0 2006.173.17:39:09.57#ibcon#flushed, iclass 20, count 0 2006.173.17:39:09.57#ibcon#about to write, iclass 20, count 0 2006.173.17:39:09.57#ibcon#wrote, iclass 20, count 0 2006.173.17:39:09.57#ibcon#about to read 3, iclass 20, count 0 2006.173.17:39:09.61#ibcon#read 3, iclass 20, count 0 2006.173.17:39:09.61#ibcon#about to read 4, iclass 20, count 0 2006.173.17:39:09.61#ibcon#read 4, iclass 20, count 0 2006.173.17:39:09.61#ibcon#about to read 5, iclass 20, count 0 2006.173.17:39:09.61#ibcon#read 5, iclass 20, count 0 2006.173.17:39:09.61#ibcon#about to read 6, iclass 20, count 0 2006.173.17:39:09.61#ibcon#read 6, iclass 20, count 0 2006.173.17:39:09.61#ibcon#end of sib2, iclass 20, count 0 2006.173.17:39:09.61#ibcon#*after write, iclass 20, count 0 2006.173.17:39:09.61#ibcon#*before return 0, iclass 20, count 0 2006.173.17:39:09.61#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.17:39:09.61#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.17:39:09.61#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.17:39:09.61#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.17:39:09.61$vck44/va=5,4 2006.173.17:39:09.61#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.17:39:09.61#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.17:39:09.61#ibcon#ireg 11 cls_cnt 2 2006.173.17:39:09.61#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.17:39:09.67#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.17:39:09.67#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.17:39:09.67#ibcon#enter wrdev, iclass 22, count 2 2006.173.17:39:09.67#ibcon#first serial, iclass 22, count 2 2006.173.17:39:09.67#ibcon#enter sib2, iclass 22, count 2 2006.173.17:39:09.67#ibcon#flushed, iclass 22, count 2 2006.173.17:39:09.67#ibcon#about to write, iclass 22, count 2 2006.173.17:39:09.67#ibcon#wrote, iclass 22, count 2 2006.173.17:39:09.67#ibcon#about to read 3, iclass 22, count 2 2006.173.17:39:09.69#ibcon#read 3, iclass 22, count 2 2006.173.17:39:09.69#ibcon#about to read 4, iclass 22, count 2 2006.173.17:39:09.69#ibcon#read 4, iclass 22, count 2 2006.173.17:39:09.69#ibcon#about to read 5, iclass 22, count 2 2006.173.17:39:09.69#ibcon#read 5, iclass 22, count 2 2006.173.17:39:09.69#ibcon#about to read 6, iclass 22, count 2 2006.173.17:39:09.69#ibcon#read 6, iclass 22, count 2 2006.173.17:39:09.69#ibcon#end of sib2, iclass 22, count 2 2006.173.17:39:09.69#ibcon#*mode == 0, iclass 22, count 2 2006.173.17:39:09.69#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.17:39:09.69#ibcon#[25=AT05-04\r\n] 2006.173.17:39:09.69#ibcon#*before write, iclass 22, count 2 2006.173.17:39:09.69#ibcon#enter sib2, iclass 22, count 2 2006.173.17:39:09.69#ibcon#flushed, iclass 22, count 2 2006.173.17:39:09.69#ibcon#about to write, iclass 22, count 2 2006.173.17:39:09.69#ibcon#wrote, iclass 22, count 2 2006.173.17:39:09.69#ibcon#about to read 3, iclass 22, count 2 2006.173.17:39:09.72#ibcon#read 3, iclass 22, count 2 2006.173.17:39:09.72#ibcon#about to read 4, iclass 22, count 2 2006.173.17:39:09.72#ibcon#read 4, iclass 22, count 2 2006.173.17:39:09.72#ibcon#about to read 5, iclass 22, count 2 2006.173.17:39:09.72#ibcon#read 5, iclass 22, count 2 2006.173.17:39:09.72#ibcon#about to read 6, iclass 22, count 2 2006.173.17:39:09.72#ibcon#read 6, iclass 22, count 2 2006.173.17:39:09.72#ibcon#end of sib2, iclass 22, count 2 2006.173.17:39:09.72#ibcon#*after write, iclass 22, count 2 2006.173.17:39:09.72#ibcon#*before return 0, iclass 22, count 2 2006.173.17:39:09.72#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.17:39:09.72#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.17:39:09.72#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.17:39:09.72#ibcon#ireg 7 cls_cnt 0 2006.173.17:39:09.72#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.17:39:09.84#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.17:39:09.84#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.17:39:09.84#ibcon#enter wrdev, iclass 22, count 0 2006.173.17:39:09.84#ibcon#first serial, iclass 22, count 0 2006.173.17:39:09.84#ibcon#enter sib2, iclass 22, count 0 2006.173.17:39:09.84#ibcon#flushed, iclass 22, count 0 2006.173.17:39:09.84#ibcon#about to write, iclass 22, count 0 2006.173.17:39:09.84#ibcon#wrote, iclass 22, count 0 2006.173.17:39:09.84#ibcon#about to read 3, iclass 22, count 0 2006.173.17:39:09.86#ibcon#read 3, iclass 22, count 0 2006.173.17:39:09.86#ibcon#about to read 4, iclass 22, count 0 2006.173.17:39:09.86#ibcon#read 4, iclass 22, count 0 2006.173.17:39:09.86#ibcon#about to read 5, iclass 22, count 0 2006.173.17:39:09.86#ibcon#read 5, iclass 22, count 0 2006.173.17:39:09.86#ibcon#about to read 6, iclass 22, count 0 2006.173.17:39:09.86#ibcon#read 6, iclass 22, count 0 2006.173.17:39:09.86#ibcon#end of sib2, iclass 22, count 0 2006.173.17:39:09.86#ibcon#*mode == 0, iclass 22, count 0 2006.173.17:39:09.86#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.17:39:09.86#ibcon#[25=USB\r\n] 2006.173.17:39:09.86#ibcon#*before write, iclass 22, count 0 2006.173.17:39:09.86#ibcon#enter sib2, iclass 22, count 0 2006.173.17:39:09.86#ibcon#flushed, iclass 22, count 0 2006.173.17:39:09.86#ibcon#about to write, iclass 22, count 0 2006.173.17:39:09.86#ibcon#wrote, iclass 22, count 0 2006.173.17:39:09.86#ibcon#about to read 3, iclass 22, count 0 2006.173.17:39:09.89#ibcon#read 3, iclass 22, count 0 2006.173.17:39:09.89#ibcon#about to read 4, iclass 22, count 0 2006.173.17:39:09.89#ibcon#read 4, iclass 22, count 0 2006.173.17:39:09.89#ibcon#about to read 5, iclass 22, count 0 2006.173.17:39:09.89#ibcon#read 5, iclass 22, count 0 2006.173.17:39:09.89#ibcon#about to read 6, iclass 22, count 0 2006.173.17:39:09.89#ibcon#read 6, iclass 22, count 0 2006.173.17:39:09.89#ibcon#end of sib2, iclass 22, count 0 2006.173.17:39:09.89#ibcon#*after write, iclass 22, count 0 2006.173.17:39:09.89#ibcon#*before return 0, iclass 22, count 0 2006.173.17:39:09.89#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.17:39:09.89#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.17:39:09.89#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.17:39:09.89#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.17:39:09.89$vck44/valo=6,814.99 2006.173.17:39:09.89#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.17:39:09.89#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.17:39:09.89#ibcon#ireg 17 cls_cnt 0 2006.173.17:39:09.89#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.17:39:09.89#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.17:39:09.89#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.17:39:09.89#ibcon#enter wrdev, iclass 24, count 0 2006.173.17:39:09.89#ibcon#first serial, iclass 24, count 0 2006.173.17:39:09.89#ibcon#enter sib2, iclass 24, count 0 2006.173.17:39:09.89#ibcon#flushed, iclass 24, count 0 2006.173.17:39:09.89#ibcon#about to write, iclass 24, count 0 2006.173.17:39:09.89#ibcon#wrote, iclass 24, count 0 2006.173.17:39:09.89#ibcon#about to read 3, iclass 24, count 0 2006.173.17:39:09.91#ibcon#read 3, iclass 24, count 0 2006.173.17:39:09.91#ibcon#about to read 4, iclass 24, count 0 2006.173.17:39:09.91#ibcon#read 4, iclass 24, count 0 2006.173.17:39:09.91#ibcon#about to read 5, iclass 24, count 0 2006.173.17:39:09.91#ibcon#read 5, iclass 24, count 0 2006.173.17:39:09.91#ibcon#about to read 6, iclass 24, count 0 2006.173.17:39:09.91#ibcon#read 6, iclass 24, count 0 2006.173.17:39:09.91#ibcon#end of sib2, iclass 24, count 0 2006.173.17:39:09.91#ibcon#*mode == 0, iclass 24, count 0 2006.173.17:39:09.91#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.17:39:09.91#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.17:39:09.91#ibcon#*before write, iclass 24, count 0 2006.173.17:39:09.91#ibcon#enter sib2, iclass 24, count 0 2006.173.17:39:09.91#ibcon#flushed, iclass 24, count 0 2006.173.17:39:09.91#ibcon#about to write, iclass 24, count 0 2006.173.17:39:09.91#ibcon#wrote, iclass 24, count 0 2006.173.17:39:09.91#ibcon#about to read 3, iclass 24, count 0 2006.173.17:39:09.95#ibcon#read 3, iclass 24, count 0 2006.173.17:39:09.95#ibcon#about to read 4, iclass 24, count 0 2006.173.17:39:09.95#ibcon#read 4, iclass 24, count 0 2006.173.17:39:09.95#ibcon#about to read 5, iclass 24, count 0 2006.173.17:39:09.95#ibcon#read 5, iclass 24, count 0 2006.173.17:39:09.95#ibcon#about to read 6, iclass 24, count 0 2006.173.17:39:09.95#ibcon#read 6, iclass 24, count 0 2006.173.17:39:09.95#ibcon#end of sib2, iclass 24, count 0 2006.173.17:39:09.95#ibcon#*after write, iclass 24, count 0 2006.173.17:39:09.95#ibcon#*before return 0, iclass 24, count 0 2006.173.17:39:09.95#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.17:39:09.95#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.17:39:09.95#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.17:39:09.95#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.17:39:09.95$vck44/va=6,3 2006.173.17:39:09.95#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.17:39:09.95#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.17:39:09.95#ibcon#ireg 11 cls_cnt 2 2006.173.17:39:09.95#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.17:39:10.01#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.17:39:10.01#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.17:39:10.01#ibcon#enter wrdev, iclass 26, count 2 2006.173.17:39:10.01#ibcon#first serial, iclass 26, count 2 2006.173.17:39:10.01#ibcon#enter sib2, iclass 26, count 2 2006.173.17:39:10.01#ibcon#flushed, iclass 26, count 2 2006.173.17:39:10.01#ibcon#about to write, iclass 26, count 2 2006.173.17:39:10.01#ibcon#wrote, iclass 26, count 2 2006.173.17:39:10.01#ibcon#about to read 3, iclass 26, count 2 2006.173.17:39:10.03#ibcon#read 3, iclass 26, count 2 2006.173.17:39:10.03#ibcon#about to read 4, iclass 26, count 2 2006.173.17:39:10.03#ibcon#read 4, iclass 26, count 2 2006.173.17:39:10.03#ibcon#about to read 5, iclass 26, count 2 2006.173.17:39:10.03#ibcon#read 5, iclass 26, count 2 2006.173.17:39:10.03#ibcon#about to read 6, iclass 26, count 2 2006.173.17:39:10.03#ibcon#read 6, iclass 26, count 2 2006.173.17:39:10.03#ibcon#end of sib2, iclass 26, count 2 2006.173.17:39:10.03#ibcon#*mode == 0, iclass 26, count 2 2006.173.17:39:10.03#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.17:39:10.03#ibcon#[25=AT06-03\r\n] 2006.173.17:39:10.03#ibcon#*before write, iclass 26, count 2 2006.173.17:39:10.03#ibcon#enter sib2, iclass 26, count 2 2006.173.17:39:10.03#ibcon#flushed, iclass 26, count 2 2006.173.17:39:10.03#ibcon#about to write, iclass 26, count 2 2006.173.17:39:10.03#ibcon#wrote, iclass 26, count 2 2006.173.17:39:10.03#ibcon#about to read 3, iclass 26, count 2 2006.173.17:39:10.06#ibcon#read 3, iclass 26, count 2 2006.173.17:39:10.06#ibcon#about to read 4, iclass 26, count 2 2006.173.17:39:10.06#ibcon#read 4, iclass 26, count 2 2006.173.17:39:10.06#ibcon#about to read 5, iclass 26, count 2 2006.173.17:39:10.06#ibcon#read 5, iclass 26, count 2 2006.173.17:39:10.06#ibcon#about to read 6, iclass 26, count 2 2006.173.17:39:10.06#ibcon#read 6, iclass 26, count 2 2006.173.17:39:10.06#ibcon#end of sib2, iclass 26, count 2 2006.173.17:39:10.06#ibcon#*after write, iclass 26, count 2 2006.173.17:39:10.06#ibcon#*before return 0, iclass 26, count 2 2006.173.17:39:10.06#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.17:39:10.06#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.17:39:10.06#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.17:39:10.06#ibcon#ireg 7 cls_cnt 0 2006.173.17:39:10.06#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.17:39:10.18#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.17:39:10.18#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.17:39:10.18#ibcon#enter wrdev, iclass 26, count 0 2006.173.17:39:10.18#ibcon#first serial, iclass 26, count 0 2006.173.17:39:10.18#ibcon#enter sib2, iclass 26, count 0 2006.173.17:39:10.18#ibcon#flushed, iclass 26, count 0 2006.173.17:39:10.18#ibcon#about to write, iclass 26, count 0 2006.173.17:39:10.18#ibcon#wrote, iclass 26, count 0 2006.173.17:39:10.18#ibcon#about to read 3, iclass 26, count 0 2006.173.17:39:10.20#ibcon#read 3, iclass 26, count 0 2006.173.17:39:10.20#ibcon#about to read 4, iclass 26, count 0 2006.173.17:39:10.20#ibcon#read 4, iclass 26, count 0 2006.173.17:39:10.20#ibcon#about to read 5, iclass 26, count 0 2006.173.17:39:10.20#ibcon#read 5, iclass 26, count 0 2006.173.17:39:10.20#ibcon#about to read 6, iclass 26, count 0 2006.173.17:39:10.20#ibcon#read 6, iclass 26, count 0 2006.173.17:39:10.20#ibcon#end of sib2, iclass 26, count 0 2006.173.17:39:10.20#ibcon#*mode == 0, iclass 26, count 0 2006.173.17:39:10.20#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.17:39:10.20#ibcon#[25=USB\r\n] 2006.173.17:39:10.20#ibcon#*before write, iclass 26, count 0 2006.173.17:39:10.20#ibcon#enter sib2, iclass 26, count 0 2006.173.17:39:10.20#ibcon#flushed, iclass 26, count 0 2006.173.17:39:10.20#ibcon#about to write, iclass 26, count 0 2006.173.17:39:10.20#ibcon#wrote, iclass 26, count 0 2006.173.17:39:10.20#ibcon#about to read 3, iclass 26, count 0 2006.173.17:39:10.23#ibcon#read 3, iclass 26, count 0 2006.173.17:39:10.23#ibcon#about to read 4, iclass 26, count 0 2006.173.17:39:10.23#ibcon#read 4, iclass 26, count 0 2006.173.17:39:10.23#ibcon#about to read 5, iclass 26, count 0 2006.173.17:39:10.23#ibcon#read 5, iclass 26, count 0 2006.173.17:39:10.23#ibcon#about to read 6, iclass 26, count 0 2006.173.17:39:10.23#ibcon#read 6, iclass 26, count 0 2006.173.17:39:10.23#ibcon#end of sib2, iclass 26, count 0 2006.173.17:39:10.23#ibcon#*after write, iclass 26, count 0 2006.173.17:39:10.23#ibcon#*before return 0, iclass 26, count 0 2006.173.17:39:10.23#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.17:39:10.23#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.17:39:10.23#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.17:39:10.23#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.17:39:10.23$vck44/valo=7,864.99 2006.173.17:39:10.23#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.17:39:10.23#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.17:39:10.23#ibcon#ireg 17 cls_cnt 0 2006.173.17:39:10.23#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.17:39:10.23#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.17:39:10.23#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.17:39:10.23#ibcon#enter wrdev, iclass 28, count 0 2006.173.17:39:10.23#ibcon#first serial, iclass 28, count 0 2006.173.17:39:10.23#ibcon#enter sib2, iclass 28, count 0 2006.173.17:39:10.23#ibcon#flushed, iclass 28, count 0 2006.173.17:39:10.23#ibcon#about to write, iclass 28, count 0 2006.173.17:39:10.23#ibcon#wrote, iclass 28, count 0 2006.173.17:39:10.23#ibcon#about to read 3, iclass 28, count 0 2006.173.17:39:10.25#ibcon#read 3, iclass 28, count 0 2006.173.17:39:10.25#ibcon#about to read 4, iclass 28, count 0 2006.173.17:39:10.25#ibcon#read 4, iclass 28, count 0 2006.173.17:39:10.25#ibcon#about to read 5, iclass 28, count 0 2006.173.17:39:10.25#ibcon#read 5, iclass 28, count 0 2006.173.17:39:10.25#ibcon#about to read 6, iclass 28, count 0 2006.173.17:39:10.25#ibcon#read 6, iclass 28, count 0 2006.173.17:39:10.25#ibcon#end of sib2, iclass 28, count 0 2006.173.17:39:10.25#ibcon#*mode == 0, iclass 28, count 0 2006.173.17:39:10.25#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.17:39:10.25#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.17:39:10.25#ibcon#*before write, iclass 28, count 0 2006.173.17:39:10.25#ibcon#enter sib2, iclass 28, count 0 2006.173.17:39:10.25#ibcon#flushed, iclass 28, count 0 2006.173.17:39:10.25#ibcon#about to write, iclass 28, count 0 2006.173.17:39:10.25#ibcon#wrote, iclass 28, count 0 2006.173.17:39:10.25#ibcon#about to read 3, iclass 28, count 0 2006.173.17:39:10.29#ibcon#read 3, iclass 28, count 0 2006.173.17:39:10.29#ibcon#about to read 4, iclass 28, count 0 2006.173.17:39:10.29#ibcon#read 4, iclass 28, count 0 2006.173.17:39:10.29#ibcon#about to read 5, iclass 28, count 0 2006.173.17:39:10.29#ibcon#read 5, iclass 28, count 0 2006.173.17:39:10.29#ibcon#about to read 6, iclass 28, count 0 2006.173.17:39:10.29#ibcon#read 6, iclass 28, count 0 2006.173.17:39:10.29#ibcon#end of sib2, iclass 28, count 0 2006.173.17:39:10.29#ibcon#*after write, iclass 28, count 0 2006.173.17:39:10.29#ibcon#*before return 0, iclass 28, count 0 2006.173.17:39:10.29#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.17:39:10.29#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.17:39:10.29#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.17:39:10.29#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.17:39:10.29$vck44/va=7,4 2006.173.17:39:10.29#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.17:39:10.29#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.17:39:10.29#ibcon#ireg 11 cls_cnt 2 2006.173.17:39:10.29#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.17:39:10.35#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.17:39:10.35#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.17:39:10.35#ibcon#enter wrdev, iclass 30, count 2 2006.173.17:39:10.35#ibcon#first serial, iclass 30, count 2 2006.173.17:39:10.35#ibcon#enter sib2, iclass 30, count 2 2006.173.17:39:10.35#ibcon#flushed, iclass 30, count 2 2006.173.17:39:10.35#ibcon#about to write, iclass 30, count 2 2006.173.17:39:10.35#ibcon#wrote, iclass 30, count 2 2006.173.17:39:10.35#ibcon#about to read 3, iclass 30, count 2 2006.173.17:39:10.37#ibcon#read 3, iclass 30, count 2 2006.173.17:39:10.37#ibcon#about to read 4, iclass 30, count 2 2006.173.17:39:10.37#ibcon#read 4, iclass 30, count 2 2006.173.17:39:10.37#ibcon#about to read 5, iclass 30, count 2 2006.173.17:39:10.37#ibcon#read 5, iclass 30, count 2 2006.173.17:39:10.37#ibcon#about to read 6, iclass 30, count 2 2006.173.17:39:10.37#ibcon#read 6, iclass 30, count 2 2006.173.17:39:10.37#ibcon#end of sib2, iclass 30, count 2 2006.173.17:39:10.37#ibcon#*mode == 0, iclass 30, count 2 2006.173.17:39:10.37#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.17:39:10.37#ibcon#[25=AT07-04\r\n] 2006.173.17:39:10.37#ibcon#*before write, iclass 30, count 2 2006.173.17:39:10.37#ibcon#enter sib2, iclass 30, count 2 2006.173.17:39:10.37#ibcon#flushed, iclass 30, count 2 2006.173.17:39:10.37#ibcon#about to write, iclass 30, count 2 2006.173.17:39:10.37#ibcon#wrote, iclass 30, count 2 2006.173.17:39:10.37#ibcon#about to read 3, iclass 30, count 2 2006.173.17:39:10.40#ibcon#read 3, iclass 30, count 2 2006.173.17:39:10.40#ibcon#about to read 4, iclass 30, count 2 2006.173.17:39:10.40#ibcon#read 4, iclass 30, count 2 2006.173.17:39:10.40#ibcon#about to read 5, iclass 30, count 2 2006.173.17:39:10.40#ibcon#read 5, iclass 30, count 2 2006.173.17:39:10.40#ibcon#about to read 6, iclass 30, count 2 2006.173.17:39:10.40#ibcon#read 6, iclass 30, count 2 2006.173.17:39:10.40#ibcon#end of sib2, iclass 30, count 2 2006.173.17:39:10.40#ibcon#*after write, iclass 30, count 2 2006.173.17:39:10.40#ibcon#*before return 0, iclass 30, count 2 2006.173.17:39:10.40#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.17:39:10.40#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.17:39:10.40#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.17:39:10.40#ibcon#ireg 7 cls_cnt 0 2006.173.17:39:10.40#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.17:39:10.52#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.17:39:10.52#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.17:39:10.52#ibcon#enter wrdev, iclass 30, count 0 2006.173.17:39:10.52#ibcon#first serial, iclass 30, count 0 2006.173.17:39:10.52#ibcon#enter sib2, iclass 30, count 0 2006.173.17:39:10.52#ibcon#flushed, iclass 30, count 0 2006.173.17:39:10.52#ibcon#about to write, iclass 30, count 0 2006.173.17:39:10.52#ibcon#wrote, iclass 30, count 0 2006.173.17:39:10.52#ibcon#about to read 3, iclass 30, count 0 2006.173.17:39:10.54#ibcon#read 3, iclass 30, count 0 2006.173.17:39:10.54#ibcon#about to read 4, iclass 30, count 0 2006.173.17:39:10.54#ibcon#read 4, iclass 30, count 0 2006.173.17:39:10.54#ibcon#about to read 5, iclass 30, count 0 2006.173.17:39:10.54#ibcon#read 5, iclass 30, count 0 2006.173.17:39:10.54#ibcon#about to read 6, iclass 30, count 0 2006.173.17:39:10.54#ibcon#read 6, iclass 30, count 0 2006.173.17:39:10.54#ibcon#end of sib2, iclass 30, count 0 2006.173.17:39:10.54#ibcon#*mode == 0, iclass 30, count 0 2006.173.17:39:10.54#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.17:39:10.54#ibcon#[25=USB\r\n] 2006.173.17:39:10.54#ibcon#*before write, iclass 30, count 0 2006.173.17:39:10.54#ibcon#enter sib2, iclass 30, count 0 2006.173.17:39:10.54#ibcon#flushed, iclass 30, count 0 2006.173.17:39:10.54#ibcon#about to write, iclass 30, count 0 2006.173.17:39:10.54#ibcon#wrote, iclass 30, count 0 2006.173.17:39:10.54#ibcon#about to read 3, iclass 30, count 0 2006.173.17:39:10.57#ibcon#read 3, iclass 30, count 0 2006.173.17:39:10.57#ibcon#about to read 4, iclass 30, count 0 2006.173.17:39:10.57#ibcon#read 4, iclass 30, count 0 2006.173.17:39:10.57#ibcon#about to read 5, iclass 30, count 0 2006.173.17:39:10.57#ibcon#read 5, iclass 30, count 0 2006.173.17:39:10.57#ibcon#about to read 6, iclass 30, count 0 2006.173.17:39:10.57#ibcon#read 6, iclass 30, count 0 2006.173.17:39:10.57#ibcon#end of sib2, iclass 30, count 0 2006.173.17:39:10.57#ibcon#*after write, iclass 30, count 0 2006.173.17:39:10.57#ibcon#*before return 0, iclass 30, count 0 2006.173.17:39:10.57#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.17:39:10.57#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.17:39:10.57#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.17:39:10.57#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.17:39:10.57$vck44/valo=8,884.99 2006.173.17:39:10.57#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.17:39:10.57#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.17:39:10.57#ibcon#ireg 17 cls_cnt 0 2006.173.17:39:10.57#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.17:39:10.57#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.17:39:10.57#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.17:39:10.57#ibcon#enter wrdev, iclass 32, count 0 2006.173.17:39:10.57#ibcon#first serial, iclass 32, count 0 2006.173.17:39:10.57#ibcon#enter sib2, iclass 32, count 0 2006.173.17:39:10.57#ibcon#flushed, iclass 32, count 0 2006.173.17:39:10.57#ibcon#about to write, iclass 32, count 0 2006.173.17:39:10.57#ibcon#wrote, iclass 32, count 0 2006.173.17:39:10.57#ibcon#about to read 3, iclass 32, count 0 2006.173.17:39:10.59#ibcon#read 3, iclass 32, count 0 2006.173.17:39:10.59#ibcon#about to read 4, iclass 32, count 0 2006.173.17:39:10.59#ibcon#read 4, iclass 32, count 0 2006.173.17:39:10.59#ibcon#about to read 5, iclass 32, count 0 2006.173.17:39:10.59#ibcon#read 5, iclass 32, count 0 2006.173.17:39:10.59#ibcon#about to read 6, iclass 32, count 0 2006.173.17:39:10.59#ibcon#read 6, iclass 32, count 0 2006.173.17:39:10.59#ibcon#end of sib2, iclass 32, count 0 2006.173.17:39:10.59#ibcon#*mode == 0, iclass 32, count 0 2006.173.17:39:10.59#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.17:39:10.59#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.17:39:10.59#ibcon#*before write, iclass 32, count 0 2006.173.17:39:10.59#ibcon#enter sib2, iclass 32, count 0 2006.173.17:39:10.59#ibcon#flushed, iclass 32, count 0 2006.173.17:39:10.59#ibcon#about to write, iclass 32, count 0 2006.173.17:39:10.59#ibcon#wrote, iclass 32, count 0 2006.173.17:39:10.59#ibcon#about to read 3, iclass 32, count 0 2006.173.17:39:10.63#ibcon#read 3, iclass 32, count 0 2006.173.17:39:10.63#ibcon#about to read 4, iclass 32, count 0 2006.173.17:39:10.63#ibcon#read 4, iclass 32, count 0 2006.173.17:39:10.63#ibcon#about to read 5, iclass 32, count 0 2006.173.17:39:10.63#ibcon#read 5, iclass 32, count 0 2006.173.17:39:10.63#ibcon#about to read 6, iclass 32, count 0 2006.173.17:39:10.63#ibcon#read 6, iclass 32, count 0 2006.173.17:39:10.63#ibcon#end of sib2, iclass 32, count 0 2006.173.17:39:10.63#ibcon#*after write, iclass 32, count 0 2006.173.17:39:10.63#ibcon#*before return 0, iclass 32, count 0 2006.173.17:39:10.63#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.17:39:10.63#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.17:39:10.63#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.17:39:10.63#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.17:39:10.63$vck44/va=8,4 2006.173.17:39:10.63#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.17:39:10.63#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.17:39:10.63#ibcon#ireg 11 cls_cnt 2 2006.173.17:39:10.63#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.17:39:10.69#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.17:39:10.69#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.17:39:10.69#ibcon#enter wrdev, iclass 34, count 2 2006.173.17:39:10.69#ibcon#first serial, iclass 34, count 2 2006.173.17:39:10.69#ibcon#enter sib2, iclass 34, count 2 2006.173.17:39:10.69#ibcon#flushed, iclass 34, count 2 2006.173.17:39:10.69#ibcon#about to write, iclass 34, count 2 2006.173.17:39:10.69#ibcon#wrote, iclass 34, count 2 2006.173.17:39:10.69#ibcon#about to read 3, iclass 34, count 2 2006.173.17:39:10.71#ibcon#read 3, iclass 34, count 2 2006.173.17:39:10.71#ibcon#about to read 4, iclass 34, count 2 2006.173.17:39:10.71#ibcon#read 4, iclass 34, count 2 2006.173.17:39:10.71#ibcon#about to read 5, iclass 34, count 2 2006.173.17:39:10.71#ibcon#read 5, iclass 34, count 2 2006.173.17:39:10.71#ibcon#about to read 6, iclass 34, count 2 2006.173.17:39:10.71#ibcon#read 6, iclass 34, count 2 2006.173.17:39:10.71#ibcon#end of sib2, iclass 34, count 2 2006.173.17:39:10.71#ibcon#*mode == 0, iclass 34, count 2 2006.173.17:39:10.71#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.17:39:10.71#ibcon#[25=AT08-04\r\n] 2006.173.17:39:10.71#ibcon#*before write, iclass 34, count 2 2006.173.17:39:10.71#ibcon#enter sib2, iclass 34, count 2 2006.173.17:39:10.71#ibcon#flushed, iclass 34, count 2 2006.173.17:39:10.71#ibcon#about to write, iclass 34, count 2 2006.173.17:39:10.71#ibcon#wrote, iclass 34, count 2 2006.173.17:39:10.71#ibcon#about to read 3, iclass 34, count 2 2006.173.17:39:10.74#ibcon#read 3, iclass 34, count 2 2006.173.17:39:10.74#ibcon#about to read 4, iclass 34, count 2 2006.173.17:39:10.74#ibcon#read 4, iclass 34, count 2 2006.173.17:39:10.74#ibcon#about to read 5, iclass 34, count 2 2006.173.17:39:10.74#ibcon#read 5, iclass 34, count 2 2006.173.17:39:10.74#ibcon#about to read 6, iclass 34, count 2 2006.173.17:39:10.74#ibcon#read 6, iclass 34, count 2 2006.173.17:39:10.74#ibcon#end of sib2, iclass 34, count 2 2006.173.17:39:10.74#ibcon#*after write, iclass 34, count 2 2006.173.17:39:10.74#ibcon#*before return 0, iclass 34, count 2 2006.173.17:39:10.74#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.17:39:10.74#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.17:39:10.74#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.17:39:10.74#ibcon#ireg 7 cls_cnt 0 2006.173.17:39:10.74#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.17:39:10.86#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.17:39:10.86#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.17:39:10.86#ibcon#enter wrdev, iclass 34, count 0 2006.173.17:39:10.86#ibcon#first serial, iclass 34, count 0 2006.173.17:39:10.86#ibcon#enter sib2, iclass 34, count 0 2006.173.17:39:10.86#ibcon#flushed, iclass 34, count 0 2006.173.17:39:10.86#ibcon#about to write, iclass 34, count 0 2006.173.17:39:10.86#ibcon#wrote, iclass 34, count 0 2006.173.17:39:10.86#ibcon#about to read 3, iclass 34, count 0 2006.173.17:39:10.88#ibcon#read 3, iclass 34, count 0 2006.173.17:39:10.88#ibcon#about to read 4, iclass 34, count 0 2006.173.17:39:10.88#ibcon#read 4, iclass 34, count 0 2006.173.17:39:10.88#ibcon#about to read 5, iclass 34, count 0 2006.173.17:39:10.88#ibcon#read 5, iclass 34, count 0 2006.173.17:39:10.88#ibcon#about to read 6, iclass 34, count 0 2006.173.17:39:10.88#ibcon#read 6, iclass 34, count 0 2006.173.17:39:10.88#ibcon#end of sib2, iclass 34, count 0 2006.173.17:39:10.88#ibcon#*mode == 0, iclass 34, count 0 2006.173.17:39:10.88#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.17:39:10.88#ibcon#[25=USB\r\n] 2006.173.17:39:10.88#ibcon#*before write, iclass 34, count 0 2006.173.17:39:10.88#ibcon#enter sib2, iclass 34, count 0 2006.173.17:39:10.88#ibcon#flushed, iclass 34, count 0 2006.173.17:39:10.88#ibcon#about to write, iclass 34, count 0 2006.173.17:39:10.88#ibcon#wrote, iclass 34, count 0 2006.173.17:39:10.88#ibcon#about to read 3, iclass 34, count 0 2006.173.17:39:10.91#ibcon#read 3, iclass 34, count 0 2006.173.17:39:10.91#ibcon#about to read 4, iclass 34, count 0 2006.173.17:39:10.91#ibcon#read 4, iclass 34, count 0 2006.173.17:39:10.91#ibcon#about to read 5, iclass 34, count 0 2006.173.17:39:10.91#ibcon#read 5, iclass 34, count 0 2006.173.17:39:10.91#ibcon#about to read 6, iclass 34, count 0 2006.173.17:39:10.91#ibcon#read 6, iclass 34, count 0 2006.173.17:39:10.91#ibcon#end of sib2, iclass 34, count 0 2006.173.17:39:10.91#ibcon#*after write, iclass 34, count 0 2006.173.17:39:10.91#ibcon#*before return 0, iclass 34, count 0 2006.173.17:39:10.91#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.17:39:10.91#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.17:39:10.91#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.17:39:10.91#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.17:39:10.91$vck44/vblo=1,629.99 2006.173.17:39:10.91#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.17:39:10.91#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.17:39:10.91#ibcon#ireg 17 cls_cnt 0 2006.173.17:39:10.91#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.17:39:10.91#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.17:39:10.91#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.17:39:10.91#ibcon#enter wrdev, iclass 36, count 0 2006.173.17:39:10.91#ibcon#first serial, iclass 36, count 0 2006.173.17:39:10.91#ibcon#enter sib2, iclass 36, count 0 2006.173.17:39:10.91#ibcon#flushed, iclass 36, count 0 2006.173.17:39:10.91#ibcon#about to write, iclass 36, count 0 2006.173.17:39:10.91#ibcon#wrote, iclass 36, count 0 2006.173.17:39:10.91#ibcon#about to read 3, iclass 36, count 0 2006.173.17:39:10.93#ibcon#read 3, iclass 36, count 0 2006.173.17:39:10.93#ibcon#about to read 4, iclass 36, count 0 2006.173.17:39:10.93#ibcon#read 4, iclass 36, count 0 2006.173.17:39:10.93#ibcon#about to read 5, iclass 36, count 0 2006.173.17:39:10.93#ibcon#read 5, iclass 36, count 0 2006.173.17:39:10.93#ibcon#about to read 6, iclass 36, count 0 2006.173.17:39:10.93#ibcon#read 6, iclass 36, count 0 2006.173.17:39:10.93#ibcon#end of sib2, iclass 36, count 0 2006.173.17:39:10.93#ibcon#*mode == 0, iclass 36, count 0 2006.173.17:39:10.93#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.17:39:10.93#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.17:39:10.93#ibcon#*before write, iclass 36, count 0 2006.173.17:39:10.93#ibcon#enter sib2, iclass 36, count 0 2006.173.17:39:10.93#ibcon#flushed, iclass 36, count 0 2006.173.17:39:10.93#ibcon#about to write, iclass 36, count 0 2006.173.17:39:10.93#ibcon#wrote, iclass 36, count 0 2006.173.17:39:10.93#ibcon#about to read 3, iclass 36, count 0 2006.173.17:39:10.97#ibcon#read 3, iclass 36, count 0 2006.173.17:39:10.97#ibcon#about to read 4, iclass 36, count 0 2006.173.17:39:10.97#ibcon#read 4, iclass 36, count 0 2006.173.17:39:10.97#ibcon#about to read 5, iclass 36, count 0 2006.173.17:39:10.97#ibcon#read 5, iclass 36, count 0 2006.173.17:39:10.97#ibcon#about to read 6, iclass 36, count 0 2006.173.17:39:10.97#ibcon#read 6, iclass 36, count 0 2006.173.17:39:10.97#ibcon#end of sib2, iclass 36, count 0 2006.173.17:39:10.97#ibcon#*after write, iclass 36, count 0 2006.173.17:39:10.97#ibcon#*before return 0, iclass 36, count 0 2006.173.17:39:10.97#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.17:39:10.97#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.17:39:10.97#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.17:39:10.97#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.17:39:10.97$vck44/vb=1,4 2006.173.17:39:10.97#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.17:39:10.97#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.17:39:10.97#ibcon#ireg 11 cls_cnt 2 2006.173.17:39:10.97#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.17:39:10.97#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.17:39:10.97#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.17:39:10.97#ibcon#enter wrdev, iclass 38, count 2 2006.173.17:39:10.97#ibcon#first serial, iclass 38, count 2 2006.173.17:39:10.97#ibcon#enter sib2, iclass 38, count 2 2006.173.17:39:10.97#ibcon#flushed, iclass 38, count 2 2006.173.17:39:10.97#ibcon#about to write, iclass 38, count 2 2006.173.17:39:10.97#ibcon#wrote, iclass 38, count 2 2006.173.17:39:10.97#ibcon#about to read 3, iclass 38, count 2 2006.173.17:39:10.99#ibcon#read 3, iclass 38, count 2 2006.173.17:39:10.99#ibcon#about to read 4, iclass 38, count 2 2006.173.17:39:10.99#ibcon#read 4, iclass 38, count 2 2006.173.17:39:10.99#ibcon#about to read 5, iclass 38, count 2 2006.173.17:39:10.99#ibcon#read 5, iclass 38, count 2 2006.173.17:39:10.99#ibcon#about to read 6, iclass 38, count 2 2006.173.17:39:10.99#ibcon#read 6, iclass 38, count 2 2006.173.17:39:10.99#ibcon#end of sib2, iclass 38, count 2 2006.173.17:39:10.99#ibcon#*mode == 0, iclass 38, count 2 2006.173.17:39:10.99#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.17:39:10.99#ibcon#[27=AT01-04\r\n] 2006.173.17:39:10.99#ibcon#*before write, iclass 38, count 2 2006.173.17:39:10.99#ibcon#enter sib2, iclass 38, count 2 2006.173.17:39:10.99#ibcon#flushed, iclass 38, count 2 2006.173.17:39:10.99#ibcon#about to write, iclass 38, count 2 2006.173.17:39:10.99#ibcon#wrote, iclass 38, count 2 2006.173.17:39:10.99#ibcon#about to read 3, iclass 38, count 2 2006.173.17:39:11.02#ibcon#read 3, iclass 38, count 2 2006.173.17:39:11.02#ibcon#about to read 4, iclass 38, count 2 2006.173.17:39:11.02#ibcon#read 4, iclass 38, count 2 2006.173.17:39:11.02#ibcon#about to read 5, iclass 38, count 2 2006.173.17:39:11.02#ibcon#read 5, iclass 38, count 2 2006.173.17:39:11.02#ibcon#about to read 6, iclass 38, count 2 2006.173.17:39:11.02#ibcon#read 6, iclass 38, count 2 2006.173.17:39:11.02#ibcon#end of sib2, iclass 38, count 2 2006.173.17:39:11.02#ibcon#*after write, iclass 38, count 2 2006.173.17:39:11.02#ibcon#*before return 0, iclass 38, count 2 2006.173.17:39:11.02#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.17:39:11.02#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.17:39:11.02#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.17:39:11.02#ibcon#ireg 7 cls_cnt 0 2006.173.17:39:11.02#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.17:39:11.14#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.17:39:11.14#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.17:39:11.14#ibcon#enter wrdev, iclass 38, count 0 2006.173.17:39:11.14#ibcon#first serial, iclass 38, count 0 2006.173.17:39:11.14#ibcon#enter sib2, iclass 38, count 0 2006.173.17:39:11.14#ibcon#flushed, iclass 38, count 0 2006.173.17:39:11.14#ibcon#about to write, iclass 38, count 0 2006.173.17:39:11.14#ibcon#wrote, iclass 38, count 0 2006.173.17:39:11.14#ibcon#about to read 3, iclass 38, count 0 2006.173.17:39:11.16#ibcon#read 3, iclass 38, count 0 2006.173.17:39:11.16#ibcon#about to read 4, iclass 38, count 0 2006.173.17:39:11.16#ibcon#read 4, iclass 38, count 0 2006.173.17:39:11.16#ibcon#about to read 5, iclass 38, count 0 2006.173.17:39:11.16#ibcon#read 5, iclass 38, count 0 2006.173.17:39:11.16#ibcon#about to read 6, iclass 38, count 0 2006.173.17:39:11.16#ibcon#read 6, iclass 38, count 0 2006.173.17:39:11.16#ibcon#end of sib2, iclass 38, count 0 2006.173.17:39:11.16#ibcon#*mode == 0, iclass 38, count 0 2006.173.17:39:11.16#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.17:39:11.16#ibcon#[27=USB\r\n] 2006.173.17:39:11.16#ibcon#*before write, iclass 38, count 0 2006.173.17:39:11.16#ibcon#enter sib2, iclass 38, count 0 2006.173.17:39:11.16#ibcon#flushed, iclass 38, count 0 2006.173.17:39:11.16#ibcon#about to write, iclass 38, count 0 2006.173.17:39:11.16#ibcon#wrote, iclass 38, count 0 2006.173.17:39:11.16#ibcon#about to read 3, iclass 38, count 0 2006.173.17:39:11.19#ibcon#read 3, iclass 38, count 0 2006.173.17:39:11.19#ibcon#about to read 4, iclass 38, count 0 2006.173.17:39:11.19#ibcon#read 4, iclass 38, count 0 2006.173.17:39:11.19#ibcon#about to read 5, iclass 38, count 0 2006.173.17:39:11.19#ibcon#read 5, iclass 38, count 0 2006.173.17:39:11.19#ibcon#about to read 6, iclass 38, count 0 2006.173.17:39:11.19#ibcon#read 6, iclass 38, count 0 2006.173.17:39:11.19#ibcon#end of sib2, iclass 38, count 0 2006.173.17:39:11.19#ibcon#*after write, iclass 38, count 0 2006.173.17:39:11.19#ibcon#*before return 0, iclass 38, count 0 2006.173.17:39:11.19#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.17:39:11.19#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.17:39:11.19#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.17:39:11.19#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.17:39:11.19$vck44/vblo=2,634.99 2006.173.17:39:11.19#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.17:39:11.19#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.17:39:11.19#ibcon#ireg 17 cls_cnt 0 2006.173.17:39:11.19#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.17:39:11.19#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.17:39:11.19#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.17:39:11.19#ibcon#enter wrdev, iclass 40, count 0 2006.173.17:39:11.19#ibcon#first serial, iclass 40, count 0 2006.173.17:39:11.19#ibcon#enter sib2, iclass 40, count 0 2006.173.17:39:11.19#ibcon#flushed, iclass 40, count 0 2006.173.17:39:11.19#ibcon#about to write, iclass 40, count 0 2006.173.17:39:11.19#ibcon#wrote, iclass 40, count 0 2006.173.17:39:11.19#ibcon#about to read 3, iclass 40, count 0 2006.173.17:39:11.21#ibcon#read 3, iclass 40, count 0 2006.173.17:39:11.21#ibcon#about to read 4, iclass 40, count 0 2006.173.17:39:11.21#ibcon#read 4, iclass 40, count 0 2006.173.17:39:11.21#ibcon#about to read 5, iclass 40, count 0 2006.173.17:39:11.21#ibcon#read 5, iclass 40, count 0 2006.173.17:39:11.21#ibcon#about to read 6, iclass 40, count 0 2006.173.17:39:11.21#ibcon#read 6, iclass 40, count 0 2006.173.17:39:11.21#ibcon#end of sib2, iclass 40, count 0 2006.173.17:39:11.21#ibcon#*mode == 0, iclass 40, count 0 2006.173.17:39:11.21#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.17:39:11.21#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.17:39:11.21#ibcon#*before write, iclass 40, count 0 2006.173.17:39:11.21#ibcon#enter sib2, iclass 40, count 0 2006.173.17:39:11.21#ibcon#flushed, iclass 40, count 0 2006.173.17:39:11.21#ibcon#about to write, iclass 40, count 0 2006.173.17:39:11.21#ibcon#wrote, iclass 40, count 0 2006.173.17:39:11.21#ibcon#about to read 3, iclass 40, count 0 2006.173.17:39:11.25#ibcon#read 3, iclass 40, count 0 2006.173.17:39:11.25#ibcon#about to read 4, iclass 40, count 0 2006.173.17:39:11.25#ibcon#read 4, iclass 40, count 0 2006.173.17:39:11.25#ibcon#about to read 5, iclass 40, count 0 2006.173.17:39:11.25#ibcon#read 5, iclass 40, count 0 2006.173.17:39:11.25#ibcon#about to read 6, iclass 40, count 0 2006.173.17:39:11.25#ibcon#read 6, iclass 40, count 0 2006.173.17:39:11.25#ibcon#end of sib2, iclass 40, count 0 2006.173.17:39:11.25#ibcon#*after write, iclass 40, count 0 2006.173.17:39:11.25#ibcon#*before return 0, iclass 40, count 0 2006.173.17:39:11.25#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.17:39:11.25#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.17:39:11.25#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.17:39:11.25#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.17:39:11.25$vck44/vb=2,4 2006.173.17:39:11.25#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.17:39:11.25#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.17:39:11.25#ibcon#ireg 11 cls_cnt 2 2006.173.17:39:11.25#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.17:39:11.31#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.17:39:11.31#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.17:39:11.31#ibcon#enter wrdev, iclass 4, count 2 2006.173.17:39:11.31#ibcon#first serial, iclass 4, count 2 2006.173.17:39:11.31#ibcon#enter sib2, iclass 4, count 2 2006.173.17:39:11.31#ibcon#flushed, iclass 4, count 2 2006.173.17:39:11.31#ibcon#about to write, iclass 4, count 2 2006.173.17:39:11.31#ibcon#wrote, iclass 4, count 2 2006.173.17:39:11.31#ibcon#about to read 3, iclass 4, count 2 2006.173.17:39:11.33#ibcon#read 3, iclass 4, count 2 2006.173.17:39:11.33#ibcon#about to read 4, iclass 4, count 2 2006.173.17:39:11.33#ibcon#read 4, iclass 4, count 2 2006.173.17:39:11.33#ibcon#about to read 5, iclass 4, count 2 2006.173.17:39:11.33#ibcon#read 5, iclass 4, count 2 2006.173.17:39:11.33#ibcon#about to read 6, iclass 4, count 2 2006.173.17:39:11.33#ibcon#read 6, iclass 4, count 2 2006.173.17:39:11.33#ibcon#end of sib2, iclass 4, count 2 2006.173.17:39:11.33#ibcon#*mode == 0, iclass 4, count 2 2006.173.17:39:11.33#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.17:39:11.33#ibcon#[27=AT02-04\r\n] 2006.173.17:39:11.33#ibcon#*before write, iclass 4, count 2 2006.173.17:39:11.33#ibcon#enter sib2, iclass 4, count 2 2006.173.17:39:11.33#ibcon#flushed, iclass 4, count 2 2006.173.17:39:11.33#ibcon#about to write, iclass 4, count 2 2006.173.17:39:11.33#ibcon#wrote, iclass 4, count 2 2006.173.17:39:11.33#ibcon#about to read 3, iclass 4, count 2 2006.173.17:39:11.36#ibcon#read 3, iclass 4, count 2 2006.173.17:39:11.36#ibcon#about to read 4, iclass 4, count 2 2006.173.17:39:11.36#ibcon#read 4, iclass 4, count 2 2006.173.17:39:11.36#ibcon#about to read 5, iclass 4, count 2 2006.173.17:39:11.36#ibcon#read 5, iclass 4, count 2 2006.173.17:39:11.36#ibcon#about to read 6, iclass 4, count 2 2006.173.17:39:11.36#ibcon#read 6, iclass 4, count 2 2006.173.17:39:11.36#ibcon#end of sib2, iclass 4, count 2 2006.173.17:39:11.36#ibcon#*after write, iclass 4, count 2 2006.173.17:39:11.36#ibcon#*before return 0, iclass 4, count 2 2006.173.17:39:11.36#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.17:39:11.36#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.17:39:11.36#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.17:39:11.36#ibcon#ireg 7 cls_cnt 0 2006.173.17:39:11.36#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.17:39:11.48#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.17:39:11.48#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.17:39:11.48#ibcon#enter wrdev, iclass 4, count 0 2006.173.17:39:11.48#ibcon#first serial, iclass 4, count 0 2006.173.17:39:11.48#ibcon#enter sib2, iclass 4, count 0 2006.173.17:39:11.48#ibcon#flushed, iclass 4, count 0 2006.173.17:39:11.48#ibcon#about to write, iclass 4, count 0 2006.173.17:39:11.48#ibcon#wrote, iclass 4, count 0 2006.173.17:39:11.48#ibcon#about to read 3, iclass 4, count 0 2006.173.17:39:11.50#ibcon#read 3, iclass 4, count 0 2006.173.17:39:11.50#ibcon#about to read 4, iclass 4, count 0 2006.173.17:39:11.50#ibcon#read 4, iclass 4, count 0 2006.173.17:39:11.50#ibcon#about to read 5, iclass 4, count 0 2006.173.17:39:11.50#ibcon#read 5, iclass 4, count 0 2006.173.17:39:11.50#ibcon#about to read 6, iclass 4, count 0 2006.173.17:39:11.50#ibcon#read 6, iclass 4, count 0 2006.173.17:39:11.50#ibcon#end of sib2, iclass 4, count 0 2006.173.17:39:11.50#ibcon#*mode == 0, iclass 4, count 0 2006.173.17:39:11.50#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.17:39:11.50#ibcon#[27=USB\r\n] 2006.173.17:39:11.50#ibcon#*before write, iclass 4, count 0 2006.173.17:39:11.50#ibcon#enter sib2, iclass 4, count 0 2006.173.17:39:11.50#ibcon#flushed, iclass 4, count 0 2006.173.17:39:11.50#ibcon#about to write, iclass 4, count 0 2006.173.17:39:11.50#ibcon#wrote, iclass 4, count 0 2006.173.17:39:11.50#ibcon#about to read 3, iclass 4, count 0 2006.173.17:39:11.53#ibcon#read 3, iclass 4, count 0 2006.173.17:39:11.53#ibcon#about to read 4, iclass 4, count 0 2006.173.17:39:11.53#ibcon#read 4, iclass 4, count 0 2006.173.17:39:11.53#ibcon#about to read 5, iclass 4, count 0 2006.173.17:39:11.53#ibcon#read 5, iclass 4, count 0 2006.173.17:39:11.53#ibcon#about to read 6, iclass 4, count 0 2006.173.17:39:11.53#ibcon#read 6, iclass 4, count 0 2006.173.17:39:11.53#ibcon#end of sib2, iclass 4, count 0 2006.173.17:39:11.53#ibcon#*after write, iclass 4, count 0 2006.173.17:39:11.53#ibcon#*before return 0, iclass 4, count 0 2006.173.17:39:11.53#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.17:39:11.53#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.17:39:11.53#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.17:39:11.53#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.17:39:11.53$vck44/vblo=3,649.99 2006.173.17:39:11.53#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.17:39:11.53#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.17:39:11.53#ibcon#ireg 17 cls_cnt 0 2006.173.17:39:11.53#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.17:39:11.53#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.17:39:11.53#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.17:39:11.53#ibcon#enter wrdev, iclass 6, count 0 2006.173.17:39:11.53#ibcon#first serial, iclass 6, count 0 2006.173.17:39:11.53#ibcon#enter sib2, iclass 6, count 0 2006.173.17:39:11.53#ibcon#flushed, iclass 6, count 0 2006.173.17:39:11.53#ibcon#about to write, iclass 6, count 0 2006.173.17:39:11.53#ibcon#wrote, iclass 6, count 0 2006.173.17:39:11.53#ibcon#about to read 3, iclass 6, count 0 2006.173.17:39:11.55#ibcon#read 3, iclass 6, count 0 2006.173.17:39:11.55#ibcon#about to read 4, iclass 6, count 0 2006.173.17:39:11.55#ibcon#read 4, iclass 6, count 0 2006.173.17:39:11.55#ibcon#about to read 5, iclass 6, count 0 2006.173.17:39:11.55#ibcon#read 5, iclass 6, count 0 2006.173.17:39:11.55#ibcon#about to read 6, iclass 6, count 0 2006.173.17:39:11.55#ibcon#read 6, iclass 6, count 0 2006.173.17:39:11.55#ibcon#end of sib2, iclass 6, count 0 2006.173.17:39:11.55#ibcon#*mode == 0, iclass 6, count 0 2006.173.17:39:11.55#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.17:39:11.55#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.17:39:11.55#ibcon#*before write, iclass 6, count 0 2006.173.17:39:11.55#ibcon#enter sib2, iclass 6, count 0 2006.173.17:39:11.55#ibcon#flushed, iclass 6, count 0 2006.173.17:39:11.55#ibcon#about to write, iclass 6, count 0 2006.173.17:39:11.55#ibcon#wrote, iclass 6, count 0 2006.173.17:39:11.55#ibcon#about to read 3, iclass 6, count 0 2006.173.17:39:11.59#ibcon#read 3, iclass 6, count 0 2006.173.17:39:11.59#ibcon#about to read 4, iclass 6, count 0 2006.173.17:39:11.59#ibcon#read 4, iclass 6, count 0 2006.173.17:39:11.59#ibcon#about to read 5, iclass 6, count 0 2006.173.17:39:11.59#ibcon#read 5, iclass 6, count 0 2006.173.17:39:11.59#ibcon#about to read 6, iclass 6, count 0 2006.173.17:39:11.59#ibcon#read 6, iclass 6, count 0 2006.173.17:39:11.59#ibcon#end of sib2, iclass 6, count 0 2006.173.17:39:11.59#ibcon#*after write, iclass 6, count 0 2006.173.17:39:11.59#ibcon#*before return 0, iclass 6, count 0 2006.173.17:39:11.59#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.17:39:11.59#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.17:39:11.59#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.17:39:11.59#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.17:39:11.59$vck44/vb=3,4 2006.173.17:39:11.59#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.17:39:11.59#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.17:39:11.59#ibcon#ireg 11 cls_cnt 2 2006.173.17:39:11.59#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.17:39:11.65#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.17:39:11.65#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.17:39:11.65#ibcon#enter wrdev, iclass 10, count 2 2006.173.17:39:11.65#ibcon#first serial, iclass 10, count 2 2006.173.17:39:11.65#ibcon#enter sib2, iclass 10, count 2 2006.173.17:39:11.65#ibcon#flushed, iclass 10, count 2 2006.173.17:39:11.65#ibcon#about to write, iclass 10, count 2 2006.173.17:39:11.65#ibcon#wrote, iclass 10, count 2 2006.173.17:39:11.65#ibcon#about to read 3, iclass 10, count 2 2006.173.17:39:11.67#ibcon#read 3, iclass 10, count 2 2006.173.17:39:11.67#ibcon#about to read 4, iclass 10, count 2 2006.173.17:39:11.67#ibcon#read 4, iclass 10, count 2 2006.173.17:39:11.67#ibcon#about to read 5, iclass 10, count 2 2006.173.17:39:11.67#ibcon#read 5, iclass 10, count 2 2006.173.17:39:11.67#ibcon#about to read 6, iclass 10, count 2 2006.173.17:39:11.67#ibcon#read 6, iclass 10, count 2 2006.173.17:39:11.67#ibcon#end of sib2, iclass 10, count 2 2006.173.17:39:11.67#ibcon#*mode == 0, iclass 10, count 2 2006.173.17:39:11.67#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.17:39:11.67#ibcon#[27=AT03-04\r\n] 2006.173.17:39:11.67#ibcon#*before write, iclass 10, count 2 2006.173.17:39:11.67#ibcon#enter sib2, iclass 10, count 2 2006.173.17:39:11.67#ibcon#flushed, iclass 10, count 2 2006.173.17:39:11.67#ibcon#about to write, iclass 10, count 2 2006.173.17:39:11.67#ibcon#wrote, iclass 10, count 2 2006.173.17:39:11.67#ibcon#about to read 3, iclass 10, count 2 2006.173.17:39:11.70#ibcon#read 3, iclass 10, count 2 2006.173.17:39:11.70#ibcon#about to read 4, iclass 10, count 2 2006.173.17:39:11.70#ibcon#read 4, iclass 10, count 2 2006.173.17:39:11.70#ibcon#about to read 5, iclass 10, count 2 2006.173.17:39:11.70#ibcon#read 5, iclass 10, count 2 2006.173.17:39:11.70#ibcon#about to read 6, iclass 10, count 2 2006.173.17:39:11.70#ibcon#read 6, iclass 10, count 2 2006.173.17:39:11.70#ibcon#end of sib2, iclass 10, count 2 2006.173.17:39:11.70#ibcon#*after write, iclass 10, count 2 2006.173.17:39:11.70#ibcon#*before return 0, iclass 10, count 2 2006.173.17:39:11.70#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.17:39:11.70#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.17:39:11.70#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.17:39:11.70#ibcon#ireg 7 cls_cnt 0 2006.173.17:39:11.70#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.17:39:11.82#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.17:39:11.82#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.17:39:11.82#ibcon#enter wrdev, iclass 10, count 0 2006.173.17:39:11.82#ibcon#first serial, iclass 10, count 0 2006.173.17:39:11.82#ibcon#enter sib2, iclass 10, count 0 2006.173.17:39:11.82#ibcon#flushed, iclass 10, count 0 2006.173.17:39:11.82#ibcon#about to write, iclass 10, count 0 2006.173.17:39:11.82#ibcon#wrote, iclass 10, count 0 2006.173.17:39:11.82#ibcon#about to read 3, iclass 10, count 0 2006.173.17:39:11.84#ibcon#read 3, iclass 10, count 0 2006.173.17:39:11.84#ibcon#about to read 4, iclass 10, count 0 2006.173.17:39:11.84#ibcon#read 4, iclass 10, count 0 2006.173.17:39:11.84#ibcon#about to read 5, iclass 10, count 0 2006.173.17:39:11.84#ibcon#read 5, iclass 10, count 0 2006.173.17:39:11.84#ibcon#about to read 6, iclass 10, count 0 2006.173.17:39:11.84#ibcon#read 6, iclass 10, count 0 2006.173.17:39:11.84#ibcon#end of sib2, iclass 10, count 0 2006.173.17:39:11.84#ibcon#*mode == 0, iclass 10, count 0 2006.173.17:39:11.84#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.17:39:11.84#ibcon#[27=USB\r\n] 2006.173.17:39:11.84#ibcon#*before write, iclass 10, count 0 2006.173.17:39:11.84#ibcon#enter sib2, iclass 10, count 0 2006.173.17:39:11.84#ibcon#flushed, iclass 10, count 0 2006.173.17:39:11.84#ibcon#about to write, iclass 10, count 0 2006.173.17:39:11.84#ibcon#wrote, iclass 10, count 0 2006.173.17:39:11.84#ibcon#about to read 3, iclass 10, count 0 2006.173.17:39:11.87#ibcon#read 3, iclass 10, count 0 2006.173.17:39:11.87#ibcon#about to read 4, iclass 10, count 0 2006.173.17:39:11.87#ibcon#read 4, iclass 10, count 0 2006.173.17:39:11.87#ibcon#about to read 5, iclass 10, count 0 2006.173.17:39:11.87#ibcon#read 5, iclass 10, count 0 2006.173.17:39:11.87#ibcon#about to read 6, iclass 10, count 0 2006.173.17:39:11.87#ibcon#read 6, iclass 10, count 0 2006.173.17:39:11.87#ibcon#end of sib2, iclass 10, count 0 2006.173.17:39:11.87#ibcon#*after write, iclass 10, count 0 2006.173.17:39:11.87#ibcon#*before return 0, iclass 10, count 0 2006.173.17:39:11.87#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.17:39:11.87#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.17:39:11.87#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.17:39:11.87#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.17:39:11.87$vck44/vblo=4,679.99 2006.173.17:39:11.87#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.17:39:11.87#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.17:39:11.87#ibcon#ireg 17 cls_cnt 0 2006.173.17:39:11.87#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.17:39:11.87#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.17:39:11.87#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.17:39:11.87#ibcon#enter wrdev, iclass 12, count 0 2006.173.17:39:11.87#ibcon#first serial, iclass 12, count 0 2006.173.17:39:11.87#ibcon#enter sib2, iclass 12, count 0 2006.173.17:39:11.87#ibcon#flushed, iclass 12, count 0 2006.173.17:39:11.87#ibcon#about to write, iclass 12, count 0 2006.173.17:39:11.87#ibcon#wrote, iclass 12, count 0 2006.173.17:39:11.87#ibcon#about to read 3, iclass 12, count 0 2006.173.17:39:11.89#ibcon#read 3, iclass 12, count 0 2006.173.17:39:11.89#ibcon#about to read 4, iclass 12, count 0 2006.173.17:39:11.89#ibcon#read 4, iclass 12, count 0 2006.173.17:39:11.89#ibcon#about to read 5, iclass 12, count 0 2006.173.17:39:11.89#ibcon#read 5, iclass 12, count 0 2006.173.17:39:11.89#ibcon#about to read 6, iclass 12, count 0 2006.173.17:39:11.89#ibcon#read 6, iclass 12, count 0 2006.173.17:39:11.89#ibcon#end of sib2, iclass 12, count 0 2006.173.17:39:11.89#ibcon#*mode == 0, iclass 12, count 0 2006.173.17:39:11.89#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.17:39:11.89#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.17:39:11.89#ibcon#*before write, iclass 12, count 0 2006.173.17:39:11.89#ibcon#enter sib2, iclass 12, count 0 2006.173.17:39:11.89#ibcon#flushed, iclass 12, count 0 2006.173.17:39:11.89#ibcon#about to write, iclass 12, count 0 2006.173.17:39:11.89#ibcon#wrote, iclass 12, count 0 2006.173.17:39:11.89#ibcon#about to read 3, iclass 12, count 0 2006.173.17:39:11.93#ibcon#read 3, iclass 12, count 0 2006.173.17:39:11.93#ibcon#about to read 4, iclass 12, count 0 2006.173.17:39:11.93#ibcon#read 4, iclass 12, count 0 2006.173.17:39:11.93#ibcon#about to read 5, iclass 12, count 0 2006.173.17:39:11.93#ibcon#read 5, iclass 12, count 0 2006.173.17:39:11.93#ibcon#about to read 6, iclass 12, count 0 2006.173.17:39:11.93#ibcon#read 6, iclass 12, count 0 2006.173.17:39:11.93#ibcon#end of sib2, iclass 12, count 0 2006.173.17:39:11.93#ibcon#*after write, iclass 12, count 0 2006.173.17:39:11.93#ibcon#*before return 0, iclass 12, count 0 2006.173.17:39:11.93#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.17:39:11.93#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.17:39:11.93#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.17:39:11.93#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.17:39:11.93$vck44/vb=4,4 2006.173.17:39:11.93#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.17:39:11.93#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.17:39:11.93#ibcon#ireg 11 cls_cnt 2 2006.173.17:39:11.93#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.17:39:11.99#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.17:39:11.99#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.17:39:11.99#ibcon#enter wrdev, iclass 14, count 2 2006.173.17:39:11.99#ibcon#first serial, iclass 14, count 2 2006.173.17:39:11.99#ibcon#enter sib2, iclass 14, count 2 2006.173.17:39:11.99#ibcon#flushed, iclass 14, count 2 2006.173.17:39:11.99#ibcon#about to write, iclass 14, count 2 2006.173.17:39:11.99#ibcon#wrote, iclass 14, count 2 2006.173.17:39:11.99#ibcon#about to read 3, iclass 14, count 2 2006.173.17:39:12.01#ibcon#read 3, iclass 14, count 2 2006.173.17:39:12.01#ibcon#about to read 4, iclass 14, count 2 2006.173.17:39:12.01#ibcon#read 4, iclass 14, count 2 2006.173.17:39:12.01#ibcon#about to read 5, iclass 14, count 2 2006.173.17:39:12.01#ibcon#read 5, iclass 14, count 2 2006.173.17:39:12.01#ibcon#about to read 6, iclass 14, count 2 2006.173.17:39:12.01#ibcon#read 6, iclass 14, count 2 2006.173.17:39:12.01#ibcon#end of sib2, iclass 14, count 2 2006.173.17:39:12.01#ibcon#*mode == 0, iclass 14, count 2 2006.173.17:39:12.01#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.17:39:12.01#ibcon#[27=AT04-04\r\n] 2006.173.17:39:12.01#ibcon#*before write, iclass 14, count 2 2006.173.17:39:12.01#ibcon#enter sib2, iclass 14, count 2 2006.173.17:39:12.01#ibcon#flushed, iclass 14, count 2 2006.173.17:39:12.01#ibcon#about to write, iclass 14, count 2 2006.173.17:39:12.01#ibcon#wrote, iclass 14, count 2 2006.173.17:39:12.01#ibcon#about to read 3, iclass 14, count 2 2006.173.17:39:12.04#ibcon#read 3, iclass 14, count 2 2006.173.17:39:12.04#ibcon#about to read 4, iclass 14, count 2 2006.173.17:39:12.04#ibcon#read 4, iclass 14, count 2 2006.173.17:39:12.04#ibcon#about to read 5, iclass 14, count 2 2006.173.17:39:12.04#ibcon#read 5, iclass 14, count 2 2006.173.17:39:12.04#ibcon#about to read 6, iclass 14, count 2 2006.173.17:39:12.04#ibcon#read 6, iclass 14, count 2 2006.173.17:39:12.04#ibcon#end of sib2, iclass 14, count 2 2006.173.17:39:12.04#ibcon#*after write, iclass 14, count 2 2006.173.17:39:12.04#ibcon#*before return 0, iclass 14, count 2 2006.173.17:39:12.04#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.17:39:12.04#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.17:39:12.04#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.17:39:12.04#ibcon#ireg 7 cls_cnt 0 2006.173.17:39:12.04#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.17:39:12.16#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.17:39:12.16#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.17:39:12.16#ibcon#enter wrdev, iclass 14, count 0 2006.173.17:39:12.16#ibcon#first serial, iclass 14, count 0 2006.173.17:39:12.16#ibcon#enter sib2, iclass 14, count 0 2006.173.17:39:12.16#ibcon#flushed, iclass 14, count 0 2006.173.17:39:12.16#ibcon#about to write, iclass 14, count 0 2006.173.17:39:12.16#ibcon#wrote, iclass 14, count 0 2006.173.17:39:12.16#ibcon#about to read 3, iclass 14, count 0 2006.173.17:39:12.18#ibcon#read 3, iclass 14, count 0 2006.173.17:39:12.18#ibcon#about to read 4, iclass 14, count 0 2006.173.17:39:12.18#ibcon#read 4, iclass 14, count 0 2006.173.17:39:12.18#ibcon#about to read 5, iclass 14, count 0 2006.173.17:39:12.18#ibcon#read 5, iclass 14, count 0 2006.173.17:39:12.18#ibcon#about to read 6, iclass 14, count 0 2006.173.17:39:12.18#ibcon#read 6, iclass 14, count 0 2006.173.17:39:12.18#ibcon#end of sib2, iclass 14, count 0 2006.173.17:39:12.18#ibcon#*mode == 0, iclass 14, count 0 2006.173.17:39:12.18#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.17:39:12.18#ibcon#[27=USB\r\n] 2006.173.17:39:12.18#ibcon#*before write, iclass 14, count 0 2006.173.17:39:12.18#ibcon#enter sib2, iclass 14, count 0 2006.173.17:39:12.18#ibcon#flushed, iclass 14, count 0 2006.173.17:39:12.18#ibcon#about to write, iclass 14, count 0 2006.173.17:39:12.18#ibcon#wrote, iclass 14, count 0 2006.173.17:39:12.18#ibcon#about to read 3, iclass 14, count 0 2006.173.17:39:12.21#ibcon#read 3, iclass 14, count 0 2006.173.17:39:12.21#ibcon#about to read 4, iclass 14, count 0 2006.173.17:39:12.21#ibcon#read 4, iclass 14, count 0 2006.173.17:39:12.21#ibcon#about to read 5, iclass 14, count 0 2006.173.17:39:12.21#ibcon#read 5, iclass 14, count 0 2006.173.17:39:12.21#ibcon#about to read 6, iclass 14, count 0 2006.173.17:39:12.21#ibcon#read 6, iclass 14, count 0 2006.173.17:39:12.21#ibcon#end of sib2, iclass 14, count 0 2006.173.17:39:12.21#ibcon#*after write, iclass 14, count 0 2006.173.17:39:12.21#ibcon#*before return 0, iclass 14, count 0 2006.173.17:39:12.21#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.17:39:12.21#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.17:39:12.21#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.17:39:12.21#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.17:39:12.21$vck44/vblo=5,709.99 2006.173.17:39:12.21#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.17:39:12.21#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.17:39:12.21#ibcon#ireg 17 cls_cnt 0 2006.173.17:39:12.21#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.17:39:12.21#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.17:39:12.21#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.17:39:12.21#ibcon#enter wrdev, iclass 16, count 0 2006.173.17:39:12.21#ibcon#first serial, iclass 16, count 0 2006.173.17:39:12.21#ibcon#enter sib2, iclass 16, count 0 2006.173.17:39:12.21#ibcon#flushed, iclass 16, count 0 2006.173.17:39:12.21#ibcon#about to write, iclass 16, count 0 2006.173.17:39:12.21#ibcon#wrote, iclass 16, count 0 2006.173.17:39:12.21#ibcon#about to read 3, iclass 16, count 0 2006.173.17:39:12.23#ibcon#read 3, iclass 16, count 0 2006.173.17:39:12.23#ibcon#about to read 4, iclass 16, count 0 2006.173.17:39:12.23#ibcon#read 4, iclass 16, count 0 2006.173.17:39:12.23#ibcon#about to read 5, iclass 16, count 0 2006.173.17:39:12.23#ibcon#read 5, iclass 16, count 0 2006.173.17:39:12.23#ibcon#about to read 6, iclass 16, count 0 2006.173.17:39:12.23#ibcon#read 6, iclass 16, count 0 2006.173.17:39:12.23#ibcon#end of sib2, iclass 16, count 0 2006.173.17:39:12.23#ibcon#*mode == 0, iclass 16, count 0 2006.173.17:39:12.23#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.17:39:12.23#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.17:39:12.23#ibcon#*before write, iclass 16, count 0 2006.173.17:39:12.23#ibcon#enter sib2, iclass 16, count 0 2006.173.17:39:12.23#ibcon#flushed, iclass 16, count 0 2006.173.17:39:12.23#ibcon#about to write, iclass 16, count 0 2006.173.17:39:12.23#ibcon#wrote, iclass 16, count 0 2006.173.17:39:12.23#ibcon#about to read 3, iclass 16, count 0 2006.173.17:39:12.27#ibcon#read 3, iclass 16, count 0 2006.173.17:39:12.27#ibcon#about to read 4, iclass 16, count 0 2006.173.17:39:12.27#ibcon#read 4, iclass 16, count 0 2006.173.17:39:12.27#ibcon#about to read 5, iclass 16, count 0 2006.173.17:39:12.27#ibcon#read 5, iclass 16, count 0 2006.173.17:39:12.27#ibcon#about to read 6, iclass 16, count 0 2006.173.17:39:12.27#ibcon#read 6, iclass 16, count 0 2006.173.17:39:12.27#ibcon#end of sib2, iclass 16, count 0 2006.173.17:39:12.27#ibcon#*after write, iclass 16, count 0 2006.173.17:39:12.27#ibcon#*before return 0, iclass 16, count 0 2006.173.17:39:12.27#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.17:39:12.27#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.17:39:12.27#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.17:39:12.27#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.17:39:12.27$vck44/vb=5,4 2006.173.17:39:12.27#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.17:39:12.27#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.17:39:12.27#ibcon#ireg 11 cls_cnt 2 2006.173.17:39:12.27#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.17:39:12.33#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.17:39:12.33#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.17:39:12.33#ibcon#enter wrdev, iclass 18, count 2 2006.173.17:39:12.33#ibcon#first serial, iclass 18, count 2 2006.173.17:39:12.33#ibcon#enter sib2, iclass 18, count 2 2006.173.17:39:12.33#ibcon#flushed, iclass 18, count 2 2006.173.17:39:12.33#ibcon#about to write, iclass 18, count 2 2006.173.17:39:12.33#ibcon#wrote, iclass 18, count 2 2006.173.17:39:12.33#ibcon#about to read 3, iclass 18, count 2 2006.173.17:39:12.35#ibcon#read 3, iclass 18, count 2 2006.173.17:39:12.35#ibcon#about to read 4, iclass 18, count 2 2006.173.17:39:12.35#ibcon#read 4, iclass 18, count 2 2006.173.17:39:12.35#ibcon#about to read 5, iclass 18, count 2 2006.173.17:39:12.35#ibcon#read 5, iclass 18, count 2 2006.173.17:39:12.35#ibcon#about to read 6, iclass 18, count 2 2006.173.17:39:12.35#ibcon#read 6, iclass 18, count 2 2006.173.17:39:12.35#ibcon#end of sib2, iclass 18, count 2 2006.173.17:39:12.35#ibcon#*mode == 0, iclass 18, count 2 2006.173.17:39:12.35#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.17:39:12.35#ibcon#[27=AT05-04\r\n] 2006.173.17:39:12.35#ibcon#*before write, iclass 18, count 2 2006.173.17:39:12.35#ibcon#enter sib2, iclass 18, count 2 2006.173.17:39:12.35#ibcon#flushed, iclass 18, count 2 2006.173.17:39:12.35#ibcon#about to write, iclass 18, count 2 2006.173.17:39:12.35#ibcon#wrote, iclass 18, count 2 2006.173.17:39:12.35#ibcon#about to read 3, iclass 18, count 2 2006.173.17:39:12.38#ibcon#read 3, iclass 18, count 2 2006.173.17:39:12.38#ibcon#about to read 4, iclass 18, count 2 2006.173.17:39:12.38#ibcon#read 4, iclass 18, count 2 2006.173.17:39:12.38#ibcon#about to read 5, iclass 18, count 2 2006.173.17:39:12.38#ibcon#read 5, iclass 18, count 2 2006.173.17:39:12.38#ibcon#about to read 6, iclass 18, count 2 2006.173.17:39:12.38#ibcon#read 6, iclass 18, count 2 2006.173.17:39:12.38#ibcon#end of sib2, iclass 18, count 2 2006.173.17:39:12.38#ibcon#*after write, iclass 18, count 2 2006.173.17:39:12.38#ibcon#*before return 0, iclass 18, count 2 2006.173.17:39:12.38#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.17:39:12.38#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.17:39:12.38#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.17:39:12.38#ibcon#ireg 7 cls_cnt 0 2006.173.17:39:12.38#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.17:39:12.50#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.17:39:12.50#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.17:39:12.50#ibcon#enter wrdev, iclass 18, count 0 2006.173.17:39:12.50#ibcon#first serial, iclass 18, count 0 2006.173.17:39:12.50#ibcon#enter sib2, iclass 18, count 0 2006.173.17:39:12.50#ibcon#flushed, iclass 18, count 0 2006.173.17:39:12.50#ibcon#about to write, iclass 18, count 0 2006.173.17:39:12.50#ibcon#wrote, iclass 18, count 0 2006.173.17:39:12.50#ibcon#about to read 3, iclass 18, count 0 2006.173.17:39:12.52#ibcon#read 3, iclass 18, count 0 2006.173.17:39:12.52#ibcon#about to read 4, iclass 18, count 0 2006.173.17:39:12.52#ibcon#read 4, iclass 18, count 0 2006.173.17:39:12.52#ibcon#about to read 5, iclass 18, count 0 2006.173.17:39:12.52#ibcon#read 5, iclass 18, count 0 2006.173.17:39:12.52#ibcon#about to read 6, iclass 18, count 0 2006.173.17:39:12.52#ibcon#read 6, iclass 18, count 0 2006.173.17:39:12.52#ibcon#end of sib2, iclass 18, count 0 2006.173.17:39:12.52#ibcon#*mode == 0, iclass 18, count 0 2006.173.17:39:12.52#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.17:39:12.52#ibcon#[27=USB\r\n] 2006.173.17:39:12.52#ibcon#*before write, iclass 18, count 0 2006.173.17:39:12.52#ibcon#enter sib2, iclass 18, count 0 2006.173.17:39:12.52#ibcon#flushed, iclass 18, count 0 2006.173.17:39:12.52#ibcon#about to write, iclass 18, count 0 2006.173.17:39:12.52#ibcon#wrote, iclass 18, count 0 2006.173.17:39:12.52#ibcon#about to read 3, iclass 18, count 0 2006.173.17:39:12.55#ibcon#read 3, iclass 18, count 0 2006.173.17:39:12.55#ibcon#about to read 4, iclass 18, count 0 2006.173.17:39:12.55#ibcon#read 4, iclass 18, count 0 2006.173.17:39:12.55#ibcon#about to read 5, iclass 18, count 0 2006.173.17:39:12.55#ibcon#read 5, iclass 18, count 0 2006.173.17:39:12.55#ibcon#about to read 6, iclass 18, count 0 2006.173.17:39:12.55#ibcon#read 6, iclass 18, count 0 2006.173.17:39:12.55#ibcon#end of sib2, iclass 18, count 0 2006.173.17:39:12.55#ibcon#*after write, iclass 18, count 0 2006.173.17:39:12.55#ibcon#*before return 0, iclass 18, count 0 2006.173.17:39:12.55#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.17:39:12.55#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.17:39:12.55#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.17:39:12.55#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.17:39:12.55$vck44/vblo=6,719.99 2006.173.17:39:12.55#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.17:39:12.55#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.17:39:12.55#ibcon#ireg 17 cls_cnt 0 2006.173.17:39:12.55#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.17:39:12.55#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.17:39:12.55#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.17:39:12.55#ibcon#enter wrdev, iclass 20, count 0 2006.173.17:39:12.55#ibcon#first serial, iclass 20, count 0 2006.173.17:39:12.55#ibcon#enter sib2, iclass 20, count 0 2006.173.17:39:12.55#ibcon#flushed, iclass 20, count 0 2006.173.17:39:12.55#ibcon#about to write, iclass 20, count 0 2006.173.17:39:12.55#ibcon#wrote, iclass 20, count 0 2006.173.17:39:12.55#ibcon#about to read 3, iclass 20, count 0 2006.173.17:39:12.57#ibcon#read 3, iclass 20, count 0 2006.173.17:39:12.57#ibcon#about to read 4, iclass 20, count 0 2006.173.17:39:12.57#ibcon#read 4, iclass 20, count 0 2006.173.17:39:12.57#ibcon#about to read 5, iclass 20, count 0 2006.173.17:39:12.57#ibcon#read 5, iclass 20, count 0 2006.173.17:39:12.57#ibcon#about to read 6, iclass 20, count 0 2006.173.17:39:12.57#ibcon#read 6, iclass 20, count 0 2006.173.17:39:12.57#ibcon#end of sib2, iclass 20, count 0 2006.173.17:39:12.57#ibcon#*mode == 0, iclass 20, count 0 2006.173.17:39:12.57#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.17:39:12.57#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.17:39:12.57#ibcon#*before write, iclass 20, count 0 2006.173.17:39:12.57#ibcon#enter sib2, iclass 20, count 0 2006.173.17:39:12.57#ibcon#flushed, iclass 20, count 0 2006.173.17:39:12.57#ibcon#about to write, iclass 20, count 0 2006.173.17:39:12.57#ibcon#wrote, iclass 20, count 0 2006.173.17:39:12.57#ibcon#about to read 3, iclass 20, count 0 2006.173.17:39:12.61#ibcon#read 3, iclass 20, count 0 2006.173.17:39:12.61#ibcon#about to read 4, iclass 20, count 0 2006.173.17:39:12.61#ibcon#read 4, iclass 20, count 0 2006.173.17:39:12.61#ibcon#about to read 5, iclass 20, count 0 2006.173.17:39:12.61#ibcon#read 5, iclass 20, count 0 2006.173.17:39:12.61#ibcon#about to read 6, iclass 20, count 0 2006.173.17:39:12.61#ibcon#read 6, iclass 20, count 0 2006.173.17:39:12.61#ibcon#end of sib2, iclass 20, count 0 2006.173.17:39:12.61#ibcon#*after write, iclass 20, count 0 2006.173.17:39:12.61#ibcon#*before return 0, iclass 20, count 0 2006.173.17:39:12.61#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.17:39:12.61#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.17:39:12.61#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.17:39:12.61#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.17:39:12.61$vck44/vb=6,4 2006.173.17:39:12.61#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.17:39:12.61#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.17:39:12.61#ibcon#ireg 11 cls_cnt 2 2006.173.17:39:12.61#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.17:39:12.67#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.17:39:12.67#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.17:39:12.67#ibcon#enter wrdev, iclass 22, count 2 2006.173.17:39:12.67#ibcon#first serial, iclass 22, count 2 2006.173.17:39:12.67#ibcon#enter sib2, iclass 22, count 2 2006.173.17:39:12.67#ibcon#flushed, iclass 22, count 2 2006.173.17:39:12.67#ibcon#about to write, iclass 22, count 2 2006.173.17:39:12.67#ibcon#wrote, iclass 22, count 2 2006.173.17:39:12.67#ibcon#about to read 3, iclass 22, count 2 2006.173.17:39:12.69#ibcon#read 3, iclass 22, count 2 2006.173.17:39:12.69#ibcon#about to read 4, iclass 22, count 2 2006.173.17:39:12.69#ibcon#read 4, iclass 22, count 2 2006.173.17:39:12.69#ibcon#about to read 5, iclass 22, count 2 2006.173.17:39:12.69#ibcon#read 5, iclass 22, count 2 2006.173.17:39:12.69#ibcon#about to read 6, iclass 22, count 2 2006.173.17:39:12.69#ibcon#read 6, iclass 22, count 2 2006.173.17:39:12.69#ibcon#end of sib2, iclass 22, count 2 2006.173.17:39:12.69#ibcon#*mode == 0, iclass 22, count 2 2006.173.17:39:12.69#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.17:39:12.69#ibcon#[27=AT06-04\r\n] 2006.173.17:39:12.69#ibcon#*before write, iclass 22, count 2 2006.173.17:39:12.69#ibcon#enter sib2, iclass 22, count 2 2006.173.17:39:12.69#ibcon#flushed, iclass 22, count 2 2006.173.17:39:12.69#ibcon#about to write, iclass 22, count 2 2006.173.17:39:12.69#ibcon#wrote, iclass 22, count 2 2006.173.17:39:12.69#ibcon#about to read 3, iclass 22, count 2 2006.173.17:39:12.72#ibcon#read 3, iclass 22, count 2 2006.173.17:39:12.72#ibcon#about to read 4, iclass 22, count 2 2006.173.17:39:12.72#ibcon#read 4, iclass 22, count 2 2006.173.17:39:12.72#ibcon#about to read 5, iclass 22, count 2 2006.173.17:39:12.72#ibcon#read 5, iclass 22, count 2 2006.173.17:39:12.72#ibcon#about to read 6, iclass 22, count 2 2006.173.17:39:12.72#ibcon#read 6, iclass 22, count 2 2006.173.17:39:12.72#ibcon#end of sib2, iclass 22, count 2 2006.173.17:39:12.72#ibcon#*after write, iclass 22, count 2 2006.173.17:39:12.72#ibcon#*before return 0, iclass 22, count 2 2006.173.17:39:12.72#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.17:39:12.72#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.17:39:12.72#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.17:39:12.72#ibcon#ireg 7 cls_cnt 0 2006.173.17:39:12.72#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.17:39:12.84#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.17:39:12.84#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.17:39:12.84#ibcon#enter wrdev, iclass 22, count 0 2006.173.17:39:12.84#ibcon#first serial, iclass 22, count 0 2006.173.17:39:12.84#ibcon#enter sib2, iclass 22, count 0 2006.173.17:39:12.84#ibcon#flushed, iclass 22, count 0 2006.173.17:39:12.84#ibcon#about to write, iclass 22, count 0 2006.173.17:39:12.84#ibcon#wrote, iclass 22, count 0 2006.173.17:39:12.84#ibcon#about to read 3, iclass 22, count 0 2006.173.17:39:12.86#ibcon#read 3, iclass 22, count 0 2006.173.17:39:12.86#ibcon#about to read 4, iclass 22, count 0 2006.173.17:39:12.86#ibcon#read 4, iclass 22, count 0 2006.173.17:39:12.86#ibcon#about to read 5, iclass 22, count 0 2006.173.17:39:12.86#ibcon#read 5, iclass 22, count 0 2006.173.17:39:12.86#ibcon#about to read 6, iclass 22, count 0 2006.173.17:39:12.86#ibcon#read 6, iclass 22, count 0 2006.173.17:39:12.86#ibcon#end of sib2, iclass 22, count 0 2006.173.17:39:12.86#ibcon#*mode == 0, iclass 22, count 0 2006.173.17:39:12.86#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.17:39:12.86#ibcon#[27=USB\r\n] 2006.173.17:39:12.86#ibcon#*before write, iclass 22, count 0 2006.173.17:39:12.86#ibcon#enter sib2, iclass 22, count 0 2006.173.17:39:12.86#ibcon#flushed, iclass 22, count 0 2006.173.17:39:12.86#ibcon#about to write, iclass 22, count 0 2006.173.17:39:12.86#ibcon#wrote, iclass 22, count 0 2006.173.17:39:12.86#ibcon#about to read 3, iclass 22, count 0 2006.173.17:39:12.89#ibcon#read 3, iclass 22, count 0 2006.173.17:39:12.89#ibcon#about to read 4, iclass 22, count 0 2006.173.17:39:12.89#ibcon#read 4, iclass 22, count 0 2006.173.17:39:12.89#ibcon#about to read 5, iclass 22, count 0 2006.173.17:39:12.89#ibcon#read 5, iclass 22, count 0 2006.173.17:39:12.89#ibcon#about to read 6, iclass 22, count 0 2006.173.17:39:12.89#ibcon#read 6, iclass 22, count 0 2006.173.17:39:12.89#ibcon#end of sib2, iclass 22, count 0 2006.173.17:39:12.89#ibcon#*after write, iclass 22, count 0 2006.173.17:39:12.89#ibcon#*before return 0, iclass 22, count 0 2006.173.17:39:12.89#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.17:39:12.89#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.17:39:12.89#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.17:39:12.89#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.17:39:12.89$vck44/vblo=7,734.99 2006.173.17:39:12.89#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.17:39:12.89#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.17:39:12.89#ibcon#ireg 17 cls_cnt 0 2006.173.17:39:12.89#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.17:39:12.89#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.17:39:12.89#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.17:39:12.89#ibcon#enter wrdev, iclass 24, count 0 2006.173.17:39:12.89#ibcon#first serial, iclass 24, count 0 2006.173.17:39:12.89#ibcon#enter sib2, iclass 24, count 0 2006.173.17:39:12.89#ibcon#flushed, iclass 24, count 0 2006.173.17:39:12.89#ibcon#about to write, iclass 24, count 0 2006.173.17:39:12.89#ibcon#wrote, iclass 24, count 0 2006.173.17:39:12.89#ibcon#about to read 3, iclass 24, count 0 2006.173.17:39:12.91#ibcon#read 3, iclass 24, count 0 2006.173.17:39:12.91#ibcon#about to read 4, iclass 24, count 0 2006.173.17:39:12.91#ibcon#read 4, iclass 24, count 0 2006.173.17:39:12.91#ibcon#about to read 5, iclass 24, count 0 2006.173.17:39:12.91#ibcon#read 5, iclass 24, count 0 2006.173.17:39:12.91#ibcon#about to read 6, iclass 24, count 0 2006.173.17:39:12.91#ibcon#read 6, iclass 24, count 0 2006.173.17:39:12.91#ibcon#end of sib2, iclass 24, count 0 2006.173.17:39:12.91#ibcon#*mode == 0, iclass 24, count 0 2006.173.17:39:12.91#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.17:39:12.91#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.17:39:12.91#ibcon#*before write, iclass 24, count 0 2006.173.17:39:12.91#ibcon#enter sib2, iclass 24, count 0 2006.173.17:39:12.91#ibcon#flushed, iclass 24, count 0 2006.173.17:39:12.91#ibcon#about to write, iclass 24, count 0 2006.173.17:39:12.91#ibcon#wrote, iclass 24, count 0 2006.173.17:39:12.91#ibcon#about to read 3, iclass 24, count 0 2006.173.17:39:12.95#ibcon#read 3, iclass 24, count 0 2006.173.17:39:12.95#ibcon#about to read 4, iclass 24, count 0 2006.173.17:39:12.95#ibcon#read 4, iclass 24, count 0 2006.173.17:39:12.95#ibcon#about to read 5, iclass 24, count 0 2006.173.17:39:12.95#ibcon#read 5, iclass 24, count 0 2006.173.17:39:12.95#ibcon#about to read 6, iclass 24, count 0 2006.173.17:39:12.95#ibcon#read 6, iclass 24, count 0 2006.173.17:39:12.95#ibcon#end of sib2, iclass 24, count 0 2006.173.17:39:12.95#ibcon#*after write, iclass 24, count 0 2006.173.17:39:12.95#ibcon#*before return 0, iclass 24, count 0 2006.173.17:39:12.95#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.17:39:12.95#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.17:39:12.95#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.17:39:12.95#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.17:39:12.95$vck44/vb=7,4 2006.173.17:39:12.95#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.17:39:12.95#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.17:39:12.95#ibcon#ireg 11 cls_cnt 2 2006.173.17:39:12.95#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.17:39:13.01#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.17:39:13.01#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.17:39:13.01#ibcon#enter wrdev, iclass 26, count 2 2006.173.17:39:13.01#ibcon#first serial, iclass 26, count 2 2006.173.17:39:13.01#ibcon#enter sib2, iclass 26, count 2 2006.173.17:39:13.01#ibcon#flushed, iclass 26, count 2 2006.173.17:39:13.01#ibcon#about to write, iclass 26, count 2 2006.173.17:39:13.01#ibcon#wrote, iclass 26, count 2 2006.173.17:39:13.01#ibcon#about to read 3, iclass 26, count 2 2006.173.17:39:13.03#ibcon#read 3, iclass 26, count 2 2006.173.17:39:13.03#ibcon#about to read 4, iclass 26, count 2 2006.173.17:39:13.03#ibcon#read 4, iclass 26, count 2 2006.173.17:39:13.03#ibcon#about to read 5, iclass 26, count 2 2006.173.17:39:13.03#ibcon#read 5, iclass 26, count 2 2006.173.17:39:13.03#ibcon#about to read 6, iclass 26, count 2 2006.173.17:39:13.03#ibcon#read 6, iclass 26, count 2 2006.173.17:39:13.03#ibcon#end of sib2, iclass 26, count 2 2006.173.17:39:13.03#ibcon#*mode == 0, iclass 26, count 2 2006.173.17:39:13.03#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.17:39:13.03#ibcon#[27=AT07-04\r\n] 2006.173.17:39:13.03#ibcon#*before write, iclass 26, count 2 2006.173.17:39:13.03#ibcon#enter sib2, iclass 26, count 2 2006.173.17:39:13.03#ibcon#flushed, iclass 26, count 2 2006.173.17:39:13.03#ibcon#about to write, iclass 26, count 2 2006.173.17:39:13.03#ibcon#wrote, iclass 26, count 2 2006.173.17:39:13.03#ibcon#about to read 3, iclass 26, count 2 2006.173.17:39:13.06#ibcon#read 3, iclass 26, count 2 2006.173.17:39:13.06#ibcon#about to read 4, iclass 26, count 2 2006.173.17:39:13.06#ibcon#read 4, iclass 26, count 2 2006.173.17:39:13.06#ibcon#about to read 5, iclass 26, count 2 2006.173.17:39:13.06#ibcon#read 5, iclass 26, count 2 2006.173.17:39:13.06#ibcon#about to read 6, iclass 26, count 2 2006.173.17:39:13.06#ibcon#read 6, iclass 26, count 2 2006.173.17:39:13.06#ibcon#end of sib2, iclass 26, count 2 2006.173.17:39:13.06#ibcon#*after write, iclass 26, count 2 2006.173.17:39:13.06#ibcon#*before return 0, iclass 26, count 2 2006.173.17:39:13.06#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.17:39:13.06#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.17:39:13.06#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.17:39:13.06#ibcon#ireg 7 cls_cnt 0 2006.173.17:39:13.06#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.17:39:13.18#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.17:39:13.18#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.17:39:13.18#ibcon#enter wrdev, iclass 26, count 0 2006.173.17:39:13.18#ibcon#first serial, iclass 26, count 0 2006.173.17:39:13.18#ibcon#enter sib2, iclass 26, count 0 2006.173.17:39:13.18#ibcon#flushed, iclass 26, count 0 2006.173.17:39:13.18#ibcon#about to write, iclass 26, count 0 2006.173.17:39:13.18#ibcon#wrote, iclass 26, count 0 2006.173.17:39:13.18#ibcon#about to read 3, iclass 26, count 0 2006.173.17:39:13.20#ibcon#read 3, iclass 26, count 0 2006.173.17:39:13.20#ibcon#about to read 4, iclass 26, count 0 2006.173.17:39:13.20#ibcon#read 4, iclass 26, count 0 2006.173.17:39:13.20#ibcon#about to read 5, iclass 26, count 0 2006.173.17:39:13.20#ibcon#read 5, iclass 26, count 0 2006.173.17:39:13.20#ibcon#about to read 6, iclass 26, count 0 2006.173.17:39:13.20#ibcon#read 6, iclass 26, count 0 2006.173.17:39:13.20#ibcon#end of sib2, iclass 26, count 0 2006.173.17:39:13.20#ibcon#*mode == 0, iclass 26, count 0 2006.173.17:39:13.20#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.17:39:13.20#ibcon#[27=USB\r\n] 2006.173.17:39:13.20#ibcon#*before write, iclass 26, count 0 2006.173.17:39:13.20#ibcon#enter sib2, iclass 26, count 0 2006.173.17:39:13.20#ibcon#flushed, iclass 26, count 0 2006.173.17:39:13.20#ibcon#about to write, iclass 26, count 0 2006.173.17:39:13.20#ibcon#wrote, iclass 26, count 0 2006.173.17:39:13.20#ibcon#about to read 3, iclass 26, count 0 2006.173.17:39:13.23#ibcon#read 3, iclass 26, count 0 2006.173.17:39:13.23#ibcon#about to read 4, iclass 26, count 0 2006.173.17:39:13.23#ibcon#read 4, iclass 26, count 0 2006.173.17:39:13.23#ibcon#about to read 5, iclass 26, count 0 2006.173.17:39:13.23#ibcon#read 5, iclass 26, count 0 2006.173.17:39:13.23#ibcon#about to read 6, iclass 26, count 0 2006.173.17:39:13.23#ibcon#read 6, iclass 26, count 0 2006.173.17:39:13.23#ibcon#end of sib2, iclass 26, count 0 2006.173.17:39:13.23#ibcon#*after write, iclass 26, count 0 2006.173.17:39:13.23#ibcon#*before return 0, iclass 26, count 0 2006.173.17:39:13.23#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.17:39:13.23#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.17:39:13.23#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.17:39:13.23#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.17:39:13.23$vck44/vblo=8,744.99 2006.173.17:39:13.23#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.17:39:13.23#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.17:39:13.23#ibcon#ireg 17 cls_cnt 0 2006.173.17:39:13.23#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.17:39:13.23#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.17:39:13.23#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.17:39:13.23#ibcon#enter wrdev, iclass 28, count 0 2006.173.17:39:13.23#ibcon#first serial, iclass 28, count 0 2006.173.17:39:13.23#ibcon#enter sib2, iclass 28, count 0 2006.173.17:39:13.23#ibcon#flushed, iclass 28, count 0 2006.173.17:39:13.23#ibcon#about to write, iclass 28, count 0 2006.173.17:39:13.23#ibcon#wrote, iclass 28, count 0 2006.173.17:39:13.23#ibcon#about to read 3, iclass 28, count 0 2006.173.17:39:13.25#ibcon#read 3, iclass 28, count 0 2006.173.17:39:13.25#ibcon#about to read 4, iclass 28, count 0 2006.173.17:39:13.25#ibcon#read 4, iclass 28, count 0 2006.173.17:39:13.25#ibcon#about to read 5, iclass 28, count 0 2006.173.17:39:13.25#ibcon#read 5, iclass 28, count 0 2006.173.17:39:13.25#ibcon#about to read 6, iclass 28, count 0 2006.173.17:39:13.25#ibcon#read 6, iclass 28, count 0 2006.173.17:39:13.25#ibcon#end of sib2, iclass 28, count 0 2006.173.17:39:13.25#ibcon#*mode == 0, iclass 28, count 0 2006.173.17:39:13.25#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.17:39:13.25#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.17:39:13.25#ibcon#*before write, iclass 28, count 0 2006.173.17:39:13.25#ibcon#enter sib2, iclass 28, count 0 2006.173.17:39:13.25#ibcon#flushed, iclass 28, count 0 2006.173.17:39:13.25#ibcon#about to write, iclass 28, count 0 2006.173.17:39:13.25#ibcon#wrote, iclass 28, count 0 2006.173.17:39:13.25#ibcon#about to read 3, iclass 28, count 0 2006.173.17:39:13.29#ibcon#read 3, iclass 28, count 0 2006.173.17:39:13.29#ibcon#about to read 4, iclass 28, count 0 2006.173.17:39:13.29#ibcon#read 4, iclass 28, count 0 2006.173.17:39:13.29#ibcon#about to read 5, iclass 28, count 0 2006.173.17:39:13.29#ibcon#read 5, iclass 28, count 0 2006.173.17:39:13.29#ibcon#about to read 6, iclass 28, count 0 2006.173.17:39:13.29#ibcon#read 6, iclass 28, count 0 2006.173.17:39:13.29#ibcon#end of sib2, iclass 28, count 0 2006.173.17:39:13.29#ibcon#*after write, iclass 28, count 0 2006.173.17:39:13.29#ibcon#*before return 0, iclass 28, count 0 2006.173.17:39:13.29#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.17:39:13.29#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.17:39:13.29#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.17:39:13.29#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.17:39:13.29$vck44/vb=8,4 2006.173.17:39:13.29#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.17:39:13.29#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.17:39:13.29#ibcon#ireg 11 cls_cnt 2 2006.173.17:39:13.29#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.17:39:13.35#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.17:39:13.35#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.17:39:13.35#ibcon#enter wrdev, iclass 30, count 2 2006.173.17:39:13.35#ibcon#first serial, iclass 30, count 2 2006.173.17:39:13.35#ibcon#enter sib2, iclass 30, count 2 2006.173.17:39:13.35#ibcon#flushed, iclass 30, count 2 2006.173.17:39:13.35#ibcon#about to write, iclass 30, count 2 2006.173.17:39:13.35#ibcon#wrote, iclass 30, count 2 2006.173.17:39:13.35#ibcon#about to read 3, iclass 30, count 2 2006.173.17:39:13.37#ibcon#read 3, iclass 30, count 2 2006.173.17:39:13.37#ibcon#about to read 4, iclass 30, count 2 2006.173.17:39:13.37#ibcon#read 4, iclass 30, count 2 2006.173.17:39:13.37#ibcon#about to read 5, iclass 30, count 2 2006.173.17:39:13.37#ibcon#read 5, iclass 30, count 2 2006.173.17:39:13.37#ibcon#about to read 6, iclass 30, count 2 2006.173.17:39:13.37#ibcon#read 6, iclass 30, count 2 2006.173.17:39:13.37#ibcon#end of sib2, iclass 30, count 2 2006.173.17:39:13.37#ibcon#*mode == 0, iclass 30, count 2 2006.173.17:39:13.37#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.17:39:13.37#ibcon#[27=AT08-04\r\n] 2006.173.17:39:13.37#ibcon#*before write, iclass 30, count 2 2006.173.17:39:13.37#ibcon#enter sib2, iclass 30, count 2 2006.173.17:39:13.37#ibcon#flushed, iclass 30, count 2 2006.173.17:39:13.37#ibcon#about to write, iclass 30, count 2 2006.173.17:39:13.37#ibcon#wrote, iclass 30, count 2 2006.173.17:39:13.37#ibcon#about to read 3, iclass 30, count 2 2006.173.17:39:13.40#ibcon#read 3, iclass 30, count 2 2006.173.17:39:13.40#ibcon#about to read 4, iclass 30, count 2 2006.173.17:39:13.40#ibcon#read 4, iclass 30, count 2 2006.173.17:39:13.40#ibcon#about to read 5, iclass 30, count 2 2006.173.17:39:13.40#ibcon#read 5, iclass 30, count 2 2006.173.17:39:13.40#ibcon#about to read 6, iclass 30, count 2 2006.173.17:39:13.40#ibcon#read 6, iclass 30, count 2 2006.173.17:39:13.40#ibcon#end of sib2, iclass 30, count 2 2006.173.17:39:13.40#ibcon#*after write, iclass 30, count 2 2006.173.17:39:13.40#ibcon#*before return 0, iclass 30, count 2 2006.173.17:39:13.40#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.17:39:13.40#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.17:39:13.40#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.17:39:13.40#ibcon#ireg 7 cls_cnt 0 2006.173.17:39:13.40#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.17:39:13.52#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.17:39:13.52#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.17:39:13.52#ibcon#enter wrdev, iclass 30, count 0 2006.173.17:39:13.52#ibcon#first serial, iclass 30, count 0 2006.173.17:39:13.52#ibcon#enter sib2, iclass 30, count 0 2006.173.17:39:13.52#ibcon#flushed, iclass 30, count 0 2006.173.17:39:13.52#ibcon#about to write, iclass 30, count 0 2006.173.17:39:13.52#ibcon#wrote, iclass 30, count 0 2006.173.17:39:13.52#ibcon#about to read 3, iclass 30, count 0 2006.173.17:39:13.54#ibcon#read 3, iclass 30, count 0 2006.173.17:39:13.54#ibcon#about to read 4, iclass 30, count 0 2006.173.17:39:13.54#ibcon#read 4, iclass 30, count 0 2006.173.17:39:13.54#ibcon#about to read 5, iclass 30, count 0 2006.173.17:39:13.54#ibcon#read 5, iclass 30, count 0 2006.173.17:39:13.54#ibcon#about to read 6, iclass 30, count 0 2006.173.17:39:13.54#ibcon#read 6, iclass 30, count 0 2006.173.17:39:13.54#ibcon#end of sib2, iclass 30, count 0 2006.173.17:39:13.54#ibcon#*mode == 0, iclass 30, count 0 2006.173.17:39:13.54#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.17:39:13.54#ibcon#[27=USB\r\n] 2006.173.17:39:13.54#ibcon#*before write, iclass 30, count 0 2006.173.17:39:13.54#ibcon#enter sib2, iclass 30, count 0 2006.173.17:39:13.54#ibcon#flushed, iclass 30, count 0 2006.173.17:39:13.54#ibcon#about to write, iclass 30, count 0 2006.173.17:39:13.54#ibcon#wrote, iclass 30, count 0 2006.173.17:39:13.54#ibcon#about to read 3, iclass 30, count 0 2006.173.17:39:13.57#ibcon#read 3, iclass 30, count 0 2006.173.17:39:13.57#ibcon#about to read 4, iclass 30, count 0 2006.173.17:39:13.57#ibcon#read 4, iclass 30, count 0 2006.173.17:39:13.57#ibcon#about to read 5, iclass 30, count 0 2006.173.17:39:13.57#ibcon#read 5, iclass 30, count 0 2006.173.17:39:13.57#ibcon#about to read 6, iclass 30, count 0 2006.173.17:39:13.57#ibcon#read 6, iclass 30, count 0 2006.173.17:39:13.57#ibcon#end of sib2, iclass 30, count 0 2006.173.17:39:13.57#ibcon#*after write, iclass 30, count 0 2006.173.17:39:13.57#ibcon#*before return 0, iclass 30, count 0 2006.173.17:39:13.57#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.17:39:13.57#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.17:39:13.57#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.17:39:13.57#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.17:39:13.57$vck44/vabw=wide 2006.173.17:39:13.57#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.17:39:13.57#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.17:39:13.57#ibcon#ireg 8 cls_cnt 0 2006.173.17:39:13.57#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.17:39:13.57#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.17:39:13.57#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.17:39:13.57#ibcon#enter wrdev, iclass 32, count 0 2006.173.17:39:13.57#ibcon#first serial, iclass 32, count 0 2006.173.17:39:13.57#ibcon#enter sib2, iclass 32, count 0 2006.173.17:39:13.57#ibcon#flushed, iclass 32, count 0 2006.173.17:39:13.57#ibcon#about to write, iclass 32, count 0 2006.173.17:39:13.57#ibcon#wrote, iclass 32, count 0 2006.173.17:39:13.57#ibcon#about to read 3, iclass 32, count 0 2006.173.17:39:13.59#ibcon#read 3, iclass 32, count 0 2006.173.17:39:13.59#ibcon#about to read 4, iclass 32, count 0 2006.173.17:39:13.59#ibcon#read 4, iclass 32, count 0 2006.173.17:39:13.59#ibcon#about to read 5, iclass 32, count 0 2006.173.17:39:13.59#ibcon#read 5, iclass 32, count 0 2006.173.17:39:13.59#ibcon#about to read 6, iclass 32, count 0 2006.173.17:39:13.59#ibcon#read 6, iclass 32, count 0 2006.173.17:39:13.59#ibcon#end of sib2, iclass 32, count 0 2006.173.17:39:13.59#ibcon#*mode == 0, iclass 32, count 0 2006.173.17:39:13.59#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.17:39:13.59#ibcon#[25=BW32\r\n] 2006.173.17:39:13.59#ibcon#*before write, iclass 32, count 0 2006.173.17:39:13.59#ibcon#enter sib2, iclass 32, count 0 2006.173.17:39:13.59#ibcon#flushed, iclass 32, count 0 2006.173.17:39:13.59#ibcon#about to write, iclass 32, count 0 2006.173.17:39:13.59#ibcon#wrote, iclass 32, count 0 2006.173.17:39:13.59#ibcon#about to read 3, iclass 32, count 0 2006.173.17:39:13.62#ibcon#read 3, iclass 32, count 0 2006.173.17:39:13.62#ibcon#about to read 4, iclass 32, count 0 2006.173.17:39:13.62#ibcon#read 4, iclass 32, count 0 2006.173.17:39:13.62#ibcon#about to read 5, iclass 32, count 0 2006.173.17:39:13.62#ibcon#read 5, iclass 32, count 0 2006.173.17:39:13.62#ibcon#about to read 6, iclass 32, count 0 2006.173.17:39:13.62#ibcon#read 6, iclass 32, count 0 2006.173.17:39:13.62#ibcon#end of sib2, iclass 32, count 0 2006.173.17:39:13.62#ibcon#*after write, iclass 32, count 0 2006.173.17:39:13.62#ibcon#*before return 0, iclass 32, count 0 2006.173.17:39:13.62#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.17:39:13.62#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.17:39:13.62#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.17:39:13.62#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.17:39:13.62$vck44/vbbw=wide 2006.173.17:39:13.62#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.17:39:13.62#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.17:39:13.62#ibcon#ireg 8 cls_cnt 0 2006.173.17:39:13.62#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.17:39:13.69#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.17:39:13.69#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.17:39:13.69#ibcon#enter wrdev, iclass 34, count 0 2006.173.17:39:13.69#ibcon#first serial, iclass 34, count 0 2006.173.17:39:13.69#ibcon#enter sib2, iclass 34, count 0 2006.173.17:39:13.69#ibcon#flushed, iclass 34, count 0 2006.173.17:39:13.69#ibcon#about to write, iclass 34, count 0 2006.173.17:39:13.69#ibcon#wrote, iclass 34, count 0 2006.173.17:39:13.69#ibcon#about to read 3, iclass 34, count 0 2006.173.17:39:13.71#ibcon#read 3, iclass 34, count 0 2006.173.17:39:13.71#ibcon#about to read 4, iclass 34, count 0 2006.173.17:39:13.71#ibcon#read 4, iclass 34, count 0 2006.173.17:39:13.71#ibcon#about to read 5, iclass 34, count 0 2006.173.17:39:13.71#ibcon#read 5, iclass 34, count 0 2006.173.17:39:13.71#ibcon#about to read 6, iclass 34, count 0 2006.173.17:39:13.71#ibcon#read 6, iclass 34, count 0 2006.173.17:39:13.71#ibcon#end of sib2, iclass 34, count 0 2006.173.17:39:13.71#ibcon#*mode == 0, iclass 34, count 0 2006.173.17:39:13.71#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.17:39:13.71#ibcon#[27=BW32\r\n] 2006.173.17:39:13.71#ibcon#*before write, iclass 34, count 0 2006.173.17:39:13.71#ibcon#enter sib2, iclass 34, count 0 2006.173.17:39:13.71#ibcon#flushed, iclass 34, count 0 2006.173.17:39:13.71#ibcon#about to write, iclass 34, count 0 2006.173.17:39:13.71#ibcon#wrote, iclass 34, count 0 2006.173.17:39:13.71#ibcon#about to read 3, iclass 34, count 0 2006.173.17:39:13.74#ibcon#read 3, iclass 34, count 0 2006.173.17:39:13.74#ibcon#about to read 4, iclass 34, count 0 2006.173.17:39:13.74#ibcon#read 4, iclass 34, count 0 2006.173.17:39:13.74#ibcon#about to read 5, iclass 34, count 0 2006.173.17:39:13.74#ibcon#read 5, iclass 34, count 0 2006.173.17:39:13.74#ibcon#about to read 6, iclass 34, count 0 2006.173.17:39:13.74#ibcon#read 6, iclass 34, count 0 2006.173.17:39:13.74#ibcon#end of sib2, iclass 34, count 0 2006.173.17:39:13.74#ibcon#*after write, iclass 34, count 0 2006.173.17:39:13.74#ibcon#*before return 0, iclass 34, count 0 2006.173.17:39:13.74#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.17:39:13.74#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.17:39:13.74#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.17:39:13.74#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.17:39:13.74$setupk4/ifdk4 2006.173.17:39:13.74$ifdk4/lo= 2006.173.17:39:13.74$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.17:39:13.74$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.17:39:13.74$ifdk4/patch= 2006.173.17:39:13.74$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.17:39:13.74$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.17:39:13.74$setupk4/!*+20s 2006.173.17:39:19.49#abcon#<5=/14 1.0 2.3 20.211001002.3\r\n> 2006.173.17:39:19.51#abcon#{5=INTERFACE CLEAR} 2006.173.17:39:19.57#abcon#[5=S1D000X0/0*\r\n] 2006.173.17:39:27.14#trakl#Source acquired 2006.173.17:39:27.14#flagr#flagr/antenna,acquired 2006.173.17:39:28.25$setupk4/"tpicd 2006.173.17:39:28.25$setupk4/echo=off 2006.173.17:39:28.25$setupk4/xlog=off 2006.173.17:39:28.25:!2006.173.17:40:53 2006.173.17:40:53.00:preob 2006.173.17:40:53.13/onsource/TRACKING 2006.173.17:40:53.13:!2006.173.17:41:03 2006.173.17:41:03.00:"tape 2006.173.17:41:03.00:"st=record 2006.173.17:41:03.00:data_valid=on 2006.173.17:41:03.00:midob 2006.173.17:41:03.13/onsource/TRACKING 2006.173.17:41:03.13/wx/20.20,1002.3,100 2006.173.17:41:03.32/cable/+6.5141E-03 2006.173.17:41:04.41/va/01,07,usb,yes,35,38 2006.173.17:41:04.41/va/02,06,usb,yes,35,36 2006.173.17:41:04.41/va/03,05,usb,yes,44,46 2006.173.17:41:04.41/va/04,06,usb,yes,35,37 2006.173.17:41:04.41/va/05,04,usb,yes,28,28 2006.173.17:41:04.41/va/06,03,usb,yes,39,39 2006.173.17:41:04.41/va/07,04,usb,yes,31,33 2006.173.17:41:04.41/va/08,04,usb,yes,27,32 2006.173.17:41:04.64/valo/01,524.99,yes,locked 2006.173.17:41:04.64/valo/02,534.99,yes,locked 2006.173.17:41:04.64/valo/03,564.99,yes,locked 2006.173.17:41:04.64/valo/04,624.99,yes,locked 2006.173.17:41:04.64/valo/05,734.99,yes,locked 2006.173.17:41:04.64/valo/06,814.99,yes,locked 2006.173.17:41:04.64/valo/07,864.99,yes,locked 2006.173.17:41:04.64/valo/08,884.99,yes,locked 2006.173.17:41:05.73/vb/01,04,usb,yes,29,27 2006.173.17:41:05.73/vb/02,04,usb,yes,31,31 2006.173.17:41:05.73/vb/03,04,usb,yes,28,31 2006.173.17:41:05.73/vb/04,04,usb,yes,32,31 2006.173.17:41:05.73/vb/05,04,usb,yes,25,28 2006.173.17:41:05.73/vb/06,04,usb,yes,30,26 2006.173.17:41:05.73/vb/07,04,usb,yes,29,29 2006.173.17:41:05.73/vb/08,04,usb,yes,27,30 2006.173.17:41:05.97/vblo/01,629.99,yes,locked 2006.173.17:41:05.97/vblo/02,634.99,yes,locked 2006.173.17:41:05.97/vblo/03,649.99,yes,locked 2006.173.17:41:05.97/vblo/04,679.99,yes,locked 2006.173.17:41:05.97/vblo/05,709.99,yes,locked 2006.173.17:41:05.97/vblo/06,719.99,yes,locked 2006.173.17:41:05.97/vblo/07,734.99,yes,locked 2006.173.17:41:05.97/vblo/08,744.99,yes,locked 2006.173.17:41:06.12/vabw/8 2006.173.17:41:06.27/vbbw/8 2006.173.17:41:06.36/xfe/off,on,15.2 2006.173.17:41:06.73/ifatt/23,28,28,28 2006.173.17:41:07.08/fmout-gps/S +4.00E-07 2006.173.17:41:07.12:!2006.173.17:41:43 2006.173.17:41:43.00:data_valid=off 2006.173.17:41:43.00:"et 2006.173.17:41:43.00:!+3s 2006.173.17:41:46.01:"tape 2006.173.17:41:46.01:postob 2006.173.17:41:46.08/cable/+6.5114E-03 2006.173.17:41:46.08/wx/20.19,1002.3,100 2006.173.17:41:47.07/fmout-gps/S +4.00E-07 2006.173.17:41:47.07:scan_name=173-1742,jd0606,120 2006.173.17:41:47.07:source=2201+315,220314.98,314538.3,2000.0,ccw 2006.173.17:41:48.13#flagr#flagr/antenna,new-source 2006.173.17:41:48.13:checkk5 2006.173.17:41:48.49/chk_autoobs//k5ts1/ autoobs is running! 2006.173.17:41:48.89/chk_autoobs//k5ts2/ autoobs is running! 2006.173.17:41:49.33/chk_autoobs//k5ts3/ autoobs is running! 2006.173.17:41:49.71/chk_autoobs//k5ts4/ autoobs is running! 2006.173.17:41:50.09/chk_obsdata//k5ts1/T1731741??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.17:41:50.50/chk_obsdata//k5ts2/T1731741??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.17:41:50.90/chk_obsdata//k5ts3/T1731741??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.17:41:51.31/chk_obsdata//k5ts4/T1731741??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.17:41:52.03/k5log//k5ts1_log_newline 2006.173.17:41:52.75/k5log//k5ts2_log_newline 2006.173.17:41:53.49/k5log//k5ts3_log_newline 2006.173.17:41:54.19/k5log//k5ts4_log_newline 2006.173.17:41:54.21/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.17:41:54.21:setupk4=1 2006.173.17:41:54.21$setupk4/echo=on 2006.173.17:41:54.21$setupk4/pcalon 2006.173.17:41:54.21$pcalon/"no phase cal control is implemented here 2006.173.17:41:54.21$setupk4/"tpicd=stop 2006.173.17:41:54.21$setupk4/"rec=synch_on 2006.173.17:41:54.21$setupk4/"rec_mode=128 2006.173.17:41:54.21$setupk4/!* 2006.173.17:41:54.21$setupk4/recpk4 2006.173.17:41:54.21$recpk4/recpatch= 2006.173.17:41:54.21$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.17:41:54.21$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.17:41:54.22$setupk4/vck44 2006.173.17:41:54.22$vck44/valo=1,524.99 2006.173.17:41:54.22#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.17:41:54.22#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.17:41:54.22#ibcon#ireg 17 cls_cnt 0 2006.173.17:41:54.22#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.17:41:54.22#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.17:41:54.22#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.17:41:54.22#ibcon#enter wrdev, iclass 31, count 0 2006.173.17:41:54.22#ibcon#first serial, iclass 31, count 0 2006.173.17:41:54.22#ibcon#enter sib2, iclass 31, count 0 2006.173.17:41:54.22#ibcon#flushed, iclass 31, count 0 2006.173.17:41:54.22#ibcon#about to write, iclass 31, count 0 2006.173.17:41:54.22#ibcon#wrote, iclass 31, count 0 2006.173.17:41:54.22#ibcon#about to read 3, iclass 31, count 0 2006.173.17:41:54.23#ibcon#read 3, iclass 31, count 0 2006.173.17:41:54.23#ibcon#about to read 4, iclass 31, count 0 2006.173.17:41:54.23#ibcon#read 4, iclass 31, count 0 2006.173.17:41:54.23#ibcon#about to read 5, iclass 31, count 0 2006.173.17:41:54.23#ibcon#read 5, iclass 31, count 0 2006.173.17:41:54.23#ibcon#about to read 6, iclass 31, count 0 2006.173.17:41:54.23#ibcon#read 6, iclass 31, count 0 2006.173.17:41:54.23#ibcon#end of sib2, iclass 31, count 0 2006.173.17:41:54.23#ibcon#*mode == 0, iclass 31, count 0 2006.173.17:41:54.23#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.17:41:54.23#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.17:41:54.23#ibcon#*before write, iclass 31, count 0 2006.173.17:41:54.23#ibcon#enter sib2, iclass 31, count 0 2006.173.17:41:54.23#ibcon#flushed, iclass 31, count 0 2006.173.17:41:54.23#ibcon#about to write, iclass 31, count 0 2006.173.17:41:54.23#ibcon#wrote, iclass 31, count 0 2006.173.17:41:54.23#ibcon#about to read 3, iclass 31, count 0 2006.173.17:41:54.28#ibcon#read 3, iclass 31, count 0 2006.173.17:41:54.28#ibcon#about to read 4, iclass 31, count 0 2006.173.17:41:54.28#ibcon#read 4, iclass 31, count 0 2006.173.17:41:54.28#ibcon#about to read 5, iclass 31, count 0 2006.173.17:41:54.28#ibcon#read 5, iclass 31, count 0 2006.173.17:41:54.28#ibcon#about to read 6, iclass 31, count 0 2006.173.17:41:54.28#ibcon#read 6, iclass 31, count 0 2006.173.17:41:54.28#ibcon#end of sib2, iclass 31, count 0 2006.173.17:41:54.28#ibcon#*after write, iclass 31, count 0 2006.173.17:41:54.28#ibcon#*before return 0, iclass 31, count 0 2006.173.17:41:54.28#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.17:41:54.28#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.17:41:54.28#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.17:41:54.28#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.17:41:54.28$vck44/va=1,7 2006.173.17:41:54.28#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.173.17:41:54.28#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.173.17:41:54.28#ibcon#ireg 11 cls_cnt 2 2006.173.17:41:54.28#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.17:41:54.28#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.17:41:54.28#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.17:41:54.28#ibcon#enter wrdev, iclass 33, count 2 2006.173.17:41:54.28#ibcon#first serial, iclass 33, count 2 2006.173.17:41:54.28#ibcon#enter sib2, iclass 33, count 2 2006.173.17:41:54.28#ibcon#flushed, iclass 33, count 2 2006.173.17:41:54.28#ibcon#about to write, iclass 33, count 2 2006.173.17:41:54.28#ibcon#wrote, iclass 33, count 2 2006.173.17:41:54.28#ibcon#about to read 3, iclass 33, count 2 2006.173.17:41:54.30#ibcon#read 3, iclass 33, count 2 2006.173.17:41:54.30#ibcon#about to read 4, iclass 33, count 2 2006.173.17:41:54.30#ibcon#read 4, iclass 33, count 2 2006.173.17:41:54.30#ibcon#about to read 5, iclass 33, count 2 2006.173.17:41:54.30#ibcon#read 5, iclass 33, count 2 2006.173.17:41:54.30#ibcon#about to read 6, iclass 33, count 2 2006.173.17:41:54.30#ibcon#read 6, iclass 33, count 2 2006.173.17:41:54.30#ibcon#end of sib2, iclass 33, count 2 2006.173.17:41:54.30#ibcon#*mode == 0, iclass 33, count 2 2006.173.17:41:54.30#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.173.17:41:54.30#ibcon#[25=AT01-07\r\n] 2006.173.17:41:54.30#ibcon#*before write, iclass 33, count 2 2006.173.17:41:54.30#ibcon#enter sib2, iclass 33, count 2 2006.173.17:41:54.30#ibcon#flushed, iclass 33, count 2 2006.173.17:41:54.30#ibcon#about to write, iclass 33, count 2 2006.173.17:41:54.30#ibcon#wrote, iclass 33, count 2 2006.173.17:41:54.30#ibcon#about to read 3, iclass 33, count 2 2006.173.17:41:54.33#ibcon#read 3, iclass 33, count 2 2006.173.17:41:54.33#ibcon#about to read 4, iclass 33, count 2 2006.173.17:41:54.33#ibcon#read 4, iclass 33, count 2 2006.173.17:41:54.33#ibcon#about to read 5, iclass 33, count 2 2006.173.17:41:54.33#ibcon#read 5, iclass 33, count 2 2006.173.17:41:54.33#ibcon#about to read 6, iclass 33, count 2 2006.173.17:41:54.33#ibcon#read 6, iclass 33, count 2 2006.173.17:41:54.33#ibcon#end of sib2, iclass 33, count 2 2006.173.17:41:54.33#ibcon#*after write, iclass 33, count 2 2006.173.17:41:54.33#ibcon#*before return 0, iclass 33, count 2 2006.173.17:41:54.33#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.17:41:54.33#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.173.17:41:54.33#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.173.17:41:54.33#ibcon#ireg 7 cls_cnt 0 2006.173.17:41:54.33#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.17:41:54.45#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.17:41:54.45#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.17:41:54.45#ibcon#enter wrdev, iclass 33, count 0 2006.173.17:41:54.45#ibcon#first serial, iclass 33, count 0 2006.173.17:41:54.45#ibcon#enter sib2, iclass 33, count 0 2006.173.17:41:54.45#ibcon#flushed, iclass 33, count 0 2006.173.17:41:54.45#ibcon#about to write, iclass 33, count 0 2006.173.17:41:54.45#ibcon#wrote, iclass 33, count 0 2006.173.17:41:54.45#ibcon#about to read 3, iclass 33, count 0 2006.173.17:41:54.47#ibcon#read 3, iclass 33, count 0 2006.173.17:41:54.47#ibcon#about to read 4, iclass 33, count 0 2006.173.17:41:54.47#ibcon#read 4, iclass 33, count 0 2006.173.17:41:54.47#ibcon#about to read 5, iclass 33, count 0 2006.173.17:41:54.47#ibcon#read 5, iclass 33, count 0 2006.173.17:41:54.47#ibcon#about to read 6, iclass 33, count 0 2006.173.17:41:54.47#ibcon#read 6, iclass 33, count 0 2006.173.17:41:54.47#ibcon#end of sib2, iclass 33, count 0 2006.173.17:41:54.47#ibcon#*mode == 0, iclass 33, count 0 2006.173.17:41:54.47#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.17:41:54.47#ibcon#[25=USB\r\n] 2006.173.17:41:54.47#ibcon#*before write, iclass 33, count 0 2006.173.17:41:54.47#ibcon#enter sib2, iclass 33, count 0 2006.173.17:41:54.47#ibcon#flushed, iclass 33, count 0 2006.173.17:41:54.47#ibcon#about to write, iclass 33, count 0 2006.173.17:41:54.47#ibcon#wrote, iclass 33, count 0 2006.173.17:41:54.47#ibcon#about to read 3, iclass 33, count 0 2006.173.17:41:54.50#ibcon#read 3, iclass 33, count 0 2006.173.17:41:54.50#ibcon#about to read 4, iclass 33, count 0 2006.173.17:41:54.50#ibcon#read 4, iclass 33, count 0 2006.173.17:41:54.50#ibcon#about to read 5, iclass 33, count 0 2006.173.17:41:54.50#ibcon#read 5, iclass 33, count 0 2006.173.17:41:54.50#ibcon#about to read 6, iclass 33, count 0 2006.173.17:41:54.50#ibcon#read 6, iclass 33, count 0 2006.173.17:41:54.50#ibcon#end of sib2, iclass 33, count 0 2006.173.17:41:54.50#ibcon#*after write, iclass 33, count 0 2006.173.17:41:54.50#ibcon#*before return 0, iclass 33, count 0 2006.173.17:41:54.50#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.17:41:54.50#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.173.17:41:54.50#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.17:41:54.50#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.17:41:54.50$vck44/valo=2,534.99 2006.173.17:41:54.50#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.17:41:54.50#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.17:41:54.50#ibcon#ireg 17 cls_cnt 0 2006.173.17:41:54.50#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.17:41:54.50#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.17:41:54.50#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.17:41:54.50#ibcon#enter wrdev, iclass 35, count 0 2006.173.17:41:54.50#ibcon#first serial, iclass 35, count 0 2006.173.17:41:54.50#ibcon#enter sib2, iclass 35, count 0 2006.173.17:41:54.50#ibcon#flushed, iclass 35, count 0 2006.173.17:41:54.50#ibcon#about to write, iclass 35, count 0 2006.173.17:41:54.50#ibcon#wrote, iclass 35, count 0 2006.173.17:41:54.50#ibcon#about to read 3, iclass 35, count 0 2006.173.17:41:54.52#ibcon#read 3, iclass 35, count 0 2006.173.17:41:54.52#ibcon#about to read 4, iclass 35, count 0 2006.173.17:41:54.52#ibcon#read 4, iclass 35, count 0 2006.173.17:41:54.52#ibcon#about to read 5, iclass 35, count 0 2006.173.17:41:54.52#ibcon#read 5, iclass 35, count 0 2006.173.17:41:54.52#ibcon#about to read 6, iclass 35, count 0 2006.173.17:41:54.52#ibcon#read 6, iclass 35, count 0 2006.173.17:41:54.52#ibcon#end of sib2, iclass 35, count 0 2006.173.17:41:54.52#ibcon#*mode == 0, iclass 35, count 0 2006.173.17:41:54.52#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.17:41:54.52#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.17:41:54.52#ibcon#*before write, iclass 35, count 0 2006.173.17:41:54.52#ibcon#enter sib2, iclass 35, count 0 2006.173.17:41:54.52#ibcon#flushed, iclass 35, count 0 2006.173.17:41:54.52#ibcon#about to write, iclass 35, count 0 2006.173.17:41:54.52#ibcon#wrote, iclass 35, count 0 2006.173.17:41:54.52#ibcon#about to read 3, iclass 35, count 0 2006.173.17:41:54.56#ibcon#read 3, iclass 35, count 0 2006.173.17:41:54.56#ibcon#about to read 4, iclass 35, count 0 2006.173.17:41:54.56#ibcon#read 4, iclass 35, count 0 2006.173.17:41:54.56#ibcon#about to read 5, iclass 35, count 0 2006.173.17:41:54.56#ibcon#read 5, iclass 35, count 0 2006.173.17:41:54.56#ibcon#about to read 6, iclass 35, count 0 2006.173.17:41:54.56#ibcon#read 6, iclass 35, count 0 2006.173.17:41:54.56#ibcon#end of sib2, iclass 35, count 0 2006.173.17:41:54.56#ibcon#*after write, iclass 35, count 0 2006.173.17:41:54.56#ibcon#*before return 0, iclass 35, count 0 2006.173.17:41:54.56#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.17:41:54.56#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.17:41:54.56#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.17:41:54.56#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.17:41:54.56$vck44/va=2,6 2006.173.17:41:54.56#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.173.17:41:54.56#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.173.17:41:54.56#ibcon#ireg 11 cls_cnt 2 2006.173.17:41:54.56#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.17:41:54.62#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.17:41:54.62#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.17:41:54.62#ibcon#enter wrdev, iclass 37, count 2 2006.173.17:41:54.62#ibcon#first serial, iclass 37, count 2 2006.173.17:41:54.62#ibcon#enter sib2, iclass 37, count 2 2006.173.17:41:54.62#ibcon#flushed, iclass 37, count 2 2006.173.17:41:54.62#ibcon#about to write, iclass 37, count 2 2006.173.17:41:54.62#ibcon#wrote, iclass 37, count 2 2006.173.17:41:54.62#ibcon#about to read 3, iclass 37, count 2 2006.173.17:41:54.64#ibcon#read 3, iclass 37, count 2 2006.173.17:41:54.64#ibcon#about to read 4, iclass 37, count 2 2006.173.17:41:54.64#ibcon#read 4, iclass 37, count 2 2006.173.17:41:54.64#ibcon#about to read 5, iclass 37, count 2 2006.173.17:41:54.64#ibcon#read 5, iclass 37, count 2 2006.173.17:41:54.64#ibcon#about to read 6, iclass 37, count 2 2006.173.17:41:54.64#ibcon#read 6, iclass 37, count 2 2006.173.17:41:54.64#ibcon#end of sib2, iclass 37, count 2 2006.173.17:41:54.64#ibcon#*mode == 0, iclass 37, count 2 2006.173.17:41:54.64#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.173.17:41:54.64#ibcon#[25=AT02-06\r\n] 2006.173.17:41:54.64#ibcon#*before write, iclass 37, count 2 2006.173.17:41:54.64#ibcon#enter sib2, iclass 37, count 2 2006.173.17:41:54.64#ibcon#flushed, iclass 37, count 2 2006.173.17:41:54.64#ibcon#about to write, iclass 37, count 2 2006.173.17:41:54.64#ibcon#wrote, iclass 37, count 2 2006.173.17:41:54.64#ibcon#about to read 3, iclass 37, count 2 2006.173.17:41:54.67#ibcon#read 3, iclass 37, count 2 2006.173.17:41:54.67#ibcon#about to read 4, iclass 37, count 2 2006.173.17:41:54.67#ibcon#read 4, iclass 37, count 2 2006.173.17:41:54.67#ibcon#about to read 5, iclass 37, count 2 2006.173.17:41:54.67#ibcon#read 5, iclass 37, count 2 2006.173.17:41:54.67#ibcon#about to read 6, iclass 37, count 2 2006.173.17:41:54.67#ibcon#read 6, iclass 37, count 2 2006.173.17:41:54.67#ibcon#end of sib2, iclass 37, count 2 2006.173.17:41:54.67#ibcon#*after write, iclass 37, count 2 2006.173.17:41:54.67#ibcon#*before return 0, iclass 37, count 2 2006.173.17:41:54.67#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.17:41:54.67#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.173.17:41:54.67#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.173.17:41:54.67#ibcon#ireg 7 cls_cnt 0 2006.173.17:41:54.67#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.17:41:54.79#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.17:41:54.79#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.17:41:54.79#ibcon#enter wrdev, iclass 37, count 0 2006.173.17:41:54.79#ibcon#first serial, iclass 37, count 0 2006.173.17:41:54.79#ibcon#enter sib2, iclass 37, count 0 2006.173.17:41:54.79#ibcon#flushed, iclass 37, count 0 2006.173.17:41:54.79#ibcon#about to write, iclass 37, count 0 2006.173.17:41:54.79#ibcon#wrote, iclass 37, count 0 2006.173.17:41:54.79#ibcon#about to read 3, iclass 37, count 0 2006.173.17:41:54.81#ibcon#read 3, iclass 37, count 0 2006.173.17:41:54.81#ibcon#about to read 4, iclass 37, count 0 2006.173.17:41:54.81#ibcon#read 4, iclass 37, count 0 2006.173.17:41:54.81#ibcon#about to read 5, iclass 37, count 0 2006.173.17:41:54.81#ibcon#read 5, iclass 37, count 0 2006.173.17:41:54.81#ibcon#about to read 6, iclass 37, count 0 2006.173.17:41:54.81#ibcon#read 6, iclass 37, count 0 2006.173.17:41:54.81#ibcon#end of sib2, iclass 37, count 0 2006.173.17:41:54.81#ibcon#*mode == 0, iclass 37, count 0 2006.173.17:41:54.81#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.17:41:54.81#ibcon#[25=USB\r\n] 2006.173.17:41:54.81#ibcon#*before write, iclass 37, count 0 2006.173.17:41:54.81#ibcon#enter sib2, iclass 37, count 0 2006.173.17:41:54.81#ibcon#flushed, iclass 37, count 0 2006.173.17:41:54.81#ibcon#about to write, iclass 37, count 0 2006.173.17:41:54.81#ibcon#wrote, iclass 37, count 0 2006.173.17:41:54.81#ibcon#about to read 3, iclass 37, count 0 2006.173.17:41:54.84#ibcon#read 3, iclass 37, count 0 2006.173.17:41:54.84#ibcon#about to read 4, iclass 37, count 0 2006.173.17:41:54.84#ibcon#read 4, iclass 37, count 0 2006.173.17:41:54.84#ibcon#about to read 5, iclass 37, count 0 2006.173.17:41:54.84#ibcon#read 5, iclass 37, count 0 2006.173.17:41:54.84#ibcon#about to read 6, iclass 37, count 0 2006.173.17:41:54.84#ibcon#read 6, iclass 37, count 0 2006.173.17:41:54.84#ibcon#end of sib2, iclass 37, count 0 2006.173.17:41:54.84#ibcon#*after write, iclass 37, count 0 2006.173.17:41:54.84#ibcon#*before return 0, iclass 37, count 0 2006.173.17:41:54.84#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.17:41:54.84#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.173.17:41:54.84#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.17:41:54.84#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.17:41:54.84$vck44/valo=3,564.99 2006.173.17:41:54.84#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.17:41:54.84#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.17:41:54.84#ibcon#ireg 17 cls_cnt 0 2006.173.17:41:54.84#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.17:41:54.84#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.17:41:54.84#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.17:41:54.84#ibcon#enter wrdev, iclass 39, count 0 2006.173.17:41:54.84#ibcon#first serial, iclass 39, count 0 2006.173.17:41:54.84#ibcon#enter sib2, iclass 39, count 0 2006.173.17:41:54.84#ibcon#flushed, iclass 39, count 0 2006.173.17:41:54.84#ibcon#about to write, iclass 39, count 0 2006.173.17:41:54.84#ibcon#wrote, iclass 39, count 0 2006.173.17:41:54.84#ibcon#about to read 3, iclass 39, count 0 2006.173.17:41:54.86#ibcon#read 3, iclass 39, count 0 2006.173.17:41:54.86#ibcon#about to read 4, iclass 39, count 0 2006.173.17:41:54.86#ibcon#read 4, iclass 39, count 0 2006.173.17:41:54.86#ibcon#about to read 5, iclass 39, count 0 2006.173.17:41:54.86#ibcon#read 5, iclass 39, count 0 2006.173.17:41:54.86#ibcon#about to read 6, iclass 39, count 0 2006.173.17:41:54.86#ibcon#read 6, iclass 39, count 0 2006.173.17:41:54.86#ibcon#end of sib2, iclass 39, count 0 2006.173.17:41:54.86#ibcon#*mode == 0, iclass 39, count 0 2006.173.17:41:54.86#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.17:41:54.86#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.17:41:54.86#ibcon#*before write, iclass 39, count 0 2006.173.17:41:54.86#ibcon#enter sib2, iclass 39, count 0 2006.173.17:41:54.86#ibcon#flushed, iclass 39, count 0 2006.173.17:41:54.86#ibcon#about to write, iclass 39, count 0 2006.173.17:41:54.86#ibcon#wrote, iclass 39, count 0 2006.173.17:41:54.86#ibcon#about to read 3, iclass 39, count 0 2006.173.17:41:54.90#ibcon#read 3, iclass 39, count 0 2006.173.17:41:54.90#ibcon#about to read 4, iclass 39, count 0 2006.173.17:41:54.90#ibcon#read 4, iclass 39, count 0 2006.173.17:41:54.90#ibcon#about to read 5, iclass 39, count 0 2006.173.17:41:54.90#ibcon#read 5, iclass 39, count 0 2006.173.17:41:54.90#ibcon#about to read 6, iclass 39, count 0 2006.173.17:41:54.90#ibcon#read 6, iclass 39, count 0 2006.173.17:41:54.90#ibcon#end of sib2, iclass 39, count 0 2006.173.17:41:54.90#ibcon#*after write, iclass 39, count 0 2006.173.17:41:54.90#ibcon#*before return 0, iclass 39, count 0 2006.173.17:41:54.90#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.17:41:54.90#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.17:41:54.90#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.17:41:54.90#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.17:41:54.90$vck44/va=3,5 2006.173.17:41:54.90#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.17:41:54.90#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.17:41:54.90#ibcon#ireg 11 cls_cnt 2 2006.173.17:41:54.90#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.17:41:54.96#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.17:41:54.96#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.17:41:54.96#ibcon#enter wrdev, iclass 3, count 2 2006.173.17:41:54.96#ibcon#first serial, iclass 3, count 2 2006.173.17:41:54.96#ibcon#enter sib2, iclass 3, count 2 2006.173.17:41:54.96#ibcon#flushed, iclass 3, count 2 2006.173.17:41:54.96#ibcon#about to write, iclass 3, count 2 2006.173.17:41:54.96#ibcon#wrote, iclass 3, count 2 2006.173.17:41:54.96#ibcon#about to read 3, iclass 3, count 2 2006.173.17:41:54.98#ibcon#read 3, iclass 3, count 2 2006.173.17:41:54.98#ibcon#about to read 4, iclass 3, count 2 2006.173.17:41:54.98#ibcon#read 4, iclass 3, count 2 2006.173.17:41:54.98#ibcon#about to read 5, iclass 3, count 2 2006.173.17:41:54.98#ibcon#read 5, iclass 3, count 2 2006.173.17:41:54.98#ibcon#about to read 6, iclass 3, count 2 2006.173.17:41:54.98#ibcon#read 6, iclass 3, count 2 2006.173.17:41:54.98#ibcon#end of sib2, iclass 3, count 2 2006.173.17:41:54.98#ibcon#*mode == 0, iclass 3, count 2 2006.173.17:41:54.98#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.17:41:54.98#ibcon#[25=AT03-05\r\n] 2006.173.17:41:54.98#ibcon#*before write, iclass 3, count 2 2006.173.17:41:54.98#ibcon#enter sib2, iclass 3, count 2 2006.173.17:41:54.98#ibcon#flushed, iclass 3, count 2 2006.173.17:41:54.98#ibcon#about to write, iclass 3, count 2 2006.173.17:41:54.98#ibcon#wrote, iclass 3, count 2 2006.173.17:41:54.98#ibcon#about to read 3, iclass 3, count 2 2006.173.17:41:55.01#ibcon#read 3, iclass 3, count 2 2006.173.17:41:55.01#ibcon#about to read 4, iclass 3, count 2 2006.173.17:41:55.01#ibcon#read 4, iclass 3, count 2 2006.173.17:41:55.01#ibcon#about to read 5, iclass 3, count 2 2006.173.17:41:55.01#ibcon#read 5, iclass 3, count 2 2006.173.17:41:55.01#ibcon#about to read 6, iclass 3, count 2 2006.173.17:41:55.01#ibcon#read 6, iclass 3, count 2 2006.173.17:41:55.01#ibcon#end of sib2, iclass 3, count 2 2006.173.17:41:55.01#ibcon#*after write, iclass 3, count 2 2006.173.17:41:55.01#ibcon#*before return 0, iclass 3, count 2 2006.173.17:41:55.01#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.17:41:55.01#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.17:41:55.01#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.17:41:55.01#ibcon#ireg 7 cls_cnt 0 2006.173.17:41:55.01#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.17:41:55.13#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.17:41:55.13#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.17:41:55.13#ibcon#enter wrdev, iclass 3, count 0 2006.173.17:41:55.13#ibcon#first serial, iclass 3, count 0 2006.173.17:41:55.13#ibcon#enter sib2, iclass 3, count 0 2006.173.17:41:55.13#ibcon#flushed, iclass 3, count 0 2006.173.17:41:55.13#ibcon#about to write, iclass 3, count 0 2006.173.17:41:55.13#ibcon#wrote, iclass 3, count 0 2006.173.17:41:55.13#ibcon#about to read 3, iclass 3, count 0 2006.173.17:41:55.15#ibcon#read 3, iclass 3, count 0 2006.173.17:41:55.15#ibcon#about to read 4, iclass 3, count 0 2006.173.17:41:55.15#ibcon#read 4, iclass 3, count 0 2006.173.17:41:55.15#ibcon#about to read 5, iclass 3, count 0 2006.173.17:41:55.15#ibcon#read 5, iclass 3, count 0 2006.173.17:41:55.15#ibcon#about to read 6, iclass 3, count 0 2006.173.17:41:55.15#ibcon#read 6, iclass 3, count 0 2006.173.17:41:55.15#ibcon#end of sib2, iclass 3, count 0 2006.173.17:41:55.15#ibcon#*mode == 0, iclass 3, count 0 2006.173.17:41:55.15#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.17:41:55.15#ibcon#[25=USB\r\n] 2006.173.17:41:55.15#ibcon#*before write, iclass 3, count 0 2006.173.17:41:55.15#ibcon#enter sib2, iclass 3, count 0 2006.173.17:41:55.15#ibcon#flushed, iclass 3, count 0 2006.173.17:41:55.15#ibcon#about to write, iclass 3, count 0 2006.173.17:41:55.15#ibcon#wrote, iclass 3, count 0 2006.173.17:41:55.15#ibcon#about to read 3, iclass 3, count 0 2006.173.17:41:55.18#ibcon#read 3, iclass 3, count 0 2006.173.17:41:55.18#ibcon#about to read 4, iclass 3, count 0 2006.173.17:41:55.18#ibcon#read 4, iclass 3, count 0 2006.173.17:41:55.18#ibcon#about to read 5, iclass 3, count 0 2006.173.17:41:55.18#ibcon#read 5, iclass 3, count 0 2006.173.17:41:55.18#ibcon#about to read 6, iclass 3, count 0 2006.173.17:41:55.18#ibcon#read 6, iclass 3, count 0 2006.173.17:41:55.18#ibcon#end of sib2, iclass 3, count 0 2006.173.17:41:55.18#ibcon#*after write, iclass 3, count 0 2006.173.17:41:55.18#ibcon#*before return 0, iclass 3, count 0 2006.173.17:41:55.18#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.17:41:55.18#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.17:41:55.18#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.17:41:55.18#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.17:41:55.18$vck44/valo=4,624.99 2006.173.17:41:55.18#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.17:41:55.18#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.17:41:55.18#ibcon#ireg 17 cls_cnt 0 2006.173.17:41:55.18#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.17:41:55.18#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.17:41:55.18#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.17:41:55.18#ibcon#enter wrdev, iclass 5, count 0 2006.173.17:41:55.18#ibcon#first serial, iclass 5, count 0 2006.173.17:41:55.18#ibcon#enter sib2, iclass 5, count 0 2006.173.17:41:55.18#ibcon#flushed, iclass 5, count 0 2006.173.17:41:55.18#ibcon#about to write, iclass 5, count 0 2006.173.17:41:55.18#ibcon#wrote, iclass 5, count 0 2006.173.17:41:55.18#ibcon#about to read 3, iclass 5, count 0 2006.173.17:41:55.20#ibcon#read 3, iclass 5, count 0 2006.173.17:41:55.20#ibcon#about to read 4, iclass 5, count 0 2006.173.17:41:55.20#ibcon#read 4, iclass 5, count 0 2006.173.17:41:55.20#ibcon#about to read 5, iclass 5, count 0 2006.173.17:41:55.20#ibcon#read 5, iclass 5, count 0 2006.173.17:41:55.20#ibcon#about to read 6, iclass 5, count 0 2006.173.17:41:55.20#ibcon#read 6, iclass 5, count 0 2006.173.17:41:55.20#ibcon#end of sib2, iclass 5, count 0 2006.173.17:41:55.20#ibcon#*mode == 0, iclass 5, count 0 2006.173.17:41:55.20#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.17:41:55.20#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.17:41:55.20#ibcon#*before write, iclass 5, count 0 2006.173.17:41:55.20#ibcon#enter sib2, iclass 5, count 0 2006.173.17:41:55.20#ibcon#flushed, iclass 5, count 0 2006.173.17:41:55.20#ibcon#about to write, iclass 5, count 0 2006.173.17:41:55.20#ibcon#wrote, iclass 5, count 0 2006.173.17:41:55.20#ibcon#about to read 3, iclass 5, count 0 2006.173.17:41:55.24#ibcon#read 3, iclass 5, count 0 2006.173.17:41:55.24#ibcon#about to read 4, iclass 5, count 0 2006.173.17:41:55.24#ibcon#read 4, iclass 5, count 0 2006.173.17:41:55.24#ibcon#about to read 5, iclass 5, count 0 2006.173.17:41:55.24#ibcon#read 5, iclass 5, count 0 2006.173.17:41:55.24#ibcon#about to read 6, iclass 5, count 0 2006.173.17:41:55.24#ibcon#read 6, iclass 5, count 0 2006.173.17:41:55.24#ibcon#end of sib2, iclass 5, count 0 2006.173.17:41:55.24#ibcon#*after write, iclass 5, count 0 2006.173.17:41:55.24#ibcon#*before return 0, iclass 5, count 0 2006.173.17:41:55.24#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.17:41:55.24#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.17:41:55.24#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.17:41:55.24#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.17:41:55.24$vck44/va=4,6 2006.173.17:41:55.24#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.173.17:41:55.24#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.173.17:41:55.24#ibcon#ireg 11 cls_cnt 2 2006.173.17:41:55.24#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.17:41:55.30#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.17:41:55.30#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.17:41:55.30#ibcon#enter wrdev, iclass 7, count 2 2006.173.17:41:55.30#ibcon#first serial, iclass 7, count 2 2006.173.17:41:55.30#ibcon#enter sib2, iclass 7, count 2 2006.173.17:41:55.30#ibcon#flushed, iclass 7, count 2 2006.173.17:41:55.30#ibcon#about to write, iclass 7, count 2 2006.173.17:41:55.30#ibcon#wrote, iclass 7, count 2 2006.173.17:41:55.30#ibcon#about to read 3, iclass 7, count 2 2006.173.17:41:55.32#ibcon#read 3, iclass 7, count 2 2006.173.17:41:55.32#ibcon#about to read 4, iclass 7, count 2 2006.173.17:41:55.32#ibcon#read 4, iclass 7, count 2 2006.173.17:41:55.32#ibcon#about to read 5, iclass 7, count 2 2006.173.17:41:55.32#ibcon#read 5, iclass 7, count 2 2006.173.17:41:55.32#ibcon#about to read 6, iclass 7, count 2 2006.173.17:41:55.32#ibcon#read 6, iclass 7, count 2 2006.173.17:41:55.32#ibcon#end of sib2, iclass 7, count 2 2006.173.17:41:55.32#ibcon#*mode == 0, iclass 7, count 2 2006.173.17:41:55.32#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.173.17:41:55.32#ibcon#[25=AT04-06\r\n] 2006.173.17:41:55.32#ibcon#*before write, iclass 7, count 2 2006.173.17:41:55.32#ibcon#enter sib2, iclass 7, count 2 2006.173.17:41:55.32#ibcon#flushed, iclass 7, count 2 2006.173.17:41:55.32#ibcon#about to write, iclass 7, count 2 2006.173.17:41:55.32#ibcon#wrote, iclass 7, count 2 2006.173.17:41:55.32#ibcon#about to read 3, iclass 7, count 2 2006.173.17:41:55.35#ibcon#read 3, iclass 7, count 2 2006.173.17:41:55.35#ibcon#about to read 4, iclass 7, count 2 2006.173.17:41:55.35#ibcon#read 4, iclass 7, count 2 2006.173.17:41:55.35#ibcon#about to read 5, iclass 7, count 2 2006.173.17:41:55.35#ibcon#read 5, iclass 7, count 2 2006.173.17:41:55.35#ibcon#about to read 6, iclass 7, count 2 2006.173.17:41:55.35#ibcon#read 6, iclass 7, count 2 2006.173.17:41:55.35#ibcon#end of sib2, iclass 7, count 2 2006.173.17:41:55.35#ibcon#*after write, iclass 7, count 2 2006.173.17:41:55.35#ibcon#*before return 0, iclass 7, count 2 2006.173.17:41:55.35#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.17:41:55.35#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.173.17:41:55.35#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.173.17:41:55.35#ibcon#ireg 7 cls_cnt 0 2006.173.17:41:55.35#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.17:41:55.47#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.17:41:55.47#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.17:41:55.47#ibcon#enter wrdev, iclass 7, count 0 2006.173.17:41:55.47#ibcon#first serial, iclass 7, count 0 2006.173.17:41:55.47#ibcon#enter sib2, iclass 7, count 0 2006.173.17:41:55.47#ibcon#flushed, iclass 7, count 0 2006.173.17:41:55.47#ibcon#about to write, iclass 7, count 0 2006.173.17:41:55.47#ibcon#wrote, iclass 7, count 0 2006.173.17:41:55.47#ibcon#about to read 3, iclass 7, count 0 2006.173.17:41:55.49#ibcon#read 3, iclass 7, count 0 2006.173.17:41:55.49#ibcon#about to read 4, iclass 7, count 0 2006.173.17:41:55.49#ibcon#read 4, iclass 7, count 0 2006.173.17:41:55.49#ibcon#about to read 5, iclass 7, count 0 2006.173.17:41:55.49#ibcon#read 5, iclass 7, count 0 2006.173.17:41:55.49#ibcon#about to read 6, iclass 7, count 0 2006.173.17:41:55.49#ibcon#read 6, iclass 7, count 0 2006.173.17:41:55.49#ibcon#end of sib2, iclass 7, count 0 2006.173.17:41:55.49#ibcon#*mode == 0, iclass 7, count 0 2006.173.17:41:55.49#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.17:41:55.49#ibcon#[25=USB\r\n] 2006.173.17:41:55.49#ibcon#*before write, iclass 7, count 0 2006.173.17:41:55.49#ibcon#enter sib2, iclass 7, count 0 2006.173.17:41:55.49#ibcon#flushed, iclass 7, count 0 2006.173.17:41:55.49#ibcon#about to write, iclass 7, count 0 2006.173.17:41:55.49#ibcon#wrote, iclass 7, count 0 2006.173.17:41:55.49#ibcon#about to read 3, iclass 7, count 0 2006.173.17:41:55.52#ibcon#read 3, iclass 7, count 0 2006.173.17:41:55.52#ibcon#about to read 4, iclass 7, count 0 2006.173.17:41:55.52#ibcon#read 4, iclass 7, count 0 2006.173.17:41:55.52#ibcon#about to read 5, iclass 7, count 0 2006.173.17:41:55.52#ibcon#read 5, iclass 7, count 0 2006.173.17:41:55.52#ibcon#about to read 6, iclass 7, count 0 2006.173.17:41:55.52#ibcon#read 6, iclass 7, count 0 2006.173.17:41:55.52#ibcon#end of sib2, iclass 7, count 0 2006.173.17:41:55.52#ibcon#*after write, iclass 7, count 0 2006.173.17:41:55.52#ibcon#*before return 0, iclass 7, count 0 2006.173.17:41:55.52#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.17:41:55.52#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.173.17:41:55.52#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.17:41:55.52#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.17:41:55.52$vck44/valo=5,734.99 2006.173.17:41:55.52#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.17:41:55.52#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.17:41:55.52#ibcon#ireg 17 cls_cnt 0 2006.173.17:41:55.52#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.17:41:55.52#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.17:41:55.52#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.17:41:55.52#ibcon#enter wrdev, iclass 11, count 0 2006.173.17:41:55.52#ibcon#first serial, iclass 11, count 0 2006.173.17:41:55.52#ibcon#enter sib2, iclass 11, count 0 2006.173.17:41:55.52#ibcon#flushed, iclass 11, count 0 2006.173.17:41:55.52#ibcon#about to write, iclass 11, count 0 2006.173.17:41:55.52#ibcon#wrote, iclass 11, count 0 2006.173.17:41:55.52#ibcon#about to read 3, iclass 11, count 0 2006.173.17:41:55.54#ibcon#read 3, iclass 11, count 0 2006.173.17:41:55.54#ibcon#about to read 4, iclass 11, count 0 2006.173.17:41:55.54#ibcon#read 4, iclass 11, count 0 2006.173.17:41:55.54#ibcon#about to read 5, iclass 11, count 0 2006.173.17:41:55.54#ibcon#read 5, iclass 11, count 0 2006.173.17:41:55.54#ibcon#about to read 6, iclass 11, count 0 2006.173.17:41:55.54#ibcon#read 6, iclass 11, count 0 2006.173.17:41:55.54#ibcon#end of sib2, iclass 11, count 0 2006.173.17:41:55.54#ibcon#*mode == 0, iclass 11, count 0 2006.173.17:41:55.54#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.17:41:55.54#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.17:41:55.54#ibcon#*before write, iclass 11, count 0 2006.173.17:41:55.54#ibcon#enter sib2, iclass 11, count 0 2006.173.17:41:55.54#ibcon#flushed, iclass 11, count 0 2006.173.17:41:55.54#ibcon#about to write, iclass 11, count 0 2006.173.17:41:55.54#ibcon#wrote, iclass 11, count 0 2006.173.17:41:55.54#ibcon#about to read 3, iclass 11, count 0 2006.173.17:41:55.58#ibcon#read 3, iclass 11, count 0 2006.173.17:41:55.58#ibcon#about to read 4, iclass 11, count 0 2006.173.17:41:55.58#ibcon#read 4, iclass 11, count 0 2006.173.17:41:55.58#ibcon#about to read 5, iclass 11, count 0 2006.173.17:41:55.58#ibcon#read 5, iclass 11, count 0 2006.173.17:41:55.58#ibcon#about to read 6, iclass 11, count 0 2006.173.17:41:55.58#ibcon#read 6, iclass 11, count 0 2006.173.17:41:55.58#ibcon#end of sib2, iclass 11, count 0 2006.173.17:41:55.58#ibcon#*after write, iclass 11, count 0 2006.173.17:41:55.58#ibcon#*before return 0, iclass 11, count 0 2006.173.17:41:55.58#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.17:41:55.58#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.17:41:55.58#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.17:41:55.58#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.17:41:55.58$vck44/va=5,4 2006.173.17:41:55.58#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.173.17:41:55.58#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.173.17:41:55.58#ibcon#ireg 11 cls_cnt 2 2006.173.17:41:55.58#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.17:41:55.64#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.17:41:55.64#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.17:41:55.64#ibcon#enter wrdev, iclass 13, count 2 2006.173.17:41:55.64#ibcon#first serial, iclass 13, count 2 2006.173.17:41:55.64#ibcon#enter sib2, iclass 13, count 2 2006.173.17:41:55.64#ibcon#flushed, iclass 13, count 2 2006.173.17:41:55.64#ibcon#about to write, iclass 13, count 2 2006.173.17:41:55.64#ibcon#wrote, iclass 13, count 2 2006.173.17:41:55.64#ibcon#about to read 3, iclass 13, count 2 2006.173.17:41:55.66#ibcon#read 3, iclass 13, count 2 2006.173.17:41:55.66#ibcon#about to read 4, iclass 13, count 2 2006.173.17:41:55.66#ibcon#read 4, iclass 13, count 2 2006.173.17:41:55.66#ibcon#about to read 5, iclass 13, count 2 2006.173.17:41:55.66#ibcon#read 5, iclass 13, count 2 2006.173.17:41:55.66#ibcon#about to read 6, iclass 13, count 2 2006.173.17:41:55.66#ibcon#read 6, iclass 13, count 2 2006.173.17:41:55.66#ibcon#end of sib2, iclass 13, count 2 2006.173.17:41:55.66#ibcon#*mode == 0, iclass 13, count 2 2006.173.17:41:55.66#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.173.17:41:55.66#ibcon#[25=AT05-04\r\n] 2006.173.17:41:55.66#ibcon#*before write, iclass 13, count 2 2006.173.17:41:55.66#ibcon#enter sib2, iclass 13, count 2 2006.173.17:41:55.66#ibcon#flushed, iclass 13, count 2 2006.173.17:41:55.66#ibcon#about to write, iclass 13, count 2 2006.173.17:41:55.66#ibcon#wrote, iclass 13, count 2 2006.173.17:41:55.66#ibcon#about to read 3, iclass 13, count 2 2006.173.17:41:55.69#ibcon#read 3, iclass 13, count 2 2006.173.17:41:55.69#ibcon#about to read 4, iclass 13, count 2 2006.173.17:41:55.69#ibcon#read 4, iclass 13, count 2 2006.173.17:41:55.69#ibcon#about to read 5, iclass 13, count 2 2006.173.17:41:55.69#ibcon#read 5, iclass 13, count 2 2006.173.17:41:55.69#ibcon#about to read 6, iclass 13, count 2 2006.173.17:41:55.69#ibcon#read 6, iclass 13, count 2 2006.173.17:41:55.69#ibcon#end of sib2, iclass 13, count 2 2006.173.17:41:55.69#ibcon#*after write, iclass 13, count 2 2006.173.17:41:55.69#ibcon#*before return 0, iclass 13, count 2 2006.173.17:41:55.69#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.17:41:55.69#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.173.17:41:55.69#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.173.17:41:55.69#ibcon#ireg 7 cls_cnt 0 2006.173.17:41:55.69#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.17:41:55.81#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.17:41:55.81#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.17:41:55.81#ibcon#enter wrdev, iclass 13, count 0 2006.173.17:41:55.81#ibcon#first serial, iclass 13, count 0 2006.173.17:41:55.81#ibcon#enter sib2, iclass 13, count 0 2006.173.17:41:55.81#ibcon#flushed, iclass 13, count 0 2006.173.17:41:55.81#ibcon#about to write, iclass 13, count 0 2006.173.17:41:55.81#ibcon#wrote, iclass 13, count 0 2006.173.17:41:55.81#ibcon#about to read 3, iclass 13, count 0 2006.173.17:41:55.83#ibcon#read 3, iclass 13, count 0 2006.173.17:41:55.83#ibcon#about to read 4, iclass 13, count 0 2006.173.17:41:55.83#ibcon#read 4, iclass 13, count 0 2006.173.17:41:55.83#ibcon#about to read 5, iclass 13, count 0 2006.173.17:41:55.83#ibcon#read 5, iclass 13, count 0 2006.173.17:41:55.83#ibcon#about to read 6, iclass 13, count 0 2006.173.17:41:55.83#ibcon#read 6, iclass 13, count 0 2006.173.17:41:55.83#ibcon#end of sib2, iclass 13, count 0 2006.173.17:41:55.83#ibcon#*mode == 0, iclass 13, count 0 2006.173.17:41:55.83#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.17:41:55.83#ibcon#[25=USB\r\n] 2006.173.17:41:55.83#ibcon#*before write, iclass 13, count 0 2006.173.17:41:55.83#ibcon#enter sib2, iclass 13, count 0 2006.173.17:41:55.83#ibcon#flushed, iclass 13, count 0 2006.173.17:41:55.83#ibcon#about to write, iclass 13, count 0 2006.173.17:41:55.83#ibcon#wrote, iclass 13, count 0 2006.173.17:41:55.83#ibcon#about to read 3, iclass 13, count 0 2006.173.17:41:55.86#ibcon#read 3, iclass 13, count 0 2006.173.17:41:55.86#ibcon#about to read 4, iclass 13, count 0 2006.173.17:41:55.86#ibcon#read 4, iclass 13, count 0 2006.173.17:41:55.86#ibcon#about to read 5, iclass 13, count 0 2006.173.17:41:55.86#ibcon#read 5, iclass 13, count 0 2006.173.17:41:55.86#ibcon#about to read 6, iclass 13, count 0 2006.173.17:41:55.86#ibcon#read 6, iclass 13, count 0 2006.173.17:41:55.86#ibcon#end of sib2, iclass 13, count 0 2006.173.17:41:55.86#ibcon#*after write, iclass 13, count 0 2006.173.17:41:55.86#ibcon#*before return 0, iclass 13, count 0 2006.173.17:41:55.86#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.17:41:55.86#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.173.17:41:55.86#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.17:41:55.86#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.17:41:55.86$vck44/valo=6,814.99 2006.173.17:41:55.86#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.17:41:55.86#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.17:41:55.86#ibcon#ireg 17 cls_cnt 0 2006.173.17:41:55.86#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.17:41:55.86#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.17:41:55.86#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.17:41:55.86#ibcon#enter wrdev, iclass 15, count 0 2006.173.17:41:55.86#ibcon#first serial, iclass 15, count 0 2006.173.17:41:55.86#ibcon#enter sib2, iclass 15, count 0 2006.173.17:41:55.86#ibcon#flushed, iclass 15, count 0 2006.173.17:41:55.86#ibcon#about to write, iclass 15, count 0 2006.173.17:41:55.86#ibcon#wrote, iclass 15, count 0 2006.173.17:41:55.86#ibcon#about to read 3, iclass 15, count 0 2006.173.17:41:55.88#ibcon#read 3, iclass 15, count 0 2006.173.17:41:55.88#ibcon#about to read 4, iclass 15, count 0 2006.173.17:41:55.88#ibcon#read 4, iclass 15, count 0 2006.173.17:41:55.88#ibcon#about to read 5, iclass 15, count 0 2006.173.17:41:55.88#ibcon#read 5, iclass 15, count 0 2006.173.17:41:55.88#ibcon#about to read 6, iclass 15, count 0 2006.173.17:41:55.88#ibcon#read 6, iclass 15, count 0 2006.173.17:41:55.88#ibcon#end of sib2, iclass 15, count 0 2006.173.17:41:55.88#ibcon#*mode == 0, iclass 15, count 0 2006.173.17:41:55.88#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.17:41:55.88#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.17:41:55.88#ibcon#*before write, iclass 15, count 0 2006.173.17:41:55.88#ibcon#enter sib2, iclass 15, count 0 2006.173.17:41:55.88#ibcon#flushed, iclass 15, count 0 2006.173.17:41:55.88#ibcon#about to write, iclass 15, count 0 2006.173.17:41:55.88#ibcon#wrote, iclass 15, count 0 2006.173.17:41:55.88#ibcon#about to read 3, iclass 15, count 0 2006.173.17:41:55.92#ibcon#read 3, iclass 15, count 0 2006.173.17:41:55.92#ibcon#about to read 4, iclass 15, count 0 2006.173.17:41:55.92#ibcon#read 4, iclass 15, count 0 2006.173.17:41:55.92#ibcon#about to read 5, iclass 15, count 0 2006.173.17:41:55.92#ibcon#read 5, iclass 15, count 0 2006.173.17:41:55.92#ibcon#about to read 6, iclass 15, count 0 2006.173.17:41:55.92#ibcon#read 6, iclass 15, count 0 2006.173.17:41:55.92#ibcon#end of sib2, iclass 15, count 0 2006.173.17:41:55.92#ibcon#*after write, iclass 15, count 0 2006.173.17:41:55.92#ibcon#*before return 0, iclass 15, count 0 2006.173.17:41:55.92#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.17:41:55.92#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.17:41:55.92#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.17:41:55.92#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.17:41:55.92$vck44/va=6,3 2006.173.17:41:55.92#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.17:41:55.92#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.17:41:55.92#ibcon#ireg 11 cls_cnt 2 2006.173.17:41:55.92#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.17:41:55.98#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.17:41:55.98#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.17:41:55.98#ibcon#enter wrdev, iclass 17, count 2 2006.173.17:41:55.98#ibcon#first serial, iclass 17, count 2 2006.173.17:41:55.98#ibcon#enter sib2, iclass 17, count 2 2006.173.17:41:55.98#ibcon#flushed, iclass 17, count 2 2006.173.17:41:55.98#ibcon#about to write, iclass 17, count 2 2006.173.17:41:55.98#ibcon#wrote, iclass 17, count 2 2006.173.17:41:55.98#ibcon#about to read 3, iclass 17, count 2 2006.173.17:41:56.00#ibcon#read 3, iclass 17, count 2 2006.173.17:41:56.00#ibcon#about to read 4, iclass 17, count 2 2006.173.17:41:56.00#ibcon#read 4, iclass 17, count 2 2006.173.17:41:56.00#ibcon#about to read 5, iclass 17, count 2 2006.173.17:41:56.00#ibcon#read 5, iclass 17, count 2 2006.173.17:41:56.00#ibcon#about to read 6, iclass 17, count 2 2006.173.17:41:56.00#ibcon#read 6, iclass 17, count 2 2006.173.17:41:56.00#ibcon#end of sib2, iclass 17, count 2 2006.173.17:41:56.00#ibcon#*mode == 0, iclass 17, count 2 2006.173.17:41:56.00#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.17:41:56.00#ibcon#[25=AT06-03\r\n] 2006.173.17:41:56.00#ibcon#*before write, iclass 17, count 2 2006.173.17:41:56.00#ibcon#enter sib2, iclass 17, count 2 2006.173.17:41:56.00#ibcon#flushed, iclass 17, count 2 2006.173.17:41:56.00#ibcon#about to write, iclass 17, count 2 2006.173.17:41:56.00#ibcon#wrote, iclass 17, count 2 2006.173.17:41:56.00#ibcon#about to read 3, iclass 17, count 2 2006.173.17:41:56.03#ibcon#read 3, iclass 17, count 2 2006.173.17:41:56.03#ibcon#about to read 4, iclass 17, count 2 2006.173.17:41:56.03#ibcon#read 4, iclass 17, count 2 2006.173.17:41:56.03#ibcon#about to read 5, iclass 17, count 2 2006.173.17:41:56.03#ibcon#read 5, iclass 17, count 2 2006.173.17:41:56.03#ibcon#about to read 6, iclass 17, count 2 2006.173.17:41:56.03#ibcon#read 6, iclass 17, count 2 2006.173.17:41:56.03#ibcon#end of sib2, iclass 17, count 2 2006.173.17:41:56.03#ibcon#*after write, iclass 17, count 2 2006.173.17:41:56.03#ibcon#*before return 0, iclass 17, count 2 2006.173.17:41:56.03#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.17:41:56.03#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.17:41:56.03#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.17:41:56.03#ibcon#ireg 7 cls_cnt 0 2006.173.17:41:56.03#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.17:41:56.15#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.17:41:56.15#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.17:41:56.15#ibcon#enter wrdev, iclass 17, count 0 2006.173.17:41:56.15#ibcon#first serial, iclass 17, count 0 2006.173.17:41:56.15#ibcon#enter sib2, iclass 17, count 0 2006.173.17:41:56.15#ibcon#flushed, iclass 17, count 0 2006.173.17:41:56.15#ibcon#about to write, iclass 17, count 0 2006.173.17:41:56.15#ibcon#wrote, iclass 17, count 0 2006.173.17:41:56.15#ibcon#about to read 3, iclass 17, count 0 2006.173.17:41:56.17#ibcon#read 3, iclass 17, count 0 2006.173.17:41:56.17#ibcon#about to read 4, iclass 17, count 0 2006.173.17:41:56.17#ibcon#read 4, iclass 17, count 0 2006.173.17:41:56.17#ibcon#about to read 5, iclass 17, count 0 2006.173.17:41:56.17#ibcon#read 5, iclass 17, count 0 2006.173.17:41:56.17#ibcon#about to read 6, iclass 17, count 0 2006.173.17:41:56.17#ibcon#read 6, iclass 17, count 0 2006.173.17:41:56.17#ibcon#end of sib2, iclass 17, count 0 2006.173.17:41:56.17#ibcon#*mode == 0, iclass 17, count 0 2006.173.17:41:56.17#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.17:41:56.17#ibcon#[25=USB\r\n] 2006.173.17:41:56.17#ibcon#*before write, iclass 17, count 0 2006.173.17:41:56.17#ibcon#enter sib2, iclass 17, count 0 2006.173.17:41:56.17#ibcon#flushed, iclass 17, count 0 2006.173.17:41:56.17#ibcon#about to write, iclass 17, count 0 2006.173.17:41:56.17#ibcon#wrote, iclass 17, count 0 2006.173.17:41:56.17#ibcon#about to read 3, iclass 17, count 0 2006.173.17:41:56.20#ibcon#read 3, iclass 17, count 0 2006.173.17:41:56.20#ibcon#about to read 4, iclass 17, count 0 2006.173.17:41:56.20#ibcon#read 4, iclass 17, count 0 2006.173.17:41:56.20#ibcon#about to read 5, iclass 17, count 0 2006.173.17:41:56.20#ibcon#read 5, iclass 17, count 0 2006.173.17:41:56.20#ibcon#about to read 6, iclass 17, count 0 2006.173.17:41:56.20#ibcon#read 6, iclass 17, count 0 2006.173.17:41:56.20#ibcon#end of sib2, iclass 17, count 0 2006.173.17:41:56.20#ibcon#*after write, iclass 17, count 0 2006.173.17:41:56.20#ibcon#*before return 0, iclass 17, count 0 2006.173.17:41:56.20#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.17:41:56.20#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.17:41:56.20#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.17:41:56.20#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.17:41:56.20$vck44/valo=7,864.99 2006.173.17:41:56.20#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.17:41:56.20#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.17:41:56.20#ibcon#ireg 17 cls_cnt 0 2006.173.17:41:56.20#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.17:41:56.20#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.17:41:56.20#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.17:41:56.20#ibcon#enter wrdev, iclass 19, count 0 2006.173.17:41:56.20#ibcon#first serial, iclass 19, count 0 2006.173.17:41:56.20#ibcon#enter sib2, iclass 19, count 0 2006.173.17:41:56.20#ibcon#flushed, iclass 19, count 0 2006.173.17:41:56.20#ibcon#about to write, iclass 19, count 0 2006.173.17:41:56.20#ibcon#wrote, iclass 19, count 0 2006.173.17:41:56.20#ibcon#about to read 3, iclass 19, count 0 2006.173.17:41:56.22#ibcon#read 3, iclass 19, count 0 2006.173.17:41:56.22#ibcon#about to read 4, iclass 19, count 0 2006.173.17:41:56.22#ibcon#read 4, iclass 19, count 0 2006.173.17:41:56.22#ibcon#about to read 5, iclass 19, count 0 2006.173.17:41:56.22#ibcon#read 5, iclass 19, count 0 2006.173.17:41:56.22#ibcon#about to read 6, iclass 19, count 0 2006.173.17:41:56.22#ibcon#read 6, iclass 19, count 0 2006.173.17:41:56.22#ibcon#end of sib2, iclass 19, count 0 2006.173.17:41:56.22#ibcon#*mode == 0, iclass 19, count 0 2006.173.17:41:56.22#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.17:41:56.22#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.17:41:56.22#ibcon#*before write, iclass 19, count 0 2006.173.17:41:56.22#ibcon#enter sib2, iclass 19, count 0 2006.173.17:41:56.22#ibcon#flushed, iclass 19, count 0 2006.173.17:41:56.22#ibcon#about to write, iclass 19, count 0 2006.173.17:41:56.22#ibcon#wrote, iclass 19, count 0 2006.173.17:41:56.22#ibcon#about to read 3, iclass 19, count 0 2006.173.17:41:56.26#ibcon#read 3, iclass 19, count 0 2006.173.17:41:56.26#ibcon#about to read 4, iclass 19, count 0 2006.173.17:41:56.26#ibcon#read 4, iclass 19, count 0 2006.173.17:41:56.26#ibcon#about to read 5, iclass 19, count 0 2006.173.17:41:56.26#ibcon#read 5, iclass 19, count 0 2006.173.17:41:56.26#ibcon#about to read 6, iclass 19, count 0 2006.173.17:41:56.26#ibcon#read 6, iclass 19, count 0 2006.173.17:41:56.26#ibcon#end of sib2, iclass 19, count 0 2006.173.17:41:56.26#ibcon#*after write, iclass 19, count 0 2006.173.17:41:56.26#ibcon#*before return 0, iclass 19, count 0 2006.173.17:41:56.26#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.17:41:56.26#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.17:41:56.26#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.17:41:56.26#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.17:41:56.26$vck44/va=7,4 2006.173.17:41:56.26#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.17:41:56.26#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.17:41:56.26#ibcon#ireg 11 cls_cnt 2 2006.173.17:41:56.26#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.17:41:56.32#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.17:41:56.32#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.17:41:56.32#ibcon#enter wrdev, iclass 21, count 2 2006.173.17:41:56.32#ibcon#first serial, iclass 21, count 2 2006.173.17:41:56.32#ibcon#enter sib2, iclass 21, count 2 2006.173.17:41:56.32#ibcon#flushed, iclass 21, count 2 2006.173.17:41:56.32#ibcon#about to write, iclass 21, count 2 2006.173.17:41:56.32#ibcon#wrote, iclass 21, count 2 2006.173.17:41:56.32#ibcon#about to read 3, iclass 21, count 2 2006.173.17:41:56.34#ibcon#read 3, iclass 21, count 2 2006.173.17:41:56.34#ibcon#about to read 4, iclass 21, count 2 2006.173.17:41:56.34#ibcon#read 4, iclass 21, count 2 2006.173.17:41:56.34#ibcon#about to read 5, iclass 21, count 2 2006.173.17:41:56.34#ibcon#read 5, iclass 21, count 2 2006.173.17:41:56.34#ibcon#about to read 6, iclass 21, count 2 2006.173.17:41:56.34#ibcon#read 6, iclass 21, count 2 2006.173.17:41:56.34#ibcon#end of sib2, iclass 21, count 2 2006.173.17:41:56.34#ibcon#*mode == 0, iclass 21, count 2 2006.173.17:41:56.34#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.17:41:56.34#ibcon#[25=AT07-04\r\n] 2006.173.17:41:56.34#ibcon#*before write, iclass 21, count 2 2006.173.17:41:56.34#ibcon#enter sib2, iclass 21, count 2 2006.173.17:41:56.34#ibcon#flushed, iclass 21, count 2 2006.173.17:41:56.34#ibcon#about to write, iclass 21, count 2 2006.173.17:41:56.34#ibcon#wrote, iclass 21, count 2 2006.173.17:41:56.34#ibcon#about to read 3, iclass 21, count 2 2006.173.17:41:56.37#ibcon#read 3, iclass 21, count 2 2006.173.17:41:56.37#ibcon#about to read 4, iclass 21, count 2 2006.173.17:41:56.37#ibcon#read 4, iclass 21, count 2 2006.173.17:41:56.37#ibcon#about to read 5, iclass 21, count 2 2006.173.17:41:56.37#ibcon#read 5, iclass 21, count 2 2006.173.17:41:56.37#ibcon#about to read 6, iclass 21, count 2 2006.173.17:41:56.37#ibcon#read 6, iclass 21, count 2 2006.173.17:41:56.37#ibcon#end of sib2, iclass 21, count 2 2006.173.17:41:56.37#ibcon#*after write, iclass 21, count 2 2006.173.17:41:56.37#ibcon#*before return 0, iclass 21, count 2 2006.173.17:41:56.37#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.17:41:56.37#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.17:41:56.37#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.17:41:56.37#ibcon#ireg 7 cls_cnt 0 2006.173.17:41:56.37#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.17:41:56.49#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.17:41:56.49#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.17:41:56.49#ibcon#enter wrdev, iclass 21, count 0 2006.173.17:41:56.49#ibcon#first serial, iclass 21, count 0 2006.173.17:41:56.49#ibcon#enter sib2, iclass 21, count 0 2006.173.17:41:56.49#ibcon#flushed, iclass 21, count 0 2006.173.17:41:56.49#ibcon#about to write, iclass 21, count 0 2006.173.17:41:56.49#ibcon#wrote, iclass 21, count 0 2006.173.17:41:56.49#ibcon#about to read 3, iclass 21, count 0 2006.173.17:41:56.51#ibcon#read 3, iclass 21, count 0 2006.173.17:41:56.51#ibcon#about to read 4, iclass 21, count 0 2006.173.17:41:56.51#ibcon#read 4, iclass 21, count 0 2006.173.17:41:56.51#ibcon#about to read 5, iclass 21, count 0 2006.173.17:41:56.51#ibcon#read 5, iclass 21, count 0 2006.173.17:41:56.51#ibcon#about to read 6, iclass 21, count 0 2006.173.17:41:56.51#ibcon#read 6, iclass 21, count 0 2006.173.17:41:56.51#ibcon#end of sib2, iclass 21, count 0 2006.173.17:41:56.51#ibcon#*mode == 0, iclass 21, count 0 2006.173.17:41:56.51#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.17:41:56.51#ibcon#[25=USB\r\n] 2006.173.17:41:56.51#ibcon#*before write, iclass 21, count 0 2006.173.17:41:56.51#ibcon#enter sib2, iclass 21, count 0 2006.173.17:41:56.51#ibcon#flushed, iclass 21, count 0 2006.173.17:41:56.51#ibcon#about to write, iclass 21, count 0 2006.173.17:41:56.51#ibcon#wrote, iclass 21, count 0 2006.173.17:41:56.51#ibcon#about to read 3, iclass 21, count 0 2006.173.17:41:56.54#ibcon#read 3, iclass 21, count 0 2006.173.17:41:56.54#ibcon#about to read 4, iclass 21, count 0 2006.173.17:41:56.54#ibcon#read 4, iclass 21, count 0 2006.173.17:41:56.54#ibcon#about to read 5, iclass 21, count 0 2006.173.17:41:56.54#ibcon#read 5, iclass 21, count 0 2006.173.17:41:56.54#ibcon#about to read 6, iclass 21, count 0 2006.173.17:41:56.54#ibcon#read 6, iclass 21, count 0 2006.173.17:41:56.54#ibcon#end of sib2, iclass 21, count 0 2006.173.17:41:56.54#ibcon#*after write, iclass 21, count 0 2006.173.17:41:56.54#ibcon#*before return 0, iclass 21, count 0 2006.173.17:41:56.54#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.17:41:56.54#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.17:41:56.54#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.17:41:56.54#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.17:41:56.54$vck44/valo=8,884.99 2006.173.17:41:56.54#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.17:41:56.54#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.17:41:56.54#ibcon#ireg 17 cls_cnt 0 2006.173.17:41:56.54#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.17:41:56.54#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.17:41:56.54#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.17:41:56.54#ibcon#enter wrdev, iclass 23, count 0 2006.173.17:41:56.54#ibcon#first serial, iclass 23, count 0 2006.173.17:41:56.54#ibcon#enter sib2, iclass 23, count 0 2006.173.17:41:56.54#ibcon#flushed, iclass 23, count 0 2006.173.17:41:56.54#ibcon#about to write, iclass 23, count 0 2006.173.17:41:56.54#ibcon#wrote, iclass 23, count 0 2006.173.17:41:56.54#ibcon#about to read 3, iclass 23, count 0 2006.173.17:41:56.56#ibcon#read 3, iclass 23, count 0 2006.173.17:41:56.56#ibcon#about to read 4, iclass 23, count 0 2006.173.17:41:56.56#ibcon#read 4, iclass 23, count 0 2006.173.17:41:56.56#ibcon#about to read 5, iclass 23, count 0 2006.173.17:41:56.56#ibcon#read 5, iclass 23, count 0 2006.173.17:41:56.56#ibcon#about to read 6, iclass 23, count 0 2006.173.17:41:56.56#ibcon#read 6, iclass 23, count 0 2006.173.17:41:56.56#ibcon#end of sib2, iclass 23, count 0 2006.173.17:41:56.56#ibcon#*mode == 0, iclass 23, count 0 2006.173.17:41:56.56#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.17:41:56.56#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.17:41:56.56#ibcon#*before write, iclass 23, count 0 2006.173.17:41:56.56#ibcon#enter sib2, iclass 23, count 0 2006.173.17:41:56.56#ibcon#flushed, iclass 23, count 0 2006.173.17:41:56.56#ibcon#about to write, iclass 23, count 0 2006.173.17:41:56.56#ibcon#wrote, iclass 23, count 0 2006.173.17:41:56.56#ibcon#about to read 3, iclass 23, count 0 2006.173.17:41:56.60#ibcon#read 3, iclass 23, count 0 2006.173.17:41:56.60#ibcon#about to read 4, iclass 23, count 0 2006.173.17:41:56.60#ibcon#read 4, iclass 23, count 0 2006.173.17:41:56.60#ibcon#about to read 5, iclass 23, count 0 2006.173.17:41:56.60#ibcon#read 5, iclass 23, count 0 2006.173.17:41:56.60#ibcon#about to read 6, iclass 23, count 0 2006.173.17:41:56.60#ibcon#read 6, iclass 23, count 0 2006.173.17:41:56.60#ibcon#end of sib2, iclass 23, count 0 2006.173.17:41:56.60#ibcon#*after write, iclass 23, count 0 2006.173.17:41:56.60#ibcon#*before return 0, iclass 23, count 0 2006.173.17:41:56.60#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.17:41:56.60#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.17:41:56.60#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.17:41:56.60#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.17:41:56.60$vck44/va=8,4 2006.173.17:41:56.60#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.17:41:56.60#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.17:41:56.60#ibcon#ireg 11 cls_cnt 2 2006.173.17:41:56.60#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.17:41:56.66#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.17:41:56.66#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.17:41:56.66#ibcon#enter wrdev, iclass 25, count 2 2006.173.17:41:56.66#ibcon#first serial, iclass 25, count 2 2006.173.17:41:56.66#ibcon#enter sib2, iclass 25, count 2 2006.173.17:41:56.66#ibcon#flushed, iclass 25, count 2 2006.173.17:41:56.66#ibcon#about to write, iclass 25, count 2 2006.173.17:41:56.66#ibcon#wrote, iclass 25, count 2 2006.173.17:41:56.66#ibcon#about to read 3, iclass 25, count 2 2006.173.17:41:56.68#ibcon#read 3, iclass 25, count 2 2006.173.17:41:56.68#ibcon#about to read 4, iclass 25, count 2 2006.173.17:41:56.68#ibcon#read 4, iclass 25, count 2 2006.173.17:41:56.68#ibcon#about to read 5, iclass 25, count 2 2006.173.17:41:56.68#ibcon#read 5, iclass 25, count 2 2006.173.17:41:56.68#ibcon#about to read 6, iclass 25, count 2 2006.173.17:41:56.68#ibcon#read 6, iclass 25, count 2 2006.173.17:41:56.68#ibcon#end of sib2, iclass 25, count 2 2006.173.17:41:56.68#ibcon#*mode == 0, iclass 25, count 2 2006.173.17:41:56.68#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.17:41:56.68#ibcon#[25=AT08-04\r\n] 2006.173.17:41:56.68#ibcon#*before write, iclass 25, count 2 2006.173.17:41:56.68#ibcon#enter sib2, iclass 25, count 2 2006.173.17:41:56.68#ibcon#flushed, iclass 25, count 2 2006.173.17:41:56.68#ibcon#about to write, iclass 25, count 2 2006.173.17:41:56.68#ibcon#wrote, iclass 25, count 2 2006.173.17:41:56.68#ibcon#about to read 3, iclass 25, count 2 2006.173.17:41:56.71#ibcon#read 3, iclass 25, count 2 2006.173.17:41:56.71#ibcon#about to read 4, iclass 25, count 2 2006.173.17:41:56.71#ibcon#read 4, iclass 25, count 2 2006.173.17:41:56.71#ibcon#about to read 5, iclass 25, count 2 2006.173.17:41:56.71#ibcon#read 5, iclass 25, count 2 2006.173.17:41:56.71#ibcon#about to read 6, iclass 25, count 2 2006.173.17:41:56.71#ibcon#read 6, iclass 25, count 2 2006.173.17:41:56.71#ibcon#end of sib2, iclass 25, count 2 2006.173.17:41:56.71#ibcon#*after write, iclass 25, count 2 2006.173.17:41:56.71#ibcon#*before return 0, iclass 25, count 2 2006.173.17:41:56.71#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.17:41:56.71#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.17:41:56.71#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.17:41:56.71#ibcon#ireg 7 cls_cnt 0 2006.173.17:41:56.71#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.17:41:56.83#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.17:41:56.83#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.17:41:56.83#ibcon#enter wrdev, iclass 25, count 0 2006.173.17:41:56.83#ibcon#first serial, iclass 25, count 0 2006.173.17:41:56.83#ibcon#enter sib2, iclass 25, count 0 2006.173.17:41:56.83#ibcon#flushed, iclass 25, count 0 2006.173.17:41:56.83#ibcon#about to write, iclass 25, count 0 2006.173.17:41:56.83#ibcon#wrote, iclass 25, count 0 2006.173.17:41:56.83#ibcon#about to read 3, iclass 25, count 0 2006.173.17:41:56.85#ibcon#read 3, iclass 25, count 0 2006.173.17:41:56.85#ibcon#about to read 4, iclass 25, count 0 2006.173.17:41:56.85#ibcon#read 4, iclass 25, count 0 2006.173.17:41:56.85#ibcon#about to read 5, iclass 25, count 0 2006.173.17:41:56.85#ibcon#read 5, iclass 25, count 0 2006.173.17:41:56.85#ibcon#about to read 6, iclass 25, count 0 2006.173.17:41:56.85#ibcon#read 6, iclass 25, count 0 2006.173.17:41:56.85#ibcon#end of sib2, iclass 25, count 0 2006.173.17:41:56.85#ibcon#*mode == 0, iclass 25, count 0 2006.173.17:41:56.85#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.17:41:56.85#ibcon#[25=USB\r\n] 2006.173.17:41:56.85#ibcon#*before write, iclass 25, count 0 2006.173.17:41:56.85#ibcon#enter sib2, iclass 25, count 0 2006.173.17:41:56.85#ibcon#flushed, iclass 25, count 0 2006.173.17:41:56.85#ibcon#about to write, iclass 25, count 0 2006.173.17:41:56.85#ibcon#wrote, iclass 25, count 0 2006.173.17:41:56.85#ibcon#about to read 3, iclass 25, count 0 2006.173.17:41:56.88#ibcon#read 3, iclass 25, count 0 2006.173.17:41:56.88#ibcon#about to read 4, iclass 25, count 0 2006.173.17:41:56.88#ibcon#read 4, iclass 25, count 0 2006.173.17:41:56.88#ibcon#about to read 5, iclass 25, count 0 2006.173.17:41:56.88#ibcon#read 5, iclass 25, count 0 2006.173.17:41:56.88#ibcon#about to read 6, iclass 25, count 0 2006.173.17:41:56.88#ibcon#read 6, iclass 25, count 0 2006.173.17:41:56.88#ibcon#end of sib2, iclass 25, count 0 2006.173.17:41:56.88#ibcon#*after write, iclass 25, count 0 2006.173.17:41:56.88#ibcon#*before return 0, iclass 25, count 0 2006.173.17:41:56.88#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.17:41:56.88#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.17:41:56.88#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.17:41:56.88#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.17:41:56.88$vck44/vblo=1,629.99 2006.173.17:41:56.88#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.17:41:56.88#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.17:41:56.88#ibcon#ireg 17 cls_cnt 0 2006.173.17:41:56.88#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.17:41:56.88#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.17:41:56.88#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.17:41:56.88#ibcon#enter wrdev, iclass 27, count 0 2006.173.17:41:56.88#ibcon#first serial, iclass 27, count 0 2006.173.17:41:56.88#ibcon#enter sib2, iclass 27, count 0 2006.173.17:41:56.88#ibcon#flushed, iclass 27, count 0 2006.173.17:41:56.88#ibcon#about to write, iclass 27, count 0 2006.173.17:41:56.88#ibcon#wrote, iclass 27, count 0 2006.173.17:41:56.88#ibcon#about to read 3, iclass 27, count 0 2006.173.17:41:56.90#ibcon#read 3, iclass 27, count 0 2006.173.17:41:56.90#ibcon#about to read 4, iclass 27, count 0 2006.173.17:41:56.90#ibcon#read 4, iclass 27, count 0 2006.173.17:41:56.90#ibcon#about to read 5, iclass 27, count 0 2006.173.17:41:56.90#ibcon#read 5, iclass 27, count 0 2006.173.17:41:56.90#ibcon#about to read 6, iclass 27, count 0 2006.173.17:41:56.90#ibcon#read 6, iclass 27, count 0 2006.173.17:41:56.90#ibcon#end of sib2, iclass 27, count 0 2006.173.17:41:56.90#ibcon#*mode == 0, iclass 27, count 0 2006.173.17:41:56.90#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.17:41:56.90#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.17:41:56.90#ibcon#*before write, iclass 27, count 0 2006.173.17:41:56.90#ibcon#enter sib2, iclass 27, count 0 2006.173.17:41:56.90#ibcon#flushed, iclass 27, count 0 2006.173.17:41:56.90#ibcon#about to write, iclass 27, count 0 2006.173.17:41:56.90#ibcon#wrote, iclass 27, count 0 2006.173.17:41:56.90#ibcon#about to read 3, iclass 27, count 0 2006.173.17:41:56.94#ibcon#read 3, iclass 27, count 0 2006.173.17:41:56.94#ibcon#about to read 4, iclass 27, count 0 2006.173.17:41:56.94#ibcon#read 4, iclass 27, count 0 2006.173.17:41:56.94#ibcon#about to read 5, iclass 27, count 0 2006.173.17:41:56.94#ibcon#read 5, iclass 27, count 0 2006.173.17:41:56.94#ibcon#about to read 6, iclass 27, count 0 2006.173.17:41:56.94#ibcon#read 6, iclass 27, count 0 2006.173.17:41:56.94#ibcon#end of sib2, iclass 27, count 0 2006.173.17:41:56.94#ibcon#*after write, iclass 27, count 0 2006.173.17:41:56.94#ibcon#*before return 0, iclass 27, count 0 2006.173.17:41:56.94#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.17:41:56.94#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.17:41:56.94#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.17:41:56.94#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.17:41:56.94$vck44/vb=1,4 2006.173.17:41:56.94#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.17:41:56.94#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.17:41:56.94#ibcon#ireg 11 cls_cnt 2 2006.173.17:41:56.94#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.17:41:56.94#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.17:41:56.94#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.17:41:56.94#ibcon#enter wrdev, iclass 29, count 2 2006.173.17:41:56.94#ibcon#first serial, iclass 29, count 2 2006.173.17:41:56.94#ibcon#enter sib2, iclass 29, count 2 2006.173.17:41:56.94#ibcon#flushed, iclass 29, count 2 2006.173.17:41:56.94#ibcon#about to write, iclass 29, count 2 2006.173.17:41:56.94#ibcon#wrote, iclass 29, count 2 2006.173.17:41:56.94#ibcon#about to read 3, iclass 29, count 2 2006.173.17:41:56.96#ibcon#read 3, iclass 29, count 2 2006.173.17:41:56.96#ibcon#about to read 4, iclass 29, count 2 2006.173.17:41:56.96#ibcon#read 4, iclass 29, count 2 2006.173.17:41:56.96#ibcon#about to read 5, iclass 29, count 2 2006.173.17:41:56.96#ibcon#read 5, iclass 29, count 2 2006.173.17:41:56.96#ibcon#about to read 6, iclass 29, count 2 2006.173.17:41:56.96#ibcon#read 6, iclass 29, count 2 2006.173.17:41:56.96#ibcon#end of sib2, iclass 29, count 2 2006.173.17:41:56.96#ibcon#*mode == 0, iclass 29, count 2 2006.173.17:41:56.96#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.17:41:56.96#ibcon#[27=AT01-04\r\n] 2006.173.17:41:56.96#ibcon#*before write, iclass 29, count 2 2006.173.17:41:56.96#ibcon#enter sib2, iclass 29, count 2 2006.173.17:41:56.96#ibcon#flushed, iclass 29, count 2 2006.173.17:41:56.96#ibcon#about to write, iclass 29, count 2 2006.173.17:41:56.96#ibcon#wrote, iclass 29, count 2 2006.173.17:41:56.96#ibcon#about to read 3, iclass 29, count 2 2006.173.17:41:56.99#ibcon#read 3, iclass 29, count 2 2006.173.17:41:56.99#ibcon#about to read 4, iclass 29, count 2 2006.173.17:41:56.99#ibcon#read 4, iclass 29, count 2 2006.173.17:41:56.99#ibcon#about to read 5, iclass 29, count 2 2006.173.17:41:56.99#ibcon#read 5, iclass 29, count 2 2006.173.17:41:56.99#ibcon#about to read 6, iclass 29, count 2 2006.173.17:41:56.99#ibcon#read 6, iclass 29, count 2 2006.173.17:41:56.99#ibcon#end of sib2, iclass 29, count 2 2006.173.17:41:56.99#ibcon#*after write, iclass 29, count 2 2006.173.17:41:56.99#ibcon#*before return 0, iclass 29, count 2 2006.173.17:41:56.99#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.17:41:56.99#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.17:41:56.99#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.17:41:56.99#ibcon#ireg 7 cls_cnt 0 2006.173.17:41:56.99#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.17:41:57.11#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.17:41:57.11#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.17:41:57.11#ibcon#enter wrdev, iclass 29, count 0 2006.173.17:41:57.11#ibcon#first serial, iclass 29, count 0 2006.173.17:41:57.11#ibcon#enter sib2, iclass 29, count 0 2006.173.17:41:57.11#ibcon#flushed, iclass 29, count 0 2006.173.17:41:57.11#ibcon#about to write, iclass 29, count 0 2006.173.17:41:57.11#ibcon#wrote, iclass 29, count 0 2006.173.17:41:57.11#ibcon#about to read 3, iclass 29, count 0 2006.173.17:41:57.13#ibcon#read 3, iclass 29, count 0 2006.173.17:41:57.13#ibcon#about to read 4, iclass 29, count 0 2006.173.17:41:57.13#ibcon#read 4, iclass 29, count 0 2006.173.17:41:57.13#ibcon#about to read 5, iclass 29, count 0 2006.173.17:41:57.13#ibcon#read 5, iclass 29, count 0 2006.173.17:41:57.13#ibcon#about to read 6, iclass 29, count 0 2006.173.17:41:57.13#ibcon#read 6, iclass 29, count 0 2006.173.17:41:57.13#ibcon#end of sib2, iclass 29, count 0 2006.173.17:41:57.13#ibcon#*mode == 0, iclass 29, count 0 2006.173.17:41:57.13#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.17:41:57.13#ibcon#[27=USB\r\n] 2006.173.17:41:57.13#ibcon#*before write, iclass 29, count 0 2006.173.17:41:57.13#ibcon#enter sib2, iclass 29, count 0 2006.173.17:41:57.13#ibcon#flushed, iclass 29, count 0 2006.173.17:41:57.13#ibcon#about to write, iclass 29, count 0 2006.173.17:41:57.13#ibcon#wrote, iclass 29, count 0 2006.173.17:41:57.13#ibcon#about to read 3, iclass 29, count 0 2006.173.17:41:57.16#ibcon#read 3, iclass 29, count 0 2006.173.17:41:57.16#ibcon#about to read 4, iclass 29, count 0 2006.173.17:41:57.16#ibcon#read 4, iclass 29, count 0 2006.173.17:41:57.16#ibcon#about to read 5, iclass 29, count 0 2006.173.17:41:57.16#ibcon#read 5, iclass 29, count 0 2006.173.17:41:57.16#ibcon#about to read 6, iclass 29, count 0 2006.173.17:41:57.16#ibcon#read 6, iclass 29, count 0 2006.173.17:41:57.16#ibcon#end of sib2, iclass 29, count 0 2006.173.17:41:57.16#ibcon#*after write, iclass 29, count 0 2006.173.17:41:57.16#ibcon#*before return 0, iclass 29, count 0 2006.173.17:41:57.16#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.17:41:57.16#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.17:41:57.16#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.17:41:57.16#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.17:41:57.16$vck44/vblo=2,634.99 2006.173.17:41:57.16#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.17:41:57.16#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.17:41:57.16#ibcon#ireg 17 cls_cnt 0 2006.173.17:41:57.16#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.17:41:57.16#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.17:41:57.16#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.17:41:57.16#ibcon#enter wrdev, iclass 31, count 0 2006.173.17:41:57.16#ibcon#first serial, iclass 31, count 0 2006.173.17:41:57.16#ibcon#enter sib2, iclass 31, count 0 2006.173.17:41:57.16#ibcon#flushed, iclass 31, count 0 2006.173.17:41:57.16#ibcon#about to write, iclass 31, count 0 2006.173.17:41:57.16#ibcon#wrote, iclass 31, count 0 2006.173.17:41:57.16#ibcon#about to read 3, iclass 31, count 0 2006.173.17:41:57.18#ibcon#read 3, iclass 31, count 0 2006.173.17:41:57.18#ibcon#about to read 4, iclass 31, count 0 2006.173.17:41:57.18#ibcon#read 4, iclass 31, count 0 2006.173.17:41:57.18#ibcon#about to read 5, iclass 31, count 0 2006.173.17:41:57.18#ibcon#read 5, iclass 31, count 0 2006.173.17:41:57.18#ibcon#about to read 6, iclass 31, count 0 2006.173.17:41:57.18#ibcon#read 6, iclass 31, count 0 2006.173.17:41:57.18#ibcon#end of sib2, iclass 31, count 0 2006.173.17:41:57.18#ibcon#*mode == 0, iclass 31, count 0 2006.173.17:41:57.18#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.17:41:57.18#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.17:41:57.18#ibcon#*before write, iclass 31, count 0 2006.173.17:41:57.18#ibcon#enter sib2, iclass 31, count 0 2006.173.17:41:57.18#ibcon#flushed, iclass 31, count 0 2006.173.17:41:57.18#ibcon#about to write, iclass 31, count 0 2006.173.17:41:57.18#ibcon#wrote, iclass 31, count 0 2006.173.17:41:57.18#ibcon#about to read 3, iclass 31, count 0 2006.173.17:41:57.22#ibcon#read 3, iclass 31, count 0 2006.173.17:41:57.22#ibcon#about to read 4, iclass 31, count 0 2006.173.17:41:57.22#ibcon#read 4, iclass 31, count 0 2006.173.17:41:57.22#ibcon#about to read 5, iclass 31, count 0 2006.173.17:41:57.22#ibcon#read 5, iclass 31, count 0 2006.173.17:41:57.22#ibcon#about to read 6, iclass 31, count 0 2006.173.17:41:57.22#ibcon#read 6, iclass 31, count 0 2006.173.17:41:57.22#ibcon#end of sib2, iclass 31, count 0 2006.173.17:41:57.22#ibcon#*after write, iclass 31, count 0 2006.173.17:41:57.22#ibcon#*before return 0, iclass 31, count 0 2006.173.17:41:57.22#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.17:41:57.22#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.17:41:57.22#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.17:41:57.22#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.17:41:57.22$vck44/vb=2,4 2006.173.17:41:57.22#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.173.17:41:57.22#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.173.17:41:57.22#ibcon#ireg 11 cls_cnt 2 2006.173.17:41:57.22#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.17:41:57.28#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.17:41:57.28#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.17:41:57.28#ibcon#enter wrdev, iclass 33, count 2 2006.173.17:41:57.28#ibcon#first serial, iclass 33, count 2 2006.173.17:41:57.28#ibcon#enter sib2, iclass 33, count 2 2006.173.17:41:57.28#ibcon#flushed, iclass 33, count 2 2006.173.17:41:57.28#ibcon#about to write, iclass 33, count 2 2006.173.17:41:57.28#ibcon#wrote, iclass 33, count 2 2006.173.17:41:57.28#ibcon#about to read 3, iclass 33, count 2 2006.173.17:41:57.30#ibcon#read 3, iclass 33, count 2 2006.173.17:41:57.30#ibcon#about to read 4, iclass 33, count 2 2006.173.17:41:57.30#ibcon#read 4, iclass 33, count 2 2006.173.17:41:57.30#ibcon#about to read 5, iclass 33, count 2 2006.173.17:41:57.30#ibcon#read 5, iclass 33, count 2 2006.173.17:41:57.30#ibcon#about to read 6, iclass 33, count 2 2006.173.17:41:57.30#ibcon#read 6, iclass 33, count 2 2006.173.17:41:57.30#ibcon#end of sib2, iclass 33, count 2 2006.173.17:41:57.30#ibcon#*mode == 0, iclass 33, count 2 2006.173.17:41:57.30#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.173.17:41:57.30#ibcon#[27=AT02-04\r\n] 2006.173.17:41:57.30#ibcon#*before write, iclass 33, count 2 2006.173.17:41:57.30#ibcon#enter sib2, iclass 33, count 2 2006.173.17:41:57.30#ibcon#flushed, iclass 33, count 2 2006.173.17:41:57.30#ibcon#about to write, iclass 33, count 2 2006.173.17:41:57.30#ibcon#wrote, iclass 33, count 2 2006.173.17:41:57.30#ibcon#about to read 3, iclass 33, count 2 2006.173.17:41:57.33#ibcon#read 3, iclass 33, count 2 2006.173.17:41:57.33#ibcon#about to read 4, iclass 33, count 2 2006.173.17:41:57.33#ibcon#read 4, iclass 33, count 2 2006.173.17:41:57.33#ibcon#about to read 5, iclass 33, count 2 2006.173.17:41:57.33#ibcon#read 5, iclass 33, count 2 2006.173.17:41:57.33#ibcon#about to read 6, iclass 33, count 2 2006.173.17:41:57.33#ibcon#read 6, iclass 33, count 2 2006.173.17:41:57.33#ibcon#end of sib2, iclass 33, count 2 2006.173.17:41:57.33#ibcon#*after write, iclass 33, count 2 2006.173.17:41:57.33#ibcon#*before return 0, iclass 33, count 2 2006.173.17:41:57.33#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.17:41:57.33#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.173.17:41:57.33#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.173.17:41:57.33#ibcon#ireg 7 cls_cnt 0 2006.173.17:41:57.33#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.17:41:57.45#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.17:41:57.45#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.17:41:57.45#ibcon#enter wrdev, iclass 33, count 0 2006.173.17:41:57.45#ibcon#first serial, iclass 33, count 0 2006.173.17:41:57.45#ibcon#enter sib2, iclass 33, count 0 2006.173.17:41:57.45#ibcon#flushed, iclass 33, count 0 2006.173.17:41:57.45#ibcon#about to write, iclass 33, count 0 2006.173.17:41:57.45#ibcon#wrote, iclass 33, count 0 2006.173.17:41:57.45#ibcon#about to read 3, iclass 33, count 0 2006.173.17:41:57.47#ibcon#read 3, iclass 33, count 0 2006.173.17:41:57.47#ibcon#about to read 4, iclass 33, count 0 2006.173.17:41:57.47#ibcon#read 4, iclass 33, count 0 2006.173.17:41:57.47#ibcon#about to read 5, iclass 33, count 0 2006.173.17:41:57.47#ibcon#read 5, iclass 33, count 0 2006.173.17:41:57.47#ibcon#about to read 6, iclass 33, count 0 2006.173.17:41:57.47#ibcon#read 6, iclass 33, count 0 2006.173.17:41:57.47#ibcon#end of sib2, iclass 33, count 0 2006.173.17:41:57.47#ibcon#*mode == 0, iclass 33, count 0 2006.173.17:41:57.47#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.17:41:57.47#ibcon#[27=USB\r\n] 2006.173.17:41:57.47#ibcon#*before write, iclass 33, count 0 2006.173.17:41:57.47#ibcon#enter sib2, iclass 33, count 0 2006.173.17:41:57.47#ibcon#flushed, iclass 33, count 0 2006.173.17:41:57.47#ibcon#about to write, iclass 33, count 0 2006.173.17:41:57.47#ibcon#wrote, iclass 33, count 0 2006.173.17:41:57.47#ibcon#about to read 3, iclass 33, count 0 2006.173.17:41:57.50#ibcon#read 3, iclass 33, count 0 2006.173.17:41:57.50#ibcon#about to read 4, iclass 33, count 0 2006.173.17:41:57.50#ibcon#read 4, iclass 33, count 0 2006.173.17:41:57.50#ibcon#about to read 5, iclass 33, count 0 2006.173.17:41:57.50#ibcon#read 5, iclass 33, count 0 2006.173.17:41:57.50#ibcon#about to read 6, iclass 33, count 0 2006.173.17:41:57.50#ibcon#read 6, iclass 33, count 0 2006.173.17:41:57.50#ibcon#end of sib2, iclass 33, count 0 2006.173.17:41:57.50#ibcon#*after write, iclass 33, count 0 2006.173.17:41:57.50#ibcon#*before return 0, iclass 33, count 0 2006.173.17:41:57.50#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.17:41:57.50#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.173.17:41:57.50#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.17:41:57.50#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.17:41:57.50$vck44/vblo=3,649.99 2006.173.17:41:57.50#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.17:41:57.50#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.17:41:57.50#ibcon#ireg 17 cls_cnt 0 2006.173.17:41:57.50#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.17:41:57.50#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.17:41:57.50#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.17:41:57.50#ibcon#enter wrdev, iclass 35, count 0 2006.173.17:41:57.50#ibcon#first serial, iclass 35, count 0 2006.173.17:41:57.50#ibcon#enter sib2, iclass 35, count 0 2006.173.17:41:57.50#ibcon#flushed, iclass 35, count 0 2006.173.17:41:57.50#ibcon#about to write, iclass 35, count 0 2006.173.17:41:57.50#ibcon#wrote, iclass 35, count 0 2006.173.17:41:57.50#ibcon#about to read 3, iclass 35, count 0 2006.173.17:41:57.52#ibcon#read 3, iclass 35, count 0 2006.173.17:41:57.52#ibcon#about to read 4, iclass 35, count 0 2006.173.17:41:57.52#ibcon#read 4, iclass 35, count 0 2006.173.17:41:57.52#ibcon#about to read 5, iclass 35, count 0 2006.173.17:41:57.52#ibcon#read 5, iclass 35, count 0 2006.173.17:41:57.52#ibcon#about to read 6, iclass 35, count 0 2006.173.17:41:57.52#ibcon#read 6, iclass 35, count 0 2006.173.17:41:57.52#ibcon#end of sib2, iclass 35, count 0 2006.173.17:41:57.52#ibcon#*mode == 0, iclass 35, count 0 2006.173.17:41:57.52#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.17:41:57.52#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.17:41:57.52#ibcon#*before write, iclass 35, count 0 2006.173.17:41:57.52#ibcon#enter sib2, iclass 35, count 0 2006.173.17:41:57.52#ibcon#flushed, iclass 35, count 0 2006.173.17:41:57.52#ibcon#about to write, iclass 35, count 0 2006.173.17:41:57.52#ibcon#wrote, iclass 35, count 0 2006.173.17:41:57.52#ibcon#about to read 3, iclass 35, count 0 2006.173.17:41:57.56#ibcon#read 3, iclass 35, count 0 2006.173.17:41:57.56#ibcon#about to read 4, iclass 35, count 0 2006.173.17:41:57.56#ibcon#read 4, iclass 35, count 0 2006.173.17:41:57.56#ibcon#about to read 5, iclass 35, count 0 2006.173.17:41:57.56#ibcon#read 5, iclass 35, count 0 2006.173.17:41:57.56#ibcon#about to read 6, iclass 35, count 0 2006.173.17:41:57.56#ibcon#read 6, iclass 35, count 0 2006.173.17:41:57.56#ibcon#end of sib2, iclass 35, count 0 2006.173.17:41:57.56#ibcon#*after write, iclass 35, count 0 2006.173.17:41:57.56#ibcon#*before return 0, iclass 35, count 0 2006.173.17:41:57.56#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.17:41:57.56#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.17:41:57.56#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.17:41:57.56#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.17:41:57.56$vck44/vb=3,4 2006.173.17:41:57.56#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.173.17:41:57.56#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.173.17:41:57.56#ibcon#ireg 11 cls_cnt 2 2006.173.17:41:57.56#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.17:41:57.62#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.17:41:57.62#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.17:41:57.62#ibcon#enter wrdev, iclass 37, count 2 2006.173.17:41:57.62#ibcon#first serial, iclass 37, count 2 2006.173.17:41:57.62#ibcon#enter sib2, iclass 37, count 2 2006.173.17:41:57.62#ibcon#flushed, iclass 37, count 2 2006.173.17:41:57.62#ibcon#about to write, iclass 37, count 2 2006.173.17:41:57.62#ibcon#wrote, iclass 37, count 2 2006.173.17:41:57.62#ibcon#about to read 3, iclass 37, count 2 2006.173.17:41:57.64#ibcon#read 3, iclass 37, count 2 2006.173.17:41:57.64#ibcon#about to read 4, iclass 37, count 2 2006.173.17:41:57.64#ibcon#read 4, iclass 37, count 2 2006.173.17:41:57.64#ibcon#about to read 5, iclass 37, count 2 2006.173.17:41:57.64#ibcon#read 5, iclass 37, count 2 2006.173.17:41:57.64#ibcon#about to read 6, iclass 37, count 2 2006.173.17:41:57.64#ibcon#read 6, iclass 37, count 2 2006.173.17:41:57.64#ibcon#end of sib2, iclass 37, count 2 2006.173.17:41:57.64#ibcon#*mode == 0, iclass 37, count 2 2006.173.17:41:57.64#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.173.17:41:57.64#ibcon#[27=AT03-04\r\n] 2006.173.17:41:57.64#ibcon#*before write, iclass 37, count 2 2006.173.17:41:57.64#ibcon#enter sib2, iclass 37, count 2 2006.173.17:41:57.64#ibcon#flushed, iclass 37, count 2 2006.173.17:41:57.64#ibcon#about to write, iclass 37, count 2 2006.173.17:41:57.64#ibcon#wrote, iclass 37, count 2 2006.173.17:41:57.64#ibcon#about to read 3, iclass 37, count 2 2006.173.17:41:57.67#ibcon#read 3, iclass 37, count 2 2006.173.17:41:57.67#ibcon#about to read 4, iclass 37, count 2 2006.173.17:41:57.67#ibcon#read 4, iclass 37, count 2 2006.173.17:41:57.67#ibcon#about to read 5, iclass 37, count 2 2006.173.17:41:57.67#ibcon#read 5, iclass 37, count 2 2006.173.17:41:57.67#ibcon#about to read 6, iclass 37, count 2 2006.173.17:41:57.67#ibcon#read 6, iclass 37, count 2 2006.173.17:41:57.67#ibcon#end of sib2, iclass 37, count 2 2006.173.17:41:57.67#ibcon#*after write, iclass 37, count 2 2006.173.17:41:57.71#ibcon#*before return 0, iclass 37, count 2 2006.173.17:41:57.71#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.17:41:57.71#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.173.17:41:57.71#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.173.17:41:57.71#ibcon#ireg 7 cls_cnt 0 2006.173.17:41:57.71#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.17:41:57.82#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.17:41:57.82#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.17:41:57.82#ibcon#enter wrdev, iclass 37, count 0 2006.173.17:41:57.82#ibcon#first serial, iclass 37, count 0 2006.173.17:41:57.82#ibcon#enter sib2, iclass 37, count 0 2006.173.17:41:57.82#ibcon#flushed, iclass 37, count 0 2006.173.17:41:57.82#ibcon#about to write, iclass 37, count 0 2006.173.17:41:57.82#ibcon#wrote, iclass 37, count 0 2006.173.17:41:57.82#ibcon#about to read 3, iclass 37, count 0 2006.173.17:41:57.84#ibcon#read 3, iclass 37, count 0 2006.173.17:41:57.84#ibcon#about to read 4, iclass 37, count 0 2006.173.17:41:57.84#ibcon#read 4, iclass 37, count 0 2006.173.17:41:57.84#ibcon#about to read 5, iclass 37, count 0 2006.173.17:41:57.84#ibcon#read 5, iclass 37, count 0 2006.173.17:41:57.84#ibcon#about to read 6, iclass 37, count 0 2006.173.17:41:57.84#ibcon#read 6, iclass 37, count 0 2006.173.17:41:57.84#ibcon#end of sib2, iclass 37, count 0 2006.173.17:41:57.84#ibcon#*mode == 0, iclass 37, count 0 2006.173.17:41:57.84#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.17:41:57.84#ibcon#[27=USB\r\n] 2006.173.17:41:57.84#ibcon#*before write, iclass 37, count 0 2006.173.17:41:57.84#ibcon#enter sib2, iclass 37, count 0 2006.173.17:41:57.84#ibcon#flushed, iclass 37, count 0 2006.173.17:41:57.84#ibcon#about to write, iclass 37, count 0 2006.173.17:41:57.84#ibcon#wrote, iclass 37, count 0 2006.173.17:41:57.84#ibcon#about to read 3, iclass 37, count 0 2006.173.17:41:57.87#ibcon#read 3, iclass 37, count 0 2006.173.17:41:57.87#ibcon#about to read 4, iclass 37, count 0 2006.173.17:41:57.87#ibcon#read 4, iclass 37, count 0 2006.173.17:41:57.87#ibcon#about to read 5, iclass 37, count 0 2006.173.17:41:57.87#ibcon#read 5, iclass 37, count 0 2006.173.17:41:57.87#ibcon#about to read 6, iclass 37, count 0 2006.173.17:41:57.87#ibcon#read 6, iclass 37, count 0 2006.173.17:41:57.87#ibcon#end of sib2, iclass 37, count 0 2006.173.17:41:57.87#ibcon#*after write, iclass 37, count 0 2006.173.17:41:57.87#ibcon#*before return 0, iclass 37, count 0 2006.173.17:41:57.87#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.17:41:57.87#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.173.17:41:57.87#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.17:41:57.87#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.17:41:57.87$vck44/vblo=4,679.99 2006.173.17:41:57.87#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.17:41:57.87#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.17:41:57.87#ibcon#ireg 17 cls_cnt 0 2006.173.17:41:57.87#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.17:41:57.87#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.17:41:57.87#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.17:41:57.87#ibcon#enter wrdev, iclass 39, count 0 2006.173.17:41:57.87#ibcon#first serial, iclass 39, count 0 2006.173.17:41:57.87#ibcon#enter sib2, iclass 39, count 0 2006.173.17:41:57.87#ibcon#flushed, iclass 39, count 0 2006.173.17:41:57.87#ibcon#about to write, iclass 39, count 0 2006.173.17:41:57.87#ibcon#wrote, iclass 39, count 0 2006.173.17:41:57.87#ibcon#about to read 3, iclass 39, count 0 2006.173.17:41:57.89#ibcon#read 3, iclass 39, count 0 2006.173.17:41:57.89#ibcon#about to read 4, iclass 39, count 0 2006.173.17:41:57.89#ibcon#read 4, iclass 39, count 0 2006.173.17:41:57.89#ibcon#about to read 5, iclass 39, count 0 2006.173.17:41:57.89#ibcon#read 5, iclass 39, count 0 2006.173.17:41:57.89#ibcon#about to read 6, iclass 39, count 0 2006.173.17:41:57.89#ibcon#read 6, iclass 39, count 0 2006.173.17:41:57.89#ibcon#end of sib2, iclass 39, count 0 2006.173.17:41:57.89#ibcon#*mode == 0, iclass 39, count 0 2006.173.17:41:57.89#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.17:41:57.89#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.17:41:57.89#ibcon#*before write, iclass 39, count 0 2006.173.17:41:57.89#ibcon#enter sib2, iclass 39, count 0 2006.173.17:41:57.89#ibcon#flushed, iclass 39, count 0 2006.173.17:41:57.89#ibcon#about to write, iclass 39, count 0 2006.173.17:41:57.89#ibcon#wrote, iclass 39, count 0 2006.173.17:41:57.89#ibcon#about to read 3, iclass 39, count 0 2006.173.17:41:57.93#ibcon#read 3, iclass 39, count 0 2006.173.17:41:57.93#ibcon#about to read 4, iclass 39, count 0 2006.173.17:41:57.93#ibcon#read 4, iclass 39, count 0 2006.173.17:41:57.93#ibcon#about to read 5, iclass 39, count 0 2006.173.17:41:57.93#ibcon#read 5, iclass 39, count 0 2006.173.17:41:57.93#ibcon#about to read 6, iclass 39, count 0 2006.173.17:41:57.93#ibcon#read 6, iclass 39, count 0 2006.173.17:41:57.93#ibcon#end of sib2, iclass 39, count 0 2006.173.17:41:57.93#ibcon#*after write, iclass 39, count 0 2006.173.17:41:57.93#ibcon#*before return 0, iclass 39, count 0 2006.173.17:41:57.93#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.17:41:57.93#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.17:41:57.93#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.17:41:57.93#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.17:41:57.93$vck44/vb=4,4 2006.173.17:41:57.93#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.17:41:57.93#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.17:41:57.93#ibcon#ireg 11 cls_cnt 2 2006.173.17:41:57.93#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.17:41:57.99#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.17:41:57.99#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.17:41:57.99#ibcon#enter wrdev, iclass 3, count 2 2006.173.17:41:57.99#ibcon#first serial, iclass 3, count 2 2006.173.17:41:57.99#ibcon#enter sib2, iclass 3, count 2 2006.173.17:41:57.99#ibcon#flushed, iclass 3, count 2 2006.173.17:41:57.99#ibcon#about to write, iclass 3, count 2 2006.173.17:41:57.99#ibcon#wrote, iclass 3, count 2 2006.173.17:41:57.99#ibcon#about to read 3, iclass 3, count 2 2006.173.17:41:58.01#ibcon#read 3, iclass 3, count 2 2006.173.17:41:58.01#ibcon#about to read 4, iclass 3, count 2 2006.173.17:41:58.01#ibcon#read 4, iclass 3, count 2 2006.173.17:41:58.01#ibcon#about to read 5, iclass 3, count 2 2006.173.17:41:58.01#ibcon#read 5, iclass 3, count 2 2006.173.17:41:58.01#ibcon#about to read 6, iclass 3, count 2 2006.173.17:41:58.01#ibcon#read 6, iclass 3, count 2 2006.173.17:41:58.01#ibcon#end of sib2, iclass 3, count 2 2006.173.17:41:58.01#ibcon#*mode == 0, iclass 3, count 2 2006.173.17:41:58.01#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.17:41:58.01#ibcon#[27=AT04-04\r\n] 2006.173.17:41:58.01#ibcon#*before write, iclass 3, count 2 2006.173.17:41:58.01#ibcon#enter sib2, iclass 3, count 2 2006.173.17:41:58.01#ibcon#flushed, iclass 3, count 2 2006.173.17:41:58.01#ibcon#about to write, iclass 3, count 2 2006.173.17:41:58.01#ibcon#wrote, iclass 3, count 2 2006.173.17:41:58.01#ibcon#about to read 3, iclass 3, count 2 2006.173.17:41:58.04#ibcon#read 3, iclass 3, count 2 2006.173.17:41:58.04#ibcon#about to read 4, iclass 3, count 2 2006.173.17:41:58.04#ibcon#read 4, iclass 3, count 2 2006.173.17:41:58.04#ibcon#about to read 5, iclass 3, count 2 2006.173.17:41:58.04#ibcon#read 5, iclass 3, count 2 2006.173.17:41:58.04#ibcon#about to read 6, iclass 3, count 2 2006.173.17:41:58.04#ibcon#read 6, iclass 3, count 2 2006.173.17:41:58.04#ibcon#end of sib2, iclass 3, count 2 2006.173.17:41:58.04#ibcon#*after write, iclass 3, count 2 2006.173.17:41:58.04#ibcon#*before return 0, iclass 3, count 2 2006.173.17:41:58.04#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.17:41:58.04#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.17:41:58.04#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.17:41:58.04#ibcon#ireg 7 cls_cnt 0 2006.173.17:41:58.04#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.17:41:58.16#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.17:41:58.16#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.17:41:58.16#ibcon#enter wrdev, iclass 3, count 0 2006.173.17:41:58.16#ibcon#first serial, iclass 3, count 0 2006.173.17:41:58.16#ibcon#enter sib2, iclass 3, count 0 2006.173.17:41:58.16#ibcon#flushed, iclass 3, count 0 2006.173.17:41:58.16#ibcon#about to write, iclass 3, count 0 2006.173.17:41:58.16#ibcon#wrote, iclass 3, count 0 2006.173.17:41:58.16#ibcon#about to read 3, iclass 3, count 0 2006.173.17:41:58.18#ibcon#read 3, iclass 3, count 0 2006.173.17:41:58.18#ibcon#about to read 4, iclass 3, count 0 2006.173.17:41:58.18#ibcon#read 4, iclass 3, count 0 2006.173.17:41:58.18#ibcon#about to read 5, iclass 3, count 0 2006.173.17:41:58.18#ibcon#read 5, iclass 3, count 0 2006.173.17:41:58.18#ibcon#about to read 6, iclass 3, count 0 2006.173.17:41:58.18#ibcon#read 6, iclass 3, count 0 2006.173.17:41:58.18#ibcon#end of sib2, iclass 3, count 0 2006.173.17:41:58.18#ibcon#*mode == 0, iclass 3, count 0 2006.173.17:41:58.18#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.17:41:58.18#ibcon#[27=USB\r\n] 2006.173.17:41:58.18#ibcon#*before write, iclass 3, count 0 2006.173.17:41:58.18#ibcon#enter sib2, iclass 3, count 0 2006.173.17:41:58.18#ibcon#flushed, iclass 3, count 0 2006.173.17:41:58.18#ibcon#about to write, iclass 3, count 0 2006.173.17:41:58.18#ibcon#wrote, iclass 3, count 0 2006.173.17:41:58.18#ibcon#about to read 3, iclass 3, count 0 2006.173.17:41:58.21#ibcon#read 3, iclass 3, count 0 2006.173.17:41:58.21#ibcon#about to read 4, iclass 3, count 0 2006.173.17:41:58.21#ibcon#read 4, iclass 3, count 0 2006.173.17:41:58.21#ibcon#about to read 5, iclass 3, count 0 2006.173.17:41:58.21#ibcon#read 5, iclass 3, count 0 2006.173.17:41:58.21#ibcon#about to read 6, iclass 3, count 0 2006.173.17:41:58.21#ibcon#read 6, iclass 3, count 0 2006.173.17:41:58.21#ibcon#end of sib2, iclass 3, count 0 2006.173.17:41:58.21#ibcon#*after write, iclass 3, count 0 2006.173.17:41:58.21#ibcon#*before return 0, iclass 3, count 0 2006.173.17:41:58.21#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.17:41:58.21#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.17:41:58.21#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.17:41:58.21#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.17:41:58.21$vck44/vblo=5,709.99 2006.173.17:41:58.21#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.17:41:58.21#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.17:41:58.21#ibcon#ireg 17 cls_cnt 0 2006.173.17:41:58.21#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.17:41:58.21#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.17:41:58.21#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.17:41:58.21#ibcon#enter wrdev, iclass 5, count 0 2006.173.17:41:58.21#ibcon#first serial, iclass 5, count 0 2006.173.17:41:58.21#ibcon#enter sib2, iclass 5, count 0 2006.173.17:41:58.21#ibcon#flushed, iclass 5, count 0 2006.173.17:41:58.21#ibcon#about to write, iclass 5, count 0 2006.173.17:41:58.21#ibcon#wrote, iclass 5, count 0 2006.173.17:41:58.21#ibcon#about to read 3, iclass 5, count 0 2006.173.17:41:58.23#ibcon#read 3, iclass 5, count 0 2006.173.17:41:58.23#ibcon#about to read 4, iclass 5, count 0 2006.173.17:41:58.23#ibcon#read 4, iclass 5, count 0 2006.173.17:41:58.23#ibcon#about to read 5, iclass 5, count 0 2006.173.17:41:58.23#ibcon#read 5, iclass 5, count 0 2006.173.17:41:58.23#ibcon#about to read 6, iclass 5, count 0 2006.173.17:41:58.23#ibcon#read 6, iclass 5, count 0 2006.173.17:41:58.23#ibcon#end of sib2, iclass 5, count 0 2006.173.17:41:58.23#ibcon#*mode == 0, iclass 5, count 0 2006.173.17:41:58.23#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.17:41:58.23#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.17:41:58.23#ibcon#*before write, iclass 5, count 0 2006.173.17:41:58.23#ibcon#enter sib2, iclass 5, count 0 2006.173.17:41:58.23#ibcon#flushed, iclass 5, count 0 2006.173.17:41:58.23#ibcon#about to write, iclass 5, count 0 2006.173.17:41:58.23#ibcon#wrote, iclass 5, count 0 2006.173.17:41:58.23#ibcon#about to read 3, iclass 5, count 0 2006.173.17:41:58.27#ibcon#read 3, iclass 5, count 0 2006.173.17:41:58.27#ibcon#about to read 4, iclass 5, count 0 2006.173.17:41:58.27#ibcon#read 4, iclass 5, count 0 2006.173.17:41:58.27#ibcon#about to read 5, iclass 5, count 0 2006.173.17:41:58.27#ibcon#read 5, iclass 5, count 0 2006.173.17:41:58.27#ibcon#about to read 6, iclass 5, count 0 2006.173.17:41:58.27#ibcon#read 6, iclass 5, count 0 2006.173.17:41:58.27#ibcon#end of sib2, iclass 5, count 0 2006.173.17:41:58.27#ibcon#*after write, iclass 5, count 0 2006.173.17:41:58.27#ibcon#*before return 0, iclass 5, count 0 2006.173.17:41:58.27#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.17:41:58.27#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.17:41:58.27#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.17:41:58.27#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.17:41:58.27$vck44/vb=5,4 2006.173.17:41:58.27#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.173.17:41:58.27#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.173.17:41:58.27#ibcon#ireg 11 cls_cnt 2 2006.173.17:41:58.27#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.17:41:58.33#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.17:41:58.33#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.17:41:58.33#ibcon#enter wrdev, iclass 7, count 2 2006.173.17:41:58.33#ibcon#first serial, iclass 7, count 2 2006.173.17:41:58.33#ibcon#enter sib2, iclass 7, count 2 2006.173.17:41:58.33#ibcon#flushed, iclass 7, count 2 2006.173.17:41:58.33#ibcon#about to write, iclass 7, count 2 2006.173.17:41:58.33#ibcon#wrote, iclass 7, count 2 2006.173.17:41:58.33#ibcon#about to read 3, iclass 7, count 2 2006.173.17:41:58.35#ibcon#read 3, iclass 7, count 2 2006.173.17:41:58.35#ibcon#about to read 4, iclass 7, count 2 2006.173.17:41:58.35#ibcon#read 4, iclass 7, count 2 2006.173.17:41:58.35#ibcon#about to read 5, iclass 7, count 2 2006.173.17:41:58.35#ibcon#read 5, iclass 7, count 2 2006.173.17:41:58.35#ibcon#about to read 6, iclass 7, count 2 2006.173.17:41:58.35#ibcon#read 6, iclass 7, count 2 2006.173.17:41:58.35#ibcon#end of sib2, iclass 7, count 2 2006.173.17:41:58.35#ibcon#*mode == 0, iclass 7, count 2 2006.173.17:41:58.35#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.173.17:41:58.35#ibcon#[27=AT05-04\r\n] 2006.173.17:41:58.35#ibcon#*before write, iclass 7, count 2 2006.173.17:41:58.35#ibcon#enter sib2, iclass 7, count 2 2006.173.17:41:58.35#ibcon#flushed, iclass 7, count 2 2006.173.17:41:58.35#ibcon#about to write, iclass 7, count 2 2006.173.17:41:58.35#ibcon#wrote, iclass 7, count 2 2006.173.17:41:58.35#ibcon#about to read 3, iclass 7, count 2 2006.173.17:41:58.38#ibcon#read 3, iclass 7, count 2 2006.173.17:41:58.38#ibcon#about to read 4, iclass 7, count 2 2006.173.17:41:58.38#ibcon#read 4, iclass 7, count 2 2006.173.17:41:58.38#ibcon#about to read 5, iclass 7, count 2 2006.173.17:41:58.38#ibcon#read 5, iclass 7, count 2 2006.173.17:41:58.38#ibcon#about to read 6, iclass 7, count 2 2006.173.17:41:58.38#ibcon#read 6, iclass 7, count 2 2006.173.17:41:58.38#ibcon#end of sib2, iclass 7, count 2 2006.173.17:41:58.38#ibcon#*after write, iclass 7, count 2 2006.173.17:41:58.38#ibcon#*before return 0, iclass 7, count 2 2006.173.17:41:58.38#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.17:41:58.38#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.173.17:41:58.38#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.173.17:41:58.38#ibcon#ireg 7 cls_cnt 0 2006.173.17:41:58.38#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.17:41:58.50#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.17:41:58.50#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.17:41:58.50#ibcon#enter wrdev, iclass 7, count 0 2006.173.17:41:58.50#ibcon#first serial, iclass 7, count 0 2006.173.17:41:58.50#ibcon#enter sib2, iclass 7, count 0 2006.173.17:41:58.50#ibcon#flushed, iclass 7, count 0 2006.173.17:41:58.50#ibcon#about to write, iclass 7, count 0 2006.173.17:41:58.50#ibcon#wrote, iclass 7, count 0 2006.173.17:41:58.50#ibcon#about to read 3, iclass 7, count 0 2006.173.17:41:58.52#ibcon#read 3, iclass 7, count 0 2006.173.17:41:58.52#ibcon#about to read 4, iclass 7, count 0 2006.173.17:41:58.52#ibcon#read 4, iclass 7, count 0 2006.173.17:41:58.52#ibcon#about to read 5, iclass 7, count 0 2006.173.17:41:58.52#ibcon#read 5, iclass 7, count 0 2006.173.17:41:58.52#ibcon#about to read 6, iclass 7, count 0 2006.173.17:41:58.52#ibcon#read 6, iclass 7, count 0 2006.173.17:41:58.52#ibcon#end of sib2, iclass 7, count 0 2006.173.17:41:58.52#ibcon#*mode == 0, iclass 7, count 0 2006.173.17:41:58.52#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.17:41:58.52#ibcon#[27=USB\r\n] 2006.173.17:41:58.52#ibcon#*before write, iclass 7, count 0 2006.173.17:41:58.52#ibcon#enter sib2, iclass 7, count 0 2006.173.17:41:58.52#ibcon#flushed, iclass 7, count 0 2006.173.17:41:58.52#ibcon#about to write, iclass 7, count 0 2006.173.17:41:58.52#ibcon#wrote, iclass 7, count 0 2006.173.17:41:58.52#ibcon#about to read 3, iclass 7, count 0 2006.173.17:41:58.55#ibcon#read 3, iclass 7, count 0 2006.173.17:41:58.55#ibcon#about to read 4, iclass 7, count 0 2006.173.17:41:58.55#ibcon#read 4, iclass 7, count 0 2006.173.17:41:58.55#ibcon#about to read 5, iclass 7, count 0 2006.173.17:41:58.55#ibcon#read 5, iclass 7, count 0 2006.173.17:41:58.55#ibcon#about to read 6, iclass 7, count 0 2006.173.17:41:58.55#ibcon#read 6, iclass 7, count 0 2006.173.17:41:58.55#ibcon#end of sib2, iclass 7, count 0 2006.173.17:41:58.55#ibcon#*after write, iclass 7, count 0 2006.173.17:41:58.55#ibcon#*before return 0, iclass 7, count 0 2006.173.17:41:58.55#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.17:41:58.55#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.173.17:41:58.55#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.17:41:58.55#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.17:41:58.55$vck44/vblo=6,719.99 2006.173.17:41:58.55#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.17:41:58.55#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.17:41:58.55#ibcon#ireg 17 cls_cnt 0 2006.173.17:41:58.55#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.17:41:58.55#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.17:41:58.55#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.17:41:58.55#ibcon#enter wrdev, iclass 11, count 0 2006.173.17:41:58.55#ibcon#first serial, iclass 11, count 0 2006.173.17:41:58.55#ibcon#enter sib2, iclass 11, count 0 2006.173.17:41:58.55#ibcon#flushed, iclass 11, count 0 2006.173.17:41:58.55#ibcon#about to write, iclass 11, count 0 2006.173.17:41:58.55#ibcon#wrote, iclass 11, count 0 2006.173.17:41:58.55#ibcon#about to read 3, iclass 11, count 0 2006.173.17:41:58.57#ibcon#read 3, iclass 11, count 0 2006.173.17:41:58.57#ibcon#about to read 4, iclass 11, count 0 2006.173.17:41:58.57#ibcon#read 4, iclass 11, count 0 2006.173.17:41:58.57#ibcon#about to read 5, iclass 11, count 0 2006.173.17:41:58.57#ibcon#read 5, iclass 11, count 0 2006.173.17:41:58.57#ibcon#about to read 6, iclass 11, count 0 2006.173.17:41:58.57#ibcon#read 6, iclass 11, count 0 2006.173.17:41:58.57#ibcon#end of sib2, iclass 11, count 0 2006.173.17:41:58.57#ibcon#*mode == 0, iclass 11, count 0 2006.173.17:41:58.57#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.17:41:58.57#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.17:41:58.57#ibcon#*before write, iclass 11, count 0 2006.173.17:41:58.57#ibcon#enter sib2, iclass 11, count 0 2006.173.17:41:58.57#ibcon#flushed, iclass 11, count 0 2006.173.17:41:58.57#ibcon#about to write, iclass 11, count 0 2006.173.17:41:58.57#ibcon#wrote, iclass 11, count 0 2006.173.17:41:58.57#ibcon#about to read 3, iclass 11, count 0 2006.173.17:41:58.61#ibcon#read 3, iclass 11, count 0 2006.173.17:41:58.61#ibcon#about to read 4, iclass 11, count 0 2006.173.17:41:58.61#ibcon#read 4, iclass 11, count 0 2006.173.17:41:58.61#ibcon#about to read 5, iclass 11, count 0 2006.173.17:41:58.61#ibcon#read 5, iclass 11, count 0 2006.173.17:41:58.61#ibcon#about to read 6, iclass 11, count 0 2006.173.17:41:58.61#ibcon#read 6, iclass 11, count 0 2006.173.17:41:58.61#ibcon#end of sib2, iclass 11, count 0 2006.173.17:41:58.61#ibcon#*after write, iclass 11, count 0 2006.173.17:41:58.61#ibcon#*before return 0, iclass 11, count 0 2006.173.17:41:58.61#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.17:41:58.61#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.17:41:58.61#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.17:41:58.61#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.17:41:58.61$vck44/vb=6,4 2006.173.17:41:58.61#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.173.17:41:58.61#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.173.17:41:58.61#ibcon#ireg 11 cls_cnt 2 2006.173.17:41:58.61#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.17:41:58.67#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.17:41:58.67#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.17:41:58.67#ibcon#enter wrdev, iclass 13, count 2 2006.173.17:41:58.67#ibcon#first serial, iclass 13, count 2 2006.173.17:41:58.67#ibcon#enter sib2, iclass 13, count 2 2006.173.17:41:58.67#ibcon#flushed, iclass 13, count 2 2006.173.17:41:58.67#ibcon#about to write, iclass 13, count 2 2006.173.17:41:58.67#ibcon#wrote, iclass 13, count 2 2006.173.17:41:58.67#ibcon#about to read 3, iclass 13, count 2 2006.173.17:41:58.69#ibcon#read 3, iclass 13, count 2 2006.173.17:41:58.69#ibcon#about to read 4, iclass 13, count 2 2006.173.17:41:58.69#ibcon#read 4, iclass 13, count 2 2006.173.17:41:58.69#ibcon#about to read 5, iclass 13, count 2 2006.173.17:41:58.69#ibcon#read 5, iclass 13, count 2 2006.173.17:41:58.69#ibcon#about to read 6, iclass 13, count 2 2006.173.17:41:58.69#ibcon#read 6, iclass 13, count 2 2006.173.17:41:58.69#ibcon#end of sib2, iclass 13, count 2 2006.173.17:41:58.69#ibcon#*mode == 0, iclass 13, count 2 2006.173.17:41:58.69#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.173.17:41:58.69#ibcon#[27=AT06-04\r\n] 2006.173.17:41:58.69#ibcon#*before write, iclass 13, count 2 2006.173.17:41:58.69#ibcon#enter sib2, iclass 13, count 2 2006.173.17:41:58.69#ibcon#flushed, iclass 13, count 2 2006.173.17:41:58.69#ibcon#about to write, iclass 13, count 2 2006.173.17:41:58.69#ibcon#wrote, iclass 13, count 2 2006.173.17:41:58.69#ibcon#about to read 3, iclass 13, count 2 2006.173.17:41:58.72#ibcon#read 3, iclass 13, count 2 2006.173.17:41:58.72#ibcon#about to read 4, iclass 13, count 2 2006.173.17:41:58.72#ibcon#read 4, iclass 13, count 2 2006.173.17:41:58.72#ibcon#about to read 5, iclass 13, count 2 2006.173.17:41:58.72#ibcon#read 5, iclass 13, count 2 2006.173.17:41:58.72#ibcon#about to read 6, iclass 13, count 2 2006.173.17:41:58.72#ibcon#read 6, iclass 13, count 2 2006.173.17:41:58.72#ibcon#end of sib2, iclass 13, count 2 2006.173.17:41:58.72#ibcon#*after write, iclass 13, count 2 2006.173.17:41:58.72#ibcon#*before return 0, iclass 13, count 2 2006.173.17:41:58.72#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.17:41:58.72#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.173.17:41:58.72#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.173.17:41:58.72#ibcon#ireg 7 cls_cnt 0 2006.173.17:41:58.72#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.17:41:58.84#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.17:41:58.84#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.17:41:58.84#ibcon#enter wrdev, iclass 13, count 0 2006.173.17:41:58.84#ibcon#first serial, iclass 13, count 0 2006.173.17:41:58.84#ibcon#enter sib2, iclass 13, count 0 2006.173.17:41:58.84#ibcon#flushed, iclass 13, count 0 2006.173.17:41:58.84#ibcon#about to write, iclass 13, count 0 2006.173.17:41:58.84#ibcon#wrote, iclass 13, count 0 2006.173.17:41:58.84#ibcon#about to read 3, iclass 13, count 0 2006.173.17:41:58.86#ibcon#read 3, iclass 13, count 0 2006.173.17:41:58.86#ibcon#about to read 4, iclass 13, count 0 2006.173.17:41:58.86#ibcon#read 4, iclass 13, count 0 2006.173.17:41:58.86#ibcon#about to read 5, iclass 13, count 0 2006.173.17:41:58.86#ibcon#read 5, iclass 13, count 0 2006.173.17:41:58.86#ibcon#about to read 6, iclass 13, count 0 2006.173.17:41:58.86#ibcon#read 6, iclass 13, count 0 2006.173.17:41:58.86#ibcon#end of sib2, iclass 13, count 0 2006.173.17:41:58.86#ibcon#*mode == 0, iclass 13, count 0 2006.173.17:41:58.86#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.17:41:58.86#ibcon#[27=USB\r\n] 2006.173.17:41:58.86#ibcon#*before write, iclass 13, count 0 2006.173.17:41:58.86#ibcon#enter sib2, iclass 13, count 0 2006.173.17:41:58.86#ibcon#flushed, iclass 13, count 0 2006.173.17:41:58.86#ibcon#about to write, iclass 13, count 0 2006.173.17:41:58.86#ibcon#wrote, iclass 13, count 0 2006.173.17:41:58.86#ibcon#about to read 3, iclass 13, count 0 2006.173.17:41:58.89#ibcon#read 3, iclass 13, count 0 2006.173.17:41:58.89#ibcon#about to read 4, iclass 13, count 0 2006.173.17:41:58.89#ibcon#read 4, iclass 13, count 0 2006.173.17:41:58.89#ibcon#about to read 5, iclass 13, count 0 2006.173.17:41:58.89#ibcon#read 5, iclass 13, count 0 2006.173.17:41:58.89#ibcon#about to read 6, iclass 13, count 0 2006.173.17:41:58.89#ibcon#read 6, iclass 13, count 0 2006.173.17:41:58.89#ibcon#end of sib2, iclass 13, count 0 2006.173.17:41:58.89#ibcon#*after write, iclass 13, count 0 2006.173.17:41:58.89#ibcon#*before return 0, iclass 13, count 0 2006.173.17:41:58.89#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.17:41:58.89#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.173.17:41:58.89#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.17:41:58.89#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.17:41:58.89$vck44/vblo=7,734.99 2006.173.17:41:58.89#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.17:41:58.89#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.17:41:58.89#ibcon#ireg 17 cls_cnt 0 2006.173.17:41:58.89#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.17:41:58.89#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.17:41:58.89#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.17:41:58.89#ibcon#enter wrdev, iclass 15, count 0 2006.173.17:41:58.89#ibcon#first serial, iclass 15, count 0 2006.173.17:41:58.89#ibcon#enter sib2, iclass 15, count 0 2006.173.17:41:58.89#ibcon#flushed, iclass 15, count 0 2006.173.17:41:58.89#ibcon#about to write, iclass 15, count 0 2006.173.17:41:58.89#ibcon#wrote, iclass 15, count 0 2006.173.17:41:58.89#ibcon#about to read 3, iclass 15, count 0 2006.173.17:41:58.91#ibcon#read 3, iclass 15, count 0 2006.173.17:41:58.91#ibcon#about to read 4, iclass 15, count 0 2006.173.17:41:58.91#ibcon#read 4, iclass 15, count 0 2006.173.17:41:58.91#ibcon#about to read 5, iclass 15, count 0 2006.173.17:41:58.91#ibcon#read 5, iclass 15, count 0 2006.173.17:41:58.91#ibcon#about to read 6, iclass 15, count 0 2006.173.17:41:58.91#ibcon#read 6, iclass 15, count 0 2006.173.17:41:58.91#ibcon#end of sib2, iclass 15, count 0 2006.173.17:41:58.91#ibcon#*mode == 0, iclass 15, count 0 2006.173.17:41:58.91#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.17:41:58.91#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.17:41:58.91#ibcon#*before write, iclass 15, count 0 2006.173.17:41:58.91#ibcon#enter sib2, iclass 15, count 0 2006.173.17:41:58.91#ibcon#flushed, iclass 15, count 0 2006.173.17:41:58.91#ibcon#about to write, iclass 15, count 0 2006.173.17:41:58.91#ibcon#wrote, iclass 15, count 0 2006.173.17:41:58.91#ibcon#about to read 3, iclass 15, count 0 2006.173.17:41:58.95#ibcon#read 3, iclass 15, count 0 2006.173.17:41:58.95#ibcon#about to read 4, iclass 15, count 0 2006.173.17:41:58.95#ibcon#read 4, iclass 15, count 0 2006.173.17:41:58.95#ibcon#about to read 5, iclass 15, count 0 2006.173.17:41:58.95#ibcon#read 5, iclass 15, count 0 2006.173.17:41:58.95#ibcon#about to read 6, iclass 15, count 0 2006.173.17:41:58.95#ibcon#read 6, iclass 15, count 0 2006.173.17:41:58.95#ibcon#end of sib2, iclass 15, count 0 2006.173.17:41:58.95#ibcon#*after write, iclass 15, count 0 2006.173.17:41:58.95#ibcon#*before return 0, iclass 15, count 0 2006.173.17:41:58.95#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.17:41:58.95#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.17:41:58.95#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.17:41:58.95#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.17:41:58.95$vck44/vb=7,4 2006.173.17:41:58.95#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.17:41:58.95#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.17:41:58.95#ibcon#ireg 11 cls_cnt 2 2006.173.17:41:58.95#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.17:41:59.01#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.17:41:59.01#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.17:41:59.01#ibcon#enter wrdev, iclass 17, count 2 2006.173.17:41:59.01#ibcon#first serial, iclass 17, count 2 2006.173.17:41:59.01#ibcon#enter sib2, iclass 17, count 2 2006.173.17:41:59.01#ibcon#flushed, iclass 17, count 2 2006.173.17:41:59.01#ibcon#about to write, iclass 17, count 2 2006.173.17:41:59.01#ibcon#wrote, iclass 17, count 2 2006.173.17:41:59.01#ibcon#about to read 3, iclass 17, count 2 2006.173.17:41:59.03#ibcon#read 3, iclass 17, count 2 2006.173.17:41:59.03#ibcon#about to read 4, iclass 17, count 2 2006.173.17:41:59.03#ibcon#read 4, iclass 17, count 2 2006.173.17:41:59.03#ibcon#about to read 5, iclass 17, count 2 2006.173.17:41:59.03#ibcon#read 5, iclass 17, count 2 2006.173.17:41:59.03#ibcon#about to read 6, iclass 17, count 2 2006.173.17:41:59.03#ibcon#read 6, iclass 17, count 2 2006.173.17:41:59.03#ibcon#end of sib2, iclass 17, count 2 2006.173.17:41:59.03#ibcon#*mode == 0, iclass 17, count 2 2006.173.17:41:59.03#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.17:41:59.03#ibcon#[27=AT07-04\r\n] 2006.173.17:41:59.03#ibcon#*before write, iclass 17, count 2 2006.173.17:41:59.03#ibcon#enter sib2, iclass 17, count 2 2006.173.17:41:59.03#ibcon#flushed, iclass 17, count 2 2006.173.17:41:59.03#ibcon#about to write, iclass 17, count 2 2006.173.17:41:59.03#ibcon#wrote, iclass 17, count 2 2006.173.17:41:59.03#ibcon#about to read 3, iclass 17, count 2 2006.173.17:41:59.06#ibcon#read 3, iclass 17, count 2 2006.173.17:41:59.06#ibcon#about to read 4, iclass 17, count 2 2006.173.17:41:59.06#ibcon#read 4, iclass 17, count 2 2006.173.17:41:59.06#ibcon#about to read 5, iclass 17, count 2 2006.173.17:41:59.06#ibcon#read 5, iclass 17, count 2 2006.173.17:41:59.06#ibcon#about to read 6, iclass 17, count 2 2006.173.17:41:59.06#ibcon#read 6, iclass 17, count 2 2006.173.17:41:59.06#ibcon#end of sib2, iclass 17, count 2 2006.173.17:41:59.06#ibcon#*after write, iclass 17, count 2 2006.173.17:41:59.06#ibcon#*before return 0, iclass 17, count 2 2006.173.17:41:59.06#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.17:41:59.06#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.17:41:59.06#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.17:41:59.06#ibcon#ireg 7 cls_cnt 0 2006.173.17:41:59.06#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.17:41:59.18#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.17:41:59.18#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.17:41:59.18#ibcon#enter wrdev, iclass 17, count 0 2006.173.17:41:59.18#ibcon#first serial, iclass 17, count 0 2006.173.17:41:59.18#ibcon#enter sib2, iclass 17, count 0 2006.173.17:41:59.18#ibcon#flushed, iclass 17, count 0 2006.173.17:41:59.18#ibcon#about to write, iclass 17, count 0 2006.173.17:41:59.18#ibcon#wrote, iclass 17, count 0 2006.173.17:41:59.18#ibcon#about to read 3, iclass 17, count 0 2006.173.17:41:59.20#ibcon#read 3, iclass 17, count 0 2006.173.17:41:59.20#ibcon#about to read 4, iclass 17, count 0 2006.173.17:41:59.20#ibcon#read 4, iclass 17, count 0 2006.173.17:41:59.20#ibcon#about to read 5, iclass 17, count 0 2006.173.17:41:59.20#ibcon#read 5, iclass 17, count 0 2006.173.17:41:59.20#ibcon#about to read 6, iclass 17, count 0 2006.173.17:41:59.20#ibcon#read 6, iclass 17, count 0 2006.173.17:41:59.20#ibcon#end of sib2, iclass 17, count 0 2006.173.17:41:59.20#ibcon#*mode == 0, iclass 17, count 0 2006.173.17:41:59.20#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.17:41:59.20#ibcon#[27=USB\r\n] 2006.173.17:41:59.20#ibcon#*before write, iclass 17, count 0 2006.173.17:41:59.20#ibcon#enter sib2, iclass 17, count 0 2006.173.17:41:59.20#ibcon#flushed, iclass 17, count 0 2006.173.17:41:59.20#ibcon#about to write, iclass 17, count 0 2006.173.17:41:59.20#ibcon#wrote, iclass 17, count 0 2006.173.17:41:59.20#ibcon#about to read 3, iclass 17, count 0 2006.173.17:41:59.23#ibcon#read 3, iclass 17, count 0 2006.173.17:41:59.23#ibcon#about to read 4, iclass 17, count 0 2006.173.17:41:59.23#ibcon#read 4, iclass 17, count 0 2006.173.17:41:59.23#ibcon#about to read 5, iclass 17, count 0 2006.173.17:41:59.23#ibcon#read 5, iclass 17, count 0 2006.173.17:41:59.23#ibcon#about to read 6, iclass 17, count 0 2006.173.17:41:59.23#ibcon#read 6, iclass 17, count 0 2006.173.17:41:59.23#ibcon#end of sib2, iclass 17, count 0 2006.173.17:41:59.23#ibcon#*after write, iclass 17, count 0 2006.173.17:41:59.23#ibcon#*before return 0, iclass 17, count 0 2006.173.17:41:59.23#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.17:41:59.23#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.17:41:59.23#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.17:41:59.23#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.17:41:59.23$vck44/vblo=8,744.99 2006.173.17:41:59.23#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.17:41:59.23#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.17:41:59.23#ibcon#ireg 17 cls_cnt 0 2006.173.17:41:59.23#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.17:41:59.23#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.17:41:59.23#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.17:41:59.23#ibcon#enter wrdev, iclass 19, count 0 2006.173.17:41:59.23#ibcon#first serial, iclass 19, count 0 2006.173.17:41:59.23#ibcon#enter sib2, iclass 19, count 0 2006.173.17:41:59.23#ibcon#flushed, iclass 19, count 0 2006.173.17:41:59.23#ibcon#about to write, iclass 19, count 0 2006.173.17:41:59.23#ibcon#wrote, iclass 19, count 0 2006.173.17:41:59.23#ibcon#about to read 3, iclass 19, count 0 2006.173.17:41:59.25#ibcon#read 3, iclass 19, count 0 2006.173.17:41:59.25#ibcon#about to read 4, iclass 19, count 0 2006.173.17:41:59.25#ibcon#read 4, iclass 19, count 0 2006.173.17:41:59.25#ibcon#about to read 5, iclass 19, count 0 2006.173.17:41:59.25#ibcon#read 5, iclass 19, count 0 2006.173.17:41:59.25#ibcon#about to read 6, iclass 19, count 0 2006.173.17:41:59.25#ibcon#read 6, iclass 19, count 0 2006.173.17:41:59.25#ibcon#end of sib2, iclass 19, count 0 2006.173.17:41:59.25#ibcon#*mode == 0, iclass 19, count 0 2006.173.17:41:59.25#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.17:41:59.25#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.17:41:59.25#ibcon#*before write, iclass 19, count 0 2006.173.17:41:59.25#ibcon#enter sib2, iclass 19, count 0 2006.173.17:41:59.25#ibcon#flushed, iclass 19, count 0 2006.173.17:41:59.25#ibcon#about to write, iclass 19, count 0 2006.173.17:41:59.25#ibcon#wrote, iclass 19, count 0 2006.173.17:41:59.25#ibcon#about to read 3, iclass 19, count 0 2006.173.17:41:59.29#ibcon#read 3, iclass 19, count 0 2006.173.17:41:59.29#ibcon#about to read 4, iclass 19, count 0 2006.173.17:41:59.29#ibcon#read 4, iclass 19, count 0 2006.173.17:41:59.29#ibcon#about to read 5, iclass 19, count 0 2006.173.17:41:59.29#ibcon#read 5, iclass 19, count 0 2006.173.17:41:59.29#ibcon#about to read 6, iclass 19, count 0 2006.173.17:41:59.29#ibcon#read 6, iclass 19, count 0 2006.173.17:41:59.29#ibcon#end of sib2, iclass 19, count 0 2006.173.17:41:59.29#ibcon#*after write, iclass 19, count 0 2006.173.17:41:59.29#ibcon#*before return 0, iclass 19, count 0 2006.173.17:41:59.29#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.17:41:59.29#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.17:41:59.29#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.17:41:59.29#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.17:41:59.29$vck44/vb=8,4 2006.173.17:41:59.29#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.17:41:59.29#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.17:41:59.29#ibcon#ireg 11 cls_cnt 2 2006.173.17:41:59.29#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.17:41:59.35#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.17:41:59.35#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.17:41:59.35#ibcon#enter wrdev, iclass 21, count 2 2006.173.17:41:59.35#ibcon#first serial, iclass 21, count 2 2006.173.17:41:59.35#ibcon#enter sib2, iclass 21, count 2 2006.173.17:41:59.35#ibcon#flushed, iclass 21, count 2 2006.173.17:41:59.35#ibcon#about to write, iclass 21, count 2 2006.173.17:41:59.35#ibcon#wrote, iclass 21, count 2 2006.173.17:41:59.35#ibcon#about to read 3, iclass 21, count 2 2006.173.17:41:59.37#ibcon#read 3, iclass 21, count 2 2006.173.17:41:59.37#ibcon#about to read 4, iclass 21, count 2 2006.173.17:41:59.37#ibcon#read 4, iclass 21, count 2 2006.173.17:41:59.37#ibcon#about to read 5, iclass 21, count 2 2006.173.17:41:59.37#ibcon#read 5, iclass 21, count 2 2006.173.17:41:59.37#ibcon#about to read 6, iclass 21, count 2 2006.173.17:41:59.37#ibcon#read 6, iclass 21, count 2 2006.173.17:41:59.37#ibcon#end of sib2, iclass 21, count 2 2006.173.17:41:59.37#ibcon#*mode == 0, iclass 21, count 2 2006.173.17:41:59.37#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.17:41:59.37#ibcon#[27=AT08-04\r\n] 2006.173.17:41:59.37#ibcon#*before write, iclass 21, count 2 2006.173.17:41:59.37#ibcon#enter sib2, iclass 21, count 2 2006.173.17:41:59.37#ibcon#flushed, iclass 21, count 2 2006.173.17:41:59.37#ibcon#about to write, iclass 21, count 2 2006.173.17:41:59.37#ibcon#wrote, iclass 21, count 2 2006.173.17:41:59.37#ibcon#about to read 3, iclass 21, count 2 2006.173.17:41:59.40#ibcon#read 3, iclass 21, count 2 2006.173.17:41:59.40#ibcon#about to read 4, iclass 21, count 2 2006.173.17:41:59.40#ibcon#read 4, iclass 21, count 2 2006.173.17:41:59.40#ibcon#about to read 5, iclass 21, count 2 2006.173.17:41:59.40#ibcon#read 5, iclass 21, count 2 2006.173.17:41:59.40#ibcon#about to read 6, iclass 21, count 2 2006.173.17:41:59.40#ibcon#read 6, iclass 21, count 2 2006.173.17:41:59.40#ibcon#end of sib2, iclass 21, count 2 2006.173.17:41:59.40#ibcon#*after write, iclass 21, count 2 2006.173.17:41:59.40#ibcon#*before return 0, iclass 21, count 2 2006.173.17:41:59.40#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.17:41:59.40#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.17:41:59.40#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.17:41:59.40#ibcon#ireg 7 cls_cnt 0 2006.173.17:41:59.40#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.17:41:59.52#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.17:41:59.52#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.17:41:59.52#ibcon#enter wrdev, iclass 21, count 0 2006.173.17:41:59.52#ibcon#first serial, iclass 21, count 0 2006.173.17:41:59.52#ibcon#enter sib2, iclass 21, count 0 2006.173.17:41:59.52#ibcon#flushed, iclass 21, count 0 2006.173.17:41:59.52#ibcon#about to write, iclass 21, count 0 2006.173.17:41:59.52#ibcon#wrote, iclass 21, count 0 2006.173.17:41:59.52#ibcon#about to read 3, iclass 21, count 0 2006.173.17:41:59.54#ibcon#read 3, iclass 21, count 0 2006.173.17:41:59.54#ibcon#about to read 4, iclass 21, count 0 2006.173.17:41:59.54#ibcon#read 4, iclass 21, count 0 2006.173.17:41:59.54#ibcon#about to read 5, iclass 21, count 0 2006.173.17:41:59.54#ibcon#read 5, iclass 21, count 0 2006.173.17:41:59.54#ibcon#about to read 6, iclass 21, count 0 2006.173.17:41:59.54#ibcon#read 6, iclass 21, count 0 2006.173.17:41:59.54#ibcon#end of sib2, iclass 21, count 0 2006.173.17:41:59.54#ibcon#*mode == 0, iclass 21, count 0 2006.173.17:41:59.54#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.17:41:59.54#ibcon#[27=USB\r\n] 2006.173.17:41:59.54#ibcon#*before write, iclass 21, count 0 2006.173.17:41:59.54#ibcon#enter sib2, iclass 21, count 0 2006.173.17:41:59.54#ibcon#flushed, iclass 21, count 0 2006.173.17:41:59.54#ibcon#about to write, iclass 21, count 0 2006.173.17:41:59.54#ibcon#wrote, iclass 21, count 0 2006.173.17:41:59.54#ibcon#about to read 3, iclass 21, count 0 2006.173.17:41:59.57#ibcon#read 3, iclass 21, count 0 2006.173.17:41:59.57#ibcon#about to read 4, iclass 21, count 0 2006.173.17:41:59.57#ibcon#read 4, iclass 21, count 0 2006.173.17:41:59.57#ibcon#about to read 5, iclass 21, count 0 2006.173.17:41:59.57#ibcon#read 5, iclass 21, count 0 2006.173.17:41:59.57#ibcon#about to read 6, iclass 21, count 0 2006.173.17:41:59.57#ibcon#read 6, iclass 21, count 0 2006.173.17:41:59.57#ibcon#end of sib2, iclass 21, count 0 2006.173.17:41:59.57#ibcon#*after write, iclass 21, count 0 2006.173.17:41:59.57#ibcon#*before return 0, iclass 21, count 0 2006.173.17:41:59.57#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.17:41:59.57#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.17:41:59.57#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.17:41:59.57#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.17:41:59.57$vck44/vabw=wide 2006.173.17:41:59.57#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.17:41:59.57#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.17:41:59.57#ibcon#ireg 8 cls_cnt 0 2006.173.17:41:59.57#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.17:41:59.57#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.17:41:59.57#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.17:41:59.57#ibcon#enter wrdev, iclass 23, count 0 2006.173.17:41:59.57#ibcon#first serial, iclass 23, count 0 2006.173.17:41:59.57#ibcon#enter sib2, iclass 23, count 0 2006.173.17:41:59.57#ibcon#flushed, iclass 23, count 0 2006.173.17:41:59.57#ibcon#about to write, iclass 23, count 0 2006.173.17:41:59.57#ibcon#wrote, iclass 23, count 0 2006.173.17:41:59.57#ibcon#about to read 3, iclass 23, count 0 2006.173.17:41:59.59#ibcon#read 3, iclass 23, count 0 2006.173.17:41:59.59#ibcon#about to read 4, iclass 23, count 0 2006.173.17:41:59.59#ibcon#read 4, iclass 23, count 0 2006.173.17:41:59.59#ibcon#about to read 5, iclass 23, count 0 2006.173.17:41:59.59#ibcon#read 5, iclass 23, count 0 2006.173.17:41:59.59#ibcon#about to read 6, iclass 23, count 0 2006.173.17:41:59.59#ibcon#read 6, iclass 23, count 0 2006.173.17:41:59.59#ibcon#end of sib2, iclass 23, count 0 2006.173.17:41:59.59#ibcon#*mode == 0, iclass 23, count 0 2006.173.17:41:59.59#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.17:41:59.59#ibcon#[25=BW32\r\n] 2006.173.17:41:59.59#ibcon#*before write, iclass 23, count 0 2006.173.17:41:59.59#ibcon#enter sib2, iclass 23, count 0 2006.173.17:41:59.59#ibcon#flushed, iclass 23, count 0 2006.173.17:41:59.59#ibcon#about to write, iclass 23, count 0 2006.173.17:41:59.59#ibcon#wrote, iclass 23, count 0 2006.173.17:41:59.59#ibcon#about to read 3, iclass 23, count 0 2006.173.17:41:59.62#ibcon#read 3, iclass 23, count 0 2006.173.17:41:59.62#ibcon#about to read 4, iclass 23, count 0 2006.173.17:41:59.62#ibcon#read 4, iclass 23, count 0 2006.173.17:41:59.62#ibcon#about to read 5, iclass 23, count 0 2006.173.17:41:59.62#ibcon#read 5, iclass 23, count 0 2006.173.17:41:59.62#ibcon#about to read 6, iclass 23, count 0 2006.173.17:41:59.62#ibcon#read 6, iclass 23, count 0 2006.173.17:41:59.62#ibcon#end of sib2, iclass 23, count 0 2006.173.17:41:59.62#ibcon#*after write, iclass 23, count 0 2006.173.17:41:59.62#ibcon#*before return 0, iclass 23, count 0 2006.173.17:41:59.62#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.17:41:59.62#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.17:41:59.62#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.17:41:59.62#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.17:41:59.62$vck44/vbbw=wide 2006.173.17:41:59.62#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.17:41:59.62#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.17:41:59.62#ibcon#ireg 8 cls_cnt 0 2006.173.17:41:59.62#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.17:41:59.69#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.17:41:59.69#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.17:41:59.69#ibcon#enter wrdev, iclass 25, count 0 2006.173.17:41:59.69#ibcon#first serial, iclass 25, count 0 2006.173.17:41:59.69#ibcon#enter sib2, iclass 25, count 0 2006.173.17:41:59.69#ibcon#flushed, iclass 25, count 0 2006.173.17:41:59.69#ibcon#about to write, iclass 25, count 0 2006.173.17:41:59.69#ibcon#wrote, iclass 25, count 0 2006.173.17:41:59.69#ibcon#about to read 3, iclass 25, count 0 2006.173.17:41:59.71#ibcon#read 3, iclass 25, count 0 2006.173.17:41:59.71#ibcon#about to read 4, iclass 25, count 0 2006.173.17:41:59.71#ibcon#read 4, iclass 25, count 0 2006.173.17:41:59.71#ibcon#about to read 5, iclass 25, count 0 2006.173.17:41:59.71#ibcon#read 5, iclass 25, count 0 2006.173.17:41:59.71#ibcon#about to read 6, iclass 25, count 0 2006.173.17:41:59.71#ibcon#read 6, iclass 25, count 0 2006.173.17:41:59.71#ibcon#end of sib2, iclass 25, count 0 2006.173.17:41:59.71#ibcon#*mode == 0, iclass 25, count 0 2006.173.17:41:59.71#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.17:41:59.71#ibcon#[27=BW32\r\n] 2006.173.17:41:59.71#ibcon#*before write, iclass 25, count 0 2006.173.17:41:59.71#ibcon#enter sib2, iclass 25, count 0 2006.173.17:41:59.71#ibcon#flushed, iclass 25, count 0 2006.173.17:41:59.71#ibcon#about to write, iclass 25, count 0 2006.173.17:41:59.71#ibcon#wrote, iclass 25, count 0 2006.173.17:41:59.71#ibcon#about to read 3, iclass 25, count 0 2006.173.17:41:59.74#ibcon#read 3, iclass 25, count 0 2006.173.17:41:59.74#ibcon#about to read 4, iclass 25, count 0 2006.173.17:41:59.74#ibcon#read 4, iclass 25, count 0 2006.173.17:41:59.74#ibcon#about to read 5, iclass 25, count 0 2006.173.17:41:59.74#ibcon#read 5, iclass 25, count 0 2006.173.17:41:59.74#ibcon#about to read 6, iclass 25, count 0 2006.173.17:41:59.74#ibcon#read 6, iclass 25, count 0 2006.173.17:41:59.74#ibcon#end of sib2, iclass 25, count 0 2006.173.17:41:59.74#ibcon#*after write, iclass 25, count 0 2006.173.17:41:59.74#ibcon#*before return 0, iclass 25, count 0 2006.173.17:41:59.74#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.17:41:59.74#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.17:41:59.74#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.17:41:59.74#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.17:41:59.74$setupk4/ifdk4 2006.173.17:41:59.74$ifdk4/lo= 2006.173.17:41:59.74$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.17:41:59.74$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.17:41:59.74$ifdk4/patch= 2006.173.17:41:59.74$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.17:41:59.74$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.17:41:59.74$setupk4/!*+20s 2006.173.17:42:02.31#abcon#<5=/14 1.1 2.3 20.191001002.3\r\n> 2006.173.17:42:02.33#abcon#{5=INTERFACE CLEAR} 2006.173.17:42:02.39#abcon#[5=S1D000X0/0*\r\n] 2006.173.17:42:08.14#trakl#Source acquired 2006.173.17:42:10.14#flagr#flagr/antenna,acquired 2006.173.17:42:12.48#abcon#<5=/14 1.1 2.3 20.191001002.2\r\n> 2006.173.17:42:12.50#abcon#{5=INTERFACE CLEAR} 2006.173.17:42:12.56#abcon#[5=S1D000X0/0*\r\n] 2006.173.17:42:14.22$setupk4/"tpicd 2006.173.17:42:14.22$setupk4/echo=off 2006.173.17:42:14.22$setupk4/xlog=off 2006.173.17:42:14.22:!2006.173.17:42:09 2006.173.17:42:14.22:preob 2006.173.17:42:15.14/onsource/TRACKING 2006.173.17:42:15.14:!2006.173.17:42:19 2006.173.17:42:19.00:"tape 2006.173.17:42:19.00:"st=record 2006.173.17:42:19.00:data_valid=on 2006.173.17:42:19.00:midob 2006.173.17:42:19.14/onsource/TRACKING 2006.173.17:42:19.14/wx/20.19,1002.2,100 2006.173.17:42:19.24/cable/+6.5127E-03 2006.173.17:42:20.33/va/01,07,usb,yes,34,37 2006.173.17:42:20.33/va/02,06,usb,yes,34,35 2006.173.17:42:20.33/va/03,05,usb,yes,43,45 2006.173.17:42:20.33/va/04,06,usb,yes,35,36 2006.173.17:42:20.33/va/05,04,usb,yes,27,28 2006.173.17:42:20.33/va/06,03,usb,yes,38,38 2006.173.17:42:20.33/va/07,04,usb,yes,31,32 2006.173.17:42:20.33/va/08,04,usb,yes,26,32 2006.173.17:42:20.56/valo/01,524.99,yes,locked 2006.173.17:42:20.56/valo/02,534.99,yes,locked 2006.173.17:42:20.56/valo/03,564.99,yes,locked 2006.173.17:42:20.56/valo/04,624.99,yes,locked 2006.173.17:42:20.56/valo/05,734.99,yes,locked 2006.173.17:42:20.56/valo/06,814.99,yes,locked 2006.173.17:42:20.56/valo/07,864.99,yes,locked 2006.173.17:42:20.56/valo/08,884.99,yes,locked 2006.173.17:42:21.65/vb/01,04,usb,yes,29,27 2006.173.17:42:21.65/vb/02,04,usb,yes,31,31 2006.173.17:42:21.65/vb/03,04,usb,yes,28,31 2006.173.17:42:21.65/vb/04,04,usb,yes,32,31 2006.173.17:42:21.65/vb/05,04,usb,yes,25,27 2006.173.17:42:21.65/vb/06,04,usb,yes,29,26 2006.173.17:42:21.65/vb/07,04,usb,yes,29,29 2006.173.17:42:21.65/vb/08,04,usb,yes,27,30 2006.173.17:42:21.89/vblo/01,629.99,yes,locked 2006.173.17:42:21.89/vblo/02,634.99,yes,locked 2006.173.17:42:21.89/vblo/03,649.99,yes,locked 2006.173.17:42:21.89/vblo/04,679.99,yes,locked 2006.173.17:42:21.89/vblo/05,709.99,yes,locked 2006.173.17:42:21.89/vblo/06,719.99,yes,locked 2006.173.17:42:21.89/vblo/07,734.99,yes,locked 2006.173.17:42:21.89/vblo/08,744.99,yes,locked 2006.173.17:42:22.04/vabw/8 2006.173.17:42:22.19/vbbw/8 2006.173.17:42:22.28/xfe/off,on,15.0 2006.173.17:42:22.67/ifatt/23,28,28,28 2006.173.17:42:23.07/fmout-gps/S +4.00E-07 2006.173.17:42:23.11:!2006.173.17:44:19 2006.173.17:44:19.01:data_valid=off 2006.173.17:44:19.01:"et 2006.173.17:44:19.02:!+3s 2006.173.17:44:22.03:"tape 2006.173.17:44:22.03:postob 2006.173.17:44:22.17/cable/+6.5129E-03 2006.173.17:44:22.17/wx/20.18,1002.2,100 2006.173.17:44:22.23/fmout-gps/S +4.00E-07 2006.173.17:44:22.23:scan_name=173-1749,jd0606,40 2006.173.17:44:22.23:source=1921-293,192451.06,-291430.1,2000.0,ccw 2006.173.17:44:23.14#flagr#flagr/antenna,new-source 2006.173.17:44:23.14:checkk5 2006.173.17:44:23.58/chk_autoobs//k5ts1/ autoobs is running! 2006.173.17:44:23.98/chk_autoobs//k5ts2/ autoobs is running! 2006.173.17:44:24.39/chk_autoobs//k5ts3/ autoobs is running! 2006.173.17:44:24.77/chk_autoobs//k5ts4/ autoobs is running! 2006.173.17:44:25.16/chk_obsdata//k5ts1/T1731742??a.dat file size is correct (nominal:480MB, actual:476MB). 2006.173.17:44:25.57/chk_obsdata//k5ts2/T1731742??b.dat file size is correct (nominal:480MB, actual:476MB). 2006.173.17:44:25.95/chk_obsdata//k5ts3/T1731742??c.dat file size is correct (nominal:480MB, actual:476MB). 2006.173.17:44:26.37/chk_obsdata//k5ts4/T1731742??d.dat file size is correct (nominal:480MB, actual:476MB). 2006.173.17:44:27.10/k5log//k5ts1_log_newline 2006.173.17:44:27.83/k5log//k5ts2_log_newline 2006.173.17:44:28.53/k5log//k5ts3_log_newline 2006.173.17:44:29.24/k5log//k5ts4_log_newline 2006.173.17:44:29.26/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.17:44:29.26:setupk4=1 2006.173.17:44:29.26$setupk4/echo=on 2006.173.17:44:29.26$setupk4/pcalon 2006.173.17:44:29.26$pcalon/"no phase cal control is implemented here 2006.173.17:44:29.26$setupk4/"tpicd=stop 2006.173.17:44:29.26$setupk4/"rec=synch_on 2006.173.17:44:29.26$setupk4/"rec_mode=128 2006.173.17:44:29.26$setupk4/!* 2006.173.17:44:29.26$setupk4/recpk4 2006.173.17:44:29.26$recpk4/recpatch= 2006.173.17:44:29.26$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.17:44:29.26$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.17:44:29.26$setupk4/vck44 2006.173.17:44:29.26$vck44/valo=1,524.99 2006.173.17:44:29.26#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.17:44:29.26#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.17:44:29.26#ibcon#ireg 17 cls_cnt 0 2006.173.17:44:29.26#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.17:44:29.26#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.17:44:29.26#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.17:44:29.26#ibcon#enter wrdev, iclass 18, count 0 2006.173.17:44:29.26#ibcon#first serial, iclass 18, count 0 2006.173.17:44:29.26#ibcon#enter sib2, iclass 18, count 0 2006.173.17:44:29.26#ibcon#flushed, iclass 18, count 0 2006.173.17:44:29.26#ibcon#about to write, iclass 18, count 0 2006.173.17:44:29.26#ibcon#wrote, iclass 18, count 0 2006.173.17:44:29.26#ibcon#about to read 3, iclass 18, count 0 2006.173.17:44:29.28#ibcon#read 3, iclass 18, count 0 2006.173.17:44:29.28#ibcon#about to read 4, iclass 18, count 0 2006.173.17:44:29.28#ibcon#read 4, iclass 18, count 0 2006.173.17:44:29.28#ibcon#about to read 5, iclass 18, count 0 2006.173.17:44:29.28#ibcon#read 5, iclass 18, count 0 2006.173.17:44:29.28#ibcon#about to read 6, iclass 18, count 0 2006.173.17:44:29.28#ibcon#read 6, iclass 18, count 0 2006.173.17:44:29.28#ibcon#end of sib2, iclass 18, count 0 2006.173.17:44:29.28#ibcon#*mode == 0, iclass 18, count 0 2006.173.17:44:29.28#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.17:44:29.28#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.17:44:29.28#ibcon#*before write, iclass 18, count 0 2006.173.17:44:29.28#ibcon#enter sib2, iclass 18, count 0 2006.173.17:44:29.28#ibcon#flushed, iclass 18, count 0 2006.173.17:44:29.28#ibcon#about to write, iclass 18, count 0 2006.173.17:44:29.28#ibcon#wrote, iclass 18, count 0 2006.173.17:44:29.28#ibcon#about to read 3, iclass 18, count 0 2006.173.17:44:29.33#ibcon#read 3, iclass 18, count 0 2006.173.17:44:29.33#ibcon#about to read 4, iclass 18, count 0 2006.173.17:44:29.33#ibcon#read 4, iclass 18, count 0 2006.173.17:44:29.33#ibcon#about to read 5, iclass 18, count 0 2006.173.17:44:29.33#ibcon#read 5, iclass 18, count 0 2006.173.17:44:29.33#ibcon#about to read 6, iclass 18, count 0 2006.173.17:44:29.33#ibcon#read 6, iclass 18, count 0 2006.173.17:44:29.33#ibcon#end of sib2, iclass 18, count 0 2006.173.17:44:29.33#ibcon#*after write, iclass 18, count 0 2006.173.17:44:29.33#ibcon#*before return 0, iclass 18, count 0 2006.173.17:44:29.33#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.17:44:29.33#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.17:44:29.33#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.17:44:29.33#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.17:44:29.33$vck44/va=1,7 2006.173.17:44:29.33#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.17:44:29.33#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.17:44:29.33#ibcon#ireg 11 cls_cnt 2 2006.173.17:44:29.33#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.17:44:29.33#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.17:44:29.33#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.17:44:29.33#ibcon#enter wrdev, iclass 20, count 2 2006.173.17:44:29.33#ibcon#first serial, iclass 20, count 2 2006.173.17:44:29.33#ibcon#enter sib2, iclass 20, count 2 2006.173.17:44:29.33#ibcon#flushed, iclass 20, count 2 2006.173.17:44:29.33#ibcon#about to write, iclass 20, count 2 2006.173.17:44:29.33#ibcon#wrote, iclass 20, count 2 2006.173.17:44:29.33#ibcon#about to read 3, iclass 20, count 2 2006.173.17:44:29.35#ibcon#read 3, iclass 20, count 2 2006.173.17:44:29.35#ibcon#about to read 4, iclass 20, count 2 2006.173.17:44:29.35#ibcon#read 4, iclass 20, count 2 2006.173.17:44:29.35#ibcon#about to read 5, iclass 20, count 2 2006.173.17:44:29.35#ibcon#read 5, iclass 20, count 2 2006.173.17:44:29.35#ibcon#about to read 6, iclass 20, count 2 2006.173.17:44:29.35#ibcon#read 6, iclass 20, count 2 2006.173.17:44:29.35#ibcon#end of sib2, iclass 20, count 2 2006.173.17:44:29.35#ibcon#*mode == 0, iclass 20, count 2 2006.173.17:44:29.35#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.17:44:29.35#ibcon#[25=AT01-07\r\n] 2006.173.17:44:29.35#ibcon#*before write, iclass 20, count 2 2006.173.17:44:29.35#ibcon#enter sib2, iclass 20, count 2 2006.173.17:44:29.35#ibcon#flushed, iclass 20, count 2 2006.173.17:44:29.35#ibcon#about to write, iclass 20, count 2 2006.173.17:44:29.35#ibcon#wrote, iclass 20, count 2 2006.173.17:44:29.35#ibcon#about to read 3, iclass 20, count 2 2006.173.17:44:29.38#ibcon#read 3, iclass 20, count 2 2006.173.17:44:29.38#ibcon#about to read 4, iclass 20, count 2 2006.173.17:44:29.38#ibcon#read 4, iclass 20, count 2 2006.173.17:44:29.38#ibcon#about to read 5, iclass 20, count 2 2006.173.17:44:29.38#ibcon#read 5, iclass 20, count 2 2006.173.17:44:29.38#ibcon#about to read 6, iclass 20, count 2 2006.173.17:44:29.38#ibcon#read 6, iclass 20, count 2 2006.173.17:44:29.38#ibcon#end of sib2, iclass 20, count 2 2006.173.17:44:29.38#ibcon#*after write, iclass 20, count 2 2006.173.17:44:29.38#ibcon#*before return 0, iclass 20, count 2 2006.173.17:44:29.38#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.17:44:29.38#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.17:44:29.38#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.17:44:29.38#ibcon#ireg 7 cls_cnt 0 2006.173.17:44:29.38#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.17:44:29.50#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.17:44:29.50#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.17:44:29.50#ibcon#enter wrdev, iclass 20, count 0 2006.173.17:44:29.50#ibcon#first serial, iclass 20, count 0 2006.173.17:44:29.50#ibcon#enter sib2, iclass 20, count 0 2006.173.17:44:29.50#ibcon#flushed, iclass 20, count 0 2006.173.17:44:29.50#ibcon#about to write, iclass 20, count 0 2006.173.17:44:29.50#ibcon#wrote, iclass 20, count 0 2006.173.17:44:29.50#ibcon#about to read 3, iclass 20, count 0 2006.173.17:44:29.52#ibcon#read 3, iclass 20, count 0 2006.173.17:44:29.52#ibcon#about to read 4, iclass 20, count 0 2006.173.17:44:29.52#ibcon#read 4, iclass 20, count 0 2006.173.17:44:29.52#ibcon#about to read 5, iclass 20, count 0 2006.173.17:44:29.52#ibcon#read 5, iclass 20, count 0 2006.173.17:44:29.52#ibcon#about to read 6, iclass 20, count 0 2006.173.17:44:29.52#ibcon#read 6, iclass 20, count 0 2006.173.17:44:29.52#ibcon#end of sib2, iclass 20, count 0 2006.173.17:44:29.52#ibcon#*mode == 0, iclass 20, count 0 2006.173.17:44:29.52#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.17:44:29.52#ibcon#[25=USB\r\n] 2006.173.17:44:29.52#ibcon#*before write, iclass 20, count 0 2006.173.17:44:29.52#ibcon#enter sib2, iclass 20, count 0 2006.173.17:44:29.52#ibcon#flushed, iclass 20, count 0 2006.173.17:44:29.52#ibcon#about to write, iclass 20, count 0 2006.173.17:44:29.52#ibcon#wrote, iclass 20, count 0 2006.173.17:44:29.52#ibcon#about to read 3, iclass 20, count 0 2006.173.17:44:29.55#ibcon#read 3, iclass 20, count 0 2006.173.17:44:29.55#ibcon#about to read 4, iclass 20, count 0 2006.173.17:44:29.55#ibcon#read 4, iclass 20, count 0 2006.173.17:44:29.55#ibcon#about to read 5, iclass 20, count 0 2006.173.17:44:29.55#ibcon#read 5, iclass 20, count 0 2006.173.17:44:29.55#ibcon#about to read 6, iclass 20, count 0 2006.173.17:44:29.55#ibcon#read 6, iclass 20, count 0 2006.173.17:44:29.55#ibcon#end of sib2, iclass 20, count 0 2006.173.17:44:29.55#ibcon#*after write, iclass 20, count 0 2006.173.17:44:29.55#ibcon#*before return 0, iclass 20, count 0 2006.173.17:44:29.55#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.17:44:29.55#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.17:44:29.55#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.17:44:29.55#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.17:44:29.55$vck44/valo=2,534.99 2006.173.17:44:29.55#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.17:44:29.55#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.17:44:29.55#ibcon#ireg 17 cls_cnt 0 2006.173.17:44:29.55#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.17:44:29.55#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.17:44:29.55#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.17:44:29.55#ibcon#enter wrdev, iclass 22, count 0 2006.173.17:44:29.55#ibcon#first serial, iclass 22, count 0 2006.173.17:44:29.55#ibcon#enter sib2, iclass 22, count 0 2006.173.17:44:29.55#ibcon#flushed, iclass 22, count 0 2006.173.17:44:29.55#ibcon#about to write, iclass 22, count 0 2006.173.17:44:29.55#ibcon#wrote, iclass 22, count 0 2006.173.17:44:29.55#ibcon#about to read 3, iclass 22, count 0 2006.173.17:44:29.57#ibcon#read 3, iclass 22, count 0 2006.173.17:44:29.57#ibcon#about to read 4, iclass 22, count 0 2006.173.17:44:29.57#ibcon#read 4, iclass 22, count 0 2006.173.17:44:29.57#ibcon#about to read 5, iclass 22, count 0 2006.173.17:44:29.57#ibcon#read 5, iclass 22, count 0 2006.173.17:44:29.57#ibcon#about to read 6, iclass 22, count 0 2006.173.17:44:29.57#ibcon#read 6, iclass 22, count 0 2006.173.17:44:29.57#ibcon#end of sib2, iclass 22, count 0 2006.173.17:44:29.57#ibcon#*mode == 0, iclass 22, count 0 2006.173.17:44:29.57#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.17:44:29.57#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.17:44:29.57#ibcon#*before write, iclass 22, count 0 2006.173.17:44:29.57#ibcon#enter sib2, iclass 22, count 0 2006.173.17:44:29.57#ibcon#flushed, iclass 22, count 0 2006.173.17:44:29.57#ibcon#about to write, iclass 22, count 0 2006.173.17:44:29.57#ibcon#wrote, iclass 22, count 0 2006.173.17:44:29.57#ibcon#about to read 3, iclass 22, count 0 2006.173.17:44:29.61#ibcon#read 3, iclass 22, count 0 2006.173.17:44:29.61#ibcon#about to read 4, iclass 22, count 0 2006.173.17:44:29.61#ibcon#read 4, iclass 22, count 0 2006.173.17:44:29.61#ibcon#about to read 5, iclass 22, count 0 2006.173.17:44:29.61#ibcon#read 5, iclass 22, count 0 2006.173.17:44:29.61#ibcon#about to read 6, iclass 22, count 0 2006.173.17:44:29.61#ibcon#read 6, iclass 22, count 0 2006.173.17:44:29.61#ibcon#end of sib2, iclass 22, count 0 2006.173.17:44:29.61#ibcon#*after write, iclass 22, count 0 2006.173.17:44:29.61#ibcon#*before return 0, iclass 22, count 0 2006.173.17:44:29.61#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.17:44:29.61#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.17:44:29.61#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.17:44:29.61#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.17:44:29.61$vck44/va=2,6 2006.173.17:44:29.61#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.17:44:29.61#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.17:44:29.61#ibcon#ireg 11 cls_cnt 2 2006.173.17:44:29.61#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.17:44:29.67#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.17:44:29.67#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.17:44:29.67#ibcon#enter wrdev, iclass 24, count 2 2006.173.17:44:29.67#ibcon#first serial, iclass 24, count 2 2006.173.17:44:29.67#ibcon#enter sib2, iclass 24, count 2 2006.173.17:44:29.67#ibcon#flushed, iclass 24, count 2 2006.173.17:44:29.67#ibcon#about to write, iclass 24, count 2 2006.173.17:44:29.67#ibcon#wrote, iclass 24, count 2 2006.173.17:44:29.67#ibcon#about to read 3, iclass 24, count 2 2006.173.17:44:29.69#ibcon#read 3, iclass 24, count 2 2006.173.17:44:29.69#ibcon#about to read 4, iclass 24, count 2 2006.173.17:44:29.69#ibcon#read 4, iclass 24, count 2 2006.173.17:44:29.69#ibcon#about to read 5, iclass 24, count 2 2006.173.17:44:29.69#ibcon#read 5, iclass 24, count 2 2006.173.17:44:29.69#ibcon#about to read 6, iclass 24, count 2 2006.173.17:44:29.69#ibcon#read 6, iclass 24, count 2 2006.173.17:44:29.69#ibcon#end of sib2, iclass 24, count 2 2006.173.17:44:29.69#ibcon#*mode == 0, iclass 24, count 2 2006.173.17:44:29.69#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.17:44:29.69#ibcon#[25=AT02-06\r\n] 2006.173.17:44:29.69#ibcon#*before write, iclass 24, count 2 2006.173.17:44:29.69#ibcon#enter sib2, iclass 24, count 2 2006.173.17:44:29.69#ibcon#flushed, iclass 24, count 2 2006.173.17:44:29.69#ibcon#about to write, iclass 24, count 2 2006.173.17:44:29.69#ibcon#wrote, iclass 24, count 2 2006.173.17:44:29.69#ibcon#about to read 3, iclass 24, count 2 2006.173.17:44:29.72#ibcon#read 3, iclass 24, count 2 2006.173.17:44:29.72#ibcon#about to read 4, iclass 24, count 2 2006.173.17:44:29.72#ibcon#read 4, iclass 24, count 2 2006.173.17:44:29.72#ibcon#about to read 5, iclass 24, count 2 2006.173.17:44:29.72#ibcon#read 5, iclass 24, count 2 2006.173.17:44:29.72#ibcon#about to read 6, iclass 24, count 2 2006.173.17:44:29.72#ibcon#read 6, iclass 24, count 2 2006.173.17:44:29.72#ibcon#end of sib2, iclass 24, count 2 2006.173.17:44:29.72#ibcon#*after write, iclass 24, count 2 2006.173.17:44:29.72#ibcon#*before return 0, iclass 24, count 2 2006.173.17:44:29.72#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.17:44:29.72#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.17:44:29.72#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.17:44:29.72#ibcon#ireg 7 cls_cnt 0 2006.173.17:44:29.72#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.17:44:29.84#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.17:44:29.84#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.17:44:29.84#ibcon#enter wrdev, iclass 24, count 0 2006.173.17:44:29.84#ibcon#first serial, iclass 24, count 0 2006.173.17:44:29.84#ibcon#enter sib2, iclass 24, count 0 2006.173.17:44:29.84#ibcon#flushed, iclass 24, count 0 2006.173.17:44:29.84#ibcon#about to write, iclass 24, count 0 2006.173.17:44:29.84#ibcon#wrote, iclass 24, count 0 2006.173.17:44:29.84#ibcon#about to read 3, iclass 24, count 0 2006.173.17:44:29.86#ibcon#read 3, iclass 24, count 0 2006.173.17:44:29.86#ibcon#about to read 4, iclass 24, count 0 2006.173.17:44:29.86#ibcon#read 4, iclass 24, count 0 2006.173.17:44:29.86#ibcon#about to read 5, iclass 24, count 0 2006.173.17:44:29.86#ibcon#read 5, iclass 24, count 0 2006.173.17:44:29.86#ibcon#about to read 6, iclass 24, count 0 2006.173.17:44:29.86#ibcon#read 6, iclass 24, count 0 2006.173.17:44:29.86#ibcon#end of sib2, iclass 24, count 0 2006.173.17:44:29.86#ibcon#*mode == 0, iclass 24, count 0 2006.173.17:44:29.86#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.17:44:29.86#ibcon#[25=USB\r\n] 2006.173.17:44:29.86#ibcon#*before write, iclass 24, count 0 2006.173.17:44:29.86#ibcon#enter sib2, iclass 24, count 0 2006.173.17:44:29.86#ibcon#flushed, iclass 24, count 0 2006.173.17:44:29.86#ibcon#about to write, iclass 24, count 0 2006.173.17:44:29.86#ibcon#wrote, iclass 24, count 0 2006.173.17:44:29.86#ibcon#about to read 3, iclass 24, count 0 2006.173.17:44:29.89#ibcon#read 3, iclass 24, count 0 2006.173.17:44:29.89#ibcon#about to read 4, iclass 24, count 0 2006.173.17:44:29.89#ibcon#read 4, iclass 24, count 0 2006.173.17:44:29.89#ibcon#about to read 5, iclass 24, count 0 2006.173.17:44:29.89#ibcon#read 5, iclass 24, count 0 2006.173.17:44:29.89#ibcon#about to read 6, iclass 24, count 0 2006.173.17:44:29.89#ibcon#read 6, iclass 24, count 0 2006.173.17:44:29.89#ibcon#end of sib2, iclass 24, count 0 2006.173.17:44:29.89#ibcon#*after write, iclass 24, count 0 2006.173.17:44:29.89#ibcon#*before return 0, iclass 24, count 0 2006.173.17:44:29.89#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.17:44:29.89#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.17:44:29.89#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.17:44:29.89#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.17:44:29.89$vck44/valo=3,564.99 2006.173.17:44:29.89#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.17:44:29.89#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.17:44:29.89#ibcon#ireg 17 cls_cnt 0 2006.173.17:44:29.89#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.17:44:29.89#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.17:44:29.89#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.17:44:29.89#ibcon#enter wrdev, iclass 26, count 0 2006.173.17:44:29.89#ibcon#first serial, iclass 26, count 0 2006.173.17:44:29.89#ibcon#enter sib2, iclass 26, count 0 2006.173.17:44:29.89#ibcon#flushed, iclass 26, count 0 2006.173.17:44:29.89#ibcon#about to write, iclass 26, count 0 2006.173.17:44:29.89#ibcon#wrote, iclass 26, count 0 2006.173.17:44:29.89#ibcon#about to read 3, iclass 26, count 0 2006.173.17:44:29.91#ibcon#read 3, iclass 26, count 0 2006.173.17:44:29.91#ibcon#about to read 4, iclass 26, count 0 2006.173.17:44:29.91#ibcon#read 4, iclass 26, count 0 2006.173.17:44:29.91#ibcon#about to read 5, iclass 26, count 0 2006.173.17:44:29.91#ibcon#read 5, iclass 26, count 0 2006.173.17:44:29.91#ibcon#about to read 6, iclass 26, count 0 2006.173.17:44:29.91#ibcon#read 6, iclass 26, count 0 2006.173.17:44:29.91#ibcon#end of sib2, iclass 26, count 0 2006.173.17:44:29.91#ibcon#*mode == 0, iclass 26, count 0 2006.173.17:44:29.91#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.17:44:29.91#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.17:44:29.91#ibcon#*before write, iclass 26, count 0 2006.173.17:44:29.91#ibcon#enter sib2, iclass 26, count 0 2006.173.17:44:29.91#ibcon#flushed, iclass 26, count 0 2006.173.17:44:29.91#ibcon#about to write, iclass 26, count 0 2006.173.17:44:29.91#ibcon#wrote, iclass 26, count 0 2006.173.17:44:29.91#ibcon#about to read 3, iclass 26, count 0 2006.173.17:44:29.95#ibcon#read 3, iclass 26, count 0 2006.173.17:44:29.95#ibcon#about to read 4, iclass 26, count 0 2006.173.17:44:29.95#ibcon#read 4, iclass 26, count 0 2006.173.17:44:29.95#ibcon#about to read 5, iclass 26, count 0 2006.173.17:44:29.95#ibcon#read 5, iclass 26, count 0 2006.173.17:44:29.95#ibcon#about to read 6, iclass 26, count 0 2006.173.17:44:29.95#ibcon#read 6, iclass 26, count 0 2006.173.17:44:29.95#ibcon#end of sib2, iclass 26, count 0 2006.173.17:44:29.95#ibcon#*after write, iclass 26, count 0 2006.173.17:44:29.95#ibcon#*before return 0, iclass 26, count 0 2006.173.17:44:29.95#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.17:44:29.95#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.17:44:29.95#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.17:44:29.95#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.17:44:29.95$vck44/va=3,5 2006.173.17:44:29.95#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.17:44:29.95#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.17:44:29.95#ibcon#ireg 11 cls_cnt 2 2006.173.17:44:29.95#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.17:44:30.01#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.17:44:30.01#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.17:44:30.01#ibcon#enter wrdev, iclass 28, count 2 2006.173.17:44:30.01#ibcon#first serial, iclass 28, count 2 2006.173.17:44:30.01#ibcon#enter sib2, iclass 28, count 2 2006.173.17:44:30.01#ibcon#flushed, iclass 28, count 2 2006.173.17:44:30.01#ibcon#about to write, iclass 28, count 2 2006.173.17:44:30.01#ibcon#wrote, iclass 28, count 2 2006.173.17:44:30.01#ibcon#about to read 3, iclass 28, count 2 2006.173.17:44:30.03#ibcon#read 3, iclass 28, count 2 2006.173.17:44:30.03#ibcon#about to read 4, iclass 28, count 2 2006.173.17:44:30.03#ibcon#read 4, iclass 28, count 2 2006.173.17:44:30.03#ibcon#about to read 5, iclass 28, count 2 2006.173.17:44:30.03#ibcon#read 5, iclass 28, count 2 2006.173.17:44:30.03#ibcon#about to read 6, iclass 28, count 2 2006.173.17:44:30.03#ibcon#read 6, iclass 28, count 2 2006.173.17:44:30.03#ibcon#end of sib2, iclass 28, count 2 2006.173.17:44:30.03#ibcon#*mode == 0, iclass 28, count 2 2006.173.17:44:30.03#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.17:44:30.03#ibcon#[25=AT03-05\r\n] 2006.173.17:44:30.03#ibcon#*before write, iclass 28, count 2 2006.173.17:44:30.03#ibcon#enter sib2, iclass 28, count 2 2006.173.17:44:30.03#ibcon#flushed, iclass 28, count 2 2006.173.17:44:30.03#ibcon#about to write, iclass 28, count 2 2006.173.17:44:30.03#ibcon#wrote, iclass 28, count 2 2006.173.17:44:30.03#ibcon#about to read 3, iclass 28, count 2 2006.173.17:44:30.06#ibcon#read 3, iclass 28, count 2 2006.173.17:44:30.06#ibcon#about to read 4, iclass 28, count 2 2006.173.17:44:30.06#ibcon#read 4, iclass 28, count 2 2006.173.17:44:30.06#ibcon#about to read 5, iclass 28, count 2 2006.173.17:44:30.06#ibcon#read 5, iclass 28, count 2 2006.173.17:44:30.06#ibcon#about to read 6, iclass 28, count 2 2006.173.17:44:30.06#ibcon#read 6, iclass 28, count 2 2006.173.17:44:30.06#ibcon#end of sib2, iclass 28, count 2 2006.173.17:44:30.06#ibcon#*after write, iclass 28, count 2 2006.173.17:44:30.06#ibcon#*before return 0, iclass 28, count 2 2006.173.17:44:30.06#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.17:44:30.06#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.17:44:30.06#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.17:44:30.06#ibcon#ireg 7 cls_cnt 0 2006.173.17:44:30.06#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.17:44:30.18#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.17:44:30.18#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.17:44:30.18#ibcon#enter wrdev, iclass 28, count 0 2006.173.17:44:30.18#ibcon#first serial, iclass 28, count 0 2006.173.17:44:30.18#ibcon#enter sib2, iclass 28, count 0 2006.173.17:44:30.18#ibcon#flushed, iclass 28, count 0 2006.173.17:44:30.18#ibcon#about to write, iclass 28, count 0 2006.173.17:44:30.18#ibcon#wrote, iclass 28, count 0 2006.173.17:44:30.18#ibcon#about to read 3, iclass 28, count 0 2006.173.17:44:30.20#ibcon#read 3, iclass 28, count 0 2006.173.17:44:30.20#ibcon#about to read 4, iclass 28, count 0 2006.173.17:44:30.20#ibcon#read 4, iclass 28, count 0 2006.173.17:44:30.20#ibcon#about to read 5, iclass 28, count 0 2006.173.17:44:30.20#ibcon#read 5, iclass 28, count 0 2006.173.17:44:30.20#ibcon#about to read 6, iclass 28, count 0 2006.173.17:44:30.20#ibcon#read 6, iclass 28, count 0 2006.173.17:44:30.20#ibcon#end of sib2, iclass 28, count 0 2006.173.17:44:30.20#ibcon#*mode == 0, iclass 28, count 0 2006.173.17:44:30.20#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.17:44:30.20#ibcon#[25=USB\r\n] 2006.173.17:44:30.20#ibcon#*before write, iclass 28, count 0 2006.173.17:44:30.20#ibcon#enter sib2, iclass 28, count 0 2006.173.17:44:30.20#ibcon#flushed, iclass 28, count 0 2006.173.17:44:30.20#ibcon#about to write, iclass 28, count 0 2006.173.17:44:30.20#ibcon#wrote, iclass 28, count 0 2006.173.17:44:30.20#ibcon#about to read 3, iclass 28, count 0 2006.173.17:44:30.23#ibcon#read 3, iclass 28, count 0 2006.173.17:44:30.23#ibcon#about to read 4, iclass 28, count 0 2006.173.17:44:30.23#ibcon#read 4, iclass 28, count 0 2006.173.17:44:30.23#ibcon#about to read 5, iclass 28, count 0 2006.173.17:44:30.23#ibcon#read 5, iclass 28, count 0 2006.173.17:44:30.23#ibcon#about to read 6, iclass 28, count 0 2006.173.17:44:30.23#ibcon#read 6, iclass 28, count 0 2006.173.17:44:30.23#ibcon#end of sib2, iclass 28, count 0 2006.173.17:44:30.23#ibcon#*after write, iclass 28, count 0 2006.173.17:44:30.23#ibcon#*before return 0, iclass 28, count 0 2006.173.17:44:30.23#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.17:44:30.23#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.17:44:30.23#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.17:44:30.23#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.17:44:30.23$vck44/valo=4,624.99 2006.173.17:44:30.23#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.17:44:30.23#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.17:44:30.23#ibcon#ireg 17 cls_cnt 0 2006.173.17:44:30.23#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.17:44:30.23#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.17:44:30.23#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.17:44:30.23#ibcon#enter wrdev, iclass 30, count 0 2006.173.17:44:30.23#ibcon#first serial, iclass 30, count 0 2006.173.17:44:30.23#ibcon#enter sib2, iclass 30, count 0 2006.173.17:44:30.23#ibcon#flushed, iclass 30, count 0 2006.173.17:44:30.23#ibcon#about to write, iclass 30, count 0 2006.173.17:44:30.23#ibcon#wrote, iclass 30, count 0 2006.173.17:44:30.23#ibcon#about to read 3, iclass 30, count 0 2006.173.17:44:30.25#ibcon#read 3, iclass 30, count 0 2006.173.17:44:30.25#ibcon#about to read 4, iclass 30, count 0 2006.173.17:44:30.25#ibcon#read 4, iclass 30, count 0 2006.173.17:44:30.25#ibcon#about to read 5, iclass 30, count 0 2006.173.17:44:30.25#ibcon#read 5, iclass 30, count 0 2006.173.17:44:30.25#ibcon#about to read 6, iclass 30, count 0 2006.173.17:44:30.25#ibcon#read 6, iclass 30, count 0 2006.173.17:44:30.25#ibcon#end of sib2, iclass 30, count 0 2006.173.17:44:30.25#ibcon#*mode == 0, iclass 30, count 0 2006.173.17:44:30.25#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.17:44:30.25#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.17:44:30.25#ibcon#*before write, iclass 30, count 0 2006.173.17:44:30.25#ibcon#enter sib2, iclass 30, count 0 2006.173.17:44:30.25#ibcon#flushed, iclass 30, count 0 2006.173.17:44:30.25#ibcon#about to write, iclass 30, count 0 2006.173.17:44:30.25#ibcon#wrote, iclass 30, count 0 2006.173.17:44:30.25#ibcon#about to read 3, iclass 30, count 0 2006.173.17:44:30.29#ibcon#read 3, iclass 30, count 0 2006.173.17:44:30.29#ibcon#about to read 4, iclass 30, count 0 2006.173.17:44:30.29#ibcon#read 4, iclass 30, count 0 2006.173.17:44:30.29#ibcon#about to read 5, iclass 30, count 0 2006.173.17:44:30.29#ibcon#read 5, iclass 30, count 0 2006.173.17:44:30.29#ibcon#about to read 6, iclass 30, count 0 2006.173.17:44:30.29#ibcon#read 6, iclass 30, count 0 2006.173.17:44:30.29#ibcon#end of sib2, iclass 30, count 0 2006.173.17:44:30.29#ibcon#*after write, iclass 30, count 0 2006.173.17:44:30.29#ibcon#*before return 0, iclass 30, count 0 2006.173.17:44:30.29#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.17:44:30.29#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.17:44:30.29#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.17:44:30.29#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.17:44:30.29$vck44/va=4,6 2006.173.17:44:30.29#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.173.17:44:30.29#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.173.17:44:30.29#ibcon#ireg 11 cls_cnt 2 2006.173.17:44:30.29#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.17:44:30.35#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.17:44:30.35#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.17:44:30.35#ibcon#enter wrdev, iclass 32, count 2 2006.173.17:44:30.35#ibcon#first serial, iclass 32, count 2 2006.173.17:44:30.35#ibcon#enter sib2, iclass 32, count 2 2006.173.17:44:30.35#ibcon#flushed, iclass 32, count 2 2006.173.17:44:30.35#ibcon#about to write, iclass 32, count 2 2006.173.17:44:30.35#ibcon#wrote, iclass 32, count 2 2006.173.17:44:30.35#ibcon#about to read 3, iclass 32, count 2 2006.173.17:44:30.37#ibcon#read 3, iclass 32, count 2 2006.173.17:44:30.37#ibcon#about to read 4, iclass 32, count 2 2006.173.17:44:30.37#ibcon#read 4, iclass 32, count 2 2006.173.17:44:30.37#ibcon#about to read 5, iclass 32, count 2 2006.173.17:44:30.37#ibcon#read 5, iclass 32, count 2 2006.173.17:44:30.37#ibcon#about to read 6, iclass 32, count 2 2006.173.17:44:30.37#ibcon#read 6, iclass 32, count 2 2006.173.17:44:30.37#ibcon#end of sib2, iclass 32, count 2 2006.173.17:44:30.37#ibcon#*mode == 0, iclass 32, count 2 2006.173.17:44:30.37#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.173.17:44:30.37#ibcon#[25=AT04-06\r\n] 2006.173.17:44:30.37#ibcon#*before write, iclass 32, count 2 2006.173.17:44:30.37#ibcon#enter sib2, iclass 32, count 2 2006.173.17:44:30.37#ibcon#flushed, iclass 32, count 2 2006.173.17:44:30.37#ibcon#about to write, iclass 32, count 2 2006.173.17:44:30.37#ibcon#wrote, iclass 32, count 2 2006.173.17:44:30.37#ibcon#about to read 3, iclass 32, count 2 2006.173.17:44:30.40#ibcon#read 3, iclass 32, count 2 2006.173.17:44:30.40#ibcon#about to read 4, iclass 32, count 2 2006.173.17:44:30.40#ibcon#read 4, iclass 32, count 2 2006.173.17:44:30.40#ibcon#about to read 5, iclass 32, count 2 2006.173.17:44:30.40#ibcon#read 5, iclass 32, count 2 2006.173.17:44:30.40#ibcon#about to read 6, iclass 32, count 2 2006.173.17:44:30.40#ibcon#read 6, iclass 32, count 2 2006.173.17:44:30.40#ibcon#end of sib2, iclass 32, count 2 2006.173.17:44:30.40#ibcon#*after write, iclass 32, count 2 2006.173.17:44:30.40#ibcon#*before return 0, iclass 32, count 2 2006.173.17:44:30.40#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.17:44:30.40#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.173.17:44:30.40#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.173.17:44:30.40#ibcon#ireg 7 cls_cnt 0 2006.173.17:44:30.40#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.17:44:30.52#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.17:44:30.52#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.17:44:30.52#ibcon#enter wrdev, iclass 32, count 0 2006.173.17:44:30.52#ibcon#first serial, iclass 32, count 0 2006.173.17:44:30.52#ibcon#enter sib2, iclass 32, count 0 2006.173.17:44:30.52#ibcon#flushed, iclass 32, count 0 2006.173.17:44:30.52#ibcon#about to write, iclass 32, count 0 2006.173.17:44:30.52#ibcon#wrote, iclass 32, count 0 2006.173.17:44:30.52#ibcon#about to read 3, iclass 32, count 0 2006.173.17:44:30.54#ibcon#read 3, iclass 32, count 0 2006.173.17:44:30.54#ibcon#about to read 4, iclass 32, count 0 2006.173.17:44:30.54#ibcon#read 4, iclass 32, count 0 2006.173.17:44:30.54#ibcon#about to read 5, iclass 32, count 0 2006.173.17:44:30.54#ibcon#read 5, iclass 32, count 0 2006.173.17:44:30.54#ibcon#about to read 6, iclass 32, count 0 2006.173.17:44:30.54#ibcon#read 6, iclass 32, count 0 2006.173.17:44:30.54#ibcon#end of sib2, iclass 32, count 0 2006.173.17:44:30.54#ibcon#*mode == 0, iclass 32, count 0 2006.173.17:44:30.54#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.17:44:30.54#ibcon#[25=USB\r\n] 2006.173.17:44:30.54#ibcon#*before write, iclass 32, count 0 2006.173.17:44:30.54#ibcon#enter sib2, iclass 32, count 0 2006.173.17:44:30.54#ibcon#flushed, iclass 32, count 0 2006.173.17:44:30.54#ibcon#about to write, iclass 32, count 0 2006.173.17:44:30.54#ibcon#wrote, iclass 32, count 0 2006.173.17:44:30.54#ibcon#about to read 3, iclass 32, count 0 2006.173.17:44:30.57#ibcon#read 3, iclass 32, count 0 2006.173.17:44:30.57#ibcon#about to read 4, iclass 32, count 0 2006.173.17:44:30.57#ibcon#read 4, iclass 32, count 0 2006.173.17:44:30.57#ibcon#about to read 5, iclass 32, count 0 2006.173.17:44:30.57#ibcon#read 5, iclass 32, count 0 2006.173.17:44:30.57#ibcon#about to read 6, iclass 32, count 0 2006.173.17:44:30.57#ibcon#read 6, iclass 32, count 0 2006.173.17:44:30.57#ibcon#end of sib2, iclass 32, count 0 2006.173.17:44:30.57#ibcon#*after write, iclass 32, count 0 2006.173.17:44:30.57#ibcon#*before return 0, iclass 32, count 0 2006.173.17:44:30.57#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.17:44:30.57#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.173.17:44:30.57#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.17:44:30.57#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.17:44:30.57$vck44/valo=5,734.99 2006.173.17:44:30.57#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.17:44:30.57#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.17:44:30.57#ibcon#ireg 17 cls_cnt 0 2006.173.17:44:30.57#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.17:44:30.57#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.17:44:30.57#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.17:44:30.57#ibcon#enter wrdev, iclass 34, count 0 2006.173.17:44:30.57#ibcon#first serial, iclass 34, count 0 2006.173.17:44:30.57#ibcon#enter sib2, iclass 34, count 0 2006.173.17:44:30.57#ibcon#flushed, iclass 34, count 0 2006.173.17:44:30.57#ibcon#about to write, iclass 34, count 0 2006.173.17:44:30.57#ibcon#wrote, iclass 34, count 0 2006.173.17:44:30.57#ibcon#about to read 3, iclass 34, count 0 2006.173.17:44:30.59#ibcon#read 3, iclass 34, count 0 2006.173.17:44:30.59#ibcon#about to read 4, iclass 34, count 0 2006.173.17:44:30.59#ibcon#read 4, iclass 34, count 0 2006.173.17:44:30.59#ibcon#about to read 5, iclass 34, count 0 2006.173.17:44:30.59#ibcon#read 5, iclass 34, count 0 2006.173.17:44:30.59#ibcon#about to read 6, iclass 34, count 0 2006.173.17:44:30.59#ibcon#read 6, iclass 34, count 0 2006.173.17:44:30.59#ibcon#end of sib2, iclass 34, count 0 2006.173.17:44:30.59#ibcon#*mode == 0, iclass 34, count 0 2006.173.17:44:30.59#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.17:44:30.59#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.17:44:30.59#ibcon#*before write, iclass 34, count 0 2006.173.17:44:30.59#ibcon#enter sib2, iclass 34, count 0 2006.173.17:44:30.59#ibcon#flushed, iclass 34, count 0 2006.173.17:44:30.59#ibcon#about to write, iclass 34, count 0 2006.173.17:44:30.59#ibcon#wrote, iclass 34, count 0 2006.173.17:44:30.59#ibcon#about to read 3, iclass 34, count 0 2006.173.17:44:30.63#ibcon#read 3, iclass 34, count 0 2006.173.17:44:30.63#ibcon#about to read 4, iclass 34, count 0 2006.173.17:44:30.63#ibcon#read 4, iclass 34, count 0 2006.173.17:44:30.63#ibcon#about to read 5, iclass 34, count 0 2006.173.17:44:30.63#ibcon#read 5, iclass 34, count 0 2006.173.17:44:30.63#ibcon#about to read 6, iclass 34, count 0 2006.173.17:44:30.63#ibcon#read 6, iclass 34, count 0 2006.173.17:44:30.63#ibcon#end of sib2, iclass 34, count 0 2006.173.17:44:30.63#ibcon#*after write, iclass 34, count 0 2006.173.17:44:30.63#ibcon#*before return 0, iclass 34, count 0 2006.173.17:44:30.63#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.17:44:30.63#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.17:44:30.63#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.17:44:30.63#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.17:44:30.63$vck44/va=5,4 2006.173.17:44:30.63#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.17:44:30.63#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.17:44:30.63#ibcon#ireg 11 cls_cnt 2 2006.173.17:44:30.63#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.17:44:30.69#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.17:44:30.69#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.17:44:30.69#ibcon#enter wrdev, iclass 36, count 2 2006.173.17:44:30.69#ibcon#first serial, iclass 36, count 2 2006.173.17:44:30.69#ibcon#enter sib2, iclass 36, count 2 2006.173.17:44:30.69#ibcon#flushed, iclass 36, count 2 2006.173.17:44:30.69#ibcon#about to write, iclass 36, count 2 2006.173.17:44:30.69#ibcon#wrote, iclass 36, count 2 2006.173.17:44:30.69#ibcon#about to read 3, iclass 36, count 2 2006.173.17:44:30.71#ibcon#read 3, iclass 36, count 2 2006.173.17:44:30.71#ibcon#about to read 4, iclass 36, count 2 2006.173.17:44:30.71#ibcon#read 4, iclass 36, count 2 2006.173.17:44:30.71#ibcon#about to read 5, iclass 36, count 2 2006.173.17:44:30.71#ibcon#read 5, iclass 36, count 2 2006.173.17:44:30.71#ibcon#about to read 6, iclass 36, count 2 2006.173.17:44:30.71#ibcon#read 6, iclass 36, count 2 2006.173.17:44:30.71#ibcon#end of sib2, iclass 36, count 2 2006.173.17:44:30.71#ibcon#*mode == 0, iclass 36, count 2 2006.173.17:44:30.71#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.17:44:30.71#ibcon#[25=AT05-04\r\n] 2006.173.17:44:30.71#ibcon#*before write, iclass 36, count 2 2006.173.17:44:30.71#ibcon#enter sib2, iclass 36, count 2 2006.173.17:44:30.71#ibcon#flushed, iclass 36, count 2 2006.173.17:44:30.71#ibcon#about to write, iclass 36, count 2 2006.173.17:44:30.71#ibcon#wrote, iclass 36, count 2 2006.173.17:44:30.71#ibcon#about to read 3, iclass 36, count 2 2006.173.17:44:30.74#ibcon#read 3, iclass 36, count 2 2006.173.17:44:30.74#ibcon#about to read 4, iclass 36, count 2 2006.173.17:44:30.74#ibcon#read 4, iclass 36, count 2 2006.173.17:44:30.74#ibcon#about to read 5, iclass 36, count 2 2006.173.17:44:30.74#ibcon#read 5, iclass 36, count 2 2006.173.17:44:30.74#ibcon#about to read 6, iclass 36, count 2 2006.173.17:44:30.74#ibcon#read 6, iclass 36, count 2 2006.173.17:44:30.74#ibcon#end of sib2, iclass 36, count 2 2006.173.17:44:30.74#ibcon#*after write, iclass 36, count 2 2006.173.17:44:30.74#ibcon#*before return 0, iclass 36, count 2 2006.173.17:44:30.74#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.17:44:30.74#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.17:44:30.74#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.17:44:30.74#ibcon#ireg 7 cls_cnt 0 2006.173.17:44:30.74#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.17:44:30.86#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.17:44:30.86#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.17:44:30.86#ibcon#enter wrdev, iclass 36, count 0 2006.173.17:44:30.86#ibcon#first serial, iclass 36, count 0 2006.173.17:44:30.86#ibcon#enter sib2, iclass 36, count 0 2006.173.17:44:30.86#ibcon#flushed, iclass 36, count 0 2006.173.17:44:30.86#ibcon#about to write, iclass 36, count 0 2006.173.17:44:30.86#ibcon#wrote, iclass 36, count 0 2006.173.17:44:30.86#ibcon#about to read 3, iclass 36, count 0 2006.173.17:44:30.88#ibcon#read 3, iclass 36, count 0 2006.173.17:44:30.88#ibcon#about to read 4, iclass 36, count 0 2006.173.17:44:30.88#ibcon#read 4, iclass 36, count 0 2006.173.17:44:30.88#ibcon#about to read 5, iclass 36, count 0 2006.173.17:44:30.88#ibcon#read 5, iclass 36, count 0 2006.173.17:44:30.88#ibcon#about to read 6, iclass 36, count 0 2006.173.17:44:30.88#ibcon#read 6, iclass 36, count 0 2006.173.17:44:30.88#ibcon#end of sib2, iclass 36, count 0 2006.173.17:44:30.88#ibcon#*mode == 0, iclass 36, count 0 2006.173.17:44:30.88#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.17:44:30.88#ibcon#[25=USB\r\n] 2006.173.17:44:30.88#ibcon#*before write, iclass 36, count 0 2006.173.17:44:30.88#ibcon#enter sib2, iclass 36, count 0 2006.173.17:44:30.88#ibcon#flushed, iclass 36, count 0 2006.173.17:44:30.88#ibcon#about to write, iclass 36, count 0 2006.173.17:44:30.88#ibcon#wrote, iclass 36, count 0 2006.173.17:44:30.88#ibcon#about to read 3, iclass 36, count 0 2006.173.17:44:30.91#ibcon#read 3, iclass 36, count 0 2006.173.17:44:30.91#ibcon#about to read 4, iclass 36, count 0 2006.173.17:44:30.91#ibcon#read 4, iclass 36, count 0 2006.173.17:44:30.91#ibcon#about to read 5, iclass 36, count 0 2006.173.17:44:30.91#ibcon#read 5, iclass 36, count 0 2006.173.17:44:30.91#ibcon#about to read 6, iclass 36, count 0 2006.173.17:44:30.91#ibcon#read 6, iclass 36, count 0 2006.173.17:44:30.91#ibcon#end of sib2, iclass 36, count 0 2006.173.17:44:30.91#ibcon#*after write, iclass 36, count 0 2006.173.17:44:30.91#ibcon#*before return 0, iclass 36, count 0 2006.173.17:44:30.91#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.17:44:30.91#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.17:44:30.91#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.17:44:30.91#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.17:44:30.91$vck44/valo=6,814.99 2006.173.17:44:30.91#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.17:44:30.91#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.17:44:30.91#ibcon#ireg 17 cls_cnt 0 2006.173.17:44:30.91#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.17:44:30.91#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.17:44:30.91#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.17:44:30.91#ibcon#enter wrdev, iclass 38, count 0 2006.173.17:44:30.91#ibcon#first serial, iclass 38, count 0 2006.173.17:44:30.91#ibcon#enter sib2, iclass 38, count 0 2006.173.17:44:30.91#ibcon#flushed, iclass 38, count 0 2006.173.17:44:30.91#ibcon#about to write, iclass 38, count 0 2006.173.17:44:30.91#ibcon#wrote, iclass 38, count 0 2006.173.17:44:30.91#ibcon#about to read 3, iclass 38, count 0 2006.173.17:44:30.93#ibcon#read 3, iclass 38, count 0 2006.173.17:44:30.93#ibcon#about to read 4, iclass 38, count 0 2006.173.17:44:30.93#ibcon#read 4, iclass 38, count 0 2006.173.17:44:30.93#ibcon#about to read 5, iclass 38, count 0 2006.173.17:44:30.93#ibcon#read 5, iclass 38, count 0 2006.173.17:44:30.93#ibcon#about to read 6, iclass 38, count 0 2006.173.17:44:30.93#ibcon#read 6, iclass 38, count 0 2006.173.17:44:30.93#ibcon#end of sib2, iclass 38, count 0 2006.173.17:44:30.93#ibcon#*mode == 0, iclass 38, count 0 2006.173.17:44:30.93#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.17:44:30.93#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.17:44:30.93#ibcon#*before write, iclass 38, count 0 2006.173.17:44:30.93#ibcon#enter sib2, iclass 38, count 0 2006.173.17:44:30.93#ibcon#flushed, iclass 38, count 0 2006.173.17:44:30.93#ibcon#about to write, iclass 38, count 0 2006.173.17:44:30.93#ibcon#wrote, iclass 38, count 0 2006.173.17:44:30.93#ibcon#about to read 3, iclass 38, count 0 2006.173.17:44:30.97#ibcon#read 3, iclass 38, count 0 2006.173.17:44:30.97#ibcon#about to read 4, iclass 38, count 0 2006.173.17:44:30.97#ibcon#read 4, iclass 38, count 0 2006.173.17:44:30.97#ibcon#about to read 5, iclass 38, count 0 2006.173.17:44:30.97#ibcon#read 5, iclass 38, count 0 2006.173.17:44:30.97#ibcon#about to read 6, iclass 38, count 0 2006.173.17:44:30.97#ibcon#read 6, iclass 38, count 0 2006.173.17:44:30.97#ibcon#end of sib2, iclass 38, count 0 2006.173.17:44:30.97#ibcon#*after write, iclass 38, count 0 2006.173.17:44:30.97#ibcon#*before return 0, iclass 38, count 0 2006.173.17:44:30.97#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.17:44:30.97#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.17:44:30.97#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.17:44:30.97#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.17:44:30.97$vck44/va=6,3 2006.173.17:44:30.97#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.17:44:30.97#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.17:44:30.97#ibcon#ireg 11 cls_cnt 2 2006.173.17:44:30.97#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.17:44:31.03#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.17:44:31.03#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.17:44:31.03#ibcon#enter wrdev, iclass 40, count 2 2006.173.17:44:31.03#ibcon#first serial, iclass 40, count 2 2006.173.17:44:31.03#ibcon#enter sib2, iclass 40, count 2 2006.173.17:44:31.03#ibcon#flushed, iclass 40, count 2 2006.173.17:44:31.03#ibcon#about to write, iclass 40, count 2 2006.173.17:44:31.03#ibcon#wrote, iclass 40, count 2 2006.173.17:44:31.03#ibcon#about to read 3, iclass 40, count 2 2006.173.17:44:31.05#ibcon#read 3, iclass 40, count 2 2006.173.17:44:31.05#ibcon#about to read 4, iclass 40, count 2 2006.173.17:44:31.05#ibcon#read 4, iclass 40, count 2 2006.173.17:44:31.05#ibcon#about to read 5, iclass 40, count 2 2006.173.17:44:31.05#ibcon#read 5, iclass 40, count 2 2006.173.17:44:31.05#ibcon#about to read 6, iclass 40, count 2 2006.173.17:44:31.05#ibcon#read 6, iclass 40, count 2 2006.173.17:44:31.05#ibcon#end of sib2, iclass 40, count 2 2006.173.17:44:31.05#ibcon#*mode == 0, iclass 40, count 2 2006.173.17:44:31.05#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.17:44:31.05#ibcon#[25=AT06-03\r\n] 2006.173.17:44:31.05#ibcon#*before write, iclass 40, count 2 2006.173.17:44:31.05#ibcon#enter sib2, iclass 40, count 2 2006.173.17:44:31.05#ibcon#flushed, iclass 40, count 2 2006.173.17:44:31.05#ibcon#about to write, iclass 40, count 2 2006.173.17:44:31.05#ibcon#wrote, iclass 40, count 2 2006.173.17:44:31.05#ibcon#about to read 3, iclass 40, count 2 2006.173.17:44:31.08#ibcon#read 3, iclass 40, count 2 2006.173.17:44:31.08#ibcon#about to read 4, iclass 40, count 2 2006.173.17:44:31.08#ibcon#read 4, iclass 40, count 2 2006.173.17:44:31.08#ibcon#about to read 5, iclass 40, count 2 2006.173.17:44:31.08#ibcon#read 5, iclass 40, count 2 2006.173.17:44:31.08#ibcon#about to read 6, iclass 40, count 2 2006.173.17:44:31.08#ibcon#read 6, iclass 40, count 2 2006.173.17:44:31.08#ibcon#end of sib2, iclass 40, count 2 2006.173.17:44:31.08#ibcon#*after write, iclass 40, count 2 2006.173.17:44:31.08#ibcon#*before return 0, iclass 40, count 2 2006.173.17:44:31.08#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.17:44:31.08#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.17:44:31.08#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.17:44:31.08#ibcon#ireg 7 cls_cnt 0 2006.173.17:44:31.08#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.17:44:31.20#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.17:44:31.20#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.17:44:31.20#ibcon#enter wrdev, iclass 40, count 0 2006.173.17:44:31.20#ibcon#first serial, iclass 40, count 0 2006.173.17:44:31.20#ibcon#enter sib2, iclass 40, count 0 2006.173.17:44:31.20#ibcon#flushed, iclass 40, count 0 2006.173.17:44:31.20#ibcon#about to write, iclass 40, count 0 2006.173.17:44:31.20#ibcon#wrote, iclass 40, count 0 2006.173.17:44:31.20#ibcon#about to read 3, iclass 40, count 0 2006.173.17:44:31.22#ibcon#read 3, iclass 40, count 0 2006.173.17:44:31.22#ibcon#about to read 4, iclass 40, count 0 2006.173.17:44:31.22#ibcon#read 4, iclass 40, count 0 2006.173.17:44:31.22#ibcon#about to read 5, iclass 40, count 0 2006.173.17:44:31.22#ibcon#read 5, iclass 40, count 0 2006.173.17:44:31.22#ibcon#about to read 6, iclass 40, count 0 2006.173.17:44:31.22#ibcon#read 6, iclass 40, count 0 2006.173.17:44:31.22#ibcon#end of sib2, iclass 40, count 0 2006.173.17:44:31.22#ibcon#*mode == 0, iclass 40, count 0 2006.173.17:44:31.22#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.17:44:31.22#ibcon#[25=USB\r\n] 2006.173.17:44:31.22#ibcon#*before write, iclass 40, count 0 2006.173.17:44:31.22#ibcon#enter sib2, iclass 40, count 0 2006.173.17:44:31.22#ibcon#flushed, iclass 40, count 0 2006.173.17:44:31.22#ibcon#about to write, iclass 40, count 0 2006.173.17:44:31.22#ibcon#wrote, iclass 40, count 0 2006.173.17:44:31.22#ibcon#about to read 3, iclass 40, count 0 2006.173.17:44:31.25#ibcon#read 3, iclass 40, count 0 2006.173.17:44:31.25#ibcon#about to read 4, iclass 40, count 0 2006.173.17:44:31.25#ibcon#read 4, iclass 40, count 0 2006.173.17:44:31.25#ibcon#about to read 5, iclass 40, count 0 2006.173.17:44:31.25#ibcon#read 5, iclass 40, count 0 2006.173.17:44:31.25#ibcon#about to read 6, iclass 40, count 0 2006.173.17:44:31.25#ibcon#read 6, iclass 40, count 0 2006.173.17:44:31.25#ibcon#end of sib2, iclass 40, count 0 2006.173.17:44:31.25#ibcon#*after write, iclass 40, count 0 2006.173.17:44:31.25#ibcon#*before return 0, iclass 40, count 0 2006.173.17:44:31.25#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.17:44:31.25#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.17:44:31.25#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.17:44:31.25#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.17:44:31.25$vck44/valo=7,864.99 2006.173.17:44:31.25#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.17:44:31.25#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.17:44:31.25#ibcon#ireg 17 cls_cnt 0 2006.173.17:44:31.25#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.17:44:31.25#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.17:44:31.25#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.17:44:31.25#ibcon#enter wrdev, iclass 4, count 0 2006.173.17:44:31.25#ibcon#first serial, iclass 4, count 0 2006.173.17:44:31.25#ibcon#enter sib2, iclass 4, count 0 2006.173.17:44:31.25#ibcon#flushed, iclass 4, count 0 2006.173.17:44:31.25#ibcon#about to write, iclass 4, count 0 2006.173.17:44:31.25#ibcon#wrote, iclass 4, count 0 2006.173.17:44:31.25#ibcon#about to read 3, iclass 4, count 0 2006.173.17:44:31.27#ibcon#read 3, iclass 4, count 0 2006.173.17:44:31.27#ibcon#about to read 4, iclass 4, count 0 2006.173.17:44:31.27#ibcon#read 4, iclass 4, count 0 2006.173.17:44:31.27#ibcon#about to read 5, iclass 4, count 0 2006.173.17:44:31.27#ibcon#read 5, iclass 4, count 0 2006.173.17:44:31.27#ibcon#about to read 6, iclass 4, count 0 2006.173.17:44:31.27#ibcon#read 6, iclass 4, count 0 2006.173.17:44:31.27#ibcon#end of sib2, iclass 4, count 0 2006.173.17:44:31.27#ibcon#*mode == 0, iclass 4, count 0 2006.173.17:44:31.27#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.17:44:31.27#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.17:44:31.27#ibcon#*before write, iclass 4, count 0 2006.173.17:44:31.27#ibcon#enter sib2, iclass 4, count 0 2006.173.17:44:31.27#ibcon#flushed, iclass 4, count 0 2006.173.17:44:31.27#ibcon#about to write, iclass 4, count 0 2006.173.17:44:31.27#ibcon#wrote, iclass 4, count 0 2006.173.17:44:31.27#ibcon#about to read 3, iclass 4, count 0 2006.173.17:44:31.31#ibcon#read 3, iclass 4, count 0 2006.173.17:44:31.31#ibcon#about to read 4, iclass 4, count 0 2006.173.17:44:31.31#ibcon#read 4, iclass 4, count 0 2006.173.17:44:31.31#ibcon#about to read 5, iclass 4, count 0 2006.173.17:44:31.31#ibcon#read 5, iclass 4, count 0 2006.173.17:44:31.31#ibcon#about to read 6, iclass 4, count 0 2006.173.17:44:31.31#ibcon#read 6, iclass 4, count 0 2006.173.17:44:31.31#ibcon#end of sib2, iclass 4, count 0 2006.173.17:44:31.31#ibcon#*after write, iclass 4, count 0 2006.173.17:44:31.31#ibcon#*before return 0, iclass 4, count 0 2006.173.17:44:31.31#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.17:44:31.31#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.17:44:31.31#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.17:44:31.31#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.17:44:31.31$vck44/va=7,4 2006.173.17:44:31.31#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.17:44:31.31#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.17:44:31.31#ibcon#ireg 11 cls_cnt 2 2006.173.17:44:31.31#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.17:44:31.37#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.17:44:31.37#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.17:44:31.37#ibcon#enter wrdev, iclass 6, count 2 2006.173.17:44:31.37#ibcon#first serial, iclass 6, count 2 2006.173.17:44:31.37#ibcon#enter sib2, iclass 6, count 2 2006.173.17:44:31.37#ibcon#flushed, iclass 6, count 2 2006.173.17:44:31.37#ibcon#about to write, iclass 6, count 2 2006.173.17:44:31.37#ibcon#wrote, iclass 6, count 2 2006.173.17:44:31.37#ibcon#about to read 3, iclass 6, count 2 2006.173.17:44:31.39#ibcon#read 3, iclass 6, count 2 2006.173.17:44:31.39#ibcon#about to read 4, iclass 6, count 2 2006.173.17:44:31.39#ibcon#read 4, iclass 6, count 2 2006.173.17:44:31.39#ibcon#about to read 5, iclass 6, count 2 2006.173.17:44:31.39#ibcon#read 5, iclass 6, count 2 2006.173.17:44:31.39#ibcon#about to read 6, iclass 6, count 2 2006.173.17:44:31.39#ibcon#read 6, iclass 6, count 2 2006.173.17:44:31.39#ibcon#end of sib2, iclass 6, count 2 2006.173.17:44:31.39#ibcon#*mode == 0, iclass 6, count 2 2006.173.17:44:31.39#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.17:44:31.39#ibcon#[25=AT07-04\r\n] 2006.173.17:44:31.39#ibcon#*before write, iclass 6, count 2 2006.173.17:44:31.39#ibcon#enter sib2, iclass 6, count 2 2006.173.17:44:31.39#ibcon#flushed, iclass 6, count 2 2006.173.17:44:31.39#ibcon#about to write, iclass 6, count 2 2006.173.17:44:31.39#ibcon#wrote, iclass 6, count 2 2006.173.17:44:31.39#ibcon#about to read 3, iclass 6, count 2 2006.173.17:44:31.42#ibcon#read 3, iclass 6, count 2 2006.173.17:44:31.42#ibcon#about to read 4, iclass 6, count 2 2006.173.17:44:31.42#ibcon#read 4, iclass 6, count 2 2006.173.17:44:31.42#ibcon#about to read 5, iclass 6, count 2 2006.173.17:44:31.42#ibcon#read 5, iclass 6, count 2 2006.173.17:44:31.42#ibcon#about to read 6, iclass 6, count 2 2006.173.17:44:31.42#ibcon#read 6, iclass 6, count 2 2006.173.17:44:31.42#ibcon#end of sib2, iclass 6, count 2 2006.173.17:44:31.42#ibcon#*after write, iclass 6, count 2 2006.173.17:44:31.42#ibcon#*before return 0, iclass 6, count 2 2006.173.17:44:31.42#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.17:44:31.42#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.17:44:31.42#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.17:44:31.42#ibcon#ireg 7 cls_cnt 0 2006.173.17:44:31.42#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.17:44:31.54#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.17:44:31.54#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.17:44:31.54#ibcon#enter wrdev, iclass 6, count 0 2006.173.17:44:31.54#ibcon#first serial, iclass 6, count 0 2006.173.17:44:31.54#ibcon#enter sib2, iclass 6, count 0 2006.173.17:44:31.54#ibcon#flushed, iclass 6, count 0 2006.173.17:44:31.54#ibcon#about to write, iclass 6, count 0 2006.173.17:44:31.54#ibcon#wrote, iclass 6, count 0 2006.173.17:44:31.54#ibcon#about to read 3, iclass 6, count 0 2006.173.17:44:31.56#ibcon#read 3, iclass 6, count 0 2006.173.17:44:31.56#ibcon#about to read 4, iclass 6, count 0 2006.173.17:44:31.56#ibcon#read 4, iclass 6, count 0 2006.173.17:44:31.56#ibcon#about to read 5, iclass 6, count 0 2006.173.17:44:31.56#ibcon#read 5, iclass 6, count 0 2006.173.17:44:31.56#ibcon#about to read 6, iclass 6, count 0 2006.173.17:44:31.56#ibcon#read 6, iclass 6, count 0 2006.173.17:44:31.56#ibcon#end of sib2, iclass 6, count 0 2006.173.17:44:31.56#ibcon#*mode == 0, iclass 6, count 0 2006.173.17:44:31.56#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.17:44:31.56#ibcon#[25=USB\r\n] 2006.173.17:44:31.56#ibcon#*before write, iclass 6, count 0 2006.173.17:44:31.56#ibcon#enter sib2, iclass 6, count 0 2006.173.17:44:31.56#ibcon#flushed, iclass 6, count 0 2006.173.17:44:31.56#ibcon#about to write, iclass 6, count 0 2006.173.17:44:31.56#ibcon#wrote, iclass 6, count 0 2006.173.17:44:31.56#ibcon#about to read 3, iclass 6, count 0 2006.173.17:44:31.59#ibcon#read 3, iclass 6, count 0 2006.173.17:44:31.59#ibcon#about to read 4, iclass 6, count 0 2006.173.17:44:31.59#ibcon#read 4, iclass 6, count 0 2006.173.17:44:31.59#ibcon#about to read 5, iclass 6, count 0 2006.173.17:44:31.59#ibcon#read 5, iclass 6, count 0 2006.173.17:44:31.59#ibcon#about to read 6, iclass 6, count 0 2006.173.17:44:31.59#ibcon#read 6, iclass 6, count 0 2006.173.17:44:31.59#ibcon#end of sib2, iclass 6, count 0 2006.173.17:44:31.59#ibcon#*after write, iclass 6, count 0 2006.173.17:44:31.59#ibcon#*before return 0, iclass 6, count 0 2006.173.17:44:31.59#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.17:44:31.59#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.17:44:31.59#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.17:44:31.59#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.17:44:31.59$vck44/valo=8,884.99 2006.173.17:44:31.59#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.17:44:31.59#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.17:44:31.59#ibcon#ireg 17 cls_cnt 0 2006.173.17:44:31.59#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.17:44:31.59#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.17:44:31.59#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.17:44:31.59#ibcon#enter wrdev, iclass 10, count 0 2006.173.17:44:31.59#ibcon#first serial, iclass 10, count 0 2006.173.17:44:31.59#ibcon#enter sib2, iclass 10, count 0 2006.173.17:44:31.59#ibcon#flushed, iclass 10, count 0 2006.173.17:44:31.59#ibcon#about to write, iclass 10, count 0 2006.173.17:44:31.59#ibcon#wrote, iclass 10, count 0 2006.173.17:44:31.59#ibcon#about to read 3, iclass 10, count 0 2006.173.17:44:31.61#ibcon#read 3, iclass 10, count 0 2006.173.17:44:31.61#ibcon#about to read 4, iclass 10, count 0 2006.173.17:44:31.61#ibcon#read 4, iclass 10, count 0 2006.173.17:44:31.61#ibcon#about to read 5, iclass 10, count 0 2006.173.17:44:31.61#ibcon#read 5, iclass 10, count 0 2006.173.17:44:31.61#ibcon#about to read 6, iclass 10, count 0 2006.173.17:44:31.61#ibcon#read 6, iclass 10, count 0 2006.173.17:44:31.61#ibcon#end of sib2, iclass 10, count 0 2006.173.17:44:31.61#ibcon#*mode == 0, iclass 10, count 0 2006.173.17:44:31.61#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.17:44:31.61#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.17:44:31.61#ibcon#*before write, iclass 10, count 0 2006.173.17:44:31.61#ibcon#enter sib2, iclass 10, count 0 2006.173.17:44:31.61#ibcon#flushed, iclass 10, count 0 2006.173.17:44:31.61#ibcon#about to write, iclass 10, count 0 2006.173.17:44:31.61#ibcon#wrote, iclass 10, count 0 2006.173.17:44:31.61#ibcon#about to read 3, iclass 10, count 0 2006.173.17:44:31.65#ibcon#read 3, iclass 10, count 0 2006.173.17:44:31.65#ibcon#about to read 4, iclass 10, count 0 2006.173.17:44:31.65#ibcon#read 4, iclass 10, count 0 2006.173.17:44:31.65#ibcon#about to read 5, iclass 10, count 0 2006.173.17:44:31.65#ibcon#read 5, iclass 10, count 0 2006.173.17:44:31.65#ibcon#about to read 6, iclass 10, count 0 2006.173.17:44:31.65#ibcon#read 6, iclass 10, count 0 2006.173.17:44:31.65#ibcon#end of sib2, iclass 10, count 0 2006.173.17:44:31.65#ibcon#*after write, iclass 10, count 0 2006.173.17:44:31.65#ibcon#*before return 0, iclass 10, count 0 2006.173.17:44:31.65#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.17:44:31.65#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.17:44:31.65#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.17:44:31.65#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.17:44:31.65$vck44/va=8,4 2006.173.17:44:31.65#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.17:44:31.65#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.17:44:31.65#ibcon#ireg 11 cls_cnt 2 2006.173.17:44:31.65#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.17:44:31.71#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.17:44:31.71#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.17:44:31.71#ibcon#enter wrdev, iclass 12, count 2 2006.173.17:44:31.71#ibcon#first serial, iclass 12, count 2 2006.173.17:44:31.71#ibcon#enter sib2, iclass 12, count 2 2006.173.17:44:31.71#ibcon#flushed, iclass 12, count 2 2006.173.17:44:31.71#ibcon#about to write, iclass 12, count 2 2006.173.17:44:31.71#ibcon#wrote, iclass 12, count 2 2006.173.17:44:31.71#ibcon#about to read 3, iclass 12, count 2 2006.173.17:44:31.73#ibcon#read 3, iclass 12, count 2 2006.173.17:44:31.73#ibcon#about to read 4, iclass 12, count 2 2006.173.17:44:31.73#ibcon#read 4, iclass 12, count 2 2006.173.17:44:31.73#ibcon#about to read 5, iclass 12, count 2 2006.173.17:44:31.73#ibcon#read 5, iclass 12, count 2 2006.173.17:44:31.73#ibcon#about to read 6, iclass 12, count 2 2006.173.17:44:31.73#ibcon#read 6, iclass 12, count 2 2006.173.17:44:31.73#ibcon#end of sib2, iclass 12, count 2 2006.173.17:44:31.73#ibcon#*mode == 0, iclass 12, count 2 2006.173.17:44:31.73#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.17:44:31.73#ibcon#[25=AT08-04\r\n] 2006.173.17:44:31.73#ibcon#*before write, iclass 12, count 2 2006.173.17:44:31.73#ibcon#enter sib2, iclass 12, count 2 2006.173.17:44:31.73#ibcon#flushed, iclass 12, count 2 2006.173.17:44:31.73#ibcon#about to write, iclass 12, count 2 2006.173.17:44:31.73#ibcon#wrote, iclass 12, count 2 2006.173.17:44:31.73#ibcon#about to read 3, iclass 12, count 2 2006.173.17:44:31.76#ibcon#read 3, iclass 12, count 2 2006.173.17:44:31.76#ibcon#about to read 4, iclass 12, count 2 2006.173.17:44:31.76#ibcon#read 4, iclass 12, count 2 2006.173.17:44:31.76#ibcon#about to read 5, iclass 12, count 2 2006.173.17:44:31.76#ibcon#read 5, iclass 12, count 2 2006.173.17:44:31.76#ibcon#about to read 6, iclass 12, count 2 2006.173.17:44:31.76#ibcon#read 6, iclass 12, count 2 2006.173.17:44:31.76#ibcon#end of sib2, iclass 12, count 2 2006.173.17:44:31.76#ibcon#*after write, iclass 12, count 2 2006.173.17:44:31.76#ibcon#*before return 0, iclass 12, count 2 2006.173.17:44:31.76#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.17:44:31.76#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.17:44:31.76#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.17:44:31.76#ibcon#ireg 7 cls_cnt 0 2006.173.17:44:31.76#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.17:44:31.88#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.17:44:31.88#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.17:44:31.88#ibcon#enter wrdev, iclass 12, count 0 2006.173.17:44:31.88#ibcon#first serial, iclass 12, count 0 2006.173.17:44:31.88#ibcon#enter sib2, iclass 12, count 0 2006.173.17:44:31.88#ibcon#flushed, iclass 12, count 0 2006.173.17:44:31.88#ibcon#about to write, iclass 12, count 0 2006.173.17:44:31.88#ibcon#wrote, iclass 12, count 0 2006.173.17:44:31.88#ibcon#about to read 3, iclass 12, count 0 2006.173.17:44:31.90#ibcon#read 3, iclass 12, count 0 2006.173.17:44:31.90#ibcon#about to read 4, iclass 12, count 0 2006.173.17:44:31.90#ibcon#read 4, iclass 12, count 0 2006.173.17:44:31.90#ibcon#about to read 5, iclass 12, count 0 2006.173.17:44:31.90#ibcon#read 5, iclass 12, count 0 2006.173.17:44:31.90#ibcon#about to read 6, iclass 12, count 0 2006.173.17:44:31.90#ibcon#read 6, iclass 12, count 0 2006.173.17:44:31.90#ibcon#end of sib2, iclass 12, count 0 2006.173.17:44:31.90#ibcon#*mode == 0, iclass 12, count 0 2006.173.17:44:31.90#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.17:44:31.90#ibcon#[25=USB\r\n] 2006.173.17:44:31.90#ibcon#*before write, iclass 12, count 0 2006.173.17:44:31.90#ibcon#enter sib2, iclass 12, count 0 2006.173.17:44:31.90#ibcon#flushed, iclass 12, count 0 2006.173.17:44:31.90#ibcon#about to write, iclass 12, count 0 2006.173.17:44:31.90#ibcon#wrote, iclass 12, count 0 2006.173.17:44:31.90#ibcon#about to read 3, iclass 12, count 0 2006.173.17:44:31.93#ibcon#read 3, iclass 12, count 0 2006.173.17:44:31.93#ibcon#about to read 4, iclass 12, count 0 2006.173.17:44:31.93#ibcon#read 4, iclass 12, count 0 2006.173.17:44:31.93#ibcon#about to read 5, iclass 12, count 0 2006.173.17:44:31.93#ibcon#read 5, iclass 12, count 0 2006.173.17:44:31.93#ibcon#about to read 6, iclass 12, count 0 2006.173.17:44:31.93#ibcon#read 6, iclass 12, count 0 2006.173.17:44:31.93#ibcon#end of sib2, iclass 12, count 0 2006.173.17:44:31.93#ibcon#*after write, iclass 12, count 0 2006.173.17:44:31.93#ibcon#*before return 0, iclass 12, count 0 2006.173.17:44:31.93#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.17:44:31.93#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.17:44:31.93#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.17:44:31.93#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.17:44:31.93$vck44/vblo=1,629.99 2006.173.17:44:31.93#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.17:44:31.93#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.17:44:31.93#ibcon#ireg 17 cls_cnt 0 2006.173.17:44:31.93#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.17:44:31.93#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.17:44:31.93#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.17:44:31.93#ibcon#enter wrdev, iclass 14, count 0 2006.173.17:44:31.93#ibcon#first serial, iclass 14, count 0 2006.173.17:44:31.93#ibcon#enter sib2, iclass 14, count 0 2006.173.17:44:31.93#ibcon#flushed, iclass 14, count 0 2006.173.17:44:31.93#ibcon#about to write, iclass 14, count 0 2006.173.17:44:31.93#ibcon#wrote, iclass 14, count 0 2006.173.17:44:31.93#ibcon#about to read 3, iclass 14, count 0 2006.173.17:44:31.95#ibcon#read 3, iclass 14, count 0 2006.173.17:44:31.95#ibcon#about to read 4, iclass 14, count 0 2006.173.17:44:31.95#ibcon#read 4, iclass 14, count 0 2006.173.17:44:31.95#ibcon#about to read 5, iclass 14, count 0 2006.173.17:44:31.95#ibcon#read 5, iclass 14, count 0 2006.173.17:44:31.95#ibcon#about to read 6, iclass 14, count 0 2006.173.17:44:31.95#ibcon#read 6, iclass 14, count 0 2006.173.17:44:31.95#ibcon#end of sib2, iclass 14, count 0 2006.173.17:44:31.95#ibcon#*mode == 0, iclass 14, count 0 2006.173.17:44:31.95#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.17:44:31.95#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.17:44:31.95#ibcon#*before write, iclass 14, count 0 2006.173.17:44:31.95#ibcon#enter sib2, iclass 14, count 0 2006.173.17:44:31.95#ibcon#flushed, iclass 14, count 0 2006.173.17:44:31.95#ibcon#about to write, iclass 14, count 0 2006.173.17:44:31.95#ibcon#wrote, iclass 14, count 0 2006.173.17:44:31.95#ibcon#about to read 3, iclass 14, count 0 2006.173.17:44:31.99#ibcon#read 3, iclass 14, count 0 2006.173.17:44:31.99#ibcon#about to read 4, iclass 14, count 0 2006.173.17:44:31.99#ibcon#read 4, iclass 14, count 0 2006.173.17:44:31.99#ibcon#about to read 5, iclass 14, count 0 2006.173.17:44:31.99#ibcon#read 5, iclass 14, count 0 2006.173.17:44:31.99#ibcon#about to read 6, iclass 14, count 0 2006.173.17:44:31.99#ibcon#read 6, iclass 14, count 0 2006.173.17:44:31.99#ibcon#end of sib2, iclass 14, count 0 2006.173.17:44:31.99#ibcon#*after write, iclass 14, count 0 2006.173.17:44:31.99#ibcon#*before return 0, iclass 14, count 0 2006.173.17:44:31.99#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.17:44:31.99#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.17:44:31.99#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.17:44:31.99#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.17:44:31.99$vck44/vb=1,4 2006.173.17:44:31.99#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.17:44:31.99#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.17:44:31.99#ibcon#ireg 11 cls_cnt 2 2006.173.17:44:31.99#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.17:44:31.99#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.17:44:31.99#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.17:44:31.99#ibcon#enter wrdev, iclass 16, count 2 2006.173.17:44:31.99#ibcon#first serial, iclass 16, count 2 2006.173.17:44:31.99#ibcon#enter sib2, iclass 16, count 2 2006.173.17:44:31.99#ibcon#flushed, iclass 16, count 2 2006.173.17:44:31.99#ibcon#about to write, iclass 16, count 2 2006.173.17:44:31.99#ibcon#wrote, iclass 16, count 2 2006.173.17:44:31.99#ibcon#about to read 3, iclass 16, count 2 2006.173.17:44:32.01#ibcon#read 3, iclass 16, count 2 2006.173.17:44:32.01#ibcon#about to read 4, iclass 16, count 2 2006.173.17:44:32.01#ibcon#read 4, iclass 16, count 2 2006.173.17:44:32.01#ibcon#about to read 5, iclass 16, count 2 2006.173.17:44:32.01#ibcon#read 5, iclass 16, count 2 2006.173.17:44:32.01#ibcon#about to read 6, iclass 16, count 2 2006.173.17:44:32.01#ibcon#read 6, iclass 16, count 2 2006.173.17:44:32.01#ibcon#end of sib2, iclass 16, count 2 2006.173.17:44:32.01#ibcon#*mode == 0, iclass 16, count 2 2006.173.17:44:32.01#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.17:44:32.01#ibcon#[27=AT01-04\r\n] 2006.173.17:44:32.01#ibcon#*before write, iclass 16, count 2 2006.173.17:44:32.01#ibcon#enter sib2, iclass 16, count 2 2006.173.17:44:32.01#ibcon#flushed, iclass 16, count 2 2006.173.17:44:32.01#ibcon#about to write, iclass 16, count 2 2006.173.17:44:32.01#ibcon#wrote, iclass 16, count 2 2006.173.17:44:32.01#ibcon#about to read 3, iclass 16, count 2 2006.173.17:44:32.04#ibcon#read 3, iclass 16, count 2 2006.173.17:44:32.04#ibcon#about to read 4, iclass 16, count 2 2006.173.17:44:32.04#ibcon#read 4, iclass 16, count 2 2006.173.17:44:32.04#ibcon#about to read 5, iclass 16, count 2 2006.173.17:44:32.04#ibcon#read 5, iclass 16, count 2 2006.173.17:44:32.04#ibcon#about to read 6, iclass 16, count 2 2006.173.17:44:32.04#ibcon#read 6, iclass 16, count 2 2006.173.17:44:32.04#ibcon#end of sib2, iclass 16, count 2 2006.173.17:44:32.04#ibcon#*after write, iclass 16, count 2 2006.173.17:44:32.04#ibcon#*before return 0, iclass 16, count 2 2006.173.17:44:32.04#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.17:44:32.04#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.17:44:32.04#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.17:44:32.04#ibcon#ireg 7 cls_cnt 0 2006.173.17:44:32.04#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.17:44:32.16#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.17:44:32.16#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.17:44:32.16#ibcon#enter wrdev, iclass 16, count 0 2006.173.17:44:32.16#ibcon#first serial, iclass 16, count 0 2006.173.17:44:32.16#ibcon#enter sib2, iclass 16, count 0 2006.173.17:44:32.16#ibcon#flushed, iclass 16, count 0 2006.173.17:44:32.16#ibcon#about to write, iclass 16, count 0 2006.173.17:44:32.16#ibcon#wrote, iclass 16, count 0 2006.173.17:44:32.16#ibcon#about to read 3, iclass 16, count 0 2006.173.17:44:32.18#ibcon#read 3, iclass 16, count 0 2006.173.17:44:32.18#ibcon#about to read 4, iclass 16, count 0 2006.173.17:44:32.18#ibcon#read 4, iclass 16, count 0 2006.173.17:44:32.18#ibcon#about to read 5, iclass 16, count 0 2006.173.17:44:32.18#ibcon#read 5, iclass 16, count 0 2006.173.17:44:32.18#ibcon#about to read 6, iclass 16, count 0 2006.173.17:44:32.18#ibcon#read 6, iclass 16, count 0 2006.173.17:44:32.18#ibcon#end of sib2, iclass 16, count 0 2006.173.17:44:32.18#ibcon#*mode == 0, iclass 16, count 0 2006.173.17:44:32.18#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.17:44:32.18#ibcon#[27=USB\r\n] 2006.173.17:44:32.18#ibcon#*before write, iclass 16, count 0 2006.173.17:44:32.18#ibcon#enter sib2, iclass 16, count 0 2006.173.17:44:32.18#ibcon#flushed, iclass 16, count 0 2006.173.17:44:32.18#ibcon#about to write, iclass 16, count 0 2006.173.17:44:32.18#ibcon#wrote, iclass 16, count 0 2006.173.17:44:32.18#ibcon#about to read 3, iclass 16, count 0 2006.173.17:44:32.21#ibcon#read 3, iclass 16, count 0 2006.173.17:44:32.21#ibcon#about to read 4, iclass 16, count 0 2006.173.17:44:32.21#ibcon#read 4, iclass 16, count 0 2006.173.17:44:32.21#ibcon#about to read 5, iclass 16, count 0 2006.173.17:44:32.21#ibcon#read 5, iclass 16, count 0 2006.173.17:44:32.21#ibcon#about to read 6, iclass 16, count 0 2006.173.17:44:32.21#ibcon#read 6, iclass 16, count 0 2006.173.17:44:32.21#ibcon#end of sib2, iclass 16, count 0 2006.173.17:44:32.21#ibcon#*after write, iclass 16, count 0 2006.173.17:44:32.21#ibcon#*before return 0, iclass 16, count 0 2006.173.17:44:32.21#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.17:44:32.21#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.17:44:32.21#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.17:44:32.21#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.17:44:32.21$vck44/vblo=2,634.99 2006.173.17:44:32.21#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.17:44:32.21#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.17:44:32.21#ibcon#ireg 17 cls_cnt 0 2006.173.17:44:32.21#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.17:44:32.21#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.17:44:32.21#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.17:44:32.21#ibcon#enter wrdev, iclass 18, count 0 2006.173.17:44:32.21#ibcon#first serial, iclass 18, count 0 2006.173.17:44:32.21#ibcon#enter sib2, iclass 18, count 0 2006.173.17:44:32.21#ibcon#flushed, iclass 18, count 0 2006.173.17:44:32.21#ibcon#about to write, iclass 18, count 0 2006.173.17:44:32.21#ibcon#wrote, iclass 18, count 0 2006.173.17:44:32.21#ibcon#about to read 3, iclass 18, count 0 2006.173.17:44:32.23#ibcon#read 3, iclass 18, count 0 2006.173.17:44:32.23#ibcon#about to read 4, iclass 18, count 0 2006.173.17:44:32.23#ibcon#read 4, iclass 18, count 0 2006.173.17:44:32.23#ibcon#about to read 5, iclass 18, count 0 2006.173.17:44:32.23#ibcon#read 5, iclass 18, count 0 2006.173.17:44:32.23#ibcon#about to read 6, iclass 18, count 0 2006.173.17:44:32.23#ibcon#read 6, iclass 18, count 0 2006.173.17:44:32.23#ibcon#end of sib2, iclass 18, count 0 2006.173.17:44:32.23#ibcon#*mode == 0, iclass 18, count 0 2006.173.17:44:32.23#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.17:44:32.23#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.17:44:32.23#ibcon#*before write, iclass 18, count 0 2006.173.17:44:32.23#ibcon#enter sib2, iclass 18, count 0 2006.173.17:44:32.23#ibcon#flushed, iclass 18, count 0 2006.173.17:44:32.23#ibcon#about to write, iclass 18, count 0 2006.173.17:44:32.23#ibcon#wrote, iclass 18, count 0 2006.173.17:44:32.23#ibcon#about to read 3, iclass 18, count 0 2006.173.17:44:32.27#ibcon#read 3, iclass 18, count 0 2006.173.17:44:32.27#ibcon#about to read 4, iclass 18, count 0 2006.173.17:44:32.27#ibcon#read 4, iclass 18, count 0 2006.173.17:44:32.27#ibcon#about to read 5, iclass 18, count 0 2006.173.17:44:32.27#ibcon#read 5, iclass 18, count 0 2006.173.17:44:32.27#ibcon#about to read 6, iclass 18, count 0 2006.173.17:44:32.27#ibcon#read 6, iclass 18, count 0 2006.173.17:44:32.27#ibcon#end of sib2, iclass 18, count 0 2006.173.17:44:32.27#ibcon#*after write, iclass 18, count 0 2006.173.17:44:32.27#ibcon#*before return 0, iclass 18, count 0 2006.173.17:44:32.27#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.17:44:32.27#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.17:44:32.27#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.17:44:32.27#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.17:44:32.27$vck44/vb=2,4 2006.173.17:44:32.27#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.17:44:32.27#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.17:44:32.27#ibcon#ireg 11 cls_cnt 2 2006.173.17:44:32.27#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.17:44:32.33#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.17:44:32.33#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.17:44:32.33#ibcon#enter wrdev, iclass 20, count 2 2006.173.17:44:32.33#ibcon#first serial, iclass 20, count 2 2006.173.17:44:32.33#ibcon#enter sib2, iclass 20, count 2 2006.173.17:44:32.33#ibcon#flushed, iclass 20, count 2 2006.173.17:44:32.33#ibcon#about to write, iclass 20, count 2 2006.173.17:44:32.33#ibcon#wrote, iclass 20, count 2 2006.173.17:44:32.33#ibcon#about to read 3, iclass 20, count 2 2006.173.17:44:32.35#ibcon#read 3, iclass 20, count 2 2006.173.17:44:32.35#ibcon#about to read 4, iclass 20, count 2 2006.173.17:44:32.35#ibcon#read 4, iclass 20, count 2 2006.173.17:44:32.35#ibcon#about to read 5, iclass 20, count 2 2006.173.17:44:32.35#ibcon#read 5, iclass 20, count 2 2006.173.17:44:32.35#ibcon#about to read 6, iclass 20, count 2 2006.173.17:44:32.35#ibcon#read 6, iclass 20, count 2 2006.173.17:44:32.35#ibcon#end of sib2, iclass 20, count 2 2006.173.17:44:32.35#ibcon#*mode == 0, iclass 20, count 2 2006.173.17:44:32.35#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.17:44:32.35#ibcon#[27=AT02-04\r\n] 2006.173.17:44:32.35#ibcon#*before write, iclass 20, count 2 2006.173.17:44:32.35#ibcon#enter sib2, iclass 20, count 2 2006.173.17:44:32.35#ibcon#flushed, iclass 20, count 2 2006.173.17:44:32.35#ibcon#about to write, iclass 20, count 2 2006.173.17:44:32.35#ibcon#wrote, iclass 20, count 2 2006.173.17:44:32.35#ibcon#about to read 3, iclass 20, count 2 2006.173.17:44:32.38#ibcon#read 3, iclass 20, count 2 2006.173.17:44:32.38#ibcon#about to read 4, iclass 20, count 2 2006.173.17:44:32.38#ibcon#read 4, iclass 20, count 2 2006.173.17:44:32.38#ibcon#about to read 5, iclass 20, count 2 2006.173.17:44:32.38#ibcon#read 5, iclass 20, count 2 2006.173.17:44:32.38#ibcon#about to read 6, iclass 20, count 2 2006.173.17:44:32.38#ibcon#read 6, iclass 20, count 2 2006.173.17:44:32.38#ibcon#end of sib2, iclass 20, count 2 2006.173.17:44:32.38#ibcon#*after write, iclass 20, count 2 2006.173.17:44:32.38#ibcon#*before return 0, iclass 20, count 2 2006.173.17:44:32.38#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.17:44:32.38#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.17:44:32.38#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.17:44:32.38#ibcon#ireg 7 cls_cnt 0 2006.173.17:44:32.38#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.17:44:32.50#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.17:44:32.50#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.17:44:32.50#ibcon#enter wrdev, iclass 20, count 0 2006.173.17:44:32.50#ibcon#first serial, iclass 20, count 0 2006.173.17:44:32.50#ibcon#enter sib2, iclass 20, count 0 2006.173.17:44:32.50#ibcon#flushed, iclass 20, count 0 2006.173.17:44:32.50#ibcon#about to write, iclass 20, count 0 2006.173.17:44:32.50#ibcon#wrote, iclass 20, count 0 2006.173.17:44:32.50#ibcon#about to read 3, iclass 20, count 0 2006.173.17:44:32.52#ibcon#read 3, iclass 20, count 0 2006.173.17:44:32.52#ibcon#about to read 4, iclass 20, count 0 2006.173.17:44:32.52#ibcon#read 4, iclass 20, count 0 2006.173.17:44:32.52#ibcon#about to read 5, iclass 20, count 0 2006.173.17:44:32.52#ibcon#read 5, iclass 20, count 0 2006.173.17:44:32.52#ibcon#about to read 6, iclass 20, count 0 2006.173.17:44:32.52#ibcon#read 6, iclass 20, count 0 2006.173.17:44:32.52#ibcon#end of sib2, iclass 20, count 0 2006.173.17:44:32.52#ibcon#*mode == 0, iclass 20, count 0 2006.173.17:44:32.52#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.17:44:32.52#ibcon#[27=USB\r\n] 2006.173.17:44:32.52#ibcon#*before write, iclass 20, count 0 2006.173.17:44:32.52#ibcon#enter sib2, iclass 20, count 0 2006.173.17:44:32.52#ibcon#flushed, iclass 20, count 0 2006.173.17:44:32.52#ibcon#about to write, iclass 20, count 0 2006.173.17:44:32.52#ibcon#wrote, iclass 20, count 0 2006.173.17:44:32.52#ibcon#about to read 3, iclass 20, count 0 2006.173.17:44:32.55#ibcon#read 3, iclass 20, count 0 2006.173.17:44:32.55#ibcon#about to read 4, iclass 20, count 0 2006.173.17:44:32.55#ibcon#read 4, iclass 20, count 0 2006.173.17:44:32.55#ibcon#about to read 5, iclass 20, count 0 2006.173.17:44:32.55#ibcon#read 5, iclass 20, count 0 2006.173.17:44:32.55#ibcon#about to read 6, iclass 20, count 0 2006.173.17:44:32.55#ibcon#read 6, iclass 20, count 0 2006.173.17:44:32.55#ibcon#end of sib2, iclass 20, count 0 2006.173.17:44:32.55#ibcon#*after write, iclass 20, count 0 2006.173.17:44:32.55#ibcon#*before return 0, iclass 20, count 0 2006.173.17:44:32.55#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.17:44:32.55#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.17:44:32.55#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.17:44:32.55#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.17:44:32.55$vck44/vblo=3,649.99 2006.173.17:44:32.55#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.17:44:32.55#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.17:44:32.55#ibcon#ireg 17 cls_cnt 0 2006.173.17:44:32.55#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.17:44:32.55#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.17:44:32.55#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.17:44:32.55#ibcon#enter wrdev, iclass 22, count 0 2006.173.17:44:32.55#ibcon#first serial, iclass 22, count 0 2006.173.17:44:32.55#ibcon#enter sib2, iclass 22, count 0 2006.173.17:44:32.55#ibcon#flushed, iclass 22, count 0 2006.173.17:44:32.55#ibcon#about to write, iclass 22, count 0 2006.173.17:44:32.55#ibcon#wrote, iclass 22, count 0 2006.173.17:44:32.55#ibcon#about to read 3, iclass 22, count 0 2006.173.17:44:32.57#ibcon#read 3, iclass 22, count 0 2006.173.17:44:32.57#ibcon#about to read 4, iclass 22, count 0 2006.173.17:44:32.57#ibcon#read 4, iclass 22, count 0 2006.173.17:44:32.57#ibcon#about to read 5, iclass 22, count 0 2006.173.17:44:32.57#ibcon#read 5, iclass 22, count 0 2006.173.17:44:32.57#ibcon#about to read 6, iclass 22, count 0 2006.173.17:44:32.57#ibcon#read 6, iclass 22, count 0 2006.173.17:44:32.57#ibcon#end of sib2, iclass 22, count 0 2006.173.17:44:32.57#ibcon#*mode == 0, iclass 22, count 0 2006.173.17:44:32.57#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.17:44:32.57#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.17:44:32.57#ibcon#*before write, iclass 22, count 0 2006.173.17:44:32.57#ibcon#enter sib2, iclass 22, count 0 2006.173.17:44:32.57#ibcon#flushed, iclass 22, count 0 2006.173.17:44:32.57#ibcon#about to write, iclass 22, count 0 2006.173.17:44:32.57#ibcon#wrote, iclass 22, count 0 2006.173.17:44:32.57#ibcon#about to read 3, iclass 22, count 0 2006.173.17:44:32.61#ibcon#read 3, iclass 22, count 0 2006.173.17:44:32.61#ibcon#about to read 4, iclass 22, count 0 2006.173.17:44:32.61#ibcon#read 4, iclass 22, count 0 2006.173.17:44:32.61#ibcon#about to read 5, iclass 22, count 0 2006.173.17:44:32.61#ibcon#read 5, iclass 22, count 0 2006.173.17:44:32.61#ibcon#about to read 6, iclass 22, count 0 2006.173.17:44:32.61#ibcon#read 6, iclass 22, count 0 2006.173.17:44:32.61#ibcon#end of sib2, iclass 22, count 0 2006.173.17:44:32.61#ibcon#*after write, iclass 22, count 0 2006.173.17:44:32.61#ibcon#*before return 0, iclass 22, count 0 2006.173.17:44:32.61#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.17:44:32.61#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.17:44:32.61#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.17:44:32.61#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.17:44:32.61$vck44/vb=3,4 2006.173.17:44:32.61#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.17:44:32.61#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.17:44:32.61#ibcon#ireg 11 cls_cnt 2 2006.173.17:44:32.61#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.17:44:32.67#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.17:44:32.67#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.17:44:32.67#ibcon#enter wrdev, iclass 24, count 2 2006.173.17:44:32.67#ibcon#first serial, iclass 24, count 2 2006.173.17:44:32.67#ibcon#enter sib2, iclass 24, count 2 2006.173.17:44:32.67#ibcon#flushed, iclass 24, count 2 2006.173.17:44:32.67#ibcon#about to write, iclass 24, count 2 2006.173.17:44:32.67#ibcon#wrote, iclass 24, count 2 2006.173.17:44:32.67#ibcon#about to read 3, iclass 24, count 2 2006.173.17:44:32.69#ibcon#read 3, iclass 24, count 2 2006.173.17:44:32.69#ibcon#about to read 4, iclass 24, count 2 2006.173.17:44:32.69#ibcon#read 4, iclass 24, count 2 2006.173.17:44:32.69#ibcon#about to read 5, iclass 24, count 2 2006.173.17:44:32.69#ibcon#read 5, iclass 24, count 2 2006.173.17:44:32.69#ibcon#about to read 6, iclass 24, count 2 2006.173.17:44:32.69#ibcon#read 6, iclass 24, count 2 2006.173.17:44:32.69#ibcon#end of sib2, iclass 24, count 2 2006.173.17:44:32.69#ibcon#*mode == 0, iclass 24, count 2 2006.173.17:44:32.69#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.17:44:32.69#ibcon#[27=AT03-04\r\n] 2006.173.17:44:32.69#ibcon#*before write, iclass 24, count 2 2006.173.17:44:32.69#ibcon#enter sib2, iclass 24, count 2 2006.173.17:44:32.69#ibcon#flushed, iclass 24, count 2 2006.173.17:44:32.69#ibcon#about to write, iclass 24, count 2 2006.173.17:44:32.69#ibcon#wrote, iclass 24, count 2 2006.173.17:44:32.69#ibcon#about to read 3, iclass 24, count 2 2006.173.17:44:32.72#ibcon#read 3, iclass 24, count 2 2006.173.17:44:32.72#ibcon#about to read 4, iclass 24, count 2 2006.173.17:44:32.72#ibcon#read 4, iclass 24, count 2 2006.173.17:44:32.72#ibcon#about to read 5, iclass 24, count 2 2006.173.17:44:32.72#ibcon#read 5, iclass 24, count 2 2006.173.17:44:32.72#ibcon#about to read 6, iclass 24, count 2 2006.173.17:44:32.72#ibcon#read 6, iclass 24, count 2 2006.173.17:44:32.72#ibcon#end of sib2, iclass 24, count 2 2006.173.17:44:32.72#ibcon#*after write, iclass 24, count 2 2006.173.17:44:32.72#ibcon#*before return 0, iclass 24, count 2 2006.173.17:44:32.72#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.17:44:32.72#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.17:44:32.72#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.17:44:32.72#ibcon#ireg 7 cls_cnt 0 2006.173.17:44:32.72#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.17:44:32.84#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.17:44:32.84#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.17:44:32.84#ibcon#enter wrdev, iclass 24, count 0 2006.173.17:44:32.84#ibcon#first serial, iclass 24, count 0 2006.173.17:44:32.84#ibcon#enter sib2, iclass 24, count 0 2006.173.17:44:32.84#ibcon#flushed, iclass 24, count 0 2006.173.17:44:32.84#ibcon#about to write, iclass 24, count 0 2006.173.17:44:32.84#ibcon#wrote, iclass 24, count 0 2006.173.17:44:32.84#ibcon#about to read 3, iclass 24, count 0 2006.173.17:44:32.86#ibcon#read 3, iclass 24, count 0 2006.173.17:44:32.86#ibcon#about to read 4, iclass 24, count 0 2006.173.17:44:32.86#ibcon#read 4, iclass 24, count 0 2006.173.17:44:32.86#ibcon#about to read 5, iclass 24, count 0 2006.173.17:44:32.86#ibcon#read 5, iclass 24, count 0 2006.173.17:44:32.86#ibcon#about to read 6, iclass 24, count 0 2006.173.17:44:32.86#ibcon#read 6, iclass 24, count 0 2006.173.17:44:32.86#ibcon#end of sib2, iclass 24, count 0 2006.173.17:44:32.86#ibcon#*mode == 0, iclass 24, count 0 2006.173.17:44:32.86#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.17:44:32.86#ibcon#[27=USB\r\n] 2006.173.17:44:32.86#ibcon#*before write, iclass 24, count 0 2006.173.17:44:32.86#ibcon#enter sib2, iclass 24, count 0 2006.173.17:44:32.86#ibcon#flushed, iclass 24, count 0 2006.173.17:44:32.86#ibcon#about to write, iclass 24, count 0 2006.173.17:44:32.86#ibcon#wrote, iclass 24, count 0 2006.173.17:44:32.86#ibcon#about to read 3, iclass 24, count 0 2006.173.17:44:32.89#ibcon#read 3, iclass 24, count 0 2006.173.17:44:32.89#ibcon#about to read 4, iclass 24, count 0 2006.173.17:44:32.89#ibcon#read 4, iclass 24, count 0 2006.173.17:44:32.89#ibcon#about to read 5, iclass 24, count 0 2006.173.17:44:32.89#ibcon#read 5, iclass 24, count 0 2006.173.17:44:32.89#ibcon#about to read 6, iclass 24, count 0 2006.173.17:44:32.89#ibcon#read 6, iclass 24, count 0 2006.173.17:44:32.89#ibcon#end of sib2, iclass 24, count 0 2006.173.17:44:32.89#ibcon#*after write, iclass 24, count 0 2006.173.17:44:32.89#ibcon#*before return 0, iclass 24, count 0 2006.173.17:44:32.89#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.17:44:32.89#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.17:44:32.89#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.17:44:32.89#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.17:44:32.89$vck44/vblo=4,679.99 2006.173.17:44:32.89#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.17:44:32.89#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.17:44:32.89#ibcon#ireg 17 cls_cnt 0 2006.173.17:44:32.89#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.17:44:32.89#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.17:44:32.89#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.17:44:32.89#ibcon#enter wrdev, iclass 26, count 0 2006.173.17:44:32.89#ibcon#first serial, iclass 26, count 0 2006.173.17:44:32.89#ibcon#enter sib2, iclass 26, count 0 2006.173.17:44:32.89#ibcon#flushed, iclass 26, count 0 2006.173.17:44:32.89#ibcon#about to write, iclass 26, count 0 2006.173.17:44:32.89#ibcon#wrote, iclass 26, count 0 2006.173.17:44:32.89#ibcon#about to read 3, iclass 26, count 0 2006.173.17:44:32.91#ibcon#read 3, iclass 26, count 0 2006.173.17:44:32.91#ibcon#about to read 4, iclass 26, count 0 2006.173.17:44:32.91#ibcon#read 4, iclass 26, count 0 2006.173.17:44:32.91#ibcon#about to read 5, iclass 26, count 0 2006.173.17:44:32.91#ibcon#read 5, iclass 26, count 0 2006.173.17:44:32.91#ibcon#about to read 6, iclass 26, count 0 2006.173.17:44:32.91#ibcon#read 6, iclass 26, count 0 2006.173.17:44:32.91#ibcon#end of sib2, iclass 26, count 0 2006.173.17:44:32.91#ibcon#*mode == 0, iclass 26, count 0 2006.173.17:44:32.91#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.17:44:32.91#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.17:44:32.91#ibcon#*before write, iclass 26, count 0 2006.173.17:44:32.91#ibcon#enter sib2, iclass 26, count 0 2006.173.17:44:32.91#ibcon#flushed, iclass 26, count 0 2006.173.17:44:32.91#ibcon#about to write, iclass 26, count 0 2006.173.17:44:32.91#ibcon#wrote, iclass 26, count 0 2006.173.17:44:32.91#ibcon#about to read 3, iclass 26, count 0 2006.173.17:44:32.95#ibcon#read 3, iclass 26, count 0 2006.173.17:44:32.95#ibcon#about to read 4, iclass 26, count 0 2006.173.17:44:32.95#ibcon#read 4, iclass 26, count 0 2006.173.17:44:32.95#ibcon#about to read 5, iclass 26, count 0 2006.173.17:44:32.95#ibcon#read 5, iclass 26, count 0 2006.173.17:44:32.95#ibcon#about to read 6, iclass 26, count 0 2006.173.17:44:32.95#ibcon#read 6, iclass 26, count 0 2006.173.17:44:32.95#ibcon#end of sib2, iclass 26, count 0 2006.173.17:44:32.95#ibcon#*after write, iclass 26, count 0 2006.173.17:44:32.95#ibcon#*before return 0, iclass 26, count 0 2006.173.17:44:32.95#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.17:44:32.95#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.17:44:32.95#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.17:44:32.95#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.17:44:32.95$vck44/vb=4,4 2006.173.17:44:32.95#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.17:44:32.95#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.17:44:32.95#ibcon#ireg 11 cls_cnt 2 2006.173.17:44:32.95#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.17:44:33.01#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.17:44:33.01#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.17:44:33.01#ibcon#enter wrdev, iclass 28, count 2 2006.173.17:44:33.01#ibcon#first serial, iclass 28, count 2 2006.173.17:44:33.01#ibcon#enter sib2, iclass 28, count 2 2006.173.17:44:33.01#ibcon#flushed, iclass 28, count 2 2006.173.17:44:33.01#ibcon#about to write, iclass 28, count 2 2006.173.17:44:33.01#ibcon#wrote, iclass 28, count 2 2006.173.17:44:33.01#ibcon#about to read 3, iclass 28, count 2 2006.173.17:44:33.03#ibcon#read 3, iclass 28, count 2 2006.173.17:44:33.03#ibcon#about to read 4, iclass 28, count 2 2006.173.17:44:33.03#ibcon#read 4, iclass 28, count 2 2006.173.17:44:33.03#ibcon#about to read 5, iclass 28, count 2 2006.173.17:44:33.03#ibcon#read 5, iclass 28, count 2 2006.173.17:44:33.03#ibcon#about to read 6, iclass 28, count 2 2006.173.17:44:33.03#ibcon#read 6, iclass 28, count 2 2006.173.17:44:33.03#ibcon#end of sib2, iclass 28, count 2 2006.173.17:44:33.03#ibcon#*mode == 0, iclass 28, count 2 2006.173.17:44:33.03#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.17:44:33.03#ibcon#[27=AT04-04\r\n] 2006.173.17:44:33.03#ibcon#*before write, iclass 28, count 2 2006.173.17:44:33.03#ibcon#enter sib2, iclass 28, count 2 2006.173.17:44:33.03#ibcon#flushed, iclass 28, count 2 2006.173.17:44:33.03#ibcon#about to write, iclass 28, count 2 2006.173.17:44:33.03#ibcon#wrote, iclass 28, count 2 2006.173.17:44:33.03#ibcon#about to read 3, iclass 28, count 2 2006.173.17:44:33.06#ibcon#read 3, iclass 28, count 2 2006.173.17:44:33.06#ibcon#about to read 4, iclass 28, count 2 2006.173.17:44:33.06#ibcon#read 4, iclass 28, count 2 2006.173.17:44:33.06#ibcon#about to read 5, iclass 28, count 2 2006.173.17:44:33.06#ibcon#read 5, iclass 28, count 2 2006.173.17:44:33.06#ibcon#about to read 6, iclass 28, count 2 2006.173.17:44:33.06#ibcon#read 6, iclass 28, count 2 2006.173.17:44:33.06#ibcon#end of sib2, iclass 28, count 2 2006.173.17:44:33.06#ibcon#*after write, iclass 28, count 2 2006.173.17:44:33.06#ibcon#*before return 0, iclass 28, count 2 2006.173.17:44:33.06#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.17:44:33.06#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.17:44:33.06#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.17:44:33.06#ibcon#ireg 7 cls_cnt 0 2006.173.17:44:33.06#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.17:44:33.18#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.17:44:33.18#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.17:44:33.18#ibcon#enter wrdev, iclass 28, count 0 2006.173.17:44:33.18#ibcon#first serial, iclass 28, count 0 2006.173.17:44:33.18#ibcon#enter sib2, iclass 28, count 0 2006.173.17:44:33.18#ibcon#flushed, iclass 28, count 0 2006.173.17:44:33.18#ibcon#about to write, iclass 28, count 0 2006.173.17:44:33.18#ibcon#wrote, iclass 28, count 0 2006.173.17:44:33.18#ibcon#about to read 3, iclass 28, count 0 2006.173.17:44:33.20#ibcon#read 3, iclass 28, count 0 2006.173.17:44:33.20#ibcon#about to read 4, iclass 28, count 0 2006.173.17:44:33.20#ibcon#read 4, iclass 28, count 0 2006.173.17:44:33.20#ibcon#about to read 5, iclass 28, count 0 2006.173.17:44:33.20#ibcon#read 5, iclass 28, count 0 2006.173.17:44:33.20#ibcon#about to read 6, iclass 28, count 0 2006.173.17:44:33.20#ibcon#read 6, iclass 28, count 0 2006.173.17:44:33.20#ibcon#end of sib2, iclass 28, count 0 2006.173.17:44:33.20#ibcon#*mode == 0, iclass 28, count 0 2006.173.17:44:33.20#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.17:44:33.20#ibcon#[27=USB\r\n] 2006.173.17:44:33.20#ibcon#*before write, iclass 28, count 0 2006.173.17:44:33.20#ibcon#enter sib2, iclass 28, count 0 2006.173.17:44:33.20#ibcon#flushed, iclass 28, count 0 2006.173.17:44:33.20#ibcon#about to write, iclass 28, count 0 2006.173.17:44:33.20#ibcon#wrote, iclass 28, count 0 2006.173.17:44:33.20#ibcon#about to read 3, iclass 28, count 0 2006.173.17:44:33.23#ibcon#read 3, iclass 28, count 0 2006.173.17:44:33.23#ibcon#about to read 4, iclass 28, count 0 2006.173.17:44:33.23#ibcon#read 4, iclass 28, count 0 2006.173.17:44:33.23#ibcon#about to read 5, iclass 28, count 0 2006.173.17:44:33.23#ibcon#read 5, iclass 28, count 0 2006.173.17:44:33.23#ibcon#about to read 6, iclass 28, count 0 2006.173.17:44:33.23#ibcon#read 6, iclass 28, count 0 2006.173.17:44:33.23#ibcon#end of sib2, iclass 28, count 0 2006.173.17:44:33.23#ibcon#*after write, iclass 28, count 0 2006.173.17:44:33.23#ibcon#*before return 0, iclass 28, count 0 2006.173.17:44:33.23#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.17:44:33.23#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.17:44:33.23#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.17:44:33.23#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.17:44:33.23$vck44/vblo=5,709.99 2006.173.17:44:33.23#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.17:44:33.23#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.17:44:33.23#ibcon#ireg 17 cls_cnt 0 2006.173.17:44:33.23#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.17:44:33.23#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.17:44:33.23#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.17:44:33.23#ibcon#enter wrdev, iclass 30, count 0 2006.173.17:44:33.23#ibcon#first serial, iclass 30, count 0 2006.173.17:44:33.23#ibcon#enter sib2, iclass 30, count 0 2006.173.17:44:33.23#ibcon#flushed, iclass 30, count 0 2006.173.17:44:33.23#ibcon#about to write, iclass 30, count 0 2006.173.17:44:33.23#ibcon#wrote, iclass 30, count 0 2006.173.17:44:33.23#ibcon#about to read 3, iclass 30, count 0 2006.173.17:44:33.25#ibcon#read 3, iclass 30, count 0 2006.173.17:44:33.25#ibcon#about to read 4, iclass 30, count 0 2006.173.17:44:33.25#ibcon#read 4, iclass 30, count 0 2006.173.17:44:33.25#ibcon#about to read 5, iclass 30, count 0 2006.173.17:44:33.25#ibcon#read 5, iclass 30, count 0 2006.173.17:44:33.25#ibcon#about to read 6, iclass 30, count 0 2006.173.17:44:33.25#ibcon#read 6, iclass 30, count 0 2006.173.17:44:33.25#ibcon#end of sib2, iclass 30, count 0 2006.173.17:44:33.25#ibcon#*mode == 0, iclass 30, count 0 2006.173.17:44:33.25#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.17:44:33.25#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.17:44:33.25#ibcon#*before write, iclass 30, count 0 2006.173.17:44:33.25#ibcon#enter sib2, iclass 30, count 0 2006.173.17:44:33.25#ibcon#flushed, iclass 30, count 0 2006.173.17:44:33.25#ibcon#about to write, iclass 30, count 0 2006.173.17:44:33.25#ibcon#wrote, iclass 30, count 0 2006.173.17:44:33.25#ibcon#about to read 3, iclass 30, count 0 2006.173.17:44:33.29#ibcon#read 3, iclass 30, count 0 2006.173.17:44:33.29#ibcon#about to read 4, iclass 30, count 0 2006.173.17:44:33.29#ibcon#read 4, iclass 30, count 0 2006.173.17:44:33.29#ibcon#about to read 5, iclass 30, count 0 2006.173.17:44:33.29#ibcon#read 5, iclass 30, count 0 2006.173.17:44:33.29#ibcon#about to read 6, iclass 30, count 0 2006.173.17:44:33.29#ibcon#read 6, iclass 30, count 0 2006.173.17:44:33.29#ibcon#end of sib2, iclass 30, count 0 2006.173.17:44:33.29#ibcon#*after write, iclass 30, count 0 2006.173.17:44:33.29#ibcon#*before return 0, iclass 30, count 0 2006.173.17:44:33.29#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.17:44:33.29#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.17:44:33.29#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.17:44:33.29#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.17:44:33.29$vck44/vb=5,4 2006.173.17:44:33.29#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.173.17:44:33.29#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.173.17:44:33.29#ibcon#ireg 11 cls_cnt 2 2006.173.17:44:33.29#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.17:44:33.35#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.17:44:33.35#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.17:44:33.35#ibcon#enter wrdev, iclass 32, count 2 2006.173.17:44:33.35#ibcon#first serial, iclass 32, count 2 2006.173.17:44:33.35#ibcon#enter sib2, iclass 32, count 2 2006.173.17:44:33.35#ibcon#flushed, iclass 32, count 2 2006.173.17:44:33.35#ibcon#about to write, iclass 32, count 2 2006.173.17:44:33.35#ibcon#wrote, iclass 32, count 2 2006.173.17:44:33.35#ibcon#about to read 3, iclass 32, count 2 2006.173.17:44:33.37#ibcon#read 3, iclass 32, count 2 2006.173.17:44:33.37#ibcon#about to read 4, iclass 32, count 2 2006.173.17:44:33.37#ibcon#read 4, iclass 32, count 2 2006.173.17:44:33.37#ibcon#about to read 5, iclass 32, count 2 2006.173.17:44:33.37#ibcon#read 5, iclass 32, count 2 2006.173.17:44:33.37#ibcon#about to read 6, iclass 32, count 2 2006.173.17:44:33.37#ibcon#read 6, iclass 32, count 2 2006.173.17:44:33.37#ibcon#end of sib2, iclass 32, count 2 2006.173.17:44:33.37#ibcon#*mode == 0, iclass 32, count 2 2006.173.17:44:33.37#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.173.17:44:33.37#ibcon#[27=AT05-04\r\n] 2006.173.17:44:33.37#ibcon#*before write, iclass 32, count 2 2006.173.17:44:33.37#ibcon#enter sib2, iclass 32, count 2 2006.173.17:44:33.37#ibcon#flushed, iclass 32, count 2 2006.173.17:44:33.37#ibcon#about to write, iclass 32, count 2 2006.173.17:44:33.37#ibcon#wrote, iclass 32, count 2 2006.173.17:44:33.37#ibcon#about to read 3, iclass 32, count 2 2006.173.17:44:33.40#ibcon#read 3, iclass 32, count 2 2006.173.17:44:33.40#ibcon#about to read 4, iclass 32, count 2 2006.173.17:44:33.40#ibcon#read 4, iclass 32, count 2 2006.173.17:44:33.40#ibcon#about to read 5, iclass 32, count 2 2006.173.17:44:33.40#ibcon#read 5, iclass 32, count 2 2006.173.17:44:33.40#ibcon#about to read 6, iclass 32, count 2 2006.173.17:44:33.40#ibcon#read 6, iclass 32, count 2 2006.173.17:44:33.40#ibcon#end of sib2, iclass 32, count 2 2006.173.17:44:33.40#ibcon#*after write, iclass 32, count 2 2006.173.17:44:33.40#ibcon#*before return 0, iclass 32, count 2 2006.173.17:44:33.40#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.17:44:33.40#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.173.17:44:33.40#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.173.17:44:33.40#ibcon#ireg 7 cls_cnt 0 2006.173.17:44:33.40#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.17:44:33.52#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.17:44:33.52#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.17:44:33.52#ibcon#enter wrdev, iclass 32, count 0 2006.173.17:44:33.52#ibcon#first serial, iclass 32, count 0 2006.173.17:44:33.52#ibcon#enter sib2, iclass 32, count 0 2006.173.17:44:33.52#ibcon#flushed, iclass 32, count 0 2006.173.17:44:33.52#ibcon#about to write, iclass 32, count 0 2006.173.17:44:33.52#ibcon#wrote, iclass 32, count 0 2006.173.17:44:33.52#ibcon#about to read 3, iclass 32, count 0 2006.173.17:44:33.54#ibcon#read 3, iclass 32, count 0 2006.173.17:44:33.54#ibcon#about to read 4, iclass 32, count 0 2006.173.17:44:33.54#ibcon#read 4, iclass 32, count 0 2006.173.17:44:33.54#ibcon#about to read 5, iclass 32, count 0 2006.173.17:44:33.54#ibcon#read 5, iclass 32, count 0 2006.173.17:44:33.54#ibcon#about to read 6, iclass 32, count 0 2006.173.17:44:33.54#ibcon#read 6, iclass 32, count 0 2006.173.17:44:33.54#ibcon#end of sib2, iclass 32, count 0 2006.173.17:44:33.54#ibcon#*mode == 0, iclass 32, count 0 2006.173.17:44:33.54#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.17:44:33.54#ibcon#[27=USB\r\n] 2006.173.17:44:33.54#ibcon#*before write, iclass 32, count 0 2006.173.17:44:33.54#ibcon#enter sib2, iclass 32, count 0 2006.173.17:44:33.54#ibcon#flushed, iclass 32, count 0 2006.173.17:44:33.54#ibcon#about to write, iclass 32, count 0 2006.173.17:44:33.54#ibcon#wrote, iclass 32, count 0 2006.173.17:44:33.54#ibcon#about to read 3, iclass 32, count 0 2006.173.17:44:33.57#ibcon#read 3, iclass 32, count 0 2006.173.17:44:33.57#ibcon#about to read 4, iclass 32, count 0 2006.173.17:44:33.57#ibcon#read 4, iclass 32, count 0 2006.173.17:44:33.57#ibcon#about to read 5, iclass 32, count 0 2006.173.17:44:33.57#ibcon#read 5, iclass 32, count 0 2006.173.17:44:33.57#ibcon#about to read 6, iclass 32, count 0 2006.173.17:44:33.57#ibcon#read 6, iclass 32, count 0 2006.173.17:44:33.57#ibcon#end of sib2, iclass 32, count 0 2006.173.17:44:33.57#ibcon#*after write, iclass 32, count 0 2006.173.17:44:33.57#ibcon#*before return 0, iclass 32, count 0 2006.173.17:44:33.57#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.17:44:33.57#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.173.17:44:33.57#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.17:44:33.57#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.17:44:33.57$vck44/vblo=6,719.99 2006.173.17:44:33.57#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.17:44:33.57#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.17:44:33.57#ibcon#ireg 17 cls_cnt 0 2006.173.17:44:33.57#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.17:44:33.57#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.17:44:33.57#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.17:44:33.57#ibcon#enter wrdev, iclass 34, count 0 2006.173.17:44:33.57#ibcon#first serial, iclass 34, count 0 2006.173.17:44:33.57#ibcon#enter sib2, iclass 34, count 0 2006.173.17:44:33.57#ibcon#flushed, iclass 34, count 0 2006.173.17:44:33.57#ibcon#about to write, iclass 34, count 0 2006.173.17:44:33.57#ibcon#wrote, iclass 34, count 0 2006.173.17:44:33.57#ibcon#about to read 3, iclass 34, count 0 2006.173.17:44:33.59#ibcon#read 3, iclass 34, count 0 2006.173.17:44:33.59#ibcon#about to read 4, iclass 34, count 0 2006.173.17:44:33.59#ibcon#read 4, iclass 34, count 0 2006.173.17:44:33.59#ibcon#about to read 5, iclass 34, count 0 2006.173.17:44:33.59#ibcon#read 5, iclass 34, count 0 2006.173.17:44:33.59#ibcon#about to read 6, iclass 34, count 0 2006.173.17:44:33.59#ibcon#read 6, iclass 34, count 0 2006.173.17:44:33.59#ibcon#end of sib2, iclass 34, count 0 2006.173.17:44:33.59#ibcon#*mode == 0, iclass 34, count 0 2006.173.17:44:33.59#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.17:44:33.59#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.17:44:33.59#ibcon#*before write, iclass 34, count 0 2006.173.17:44:33.59#ibcon#enter sib2, iclass 34, count 0 2006.173.17:44:33.59#ibcon#flushed, iclass 34, count 0 2006.173.17:44:33.59#ibcon#about to write, iclass 34, count 0 2006.173.17:44:33.59#ibcon#wrote, iclass 34, count 0 2006.173.17:44:33.59#ibcon#about to read 3, iclass 34, count 0 2006.173.17:44:33.63#ibcon#read 3, iclass 34, count 0 2006.173.17:44:33.63#ibcon#about to read 4, iclass 34, count 0 2006.173.17:44:33.63#ibcon#read 4, iclass 34, count 0 2006.173.17:44:33.63#ibcon#about to read 5, iclass 34, count 0 2006.173.17:44:33.63#ibcon#read 5, iclass 34, count 0 2006.173.17:44:33.63#ibcon#about to read 6, iclass 34, count 0 2006.173.17:44:33.63#ibcon#read 6, iclass 34, count 0 2006.173.17:44:33.63#ibcon#end of sib2, iclass 34, count 0 2006.173.17:44:33.63#ibcon#*after write, iclass 34, count 0 2006.173.17:44:33.63#ibcon#*before return 0, iclass 34, count 0 2006.173.17:44:33.63#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.17:44:33.63#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.17:44:33.63#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.17:44:33.63#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.17:44:33.63$vck44/vb=6,4 2006.173.17:44:33.63#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.17:44:33.63#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.17:44:33.63#ibcon#ireg 11 cls_cnt 2 2006.173.17:44:33.63#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.17:44:33.69#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.17:44:33.69#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.17:44:33.69#ibcon#enter wrdev, iclass 36, count 2 2006.173.17:44:33.69#ibcon#first serial, iclass 36, count 2 2006.173.17:44:33.69#ibcon#enter sib2, iclass 36, count 2 2006.173.17:44:33.69#ibcon#flushed, iclass 36, count 2 2006.173.17:44:33.69#ibcon#about to write, iclass 36, count 2 2006.173.17:44:33.69#ibcon#wrote, iclass 36, count 2 2006.173.17:44:33.69#ibcon#about to read 3, iclass 36, count 2 2006.173.17:44:33.71#ibcon#read 3, iclass 36, count 2 2006.173.17:44:33.71#ibcon#about to read 4, iclass 36, count 2 2006.173.17:44:33.71#ibcon#read 4, iclass 36, count 2 2006.173.17:44:33.71#ibcon#about to read 5, iclass 36, count 2 2006.173.17:44:33.71#ibcon#read 5, iclass 36, count 2 2006.173.17:44:33.71#ibcon#about to read 6, iclass 36, count 2 2006.173.17:44:33.71#ibcon#read 6, iclass 36, count 2 2006.173.17:44:33.71#ibcon#end of sib2, iclass 36, count 2 2006.173.17:44:33.71#ibcon#*mode == 0, iclass 36, count 2 2006.173.17:44:33.71#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.17:44:33.71#ibcon#[27=AT06-04\r\n] 2006.173.17:44:33.71#ibcon#*before write, iclass 36, count 2 2006.173.17:44:33.71#ibcon#enter sib2, iclass 36, count 2 2006.173.17:44:33.71#ibcon#flushed, iclass 36, count 2 2006.173.17:44:33.71#ibcon#about to write, iclass 36, count 2 2006.173.17:44:33.71#ibcon#wrote, iclass 36, count 2 2006.173.17:44:33.71#ibcon#about to read 3, iclass 36, count 2 2006.173.17:44:33.74#ibcon#read 3, iclass 36, count 2 2006.173.17:44:33.74#ibcon#about to read 4, iclass 36, count 2 2006.173.17:44:33.74#ibcon#read 4, iclass 36, count 2 2006.173.17:44:33.74#ibcon#about to read 5, iclass 36, count 2 2006.173.17:44:33.74#ibcon#read 5, iclass 36, count 2 2006.173.17:44:33.74#ibcon#about to read 6, iclass 36, count 2 2006.173.17:44:33.74#ibcon#read 6, iclass 36, count 2 2006.173.17:44:33.74#ibcon#end of sib2, iclass 36, count 2 2006.173.17:44:33.74#ibcon#*after write, iclass 36, count 2 2006.173.17:44:33.74#ibcon#*before return 0, iclass 36, count 2 2006.173.17:44:33.74#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.17:44:33.74#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.17:44:33.74#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.17:44:33.74#ibcon#ireg 7 cls_cnt 0 2006.173.17:44:33.74#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.17:44:33.86#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.17:44:33.86#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.17:44:33.86#ibcon#enter wrdev, iclass 36, count 0 2006.173.17:44:33.86#ibcon#first serial, iclass 36, count 0 2006.173.17:44:33.86#ibcon#enter sib2, iclass 36, count 0 2006.173.17:44:33.86#ibcon#flushed, iclass 36, count 0 2006.173.17:44:33.86#ibcon#about to write, iclass 36, count 0 2006.173.17:44:33.86#ibcon#wrote, iclass 36, count 0 2006.173.17:44:33.86#ibcon#about to read 3, iclass 36, count 0 2006.173.17:44:33.88#ibcon#read 3, iclass 36, count 0 2006.173.17:44:33.88#ibcon#about to read 4, iclass 36, count 0 2006.173.17:44:33.88#ibcon#read 4, iclass 36, count 0 2006.173.17:44:33.88#ibcon#about to read 5, iclass 36, count 0 2006.173.17:44:33.88#ibcon#read 5, iclass 36, count 0 2006.173.17:44:33.88#ibcon#about to read 6, iclass 36, count 0 2006.173.17:44:33.88#ibcon#read 6, iclass 36, count 0 2006.173.17:44:33.88#ibcon#end of sib2, iclass 36, count 0 2006.173.17:44:33.88#ibcon#*mode == 0, iclass 36, count 0 2006.173.17:44:33.88#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.17:44:33.88#ibcon#[27=USB\r\n] 2006.173.17:44:33.88#ibcon#*before write, iclass 36, count 0 2006.173.17:44:33.88#ibcon#enter sib2, iclass 36, count 0 2006.173.17:44:33.88#ibcon#flushed, iclass 36, count 0 2006.173.17:44:33.88#ibcon#about to write, iclass 36, count 0 2006.173.17:44:33.88#ibcon#wrote, iclass 36, count 0 2006.173.17:44:33.88#ibcon#about to read 3, iclass 36, count 0 2006.173.17:44:33.91#ibcon#read 3, iclass 36, count 0 2006.173.17:44:33.91#ibcon#about to read 4, iclass 36, count 0 2006.173.17:44:33.91#ibcon#read 4, iclass 36, count 0 2006.173.17:44:33.91#ibcon#about to read 5, iclass 36, count 0 2006.173.17:44:33.91#ibcon#read 5, iclass 36, count 0 2006.173.17:44:33.91#ibcon#about to read 6, iclass 36, count 0 2006.173.17:44:33.91#ibcon#read 6, iclass 36, count 0 2006.173.17:44:33.91#ibcon#end of sib2, iclass 36, count 0 2006.173.17:44:33.91#ibcon#*after write, iclass 36, count 0 2006.173.17:44:33.91#ibcon#*before return 0, iclass 36, count 0 2006.173.17:44:33.91#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.17:44:33.91#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.17:44:33.91#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.17:44:33.91#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.17:44:33.91$vck44/vblo=7,734.99 2006.173.17:44:33.91#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.17:44:33.91#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.17:44:33.91#ibcon#ireg 17 cls_cnt 0 2006.173.17:44:33.91#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.17:44:33.91#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.17:44:33.91#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.17:44:33.91#ibcon#enter wrdev, iclass 38, count 0 2006.173.17:44:33.91#ibcon#first serial, iclass 38, count 0 2006.173.17:44:33.91#ibcon#enter sib2, iclass 38, count 0 2006.173.17:44:33.91#ibcon#flushed, iclass 38, count 0 2006.173.17:44:33.91#ibcon#about to write, iclass 38, count 0 2006.173.17:44:33.91#ibcon#wrote, iclass 38, count 0 2006.173.17:44:33.91#ibcon#about to read 3, iclass 38, count 0 2006.173.17:44:33.93#ibcon#read 3, iclass 38, count 0 2006.173.17:44:33.93#ibcon#about to read 4, iclass 38, count 0 2006.173.17:44:33.93#ibcon#read 4, iclass 38, count 0 2006.173.17:44:33.93#ibcon#about to read 5, iclass 38, count 0 2006.173.17:44:33.93#ibcon#read 5, iclass 38, count 0 2006.173.17:44:33.93#ibcon#about to read 6, iclass 38, count 0 2006.173.17:44:33.93#ibcon#read 6, iclass 38, count 0 2006.173.17:44:33.93#ibcon#end of sib2, iclass 38, count 0 2006.173.17:44:33.93#ibcon#*mode == 0, iclass 38, count 0 2006.173.17:44:33.93#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.17:44:33.93#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.17:44:33.93#ibcon#*before write, iclass 38, count 0 2006.173.17:44:33.93#ibcon#enter sib2, iclass 38, count 0 2006.173.17:44:33.93#ibcon#flushed, iclass 38, count 0 2006.173.17:44:33.93#ibcon#about to write, iclass 38, count 0 2006.173.17:44:33.93#ibcon#wrote, iclass 38, count 0 2006.173.17:44:33.93#ibcon#about to read 3, iclass 38, count 0 2006.173.17:44:33.97#ibcon#read 3, iclass 38, count 0 2006.173.17:44:33.97#ibcon#about to read 4, iclass 38, count 0 2006.173.17:44:33.97#ibcon#read 4, iclass 38, count 0 2006.173.17:44:33.97#ibcon#about to read 5, iclass 38, count 0 2006.173.17:44:33.97#ibcon#read 5, iclass 38, count 0 2006.173.17:44:33.97#ibcon#about to read 6, iclass 38, count 0 2006.173.17:44:33.97#ibcon#read 6, iclass 38, count 0 2006.173.17:44:33.97#ibcon#end of sib2, iclass 38, count 0 2006.173.17:44:33.97#ibcon#*after write, iclass 38, count 0 2006.173.17:44:33.97#ibcon#*before return 0, iclass 38, count 0 2006.173.17:44:33.97#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.17:44:33.97#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.17:44:33.97#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.17:44:33.97#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.17:44:33.97$vck44/vb=7,4 2006.173.17:44:33.97#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.17:44:33.97#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.17:44:33.97#ibcon#ireg 11 cls_cnt 2 2006.173.17:44:33.97#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.17:44:34.03#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.17:44:34.03#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.17:44:34.03#ibcon#enter wrdev, iclass 40, count 2 2006.173.17:44:34.03#ibcon#first serial, iclass 40, count 2 2006.173.17:44:34.03#ibcon#enter sib2, iclass 40, count 2 2006.173.17:44:34.03#ibcon#flushed, iclass 40, count 2 2006.173.17:44:34.03#ibcon#about to write, iclass 40, count 2 2006.173.17:44:34.03#ibcon#wrote, iclass 40, count 2 2006.173.17:44:34.03#ibcon#about to read 3, iclass 40, count 2 2006.173.17:44:34.05#ibcon#read 3, iclass 40, count 2 2006.173.17:44:34.05#ibcon#about to read 4, iclass 40, count 2 2006.173.17:44:34.05#ibcon#read 4, iclass 40, count 2 2006.173.17:44:34.05#ibcon#about to read 5, iclass 40, count 2 2006.173.17:44:34.05#ibcon#read 5, iclass 40, count 2 2006.173.17:44:34.05#ibcon#about to read 6, iclass 40, count 2 2006.173.17:44:34.05#ibcon#read 6, iclass 40, count 2 2006.173.17:44:34.05#ibcon#end of sib2, iclass 40, count 2 2006.173.17:44:34.05#ibcon#*mode == 0, iclass 40, count 2 2006.173.17:44:34.05#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.17:44:34.05#ibcon#[27=AT07-04\r\n] 2006.173.17:44:34.05#ibcon#*before write, iclass 40, count 2 2006.173.17:44:34.05#ibcon#enter sib2, iclass 40, count 2 2006.173.17:44:34.05#ibcon#flushed, iclass 40, count 2 2006.173.17:44:34.05#ibcon#about to write, iclass 40, count 2 2006.173.17:44:34.05#ibcon#wrote, iclass 40, count 2 2006.173.17:44:34.05#ibcon#about to read 3, iclass 40, count 2 2006.173.17:44:34.08#ibcon#read 3, iclass 40, count 2 2006.173.17:44:34.08#ibcon#about to read 4, iclass 40, count 2 2006.173.17:44:34.08#ibcon#read 4, iclass 40, count 2 2006.173.17:44:34.08#ibcon#about to read 5, iclass 40, count 2 2006.173.17:44:34.08#ibcon#read 5, iclass 40, count 2 2006.173.17:44:34.08#ibcon#about to read 6, iclass 40, count 2 2006.173.17:44:34.08#ibcon#read 6, iclass 40, count 2 2006.173.17:44:34.08#ibcon#end of sib2, iclass 40, count 2 2006.173.17:44:34.08#ibcon#*after write, iclass 40, count 2 2006.173.17:44:34.08#ibcon#*before return 0, iclass 40, count 2 2006.173.17:44:34.08#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.17:44:34.08#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.17:44:34.08#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.17:44:34.08#ibcon#ireg 7 cls_cnt 0 2006.173.17:44:34.08#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.17:44:34.20#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.17:44:34.20#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.17:44:34.20#ibcon#enter wrdev, iclass 40, count 0 2006.173.17:44:34.20#ibcon#first serial, iclass 40, count 0 2006.173.17:44:34.20#ibcon#enter sib2, iclass 40, count 0 2006.173.17:44:34.20#ibcon#flushed, iclass 40, count 0 2006.173.17:44:34.20#ibcon#about to write, iclass 40, count 0 2006.173.17:44:34.20#ibcon#wrote, iclass 40, count 0 2006.173.17:44:34.20#ibcon#about to read 3, iclass 40, count 0 2006.173.17:44:34.22#ibcon#read 3, iclass 40, count 0 2006.173.17:44:34.22#ibcon#about to read 4, iclass 40, count 0 2006.173.17:44:34.22#ibcon#read 4, iclass 40, count 0 2006.173.17:44:34.22#ibcon#about to read 5, iclass 40, count 0 2006.173.17:44:34.22#ibcon#read 5, iclass 40, count 0 2006.173.17:44:34.22#ibcon#about to read 6, iclass 40, count 0 2006.173.17:44:34.22#ibcon#read 6, iclass 40, count 0 2006.173.17:44:34.22#ibcon#end of sib2, iclass 40, count 0 2006.173.17:44:34.22#ibcon#*mode == 0, iclass 40, count 0 2006.173.17:44:34.22#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.17:44:34.22#ibcon#[27=USB\r\n] 2006.173.17:44:34.22#ibcon#*before write, iclass 40, count 0 2006.173.17:44:34.22#ibcon#enter sib2, iclass 40, count 0 2006.173.17:44:34.22#ibcon#flushed, iclass 40, count 0 2006.173.17:44:34.22#ibcon#about to write, iclass 40, count 0 2006.173.17:44:34.22#ibcon#wrote, iclass 40, count 0 2006.173.17:44:34.22#ibcon#about to read 3, iclass 40, count 0 2006.173.17:44:34.25#ibcon#read 3, iclass 40, count 0 2006.173.17:44:34.25#ibcon#about to read 4, iclass 40, count 0 2006.173.17:44:34.25#ibcon#read 4, iclass 40, count 0 2006.173.17:44:34.25#ibcon#about to read 5, iclass 40, count 0 2006.173.17:44:34.25#ibcon#read 5, iclass 40, count 0 2006.173.17:44:34.25#ibcon#about to read 6, iclass 40, count 0 2006.173.17:44:34.25#ibcon#read 6, iclass 40, count 0 2006.173.17:44:34.25#ibcon#end of sib2, iclass 40, count 0 2006.173.17:44:34.25#ibcon#*after write, iclass 40, count 0 2006.173.17:44:34.25#ibcon#*before return 0, iclass 40, count 0 2006.173.17:44:34.25#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.17:44:34.25#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.17:44:34.25#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.17:44:34.25#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.17:44:34.25$vck44/vblo=8,744.99 2006.173.17:44:34.25#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.17:44:34.25#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.17:44:34.25#ibcon#ireg 17 cls_cnt 0 2006.173.17:44:34.25#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.17:44:34.25#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.17:44:34.25#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.17:44:34.25#ibcon#enter wrdev, iclass 4, count 0 2006.173.17:44:34.25#ibcon#first serial, iclass 4, count 0 2006.173.17:44:34.25#ibcon#enter sib2, iclass 4, count 0 2006.173.17:44:34.25#ibcon#flushed, iclass 4, count 0 2006.173.17:44:34.25#ibcon#about to write, iclass 4, count 0 2006.173.17:44:34.25#ibcon#wrote, iclass 4, count 0 2006.173.17:44:34.25#ibcon#about to read 3, iclass 4, count 0 2006.173.17:44:34.27#ibcon#read 3, iclass 4, count 0 2006.173.17:44:34.27#ibcon#about to read 4, iclass 4, count 0 2006.173.17:44:34.27#ibcon#read 4, iclass 4, count 0 2006.173.17:44:34.27#ibcon#about to read 5, iclass 4, count 0 2006.173.17:44:34.27#ibcon#read 5, iclass 4, count 0 2006.173.17:44:34.27#ibcon#about to read 6, iclass 4, count 0 2006.173.17:44:34.27#ibcon#read 6, iclass 4, count 0 2006.173.17:44:34.27#ibcon#end of sib2, iclass 4, count 0 2006.173.17:44:34.27#ibcon#*mode == 0, iclass 4, count 0 2006.173.17:44:34.27#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.17:44:34.27#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.17:44:34.27#ibcon#*before write, iclass 4, count 0 2006.173.17:44:34.27#ibcon#enter sib2, iclass 4, count 0 2006.173.17:44:34.27#ibcon#flushed, iclass 4, count 0 2006.173.17:44:34.27#ibcon#about to write, iclass 4, count 0 2006.173.17:44:34.27#ibcon#wrote, iclass 4, count 0 2006.173.17:44:34.27#ibcon#about to read 3, iclass 4, count 0 2006.173.17:44:34.31#ibcon#read 3, iclass 4, count 0 2006.173.17:44:34.31#ibcon#about to read 4, iclass 4, count 0 2006.173.17:44:34.31#ibcon#read 4, iclass 4, count 0 2006.173.17:44:34.31#ibcon#about to read 5, iclass 4, count 0 2006.173.17:44:34.31#ibcon#read 5, iclass 4, count 0 2006.173.17:44:34.31#ibcon#about to read 6, iclass 4, count 0 2006.173.17:44:34.31#ibcon#read 6, iclass 4, count 0 2006.173.17:44:34.31#ibcon#end of sib2, iclass 4, count 0 2006.173.17:44:34.31#ibcon#*after write, iclass 4, count 0 2006.173.17:44:34.31#ibcon#*before return 0, iclass 4, count 0 2006.173.17:44:34.31#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.17:44:34.31#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.17:44:34.31#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.17:44:34.31#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.17:44:34.31$vck44/vb=8,4 2006.173.17:44:34.31#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.17:44:34.31#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.17:44:34.31#ibcon#ireg 11 cls_cnt 2 2006.173.17:44:34.31#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.17:44:34.37#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.17:44:34.37#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.17:44:34.37#ibcon#enter wrdev, iclass 6, count 2 2006.173.17:44:34.37#ibcon#first serial, iclass 6, count 2 2006.173.17:44:34.37#ibcon#enter sib2, iclass 6, count 2 2006.173.17:44:34.37#ibcon#flushed, iclass 6, count 2 2006.173.17:44:34.37#ibcon#about to write, iclass 6, count 2 2006.173.17:44:34.37#ibcon#wrote, iclass 6, count 2 2006.173.17:44:34.37#ibcon#about to read 3, iclass 6, count 2 2006.173.17:44:34.39#ibcon#read 3, iclass 6, count 2 2006.173.17:44:34.39#ibcon#about to read 4, iclass 6, count 2 2006.173.17:44:34.39#ibcon#read 4, iclass 6, count 2 2006.173.17:44:34.39#ibcon#about to read 5, iclass 6, count 2 2006.173.17:44:34.39#ibcon#read 5, iclass 6, count 2 2006.173.17:44:34.39#ibcon#about to read 6, iclass 6, count 2 2006.173.17:44:34.39#ibcon#read 6, iclass 6, count 2 2006.173.17:44:34.39#ibcon#end of sib2, iclass 6, count 2 2006.173.17:44:34.39#ibcon#*mode == 0, iclass 6, count 2 2006.173.17:44:34.39#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.17:44:34.39#ibcon#[27=AT08-04\r\n] 2006.173.17:44:34.39#ibcon#*before write, iclass 6, count 2 2006.173.17:44:34.39#ibcon#enter sib2, iclass 6, count 2 2006.173.17:44:34.39#ibcon#flushed, iclass 6, count 2 2006.173.17:44:34.39#ibcon#about to write, iclass 6, count 2 2006.173.17:44:34.39#ibcon#wrote, iclass 6, count 2 2006.173.17:44:34.39#ibcon#about to read 3, iclass 6, count 2 2006.173.17:44:34.42#ibcon#read 3, iclass 6, count 2 2006.173.17:44:34.42#ibcon#about to read 4, iclass 6, count 2 2006.173.17:44:34.42#ibcon#read 4, iclass 6, count 2 2006.173.17:44:34.42#ibcon#about to read 5, iclass 6, count 2 2006.173.17:44:34.42#ibcon#read 5, iclass 6, count 2 2006.173.17:44:34.42#ibcon#about to read 6, iclass 6, count 2 2006.173.17:44:34.42#ibcon#read 6, iclass 6, count 2 2006.173.17:44:34.42#ibcon#end of sib2, iclass 6, count 2 2006.173.17:44:34.42#ibcon#*after write, iclass 6, count 2 2006.173.17:44:34.42#ibcon#*before return 0, iclass 6, count 2 2006.173.17:44:34.42#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.17:44:34.42#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.17:44:34.42#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.17:44:34.42#ibcon#ireg 7 cls_cnt 0 2006.173.17:44:34.42#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.17:44:34.54#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.17:44:34.54#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.17:44:34.54#ibcon#enter wrdev, iclass 6, count 0 2006.173.17:44:34.54#ibcon#first serial, iclass 6, count 0 2006.173.17:44:34.54#ibcon#enter sib2, iclass 6, count 0 2006.173.17:44:34.54#ibcon#flushed, iclass 6, count 0 2006.173.17:44:34.54#ibcon#about to write, iclass 6, count 0 2006.173.17:44:34.54#ibcon#wrote, iclass 6, count 0 2006.173.17:44:34.54#ibcon#about to read 3, iclass 6, count 0 2006.173.17:44:34.56#ibcon#read 3, iclass 6, count 0 2006.173.17:44:34.56#ibcon#about to read 4, iclass 6, count 0 2006.173.17:44:34.56#ibcon#read 4, iclass 6, count 0 2006.173.17:44:34.56#ibcon#about to read 5, iclass 6, count 0 2006.173.17:44:34.56#ibcon#read 5, iclass 6, count 0 2006.173.17:44:34.56#ibcon#about to read 6, iclass 6, count 0 2006.173.17:44:34.56#ibcon#read 6, iclass 6, count 0 2006.173.17:44:34.56#ibcon#end of sib2, iclass 6, count 0 2006.173.17:44:34.56#ibcon#*mode == 0, iclass 6, count 0 2006.173.17:44:34.56#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.17:44:34.56#ibcon#[27=USB\r\n] 2006.173.17:44:34.56#ibcon#*before write, iclass 6, count 0 2006.173.17:44:34.56#ibcon#enter sib2, iclass 6, count 0 2006.173.17:44:34.56#ibcon#flushed, iclass 6, count 0 2006.173.17:44:34.56#ibcon#about to write, iclass 6, count 0 2006.173.17:44:34.56#ibcon#wrote, iclass 6, count 0 2006.173.17:44:34.56#ibcon#about to read 3, iclass 6, count 0 2006.173.17:44:34.59#ibcon#read 3, iclass 6, count 0 2006.173.17:44:34.59#ibcon#about to read 4, iclass 6, count 0 2006.173.17:44:34.59#ibcon#read 4, iclass 6, count 0 2006.173.17:44:34.59#ibcon#about to read 5, iclass 6, count 0 2006.173.17:44:34.59#ibcon#read 5, iclass 6, count 0 2006.173.17:44:34.59#ibcon#about to read 6, iclass 6, count 0 2006.173.17:44:34.59#ibcon#read 6, iclass 6, count 0 2006.173.17:44:34.59#ibcon#end of sib2, iclass 6, count 0 2006.173.17:44:34.59#ibcon#*after write, iclass 6, count 0 2006.173.17:44:34.59#ibcon#*before return 0, iclass 6, count 0 2006.173.17:44:34.59#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.17:44:34.59#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.17:44:34.59#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.17:44:34.59#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.17:44:34.59$vck44/vabw=wide 2006.173.17:44:34.59#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.17:44:34.59#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.17:44:34.59#ibcon#ireg 8 cls_cnt 0 2006.173.17:44:34.59#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.17:44:34.59#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.17:44:34.59#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.17:44:34.59#ibcon#enter wrdev, iclass 10, count 0 2006.173.17:44:34.59#ibcon#first serial, iclass 10, count 0 2006.173.17:44:34.59#ibcon#enter sib2, iclass 10, count 0 2006.173.17:44:34.59#ibcon#flushed, iclass 10, count 0 2006.173.17:44:34.59#ibcon#about to write, iclass 10, count 0 2006.173.17:44:34.59#ibcon#wrote, iclass 10, count 0 2006.173.17:44:34.59#ibcon#about to read 3, iclass 10, count 0 2006.173.17:44:34.61#ibcon#read 3, iclass 10, count 0 2006.173.17:44:34.61#ibcon#about to read 4, iclass 10, count 0 2006.173.17:44:34.61#ibcon#read 4, iclass 10, count 0 2006.173.17:44:34.61#ibcon#about to read 5, iclass 10, count 0 2006.173.17:44:34.61#ibcon#read 5, iclass 10, count 0 2006.173.17:44:34.61#ibcon#about to read 6, iclass 10, count 0 2006.173.17:44:34.61#ibcon#read 6, iclass 10, count 0 2006.173.17:44:34.61#ibcon#end of sib2, iclass 10, count 0 2006.173.17:44:34.61#ibcon#*mode == 0, iclass 10, count 0 2006.173.17:44:34.61#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.17:44:34.61#ibcon#[25=BW32\r\n] 2006.173.17:44:34.61#ibcon#*before write, iclass 10, count 0 2006.173.17:44:34.61#ibcon#enter sib2, iclass 10, count 0 2006.173.17:44:34.61#ibcon#flushed, iclass 10, count 0 2006.173.17:44:34.61#ibcon#about to write, iclass 10, count 0 2006.173.17:44:34.61#ibcon#wrote, iclass 10, count 0 2006.173.17:44:34.61#ibcon#about to read 3, iclass 10, count 0 2006.173.17:44:34.64#ibcon#read 3, iclass 10, count 0 2006.173.17:44:34.64#ibcon#about to read 4, iclass 10, count 0 2006.173.17:44:34.64#ibcon#read 4, iclass 10, count 0 2006.173.17:44:34.64#ibcon#about to read 5, iclass 10, count 0 2006.173.17:44:34.64#ibcon#read 5, iclass 10, count 0 2006.173.17:44:34.64#ibcon#about to read 6, iclass 10, count 0 2006.173.17:44:34.64#ibcon#read 6, iclass 10, count 0 2006.173.17:44:34.64#ibcon#end of sib2, iclass 10, count 0 2006.173.17:44:34.64#ibcon#*after write, iclass 10, count 0 2006.173.17:44:34.64#ibcon#*before return 0, iclass 10, count 0 2006.173.17:44:34.64#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.17:44:34.64#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.17:44:34.64#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.17:44:34.64#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.17:44:34.64$vck44/vbbw=wide 2006.173.17:44:34.64#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.17:44:34.64#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.17:44:34.64#ibcon#ireg 8 cls_cnt 0 2006.173.17:44:34.64#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.17:44:34.71#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.17:44:34.71#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.17:44:34.71#ibcon#enter wrdev, iclass 12, count 0 2006.173.17:44:34.71#ibcon#first serial, iclass 12, count 0 2006.173.17:44:34.71#ibcon#enter sib2, iclass 12, count 0 2006.173.17:44:34.71#ibcon#flushed, iclass 12, count 0 2006.173.17:44:34.71#ibcon#about to write, iclass 12, count 0 2006.173.17:44:34.71#ibcon#wrote, iclass 12, count 0 2006.173.17:44:34.71#ibcon#about to read 3, iclass 12, count 0 2006.173.17:44:34.73#ibcon#read 3, iclass 12, count 0 2006.173.17:44:34.73#ibcon#about to read 4, iclass 12, count 0 2006.173.17:44:34.73#ibcon#read 4, iclass 12, count 0 2006.173.17:44:34.73#ibcon#about to read 5, iclass 12, count 0 2006.173.17:44:34.73#ibcon#read 5, iclass 12, count 0 2006.173.17:44:34.73#ibcon#about to read 6, iclass 12, count 0 2006.173.17:44:34.73#ibcon#read 6, iclass 12, count 0 2006.173.17:44:34.73#ibcon#end of sib2, iclass 12, count 0 2006.173.17:44:34.73#ibcon#*mode == 0, iclass 12, count 0 2006.173.17:44:34.73#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.17:44:34.73#ibcon#[27=BW32\r\n] 2006.173.17:44:34.73#ibcon#*before write, iclass 12, count 0 2006.173.17:44:34.73#ibcon#enter sib2, iclass 12, count 0 2006.173.17:44:34.73#ibcon#flushed, iclass 12, count 0 2006.173.17:44:34.73#ibcon#about to write, iclass 12, count 0 2006.173.17:44:34.73#ibcon#wrote, iclass 12, count 0 2006.173.17:44:34.73#ibcon#about to read 3, iclass 12, count 0 2006.173.17:44:34.76#ibcon#read 3, iclass 12, count 0 2006.173.17:44:34.76#ibcon#about to read 4, iclass 12, count 0 2006.173.17:44:34.76#ibcon#read 4, iclass 12, count 0 2006.173.17:44:34.76#ibcon#about to read 5, iclass 12, count 0 2006.173.17:44:34.76#ibcon#read 5, iclass 12, count 0 2006.173.17:44:34.76#ibcon#about to read 6, iclass 12, count 0 2006.173.17:44:34.76#ibcon#read 6, iclass 12, count 0 2006.173.17:44:34.76#ibcon#end of sib2, iclass 12, count 0 2006.173.17:44:34.76#ibcon#*after write, iclass 12, count 0 2006.173.17:44:34.76#ibcon#*before return 0, iclass 12, count 0 2006.173.17:44:34.76#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.17:44:34.76#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.17:44:34.76#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.17:44:34.76#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.17:44:34.76$setupk4/ifdk4 2006.173.17:44:34.76$ifdk4/lo= 2006.173.17:44:34.76$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.17:44:34.76$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.17:44:34.76$ifdk4/patch= 2006.173.17:44:34.76$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.17:44:34.76$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.17:44:34.76$setupk4/!*+20s 2006.173.17:44:34.94#abcon#<5=/14 1.2 3.2 20.181001002.2\r\n> 2006.173.17:44:34.96#abcon#{5=INTERFACE CLEAR} 2006.173.17:44:35.02#abcon#[5=S1D000X0/0*\r\n] 2006.173.17:44:45.11#abcon#<5=/14 1.2 3.2 20.181001002.2\r\n> 2006.173.17:44:45.13#abcon#{5=INTERFACE CLEAR} 2006.173.17:44:45.19#abcon#[5=S1D000X0/0*\r\n] 2006.173.17:44:49.27$setupk4/"tpicd 2006.173.17:44:49.27$setupk4/echo=off 2006.173.17:44:49.27$setupk4/xlog=off 2006.173.17:44:49.27:!2006.173.17:49:49 2006.173.17:45:03.14#trakl#Source acquired 2006.173.17:45:04.14#flagr#flagr/antenna,acquired 2006.173.17:49:49.00:preob 2006.173.17:49:50.13/onsource/TRACKING 2006.173.17:49:50.13:!2006.173.17:49:59 2006.173.17:49:59.00:"tape 2006.173.17:49:59.00:"st=record 2006.173.17:49:59.00:data_valid=on 2006.173.17:49:59.00:midob 2006.173.17:49:59.13/onsource/TRACKING 2006.173.17:49:59.13/wx/20.12,1002.2,100 2006.173.17:49:59.34/cable/+6.5154E-03 2006.173.17:50:00.43/va/01,07,usb,yes,38,41 2006.173.17:50:00.43/va/02,06,usb,yes,38,39 2006.173.17:50:00.43/va/03,05,usb,yes,48,50 2006.173.17:50:00.43/va/04,06,usb,yes,38,40 2006.173.17:50:00.43/va/05,04,usb,yes,30,31 2006.173.17:50:00.43/va/06,03,usb,yes,42,42 2006.173.17:50:00.43/va/07,04,usb,yes,34,35 2006.173.17:50:00.43/va/08,04,usb,yes,29,35 2006.173.17:50:00.66/valo/01,524.99,yes,locked 2006.173.17:50:00.66/valo/02,534.99,yes,locked 2006.173.17:50:00.66/valo/03,564.99,yes,locked 2006.173.17:50:00.66/valo/04,624.99,yes,locked 2006.173.17:50:00.66/valo/05,734.99,yes,locked 2006.173.17:50:00.66/valo/06,814.99,yes,locked 2006.173.17:50:00.66/valo/07,864.99,yes,locked 2006.173.17:50:00.66/valo/08,884.99,yes,locked 2006.173.17:50:01.75/vb/01,04,usb,yes,31,28 2006.173.17:50:01.75/vb/02,04,usb,yes,33,33 2006.173.17:50:01.75/vb/03,04,usb,yes,30,33 2006.173.17:50:01.75/vb/04,04,usb,yes,34,33 2006.173.17:50:01.75/vb/05,04,usb,yes,27,29 2006.173.17:50:01.75/vb/06,04,usb,yes,31,28 2006.173.17:50:01.75/vb/07,04,usb,yes,31,31 2006.173.17:50:01.75/vb/08,04,usb,yes,29,32 2006.173.17:50:01.98/vblo/01,629.99,yes,locked 2006.173.17:50:01.98/vblo/02,634.99,yes,locked 2006.173.17:50:01.98/vblo/03,649.99,yes,locked 2006.173.17:50:01.98/vblo/04,679.99,yes,locked 2006.173.17:50:01.98/vblo/05,709.99,yes,locked 2006.173.17:50:01.98/vblo/06,719.99,yes,locked 2006.173.17:50:01.98/vblo/07,734.99,yes,locked 2006.173.17:50:01.98/vblo/08,744.99,yes,locked 2006.173.17:50:02.13/vabw/8 2006.173.17:50:02.28/vbbw/8 2006.173.17:50:02.37/xfe/off,on,15.0 2006.173.17:50:02.75/ifatt/23,28,28,28 2006.173.17:50:03.07/fmout-gps/S +4.03E-07 2006.173.17:50:03.11:!2006.173.17:50:39 2006.173.17:50:39.01:data_valid=off 2006.173.17:50:39.01:"et 2006.173.17:50:39.01:!+3s 2006.173.17:50:42.02:"tape 2006.173.17:50:42.02:postob 2006.173.17:50:42.09/cable/+6.5136E-03 2006.173.17:50:42.09/wx/20.12,1002.2,100 2006.173.17:50:43.07/fmout-gps/S +4.03E-07 2006.173.17:50:43.07:scan_name=173-1751,jd0606,760 2006.173.17:50:43.07:source=1749+096,175132.82,093900.7,2000.0,ccw 2006.173.17:50:44.14#flagr#flagr/antenna,new-source 2006.173.17:50:44.14:checkk5 2006.173.17:50:44.51/chk_autoobs//k5ts1/ autoobs is running! 2006.173.17:50:44.91/chk_autoobs//k5ts2/ autoobs is running! 2006.173.17:50:45.34/chk_autoobs//k5ts3/ autoobs is running! 2006.173.17:50:45.72/chk_autoobs//k5ts4/ autoobs is running! 2006.173.17:50:46.11/chk_obsdata//k5ts1/T1731749??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.17:50:46.51/chk_obsdata//k5ts2/T1731749??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.17:50:46.91/chk_obsdata//k5ts3/T1731749??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.17:50:47.31/chk_obsdata//k5ts4/T1731749??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.17:50:48.03/k5log//k5ts1_log_newline 2006.173.17:50:48.72/k5log//k5ts2_log_newline 2006.173.17:50:49.42/k5log//k5ts3_log_newline 2006.173.17:50:50.15/k5log//k5ts4_log_newline 2006.173.17:50:50.17/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.17:50:50.17:setupk4=1 2006.173.17:50:50.17$setupk4/echo=on 2006.173.17:50:50.17$setupk4/pcalon 2006.173.17:50:50.17$pcalon/"no phase cal control is implemented here 2006.173.17:50:50.17$setupk4/"tpicd=stop 2006.173.17:50:50.17$setupk4/"rec=synch_on 2006.173.17:50:50.17$setupk4/"rec_mode=128 2006.173.17:50:50.17$setupk4/!* 2006.173.17:50:50.17$setupk4/recpk4 2006.173.17:50:50.17$recpk4/recpatch= 2006.173.17:50:50.18$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.17:50:50.18$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.17:50:50.18$setupk4/vck44 2006.173.17:50:50.18$vck44/valo=1,524.99 2006.173.17:50:50.18#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.17:50:50.18#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.17:50:50.18#ibcon#ireg 17 cls_cnt 0 2006.173.17:50:50.18#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.17:50:50.18#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.17:50:50.18#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.17:50:50.18#ibcon#enter wrdev, iclass 21, count 0 2006.173.17:50:50.18#ibcon#first serial, iclass 21, count 0 2006.173.17:50:50.18#ibcon#enter sib2, iclass 21, count 0 2006.173.17:50:50.18#ibcon#flushed, iclass 21, count 0 2006.173.17:50:50.18#ibcon#about to write, iclass 21, count 0 2006.173.17:50:50.18#ibcon#wrote, iclass 21, count 0 2006.173.17:50:50.18#ibcon#about to read 3, iclass 21, count 0 2006.173.17:50:50.20#ibcon#read 3, iclass 21, count 0 2006.173.17:50:50.20#ibcon#about to read 4, iclass 21, count 0 2006.173.17:50:50.20#ibcon#read 4, iclass 21, count 0 2006.173.17:50:50.20#ibcon#about to read 5, iclass 21, count 0 2006.173.17:50:50.20#ibcon#read 5, iclass 21, count 0 2006.173.17:50:50.20#ibcon#about to read 6, iclass 21, count 0 2006.173.17:50:50.20#ibcon#read 6, iclass 21, count 0 2006.173.17:50:50.20#ibcon#end of sib2, iclass 21, count 0 2006.173.17:50:50.20#ibcon#*mode == 0, iclass 21, count 0 2006.173.17:50:50.20#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.17:50:50.20#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.17:50:50.20#ibcon#*before write, iclass 21, count 0 2006.173.17:50:50.20#ibcon#enter sib2, iclass 21, count 0 2006.173.17:50:50.20#ibcon#flushed, iclass 21, count 0 2006.173.17:50:50.20#ibcon#about to write, iclass 21, count 0 2006.173.17:50:50.20#ibcon#wrote, iclass 21, count 0 2006.173.17:50:50.20#ibcon#about to read 3, iclass 21, count 0 2006.173.17:50:50.25#ibcon#read 3, iclass 21, count 0 2006.173.17:50:50.25#ibcon#about to read 4, iclass 21, count 0 2006.173.17:50:50.25#ibcon#read 4, iclass 21, count 0 2006.173.17:50:50.25#ibcon#about to read 5, iclass 21, count 0 2006.173.17:50:50.25#ibcon#read 5, iclass 21, count 0 2006.173.17:50:50.25#ibcon#about to read 6, iclass 21, count 0 2006.173.17:50:50.25#ibcon#read 6, iclass 21, count 0 2006.173.17:50:50.25#ibcon#end of sib2, iclass 21, count 0 2006.173.17:50:50.25#ibcon#*after write, iclass 21, count 0 2006.173.17:50:50.25#ibcon#*before return 0, iclass 21, count 0 2006.173.17:50:50.25#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.17:50:50.25#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.17:50:50.25#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.17:50:50.25#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.17:50:50.25$vck44/va=1,7 2006.173.17:50:50.25#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.17:50:50.25#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.17:50:50.25#ibcon#ireg 11 cls_cnt 2 2006.173.17:50:50.25#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.17:50:50.25#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.17:50:50.25#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.17:50:50.25#ibcon#enter wrdev, iclass 23, count 2 2006.173.17:50:50.25#ibcon#first serial, iclass 23, count 2 2006.173.17:50:50.25#ibcon#enter sib2, iclass 23, count 2 2006.173.17:50:50.25#ibcon#flushed, iclass 23, count 2 2006.173.17:50:50.25#ibcon#about to write, iclass 23, count 2 2006.173.17:50:50.25#ibcon#wrote, iclass 23, count 2 2006.173.17:50:50.25#ibcon#about to read 3, iclass 23, count 2 2006.173.17:50:50.27#ibcon#read 3, iclass 23, count 2 2006.173.17:50:50.27#ibcon#about to read 4, iclass 23, count 2 2006.173.17:50:50.27#ibcon#read 4, iclass 23, count 2 2006.173.17:50:50.27#ibcon#about to read 5, iclass 23, count 2 2006.173.17:50:50.27#ibcon#read 5, iclass 23, count 2 2006.173.17:50:50.27#ibcon#about to read 6, iclass 23, count 2 2006.173.17:50:50.27#ibcon#read 6, iclass 23, count 2 2006.173.17:50:50.27#ibcon#end of sib2, iclass 23, count 2 2006.173.17:50:50.27#ibcon#*mode == 0, iclass 23, count 2 2006.173.17:50:50.27#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.17:50:50.27#ibcon#[25=AT01-07\r\n] 2006.173.17:50:50.27#ibcon#*before write, iclass 23, count 2 2006.173.17:50:50.27#ibcon#enter sib2, iclass 23, count 2 2006.173.17:50:50.27#ibcon#flushed, iclass 23, count 2 2006.173.17:50:50.27#ibcon#about to write, iclass 23, count 2 2006.173.17:50:50.27#ibcon#wrote, iclass 23, count 2 2006.173.17:50:50.27#ibcon#about to read 3, iclass 23, count 2 2006.173.17:50:50.30#ibcon#read 3, iclass 23, count 2 2006.173.17:50:50.30#ibcon#about to read 4, iclass 23, count 2 2006.173.17:50:50.30#ibcon#read 4, iclass 23, count 2 2006.173.17:50:50.30#ibcon#about to read 5, iclass 23, count 2 2006.173.17:50:50.30#ibcon#read 5, iclass 23, count 2 2006.173.17:50:50.30#ibcon#about to read 6, iclass 23, count 2 2006.173.17:50:50.30#ibcon#read 6, iclass 23, count 2 2006.173.17:50:50.30#ibcon#end of sib2, iclass 23, count 2 2006.173.17:50:50.30#ibcon#*after write, iclass 23, count 2 2006.173.17:50:50.30#ibcon#*before return 0, iclass 23, count 2 2006.173.17:50:50.30#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.17:50:50.30#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.17:50:50.30#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.17:50:50.30#ibcon#ireg 7 cls_cnt 0 2006.173.17:50:50.30#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.17:50:50.42#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.17:50:50.42#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.17:50:50.42#ibcon#enter wrdev, iclass 23, count 0 2006.173.17:50:50.42#ibcon#first serial, iclass 23, count 0 2006.173.17:50:50.42#ibcon#enter sib2, iclass 23, count 0 2006.173.17:50:50.42#ibcon#flushed, iclass 23, count 0 2006.173.17:50:50.42#ibcon#about to write, iclass 23, count 0 2006.173.17:50:50.42#ibcon#wrote, iclass 23, count 0 2006.173.17:50:50.42#ibcon#about to read 3, iclass 23, count 0 2006.173.17:50:50.44#ibcon#read 3, iclass 23, count 0 2006.173.17:50:50.44#ibcon#about to read 4, iclass 23, count 0 2006.173.17:50:50.44#ibcon#read 4, iclass 23, count 0 2006.173.17:50:50.44#ibcon#about to read 5, iclass 23, count 0 2006.173.17:50:50.44#ibcon#read 5, iclass 23, count 0 2006.173.17:50:50.44#ibcon#about to read 6, iclass 23, count 0 2006.173.17:50:50.44#ibcon#read 6, iclass 23, count 0 2006.173.17:50:50.44#ibcon#end of sib2, iclass 23, count 0 2006.173.17:50:50.44#ibcon#*mode == 0, iclass 23, count 0 2006.173.17:50:50.44#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.17:50:50.44#ibcon#[25=USB\r\n] 2006.173.17:50:50.44#ibcon#*before write, iclass 23, count 0 2006.173.17:50:50.44#ibcon#enter sib2, iclass 23, count 0 2006.173.17:50:50.44#ibcon#flushed, iclass 23, count 0 2006.173.17:50:50.44#ibcon#about to write, iclass 23, count 0 2006.173.17:50:50.44#ibcon#wrote, iclass 23, count 0 2006.173.17:50:50.44#ibcon#about to read 3, iclass 23, count 0 2006.173.17:50:50.47#ibcon#read 3, iclass 23, count 0 2006.173.17:50:50.47#ibcon#about to read 4, iclass 23, count 0 2006.173.17:50:50.47#ibcon#read 4, iclass 23, count 0 2006.173.17:50:50.47#ibcon#about to read 5, iclass 23, count 0 2006.173.17:50:50.47#ibcon#read 5, iclass 23, count 0 2006.173.17:50:50.47#ibcon#about to read 6, iclass 23, count 0 2006.173.17:50:50.47#ibcon#read 6, iclass 23, count 0 2006.173.17:50:50.47#ibcon#end of sib2, iclass 23, count 0 2006.173.17:50:50.47#ibcon#*after write, iclass 23, count 0 2006.173.17:50:50.47#ibcon#*before return 0, iclass 23, count 0 2006.173.17:50:50.47#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.17:50:50.47#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.17:50:50.47#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.17:50:50.47#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.17:50:50.47$vck44/valo=2,534.99 2006.173.17:50:50.47#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.17:50:50.47#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.17:50:50.47#ibcon#ireg 17 cls_cnt 0 2006.173.17:50:50.47#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.17:50:50.47#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.17:50:50.47#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.17:50:50.47#ibcon#enter wrdev, iclass 25, count 0 2006.173.17:50:50.47#ibcon#first serial, iclass 25, count 0 2006.173.17:50:50.47#ibcon#enter sib2, iclass 25, count 0 2006.173.17:50:50.47#ibcon#flushed, iclass 25, count 0 2006.173.17:50:50.47#ibcon#about to write, iclass 25, count 0 2006.173.17:50:50.47#ibcon#wrote, iclass 25, count 0 2006.173.17:50:50.47#ibcon#about to read 3, iclass 25, count 0 2006.173.17:50:50.49#ibcon#read 3, iclass 25, count 0 2006.173.17:50:50.49#ibcon#about to read 4, iclass 25, count 0 2006.173.17:50:50.49#ibcon#read 4, iclass 25, count 0 2006.173.17:50:50.49#ibcon#about to read 5, iclass 25, count 0 2006.173.17:50:50.49#ibcon#read 5, iclass 25, count 0 2006.173.17:50:50.49#ibcon#about to read 6, iclass 25, count 0 2006.173.17:50:50.49#ibcon#read 6, iclass 25, count 0 2006.173.17:50:50.49#ibcon#end of sib2, iclass 25, count 0 2006.173.17:50:50.49#ibcon#*mode == 0, iclass 25, count 0 2006.173.17:50:50.49#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.17:50:50.49#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.17:50:50.49#ibcon#*before write, iclass 25, count 0 2006.173.17:50:50.49#ibcon#enter sib2, iclass 25, count 0 2006.173.17:50:50.49#ibcon#flushed, iclass 25, count 0 2006.173.17:50:50.49#ibcon#about to write, iclass 25, count 0 2006.173.17:50:50.49#ibcon#wrote, iclass 25, count 0 2006.173.17:50:50.49#ibcon#about to read 3, iclass 25, count 0 2006.173.17:50:50.53#ibcon#read 3, iclass 25, count 0 2006.173.17:50:50.53#ibcon#about to read 4, iclass 25, count 0 2006.173.17:50:50.53#ibcon#read 4, iclass 25, count 0 2006.173.17:50:50.53#ibcon#about to read 5, iclass 25, count 0 2006.173.17:50:50.53#ibcon#read 5, iclass 25, count 0 2006.173.17:50:50.53#ibcon#about to read 6, iclass 25, count 0 2006.173.17:50:50.53#ibcon#read 6, iclass 25, count 0 2006.173.17:50:50.53#ibcon#end of sib2, iclass 25, count 0 2006.173.17:50:50.53#ibcon#*after write, iclass 25, count 0 2006.173.17:50:50.53#ibcon#*before return 0, iclass 25, count 0 2006.173.17:50:50.53#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.17:50:50.53#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.17:50:50.53#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.17:50:50.53#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.17:50:50.53$vck44/va=2,6 2006.173.17:50:50.53#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.17:50:50.53#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.17:50:50.53#ibcon#ireg 11 cls_cnt 2 2006.173.17:50:50.53#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.17:50:50.59#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.17:50:50.59#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.17:50:50.59#ibcon#enter wrdev, iclass 27, count 2 2006.173.17:50:50.59#ibcon#first serial, iclass 27, count 2 2006.173.17:50:50.59#ibcon#enter sib2, iclass 27, count 2 2006.173.17:50:50.59#ibcon#flushed, iclass 27, count 2 2006.173.17:50:50.59#ibcon#about to write, iclass 27, count 2 2006.173.17:50:50.59#ibcon#wrote, iclass 27, count 2 2006.173.17:50:50.59#ibcon#about to read 3, iclass 27, count 2 2006.173.17:50:50.61#ibcon#read 3, iclass 27, count 2 2006.173.17:50:50.61#ibcon#about to read 4, iclass 27, count 2 2006.173.17:50:50.61#ibcon#read 4, iclass 27, count 2 2006.173.17:50:50.61#ibcon#about to read 5, iclass 27, count 2 2006.173.17:50:50.61#ibcon#read 5, iclass 27, count 2 2006.173.17:50:50.61#ibcon#about to read 6, iclass 27, count 2 2006.173.17:50:50.61#ibcon#read 6, iclass 27, count 2 2006.173.17:50:50.61#ibcon#end of sib2, iclass 27, count 2 2006.173.17:50:50.61#ibcon#*mode == 0, iclass 27, count 2 2006.173.17:50:50.61#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.17:50:50.61#ibcon#[25=AT02-06\r\n] 2006.173.17:50:50.61#ibcon#*before write, iclass 27, count 2 2006.173.17:50:50.61#ibcon#enter sib2, iclass 27, count 2 2006.173.17:50:50.61#ibcon#flushed, iclass 27, count 2 2006.173.17:50:50.61#ibcon#about to write, iclass 27, count 2 2006.173.17:50:50.61#ibcon#wrote, iclass 27, count 2 2006.173.17:50:50.61#ibcon#about to read 3, iclass 27, count 2 2006.173.17:50:50.64#ibcon#read 3, iclass 27, count 2 2006.173.17:50:50.64#ibcon#about to read 4, iclass 27, count 2 2006.173.17:50:50.64#ibcon#read 4, iclass 27, count 2 2006.173.17:50:50.64#ibcon#about to read 5, iclass 27, count 2 2006.173.17:50:50.64#ibcon#read 5, iclass 27, count 2 2006.173.17:50:50.64#ibcon#about to read 6, iclass 27, count 2 2006.173.17:50:50.64#ibcon#read 6, iclass 27, count 2 2006.173.17:50:50.64#ibcon#end of sib2, iclass 27, count 2 2006.173.17:50:50.64#ibcon#*after write, iclass 27, count 2 2006.173.17:50:50.64#ibcon#*before return 0, iclass 27, count 2 2006.173.17:50:50.64#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.17:50:50.64#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.17:50:50.64#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.17:50:50.64#ibcon#ireg 7 cls_cnt 0 2006.173.17:50:50.64#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.17:50:50.76#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.17:50:50.76#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.17:50:50.76#ibcon#enter wrdev, iclass 27, count 0 2006.173.17:50:50.76#ibcon#first serial, iclass 27, count 0 2006.173.17:50:50.76#ibcon#enter sib2, iclass 27, count 0 2006.173.17:50:50.76#ibcon#flushed, iclass 27, count 0 2006.173.17:50:50.76#ibcon#about to write, iclass 27, count 0 2006.173.17:50:50.76#ibcon#wrote, iclass 27, count 0 2006.173.17:50:50.76#ibcon#about to read 3, iclass 27, count 0 2006.173.17:50:50.78#ibcon#read 3, iclass 27, count 0 2006.173.17:50:50.78#ibcon#about to read 4, iclass 27, count 0 2006.173.17:50:50.78#ibcon#read 4, iclass 27, count 0 2006.173.17:50:50.78#ibcon#about to read 5, iclass 27, count 0 2006.173.17:50:50.78#ibcon#read 5, iclass 27, count 0 2006.173.17:50:50.78#ibcon#about to read 6, iclass 27, count 0 2006.173.17:50:50.78#ibcon#read 6, iclass 27, count 0 2006.173.17:50:50.78#ibcon#end of sib2, iclass 27, count 0 2006.173.17:50:50.78#ibcon#*mode == 0, iclass 27, count 0 2006.173.17:50:50.78#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.17:50:50.78#ibcon#[25=USB\r\n] 2006.173.17:50:50.78#ibcon#*before write, iclass 27, count 0 2006.173.17:50:50.78#ibcon#enter sib2, iclass 27, count 0 2006.173.17:50:50.78#ibcon#flushed, iclass 27, count 0 2006.173.17:50:50.78#ibcon#about to write, iclass 27, count 0 2006.173.17:50:50.78#ibcon#wrote, iclass 27, count 0 2006.173.17:50:50.78#ibcon#about to read 3, iclass 27, count 0 2006.173.17:50:50.81#ibcon#read 3, iclass 27, count 0 2006.173.17:50:50.81#ibcon#about to read 4, iclass 27, count 0 2006.173.17:50:50.81#ibcon#read 4, iclass 27, count 0 2006.173.17:50:50.81#ibcon#about to read 5, iclass 27, count 0 2006.173.17:50:50.81#ibcon#read 5, iclass 27, count 0 2006.173.17:50:50.81#ibcon#about to read 6, iclass 27, count 0 2006.173.17:50:50.81#ibcon#read 6, iclass 27, count 0 2006.173.17:50:50.81#ibcon#end of sib2, iclass 27, count 0 2006.173.17:50:50.81#ibcon#*after write, iclass 27, count 0 2006.173.17:50:50.81#ibcon#*before return 0, iclass 27, count 0 2006.173.17:50:50.81#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.17:50:50.81#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.17:50:50.81#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.17:50:50.81#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.17:50:50.81$vck44/valo=3,564.99 2006.173.17:50:50.81#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.17:50:50.81#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.17:50:50.81#ibcon#ireg 17 cls_cnt 0 2006.173.17:50:50.81#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.17:50:50.81#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.17:50:50.81#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.17:50:50.81#ibcon#enter wrdev, iclass 29, count 0 2006.173.17:50:50.81#ibcon#first serial, iclass 29, count 0 2006.173.17:50:50.81#ibcon#enter sib2, iclass 29, count 0 2006.173.17:50:50.81#ibcon#flushed, iclass 29, count 0 2006.173.17:50:50.81#ibcon#about to write, iclass 29, count 0 2006.173.17:50:50.81#ibcon#wrote, iclass 29, count 0 2006.173.17:50:50.81#ibcon#about to read 3, iclass 29, count 0 2006.173.17:50:50.83#ibcon#read 3, iclass 29, count 0 2006.173.17:50:50.83#ibcon#about to read 4, iclass 29, count 0 2006.173.17:50:50.83#ibcon#read 4, iclass 29, count 0 2006.173.17:50:50.83#ibcon#about to read 5, iclass 29, count 0 2006.173.17:50:50.83#ibcon#read 5, iclass 29, count 0 2006.173.17:50:50.83#ibcon#about to read 6, iclass 29, count 0 2006.173.17:50:50.83#ibcon#read 6, iclass 29, count 0 2006.173.17:50:50.83#ibcon#end of sib2, iclass 29, count 0 2006.173.17:50:50.83#ibcon#*mode == 0, iclass 29, count 0 2006.173.17:50:50.83#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.17:50:50.83#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.17:50:50.83#ibcon#*before write, iclass 29, count 0 2006.173.17:50:50.83#ibcon#enter sib2, iclass 29, count 0 2006.173.17:50:50.83#ibcon#flushed, iclass 29, count 0 2006.173.17:50:50.83#ibcon#about to write, iclass 29, count 0 2006.173.17:50:50.83#ibcon#wrote, iclass 29, count 0 2006.173.17:50:50.83#ibcon#about to read 3, iclass 29, count 0 2006.173.17:50:50.87#ibcon#read 3, iclass 29, count 0 2006.173.17:50:50.87#ibcon#about to read 4, iclass 29, count 0 2006.173.17:50:50.87#ibcon#read 4, iclass 29, count 0 2006.173.17:50:50.87#ibcon#about to read 5, iclass 29, count 0 2006.173.17:50:50.87#ibcon#read 5, iclass 29, count 0 2006.173.17:50:50.87#ibcon#about to read 6, iclass 29, count 0 2006.173.17:50:50.87#ibcon#read 6, iclass 29, count 0 2006.173.17:50:50.87#ibcon#end of sib2, iclass 29, count 0 2006.173.17:50:50.87#ibcon#*after write, iclass 29, count 0 2006.173.17:50:50.87#ibcon#*before return 0, iclass 29, count 0 2006.173.17:50:50.87#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.17:50:50.87#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.17:50:50.87#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.17:50:50.87#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.17:50:50.87$vck44/va=3,5 2006.173.17:50:50.87#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.17:50:50.87#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.17:50:50.87#ibcon#ireg 11 cls_cnt 2 2006.173.17:50:50.87#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.17:50:50.93#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.17:50:50.93#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.17:50:50.93#ibcon#enter wrdev, iclass 31, count 2 2006.173.17:50:50.93#ibcon#first serial, iclass 31, count 2 2006.173.17:50:50.93#ibcon#enter sib2, iclass 31, count 2 2006.173.17:50:50.93#ibcon#flushed, iclass 31, count 2 2006.173.17:50:50.93#ibcon#about to write, iclass 31, count 2 2006.173.17:50:50.93#ibcon#wrote, iclass 31, count 2 2006.173.17:50:50.93#ibcon#about to read 3, iclass 31, count 2 2006.173.17:50:50.95#ibcon#read 3, iclass 31, count 2 2006.173.17:50:50.95#ibcon#about to read 4, iclass 31, count 2 2006.173.17:50:50.95#ibcon#read 4, iclass 31, count 2 2006.173.17:50:50.95#ibcon#about to read 5, iclass 31, count 2 2006.173.17:50:50.95#ibcon#read 5, iclass 31, count 2 2006.173.17:50:50.95#ibcon#about to read 6, iclass 31, count 2 2006.173.17:50:50.95#ibcon#read 6, iclass 31, count 2 2006.173.17:50:50.95#ibcon#end of sib2, iclass 31, count 2 2006.173.17:50:50.95#ibcon#*mode == 0, iclass 31, count 2 2006.173.17:50:50.95#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.17:50:50.95#ibcon#[25=AT03-05\r\n] 2006.173.17:50:50.95#ibcon#*before write, iclass 31, count 2 2006.173.17:50:50.95#ibcon#enter sib2, iclass 31, count 2 2006.173.17:50:50.95#ibcon#flushed, iclass 31, count 2 2006.173.17:50:50.95#ibcon#about to write, iclass 31, count 2 2006.173.17:50:50.95#ibcon#wrote, iclass 31, count 2 2006.173.17:50:50.95#ibcon#about to read 3, iclass 31, count 2 2006.173.17:50:50.98#ibcon#read 3, iclass 31, count 2 2006.173.17:50:50.98#ibcon#about to read 4, iclass 31, count 2 2006.173.17:50:50.98#ibcon#read 4, iclass 31, count 2 2006.173.17:50:50.98#ibcon#about to read 5, iclass 31, count 2 2006.173.17:50:50.98#ibcon#read 5, iclass 31, count 2 2006.173.17:50:50.98#ibcon#about to read 6, iclass 31, count 2 2006.173.17:50:50.98#ibcon#read 6, iclass 31, count 2 2006.173.17:50:50.98#ibcon#end of sib2, iclass 31, count 2 2006.173.17:50:50.98#ibcon#*after write, iclass 31, count 2 2006.173.17:50:50.98#ibcon#*before return 0, iclass 31, count 2 2006.173.17:50:50.98#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.17:50:50.98#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.17:50:50.98#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.17:50:50.98#ibcon#ireg 7 cls_cnt 0 2006.173.17:50:50.98#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.17:50:51.10#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.17:50:51.10#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.17:50:51.10#ibcon#enter wrdev, iclass 31, count 0 2006.173.17:50:51.10#ibcon#first serial, iclass 31, count 0 2006.173.17:50:51.10#ibcon#enter sib2, iclass 31, count 0 2006.173.17:50:51.10#ibcon#flushed, iclass 31, count 0 2006.173.17:50:51.10#ibcon#about to write, iclass 31, count 0 2006.173.17:50:51.10#ibcon#wrote, iclass 31, count 0 2006.173.17:50:51.10#ibcon#about to read 3, iclass 31, count 0 2006.173.17:50:51.12#ibcon#read 3, iclass 31, count 0 2006.173.17:50:51.12#ibcon#about to read 4, iclass 31, count 0 2006.173.17:50:51.12#ibcon#read 4, iclass 31, count 0 2006.173.17:50:51.12#ibcon#about to read 5, iclass 31, count 0 2006.173.17:50:51.12#ibcon#read 5, iclass 31, count 0 2006.173.17:50:51.12#ibcon#about to read 6, iclass 31, count 0 2006.173.17:50:51.12#ibcon#read 6, iclass 31, count 0 2006.173.17:50:51.12#ibcon#end of sib2, iclass 31, count 0 2006.173.17:50:51.12#ibcon#*mode == 0, iclass 31, count 0 2006.173.17:50:51.12#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.17:50:51.12#ibcon#[25=USB\r\n] 2006.173.17:50:51.12#ibcon#*before write, iclass 31, count 0 2006.173.17:50:51.12#ibcon#enter sib2, iclass 31, count 0 2006.173.17:50:51.12#ibcon#flushed, iclass 31, count 0 2006.173.17:50:51.12#ibcon#about to write, iclass 31, count 0 2006.173.17:50:51.12#ibcon#wrote, iclass 31, count 0 2006.173.17:50:51.12#ibcon#about to read 3, iclass 31, count 0 2006.173.17:50:51.15#ibcon#read 3, iclass 31, count 0 2006.173.17:50:51.15#ibcon#about to read 4, iclass 31, count 0 2006.173.17:50:51.15#ibcon#read 4, iclass 31, count 0 2006.173.17:50:51.15#ibcon#about to read 5, iclass 31, count 0 2006.173.17:50:51.15#ibcon#read 5, iclass 31, count 0 2006.173.17:50:51.15#ibcon#about to read 6, iclass 31, count 0 2006.173.17:50:51.15#ibcon#read 6, iclass 31, count 0 2006.173.17:50:51.15#ibcon#end of sib2, iclass 31, count 0 2006.173.17:50:51.15#ibcon#*after write, iclass 31, count 0 2006.173.17:50:51.15#ibcon#*before return 0, iclass 31, count 0 2006.173.17:50:51.15#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.17:50:51.15#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.17:50:51.15#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.17:50:51.15#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.17:50:51.15$vck44/valo=4,624.99 2006.173.17:50:51.15#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.17:50:51.15#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.17:50:51.15#ibcon#ireg 17 cls_cnt 0 2006.173.17:50:51.15#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.17:50:51.15#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.17:50:51.15#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.17:50:51.15#ibcon#enter wrdev, iclass 33, count 0 2006.173.17:50:51.15#ibcon#first serial, iclass 33, count 0 2006.173.17:50:51.15#ibcon#enter sib2, iclass 33, count 0 2006.173.17:50:51.15#ibcon#flushed, iclass 33, count 0 2006.173.17:50:51.15#ibcon#about to write, iclass 33, count 0 2006.173.17:50:51.15#ibcon#wrote, iclass 33, count 0 2006.173.17:50:51.15#ibcon#about to read 3, iclass 33, count 0 2006.173.17:50:51.17#ibcon#read 3, iclass 33, count 0 2006.173.17:50:51.17#ibcon#about to read 4, iclass 33, count 0 2006.173.17:50:51.17#ibcon#read 4, iclass 33, count 0 2006.173.17:50:51.17#ibcon#about to read 5, iclass 33, count 0 2006.173.17:50:51.17#ibcon#read 5, iclass 33, count 0 2006.173.17:50:51.17#ibcon#about to read 6, iclass 33, count 0 2006.173.17:50:51.17#ibcon#read 6, iclass 33, count 0 2006.173.17:50:51.17#ibcon#end of sib2, iclass 33, count 0 2006.173.17:50:51.17#ibcon#*mode == 0, iclass 33, count 0 2006.173.17:50:51.17#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.17:50:51.17#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.17:50:51.17#ibcon#*before write, iclass 33, count 0 2006.173.17:50:51.17#ibcon#enter sib2, iclass 33, count 0 2006.173.17:50:51.17#ibcon#flushed, iclass 33, count 0 2006.173.17:50:51.17#ibcon#about to write, iclass 33, count 0 2006.173.17:50:51.17#ibcon#wrote, iclass 33, count 0 2006.173.17:50:51.17#ibcon#about to read 3, iclass 33, count 0 2006.173.17:50:51.21#ibcon#read 3, iclass 33, count 0 2006.173.17:50:51.21#ibcon#about to read 4, iclass 33, count 0 2006.173.17:50:51.21#ibcon#read 4, iclass 33, count 0 2006.173.17:50:51.21#ibcon#about to read 5, iclass 33, count 0 2006.173.17:50:51.21#ibcon#read 5, iclass 33, count 0 2006.173.17:50:51.21#ibcon#about to read 6, iclass 33, count 0 2006.173.17:50:51.21#ibcon#read 6, iclass 33, count 0 2006.173.17:50:51.21#ibcon#end of sib2, iclass 33, count 0 2006.173.17:50:51.21#ibcon#*after write, iclass 33, count 0 2006.173.17:50:51.21#ibcon#*before return 0, iclass 33, count 0 2006.173.17:50:51.21#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.17:50:51.21#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.17:50:51.21#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.17:50:51.21#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.17:50:51.21$vck44/va=4,6 2006.173.17:50:51.21#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.17:50:51.21#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.17:50:51.21#ibcon#ireg 11 cls_cnt 2 2006.173.17:50:51.21#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.17:50:51.27#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.17:50:51.27#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.17:50:51.27#ibcon#enter wrdev, iclass 35, count 2 2006.173.17:50:51.27#ibcon#first serial, iclass 35, count 2 2006.173.17:50:51.27#ibcon#enter sib2, iclass 35, count 2 2006.173.17:50:51.27#ibcon#flushed, iclass 35, count 2 2006.173.17:50:51.27#ibcon#about to write, iclass 35, count 2 2006.173.17:50:51.27#ibcon#wrote, iclass 35, count 2 2006.173.17:50:51.27#ibcon#about to read 3, iclass 35, count 2 2006.173.17:50:51.29#ibcon#read 3, iclass 35, count 2 2006.173.17:50:51.29#ibcon#about to read 4, iclass 35, count 2 2006.173.17:50:51.29#ibcon#read 4, iclass 35, count 2 2006.173.17:50:51.29#ibcon#about to read 5, iclass 35, count 2 2006.173.17:50:51.29#ibcon#read 5, iclass 35, count 2 2006.173.17:50:51.29#ibcon#about to read 6, iclass 35, count 2 2006.173.17:50:51.29#ibcon#read 6, iclass 35, count 2 2006.173.17:50:51.29#ibcon#end of sib2, iclass 35, count 2 2006.173.17:50:51.29#ibcon#*mode == 0, iclass 35, count 2 2006.173.17:50:51.29#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.17:50:51.29#ibcon#[25=AT04-06\r\n] 2006.173.17:50:51.29#ibcon#*before write, iclass 35, count 2 2006.173.17:50:51.29#ibcon#enter sib2, iclass 35, count 2 2006.173.17:50:51.29#ibcon#flushed, iclass 35, count 2 2006.173.17:50:51.29#ibcon#about to write, iclass 35, count 2 2006.173.17:50:51.29#ibcon#wrote, iclass 35, count 2 2006.173.17:50:51.29#ibcon#about to read 3, iclass 35, count 2 2006.173.17:50:51.32#ibcon#read 3, iclass 35, count 2 2006.173.17:50:51.32#ibcon#about to read 4, iclass 35, count 2 2006.173.17:50:51.32#ibcon#read 4, iclass 35, count 2 2006.173.17:50:51.32#ibcon#about to read 5, iclass 35, count 2 2006.173.17:50:51.32#ibcon#read 5, iclass 35, count 2 2006.173.17:50:51.32#ibcon#about to read 6, iclass 35, count 2 2006.173.17:50:51.32#ibcon#read 6, iclass 35, count 2 2006.173.17:50:51.32#ibcon#end of sib2, iclass 35, count 2 2006.173.17:50:51.32#ibcon#*after write, iclass 35, count 2 2006.173.17:50:51.32#ibcon#*before return 0, iclass 35, count 2 2006.173.17:50:51.32#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.17:50:51.32#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.17:50:51.32#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.17:50:51.32#ibcon#ireg 7 cls_cnt 0 2006.173.17:50:51.32#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.17:50:51.36#abcon#<5=/14 1.2 3.2 20.111001002.2\r\n> 2006.173.17:50:51.38#abcon#{5=INTERFACE CLEAR} 2006.173.17:50:51.44#abcon#[5=S1D000X0/0*\r\n] 2006.173.17:50:51.44#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.17:50:51.44#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.17:50:51.44#ibcon#enter wrdev, iclass 35, count 0 2006.173.17:50:51.44#ibcon#first serial, iclass 35, count 0 2006.173.17:50:51.44#ibcon#enter sib2, iclass 35, count 0 2006.173.17:50:51.44#ibcon#flushed, iclass 35, count 0 2006.173.17:50:51.44#ibcon#about to write, iclass 35, count 0 2006.173.17:50:51.44#ibcon#wrote, iclass 35, count 0 2006.173.17:50:51.44#ibcon#about to read 3, iclass 35, count 0 2006.173.17:50:51.46#ibcon#read 3, iclass 35, count 0 2006.173.17:50:51.46#ibcon#about to read 4, iclass 35, count 0 2006.173.17:50:51.46#ibcon#read 4, iclass 35, count 0 2006.173.17:50:51.46#ibcon#about to read 5, iclass 35, count 0 2006.173.17:50:51.46#ibcon#read 5, iclass 35, count 0 2006.173.17:50:51.46#ibcon#about to read 6, iclass 35, count 0 2006.173.17:50:51.46#ibcon#read 6, iclass 35, count 0 2006.173.17:50:51.46#ibcon#end of sib2, iclass 35, count 0 2006.173.17:50:51.46#ibcon#*mode == 0, iclass 35, count 0 2006.173.17:50:51.46#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.17:50:51.46#ibcon#[25=USB\r\n] 2006.173.17:50:51.46#ibcon#*before write, iclass 35, count 0 2006.173.17:50:51.46#ibcon#enter sib2, iclass 35, count 0 2006.173.17:50:51.46#ibcon#flushed, iclass 35, count 0 2006.173.17:50:51.46#ibcon#about to write, iclass 35, count 0 2006.173.17:50:51.46#ibcon#wrote, iclass 35, count 0 2006.173.17:50:51.46#ibcon#about to read 3, iclass 35, count 0 2006.173.17:50:51.49#ibcon#read 3, iclass 35, count 0 2006.173.17:50:51.49#ibcon#about to read 4, iclass 35, count 0 2006.173.17:50:51.49#ibcon#read 4, iclass 35, count 0 2006.173.17:50:51.49#ibcon#about to read 5, iclass 35, count 0 2006.173.17:50:51.49#ibcon#read 5, iclass 35, count 0 2006.173.17:50:51.49#ibcon#about to read 6, iclass 35, count 0 2006.173.17:50:51.49#ibcon#read 6, iclass 35, count 0 2006.173.17:50:51.49#ibcon#end of sib2, iclass 35, count 0 2006.173.17:50:51.49#ibcon#*after write, iclass 35, count 0 2006.173.17:50:51.49#ibcon#*before return 0, iclass 35, count 0 2006.173.17:50:51.49#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.17:50:51.49#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.17:50:51.49#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.17:50:51.49#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.17:50:51.49$vck44/valo=5,734.99 2006.173.17:50:51.49#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.17:50:51.49#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.17:50:51.49#ibcon#ireg 17 cls_cnt 0 2006.173.17:50:51.49#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.17:50:51.49#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.17:50:51.49#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.17:50:51.49#ibcon#enter wrdev, iclass 3, count 0 2006.173.17:50:51.49#ibcon#first serial, iclass 3, count 0 2006.173.17:50:51.49#ibcon#enter sib2, iclass 3, count 0 2006.173.17:50:51.49#ibcon#flushed, iclass 3, count 0 2006.173.17:50:51.49#ibcon#about to write, iclass 3, count 0 2006.173.17:50:51.49#ibcon#wrote, iclass 3, count 0 2006.173.17:50:51.49#ibcon#about to read 3, iclass 3, count 0 2006.173.17:50:51.51#ibcon#read 3, iclass 3, count 0 2006.173.17:50:51.51#ibcon#about to read 4, iclass 3, count 0 2006.173.17:50:51.51#ibcon#read 4, iclass 3, count 0 2006.173.17:50:51.51#ibcon#about to read 5, iclass 3, count 0 2006.173.17:50:51.51#ibcon#read 5, iclass 3, count 0 2006.173.17:50:51.51#ibcon#about to read 6, iclass 3, count 0 2006.173.17:50:51.51#ibcon#read 6, iclass 3, count 0 2006.173.17:50:51.51#ibcon#end of sib2, iclass 3, count 0 2006.173.17:50:51.51#ibcon#*mode == 0, iclass 3, count 0 2006.173.17:50:51.51#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.17:50:51.51#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.17:50:51.51#ibcon#*before write, iclass 3, count 0 2006.173.17:50:51.51#ibcon#enter sib2, iclass 3, count 0 2006.173.17:50:51.51#ibcon#flushed, iclass 3, count 0 2006.173.17:50:51.51#ibcon#about to write, iclass 3, count 0 2006.173.17:50:51.51#ibcon#wrote, iclass 3, count 0 2006.173.17:50:51.51#ibcon#about to read 3, iclass 3, count 0 2006.173.17:50:51.55#ibcon#read 3, iclass 3, count 0 2006.173.17:50:51.55#ibcon#about to read 4, iclass 3, count 0 2006.173.17:50:51.55#ibcon#read 4, iclass 3, count 0 2006.173.17:50:51.55#ibcon#about to read 5, iclass 3, count 0 2006.173.17:50:51.55#ibcon#read 5, iclass 3, count 0 2006.173.17:50:51.55#ibcon#about to read 6, iclass 3, count 0 2006.173.17:50:51.55#ibcon#read 6, iclass 3, count 0 2006.173.17:50:51.55#ibcon#end of sib2, iclass 3, count 0 2006.173.17:50:51.55#ibcon#*after write, iclass 3, count 0 2006.173.17:50:51.55#ibcon#*before return 0, iclass 3, count 0 2006.173.17:50:51.55#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.17:50:51.55#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.17:50:51.55#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.17:50:51.55#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.17:50:51.55$vck44/va=5,4 2006.173.17:50:51.55#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.17:50:51.55#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.17:50:51.55#ibcon#ireg 11 cls_cnt 2 2006.173.17:50:51.55#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.17:50:51.61#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.17:50:51.61#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.17:50:51.61#ibcon#enter wrdev, iclass 5, count 2 2006.173.17:50:51.61#ibcon#first serial, iclass 5, count 2 2006.173.17:50:51.61#ibcon#enter sib2, iclass 5, count 2 2006.173.17:50:51.61#ibcon#flushed, iclass 5, count 2 2006.173.17:50:51.61#ibcon#about to write, iclass 5, count 2 2006.173.17:50:51.61#ibcon#wrote, iclass 5, count 2 2006.173.17:50:51.61#ibcon#about to read 3, iclass 5, count 2 2006.173.17:50:51.63#ibcon#read 3, iclass 5, count 2 2006.173.17:50:51.63#ibcon#about to read 4, iclass 5, count 2 2006.173.17:50:51.63#ibcon#read 4, iclass 5, count 2 2006.173.17:50:51.63#ibcon#about to read 5, iclass 5, count 2 2006.173.17:50:51.63#ibcon#read 5, iclass 5, count 2 2006.173.17:50:51.63#ibcon#about to read 6, iclass 5, count 2 2006.173.17:50:51.63#ibcon#read 6, iclass 5, count 2 2006.173.17:50:51.63#ibcon#end of sib2, iclass 5, count 2 2006.173.17:50:51.63#ibcon#*mode == 0, iclass 5, count 2 2006.173.17:50:51.63#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.17:50:51.63#ibcon#[25=AT05-04\r\n] 2006.173.17:50:51.63#ibcon#*before write, iclass 5, count 2 2006.173.17:50:51.63#ibcon#enter sib2, iclass 5, count 2 2006.173.17:50:51.63#ibcon#flushed, iclass 5, count 2 2006.173.17:50:51.63#ibcon#about to write, iclass 5, count 2 2006.173.17:50:51.63#ibcon#wrote, iclass 5, count 2 2006.173.17:50:51.63#ibcon#about to read 3, iclass 5, count 2 2006.173.17:50:51.66#ibcon#read 3, iclass 5, count 2 2006.173.17:50:51.66#ibcon#about to read 4, iclass 5, count 2 2006.173.17:50:51.66#ibcon#read 4, iclass 5, count 2 2006.173.17:50:51.66#ibcon#about to read 5, iclass 5, count 2 2006.173.17:50:51.66#ibcon#read 5, iclass 5, count 2 2006.173.17:50:51.66#ibcon#about to read 6, iclass 5, count 2 2006.173.17:50:51.66#ibcon#read 6, iclass 5, count 2 2006.173.17:50:51.66#ibcon#end of sib2, iclass 5, count 2 2006.173.17:50:51.66#ibcon#*after write, iclass 5, count 2 2006.173.17:50:51.66#ibcon#*before return 0, iclass 5, count 2 2006.173.17:50:51.66#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.17:50:51.66#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.17:50:51.66#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.17:50:51.66#ibcon#ireg 7 cls_cnt 0 2006.173.17:50:51.66#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.17:50:51.78#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.17:50:51.78#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.17:50:51.78#ibcon#enter wrdev, iclass 5, count 0 2006.173.17:50:51.78#ibcon#first serial, iclass 5, count 0 2006.173.17:50:51.78#ibcon#enter sib2, iclass 5, count 0 2006.173.17:50:51.78#ibcon#flushed, iclass 5, count 0 2006.173.17:50:51.78#ibcon#about to write, iclass 5, count 0 2006.173.17:50:51.78#ibcon#wrote, iclass 5, count 0 2006.173.17:50:51.78#ibcon#about to read 3, iclass 5, count 0 2006.173.17:50:51.80#ibcon#read 3, iclass 5, count 0 2006.173.17:50:51.80#ibcon#about to read 4, iclass 5, count 0 2006.173.17:50:51.80#ibcon#read 4, iclass 5, count 0 2006.173.17:50:51.80#ibcon#about to read 5, iclass 5, count 0 2006.173.17:50:51.80#ibcon#read 5, iclass 5, count 0 2006.173.17:50:51.80#ibcon#about to read 6, iclass 5, count 0 2006.173.17:50:51.80#ibcon#read 6, iclass 5, count 0 2006.173.17:50:51.80#ibcon#end of sib2, iclass 5, count 0 2006.173.17:50:51.80#ibcon#*mode == 0, iclass 5, count 0 2006.173.17:50:51.80#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.17:50:51.80#ibcon#[25=USB\r\n] 2006.173.17:50:51.80#ibcon#*before write, iclass 5, count 0 2006.173.17:50:51.80#ibcon#enter sib2, iclass 5, count 0 2006.173.17:50:51.80#ibcon#flushed, iclass 5, count 0 2006.173.17:50:51.80#ibcon#about to write, iclass 5, count 0 2006.173.17:50:51.80#ibcon#wrote, iclass 5, count 0 2006.173.17:50:51.80#ibcon#about to read 3, iclass 5, count 0 2006.173.17:50:51.83#ibcon#read 3, iclass 5, count 0 2006.173.17:50:51.83#ibcon#about to read 4, iclass 5, count 0 2006.173.17:50:51.83#ibcon#read 4, iclass 5, count 0 2006.173.17:50:51.83#ibcon#about to read 5, iclass 5, count 0 2006.173.17:50:51.83#ibcon#read 5, iclass 5, count 0 2006.173.17:50:51.83#ibcon#about to read 6, iclass 5, count 0 2006.173.17:50:51.83#ibcon#read 6, iclass 5, count 0 2006.173.17:50:51.83#ibcon#end of sib2, iclass 5, count 0 2006.173.17:50:51.83#ibcon#*after write, iclass 5, count 0 2006.173.17:50:51.83#ibcon#*before return 0, iclass 5, count 0 2006.173.17:50:51.83#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.17:50:51.83#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.17:50:51.83#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.17:50:51.83#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.17:50:51.83$vck44/valo=6,814.99 2006.173.17:50:51.83#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.17:50:51.83#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.17:50:51.83#ibcon#ireg 17 cls_cnt 0 2006.173.17:50:51.83#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.17:50:51.83#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.17:50:51.83#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.17:50:51.83#ibcon#enter wrdev, iclass 7, count 0 2006.173.17:50:51.83#ibcon#first serial, iclass 7, count 0 2006.173.17:50:51.83#ibcon#enter sib2, iclass 7, count 0 2006.173.17:50:51.83#ibcon#flushed, iclass 7, count 0 2006.173.17:50:51.83#ibcon#about to write, iclass 7, count 0 2006.173.17:50:51.83#ibcon#wrote, iclass 7, count 0 2006.173.17:50:51.83#ibcon#about to read 3, iclass 7, count 0 2006.173.17:50:51.85#ibcon#read 3, iclass 7, count 0 2006.173.17:50:51.85#ibcon#about to read 4, iclass 7, count 0 2006.173.17:50:51.85#ibcon#read 4, iclass 7, count 0 2006.173.17:50:51.85#ibcon#about to read 5, iclass 7, count 0 2006.173.17:50:51.85#ibcon#read 5, iclass 7, count 0 2006.173.17:50:51.85#ibcon#about to read 6, iclass 7, count 0 2006.173.17:50:51.85#ibcon#read 6, iclass 7, count 0 2006.173.17:50:51.85#ibcon#end of sib2, iclass 7, count 0 2006.173.17:50:51.85#ibcon#*mode == 0, iclass 7, count 0 2006.173.17:50:51.85#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.17:50:51.85#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.17:50:51.85#ibcon#*before write, iclass 7, count 0 2006.173.17:50:51.85#ibcon#enter sib2, iclass 7, count 0 2006.173.17:50:51.85#ibcon#flushed, iclass 7, count 0 2006.173.17:50:51.85#ibcon#about to write, iclass 7, count 0 2006.173.17:50:51.85#ibcon#wrote, iclass 7, count 0 2006.173.17:50:51.85#ibcon#about to read 3, iclass 7, count 0 2006.173.17:50:51.89#ibcon#read 3, iclass 7, count 0 2006.173.17:50:51.89#ibcon#about to read 4, iclass 7, count 0 2006.173.17:50:51.89#ibcon#read 4, iclass 7, count 0 2006.173.17:50:51.89#ibcon#about to read 5, iclass 7, count 0 2006.173.17:50:51.89#ibcon#read 5, iclass 7, count 0 2006.173.17:50:51.89#ibcon#about to read 6, iclass 7, count 0 2006.173.17:50:51.89#ibcon#read 6, iclass 7, count 0 2006.173.17:50:51.89#ibcon#end of sib2, iclass 7, count 0 2006.173.17:50:51.89#ibcon#*after write, iclass 7, count 0 2006.173.17:50:51.89#ibcon#*before return 0, iclass 7, count 0 2006.173.17:50:51.89#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.17:50:51.89#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.17:50:51.89#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.17:50:51.89#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.17:50:51.89$vck44/va=6,3 2006.173.17:50:51.89#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.17:50:51.89#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.17:50:51.89#ibcon#ireg 11 cls_cnt 2 2006.173.17:50:51.89#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.17:50:51.95#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.17:50:51.95#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.17:50:51.95#ibcon#enter wrdev, iclass 11, count 2 2006.173.17:50:51.95#ibcon#first serial, iclass 11, count 2 2006.173.17:50:51.95#ibcon#enter sib2, iclass 11, count 2 2006.173.17:50:51.95#ibcon#flushed, iclass 11, count 2 2006.173.17:50:51.95#ibcon#about to write, iclass 11, count 2 2006.173.17:50:51.95#ibcon#wrote, iclass 11, count 2 2006.173.17:50:51.95#ibcon#about to read 3, iclass 11, count 2 2006.173.17:50:51.97#ibcon#read 3, iclass 11, count 2 2006.173.17:50:51.97#ibcon#about to read 4, iclass 11, count 2 2006.173.17:50:51.97#ibcon#read 4, iclass 11, count 2 2006.173.17:50:51.97#ibcon#about to read 5, iclass 11, count 2 2006.173.17:50:51.97#ibcon#read 5, iclass 11, count 2 2006.173.17:50:51.97#ibcon#about to read 6, iclass 11, count 2 2006.173.17:50:51.97#ibcon#read 6, iclass 11, count 2 2006.173.17:50:51.97#ibcon#end of sib2, iclass 11, count 2 2006.173.17:50:51.97#ibcon#*mode == 0, iclass 11, count 2 2006.173.17:50:51.97#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.17:50:51.97#ibcon#[25=AT06-03\r\n] 2006.173.17:50:51.97#ibcon#*before write, iclass 11, count 2 2006.173.17:50:51.97#ibcon#enter sib2, iclass 11, count 2 2006.173.17:50:51.97#ibcon#flushed, iclass 11, count 2 2006.173.17:50:51.97#ibcon#about to write, iclass 11, count 2 2006.173.17:50:51.97#ibcon#wrote, iclass 11, count 2 2006.173.17:50:51.97#ibcon#about to read 3, iclass 11, count 2 2006.173.17:50:52.00#ibcon#read 3, iclass 11, count 2 2006.173.17:50:52.00#ibcon#about to read 4, iclass 11, count 2 2006.173.17:50:52.00#ibcon#read 4, iclass 11, count 2 2006.173.17:50:52.00#ibcon#about to read 5, iclass 11, count 2 2006.173.17:50:52.00#ibcon#read 5, iclass 11, count 2 2006.173.17:50:52.00#ibcon#about to read 6, iclass 11, count 2 2006.173.17:50:52.00#ibcon#read 6, iclass 11, count 2 2006.173.17:50:52.00#ibcon#end of sib2, iclass 11, count 2 2006.173.17:50:52.00#ibcon#*after write, iclass 11, count 2 2006.173.17:50:52.00#ibcon#*before return 0, iclass 11, count 2 2006.173.17:50:52.00#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.17:50:52.00#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.17:50:52.00#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.17:50:52.00#ibcon#ireg 7 cls_cnt 0 2006.173.17:50:52.00#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.17:50:52.12#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.17:50:52.12#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.17:50:52.12#ibcon#enter wrdev, iclass 11, count 0 2006.173.17:50:52.12#ibcon#first serial, iclass 11, count 0 2006.173.17:50:52.12#ibcon#enter sib2, iclass 11, count 0 2006.173.17:50:52.12#ibcon#flushed, iclass 11, count 0 2006.173.17:50:52.12#ibcon#about to write, iclass 11, count 0 2006.173.17:50:52.12#ibcon#wrote, iclass 11, count 0 2006.173.17:50:52.12#ibcon#about to read 3, iclass 11, count 0 2006.173.17:50:52.14#ibcon#read 3, iclass 11, count 0 2006.173.17:50:52.14#ibcon#about to read 4, iclass 11, count 0 2006.173.17:50:52.14#ibcon#read 4, iclass 11, count 0 2006.173.17:50:52.14#ibcon#about to read 5, iclass 11, count 0 2006.173.17:50:52.14#ibcon#read 5, iclass 11, count 0 2006.173.17:50:52.14#ibcon#about to read 6, iclass 11, count 0 2006.173.17:50:52.14#ibcon#read 6, iclass 11, count 0 2006.173.17:50:52.14#ibcon#end of sib2, iclass 11, count 0 2006.173.17:50:52.14#ibcon#*mode == 0, iclass 11, count 0 2006.173.17:50:52.14#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.17:50:52.14#ibcon#[25=USB\r\n] 2006.173.17:50:52.14#ibcon#*before write, iclass 11, count 0 2006.173.17:50:52.14#ibcon#enter sib2, iclass 11, count 0 2006.173.17:50:52.14#ibcon#flushed, iclass 11, count 0 2006.173.17:50:52.14#ibcon#about to write, iclass 11, count 0 2006.173.17:50:52.14#ibcon#wrote, iclass 11, count 0 2006.173.17:50:52.14#ibcon#about to read 3, iclass 11, count 0 2006.173.17:50:52.17#ibcon#read 3, iclass 11, count 0 2006.173.17:50:52.17#ibcon#about to read 4, iclass 11, count 0 2006.173.17:50:52.17#ibcon#read 4, iclass 11, count 0 2006.173.17:50:52.17#ibcon#about to read 5, iclass 11, count 0 2006.173.17:50:52.17#ibcon#read 5, iclass 11, count 0 2006.173.17:50:52.17#ibcon#about to read 6, iclass 11, count 0 2006.173.17:50:52.17#ibcon#read 6, iclass 11, count 0 2006.173.17:50:52.17#ibcon#end of sib2, iclass 11, count 0 2006.173.17:50:52.17#ibcon#*after write, iclass 11, count 0 2006.173.17:50:52.17#ibcon#*before return 0, iclass 11, count 0 2006.173.17:50:52.17#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.17:50:52.17#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.17:50:52.17#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.17:50:52.17#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.17:50:52.17$vck44/valo=7,864.99 2006.173.17:50:52.17#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.17:50:52.17#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.17:50:52.17#ibcon#ireg 17 cls_cnt 0 2006.173.17:50:52.17#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.17:50:52.17#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.17:50:52.17#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.17:50:52.17#ibcon#enter wrdev, iclass 13, count 0 2006.173.17:50:52.17#ibcon#first serial, iclass 13, count 0 2006.173.17:50:52.17#ibcon#enter sib2, iclass 13, count 0 2006.173.17:50:52.17#ibcon#flushed, iclass 13, count 0 2006.173.17:50:52.17#ibcon#about to write, iclass 13, count 0 2006.173.17:50:52.17#ibcon#wrote, iclass 13, count 0 2006.173.17:50:52.17#ibcon#about to read 3, iclass 13, count 0 2006.173.17:50:52.19#ibcon#read 3, iclass 13, count 0 2006.173.17:50:52.19#ibcon#about to read 4, iclass 13, count 0 2006.173.17:50:52.19#ibcon#read 4, iclass 13, count 0 2006.173.17:50:52.19#ibcon#about to read 5, iclass 13, count 0 2006.173.17:50:52.19#ibcon#read 5, iclass 13, count 0 2006.173.17:50:52.19#ibcon#about to read 6, iclass 13, count 0 2006.173.17:50:52.19#ibcon#read 6, iclass 13, count 0 2006.173.17:50:52.19#ibcon#end of sib2, iclass 13, count 0 2006.173.17:50:52.19#ibcon#*mode == 0, iclass 13, count 0 2006.173.17:50:52.19#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.17:50:52.19#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.17:50:52.19#ibcon#*before write, iclass 13, count 0 2006.173.17:50:52.19#ibcon#enter sib2, iclass 13, count 0 2006.173.17:50:52.19#ibcon#flushed, iclass 13, count 0 2006.173.17:50:52.19#ibcon#about to write, iclass 13, count 0 2006.173.17:50:52.19#ibcon#wrote, iclass 13, count 0 2006.173.17:50:52.19#ibcon#about to read 3, iclass 13, count 0 2006.173.17:50:52.23#ibcon#read 3, iclass 13, count 0 2006.173.17:50:52.23#ibcon#about to read 4, iclass 13, count 0 2006.173.17:50:52.23#ibcon#read 4, iclass 13, count 0 2006.173.17:50:52.23#ibcon#about to read 5, iclass 13, count 0 2006.173.17:50:52.23#ibcon#read 5, iclass 13, count 0 2006.173.17:50:52.23#ibcon#about to read 6, iclass 13, count 0 2006.173.17:50:52.23#ibcon#read 6, iclass 13, count 0 2006.173.17:50:52.23#ibcon#end of sib2, iclass 13, count 0 2006.173.17:50:52.23#ibcon#*after write, iclass 13, count 0 2006.173.17:50:52.23#ibcon#*before return 0, iclass 13, count 0 2006.173.17:50:52.23#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.17:50:52.23#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.17:50:52.23#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.17:50:52.23#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.17:50:52.23$vck44/va=7,4 2006.173.17:50:52.23#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.17:50:52.23#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.17:50:52.23#ibcon#ireg 11 cls_cnt 2 2006.173.17:50:52.23#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.17:50:52.29#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.17:50:52.29#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.17:50:52.29#ibcon#enter wrdev, iclass 15, count 2 2006.173.17:50:52.29#ibcon#first serial, iclass 15, count 2 2006.173.17:50:52.29#ibcon#enter sib2, iclass 15, count 2 2006.173.17:50:52.29#ibcon#flushed, iclass 15, count 2 2006.173.17:50:52.29#ibcon#about to write, iclass 15, count 2 2006.173.17:50:52.29#ibcon#wrote, iclass 15, count 2 2006.173.17:50:52.29#ibcon#about to read 3, iclass 15, count 2 2006.173.17:50:52.31#ibcon#read 3, iclass 15, count 2 2006.173.17:50:52.31#ibcon#about to read 4, iclass 15, count 2 2006.173.17:50:52.31#ibcon#read 4, iclass 15, count 2 2006.173.17:50:52.31#ibcon#about to read 5, iclass 15, count 2 2006.173.17:50:52.31#ibcon#read 5, iclass 15, count 2 2006.173.17:50:52.31#ibcon#about to read 6, iclass 15, count 2 2006.173.17:50:52.31#ibcon#read 6, iclass 15, count 2 2006.173.17:50:52.31#ibcon#end of sib2, iclass 15, count 2 2006.173.17:50:52.31#ibcon#*mode == 0, iclass 15, count 2 2006.173.17:50:52.31#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.17:50:52.31#ibcon#[25=AT07-04\r\n] 2006.173.17:50:52.31#ibcon#*before write, iclass 15, count 2 2006.173.17:50:52.31#ibcon#enter sib2, iclass 15, count 2 2006.173.17:50:52.31#ibcon#flushed, iclass 15, count 2 2006.173.17:50:52.31#ibcon#about to write, iclass 15, count 2 2006.173.17:50:52.31#ibcon#wrote, iclass 15, count 2 2006.173.17:50:52.31#ibcon#about to read 3, iclass 15, count 2 2006.173.17:50:52.34#ibcon#read 3, iclass 15, count 2 2006.173.17:50:52.34#ibcon#about to read 4, iclass 15, count 2 2006.173.17:50:52.34#ibcon#read 4, iclass 15, count 2 2006.173.17:50:52.34#ibcon#about to read 5, iclass 15, count 2 2006.173.17:50:52.34#ibcon#read 5, iclass 15, count 2 2006.173.17:50:52.34#ibcon#about to read 6, iclass 15, count 2 2006.173.17:50:52.34#ibcon#read 6, iclass 15, count 2 2006.173.17:50:52.34#ibcon#end of sib2, iclass 15, count 2 2006.173.17:50:52.34#ibcon#*after write, iclass 15, count 2 2006.173.17:50:52.34#ibcon#*before return 0, iclass 15, count 2 2006.173.17:50:52.34#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.17:50:52.34#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.17:50:52.34#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.17:50:52.34#ibcon#ireg 7 cls_cnt 0 2006.173.17:50:52.34#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.17:50:52.46#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.17:50:52.46#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.17:50:52.46#ibcon#enter wrdev, iclass 15, count 0 2006.173.17:50:52.46#ibcon#first serial, iclass 15, count 0 2006.173.17:50:52.46#ibcon#enter sib2, iclass 15, count 0 2006.173.17:50:52.46#ibcon#flushed, iclass 15, count 0 2006.173.17:50:52.46#ibcon#about to write, iclass 15, count 0 2006.173.17:50:52.46#ibcon#wrote, iclass 15, count 0 2006.173.17:50:52.46#ibcon#about to read 3, iclass 15, count 0 2006.173.17:50:52.48#ibcon#read 3, iclass 15, count 0 2006.173.17:50:52.48#ibcon#about to read 4, iclass 15, count 0 2006.173.17:50:52.48#ibcon#read 4, iclass 15, count 0 2006.173.17:50:52.48#ibcon#about to read 5, iclass 15, count 0 2006.173.17:50:52.48#ibcon#read 5, iclass 15, count 0 2006.173.17:50:52.48#ibcon#about to read 6, iclass 15, count 0 2006.173.17:50:52.48#ibcon#read 6, iclass 15, count 0 2006.173.17:50:52.48#ibcon#end of sib2, iclass 15, count 0 2006.173.17:50:52.48#ibcon#*mode == 0, iclass 15, count 0 2006.173.17:50:52.48#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.17:50:52.48#ibcon#[25=USB\r\n] 2006.173.17:50:52.48#ibcon#*before write, iclass 15, count 0 2006.173.17:50:52.48#ibcon#enter sib2, iclass 15, count 0 2006.173.17:50:52.48#ibcon#flushed, iclass 15, count 0 2006.173.17:50:52.48#ibcon#about to write, iclass 15, count 0 2006.173.17:50:52.48#ibcon#wrote, iclass 15, count 0 2006.173.17:50:52.48#ibcon#about to read 3, iclass 15, count 0 2006.173.17:50:52.51#ibcon#read 3, iclass 15, count 0 2006.173.17:50:52.51#ibcon#about to read 4, iclass 15, count 0 2006.173.17:50:52.51#ibcon#read 4, iclass 15, count 0 2006.173.17:50:52.51#ibcon#about to read 5, iclass 15, count 0 2006.173.17:50:52.51#ibcon#read 5, iclass 15, count 0 2006.173.17:50:52.51#ibcon#about to read 6, iclass 15, count 0 2006.173.17:50:52.51#ibcon#read 6, iclass 15, count 0 2006.173.17:50:52.51#ibcon#end of sib2, iclass 15, count 0 2006.173.17:50:52.51#ibcon#*after write, iclass 15, count 0 2006.173.17:50:52.51#ibcon#*before return 0, iclass 15, count 0 2006.173.17:50:52.51#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.17:50:52.51#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.17:50:52.51#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.17:50:52.51#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.17:50:52.51$vck44/valo=8,884.99 2006.173.17:50:52.51#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.17:50:52.51#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.17:50:52.51#ibcon#ireg 17 cls_cnt 0 2006.173.17:50:52.51#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.17:50:52.51#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.17:50:52.51#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.17:50:52.51#ibcon#enter wrdev, iclass 17, count 0 2006.173.17:50:52.51#ibcon#first serial, iclass 17, count 0 2006.173.17:50:52.51#ibcon#enter sib2, iclass 17, count 0 2006.173.17:50:52.51#ibcon#flushed, iclass 17, count 0 2006.173.17:50:52.51#ibcon#about to write, iclass 17, count 0 2006.173.17:50:52.51#ibcon#wrote, iclass 17, count 0 2006.173.17:50:52.51#ibcon#about to read 3, iclass 17, count 0 2006.173.17:50:52.53#ibcon#read 3, iclass 17, count 0 2006.173.17:50:52.53#ibcon#about to read 4, iclass 17, count 0 2006.173.17:50:52.53#ibcon#read 4, iclass 17, count 0 2006.173.17:50:52.53#ibcon#about to read 5, iclass 17, count 0 2006.173.17:50:52.53#ibcon#read 5, iclass 17, count 0 2006.173.17:50:52.53#ibcon#about to read 6, iclass 17, count 0 2006.173.17:50:52.53#ibcon#read 6, iclass 17, count 0 2006.173.17:50:52.53#ibcon#end of sib2, iclass 17, count 0 2006.173.17:50:52.53#ibcon#*mode == 0, iclass 17, count 0 2006.173.17:50:52.53#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.17:50:52.53#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.17:50:52.53#ibcon#*before write, iclass 17, count 0 2006.173.17:50:52.53#ibcon#enter sib2, iclass 17, count 0 2006.173.17:50:52.53#ibcon#flushed, iclass 17, count 0 2006.173.17:50:52.53#ibcon#about to write, iclass 17, count 0 2006.173.17:50:52.53#ibcon#wrote, iclass 17, count 0 2006.173.17:50:52.53#ibcon#about to read 3, iclass 17, count 0 2006.173.17:50:52.57#ibcon#read 3, iclass 17, count 0 2006.173.17:50:52.57#ibcon#about to read 4, iclass 17, count 0 2006.173.17:50:52.57#ibcon#read 4, iclass 17, count 0 2006.173.17:50:52.57#ibcon#about to read 5, iclass 17, count 0 2006.173.17:50:52.57#ibcon#read 5, iclass 17, count 0 2006.173.17:50:52.57#ibcon#about to read 6, iclass 17, count 0 2006.173.17:50:52.57#ibcon#read 6, iclass 17, count 0 2006.173.17:50:52.57#ibcon#end of sib2, iclass 17, count 0 2006.173.17:50:52.57#ibcon#*after write, iclass 17, count 0 2006.173.17:50:52.57#ibcon#*before return 0, iclass 17, count 0 2006.173.17:50:52.57#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.17:50:52.57#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.17:50:52.57#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.17:50:52.57#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.17:50:52.57$vck44/va=8,4 2006.173.17:50:52.57#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.17:50:52.57#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.17:50:52.57#ibcon#ireg 11 cls_cnt 2 2006.173.17:50:52.57#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.17:50:52.63#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.17:50:52.63#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.17:50:52.63#ibcon#enter wrdev, iclass 19, count 2 2006.173.17:50:52.63#ibcon#first serial, iclass 19, count 2 2006.173.17:50:52.63#ibcon#enter sib2, iclass 19, count 2 2006.173.17:50:52.63#ibcon#flushed, iclass 19, count 2 2006.173.17:50:52.63#ibcon#about to write, iclass 19, count 2 2006.173.17:50:52.63#ibcon#wrote, iclass 19, count 2 2006.173.17:50:52.63#ibcon#about to read 3, iclass 19, count 2 2006.173.17:50:52.65#ibcon#read 3, iclass 19, count 2 2006.173.17:50:52.65#ibcon#about to read 4, iclass 19, count 2 2006.173.17:50:52.65#ibcon#read 4, iclass 19, count 2 2006.173.17:50:52.65#ibcon#about to read 5, iclass 19, count 2 2006.173.17:50:52.65#ibcon#read 5, iclass 19, count 2 2006.173.17:50:52.65#ibcon#about to read 6, iclass 19, count 2 2006.173.17:50:52.65#ibcon#read 6, iclass 19, count 2 2006.173.17:50:52.65#ibcon#end of sib2, iclass 19, count 2 2006.173.17:50:52.65#ibcon#*mode == 0, iclass 19, count 2 2006.173.17:50:52.65#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.17:50:52.65#ibcon#[25=AT08-04\r\n] 2006.173.17:50:52.65#ibcon#*before write, iclass 19, count 2 2006.173.17:50:52.65#ibcon#enter sib2, iclass 19, count 2 2006.173.17:50:52.65#ibcon#flushed, iclass 19, count 2 2006.173.17:50:52.65#ibcon#about to write, iclass 19, count 2 2006.173.17:50:52.65#ibcon#wrote, iclass 19, count 2 2006.173.17:50:52.65#ibcon#about to read 3, iclass 19, count 2 2006.173.17:50:52.68#ibcon#read 3, iclass 19, count 2 2006.173.17:50:52.68#ibcon#about to read 4, iclass 19, count 2 2006.173.17:50:52.68#ibcon#read 4, iclass 19, count 2 2006.173.17:50:52.68#ibcon#about to read 5, iclass 19, count 2 2006.173.17:50:52.68#ibcon#read 5, iclass 19, count 2 2006.173.17:50:52.68#ibcon#about to read 6, iclass 19, count 2 2006.173.17:50:52.68#ibcon#read 6, iclass 19, count 2 2006.173.17:50:52.68#ibcon#end of sib2, iclass 19, count 2 2006.173.17:50:52.68#ibcon#*after write, iclass 19, count 2 2006.173.17:50:52.68#ibcon#*before return 0, iclass 19, count 2 2006.173.17:50:52.68#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.17:50:52.68#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.17:50:52.68#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.17:50:52.68#ibcon#ireg 7 cls_cnt 0 2006.173.17:50:52.68#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.17:50:52.80#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.17:50:52.80#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.17:50:52.80#ibcon#enter wrdev, iclass 19, count 0 2006.173.17:50:52.80#ibcon#first serial, iclass 19, count 0 2006.173.17:50:52.80#ibcon#enter sib2, iclass 19, count 0 2006.173.17:50:52.80#ibcon#flushed, iclass 19, count 0 2006.173.17:50:52.80#ibcon#about to write, iclass 19, count 0 2006.173.17:50:52.80#ibcon#wrote, iclass 19, count 0 2006.173.17:50:52.80#ibcon#about to read 3, iclass 19, count 0 2006.173.17:50:52.82#ibcon#read 3, iclass 19, count 0 2006.173.17:50:52.82#ibcon#about to read 4, iclass 19, count 0 2006.173.17:50:52.82#ibcon#read 4, iclass 19, count 0 2006.173.17:50:52.82#ibcon#about to read 5, iclass 19, count 0 2006.173.17:50:52.82#ibcon#read 5, iclass 19, count 0 2006.173.17:50:52.82#ibcon#about to read 6, iclass 19, count 0 2006.173.17:50:52.82#ibcon#read 6, iclass 19, count 0 2006.173.17:50:52.82#ibcon#end of sib2, iclass 19, count 0 2006.173.17:50:52.82#ibcon#*mode == 0, iclass 19, count 0 2006.173.17:50:52.82#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.17:50:52.82#ibcon#[25=USB\r\n] 2006.173.17:50:52.82#ibcon#*before write, iclass 19, count 0 2006.173.17:50:52.82#ibcon#enter sib2, iclass 19, count 0 2006.173.17:50:52.82#ibcon#flushed, iclass 19, count 0 2006.173.17:50:52.82#ibcon#about to write, iclass 19, count 0 2006.173.17:50:52.82#ibcon#wrote, iclass 19, count 0 2006.173.17:50:52.82#ibcon#about to read 3, iclass 19, count 0 2006.173.17:50:52.85#ibcon#read 3, iclass 19, count 0 2006.173.17:50:52.85#ibcon#about to read 4, iclass 19, count 0 2006.173.17:50:52.85#ibcon#read 4, iclass 19, count 0 2006.173.17:50:52.85#ibcon#about to read 5, iclass 19, count 0 2006.173.17:50:52.85#ibcon#read 5, iclass 19, count 0 2006.173.17:50:52.85#ibcon#about to read 6, iclass 19, count 0 2006.173.17:50:52.85#ibcon#read 6, iclass 19, count 0 2006.173.17:50:52.85#ibcon#end of sib2, iclass 19, count 0 2006.173.17:50:52.85#ibcon#*after write, iclass 19, count 0 2006.173.17:50:52.85#ibcon#*before return 0, iclass 19, count 0 2006.173.17:50:52.85#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.17:50:52.85#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.17:50:52.85#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.17:50:52.85#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.17:50:52.85$vck44/vblo=1,629.99 2006.173.17:50:52.85#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.17:50:52.85#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.17:50:52.85#ibcon#ireg 17 cls_cnt 0 2006.173.17:50:52.85#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.17:50:52.85#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.17:50:52.85#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.17:50:52.85#ibcon#enter wrdev, iclass 21, count 0 2006.173.17:50:52.85#ibcon#first serial, iclass 21, count 0 2006.173.17:50:52.85#ibcon#enter sib2, iclass 21, count 0 2006.173.17:50:52.85#ibcon#flushed, iclass 21, count 0 2006.173.17:50:52.85#ibcon#about to write, iclass 21, count 0 2006.173.17:50:52.85#ibcon#wrote, iclass 21, count 0 2006.173.17:50:52.85#ibcon#about to read 3, iclass 21, count 0 2006.173.17:50:52.87#ibcon#read 3, iclass 21, count 0 2006.173.17:50:52.87#ibcon#about to read 4, iclass 21, count 0 2006.173.17:50:52.87#ibcon#read 4, iclass 21, count 0 2006.173.17:50:52.87#ibcon#about to read 5, iclass 21, count 0 2006.173.17:50:52.87#ibcon#read 5, iclass 21, count 0 2006.173.17:50:52.87#ibcon#about to read 6, iclass 21, count 0 2006.173.17:50:52.87#ibcon#read 6, iclass 21, count 0 2006.173.17:50:52.87#ibcon#end of sib2, iclass 21, count 0 2006.173.17:50:52.87#ibcon#*mode == 0, iclass 21, count 0 2006.173.17:50:52.87#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.17:50:52.87#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.17:50:52.87#ibcon#*before write, iclass 21, count 0 2006.173.17:50:52.87#ibcon#enter sib2, iclass 21, count 0 2006.173.17:50:52.87#ibcon#flushed, iclass 21, count 0 2006.173.17:50:52.87#ibcon#about to write, iclass 21, count 0 2006.173.17:50:52.87#ibcon#wrote, iclass 21, count 0 2006.173.17:50:52.87#ibcon#about to read 3, iclass 21, count 0 2006.173.17:50:52.91#ibcon#read 3, iclass 21, count 0 2006.173.17:50:52.91#ibcon#about to read 4, iclass 21, count 0 2006.173.17:50:52.91#ibcon#read 4, iclass 21, count 0 2006.173.17:50:52.91#ibcon#about to read 5, iclass 21, count 0 2006.173.17:50:52.91#ibcon#read 5, iclass 21, count 0 2006.173.17:50:52.91#ibcon#about to read 6, iclass 21, count 0 2006.173.17:50:52.91#ibcon#read 6, iclass 21, count 0 2006.173.17:50:52.91#ibcon#end of sib2, iclass 21, count 0 2006.173.17:50:52.91#ibcon#*after write, iclass 21, count 0 2006.173.17:50:52.91#ibcon#*before return 0, iclass 21, count 0 2006.173.17:50:52.91#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.17:50:52.91#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.17:50:52.91#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.17:50:52.91#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.17:50:52.91$vck44/vb=1,4 2006.173.17:50:52.91#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.17:50:52.91#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.17:50:52.91#ibcon#ireg 11 cls_cnt 2 2006.173.17:50:52.91#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.17:50:52.91#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.17:50:52.91#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.17:50:52.91#ibcon#enter wrdev, iclass 23, count 2 2006.173.17:50:52.91#ibcon#first serial, iclass 23, count 2 2006.173.17:50:52.91#ibcon#enter sib2, iclass 23, count 2 2006.173.17:50:52.91#ibcon#flushed, iclass 23, count 2 2006.173.17:50:52.91#ibcon#about to write, iclass 23, count 2 2006.173.17:50:52.91#ibcon#wrote, iclass 23, count 2 2006.173.17:50:52.91#ibcon#about to read 3, iclass 23, count 2 2006.173.17:50:52.93#ibcon#read 3, iclass 23, count 2 2006.173.17:50:52.93#ibcon#about to read 4, iclass 23, count 2 2006.173.17:50:52.93#ibcon#read 4, iclass 23, count 2 2006.173.17:50:52.93#ibcon#about to read 5, iclass 23, count 2 2006.173.17:50:52.93#ibcon#read 5, iclass 23, count 2 2006.173.17:50:52.93#ibcon#about to read 6, iclass 23, count 2 2006.173.17:50:52.93#ibcon#read 6, iclass 23, count 2 2006.173.17:50:52.93#ibcon#end of sib2, iclass 23, count 2 2006.173.17:50:52.93#ibcon#*mode == 0, iclass 23, count 2 2006.173.17:50:52.93#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.17:50:52.93#ibcon#[27=AT01-04\r\n] 2006.173.17:50:52.93#ibcon#*before write, iclass 23, count 2 2006.173.17:50:52.93#ibcon#enter sib2, iclass 23, count 2 2006.173.17:50:52.93#ibcon#flushed, iclass 23, count 2 2006.173.17:50:52.93#ibcon#about to write, iclass 23, count 2 2006.173.17:50:52.93#ibcon#wrote, iclass 23, count 2 2006.173.17:50:52.93#ibcon#about to read 3, iclass 23, count 2 2006.173.17:50:52.96#ibcon#read 3, iclass 23, count 2 2006.173.17:50:52.96#ibcon#about to read 4, iclass 23, count 2 2006.173.17:50:52.96#ibcon#read 4, iclass 23, count 2 2006.173.17:50:52.96#ibcon#about to read 5, iclass 23, count 2 2006.173.17:50:52.96#ibcon#read 5, iclass 23, count 2 2006.173.17:50:52.96#ibcon#about to read 6, iclass 23, count 2 2006.173.17:50:52.96#ibcon#read 6, iclass 23, count 2 2006.173.17:50:52.96#ibcon#end of sib2, iclass 23, count 2 2006.173.17:50:52.96#ibcon#*after write, iclass 23, count 2 2006.173.17:50:52.96#ibcon#*before return 0, iclass 23, count 2 2006.173.17:50:52.96#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.17:50:52.96#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.17:50:52.96#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.17:50:52.96#ibcon#ireg 7 cls_cnt 0 2006.173.17:50:52.96#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.17:50:53.08#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.17:50:53.08#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.17:50:53.08#ibcon#enter wrdev, iclass 23, count 0 2006.173.17:50:53.08#ibcon#first serial, iclass 23, count 0 2006.173.17:50:53.08#ibcon#enter sib2, iclass 23, count 0 2006.173.17:50:53.08#ibcon#flushed, iclass 23, count 0 2006.173.17:50:53.08#ibcon#about to write, iclass 23, count 0 2006.173.17:50:53.08#ibcon#wrote, iclass 23, count 0 2006.173.17:50:53.08#ibcon#about to read 3, iclass 23, count 0 2006.173.17:50:53.10#ibcon#read 3, iclass 23, count 0 2006.173.17:50:53.10#ibcon#about to read 4, iclass 23, count 0 2006.173.17:50:53.10#ibcon#read 4, iclass 23, count 0 2006.173.17:50:53.10#ibcon#about to read 5, iclass 23, count 0 2006.173.17:50:53.10#ibcon#read 5, iclass 23, count 0 2006.173.17:50:53.10#ibcon#about to read 6, iclass 23, count 0 2006.173.17:50:53.10#ibcon#read 6, iclass 23, count 0 2006.173.17:50:53.10#ibcon#end of sib2, iclass 23, count 0 2006.173.17:50:53.10#ibcon#*mode == 0, iclass 23, count 0 2006.173.17:50:53.10#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.17:50:53.10#ibcon#[27=USB\r\n] 2006.173.17:50:53.10#ibcon#*before write, iclass 23, count 0 2006.173.17:50:53.10#ibcon#enter sib2, iclass 23, count 0 2006.173.17:50:53.10#ibcon#flushed, iclass 23, count 0 2006.173.17:50:53.10#ibcon#about to write, iclass 23, count 0 2006.173.17:50:53.10#ibcon#wrote, iclass 23, count 0 2006.173.17:50:53.10#ibcon#about to read 3, iclass 23, count 0 2006.173.17:50:53.13#ibcon#read 3, iclass 23, count 0 2006.173.17:50:53.13#ibcon#about to read 4, iclass 23, count 0 2006.173.17:50:53.13#ibcon#read 4, iclass 23, count 0 2006.173.17:50:53.13#ibcon#about to read 5, iclass 23, count 0 2006.173.17:50:53.13#ibcon#read 5, iclass 23, count 0 2006.173.17:50:53.13#ibcon#about to read 6, iclass 23, count 0 2006.173.17:50:53.13#ibcon#read 6, iclass 23, count 0 2006.173.17:50:53.13#ibcon#end of sib2, iclass 23, count 0 2006.173.17:50:53.13#ibcon#*after write, iclass 23, count 0 2006.173.17:50:53.13#ibcon#*before return 0, iclass 23, count 0 2006.173.17:50:53.13#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.17:50:53.13#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.17:50:53.13#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.17:50:53.13#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.17:50:53.13$vck44/vblo=2,634.99 2006.173.17:50:53.13#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.17:50:53.13#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.17:50:53.13#ibcon#ireg 17 cls_cnt 0 2006.173.17:50:53.13#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.17:50:53.13#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.17:50:53.13#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.17:50:53.13#ibcon#enter wrdev, iclass 25, count 0 2006.173.17:50:53.13#ibcon#first serial, iclass 25, count 0 2006.173.17:50:53.13#ibcon#enter sib2, iclass 25, count 0 2006.173.17:50:53.13#ibcon#flushed, iclass 25, count 0 2006.173.17:50:53.13#ibcon#about to write, iclass 25, count 0 2006.173.17:50:53.13#ibcon#wrote, iclass 25, count 0 2006.173.17:50:53.13#ibcon#about to read 3, iclass 25, count 0 2006.173.17:50:53.15#ibcon#read 3, iclass 25, count 0 2006.173.17:50:53.15#ibcon#about to read 4, iclass 25, count 0 2006.173.17:50:53.15#ibcon#read 4, iclass 25, count 0 2006.173.17:50:53.15#ibcon#about to read 5, iclass 25, count 0 2006.173.17:50:53.15#ibcon#read 5, iclass 25, count 0 2006.173.17:50:53.15#ibcon#about to read 6, iclass 25, count 0 2006.173.17:50:53.15#ibcon#read 6, iclass 25, count 0 2006.173.17:50:53.15#ibcon#end of sib2, iclass 25, count 0 2006.173.17:50:53.15#ibcon#*mode == 0, iclass 25, count 0 2006.173.17:50:53.15#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.17:50:53.15#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.17:50:53.15#ibcon#*before write, iclass 25, count 0 2006.173.17:50:53.15#ibcon#enter sib2, iclass 25, count 0 2006.173.17:50:53.15#ibcon#flushed, iclass 25, count 0 2006.173.17:50:53.15#ibcon#about to write, iclass 25, count 0 2006.173.17:50:53.15#ibcon#wrote, iclass 25, count 0 2006.173.17:50:53.15#ibcon#about to read 3, iclass 25, count 0 2006.173.17:50:53.19#ibcon#read 3, iclass 25, count 0 2006.173.17:50:53.19#ibcon#about to read 4, iclass 25, count 0 2006.173.17:50:53.19#ibcon#read 4, iclass 25, count 0 2006.173.17:50:53.19#ibcon#about to read 5, iclass 25, count 0 2006.173.17:50:53.19#ibcon#read 5, iclass 25, count 0 2006.173.17:50:53.19#ibcon#about to read 6, iclass 25, count 0 2006.173.17:50:53.19#ibcon#read 6, iclass 25, count 0 2006.173.17:50:53.19#ibcon#end of sib2, iclass 25, count 0 2006.173.17:50:53.19#ibcon#*after write, iclass 25, count 0 2006.173.17:50:53.19#ibcon#*before return 0, iclass 25, count 0 2006.173.17:50:53.19#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.17:50:53.19#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.17:50:53.19#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.17:50:53.19#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.17:50:53.19$vck44/vb=2,4 2006.173.17:50:53.19#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.17:50:53.19#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.17:50:53.19#ibcon#ireg 11 cls_cnt 2 2006.173.17:50:53.19#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.17:50:53.25#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.17:50:53.25#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.17:50:53.25#ibcon#enter wrdev, iclass 27, count 2 2006.173.17:50:53.25#ibcon#first serial, iclass 27, count 2 2006.173.17:50:53.25#ibcon#enter sib2, iclass 27, count 2 2006.173.17:50:53.25#ibcon#flushed, iclass 27, count 2 2006.173.17:50:53.25#ibcon#about to write, iclass 27, count 2 2006.173.17:50:53.25#ibcon#wrote, iclass 27, count 2 2006.173.17:50:53.25#ibcon#about to read 3, iclass 27, count 2 2006.173.17:50:53.27#ibcon#read 3, iclass 27, count 2 2006.173.17:50:53.27#ibcon#about to read 4, iclass 27, count 2 2006.173.17:50:53.27#ibcon#read 4, iclass 27, count 2 2006.173.17:50:53.27#ibcon#about to read 5, iclass 27, count 2 2006.173.17:50:53.27#ibcon#read 5, iclass 27, count 2 2006.173.17:50:53.27#ibcon#about to read 6, iclass 27, count 2 2006.173.17:50:53.27#ibcon#read 6, iclass 27, count 2 2006.173.17:50:53.27#ibcon#end of sib2, iclass 27, count 2 2006.173.17:50:53.27#ibcon#*mode == 0, iclass 27, count 2 2006.173.17:50:53.27#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.17:50:53.27#ibcon#[27=AT02-04\r\n] 2006.173.17:50:53.27#ibcon#*before write, iclass 27, count 2 2006.173.17:50:53.27#ibcon#enter sib2, iclass 27, count 2 2006.173.17:50:53.27#ibcon#flushed, iclass 27, count 2 2006.173.17:50:53.27#ibcon#about to write, iclass 27, count 2 2006.173.17:50:53.27#ibcon#wrote, iclass 27, count 2 2006.173.17:50:53.27#ibcon#about to read 3, iclass 27, count 2 2006.173.17:50:53.30#ibcon#read 3, iclass 27, count 2 2006.173.17:50:53.30#ibcon#about to read 4, iclass 27, count 2 2006.173.17:50:53.30#ibcon#read 4, iclass 27, count 2 2006.173.17:50:53.30#ibcon#about to read 5, iclass 27, count 2 2006.173.17:50:53.30#ibcon#read 5, iclass 27, count 2 2006.173.17:50:53.30#ibcon#about to read 6, iclass 27, count 2 2006.173.17:50:53.30#ibcon#read 6, iclass 27, count 2 2006.173.17:50:53.30#ibcon#end of sib2, iclass 27, count 2 2006.173.17:50:53.30#ibcon#*after write, iclass 27, count 2 2006.173.17:50:53.30#ibcon#*before return 0, iclass 27, count 2 2006.173.17:50:53.30#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.17:50:53.30#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.17:50:53.30#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.17:50:53.30#ibcon#ireg 7 cls_cnt 0 2006.173.17:50:53.30#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.17:50:53.42#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.17:50:53.42#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.17:50:53.42#ibcon#enter wrdev, iclass 27, count 0 2006.173.17:50:53.42#ibcon#first serial, iclass 27, count 0 2006.173.17:50:53.42#ibcon#enter sib2, iclass 27, count 0 2006.173.17:50:53.42#ibcon#flushed, iclass 27, count 0 2006.173.17:50:53.42#ibcon#about to write, iclass 27, count 0 2006.173.17:50:53.42#ibcon#wrote, iclass 27, count 0 2006.173.17:50:53.42#ibcon#about to read 3, iclass 27, count 0 2006.173.17:50:53.44#ibcon#read 3, iclass 27, count 0 2006.173.17:50:53.44#ibcon#about to read 4, iclass 27, count 0 2006.173.17:50:53.44#ibcon#read 4, iclass 27, count 0 2006.173.17:50:53.44#ibcon#about to read 5, iclass 27, count 0 2006.173.17:50:53.44#ibcon#read 5, iclass 27, count 0 2006.173.17:50:53.44#ibcon#about to read 6, iclass 27, count 0 2006.173.17:50:53.44#ibcon#read 6, iclass 27, count 0 2006.173.17:50:53.44#ibcon#end of sib2, iclass 27, count 0 2006.173.17:50:53.44#ibcon#*mode == 0, iclass 27, count 0 2006.173.17:50:53.44#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.17:50:53.44#ibcon#[27=USB\r\n] 2006.173.17:50:53.44#ibcon#*before write, iclass 27, count 0 2006.173.17:50:53.44#ibcon#enter sib2, iclass 27, count 0 2006.173.17:50:53.44#ibcon#flushed, iclass 27, count 0 2006.173.17:50:53.44#ibcon#about to write, iclass 27, count 0 2006.173.17:50:53.44#ibcon#wrote, iclass 27, count 0 2006.173.17:50:53.44#ibcon#about to read 3, iclass 27, count 0 2006.173.17:50:53.47#ibcon#read 3, iclass 27, count 0 2006.173.17:50:53.47#ibcon#about to read 4, iclass 27, count 0 2006.173.17:50:53.47#ibcon#read 4, iclass 27, count 0 2006.173.17:50:53.47#ibcon#about to read 5, iclass 27, count 0 2006.173.17:50:53.47#ibcon#read 5, iclass 27, count 0 2006.173.17:50:53.47#ibcon#about to read 6, iclass 27, count 0 2006.173.17:50:53.47#ibcon#read 6, iclass 27, count 0 2006.173.17:50:53.47#ibcon#end of sib2, iclass 27, count 0 2006.173.17:50:53.47#ibcon#*after write, iclass 27, count 0 2006.173.17:50:53.47#ibcon#*before return 0, iclass 27, count 0 2006.173.17:50:53.47#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.17:50:53.47#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.17:50:53.47#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.17:50:53.47#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.17:50:53.47$vck44/vblo=3,649.99 2006.173.17:50:53.47#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.17:50:53.47#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.17:50:53.47#ibcon#ireg 17 cls_cnt 0 2006.173.17:50:53.47#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.17:50:53.47#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.17:50:53.47#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.17:50:53.47#ibcon#enter wrdev, iclass 29, count 0 2006.173.17:50:53.47#ibcon#first serial, iclass 29, count 0 2006.173.17:50:53.47#ibcon#enter sib2, iclass 29, count 0 2006.173.17:50:53.47#ibcon#flushed, iclass 29, count 0 2006.173.17:50:53.47#ibcon#about to write, iclass 29, count 0 2006.173.17:50:53.47#ibcon#wrote, iclass 29, count 0 2006.173.17:50:53.47#ibcon#about to read 3, iclass 29, count 0 2006.173.17:50:53.49#ibcon#read 3, iclass 29, count 0 2006.173.17:50:53.49#ibcon#about to read 4, iclass 29, count 0 2006.173.17:50:53.49#ibcon#read 4, iclass 29, count 0 2006.173.17:50:53.49#ibcon#about to read 5, iclass 29, count 0 2006.173.17:50:53.49#ibcon#read 5, iclass 29, count 0 2006.173.17:50:53.49#ibcon#about to read 6, iclass 29, count 0 2006.173.17:50:53.49#ibcon#read 6, iclass 29, count 0 2006.173.17:50:53.49#ibcon#end of sib2, iclass 29, count 0 2006.173.17:50:53.49#ibcon#*mode == 0, iclass 29, count 0 2006.173.17:50:53.49#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.17:50:53.49#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.17:50:53.49#ibcon#*before write, iclass 29, count 0 2006.173.17:50:53.49#ibcon#enter sib2, iclass 29, count 0 2006.173.17:50:53.49#ibcon#flushed, iclass 29, count 0 2006.173.17:50:53.49#ibcon#about to write, iclass 29, count 0 2006.173.17:50:53.49#ibcon#wrote, iclass 29, count 0 2006.173.17:50:53.49#ibcon#about to read 3, iclass 29, count 0 2006.173.17:50:53.53#ibcon#read 3, iclass 29, count 0 2006.173.17:50:53.53#ibcon#about to read 4, iclass 29, count 0 2006.173.17:50:53.53#ibcon#read 4, iclass 29, count 0 2006.173.17:50:53.53#ibcon#about to read 5, iclass 29, count 0 2006.173.17:50:53.53#ibcon#read 5, iclass 29, count 0 2006.173.17:50:53.53#ibcon#about to read 6, iclass 29, count 0 2006.173.17:50:53.53#ibcon#read 6, iclass 29, count 0 2006.173.17:50:53.53#ibcon#end of sib2, iclass 29, count 0 2006.173.17:50:53.53#ibcon#*after write, iclass 29, count 0 2006.173.17:50:53.53#ibcon#*before return 0, iclass 29, count 0 2006.173.17:50:53.53#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.17:50:53.53#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.17:50:53.53#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.17:50:53.53#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.17:50:53.53$vck44/vb=3,4 2006.173.17:50:53.53#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.17:50:53.53#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.17:50:53.53#ibcon#ireg 11 cls_cnt 2 2006.173.17:50:53.53#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.17:50:53.59#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.17:50:53.59#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.17:50:53.59#ibcon#enter wrdev, iclass 31, count 2 2006.173.17:50:53.59#ibcon#first serial, iclass 31, count 2 2006.173.17:50:53.59#ibcon#enter sib2, iclass 31, count 2 2006.173.17:50:53.59#ibcon#flushed, iclass 31, count 2 2006.173.17:50:53.59#ibcon#about to write, iclass 31, count 2 2006.173.17:50:53.59#ibcon#wrote, iclass 31, count 2 2006.173.17:50:53.59#ibcon#about to read 3, iclass 31, count 2 2006.173.17:50:53.61#ibcon#read 3, iclass 31, count 2 2006.173.17:50:53.61#ibcon#about to read 4, iclass 31, count 2 2006.173.17:50:53.61#ibcon#read 4, iclass 31, count 2 2006.173.17:50:53.61#ibcon#about to read 5, iclass 31, count 2 2006.173.17:50:53.61#ibcon#read 5, iclass 31, count 2 2006.173.17:50:53.61#ibcon#about to read 6, iclass 31, count 2 2006.173.17:50:53.61#ibcon#read 6, iclass 31, count 2 2006.173.17:50:53.61#ibcon#end of sib2, iclass 31, count 2 2006.173.17:50:53.61#ibcon#*mode == 0, iclass 31, count 2 2006.173.17:50:53.61#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.17:50:53.61#ibcon#[27=AT03-04\r\n] 2006.173.17:50:53.61#ibcon#*before write, iclass 31, count 2 2006.173.17:50:53.61#ibcon#enter sib2, iclass 31, count 2 2006.173.17:50:53.61#ibcon#flushed, iclass 31, count 2 2006.173.17:50:53.61#ibcon#about to write, iclass 31, count 2 2006.173.17:50:53.61#ibcon#wrote, iclass 31, count 2 2006.173.17:50:53.61#ibcon#about to read 3, iclass 31, count 2 2006.173.17:50:53.64#ibcon#read 3, iclass 31, count 2 2006.173.17:50:53.64#ibcon#about to read 4, iclass 31, count 2 2006.173.17:50:53.64#ibcon#read 4, iclass 31, count 2 2006.173.17:50:53.64#ibcon#about to read 5, iclass 31, count 2 2006.173.17:50:53.64#ibcon#read 5, iclass 31, count 2 2006.173.17:50:53.64#ibcon#about to read 6, iclass 31, count 2 2006.173.17:50:53.64#ibcon#read 6, iclass 31, count 2 2006.173.17:50:53.64#ibcon#end of sib2, iclass 31, count 2 2006.173.17:50:53.64#ibcon#*after write, iclass 31, count 2 2006.173.17:50:53.64#ibcon#*before return 0, iclass 31, count 2 2006.173.17:50:53.64#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.17:50:53.64#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.17:50:53.64#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.17:50:53.64#ibcon#ireg 7 cls_cnt 0 2006.173.17:50:53.64#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.17:50:53.76#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.17:50:53.76#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.17:50:53.76#ibcon#enter wrdev, iclass 31, count 0 2006.173.17:50:53.76#ibcon#first serial, iclass 31, count 0 2006.173.17:50:53.76#ibcon#enter sib2, iclass 31, count 0 2006.173.17:50:53.76#ibcon#flushed, iclass 31, count 0 2006.173.17:50:53.76#ibcon#about to write, iclass 31, count 0 2006.173.17:50:53.76#ibcon#wrote, iclass 31, count 0 2006.173.17:50:53.76#ibcon#about to read 3, iclass 31, count 0 2006.173.17:50:53.78#ibcon#read 3, iclass 31, count 0 2006.173.17:50:53.78#ibcon#about to read 4, iclass 31, count 0 2006.173.17:50:53.78#ibcon#read 4, iclass 31, count 0 2006.173.17:50:53.78#ibcon#about to read 5, iclass 31, count 0 2006.173.17:50:53.78#ibcon#read 5, iclass 31, count 0 2006.173.17:50:53.78#ibcon#about to read 6, iclass 31, count 0 2006.173.17:50:53.78#ibcon#read 6, iclass 31, count 0 2006.173.17:50:53.78#ibcon#end of sib2, iclass 31, count 0 2006.173.17:50:53.78#ibcon#*mode == 0, iclass 31, count 0 2006.173.17:50:53.78#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.17:50:53.78#ibcon#[27=USB\r\n] 2006.173.17:50:53.78#ibcon#*before write, iclass 31, count 0 2006.173.17:50:53.78#ibcon#enter sib2, iclass 31, count 0 2006.173.17:50:53.78#ibcon#flushed, iclass 31, count 0 2006.173.17:50:53.78#ibcon#about to write, iclass 31, count 0 2006.173.17:50:53.78#ibcon#wrote, iclass 31, count 0 2006.173.17:50:53.78#ibcon#about to read 3, iclass 31, count 0 2006.173.17:50:53.81#ibcon#read 3, iclass 31, count 0 2006.173.17:50:53.81#ibcon#about to read 4, iclass 31, count 0 2006.173.17:50:53.81#ibcon#read 4, iclass 31, count 0 2006.173.17:50:53.81#ibcon#about to read 5, iclass 31, count 0 2006.173.17:50:53.81#ibcon#read 5, iclass 31, count 0 2006.173.17:50:53.81#ibcon#about to read 6, iclass 31, count 0 2006.173.17:50:53.81#ibcon#read 6, iclass 31, count 0 2006.173.17:50:53.81#ibcon#end of sib2, iclass 31, count 0 2006.173.17:50:53.81#ibcon#*after write, iclass 31, count 0 2006.173.17:50:53.81#ibcon#*before return 0, iclass 31, count 0 2006.173.17:50:53.81#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.17:50:53.81#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.17:50:53.81#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.17:50:53.81#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.17:50:53.81$vck44/vblo=4,679.99 2006.173.17:50:53.81#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.17:50:53.81#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.17:50:53.81#ibcon#ireg 17 cls_cnt 0 2006.173.17:50:53.81#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.17:50:53.81#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.17:50:53.81#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.17:50:53.81#ibcon#enter wrdev, iclass 33, count 0 2006.173.17:50:53.81#ibcon#first serial, iclass 33, count 0 2006.173.17:50:53.81#ibcon#enter sib2, iclass 33, count 0 2006.173.17:50:53.81#ibcon#flushed, iclass 33, count 0 2006.173.17:50:53.81#ibcon#about to write, iclass 33, count 0 2006.173.17:50:53.81#ibcon#wrote, iclass 33, count 0 2006.173.17:50:53.81#ibcon#about to read 3, iclass 33, count 0 2006.173.17:50:53.83#ibcon#read 3, iclass 33, count 0 2006.173.17:50:53.83#ibcon#about to read 4, iclass 33, count 0 2006.173.17:50:53.83#ibcon#read 4, iclass 33, count 0 2006.173.17:50:53.83#ibcon#about to read 5, iclass 33, count 0 2006.173.17:50:53.83#ibcon#read 5, iclass 33, count 0 2006.173.17:50:53.83#ibcon#about to read 6, iclass 33, count 0 2006.173.17:50:53.83#ibcon#read 6, iclass 33, count 0 2006.173.17:50:53.83#ibcon#end of sib2, iclass 33, count 0 2006.173.17:50:53.83#ibcon#*mode == 0, iclass 33, count 0 2006.173.17:50:53.83#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.17:50:53.83#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.17:50:53.83#ibcon#*before write, iclass 33, count 0 2006.173.17:50:53.83#ibcon#enter sib2, iclass 33, count 0 2006.173.17:50:53.83#ibcon#flushed, iclass 33, count 0 2006.173.17:50:53.83#ibcon#about to write, iclass 33, count 0 2006.173.17:50:53.83#ibcon#wrote, iclass 33, count 0 2006.173.17:50:53.83#ibcon#about to read 3, iclass 33, count 0 2006.173.17:50:53.87#ibcon#read 3, iclass 33, count 0 2006.173.17:50:53.87#ibcon#about to read 4, iclass 33, count 0 2006.173.17:50:53.87#ibcon#read 4, iclass 33, count 0 2006.173.17:50:53.87#ibcon#about to read 5, iclass 33, count 0 2006.173.17:50:53.87#ibcon#read 5, iclass 33, count 0 2006.173.17:50:53.87#ibcon#about to read 6, iclass 33, count 0 2006.173.17:50:53.87#ibcon#read 6, iclass 33, count 0 2006.173.17:50:53.87#ibcon#end of sib2, iclass 33, count 0 2006.173.17:50:53.87#ibcon#*after write, iclass 33, count 0 2006.173.17:50:53.87#ibcon#*before return 0, iclass 33, count 0 2006.173.17:50:53.87#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.17:50:53.87#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.17:50:53.87#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.17:50:53.87#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.17:50:53.87$vck44/vb=4,4 2006.173.17:50:53.87#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.17:50:53.87#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.17:50:53.87#ibcon#ireg 11 cls_cnt 2 2006.173.17:50:53.87#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.17:50:53.93#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.17:50:53.93#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.17:50:53.93#ibcon#enter wrdev, iclass 35, count 2 2006.173.17:50:53.93#ibcon#first serial, iclass 35, count 2 2006.173.17:50:53.93#ibcon#enter sib2, iclass 35, count 2 2006.173.17:50:53.93#ibcon#flushed, iclass 35, count 2 2006.173.17:50:53.93#ibcon#about to write, iclass 35, count 2 2006.173.17:50:53.93#ibcon#wrote, iclass 35, count 2 2006.173.17:50:53.93#ibcon#about to read 3, iclass 35, count 2 2006.173.17:50:53.95#ibcon#read 3, iclass 35, count 2 2006.173.17:50:53.95#ibcon#about to read 4, iclass 35, count 2 2006.173.17:50:53.95#ibcon#read 4, iclass 35, count 2 2006.173.17:50:53.95#ibcon#about to read 5, iclass 35, count 2 2006.173.17:50:53.95#ibcon#read 5, iclass 35, count 2 2006.173.17:50:53.95#ibcon#about to read 6, iclass 35, count 2 2006.173.17:50:53.95#ibcon#read 6, iclass 35, count 2 2006.173.17:50:53.95#ibcon#end of sib2, iclass 35, count 2 2006.173.17:50:53.95#ibcon#*mode == 0, iclass 35, count 2 2006.173.17:50:53.95#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.17:50:53.95#ibcon#[27=AT04-04\r\n] 2006.173.17:50:53.95#ibcon#*before write, iclass 35, count 2 2006.173.17:50:53.95#ibcon#enter sib2, iclass 35, count 2 2006.173.17:50:53.95#ibcon#flushed, iclass 35, count 2 2006.173.17:50:53.95#ibcon#about to write, iclass 35, count 2 2006.173.17:50:53.95#ibcon#wrote, iclass 35, count 2 2006.173.17:50:53.95#ibcon#about to read 3, iclass 35, count 2 2006.173.17:50:53.98#ibcon#read 3, iclass 35, count 2 2006.173.17:50:53.98#ibcon#about to read 4, iclass 35, count 2 2006.173.17:50:53.98#ibcon#read 4, iclass 35, count 2 2006.173.17:50:53.98#ibcon#about to read 5, iclass 35, count 2 2006.173.17:50:53.98#ibcon#read 5, iclass 35, count 2 2006.173.17:50:53.98#ibcon#about to read 6, iclass 35, count 2 2006.173.17:50:53.98#ibcon#read 6, iclass 35, count 2 2006.173.17:50:53.98#ibcon#end of sib2, iclass 35, count 2 2006.173.17:50:53.98#ibcon#*after write, iclass 35, count 2 2006.173.17:50:53.98#ibcon#*before return 0, iclass 35, count 2 2006.173.17:50:53.98#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.17:50:53.98#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.17:50:53.98#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.17:50:53.98#ibcon#ireg 7 cls_cnt 0 2006.173.17:50:53.98#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.17:50:54.10#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.17:50:54.10#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.17:50:54.10#ibcon#enter wrdev, iclass 35, count 0 2006.173.17:50:54.10#ibcon#first serial, iclass 35, count 0 2006.173.17:50:54.10#ibcon#enter sib2, iclass 35, count 0 2006.173.17:50:54.10#ibcon#flushed, iclass 35, count 0 2006.173.17:50:54.10#ibcon#about to write, iclass 35, count 0 2006.173.17:50:54.10#ibcon#wrote, iclass 35, count 0 2006.173.17:50:54.10#ibcon#about to read 3, iclass 35, count 0 2006.173.17:50:54.12#ibcon#read 3, iclass 35, count 0 2006.173.17:50:54.12#ibcon#about to read 4, iclass 35, count 0 2006.173.17:50:54.12#ibcon#read 4, iclass 35, count 0 2006.173.17:50:54.12#ibcon#about to read 5, iclass 35, count 0 2006.173.17:50:54.12#ibcon#read 5, iclass 35, count 0 2006.173.17:50:54.12#ibcon#about to read 6, iclass 35, count 0 2006.173.17:50:54.12#ibcon#read 6, iclass 35, count 0 2006.173.17:50:54.12#ibcon#end of sib2, iclass 35, count 0 2006.173.17:50:54.12#ibcon#*mode == 0, iclass 35, count 0 2006.173.17:50:54.12#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.17:50:54.12#ibcon#[27=USB\r\n] 2006.173.17:50:54.12#ibcon#*before write, iclass 35, count 0 2006.173.17:50:54.12#ibcon#enter sib2, iclass 35, count 0 2006.173.17:50:54.12#ibcon#flushed, iclass 35, count 0 2006.173.17:50:54.12#ibcon#about to write, iclass 35, count 0 2006.173.17:50:54.12#ibcon#wrote, iclass 35, count 0 2006.173.17:50:54.12#ibcon#about to read 3, iclass 35, count 0 2006.173.17:50:54.15#ibcon#read 3, iclass 35, count 0 2006.173.17:50:54.15#ibcon#about to read 4, iclass 35, count 0 2006.173.17:50:54.15#ibcon#read 4, iclass 35, count 0 2006.173.17:50:54.15#ibcon#about to read 5, iclass 35, count 0 2006.173.17:50:54.15#ibcon#read 5, iclass 35, count 0 2006.173.17:50:54.15#ibcon#about to read 6, iclass 35, count 0 2006.173.17:50:54.15#ibcon#read 6, iclass 35, count 0 2006.173.17:50:54.15#ibcon#end of sib2, iclass 35, count 0 2006.173.17:50:54.15#ibcon#*after write, iclass 35, count 0 2006.173.17:50:54.15#ibcon#*before return 0, iclass 35, count 0 2006.173.17:50:54.15#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.17:50:54.15#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.17:50:54.15#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.17:50:54.15#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.17:50:54.15$vck44/vblo=5,709.99 2006.173.17:50:54.15#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.17:50:54.15#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.17:50:54.15#ibcon#ireg 17 cls_cnt 0 2006.173.17:50:54.15#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.17:50:54.15#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.17:50:54.15#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.17:50:54.15#ibcon#enter wrdev, iclass 37, count 0 2006.173.17:50:54.15#ibcon#first serial, iclass 37, count 0 2006.173.17:50:54.15#ibcon#enter sib2, iclass 37, count 0 2006.173.17:50:54.15#ibcon#flushed, iclass 37, count 0 2006.173.17:50:54.15#ibcon#about to write, iclass 37, count 0 2006.173.17:50:54.15#ibcon#wrote, iclass 37, count 0 2006.173.17:50:54.15#ibcon#about to read 3, iclass 37, count 0 2006.173.17:50:54.17#ibcon#read 3, iclass 37, count 0 2006.173.17:50:54.17#ibcon#about to read 4, iclass 37, count 0 2006.173.17:50:54.17#ibcon#read 4, iclass 37, count 0 2006.173.17:50:54.17#ibcon#about to read 5, iclass 37, count 0 2006.173.17:50:54.17#ibcon#read 5, iclass 37, count 0 2006.173.17:50:54.17#ibcon#about to read 6, iclass 37, count 0 2006.173.17:50:54.17#ibcon#read 6, iclass 37, count 0 2006.173.17:50:54.17#ibcon#end of sib2, iclass 37, count 0 2006.173.17:50:54.17#ibcon#*mode == 0, iclass 37, count 0 2006.173.17:50:54.17#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.17:50:54.17#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.17:50:54.17#ibcon#*before write, iclass 37, count 0 2006.173.17:50:54.17#ibcon#enter sib2, iclass 37, count 0 2006.173.17:50:54.17#ibcon#flushed, iclass 37, count 0 2006.173.17:50:54.17#ibcon#about to write, iclass 37, count 0 2006.173.17:50:54.17#ibcon#wrote, iclass 37, count 0 2006.173.17:50:54.17#ibcon#about to read 3, iclass 37, count 0 2006.173.17:50:54.21#ibcon#read 3, iclass 37, count 0 2006.173.17:50:54.21#ibcon#about to read 4, iclass 37, count 0 2006.173.17:50:54.21#ibcon#read 4, iclass 37, count 0 2006.173.17:50:54.21#ibcon#about to read 5, iclass 37, count 0 2006.173.17:50:54.21#ibcon#read 5, iclass 37, count 0 2006.173.17:50:54.21#ibcon#about to read 6, iclass 37, count 0 2006.173.17:50:54.21#ibcon#read 6, iclass 37, count 0 2006.173.17:50:54.21#ibcon#end of sib2, iclass 37, count 0 2006.173.17:50:54.21#ibcon#*after write, iclass 37, count 0 2006.173.17:50:54.21#ibcon#*before return 0, iclass 37, count 0 2006.173.17:50:54.21#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.17:50:54.21#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.17:50:54.21#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.17:50:54.21#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.17:50:54.21$vck44/vb=5,4 2006.173.17:50:54.21#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.17:50:54.21#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.17:50:54.21#ibcon#ireg 11 cls_cnt 2 2006.173.17:50:54.21#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.17:50:54.27#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.17:50:54.27#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.17:50:54.27#ibcon#enter wrdev, iclass 39, count 2 2006.173.17:50:54.27#ibcon#first serial, iclass 39, count 2 2006.173.17:50:54.27#ibcon#enter sib2, iclass 39, count 2 2006.173.17:50:54.27#ibcon#flushed, iclass 39, count 2 2006.173.17:50:54.27#ibcon#about to write, iclass 39, count 2 2006.173.17:50:54.27#ibcon#wrote, iclass 39, count 2 2006.173.17:50:54.27#ibcon#about to read 3, iclass 39, count 2 2006.173.17:50:54.29#ibcon#read 3, iclass 39, count 2 2006.173.17:50:54.29#ibcon#about to read 4, iclass 39, count 2 2006.173.17:50:54.29#ibcon#read 4, iclass 39, count 2 2006.173.17:50:54.29#ibcon#about to read 5, iclass 39, count 2 2006.173.17:50:54.29#ibcon#read 5, iclass 39, count 2 2006.173.17:50:54.29#ibcon#about to read 6, iclass 39, count 2 2006.173.17:50:54.29#ibcon#read 6, iclass 39, count 2 2006.173.17:50:54.29#ibcon#end of sib2, iclass 39, count 2 2006.173.17:50:54.29#ibcon#*mode == 0, iclass 39, count 2 2006.173.17:50:54.29#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.17:50:54.29#ibcon#[27=AT05-04\r\n] 2006.173.17:50:54.29#ibcon#*before write, iclass 39, count 2 2006.173.17:50:54.29#ibcon#enter sib2, iclass 39, count 2 2006.173.17:50:54.29#ibcon#flushed, iclass 39, count 2 2006.173.17:50:54.29#ibcon#about to write, iclass 39, count 2 2006.173.17:50:54.29#ibcon#wrote, iclass 39, count 2 2006.173.17:50:54.29#ibcon#about to read 3, iclass 39, count 2 2006.173.17:50:54.32#ibcon#read 3, iclass 39, count 2 2006.173.17:50:54.32#ibcon#about to read 4, iclass 39, count 2 2006.173.17:50:54.32#ibcon#read 4, iclass 39, count 2 2006.173.17:50:54.32#ibcon#about to read 5, iclass 39, count 2 2006.173.17:50:54.32#ibcon#read 5, iclass 39, count 2 2006.173.17:50:54.32#ibcon#about to read 6, iclass 39, count 2 2006.173.17:50:54.32#ibcon#read 6, iclass 39, count 2 2006.173.17:50:54.32#ibcon#end of sib2, iclass 39, count 2 2006.173.17:50:54.32#ibcon#*after write, iclass 39, count 2 2006.173.17:50:54.32#ibcon#*before return 0, iclass 39, count 2 2006.173.17:50:54.32#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.17:50:54.32#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.17:50:54.32#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.17:50:54.32#ibcon#ireg 7 cls_cnt 0 2006.173.17:50:54.32#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.17:50:54.44#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.17:50:54.44#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.17:50:54.44#ibcon#enter wrdev, iclass 39, count 0 2006.173.17:50:54.44#ibcon#first serial, iclass 39, count 0 2006.173.17:50:54.44#ibcon#enter sib2, iclass 39, count 0 2006.173.17:50:54.44#ibcon#flushed, iclass 39, count 0 2006.173.17:50:54.44#ibcon#about to write, iclass 39, count 0 2006.173.17:50:54.44#ibcon#wrote, iclass 39, count 0 2006.173.17:50:54.44#ibcon#about to read 3, iclass 39, count 0 2006.173.17:50:54.46#ibcon#read 3, iclass 39, count 0 2006.173.17:50:54.46#ibcon#about to read 4, iclass 39, count 0 2006.173.17:50:54.46#ibcon#read 4, iclass 39, count 0 2006.173.17:50:54.46#ibcon#about to read 5, iclass 39, count 0 2006.173.17:50:54.46#ibcon#read 5, iclass 39, count 0 2006.173.17:50:54.46#ibcon#about to read 6, iclass 39, count 0 2006.173.17:50:54.46#ibcon#read 6, iclass 39, count 0 2006.173.17:50:54.46#ibcon#end of sib2, iclass 39, count 0 2006.173.17:50:54.46#ibcon#*mode == 0, iclass 39, count 0 2006.173.17:50:54.46#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.17:50:54.46#ibcon#[27=USB\r\n] 2006.173.17:50:54.46#ibcon#*before write, iclass 39, count 0 2006.173.17:50:54.46#ibcon#enter sib2, iclass 39, count 0 2006.173.17:50:54.46#ibcon#flushed, iclass 39, count 0 2006.173.17:50:54.46#ibcon#about to write, iclass 39, count 0 2006.173.17:50:54.46#ibcon#wrote, iclass 39, count 0 2006.173.17:50:54.46#ibcon#about to read 3, iclass 39, count 0 2006.173.17:50:54.49#ibcon#read 3, iclass 39, count 0 2006.173.17:50:54.49#ibcon#about to read 4, iclass 39, count 0 2006.173.17:50:54.49#ibcon#read 4, iclass 39, count 0 2006.173.17:50:54.49#ibcon#about to read 5, iclass 39, count 0 2006.173.17:50:54.49#ibcon#read 5, iclass 39, count 0 2006.173.17:50:54.49#ibcon#about to read 6, iclass 39, count 0 2006.173.17:50:54.49#ibcon#read 6, iclass 39, count 0 2006.173.17:50:54.49#ibcon#end of sib2, iclass 39, count 0 2006.173.17:50:54.49#ibcon#*after write, iclass 39, count 0 2006.173.17:50:54.49#ibcon#*before return 0, iclass 39, count 0 2006.173.17:50:54.49#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.17:50:54.49#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.17:50:54.49#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.17:50:54.49#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.17:50:54.49$vck44/vblo=6,719.99 2006.173.17:50:54.49#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.17:50:54.49#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.17:50:54.49#ibcon#ireg 17 cls_cnt 0 2006.173.17:50:54.49#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.17:50:54.49#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.17:50:54.49#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.17:50:54.49#ibcon#enter wrdev, iclass 3, count 0 2006.173.17:50:54.49#ibcon#first serial, iclass 3, count 0 2006.173.17:50:54.49#ibcon#enter sib2, iclass 3, count 0 2006.173.17:50:54.49#ibcon#flushed, iclass 3, count 0 2006.173.17:50:54.49#ibcon#about to write, iclass 3, count 0 2006.173.17:50:54.49#ibcon#wrote, iclass 3, count 0 2006.173.17:50:54.49#ibcon#about to read 3, iclass 3, count 0 2006.173.17:50:54.51#ibcon#read 3, iclass 3, count 0 2006.173.17:50:54.51#ibcon#about to read 4, iclass 3, count 0 2006.173.17:50:54.51#ibcon#read 4, iclass 3, count 0 2006.173.17:50:54.51#ibcon#about to read 5, iclass 3, count 0 2006.173.17:50:54.51#ibcon#read 5, iclass 3, count 0 2006.173.17:50:54.51#ibcon#about to read 6, iclass 3, count 0 2006.173.17:50:54.51#ibcon#read 6, iclass 3, count 0 2006.173.17:50:54.51#ibcon#end of sib2, iclass 3, count 0 2006.173.17:50:54.51#ibcon#*mode == 0, iclass 3, count 0 2006.173.17:50:54.51#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.17:50:54.51#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.17:50:54.51#ibcon#*before write, iclass 3, count 0 2006.173.17:50:54.51#ibcon#enter sib2, iclass 3, count 0 2006.173.17:50:54.51#ibcon#flushed, iclass 3, count 0 2006.173.17:50:54.51#ibcon#about to write, iclass 3, count 0 2006.173.17:50:54.51#ibcon#wrote, iclass 3, count 0 2006.173.17:50:54.51#ibcon#about to read 3, iclass 3, count 0 2006.173.17:50:54.55#ibcon#read 3, iclass 3, count 0 2006.173.17:50:54.55#ibcon#about to read 4, iclass 3, count 0 2006.173.17:50:54.55#ibcon#read 4, iclass 3, count 0 2006.173.17:50:54.55#ibcon#about to read 5, iclass 3, count 0 2006.173.17:50:54.55#ibcon#read 5, iclass 3, count 0 2006.173.17:50:54.55#ibcon#about to read 6, iclass 3, count 0 2006.173.17:50:54.55#ibcon#read 6, iclass 3, count 0 2006.173.17:50:54.55#ibcon#end of sib2, iclass 3, count 0 2006.173.17:50:54.55#ibcon#*after write, iclass 3, count 0 2006.173.17:50:54.55#ibcon#*before return 0, iclass 3, count 0 2006.173.17:50:54.55#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.17:50:54.55#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.17:50:54.55#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.17:50:54.55#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.17:50:54.55$vck44/vb=6,4 2006.173.17:50:54.55#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.17:50:54.55#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.17:50:54.55#ibcon#ireg 11 cls_cnt 2 2006.173.17:50:54.55#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.17:50:54.61#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.17:50:54.61#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.17:50:54.61#ibcon#enter wrdev, iclass 5, count 2 2006.173.17:50:54.61#ibcon#first serial, iclass 5, count 2 2006.173.17:50:54.61#ibcon#enter sib2, iclass 5, count 2 2006.173.17:50:54.61#ibcon#flushed, iclass 5, count 2 2006.173.17:50:54.61#ibcon#about to write, iclass 5, count 2 2006.173.17:50:54.61#ibcon#wrote, iclass 5, count 2 2006.173.17:50:54.61#ibcon#about to read 3, iclass 5, count 2 2006.173.17:50:54.63#ibcon#read 3, iclass 5, count 2 2006.173.17:50:54.63#ibcon#about to read 4, iclass 5, count 2 2006.173.17:50:54.63#ibcon#read 4, iclass 5, count 2 2006.173.17:50:54.63#ibcon#about to read 5, iclass 5, count 2 2006.173.17:50:54.63#ibcon#read 5, iclass 5, count 2 2006.173.17:50:54.63#ibcon#about to read 6, iclass 5, count 2 2006.173.17:50:54.63#ibcon#read 6, iclass 5, count 2 2006.173.17:50:54.63#ibcon#end of sib2, iclass 5, count 2 2006.173.17:50:54.63#ibcon#*mode == 0, iclass 5, count 2 2006.173.17:50:54.63#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.17:50:54.63#ibcon#[27=AT06-04\r\n] 2006.173.17:50:54.63#ibcon#*before write, iclass 5, count 2 2006.173.17:50:54.63#ibcon#enter sib2, iclass 5, count 2 2006.173.17:50:54.63#ibcon#flushed, iclass 5, count 2 2006.173.17:50:54.63#ibcon#about to write, iclass 5, count 2 2006.173.17:50:54.63#ibcon#wrote, iclass 5, count 2 2006.173.17:50:54.63#ibcon#about to read 3, iclass 5, count 2 2006.173.17:50:54.66#ibcon#read 3, iclass 5, count 2 2006.173.17:50:54.66#ibcon#about to read 4, iclass 5, count 2 2006.173.17:50:54.66#ibcon#read 4, iclass 5, count 2 2006.173.17:50:54.66#ibcon#about to read 5, iclass 5, count 2 2006.173.17:50:54.66#ibcon#read 5, iclass 5, count 2 2006.173.17:50:54.66#ibcon#about to read 6, iclass 5, count 2 2006.173.17:50:54.66#ibcon#read 6, iclass 5, count 2 2006.173.17:50:54.66#ibcon#end of sib2, iclass 5, count 2 2006.173.17:50:54.66#ibcon#*after write, iclass 5, count 2 2006.173.17:50:54.66#ibcon#*before return 0, iclass 5, count 2 2006.173.17:50:54.66#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.17:50:54.66#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.17:50:54.66#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.17:50:54.66#ibcon#ireg 7 cls_cnt 0 2006.173.17:50:54.66#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.17:50:54.78#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.17:50:54.78#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.17:50:54.78#ibcon#enter wrdev, iclass 5, count 0 2006.173.17:50:54.78#ibcon#first serial, iclass 5, count 0 2006.173.17:50:54.78#ibcon#enter sib2, iclass 5, count 0 2006.173.17:50:54.78#ibcon#flushed, iclass 5, count 0 2006.173.17:50:54.78#ibcon#about to write, iclass 5, count 0 2006.173.17:50:54.78#ibcon#wrote, iclass 5, count 0 2006.173.17:50:54.78#ibcon#about to read 3, iclass 5, count 0 2006.173.17:50:54.80#ibcon#read 3, iclass 5, count 0 2006.173.17:50:54.80#ibcon#about to read 4, iclass 5, count 0 2006.173.17:50:54.80#ibcon#read 4, iclass 5, count 0 2006.173.17:50:54.80#ibcon#about to read 5, iclass 5, count 0 2006.173.17:50:54.80#ibcon#read 5, iclass 5, count 0 2006.173.17:50:54.80#ibcon#about to read 6, iclass 5, count 0 2006.173.17:50:54.80#ibcon#read 6, iclass 5, count 0 2006.173.17:50:54.80#ibcon#end of sib2, iclass 5, count 0 2006.173.17:50:54.80#ibcon#*mode == 0, iclass 5, count 0 2006.173.17:50:54.80#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.17:50:54.80#ibcon#[27=USB\r\n] 2006.173.17:50:54.80#ibcon#*before write, iclass 5, count 0 2006.173.17:50:54.80#ibcon#enter sib2, iclass 5, count 0 2006.173.17:50:54.80#ibcon#flushed, iclass 5, count 0 2006.173.17:50:54.80#ibcon#about to write, iclass 5, count 0 2006.173.17:50:54.80#ibcon#wrote, iclass 5, count 0 2006.173.17:50:54.80#ibcon#about to read 3, iclass 5, count 0 2006.173.17:50:54.83#ibcon#read 3, iclass 5, count 0 2006.173.17:50:54.83#ibcon#about to read 4, iclass 5, count 0 2006.173.17:50:54.83#ibcon#read 4, iclass 5, count 0 2006.173.17:50:54.83#ibcon#about to read 5, iclass 5, count 0 2006.173.17:50:54.83#ibcon#read 5, iclass 5, count 0 2006.173.17:50:54.83#ibcon#about to read 6, iclass 5, count 0 2006.173.17:50:54.83#ibcon#read 6, iclass 5, count 0 2006.173.17:50:54.83#ibcon#end of sib2, iclass 5, count 0 2006.173.17:50:54.83#ibcon#*after write, iclass 5, count 0 2006.173.17:50:54.83#ibcon#*before return 0, iclass 5, count 0 2006.173.17:50:54.83#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.17:50:54.83#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.17:50:54.83#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.17:50:54.83#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.17:50:54.83$vck44/vblo=7,734.99 2006.173.17:50:54.83#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.17:50:54.83#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.17:50:54.83#ibcon#ireg 17 cls_cnt 0 2006.173.17:50:54.83#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.17:50:54.83#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.17:50:54.83#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.17:50:54.83#ibcon#enter wrdev, iclass 7, count 0 2006.173.17:50:54.83#ibcon#first serial, iclass 7, count 0 2006.173.17:50:54.83#ibcon#enter sib2, iclass 7, count 0 2006.173.17:50:54.83#ibcon#flushed, iclass 7, count 0 2006.173.17:50:54.83#ibcon#about to write, iclass 7, count 0 2006.173.17:50:54.83#ibcon#wrote, iclass 7, count 0 2006.173.17:50:54.83#ibcon#about to read 3, iclass 7, count 0 2006.173.17:50:54.85#ibcon#read 3, iclass 7, count 0 2006.173.17:50:54.85#ibcon#about to read 4, iclass 7, count 0 2006.173.17:50:54.85#ibcon#read 4, iclass 7, count 0 2006.173.17:50:54.85#ibcon#about to read 5, iclass 7, count 0 2006.173.17:50:54.85#ibcon#read 5, iclass 7, count 0 2006.173.17:50:54.85#ibcon#about to read 6, iclass 7, count 0 2006.173.17:50:54.85#ibcon#read 6, iclass 7, count 0 2006.173.17:50:54.85#ibcon#end of sib2, iclass 7, count 0 2006.173.17:50:54.85#ibcon#*mode == 0, iclass 7, count 0 2006.173.17:50:54.85#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.17:50:54.85#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.17:50:54.85#ibcon#*before write, iclass 7, count 0 2006.173.17:50:54.85#ibcon#enter sib2, iclass 7, count 0 2006.173.17:50:54.85#ibcon#flushed, iclass 7, count 0 2006.173.17:50:54.85#ibcon#about to write, iclass 7, count 0 2006.173.17:50:54.85#ibcon#wrote, iclass 7, count 0 2006.173.17:50:54.85#ibcon#about to read 3, iclass 7, count 0 2006.173.17:50:54.89#ibcon#read 3, iclass 7, count 0 2006.173.17:50:54.89#ibcon#about to read 4, iclass 7, count 0 2006.173.17:50:54.89#ibcon#read 4, iclass 7, count 0 2006.173.17:50:54.89#ibcon#about to read 5, iclass 7, count 0 2006.173.17:50:54.89#ibcon#read 5, iclass 7, count 0 2006.173.17:50:54.89#ibcon#about to read 6, iclass 7, count 0 2006.173.17:50:54.89#ibcon#read 6, iclass 7, count 0 2006.173.17:50:54.89#ibcon#end of sib2, iclass 7, count 0 2006.173.17:50:54.89#ibcon#*after write, iclass 7, count 0 2006.173.17:50:54.89#ibcon#*before return 0, iclass 7, count 0 2006.173.17:50:54.89#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.17:50:54.89#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.17:50:54.89#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.17:50:54.89#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.17:50:54.89$vck44/vb=7,4 2006.173.17:50:54.89#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.17:50:54.89#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.17:50:54.89#ibcon#ireg 11 cls_cnt 2 2006.173.17:50:54.89#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.17:50:54.95#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.17:50:54.95#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.17:50:54.95#ibcon#enter wrdev, iclass 11, count 2 2006.173.17:50:54.95#ibcon#first serial, iclass 11, count 2 2006.173.17:50:54.95#ibcon#enter sib2, iclass 11, count 2 2006.173.17:50:54.95#ibcon#flushed, iclass 11, count 2 2006.173.17:50:54.95#ibcon#about to write, iclass 11, count 2 2006.173.17:50:54.95#ibcon#wrote, iclass 11, count 2 2006.173.17:50:54.95#ibcon#about to read 3, iclass 11, count 2 2006.173.17:50:54.97#ibcon#read 3, iclass 11, count 2 2006.173.17:50:54.97#ibcon#about to read 4, iclass 11, count 2 2006.173.17:50:54.97#ibcon#read 4, iclass 11, count 2 2006.173.17:50:54.97#ibcon#about to read 5, iclass 11, count 2 2006.173.17:50:54.97#ibcon#read 5, iclass 11, count 2 2006.173.17:50:54.97#ibcon#about to read 6, iclass 11, count 2 2006.173.17:50:54.97#ibcon#read 6, iclass 11, count 2 2006.173.17:50:54.97#ibcon#end of sib2, iclass 11, count 2 2006.173.17:50:54.97#ibcon#*mode == 0, iclass 11, count 2 2006.173.17:50:54.97#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.17:50:54.97#ibcon#[27=AT07-04\r\n] 2006.173.17:50:54.97#ibcon#*before write, iclass 11, count 2 2006.173.17:50:54.97#ibcon#enter sib2, iclass 11, count 2 2006.173.17:50:54.97#ibcon#flushed, iclass 11, count 2 2006.173.17:50:54.97#ibcon#about to write, iclass 11, count 2 2006.173.17:50:54.97#ibcon#wrote, iclass 11, count 2 2006.173.17:50:54.97#ibcon#about to read 3, iclass 11, count 2 2006.173.17:50:55.00#ibcon#read 3, iclass 11, count 2 2006.173.17:50:55.00#ibcon#about to read 4, iclass 11, count 2 2006.173.17:50:55.00#ibcon#read 4, iclass 11, count 2 2006.173.17:50:55.00#ibcon#about to read 5, iclass 11, count 2 2006.173.17:50:55.00#ibcon#read 5, iclass 11, count 2 2006.173.17:50:55.00#ibcon#about to read 6, iclass 11, count 2 2006.173.17:50:55.00#ibcon#read 6, iclass 11, count 2 2006.173.17:50:55.00#ibcon#end of sib2, iclass 11, count 2 2006.173.17:50:55.00#ibcon#*after write, iclass 11, count 2 2006.173.17:50:55.00#ibcon#*before return 0, iclass 11, count 2 2006.173.17:50:55.00#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.17:50:55.00#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.17:50:55.00#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.17:50:55.00#ibcon#ireg 7 cls_cnt 0 2006.173.17:50:55.00#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.17:50:55.12#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.17:50:55.12#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.17:50:55.12#ibcon#enter wrdev, iclass 11, count 0 2006.173.17:50:55.12#ibcon#first serial, iclass 11, count 0 2006.173.17:50:55.12#ibcon#enter sib2, iclass 11, count 0 2006.173.17:50:55.12#ibcon#flushed, iclass 11, count 0 2006.173.17:50:55.12#ibcon#about to write, iclass 11, count 0 2006.173.17:50:55.12#ibcon#wrote, iclass 11, count 0 2006.173.17:50:55.12#ibcon#about to read 3, iclass 11, count 0 2006.173.17:50:55.14#ibcon#read 3, iclass 11, count 0 2006.173.17:50:55.14#ibcon#about to read 4, iclass 11, count 0 2006.173.17:50:55.14#ibcon#read 4, iclass 11, count 0 2006.173.17:50:55.14#ibcon#about to read 5, iclass 11, count 0 2006.173.17:50:55.14#ibcon#read 5, iclass 11, count 0 2006.173.17:50:55.14#ibcon#about to read 6, iclass 11, count 0 2006.173.17:50:55.14#ibcon#read 6, iclass 11, count 0 2006.173.17:50:55.14#ibcon#end of sib2, iclass 11, count 0 2006.173.17:50:55.14#ibcon#*mode == 0, iclass 11, count 0 2006.173.17:50:55.14#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.17:50:55.14#ibcon#[27=USB\r\n] 2006.173.17:50:55.14#ibcon#*before write, iclass 11, count 0 2006.173.17:50:55.14#ibcon#enter sib2, iclass 11, count 0 2006.173.17:50:55.14#ibcon#flushed, iclass 11, count 0 2006.173.17:50:55.14#ibcon#about to write, iclass 11, count 0 2006.173.17:50:55.14#ibcon#wrote, iclass 11, count 0 2006.173.17:50:55.14#ibcon#about to read 3, iclass 11, count 0 2006.173.17:50:55.17#ibcon#read 3, iclass 11, count 0 2006.173.17:50:55.17#ibcon#about to read 4, iclass 11, count 0 2006.173.17:50:55.17#ibcon#read 4, iclass 11, count 0 2006.173.17:50:55.17#ibcon#about to read 5, iclass 11, count 0 2006.173.17:50:55.17#ibcon#read 5, iclass 11, count 0 2006.173.17:50:55.17#ibcon#about to read 6, iclass 11, count 0 2006.173.17:50:55.17#ibcon#read 6, iclass 11, count 0 2006.173.17:50:55.17#ibcon#end of sib2, iclass 11, count 0 2006.173.17:50:55.17#ibcon#*after write, iclass 11, count 0 2006.173.17:50:55.17#ibcon#*before return 0, iclass 11, count 0 2006.173.17:50:55.17#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.17:50:55.17#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.17:50:55.17#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.17:50:55.17#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.17:50:55.17$vck44/vblo=8,744.99 2006.173.17:50:55.17#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.17:50:55.17#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.17:50:55.17#ibcon#ireg 17 cls_cnt 0 2006.173.17:50:55.17#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.17:50:55.17#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.17:50:55.17#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.17:50:55.17#ibcon#enter wrdev, iclass 13, count 0 2006.173.17:50:55.17#ibcon#first serial, iclass 13, count 0 2006.173.17:50:55.17#ibcon#enter sib2, iclass 13, count 0 2006.173.17:50:55.17#ibcon#flushed, iclass 13, count 0 2006.173.17:50:55.17#ibcon#about to write, iclass 13, count 0 2006.173.17:50:55.17#ibcon#wrote, iclass 13, count 0 2006.173.17:50:55.17#ibcon#about to read 3, iclass 13, count 0 2006.173.17:50:55.19#ibcon#read 3, iclass 13, count 0 2006.173.17:50:55.19#ibcon#about to read 4, iclass 13, count 0 2006.173.17:50:55.19#ibcon#read 4, iclass 13, count 0 2006.173.17:50:55.19#ibcon#about to read 5, iclass 13, count 0 2006.173.17:50:55.19#ibcon#read 5, iclass 13, count 0 2006.173.17:50:55.19#ibcon#about to read 6, iclass 13, count 0 2006.173.17:50:55.19#ibcon#read 6, iclass 13, count 0 2006.173.17:50:55.19#ibcon#end of sib2, iclass 13, count 0 2006.173.17:50:55.19#ibcon#*mode == 0, iclass 13, count 0 2006.173.17:50:55.19#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.17:50:55.19#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.17:50:55.19#ibcon#*before write, iclass 13, count 0 2006.173.17:50:55.19#ibcon#enter sib2, iclass 13, count 0 2006.173.17:50:55.19#ibcon#flushed, iclass 13, count 0 2006.173.17:50:55.19#ibcon#about to write, iclass 13, count 0 2006.173.17:50:55.19#ibcon#wrote, iclass 13, count 0 2006.173.17:50:55.19#ibcon#about to read 3, iclass 13, count 0 2006.173.17:50:55.23#ibcon#read 3, iclass 13, count 0 2006.173.17:50:55.23#ibcon#about to read 4, iclass 13, count 0 2006.173.17:50:55.23#ibcon#read 4, iclass 13, count 0 2006.173.17:50:55.23#ibcon#about to read 5, iclass 13, count 0 2006.173.17:50:55.23#ibcon#read 5, iclass 13, count 0 2006.173.17:50:55.23#ibcon#about to read 6, iclass 13, count 0 2006.173.17:50:55.23#ibcon#read 6, iclass 13, count 0 2006.173.17:50:55.23#ibcon#end of sib2, iclass 13, count 0 2006.173.17:50:55.23#ibcon#*after write, iclass 13, count 0 2006.173.17:50:55.23#ibcon#*before return 0, iclass 13, count 0 2006.173.17:50:55.23#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.17:50:55.23#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.17:50:55.23#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.17:50:55.23#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.17:50:55.23$vck44/vb=8,4 2006.173.17:50:55.23#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.17:50:55.23#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.17:50:55.23#ibcon#ireg 11 cls_cnt 2 2006.173.17:50:55.23#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.17:50:55.29#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.17:50:55.29#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.17:50:55.29#ibcon#enter wrdev, iclass 15, count 2 2006.173.17:50:55.29#ibcon#first serial, iclass 15, count 2 2006.173.17:50:55.29#ibcon#enter sib2, iclass 15, count 2 2006.173.17:50:55.29#ibcon#flushed, iclass 15, count 2 2006.173.17:50:55.29#ibcon#about to write, iclass 15, count 2 2006.173.17:50:55.29#ibcon#wrote, iclass 15, count 2 2006.173.17:50:55.29#ibcon#about to read 3, iclass 15, count 2 2006.173.17:50:55.31#ibcon#read 3, iclass 15, count 2 2006.173.17:50:55.31#ibcon#about to read 4, iclass 15, count 2 2006.173.17:50:55.31#ibcon#read 4, iclass 15, count 2 2006.173.17:50:55.31#ibcon#about to read 5, iclass 15, count 2 2006.173.17:50:55.31#ibcon#read 5, iclass 15, count 2 2006.173.17:50:55.31#ibcon#about to read 6, iclass 15, count 2 2006.173.17:50:55.31#ibcon#read 6, iclass 15, count 2 2006.173.17:50:55.31#ibcon#end of sib2, iclass 15, count 2 2006.173.17:50:55.31#ibcon#*mode == 0, iclass 15, count 2 2006.173.17:50:55.31#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.17:50:55.31#ibcon#[27=AT08-04\r\n] 2006.173.17:50:55.31#ibcon#*before write, iclass 15, count 2 2006.173.17:50:55.31#ibcon#enter sib2, iclass 15, count 2 2006.173.17:50:55.31#ibcon#flushed, iclass 15, count 2 2006.173.17:50:55.31#ibcon#about to write, iclass 15, count 2 2006.173.17:50:55.31#ibcon#wrote, iclass 15, count 2 2006.173.17:50:55.31#ibcon#about to read 3, iclass 15, count 2 2006.173.17:50:55.34#ibcon#read 3, iclass 15, count 2 2006.173.17:50:55.34#ibcon#about to read 4, iclass 15, count 2 2006.173.17:50:55.34#ibcon#read 4, iclass 15, count 2 2006.173.17:50:55.34#ibcon#about to read 5, iclass 15, count 2 2006.173.17:50:55.34#ibcon#read 5, iclass 15, count 2 2006.173.17:50:55.34#ibcon#about to read 6, iclass 15, count 2 2006.173.17:50:55.34#ibcon#read 6, iclass 15, count 2 2006.173.17:50:55.34#ibcon#end of sib2, iclass 15, count 2 2006.173.17:50:55.34#ibcon#*after write, iclass 15, count 2 2006.173.17:50:55.34#ibcon#*before return 0, iclass 15, count 2 2006.173.17:50:55.34#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.17:50:55.34#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.17:50:55.34#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.17:50:55.34#ibcon#ireg 7 cls_cnt 0 2006.173.17:50:55.34#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.17:50:55.46#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.17:50:55.46#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.17:50:55.46#ibcon#enter wrdev, iclass 15, count 0 2006.173.17:50:55.46#ibcon#first serial, iclass 15, count 0 2006.173.17:50:55.46#ibcon#enter sib2, iclass 15, count 0 2006.173.17:50:55.46#ibcon#flushed, iclass 15, count 0 2006.173.17:50:55.46#ibcon#about to write, iclass 15, count 0 2006.173.17:50:55.46#ibcon#wrote, iclass 15, count 0 2006.173.17:50:55.46#ibcon#about to read 3, iclass 15, count 0 2006.173.17:50:55.48#ibcon#read 3, iclass 15, count 0 2006.173.17:50:55.48#ibcon#about to read 4, iclass 15, count 0 2006.173.17:50:55.48#ibcon#read 4, iclass 15, count 0 2006.173.17:50:55.48#ibcon#about to read 5, iclass 15, count 0 2006.173.17:50:55.48#ibcon#read 5, iclass 15, count 0 2006.173.17:50:55.48#ibcon#about to read 6, iclass 15, count 0 2006.173.17:50:55.48#ibcon#read 6, iclass 15, count 0 2006.173.17:50:55.48#ibcon#end of sib2, iclass 15, count 0 2006.173.17:50:55.48#ibcon#*mode == 0, iclass 15, count 0 2006.173.17:50:55.48#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.17:50:55.48#ibcon#[27=USB\r\n] 2006.173.17:50:55.48#ibcon#*before write, iclass 15, count 0 2006.173.17:50:55.48#ibcon#enter sib2, iclass 15, count 0 2006.173.17:50:55.48#ibcon#flushed, iclass 15, count 0 2006.173.17:50:55.48#ibcon#about to write, iclass 15, count 0 2006.173.17:50:55.48#ibcon#wrote, iclass 15, count 0 2006.173.17:50:55.48#ibcon#about to read 3, iclass 15, count 0 2006.173.17:50:55.51#ibcon#read 3, iclass 15, count 0 2006.173.17:50:55.51#ibcon#about to read 4, iclass 15, count 0 2006.173.17:50:55.51#ibcon#read 4, iclass 15, count 0 2006.173.17:50:55.51#ibcon#about to read 5, iclass 15, count 0 2006.173.17:50:55.51#ibcon#read 5, iclass 15, count 0 2006.173.17:50:55.51#ibcon#about to read 6, iclass 15, count 0 2006.173.17:50:55.51#ibcon#read 6, iclass 15, count 0 2006.173.17:50:55.51#ibcon#end of sib2, iclass 15, count 0 2006.173.17:50:55.51#ibcon#*after write, iclass 15, count 0 2006.173.17:50:55.51#ibcon#*before return 0, iclass 15, count 0 2006.173.17:50:55.51#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.17:50:55.51#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.17:50:55.51#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.17:50:55.51#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.17:50:55.51$vck44/vabw=wide 2006.173.17:50:55.51#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.17:50:55.51#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.17:50:55.51#ibcon#ireg 8 cls_cnt 0 2006.173.17:50:55.51#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.17:50:55.51#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.17:50:55.51#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.17:50:55.51#ibcon#enter wrdev, iclass 17, count 0 2006.173.17:50:55.51#ibcon#first serial, iclass 17, count 0 2006.173.17:50:55.51#ibcon#enter sib2, iclass 17, count 0 2006.173.17:50:55.51#ibcon#flushed, iclass 17, count 0 2006.173.17:50:55.51#ibcon#about to write, iclass 17, count 0 2006.173.17:50:55.51#ibcon#wrote, iclass 17, count 0 2006.173.17:50:55.51#ibcon#about to read 3, iclass 17, count 0 2006.173.17:50:55.53#ibcon#read 3, iclass 17, count 0 2006.173.17:50:55.53#ibcon#about to read 4, iclass 17, count 0 2006.173.17:50:55.53#ibcon#read 4, iclass 17, count 0 2006.173.17:50:55.53#ibcon#about to read 5, iclass 17, count 0 2006.173.17:50:55.53#ibcon#read 5, iclass 17, count 0 2006.173.17:50:55.53#ibcon#about to read 6, iclass 17, count 0 2006.173.17:50:55.53#ibcon#read 6, iclass 17, count 0 2006.173.17:50:55.53#ibcon#end of sib2, iclass 17, count 0 2006.173.17:50:55.53#ibcon#*mode == 0, iclass 17, count 0 2006.173.17:50:55.53#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.17:50:55.53#ibcon#[25=BW32\r\n] 2006.173.17:50:55.53#ibcon#*before write, iclass 17, count 0 2006.173.17:50:55.53#ibcon#enter sib2, iclass 17, count 0 2006.173.17:50:55.53#ibcon#flushed, iclass 17, count 0 2006.173.17:50:55.53#ibcon#about to write, iclass 17, count 0 2006.173.17:50:55.53#ibcon#wrote, iclass 17, count 0 2006.173.17:50:55.53#ibcon#about to read 3, iclass 17, count 0 2006.173.17:50:55.56#ibcon#read 3, iclass 17, count 0 2006.173.17:50:55.56#ibcon#about to read 4, iclass 17, count 0 2006.173.17:50:55.56#ibcon#read 4, iclass 17, count 0 2006.173.17:50:55.56#ibcon#about to read 5, iclass 17, count 0 2006.173.17:50:55.56#ibcon#read 5, iclass 17, count 0 2006.173.17:50:55.56#ibcon#about to read 6, iclass 17, count 0 2006.173.17:50:55.56#ibcon#read 6, iclass 17, count 0 2006.173.17:50:55.56#ibcon#end of sib2, iclass 17, count 0 2006.173.17:50:55.56#ibcon#*after write, iclass 17, count 0 2006.173.17:50:55.56#ibcon#*before return 0, iclass 17, count 0 2006.173.17:50:55.56#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.17:50:55.56#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.17:50:55.56#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.17:50:55.56#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.17:50:55.56$vck44/vbbw=wide 2006.173.17:50:55.56#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.17:50:55.56#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.17:50:55.56#ibcon#ireg 8 cls_cnt 0 2006.173.17:50:55.56#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.17:50:55.63#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.17:50:55.63#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.17:50:55.63#ibcon#enter wrdev, iclass 19, count 0 2006.173.17:50:55.63#ibcon#first serial, iclass 19, count 0 2006.173.17:50:55.63#ibcon#enter sib2, iclass 19, count 0 2006.173.17:50:55.63#ibcon#flushed, iclass 19, count 0 2006.173.17:50:55.63#ibcon#about to write, iclass 19, count 0 2006.173.17:50:55.63#ibcon#wrote, iclass 19, count 0 2006.173.17:50:55.63#ibcon#about to read 3, iclass 19, count 0 2006.173.17:50:55.65#ibcon#read 3, iclass 19, count 0 2006.173.17:50:55.65#ibcon#about to read 4, iclass 19, count 0 2006.173.17:50:55.65#ibcon#read 4, iclass 19, count 0 2006.173.17:50:55.65#ibcon#about to read 5, iclass 19, count 0 2006.173.17:50:55.65#ibcon#read 5, iclass 19, count 0 2006.173.17:50:55.65#ibcon#about to read 6, iclass 19, count 0 2006.173.17:50:55.65#ibcon#read 6, iclass 19, count 0 2006.173.17:50:55.65#ibcon#end of sib2, iclass 19, count 0 2006.173.17:50:55.65#ibcon#*mode == 0, iclass 19, count 0 2006.173.17:50:55.65#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.17:50:55.65#ibcon#[27=BW32\r\n] 2006.173.17:50:55.65#ibcon#*before write, iclass 19, count 0 2006.173.17:50:55.65#ibcon#enter sib2, iclass 19, count 0 2006.173.17:50:55.65#ibcon#flushed, iclass 19, count 0 2006.173.17:50:55.65#ibcon#about to write, iclass 19, count 0 2006.173.17:50:55.65#ibcon#wrote, iclass 19, count 0 2006.173.17:50:55.65#ibcon#about to read 3, iclass 19, count 0 2006.173.17:50:55.68#ibcon#read 3, iclass 19, count 0 2006.173.17:50:55.68#ibcon#about to read 4, iclass 19, count 0 2006.173.17:50:55.68#ibcon#read 4, iclass 19, count 0 2006.173.17:50:55.68#ibcon#about to read 5, iclass 19, count 0 2006.173.17:50:55.68#ibcon#read 5, iclass 19, count 0 2006.173.17:50:55.68#ibcon#about to read 6, iclass 19, count 0 2006.173.17:50:55.68#ibcon#read 6, iclass 19, count 0 2006.173.17:50:55.68#ibcon#end of sib2, iclass 19, count 0 2006.173.17:50:55.68#ibcon#*after write, iclass 19, count 0 2006.173.17:50:55.68#ibcon#*before return 0, iclass 19, count 0 2006.173.17:50:55.68#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.17:50:55.68#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.17:50:55.68#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.17:50:55.68#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.17:50:55.68$setupk4/ifdk4 2006.173.17:50:55.68$ifdk4/lo= 2006.173.17:50:55.68$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.17:50:55.68$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.17:50:55.68$ifdk4/patch= 2006.173.17:50:55.68$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.17:50:55.68$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.17:50:55.68$setupk4/!*+20s 2006.173.17:51:01.53#abcon#<5=/14 1.2 3.2 20.111001002.2\r\n> 2006.173.17:51:01.55#abcon#{5=INTERFACE CLEAR} 2006.173.17:51:01.61#abcon#[5=S1D000X0/0*\r\n] 2006.173.17:51:08.14#trakl#Source acquired 2006.173.17:51:09.14#flagr#flagr/antenna,acquired 2006.173.17:51:10.18$setupk4/"tpicd 2006.173.17:51:10.18$setupk4/echo=off 2006.173.17:51:10.18$setupk4/xlog=off 2006.173.17:51:10.18:!2006.173.17:51:23 2006.173.17:51:23.00:preob 2006.173.17:51:23.14/onsource/TRACKING 2006.173.17:51:23.14:!2006.173.17:51:33 2006.173.17:51:33.00:"tape 2006.173.17:51:33.00:"st=record 2006.173.17:51:33.00:data_valid=on 2006.173.17:51:33.00:midob 2006.173.17:51:33.14/onsource/TRACKING 2006.173.17:51:33.14/wx/20.11,1002.2,100 2006.173.17:51:33.22/cable/+6.5152E-03 2006.173.17:51:34.31/va/01,07,usb,yes,35,38 2006.173.17:51:34.31/va/02,06,usb,yes,35,36 2006.173.17:51:34.31/va/03,05,usb,yes,44,46 2006.173.17:51:34.31/va/04,06,usb,yes,36,38 2006.173.17:51:34.31/va/05,04,usb,yes,28,28 2006.173.17:51:34.31/va/06,03,usb,yes,39,39 2006.173.17:51:34.31/va/07,04,usb,yes,32,33 2006.173.17:51:34.31/va/08,04,usb,yes,27,32 2006.173.17:51:34.54/valo/01,524.99,yes,locked 2006.173.17:51:34.54/valo/02,534.99,yes,locked 2006.173.17:51:34.54/valo/03,564.99,yes,locked 2006.173.17:51:34.54/valo/04,624.99,yes,locked 2006.173.17:51:34.54/valo/05,734.99,yes,locked 2006.173.17:51:34.54/valo/06,814.99,yes,locked 2006.173.17:51:34.54/valo/07,864.99,yes,locked 2006.173.17:51:34.54/valo/08,884.99,yes,locked 2006.173.17:51:35.63/vb/01,04,usb,yes,29,27 2006.173.17:51:35.63/vb/02,04,usb,yes,31,31 2006.173.17:51:35.63/vb/03,04,usb,yes,28,31 2006.173.17:51:35.63/vb/04,04,usb,yes,33,32 2006.173.17:51:35.63/vb/05,04,usb,yes,25,28 2006.173.17:51:35.63/vb/06,04,usb,yes,30,26 2006.173.17:51:35.63/vb/07,04,usb,yes,29,29 2006.173.17:51:35.63/vb/08,04,usb,yes,27,30 2006.173.17:51:35.86/vblo/01,629.99,yes,locked 2006.173.17:51:35.86/vblo/02,634.99,yes,locked 2006.173.17:51:35.86/vblo/03,649.99,yes,locked 2006.173.17:51:35.86/vblo/04,679.99,yes,locked 2006.173.17:51:35.86/vblo/05,709.99,yes,locked 2006.173.17:51:35.86/vblo/06,719.99,yes,locked 2006.173.17:51:35.86/vblo/07,734.99,yes,locked 2006.173.17:51:35.86/vblo/08,744.99,yes,locked 2006.173.17:51:36.01/vabw/8 2006.173.17:51:36.16/vbbw/8 2006.173.17:51:36.25/xfe/off,on,14.7 2006.173.17:51:36.62/ifatt/23,28,28,28 2006.173.17:51:37.08/fmout-gps/S +4.03E-07 2006.173.17:51:37.12:!2006.173.18:04:13 2006.173.18:04:13.00:data_valid=off 2006.173.18:04:13.00:"et 2006.173.18:04:13.00:!+3s 2006.173.18:04:16.01:"tape 2006.173.18:04:16.01:postob 2006.173.18:04:16.20/cable/+6.5148E-03 2006.173.18:04:16.20/wx/20.02,1002.2,100 2006.173.18:04:17.07/fmout-gps/S +4.02E-07 2006.173.18:04:17.07:scan_name=173-1805,jd0606,80 2006.173.18:04:17.07:source=1908-201,191109.65,-200655.1,2000.0,ccw 2006.173.18:04:18.14#flagr#flagr/antenna,new-source 2006.173.18:04:18.14:checkk5 2006.173.18:04:18.57/chk_autoobs//k5ts1/ autoobs is running! 2006.173.18:04:18.96/chk_autoobs//k5ts2/ autoobs is running! 2006.173.18:04:19.37/chk_autoobs//k5ts3/ autoobs is running! 2006.173.18:04:19.78/chk_autoobs//k5ts4/ autoobs is running! 2006.173.18:04:20.47/chk_obsdata//k5ts1/T1731751??a.dat file size is correct (nominal:3040MB, actual:3040MB). 2006.173.18:04:21.19/chk_obsdata//k5ts2/T1731751??b.dat file size is correct (nominal:3040MB, actual:3040MB). 2006.173.18:04:21.89/chk_obsdata//k5ts3/T1731751??c.dat file size is correct (nominal:3040MB, actual:3040MB). 2006.173.18:04:22.60/chk_obsdata//k5ts4/T1731751??d.dat file size is correct (nominal:3040MB, actual:3040MB). 2006.173.18:04:23.32/k5log//k5ts1_log_newline 2006.173.18:04:24.03/k5log//k5ts2_log_newline 2006.173.18:04:24.73/k5log//k5ts3_log_newline 2006.173.18:04:25.46/k5log//k5ts4_log_newline 2006.173.18:04:25.48/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.18:04:25.48:setupk4=1 2006.173.18:04:25.48$setupk4/echo=on 2006.173.18:04:25.48$setupk4/pcalon 2006.173.18:04:25.48$pcalon/"no phase cal control is implemented here 2006.173.18:04:25.48$setupk4/"tpicd=stop 2006.173.18:04:25.48$setupk4/"rec=synch_on 2006.173.18:04:25.48$setupk4/"rec_mode=128 2006.173.18:04:25.48$setupk4/!* 2006.173.18:04:25.48$setupk4/recpk4 2006.173.18:04:25.48$recpk4/recpatch= 2006.173.18:04:25.49$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.18:04:25.49$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.18:04:25.49$setupk4/vck44 2006.173.18:04:25.49$vck44/valo=1,524.99 2006.173.18:04:25.49#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.18:04:25.49#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.18:04:25.49#ibcon#ireg 17 cls_cnt 0 2006.173.18:04:25.49#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.18:04:25.49#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.18:04:25.49#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.18:04:25.49#ibcon#enter wrdev, iclass 20, count 0 2006.173.18:04:25.49#ibcon#first serial, iclass 20, count 0 2006.173.18:04:25.49#ibcon#enter sib2, iclass 20, count 0 2006.173.18:04:25.49#ibcon#flushed, iclass 20, count 0 2006.173.18:04:25.49#ibcon#about to write, iclass 20, count 0 2006.173.18:04:25.49#ibcon#wrote, iclass 20, count 0 2006.173.18:04:25.49#ibcon#about to read 3, iclass 20, count 0 2006.173.18:04:25.50#ibcon#read 3, iclass 20, count 0 2006.173.18:04:25.50#ibcon#about to read 4, iclass 20, count 0 2006.173.18:04:25.50#ibcon#read 4, iclass 20, count 0 2006.173.18:04:25.50#ibcon#about to read 5, iclass 20, count 0 2006.173.18:04:25.50#ibcon#read 5, iclass 20, count 0 2006.173.18:04:25.50#ibcon#about to read 6, iclass 20, count 0 2006.173.18:04:25.50#ibcon#read 6, iclass 20, count 0 2006.173.18:04:25.50#ibcon#end of sib2, iclass 20, count 0 2006.173.18:04:25.50#ibcon#*mode == 0, iclass 20, count 0 2006.173.18:04:25.50#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.18:04:25.50#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.18:04:25.50#ibcon#*before write, iclass 20, count 0 2006.173.18:04:25.50#ibcon#enter sib2, iclass 20, count 0 2006.173.18:04:25.50#ibcon#flushed, iclass 20, count 0 2006.173.18:04:25.50#ibcon#about to write, iclass 20, count 0 2006.173.18:04:25.50#ibcon#wrote, iclass 20, count 0 2006.173.18:04:25.50#ibcon#about to read 3, iclass 20, count 0 2006.173.18:04:25.55#ibcon#read 3, iclass 20, count 0 2006.173.18:04:25.55#ibcon#about to read 4, iclass 20, count 0 2006.173.18:04:25.55#ibcon#read 4, iclass 20, count 0 2006.173.18:04:25.55#ibcon#about to read 5, iclass 20, count 0 2006.173.18:04:25.55#ibcon#read 5, iclass 20, count 0 2006.173.18:04:25.55#ibcon#about to read 6, iclass 20, count 0 2006.173.18:04:25.55#ibcon#read 6, iclass 20, count 0 2006.173.18:04:25.55#ibcon#end of sib2, iclass 20, count 0 2006.173.18:04:25.55#ibcon#*after write, iclass 20, count 0 2006.173.18:04:25.55#ibcon#*before return 0, iclass 20, count 0 2006.173.18:04:25.55#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.18:04:25.55#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.18:04:25.55#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.18:04:25.55#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.18:04:25.55$vck44/va=1,7 2006.173.18:04:25.55#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.18:04:25.55#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.18:04:25.55#ibcon#ireg 11 cls_cnt 2 2006.173.18:04:25.55#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.18:04:25.55#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.18:04:25.55#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.18:04:25.55#ibcon#enter wrdev, iclass 22, count 2 2006.173.18:04:25.55#ibcon#first serial, iclass 22, count 2 2006.173.18:04:25.55#ibcon#enter sib2, iclass 22, count 2 2006.173.18:04:25.55#ibcon#flushed, iclass 22, count 2 2006.173.18:04:25.55#ibcon#about to write, iclass 22, count 2 2006.173.18:04:25.55#ibcon#wrote, iclass 22, count 2 2006.173.18:04:25.55#ibcon#about to read 3, iclass 22, count 2 2006.173.18:04:25.57#ibcon#read 3, iclass 22, count 2 2006.173.18:04:25.57#ibcon#about to read 4, iclass 22, count 2 2006.173.18:04:25.57#ibcon#read 4, iclass 22, count 2 2006.173.18:04:25.57#ibcon#about to read 5, iclass 22, count 2 2006.173.18:04:25.57#ibcon#read 5, iclass 22, count 2 2006.173.18:04:25.57#ibcon#about to read 6, iclass 22, count 2 2006.173.18:04:25.57#ibcon#read 6, iclass 22, count 2 2006.173.18:04:25.57#ibcon#end of sib2, iclass 22, count 2 2006.173.18:04:25.57#ibcon#*mode == 0, iclass 22, count 2 2006.173.18:04:25.57#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.18:04:25.57#ibcon#[25=AT01-07\r\n] 2006.173.18:04:25.57#ibcon#*before write, iclass 22, count 2 2006.173.18:04:25.57#ibcon#enter sib2, iclass 22, count 2 2006.173.18:04:25.57#ibcon#flushed, iclass 22, count 2 2006.173.18:04:25.57#ibcon#about to write, iclass 22, count 2 2006.173.18:04:25.57#ibcon#wrote, iclass 22, count 2 2006.173.18:04:25.57#ibcon#about to read 3, iclass 22, count 2 2006.173.18:04:25.60#ibcon#read 3, iclass 22, count 2 2006.173.18:04:25.60#ibcon#about to read 4, iclass 22, count 2 2006.173.18:04:25.60#ibcon#read 4, iclass 22, count 2 2006.173.18:04:25.60#ibcon#about to read 5, iclass 22, count 2 2006.173.18:04:25.60#ibcon#read 5, iclass 22, count 2 2006.173.18:04:25.60#ibcon#about to read 6, iclass 22, count 2 2006.173.18:04:25.60#ibcon#read 6, iclass 22, count 2 2006.173.18:04:25.60#ibcon#end of sib2, iclass 22, count 2 2006.173.18:04:25.60#ibcon#*after write, iclass 22, count 2 2006.173.18:04:25.60#ibcon#*before return 0, iclass 22, count 2 2006.173.18:04:25.60#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.18:04:25.60#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.18:04:25.60#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.18:04:25.60#ibcon#ireg 7 cls_cnt 0 2006.173.18:04:25.60#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.18:04:25.72#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.18:04:25.72#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.18:04:25.72#ibcon#enter wrdev, iclass 22, count 0 2006.173.18:04:25.72#ibcon#first serial, iclass 22, count 0 2006.173.18:04:25.72#ibcon#enter sib2, iclass 22, count 0 2006.173.18:04:25.72#ibcon#flushed, iclass 22, count 0 2006.173.18:04:25.72#ibcon#about to write, iclass 22, count 0 2006.173.18:04:25.72#ibcon#wrote, iclass 22, count 0 2006.173.18:04:25.72#ibcon#about to read 3, iclass 22, count 0 2006.173.18:04:25.74#ibcon#read 3, iclass 22, count 0 2006.173.18:04:25.74#ibcon#about to read 4, iclass 22, count 0 2006.173.18:04:25.74#ibcon#read 4, iclass 22, count 0 2006.173.18:04:25.74#ibcon#about to read 5, iclass 22, count 0 2006.173.18:04:25.74#ibcon#read 5, iclass 22, count 0 2006.173.18:04:25.74#ibcon#about to read 6, iclass 22, count 0 2006.173.18:04:25.74#ibcon#read 6, iclass 22, count 0 2006.173.18:04:25.74#ibcon#end of sib2, iclass 22, count 0 2006.173.18:04:25.74#ibcon#*mode == 0, iclass 22, count 0 2006.173.18:04:25.74#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.18:04:25.74#ibcon#[25=USB\r\n] 2006.173.18:04:25.74#ibcon#*before write, iclass 22, count 0 2006.173.18:04:25.74#ibcon#enter sib2, iclass 22, count 0 2006.173.18:04:25.74#ibcon#flushed, iclass 22, count 0 2006.173.18:04:25.74#ibcon#about to write, iclass 22, count 0 2006.173.18:04:25.74#ibcon#wrote, iclass 22, count 0 2006.173.18:04:25.74#ibcon#about to read 3, iclass 22, count 0 2006.173.18:04:25.77#ibcon#read 3, iclass 22, count 0 2006.173.18:04:25.77#ibcon#about to read 4, iclass 22, count 0 2006.173.18:04:25.77#ibcon#read 4, iclass 22, count 0 2006.173.18:04:25.77#ibcon#about to read 5, iclass 22, count 0 2006.173.18:04:25.77#ibcon#read 5, iclass 22, count 0 2006.173.18:04:25.77#ibcon#about to read 6, iclass 22, count 0 2006.173.18:04:25.77#ibcon#read 6, iclass 22, count 0 2006.173.18:04:25.77#ibcon#end of sib2, iclass 22, count 0 2006.173.18:04:25.77#ibcon#*after write, iclass 22, count 0 2006.173.18:04:25.77#ibcon#*before return 0, iclass 22, count 0 2006.173.18:04:25.77#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.18:04:25.77#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.18:04:25.77#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.18:04:25.77#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.18:04:25.77$vck44/valo=2,534.99 2006.173.18:04:25.77#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.18:04:25.77#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.18:04:25.77#ibcon#ireg 17 cls_cnt 0 2006.173.18:04:25.77#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.18:04:25.77#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.18:04:25.77#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.18:04:25.77#ibcon#enter wrdev, iclass 24, count 0 2006.173.18:04:25.77#ibcon#first serial, iclass 24, count 0 2006.173.18:04:25.77#ibcon#enter sib2, iclass 24, count 0 2006.173.18:04:25.77#ibcon#flushed, iclass 24, count 0 2006.173.18:04:25.77#ibcon#about to write, iclass 24, count 0 2006.173.18:04:25.77#ibcon#wrote, iclass 24, count 0 2006.173.18:04:25.77#ibcon#about to read 3, iclass 24, count 0 2006.173.18:04:25.79#ibcon#read 3, iclass 24, count 0 2006.173.18:04:25.79#ibcon#about to read 4, iclass 24, count 0 2006.173.18:04:25.79#ibcon#read 4, iclass 24, count 0 2006.173.18:04:25.79#ibcon#about to read 5, iclass 24, count 0 2006.173.18:04:25.79#ibcon#read 5, iclass 24, count 0 2006.173.18:04:25.79#ibcon#about to read 6, iclass 24, count 0 2006.173.18:04:25.79#ibcon#read 6, iclass 24, count 0 2006.173.18:04:25.79#ibcon#end of sib2, iclass 24, count 0 2006.173.18:04:25.79#ibcon#*mode == 0, iclass 24, count 0 2006.173.18:04:25.79#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.18:04:25.79#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.18:04:25.79#ibcon#*before write, iclass 24, count 0 2006.173.18:04:25.79#ibcon#enter sib2, iclass 24, count 0 2006.173.18:04:25.79#ibcon#flushed, iclass 24, count 0 2006.173.18:04:25.79#ibcon#about to write, iclass 24, count 0 2006.173.18:04:25.79#ibcon#wrote, iclass 24, count 0 2006.173.18:04:25.79#ibcon#about to read 3, iclass 24, count 0 2006.173.18:04:25.83#ibcon#read 3, iclass 24, count 0 2006.173.18:04:25.83#ibcon#about to read 4, iclass 24, count 0 2006.173.18:04:25.83#ibcon#read 4, iclass 24, count 0 2006.173.18:04:25.83#ibcon#about to read 5, iclass 24, count 0 2006.173.18:04:25.83#ibcon#read 5, iclass 24, count 0 2006.173.18:04:25.83#ibcon#about to read 6, iclass 24, count 0 2006.173.18:04:25.83#ibcon#read 6, iclass 24, count 0 2006.173.18:04:25.83#ibcon#end of sib2, iclass 24, count 0 2006.173.18:04:25.83#ibcon#*after write, iclass 24, count 0 2006.173.18:04:25.83#ibcon#*before return 0, iclass 24, count 0 2006.173.18:04:25.83#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.18:04:25.83#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.18:04:25.83#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.18:04:25.83#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.18:04:25.83$vck44/va=2,6 2006.173.18:04:25.83#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.18:04:25.83#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.18:04:25.83#ibcon#ireg 11 cls_cnt 2 2006.173.18:04:25.83#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.18:04:25.89#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.18:04:25.89#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.18:04:25.89#ibcon#enter wrdev, iclass 26, count 2 2006.173.18:04:25.89#ibcon#first serial, iclass 26, count 2 2006.173.18:04:25.89#ibcon#enter sib2, iclass 26, count 2 2006.173.18:04:25.89#ibcon#flushed, iclass 26, count 2 2006.173.18:04:25.89#ibcon#about to write, iclass 26, count 2 2006.173.18:04:25.89#ibcon#wrote, iclass 26, count 2 2006.173.18:04:25.89#ibcon#about to read 3, iclass 26, count 2 2006.173.18:04:25.91#ibcon#read 3, iclass 26, count 2 2006.173.18:04:25.91#ibcon#about to read 4, iclass 26, count 2 2006.173.18:04:25.91#ibcon#read 4, iclass 26, count 2 2006.173.18:04:25.91#ibcon#about to read 5, iclass 26, count 2 2006.173.18:04:25.91#ibcon#read 5, iclass 26, count 2 2006.173.18:04:25.91#ibcon#about to read 6, iclass 26, count 2 2006.173.18:04:25.91#ibcon#read 6, iclass 26, count 2 2006.173.18:04:25.91#ibcon#end of sib2, iclass 26, count 2 2006.173.18:04:25.91#ibcon#*mode == 0, iclass 26, count 2 2006.173.18:04:25.91#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.18:04:25.91#ibcon#[25=AT02-06\r\n] 2006.173.18:04:25.91#ibcon#*before write, iclass 26, count 2 2006.173.18:04:25.91#ibcon#enter sib2, iclass 26, count 2 2006.173.18:04:25.91#ibcon#flushed, iclass 26, count 2 2006.173.18:04:25.91#ibcon#about to write, iclass 26, count 2 2006.173.18:04:25.91#ibcon#wrote, iclass 26, count 2 2006.173.18:04:25.91#ibcon#about to read 3, iclass 26, count 2 2006.173.18:04:25.94#ibcon#read 3, iclass 26, count 2 2006.173.18:04:25.94#ibcon#about to read 4, iclass 26, count 2 2006.173.18:04:25.94#ibcon#read 4, iclass 26, count 2 2006.173.18:04:25.94#ibcon#about to read 5, iclass 26, count 2 2006.173.18:04:25.94#ibcon#read 5, iclass 26, count 2 2006.173.18:04:25.94#ibcon#about to read 6, iclass 26, count 2 2006.173.18:04:25.94#ibcon#read 6, iclass 26, count 2 2006.173.18:04:25.94#ibcon#end of sib2, iclass 26, count 2 2006.173.18:04:25.94#ibcon#*after write, iclass 26, count 2 2006.173.18:04:25.94#ibcon#*before return 0, iclass 26, count 2 2006.173.18:04:25.94#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.18:04:25.94#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.18:04:25.94#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.18:04:25.94#ibcon#ireg 7 cls_cnt 0 2006.173.18:04:25.94#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.18:04:26.06#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.18:04:26.06#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.18:04:26.06#ibcon#enter wrdev, iclass 26, count 0 2006.173.18:04:26.06#ibcon#first serial, iclass 26, count 0 2006.173.18:04:26.06#ibcon#enter sib2, iclass 26, count 0 2006.173.18:04:26.06#ibcon#flushed, iclass 26, count 0 2006.173.18:04:26.06#ibcon#about to write, iclass 26, count 0 2006.173.18:04:26.06#ibcon#wrote, iclass 26, count 0 2006.173.18:04:26.06#ibcon#about to read 3, iclass 26, count 0 2006.173.18:04:26.08#ibcon#read 3, iclass 26, count 0 2006.173.18:04:26.08#ibcon#about to read 4, iclass 26, count 0 2006.173.18:04:26.08#ibcon#read 4, iclass 26, count 0 2006.173.18:04:26.08#ibcon#about to read 5, iclass 26, count 0 2006.173.18:04:26.08#ibcon#read 5, iclass 26, count 0 2006.173.18:04:26.08#ibcon#about to read 6, iclass 26, count 0 2006.173.18:04:26.08#ibcon#read 6, iclass 26, count 0 2006.173.18:04:26.08#ibcon#end of sib2, iclass 26, count 0 2006.173.18:04:26.08#ibcon#*mode == 0, iclass 26, count 0 2006.173.18:04:26.08#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.18:04:26.08#ibcon#[25=USB\r\n] 2006.173.18:04:26.08#ibcon#*before write, iclass 26, count 0 2006.173.18:04:26.08#ibcon#enter sib2, iclass 26, count 0 2006.173.18:04:26.08#ibcon#flushed, iclass 26, count 0 2006.173.18:04:26.08#ibcon#about to write, iclass 26, count 0 2006.173.18:04:26.08#ibcon#wrote, iclass 26, count 0 2006.173.18:04:26.08#ibcon#about to read 3, iclass 26, count 0 2006.173.18:04:26.11#ibcon#read 3, iclass 26, count 0 2006.173.18:04:26.11#ibcon#about to read 4, iclass 26, count 0 2006.173.18:04:26.11#ibcon#read 4, iclass 26, count 0 2006.173.18:04:26.11#ibcon#about to read 5, iclass 26, count 0 2006.173.18:04:26.11#ibcon#read 5, iclass 26, count 0 2006.173.18:04:26.11#ibcon#about to read 6, iclass 26, count 0 2006.173.18:04:26.11#ibcon#read 6, iclass 26, count 0 2006.173.18:04:26.11#ibcon#end of sib2, iclass 26, count 0 2006.173.18:04:26.11#ibcon#*after write, iclass 26, count 0 2006.173.18:04:26.11#ibcon#*before return 0, iclass 26, count 0 2006.173.18:04:26.11#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.18:04:26.11#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.18:04:26.11#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.18:04:26.11#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.18:04:26.11$vck44/valo=3,564.99 2006.173.18:04:26.11#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.18:04:26.11#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.18:04:26.11#ibcon#ireg 17 cls_cnt 0 2006.173.18:04:26.11#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.18:04:26.11#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.18:04:26.11#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.18:04:26.11#ibcon#enter wrdev, iclass 28, count 0 2006.173.18:04:26.11#ibcon#first serial, iclass 28, count 0 2006.173.18:04:26.11#ibcon#enter sib2, iclass 28, count 0 2006.173.18:04:26.11#ibcon#flushed, iclass 28, count 0 2006.173.18:04:26.11#ibcon#about to write, iclass 28, count 0 2006.173.18:04:26.11#ibcon#wrote, iclass 28, count 0 2006.173.18:04:26.11#ibcon#about to read 3, iclass 28, count 0 2006.173.18:04:26.13#ibcon#read 3, iclass 28, count 0 2006.173.18:04:26.13#ibcon#about to read 4, iclass 28, count 0 2006.173.18:04:26.13#ibcon#read 4, iclass 28, count 0 2006.173.18:04:26.13#ibcon#about to read 5, iclass 28, count 0 2006.173.18:04:26.13#ibcon#read 5, iclass 28, count 0 2006.173.18:04:26.13#ibcon#about to read 6, iclass 28, count 0 2006.173.18:04:26.13#ibcon#read 6, iclass 28, count 0 2006.173.18:04:26.13#ibcon#end of sib2, iclass 28, count 0 2006.173.18:04:26.13#ibcon#*mode == 0, iclass 28, count 0 2006.173.18:04:26.13#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.18:04:26.13#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.18:04:26.13#ibcon#*before write, iclass 28, count 0 2006.173.18:04:26.13#ibcon#enter sib2, iclass 28, count 0 2006.173.18:04:26.13#ibcon#flushed, iclass 28, count 0 2006.173.18:04:26.13#ibcon#about to write, iclass 28, count 0 2006.173.18:04:26.13#ibcon#wrote, iclass 28, count 0 2006.173.18:04:26.13#ibcon#about to read 3, iclass 28, count 0 2006.173.18:04:26.17#ibcon#read 3, iclass 28, count 0 2006.173.18:04:26.17#ibcon#about to read 4, iclass 28, count 0 2006.173.18:04:26.17#ibcon#read 4, iclass 28, count 0 2006.173.18:04:26.17#ibcon#about to read 5, iclass 28, count 0 2006.173.18:04:26.17#ibcon#read 5, iclass 28, count 0 2006.173.18:04:26.17#ibcon#about to read 6, iclass 28, count 0 2006.173.18:04:26.17#ibcon#read 6, iclass 28, count 0 2006.173.18:04:26.17#ibcon#end of sib2, iclass 28, count 0 2006.173.18:04:26.17#ibcon#*after write, iclass 28, count 0 2006.173.18:04:26.17#ibcon#*before return 0, iclass 28, count 0 2006.173.18:04:26.17#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.18:04:26.17#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.18:04:26.17#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.18:04:26.17#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.18:04:26.17$vck44/va=3,5 2006.173.18:04:26.17#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.18:04:26.17#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.18:04:26.17#ibcon#ireg 11 cls_cnt 2 2006.173.18:04:26.17#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.18:04:26.23#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.18:04:26.23#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.18:04:26.23#ibcon#enter wrdev, iclass 30, count 2 2006.173.18:04:26.23#ibcon#first serial, iclass 30, count 2 2006.173.18:04:26.23#ibcon#enter sib2, iclass 30, count 2 2006.173.18:04:26.23#ibcon#flushed, iclass 30, count 2 2006.173.18:04:26.23#ibcon#about to write, iclass 30, count 2 2006.173.18:04:26.23#ibcon#wrote, iclass 30, count 2 2006.173.18:04:26.23#ibcon#about to read 3, iclass 30, count 2 2006.173.18:04:26.25#ibcon#read 3, iclass 30, count 2 2006.173.18:04:26.25#ibcon#about to read 4, iclass 30, count 2 2006.173.18:04:26.25#ibcon#read 4, iclass 30, count 2 2006.173.18:04:26.25#ibcon#about to read 5, iclass 30, count 2 2006.173.18:04:26.25#ibcon#read 5, iclass 30, count 2 2006.173.18:04:26.25#ibcon#about to read 6, iclass 30, count 2 2006.173.18:04:26.25#ibcon#read 6, iclass 30, count 2 2006.173.18:04:26.25#ibcon#end of sib2, iclass 30, count 2 2006.173.18:04:26.25#ibcon#*mode == 0, iclass 30, count 2 2006.173.18:04:26.25#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.18:04:26.25#ibcon#[25=AT03-05\r\n] 2006.173.18:04:26.25#ibcon#*before write, iclass 30, count 2 2006.173.18:04:26.25#ibcon#enter sib2, iclass 30, count 2 2006.173.18:04:26.25#ibcon#flushed, iclass 30, count 2 2006.173.18:04:26.25#ibcon#about to write, iclass 30, count 2 2006.173.18:04:26.25#ibcon#wrote, iclass 30, count 2 2006.173.18:04:26.25#ibcon#about to read 3, iclass 30, count 2 2006.173.18:04:26.28#ibcon#read 3, iclass 30, count 2 2006.173.18:04:26.28#ibcon#about to read 4, iclass 30, count 2 2006.173.18:04:26.28#ibcon#read 4, iclass 30, count 2 2006.173.18:04:26.28#ibcon#about to read 5, iclass 30, count 2 2006.173.18:04:26.28#ibcon#read 5, iclass 30, count 2 2006.173.18:04:26.28#ibcon#about to read 6, iclass 30, count 2 2006.173.18:04:26.28#ibcon#read 6, iclass 30, count 2 2006.173.18:04:26.28#ibcon#end of sib2, iclass 30, count 2 2006.173.18:04:26.28#ibcon#*after write, iclass 30, count 2 2006.173.18:04:26.28#ibcon#*before return 0, iclass 30, count 2 2006.173.18:04:26.28#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.18:04:26.28#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.18:04:26.28#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.18:04:26.28#ibcon#ireg 7 cls_cnt 0 2006.173.18:04:26.28#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.18:04:26.40#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.18:04:26.40#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.18:04:26.40#ibcon#enter wrdev, iclass 30, count 0 2006.173.18:04:26.40#ibcon#first serial, iclass 30, count 0 2006.173.18:04:26.40#ibcon#enter sib2, iclass 30, count 0 2006.173.18:04:26.40#ibcon#flushed, iclass 30, count 0 2006.173.18:04:26.40#ibcon#about to write, iclass 30, count 0 2006.173.18:04:26.40#ibcon#wrote, iclass 30, count 0 2006.173.18:04:26.40#ibcon#about to read 3, iclass 30, count 0 2006.173.18:04:26.42#ibcon#read 3, iclass 30, count 0 2006.173.18:04:26.42#ibcon#about to read 4, iclass 30, count 0 2006.173.18:04:26.42#ibcon#read 4, iclass 30, count 0 2006.173.18:04:26.42#ibcon#about to read 5, iclass 30, count 0 2006.173.18:04:26.42#ibcon#read 5, iclass 30, count 0 2006.173.18:04:26.42#ibcon#about to read 6, iclass 30, count 0 2006.173.18:04:26.42#ibcon#read 6, iclass 30, count 0 2006.173.18:04:26.42#ibcon#end of sib2, iclass 30, count 0 2006.173.18:04:26.42#ibcon#*mode == 0, iclass 30, count 0 2006.173.18:04:26.42#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.18:04:26.42#ibcon#[25=USB\r\n] 2006.173.18:04:26.42#ibcon#*before write, iclass 30, count 0 2006.173.18:04:26.42#ibcon#enter sib2, iclass 30, count 0 2006.173.18:04:26.42#ibcon#flushed, iclass 30, count 0 2006.173.18:04:26.42#ibcon#about to write, iclass 30, count 0 2006.173.18:04:26.42#ibcon#wrote, iclass 30, count 0 2006.173.18:04:26.42#ibcon#about to read 3, iclass 30, count 0 2006.173.18:04:26.45#ibcon#read 3, iclass 30, count 0 2006.173.18:04:26.45#ibcon#about to read 4, iclass 30, count 0 2006.173.18:04:26.45#ibcon#read 4, iclass 30, count 0 2006.173.18:04:26.45#ibcon#about to read 5, iclass 30, count 0 2006.173.18:04:26.45#ibcon#read 5, iclass 30, count 0 2006.173.18:04:26.45#ibcon#about to read 6, iclass 30, count 0 2006.173.18:04:26.45#ibcon#read 6, iclass 30, count 0 2006.173.18:04:26.45#ibcon#end of sib2, iclass 30, count 0 2006.173.18:04:26.45#ibcon#*after write, iclass 30, count 0 2006.173.18:04:26.45#ibcon#*before return 0, iclass 30, count 0 2006.173.18:04:26.45#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.18:04:26.45#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.18:04:26.45#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.18:04:26.45#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.18:04:26.45$vck44/valo=4,624.99 2006.173.18:04:26.45#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.18:04:26.45#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.18:04:26.45#ibcon#ireg 17 cls_cnt 0 2006.173.18:04:26.45#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.18:04:26.45#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.18:04:26.45#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.18:04:26.45#ibcon#enter wrdev, iclass 32, count 0 2006.173.18:04:26.45#ibcon#first serial, iclass 32, count 0 2006.173.18:04:26.45#ibcon#enter sib2, iclass 32, count 0 2006.173.18:04:26.45#ibcon#flushed, iclass 32, count 0 2006.173.18:04:26.45#ibcon#about to write, iclass 32, count 0 2006.173.18:04:26.45#ibcon#wrote, iclass 32, count 0 2006.173.18:04:26.45#ibcon#about to read 3, iclass 32, count 0 2006.173.18:04:26.47#ibcon#read 3, iclass 32, count 0 2006.173.18:04:26.47#ibcon#about to read 4, iclass 32, count 0 2006.173.18:04:26.47#ibcon#read 4, iclass 32, count 0 2006.173.18:04:26.47#ibcon#about to read 5, iclass 32, count 0 2006.173.18:04:26.47#ibcon#read 5, iclass 32, count 0 2006.173.18:04:26.47#ibcon#about to read 6, iclass 32, count 0 2006.173.18:04:26.47#ibcon#read 6, iclass 32, count 0 2006.173.18:04:26.47#ibcon#end of sib2, iclass 32, count 0 2006.173.18:04:26.47#ibcon#*mode == 0, iclass 32, count 0 2006.173.18:04:26.47#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.18:04:26.47#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.18:04:26.47#ibcon#*before write, iclass 32, count 0 2006.173.18:04:26.47#ibcon#enter sib2, iclass 32, count 0 2006.173.18:04:26.47#ibcon#flushed, iclass 32, count 0 2006.173.18:04:26.47#ibcon#about to write, iclass 32, count 0 2006.173.18:04:26.47#ibcon#wrote, iclass 32, count 0 2006.173.18:04:26.47#ibcon#about to read 3, iclass 32, count 0 2006.173.18:04:26.51#ibcon#read 3, iclass 32, count 0 2006.173.18:04:26.51#ibcon#about to read 4, iclass 32, count 0 2006.173.18:04:26.51#ibcon#read 4, iclass 32, count 0 2006.173.18:04:26.51#ibcon#about to read 5, iclass 32, count 0 2006.173.18:04:26.51#ibcon#read 5, iclass 32, count 0 2006.173.18:04:26.51#ibcon#about to read 6, iclass 32, count 0 2006.173.18:04:26.51#ibcon#read 6, iclass 32, count 0 2006.173.18:04:26.51#ibcon#end of sib2, iclass 32, count 0 2006.173.18:04:26.51#ibcon#*after write, iclass 32, count 0 2006.173.18:04:26.51#ibcon#*before return 0, iclass 32, count 0 2006.173.18:04:26.51#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.18:04:26.51#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.18:04:26.51#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.18:04:26.51#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.18:04:26.51$vck44/va=4,6 2006.173.18:04:26.51#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.18:04:26.51#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.18:04:26.51#ibcon#ireg 11 cls_cnt 2 2006.173.18:04:26.51#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.18:04:26.57#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.18:04:26.57#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.18:04:26.57#ibcon#enter wrdev, iclass 34, count 2 2006.173.18:04:26.57#ibcon#first serial, iclass 34, count 2 2006.173.18:04:26.57#ibcon#enter sib2, iclass 34, count 2 2006.173.18:04:26.57#ibcon#flushed, iclass 34, count 2 2006.173.18:04:26.57#ibcon#about to write, iclass 34, count 2 2006.173.18:04:26.57#ibcon#wrote, iclass 34, count 2 2006.173.18:04:26.57#ibcon#about to read 3, iclass 34, count 2 2006.173.18:04:26.59#ibcon#read 3, iclass 34, count 2 2006.173.18:04:26.59#ibcon#about to read 4, iclass 34, count 2 2006.173.18:04:26.59#ibcon#read 4, iclass 34, count 2 2006.173.18:04:26.59#ibcon#about to read 5, iclass 34, count 2 2006.173.18:04:26.59#ibcon#read 5, iclass 34, count 2 2006.173.18:04:26.59#ibcon#about to read 6, iclass 34, count 2 2006.173.18:04:26.59#ibcon#read 6, iclass 34, count 2 2006.173.18:04:26.59#ibcon#end of sib2, iclass 34, count 2 2006.173.18:04:26.59#ibcon#*mode == 0, iclass 34, count 2 2006.173.18:04:26.59#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.18:04:26.59#ibcon#[25=AT04-06\r\n] 2006.173.18:04:26.59#ibcon#*before write, iclass 34, count 2 2006.173.18:04:26.59#ibcon#enter sib2, iclass 34, count 2 2006.173.18:04:26.59#ibcon#flushed, iclass 34, count 2 2006.173.18:04:26.59#ibcon#about to write, iclass 34, count 2 2006.173.18:04:26.59#ibcon#wrote, iclass 34, count 2 2006.173.18:04:26.59#ibcon#about to read 3, iclass 34, count 2 2006.173.18:04:26.62#ibcon#read 3, iclass 34, count 2 2006.173.18:04:26.62#ibcon#about to read 4, iclass 34, count 2 2006.173.18:04:26.62#ibcon#read 4, iclass 34, count 2 2006.173.18:04:26.62#ibcon#about to read 5, iclass 34, count 2 2006.173.18:04:26.62#ibcon#read 5, iclass 34, count 2 2006.173.18:04:26.62#ibcon#about to read 6, iclass 34, count 2 2006.173.18:04:26.62#ibcon#read 6, iclass 34, count 2 2006.173.18:04:26.62#ibcon#end of sib2, iclass 34, count 2 2006.173.18:04:26.62#ibcon#*after write, iclass 34, count 2 2006.173.18:04:26.62#ibcon#*before return 0, iclass 34, count 2 2006.173.18:04:26.62#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.18:04:26.62#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.18:04:26.62#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.18:04:26.62#ibcon#ireg 7 cls_cnt 0 2006.173.18:04:26.62#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.18:04:26.74#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.18:04:26.74#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.18:04:26.74#ibcon#enter wrdev, iclass 34, count 0 2006.173.18:04:26.74#ibcon#first serial, iclass 34, count 0 2006.173.18:04:26.74#ibcon#enter sib2, iclass 34, count 0 2006.173.18:04:26.74#ibcon#flushed, iclass 34, count 0 2006.173.18:04:26.74#ibcon#about to write, iclass 34, count 0 2006.173.18:04:26.74#ibcon#wrote, iclass 34, count 0 2006.173.18:04:26.74#ibcon#about to read 3, iclass 34, count 0 2006.173.18:04:26.76#ibcon#read 3, iclass 34, count 0 2006.173.18:04:26.76#ibcon#about to read 4, iclass 34, count 0 2006.173.18:04:26.76#ibcon#read 4, iclass 34, count 0 2006.173.18:04:26.76#ibcon#about to read 5, iclass 34, count 0 2006.173.18:04:26.76#ibcon#read 5, iclass 34, count 0 2006.173.18:04:26.76#ibcon#about to read 6, iclass 34, count 0 2006.173.18:04:26.76#ibcon#read 6, iclass 34, count 0 2006.173.18:04:26.76#ibcon#end of sib2, iclass 34, count 0 2006.173.18:04:26.76#ibcon#*mode == 0, iclass 34, count 0 2006.173.18:04:26.76#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.18:04:26.76#ibcon#[25=USB\r\n] 2006.173.18:04:26.76#ibcon#*before write, iclass 34, count 0 2006.173.18:04:26.76#ibcon#enter sib2, iclass 34, count 0 2006.173.18:04:26.76#ibcon#flushed, iclass 34, count 0 2006.173.18:04:26.76#ibcon#about to write, iclass 34, count 0 2006.173.18:04:26.76#ibcon#wrote, iclass 34, count 0 2006.173.18:04:26.76#ibcon#about to read 3, iclass 34, count 0 2006.173.18:04:26.79#ibcon#read 3, iclass 34, count 0 2006.173.18:04:26.79#ibcon#about to read 4, iclass 34, count 0 2006.173.18:04:26.79#ibcon#read 4, iclass 34, count 0 2006.173.18:04:26.79#ibcon#about to read 5, iclass 34, count 0 2006.173.18:04:26.79#ibcon#read 5, iclass 34, count 0 2006.173.18:04:26.79#ibcon#about to read 6, iclass 34, count 0 2006.173.18:04:26.79#ibcon#read 6, iclass 34, count 0 2006.173.18:04:26.79#ibcon#end of sib2, iclass 34, count 0 2006.173.18:04:26.79#ibcon#*after write, iclass 34, count 0 2006.173.18:04:26.79#ibcon#*before return 0, iclass 34, count 0 2006.173.18:04:26.79#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.18:04:26.79#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.18:04:26.79#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.18:04:26.79#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.18:04:26.79$vck44/valo=5,734.99 2006.173.18:04:26.79#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.18:04:26.79#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.18:04:26.79#ibcon#ireg 17 cls_cnt 0 2006.173.18:04:26.79#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.18:04:26.79#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.18:04:26.79#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.18:04:26.79#ibcon#enter wrdev, iclass 36, count 0 2006.173.18:04:26.79#ibcon#first serial, iclass 36, count 0 2006.173.18:04:26.79#ibcon#enter sib2, iclass 36, count 0 2006.173.18:04:26.79#ibcon#flushed, iclass 36, count 0 2006.173.18:04:26.79#ibcon#about to write, iclass 36, count 0 2006.173.18:04:26.79#ibcon#wrote, iclass 36, count 0 2006.173.18:04:26.79#ibcon#about to read 3, iclass 36, count 0 2006.173.18:04:26.81#ibcon#read 3, iclass 36, count 0 2006.173.18:04:26.81#ibcon#about to read 4, iclass 36, count 0 2006.173.18:04:26.81#ibcon#read 4, iclass 36, count 0 2006.173.18:04:26.81#ibcon#about to read 5, iclass 36, count 0 2006.173.18:04:26.81#ibcon#read 5, iclass 36, count 0 2006.173.18:04:26.81#ibcon#about to read 6, iclass 36, count 0 2006.173.18:04:26.81#ibcon#read 6, iclass 36, count 0 2006.173.18:04:26.81#ibcon#end of sib2, iclass 36, count 0 2006.173.18:04:26.81#ibcon#*mode == 0, iclass 36, count 0 2006.173.18:04:26.81#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.18:04:26.81#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.18:04:26.81#ibcon#*before write, iclass 36, count 0 2006.173.18:04:26.81#ibcon#enter sib2, iclass 36, count 0 2006.173.18:04:26.81#ibcon#flushed, iclass 36, count 0 2006.173.18:04:26.81#ibcon#about to write, iclass 36, count 0 2006.173.18:04:26.81#ibcon#wrote, iclass 36, count 0 2006.173.18:04:26.81#ibcon#about to read 3, iclass 36, count 0 2006.173.18:04:26.85#ibcon#read 3, iclass 36, count 0 2006.173.18:04:26.85#ibcon#about to read 4, iclass 36, count 0 2006.173.18:04:26.85#ibcon#read 4, iclass 36, count 0 2006.173.18:04:26.85#ibcon#about to read 5, iclass 36, count 0 2006.173.18:04:26.85#ibcon#read 5, iclass 36, count 0 2006.173.18:04:26.85#ibcon#about to read 6, iclass 36, count 0 2006.173.18:04:26.85#ibcon#read 6, iclass 36, count 0 2006.173.18:04:26.85#ibcon#end of sib2, iclass 36, count 0 2006.173.18:04:26.85#ibcon#*after write, iclass 36, count 0 2006.173.18:04:26.85#ibcon#*before return 0, iclass 36, count 0 2006.173.18:04:26.85#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.18:04:26.85#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.18:04:26.85#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.18:04:26.85#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.18:04:26.85$vck44/va=5,4 2006.173.18:04:26.85#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.18:04:26.85#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.18:04:26.85#ibcon#ireg 11 cls_cnt 2 2006.173.18:04:26.85#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.18:04:26.91#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.18:04:26.91#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.18:04:26.91#ibcon#enter wrdev, iclass 38, count 2 2006.173.18:04:26.91#ibcon#first serial, iclass 38, count 2 2006.173.18:04:26.91#ibcon#enter sib2, iclass 38, count 2 2006.173.18:04:26.91#ibcon#flushed, iclass 38, count 2 2006.173.18:04:26.91#ibcon#about to write, iclass 38, count 2 2006.173.18:04:26.91#ibcon#wrote, iclass 38, count 2 2006.173.18:04:26.91#ibcon#about to read 3, iclass 38, count 2 2006.173.18:04:26.93#ibcon#read 3, iclass 38, count 2 2006.173.18:04:26.93#ibcon#about to read 4, iclass 38, count 2 2006.173.18:04:26.93#ibcon#read 4, iclass 38, count 2 2006.173.18:04:26.93#ibcon#about to read 5, iclass 38, count 2 2006.173.18:04:26.93#ibcon#read 5, iclass 38, count 2 2006.173.18:04:26.93#ibcon#about to read 6, iclass 38, count 2 2006.173.18:04:26.93#ibcon#read 6, iclass 38, count 2 2006.173.18:04:26.93#ibcon#end of sib2, iclass 38, count 2 2006.173.18:04:26.93#ibcon#*mode == 0, iclass 38, count 2 2006.173.18:04:26.93#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.18:04:26.93#ibcon#[25=AT05-04\r\n] 2006.173.18:04:26.93#ibcon#*before write, iclass 38, count 2 2006.173.18:04:26.93#ibcon#enter sib2, iclass 38, count 2 2006.173.18:04:26.93#ibcon#flushed, iclass 38, count 2 2006.173.18:04:26.93#ibcon#about to write, iclass 38, count 2 2006.173.18:04:26.93#ibcon#wrote, iclass 38, count 2 2006.173.18:04:26.93#ibcon#about to read 3, iclass 38, count 2 2006.173.18:04:26.96#ibcon#read 3, iclass 38, count 2 2006.173.18:04:26.96#ibcon#about to read 4, iclass 38, count 2 2006.173.18:04:26.96#ibcon#read 4, iclass 38, count 2 2006.173.18:04:26.96#ibcon#about to read 5, iclass 38, count 2 2006.173.18:04:26.96#ibcon#read 5, iclass 38, count 2 2006.173.18:04:26.96#ibcon#about to read 6, iclass 38, count 2 2006.173.18:04:26.96#ibcon#read 6, iclass 38, count 2 2006.173.18:04:26.96#ibcon#end of sib2, iclass 38, count 2 2006.173.18:04:26.96#ibcon#*after write, iclass 38, count 2 2006.173.18:04:26.96#ibcon#*before return 0, iclass 38, count 2 2006.173.18:04:26.96#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.18:04:26.96#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.18:04:26.96#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.18:04:26.96#ibcon#ireg 7 cls_cnt 0 2006.173.18:04:26.96#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.18:04:27.08#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.18:04:27.08#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.18:04:27.08#ibcon#enter wrdev, iclass 38, count 0 2006.173.18:04:27.08#ibcon#first serial, iclass 38, count 0 2006.173.18:04:27.08#ibcon#enter sib2, iclass 38, count 0 2006.173.18:04:27.08#ibcon#flushed, iclass 38, count 0 2006.173.18:04:27.08#ibcon#about to write, iclass 38, count 0 2006.173.18:04:27.08#ibcon#wrote, iclass 38, count 0 2006.173.18:04:27.08#ibcon#about to read 3, iclass 38, count 0 2006.173.18:04:27.10#ibcon#read 3, iclass 38, count 0 2006.173.18:04:27.10#ibcon#about to read 4, iclass 38, count 0 2006.173.18:04:27.10#ibcon#read 4, iclass 38, count 0 2006.173.18:04:27.10#ibcon#about to read 5, iclass 38, count 0 2006.173.18:04:27.10#ibcon#read 5, iclass 38, count 0 2006.173.18:04:27.10#ibcon#about to read 6, iclass 38, count 0 2006.173.18:04:27.10#ibcon#read 6, iclass 38, count 0 2006.173.18:04:27.10#ibcon#end of sib2, iclass 38, count 0 2006.173.18:04:27.10#ibcon#*mode == 0, iclass 38, count 0 2006.173.18:04:27.10#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.18:04:27.10#ibcon#[25=USB\r\n] 2006.173.18:04:27.10#ibcon#*before write, iclass 38, count 0 2006.173.18:04:27.10#ibcon#enter sib2, iclass 38, count 0 2006.173.18:04:27.10#ibcon#flushed, iclass 38, count 0 2006.173.18:04:27.10#ibcon#about to write, iclass 38, count 0 2006.173.18:04:27.10#ibcon#wrote, iclass 38, count 0 2006.173.18:04:27.10#ibcon#about to read 3, iclass 38, count 0 2006.173.18:04:27.13#ibcon#read 3, iclass 38, count 0 2006.173.18:04:27.13#ibcon#about to read 4, iclass 38, count 0 2006.173.18:04:27.13#ibcon#read 4, iclass 38, count 0 2006.173.18:04:27.13#ibcon#about to read 5, iclass 38, count 0 2006.173.18:04:27.13#ibcon#read 5, iclass 38, count 0 2006.173.18:04:27.13#ibcon#about to read 6, iclass 38, count 0 2006.173.18:04:27.13#ibcon#read 6, iclass 38, count 0 2006.173.18:04:27.13#ibcon#end of sib2, iclass 38, count 0 2006.173.18:04:27.13#ibcon#*after write, iclass 38, count 0 2006.173.18:04:27.13#ibcon#*before return 0, iclass 38, count 0 2006.173.18:04:27.13#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.18:04:27.13#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.18:04:27.13#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.18:04:27.13#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.18:04:27.13$vck44/valo=6,814.99 2006.173.18:04:27.13#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.18:04:27.13#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.18:04:27.13#ibcon#ireg 17 cls_cnt 0 2006.173.18:04:27.13#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.18:04:27.13#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.18:04:27.13#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.18:04:27.13#ibcon#enter wrdev, iclass 40, count 0 2006.173.18:04:27.13#ibcon#first serial, iclass 40, count 0 2006.173.18:04:27.13#ibcon#enter sib2, iclass 40, count 0 2006.173.18:04:27.13#ibcon#flushed, iclass 40, count 0 2006.173.18:04:27.13#ibcon#about to write, iclass 40, count 0 2006.173.18:04:27.13#ibcon#wrote, iclass 40, count 0 2006.173.18:04:27.13#ibcon#about to read 3, iclass 40, count 0 2006.173.18:04:27.15#ibcon#read 3, iclass 40, count 0 2006.173.18:04:27.15#ibcon#about to read 4, iclass 40, count 0 2006.173.18:04:27.15#ibcon#read 4, iclass 40, count 0 2006.173.18:04:27.15#ibcon#about to read 5, iclass 40, count 0 2006.173.18:04:27.15#ibcon#read 5, iclass 40, count 0 2006.173.18:04:27.15#ibcon#about to read 6, iclass 40, count 0 2006.173.18:04:27.15#ibcon#read 6, iclass 40, count 0 2006.173.18:04:27.15#ibcon#end of sib2, iclass 40, count 0 2006.173.18:04:27.15#ibcon#*mode == 0, iclass 40, count 0 2006.173.18:04:27.15#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.18:04:27.15#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.18:04:27.15#ibcon#*before write, iclass 40, count 0 2006.173.18:04:27.15#ibcon#enter sib2, iclass 40, count 0 2006.173.18:04:27.15#ibcon#flushed, iclass 40, count 0 2006.173.18:04:27.15#ibcon#about to write, iclass 40, count 0 2006.173.18:04:27.15#ibcon#wrote, iclass 40, count 0 2006.173.18:04:27.15#ibcon#about to read 3, iclass 40, count 0 2006.173.18:04:27.19#ibcon#read 3, iclass 40, count 0 2006.173.18:04:27.19#ibcon#about to read 4, iclass 40, count 0 2006.173.18:04:27.19#ibcon#read 4, iclass 40, count 0 2006.173.18:04:27.19#ibcon#about to read 5, iclass 40, count 0 2006.173.18:04:27.19#ibcon#read 5, iclass 40, count 0 2006.173.18:04:27.19#ibcon#about to read 6, iclass 40, count 0 2006.173.18:04:27.19#ibcon#read 6, iclass 40, count 0 2006.173.18:04:27.19#ibcon#end of sib2, iclass 40, count 0 2006.173.18:04:27.19#ibcon#*after write, iclass 40, count 0 2006.173.18:04:27.19#ibcon#*before return 0, iclass 40, count 0 2006.173.18:04:27.19#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.18:04:27.19#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.18:04:27.19#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.18:04:27.19#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.18:04:27.19$vck44/va=6,3 2006.173.18:04:27.19#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.18:04:27.19#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.18:04:27.19#ibcon#ireg 11 cls_cnt 2 2006.173.18:04:27.19#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.18:04:27.25#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.18:04:27.25#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.18:04:27.25#ibcon#enter wrdev, iclass 4, count 2 2006.173.18:04:27.25#ibcon#first serial, iclass 4, count 2 2006.173.18:04:27.25#ibcon#enter sib2, iclass 4, count 2 2006.173.18:04:27.25#ibcon#flushed, iclass 4, count 2 2006.173.18:04:27.25#ibcon#about to write, iclass 4, count 2 2006.173.18:04:27.25#ibcon#wrote, iclass 4, count 2 2006.173.18:04:27.25#ibcon#about to read 3, iclass 4, count 2 2006.173.18:04:27.27#ibcon#read 3, iclass 4, count 2 2006.173.18:04:27.27#ibcon#about to read 4, iclass 4, count 2 2006.173.18:04:27.27#ibcon#read 4, iclass 4, count 2 2006.173.18:04:27.27#ibcon#about to read 5, iclass 4, count 2 2006.173.18:04:27.27#ibcon#read 5, iclass 4, count 2 2006.173.18:04:27.27#ibcon#about to read 6, iclass 4, count 2 2006.173.18:04:27.27#ibcon#read 6, iclass 4, count 2 2006.173.18:04:27.27#ibcon#end of sib2, iclass 4, count 2 2006.173.18:04:27.27#ibcon#*mode == 0, iclass 4, count 2 2006.173.18:04:27.27#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.18:04:27.27#ibcon#[25=AT06-03\r\n] 2006.173.18:04:27.27#ibcon#*before write, iclass 4, count 2 2006.173.18:04:27.27#ibcon#enter sib2, iclass 4, count 2 2006.173.18:04:27.27#ibcon#flushed, iclass 4, count 2 2006.173.18:04:27.27#ibcon#about to write, iclass 4, count 2 2006.173.18:04:27.27#ibcon#wrote, iclass 4, count 2 2006.173.18:04:27.27#ibcon#about to read 3, iclass 4, count 2 2006.173.18:04:27.30#ibcon#read 3, iclass 4, count 2 2006.173.18:04:27.30#ibcon#about to read 4, iclass 4, count 2 2006.173.18:04:27.30#ibcon#read 4, iclass 4, count 2 2006.173.18:04:27.30#ibcon#about to read 5, iclass 4, count 2 2006.173.18:04:27.30#ibcon#read 5, iclass 4, count 2 2006.173.18:04:27.30#ibcon#about to read 6, iclass 4, count 2 2006.173.18:04:27.30#ibcon#read 6, iclass 4, count 2 2006.173.18:04:27.30#ibcon#end of sib2, iclass 4, count 2 2006.173.18:04:27.30#ibcon#*after write, iclass 4, count 2 2006.173.18:04:27.30#ibcon#*before return 0, iclass 4, count 2 2006.173.18:04:27.30#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.18:04:27.30#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.18:04:27.30#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.18:04:27.30#ibcon#ireg 7 cls_cnt 0 2006.173.18:04:27.30#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.18:04:27.42#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.18:04:27.42#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.18:04:27.42#ibcon#enter wrdev, iclass 4, count 0 2006.173.18:04:27.42#ibcon#first serial, iclass 4, count 0 2006.173.18:04:27.42#ibcon#enter sib2, iclass 4, count 0 2006.173.18:04:27.42#ibcon#flushed, iclass 4, count 0 2006.173.18:04:27.42#ibcon#about to write, iclass 4, count 0 2006.173.18:04:27.42#ibcon#wrote, iclass 4, count 0 2006.173.18:04:27.42#ibcon#about to read 3, iclass 4, count 0 2006.173.18:04:27.44#ibcon#read 3, iclass 4, count 0 2006.173.18:04:27.44#ibcon#about to read 4, iclass 4, count 0 2006.173.18:04:27.44#ibcon#read 4, iclass 4, count 0 2006.173.18:04:27.44#ibcon#about to read 5, iclass 4, count 0 2006.173.18:04:27.44#ibcon#read 5, iclass 4, count 0 2006.173.18:04:27.44#ibcon#about to read 6, iclass 4, count 0 2006.173.18:04:27.44#ibcon#read 6, iclass 4, count 0 2006.173.18:04:27.44#ibcon#end of sib2, iclass 4, count 0 2006.173.18:04:27.44#ibcon#*mode == 0, iclass 4, count 0 2006.173.18:04:27.44#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.18:04:27.44#ibcon#[25=USB\r\n] 2006.173.18:04:27.44#ibcon#*before write, iclass 4, count 0 2006.173.18:04:27.44#ibcon#enter sib2, iclass 4, count 0 2006.173.18:04:27.44#ibcon#flushed, iclass 4, count 0 2006.173.18:04:27.44#ibcon#about to write, iclass 4, count 0 2006.173.18:04:27.44#ibcon#wrote, iclass 4, count 0 2006.173.18:04:27.44#ibcon#about to read 3, iclass 4, count 0 2006.173.18:04:27.47#ibcon#read 3, iclass 4, count 0 2006.173.18:04:27.47#ibcon#about to read 4, iclass 4, count 0 2006.173.18:04:27.47#ibcon#read 4, iclass 4, count 0 2006.173.18:04:27.47#ibcon#about to read 5, iclass 4, count 0 2006.173.18:04:27.47#ibcon#read 5, iclass 4, count 0 2006.173.18:04:27.47#ibcon#about to read 6, iclass 4, count 0 2006.173.18:04:27.47#ibcon#read 6, iclass 4, count 0 2006.173.18:04:27.47#ibcon#end of sib2, iclass 4, count 0 2006.173.18:04:27.47#ibcon#*after write, iclass 4, count 0 2006.173.18:04:27.47#ibcon#*before return 0, iclass 4, count 0 2006.173.18:04:27.47#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.18:04:27.47#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.18:04:27.47#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.18:04:27.47#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.18:04:27.47$vck44/valo=7,864.99 2006.173.18:04:27.47#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.18:04:27.47#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.18:04:27.47#ibcon#ireg 17 cls_cnt 0 2006.173.18:04:27.47#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.18:04:27.47#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.18:04:27.47#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.18:04:27.47#ibcon#enter wrdev, iclass 6, count 0 2006.173.18:04:27.47#ibcon#first serial, iclass 6, count 0 2006.173.18:04:27.47#ibcon#enter sib2, iclass 6, count 0 2006.173.18:04:27.47#ibcon#flushed, iclass 6, count 0 2006.173.18:04:27.47#ibcon#about to write, iclass 6, count 0 2006.173.18:04:27.47#ibcon#wrote, iclass 6, count 0 2006.173.18:04:27.47#ibcon#about to read 3, iclass 6, count 0 2006.173.18:04:27.49#ibcon#read 3, iclass 6, count 0 2006.173.18:04:27.49#ibcon#about to read 4, iclass 6, count 0 2006.173.18:04:27.49#ibcon#read 4, iclass 6, count 0 2006.173.18:04:27.49#ibcon#about to read 5, iclass 6, count 0 2006.173.18:04:27.49#ibcon#read 5, iclass 6, count 0 2006.173.18:04:27.49#ibcon#about to read 6, iclass 6, count 0 2006.173.18:04:27.49#ibcon#read 6, iclass 6, count 0 2006.173.18:04:27.49#ibcon#end of sib2, iclass 6, count 0 2006.173.18:04:27.49#ibcon#*mode == 0, iclass 6, count 0 2006.173.18:04:27.49#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.18:04:27.49#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.18:04:27.49#ibcon#*before write, iclass 6, count 0 2006.173.18:04:27.49#ibcon#enter sib2, iclass 6, count 0 2006.173.18:04:27.49#ibcon#flushed, iclass 6, count 0 2006.173.18:04:27.49#ibcon#about to write, iclass 6, count 0 2006.173.18:04:27.49#ibcon#wrote, iclass 6, count 0 2006.173.18:04:27.49#ibcon#about to read 3, iclass 6, count 0 2006.173.18:04:27.53#ibcon#read 3, iclass 6, count 0 2006.173.18:04:27.53#ibcon#about to read 4, iclass 6, count 0 2006.173.18:04:27.53#ibcon#read 4, iclass 6, count 0 2006.173.18:04:27.53#ibcon#about to read 5, iclass 6, count 0 2006.173.18:04:27.53#ibcon#read 5, iclass 6, count 0 2006.173.18:04:27.53#ibcon#about to read 6, iclass 6, count 0 2006.173.18:04:27.53#ibcon#read 6, iclass 6, count 0 2006.173.18:04:27.53#ibcon#end of sib2, iclass 6, count 0 2006.173.18:04:27.53#ibcon#*after write, iclass 6, count 0 2006.173.18:04:27.53#ibcon#*before return 0, iclass 6, count 0 2006.173.18:04:27.53#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.18:04:27.53#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.18:04:27.53#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.18:04:27.53#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.18:04:27.53$vck44/va=7,4 2006.173.18:04:27.53#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.18:04:27.53#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.18:04:27.53#ibcon#ireg 11 cls_cnt 2 2006.173.18:04:27.53#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.18:04:27.59#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.18:04:27.59#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.18:04:27.59#ibcon#enter wrdev, iclass 10, count 2 2006.173.18:04:27.59#ibcon#first serial, iclass 10, count 2 2006.173.18:04:27.59#ibcon#enter sib2, iclass 10, count 2 2006.173.18:04:27.59#ibcon#flushed, iclass 10, count 2 2006.173.18:04:27.59#ibcon#about to write, iclass 10, count 2 2006.173.18:04:27.59#ibcon#wrote, iclass 10, count 2 2006.173.18:04:27.59#ibcon#about to read 3, iclass 10, count 2 2006.173.18:04:27.61#ibcon#read 3, iclass 10, count 2 2006.173.18:04:27.61#ibcon#about to read 4, iclass 10, count 2 2006.173.18:04:27.61#ibcon#read 4, iclass 10, count 2 2006.173.18:04:27.61#ibcon#about to read 5, iclass 10, count 2 2006.173.18:04:27.61#ibcon#read 5, iclass 10, count 2 2006.173.18:04:27.61#ibcon#about to read 6, iclass 10, count 2 2006.173.18:04:27.61#ibcon#read 6, iclass 10, count 2 2006.173.18:04:27.61#ibcon#end of sib2, iclass 10, count 2 2006.173.18:04:27.61#ibcon#*mode == 0, iclass 10, count 2 2006.173.18:04:27.61#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.18:04:27.61#ibcon#[25=AT07-04\r\n] 2006.173.18:04:27.61#ibcon#*before write, iclass 10, count 2 2006.173.18:04:27.61#ibcon#enter sib2, iclass 10, count 2 2006.173.18:04:27.61#ibcon#flushed, iclass 10, count 2 2006.173.18:04:27.61#ibcon#about to write, iclass 10, count 2 2006.173.18:04:27.61#ibcon#wrote, iclass 10, count 2 2006.173.18:04:27.61#ibcon#about to read 3, iclass 10, count 2 2006.173.18:04:27.64#ibcon#read 3, iclass 10, count 2 2006.173.18:04:27.64#ibcon#about to read 4, iclass 10, count 2 2006.173.18:04:27.64#ibcon#read 4, iclass 10, count 2 2006.173.18:04:27.64#ibcon#about to read 5, iclass 10, count 2 2006.173.18:04:27.64#ibcon#read 5, iclass 10, count 2 2006.173.18:04:27.64#ibcon#about to read 6, iclass 10, count 2 2006.173.18:04:27.64#ibcon#read 6, iclass 10, count 2 2006.173.18:04:27.64#ibcon#end of sib2, iclass 10, count 2 2006.173.18:04:27.64#ibcon#*after write, iclass 10, count 2 2006.173.18:04:27.64#ibcon#*before return 0, iclass 10, count 2 2006.173.18:04:27.64#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.18:04:27.64#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.18:04:27.64#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.18:04:27.64#ibcon#ireg 7 cls_cnt 0 2006.173.18:04:27.64#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.18:04:27.76#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.18:04:27.76#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.18:04:27.76#ibcon#enter wrdev, iclass 10, count 0 2006.173.18:04:27.76#ibcon#first serial, iclass 10, count 0 2006.173.18:04:27.76#ibcon#enter sib2, iclass 10, count 0 2006.173.18:04:27.76#ibcon#flushed, iclass 10, count 0 2006.173.18:04:27.76#ibcon#about to write, iclass 10, count 0 2006.173.18:04:27.76#ibcon#wrote, iclass 10, count 0 2006.173.18:04:27.76#ibcon#about to read 3, iclass 10, count 0 2006.173.18:04:27.78#ibcon#read 3, iclass 10, count 0 2006.173.18:04:27.78#ibcon#about to read 4, iclass 10, count 0 2006.173.18:04:27.78#ibcon#read 4, iclass 10, count 0 2006.173.18:04:27.78#ibcon#about to read 5, iclass 10, count 0 2006.173.18:04:27.78#ibcon#read 5, iclass 10, count 0 2006.173.18:04:27.78#ibcon#about to read 6, iclass 10, count 0 2006.173.18:04:27.78#ibcon#read 6, iclass 10, count 0 2006.173.18:04:27.78#ibcon#end of sib2, iclass 10, count 0 2006.173.18:04:27.78#ibcon#*mode == 0, iclass 10, count 0 2006.173.18:04:27.78#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.18:04:27.78#ibcon#[25=USB\r\n] 2006.173.18:04:27.78#ibcon#*before write, iclass 10, count 0 2006.173.18:04:27.78#ibcon#enter sib2, iclass 10, count 0 2006.173.18:04:27.78#ibcon#flushed, iclass 10, count 0 2006.173.18:04:27.78#ibcon#about to write, iclass 10, count 0 2006.173.18:04:27.78#ibcon#wrote, iclass 10, count 0 2006.173.18:04:27.78#ibcon#about to read 3, iclass 10, count 0 2006.173.18:04:27.81#ibcon#read 3, iclass 10, count 0 2006.173.18:04:27.81#ibcon#about to read 4, iclass 10, count 0 2006.173.18:04:27.81#ibcon#read 4, iclass 10, count 0 2006.173.18:04:27.81#ibcon#about to read 5, iclass 10, count 0 2006.173.18:04:27.81#ibcon#read 5, iclass 10, count 0 2006.173.18:04:27.81#ibcon#about to read 6, iclass 10, count 0 2006.173.18:04:27.81#ibcon#read 6, iclass 10, count 0 2006.173.18:04:27.81#ibcon#end of sib2, iclass 10, count 0 2006.173.18:04:27.81#ibcon#*after write, iclass 10, count 0 2006.173.18:04:27.81#ibcon#*before return 0, iclass 10, count 0 2006.173.18:04:27.81#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.18:04:27.81#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.18:04:27.81#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.18:04:27.81#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.18:04:27.81$vck44/valo=8,884.99 2006.173.18:04:27.81#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.18:04:27.81#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.18:04:27.81#ibcon#ireg 17 cls_cnt 0 2006.173.18:04:27.81#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.18:04:27.81#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.18:04:27.81#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.18:04:27.81#ibcon#enter wrdev, iclass 12, count 0 2006.173.18:04:27.81#ibcon#first serial, iclass 12, count 0 2006.173.18:04:27.81#ibcon#enter sib2, iclass 12, count 0 2006.173.18:04:27.81#ibcon#flushed, iclass 12, count 0 2006.173.18:04:27.81#ibcon#about to write, iclass 12, count 0 2006.173.18:04:27.81#ibcon#wrote, iclass 12, count 0 2006.173.18:04:27.81#ibcon#about to read 3, iclass 12, count 0 2006.173.18:04:27.83#ibcon#read 3, iclass 12, count 0 2006.173.18:04:27.83#ibcon#about to read 4, iclass 12, count 0 2006.173.18:04:27.83#ibcon#read 4, iclass 12, count 0 2006.173.18:04:27.83#ibcon#about to read 5, iclass 12, count 0 2006.173.18:04:27.83#ibcon#read 5, iclass 12, count 0 2006.173.18:04:27.83#ibcon#about to read 6, iclass 12, count 0 2006.173.18:04:27.83#ibcon#read 6, iclass 12, count 0 2006.173.18:04:27.83#ibcon#end of sib2, iclass 12, count 0 2006.173.18:04:27.83#ibcon#*mode == 0, iclass 12, count 0 2006.173.18:04:27.83#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.18:04:27.83#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.18:04:27.83#ibcon#*before write, iclass 12, count 0 2006.173.18:04:27.83#ibcon#enter sib2, iclass 12, count 0 2006.173.18:04:27.83#ibcon#flushed, iclass 12, count 0 2006.173.18:04:27.83#ibcon#about to write, iclass 12, count 0 2006.173.18:04:27.83#ibcon#wrote, iclass 12, count 0 2006.173.18:04:27.83#ibcon#about to read 3, iclass 12, count 0 2006.173.18:04:27.87#ibcon#read 3, iclass 12, count 0 2006.173.18:04:27.87#ibcon#about to read 4, iclass 12, count 0 2006.173.18:04:27.87#ibcon#read 4, iclass 12, count 0 2006.173.18:04:27.87#ibcon#about to read 5, iclass 12, count 0 2006.173.18:04:27.87#ibcon#read 5, iclass 12, count 0 2006.173.18:04:27.87#ibcon#about to read 6, iclass 12, count 0 2006.173.18:04:27.87#ibcon#read 6, iclass 12, count 0 2006.173.18:04:27.87#ibcon#end of sib2, iclass 12, count 0 2006.173.18:04:27.87#ibcon#*after write, iclass 12, count 0 2006.173.18:04:27.87#ibcon#*before return 0, iclass 12, count 0 2006.173.18:04:27.87#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.18:04:27.87#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.18:04:27.87#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.18:04:27.87#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.18:04:27.87$vck44/va=8,4 2006.173.18:04:27.87#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.18:04:27.87#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.18:04:27.87#ibcon#ireg 11 cls_cnt 2 2006.173.18:04:27.87#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.18:04:27.93#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.18:04:27.93#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.18:04:27.93#ibcon#enter wrdev, iclass 14, count 2 2006.173.18:04:27.93#ibcon#first serial, iclass 14, count 2 2006.173.18:04:27.93#ibcon#enter sib2, iclass 14, count 2 2006.173.18:04:27.93#ibcon#flushed, iclass 14, count 2 2006.173.18:04:27.93#ibcon#about to write, iclass 14, count 2 2006.173.18:04:27.93#ibcon#wrote, iclass 14, count 2 2006.173.18:04:27.93#ibcon#about to read 3, iclass 14, count 2 2006.173.18:04:27.95#ibcon#read 3, iclass 14, count 2 2006.173.18:04:27.95#ibcon#about to read 4, iclass 14, count 2 2006.173.18:04:27.95#ibcon#read 4, iclass 14, count 2 2006.173.18:04:27.95#ibcon#about to read 5, iclass 14, count 2 2006.173.18:04:27.95#ibcon#read 5, iclass 14, count 2 2006.173.18:04:27.95#ibcon#about to read 6, iclass 14, count 2 2006.173.18:04:27.95#ibcon#read 6, iclass 14, count 2 2006.173.18:04:27.95#ibcon#end of sib2, iclass 14, count 2 2006.173.18:04:27.95#ibcon#*mode == 0, iclass 14, count 2 2006.173.18:04:27.95#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.18:04:27.95#ibcon#[25=AT08-04\r\n] 2006.173.18:04:27.95#ibcon#*before write, iclass 14, count 2 2006.173.18:04:27.95#ibcon#enter sib2, iclass 14, count 2 2006.173.18:04:27.95#ibcon#flushed, iclass 14, count 2 2006.173.18:04:27.95#ibcon#about to write, iclass 14, count 2 2006.173.18:04:27.95#ibcon#wrote, iclass 14, count 2 2006.173.18:04:27.95#ibcon#about to read 3, iclass 14, count 2 2006.173.18:04:27.98#ibcon#read 3, iclass 14, count 2 2006.173.18:04:27.98#ibcon#about to read 4, iclass 14, count 2 2006.173.18:04:27.98#ibcon#read 4, iclass 14, count 2 2006.173.18:04:27.98#ibcon#about to read 5, iclass 14, count 2 2006.173.18:04:27.98#ibcon#read 5, iclass 14, count 2 2006.173.18:04:27.98#ibcon#about to read 6, iclass 14, count 2 2006.173.18:04:27.98#ibcon#read 6, iclass 14, count 2 2006.173.18:04:27.98#ibcon#end of sib2, iclass 14, count 2 2006.173.18:04:27.98#ibcon#*after write, iclass 14, count 2 2006.173.18:04:27.98#ibcon#*before return 0, iclass 14, count 2 2006.173.18:04:27.98#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.18:04:27.98#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.18:04:27.98#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.18:04:27.98#ibcon#ireg 7 cls_cnt 0 2006.173.18:04:27.98#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.18:04:28.10#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.18:04:28.10#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.18:04:28.10#ibcon#enter wrdev, iclass 14, count 0 2006.173.18:04:28.10#ibcon#first serial, iclass 14, count 0 2006.173.18:04:28.10#ibcon#enter sib2, iclass 14, count 0 2006.173.18:04:28.10#ibcon#flushed, iclass 14, count 0 2006.173.18:04:28.10#ibcon#about to write, iclass 14, count 0 2006.173.18:04:28.10#ibcon#wrote, iclass 14, count 0 2006.173.18:04:28.10#ibcon#about to read 3, iclass 14, count 0 2006.173.18:04:28.12#ibcon#read 3, iclass 14, count 0 2006.173.18:04:28.12#ibcon#about to read 4, iclass 14, count 0 2006.173.18:04:28.12#ibcon#read 4, iclass 14, count 0 2006.173.18:04:28.12#ibcon#about to read 5, iclass 14, count 0 2006.173.18:04:28.12#ibcon#read 5, iclass 14, count 0 2006.173.18:04:28.12#ibcon#about to read 6, iclass 14, count 0 2006.173.18:04:28.12#ibcon#read 6, iclass 14, count 0 2006.173.18:04:28.12#ibcon#end of sib2, iclass 14, count 0 2006.173.18:04:28.12#ibcon#*mode == 0, iclass 14, count 0 2006.173.18:04:28.12#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.18:04:28.12#ibcon#[25=USB\r\n] 2006.173.18:04:28.12#ibcon#*before write, iclass 14, count 0 2006.173.18:04:28.12#ibcon#enter sib2, iclass 14, count 0 2006.173.18:04:28.12#ibcon#flushed, iclass 14, count 0 2006.173.18:04:28.12#ibcon#about to write, iclass 14, count 0 2006.173.18:04:28.12#ibcon#wrote, iclass 14, count 0 2006.173.18:04:28.12#ibcon#about to read 3, iclass 14, count 0 2006.173.18:04:28.15#ibcon#read 3, iclass 14, count 0 2006.173.18:04:28.15#ibcon#about to read 4, iclass 14, count 0 2006.173.18:04:28.15#ibcon#read 4, iclass 14, count 0 2006.173.18:04:28.15#ibcon#about to read 5, iclass 14, count 0 2006.173.18:04:28.15#ibcon#read 5, iclass 14, count 0 2006.173.18:04:28.15#ibcon#about to read 6, iclass 14, count 0 2006.173.18:04:28.15#ibcon#read 6, iclass 14, count 0 2006.173.18:04:28.15#ibcon#end of sib2, iclass 14, count 0 2006.173.18:04:28.15#ibcon#*after write, iclass 14, count 0 2006.173.18:04:28.15#ibcon#*before return 0, iclass 14, count 0 2006.173.18:04:28.15#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.18:04:28.15#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.18:04:28.15#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.18:04:28.15#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.18:04:28.15$vck44/vblo=1,629.99 2006.173.18:04:28.15#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.18:04:28.15#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.18:04:28.15#ibcon#ireg 17 cls_cnt 0 2006.173.18:04:28.15#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.18:04:28.15#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.18:04:28.15#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.18:04:28.15#ibcon#enter wrdev, iclass 16, count 0 2006.173.18:04:28.15#ibcon#first serial, iclass 16, count 0 2006.173.18:04:28.15#ibcon#enter sib2, iclass 16, count 0 2006.173.18:04:28.15#ibcon#flushed, iclass 16, count 0 2006.173.18:04:28.15#ibcon#about to write, iclass 16, count 0 2006.173.18:04:28.15#ibcon#wrote, iclass 16, count 0 2006.173.18:04:28.15#ibcon#about to read 3, iclass 16, count 0 2006.173.18:04:28.17#ibcon#read 3, iclass 16, count 0 2006.173.18:04:28.17#ibcon#about to read 4, iclass 16, count 0 2006.173.18:04:28.17#ibcon#read 4, iclass 16, count 0 2006.173.18:04:28.17#ibcon#about to read 5, iclass 16, count 0 2006.173.18:04:28.17#ibcon#read 5, iclass 16, count 0 2006.173.18:04:28.17#ibcon#about to read 6, iclass 16, count 0 2006.173.18:04:28.17#ibcon#read 6, iclass 16, count 0 2006.173.18:04:28.17#ibcon#end of sib2, iclass 16, count 0 2006.173.18:04:28.17#ibcon#*mode == 0, iclass 16, count 0 2006.173.18:04:28.17#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.18:04:28.17#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.18:04:28.17#ibcon#*before write, iclass 16, count 0 2006.173.18:04:28.17#ibcon#enter sib2, iclass 16, count 0 2006.173.18:04:28.17#ibcon#flushed, iclass 16, count 0 2006.173.18:04:28.17#ibcon#about to write, iclass 16, count 0 2006.173.18:04:28.17#ibcon#wrote, iclass 16, count 0 2006.173.18:04:28.17#ibcon#about to read 3, iclass 16, count 0 2006.173.18:04:28.21#ibcon#read 3, iclass 16, count 0 2006.173.18:04:28.21#ibcon#about to read 4, iclass 16, count 0 2006.173.18:04:28.21#ibcon#read 4, iclass 16, count 0 2006.173.18:04:28.21#ibcon#about to read 5, iclass 16, count 0 2006.173.18:04:28.21#ibcon#read 5, iclass 16, count 0 2006.173.18:04:28.21#ibcon#about to read 6, iclass 16, count 0 2006.173.18:04:28.21#ibcon#read 6, iclass 16, count 0 2006.173.18:04:28.21#ibcon#end of sib2, iclass 16, count 0 2006.173.18:04:28.21#ibcon#*after write, iclass 16, count 0 2006.173.18:04:28.21#ibcon#*before return 0, iclass 16, count 0 2006.173.18:04:28.21#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.18:04:28.21#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.18:04:28.21#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.18:04:28.21#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.18:04:28.21$vck44/vb=1,4 2006.173.18:04:28.21#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.18:04:28.21#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.18:04:28.21#ibcon#ireg 11 cls_cnt 2 2006.173.18:04:28.21#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.18:04:28.21#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.18:04:28.21#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.18:04:28.21#ibcon#enter wrdev, iclass 18, count 2 2006.173.18:04:28.21#ibcon#first serial, iclass 18, count 2 2006.173.18:04:28.21#ibcon#enter sib2, iclass 18, count 2 2006.173.18:04:28.21#ibcon#flushed, iclass 18, count 2 2006.173.18:04:28.21#ibcon#about to write, iclass 18, count 2 2006.173.18:04:28.21#ibcon#wrote, iclass 18, count 2 2006.173.18:04:28.21#ibcon#about to read 3, iclass 18, count 2 2006.173.18:04:28.23#ibcon#read 3, iclass 18, count 2 2006.173.18:04:28.23#ibcon#about to read 4, iclass 18, count 2 2006.173.18:04:28.23#ibcon#read 4, iclass 18, count 2 2006.173.18:04:28.23#ibcon#about to read 5, iclass 18, count 2 2006.173.18:04:28.23#ibcon#read 5, iclass 18, count 2 2006.173.18:04:28.23#ibcon#about to read 6, iclass 18, count 2 2006.173.18:04:28.23#ibcon#read 6, iclass 18, count 2 2006.173.18:04:28.23#ibcon#end of sib2, iclass 18, count 2 2006.173.18:04:28.23#ibcon#*mode == 0, iclass 18, count 2 2006.173.18:04:28.23#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.18:04:28.23#ibcon#[27=AT01-04\r\n] 2006.173.18:04:28.23#ibcon#*before write, iclass 18, count 2 2006.173.18:04:28.23#ibcon#enter sib2, iclass 18, count 2 2006.173.18:04:28.23#ibcon#flushed, iclass 18, count 2 2006.173.18:04:28.23#ibcon#about to write, iclass 18, count 2 2006.173.18:04:28.23#ibcon#wrote, iclass 18, count 2 2006.173.18:04:28.23#ibcon#about to read 3, iclass 18, count 2 2006.173.18:04:28.26#ibcon#read 3, iclass 18, count 2 2006.173.18:04:28.26#ibcon#about to read 4, iclass 18, count 2 2006.173.18:04:28.26#ibcon#read 4, iclass 18, count 2 2006.173.18:04:28.26#ibcon#about to read 5, iclass 18, count 2 2006.173.18:04:28.26#ibcon#read 5, iclass 18, count 2 2006.173.18:04:28.26#ibcon#about to read 6, iclass 18, count 2 2006.173.18:04:28.26#ibcon#read 6, iclass 18, count 2 2006.173.18:04:28.26#ibcon#end of sib2, iclass 18, count 2 2006.173.18:04:28.26#ibcon#*after write, iclass 18, count 2 2006.173.18:04:28.26#ibcon#*before return 0, iclass 18, count 2 2006.173.18:04:28.26#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.18:04:28.26#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.18:04:28.26#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.18:04:28.26#ibcon#ireg 7 cls_cnt 0 2006.173.18:04:28.26#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.18:04:28.38#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.18:04:28.38#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.18:04:28.38#ibcon#enter wrdev, iclass 18, count 0 2006.173.18:04:28.38#ibcon#first serial, iclass 18, count 0 2006.173.18:04:28.38#ibcon#enter sib2, iclass 18, count 0 2006.173.18:04:28.38#ibcon#flushed, iclass 18, count 0 2006.173.18:04:28.38#ibcon#about to write, iclass 18, count 0 2006.173.18:04:28.38#ibcon#wrote, iclass 18, count 0 2006.173.18:04:28.38#ibcon#about to read 3, iclass 18, count 0 2006.173.18:04:28.40#ibcon#read 3, iclass 18, count 0 2006.173.18:04:28.40#ibcon#about to read 4, iclass 18, count 0 2006.173.18:04:28.40#ibcon#read 4, iclass 18, count 0 2006.173.18:04:28.40#ibcon#about to read 5, iclass 18, count 0 2006.173.18:04:28.40#ibcon#read 5, iclass 18, count 0 2006.173.18:04:28.40#ibcon#about to read 6, iclass 18, count 0 2006.173.18:04:28.40#ibcon#read 6, iclass 18, count 0 2006.173.18:04:28.40#ibcon#end of sib2, iclass 18, count 0 2006.173.18:04:28.40#ibcon#*mode == 0, iclass 18, count 0 2006.173.18:04:28.40#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.18:04:28.40#ibcon#[27=USB\r\n] 2006.173.18:04:28.40#ibcon#*before write, iclass 18, count 0 2006.173.18:04:28.40#ibcon#enter sib2, iclass 18, count 0 2006.173.18:04:28.40#ibcon#flushed, iclass 18, count 0 2006.173.18:04:28.40#ibcon#about to write, iclass 18, count 0 2006.173.18:04:28.40#ibcon#wrote, iclass 18, count 0 2006.173.18:04:28.40#ibcon#about to read 3, iclass 18, count 0 2006.173.18:04:28.43#ibcon#read 3, iclass 18, count 0 2006.173.18:04:28.43#ibcon#about to read 4, iclass 18, count 0 2006.173.18:04:28.43#ibcon#read 4, iclass 18, count 0 2006.173.18:04:28.43#ibcon#about to read 5, iclass 18, count 0 2006.173.18:04:28.43#ibcon#read 5, iclass 18, count 0 2006.173.18:04:28.43#ibcon#about to read 6, iclass 18, count 0 2006.173.18:04:28.43#ibcon#read 6, iclass 18, count 0 2006.173.18:04:28.43#ibcon#end of sib2, iclass 18, count 0 2006.173.18:04:28.43#ibcon#*after write, iclass 18, count 0 2006.173.18:04:28.43#ibcon#*before return 0, iclass 18, count 0 2006.173.18:04:28.43#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.18:04:28.43#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.18:04:28.43#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.18:04:28.43#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.18:04:28.43$vck44/vblo=2,634.99 2006.173.18:04:28.43#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.18:04:28.43#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.18:04:28.43#ibcon#ireg 17 cls_cnt 0 2006.173.18:04:28.43#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.18:04:28.43#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.18:04:28.43#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.18:04:28.43#ibcon#enter wrdev, iclass 20, count 0 2006.173.18:04:28.43#ibcon#first serial, iclass 20, count 0 2006.173.18:04:28.43#ibcon#enter sib2, iclass 20, count 0 2006.173.18:04:28.43#ibcon#flushed, iclass 20, count 0 2006.173.18:04:28.43#ibcon#about to write, iclass 20, count 0 2006.173.18:04:28.43#ibcon#wrote, iclass 20, count 0 2006.173.18:04:28.43#ibcon#about to read 3, iclass 20, count 0 2006.173.18:04:28.45#ibcon#read 3, iclass 20, count 0 2006.173.18:04:28.45#ibcon#about to read 4, iclass 20, count 0 2006.173.18:04:28.45#ibcon#read 4, iclass 20, count 0 2006.173.18:04:28.45#ibcon#about to read 5, iclass 20, count 0 2006.173.18:04:28.45#ibcon#read 5, iclass 20, count 0 2006.173.18:04:28.45#ibcon#about to read 6, iclass 20, count 0 2006.173.18:04:28.45#ibcon#read 6, iclass 20, count 0 2006.173.18:04:28.45#ibcon#end of sib2, iclass 20, count 0 2006.173.18:04:28.45#ibcon#*mode == 0, iclass 20, count 0 2006.173.18:04:28.45#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.18:04:28.45#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.18:04:28.45#ibcon#*before write, iclass 20, count 0 2006.173.18:04:28.45#ibcon#enter sib2, iclass 20, count 0 2006.173.18:04:28.45#ibcon#flushed, iclass 20, count 0 2006.173.18:04:28.45#ibcon#about to write, iclass 20, count 0 2006.173.18:04:28.45#ibcon#wrote, iclass 20, count 0 2006.173.18:04:28.45#ibcon#about to read 3, iclass 20, count 0 2006.173.18:04:28.49#ibcon#read 3, iclass 20, count 0 2006.173.18:04:28.49#ibcon#about to read 4, iclass 20, count 0 2006.173.18:04:28.49#ibcon#read 4, iclass 20, count 0 2006.173.18:04:28.49#ibcon#about to read 5, iclass 20, count 0 2006.173.18:04:28.49#ibcon#read 5, iclass 20, count 0 2006.173.18:04:28.49#ibcon#about to read 6, iclass 20, count 0 2006.173.18:04:28.49#ibcon#read 6, iclass 20, count 0 2006.173.18:04:28.49#ibcon#end of sib2, iclass 20, count 0 2006.173.18:04:28.49#ibcon#*after write, iclass 20, count 0 2006.173.18:04:28.49#ibcon#*before return 0, iclass 20, count 0 2006.173.18:04:28.49#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.18:04:28.49#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.18:04:28.49#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.18:04:28.49#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.18:04:28.49$vck44/vb=2,4 2006.173.18:04:28.49#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.18:04:28.49#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.18:04:28.49#ibcon#ireg 11 cls_cnt 2 2006.173.18:04:28.49#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.18:04:28.55#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.18:04:28.55#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.18:04:28.55#ibcon#enter wrdev, iclass 22, count 2 2006.173.18:04:28.55#ibcon#first serial, iclass 22, count 2 2006.173.18:04:28.55#ibcon#enter sib2, iclass 22, count 2 2006.173.18:04:28.55#ibcon#flushed, iclass 22, count 2 2006.173.18:04:28.55#ibcon#about to write, iclass 22, count 2 2006.173.18:04:28.55#ibcon#wrote, iclass 22, count 2 2006.173.18:04:28.55#ibcon#about to read 3, iclass 22, count 2 2006.173.18:04:28.57#ibcon#read 3, iclass 22, count 2 2006.173.18:04:28.57#ibcon#about to read 4, iclass 22, count 2 2006.173.18:04:28.57#ibcon#read 4, iclass 22, count 2 2006.173.18:04:28.57#ibcon#about to read 5, iclass 22, count 2 2006.173.18:04:28.57#ibcon#read 5, iclass 22, count 2 2006.173.18:04:28.57#ibcon#about to read 6, iclass 22, count 2 2006.173.18:04:28.57#ibcon#read 6, iclass 22, count 2 2006.173.18:04:28.57#ibcon#end of sib2, iclass 22, count 2 2006.173.18:04:28.57#ibcon#*mode == 0, iclass 22, count 2 2006.173.18:04:28.57#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.18:04:28.57#ibcon#[27=AT02-04\r\n] 2006.173.18:04:28.57#ibcon#*before write, iclass 22, count 2 2006.173.18:04:28.57#ibcon#enter sib2, iclass 22, count 2 2006.173.18:04:28.57#ibcon#flushed, iclass 22, count 2 2006.173.18:04:28.57#ibcon#about to write, iclass 22, count 2 2006.173.18:04:28.57#ibcon#wrote, iclass 22, count 2 2006.173.18:04:28.57#ibcon#about to read 3, iclass 22, count 2 2006.173.18:04:28.60#ibcon#read 3, iclass 22, count 2 2006.173.18:04:28.60#ibcon#about to read 4, iclass 22, count 2 2006.173.18:04:28.60#ibcon#read 4, iclass 22, count 2 2006.173.18:04:28.60#ibcon#about to read 5, iclass 22, count 2 2006.173.18:04:28.60#ibcon#read 5, iclass 22, count 2 2006.173.18:04:28.60#ibcon#about to read 6, iclass 22, count 2 2006.173.18:04:28.60#ibcon#read 6, iclass 22, count 2 2006.173.18:04:28.60#ibcon#end of sib2, iclass 22, count 2 2006.173.18:04:28.60#ibcon#*after write, iclass 22, count 2 2006.173.18:04:28.60#ibcon#*before return 0, iclass 22, count 2 2006.173.18:04:28.60#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.18:04:28.60#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.18:04:28.60#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.18:04:28.60#ibcon#ireg 7 cls_cnt 0 2006.173.18:04:28.60#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.18:04:28.72#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.18:04:28.72#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.18:04:28.72#ibcon#enter wrdev, iclass 22, count 0 2006.173.18:04:28.72#ibcon#first serial, iclass 22, count 0 2006.173.18:04:28.72#ibcon#enter sib2, iclass 22, count 0 2006.173.18:04:28.72#ibcon#flushed, iclass 22, count 0 2006.173.18:04:28.72#ibcon#about to write, iclass 22, count 0 2006.173.18:04:28.72#ibcon#wrote, iclass 22, count 0 2006.173.18:04:28.72#ibcon#about to read 3, iclass 22, count 0 2006.173.18:04:28.74#ibcon#read 3, iclass 22, count 0 2006.173.18:04:28.74#ibcon#about to read 4, iclass 22, count 0 2006.173.18:04:28.74#ibcon#read 4, iclass 22, count 0 2006.173.18:04:28.74#ibcon#about to read 5, iclass 22, count 0 2006.173.18:04:28.74#ibcon#read 5, iclass 22, count 0 2006.173.18:04:28.74#ibcon#about to read 6, iclass 22, count 0 2006.173.18:04:28.74#ibcon#read 6, iclass 22, count 0 2006.173.18:04:28.74#ibcon#end of sib2, iclass 22, count 0 2006.173.18:04:28.74#ibcon#*mode == 0, iclass 22, count 0 2006.173.18:04:28.74#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.18:04:28.74#ibcon#[27=USB\r\n] 2006.173.18:04:28.74#ibcon#*before write, iclass 22, count 0 2006.173.18:04:28.74#ibcon#enter sib2, iclass 22, count 0 2006.173.18:04:28.74#ibcon#flushed, iclass 22, count 0 2006.173.18:04:28.74#ibcon#about to write, iclass 22, count 0 2006.173.18:04:28.74#ibcon#wrote, iclass 22, count 0 2006.173.18:04:28.74#ibcon#about to read 3, iclass 22, count 0 2006.173.18:04:28.77#ibcon#read 3, iclass 22, count 0 2006.173.18:04:28.77#ibcon#about to read 4, iclass 22, count 0 2006.173.18:04:28.77#ibcon#read 4, iclass 22, count 0 2006.173.18:04:28.77#ibcon#about to read 5, iclass 22, count 0 2006.173.18:04:28.77#ibcon#read 5, iclass 22, count 0 2006.173.18:04:28.77#ibcon#about to read 6, iclass 22, count 0 2006.173.18:04:28.77#ibcon#read 6, iclass 22, count 0 2006.173.18:04:28.77#ibcon#end of sib2, iclass 22, count 0 2006.173.18:04:28.77#ibcon#*after write, iclass 22, count 0 2006.173.18:04:28.77#ibcon#*before return 0, iclass 22, count 0 2006.173.18:04:28.77#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.18:04:28.77#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.18:04:28.77#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.18:04:28.77#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.18:04:28.77$vck44/vblo=3,649.99 2006.173.18:04:28.77#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.18:04:28.77#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.18:04:28.77#ibcon#ireg 17 cls_cnt 0 2006.173.18:04:28.77#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.18:04:28.77#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.18:04:28.77#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.18:04:28.77#ibcon#enter wrdev, iclass 24, count 0 2006.173.18:04:28.77#ibcon#first serial, iclass 24, count 0 2006.173.18:04:28.77#ibcon#enter sib2, iclass 24, count 0 2006.173.18:04:28.77#ibcon#flushed, iclass 24, count 0 2006.173.18:04:28.77#ibcon#about to write, iclass 24, count 0 2006.173.18:04:28.77#ibcon#wrote, iclass 24, count 0 2006.173.18:04:28.77#ibcon#about to read 3, iclass 24, count 0 2006.173.18:04:28.79#ibcon#read 3, iclass 24, count 0 2006.173.18:04:28.79#ibcon#about to read 4, iclass 24, count 0 2006.173.18:04:28.79#ibcon#read 4, iclass 24, count 0 2006.173.18:04:28.79#ibcon#about to read 5, iclass 24, count 0 2006.173.18:04:28.79#ibcon#read 5, iclass 24, count 0 2006.173.18:04:28.79#ibcon#about to read 6, iclass 24, count 0 2006.173.18:04:28.79#ibcon#read 6, iclass 24, count 0 2006.173.18:04:28.79#ibcon#end of sib2, iclass 24, count 0 2006.173.18:04:28.79#ibcon#*mode == 0, iclass 24, count 0 2006.173.18:04:28.79#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.18:04:28.79#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.18:04:28.79#ibcon#*before write, iclass 24, count 0 2006.173.18:04:28.79#ibcon#enter sib2, iclass 24, count 0 2006.173.18:04:28.79#ibcon#flushed, iclass 24, count 0 2006.173.18:04:28.79#ibcon#about to write, iclass 24, count 0 2006.173.18:04:28.79#ibcon#wrote, iclass 24, count 0 2006.173.18:04:28.79#ibcon#about to read 3, iclass 24, count 0 2006.173.18:04:28.83#ibcon#read 3, iclass 24, count 0 2006.173.18:04:28.83#ibcon#about to read 4, iclass 24, count 0 2006.173.18:04:28.83#ibcon#read 4, iclass 24, count 0 2006.173.18:04:28.83#ibcon#about to read 5, iclass 24, count 0 2006.173.18:04:28.83#ibcon#read 5, iclass 24, count 0 2006.173.18:04:28.83#ibcon#about to read 6, iclass 24, count 0 2006.173.18:04:28.83#ibcon#read 6, iclass 24, count 0 2006.173.18:04:28.83#ibcon#end of sib2, iclass 24, count 0 2006.173.18:04:28.83#ibcon#*after write, iclass 24, count 0 2006.173.18:04:28.83#ibcon#*before return 0, iclass 24, count 0 2006.173.18:04:28.83#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.18:04:28.83#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.18:04:28.83#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.18:04:28.83#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.18:04:28.83$vck44/vb=3,4 2006.173.18:04:28.83#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.18:04:28.83#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.18:04:28.83#ibcon#ireg 11 cls_cnt 2 2006.173.18:04:28.83#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.18:04:28.89#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.18:04:28.89#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.18:04:28.89#ibcon#enter wrdev, iclass 26, count 2 2006.173.18:04:28.89#ibcon#first serial, iclass 26, count 2 2006.173.18:04:28.89#ibcon#enter sib2, iclass 26, count 2 2006.173.18:04:28.89#ibcon#flushed, iclass 26, count 2 2006.173.18:04:28.89#ibcon#about to write, iclass 26, count 2 2006.173.18:04:28.89#ibcon#wrote, iclass 26, count 2 2006.173.18:04:28.89#ibcon#about to read 3, iclass 26, count 2 2006.173.18:04:28.91#ibcon#read 3, iclass 26, count 2 2006.173.18:04:28.91#ibcon#about to read 4, iclass 26, count 2 2006.173.18:04:28.91#ibcon#read 4, iclass 26, count 2 2006.173.18:04:28.91#ibcon#about to read 5, iclass 26, count 2 2006.173.18:04:28.91#ibcon#read 5, iclass 26, count 2 2006.173.18:04:28.91#ibcon#about to read 6, iclass 26, count 2 2006.173.18:04:28.91#ibcon#read 6, iclass 26, count 2 2006.173.18:04:28.91#ibcon#end of sib2, iclass 26, count 2 2006.173.18:04:28.91#ibcon#*mode == 0, iclass 26, count 2 2006.173.18:04:28.91#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.18:04:28.91#ibcon#[27=AT03-04\r\n] 2006.173.18:04:28.91#ibcon#*before write, iclass 26, count 2 2006.173.18:04:28.91#ibcon#enter sib2, iclass 26, count 2 2006.173.18:04:28.91#ibcon#flushed, iclass 26, count 2 2006.173.18:04:28.91#ibcon#about to write, iclass 26, count 2 2006.173.18:04:28.91#ibcon#wrote, iclass 26, count 2 2006.173.18:04:28.91#ibcon#about to read 3, iclass 26, count 2 2006.173.18:04:28.94#ibcon#read 3, iclass 26, count 2 2006.173.18:04:28.94#ibcon#about to read 4, iclass 26, count 2 2006.173.18:04:28.94#ibcon#read 4, iclass 26, count 2 2006.173.18:04:28.94#ibcon#about to read 5, iclass 26, count 2 2006.173.18:04:28.94#ibcon#read 5, iclass 26, count 2 2006.173.18:04:28.94#ibcon#about to read 6, iclass 26, count 2 2006.173.18:04:28.94#ibcon#read 6, iclass 26, count 2 2006.173.18:04:28.94#ibcon#end of sib2, iclass 26, count 2 2006.173.18:04:28.94#ibcon#*after write, iclass 26, count 2 2006.173.18:04:28.94#ibcon#*before return 0, iclass 26, count 2 2006.173.18:04:28.94#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.18:04:28.94#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.18:04:28.94#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.18:04:28.94#ibcon#ireg 7 cls_cnt 0 2006.173.18:04:28.94#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.18:04:29.06#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.18:04:29.06#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.18:04:29.06#ibcon#enter wrdev, iclass 26, count 0 2006.173.18:04:29.06#ibcon#first serial, iclass 26, count 0 2006.173.18:04:29.06#ibcon#enter sib2, iclass 26, count 0 2006.173.18:04:29.06#ibcon#flushed, iclass 26, count 0 2006.173.18:04:29.06#ibcon#about to write, iclass 26, count 0 2006.173.18:04:29.06#ibcon#wrote, iclass 26, count 0 2006.173.18:04:29.06#ibcon#about to read 3, iclass 26, count 0 2006.173.18:04:29.08#ibcon#read 3, iclass 26, count 0 2006.173.18:04:29.08#ibcon#about to read 4, iclass 26, count 0 2006.173.18:04:29.08#ibcon#read 4, iclass 26, count 0 2006.173.18:04:29.08#ibcon#about to read 5, iclass 26, count 0 2006.173.18:04:29.08#ibcon#read 5, iclass 26, count 0 2006.173.18:04:29.08#ibcon#about to read 6, iclass 26, count 0 2006.173.18:04:29.08#ibcon#read 6, iclass 26, count 0 2006.173.18:04:29.08#ibcon#end of sib2, iclass 26, count 0 2006.173.18:04:29.08#ibcon#*mode == 0, iclass 26, count 0 2006.173.18:04:29.08#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.18:04:29.08#ibcon#[27=USB\r\n] 2006.173.18:04:29.08#ibcon#*before write, iclass 26, count 0 2006.173.18:04:29.08#ibcon#enter sib2, iclass 26, count 0 2006.173.18:04:29.08#ibcon#flushed, iclass 26, count 0 2006.173.18:04:29.08#ibcon#about to write, iclass 26, count 0 2006.173.18:04:29.08#ibcon#wrote, iclass 26, count 0 2006.173.18:04:29.08#ibcon#about to read 3, iclass 26, count 0 2006.173.18:04:29.11#ibcon#read 3, iclass 26, count 0 2006.173.18:04:29.11#ibcon#about to read 4, iclass 26, count 0 2006.173.18:04:29.11#ibcon#read 4, iclass 26, count 0 2006.173.18:04:29.11#ibcon#about to read 5, iclass 26, count 0 2006.173.18:04:29.11#ibcon#read 5, iclass 26, count 0 2006.173.18:04:29.11#ibcon#about to read 6, iclass 26, count 0 2006.173.18:04:29.11#ibcon#read 6, iclass 26, count 0 2006.173.18:04:29.11#ibcon#end of sib2, iclass 26, count 0 2006.173.18:04:29.11#ibcon#*after write, iclass 26, count 0 2006.173.18:04:29.11#ibcon#*before return 0, iclass 26, count 0 2006.173.18:04:29.11#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.18:04:29.11#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.18:04:29.11#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.18:04:29.11#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.18:04:29.11$vck44/vblo=4,679.99 2006.173.18:04:29.11#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.18:04:29.11#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.18:04:29.11#ibcon#ireg 17 cls_cnt 0 2006.173.18:04:29.11#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.18:04:29.11#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.18:04:29.11#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.18:04:29.11#ibcon#enter wrdev, iclass 28, count 0 2006.173.18:04:29.11#ibcon#first serial, iclass 28, count 0 2006.173.18:04:29.11#ibcon#enter sib2, iclass 28, count 0 2006.173.18:04:29.11#ibcon#flushed, iclass 28, count 0 2006.173.18:04:29.11#ibcon#about to write, iclass 28, count 0 2006.173.18:04:29.11#ibcon#wrote, iclass 28, count 0 2006.173.18:04:29.11#ibcon#about to read 3, iclass 28, count 0 2006.173.18:04:29.13#ibcon#read 3, iclass 28, count 0 2006.173.18:04:29.13#ibcon#about to read 4, iclass 28, count 0 2006.173.18:04:29.13#ibcon#read 4, iclass 28, count 0 2006.173.18:04:29.13#ibcon#about to read 5, iclass 28, count 0 2006.173.18:04:29.13#ibcon#read 5, iclass 28, count 0 2006.173.18:04:29.13#ibcon#about to read 6, iclass 28, count 0 2006.173.18:04:29.13#ibcon#read 6, iclass 28, count 0 2006.173.18:04:29.13#ibcon#end of sib2, iclass 28, count 0 2006.173.18:04:29.13#ibcon#*mode == 0, iclass 28, count 0 2006.173.18:04:29.13#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.18:04:29.13#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.18:04:29.13#ibcon#*before write, iclass 28, count 0 2006.173.18:04:29.13#ibcon#enter sib2, iclass 28, count 0 2006.173.18:04:29.13#ibcon#flushed, iclass 28, count 0 2006.173.18:04:29.13#ibcon#about to write, iclass 28, count 0 2006.173.18:04:29.13#ibcon#wrote, iclass 28, count 0 2006.173.18:04:29.13#ibcon#about to read 3, iclass 28, count 0 2006.173.18:04:29.17#ibcon#read 3, iclass 28, count 0 2006.173.18:04:29.17#ibcon#about to read 4, iclass 28, count 0 2006.173.18:04:29.17#ibcon#read 4, iclass 28, count 0 2006.173.18:04:29.17#ibcon#about to read 5, iclass 28, count 0 2006.173.18:04:29.17#ibcon#read 5, iclass 28, count 0 2006.173.18:04:29.17#ibcon#about to read 6, iclass 28, count 0 2006.173.18:04:29.17#ibcon#read 6, iclass 28, count 0 2006.173.18:04:29.17#ibcon#end of sib2, iclass 28, count 0 2006.173.18:04:29.17#ibcon#*after write, iclass 28, count 0 2006.173.18:04:29.17#ibcon#*before return 0, iclass 28, count 0 2006.173.18:04:29.17#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.18:04:29.17#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.18:04:29.17#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.18:04:29.17#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.18:04:29.17$vck44/vb=4,4 2006.173.18:04:29.17#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.18:04:29.17#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.18:04:29.17#ibcon#ireg 11 cls_cnt 2 2006.173.18:04:29.17#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.18:04:29.23#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.18:04:29.23#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.18:04:29.23#ibcon#enter wrdev, iclass 30, count 2 2006.173.18:04:29.23#ibcon#first serial, iclass 30, count 2 2006.173.18:04:29.23#ibcon#enter sib2, iclass 30, count 2 2006.173.18:04:29.23#ibcon#flushed, iclass 30, count 2 2006.173.18:04:29.23#ibcon#about to write, iclass 30, count 2 2006.173.18:04:29.23#ibcon#wrote, iclass 30, count 2 2006.173.18:04:29.23#ibcon#about to read 3, iclass 30, count 2 2006.173.18:04:29.25#ibcon#read 3, iclass 30, count 2 2006.173.18:04:29.25#ibcon#about to read 4, iclass 30, count 2 2006.173.18:04:29.25#ibcon#read 4, iclass 30, count 2 2006.173.18:04:29.25#ibcon#about to read 5, iclass 30, count 2 2006.173.18:04:29.25#ibcon#read 5, iclass 30, count 2 2006.173.18:04:29.25#ibcon#about to read 6, iclass 30, count 2 2006.173.18:04:29.25#ibcon#read 6, iclass 30, count 2 2006.173.18:04:29.25#ibcon#end of sib2, iclass 30, count 2 2006.173.18:04:29.25#ibcon#*mode == 0, iclass 30, count 2 2006.173.18:04:29.25#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.18:04:29.25#ibcon#[27=AT04-04\r\n] 2006.173.18:04:29.25#ibcon#*before write, iclass 30, count 2 2006.173.18:04:29.25#ibcon#enter sib2, iclass 30, count 2 2006.173.18:04:29.25#ibcon#flushed, iclass 30, count 2 2006.173.18:04:29.25#ibcon#about to write, iclass 30, count 2 2006.173.18:04:29.25#ibcon#wrote, iclass 30, count 2 2006.173.18:04:29.25#ibcon#about to read 3, iclass 30, count 2 2006.173.18:04:29.28#ibcon#read 3, iclass 30, count 2 2006.173.18:04:29.28#ibcon#about to read 4, iclass 30, count 2 2006.173.18:04:29.28#ibcon#read 4, iclass 30, count 2 2006.173.18:04:29.28#ibcon#about to read 5, iclass 30, count 2 2006.173.18:04:29.28#ibcon#read 5, iclass 30, count 2 2006.173.18:04:29.28#ibcon#about to read 6, iclass 30, count 2 2006.173.18:04:29.28#ibcon#read 6, iclass 30, count 2 2006.173.18:04:29.28#ibcon#end of sib2, iclass 30, count 2 2006.173.18:04:29.28#ibcon#*after write, iclass 30, count 2 2006.173.18:04:29.28#ibcon#*before return 0, iclass 30, count 2 2006.173.18:04:29.28#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.18:04:29.28#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.18:04:29.28#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.18:04:29.28#ibcon#ireg 7 cls_cnt 0 2006.173.18:04:29.28#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.18:04:29.40#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.18:04:29.40#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.18:04:29.40#ibcon#enter wrdev, iclass 30, count 0 2006.173.18:04:29.40#ibcon#first serial, iclass 30, count 0 2006.173.18:04:29.40#ibcon#enter sib2, iclass 30, count 0 2006.173.18:04:29.40#ibcon#flushed, iclass 30, count 0 2006.173.18:04:29.40#ibcon#about to write, iclass 30, count 0 2006.173.18:04:29.40#ibcon#wrote, iclass 30, count 0 2006.173.18:04:29.40#ibcon#about to read 3, iclass 30, count 0 2006.173.18:04:29.42#ibcon#read 3, iclass 30, count 0 2006.173.18:04:29.42#ibcon#about to read 4, iclass 30, count 0 2006.173.18:04:29.42#ibcon#read 4, iclass 30, count 0 2006.173.18:04:29.42#ibcon#about to read 5, iclass 30, count 0 2006.173.18:04:29.42#ibcon#read 5, iclass 30, count 0 2006.173.18:04:29.42#ibcon#about to read 6, iclass 30, count 0 2006.173.18:04:29.42#ibcon#read 6, iclass 30, count 0 2006.173.18:04:29.42#ibcon#end of sib2, iclass 30, count 0 2006.173.18:04:29.42#ibcon#*mode == 0, iclass 30, count 0 2006.173.18:04:29.42#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.18:04:29.42#ibcon#[27=USB\r\n] 2006.173.18:04:29.42#ibcon#*before write, iclass 30, count 0 2006.173.18:04:29.42#ibcon#enter sib2, iclass 30, count 0 2006.173.18:04:29.42#ibcon#flushed, iclass 30, count 0 2006.173.18:04:29.42#ibcon#about to write, iclass 30, count 0 2006.173.18:04:29.42#ibcon#wrote, iclass 30, count 0 2006.173.18:04:29.42#ibcon#about to read 3, iclass 30, count 0 2006.173.18:04:29.45#ibcon#read 3, iclass 30, count 0 2006.173.18:04:29.45#ibcon#about to read 4, iclass 30, count 0 2006.173.18:04:29.45#ibcon#read 4, iclass 30, count 0 2006.173.18:04:29.45#ibcon#about to read 5, iclass 30, count 0 2006.173.18:04:29.45#ibcon#read 5, iclass 30, count 0 2006.173.18:04:29.45#ibcon#about to read 6, iclass 30, count 0 2006.173.18:04:29.45#ibcon#read 6, iclass 30, count 0 2006.173.18:04:29.45#ibcon#end of sib2, iclass 30, count 0 2006.173.18:04:29.45#ibcon#*after write, iclass 30, count 0 2006.173.18:04:29.45#ibcon#*before return 0, iclass 30, count 0 2006.173.18:04:29.45#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.18:04:29.45#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.18:04:29.45#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.18:04:29.45#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.18:04:29.45$vck44/vblo=5,709.99 2006.173.18:04:29.45#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.18:04:29.45#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.18:04:29.45#ibcon#ireg 17 cls_cnt 0 2006.173.18:04:29.45#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.18:04:29.45#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.18:04:29.45#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.18:04:29.45#ibcon#enter wrdev, iclass 32, count 0 2006.173.18:04:29.45#ibcon#first serial, iclass 32, count 0 2006.173.18:04:29.45#ibcon#enter sib2, iclass 32, count 0 2006.173.18:04:29.45#ibcon#flushed, iclass 32, count 0 2006.173.18:04:29.45#ibcon#about to write, iclass 32, count 0 2006.173.18:04:29.45#ibcon#wrote, iclass 32, count 0 2006.173.18:04:29.45#ibcon#about to read 3, iclass 32, count 0 2006.173.18:04:29.47#ibcon#read 3, iclass 32, count 0 2006.173.18:04:29.47#ibcon#about to read 4, iclass 32, count 0 2006.173.18:04:29.47#ibcon#read 4, iclass 32, count 0 2006.173.18:04:29.47#ibcon#about to read 5, iclass 32, count 0 2006.173.18:04:29.47#ibcon#read 5, iclass 32, count 0 2006.173.18:04:29.47#ibcon#about to read 6, iclass 32, count 0 2006.173.18:04:29.47#ibcon#read 6, iclass 32, count 0 2006.173.18:04:29.47#ibcon#end of sib2, iclass 32, count 0 2006.173.18:04:29.47#ibcon#*mode == 0, iclass 32, count 0 2006.173.18:04:29.47#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.18:04:29.47#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.18:04:29.47#ibcon#*before write, iclass 32, count 0 2006.173.18:04:29.47#ibcon#enter sib2, iclass 32, count 0 2006.173.18:04:29.47#ibcon#flushed, iclass 32, count 0 2006.173.18:04:29.47#ibcon#about to write, iclass 32, count 0 2006.173.18:04:29.47#ibcon#wrote, iclass 32, count 0 2006.173.18:04:29.47#ibcon#about to read 3, iclass 32, count 0 2006.173.18:04:29.51#ibcon#read 3, iclass 32, count 0 2006.173.18:04:29.51#ibcon#about to read 4, iclass 32, count 0 2006.173.18:04:29.51#ibcon#read 4, iclass 32, count 0 2006.173.18:04:29.51#ibcon#about to read 5, iclass 32, count 0 2006.173.18:04:29.51#ibcon#read 5, iclass 32, count 0 2006.173.18:04:29.51#ibcon#about to read 6, iclass 32, count 0 2006.173.18:04:29.51#ibcon#read 6, iclass 32, count 0 2006.173.18:04:29.51#ibcon#end of sib2, iclass 32, count 0 2006.173.18:04:29.51#ibcon#*after write, iclass 32, count 0 2006.173.18:04:29.51#ibcon#*before return 0, iclass 32, count 0 2006.173.18:04:29.51#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.18:04:29.51#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.18:04:29.51#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.18:04:29.51#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.18:04:29.51$vck44/vb=5,4 2006.173.18:04:29.51#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.18:04:29.51#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.18:04:29.51#ibcon#ireg 11 cls_cnt 2 2006.173.18:04:29.51#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.18:04:29.57#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.18:04:29.57#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.18:04:29.57#ibcon#enter wrdev, iclass 34, count 2 2006.173.18:04:29.57#ibcon#first serial, iclass 34, count 2 2006.173.18:04:29.57#ibcon#enter sib2, iclass 34, count 2 2006.173.18:04:29.57#ibcon#flushed, iclass 34, count 2 2006.173.18:04:29.57#ibcon#about to write, iclass 34, count 2 2006.173.18:04:29.57#ibcon#wrote, iclass 34, count 2 2006.173.18:04:29.57#ibcon#about to read 3, iclass 34, count 2 2006.173.18:04:29.59#ibcon#read 3, iclass 34, count 2 2006.173.18:04:29.59#ibcon#about to read 4, iclass 34, count 2 2006.173.18:04:29.59#ibcon#read 4, iclass 34, count 2 2006.173.18:04:29.59#ibcon#about to read 5, iclass 34, count 2 2006.173.18:04:29.59#ibcon#read 5, iclass 34, count 2 2006.173.18:04:29.59#ibcon#about to read 6, iclass 34, count 2 2006.173.18:04:29.59#ibcon#read 6, iclass 34, count 2 2006.173.18:04:29.59#ibcon#end of sib2, iclass 34, count 2 2006.173.18:04:29.59#ibcon#*mode == 0, iclass 34, count 2 2006.173.18:04:29.59#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.18:04:29.59#ibcon#[27=AT05-04\r\n] 2006.173.18:04:29.59#ibcon#*before write, iclass 34, count 2 2006.173.18:04:29.59#ibcon#enter sib2, iclass 34, count 2 2006.173.18:04:29.59#ibcon#flushed, iclass 34, count 2 2006.173.18:04:29.59#ibcon#about to write, iclass 34, count 2 2006.173.18:04:29.59#ibcon#wrote, iclass 34, count 2 2006.173.18:04:29.59#ibcon#about to read 3, iclass 34, count 2 2006.173.18:04:29.62#ibcon#read 3, iclass 34, count 2 2006.173.18:04:29.62#ibcon#about to read 4, iclass 34, count 2 2006.173.18:04:29.62#ibcon#read 4, iclass 34, count 2 2006.173.18:04:29.62#ibcon#about to read 5, iclass 34, count 2 2006.173.18:04:29.62#ibcon#read 5, iclass 34, count 2 2006.173.18:04:29.62#ibcon#about to read 6, iclass 34, count 2 2006.173.18:04:29.62#ibcon#read 6, iclass 34, count 2 2006.173.18:04:29.62#ibcon#end of sib2, iclass 34, count 2 2006.173.18:04:29.62#ibcon#*after write, iclass 34, count 2 2006.173.18:04:29.62#ibcon#*before return 0, iclass 34, count 2 2006.173.18:04:29.62#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.18:04:29.62#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.18:04:29.62#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.18:04:29.62#ibcon#ireg 7 cls_cnt 0 2006.173.18:04:29.62#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.18:04:29.74#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.18:04:29.74#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.18:04:29.74#ibcon#enter wrdev, iclass 34, count 0 2006.173.18:04:29.74#ibcon#first serial, iclass 34, count 0 2006.173.18:04:29.74#ibcon#enter sib2, iclass 34, count 0 2006.173.18:04:29.74#ibcon#flushed, iclass 34, count 0 2006.173.18:04:29.74#ibcon#about to write, iclass 34, count 0 2006.173.18:04:29.74#ibcon#wrote, iclass 34, count 0 2006.173.18:04:29.74#ibcon#about to read 3, iclass 34, count 0 2006.173.18:04:29.76#ibcon#read 3, iclass 34, count 0 2006.173.18:04:29.76#ibcon#about to read 4, iclass 34, count 0 2006.173.18:04:29.76#ibcon#read 4, iclass 34, count 0 2006.173.18:04:29.76#ibcon#about to read 5, iclass 34, count 0 2006.173.18:04:29.76#ibcon#read 5, iclass 34, count 0 2006.173.18:04:29.76#ibcon#about to read 6, iclass 34, count 0 2006.173.18:04:29.76#ibcon#read 6, iclass 34, count 0 2006.173.18:04:29.76#ibcon#end of sib2, iclass 34, count 0 2006.173.18:04:29.76#ibcon#*mode == 0, iclass 34, count 0 2006.173.18:04:29.76#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.18:04:29.76#ibcon#[27=USB\r\n] 2006.173.18:04:29.76#ibcon#*before write, iclass 34, count 0 2006.173.18:04:29.76#ibcon#enter sib2, iclass 34, count 0 2006.173.18:04:29.76#ibcon#flushed, iclass 34, count 0 2006.173.18:04:29.76#ibcon#about to write, iclass 34, count 0 2006.173.18:04:29.76#ibcon#wrote, iclass 34, count 0 2006.173.18:04:29.76#ibcon#about to read 3, iclass 34, count 0 2006.173.18:04:29.79#ibcon#read 3, iclass 34, count 0 2006.173.18:04:29.79#ibcon#about to read 4, iclass 34, count 0 2006.173.18:04:29.79#ibcon#read 4, iclass 34, count 0 2006.173.18:04:29.79#ibcon#about to read 5, iclass 34, count 0 2006.173.18:04:29.79#ibcon#read 5, iclass 34, count 0 2006.173.18:04:29.79#ibcon#about to read 6, iclass 34, count 0 2006.173.18:04:29.79#ibcon#read 6, iclass 34, count 0 2006.173.18:04:29.79#ibcon#end of sib2, iclass 34, count 0 2006.173.18:04:29.79#ibcon#*after write, iclass 34, count 0 2006.173.18:04:29.79#ibcon#*before return 0, iclass 34, count 0 2006.173.18:04:29.79#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.18:04:29.79#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.18:04:29.79#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.18:04:29.79#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.18:04:29.79$vck44/vblo=6,719.99 2006.173.18:04:29.79#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.18:04:29.79#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.18:04:29.79#ibcon#ireg 17 cls_cnt 0 2006.173.18:04:29.79#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.18:04:29.79#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.18:04:29.79#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.18:04:29.79#ibcon#enter wrdev, iclass 36, count 0 2006.173.18:04:29.79#ibcon#first serial, iclass 36, count 0 2006.173.18:04:29.79#ibcon#enter sib2, iclass 36, count 0 2006.173.18:04:29.79#ibcon#flushed, iclass 36, count 0 2006.173.18:04:29.79#ibcon#about to write, iclass 36, count 0 2006.173.18:04:29.79#ibcon#wrote, iclass 36, count 0 2006.173.18:04:29.79#ibcon#about to read 3, iclass 36, count 0 2006.173.18:04:29.81#ibcon#read 3, iclass 36, count 0 2006.173.18:04:29.81#ibcon#about to read 4, iclass 36, count 0 2006.173.18:04:29.81#ibcon#read 4, iclass 36, count 0 2006.173.18:04:29.81#ibcon#about to read 5, iclass 36, count 0 2006.173.18:04:29.81#ibcon#read 5, iclass 36, count 0 2006.173.18:04:29.81#ibcon#about to read 6, iclass 36, count 0 2006.173.18:04:29.81#ibcon#read 6, iclass 36, count 0 2006.173.18:04:29.81#ibcon#end of sib2, iclass 36, count 0 2006.173.18:04:29.81#ibcon#*mode == 0, iclass 36, count 0 2006.173.18:04:29.81#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.18:04:29.81#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.18:04:29.81#ibcon#*before write, iclass 36, count 0 2006.173.18:04:29.81#ibcon#enter sib2, iclass 36, count 0 2006.173.18:04:29.81#ibcon#flushed, iclass 36, count 0 2006.173.18:04:29.81#ibcon#about to write, iclass 36, count 0 2006.173.18:04:29.81#ibcon#wrote, iclass 36, count 0 2006.173.18:04:29.81#ibcon#about to read 3, iclass 36, count 0 2006.173.18:04:29.85#ibcon#read 3, iclass 36, count 0 2006.173.18:04:29.85#ibcon#about to read 4, iclass 36, count 0 2006.173.18:04:29.85#ibcon#read 4, iclass 36, count 0 2006.173.18:04:29.85#ibcon#about to read 5, iclass 36, count 0 2006.173.18:04:29.85#ibcon#read 5, iclass 36, count 0 2006.173.18:04:29.85#ibcon#about to read 6, iclass 36, count 0 2006.173.18:04:29.85#ibcon#read 6, iclass 36, count 0 2006.173.18:04:29.85#ibcon#end of sib2, iclass 36, count 0 2006.173.18:04:29.85#ibcon#*after write, iclass 36, count 0 2006.173.18:04:29.85#ibcon#*before return 0, iclass 36, count 0 2006.173.18:04:29.85#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.18:04:29.85#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.18:04:29.85#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.18:04:29.85#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.18:04:29.85$vck44/vb=6,4 2006.173.18:04:29.85#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.18:04:29.85#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.18:04:29.85#ibcon#ireg 11 cls_cnt 2 2006.173.18:04:29.85#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.18:04:29.91#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.18:04:29.91#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.18:04:29.91#ibcon#enter wrdev, iclass 38, count 2 2006.173.18:04:29.91#ibcon#first serial, iclass 38, count 2 2006.173.18:04:29.91#ibcon#enter sib2, iclass 38, count 2 2006.173.18:04:29.91#ibcon#flushed, iclass 38, count 2 2006.173.18:04:29.91#ibcon#about to write, iclass 38, count 2 2006.173.18:04:29.91#ibcon#wrote, iclass 38, count 2 2006.173.18:04:29.91#ibcon#about to read 3, iclass 38, count 2 2006.173.18:04:29.93#ibcon#read 3, iclass 38, count 2 2006.173.18:04:29.93#ibcon#about to read 4, iclass 38, count 2 2006.173.18:04:29.93#ibcon#read 4, iclass 38, count 2 2006.173.18:04:29.93#ibcon#about to read 5, iclass 38, count 2 2006.173.18:04:29.93#ibcon#read 5, iclass 38, count 2 2006.173.18:04:29.93#ibcon#about to read 6, iclass 38, count 2 2006.173.18:04:29.93#ibcon#read 6, iclass 38, count 2 2006.173.18:04:29.93#ibcon#end of sib2, iclass 38, count 2 2006.173.18:04:29.93#ibcon#*mode == 0, iclass 38, count 2 2006.173.18:04:29.93#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.18:04:29.93#ibcon#[27=AT06-04\r\n] 2006.173.18:04:29.93#ibcon#*before write, iclass 38, count 2 2006.173.18:04:29.93#ibcon#enter sib2, iclass 38, count 2 2006.173.18:04:29.93#ibcon#flushed, iclass 38, count 2 2006.173.18:04:29.93#ibcon#about to write, iclass 38, count 2 2006.173.18:04:29.93#ibcon#wrote, iclass 38, count 2 2006.173.18:04:29.93#ibcon#about to read 3, iclass 38, count 2 2006.173.18:04:29.96#ibcon#read 3, iclass 38, count 2 2006.173.18:04:29.96#ibcon#about to read 4, iclass 38, count 2 2006.173.18:04:29.96#ibcon#read 4, iclass 38, count 2 2006.173.18:04:29.96#ibcon#about to read 5, iclass 38, count 2 2006.173.18:04:29.96#ibcon#read 5, iclass 38, count 2 2006.173.18:04:29.96#ibcon#about to read 6, iclass 38, count 2 2006.173.18:04:29.96#ibcon#read 6, iclass 38, count 2 2006.173.18:04:29.96#ibcon#end of sib2, iclass 38, count 2 2006.173.18:04:29.96#ibcon#*after write, iclass 38, count 2 2006.173.18:04:29.96#ibcon#*before return 0, iclass 38, count 2 2006.173.18:04:29.96#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.18:04:29.96#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.18:04:29.96#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.18:04:29.96#ibcon#ireg 7 cls_cnt 0 2006.173.18:04:29.96#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.18:04:30.08#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.18:04:30.08#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.18:04:30.08#ibcon#enter wrdev, iclass 38, count 0 2006.173.18:04:30.08#ibcon#first serial, iclass 38, count 0 2006.173.18:04:30.08#ibcon#enter sib2, iclass 38, count 0 2006.173.18:04:30.08#ibcon#flushed, iclass 38, count 0 2006.173.18:04:30.08#ibcon#about to write, iclass 38, count 0 2006.173.18:04:30.08#ibcon#wrote, iclass 38, count 0 2006.173.18:04:30.08#ibcon#about to read 3, iclass 38, count 0 2006.173.18:04:30.10#ibcon#read 3, iclass 38, count 0 2006.173.18:04:30.10#ibcon#about to read 4, iclass 38, count 0 2006.173.18:04:30.10#ibcon#read 4, iclass 38, count 0 2006.173.18:04:30.10#ibcon#about to read 5, iclass 38, count 0 2006.173.18:04:30.10#ibcon#read 5, iclass 38, count 0 2006.173.18:04:30.10#ibcon#about to read 6, iclass 38, count 0 2006.173.18:04:30.10#ibcon#read 6, iclass 38, count 0 2006.173.18:04:30.10#ibcon#end of sib2, iclass 38, count 0 2006.173.18:04:30.10#ibcon#*mode == 0, iclass 38, count 0 2006.173.18:04:30.10#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.18:04:30.10#ibcon#[27=USB\r\n] 2006.173.18:04:30.10#ibcon#*before write, iclass 38, count 0 2006.173.18:04:30.10#ibcon#enter sib2, iclass 38, count 0 2006.173.18:04:30.10#ibcon#flushed, iclass 38, count 0 2006.173.18:04:30.10#ibcon#about to write, iclass 38, count 0 2006.173.18:04:30.10#ibcon#wrote, iclass 38, count 0 2006.173.18:04:30.10#ibcon#about to read 3, iclass 38, count 0 2006.173.18:04:30.13#ibcon#read 3, iclass 38, count 0 2006.173.18:04:30.13#ibcon#about to read 4, iclass 38, count 0 2006.173.18:04:30.13#ibcon#read 4, iclass 38, count 0 2006.173.18:04:30.13#ibcon#about to read 5, iclass 38, count 0 2006.173.18:04:30.13#ibcon#read 5, iclass 38, count 0 2006.173.18:04:30.13#ibcon#about to read 6, iclass 38, count 0 2006.173.18:04:30.13#ibcon#read 6, iclass 38, count 0 2006.173.18:04:30.13#ibcon#end of sib2, iclass 38, count 0 2006.173.18:04:30.13#ibcon#*after write, iclass 38, count 0 2006.173.18:04:30.13#ibcon#*before return 0, iclass 38, count 0 2006.173.18:04:30.13#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.18:04:30.13#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.18:04:30.13#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.18:04:30.13#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.18:04:30.13$vck44/vblo=7,734.99 2006.173.18:04:30.13#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.18:04:30.13#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.18:04:30.13#ibcon#ireg 17 cls_cnt 0 2006.173.18:04:30.13#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.18:04:30.13#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.18:04:30.13#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.18:04:30.13#ibcon#enter wrdev, iclass 40, count 0 2006.173.18:04:30.13#ibcon#first serial, iclass 40, count 0 2006.173.18:04:30.13#ibcon#enter sib2, iclass 40, count 0 2006.173.18:04:30.13#ibcon#flushed, iclass 40, count 0 2006.173.18:04:30.13#ibcon#about to write, iclass 40, count 0 2006.173.18:04:30.13#ibcon#wrote, iclass 40, count 0 2006.173.18:04:30.13#ibcon#about to read 3, iclass 40, count 0 2006.173.18:04:30.15#ibcon#read 3, iclass 40, count 0 2006.173.18:04:30.15#ibcon#about to read 4, iclass 40, count 0 2006.173.18:04:30.15#ibcon#read 4, iclass 40, count 0 2006.173.18:04:30.15#ibcon#about to read 5, iclass 40, count 0 2006.173.18:04:30.15#ibcon#read 5, iclass 40, count 0 2006.173.18:04:30.15#ibcon#about to read 6, iclass 40, count 0 2006.173.18:04:30.15#ibcon#read 6, iclass 40, count 0 2006.173.18:04:30.15#ibcon#end of sib2, iclass 40, count 0 2006.173.18:04:30.15#ibcon#*mode == 0, iclass 40, count 0 2006.173.18:04:30.15#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.18:04:30.15#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.18:04:30.15#ibcon#*before write, iclass 40, count 0 2006.173.18:04:30.15#ibcon#enter sib2, iclass 40, count 0 2006.173.18:04:30.15#ibcon#flushed, iclass 40, count 0 2006.173.18:04:30.15#ibcon#about to write, iclass 40, count 0 2006.173.18:04:30.15#ibcon#wrote, iclass 40, count 0 2006.173.18:04:30.15#ibcon#about to read 3, iclass 40, count 0 2006.173.18:04:30.19#ibcon#read 3, iclass 40, count 0 2006.173.18:04:30.19#ibcon#about to read 4, iclass 40, count 0 2006.173.18:04:30.19#ibcon#read 4, iclass 40, count 0 2006.173.18:04:30.19#ibcon#about to read 5, iclass 40, count 0 2006.173.18:04:30.19#ibcon#read 5, iclass 40, count 0 2006.173.18:04:30.19#ibcon#about to read 6, iclass 40, count 0 2006.173.18:04:30.19#ibcon#read 6, iclass 40, count 0 2006.173.18:04:30.19#ibcon#end of sib2, iclass 40, count 0 2006.173.18:04:30.19#ibcon#*after write, iclass 40, count 0 2006.173.18:04:30.19#ibcon#*before return 0, iclass 40, count 0 2006.173.18:04:30.19#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.18:04:30.19#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.18:04:30.19#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.18:04:30.19#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.18:04:30.19$vck44/vb=7,4 2006.173.18:04:30.19#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.18:04:30.19#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.18:04:30.19#ibcon#ireg 11 cls_cnt 2 2006.173.18:04:30.19#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.18:04:30.25#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.18:04:30.25#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.18:04:30.25#ibcon#enter wrdev, iclass 4, count 2 2006.173.18:04:30.25#ibcon#first serial, iclass 4, count 2 2006.173.18:04:30.25#ibcon#enter sib2, iclass 4, count 2 2006.173.18:04:30.25#ibcon#flushed, iclass 4, count 2 2006.173.18:04:30.25#ibcon#about to write, iclass 4, count 2 2006.173.18:04:30.25#ibcon#wrote, iclass 4, count 2 2006.173.18:04:30.25#ibcon#about to read 3, iclass 4, count 2 2006.173.18:04:30.27#ibcon#read 3, iclass 4, count 2 2006.173.18:04:30.27#ibcon#about to read 4, iclass 4, count 2 2006.173.18:04:30.27#ibcon#read 4, iclass 4, count 2 2006.173.18:04:30.27#ibcon#about to read 5, iclass 4, count 2 2006.173.18:04:30.27#ibcon#read 5, iclass 4, count 2 2006.173.18:04:30.27#ibcon#about to read 6, iclass 4, count 2 2006.173.18:04:30.27#ibcon#read 6, iclass 4, count 2 2006.173.18:04:30.27#ibcon#end of sib2, iclass 4, count 2 2006.173.18:04:30.27#ibcon#*mode == 0, iclass 4, count 2 2006.173.18:04:30.27#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.18:04:30.27#ibcon#[27=AT07-04\r\n] 2006.173.18:04:30.27#ibcon#*before write, iclass 4, count 2 2006.173.18:04:30.27#ibcon#enter sib2, iclass 4, count 2 2006.173.18:04:30.27#ibcon#flushed, iclass 4, count 2 2006.173.18:04:30.27#ibcon#about to write, iclass 4, count 2 2006.173.18:04:30.27#ibcon#wrote, iclass 4, count 2 2006.173.18:04:30.27#ibcon#about to read 3, iclass 4, count 2 2006.173.18:04:30.30#ibcon#read 3, iclass 4, count 2 2006.173.18:04:30.30#ibcon#about to read 4, iclass 4, count 2 2006.173.18:04:30.30#ibcon#read 4, iclass 4, count 2 2006.173.18:04:30.30#ibcon#about to read 5, iclass 4, count 2 2006.173.18:04:30.30#ibcon#read 5, iclass 4, count 2 2006.173.18:04:30.30#ibcon#about to read 6, iclass 4, count 2 2006.173.18:04:30.30#ibcon#read 6, iclass 4, count 2 2006.173.18:04:30.30#ibcon#end of sib2, iclass 4, count 2 2006.173.18:04:30.30#ibcon#*after write, iclass 4, count 2 2006.173.18:04:30.30#ibcon#*before return 0, iclass 4, count 2 2006.173.18:04:30.30#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.18:04:30.30#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.18:04:30.30#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.18:04:30.30#ibcon#ireg 7 cls_cnt 0 2006.173.18:04:30.30#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.18:04:30.42#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.18:04:30.42#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.18:04:30.42#ibcon#enter wrdev, iclass 4, count 0 2006.173.18:04:30.42#ibcon#first serial, iclass 4, count 0 2006.173.18:04:30.42#ibcon#enter sib2, iclass 4, count 0 2006.173.18:04:30.42#ibcon#flushed, iclass 4, count 0 2006.173.18:04:30.42#ibcon#about to write, iclass 4, count 0 2006.173.18:04:30.42#ibcon#wrote, iclass 4, count 0 2006.173.18:04:30.42#ibcon#about to read 3, iclass 4, count 0 2006.173.18:04:30.44#ibcon#read 3, iclass 4, count 0 2006.173.18:04:30.44#ibcon#about to read 4, iclass 4, count 0 2006.173.18:04:30.44#ibcon#read 4, iclass 4, count 0 2006.173.18:04:30.44#ibcon#about to read 5, iclass 4, count 0 2006.173.18:04:30.44#ibcon#read 5, iclass 4, count 0 2006.173.18:04:30.44#ibcon#about to read 6, iclass 4, count 0 2006.173.18:04:30.44#ibcon#read 6, iclass 4, count 0 2006.173.18:04:30.44#ibcon#end of sib2, iclass 4, count 0 2006.173.18:04:30.44#ibcon#*mode == 0, iclass 4, count 0 2006.173.18:04:30.44#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.18:04:30.44#ibcon#[27=USB\r\n] 2006.173.18:04:30.44#ibcon#*before write, iclass 4, count 0 2006.173.18:04:30.44#ibcon#enter sib2, iclass 4, count 0 2006.173.18:04:30.44#ibcon#flushed, iclass 4, count 0 2006.173.18:04:30.44#ibcon#about to write, iclass 4, count 0 2006.173.18:04:30.44#ibcon#wrote, iclass 4, count 0 2006.173.18:04:30.44#ibcon#about to read 3, iclass 4, count 0 2006.173.18:04:30.47#ibcon#read 3, iclass 4, count 0 2006.173.18:04:30.47#ibcon#about to read 4, iclass 4, count 0 2006.173.18:04:30.47#ibcon#read 4, iclass 4, count 0 2006.173.18:04:30.47#ibcon#about to read 5, iclass 4, count 0 2006.173.18:04:30.47#ibcon#read 5, iclass 4, count 0 2006.173.18:04:30.47#ibcon#about to read 6, iclass 4, count 0 2006.173.18:04:30.47#ibcon#read 6, iclass 4, count 0 2006.173.18:04:30.47#ibcon#end of sib2, iclass 4, count 0 2006.173.18:04:30.47#ibcon#*after write, iclass 4, count 0 2006.173.18:04:30.47#ibcon#*before return 0, iclass 4, count 0 2006.173.18:04:30.47#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.18:04:30.47#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.18:04:30.47#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.18:04:30.47#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.18:04:30.47$vck44/vblo=8,744.99 2006.173.18:04:30.47#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.18:04:30.47#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.18:04:30.47#ibcon#ireg 17 cls_cnt 0 2006.173.18:04:30.47#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.18:04:30.47#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.18:04:30.47#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.18:04:30.47#ibcon#enter wrdev, iclass 6, count 0 2006.173.18:04:30.47#ibcon#first serial, iclass 6, count 0 2006.173.18:04:30.47#ibcon#enter sib2, iclass 6, count 0 2006.173.18:04:30.47#ibcon#flushed, iclass 6, count 0 2006.173.18:04:30.47#ibcon#about to write, iclass 6, count 0 2006.173.18:04:30.47#ibcon#wrote, iclass 6, count 0 2006.173.18:04:30.47#ibcon#about to read 3, iclass 6, count 0 2006.173.18:04:30.49#ibcon#read 3, iclass 6, count 0 2006.173.18:04:30.49#ibcon#about to read 4, iclass 6, count 0 2006.173.18:04:30.49#ibcon#read 4, iclass 6, count 0 2006.173.18:04:30.49#ibcon#about to read 5, iclass 6, count 0 2006.173.18:04:30.49#ibcon#read 5, iclass 6, count 0 2006.173.18:04:30.49#ibcon#about to read 6, iclass 6, count 0 2006.173.18:04:30.49#ibcon#read 6, iclass 6, count 0 2006.173.18:04:30.49#ibcon#end of sib2, iclass 6, count 0 2006.173.18:04:30.49#ibcon#*mode == 0, iclass 6, count 0 2006.173.18:04:30.49#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.18:04:30.49#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.18:04:30.49#ibcon#*before write, iclass 6, count 0 2006.173.18:04:30.49#ibcon#enter sib2, iclass 6, count 0 2006.173.18:04:30.49#ibcon#flushed, iclass 6, count 0 2006.173.18:04:30.49#ibcon#about to write, iclass 6, count 0 2006.173.18:04:30.49#ibcon#wrote, iclass 6, count 0 2006.173.18:04:30.49#ibcon#about to read 3, iclass 6, count 0 2006.173.18:04:30.53#ibcon#read 3, iclass 6, count 0 2006.173.18:04:30.53#ibcon#about to read 4, iclass 6, count 0 2006.173.18:04:30.53#ibcon#read 4, iclass 6, count 0 2006.173.18:04:30.53#ibcon#about to read 5, iclass 6, count 0 2006.173.18:04:30.53#ibcon#read 5, iclass 6, count 0 2006.173.18:04:30.53#ibcon#about to read 6, iclass 6, count 0 2006.173.18:04:30.53#ibcon#read 6, iclass 6, count 0 2006.173.18:04:30.53#ibcon#end of sib2, iclass 6, count 0 2006.173.18:04:30.53#ibcon#*after write, iclass 6, count 0 2006.173.18:04:30.53#ibcon#*before return 0, iclass 6, count 0 2006.173.18:04:30.53#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.18:04:30.53#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.18:04:30.53#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.18:04:30.53#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.18:04:30.53$vck44/vb=8,4 2006.173.18:04:30.53#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.18:04:30.53#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.18:04:30.53#ibcon#ireg 11 cls_cnt 2 2006.173.18:04:30.53#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.18:04:30.59#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.18:04:30.59#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.18:04:30.59#ibcon#enter wrdev, iclass 10, count 2 2006.173.18:04:30.59#ibcon#first serial, iclass 10, count 2 2006.173.18:04:30.59#ibcon#enter sib2, iclass 10, count 2 2006.173.18:04:30.59#ibcon#flushed, iclass 10, count 2 2006.173.18:04:30.59#ibcon#about to write, iclass 10, count 2 2006.173.18:04:30.59#ibcon#wrote, iclass 10, count 2 2006.173.18:04:30.59#ibcon#about to read 3, iclass 10, count 2 2006.173.18:04:30.61#ibcon#read 3, iclass 10, count 2 2006.173.18:04:30.61#ibcon#about to read 4, iclass 10, count 2 2006.173.18:04:30.61#ibcon#read 4, iclass 10, count 2 2006.173.18:04:30.61#ibcon#about to read 5, iclass 10, count 2 2006.173.18:04:30.61#ibcon#read 5, iclass 10, count 2 2006.173.18:04:30.61#ibcon#about to read 6, iclass 10, count 2 2006.173.18:04:30.61#ibcon#read 6, iclass 10, count 2 2006.173.18:04:30.61#ibcon#end of sib2, iclass 10, count 2 2006.173.18:04:30.61#ibcon#*mode == 0, iclass 10, count 2 2006.173.18:04:30.61#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.18:04:30.61#ibcon#[27=AT08-04\r\n] 2006.173.18:04:30.61#ibcon#*before write, iclass 10, count 2 2006.173.18:04:30.61#ibcon#enter sib2, iclass 10, count 2 2006.173.18:04:30.61#ibcon#flushed, iclass 10, count 2 2006.173.18:04:30.61#ibcon#about to write, iclass 10, count 2 2006.173.18:04:30.61#ibcon#wrote, iclass 10, count 2 2006.173.18:04:30.61#ibcon#about to read 3, iclass 10, count 2 2006.173.18:04:30.64#ibcon#read 3, iclass 10, count 2 2006.173.18:04:30.64#ibcon#about to read 4, iclass 10, count 2 2006.173.18:04:30.64#ibcon#read 4, iclass 10, count 2 2006.173.18:04:30.64#ibcon#about to read 5, iclass 10, count 2 2006.173.18:04:30.64#ibcon#read 5, iclass 10, count 2 2006.173.18:04:30.64#ibcon#about to read 6, iclass 10, count 2 2006.173.18:04:30.64#ibcon#read 6, iclass 10, count 2 2006.173.18:04:30.64#ibcon#end of sib2, iclass 10, count 2 2006.173.18:04:30.64#ibcon#*after write, iclass 10, count 2 2006.173.18:04:30.64#ibcon#*before return 0, iclass 10, count 2 2006.173.18:04:30.64#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.18:04:30.64#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.18:04:30.64#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.18:04:30.64#ibcon#ireg 7 cls_cnt 0 2006.173.18:04:30.64#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.18:04:30.76#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.18:04:30.76#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.18:04:30.76#ibcon#enter wrdev, iclass 10, count 0 2006.173.18:04:30.76#ibcon#first serial, iclass 10, count 0 2006.173.18:04:30.76#ibcon#enter sib2, iclass 10, count 0 2006.173.18:04:30.76#ibcon#flushed, iclass 10, count 0 2006.173.18:04:30.76#ibcon#about to write, iclass 10, count 0 2006.173.18:04:30.76#ibcon#wrote, iclass 10, count 0 2006.173.18:04:30.76#ibcon#about to read 3, iclass 10, count 0 2006.173.18:04:30.78#ibcon#read 3, iclass 10, count 0 2006.173.18:04:30.78#ibcon#about to read 4, iclass 10, count 0 2006.173.18:04:30.78#ibcon#read 4, iclass 10, count 0 2006.173.18:04:30.78#ibcon#about to read 5, iclass 10, count 0 2006.173.18:04:30.78#ibcon#read 5, iclass 10, count 0 2006.173.18:04:30.78#ibcon#about to read 6, iclass 10, count 0 2006.173.18:04:30.78#ibcon#read 6, iclass 10, count 0 2006.173.18:04:30.78#ibcon#end of sib2, iclass 10, count 0 2006.173.18:04:30.78#ibcon#*mode == 0, iclass 10, count 0 2006.173.18:04:30.78#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.18:04:30.78#ibcon#[27=USB\r\n] 2006.173.18:04:30.78#ibcon#*before write, iclass 10, count 0 2006.173.18:04:30.78#ibcon#enter sib2, iclass 10, count 0 2006.173.18:04:30.78#ibcon#flushed, iclass 10, count 0 2006.173.18:04:30.78#ibcon#about to write, iclass 10, count 0 2006.173.18:04:30.78#ibcon#wrote, iclass 10, count 0 2006.173.18:04:30.78#ibcon#about to read 3, iclass 10, count 0 2006.173.18:04:30.81#ibcon#read 3, iclass 10, count 0 2006.173.18:04:30.81#ibcon#about to read 4, iclass 10, count 0 2006.173.18:04:30.81#ibcon#read 4, iclass 10, count 0 2006.173.18:04:30.81#ibcon#about to read 5, iclass 10, count 0 2006.173.18:04:30.81#ibcon#read 5, iclass 10, count 0 2006.173.18:04:30.81#ibcon#about to read 6, iclass 10, count 0 2006.173.18:04:30.81#ibcon#read 6, iclass 10, count 0 2006.173.18:04:30.81#ibcon#end of sib2, iclass 10, count 0 2006.173.18:04:30.81#ibcon#*after write, iclass 10, count 0 2006.173.18:04:30.81#ibcon#*before return 0, iclass 10, count 0 2006.173.18:04:30.81#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.18:04:30.81#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.18:04:30.81#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.18:04:30.81#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.18:04:30.81$vck44/vabw=wide 2006.173.18:04:30.81#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.18:04:30.81#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.18:04:30.81#ibcon#ireg 8 cls_cnt 0 2006.173.18:04:30.81#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.18:04:30.81#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.18:04:30.81#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.18:04:30.81#ibcon#enter wrdev, iclass 12, count 0 2006.173.18:04:30.81#ibcon#first serial, iclass 12, count 0 2006.173.18:04:30.81#ibcon#enter sib2, iclass 12, count 0 2006.173.18:04:30.81#ibcon#flushed, iclass 12, count 0 2006.173.18:04:30.81#ibcon#about to write, iclass 12, count 0 2006.173.18:04:30.81#ibcon#wrote, iclass 12, count 0 2006.173.18:04:30.81#ibcon#about to read 3, iclass 12, count 0 2006.173.18:04:30.83#ibcon#read 3, iclass 12, count 0 2006.173.18:04:30.83#ibcon#about to read 4, iclass 12, count 0 2006.173.18:04:30.83#ibcon#read 4, iclass 12, count 0 2006.173.18:04:30.83#ibcon#about to read 5, iclass 12, count 0 2006.173.18:04:30.83#ibcon#read 5, iclass 12, count 0 2006.173.18:04:30.83#ibcon#about to read 6, iclass 12, count 0 2006.173.18:04:30.83#ibcon#read 6, iclass 12, count 0 2006.173.18:04:30.83#ibcon#end of sib2, iclass 12, count 0 2006.173.18:04:30.83#ibcon#*mode == 0, iclass 12, count 0 2006.173.18:04:30.83#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.18:04:30.83#ibcon#[25=BW32\r\n] 2006.173.18:04:30.83#ibcon#*before write, iclass 12, count 0 2006.173.18:04:30.83#ibcon#enter sib2, iclass 12, count 0 2006.173.18:04:30.83#ibcon#flushed, iclass 12, count 0 2006.173.18:04:30.83#ibcon#about to write, iclass 12, count 0 2006.173.18:04:30.83#ibcon#wrote, iclass 12, count 0 2006.173.18:04:30.83#ibcon#about to read 3, iclass 12, count 0 2006.173.18:04:30.86#ibcon#read 3, iclass 12, count 0 2006.173.18:04:30.86#ibcon#about to read 4, iclass 12, count 0 2006.173.18:04:30.86#ibcon#read 4, iclass 12, count 0 2006.173.18:04:30.86#ibcon#about to read 5, iclass 12, count 0 2006.173.18:04:30.86#ibcon#read 5, iclass 12, count 0 2006.173.18:04:30.86#ibcon#about to read 6, iclass 12, count 0 2006.173.18:04:30.86#ibcon#read 6, iclass 12, count 0 2006.173.18:04:30.86#ibcon#end of sib2, iclass 12, count 0 2006.173.18:04:30.86#ibcon#*after write, iclass 12, count 0 2006.173.18:04:30.86#ibcon#*before return 0, iclass 12, count 0 2006.173.18:04:30.86#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.18:04:30.86#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.18:04:30.86#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.18:04:30.86#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.18:04:30.86$vck44/vbbw=wide 2006.173.18:04:30.86#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.18:04:30.86#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.18:04:30.86#ibcon#ireg 8 cls_cnt 0 2006.173.18:04:30.86#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.18:04:30.93#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.18:04:30.93#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.18:04:30.93#ibcon#enter wrdev, iclass 14, count 0 2006.173.18:04:30.93#ibcon#first serial, iclass 14, count 0 2006.173.18:04:30.93#ibcon#enter sib2, iclass 14, count 0 2006.173.18:04:30.93#ibcon#flushed, iclass 14, count 0 2006.173.18:04:30.93#ibcon#about to write, iclass 14, count 0 2006.173.18:04:30.93#ibcon#wrote, iclass 14, count 0 2006.173.18:04:30.93#ibcon#about to read 3, iclass 14, count 0 2006.173.18:04:30.95#ibcon#read 3, iclass 14, count 0 2006.173.18:04:30.95#ibcon#about to read 4, iclass 14, count 0 2006.173.18:04:30.95#ibcon#read 4, iclass 14, count 0 2006.173.18:04:30.95#ibcon#about to read 5, iclass 14, count 0 2006.173.18:04:30.95#ibcon#read 5, iclass 14, count 0 2006.173.18:04:30.95#ibcon#about to read 6, iclass 14, count 0 2006.173.18:04:30.95#ibcon#read 6, iclass 14, count 0 2006.173.18:04:30.95#ibcon#end of sib2, iclass 14, count 0 2006.173.18:04:30.95#ibcon#*mode == 0, iclass 14, count 0 2006.173.18:04:30.95#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.18:04:30.95#ibcon#[27=BW32\r\n] 2006.173.18:04:30.95#ibcon#*before write, iclass 14, count 0 2006.173.18:04:30.95#ibcon#enter sib2, iclass 14, count 0 2006.173.18:04:30.95#ibcon#flushed, iclass 14, count 0 2006.173.18:04:30.95#ibcon#about to write, iclass 14, count 0 2006.173.18:04:30.95#ibcon#wrote, iclass 14, count 0 2006.173.18:04:30.95#ibcon#about to read 3, iclass 14, count 0 2006.173.18:04:30.98#ibcon#read 3, iclass 14, count 0 2006.173.18:04:30.98#ibcon#about to read 4, iclass 14, count 0 2006.173.18:04:30.98#ibcon#read 4, iclass 14, count 0 2006.173.18:04:30.98#ibcon#about to read 5, iclass 14, count 0 2006.173.18:04:30.98#ibcon#read 5, iclass 14, count 0 2006.173.18:04:30.98#ibcon#about to read 6, iclass 14, count 0 2006.173.18:04:30.98#ibcon#read 6, iclass 14, count 0 2006.173.18:04:30.98#ibcon#end of sib2, iclass 14, count 0 2006.173.18:04:30.98#ibcon#*after write, iclass 14, count 0 2006.173.18:04:30.98#ibcon#*before return 0, iclass 14, count 0 2006.173.18:04:30.98#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.18:04:30.98#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.18:04:30.98#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.18:04:30.98#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.18:04:30.98$setupk4/ifdk4 2006.173.18:04:30.98$ifdk4/lo= 2006.173.18:04:30.98$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.18:04:30.98$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.18:04:30.98$ifdk4/patch= 2006.173.18:04:30.98$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.18:04:30.98$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.18:04:30.98$setupk4/!*+20s 2006.173.18:04:35.43#abcon#<5=/14 1.2 2.7 20.021001002.2\r\n> 2006.173.18:04:35.45#abcon#{5=INTERFACE CLEAR} 2006.173.18:04:35.51#abcon#[5=S1D000X0/0*\r\n] 2006.173.18:04:40.14#trakl#Source acquired 2006.173.18:04:40.14#flagr#flagr/antenna,acquired 2006.173.18:04:45.49$setupk4/"tpicd 2006.173.18:04:45.49$setupk4/echo=off 2006.173.18:04:45.49$setupk4/xlog=off 2006.173.18:04:45.49:!2006.173.18:05:03 2006.173.18:05:03.00:preob 2006.173.18:05:03.13/onsource/TRACKING 2006.173.18:05:03.13:!2006.173.18:05:13 2006.173.18:05:13.00:"tape 2006.173.18:05:13.00:"st=record 2006.173.18:05:13.00:data_valid=on 2006.173.18:05:13.00:midob 2006.173.18:05:14.13/onsource/TRACKING 2006.173.18:05:14.13/wx/20.02,1002.2,100 2006.173.18:05:14.28/cable/+6.5147E-03 2006.173.18:05:15.37/va/01,07,usb,yes,36,39 2006.173.18:05:15.37/va/02,06,usb,yes,36,37 2006.173.18:05:15.37/va/03,05,usb,yes,46,48 2006.173.18:05:15.37/va/04,06,usb,yes,37,39 2006.173.18:05:15.37/va/05,04,usb,yes,29,29 2006.173.18:05:15.37/va/06,03,usb,yes,41,40 2006.173.18:05:15.37/va/07,04,usb,yes,33,34 2006.173.18:05:15.37/va/08,04,usb,yes,28,34 2006.173.18:05:15.60/valo/01,524.99,yes,locked 2006.173.18:05:15.60/valo/02,534.99,yes,locked 2006.173.18:05:15.60/valo/03,564.99,yes,locked 2006.173.18:05:15.60/valo/04,624.99,yes,locked 2006.173.18:05:15.60/valo/05,734.99,yes,locked 2006.173.18:05:15.60/valo/06,814.99,yes,locked 2006.173.18:05:15.60/valo/07,864.99,yes,locked 2006.173.18:05:15.60/valo/08,884.99,yes,locked 2006.173.18:05:16.69/vb/01,04,usb,yes,30,28 2006.173.18:05:16.69/vb/02,04,usb,yes,32,32 2006.173.18:05:16.69/vb/03,04,usb,yes,29,32 2006.173.18:05:16.69/vb/04,04,usb,yes,33,32 2006.173.18:05:16.69/vb/05,04,usb,yes,26,28 2006.173.18:05:16.69/vb/06,04,usb,yes,30,27 2006.173.18:05:16.69/vb/07,04,usb,yes,30,30 2006.173.18:05:16.69/vb/08,04,usb,yes,28,31 2006.173.18:05:16.92/vblo/01,629.99,yes,locked 2006.173.18:05:16.92/vblo/02,634.99,yes,locked 2006.173.18:05:16.92/vblo/03,649.99,yes,locked 2006.173.18:05:16.92/vblo/04,679.99,yes,locked 2006.173.18:05:16.92/vblo/05,709.99,yes,locked 2006.173.18:05:16.92/vblo/06,719.99,yes,locked 2006.173.18:05:16.92/vblo/07,734.99,yes,locked 2006.173.18:05:16.92/vblo/08,744.99,yes,locked 2006.173.18:05:17.07/vabw/8 2006.173.18:05:17.22/vbbw/8 2006.173.18:05:17.31/xfe/off,on,16.0 2006.173.18:05:17.70/ifatt/23,28,28,28 2006.173.18:05:18.07/fmout-gps/S +4.01E-07 2006.173.18:05:18.11:!2006.173.18:06:33 2006.173.18:06:33.01:data_valid=off 2006.173.18:06:33.01:"et 2006.173.18:06:33.01:!+3s 2006.173.18:06:36.02:"tape 2006.173.18:06:36.02:postob 2006.173.18:06:36.13/cable/+6.5138E-03 2006.173.18:06:36.13/wx/20.02,1002.2,100 2006.173.18:06:36.19/fmout-gps/S +3.99E-07 2006.173.18:06:36.19:scan_name=173-1809,jd0606,70 2006.173.18:06:36.19:source=1611+343,161341.06,341247.9,2000.0,ccw 2006.173.18:06:37.13#flagr#flagr/antenna,new-source 2006.173.18:06:37.13:checkk5 2006.173.18:06:37.54/chk_autoobs//k5ts1/ autoobs is running! 2006.173.18:06:37.93/chk_autoobs//k5ts2/ autoobs is running! 2006.173.18:06:38.33/chk_autoobs//k5ts3/ autoobs is running! 2006.173.18:06:38.73/chk_autoobs//k5ts4/ autoobs is running! 2006.173.18:06:39.12/chk_obsdata//k5ts1/T1731805??a.dat file size is correct (nominal:320MB, actual:316MB). 2006.173.18:06:39.52/chk_obsdata//k5ts2/T1731805??b.dat file size is correct (nominal:320MB, actual:316MB). 2006.173.18:06:39.93/chk_obsdata//k5ts3/T1731805??c.dat file size is correct (nominal:320MB, actual:316MB). 2006.173.18:06:40.37/chk_obsdata//k5ts4/T1731805??d.dat file size is correct (nominal:320MB, actual:316MB). 2006.173.18:06:41.08/k5log//k5ts1_log_newline 2006.173.18:06:41.79/k5log//k5ts2_log_newline 2006.173.18:06:42.50/k5log//k5ts3_log_newline 2006.173.18:06:43.20/k5log//k5ts4_log_newline 2006.173.18:06:43.22/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.18:06:43.22:setupk4=1 2006.173.18:06:43.22$setupk4/echo=on 2006.173.18:06:43.22$setupk4/pcalon 2006.173.18:06:43.22$pcalon/"no phase cal control is implemented here 2006.173.18:06:43.22$setupk4/"tpicd=stop 2006.173.18:06:43.22$setupk4/"rec=synch_on 2006.173.18:06:43.22$setupk4/"rec_mode=128 2006.173.18:06:43.22$setupk4/!* 2006.173.18:06:43.23$setupk4/recpk4 2006.173.18:06:43.23$recpk4/recpatch= 2006.173.18:06:43.23$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.18:06:43.23$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.18:06:43.23$setupk4/vck44 2006.173.18:06:43.23$vck44/valo=1,524.99 2006.173.18:06:43.23#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.18:06:43.23#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.18:06:43.23#ibcon#ireg 17 cls_cnt 0 2006.173.18:06:43.23#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.18:06:43.23#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.18:06:43.23#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.18:06:43.23#ibcon#enter wrdev, iclass 35, count 0 2006.173.18:06:43.23#ibcon#first serial, iclass 35, count 0 2006.173.18:06:43.23#ibcon#enter sib2, iclass 35, count 0 2006.173.18:06:43.23#ibcon#flushed, iclass 35, count 0 2006.173.18:06:43.23#ibcon#about to write, iclass 35, count 0 2006.173.18:06:43.23#ibcon#wrote, iclass 35, count 0 2006.173.18:06:43.23#ibcon#about to read 3, iclass 35, count 0 2006.173.18:06:43.24#ibcon#read 3, iclass 35, count 0 2006.173.18:06:43.24#ibcon#about to read 4, iclass 35, count 0 2006.173.18:06:43.24#ibcon#read 4, iclass 35, count 0 2006.173.18:06:43.24#ibcon#about to read 5, iclass 35, count 0 2006.173.18:06:43.24#ibcon#read 5, iclass 35, count 0 2006.173.18:06:43.24#ibcon#about to read 6, iclass 35, count 0 2006.173.18:06:43.24#ibcon#read 6, iclass 35, count 0 2006.173.18:06:43.24#ibcon#end of sib2, iclass 35, count 0 2006.173.18:06:43.24#ibcon#*mode == 0, iclass 35, count 0 2006.173.18:06:43.24#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.18:06:43.24#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.18:06:43.24#ibcon#*before write, iclass 35, count 0 2006.173.18:06:43.24#ibcon#enter sib2, iclass 35, count 0 2006.173.18:06:43.24#ibcon#flushed, iclass 35, count 0 2006.173.18:06:43.24#ibcon#about to write, iclass 35, count 0 2006.173.18:06:43.24#ibcon#wrote, iclass 35, count 0 2006.173.18:06:43.24#ibcon#about to read 3, iclass 35, count 0 2006.173.18:06:43.29#ibcon#read 3, iclass 35, count 0 2006.173.18:06:43.29#ibcon#about to read 4, iclass 35, count 0 2006.173.18:06:43.29#ibcon#read 4, iclass 35, count 0 2006.173.18:06:43.29#ibcon#about to read 5, iclass 35, count 0 2006.173.18:06:43.29#ibcon#read 5, iclass 35, count 0 2006.173.18:06:43.29#ibcon#about to read 6, iclass 35, count 0 2006.173.18:06:43.29#ibcon#read 6, iclass 35, count 0 2006.173.18:06:43.29#ibcon#end of sib2, iclass 35, count 0 2006.173.18:06:43.29#ibcon#*after write, iclass 35, count 0 2006.173.18:06:43.29#ibcon#*before return 0, iclass 35, count 0 2006.173.18:06:43.29#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.18:06:43.29#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.18:06:43.29#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.18:06:43.29#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.18:06:43.29$vck44/va=1,7 2006.173.18:06:43.29#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.173.18:06:43.29#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.173.18:06:43.29#ibcon#ireg 11 cls_cnt 2 2006.173.18:06:43.29#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.18:06:43.29#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.18:06:43.29#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.18:06:43.29#ibcon#enter wrdev, iclass 37, count 2 2006.173.18:06:43.29#ibcon#first serial, iclass 37, count 2 2006.173.18:06:43.29#ibcon#enter sib2, iclass 37, count 2 2006.173.18:06:43.29#ibcon#flushed, iclass 37, count 2 2006.173.18:06:43.29#ibcon#about to write, iclass 37, count 2 2006.173.18:06:43.29#ibcon#wrote, iclass 37, count 2 2006.173.18:06:43.29#ibcon#about to read 3, iclass 37, count 2 2006.173.18:06:43.31#ibcon#read 3, iclass 37, count 2 2006.173.18:06:43.31#ibcon#about to read 4, iclass 37, count 2 2006.173.18:06:43.31#ibcon#read 4, iclass 37, count 2 2006.173.18:06:43.31#ibcon#about to read 5, iclass 37, count 2 2006.173.18:06:43.31#ibcon#read 5, iclass 37, count 2 2006.173.18:06:43.31#ibcon#about to read 6, iclass 37, count 2 2006.173.18:06:43.31#ibcon#read 6, iclass 37, count 2 2006.173.18:06:43.31#ibcon#end of sib2, iclass 37, count 2 2006.173.18:06:43.31#ibcon#*mode == 0, iclass 37, count 2 2006.173.18:06:43.31#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.173.18:06:43.31#ibcon#[25=AT01-07\r\n] 2006.173.18:06:43.31#ibcon#*before write, iclass 37, count 2 2006.173.18:06:43.31#ibcon#enter sib2, iclass 37, count 2 2006.173.18:06:43.31#ibcon#flushed, iclass 37, count 2 2006.173.18:06:43.31#ibcon#about to write, iclass 37, count 2 2006.173.18:06:43.31#ibcon#wrote, iclass 37, count 2 2006.173.18:06:43.31#ibcon#about to read 3, iclass 37, count 2 2006.173.18:06:43.34#ibcon#read 3, iclass 37, count 2 2006.173.18:06:43.34#ibcon#about to read 4, iclass 37, count 2 2006.173.18:06:43.34#ibcon#read 4, iclass 37, count 2 2006.173.18:06:43.34#ibcon#about to read 5, iclass 37, count 2 2006.173.18:06:43.34#ibcon#read 5, iclass 37, count 2 2006.173.18:06:43.34#ibcon#about to read 6, iclass 37, count 2 2006.173.18:06:43.34#ibcon#read 6, iclass 37, count 2 2006.173.18:06:43.34#ibcon#end of sib2, iclass 37, count 2 2006.173.18:06:43.34#ibcon#*after write, iclass 37, count 2 2006.173.18:06:43.34#ibcon#*before return 0, iclass 37, count 2 2006.173.18:06:43.34#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.18:06:43.34#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.173.18:06:43.34#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.173.18:06:43.34#ibcon#ireg 7 cls_cnt 0 2006.173.18:06:43.34#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.18:06:43.46#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.18:06:43.46#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.18:06:43.46#ibcon#enter wrdev, iclass 37, count 0 2006.173.18:06:43.46#ibcon#first serial, iclass 37, count 0 2006.173.18:06:43.46#ibcon#enter sib2, iclass 37, count 0 2006.173.18:06:43.46#ibcon#flushed, iclass 37, count 0 2006.173.18:06:43.46#ibcon#about to write, iclass 37, count 0 2006.173.18:06:43.46#ibcon#wrote, iclass 37, count 0 2006.173.18:06:43.46#ibcon#about to read 3, iclass 37, count 0 2006.173.18:06:43.48#ibcon#read 3, iclass 37, count 0 2006.173.18:06:43.48#ibcon#about to read 4, iclass 37, count 0 2006.173.18:06:43.48#ibcon#read 4, iclass 37, count 0 2006.173.18:06:43.48#ibcon#about to read 5, iclass 37, count 0 2006.173.18:06:43.48#ibcon#read 5, iclass 37, count 0 2006.173.18:06:43.48#ibcon#about to read 6, iclass 37, count 0 2006.173.18:06:43.48#ibcon#read 6, iclass 37, count 0 2006.173.18:06:43.48#ibcon#end of sib2, iclass 37, count 0 2006.173.18:06:43.48#ibcon#*mode == 0, iclass 37, count 0 2006.173.18:06:43.48#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.18:06:43.48#ibcon#[25=USB\r\n] 2006.173.18:06:43.48#ibcon#*before write, iclass 37, count 0 2006.173.18:06:43.48#ibcon#enter sib2, iclass 37, count 0 2006.173.18:06:43.48#ibcon#flushed, iclass 37, count 0 2006.173.18:06:43.48#ibcon#about to write, iclass 37, count 0 2006.173.18:06:43.48#ibcon#wrote, iclass 37, count 0 2006.173.18:06:43.48#ibcon#about to read 3, iclass 37, count 0 2006.173.18:06:43.51#ibcon#read 3, iclass 37, count 0 2006.173.18:06:43.51#ibcon#about to read 4, iclass 37, count 0 2006.173.18:06:43.51#ibcon#read 4, iclass 37, count 0 2006.173.18:06:43.51#ibcon#about to read 5, iclass 37, count 0 2006.173.18:06:43.51#ibcon#read 5, iclass 37, count 0 2006.173.18:06:43.51#ibcon#about to read 6, iclass 37, count 0 2006.173.18:06:43.51#ibcon#read 6, iclass 37, count 0 2006.173.18:06:43.51#ibcon#end of sib2, iclass 37, count 0 2006.173.18:06:43.51#ibcon#*after write, iclass 37, count 0 2006.173.18:06:43.51#ibcon#*before return 0, iclass 37, count 0 2006.173.18:06:43.51#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.18:06:43.51#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.173.18:06:43.51#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.18:06:43.51#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.18:06:43.51$vck44/valo=2,534.99 2006.173.18:06:43.51#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.18:06:43.51#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.18:06:43.51#ibcon#ireg 17 cls_cnt 0 2006.173.18:06:43.51#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.18:06:43.51#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.18:06:43.51#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.18:06:43.51#ibcon#enter wrdev, iclass 39, count 0 2006.173.18:06:43.51#ibcon#first serial, iclass 39, count 0 2006.173.18:06:43.51#ibcon#enter sib2, iclass 39, count 0 2006.173.18:06:43.51#ibcon#flushed, iclass 39, count 0 2006.173.18:06:43.51#ibcon#about to write, iclass 39, count 0 2006.173.18:06:43.51#ibcon#wrote, iclass 39, count 0 2006.173.18:06:43.51#ibcon#about to read 3, iclass 39, count 0 2006.173.18:06:43.53#ibcon#read 3, iclass 39, count 0 2006.173.18:06:43.53#ibcon#about to read 4, iclass 39, count 0 2006.173.18:06:43.53#ibcon#read 4, iclass 39, count 0 2006.173.18:06:43.53#ibcon#about to read 5, iclass 39, count 0 2006.173.18:06:43.53#ibcon#read 5, iclass 39, count 0 2006.173.18:06:43.53#ibcon#about to read 6, iclass 39, count 0 2006.173.18:06:43.53#ibcon#read 6, iclass 39, count 0 2006.173.18:06:43.53#ibcon#end of sib2, iclass 39, count 0 2006.173.18:06:43.53#ibcon#*mode == 0, iclass 39, count 0 2006.173.18:06:43.53#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.18:06:43.53#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.18:06:43.53#ibcon#*before write, iclass 39, count 0 2006.173.18:06:43.53#ibcon#enter sib2, iclass 39, count 0 2006.173.18:06:43.53#ibcon#flushed, iclass 39, count 0 2006.173.18:06:43.53#ibcon#about to write, iclass 39, count 0 2006.173.18:06:43.53#ibcon#wrote, iclass 39, count 0 2006.173.18:06:43.53#ibcon#about to read 3, iclass 39, count 0 2006.173.18:06:43.57#ibcon#read 3, iclass 39, count 0 2006.173.18:06:43.57#ibcon#about to read 4, iclass 39, count 0 2006.173.18:06:43.57#ibcon#read 4, iclass 39, count 0 2006.173.18:06:43.57#ibcon#about to read 5, iclass 39, count 0 2006.173.18:06:43.57#ibcon#read 5, iclass 39, count 0 2006.173.18:06:43.57#ibcon#about to read 6, iclass 39, count 0 2006.173.18:06:43.57#ibcon#read 6, iclass 39, count 0 2006.173.18:06:43.57#ibcon#end of sib2, iclass 39, count 0 2006.173.18:06:43.57#ibcon#*after write, iclass 39, count 0 2006.173.18:06:43.57#ibcon#*before return 0, iclass 39, count 0 2006.173.18:06:43.57#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.18:06:43.57#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.18:06:43.57#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.18:06:43.57#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.18:06:43.57$vck44/va=2,6 2006.173.18:06:43.57#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.18:06:43.57#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.18:06:43.57#ibcon#ireg 11 cls_cnt 2 2006.173.18:06:43.57#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.18:06:43.63#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.18:06:43.63#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.18:06:43.63#ibcon#enter wrdev, iclass 3, count 2 2006.173.18:06:43.63#ibcon#first serial, iclass 3, count 2 2006.173.18:06:43.63#ibcon#enter sib2, iclass 3, count 2 2006.173.18:06:43.63#ibcon#flushed, iclass 3, count 2 2006.173.18:06:43.63#ibcon#about to write, iclass 3, count 2 2006.173.18:06:43.63#ibcon#wrote, iclass 3, count 2 2006.173.18:06:43.63#ibcon#about to read 3, iclass 3, count 2 2006.173.18:06:43.65#ibcon#read 3, iclass 3, count 2 2006.173.18:06:43.65#ibcon#about to read 4, iclass 3, count 2 2006.173.18:06:43.65#ibcon#read 4, iclass 3, count 2 2006.173.18:06:43.65#ibcon#about to read 5, iclass 3, count 2 2006.173.18:06:43.65#ibcon#read 5, iclass 3, count 2 2006.173.18:06:43.65#ibcon#about to read 6, iclass 3, count 2 2006.173.18:06:43.65#ibcon#read 6, iclass 3, count 2 2006.173.18:06:43.65#ibcon#end of sib2, iclass 3, count 2 2006.173.18:06:43.65#ibcon#*mode == 0, iclass 3, count 2 2006.173.18:06:43.65#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.18:06:43.65#ibcon#[25=AT02-06\r\n] 2006.173.18:06:43.65#ibcon#*before write, iclass 3, count 2 2006.173.18:06:43.65#ibcon#enter sib2, iclass 3, count 2 2006.173.18:06:43.65#ibcon#flushed, iclass 3, count 2 2006.173.18:06:43.65#ibcon#about to write, iclass 3, count 2 2006.173.18:06:43.65#ibcon#wrote, iclass 3, count 2 2006.173.18:06:43.65#ibcon#about to read 3, iclass 3, count 2 2006.173.18:06:43.68#ibcon#read 3, iclass 3, count 2 2006.173.18:06:43.68#ibcon#about to read 4, iclass 3, count 2 2006.173.18:06:43.68#ibcon#read 4, iclass 3, count 2 2006.173.18:06:43.68#ibcon#about to read 5, iclass 3, count 2 2006.173.18:06:43.68#ibcon#read 5, iclass 3, count 2 2006.173.18:06:43.68#ibcon#about to read 6, iclass 3, count 2 2006.173.18:06:43.68#ibcon#read 6, iclass 3, count 2 2006.173.18:06:43.68#ibcon#end of sib2, iclass 3, count 2 2006.173.18:06:43.68#ibcon#*after write, iclass 3, count 2 2006.173.18:06:43.68#ibcon#*before return 0, iclass 3, count 2 2006.173.18:06:43.68#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.18:06:43.68#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.18:06:43.68#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.18:06:43.68#ibcon#ireg 7 cls_cnt 0 2006.173.18:06:43.68#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.18:06:43.80#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.18:06:43.80#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.18:06:43.80#ibcon#enter wrdev, iclass 3, count 0 2006.173.18:06:43.80#ibcon#first serial, iclass 3, count 0 2006.173.18:06:43.80#ibcon#enter sib2, iclass 3, count 0 2006.173.18:06:43.80#ibcon#flushed, iclass 3, count 0 2006.173.18:06:43.80#ibcon#about to write, iclass 3, count 0 2006.173.18:06:43.80#ibcon#wrote, iclass 3, count 0 2006.173.18:06:43.80#ibcon#about to read 3, iclass 3, count 0 2006.173.18:06:43.82#ibcon#read 3, iclass 3, count 0 2006.173.18:06:43.82#ibcon#about to read 4, iclass 3, count 0 2006.173.18:06:43.82#ibcon#read 4, iclass 3, count 0 2006.173.18:06:43.82#ibcon#about to read 5, iclass 3, count 0 2006.173.18:06:43.82#ibcon#read 5, iclass 3, count 0 2006.173.18:06:43.82#ibcon#about to read 6, iclass 3, count 0 2006.173.18:06:43.82#ibcon#read 6, iclass 3, count 0 2006.173.18:06:43.82#ibcon#end of sib2, iclass 3, count 0 2006.173.18:06:43.82#ibcon#*mode == 0, iclass 3, count 0 2006.173.18:06:43.82#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.18:06:43.82#ibcon#[25=USB\r\n] 2006.173.18:06:43.82#ibcon#*before write, iclass 3, count 0 2006.173.18:06:43.82#ibcon#enter sib2, iclass 3, count 0 2006.173.18:06:43.82#ibcon#flushed, iclass 3, count 0 2006.173.18:06:43.82#ibcon#about to write, iclass 3, count 0 2006.173.18:06:43.82#ibcon#wrote, iclass 3, count 0 2006.173.18:06:43.82#ibcon#about to read 3, iclass 3, count 0 2006.173.18:06:43.85#ibcon#read 3, iclass 3, count 0 2006.173.18:06:43.85#ibcon#about to read 4, iclass 3, count 0 2006.173.18:06:43.85#ibcon#read 4, iclass 3, count 0 2006.173.18:06:43.85#ibcon#about to read 5, iclass 3, count 0 2006.173.18:06:43.85#ibcon#read 5, iclass 3, count 0 2006.173.18:06:43.85#ibcon#about to read 6, iclass 3, count 0 2006.173.18:06:43.85#ibcon#read 6, iclass 3, count 0 2006.173.18:06:43.85#ibcon#end of sib2, iclass 3, count 0 2006.173.18:06:43.85#ibcon#*after write, iclass 3, count 0 2006.173.18:06:43.85#ibcon#*before return 0, iclass 3, count 0 2006.173.18:06:43.85#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.18:06:43.85#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.18:06:43.85#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.18:06:43.85#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.18:06:43.85$vck44/valo=3,564.99 2006.173.18:06:43.85#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.18:06:43.85#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.18:06:43.85#ibcon#ireg 17 cls_cnt 0 2006.173.18:06:43.85#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.18:06:43.85#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.18:06:43.85#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.18:06:43.85#ibcon#enter wrdev, iclass 5, count 0 2006.173.18:06:43.85#ibcon#first serial, iclass 5, count 0 2006.173.18:06:43.85#ibcon#enter sib2, iclass 5, count 0 2006.173.18:06:43.85#ibcon#flushed, iclass 5, count 0 2006.173.18:06:43.85#ibcon#about to write, iclass 5, count 0 2006.173.18:06:43.85#ibcon#wrote, iclass 5, count 0 2006.173.18:06:43.85#ibcon#about to read 3, iclass 5, count 0 2006.173.18:06:43.87#ibcon#read 3, iclass 5, count 0 2006.173.18:06:43.87#ibcon#about to read 4, iclass 5, count 0 2006.173.18:06:43.87#ibcon#read 4, iclass 5, count 0 2006.173.18:06:43.87#ibcon#about to read 5, iclass 5, count 0 2006.173.18:06:43.87#ibcon#read 5, iclass 5, count 0 2006.173.18:06:43.87#ibcon#about to read 6, iclass 5, count 0 2006.173.18:06:43.87#ibcon#read 6, iclass 5, count 0 2006.173.18:06:43.87#ibcon#end of sib2, iclass 5, count 0 2006.173.18:06:43.87#ibcon#*mode == 0, iclass 5, count 0 2006.173.18:06:43.87#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.18:06:43.87#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.18:06:43.87#ibcon#*before write, iclass 5, count 0 2006.173.18:06:43.87#ibcon#enter sib2, iclass 5, count 0 2006.173.18:06:43.87#ibcon#flushed, iclass 5, count 0 2006.173.18:06:43.87#ibcon#about to write, iclass 5, count 0 2006.173.18:06:43.87#ibcon#wrote, iclass 5, count 0 2006.173.18:06:43.87#ibcon#about to read 3, iclass 5, count 0 2006.173.18:06:43.91#ibcon#read 3, iclass 5, count 0 2006.173.18:06:43.91#ibcon#about to read 4, iclass 5, count 0 2006.173.18:06:43.91#ibcon#read 4, iclass 5, count 0 2006.173.18:06:43.91#ibcon#about to read 5, iclass 5, count 0 2006.173.18:06:43.91#ibcon#read 5, iclass 5, count 0 2006.173.18:06:43.91#ibcon#about to read 6, iclass 5, count 0 2006.173.18:06:43.91#ibcon#read 6, iclass 5, count 0 2006.173.18:06:43.91#ibcon#end of sib2, iclass 5, count 0 2006.173.18:06:43.91#ibcon#*after write, iclass 5, count 0 2006.173.18:06:43.91#ibcon#*before return 0, iclass 5, count 0 2006.173.18:06:43.91#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.18:06:43.91#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.18:06:43.91#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.18:06:43.91#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.18:06:43.91$vck44/va=3,5 2006.173.18:06:43.91#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.173.18:06:43.91#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.173.18:06:43.91#ibcon#ireg 11 cls_cnt 2 2006.173.18:06:43.91#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.18:06:43.97#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.18:06:43.97#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.18:06:43.97#ibcon#enter wrdev, iclass 7, count 2 2006.173.18:06:43.97#ibcon#first serial, iclass 7, count 2 2006.173.18:06:43.97#ibcon#enter sib2, iclass 7, count 2 2006.173.18:06:43.97#ibcon#flushed, iclass 7, count 2 2006.173.18:06:43.97#ibcon#about to write, iclass 7, count 2 2006.173.18:06:43.97#ibcon#wrote, iclass 7, count 2 2006.173.18:06:43.97#ibcon#about to read 3, iclass 7, count 2 2006.173.18:06:43.99#ibcon#read 3, iclass 7, count 2 2006.173.18:06:43.99#ibcon#about to read 4, iclass 7, count 2 2006.173.18:06:43.99#ibcon#read 4, iclass 7, count 2 2006.173.18:06:43.99#ibcon#about to read 5, iclass 7, count 2 2006.173.18:06:43.99#ibcon#read 5, iclass 7, count 2 2006.173.18:06:43.99#ibcon#about to read 6, iclass 7, count 2 2006.173.18:06:43.99#ibcon#read 6, iclass 7, count 2 2006.173.18:06:43.99#ibcon#end of sib2, iclass 7, count 2 2006.173.18:06:43.99#ibcon#*mode == 0, iclass 7, count 2 2006.173.18:06:43.99#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.173.18:06:43.99#ibcon#[25=AT03-05\r\n] 2006.173.18:06:43.99#ibcon#*before write, iclass 7, count 2 2006.173.18:06:43.99#ibcon#enter sib2, iclass 7, count 2 2006.173.18:06:43.99#ibcon#flushed, iclass 7, count 2 2006.173.18:06:43.99#ibcon#about to write, iclass 7, count 2 2006.173.18:06:43.99#ibcon#wrote, iclass 7, count 2 2006.173.18:06:43.99#ibcon#about to read 3, iclass 7, count 2 2006.173.18:06:44.02#ibcon#read 3, iclass 7, count 2 2006.173.18:06:44.02#ibcon#about to read 4, iclass 7, count 2 2006.173.18:06:44.02#ibcon#read 4, iclass 7, count 2 2006.173.18:06:44.02#ibcon#about to read 5, iclass 7, count 2 2006.173.18:06:44.02#ibcon#read 5, iclass 7, count 2 2006.173.18:06:44.02#ibcon#about to read 6, iclass 7, count 2 2006.173.18:06:44.02#ibcon#read 6, iclass 7, count 2 2006.173.18:06:44.02#ibcon#end of sib2, iclass 7, count 2 2006.173.18:06:44.02#ibcon#*after write, iclass 7, count 2 2006.173.18:06:44.02#ibcon#*before return 0, iclass 7, count 2 2006.173.18:06:44.02#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.18:06:44.02#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.173.18:06:44.02#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.173.18:06:44.02#ibcon#ireg 7 cls_cnt 0 2006.173.18:06:44.02#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.18:06:44.14#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.18:06:44.14#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.18:06:44.14#ibcon#enter wrdev, iclass 7, count 0 2006.173.18:06:44.14#ibcon#first serial, iclass 7, count 0 2006.173.18:06:44.14#ibcon#enter sib2, iclass 7, count 0 2006.173.18:06:44.14#ibcon#flushed, iclass 7, count 0 2006.173.18:06:44.14#ibcon#about to write, iclass 7, count 0 2006.173.18:06:44.14#ibcon#wrote, iclass 7, count 0 2006.173.18:06:44.14#ibcon#about to read 3, iclass 7, count 0 2006.173.18:06:44.16#ibcon#read 3, iclass 7, count 0 2006.173.18:06:44.16#ibcon#about to read 4, iclass 7, count 0 2006.173.18:06:44.16#ibcon#read 4, iclass 7, count 0 2006.173.18:06:44.16#ibcon#about to read 5, iclass 7, count 0 2006.173.18:06:44.16#ibcon#read 5, iclass 7, count 0 2006.173.18:06:44.16#ibcon#about to read 6, iclass 7, count 0 2006.173.18:06:44.16#ibcon#read 6, iclass 7, count 0 2006.173.18:06:44.16#ibcon#end of sib2, iclass 7, count 0 2006.173.18:06:44.16#ibcon#*mode == 0, iclass 7, count 0 2006.173.18:06:44.16#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.18:06:44.16#ibcon#[25=USB\r\n] 2006.173.18:06:44.16#ibcon#*before write, iclass 7, count 0 2006.173.18:06:44.16#ibcon#enter sib2, iclass 7, count 0 2006.173.18:06:44.16#ibcon#flushed, iclass 7, count 0 2006.173.18:06:44.16#ibcon#about to write, iclass 7, count 0 2006.173.18:06:44.16#ibcon#wrote, iclass 7, count 0 2006.173.18:06:44.16#ibcon#about to read 3, iclass 7, count 0 2006.173.18:06:44.19#ibcon#read 3, iclass 7, count 0 2006.173.18:06:44.19#ibcon#about to read 4, iclass 7, count 0 2006.173.18:06:44.19#ibcon#read 4, iclass 7, count 0 2006.173.18:06:44.19#ibcon#about to read 5, iclass 7, count 0 2006.173.18:06:44.19#ibcon#read 5, iclass 7, count 0 2006.173.18:06:44.19#ibcon#about to read 6, iclass 7, count 0 2006.173.18:06:44.19#ibcon#read 6, iclass 7, count 0 2006.173.18:06:44.19#ibcon#end of sib2, iclass 7, count 0 2006.173.18:06:44.19#ibcon#*after write, iclass 7, count 0 2006.173.18:06:44.19#ibcon#*before return 0, iclass 7, count 0 2006.173.18:06:44.19#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.18:06:44.19#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.173.18:06:44.19#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.18:06:44.19#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.18:06:44.19$vck44/valo=4,624.99 2006.173.18:06:44.19#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.18:06:44.19#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.18:06:44.19#ibcon#ireg 17 cls_cnt 0 2006.173.18:06:44.19#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.18:06:44.19#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.18:06:44.19#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.18:06:44.19#ibcon#enter wrdev, iclass 11, count 0 2006.173.18:06:44.19#ibcon#first serial, iclass 11, count 0 2006.173.18:06:44.19#ibcon#enter sib2, iclass 11, count 0 2006.173.18:06:44.19#ibcon#flushed, iclass 11, count 0 2006.173.18:06:44.19#ibcon#about to write, iclass 11, count 0 2006.173.18:06:44.19#ibcon#wrote, iclass 11, count 0 2006.173.18:06:44.19#ibcon#about to read 3, iclass 11, count 0 2006.173.18:06:44.21#ibcon#read 3, iclass 11, count 0 2006.173.18:06:44.21#ibcon#about to read 4, iclass 11, count 0 2006.173.18:06:44.21#ibcon#read 4, iclass 11, count 0 2006.173.18:06:44.21#ibcon#about to read 5, iclass 11, count 0 2006.173.18:06:44.21#ibcon#read 5, iclass 11, count 0 2006.173.18:06:44.21#ibcon#about to read 6, iclass 11, count 0 2006.173.18:06:44.21#ibcon#read 6, iclass 11, count 0 2006.173.18:06:44.21#ibcon#end of sib2, iclass 11, count 0 2006.173.18:06:44.21#ibcon#*mode == 0, iclass 11, count 0 2006.173.18:06:44.21#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.18:06:44.21#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.18:06:44.21#ibcon#*before write, iclass 11, count 0 2006.173.18:06:44.21#ibcon#enter sib2, iclass 11, count 0 2006.173.18:06:44.21#ibcon#flushed, iclass 11, count 0 2006.173.18:06:44.21#ibcon#about to write, iclass 11, count 0 2006.173.18:06:44.21#ibcon#wrote, iclass 11, count 0 2006.173.18:06:44.21#ibcon#about to read 3, iclass 11, count 0 2006.173.18:06:44.25#ibcon#read 3, iclass 11, count 0 2006.173.18:06:44.25#ibcon#about to read 4, iclass 11, count 0 2006.173.18:06:44.25#ibcon#read 4, iclass 11, count 0 2006.173.18:06:44.25#ibcon#about to read 5, iclass 11, count 0 2006.173.18:06:44.25#ibcon#read 5, iclass 11, count 0 2006.173.18:06:44.25#ibcon#about to read 6, iclass 11, count 0 2006.173.18:06:44.25#ibcon#read 6, iclass 11, count 0 2006.173.18:06:44.25#ibcon#end of sib2, iclass 11, count 0 2006.173.18:06:44.25#ibcon#*after write, iclass 11, count 0 2006.173.18:06:44.25#ibcon#*before return 0, iclass 11, count 0 2006.173.18:06:44.25#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.18:06:44.25#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.18:06:44.25#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.18:06:44.25#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.18:06:44.25$vck44/va=4,6 2006.173.18:06:44.25#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.173.18:06:44.25#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.173.18:06:44.25#ibcon#ireg 11 cls_cnt 2 2006.173.18:06:44.25#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.18:06:44.31#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.18:06:44.31#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.18:06:44.31#ibcon#enter wrdev, iclass 13, count 2 2006.173.18:06:44.31#ibcon#first serial, iclass 13, count 2 2006.173.18:06:44.31#ibcon#enter sib2, iclass 13, count 2 2006.173.18:06:44.31#ibcon#flushed, iclass 13, count 2 2006.173.18:06:44.31#ibcon#about to write, iclass 13, count 2 2006.173.18:06:44.31#ibcon#wrote, iclass 13, count 2 2006.173.18:06:44.31#ibcon#about to read 3, iclass 13, count 2 2006.173.18:06:44.33#ibcon#read 3, iclass 13, count 2 2006.173.18:06:44.33#ibcon#about to read 4, iclass 13, count 2 2006.173.18:06:44.33#ibcon#read 4, iclass 13, count 2 2006.173.18:06:44.33#ibcon#about to read 5, iclass 13, count 2 2006.173.18:06:44.33#ibcon#read 5, iclass 13, count 2 2006.173.18:06:44.33#ibcon#about to read 6, iclass 13, count 2 2006.173.18:06:44.33#ibcon#read 6, iclass 13, count 2 2006.173.18:06:44.33#ibcon#end of sib2, iclass 13, count 2 2006.173.18:06:44.33#ibcon#*mode == 0, iclass 13, count 2 2006.173.18:06:44.33#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.173.18:06:44.33#ibcon#[25=AT04-06\r\n] 2006.173.18:06:44.33#ibcon#*before write, iclass 13, count 2 2006.173.18:06:44.33#ibcon#enter sib2, iclass 13, count 2 2006.173.18:06:44.33#ibcon#flushed, iclass 13, count 2 2006.173.18:06:44.33#ibcon#about to write, iclass 13, count 2 2006.173.18:06:44.33#ibcon#wrote, iclass 13, count 2 2006.173.18:06:44.33#ibcon#about to read 3, iclass 13, count 2 2006.173.18:06:44.36#ibcon#read 3, iclass 13, count 2 2006.173.18:06:44.36#ibcon#about to read 4, iclass 13, count 2 2006.173.18:06:44.36#ibcon#read 4, iclass 13, count 2 2006.173.18:06:44.36#ibcon#about to read 5, iclass 13, count 2 2006.173.18:06:44.36#ibcon#read 5, iclass 13, count 2 2006.173.18:06:44.36#ibcon#about to read 6, iclass 13, count 2 2006.173.18:06:44.36#ibcon#read 6, iclass 13, count 2 2006.173.18:06:44.36#ibcon#end of sib2, iclass 13, count 2 2006.173.18:06:44.36#ibcon#*after write, iclass 13, count 2 2006.173.18:06:44.36#ibcon#*before return 0, iclass 13, count 2 2006.173.18:06:44.36#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.18:06:44.36#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.173.18:06:44.36#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.173.18:06:44.36#ibcon#ireg 7 cls_cnt 0 2006.173.18:06:44.36#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.18:06:44.48#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.18:06:44.48#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.18:06:44.48#ibcon#enter wrdev, iclass 13, count 0 2006.173.18:06:44.48#ibcon#first serial, iclass 13, count 0 2006.173.18:06:44.48#ibcon#enter sib2, iclass 13, count 0 2006.173.18:06:44.48#ibcon#flushed, iclass 13, count 0 2006.173.18:06:44.48#ibcon#about to write, iclass 13, count 0 2006.173.18:06:44.48#ibcon#wrote, iclass 13, count 0 2006.173.18:06:44.48#ibcon#about to read 3, iclass 13, count 0 2006.173.18:06:44.50#ibcon#read 3, iclass 13, count 0 2006.173.18:06:44.50#ibcon#about to read 4, iclass 13, count 0 2006.173.18:06:44.50#ibcon#read 4, iclass 13, count 0 2006.173.18:06:44.50#ibcon#about to read 5, iclass 13, count 0 2006.173.18:06:44.50#ibcon#read 5, iclass 13, count 0 2006.173.18:06:44.50#ibcon#about to read 6, iclass 13, count 0 2006.173.18:06:44.50#ibcon#read 6, iclass 13, count 0 2006.173.18:06:44.50#ibcon#end of sib2, iclass 13, count 0 2006.173.18:06:44.50#ibcon#*mode == 0, iclass 13, count 0 2006.173.18:06:44.50#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.18:06:44.50#ibcon#[25=USB\r\n] 2006.173.18:06:44.50#ibcon#*before write, iclass 13, count 0 2006.173.18:06:44.50#ibcon#enter sib2, iclass 13, count 0 2006.173.18:06:44.50#ibcon#flushed, iclass 13, count 0 2006.173.18:06:44.50#ibcon#about to write, iclass 13, count 0 2006.173.18:06:44.50#ibcon#wrote, iclass 13, count 0 2006.173.18:06:44.50#ibcon#about to read 3, iclass 13, count 0 2006.173.18:06:44.53#ibcon#read 3, iclass 13, count 0 2006.173.18:06:44.53#ibcon#about to read 4, iclass 13, count 0 2006.173.18:06:44.53#ibcon#read 4, iclass 13, count 0 2006.173.18:06:44.53#ibcon#about to read 5, iclass 13, count 0 2006.173.18:06:44.53#ibcon#read 5, iclass 13, count 0 2006.173.18:06:44.53#ibcon#about to read 6, iclass 13, count 0 2006.173.18:06:44.53#ibcon#read 6, iclass 13, count 0 2006.173.18:06:44.53#ibcon#end of sib2, iclass 13, count 0 2006.173.18:06:44.53#ibcon#*after write, iclass 13, count 0 2006.173.18:06:44.53#ibcon#*before return 0, iclass 13, count 0 2006.173.18:06:44.53#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.18:06:44.53#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.173.18:06:44.53#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.18:06:44.53#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.18:06:44.53$vck44/valo=5,734.99 2006.173.18:06:44.53#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.18:06:44.53#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.18:06:44.53#ibcon#ireg 17 cls_cnt 0 2006.173.18:06:44.53#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.18:06:44.53#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.18:06:44.53#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.18:06:44.53#ibcon#enter wrdev, iclass 15, count 0 2006.173.18:06:44.53#ibcon#first serial, iclass 15, count 0 2006.173.18:06:44.53#ibcon#enter sib2, iclass 15, count 0 2006.173.18:06:44.53#ibcon#flushed, iclass 15, count 0 2006.173.18:06:44.53#ibcon#about to write, iclass 15, count 0 2006.173.18:06:44.53#ibcon#wrote, iclass 15, count 0 2006.173.18:06:44.53#ibcon#about to read 3, iclass 15, count 0 2006.173.18:06:44.55#ibcon#read 3, iclass 15, count 0 2006.173.18:06:44.55#ibcon#about to read 4, iclass 15, count 0 2006.173.18:06:44.55#ibcon#read 4, iclass 15, count 0 2006.173.18:06:44.55#ibcon#about to read 5, iclass 15, count 0 2006.173.18:06:44.55#ibcon#read 5, iclass 15, count 0 2006.173.18:06:44.55#ibcon#about to read 6, iclass 15, count 0 2006.173.18:06:44.55#ibcon#read 6, iclass 15, count 0 2006.173.18:06:44.55#ibcon#end of sib2, iclass 15, count 0 2006.173.18:06:44.55#ibcon#*mode == 0, iclass 15, count 0 2006.173.18:06:44.55#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.18:06:44.55#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.18:06:44.55#ibcon#*before write, iclass 15, count 0 2006.173.18:06:44.55#ibcon#enter sib2, iclass 15, count 0 2006.173.18:06:44.55#ibcon#flushed, iclass 15, count 0 2006.173.18:06:44.55#ibcon#about to write, iclass 15, count 0 2006.173.18:06:44.55#ibcon#wrote, iclass 15, count 0 2006.173.18:06:44.55#ibcon#about to read 3, iclass 15, count 0 2006.173.18:06:44.59#ibcon#read 3, iclass 15, count 0 2006.173.18:06:44.59#ibcon#about to read 4, iclass 15, count 0 2006.173.18:06:44.59#ibcon#read 4, iclass 15, count 0 2006.173.18:06:44.59#ibcon#about to read 5, iclass 15, count 0 2006.173.18:06:44.59#ibcon#read 5, iclass 15, count 0 2006.173.18:06:44.59#ibcon#about to read 6, iclass 15, count 0 2006.173.18:06:44.59#ibcon#read 6, iclass 15, count 0 2006.173.18:06:44.59#ibcon#end of sib2, iclass 15, count 0 2006.173.18:06:44.59#ibcon#*after write, iclass 15, count 0 2006.173.18:06:44.59#ibcon#*before return 0, iclass 15, count 0 2006.173.18:06:44.59#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.18:06:44.59#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.18:06:44.59#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.18:06:44.59#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.18:06:44.59$vck44/va=5,4 2006.173.18:06:44.59#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.18:06:44.59#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.18:06:44.59#ibcon#ireg 11 cls_cnt 2 2006.173.18:06:44.59#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.18:06:44.65#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.18:06:44.65#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.18:06:44.65#ibcon#enter wrdev, iclass 17, count 2 2006.173.18:06:44.65#ibcon#first serial, iclass 17, count 2 2006.173.18:06:44.65#ibcon#enter sib2, iclass 17, count 2 2006.173.18:06:44.65#ibcon#flushed, iclass 17, count 2 2006.173.18:06:44.65#ibcon#about to write, iclass 17, count 2 2006.173.18:06:44.65#ibcon#wrote, iclass 17, count 2 2006.173.18:06:44.65#ibcon#about to read 3, iclass 17, count 2 2006.173.18:06:44.67#ibcon#read 3, iclass 17, count 2 2006.173.18:06:44.67#ibcon#about to read 4, iclass 17, count 2 2006.173.18:06:44.67#ibcon#read 4, iclass 17, count 2 2006.173.18:06:44.67#ibcon#about to read 5, iclass 17, count 2 2006.173.18:06:44.67#ibcon#read 5, iclass 17, count 2 2006.173.18:06:44.67#ibcon#about to read 6, iclass 17, count 2 2006.173.18:06:44.67#ibcon#read 6, iclass 17, count 2 2006.173.18:06:44.67#ibcon#end of sib2, iclass 17, count 2 2006.173.18:06:44.67#ibcon#*mode == 0, iclass 17, count 2 2006.173.18:06:44.67#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.18:06:44.67#ibcon#[25=AT05-04\r\n] 2006.173.18:06:44.67#ibcon#*before write, iclass 17, count 2 2006.173.18:06:44.67#ibcon#enter sib2, iclass 17, count 2 2006.173.18:06:44.67#ibcon#flushed, iclass 17, count 2 2006.173.18:06:44.67#ibcon#about to write, iclass 17, count 2 2006.173.18:06:44.67#ibcon#wrote, iclass 17, count 2 2006.173.18:06:44.67#ibcon#about to read 3, iclass 17, count 2 2006.173.18:06:44.70#ibcon#read 3, iclass 17, count 2 2006.173.18:06:44.70#ibcon#about to read 4, iclass 17, count 2 2006.173.18:06:44.70#ibcon#read 4, iclass 17, count 2 2006.173.18:06:44.70#ibcon#about to read 5, iclass 17, count 2 2006.173.18:06:44.70#ibcon#read 5, iclass 17, count 2 2006.173.18:06:44.70#ibcon#about to read 6, iclass 17, count 2 2006.173.18:06:44.70#ibcon#read 6, iclass 17, count 2 2006.173.18:06:44.70#ibcon#end of sib2, iclass 17, count 2 2006.173.18:06:44.70#ibcon#*after write, iclass 17, count 2 2006.173.18:06:44.70#ibcon#*before return 0, iclass 17, count 2 2006.173.18:06:44.70#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.18:06:44.70#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.18:06:44.70#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.18:06:44.70#ibcon#ireg 7 cls_cnt 0 2006.173.18:06:44.70#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.18:06:44.82#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.18:06:44.82#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.18:06:44.82#ibcon#enter wrdev, iclass 17, count 0 2006.173.18:06:44.82#ibcon#first serial, iclass 17, count 0 2006.173.18:06:44.82#ibcon#enter sib2, iclass 17, count 0 2006.173.18:06:44.82#ibcon#flushed, iclass 17, count 0 2006.173.18:06:44.82#ibcon#about to write, iclass 17, count 0 2006.173.18:06:44.82#ibcon#wrote, iclass 17, count 0 2006.173.18:06:44.82#ibcon#about to read 3, iclass 17, count 0 2006.173.18:06:44.84#ibcon#read 3, iclass 17, count 0 2006.173.18:06:44.84#ibcon#about to read 4, iclass 17, count 0 2006.173.18:06:44.84#ibcon#read 4, iclass 17, count 0 2006.173.18:06:44.84#ibcon#about to read 5, iclass 17, count 0 2006.173.18:06:44.84#ibcon#read 5, iclass 17, count 0 2006.173.18:06:44.84#ibcon#about to read 6, iclass 17, count 0 2006.173.18:06:44.84#ibcon#read 6, iclass 17, count 0 2006.173.18:06:44.84#ibcon#end of sib2, iclass 17, count 0 2006.173.18:06:44.84#ibcon#*mode == 0, iclass 17, count 0 2006.173.18:06:44.84#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.18:06:44.84#ibcon#[25=USB\r\n] 2006.173.18:06:44.84#ibcon#*before write, iclass 17, count 0 2006.173.18:06:44.84#ibcon#enter sib2, iclass 17, count 0 2006.173.18:06:44.84#ibcon#flushed, iclass 17, count 0 2006.173.18:06:44.84#ibcon#about to write, iclass 17, count 0 2006.173.18:06:44.84#ibcon#wrote, iclass 17, count 0 2006.173.18:06:44.84#ibcon#about to read 3, iclass 17, count 0 2006.173.18:06:44.87#ibcon#read 3, iclass 17, count 0 2006.173.18:06:44.87#ibcon#about to read 4, iclass 17, count 0 2006.173.18:06:44.87#ibcon#read 4, iclass 17, count 0 2006.173.18:06:44.87#ibcon#about to read 5, iclass 17, count 0 2006.173.18:06:44.87#ibcon#read 5, iclass 17, count 0 2006.173.18:06:44.87#ibcon#about to read 6, iclass 17, count 0 2006.173.18:06:44.87#ibcon#read 6, iclass 17, count 0 2006.173.18:06:44.87#ibcon#end of sib2, iclass 17, count 0 2006.173.18:06:44.87#ibcon#*after write, iclass 17, count 0 2006.173.18:06:44.87#ibcon#*before return 0, iclass 17, count 0 2006.173.18:06:44.87#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.18:06:44.87#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.18:06:44.87#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.18:06:44.87#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.18:06:44.87$vck44/valo=6,814.99 2006.173.18:06:44.87#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.18:06:44.87#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.18:06:44.87#ibcon#ireg 17 cls_cnt 0 2006.173.18:06:44.87#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.18:06:44.87#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.18:06:44.87#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.18:06:44.87#ibcon#enter wrdev, iclass 19, count 0 2006.173.18:06:44.87#ibcon#first serial, iclass 19, count 0 2006.173.18:06:44.87#ibcon#enter sib2, iclass 19, count 0 2006.173.18:06:44.87#ibcon#flushed, iclass 19, count 0 2006.173.18:06:44.87#ibcon#about to write, iclass 19, count 0 2006.173.18:06:44.87#ibcon#wrote, iclass 19, count 0 2006.173.18:06:44.87#ibcon#about to read 3, iclass 19, count 0 2006.173.18:06:44.89#ibcon#read 3, iclass 19, count 0 2006.173.18:06:44.89#ibcon#about to read 4, iclass 19, count 0 2006.173.18:06:44.89#ibcon#read 4, iclass 19, count 0 2006.173.18:06:44.89#ibcon#about to read 5, iclass 19, count 0 2006.173.18:06:44.89#ibcon#read 5, iclass 19, count 0 2006.173.18:06:44.89#ibcon#about to read 6, iclass 19, count 0 2006.173.18:06:44.89#ibcon#read 6, iclass 19, count 0 2006.173.18:06:44.89#ibcon#end of sib2, iclass 19, count 0 2006.173.18:06:44.89#ibcon#*mode == 0, iclass 19, count 0 2006.173.18:06:44.89#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.18:06:44.89#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.18:06:44.89#ibcon#*before write, iclass 19, count 0 2006.173.18:06:44.89#ibcon#enter sib2, iclass 19, count 0 2006.173.18:06:44.89#ibcon#flushed, iclass 19, count 0 2006.173.18:06:44.89#ibcon#about to write, iclass 19, count 0 2006.173.18:06:44.89#ibcon#wrote, iclass 19, count 0 2006.173.18:06:44.89#ibcon#about to read 3, iclass 19, count 0 2006.173.18:06:44.93#ibcon#read 3, iclass 19, count 0 2006.173.18:06:44.93#ibcon#about to read 4, iclass 19, count 0 2006.173.18:06:44.93#ibcon#read 4, iclass 19, count 0 2006.173.18:06:44.93#ibcon#about to read 5, iclass 19, count 0 2006.173.18:06:44.93#ibcon#read 5, iclass 19, count 0 2006.173.18:06:44.93#ibcon#about to read 6, iclass 19, count 0 2006.173.18:06:44.93#ibcon#read 6, iclass 19, count 0 2006.173.18:06:44.93#ibcon#end of sib2, iclass 19, count 0 2006.173.18:06:44.93#ibcon#*after write, iclass 19, count 0 2006.173.18:06:44.93#ibcon#*before return 0, iclass 19, count 0 2006.173.18:06:44.93#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.18:06:44.93#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.18:06:44.93#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.18:06:44.93#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.18:06:44.93$vck44/va=6,3 2006.173.18:06:44.93#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.18:06:44.93#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.18:06:44.93#ibcon#ireg 11 cls_cnt 2 2006.173.18:06:44.93#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.18:06:44.99#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.18:06:44.99#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.18:06:44.99#ibcon#enter wrdev, iclass 21, count 2 2006.173.18:06:44.99#ibcon#first serial, iclass 21, count 2 2006.173.18:06:44.99#ibcon#enter sib2, iclass 21, count 2 2006.173.18:06:44.99#ibcon#flushed, iclass 21, count 2 2006.173.18:06:44.99#ibcon#about to write, iclass 21, count 2 2006.173.18:06:44.99#ibcon#wrote, iclass 21, count 2 2006.173.18:06:44.99#ibcon#about to read 3, iclass 21, count 2 2006.173.18:06:45.01#ibcon#read 3, iclass 21, count 2 2006.173.18:06:45.01#ibcon#about to read 4, iclass 21, count 2 2006.173.18:06:45.01#ibcon#read 4, iclass 21, count 2 2006.173.18:06:45.01#ibcon#about to read 5, iclass 21, count 2 2006.173.18:06:45.01#ibcon#read 5, iclass 21, count 2 2006.173.18:06:45.01#ibcon#about to read 6, iclass 21, count 2 2006.173.18:06:45.01#ibcon#read 6, iclass 21, count 2 2006.173.18:06:45.01#ibcon#end of sib2, iclass 21, count 2 2006.173.18:06:45.01#ibcon#*mode == 0, iclass 21, count 2 2006.173.18:06:45.01#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.18:06:45.01#ibcon#[25=AT06-03\r\n] 2006.173.18:06:45.01#ibcon#*before write, iclass 21, count 2 2006.173.18:06:45.01#ibcon#enter sib2, iclass 21, count 2 2006.173.18:06:45.01#ibcon#flushed, iclass 21, count 2 2006.173.18:06:45.01#ibcon#about to write, iclass 21, count 2 2006.173.18:06:45.01#ibcon#wrote, iclass 21, count 2 2006.173.18:06:45.01#ibcon#about to read 3, iclass 21, count 2 2006.173.18:06:45.04#ibcon#read 3, iclass 21, count 2 2006.173.18:06:45.04#ibcon#about to read 4, iclass 21, count 2 2006.173.18:06:45.04#ibcon#read 4, iclass 21, count 2 2006.173.18:06:45.04#ibcon#about to read 5, iclass 21, count 2 2006.173.18:06:45.04#ibcon#read 5, iclass 21, count 2 2006.173.18:06:45.04#ibcon#about to read 6, iclass 21, count 2 2006.173.18:06:45.04#ibcon#read 6, iclass 21, count 2 2006.173.18:06:45.04#ibcon#end of sib2, iclass 21, count 2 2006.173.18:06:45.04#ibcon#*after write, iclass 21, count 2 2006.173.18:06:45.04#ibcon#*before return 0, iclass 21, count 2 2006.173.18:06:45.04#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.18:06:45.04#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.18:06:45.04#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.18:06:45.04#ibcon#ireg 7 cls_cnt 0 2006.173.18:06:45.04#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.18:06:45.16#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.18:06:45.16#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.18:06:45.16#ibcon#enter wrdev, iclass 21, count 0 2006.173.18:06:45.16#ibcon#first serial, iclass 21, count 0 2006.173.18:06:45.16#ibcon#enter sib2, iclass 21, count 0 2006.173.18:06:45.16#ibcon#flushed, iclass 21, count 0 2006.173.18:06:45.16#ibcon#about to write, iclass 21, count 0 2006.173.18:06:45.16#ibcon#wrote, iclass 21, count 0 2006.173.18:06:45.16#ibcon#about to read 3, iclass 21, count 0 2006.173.18:06:45.18#ibcon#read 3, iclass 21, count 0 2006.173.18:06:45.18#ibcon#about to read 4, iclass 21, count 0 2006.173.18:06:45.18#ibcon#read 4, iclass 21, count 0 2006.173.18:06:45.18#ibcon#about to read 5, iclass 21, count 0 2006.173.18:06:45.18#ibcon#read 5, iclass 21, count 0 2006.173.18:06:45.18#ibcon#about to read 6, iclass 21, count 0 2006.173.18:06:45.18#ibcon#read 6, iclass 21, count 0 2006.173.18:06:45.18#ibcon#end of sib2, iclass 21, count 0 2006.173.18:06:45.18#ibcon#*mode == 0, iclass 21, count 0 2006.173.18:06:45.18#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.18:06:45.18#ibcon#[25=USB\r\n] 2006.173.18:06:45.18#ibcon#*before write, iclass 21, count 0 2006.173.18:06:45.18#ibcon#enter sib2, iclass 21, count 0 2006.173.18:06:45.18#ibcon#flushed, iclass 21, count 0 2006.173.18:06:45.18#ibcon#about to write, iclass 21, count 0 2006.173.18:06:45.18#ibcon#wrote, iclass 21, count 0 2006.173.18:06:45.18#ibcon#about to read 3, iclass 21, count 0 2006.173.18:06:45.21#ibcon#read 3, iclass 21, count 0 2006.173.18:06:45.21#ibcon#about to read 4, iclass 21, count 0 2006.173.18:06:45.21#ibcon#read 4, iclass 21, count 0 2006.173.18:06:45.21#ibcon#about to read 5, iclass 21, count 0 2006.173.18:06:45.21#ibcon#read 5, iclass 21, count 0 2006.173.18:06:45.21#ibcon#about to read 6, iclass 21, count 0 2006.173.18:06:45.21#ibcon#read 6, iclass 21, count 0 2006.173.18:06:45.21#ibcon#end of sib2, iclass 21, count 0 2006.173.18:06:45.21#ibcon#*after write, iclass 21, count 0 2006.173.18:06:45.21#ibcon#*before return 0, iclass 21, count 0 2006.173.18:06:45.21#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.18:06:45.21#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.18:06:45.21#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.18:06:45.21#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.18:06:45.21$vck44/valo=7,864.99 2006.173.18:06:45.21#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.18:06:45.21#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.18:06:45.21#ibcon#ireg 17 cls_cnt 0 2006.173.18:06:45.21#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.18:06:45.21#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.18:06:45.21#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.18:06:45.21#ibcon#enter wrdev, iclass 23, count 0 2006.173.18:06:45.21#ibcon#first serial, iclass 23, count 0 2006.173.18:06:45.21#ibcon#enter sib2, iclass 23, count 0 2006.173.18:06:45.21#ibcon#flushed, iclass 23, count 0 2006.173.18:06:45.21#ibcon#about to write, iclass 23, count 0 2006.173.18:06:45.21#ibcon#wrote, iclass 23, count 0 2006.173.18:06:45.21#ibcon#about to read 3, iclass 23, count 0 2006.173.18:06:45.23#ibcon#read 3, iclass 23, count 0 2006.173.18:06:45.23#ibcon#about to read 4, iclass 23, count 0 2006.173.18:06:45.23#ibcon#read 4, iclass 23, count 0 2006.173.18:06:45.23#ibcon#about to read 5, iclass 23, count 0 2006.173.18:06:45.23#ibcon#read 5, iclass 23, count 0 2006.173.18:06:45.23#ibcon#about to read 6, iclass 23, count 0 2006.173.18:06:45.23#ibcon#read 6, iclass 23, count 0 2006.173.18:06:45.23#ibcon#end of sib2, iclass 23, count 0 2006.173.18:06:45.23#ibcon#*mode == 0, iclass 23, count 0 2006.173.18:06:45.23#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.18:06:45.23#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.18:06:45.23#ibcon#*before write, iclass 23, count 0 2006.173.18:06:45.23#ibcon#enter sib2, iclass 23, count 0 2006.173.18:06:45.23#ibcon#flushed, iclass 23, count 0 2006.173.18:06:45.23#ibcon#about to write, iclass 23, count 0 2006.173.18:06:45.23#ibcon#wrote, iclass 23, count 0 2006.173.18:06:45.23#ibcon#about to read 3, iclass 23, count 0 2006.173.18:06:45.27#ibcon#read 3, iclass 23, count 0 2006.173.18:06:45.27#ibcon#about to read 4, iclass 23, count 0 2006.173.18:06:45.27#ibcon#read 4, iclass 23, count 0 2006.173.18:06:45.27#ibcon#about to read 5, iclass 23, count 0 2006.173.18:06:45.27#ibcon#read 5, iclass 23, count 0 2006.173.18:06:45.27#ibcon#about to read 6, iclass 23, count 0 2006.173.18:06:45.27#ibcon#read 6, iclass 23, count 0 2006.173.18:06:45.27#ibcon#end of sib2, iclass 23, count 0 2006.173.18:06:45.27#ibcon#*after write, iclass 23, count 0 2006.173.18:06:45.27#ibcon#*before return 0, iclass 23, count 0 2006.173.18:06:45.27#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.18:06:45.27#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.18:06:45.27#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.18:06:45.27#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.18:06:45.27$vck44/va=7,4 2006.173.18:06:45.27#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.18:06:45.27#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.18:06:45.27#ibcon#ireg 11 cls_cnt 2 2006.173.18:06:45.27#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.18:06:45.33#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.18:06:45.33#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.18:06:45.33#ibcon#enter wrdev, iclass 25, count 2 2006.173.18:06:45.33#ibcon#first serial, iclass 25, count 2 2006.173.18:06:45.33#ibcon#enter sib2, iclass 25, count 2 2006.173.18:06:45.33#ibcon#flushed, iclass 25, count 2 2006.173.18:06:45.33#ibcon#about to write, iclass 25, count 2 2006.173.18:06:45.33#ibcon#wrote, iclass 25, count 2 2006.173.18:06:45.33#ibcon#about to read 3, iclass 25, count 2 2006.173.18:06:45.35#ibcon#read 3, iclass 25, count 2 2006.173.18:06:45.35#ibcon#about to read 4, iclass 25, count 2 2006.173.18:06:45.35#ibcon#read 4, iclass 25, count 2 2006.173.18:06:45.35#ibcon#about to read 5, iclass 25, count 2 2006.173.18:06:45.35#ibcon#read 5, iclass 25, count 2 2006.173.18:06:45.35#ibcon#about to read 6, iclass 25, count 2 2006.173.18:06:45.35#ibcon#read 6, iclass 25, count 2 2006.173.18:06:45.35#ibcon#end of sib2, iclass 25, count 2 2006.173.18:06:45.35#ibcon#*mode == 0, iclass 25, count 2 2006.173.18:06:45.35#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.18:06:45.35#ibcon#[25=AT07-04\r\n] 2006.173.18:06:45.35#ibcon#*before write, iclass 25, count 2 2006.173.18:06:45.35#ibcon#enter sib2, iclass 25, count 2 2006.173.18:06:45.35#ibcon#flushed, iclass 25, count 2 2006.173.18:06:45.35#ibcon#about to write, iclass 25, count 2 2006.173.18:06:45.35#ibcon#wrote, iclass 25, count 2 2006.173.18:06:45.35#ibcon#about to read 3, iclass 25, count 2 2006.173.18:06:45.38#ibcon#read 3, iclass 25, count 2 2006.173.18:06:45.38#ibcon#about to read 4, iclass 25, count 2 2006.173.18:06:45.38#ibcon#read 4, iclass 25, count 2 2006.173.18:06:45.38#ibcon#about to read 5, iclass 25, count 2 2006.173.18:06:45.38#ibcon#read 5, iclass 25, count 2 2006.173.18:06:45.38#ibcon#about to read 6, iclass 25, count 2 2006.173.18:06:45.38#ibcon#read 6, iclass 25, count 2 2006.173.18:06:45.38#ibcon#end of sib2, iclass 25, count 2 2006.173.18:06:45.38#ibcon#*after write, iclass 25, count 2 2006.173.18:06:45.38#ibcon#*before return 0, iclass 25, count 2 2006.173.18:06:45.38#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.18:06:45.38#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.18:06:45.38#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.18:06:45.38#ibcon#ireg 7 cls_cnt 0 2006.173.18:06:45.38#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.18:06:45.50#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.18:06:45.50#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.18:06:45.50#ibcon#enter wrdev, iclass 25, count 0 2006.173.18:06:45.50#ibcon#first serial, iclass 25, count 0 2006.173.18:06:45.50#ibcon#enter sib2, iclass 25, count 0 2006.173.18:06:45.50#ibcon#flushed, iclass 25, count 0 2006.173.18:06:45.50#ibcon#about to write, iclass 25, count 0 2006.173.18:06:45.50#ibcon#wrote, iclass 25, count 0 2006.173.18:06:45.50#ibcon#about to read 3, iclass 25, count 0 2006.173.18:06:45.52#ibcon#read 3, iclass 25, count 0 2006.173.18:06:45.52#ibcon#about to read 4, iclass 25, count 0 2006.173.18:06:45.52#ibcon#read 4, iclass 25, count 0 2006.173.18:06:45.52#ibcon#about to read 5, iclass 25, count 0 2006.173.18:06:45.52#ibcon#read 5, iclass 25, count 0 2006.173.18:06:45.52#ibcon#about to read 6, iclass 25, count 0 2006.173.18:06:45.52#ibcon#read 6, iclass 25, count 0 2006.173.18:06:45.52#ibcon#end of sib2, iclass 25, count 0 2006.173.18:06:45.52#ibcon#*mode == 0, iclass 25, count 0 2006.173.18:06:45.52#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.18:06:45.52#ibcon#[25=USB\r\n] 2006.173.18:06:45.52#ibcon#*before write, iclass 25, count 0 2006.173.18:06:45.52#ibcon#enter sib2, iclass 25, count 0 2006.173.18:06:45.52#ibcon#flushed, iclass 25, count 0 2006.173.18:06:45.52#ibcon#about to write, iclass 25, count 0 2006.173.18:06:45.52#ibcon#wrote, iclass 25, count 0 2006.173.18:06:45.52#ibcon#about to read 3, iclass 25, count 0 2006.173.18:06:45.55#ibcon#read 3, iclass 25, count 0 2006.173.18:06:45.55#ibcon#about to read 4, iclass 25, count 0 2006.173.18:06:45.55#ibcon#read 4, iclass 25, count 0 2006.173.18:06:45.55#ibcon#about to read 5, iclass 25, count 0 2006.173.18:06:45.55#ibcon#read 5, iclass 25, count 0 2006.173.18:06:45.55#ibcon#about to read 6, iclass 25, count 0 2006.173.18:06:45.55#ibcon#read 6, iclass 25, count 0 2006.173.18:06:45.55#ibcon#end of sib2, iclass 25, count 0 2006.173.18:06:45.55#ibcon#*after write, iclass 25, count 0 2006.173.18:06:45.55#ibcon#*before return 0, iclass 25, count 0 2006.173.18:06:45.55#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.18:06:45.55#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.18:06:45.55#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.18:06:45.55#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.18:06:45.55$vck44/valo=8,884.99 2006.173.18:06:45.55#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.18:06:45.55#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.18:06:45.55#ibcon#ireg 17 cls_cnt 0 2006.173.18:06:45.55#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.18:06:45.55#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.18:06:45.55#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.18:06:45.55#ibcon#enter wrdev, iclass 27, count 0 2006.173.18:06:45.55#ibcon#first serial, iclass 27, count 0 2006.173.18:06:45.55#ibcon#enter sib2, iclass 27, count 0 2006.173.18:06:45.55#ibcon#flushed, iclass 27, count 0 2006.173.18:06:45.55#ibcon#about to write, iclass 27, count 0 2006.173.18:06:45.55#ibcon#wrote, iclass 27, count 0 2006.173.18:06:45.55#ibcon#about to read 3, iclass 27, count 0 2006.173.18:06:45.57#ibcon#read 3, iclass 27, count 0 2006.173.18:06:45.57#ibcon#about to read 4, iclass 27, count 0 2006.173.18:06:45.57#ibcon#read 4, iclass 27, count 0 2006.173.18:06:45.57#ibcon#about to read 5, iclass 27, count 0 2006.173.18:06:45.57#ibcon#read 5, iclass 27, count 0 2006.173.18:06:45.57#ibcon#about to read 6, iclass 27, count 0 2006.173.18:06:45.57#ibcon#read 6, iclass 27, count 0 2006.173.18:06:45.57#ibcon#end of sib2, iclass 27, count 0 2006.173.18:06:45.57#ibcon#*mode == 0, iclass 27, count 0 2006.173.18:06:45.57#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.18:06:45.57#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.18:06:45.57#ibcon#*before write, iclass 27, count 0 2006.173.18:06:45.57#ibcon#enter sib2, iclass 27, count 0 2006.173.18:06:45.57#ibcon#flushed, iclass 27, count 0 2006.173.18:06:45.57#ibcon#about to write, iclass 27, count 0 2006.173.18:06:45.57#ibcon#wrote, iclass 27, count 0 2006.173.18:06:45.57#ibcon#about to read 3, iclass 27, count 0 2006.173.18:06:45.61#ibcon#read 3, iclass 27, count 0 2006.173.18:06:45.61#ibcon#about to read 4, iclass 27, count 0 2006.173.18:06:45.61#ibcon#read 4, iclass 27, count 0 2006.173.18:06:45.61#ibcon#about to read 5, iclass 27, count 0 2006.173.18:06:45.61#ibcon#read 5, iclass 27, count 0 2006.173.18:06:45.61#ibcon#about to read 6, iclass 27, count 0 2006.173.18:06:45.61#ibcon#read 6, iclass 27, count 0 2006.173.18:06:45.61#ibcon#end of sib2, iclass 27, count 0 2006.173.18:06:45.61#ibcon#*after write, iclass 27, count 0 2006.173.18:06:45.61#ibcon#*before return 0, iclass 27, count 0 2006.173.18:06:45.61#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.18:06:45.61#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.18:06:45.61#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.18:06:45.61#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.18:06:45.61$vck44/va=8,4 2006.173.18:06:45.61#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.18:06:45.61#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.18:06:45.61#ibcon#ireg 11 cls_cnt 2 2006.173.18:06:45.61#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.18:06:45.67#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.18:06:45.67#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.18:06:45.67#ibcon#enter wrdev, iclass 29, count 2 2006.173.18:06:45.67#ibcon#first serial, iclass 29, count 2 2006.173.18:06:45.67#ibcon#enter sib2, iclass 29, count 2 2006.173.18:06:45.67#ibcon#flushed, iclass 29, count 2 2006.173.18:06:45.67#ibcon#about to write, iclass 29, count 2 2006.173.18:06:45.67#ibcon#wrote, iclass 29, count 2 2006.173.18:06:45.67#ibcon#about to read 3, iclass 29, count 2 2006.173.18:06:45.69#ibcon#read 3, iclass 29, count 2 2006.173.18:06:45.69#ibcon#about to read 4, iclass 29, count 2 2006.173.18:06:45.69#ibcon#read 4, iclass 29, count 2 2006.173.18:06:45.69#ibcon#about to read 5, iclass 29, count 2 2006.173.18:06:45.69#ibcon#read 5, iclass 29, count 2 2006.173.18:06:45.69#ibcon#about to read 6, iclass 29, count 2 2006.173.18:06:45.69#ibcon#read 6, iclass 29, count 2 2006.173.18:06:45.69#ibcon#end of sib2, iclass 29, count 2 2006.173.18:06:45.69#ibcon#*mode == 0, iclass 29, count 2 2006.173.18:06:45.69#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.18:06:45.69#ibcon#[25=AT08-04\r\n] 2006.173.18:06:45.69#ibcon#*before write, iclass 29, count 2 2006.173.18:06:45.69#ibcon#enter sib2, iclass 29, count 2 2006.173.18:06:45.69#ibcon#flushed, iclass 29, count 2 2006.173.18:06:45.69#ibcon#about to write, iclass 29, count 2 2006.173.18:06:45.69#ibcon#wrote, iclass 29, count 2 2006.173.18:06:45.69#ibcon#about to read 3, iclass 29, count 2 2006.173.18:06:45.72#ibcon#read 3, iclass 29, count 2 2006.173.18:06:45.72#ibcon#about to read 4, iclass 29, count 2 2006.173.18:06:45.72#ibcon#read 4, iclass 29, count 2 2006.173.18:06:45.72#ibcon#about to read 5, iclass 29, count 2 2006.173.18:06:45.72#ibcon#read 5, iclass 29, count 2 2006.173.18:06:45.72#ibcon#about to read 6, iclass 29, count 2 2006.173.18:06:45.72#ibcon#read 6, iclass 29, count 2 2006.173.18:06:45.72#ibcon#end of sib2, iclass 29, count 2 2006.173.18:06:45.72#ibcon#*after write, iclass 29, count 2 2006.173.18:06:45.72#ibcon#*before return 0, iclass 29, count 2 2006.173.18:06:45.72#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.18:06:45.72#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.18:06:45.72#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.18:06:45.72#ibcon#ireg 7 cls_cnt 0 2006.173.18:06:45.72#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.18:06:45.84#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.18:06:45.84#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.18:06:45.84#ibcon#enter wrdev, iclass 29, count 0 2006.173.18:06:45.84#ibcon#first serial, iclass 29, count 0 2006.173.18:06:45.84#ibcon#enter sib2, iclass 29, count 0 2006.173.18:06:45.84#ibcon#flushed, iclass 29, count 0 2006.173.18:06:45.84#ibcon#about to write, iclass 29, count 0 2006.173.18:06:45.84#ibcon#wrote, iclass 29, count 0 2006.173.18:06:45.84#ibcon#about to read 3, iclass 29, count 0 2006.173.18:06:45.86#ibcon#read 3, iclass 29, count 0 2006.173.18:06:45.86#ibcon#about to read 4, iclass 29, count 0 2006.173.18:06:45.86#ibcon#read 4, iclass 29, count 0 2006.173.18:06:45.86#ibcon#about to read 5, iclass 29, count 0 2006.173.18:06:45.86#ibcon#read 5, iclass 29, count 0 2006.173.18:06:45.86#ibcon#about to read 6, iclass 29, count 0 2006.173.18:06:45.86#ibcon#read 6, iclass 29, count 0 2006.173.18:06:45.86#ibcon#end of sib2, iclass 29, count 0 2006.173.18:06:45.86#ibcon#*mode == 0, iclass 29, count 0 2006.173.18:06:45.86#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.18:06:45.86#ibcon#[25=USB\r\n] 2006.173.18:06:45.86#ibcon#*before write, iclass 29, count 0 2006.173.18:06:45.86#ibcon#enter sib2, iclass 29, count 0 2006.173.18:06:45.86#ibcon#flushed, iclass 29, count 0 2006.173.18:06:45.86#ibcon#about to write, iclass 29, count 0 2006.173.18:06:45.86#ibcon#wrote, iclass 29, count 0 2006.173.18:06:45.86#ibcon#about to read 3, iclass 29, count 0 2006.173.18:06:45.89#ibcon#read 3, iclass 29, count 0 2006.173.18:06:45.89#ibcon#about to read 4, iclass 29, count 0 2006.173.18:06:45.89#ibcon#read 4, iclass 29, count 0 2006.173.18:06:45.89#ibcon#about to read 5, iclass 29, count 0 2006.173.18:06:45.89#ibcon#read 5, iclass 29, count 0 2006.173.18:06:45.89#ibcon#about to read 6, iclass 29, count 0 2006.173.18:06:45.89#ibcon#read 6, iclass 29, count 0 2006.173.18:06:45.89#ibcon#end of sib2, iclass 29, count 0 2006.173.18:06:45.89#ibcon#*after write, iclass 29, count 0 2006.173.18:06:45.89#ibcon#*before return 0, iclass 29, count 0 2006.173.18:06:45.89#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.18:06:45.89#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.18:06:45.89#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.18:06:45.89#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.18:06:45.89$vck44/vblo=1,629.99 2006.173.18:06:45.89#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.18:06:45.89#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.18:06:45.89#ibcon#ireg 17 cls_cnt 0 2006.173.18:06:45.89#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.18:06:45.89#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.18:06:45.89#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.18:06:45.89#ibcon#enter wrdev, iclass 31, count 0 2006.173.18:06:45.89#ibcon#first serial, iclass 31, count 0 2006.173.18:06:45.89#ibcon#enter sib2, iclass 31, count 0 2006.173.18:06:45.89#ibcon#flushed, iclass 31, count 0 2006.173.18:06:45.89#ibcon#about to write, iclass 31, count 0 2006.173.18:06:45.89#ibcon#wrote, iclass 31, count 0 2006.173.18:06:45.89#ibcon#about to read 3, iclass 31, count 0 2006.173.18:06:45.91#ibcon#read 3, iclass 31, count 0 2006.173.18:06:45.91#ibcon#about to read 4, iclass 31, count 0 2006.173.18:06:45.91#ibcon#read 4, iclass 31, count 0 2006.173.18:06:45.91#ibcon#about to read 5, iclass 31, count 0 2006.173.18:06:45.91#ibcon#read 5, iclass 31, count 0 2006.173.18:06:45.91#ibcon#about to read 6, iclass 31, count 0 2006.173.18:06:45.91#ibcon#read 6, iclass 31, count 0 2006.173.18:06:45.91#ibcon#end of sib2, iclass 31, count 0 2006.173.18:06:45.91#ibcon#*mode == 0, iclass 31, count 0 2006.173.18:06:45.91#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.18:06:45.91#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.18:06:45.91#ibcon#*before write, iclass 31, count 0 2006.173.18:06:45.91#ibcon#enter sib2, iclass 31, count 0 2006.173.18:06:45.91#ibcon#flushed, iclass 31, count 0 2006.173.18:06:45.91#ibcon#about to write, iclass 31, count 0 2006.173.18:06:45.91#ibcon#wrote, iclass 31, count 0 2006.173.18:06:45.91#ibcon#about to read 3, iclass 31, count 0 2006.173.18:06:45.95#ibcon#read 3, iclass 31, count 0 2006.173.18:06:45.95#ibcon#about to read 4, iclass 31, count 0 2006.173.18:06:45.95#ibcon#read 4, iclass 31, count 0 2006.173.18:06:45.95#ibcon#about to read 5, iclass 31, count 0 2006.173.18:06:45.95#ibcon#read 5, iclass 31, count 0 2006.173.18:06:45.95#ibcon#about to read 6, iclass 31, count 0 2006.173.18:06:45.95#ibcon#read 6, iclass 31, count 0 2006.173.18:06:45.95#ibcon#end of sib2, iclass 31, count 0 2006.173.18:06:45.95#ibcon#*after write, iclass 31, count 0 2006.173.18:06:45.95#ibcon#*before return 0, iclass 31, count 0 2006.173.18:06:45.95#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.18:06:45.95#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.18:06:45.95#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.18:06:45.95#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.18:06:45.95$vck44/vb=1,4 2006.173.18:06:45.95#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.173.18:06:45.95#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.173.18:06:45.95#ibcon#ireg 11 cls_cnt 2 2006.173.18:06:45.95#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.18:06:45.95#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.18:06:45.95#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.18:06:45.95#ibcon#enter wrdev, iclass 33, count 2 2006.173.18:06:45.95#ibcon#first serial, iclass 33, count 2 2006.173.18:06:45.95#ibcon#enter sib2, iclass 33, count 2 2006.173.18:06:45.95#ibcon#flushed, iclass 33, count 2 2006.173.18:06:45.95#ibcon#about to write, iclass 33, count 2 2006.173.18:06:45.95#ibcon#wrote, iclass 33, count 2 2006.173.18:06:45.95#ibcon#about to read 3, iclass 33, count 2 2006.173.18:06:45.97#ibcon#read 3, iclass 33, count 2 2006.173.18:06:45.97#ibcon#about to read 4, iclass 33, count 2 2006.173.18:06:45.97#ibcon#read 4, iclass 33, count 2 2006.173.18:06:45.97#ibcon#about to read 5, iclass 33, count 2 2006.173.18:06:45.97#ibcon#read 5, iclass 33, count 2 2006.173.18:06:45.97#ibcon#about to read 6, iclass 33, count 2 2006.173.18:06:45.97#ibcon#read 6, iclass 33, count 2 2006.173.18:06:45.97#ibcon#end of sib2, iclass 33, count 2 2006.173.18:06:45.97#ibcon#*mode == 0, iclass 33, count 2 2006.173.18:06:45.97#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.173.18:06:45.97#ibcon#[27=AT01-04\r\n] 2006.173.18:06:45.97#ibcon#*before write, iclass 33, count 2 2006.173.18:06:45.97#ibcon#enter sib2, iclass 33, count 2 2006.173.18:06:45.97#ibcon#flushed, iclass 33, count 2 2006.173.18:06:45.97#ibcon#about to write, iclass 33, count 2 2006.173.18:06:45.97#ibcon#wrote, iclass 33, count 2 2006.173.18:06:45.97#ibcon#about to read 3, iclass 33, count 2 2006.173.18:06:46.00#ibcon#read 3, iclass 33, count 2 2006.173.18:06:46.00#ibcon#about to read 4, iclass 33, count 2 2006.173.18:06:46.00#ibcon#read 4, iclass 33, count 2 2006.173.18:06:46.00#ibcon#about to read 5, iclass 33, count 2 2006.173.18:06:46.00#ibcon#read 5, iclass 33, count 2 2006.173.18:06:46.00#ibcon#about to read 6, iclass 33, count 2 2006.173.18:06:46.00#ibcon#read 6, iclass 33, count 2 2006.173.18:06:46.00#ibcon#end of sib2, iclass 33, count 2 2006.173.18:06:46.00#ibcon#*after write, iclass 33, count 2 2006.173.18:06:46.00#ibcon#*before return 0, iclass 33, count 2 2006.173.18:06:46.00#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.18:06:46.00#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.173.18:06:46.00#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.173.18:06:46.00#ibcon#ireg 7 cls_cnt 0 2006.173.18:06:46.00#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.18:06:46.12#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.18:06:46.12#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.18:06:46.12#ibcon#enter wrdev, iclass 33, count 0 2006.173.18:06:46.12#ibcon#first serial, iclass 33, count 0 2006.173.18:06:46.12#ibcon#enter sib2, iclass 33, count 0 2006.173.18:06:46.12#ibcon#flushed, iclass 33, count 0 2006.173.18:06:46.12#ibcon#about to write, iclass 33, count 0 2006.173.18:06:46.12#ibcon#wrote, iclass 33, count 0 2006.173.18:06:46.12#ibcon#about to read 3, iclass 33, count 0 2006.173.18:06:46.14#ibcon#read 3, iclass 33, count 0 2006.173.18:06:46.14#ibcon#about to read 4, iclass 33, count 0 2006.173.18:06:46.14#ibcon#read 4, iclass 33, count 0 2006.173.18:06:46.14#ibcon#about to read 5, iclass 33, count 0 2006.173.18:06:46.14#ibcon#read 5, iclass 33, count 0 2006.173.18:06:46.14#ibcon#about to read 6, iclass 33, count 0 2006.173.18:06:46.14#ibcon#read 6, iclass 33, count 0 2006.173.18:06:46.14#ibcon#end of sib2, iclass 33, count 0 2006.173.18:06:46.14#ibcon#*mode == 0, iclass 33, count 0 2006.173.18:06:46.14#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.18:06:46.14#ibcon#[27=USB\r\n] 2006.173.18:06:46.14#ibcon#*before write, iclass 33, count 0 2006.173.18:06:46.14#ibcon#enter sib2, iclass 33, count 0 2006.173.18:06:46.14#ibcon#flushed, iclass 33, count 0 2006.173.18:06:46.14#ibcon#about to write, iclass 33, count 0 2006.173.18:06:46.14#ibcon#wrote, iclass 33, count 0 2006.173.18:06:46.14#ibcon#about to read 3, iclass 33, count 0 2006.173.18:06:46.17#ibcon#read 3, iclass 33, count 0 2006.173.18:06:46.17#ibcon#about to read 4, iclass 33, count 0 2006.173.18:06:46.17#ibcon#read 4, iclass 33, count 0 2006.173.18:06:46.17#ibcon#about to read 5, iclass 33, count 0 2006.173.18:06:46.17#ibcon#read 5, iclass 33, count 0 2006.173.18:06:46.17#ibcon#about to read 6, iclass 33, count 0 2006.173.18:06:46.17#ibcon#read 6, iclass 33, count 0 2006.173.18:06:46.17#ibcon#end of sib2, iclass 33, count 0 2006.173.18:06:46.17#ibcon#*after write, iclass 33, count 0 2006.173.18:06:46.17#ibcon#*before return 0, iclass 33, count 0 2006.173.18:06:46.17#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.18:06:46.17#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.173.18:06:46.17#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.18:06:46.17#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.18:06:46.17$vck44/vblo=2,634.99 2006.173.18:06:46.17#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.18:06:46.17#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.18:06:46.17#ibcon#ireg 17 cls_cnt 0 2006.173.18:06:46.17#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.18:06:46.17#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.18:06:46.17#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.18:06:46.17#ibcon#enter wrdev, iclass 35, count 0 2006.173.18:06:46.17#ibcon#first serial, iclass 35, count 0 2006.173.18:06:46.17#ibcon#enter sib2, iclass 35, count 0 2006.173.18:06:46.17#ibcon#flushed, iclass 35, count 0 2006.173.18:06:46.17#ibcon#about to write, iclass 35, count 0 2006.173.18:06:46.17#ibcon#wrote, iclass 35, count 0 2006.173.18:06:46.17#ibcon#about to read 3, iclass 35, count 0 2006.173.18:06:46.19#ibcon#read 3, iclass 35, count 0 2006.173.18:06:46.19#ibcon#about to read 4, iclass 35, count 0 2006.173.18:06:46.19#ibcon#read 4, iclass 35, count 0 2006.173.18:06:46.19#ibcon#about to read 5, iclass 35, count 0 2006.173.18:06:46.19#ibcon#read 5, iclass 35, count 0 2006.173.18:06:46.19#ibcon#about to read 6, iclass 35, count 0 2006.173.18:06:46.19#ibcon#read 6, iclass 35, count 0 2006.173.18:06:46.19#ibcon#end of sib2, iclass 35, count 0 2006.173.18:06:46.19#ibcon#*mode == 0, iclass 35, count 0 2006.173.18:06:46.19#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.18:06:46.19#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.18:06:46.19#ibcon#*before write, iclass 35, count 0 2006.173.18:06:46.19#ibcon#enter sib2, iclass 35, count 0 2006.173.18:06:46.19#ibcon#flushed, iclass 35, count 0 2006.173.18:06:46.19#ibcon#about to write, iclass 35, count 0 2006.173.18:06:46.19#ibcon#wrote, iclass 35, count 0 2006.173.18:06:46.19#ibcon#about to read 3, iclass 35, count 0 2006.173.18:06:46.23#ibcon#read 3, iclass 35, count 0 2006.173.18:06:46.23#ibcon#about to read 4, iclass 35, count 0 2006.173.18:06:46.23#ibcon#read 4, iclass 35, count 0 2006.173.18:06:46.23#ibcon#about to read 5, iclass 35, count 0 2006.173.18:06:46.23#ibcon#read 5, iclass 35, count 0 2006.173.18:06:46.23#ibcon#about to read 6, iclass 35, count 0 2006.173.18:06:46.23#ibcon#read 6, iclass 35, count 0 2006.173.18:06:46.23#ibcon#end of sib2, iclass 35, count 0 2006.173.18:06:46.23#ibcon#*after write, iclass 35, count 0 2006.173.18:06:46.23#ibcon#*before return 0, iclass 35, count 0 2006.173.18:06:46.23#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.18:06:46.23#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.18:06:46.23#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.18:06:46.23#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.18:06:46.23$vck44/vb=2,4 2006.173.18:06:46.23#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.173.18:06:46.23#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.173.18:06:46.23#ibcon#ireg 11 cls_cnt 2 2006.173.18:06:46.23#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.18:06:46.29#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.18:06:46.29#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.18:06:46.29#ibcon#enter wrdev, iclass 37, count 2 2006.173.18:06:46.29#ibcon#first serial, iclass 37, count 2 2006.173.18:06:46.29#ibcon#enter sib2, iclass 37, count 2 2006.173.18:06:46.29#ibcon#flushed, iclass 37, count 2 2006.173.18:06:46.29#ibcon#about to write, iclass 37, count 2 2006.173.18:06:46.29#ibcon#wrote, iclass 37, count 2 2006.173.18:06:46.29#ibcon#about to read 3, iclass 37, count 2 2006.173.18:06:46.31#ibcon#read 3, iclass 37, count 2 2006.173.18:06:46.31#ibcon#about to read 4, iclass 37, count 2 2006.173.18:06:46.31#ibcon#read 4, iclass 37, count 2 2006.173.18:06:46.31#ibcon#about to read 5, iclass 37, count 2 2006.173.18:06:46.31#ibcon#read 5, iclass 37, count 2 2006.173.18:06:46.31#ibcon#about to read 6, iclass 37, count 2 2006.173.18:06:46.31#ibcon#read 6, iclass 37, count 2 2006.173.18:06:46.31#ibcon#end of sib2, iclass 37, count 2 2006.173.18:06:46.31#ibcon#*mode == 0, iclass 37, count 2 2006.173.18:06:46.31#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.173.18:06:46.31#ibcon#[27=AT02-04\r\n] 2006.173.18:06:46.31#ibcon#*before write, iclass 37, count 2 2006.173.18:06:46.31#ibcon#enter sib2, iclass 37, count 2 2006.173.18:06:46.31#ibcon#flushed, iclass 37, count 2 2006.173.18:06:46.31#ibcon#about to write, iclass 37, count 2 2006.173.18:06:46.31#ibcon#wrote, iclass 37, count 2 2006.173.18:06:46.31#ibcon#about to read 3, iclass 37, count 2 2006.173.18:06:46.34#ibcon#read 3, iclass 37, count 2 2006.173.18:06:46.34#ibcon#about to read 4, iclass 37, count 2 2006.173.18:06:46.34#ibcon#read 4, iclass 37, count 2 2006.173.18:06:46.34#ibcon#about to read 5, iclass 37, count 2 2006.173.18:06:46.34#ibcon#read 5, iclass 37, count 2 2006.173.18:06:46.34#ibcon#about to read 6, iclass 37, count 2 2006.173.18:06:46.34#ibcon#read 6, iclass 37, count 2 2006.173.18:06:46.34#ibcon#end of sib2, iclass 37, count 2 2006.173.18:06:46.34#ibcon#*after write, iclass 37, count 2 2006.173.18:06:46.34#ibcon#*before return 0, iclass 37, count 2 2006.173.18:06:46.34#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.18:06:46.34#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.173.18:06:46.34#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.173.18:06:46.34#ibcon#ireg 7 cls_cnt 0 2006.173.18:06:46.34#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.18:06:46.46#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.18:06:46.46#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.18:06:46.46#ibcon#enter wrdev, iclass 37, count 0 2006.173.18:06:46.46#ibcon#first serial, iclass 37, count 0 2006.173.18:06:46.46#ibcon#enter sib2, iclass 37, count 0 2006.173.18:06:46.46#ibcon#flushed, iclass 37, count 0 2006.173.18:06:46.46#ibcon#about to write, iclass 37, count 0 2006.173.18:06:46.46#ibcon#wrote, iclass 37, count 0 2006.173.18:06:46.46#ibcon#about to read 3, iclass 37, count 0 2006.173.18:06:46.48#ibcon#read 3, iclass 37, count 0 2006.173.18:06:46.48#ibcon#about to read 4, iclass 37, count 0 2006.173.18:06:46.48#ibcon#read 4, iclass 37, count 0 2006.173.18:06:46.48#ibcon#about to read 5, iclass 37, count 0 2006.173.18:06:46.48#ibcon#read 5, iclass 37, count 0 2006.173.18:06:46.48#ibcon#about to read 6, iclass 37, count 0 2006.173.18:06:46.48#ibcon#read 6, iclass 37, count 0 2006.173.18:06:46.48#ibcon#end of sib2, iclass 37, count 0 2006.173.18:06:46.48#ibcon#*mode == 0, iclass 37, count 0 2006.173.18:06:46.48#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.18:06:46.48#ibcon#[27=USB\r\n] 2006.173.18:06:46.48#ibcon#*before write, iclass 37, count 0 2006.173.18:06:46.48#ibcon#enter sib2, iclass 37, count 0 2006.173.18:06:46.48#ibcon#flushed, iclass 37, count 0 2006.173.18:06:46.48#ibcon#about to write, iclass 37, count 0 2006.173.18:06:46.48#ibcon#wrote, iclass 37, count 0 2006.173.18:06:46.48#ibcon#about to read 3, iclass 37, count 0 2006.173.18:06:46.51#ibcon#read 3, iclass 37, count 0 2006.173.18:06:46.51#ibcon#about to read 4, iclass 37, count 0 2006.173.18:06:46.51#ibcon#read 4, iclass 37, count 0 2006.173.18:06:46.51#ibcon#about to read 5, iclass 37, count 0 2006.173.18:06:46.51#ibcon#read 5, iclass 37, count 0 2006.173.18:06:46.51#ibcon#about to read 6, iclass 37, count 0 2006.173.18:06:46.51#ibcon#read 6, iclass 37, count 0 2006.173.18:06:46.51#ibcon#end of sib2, iclass 37, count 0 2006.173.18:06:46.51#ibcon#*after write, iclass 37, count 0 2006.173.18:06:46.51#ibcon#*before return 0, iclass 37, count 0 2006.173.18:06:46.51#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.18:06:46.51#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.173.18:06:46.51#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.18:06:46.51#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.18:06:46.51$vck44/vblo=3,649.99 2006.173.18:06:46.51#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.18:06:46.51#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.18:06:46.51#ibcon#ireg 17 cls_cnt 0 2006.173.18:06:46.51#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.18:06:46.51#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.18:06:46.51#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.18:06:46.51#ibcon#enter wrdev, iclass 39, count 0 2006.173.18:06:46.51#ibcon#first serial, iclass 39, count 0 2006.173.18:06:46.51#ibcon#enter sib2, iclass 39, count 0 2006.173.18:06:46.51#ibcon#flushed, iclass 39, count 0 2006.173.18:06:46.51#ibcon#about to write, iclass 39, count 0 2006.173.18:06:46.51#ibcon#wrote, iclass 39, count 0 2006.173.18:06:46.51#ibcon#about to read 3, iclass 39, count 0 2006.173.18:06:46.53#ibcon#read 3, iclass 39, count 0 2006.173.18:06:46.53#ibcon#about to read 4, iclass 39, count 0 2006.173.18:06:46.53#ibcon#read 4, iclass 39, count 0 2006.173.18:06:46.53#ibcon#about to read 5, iclass 39, count 0 2006.173.18:06:46.53#ibcon#read 5, iclass 39, count 0 2006.173.18:06:46.53#ibcon#about to read 6, iclass 39, count 0 2006.173.18:06:46.53#ibcon#read 6, iclass 39, count 0 2006.173.18:06:46.53#ibcon#end of sib2, iclass 39, count 0 2006.173.18:06:46.53#ibcon#*mode == 0, iclass 39, count 0 2006.173.18:06:46.53#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.18:06:46.53#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.18:06:46.53#ibcon#*before write, iclass 39, count 0 2006.173.18:06:46.53#ibcon#enter sib2, iclass 39, count 0 2006.173.18:06:46.53#ibcon#flushed, iclass 39, count 0 2006.173.18:06:46.53#ibcon#about to write, iclass 39, count 0 2006.173.18:06:46.53#ibcon#wrote, iclass 39, count 0 2006.173.18:06:46.53#ibcon#about to read 3, iclass 39, count 0 2006.173.18:06:46.57#ibcon#read 3, iclass 39, count 0 2006.173.18:06:46.57#ibcon#about to read 4, iclass 39, count 0 2006.173.18:06:46.57#ibcon#read 4, iclass 39, count 0 2006.173.18:06:46.57#ibcon#about to read 5, iclass 39, count 0 2006.173.18:06:46.57#ibcon#read 5, iclass 39, count 0 2006.173.18:06:46.57#ibcon#about to read 6, iclass 39, count 0 2006.173.18:06:46.57#ibcon#read 6, iclass 39, count 0 2006.173.18:06:46.57#ibcon#end of sib2, iclass 39, count 0 2006.173.18:06:46.57#ibcon#*after write, iclass 39, count 0 2006.173.18:06:46.57#ibcon#*before return 0, iclass 39, count 0 2006.173.18:06:46.57#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.18:06:46.57#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.18:06:46.57#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.18:06:46.57#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.18:06:46.57$vck44/vb=3,4 2006.173.18:06:46.57#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.18:06:46.57#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.18:06:46.57#ibcon#ireg 11 cls_cnt 2 2006.173.18:06:46.57#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.18:06:46.63#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.18:06:46.63#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.18:06:46.63#ibcon#enter wrdev, iclass 3, count 2 2006.173.18:06:46.63#ibcon#first serial, iclass 3, count 2 2006.173.18:06:46.63#ibcon#enter sib2, iclass 3, count 2 2006.173.18:06:46.63#ibcon#flushed, iclass 3, count 2 2006.173.18:06:46.63#ibcon#about to write, iclass 3, count 2 2006.173.18:06:46.63#ibcon#wrote, iclass 3, count 2 2006.173.18:06:46.63#ibcon#about to read 3, iclass 3, count 2 2006.173.18:06:46.65#ibcon#read 3, iclass 3, count 2 2006.173.18:06:46.65#ibcon#about to read 4, iclass 3, count 2 2006.173.18:06:46.65#ibcon#read 4, iclass 3, count 2 2006.173.18:06:46.65#ibcon#about to read 5, iclass 3, count 2 2006.173.18:06:46.65#ibcon#read 5, iclass 3, count 2 2006.173.18:06:46.65#ibcon#about to read 6, iclass 3, count 2 2006.173.18:06:46.65#ibcon#read 6, iclass 3, count 2 2006.173.18:06:46.65#ibcon#end of sib2, iclass 3, count 2 2006.173.18:06:46.65#ibcon#*mode == 0, iclass 3, count 2 2006.173.18:06:46.65#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.18:06:46.65#ibcon#[27=AT03-04\r\n] 2006.173.18:06:46.65#ibcon#*before write, iclass 3, count 2 2006.173.18:06:46.65#ibcon#enter sib2, iclass 3, count 2 2006.173.18:06:46.65#ibcon#flushed, iclass 3, count 2 2006.173.18:06:46.65#ibcon#about to write, iclass 3, count 2 2006.173.18:06:46.65#ibcon#wrote, iclass 3, count 2 2006.173.18:06:46.65#ibcon#about to read 3, iclass 3, count 2 2006.173.18:06:46.68#ibcon#read 3, iclass 3, count 2 2006.173.18:06:46.68#ibcon#about to read 4, iclass 3, count 2 2006.173.18:06:46.68#ibcon#read 4, iclass 3, count 2 2006.173.18:06:46.68#ibcon#about to read 5, iclass 3, count 2 2006.173.18:06:46.68#ibcon#read 5, iclass 3, count 2 2006.173.18:06:46.68#ibcon#about to read 6, iclass 3, count 2 2006.173.18:06:46.68#ibcon#read 6, iclass 3, count 2 2006.173.18:06:46.68#ibcon#end of sib2, iclass 3, count 2 2006.173.18:06:46.68#ibcon#*after write, iclass 3, count 2 2006.173.18:06:46.68#ibcon#*before return 0, iclass 3, count 2 2006.173.18:06:46.68#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.18:06:46.68#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.18:06:46.68#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.18:06:46.68#ibcon#ireg 7 cls_cnt 0 2006.173.18:06:46.68#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.18:06:46.80#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.18:06:46.80#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.18:06:46.80#ibcon#enter wrdev, iclass 3, count 0 2006.173.18:06:46.80#ibcon#first serial, iclass 3, count 0 2006.173.18:06:46.80#ibcon#enter sib2, iclass 3, count 0 2006.173.18:06:46.80#ibcon#flushed, iclass 3, count 0 2006.173.18:06:46.80#ibcon#about to write, iclass 3, count 0 2006.173.18:06:46.80#ibcon#wrote, iclass 3, count 0 2006.173.18:06:46.80#ibcon#about to read 3, iclass 3, count 0 2006.173.18:06:46.82#ibcon#read 3, iclass 3, count 0 2006.173.18:06:46.82#ibcon#about to read 4, iclass 3, count 0 2006.173.18:06:46.82#ibcon#read 4, iclass 3, count 0 2006.173.18:06:46.82#ibcon#about to read 5, iclass 3, count 0 2006.173.18:06:46.82#ibcon#read 5, iclass 3, count 0 2006.173.18:06:46.82#ibcon#about to read 6, iclass 3, count 0 2006.173.18:06:46.82#ibcon#read 6, iclass 3, count 0 2006.173.18:06:46.82#ibcon#end of sib2, iclass 3, count 0 2006.173.18:06:46.82#ibcon#*mode == 0, iclass 3, count 0 2006.173.18:06:46.82#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.18:06:46.82#ibcon#[27=USB\r\n] 2006.173.18:06:46.82#ibcon#*before write, iclass 3, count 0 2006.173.18:06:46.82#ibcon#enter sib2, iclass 3, count 0 2006.173.18:06:46.82#ibcon#flushed, iclass 3, count 0 2006.173.18:06:46.82#ibcon#about to write, iclass 3, count 0 2006.173.18:06:46.82#ibcon#wrote, iclass 3, count 0 2006.173.18:06:46.82#ibcon#about to read 3, iclass 3, count 0 2006.173.18:06:46.85#ibcon#read 3, iclass 3, count 0 2006.173.18:06:46.85#ibcon#about to read 4, iclass 3, count 0 2006.173.18:06:46.85#ibcon#read 4, iclass 3, count 0 2006.173.18:06:46.85#ibcon#about to read 5, iclass 3, count 0 2006.173.18:06:46.85#ibcon#read 5, iclass 3, count 0 2006.173.18:06:46.85#ibcon#about to read 6, iclass 3, count 0 2006.173.18:06:46.85#ibcon#read 6, iclass 3, count 0 2006.173.18:06:46.85#ibcon#end of sib2, iclass 3, count 0 2006.173.18:06:46.85#ibcon#*after write, iclass 3, count 0 2006.173.18:06:46.85#ibcon#*before return 0, iclass 3, count 0 2006.173.18:06:46.85#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.18:06:46.85#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.18:06:46.85#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.18:06:46.85#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.18:06:46.85$vck44/vblo=4,679.99 2006.173.18:06:46.85#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.18:06:46.85#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.18:06:46.85#ibcon#ireg 17 cls_cnt 0 2006.173.18:06:46.85#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.18:06:46.85#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.18:06:46.85#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.18:06:46.85#ibcon#enter wrdev, iclass 5, count 0 2006.173.18:06:46.85#ibcon#first serial, iclass 5, count 0 2006.173.18:06:46.85#ibcon#enter sib2, iclass 5, count 0 2006.173.18:06:46.85#ibcon#flushed, iclass 5, count 0 2006.173.18:06:46.85#ibcon#about to write, iclass 5, count 0 2006.173.18:06:46.85#ibcon#wrote, iclass 5, count 0 2006.173.18:06:46.85#ibcon#about to read 3, iclass 5, count 0 2006.173.18:06:46.87#ibcon#read 3, iclass 5, count 0 2006.173.18:06:46.87#ibcon#about to read 4, iclass 5, count 0 2006.173.18:06:46.87#ibcon#read 4, iclass 5, count 0 2006.173.18:06:46.87#ibcon#about to read 5, iclass 5, count 0 2006.173.18:06:46.87#ibcon#read 5, iclass 5, count 0 2006.173.18:06:46.87#ibcon#about to read 6, iclass 5, count 0 2006.173.18:06:46.87#ibcon#read 6, iclass 5, count 0 2006.173.18:06:46.87#ibcon#end of sib2, iclass 5, count 0 2006.173.18:06:46.87#ibcon#*mode == 0, iclass 5, count 0 2006.173.18:06:46.87#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.18:06:46.87#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.18:06:46.87#ibcon#*before write, iclass 5, count 0 2006.173.18:06:46.87#ibcon#enter sib2, iclass 5, count 0 2006.173.18:06:46.87#ibcon#flushed, iclass 5, count 0 2006.173.18:06:46.87#ibcon#about to write, iclass 5, count 0 2006.173.18:06:46.87#ibcon#wrote, iclass 5, count 0 2006.173.18:06:46.87#ibcon#about to read 3, iclass 5, count 0 2006.173.18:06:46.91#ibcon#read 3, iclass 5, count 0 2006.173.18:06:46.91#ibcon#about to read 4, iclass 5, count 0 2006.173.18:06:46.91#ibcon#read 4, iclass 5, count 0 2006.173.18:06:46.91#ibcon#about to read 5, iclass 5, count 0 2006.173.18:06:46.91#ibcon#read 5, iclass 5, count 0 2006.173.18:06:46.91#ibcon#about to read 6, iclass 5, count 0 2006.173.18:06:46.91#ibcon#read 6, iclass 5, count 0 2006.173.18:06:46.91#ibcon#end of sib2, iclass 5, count 0 2006.173.18:06:46.91#ibcon#*after write, iclass 5, count 0 2006.173.18:06:46.91#ibcon#*before return 0, iclass 5, count 0 2006.173.18:06:46.91#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.18:06:46.91#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.18:06:46.91#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.18:06:46.91#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.18:06:46.91$vck44/vb=4,4 2006.173.18:06:46.91#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.173.18:06:46.91#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.173.18:06:46.91#ibcon#ireg 11 cls_cnt 2 2006.173.18:06:46.91#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.18:06:46.97#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.18:06:46.97#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.18:06:46.97#ibcon#enter wrdev, iclass 7, count 2 2006.173.18:06:46.97#ibcon#first serial, iclass 7, count 2 2006.173.18:06:46.97#ibcon#enter sib2, iclass 7, count 2 2006.173.18:06:46.97#ibcon#flushed, iclass 7, count 2 2006.173.18:06:46.97#ibcon#about to write, iclass 7, count 2 2006.173.18:06:46.97#ibcon#wrote, iclass 7, count 2 2006.173.18:06:46.97#ibcon#about to read 3, iclass 7, count 2 2006.173.18:06:46.99#ibcon#read 3, iclass 7, count 2 2006.173.18:06:46.99#ibcon#about to read 4, iclass 7, count 2 2006.173.18:06:46.99#ibcon#read 4, iclass 7, count 2 2006.173.18:06:46.99#ibcon#about to read 5, iclass 7, count 2 2006.173.18:06:46.99#ibcon#read 5, iclass 7, count 2 2006.173.18:06:46.99#ibcon#about to read 6, iclass 7, count 2 2006.173.18:06:46.99#ibcon#read 6, iclass 7, count 2 2006.173.18:06:46.99#ibcon#end of sib2, iclass 7, count 2 2006.173.18:06:46.99#ibcon#*mode == 0, iclass 7, count 2 2006.173.18:06:46.99#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.173.18:06:46.99#ibcon#[27=AT04-04\r\n] 2006.173.18:06:46.99#ibcon#*before write, iclass 7, count 2 2006.173.18:06:46.99#ibcon#enter sib2, iclass 7, count 2 2006.173.18:06:46.99#ibcon#flushed, iclass 7, count 2 2006.173.18:06:46.99#ibcon#about to write, iclass 7, count 2 2006.173.18:06:46.99#ibcon#wrote, iclass 7, count 2 2006.173.18:06:46.99#ibcon#about to read 3, iclass 7, count 2 2006.173.18:06:47.02#ibcon#read 3, iclass 7, count 2 2006.173.18:06:47.02#ibcon#about to read 4, iclass 7, count 2 2006.173.18:06:47.02#ibcon#read 4, iclass 7, count 2 2006.173.18:06:47.02#ibcon#about to read 5, iclass 7, count 2 2006.173.18:06:47.02#ibcon#read 5, iclass 7, count 2 2006.173.18:06:47.02#ibcon#about to read 6, iclass 7, count 2 2006.173.18:06:47.02#ibcon#read 6, iclass 7, count 2 2006.173.18:06:47.02#ibcon#end of sib2, iclass 7, count 2 2006.173.18:06:47.02#ibcon#*after write, iclass 7, count 2 2006.173.18:06:47.02#ibcon#*before return 0, iclass 7, count 2 2006.173.18:06:47.02#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.18:06:47.02#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.173.18:06:47.02#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.173.18:06:47.02#ibcon#ireg 7 cls_cnt 0 2006.173.18:06:47.02#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.18:06:47.14#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.18:06:47.14#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.18:06:47.14#ibcon#enter wrdev, iclass 7, count 0 2006.173.18:06:47.14#ibcon#first serial, iclass 7, count 0 2006.173.18:06:47.14#ibcon#enter sib2, iclass 7, count 0 2006.173.18:06:47.14#ibcon#flushed, iclass 7, count 0 2006.173.18:06:47.14#ibcon#about to write, iclass 7, count 0 2006.173.18:06:47.14#ibcon#wrote, iclass 7, count 0 2006.173.18:06:47.14#ibcon#about to read 3, iclass 7, count 0 2006.173.18:06:47.16#ibcon#read 3, iclass 7, count 0 2006.173.18:06:47.16#ibcon#about to read 4, iclass 7, count 0 2006.173.18:06:47.16#ibcon#read 4, iclass 7, count 0 2006.173.18:06:47.16#ibcon#about to read 5, iclass 7, count 0 2006.173.18:06:47.16#ibcon#read 5, iclass 7, count 0 2006.173.18:06:47.16#ibcon#about to read 6, iclass 7, count 0 2006.173.18:06:47.16#ibcon#read 6, iclass 7, count 0 2006.173.18:06:47.16#ibcon#end of sib2, iclass 7, count 0 2006.173.18:06:47.16#ibcon#*mode == 0, iclass 7, count 0 2006.173.18:06:47.16#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.18:06:47.16#ibcon#[27=USB\r\n] 2006.173.18:06:47.16#ibcon#*before write, iclass 7, count 0 2006.173.18:06:47.16#ibcon#enter sib2, iclass 7, count 0 2006.173.18:06:47.16#ibcon#flushed, iclass 7, count 0 2006.173.18:06:47.16#ibcon#about to write, iclass 7, count 0 2006.173.18:06:47.16#ibcon#wrote, iclass 7, count 0 2006.173.18:06:47.16#ibcon#about to read 3, iclass 7, count 0 2006.173.18:06:47.19#ibcon#read 3, iclass 7, count 0 2006.173.18:06:47.19#ibcon#about to read 4, iclass 7, count 0 2006.173.18:06:47.19#ibcon#read 4, iclass 7, count 0 2006.173.18:06:47.19#ibcon#about to read 5, iclass 7, count 0 2006.173.18:06:47.19#ibcon#read 5, iclass 7, count 0 2006.173.18:06:47.19#ibcon#about to read 6, iclass 7, count 0 2006.173.18:06:47.19#ibcon#read 6, iclass 7, count 0 2006.173.18:06:47.19#ibcon#end of sib2, iclass 7, count 0 2006.173.18:06:47.19#ibcon#*after write, iclass 7, count 0 2006.173.18:06:47.19#ibcon#*before return 0, iclass 7, count 0 2006.173.18:06:47.19#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.18:06:47.19#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.173.18:06:47.19#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.18:06:47.19#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.18:06:47.19$vck44/vblo=5,709.99 2006.173.18:06:47.19#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.18:06:47.19#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.18:06:47.19#ibcon#ireg 17 cls_cnt 0 2006.173.18:06:47.19#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.18:06:47.19#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.18:06:47.19#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.18:06:47.19#ibcon#enter wrdev, iclass 11, count 0 2006.173.18:06:47.19#ibcon#first serial, iclass 11, count 0 2006.173.18:06:47.19#ibcon#enter sib2, iclass 11, count 0 2006.173.18:06:47.19#ibcon#flushed, iclass 11, count 0 2006.173.18:06:47.19#ibcon#about to write, iclass 11, count 0 2006.173.18:06:47.19#ibcon#wrote, iclass 11, count 0 2006.173.18:06:47.19#ibcon#about to read 3, iclass 11, count 0 2006.173.18:06:47.21#ibcon#read 3, iclass 11, count 0 2006.173.18:06:47.21#ibcon#about to read 4, iclass 11, count 0 2006.173.18:06:47.21#ibcon#read 4, iclass 11, count 0 2006.173.18:06:47.21#ibcon#about to read 5, iclass 11, count 0 2006.173.18:06:47.21#ibcon#read 5, iclass 11, count 0 2006.173.18:06:47.21#ibcon#about to read 6, iclass 11, count 0 2006.173.18:06:47.21#ibcon#read 6, iclass 11, count 0 2006.173.18:06:47.21#ibcon#end of sib2, iclass 11, count 0 2006.173.18:06:47.21#ibcon#*mode == 0, iclass 11, count 0 2006.173.18:06:47.21#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.18:06:47.21#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.18:06:47.21#ibcon#*before write, iclass 11, count 0 2006.173.18:06:47.21#ibcon#enter sib2, iclass 11, count 0 2006.173.18:06:47.21#ibcon#flushed, iclass 11, count 0 2006.173.18:06:47.21#ibcon#about to write, iclass 11, count 0 2006.173.18:06:47.21#ibcon#wrote, iclass 11, count 0 2006.173.18:06:47.21#ibcon#about to read 3, iclass 11, count 0 2006.173.18:06:47.25#ibcon#read 3, iclass 11, count 0 2006.173.18:06:47.25#ibcon#about to read 4, iclass 11, count 0 2006.173.18:06:47.25#ibcon#read 4, iclass 11, count 0 2006.173.18:06:47.25#ibcon#about to read 5, iclass 11, count 0 2006.173.18:06:47.25#ibcon#read 5, iclass 11, count 0 2006.173.18:06:47.25#ibcon#about to read 6, iclass 11, count 0 2006.173.18:06:47.25#ibcon#read 6, iclass 11, count 0 2006.173.18:06:47.25#ibcon#end of sib2, iclass 11, count 0 2006.173.18:06:47.25#ibcon#*after write, iclass 11, count 0 2006.173.18:06:47.25#ibcon#*before return 0, iclass 11, count 0 2006.173.18:06:47.25#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.18:06:47.25#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.18:06:47.25#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.18:06:47.25#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.18:06:47.25$vck44/vb=5,4 2006.173.18:06:47.25#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.173.18:06:47.25#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.173.18:06:47.25#ibcon#ireg 11 cls_cnt 2 2006.173.18:06:47.25#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.18:06:47.31#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.18:06:47.31#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.18:06:47.31#ibcon#enter wrdev, iclass 13, count 2 2006.173.18:06:47.31#ibcon#first serial, iclass 13, count 2 2006.173.18:06:47.31#ibcon#enter sib2, iclass 13, count 2 2006.173.18:06:47.31#ibcon#flushed, iclass 13, count 2 2006.173.18:06:47.31#ibcon#about to write, iclass 13, count 2 2006.173.18:06:47.31#ibcon#wrote, iclass 13, count 2 2006.173.18:06:47.31#ibcon#about to read 3, iclass 13, count 2 2006.173.18:06:47.33#ibcon#read 3, iclass 13, count 2 2006.173.18:06:47.33#ibcon#about to read 4, iclass 13, count 2 2006.173.18:06:47.33#ibcon#read 4, iclass 13, count 2 2006.173.18:06:47.33#ibcon#about to read 5, iclass 13, count 2 2006.173.18:06:47.33#ibcon#read 5, iclass 13, count 2 2006.173.18:06:47.33#ibcon#about to read 6, iclass 13, count 2 2006.173.18:06:47.33#ibcon#read 6, iclass 13, count 2 2006.173.18:06:47.33#ibcon#end of sib2, iclass 13, count 2 2006.173.18:06:47.33#ibcon#*mode == 0, iclass 13, count 2 2006.173.18:06:47.33#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.173.18:06:47.33#ibcon#[27=AT05-04\r\n] 2006.173.18:06:47.33#ibcon#*before write, iclass 13, count 2 2006.173.18:06:47.33#ibcon#enter sib2, iclass 13, count 2 2006.173.18:06:47.33#ibcon#flushed, iclass 13, count 2 2006.173.18:06:47.33#ibcon#about to write, iclass 13, count 2 2006.173.18:06:47.33#ibcon#wrote, iclass 13, count 2 2006.173.18:06:47.33#ibcon#about to read 3, iclass 13, count 2 2006.173.18:06:47.36#ibcon#read 3, iclass 13, count 2 2006.173.18:06:47.36#ibcon#about to read 4, iclass 13, count 2 2006.173.18:06:47.36#ibcon#read 4, iclass 13, count 2 2006.173.18:06:47.36#ibcon#about to read 5, iclass 13, count 2 2006.173.18:06:47.36#ibcon#read 5, iclass 13, count 2 2006.173.18:06:47.36#ibcon#about to read 6, iclass 13, count 2 2006.173.18:06:47.36#ibcon#read 6, iclass 13, count 2 2006.173.18:06:47.36#ibcon#end of sib2, iclass 13, count 2 2006.173.18:06:47.36#ibcon#*after write, iclass 13, count 2 2006.173.18:06:47.36#ibcon#*before return 0, iclass 13, count 2 2006.173.18:06:47.36#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.18:06:47.36#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.173.18:06:47.36#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.173.18:06:47.36#ibcon#ireg 7 cls_cnt 0 2006.173.18:06:47.36#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.18:06:47.48#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.18:06:47.48#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.18:06:47.48#ibcon#enter wrdev, iclass 13, count 0 2006.173.18:06:47.48#ibcon#first serial, iclass 13, count 0 2006.173.18:06:47.48#ibcon#enter sib2, iclass 13, count 0 2006.173.18:06:47.48#ibcon#flushed, iclass 13, count 0 2006.173.18:06:47.48#ibcon#about to write, iclass 13, count 0 2006.173.18:06:47.48#ibcon#wrote, iclass 13, count 0 2006.173.18:06:47.48#ibcon#about to read 3, iclass 13, count 0 2006.173.18:06:47.50#ibcon#read 3, iclass 13, count 0 2006.173.18:06:47.50#ibcon#about to read 4, iclass 13, count 0 2006.173.18:06:47.50#ibcon#read 4, iclass 13, count 0 2006.173.18:06:47.50#ibcon#about to read 5, iclass 13, count 0 2006.173.18:06:47.50#ibcon#read 5, iclass 13, count 0 2006.173.18:06:47.50#ibcon#about to read 6, iclass 13, count 0 2006.173.18:06:47.50#ibcon#read 6, iclass 13, count 0 2006.173.18:06:47.50#ibcon#end of sib2, iclass 13, count 0 2006.173.18:06:47.50#ibcon#*mode == 0, iclass 13, count 0 2006.173.18:06:47.50#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.18:06:47.50#ibcon#[27=USB\r\n] 2006.173.18:06:47.50#ibcon#*before write, iclass 13, count 0 2006.173.18:06:47.50#ibcon#enter sib2, iclass 13, count 0 2006.173.18:06:47.50#ibcon#flushed, iclass 13, count 0 2006.173.18:06:47.50#ibcon#about to write, iclass 13, count 0 2006.173.18:06:47.50#ibcon#wrote, iclass 13, count 0 2006.173.18:06:47.50#ibcon#about to read 3, iclass 13, count 0 2006.173.18:06:47.53#ibcon#read 3, iclass 13, count 0 2006.173.18:06:47.53#ibcon#about to read 4, iclass 13, count 0 2006.173.18:06:47.53#ibcon#read 4, iclass 13, count 0 2006.173.18:06:47.53#ibcon#about to read 5, iclass 13, count 0 2006.173.18:06:47.53#ibcon#read 5, iclass 13, count 0 2006.173.18:06:47.53#ibcon#about to read 6, iclass 13, count 0 2006.173.18:06:47.53#ibcon#read 6, iclass 13, count 0 2006.173.18:06:47.53#ibcon#end of sib2, iclass 13, count 0 2006.173.18:06:47.53#ibcon#*after write, iclass 13, count 0 2006.173.18:06:47.53#ibcon#*before return 0, iclass 13, count 0 2006.173.18:06:47.53#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.18:06:47.53#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.173.18:06:47.53#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.18:06:47.53#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.18:06:47.53$vck44/vblo=6,719.99 2006.173.18:06:47.53#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.18:06:47.53#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.18:06:47.53#ibcon#ireg 17 cls_cnt 0 2006.173.18:06:47.53#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.18:06:47.53#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.18:06:47.53#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.18:06:47.53#ibcon#enter wrdev, iclass 15, count 0 2006.173.18:06:47.53#ibcon#first serial, iclass 15, count 0 2006.173.18:06:47.53#ibcon#enter sib2, iclass 15, count 0 2006.173.18:06:47.53#ibcon#flushed, iclass 15, count 0 2006.173.18:06:47.53#ibcon#about to write, iclass 15, count 0 2006.173.18:06:47.53#ibcon#wrote, iclass 15, count 0 2006.173.18:06:47.53#ibcon#about to read 3, iclass 15, count 0 2006.173.18:06:47.55#ibcon#read 3, iclass 15, count 0 2006.173.18:06:47.55#ibcon#about to read 4, iclass 15, count 0 2006.173.18:06:47.55#ibcon#read 4, iclass 15, count 0 2006.173.18:06:47.55#ibcon#about to read 5, iclass 15, count 0 2006.173.18:06:47.55#ibcon#read 5, iclass 15, count 0 2006.173.18:06:47.55#ibcon#about to read 6, iclass 15, count 0 2006.173.18:06:47.55#ibcon#read 6, iclass 15, count 0 2006.173.18:06:47.55#ibcon#end of sib2, iclass 15, count 0 2006.173.18:06:47.55#ibcon#*mode == 0, iclass 15, count 0 2006.173.18:06:47.55#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.18:06:47.55#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.18:06:47.55#ibcon#*before write, iclass 15, count 0 2006.173.18:06:47.55#ibcon#enter sib2, iclass 15, count 0 2006.173.18:06:47.55#ibcon#flushed, iclass 15, count 0 2006.173.18:06:47.55#ibcon#about to write, iclass 15, count 0 2006.173.18:06:47.55#ibcon#wrote, iclass 15, count 0 2006.173.18:06:47.55#ibcon#about to read 3, iclass 15, count 0 2006.173.18:06:47.59#ibcon#read 3, iclass 15, count 0 2006.173.18:06:47.59#ibcon#about to read 4, iclass 15, count 0 2006.173.18:06:47.59#ibcon#read 4, iclass 15, count 0 2006.173.18:06:47.59#ibcon#about to read 5, iclass 15, count 0 2006.173.18:06:47.59#ibcon#read 5, iclass 15, count 0 2006.173.18:06:47.59#ibcon#about to read 6, iclass 15, count 0 2006.173.18:06:47.59#ibcon#read 6, iclass 15, count 0 2006.173.18:06:47.59#ibcon#end of sib2, iclass 15, count 0 2006.173.18:06:47.59#ibcon#*after write, iclass 15, count 0 2006.173.18:06:47.59#ibcon#*before return 0, iclass 15, count 0 2006.173.18:06:47.59#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.18:06:47.59#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.18:06:47.59#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.18:06:47.59#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.18:06:47.59$vck44/vb=6,4 2006.173.18:06:47.59#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.18:06:47.59#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.18:06:47.59#ibcon#ireg 11 cls_cnt 2 2006.173.18:06:47.59#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.18:06:47.65#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.18:06:47.65#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.18:06:47.65#ibcon#enter wrdev, iclass 17, count 2 2006.173.18:06:47.65#ibcon#first serial, iclass 17, count 2 2006.173.18:06:47.65#ibcon#enter sib2, iclass 17, count 2 2006.173.18:06:47.65#ibcon#flushed, iclass 17, count 2 2006.173.18:06:47.65#ibcon#about to write, iclass 17, count 2 2006.173.18:06:47.65#ibcon#wrote, iclass 17, count 2 2006.173.18:06:47.65#ibcon#about to read 3, iclass 17, count 2 2006.173.18:06:47.67#ibcon#read 3, iclass 17, count 2 2006.173.18:06:47.67#ibcon#about to read 4, iclass 17, count 2 2006.173.18:06:47.67#ibcon#read 4, iclass 17, count 2 2006.173.18:06:47.67#ibcon#about to read 5, iclass 17, count 2 2006.173.18:06:47.67#ibcon#read 5, iclass 17, count 2 2006.173.18:06:47.67#ibcon#about to read 6, iclass 17, count 2 2006.173.18:06:47.67#ibcon#read 6, iclass 17, count 2 2006.173.18:06:47.67#ibcon#end of sib2, iclass 17, count 2 2006.173.18:06:47.67#ibcon#*mode == 0, iclass 17, count 2 2006.173.18:06:47.67#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.18:06:47.67#ibcon#[27=AT06-04\r\n] 2006.173.18:06:47.67#ibcon#*before write, iclass 17, count 2 2006.173.18:06:47.67#ibcon#enter sib2, iclass 17, count 2 2006.173.18:06:47.67#ibcon#flushed, iclass 17, count 2 2006.173.18:06:47.67#ibcon#about to write, iclass 17, count 2 2006.173.18:06:47.67#ibcon#wrote, iclass 17, count 2 2006.173.18:06:47.67#ibcon#about to read 3, iclass 17, count 2 2006.173.18:06:47.70#ibcon#read 3, iclass 17, count 2 2006.173.18:06:47.70#ibcon#about to read 4, iclass 17, count 2 2006.173.18:06:47.70#ibcon#read 4, iclass 17, count 2 2006.173.18:06:47.70#ibcon#about to read 5, iclass 17, count 2 2006.173.18:06:47.70#ibcon#read 5, iclass 17, count 2 2006.173.18:06:47.70#ibcon#about to read 6, iclass 17, count 2 2006.173.18:06:47.70#ibcon#read 6, iclass 17, count 2 2006.173.18:06:47.70#ibcon#end of sib2, iclass 17, count 2 2006.173.18:06:47.70#ibcon#*after write, iclass 17, count 2 2006.173.18:06:47.70#ibcon#*before return 0, iclass 17, count 2 2006.173.18:06:47.70#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.18:06:47.70#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.18:06:47.70#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.18:06:47.70#ibcon#ireg 7 cls_cnt 0 2006.173.18:06:47.70#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.18:06:47.73#abcon#<5=/14 1.1 2.2 20.021001002.2\r\n> 2006.173.18:06:47.75#abcon#{5=INTERFACE CLEAR} 2006.173.18:06:47.81#abcon#[5=S1D000X0/0*\r\n] 2006.173.18:06:47.82#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.18:06:47.82#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.18:06:47.82#ibcon#enter wrdev, iclass 17, count 0 2006.173.18:06:47.82#ibcon#first serial, iclass 17, count 0 2006.173.18:06:47.82#ibcon#enter sib2, iclass 17, count 0 2006.173.18:06:47.82#ibcon#flushed, iclass 17, count 0 2006.173.18:06:47.82#ibcon#about to write, iclass 17, count 0 2006.173.18:06:47.82#ibcon#wrote, iclass 17, count 0 2006.173.18:06:47.82#ibcon#about to read 3, iclass 17, count 0 2006.173.18:06:47.84#ibcon#read 3, iclass 17, count 0 2006.173.18:06:47.84#ibcon#about to read 4, iclass 17, count 0 2006.173.18:06:47.84#ibcon#read 4, iclass 17, count 0 2006.173.18:06:47.84#ibcon#about to read 5, iclass 17, count 0 2006.173.18:06:47.84#ibcon#read 5, iclass 17, count 0 2006.173.18:06:47.84#ibcon#about to read 6, iclass 17, count 0 2006.173.18:06:47.84#ibcon#read 6, iclass 17, count 0 2006.173.18:06:47.84#ibcon#end of sib2, iclass 17, count 0 2006.173.18:06:47.84#ibcon#*mode == 0, iclass 17, count 0 2006.173.18:06:47.84#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.18:06:47.84#ibcon#[27=USB\r\n] 2006.173.18:06:47.84#ibcon#*before write, iclass 17, count 0 2006.173.18:06:47.84#ibcon#enter sib2, iclass 17, count 0 2006.173.18:06:47.84#ibcon#flushed, iclass 17, count 0 2006.173.18:06:47.84#ibcon#about to write, iclass 17, count 0 2006.173.18:06:47.84#ibcon#wrote, iclass 17, count 0 2006.173.18:06:47.84#ibcon#about to read 3, iclass 17, count 0 2006.173.18:06:47.87#ibcon#read 3, iclass 17, count 0 2006.173.18:06:47.87#ibcon#about to read 4, iclass 17, count 0 2006.173.18:06:47.87#ibcon#read 4, iclass 17, count 0 2006.173.18:06:47.87#ibcon#about to read 5, iclass 17, count 0 2006.173.18:06:47.87#ibcon#read 5, iclass 17, count 0 2006.173.18:06:47.87#ibcon#about to read 6, iclass 17, count 0 2006.173.18:06:47.87#ibcon#read 6, iclass 17, count 0 2006.173.18:06:47.87#ibcon#end of sib2, iclass 17, count 0 2006.173.18:06:47.87#ibcon#*after write, iclass 17, count 0 2006.173.18:06:47.87#ibcon#*before return 0, iclass 17, count 0 2006.173.18:06:47.87#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.18:06:47.87#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.18:06:47.87#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.18:06:47.87#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.18:06:47.87$vck44/vblo=7,734.99 2006.173.18:06:47.87#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.18:06:47.87#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.18:06:47.87#ibcon#ireg 17 cls_cnt 0 2006.173.18:06:47.87#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.18:06:47.87#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.18:06:47.87#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.18:06:47.87#ibcon#enter wrdev, iclass 23, count 0 2006.173.18:06:47.87#ibcon#first serial, iclass 23, count 0 2006.173.18:06:47.87#ibcon#enter sib2, iclass 23, count 0 2006.173.18:06:47.87#ibcon#flushed, iclass 23, count 0 2006.173.18:06:47.87#ibcon#about to write, iclass 23, count 0 2006.173.18:06:47.87#ibcon#wrote, iclass 23, count 0 2006.173.18:06:47.87#ibcon#about to read 3, iclass 23, count 0 2006.173.18:06:47.89#ibcon#read 3, iclass 23, count 0 2006.173.18:06:47.89#ibcon#about to read 4, iclass 23, count 0 2006.173.18:06:47.89#ibcon#read 4, iclass 23, count 0 2006.173.18:06:47.89#ibcon#about to read 5, iclass 23, count 0 2006.173.18:06:47.89#ibcon#read 5, iclass 23, count 0 2006.173.18:06:47.89#ibcon#about to read 6, iclass 23, count 0 2006.173.18:06:47.89#ibcon#read 6, iclass 23, count 0 2006.173.18:06:47.89#ibcon#end of sib2, iclass 23, count 0 2006.173.18:06:47.89#ibcon#*mode == 0, iclass 23, count 0 2006.173.18:06:47.89#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.18:06:47.89#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.18:06:47.89#ibcon#*before write, iclass 23, count 0 2006.173.18:06:47.89#ibcon#enter sib2, iclass 23, count 0 2006.173.18:06:47.89#ibcon#flushed, iclass 23, count 0 2006.173.18:06:47.89#ibcon#about to write, iclass 23, count 0 2006.173.18:06:47.89#ibcon#wrote, iclass 23, count 0 2006.173.18:06:47.89#ibcon#about to read 3, iclass 23, count 0 2006.173.18:06:47.93#ibcon#read 3, iclass 23, count 0 2006.173.18:06:47.93#ibcon#about to read 4, iclass 23, count 0 2006.173.18:06:47.93#ibcon#read 4, iclass 23, count 0 2006.173.18:06:47.93#ibcon#about to read 5, iclass 23, count 0 2006.173.18:06:47.93#ibcon#read 5, iclass 23, count 0 2006.173.18:06:47.93#ibcon#about to read 6, iclass 23, count 0 2006.173.18:06:47.93#ibcon#read 6, iclass 23, count 0 2006.173.18:06:47.93#ibcon#end of sib2, iclass 23, count 0 2006.173.18:06:47.93#ibcon#*after write, iclass 23, count 0 2006.173.18:06:47.93#ibcon#*before return 0, iclass 23, count 0 2006.173.18:06:47.93#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.18:06:47.93#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.18:06:47.93#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.18:06:47.93#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.18:06:47.93$vck44/vb=7,4 2006.173.18:06:47.93#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.18:06:47.93#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.18:06:47.93#ibcon#ireg 11 cls_cnt 2 2006.173.18:06:47.93#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.18:06:47.99#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.18:06:47.99#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.18:06:47.99#ibcon#enter wrdev, iclass 25, count 2 2006.173.18:06:47.99#ibcon#first serial, iclass 25, count 2 2006.173.18:06:47.99#ibcon#enter sib2, iclass 25, count 2 2006.173.18:06:47.99#ibcon#flushed, iclass 25, count 2 2006.173.18:06:47.99#ibcon#about to write, iclass 25, count 2 2006.173.18:06:47.99#ibcon#wrote, iclass 25, count 2 2006.173.18:06:47.99#ibcon#about to read 3, iclass 25, count 2 2006.173.18:06:48.01#ibcon#read 3, iclass 25, count 2 2006.173.18:06:48.01#ibcon#about to read 4, iclass 25, count 2 2006.173.18:06:48.01#ibcon#read 4, iclass 25, count 2 2006.173.18:06:48.01#ibcon#about to read 5, iclass 25, count 2 2006.173.18:06:48.01#ibcon#read 5, iclass 25, count 2 2006.173.18:06:48.01#ibcon#about to read 6, iclass 25, count 2 2006.173.18:06:48.01#ibcon#read 6, iclass 25, count 2 2006.173.18:06:48.01#ibcon#end of sib2, iclass 25, count 2 2006.173.18:06:48.01#ibcon#*mode == 0, iclass 25, count 2 2006.173.18:06:48.01#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.18:06:48.01#ibcon#[27=AT07-04\r\n] 2006.173.18:06:48.01#ibcon#*before write, iclass 25, count 2 2006.173.18:06:48.01#ibcon#enter sib2, iclass 25, count 2 2006.173.18:06:48.01#ibcon#flushed, iclass 25, count 2 2006.173.18:06:48.01#ibcon#about to write, iclass 25, count 2 2006.173.18:06:48.01#ibcon#wrote, iclass 25, count 2 2006.173.18:06:48.01#ibcon#about to read 3, iclass 25, count 2 2006.173.18:06:48.04#ibcon#read 3, iclass 25, count 2 2006.173.18:06:48.04#ibcon#about to read 4, iclass 25, count 2 2006.173.18:06:48.04#ibcon#read 4, iclass 25, count 2 2006.173.18:06:48.04#ibcon#about to read 5, iclass 25, count 2 2006.173.18:06:48.04#ibcon#read 5, iclass 25, count 2 2006.173.18:06:48.04#ibcon#about to read 6, iclass 25, count 2 2006.173.18:06:48.04#ibcon#read 6, iclass 25, count 2 2006.173.18:06:48.04#ibcon#end of sib2, iclass 25, count 2 2006.173.18:06:48.04#ibcon#*after write, iclass 25, count 2 2006.173.18:06:48.04#ibcon#*before return 0, iclass 25, count 2 2006.173.18:06:48.04#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.18:06:48.04#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.18:06:48.04#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.18:06:48.04#ibcon#ireg 7 cls_cnt 0 2006.173.18:06:48.04#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.18:06:48.16#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.18:06:48.16#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.18:06:48.16#ibcon#enter wrdev, iclass 25, count 0 2006.173.18:06:48.16#ibcon#first serial, iclass 25, count 0 2006.173.18:06:48.16#ibcon#enter sib2, iclass 25, count 0 2006.173.18:06:48.16#ibcon#flushed, iclass 25, count 0 2006.173.18:06:48.16#ibcon#about to write, iclass 25, count 0 2006.173.18:06:48.16#ibcon#wrote, iclass 25, count 0 2006.173.18:06:48.16#ibcon#about to read 3, iclass 25, count 0 2006.173.18:06:48.18#ibcon#read 3, iclass 25, count 0 2006.173.18:06:48.18#ibcon#about to read 4, iclass 25, count 0 2006.173.18:06:48.18#ibcon#read 4, iclass 25, count 0 2006.173.18:06:48.18#ibcon#about to read 5, iclass 25, count 0 2006.173.18:06:48.18#ibcon#read 5, iclass 25, count 0 2006.173.18:06:48.18#ibcon#about to read 6, iclass 25, count 0 2006.173.18:06:48.18#ibcon#read 6, iclass 25, count 0 2006.173.18:06:48.18#ibcon#end of sib2, iclass 25, count 0 2006.173.18:06:48.18#ibcon#*mode == 0, iclass 25, count 0 2006.173.18:06:48.18#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.18:06:48.18#ibcon#[27=USB\r\n] 2006.173.18:06:48.18#ibcon#*before write, iclass 25, count 0 2006.173.18:06:48.18#ibcon#enter sib2, iclass 25, count 0 2006.173.18:06:48.18#ibcon#flushed, iclass 25, count 0 2006.173.18:06:48.18#ibcon#about to write, iclass 25, count 0 2006.173.18:06:48.18#ibcon#wrote, iclass 25, count 0 2006.173.18:06:48.18#ibcon#about to read 3, iclass 25, count 0 2006.173.18:06:48.21#ibcon#read 3, iclass 25, count 0 2006.173.18:06:48.21#ibcon#about to read 4, iclass 25, count 0 2006.173.18:06:48.21#ibcon#read 4, iclass 25, count 0 2006.173.18:06:48.21#ibcon#about to read 5, iclass 25, count 0 2006.173.18:06:48.21#ibcon#read 5, iclass 25, count 0 2006.173.18:06:48.21#ibcon#about to read 6, iclass 25, count 0 2006.173.18:06:48.21#ibcon#read 6, iclass 25, count 0 2006.173.18:06:48.21#ibcon#end of sib2, iclass 25, count 0 2006.173.18:06:48.21#ibcon#*after write, iclass 25, count 0 2006.173.18:06:48.21#ibcon#*before return 0, iclass 25, count 0 2006.173.18:06:48.21#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.18:06:48.21#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.18:06:48.21#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.18:06:48.21#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.18:06:48.21$vck44/vblo=8,744.99 2006.173.18:06:48.21#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.18:06:48.21#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.18:06:48.21#ibcon#ireg 17 cls_cnt 0 2006.173.18:06:48.21#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.18:06:48.21#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.18:06:48.21#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.18:06:48.21#ibcon#enter wrdev, iclass 27, count 0 2006.173.18:06:48.21#ibcon#first serial, iclass 27, count 0 2006.173.18:06:48.21#ibcon#enter sib2, iclass 27, count 0 2006.173.18:06:48.21#ibcon#flushed, iclass 27, count 0 2006.173.18:06:48.21#ibcon#about to write, iclass 27, count 0 2006.173.18:06:48.21#ibcon#wrote, iclass 27, count 0 2006.173.18:06:48.21#ibcon#about to read 3, iclass 27, count 0 2006.173.18:06:48.23#ibcon#read 3, iclass 27, count 0 2006.173.18:06:48.23#ibcon#about to read 4, iclass 27, count 0 2006.173.18:06:48.23#ibcon#read 4, iclass 27, count 0 2006.173.18:06:48.23#ibcon#about to read 5, iclass 27, count 0 2006.173.18:06:48.23#ibcon#read 5, iclass 27, count 0 2006.173.18:06:48.23#ibcon#about to read 6, iclass 27, count 0 2006.173.18:06:48.23#ibcon#read 6, iclass 27, count 0 2006.173.18:06:48.23#ibcon#end of sib2, iclass 27, count 0 2006.173.18:06:48.23#ibcon#*mode == 0, iclass 27, count 0 2006.173.18:06:48.23#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.18:06:48.23#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.18:06:48.23#ibcon#*before write, iclass 27, count 0 2006.173.18:06:48.23#ibcon#enter sib2, iclass 27, count 0 2006.173.18:06:48.23#ibcon#flushed, iclass 27, count 0 2006.173.18:06:48.23#ibcon#about to write, iclass 27, count 0 2006.173.18:06:48.23#ibcon#wrote, iclass 27, count 0 2006.173.18:06:48.23#ibcon#about to read 3, iclass 27, count 0 2006.173.18:06:48.27#ibcon#read 3, iclass 27, count 0 2006.173.18:06:48.27#ibcon#about to read 4, iclass 27, count 0 2006.173.18:06:48.27#ibcon#read 4, iclass 27, count 0 2006.173.18:06:48.27#ibcon#about to read 5, iclass 27, count 0 2006.173.18:06:48.27#ibcon#read 5, iclass 27, count 0 2006.173.18:06:48.27#ibcon#about to read 6, iclass 27, count 0 2006.173.18:06:48.27#ibcon#read 6, iclass 27, count 0 2006.173.18:06:48.27#ibcon#end of sib2, iclass 27, count 0 2006.173.18:06:48.27#ibcon#*after write, iclass 27, count 0 2006.173.18:06:48.27#ibcon#*before return 0, iclass 27, count 0 2006.173.18:06:48.27#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.18:06:48.27#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.18:06:48.27#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.18:06:48.27#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.18:06:48.27$vck44/vb=8,4 2006.173.18:06:48.27#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.18:06:48.27#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.18:06:48.27#ibcon#ireg 11 cls_cnt 2 2006.173.18:06:48.27#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.18:06:48.33#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.18:06:48.33#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.18:06:48.33#ibcon#enter wrdev, iclass 29, count 2 2006.173.18:06:48.33#ibcon#first serial, iclass 29, count 2 2006.173.18:06:48.33#ibcon#enter sib2, iclass 29, count 2 2006.173.18:06:48.33#ibcon#flushed, iclass 29, count 2 2006.173.18:06:48.33#ibcon#about to write, iclass 29, count 2 2006.173.18:06:48.33#ibcon#wrote, iclass 29, count 2 2006.173.18:06:48.33#ibcon#about to read 3, iclass 29, count 2 2006.173.18:06:48.35#ibcon#read 3, iclass 29, count 2 2006.173.18:06:48.35#ibcon#about to read 4, iclass 29, count 2 2006.173.18:06:48.35#ibcon#read 4, iclass 29, count 2 2006.173.18:06:48.35#ibcon#about to read 5, iclass 29, count 2 2006.173.18:06:48.35#ibcon#read 5, iclass 29, count 2 2006.173.18:06:48.35#ibcon#about to read 6, iclass 29, count 2 2006.173.18:06:48.35#ibcon#read 6, iclass 29, count 2 2006.173.18:06:48.35#ibcon#end of sib2, iclass 29, count 2 2006.173.18:06:48.35#ibcon#*mode == 0, iclass 29, count 2 2006.173.18:06:48.35#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.18:06:48.35#ibcon#[27=AT08-04\r\n] 2006.173.18:06:48.35#ibcon#*before write, iclass 29, count 2 2006.173.18:06:48.35#ibcon#enter sib2, iclass 29, count 2 2006.173.18:06:48.35#ibcon#flushed, iclass 29, count 2 2006.173.18:06:48.35#ibcon#about to write, iclass 29, count 2 2006.173.18:06:48.35#ibcon#wrote, iclass 29, count 2 2006.173.18:06:48.35#ibcon#about to read 3, iclass 29, count 2 2006.173.18:06:48.38#ibcon#read 3, iclass 29, count 2 2006.173.18:06:48.38#ibcon#about to read 4, iclass 29, count 2 2006.173.18:06:48.38#ibcon#read 4, iclass 29, count 2 2006.173.18:06:48.38#ibcon#about to read 5, iclass 29, count 2 2006.173.18:06:48.38#ibcon#read 5, iclass 29, count 2 2006.173.18:06:48.38#ibcon#about to read 6, iclass 29, count 2 2006.173.18:06:48.38#ibcon#read 6, iclass 29, count 2 2006.173.18:06:48.38#ibcon#end of sib2, iclass 29, count 2 2006.173.18:06:48.38#ibcon#*after write, iclass 29, count 2 2006.173.18:06:48.38#ibcon#*before return 0, iclass 29, count 2 2006.173.18:06:48.38#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.18:06:48.38#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.18:06:48.38#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.18:06:48.38#ibcon#ireg 7 cls_cnt 0 2006.173.18:06:48.38#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.18:06:48.50#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.18:06:48.50#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.18:06:48.50#ibcon#enter wrdev, iclass 29, count 0 2006.173.18:06:48.50#ibcon#first serial, iclass 29, count 0 2006.173.18:06:48.50#ibcon#enter sib2, iclass 29, count 0 2006.173.18:06:48.50#ibcon#flushed, iclass 29, count 0 2006.173.18:06:48.50#ibcon#about to write, iclass 29, count 0 2006.173.18:06:48.50#ibcon#wrote, iclass 29, count 0 2006.173.18:06:48.50#ibcon#about to read 3, iclass 29, count 0 2006.173.18:06:48.52#ibcon#read 3, iclass 29, count 0 2006.173.18:06:48.52#ibcon#about to read 4, iclass 29, count 0 2006.173.18:06:48.52#ibcon#read 4, iclass 29, count 0 2006.173.18:06:48.52#ibcon#about to read 5, iclass 29, count 0 2006.173.18:06:48.52#ibcon#read 5, iclass 29, count 0 2006.173.18:06:48.52#ibcon#about to read 6, iclass 29, count 0 2006.173.18:06:48.52#ibcon#read 6, iclass 29, count 0 2006.173.18:06:48.52#ibcon#end of sib2, iclass 29, count 0 2006.173.18:06:48.52#ibcon#*mode == 0, iclass 29, count 0 2006.173.18:06:48.52#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.18:06:48.52#ibcon#[27=USB\r\n] 2006.173.18:06:48.52#ibcon#*before write, iclass 29, count 0 2006.173.18:06:48.52#ibcon#enter sib2, iclass 29, count 0 2006.173.18:06:48.52#ibcon#flushed, iclass 29, count 0 2006.173.18:06:48.52#ibcon#about to write, iclass 29, count 0 2006.173.18:06:48.52#ibcon#wrote, iclass 29, count 0 2006.173.18:06:48.52#ibcon#about to read 3, iclass 29, count 0 2006.173.18:06:48.55#ibcon#read 3, iclass 29, count 0 2006.173.18:06:48.55#ibcon#about to read 4, iclass 29, count 0 2006.173.18:06:48.55#ibcon#read 4, iclass 29, count 0 2006.173.18:06:48.55#ibcon#about to read 5, iclass 29, count 0 2006.173.18:06:48.55#ibcon#read 5, iclass 29, count 0 2006.173.18:06:48.55#ibcon#about to read 6, iclass 29, count 0 2006.173.18:06:48.55#ibcon#read 6, iclass 29, count 0 2006.173.18:06:48.55#ibcon#end of sib2, iclass 29, count 0 2006.173.18:06:48.55#ibcon#*after write, iclass 29, count 0 2006.173.18:06:48.55#ibcon#*before return 0, iclass 29, count 0 2006.173.18:06:48.55#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.18:06:48.55#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.18:06:48.55#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.18:06:48.55#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.18:06:48.55$vck44/vabw=wide 2006.173.18:06:48.55#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.18:06:48.55#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.18:06:48.55#ibcon#ireg 8 cls_cnt 0 2006.173.18:06:48.55#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.18:06:48.55#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.18:06:48.55#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.18:06:48.55#ibcon#enter wrdev, iclass 31, count 0 2006.173.18:06:48.55#ibcon#first serial, iclass 31, count 0 2006.173.18:06:48.55#ibcon#enter sib2, iclass 31, count 0 2006.173.18:06:48.55#ibcon#flushed, iclass 31, count 0 2006.173.18:06:48.55#ibcon#about to write, iclass 31, count 0 2006.173.18:06:48.55#ibcon#wrote, iclass 31, count 0 2006.173.18:06:48.55#ibcon#about to read 3, iclass 31, count 0 2006.173.18:06:48.57#ibcon#read 3, iclass 31, count 0 2006.173.18:06:48.57#ibcon#about to read 4, iclass 31, count 0 2006.173.18:06:48.57#ibcon#read 4, iclass 31, count 0 2006.173.18:06:48.57#ibcon#about to read 5, iclass 31, count 0 2006.173.18:06:48.57#ibcon#read 5, iclass 31, count 0 2006.173.18:06:48.57#ibcon#about to read 6, iclass 31, count 0 2006.173.18:06:48.57#ibcon#read 6, iclass 31, count 0 2006.173.18:06:48.57#ibcon#end of sib2, iclass 31, count 0 2006.173.18:06:48.57#ibcon#*mode == 0, iclass 31, count 0 2006.173.18:06:48.57#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.18:06:48.57#ibcon#[25=BW32\r\n] 2006.173.18:06:48.57#ibcon#*before write, iclass 31, count 0 2006.173.18:06:48.57#ibcon#enter sib2, iclass 31, count 0 2006.173.18:06:48.57#ibcon#flushed, iclass 31, count 0 2006.173.18:06:48.57#ibcon#about to write, iclass 31, count 0 2006.173.18:06:48.57#ibcon#wrote, iclass 31, count 0 2006.173.18:06:48.57#ibcon#about to read 3, iclass 31, count 0 2006.173.18:06:48.60#ibcon#read 3, iclass 31, count 0 2006.173.18:06:48.60#ibcon#about to read 4, iclass 31, count 0 2006.173.18:06:48.60#ibcon#read 4, iclass 31, count 0 2006.173.18:06:48.60#ibcon#about to read 5, iclass 31, count 0 2006.173.18:06:48.60#ibcon#read 5, iclass 31, count 0 2006.173.18:06:48.60#ibcon#about to read 6, iclass 31, count 0 2006.173.18:06:48.60#ibcon#read 6, iclass 31, count 0 2006.173.18:06:48.60#ibcon#end of sib2, iclass 31, count 0 2006.173.18:06:48.60#ibcon#*after write, iclass 31, count 0 2006.173.18:06:48.60#ibcon#*before return 0, iclass 31, count 0 2006.173.18:06:48.60#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.18:06:48.60#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.18:06:48.60#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.18:06:48.60#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.18:06:48.60$vck44/vbbw=wide 2006.173.18:06:48.60#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.18:06:48.60#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.18:06:48.60#ibcon#ireg 8 cls_cnt 0 2006.173.18:06:48.60#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.18:06:48.67#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.18:06:48.67#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.18:06:48.67#ibcon#enter wrdev, iclass 33, count 0 2006.173.18:06:48.67#ibcon#first serial, iclass 33, count 0 2006.173.18:06:48.67#ibcon#enter sib2, iclass 33, count 0 2006.173.18:06:48.67#ibcon#flushed, iclass 33, count 0 2006.173.18:06:48.67#ibcon#about to write, iclass 33, count 0 2006.173.18:06:48.67#ibcon#wrote, iclass 33, count 0 2006.173.18:06:48.67#ibcon#about to read 3, iclass 33, count 0 2006.173.18:06:48.69#ibcon#read 3, iclass 33, count 0 2006.173.18:06:48.69#ibcon#about to read 4, iclass 33, count 0 2006.173.18:06:48.69#ibcon#read 4, iclass 33, count 0 2006.173.18:06:48.69#ibcon#about to read 5, iclass 33, count 0 2006.173.18:06:48.69#ibcon#read 5, iclass 33, count 0 2006.173.18:06:48.69#ibcon#about to read 6, iclass 33, count 0 2006.173.18:06:48.69#ibcon#read 6, iclass 33, count 0 2006.173.18:06:48.69#ibcon#end of sib2, iclass 33, count 0 2006.173.18:06:48.69#ibcon#*mode == 0, iclass 33, count 0 2006.173.18:06:48.69#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.18:06:48.69#ibcon#[27=BW32\r\n] 2006.173.18:06:48.69#ibcon#*before write, iclass 33, count 0 2006.173.18:06:48.69#ibcon#enter sib2, iclass 33, count 0 2006.173.18:06:48.69#ibcon#flushed, iclass 33, count 0 2006.173.18:06:48.69#ibcon#about to write, iclass 33, count 0 2006.173.18:06:48.69#ibcon#wrote, iclass 33, count 0 2006.173.18:06:48.69#ibcon#about to read 3, iclass 33, count 0 2006.173.18:06:48.72#ibcon#read 3, iclass 33, count 0 2006.173.18:06:48.72#ibcon#about to read 4, iclass 33, count 0 2006.173.18:06:48.72#ibcon#read 4, iclass 33, count 0 2006.173.18:06:48.72#ibcon#about to read 5, iclass 33, count 0 2006.173.18:06:48.72#ibcon#read 5, iclass 33, count 0 2006.173.18:06:48.72#ibcon#about to read 6, iclass 33, count 0 2006.173.18:06:48.72#ibcon#read 6, iclass 33, count 0 2006.173.18:06:48.72#ibcon#end of sib2, iclass 33, count 0 2006.173.18:06:48.72#ibcon#*after write, iclass 33, count 0 2006.173.18:06:48.72#ibcon#*before return 0, iclass 33, count 0 2006.173.18:06:48.72#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.18:06:48.72#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.18:06:48.72#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.18:06:48.72#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.18:06:48.72$setupk4/ifdk4 2006.173.18:06:48.72$ifdk4/lo= 2006.173.18:06:48.72$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.18:06:48.72$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.18:06:48.72$ifdk4/patch= 2006.173.18:06:48.72$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.18:06:48.72$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.18:06:48.72$setupk4/!*+20s 2006.173.18:06:57.96#abcon#<5=/14 1.1 2.2 20.021001002.2\r\n> 2006.173.18:06:57.98#abcon#{5=INTERFACE CLEAR} 2006.173.18:06:58.04#abcon#[5=S1D000X0/0*\r\n] 2006.173.18:07:03.23$setupk4/"tpicd 2006.173.18:07:03.23$setupk4/echo=off 2006.173.18:07:03.23$setupk4/xlog=off 2006.173.18:07:03.23:!2006.173.18:09:42 2006.173.18:07:11.13#trakl#Source acquired 2006.173.18:07:11.13#flagr#flagr/antenna,acquired 2006.173.18:09:42.00:preob 2006.173.18:09:42.14/onsource/TRACKING 2006.173.18:09:42.14:!2006.173.18:09:52 2006.173.18:09:52.00:"tape 2006.173.18:09:52.00:"st=record 2006.173.18:09:52.00:data_valid=on 2006.173.18:09:52.00:midob 2006.173.18:09:53.14/onsource/TRACKING 2006.173.18:09:53.14/wx/20.01,1002.2,100 2006.173.18:09:53.20/cable/+6.5150E-03 2006.173.18:09:54.29/va/01,07,usb,yes,36,39 2006.173.18:09:54.29/va/02,06,usb,yes,36,37 2006.173.18:09:54.29/va/03,05,usb,yes,46,48 2006.173.18:09:54.29/va/04,06,usb,yes,37,39 2006.173.18:09:54.29/va/05,04,usb,yes,29,29 2006.173.18:09:54.29/va/06,03,usb,yes,40,40 2006.173.18:09:54.29/va/07,04,usb,yes,33,34 2006.173.18:09:54.29/va/08,04,usb,yes,28,33 2006.173.18:09:54.52/valo/01,524.99,yes,locked 2006.173.18:09:54.52/valo/02,534.99,yes,locked 2006.173.18:09:54.52/valo/03,564.99,yes,locked 2006.173.18:09:54.52/valo/04,624.99,yes,locked 2006.173.18:09:54.52/valo/05,734.99,yes,locked 2006.173.18:09:54.52/valo/06,814.99,yes,locked 2006.173.18:09:54.52/valo/07,864.99,yes,locked 2006.173.18:09:54.52/valo/08,884.99,yes,locked 2006.173.18:09:55.61/vb/01,04,usb,yes,30,28 2006.173.18:09:55.61/vb/02,04,usb,yes,32,32 2006.173.18:09:55.61/vb/03,04,usb,yes,29,32 2006.173.18:09:55.61/vb/04,04,usb,yes,34,32 2006.173.18:09:55.61/vb/05,04,usb,yes,26,28 2006.173.18:09:55.61/vb/06,04,usb,yes,30,27 2006.173.18:09:55.61/vb/07,04,usb,yes,30,30 2006.173.18:09:55.61/vb/08,04,usb,yes,28,31 2006.173.18:09:55.84/vblo/01,629.99,yes,locked 2006.173.18:09:55.84/vblo/02,634.99,yes,locked 2006.173.18:09:55.84/vblo/03,649.99,yes,locked 2006.173.18:09:55.84/vblo/04,679.99,yes,locked 2006.173.18:09:55.84/vblo/05,709.99,yes,locked 2006.173.18:09:55.84/vblo/06,719.99,yes,locked 2006.173.18:09:55.84/vblo/07,734.99,yes,locked 2006.173.18:09:55.84/vblo/08,744.99,yes,locked 2006.173.18:09:55.99/vabw/8 2006.173.18:09:56.14/vbbw/8 2006.173.18:09:56.25/xfe/off,on,15.2 2006.173.18:09:56.64/ifatt/23,28,28,28 2006.173.18:09:57.07/fmout-gps/S +4.00E-07 2006.173.18:09:57.11:!2006.173.18:11:02 2006.173.18:11:02.01:data_valid=off 2006.173.18:11:02.02:"et 2006.173.18:11:02.02:!+3s 2006.173.18:11:05.03:"tape 2006.173.18:11:05.03:postob 2006.173.18:11:05.20/cable/+6.5138E-03 2006.173.18:11:05.21/wx/20.00,1002.2,100 2006.173.18:11:05.26/fmout-gps/S +4.00E-07 2006.173.18:11:05.27:scan_name=173-1814,jd0606,260 2006.173.18:11:05.27:source=1044+719,104827.62,714335.9,2000.0,neutral 2006.173.18:11:07.14#flagr#flagr/antenna,new-source 2006.173.18:11:07.15:checkk5 2006.173.18:11:07.57/chk_autoobs//k5ts1/ autoobs is running! 2006.173.18:11:07.97/chk_autoobs//k5ts2/ autoobs is running! 2006.173.18:11:08.37/chk_autoobs//k5ts3/ autoobs is running! 2006.173.18:11:08.77/chk_autoobs//k5ts4/ autoobs is running! 2006.173.18:11:09.16/chk_obsdata//k5ts1/T1731809??a.dat file size is correct (nominal:280MB, actual:276MB). 2006.173.18:11:09.55/chk_obsdata//k5ts2/T1731809??b.dat file size is correct (nominal:280MB, actual:276MB). 2006.173.18:11:09.95/chk_obsdata//k5ts3/T1731809??c.dat file size is correct (nominal:280MB, actual:276MB). 2006.173.18:11:10.36/chk_obsdata//k5ts4/T1731809??d.dat file size is correct (nominal:280MB, actual:276MB). 2006.173.18:11:11.08/k5log//k5ts1_log_newline 2006.173.18:11:11.81/k5log//k5ts2_log_newline 2006.173.18:11:12.52/k5log//k5ts3_log_newline 2006.173.18:11:13.23/k5log//k5ts4_log_newline 2006.173.18:11:13.25/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.18:11:13.25:setupk4=1 2006.173.18:11:13.25$setupk4/echo=on 2006.173.18:11:13.26$setupk4/pcalon 2006.173.18:11:13.26$pcalon/"no phase cal control is implemented here 2006.173.18:11:13.26$setupk4/"tpicd=stop 2006.173.18:11:13.26$setupk4/"rec=synch_on 2006.173.18:11:13.26$setupk4/"rec_mode=128 2006.173.18:11:13.26$setupk4/!* 2006.173.18:11:13.26$setupk4/recpk4 2006.173.18:11:13.26$recpk4/recpatch= 2006.173.18:11:13.26$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.18:11:13.26$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.18:11:13.26$setupk4/vck44 2006.173.18:11:13.26$vck44/valo=1,524.99 2006.173.18:11:13.26#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.18:11:13.26#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.18:11:13.26#ibcon#ireg 17 cls_cnt 0 2006.173.18:11:13.26#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.18:11:13.26#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.18:11:13.26#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.18:11:13.26#ibcon#enter wrdev, iclass 34, count 0 2006.173.18:11:13.26#ibcon#first serial, iclass 34, count 0 2006.173.18:11:13.26#ibcon#enter sib2, iclass 34, count 0 2006.173.18:11:13.26#ibcon#flushed, iclass 34, count 0 2006.173.18:11:13.26#ibcon#about to write, iclass 34, count 0 2006.173.18:11:13.26#ibcon#wrote, iclass 34, count 0 2006.173.18:11:13.26#ibcon#about to read 3, iclass 34, count 0 2006.173.18:11:13.27#ibcon#read 3, iclass 34, count 0 2006.173.18:11:13.27#ibcon#about to read 4, iclass 34, count 0 2006.173.18:11:13.27#ibcon#read 4, iclass 34, count 0 2006.173.18:11:13.27#ibcon#about to read 5, iclass 34, count 0 2006.173.18:11:13.27#ibcon#read 5, iclass 34, count 0 2006.173.18:11:13.27#ibcon#about to read 6, iclass 34, count 0 2006.173.18:11:13.27#ibcon#read 6, iclass 34, count 0 2006.173.18:11:13.27#ibcon#end of sib2, iclass 34, count 0 2006.173.18:11:13.27#ibcon#*mode == 0, iclass 34, count 0 2006.173.18:11:13.27#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.18:11:13.27#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.18:11:13.27#ibcon#*before write, iclass 34, count 0 2006.173.18:11:13.27#ibcon#enter sib2, iclass 34, count 0 2006.173.18:11:13.27#ibcon#flushed, iclass 34, count 0 2006.173.18:11:13.27#ibcon#about to write, iclass 34, count 0 2006.173.18:11:13.27#ibcon#wrote, iclass 34, count 0 2006.173.18:11:13.27#ibcon#about to read 3, iclass 34, count 0 2006.173.18:11:13.32#ibcon#read 3, iclass 34, count 0 2006.173.18:11:13.32#ibcon#about to read 4, iclass 34, count 0 2006.173.18:11:13.32#ibcon#read 4, iclass 34, count 0 2006.173.18:11:13.32#ibcon#about to read 5, iclass 34, count 0 2006.173.18:11:13.32#ibcon#read 5, iclass 34, count 0 2006.173.18:11:13.32#ibcon#about to read 6, iclass 34, count 0 2006.173.18:11:13.32#ibcon#read 6, iclass 34, count 0 2006.173.18:11:13.32#ibcon#end of sib2, iclass 34, count 0 2006.173.18:11:13.32#ibcon#*after write, iclass 34, count 0 2006.173.18:11:13.32#ibcon#*before return 0, iclass 34, count 0 2006.173.18:11:13.32#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.18:11:13.32#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.18:11:13.32#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.18:11:13.32#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.18:11:13.32$vck44/va=1,7 2006.173.18:11:13.32#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.18:11:13.32#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.18:11:13.32#ibcon#ireg 11 cls_cnt 2 2006.173.18:11:13.32#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.18:11:13.32#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.18:11:13.32#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.18:11:13.32#ibcon#enter wrdev, iclass 36, count 2 2006.173.18:11:13.32#ibcon#first serial, iclass 36, count 2 2006.173.18:11:13.32#ibcon#enter sib2, iclass 36, count 2 2006.173.18:11:13.32#ibcon#flushed, iclass 36, count 2 2006.173.18:11:13.32#ibcon#about to write, iclass 36, count 2 2006.173.18:11:13.32#ibcon#wrote, iclass 36, count 2 2006.173.18:11:13.32#ibcon#about to read 3, iclass 36, count 2 2006.173.18:11:13.34#ibcon#read 3, iclass 36, count 2 2006.173.18:11:13.34#ibcon#about to read 4, iclass 36, count 2 2006.173.18:11:13.34#ibcon#read 4, iclass 36, count 2 2006.173.18:11:13.34#ibcon#about to read 5, iclass 36, count 2 2006.173.18:11:13.34#ibcon#read 5, iclass 36, count 2 2006.173.18:11:13.34#ibcon#about to read 6, iclass 36, count 2 2006.173.18:11:13.34#ibcon#read 6, iclass 36, count 2 2006.173.18:11:13.34#ibcon#end of sib2, iclass 36, count 2 2006.173.18:11:13.34#ibcon#*mode == 0, iclass 36, count 2 2006.173.18:11:13.34#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.18:11:13.34#ibcon#[25=AT01-07\r\n] 2006.173.18:11:13.34#ibcon#*before write, iclass 36, count 2 2006.173.18:11:13.34#ibcon#enter sib2, iclass 36, count 2 2006.173.18:11:13.34#ibcon#flushed, iclass 36, count 2 2006.173.18:11:13.34#ibcon#about to write, iclass 36, count 2 2006.173.18:11:13.34#ibcon#wrote, iclass 36, count 2 2006.173.18:11:13.34#ibcon#about to read 3, iclass 36, count 2 2006.173.18:11:13.37#ibcon#read 3, iclass 36, count 2 2006.173.18:11:13.37#ibcon#about to read 4, iclass 36, count 2 2006.173.18:11:13.37#ibcon#read 4, iclass 36, count 2 2006.173.18:11:13.37#ibcon#about to read 5, iclass 36, count 2 2006.173.18:11:13.37#ibcon#read 5, iclass 36, count 2 2006.173.18:11:13.37#ibcon#about to read 6, iclass 36, count 2 2006.173.18:11:13.37#ibcon#read 6, iclass 36, count 2 2006.173.18:11:13.37#ibcon#end of sib2, iclass 36, count 2 2006.173.18:11:13.37#ibcon#*after write, iclass 36, count 2 2006.173.18:11:13.37#ibcon#*before return 0, iclass 36, count 2 2006.173.18:11:13.37#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.18:11:13.37#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.18:11:13.37#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.18:11:13.37#ibcon#ireg 7 cls_cnt 0 2006.173.18:11:13.37#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.18:11:13.49#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.18:11:13.49#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.18:11:13.49#ibcon#enter wrdev, iclass 36, count 0 2006.173.18:11:13.49#ibcon#first serial, iclass 36, count 0 2006.173.18:11:13.49#ibcon#enter sib2, iclass 36, count 0 2006.173.18:11:13.49#ibcon#flushed, iclass 36, count 0 2006.173.18:11:13.49#ibcon#about to write, iclass 36, count 0 2006.173.18:11:13.49#ibcon#wrote, iclass 36, count 0 2006.173.18:11:13.49#ibcon#about to read 3, iclass 36, count 0 2006.173.18:11:13.51#ibcon#read 3, iclass 36, count 0 2006.173.18:11:13.51#ibcon#about to read 4, iclass 36, count 0 2006.173.18:11:13.51#ibcon#read 4, iclass 36, count 0 2006.173.18:11:13.51#ibcon#about to read 5, iclass 36, count 0 2006.173.18:11:13.51#ibcon#read 5, iclass 36, count 0 2006.173.18:11:13.51#ibcon#about to read 6, iclass 36, count 0 2006.173.18:11:13.51#ibcon#read 6, iclass 36, count 0 2006.173.18:11:13.51#ibcon#end of sib2, iclass 36, count 0 2006.173.18:11:13.51#ibcon#*mode == 0, iclass 36, count 0 2006.173.18:11:13.51#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.18:11:13.51#ibcon#[25=USB\r\n] 2006.173.18:11:13.51#ibcon#*before write, iclass 36, count 0 2006.173.18:11:13.51#ibcon#enter sib2, iclass 36, count 0 2006.173.18:11:13.51#ibcon#flushed, iclass 36, count 0 2006.173.18:11:13.51#ibcon#about to write, iclass 36, count 0 2006.173.18:11:13.51#ibcon#wrote, iclass 36, count 0 2006.173.18:11:13.51#ibcon#about to read 3, iclass 36, count 0 2006.173.18:11:13.54#ibcon#read 3, iclass 36, count 0 2006.173.18:11:13.54#ibcon#about to read 4, iclass 36, count 0 2006.173.18:11:13.54#ibcon#read 4, iclass 36, count 0 2006.173.18:11:13.54#ibcon#about to read 5, iclass 36, count 0 2006.173.18:11:13.54#ibcon#read 5, iclass 36, count 0 2006.173.18:11:13.54#ibcon#about to read 6, iclass 36, count 0 2006.173.18:11:13.54#ibcon#read 6, iclass 36, count 0 2006.173.18:11:13.54#ibcon#end of sib2, iclass 36, count 0 2006.173.18:11:13.54#ibcon#*after write, iclass 36, count 0 2006.173.18:11:13.54#ibcon#*before return 0, iclass 36, count 0 2006.173.18:11:13.54#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.18:11:13.54#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.18:11:13.54#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.18:11:13.54#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.18:11:13.54$vck44/valo=2,534.99 2006.173.18:11:13.54#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.18:11:13.54#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.18:11:13.54#ibcon#ireg 17 cls_cnt 0 2006.173.18:11:13.54#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.18:11:13.54#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.18:11:13.54#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.18:11:13.54#ibcon#enter wrdev, iclass 38, count 0 2006.173.18:11:13.54#ibcon#first serial, iclass 38, count 0 2006.173.18:11:13.54#ibcon#enter sib2, iclass 38, count 0 2006.173.18:11:13.54#ibcon#flushed, iclass 38, count 0 2006.173.18:11:13.54#ibcon#about to write, iclass 38, count 0 2006.173.18:11:13.54#ibcon#wrote, iclass 38, count 0 2006.173.18:11:13.54#ibcon#about to read 3, iclass 38, count 0 2006.173.18:11:13.56#ibcon#read 3, iclass 38, count 0 2006.173.18:11:13.56#ibcon#about to read 4, iclass 38, count 0 2006.173.18:11:13.56#ibcon#read 4, iclass 38, count 0 2006.173.18:11:13.56#ibcon#about to read 5, iclass 38, count 0 2006.173.18:11:13.56#ibcon#read 5, iclass 38, count 0 2006.173.18:11:13.56#ibcon#about to read 6, iclass 38, count 0 2006.173.18:11:13.56#ibcon#read 6, iclass 38, count 0 2006.173.18:11:13.56#ibcon#end of sib2, iclass 38, count 0 2006.173.18:11:13.56#ibcon#*mode == 0, iclass 38, count 0 2006.173.18:11:13.56#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.18:11:13.56#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.18:11:13.56#ibcon#*before write, iclass 38, count 0 2006.173.18:11:13.56#ibcon#enter sib2, iclass 38, count 0 2006.173.18:11:13.56#ibcon#flushed, iclass 38, count 0 2006.173.18:11:13.56#ibcon#about to write, iclass 38, count 0 2006.173.18:11:13.56#ibcon#wrote, iclass 38, count 0 2006.173.18:11:13.56#ibcon#about to read 3, iclass 38, count 0 2006.173.18:11:13.60#ibcon#read 3, iclass 38, count 0 2006.173.18:11:13.60#ibcon#about to read 4, iclass 38, count 0 2006.173.18:11:13.60#ibcon#read 4, iclass 38, count 0 2006.173.18:11:13.60#ibcon#about to read 5, iclass 38, count 0 2006.173.18:11:13.60#ibcon#read 5, iclass 38, count 0 2006.173.18:11:13.60#ibcon#about to read 6, iclass 38, count 0 2006.173.18:11:13.60#ibcon#read 6, iclass 38, count 0 2006.173.18:11:13.60#ibcon#end of sib2, iclass 38, count 0 2006.173.18:11:13.60#ibcon#*after write, iclass 38, count 0 2006.173.18:11:13.60#ibcon#*before return 0, iclass 38, count 0 2006.173.18:11:13.60#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.18:11:13.60#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.18:11:13.60#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.18:11:13.60#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.18:11:13.60$vck44/va=2,6 2006.173.18:11:13.60#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.18:11:13.60#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.18:11:13.60#ibcon#ireg 11 cls_cnt 2 2006.173.18:11:13.60#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.18:11:13.66#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.18:11:13.66#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.18:11:13.66#ibcon#enter wrdev, iclass 40, count 2 2006.173.18:11:13.66#ibcon#first serial, iclass 40, count 2 2006.173.18:11:13.66#ibcon#enter sib2, iclass 40, count 2 2006.173.18:11:13.66#ibcon#flushed, iclass 40, count 2 2006.173.18:11:13.66#ibcon#about to write, iclass 40, count 2 2006.173.18:11:13.66#ibcon#wrote, iclass 40, count 2 2006.173.18:11:13.66#ibcon#about to read 3, iclass 40, count 2 2006.173.18:11:13.68#ibcon#read 3, iclass 40, count 2 2006.173.18:11:13.68#ibcon#about to read 4, iclass 40, count 2 2006.173.18:11:13.68#ibcon#read 4, iclass 40, count 2 2006.173.18:11:13.68#ibcon#about to read 5, iclass 40, count 2 2006.173.18:11:13.68#ibcon#read 5, iclass 40, count 2 2006.173.18:11:13.68#ibcon#about to read 6, iclass 40, count 2 2006.173.18:11:13.68#ibcon#read 6, iclass 40, count 2 2006.173.18:11:13.68#ibcon#end of sib2, iclass 40, count 2 2006.173.18:11:13.68#ibcon#*mode == 0, iclass 40, count 2 2006.173.18:11:13.68#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.18:11:13.68#ibcon#[25=AT02-06\r\n] 2006.173.18:11:13.68#ibcon#*before write, iclass 40, count 2 2006.173.18:11:13.68#ibcon#enter sib2, iclass 40, count 2 2006.173.18:11:13.68#ibcon#flushed, iclass 40, count 2 2006.173.18:11:13.68#ibcon#about to write, iclass 40, count 2 2006.173.18:11:13.68#ibcon#wrote, iclass 40, count 2 2006.173.18:11:13.68#ibcon#about to read 3, iclass 40, count 2 2006.173.18:11:13.71#ibcon#read 3, iclass 40, count 2 2006.173.18:11:13.71#ibcon#about to read 4, iclass 40, count 2 2006.173.18:11:13.71#ibcon#read 4, iclass 40, count 2 2006.173.18:11:13.71#ibcon#about to read 5, iclass 40, count 2 2006.173.18:11:13.71#ibcon#read 5, iclass 40, count 2 2006.173.18:11:13.71#ibcon#about to read 6, iclass 40, count 2 2006.173.18:11:13.71#ibcon#read 6, iclass 40, count 2 2006.173.18:11:13.71#ibcon#end of sib2, iclass 40, count 2 2006.173.18:11:13.71#ibcon#*after write, iclass 40, count 2 2006.173.18:11:13.71#ibcon#*before return 0, iclass 40, count 2 2006.173.18:11:13.71#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.18:11:13.71#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.18:11:13.71#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.18:11:13.71#ibcon#ireg 7 cls_cnt 0 2006.173.18:11:13.71#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.18:11:13.83#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.18:11:13.83#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.18:11:13.83#ibcon#enter wrdev, iclass 40, count 0 2006.173.18:11:13.83#ibcon#first serial, iclass 40, count 0 2006.173.18:11:13.83#ibcon#enter sib2, iclass 40, count 0 2006.173.18:11:13.83#ibcon#flushed, iclass 40, count 0 2006.173.18:11:13.83#ibcon#about to write, iclass 40, count 0 2006.173.18:11:13.83#ibcon#wrote, iclass 40, count 0 2006.173.18:11:13.83#ibcon#about to read 3, iclass 40, count 0 2006.173.18:11:13.85#ibcon#read 3, iclass 40, count 0 2006.173.18:11:13.85#ibcon#about to read 4, iclass 40, count 0 2006.173.18:11:13.85#ibcon#read 4, iclass 40, count 0 2006.173.18:11:13.85#ibcon#about to read 5, iclass 40, count 0 2006.173.18:11:13.85#ibcon#read 5, iclass 40, count 0 2006.173.18:11:13.85#ibcon#about to read 6, iclass 40, count 0 2006.173.18:11:13.85#ibcon#read 6, iclass 40, count 0 2006.173.18:11:13.85#ibcon#end of sib2, iclass 40, count 0 2006.173.18:11:13.85#ibcon#*mode == 0, iclass 40, count 0 2006.173.18:11:13.85#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.18:11:13.85#ibcon#[25=USB\r\n] 2006.173.18:11:13.85#ibcon#*before write, iclass 40, count 0 2006.173.18:11:13.85#ibcon#enter sib2, iclass 40, count 0 2006.173.18:11:13.85#ibcon#flushed, iclass 40, count 0 2006.173.18:11:13.85#ibcon#about to write, iclass 40, count 0 2006.173.18:11:13.85#ibcon#wrote, iclass 40, count 0 2006.173.18:11:13.85#ibcon#about to read 3, iclass 40, count 0 2006.173.18:11:13.88#ibcon#read 3, iclass 40, count 0 2006.173.18:11:13.88#ibcon#about to read 4, iclass 40, count 0 2006.173.18:11:13.88#ibcon#read 4, iclass 40, count 0 2006.173.18:11:13.88#ibcon#about to read 5, iclass 40, count 0 2006.173.18:11:13.88#ibcon#read 5, iclass 40, count 0 2006.173.18:11:13.88#ibcon#about to read 6, iclass 40, count 0 2006.173.18:11:13.88#ibcon#read 6, iclass 40, count 0 2006.173.18:11:13.88#ibcon#end of sib2, iclass 40, count 0 2006.173.18:11:13.88#ibcon#*after write, iclass 40, count 0 2006.173.18:11:13.88#ibcon#*before return 0, iclass 40, count 0 2006.173.18:11:13.88#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.18:11:13.88#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.18:11:13.88#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.18:11:13.88#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.18:11:13.88$vck44/valo=3,564.99 2006.173.18:11:13.88#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.18:11:13.88#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.18:11:13.88#ibcon#ireg 17 cls_cnt 0 2006.173.18:11:13.88#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.18:11:13.88#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.18:11:13.88#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.18:11:13.88#ibcon#enter wrdev, iclass 4, count 0 2006.173.18:11:13.88#ibcon#first serial, iclass 4, count 0 2006.173.18:11:13.88#ibcon#enter sib2, iclass 4, count 0 2006.173.18:11:13.88#ibcon#flushed, iclass 4, count 0 2006.173.18:11:13.88#ibcon#about to write, iclass 4, count 0 2006.173.18:11:13.88#ibcon#wrote, iclass 4, count 0 2006.173.18:11:13.88#ibcon#about to read 3, iclass 4, count 0 2006.173.18:11:13.90#ibcon#read 3, iclass 4, count 0 2006.173.18:11:13.90#ibcon#about to read 4, iclass 4, count 0 2006.173.18:11:13.90#ibcon#read 4, iclass 4, count 0 2006.173.18:11:13.90#ibcon#about to read 5, iclass 4, count 0 2006.173.18:11:13.90#ibcon#read 5, iclass 4, count 0 2006.173.18:11:13.90#ibcon#about to read 6, iclass 4, count 0 2006.173.18:11:13.90#ibcon#read 6, iclass 4, count 0 2006.173.18:11:13.90#ibcon#end of sib2, iclass 4, count 0 2006.173.18:11:13.90#ibcon#*mode == 0, iclass 4, count 0 2006.173.18:11:13.90#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.18:11:13.90#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.18:11:13.90#ibcon#*before write, iclass 4, count 0 2006.173.18:11:13.90#ibcon#enter sib2, iclass 4, count 0 2006.173.18:11:13.90#ibcon#flushed, iclass 4, count 0 2006.173.18:11:13.90#ibcon#about to write, iclass 4, count 0 2006.173.18:11:13.90#ibcon#wrote, iclass 4, count 0 2006.173.18:11:13.90#ibcon#about to read 3, iclass 4, count 0 2006.173.18:11:13.94#ibcon#read 3, iclass 4, count 0 2006.173.18:11:13.94#ibcon#about to read 4, iclass 4, count 0 2006.173.18:11:13.94#ibcon#read 4, iclass 4, count 0 2006.173.18:11:13.94#ibcon#about to read 5, iclass 4, count 0 2006.173.18:11:13.94#ibcon#read 5, iclass 4, count 0 2006.173.18:11:13.94#ibcon#about to read 6, iclass 4, count 0 2006.173.18:11:13.94#ibcon#read 6, iclass 4, count 0 2006.173.18:11:13.94#ibcon#end of sib2, iclass 4, count 0 2006.173.18:11:13.94#ibcon#*after write, iclass 4, count 0 2006.173.18:11:13.94#ibcon#*before return 0, iclass 4, count 0 2006.173.18:11:13.94#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.18:11:13.94#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.18:11:13.94#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.18:11:13.94#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.18:11:13.94$vck44/va=3,5 2006.173.18:11:13.94#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.18:11:13.94#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.18:11:13.94#ibcon#ireg 11 cls_cnt 2 2006.173.18:11:13.94#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.18:11:14.00#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.18:11:14.00#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.18:11:14.00#ibcon#enter wrdev, iclass 6, count 2 2006.173.18:11:14.00#ibcon#first serial, iclass 6, count 2 2006.173.18:11:14.00#ibcon#enter sib2, iclass 6, count 2 2006.173.18:11:14.00#ibcon#flushed, iclass 6, count 2 2006.173.18:11:14.00#ibcon#about to write, iclass 6, count 2 2006.173.18:11:14.00#ibcon#wrote, iclass 6, count 2 2006.173.18:11:14.00#ibcon#about to read 3, iclass 6, count 2 2006.173.18:11:14.02#ibcon#read 3, iclass 6, count 2 2006.173.18:11:14.02#ibcon#about to read 4, iclass 6, count 2 2006.173.18:11:14.02#ibcon#read 4, iclass 6, count 2 2006.173.18:11:14.02#ibcon#about to read 5, iclass 6, count 2 2006.173.18:11:14.02#ibcon#read 5, iclass 6, count 2 2006.173.18:11:14.02#ibcon#about to read 6, iclass 6, count 2 2006.173.18:11:14.02#ibcon#read 6, iclass 6, count 2 2006.173.18:11:14.02#ibcon#end of sib2, iclass 6, count 2 2006.173.18:11:14.02#ibcon#*mode == 0, iclass 6, count 2 2006.173.18:11:14.02#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.18:11:14.02#ibcon#[25=AT03-05\r\n] 2006.173.18:11:14.02#ibcon#*before write, iclass 6, count 2 2006.173.18:11:14.02#ibcon#enter sib2, iclass 6, count 2 2006.173.18:11:14.02#ibcon#flushed, iclass 6, count 2 2006.173.18:11:14.02#ibcon#about to write, iclass 6, count 2 2006.173.18:11:14.02#ibcon#wrote, iclass 6, count 2 2006.173.18:11:14.02#ibcon#about to read 3, iclass 6, count 2 2006.173.18:11:14.05#ibcon#read 3, iclass 6, count 2 2006.173.18:11:14.05#ibcon#about to read 4, iclass 6, count 2 2006.173.18:11:14.05#ibcon#read 4, iclass 6, count 2 2006.173.18:11:14.05#ibcon#about to read 5, iclass 6, count 2 2006.173.18:11:14.05#ibcon#read 5, iclass 6, count 2 2006.173.18:11:14.05#ibcon#about to read 6, iclass 6, count 2 2006.173.18:11:14.05#ibcon#read 6, iclass 6, count 2 2006.173.18:11:14.05#ibcon#end of sib2, iclass 6, count 2 2006.173.18:11:14.05#ibcon#*after write, iclass 6, count 2 2006.173.18:11:14.05#ibcon#*before return 0, iclass 6, count 2 2006.173.18:11:14.05#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.18:11:14.05#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.18:11:14.05#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.18:11:14.05#ibcon#ireg 7 cls_cnt 0 2006.173.18:11:14.05#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.18:11:14.17#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.18:11:14.17#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.18:11:14.17#ibcon#enter wrdev, iclass 6, count 0 2006.173.18:11:14.17#ibcon#first serial, iclass 6, count 0 2006.173.18:11:14.17#ibcon#enter sib2, iclass 6, count 0 2006.173.18:11:14.17#ibcon#flushed, iclass 6, count 0 2006.173.18:11:14.17#ibcon#about to write, iclass 6, count 0 2006.173.18:11:14.17#ibcon#wrote, iclass 6, count 0 2006.173.18:11:14.17#ibcon#about to read 3, iclass 6, count 0 2006.173.18:11:14.19#ibcon#read 3, iclass 6, count 0 2006.173.18:11:14.19#ibcon#about to read 4, iclass 6, count 0 2006.173.18:11:14.19#ibcon#read 4, iclass 6, count 0 2006.173.18:11:14.19#ibcon#about to read 5, iclass 6, count 0 2006.173.18:11:14.19#ibcon#read 5, iclass 6, count 0 2006.173.18:11:14.19#ibcon#about to read 6, iclass 6, count 0 2006.173.18:11:14.19#ibcon#read 6, iclass 6, count 0 2006.173.18:11:14.19#ibcon#end of sib2, iclass 6, count 0 2006.173.18:11:14.19#ibcon#*mode == 0, iclass 6, count 0 2006.173.18:11:14.19#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.18:11:14.19#ibcon#[25=USB\r\n] 2006.173.18:11:14.19#ibcon#*before write, iclass 6, count 0 2006.173.18:11:14.19#ibcon#enter sib2, iclass 6, count 0 2006.173.18:11:14.19#ibcon#flushed, iclass 6, count 0 2006.173.18:11:14.19#ibcon#about to write, iclass 6, count 0 2006.173.18:11:14.19#ibcon#wrote, iclass 6, count 0 2006.173.18:11:14.19#ibcon#about to read 3, iclass 6, count 0 2006.173.18:11:14.22#ibcon#read 3, iclass 6, count 0 2006.173.18:11:14.22#ibcon#about to read 4, iclass 6, count 0 2006.173.18:11:14.22#ibcon#read 4, iclass 6, count 0 2006.173.18:11:14.22#ibcon#about to read 5, iclass 6, count 0 2006.173.18:11:14.22#ibcon#read 5, iclass 6, count 0 2006.173.18:11:14.22#ibcon#about to read 6, iclass 6, count 0 2006.173.18:11:14.22#ibcon#read 6, iclass 6, count 0 2006.173.18:11:14.22#ibcon#end of sib2, iclass 6, count 0 2006.173.18:11:14.22#ibcon#*after write, iclass 6, count 0 2006.173.18:11:14.22#ibcon#*before return 0, iclass 6, count 0 2006.173.18:11:14.22#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.18:11:14.22#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.18:11:14.22#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.18:11:14.22#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.18:11:14.22$vck44/valo=4,624.99 2006.173.18:11:14.22#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.18:11:14.22#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.18:11:14.22#ibcon#ireg 17 cls_cnt 0 2006.173.18:11:14.22#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.18:11:14.22#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.18:11:14.22#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.18:11:14.22#ibcon#enter wrdev, iclass 10, count 0 2006.173.18:11:14.22#ibcon#first serial, iclass 10, count 0 2006.173.18:11:14.22#ibcon#enter sib2, iclass 10, count 0 2006.173.18:11:14.22#ibcon#flushed, iclass 10, count 0 2006.173.18:11:14.22#ibcon#about to write, iclass 10, count 0 2006.173.18:11:14.22#ibcon#wrote, iclass 10, count 0 2006.173.18:11:14.22#ibcon#about to read 3, iclass 10, count 0 2006.173.18:11:14.24#ibcon#read 3, iclass 10, count 0 2006.173.18:11:14.24#ibcon#about to read 4, iclass 10, count 0 2006.173.18:11:14.24#ibcon#read 4, iclass 10, count 0 2006.173.18:11:14.24#ibcon#about to read 5, iclass 10, count 0 2006.173.18:11:14.24#ibcon#read 5, iclass 10, count 0 2006.173.18:11:14.24#ibcon#about to read 6, iclass 10, count 0 2006.173.18:11:14.24#ibcon#read 6, iclass 10, count 0 2006.173.18:11:14.24#ibcon#end of sib2, iclass 10, count 0 2006.173.18:11:14.24#ibcon#*mode == 0, iclass 10, count 0 2006.173.18:11:14.24#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.18:11:14.24#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.18:11:14.24#ibcon#*before write, iclass 10, count 0 2006.173.18:11:14.24#ibcon#enter sib2, iclass 10, count 0 2006.173.18:11:14.24#ibcon#flushed, iclass 10, count 0 2006.173.18:11:14.24#ibcon#about to write, iclass 10, count 0 2006.173.18:11:14.24#ibcon#wrote, iclass 10, count 0 2006.173.18:11:14.24#ibcon#about to read 3, iclass 10, count 0 2006.173.18:11:14.28#ibcon#read 3, iclass 10, count 0 2006.173.18:11:14.28#ibcon#about to read 4, iclass 10, count 0 2006.173.18:11:14.28#ibcon#read 4, iclass 10, count 0 2006.173.18:11:14.28#ibcon#about to read 5, iclass 10, count 0 2006.173.18:11:14.28#ibcon#read 5, iclass 10, count 0 2006.173.18:11:14.28#ibcon#about to read 6, iclass 10, count 0 2006.173.18:11:14.28#ibcon#read 6, iclass 10, count 0 2006.173.18:11:14.28#ibcon#end of sib2, iclass 10, count 0 2006.173.18:11:14.28#ibcon#*after write, iclass 10, count 0 2006.173.18:11:14.28#ibcon#*before return 0, iclass 10, count 0 2006.173.18:11:14.28#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.18:11:14.28#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.18:11:14.28#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.18:11:14.28#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.18:11:14.28$vck44/va=4,6 2006.173.18:11:14.28#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.18:11:14.28#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.18:11:14.28#ibcon#ireg 11 cls_cnt 2 2006.173.18:11:14.28#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.18:11:14.34#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.18:11:14.34#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.18:11:14.34#ibcon#enter wrdev, iclass 12, count 2 2006.173.18:11:14.34#ibcon#first serial, iclass 12, count 2 2006.173.18:11:14.34#ibcon#enter sib2, iclass 12, count 2 2006.173.18:11:14.34#ibcon#flushed, iclass 12, count 2 2006.173.18:11:14.34#ibcon#about to write, iclass 12, count 2 2006.173.18:11:14.34#ibcon#wrote, iclass 12, count 2 2006.173.18:11:14.34#ibcon#about to read 3, iclass 12, count 2 2006.173.18:11:14.36#ibcon#read 3, iclass 12, count 2 2006.173.18:11:14.36#ibcon#about to read 4, iclass 12, count 2 2006.173.18:11:14.36#ibcon#read 4, iclass 12, count 2 2006.173.18:11:14.36#ibcon#about to read 5, iclass 12, count 2 2006.173.18:11:14.36#ibcon#read 5, iclass 12, count 2 2006.173.18:11:14.36#ibcon#about to read 6, iclass 12, count 2 2006.173.18:11:14.36#ibcon#read 6, iclass 12, count 2 2006.173.18:11:14.36#ibcon#end of sib2, iclass 12, count 2 2006.173.18:11:14.36#ibcon#*mode == 0, iclass 12, count 2 2006.173.18:11:14.36#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.18:11:14.36#ibcon#[25=AT04-06\r\n] 2006.173.18:11:14.36#ibcon#*before write, iclass 12, count 2 2006.173.18:11:14.36#ibcon#enter sib2, iclass 12, count 2 2006.173.18:11:14.36#ibcon#flushed, iclass 12, count 2 2006.173.18:11:14.36#ibcon#about to write, iclass 12, count 2 2006.173.18:11:14.36#ibcon#wrote, iclass 12, count 2 2006.173.18:11:14.36#ibcon#about to read 3, iclass 12, count 2 2006.173.18:11:14.39#ibcon#read 3, iclass 12, count 2 2006.173.18:11:14.39#ibcon#about to read 4, iclass 12, count 2 2006.173.18:11:14.39#ibcon#read 4, iclass 12, count 2 2006.173.18:11:14.39#ibcon#about to read 5, iclass 12, count 2 2006.173.18:11:14.39#ibcon#read 5, iclass 12, count 2 2006.173.18:11:14.39#ibcon#about to read 6, iclass 12, count 2 2006.173.18:11:14.39#ibcon#read 6, iclass 12, count 2 2006.173.18:11:14.39#ibcon#end of sib2, iclass 12, count 2 2006.173.18:11:14.39#ibcon#*after write, iclass 12, count 2 2006.173.18:11:14.39#ibcon#*before return 0, iclass 12, count 2 2006.173.18:11:14.39#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.18:11:14.39#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.18:11:14.39#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.18:11:14.39#ibcon#ireg 7 cls_cnt 0 2006.173.18:11:14.39#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.18:11:14.51#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.18:11:14.51#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.18:11:14.51#ibcon#enter wrdev, iclass 12, count 0 2006.173.18:11:14.51#ibcon#first serial, iclass 12, count 0 2006.173.18:11:14.51#ibcon#enter sib2, iclass 12, count 0 2006.173.18:11:14.51#ibcon#flushed, iclass 12, count 0 2006.173.18:11:14.51#ibcon#about to write, iclass 12, count 0 2006.173.18:11:14.51#ibcon#wrote, iclass 12, count 0 2006.173.18:11:14.51#ibcon#about to read 3, iclass 12, count 0 2006.173.18:11:14.53#ibcon#read 3, iclass 12, count 0 2006.173.18:11:14.53#ibcon#about to read 4, iclass 12, count 0 2006.173.18:11:14.53#ibcon#read 4, iclass 12, count 0 2006.173.18:11:14.53#ibcon#about to read 5, iclass 12, count 0 2006.173.18:11:14.53#ibcon#read 5, iclass 12, count 0 2006.173.18:11:14.53#ibcon#about to read 6, iclass 12, count 0 2006.173.18:11:14.53#ibcon#read 6, iclass 12, count 0 2006.173.18:11:14.53#ibcon#end of sib2, iclass 12, count 0 2006.173.18:11:14.53#ibcon#*mode == 0, iclass 12, count 0 2006.173.18:11:14.53#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.18:11:14.53#ibcon#[25=USB\r\n] 2006.173.18:11:14.53#ibcon#*before write, iclass 12, count 0 2006.173.18:11:14.53#ibcon#enter sib2, iclass 12, count 0 2006.173.18:11:14.53#ibcon#flushed, iclass 12, count 0 2006.173.18:11:14.53#ibcon#about to write, iclass 12, count 0 2006.173.18:11:14.53#ibcon#wrote, iclass 12, count 0 2006.173.18:11:14.53#ibcon#about to read 3, iclass 12, count 0 2006.173.18:11:14.56#ibcon#read 3, iclass 12, count 0 2006.173.18:11:14.56#ibcon#about to read 4, iclass 12, count 0 2006.173.18:11:14.56#ibcon#read 4, iclass 12, count 0 2006.173.18:11:14.56#ibcon#about to read 5, iclass 12, count 0 2006.173.18:11:14.56#ibcon#read 5, iclass 12, count 0 2006.173.18:11:14.56#ibcon#about to read 6, iclass 12, count 0 2006.173.18:11:14.56#ibcon#read 6, iclass 12, count 0 2006.173.18:11:14.56#ibcon#end of sib2, iclass 12, count 0 2006.173.18:11:14.56#ibcon#*after write, iclass 12, count 0 2006.173.18:11:14.56#ibcon#*before return 0, iclass 12, count 0 2006.173.18:11:14.56#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.18:11:14.56#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.18:11:14.56#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.18:11:14.56#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.18:11:14.56$vck44/valo=5,734.99 2006.173.18:11:14.56#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.18:11:14.56#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.18:11:14.56#ibcon#ireg 17 cls_cnt 0 2006.173.18:11:14.56#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.18:11:14.56#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.18:11:14.56#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.18:11:14.56#ibcon#enter wrdev, iclass 14, count 0 2006.173.18:11:14.56#ibcon#first serial, iclass 14, count 0 2006.173.18:11:14.56#ibcon#enter sib2, iclass 14, count 0 2006.173.18:11:14.56#ibcon#flushed, iclass 14, count 0 2006.173.18:11:14.56#ibcon#about to write, iclass 14, count 0 2006.173.18:11:14.56#ibcon#wrote, iclass 14, count 0 2006.173.18:11:14.56#ibcon#about to read 3, iclass 14, count 0 2006.173.18:11:14.58#ibcon#read 3, iclass 14, count 0 2006.173.18:11:14.58#ibcon#about to read 4, iclass 14, count 0 2006.173.18:11:14.58#ibcon#read 4, iclass 14, count 0 2006.173.18:11:14.58#ibcon#about to read 5, iclass 14, count 0 2006.173.18:11:14.58#ibcon#read 5, iclass 14, count 0 2006.173.18:11:14.58#ibcon#about to read 6, iclass 14, count 0 2006.173.18:11:14.58#ibcon#read 6, iclass 14, count 0 2006.173.18:11:14.58#ibcon#end of sib2, iclass 14, count 0 2006.173.18:11:14.58#ibcon#*mode == 0, iclass 14, count 0 2006.173.18:11:14.58#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.18:11:14.58#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.18:11:14.58#ibcon#*before write, iclass 14, count 0 2006.173.18:11:14.58#ibcon#enter sib2, iclass 14, count 0 2006.173.18:11:14.58#ibcon#flushed, iclass 14, count 0 2006.173.18:11:14.58#ibcon#about to write, iclass 14, count 0 2006.173.18:11:14.58#ibcon#wrote, iclass 14, count 0 2006.173.18:11:14.58#ibcon#about to read 3, iclass 14, count 0 2006.173.18:11:14.62#ibcon#read 3, iclass 14, count 0 2006.173.18:11:14.62#ibcon#about to read 4, iclass 14, count 0 2006.173.18:11:14.62#ibcon#read 4, iclass 14, count 0 2006.173.18:11:14.62#ibcon#about to read 5, iclass 14, count 0 2006.173.18:11:14.62#ibcon#read 5, iclass 14, count 0 2006.173.18:11:14.62#ibcon#about to read 6, iclass 14, count 0 2006.173.18:11:14.62#ibcon#read 6, iclass 14, count 0 2006.173.18:11:14.62#ibcon#end of sib2, iclass 14, count 0 2006.173.18:11:14.62#ibcon#*after write, iclass 14, count 0 2006.173.18:11:14.62#ibcon#*before return 0, iclass 14, count 0 2006.173.18:11:14.62#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.18:11:14.62#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.18:11:14.62#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.18:11:14.62#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.18:11:14.62$vck44/va=5,4 2006.173.18:11:14.62#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.18:11:14.62#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.18:11:14.62#ibcon#ireg 11 cls_cnt 2 2006.173.18:11:14.62#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.18:11:14.68#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.18:11:14.68#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.18:11:14.68#ibcon#enter wrdev, iclass 16, count 2 2006.173.18:11:14.68#ibcon#first serial, iclass 16, count 2 2006.173.18:11:14.68#ibcon#enter sib2, iclass 16, count 2 2006.173.18:11:14.68#ibcon#flushed, iclass 16, count 2 2006.173.18:11:14.68#ibcon#about to write, iclass 16, count 2 2006.173.18:11:14.68#ibcon#wrote, iclass 16, count 2 2006.173.18:11:14.68#ibcon#about to read 3, iclass 16, count 2 2006.173.18:11:14.70#ibcon#read 3, iclass 16, count 2 2006.173.18:11:14.70#ibcon#about to read 4, iclass 16, count 2 2006.173.18:11:14.70#ibcon#read 4, iclass 16, count 2 2006.173.18:11:14.70#ibcon#about to read 5, iclass 16, count 2 2006.173.18:11:14.70#ibcon#read 5, iclass 16, count 2 2006.173.18:11:14.70#ibcon#about to read 6, iclass 16, count 2 2006.173.18:11:14.70#ibcon#read 6, iclass 16, count 2 2006.173.18:11:14.70#ibcon#end of sib2, iclass 16, count 2 2006.173.18:11:14.70#ibcon#*mode == 0, iclass 16, count 2 2006.173.18:11:14.70#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.18:11:14.70#ibcon#[25=AT05-04\r\n] 2006.173.18:11:14.70#ibcon#*before write, iclass 16, count 2 2006.173.18:11:14.70#ibcon#enter sib2, iclass 16, count 2 2006.173.18:11:14.70#ibcon#flushed, iclass 16, count 2 2006.173.18:11:14.70#ibcon#about to write, iclass 16, count 2 2006.173.18:11:14.70#ibcon#wrote, iclass 16, count 2 2006.173.18:11:14.70#ibcon#about to read 3, iclass 16, count 2 2006.173.18:11:14.73#ibcon#read 3, iclass 16, count 2 2006.173.18:11:14.73#ibcon#about to read 4, iclass 16, count 2 2006.173.18:11:14.73#ibcon#read 4, iclass 16, count 2 2006.173.18:11:14.73#ibcon#about to read 5, iclass 16, count 2 2006.173.18:11:14.73#ibcon#read 5, iclass 16, count 2 2006.173.18:11:14.73#ibcon#about to read 6, iclass 16, count 2 2006.173.18:11:14.73#ibcon#read 6, iclass 16, count 2 2006.173.18:11:14.73#ibcon#end of sib2, iclass 16, count 2 2006.173.18:11:14.73#ibcon#*after write, iclass 16, count 2 2006.173.18:11:14.73#ibcon#*before return 0, iclass 16, count 2 2006.173.18:11:14.73#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.18:11:14.73#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.18:11:14.73#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.18:11:14.73#ibcon#ireg 7 cls_cnt 0 2006.173.18:11:14.73#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.18:11:14.85#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.18:11:14.85#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.18:11:14.85#ibcon#enter wrdev, iclass 16, count 0 2006.173.18:11:14.85#ibcon#first serial, iclass 16, count 0 2006.173.18:11:14.85#ibcon#enter sib2, iclass 16, count 0 2006.173.18:11:14.85#ibcon#flushed, iclass 16, count 0 2006.173.18:11:14.85#ibcon#about to write, iclass 16, count 0 2006.173.18:11:14.85#ibcon#wrote, iclass 16, count 0 2006.173.18:11:14.85#ibcon#about to read 3, iclass 16, count 0 2006.173.18:11:14.87#ibcon#read 3, iclass 16, count 0 2006.173.18:11:14.87#ibcon#about to read 4, iclass 16, count 0 2006.173.18:11:14.87#ibcon#read 4, iclass 16, count 0 2006.173.18:11:14.87#ibcon#about to read 5, iclass 16, count 0 2006.173.18:11:14.87#ibcon#read 5, iclass 16, count 0 2006.173.18:11:14.87#ibcon#about to read 6, iclass 16, count 0 2006.173.18:11:14.87#ibcon#read 6, iclass 16, count 0 2006.173.18:11:14.87#ibcon#end of sib2, iclass 16, count 0 2006.173.18:11:14.87#ibcon#*mode == 0, iclass 16, count 0 2006.173.18:11:14.87#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.18:11:14.87#ibcon#[25=USB\r\n] 2006.173.18:11:14.87#ibcon#*before write, iclass 16, count 0 2006.173.18:11:14.87#ibcon#enter sib2, iclass 16, count 0 2006.173.18:11:14.87#ibcon#flushed, iclass 16, count 0 2006.173.18:11:14.87#ibcon#about to write, iclass 16, count 0 2006.173.18:11:14.87#ibcon#wrote, iclass 16, count 0 2006.173.18:11:14.87#ibcon#about to read 3, iclass 16, count 0 2006.173.18:11:14.90#ibcon#read 3, iclass 16, count 0 2006.173.18:11:14.90#ibcon#about to read 4, iclass 16, count 0 2006.173.18:11:14.90#ibcon#read 4, iclass 16, count 0 2006.173.18:11:14.90#ibcon#about to read 5, iclass 16, count 0 2006.173.18:11:14.90#ibcon#read 5, iclass 16, count 0 2006.173.18:11:14.90#ibcon#about to read 6, iclass 16, count 0 2006.173.18:11:14.90#ibcon#read 6, iclass 16, count 0 2006.173.18:11:14.90#ibcon#end of sib2, iclass 16, count 0 2006.173.18:11:14.90#ibcon#*after write, iclass 16, count 0 2006.173.18:11:14.90#ibcon#*before return 0, iclass 16, count 0 2006.173.18:11:14.90#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.18:11:14.90#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.18:11:14.90#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.18:11:14.90#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.18:11:14.90$vck44/valo=6,814.99 2006.173.18:11:14.90#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.18:11:14.90#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.18:11:14.90#ibcon#ireg 17 cls_cnt 0 2006.173.18:11:14.90#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.18:11:14.90#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.18:11:14.90#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.18:11:14.90#ibcon#enter wrdev, iclass 18, count 0 2006.173.18:11:14.90#ibcon#first serial, iclass 18, count 0 2006.173.18:11:14.90#ibcon#enter sib2, iclass 18, count 0 2006.173.18:11:14.90#ibcon#flushed, iclass 18, count 0 2006.173.18:11:14.90#ibcon#about to write, iclass 18, count 0 2006.173.18:11:14.90#ibcon#wrote, iclass 18, count 0 2006.173.18:11:14.90#ibcon#about to read 3, iclass 18, count 0 2006.173.18:11:14.92#ibcon#read 3, iclass 18, count 0 2006.173.18:11:14.92#ibcon#about to read 4, iclass 18, count 0 2006.173.18:11:14.92#ibcon#read 4, iclass 18, count 0 2006.173.18:11:14.92#ibcon#about to read 5, iclass 18, count 0 2006.173.18:11:14.92#ibcon#read 5, iclass 18, count 0 2006.173.18:11:14.92#ibcon#about to read 6, iclass 18, count 0 2006.173.18:11:14.92#ibcon#read 6, iclass 18, count 0 2006.173.18:11:14.92#ibcon#end of sib2, iclass 18, count 0 2006.173.18:11:14.92#ibcon#*mode == 0, iclass 18, count 0 2006.173.18:11:14.92#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.18:11:14.92#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.18:11:14.92#ibcon#*before write, iclass 18, count 0 2006.173.18:11:14.92#ibcon#enter sib2, iclass 18, count 0 2006.173.18:11:14.92#ibcon#flushed, iclass 18, count 0 2006.173.18:11:14.92#ibcon#about to write, iclass 18, count 0 2006.173.18:11:14.92#ibcon#wrote, iclass 18, count 0 2006.173.18:11:14.92#ibcon#about to read 3, iclass 18, count 0 2006.173.18:11:14.96#ibcon#read 3, iclass 18, count 0 2006.173.18:11:14.96#ibcon#about to read 4, iclass 18, count 0 2006.173.18:11:14.96#ibcon#read 4, iclass 18, count 0 2006.173.18:11:14.96#ibcon#about to read 5, iclass 18, count 0 2006.173.18:11:14.96#ibcon#read 5, iclass 18, count 0 2006.173.18:11:14.96#ibcon#about to read 6, iclass 18, count 0 2006.173.18:11:14.96#ibcon#read 6, iclass 18, count 0 2006.173.18:11:14.96#ibcon#end of sib2, iclass 18, count 0 2006.173.18:11:14.96#ibcon#*after write, iclass 18, count 0 2006.173.18:11:14.96#ibcon#*before return 0, iclass 18, count 0 2006.173.18:11:14.96#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.18:11:14.96#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.18:11:14.96#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.18:11:14.96#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.18:11:14.96$vck44/va=6,3 2006.173.18:11:14.96#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.18:11:14.96#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.18:11:14.96#ibcon#ireg 11 cls_cnt 2 2006.173.18:11:14.96#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.18:11:15.02#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.18:11:15.02#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.18:11:15.02#ibcon#enter wrdev, iclass 20, count 2 2006.173.18:11:15.02#ibcon#first serial, iclass 20, count 2 2006.173.18:11:15.02#ibcon#enter sib2, iclass 20, count 2 2006.173.18:11:15.02#ibcon#flushed, iclass 20, count 2 2006.173.18:11:15.02#ibcon#about to write, iclass 20, count 2 2006.173.18:11:15.02#ibcon#wrote, iclass 20, count 2 2006.173.18:11:15.02#ibcon#about to read 3, iclass 20, count 2 2006.173.18:11:15.04#ibcon#read 3, iclass 20, count 2 2006.173.18:11:15.04#ibcon#about to read 4, iclass 20, count 2 2006.173.18:11:15.04#ibcon#read 4, iclass 20, count 2 2006.173.18:11:15.04#ibcon#about to read 5, iclass 20, count 2 2006.173.18:11:15.04#ibcon#read 5, iclass 20, count 2 2006.173.18:11:15.04#ibcon#about to read 6, iclass 20, count 2 2006.173.18:11:15.04#ibcon#read 6, iclass 20, count 2 2006.173.18:11:15.04#ibcon#end of sib2, iclass 20, count 2 2006.173.18:11:15.04#ibcon#*mode == 0, iclass 20, count 2 2006.173.18:11:15.04#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.18:11:15.04#ibcon#[25=AT06-03\r\n] 2006.173.18:11:15.04#ibcon#*before write, iclass 20, count 2 2006.173.18:11:15.04#ibcon#enter sib2, iclass 20, count 2 2006.173.18:11:15.04#ibcon#flushed, iclass 20, count 2 2006.173.18:11:15.04#ibcon#about to write, iclass 20, count 2 2006.173.18:11:15.04#ibcon#wrote, iclass 20, count 2 2006.173.18:11:15.04#ibcon#about to read 3, iclass 20, count 2 2006.173.18:11:15.07#ibcon#read 3, iclass 20, count 2 2006.173.18:11:15.07#ibcon#about to read 4, iclass 20, count 2 2006.173.18:11:15.07#ibcon#read 4, iclass 20, count 2 2006.173.18:11:15.07#ibcon#about to read 5, iclass 20, count 2 2006.173.18:11:15.07#ibcon#read 5, iclass 20, count 2 2006.173.18:11:15.07#ibcon#about to read 6, iclass 20, count 2 2006.173.18:11:15.07#ibcon#read 6, iclass 20, count 2 2006.173.18:11:15.07#ibcon#end of sib2, iclass 20, count 2 2006.173.18:11:15.07#ibcon#*after write, iclass 20, count 2 2006.173.18:11:15.07#ibcon#*before return 0, iclass 20, count 2 2006.173.18:11:15.07#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.18:11:15.07#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.18:11:15.07#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.18:11:15.07#ibcon#ireg 7 cls_cnt 0 2006.173.18:11:15.07#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.18:11:15.19#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.18:11:15.19#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.18:11:15.19#ibcon#enter wrdev, iclass 20, count 0 2006.173.18:11:15.19#ibcon#first serial, iclass 20, count 0 2006.173.18:11:15.19#ibcon#enter sib2, iclass 20, count 0 2006.173.18:11:15.19#ibcon#flushed, iclass 20, count 0 2006.173.18:11:15.19#ibcon#about to write, iclass 20, count 0 2006.173.18:11:15.19#ibcon#wrote, iclass 20, count 0 2006.173.18:11:15.19#ibcon#about to read 3, iclass 20, count 0 2006.173.18:11:15.21#ibcon#read 3, iclass 20, count 0 2006.173.18:11:15.21#ibcon#about to read 4, iclass 20, count 0 2006.173.18:11:15.21#ibcon#read 4, iclass 20, count 0 2006.173.18:11:15.21#ibcon#about to read 5, iclass 20, count 0 2006.173.18:11:15.21#ibcon#read 5, iclass 20, count 0 2006.173.18:11:15.21#ibcon#about to read 6, iclass 20, count 0 2006.173.18:11:15.21#ibcon#read 6, iclass 20, count 0 2006.173.18:11:15.21#ibcon#end of sib2, iclass 20, count 0 2006.173.18:11:15.21#ibcon#*mode == 0, iclass 20, count 0 2006.173.18:11:15.21#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.18:11:15.21#ibcon#[25=USB\r\n] 2006.173.18:11:15.21#ibcon#*before write, iclass 20, count 0 2006.173.18:11:15.21#ibcon#enter sib2, iclass 20, count 0 2006.173.18:11:15.21#ibcon#flushed, iclass 20, count 0 2006.173.18:11:15.21#ibcon#about to write, iclass 20, count 0 2006.173.18:11:15.21#ibcon#wrote, iclass 20, count 0 2006.173.18:11:15.21#ibcon#about to read 3, iclass 20, count 0 2006.173.18:11:15.24#ibcon#read 3, iclass 20, count 0 2006.173.18:11:15.24#ibcon#about to read 4, iclass 20, count 0 2006.173.18:11:15.24#ibcon#read 4, iclass 20, count 0 2006.173.18:11:15.24#ibcon#about to read 5, iclass 20, count 0 2006.173.18:11:15.24#ibcon#read 5, iclass 20, count 0 2006.173.18:11:15.24#ibcon#about to read 6, iclass 20, count 0 2006.173.18:11:15.24#ibcon#read 6, iclass 20, count 0 2006.173.18:11:15.24#ibcon#end of sib2, iclass 20, count 0 2006.173.18:11:15.24#ibcon#*after write, iclass 20, count 0 2006.173.18:11:15.24#ibcon#*before return 0, iclass 20, count 0 2006.173.18:11:15.24#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.18:11:15.24#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.18:11:15.24#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.18:11:15.24#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.18:11:15.24$vck44/valo=7,864.99 2006.173.18:11:15.24#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.18:11:15.24#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.18:11:15.24#ibcon#ireg 17 cls_cnt 0 2006.173.18:11:15.24#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.18:11:15.24#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.18:11:15.24#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.18:11:15.24#ibcon#enter wrdev, iclass 22, count 0 2006.173.18:11:15.24#ibcon#first serial, iclass 22, count 0 2006.173.18:11:15.24#ibcon#enter sib2, iclass 22, count 0 2006.173.18:11:15.24#ibcon#flushed, iclass 22, count 0 2006.173.18:11:15.24#ibcon#about to write, iclass 22, count 0 2006.173.18:11:15.24#ibcon#wrote, iclass 22, count 0 2006.173.18:11:15.24#ibcon#about to read 3, iclass 22, count 0 2006.173.18:11:15.26#ibcon#read 3, iclass 22, count 0 2006.173.18:11:15.26#ibcon#about to read 4, iclass 22, count 0 2006.173.18:11:15.26#ibcon#read 4, iclass 22, count 0 2006.173.18:11:15.26#ibcon#about to read 5, iclass 22, count 0 2006.173.18:11:15.26#ibcon#read 5, iclass 22, count 0 2006.173.18:11:15.26#ibcon#about to read 6, iclass 22, count 0 2006.173.18:11:15.26#ibcon#read 6, iclass 22, count 0 2006.173.18:11:15.26#ibcon#end of sib2, iclass 22, count 0 2006.173.18:11:15.26#ibcon#*mode == 0, iclass 22, count 0 2006.173.18:11:15.26#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.18:11:15.26#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.18:11:15.26#ibcon#*before write, iclass 22, count 0 2006.173.18:11:15.26#ibcon#enter sib2, iclass 22, count 0 2006.173.18:11:15.26#ibcon#flushed, iclass 22, count 0 2006.173.18:11:15.26#ibcon#about to write, iclass 22, count 0 2006.173.18:11:15.26#ibcon#wrote, iclass 22, count 0 2006.173.18:11:15.26#ibcon#about to read 3, iclass 22, count 0 2006.173.18:11:15.30#ibcon#read 3, iclass 22, count 0 2006.173.18:11:15.30#ibcon#about to read 4, iclass 22, count 0 2006.173.18:11:15.30#ibcon#read 4, iclass 22, count 0 2006.173.18:11:15.30#ibcon#about to read 5, iclass 22, count 0 2006.173.18:11:15.30#ibcon#read 5, iclass 22, count 0 2006.173.18:11:15.30#ibcon#about to read 6, iclass 22, count 0 2006.173.18:11:15.30#ibcon#read 6, iclass 22, count 0 2006.173.18:11:15.30#ibcon#end of sib2, iclass 22, count 0 2006.173.18:11:15.30#ibcon#*after write, iclass 22, count 0 2006.173.18:11:15.30#ibcon#*before return 0, iclass 22, count 0 2006.173.18:11:15.30#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.18:11:15.30#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.18:11:15.30#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.18:11:15.30#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.18:11:15.30$vck44/va=7,4 2006.173.18:11:15.30#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.18:11:15.30#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.18:11:15.30#ibcon#ireg 11 cls_cnt 2 2006.173.18:11:15.30#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.18:11:15.36#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.18:11:15.36#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.18:11:15.36#ibcon#enter wrdev, iclass 24, count 2 2006.173.18:11:15.36#ibcon#first serial, iclass 24, count 2 2006.173.18:11:15.36#ibcon#enter sib2, iclass 24, count 2 2006.173.18:11:15.36#ibcon#flushed, iclass 24, count 2 2006.173.18:11:15.36#ibcon#about to write, iclass 24, count 2 2006.173.18:11:15.36#ibcon#wrote, iclass 24, count 2 2006.173.18:11:15.36#ibcon#about to read 3, iclass 24, count 2 2006.173.18:11:15.38#ibcon#read 3, iclass 24, count 2 2006.173.18:11:15.38#ibcon#about to read 4, iclass 24, count 2 2006.173.18:11:15.38#ibcon#read 4, iclass 24, count 2 2006.173.18:11:15.38#ibcon#about to read 5, iclass 24, count 2 2006.173.18:11:15.38#ibcon#read 5, iclass 24, count 2 2006.173.18:11:15.38#ibcon#about to read 6, iclass 24, count 2 2006.173.18:11:15.38#ibcon#read 6, iclass 24, count 2 2006.173.18:11:15.38#ibcon#end of sib2, iclass 24, count 2 2006.173.18:11:15.38#ibcon#*mode == 0, iclass 24, count 2 2006.173.18:11:15.38#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.18:11:15.38#ibcon#[25=AT07-04\r\n] 2006.173.18:11:15.38#ibcon#*before write, iclass 24, count 2 2006.173.18:11:15.38#ibcon#enter sib2, iclass 24, count 2 2006.173.18:11:15.38#ibcon#flushed, iclass 24, count 2 2006.173.18:11:15.38#ibcon#about to write, iclass 24, count 2 2006.173.18:11:15.38#ibcon#wrote, iclass 24, count 2 2006.173.18:11:15.38#ibcon#about to read 3, iclass 24, count 2 2006.173.18:11:15.41#ibcon#read 3, iclass 24, count 2 2006.173.18:11:15.41#ibcon#about to read 4, iclass 24, count 2 2006.173.18:11:15.41#ibcon#read 4, iclass 24, count 2 2006.173.18:11:15.41#ibcon#about to read 5, iclass 24, count 2 2006.173.18:11:15.41#ibcon#read 5, iclass 24, count 2 2006.173.18:11:15.41#ibcon#about to read 6, iclass 24, count 2 2006.173.18:11:15.41#ibcon#read 6, iclass 24, count 2 2006.173.18:11:15.41#ibcon#end of sib2, iclass 24, count 2 2006.173.18:11:15.41#ibcon#*after write, iclass 24, count 2 2006.173.18:11:15.41#ibcon#*before return 0, iclass 24, count 2 2006.173.18:11:15.41#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.18:11:15.41#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.18:11:15.41#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.18:11:15.41#ibcon#ireg 7 cls_cnt 0 2006.173.18:11:15.41#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.18:11:15.53#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.18:11:15.53#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.18:11:15.53#ibcon#enter wrdev, iclass 24, count 0 2006.173.18:11:15.53#ibcon#first serial, iclass 24, count 0 2006.173.18:11:15.53#ibcon#enter sib2, iclass 24, count 0 2006.173.18:11:15.53#ibcon#flushed, iclass 24, count 0 2006.173.18:11:15.53#ibcon#about to write, iclass 24, count 0 2006.173.18:11:15.53#ibcon#wrote, iclass 24, count 0 2006.173.18:11:15.53#ibcon#about to read 3, iclass 24, count 0 2006.173.18:11:15.55#ibcon#read 3, iclass 24, count 0 2006.173.18:11:15.55#ibcon#about to read 4, iclass 24, count 0 2006.173.18:11:15.55#ibcon#read 4, iclass 24, count 0 2006.173.18:11:15.55#ibcon#about to read 5, iclass 24, count 0 2006.173.18:11:15.55#ibcon#read 5, iclass 24, count 0 2006.173.18:11:15.55#ibcon#about to read 6, iclass 24, count 0 2006.173.18:11:15.55#ibcon#read 6, iclass 24, count 0 2006.173.18:11:15.55#ibcon#end of sib2, iclass 24, count 0 2006.173.18:11:15.55#ibcon#*mode == 0, iclass 24, count 0 2006.173.18:11:15.55#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.18:11:15.55#ibcon#[25=USB\r\n] 2006.173.18:11:15.55#ibcon#*before write, iclass 24, count 0 2006.173.18:11:15.55#ibcon#enter sib2, iclass 24, count 0 2006.173.18:11:15.55#ibcon#flushed, iclass 24, count 0 2006.173.18:11:15.55#ibcon#about to write, iclass 24, count 0 2006.173.18:11:15.55#ibcon#wrote, iclass 24, count 0 2006.173.18:11:15.55#ibcon#about to read 3, iclass 24, count 0 2006.173.18:11:15.58#ibcon#read 3, iclass 24, count 0 2006.173.18:11:15.58#ibcon#about to read 4, iclass 24, count 0 2006.173.18:11:15.58#ibcon#read 4, iclass 24, count 0 2006.173.18:11:15.58#ibcon#about to read 5, iclass 24, count 0 2006.173.18:11:15.58#ibcon#read 5, iclass 24, count 0 2006.173.18:11:15.58#ibcon#about to read 6, iclass 24, count 0 2006.173.18:11:15.58#ibcon#read 6, iclass 24, count 0 2006.173.18:11:15.58#ibcon#end of sib2, iclass 24, count 0 2006.173.18:11:15.58#ibcon#*after write, iclass 24, count 0 2006.173.18:11:15.58#ibcon#*before return 0, iclass 24, count 0 2006.173.18:11:15.58#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.18:11:15.58#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.18:11:15.58#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.18:11:15.58#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.18:11:15.58$vck44/valo=8,884.99 2006.173.18:11:15.58#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.18:11:15.58#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.18:11:15.58#ibcon#ireg 17 cls_cnt 0 2006.173.18:11:15.58#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.18:11:15.58#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.18:11:15.58#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.18:11:15.58#ibcon#enter wrdev, iclass 26, count 0 2006.173.18:11:15.58#ibcon#first serial, iclass 26, count 0 2006.173.18:11:15.58#ibcon#enter sib2, iclass 26, count 0 2006.173.18:11:15.58#ibcon#flushed, iclass 26, count 0 2006.173.18:11:15.58#ibcon#about to write, iclass 26, count 0 2006.173.18:11:15.58#ibcon#wrote, iclass 26, count 0 2006.173.18:11:15.58#ibcon#about to read 3, iclass 26, count 0 2006.173.18:11:15.60#ibcon#read 3, iclass 26, count 0 2006.173.18:11:15.60#ibcon#about to read 4, iclass 26, count 0 2006.173.18:11:15.60#ibcon#read 4, iclass 26, count 0 2006.173.18:11:15.60#ibcon#about to read 5, iclass 26, count 0 2006.173.18:11:15.60#ibcon#read 5, iclass 26, count 0 2006.173.18:11:15.60#ibcon#about to read 6, iclass 26, count 0 2006.173.18:11:15.60#ibcon#read 6, iclass 26, count 0 2006.173.18:11:15.60#ibcon#end of sib2, iclass 26, count 0 2006.173.18:11:15.60#ibcon#*mode == 0, iclass 26, count 0 2006.173.18:11:15.60#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.18:11:15.60#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.18:11:15.60#ibcon#*before write, iclass 26, count 0 2006.173.18:11:15.60#ibcon#enter sib2, iclass 26, count 0 2006.173.18:11:15.60#ibcon#flushed, iclass 26, count 0 2006.173.18:11:15.60#ibcon#about to write, iclass 26, count 0 2006.173.18:11:15.60#ibcon#wrote, iclass 26, count 0 2006.173.18:11:15.60#ibcon#about to read 3, iclass 26, count 0 2006.173.18:11:15.64#ibcon#read 3, iclass 26, count 0 2006.173.18:11:15.64#ibcon#about to read 4, iclass 26, count 0 2006.173.18:11:15.64#ibcon#read 4, iclass 26, count 0 2006.173.18:11:15.64#ibcon#about to read 5, iclass 26, count 0 2006.173.18:11:15.64#ibcon#read 5, iclass 26, count 0 2006.173.18:11:15.64#ibcon#about to read 6, iclass 26, count 0 2006.173.18:11:15.64#ibcon#read 6, iclass 26, count 0 2006.173.18:11:15.64#ibcon#end of sib2, iclass 26, count 0 2006.173.18:11:15.64#ibcon#*after write, iclass 26, count 0 2006.173.18:11:15.64#ibcon#*before return 0, iclass 26, count 0 2006.173.18:11:15.64#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.18:11:15.64#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.18:11:15.64#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.18:11:15.64#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.18:11:15.64$vck44/va=8,4 2006.173.18:11:15.64#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.18:11:15.64#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.18:11:15.64#ibcon#ireg 11 cls_cnt 2 2006.173.18:11:15.64#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.18:11:15.70#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.18:11:15.70#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.18:11:15.70#ibcon#enter wrdev, iclass 28, count 2 2006.173.18:11:15.70#ibcon#first serial, iclass 28, count 2 2006.173.18:11:15.70#ibcon#enter sib2, iclass 28, count 2 2006.173.18:11:15.70#ibcon#flushed, iclass 28, count 2 2006.173.18:11:15.70#ibcon#about to write, iclass 28, count 2 2006.173.18:11:15.70#ibcon#wrote, iclass 28, count 2 2006.173.18:11:15.70#ibcon#about to read 3, iclass 28, count 2 2006.173.18:11:15.72#ibcon#read 3, iclass 28, count 2 2006.173.18:11:15.72#ibcon#about to read 4, iclass 28, count 2 2006.173.18:11:15.72#ibcon#read 4, iclass 28, count 2 2006.173.18:11:15.72#ibcon#about to read 5, iclass 28, count 2 2006.173.18:11:15.72#ibcon#read 5, iclass 28, count 2 2006.173.18:11:15.72#ibcon#about to read 6, iclass 28, count 2 2006.173.18:11:15.72#ibcon#read 6, iclass 28, count 2 2006.173.18:11:15.72#ibcon#end of sib2, iclass 28, count 2 2006.173.18:11:15.72#ibcon#*mode == 0, iclass 28, count 2 2006.173.18:11:15.72#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.18:11:15.72#ibcon#[25=AT08-04\r\n] 2006.173.18:11:15.72#ibcon#*before write, iclass 28, count 2 2006.173.18:11:15.72#ibcon#enter sib2, iclass 28, count 2 2006.173.18:11:15.72#ibcon#flushed, iclass 28, count 2 2006.173.18:11:15.72#ibcon#about to write, iclass 28, count 2 2006.173.18:11:15.72#ibcon#wrote, iclass 28, count 2 2006.173.18:11:15.72#ibcon#about to read 3, iclass 28, count 2 2006.173.18:11:15.75#ibcon#read 3, iclass 28, count 2 2006.173.18:11:15.75#ibcon#about to read 4, iclass 28, count 2 2006.173.18:11:15.75#ibcon#read 4, iclass 28, count 2 2006.173.18:11:15.75#ibcon#about to read 5, iclass 28, count 2 2006.173.18:11:15.75#ibcon#read 5, iclass 28, count 2 2006.173.18:11:15.75#ibcon#about to read 6, iclass 28, count 2 2006.173.18:11:15.75#ibcon#read 6, iclass 28, count 2 2006.173.18:11:15.75#ibcon#end of sib2, iclass 28, count 2 2006.173.18:11:15.75#ibcon#*after write, iclass 28, count 2 2006.173.18:11:15.75#ibcon#*before return 0, iclass 28, count 2 2006.173.18:11:15.75#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.18:11:15.75#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.18:11:15.75#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.18:11:15.75#ibcon#ireg 7 cls_cnt 0 2006.173.18:11:15.75#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.18:11:15.87#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.18:11:15.87#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.18:11:15.87#ibcon#enter wrdev, iclass 28, count 0 2006.173.18:11:15.87#ibcon#first serial, iclass 28, count 0 2006.173.18:11:15.87#ibcon#enter sib2, iclass 28, count 0 2006.173.18:11:15.87#ibcon#flushed, iclass 28, count 0 2006.173.18:11:15.87#ibcon#about to write, iclass 28, count 0 2006.173.18:11:15.87#ibcon#wrote, iclass 28, count 0 2006.173.18:11:15.87#ibcon#about to read 3, iclass 28, count 0 2006.173.18:11:15.89#ibcon#read 3, iclass 28, count 0 2006.173.18:11:15.89#ibcon#about to read 4, iclass 28, count 0 2006.173.18:11:15.89#ibcon#read 4, iclass 28, count 0 2006.173.18:11:15.89#ibcon#about to read 5, iclass 28, count 0 2006.173.18:11:15.89#ibcon#read 5, iclass 28, count 0 2006.173.18:11:15.89#ibcon#about to read 6, iclass 28, count 0 2006.173.18:11:15.89#ibcon#read 6, iclass 28, count 0 2006.173.18:11:15.89#ibcon#end of sib2, iclass 28, count 0 2006.173.18:11:15.89#ibcon#*mode == 0, iclass 28, count 0 2006.173.18:11:15.89#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.18:11:15.89#ibcon#[25=USB\r\n] 2006.173.18:11:15.89#ibcon#*before write, iclass 28, count 0 2006.173.18:11:15.89#ibcon#enter sib2, iclass 28, count 0 2006.173.18:11:15.89#ibcon#flushed, iclass 28, count 0 2006.173.18:11:15.89#ibcon#about to write, iclass 28, count 0 2006.173.18:11:15.89#ibcon#wrote, iclass 28, count 0 2006.173.18:11:15.89#ibcon#about to read 3, iclass 28, count 0 2006.173.18:11:15.92#ibcon#read 3, iclass 28, count 0 2006.173.18:11:15.92#ibcon#about to read 4, iclass 28, count 0 2006.173.18:11:15.92#ibcon#read 4, iclass 28, count 0 2006.173.18:11:15.92#ibcon#about to read 5, iclass 28, count 0 2006.173.18:11:15.92#ibcon#read 5, iclass 28, count 0 2006.173.18:11:15.92#ibcon#about to read 6, iclass 28, count 0 2006.173.18:11:15.92#ibcon#read 6, iclass 28, count 0 2006.173.18:11:15.92#ibcon#end of sib2, iclass 28, count 0 2006.173.18:11:15.92#ibcon#*after write, iclass 28, count 0 2006.173.18:11:15.92#ibcon#*before return 0, iclass 28, count 0 2006.173.18:11:15.92#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.18:11:15.92#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.18:11:15.92#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.18:11:15.92#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.18:11:15.92$vck44/vblo=1,629.99 2006.173.18:11:15.92#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.18:11:15.92#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.18:11:15.92#ibcon#ireg 17 cls_cnt 0 2006.173.18:11:15.92#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.18:11:15.92#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.18:11:15.92#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.18:11:15.92#ibcon#enter wrdev, iclass 30, count 0 2006.173.18:11:15.92#ibcon#first serial, iclass 30, count 0 2006.173.18:11:15.92#ibcon#enter sib2, iclass 30, count 0 2006.173.18:11:15.92#ibcon#flushed, iclass 30, count 0 2006.173.18:11:15.92#ibcon#about to write, iclass 30, count 0 2006.173.18:11:15.92#ibcon#wrote, iclass 30, count 0 2006.173.18:11:15.92#ibcon#about to read 3, iclass 30, count 0 2006.173.18:11:15.94#ibcon#read 3, iclass 30, count 0 2006.173.18:11:15.94#ibcon#about to read 4, iclass 30, count 0 2006.173.18:11:15.94#ibcon#read 4, iclass 30, count 0 2006.173.18:11:15.94#ibcon#about to read 5, iclass 30, count 0 2006.173.18:11:15.94#ibcon#read 5, iclass 30, count 0 2006.173.18:11:15.94#ibcon#about to read 6, iclass 30, count 0 2006.173.18:11:15.94#ibcon#read 6, iclass 30, count 0 2006.173.18:11:15.94#ibcon#end of sib2, iclass 30, count 0 2006.173.18:11:15.94#ibcon#*mode == 0, iclass 30, count 0 2006.173.18:11:15.94#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.18:11:15.94#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.18:11:15.94#ibcon#*before write, iclass 30, count 0 2006.173.18:11:15.94#ibcon#enter sib2, iclass 30, count 0 2006.173.18:11:15.94#ibcon#flushed, iclass 30, count 0 2006.173.18:11:15.94#ibcon#about to write, iclass 30, count 0 2006.173.18:11:15.94#ibcon#wrote, iclass 30, count 0 2006.173.18:11:15.94#ibcon#about to read 3, iclass 30, count 0 2006.173.18:11:15.98#ibcon#read 3, iclass 30, count 0 2006.173.18:11:15.98#ibcon#about to read 4, iclass 30, count 0 2006.173.18:11:15.98#ibcon#read 4, iclass 30, count 0 2006.173.18:11:15.98#ibcon#about to read 5, iclass 30, count 0 2006.173.18:11:15.98#ibcon#read 5, iclass 30, count 0 2006.173.18:11:15.98#ibcon#about to read 6, iclass 30, count 0 2006.173.18:11:15.98#ibcon#read 6, iclass 30, count 0 2006.173.18:11:15.98#ibcon#end of sib2, iclass 30, count 0 2006.173.18:11:15.98#ibcon#*after write, iclass 30, count 0 2006.173.18:11:15.98#ibcon#*before return 0, iclass 30, count 0 2006.173.18:11:15.98#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.18:11:15.98#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.18:11:15.98#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.18:11:15.98#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.18:11:15.98$vck44/vb=1,4 2006.173.18:11:15.98#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.173.18:11:15.98#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.173.18:11:15.98#ibcon#ireg 11 cls_cnt 2 2006.173.18:11:15.98#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.18:11:15.98#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.18:11:15.98#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.18:11:15.98#ibcon#enter wrdev, iclass 32, count 2 2006.173.18:11:15.98#ibcon#first serial, iclass 32, count 2 2006.173.18:11:15.98#ibcon#enter sib2, iclass 32, count 2 2006.173.18:11:15.98#ibcon#flushed, iclass 32, count 2 2006.173.18:11:15.98#ibcon#about to write, iclass 32, count 2 2006.173.18:11:15.98#ibcon#wrote, iclass 32, count 2 2006.173.18:11:15.98#ibcon#about to read 3, iclass 32, count 2 2006.173.18:11:16.00#ibcon#read 3, iclass 32, count 2 2006.173.18:11:16.00#ibcon#about to read 4, iclass 32, count 2 2006.173.18:11:16.00#ibcon#read 4, iclass 32, count 2 2006.173.18:11:16.00#ibcon#about to read 5, iclass 32, count 2 2006.173.18:11:16.00#ibcon#read 5, iclass 32, count 2 2006.173.18:11:16.00#ibcon#about to read 6, iclass 32, count 2 2006.173.18:11:16.00#ibcon#read 6, iclass 32, count 2 2006.173.18:11:16.00#ibcon#end of sib2, iclass 32, count 2 2006.173.18:11:16.00#ibcon#*mode == 0, iclass 32, count 2 2006.173.18:11:16.00#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.173.18:11:16.00#ibcon#[27=AT01-04\r\n] 2006.173.18:11:16.00#ibcon#*before write, iclass 32, count 2 2006.173.18:11:16.00#ibcon#enter sib2, iclass 32, count 2 2006.173.18:11:16.00#ibcon#flushed, iclass 32, count 2 2006.173.18:11:16.00#ibcon#about to write, iclass 32, count 2 2006.173.18:11:16.00#ibcon#wrote, iclass 32, count 2 2006.173.18:11:16.00#ibcon#about to read 3, iclass 32, count 2 2006.173.18:11:16.03#ibcon#read 3, iclass 32, count 2 2006.173.18:11:16.03#ibcon#about to read 4, iclass 32, count 2 2006.173.18:11:16.03#ibcon#read 4, iclass 32, count 2 2006.173.18:11:16.03#ibcon#about to read 5, iclass 32, count 2 2006.173.18:11:16.03#ibcon#read 5, iclass 32, count 2 2006.173.18:11:16.03#ibcon#about to read 6, iclass 32, count 2 2006.173.18:11:16.03#ibcon#read 6, iclass 32, count 2 2006.173.18:11:16.03#ibcon#end of sib2, iclass 32, count 2 2006.173.18:11:16.03#ibcon#*after write, iclass 32, count 2 2006.173.18:11:16.03#ibcon#*before return 0, iclass 32, count 2 2006.173.18:11:16.03#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.18:11:16.03#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.173.18:11:16.03#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.173.18:11:16.03#ibcon#ireg 7 cls_cnt 0 2006.173.18:11:16.03#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.18:11:16.15#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.18:11:16.15#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.18:11:16.15#ibcon#enter wrdev, iclass 32, count 0 2006.173.18:11:16.15#ibcon#first serial, iclass 32, count 0 2006.173.18:11:16.15#ibcon#enter sib2, iclass 32, count 0 2006.173.18:11:16.15#ibcon#flushed, iclass 32, count 0 2006.173.18:11:16.15#ibcon#about to write, iclass 32, count 0 2006.173.18:11:16.15#ibcon#wrote, iclass 32, count 0 2006.173.18:11:16.15#ibcon#about to read 3, iclass 32, count 0 2006.173.18:11:16.17#ibcon#read 3, iclass 32, count 0 2006.173.18:11:16.17#ibcon#about to read 4, iclass 32, count 0 2006.173.18:11:16.17#ibcon#read 4, iclass 32, count 0 2006.173.18:11:16.17#ibcon#about to read 5, iclass 32, count 0 2006.173.18:11:16.17#ibcon#read 5, iclass 32, count 0 2006.173.18:11:16.17#ibcon#about to read 6, iclass 32, count 0 2006.173.18:11:16.17#ibcon#read 6, iclass 32, count 0 2006.173.18:11:16.17#ibcon#end of sib2, iclass 32, count 0 2006.173.18:11:16.17#ibcon#*mode == 0, iclass 32, count 0 2006.173.18:11:16.17#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.18:11:16.17#ibcon#[27=USB\r\n] 2006.173.18:11:16.17#ibcon#*before write, iclass 32, count 0 2006.173.18:11:16.17#ibcon#enter sib2, iclass 32, count 0 2006.173.18:11:16.17#ibcon#flushed, iclass 32, count 0 2006.173.18:11:16.17#ibcon#about to write, iclass 32, count 0 2006.173.18:11:16.17#ibcon#wrote, iclass 32, count 0 2006.173.18:11:16.17#ibcon#about to read 3, iclass 32, count 0 2006.173.18:11:16.20#ibcon#read 3, iclass 32, count 0 2006.173.18:11:16.20#ibcon#about to read 4, iclass 32, count 0 2006.173.18:11:16.20#ibcon#read 4, iclass 32, count 0 2006.173.18:11:16.20#ibcon#about to read 5, iclass 32, count 0 2006.173.18:11:16.20#ibcon#read 5, iclass 32, count 0 2006.173.18:11:16.20#ibcon#about to read 6, iclass 32, count 0 2006.173.18:11:16.20#ibcon#read 6, iclass 32, count 0 2006.173.18:11:16.20#ibcon#end of sib2, iclass 32, count 0 2006.173.18:11:16.20#ibcon#*after write, iclass 32, count 0 2006.173.18:11:16.20#ibcon#*before return 0, iclass 32, count 0 2006.173.18:11:16.20#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.18:11:16.20#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.173.18:11:16.20#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.18:11:16.20#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.18:11:16.20$vck44/vblo=2,634.99 2006.173.18:11:16.20#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.18:11:16.20#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.18:11:16.20#ibcon#ireg 17 cls_cnt 0 2006.173.18:11:16.20#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.18:11:16.20#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.18:11:16.20#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.18:11:16.20#ibcon#enter wrdev, iclass 34, count 0 2006.173.18:11:16.20#ibcon#first serial, iclass 34, count 0 2006.173.18:11:16.20#ibcon#enter sib2, iclass 34, count 0 2006.173.18:11:16.20#ibcon#flushed, iclass 34, count 0 2006.173.18:11:16.20#ibcon#about to write, iclass 34, count 0 2006.173.18:11:16.20#ibcon#wrote, iclass 34, count 0 2006.173.18:11:16.20#ibcon#about to read 3, iclass 34, count 0 2006.173.18:11:16.22#ibcon#read 3, iclass 34, count 0 2006.173.18:11:16.22#ibcon#about to read 4, iclass 34, count 0 2006.173.18:11:16.22#ibcon#read 4, iclass 34, count 0 2006.173.18:11:16.22#ibcon#about to read 5, iclass 34, count 0 2006.173.18:11:16.22#ibcon#read 5, iclass 34, count 0 2006.173.18:11:16.22#ibcon#about to read 6, iclass 34, count 0 2006.173.18:11:16.22#ibcon#read 6, iclass 34, count 0 2006.173.18:11:16.22#ibcon#end of sib2, iclass 34, count 0 2006.173.18:11:16.22#ibcon#*mode == 0, iclass 34, count 0 2006.173.18:11:16.22#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.18:11:16.22#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.18:11:16.22#ibcon#*before write, iclass 34, count 0 2006.173.18:11:16.22#ibcon#enter sib2, iclass 34, count 0 2006.173.18:11:16.22#ibcon#flushed, iclass 34, count 0 2006.173.18:11:16.22#ibcon#about to write, iclass 34, count 0 2006.173.18:11:16.22#ibcon#wrote, iclass 34, count 0 2006.173.18:11:16.22#ibcon#about to read 3, iclass 34, count 0 2006.173.18:11:16.26#ibcon#read 3, iclass 34, count 0 2006.173.18:11:16.26#ibcon#about to read 4, iclass 34, count 0 2006.173.18:11:16.26#ibcon#read 4, iclass 34, count 0 2006.173.18:11:16.26#ibcon#about to read 5, iclass 34, count 0 2006.173.18:11:16.26#ibcon#read 5, iclass 34, count 0 2006.173.18:11:16.26#ibcon#about to read 6, iclass 34, count 0 2006.173.18:11:16.26#ibcon#read 6, iclass 34, count 0 2006.173.18:11:16.26#ibcon#end of sib2, iclass 34, count 0 2006.173.18:11:16.26#ibcon#*after write, iclass 34, count 0 2006.173.18:11:16.26#ibcon#*before return 0, iclass 34, count 0 2006.173.18:11:16.26#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.18:11:16.26#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.18:11:16.26#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.18:11:16.26#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.18:11:16.26$vck44/vb=2,4 2006.173.18:11:16.26#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.18:11:16.26#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.18:11:16.26#ibcon#ireg 11 cls_cnt 2 2006.173.18:11:16.26#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.18:11:16.32#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.18:11:16.32#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.18:11:16.32#ibcon#enter wrdev, iclass 36, count 2 2006.173.18:11:16.32#ibcon#first serial, iclass 36, count 2 2006.173.18:11:16.32#ibcon#enter sib2, iclass 36, count 2 2006.173.18:11:16.32#ibcon#flushed, iclass 36, count 2 2006.173.18:11:16.32#ibcon#about to write, iclass 36, count 2 2006.173.18:11:16.32#ibcon#wrote, iclass 36, count 2 2006.173.18:11:16.32#ibcon#about to read 3, iclass 36, count 2 2006.173.18:11:16.34#ibcon#read 3, iclass 36, count 2 2006.173.18:11:16.34#ibcon#about to read 4, iclass 36, count 2 2006.173.18:11:16.34#ibcon#read 4, iclass 36, count 2 2006.173.18:11:16.34#ibcon#about to read 5, iclass 36, count 2 2006.173.18:11:16.34#ibcon#read 5, iclass 36, count 2 2006.173.18:11:16.34#ibcon#about to read 6, iclass 36, count 2 2006.173.18:11:16.34#ibcon#read 6, iclass 36, count 2 2006.173.18:11:16.34#ibcon#end of sib2, iclass 36, count 2 2006.173.18:11:16.34#ibcon#*mode == 0, iclass 36, count 2 2006.173.18:11:16.34#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.18:11:16.34#ibcon#[27=AT02-04\r\n] 2006.173.18:11:16.34#ibcon#*before write, iclass 36, count 2 2006.173.18:11:16.34#ibcon#enter sib2, iclass 36, count 2 2006.173.18:11:16.34#ibcon#flushed, iclass 36, count 2 2006.173.18:11:16.34#ibcon#about to write, iclass 36, count 2 2006.173.18:11:16.34#ibcon#wrote, iclass 36, count 2 2006.173.18:11:16.34#ibcon#about to read 3, iclass 36, count 2 2006.173.18:11:16.37#ibcon#read 3, iclass 36, count 2 2006.173.18:11:16.37#ibcon#about to read 4, iclass 36, count 2 2006.173.18:11:16.37#ibcon#read 4, iclass 36, count 2 2006.173.18:11:16.37#ibcon#about to read 5, iclass 36, count 2 2006.173.18:11:16.37#ibcon#read 5, iclass 36, count 2 2006.173.18:11:16.37#ibcon#about to read 6, iclass 36, count 2 2006.173.18:11:16.37#ibcon#read 6, iclass 36, count 2 2006.173.18:11:16.37#ibcon#end of sib2, iclass 36, count 2 2006.173.18:11:16.37#ibcon#*after write, iclass 36, count 2 2006.173.18:11:16.37#ibcon#*before return 0, iclass 36, count 2 2006.173.18:11:16.37#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.18:11:16.37#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.18:11:16.37#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.18:11:16.37#ibcon#ireg 7 cls_cnt 0 2006.173.18:11:16.37#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.18:11:16.49#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.18:11:16.49#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.18:11:16.49#ibcon#enter wrdev, iclass 36, count 0 2006.173.18:11:16.49#ibcon#first serial, iclass 36, count 0 2006.173.18:11:16.49#ibcon#enter sib2, iclass 36, count 0 2006.173.18:11:16.49#ibcon#flushed, iclass 36, count 0 2006.173.18:11:16.49#ibcon#about to write, iclass 36, count 0 2006.173.18:11:16.49#ibcon#wrote, iclass 36, count 0 2006.173.18:11:16.49#ibcon#about to read 3, iclass 36, count 0 2006.173.18:11:16.51#ibcon#read 3, iclass 36, count 0 2006.173.18:11:16.51#ibcon#about to read 4, iclass 36, count 0 2006.173.18:11:16.51#ibcon#read 4, iclass 36, count 0 2006.173.18:11:16.51#ibcon#about to read 5, iclass 36, count 0 2006.173.18:11:16.51#ibcon#read 5, iclass 36, count 0 2006.173.18:11:16.51#ibcon#about to read 6, iclass 36, count 0 2006.173.18:11:16.51#ibcon#read 6, iclass 36, count 0 2006.173.18:11:16.51#ibcon#end of sib2, iclass 36, count 0 2006.173.18:11:16.51#ibcon#*mode == 0, iclass 36, count 0 2006.173.18:11:16.51#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.18:11:16.51#ibcon#[27=USB\r\n] 2006.173.18:11:16.51#ibcon#*before write, iclass 36, count 0 2006.173.18:11:16.51#ibcon#enter sib2, iclass 36, count 0 2006.173.18:11:16.51#ibcon#flushed, iclass 36, count 0 2006.173.18:11:16.51#ibcon#about to write, iclass 36, count 0 2006.173.18:11:16.51#ibcon#wrote, iclass 36, count 0 2006.173.18:11:16.51#ibcon#about to read 3, iclass 36, count 0 2006.173.18:11:16.54#ibcon#read 3, iclass 36, count 0 2006.173.18:11:16.54#ibcon#about to read 4, iclass 36, count 0 2006.173.18:11:16.54#ibcon#read 4, iclass 36, count 0 2006.173.18:11:16.54#ibcon#about to read 5, iclass 36, count 0 2006.173.18:11:16.54#ibcon#read 5, iclass 36, count 0 2006.173.18:11:16.54#ibcon#about to read 6, iclass 36, count 0 2006.173.18:11:16.54#ibcon#read 6, iclass 36, count 0 2006.173.18:11:16.54#ibcon#end of sib2, iclass 36, count 0 2006.173.18:11:16.54#ibcon#*after write, iclass 36, count 0 2006.173.18:11:16.54#ibcon#*before return 0, iclass 36, count 0 2006.173.18:11:16.54#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.18:11:16.54#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.18:11:16.54#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.18:11:16.54#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.18:11:16.54$vck44/vblo=3,649.99 2006.173.18:11:16.54#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.18:11:16.54#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.18:11:16.54#ibcon#ireg 17 cls_cnt 0 2006.173.18:11:16.54#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.18:11:16.54#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.18:11:16.54#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.18:11:16.54#ibcon#enter wrdev, iclass 38, count 0 2006.173.18:11:16.54#ibcon#first serial, iclass 38, count 0 2006.173.18:11:16.54#ibcon#enter sib2, iclass 38, count 0 2006.173.18:11:16.54#ibcon#flushed, iclass 38, count 0 2006.173.18:11:16.54#ibcon#about to write, iclass 38, count 0 2006.173.18:11:16.54#ibcon#wrote, iclass 38, count 0 2006.173.18:11:16.54#ibcon#about to read 3, iclass 38, count 0 2006.173.18:11:16.56#ibcon#read 3, iclass 38, count 0 2006.173.18:11:16.56#ibcon#about to read 4, iclass 38, count 0 2006.173.18:11:16.56#ibcon#read 4, iclass 38, count 0 2006.173.18:11:16.56#ibcon#about to read 5, iclass 38, count 0 2006.173.18:11:16.56#ibcon#read 5, iclass 38, count 0 2006.173.18:11:16.56#ibcon#about to read 6, iclass 38, count 0 2006.173.18:11:16.56#ibcon#read 6, iclass 38, count 0 2006.173.18:11:16.56#ibcon#end of sib2, iclass 38, count 0 2006.173.18:11:16.56#ibcon#*mode == 0, iclass 38, count 0 2006.173.18:11:16.56#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.18:11:16.56#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.18:11:16.56#ibcon#*before write, iclass 38, count 0 2006.173.18:11:16.56#ibcon#enter sib2, iclass 38, count 0 2006.173.18:11:16.56#ibcon#flushed, iclass 38, count 0 2006.173.18:11:16.56#ibcon#about to write, iclass 38, count 0 2006.173.18:11:16.56#ibcon#wrote, iclass 38, count 0 2006.173.18:11:16.56#ibcon#about to read 3, iclass 38, count 0 2006.173.18:11:16.60#ibcon#read 3, iclass 38, count 0 2006.173.18:11:16.60#ibcon#about to read 4, iclass 38, count 0 2006.173.18:11:16.60#ibcon#read 4, iclass 38, count 0 2006.173.18:11:16.60#ibcon#about to read 5, iclass 38, count 0 2006.173.18:11:16.60#ibcon#read 5, iclass 38, count 0 2006.173.18:11:16.60#ibcon#about to read 6, iclass 38, count 0 2006.173.18:11:16.60#ibcon#read 6, iclass 38, count 0 2006.173.18:11:16.60#ibcon#end of sib2, iclass 38, count 0 2006.173.18:11:16.60#ibcon#*after write, iclass 38, count 0 2006.173.18:11:16.60#ibcon#*before return 0, iclass 38, count 0 2006.173.18:11:16.60#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.18:11:16.60#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.18:11:16.60#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.18:11:16.60#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.18:11:16.60$vck44/vb=3,4 2006.173.18:11:16.60#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.18:11:16.60#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.18:11:16.60#ibcon#ireg 11 cls_cnt 2 2006.173.18:11:16.60#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.18:11:16.66#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.18:11:16.66#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.18:11:16.66#ibcon#enter wrdev, iclass 40, count 2 2006.173.18:11:16.66#ibcon#first serial, iclass 40, count 2 2006.173.18:11:16.66#ibcon#enter sib2, iclass 40, count 2 2006.173.18:11:16.66#ibcon#flushed, iclass 40, count 2 2006.173.18:11:16.66#ibcon#about to write, iclass 40, count 2 2006.173.18:11:16.66#ibcon#wrote, iclass 40, count 2 2006.173.18:11:16.66#ibcon#about to read 3, iclass 40, count 2 2006.173.18:11:16.68#ibcon#read 3, iclass 40, count 2 2006.173.18:11:16.68#ibcon#about to read 4, iclass 40, count 2 2006.173.18:11:16.68#ibcon#read 4, iclass 40, count 2 2006.173.18:11:16.68#ibcon#about to read 5, iclass 40, count 2 2006.173.18:11:16.68#ibcon#read 5, iclass 40, count 2 2006.173.18:11:16.68#ibcon#about to read 6, iclass 40, count 2 2006.173.18:11:16.68#ibcon#read 6, iclass 40, count 2 2006.173.18:11:16.68#ibcon#end of sib2, iclass 40, count 2 2006.173.18:11:16.68#ibcon#*mode == 0, iclass 40, count 2 2006.173.18:11:16.68#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.18:11:16.68#ibcon#[27=AT03-04\r\n] 2006.173.18:11:16.68#ibcon#*before write, iclass 40, count 2 2006.173.18:11:16.68#ibcon#enter sib2, iclass 40, count 2 2006.173.18:11:16.68#ibcon#flushed, iclass 40, count 2 2006.173.18:11:16.68#ibcon#about to write, iclass 40, count 2 2006.173.18:11:16.68#ibcon#wrote, iclass 40, count 2 2006.173.18:11:16.68#ibcon#about to read 3, iclass 40, count 2 2006.173.18:11:16.71#ibcon#read 3, iclass 40, count 2 2006.173.18:11:16.71#ibcon#about to read 4, iclass 40, count 2 2006.173.18:11:16.71#ibcon#read 4, iclass 40, count 2 2006.173.18:11:16.71#ibcon#about to read 5, iclass 40, count 2 2006.173.18:11:16.71#ibcon#read 5, iclass 40, count 2 2006.173.18:11:16.71#ibcon#about to read 6, iclass 40, count 2 2006.173.18:11:16.71#ibcon#read 6, iclass 40, count 2 2006.173.18:11:16.71#ibcon#end of sib2, iclass 40, count 2 2006.173.18:11:16.71#ibcon#*after write, iclass 40, count 2 2006.173.18:11:16.71#ibcon#*before return 0, iclass 40, count 2 2006.173.18:11:16.71#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.18:11:16.71#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.18:11:16.71#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.18:11:16.71#ibcon#ireg 7 cls_cnt 0 2006.173.18:11:16.71#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.18:11:16.83#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.18:11:16.83#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.18:11:16.83#ibcon#enter wrdev, iclass 40, count 0 2006.173.18:11:16.83#ibcon#first serial, iclass 40, count 0 2006.173.18:11:16.83#ibcon#enter sib2, iclass 40, count 0 2006.173.18:11:16.83#ibcon#flushed, iclass 40, count 0 2006.173.18:11:16.83#ibcon#about to write, iclass 40, count 0 2006.173.18:11:16.83#ibcon#wrote, iclass 40, count 0 2006.173.18:11:16.83#ibcon#about to read 3, iclass 40, count 0 2006.173.18:11:16.85#ibcon#read 3, iclass 40, count 0 2006.173.18:11:16.85#ibcon#about to read 4, iclass 40, count 0 2006.173.18:11:16.85#ibcon#read 4, iclass 40, count 0 2006.173.18:11:16.85#ibcon#about to read 5, iclass 40, count 0 2006.173.18:11:16.85#ibcon#read 5, iclass 40, count 0 2006.173.18:11:16.85#ibcon#about to read 6, iclass 40, count 0 2006.173.18:11:16.85#ibcon#read 6, iclass 40, count 0 2006.173.18:11:16.85#ibcon#end of sib2, iclass 40, count 0 2006.173.18:11:16.85#ibcon#*mode == 0, iclass 40, count 0 2006.173.18:11:16.85#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.18:11:16.85#ibcon#[27=USB\r\n] 2006.173.18:11:16.85#ibcon#*before write, iclass 40, count 0 2006.173.18:11:16.85#ibcon#enter sib2, iclass 40, count 0 2006.173.18:11:16.85#ibcon#flushed, iclass 40, count 0 2006.173.18:11:16.85#ibcon#about to write, iclass 40, count 0 2006.173.18:11:16.85#ibcon#wrote, iclass 40, count 0 2006.173.18:11:16.85#ibcon#about to read 3, iclass 40, count 0 2006.173.18:11:16.88#ibcon#read 3, iclass 40, count 0 2006.173.18:11:16.88#ibcon#about to read 4, iclass 40, count 0 2006.173.18:11:16.88#ibcon#read 4, iclass 40, count 0 2006.173.18:11:16.88#ibcon#about to read 5, iclass 40, count 0 2006.173.18:11:16.88#ibcon#read 5, iclass 40, count 0 2006.173.18:11:16.88#ibcon#about to read 6, iclass 40, count 0 2006.173.18:11:16.88#ibcon#read 6, iclass 40, count 0 2006.173.18:11:16.88#ibcon#end of sib2, iclass 40, count 0 2006.173.18:11:16.88#ibcon#*after write, iclass 40, count 0 2006.173.18:11:16.88#ibcon#*before return 0, iclass 40, count 0 2006.173.18:11:16.88#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.18:11:16.88#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.18:11:16.88#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.18:11:16.88#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.18:11:16.88$vck44/vblo=4,679.99 2006.173.18:11:16.88#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.18:11:16.88#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.18:11:16.88#ibcon#ireg 17 cls_cnt 0 2006.173.18:11:16.88#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.18:11:16.88#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.18:11:16.88#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.18:11:16.88#ibcon#enter wrdev, iclass 4, count 0 2006.173.18:11:16.88#ibcon#first serial, iclass 4, count 0 2006.173.18:11:16.88#ibcon#enter sib2, iclass 4, count 0 2006.173.18:11:16.88#ibcon#flushed, iclass 4, count 0 2006.173.18:11:16.88#ibcon#about to write, iclass 4, count 0 2006.173.18:11:16.88#ibcon#wrote, iclass 4, count 0 2006.173.18:11:16.88#ibcon#about to read 3, iclass 4, count 0 2006.173.18:11:16.90#ibcon#read 3, iclass 4, count 0 2006.173.18:11:16.90#ibcon#about to read 4, iclass 4, count 0 2006.173.18:11:16.90#ibcon#read 4, iclass 4, count 0 2006.173.18:11:16.90#ibcon#about to read 5, iclass 4, count 0 2006.173.18:11:16.90#ibcon#read 5, iclass 4, count 0 2006.173.18:11:16.90#ibcon#about to read 6, iclass 4, count 0 2006.173.18:11:16.90#ibcon#read 6, iclass 4, count 0 2006.173.18:11:16.90#ibcon#end of sib2, iclass 4, count 0 2006.173.18:11:16.90#ibcon#*mode == 0, iclass 4, count 0 2006.173.18:11:16.90#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.18:11:16.90#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.18:11:16.90#ibcon#*before write, iclass 4, count 0 2006.173.18:11:16.90#ibcon#enter sib2, iclass 4, count 0 2006.173.18:11:16.90#ibcon#flushed, iclass 4, count 0 2006.173.18:11:16.90#ibcon#about to write, iclass 4, count 0 2006.173.18:11:16.90#ibcon#wrote, iclass 4, count 0 2006.173.18:11:16.90#ibcon#about to read 3, iclass 4, count 0 2006.173.18:11:16.94#ibcon#read 3, iclass 4, count 0 2006.173.18:11:16.94#ibcon#about to read 4, iclass 4, count 0 2006.173.18:11:16.94#ibcon#read 4, iclass 4, count 0 2006.173.18:11:16.94#ibcon#about to read 5, iclass 4, count 0 2006.173.18:11:16.94#ibcon#read 5, iclass 4, count 0 2006.173.18:11:16.94#ibcon#about to read 6, iclass 4, count 0 2006.173.18:11:16.94#ibcon#read 6, iclass 4, count 0 2006.173.18:11:16.94#ibcon#end of sib2, iclass 4, count 0 2006.173.18:11:16.94#ibcon#*after write, iclass 4, count 0 2006.173.18:11:16.94#ibcon#*before return 0, iclass 4, count 0 2006.173.18:11:16.94#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.18:11:16.94#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.18:11:16.94#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.18:11:16.94#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.18:11:16.94$vck44/vb=4,4 2006.173.18:11:16.94#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.18:11:16.94#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.18:11:16.94#ibcon#ireg 11 cls_cnt 2 2006.173.18:11:16.94#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.18:11:17.00#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.18:11:17.00#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.18:11:17.00#ibcon#enter wrdev, iclass 6, count 2 2006.173.18:11:17.00#ibcon#first serial, iclass 6, count 2 2006.173.18:11:17.00#ibcon#enter sib2, iclass 6, count 2 2006.173.18:11:17.00#ibcon#flushed, iclass 6, count 2 2006.173.18:11:17.00#ibcon#about to write, iclass 6, count 2 2006.173.18:11:17.00#ibcon#wrote, iclass 6, count 2 2006.173.18:11:17.00#ibcon#about to read 3, iclass 6, count 2 2006.173.18:11:17.02#ibcon#read 3, iclass 6, count 2 2006.173.18:11:17.02#ibcon#about to read 4, iclass 6, count 2 2006.173.18:11:17.02#ibcon#read 4, iclass 6, count 2 2006.173.18:11:17.02#ibcon#about to read 5, iclass 6, count 2 2006.173.18:11:17.02#ibcon#read 5, iclass 6, count 2 2006.173.18:11:17.02#ibcon#about to read 6, iclass 6, count 2 2006.173.18:11:17.02#ibcon#read 6, iclass 6, count 2 2006.173.18:11:17.02#ibcon#end of sib2, iclass 6, count 2 2006.173.18:11:17.02#ibcon#*mode == 0, iclass 6, count 2 2006.173.18:11:17.02#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.18:11:17.02#ibcon#[27=AT04-04\r\n] 2006.173.18:11:17.02#ibcon#*before write, iclass 6, count 2 2006.173.18:11:17.02#ibcon#enter sib2, iclass 6, count 2 2006.173.18:11:17.02#ibcon#flushed, iclass 6, count 2 2006.173.18:11:17.02#ibcon#about to write, iclass 6, count 2 2006.173.18:11:17.02#ibcon#wrote, iclass 6, count 2 2006.173.18:11:17.02#ibcon#about to read 3, iclass 6, count 2 2006.173.18:11:17.05#ibcon#read 3, iclass 6, count 2 2006.173.18:11:17.05#ibcon#about to read 4, iclass 6, count 2 2006.173.18:11:17.05#ibcon#read 4, iclass 6, count 2 2006.173.18:11:17.05#ibcon#about to read 5, iclass 6, count 2 2006.173.18:11:17.05#ibcon#read 5, iclass 6, count 2 2006.173.18:11:17.05#ibcon#about to read 6, iclass 6, count 2 2006.173.18:11:17.05#ibcon#read 6, iclass 6, count 2 2006.173.18:11:17.05#ibcon#end of sib2, iclass 6, count 2 2006.173.18:11:17.05#ibcon#*after write, iclass 6, count 2 2006.173.18:11:17.05#ibcon#*before return 0, iclass 6, count 2 2006.173.18:11:17.05#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.18:11:17.05#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.18:11:17.05#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.18:11:17.05#ibcon#ireg 7 cls_cnt 0 2006.173.18:11:17.05#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.18:11:17.17#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.18:11:17.17#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.18:11:17.17#ibcon#enter wrdev, iclass 6, count 0 2006.173.18:11:17.17#ibcon#first serial, iclass 6, count 0 2006.173.18:11:17.17#ibcon#enter sib2, iclass 6, count 0 2006.173.18:11:17.17#ibcon#flushed, iclass 6, count 0 2006.173.18:11:17.17#ibcon#about to write, iclass 6, count 0 2006.173.18:11:17.17#ibcon#wrote, iclass 6, count 0 2006.173.18:11:17.17#ibcon#about to read 3, iclass 6, count 0 2006.173.18:11:17.19#ibcon#read 3, iclass 6, count 0 2006.173.18:11:17.19#ibcon#about to read 4, iclass 6, count 0 2006.173.18:11:17.19#ibcon#read 4, iclass 6, count 0 2006.173.18:11:17.19#ibcon#about to read 5, iclass 6, count 0 2006.173.18:11:17.19#ibcon#read 5, iclass 6, count 0 2006.173.18:11:17.19#ibcon#about to read 6, iclass 6, count 0 2006.173.18:11:17.19#ibcon#read 6, iclass 6, count 0 2006.173.18:11:17.19#ibcon#end of sib2, iclass 6, count 0 2006.173.18:11:17.19#ibcon#*mode == 0, iclass 6, count 0 2006.173.18:11:17.19#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.18:11:17.19#ibcon#[27=USB\r\n] 2006.173.18:11:17.19#ibcon#*before write, iclass 6, count 0 2006.173.18:11:17.19#ibcon#enter sib2, iclass 6, count 0 2006.173.18:11:17.19#ibcon#flushed, iclass 6, count 0 2006.173.18:11:17.19#ibcon#about to write, iclass 6, count 0 2006.173.18:11:17.19#ibcon#wrote, iclass 6, count 0 2006.173.18:11:17.19#ibcon#about to read 3, iclass 6, count 0 2006.173.18:11:17.22#ibcon#read 3, iclass 6, count 0 2006.173.18:11:17.22#ibcon#about to read 4, iclass 6, count 0 2006.173.18:11:17.22#ibcon#read 4, iclass 6, count 0 2006.173.18:11:17.22#ibcon#about to read 5, iclass 6, count 0 2006.173.18:11:17.22#ibcon#read 5, iclass 6, count 0 2006.173.18:11:17.22#ibcon#about to read 6, iclass 6, count 0 2006.173.18:11:17.22#ibcon#read 6, iclass 6, count 0 2006.173.18:11:17.22#ibcon#end of sib2, iclass 6, count 0 2006.173.18:11:17.22#ibcon#*after write, iclass 6, count 0 2006.173.18:11:17.22#ibcon#*before return 0, iclass 6, count 0 2006.173.18:11:17.22#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.18:11:17.22#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.18:11:17.22#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.18:11:17.22#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.18:11:17.22$vck44/vblo=5,709.99 2006.173.18:11:17.22#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.18:11:17.22#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.18:11:17.22#ibcon#ireg 17 cls_cnt 0 2006.173.18:11:17.22#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.18:11:17.22#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.18:11:17.22#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.18:11:17.22#ibcon#enter wrdev, iclass 10, count 0 2006.173.18:11:17.22#ibcon#first serial, iclass 10, count 0 2006.173.18:11:17.22#ibcon#enter sib2, iclass 10, count 0 2006.173.18:11:17.22#ibcon#flushed, iclass 10, count 0 2006.173.18:11:17.22#ibcon#about to write, iclass 10, count 0 2006.173.18:11:17.22#ibcon#wrote, iclass 10, count 0 2006.173.18:11:17.22#ibcon#about to read 3, iclass 10, count 0 2006.173.18:11:17.24#ibcon#read 3, iclass 10, count 0 2006.173.18:11:17.24#ibcon#about to read 4, iclass 10, count 0 2006.173.18:11:17.24#ibcon#read 4, iclass 10, count 0 2006.173.18:11:17.24#ibcon#about to read 5, iclass 10, count 0 2006.173.18:11:17.24#ibcon#read 5, iclass 10, count 0 2006.173.18:11:17.24#ibcon#about to read 6, iclass 10, count 0 2006.173.18:11:17.24#ibcon#read 6, iclass 10, count 0 2006.173.18:11:17.24#ibcon#end of sib2, iclass 10, count 0 2006.173.18:11:17.24#ibcon#*mode == 0, iclass 10, count 0 2006.173.18:11:17.24#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.18:11:17.24#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.18:11:17.24#ibcon#*before write, iclass 10, count 0 2006.173.18:11:17.24#ibcon#enter sib2, iclass 10, count 0 2006.173.18:11:17.24#ibcon#flushed, iclass 10, count 0 2006.173.18:11:17.24#ibcon#about to write, iclass 10, count 0 2006.173.18:11:17.24#ibcon#wrote, iclass 10, count 0 2006.173.18:11:17.24#ibcon#about to read 3, iclass 10, count 0 2006.173.18:11:17.28#ibcon#read 3, iclass 10, count 0 2006.173.18:11:17.28#ibcon#about to read 4, iclass 10, count 0 2006.173.18:11:17.28#ibcon#read 4, iclass 10, count 0 2006.173.18:11:17.28#ibcon#about to read 5, iclass 10, count 0 2006.173.18:11:17.28#ibcon#read 5, iclass 10, count 0 2006.173.18:11:17.28#ibcon#about to read 6, iclass 10, count 0 2006.173.18:11:17.28#ibcon#read 6, iclass 10, count 0 2006.173.18:11:17.28#ibcon#end of sib2, iclass 10, count 0 2006.173.18:11:17.28#ibcon#*after write, iclass 10, count 0 2006.173.18:11:17.28#ibcon#*before return 0, iclass 10, count 0 2006.173.18:11:17.28#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.18:11:17.28#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.18:11:17.28#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.18:11:17.28#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.18:11:17.28$vck44/vb=5,4 2006.173.18:11:17.28#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.18:11:17.28#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.18:11:17.28#ibcon#ireg 11 cls_cnt 2 2006.173.18:11:17.28#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.18:11:17.34#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.18:11:17.34#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.18:11:17.34#ibcon#enter wrdev, iclass 12, count 2 2006.173.18:11:17.34#ibcon#first serial, iclass 12, count 2 2006.173.18:11:17.34#ibcon#enter sib2, iclass 12, count 2 2006.173.18:11:17.34#ibcon#flushed, iclass 12, count 2 2006.173.18:11:17.34#ibcon#about to write, iclass 12, count 2 2006.173.18:11:17.34#ibcon#wrote, iclass 12, count 2 2006.173.18:11:17.34#ibcon#about to read 3, iclass 12, count 2 2006.173.18:11:17.36#ibcon#read 3, iclass 12, count 2 2006.173.18:11:17.36#ibcon#about to read 4, iclass 12, count 2 2006.173.18:11:17.36#ibcon#read 4, iclass 12, count 2 2006.173.18:11:17.36#ibcon#about to read 5, iclass 12, count 2 2006.173.18:11:17.36#ibcon#read 5, iclass 12, count 2 2006.173.18:11:17.36#ibcon#about to read 6, iclass 12, count 2 2006.173.18:11:17.36#ibcon#read 6, iclass 12, count 2 2006.173.18:11:17.36#ibcon#end of sib2, iclass 12, count 2 2006.173.18:11:17.36#ibcon#*mode == 0, iclass 12, count 2 2006.173.18:11:17.36#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.18:11:17.36#ibcon#[27=AT05-04\r\n] 2006.173.18:11:17.36#ibcon#*before write, iclass 12, count 2 2006.173.18:11:17.36#ibcon#enter sib2, iclass 12, count 2 2006.173.18:11:17.36#ibcon#flushed, iclass 12, count 2 2006.173.18:11:17.36#ibcon#about to write, iclass 12, count 2 2006.173.18:11:17.36#ibcon#wrote, iclass 12, count 2 2006.173.18:11:17.36#ibcon#about to read 3, iclass 12, count 2 2006.173.18:11:17.39#ibcon#read 3, iclass 12, count 2 2006.173.18:11:17.39#ibcon#about to read 4, iclass 12, count 2 2006.173.18:11:17.39#ibcon#read 4, iclass 12, count 2 2006.173.18:11:17.39#ibcon#about to read 5, iclass 12, count 2 2006.173.18:11:17.39#ibcon#read 5, iclass 12, count 2 2006.173.18:11:17.39#ibcon#about to read 6, iclass 12, count 2 2006.173.18:11:17.39#ibcon#read 6, iclass 12, count 2 2006.173.18:11:17.39#ibcon#end of sib2, iclass 12, count 2 2006.173.18:11:17.39#ibcon#*after write, iclass 12, count 2 2006.173.18:11:17.39#ibcon#*before return 0, iclass 12, count 2 2006.173.18:11:17.39#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.18:11:17.39#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.18:11:17.39#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.18:11:17.39#ibcon#ireg 7 cls_cnt 0 2006.173.18:11:17.39#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.18:11:17.51#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.18:11:17.51#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.18:11:17.51#ibcon#enter wrdev, iclass 12, count 0 2006.173.18:11:17.51#ibcon#first serial, iclass 12, count 0 2006.173.18:11:17.51#ibcon#enter sib2, iclass 12, count 0 2006.173.18:11:17.51#ibcon#flushed, iclass 12, count 0 2006.173.18:11:17.51#ibcon#about to write, iclass 12, count 0 2006.173.18:11:17.51#ibcon#wrote, iclass 12, count 0 2006.173.18:11:17.51#ibcon#about to read 3, iclass 12, count 0 2006.173.18:11:17.53#ibcon#read 3, iclass 12, count 0 2006.173.18:11:17.53#ibcon#about to read 4, iclass 12, count 0 2006.173.18:11:17.53#ibcon#read 4, iclass 12, count 0 2006.173.18:11:17.53#ibcon#about to read 5, iclass 12, count 0 2006.173.18:11:17.53#ibcon#read 5, iclass 12, count 0 2006.173.18:11:17.53#ibcon#about to read 6, iclass 12, count 0 2006.173.18:11:17.53#ibcon#read 6, iclass 12, count 0 2006.173.18:11:17.53#ibcon#end of sib2, iclass 12, count 0 2006.173.18:11:17.53#ibcon#*mode == 0, iclass 12, count 0 2006.173.18:11:17.53#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.18:11:17.53#ibcon#[27=USB\r\n] 2006.173.18:11:17.53#ibcon#*before write, iclass 12, count 0 2006.173.18:11:17.53#ibcon#enter sib2, iclass 12, count 0 2006.173.18:11:17.53#ibcon#flushed, iclass 12, count 0 2006.173.18:11:17.53#ibcon#about to write, iclass 12, count 0 2006.173.18:11:17.53#ibcon#wrote, iclass 12, count 0 2006.173.18:11:17.53#ibcon#about to read 3, iclass 12, count 0 2006.173.18:11:17.56#ibcon#read 3, iclass 12, count 0 2006.173.18:11:17.56#ibcon#about to read 4, iclass 12, count 0 2006.173.18:11:17.56#ibcon#read 4, iclass 12, count 0 2006.173.18:11:17.56#ibcon#about to read 5, iclass 12, count 0 2006.173.18:11:17.56#ibcon#read 5, iclass 12, count 0 2006.173.18:11:17.56#ibcon#about to read 6, iclass 12, count 0 2006.173.18:11:17.56#ibcon#read 6, iclass 12, count 0 2006.173.18:11:17.56#ibcon#end of sib2, iclass 12, count 0 2006.173.18:11:17.56#ibcon#*after write, iclass 12, count 0 2006.173.18:11:17.56#ibcon#*before return 0, iclass 12, count 0 2006.173.18:11:17.56#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.18:11:17.56#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.18:11:17.56#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.18:11:17.56#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.18:11:17.56$vck44/vblo=6,719.99 2006.173.18:11:17.56#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.18:11:17.56#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.18:11:17.56#ibcon#ireg 17 cls_cnt 0 2006.173.18:11:17.56#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.18:11:17.56#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.18:11:17.56#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.18:11:17.56#ibcon#enter wrdev, iclass 14, count 0 2006.173.18:11:17.56#ibcon#first serial, iclass 14, count 0 2006.173.18:11:17.56#ibcon#enter sib2, iclass 14, count 0 2006.173.18:11:17.56#ibcon#flushed, iclass 14, count 0 2006.173.18:11:17.56#ibcon#about to write, iclass 14, count 0 2006.173.18:11:17.56#ibcon#wrote, iclass 14, count 0 2006.173.18:11:17.56#ibcon#about to read 3, iclass 14, count 0 2006.173.18:11:17.58#ibcon#read 3, iclass 14, count 0 2006.173.18:11:17.58#ibcon#about to read 4, iclass 14, count 0 2006.173.18:11:17.58#ibcon#read 4, iclass 14, count 0 2006.173.18:11:17.58#ibcon#about to read 5, iclass 14, count 0 2006.173.18:11:17.58#ibcon#read 5, iclass 14, count 0 2006.173.18:11:17.58#ibcon#about to read 6, iclass 14, count 0 2006.173.18:11:17.58#ibcon#read 6, iclass 14, count 0 2006.173.18:11:17.58#ibcon#end of sib2, iclass 14, count 0 2006.173.18:11:17.58#ibcon#*mode == 0, iclass 14, count 0 2006.173.18:11:17.58#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.18:11:17.58#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.18:11:17.58#ibcon#*before write, iclass 14, count 0 2006.173.18:11:17.58#ibcon#enter sib2, iclass 14, count 0 2006.173.18:11:17.58#ibcon#flushed, iclass 14, count 0 2006.173.18:11:17.58#ibcon#about to write, iclass 14, count 0 2006.173.18:11:17.58#ibcon#wrote, iclass 14, count 0 2006.173.18:11:17.58#ibcon#about to read 3, iclass 14, count 0 2006.173.18:11:17.62#ibcon#read 3, iclass 14, count 0 2006.173.18:11:17.62#ibcon#about to read 4, iclass 14, count 0 2006.173.18:11:17.62#ibcon#read 4, iclass 14, count 0 2006.173.18:11:17.62#ibcon#about to read 5, iclass 14, count 0 2006.173.18:11:17.62#ibcon#read 5, iclass 14, count 0 2006.173.18:11:17.62#ibcon#about to read 6, iclass 14, count 0 2006.173.18:11:17.62#ibcon#read 6, iclass 14, count 0 2006.173.18:11:17.62#ibcon#end of sib2, iclass 14, count 0 2006.173.18:11:17.62#ibcon#*after write, iclass 14, count 0 2006.173.18:11:17.62#ibcon#*before return 0, iclass 14, count 0 2006.173.18:11:17.62#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.18:11:17.62#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.18:11:17.62#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.18:11:17.62#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.18:11:17.62$vck44/vb=6,4 2006.173.18:11:17.62#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.18:11:17.62#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.18:11:17.62#ibcon#ireg 11 cls_cnt 2 2006.173.18:11:17.62#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.18:11:17.68#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.18:11:17.68#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.18:11:17.68#ibcon#enter wrdev, iclass 16, count 2 2006.173.18:11:17.68#ibcon#first serial, iclass 16, count 2 2006.173.18:11:17.68#ibcon#enter sib2, iclass 16, count 2 2006.173.18:11:17.68#ibcon#flushed, iclass 16, count 2 2006.173.18:11:17.68#ibcon#about to write, iclass 16, count 2 2006.173.18:11:17.68#ibcon#wrote, iclass 16, count 2 2006.173.18:11:17.68#ibcon#about to read 3, iclass 16, count 2 2006.173.18:11:17.70#ibcon#read 3, iclass 16, count 2 2006.173.18:11:17.70#ibcon#about to read 4, iclass 16, count 2 2006.173.18:11:17.70#ibcon#read 4, iclass 16, count 2 2006.173.18:11:17.70#ibcon#about to read 5, iclass 16, count 2 2006.173.18:11:17.70#ibcon#read 5, iclass 16, count 2 2006.173.18:11:17.70#ibcon#about to read 6, iclass 16, count 2 2006.173.18:11:17.70#ibcon#read 6, iclass 16, count 2 2006.173.18:11:17.70#ibcon#end of sib2, iclass 16, count 2 2006.173.18:11:17.70#ibcon#*mode == 0, iclass 16, count 2 2006.173.18:11:17.70#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.18:11:17.70#ibcon#[27=AT06-04\r\n] 2006.173.18:11:17.70#ibcon#*before write, iclass 16, count 2 2006.173.18:11:17.70#ibcon#enter sib2, iclass 16, count 2 2006.173.18:11:17.70#ibcon#flushed, iclass 16, count 2 2006.173.18:11:17.70#ibcon#about to write, iclass 16, count 2 2006.173.18:11:17.70#ibcon#wrote, iclass 16, count 2 2006.173.18:11:17.70#ibcon#about to read 3, iclass 16, count 2 2006.173.18:11:17.73#ibcon#read 3, iclass 16, count 2 2006.173.18:11:17.73#ibcon#about to read 4, iclass 16, count 2 2006.173.18:11:17.73#ibcon#read 4, iclass 16, count 2 2006.173.18:11:17.73#ibcon#about to read 5, iclass 16, count 2 2006.173.18:11:17.73#ibcon#read 5, iclass 16, count 2 2006.173.18:11:17.73#ibcon#about to read 6, iclass 16, count 2 2006.173.18:11:17.73#ibcon#read 6, iclass 16, count 2 2006.173.18:11:17.73#ibcon#end of sib2, iclass 16, count 2 2006.173.18:11:17.73#ibcon#*after write, iclass 16, count 2 2006.173.18:11:17.73#ibcon#*before return 0, iclass 16, count 2 2006.173.18:11:17.73#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.18:11:17.73#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.18:11:17.73#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.18:11:17.73#ibcon#ireg 7 cls_cnt 0 2006.173.18:11:17.73#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.18:11:17.85#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.18:11:17.85#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.18:11:17.85#ibcon#enter wrdev, iclass 16, count 0 2006.173.18:11:17.85#ibcon#first serial, iclass 16, count 0 2006.173.18:11:17.85#ibcon#enter sib2, iclass 16, count 0 2006.173.18:11:17.85#ibcon#flushed, iclass 16, count 0 2006.173.18:11:17.85#ibcon#about to write, iclass 16, count 0 2006.173.18:11:17.85#ibcon#wrote, iclass 16, count 0 2006.173.18:11:17.85#ibcon#about to read 3, iclass 16, count 0 2006.173.18:11:17.87#ibcon#read 3, iclass 16, count 0 2006.173.18:11:17.87#ibcon#about to read 4, iclass 16, count 0 2006.173.18:11:17.87#ibcon#read 4, iclass 16, count 0 2006.173.18:11:17.87#ibcon#about to read 5, iclass 16, count 0 2006.173.18:11:17.87#ibcon#read 5, iclass 16, count 0 2006.173.18:11:17.87#ibcon#about to read 6, iclass 16, count 0 2006.173.18:11:17.87#ibcon#read 6, iclass 16, count 0 2006.173.18:11:17.87#ibcon#end of sib2, iclass 16, count 0 2006.173.18:11:17.87#ibcon#*mode == 0, iclass 16, count 0 2006.173.18:11:17.87#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.18:11:17.87#ibcon#[27=USB\r\n] 2006.173.18:11:17.87#ibcon#*before write, iclass 16, count 0 2006.173.18:11:17.87#ibcon#enter sib2, iclass 16, count 0 2006.173.18:11:17.87#ibcon#flushed, iclass 16, count 0 2006.173.18:11:17.87#ibcon#about to write, iclass 16, count 0 2006.173.18:11:17.87#ibcon#wrote, iclass 16, count 0 2006.173.18:11:17.87#ibcon#about to read 3, iclass 16, count 0 2006.173.18:11:17.90#ibcon#read 3, iclass 16, count 0 2006.173.18:11:17.90#ibcon#about to read 4, iclass 16, count 0 2006.173.18:11:17.90#ibcon#read 4, iclass 16, count 0 2006.173.18:11:17.90#ibcon#about to read 5, iclass 16, count 0 2006.173.18:11:17.90#ibcon#read 5, iclass 16, count 0 2006.173.18:11:17.90#ibcon#about to read 6, iclass 16, count 0 2006.173.18:11:17.90#ibcon#read 6, iclass 16, count 0 2006.173.18:11:17.90#ibcon#end of sib2, iclass 16, count 0 2006.173.18:11:17.90#ibcon#*after write, iclass 16, count 0 2006.173.18:11:17.90#ibcon#*before return 0, iclass 16, count 0 2006.173.18:11:17.90#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.18:11:17.90#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.18:11:17.90#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.18:11:17.90#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.18:11:17.90$vck44/vblo=7,734.99 2006.173.18:11:17.90#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.18:11:17.90#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.18:11:17.90#ibcon#ireg 17 cls_cnt 0 2006.173.18:11:17.90#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.18:11:17.90#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.18:11:17.90#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.18:11:17.90#ibcon#enter wrdev, iclass 18, count 0 2006.173.18:11:17.90#ibcon#first serial, iclass 18, count 0 2006.173.18:11:17.90#ibcon#enter sib2, iclass 18, count 0 2006.173.18:11:17.90#ibcon#flushed, iclass 18, count 0 2006.173.18:11:17.90#ibcon#about to write, iclass 18, count 0 2006.173.18:11:17.90#ibcon#wrote, iclass 18, count 0 2006.173.18:11:17.90#ibcon#about to read 3, iclass 18, count 0 2006.173.18:11:17.92#ibcon#read 3, iclass 18, count 0 2006.173.18:11:17.92#ibcon#about to read 4, iclass 18, count 0 2006.173.18:11:17.92#ibcon#read 4, iclass 18, count 0 2006.173.18:11:17.92#ibcon#about to read 5, iclass 18, count 0 2006.173.18:11:17.92#ibcon#read 5, iclass 18, count 0 2006.173.18:11:17.92#ibcon#about to read 6, iclass 18, count 0 2006.173.18:11:17.92#ibcon#read 6, iclass 18, count 0 2006.173.18:11:17.92#ibcon#end of sib2, iclass 18, count 0 2006.173.18:11:17.92#ibcon#*mode == 0, iclass 18, count 0 2006.173.18:11:17.92#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.18:11:17.92#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.18:11:17.92#ibcon#*before write, iclass 18, count 0 2006.173.18:11:17.92#ibcon#enter sib2, iclass 18, count 0 2006.173.18:11:17.92#ibcon#flushed, iclass 18, count 0 2006.173.18:11:17.92#ibcon#about to write, iclass 18, count 0 2006.173.18:11:17.92#ibcon#wrote, iclass 18, count 0 2006.173.18:11:17.92#ibcon#about to read 3, iclass 18, count 0 2006.173.18:11:17.96#ibcon#read 3, iclass 18, count 0 2006.173.18:11:17.96#ibcon#about to read 4, iclass 18, count 0 2006.173.18:11:17.96#ibcon#read 4, iclass 18, count 0 2006.173.18:11:17.96#ibcon#about to read 5, iclass 18, count 0 2006.173.18:11:17.96#ibcon#read 5, iclass 18, count 0 2006.173.18:11:17.96#ibcon#about to read 6, iclass 18, count 0 2006.173.18:11:17.96#ibcon#read 6, iclass 18, count 0 2006.173.18:11:17.96#ibcon#end of sib2, iclass 18, count 0 2006.173.18:11:17.96#ibcon#*after write, iclass 18, count 0 2006.173.18:11:17.96#ibcon#*before return 0, iclass 18, count 0 2006.173.18:11:17.96#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.18:11:17.96#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.18:11:17.96#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.18:11:17.96#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.18:11:17.96$vck44/vb=7,4 2006.173.18:11:17.96#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.18:11:17.96#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.18:11:17.96#ibcon#ireg 11 cls_cnt 2 2006.173.18:11:17.96#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.18:11:18.02#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.18:11:18.02#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.18:11:18.02#ibcon#enter wrdev, iclass 20, count 2 2006.173.18:11:18.02#ibcon#first serial, iclass 20, count 2 2006.173.18:11:18.02#ibcon#enter sib2, iclass 20, count 2 2006.173.18:11:18.02#ibcon#flushed, iclass 20, count 2 2006.173.18:11:18.02#ibcon#about to write, iclass 20, count 2 2006.173.18:11:18.02#ibcon#wrote, iclass 20, count 2 2006.173.18:11:18.02#ibcon#about to read 3, iclass 20, count 2 2006.173.18:11:18.04#ibcon#read 3, iclass 20, count 2 2006.173.18:11:18.04#ibcon#about to read 4, iclass 20, count 2 2006.173.18:11:18.04#ibcon#read 4, iclass 20, count 2 2006.173.18:11:18.04#ibcon#about to read 5, iclass 20, count 2 2006.173.18:11:18.04#ibcon#read 5, iclass 20, count 2 2006.173.18:11:18.04#ibcon#about to read 6, iclass 20, count 2 2006.173.18:11:18.04#ibcon#read 6, iclass 20, count 2 2006.173.18:11:18.04#ibcon#end of sib2, iclass 20, count 2 2006.173.18:11:18.04#ibcon#*mode == 0, iclass 20, count 2 2006.173.18:11:18.04#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.18:11:18.04#ibcon#[27=AT07-04\r\n] 2006.173.18:11:18.04#ibcon#*before write, iclass 20, count 2 2006.173.18:11:18.04#ibcon#enter sib2, iclass 20, count 2 2006.173.18:11:18.04#ibcon#flushed, iclass 20, count 2 2006.173.18:11:18.04#ibcon#about to write, iclass 20, count 2 2006.173.18:11:18.04#ibcon#wrote, iclass 20, count 2 2006.173.18:11:18.04#ibcon#about to read 3, iclass 20, count 2 2006.173.18:11:18.07#ibcon#read 3, iclass 20, count 2 2006.173.18:11:18.07#ibcon#about to read 4, iclass 20, count 2 2006.173.18:11:18.07#ibcon#read 4, iclass 20, count 2 2006.173.18:11:18.07#ibcon#about to read 5, iclass 20, count 2 2006.173.18:11:18.07#ibcon#read 5, iclass 20, count 2 2006.173.18:11:18.07#ibcon#about to read 6, iclass 20, count 2 2006.173.18:11:18.07#ibcon#read 6, iclass 20, count 2 2006.173.18:11:18.07#ibcon#end of sib2, iclass 20, count 2 2006.173.18:11:18.07#ibcon#*after write, iclass 20, count 2 2006.173.18:11:18.07#ibcon#*before return 0, iclass 20, count 2 2006.173.18:11:18.07#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.18:11:18.07#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.18:11:18.07#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.18:11:18.07#ibcon#ireg 7 cls_cnt 0 2006.173.18:11:18.07#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.18:11:18.19#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.18:11:18.19#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.18:11:18.19#ibcon#enter wrdev, iclass 20, count 0 2006.173.18:11:18.19#ibcon#first serial, iclass 20, count 0 2006.173.18:11:18.19#ibcon#enter sib2, iclass 20, count 0 2006.173.18:11:18.19#ibcon#flushed, iclass 20, count 0 2006.173.18:11:18.19#ibcon#about to write, iclass 20, count 0 2006.173.18:11:18.19#ibcon#wrote, iclass 20, count 0 2006.173.18:11:18.19#ibcon#about to read 3, iclass 20, count 0 2006.173.18:11:18.21#ibcon#read 3, iclass 20, count 0 2006.173.18:11:18.21#ibcon#about to read 4, iclass 20, count 0 2006.173.18:11:18.21#ibcon#read 4, iclass 20, count 0 2006.173.18:11:18.21#ibcon#about to read 5, iclass 20, count 0 2006.173.18:11:18.21#ibcon#read 5, iclass 20, count 0 2006.173.18:11:18.21#ibcon#about to read 6, iclass 20, count 0 2006.173.18:11:18.21#ibcon#read 6, iclass 20, count 0 2006.173.18:11:18.21#ibcon#end of sib2, iclass 20, count 0 2006.173.18:11:18.21#ibcon#*mode == 0, iclass 20, count 0 2006.173.18:11:18.21#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.18:11:18.21#ibcon#[27=USB\r\n] 2006.173.18:11:18.21#ibcon#*before write, iclass 20, count 0 2006.173.18:11:18.21#ibcon#enter sib2, iclass 20, count 0 2006.173.18:11:18.21#ibcon#flushed, iclass 20, count 0 2006.173.18:11:18.21#ibcon#about to write, iclass 20, count 0 2006.173.18:11:18.21#ibcon#wrote, iclass 20, count 0 2006.173.18:11:18.21#ibcon#about to read 3, iclass 20, count 0 2006.173.18:11:18.24#ibcon#read 3, iclass 20, count 0 2006.173.18:11:18.24#ibcon#about to read 4, iclass 20, count 0 2006.173.18:11:18.24#ibcon#read 4, iclass 20, count 0 2006.173.18:11:18.24#ibcon#about to read 5, iclass 20, count 0 2006.173.18:11:18.24#ibcon#read 5, iclass 20, count 0 2006.173.18:11:18.24#ibcon#about to read 6, iclass 20, count 0 2006.173.18:11:18.24#ibcon#read 6, iclass 20, count 0 2006.173.18:11:18.24#ibcon#end of sib2, iclass 20, count 0 2006.173.18:11:18.24#ibcon#*after write, iclass 20, count 0 2006.173.18:11:18.24#ibcon#*before return 0, iclass 20, count 0 2006.173.18:11:18.24#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.18:11:18.24#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.18:11:18.24#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.18:11:18.24#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.18:11:18.24$vck44/vblo=8,744.99 2006.173.18:11:18.24#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.18:11:18.24#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.18:11:18.24#ibcon#ireg 17 cls_cnt 0 2006.173.18:11:18.24#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.18:11:18.24#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.18:11:18.24#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.18:11:18.24#ibcon#enter wrdev, iclass 22, count 0 2006.173.18:11:18.24#ibcon#first serial, iclass 22, count 0 2006.173.18:11:18.24#ibcon#enter sib2, iclass 22, count 0 2006.173.18:11:18.24#ibcon#flushed, iclass 22, count 0 2006.173.18:11:18.24#ibcon#about to write, iclass 22, count 0 2006.173.18:11:18.24#ibcon#wrote, iclass 22, count 0 2006.173.18:11:18.24#ibcon#about to read 3, iclass 22, count 0 2006.173.18:11:18.26#ibcon#read 3, iclass 22, count 0 2006.173.18:11:18.26#ibcon#about to read 4, iclass 22, count 0 2006.173.18:11:18.26#ibcon#read 4, iclass 22, count 0 2006.173.18:11:18.26#ibcon#about to read 5, iclass 22, count 0 2006.173.18:11:18.26#ibcon#read 5, iclass 22, count 0 2006.173.18:11:18.26#ibcon#about to read 6, iclass 22, count 0 2006.173.18:11:18.26#ibcon#read 6, iclass 22, count 0 2006.173.18:11:18.26#ibcon#end of sib2, iclass 22, count 0 2006.173.18:11:18.26#ibcon#*mode == 0, iclass 22, count 0 2006.173.18:11:18.26#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.18:11:18.26#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.18:11:18.26#ibcon#*before write, iclass 22, count 0 2006.173.18:11:18.26#ibcon#enter sib2, iclass 22, count 0 2006.173.18:11:18.26#ibcon#flushed, iclass 22, count 0 2006.173.18:11:18.26#ibcon#about to write, iclass 22, count 0 2006.173.18:11:18.26#ibcon#wrote, iclass 22, count 0 2006.173.18:11:18.26#ibcon#about to read 3, iclass 22, count 0 2006.173.18:11:18.30#ibcon#read 3, iclass 22, count 0 2006.173.18:11:18.30#ibcon#about to read 4, iclass 22, count 0 2006.173.18:11:18.30#ibcon#read 4, iclass 22, count 0 2006.173.18:11:18.30#ibcon#about to read 5, iclass 22, count 0 2006.173.18:11:18.30#ibcon#read 5, iclass 22, count 0 2006.173.18:11:18.30#ibcon#about to read 6, iclass 22, count 0 2006.173.18:11:18.30#ibcon#read 6, iclass 22, count 0 2006.173.18:11:18.30#ibcon#end of sib2, iclass 22, count 0 2006.173.18:11:18.30#ibcon#*after write, iclass 22, count 0 2006.173.18:11:18.30#ibcon#*before return 0, iclass 22, count 0 2006.173.18:11:18.30#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.18:11:18.30#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.18:11:18.30#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.18:11:18.30#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.18:11:18.30$vck44/vb=8,4 2006.173.18:11:18.30#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.18:11:18.30#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.18:11:18.30#ibcon#ireg 11 cls_cnt 2 2006.173.18:11:18.30#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.18:11:18.36#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.18:11:18.36#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.18:11:18.36#ibcon#enter wrdev, iclass 24, count 2 2006.173.18:11:18.36#ibcon#first serial, iclass 24, count 2 2006.173.18:11:18.36#ibcon#enter sib2, iclass 24, count 2 2006.173.18:11:18.36#ibcon#flushed, iclass 24, count 2 2006.173.18:11:18.36#ibcon#about to write, iclass 24, count 2 2006.173.18:11:18.36#ibcon#wrote, iclass 24, count 2 2006.173.18:11:18.36#ibcon#about to read 3, iclass 24, count 2 2006.173.18:11:18.38#ibcon#read 3, iclass 24, count 2 2006.173.18:11:18.38#ibcon#about to read 4, iclass 24, count 2 2006.173.18:11:18.38#ibcon#read 4, iclass 24, count 2 2006.173.18:11:18.38#ibcon#about to read 5, iclass 24, count 2 2006.173.18:11:18.38#ibcon#read 5, iclass 24, count 2 2006.173.18:11:18.38#ibcon#about to read 6, iclass 24, count 2 2006.173.18:11:18.38#ibcon#read 6, iclass 24, count 2 2006.173.18:11:18.38#ibcon#end of sib2, iclass 24, count 2 2006.173.18:11:18.38#ibcon#*mode == 0, iclass 24, count 2 2006.173.18:11:18.38#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.18:11:18.38#ibcon#[27=AT08-04\r\n] 2006.173.18:11:18.38#ibcon#*before write, iclass 24, count 2 2006.173.18:11:18.38#ibcon#enter sib2, iclass 24, count 2 2006.173.18:11:18.38#ibcon#flushed, iclass 24, count 2 2006.173.18:11:18.38#ibcon#about to write, iclass 24, count 2 2006.173.18:11:18.38#ibcon#wrote, iclass 24, count 2 2006.173.18:11:18.38#ibcon#about to read 3, iclass 24, count 2 2006.173.18:11:18.41#ibcon#read 3, iclass 24, count 2 2006.173.18:11:18.41#ibcon#about to read 4, iclass 24, count 2 2006.173.18:11:18.41#ibcon#read 4, iclass 24, count 2 2006.173.18:11:18.41#ibcon#about to read 5, iclass 24, count 2 2006.173.18:11:18.41#ibcon#read 5, iclass 24, count 2 2006.173.18:11:18.41#ibcon#about to read 6, iclass 24, count 2 2006.173.18:11:18.41#ibcon#read 6, iclass 24, count 2 2006.173.18:11:18.41#ibcon#end of sib2, iclass 24, count 2 2006.173.18:11:18.41#ibcon#*after write, iclass 24, count 2 2006.173.18:11:18.41#ibcon#*before return 0, iclass 24, count 2 2006.173.18:11:18.41#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.18:11:18.41#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.18:11:18.41#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.18:11:18.41#ibcon#ireg 7 cls_cnt 0 2006.173.18:11:18.41#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.18:11:18.53#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.18:11:18.53#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.18:11:18.53#ibcon#enter wrdev, iclass 24, count 0 2006.173.18:11:18.53#ibcon#first serial, iclass 24, count 0 2006.173.18:11:18.53#ibcon#enter sib2, iclass 24, count 0 2006.173.18:11:18.53#ibcon#flushed, iclass 24, count 0 2006.173.18:11:18.53#ibcon#about to write, iclass 24, count 0 2006.173.18:11:18.53#ibcon#wrote, iclass 24, count 0 2006.173.18:11:18.53#ibcon#about to read 3, iclass 24, count 0 2006.173.18:11:18.55#ibcon#read 3, iclass 24, count 0 2006.173.18:11:18.55#ibcon#about to read 4, iclass 24, count 0 2006.173.18:11:18.55#ibcon#read 4, iclass 24, count 0 2006.173.18:11:18.55#ibcon#about to read 5, iclass 24, count 0 2006.173.18:11:18.55#ibcon#read 5, iclass 24, count 0 2006.173.18:11:18.55#ibcon#about to read 6, iclass 24, count 0 2006.173.18:11:18.55#ibcon#read 6, iclass 24, count 0 2006.173.18:11:18.55#ibcon#end of sib2, iclass 24, count 0 2006.173.18:11:18.55#ibcon#*mode == 0, iclass 24, count 0 2006.173.18:11:18.55#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.18:11:18.55#ibcon#[27=USB\r\n] 2006.173.18:11:18.55#ibcon#*before write, iclass 24, count 0 2006.173.18:11:18.55#ibcon#enter sib2, iclass 24, count 0 2006.173.18:11:18.55#ibcon#flushed, iclass 24, count 0 2006.173.18:11:18.55#ibcon#about to write, iclass 24, count 0 2006.173.18:11:18.55#ibcon#wrote, iclass 24, count 0 2006.173.18:11:18.55#ibcon#about to read 3, iclass 24, count 0 2006.173.18:11:18.58#ibcon#read 3, iclass 24, count 0 2006.173.18:11:18.58#ibcon#about to read 4, iclass 24, count 0 2006.173.18:11:18.58#ibcon#read 4, iclass 24, count 0 2006.173.18:11:18.58#ibcon#about to read 5, iclass 24, count 0 2006.173.18:11:18.58#ibcon#read 5, iclass 24, count 0 2006.173.18:11:18.58#ibcon#about to read 6, iclass 24, count 0 2006.173.18:11:18.58#ibcon#read 6, iclass 24, count 0 2006.173.18:11:18.58#ibcon#end of sib2, iclass 24, count 0 2006.173.18:11:18.58#ibcon#*after write, iclass 24, count 0 2006.173.18:11:18.58#ibcon#*before return 0, iclass 24, count 0 2006.173.18:11:18.58#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.18:11:18.58#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.18:11:18.58#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.18:11:18.58#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.18:11:18.58$vck44/vabw=wide 2006.173.18:11:18.58#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.18:11:18.58#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.18:11:18.58#ibcon#ireg 8 cls_cnt 0 2006.173.18:11:18.58#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.18:11:18.58#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.18:11:18.58#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.18:11:18.58#ibcon#enter wrdev, iclass 26, count 0 2006.173.18:11:18.58#ibcon#first serial, iclass 26, count 0 2006.173.18:11:18.58#ibcon#enter sib2, iclass 26, count 0 2006.173.18:11:18.58#ibcon#flushed, iclass 26, count 0 2006.173.18:11:18.58#ibcon#about to write, iclass 26, count 0 2006.173.18:11:18.58#ibcon#wrote, iclass 26, count 0 2006.173.18:11:18.58#ibcon#about to read 3, iclass 26, count 0 2006.173.18:11:18.60#ibcon#read 3, iclass 26, count 0 2006.173.18:11:18.60#ibcon#about to read 4, iclass 26, count 0 2006.173.18:11:18.60#ibcon#read 4, iclass 26, count 0 2006.173.18:11:18.60#ibcon#about to read 5, iclass 26, count 0 2006.173.18:11:18.60#ibcon#read 5, iclass 26, count 0 2006.173.18:11:18.60#ibcon#about to read 6, iclass 26, count 0 2006.173.18:11:18.60#ibcon#read 6, iclass 26, count 0 2006.173.18:11:18.60#ibcon#end of sib2, iclass 26, count 0 2006.173.18:11:18.60#ibcon#*mode == 0, iclass 26, count 0 2006.173.18:11:18.60#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.18:11:18.60#ibcon#[25=BW32\r\n] 2006.173.18:11:18.60#ibcon#*before write, iclass 26, count 0 2006.173.18:11:18.60#ibcon#enter sib2, iclass 26, count 0 2006.173.18:11:18.60#ibcon#flushed, iclass 26, count 0 2006.173.18:11:18.60#ibcon#about to write, iclass 26, count 0 2006.173.18:11:18.60#ibcon#wrote, iclass 26, count 0 2006.173.18:11:18.60#ibcon#about to read 3, iclass 26, count 0 2006.173.18:11:18.63#ibcon#read 3, iclass 26, count 0 2006.173.18:11:18.63#ibcon#about to read 4, iclass 26, count 0 2006.173.18:11:18.63#ibcon#read 4, iclass 26, count 0 2006.173.18:11:18.63#ibcon#about to read 5, iclass 26, count 0 2006.173.18:11:18.63#ibcon#read 5, iclass 26, count 0 2006.173.18:11:18.63#ibcon#about to read 6, iclass 26, count 0 2006.173.18:11:18.63#ibcon#read 6, iclass 26, count 0 2006.173.18:11:18.63#ibcon#end of sib2, iclass 26, count 0 2006.173.18:11:18.63#ibcon#*after write, iclass 26, count 0 2006.173.18:11:18.63#ibcon#*before return 0, iclass 26, count 0 2006.173.18:11:18.63#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.18:11:18.63#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.18:11:18.63#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.18:11:18.63#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.18:11:18.63$vck44/vbbw=wide 2006.173.18:11:18.63#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.18:11:18.63#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.18:11:18.63#ibcon#ireg 8 cls_cnt 0 2006.173.18:11:18.63#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.18:11:18.70#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.18:11:18.70#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.18:11:18.70#ibcon#enter wrdev, iclass 28, count 0 2006.173.18:11:18.70#ibcon#first serial, iclass 28, count 0 2006.173.18:11:18.70#ibcon#enter sib2, iclass 28, count 0 2006.173.18:11:18.70#ibcon#flushed, iclass 28, count 0 2006.173.18:11:18.70#ibcon#about to write, iclass 28, count 0 2006.173.18:11:18.70#ibcon#wrote, iclass 28, count 0 2006.173.18:11:18.70#ibcon#about to read 3, iclass 28, count 0 2006.173.18:11:18.72#ibcon#read 3, iclass 28, count 0 2006.173.18:11:18.72#ibcon#about to read 4, iclass 28, count 0 2006.173.18:11:18.72#ibcon#read 4, iclass 28, count 0 2006.173.18:11:18.72#ibcon#about to read 5, iclass 28, count 0 2006.173.18:11:18.72#ibcon#read 5, iclass 28, count 0 2006.173.18:11:18.72#ibcon#about to read 6, iclass 28, count 0 2006.173.18:11:18.72#ibcon#read 6, iclass 28, count 0 2006.173.18:11:18.72#ibcon#end of sib2, iclass 28, count 0 2006.173.18:11:18.72#ibcon#*mode == 0, iclass 28, count 0 2006.173.18:11:18.72#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.18:11:18.72#ibcon#[27=BW32\r\n] 2006.173.18:11:18.72#ibcon#*before write, iclass 28, count 0 2006.173.18:11:18.72#ibcon#enter sib2, iclass 28, count 0 2006.173.18:11:18.72#ibcon#flushed, iclass 28, count 0 2006.173.18:11:18.72#ibcon#about to write, iclass 28, count 0 2006.173.18:11:18.72#ibcon#wrote, iclass 28, count 0 2006.173.18:11:18.72#ibcon#about to read 3, iclass 28, count 0 2006.173.18:11:18.75#ibcon#read 3, iclass 28, count 0 2006.173.18:11:18.75#ibcon#about to read 4, iclass 28, count 0 2006.173.18:11:18.75#ibcon#read 4, iclass 28, count 0 2006.173.18:11:18.75#ibcon#about to read 5, iclass 28, count 0 2006.173.18:11:18.75#ibcon#read 5, iclass 28, count 0 2006.173.18:11:18.75#ibcon#about to read 6, iclass 28, count 0 2006.173.18:11:18.75#ibcon#read 6, iclass 28, count 0 2006.173.18:11:18.75#ibcon#end of sib2, iclass 28, count 0 2006.173.18:11:18.75#ibcon#*after write, iclass 28, count 0 2006.173.18:11:18.75#ibcon#*before return 0, iclass 28, count 0 2006.173.18:11:18.75#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.18:11:18.75#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.18:11:18.75#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.18:11:18.75#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.18:11:18.75$setupk4/ifdk4 2006.173.18:11:18.75$ifdk4/lo= 2006.173.18:11:18.75$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.18:11:18.75$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.18:11:18.75$ifdk4/patch= 2006.173.18:11:18.75$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.18:11:18.75$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.18:11:18.75$setupk4/!*+20s 2006.173.18:11:22.38#abcon#<5=/14 0.9 2.3 20.001001002.2\r\n> 2006.173.18:11:22.40#abcon#{5=INTERFACE CLEAR} 2006.173.18:11:22.46#abcon#[5=S1D000X0/0*\r\n] 2006.173.18:11:32.55#abcon#<5=/14 0.9 2.3 19.991001002.2\r\n> 2006.173.18:11:32.57#abcon#{5=INTERFACE CLEAR} 2006.173.18:11:32.63#abcon#[5=S1D000X0/0*\r\n] 2006.173.18:11:33.27$setupk4/"tpicd 2006.173.18:11:33.27$setupk4/echo=off 2006.173.18:11:33.27$setupk4/xlog=off 2006.173.18:11:33.27:!2006.173.18:14:18 2006.173.18:11:35.14#trakl#Source acquired 2006.173.18:11:35.14#flagr#flagr/antenna,acquired 2006.173.18:14:18.00:preob 2006.173.18:14:18.13/onsource/TRACKING 2006.173.18:14:18.13:!2006.173.18:14:28 2006.173.18:14:28.00:"tape 2006.173.18:14:28.00:"st=record 2006.173.18:14:28.00:data_valid=on 2006.173.18:14:28.00:midob 2006.173.18:14:29.13/onsource/TRACKING 2006.173.18:14:29.13/wx/19.97,1002.2,100 2006.173.18:14:29.20/cable/+6.5120E-03 2006.173.18:14:30.29/va/01,07,usb,yes,37,40 2006.173.18:14:30.29/va/02,06,usb,yes,37,38 2006.173.18:14:30.29/va/03,05,usb,yes,47,49 2006.173.18:14:30.29/va/04,06,usb,yes,38,40 2006.173.18:14:30.29/va/05,04,usb,yes,30,30 2006.173.18:14:30.29/va/06,03,usb,yes,41,41 2006.173.18:14:30.29/va/07,04,usb,yes,34,35 2006.173.18:14:30.29/va/08,04,usb,yes,29,34 2006.173.18:14:30.52/valo/01,524.99,yes,locked 2006.173.18:14:30.52/valo/02,534.99,yes,locked 2006.173.18:14:30.52/valo/03,564.99,yes,locked 2006.173.18:14:30.52/valo/04,624.99,yes,locked 2006.173.18:14:30.52/valo/05,734.99,yes,locked 2006.173.18:14:30.52/valo/06,814.99,yes,locked 2006.173.18:14:30.52/valo/07,864.99,yes,locked 2006.173.18:14:30.52/valo/08,884.99,yes,locked 2006.173.18:14:31.61/vb/01,04,usb,yes,29,36 2006.173.18:14:31.61/vb/02,04,usb,yes,31,39 2006.173.18:14:31.61/vb/03,04,usb,yes,29,32 2006.173.18:14:31.61/vb/04,04,usb,yes,33,32 2006.173.18:14:31.61/vb/05,04,usb,yes,26,28 2006.173.18:14:31.61/vb/06,04,usb,yes,31,27 2006.173.18:14:31.61/vb/07,04,usb,yes,30,30 2006.173.18:14:31.61/vb/08,04,usb,yes,27,31 2006.173.18:14:31.84/vblo/01,629.99,yes,locked 2006.173.18:14:31.84/vblo/02,634.99,yes,locked 2006.173.18:14:31.84/vblo/03,649.99,yes,locked 2006.173.18:14:31.84/vblo/04,679.99,yes,locked 2006.173.18:14:31.84/vblo/05,709.99,yes,locked 2006.173.18:14:31.84/vblo/06,719.99,yes,locked 2006.173.18:14:31.84/vblo/07,734.99,yes,locked 2006.173.18:14:31.84/vblo/08,744.99,yes,locked 2006.173.18:14:31.99/vabw/8 2006.173.18:14:32.14/vbbw/8 2006.173.18:14:32.23/xfe/off,on,15.0 2006.173.18:14:32.61/ifatt/23,28,28,28 2006.173.18:14:33.07/fmout-gps/S +4.00E-07 2006.173.18:14:33.11:!2006.173.18:18:48 2006.173.18:18:48.01:data_valid=off 2006.173.18:18:48.01:"et 2006.173.18:18:48.01:!+3s 2006.173.18:18:51.02:"tape 2006.173.18:18:51.02:postob 2006.173.18:18:51.21/cable/+6.5134E-03 2006.173.18:18:51.21/wx/19.98,1002.2,100 2006.173.18:18:52.07/fmout-gps/S +4.00E-07 2006.173.18:18:52.07:scan_name=173-1819,jd0606,610 2006.173.18:18:52.07:source=1418+546,141946.60,542314.8,2000.0,ccw 2006.173.18:18:53.14#flagr#flagr/antenna,new-source 2006.173.18:18:53.14:checkk5 2006.173.18:18:53.52/chk_autoobs//k5ts1/ autoobs is running! 2006.173.18:18:53.92/chk_autoobs//k5ts2/ autoobs is running! 2006.173.18:18:54.34/chk_autoobs//k5ts3/ autoobs is running! 2006.173.18:18:54.73/chk_autoobs//k5ts4/ autoobs is running! 2006.173.18:18:55.13/chk_obsdata//k5ts1/T1731814??a.dat file size is correct (nominal:1040MB, actual:1036MB). 2006.173.18:18:55.52/chk_obsdata//k5ts2/T1731814??b.dat file size is correct (nominal:1040MB, actual:1036MB). 2006.173.18:18:55.90/chk_obsdata//k5ts3/T1731814??c.dat file size is correct (nominal:1040MB, actual:1036MB). 2006.173.18:18:56.33/chk_obsdata//k5ts4/T1731814??d.dat file size is correct (nominal:1040MB, actual:1036MB). 2006.173.18:18:57.04/k5log//k5ts1_log_newline 2006.173.18:18:57.73/k5log//k5ts2_log_newline 2006.173.18:18:58.45/k5log//k5ts3_log_newline 2006.173.18:18:59.16/k5log//k5ts4_log_newline 2006.173.18:18:59.18/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.18:18:59.18:setupk4=1 2006.173.18:18:59.18$setupk4/echo=on 2006.173.18:18:59.18$setupk4/pcalon 2006.173.18:18:59.18$pcalon/"no phase cal control is implemented here 2006.173.18:18:59.18$setupk4/"tpicd=stop 2006.173.18:18:59.18$setupk4/"rec=synch_on 2006.173.18:18:59.18$setupk4/"rec_mode=128 2006.173.18:18:59.18$setupk4/!* 2006.173.18:18:59.18$setupk4/recpk4 2006.173.18:18:59.18$recpk4/recpatch= 2006.173.18:18:59.19$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.18:18:59.19$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.18:18:59.19$setupk4/vck44 2006.173.18:18:59.19$vck44/valo=1,524.99 2006.173.18:18:59.19#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.18:18:59.19#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.18:18:59.19#ibcon#ireg 17 cls_cnt 0 2006.173.18:18:59.19#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.18:18:59.19#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.18:18:59.19#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.18:18:59.19#ibcon#enter wrdev, iclass 28, count 0 2006.173.18:18:59.19#ibcon#first serial, iclass 28, count 0 2006.173.18:18:59.19#ibcon#enter sib2, iclass 28, count 0 2006.173.18:18:59.19#ibcon#flushed, iclass 28, count 0 2006.173.18:18:59.19#ibcon#about to write, iclass 28, count 0 2006.173.18:18:59.19#ibcon#wrote, iclass 28, count 0 2006.173.18:18:59.19#ibcon#about to read 3, iclass 28, count 0 2006.173.18:18:59.21#ibcon#read 3, iclass 28, count 0 2006.173.18:18:59.21#ibcon#about to read 4, iclass 28, count 0 2006.173.18:18:59.21#ibcon#read 4, iclass 28, count 0 2006.173.18:18:59.21#ibcon#about to read 5, iclass 28, count 0 2006.173.18:18:59.21#ibcon#read 5, iclass 28, count 0 2006.173.18:18:59.21#ibcon#about to read 6, iclass 28, count 0 2006.173.18:18:59.21#ibcon#read 6, iclass 28, count 0 2006.173.18:18:59.21#ibcon#end of sib2, iclass 28, count 0 2006.173.18:18:59.21#ibcon#*mode == 0, iclass 28, count 0 2006.173.18:18:59.21#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.18:18:59.21#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.18:18:59.21#ibcon#*before write, iclass 28, count 0 2006.173.18:18:59.21#ibcon#enter sib2, iclass 28, count 0 2006.173.18:18:59.21#ibcon#flushed, iclass 28, count 0 2006.173.18:18:59.21#ibcon#about to write, iclass 28, count 0 2006.173.18:18:59.21#ibcon#wrote, iclass 28, count 0 2006.173.18:18:59.21#ibcon#about to read 3, iclass 28, count 0 2006.173.18:18:59.26#ibcon#read 3, iclass 28, count 0 2006.173.18:18:59.26#ibcon#about to read 4, iclass 28, count 0 2006.173.18:18:59.26#ibcon#read 4, iclass 28, count 0 2006.173.18:18:59.26#ibcon#about to read 5, iclass 28, count 0 2006.173.18:18:59.26#ibcon#read 5, iclass 28, count 0 2006.173.18:18:59.26#ibcon#about to read 6, iclass 28, count 0 2006.173.18:18:59.26#ibcon#read 6, iclass 28, count 0 2006.173.18:18:59.26#ibcon#end of sib2, iclass 28, count 0 2006.173.18:18:59.26#ibcon#*after write, iclass 28, count 0 2006.173.18:18:59.26#ibcon#*before return 0, iclass 28, count 0 2006.173.18:18:59.26#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.18:18:59.26#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.18:18:59.26#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.18:18:59.26#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.18:18:59.26$vck44/va=1,7 2006.173.18:18:59.26#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.18:18:59.26#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.18:18:59.26#ibcon#ireg 11 cls_cnt 2 2006.173.18:18:59.26#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.18:18:59.26#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.18:18:59.26#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.18:18:59.26#ibcon#enter wrdev, iclass 30, count 2 2006.173.18:18:59.26#ibcon#first serial, iclass 30, count 2 2006.173.18:18:59.26#ibcon#enter sib2, iclass 30, count 2 2006.173.18:18:59.26#ibcon#flushed, iclass 30, count 2 2006.173.18:18:59.26#ibcon#about to write, iclass 30, count 2 2006.173.18:18:59.26#ibcon#wrote, iclass 30, count 2 2006.173.18:18:59.26#ibcon#about to read 3, iclass 30, count 2 2006.173.18:18:59.28#ibcon#read 3, iclass 30, count 2 2006.173.18:18:59.28#ibcon#about to read 4, iclass 30, count 2 2006.173.18:18:59.28#ibcon#read 4, iclass 30, count 2 2006.173.18:18:59.28#ibcon#about to read 5, iclass 30, count 2 2006.173.18:18:59.28#ibcon#read 5, iclass 30, count 2 2006.173.18:18:59.28#ibcon#about to read 6, iclass 30, count 2 2006.173.18:18:59.28#ibcon#read 6, iclass 30, count 2 2006.173.18:18:59.28#ibcon#end of sib2, iclass 30, count 2 2006.173.18:18:59.28#ibcon#*mode == 0, iclass 30, count 2 2006.173.18:18:59.28#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.18:18:59.28#ibcon#[25=AT01-07\r\n] 2006.173.18:18:59.28#ibcon#*before write, iclass 30, count 2 2006.173.18:18:59.28#ibcon#enter sib2, iclass 30, count 2 2006.173.18:18:59.28#ibcon#flushed, iclass 30, count 2 2006.173.18:18:59.28#ibcon#about to write, iclass 30, count 2 2006.173.18:18:59.28#ibcon#wrote, iclass 30, count 2 2006.173.18:18:59.28#ibcon#about to read 3, iclass 30, count 2 2006.173.18:18:59.31#ibcon#read 3, iclass 30, count 2 2006.173.18:18:59.31#ibcon#about to read 4, iclass 30, count 2 2006.173.18:18:59.31#ibcon#read 4, iclass 30, count 2 2006.173.18:18:59.31#ibcon#about to read 5, iclass 30, count 2 2006.173.18:18:59.31#ibcon#read 5, iclass 30, count 2 2006.173.18:18:59.31#ibcon#about to read 6, iclass 30, count 2 2006.173.18:18:59.31#ibcon#read 6, iclass 30, count 2 2006.173.18:18:59.31#ibcon#end of sib2, iclass 30, count 2 2006.173.18:18:59.31#ibcon#*after write, iclass 30, count 2 2006.173.18:18:59.31#ibcon#*before return 0, iclass 30, count 2 2006.173.18:18:59.31#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.18:18:59.31#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.18:18:59.31#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.18:18:59.31#ibcon#ireg 7 cls_cnt 0 2006.173.18:18:59.31#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.18:18:59.43#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.18:18:59.43#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.18:18:59.43#ibcon#enter wrdev, iclass 30, count 0 2006.173.18:18:59.43#ibcon#first serial, iclass 30, count 0 2006.173.18:18:59.43#ibcon#enter sib2, iclass 30, count 0 2006.173.18:18:59.43#ibcon#flushed, iclass 30, count 0 2006.173.18:18:59.43#ibcon#about to write, iclass 30, count 0 2006.173.18:18:59.43#ibcon#wrote, iclass 30, count 0 2006.173.18:18:59.43#ibcon#about to read 3, iclass 30, count 0 2006.173.18:18:59.45#ibcon#read 3, iclass 30, count 0 2006.173.18:18:59.45#ibcon#about to read 4, iclass 30, count 0 2006.173.18:18:59.45#ibcon#read 4, iclass 30, count 0 2006.173.18:18:59.45#ibcon#about to read 5, iclass 30, count 0 2006.173.18:18:59.45#ibcon#read 5, iclass 30, count 0 2006.173.18:18:59.45#ibcon#about to read 6, iclass 30, count 0 2006.173.18:18:59.45#ibcon#read 6, iclass 30, count 0 2006.173.18:18:59.45#ibcon#end of sib2, iclass 30, count 0 2006.173.18:18:59.45#ibcon#*mode == 0, iclass 30, count 0 2006.173.18:18:59.45#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.18:18:59.45#ibcon#[25=USB\r\n] 2006.173.18:18:59.45#ibcon#*before write, iclass 30, count 0 2006.173.18:18:59.45#ibcon#enter sib2, iclass 30, count 0 2006.173.18:18:59.45#ibcon#flushed, iclass 30, count 0 2006.173.18:18:59.45#ibcon#about to write, iclass 30, count 0 2006.173.18:18:59.45#ibcon#wrote, iclass 30, count 0 2006.173.18:18:59.45#ibcon#about to read 3, iclass 30, count 0 2006.173.18:18:59.48#ibcon#read 3, iclass 30, count 0 2006.173.18:18:59.48#ibcon#about to read 4, iclass 30, count 0 2006.173.18:18:59.48#ibcon#read 4, iclass 30, count 0 2006.173.18:18:59.48#ibcon#about to read 5, iclass 30, count 0 2006.173.18:18:59.48#ibcon#read 5, iclass 30, count 0 2006.173.18:18:59.48#ibcon#about to read 6, iclass 30, count 0 2006.173.18:18:59.48#ibcon#read 6, iclass 30, count 0 2006.173.18:18:59.48#ibcon#end of sib2, iclass 30, count 0 2006.173.18:18:59.48#ibcon#*after write, iclass 30, count 0 2006.173.18:18:59.48#ibcon#*before return 0, iclass 30, count 0 2006.173.18:18:59.48#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.18:18:59.48#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.18:18:59.48#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.18:18:59.48#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.18:18:59.48$vck44/valo=2,534.99 2006.173.18:18:59.48#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.18:18:59.48#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.18:18:59.48#ibcon#ireg 17 cls_cnt 0 2006.173.18:18:59.48#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.18:18:59.48#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.18:18:59.48#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.18:18:59.48#ibcon#enter wrdev, iclass 32, count 0 2006.173.18:18:59.48#ibcon#first serial, iclass 32, count 0 2006.173.18:18:59.48#ibcon#enter sib2, iclass 32, count 0 2006.173.18:18:59.48#ibcon#flushed, iclass 32, count 0 2006.173.18:18:59.48#ibcon#about to write, iclass 32, count 0 2006.173.18:18:59.48#ibcon#wrote, iclass 32, count 0 2006.173.18:18:59.48#ibcon#about to read 3, iclass 32, count 0 2006.173.18:18:59.50#ibcon#read 3, iclass 32, count 0 2006.173.18:18:59.50#ibcon#about to read 4, iclass 32, count 0 2006.173.18:18:59.50#ibcon#read 4, iclass 32, count 0 2006.173.18:18:59.50#ibcon#about to read 5, iclass 32, count 0 2006.173.18:18:59.50#ibcon#read 5, iclass 32, count 0 2006.173.18:18:59.50#ibcon#about to read 6, iclass 32, count 0 2006.173.18:18:59.50#ibcon#read 6, iclass 32, count 0 2006.173.18:18:59.50#ibcon#end of sib2, iclass 32, count 0 2006.173.18:18:59.50#ibcon#*mode == 0, iclass 32, count 0 2006.173.18:18:59.50#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.18:18:59.50#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.18:18:59.50#ibcon#*before write, iclass 32, count 0 2006.173.18:18:59.50#ibcon#enter sib2, iclass 32, count 0 2006.173.18:18:59.50#ibcon#flushed, iclass 32, count 0 2006.173.18:18:59.50#ibcon#about to write, iclass 32, count 0 2006.173.18:18:59.50#ibcon#wrote, iclass 32, count 0 2006.173.18:18:59.50#ibcon#about to read 3, iclass 32, count 0 2006.173.18:18:59.54#ibcon#read 3, iclass 32, count 0 2006.173.18:18:59.54#ibcon#about to read 4, iclass 32, count 0 2006.173.18:18:59.54#ibcon#read 4, iclass 32, count 0 2006.173.18:18:59.54#ibcon#about to read 5, iclass 32, count 0 2006.173.18:18:59.54#ibcon#read 5, iclass 32, count 0 2006.173.18:18:59.54#ibcon#about to read 6, iclass 32, count 0 2006.173.18:18:59.54#ibcon#read 6, iclass 32, count 0 2006.173.18:18:59.54#ibcon#end of sib2, iclass 32, count 0 2006.173.18:18:59.54#ibcon#*after write, iclass 32, count 0 2006.173.18:18:59.54#ibcon#*before return 0, iclass 32, count 0 2006.173.18:18:59.54#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.18:18:59.54#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.18:18:59.54#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.18:18:59.54#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.18:18:59.54$vck44/va=2,6 2006.173.18:18:59.54#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.18:18:59.54#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.18:18:59.54#ibcon#ireg 11 cls_cnt 2 2006.173.18:18:59.54#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.18:18:59.60#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.18:18:59.60#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.18:18:59.60#ibcon#enter wrdev, iclass 34, count 2 2006.173.18:18:59.60#ibcon#first serial, iclass 34, count 2 2006.173.18:18:59.60#ibcon#enter sib2, iclass 34, count 2 2006.173.18:18:59.60#ibcon#flushed, iclass 34, count 2 2006.173.18:18:59.60#ibcon#about to write, iclass 34, count 2 2006.173.18:18:59.60#ibcon#wrote, iclass 34, count 2 2006.173.18:18:59.60#ibcon#about to read 3, iclass 34, count 2 2006.173.18:18:59.62#ibcon#read 3, iclass 34, count 2 2006.173.18:18:59.62#ibcon#about to read 4, iclass 34, count 2 2006.173.18:18:59.62#ibcon#read 4, iclass 34, count 2 2006.173.18:18:59.62#ibcon#about to read 5, iclass 34, count 2 2006.173.18:18:59.62#ibcon#read 5, iclass 34, count 2 2006.173.18:18:59.62#ibcon#about to read 6, iclass 34, count 2 2006.173.18:18:59.62#ibcon#read 6, iclass 34, count 2 2006.173.18:18:59.62#ibcon#end of sib2, iclass 34, count 2 2006.173.18:18:59.62#ibcon#*mode == 0, iclass 34, count 2 2006.173.18:18:59.62#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.18:18:59.62#ibcon#[25=AT02-06\r\n] 2006.173.18:18:59.62#ibcon#*before write, iclass 34, count 2 2006.173.18:18:59.62#ibcon#enter sib2, iclass 34, count 2 2006.173.18:18:59.62#ibcon#flushed, iclass 34, count 2 2006.173.18:18:59.62#ibcon#about to write, iclass 34, count 2 2006.173.18:18:59.62#ibcon#wrote, iclass 34, count 2 2006.173.18:18:59.62#ibcon#about to read 3, iclass 34, count 2 2006.173.18:18:59.65#ibcon#read 3, iclass 34, count 2 2006.173.18:18:59.65#ibcon#about to read 4, iclass 34, count 2 2006.173.18:18:59.65#ibcon#read 4, iclass 34, count 2 2006.173.18:18:59.65#ibcon#about to read 5, iclass 34, count 2 2006.173.18:18:59.65#ibcon#read 5, iclass 34, count 2 2006.173.18:18:59.65#ibcon#about to read 6, iclass 34, count 2 2006.173.18:18:59.65#ibcon#read 6, iclass 34, count 2 2006.173.18:18:59.65#ibcon#end of sib2, iclass 34, count 2 2006.173.18:18:59.65#ibcon#*after write, iclass 34, count 2 2006.173.18:18:59.65#ibcon#*before return 0, iclass 34, count 2 2006.173.18:18:59.65#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.18:18:59.65#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.18:18:59.65#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.18:18:59.65#ibcon#ireg 7 cls_cnt 0 2006.173.18:18:59.65#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.18:18:59.77#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.18:18:59.77#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.18:18:59.77#ibcon#enter wrdev, iclass 34, count 0 2006.173.18:18:59.77#ibcon#first serial, iclass 34, count 0 2006.173.18:18:59.77#ibcon#enter sib2, iclass 34, count 0 2006.173.18:18:59.77#ibcon#flushed, iclass 34, count 0 2006.173.18:18:59.77#ibcon#about to write, iclass 34, count 0 2006.173.18:18:59.77#ibcon#wrote, iclass 34, count 0 2006.173.18:18:59.77#ibcon#about to read 3, iclass 34, count 0 2006.173.18:18:59.79#ibcon#read 3, iclass 34, count 0 2006.173.18:18:59.79#ibcon#about to read 4, iclass 34, count 0 2006.173.18:18:59.79#ibcon#read 4, iclass 34, count 0 2006.173.18:18:59.79#ibcon#about to read 5, iclass 34, count 0 2006.173.18:18:59.79#ibcon#read 5, iclass 34, count 0 2006.173.18:18:59.79#ibcon#about to read 6, iclass 34, count 0 2006.173.18:18:59.79#ibcon#read 6, iclass 34, count 0 2006.173.18:18:59.79#ibcon#end of sib2, iclass 34, count 0 2006.173.18:18:59.79#ibcon#*mode == 0, iclass 34, count 0 2006.173.18:18:59.79#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.18:18:59.79#ibcon#[25=USB\r\n] 2006.173.18:18:59.79#ibcon#*before write, iclass 34, count 0 2006.173.18:18:59.79#ibcon#enter sib2, iclass 34, count 0 2006.173.18:18:59.79#ibcon#flushed, iclass 34, count 0 2006.173.18:18:59.79#ibcon#about to write, iclass 34, count 0 2006.173.18:18:59.79#ibcon#wrote, iclass 34, count 0 2006.173.18:18:59.79#ibcon#about to read 3, iclass 34, count 0 2006.173.18:18:59.82#ibcon#read 3, iclass 34, count 0 2006.173.18:18:59.82#ibcon#about to read 4, iclass 34, count 0 2006.173.18:18:59.82#ibcon#read 4, iclass 34, count 0 2006.173.18:18:59.82#ibcon#about to read 5, iclass 34, count 0 2006.173.18:18:59.82#ibcon#read 5, iclass 34, count 0 2006.173.18:18:59.82#ibcon#about to read 6, iclass 34, count 0 2006.173.18:18:59.82#ibcon#read 6, iclass 34, count 0 2006.173.18:18:59.82#ibcon#end of sib2, iclass 34, count 0 2006.173.18:18:59.82#ibcon#*after write, iclass 34, count 0 2006.173.18:18:59.82#ibcon#*before return 0, iclass 34, count 0 2006.173.18:18:59.82#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.18:18:59.82#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.18:18:59.82#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.18:18:59.82#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.18:18:59.82$vck44/valo=3,564.99 2006.173.18:18:59.82#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.18:18:59.82#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.18:18:59.82#ibcon#ireg 17 cls_cnt 0 2006.173.18:18:59.82#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.18:18:59.82#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.18:18:59.82#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.18:18:59.82#ibcon#enter wrdev, iclass 36, count 0 2006.173.18:18:59.82#ibcon#first serial, iclass 36, count 0 2006.173.18:18:59.82#ibcon#enter sib2, iclass 36, count 0 2006.173.18:18:59.82#ibcon#flushed, iclass 36, count 0 2006.173.18:18:59.82#ibcon#about to write, iclass 36, count 0 2006.173.18:18:59.82#ibcon#wrote, iclass 36, count 0 2006.173.18:18:59.82#ibcon#about to read 3, iclass 36, count 0 2006.173.18:18:59.84#ibcon#read 3, iclass 36, count 0 2006.173.18:18:59.84#ibcon#about to read 4, iclass 36, count 0 2006.173.18:18:59.84#ibcon#read 4, iclass 36, count 0 2006.173.18:18:59.84#ibcon#about to read 5, iclass 36, count 0 2006.173.18:18:59.84#ibcon#read 5, iclass 36, count 0 2006.173.18:18:59.84#ibcon#about to read 6, iclass 36, count 0 2006.173.18:18:59.84#ibcon#read 6, iclass 36, count 0 2006.173.18:18:59.84#ibcon#end of sib2, iclass 36, count 0 2006.173.18:18:59.84#ibcon#*mode == 0, iclass 36, count 0 2006.173.18:18:59.84#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.18:18:59.84#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.18:18:59.84#ibcon#*before write, iclass 36, count 0 2006.173.18:18:59.84#ibcon#enter sib2, iclass 36, count 0 2006.173.18:18:59.84#ibcon#flushed, iclass 36, count 0 2006.173.18:18:59.84#ibcon#about to write, iclass 36, count 0 2006.173.18:18:59.84#ibcon#wrote, iclass 36, count 0 2006.173.18:18:59.84#ibcon#about to read 3, iclass 36, count 0 2006.173.18:18:59.88#ibcon#read 3, iclass 36, count 0 2006.173.18:18:59.88#ibcon#about to read 4, iclass 36, count 0 2006.173.18:18:59.88#ibcon#read 4, iclass 36, count 0 2006.173.18:18:59.88#ibcon#about to read 5, iclass 36, count 0 2006.173.18:18:59.88#ibcon#read 5, iclass 36, count 0 2006.173.18:18:59.88#ibcon#about to read 6, iclass 36, count 0 2006.173.18:18:59.88#ibcon#read 6, iclass 36, count 0 2006.173.18:18:59.88#ibcon#end of sib2, iclass 36, count 0 2006.173.18:18:59.88#ibcon#*after write, iclass 36, count 0 2006.173.18:18:59.88#ibcon#*before return 0, iclass 36, count 0 2006.173.18:18:59.88#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.18:18:59.88#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.18:18:59.88#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.18:18:59.88#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.18:18:59.88$vck44/va=3,5 2006.173.18:18:59.88#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.18:18:59.88#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.18:18:59.88#ibcon#ireg 11 cls_cnt 2 2006.173.18:18:59.88#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.18:18:59.94#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.18:18:59.94#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.18:18:59.94#ibcon#enter wrdev, iclass 38, count 2 2006.173.18:18:59.94#ibcon#first serial, iclass 38, count 2 2006.173.18:18:59.94#ibcon#enter sib2, iclass 38, count 2 2006.173.18:18:59.94#ibcon#flushed, iclass 38, count 2 2006.173.18:18:59.94#ibcon#about to write, iclass 38, count 2 2006.173.18:18:59.94#ibcon#wrote, iclass 38, count 2 2006.173.18:18:59.94#ibcon#about to read 3, iclass 38, count 2 2006.173.18:18:59.96#ibcon#read 3, iclass 38, count 2 2006.173.18:18:59.96#ibcon#about to read 4, iclass 38, count 2 2006.173.18:18:59.96#ibcon#read 4, iclass 38, count 2 2006.173.18:18:59.96#ibcon#about to read 5, iclass 38, count 2 2006.173.18:18:59.96#ibcon#read 5, iclass 38, count 2 2006.173.18:18:59.96#ibcon#about to read 6, iclass 38, count 2 2006.173.18:18:59.96#ibcon#read 6, iclass 38, count 2 2006.173.18:18:59.96#ibcon#end of sib2, iclass 38, count 2 2006.173.18:18:59.96#ibcon#*mode == 0, iclass 38, count 2 2006.173.18:18:59.96#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.18:18:59.96#ibcon#[25=AT03-05\r\n] 2006.173.18:18:59.96#ibcon#*before write, iclass 38, count 2 2006.173.18:18:59.96#ibcon#enter sib2, iclass 38, count 2 2006.173.18:18:59.96#ibcon#flushed, iclass 38, count 2 2006.173.18:18:59.96#ibcon#about to write, iclass 38, count 2 2006.173.18:18:59.96#ibcon#wrote, iclass 38, count 2 2006.173.18:18:59.96#ibcon#about to read 3, iclass 38, count 2 2006.173.18:18:59.99#ibcon#read 3, iclass 38, count 2 2006.173.18:18:59.99#ibcon#about to read 4, iclass 38, count 2 2006.173.18:18:59.99#ibcon#read 4, iclass 38, count 2 2006.173.18:18:59.99#ibcon#about to read 5, iclass 38, count 2 2006.173.18:18:59.99#ibcon#read 5, iclass 38, count 2 2006.173.18:18:59.99#ibcon#about to read 6, iclass 38, count 2 2006.173.18:18:59.99#ibcon#read 6, iclass 38, count 2 2006.173.18:18:59.99#ibcon#end of sib2, iclass 38, count 2 2006.173.18:18:59.99#ibcon#*after write, iclass 38, count 2 2006.173.18:18:59.99#ibcon#*before return 0, iclass 38, count 2 2006.173.18:18:59.99#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.18:18:59.99#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.18:18:59.99#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.18:18:59.99#ibcon#ireg 7 cls_cnt 0 2006.173.18:18:59.99#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.18:19:00.11#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.18:19:00.11#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.18:19:00.11#ibcon#enter wrdev, iclass 38, count 0 2006.173.18:19:00.11#ibcon#first serial, iclass 38, count 0 2006.173.18:19:00.11#ibcon#enter sib2, iclass 38, count 0 2006.173.18:19:00.11#ibcon#flushed, iclass 38, count 0 2006.173.18:19:00.11#ibcon#about to write, iclass 38, count 0 2006.173.18:19:00.11#ibcon#wrote, iclass 38, count 0 2006.173.18:19:00.11#ibcon#about to read 3, iclass 38, count 0 2006.173.18:19:00.13#ibcon#read 3, iclass 38, count 0 2006.173.18:19:00.13#ibcon#about to read 4, iclass 38, count 0 2006.173.18:19:00.13#ibcon#read 4, iclass 38, count 0 2006.173.18:19:00.13#ibcon#about to read 5, iclass 38, count 0 2006.173.18:19:00.13#ibcon#read 5, iclass 38, count 0 2006.173.18:19:00.13#ibcon#about to read 6, iclass 38, count 0 2006.173.18:19:00.13#ibcon#read 6, iclass 38, count 0 2006.173.18:19:00.13#ibcon#end of sib2, iclass 38, count 0 2006.173.18:19:00.13#ibcon#*mode == 0, iclass 38, count 0 2006.173.18:19:00.13#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.18:19:00.13#ibcon#[25=USB\r\n] 2006.173.18:19:00.13#ibcon#*before write, iclass 38, count 0 2006.173.18:19:00.13#ibcon#enter sib2, iclass 38, count 0 2006.173.18:19:00.13#ibcon#flushed, iclass 38, count 0 2006.173.18:19:00.13#ibcon#about to write, iclass 38, count 0 2006.173.18:19:00.13#ibcon#wrote, iclass 38, count 0 2006.173.18:19:00.13#ibcon#about to read 3, iclass 38, count 0 2006.173.18:19:00.16#ibcon#read 3, iclass 38, count 0 2006.173.18:19:00.16#ibcon#about to read 4, iclass 38, count 0 2006.173.18:19:00.16#ibcon#read 4, iclass 38, count 0 2006.173.18:19:00.16#ibcon#about to read 5, iclass 38, count 0 2006.173.18:19:00.16#ibcon#read 5, iclass 38, count 0 2006.173.18:19:00.16#ibcon#about to read 6, iclass 38, count 0 2006.173.18:19:00.16#ibcon#read 6, iclass 38, count 0 2006.173.18:19:00.16#ibcon#end of sib2, iclass 38, count 0 2006.173.18:19:00.16#ibcon#*after write, iclass 38, count 0 2006.173.18:19:00.16#ibcon#*before return 0, iclass 38, count 0 2006.173.18:19:00.16#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.18:19:00.16#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.18:19:00.16#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.18:19:00.16#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.18:19:00.16$vck44/valo=4,624.99 2006.173.18:19:00.16#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.18:19:00.16#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.18:19:00.16#ibcon#ireg 17 cls_cnt 0 2006.173.18:19:00.16#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.18:19:00.16#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.18:19:00.16#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.18:19:00.16#ibcon#enter wrdev, iclass 40, count 0 2006.173.18:19:00.16#ibcon#first serial, iclass 40, count 0 2006.173.18:19:00.16#ibcon#enter sib2, iclass 40, count 0 2006.173.18:19:00.16#ibcon#flushed, iclass 40, count 0 2006.173.18:19:00.16#ibcon#about to write, iclass 40, count 0 2006.173.18:19:00.16#ibcon#wrote, iclass 40, count 0 2006.173.18:19:00.16#ibcon#about to read 3, iclass 40, count 0 2006.173.18:19:00.18#ibcon#read 3, iclass 40, count 0 2006.173.18:19:00.18#ibcon#about to read 4, iclass 40, count 0 2006.173.18:19:00.18#ibcon#read 4, iclass 40, count 0 2006.173.18:19:00.18#ibcon#about to read 5, iclass 40, count 0 2006.173.18:19:00.18#ibcon#read 5, iclass 40, count 0 2006.173.18:19:00.18#ibcon#about to read 6, iclass 40, count 0 2006.173.18:19:00.18#ibcon#read 6, iclass 40, count 0 2006.173.18:19:00.18#ibcon#end of sib2, iclass 40, count 0 2006.173.18:19:00.18#ibcon#*mode == 0, iclass 40, count 0 2006.173.18:19:00.18#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.18:19:00.18#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.18:19:00.18#ibcon#*before write, iclass 40, count 0 2006.173.18:19:00.18#ibcon#enter sib2, iclass 40, count 0 2006.173.18:19:00.18#ibcon#flushed, iclass 40, count 0 2006.173.18:19:00.18#ibcon#about to write, iclass 40, count 0 2006.173.18:19:00.18#ibcon#wrote, iclass 40, count 0 2006.173.18:19:00.18#ibcon#about to read 3, iclass 40, count 0 2006.173.18:19:00.22#ibcon#read 3, iclass 40, count 0 2006.173.18:19:00.22#ibcon#about to read 4, iclass 40, count 0 2006.173.18:19:00.22#ibcon#read 4, iclass 40, count 0 2006.173.18:19:00.22#ibcon#about to read 5, iclass 40, count 0 2006.173.18:19:00.22#ibcon#read 5, iclass 40, count 0 2006.173.18:19:00.22#ibcon#about to read 6, iclass 40, count 0 2006.173.18:19:00.22#ibcon#read 6, iclass 40, count 0 2006.173.18:19:00.22#ibcon#end of sib2, iclass 40, count 0 2006.173.18:19:00.22#ibcon#*after write, iclass 40, count 0 2006.173.18:19:00.22#ibcon#*before return 0, iclass 40, count 0 2006.173.18:19:00.22#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.18:19:00.22#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.18:19:00.22#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.18:19:00.22#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.18:19:00.22$vck44/va=4,6 2006.173.18:19:00.22#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.18:19:00.22#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.18:19:00.22#ibcon#ireg 11 cls_cnt 2 2006.173.18:19:00.22#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.18:19:00.28#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.18:19:00.28#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.18:19:00.28#ibcon#enter wrdev, iclass 4, count 2 2006.173.18:19:00.28#ibcon#first serial, iclass 4, count 2 2006.173.18:19:00.28#ibcon#enter sib2, iclass 4, count 2 2006.173.18:19:00.28#ibcon#flushed, iclass 4, count 2 2006.173.18:19:00.28#ibcon#about to write, iclass 4, count 2 2006.173.18:19:00.28#ibcon#wrote, iclass 4, count 2 2006.173.18:19:00.28#ibcon#about to read 3, iclass 4, count 2 2006.173.18:19:00.30#ibcon#read 3, iclass 4, count 2 2006.173.18:19:00.30#ibcon#about to read 4, iclass 4, count 2 2006.173.18:19:00.30#ibcon#read 4, iclass 4, count 2 2006.173.18:19:00.30#ibcon#about to read 5, iclass 4, count 2 2006.173.18:19:00.30#ibcon#read 5, iclass 4, count 2 2006.173.18:19:00.30#ibcon#about to read 6, iclass 4, count 2 2006.173.18:19:00.30#ibcon#read 6, iclass 4, count 2 2006.173.18:19:00.30#ibcon#end of sib2, iclass 4, count 2 2006.173.18:19:00.30#ibcon#*mode == 0, iclass 4, count 2 2006.173.18:19:00.30#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.18:19:00.30#ibcon#[25=AT04-06\r\n] 2006.173.18:19:00.30#ibcon#*before write, iclass 4, count 2 2006.173.18:19:00.30#ibcon#enter sib2, iclass 4, count 2 2006.173.18:19:00.30#ibcon#flushed, iclass 4, count 2 2006.173.18:19:00.30#ibcon#about to write, iclass 4, count 2 2006.173.18:19:00.30#ibcon#wrote, iclass 4, count 2 2006.173.18:19:00.30#ibcon#about to read 3, iclass 4, count 2 2006.173.18:19:00.33#ibcon#read 3, iclass 4, count 2 2006.173.18:19:00.33#ibcon#about to read 4, iclass 4, count 2 2006.173.18:19:00.33#ibcon#read 4, iclass 4, count 2 2006.173.18:19:00.33#ibcon#about to read 5, iclass 4, count 2 2006.173.18:19:00.33#ibcon#read 5, iclass 4, count 2 2006.173.18:19:00.33#ibcon#about to read 6, iclass 4, count 2 2006.173.18:19:00.33#ibcon#read 6, iclass 4, count 2 2006.173.18:19:00.33#ibcon#end of sib2, iclass 4, count 2 2006.173.18:19:00.33#ibcon#*after write, iclass 4, count 2 2006.173.18:19:00.33#ibcon#*before return 0, iclass 4, count 2 2006.173.18:19:00.33#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.18:19:00.33#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.18:19:00.33#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.18:19:00.33#ibcon#ireg 7 cls_cnt 0 2006.173.18:19:00.33#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.18:19:00.45#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.18:19:00.45#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.18:19:00.45#ibcon#enter wrdev, iclass 4, count 0 2006.173.18:19:00.45#ibcon#first serial, iclass 4, count 0 2006.173.18:19:00.45#ibcon#enter sib2, iclass 4, count 0 2006.173.18:19:00.45#ibcon#flushed, iclass 4, count 0 2006.173.18:19:00.45#ibcon#about to write, iclass 4, count 0 2006.173.18:19:00.45#ibcon#wrote, iclass 4, count 0 2006.173.18:19:00.45#ibcon#about to read 3, iclass 4, count 0 2006.173.18:19:00.47#ibcon#read 3, iclass 4, count 0 2006.173.18:19:00.47#ibcon#about to read 4, iclass 4, count 0 2006.173.18:19:00.47#ibcon#read 4, iclass 4, count 0 2006.173.18:19:00.47#ibcon#about to read 5, iclass 4, count 0 2006.173.18:19:00.47#ibcon#read 5, iclass 4, count 0 2006.173.18:19:00.47#ibcon#about to read 6, iclass 4, count 0 2006.173.18:19:00.47#ibcon#read 6, iclass 4, count 0 2006.173.18:19:00.47#ibcon#end of sib2, iclass 4, count 0 2006.173.18:19:00.47#ibcon#*mode == 0, iclass 4, count 0 2006.173.18:19:00.47#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.18:19:00.47#ibcon#[25=USB\r\n] 2006.173.18:19:00.47#ibcon#*before write, iclass 4, count 0 2006.173.18:19:00.47#ibcon#enter sib2, iclass 4, count 0 2006.173.18:19:00.47#ibcon#flushed, iclass 4, count 0 2006.173.18:19:00.47#ibcon#about to write, iclass 4, count 0 2006.173.18:19:00.47#ibcon#wrote, iclass 4, count 0 2006.173.18:19:00.47#ibcon#about to read 3, iclass 4, count 0 2006.173.18:19:00.50#ibcon#read 3, iclass 4, count 0 2006.173.18:19:00.50#ibcon#about to read 4, iclass 4, count 0 2006.173.18:19:00.50#ibcon#read 4, iclass 4, count 0 2006.173.18:19:00.50#ibcon#about to read 5, iclass 4, count 0 2006.173.18:19:00.50#ibcon#read 5, iclass 4, count 0 2006.173.18:19:00.50#ibcon#about to read 6, iclass 4, count 0 2006.173.18:19:00.50#ibcon#read 6, iclass 4, count 0 2006.173.18:19:00.50#ibcon#end of sib2, iclass 4, count 0 2006.173.18:19:00.50#ibcon#*after write, iclass 4, count 0 2006.173.18:19:00.50#ibcon#*before return 0, iclass 4, count 0 2006.173.18:19:00.50#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.18:19:00.50#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.18:19:00.50#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.18:19:00.50#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.18:19:00.50$vck44/valo=5,734.99 2006.173.18:19:00.50#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.18:19:00.50#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.18:19:00.50#ibcon#ireg 17 cls_cnt 0 2006.173.18:19:00.50#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.18:19:00.50#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.18:19:00.50#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.18:19:00.50#ibcon#enter wrdev, iclass 6, count 0 2006.173.18:19:00.50#ibcon#first serial, iclass 6, count 0 2006.173.18:19:00.50#ibcon#enter sib2, iclass 6, count 0 2006.173.18:19:00.50#ibcon#flushed, iclass 6, count 0 2006.173.18:19:00.50#ibcon#about to write, iclass 6, count 0 2006.173.18:19:00.50#ibcon#wrote, iclass 6, count 0 2006.173.18:19:00.50#ibcon#about to read 3, iclass 6, count 0 2006.173.18:19:00.52#ibcon#read 3, iclass 6, count 0 2006.173.18:19:00.52#ibcon#about to read 4, iclass 6, count 0 2006.173.18:19:00.52#ibcon#read 4, iclass 6, count 0 2006.173.18:19:00.52#ibcon#about to read 5, iclass 6, count 0 2006.173.18:19:00.52#ibcon#read 5, iclass 6, count 0 2006.173.18:19:00.52#ibcon#about to read 6, iclass 6, count 0 2006.173.18:19:00.52#ibcon#read 6, iclass 6, count 0 2006.173.18:19:00.52#ibcon#end of sib2, iclass 6, count 0 2006.173.18:19:00.52#ibcon#*mode == 0, iclass 6, count 0 2006.173.18:19:00.52#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.18:19:00.52#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.18:19:00.52#ibcon#*before write, iclass 6, count 0 2006.173.18:19:00.52#ibcon#enter sib2, iclass 6, count 0 2006.173.18:19:00.52#ibcon#flushed, iclass 6, count 0 2006.173.18:19:00.52#ibcon#about to write, iclass 6, count 0 2006.173.18:19:00.52#ibcon#wrote, iclass 6, count 0 2006.173.18:19:00.52#ibcon#about to read 3, iclass 6, count 0 2006.173.18:19:00.56#ibcon#read 3, iclass 6, count 0 2006.173.18:19:00.56#ibcon#about to read 4, iclass 6, count 0 2006.173.18:19:00.56#ibcon#read 4, iclass 6, count 0 2006.173.18:19:00.56#ibcon#about to read 5, iclass 6, count 0 2006.173.18:19:00.56#ibcon#read 5, iclass 6, count 0 2006.173.18:19:00.56#ibcon#about to read 6, iclass 6, count 0 2006.173.18:19:00.56#ibcon#read 6, iclass 6, count 0 2006.173.18:19:00.56#ibcon#end of sib2, iclass 6, count 0 2006.173.18:19:00.56#ibcon#*after write, iclass 6, count 0 2006.173.18:19:00.56#ibcon#*before return 0, iclass 6, count 0 2006.173.18:19:00.56#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.18:19:00.56#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.18:19:00.56#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.18:19:00.56#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.18:19:00.56$vck44/va=5,4 2006.173.18:19:00.56#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.18:19:00.56#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.18:19:00.56#ibcon#ireg 11 cls_cnt 2 2006.173.18:19:00.56#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.18:19:00.62#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.18:19:00.62#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.18:19:00.62#ibcon#enter wrdev, iclass 10, count 2 2006.173.18:19:00.62#ibcon#first serial, iclass 10, count 2 2006.173.18:19:00.62#ibcon#enter sib2, iclass 10, count 2 2006.173.18:19:00.62#ibcon#flushed, iclass 10, count 2 2006.173.18:19:00.62#ibcon#about to write, iclass 10, count 2 2006.173.18:19:00.62#ibcon#wrote, iclass 10, count 2 2006.173.18:19:00.62#ibcon#about to read 3, iclass 10, count 2 2006.173.18:19:00.64#ibcon#read 3, iclass 10, count 2 2006.173.18:19:00.64#ibcon#about to read 4, iclass 10, count 2 2006.173.18:19:00.64#ibcon#read 4, iclass 10, count 2 2006.173.18:19:00.64#ibcon#about to read 5, iclass 10, count 2 2006.173.18:19:00.64#ibcon#read 5, iclass 10, count 2 2006.173.18:19:00.64#ibcon#about to read 6, iclass 10, count 2 2006.173.18:19:00.64#ibcon#read 6, iclass 10, count 2 2006.173.18:19:00.64#ibcon#end of sib2, iclass 10, count 2 2006.173.18:19:00.64#ibcon#*mode == 0, iclass 10, count 2 2006.173.18:19:00.64#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.18:19:00.64#ibcon#[25=AT05-04\r\n] 2006.173.18:19:00.64#ibcon#*before write, iclass 10, count 2 2006.173.18:19:00.64#ibcon#enter sib2, iclass 10, count 2 2006.173.18:19:00.64#ibcon#flushed, iclass 10, count 2 2006.173.18:19:00.64#ibcon#about to write, iclass 10, count 2 2006.173.18:19:00.64#ibcon#wrote, iclass 10, count 2 2006.173.18:19:00.64#ibcon#about to read 3, iclass 10, count 2 2006.173.18:19:00.67#ibcon#read 3, iclass 10, count 2 2006.173.18:19:00.67#ibcon#about to read 4, iclass 10, count 2 2006.173.18:19:00.67#ibcon#read 4, iclass 10, count 2 2006.173.18:19:00.67#ibcon#about to read 5, iclass 10, count 2 2006.173.18:19:00.67#ibcon#read 5, iclass 10, count 2 2006.173.18:19:00.67#ibcon#about to read 6, iclass 10, count 2 2006.173.18:19:00.67#ibcon#read 6, iclass 10, count 2 2006.173.18:19:00.67#ibcon#end of sib2, iclass 10, count 2 2006.173.18:19:00.67#ibcon#*after write, iclass 10, count 2 2006.173.18:19:00.67#ibcon#*before return 0, iclass 10, count 2 2006.173.18:19:00.67#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.18:19:00.67#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.18:19:00.67#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.18:19:00.67#ibcon#ireg 7 cls_cnt 0 2006.173.18:19:00.67#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.18:19:00.79#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.18:19:00.79#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.18:19:00.79#ibcon#enter wrdev, iclass 10, count 0 2006.173.18:19:00.79#ibcon#first serial, iclass 10, count 0 2006.173.18:19:00.79#ibcon#enter sib2, iclass 10, count 0 2006.173.18:19:00.79#ibcon#flushed, iclass 10, count 0 2006.173.18:19:00.79#ibcon#about to write, iclass 10, count 0 2006.173.18:19:00.79#ibcon#wrote, iclass 10, count 0 2006.173.18:19:00.79#ibcon#about to read 3, iclass 10, count 0 2006.173.18:19:00.81#ibcon#read 3, iclass 10, count 0 2006.173.18:19:00.81#ibcon#about to read 4, iclass 10, count 0 2006.173.18:19:00.81#ibcon#read 4, iclass 10, count 0 2006.173.18:19:00.81#ibcon#about to read 5, iclass 10, count 0 2006.173.18:19:00.81#ibcon#read 5, iclass 10, count 0 2006.173.18:19:00.81#ibcon#about to read 6, iclass 10, count 0 2006.173.18:19:00.81#ibcon#read 6, iclass 10, count 0 2006.173.18:19:00.81#ibcon#end of sib2, iclass 10, count 0 2006.173.18:19:00.81#ibcon#*mode == 0, iclass 10, count 0 2006.173.18:19:00.81#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.18:19:00.81#ibcon#[25=USB\r\n] 2006.173.18:19:00.81#ibcon#*before write, iclass 10, count 0 2006.173.18:19:00.81#ibcon#enter sib2, iclass 10, count 0 2006.173.18:19:00.81#ibcon#flushed, iclass 10, count 0 2006.173.18:19:00.81#ibcon#about to write, iclass 10, count 0 2006.173.18:19:00.81#ibcon#wrote, iclass 10, count 0 2006.173.18:19:00.81#ibcon#about to read 3, iclass 10, count 0 2006.173.18:19:00.84#ibcon#read 3, iclass 10, count 0 2006.173.18:19:00.84#ibcon#about to read 4, iclass 10, count 0 2006.173.18:19:00.84#ibcon#read 4, iclass 10, count 0 2006.173.18:19:00.84#ibcon#about to read 5, iclass 10, count 0 2006.173.18:19:00.84#ibcon#read 5, iclass 10, count 0 2006.173.18:19:00.84#ibcon#about to read 6, iclass 10, count 0 2006.173.18:19:00.84#ibcon#read 6, iclass 10, count 0 2006.173.18:19:00.84#ibcon#end of sib2, iclass 10, count 0 2006.173.18:19:00.84#ibcon#*after write, iclass 10, count 0 2006.173.18:19:00.84#ibcon#*before return 0, iclass 10, count 0 2006.173.18:19:00.84#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.18:19:00.84#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.18:19:00.84#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.18:19:00.84#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.18:19:00.84$vck44/valo=6,814.99 2006.173.18:19:00.84#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.18:19:00.84#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.18:19:00.84#ibcon#ireg 17 cls_cnt 0 2006.173.18:19:00.84#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.18:19:00.84#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.18:19:00.84#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.18:19:00.84#ibcon#enter wrdev, iclass 12, count 0 2006.173.18:19:00.84#ibcon#first serial, iclass 12, count 0 2006.173.18:19:00.84#ibcon#enter sib2, iclass 12, count 0 2006.173.18:19:00.84#ibcon#flushed, iclass 12, count 0 2006.173.18:19:00.84#ibcon#about to write, iclass 12, count 0 2006.173.18:19:00.84#ibcon#wrote, iclass 12, count 0 2006.173.18:19:00.84#ibcon#about to read 3, iclass 12, count 0 2006.173.18:19:00.86#ibcon#read 3, iclass 12, count 0 2006.173.18:19:00.86#ibcon#about to read 4, iclass 12, count 0 2006.173.18:19:00.86#ibcon#read 4, iclass 12, count 0 2006.173.18:19:00.86#ibcon#about to read 5, iclass 12, count 0 2006.173.18:19:00.86#ibcon#read 5, iclass 12, count 0 2006.173.18:19:00.86#ibcon#about to read 6, iclass 12, count 0 2006.173.18:19:00.86#ibcon#read 6, iclass 12, count 0 2006.173.18:19:00.86#ibcon#end of sib2, iclass 12, count 0 2006.173.18:19:00.86#ibcon#*mode == 0, iclass 12, count 0 2006.173.18:19:00.86#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.18:19:00.86#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.18:19:00.86#ibcon#*before write, iclass 12, count 0 2006.173.18:19:00.86#ibcon#enter sib2, iclass 12, count 0 2006.173.18:19:00.86#ibcon#flushed, iclass 12, count 0 2006.173.18:19:00.86#ibcon#about to write, iclass 12, count 0 2006.173.18:19:00.86#ibcon#wrote, iclass 12, count 0 2006.173.18:19:00.86#ibcon#about to read 3, iclass 12, count 0 2006.173.18:19:00.90#ibcon#read 3, iclass 12, count 0 2006.173.18:19:00.90#ibcon#about to read 4, iclass 12, count 0 2006.173.18:19:00.90#ibcon#read 4, iclass 12, count 0 2006.173.18:19:00.90#ibcon#about to read 5, iclass 12, count 0 2006.173.18:19:00.90#ibcon#read 5, iclass 12, count 0 2006.173.18:19:00.90#ibcon#about to read 6, iclass 12, count 0 2006.173.18:19:00.90#ibcon#read 6, iclass 12, count 0 2006.173.18:19:00.90#ibcon#end of sib2, iclass 12, count 0 2006.173.18:19:00.90#ibcon#*after write, iclass 12, count 0 2006.173.18:19:00.90#ibcon#*before return 0, iclass 12, count 0 2006.173.18:19:00.90#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.18:19:00.90#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.18:19:00.90#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.18:19:00.90#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.18:19:00.90$vck44/va=6,3 2006.173.18:19:00.90#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.18:19:00.90#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.18:19:00.90#ibcon#ireg 11 cls_cnt 2 2006.173.18:19:00.90#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.18:19:00.96#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.18:19:00.96#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.18:19:00.96#ibcon#enter wrdev, iclass 14, count 2 2006.173.18:19:00.96#ibcon#first serial, iclass 14, count 2 2006.173.18:19:00.96#ibcon#enter sib2, iclass 14, count 2 2006.173.18:19:00.96#ibcon#flushed, iclass 14, count 2 2006.173.18:19:00.96#ibcon#about to write, iclass 14, count 2 2006.173.18:19:00.96#ibcon#wrote, iclass 14, count 2 2006.173.18:19:00.96#ibcon#about to read 3, iclass 14, count 2 2006.173.18:19:00.98#ibcon#read 3, iclass 14, count 2 2006.173.18:19:00.98#ibcon#about to read 4, iclass 14, count 2 2006.173.18:19:00.98#ibcon#read 4, iclass 14, count 2 2006.173.18:19:00.98#ibcon#about to read 5, iclass 14, count 2 2006.173.18:19:00.98#ibcon#read 5, iclass 14, count 2 2006.173.18:19:00.98#ibcon#about to read 6, iclass 14, count 2 2006.173.18:19:00.98#ibcon#read 6, iclass 14, count 2 2006.173.18:19:00.98#ibcon#end of sib2, iclass 14, count 2 2006.173.18:19:00.98#ibcon#*mode == 0, iclass 14, count 2 2006.173.18:19:00.98#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.18:19:00.98#ibcon#[25=AT06-03\r\n] 2006.173.18:19:00.98#ibcon#*before write, iclass 14, count 2 2006.173.18:19:00.98#ibcon#enter sib2, iclass 14, count 2 2006.173.18:19:00.98#ibcon#flushed, iclass 14, count 2 2006.173.18:19:00.98#ibcon#about to write, iclass 14, count 2 2006.173.18:19:00.98#ibcon#wrote, iclass 14, count 2 2006.173.18:19:00.98#ibcon#about to read 3, iclass 14, count 2 2006.173.18:19:01.01#ibcon#read 3, iclass 14, count 2 2006.173.18:19:01.01#ibcon#about to read 4, iclass 14, count 2 2006.173.18:19:01.01#ibcon#read 4, iclass 14, count 2 2006.173.18:19:01.01#ibcon#about to read 5, iclass 14, count 2 2006.173.18:19:01.01#ibcon#read 5, iclass 14, count 2 2006.173.18:19:01.01#ibcon#about to read 6, iclass 14, count 2 2006.173.18:19:01.01#ibcon#read 6, iclass 14, count 2 2006.173.18:19:01.01#ibcon#end of sib2, iclass 14, count 2 2006.173.18:19:01.01#ibcon#*after write, iclass 14, count 2 2006.173.18:19:01.01#ibcon#*before return 0, iclass 14, count 2 2006.173.18:19:01.01#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.18:19:01.01#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.18:19:01.01#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.18:19:01.01#ibcon#ireg 7 cls_cnt 0 2006.173.18:19:01.01#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.18:19:01.13#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.18:19:01.13#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.18:19:01.13#ibcon#enter wrdev, iclass 14, count 0 2006.173.18:19:01.13#ibcon#first serial, iclass 14, count 0 2006.173.18:19:01.13#ibcon#enter sib2, iclass 14, count 0 2006.173.18:19:01.13#ibcon#flushed, iclass 14, count 0 2006.173.18:19:01.13#ibcon#about to write, iclass 14, count 0 2006.173.18:19:01.13#ibcon#wrote, iclass 14, count 0 2006.173.18:19:01.13#ibcon#about to read 3, iclass 14, count 0 2006.173.18:19:01.15#ibcon#read 3, iclass 14, count 0 2006.173.18:19:01.15#ibcon#about to read 4, iclass 14, count 0 2006.173.18:19:01.15#ibcon#read 4, iclass 14, count 0 2006.173.18:19:01.15#ibcon#about to read 5, iclass 14, count 0 2006.173.18:19:01.15#ibcon#read 5, iclass 14, count 0 2006.173.18:19:01.15#ibcon#about to read 6, iclass 14, count 0 2006.173.18:19:01.15#ibcon#read 6, iclass 14, count 0 2006.173.18:19:01.15#ibcon#end of sib2, iclass 14, count 0 2006.173.18:19:01.15#ibcon#*mode == 0, iclass 14, count 0 2006.173.18:19:01.15#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.18:19:01.15#ibcon#[25=USB\r\n] 2006.173.18:19:01.15#ibcon#*before write, iclass 14, count 0 2006.173.18:19:01.15#ibcon#enter sib2, iclass 14, count 0 2006.173.18:19:01.15#ibcon#flushed, iclass 14, count 0 2006.173.18:19:01.15#ibcon#about to write, iclass 14, count 0 2006.173.18:19:01.15#ibcon#wrote, iclass 14, count 0 2006.173.18:19:01.15#ibcon#about to read 3, iclass 14, count 0 2006.173.18:19:01.18#ibcon#read 3, iclass 14, count 0 2006.173.18:19:01.18#ibcon#about to read 4, iclass 14, count 0 2006.173.18:19:01.18#ibcon#read 4, iclass 14, count 0 2006.173.18:19:01.18#ibcon#about to read 5, iclass 14, count 0 2006.173.18:19:01.18#ibcon#read 5, iclass 14, count 0 2006.173.18:19:01.18#ibcon#about to read 6, iclass 14, count 0 2006.173.18:19:01.18#ibcon#read 6, iclass 14, count 0 2006.173.18:19:01.18#ibcon#end of sib2, iclass 14, count 0 2006.173.18:19:01.18#ibcon#*after write, iclass 14, count 0 2006.173.18:19:01.18#ibcon#*before return 0, iclass 14, count 0 2006.173.18:19:01.18#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.18:19:01.18#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.18:19:01.18#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.18:19:01.18#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.18:19:01.18$vck44/valo=7,864.99 2006.173.18:19:01.18#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.18:19:01.18#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.18:19:01.18#ibcon#ireg 17 cls_cnt 0 2006.173.18:19:01.18#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.18:19:01.18#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.18:19:01.18#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.18:19:01.18#ibcon#enter wrdev, iclass 16, count 0 2006.173.18:19:01.18#ibcon#first serial, iclass 16, count 0 2006.173.18:19:01.18#ibcon#enter sib2, iclass 16, count 0 2006.173.18:19:01.18#ibcon#flushed, iclass 16, count 0 2006.173.18:19:01.18#ibcon#about to write, iclass 16, count 0 2006.173.18:19:01.18#ibcon#wrote, iclass 16, count 0 2006.173.18:19:01.18#ibcon#about to read 3, iclass 16, count 0 2006.173.18:19:01.20#ibcon#read 3, iclass 16, count 0 2006.173.18:19:01.20#ibcon#about to read 4, iclass 16, count 0 2006.173.18:19:01.20#ibcon#read 4, iclass 16, count 0 2006.173.18:19:01.20#ibcon#about to read 5, iclass 16, count 0 2006.173.18:19:01.20#ibcon#read 5, iclass 16, count 0 2006.173.18:19:01.20#ibcon#about to read 6, iclass 16, count 0 2006.173.18:19:01.20#ibcon#read 6, iclass 16, count 0 2006.173.18:19:01.20#ibcon#end of sib2, iclass 16, count 0 2006.173.18:19:01.20#ibcon#*mode == 0, iclass 16, count 0 2006.173.18:19:01.20#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.18:19:01.20#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.18:19:01.20#ibcon#*before write, iclass 16, count 0 2006.173.18:19:01.20#ibcon#enter sib2, iclass 16, count 0 2006.173.18:19:01.20#ibcon#flushed, iclass 16, count 0 2006.173.18:19:01.20#ibcon#about to write, iclass 16, count 0 2006.173.18:19:01.20#ibcon#wrote, iclass 16, count 0 2006.173.18:19:01.20#ibcon#about to read 3, iclass 16, count 0 2006.173.18:19:01.24#ibcon#read 3, iclass 16, count 0 2006.173.18:19:01.24#ibcon#about to read 4, iclass 16, count 0 2006.173.18:19:01.24#ibcon#read 4, iclass 16, count 0 2006.173.18:19:01.24#ibcon#about to read 5, iclass 16, count 0 2006.173.18:19:01.24#ibcon#read 5, iclass 16, count 0 2006.173.18:19:01.24#ibcon#about to read 6, iclass 16, count 0 2006.173.18:19:01.24#ibcon#read 6, iclass 16, count 0 2006.173.18:19:01.24#ibcon#end of sib2, iclass 16, count 0 2006.173.18:19:01.24#ibcon#*after write, iclass 16, count 0 2006.173.18:19:01.24#ibcon#*before return 0, iclass 16, count 0 2006.173.18:19:01.24#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.18:19:01.24#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.18:19:01.24#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.18:19:01.24#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.18:19:01.24$vck44/va=7,4 2006.173.18:19:01.24#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.18:19:01.24#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.18:19:01.24#ibcon#ireg 11 cls_cnt 2 2006.173.18:19:01.24#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.18:19:01.30#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.18:19:01.30#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.18:19:01.30#ibcon#enter wrdev, iclass 18, count 2 2006.173.18:19:01.30#ibcon#first serial, iclass 18, count 2 2006.173.18:19:01.30#ibcon#enter sib2, iclass 18, count 2 2006.173.18:19:01.30#ibcon#flushed, iclass 18, count 2 2006.173.18:19:01.30#ibcon#about to write, iclass 18, count 2 2006.173.18:19:01.30#ibcon#wrote, iclass 18, count 2 2006.173.18:19:01.30#ibcon#about to read 3, iclass 18, count 2 2006.173.18:19:01.32#ibcon#read 3, iclass 18, count 2 2006.173.18:19:01.32#ibcon#about to read 4, iclass 18, count 2 2006.173.18:19:01.32#ibcon#read 4, iclass 18, count 2 2006.173.18:19:01.32#ibcon#about to read 5, iclass 18, count 2 2006.173.18:19:01.32#ibcon#read 5, iclass 18, count 2 2006.173.18:19:01.32#ibcon#about to read 6, iclass 18, count 2 2006.173.18:19:01.32#ibcon#read 6, iclass 18, count 2 2006.173.18:19:01.32#ibcon#end of sib2, iclass 18, count 2 2006.173.18:19:01.32#ibcon#*mode == 0, iclass 18, count 2 2006.173.18:19:01.32#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.18:19:01.32#ibcon#[25=AT07-04\r\n] 2006.173.18:19:01.32#ibcon#*before write, iclass 18, count 2 2006.173.18:19:01.32#ibcon#enter sib2, iclass 18, count 2 2006.173.18:19:01.32#ibcon#flushed, iclass 18, count 2 2006.173.18:19:01.32#ibcon#about to write, iclass 18, count 2 2006.173.18:19:01.32#ibcon#wrote, iclass 18, count 2 2006.173.18:19:01.32#ibcon#about to read 3, iclass 18, count 2 2006.173.18:19:01.35#ibcon#read 3, iclass 18, count 2 2006.173.18:19:01.35#ibcon#about to read 4, iclass 18, count 2 2006.173.18:19:01.35#ibcon#read 4, iclass 18, count 2 2006.173.18:19:01.35#ibcon#about to read 5, iclass 18, count 2 2006.173.18:19:01.35#ibcon#read 5, iclass 18, count 2 2006.173.18:19:01.35#ibcon#about to read 6, iclass 18, count 2 2006.173.18:19:01.35#ibcon#read 6, iclass 18, count 2 2006.173.18:19:01.35#ibcon#end of sib2, iclass 18, count 2 2006.173.18:19:01.35#ibcon#*after write, iclass 18, count 2 2006.173.18:19:01.35#ibcon#*before return 0, iclass 18, count 2 2006.173.18:19:01.35#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.18:19:01.35#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.18:19:01.35#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.18:19:01.35#ibcon#ireg 7 cls_cnt 0 2006.173.18:19:01.35#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.18:19:01.47#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.18:19:01.47#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.18:19:01.47#ibcon#enter wrdev, iclass 18, count 0 2006.173.18:19:01.47#ibcon#first serial, iclass 18, count 0 2006.173.18:19:01.47#ibcon#enter sib2, iclass 18, count 0 2006.173.18:19:01.47#ibcon#flushed, iclass 18, count 0 2006.173.18:19:01.47#ibcon#about to write, iclass 18, count 0 2006.173.18:19:01.47#ibcon#wrote, iclass 18, count 0 2006.173.18:19:01.47#ibcon#about to read 3, iclass 18, count 0 2006.173.18:19:01.49#ibcon#read 3, iclass 18, count 0 2006.173.18:19:01.49#ibcon#about to read 4, iclass 18, count 0 2006.173.18:19:01.49#ibcon#read 4, iclass 18, count 0 2006.173.18:19:01.49#ibcon#about to read 5, iclass 18, count 0 2006.173.18:19:01.49#ibcon#read 5, iclass 18, count 0 2006.173.18:19:01.49#ibcon#about to read 6, iclass 18, count 0 2006.173.18:19:01.49#ibcon#read 6, iclass 18, count 0 2006.173.18:19:01.49#ibcon#end of sib2, iclass 18, count 0 2006.173.18:19:01.49#ibcon#*mode == 0, iclass 18, count 0 2006.173.18:19:01.49#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.18:19:01.49#ibcon#[25=USB\r\n] 2006.173.18:19:01.49#ibcon#*before write, iclass 18, count 0 2006.173.18:19:01.49#ibcon#enter sib2, iclass 18, count 0 2006.173.18:19:01.49#ibcon#flushed, iclass 18, count 0 2006.173.18:19:01.49#ibcon#about to write, iclass 18, count 0 2006.173.18:19:01.49#ibcon#wrote, iclass 18, count 0 2006.173.18:19:01.49#ibcon#about to read 3, iclass 18, count 0 2006.173.18:19:01.52#ibcon#read 3, iclass 18, count 0 2006.173.18:19:01.52#ibcon#about to read 4, iclass 18, count 0 2006.173.18:19:01.52#ibcon#read 4, iclass 18, count 0 2006.173.18:19:01.52#ibcon#about to read 5, iclass 18, count 0 2006.173.18:19:01.52#ibcon#read 5, iclass 18, count 0 2006.173.18:19:01.52#ibcon#about to read 6, iclass 18, count 0 2006.173.18:19:01.52#ibcon#read 6, iclass 18, count 0 2006.173.18:19:01.52#ibcon#end of sib2, iclass 18, count 0 2006.173.18:19:01.52#ibcon#*after write, iclass 18, count 0 2006.173.18:19:01.52#ibcon#*before return 0, iclass 18, count 0 2006.173.18:19:01.52#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.18:19:01.52#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.18:19:01.52#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.18:19:01.52#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.18:19:01.52$vck44/valo=8,884.99 2006.173.18:19:01.52#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.18:19:01.52#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.18:19:01.52#ibcon#ireg 17 cls_cnt 0 2006.173.18:19:01.52#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.18:19:01.52#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.18:19:01.52#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.18:19:01.52#ibcon#enter wrdev, iclass 20, count 0 2006.173.18:19:01.52#ibcon#first serial, iclass 20, count 0 2006.173.18:19:01.52#ibcon#enter sib2, iclass 20, count 0 2006.173.18:19:01.52#ibcon#flushed, iclass 20, count 0 2006.173.18:19:01.52#ibcon#about to write, iclass 20, count 0 2006.173.18:19:01.52#ibcon#wrote, iclass 20, count 0 2006.173.18:19:01.52#ibcon#about to read 3, iclass 20, count 0 2006.173.18:19:01.54#ibcon#read 3, iclass 20, count 0 2006.173.18:19:01.54#ibcon#about to read 4, iclass 20, count 0 2006.173.18:19:01.54#ibcon#read 4, iclass 20, count 0 2006.173.18:19:01.54#ibcon#about to read 5, iclass 20, count 0 2006.173.18:19:01.54#ibcon#read 5, iclass 20, count 0 2006.173.18:19:01.54#ibcon#about to read 6, iclass 20, count 0 2006.173.18:19:01.54#ibcon#read 6, iclass 20, count 0 2006.173.18:19:01.54#ibcon#end of sib2, iclass 20, count 0 2006.173.18:19:01.54#ibcon#*mode == 0, iclass 20, count 0 2006.173.18:19:01.54#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.18:19:01.54#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.18:19:01.54#ibcon#*before write, iclass 20, count 0 2006.173.18:19:01.54#ibcon#enter sib2, iclass 20, count 0 2006.173.18:19:01.54#ibcon#flushed, iclass 20, count 0 2006.173.18:19:01.54#ibcon#about to write, iclass 20, count 0 2006.173.18:19:01.54#ibcon#wrote, iclass 20, count 0 2006.173.18:19:01.54#ibcon#about to read 3, iclass 20, count 0 2006.173.18:19:01.58#ibcon#read 3, iclass 20, count 0 2006.173.18:19:01.58#ibcon#about to read 4, iclass 20, count 0 2006.173.18:19:01.58#ibcon#read 4, iclass 20, count 0 2006.173.18:19:01.58#ibcon#about to read 5, iclass 20, count 0 2006.173.18:19:01.58#ibcon#read 5, iclass 20, count 0 2006.173.18:19:01.58#ibcon#about to read 6, iclass 20, count 0 2006.173.18:19:01.58#ibcon#read 6, iclass 20, count 0 2006.173.18:19:01.58#ibcon#end of sib2, iclass 20, count 0 2006.173.18:19:01.58#ibcon#*after write, iclass 20, count 0 2006.173.18:19:01.58#ibcon#*before return 0, iclass 20, count 0 2006.173.18:19:01.58#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.18:19:01.58#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.18:19:01.58#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.18:19:01.58#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.18:19:01.58$vck44/va=8,4 2006.173.18:19:01.58#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.18:19:01.58#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.18:19:01.58#ibcon#ireg 11 cls_cnt 2 2006.173.18:19:01.58#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.18:19:01.64#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.18:19:01.64#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.18:19:01.64#ibcon#enter wrdev, iclass 22, count 2 2006.173.18:19:01.64#ibcon#first serial, iclass 22, count 2 2006.173.18:19:01.64#ibcon#enter sib2, iclass 22, count 2 2006.173.18:19:01.64#ibcon#flushed, iclass 22, count 2 2006.173.18:19:01.64#ibcon#about to write, iclass 22, count 2 2006.173.18:19:01.64#ibcon#wrote, iclass 22, count 2 2006.173.18:19:01.64#ibcon#about to read 3, iclass 22, count 2 2006.173.18:19:01.66#ibcon#read 3, iclass 22, count 2 2006.173.18:19:01.66#ibcon#about to read 4, iclass 22, count 2 2006.173.18:19:01.66#ibcon#read 4, iclass 22, count 2 2006.173.18:19:01.66#ibcon#about to read 5, iclass 22, count 2 2006.173.18:19:01.66#ibcon#read 5, iclass 22, count 2 2006.173.18:19:01.66#ibcon#about to read 6, iclass 22, count 2 2006.173.18:19:01.66#ibcon#read 6, iclass 22, count 2 2006.173.18:19:01.66#ibcon#end of sib2, iclass 22, count 2 2006.173.18:19:01.66#ibcon#*mode == 0, iclass 22, count 2 2006.173.18:19:01.66#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.18:19:01.66#ibcon#[25=AT08-04\r\n] 2006.173.18:19:01.66#ibcon#*before write, iclass 22, count 2 2006.173.18:19:01.66#ibcon#enter sib2, iclass 22, count 2 2006.173.18:19:01.66#ibcon#flushed, iclass 22, count 2 2006.173.18:19:01.66#ibcon#about to write, iclass 22, count 2 2006.173.18:19:01.66#ibcon#wrote, iclass 22, count 2 2006.173.18:19:01.66#ibcon#about to read 3, iclass 22, count 2 2006.173.18:19:01.69#ibcon#read 3, iclass 22, count 2 2006.173.18:19:01.69#ibcon#about to read 4, iclass 22, count 2 2006.173.18:19:01.69#ibcon#read 4, iclass 22, count 2 2006.173.18:19:01.69#ibcon#about to read 5, iclass 22, count 2 2006.173.18:19:01.69#ibcon#read 5, iclass 22, count 2 2006.173.18:19:01.69#ibcon#about to read 6, iclass 22, count 2 2006.173.18:19:01.69#ibcon#read 6, iclass 22, count 2 2006.173.18:19:01.69#ibcon#end of sib2, iclass 22, count 2 2006.173.18:19:01.69#ibcon#*after write, iclass 22, count 2 2006.173.18:19:01.69#ibcon#*before return 0, iclass 22, count 2 2006.173.18:19:01.69#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.18:19:01.69#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.18:19:01.69#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.18:19:01.69#ibcon#ireg 7 cls_cnt 0 2006.173.18:19:01.69#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.18:19:01.81#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.18:19:01.81#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.18:19:01.81#ibcon#enter wrdev, iclass 22, count 0 2006.173.18:19:01.81#ibcon#first serial, iclass 22, count 0 2006.173.18:19:01.81#ibcon#enter sib2, iclass 22, count 0 2006.173.18:19:01.81#ibcon#flushed, iclass 22, count 0 2006.173.18:19:01.81#ibcon#about to write, iclass 22, count 0 2006.173.18:19:01.81#ibcon#wrote, iclass 22, count 0 2006.173.18:19:01.81#ibcon#about to read 3, iclass 22, count 0 2006.173.18:19:01.83#ibcon#read 3, iclass 22, count 0 2006.173.18:19:01.83#ibcon#about to read 4, iclass 22, count 0 2006.173.18:19:01.83#ibcon#read 4, iclass 22, count 0 2006.173.18:19:01.83#ibcon#about to read 5, iclass 22, count 0 2006.173.18:19:01.83#ibcon#read 5, iclass 22, count 0 2006.173.18:19:01.83#ibcon#about to read 6, iclass 22, count 0 2006.173.18:19:01.83#ibcon#read 6, iclass 22, count 0 2006.173.18:19:01.83#ibcon#end of sib2, iclass 22, count 0 2006.173.18:19:01.83#ibcon#*mode == 0, iclass 22, count 0 2006.173.18:19:01.83#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.18:19:01.83#ibcon#[25=USB\r\n] 2006.173.18:19:01.83#ibcon#*before write, iclass 22, count 0 2006.173.18:19:01.83#ibcon#enter sib2, iclass 22, count 0 2006.173.18:19:01.83#ibcon#flushed, iclass 22, count 0 2006.173.18:19:01.83#ibcon#about to write, iclass 22, count 0 2006.173.18:19:01.83#ibcon#wrote, iclass 22, count 0 2006.173.18:19:01.83#ibcon#about to read 3, iclass 22, count 0 2006.173.18:19:01.86#ibcon#read 3, iclass 22, count 0 2006.173.18:19:01.86#ibcon#about to read 4, iclass 22, count 0 2006.173.18:19:01.86#ibcon#read 4, iclass 22, count 0 2006.173.18:19:01.86#ibcon#about to read 5, iclass 22, count 0 2006.173.18:19:01.86#ibcon#read 5, iclass 22, count 0 2006.173.18:19:01.86#ibcon#about to read 6, iclass 22, count 0 2006.173.18:19:01.86#ibcon#read 6, iclass 22, count 0 2006.173.18:19:01.86#ibcon#end of sib2, iclass 22, count 0 2006.173.18:19:01.86#ibcon#*after write, iclass 22, count 0 2006.173.18:19:01.86#ibcon#*before return 0, iclass 22, count 0 2006.173.18:19:01.86#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.18:19:01.86#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.18:19:01.86#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.18:19:01.86#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.18:19:01.86$vck44/vblo=1,629.99 2006.173.18:19:01.86#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.18:19:01.86#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.18:19:01.86#ibcon#ireg 17 cls_cnt 0 2006.173.18:19:01.86#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.18:19:01.86#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.18:19:01.86#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.18:19:01.86#ibcon#enter wrdev, iclass 24, count 0 2006.173.18:19:01.86#ibcon#first serial, iclass 24, count 0 2006.173.18:19:01.86#ibcon#enter sib2, iclass 24, count 0 2006.173.18:19:01.86#ibcon#flushed, iclass 24, count 0 2006.173.18:19:01.86#ibcon#about to write, iclass 24, count 0 2006.173.18:19:01.86#ibcon#wrote, iclass 24, count 0 2006.173.18:19:01.86#ibcon#about to read 3, iclass 24, count 0 2006.173.18:19:01.88#ibcon#read 3, iclass 24, count 0 2006.173.18:19:01.88#ibcon#about to read 4, iclass 24, count 0 2006.173.18:19:01.88#ibcon#read 4, iclass 24, count 0 2006.173.18:19:01.88#ibcon#about to read 5, iclass 24, count 0 2006.173.18:19:01.88#ibcon#read 5, iclass 24, count 0 2006.173.18:19:01.88#ibcon#about to read 6, iclass 24, count 0 2006.173.18:19:01.88#ibcon#read 6, iclass 24, count 0 2006.173.18:19:01.88#ibcon#end of sib2, iclass 24, count 0 2006.173.18:19:01.88#ibcon#*mode == 0, iclass 24, count 0 2006.173.18:19:01.88#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.18:19:01.88#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.18:19:01.88#ibcon#*before write, iclass 24, count 0 2006.173.18:19:01.88#ibcon#enter sib2, iclass 24, count 0 2006.173.18:19:01.88#ibcon#flushed, iclass 24, count 0 2006.173.18:19:01.88#ibcon#about to write, iclass 24, count 0 2006.173.18:19:01.88#ibcon#wrote, iclass 24, count 0 2006.173.18:19:01.88#ibcon#about to read 3, iclass 24, count 0 2006.173.18:19:01.92#ibcon#read 3, iclass 24, count 0 2006.173.18:19:01.92#ibcon#about to read 4, iclass 24, count 0 2006.173.18:19:01.92#ibcon#read 4, iclass 24, count 0 2006.173.18:19:01.92#ibcon#about to read 5, iclass 24, count 0 2006.173.18:19:01.92#ibcon#read 5, iclass 24, count 0 2006.173.18:19:01.92#ibcon#about to read 6, iclass 24, count 0 2006.173.18:19:01.92#ibcon#read 6, iclass 24, count 0 2006.173.18:19:01.92#ibcon#end of sib2, iclass 24, count 0 2006.173.18:19:01.92#ibcon#*after write, iclass 24, count 0 2006.173.18:19:01.92#ibcon#*before return 0, iclass 24, count 0 2006.173.18:19:01.92#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.18:19:01.92#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.18:19:01.92#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.18:19:01.92#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.18:19:01.92$vck44/vb=1,4 2006.173.18:19:01.92#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.18:19:01.92#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.18:19:01.92#ibcon#ireg 11 cls_cnt 2 2006.173.18:19:01.92#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.18:19:01.92#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.18:19:01.92#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.18:19:01.92#ibcon#enter wrdev, iclass 26, count 2 2006.173.18:19:01.92#ibcon#first serial, iclass 26, count 2 2006.173.18:19:01.92#ibcon#enter sib2, iclass 26, count 2 2006.173.18:19:01.92#ibcon#flushed, iclass 26, count 2 2006.173.18:19:01.92#ibcon#about to write, iclass 26, count 2 2006.173.18:19:01.92#ibcon#wrote, iclass 26, count 2 2006.173.18:19:01.92#ibcon#about to read 3, iclass 26, count 2 2006.173.18:19:01.94#ibcon#read 3, iclass 26, count 2 2006.173.18:19:01.94#ibcon#about to read 4, iclass 26, count 2 2006.173.18:19:01.94#ibcon#read 4, iclass 26, count 2 2006.173.18:19:01.94#ibcon#about to read 5, iclass 26, count 2 2006.173.18:19:01.94#ibcon#read 5, iclass 26, count 2 2006.173.18:19:01.94#ibcon#about to read 6, iclass 26, count 2 2006.173.18:19:01.94#ibcon#read 6, iclass 26, count 2 2006.173.18:19:01.94#ibcon#end of sib2, iclass 26, count 2 2006.173.18:19:01.94#ibcon#*mode == 0, iclass 26, count 2 2006.173.18:19:01.94#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.18:19:01.94#ibcon#[27=AT01-04\r\n] 2006.173.18:19:01.94#ibcon#*before write, iclass 26, count 2 2006.173.18:19:01.94#ibcon#enter sib2, iclass 26, count 2 2006.173.18:19:01.94#ibcon#flushed, iclass 26, count 2 2006.173.18:19:01.94#ibcon#about to write, iclass 26, count 2 2006.173.18:19:01.94#ibcon#wrote, iclass 26, count 2 2006.173.18:19:01.94#ibcon#about to read 3, iclass 26, count 2 2006.173.18:19:01.97#ibcon#read 3, iclass 26, count 2 2006.173.18:19:01.97#ibcon#about to read 4, iclass 26, count 2 2006.173.18:19:01.97#ibcon#read 4, iclass 26, count 2 2006.173.18:19:01.97#ibcon#about to read 5, iclass 26, count 2 2006.173.18:19:01.97#ibcon#read 5, iclass 26, count 2 2006.173.18:19:01.97#ibcon#about to read 6, iclass 26, count 2 2006.173.18:19:01.97#ibcon#read 6, iclass 26, count 2 2006.173.18:19:01.97#ibcon#end of sib2, iclass 26, count 2 2006.173.18:19:01.97#ibcon#*after write, iclass 26, count 2 2006.173.18:19:01.97#ibcon#*before return 0, iclass 26, count 2 2006.173.18:19:01.97#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.18:19:01.97#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.18:19:01.97#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.18:19:01.97#ibcon#ireg 7 cls_cnt 0 2006.173.18:19:01.97#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.18:19:02.09#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.18:19:02.09#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.18:19:02.09#ibcon#enter wrdev, iclass 26, count 0 2006.173.18:19:02.09#ibcon#first serial, iclass 26, count 0 2006.173.18:19:02.09#ibcon#enter sib2, iclass 26, count 0 2006.173.18:19:02.09#ibcon#flushed, iclass 26, count 0 2006.173.18:19:02.09#ibcon#about to write, iclass 26, count 0 2006.173.18:19:02.09#ibcon#wrote, iclass 26, count 0 2006.173.18:19:02.09#ibcon#about to read 3, iclass 26, count 0 2006.173.18:19:02.11#ibcon#read 3, iclass 26, count 0 2006.173.18:19:02.11#ibcon#about to read 4, iclass 26, count 0 2006.173.18:19:02.11#ibcon#read 4, iclass 26, count 0 2006.173.18:19:02.11#ibcon#about to read 5, iclass 26, count 0 2006.173.18:19:02.11#ibcon#read 5, iclass 26, count 0 2006.173.18:19:02.11#ibcon#about to read 6, iclass 26, count 0 2006.173.18:19:02.11#ibcon#read 6, iclass 26, count 0 2006.173.18:19:02.11#ibcon#end of sib2, iclass 26, count 0 2006.173.18:19:02.11#ibcon#*mode == 0, iclass 26, count 0 2006.173.18:19:02.11#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.18:19:02.11#ibcon#[27=USB\r\n] 2006.173.18:19:02.11#ibcon#*before write, iclass 26, count 0 2006.173.18:19:02.11#ibcon#enter sib2, iclass 26, count 0 2006.173.18:19:02.11#ibcon#flushed, iclass 26, count 0 2006.173.18:19:02.11#ibcon#about to write, iclass 26, count 0 2006.173.18:19:02.11#ibcon#wrote, iclass 26, count 0 2006.173.18:19:02.11#ibcon#about to read 3, iclass 26, count 0 2006.173.18:19:02.14#ibcon#read 3, iclass 26, count 0 2006.173.18:19:02.14#ibcon#about to read 4, iclass 26, count 0 2006.173.18:19:02.14#ibcon#read 4, iclass 26, count 0 2006.173.18:19:02.14#ibcon#about to read 5, iclass 26, count 0 2006.173.18:19:02.14#ibcon#read 5, iclass 26, count 0 2006.173.18:19:02.14#ibcon#about to read 6, iclass 26, count 0 2006.173.18:19:02.14#ibcon#read 6, iclass 26, count 0 2006.173.18:19:02.14#ibcon#end of sib2, iclass 26, count 0 2006.173.18:19:02.14#ibcon#*after write, iclass 26, count 0 2006.173.18:19:02.14#ibcon#*before return 0, iclass 26, count 0 2006.173.18:19:02.14#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.18:19:02.14#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.18:19:02.14#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.18:19:02.14#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.18:19:02.14$vck44/vblo=2,634.99 2006.173.18:19:02.14#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.18:19:02.14#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.18:19:02.14#ibcon#ireg 17 cls_cnt 0 2006.173.18:19:02.14#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.18:19:02.14#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.18:19:02.14#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.18:19:02.14#ibcon#enter wrdev, iclass 28, count 0 2006.173.18:19:02.14#ibcon#first serial, iclass 28, count 0 2006.173.18:19:02.14#ibcon#enter sib2, iclass 28, count 0 2006.173.18:19:02.14#ibcon#flushed, iclass 28, count 0 2006.173.18:19:02.14#ibcon#about to write, iclass 28, count 0 2006.173.18:19:02.14#ibcon#wrote, iclass 28, count 0 2006.173.18:19:02.14#ibcon#about to read 3, iclass 28, count 0 2006.173.18:19:02.16#ibcon#read 3, iclass 28, count 0 2006.173.18:19:02.16#ibcon#about to read 4, iclass 28, count 0 2006.173.18:19:02.16#ibcon#read 4, iclass 28, count 0 2006.173.18:19:02.16#ibcon#about to read 5, iclass 28, count 0 2006.173.18:19:02.16#ibcon#read 5, iclass 28, count 0 2006.173.18:19:02.16#ibcon#about to read 6, iclass 28, count 0 2006.173.18:19:02.16#ibcon#read 6, iclass 28, count 0 2006.173.18:19:02.16#ibcon#end of sib2, iclass 28, count 0 2006.173.18:19:02.16#ibcon#*mode == 0, iclass 28, count 0 2006.173.18:19:02.16#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.18:19:02.16#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.18:19:02.16#ibcon#*before write, iclass 28, count 0 2006.173.18:19:02.16#ibcon#enter sib2, iclass 28, count 0 2006.173.18:19:02.16#ibcon#flushed, iclass 28, count 0 2006.173.18:19:02.16#ibcon#about to write, iclass 28, count 0 2006.173.18:19:02.16#ibcon#wrote, iclass 28, count 0 2006.173.18:19:02.16#ibcon#about to read 3, iclass 28, count 0 2006.173.18:19:02.20#ibcon#read 3, iclass 28, count 0 2006.173.18:19:02.20#ibcon#about to read 4, iclass 28, count 0 2006.173.18:19:02.20#ibcon#read 4, iclass 28, count 0 2006.173.18:19:02.20#ibcon#about to read 5, iclass 28, count 0 2006.173.18:19:02.20#ibcon#read 5, iclass 28, count 0 2006.173.18:19:02.20#ibcon#about to read 6, iclass 28, count 0 2006.173.18:19:02.20#ibcon#read 6, iclass 28, count 0 2006.173.18:19:02.20#ibcon#end of sib2, iclass 28, count 0 2006.173.18:19:02.20#ibcon#*after write, iclass 28, count 0 2006.173.18:19:02.20#ibcon#*before return 0, iclass 28, count 0 2006.173.18:19:02.20#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.18:19:02.20#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.18:19:02.20#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.18:19:02.20#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.18:19:02.20$vck44/vb=2,4 2006.173.18:19:02.20#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.18:19:02.20#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.18:19:02.20#ibcon#ireg 11 cls_cnt 2 2006.173.18:19:02.20#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.18:19:02.26#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.18:19:02.26#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.18:19:02.26#ibcon#enter wrdev, iclass 30, count 2 2006.173.18:19:02.26#ibcon#first serial, iclass 30, count 2 2006.173.18:19:02.26#ibcon#enter sib2, iclass 30, count 2 2006.173.18:19:02.26#ibcon#flushed, iclass 30, count 2 2006.173.18:19:02.26#ibcon#about to write, iclass 30, count 2 2006.173.18:19:02.26#ibcon#wrote, iclass 30, count 2 2006.173.18:19:02.26#ibcon#about to read 3, iclass 30, count 2 2006.173.18:19:02.28#ibcon#read 3, iclass 30, count 2 2006.173.18:19:02.28#ibcon#about to read 4, iclass 30, count 2 2006.173.18:19:02.28#ibcon#read 4, iclass 30, count 2 2006.173.18:19:02.28#ibcon#about to read 5, iclass 30, count 2 2006.173.18:19:02.28#ibcon#read 5, iclass 30, count 2 2006.173.18:19:02.28#ibcon#about to read 6, iclass 30, count 2 2006.173.18:19:02.28#ibcon#read 6, iclass 30, count 2 2006.173.18:19:02.28#ibcon#end of sib2, iclass 30, count 2 2006.173.18:19:02.28#ibcon#*mode == 0, iclass 30, count 2 2006.173.18:19:02.28#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.18:19:02.28#ibcon#[27=AT02-04\r\n] 2006.173.18:19:02.28#ibcon#*before write, iclass 30, count 2 2006.173.18:19:02.28#ibcon#enter sib2, iclass 30, count 2 2006.173.18:19:02.28#ibcon#flushed, iclass 30, count 2 2006.173.18:19:02.28#ibcon#about to write, iclass 30, count 2 2006.173.18:19:02.28#ibcon#wrote, iclass 30, count 2 2006.173.18:19:02.28#ibcon#about to read 3, iclass 30, count 2 2006.173.18:19:02.31#ibcon#read 3, iclass 30, count 2 2006.173.18:19:02.31#ibcon#about to read 4, iclass 30, count 2 2006.173.18:19:02.31#ibcon#read 4, iclass 30, count 2 2006.173.18:19:02.31#ibcon#about to read 5, iclass 30, count 2 2006.173.18:19:02.31#ibcon#read 5, iclass 30, count 2 2006.173.18:19:02.31#ibcon#about to read 6, iclass 30, count 2 2006.173.18:19:02.31#ibcon#read 6, iclass 30, count 2 2006.173.18:19:02.31#ibcon#end of sib2, iclass 30, count 2 2006.173.18:19:02.31#ibcon#*after write, iclass 30, count 2 2006.173.18:19:02.31#ibcon#*before return 0, iclass 30, count 2 2006.173.18:19:02.31#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.18:19:02.31#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.18:19:02.31#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.18:19:02.31#ibcon#ireg 7 cls_cnt 0 2006.173.18:19:02.31#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.18:19:02.43#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.18:19:02.43#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.18:19:02.43#ibcon#enter wrdev, iclass 30, count 0 2006.173.18:19:02.43#ibcon#first serial, iclass 30, count 0 2006.173.18:19:02.43#ibcon#enter sib2, iclass 30, count 0 2006.173.18:19:02.43#ibcon#flushed, iclass 30, count 0 2006.173.18:19:02.43#ibcon#about to write, iclass 30, count 0 2006.173.18:19:02.43#ibcon#wrote, iclass 30, count 0 2006.173.18:19:02.43#ibcon#about to read 3, iclass 30, count 0 2006.173.18:19:02.45#ibcon#read 3, iclass 30, count 0 2006.173.18:19:02.45#ibcon#about to read 4, iclass 30, count 0 2006.173.18:19:02.45#ibcon#read 4, iclass 30, count 0 2006.173.18:19:02.45#ibcon#about to read 5, iclass 30, count 0 2006.173.18:19:02.45#ibcon#read 5, iclass 30, count 0 2006.173.18:19:02.45#ibcon#about to read 6, iclass 30, count 0 2006.173.18:19:02.45#ibcon#read 6, iclass 30, count 0 2006.173.18:19:02.45#ibcon#end of sib2, iclass 30, count 0 2006.173.18:19:02.45#ibcon#*mode == 0, iclass 30, count 0 2006.173.18:19:02.45#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.18:19:02.45#ibcon#[27=USB\r\n] 2006.173.18:19:02.45#ibcon#*before write, iclass 30, count 0 2006.173.18:19:02.45#ibcon#enter sib2, iclass 30, count 0 2006.173.18:19:02.45#ibcon#flushed, iclass 30, count 0 2006.173.18:19:02.45#ibcon#about to write, iclass 30, count 0 2006.173.18:19:02.45#ibcon#wrote, iclass 30, count 0 2006.173.18:19:02.45#ibcon#about to read 3, iclass 30, count 0 2006.173.18:19:02.48#ibcon#read 3, iclass 30, count 0 2006.173.18:19:02.48#ibcon#about to read 4, iclass 30, count 0 2006.173.18:19:02.48#ibcon#read 4, iclass 30, count 0 2006.173.18:19:02.48#ibcon#about to read 5, iclass 30, count 0 2006.173.18:19:02.48#ibcon#read 5, iclass 30, count 0 2006.173.18:19:02.48#ibcon#about to read 6, iclass 30, count 0 2006.173.18:19:02.48#ibcon#read 6, iclass 30, count 0 2006.173.18:19:02.48#ibcon#end of sib2, iclass 30, count 0 2006.173.18:19:02.48#ibcon#*after write, iclass 30, count 0 2006.173.18:19:02.48#ibcon#*before return 0, iclass 30, count 0 2006.173.18:19:02.48#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.18:19:02.48#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.18:19:02.48#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.18:19:02.48#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.18:19:02.48$vck44/vblo=3,649.99 2006.173.18:19:02.48#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.18:19:02.48#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.18:19:02.48#ibcon#ireg 17 cls_cnt 0 2006.173.18:19:02.48#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.18:19:02.48#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.18:19:02.48#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.18:19:02.48#ibcon#enter wrdev, iclass 32, count 0 2006.173.18:19:02.48#ibcon#first serial, iclass 32, count 0 2006.173.18:19:02.48#ibcon#enter sib2, iclass 32, count 0 2006.173.18:19:02.48#ibcon#flushed, iclass 32, count 0 2006.173.18:19:02.48#ibcon#about to write, iclass 32, count 0 2006.173.18:19:02.48#ibcon#wrote, iclass 32, count 0 2006.173.18:19:02.48#ibcon#about to read 3, iclass 32, count 0 2006.173.18:19:02.50#ibcon#read 3, iclass 32, count 0 2006.173.18:19:02.50#ibcon#about to read 4, iclass 32, count 0 2006.173.18:19:02.50#ibcon#read 4, iclass 32, count 0 2006.173.18:19:02.50#ibcon#about to read 5, iclass 32, count 0 2006.173.18:19:02.50#ibcon#read 5, iclass 32, count 0 2006.173.18:19:02.50#ibcon#about to read 6, iclass 32, count 0 2006.173.18:19:02.50#ibcon#read 6, iclass 32, count 0 2006.173.18:19:02.50#ibcon#end of sib2, iclass 32, count 0 2006.173.18:19:02.50#ibcon#*mode == 0, iclass 32, count 0 2006.173.18:19:02.50#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.18:19:02.50#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.18:19:02.50#ibcon#*before write, iclass 32, count 0 2006.173.18:19:02.50#ibcon#enter sib2, iclass 32, count 0 2006.173.18:19:02.50#ibcon#flushed, iclass 32, count 0 2006.173.18:19:02.50#ibcon#about to write, iclass 32, count 0 2006.173.18:19:02.50#ibcon#wrote, iclass 32, count 0 2006.173.18:19:02.50#ibcon#about to read 3, iclass 32, count 0 2006.173.18:19:02.54#ibcon#read 3, iclass 32, count 0 2006.173.18:19:02.54#ibcon#about to read 4, iclass 32, count 0 2006.173.18:19:02.54#ibcon#read 4, iclass 32, count 0 2006.173.18:19:02.54#ibcon#about to read 5, iclass 32, count 0 2006.173.18:19:02.54#ibcon#read 5, iclass 32, count 0 2006.173.18:19:02.54#ibcon#about to read 6, iclass 32, count 0 2006.173.18:19:02.54#ibcon#read 6, iclass 32, count 0 2006.173.18:19:02.54#ibcon#end of sib2, iclass 32, count 0 2006.173.18:19:02.54#ibcon#*after write, iclass 32, count 0 2006.173.18:19:02.54#ibcon#*before return 0, iclass 32, count 0 2006.173.18:19:02.54#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.18:19:02.54#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.18:19:02.54#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.18:19:02.54#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.18:19:02.54$vck44/vb=3,4 2006.173.18:19:02.54#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.18:19:02.54#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.18:19:02.54#ibcon#ireg 11 cls_cnt 2 2006.173.18:19:02.54#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.18:19:02.60#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.18:19:02.60#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.18:19:02.60#ibcon#enter wrdev, iclass 34, count 2 2006.173.18:19:02.60#ibcon#first serial, iclass 34, count 2 2006.173.18:19:02.60#ibcon#enter sib2, iclass 34, count 2 2006.173.18:19:02.60#ibcon#flushed, iclass 34, count 2 2006.173.18:19:02.60#ibcon#about to write, iclass 34, count 2 2006.173.18:19:02.60#ibcon#wrote, iclass 34, count 2 2006.173.18:19:02.60#ibcon#about to read 3, iclass 34, count 2 2006.173.18:19:02.62#ibcon#read 3, iclass 34, count 2 2006.173.18:19:02.62#ibcon#about to read 4, iclass 34, count 2 2006.173.18:19:02.62#ibcon#read 4, iclass 34, count 2 2006.173.18:19:02.62#ibcon#about to read 5, iclass 34, count 2 2006.173.18:19:02.62#ibcon#read 5, iclass 34, count 2 2006.173.18:19:02.62#ibcon#about to read 6, iclass 34, count 2 2006.173.18:19:02.62#ibcon#read 6, iclass 34, count 2 2006.173.18:19:02.62#ibcon#end of sib2, iclass 34, count 2 2006.173.18:19:02.62#ibcon#*mode == 0, iclass 34, count 2 2006.173.18:19:02.62#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.18:19:02.62#ibcon#[27=AT03-04\r\n] 2006.173.18:19:02.62#ibcon#*before write, iclass 34, count 2 2006.173.18:19:02.62#ibcon#enter sib2, iclass 34, count 2 2006.173.18:19:02.62#ibcon#flushed, iclass 34, count 2 2006.173.18:19:02.62#ibcon#about to write, iclass 34, count 2 2006.173.18:19:02.62#ibcon#wrote, iclass 34, count 2 2006.173.18:19:02.62#ibcon#about to read 3, iclass 34, count 2 2006.173.18:19:02.65#ibcon#read 3, iclass 34, count 2 2006.173.18:19:02.65#ibcon#about to read 4, iclass 34, count 2 2006.173.18:19:02.65#ibcon#read 4, iclass 34, count 2 2006.173.18:19:02.65#ibcon#about to read 5, iclass 34, count 2 2006.173.18:19:02.65#ibcon#read 5, iclass 34, count 2 2006.173.18:19:02.65#ibcon#about to read 6, iclass 34, count 2 2006.173.18:19:02.65#ibcon#read 6, iclass 34, count 2 2006.173.18:19:02.65#ibcon#end of sib2, iclass 34, count 2 2006.173.18:19:02.65#ibcon#*after write, iclass 34, count 2 2006.173.18:19:02.65#ibcon#*before return 0, iclass 34, count 2 2006.173.18:19:02.65#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.18:19:02.65#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.18:19:02.65#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.18:19:02.65#ibcon#ireg 7 cls_cnt 0 2006.173.18:19:02.65#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.18:19:02.77#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.18:19:02.77#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.18:19:02.77#ibcon#enter wrdev, iclass 34, count 0 2006.173.18:19:02.77#ibcon#first serial, iclass 34, count 0 2006.173.18:19:02.77#ibcon#enter sib2, iclass 34, count 0 2006.173.18:19:02.77#ibcon#flushed, iclass 34, count 0 2006.173.18:19:02.77#ibcon#about to write, iclass 34, count 0 2006.173.18:19:02.77#ibcon#wrote, iclass 34, count 0 2006.173.18:19:02.77#ibcon#about to read 3, iclass 34, count 0 2006.173.18:19:02.79#ibcon#read 3, iclass 34, count 0 2006.173.18:19:02.79#ibcon#about to read 4, iclass 34, count 0 2006.173.18:19:02.79#ibcon#read 4, iclass 34, count 0 2006.173.18:19:02.79#ibcon#about to read 5, iclass 34, count 0 2006.173.18:19:02.79#ibcon#read 5, iclass 34, count 0 2006.173.18:19:02.79#ibcon#about to read 6, iclass 34, count 0 2006.173.18:19:02.79#ibcon#read 6, iclass 34, count 0 2006.173.18:19:02.79#ibcon#end of sib2, iclass 34, count 0 2006.173.18:19:02.79#ibcon#*mode == 0, iclass 34, count 0 2006.173.18:19:02.79#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.18:19:02.79#ibcon#[27=USB\r\n] 2006.173.18:19:02.79#ibcon#*before write, iclass 34, count 0 2006.173.18:19:02.79#ibcon#enter sib2, iclass 34, count 0 2006.173.18:19:02.79#ibcon#flushed, iclass 34, count 0 2006.173.18:19:02.79#ibcon#about to write, iclass 34, count 0 2006.173.18:19:02.79#ibcon#wrote, iclass 34, count 0 2006.173.18:19:02.79#ibcon#about to read 3, iclass 34, count 0 2006.173.18:19:02.82#ibcon#read 3, iclass 34, count 0 2006.173.18:19:02.82#ibcon#about to read 4, iclass 34, count 0 2006.173.18:19:02.82#ibcon#read 4, iclass 34, count 0 2006.173.18:19:02.82#ibcon#about to read 5, iclass 34, count 0 2006.173.18:19:02.82#ibcon#read 5, iclass 34, count 0 2006.173.18:19:02.82#ibcon#about to read 6, iclass 34, count 0 2006.173.18:19:02.82#ibcon#read 6, iclass 34, count 0 2006.173.18:19:02.82#ibcon#end of sib2, iclass 34, count 0 2006.173.18:19:02.82#ibcon#*after write, iclass 34, count 0 2006.173.18:19:02.82#ibcon#*before return 0, iclass 34, count 0 2006.173.18:19:02.82#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.18:19:02.82#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.18:19:02.82#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.18:19:02.82#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.18:19:02.82$vck44/vblo=4,679.99 2006.173.18:19:02.82#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.18:19:02.82#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.18:19:02.82#ibcon#ireg 17 cls_cnt 0 2006.173.18:19:02.82#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.18:19:02.82#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.18:19:02.82#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.18:19:02.82#ibcon#enter wrdev, iclass 36, count 0 2006.173.18:19:02.82#ibcon#first serial, iclass 36, count 0 2006.173.18:19:02.82#ibcon#enter sib2, iclass 36, count 0 2006.173.18:19:02.82#ibcon#flushed, iclass 36, count 0 2006.173.18:19:02.82#ibcon#about to write, iclass 36, count 0 2006.173.18:19:02.82#ibcon#wrote, iclass 36, count 0 2006.173.18:19:02.82#ibcon#about to read 3, iclass 36, count 0 2006.173.18:19:02.84#ibcon#read 3, iclass 36, count 0 2006.173.18:19:02.84#ibcon#about to read 4, iclass 36, count 0 2006.173.18:19:02.84#ibcon#read 4, iclass 36, count 0 2006.173.18:19:02.84#ibcon#about to read 5, iclass 36, count 0 2006.173.18:19:02.84#ibcon#read 5, iclass 36, count 0 2006.173.18:19:02.84#ibcon#about to read 6, iclass 36, count 0 2006.173.18:19:02.84#ibcon#read 6, iclass 36, count 0 2006.173.18:19:02.84#ibcon#end of sib2, iclass 36, count 0 2006.173.18:19:02.84#ibcon#*mode == 0, iclass 36, count 0 2006.173.18:19:02.84#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.18:19:02.84#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.18:19:02.84#ibcon#*before write, iclass 36, count 0 2006.173.18:19:02.84#ibcon#enter sib2, iclass 36, count 0 2006.173.18:19:02.84#ibcon#flushed, iclass 36, count 0 2006.173.18:19:02.84#ibcon#about to write, iclass 36, count 0 2006.173.18:19:02.84#ibcon#wrote, iclass 36, count 0 2006.173.18:19:02.84#ibcon#about to read 3, iclass 36, count 0 2006.173.18:19:02.88#ibcon#read 3, iclass 36, count 0 2006.173.18:19:02.88#ibcon#about to read 4, iclass 36, count 0 2006.173.18:19:02.88#ibcon#read 4, iclass 36, count 0 2006.173.18:19:02.88#ibcon#about to read 5, iclass 36, count 0 2006.173.18:19:02.88#ibcon#read 5, iclass 36, count 0 2006.173.18:19:02.88#ibcon#about to read 6, iclass 36, count 0 2006.173.18:19:02.88#ibcon#read 6, iclass 36, count 0 2006.173.18:19:02.88#ibcon#end of sib2, iclass 36, count 0 2006.173.18:19:02.88#ibcon#*after write, iclass 36, count 0 2006.173.18:19:02.88#ibcon#*before return 0, iclass 36, count 0 2006.173.18:19:02.88#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.18:19:02.88#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.18:19:02.88#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.18:19:02.88#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.18:19:02.88$vck44/vb=4,4 2006.173.18:19:02.88#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.18:19:02.88#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.18:19:02.88#ibcon#ireg 11 cls_cnt 2 2006.173.18:19:02.88#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.18:19:02.94#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.18:19:02.94#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.18:19:02.94#ibcon#enter wrdev, iclass 38, count 2 2006.173.18:19:02.94#ibcon#first serial, iclass 38, count 2 2006.173.18:19:02.94#ibcon#enter sib2, iclass 38, count 2 2006.173.18:19:02.94#ibcon#flushed, iclass 38, count 2 2006.173.18:19:02.94#ibcon#about to write, iclass 38, count 2 2006.173.18:19:02.94#ibcon#wrote, iclass 38, count 2 2006.173.18:19:02.94#ibcon#about to read 3, iclass 38, count 2 2006.173.18:19:02.95#abcon#<5=/14 1.1 2.2 19.981001002.2\r\n> 2006.173.18:19:02.96#ibcon#read 3, iclass 38, count 2 2006.173.18:19:02.96#ibcon#about to read 4, iclass 38, count 2 2006.173.18:19:02.96#ibcon#read 4, iclass 38, count 2 2006.173.18:19:02.96#ibcon#about to read 5, iclass 38, count 2 2006.173.18:19:02.96#ibcon#read 5, iclass 38, count 2 2006.173.18:19:02.96#ibcon#about to read 6, iclass 38, count 2 2006.173.18:19:02.96#ibcon#read 6, iclass 38, count 2 2006.173.18:19:02.96#ibcon#end of sib2, iclass 38, count 2 2006.173.18:19:02.96#ibcon#*mode == 0, iclass 38, count 2 2006.173.18:19:02.96#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.18:19:02.96#ibcon#[27=AT04-04\r\n] 2006.173.18:19:02.96#ibcon#*before write, iclass 38, count 2 2006.173.18:19:02.96#ibcon#enter sib2, iclass 38, count 2 2006.173.18:19:02.96#ibcon#flushed, iclass 38, count 2 2006.173.18:19:02.96#ibcon#about to write, iclass 38, count 2 2006.173.18:19:02.96#ibcon#wrote, iclass 38, count 2 2006.173.18:19:02.96#ibcon#about to read 3, iclass 38, count 2 2006.173.18:19:02.97#abcon#{5=INTERFACE CLEAR} 2006.173.18:19:02.99#ibcon#read 3, iclass 38, count 2 2006.173.18:19:02.99#ibcon#about to read 4, iclass 38, count 2 2006.173.18:19:02.99#ibcon#read 4, iclass 38, count 2 2006.173.18:19:02.99#ibcon#about to read 5, iclass 38, count 2 2006.173.18:19:02.99#ibcon#read 5, iclass 38, count 2 2006.173.18:19:02.99#ibcon#about to read 6, iclass 38, count 2 2006.173.18:19:02.99#ibcon#read 6, iclass 38, count 2 2006.173.18:19:02.99#ibcon#end of sib2, iclass 38, count 2 2006.173.18:19:02.99#ibcon#*after write, iclass 38, count 2 2006.173.18:19:02.99#ibcon#*before return 0, iclass 38, count 2 2006.173.18:19:02.99#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.18:19:02.99#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.18:19:02.99#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.18:19:02.99#ibcon#ireg 7 cls_cnt 0 2006.173.18:19:02.99#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.18:19:03.03#abcon#[5=S1D000X0/0*\r\n] 2006.173.18:19:03.11#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.18:19:03.11#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.18:19:03.11#ibcon#enter wrdev, iclass 38, count 0 2006.173.18:19:03.11#ibcon#first serial, iclass 38, count 0 2006.173.18:19:03.11#ibcon#enter sib2, iclass 38, count 0 2006.173.18:19:03.11#ibcon#flushed, iclass 38, count 0 2006.173.18:19:03.11#ibcon#about to write, iclass 38, count 0 2006.173.18:19:03.11#ibcon#wrote, iclass 38, count 0 2006.173.18:19:03.11#ibcon#about to read 3, iclass 38, count 0 2006.173.18:19:03.13#ibcon#read 3, iclass 38, count 0 2006.173.18:19:03.13#ibcon#about to read 4, iclass 38, count 0 2006.173.18:19:03.13#ibcon#read 4, iclass 38, count 0 2006.173.18:19:03.13#ibcon#about to read 5, iclass 38, count 0 2006.173.18:19:03.13#ibcon#read 5, iclass 38, count 0 2006.173.18:19:03.13#ibcon#about to read 6, iclass 38, count 0 2006.173.18:19:03.13#ibcon#read 6, iclass 38, count 0 2006.173.18:19:03.13#ibcon#end of sib2, iclass 38, count 0 2006.173.18:19:03.13#ibcon#*mode == 0, iclass 38, count 0 2006.173.18:19:03.13#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.18:19:03.13#ibcon#[27=USB\r\n] 2006.173.18:19:03.13#ibcon#*before write, iclass 38, count 0 2006.173.18:19:03.13#ibcon#enter sib2, iclass 38, count 0 2006.173.18:19:03.13#ibcon#flushed, iclass 38, count 0 2006.173.18:19:03.13#ibcon#about to write, iclass 38, count 0 2006.173.18:19:03.13#ibcon#wrote, iclass 38, count 0 2006.173.18:19:03.13#ibcon#about to read 3, iclass 38, count 0 2006.173.18:19:03.16#ibcon#read 3, iclass 38, count 0 2006.173.18:19:03.16#ibcon#about to read 4, iclass 38, count 0 2006.173.18:19:03.16#ibcon#read 4, iclass 38, count 0 2006.173.18:19:03.16#ibcon#about to read 5, iclass 38, count 0 2006.173.18:19:03.16#ibcon#read 5, iclass 38, count 0 2006.173.18:19:03.16#ibcon#about to read 6, iclass 38, count 0 2006.173.18:19:03.16#ibcon#read 6, iclass 38, count 0 2006.173.18:19:03.16#ibcon#end of sib2, iclass 38, count 0 2006.173.18:19:03.16#ibcon#*after write, iclass 38, count 0 2006.173.18:19:03.16#ibcon#*before return 0, iclass 38, count 0 2006.173.18:19:03.16#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.18:19:03.16#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.18:19:03.16#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.18:19:03.16#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.18:19:03.16$vck44/vblo=5,709.99 2006.173.18:19:03.16#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.18:19:03.16#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.18:19:03.16#ibcon#ireg 17 cls_cnt 0 2006.173.18:19:03.16#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.18:19:03.16#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.18:19:03.16#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.18:19:03.16#ibcon#enter wrdev, iclass 6, count 0 2006.173.18:19:03.16#ibcon#first serial, iclass 6, count 0 2006.173.18:19:03.16#ibcon#enter sib2, iclass 6, count 0 2006.173.18:19:03.16#ibcon#flushed, iclass 6, count 0 2006.173.18:19:03.16#ibcon#about to write, iclass 6, count 0 2006.173.18:19:03.16#ibcon#wrote, iclass 6, count 0 2006.173.18:19:03.16#ibcon#about to read 3, iclass 6, count 0 2006.173.18:19:03.18#ibcon#read 3, iclass 6, count 0 2006.173.18:19:03.18#ibcon#about to read 4, iclass 6, count 0 2006.173.18:19:03.18#ibcon#read 4, iclass 6, count 0 2006.173.18:19:03.18#ibcon#about to read 5, iclass 6, count 0 2006.173.18:19:03.18#ibcon#read 5, iclass 6, count 0 2006.173.18:19:03.18#ibcon#about to read 6, iclass 6, count 0 2006.173.18:19:03.18#ibcon#read 6, iclass 6, count 0 2006.173.18:19:03.18#ibcon#end of sib2, iclass 6, count 0 2006.173.18:19:03.18#ibcon#*mode == 0, iclass 6, count 0 2006.173.18:19:03.18#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.18:19:03.18#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.18:19:03.18#ibcon#*before write, iclass 6, count 0 2006.173.18:19:03.18#ibcon#enter sib2, iclass 6, count 0 2006.173.18:19:03.18#ibcon#flushed, iclass 6, count 0 2006.173.18:19:03.18#ibcon#about to write, iclass 6, count 0 2006.173.18:19:03.18#ibcon#wrote, iclass 6, count 0 2006.173.18:19:03.18#ibcon#about to read 3, iclass 6, count 0 2006.173.18:19:03.22#ibcon#read 3, iclass 6, count 0 2006.173.18:19:03.22#ibcon#about to read 4, iclass 6, count 0 2006.173.18:19:03.22#ibcon#read 4, iclass 6, count 0 2006.173.18:19:03.22#ibcon#about to read 5, iclass 6, count 0 2006.173.18:19:03.22#ibcon#read 5, iclass 6, count 0 2006.173.18:19:03.22#ibcon#about to read 6, iclass 6, count 0 2006.173.18:19:03.22#ibcon#read 6, iclass 6, count 0 2006.173.18:19:03.22#ibcon#end of sib2, iclass 6, count 0 2006.173.18:19:03.22#ibcon#*after write, iclass 6, count 0 2006.173.18:19:03.22#ibcon#*before return 0, iclass 6, count 0 2006.173.18:19:03.22#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.18:19:03.22#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.18:19:03.22#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.18:19:03.22#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.18:19:03.22$vck44/vb=5,4 2006.173.18:19:03.22#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.18:19:03.22#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.18:19:03.22#ibcon#ireg 11 cls_cnt 2 2006.173.18:19:03.22#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.18:19:03.28#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.18:19:03.28#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.18:19:03.28#ibcon#enter wrdev, iclass 10, count 2 2006.173.18:19:03.28#ibcon#first serial, iclass 10, count 2 2006.173.18:19:03.28#ibcon#enter sib2, iclass 10, count 2 2006.173.18:19:03.28#ibcon#flushed, iclass 10, count 2 2006.173.18:19:03.28#ibcon#about to write, iclass 10, count 2 2006.173.18:19:03.28#ibcon#wrote, iclass 10, count 2 2006.173.18:19:03.28#ibcon#about to read 3, iclass 10, count 2 2006.173.18:19:03.30#ibcon#read 3, iclass 10, count 2 2006.173.18:19:03.30#ibcon#about to read 4, iclass 10, count 2 2006.173.18:19:03.30#ibcon#read 4, iclass 10, count 2 2006.173.18:19:03.30#ibcon#about to read 5, iclass 10, count 2 2006.173.18:19:03.30#ibcon#read 5, iclass 10, count 2 2006.173.18:19:03.30#ibcon#about to read 6, iclass 10, count 2 2006.173.18:19:03.30#ibcon#read 6, iclass 10, count 2 2006.173.18:19:03.30#ibcon#end of sib2, iclass 10, count 2 2006.173.18:19:03.30#ibcon#*mode == 0, iclass 10, count 2 2006.173.18:19:03.30#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.18:19:03.30#ibcon#[27=AT05-04\r\n] 2006.173.18:19:03.30#ibcon#*before write, iclass 10, count 2 2006.173.18:19:03.30#ibcon#enter sib2, iclass 10, count 2 2006.173.18:19:03.30#ibcon#flushed, iclass 10, count 2 2006.173.18:19:03.30#ibcon#about to write, iclass 10, count 2 2006.173.18:19:03.30#ibcon#wrote, iclass 10, count 2 2006.173.18:19:03.30#ibcon#about to read 3, iclass 10, count 2 2006.173.18:19:03.33#ibcon#read 3, iclass 10, count 2 2006.173.18:19:03.33#ibcon#about to read 4, iclass 10, count 2 2006.173.18:19:03.33#ibcon#read 4, iclass 10, count 2 2006.173.18:19:03.33#ibcon#about to read 5, iclass 10, count 2 2006.173.18:19:03.33#ibcon#read 5, iclass 10, count 2 2006.173.18:19:03.33#ibcon#about to read 6, iclass 10, count 2 2006.173.18:19:03.33#ibcon#read 6, iclass 10, count 2 2006.173.18:19:03.33#ibcon#end of sib2, iclass 10, count 2 2006.173.18:19:03.33#ibcon#*after write, iclass 10, count 2 2006.173.18:19:03.33#ibcon#*before return 0, iclass 10, count 2 2006.173.18:19:03.33#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.18:19:03.33#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.18:19:03.33#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.18:19:03.33#ibcon#ireg 7 cls_cnt 0 2006.173.18:19:03.33#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.18:19:03.45#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.18:19:03.45#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.18:19:03.45#ibcon#enter wrdev, iclass 10, count 0 2006.173.18:19:03.45#ibcon#first serial, iclass 10, count 0 2006.173.18:19:03.45#ibcon#enter sib2, iclass 10, count 0 2006.173.18:19:03.45#ibcon#flushed, iclass 10, count 0 2006.173.18:19:03.45#ibcon#about to write, iclass 10, count 0 2006.173.18:19:03.45#ibcon#wrote, iclass 10, count 0 2006.173.18:19:03.45#ibcon#about to read 3, iclass 10, count 0 2006.173.18:19:03.47#ibcon#read 3, iclass 10, count 0 2006.173.18:19:03.47#ibcon#about to read 4, iclass 10, count 0 2006.173.18:19:03.47#ibcon#read 4, iclass 10, count 0 2006.173.18:19:03.47#ibcon#about to read 5, iclass 10, count 0 2006.173.18:19:03.47#ibcon#read 5, iclass 10, count 0 2006.173.18:19:03.47#ibcon#about to read 6, iclass 10, count 0 2006.173.18:19:03.47#ibcon#read 6, iclass 10, count 0 2006.173.18:19:03.47#ibcon#end of sib2, iclass 10, count 0 2006.173.18:19:03.47#ibcon#*mode == 0, iclass 10, count 0 2006.173.18:19:03.47#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.18:19:03.47#ibcon#[27=USB\r\n] 2006.173.18:19:03.47#ibcon#*before write, iclass 10, count 0 2006.173.18:19:03.47#ibcon#enter sib2, iclass 10, count 0 2006.173.18:19:03.47#ibcon#flushed, iclass 10, count 0 2006.173.18:19:03.47#ibcon#about to write, iclass 10, count 0 2006.173.18:19:03.47#ibcon#wrote, iclass 10, count 0 2006.173.18:19:03.47#ibcon#about to read 3, iclass 10, count 0 2006.173.18:19:03.50#ibcon#read 3, iclass 10, count 0 2006.173.18:19:03.50#ibcon#about to read 4, iclass 10, count 0 2006.173.18:19:03.50#ibcon#read 4, iclass 10, count 0 2006.173.18:19:03.50#ibcon#about to read 5, iclass 10, count 0 2006.173.18:19:03.50#ibcon#read 5, iclass 10, count 0 2006.173.18:19:03.50#ibcon#about to read 6, iclass 10, count 0 2006.173.18:19:03.50#ibcon#read 6, iclass 10, count 0 2006.173.18:19:03.50#ibcon#end of sib2, iclass 10, count 0 2006.173.18:19:03.50#ibcon#*after write, iclass 10, count 0 2006.173.18:19:03.50#ibcon#*before return 0, iclass 10, count 0 2006.173.18:19:03.50#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.18:19:03.50#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.18:19:03.50#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.18:19:03.50#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.18:19:03.50$vck44/vblo=6,719.99 2006.173.18:19:03.50#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.18:19:03.50#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.18:19:03.50#ibcon#ireg 17 cls_cnt 0 2006.173.18:19:03.50#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.18:19:03.50#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.18:19:03.50#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.18:19:03.50#ibcon#enter wrdev, iclass 12, count 0 2006.173.18:19:03.50#ibcon#first serial, iclass 12, count 0 2006.173.18:19:03.50#ibcon#enter sib2, iclass 12, count 0 2006.173.18:19:03.50#ibcon#flushed, iclass 12, count 0 2006.173.18:19:03.50#ibcon#about to write, iclass 12, count 0 2006.173.18:19:03.50#ibcon#wrote, iclass 12, count 0 2006.173.18:19:03.50#ibcon#about to read 3, iclass 12, count 0 2006.173.18:19:03.52#ibcon#read 3, iclass 12, count 0 2006.173.18:19:03.52#ibcon#about to read 4, iclass 12, count 0 2006.173.18:19:03.52#ibcon#read 4, iclass 12, count 0 2006.173.18:19:03.52#ibcon#about to read 5, iclass 12, count 0 2006.173.18:19:03.52#ibcon#read 5, iclass 12, count 0 2006.173.18:19:03.52#ibcon#about to read 6, iclass 12, count 0 2006.173.18:19:03.52#ibcon#read 6, iclass 12, count 0 2006.173.18:19:03.52#ibcon#end of sib2, iclass 12, count 0 2006.173.18:19:03.52#ibcon#*mode == 0, iclass 12, count 0 2006.173.18:19:03.52#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.18:19:03.52#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.18:19:03.52#ibcon#*before write, iclass 12, count 0 2006.173.18:19:03.52#ibcon#enter sib2, iclass 12, count 0 2006.173.18:19:03.52#ibcon#flushed, iclass 12, count 0 2006.173.18:19:03.52#ibcon#about to write, iclass 12, count 0 2006.173.18:19:03.52#ibcon#wrote, iclass 12, count 0 2006.173.18:19:03.52#ibcon#about to read 3, iclass 12, count 0 2006.173.18:19:03.56#ibcon#read 3, iclass 12, count 0 2006.173.18:19:03.56#ibcon#about to read 4, iclass 12, count 0 2006.173.18:19:03.56#ibcon#read 4, iclass 12, count 0 2006.173.18:19:03.56#ibcon#about to read 5, iclass 12, count 0 2006.173.18:19:03.56#ibcon#read 5, iclass 12, count 0 2006.173.18:19:03.56#ibcon#about to read 6, iclass 12, count 0 2006.173.18:19:03.56#ibcon#read 6, iclass 12, count 0 2006.173.18:19:03.56#ibcon#end of sib2, iclass 12, count 0 2006.173.18:19:03.56#ibcon#*after write, iclass 12, count 0 2006.173.18:19:03.56#ibcon#*before return 0, iclass 12, count 0 2006.173.18:19:03.56#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.18:19:03.56#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.18:19:03.56#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.18:19:03.56#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.18:19:03.56$vck44/vb=6,4 2006.173.18:19:03.56#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.18:19:03.56#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.18:19:03.56#ibcon#ireg 11 cls_cnt 2 2006.173.18:19:03.56#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.18:19:03.62#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.18:19:03.62#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.18:19:03.62#ibcon#enter wrdev, iclass 14, count 2 2006.173.18:19:03.62#ibcon#first serial, iclass 14, count 2 2006.173.18:19:03.62#ibcon#enter sib2, iclass 14, count 2 2006.173.18:19:03.62#ibcon#flushed, iclass 14, count 2 2006.173.18:19:03.62#ibcon#about to write, iclass 14, count 2 2006.173.18:19:03.62#ibcon#wrote, iclass 14, count 2 2006.173.18:19:03.62#ibcon#about to read 3, iclass 14, count 2 2006.173.18:19:03.64#ibcon#read 3, iclass 14, count 2 2006.173.18:19:03.64#ibcon#about to read 4, iclass 14, count 2 2006.173.18:19:03.64#ibcon#read 4, iclass 14, count 2 2006.173.18:19:03.64#ibcon#about to read 5, iclass 14, count 2 2006.173.18:19:03.64#ibcon#read 5, iclass 14, count 2 2006.173.18:19:03.64#ibcon#about to read 6, iclass 14, count 2 2006.173.18:19:03.64#ibcon#read 6, iclass 14, count 2 2006.173.18:19:03.64#ibcon#end of sib2, iclass 14, count 2 2006.173.18:19:03.64#ibcon#*mode == 0, iclass 14, count 2 2006.173.18:19:03.64#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.18:19:03.64#ibcon#[27=AT06-04\r\n] 2006.173.18:19:03.64#ibcon#*before write, iclass 14, count 2 2006.173.18:19:03.64#ibcon#enter sib2, iclass 14, count 2 2006.173.18:19:03.64#ibcon#flushed, iclass 14, count 2 2006.173.18:19:03.64#ibcon#about to write, iclass 14, count 2 2006.173.18:19:03.64#ibcon#wrote, iclass 14, count 2 2006.173.18:19:03.64#ibcon#about to read 3, iclass 14, count 2 2006.173.18:19:03.67#ibcon#read 3, iclass 14, count 2 2006.173.18:19:03.67#ibcon#about to read 4, iclass 14, count 2 2006.173.18:19:03.67#ibcon#read 4, iclass 14, count 2 2006.173.18:19:03.67#ibcon#about to read 5, iclass 14, count 2 2006.173.18:19:03.67#ibcon#read 5, iclass 14, count 2 2006.173.18:19:03.67#ibcon#about to read 6, iclass 14, count 2 2006.173.18:19:03.67#ibcon#read 6, iclass 14, count 2 2006.173.18:19:03.67#ibcon#end of sib2, iclass 14, count 2 2006.173.18:19:03.67#ibcon#*after write, iclass 14, count 2 2006.173.18:19:03.67#ibcon#*before return 0, iclass 14, count 2 2006.173.18:19:03.67#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.18:19:03.67#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.18:19:03.67#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.18:19:03.67#ibcon#ireg 7 cls_cnt 0 2006.173.18:19:03.67#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.18:19:03.79#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.18:19:03.79#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.18:19:03.79#ibcon#enter wrdev, iclass 14, count 0 2006.173.18:19:03.79#ibcon#first serial, iclass 14, count 0 2006.173.18:19:03.79#ibcon#enter sib2, iclass 14, count 0 2006.173.18:19:03.79#ibcon#flushed, iclass 14, count 0 2006.173.18:19:03.79#ibcon#about to write, iclass 14, count 0 2006.173.18:19:03.79#ibcon#wrote, iclass 14, count 0 2006.173.18:19:03.79#ibcon#about to read 3, iclass 14, count 0 2006.173.18:19:03.81#ibcon#read 3, iclass 14, count 0 2006.173.18:19:03.81#ibcon#about to read 4, iclass 14, count 0 2006.173.18:19:03.81#ibcon#read 4, iclass 14, count 0 2006.173.18:19:03.81#ibcon#about to read 5, iclass 14, count 0 2006.173.18:19:03.81#ibcon#read 5, iclass 14, count 0 2006.173.18:19:03.81#ibcon#about to read 6, iclass 14, count 0 2006.173.18:19:03.81#ibcon#read 6, iclass 14, count 0 2006.173.18:19:03.81#ibcon#end of sib2, iclass 14, count 0 2006.173.18:19:03.81#ibcon#*mode == 0, iclass 14, count 0 2006.173.18:19:03.81#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.18:19:03.81#ibcon#[27=USB\r\n] 2006.173.18:19:03.81#ibcon#*before write, iclass 14, count 0 2006.173.18:19:03.81#ibcon#enter sib2, iclass 14, count 0 2006.173.18:19:03.81#ibcon#flushed, iclass 14, count 0 2006.173.18:19:03.81#ibcon#about to write, iclass 14, count 0 2006.173.18:19:03.81#ibcon#wrote, iclass 14, count 0 2006.173.18:19:03.81#ibcon#about to read 3, iclass 14, count 0 2006.173.18:19:03.84#ibcon#read 3, iclass 14, count 0 2006.173.18:19:03.84#ibcon#about to read 4, iclass 14, count 0 2006.173.18:19:03.84#ibcon#read 4, iclass 14, count 0 2006.173.18:19:03.84#ibcon#about to read 5, iclass 14, count 0 2006.173.18:19:03.84#ibcon#read 5, iclass 14, count 0 2006.173.18:19:03.84#ibcon#about to read 6, iclass 14, count 0 2006.173.18:19:03.84#ibcon#read 6, iclass 14, count 0 2006.173.18:19:03.84#ibcon#end of sib2, iclass 14, count 0 2006.173.18:19:03.84#ibcon#*after write, iclass 14, count 0 2006.173.18:19:03.84#ibcon#*before return 0, iclass 14, count 0 2006.173.18:19:03.84#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.18:19:03.84#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.18:19:03.84#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.18:19:03.84#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.18:19:03.84$vck44/vblo=7,734.99 2006.173.18:19:03.84#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.18:19:03.84#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.18:19:03.84#ibcon#ireg 17 cls_cnt 0 2006.173.18:19:03.84#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.18:19:03.84#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.18:19:03.84#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.18:19:03.84#ibcon#enter wrdev, iclass 16, count 0 2006.173.18:19:03.84#ibcon#first serial, iclass 16, count 0 2006.173.18:19:03.84#ibcon#enter sib2, iclass 16, count 0 2006.173.18:19:03.84#ibcon#flushed, iclass 16, count 0 2006.173.18:19:03.84#ibcon#about to write, iclass 16, count 0 2006.173.18:19:03.84#ibcon#wrote, iclass 16, count 0 2006.173.18:19:03.84#ibcon#about to read 3, iclass 16, count 0 2006.173.18:19:03.86#ibcon#read 3, iclass 16, count 0 2006.173.18:19:03.86#ibcon#about to read 4, iclass 16, count 0 2006.173.18:19:03.86#ibcon#read 4, iclass 16, count 0 2006.173.18:19:03.86#ibcon#about to read 5, iclass 16, count 0 2006.173.18:19:03.86#ibcon#read 5, iclass 16, count 0 2006.173.18:19:03.86#ibcon#about to read 6, iclass 16, count 0 2006.173.18:19:03.86#ibcon#read 6, iclass 16, count 0 2006.173.18:19:03.86#ibcon#end of sib2, iclass 16, count 0 2006.173.18:19:03.86#ibcon#*mode == 0, iclass 16, count 0 2006.173.18:19:03.86#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.18:19:03.86#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.18:19:03.86#ibcon#*before write, iclass 16, count 0 2006.173.18:19:03.86#ibcon#enter sib2, iclass 16, count 0 2006.173.18:19:03.86#ibcon#flushed, iclass 16, count 0 2006.173.18:19:03.86#ibcon#about to write, iclass 16, count 0 2006.173.18:19:03.86#ibcon#wrote, iclass 16, count 0 2006.173.18:19:03.86#ibcon#about to read 3, iclass 16, count 0 2006.173.18:19:03.90#ibcon#read 3, iclass 16, count 0 2006.173.18:19:03.90#ibcon#about to read 4, iclass 16, count 0 2006.173.18:19:03.90#ibcon#read 4, iclass 16, count 0 2006.173.18:19:03.90#ibcon#about to read 5, iclass 16, count 0 2006.173.18:19:03.90#ibcon#read 5, iclass 16, count 0 2006.173.18:19:03.90#ibcon#about to read 6, iclass 16, count 0 2006.173.18:19:03.90#ibcon#read 6, iclass 16, count 0 2006.173.18:19:03.90#ibcon#end of sib2, iclass 16, count 0 2006.173.18:19:03.90#ibcon#*after write, iclass 16, count 0 2006.173.18:19:03.90#ibcon#*before return 0, iclass 16, count 0 2006.173.18:19:03.90#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.18:19:03.90#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.18:19:03.90#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.18:19:03.90#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.18:19:03.90$vck44/vb=7,4 2006.173.18:19:03.90#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.18:19:03.90#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.18:19:03.90#ibcon#ireg 11 cls_cnt 2 2006.173.18:19:03.90#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.18:19:03.96#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.18:19:03.96#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.18:19:03.96#ibcon#enter wrdev, iclass 18, count 2 2006.173.18:19:03.96#ibcon#first serial, iclass 18, count 2 2006.173.18:19:03.96#ibcon#enter sib2, iclass 18, count 2 2006.173.18:19:03.96#ibcon#flushed, iclass 18, count 2 2006.173.18:19:03.96#ibcon#about to write, iclass 18, count 2 2006.173.18:19:03.96#ibcon#wrote, iclass 18, count 2 2006.173.18:19:03.96#ibcon#about to read 3, iclass 18, count 2 2006.173.18:19:03.98#ibcon#read 3, iclass 18, count 2 2006.173.18:19:03.98#ibcon#about to read 4, iclass 18, count 2 2006.173.18:19:03.98#ibcon#read 4, iclass 18, count 2 2006.173.18:19:03.98#ibcon#about to read 5, iclass 18, count 2 2006.173.18:19:03.98#ibcon#read 5, iclass 18, count 2 2006.173.18:19:03.98#ibcon#about to read 6, iclass 18, count 2 2006.173.18:19:03.98#ibcon#read 6, iclass 18, count 2 2006.173.18:19:03.98#ibcon#end of sib2, iclass 18, count 2 2006.173.18:19:03.98#ibcon#*mode == 0, iclass 18, count 2 2006.173.18:19:03.98#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.18:19:03.98#ibcon#[27=AT07-04\r\n] 2006.173.18:19:03.98#ibcon#*before write, iclass 18, count 2 2006.173.18:19:03.98#ibcon#enter sib2, iclass 18, count 2 2006.173.18:19:03.98#ibcon#flushed, iclass 18, count 2 2006.173.18:19:03.98#ibcon#about to write, iclass 18, count 2 2006.173.18:19:03.98#ibcon#wrote, iclass 18, count 2 2006.173.18:19:03.98#ibcon#about to read 3, iclass 18, count 2 2006.173.18:19:04.01#ibcon#read 3, iclass 18, count 2 2006.173.18:19:04.01#ibcon#about to read 4, iclass 18, count 2 2006.173.18:19:04.01#ibcon#read 4, iclass 18, count 2 2006.173.18:19:04.01#ibcon#about to read 5, iclass 18, count 2 2006.173.18:19:04.01#ibcon#read 5, iclass 18, count 2 2006.173.18:19:04.01#ibcon#about to read 6, iclass 18, count 2 2006.173.18:19:04.01#ibcon#read 6, iclass 18, count 2 2006.173.18:19:04.01#ibcon#end of sib2, iclass 18, count 2 2006.173.18:19:04.01#ibcon#*after write, iclass 18, count 2 2006.173.18:19:04.01#ibcon#*before return 0, iclass 18, count 2 2006.173.18:19:04.01#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.18:19:04.01#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.18:19:04.01#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.18:19:04.01#ibcon#ireg 7 cls_cnt 0 2006.173.18:19:04.01#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.18:19:04.13#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.18:19:04.13#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.18:19:04.13#ibcon#enter wrdev, iclass 18, count 0 2006.173.18:19:04.13#ibcon#first serial, iclass 18, count 0 2006.173.18:19:04.13#ibcon#enter sib2, iclass 18, count 0 2006.173.18:19:04.13#ibcon#flushed, iclass 18, count 0 2006.173.18:19:04.13#ibcon#about to write, iclass 18, count 0 2006.173.18:19:04.13#ibcon#wrote, iclass 18, count 0 2006.173.18:19:04.13#ibcon#about to read 3, iclass 18, count 0 2006.173.18:19:04.15#ibcon#read 3, iclass 18, count 0 2006.173.18:19:04.15#ibcon#about to read 4, iclass 18, count 0 2006.173.18:19:04.15#ibcon#read 4, iclass 18, count 0 2006.173.18:19:04.15#ibcon#about to read 5, iclass 18, count 0 2006.173.18:19:04.15#ibcon#read 5, iclass 18, count 0 2006.173.18:19:04.15#ibcon#about to read 6, iclass 18, count 0 2006.173.18:19:04.15#ibcon#read 6, iclass 18, count 0 2006.173.18:19:04.15#ibcon#end of sib2, iclass 18, count 0 2006.173.18:19:04.15#ibcon#*mode == 0, iclass 18, count 0 2006.173.18:19:04.15#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.18:19:04.15#ibcon#[27=USB\r\n] 2006.173.18:19:04.15#ibcon#*before write, iclass 18, count 0 2006.173.18:19:04.15#ibcon#enter sib2, iclass 18, count 0 2006.173.18:19:04.15#ibcon#flushed, iclass 18, count 0 2006.173.18:19:04.15#ibcon#about to write, iclass 18, count 0 2006.173.18:19:04.15#ibcon#wrote, iclass 18, count 0 2006.173.18:19:04.15#ibcon#about to read 3, iclass 18, count 0 2006.173.18:19:04.18#ibcon#read 3, iclass 18, count 0 2006.173.18:19:04.18#ibcon#about to read 4, iclass 18, count 0 2006.173.18:19:04.18#ibcon#read 4, iclass 18, count 0 2006.173.18:19:04.18#ibcon#about to read 5, iclass 18, count 0 2006.173.18:19:04.18#ibcon#read 5, iclass 18, count 0 2006.173.18:19:04.18#ibcon#about to read 6, iclass 18, count 0 2006.173.18:19:04.18#ibcon#read 6, iclass 18, count 0 2006.173.18:19:04.18#ibcon#end of sib2, iclass 18, count 0 2006.173.18:19:04.18#ibcon#*after write, iclass 18, count 0 2006.173.18:19:04.18#ibcon#*before return 0, iclass 18, count 0 2006.173.18:19:04.18#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.18:19:04.18#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.18:19:04.18#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.18:19:04.18#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.18:19:04.18$vck44/vblo=8,744.99 2006.173.18:19:04.18#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.18:19:04.18#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.18:19:04.18#ibcon#ireg 17 cls_cnt 0 2006.173.18:19:04.18#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.18:19:04.18#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.18:19:04.18#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.18:19:04.18#ibcon#enter wrdev, iclass 20, count 0 2006.173.18:19:04.18#ibcon#first serial, iclass 20, count 0 2006.173.18:19:04.18#ibcon#enter sib2, iclass 20, count 0 2006.173.18:19:04.18#ibcon#flushed, iclass 20, count 0 2006.173.18:19:04.18#ibcon#about to write, iclass 20, count 0 2006.173.18:19:04.18#ibcon#wrote, iclass 20, count 0 2006.173.18:19:04.18#ibcon#about to read 3, iclass 20, count 0 2006.173.18:19:04.20#ibcon#read 3, iclass 20, count 0 2006.173.18:19:04.20#ibcon#about to read 4, iclass 20, count 0 2006.173.18:19:04.20#ibcon#read 4, iclass 20, count 0 2006.173.18:19:04.20#ibcon#about to read 5, iclass 20, count 0 2006.173.18:19:04.20#ibcon#read 5, iclass 20, count 0 2006.173.18:19:04.20#ibcon#about to read 6, iclass 20, count 0 2006.173.18:19:04.20#ibcon#read 6, iclass 20, count 0 2006.173.18:19:04.20#ibcon#end of sib2, iclass 20, count 0 2006.173.18:19:04.20#ibcon#*mode == 0, iclass 20, count 0 2006.173.18:19:04.20#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.18:19:04.20#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.18:19:04.20#ibcon#*before write, iclass 20, count 0 2006.173.18:19:04.20#ibcon#enter sib2, iclass 20, count 0 2006.173.18:19:04.20#ibcon#flushed, iclass 20, count 0 2006.173.18:19:04.20#ibcon#about to write, iclass 20, count 0 2006.173.18:19:04.20#ibcon#wrote, iclass 20, count 0 2006.173.18:19:04.20#ibcon#about to read 3, iclass 20, count 0 2006.173.18:19:04.24#ibcon#read 3, iclass 20, count 0 2006.173.18:19:04.24#ibcon#about to read 4, iclass 20, count 0 2006.173.18:19:04.24#ibcon#read 4, iclass 20, count 0 2006.173.18:19:04.24#ibcon#about to read 5, iclass 20, count 0 2006.173.18:19:04.24#ibcon#read 5, iclass 20, count 0 2006.173.18:19:04.24#ibcon#about to read 6, iclass 20, count 0 2006.173.18:19:04.24#ibcon#read 6, iclass 20, count 0 2006.173.18:19:04.24#ibcon#end of sib2, iclass 20, count 0 2006.173.18:19:04.24#ibcon#*after write, iclass 20, count 0 2006.173.18:19:04.24#ibcon#*before return 0, iclass 20, count 0 2006.173.18:19:04.24#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.18:19:04.24#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.18:19:04.24#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.18:19:04.24#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.18:19:04.24$vck44/vb=8,4 2006.173.18:19:04.24#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.18:19:04.24#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.18:19:04.24#ibcon#ireg 11 cls_cnt 2 2006.173.18:19:04.24#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.18:19:04.30#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.18:19:04.30#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.18:19:04.30#ibcon#enter wrdev, iclass 22, count 2 2006.173.18:19:04.30#ibcon#first serial, iclass 22, count 2 2006.173.18:19:04.30#ibcon#enter sib2, iclass 22, count 2 2006.173.18:19:04.30#ibcon#flushed, iclass 22, count 2 2006.173.18:19:04.30#ibcon#about to write, iclass 22, count 2 2006.173.18:19:04.30#ibcon#wrote, iclass 22, count 2 2006.173.18:19:04.30#ibcon#about to read 3, iclass 22, count 2 2006.173.18:19:04.32#ibcon#read 3, iclass 22, count 2 2006.173.18:19:04.32#ibcon#about to read 4, iclass 22, count 2 2006.173.18:19:04.32#ibcon#read 4, iclass 22, count 2 2006.173.18:19:04.32#ibcon#about to read 5, iclass 22, count 2 2006.173.18:19:04.32#ibcon#read 5, iclass 22, count 2 2006.173.18:19:04.32#ibcon#about to read 6, iclass 22, count 2 2006.173.18:19:04.32#ibcon#read 6, iclass 22, count 2 2006.173.18:19:04.32#ibcon#end of sib2, iclass 22, count 2 2006.173.18:19:04.32#ibcon#*mode == 0, iclass 22, count 2 2006.173.18:19:04.32#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.18:19:04.32#ibcon#[27=AT08-04\r\n] 2006.173.18:19:04.32#ibcon#*before write, iclass 22, count 2 2006.173.18:19:04.32#ibcon#enter sib2, iclass 22, count 2 2006.173.18:19:04.32#ibcon#flushed, iclass 22, count 2 2006.173.18:19:04.32#ibcon#about to write, iclass 22, count 2 2006.173.18:19:04.32#ibcon#wrote, iclass 22, count 2 2006.173.18:19:04.32#ibcon#about to read 3, iclass 22, count 2 2006.173.18:19:04.35#ibcon#read 3, iclass 22, count 2 2006.173.18:19:04.35#ibcon#about to read 4, iclass 22, count 2 2006.173.18:19:04.35#ibcon#read 4, iclass 22, count 2 2006.173.18:19:04.35#ibcon#about to read 5, iclass 22, count 2 2006.173.18:19:04.35#ibcon#read 5, iclass 22, count 2 2006.173.18:19:04.35#ibcon#about to read 6, iclass 22, count 2 2006.173.18:19:04.35#ibcon#read 6, iclass 22, count 2 2006.173.18:19:04.35#ibcon#end of sib2, iclass 22, count 2 2006.173.18:19:04.35#ibcon#*after write, iclass 22, count 2 2006.173.18:19:04.35#ibcon#*before return 0, iclass 22, count 2 2006.173.18:19:04.35#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.18:19:04.35#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.18:19:04.35#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.18:19:04.35#ibcon#ireg 7 cls_cnt 0 2006.173.18:19:04.35#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.18:19:04.47#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.18:19:04.47#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.18:19:04.47#ibcon#enter wrdev, iclass 22, count 0 2006.173.18:19:04.47#ibcon#first serial, iclass 22, count 0 2006.173.18:19:04.47#ibcon#enter sib2, iclass 22, count 0 2006.173.18:19:04.47#ibcon#flushed, iclass 22, count 0 2006.173.18:19:04.47#ibcon#about to write, iclass 22, count 0 2006.173.18:19:04.47#ibcon#wrote, iclass 22, count 0 2006.173.18:19:04.47#ibcon#about to read 3, iclass 22, count 0 2006.173.18:19:04.49#ibcon#read 3, iclass 22, count 0 2006.173.18:19:04.49#ibcon#about to read 4, iclass 22, count 0 2006.173.18:19:04.49#ibcon#read 4, iclass 22, count 0 2006.173.18:19:04.49#ibcon#about to read 5, iclass 22, count 0 2006.173.18:19:04.49#ibcon#read 5, iclass 22, count 0 2006.173.18:19:04.49#ibcon#about to read 6, iclass 22, count 0 2006.173.18:19:04.49#ibcon#read 6, iclass 22, count 0 2006.173.18:19:04.49#ibcon#end of sib2, iclass 22, count 0 2006.173.18:19:04.49#ibcon#*mode == 0, iclass 22, count 0 2006.173.18:19:04.49#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.18:19:04.49#ibcon#[27=USB\r\n] 2006.173.18:19:04.49#ibcon#*before write, iclass 22, count 0 2006.173.18:19:04.49#ibcon#enter sib2, iclass 22, count 0 2006.173.18:19:04.49#ibcon#flushed, iclass 22, count 0 2006.173.18:19:04.49#ibcon#about to write, iclass 22, count 0 2006.173.18:19:04.49#ibcon#wrote, iclass 22, count 0 2006.173.18:19:04.49#ibcon#about to read 3, iclass 22, count 0 2006.173.18:19:04.52#ibcon#read 3, iclass 22, count 0 2006.173.18:19:04.52#ibcon#about to read 4, iclass 22, count 0 2006.173.18:19:04.52#ibcon#read 4, iclass 22, count 0 2006.173.18:19:04.52#ibcon#about to read 5, iclass 22, count 0 2006.173.18:19:04.52#ibcon#read 5, iclass 22, count 0 2006.173.18:19:04.52#ibcon#about to read 6, iclass 22, count 0 2006.173.18:19:04.52#ibcon#read 6, iclass 22, count 0 2006.173.18:19:04.52#ibcon#end of sib2, iclass 22, count 0 2006.173.18:19:04.52#ibcon#*after write, iclass 22, count 0 2006.173.18:19:04.52#ibcon#*before return 0, iclass 22, count 0 2006.173.18:19:04.52#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.18:19:04.52#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.18:19:04.52#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.18:19:04.52#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.18:19:04.52$vck44/vabw=wide 2006.173.18:19:04.52#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.18:19:04.52#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.18:19:04.52#ibcon#ireg 8 cls_cnt 0 2006.173.18:19:04.52#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.18:19:04.52#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.18:19:04.52#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.18:19:04.52#ibcon#enter wrdev, iclass 24, count 0 2006.173.18:19:04.52#ibcon#first serial, iclass 24, count 0 2006.173.18:19:04.52#ibcon#enter sib2, iclass 24, count 0 2006.173.18:19:04.52#ibcon#flushed, iclass 24, count 0 2006.173.18:19:04.52#ibcon#about to write, iclass 24, count 0 2006.173.18:19:04.52#ibcon#wrote, iclass 24, count 0 2006.173.18:19:04.52#ibcon#about to read 3, iclass 24, count 0 2006.173.18:19:04.54#ibcon#read 3, iclass 24, count 0 2006.173.18:19:04.54#ibcon#about to read 4, iclass 24, count 0 2006.173.18:19:04.54#ibcon#read 4, iclass 24, count 0 2006.173.18:19:04.54#ibcon#about to read 5, iclass 24, count 0 2006.173.18:19:04.54#ibcon#read 5, iclass 24, count 0 2006.173.18:19:04.54#ibcon#about to read 6, iclass 24, count 0 2006.173.18:19:04.54#ibcon#read 6, iclass 24, count 0 2006.173.18:19:04.54#ibcon#end of sib2, iclass 24, count 0 2006.173.18:19:04.54#ibcon#*mode == 0, iclass 24, count 0 2006.173.18:19:04.54#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.18:19:04.54#ibcon#[25=BW32\r\n] 2006.173.18:19:04.54#ibcon#*before write, iclass 24, count 0 2006.173.18:19:04.54#ibcon#enter sib2, iclass 24, count 0 2006.173.18:19:04.54#ibcon#flushed, iclass 24, count 0 2006.173.18:19:04.54#ibcon#about to write, iclass 24, count 0 2006.173.18:19:04.54#ibcon#wrote, iclass 24, count 0 2006.173.18:19:04.54#ibcon#about to read 3, iclass 24, count 0 2006.173.18:19:04.57#ibcon#read 3, iclass 24, count 0 2006.173.18:19:04.57#ibcon#about to read 4, iclass 24, count 0 2006.173.18:19:04.57#ibcon#read 4, iclass 24, count 0 2006.173.18:19:04.57#ibcon#about to read 5, iclass 24, count 0 2006.173.18:19:04.57#ibcon#read 5, iclass 24, count 0 2006.173.18:19:04.57#ibcon#about to read 6, iclass 24, count 0 2006.173.18:19:04.57#ibcon#read 6, iclass 24, count 0 2006.173.18:19:04.57#ibcon#end of sib2, iclass 24, count 0 2006.173.18:19:04.57#ibcon#*after write, iclass 24, count 0 2006.173.18:19:04.57#ibcon#*before return 0, iclass 24, count 0 2006.173.18:19:04.57#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.18:19:04.57#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.18:19:04.57#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.18:19:04.57#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.18:19:04.57$vck44/vbbw=wide 2006.173.18:19:04.57#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.18:19:04.57#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.18:19:04.57#ibcon#ireg 8 cls_cnt 0 2006.173.18:19:04.57#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.18:19:04.64#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.18:19:04.64#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.18:19:04.64#ibcon#enter wrdev, iclass 26, count 0 2006.173.18:19:04.64#ibcon#first serial, iclass 26, count 0 2006.173.18:19:04.64#ibcon#enter sib2, iclass 26, count 0 2006.173.18:19:04.64#ibcon#flushed, iclass 26, count 0 2006.173.18:19:04.64#ibcon#about to write, iclass 26, count 0 2006.173.18:19:04.64#ibcon#wrote, iclass 26, count 0 2006.173.18:19:04.64#ibcon#about to read 3, iclass 26, count 0 2006.173.18:19:04.66#ibcon#read 3, iclass 26, count 0 2006.173.18:19:04.66#ibcon#about to read 4, iclass 26, count 0 2006.173.18:19:04.66#ibcon#read 4, iclass 26, count 0 2006.173.18:19:04.66#ibcon#about to read 5, iclass 26, count 0 2006.173.18:19:04.66#ibcon#read 5, iclass 26, count 0 2006.173.18:19:04.66#ibcon#about to read 6, iclass 26, count 0 2006.173.18:19:04.66#ibcon#read 6, iclass 26, count 0 2006.173.18:19:04.66#ibcon#end of sib2, iclass 26, count 0 2006.173.18:19:04.66#ibcon#*mode == 0, iclass 26, count 0 2006.173.18:19:04.66#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.18:19:04.66#ibcon#[27=BW32\r\n] 2006.173.18:19:04.66#ibcon#*before write, iclass 26, count 0 2006.173.18:19:04.66#ibcon#enter sib2, iclass 26, count 0 2006.173.18:19:04.66#ibcon#flushed, iclass 26, count 0 2006.173.18:19:04.66#ibcon#about to write, iclass 26, count 0 2006.173.18:19:04.66#ibcon#wrote, iclass 26, count 0 2006.173.18:19:04.66#ibcon#about to read 3, iclass 26, count 0 2006.173.18:19:04.69#ibcon#read 3, iclass 26, count 0 2006.173.18:19:04.69#ibcon#about to read 4, iclass 26, count 0 2006.173.18:19:04.69#ibcon#read 4, iclass 26, count 0 2006.173.18:19:04.69#ibcon#about to read 5, iclass 26, count 0 2006.173.18:19:04.69#ibcon#read 5, iclass 26, count 0 2006.173.18:19:04.69#ibcon#about to read 6, iclass 26, count 0 2006.173.18:19:04.69#ibcon#read 6, iclass 26, count 0 2006.173.18:19:04.69#ibcon#end of sib2, iclass 26, count 0 2006.173.18:19:04.69#ibcon#*after write, iclass 26, count 0 2006.173.18:19:04.69#ibcon#*before return 0, iclass 26, count 0 2006.173.18:19:04.69#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.18:19:04.69#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.18:19:04.69#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.18:19:04.69#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.18:19:04.69$setupk4/ifdk4 2006.173.18:19:04.69$ifdk4/lo= 2006.173.18:19:04.69$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.18:19:04.69$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.18:19:04.69$ifdk4/patch= 2006.173.18:19:04.69$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.18:19:04.69$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.18:19:04.69$setupk4/!*+20s 2006.173.18:19:12.14#trakl#Source acquired 2006.173.18:19:13.12#abcon#<5=/14 1.0 2.2 19.981001002.2\r\n> 2006.173.18:19:13.14#abcon#{5=INTERFACE CLEAR} 2006.173.18:19:13.14#flagr#flagr/antenna,acquired 2006.173.18:19:13.20#abcon#[5=S1D000X0/0*\r\n] 2006.173.18:19:19.19$setupk4/"tpicd 2006.173.18:19:19.19$setupk4/echo=off 2006.173.18:19:19.19$setupk4/xlog=off 2006.173.18:19:19.19:!2006.173.18:19:19 2006.173.18:19:19.19:preob 2006.173.18:19:20.14/onsource/TRACKING 2006.173.18:19:20.14:!2006.173.18:19:29 2006.173.18:19:29.00:"tape 2006.173.18:19:29.00:"st=record 2006.173.18:19:29.00:data_valid=on 2006.173.18:19:29.00:midob 2006.173.18:19:29.14/onsource/TRACKING 2006.173.18:19:29.14/wx/19.98,1002.2,100 2006.173.18:19:29.24/cable/+6.5160E-03 2006.173.18:19:30.33/va/01,07,usb,yes,37,40 2006.173.18:19:30.33/va/02,06,usb,yes,37,38 2006.173.18:19:30.33/va/03,05,usb,yes,47,49 2006.173.18:19:30.33/va/04,06,usb,yes,38,40 2006.173.18:19:30.33/va/05,04,usb,yes,30,30 2006.173.18:19:30.33/va/06,03,usb,yes,42,41 2006.173.18:19:30.33/va/07,04,usb,yes,34,35 2006.173.18:19:30.33/va/08,04,usb,yes,29,35 2006.173.18:19:30.56/valo/01,524.99,yes,locked 2006.173.18:19:30.56/valo/02,534.99,yes,locked 2006.173.18:19:30.56/valo/03,564.99,yes,locked 2006.173.18:19:30.56/valo/04,624.99,yes,locked 2006.173.18:19:30.56/valo/05,734.99,yes,locked 2006.173.18:19:30.56/valo/06,814.99,yes,locked 2006.173.18:19:30.56/valo/07,864.99,yes,locked 2006.173.18:19:30.56/valo/08,884.99,yes,locked 2006.173.18:19:31.65/vb/01,04,usb,yes,30,28 2006.173.18:19:31.65/vb/02,04,usb,yes,32,32 2006.173.18:19:31.65/vb/03,04,usb,yes,29,32 2006.173.18:19:31.65/vb/04,04,usb,yes,33,32 2006.173.18:19:31.65/vb/05,04,usb,yes,26,28 2006.173.18:19:31.65/vb/06,04,usb,yes,31,27 2006.173.18:19:31.65/vb/07,04,usb,yes,30,30 2006.173.18:19:31.65/vb/08,04,usb,yes,28,31 2006.173.18:19:31.88/vblo/01,629.99,yes,locked 2006.173.18:19:31.88/vblo/02,634.99,yes,locked 2006.173.18:19:31.88/vblo/03,649.99,yes,locked 2006.173.18:19:31.88/vblo/04,679.99,yes,locked 2006.173.18:19:31.88/vblo/05,709.99,yes,locked 2006.173.18:19:31.88/vblo/06,719.99,yes,locked 2006.173.18:19:31.88/vblo/07,734.99,yes,locked 2006.173.18:19:31.88/vblo/08,744.99,yes,locked 2006.173.18:19:32.03/vabw/8 2006.173.18:19:32.18/vbbw/8 2006.173.18:19:32.27/xfe/off,on,16.0 2006.173.18:19:32.67/ifatt/23,28,28,28 2006.173.18:19:33.08/fmout-gps/S +4.00E-07 2006.173.18:19:33.12:!2006.173.18:29:39 2006.173.18:29:39.00:data_valid=off 2006.173.18:29:39.00:"et 2006.173.18:29:39.00:!+3s 2006.173.18:29:42.01:"tape 2006.173.18:29:42.01:postob 2006.173.18:29:42.17/cable/+6.5167E-03 2006.173.18:29:42.17/wx/19.90,1002.3,100 2006.173.18:29:43.08/fmout-gps/S +3.97E-07 2006.173.18:29:43.08:scan_name=173-1833,jd0606,40 2006.173.18:29:43.08:source=1741-038,174358.86,-035004.6,2000.0,ccw 2006.173.18:29:44.14#flagr#flagr/antenna,new-source 2006.173.18:29:44.14:checkk5 2006.173.18:29:44.57/chk_autoobs//k5ts1/ autoobs is running! 2006.173.18:29:44.98/chk_autoobs//k5ts2/ autoobs is running! 2006.173.18:29:45.40/chk_autoobs//k5ts3/ autoobs is running! 2006.173.18:29:45.80/chk_autoobs//k5ts4/ autoobs is running! 2006.173.18:29:46.51/chk_obsdata//k5ts1/T1731819??a.dat file size is correct (nominal:2440MB, actual:2436MB). 2006.173.18:29:47.22/chk_obsdata//k5ts2/T1731819??b.dat file size is correct (nominal:2440MB, actual:2436MB). 2006.173.18:29:47.93/chk_obsdata//k5ts3/T1731819??c.dat file size is correct (nominal:2440MB, actual:2436MB). 2006.173.18:29:48.65/chk_obsdata//k5ts4/T1731819??d.dat file size is correct (nominal:2440MB, actual:2436MB). 2006.173.18:29:49.40/k5log//k5ts1_log_newline 2006.173.18:29:50.11/k5log//k5ts2_log_newline 2006.173.18:29:50.86/k5log//k5ts3_log_newline 2006.173.18:29:51.57/k5log//k5ts4_log_newline 2006.173.18:29:51.59/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.18:29:51.59:setupk4=1 2006.173.18:29:51.59$setupk4/echo=on 2006.173.18:29:51.59$setupk4/pcalon 2006.173.18:29:51.59$pcalon/"no phase cal control is implemented here 2006.173.18:29:51.59$setupk4/"tpicd=stop 2006.173.18:29:51.59$setupk4/"rec=synch_on 2006.173.18:29:51.59$setupk4/"rec_mode=128 2006.173.18:29:51.59$setupk4/!* 2006.173.18:29:51.59$setupk4/recpk4 2006.173.18:29:51.59$recpk4/recpatch= 2006.173.18:29:51.60$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.18:29:51.60$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.18:29:51.60$setupk4/vck44 2006.173.18:29:51.60$vck44/valo=1,524.99 2006.173.18:29:51.60#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.18:29:51.60#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.18:29:51.60#ibcon#ireg 17 cls_cnt 0 2006.173.18:29:51.60#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.18:29:51.60#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.18:29:51.60#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.18:29:51.60#ibcon#enter wrdev, iclass 26, count 0 2006.173.18:29:51.60#ibcon#first serial, iclass 26, count 0 2006.173.18:29:51.60#ibcon#enter sib2, iclass 26, count 0 2006.173.18:29:51.60#ibcon#flushed, iclass 26, count 0 2006.173.18:29:51.60#ibcon#about to write, iclass 26, count 0 2006.173.18:29:51.60#ibcon#wrote, iclass 26, count 0 2006.173.18:29:51.60#ibcon#about to read 3, iclass 26, count 0 2006.173.18:29:51.62#ibcon#read 3, iclass 26, count 0 2006.173.18:29:51.62#ibcon#about to read 4, iclass 26, count 0 2006.173.18:29:51.62#ibcon#read 4, iclass 26, count 0 2006.173.18:29:51.62#ibcon#about to read 5, iclass 26, count 0 2006.173.18:29:51.62#ibcon#read 5, iclass 26, count 0 2006.173.18:29:51.62#ibcon#about to read 6, iclass 26, count 0 2006.173.18:29:51.62#ibcon#read 6, iclass 26, count 0 2006.173.18:29:51.62#ibcon#end of sib2, iclass 26, count 0 2006.173.18:29:51.62#ibcon#*mode == 0, iclass 26, count 0 2006.173.18:29:51.62#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.18:29:51.62#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.18:29:51.62#ibcon#*before write, iclass 26, count 0 2006.173.18:29:51.62#ibcon#enter sib2, iclass 26, count 0 2006.173.18:29:51.62#ibcon#flushed, iclass 26, count 0 2006.173.18:29:51.62#ibcon#about to write, iclass 26, count 0 2006.173.18:29:51.62#ibcon#wrote, iclass 26, count 0 2006.173.18:29:51.62#ibcon#about to read 3, iclass 26, count 0 2006.173.18:29:51.67#ibcon#read 3, iclass 26, count 0 2006.173.18:29:51.67#ibcon#about to read 4, iclass 26, count 0 2006.173.18:29:51.67#ibcon#read 4, iclass 26, count 0 2006.173.18:29:51.67#ibcon#about to read 5, iclass 26, count 0 2006.173.18:29:51.67#ibcon#read 5, iclass 26, count 0 2006.173.18:29:51.67#ibcon#about to read 6, iclass 26, count 0 2006.173.18:29:51.67#ibcon#read 6, iclass 26, count 0 2006.173.18:29:51.67#ibcon#end of sib2, iclass 26, count 0 2006.173.18:29:51.67#ibcon#*after write, iclass 26, count 0 2006.173.18:29:51.67#ibcon#*before return 0, iclass 26, count 0 2006.173.18:29:51.67#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.18:29:51.67#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.18:29:51.67#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.18:29:51.67#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.18:29:51.67$vck44/va=1,7 2006.173.18:29:51.67#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.18:29:51.67#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.18:29:51.67#ibcon#ireg 11 cls_cnt 2 2006.173.18:29:51.67#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.18:29:51.67#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.18:29:51.67#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.18:29:51.67#ibcon#enter wrdev, iclass 28, count 2 2006.173.18:29:51.67#ibcon#first serial, iclass 28, count 2 2006.173.18:29:51.67#ibcon#enter sib2, iclass 28, count 2 2006.173.18:29:51.67#ibcon#flushed, iclass 28, count 2 2006.173.18:29:51.67#ibcon#about to write, iclass 28, count 2 2006.173.18:29:51.67#ibcon#wrote, iclass 28, count 2 2006.173.18:29:51.67#ibcon#about to read 3, iclass 28, count 2 2006.173.18:29:51.69#ibcon#read 3, iclass 28, count 2 2006.173.18:29:51.69#ibcon#about to read 4, iclass 28, count 2 2006.173.18:29:51.69#ibcon#read 4, iclass 28, count 2 2006.173.18:29:51.69#ibcon#about to read 5, iclass 28, count 2 2006.173.18:29:51.69#ibcon#read 5, iclass 28, count 2 2006.173.18:29:51.69#ibcon#about to read 6, iclass 28, count 2 2006.173.18:29:51.69#ibcon#read 6, iclass 28, count 2 2006.173.18:29:51.69#ibcon#end of sib2, iclass 28, count 2 2006.173.18:29:51.69#ibcon#*mode == 0, iclass 28, count 2 2006.173.18:29:51.69#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.18:29:51.69#ibcon#[25=AT01-07\r\n] 2006.173.18:29:51.69#ibcon#*before write, iclass 28, count 2 2006.173.18:29:51.69#ibcon#enter sib2, iclass 28, count 2 2006.173.18:29:51.69#ibcon#flushed, iclass 28, count 2 2006.173.18:29:51.69#ibcon#about to write, iclass 28, count 2 2006.173.18:29:51.69#ibcon#wrote, iclass 28, count 2 2006.173.18:29:51.69#ibcon#about to read 3, iclass 28, count 2 2006.173.18:29:51.72#ibcon#read 3, iclass 28, count 2 2006.173.18:29:51.72#ibcon#about to read 4, iclass 28, count 2 2006.173.18:29:51.72#ibcon#read 4, iclass 28, count 2 2006.173.18:29:51.72#ibcon#about to read 5, iclass 28, count 2 2006.173.18:29:51.72#ibcon#read 5, iclass 28, count 2 2006.173.18:29:51.72#ibcon#about to read 6, iclass 28, count 2 2006.173.18:29:51.72#ibcon#read 6, iclass 28, count 2 2006.173.18:29:51.72#ibcon#end of sib2, iclass 28, count 2 2006.173.18:29:51.72#ibcon#*after write, iclass 28, count 2 2006.173.18:29:51.72#ibcon#*before return 0, iclass 28, count 2 2006.173.18:29:51.72#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.18:29:51.72#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.18:29:51.72#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.18:29:51.72#ibcon#ireg 7 cls_cnt 0 2006.173.18:29:51.72#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.18:29:51.84#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.18:29:51.84#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.18:29:51.84#ibcon#enter wrdev, iclass 28, count 0 2006.173.18:29:51.84#ibcon#first serial, iclass 28, count 0 2006.173.18:29:51.84#ibcon#enter sib2, iclass 28, count 0 2006.173.18:29:51.84#ibcon#flushed, iclass 28, count 0 2006.173.18:29:51.84#ibcon#about to write, iclass 28, count 0 2006.173.18:29:51.84#ibcon#wrote, iclass 28, count 0 2006.173.18:29:51.84#ibcon#about to read 3, iclass 28, count 0 2006.173.18:29:51.86#ibcon#read 3, iclass 28, count 0 2006.173.18:29:51.86#ibcon#about to read 4, iclass 28, count 0 2006.173.18:29:51.86#ibcon#read 4, iclass 28, count 0 2006.173.18:29:51.86#ibcon#about to read 5, iclass 28, count 0 2006.173.18:29:51.86#ibcon#read 5, iclass 28, count 0 2006.173.18:29:51.86#ibcon#about to read 6, iclass 28, count 0 2006.173.18:29:51.86#ibcon#read 6, iclass 28, count 0 2006.173.18:29:51.86#ibcon#end of sib2, iclass 28, count 0 2006.173.18:29:51.86#ibcon#*mode == 0, iclass 28, count 0 2006.173.18:29:51.86#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.18:29:51.86#ibcon#[25=USB\r\n] 2006.173.18:29:51.86#ibcon#*before write, iclass 28, count 0 2006.173.18:29:51.86#ibcon#enter sib2, iclass 28, count 0 2006.173.18:29:51.86#ibcon#flushed, iclass 28, count 0 2006.173.18:29:51.86#ibcon#about to write, iclass 28, count 0 2006.173.18:29:51.86#ibcon#wrote, iclass 28, count 0 2006.173.18:29:51.86#ibcon#about to read 3, iclass 28, count 0 2006.173.18:29:51.89#ibcon#read 3, iclass 28, count 0 2006.173.18:29:51.89#ibcon#about to read 4, iclass 28, count 0 2006.173.18:29:51.89#ibcon#read 4, iclass 28, count 0 2006.173.18:29:51.89#ibcon#about to read 5, iclass 28, count 0 2006.173.18:29:51.89#ibcon#read 5, iclass 28, count 0 2006.173.18:29:51.89#ibcon#about to read 6, iclass 28, count 0 2006.173.18:29:51.89#ibcon#read 6, iclass 28, count 0 2006.173.18:29:51.89#ibcon#end of sib2, iclass 28, count 0 2006.173.18:29:51.89#ibcon#*after write, iclass 28, count 0 2006.173.18:29:51.89#ibcon#*before return 0, iclass 28, count 0 2006.173.18:29:51.89#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.18:29:51.89#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.18:29:51.89#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.18:29:51.89#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.18:29:51.89$vck44/valo=2,534.99 2006.173.18:29:51.89#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.18:29:51.89#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.18:29:51.89#ibcon#ireg 17 cls_cnt 0 2006.173.18:29:51.89#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.18:29:51.89#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.18:29:51.89#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.18:29:51.89#ibcon#enter wrdev, iclass 30, count 0 2006.173.18:29:51.89#ibcon#first serial, iclass 30, count 0 2006.173.18:29:51.89#ibcon#enter sib2, iclass 30, count 0 2006.173.18:29:51.89#ibcon#flushed, iclass 30, count 0 2006.173.18:29:51.89#ibcon#about to write, iclass 30, count 0 2006.173.18:29:51.89#ibcon#wrote, iclass 30, count 0 2006.173.18:29:51.89#ibcon#about to read 3, iclass 30, count 0 2006.173.18:29:51.91#ibcon#read 3, iclass 30, count 0 2006.173.18:29:51.91#ibcon#about to read 4, iclass 30, count 0 2006.173.18:29:51.91#ibcon#read 4, iclass 30, count 0 2006.173.18:29:51.91#ibcon#about to read 5, iclass 30, count 0 2006.173.18:29:51.91#ibcon#read 5, iclass 30, count 0 2006.173.18:29:51.91#ibcon#about to read 6, iclass 30, count 0 2006.173.18:29:51.91#ibcon#read 6, iclass 30, count 0 2006.173.18:29:51.91#ibcon#end of sib2, iclass 30, count 0 2006.173.18:29:51.91#ibcon#*mode == 0, iclass 30, count 0 2006.173.18:29:51.91#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.18:29:51.91#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.18:29:51.91#ibcon#*before write, iclass 30, count 0 2006.173.18:29:51.91#ibcon#enter sib2, iclass 30, count 0 2006.173.18:29:51.91#ibcon#flushed, iclass 30, count 0 2006.173.18:29:51.91#ibcon#about to write, iclass 30, count 0 2006.173.18:29:51.91#ibcon#wrote, iclass 30, count 0 2006.173.18:29:51.91#ibcon#about to read 3, iclass 30, count 0 2006.173.18:29:51.95#ibcon#read 3, iclass 30, count 0 2006.173.18:29:51.95#ibcon#about to read 4, iclass 30, count 0 2006.173.18:29:51.95#ibcon#read 4, iclass 30, count 0 2006.173.18:29:51.95#ibcon#about to read 5, iclass 30, count 0 2006.173.18:29:51.95#ibcon#read 5, iclass 30, count 0 2006.173.18:29:51.95#ibcon#about to read 6, iclass 30, count 0 2006.173.18:29:51.95#ibcon#read 6, iclass 30, count 0 2006.173.18:29:51.95#ibcon#end of sib2, iclass 30, count 0 2006.173.18:29:51.95#ibcon#*after write, iclass 30, count 0 2006.173.18:29:51.95#ibcon#*before return 0, iclass 30, count 0 2006.173.18:29:51.95#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.18:29:51.95#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.18:29:51.95#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.18:29:51.95#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.18:29:51.95$vck44/va=2,6 2006.173.18:29:51.95#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.173.18:29:51.95#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.173.18:29:51.95#ibcon#ireg 11 cls_cnt 2 2006.173.18:29:51.95#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.18:29:52.01#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.18:29:52.01#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.18:29:52.01#ibcon#enter wrdev, iclass 32, count 2 2006.173.18:29:52.01#ibcon#first serial, iclass 32, count 2 2006.173.18:29:52.01#ibcon#enter sib2, iclass 32, count 2 2006.173.18:29:52.01#ibcon#flushed, iclass 32, count 2 2006.173.18:29:52.01#ibcon#about to write, iclass 32, count 2 2006.173.18:29:52.01#ibcon#wrote, iclass 32, count 2 2006.173.18:29:52.01#ibcon#about to read 3, iclass 32, count 2 2006.173.18:29:52.03#ibcon#read 3, iclass 32, count 2 2006.173.18:29:52.03#ibcon#about to read 4, iclass 32, count 2 2006.173.18:29:52.03#ibcon#read 4, iclass 32, count 2 2006.173.18:29:52.03#ibcon#about to read 5, iclass 32, count 2 2006.173.18:29:52.03#ibcon#read 5, iclass 32, count 2 2006.173.18:29:52.03#ibcon#about to read 6, iclass 32, count 2 2006.173.18:29:52.03#ibcon#read 6, iclass 32, count 2 2006.173.18:29:52.03#ibcon#end of sib2, iclass 32, count 2 2006.173.18:29:52.03#ibcon#*mode == 0, iclass 32, count 2 2006.173.18:29:52.03#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.173.18:29:52.03#ibcon#[25=AT02-06\r\n] 2006.173.18:29:52.03#ibcon#*before write, iclass 32, count 2 2006.173.18:29:52.03#ibcon#enter sib2, iclass 32, count 2 2006.173.18:29:52.03#ibcon#flushed, iclass 32, count 2 2006.173.18:29:52.03#ibcon#about to write, iclass 32, count 2 2006.173.18:29:52.03#ibcon#wrote, iclass 32, count 2 2006.173.18:29:52.03#ibcon#about to read 3, iclass 32, count 2 2006.173.18:29:52.06#ibcon#read 3, iclass 32, count 2 2006.173.18:29:52.06#ibcon#about to read 4, iclass 32, count 2 2006.173.18:29:52.06#ibcon#read 4, iclass 32, count 2 2006.173.18:29:52.06#ibcon#about to read 5, iclass 32, count 2 2006.173.18:29:52.06#ibcon#read 5, iclass 32, count 2 2006.173.18:29:52.06#ibcon#about to read 6, iclass 32, count 2 2006.173.18:29:52.06#ibcon#read 6, iclass 32, count 2 2006.173.18:29:52.06#ibcon#end of sib2, iclass 32, count 2 2006.173.18:29:52.06#ibcon#*after write, iclass 32, count 2 2006.173.18:29:52.06#ibcon#*before return 0, iclass 32, count 2 2006.173.18:29:52.06#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.18:29:52.06#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.173.18:29:52.06#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.173.18:29:52.06#ibcon#ireg 7 cls_cnt 0 2006.173.18:29:52.06#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.18:29:52.18#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.18:29:52.18#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.18:29:52.18#ibcon#enter wrdev, iclass 32, count 0 2006.173.18:29:52.18#ibcon#first serial, iclass 32, count 0 2006.173.18:29:52.18#ibcon#enter sib2, iclass 32, count 0 2006.173.18:29:52.18#ibcon#flushed, iclass 32, count 0 2006.173.18:29:52.18#ibcon#about to write, iclass 32, count 0 2006.173.18:29:52.18#ibcon#wrote, iclass 32, count 0 2006.173.18:29:52.18#ibcon#about to read 3, iclass 32, count 0 2006.173.18:29:52.20#ibcon#read 3, iclass 32, count 0 2006.173.18:29:52.20#ibcon#about to read 4, iclass 32, count 0 2006.173.18:29:52.20#ibcon#read 4, iclass 32, count 0 2006.173.18:29:52.20#ibcon#about to read 5, iclass 32, count 0 2006.173.18:29:52.20#ibcon#read 5, iclass 32, count 0 2006.173.18:29:52.20#ibcon#about to read 6, iclass 32, count 0 2006.173.18:29:52.20#ibcon#read 6, iclass 32, count 0 2006.173.18:29:52.20#ibcon#end of sib2, iclass 32, count 0 2006.173.18:29:52.20#ibcon#*mode == 0, iclass 32, count 0 2006.173.18:29:52.20#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.18:29:52.20#ibcon#[25=USB\r\n] 2006.173.18:29:52.20#ibcon#*before write, iclass 32, count 0 2006.173.18:29:52.20#ibcon#enter sib2, iclass 32, count 0 2006.173.18:29:52.20#ibcon#flushed, iclass 32, count 0 2006.173.18:29:52.20#ibcon#about to write, iclass 32, count 0 2006.173.18:29:52.20#ibcon#wrote, iclass 32, count 0 2006.173.18:29:52.20#ibcon#about to read 3, iclass 32, count 0 2006.173.18:29:52.23#ibcon#read 3, iclass 32, count 0 2006.173.18:29:52.23#ibcon#about to read 4, iclass 32, count 0 2006.173.18:29:52.23#ibcon#read 4, iclass 32, count 0 2006.173.18:29:52.23#ibcon#about to read 5, iclass 32, count 0 2006.173.18:29:52.23#ibcon#read 5, iclass 32, count 0 2006.173.18:29:52.23#ibcon#about to read 6, iclass 32, count 0 2006.173.18:29:52.23#ibcon#read 6, iclass 32, count 0 2006.173.18:29:52.23#ibcon#end of sib2, iclass 32, count 0 2006.173.18:29:52.23#ibcon#*after write, iclass 32, count 0 2006.173.18:29:52.23#ibcon#*before return 0, iclass 32, count 0 2006.173.18:29:52.23#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.18:29:52.23#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.173.18:29:52.23#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.18:29:52.23#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.18:29:52.23$vck44/valo=3,564.99 2006.173.18:29:52.23#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.18:29:52.23#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.18:29:52.23#ibcon#ireg 17 cls_cnt 0 2006.173.18:29:52.23#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.18:29:52.23#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.18:29:52.23#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.18:29:52.23#ibcon#enter wrdev, iclass 34, count 0 2006.173.18:29:52.23#ibcon#first serial, iclass 34, count 0 2006.173.18:29:52.23#ibcon#enter sib2, iclass 34, count 0 2006.173.18:29:52.23#ibcon#flushed, iclass 34, count 0 2006.173.18:29:52.23#ibcon#about to write, iclass 34, count 0 2006.173.18:29:52.23#ibcon#wrote, iclass 34, count 0 2006.173.18:29:52.23#ibcon#about to read 3, iclass 34, count 0 2006.173.18:29:52.25#ibcon#read 3, iclass 34, count 0 2006.173.18:29:52.25#ibcon#about to read 4, iclass 34, count 0 2006.173.18:29:52.25#ibcon#read 4, iclass 34, count 0 2006.173.18:29:52.25#ibcon#about to read 5, iclass 34, count 0 2006.173.18:29:52.25#ibcon#read 5, iclass 34, count 0 2006.173.18:29:52.25#ibcon#about to read 6, iclass 34, count 0 2006.173.18:29:52.25#ibcon#read 6, iclass 34, count 0 2006.173.18:29:52.25#ibcon#end of sib2, iclass 34, count 0 2006.173.18:29:52.25#ibcon#*mode == 0, iclass 34, count 0 2006.173.18:29:52.25#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.18:29:52.25#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.18:29:52.25#ibcon#*before write, iclass 34, count 0 2006.173.18:29:52.25#ibcon#enter sib2, iclass 34, count 0 2006.173.18:29:52.25#ibcon#flushed, iclass 34, count 0 2006.173.18:29:52.25#ibcon#about to write, iclass 34, count 0 2006.173.18:29:52.25#ibcon#wrote, iclass 34, count 0 2006.173.18:29:52.25#ibcon#about to read 3, iclass 34, count 0 2006.173.18:29:52.29#ibcon#read 3, iclass 34, count 0 2006.173.18:29:52.29#ibcon#about to read 4, iclass 34, count 0 2006.173.18:29:52.29#ibcon#read 4, iclass 34, count 0 2006.173.18:29:52.29#ibcon#about to read 5, iclass 34, count 0 2006.173.18:29:52.29#ibcon#read 5, iclass 34, count 0 2006.173.18:29:52.29#ibcon#about to read 6, iclass 34, count 0 2006.173.18:29:52.29#ibcon#read 6, iclass 34, count 0 2006.173.18:29:52.29#ibcon#end of sib2, iclass 34, count 0 2006.173.18:29:52.29#ibcon#*after write, iclass 34, count 0 2006.173.18:29:52.29#ibcon#*before return 0, iclass 34, count 0 2006.173.18:29:52.29#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.18:29:52.29#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.18:29:52.29#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.18:29:52.29#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.18:29:52.29$vck44/va=3,5 2006.173.18:29:52.29#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.18:29:52.29#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.18:29:52.29#ibcon#ireg 11 cls_cnt 2 2006.173.18:29:52.29#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.18:29:52.35#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.18:29:52.35#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.18:29:52.35#ibcon#enter wrdev, iclass 36, count 2 2006.173.18:29:52.35#ibcon#first serial, iclass 36, count 2 2006.173.18:29:52.35#ibcon#enter sib2, iclass 36, count 2 2006.173.18:29:52.35#ibcon#flushed, iclass 36, count 2 2006.173.18:29:52.35#ibcon#about to write, iclass 36, count 2 2006.173.18:29:52.35#ibcon#wrote, iclass 36, count 2 2006.173.18:29:52.35#ibcon#about to read 3, iclass 36, count 2 2006.173.18:29:52.37#ibcon#read 3, iclass 36, count 2 2006.173.18:29:52.37#ibcon#about to read 4, iclass 36, count 2 2006.173.18:29:52.37#ibcon#read 4, iclass 36, count 2 2006.173.18:29:52.37#ibcon#about to read 5, iclass 36, count 2 2006.173.18:29:52.37#ibcon#read 5, iclass 36, count 2 2006.173.18:29:52.37#ibcon#about to read 6, iclass 36, count 2 2006.173.18:29:52.37#ibcon#read 6, iclass 36, count 2 2006.173.18:29:52.37#ibcon#end of sib2, iclass 36, count 2 2006.173.18:29:52.37#ibcon#*mode == 0, iclass 36, count 2 2006.173.18:29:52.37#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.18:29:52.37#ibcon#[25=AT03-05\r\n] 2006.173.18:29:52.37#ibcon#*before write, iclass 36, count 2 2006.173.18:29:52.37#ibcon#enter sib2, iclass 36, count 2 2006.173.18:29:52.37#ibcon#flushed, iclass 36, count 2 2006.173.18:29:52.37#ibcon#about to write, iclass 36, count 2 2006.173.18:29:52.37#ibcon#wrote, iclass 36, count 2 2006.173.18:29:52.37#ibcon#about to read 3, iclass 36, count 2 2006.173.18:29:52.40#ibcon#read 3, iclass 36, count 2 2006.173.18:29:52.40#ibcon#about to read 4, iclass 36, count 2 2006.173.18:29:52.40#ibcon#read 4, iclass 36, count 2 2006.173.18:29:52.40#ibcon#about to read 5, iclass 36, count 2 2006.173.18:29:52.40#ibcon#read 5, iclass 36, count 2 2006.173.18:29:52.40#ibcon#about to read 6, iclass 36, count 2 2006.173.18:29:52.40#ibcon#read 6, iclass 36, count 2 2006.173.18:29:52.40#ibcon#end of sib2, iclass 36, count 2 2006.173.18:29:52.40#ibcon#*after write, iclass 36, count 2 2006.173.18:29:52.40#ibcon#*before return 0, iclass 36, count 2 2006.173.18:29:52.40#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.18:29:52.40#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.18:29:52.40#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.18:29:52.40#ibcon#ireg 7 cls_cnt 0 2006.173.18:29:52.40#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.18:29:52.52#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.18:29:52.52#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.18:29:52.52#ibcon#enter wrdev, iclass 36, count 0 2006.173.18:29:52.52#ibcon#first serial, iclass 36, count 0 2006.173.18:29:52.52#ibcon#enter sib2, iclass 36, count 0 2006.173.18:29:52.52#ibcon#flushed, iclass 36, count 0 2006.173.18:29:52.52#ibcon#about to write, iclass 36, count 0 2006.173.18:29:52.52#ibcon#wrote, iclass 36, count 0 2006.173.18:29:52.52#ibcon#about to read 3, iclass 36, count 0 2006.173.18:29:52.54#ibcon#read 3, iclass 36, count 0 2006.173.18:29:52.54#ibcon#about to read 4, iclass 36, count 0 2006.173.18:29:52.54#ibcon#read 4, iclass 36, count 0 2006.173.18:29:52.54#ibcon#about to read 5, iclass 36, count 0 2006.173.18:29:52.54#ibcon#read 5, iclass 36, count 0 2006.173.18:29:52.54#ibcon#about to read 6, iclass 36, count 0 2006.173.18:29:52.54#ibcon#read 6, iclass 36, count 0 2006.173.18:29:52.54#ibcon#end of sib2, iclass 36, count 0 2006.173.18:29:52.54#ibcon#*mode == 0, iclass 36, count 0 2006.173.18:29:52.54#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.18:29:52.54#ibcon#[25=USB\r\n] 2006.173.18:29:52.54#ibcon#*before write, iclass 36, count 0 2006.173.18:29:52.54#ibcon#enter sib2, iclass 36, count 0 2006.173.18:29:52.54#ibcon#flushed, iclass 36, count 0 2006.173.18:29:52.54#ibcon#about to write, iclass 36, count 0 2006.173.18:29:52.54#ibcon#wrote, iclass 36, count 0 2006.173.18:29:52.54#ibcon#about to read 3, iclass 36, count 0 2006.173.18:29:52.57#ibcon#read 3, iclass 36, count 0 2006.173.18:29:52.57#ibcon#about to read 4, iclass 36, count 0 2006.173.18:29:52.57#ibcon#read 4, iclass 36, count 0 2006.173.18:29:52.57#ibcon#about to read 5, iclass 36, count 0 2006.173.18:29:52.57#ibcon#read 5, iclass 36, count 0 2006.173.18:29:52.57#ibcon#about to read 6, iclass 36, count 0 2006.173.18:29:52.57#ibcon#read 6, iclass 36, count 0 2006.173.18:29:52.57#ibcon#end of sib2, iclass 36, count 0 2006.173.18:29:52.57#ibcon#*after write, iclass 36, count 0 2006.173.18:29:52.57#ibcon#*before return 0, iclass 36, count 0 2006.173.18:29:52.57#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.18:29:52.57#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.18:29:52.57#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.18:29:52.57#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.18:29:52.57$vck44/valo=4,624.99 2006.173.18:29:52.57#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.18:29:52.57#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.18:29:52.57#ibcon#ireg 17 cls_cnt 0 2006.173.18:29:52.57#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.18:29:52.57#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.18:29:52.57#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.18:29:52.57#ibcon#enter wrdev, iclass 38, count 0 2006.173.18:29:52.57#ibcon#first serial, iclass 38, count 0 2006.173.18:29:52.57#ibcon#enter sib2, iclass 38, count 0 2006.173.18:29:52.57#ibcon#flushed, iclass 38, count 0 2006.173.18:29:52.57#ibcon#about to write, iclass 38, count 0 2006.173.18:29:52.57#ibcon#wrote, iclass 38, count 0 2006.173.18:29:52.57#ibcon#about to read 3, iclass 38, count 0 2006.173.18:29:52.59#ibcon#read 3, iclass 38, count 0 2006.173.18:29:52.59#ibcon#about to read 4, iclass 38, count 0 2006.173.18:29:52.59#ibcon#read 4, iclass 38, count 0 2006.173.18:29:52.59#ibcon#about to read 5, iclass 38, count 0 2006.173.18:29:52.59#ibcon#read 5, iclass 38, count 0 2006.173.18:29:52.59#ibcon#about to read 6, iclass 38, count 0 2006.173.18:29:52.59#ibcon#read 6, iclass 38, count 0 2006.173.18:29:52.59#ibcon#end of sib2, iclass 38, count 0 2006.173.18:29:52.59#ibcon#*mode == 0, iclass 38, count 0 2006.173.18:29:52.59#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.18:29:52.59#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.18:29:52.59#ibcon#*before write, iclass 38, count 0 2006.173.18:29:52.59#ibcon#enter sib2, iclass 38, count 0 2006.173.18:29:52.59#ibcon#flushed, iclass 38, count 0 2006.173.18:29:52.59#ibcon#about to write, iclass 38, count 0 2006.173.18:29:52.59#ibcon#wrote, iclass 38, count 0 2006.173.18:29:52.59#ibcon#about to read 3, iclass 38, count 0 2006.173.18:29:52.63#ibcon#read 3, iclass 38, count 0 2006.173.18:29:52.63#ibcon#about to read 4, iclass 38, count 0 2006.173.18:29:52.63#ibcon#read 4, iclass 38, count 0 2006.173.18:29:52.63#ibcon#about to read 5, iclass 38, count 0 2006.173.18:29:52.63#ibcon#read 5, iclass 38, count 0 2006.173.18:29:52.63#ibcon#about to read 6, iclass 38, count 0 2006.173.18:29:52.63#ibcon#read 6, iclass 38, count 0 2006.173.18:29:52.63#ibcon#end of sib2, iclass 38, count 0 2006.173.18:29:52.63#ibcon#*after write, iclass 38, count 0 2006.173.18:29:52.63#ibcon#*before return 0, iclass 38, count 0 2006.173.18:29:52.63#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.18:29:52.63#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.18:29:52.63#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.18:29:52.63#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.18:29:52.63$vck44/va=4,6 2006.173.18:29:52.63#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.18:29:52.63#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.18:29:52.63#ibcon#ireg 11 cls_cnt 2 2006.173.18:29:52.63#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.18:29:52.69#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.18:29:52.69#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.18:29:52.69#ibcon#enter wrdev, iclass 40, count 2 2006.173.18:29:52.69#ibcon#first serial, iclass 40, count 2 2006.173.18:29:52.69#ibcon#enter sib2, iclass 40, count 2 2006.173.18:29:52.69#ibcon#flushed, iclass 40, count 2 2006.173.18:29:52.69#ibcon#about to write, iclass 40, count 2 2006.173.18:29:52.69#ibcon#wrote, iclass 40, count 2 2006.173.18:29:52.69#ibcon#about to read 3, iclass 40, count 2 2006.173.18:29:52.71#ibcon#read 3, iclass 40, count 2 2006.173.18:29:52.71#ibcon#about to read 4, iclass 40, count 2 2006.173.18:29:52.71#ibcon#read 4, iclass 40, count 2 2006.173.18:29:52.71#ibcon#about to read 5, iclass 40, count 2 2006.173.18:29:52.71#ibcon#read 5, iclass 40, count 2 2006.173.18:29:52.71#ibcon#about to read 6, iclass 40, count 2 2006.173.18:29:52.71#ibcon#read 6, iclass 40, count 2 2006.173.18:29:52.71#ibcon#end of sib2, iclass 40, count 2 2006.173.18:29:52.71#ibcon#*mode == 0, iclass 40, count 2 2006.173.18:29:52.71#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.18:29:52.71#ibcon#[25=AT04-06\r\n] 2006.173.18:29:52.71#ibcon#*before write, iclass 40, count 2 2006.173.18:29:52.71#ibcon#enter sib2, iclass 40, count 2 2006.173.18:29:52.71#ibcon#flushed, iclass 40, count 2 2006.173.18:29:52.71#ibcon#about to write, iclass 40, count 2 2006.173.18:29:52.71#ibcon#wrote, iclass 40, count 2 2006.173.18:29:52.71#ibcon#about to read 3, iclass 40, count 2 2006.173.18:29:52.74#ibcon#read 3, iclass 40, count 2 2006.173.18:29:52.74#ibcon#about to read 4, iclass 40, count 2 2006.173.18:29:52.74#ibcon#read 4, iclass 40, count 2 2006.173.18:29:52.74#ibcon#about to read 5, iclass 40, count 2 2006.173.18:29:52.74#ibcon#read 5, iclass 40, count 2 2006.173.18:29:52.74#ibcon#about to read 6, iclass 40, count 2 2006.173.18:29:52.74#ibcon#read 6, iclass 40, count 2 2006.173.18:29:52.74#ibcon#end of sib2, iclass 40, count 2 2006.173.18:29:52.74#ibcon#*after write, iclass 40, count 2 2006.173.18:29:52.74#ibcon#*before return 0, iclass 40, count 2 2006.173.18:29:52.74#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.18:29:52.74#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.18:29:52.74#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.18:29:52.74#ibcon#ireg 7 cls_cnt 0 2006.173.18:29:52.74#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.18:29:52.86#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.18:29:52.86#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.18:29:52.86#ibcon#enter wrdev, iclass 40, count 0 2006.173.18:29:52.86#ibcon#first serial, iclass 40, count 0 2006.173.18:29:52.86#ibcon#enter sib2, iclass 40, count 0 2006.173.18:29:52.86#ibcon#flushed, iclass 40, count 0 2006.173.18:29:52.86#ibcon#about to write, iclass 40, count 0 2006.173.18:29:52.86#ibcon#wrote, iclass 40, count 0 2006.173.18:29:52.86#ibcon#about to read 3, iclass 40, count 0 2006.173.18:29:52.88#ibcon#read 3, iclass 40, count 0 2006.173.18:29:52.88#ibcon#about to read 4, iclass 40, count 0 2006.173.18:29:52.88#ibcon#read 4, iclass 40, count 0 2006.173.18:29:52.88#ibcon#about to read 5, iclass 40, count 0 2006.173.18:29:52.88#ibcon#read 5, iclass 40, count 0 2006.173.18:29:52.88#ibcon#about to read 6, iclass 40, count 0 2006.173.18:29:52.88#ibcon#read 6, iclass 40, count 0 2006.173.18:29:52.88#ibcon#end of sib2, iclass 40, count 0 2006.173.18:29:52.88#ibcon#*mode == 0, iclass 40, count 0 2006.173.18:29:52.88#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.18:29:52.88#ibcon#[25=USB\r\n] 2006.173.18:29:52.88#ibcon#*before write, iclass 40, count 0 2006.173.18:29:52.88#ibcon#enter sib2, iclass 40, count 0 2006.173.18:29:52.88#ibcon#flushed, iclass 40, count 0 2006.173.18:29:52.88#ibcon#about to write, iclass 40, count 0 2006.173.18:29:52.88#ibcon#wrote, iclass 40, count 0 2006.173.18:29:52.88#ibcon#about to read 3, iclass 40, count 0 2006.173.18:29:52.91#ibcon#read 3, iclass 40, count 0 2006.173.18:29:52.91#ibcon#about to read 4, iclass 40, count 0 2006.173.18:29:52.91#ibcon#read 4, iclass 40, count 0 2006.173.18:29:52.91#ibcon#about to read 5, iclass 40, count 0 2006.173.18:29:52.91#ibcon#read 5, iclass 40, count 0 2006.173.18:29:52.91#ibcon#about to read 6, iclass 40, count 0 2006.173.18:29:52.91#ibcon#read 6, iclass 40, count 0 2006.173.18:29:52.91#ibcon#end of sib2, iclass 40, count 0 2006.173.18:29:52.91#ibcon#*after write, iclass 40, count 0 2006.173.18:29:52.91#ibcon#*before return 0, iclass 40, count 0 2006.173.18:29:52.91#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.18:29:52.91#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.18:29:52.91#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.18:29:52.91#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.18:29:52.91$vck44/valo=5,734.99 2006.173.18:29:52.91#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.18:29:52.91#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.18:29:52.91#ibcon#ireg 17 cls_cnt 0 2006.173.18:29:52.91#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.18:29:52.91#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.18:29:52.91#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.18:29:52.91#ibcon#enter wrdev, iclass 4, count 0 2006.173.18:29:52.91#ibcon#first serial, iclass 4, count 0 2006.173.18:29:52.91#ibcon#enter sib2, iclass 4, count 0 2006.173.18:29:52.91#ibcon#flushed, iclass 4, count 0 2006.173.18:29:52.91#ibcon#about to write, iclass 4, count 0 2006.173.18:29:52.91#ibcon#wrote, iclass 4, count 0 2006.173.18:29:52.91#ibcon#about to read 3, iclass 4, count 0 2006.173.18:29:52.93#ibcon#read 3, iclass 4, count 0 2006.173.18:29:52.93#ibcon#about to read 4, iclass 4, count 0 2006.173.18:29:52.93#ibcon#read 4, iclass 4, count 0 2006.173.18:29:52.93#ibcon#about to read 5, iclass 4, count 0 2006.173.18:29:52.93#ibcon#read 5, iclass 4, count 0 2006.173.18:29:52.93#ibcon#about to read 6, iclass 4, count 0 2006.173.18:29:52.93#ibcon#read 6, iclass 4, count 0 2006.173.18:29:52.93#ibcon#end of sib2, iclass 4, count 0 2006.173.18:29:52.93#ibcon#*mode == 0, iclass 4, count 0 2006.173.18:29:52.93#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.18:29:52.93#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.18:29:52.93#ibcon#*before write, iclass 4, count 0 2006.173.18:29:52.93#ibcon#enter sib2, iclass 4, count 0 2006.173.18:29:52.93#ibcon#flushed, iclass 4, count 0 2006.173.18:29:52.93#ibcon#about to write, iclass 4, count 0 2006.173.18:29:52.93#ibcon#wrote, iclass 4, count 0 2006.173.18:29:52.93#ibcon#about to read 3, iclass 4, count 0 2006.173.18:29:52.97#ibcon#read 3, iclass 4, count 0 2006.173.18:29:52.97#ibcon#about to read 4, iclass 4, count 0 2006.173.18:29:52.97#ibcon#read 4, iclass 4, count 0 2006.173.18:29:52.97#ibcon#about to read 5, iclass 4, count 0 2006.173.18:29:52.97#ibcon#read 5, iclass 4, count 0 2006.173.18:29:52.97#ibcon#about to read 6, iclass 4, count 0 2006.173.18:29:52.97#ibcon#read 6, iclass 4, count 0 2006.173.18:29:52.97#ibcon#end of sib2, iclass 4, count 0 2006.173.18:29:52.97#ibcon#*after write, iclass 4, count 0 2006.173.18:29:52.97#ibcon#*before return 0, iclass 4, count 0 2006.173.18:29:52.97#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.18:29:52.97#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.18:29:52.97#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.18:29:52.97#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.18:29:52.97$vck44/va=5,4 2006.173.18:29:52.97#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.18:29:52.97#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.18:29:52.97#ibcon#ireg 11 cls_cnt 2 2006.173.18:29:52.97#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.18:29:53.03#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.18:29:53.03#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.18:29:53.03#ibcon#enter wrdev, iclass 6, count 2 2006.173.18:29:53.03#ibcon#first serial, iclass 6, count 2 2006.173.18:29:53.03#ibcon#enter sib2, iclass 6, count 2 2006.173.18:29:53.03#ibcon#flushed, iclass 6, count 2 2006.173.18:29:53.03#ibcon#about to write, iclass 6, count 2 2006.173.18:29:53.03#ibcon#wrote, iclass 6, count 2 2006.173.18:29:53.03#ibcon#about to read 3, iclass 6, count 2 2006.173.18:29:53.05#ibcon#read 3, iclass 6, count 2 2006.173.18:29:53.05#ibcon#about to read 4, iclass 6, count 2 2006.173.18:29:53.05#ibcon#read 4, iclass 6, count 2 2006.173.18:29:53.05#ibcon#about to read 5, iclass 6, count 2 2006.173.18:29:53.05#ibcon#read 5, iclass 6, count 2 2006.173.18:29:53.05#ibcon#about to read 6, iclass 6, count 2 2006.173.18:29:53.05#ibcon#read 6, iclass 6, count 2 2006.173.18:29:53.05#ibcon#end of sib2, iclass 6, count 2 2006.173.18:29:53.05#ibcon#*mode == 0, iclass 6, count 2 2006.173.18:29:53.05#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.18:29:53.05#ibcon#[25=AT05-04\r\n] 2006.173.18:29:53.05#ibcon#*before write, iclass 6, count 2 2006.173.18:29:53.05#ibcon#enter sib2, iclass 6, count 2 2006.173.18:29:53.05#ibcon#flushed, iclass 6, count 2 2006.173.18:29:53.05#ibcon#about to write, iclass 6, count 2 2006.173.18:29:53.05#ibcon#wrote, iclass 6, count 2 2006.173.18:29:53.05#ibcon#about to read 3, iclass 6, count 2 2006.173.18:29:53.08#ibcon#read 3, iclass 6, count 2 2006.173.18:29:53.08#ibcon#about to read 4, iclass 6, count 2 2006.173.18:29:53.08#ibcon#read 4, iclass 6, count 2 2006.173.18:29:53.08#ibcon#about to read 5, iclass 6, count 2 2006.173.18:29:53.08#ibcon#read 5, iclass 6, count 2 2006.173.18:29:53.08#ibcon#about to read 6, iclass 6, count 2 2006.173.18:29:53.08#ibcon#read 6, iclass 6, count 2 2006.173.18:29:53.08#ibcon#end of sib2, iclass 6, count 2 2006.173.18:29:53.08#ibcon#*after write, iclass 6, count 2 2006.173.18:29:53.08#ibcon#*before return 0, iclass 6, count 2 2006.173.18:29:53.08#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.18:29:53.08#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.18:29:53.08#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.18:29:53.08#ibcon#ireg 7 cls_cnt 0 2006.173.18:29:53.08#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.18:29:53.20#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.18:29:53.20#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.18:29:53.20#ibcon#enter wrdev, iclass 6, count 0 2006.173.18:29:53.20#ibcon#first serial, iclass 6, count 0 2006.173.18:29:53.20#ibcon#enter sib2, iclass 6, count 0 2006.173.18:29:53.20#ibcon#flushed, iclass 6, count 0 2006.173.18:29:53.20#ibcon#about to write, iclass 6, count 0 2006.173.18:29:53.20#ibcon#wrote, iclass 6, count 0 2006.173.18:29:53.20#ibcon#about to read 3, iclass 6, count 0 2006.173.18:29:53.22#ibcon#read 3, iclass 6, count 0 2006.173.18:29:53.22#ibcon#about to read 4, iclass 6, count 0 2006.173.18:29:53.22#ibcon#read 4, iclass 6, count 0 2006.173.18:29:53.22#ibcon#about to read 5, iclass 6, count 0 2006.173.18:29:53.22#ibcon#read 5, iclass 6, count 0 2006.173.18:29:53.22#ibcon#about to read 6, iclass 6, count 0 2006.173.18:29:53.22#ibcon#read 6, iclass 6, count 0 2006.173.18:29:53.22#ibcon#end of sib2, iclass 6, count 0 2006.173.18:29:53.22#ibcon#*mode == 0, iclass 6, count 0 2006.173.18:29:53.22#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.18:29:53.22#ibcon#[25=USB\r\n] 2006.173.18:29:53.22#ibcon#*before write, iclass 6, count 0 2006.173.18:29:53.22#ibcon#enter sib2, iclass 6, count 0 2006.173.18:29:53.22#ibcon#flushed, iclass 6, count 0 2006.173.18:29:53.22#ibcon#about to write, iclass 6, count 0 2006.173.18:29:53.22#ibcon#wrote, iclass 6, count 0 2006.173.18:29:53.22#ibcon#about to read 3, iclass 6, count 0 2006.173.18:29:53.25#ibcon#read 3, iclass 6, count 0 2006.173.18:29:53.25#ibcon#about to read 4, iclass 6, count 0 2006.173.18:29:53.25#ibcon#read 4, iclass 6, count 0 2006.173.18:29:53.25#ibcon#about to read 5, iclass 6, count 0 2006.173.18:29:53.25#ibcon#read 5, iclass 6, count 0 2006.173.18:29:53.25#ibcon#about to read 6, iclass 6, count 0 2006.173.18:29:53.25#ibcon#read 6, iclass 6, count 0 2006.173.18:29:53.25#ibcon#end of sib2, iclass 6, count 0 2006.173.18:29:53.25#ibcon#*after write, iclass 6, count 0 2006.173.18:29:53.25#ibcon#*before return 0, iclass 6, count 0 2006.173.18:29:53.25#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.18:29:53.25#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.18:29:53.25#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.18:29:53.25#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.18:29:53.25$vck44/valo=6,814.99 2006.173.18:29:53.25#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.18:29:53.25#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.18:29:53.25#ibcon#ireg 17 cls_cnt 0 2006.173.18:29:53.25#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.18:29:53.25#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.18:29:53.25#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.18:29:53.25#ibcon#enter wrdev, iclass 10, count 0 2006.173.18:29:53.25#ibcon#first serial, iclass 10, count 0 2006.173.18:29:53.25#ibcon#enter sib2, iclass 10, count 0 2006.173.18:29:53.25#ibcon#flushed, iclass 10, count 0 2006.173.18:29:53.25#ibcon#about to write, iclass 10, count 0 2006.173.18:29:53.25#ibcon#wrote, iclass 10, count 0 2006.173.18:29:53.25#ibcon#about to read 3, iclass 10, count 0 2006.173.18:29:53.27#ibcon#read 3, iclass 10, count 0 2006.173.18:29:53.27#ibcon#about to read 4, iclass 10, count 0 2006.173.18:29:53.27#ibcon#read 4, iclass 10, count 0 2006.173.18:29:53.27#ibcon#about to read 5, iclass 10, count 0 2006.173.18:29:53.27#ibcon#read 5, iclass 10, count 0 2006.173.18:29:53.27#ibcon#about to read 6, iclass 10, count 0 2006.173.18:29:53.27#ibcon#read 6, iclass 10, count 0 2006.173.18:29:53.27#ibcon#end of sib2, iclass 10, count 0 2006.173.18:29:53.27#ibcon#*mode == 0, iclass 10, count 0 2006.173.18:29:53.27#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.18:29:53.27#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.18:29:53.27#ibcon#*before write, iclass 10, count 0 2006.173.18:29:53.27#ibcon#enter sib2, iclass 10, count 0 2006.173.18:29:53.27#ibcon#flushed, iclass 10, count 0 2006.173.18:29:53.27#ibcon#about to write, iclass 10, count 0 2006.173.18:29:53.27#ibcon#wrote, iclass 10, count 0 2006.173.18:29:53.27#ibcon#about to read 3, iclass 10, count 0 2006.173.18:29:53.31#ibcon#read 3, iclass 10, count 0 2006.173.18:29:53.31#ibcon#about to read 4, iclass 10, count 0 2006.173.18:29:53.31#ibcon#read 4, iclass 10, count 0 2006.173.18:29:53.31#ibcon#about to read 5, iclass 10, count 0 2006.173.18:29:53.31#ibcon#read 5, iclass 10, count 0 2006.173.18:29:53.31#ibcon#about to read 6, iclass 10, count 0 2006.173.18:29:53.31#ibcon#read 6, iclass 10, count 0 2006.173.18:29:53.31#ibcon#end of sib2, iclass 10, count 0 2006.173.18:29:53.31#ibcon#*after write, iclass 10, count 0 2006.173.18:29:53.31#ibcon#*before return 0, iclass 10, count 0 2006.173.18:29:53.31#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.18:29:53.31#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.18:29:53.31#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.18:29:53.31#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.18:29:53.31$vck44/va=6,3 2006.173.18:29:53.31#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.18:29:53.31#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.18:29:53.31#ibcon#ireg 11 cls_cnt 2 2006.173.18:29:53.31#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.18:29:53.37#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.18:29:53.37#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.18:29:53.37#ibcon#enter wrdev, iclass 12, count 2 2006.173.18:29:53.37#ibcon#first serial, iclass 12, count 2 2006.173.18:29:53.37#ibcon#enter sib2, iclass 12, count 2 2006.173.18:29:53.37#ibcon#flushed, iclass 12, count 2 2006.173.18:29:53.37#ibcon#about to write, iclass 12, count 2 2006.173.18:29:53.37#ibcon#wrote, iclass 12, count 2 2006.173.18:29:53.37#ibcon#about to read 3, iclass 12, count 2 2006.173.18:29:53.39#ibcon#read 3, iclass 12, count 2 2006.173.18:29:53.39#ibcon#about to read 4, iclass 12, count 2 2006.173.18:29:53.39#ibcon#read 4, iclass 12, count 2 2006.173.18:29:53.39#ibcon#about to read 5, iclass 12, count 2 2006.173.18:29:53.39#ibcon#read 5, iclass 12, count 2 2006.173.18:29:53.39#ibcon#about to read 6, iclass 12, count 2 2006.173.18:29:53.39#ibcon#read 6, iclass 12, count 2 2006.173.18:29:53.39#ibcon#end of sib2, iclass 12, count 2 2006.173.18:29:53.39#ibcon#*mode == 0, iclass 12, count 2 2006.173.18:29:53.39#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.18:29:53.39#ibcon#[25=AT06-03\r\n] 2006.173.18:29:53.39#ibcon#*before write, iclass 12, count 2 2006.173.18:29:53.39#ibcon#enter sib2, iclass 12, count 2 2006.173.18:29:53.39#ibcon#flushed, iclass 12, count 2 2006.173.18:29:53.39#ibcon#about to write, iclass 12, count 2 2006.173.18:29:53.39#ibcon#wrote, iclass 12, count 2 2006.173.18:29:53.39#ibcon#about to read 3, iclass 12, count 2 2006.173.18:29:53.42#ibcon#read 3, iclass 12, count 2 2006.173.18:29:53.42#ibcon#about to read 4, iclass 12, count 2 2006.173.18:29:53.42#ibcon#read 4, iclass 12, count 2 2006.173.18:29:53.42#ibcon#about to read 5, iclass 12, count 2 2006.173.18:29:53.42#ibcon#read 5, iclass 12, count 2 2006.173.18:29:53.42#ibcon#about to read 6, iclass 12, count 2 2006.173.18:29:53.42#ibcon#read 6, iclass 12, count 2 2006.173.18:29:53.42#ibcon#end of sib2, iclass 12, count 2 2006.173.18:29:53.42#ibcon#*after write, iclass 12, count 2 2006.173.18:29:53.42#ibcon#*before return 0, iclass 12, count 2 2006.173.18:29:53.42#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.18:29:53.42#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.18:29:53.42#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.18:29:53.42#ibcon#ireg 7 cls_cnt 0 2006.173.18:29:53.42#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.18:29:53.54#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.18:29:53.54#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.18:29:53.54#ibcon#enter wrdev, iclass 12, count 0 2006.173.18:29:53.54#ibcon#first serial, iclass 12, count 0 2006.173.18:29:53.54#ibcon#enter sib2, iclass 12, count 0 2006.173.18:29:53.54#ibcon#flushed, iclass 12, count 0 2006.173.18:29:53.54#ibcon#about to write, iclass 12, count 0 2006.173.18:29:53.54#ibcon#wrote, iclass 12, count 0 2006.173.18:29:53.54#ibcon#about to read 3, iclass 12, count 0 2006.173.18:29:53.56#ibcon#read 3, iclass 12, count 0 2006.173.18:29:53.56#ibcon#about to read 4, iclass 12, count 0 2006.173.18:29:53.56#ibcon#read 4, iclass 12, count 0 2006.173.18:29:53.56#ibcon#about to read 5, iclass 12, count 0 2006.173.18:29:53.56#ibcon#read 5, iclass 12, count 0 2006.173.18:29:53.56#ibcon#about to read 6, iclass 12, count 0 2006.173.18:29:53.56#ibcon#read 6, iclass 12, count 0 2006.173.18:29:53.56#ibcon#end of sib2, iclass 12, count 0 2006.173.18:29:53.56#ibcon#*mode == 0, iclass 12, count 0 2006.173.18:29:53.56#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.18:29:53.56#ibcon#[25=USB\r\n] 2006.173.18:29:53.56#ibcon#*before write, iclass 12, count 0 2006.173.18:29:53.56#ibcon#enter sib2, iclass 12, count 0 2006.173.18:29:53.56#ibcon#flushed, iclass 12, count 0 2006.173.18:29:53.56#ibcon#about to write, iclass 12, count 0 2006.173.18:29:53.56#ibcon#wrote, iclass 12, count 0 2006.173.18:29:53.56#ibcon#about to read 3, iclass 12, count 0 2006.173.18:29:53.59#ibcon#read 3, iclass 12, count 0 2006.173.18:29:53.59#ibcon#about to read 4, iclass 12, count 0 2006.173.18:29:53.59#ibcon#read 4, iclass 12, count 0 2006.173.18:29:53.59#ibcon#about to read 5, iclass 12, count 0 2006.173.18:29:53.59#ibcon#read 5, iclass 12, count 0 2006.173.18:29:53.59#ibcon#about to read 6, iclass 12, count 0 2006.173.18:29:53.59#ibcon#read 6, iclass 12, count 0 2006.173.18:29:53.59#ibcon#end of sib2, iclass 12, count 0 2006.173.18:29:53.59#ibcon#*after write, iclass 12, count 0 2006.173.18:29:53.59#ibcon#*before return 0, iclass 12, count 0 2006.173.18:29:53.59#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.18:29:53.59#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.18:29:53.59#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.18:29:53.59#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.18:29:53.59$vck44/valo=7,864.99 2006.173.18:29:53.59#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.18:29:53.59#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.18:29:53.59#ibcon#ireg 17 cls_cnt 0 2006.173.18:29:53.59#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.18:29:53.59#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.18:29:53.59#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.18:29:53.59#ibcon#enter wrdev, iclass 14, count 0 2006.173.18:29:53.59#ibcon#first serial, iclass 14, count 0 2006.173.18:29:53.59#ibcon#enter sib2, iclass 14, count 0 2006.173.18:29:53.59#ibcon#flushed, iclass 14, count 0 2006.173.18:29:53.59#ibcon#about to write, iclass 14, count 0 2006.173.18:29:53.59#ibcon#wrote, iclass 14, count 0 2006.173.18:29:53.59#ibcon#about to read 3, iclass 14, count 0 2006.173.18:29:53.61#ibcon#read 3, iclass 14, count 0 2006.173.18:29:53.61#ibcon#about to read 4, iclass 14, count 0 2006.173.18:29:53.61#ibcon#read 4, iclass 14, count 0 2006.173.18:29:53.61#ibcon#about to read 5, iclass 14, count 0 2006.173.18:29:53.61#ibcon#read 5, iclass 14, count 0 2006.173.18:29:53.61#ibcon#about to read 6, iclass 14, count 0 2006.173.18:29:53.61#ibcon#read 6, iclass 14, count 0 2006.173.18:29:53.61#ibcon#end of sib2, iclass 14, count 0 2006.173.18:29:53.61#ibcon#*mode == 0, iclass 14, count 0 2006.173.18:29:53.61#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.18:29:53.61#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.18:29:53.61#ibcon#*before write, iclass 14, count 0 2006.173.18:29:53.61#ibcon#enter sib2, iclass 14, count 0 2006.173.18:29:53.61#ibcon#flushed, iclass 14, count 0 2006.173.18:29:53.61#ibcon#about to write, iclass 14, count 0 2006.173.18:29:53.61#ibcon#wrote, iclass 14, count 0 2006.173.18:29:53.61#ibcon#about to read 3, iclass 14, count 0 2006.173.18:29:53.65#ibcon#read 3, iclass 14, count 0 2006.173.18:29:53.65#ibcon#about to read 4, iclass 14, count 0 2006.173.18:29:53.65#ibcon#read 4, iclass 14, count 0 2006.173.18:29:53.65#ibcon#about to read 5, iclass 14, count 0 2006.173.18:29:53.65#ibcon#read 5, iclass 14, count 0 2006.173.18:29:53.65#ibcon#about to read 6, iclass 14, count 0 2006.173.18:29:53.65#ibcon#read 6, iclass 14, count 0 2006.173.18:29:53.65#ibcon#end of sib2, iclass 14, count 0 2006.173.18:29:53.65#ibcon#*after write, iclass 14, count 0 2006.173.18:29:53.65#ibcon#*before return 0, iclass 14, count 0 2006.173.18:29:53.65#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.18:29:53.65#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.18:29:53.65#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.18:29:53.65#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.18:29:53.65$vck44/va=7,4 2006.173.18:29:53.65#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.18:29:53.65#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.18:29:53.65#ibcon#ireg 11 cls_cnt 2 2006.173.18:29:53.65#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.18:29:53.71#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.18:29:53.71#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.18:29:53.71#ibcon#enter wrdev, iclass 16, count 2 2006.173.18:29:53.71#ibcon#first serial, iclass 16, count 2 2006.173.18:29:53.71#ibcon#enter sib2, iclass 16, count 2 2006.173.18:29:53.71#ibcon#flushed, iclass 16, count 2 2006.173.18:29:53.71#ibcon#about to write, iclass 16, count 2 2006.173.18:29:53.71#ibcon#wrote, iclass 16, count 2 2006.173.18:29:53.71#ibcon#about to read 3, iclass 16, count 2 2006.173.18:29:53.73#ibcon#read 3, iclass 16, count 2 2006.173.18:29:53.73#ibcon#about to read 4, iclass 16, count 2 2006.173.18:29:53.73#ibcon#read 4, iclass 16, count 2 2006.173.18:29:53.73#ibcon#about to read 5, iclass 16, count 2 2006.173.18:29:53.73#ibcon#read 5, iclass 16, count 2 2006.173.18:29:53.73#ibcon#about to read 6, iclass 16, count 2 2006.173.18:29:53.73#ibcon#read 6, iclass 16, count 2 2006.173.18:29:53.73#ibcon#end of sib2, iclass 16, count 2 2006.173.18:29:53.73#ibcon#*mode == 0, iclass 16, count 2 2006.173.18:29:53.73#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.18:29:53.73#ibcon#[25=AT07-04\r\n] 2006.173.18:29:53.73#ibcon#*before write, iclass 16, count 2 2006.173.18:29:53.73#ibcon#enter sib2, iclass 16, count 2 2006.173.18:29:53.73#ibcon#flushed, iclass 16, count 2 2006.173.18:29:53.73#ibcon#about to write, iclass 16, count 2 2006.173.18:29:53.73#ibcon#wrote, iclass 16, count 2 2006.173.18:29:53.73#ibcon#about to read 3, iclass 16, count 2 2006.173.18:29:53.76#ibcon#read 3, iclass 16, count 2 2006.173.18:29:53.76#ibcon#about to read 4, iclass 16, count 2 2006.173.18:29:53.76#ibcon#read 4, iclass 16, count 2 2006.173.18:29:53.76#ibcon#about to read 5, iclass 16, count 2 2006.173.18:29:53.76#ibcon#read 5, iclass 16, count 2 2006.173.18:29:53.76#ibcon#about to read 6, iclass 16, count 2 2006.173.18:29:53.76#ibcon#read 6, iclass 16, count 2 2006.173.18:29:53.76#ibcon#end of sib2, iclass 16, count 2 2006.173.18:29:53.76#ibcon#*after write, iclass 16, count 2 2006.173.18:29:53.76#ibcon#*before return 0, iclass 16, count 2 2006.173.18:29:53.76#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.18:29:53.76#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.18:29:53.76#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.18:29:53.76#ibcon#ireg 7 cls_cnt 0 2006.173.18:29:53.76#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.18:29:53.88#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.18:29:53.88#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.18:29:53.88#ibcon#enter wrdev, iclass 16, count 0 2006.173.18:29:53.88#ibcon#first serial, iclass 16, count 0 2006.173.18:29:53.88#ibcon#enter sib2, iclass 16, count 0 2006.173.18:29:53.88#ibcon#flushed, iclass 16, count 0 2006.173.18:29:53.88#ibcon#about to write, iclass 16, count 0 2006.173.18:29:53.88#ibcon#wrote, iclass 16, count 0 2006.173.18:29:53.88#ibcon#about to read 3, iclass 16, count 0 2006.173.18:29:53.90#ibcon#read 3, iclass 16, count 0 2006.173.18:29:53.90#ibcon#about to read 4, iclass 16, count 0 2006.173.18:29:53.90#ibcon#read 4, iclass 16, count 0 2006.173.18:29:53.90#ibcon#about to read 5, iclass 16, count 0 2006.173.18:29:53.90#ibcon#read 5, iclass 16, count 0 2006.173.18:29:53.90#ibcon#about to read 6, iclass 16, count 0 2006.173.18:29:53.90#ibcon#read 6, iclass 16, count 0 2006.173.18:29:53.90#ibcon#end of sib2, iclass 16, count 0 2006.173.18:29:53.90#ibcon#*mode == 0, iclass 16, count 0 2006.173.18:29:53.90#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.18:29:53.90#ibcon#[25=USB\r\n] 2006.173.18:29:53.90#ibcon#*before write, iclass 16, count 0 2006.173.18:29:53.90#ibcon#enter sib2, iclass 16, count 0 2006.173.18:29:53.90#ibcon#flushed, iclass 16, count 0 2006.173.18:29:53.90#ibcon#about to write, iclass 16, count 0 2006.173.18:29:53.90#ibcon#wrote, iclass 16, count 0 2006.173.18:29:53.90#ibcon#about to read 3, iclass 16, count 0 2006.173.18:29:53.93#ibcon#read 3, iclass 16, count 0 2006.173.18:29:53.93#ibcon#about to read 4, iclass 16, count 0 2006.173.18:29:53.93#ibcon#read 4, iclass 16, count 0 2006.173.18:29:53.93#ibcon#about to read 5, iclass 16, count 0 2006.173.18:29:53.93#ibcon#read 5, iclass 16, count 0 2006.173.18:29:53.93#ibcon#about to read 6, iclass 16, count 0 2006.173.18:29:53.93#ibcon#read 6, iclass 16, count 0 2006.173.18:29:53.93#ibcon#end of sib2, iclass 16, count 0 2006.173.18:29:53.93#ibcon#*after write, iclass 16, count 0 2006.173.18:29:53.93#ibcon#*before return 0, iclass 16, count 0 2006.173.18:29:53.93#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.18:29:53.93#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.18:29:53.93#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.18:29:53.93#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.18:29:53.93$vck44/valo=8,884.99 2006.173.18:29:53.93#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.18:29:53.93#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.18:29:53.93#ibcon#ireg 17 cls_cnt 0 2006.173.18:29:53.93#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.18:29:53.93#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.18:29:53.93#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.18:29:53.93#ibcon#enter wrdev, iclass 18, count 0 2006.173.18:29:53.93#ibcon#first serial, iclass 18, count 0 2006.173.18:29:53.93#ibcon#enter sib2, iclass 18, count 0 2006.173.18:29:53.93#ibcon#flushed, iclass 18, count 0 2006.173.18:29:53.93#ibcon#about to write, iclass 18, count 0 2006.173.18:29:53.93#ibcon#wrote, iclass 18, count 0 2006.173.18:29:53.93#ibcon#about to read 3, iclass 18, count 0 2006.173.18:29:53.95#ibcon#read 3, iclass 18, count 0 2006.173.18:29:53.95#ibcon#about to read 4, iclass 18, count 0 2006.173.18:29:53.95#ibcon#read 4, iclass 18, count 0 2006.173.18:29:53.95#ibcon#about to read 5, iclass 18, count 0 2006.173.18:29:53.95#ibcon#read 5, iclass 18, count 0 2006.173.18:29:53.95#ibcon#about to read 6, iclass 18, count 0 2006.173.18:29:53.95#ibcon#read 6, iclass 18, count 0 2006.173.18:29:53.95#ibcon#end of sib2, iclass 18, count 0 2006.173.18:29:53.95#ibcon#*mode == 0, iclass 18, count 0 2006.173.18:29:53.95#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.18:29:53.95#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.18:29:53.95#ibcon#*before write, iclass 18, count 0 2006.173.18:29:53.95#ibcon#enter sib2, iclass 18, count 0 2006.173.18:29:53.95#ibcon#flushed, iclass 18, count 0 2006.173.18:29:53.95#ibcon#about to write, iclass 18, count 0 2006.173.18:29:53.95#ibcon#wrote, iclass 18, count 0 2006.173.18:29:53.95#ibcon#about to read 3, iclass 18, count 0 2006.173.18:29:53.99#ibcon#read 3, iclass 18, count 0 2006.173.18:29:53.99#ibcon#about to read 4, iclass 18, count 0 2006.173.18:29:53.99#ibcon#read 4, iclass 18, count 0 2006.173.18:29:53.99#ibcon#about to read 5, iclass 18, count 0 2006.173.18:29:53.99#ibcon#read 5, iclass 18, count 0 2006.173.18:29:53.99#ibcon#about to read 6, iclass 18, count 0 2006.173.18:29:53.99#ibcon#read 6, iclass 18, count 0 2006.173.18:29:53.99#ibcon#end of sib2, iclass 18, count 0 2006.173.18:29:53.99#ibcon#*after write, iclass 18, count 0 2006.173.18:29:53.99#ibcon#*before return 0, iclass 18, count 0 2006.173.18:29:53.99#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.18:29:53.99#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.18:29:53.99#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.18:29:53.99#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.18:29:53.99$vck44/va=8,4 2006.173.18:29:53.99#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.18:29:53.99#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.18:29:53.99#ibcon#ireg 11 cls_cnt 2 2006.173.18:29:53.99#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.18:29:54.05#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.18:29:54.05#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.18:29:54.05#ibcon#enter wrdev, iclass 20, count 2 2006.173.18:29:54.05#ibcon#first serial, iclass 20, count 2 2006.173.18:29:54.05#ibcon#enter sib2, iclass 20, count 2 2006.173.18:29:54.05#ibcon#flushed, iclass 20, count 2 2006.173.18:29:54.05#ibcon#about to write, iclass 20, count 2 2006.173.18:29:54.05#ibcon#wrote, iclass 20, count 2 2006.173.18:29:54.05#ibcon#about to read 3, iclass 20, count 2 2006.173.18:29:54.07#ibcon#read 3, iclass 20, count 2 2006.173.18:29:54.07#ibcon#about to read 4, iclass 20, count 2 2006.173.18:29:54.07#ibcon#read 4, iclass 20, count 2 2006.173.18:29:54.07#ibcon#about to read 5, iclass 20, count 2 2006.173.18:29:54.07#ibcon#read 5, iclass 20, count 2 2006.173.18:29:54.07#ibcon#about to read 6, iclass 20, count 2 2006.173.18:29:54.07#ibcon#read 6, iclass 20, count 2 2006.173.18:29:54.07#ibcon#end of sib2, iclass 20, count 2 2006.173.18:29:54.07#ibcon#*mode == 0, iclass 20, count 2 2006.173.18:29:54.07#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.18:29:54.07#ibcon#[25=AT08-04\r\n] 2006.173.18:29:54.07#ibcon#*before write, iclass 20, count 2 2006.173.18:29:54.07#ibcon#enter sib2, iclass 20, count 2 2006.173.18:29:54.07#ibcon#flushed, iclass 20, count 2 2006.173.18:29:54.07#ibcon#about to write, iclass 20, count 2 2006.173.18:29:54.07#ibcon#wrote, iclass 20, count 2 2006.173.18:29:54.07#ibcon#about to read 3, iclass 20, count 2 2006.173.18:29:54.10#ibcon#read 3, iclass 20, count 2 2006.173.18:29:54.10#ibcon#about to read 4, iclass 20, count 2 2006.173.18:29:54.10#ibcon#read 4, iclass 20, count 2 2006.173.18:29:54.10#ibcon#about to read 5, iclass 20, count 2 2006.173.18:29:54.10#ibcon#read 5, iclass 20, count 2 2006.173.18:29:54.10#ibcon#about to read 6, iclass 20, count 2 2006.173.18:29:54.10#ibcon#read 6, iclass 20, count 2 2006.173.18:29:54.10#ibcon#end of sib2, iclass 20, count 2 2006.173.18:29:54.10#ibcon#*after write, iclass 20, count 2 2006.173.18:29:54.10#ibcon#*before return 0, iclass 20, count 2 2006.173.18:29:54.10#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.18:29:54.10#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.18:29:54.10#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.18:29:54.10#ibcon#ireg 7 cls_cnt 0 2006.173.18:29:54.10#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.18:29:54.22#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.18:29:54.22#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.18:29:54.22#ibcon#enter wrdev, iclass 20, count 0 2006.173.18:29:54.22#ibcon#first serial, iclass 20, count 0 2006.173.18:29:54.22#ibcon#enter sib2, iclass 20, count 0 2006.173.18:29:54.22#ibcon#flushed, iclass 20, count 0 2006.173.18:29:54.22#ibcon#about to write, iclass 20, count 0 2006.173.18:29:54.22#ibcon#wrote, iclass 20, count 0 2006.173.18:29:54.22#ibcon#about to read 3, iclass 20, count 0 2006.173.18:29:54.24#ibcon#read 3, iclass 20, count 0 2006.173.18:29:54.24#ibcon#about to read 4, iclass 20, count 0 2006.173.18:29:54.24#ibcon#read 4, iclass 20, count 0 2006.173.18:29:54.24#ibcon#about to read 5, iclass 20, count 0 2006.173.18:29:54.24#ibcon#read 5, iclass 20, count 0 2006.173.18:29:54.24#ibcon#about to read 6, iclass 20, count 0 2006.173.18:29:54.24#ibcon#read 6, iclass 20, count 0 2006.173.18:29:54.24#ibcon#end of sib2, iclass 20, count 0 2006.173.18:29:54.24#ibcon#*mode == 0, iclass 20, count 0 2006.173.18:29:54.24#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.18:29:54.24#ibcon#[25=USB\r\n] 2006.173.18:29:54.24#ibcon#*before write, iclass 20, count 0 2006.173.18:29:54.24#ibcon#enter sib2, iclass 20, count 0 2006.173.18:29:54.24#ibcon#flushed, iclass 20, count 0 2006.173.18:29:54.24#ibcon#about to write, iclass 20, count 0 2006.173.18:29:54.24#ibcon#wrote, iclass 20, count 0 2006.173.18:29:54.24#ibcon#about to read 3, iclass 20, count 0 2006.173.18:29:54.27#ibcon#read 3, iclass 20, count 0 2006.173.18:29:54.27#ibcon#about to read 4, iclass 20, count 0 2006.173.18:29:54.27#ibcon#read 4, iclass 20, count 0 2006.173.18:29:54.27#ibcon#about to read 5, iclass 20, count 0 2006.173.18:29:54.27#ibcon#read 5, iclass 20, count 0 2006.173.18:29:54.27#ibcon#about to read 6, iclass 20, count 0 2006.173.18:29:54.27#ibcon#read 6, iclass 20, count 0 2006.173.18:29:54.27#ibcon#end of sib2, iclass 20, count 0 2006.173.18:29:54.27#ibcon#*after write, iclass 20, count 0 2006.173.18:29:54.27#ibcon#*before return 0, iclass 20, count 0 2006.173.18:29:54.27#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.18:29:54.27#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.18:29:54.27#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.18:29:54.27#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.18:29:54.27$vck44/vblo=1,629.99 2006.173.18:29:54.27#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.18:29:54.27#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.18:29:54.27#ibcon#ireg 17 cls_cnt 0 2006.173.18:29:54.27#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.18:29:54.27#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.18:29:54.27#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.18:29:54.27#ibcon#enter wrdev, iclass 22, count 0 2006.173.18:29:54.27#ibcon#first serial, iclass 22, count 0 2006.173.18:29:54.27#ibcon#enter sib2, iclass 22, count 0 2006.173.18:29:54.27#ibcon#flushed, iclass 22, count 0 2006.173.18:29:54.27#ibcon#about to write, iclass 22, count 0 2006.173.18:29:54.27#ibcon#wrote, iclass 22, count 0 2006.173.18:29:54.27#ibcon#about to read 3, iclass 22, count 0 2006.173.18:29:54.29#ibcon#read 3, iclass 22, count 0 2006.173.18:29:54.29#ibcon#about to read 4, iclass 22, count 0 2006.173.18:29:54.29#ibcon#read 4, iclass 22, count 0 2006.173.18:29:54.29#ibcon#about to read 5, iclass 22, count 0 2006.173.18:29:54.29#ibcon#read 5, iclass 22, count 0 2006.173.18:29:54.29#ibcon#about to read 6, iclass 22, count 0 2006.173.18:29:54.29#ibcon#read 6, iclass 22, count 0 2006.173.18:29:54.29#ibcon#end of sib2, iclass 22, count 0 2006.173.18:29:54.29#ibcon#*mode == 0, iclass 22, count 0 2006.173.18:29:54.29#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.18:29:54.29#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.18:29:54.29#ibcon#*before write, iclass 22, count 0 2006.173.18:29:54.29#ibcon#enter sib2, iclass 22, count 0 2006.173.18:29:54.29#ibcon#flushed, iclass 22, count 0 2006.173.18:29:54.29#ibcon#about to write, iclass 22, count 0 2006.173.18:29:54.29#ibcon#wrote, iclass 22, count 0 2006.173.18:29:54.29#ibcon#about to read 3, iclass 22, count 0 2006.173.18:29:54.33#ibcon#read 3, iclass 22, count 0 2006.173.18:29:54.33#ibcon#about to read 4, iclass 22, count 0 2006.173.18:29:54.33#ibcon#read 4, iclass 22, count 0 2006.173.18:29:54.33#ibcon#about to read 5, iclass 22, count 0 2006.173.18:29:54.33#ibcon#read 5, iclass 22, count 0 2006.173.18:29:54.33#ibcon#about to read 6, iclass 22, count 0 2006.173.18:29:54.33#ibcon#read 6, iclass 22, count 0 2006.173.18:29:54.33#ibcon#end of sib2, iclass 22, count 0 2006.173.18:29:54.33#ibcon#*after write, iclass 22, count 0 2006.173.18:29:54.33#ibcon#*before return 0, iclass 22, count 0 2006.173.18:29:54.33#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.18:29:54.33#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.18:29:54.33#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.18:29:54.33#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.18:29:54.33$vck44/vb=1,4 2006.173.18:29:54.33#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.18:29:54.33#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.18:29:54.33#ibcon#ireg 11 cls_cnt 2 2006.173.18:29:54.33#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.18:29:54.33#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.18:29:54.33#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.18:29:54.33#ibcon#enter wrdev, iclass 24, count 2 2006.173.18:29:54.33#ibcon#first serial, iclass 24, count 2 2006.173.18:29:54.33#ibcon#enter sib2, iclass 24, count 2 2006.173.18:29:54.33#ibcon#flushed, iclass 24, count 2 2006.173.18:29:54.33#ibcon#about to write, iclass 24, count 2 2006.173.18:29:54.33#ibcon#wrote, iclass 24, count 2 2006.173.18:29:54.33#ibcon#about to read 3, iclass 24, count 2 2006.173.18:29:54.35#ibcon#read 3, iclass 24, count 2 2006.173.18:29:54.35#ibcon#about to read 4, iclass 24, count 2 2006.173.18:29:54.35#ibcon#read 4, iclass 24, count 2 2006.173.18:29:54.35#ibcon#about to read 5, iclass 24, count 2 2006.173.18:29:54.35#ibcon#read 5, iclass 24, count 2 2006.173.18:29:54.35#ibcon#about to read 6, iclass 24, count 2 2006.173.18:29:54.35#ibcon#read 6, iclass 24, count 2 2006.173.18:29:54.35#ibcon#end of sib2, iclass 24, count 2 2006.173.18:29:54.35#ibcon#*mode == 0, iclass 24, count 2 2006.173.18:29:54.35#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.18:29:54.35#ibcon#[27=AT01-04\r\n] 2006.173.18:29:54.35#ibcon#*before write, iclass 24, count 2 2006.173.18:29:54.35#ibcon#enter sib2, iclass 24, count 2 2006.173.18:29:54.35#ibcon#flushed, iclass 24, count 2 2006.173.18:29:54.35#ibcon#about to write, iclass 24, count 2 2006.173.18:29:54.35#ibcon#wrote, iclass 24, count 2 2006.173.18:29:54.35#ibcon#about to read 3, iclass 24, count 2 2006.173.18:29:54.38#ibcon#read 3, iclass 24, count 2 2006.173.18:29:54.38#ibcon#about to read 4, iclass 24, count 2 2006.173.18:29:54.38#ibcon#read 4, iclass 24, count 2 2006.173.18:29:54.38#ibcon#about to read 5, iclass 24, count 2 2006.173.18:29:54.38#ibcon#read 5, iclass 24, count 2 2006.173.18:29:54.38#ibcon#about to read 6, iclass 24, count 2 2006.173.18:29:54.38#ibcon#read 6, iclass 24, count 2 2006.173.18:29:54.38#ibcon#end of sib2, iclass 24, count 2 2006.173.18:29:54.38#ibcon#*after write, iclass 24, count 2 2006.173.18:29:54.38#ibcon#*before return 0, iclass 24, count 2 2006.173.18:29:54.38#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.18:29:54.38#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.18:29:54.38#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.18:29:54.38#ibcon#ireg 7 cls_cnt 0 2006.173.18:29:54.38#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.18:29:54.50#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.18:29:54.50#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.18:29:54.50#ibcon#enter wrdev, iclass 24, count 0 2006.173.18:29:54.50#ibcon#first serial, iclass 24, count 0 2006.173.18:29:54.50#ibcon#enter sib2, iclass 24, count 0 2006.173.18:29:54.50#ibcon#flushed, iclass 24, count 0 2006.173.18:29:54.50#ibcon#about to write, iclass 24, count 0 2006.173.18:29:54.50#ibcon#wrote, iclass 24, count 0 2006.173.18:29:54.50#ibcon#about to read 3, iclass 24, count 0 2006.173.18:29:54.52#ibcon#read 3, iclass 24, count 0 2006.173.18:29:54.52#ibcon#about to read 4, iclass 24, count 0 2006.173.18:29:54.52#ibcon#read 4, iclass 24, count 0 2006.173.18:29:54.52#ibcon#about to read 5, iclass 24, count 0 2006.173.18:29:54.52#ibcon#read 5, iclass 24, count 0 2006.173.18:29:54.52#ibcon#about to read 6, iclass 24, count 0 2006.173.18:29:54.52#ibcon#read 6, iclass 24, count 0 2006.173.18:29:54.52#ibcon#end of sib2, iclass 24, count 0 2006.173.18:29:54.52#ibcon#*mode == 0, iclass 24, count 0 2006.173.18:29:54.52#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.18:29:54.52#ibcon#[27=USB\r\n] 2006.173.18:29:54.52#ibcon#*before write, iclass 24, count 0 2006.173.18:29:54.52#ibcon#enter sib2, iclass 24, count 0 2006.173.18:29:54.52#ibcon#flushed, iclass 24, count 0 2006.173.18:29:54.52#ibcon#about to write, iclass 24, count 0 2006.173.18:29:54.52#ibcon#wrote, iclass 24, count 0 2006.173.18:29:54.52#ibcon#about to read 3, iclass 24, count 0 2006.173.18:29:54.55#ibcon#read 3, iclass 24, count 0 2006.173.18:29:54.55#ibcon#about to read 4, iclass 24, count 0 2006.173.18:29:54.55#ibcon#read 4, iclass 24, count 0 2006.173.18:29:54.55#ibcon#about to read 5, iclass 24, count 0 2006.173.18:29:54.55#ibcon#read 5, iclass 24, count 0 2006.173.18:29:54.55#ibcon#about to read 6, iclass 24, count 0 2006.173.18:29:54.55#ibcon#read 6, iclass 24, count 0 2006.173.18:29:54.55#ibcon#end of sib2, iclass 24, count 0 2006.173.18:29:54.55#ibcon#*after write, iclass 24, count 0 2006.173.18:29:54.55#ibcon#*before return 0, iclass 24, count 0 2006.173.18:29:54.55#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.18:29:54.55#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.18:29:54.55#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.18:29:54.55#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.18:29:54.55$vck44/vblo=2,634.99 2006.173.18:29:54.55#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.18:29:54.55#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.18:29:54.55#ibcon#ireg 17 cls_cnt 0 2006.173.18:29:54.55#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.18:29:54.55#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.18:29:54.55#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.18:29:54.55#ibcon#enter wrdev, iclass 26, count 0 2006.173.18:29:54.55#ibcon#first serial, iclass 26, count 0 2006.173.18:29:54.55#ibcon#enter sib2, iclass 26, count 0 2006.173.18:29:54.55#ibcon#flushed, iclass 26, count 0 2006.173.18:29:54.55#ibcon#about to write, iclass 26, count 0 2006.173.18:29:54.55#ibcon#wrote, iclass 26, count 0 2006.173.18:29:54.55#ibcon#about to read 3, iclass 26, count 0 2006.173.18:29:54.57#ibcon#read 3, iclass 26, count 0 2006.173.18:29:54.57#ibcon#about to read 4, iclass 26, count 0 2006.173.18:29:54.57#ibcon#read 4, iclass 26, count 0 2006.173.18:29:54.57#ibcon#about to read 5, iclass 26, count 0 2006.173.18:29:54.57#ibcon#read 5, iclass 26, count 0 2006.173.18:29:54.57#ibcon#about to read 6, iclass 26, count 0 2006.173.18:29:54.57#ibcon#read 6, iclass 26, count 0 2006.173.18:29:54.57#ibcon#end of sib2, iclass 26, count 0 2006.173.18:29:54.57#ibcon#*mode == 0, iclass 26, count 0 2006.173.18:29:54.57#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.18:29:54.57#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.18:29:54.57#ibcon#*before write, iclass 26, count 0 2006.173.18:29:54.57#ibcon#enter sib2, iclass 26, count 0 2006.173.18:29:54.57#ibcon#flushed, iclass 26, count 0 2006.173.18:29:54.57#ibcon#about to write, iclass 26, count 0 2006.173.18:29:54.57#ibcon#wrote, iclass 26, count 0 2006.173.18:29:54.57#ibcon#about to read 3, iclass 26, count 0 2006.173.18:29:54.61#ibcon#read 3, iclass 26, count 0 2006.173.18:29:54.61#ibcon#about to read 4, iclass 26, count 0 2006.173.18:29:54.61#ibcon#read 4, iclass 26, count 0 2006.173.18:29:54.61#ibcon#about to read 5, iclass 26, count 0 2006.173.18:29:54.61#ibcon#read 5, iclass 26, count 0 2006.173.18:29:54.61#ibcon#about to read 6, iclass 26, count 0 2006.173.18:29:54.61#ibcon#read 6, iclass 26, count 0 2006.173.18:29:54.61#ibcon#end of sib2, iclass 26, count 0 2006.173.18:29:54.61#ibcon#*after write, iclass 26, count 0 2006.173.18:29:54.61#ibcon#*before return 0, iclass 26, count 0 2006.173.18:29:54.61#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.18:29:54.61#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.18:29:54.61#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.18:29:54.61#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.18:29:54.61$vck44/vb=2,4 2006.173.18:29:54.61#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.18:29:54.61#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.18:29:54.61#ibcon#ireg 11 cls_cnt 2 2006.173.18:29:54.61#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.18:29:54.67#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.18:29:54.67#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.18:29:54.67#ibcon#enter wrdev, iclass 28, count 2 2006.173.18:29:54.67#ibcon#first serial, iclass 28, count 2 2006.173.18:29:54.67#ibcon#enter sib2, iclass 28, count 2 2006.173.18:29:54.67#ibcon#flushed, iclass 28, count 2 2006.173.18:29:54.67#ibcon#about to write, iclass 28, count 2 2006.173.18:29:54.67#ibcon#wrote, iclass 28, count 2 2006.173.18:29:54.67#ibcon#about to read 3, iclass 28, count 2 2006.173.18:29:54.69#ibcon#read 3, iclass 28, count 2 2006.173.18:29:54.69#ibcon#about to read 4, iclass 28, count 2 2006.173.18:29:54.69#ibcon#read 4, iclass 28, count 2 2006.173.18:29:54.69#ibcon#about to read 5, iclass 28, count 2 2006.173.18:29:54.69#ibcon#read 5, iclass 28, count 2 2006.173.18:29:54.69#ibcon#about to read 6, iclass 28, count 2 2006.173.18:29:54.69#ibcon#read 6, iclass 28, count 2 2006.173.18:29:54.69#ibcon#end of sib2, iclass 28, count 2 2006.173.18:29:54.69#ibcon#*mode == 0, iclass 28, count 2 2006.173.18:29:54.69#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.18:29:54.69#ibcon#[27=AT02-04\r\n] 2006.173.18:29:54.69#ibcon#*before write, iclass 28, count 2 2006.173.18:29:54.69#ibcon#enter sib2, iclass 28, count 2 2006.173.18:29:54.69#ibcon#flushed, iclass 28, count 2 2006.173.18:29:54.69#ibcon#about to write, iclass 28, count 2 2006.173.18:29:54.69#ibcon#wrote, iclass 28, count 2 2006.173.18:29:54.69#ibcon#about to read 3, iclass 28, count 2 2006.173.18:29:54.72#ibcon#read 3, iclass 28, count 2 2006.173.18:29:54.72#ibcon#about to read 4, iclass 28, count 2 2006.173.18:29:54.72#ibcon#read 4, iclass 28, count 2 2006.173.18:29:54.72#ibcon#about to read 5, iclass 28, count 2 2006.173.18:29:54.72#ibcon#read 5, iclass 28, count 2 2006.173.18:29:54.72#ibcon#about to read 6, iclass 28, count 2 2006.173.18:29:54.72#ibcon#read 6, iclass 28, count 2 2006.173.18:29:54.72#ibcon#end of sib2, iclass 28, count 2 2006.173.18:29:54.72#ibcon#*after write, iclass 28, count 2 2006.173.18:29:54.72#ibcon#*before return 0, iclass 28, count 2 2006.173.18:29:54.72#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.18:29:54.72#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.18:29:54.72#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.18:29:54.72#ibcon#ireg 7 cls_cnt 0 2006.173.18:29:54.72#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.18:29:54.84#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.18:29:54.84#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.18:29:54.84#ibcon#enter wrdev, iclass 28, count 0 2006.173.18:29:54.84#ibcon#first serial, iclass 28, count 0 2006.173.18:29:54.84#ibcon#enter sib2, iclass 28, count 0 2006.173.18:29:54.84#ibcon#flushed, iclass 28, count 0 2006.173.18:29:54.84#ibcon#about to write, iclass 28, count 0 2006.173.18:29:54.84#ibcon#wrote, iclass 28, count 0 2006.173.18:29:54.84#ibcon#about to read 3, iclass 28, count 0 2006.173.18:29:54.86#ibcon#read 3, iclass 28, count 0 2006.173.18:29:54.86#ibcon#about to read 4, iclass 28, count 0 2006.173.18:29:54.86#ibcon#read 4, iclass 28, count 0 2006.173.18:29:54.86#ibcon#about to read 5, iclass 28, count 0 2006.173.18:29:54.86#ibcon#read 5, iclass 28, count 0 2006.173.18:29:54.86#ibcon#about to read 6, iclass 28, count 0 2006.173.18:29:54.86#ibcon#read 6, iclass 28, count 0 2006.173.18:29:54.86#ibcon#end of sib2, iclass 28, count 0 2006.173.18:29:54.86#ibcon#*mode == 0, iclass 28, count 0 2006.173.18:29:54.86#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.18:29:54.86#ibcon#[27=USB\r\n] 2006.173.18:29:54.86#ibcon#*before write, iclass 28, count 0 2006.173.18:29:54.86#ibcon#enter sib2, iclass 28, count 0 2006.173.18:29:54.86#ibcon#flushed, iclass 28, count 0 2006.173.18:29:54.86#ibcon#about to write, iclass 28, count 0 2006.173.18:29:54.86#ibcon#wrote, iclass 28, count 0 2006.173.18:29:54.86#ibcon#about to read 3, iclass 28, count 0 2006.173.18:29:54.89#ibcon#read 3, iclass 28, count 0 2006.173.18:29:54.89#ibcon#about to read 4, iclass 28, count 0 2006.173.18:29:54.89#ibcon#read 4, iclass 28, count 0 2006.173.18:29:54.89#ibcon#about to read 5, iclass 28, count 0 2006.173.18:29:54.89#ibcon#read 5, iclass 28, count 0 2006.173.18:29:54.89#ibcon#about to read 6, iclass 28, count 0 2006.173.18:29:54.89#ibcon#read 6, iclass 28, count 0 2006.173.18:29:54.89#ibcon#end of sib2, iclass 28, count 0 2006.173.18:29:54.89#ibcon#*after write, iclass 28, count 0 2006.173.18:29:54.89#ibcon#*before return 0, iclass 28, count 0 2006.173.18:29:54.89#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.18:29:54.89#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.18:29:54.89#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.18:29:54.89#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.18:29:54.89$vck44/vblo=3,649.99 2006.173.18:29:54.89#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.18:29:54.89#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.18:29:54.89#ibcon#ireg 17 cls_cnt 0 2006.173.18:29:54.89#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.18:29:54.89#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.18:29:54.89#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.18:29:54.89#ibcon#enter wrdev, iclass 30, count 0 2006.173.18:29:54.89#ibcon#first serial, iclass 30, count 0 2006.173.18:29:54.89#ibcon#enter sib2, iclass 30, count 0 2006.173.18:29:54.89#ibcon#flushed, iclass 30, count 0 2006.173.18:29:54.89#ibcon#about to write, iclass 30, count 0 2006.173.18:29:54.89#ibcon#wrote, iclass 30, count 0 2006.173.18:29:54.89#ibcon#about to read 3, iclass 30, count 0 2006.173.18:29:54.91#ibcon#read 3, iclass 30, count 0 2006.173.18:29:54.91#ibcon#about to read 4, iclass 30, count 0 2006.173.18:29:54.91#ibcon#read 4, iclass 30, count 0 2006.173.18:29:54.91#ibcon#about to read 5, iclass 30, count 0 2006.173.18:29:54.91#ibcon#read 5, iclass 30, count 0 2006.173.18:29:54.91#ibcon#about to read 6, iclass 30, count 0 2006.173.18:29:54.91#ibcon#read 6, iclass 30, count 0 2006.173.18:29:54.91#ibcon#end of sib2, iclass 30, count 0 2006.173.18:29:54.91#ibcon#*mode == 0, iclass 30, count 0 2006.173.18:29:54.91#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.18:29:54.91#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.18:29:54.91#ibcon#*before write, iclass 30, count 0 2006.173.18:29:54.91#ibcon#enter sib2, iclass 30, count 0 2006.173.18:29:54.91#ibcon#flushed, iclass 30, count 0 2006.173.18:29:54.91#ibcon#about to write, iclass 30, count 0 2006.173.18:29:54.91#ibcon#wrote, iclass 30, count 0 2006.173.18:29:54.91#ibcon#about to read 3, iclass 30, count 0 2006.173.18:29:54.95#ibcon#read 3, iclass 30, count 0 2006.173.18:29:54.95#ibcon#about to read 4, iclass 30, count 0 2006.173.18:29:54.95#ibcon#read 4, iclass 30, count 0 2006.173.18:29:54.95#ibcon#about to read 5, iclass 30, count 0 2006.173.18:29:54.95#ibcon#read 5, iclass 30, count 0 2006.173.18:29:54.95#ibcon#about to read 6, iclass 30, count 0 2006.173.18:29:54.95#ibcon#read 6, iclass 30, count 0 2006.173.18:29:54.95#ibcon#end of sib2, iclass 30, count 0 2006.173.18:29:54.95#ibcon#*after write, iclass 30, count 0 2006.173.18:29:54.95#ibcon#*before return 0, iclass 30, count 0 2006.173.18:29:54.95#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.18:29:54.95#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.18:29:54.95#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.18:29:54.95#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.18:29:54.95$vck44/vb=3,4 2006.173.18:29:54.95#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.173.18:29:54.95#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.173.18:29:54.95#ibcon#ireg 11 cls_cnt 2 2006.173.18:29:54.95#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.18:29:55.01#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.18:29:55.01#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.18:29:55.01#ibcon#enter wrdev, iclass 32, count 2 2006.173.18:29:55.01#ibcon#first serial, iclass 32, count 2 2006.173.18:29:55.01#ibcon#enter sib2, iclass 32, count 2 2006.173.18:29:55.01#ibcon#flushed, iclass 32, count 2 2006.173.18:29:55.01#ibcon#about to write, iclass 32, count 2 2006.173.18:29:55.01#ibcon#wrote, iclass 32, count 2 2006.173.18:29:55.01#ibcon#about to read 3, iclass 32, count 2 2006.173.18:29:55.03#ibcon#read 3, iclass 32, count 2 2006.173.18:29:55.03#ibcon#about to read 4, iclass 32, count 2 2006.173.18:29:55.03#ibcon#read 4, iclass 32, count 2 2006.173.18:29:55.03#ibcon#about to read 5, iclass 32, count 2 2006.173.18:29:55.03#ibcon#read 5, iclass 32, count 2 2006.173.18:29:55.03#ibcon#about to read 6, iclass 32, count 2 2006.173.18:29:55.03#ibcon#read 6, iclass 32, count 2 2006.173.18:29:55.03#ibcon#end of sib2, iclass 32, count 2 2006.173.18:29:55.03#ibcon#*mode == 0, iclass 32, count 2 2006.173.18:29:55.03#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.173.18:29:55.03#ibcon#[27=AT03-04\r\n] 2006.173.18:29:55.03#ibcon#*before write, iclass 32, count 2 2006.173.18:29:55.03#ibcon#enter sib2, iclass 32, count 2 2006.173.18:29:55.03#ibcon#flushed, iclass 32, count 2 2006.173.18:29:55.03#ibcon#about to write, iclass 32, count 2 2006.173.18:29:55.03#ibcon#wrote, iclass 32, count 2 2006.173.18:29:55.03#ibcon#about to read 3, iclass 32, count 2 2006.173.18:29:55.06#ibcon#read 3, iclass 32, count 2 2006.173.18:29:55.06#ibcon#about to read 4, iclass 32, count 2 2006.173.18:29:55.06#ibcon#read 4, iclass 32, count 2 2006.173.18:29:55.06#ibcon#about to read 5, iclass 32, count 2 2006.173.18:29:55.06#ibcon#read 5, iclass 32, count 2 2006.173.18:29:55.06#ibcon#about to read 6, iclass 32, count 2 2006.173.18:29:55.06#ibcon#read 6, iclass 32, count 2 2006.173.18:29:55.06#ibcon#end of sib2, iclass 32, count 2 2006.173.18:29:55.06#ibcon#*after write, iclass 32, count 2 2006.173.18:29:55.06#ibcon#*before return 0, iclass 32, count 2 2006.173.18:29:55.06#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.18:29:55.06#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.173.18:29:55.06#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.173.18:29:55.06#ibcon#ireg 7 cls_cnt 0 2006.173.18:29:55.06#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.18:29:55.18#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.18:29:55.18#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.18:29:55.18#ibcon#enter wrdev, iclass 32, count 0 2006.173.18:29:55.18#ibcon#first serial, iclass 32, count 0 2006.173.18:29:55.18#ibcon#enter sib2, iclass 32, count 0 2006.173.18:29:55.18#ibcon#flushed, iclass 32, count 0 2006.173.18:29:55.18#ibcon#about to write, iclass 32, count 0 2006.173.18:29:55.18#ibcon#wrote, iclass 32, count 0 2006.173.18:29:55.18#ibcon#about to read 3, iclass 32, count 0 2006.173.18:29:55.20#ibcon#read 3, iclass 32, count 0 2006.173.18:29:55.20#ibcon#about to read 4, iclass 32, count 0 2006.173.18:29:55.20#ibcon#read 4, iclass 32, count 0 2006.173.18:29:55.20#ibcon#about to read 5, iclass 32, count 0 2006.173.18:29:55.20#ibcon#read 5, iclass 32, count 0 2006.173.18:29:55.20#ibcon#about to read 6, iclass 32, count 0 2006.173.18:29:55.20#ibcon#read 6, iclass 32, count 0 2006.173.18:29:55.20#ibcon#end of sib2, iclass 32, count 0 2006.173.18:29:55.20#ibcon#*mode == 0, iclass 32, count 0 2006.173.18:29:55.20#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.18:29:55.20#ibcon#[27=USB\r\n] 2006.173.18:29:55.20#ibcon#*before write, iclass 32, count 0 2006.173.18:29:55.20#ibcon#enter sib2, iclass 32, count 0 2006.173.18:29:55.20#ibcon#flushed, iclass 32, count 0 2006.173.18:29:55.20#ibcon#about to write, iclass 32, count 0 2006.173.18:29:55.20#ibcon#wrote, iclass 32, count 0 2006.173.18:29:55.20#ibcon#about to read 3, iclass 32, count 0 2006.173.18:29:55.23#ibcon#read 3, iclass 32, count 0 2006.173.18:29:55.23#ibcon#about to read 4, iclass 32, count 0 2006.173.18:29:55.23#ibcon#read 4, iclass 32, count 0 2006.173.18:29:55.23#ibcon#about to read 5, iclass 32, count 0 2006.173.18:29:55.23#ibcon#read 5, iclass 32, count 0 2006.173.18:29:55.23#ibcon#about to read 6, iclass 32, count 0 2006.173.18:29:55.23#ibcon#read 6, iclass 32, count 0 2006.173.18:29:55.23#ibcon#end of sib2, iclass 32, count 0 2006.173.18:29:55.23#ibcon#*after write, iclass 32, count 0 2006.173.18:29:55.23#ibcon#*before return 0, iclass 32, count 0 2006.173.18:29:55.23#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.18:29:55.23#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.173.18:29:55.23#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.18:29:55.23#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.18:29:55.23$vck44/vblo=4,679.99 2006.173.18:29:55.23#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.18:29:55.23#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.18:29:55.23#ibcon#ireg 17 cls_cnt 0 2006.173.18:29:55.23#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.18:29:55.23#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.18:29:55.23#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.18:29:55.23#ibcon#enter wrdev, iclass 34, count 0 2006.173.18:29:55.23#ibcon#first serial, iclass 34, count 0 2006.173.18:29:55.23#ibcon#enter sib2, iclass 34, count 0 2006.173.18:29:55.23#ibcon#flushed, iclass 34, count 0 2006.173.18:29:55.23#ibcon#about to write, iclass 34, count 0 2006.173.18:29:55.23#ibcon#wrote, iclass 34, count 0 2006.173.18:29:55.23#ibcon#about to read 3, iclass 34, count 0 2006.173.18:29:55.25#ibcon#read 3, iclass 34, count 0 2006.173.18:29:55.25#ibcon#about to read 4, iclass 34, count 0 2006.173.18:29:55.25#ibcon#read 4, iclass 34, count 0 2006.173.18:29:55.25#ibcon#about to read 5, iclass 34, count 0 2006.173.18:29:55.25#ibcon#read 5, iclass 34, count 0 2006.173.18:29:55.25#ibcon#about to read 6, iclass 34, count 0 2006.173.18:29:55.25#ibcon#read 6, iclass 34, count 0 2006.173.18:29:55.25#ibcon#end of sib2, iclass 34, count 0 2006.173.18:29:55.25#ibcon#*mode == 0, iclass 34, count 0 2006.173.18:29:55.25#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.18:29:55.25#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.18:29:55.25#ibcon#*before write, iclass 34, count 0 2006.173.18:29:55.25#ibcon#enter sib2, iclass 34, count 0 2006.173.18:29:55.25#ibcon#flushed, iclass 34, count 0 2006.173.18:29:55.25#ibcon#about to write, iclass 34, count 0 2006.173.18:29:55.25#ibcon#wrote, iclass 34, count 0 2006.173.18:29:55.25#ibcon#about to read 3, iclass 34, count 0 2006.173.18:29:55.29#ibcon#read 3, iclass 34, count 0 2006.173.18:29:55.29#ibcon#about to read 4, iclass 34, count 0 2006.173.18:29:55.29#ibcon#read 4, iclass 34, count 0 2006.173.18:29:55.29#ibcon#about to read 5, iclass 34, count 0 2006.173.18:29:55.29#ibcon#read 5, iclass 34, count 0 2006.173.18:29:55.29#ibcon#about to read 6, iclass 34, count 0 2006.173.18:29:55.29#ibcon#read 6, iclass 34, count 0 2006.173.18:29:55.29#ibcon#end of sib2, iclass 34, count 0 2006.173.18:29:55.29#ibcon#*after write, iclass 34, count 0 2006.173.18:29:55.29#ibcon#*before return 0, iclass 34, count 0 2006.173.18:29:55.29#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.18:29:55.29#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.18:29:55.29#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.18:29:55.29#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.18:29:55.29$vck44/vb=4,4 2006.173.18:29:55.29#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.18:29:55.29#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.18:29:55.29#ibcon#ireg 11 cls_cnt 2 2006.173.18:29:55.29#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.18:29:55.35#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.18:29:55.35#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.18:29:55.35#ibcon#enter wrdev, iclass 36, count 2 2006.173.18:29:55.35#ibcon#first serial, iclass 36, count 2 2006.173.18:29:55.35#ibcon#enter sib2, iclass 36, count 2 2006.173.18:29:55.35#ibcon#flushed, iclass 36, count 2 2006.173.18:29:55.35#ibcon#about to write, iclass 36, count 2 2006.173.18:29:55.35#ibcon#wrote, iclass 36, count 2 2006.173.18:29:55.35#ibcon#about to read 3, iclass 36, count 2 2006.173.18:29:55.37#ibcon#read 3, iclass 36, count 2 2006.173.18:29:55.37#ibcon#about to read 4, iclass 36, count 2 2006.173.18:29:55.37#ibcon#read 4, iclass 36, count 2 2006.173.18:29:55.37#ibcon#about to read 5, iclass 36, count 2 2006.173.18:29:55.37#ibcon#read 5, iclass 36, count 2 2006.173.18:29:55.37#ibcon#about to read 6, iclass 36, count 2 2006.173.18:29:55.37#ibcon#read 6, iclass 36, count 2 2006.173.18:29:55.37#ibcon#end of sib2, iclass 36, count 2 2006.173.18:29:55.37#ibcon#*mode == 0, iclass 36, count 2 2006.173.18:29:55.37#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.18:29:55.37#ibcon#[27=AT04-04\r\n] 2006.173.18:29:55.37#ibcon#*before write, iclass 36, count 2 2006.173.18:29:55.37#ibcon#enter sib2, iclass 36, count 2 2006.173.18:29:55.37#ibcon#flushed, iclass 36, count 2 2006.173.18:29:55.37#ibcon#about to write, iclass 36, count 2 2006.173.18:29:55.37#ibcon#wrote, iclass 36, count 2 2006.173.18:29:55.37#ibcon#about to read 3, iclass 36, count 2 2006.173.18:29:55.40#ibcon#read 3, iclass 36, count 2 2006.173.18:29:55.40#ibcon#about to read 4, iclass 36, count 2 2006.173.18:29:55.40#ibcon#read 4, iclass 36, count 2 2006.173.18:29:55.40#ibcon#about to read 5, iclass 36, count 2 2006.173.18:29:55.40#ibcon#read 5, iclass 36, count 2 2006.173.18:29:55.40#ibcon#about to read 6, iclass 36, count 2 2006.173.18:29:55.40#ibcon#read 6, iclass 36, count 2 2006.173.18:29:55.40#ibcon#end of sib2, iclass 36, count 2 2006.173.18:29:55.40#ibcon#*after write, iclass 36, count 2 2006.173.18:29:55.40#ibcon#*before return 0, iclass 36, count 2 2006.173.18:29:55.40#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.18:29:55.40#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.18:29:55.40#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.18:29:55.40#ibcon#ireg 7 cls_cnt 0 2006.173.18:29:55.40#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.18:29:55.52#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.18:29:55.52#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.18:29:55.52#ibcon#enter wrdev, iclass 36, count 0 2006.173.18:29:55.52#ibcon#first serial, iclass 36, count 0 2006.173.18:29:55.52#ibcon#enter sib2, iclass 36, count 0 2006.173.18:29:55.52#ibcon#flushed, iclass 36, count 0 2006.173.18:29:55.52#ibcon#about to write, iclass 36, count 0 2006.173.18:29:55.52#ibcon#wrote, iclass 36, count 0 2006.173.18:29:55.52#ibcon#about to read 3, iclass 36, count 0 2006.173.18:29:55.54#ibcon#read 3, iclass 36, count 0 2006.173.18:29:55.54#ibcon#about to read 4, iclass 36, count 0 2006.173.18:29:55.54#ibcon#read 4, iclass 36, count 0 2006.173.18:29:55.54#ibcon#about to read 5, iclass 36, count 0 2006.173.18:29:55.54#ibcon#read 5, iclass 36, count 0 2006.173.18:29:55.54#ibcon#about to read 6, iclass 36, count 0 2006.173.18:29:55.54#ibcon#read 6, iclass 36, count 0 2006.173.18:29:55.54#ibcon#end of sib2, iclass 36, count 0 2006.173.18:29:55.54#ibcon#*mode == 0, iclass 36, count 0 2006.173.18:29:55.54#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.18:29:55.54#ibcon#[27=USB\r\n] 2006.173.18:29:55.54#ibcon#*before write, iclass 36, count 0 2006.173.18:29:55.54#ibcon#enter sib2, iclass 36, count 0 2006.173.18:29:55.54#ibcon#flushed, iclass 36, count 0 2006.173.18:29:55.54#ibcon#about to write, iclass 36, count 0 2006.173.18:29:55.54#ibcon#wrote, iclass 36, count 0 2006.173.18:29:55.54#ibcon#about to read 3, iclass 36, count 0 2006.173.18:29:55.57#ibcon#read 3, iclass 36, count 0 2006.173.18:29:55.57#ibcon#about to read 4, iclass 36, count 0 2006.173.18:29:55.57#ibcon#read 4, iclass 36, count 0 2006.173.18:29:55.57#ibcon#about to read 5, iclass 36, count 0 2006.173.18:29:55.57#ibcon#read 5, iclass 36, count 0 2006.173.18:29:55.57#ibcon#about to read 6, iclass 36, count 0 2006.173.18:29:55.57#ibcon#read 6, iclass 36, count 0 2006.173.18:29:55.57#ibcon#end of sib2, iclass 36, count 0 2006.173.18:29:55.57#ibcon#*after write, iclass 36, count 0 2006.173.18:29:55.57#ibcon#*before return 0, iclass 36, count 0 2006.173.18:29:55.57#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.18:29:55.57#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.18:29:55.57#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.18:29:55.57#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.18:29:55.57$vck44/vblo=5,709.99 2006.173.18:29:55.57#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.18:29:55.57#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.18:29:55.57#ibcon#ireg 17 cls_cnt 0 2006.173.18:29:55.57#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.18:29:55.57#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.18:29:55.57#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.18:29:55.57#ibcon#enter wrdev, iclass 38, count 0 2006.173.18:29:55.57#ibcon#first serial, iclass 38, count 0 2006.173.18:29:55.57#ibcon#enter sib2, iclass 38, count 0 2006.173.18:29:55.57#ibcon#flushed, iclass 38, count 0 2006.173.18:29:55.57#ibcon#about to write, iclass 38, count 0 2006.173.18:29:55.57#ibcon#wrote, iclass 38, count 0 2006.173.18:29:55.57#ibcon#about to read 3, iclass 38, count 0 2006.173.18:29:55.59#ibcon#read 3, iclass 38, count 0 2006.173.18:29:55.59#ibcon#about to read 4, iclass 38, count 0 2006.173.18:29:55.59#ibcon#read 4, iclass 38, count 0 2006.173.18:29:55.59#ibcon#about to read 5, iclass 38, count 0 2006.173.18:29:55.59#ibcon#read 5, iclass 38, count 0 2006.173.18:29:55.59#ibcon#about to read 6, iclass 38, count 0 2006.173.18:29:55.59#ibcon#read 6, iclass 38, count 0 2006.173.18:29:55.59#ibcon#end of sib2, iclass 38, count 0 2006.173.18:29:55.59#ibcon#*mode == 0, iclass 38, count 0 2006.173.18:29:55.59#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.18:29:55.59#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.18:29:55.59#ibcon#*before write, iclass 38, count 0 2006.173.18:29:55.59#ibcon#enter sib2, iclass 38, count 0 2006.173.18:29:55.59#ibcon#flushed, iclass 38, count 0 2006.173.18:29:55.59#ibcon#about to write, iclass 38, count 0 2006.173.18:29:55.59#ibcon#wrote, iclass 38, count 0 2006.173.18:29:55.59#ibcon#about to read 3, iclass 38, count 0 2006.173.18:29:55.63#ibcon#read 3, iclass 38, count 0 2006.173.18:29:55.63#ibcon#about to read 4, iclass 38, count 0 2006.173.18:29:55.63#ibcon#read 4, iclass 38, count 0 2006.173.18:29:55.63#ibcon#about to read 5, iclass 38, count 0 2006.173.18:29:55.63#ibcon#read 5, iclass 38, count 0 2006.173.18:29:55.63#ibcon#about to read 6, iclass 38, count 0 2006.173.18:29:55.63#ibcon#read 6, iclass 38, count 0 2006.173.18:29:55.63#ibcon#end of sib2, iclass 38, count 0 2006.173.18:29:55.63#ibcon#*after write, iclass 38, count 0 2006.173.18:29:55.63#ibcon#*before return 0, iclass 38, count 0 2006.173.18:29:55.63#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.18:29:55.63#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.18:29:55.63#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.18:29:55.63#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.18:29:55.63$vck44/vb=5,4 2006.173.18:29:55.63#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.18:29:55.63#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.18:29:55.63#ibcon#ireg 11 cls_cnt 2 2006.173.18:29:55.63#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.18:29:55.69#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.18:29:55.69#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.18:29:55.69#ibcon#enter wrdev, iclass 40, count 2 2006.173.18:29:55.69#ibcon#first serial, iclass 40, count 2 2006.173.18:29:55.69#ibcon#enter sib2, iclass 40, count 2 2006.173.18:29:55.69#ibcon#flushed, iclass 40, count 2 2006.173.18:29:55.69#ibcon#about to write, iclass 40, count 2 2006.173.18:29:55.69#ibcon#wrote, iclass 40, count 2 2006.173.18:29:55.69#ibcon#about to read 3, iclass 40, count 2 2006.173.18:29:55.71#ibcon#read 3, iclass 40, count 2 2006.173.18:29:55.71#ibcon#about to read 4, iclass 40, count 2 2006.173.18:29:55.71#ibcon#read 4, iclass 40, count 2 2006.173.18:29:55.71#ibcon#about to read 5, iclass 40, count 2 2006.173.18:29:55.71#ibcon#read 5, iclass 40, count 2 2006.173.18:29:55.71#ibcon#about to read 6, iclass 40, count 2 2006.173.18:29:55.71#ibcon#read 6, iclass 40, count 2 2006.173.18:29:55.71#ibcon#end of sib2, iclass 40, count 2 2006.173.18:29:55.71#ibcon#*mode == 0, iclass 40, count 2 2006.173.18:29:55.71#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.18:29:55.71#ibcon#[27=AT05-04\r\n] 2006.173.18:29:55.71#ibcon#*before write, iclass 40, count 2 2006.173.18:29:55.71#ibcon#enter sib2, iclass 40, count 2 2006.173.18:29:55.71#ibcon#flushed, iclass 40, count 2 2006.173.18:29:55.71#ibcon#about to write, iclass 40, count 2 2006.173.18:29:55.71#ibcon#wrote, iclass 40, count 2 2006.173.18:29:55.71#ibcon#about to read 3, iclass 40, count 2 2006.173.18:29:55.74#ibcon#read 3, iclass 40, count 2 2006.173.18:29:55.74#ibcon#about to read 4, iclass 40, count 2 2006.173.18:29:55.74#ibcon#read 4, iclass 40, count 2 2006.173.18:29:55.74#ibcon#about to read 5, iclass 40, count 2 2006.173.18:29:55.74#ibcon#read 5, iclass 40, count 2 2006.173.18:29:55.74#ibcon#about to read 6, iclass 40, count 2 2006.173.18:29:55.74#ibcon#read 6, iclass 40, count 2 2006.173.18:29:55.74#ibcon#end of sib2, iclass 40, count 2 2006.173.18:29:55.74#ibcon#*after write, iclass 40, count 2 2006.173.18:29:55.74#ibcon#*before return 0, iclass 40, count 2 2006.173.18:29:55.74#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.18:29:55.74#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.18:29:55.74#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.18:29:55.74#ibcon#ireg 7 cls_cnt 0 2006.173.18:29:55.74#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.18:29:55.86#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.18:29:55.86#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.18:29:55.86#ibcon#enter wrdev, iclass 40, count 0 2006.173.18:29:55.86#ibcon#first serial, iclass 40, count 0 2006.173.18:29:55.86#ibcon#enter sib2, iclass 40, count 0 2006.173.18:29:55.86#ibcon#flushed, iclass 40, count 0 2006.173.18:29:55.86#ibcon#about to write, iclass 40, count 0 2006.173.18:29:55.86#ibcon#wrote, iclass 40, count 0 2006.173.18:29:55.86#ibcon#about to read 3, iclass 40, count 0 2006.173.18:29:55.88#ibcon#read 3, iclass 40, count 0 2006.173.18:29:55.88#ibcon#about to read 4, iclass 40, count 0 2006.173.18:29:55.88#ibcon#read 4, iclass 40, count 0 2006.173.18:29:55.88#ibcon#about to read 5, iclass 40, count 0 2006.173.18:29:55.88#ibcon#read 5, iclass 40, count 0 2006.173.18:29:55.88#ibcon#about to read 6, iclass 40, count 0 2006.173.18:29:55.88#ibcon#read 6, iclass 40, count 0 2006.173.18:29:55.88#ibcon#end of sib2, iclass 40, count 0 2006.173.18:29:55.88#ibcon#*mode == 0, iclass 40, count 0 2006.173.18:29:55.88#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.18:29:55.88#ibcon#[27=USB\r\n] 2006.173.18:29:55.88#ibcon#*before write, iclass 40, count 0 2006.173.18:29:55.88#ibcon#enter sib2, iclass 40, count 0 2006.173.18:29:55.88#ibcon#flushed, iclass 40, count 0 2006.173.18:29:55.88#ibcon#about to write, iclass 40, count 0 2006.173.18:29:55.88#ibcon#wrote, iclass 40, count 0 2006.173.18:29:55.88#ibcon#about to read 3, iclass 40, count 0 2006.173.18:29:55.91#ibcon#read 3, iclass 40, count 0 2006.173.18:29:55.91#ibcon#about to read 4, iclass 40, count 0 2006.173.18:29:55.91#ibcon#read 4, iclass 40, count 0 2006.173.18:29:55.91#ibcon#about to read 5, iclass 40, count 0 2006.173.18:29:55.91#ibcon#read 5, iclass 40, count 0 2006.173.18:29:55.91#ibcon#about to read 6, iclass 40, count 0 2006.173.18:29:55.91#ibcon#read 6, iclass 40, count 0 2006.173.18:29:55.91#ibcon#end of sib2, iclass 40, count 0 2006.173.18:29:55.91#ibcon#*after write, iclass 40, count 0 2006.173.18:29:55.91#ibcon#*before return 0, iclass 40, count 0 2006.173.18:29:55.91#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.18:29:55.91#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.18:29:55.91#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.18:29:55.91#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.18:29:55.91$vck44/vblo=6,719.99 2006.173.18:29:55.91#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.18:29:55.91#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.18:29:55.91#ibcon#ireg 17 cls_cnt 0 2006.173.18:29:55.91#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.18:29:55.91#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.18:29:55.91#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.18:29:55.91#ibcon#enter wrdev, iclass 4, count 0 2006.173.18:29:55.91#ibcon#first serial, iclass 4, count 0 2006.173.18:29:55.91#ibcon#enter sib2, iclass 4, count 0 2006.173.18:29:55.91#ibcon#flushed, iclass 4, count 0 2006.173.18:29:55.91#ibcon#about to write, iclass 4, count 0 2006.173.18:29:55.91#ibcon#wrote, iclass 4, count 0 2006.173.18:29:55.91#ibcon#about to read 3, iclass 4, count 0 2006.173.18:29:55.93#ibcon#read 3, iclass 4, count 0 2006.173.18:29:55.93#ibcon#about to read 4, iclass 4, count 0 2006.173.18:29:55.93#ibcon#read 4, iclass 4, count 0 2006.173.18:29:55.93#ibcon#about to read 5, iclass 4, count 0 2006.173.18:29:55.93#ibcon#read 5, iclass 4, count 0 2006.173.18:29:55.93#ibcon#about to read 6, iclass 4, count 0 2006.173.18:29:55.93#ibcon#read 6, iclass 4, count 0 2006.173.18:29:55.93#ibcon#end of sib2, iclass 4, count 0 2006.173.18:29:55.93#ibcon#*mode == 0, iclass 4, count 0 2006.173.18:29:55.93#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.18:29:55.93#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.18:29:55.93#ibcon#*before write, iclass 4, count 0 2006.173.18:29:55.93#ibcon#enter sib2, iclass 4, count 0 2006.173.18:29:55.93#ibcon#flushed, iclass 4, count 0 2006.173.18:29:55.93#ibcon#about to write, iclass 4, count 0 2006.173.18:29:55.93#ibcon#wrote, iclass 4, count 0 2006.173.18:29:55.93#ibcon#about to read 3, iclass 4, count 0 2006.173.18:29:55.97#ibcon#read 3, iclass 4, count 0 2006.173.18:29:55.97#ibcon#about to read 4, iclass 4, count 0 2006.173.18:29:55.97#ibcon#read 4, iclass 4, count 0 2006.173.18:29:55.97#ibcon#about to read 5, iclass 4, count 0 2006.173.18:29:55.97#ibcon#read 5, iclass 4, count 0 2006.173.18:29:55.97#ibcon#about to read 6, iclass 4, count 0 2006.173.18:29:55.97#ibcon#read 6, iclass 4, count 0 2006.173.18:29:55.97#ibcon#end of sib2, iclass 4, count 0 2006.173.18:29:55.97#ibcon#*after write, iclass 4, count 0 2006.173.18:29:55.97#ibcon#*before return 0, iclass 4, count 0 2006.173.18:29:55.97#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.18:29:55.97#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.18:29:55.97#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.18:29:55.97#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.18:29:55.97$vck44/vb=6,4 2006.173.18:29:55.97#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.18:29:55.97#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.18:29:55.97#ibcon#ireg 11 cls_cnt 2 2006.173.18:29:55.97#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.18:29:56.03#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.18:29:56.03#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.18:29:56.03#ibcon#enter wrdev, iclass 6, count 2 2006.173.18:29:56.03#ibcon#first serial, iclass 6, count 2 2006.173.18:29:56.03#ibcon#enter sib2, iclass 6, count 2 2006.173.18:29:56.03#ibcon#flushed, iclass 6, count 2 2006.173.18:29:56.03#ibcon#about to write, iclass 6, count 2 2006.173.18:29:56.03#ibcon#wrote, iclass 6, count 2 2006.173.18:29:56.03#ibcon#about to read 3, iclass 6, count 2 2006.173.18:29:56.05#ibcon#read 3, iclass 6, count 2 2006.173.18:29:56.05#ibcon#about to read 4, iclass 6, count 2 2006.173.18:29:56.05#ibcon#read 4, iclass 6, count 2 2006.173.18:29:56.05#ibcon#about to read 5, iclass 6, count 2 2006.173.18:29:56.05#ibcon#read 5, iclass 6, count 2 2006.173.18:29:56.05#ibcon#about to read 6, iclass 6, count 2 2006.173.18:29:56.05#ibcon#read 6, iclass 6, count 2 2006.173.18:29:56.05#ibcon#end of sib2, iclass 6, count 2 2006.173.18:29:56.05#ibcon#*mode == 0, iclass 6, count 2 2006.173.18:29:56.05#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.18:29:56.05#ibcon#[27=AT06-04\r\n] 2006.173.18:29:56.05#ibcon#*before write, iclass 6, count 2 2006.173.18:29:56.05#ibcon#enter sib2, iclass 6, count 2 2006.173.18:29:56.05#ibcon#flushed, iclass 6, count 2 2006.173.18:29:56.05#ibcon#about to write, iclass 6, count 2 2006.173.18:29:56.05#ibcon#wrote, iclass 6, count 2 2006.173.18:29:56.05#ibcon#about to read 3, iclass 6, count 2 2006.173.18:29:56.08#ibcon#read 3, iclass 6, count 2 2006.173.18:29:56.08#ibcon#about to read 4, iclass 6, count 2 2006.173.18:29:56.08#ibcon#read 4, iclass 6, count 2 2006.173.18:29:56.08#ibcon#about to read 5, iclass 6, count 2 2006.173.18:29:56.08#ibcon#read 5, iclass 6, count 2 2006.173.18:29:56.08#ibcon#about to read 6, iclass 6, count 2 2006.173.18:29:56.08#ibcon#read 6, iclass 6, count 2 2006.173.18:29:56.08#ibcon#end of sib2, iclass 6, count 2 2006.173.18:29:56.08#ibcon#*after write, iclass 6, count 2 2006.173.18:29:56.08#ibcon#*before return 0, iclass 6, count 2 2006.173.18:29:56.08#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.18:29:56.08#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.18:29:56.08#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.18:29:56.08#ibcon#ireg 7 cls_cnt 0 2006.173.18:29:56.08#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.18:29:56.20#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.18:29:56.20#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.18:29:56.20#ibcon#enter wrdev, iclass 6, count 0 2006.173.18:29:56.20#ibcon#first serial, iclass 6, count 0 2006.173.18:29:56.20#ibcon#enter sib2, iclass 6, count 0 2006.173.18:29:56.20#ibcon#flushed, iclass 6, count 0 2006.173.18:29:56.20#ibcon#about to write, iclass 6, count 0 2006.173.18:29:56.20#ibcon#wrote, iclass 6, count 0 2006.173.18:29:56.20#ibcon#about to read 3, iclass 6, count 0 2006.173.18:29:56.22#ibcon#read 3, iclass 6, count 0 2006.173.18:29:56.22#ibcon#about to read 4, iclass 6, count 0 2006.173.18:29:56.22#ibcon#read 4, iclass 6, count 0 2006.173.18:29:56.22#ibcon#about to read 5, iclass 6, count 0 2006.173.18:29:56.22#ibcon#read 5, iclass 6, count 0 2006.173.18:29:56.22#ibcon#about to read 6, iclass 6, count 0 2006.173.18:29:56.22#ibcon#read 6, iclass 6, count 0 2006.173.18:29:56.22#ibcon#end of sib2, iclass 6, count 0 2006.173.18:29:56.22#ibcon#*mode == 0, iclass 6, count 0 2006.173.18:29:56.22#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.18:29:56.22#ibcon#[27=USB\r\n] 2006.173.18:29:56.22#ibcon#*before write, iclass 6, count 0 2006.173.18:29:56.22#ibcon#enter sib2, iclass 6, count 0 2006.173.18:29:56.22#ibcon#flushed, iclass 6, count 0 2006.173.18:29:56.22#ibcon#about to write, iclass 6, count 0 2006.173.18:29:56.22#ibcon#wrote, iclass 6, count 0 2006.173.18:29:56.22#ibcon#about to read 3, iclass 6, count 0 2006.173.18:29:56.25#ibcon#read 3, iclass 6, count 0 2006.173.18:29:56.25#ibcon#about to read 4, iclass 6, count 0 2006.173.18:29:56.25#ibcon#read 4, iclass 6, count 0 2006.173.18:29:56.25#ibcon#about to read 5, iclass 6, count 0 2006.173.18:29:56.25#ibcon#read 5, iclass 6, count 0 2006.173.18:29:56.25#ibcon#about to read 6, iclass 6, count 0 2006.173.18:29:56.25#ibcon#read 6, iclass 6, count 0 2006.173.18:29:56.25#ibcon#end of sib2, iclass 6, count 0 2006.173.18:29:56.25#ibcon#*after write, iclass 6, count 0 2006.173.18:29:56.25#ibcon#*before return 0, iclass 6, count 0 2006.173.18:29:56.25#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.18:29:56.25#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.18:29:56.25#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.18:29:56.25#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.18:29:56.25$vck44/vblo=7,734.99 2006.173.18:29:56.25#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.18:29:56.25#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.18:29:56.25#ibcon#ireg 17 cls_cnt 0 2006.173.18:29:56.25#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.18:29:56.25#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.18:29:56.25#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.18:29:56.25#ibcon#enter wrdev, iclass 10, count 0 2006.173.18:29:56.25#ibcon#first serial, iclass 10, count 0 2006.173.18:29:56.25#ibcon#enter sib2, iclass 10, count 0 2006.173.18:29:56.25#ibcon#flushed, iclass 10, count 0 2006.173.18:29:56.25#ibcon#about to write, iclass 10, count 0 2006.173.18:29:56.25#ibcon#wrote, iclass 10, count 0 2006.173.18:29:56.25#ibcon#about to read 3, iclass 10, count 0 2006.173.18:29:56.27#ibcon#read 3, iclass 10, count 0 2006.173.18:29:56.27#ibcon#about to read 4, iclass 10, count 0 2006.173.18:29:56.27#ibcon#read 4, iclass 10, count 0 2006.173.18:29:56.27#ibcon#about to read 5, iclass 10, count 0 2006.173.18:29:56.27#ibcon#read 5, iclass 10, count 0 2006.173.18:29:56.27#ibcon#about to read 6, iclass 10, count 0 2006.173.18:29:56.27#ibcon#read 6, iclass 10, count 0 2006.173.18:29:56.27#ibcon#end of sib2, iclass 10, count 0 2006.173.18:29:56.27#ibcon#*mode == 0, iclass 10, count 0 2006.173.18:29:56.27#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.18:29:56.27#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.18:29:56.27#ibcon#*before write, iclass 10, count 0 2006.173.18:29:56.27#ibcon#enter sib2, iclass 10, count 0 2006.173.18:29:56.27#ibcon#flushed, iclass 10, count 0 2006.173.18:29:56.27#ibcon#about to write, iclass 10, count 0 2006.173.18:29:56.27#ibcon#wrote, iclass 10, count 0 2006.173.18:29:56.27#ibcon#about to read 3, iclass 10, count 0 2006.173.18:29:56.31#ibcon#read 3, iclass 10, count 0 2006.173.18:29:56.31#ibcon#about to read 4, iclass 10, count 0 2006.173.18:29:56.31#ibcon#read 4, iclass 10, count 0 2006.173.18:29:56.31#ibcon#about to read 5, iclass 10, count 0 2006.173.18:29:56.31#ibcon#read 5, iclass 10, count 0 2006.173.18:29:56.31#ibcon#about to read 6, iclass 10, count 0 2006.173.18:29:56.31#ibcon#read 6, iclass 10, count 0 2006.173.18:29:56.31#ibcon#end of sib2, iclass 10, count 0 2006.173.18:29:56.31#ibcon#*after write, iclass 10, count 0 2006.173.18:29:56.31#ibcon#*before return 0, iclass 10, count 0 2006.173.18:29:56.31#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.18:29:56.31#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.18:29:56.31#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.18:29:56.31#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.18:29:56.31$vck44/vb=7,4 2006.173.18:29:56.31#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.18:29:56.31#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.18:29:56.31#ibcon#ireg 11 cls_cnt 2 2006.173.18:29:56.31#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.18:29:56.37#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.18:29:56.37#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.18:29:56.37#ibcon#enter wrdev, iclass 12, count 2 2006.173.18:29:56.37#ibcon#first serial, iclass 12, count 2 2006.173.18:29:56.37#ibcon#enter sib2, iclass 12, count 2 2006.173.18:29:56.37#ibcon#flushed, iclass 12, count 2 2006.173.18:29:56.37#ibcon#about to write, iclass 12, count 2 2006.173.18:29:56.37#ibcon#wrote, iclass 12, count 2 2006.173.18:29:56.37#ibcon#about to read 3, iclass 12, count 2 2006.173.18:29:56.39#ibcon#read 3, iclass 12, count 2 2006.173.18:29:56.39#ibcon#about to read 4, iclass 12, count 2 2006.173.18:29:56.39#ibcon#read 4, iclass 12, count 2 2006.173.18:29:56.39#ibcon#about to read 5, iclass 12, count 2 2006.173.18:29:56.39#ibcon#read 5, iclass 12, count 2 2006.173.18:29:56.39#ibcon#about to read 6, iclass 12, count 2 2006.173.18:29:56.39#ibcon#read 6, iclass 12, count 2 2006.173.18:29:56.39#ibcon#end of sib2, iclass 12, count 2 2006.173.18:29:56.39#ibcon#*mode == 0, iclass 12, count 2 2006.173.18:29:56.39#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.18:29:56.39#ibcon#[27=AT07-04\r\n] 2006.173.18:29:56.39#ibcon#*before write, iclass 12, count 2 2006.173.18:29:56.39#ibcon#enter sib2, iclass 12, count 2 2006.173.18:29:56.39#ibcon#flushed, iclass 12, count 2 2006.173.18:29:56.39#ibcon#about to write, iclass 12, count 2 2006.173.18:29:56.39#ibcon#wrote, iclass 12, count 2 2006.173.18:29:56.39#ibcon#about to read 3, iclass 12, count 2 2006.173.18:29:56.42#ibcon#read 3, iclass 12, count 2 2006.173.18:29:56.42#ibcon#about to read 4, iclass 12, count 2 2006.173.18:29:56.42#ibcon#read 4, iclass 12, count 2 2006.173.18:29:56.42#ibcon#about to read 5, iclass 12, count 2 2006.173.18:29:56.42#ibcon#read 5, iclass 12, count 2 2006.173.18:29:56.42#ibcon#about to read 6, iclass 12, count 2 2006.173.18:29:56.42#ibcon#read 6, iclass 12, count 2 2006.173.18:29:56.42#ibcon#end of sib2, iclass 12, count 2 2006.173.18:29:56.42#ibcon#*after write, iclass 12, count 2 2006.173.18:29:56.42#ibcon#*before return 0, iclass 12, count 2 2006.173.18:29:56.42#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.18:29:56.42#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.18:29:56.42#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.18:29:56.42#ibcon#ireg 7 cls_cnt 0 2006.173.18:29:56.42#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.18:29:56.54#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.18:29:56.54#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.18:29:56.54#ibcon#enter wrdev, iclass 12, count 0 2006.173.18:29:56.54#ibcon#first serial, iclass 12, count 0 2006.173.18:29:56.54#ibcon#enter sib2, iclass 12, count 0 2006.173.18:29:56.54#ibcon#flushed, iclass 12, count 0 2006.173.18:29:56.54#ibcon#about to write, iclass 12, count 0 2006.173.18:29:56.54#ibcon#wrote, iclass 12, count 0 2006.173.18:29:56.54#ibcon#about to read 3, iclass 12, count 0 2006.173.18:29:56.56#ibcon#read 3, iclass 12, count 0 2006.173.18:29:56.56#ibcon#about to read 4, iclass 12, count 0 2006.173.18:29:56.56#ibcon#read 4, iclass 12, count 0 2006.173.18:29:56.56#ibcon#about to read 5, iclass 12, count 0 2006.173.18:29:56.56#ibcon#read 5, iclass 12, count 0 2006.173.18:29:56.56#ibcon#about to read 6, iclass 12, count 0 2006.173.18:29:56.56#ibcon#read 6, iclass 12, count 0 2006.173.18:29:56.56#ibcon#end of sib2, iclass 12, count 0 2006.173.18:29:56.56#ibcon#*mode == 0, iclass 12, count 0 2006.173.18:29:56.56#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.18:29:56.56#ibcon#[27=USB\r\n] 2006.173.18:29:56.56#ibcon#*before write, iclass 12, count 0 2006.173.18:29:56.56#ibcon#enter sib2, iclass 12, count 0 2006.173.18:29:56.56#ibcon#flushed, iclass 12, count 0 2006.173.18:29:56.56#ibcon#about to write, iclass 12, count 0 2006.173.18:29:56.56#ibcon#wrote, iclass 12, count 0 2006.173.18:29:56.56#ibcon#about to read 3, iclass 12, count 0 2006.173.18:29:56.59#ibcon#read 3, iclass 12, count 0 2006.173.18:29:56.59#ibcon#about to read 4, iclass 12, count 0 2006.173.18:29:56.59#ibcon#read 4, iclass 12, count 0 2006.173.18:29:56.59#ibcon#about to read 5, iclass 12, count 0 2006.173.18:29:56.59#ibcon#read 5, iclass 12, count 0 2006.173.18:29:56.59#ibcon#about to read 6, iclass 12, count 0 2006.173.18:29:56.59#ibcon#read 6, iclass 12, count 0 2006.173.18:29:56.59#ibcon#end of sib2, iclass 12, count 0 2006.173.18:29:56.59#ibcon#*after write, iclass 12, count 0 2006.173.18:29:56.59#ibcon#*before return 0, iclass 12, count 0 2006.173.18:29:56.59#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.18:29:56.59#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.18:29:56.59#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.18:29:56.59#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.18:29:56.59$vck44/vblo=8,744.99 2006.173.18:29:56.59#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.18:29:56.59#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.18:29:56.59#ibcon#ireg 17 cls_cnt 0 2006.173.18:29:56.59#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.18:29:56.59#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.18:29:56.59#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.18:29:56.59#ibcon#enter wrdev, iclass 14, count 0 2006.173.18:29:56.59#ibcon#first serial, iclass 14, count 0 2006.173.18:29:56.59#ibcon#enter sib2, iclass 14, count 0 2006.173.18:29:56.59#ibcon#flushed, iclass 14, count 0 2006.173.18:29:56.59#ibcon#about to write, iclass 14, count 0 2006.173.18:29:56.59#ibcon#wrote, iclass 14, count 0 2006.173.18:29:56.59#ibcon#about to read 3, iclass 14, count 0 2006.173.18:29:56.61#ibcon#read 3, iclass 14, count 0 2006.173.18:29:56.61#ibcon#about to read 4, iclass 14, count 0 2006.173.18:29:56.61#ibcon#read 4, iclass 14, count 0 2006.173.18:29:56.61#ibcon#about to read 5, iclass 14, count 0 2006.173.18:29:56.61#ibcon#read 5, iclass 14, count 0 2006.173.18:29:56.61#ibcon#about to read 6, iclass 14, count 0 2006.173.18:29:56.61#ibcon#read 6, iclass 14, count 0 2006.173.18:29:56.61#ibcon#end of sib2, iclass 14, count 0 2006.173.18:29:56.61#ibcon#*mode == 0, iclass 14, count 0 2006.173.18:29:56.61#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.18:29:56.61#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.18:29:56.61#ibcon#*before write, iclass 14, count 0 2006.173.18:29:56.61#ibcon#enter sib2, iclass 14, count 0 2006.173.18:29:56.61#ibcon#flushed, iclass 14, count 0 2006.173.18:29:56.61#ibcon#about to write, iclass 14, count 0 2006.173.18:29:56.61#ibcon#wrote, iclass 14, count 0 2006.173.18:29:56.61#ibcon#about to read 3, iclass 14, count 0 2006.173.18:29:56.65#ibcon#read 3, iclass 14, count 0 2006.173.18:29:56.65#ibcon#about to read 4, iclass 14, count 0 2006.173.18:29:56.65#ibcon#read 4, iclass 14, count 0 2006.173.18:29:56.65#ibcon#about to read 5, iclass 14, count 0 2006.173.18:29:56.65#ibcon#read 5, iclass 14, count 0 2006.173.18:29:56.65#ibcon#about to read 6, iclass 14, count 0 2006.173.18:29:56.65#ibcon#read 6, iclass 14, count 0 2006.173.18:29:56.65#ibcon#end of sib2, iclass 14, count 0 2006.173.18:29:56.65#ibcon#*after write, iclass 14, count 0 2006.173.18:29:56.65#ibcon#*before return 0, iclass 14, count 0 2006.173.18:29:56.65#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.18:29:56.65#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.18:29:56.65#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.18:29:56.65#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.18:29:56.65$vck44/vb=8,4 2006.173.18:29:56.65#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.18:29:56.65#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.18:29:56.65#ibcon#ireg 11 cls_cnt 2 2006.173.18:29:56.65#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.18:29:56.71#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.18:29:56.71#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.18:29:56.71#ibcon#enter wrdev, iclass 16, count 2 2006.173.18:29:56.71#ibcon#first serial, iclass 16, count 2 2006.173.18:29:56.71#ibcon#enter sib2, iclass 16, count 2 2006.173.18:29:56.71#ibcon#flushed, iclass 16, count 2 2006.173.18:29:56.71#ibcon#about to write, iclass 16, count 2 2006.173.18:29:56.71#ibcon#wrote, iclass 16, count 2 2006.173.18:29:56.71#ibcon#about to read 3, iclass 16, count 2 2006.173.18:29:56.73#ibcon#read 3, iclass 16, count 2 2006.173.18:29:56.73#ibcon#about to read 4, iclass 16, count 2 2006.173.18:29:56.73#ibcon#read 4, iclass 16, count 2 2006.173.18:29:56.73#ibcon#about to read 5, iclass 16, count 2 2006.173.18:29:56.73#ibcon#read 5, iclass 16, count 2 2006.173.18:29:56.73#ibcon#about to read 6, iclass 16, count 2 2006.173.18:29:56.73#ibcon#read 6, iclass 16, count 2 2006.173.18:29:56.73#ibcon#end of sib2, iclass 16, count 2 2006.173.18:29:56.73#ibcon#*mode == 0, iclass 16, count 2 2006.173.18:29:56.73#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.18:29:56.73#ibcon#[27=AT08-04\r\n] 2006.173.18:29:56.73#ibcon#*before write, iclass 16, count 2 2006.173.18:29:56.73#ibcon#enter sib2, iclass 16, count 2 2006.173.18:29:56.73#ibcon#flushed, iclass 16, count 2 2006.173.18:29:56.73#ibcon#about to write, iclass 16, count 2 2006.173.18:29:56.73#ibcon#wrote, iclass 16, count 2 2006.173.18:29:56.73#ibcon#about to read 3, iclass 16, count 2 2006.173.18:29:56.76#abcon#<5=/14 1.1 2.3 19.901001002.3\r\n> 2006.173.18:29:56.76#ibcon#read 3, iclass 16, count 2 2006.173.18:29:56.76#ibcon#about to read 4, iclass 16, count 2 2006.173.18:29:56.76#ibcon#read 4, iclass 16, count 2 2006.173.18:29:56.76#ibcon#about to read 5, iclass 16, count 2 2006.173.18:29:56.76#ibcon#read 5, iclass 16, count 2 2006.173.18:29:56.76#ibcon#about to read 6, iclass 16, count 2 2006.173.18:29:56.76#ibcon#read 6, iclass 16, count 2 2006.173.18:29:56.76#ibcon#end of sib2, iclass 16, count 2 2006.173.18:29:56.76#ibcon#*after write, iclass 16, count 2 2006.173.18:29:56.76#ibcon#*before return 0, iclass 16, count 2 2006.173.18:29:56.76#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.18:29:56.76#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.18:29:56.76#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.18:29:56.76#ibcon#ireg 7 cls_cnt 0 2006.173.18:29:56.76#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.18:29:56.78#abcon#{5=INTERFACE CLEAR} 2006.173.18:29:56.84#abcon#[5=S1D000X0/0*\r\n] 2006.173.18:29:56.88#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.18:29:56.88#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.18:29:56.88#ibcon#enter wrdev, iclass 16, count 0 2006.173.18:29:56.88#ibcon#first serial, iclass 16, count 0 2006.173.18:29:56.88#ibcon#enter sib2, iclass 16, count 0 2006.173.18:29:56.88#ibcon#flushed, iclass 16, count 0 2006.173.18:29:56.88#ibcon#about to write, iclass 16, count 0 2006.173.18:29:56.88#ibcon#wrote, iclass 16, count 0 2006.173.18:29:56.88#ibcon#about to read 3, iclass 16, count 0 2006.173.18:29:56.90#ibcon#read 3, iclass 16, count 0 2006.173.18:29:56.90#ibcon#about to read 4, iclass 16, count 0 2006.173.18:29:56.90#ibcon#read 4, iclass 16, count 0 2006.173.18:29:56.90#ibcon#about to read 5, iclass 16, count 0 2006.173.18:29:56.90#ibcon#read 5, iclass 16, count 0 2006.173.18:29:56.90#ibcon#about to read 6, iclass 16, count 0 2006.173.18:29:56.90#ibcon#read 6, iclass 16, count 0 2006.173.18:29:56.90#ibcon#end of sib2, iclass 16, count 0 2006.173.18:29:56.90#ibcon#*mode == 0, iclass 16, count 0 2006.173.18:29:56.90#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.18:29:56.90#ibcon#[27=USB\r\n] 2006.173.18:29:56.90#ibcon#*before write, iclass 16, count 0 2006.173.18:29:56.90#ibcon#enter sib2, iclass 16, count 0 2006.173.18:29:56.90#ibcon#flushed, iclass 16, count 0 2006.173.18:29:56.90#ibcon#about to write, iclass 16, count 0 2006.173.18:29:56.90#ibcon#wrote, iclass 16, count 0 2006.173.18:29:56.90#ibcon#about to read 3, iclass 16, count 0 2006.173.18:29:56.93#ibcon#read 3, iclass 16, count 0 2006.173.18:29:56.93#ibcon#about to read 4, iclass 16, count 0 2006.173.18:29:56.93#ibcon#read 4, iclass 16, count 0 2006.173.18:29:56.93#ibcon#about to read 5, iclass 16, count 0 2006.173.18:29:56.93#ibcon#read 5, iclass 16, count 0 2006.173.18:29:56.93#ibcon#about to read 6, iclass 16, count 0 2006.173.18:29:56.93#ibcon#read 6, iclass 16, count 0 2006.173.18:29:56.93#ibcon#end of sib2, iclass 16, count 0 2006.173.18:29:56.93#ibcon#*after write, iclass 16, count 0 2006.173.18:29:56.93#ibcon#*before return 0, iclass 16, count 0 2006.173.18:29:56.93#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.18:29:56.93#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.18:29:56.93#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.18:29:56.93#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.18:29:56.93$vck44/vabw=wide 2006.173.18:29:56.93#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.18:29:56.93#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.18:29:56.93#ibcon#ireg 8 cls_cnt 0 2006.173.18:29:56.93#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.18:29:56.93#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.18:29:56.93#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.18:29:56.93#ibcon#enter wrdev, iclass 22, count 0 2006.173.18:29:56.93#ibcon#first serial, iclass 22, count 0 2006.173.18:29:56.93#ibcon#enter sib2, iclass 22, count 0 2006.173.18:29:56.93#ibcon#flushed, iclass 22, count 0 2006.173.18:29:56.93#ibcon#about to write, iclass 22, count 0 2006.173.18:29:56.93#ibcon#wrote, iclass 22, count 0 2006.173.18:29:56.93#ibcon#about to read 3, iclass 22, count 0 2006.173.18:29:56.95#ibcon#read 3, iclass 22, count 0 2006.173.18:29:56.95#ibcon#about to read 4, iclass 22, count 0 2006.173.18:29:56.95#ibcon#read 4, iclass 22, count 0 2006.173.18:29:56.95#ibcon#about to read 5, iclass 22, count 0 2006.173.18:29:56.95#ibcon#read 5, iclass 22, count 0 2006.173.18:29:56.95#ibcon#about to read 6, iclass 22, count 0 2006.173.18:29:56.95#ibcon#read 6, iclass 22, count 0 2006.173.18:29:56.95#ibcon#end of sib2, iclass 22, count 0 2006.173.18:29:56.95#ibcon#*mode == 0, iclass 22, count 0 2006.173.18:29:56.95#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.18:29:56.95#ibcon#[25=BW32\r\n] 2006.173.18:29:56.95#ibcon#*before write, iclass 22, count 0 2006.173.18:29:56.95#ibcon#enter sib2, iclass 22, count 0 2006.173.18:29:56.95#ibcon#flushed, iclass 22, count 0 2006.173.18:29:56.95#ibcon#about to write, iclass 22, count 0 2006.173.18:29:56.95#ibcon#wrote, iclass 22, count 0 2006.173.18:29:56.95#ibcon#about to read 3, iclass 22, count 0 2006.173.18:29:56.98#ibcon#read 3, iclass 22, count 0 2006.173.18:29:56.98#ibcon#about to read 4, iclass 22, count 0 2006.173.18:29:56.98#ibcon#read 4, iclass 22, count 0 2006.173.18:29:56.98#ibcon#about to read 5, iclass 22, count 0 2006.173.18:29:56.98#ibcon#read 5, iclass 22, count 0 2006.173.18:29:56.98#ibcon#about to read 6, iclass 22, count 0 2006.173.18:29:56.98#ibcon#read 6, iclass 22, count 0 2006.173.18:29:56.98#ibcon#end of sib2, iclass 22, count 0 2006.173.18:29:56.98#ibcon#*after write, iclass 22, count 0 2006.173.18:29:56.98#ibcon#*before return 0, iclass 22, count 0 2006.173.18:29:56.98#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.18:29:56.98#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.18:29:56.98#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.18:29:56.98#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.18:29:56.98$vck44/vbbw=wide 2006.173.18:29:56.98#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.18:29:56.98#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.18:29:56.98#ibcon#ireg 8 cls_cnt 0 2006.173.18:29:56.98#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.18:29:57.05#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.18:29:57.05#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.18:29:57.05#ibcon#enter wrdev, iclass 24, count 0 2006.173.18:29:57.05#ibcon#first serial, iclass 24, count 0 2006.173.18:29:57.05#ibcon#enter sib2, iclass 24, count 0 2006.173.18:29:57.05#ibcon#flushed, iclass 24, count 0 2006.173.18:29:57.05#ibcon#about to write, iclass 24, count 0 2006.173.18:29:57.05#ibcon#wrote, iclass 24, count 0 2006.173.18:29:57.05#ibcon#about to read 3, iclass 24, count 0 2006.173.18:29:57.07#ibcon#read 3, iclass 24, count 0 2006.173.18:29:57.07#ibcon#about to read 4, iclass 24, count 0 2006.173.18:29:57.07#ibcon#read 4, iclass 24, count 0 2006.173.18:29:57.07#ibcon#about to read 5, iclass 24, count 0 2006.173.18:29:57.07#ibcon#read 5, iclass 24, count 0 2006.173.18:29:57.07#ibcon#about to read 6, iclass 24, count 0 2006.173.18:29:57.07#ibcon#read 6, iclass 24, count 0 2006.173.18:29:57.07#ibcon#end of sib2, iclass 24, count 0 2006.173.18:29:57.07#ibcon#*mode == 0, iclass 24, count 0 2006.173.18:29:57.07#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.18:29:57.07#ibcon#[27=BW32\r\n] 2006.173.18:29:57.07#ibcon#*before write, iclass 24, count 0 2006.173.18:29:57.07#ibcon#enter sib2, iclass 24, count 0 2006.173.18:29:57.07#ibcon#flushed, iclass 24, count 0 2006.173.18:29:57.07#ibcon#about to write, iclass 24, count 0 2006.173.18:29:57.07#ibcon#wrote, iclass 24, count 0 2006.173.18:29:57.07#ibcon#about to read 3, iclass 24, count 0 2006.173.18:29:57.10#ibcon#read 3, iclass 24, count 0 2006.173.18:29:57.10#ibcon#about to read 4, iclass 24, count 0 2006.173.18:29:57.10#ibcon#read 4, iclass 24, count 0 2006.173.18:29:57.10#ibcon#about to read 5, iclass 24, count 0 2006.173.18:29:57.10#ibcon#read 5, iclass 24, count 0 2006.173.18:29:57.10#ibcon#about to read 6, iclass 24, count 0 2006.173.18:29:57.10#ibcon#read 6, iclass 24, count 0 2006.173.18:29:57.10#ibcon#end of sib2, iclass 24, count 0 2006.173.18:29:57.10#ibcon#*after write, iclass 24, count 0 2006.173.18:29:57.10#ibcon#*before return 0, iclass 24, count 0 2006.173.18:29:57.10#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.18:29:57.10#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.18:29:57.10#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.18:29:57.10#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.18:29:57.10$setupk4/ifdk4 2006.173.18:29:57.10$ifdk4/lo= 2006.173.18:29:57.10$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.18:29:57.10$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.18:29:57.10$ifdk4/patch= 2006.173.18:29:57.10$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.18:29:57.10$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.18:29:57.10$setupk4/!*+20s 2006.173.18:30:06.93#abcon#<5=/14 1.1 2.3 19.901001002.3\r\n> 2006.173.18:30:06.95#abcon#{5=INTERFACE CLEAR} 2006.173.18:30:07.01#abcon#[5=S1D000X0/0*\r\n] 2006.173.18:30:11.60$setupk4/"tpicd 2006.173.18:30:11.60$setupk4/echo=off 2006.173.18:30:11.60$setupk4/xlog=off 2006.173.18:30:11.60:!2006.173.18:33:00 2006.173.18:30:17.13#trakl#Source acquired 2006.173.18:30:18.13#flagr#flagr/antenna,acquired 2006.173.18:33:00.00:preob 2006.173.18:33:01.14/onsource/TRACKING 2006.173.18:33:01.14:!2006.173.18:33:10 2006.173.18:33:10.00:"tape 2006.173.18:33:10.00:"st=record 2006.173.18:33:10.00:data_valid=on 2006.173.18:33:10.00:midob 2006.173.18:33:10.14/onsource/TRACKING 2006.173.18:33:10.14/wx/19.88,1002.3,100 2006.173.18:33:10.36/cable/+6.5162E-03 2006.173.18:33:11.45/va/01,07,usb,yes,37,40 2006.173.18:33:11.45/va/02,06,usb,yes,37,38 2006.173.18:33:11.45/va/03,05,usb,yes,47,49 2006.173.18:33:11.45/va/04,06,usb,yes,38,40 2006.173.18:33:11.45/va/05,04,usb,yes,30,30 2006.173.18:33:11.45/va/06,03,usb,yes,41,41 2006.173.18:33:11.45/va/07,04,usb,yes,34,35 2006.173.18:33:11.45/va/08,04,usb,yes,29,34 2006.173.18:33:11.68/valo/01,524.99,yes,locked 2006.173.18:33:11.68/valo/02,534.99,yes,locked 2006.173.18:33:11.68/valo/03,564.99,yes,locked 2006.173.18:33:11.68/valo/04,624.99,yes,locked 2006.173.18:33:11.68/valo/05,734.99,yes,locked 2006.173.18:33:11.68/valo/06,814.99,yes,locked 2006.173.18:33:11.68/valo/07,864.99,yes,locked 2006.173.18:33:11.68/valo/08,884.99,yes,locked 2006.173.18:33:12.77/vb/01,04,usb,yes,33,28 2006.173.18:33:12.77/vb/02,04,usb,yes,35,36 2006.173.18:33:12.77/vb/03,04,usb,yes,34,34 2006.173.18:33:12.77/vb/04,04,usb,yes,34,33 2006.173.18:33:12.77/vb/05,04,usb,yes,26,29 2006.173.18:33:12.77/vb/06,04,usb,yes,31,27 2006.173.18:33:12.77/vb/07,04,usb,yes,31,30 2006.173.18:33:12.77/vb/08,04,usb,yes,28,31 2006.173.18:33:13.00/vblo/01,629.99,yes,locked 2006.173.18:33:13.00/vblo/02,634.99,yes,locked 2006.173.18:33:13.00/vblo/03,649.99,yes,locked 2006.173.18:33:13.00/vblo/04,679.99,yes,locked 2006.173.18:33:13.00/vblo/05,709.99,yes,locked 2006.173.18:33:13.00/vblo/06,719.99,yes,locked 2006.173.18:33:13.00/vblo/07,734.99,yes,locked 2006.173.18:33:13.00/vblo/08,744.99,yes,locked 2006.173.18:33:13.15/vabw/8 2006.173.18:33:13.30/vbbw/8 2006.173.18:33:13.39/xfe/off,on,15.5 2006.173.18:33:13.77/ifatt/23,28,28,28 2006.173.18:33:14.08/fmout-gps/S +3.91E-07 2006.173.18:33:14.12:!2006.173.18:33:50 2006.173.18:33:50.00:data_valid=off 2006.173.18:33:50.00:"et 2006.173.18:33:50.00:!+3s 2006.173.18:33:53.01:"tape 2006.173.18:33:53.01:postob 2006.173.18:33:53.18/cable/+6.5172E-03 2006.173.18:33:53.18/wx/19.86,1002.3,100 2006.173.18:33:54.08/fmout-gps/S +3.91E-07 2006.173.18:33:54.08:scan_name=173-1835,jd0606,120 2006.173.18:33:54.08:source=2201+315,220314.98,314538.3,2000.0,ccw 2006.173.18:33:55.14#flagr#flagr/antenna,new-source 2006.173.18:33:55.14:checkk5 2006.173.18:33:55.56/chk_autoobs//k5ts1/ autoobs is running! 2006.173.18:33:55.96/chk_autoobs//k5ts2/ autoobs is running! 2006.173.18:33:56.39/chk_autoobs//k5ts3/ autoobs is running! 2006.173.18:33:56.78/chk_autoobs//k5ts4/ autoobs is running! 2006.173.18:33:57.17/chk_obsdata//k5ts1/T1731833??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.18:33:57.56/chk_obsdata//k5ts2/T1731833??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.18:33:57.97/chk_obsdata//k5ts3/T1731833??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.18:33:58.36/chk_obsdata//k5ts4/T1731833??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.18:33:59.08/k5log//k5ts1_log_newline 2006.173.18:33:59.79/k5log//k5ts2_log_newline 2006.173.18:34:00.50/k5log//k5ts3_log_newline 2006.173.18:34:01.21/k5log//k5ts4_log_newline 2006.173.18:34:01.23/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.18:34:01.23:setupk4=1 2006.173.18:34:01.23$setupk4/echo=on 2006.173.18:34:01.23$setupk4/pcalon 2006.173.18:34:01.23$pcalon/"no phase cal control is implemented here 2006.173.18:34:01.23$setupk4/"tpicd=stop 2006.173.18:34:01.23$setupk4/"rec=synch_on 2006.173.18:34:01.23$setupk4/"rec_mode=128 2006.173.18:34:01.23$setupk4/!* 2006.173.18:34:01.23$setupk4/recpk4 2006.173.18:34:01.23$recpk4/recpatch= 2006.173.18:34:01.24$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.18:34:01.24$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.18:34:01.24$setupk4/vck44 2006.173.18:34:01.24$vck44/valo=1,524.99 2006.173.18:34:01.24#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.18:34:01.24#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.18:34:01.24#ibcon#ireg 17 cls_cnt 0 2006.173.18:34:01.24#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.18:34:01.24#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.18:34:01.24#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.18:34:01.24#ibcon#enter wrdev, iclass 17, count 0 2006.173.18:34:01.24#ibcon#first serial, iclass 17, count 0 2006.173.18:34:01.24#ibcon#enter sib2, iclass 17, count 0 2006.173.18:34:01.24#ibcon#flushed, iclass 17, count 0 2006.173.18:34:01.24#ibcon#about to write, iclass 17, count 0 2006.173.18:34:01.24#ibcon#wrote, iclass 17, count 0 2006.173.18:34:01.24#ibcon#about to read 3, iclass 17, count 0 2006.173.18:34:01.26#ibcon#read 3, iclass 17, count 0 2006.173.18:34:01.26#ibcon#about to read 4, iclass 17, count 0 2006.173.18:34:01.26#ibcon#read 4, iclass 17, count 0 2006.173.18:34:01.26#ibcon#about to read 5, iclass 17, count 0 2006.173.18:34:01.26#ibcon#read 5, iclass 17, count 0 2006.173.18:34:01.26#ibcon#about to read 6, iclass 17, count 0 2006.173.18:34:01.26#ibcon#read 6, iclass 17, count 0 2006.173.18:34:01.26#ibcon#end of sib2, iclass 17, count 0 2006.173.18:34:01.26#ibcon#*mode == 0, iclass 17, count 0 2006.173.18:34:01.26#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.18:34:01.26#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.18:34:01.26#ibcon#*before write, iclass 17, count 0 2006.173.18:34:01.26#ibcon#enter sib2, iclass 17, count 0 2006.173.18:34:01.26#ibcon#flushed, iclass 17, count 0 2006.173.18:34:01.26#ibcon#about to write, iclass 17, count 0 2006.173.18:34:01.26#ibcon#wrote, iclass 17, count 0 2006.173.18:34:01.26#ibcon#about to read 3, iclass 17, count 0 2006.173.18:34:01.31#ibcon#read 3, iclass 17, count 0 2006.173.18:34:01.31#ibcon#about to read 4, iclass 17, count 0 2006.173.18:34:01.31#ibcon#read 4, iclass 17, count 0 2006.173.18:34:01.31#ibcon#about to read 5, iclass 17, count 0 2006.173.18:34:01.31#ibcon#read 5, iclass 17, count 0 2006.173.18:34:01.31#ibcon#about to read 6, iclass 17, count 0 2006.173.18:34:01.31#ibcon#read 6, iclass 17, count 0 2006.173.18:34:01.31#ibcon#end of sib2, iclass 17, count 0 2006.173.18:34:01.31#ibcon#*after write, iclass 17, count 0 2006.173.18:34:01.31#ibcon#*before return 0, iclass 17, count 0 2006.173.18:34:01.31#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.18:34:01.31#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.18:34:01.31#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.18:34:01.31#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.18:34:01.31$vck44/va=1,7 2006.173.18:34:01.31#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.18:34:01.31#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.18:34:01.31#ibcon#ireg 11 cls_cnt 2 2006.173.18:34:01.31#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.18:34:01.31#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.18:34:01.31#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.18:34:01.31#ibcon#enter wrdev, iclass 19, count 2 2006.173.18:34:01.31#ibcon#first serial, iclass 19, count 2 2006.173.18:34:01.31#ibcon#enter sib2, iclass 19, count 2 2006.173.18:34:01.31#ibcon#flushed, iclass 19, count 2 2006.173.18:34:01.31#ibcon#about to write, iclass 19, count 2 2006.173.18:34:01.31#ibcon#wrote, iclass 19, count 2 2006.173.18:34:01.31#ibcon#about to read 3, iclass 19, count 2 2006.173.18:34:01.33#ibcon#read 3, iclass 19, count 2 2006.173.18:34:01.33#ibcon#about to read 4, iclass 19, count 2 2006.173.18:34:01.33#ibcon#read 4, iclass 19, count 2 2006.173.18:34:01.33#ibcon#about to read 5, iclass 19, count 2 2006.173.18:34:01.33#ibcon#read 5, iclass 19, count 2 2006.173.18:34:01.33#ibcon#about to read 6, iclass 19, count 2 2006.173.18:34:01.33#ibcon#read 6, iclass 19, count 2 2006.173.18:34:01.33#ibcon#end of sib2, iclass 19, count 2 2006.173.18:34:01.33#ibcon#*mode == 0, iclass 19, count 2 2006.173.18:34:01.33#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.18:34:01.33#ibcon#[25=AT01-07\r\n] 2006.173.18:34:01.33#ibcon#*before write, iclass 19, count 2 2006.173.18:34:01.33#ibcon#enter sib2, iclass 19, count 2 2006.173.18:34:01.33#ibcon#flushed, iclass 19, count 2 2006.173.18:34:01.33#ibcon#about to write, iclass 19, count 2 2006.173.18:34:01.33#ibcon#wrote, iclass 19, count 2 2006.173.18:34:01.33#ibcon#about to read 3, iclass 19, count 2 2006.173.18:34:01.36#ibcon#read 3, iclass 19, count 2 2006.173.18:34:01.36#ibcon#about to read 4, iclass 19, count 2 2006.173.18:34:01.36#ibcon#read 4, iclass 19, count 2 2006.173.18:34:01.36#ibcon#about to read 5, iclass 19, count 2 2006.173.18:34:01.36#ibcon#read 5, iclass 19, count 2 2006.173.18:34:01.36#ibcon#about to read 6, iclass 19, count 2 2006.173.18:34:01.36#ibcon#read 6, iclass 19, count 2 2006.173.18:34:01.36#ibcon#end of sib2, iclass 19, count 2 2006.173.18:34:01.36#ibcon#*after write, iclass 19, count 2 2006.173.18:34:01.36#ibcon#*before return 0, iclass 19, count 2 2006.173.18:34:01.36#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.18:34:01.36#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.18:34:01.36#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.18:34:01.36#ibcon#ireg 7 cls_cnt 0 2006.173.18:34:01.36#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.18:34:01.48#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.18:34:01.48#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.18:34:01.48#ibcon#enter wrdev, iclass 19, count 0 2006.173.18:34:01.48#ibcon#first serial, iclass 19, count 0 2006.173.18:34:01.48#ibcon#enter sib2, iclass 19, count 0 2006.173.18:34:01.48#ibcon#flushed, iclass 19, count 0 2006.173.18:34:01.48#ibcon#about to write, iclass 19, count 0 2006.173.18:34:01.48#ibcon#wrote, iclass 19, count 0 2006.173.18:34:01.48#ibcon#about to read 3, iclass 19, count 0 2006.173.18:34:01.50#ibcon#read 3, iclass 19, count 0 2006.173.18:34:01.50#ibcon#about to read 4, iclass 19, count 0 2006.173.18:34:01.50#ibcon#read 4, iclass 19, count 0 2006.173.18:34:01.50#ibcon#about to read 5, iclass 19, count 0 2006.173.18:34:01.50#ibcon#read 5, iclass 19, count 0 2006.173.18:34:01.50#ibcon#about to read 6, iclass 19, count 0 2006.173.18:34:01.50#ibcon#read 6, iclass 19, count 0 2006.173.18:34:01.50#ibcon#end of sib2, iclass 19, count 0 2006.173.18:34:01.50#ibcon#*mode == 0, iclass 19, count 0 2006.173.18:34:01.50#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.18:34:01.50#ibcon#[25=USB\r\n] 2006.173.18:34:01.50#ibcon#*before write, iclass 19, count 0 2006.173.18:34:01.50#ibcon#enter sib2, iclass 19, count 0 2006.173.18:34:01.50#ibcon#flushed, iclass 19, count 0 2006.173.18:34:01.50#ibcon#about to write, iclass 19, count 0 2006.173.18:34:01.50#ibcon#wrote, iclass 19, count 0 2006.173.18:34:01.50#ibcon#about to read 3, iclass 19, count 0 2006.173.18:34:01.53#ibcon#read 3, iclass 19, count 0 2006.173.18:34:01.53#ibcon#about to read 4, iclass 19, count 0 2006.173.18:34:01.53#ibcon#read 4, iclass 19, count 0 2006.173.18:34:01.53#ibcon#about to read 5, iclass 19, count 0 2006.173.18:34:01.53#ibcon#read 5, iclass 19, count 0 2006.173.18:34:01.53#ibcon#about to read 6, iclass 19, count 0 2006.173.18:34:01.53#ibcon#read 6, iclass 19, count 0 2006.173.18:34:01.53#ibcon#end of sib2, iclass 19, count 0 2006.173.18:34:01.53#ibcon#*after write, iclass 19, count 0 2006.173.18:34:01.53#ibcon#*before return 0, iclass 19, count 0 2006.173.18:34:01.53#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.18:34:01.53#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.18:34:01.53#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.18:34:01.53#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.18:34:01.53$vck44/valo=2,534.99 2006.173.18:34:01.53#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.18:34:01.53#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.18:34:01.53#ibcon#ireg 17 cls_cnt 0 2006.173.18:34:01.53#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.18:34:01.53#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.18:34:01.53#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.18:34:01.53#ibcon#enter wrdev, iclass 21, count 0 2006.173.18:34:01.53#ibcon#first serial, iclass 21, count 0 2006.173.18:34:01.53#ibcon#enter sib2, iclass 21, count 0 2006.173.18:34:01.53#ibcon#flushed, iclass 21, count 0 2006.173.18:34:01.53#ibcon#about to write, iclass 21, count 0 2006.173.18:34:01.53#ibcon#wrote, iclass 21, count 0 2006.173.18:34:01.53#ibcon#about to read 3, iclass 21, count 0 2006.173.18:34:01.55#ibcon#read 3, iclass 21, count 0 2006.173.18:34:01.55#ibcon#about to read 4, iclass 21, count 0 2006.173.18:34:01.55#ibcon#read 4, iclass 21, count 0 2006.173.18:34:01.55#ibcon#about to read 5, iclass 21, count 0 2006.173.18:34:01.55#ibcon#read 5, iclass 21, count 0 2006.173.18:34:01.55#ibcon#about to read 6, iclass 21, count 0 2006.173.18:34:01.55#ibcon#read 6, iclass 21, count 0 2006.173.18:34:01.55#ibcon#end of sib2, iclass 21, count 0 2006.173.18:34:01.55#ibcon#*mode == 0, iclass 21, count 0 2006.173.18:34:01.55#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.18:34:01.55#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.18:34:01.55#ibcon#*before write, iclass 21, count 0 2006.173.18:34:01.55#ibcon#enter sib2, iclass 21, count 0 2006.173.18:34:01.55#ibcon#flushed, iclass 21, count 0 2006.173.18:34:01.55#ibcon#about to write, iclass 21, count 0 2006.173.18:34:01.55#ibcon#wrote, iclass 21, count 0 2006.173.18:34:01.55#ibcon#about to read 3, iclass 21, count 0 2006.173.18:34:01.59#ibcon#read 3, iclass 21, count 0 2006.173.18:34:01.59#ibcon#about to read 4, iclass 21, count 0 2006.173.18:34:01.59#ibcon#read 4, iclass 21, count 0 2006.173.18:34:01.59#ibcon#about to read 5, iclass 21, count 0 2006.173.18:34:01.59#ibcon#read 5, iclass 21, count 0 2006.173.18:34:01.59#ibcon#about to read 6, iclass 21, count 0 2006.173.18:34:01.59#ibcon#read 6, iclass 21, count 0 2006.173.18:34:01.59#ibcon#end of sib2, iclass 21, count 0 2006.173.18:34:01.59#ibcon#*after write, iclass 21, count 0 2006.173.18:34:01.59#ibcon#*before return 0, iclass 21, count 0 2006.173.18:34:01.59#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.18:34:01.59#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.18:34:01.59#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.18:34:01.59#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.18:34:01.59$vck44/va=2,6 2006.173.18:34:01.59#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.18:34:01.59#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.18:34:01.59#ibcon#ireg 11 cls_cnt 2 2006.173.18:34:01.59#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.18:34:01.65#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.18:34:01.65#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.18:34:01.65#ibcon#enter wrdev, iclass 23, count 2 2006.173.18:34:01.65#ibcon#first serial, iclass 23, count 2 2006.173.18:34:01.65#ibcon#enter sib2, iclass 23, count 2 2006.173.18:34:01.65#ibcon#flushed, iclass 23, count 2 2006.173.18:34:01.65#ibcon#about to write, iclass 23, count 2 2006.173.18:34:01.65#ibcon#wrote, iclass 23, count 2 2006.173.18:34:01.65#ibcon#about to read 3, iclass 23, count 2 2006.173.18:34:01.67#ibcon#read 3, iclass 23, count 2 2006.173.18:34:01.67#ibcon#about to read 4, iclass 23, count 2 2006.173.18:34:01.67#ibcon#read 4, iclass 23, count 2 2006.173.18:34:01.67#ibcon#about to read 5, iclass 23, count 2 2006.173.18:34:01.67#ibcon#read 5, iclass 23, count 2 2006.173.18:34:01.67#ibcon#about to read 6, iclass 23, count 2 2006.173.18:34:01.67#ibcon#read 6, iclass 23, count 2 2006.173.18:34:01.67#ibcon#end of sib2, iclass 23, count 2 2006.173.18:34:01.67#ibcon#*mode == 0, iclass 23, count 2 2006.173.18:34:01.67#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.18:34:01.67#ibcon#[25=AT02-06\r\n] 2006.173.18:34:01.67#ibcon#*before write, iclass 23, count 2 2006.173.18:34:01.67#ibcon#enter sib2, iclass 23, count 2 2006.173.18:34:01.67#ibcon#flushed, iclass 23, count 2 2006.173.18:34:01.67#ibcon#about to write, iclass 23, count 2 2006.173.18:34:01.67#ibcon#wrote, iclass 23, count 2 2006.173.18:34:01.67#ibcon#about to read 3, iclass 23, count 2 2006.173.18:34:01.70#ibcon#read 3, iclass 23, count 2 2006.173.18:34:01.70#ibcon#about to read 4, iclass 23, count 2 2006.173.18:34:01.70#ibcon#read 4, iclass 23, count 2 2006.173.18:34:01.70#ibcon#about to read 5, iclass 23, count 2 2006.173.18:34:01.70#ibcon#read 5, iclass 23, count 2 2006.173.18:34:01.70#ibcon#about to read 6, iclass 23, count 2 2006.173.18:34:01.70#ibcon#read 6, iclass 23, count 2 2006.173.18:34:01.70#ibcon#end of sib2, iclass 23, count 2 2006.173.18:34:01.70#ibcon#*after write, iclass 23, count 2 2006.173.18:34:01.70#ibcon#*before return 0, iclass 23, count 2 2006.173.18:34:01.70#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.18:34:01.70#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.18:34:01.70#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.18:34:01.70#ibcon#ireg 7 cls_cnt 0 2006.173.18:34:01.70#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.18:34:01.82#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.18:34:01.82#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.18:34:01.82#ibcon#enter wrdev, iclass 23, count 0 2006.173.18:34:01.82#ibcon#first serial, iclass 23, count 0 2006.173.18:34:01.82#ibcon#enter sib2, iclass 23, count 0 2006.173.18:34:01.82#ibcon#flushed, iclass 23, count 0 2006.173.18:34:01.82#ibcon#about to write, iclass 23, count 0 2006.173.18:34:01.82#ibcon#wrote, iclass 23, count 0 2006.173.18:34:01.82#ibcon#about to read 3, iclass 23, count 0 2006.173.18:34:01.84#ibcon#read 3, iclass 23, count 0 2006.173.18:34:01.84#ibcon#about to read 4, iclass 23, count 0 2006.173.18:34:01.84#ibcon#read 4, iclass 23, count 0 2006.173.18:34:01.84#ibcon#about to read 5, iclass 23, count 0 2006.173.18:34:01.84#ibcon#read 5, iclass 23, count 0 2006.173.18:34:01.84#ibcon#about to read 6, iclass 23, count 0 2006.173.18:34:01.84#ibcon#read 6, iclass 23, count 0 2006.173.18:34:01.84#ibcon#end of sib2, iclass 23, count 0 2006.173.18:34:01.84#ibcon#*mode == 0, iclass 23, count 0 2006.173.18:34:01.84#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.18:34:01.84#ibcon#[25=USB\r\n] 2006.173.18:34:01.84#ibcon#*before write, iclass 23, count 0 2006.173.18:34:01.84#ibcon#enter sib2, iclass 23, count 0 2006.173.18:34:01.84#ibcon#flushed, iclass 23, count 0 2006.173.18:34:01.84#ibcon#about to write, iclass 23, count 0 2006.173.18:34:01.84#ibcon#wrote, iclass 23, count 0 2006.173.18:34:01.84#ibcon#about to read 3, iclass 23, count 0 2006.173.18:34:01.87#ibcon#read 3, iclass 23, count 0 2006.173.18:34:01.87#ibcon#about to read 4, iclass 23, count 0 2006.173.18:34:01.87#ibcon#read 4, iclass 23, count 0 2006.173.18:34:01.87#ibcon#about to read 5, iclass 23, count 0 2006.173.18:34:01.87#ibcon#read 5, iclass 23, count 0 2006.173.18:34:01.87#ibcon#about to read 6, iclass 23, count 0 2006.173.18:34:01.87#ibcon#read 6, iclass 23, count 0 2006.173.18:34:01.87#ibcon#end of sib2, iclass 23, count 0 2006.173.18:34:01.87#ibcon#*after write, iclass 23, count 0 2006.173.18:34:01.87#ibcon#*before return 0, iclass 23, count 0 2006.173.18:34:01.87#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.18:34:01.87#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.18:34:01.87#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.18:34:01.87#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.18:34:01.87$vck44/valo=3,564.99 2006.173.18:34:01.87#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.18:34:01.87#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.18:34:01.87#ibcon#ireg 17 cls_cnt 0 2006.173.18:34:01.87#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.18:34:01.87#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.18:34:01.87#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.18:34:01.87#ibcon#enter wrdev, iclass 25, count 0 2006.173.18:34:01.87#ibcon#first serial, iclass 25, count 0 2006.173.18:34:01.87#ibcon#enter sib2, iclass 25, count 0 2006.173.18:34:01.87#ibcon#flushed, iclass 25, count 0 2006.173.18:34:01.87#ibcon#about to write, iclass 25, count 0 2006.173.18:34:01.87#ibcon#wrote, iclass 25, count 0 2006.173.18:34:01.87#ibcon#about to read 3, iclass 25, count 0 2006.173.18:34:01.89#ibcon#read 3, iclass 25, count 0 2006.173.18:34:01.89#ibcon#about to read 4, iclass 25, count 0 2006.173.18:34:01.89#ibcon#read 4, iclass 25, count 0 2006.173.18:34:01.89#ibcon#about to read 5, iclass 25, count 0 2006.173.18:34:01.89#ibcon#read 5, iclass 25, count 0 2006.173.18:34:01.89#ibcon#about to read 6, iclass 25, count 0 2006.173.18:34:01.89#ibcon#read 6, iclass 25, count 0 2006.173.18:34:01.89#ibcon#end of sib2, iclass 25, count 0 2006.173.18:34:01.89#ibcon#*mode == 0, iclass 25, count 0 2006.173.18:34:01.89#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.18:34:01.89#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.18:34:01.89#ibcon#*before write, iclass 25, count 0 2006.173.18:34:01.89#ibcon#enter sib2, iclass 25, count 0 2006.173.18:34:01.89#ibcon#flushed, iclass 25, count 0 2006.173.18:34:01.89#ibcon#about to write, iclass 25, count 0 2006.173.18:34:01.89#ibcon#wrote, iclass 25, count 0 2006.173.18:34:01.89#ibcon#about to read 3, iclass 25, count 0 2006.173.18:34:01.93#ibcon#read 3, iclass 25, count 0 2006.173.18:34:01.93#ibcon#about to read 4, iclass 25, count 0 2006.173.18:34:01.93#ibcon#read 4, iclass 25, count 0 2006.173.18:34:01.93#ibcon#about to read 5, iclass 25, count 0 2006.173.18:34:01.93#ibcon#read 5, iclass 25, count 0 2006.173.18:34:01.93#ibcon#about to read 6, iclass 25, count 0 2006.173.18:34:01.93#ibcon#read 6, iclass 25, count 0 2006.173.18:34:01.93#ibcon#end of sib2, iclass 25, count 0 2006.173.18:34:01.93#ibcon#*after write, iclass 25, count 0 2006.173.18:34:01.93#ibcon#*before return 0, iclass 25, count 0 2006.173.18:34:01.93#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.18:34:01.93#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.18:34:01.93#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.18:34:01.93#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.18:34:01.93$vck44/va=3,5 2006.173.18:34:01.93#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.18:34:01.93#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.18:34:01.93#ibcon#ireg 11 cls_cnt 2 2006.173.18:34:01.93#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.18:34:01.99#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.18:34:01.99#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.18:34:01.99#ibcon#enter wrdev, iclass 27, count 2 2006.173.18:34:01.99#ibcon#first serial, iclass 27, count 2 2006.173.18:34:01.99#ibcon#enter sib2, iclass 27, count 2 2006.173.18:34:01.99#ibcon#flushed, iclass 27, count 2 2006.173.18:34:01.99#ibcon#about to write, iclass 27, count 2 2006.173.18:34:01.99#ibcon#wrote, iclass 27, count 2 2006.173.18:34:01.99#ibcon#about to read 3, iclass 27, count 2 2006.173.18:34:02.01#ibcon#read 3, iclass 27, count 2 2006.173.18:34:02.01#ibcon#about to read 4, iclass 27, count 2 2006.173.18:34:02.01#ibcon#read 4, iclass 27, count 2 2006.173.18:34:02.01#ibcon#about to read 5, iclass 27, count 2 2006.173.18:34:02.01#ibcon#read 5, iclass 27, count 2 2006.173.18:34:02.01#ibcon#about to read 6, iclass 27, count 2 2006.173.18:34:02.01#ibcon#read 6, iclass 27, count 2 2006.173.18:34:02.01#ibcon#end of sib2, iclass 27, count 2 2006.173.18:34:02.01#ibcon#*mode == 0, iclass 27, count 2 2006.173.18:34:02.01#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.18:34:02.01#ibcon#[25=AT03-05\r\n] 2006.173.18:34:02.01#ibcon#*before write, iclass 27, count 2 2006.173.18:34:02.01#ibcon#enter sib2, iclass 27, count 2 2006.173.18:34:02.01#ibcon#flushed, iclass 27, count 2 2006.173.18:34:02.01#ibcon#about to write, iclass 27, count 2 2006.173.18:34:02.01#ibcon#wrote, iclass 27, count 2 2006.173.18:34:02.01#ibcon#about to read 3, iclass 27, count 2 2006.173.18:34:02.04#ibcon#read 3, iclass 27, count 2 2006.173.18:34:02.04#ibcon#about to read 4, iclass 27, count 2 2006.173.18:34:02.04#ibcon#read 4, iclass 27, count 2 2006.173.18:34:02.04#ibcon#about to read 5, iclass 27, count 2 2006.173.18:34:02.04#ibcon#read 5, iclass 27, count 2 2006.173.18:34:02.04#ibcon#about to read 6, iclass 27, count 2 2006.173.18:34:02.04#ibcon#read 6, iclass 27, count 2 2006.173.18:34:02.04#ibcon#end of sib2, iclass 27, count 2 2006.173.18:34:02.04#ibcon#*after write, iclass 27, count 2 2006.173.18:34:02.04#ibcon#*before return 0, iclass 27, count 2 2006.173.18:34:02.04#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.18:34:02.04#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.18:34:02.04#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.18:34:02.04#ibcon#ireg 7 cls_cnt 0 2006.173.18:34:02.04#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.18:34:02.16#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.18:34:02.16#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.18:34:02.16#ibcon#enter wrdev, iclass 27, count 0 2006.173.18:34:02.16#ibcon#first serial, iclass 27, count 0 2006.173.18:34:02.16#ibcon#enter sib2, iclass 27, count 0 2006.173.18:34:02.16#ibcon#flushed, iclass 27, count 0 2006.173.18:34:02.16#ibcon#about to write, iclass 27, count 0 2006.173.18:34:02.16#ibcon#wrote, iclass 27, count 0 2006.173.18:34:02.16#ibcon#about to read 3, iclass 27, count 0 2006.173.18:34:02.18#ibcon#read 3, iclass 27, count 0 2006.173.18:34:02.18#ibcon#about to read 4, iclass 27, count 0 2006.173.18:34:02.18#ibcon#read 4, iclass 27, count 0 2006.173.18:34:02.18#ibcon#about to read 5, iclass 27, count 0 2006.173.18:34:02.18#ibcon#read 5, iclass 27, count 0 2006.173.18:34:02.18#ibcon#about to read 6, iclass 27, count 0 2006.173.18:34:02.18#ibcon#read 6, iclass 27, count 0 2006.173.18:34:02.18#ibcon#end of sib2, iclass 27, count 0 2006.173.18:34:02.18#ibcon#*mode == 0, iclass 27, count 0 2006.173.18:34:02.18#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.18:34:02.18#ibcon#[25=USB\r\n] 2006.173.18:34:02.18#ibcon#*before write, iclass 27, count 0 2006.173.18:34:02.18#ibcon#enter sib2, iclass 27, count 0 2006.173.18:34:02.18#ibcon#flushed, iclass 27, count 0 2006.173.18:34:02.18#ibcon#about to write, iclass 27, count 0 2006.173.18:34:02.18#ibcon#wrote, iclass 27, count 0 2006.173.18:34:02.18#ibcon#about to read 3, iclass 27, count 0 2006.173.18:34:02.21#ibcon#read 3, iclass 27, count 0 2006.173.18:34:02.21#ibcon#about to read 4, iclass 27, count 0 2006.173.18:34:02.21#ibcon#read 4, iclass 27, count 0 2006.173.18:34:02.21#ibcon#about to read 5, iclass 27, count 0 2006.173.18:34:02.21#ibcon#read 5, iclass 27, count 0 2006.173.18:34:02.21#ibcon#about to read 6, iclass 27, count 0 2006.173.18:34:02.21#ibcon#read 6, iclass 27, count 0 2006.173.18:34:02.21#ibcon#end of sib2, iclass 27, count 0 2006.173.18:34:02.21#ibcon#*after write, iclass 27, count 0 2006.173.18:34:02.21#ibcon#*before return 0, iclass 27, count 0 2006.173.18:34:02.21#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.18:34:02.21#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.18:34:02.21#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.18:34:02.21#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.18:34:02.21$vck44/valo=4,624.99 2006.173.18:34:02.21#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.18:34:02.21#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.18:34:02.21#ibcon#ireg 17 cls_cnt 0 2006.173.18:34:02.21#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.18:34:02.21#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.18:34:02.21#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.18:34:02.21#ibcon#enter wrdev, iclass 29, count 0 2006.173.18:34:02.21#ibcon#first serial, iclass 29, count 0 2006.173.18:34:02.21#ibcon#enter sib2, iclass 29, count 0 2006.173.18:34:02.21#ibcon#flushed, iclass 29, count 0 2006.173.18:34:02.21#ibcon#about to write, iclass 29, count 0 2006.173.18:34:02.21#ibcon#wrote, iclass 29, count 0 2006.173.18:34:02.21#ibcon#about to read 3, iclass 29, count 0 2006.173.18:34:02.23#ibcon#read 3, iclass 29, count 0 2006.173.18:34:02.23#ibcon#about to read 4, iclass 29, count 0 2006.173.18:34:02.23#ibcon#read 4, iclass 29, count 0 2006.173.18:34:02.23#ibcon#about to read 5, iclass 29, count 0 2006.173.18:34:02.23#ibcon#read 5, iclass 29, count 0 2006.173.18:34:02.23#ibcon#about to read 6, iclass 29, count 0 2006.173.18:34:02.23#ibcon#read 6, iclass 29, count 0 2006.173.18:34:02.23#ibcon#end of sib2, iclass 29, count 0 2006.173.18:34:02.23#ibcon#*mode == 0, iclass 29, count 0 2006.173.18:34:02.23#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.18:34:02.23#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.18:34:02.23#ibcon#*before write, iclass 29, count 0 2006.173.18:34:02.23#ibcon#enter sib2, iclass 29, count 0 2006.173.18:34:02.23#ibcon#flushed, iclass 29, count 0 2006.173.18:34:02.23#ibcon#about to write, iclass 29, count 0 2006.173.18:34:02.23#ibcon#wrote, iclass 29, count 0 2006.173.18:34:02.23#ibcon#about to read 3, iclass 29, count 0 2006.173.18:34:02.27#ibcon#read 3, iclass 29, count 0 2006.173.18:34:02.27#ibcon#about to read 4, iclass 29, count 0 2006.173.18:34:02.27#ibcon#read 4, iclass 29, count 0 2006.173.18:34:02.27#ibcon#about to read 5, iclass 29, count 0 2006.173.18:34:02.27#ibcon#read 5, iclass 29, count 0 2006.173.18:34:02.27#ibcon#about to read 6, iclass 29, count 0 2006.173.18:34:02.27#ibcon#read 6, iclass 29, count 0 2006.173.18:34:02.27#ibcon#end of sib2, iclass 29, count 0 2006.173.18:34:02.27#ibcon#*after write, iclass 29, count 0 2006.173.18:34:02.27#ibcon#*before return 0, iclass 29, count 0 2006.173.18:34:02.27#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.18:34:02.27#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.18:34:02.27#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.18:34:02.27#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.18:34:02.27$vck44/va=4,6 2006.173.18:34:02.27#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.18:34:02.27#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.18:34:02.27#ibcon#ireg 11 cls_cnt 2 2006.173.18:34:02.27#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.18:34:02.33#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.18:34:02.33#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.18:34:02.33#ibcon#enter wrdev, iclass 31, count 2 2006.173.18:34:02.33#ibcon#first serial, iclass 31, count 2 2006.173.18:34:02.33#ibcon#enter sib2, iclass 31, count 2 2006.173.18:34:02.33#ibcon#flushed, iclass 31, count 2 2006.173.18:34:02.33#ibcon#about to write, iclass 31, count 2 2006.173.18:34:02.33#ibcon#wrote, iclass 31, count 2 2006.173.18:34:02.33#ibcon#about to read 3, iclass 31, count 2 2006.173.18:34:02.35#ibcon#read 3, iclass 31, count 2 2006.173.18:34:02.35#ibcon#about to read 4, iclass 31, count 2 2006.173.18:34:02.35#ibcon#read 4, iclass 31, count 2 2006.173.18:34:02.35#ibcon#about to read 5, iclass 31, count 2 2006.173.18:34:02.35#ibcon#read 5, iclass 31, count 2 2006.173.18:34:02.35#ibcon#about to read 6, iclass 31, count 2 2006.173.18:34:02.35#ibcon#read 6, iclass 31, count 2 2006.173.18:34:02.35#ibcon#end of sib2, iclass 31, count 2 2006.173.18:34:02.35#ibcon#*mode == 0, iclass 31, count 2 2006.173.18:34:02.35#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.18:34:02.35#ibcon#[25=AT04-06\r\n] 2006.173.18:34:02.35#ibcon#*before write, iclass 31, count 2 2006.173.18:34:02.35#ibcon#enter sib2, iclass 31, count 2 2006.173.18:34:02.35#ibcon#flushed, iclass 31, count 2 2006.173.18:34:02.35#ibcon#about to write, iclass 31, count 2 2006.173.18:34:02.35#ibcon#wrote, iclass 31, count 2 2006.173.18:34:02.35#ibcon#about to read 3, iclass 31, count 2 2006.173.18:34:02.38#ibcon#read 3, iclass 31, count 2 2006.173.18:34:02.38#ibcon#about to read 4, iclass 31, count 2 2006.173.18:34:02.38#ibcon#read 4, iclass 31, count 2 2006.173.18:34:02.38#ibcon#about to read 5, iclass 31, count 2 2006.173.18:34:02.38#ibcon#read 5, iclass 31, count 2 2006.173.18:34:02.38#ibcon#about to read 6, iclass 31, count 2 2006.173.18:34:02.38#ibcon#read 6, iclass 31, count 2 2006.173.18:34:02.38#ibcon#end of sib2, iclass 31, count 2 2006.173.18:34:02.38#ibcon#*after write, iclass 31, count 2 2006.173.18:34:02.38#ibcon#*before return 0, iclass 31, count 2 2006.173.18:34:02.38#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.18:34:02.38#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.18:34:02.38#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.18:34:02.38#ibcon#ireg 7 cls_cnt 0 2006.173.18:34:02.38#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.18:34:02.50#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.18:34:02.50#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.18:34:02.50#ibcon#enter wrdev, iclass 31, count 0 2006.173.18:34:02.50#ibcon#first serial, iclass 31, count 0 2006.173.18:34:02.50#ibcon#enter sib2, iclass 31, count 0 2006.173.18:34:02.50#ibcon#flushed, iclass 31, count 0 2006.173.18:34:02.50#ibcon#about to write, iclass 31, count 0 2006.173.18:34:02.50#ibcon#wrote, iclass 31, count 0 2006.173.18:34:02.50#ibcon#about to read 3, iclass 31, count 0 2006.173.18:34:02.52#ibcon#read 3, iclass 31, count 0 2006.173.18:34:02.52#ibcon#about to read 4, iclass 31, count 0 2006.173.18:34:02.52#ibcon#read 4, iclass 31, count 0 2006.173.18:34:02.52#ibcon#about to read 5, iclass 31, count 0 2006.173.18:34:02.52#ibcon#read 5, iclass 31, count 0 2006.173.18:34:02.52#ibcon#about to read 6, iclass 31, count 0 2006.173.18:34:02.52#ibcon#read 6, iclass 31, count 0 2006.173.18:34:02.52#ibcon#end of sib2, iclass 31, count 0 2006.173.18:34:02.52#ibcon#*mode == 0, iclass 31, count 0 2006.173.18:34:02.52#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.18:34:02.52#ibcon#[25=USB\r\n] 2006.173.18:34:02.52#ibcon#*before write, iclass 31, count 0 2006.173.18:34:02.52#ibcon#enter sib2, iclass 31, count 0 2006.173.18:34:02.52#ibcon#flushed, iclass 31, count 0 2006.173.18:34:02.52#ibcon#about to write, iclass 31, count 0 2006.173.18:34:02.52#ibcon#wrote, iclass 31, count 0 2006.173.18:34:02.52#ibcon#about to read 3, iclass 31, count 0 2006.173.18:34:02.55#ibcon#read 3, iclass 31, count 0 2006.173.18:34:02.55#ibcon#about to read 4, iclass 31, count 0 2006.173.18:34:02.55#ibcon#read 4, iclass 31, count 0 2006.173.18:34:02.55#ibcon#about to read 5, iclass 31, count 0 2006.173.18:34:02.55#ibcon#read 5, iclass 31, count 0 2006.173.18:34:02.55#ibcon#about to read 6, iclass 31, count 0 2006.173.18:34:02.55#ibcon#read 6, iclass 31, count 0 2006.173.18:34:02.55#ibcon#end of sib2, iclass 31, count 0 2006.173.18:34:02.55#ibcon#*after write, iclass 31, count 0 2006.173.18:34:02.55#ibcon#*before return 0, iclass 31, count 0 2006.173.18:34:02.55#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.18:34:02.55#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.18:34:02.55#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.18:34:02.55#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.18:34:02.55$vck44/valo=5,734.99 2006.173.18:34:02.55#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.18:34:02.55#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.18:34:02.55#ibcon#ireg 17 cls_cnt 0 2006.173.18:34:02.55#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.18:34:02.55#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.18:34:02.55#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.18:34:02.55#ibcon#enter wrdev, iclass 33, count 0 2006.173.18:34:02.55#ibcon#first serial, iclass 33, count 0 2006.173.18:34:02.55#ibcon#enter sib2, iclass 33, count 0 2006.173.18:34:02.55#ibcon#flushed, iclass 33, count 0 2006.173.18:34:02.55#ibcon#about to write, iclass 33, count 0 2006.173.18:34:02.55#ibcon#wrote, iclass 33, count 0 2006.173.18:34:02.55#ibcon#about to read 3, iclass 33, count 0 2006.173.18:34:02.57#ibcon#read 3, iclass 33, count 0 2006.173.18:34:02.57#ibcon#about to read 4, iclass 33, count 0 2006.173.18:34:02.57#ibcon#read 4, iclass 33, count 0 2006.173.18:34:02.57#ibcon#about to read 5, iclass 33, count 0 2006.173.18:34:02.57#ibcon#read 5, iclass 33, count 0 2006.173.18:34:02.57#ibcon#about to read 6, iclass 33, count 0 2006.173.18:34:02.57#ibcon#read 6, iclass 33, count 0 2006.173.18:34:02.57#ibcon#end of sib2, iclass 33, count 0 2006.173.18:34:02.57#ibcon#*mode == 0, iclass 33, count 0 2006.173.18:34:02.57#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.18:34:02.57#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.18:34:02.57#ibcon#*before write, iclass 33, count 0 2006.173.18:34:02.57#ibcon#enter sib2, iclass 33, count 0 2006.173.18:34:02.57#ibcon#flushed, iclass 33, count 0 2006.173.18:34:02.57#ibcon#about to write, iclass 33, count 0 2006.173.18:34:02.57#ibcon#wrote, iclass 33, count 0 2006.173.18:34:02.57#ibcon#about to read 3, iclass 33, count 0 2006.173.18:34:02.61#ibcon#read 3, iclass 33, count 0 2006.173.18:34:02.61#ibcon#about to read 4, iclass 33, count 0 2006.173.18:34:02.61#ibcon#read 4, iclass 33, count 0 2006.173.18:34:02.61#ibcon#about to read 5, iclass 33, count 0 2006.173.18:34:02.61#ibcon#read 5, iclass 33, count 0 2006.173.18:34:02.61#ibcon#about to read 6, iclass 33, count 0 2006.173.18:34:02.61#ibcon#read 6, iclass 33, count 0 2006.173.18:34:02.61#ibcon#end of sib2, iclass 33, count 0 2006.173.18:34:02.61#ibcon#*after write, iclass 33, count 0 2006.173.18:34:02.61#ibcon#*before return 0, iclass 33, count 0 2006.173.18:34:02.61#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.18:34:02.61#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.18:34:02.61#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.18:34:02.61#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.18:34:02.61$vck44/va=5,4 2006.173.18:34:02.61#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.18:34:02.61#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.18:34:02.61#ibcon#ireg 11 cls_cnt 2 2006.173.18:34:02.61#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.18:34:02.67#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.18:34:02.67#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.18:34:02.67#ibcon#enter wrdev, iclass 35, count 2 2006.173.18:34:02.67#ibcon#first serial, iclass 35, count 2 2006.173.18:34:02.67#ibcon#enter sib2, iclass 35, count 2 2006.173.18:34:02.67#ibcon#flushed, iclass 35, count 2 2006.173.18:34:02.67#ibcon#about to write, iclass 35, count 2 2006.173.18:34:02.67#ibcon#wrote, iclass 35, count 2 2006.173.18:34:02.67#ibcon#about to read 3, iclass 35, count 2 2006.173.18:34:02.69#ibcon#read 3, iclass 35, count 2 2006.173.18:34:02.69#ibcon#about to read 4, iclass 35, count 2 2006.173.18:34:02.69#ibcon#read 4, iclass 35, count 2 2006.173.18:34:02.69#ibcon#about to read 5, iclass 35, count 2 2006.173.18:34:02.69#ibcon#read 5, iclass 35, count 2 2006.173.18:34:02.69#ibcon#about to read 6, iclass 35, count 2 2006.173.18:34:02.69#ibcon#read 6, iclass 35, count 2 2006.173.18:34:02.69#ibcon#end of sib2, iclass 35, count 2 2006.173.18:34:02.69#ibcon#*mode == 0, iclass 35, count 2 2006.173.18:34:02.69#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.18:34:02.69#ibcon#[25=AT05-04\r\n] 2006.173.18:34:02.69#ibcon#*before write, iclass 35, count 2 2006.173.18:34:02.69#ibcon#enter sib2, iclass 35, count 2 2006.173.18:34:02.69#ibcon#flushed, iclass 35, count 2 2006.173.18:34:02.69#ibcon#about to write, iclass 35, count 2 2006.173.18:34:02.69#ibcon#wrote, iclass 35, count 2 2006.173.18:34:02.69#ibcon#about to read 3, iclass 35, count 2 2006.173.18:34:02.72#ibcon#read 3, iclass 35, count 2 2006.173.18:34:02.72#ibcon#about to read 4, iclass 35, count 2 2006.173.18:34:02.72#ibcon#read 4, iclass 35, count 2 2006.173.18:34:02.72#ibcon#about to read 5, iclass 35, count 2 2006.173.18:34:02.72#ibcon#read 5, iclass 35, count 2 2006.173.18:34:02.72#ibcon#about to read 6, iclass 35, count 2 2006.173.18:34:02.72#ibcon#read 6, iclass 35, count 2 2006.173.18:34:02.72#ibcon#end of sib2, iclass 35, count 2 2006.173.18:34:02.72#ibcon#*after write, iclass 35, count 2 2006.173.18:34:02.72#ibcon#*before return 0, iclass 35, count 2 2006.173.18:34:02.72#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.18:34:02.72#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.18:34:02.72#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.18:34:02.72#ibcon#ireg 7 cls_cnt 0 2006.173.18:34:02.72#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.18:34:02.84#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.18:34:02.84#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.18:34:02.84#ibcon#enter wrdev, iclass 35, count 0 2006.173.18:34:02.84#ibcon#first serial, iclass 35, count 0 2006.173.18:34:02.84#ibcon#enter sib2, iclass 35, count 0 2006.173.18:34:02.84#ibcon#flushed, iclass 35, count 0 2006.173.18:34:02.84#ibcon#about to write, iclass 35, count 0 2006.173.18:34:02.84#ibcon#wrote, iclass 35, count 0 2006.173.18:34:02.84#ibcon#about to read 3, iclass 35, count 0 2006.173.18:34:02.86#ibcon#read 3, iclass 35, count 0 2006.173.18:34:02.86#ibcon#about to read 4, iclass 35, count 0 2006.173.18:34:02.86#ibcon#read 4, iclass 35, count 0 2006.173.18:34:02.86#ibcon#about to read 5, iclass 35, count 0 2006.173.18:34:02.86#ibcon#read 5, iclass 35, count 0 2006.173.18:34:02.86#ibcon#about to read 6, iclass 35, count 0 2006.173.18:34:02.86#ibcon#read 6, iclass 35, count 0 2006.173.18:34:02.86#ibcon#end of sib2, iclass 35, count 0 2006.173.18:34:02.86#ibcon#*mode == 0, iclass 35, count 0 2006.173.18:34:02.86#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.18:34:02.86#ibcon#[25=USB\r\n] 2006.173.18:34:02.86#ibcon#*before write, iclass 35, count 0 2006.173.18:34:02.86#ibcon#enter sib2, iclass 35, count 0 2006.173.18:34:02.86#ibcon#flushed, iclass 35, count 0 2006.173.18:34:02.86#ibcon#about to write, iclass 35, count 0 2006.173.18:34:02.86#ibcon#wrote, iclass 35, count 0 2006.173.18:34:02.86#ibcon#about to read 3, iclass 35, count 0 2006.173.18:34:02.89#ibcon#read 3, iclass 35, count 0 2006.173.18:34:02.89#ibcon#about to read 4, iclass 35, count 0 2006.173.18:34:02.89#ibcon#read 4, iclass 35, count 0 2006.173.18:34:02.89#ibcon#about to read 5, iclass 35, count 0 2006.173.18:34:02.89#ibcon#read 5, iclass 35, count 0 2006.173.18:34:02.89#ibcon#about to read 6, iclass 35, count 0 2006.173.18:34:02.89#ibcon#read 6, iclass 35, count 0 2006.173.18:34:02.89#ibcon#end of sib2, iclass 35, count 0 2006.173.18:34:02.89#ibcon#*after write, iclass 35, count 0 2006.173.18:34:02.89#ibcon#*before return 0, iclass 35, count 0 2006.173.18:34:02.89#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.18:34:02.89#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.18:34:02.89#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.18:34:02.89#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.18:34:02.89$vck44/valo=6,814.99 2006.173.18:34:02.89#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.18:34:02.89#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.18:34:02.89#ibcon#ireg 17 cls_cnt 0 2006.173.18:34:02.89#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.18:34:02.89#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.18:34:02.89#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.18:34:02.89#ibcon#enter wrdev, iclass 37, count 0 2006.173.18:34:02.89#ibcon#first serial, iclass 37, count 0 2006.173.18:34:02.89#ibcon#enter sib2, iclass 37, count 0 2006.173.18:34:02.89#ibcon#flushed, iclass 37, count 0 2006.173.18:34:02.89#ibcon#about to write, iclass 37, count 0 2006.173.18:34:02.89#ibcon#wrote, iclass 37, count 0 2006.173.18:34:02.89#ibcon#about to read 3, iclass 37, count 0 2006.173.18:34:02.91#ibcon#read 3, iclass 37, count 0 2006.173.18:34:02.91#ibcon#about to read 4, iclass 37, count 0 2006.173.18:34:02.91#ibcon#read 4, iclass 37, count 0 2006.173.18:34:02.91#ibcon#about to read 5, iclass 37, count 0 2006.173.18:34:02.91#ibcon#read 5, iclass 37, count 0 2006.173.18:34:02.91#ibcon#about to read 6, iclass 37, count 0 2006.173.18:34:02.91#ibcon#read 6, iclass 37, count 0 2006.173.18:34:02.91#ibcon#end of sib2, iclass 37, count 0 2006.173.18:34:02.91#ibcon#*mode == 0, iclass 37, count 0 2006.173.18:34:02.91#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.18:34:02.91#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.18:34:02.91#ibcon#*before write, iclass 37, count 0 2006.173.18:34:02.91#ibcon#enter sib2, iclass 37, count 0 2006.173.18:34:02.91#ibcon#flushed, iclass 37, count 0 2006.173.18:34:02.91#ibcon#about to write, iclass 37, count 0 2006.173.18:34:02.91#ibcon#wrote, iclass 37, count 0 2006.173.18:34:02.91#ibcon#about to read 3, iclass 37, count 0 2006.173.18:34:02.95#ibcon#read 3, iclass 37, count 0 2006.173.18:34:02.95#ibcon#about to read 4, iclass 37, count 0 2006.173.18:34:02.95#ibcon#read 4, iclass 37, count 0 2006.173.18:34:02.95#ibcon#about to read 5, iclass 37, count 0 2006.173.18:34:02.95#ibcon#read 5, iclass 37, count 0 2006.173.18:34:02.95#ibcon#about to read 6, iclass 37, count 0 2006.173.18:34:02.95#ibcon#read 6, iclass 37, count 0 2006.173.18:34:02.95#ibcon#end of sib2, iclass 37, count 0 2006.173.18:34:02.95#ibcon#*after write, iclass 37, count 0 2006.173.18:34:02.95#ibcon#*before return 0, iclass 37, count 0 2006.173.18:34:02.95#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.18:34:02.95#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.18:34:02.95#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.18:34:02.95#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.18:34:02.95$vck44/va=6,3 2006.173.18:34:02.95#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.18:34:02.95#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.18:34:02.95#ibcon#ireg 11 cls_cnt 2 2006.173.18:34:02.95#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.18:34:03.01#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.18:34:03.01#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.18:34:03.01#ibcon#enter wrdev, iclass 39, count 2 2006.173.18:34:03.01#ibcon#first serial, iclass 39, count 2 2006.173.18:34:03.01#ibcon#enter sib2, iclass 39, count 2 2006.173.18:34:03.01#ibcon#flushed, iclass 39, count 2 2006.173.18:34:03.01#ibcon#about to write, iclass 39, count 2 2006.173.18:34:03.01#ibcon#wrote, iclass 39, count 2 2006.173.18:34:03.01#ibcon#about to read 3, iclass 39, count 2 2006.173.18:34:03.03#ibcon#read 3, iclass 39, count 2 2006.173.18:34:03.03#ibcon#about to read 4, iclass 39, count 2 2006.173.18:34:03.03#ibcon#read 4, iclass 39, count 2 2006.173.18:34:03.03#ibcon#about to read 5, iclass 39, count 2 2006.173.18:34:03.03#ibcon#read 5, iclass 39, count 2 2006.173.18:34:03.03#ibcon#about to read 6, iclass 39, count 2 2006.173.18:34:03.03#ibcon#read 6, iclass 39, count 2 2006.173.18:34:03.03#ibcon#end of sib2, iclass 39, count 2 2006.173.18:34:03.03#ibcon#*mode == 0, iclass 39, count 2 2006.173.18:34:03.03#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.18:34:03.03#ibcon#[25=AT06-03\r\n] 2006.173.18:34:03.03#ibcon#*before write, iclass 39, count 2 2006.173.18:34:03.03#ibcon#enter sib2, iclass 39, count 2 2006.173.18:34:03.03#ibcon#flushed, iclass 39, count 2 2006.173.18:34:03.03#ibcon#about to write, iclass 39, count 2 2006.173.18:34:03.03#ibcon#wrote, iclass 39, count 2 2006.173.18:34:03.03#ibcon#about to read 3, iclass 39, count 2 2006.173.18:34:03.06#ibcon#read 3, iclass 39, count 2 2006.173.18:34:03.06#ibcon#about to read 4, iclass 39, count 2 2006.173.18:34:03.06#ibcon#read 4, iclass 39, count 2 2006.173.18:34:03.06#ibcon#about to read 5, iclass 39, count 2 2006.173.18:34:03.06#ibcon#read 5, iclass 39, count 2 2006.173.18:34:03.06#ibcon#about to read 6, iclass 39, count 2 2006.173.18:34:03.06#ibcon#read 6, iclass 39, count 2 2006.173.18:34:03.06#ibcon#end of sib2, iclass 39, count 2 2006.173.18:34:03.06#ibcon#*after write, iclass 39, count 2 2006.173.18:34:03.06#ibcon#*before return 0, iclass 39, count 2 2006.173.18:34:03.06#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.18:34:03.06#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.18:34:03.06#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.18:34:03.06#ibcon#ireg 7 cls_cnt 0 2006.173.18:34:03.06#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.18:34:03.18#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.18:34:03.18#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.18:34:03.18#ibcon#enter wrdev, iclass 39, count 0 2006.173.18:34:03.18#ibcon#first serial, iclass 39, count 0 2006.173.18:34:03.18#ibcon#enter sib2, iclass 39, count 0 2006.173.18:34:03.18#ibcon#flushed, iclass 39, count 0 2006.173.18:34:03.18#ibcon#about to write, iclass 39, count 0 2006.173.18:34:03.18#ibcon#wrote, iclass 39, count 0 2006.173.18:34:03.18#ibcon#about to read 3, iclass 39, count 0 2006.173.18:34:03.20#ibcon#read 3, iclass 39, count 0 2006.173.18:34:03.20#ibcon#about to read 4, iclass 39, count 0 2006.173.18:34:03.20#ibcon#read 4, iclass 39, count 0 2006.173.18:34:03.20#ibcon#about to read 5, iclass 39, count 0 2006.173.18:34:03.20#ibcon#read 5, iclass 39, count 0 2006.173.18:34:03.20#ibcon#about to read 6, iclass 39, count 0 2006.173.18:34:03.20#ibcon#read 6, iclass 39, count 0 2006.173.18:34:03.20#ibcon#end of sib2, iclass 39, count 0 2006.173.18:34:03.20#ibcon#*mode == 0, iclass 39, count 0 2006.173.18:34:03.20#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.18:34:03.20#ibcon#[25=USB\r\n] 2006.173.18:34:03.20#ibcon#*before write, iclass 39, count 0 2006.173.18:34:03.20#ibcon#enter sib2, iclass 39, count 0 2006.173.18:34:03.20#ibcon#flushed, iclass 39, count 0 2006.173.18:34:03.20#ibcon#about to write, iclass 39, count 0 2006.173.18:34:03.20#ibcon#wrote, iclass 39, count 0 2006.173.18:34:03.20#ibcon#about to read 3, iclass 39, count 0 2006.173.18:34:03.23#ibcon#read 3, iclass 39, count 0 2006.173.18:34:03.23#ibcon#about to read 4, iclass 39, count 0 2006.173.18:34:03.23#ibcon#read 4, iclass 39, count 0 2006.173.18:34:03.23#ibcon#about to read 5, iclass 39, count 0 2006.173.18:34:03.23#ibcon#read 5, iclass 39, count 0 2006.173.18:34:03.23#ibcon#about to read 6, iclass 39, count 0 2006.173.18:34:03.23#ibcon#read 6, iclass 39, count 0 2006.173.18:34:03.23#ibcon#end of sib2, iclass 39, count 0 2006.173.18:34:03.23#ibcon#*after write, iclass 39, count 0 2006.173.18:34:03.23#ibcon#*before return 0, iclass 39, count 0 2006.173.18:34:03.23#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.18:34:03.23#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.18:34:03.23#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.18:34:03.23#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.18:34:03.23$vck44/valo=7,864.99 2006.173.18:34:03.23#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.18:34:03.23#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.18:34:03.23#ibcon#ireg 17 cls_cnt 0 2006.173.18:34:03.23#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.18:34:03.23#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.18:34:03.23#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.18:34:03.23#ibcon#enter wrdev, iclass 3, count 0 2006.173.18:34:03.23#ibcon#first serial, iclass 3, count 0 2006.173.18:34:03.23#ibcon#enter sib2, iclass 3, count 0 2006.173.18:34:03.23#ibcon#flushed, iclass 3, count 0 2006.173.18:34:03.23#ibcon#about to write, iclass 3, count 0 2006.173.18:34:03.23#ibcon#wrote, iclass 3, count 0 2006.173.18:34:03.23#ibcon#about to read 3, iclass 3, count 0 2006.173.18:34:03.25#ibcon#read 3, iclass 3, count 0 2006.173.18:34:03.25#ibcon#about to read 4, iclass 3, count 0 2006.173.18:34:03.25#ibcon#read 4, iclass 3, count 0 2006.173.18:34:03.25#ibcon#about to read 5, iclass 3, count 0 2006.173.18:34:03.25#ibcon#read 5, iclass 3, count 0 2006.173.18:34:03.25#ibcon#about to read 6, iclass 3, count 0 2006.173.18:34:03.25#ibcon#read 6, iclass 3, count 0 2006.173.18:34:03.25#ibcon#end of sib2, iclass 3, count 0 2006.173.18:34:03.25#ibcon#*mode == 0, iclass 3, count 0 2006.173.18:34:03.25#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.18:34:03.25#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.18:34:03.25#ibcon#*before write, iclass 3, count 0 2006.173.18:34:03.25#ibcon#enter sib2, iclass 3, count 0 2006.173.18:34:03.25#ibcon#flushed, iclass 3, count 0 2006.173.18:34:03.25#ibcon#about to write, iclass 3, count 0 2006.173.18:34:03.25#ibcon#wrote, iclass 3, count 0 2006.173.18:34:03.25#ibcon#about to read 3, iclass 3, count 0 2006.173.18:34:03.29#ibcon#read 3, iclass 3, count 0 2006.173.18:34:03.29#ibcon#about to read 4, iclass 3, count 0 2006.173.18:34:03.29#ibcon#read 4, iclass 3, count 0 2006.173.18:34:03.29#ibcon#about to read 5, iclass 3, count 0 2006.173.18:34:03.29#ibcon#read 5, iclass 3, count 0 2006.173.18:34:03.29#ibcon#about to read 6, iclass 3, count 0 2006.173.18:34:03.29#ibcon#read 6, iclass 3, count 0 2006.173.18:34:03.29#ibcon#end of sib2, iclass 3, count 0 2006.173.18:34:03.29#ibcon#*after write, iclass 3, count 0 2006.173.18:34:03.29#ibcon#*before return 0, iclass 3, count 0 2006.173.18:34:03.29#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.18:34:03.29#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.18:34:03.29#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.18:34:03.29#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.18:34:03.29$vck44/va=7,4 2006.173.18:34:03.29#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.18:34:03.29#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.18:34:03.29#ibcon#ireg 11 cls_cnt 2 2006.173.18:34:03.29#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.18:34:03.35#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.18:34:03.35#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.18:34:03.35#ibcon#enter wrdev, iclass 5, count 2 2006.173.18:34:03.35#ibcon#first serial, iclass 5, count 2 2006.173.18:34:03.35#ibcon#enter sib2, iclass 5, count 2 2006.173.18:34:03.35#ibcon#flushed, iclass 5, count 2 2006.173.18:34:03.35#ibcon#about to write, iclass 5, count 2 2006.173.18:34:03.35#ibcon#wrote, iclass 5, count 2 2006.173.18:34:03.35#ibcon#about to read 3, iclass 5, count 2 2006.173.18:34:03.37#ibcon#read 3, iclass 5, count 2 2006.173.18:34:03.37#ibcon#about to read 4, iclass 5, count 2 2006.173.18:34:03.37#ibcon#read 4, iclass 5, count 2 2006.173.18:34:03.37#ibcon#about to read 5, iclass 5, count 2 2006.173.18:34:03.37#ibcon#read 5, iclass 5, count 2 2006.173.18:34:03.37#ibcon#about to read 6, iclass 5, count 2 2006.173.18:34:03.37#ibcon#read 6, iclass 5, count 2 2006.173.18:34:03.37#ibcon#end of sib2, iclass 5, count 2 2006.173.18:34:03.37#ibcon#*mode == 0, iclass 5, count 2 2006.173.18:34:03.37#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.18:34:03.37#ibcon#[25=AT07-04\r\n] 2006.173.18:34:03.37#ibcon#*before write, iclass 5, count 2 2006.173.18:34:03.37#ibcon#enter sib2, iclass 5, count 2 2006.173.18:34:03.37#ibcon#flushed, iclass 5, count 2 2006.173.18:34:03.37#ibcon#about to write, iclass 5, count 2 2006.173.18:34:03.37#ibcon#wrote, iclass 5, count 2 2006.173.18:34:03.37#ibcon#about to read 3, iclass 5, count 2 2006.173.18:34:03.40#ibcon#read 3, iclass 5, count 2 2006.173.18:34:03.40#ibcon#about to read 4, iclass 5, count 2 2006.173.18:34:03.40#ibcon#read 4, iclass 5, count 2 2006.173.18:34:03.40#ibcon#about to read 5, iclass 5, count 2 2006.173.18:34:03.40#ibcon#read 5, iclass 5, count 2 2006.173.18:34:03.40#ibcon#about to read 6, iclass 5, count 2 2006.173.18:34:03.40#ibcon#read 6, iclass 5, count 2 2006.173.18:34:03.40#ibcon#end of sib2, iclass 5, count 2 2006.173.18:34:03.40#ibcon#*after write, iclass 5, count 2 2006.173.18:34:03.40#ibcon#*before return 0, iclass 5, count 2 2006.173.18:34:03.40#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.18:34:03.40#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.18:34:03.40#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.18:34:03.40#ibcon#ireg 7 cls_cnt 0 2006.173.18:34:03.40#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.18:34:03.52#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.18:34:03.52#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.18:34:03.52#ibcon#enter wrdev, iclass 5, count 0 2006.173.18:34:03.52#ibcon#first serial, iclass 5, count 0 2006.173.18:34:03.52#ibcon#enter sib2, iclass 5, count 0 2006.173.18:34:03.52#ibcon#flushed, iclass 5, count 0 2006.173.18:34:03.52#ibcon#about to write, iclass 5, count 0 2006.173.18:34:03.52#ibcon#wrote, iclass 5, count 0 2006.173.18:34:03.52#ibcon#about to read 3, iclass 5, count 0 2006.173.18:34:03.54#ibcon#read 3, iclass 5, count 0 2006.173.18:34:03.54#ibcon#about to read 4, iclass 5, count 0 2006.173.18:34:03.54#ibcon#read 4, iclass 5, count 0 2006.173.18:34:03.54#ibcon#about to read 5, iclass 5, count 0 2006.173.18:34:03.54#ibcon#read 5, iclass 5, count 0 2006.173.18:34:03.54#ibcon#about to read 6, iclass 5, count 0 2006.173.18:34:03.54#ibcon#read 6, iclass 5, count 0 2006.173.18:34:03.54#ibcon#end of sib2, iclass 5, count 0 2006.173.18:34:03.54#ibcon#*mode == 0, iclass 5, count 0 2006.173.18:34:03.54#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.18:34:03.54#ibcon#[25=USB\r\n] 2006.173.18:34:03.54#ibcon#*before write, iclass 5, count 0 2006.173.18:34:03.54#ibcon#enter sib2, iclass 5, count 0 2006.173.18:34:03.54#ibcon#flushed, iclass 5, count 0 2006.173.18:34:03.54#ibcon#about to write, iclass 5, count 0 2006.173.18:34:03.54#ibcon#wrote, iclass 5, count 0 2006.173.18:34:03.54#ibcon#about to read 3, iclass 5, count 0 2006.173.18:34:03.57#ibcon#read 3, iclass 5, count 0 2006.173.18:34:03.57#ibcon#about to read 4, iclass 5, count 0 2006.173.18:34:03.57#ibcon#read 4, iclass 5, count 0 2006.173.18:34:03.57#ibcon#about to read 5, iclass 5, count 0 2006.173.18:34:03.57#ibcon#read 5, iclass 5, count 0 2006.173.18:34:03.57#ibcon#about to read 6, iclass 5, count 0 2006.173.18:34:03.57#ibcon#read 6, iclass 5, count 0 2006.173.18:34:03.57#ibcon#end of sib2, iclass 5, count 0 2006.173.18:34:03.57#ibcon#*after write, iclass 5, count 0 2006.173.18:34:03.57#ibcon#*before return 0, iclass 5, count 0 2006.173.18:34:03.57#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.18:34:03.57#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.18:34:03.57#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.18:34:03.57#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.18:34:03.57$vck44/valo=8,884.99 2006.173.18:34:03.57#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.18:34:03.57#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.18:34:03.57#ibcon#ireg 17 cls_cnt 0 2006.173.18:34:03.57#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.18:34:03.57#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.18:34:03.57#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.18:34:03.57#ibcon#enter wrdev, iclass 7, count 0 2006.173.18:34:03.57#ibcon#first serial, iclass 7, count 0 2006.173.18:34:03.57#ibcon#enter sib2, iclass 7, count 0 2006.173.18:34:03.57#ibcon#flushed, iclass 7, count 0 2006.173.18:34:03.57#ibcon#about to write, iclass 7, count 0 2006.173.18:34:03.57#ibcon#wrote, iclass 7, count 0 2006.173.18:34:03.57#ibcon#about to read 3, iclass 7, count 0 2006.173.18:34:03.59#ibcon#read 3, iclass 7, count 0 2006.173.18:34:03.59#ibcon#about to read 4, iclass 7, count 0 2006.173.18:34:03.59#ibcon#read 4, iclass 7, count 0 2006.173.18:34:03.59#ibcon#about to read 5, iclass 7, count 0 2006.173.18:34:03.59#ibcon#read 5, iclass 7, count 0 2006.173.18:34:03.59#ibcon#about to read 6, iclass 7, count 0 2006.173.18:34:03.59#ibcon#read 6, iclass 7, count 0 2006.173.18:34:03.59#ibcon#end of sib2, iclass 7, count 0 2006.173.18:34:03.59#ibcon#*mode == 0, iclass 7, count 0 2006.173.18:34:03.59#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.18:34:03.59#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.18:34:03.59#ibcon#*before write, iclass 7, count 0 2006.173.18:34:03.59#ibcon#enter sib2, iclass 7, count 0 2006.173.18:34:03.59#ibcon#flushed, iclass 7, count 0 2006.173.18:34:03.59#ibcon#about to write, iclass 7, count 0 2006.173.18:34:03.59#ibcon#wrote, iclass 7, count 0 2006.173.18:34:03.59#ibcon#about to read 3, iclass 7, count 0 2006.173.18:34:03.63#ibcon#read 3, iclass 7, count 0 2006.173.18:34:03.63#ibcon#about to read 4, iclass 7, count 0 2006.173.18:34:03.63#ibcon#read 4, iclass 7, count 0 2006.173.18:34:03.63#ibcon#about to read 5, iclass 7, count 0 2006.173.18:34:03.63#ibcon#read 5, iclass 7, count 0 2006.173.18:34:03.63#ibcon#about to read 6, iclass 7, count 0 2006.173.18:34:03.63#ibcon#read 6, iclass 7, count 0 2006.173.18:34:03.63#ibcon#end of sib2, iclass 7, count 0 2006.173.18:34:03.63#ibcon#*after write, iclass 7, count 0 2006.173.18:34:03.63#ibcon#*before return 0, iclass 7, count 0 2006.173.18:34:03.63#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.18:34:03.63#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.18:34:03.63#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.18:34:03.63#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.18:34:03.63$vck44/va=8,4 2006.173.18:34:03.63#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.18:34:03.63#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.18:34:03.63#ibcon#ireg 11 cls_cnt 2 2006.173.18:34:03.63#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.18:34:03.69#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.18:34:03.69#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.18:34:03.69#ibcon#enter wrdev, iclass 11, count 2 2006.173.18:34:03.69#ibcon#first serial, iclass 11, count 2 2006.173.18:34:03.69#ibcon#enter sib2, iclass 11, count 2 2006.173.18:34:03.69#ibcon#flushed, iclass 11, count 2 2006.173.18:34:03.69#ibcon#about to write, iclass 11, count 2 2006.173.18:34:03.69#ibcon#wrote, iclass 11, count 2 2006.173.18:34:03.69#ibcon#about to read 3, iclass 11, count 2 2006.173.18:34:03.71#ibcon#read 3, iclass 11, count 2 2006.173.18:34:03.71#ibcon#about to read 4, iclass 11, count 2 2006.173.18:34:03.71#ibcon#read 4, iclass 11, count 2 2006.173.18:34:03.71#ibcon#about to read 5, iclass 11, count 2 2006.173.18:34:03.71#ibcon#read 5, iclass 11, count 2 2006.173.18:34:03.71#ibcon#about to read 6, iclass 11, count 2 2006.173.18:34:03.71#ibcon#read 6, iclass 11, count 2 2006.173.18:34:03.71#ibcon#end of sib2, iclass 11, count 2 2006.173.18:34:03.71#ibcon#*mode == 0, iclass 11, count 2 2006.173.18:34:03.71#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.18:34:03.71#ibcon#[25=AT08-04\r\n] 2006.173.18:34:03.71#ibcon#*before write, iclass 11, count 2 2006.173.18:34:03.71#ibcon#enter sib2, iclass 11, count 2 2006.173.18:34:03.71#ibcon#flushed, iclass 11, count 2 2006.173.18:34:03.71#ibcon#about to write, iclass 11, count 2 2006.173.18:34:03.71#ibcon#wrote, iclass 11, count 2 2006.173.18:34:03.71#ibcon#about to read 3, iclass 11, count 2 2006.173.18:34:03.74#ibcon#read 3, iclass 11, count 2 2006.173.18:34:03.74#ibcon#about to read 4, iclass 11, count 2 2006.173.18:34:03.74#ibcon#read 4, iclass 11, count 2 2006.173.18:34:03.74#ibcon#about to read 5, iclass 11, count 2 2006.173.18:34:03.74#ibcon#read 5, iclass 11, count 2 2006.173.18:34:03.74#ibcon#about to read 6, iclass 11, count 2 2006.173.18:34:03.74#ibcon#read 6, iclass 11, count 2 2006.173.18:34:03.74#ibcon#end of sib2, iclass 11, count 2 2006.173.18:34:03.74#ibcon#*after write, iclass 11, count 2 2006.173.18:34:03.74#ibcon#*before return 0, iclass 11, count 2 2006.173.18:34:03.74#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.18:34:03.74#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.18:34:03.74#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.18:34:03.74#ibcon#ireg 7 cls_cnt 0 2006.173.18:34:03.74#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.18:34:03.86#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.18:34:03.86#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.18:34:03.86#ibcon#enter wrdev, iclass 11, count 0 2006.173.18:34:03.86#ibcon#first serial, iclass 11, count 0 2006.173.18:34:03.86#ibcon#enter sib2, iclass 11, count 0 2006.173.18:34:03.86#ibcon#flushed, iclass 11, count 0 2006.173.18:34:03.86#ibcon#about to write, iclass 11, count 0 2006.173.18:34:03.86#ibcon#wrote, iclass 11, count 0 2006.173.18:34:03.86#ibcon#about to read 3, iclass 11, count 0 2006.173.18:34:03.88#ibcon#read 3, iclass 11, count 0 2006.173.18:34:03.88#ibcon#about to read 4, iclass 11, count 0 2006.173.18:34:03.88#ibcon#read 4, iclass 11, count 0 2006.173.18:34:03.88#ibcon#about to read 5, iclass 11, count 0 2006.173.18:34:03.88#ibcon#read 5, iclass 11, count 0 2006.173.18:34:03.88#ibcon#about to read 6, iclass 11, count 0 2006.173.18:34:03.88#ibcon#read 6, iclass 11, count 0 2006.173.18:34:03.88#ibcon#end of sib2, iclass 11, count 0 2006.173.18:34:03.88#ibcon#*mode == 0, iclass 11, count 0 2006.173.18:34:03.88#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.18:34:03.88#ibcon#[25=USB\r\n] 2006.173.18:34:03.88#ibcon#*before write, iclass 11, count 0 2006.173.18:34:03.88#ibcon#enter sib2, iclass 11, count 0 2006.173.18:34:03.88#ibcon#flushed, iclass 11, count 0 2006.173.18:34:03.88#ibcon#about to write, iclass 11, count 0 2006.173.18:34:03.88#ibcon#wrote, iclass 11, count 0 2006.173.18:34:03.88#ibcon#about to read 3, iclass 11, count 0 2006.173.18:34:03.91#ibcon#read 3, iclass 11, count 0 2006.173.18:34:03.91#ibcon#about to read 4, iclass 11, count 0 2006.173.18:34:03.91#ibcon#read 4, iclass 11, count 0 2006.173.18:34:03.91#ibcon#about to read 5, iclass 11, count 0 2006.173.18:34:03.91#ibcon#read 5, iclass 11, count 0 2006.173.18:34:03.91#ibcon#about to read 6, iclass 11, count 0 2006.173.18:34:03.91#ibcon#read 6, iclass 11, count 0 2006.173.18:34:03.91#ibcon#end of sib2, iclass 11, count 0 2006.173.18:34:03.91#ibcon#*after write, iclass 11, count 0 2006.173.18:34:03.91#ibcon#*before return 0, iclass 11, count 0 2006.173.18:34:03.91#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.18:34:03.91#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.18:34:03.91#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.18:34:03.91#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.18:34:03.91$vck44/vblo=1,629.99 2006.173.18:34:03.91#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.18:34:03.91#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.18:34:03.91#ibcon#ireg 17 cls_cnt 0 2006.173.18:34:03.91#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.18:34:03.91#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.18:34:03.91#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.18:34:03.91#ibcon#enter wrdev, iclass 13, count 0 2006.173.18:34:03.91#ibcon#first serial, iclass 13, count 0 2006.173.18:34:03.91#ibcon#enter sib2, iclass 13, count 0 2006.173.18:34:03.91#ibcon#flushed, iclass 13, count 0 2006.173.18:34:03.91#ibcon#about to write, iclass 13, count 0 2006.173.18:34:03.91#ibcon#wrote, iclass 13, count 0 2006.173.18:34:03.91#ibcon#about to read 3, iclass 13, count 0 2006.173.18:34:03.93#ibcon#read 3, iclass 13, count 0 2006.173.18:34:03.93#ibcon#about to read 4, iclass 13, count 0 2006.173.18:34:03.93#ibcon#read 4, iclass 13, count 0 2006.173.18:34:03.93#ibcon#about to read 5, iclass 13, count 0 2006.173.18:34:03.93#ibcon#read 5, iclass 13, count 0 2006.173.18:34:03.93#ibcon#about to read 6, iclass 13, count 0 2006.173.18:34:03.93#ibcon#read 6, iclass 13, count 0 2006.173.18:34:03.93#ibcon#end of sib2, iclass 13, count 0 2006.173.18:34:03.93#ibcon#*mode == 0, iclass 13, count 0 2006.173.18:34:03.93#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.18:34:03.93#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.18:34:03.93#ibcon#*before write, iclass 13, count 0 2006.173.18:34:03.93#ibcon#enter sib2, iclass 13, count 0 2006.173.18:34:03.93#ibcon#flushed, iclass 13, count 0 2006.173.18:34:03.93#ibcon#about to write, iclass 13, count 0 2006.173.18:34:03.93#ibcon#wrote, iclass 13, count 0 2006.173.18:34:03.93#ibcon#about to read 3, iclass 13, count 0 2006.173.18:34:03.97#ibcon#read 3, iclass 13, count 0 2006.173.18:34:03.97#ibcon#about to read 4, iclass 13, count 0 2006.173.18:34:03.97#ibcon#read 4, iclass 13, count 0 2006.173.18:34:03.97#ibcon#about to read 5, iclass 13, count 0 2006.173.18:34:03.97#ibcon#read 5, iclass 13, count 0 2006.173.18:34:03.97#ibcon#about to read 6, iclass 13, count 0 2006.173.18:34:03.97#ibcon#read 6, iclass 13, count 0 2006.173.18:34:03.97#ibcon#end of sib2, iclass 13, count 0 2006.173.18:34:03.97#ibcon#*after write, iclass 13, count 0 2006.173.18:34:03.97#ibcon#*before return 0, iclass 13, count 0 2006.173.18:34:03.97#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.18:34:03.97#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.18:34:03.97#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.18:34:03.97#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.18:34:03.97$vck44/vb=1,4 2006.173.18:34:03.97#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.18:34:03.97#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.18:34:03.97#ibcon#ireg 11 cls_cnt 2 2006.173.18:34:03.97#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.18:34:03.97#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.18:34:03.97#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.18:34:03.97#ibcon#enter wrdev, iclass 15, count 2 2006.173.18:34:03.97#ibcon#first serial, iclass 15, count 2 2006.173.18:34:03.97#ibcon#enter sib2, iclass 15, count 2 2006.173.18:34:03.97#ibcon#flushed, iclass 15, count 2 2006.173.18:34:03.97#ibcon#about to write, iclass 15, count 2 2006.173.18:34:03.97#ibcon#wrote, iclass 15, count 2 2006.173.18:34:03.97#ibcon#about to read 3, iclass 15, count 2 2006.173.18:34:03.99#ibcon#read 3, iclass 15, count 2 2006.173.18:34:03.99#ibcon#about to read 4, iclass 15, count 2 2006.173.18:34:03.99#ibcon#read 4, iclass 15, count 2 2006.173.18:34:03.99#ibcon#about to read 5, iclass 15, count 2 2006.173.18:34:03.99#ibcon#read 5, iclass 15, count 2 2006.173.18:34:03.99#ibcon#about to read 6, iclass 15, count 2 2006.173.18:34:03.99#ibcon#read 6, iclass 15, count 2 2006.173.18:34:03.99#ibcon#end of sib2, iclass 15, count 2 2006.173.18:34:03.99#ibcon#*mode == 0, iclass 15, count 2 2006.173.18:34:03.99#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.18:34:03.99#ibcon#[27=AT01-04\r\n] 2006.173.18:34:03.99#ibcon#*before write, iclass 15, count 2 2006.173.18:34:03.99#ibcon#enter sib2, iclass 15, count 2 2006.173.18:34:03.99#ibcon#flushed, iclass 15, count 2 2006.173.18:34:03.99#ibcon#about to write, iclass 15, count 2 2006.173.18:34:03.99#ibcon#wrote, iclass 15, count 2 2006.173.18:34:03.99#ibcon#about to read 3, iclass 15, count 2 2006.173.18:34:04.02#ibcon#read 3, iclass 15, count 2 2006.173.18:34:04.02#ibcon#about to read 4, iclass 15, count 2 2006.173.18:34:04.02#ibcon#read 4, iclass 15, count 2 2006.173.18:34:04.02#ibcon#about to read 5, iclass 15, count 2 2006.173.18:34:04.02#ibcon#read 5, iclass 15, count 2 2006.173.18:34:04.02#ibcon#about to read 6, iclass 15, count 2 2006.173.18:34:04.02#ibcon#read 6, iclass 15, count 2 2006.173.18:34:04.02#ibcon#end of sib2, iclass 15, count 2 2006.173.18:34:04.02#ibcon#*after write, iclass 15, count 2 2006.173.18:34:04.02#ibcon#*before return 0, iclass 15, count 2 2006.173.18:34:04.02#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.18:34:04.02#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.18:34:04.02#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.18:34:04.02#ibcon#ireg 7 cls_cnt 0 2006.173.18:34:04.02#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.18:34:04.14#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.18:34:04.14#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.18:34:04.14#ibcon#enter wrdev, iclass 15, count 0 2006.173.18:34:04.14#ibcon#first serial, iclass 15, count 0 2006.173.18:34:04.14#ibcon#enter sib2, iclass 15, count 0 2006.173.18:34:04.14#ibcon#flushed, iclass 15, count 0 2006.173.18:34:04.14#ibcon#about to write, iclass 15, count 0 2006.173.18:34:04.14#ibcon#wrote, iclass 15, count 0 2006.173.18:34:04.14#ibcon#about to read 3, iclass 15, count 0 2006.173.18:34:04.16#ibcon#read 3, iclass 15, count 0 2006.173.18:34:04.16#ibcon#about to read 4, iclass 15, count 0 2006.173.18:34:04.16#ibcon#read 4, iclass 15, count 0 2006.173.18:34:04.16#ibcon#about to read 5, iclass 15, count 0 2006.173.18:34:04.16#ibcon#read 5, iclass 15, count 0 2006.173.18:34:04.16#ibcon#about to read 6, iclass 15, count 0 2006.173.18:34:04.16#ibcon#read 6, iclass 15, count 0 2006.173.18:34:04.16#ibcon#end of sib2, iclass 15, count 0 2006.173.18:34:04.16#ibcon#*mode == 0, iclass 15, count 0 2006.173.18:34:04.16#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.18:34:04.16#ibcon#[27=USB\r\n] 2006.173.18:34:04.16#ibcon#*before write, iclass 15, count 0 2006.173.18:34:04.16#ibcon#enter sib2, iclass 15, count 0 2006.173.18:34:04.16#ibcon#flushed, iclass 15, count 0 2006.173.18:34:04.16#ibcon#about to write, iclass 15, count 0 2006.173.18:34:04.16#ibcon#wrote, iclass 15, count 0 2006.173.18:34:04.16#ibcon#about to read 3, iclass 15, count 0 2006.173.18:34:04.19#ibcon#read 3, iclass 15, count 0 2006.173.18:34:04.19#ibcon#about to read 4, iclass 15, count 0 2006.173.18:34:04.19#ibcon#read 4, iclass 15, count 0 2006.173.18:34:04.19#ibcon#about to read 5, iclass 15, count 0 2006.173.18:34:04.19#ibcon#read 5, iclass 15, count 0 2006.173.18:34:04.19#ibcon#about to read 6, iclass 15, count 0 2006.173.18:34:04.19#ibcon#read 6, iclass 15, count 0 2006.173.18:34:04.19#ibcon#end of sib2, iclass 15, count 0 2006.173.18:34:04.19#ibcon#*after write, iclass 15, count 0 2006.173.18:34:04.19#ibcon#*before return 0, iclass 15, count 0 2006.173.18:34:04.19#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.18:34:04.19#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.18:34:04.19#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.18:34:04.19#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.18:34:04.19$vck44/vblo=2,634.99 2006.173.18:34:04.19#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.18:34:04.19#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.18:34:04.19#ibcon#ireg 17 cls_cnt 0 2006.173.18:34:04.19#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.18:34:04.19#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.18:34:04.19#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.18:34:04.19#ibcon#enter wrdev, iclass 17, count 0 2006.173.18:34:04.19#ibcon#first serial, iclass 17, count 0 2006.173.18:34:04.19#ibcon#enter sib2, iclass 17, count 0 2006.173.18:34:04.19#ibcon#flushed, iclass 17, count 0 2006.173.18:34:04.19#ibcon#about to write, iclass 17, count 0 2006.173.18:34:04.19#ibcon#wrote, iclass 17, count 0 2006.173.18:34:04.19#ibcon#about to read 3, iclass 17, count 0 2006.173.18:34:04.21#ibcon#read 3, iclass 17, count 0 2006.173.18:34:04.21#ibcon#about to read 4, iclass 17, count 0 2006.173.18:34:04.21#ibcon#read 4, iclass 17, count 0 2006.173.18:34:04.21#ibcon#about to read 5, iclass 17, count 0 2006.173.18:34:04.21#ibcon#read 5, iclass 17, count 0 2006.173.18:34:04.21#ibcon#about to read 6, iclass 17, count 0 2006.173.18:34:04.21#ibcon#read 6, iclass 17, count 0 2006.173.18:34:04.21#ibcon#end of sib2, iclass 17, count 0 2006.173.18:34:04.21#ibcon#*mode == 0, iclass 17, count 0 2006.173.18:34:04.21#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.18:34:04.21#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.18:34:04.21#ibcon#*before write, iclass 17, count 0 2006.173.18:34:04.21#ibcon#enter sib2, iclass 17, count 0 2006.173.18:34:04.21#ibcon#flushed, iclass 17, count 0 2006.173.18:34:04.21#ibcon#about to write, iclass 17, count 0 2006.173.18:34:04.21#ibcon#wrote, iclass 17, count 0 2006.173.18:34:04.21#ibcon#about to read 3, iclass 17, count 0 2006.173.18:34:04.25#ibcon#read 3, iclass 17, count 0 2006.173.18:34:04.25#ibcon#about to read 4, iclass 17, count 0 2006.173.18:34:04.25#ibcon#read 4, iclass 17, count 0 2006.173.18:34:04.25#ibcon#about to read 5, iclass 17, count 0 2006.173.18:34:04.25#ibcon#read 5, iclass 17, count 0 2006.173.18:34:04.25#ibcon#about to read 6, iclass 17, count 0 2006.173.18:34:04.25#ibcon#read 6, iclass 17, count 0 2006.173.18:34:04.25#ibcon#end of sib2, iclass 17, count 0 2006.173.18:34:04.25#ibcon#*after write, iclass 17, count 0 2006.173.18:34:04.25#ibcon#*before return 0, iclass 17, count 0 2006.173.18:34:04.25#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.18:34:04.25#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.18:34:04.25#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.18:34:04.25#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.18:34:04.25$vck44/vb=2,4 2006.173.18:34:04.25#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.18:34:04.25#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.18:34:04.25#ibcon#ireg 11 cls_cnt 2 2006.173.18:34:04.25#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.18:34:04.31#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.18:34:04.31#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.18:34:04.31#ibcon#enter wrdev, iclass 19, count 2 2006.173.18:34:04.31#ibcon#first serial, iclass 19, count 2 2006.173.18:34:04.31#ibcon#enter sib2, iclass 19, count 2 2006.173.18:34:04.31#ibcon#flushed, iclass 19, count 2 2006.173.18:34:04.31#ibcon#about to write, iclass 19, count 2 2006.173.18:34:04.31#ibcon#wrote, iclass 19, count 2 2006.173.18:34:04.31#ibcon#about to read 3, iclass 19, count 2 2006.173.18:34:04.33#ibcon#read 3, iclass 19, count 2 2006.173.18:34:04.33#ibcon#about to read 4, iclass 19, count 2 2006.173.18:34:04.33#ibcon#read 4, iclass 19, count 2 2006.173.18:34:04.33#ibcon#about to read 5, iclass 19, count 2 2006.173.18:34:04.33#ibcon#read 5, iclass 19, count 2 2006.173.18:34:04.33#ibcon#about to read 6, iclass 19, count 2 2006.173.18:34:04.33#ibcon#read 6, iclass 19, count 2 2006.173.18:34:04.33#ibcon#end of sib2, iclass 19, count 2 2006.173.18:34:04.33#ibcon#*mode == 0, iclass 19, count 2 2006.173.18:34:04.33#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.18:34:04.33#ibcon#[27=AT02-04\r\n] 2006.173.18:34:04.33#ibcon#*before write, iclass 19, count 2 2006.173.18:34:04.33#ibcon#enter sib2, iclass 19, count 2 2006.173.18:34:04.33#ibcon#flushed, iclass 19, count 2 2006.173.18:34:04.33#ibcon#about to write, iclass 19, count 2 2006.173.18:34:04.33#ibcon#wrote, iclass 19, count 2 2006.173.18:34:04.33#ibcon#about to read 3, iclass 19, count 2 2006.173.18:34:04.36#ibcon#read 3, iclass 19, count 2 2006.173.18:34:04.36#ibcon#about to read 4, iclass 19, count 2 2006.173.18:34:04.36#ibcon#read 4, iclass 19, count 2 2006.173.18:34:04.36#ibcon#about to read 5, iclass 19, count 2 2006.173.18:34:04.36#ibcon#read 5, iclass 19, count 2 2006.173.18:34:04.36#ibcon#about to read 6, iclass 19, count 2 2006.173.18:34:04.36#ibcon#read 6, iclass 19, count 2 2006.173.18:34:04.36#ibcon#end of sib2, iclass 19, count 2 2006.173.18:34:04.36#ibcon#*after write, iclass 19, count 2 2006.173.18:34:04.36#ibcon#*before return 0, iclass 19, count 2 2006.173.18:34:04.36#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.18:34:04.36#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.18:34:04.36#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.18:34:04.36#ibcon#ireg 7 cls_cnt 0 2006.173.18:34:04.36#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.18:34:04.48#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.18:34:04.48#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.18:34:04.48#ibcon#enter wrdev, iclass 19, count 0 2006.173.18:34:04.48#ibcon#first serial, iclass 19, count 0 2006.173.18:34:04.48#ibcon#enter sib2, iclass 19, count 0 2006.173.18:34:04.48#ibcon#flushed, iclass 19, count 0 2006.173.18:34:04.48#ibcon#about to write, iclass 19, count 0 2006.173.18:34:04.48#ibcon#wrote, iclass 19, count 0 2006.173.18:34:04.48#ibcon#about to read 3, iclass 19, count 0 2006.173.18:34:04.50#ibcon#read 3, iclass 19, count 0 2006.173.18:34:04.50#ibcon#about to read 4, iclass 19, count 0 2006.173.18:34:04.50#ibcon#read 4, iclass 19, count 0 2006.173.18:34:04.50#ibcon#about to read 5, iclass 19, count 0 2006.173.18:34:04.50#ibcon#read 5, iclass 19, count 0 2006.173.18:34:04.50#ibcon#about to read 6, iclass 19, count 0 2006.173.18:34:04.50#ibcon#read 6, iclass 19, count 0 2006.173.18:34:04.50#ibcon#end of sib2, iclass 19, count 0 2006.173.18:34:04.50#ibcon#*mode == 0, iclass 19, count 0 2006.173.18:34:04.50#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.18:34:04.50#ibcon#[27=USB\r\n] 2006.173.18:34:04.50#ibcon#*before write, iclass 19, count 0 2006.173.18:34:04.50#ibcon#enter sib2, iclass 19, count 0 2006.173.18:34:04.50#ibcon#flushed, iclass 19, count 0 2006.173.18:34:04.50#ibcon#about to write, iclass 19, count 0 2006.173.18:34:04.50#ibcon#wrote, iclass 19, count 0 2006.173.18:34:04.50#ibcon#about to read 3, iclass 19, count 0 2006.173.18:34:04.53#ibcon#read 3, iclass 19, count 0 2006.173.18:34:04.53#ibcon#about to read 4, iclass 19, count 0 2006.173.18:34:04.53#ibcon#read 4, iclass 19, count 0 2006.173.18:34:04.53#ibcon#about to read 5, iclass 19, count 0 2006.173.18:34:04.53#ibcon#read 5, iclass 19, count 0 2006.173.18:34:04.53#ibcon#about to read 6, iclass 19, count 0 2006.173.18:34:04.53#ibcon#read 6, iclass 19, count 0 2006.173.18:34:04.53#ibcon#end of sib2, iclass 19, count 0 2006.173.18:34:04.53#ibcon#*after write, iclass 19, count 0 2006.173.18:34:04.53#ibcon#*before return 0, iclass 19, count 0 2006.173.18:34:04.53#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.18:34:04.53#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.18:34:04.53#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.18:34:04.53#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.18:34:04.53$vck44/vblo=3,649.99 2006.173.18:34:04.53#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.18:34:04.53#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.18:34:04.53#ibcon#ireg 17 cls_cnt 0 2006.173.18:34:04.53#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.18:34:04.53#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.18:34:04.53#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.18:34:04.53#ibcon#enter wrdev, iclass 21, count 0 2006.173.18:34:04.53#ibcon#first serial, iclass 21, count 0 2006.173.18:34:04.53#ibcon#enter sib2, iclass 21, count 0 2006.173.18:34:04.53#ibcon#flushed, iclass 21, count 0 2006.173.18:34:04.53#ibcon#about to write, iclass 21, count 0 2006.173.18:34:04.53#ibcon#wrote, iclass 21, count 0 2006.173.18:34:04.53#ibcon#about to read 3, iclass 21, count 0 2006.173.18:34:04.55#ibcon#read 3, iclass 21, count 0 2006.173.18:34:04.55#ibcon#about to read 4, iclass 21, count 0 2006.173.18:34:04.55#ibcon#read 4, iclass 21, count 0 2006.173.18:34:04.55#ibcon#about to read 5, iclass 21, count 0 2006.173.18:34:04.55#ibcon#read 5, iclass 21, count 0 2006.173.18:34:04.55#ibcon#about to read 6, iclass 21, count 0 2006.173.18:34:04.55#ibcon#read 6, iclass 21, count 0 2006.173.18:34:04.55#ibcon#end of sib2, iclass 21, count 0 2006.173.18:34:04.55#ibcon#*mode == 0, iclass 21, count 0 2006.173.18:34:04.55#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.18:34:04.55#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.18:34:04.55#ibcon#*before write, iclass 21, count 0 2006.173.18:34:04.55#ibcon#enter sib2, iclass 21, count 0 2006.173.18:34:04.55#ibcon#flushed, iclass 21, count 0 2006.173.18:34:04.55#ibcon#about to write, iclass 21, count 0 2006.173.18:34:04.55#ibcon#wrote, iclass 21, count 0 2006.173.18:34:04.55#ibcon#about to read 3, iclass 21, count 0 2006.173.18:34:04.59#ibcon#read 3, iclass 21, count 0 2006.173.18:34:04.59#ibcon#about to read 4, iclass 21, count 0 2006.173.18:34:04.59#ibcon#read 4, iclass 21, count 0 2006.173.18:34:04.59#ibcon#about to read 5, iclass 21, count 0 2006.173.18:34:04.59#ibcon#read 5, iclass 21, count 0 2006.173.18:34:04.59#ibcon#about to read 6, iclass 21, count 0 2006.173.18:34:04.59#ibcon#read 6, iclass 21, count 0 2006.173.18:34:04.59#ibcon#end of sib2, iclass 21, count 0 2006.173.18:34:04.59#ibcon#*after write, iclass 21, count 0 2006.173.18:34:04.59#ibcon#*before return 0, iclass 21, count 0 2006.173.18:34:04.59#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.18:34:04.59#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.18:34:04.59#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.18:34:04.59#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.18:34:04.59$vck44/vb=3,4 2006.173.18:34:04.59#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.18:34:04.59#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.18:34:04.59#ibcon#ireg 11 cls_cnt 2 2006.173.18:34:04.59#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.18:34:04.65#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.18:34:04.65#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.18:34:04.65#ibcon#enter wrdev, iclass 23, count 2 2006.173.18:34:04.65#ibcon#first serial, iclass 23, count 2 2006.173.18:34:04.65#ibcon#enter sib2, iclass 23, count 2 2006.173.18:34:04.65#ibcon#flushed, iclass 23, count 2 2006.173.18:34:04.65#ibcon#about to write, iclass 23, count 2 2006.173.18:34:04.65#ibcon#wrote, iclass 23, count 2 2006.173.18:34:04.65#ibcon#about to read 3, iclass 23, count 2 2006.173.18:34:04.67#ibcon#read 3, iclass 23, count 2 2006.173.18:34:04.67#ibcon#about to read 4, iclass 23, count 2 2006.173.18:34:04.67#ibcon#read 4, iclass 23, count 2 2006.173.18:34:04.67#ibcon#about to read 5, iclass 23, count 2 2006.173.18:34:04.67#ibcon#read 5, iclass 23, count 2 2006.173.18:34:04.67#ibcon#about to read 6, iclass 23, count 2 2006.173.18:34:04.67#ibcon#read 6, iclass 23, count 2 2006.173.18:34:04.67#ibcon#end of sib2, iclass 23, count 2 2006.173.18:34:04.67#ibcon#*mode == 0, iclass 23, count 2 2006.173.18:34:04.67#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.18:34:04.67#ibcon#[27=AT03-04\r\n] 2006.173.18:34:04.67#ibcon#*before write, iclass 23, count 2 2006.173.18:34:04.67#ibcon#enter sib2, iclass 23, count 2 2006.173.18:34:04.67#ibcon#flushed, iclass 23, count 2 2006.173.18:34:04.67#ibcon#about to write, iclass 23, count 2 2006.173.18:34:04.67#ibcon#wrote, iclass 23, count 2 2006.173.18:34:04.67#ibcon#about to read 3, iclass 23, count 2 2006.173.18:34:04.70#ibcon#read 3, iclass 23, count 2 2006.173.18:34:04.70#ibcon#about to read 4, iclass 23, count 2 2006.173.18:34:04.70#ibcon#read 4, iclass 23, count 2 2006.173.18:34:04.70#ibcon#about to read 5, iclass 23, count 2 2006.173.18:34:04.70#ibcon#read 5, iclass 23, count 2 2006.173.18:34:04.70#ibcon#about to read 6, iclass 23, count 2 2006.173.18:34:04.70#ibcon#read 6, iclass 23, count 2 2006.173.18:34:04.70#ibcon#end of sib2, iclass 23, count 2 2006.173.18:34:04.70#ibcon#*after write, iclass 23, count 2 2006.173.18:34:04.70#ibcon#*before return 0, iclass 23, count 2 2006.173.18:34:04.70#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.18:34:04.70#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.18:34:04.70#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.18:34:04.70#ibcon#ireg 7 cls_cnt 0 2006.173.18:34:04.70#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.18:34:04.82#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.18:34:04.82#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.18:34:04.82#ibcon#enter wrdev, iclass 23, count 0 2006.173.18:34:04.82#ibcon#first serial, iclass 23, count 0 2006.173.18:34:04.82#ibcon#enter sib2, iclass 23, count 0 2006.173.18:34:04.82#ibcon#flushed, iclass 23, count 0 2006.173.18:34:04.82#ibcon#about to write, iclass 23, count 0 2006.173.18:34:04.82#ibcon#wrote, iclass 23, count 0 2006.173.18:34:04.82#ibcon#about to read 3, iclass 23, count 0 2006.173.18:34:04.84#ibcon#read 3, iclass 23, count 0 2006.173.18:34:04.84#ibcon#about to read 4, iclass 23, count 0 2006.173.18:34:04.84#ibcon#read 4, iclass 23, count 0 2006.173.18:34:04.84#ibcon#about to read 5, iclass 23, count 0 2006.173.18:34:04.84#ibcon#read 5, iclass 23, count 0 2006.173.18:34:04.84#ibcon#about to read 6, iclass 23, count 0 2006.173.18:34:04.84#ibcon#read 6, iclass 23, count 0 2006.173.18:34:04.84#ibcon#end of sib2, iclass 23, count 0 2006.173.18:34:04.84#ibcon#*mode == 0, iclass 23, count 0 2006.173.18:34:04.84#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.18:34:04.84#ibcon#[27=USB\r\n] 2006.173.18:34:04.84#ibcon#*before write, iclass 23, count 0 2006.173.18:34:04.84#ibcon#enter sib2, iclass 23, count 0 2006.173.18:34:04.84#ibcon#flushed, iclass 23, count 0 2006.173.18:34:04.84#ibcon#about to write, iclass 23, count 0 2006.173.18:34:04.84#ibcon#wrote, iclass 23, count 0 2006.173.18:34:04.84#ibcon#about to read 3, iclass 23, count 0 2006.173.18:34:04.87#ibcon#read 3, iclass 23, count 0 2006.173.18:34:04.87#ibcon#about to read 4, iclass 23, count 0 2006.173.18:34:04.87#ibcon#read 4, iclass 23, count 0 2006.173.18:34:04.87#ibcon#about to read 5, iclass 23, count 0 2006.173.18:34:04.87#ibcon#read 5, iclass 23, count 0 2006.173.18:34:04.87#ibcon#about to read 6, iclass 23, count 0 2006.173.18:34:04.87#ibcon#read 6, iclass 23, count 0 2006.173.18:34:04.87#ibcon#end of sib2, iclass 23, count 0 2006.173.18:34:04.87#ibcon#*after write, iclass 23, count 0 2006.173.18:34:04.87#ibcon#*before return 0, iclass 23, count 0 2006.173.18:34:04.87#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.18:34:04.87#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.18:34:04.87#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.18:34:04.87#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.18:34:04.87$vck44/vblo=4,679.99 2006.173.18:34:04.87#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.18:34:04.87#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.18:34:04.87#ibcon#ireg 17 cls_cnt 0 2006.173.18:34:04.87#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.18:34:04.87#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.18:34:04.87#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.18:34:04.87#ibcon#enter wrdev, iclass 25, count 0 2006.173.18:34:04.87#ibcon#first serial, iclass 25, count 0 2006.173.18:34:04.87#ibcon#enter sib2, iclass 25, count 0 2006.173.18:34:04.87#ibcon#flushed, iclass 25, count 0 2006.173.18:34:04.87#ibcon#about to write, iclass 25, count 0 2006.173.18:34:04.87#ibcon#wrote, iclass 25, count 0 2006.173.18:34:04.87#ibcon#about to read 3, iclass 25, count 0 2006.173.18:34:04.89#ibcon#read 3, iclass 25, count 0 2006.173.18:34:04.89#ibcon#about to read 4, iclass 25, count 0 2006.173.18:34:04.89#ibcon#read 4, iclass 25, count 0 2006.173.18:34:04.89#ibcon#about to read 5, iclass 25, count 0 2006.173.18:34:04.89#ibcon#read 5, iclass 25, count 0 2006.173.18:34:04.89#ibcon#about to read 6, iclass 25, count 0 2006.173.18:34:04.89#ibcon#read 6, iclass 25, count 0 2006.173.18:34:04.89#ibcon#end of sib2, iclass 25, count 0 2006.173.18:34:04.89#ibcon#*mode == 0, iclass 25, count 0 2006.173.18:34:04.89#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.18:34:04.89#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.18:34:04.89#ibcon#*before write, iclass 25, count 0 2006.173.18:34:04.89#ibcon#enter sib2, iclass 25, count 0 2006.173.18:34:04.89#ibcon#flushed, iclass 25, count 0 2006.173.18:34:04.89#ibcon#about to write, iclass 25, count 0 2006.173.18:34:04.89#ibcon#wrote, iclass 25, count 0 2006.173.18:34:04.89#ibcon#about to read 3, iclass 25, count 0 2006.173.18:34:04.93#ibcon#read 3, iclass 25, count 0 2006.173.18:34:04.93#ibcon#about to read 4, iclass 25, count 0 2006.173.18:34:04.93#ibcon#read 4, iclass 25, count 0 2006.173.18:34:04.93#ibcon#about to read 5, iclass 25, count 0 2006.173.18:34:04.93#ibcon#read 5, iclass 25, count 0 2006.173.18:34:04.93#ibcon#about to read 6, iclass 25, count 0 2006.173.18:34:04.93#ibcon#read 6, iclass 25, count 0 2006.173.18:34:04.93#ibcon#end of sib2, iclass 25, count 0 2006.173.18:34:04.93#ibcon#*after write, iclass 25, count 0 2006.173.18:34:04.93#ibcon#*before return 0, iclass 25, count 0 2006.173.18:34:04.93#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.18:34:04.93#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.18:34:04.93#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.18:34:04.93#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.18:34:04.93$vck44/vb=4,4 2006.173.18:34:04.93#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.18:34:04.93#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.18:34:04.93#ibcon#ireg 11 cls_cnt 2 2006.173.18:34:04.93#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.18:34:04.99#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.18:34:04.99#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.18:34:04.99#ibcon#enter wrdev, iclass 27, count 2 2006.173.18:34:04.99#ibcon#first serial, iclass 27, count 2 2006.173.18:34:04.99#ibcon#enter sib2, iclass 27, count 2 2006.173.18:34:04.99#ibcon#flushed, iclass 27, count 2 2006.173.18:34:04.99#ibcon#about to write, iclass 27, count 2 2006.173.18:34:04.99#ibcon#wrote, iclass 27, count 2 2006.173.18:34:04.99#ibcon#about to read 3, iclass 27, count 2 2006.173.18:34:05.01#ibcon#read 3, iclass 27, count 2 2006.173.18:34:05.01#ibcon#about to read 4, iclass 27, count 2 2006.173.18:34:05.01#ibcon#read 4, iclass 27, count 2 2006.173.18:34:05.01#ibcon#about to read 5, iclass 27, count 2 2006.173.18:34:05.01#ibcon#read 5, iclass 27, count 2 2006.173.18:34:05.01#ibcon#about to read 6, iclass 27, count 2 2006.173.18:34:05.01#ibcon#read 6, iclass 27, count 2 2006.173.18:34:05.01#ibcon#end of sib2, iclass 27, count 2 2006.173.18:34:05.01#ibcon#*mode == 0, iclass 27, count 2 2006.173.18:34:05.01#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.18:34:05.01#ibcon#[27=AT04-04\r\n] 2006.173.18:34:05.01#ibcon#*before write, iclass 27, count 2 2006.173.18:34:05.01#ibcon#enter sib2, iclass 27, count 2 2006.173.18:34:05.01#ibcon#flushed, iclass 27, count 2 2006.173.18:34:05.01#ibcon#about to write, iclass 27, count 2 2006.173.18:34:05.01#ibcon#wrote, iclass 27, count 2 2006.173.18:34:05.01#ibcon#about to read 3, iclass 27, count 2 2006.173.18:34:05.04#ibcon#read 3, iclass 27, count 2 2006.173.18:34:05.04#ibcon#about to read 4, iclass 27, count 2 2006.173.18:34:05.04#ibcon#read 4, iclass 27, count 2 2006.173.18:34:05.04#ibcon#about to read 5, iclass 27, count 2 2006.173.18:34:05.04#ibcon#read 5, iclass 27, count 2 2006.173.18:34:05.04#ibcon#about to read 6, iclass 27, count 2 2006.173.18:34:05.04#ibcon#read 6, iclass 27, count 2 2006.173.18:34:05.04#ibcon#end of sib2, iclass 27, count 2 2006.173.18:34:05.04#ibcon#*after write, iclass 27, count 2 2006.173.18:34:05.04#ibcon#*before return 0, iclass 27, count 2 2006.173.18:34:05.04#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.18:34:05.04#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.18:34:05.04#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.18:34:05.04#ibcon#ireg 7 cls_cnt 0 2006.173.18:34:05.04#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.18:34:05.16#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.18:34:05.16#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.18:34:05.16#ibcon#enter wrdev, iclass 27, count 0 2006.173.18:34:05.16#ibcon#first serial, iclass 27, count 0 2006.173.18:34:05.16#ibcon#enter sib2, iclass 27, count 0 2006.173.18:34:05.16#ibcon#flushed, iclass 27, count 0 2006.173.18:34:05.16#ibcon#about to write, iclass 27, count 0 2006.173.18:34:05.16#ibcon#wrote, iclass 27, count 0 2006.173.18:34:05.16#ibcon#about to read 3, iclass 27, count 0 2006.173.18:34:05.18#ibcon#read 3, iclass 27, count 0 2006.173.18:34:05.18#ibcon#about to read 4, iclass 27, count 0 2006.173.18:34:05.18#ibcon#read 4, iclass 27, count 0 2006.173.18:34:05.18#ibcon#about to read 5, iclass 27, count 0 2006.173.18:34:05.18#ibcon#read 5, iclass 27, count 0 2006.173.18:34:05.18#ibcon#about to read 6, iclass 27, count 0 2006.173.18:34:05.18#ibcon#read 6, iclass 27, count 0 2006.173.18:34:05.18#ibcon#end of sib2, iclass 27, count 0 2006.173.18:34:05.18#ibcon#*mode == 0, iclass 27, count 0 2006.173.18:34:05.18#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.18:34:05.18#ibcon#[27=USB\r\n] 2006.173.18:34:05.18#ibcon#*before write, iclass 27, count 0 2006.173.18:34:05.18#ibcon#enter sib2, iclass 27, count 0 2006.173.18:34:05.18#ibcon#flushed, iclass 27, count 0 2006.173.18:34:05.18#ibcon#about to write, iclass 27, count 0 2006.173.18:34:05.18#ibcon#wrote, iclass 27, count 0 2006.173.18:34:05.18#ibcon#about to read 3, iclass 27, count 0 2006.173.18:34:05.21#ibcon#read 3, iclass 27, count 0 2006.173.18:34:05.21#ibcon#about to read 4, iclass 27, count 0 2006.173.18:34:05.21#ibcon#read 4, iclass 27, count 0 2006.173.18:34:05.21#ibcon#about to read 5, iclass 27, count 0 2006.173.18:34:05.21#ibcon#read 5, iclass 27, count 0 2006.173.18:34:05.21#ibcon#about to read 6, iclass 27, count 0 2006.173.18:34:05.21#ibcon#read 6, iclass 27, count 0 2006.173.18:34:05.21#ibcon#end of sib2, iclass 27, count 0 2006.173.18:34:05.21#ibcon#*after write, iclass 27, count 0 2006.173.18:34:05.21#ibcon#*before return 0, iclass 27, count 0 2006.173.18:34:05.21#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.18:34:05.21#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.18:34:05.21#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.18:34:05.21#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.18:34:05.21$vck44/vblo=5,709.99 2006.173.18:34:05.21#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.18:34:05.21#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.18:34:05.21#ibcon#ireg 17 cls_cnt 0 2006.173.18:34:05.21#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.18:34:05.21#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.18:34:05.21#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.18:34:05.21#ibcon#enter wrdev, iclass 29, count 0 2006.173.18:34:05.21#ibcon#first serial, iclass 29, count 0 2006.173.18:34:05.21#ibcon#enter sib2, iclass 29, count 0 2006.173.18:34:05.21#ibcon#flushed, iclass 29, count 0 2006.173.18:34:05.21#ibcon#about to write, iclass 29, count 0 2006.173.18:34:05.21#ibcon#wrote, iclass 29, count 0 2006.173.18:34:05.21#ibcon#about to read 3, iclass 29, count 0 2006.173.18:34:05.23#ibcon#read 3, iclass 29, count 0 2006.173.18:34:05.23#ibcon#about to read 4, iclass 29, count 0 2006.173.18:34:05.23#ibcon#read 4, iclass 29, count 0 2006.173.18:34:05.23#ibcon#about to read 5, iclass 29, count 0 2006.173.18:34:05.23#ibcon#read 5, iclass 29, count 0 2006.173.18:34:05.23#ibcon#about to read 6, iclass 29, count 0 2006.173.18:34:05.23#ibcon#read 6, iclass 29, count 0 2006.173.18:34:05.23#ibcon#end of sib2, iclass 29, count 0 2006.173.18:34:05.23#ibcon#*mode == 0, iclass 29, count 0 2006.173.18:34:05.23#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.18:34:05.23#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.18:34:05.23#ibcon#*before write, iclass 29, count 0 2006.173.18:34:05.23#ibcon#enter sib2, iclass 29, count 0 2006.173.18:34:05.23#ibcon#flushed, iclass 29, count 0 2006.173.18:34:05.23#ibcon#about to write, iclass 29, count 0 2006.173.18:34:05.23#ibcon#wrote, iclass 29, count 0 2006.173.18:34:05.23#ibcon#about to read 3, iclass 29, count 0 2006.173.18:34:05.27#ibcon#read 3, iclass 29, count 0 2006.173.18:34:05.27#ibcon#about to read 4, iclass 29, count 0 2006.173.18:34:05.27#ibcon#read 4, iclass 29, count 0 2006.173.18:34:05.27#ibcon#about to read 5, iclass 29, count 0 2006.173.18:34:05.27#ibcon#read 5, iclass 29, count 0 2006.173.18:34:05.27#ibcon#about to read 6, iclass 29, count 0 2006.173.18:34:05.27#ibcon#read 6, iclass 29, count 0 2006.173.18:34:05.27#ibcon#end of sib2, iclass 29, count 0 2006.173.18:34:05.27#ibcon#*after write, iclass 29, count 0 2006.173.18:34:05.27#ibcon#*before return 0, iclass 29, count 0 2006.173.18:34:05.27#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.18:34:05.27#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.18:34:05.27#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.18:34:05.27#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.18:34:05.27$vck44/vb=5,4 2006.173.18:34:05.27#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.18:34:05.27#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.18:34:05.27#ibcon#ireg 11 cls_cnt 2 2006.173.18:34:05.27#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.18:34:05.33#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.18:34:05.33#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.18:34:05.33#ibcon#enter wrdev, iclass 31, count 2 2006.173.18:34:05.33#ibcon#first serial, iclass 31, count 2 2006.173.18:34:05.33#ibcon#enter sib2, iclass 31, count 2 2006.173.18:34:05.33#ibcon#flushed, iclass 31, count 2 2006.173.18:34:05.33#ibcon#about to write, iclass 31, count 2 2006.173.18:34:05.33#ibcon#wrote, iclass 31, count 2 2006.173.18:34:05.33#ibcon#about to read 3, iclass 31, count 2 2006.173.18:34:05.35#ibcon#read 3, iclass 31, count 2 2006.173.18:34:05.35#ibcon#about to read 4, iclass 31, count 2 2006.173.18:34:05.35#ibcon#read 4, iclass 31, count 2 2006.173.18:34:05.35#ibcon#about to read 5, iclass 31, count 2 2006.173.18:34:05.35#ibcon#read 5, iclass 31, count 2 2006.173.18:34:05.35#ibcon#about to read 6, iclass 31, count 2 2006.173.18:34:05.35#ibcon#read 6, iclass 31, count 2 2006.173.18:34:05.35#ibcon#end of sib2, iclass 31, count 2 2006.173.18:34:05.35#ibcon#*mode == 0, iclass 31, count 2 2006.173.18:34:05.35#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.18:34:05.35#ibcon#[27=AT05-04\r\n] 2006.173.18:34:05.35#ibcon#*before write, iclass 31, count 2 2006.173.18:34:05.35#ibcon#enter sib2, iclass 31, count 2 2006.173.18:34:05.35#ibcon#flushed, iclass 31, count 2 2006.173.18:34:05.35#ibcon#about to write, iclass 31, count 2 2006.173.18:34:05.35#ibcon#wrote, iclass 31, count 2 2006.173.18:34:05.35#ibcon#about to read 3, iclass 31, count 2 2006.173.18:34:05.38#ibcon#read 3, iclass 31, count 2 2006.173.18:34:05.38#ibcon#about to read 4, iclass 31, count 2 2006.173.18:34:05.38#ibcon#read 4, iclass 31, count 2 2006.173.18:34:05.38#ibcon#about to read 5, iclass 31, count 2 2006.173.18:34:05.38#ibcon#read 5, iclass 31, count 2 2006.173.18:34:05.38#ibcon#about to read 6, iclass 31, count 2 2006.173.18:34:05.38#ibcon#read 6, iclass 31, count 2 2006.173.18:34:05.38#ibcon#end of sib2, iclass 31, count 2 2006.173.18:34:05.38#ibcon#*after write, iclass 31, count 2 2006.173.18:34:05.38#ibcon#*before return 0, iclass 31, count 2 2006.173.18:34:05.38#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.18:34:05.38#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.18:34:05.38#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.18:34:05.38#ibcon#ireg 7 cls_cnt 0 2006.173.18:34:05.38#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.18:34:05.50#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.18:34:05.50#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.18:34:05.50#ibcon#enter wrdev, iclass 31, count 0 2006.173.18:34:05.50#ibcon#first serial, iclass 31, count 0 2006.173.18:34:05.50#ibcon#enter sib2, iclass 31, count 0 2006.173.18:34:05.50#ibcon#flushed, iclass 31, count 0 2006.173.18:34:05.50#ibcon#about to write, iclass 31, count 0 2006.173.18:34:05.50#ibcon#wrote, iclass 31, count 0 2006.173.18:34:05.50#ibcon#about to read 3, iclass 31, count 0 2006.173.18:34:05.52#ibcon#read 3, iclass 31, count 0 2006.173.18:34:05.52#ibcon#about to read 4, iclass 31, count 0 2006.173.18:34:05.52#ibcon#read 4, iclass 31, count 0 2006.173.18:34:05.52#ibcon#about to read 5, iclass 31, count 0 2006.173.18:34:05.52#ibcon#read 5, iclass 31, count 0 2006.173.18:34:05.52#ibcon#about to read 6, iclass 31, count 0 2006.173.18:34:05.52#ibcon#read 6, iclass 31, count 0 2006.173.18:34:05.52#ibcon#end of sib2, iclass 31, count 0 2006.173.18:34:05.52#ibcon#*mode == 0, iclass 31, count 0 2006.173.18:34:05.52#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.18:34:05.52#ibcon#[27=USB\r\n] 2006.173.18:34:05.52#ibcon#*before write, iclass 31, count 0 2006.173.18:34:05.52#ibcon#enter sib2, iclass 31, count 0 2006.173.18:34:05.52#ibcon#flushed, iclass 31, count 0 2006.173.18:34:05.52#ibcon#about to write, iclass 31, count 0 2006.173.18:34:05.52#ibcon#wrote, iclass 31, count 0 2006.173.18:34:05.52#ibcon#about to read 3, iclass 31, count 0 2006.173.18:34:05.55#ibcon#read 3, iclass 31, count 0 2006.173.18:34:05.55#ibcon#about to read 4, iclass 31, count 0 2006.173.18:34:05.55#ibcon#read 4, iclass 31, count 0 2006.173.18:34:05.55#ibcon#about to read 5, iclass 31, count 0 2006.173.18:34:05.55#ibcon#read 5, iclass 31, count 0 2006.173.18:34:05.55#ibcon#about to read 6, iclass 31, count 0 2006.173.18:34:05.55#ibcon#read 6, iclass 31, count 0 2006.173.18:34:05.55#ibcon#end of sib2, iclass 31, count 0 2006.173.18:34:05.55#ibcon#*after write, iclass 31, count 0 2006.173.18:34:05.55#ibcon#*before return 0, iclass 31, count 0 2006.173.18:34:05.55#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.18:34:05.55#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.18:34:05.55#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.18:34:05.55#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.18:34:05.55$vck44/vblo=6,719.99 2006.173.18:34:05.55#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.18:34:05.55#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.18:34:05.55#ibcon#ireg 17 cls_cnt 0 2006.173.18:34:05.55#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.18:34:05.55#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.18:34:05.55#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.18:34:05.55#ibcon#enter wrdev, iclass 33, count 0 2006.173.18:34:05.55#ibcon#first serial, iclass 33, count 0 2006.173.18:34:05.55#ibcon#enter sib2, iclass 33, count 0 2006.173.18:34:05.55#ibcon#flushed, iclass 33, count 0 2006.173.18:34:05.55#ibcon#about to write, iclass 33, count 0 2006.173.18:34:05.55#ibcon#wrote, iclass 33, count 0 2006.173.18:34:05.55#ibcon#about to read 3, iclass 33, count 0 2006.173.18:34:05.57#ibcon#read 3, iclass 33, count 0 2006.173.18:34:05.57#ibcon#about to read 4, iclass 33, count 0 2006.173.18:34:05.57#ibcon#read 4, iclass 33, count 0 2006.173.18:34:05.57#ibcon#about to read 5, iclass 33, count 0 2006.173.18:34:05.57#ibcon#read 5, iclass 33, count 0 2006.173.18:34:05.57#ibcon#about to read 6, iclass 33, count 0 2006.173.18:34:05.57#ibcon#read 6, iclass 33, count 0 2006.173.18:34:05.57#ibcon#end of sib2, iclass 33, count 0 2006.173.18:34:05.57#ibcon#*mode == 0, iclass 33, count 0 2006.173.18:34:05.57#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.18:34:05.57#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.18:34:05.57#ibcon#*before write, iclass 33, count 0 2006.173.18:34:05.57#ibcon#enter sib2, iclass 33, count 0 2006.173.18:34:05.57#ibcon#flushed, iclass 33, count 0 2006.173.18:34:05.57#ibcon#about to write, iclass 33, count 0 2006.173.18:34:05.57#ibcon#wrote, iclass 33, count 0 2006.173.18:34:05.57#ibcon#about to read 3, iclass 33, count 0 2006.173.18:34:05.61#ibcon#read 3, iclass 33, count 0 2006.173.18:34:05.61#ibcon#about to read 4, iclass 33, count 0 2006.173.18:34:05.61#ibcon#read 4, iclass 33, count 0 2006.173.18:34:05.61#ibcon#about to read 5, iclass 33, count 0 2006.173.18:34:05.61#ibcon#read 5, iclass 33, count 0 2006.173.18:34:05.61#ibcon#about to read 6, iclass 33, count 0 2006.173.18:34:05.61#ibcon#read 6, iclass 33, count 0 2006.173.18:34:05.61#ibcon#end of sib2, iclass 33, count 0 2006.173.18:34:05.61#ibcon#*after write, iclass 33, count 0 2006.173.18:34:05.61#ibcon#*before return 0, iclass 33, count 0 2006.173.18:34:05.61#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.18:34:05.61#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.18:34:05.61#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.18:34:05.61#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.18:34:05.61$vck44/vb=6,4 2006.173.18:34:05.61#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.18:34:05.61#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.18:34:05.61#ibcon#ireg 11 cls_cnt 2 2006.173.18:34:05.61#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.18:34:05.67#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.18:34:05.67#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.18:34:05.67#ibcon#enter wrdev, iclass 35, count 2 2006.173.18:34:05.67#ibcon#first serial, iclass 35, count 2 2006.173.18:34:05.67#ibcon#enter sib2, iclass 35, count 2 2006.173.18:34:05.67#ibcon#flushed, iclass 35, count 2 2006.173.18:34:05.67#ibcon#about to write, iclass 35, count 2 2006.173.18:34:05.67#ibcon#wrote, iclass 35, count 2 2006.173.18:34:05.67#ibcon#about to read 3, iclass 35, count 2 2006.173.18:34:05.69#ibcon#read 3, iclass 35, count 2 2006.173.18:34:05.69#ibcon#about to read 4, iclass 35, count 2 2006.173.18:34:05.69#ibcon#read 4, iclass 35, count 2 2006.173.18:34:05.69#ibcon#about to read 5, iclass 35, count 2 2006.173.18:34:05.69#ibcon#read 5, iclass 35, count 2 2006.173.18:34:05.69#ibcon#about to read 6, iclass 35, count 2 2006.173.18:34:05.69#ibcon#read 6, iclass 35, count 2 2006.173.18:34:05.69#ibcon#end of sib2, iclass 35, count 2 2006.173.18:34:05.69#ibcon#*mode == 0, iclass 35, count 2 2006.173.18:34:05.69#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.18:34:05.69#ibcon#[27=AT06-04\r\n] 2006.173.18:34:05.69#ibcon#*before write, iclass 35, count 2 2006.173.18:34:05.69#ibcon#enter sib2, iclass 35, count 2 2006.173.18:34:05.69#ibcon#flushed, iclass 35, count 2 2006.173.18:34:05.69#ibcon#about to write, iclass 35, count 2 2006.173.18:34:05.69#ibcon#wrote, iclass 35, count 2 2006.173.18:34:05.69#ibcon#about to read 3, iclass 35, count 2 2006.173.18:34:05.72#ibcon#read 3, iclass 35, count 2 2006.173.18:34:05.72#ibcon#about to read 4, iclass 35, count 2 2006.173.18:34:05.72#ibcon#read 4, iclass 35, count 2 2006.173.18:34:05.72#ibcon#about to read 5, iclass 35, count 2 2006.173.18:34:05.72#ibcon#read 5, iclass 35, count 2 2006.173.18:34:05.72#ibcon#about to read 6, iclass 35, count 2 2006.173.18:34:05.72#ibcon#read 6, iclass 35, count 2 2006.173.18:34:05.72#ibcon#end of sib2, iclass 35, count 2 2006.173.18:34:05.72#ibcon#*after write, iclass 35, count 2 2006.173.18:34:05.72#ibcon#*before return 0, iclass 35, count 2 2006.173.18:34:05.72#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.18:34:05.72#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.18:34:05.72#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.18:34:05.72#ibcon#ireg 7 cls_cnt 0 2006.173.18:34:05.72#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.18:34:05.84#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.18:34:05.84#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.18:34:05.84#ibcon#enter wrdev, iclass 35, count 0 2006.173.18:34:05.84#ibcon#first serial, iclass 35, count 0 2006.173.18:34:05.84#ibcon#enter sib2, iclass 35, count 0 2006.173.18:34:05.84#ibcon#flushed, iclass 35, count 0 2006.173.18:34:05.84#ibcon#about to write, iclass 35, count 0 2006.173.18:34:05.84#ibcon#wrote, iclass 35, count 0 2006.173.18:34:05.84#ibcon#about to read 3, iclass 35, count 0 2006.173.18:34:05.86#ibcon#read 3, iclass 35, count 0 2006.173.18:34:05.86#ibcon#about to read 4, iclass 35, count 0 2006.173.18:34:05.86#ibcon#read 4, iclass 35, count 0 2006.173.18:34:05.86#ibcon#about to read 5, iclass 35, count 0 2006.173.18:34:05.86#ibcon#read 5, iclass 35, count 0 2006.173.18:34:05.86#ibcon#about to read 6, iclass 35, count 0 2006.173.18:34:05.86#ibcon#read 6, iclass 35, count 0 2006.173.18:34:05.86#ibcon#end of sib2, iclass 35, count 0 2006.173.18:34:05.86#ibcon#*mode == 0, iclass 35, count 0 2006.173.18:34:05.86#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.18:34:05.86#ibcon#[27=USB\r\n] 2006.173.18:34:05.86#ibcon#*before write, iclass 35, count 0 2006.173.18:34:05.86#ibcon#enter sib2, iclass 35, count 0 2006.173.18:34:05.86#ibcon#flushed, iclass 35, count 0 2006.173.18:34:05.86#ibcon#about to write, iclass 35, count 0 2006.173.18:34:05.86#ibcon#wrote, iclass 35, count 0 2006.173.18:34:05.86#ibcon#about to read 3, iclass 35, count 0 2006.173.18:34:05.89#ibcon#read 3, iclass 35, count 0 2006.173.18:34:05.89#ibcon#about to read 4, iclass 35, count 0 2006.173.18:34:05.89#ibcon#read 4, iclass 35, count 0 2006.173.18:34:05.89#ibcon#about to read 5, iclass 35, count 0 2006.173.18:34:05.89#ibcon#read 5, iclass 35, count 0 2006.173.18:34:05.89#ibcon#about to read 6, iclass 35, count 0 2006.173.18:34:05.89#ibcon#read 6, iclass 35, count 0 2006.173.18:34:05.89#ibcon#end of sib2, iclass 35, count 0 2006.173.18:34:05.89#ibcon#*after write, iclass 35, count 0 2006.173.18:34:05.89#ibcon#*before return 0, iclass 35, count 0 2006.173.18:34:05.89#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.18:34:05.89#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.18:34:05.89#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.18:34:05.89#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.18:34:05.89$vck44/vblo=7,734.99 2006.173.18:34:05.89#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.18:34:05.89#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.18:34:05.89#ibcon#ireg 17 cls_cnt 0 2006.173.18:34:05.89#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.18:34:05.89#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.18:34:05.89#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.18:34:05.89#ibcon#enter wrdev, iclass 37, count 0 2006.173.18:34:05.89#ibcon#first serial, iclass 37, count 0 2006.173.18:34:05.89#ibcon#enter sib2, iclass 37, count 0 2006.173.18:34:05.89#ibcon#flushed, iclass 37, count 0 2006.173.18:34:05.89#ibcon#about to write, iclass 37, count 0 2006.173.18:34:05.89#ibcon#wrote, iclass 37, count 0 2006.173.18:34:05.89#ibcon#about to read 3, iclass 37, count 0 2006.173.18:34:05.91#ibcon#read 3, iclass 37, count 0 2006.173.18:34:05.91#ibcon#about to read 4, iclass 37, count 0 2006.173.18:34:05.91#ibcon#read 4, iclass 37, count 0 2006.173.18:34:05.91#ibcon#about to read 5, iclass 37, count 0 2006.173.18:34:05.91#ibcon#read 5, iclass 37, count 0 2006.173.18:34:05.91#ibcon#about to read 6, iclass 37, count 0 2006.173.18:34:05.91#ibcon#read 6, iclass 37, count 0 2006.173.18:34:05.91#ibcon#end of sib2, iclass 37, count 0 2006.173.18:34:05.91#ibcon#*mode == 0, iclass 37, count 0 2006.173.18:34:05.91#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.18:34:05.91#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.18:34:05.91#ibcon#*before write, iclass 37, count 0 2006.173.18:34:05.91#ibcon#enter sib2, iclass 37, count 0 2006.173.18:34:05.91#ibcon#flushed, iclass 37, count 0 2006.173.18:34:05.91#ibcon#about to write, iclass 37, count 0 2006.173.18:34:05.91#ibcon#wrote, iclass 37, count 0 2006.173.18:34:05.91#ibcon#about to read 3, iclass 37, count 0 2006.173.18:34:05.95#ibcon#read 3, iclass 37, count 0 2006.173.18:34:05.95#ibcon#about to read 4, iclass 37, count 0 2006.173.18:34:05.95#ibcon#read 4, iclass 37, count 0 2006.173.18:34:05.95#ibcon#about to read 5, iclass 37, count 0 2006.173.18:34:05.95#ibcon#read 5, iclass 37, count 0 2006.173.18:34:05.95#ibcon#about to read 6, iclass 37, count 0 2006.173.18:34:05.95#ibcon#read 6, iclass 37, count 0 2006.173.18:34:05.95#ibcon#end of sib2, iclass 37, count 0 2006.173.18:34:05.95#ibcon#*after write, iclass 37, count 0 2006.173.18:34:05.95#ibcon#*before return 0, iclass 37, count 0 2006.173.18:34:05.95#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.18:34:05.95#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.18:34:05.95#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.18:34:05.95#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.18:34:05.95$vck44/vb=7,4 2006.173.18:34:05.95#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.18:34:05.95#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.18:34:05.95#ibcon#ireg 11 cls_cnt 2 2006.173.18:34:05.95#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.18:34:06.01#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.18:34:06.01#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.18:34:06.01#ibcon#enter wrdev, iclass 39, count 2 2006.173.18:34:06.01#ibcon#first serial, iclass 39, count 2 2006.173.18:34:06.01#ibcon#enter sib2, iclass 39, count 2 2006.173.18:34:06.01#ibcon#flushed, iclass 39, count 2 2006.173.18:34:06.01#ibcon#about to write, iclass 39, count 2 2006.173.18:34:06.01#ibcon#wrote, iclass 39, count 2 2006.173.18:34:06.01#ibcon#about to read 3, iclass 39, count 2 2006.173.18:34:06.03#ibcon#read 3, iclass 39, count 2 2006.173.18:34:06.03#ibcon#about to read 4, iclass 39, count 2 2006.173.18:34:06.03#ibcon#read 4, iclass 39, count 2 2006.173.18:34:06.03#ibcon#about to read 5, iclass 39, count 2 2006.173.18:34:06.03#ibcon#read 5, iclass 39, count 2 2006.173.18:34:06.03#ibcon#about to read 6, iclass 39, count 2 2006.173.18:34:06.03#ibcon#read 6, iclass 39, count 2 2006.173.18:34:06.03#ibcon#end of sib2, iclass 39, count 2 2006.173.18:34:06.03#ibcon#*mode == 0, iclass 39, count 2 2006.173.18:34:06.03#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.18:34:06.03#ibcon#[27=AT07-04\r\n] 2006.173.18:34:06.03#ibcon#*before write, iclass 39, count 2 2006.173.18:34:06.03#ibcon#enter sib2, iclass 39, count 2 2006.173.18:34:06.03#ibcon#flushed, iclass 39, count 2 2006.173.18:34:06.03#ibcon#about to write, iclass 39, count 2 2006.173.18:34:06.03#ibcon#wrote, iclass 39, count 2 2006.173.18:34:06.03#ibcon#about to read 3, iclass 39, count 2 2006.173.18:34:06.06#ibcon#read 3, iclass 39, count 2 2006.173.18:34:06.06#ibcon#about to read 4, iclass 39, count 2 2006.173.18:34:06.06#ibcon#read 4, iclass 39, count 2 2006.173.18:34:06.06#ibcon#about to read 5, iclass 39, count 2 2006.173.18:34:06.06#ibcon#read 5, iclass 39, count 2 2006.173.18:34:06.06#ibcon#about to read 6, iclass 39, count 2 2006.173.18:34:06.06#ibcon#read 6, iclass 39, count 2 2006.173.18:34:06.06#ibcon#end of sib2, iclass 39, count 2 2006.173.18:34:06.06#ibcon#*after write, iclass 39, count 2 2006.173.18:34:06.06#ibcon#*before return 0, iclass 39, count 2 2006.173.18:34:06.06#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.18:34:06.06#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.18:34:06.06#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.18:34:06.06#ibcon#ireg 7 cls_cnt 0 2006.173.18:34:06.06#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.18:34:06.18#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.18:34:06.18#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.18:34:06.18#ibcon#enter wrdev, iclass 39, count 0 2006.173.18:34:06.18#ibcon#first serial, iclass 39, count 0 2006.173.18:34:06.18#ibcon#enter sib2, iclass 39, count 0 2006.173.18:34:06.18#ibcon#flushed, iclass 39, count 0 2006.173.18:34:06.18#ibcon#about to write, iclass 39, count 0 2006.173.18:34:06.18#ibcon#wrote, iclass 39, count 0 2006.173.18:34:06.18#ibcon#about to read 3, iclass 39, count 0 2006.173.18:34:06.20#ibcon#read 3, iclass 39, count 0 2006.173.18:34:06.20#ibcon#about to read 4, iclass 39, count 0 2006.173.18:34:06.20#ibcon#read 4, iclass 39, count 0 2006.173.18:34:06.20#ibcon#about to read 5, iclass 39, count 0 2006.173.18:34:06.20#ibcon#read 5, iclass 39, count 0 2006.173.18:34:06.20#ibcon#about to read 6, iclass 39, count 0 2006.173.18:34:06.20#ibcon#read 6, iclass 39, count 0 2006.173.18:34:06.20#ibcon#end of sib2, iclass 39, count 0 2006.173.18:34:06.20#ibcon#*mode == 0, iclass 39, count 0 2006.173.18:34:06.20#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.18:34:06.20#ibcon#[27=USB\r\n] 2006.173.18:34:06.20#ibcon#*before write, iclass 39, count 0 2006.173.18:34:06.20#ibcon#enter sib2, iclass 39, count 0 2006.173.18:34:06.20#ibcon#flushed, iclass 39, count 0 2006.173.18:34:06.20#ibcon#about to write, iclass 39, count 0 2006.173.18:34:06.20#ibcon#wrote, iclass 39, count 0 2006.173.18:34:06.20#ibcon#about to read 3, iclass 39, count 0 2006.173.18:34:06.23#ibcon#read 3, iclass 39, count 0 2006.173.18:34:06.23#ibcon#about to read 4, iclass 39, count 0 2006.173.18:34:06.23#ibcon#read 4, iclass 39, count 0 2006.173.18:34:06.23#ibcon#about to read 5, iclass 39, count 0 2006.173.18:34:06.23#ibcon#read 5, iclass 39, count 0 2006.173.18:34:06.23#ibcon#about to read 6, iclass 39, count 0 2006.173.18:34:06.23#ibcon#read 6, iclass 39, count 0 2006.173.18:34:06.23#ibcon#end of sib2, iclass 39, count 0 2006.173.18:34:06.23#ibcon#*after write, iclass 39, count 0 2006.173.18:34:06.23#ibcon#*before return 0, iclass 39, count 0 2006.173.18:34:06.23#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.18:34:06.23#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.18:34:06.23#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.18:34:06.23#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.18:34:06.23$vck44/vblo=8,744.99 2006.173.18:34:06.23#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.18:34:06.23#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.18:34:06.23#ibcon#ireg 17 cls_cnt 0 2006.173.18:34:06.23#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.18:34:06.23#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.18:34:06.23#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.18:34:06.23#ibcon#enter wrdev, iclass 3, count 0 2006.173.18:34:06.23#ibcon#first serial, iclass 3, count 0 2006.173.18:34:06.23#ibcon#enter sib2, iclass 3, count 0 2006.173.18:34:06.23#ibcon#flushed, iclass 3, count 0 2006.173.18:34:06.23#ibcon#about to write, iclass 3, count 0 2006.173.18:34:06.23#ibcon#wrote, iclass 3, count 0 2006.173.18:34:06.23#ibcon#about to read 3, iclass 3, count 0 2006.173.18:34:06.25#ibcon#read 3, iclass 3, count 0 2006.173.18:34:06.25#ibcon#about to read 4, iclass 3, count 0 2006.173.18:34:06.25#ibcon#read 4, iclass 3, count 0 2006.173.18:34:06.25#ibcon#about to read 5, iclass 3, count 0 2006.173.18:34:06.25#ibcon#read 5, iclass 3, count 0 2006.173.18:34:06.25#ibcon#about to read 6, iclass 3, count 0 2006.173.18:34:06.25#ibcon#read 6, iclass 3, count 0 2006.173.18:34:06.25#ibcon#end of sib2, iclass 3, count 0 2006.173.18:34:06.25#ibcon#*mode == 0, iclass 3, count 0 2006.173.18:34:06.25#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.18:34:06.25#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.18:34:06.25#ibcon#*before write, iclass 3, count 0 2006.173.18:34:06.25#ibcon#enter sib2, iclass 3, count 0 2006.173.18:34:06.25#ibcon#flushed, iclass 3, count 0 2006.173.18:34:06.25#ibcon#about to write, iclass 3, count 0 2006.173.18:34:06.25#ibcon#wrote, iclass 3, count 0 2006.173.18:34:06.25#ibcon#about to read 3, iclass 3, count 0 2006.173.18:34:06.29#ibcon#read 3, iclass 3, count 0 2006.173.18:34:06.29#ibcon#about to read 4, iclass 3, count 0 2006.173.18:34:06.29#ibcon#read 4, iclass 3, count 0 2006.173.18:34:06.29#ibcon#about to read 5, iclass 3, count 0 2006.173.18:34:06.29#ibcon#read 5, iclass 3, count 0 2006.173.18:34:06.29#ibcon#about to read 6, iclass 3, count 0 2006.173.18:34:06.29#ibcon#read 6, iclass 3, count 0 2006.173.18:34:06.29#ibcon#end of sib2, iclass 3, count 0 2006.173.18:34:06.29#ibcon#*after write, iclass 3, count 0 2006.173.18:34:06.29#ibcon#*before return 0, iclass 3, count 0 2006.173.18:34:06.29#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.18:34:06.29#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.18:34:06.29#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.18:34:06.29#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.18:34:06.29$vck44/vb=8,4 2006.173.18:34:06.29#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.18:34:06.29#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.18:34:06.29#ibcon#ireg 11 cls_cnt 2 2006.173.18:34:06.29#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.18:34:06.35#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.18:34:06.35#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.18:34:06.35#ibcon#enter wrdev, iclass 5, count 2 2006.173.18:34:06.35#ibcon#first serial, iclass 5, count 2 2006.173.18:34:06.35#ibcon#enter sib2, iclass 5, count 2 2006.173.18:34:06.35#ibcon#flushed, iclass 5, count 2 2006.173.18:34:06.35#ibcon#about to write, iclass 5, count 2 2006.173.18:34:06.35#ibcon#wrote, iclass 5, count 2 2006.173.18:34:06.35#ibcon#about to read 3, iclass 5, count 2 2006.173.18:34:06.37#ibcon#read 3, iclass 5, count 2 2006.173.18:34:06.37#ibcon#about to read 4, iclass 5, count 2 2006.173.18:34:06.37#ibcon#read 4, iclass 5, count 2 2006.173.18:34:06.37#ibcon#about to read 5, iclass 5, count 2 2006.173.18:34:06.37#ibcon#read 5, iclass 5, count 2 2006.173.18:34:06.37#ibcon#about to read 6, iclass 5, count 2 2006.173.18:34:06.37#ibcon#read 6, iclass 5, count 2 2006.173.18:34:06.37#ibcon#end of sib2, iclass 5, count 2 2006.173.18:34:06.37#ibcon#*mode == 0, iclass 5, count 2 2006.173.18:34:06.37#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.18:34:06.37#ibcon#[27=AT08-04\r\n] 2006.173.18:34:06.37#ibcon#*before write, iclass 5, count 2 2006.173.18:34:06.37#ibcon#enter sib2, iclass 5, count 2 2006.173.18:34:06.37#ibcon#flushed, iclass 5, count 2 2006.173.18:34:06.37#ibcon#about to write, iclass 5, count 2 2006.173.18:34:06.37#ibcon#wrote, iclass 5, count 2 2006.173.18:34:06.37#ibcon#about to read 3, iclass 5, count 2 2006.173.18:34:06.40#ibcon#read 3, iclass 5, count 2 2006.173.18:34:06.40#ibcon#about to read 4, iclass 5, count 2 2006.173.18:34:06.40#ibcon#read 4, iclass 5, count 2 2006.173.18:34:06.40#ibcon#about to read 5, iclass 5, count 2 2006.173.18:34:06.40#ibcon#read 5, iclass 5, count 2 2006.173.18:34:06.40#ibcon#about to read 6, iclass 5, count 2 2006.173.18:34:06.40#ibcon#read 6, iclass 5, count 2 2006.173.18:34:06.40#ibcon#end of sib2, iclass 5, count 2 2006.173.18:34:06.40#ibcon#*after write, iclass 5, count 2 2006.173.18:34:06.40#ibcon#*before return 0, iclass 5, count 2 2006.173.18:34:06.40#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.18:34:06.40#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.18:34:06.40#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.18:34:06.40#ibcon#ireg 7 cls_cnt 0 2006.173.18:34:06.40#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.18:34:06.52#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.18:34:06.52#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.18:34:06.52#ibcon#enter wrdev, iclass 5, count 0 2006.173.18:34:06.52#ibcon#first serial, iclass 5, count 0 2006.173.18:34:06.52#ibcon#enter sib2, iclass 5, count 0 2006.173.18:34:06.52#ibcon#flushed, iclass 5, count 0 2006.173.18:34:06.52#ibcon#about to write, iclass 5, count 0 2006.173.18:34:06.52#ibcon#wrote, iclass 5, count 0 2006.173.18:34:06.52#ibcon#about to read 3, iclass 5, count 0 2006.173.18:34:06.54#ibcon#read 3, iclass 5, count 0 2006.173.18:34:06.54#ibcon#about to read 4, iclass 5, count 0 2006.173.18:34:06.54#ibcon#read 4, iclass 5, count 0 2006.173.18:34:06.54#ibcon#about to read 5, iclass 5, count 0 2006.173.18:34:06.54#ibcon#read 5, iclass 5, count 0 2006.173.18:34:06.54#ibcon#about to read 6, iclass 5, count 0 2006.173.18:34:06.54#ibcon#read 6, iclass 5, count 0 2006.173.18:34:06.54#ibcon#end of sib2, iclass 5, count 0 2006.173.18:34:06.54#ibcon#*mode == 0, iclass 5, count 0 2006.173.18:34:06.54#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.18:34:06.54#ibcon#[27=USB\r\n] 2006.173.18:34:06.54#ibcon#*before write, iclass 5, count 0 2006.173.18:34:06.54#ibcon#enter sib2, iclass 5, count 0 2006.173.18:34:06.54#ibcon#flushed, iclass 5, count 0 2006.173.18:34:06.54#ibcon#about to write, iclass 5, count 0 2006.173.18:34:06.54#ibcon#wrote, iclass 5, count 0 2006.173.18:34:06.54#ibcon#about to read 3, iclass 5, count 0 2006.173.18:34:06.57#ibcon#read 3, iclass 5, count 0 2006.173.18:34:06.57#ibcon#about to read 4, iclass 5, count 0 2006.173.18:34:06.57#ibcon#read 4, iclass 5, count 0 2006.173.18:34:06.57#ibcon#about to read 5, iclass 5, count 0 2006.173.18:34:06.57#ibcon#read 5, iclass 5, count 0 2006.173.18:34:06.57#ibcon#about to read 6, iclass 5, count 0 2006.173.18:34:06.57#ibcon#read 6, iclass 5, count 0 2006.173.18:34:06.57#ibcon#end of sib2, iclass 5, count 0 2006.173.18:34:06.57#ibcon#*after write, iclass 5, count 0 2006.173.18:34:06.57#ibcon#*before return 0, iclass 5, count 0 2006.173.18:34:06.57#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.18:34:06.57#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.18:34:06.57#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.18:34:06.57#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.18:34:06.57$vck44/vabw=wide 2006.173.18:34:06.57#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.18:34:06.57#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.18:34:06.57#ibcon#ireg 8 cls_cnt 0 2006.173.18:34:06.57#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.18:34:06.57#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.18:34:06.57#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.18:34:06.57#ibcon#enter wrdev, iclass 7, count 0 2006.173.18:34:06.57#ibcon#first serial, iclass 7, count 0 2006.173.18:34:06.57#ibcon#enter sib2, iclass 7, count 0 2006.173.18:34:06.57#ibcon#flushed, iclass 7, count 0 2006.173.18:34:06.57#ibcon#about to write, iclass 7, count 0 2006.173.18:34:06.57#ibcon#wrote, iclass 7, count 0 2006.173.18:34:06.57#ibcon#about to read 3, iclass 7, count 0 2006.173.18:34:06.59#ibcon#read 3, iclass 7, count 0 2006.173.18:34:06.59#ibcon#about to read 4, iclass 7, count 0 2006.173.18:34:06.59#ibcon#read 4, iclass 7, count 0 2006.173.18:34:06.59#ibcon#about to read 5, iclass 7, count 0 2006.173.18:34:06.59#ibcon#read 5, iclass 7, count 0 2006.173.18:34:06.59#ibcon#about to read 6, iclass 7, count 0 2006.173.18:34:06.59#ibcon#read 6, iclass 7, count 0 2006.173.18:34:06.59#ibcon#end of sib2, iclass 7, count 0 2006.173.18:34:06.59#ibcon#*mode == 0, iclass 7, count 0 2006.173.18:34:06.59#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.18:34:06.59#ibcon#[25=BW32\r\n] 2006.173.18:34:06.59#ibcon#*before write, iclass 7, count 0 2006.173.18:34:06.59#ibcon#enter sib2, iclass 7, count 0 2006.173.18:34:06.59#ibcon#flushed, iclass 7, count 0 2006.173.18:34:06.59#ibcon#about to write, iclass 7, count 0 2006.173.18:34:06.59#ibcon#wrote, iclass 7, count 0 2006.173.18:34:06.59#ibcon#about to read 3, iclass 7, count 0 2006.173.18:34:06.62#ibcon#read 3, iclass 7, count 0 2006.173.18:34:06.62#ibcon#about to read 4, iclass 7, count 0 2006.173.18:34:06.62#ibcon#read 4, iclass 7, count 0 2006.173.18:34:06.62#ibcon#about to read 5, iclass 7, count 0 2006.173.18:34:06.62#ibcon#read 5, iclass 7, count 0 2006.173.18:34:06.62#ibcon#about to read 6, iclass 7, count 0 2006.173.18:34:06.62#ibcon#read 6, iclass 7, count 0 2006.173.18:34:06.62#ibcon#end of sib2, iclass 7, count 0 2006.173.18:34:06.62#ibcon#*after write, iclass 7, count 0 2006.173.18:34:06.62#ibcon#*before return 0, iclass 7, count 0 2006.173.18:34:06.62#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.18:34:06.62#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.18:34:06.62#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.18:34:06.62#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.18:34:06.62$vck44/vbbw=wide 2006.173.18:34:06.62#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.18:34:06.62#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.18:34:06.62#ibcon#ireg 8 cls_cnt 0 2006.173.18:34:06.62#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.18:34:06.69#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.18:34:06.69#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.18:34:06.69#ibcon#enter wrdev, iclass 11, count 0 2006.173.18:34:06.69#ibcon#first serial, iclass 11, count 0 2006.173.18:34:06.69#ibcon#enter sib2, iclass 11, count 0 2006.173.18:34:06.69#ibcon#flushed, iclass 11, count 0 2006.173.18:34:06.69#ibcon#about to write, iclass 11, count 0 2006.173.18:34:06.69#ibcon#wrote, iclass 11, count 0 2006.173.18:34:06.69#ibcon#about to read 3, iclass 11, count 0 2006.173.18:34:06.71#ibcon#read 3, iclass 11, count 0 2006.173.18:34:06.71#ibcon#about to read 4, iclass 11, count 0 2006.173.18:34:06.71#ibcon#read 4, iclass 11, count 0 2006.173.18:34:06.71#ibcon#about to read 5, iclass 11, count 0 2006.173.18:34:06.71#ibcon#read 5, iclass 11, count 0 2006.173.18:34:06.71#ibcon#about to read 6, iclass 11, count 0 2006.173.18:34:06.71#ibcon#read 6, iclass 11, count 0 2006.173.18:34:06.71#ibcon#end of sib2, iclass 11, count 0 2006.173.18:34:06.71#ibcon#*mode == 0, iclass 11, count 0 2006.173.18:34:06.71#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.18:34:06.71#ibcon#[27=BW32\r\n] 2006.173.18:34:06.71#ibcon#*before write, iclass 11, count 0 2006.173.18:34:06.71#ibcon#enter sib2, iclass 11, count 0 2006.173.18:34:06.71#ibcon#flushed, iclass 11, count 0 2006.173.18:34:06.71#ibcon#about to write, iclass 11, count 0 2006.173.18:34:06.71#ibcon#wrote, iclass 11, count 0 2006.173.18:34:06.71#ibcon#about to read 3, iclass 11, count 0 2006.173.18:34:06.74#ibcon#read 3, iclass 11, count 0 2006.173.18:34:06.74#ibcon#about to read 4, iclass 11, count 0 2006.173.18:34:06.74#ibcon#read 4, iclass 11, count 0 2006.173.18:34:06.74#ibcon#about to read 5, iclass 11, count 0 2006.173.18:34:06.74#ibcon#read 5, iclass 11, count 0 2006.173.18:34:06.74#ibcon#about to read 6, iclass 11, count 0 2006.173.18:34:06.74#ibcon#read 6, iclass 11, count 0 2006.173.18:34:06.74#ibcon#end of sib2, iclass 11, count 0 2006.173.18:34:06.74#ibcon#*after write, iclass 11, count 0 2006.173.18:34:06.74#ibcon#*before return 0, iclass 11, count 0 2006.173.18:34:06.74#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.18:34:06.74#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.18:34:06.74#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.18:34:06.74#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.18:34:06.74$setupk4/ifdk4 2006.173.18:34:06.74$ifdk4/lo= 2006.173.18:34:06.74$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.18:34:06.74$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.18:34:06.74$ifdk4/patch= 2006.173.18:34:06.74$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.18:34:06.74$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.18:34:06.74$setupk4/!*+20s 2006.173.18:34:11.28#abcon#<5=/14 1.1 2.0 19.861001002.3\r\n> 2006.173.18:34:11.30#abcon#{5=INTERFACE CLEAR} 2006.173.18:34:11.36#abcon#[5=S1D000X0/0*\r\n] 2006.173.18:34:21.24$setupk4/"tpicd 2006.173.18:34:21.24$setupk4/echo=off 2006.173.18:34:21.24$setupk4/xlog=off 2006.173.18:34:21.24:!2006.173.18:35:33 2006.173.18:34:31.14#trakl#Source acquired 2006.173.18:34:32.14#flagr#flagr/antenna,acquired 2006.173.18:35:33.02:preob 2006.173.18:35:34.15/onsource/TRACKING 2006.173.18:35:34.15:!2006.173.18:35:43 2006.173.18:35:43.02:"tape 2006.173.18:35:43.02:"st=record 2006.173.18:35:43.02:data_valid=on 2006.173.18:35:43.02:midob 2006.173.18:35:44.15/onsource/TRACKING 2006.173.18:35:44.15/wx/19.84,1002.3,100 2006.173.18:35:44.20/cable/+6.5154E-03 2006.173.18:35:45.29/va/01,07,usb,yes,35,37 2006.173.18:35:45.29/va/02,06,usb,yes,34,35 2006.173.18:35:45.29/va/03,05,usb,yes,44,46 2006.173.18:35:45.29/va/04,06,usb,yes,35,37 2006.173.18:35:45.29/va/05,04,usb,yes,27,28 2006.173.18:35:45.29/va/06,03,usb,yes,39,38 2006.173.18:35:45.29/va/07,04,usb,yes,31,32 2006.173.18:35:45.29/va/08,04,usb,yes,27,32 2006.173.18:35:45.52/valo/01,524.99,yes,locked 2006.173.18:35:45.53/valo/02,534.99,yes,locked 2006.173.18:35:45.53/valo/03,564.99,yes,locked 2006.173.18:35:45.53/valo/04,624.99,yes,locked 2006.173.18:35:45.53/valo/05,734.99,yes,locked 2006.173.18:35:45.53/valo/06,814.99,yes,locked 2006.173.18:35:45.53/valo/07,864.99,yes,locked 2006.173.18:35:45.53/valo/08,884.99,yes,locked 2006.173.18:35:46.61/vb/01,04,usb,yes,29,27 2006.173.18:35:46.61/vb/02,04,usb,yes,31,31 2006.173.18:35:46.61/vb/03,04,usb,yes,28,31 2006.173.18:35:46.61/vb/04,04,usb,yes,32,31 2006.173.18:35:46.61/vb/05,04,usb,yes,25,27 2006.173.18:35:46.61/vb/06,04,usb,yes,29,26 2006.173.18:35:46.61/vb/07,04,usb,yes,29,29 2006.173.18:35:46.61/vb/08,04,usb,yes,27,30 2006.173.18:35:46.85/vblo/01,629.99,yes,locked 2006.173.18:35:46.85/vblo/02,634.99,yes,locked 2006.173.18:35:46.85/vblo/03,649.99,yes,locked 2006.173.18:35:46.86/vblo/04,679.99,yes,locked 2006.173.18:35:46.86/vblo/05,709.99,yes,locked 2006.173.18:35:46.86/vblo/06,719.99,yes,locked 2006.173.18:35:46.86/vblo/07,734.99,yes,locked 2006.173.18:35:46.86/vblo/08,744.99,yes,locked 2006.173.18:35:47.00/vabw/8 2006.173.18:35:47.15/vbbw/8 2006.173.18:35:47.25/xfe/off,on,15.2 2006.173.18:35:47.63/ifatt/23,28,28,28 2006.173.18:35:48.07/fmout-gps/S +3.89E-07 2006.173.18:35:48.12:!2006.173.18:37:43 2006.173.18:37:43.01:data_valid=off 2006.173.18:37:43.02:"et 2006.173.18:37:43.02:!+3s 2006.173.18:37:46.04:"tape 2006.173.18:37:46.04:postob 2006.173.18:37:46.28/cable/+6.5163E-03 2006.173.18:37:46.29/wx/19.83,1002.3,100 2006.173.18:37:46.34/fmout-gps/S +3.88E-07 2006.173.18:37:46.35:scan_name=173-1842,jd0606,210 2006.173.18:37:46.35:source=0059+581,010245.76,582411.1,2000.0,ccw 2006.173.18:37:47.14#flagr#flagr/antenna,new-source 2006.173.18:37:47.15:checkk5 2006.173.18:37:47.57/chk_autoobs//k5ts1/ autoobs is running! 2006.173.18:37:47.96/chk_autoobs//k5ts2/ autoobs is running! 2006.173.18:37:48.35/chk_autoobs//k5ts3/ autoobs is running! 2006.173.18:37:48.75/chk_autoobs//k5ts4/ autoobs is running! 2006.173.18:37:49.14/chk_obsdata//k5ts1/T1731835??a.dat file size is correct (nominal:480MB, actual:476MB). 2006.173.18:37:49.55/chk_obsdata//k5ts2/T1731835??b.dat file size is correct (nominal:480MB, actual:476MB). 2006.173.18:37:49.96/chk_obsdata//k5ts3/T1731835??c.dat file size is correct (nominal:480MB, actual:476MB). 2006.173.18:37:50.36/chk_obsdata//k5ts4/T1731835??d.dat file size is correct (nominal:480MB, actual:476MB). 2006.173.18:37:51.08/k5log//k5ts1_log_newline 2006.173.18:37:51.78/k5log//k5ts2_log_newline 2006.173.18:37:52.49/k5log//k5ts3_log_newline 2006.173.18:37:53.20/k5log//k5ts4_log_newline 2006.173.18:37:53.23/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.18:37:53.23:setupk4=1 2006.173.18:37:53.23$setupk4/echo=on 2006.173.18:37:53.23$setupk4/pcalon 2006.173.18:37:53.23$pcalon/"no phase cal control is implemented here 2006.173.18:37:53.23$setupk4/"tpicd=stop 2006.173.18:37:53.23$setupk4/"rec=synch_on 2006.173.18:37:53.23$setupk4/"rec_mode=128 2006.173.18:37:53.23$setupk4/!* 2006.173.18:37:53.23$setupk4/recpk4 2006.173.18:37:53.23$recpk4/recpatch= 2006.173.18:37:53.23$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.18:37:53.23$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.18:37:53.23$setupk4/vck44 2006.173.18:37:53.23$vck44/valo=1,524.99 2006.173.18:37:53.23#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.18:37:53.23#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.18:37:53.23#ibcon#ireg 17 cls_cnt 0 2006.173.18:37:53.23#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.18:37:53.23#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.18:37:53.23#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.18:37:53.23#ibcon#enter wrdev, iclass 32, count 0 2006.173.18:37:53.23#ibcon#first serial, iclass 32, count 0 2006.173.18:37:53.23#ibcon#enter sib2, iclass 32, count 0 2006.173.18:37:53.23#ibcon#flushed, iclass 32, count 0 2006.173.18:37:53.23#ibcon#about to write, iclass 32, count 0 2006.173.18:37:53.23#ibcon#wrote, iclass 32, count 0 2006.173.18:37:53.23#ibcon#about to read 3, iclass 32, count 0 2006.173.18:37:53.24#ibcon#read 3, iclass 32, count 0 2006.173.18:37:53.24#ibcon#about to read 4, iclass 32, count 0 2006.173.18:37:53.24#ibcon#read 4, iclass 32, count 0 2006.173.18:37:53.24#ibcon#about to read 5, iclass 32, count 0 2006.173.18:37:53.24#ibcon#read 5, iclass 32, count 0 2006.173.18:37:53.24#ibcon#about to read 6, iclass 32, count 0 2006.173.18:37:53.24#ibcon#read 6, iclass 32, count 0 2006.173.18:37:53.24#ibcon#end of sib2, iclass 32, count 0 2006.173.18:37:53.24#ibcon#*mode == 0, iclass 32, count 0 2006.173.18:37:53.24#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.18:37:53.24#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.18:37:53.24#ibcon#*before write, iclass 32, count 0 2006.173.18:37:53.24#ibcon#enter sib2, iclass 32, count 0 2006.173.18:37:53.24#ibcon#flushed, iclass 32, count 0 2006.173.18:37:53.24#ibcon#about to write, iclass 32, count 0 2006.173.18:37:53.24#ibcon#wrote, iclass 32, count 0 2006.173.18:37:53.24#ibcon#about to read 3, iclass 32, count 0 2006.173.18:37:53.29#ibcon#read 3, iclass 32, count 0 2006.173.18:37:53.29#ibcon#about to read 4, iclass 32, count 0 2006.173.18:37:53.29#ibcon#read 4, iclass 32, count 0 2006.173.18:37:53.29#ibcon#about to read 5, iclass 32, count 0 2006.173.18:37:53.29#ibcon#read 5, iclass 32, count 0 2006.173.18:37:53.29#ibcon#about to read 6, iclass 32, count 0 2006.173.18:37:53.29#ibcon#read 6, iclass 32, count 0 2006.173.18:37:53.29#ibcon#end of sib2, iclass 32, count 0 2006.173.18:37:53.29#ibcon#*after write, iclass 32, count 0 2006.173.18:37:53.29#ibcon#*before return 0, iclass 32, count 0 2006.173.18:37:53.29#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.18:37:53.29#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.18:37:53.29#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.18:37:53.29#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.18:37:53.29$vck44/va=1,7 2006.173.18:37:53.29#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.18:37:53.29#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.18:37:53.29#ibcon#ireg 11 cls_cnt 2 2006.173.18:37:53.29#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.18:37:53.29#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.18:37:53.29#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.18:37:53.29#ibcon#enter wrdev, iclass 34, count 2 2006.173.18:37:53.29#ibcon#first serial, iclass 34, count 2 2006.173.18:37:53.29#ibcon#enter sib2, iclass 34, count 2 2006.173.18:37:53.29#ibcon#flushed, iclass 34, count 2 2006.173.18:37:53.29#ibcon#about to write, iclass 34, count 2 2006.173.18:37:53.29#ibcon#wrote, iclass 34, count 2 2006.173.18:37:53.29#ibcon#about to read 3, iclass 34, count 2 2006.173.18:37:53.31#ibcon#read 3, iclass 34, count 2 2006.173.18:37:53.31#ibcon#about to read 4, iclass 34, count 2 2006.173.18:37:53.31#ibcon#read 4, iclass 34, count 2 2006.173.18:37:53.31#ibcon#about to read 5, iclass 34, count 2 2006.173.18:37:53.31#ibcon#read 5, iclass 34, count 2 2006.173.18:37:53.31#ibcon#about to read 6, iclass 34, count 2 2006.173.18:37:53.31#ibcon#read 6, iclass 34, count 2 2006.173.18:37:53.31#ibcon#end of sib2, iclass 34, count 2 2006.173.18:37:53.31#ibcon#*mode == 0, iclass 34, count 2 2006.173.18:37:53.31#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.18:37:53.31#ibcon#[25=AT01-07\r\n] 2006.173.18:37:53.31#ibcon#*before write, iclass 34, count 2 2006.173.18:37:53.31#ibcon#enter sib2, iclass 34, count 2 2006.173.18:37:53.31#ibcon#flushed, iclass 34, count 2 2006.173.18:37:53.31#ibcon#about to write, iclass 34, count 2 2006.173.18:37:53.31#ibcon#wrote, iclass 34, count 2 2006.173.18:37:53.31#ibcon#about to read 3, iclass 34, count 2 2006.173.18:37:53.34#ibcon#read 3, iclass 34, count 2 2006.173.18:37:53.34#ibcon#about to read 4, iclass 34, count 2 2006.173.18:37:53.34#ibcon#read 4, iclass 34, count 2 2006.173.18:37:53.34#ibcon#about to read 5, iclass 34, count 2 2006.173.18:37:53.34#ibcon#read 5, iclass 34, count 2 2006.173.18:37:53.34#ibcon#about to read 6, iclass 34, count 2 2006.173.18:37:53.34#ibcon#read 6, iclass 34, count 2 2006.173.18:37:53.34#ibcon#end of sib2, iclass 34, count 2 2006.173.18:37:53.34#ibcon#*after write, iclass 34, count 2 2006.173.18:37:53.34#ibcon#*before return 0, iclass 34, count 2 2006.173.18:37:53.34#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.18:37:53.34#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.18:37:53.34#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.18:37:53.34#ibcon#ireg 7 cls_cnt 0 2006.173.18:37:53.34#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.18:37:53.46#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.18:37:53.46#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.18:37:53.46#ibcon#enter wrdev, iclass 34, count 0 2006.173.18:37:53.46#ibcon#first serial, iclass 34, count 0 2006.173.18:37:53.46#ibcon#enter sib2, iclass 34, count 0 2006.173.18:37:53.46#ibcon#flushed, iclass 34, count 0 2006.173.18:37:53.46#ibcon#about to write, iclass 34, count 0 2006.173.18:37:53.46#ibcon#wrote, iclass 34, count 0 2006.173.18:37:53.46#ibcon#about to read 3, iclass 34, count 0 2006.173.18:37:53.48#ibcon#read 3, iclass 34, count 0 2006.173.18:37:53.48#ibcon#about to read 4, iclass 34, count 0 2006.173.18:37:53.48#ibcon#read 4, iclass 34, count 0 2006.173.18:37:53.48#ibcon#about to read 5, iclass 34, count 0 2006.173.18:37:53.48#ibcon#read 5, iclass 34, count 0 2006.173.18:37:53.48#ibcon#about to read 6, iclass 34, count 0 2006.173.18:37:53.48#ibcon#read 6, iclass 34, count 0 2006.173.18:37:53.48#ibcon#end of sib2, iclass 34, count 0 2006.173.18:37:53.48#ibcon#*mode == 0, iclass 34, count 0 2006.173.18:37:53.48#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.18:37:53.48#ibcon#[25=USB\r\n] 2006.173.18:37:53.48#ibcon#*before write, iclass 34, count 0 2006.173.18:37:53.48#ibcon#enter sib2, iclass 34, count 0 2006.173.18:37:53.48#ibcon#flushed, iclass 34, count 0 2006.173.18:37:53.48#ibcon#about to write, iclass 34, count 0 2006.173.18:37:53.48#ibcon#wrote, iclass 34, count 0 2006.173.18:37:53.48#ibcon#about to read 3, iclass 34, count 0 2006.173.18:37:53.51#ibcon#read 3, iclass 34, count 0 2006.173.18:37:53.51#ibcon#about to read 4, iclass 34, count 0 2006.173.18:37:53.51#ibcon#read 4, iclass 34, count 0 2006.173.18:37:53.51#ibcon#about to read 5, iclass 34, count 0 2006.173.18:37:53.51#ibcon#read 5, iclass 34, count 0 2006.173.18:37:53.51#ibcon#about to read 6, iclass 34, count 0 2006.173.18:37:53.51#ibcon#read 6, iclass 34, count 0 2006.173.18:37:53.51#ibcon#end of sib2, iclass 34, count 0 2006.173.18:37:53.51#ibcon#*after write, iclass 34, count 0 2006.173.18:37:53.51#ibcon#*before return 0, iclass 34, count 0 2006.173.18:37:53.51#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.18:37:53.51#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.18:37:53.51#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.18:37:53.51#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.18:37:53.51$vck44/valo=2,534.99 2006.173.18:37:53.51#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.18:37:53.51#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.18:37:53.51#ibcon#ireg 17 cls_cnt 0 2006.173.18:37:53.51#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.18:37:53.51#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.18:37:53.51#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.18:37:53.51#ibcon#enter wrdev, iclass 36, count 0 2006.173.18:37:53.51#ibcon#first serial, iclass 36, count 0 2006.173.18:37:53.51#ibcon#enter sib2, iclass 36, count 0 2006.173.18:37:53.51#ibcon#flushed, iclass 36, count 0 2006.173.18:37:53.51#ibcon#about to write, iclass 36, count 0 2006.173.18:37:53.51#ibcon#wrote, iclass 36, count 0 2006.173.18:37:53.52#ibcon#about to read 3, iclass 36, count 0 2006.173.18:37:53.53#ibcon#read 3, iclass 36, count 0 2006.173.18:37:53.53#ibcon#about to read 4, iclass 36, count 0 2006.173.18:37:53.53#ibcon#read 4, iclass 36, count 0 2006.173.18:37:53.53#ibcon#about to read 5, iclass 36, count 0 2006.173.18:37:53.53#ibcon#read 5, iclass 36, count 0 2006.173.18:37:53.53#ibcon#about to read 6, iclass 36, count 0 2006.173.18:37:53.53#ibcon#read 6, iclass 36, count 0 2006.173.18:37:53.53#ibcon#end of sib2, iclass 36, count 0 2006.173.18:37:53.53#ibcon#*mode == 0, iclass 36, count 0 2006.173.18:37:53.53#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.18:37:53.53#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.18:37:53.53#ibcon#*before write, iclass 36, count 0 2006.173.18:37:53.53#ibcon#enter sib2, iclass 36, count 0 2006.173.18:37:53.53#ibcon#flushed, iclass 36, count 0 2006.173.18:37:53.53#ibcon#about to write, iclass 36, count 0 2006.173.18:37:53.53#ibcon#wrote, iclass 36, count 0 2006.173.18:37:53.53#ibcon#about to read 3, iclass 36, count 0 2006.173.18:37:53.57#ibcon#read 3, iclass 36, count 0 2006.173.18:37:53.57#ibcon#about to read 4, iclass 36, count 0 2006.173.18:37:53.57#ibcon#read 4, iclass 36, count 0 2006.173.18:37:53.57#ibcon#about to read 5, iclass 36, count 0 2006.173.18:37:53.57#ibcon#read 5, iclass 36, count 0 2006.173.18:37:53.57#ibcon#about to read 6, iclass 36, count 0 2006.173.18:37:53.57#ibcon#read 6, iclass 36, count 0 2006.173.18:37:53.57#ibcon#end of sib2, iclass 36, count 0 2006.173.18:37:53.57#ibcon#*after write, iclass 36, count 0 2006.173.18:37:53.57#ibcon#*before return 0, iclass 36, count 0 2006.173.18:37:53.57#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.18:37:53.57#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.18:37:53.57#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.18:37:53.57#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.18:37:53.57$vck44/va=2,6 2006.173.18:37:53.57#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.18:37:53.57#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.18:37:53.57#ibcon#ireg 11 cls_cnt 2 2006.173.18:37:53.57#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.18:37:53.63#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.18:37:53.63#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.18:37:53.63#ibcon#enter wrdev, iclass 38, count 2 2006.173.18:37:53.63#ibcon#first serial, iclass 38, count 2 2006.173.18:37:53.63#ibcon#enter sib2, iclass 38, count 2 2006.173.18:37:53.63#ibcon#flushed, iclass 38, count 2 2006.173.18:37:53.63#ibcon#about to write, iclass 38, count 2 2006.173.18:37:53.63#ibcon#wrote, iclass 38, count 2 2006.173.18:37:53.63#ibcon#about to read 3, iclass 38, count 2 2006.173.18:37:53.65#ibcon#read 3, iclass 38, count 2 2006.173.18:37:53.65#ibcon#about to read 4, iclass 38, count 2 2006.173.18:37:53.65#ibcon#read 4, iclass 38, count 2 2006.173.18:37:53.65#ibcon#about to read 5, iclass 38, count 2 2006.173.18:37:53.65#ibcon#read 5, iclass 38, count 2 2006.173.18:37:53.65#ibcon#about to read 6, iclass 38, count 2 2006.173.18:37:53.65#ibcon#read 6, iclass 38, count 2 2006.173.18:37:53.65#ibcon#end of sib2, iclass 38, count 2 2006.173.18:37:53.65#ibcon#*mode == 0, iclass 38, count 2 2006.173.18:37:53.65#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.18:37:53.65#ibcon#[25=AT02-06\r\n] 2006.173.18:37:53.65#ibcon#*before write, iclass 38, count 2 2006.173.18:37:53.65#ibcon#enter sib2, iclass 38, count 2 2006.173.18:37:53.65#ibcon#flushed, iclass 38, count 2 2006.173.18:37:53.65#ibcon#about to write, iclass 38, count 2 2006.173.18:37:53.65#ibcon#wrote, iclass 38, count 2 2006.173.18:37:53.65#ibcon#about to read 3, iclass 38, count 2 2006.173.18:37:53.68#ibcon#read 3, iclass 38, count 2 2006.173.18:37:53.68#ibcon#about to read 4, iclass 38, count 2 2006.173.18:37:53.68#ibcon#read 4, iclass 38, count 2 2006.173.18:37:53.68#ibcon#about to read 5, iclass 38, count 2 2006.173.18:37:53.68#ibcon#read 5, iclass 38, count 2 2006.173.18:37:53.68#ibcon#about to read 6, iclass 38, count 2 2006.173.18:37:53.68#ibcon#read 6, iclass 38, count 2 2006.173.18:37:53.68#ibcon#end of sib2, iclass 38, count 2 2006.173.18:37:53.68#ibcon#*after write, iclass 38, count 2 2006.173.18:37:53.68#ibcon#*before return 0, iclass 38, count 2 2006.173.18:37:53.68#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.18:37:53.68#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.18:37:53.68#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.18:37:53.68#ibcon#ireg 7 cls_cnt 0 2006.173.18:37:53.68#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.18:37:53.80#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.18:37:53.80#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.18:37:53.80#ibcon#enter wrdev, iclass 38, count 0 2006.173.18:37:53.80#ibcon#first serial, iclass 38, count 0 2006.173.18:37:53.80#ibcon#enter sib2, iclass 38, count 0 2006.173.18:37:53.80#ibcon#flushed, iclass 38, count 0 2006.173.18:37:53.80#ibcon#about to write, iclass 38, count 0 2006.173.18:37:53.80#ibcon#wrote, iclass 38, count 0 2006.173.18:37:53.80#ibcon#about to read 3, iclass 38, count 0 2006.173.18:37:53.82#ibcon#read 3, iclass 38, count 0 2006.173.18:37:53.82#ibcon#about to read 4, iclass 38, count 0 2006.173.18:37:53.82#ibcon#read 4, iclass 38, count 0 2006.173.18:37:53.82#ibcon#about to read 5, iclass 38, count 0 2006.173.18:37:53.82#ibcon#read 5, iclass 38, count 0 2006.173.18:37:53.82#ibcon#about to read 6, iclass 38, count 0 2006.173.18:37:53.82#ibcon#read 6, iclass 38, count 0 2006.173.18:37:53.82#ibcon#end of sib2, iclass 38, count 0 2006.173.18:37:53.82#ibcon#*mode == 0, iclass 38, count 0 2006.173.18:37:53.82#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.18:37:53.82#ibcon#[25=USB\r\n] 2006.173.18:37:53.82#ibcon#*before write, iclass 38, count 0 2006.173.18:37:53.82#ibcon#enter sib2, iclass 38, count 0 2006.173.18:37:53.82#ibcon#flushed, iclass 38, count 0 2006.173.18:37:53.82#ibcon#about to write, iclass 38, count 0 2006.173.18:37:53.82#ibcon#wrote, iclass 38, count 0 2006.173.18:37:53.82#ibcon#about to read 3, iclass 38, count 0 2006.173.18:37:53.85#ibcon#read 3, iclass 38, count 0 2006.173.18:37:53.85#ibcon#about to read 4, iclass 38, count 0 2006.173.18:37:53.85#ibcon#read 4, iclass 38, count 0 2006.173.18:37:53.85#ibcon#about to read 5, iclass 38, count 0 2006.173.18:37:53.85#ibcon#read 5, iclass 38, count 0 2006.173.18:37:53.85#ibcon#about to read 6, iclass 38, count 0 2006.173.18:37:53.85#ibcon#read 6, iclass 38, count 0 2006.173.18:37:53.85#ibcon#end of sib2, iclass 38, count 0 2006.173.18:37:53.85#ibcon#*after write, iclass 38, count 0 2006.173.18:37:53.85#ibcon#*before return 0, iclass 38, count 0 2006.173.18:37:53.85#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.18:37:53.85#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.18:37:53.85#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.18:37:53.85#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.18:37:53.85$vck44/valo=3,564.99 2006.173.18:37:53.85#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.18:37:53.85#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.18:37:53.85#ibcon#ireg 17 cls_cnt 0 2006.173.18:37:53.85#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.18:37:53.85#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.18:37:53.85#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.18:37:53.85#ibcon#enter wrdev, iclass 40, count 0 2006.173.18:37:53.85#ibcon#first serial, iclass 40, count 0 2006.173.18:37:53.85#ibcon#enter sib2, iclass 40, count 0 2006.173.18:37:53.85#ibcon#flushed, iclass 40, count 0 2006.173.18:37:53.85#ibcon#about to write, iclass 40, count 0 2006.173.18:37:53.85#ibcon#wrote, iclass 40, count 0 2006.173.18:37:53.85#ibcon#about to read 3, iclass 40, count 0 2006.173.18:37:53.87#ibcon#read 3, iclass 40, count 0 2006.173.18:37:53.87#ibcon#about to read 4, iclass 40, count 0 2006.173.18:37:53.87#ibcon#read 4, iclass 40, count 0 2006.173.18:37:53.87#ibcon#about to read 5, iclass 40, count 0 2006.173.18:37:53.87#ibcon#read 5, iclass 40, count 0 2006.173.18:37:53.87#ibcon#about to read 6, iclass 40, count 0 2006.173.18:37:53.87#ibcon#read 6, iclass 40, count 0 2006.173.18:37:53.87#ibcon#end of sib2, iclass 40, count 0 2006.173.18:37:53.87#ibcon#*mode == 0, iclass 40, count 0 2006.173.18:37:53.87#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.18:37:53.87#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.18:37:53.87#ibcon#*before write, iclass 40, count 0 2006.173.18:37:53.87#ibcon#enter sib2, iclass 40, count 0 2006.173.18:37:53.87#ibcon#flushed, iclass 40, count 0 2006.173.18:37:53.87#ibcon#about to write, iclass 40, count 0 2006.173.18:37:53.87#ibcon#wrote, iclass 40, count 0 2006.173.18:37:53.87#ibcon#about to read 3, iclass 40, count 0 2006.173.18:37:53.91#ibcon#read 3, iclass 40, count 0 2006.173.18:37:53.91#ibcon#about to read 4, iclass 40, count 0 2006.173.18:37:53.91#ibcon#read 4, iclass 40, count 0 2006.173.18:37:53.91#ibcon#about to read 5, iclass 40, count 0 2006.173.18:37:53.91#ibcon#read 5, iclass 40, count 0 2006.173.18:37:53.91#ibcon#about to read 6, iclass 40, count 0 2006.173.18:37:53.91#ibcon#read 6, iclass 40, count 0 2006.173.18:37:53.91#ibcon#end of sib2, iclass 40, count 0 2006.173.18:37:53.91#ibcon#*after write, iclass 40, count 0 2006.173.18:37:53.91#ibcon#*before return 0, iclass 40, count 0 2006.173.18:37:53.91#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.18:37:53.91#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.18:37:53.91#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.18:37:53.91#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.18:37:53.91$vck44/va=3,5 2006.173.18:37:53.91#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.18:37:53.91#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.18:37:53.91#ibcon#ireg 11 cls_cnt 2 2006.173.18:37:53.91#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.18:37:53.97#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.18:37:53.97#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.18:37:53.97#ibcon#enter wrdev, iclass 4, count 2 2006.173.18:37:53.97#ibcon#first serial, iclass 4, count 2 2006.173.18:37:53.97#ibcon#enter sib2, iclass 4, count 2 2006.173.18:37:53.97#ibcon#flushed, iclass 4, count 2 2006.173.18:37:53.97#ibcon#about to write, iclass 4, count 2 2006.173.18:37:53.97#ibcon#wrote, iclass 4, count 2 2006.173.18:37:53.97#ibcon#about to read 3, iclass 4, count 2 2006.173.18:37:53.99#ibcon#read 3, iclass 4, count 2 2006.173.18:37:53.99#ibcon#about to read 4, iclass 4, count 2 2006.173.18:37:53.99#ibcon#read 4, iclass 4, count 2 2006.173.18:37:53.99#ibcon#about to read 5, iclass 4, count 2 2006.173.18:37:53.99#ibcon#read 5, iclass 4, count 2 2006.173.18:37:53.99#ibcon#about to read 6, iclass 4, count 2 2006.173.18:37:53.99#ibcon#read 6, iclass 4, count 2 2006.173.18:37:53.99#ibcon#end of sib2, iclass 4, count 2 2006.173.18:37:53.99#ibcon#*mode == 0, iclass 4, count 2 2006.173.18:37:53.99#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.18:37:53.99#ibcon#[25=AT03-05\r\n] 2006.173.18:37:53.99#ibcon#*before write, iclass 4, count 2 2006.173.18:37:53.99#ibcon#enter sib2, iclass 4, count 2 2006.173.18:37:53.99#ibcon#flushed, iclass 4, count 2 2006.173.18:37:53.99#ibcon#about to write, iclass 4, count 2 2006.173.18:37:53.99#ibcon#wrote, iclass 4, count 2 2006.173.18:37:53.99#ibcon#about to read 3, iclass 4, count 2 2006.173.18:37:54.02#ibcon#read 3, iclass 4, count 2 2006.173.18:37:54.02#ibcon#about to read 4, iclass 4, count 2 2006.173.18:37:54.02#ibcon#read 4, iclass 4, count 2 2006.173.18:37:54.02#ibcon#about to read 5, iclass 4, count 2 2006.173.18:37:54.02#ibcon#read 5, iclass 4, count 2 2006.173.18:37:54.02#ibcon#about to read 6, iclass 4, count 2 2006.173.18:37:54.02#ibcon#read 6, iclass 4, count 2 2006.173.18:37:54.02#ibcon#end of sib2, iclass 4, count 2 2006.173.18:37:54.02#ibcon#*after write, iclass 4, count 2 2006.173.18:37:54.02#ibcon#*before return 0, iclass 4, count 2 2006.173.18:37:54.02#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.18:37:54.02#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.18:37:54.02#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.18:37:54.02#ibcon#ireg 7 cls_cnt 0 2006.173.18:37:54.02#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.18:37:54.14#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.18:37:54.14#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.18:37:54.14#ibcon#enter wrdev, iclass 4, count 0 2006.173.18:37:54.14#ibcon#first serial, iclass 4, count 0 2006.173.18:37:54.15#ibcon#enter sib2, iclass 4, count 0 2006.173.18:37:54.15#ibcon#flushed, iclass 4, count 0 2006.173.18:37:54.15#ibcon#about to write, iclass 4, count 0 2006.173.18:37:54.15#ibcon#wrote, iclass 4, count 0 2006.173.18:37:54.15#ibcon#about to read 3, iclass 4, count 0 2006.173.18:37:54.16#ibcon#read 3, iclass 4, count 0 2006.173.18:37:54.16#ibcon#about to read 4, iclass 4, count 0 2006.173.18:37:54.16#ibcon#read 4, iclass 4, count 0 2006.173.18:37:54.16#ibcon#about to read 5, iclass 4, count 0 2006.173.18:37:54.16#ibcon#read 5, iclass 4, count 0 2006.173.18:37:54.16#ibcon#about to read 6, iclass 4, count 0 2006.173.18:37:54.16#ibcon#read 6, iclass 4, count 0 2006.173.18:37:54.16#ibcon#end of sib2, iclass 4, count 0 2006.173.18:37:54.16#ibcon#*mode == 0, iclass 4, count 0 2006.173.18:37:54.16#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.18:37:54.16#ibcon#[25=USB\r\n] 2006.173.18:37:54.16#ibcon#*before write, iclass 4, count 0 2006.173.18:37:54.16#ibcon#enter sib2, iclass 4, count 0 2006.173.18:37:54.16#ibcon#flushed, iclass 4, count 0 2006.173.18:37:54.16#ibcon#about to write, iclass 4, count 0 2006.173.18:37:54.16#ibcon#wrote, iclass 4, count 0 2006.173.18:37:54.16#ibcon#about to read 3, iclass 4, count 0 2006.173.18:37:54.19#ibcon#read 3, iclass 4, count 0 2006.173.18:37:54.19#ibcon#about to read 4, iclass 4, count 0 2006.173.18:37:54.19#ibcon#read 4, iclass 4, count 0 2006.173.18:37:54.19#ibcon#about to read 5, iclass 4, count 0 2006.173.18:37:54.19#ibcon#read 5, iclass 4, count 0 2006.173.18:37:54.19#ibcon#about to read 6, iclass 4, count 0 2006.173.18:37:54.19#ibcon#read 6, iclass 4, count 0 2006.173.18:37:54.19#ibcon#end of sib2, iclass 4, count 0 2006.173.18:37:54.19#ibcon#*after write, iclass 4, count 0 2006.173.18:37:54.19#ibcon#*before return 0, iclass 4, count 0 2006.173.18:37:54.19#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.18:37:54.19#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.18:37:54.19#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.18:37:54.19#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.18:37:54.19$vck44/valo=4,624.99 2006.173.18:37:54.19#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.18:37:54.19#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.18:37:54.19#ibcon#ireg 17 cls_cnt 0 2006.173.18:37:54.19#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.18:37:54.19#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.18:37:54.19#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.18:37:54.19#ibcon#enter wrdev, iclass 6, count 0 2006.173.18:37:54.19#ibcon#first serial, iclass 6, count 0 2006.173.18:37:54.19#ibcon#enter sib2, iclass 6, count 0 2006.173.18:37:54.19#ibcon#flushed, iclass 6, count 0 2006.173.18:37:54.19#ibcon#about to write, iclass 6, count 0 2006.173.18:37:54.19#ibcon#wrote, iclass 6, count 0 2006.173.18:37:54.19#ibcon#about to read 3, iclass 6, count 0 2006.173.18:37:54.21#ibcon#read 3, iclass 6, count 0 2006.173.18:37:54.21#ibcon#about to read 4, iclass 6, count 0 2006.173.18:37:54.21#ibcon#read 4, iclass 6, count 0 2006.173.18:37:54.21#ibcon#about to read 5, iclass 6, count 0 2006.173.18:37:54.21#ibcon#read 5, iclass 6, count 0 2006.173.18:37:54.21#ibcon#about to read 6, iclass 6, count 0 2006.173.18:37:54.21#ibcon#read 6, iclass 6, count 0 2006.173.18:37:54.21#ibcon#end of sib2, iclass 6, count 0 2006.173.18:37:54.21#ibcon#*mode == 0, iclass 6, count 0 2006.173.18:37:54.21#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.18:37:54.21#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.18:37:54.21#ibcon#*before write, iclass 6, count 0 2006.173.18:37:54.21#ibcon#enter sib2, iclass 6, count 0 2006.173.18:37:54.21#ibcon#flushed, iclass 6, count 0 2006.173.18:37:54.21#ibcon#about to write, iclass 6, count 0 2006.173.18:37:54.21#ibcon#wrote, iclass 6, count 0 2006.173.18:37:54.21#ibcon#about to read 3, iclass 6, count 0 2006.173.18:37:54.25#ibcon#read 3, iclass 6, count 0 2006.173.18:37:54.25#ibcon#about to read 4, iclass 6, count 0 2006.173.18:37:54.25#ibcon#read 4, iclass 6, count 0 2006.173.18:37:54.25#ibcon#about to read 5, iclass 6, count 0 2006.173.18:37:54.25#ibcon#read 5, iclass 6, count 0 2006.173.18:37:54.25#ibcon#about to read 6, iclass 6, count 0 2006.173.18:37:54.25#ibcon#read 6, iclass 6, count 0 2006.173.18:37:54.25#ibcon#end of sib2, iclass 6, count 0 2006.173.18:37:54.25#ibcon#*after write, iclass 6, count 0 2006.173.18:37:54.25#ibcon#*before return 0, iclass 6, count 0 2006.173.18:37:54.25#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.18:37:54.25#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.18:37:54.25#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.18:37:54.25#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.18:37:54.25$vck44/va=4,6 2006.173.18:37:54.25#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.18:37:54.25#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.18:37:54.25#ibcon#ireg 11 cls_cnt 2 2006.173.18:37:54.25#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.18:37:54.31#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.18:37:54.31#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.18:37:54.31#ibcon#enter wrdev, iclass 10, count 2 2006.173.18:37:54.31#ibcon#first serial, iclass 10, count 2 2006.173.18:37:54.31#ibcon#enter sib2, iclass 10, count 2 2006.173.18:37:54.31#ibcon#flushed, iclass 10, count 2 2006.173.18:37:54.31#ibcon#about to write, iclass 10, count 2 2006.173.18:37:54.31#ibcon#wrote, iclass 10, count 2 2006.173.18:37:54.31#ibcon#about to read 3, iclass 10, count 2 2006.173.18:37:54.33#ibcon#read 3, iclass 10, count 2 2006.173.18:37:54.33#ibcon#about to read 4, iclass 10, count 2 2006.173.18:37:54.33#ibcon#read 4, iclass 10, count 2 2006.173.18:37:54.33#ibcon#about to read 5, iclass 10, count 2 2006.173.18:37:54.33#ibcon#read 5, iclass 10, count 2 2006.173.18:37:54.33#ibcon#about to read 6, iclass 10, count 2 2006.173.18:37:54.33#ibcon#read 6, iclass 10, count 2 2006.173.18:37:54.33#ibcon#end of sib2, iclass 10, count 2 2006.173.18:37:54.33#ibcon#*mode == 0, iclass 10, count 2 2006.173.18:37:54.33#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.18:37:54.33#ibcon#[25=AT04-06\r\n] 2006.173.18:37:54.33#ibcon#*before write, iclass 10, count 2 2006.173.18:37:54.33#ibcon#enter sib2, iclass 10, count 2 2006.173.18:37:54.33#ibcon#flushed, iclass 10, count 2 2006.173.18:37:54.33#ibcon#about to write, iclass 10, count 2 2006.173.18:37:54.33#ibcon#wrote, iclass 10, count 2 2006.173.18:37:54.33#ibcon#about to read 3, iclass 10, count 2 2006.173.18:37:54.36#ibcon#read 3, iclass 10, count 2 2006.173.18:37:54.36#ibcon#about to read 4, iclass 10, count 2 2006.173.18:37:54.36#ibcon#read 4, iclass 10, count 2 2006.173.18:37:54.36#ibcon#about to read 5, iclass 10, count 2 2006.173.18:37:54.36#ibcon#read 5, iclass 10, count 2 2006.173.18:37:54.36#ibcon#about to read 6, iclass 10, count 2 2006.173.18:37:54.36#ibcon#read 6, iclass 10, count 2 2006.173.18:37:54.36#ibcon#end of sib2, iclass 10, count 2 2006.173.18:37:54.36#ibcon#*after write, iclass 10, count 2 2006.173.18:37:54.36#ibcon#*before return 0, iclass 10, count 2 2006.173.18:37:54.36#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.18:37:54.36#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.18:37:54.36#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.18:37:54.36#ibcon#ireg 7 cls_cnt 0 2006.173.18:37:54.36#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.18:37:54.48#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.18:37:54.48#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.18:37:54.48#ibcon#enter wrdev, iclass 10, count 0 2006.173.18:37:54.48#ibcon#first serial, iclass 10, count 0 2006.173.18:37:54.48#ibcon#enter sib2, iclass 10, count 0 2006.173.18:37:54.48#ibcon#flushed, iclass 10, count 0 2006.173.18:37:54.48#ibcon#about to write, iclass 10, count 0 2006.173.18:37:54.48#ibcon#wrote, iclass 10, count 0 2006.173.18:37:54.48#ibcon#about to read 3, iclass 10, count 0 2006.173.18:37:54.50#ibcon#read 3, iclass 10, count 0 2006.173.18:37:54.50#ibcon#about to read 4, iclass 10, count 0 2006.173.18:37:54.50#ibcon#read 4, iclass 10, count 0 2006.173.18:37:54.50#ibcon#about to read 5, iclass 10, count 0 2006.173.18:37:54.50#ibcon#read 5, iclass 10, count 0 2006.173.18:37:54.50#ibcon#about to read 6, iclass 10, count 0 2006.173.18:37:54.50#ibcon#read 6, iclass 10, count 0 2006.173.18:37:54.50#ibcon#end of sib2, iclass 10, count 0 2006.173.18:37:54.50#ibcon#*mode == 0, iclass 10, count 0 2006.173.18:37:54.50#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.18:37:54.50#ibcon#[25=USB\r\n] 2006.173.18:37:54.50#ibcon#*before write, iclass 10, count 0 2006.173.18:37:54.50#ibcon#enter sib2, iclass 10, count 0 2006.173.18:37:54.50#ibcon#flushed, iclass 10, count 0 2006.173.18:37:54.50#ibcon#about to write, iclass 10, count 0 2006.173.18:37:54.50#ibcon#wrote, iclass 10, count 0 2006.173.18:37:54.50#ibcon#about to read 3, iclass 10, count 0 2006.173.18:37:54.53#ibcon#read 3, iclass 10, count 0 2006.173.18:37:54.53#ibcon#about to read 4, iclass 10, count 0 2006.173.18:37:54.53#ibcon#read 4, iclass 10, count 0 2006.173.18:37:54.53#ibcon#about to read 5, iclass 10, count 0 2006.173.18:37:54.53#ibcon#read 5, iclass 10, count 0 2006.173.18:37:54.53#ibcon#about to read 6, iclass 10, count 0 2006.173.18:37:54.53#ibcon#read 6, iclass 10, count 0 2006.173.18:37:54.53#ibcon#end of sib2, iclass 10, count 0 2006.173.18:37:54.53#ibcon#*after write, iclass 10, count 0 2006.173.18:37:54.53#ibcon#*before return 0, iclass 10, count 0 2006.173.18:37:54.53#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.18:37:54.53#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.18:37:54.53#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.18:37:54.53#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.18:37:54.53$vck44/valo=5,734.99 2006.173.18:37:54.53#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.18:37:54.53#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.18:37:54.53#ibcon#ireg 17 cls_cnt 0 2006.173.18:37:54.53#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.18:37:54.53#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.18:37:54.53#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.18:37:54.53#ibcon#enter wrdev, iclass 12, count 0 2006.173.18:37:54.53#ibcon#first serial, iclass 12, count 0 2006.173.18:37:54.53#ibcon#enter sib2, iclass 12, count 0 2006.173.18:37:54.53#ibcon#flushed, iclass 12, count 0 2006.173.18:37:54.53#ibcon#about to write, iclass 12, count 0 2006.173.18:37:54.53#ibcon#wrote, iclass 12, count 0 2006.173.18:37:54.53#ibcon#about to read 3, iclass 12, count 0 2006.173.18:37:54.55#ibcon#read 3, iclass 12, count 0 2006.173.18:37:54.55#ibcon#about to read 4, iclass 12, count 0 2006.173.18:37:54.55#ibcon#read 4, iclass 12, count 0 2006.173.18:37:54.55#ibcon#about to read 5, iclass 12, count 0 2006.173.18:37:54.55#ibcon#read 5, iclass 12, count 0 2006.173.18:37:54.55#ibcon#about to read 6, iclass 12, count 0 2006.173.18:37:54.55#ibcon#read 6, iclass 12, count 0 2006.173.18:37:54.55#ibcon#end of sib2, iclass 12, count 0 2006.173.18:37:54.55#ibcon#*mode == 0, iclass 12, count 0 2006.173.18:37:54.55#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.18:37:54.55#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.18:37:54.55#ibcon#*before write, iclass 12, count 0 2006.173.18:37:54.55#ibcon#enter sib2, iclass 12, count 0 2006.173.18:37:54.55#ibcon#flushed, iclass 12, count 0 2006.173.18:37:54.55#ibcon#about to write, iclass 12, count 0 2006.173.18:37:54.55#ibcon#wrote, iclass 12, count 0 2006.173.18:37:54.55#ibcon#about to read 3, iclass 12, count 0 2006.173.18:37:54.59#ibcon#read 3, iclass 12, count 0 2006.173.18:37:54.59#ibcon#about to read 4, iclass 12, count 0 2006.173.18:37:54.59#ibcon#read 4, iclass 12, count 0 2006.173.18:37:54.59#ibcon#about to read 5, iclass 12, count 0 2006.173.18:37:54.59#ibcon#read 5, iclass 12, count 0 2006.173.18:37:54.59#ibcon#about to read 6, iclass 12, count 0 2006.173.18:37:54.59#ibcon#read 6, iclass 12, count 0 2006.173.18:37:54.59#ibcon#end of sib2, iclass 12, count 0 2006.173.18:37:54.59#ibcon#*after write, iclass 12, count 0 2006.173.18:37:54.59#ibcon#*before return 0, iclass 12, count 0 2006.173.18:37:54.59#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.18:37:54.59#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.18:37:54.59#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.18:37:54.59#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.18:37:54.59$vck44/va=5,4 2006.173.18:37:54.59#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.18:37:54.59#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.18:37:54.59#ibcon#ireg 11 cls_cnt 2 2006.173.18:37:54.59#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.18:37:54.65#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.18:37:54.65#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.18:37:54.65#ibcon#enter wrdev, iclass 14, count 2 2006.173.18:37:54.65#ibcon#first serial, iclass 14, count 2 2006.173.18:37:54.65#ibcon#enter sib2, iclass 14, count 2 2006.173.18:37:54.65#ibcon#flushed, iclass 14, count 2 2006.173.18:37:54.65#ibcon#about to write, iclass 14, count 2 2006.173.18:37:54.65#ibcon#wrote, iclass 14, count 2 2006.173.18:37:54.65#ibcon#about to read 3, iclass 14, count 2 2006.173.18:37:54.67#ibcon#read 3, iclass 14, count 2 2006.173.18:37:54.67#ibcon#about to read 4, iclass 14, count 2 2006.173.18:37:54.67#ibcon#read 4, iclass 14, count 2 2006.173.18:37:54.67#ibcon#about to read 5, iclass 14, count 2 2006.173.18:37:54.67#ibcon#read 5, iclass 14, count 2 2006.173.18:37:54.67#ibcon#about to read 6, iclass 14, count 2 2006.173.18:37:54.67#ibcon#read 6, iclass 14, count 2 2006.173.18:37:54.67#ibcon#end of sib2, iclass 14, count 2 2006.173.18:37:54.67#ibcon#*mode == 0, iclass 14, count 2 2006.173.18:37:54.67#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.18:37:54.67#ibcon#[25=AT05-04\r\n] 2006.173.18:37:54.67#ibcon#*before write, iclass 14, count 2 2006.173.18:37:54.67#ibcon#enter sib2, iclass 14, count 2 2006.173.18:37:54.67#ibcon#flushed, iclass 14, count 2 2006.173.18:37:54.67#ibcon#about to write, iclass 14, count 2 2006.173.18:37:54.67#ibcon#wrote, iclass 14, count 2 2006.173.18:37:54.67#ibcon#about to read 3, iclass 14, count 2 2006.173.18:37:54.70#ibcon#read 3, iclass 14, count 2 2006.173.18:37:54.70#ibcon#about to read 4, iclass 14, count 2 2006.173.18:37:54.70#ibcon#read 4, iclass 14, count 2 2006.173.18:37:54.70#ibcon#about to read 5, iclass 14, count 2 2006.173.18:37:54.70#ibcon#read 5, iclass 14, count 2 2006.173.18:37:54.70#ibcon#about to read 6, iclass 14, count 2 2006.173.18:37:54.70#ibcon#read 6, iclass 14, count 2 2006.173.18:37:54.70#ibcon#end of sib2, iclass 14, count 2 2006.173.18:37:54.70#ibcon#*after write, iclass 14, count 2 2006.173.18:37:54.70#ibcon#*before return 0, iclass 14, count 2 2006.173.18:37:54.70#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.18:37:54.70#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.18:37:54.70#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.18:37:54.70#ibcon#ireg 7 cls_cnt 0 2006.173.18:37:54.70#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.18:37:54.82#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.18:37:54.82#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.18:37:54.82#ibcon#enter wrdev, iclass 14, count 0 2006.173.18:37:54.82#ibcon#first serial, iclass 14, count 0 2006.173.18:37:54.82#ibcon#enter sib2, iclass 14, count 0 2006.173.18:37:54.82#ibcon#flushed, iclass 14, count 0 2006.173.18:37:54.82#ibcon#about to write, iclass 14, count 0 2006.173.18:37:54.82#ibcon#wrote, iclass 14, count 0 2006.173.18:37:54.82#ibcon#about to read 3, iclass 14, count 0 2006.173.18:37:54.84#ibcon#read 3, iclass 14, count 0 2006.173.18:37:54.84#ibcon#about to read 4, iclass 14, count 0 2006.173.18:37:54.84#ibcon#read 4, iclass 14, count 0 2006.173.18:37:54.84#ibcon#about to read 5, iclass 14, count 0 2006.173.18:37:54.84#ibcon#read 5, iclass 14, count 0 2006.173.18:37:54.84#ibcon#about to read 6, iclass 14, count 0 2006.173.18:37:54.84#ibcon#read 6, iclass 14, count 0 2006.173.18:37:54.84#ibcon#end of sib2, iclass 14, count 0 2006.173.18:37:54.84#ibcon#*mode == 0, iclass 14, count 0 2006.173.18:37:54.84#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.18:37:54.84#ibcon#[25=USB\r\n] 2006.173.18:37:54.84#ibcon#*before write, iclass 14, count 0 2006.173.18:37:54.84#ibcon#enter sib2, iclass 14, count 0 2006.173.18:37:54.84#ibcon#flushed, iclass 14, count 0 2006.173.18:37:54.84#ibcon#about to write, iclass 14, count 0 2006.173.18:37:54.84#ibcon#wrote, iclass 14, count 0 2006.173.18:37:54.84#ibcon#about to read 3, iclass 14, count 0 2006.173.18:37:54.87#ibcon#read 3, iclass 14, count 0 2006.173.18:37:54.87#ibcon#about to read 4, iclass 14, count 0 2006.173.18:37:54.87#ibcon#read 4, iclass 14, count 0 2006.173.18:37:54.87#ibcon#about to read 5, iclass 14, count 0 2006.173.18:37:54.87#ibcon#read 5, iclass 14, count 0 2006.173.18:37:54.87#ibcon#about to read 6, iclass 14, count 0 2006.173.18:37:54.87#ibcon#read 6, iclass 14, count 0 2006.173.18:37:54.87#ibcon#end of sib2, iclass 14, count 0 2006.173.18:37:54.87#ibcon#*after write, iclass 14, count 0 2006.173.18:37:54.87#ibcon#*before return 0, iclass 14, count 0 2006.173.18:37:54.87#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.18:37:54.87#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.18:37:54.87#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.18:37:54.87#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.18:37:54.87$vck44/valo=6,814.99 2006.173.18:37:54.87#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.18:37:54.87#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.18:37:54.87#ibcon#ireg 17 cls_cnt 0 2006.173.18:37:54.87#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.18:37:54.87#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.18:37:54.87#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.18:37:54.87#ibcon#enter wrdev, iclass 16, count 0 2006.173.18:37:54.87#ibcon#first serial, iclass 16, count 0 2006.173.18:37:54.87#ibcon#enter sib2, iclass 16, count 0 2006.173.18:37:54.87#ibcon#flushed, iclass 16, count 0 2006.173.18:37:54.87#ibcon#about to write, iclass 16, count 0 2006.173.18:37:54.87#ibcon#wrote, iclass 16, count 0 2006.173.18:37:54.87#ibcon#about to read 3, iclass 16, count 0 2006.173.18:37:54.89#ibcon#read 3, iclass 16, count 0 2006.173.18:37:54.89#ibcon#about to read 4, iclass 16, count 0 2006.173.18:37:54.89#ibcon#read 4, iclass 16, count 0 2006.173.18:37:54.89#ibcon#about to read 5, iclass 16, count 0 2006.173.18:37:54.89#ibcon#read 5, iclass 16, count 0 2006.173.18:37:54.89#ibcon#about to read 6, iclass 16, count 0 2006.173.18:37:54.89#ibcon#read 6, iclass 16, count 0 2006.173.18:37:54.89#ibcon#end of sib2, iclass 16, count 0 2006.173.18:37:54.89#ibcon#*mode == 0, iclass 16, count 0 2006.173.18:37:54.89#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.18:37:54.89#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.18:37:54.89#ibcon#*before write, iclass 16, count 0 2006.173.18:37:54.89#ibcon#enter sib2, iclass 16, count 0 2006.173.18:37:54.89#ibcon#flushed, iclass 16, count 0 2006.173.18:37:54.89#ibcon#about to write, iclass 16, count 0 2006.173.18:37:54.89#ibcon#wrote, iclass 16, count 0 2006.173.18:37:54.89#ibcon#about to read 3, iclass 16, count 0 2006.173.18:37:54.93#ibcon#read 3, iclass 16, count 0 2006.173.18:37:54.93#ibcon#about to read 4, iclass 16, count 0 2006.173.18:37:54.93#ibcon#read 4, iclass 16, count 0 2006.173.18:37:54.93#ibcon#about to read 5, iclass 16, count 0 2006.173.18:37:54.93#ibcon#read 5, iclass 16, count 0 2006.173.18:37:54.93#ibcon#about to read 6, iclass 16, count 0 2006.173.18:37:54.93#ibcon#read 6, iclass 16, count 0 2006.173.18:37:54.93#ibcon#end of sib2, iclass 16, count 0 2006.173.18:37:54.93#ibcon#*after write, iclass 16, count 0 2006.173.18:37:54.93#ibcon#*before return 0, iclass 16, count 0 2006.173.18:37:54.93#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.18:37:54.93#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.18:37:54.93#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.18:37:54.93#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.18:37:54.93$vck44/va=6,3 2006.173.18:37:54.93#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.18:37:54.93#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.18:37:54.93#ibcon#ireg 11 cls_cnt 2 2006.173.18:37:54.93#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.18:37:54.99#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.18:37:54.99#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.18:37:54.99#ibcon#enter wrdev, iclass 18, count 2 2006.173.18:37:54.99#ibcon#first serial, iclass 18, count 2 2006.173.18:37:54.99#ibcon#enter sib2, iclass 18, count 2 2006.173.18:37:54.99#ibcon#flushed, iclass 18, count 2 2006.173.18:37:54.99#ibcon#about to write, iclass 18, count 2 2006.173.18:37:54.99#ibcon#wrote, iclass 18, count 2 2006.173.18:37:54.99#ibcon#about to read 3, iclass 18, count 2 2006.173.18:37:55.01#ibcon#read 3, iclass 18, count 2 2006.173.18:37:55.01#ibcon#about to read 4, iclass 18, count 2 2006.173.18:37:55.01#ibcon#read 4, iclass 18, count 2 2006.173.18:37:55.01#ibcon#about to read 5, iclass 18, count 2 2006.173.18:37:55.01#ibcon#read 5, iclass 18, count 2 2006.173.18:37:55.01#ibcon#about to read 6, iclass 18, count 2 2006.173.18:37:55.01#ibcon#read 6, iclass 18, count 2 2006.173.18:37:55.01#ibcon#end of sib2, iclass 18, count 2 2006.173.18:37:55.01#ibcon#*mode == 0, iclass 18, count 2 2006.173.18:37:55.01#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.18:37:55.01#ibcon#[25=AT06-03\r\n] 2006.173.18:37:55.01#ibcon#*before write, iclass 18, count 2 2006.173.18:37:55.01#ibcon#enter sib2, iclass 18, count 2 2006.173.18:37:55.01#ibcon#flushed, iclass 18, count 2 2006.173.18:37:55.01#ibcon#about to write, iclass 18, count 2 2006.173.18:37:55.01#ibcon#wrote, iclass 18, count 2 2006.173.18:37:55.01#ibcon#about to read 3, iclass 18, count 2 2006.173.18:37:55.01#abcon#<5=/14 1.0 1.9 19.821001002.3\r\n> 2006.173.18:37:55.03#abcon#{5=INTERFACE CLEAR} 2006.173.18:37:55.04#ibcon#read 3, iclass 18, count 2 2006.173.18:37:55.04#ibcon#about to read 4, iclass 18, count 2 2006.173.18:37:55.04#ibcon#read 4, iclass 18, count 2 2006.173.18:37:55.04#ibcon#about to read 5, iclass 18, count 2 2006.173.18:37:55.04#ibcon#read 5, iclass 18, count 2 2006.173.18:37:55.04#ibcon#about to read 6, iclass 18, count 2 2006.173.18:37:55.04#ibcon#read 6, iclass 18, count 2 2006.173.18:37:55.04#ibcon#end of sib2, iclass 18, count 2 2006.173.18:37:55.04#ibcon#*after write, iclass 18, count 2 2006.173.18:37:55.04#ibcon#*before return 0, iclass 18, count 2 2006.173.18:37:55.04#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.18:37:55.04#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.18:37:55.04#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.18:37:55.04#ibcon#ireg 7 cls_cnt 0 2006.173.18:37:55.04#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.18:37:55.09#abcon#[5=S1D000X0/0*\r\n] 2006.173.18:37:55.16#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.18:37:55.16#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.18:37:55.16#ibcon#enter wrdev, iclass 18, count 0 2006.173.18:37:55.16#ibcon#first serial, iclass 18, count 0 2006.173.18:37:55.16#ibcon#enter sib2, iclass 18, count 0 2006.173.18:37:55.16#ibcon#flushed, iclass 18, count 0 2006.173.18:37:55.16#ibcon#about to write, iclass 18, count 0 2006.173.18:37:55.16#ibcon#wrote, iclass 18, count 0 2006.173.18:37:55.16#ibcon#about to read 3, iclass 18, count 0 2006.173.18:37:55.18#ibcon#read 3, iclass 18, count 0 2006.173.18:37:55.18#ibcon#about to read 4, iclass 18, count 0 2006.173.18:37:55.18#ibcon#read 4, iclass 18, count 0 2006.173.18:37:55.18#ibcon#about to read 5, iclass 18, count 0 2006.173.18:37:55.18#ibcon#read 5, iclass 18, count 0 2006.173.18:37:55.18#ibcon#about to read 6, iclass 18, count 0 2006.173.18:37:55.18#ibcon#read 6, iclass 18, count 0 2006.173.18:37:55.18#ibcon#end of sib2, iclass 18, count 0 2006.173.18:37:55.18#ibcon#*mode == 0, iclass 18, count 0 2006.173.18:37:55.18#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.18:37:55.18#ibcon#[25=USB\r\n] 2006.173.18:37:55.18#ibcon#*before write, iclass 18, count 0 2006.173.18:37:55.18#ibcon#enter sib2, iclass 18, count 0 2006.173.18:37:55.18#ibcon#flushed, iclass 18, count 0 2006.173.18:37:55.18#ibcon#about to write, iclass 18, count 0 2006.173.18:37:55.18#ibcon#wrote, iclass 18, count 0 2006.173.18:37:55.18#ibcon#about to read 3, iclass 18, count 0 2006.173.18:37:55.21#ibcon#read 3, iclass 18, count 0 2006.173.18:37:55.21#ibcon#about to read 4, iclass 18, count 0 2006.173.18:37:55.21#ibcon#read 4, iclass 18, count 0 2006.173.18:37:55.21#ibcon#about to read 5, iclass 18, count 0 2006.173.18:37:55.21#ibcon#read 5, iclass 18, count 0 2006.173.18:37:55.21#ibcon#about to read 6, iclass 18, count 0 2006.173.18:37:55.21#ibcon#read 6, iclass 18, count 0 2006.173.18:37:55.21#ibcon#end of sib2, iclass 18, count 0 2006.173.18:37:55.21#ibcon#*after write, iclass 18, count 0 2006.173.18:37:55.21#ibcon#*before return 0, iclass 18, count 0 2006.173.18:37:55.21#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.18:37:55.21#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.18:37:55.21#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.18:37:55.21#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.18:37:55.21$vck44/valo=7,864.99 2006.173.18:37:55.21#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.18:37:55.21#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.18:37:55.21#ibcon#ireg 17 cls_cnt 0 2006.173.18:37:55.21#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.18:37:55.21#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.18:37:55.21#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.18:37:55.21#ibcon#enter wrdev, iclass 24, count 0 2006.173.18:37:55.21#ibcon#first serial, iclass 24, count 0 2006.173.18:37:55.21#ibcon#enter sib2, iclass 24, count 0 2006.173.18:37:55.21#ibcon#flushed, iclass 24, count 0 2006.173.18:37:55.21#ibcon#about to write, iclass 24, count 0 2006.173.18:37:55.21#ibcon#wrote, iclass 24, count 0 2006.173.18:37:55.21#ibcon#about to read 3, iclass 24, count 0 2006.173.18:37:55.23#ibcon#read 3, iclass 24, count 0 2006.173.18:37:55.23#ibcon#about to read 4, iclass 24, count 0 2006.173.18:37:55.23#ibcon#read 4, iclass 24, count 0 2006.173.18:37:55.23#ibcon#about to read 5, iclass 24, count 0 2006.173.18:37:55.23#ibcon#read 5, iclass 24, count 0 2006.173.18:37:55.23#ibcon#about to read 6, iclass 24, count 0 2006.173.18:37:55.23#ibcon#read 6, iclass 24, count 0 2006.173.18:37:55.23#ibcon#end of sib2, iclass 24, count 0 2006.173.18:37:55.23#ibcon#*mode == 0, iclass 24, count 0 2006.173.18:37:55.23#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.18:37:55.23#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.18:37:55.23#ibcon#*before write, iclass 24, count 0 2006.173.18:37:55.23#ibcon#enter sib2, iclass 24, count 0 2006.173.18:37:55.23#ibcon#flushed, iclass 24, count 0 2006.173.18:37:55.23#ibcon#about to write, iclass 24, count 0 2006.173.18:37:55.23#ibcon#wrote, iclass 24, count 0 2006.173.18:37:55.23#ibcon#about to read 3, iclass 24, count 0 2006.173.18:37:55.27#ibcon#read 3, iclass 24, count 0 2006.173.18:37:55.27#ibcon#about to read 4, iclass 24, count 0 2006.173.18:37:55.27#ibcon#read 4, iclass 24, count 0 2006.173.18:37:55.27#ibcon#about to read 5, iclass 24, count 0 2006.173.18:37:55.27#ibcon#read 5, iclass 24, count 0 2006.173.18:37:55.27#ibcon#about to read 6, iclass 24, count 0 2006.173.18:37:55.27#ibcon#read 6, iclass 24, count 0 2006.173.18:37:55.27#ibcon#end of sib2, iclass 24, count 0 2006.173.18:37:55.27#ibcon#*after write, iclass 24, count 0 2006.173.18:37:55.27#ibcon#*before return 0, iclass 24, count 0 2006.173.18:37:55.27#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.18:37:55.27#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.18:37:55.27#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.18:37:55.27#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.18:37:55.27$vck44/va=7,4 2006.173.18:37:55.27#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.18:37:55.27#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.18:37:55.27#ibcon#ireg 11 cls_cnt 2 2006.173.18:37:55.27#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.18:37:55.33#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.18:37:55.33#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.18:37:55.33#ibcon#enter wrdev, iclass 26, count 2 2006.173.18:37:55.33#ibcon#first serial, iclass 26, count 2 2006.173.18:37:55.33#ibcon#enter sib2, iclass 26, count 2 2006.173.18:37:55.33#ibcon#flushed, iclass 26, count 2 2006.173.18:37:55.33#ibcon#about to write, iclass 26, count 2 2006.173.18:37:55.33#ibcon#wrote, iclass 26, count 2 2006.173.18:37:55.33#ibcon#about to read 3, iclass 26, count 2 2006.173.18:37:55.35#ibcon#read 3, iclass 26, count 2 2006.173.18:37:55.35#ibcon#about to read 4, iclass 26, count 2 2006.173.18:37:55.35#ibcon#read 4, iclass 26, count 2 2006.173.18:37:55.35#ibcon#about to read 5, iclass 26, count 2 2006.173.18:37:55.35#ibcon#read 5, iclass 26, count 2 2006.173.18:37:55.35#ibcon#about to read 6, iclass 26, count 2 2006.173.18:37:55.35#ibcon#read 6, iclass 26, count 2 2006.173.18:37:55.35#ibcon#end of sib2, iclass 26, count 2 2006.173.18:37:55.35#ibcon#*mode == 0, iclass 26, count 2 2006.173.18:37:55.35#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.18:37:55.35#ibcon#[25=AT07-04\r\n] 2006.173.18:37:55.35#ibcon#*before write, iclass 26, count 2 2006.173.18:37:55.35#ibcon#enter sib2, iclass 26, count 2 2006.173.18:37:55.35#ibcon#flushed, iclass 26, count 2 2006.173.18:37:55.35#ibcon#about to write, iclass 26, count 2 2006.173.18:37:55.35#ibcon#wrote, iclass 26, count 2 2006.173.18:37:55.35#ibcon#about to read 3, iclass 26, count 2 2006.173.18:37:55.38#ibcon#read 3, iclass 26, count 2 2006.173.18:37:55.38#ibcon#about to read 4, iclass 26, count 2 2006.173.18:37:55.38#ibcon#read 4, iclass 26, count 2 2006.173.18:37:55.38#ibcon#about to read 5, iclass 26, count 2 2006.173.18:37:55.38#ibcon#read 5, iclass 26, count 2 2006.173.18:37:55.38#ibcon#about to read 6, iclass 26, count 2 2006.173.18:37:55.38#ibcon#read 6, iclass 26, count 2 2006.173.18:37:55.38#ibcon#end of sib2, iclass 26, count 2 2006.173.18:37:55.38#ibcon#*after write, iclass 26, count 2 2006.173.18:37:55.38#ibcon#*before return 0, iclass 26, count 2 2006.173.18:37:55.38#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.18:37:55.38#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.18:37:55.38#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.18:37:55.38#ibcon#ireg 7 cls_cnt 0 2006.173.18:37:55.38#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.18:37:55.50#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.18:37:55.50#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.18:37:55.50#ibcon#enter wrdev, iclass 26, count 0 2006.173.18:37:55.50#ibcon#first serial, iclass 26, count 0 2006.173.18:37:55.50#ibcon#enter sib2, iclass 26, count 0 2006.173.18:37:55.50#ibcon#flushed, iclass 26, count 0 2006.173.18:37:55.50#ibcon#about to write, iclass 26, count 0 2006.173.18:37:55.50#ibcon#wrote, iclass 26, count 0 2006.173.18:37:55.50#ibcon#about to read 3, iclass 26, count 0 2006.173.18:37:55.52#ibcon#read 3, iclass 26, count 0 2006.173.18:37:55.52#ibcon#about to read 4, iclass 26, count 0 2006.173.18:37:55.52#ibcon#read 4, iclass 26, count 0 2006.173.18:37:55.52#ibcon#about to read 5, iclass 26, count 0 2006.173.18:37:55.52#ibcon#read 5, iclass 26, count 0 2006.173.18:37:55.52#ibcon#about to read 6, iclass 26, count 0 2006.173.18:37:55.52#ibcon#read 6, iclass 26, count 0 2006.173.18:37:55.52#ibcon#end of sib2, iclass 26, count 0 2006.173.18:37:55.52#ibcon#*mode == 0, iclass 26, count 0 2006.173.18:37:55.52#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.18:37:55.52#ibcon#[25=USB\r\n] 2006.173.18:37:55.52#ibcon#*before write, iclass 26, count 0 2006.173.18:37:55.52#ibcon#enter sib2, iclass 26, count 0 2006.173.18:37:55.52#ibcon#flushed, iclass 26, count 0 2006.173.18:37:55.52#ibcon#about to write, iclass 26, count 0 2006.173.18:37:55.52#ibcon#wrote, iclass 26, count 0 2006.173.18:37:55.52#ibcon#about to read 3, iclass 26, count 0 2006.173.18:37:55.55#ibcon#read 3, iclass 26, count 0 2006.173.18:37:55.55#ibcon#about to read 4, iclass 26, count 0 2006.173.18:37:55.55#ibcon#read 4, iclass 26, count 0 2006.173.18:37:55.55#ibcon#about to read 5, iclass 26, count 0 2006.173.18:37:55.55#ibcon#read 5, iclass 26, count 0 2006.173.18:37:55.55#ibcon#about to read 6, iclass 26, count 0 2006.173.18:37:55.55#ibcon#read 6, iclass 26, count 0 2006.173.18:37:55.55#ibcon#end of sib2, iclass 26, count 0 2006.173.18:37:55.55#ibcon#*after write, iclass 26, count 0 2006.173.18:37:55.55#ibcon#*before return 0, iclass 26, count 0 2006.173.18:37:55.55#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.18:37:55.55#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.18:37:55.55#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.18:37:55.55#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.18:37:55.55$vck44/valo=8,884.99 2006.173.18:37:55.55#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.18:37:55.55#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.18:37:55.55#ibcon#ireg 17 cls_cnt 0 2006.173.18:37:55.55#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.18:37:55.55#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.18:37:55.55#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.18:37:55.55#ibcon#enter wrdev, iclass 28, count 0 2006.173.18:37:55.55#ibcon#first serial, iclass 28, count 0 2006.173.18:37:55.55#ibcon#enter sib2, iclass 28, count 0 2006.173.18:37:55.55#ibcon#flushed, iclass 28, count 0 2006.173.18:37:55.55#ibcon#about to write, iclass 28, count 0 2006.173.18:37:55.56#ibcon#wrote, iclass 28, count 0 2006.173.18:37:55.56#ibcon#about to read 3, iclass 28, count 0 2006.173.18:37:55.57#ibcon#read 3, iclass 28, count 0 2006.173.18:37:55.57#ibcon#about to read 4, iclass 28, count 0 2006.173.18:37:55.57#ibcon#read 4, iclass 28, count 0 2006.173.18:37:55.57#ibcon#about to read 5, iclass 28, count 0 2006.173.18:37:55.57#ibcon#read 5, iclass 28, count 0 2006.173.18:37:55.57#ibcon#about to read 6, iclass 28, count 0 2006.173.18:37:55.57#ibcon#read 6, iclass 28, count 0 2006.173.18:37:55.57#ibcon#end of sib2, iclass 28, count 0 2006.173.18:37:55.57#ibcon#*mode == 0, iclass 28, count 0 2006.173.18:37:55.57#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.18:37:55.57#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.18:37:55.57#ibcon#*before write, iclass 28, count 0 2006.173.18:37:55.57#ibcon#enter sib2, iclass 28, count 0 2006.173.18:37:55.57#ibcon#flushed, iclass 28, count 0 2006.173.18:37:55.57#ibcon#about to write, iclass 28, count 0 2006.173.18:37:55.57#ibcon#wrote, iclass 28, count 0 2006.173.18:37:55.57#ibcon#about to read 3, iclass 28, count 0 2006.173.18:37:55.61#ibcon#read 3, iclass 28, count 0 2006.173.18:37:55.61#ibcon#about to read 4, iclass 28, count 0 2006.173.18:37:55.61#ibcon#read 4, iclass 28, count 0 2006.173.18:37:55.61#ibcon#about to read 5, iclass 28, count 0 2006.173.18:37:55.61#ibcon#read 5, iclass 28, count 0 2006.173.18:37:55.61#ibcon#about to read 6, iclass 28, count 0 2006.173.18:37:55.61#ibcon#read 6, iclass 28, count 0 2006.173.18:37:55.61#ibcon#end of sib2, iclass 28, count 0 2006.173.18:37:55.61#ibcon#*after write, iclass 28, count 0 2006.173.18:37:55.61#ibcon#*before return 0, iclass 28, count 0 2006.173.18:37:55.61#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.18:37:55.61#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.18:37:55.61#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.18:37:55.61#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.18:37:55.61$vck44/va=8,4 2006.173.18:37:55.61#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.18:37:55.61#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.18:37:55.61#ibcon#ireg 11 cls_cnt 2 2006.173.18:37:55.61#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.18:37:55.67#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.18:37:55.67#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.18:37:55.67#ibcon#enter wrdev, iclass 30, count 2 2006.173.18:37:55.67#ibcon#first serial, iclass 30, count 2 2006.173.18:37:55.67#ibcon#enter sib2, iclass 30, count 2 2006.173.18:37:55.67#ibcon#flushed, iclass 30, count 2 2006.173.18:37:55.67#ibcon#about to write, iclass 30, count 2 2006.173.18:37:55.67#ibcon#wrote, iclass 30, count 2 2006.173.18:37:55.67#ibcon#about to read 3, iclass 30, count 2 2006.173.18:37:55.69#ibcon#read 3, iclass 30, count 2 2006.173.18:37:55.69#ibcon#about to read 4, iclass 30, count 2 2006.173.18:37:55.69#ibcon#read 4, iclass 30, count 2 2006.173.18:37:55.69#ibcon#about to read 5, iclass 30, count 2 2006.173.18:37:55.69#ibcon#read 5, iclass 30, count 2 2006.173.18:37:55.69#ibcon#about to read 6, iclass 30, count 2 2006.173.18:37:55.69#ibcon#read 6, iclass 30, count 2 2006.173.18:37:55.69#ibcon#end of sib2, iclass 30, count 2 2006.173.18:37:55.69#ibcon#*mode == 0, iclass 30, count 2 2006.173.18:37:55.69#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.18:37:55.69#ibcon#[25=AT08-04\r\n] 2006.173.18:37:55.69#ibcon#*before write, iclass 30, count 2 2006.173.18:37:55.69#ibcon#enter sib2, iclass 30, count 2 2006.173.18:37:55.69#ibcon#flushed, iclass 30, count 2 2006.173.18:37:55.69#ibcon#about to write, iclass 30, count 2 2006.173.18:37:55.69#ibcon#wrote, iclass 30, count 2 2006.173.18:37:55.69#ibcon#about to read 3, iclass 30, count 2 2006.173.18:37:55.72#ibcon#read 3, iclass 30, count 2 2006.173.18:37:55.72#ibcon#about to read 4, iclass 30, count 2 2006.173.18:37:55.72#ibcon#read 4, iclass 30, count 2 2006.173.18:37:55.72#ibcon#about to read 5, iclass 30, count 2 2006.173.18:37:55.72#ibcon#read 5, iclass 30, count 2 2006.173.18:37:55.72#ibcon#about to read 6, iclass 30, count 2 2006.173.18:37:55.72#ibcon#read 6, iclass 30, count 2 2006.173.18:37:55.72#ibcon#end of sib2, iclass 30, count 2 2006.173.18:37:55.72#ibcon#*after write, iclass 30, count 2 2006.173.18:37:55.72#ibcon#*before return 0, iclass 30, count 2 2006.173.18:37:55.72#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.18:37:55.72#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.18:37:55.72#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.18:37:55.72#ibcon#ireg 7 cls_cnt 0 2006.173.18:37:55.72#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.18:37:55.84#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.18:37:55.84#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.18:37:55.84#ibcon#enter wrdev, iclass 30, count 0 2006.173.18:37:55.84#ibcon#first serial, iclass 30, count 0 2006.173.18:37:55.84#ibcon#enter sib2, iclass 30, count 0 2006.173.18:37:55.84#ibcon#flushed, iclass 30, count 0 2006.173.18:37:55.84#ibcon#about to write, iclass 30, count 0 2006.173.18:37:55.84#ibcon#wrote, iclass 30, count 0 2006.173.18:37:55.84#ibcon#about to read 3, iclass 30, count 0 2006.173.18:37:55.86#ibcon#read 3, iclass 30, count 0 2006.173.18:37:55.86#ibcon#about to read 4, iclass 30, count 0 2006.173.18:37:55.86#ibcon#read 4, iclass 30, count 0 2006.173.18:37:55.86#ibcon#about to read 5, iclass 30, count 0 2006.173.18:37:55.86#ibcon#read 5, iclass 30, count 0 2006.173.18:37:55.86#ibcon#about to read 6, iclass 30, count 0 2006.173.18:37:55.86#ibcon#read 6, iclass 30, count 0 2006.173.18:37:55.86#ibcon#end of sib2, iclass 30, count 0 2006.173.18:37:55.86#ibcon#*mode == 0, iclass 30, count 0 2006.173.18:37:55.86#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.18:37:55.86#ibcon#[25=USB\r\n] 2006.173.18:37:55.86#ibcon#*before write, iclass 30, count 0 2006.173.18:37:55.86#ibcon#enter sib2, iclass 30, count 0 2006.173.18:37:55.86#ibcon#flushed, iclass 30, count 0 2006.173.18:37:55.86#ibcon#about to write, iclass 30, count 0 2006.173.18:37:55.86#ibcon#wrote, iclass 30, count 0 2006.173.18:37:55.86#ibcon#about to read 3, iclass 30, count 0 2006.173.18:37:55.89#ibcon#read 3, iclass 30, count 0 2006.173.18:37:55.89#ibcon#about to read 4, iclass 30, count 0 2006.173.18:37:55.89#ibcon#read 4, iclass 30, count 0 2006.173.18:37:55.89#ibcon#about to read 5, iclass 30, count 0 2006.173.18:37:55.89#ibcon#read 5, iclass 30, count 0 2006.173.18:37:55.89#ibcon#about to read 6, iclass 30, count 0 2006.173.18:37:55.89#ibcon#read 6, iclass 30, count 0 2006.173.18:37:55.89#ibcon#end of sib2, iclass 30, count 0 2006.173.18:37:55.89#ibcon#*after write, iclass 30, count 0 2006.173.18:37:55.89#ibcon#*before return 0, iclass 30, count 0 2006.173.18:37:55.89#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.18:37:55.89#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.18:37:55.89#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.18:37:55.89#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.18:37:55.89$vck44/vblo=1,629.99 2006.173.18:37:55.89#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.18:37:55.89#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.18:37:55.89#ibcon#ireg 17 cls_cnt 0 2006.173.18:37:55.89#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.18:37:55.89#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.18:37:55.89#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.18:37:55.89#ibcon#enter wrdev, iclass 32, count 0 2006.173.18:37:55.89#ibcon#first serial, iclass 32, count 0 2006.173.18:37:55.89#ibcon#enter sib2, iclass 32, count 0 2006.173.18:37:55.89#ibcon#flushed, iclass 32, count 0 2006.173.18:37:55.89#ibcon#about to write, iclass 32, count 0 2006.173.18:37:55.89#ibcon#wrote, iclass 32, count 0 2006.173.18:37:55.89#ibcon#about to read 3, iclass 32, count 0 2006.173.18:37:55.91#ibcon#read 3, iclass 32, count 0 2006.173.18:37:55.91#ibcon#about to read 4, iclass 32, count 0 2006.173.18:37:55.91#ibcon#read 4, iclass 32, count 0 2006.173.18:37:55.91#ibcon#about to read 5, iclass 32, count 0 2006.173.18:37:55.91#ibcon#read 5, iclass 32, count 0 2006.173.18:37:55.91#ibcon#about to read 6, iclass 32, count 0 2006.173.18:37:55.91#ibcon#read 6, iclass 32, count 0 2006.173.18:37:55.91#ibcon#end of sib2, iclass 32, count 0 2006.173.18:37:55.91#ibcon#*mode == 0, iclass 32, count 0 2006.173.18:37:55.91#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.18:37:55.91#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.18:37:55.91#ibcon#*before write, iclass 32, count 0 2006.173.18:37:55.91#ibcon#enter sib2, iclass 32, count 0 2006.173.18:37:55.91#ibcon#flushed, iclass 32, count 0 2006.173.18:37:55.91#ibcon#about to write, iclass 32, count 0 2006.173.18:37:55.91#ibcon#wrote, iclass 32, count 0 2006.173.18:37:55.91#ibcon#about to read 3, iclass 32, count 0 2006.173.18:37:55.95#ibcon#read 3, iclass 32, count 0 2006.173.18:37:55.95#ibcon#about to read 4, iclass 32, count 0 2006.173.18:37:55.95#ibcon#read 4, iclass 32, count 0 2006.173.18:37:55.95#ibcon#about to read 5, iclass 32, count 0 2006.173.18:37:55.95#ibcon#read 5, iclass 32, count 0 2006.173.18:37:55.95#ibcon#about to read 6, iclass 32, count 0 2006.173.18:37:55.95#ibcon#read 6, iclass 32, count 0 2006.173.18:37:55.95#ibcon#end of sib2, iclass 32, count 0 2006.173.18:37:55.95#ibcon#*after write, iclass 32, count 0 2006.173.18:37:55.95#ibcon#*before return 0, iclass 32, count 0 2006.173.18:37:55.95#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.18:37:55.95#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.18:37:55.95#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.18:37:55.95#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.18:37:55.95$vck44/vb=1,4 2006.173.18:37:55.95#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.18:37:55.95#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.18:37:55.95#ibcon#ireg 11 cls_cnt 2 2006.173.18:37:55.95#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.18:37:55.95#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.18:37:55.95#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.18:37:55.95#ibcon#enter wrdev, iclass 34, count 2 2006.173.18:37:55.95#ibcon#first serial, iclass 34, count 2 2006.173.18:37:55.95#ibcon#enter sib2, iclass 34, count 2 2006.173.18:37:55.95#ibcon#flushed, iclass 34, count 2 2006.173.18:37:55.95#ibcon#about to write, iclass 34, count 2 2006.173.18:37:55.95#ibcon#wrote, iclass 34, count 2 2006.173.18:37:55.95#ibcon#about to read 3, iclass 34, count 2 2006.173.18:37:55.97#ibcon#read 3, iclass 34, count 2 2006.173.18:37:55.97#ibcon#about to read 4, iclass 34, count 2 2006.173.18:37:55.97#ibcon#read 4, iclass 34, count 2 2006.173.18:37:55.97#ibcon#about to read 5, iclass 34, count 2 2006.173.18:37:55.97#ibcon#read 5, iclass 34, count 2 2006.173.18:37:55.97#ibcon#about to read 6, iclass 34, count 2 2006.173.18:37:55.97#ibcon#read 6, iclass 34, count 2 2006.173.18:37:55.97#ibcon#end of sib2, iclass 34, count 2 2006.173.18:37:55.97#ibcon#*mode == 0, iclass 34, count 2 2006.173.18:37:55.97#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.18:37:55.97#ibcon#[27=AT01-04\r\n] 2006.173.18:37:55.97#ibcon#*before write, iclass 34, count 2 2006.173.18:37:55.97#ibcon#enter sib2, iclass 34, count 2 2006.173.18:37:55.97#ibcon#flushed, iclass 34, count 2 2006.173.18:37:55.97#ibcon#about to write, iclass 34, count 2 2006.173.18:37:55.97#ibcon#wrote, iclass 34, count 2 2006.173.18:37:55.97#ibcon#about to read 3, iclass 34, count 2 2006.173.18:37:56.00#ibcon#read 3, iclass 34, count 2 2006.173.18:37:56.00#ibcon#about to read 4, iclass 34, count 2 2006.173.18:37:56.00#ibcon#read 4, iclass 34, count 2 2006.173.18:37:56.00#ibcon#about to read 5, iclass 34, count 2 2006.173.18:37:56.00#ibcon#read 5, iclass 34, count 2 2006.173.18:37:56.00#ibcon#about to read 6, iclass 34, count 2 2006.173.18:37:56.00#ibcon#read 6, iclass 34, count 2 2006.173.18:37:56.00#ibcon#end of sib2, iclass 34, count 2 2006.173.18:37:56.00#ibcon#*after write, iclass 34, count 2 2006.173.18:37:56.00#ibcon#*before return 0, iclass 34, count 2 2006.173.18:37:56.00#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.18:37:56.00#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.18:37:56.00#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.18:37:56.00#ibcon#ireg 7 cls_cnt 0 2006.173.18:37:56.00#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.18:37:56.12#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.18:37:56.12#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.18:37:56.12#ibcon#enter wrdev, iclass 34, count 0 2006.173.18:37:56.12#ibcon#first serial, iclass 34, count 0 2006.173.18:37:56.12#ibcon#enter sib2, iclass 34, count 0 2006.173.18:37:56.12#ibcon#flushed, iclass 34, count 0 2006.173.18:37:56.12#ibcon#about to write, iclass 34, count 0 2006.173.18:37:56.12#ibcon#wrote, iclass 34, count 0 2006.173.18:37:56.12#ibcon#about to read 3, iclass 34, count 0 2006.173.18:37:56.14#ibcon#read 3, iclass 34, count 0 2006.173.18:37:56.14#ibcon#about to read 4, iclass 34, count 0 2006.173.18:37:56.14#ibcon#read 4, iclass 34, count 0 2006.173.18:37:56.14#ibcon#about to read 5, iclass 34, count 0 2006.173.18:37:56.14#ibcon#read 5, iclass 34, count 0 2006.173.18:37:56.14#ibcon#about to read 6, iclass 34, count 0 2006.173.18:37:56.14#ibcon#read 6, iclass 34, count 0 2006.173.18:37:56.14#ibcon#end of sib2, iclass 34, count 0 2006.173.18:37:56.14#ibcon#*mode == 0, iclass 34, count 0 2006.173.18:37:56.14#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.18:37:56.14#ibcon#[27=USB\r\n] 2006.173.18:37:56.14#ibcon#*before write, iclass 34, count 0 2006.173.18:37:56.14#ibcon#enter sib2, iclass 34, count 0 2006.173.18:37:56.14#ibcon#flushed, iclass 34, count 0 2006.173.18:37:56.14#ibcon#about to write, iclass 34, count 0 2006.173.18:37:56.14#ibcon#wrote, iclass 34, count 0 2006.173.18:37:56.14#ibcon#about to read 3, iclass 34, count 0 2006.173.18:37:56.17#ibcon#read 3, iclass 34, count 0 2006.173.18:37:56.17#ibcon#about to read 4, iclass 34, count 0 2006.173.18:37:56.17#ibcon#read 4, iclass 34, count 0 2006.173.18:37:56.17#ibcon#about to read 5, iclass 34, count 0 2006.173.18:37:56.17#ibcon#read 5, iclass 34, count 0 2006.173.18:37:56.17#ibcon#about to read 6, iclass 34, count 0 2006.173.18:37:56.17#ibcon#read 6, iclass 34, count 0 2006.173.18:37:56.17#ibcon#end of sib2, iclass 34, count 0 2006.173.18:37:56.17#ibcon#*after write, iclass 34, count 0 2006.173.18:37:56.17#ibcon#*before return 0, iclass 34, count 0 2006.173.18:37:56.17#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.18:37:56.17#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.18:37:56.17#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.18:37:56.17#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.18:37:56.17$vck44/vblo=2,634.99 2006.173.18:37:56.17#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.18:37:56.17#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.18:37:56.17#ibcon#ireg 17 cls_cnt 0 2006.173.18:37:56.17#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.18:37:56.17#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.18:37:56.17#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.18:37:56.17#ibcon#enter wrdev, iclass 36, count 0 2006.173.18:37:56.17#ibcon#first serial, iclass 36, count 0 2006.173.18:37:56.17#ibcon#enter sib2, iclass 36, count 0 2006.173.18:37:56.17#ibcon#flushed, iclass 36, count 0 2006.173.18:37:56.17#ibcon#about to write, iclass 36, count 0 2006.173.18:37:56.17#ibcon#wrote, iclass 36, count 0 2006.173.18:37:56.17#ibcon#about to read 3, iclass 36, count 0 2006.173.18:37:56.19#ibcon#read 3, iclass 36, count 0 2006.173.18:37:56.19#ibcon#about to read 4, iclass 36, count 0 2006.173.18:37:56.19#ibcon#read 4, iclass 36, count 0 2006.173.18:37:56.19#ibcon#about to read 5, iclass 36, count 0 2006.173.18:37:56.19#ibcon#read 5, iclass 36, count 0 2006.173.18:37:56.19#ibcon#about to read 6, iclass 36, count 0 2006.173.18:37:56.19#ibcon#read 6, iclass 36, count 0 2006.173.18:37:56.19#ibcon#end of sib2, iclass 36, count 0 2006.173.18:37:56.19#ibcon#*mode == 0, iclass 36, count 0 2006.173.18:37:56.19#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.18:37:56.19#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.18:37:56.19#ibcon#*before write, iclass 36, count 0 2006.173.18:37:56.19#ibcon#enter sib2, iclass 36, count 0 2006.173.18:37:56.19#ibcon#flushed, iclass 36, count 0 2006.173.18:37:56.19#ibcon#about to write, iclass 36, count 0 2006.173.18:37:56.19#ibcon#wrote, iclass 36, count 0 2006.173.18:37:56.19#ibcon#about to read 3, iclass 36, count 0 2006.173.18:37:56.23#ibcon#read 3, iclass 36, count 0 2006.173.18:37:56.23#ibcon#about to read 4, iclass 36, count 0 2006.173.18:37:56.23#ibcon#read 4, iclass 36, count 0 2006.173.18:37:56.23#ibcon#about to read 5, iclass 36, count 0 2006.173.18:37:56.23#ibcon#read 5, iclass 36, count 0 2006.173.18:37:56.23#ibcon#about to read 6, iclass 36, count 0 2006.173.18:37:56.23#ibcon#read 6, iclass 36, count 0 2006.173.18:37:56.23#ibcon#end of sib2, iclass 36, count 0 2006.173.18:37:56.23#ibcon#*after write, iclass 36, count 0 2006.173.18:37:56.23#ibcon#*before return 0, iclass 36, count 0 2006.173.18:37:56.23#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.18:37:56.23#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.18:37:56.23#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.18:37:56.23#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.18:37:56.23$vck44/vb=2,4 2006.173.18:37:56.23#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.18:37:56.23#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.18:37:56.23#ibcon#ireg 11 cls_cnt 2 2006.173.18:37:56.23#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.18:37:56.29#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.18:37:56.29#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.18:37:56.29#ibcon#enter wrdev, iclass 38, count 2 2006.173.18:37:56.29#ibcon#first serial, iclass 38, count 2 2006.173.18:37:56.29#ibcon#enter sib2, iclass 38, count 2 2006.173.18:37:56.29#ibcon#flushed, iclass 38, count 2 2006.173.18:37:56.29#ibcon#about to write, iclass 38, count 2 2006.173.18:37:56.29#ibcon#wrote, iclass 38, count 2 2006.173.18:37:56.29#ibcon#about to read 3, iclass 38, count 2 2006.173.18:37:56.31#ibcon#read 3, iclass 38, count 2 2006.173.18:37:56.31#ibcon#about to read 4, iclass 38, count 2 2006.173.18:37:56.31#ibcon#read 4, iclass 38, count 2 2006.173.18:37:56.31#ibcon#about to read 5, iclass 38, count 2 2006.173.18:37:56.31#ibcon#read 5, iclass 38, count 2 2006.173.18:37:56.31#ibcon#about to read 6, iclass 38, count 2 2006.173.18:37:56.31#ibcon#read 6, iclass 38, count 2 2006.173.18:37:56.31#ibcon#end of sib2, iclass 38, count 2 2006.173.18:37:56.31#ibcon#*mode == 0, iclass 38, count 2 2006.173.18:37:56.31#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.18:37:56.31#ibcon#[27=AT02-04\r\n] 2006.173.18:37:56.31#ibcon#*before write, iclass 38, count 2 2006.173.18:37:56.31#ibcon#enter sib2, iclass 38, count 2 2006.173.18:37:56.31#ibcon#flushed, iclass 38, count 2 2006.173.18:37:56.31#ibcon#about to write, iclass 38, count 2 2006.173.18:37:56.31#ibcon#wrote, iclass 38, count 2 2006.173.18:37:56.31#ibcon#about to read 3, iclass 38, count 2 2006.173.18:37:56.34#ibcon#read 3, iclass 38, count 2 2006.173.18:37:56.34#ibcon#about to read 4, iclass 38, count 2 2006.173.18:37:56.34#ibcon#read 4, iclass 38, count 2 2006.173.18:37:56.34#ibcon#about to read 5, iclass 38, count 2 2006.173.18:37:56.34#ibcon#read 5, iclass 38, count 2 2006.173.18:37:56.34#ibcon#about to read 6, iclass 38, count 2 2006.173.18:37:56.34#ibcon#read 6, iclass 38, count 2 2006.173.18:37:56.34#ibcon#end of sib2, iclass 38, count 2 2006.173.18:37:56.34#ibcon#*after write, iclass 38, count 2 2006.173.18:37:56.34#ibcon#*before return 0, iclass 38, count 2 2006.173.18:37:56.34#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.18:37:56.34#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.18:37:56.34#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.18:37:56.34#ibcon#ireg 7 cls_cnt 0 2006.173.18:37:56.34#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.18:37:56.46#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.18:37:56.46#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.18:37:56.46#ibcon#enter wrdev, iclass 38, count 0 2006.173.18:37:56.46#ibcon#first serial, iclass 38, count 0 2006.173.18:37:56.46#ibcon#enter sib2, iclass 38, count 0 2006.173.18:37:56.46#ibcon#flushed, iclass 38, count 0 2006.173.18:37:56.46#ibcon#about to write, iclass 38, count 0 2006.173.18:37:56.46#ibcon#wrote, iclass 38, count 0 2006.173.18:37:56.46#ibcon#about to read 3, iclass 38, count 0 2006.173.18:37:56.48#ibcon#read 3, iclass 38, count 0 2006.173.18:37:56.48#ibcon#about to read 4, iclass 38, count 0 2006.173.18:37:56.48#ibcon#read 4, iclass 38, count 0 2006.173.18:37:56.48#ibcon#about to read 5, iclass 38, count 0 2006.173.18:37:56.48#ibcon#read 5, iclass 38, count 0 2006.173.18:37:56.48#ibcon#about to read 6, iclass 38, count 0 2006.173.18:37:56.48#ibcon#read 6, iclass 38, count 0 2006.173.18:37:56.48#ibcon#end of sib2, iclass 38, count 0 2006.173.18:37:56.48#ibcon#*mode == 0, iclass 38, count 0 2006.173.18:37:56.48#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.18:37:56.48#ibcon#[27=USB\r\n] 2006.173.18:37:56.48#ibcon#*before write, iclass 38, count 0 2006.173.18:37:56.48#ibcon#enter sib2, iclass 38, count 0 2006.173.18:37:56.48#ibcon#flushed, iclass 38, count 0 2006.173.18:37:56.48#ibcon#about to write, iclass 38, count 0 2006.173.18:37:56.48#ibcon#wrote, iclass 38, count 0 2006.173.18:37:56.48#ibcon#about to read 3, iclass 38, count 0 2006.173.18:37:56.51#ibcon#read 3, iclass 38, count 0 2006.173.18:37:56.51#ibcon#about to read 4, iclass 38, count 0 2006.173.18:37:56.51#ibcon#read 4, iclass 38, count 0 2006.173.18:37:56.51#ibcon#about to read 5, iclass 38, count 0 2006.173.18:37:56.51#ibcon#read 5, iclass 38, count 0 2006.173.18:37:56.51#ibcon#about to read 6, iclass 38, count 0 2006.173.18:37:56.51#ibcon#read 6, iclass 38, count 0 2006.173.18:37:56.51#ibcon#end of sib2, iclass 38, count 0 2006.173.18:37:56.51#ibcon#*after write, iclass 38, count 0 2006.173.18:37:56.51#ibcon#*before return 0, iclass 38, count 0 2006.173.18:37:56.51#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.18:37:56.51#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.18:37:56.51#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.18:37:56.51#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.18:37:56.51$vck44/vblo=3,649.99 2006.173.18:37:56.51#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.18:37:56.51#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.18:37:56.51#ibcon#ireg 17 cls_cnt 0 2006.173.18:37:56.51#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.18:37:56.51#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.18:37:56.51#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.18:37:56.51#ibcon#enter wrdev, iclass 40, count 0 2006.173.18:37:56.51#ibcon#first serial, iclass 40, count 0 2006.173.18:37:56.51#ibcon#enter sib2, iclass 40, count 0 2006.173.18:37:56.51#ibcon#flushed, iclass 40, count 0 2006.173.18:37:56.51#ibcon#about to write, iclass 40, count 0 2006.173.18:37:56.52#ibcon#wrote, iclass 40, count 0 2006.173.18:37:56.52#ibcon#about to read 3, iclass 40, count 0 2006.173.18:37:56.53#ibcon#read 3, iclass 40, count 0 2006.173.18:37:56.53#ibcon#about to read 4, iclass 40, count 0 2006.173.18:37:56.53#ibcon#read 4, iclass 40, count 0 2006.173.18:37:56.53#ibcon#about to read 5, iclass 40, count 0 2006.173.18:37:56.53#ibcon#read 5, iclass 40, count 0 2006.173.18:37:56.53#ibcon#about to read 6, iclass 40, count 0 2006.173.18:37:56.53#ibcon#read 6, iclass 40, count 0 2006.173.18:37:56.53#ibcon#end of sib2, iclass 40, count 0 2006.173.18:37:56.53#ibcon#*mode == 0, iclass 40, count 0 2006.173.18:37:56.53#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.18:37:56.53#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.18:37:56.53#ibcon#*before write, iclass 40, count 0 2006.173.18:37:56.53#ibcon#enter sib2, iclass 40, count 0 2006.173.18:37:56.53#ibcon#flushed, iclass 40, count 0 2006.173.18:37:56.53#ibcon#about to write, iclass 40, count 0 2006.173.18:37:56.53#ibcon#wrote, iclass 40, count 0 2006.173.18:37:56.53#ibcon#about to read 3, iclass 40, count 0 2006.173.18:37:56.57#ibcon#read 3, iclass 40, count 0 2006.173.18:37:56.57#ibcon#about to read 4, iclass 40, count 0 2006.173.18:37:56.57#ibcon#read 4, iclass 40, count 0 2006.173.18:37:56.57#ibcon#about to read 5, iclass 40, count 0 2006.173.18:37:56.57#ibcon#read 5, iclass 40, count 0 2006.173.18:37:56.57#ibcon#about to read 6, iclass 40, count 0 2006.173.18:37:56.57#ibcon#read 6, iclass 40, count 0 2006.173.18:37:56.57#ibcon#end of sib2, iclass 40, count 0 2006.173.18:37:56.57#ibcon#*after write, iclass 40, count 0 2006.173.18:37:56.57#ibcon#*before return 0, iclass 40, count 0 2006.173.18:37:56.57#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.18:37:56.57#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.18:37:56.57#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.18:37:56.57#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.18:37:56.57$vck44/vb=3,4 2006.173.18:37:56.57#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.18:37:56.57#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.18:37:56.57#ibcon#ireg 11 cls_cnt 2 2006.173.18:37:56.57#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.18:37:56.63#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.18:37:56.63#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.18:37:56.63#ibcon#enter wrdev, iclass 4, count 2 2006.173.18:37:56.63#ibcon#first serial, iclass 4, count 2 2006.173.18:37:56.63#ibcon#enter sib2, iclass 4, count 2 2006.173.18:37:56.63#ibcon#flushed, iclass 4, count 2 2006.173.18:37:56.63#ibcon#about to write, iclass 4, count 2 2006.173.18:37:56.63#ibcon#wrote, iclass 4, count 2 2006.173.18:37:56.63#ibcon#about to read 3, iclass 4, count 2 2006.173.18:37:56.65#ibcon#read 3, iclass 4, count 2 2006.173.18:37:56.65#ibcon#about to read 4, iclass 4, count 2 2006.173.18:37:56.65#ibcon#read 4, iclass 4, count 2 2006.173.18:37:56.65#ibcon#about to read 5, iclass 4, count 2 2006.173.18:37:56.65#ibcon#read 5, iclass 4, count 2 2006.173.18:37:56.65#ibcon#about to read 6, iclass 4, count 2 2006.173.18:37:56.65#ibcon#read 6, iclass 4, count 2 2006.173.18:37:56.65#ibcon#end of sib2, iclass 4, count 2 2006.173.18:37:56.65#ibcon#*mode == 0, iclass 4, count 2 2006.173.18:37:56.65#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.18:37:56.65#ibcon#[27=AT03-04\r\n] 2006.173.18:37:56.65#ibcon#*before write, iclass 4, count 2 2006.173.18:37:56.65#ibcon#enter sib2, iclass 4, count 2 2006.173.18:37:56.65#ibcon#flushed, iclass 4, count 2 2006.173.18:37:56.65#ibcon#about to write, iclass 4, count 2 2006.173.18:37:56.65#ibcon#wrote, iclass 4, count 2 2006.173.18:37:56.65#ibcon#about to read 3, iclass 4, count 2 2006.173.18:37:56.68#ibcon#read 3, iclass 4, count 2 2006.173.18:37:56.68#ibcon#about to read 4, iclass 4, count 2 2006.173.18:37:56.68#ibcon#read 4, iclass 4, count 2 2006.173.18:37:56.68#ibcon#about to read 5, iclass 4, count 2 2006.173.18:37:56.68#ibcon#read 5, iclass 4, count 2 2006.173.18:37:56.68#ibcon#about to read 6, iclass 4, count 2 2006.173.18:37:56.68#ibcon#read 6, iclass 4, count 2 2006.173.18:37:56.68#ibcon#end of sib2, iclass 4, count 2 2006.173.18:37:56.68#ibcon#*after write, iclass 4, count 2 2006.173.18:37:56.68#ibcon#*before return 0, iclass 4, count 2 2006.173.18:37:56.68#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.18:37:56.68#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.18:37:56.68#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.18:37:56.68#ibcon#ireg 7 cls_cnt 0 2006.173.18:37:56.68#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.18:37:56.80#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.18:37:56.80#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.18:37:56.80#ibcon#enter wrdev, iclass 4, count 0 2006.173.18:37:56.80#ibcon#first serial, iclass 4, count 0 2006.173.18:37:56.80#ibcon#enter sib2, iclass 4, count 0 2006.173.18:37:56.80#ibcon#flushed, iclass 4, count 0 2006.173.18:37:56.80#ibcon#about to write, iclass 4, count 0 2006.173.18:37:56.80#ibcon#wrote, iclass 4, count 0 2006.173.18:37:56.80#ibcon#about to read 3, iclass 4, count 0 2006.173.18:37:56.82#ibcon#read 3, iclass 4, count 0 2006.173.18:37:56.82#ibcon#about to read 4, iclass 4, count 0 2006.173.18:37:56.82#ibcon#read 4, iclass 4, count 0 2006.173.18:37:56.82#ibcon#about to read 5, iclass 4, count 0 2006.173.18:37:56.82#ibcon#read 5, iclass 4, count 0 2006.173.18:37:56.82#ibcon#about to read 6, iclass 4, count 0 2006.173.18:37:56.82#ibcon#read 6, iclass 4, count 0 2006.173.18:37:56.82#ibcon#end of sib2, iclass 4, count 0 2006.173.18:37:56.82#ibcon#*mode == 0, iclass 4, count 0 2006.173.18:37:56.82#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.18:37:56.82#ibcon#[27=USB\r\n] 2006.173.18:37:56.82#ibcon#*before write, iclass 4, count 0 2006.173.18:37:56.82#ibcon#enter sib2, iclass 4, count 0 2006.173.18:37:56.82#ibcon#flushed, iclass 4, count 0 2006.173.18:37:56.82#ibcon#about to write, iclass 4, count 0 2006.173.18:37:56.82#ibcon#wrote, iclass 4, count 0 2006.173.18:37:56.82#ibcon#about to read 3, iclass 4, count 0 2006.173.18:37:56.85#ibcon#read 3, iclass 4, count 0 2006.173.18:37:56.85#ibcon#about to read 4, iclass 4, count 0 2006.173.18:37:56.85#ibcon#read 4, iclass 4, count 0 2006.173.18:37:56.85#ibcon#about to read 5, iclass 4, count 0 2006.173.18:37:56.85#ibcon#read 5, iclass 4, count 0 2006.173.18:37:56.85#ibcon#about to read 6, iclass 4, count 0 2006.173.18:37:56.85#ibcon#read 6, iclass 4, count 0 2006.173.18:37:56.85#ibcon#end of sib2, iclass 4, count 0 2006.173.18:37:56.85#ibcon#*after write, iclass 4, count 0 2006.173.18:37:56.85#ibcon#*before return 0, iclass 4, count 0 2006.173.18:37:56.85#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.18:37:56.85#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.18:37:56.85#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.18:37:56.85#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.18:37:56.85$vck44/vblo=4,679.99 2006.173.18:37:56.85#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.18:37:56.85#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.18:37:56.85#ibcon#ireg 17 cls_cnt 0 2006.173.18:37:56.85#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.18:37:56.85#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.18:37:56.85#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.18:37:56.85#ibcon#enter wrdev, iclass 6, count 0 2006.173.18:37:56.85#ibcon#first serial, iclass 6, count 0 2006.173.18:37:56.85#ibcon#enter sib2, iclass 6, count 0 2006.173.18:37:56.85#ibcon#flushed, iclass 6, count 0 2006.173.18:37:56.85#ibcon#about to write, iclass 6, count 0 2006.173.18:37:56.85#ibcon#wrote, iclass 6, count 0 2006.173.18:37:56.85#ibcon#about to read 3, iclass 6, count 0 2006.173.18:37:56.87#ibcon#read 3, iclass 6, count 0 2006.173.18:37:56.87#ibcon#about to read 4, iclass 6, count 0 2006.173.18:37:56.87#ibcon#read 4, iclass 6, count 0 2006.173.18:37:56.87#ibcon#about to read 5, iclass 6, count 0 2006.173.18:37:56.87#ibcon#read 5, iclass 6, count 0 2006.173.18:37:56.87#ibcon#about to read 6, iclass 6, count 0 2006.173.18:37:56.87#ibcon#read 6, iclass 6, count 0 2006.173.18:37:56.87#ibcon#end of sib2, iclass 6, count 0 2006.173.18:37:56.87#ibcon#*mode == 0, iclass 6, count 0 2006.173.18:37:56.87#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.18:37:56.87#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.18:37:56.87#ibcon#*before write, iclass 6, count 0 2006.173.18:37:56.87#ibcon#enter sib2, iclass 6, count 0 2006.173.18:37:56.87#ibcon#flushed, iclass 6, count 0 2006.173.18:37:56.87#ibcon#about to write, iclass 6, count 0 2006.173.18:37:56.87#ibcon#wrote, iclass 6, count 0 2006.173.18:37:56.87#ibcon#about to read 3, iclass 6, count 0 2006.173.18:37:56.91#ibcon#read 3, iclass 6, count 0 2006.173.18:37:56.91#ibcon#about to read 4, iclass 6, count 0 2006.173.18:37:56.91#ibcon#read 4, iclass 6, count 0 2006.173.18:37:56.91#ibcon#about to read 5, iclass 6, count 0 2006.173.18:37:56.91#ibcon#read 5, iclass 6, count 0 2006.173.18:37:56.91#ibcon#about to read 6, iclass 6, count 0 2006.173.18:37:56.91#ibcon#read 6, iclass 6, count 0 2006.173.18:37:56.91#ibcon#end of sib2, iclass 6, count 0 2006.173.18:37:56.91#ibcon#*after write, iclass 6, count 0 2006.173.18:37:56.91#ibcon#*before return 0, iclass 6, count 0 2006.173.18:37:56.91#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.18:37:56.91#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.18:37:56.91#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.18:37:56.91#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.18:37:56.91$vck44/vb=4,4 2006.173.18:37:56.91#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.18:37:56.91#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.18:37:56.91#ibcon#ireg 11 cls_cnt 2 2006.173.18:37:56.91#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.18:37:56.97#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.18:37:56.97#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.18:37:56.97#ibcon#enter wrdev, iclass 10, count 2 2006.173.18:37:56.97#ibcon#first serial, iclass 10, count 2 2006.173.18:37:56.97#ibcon#enter sib2, iclass 10, count 2 2006.173.18:37:56.97#ibcon#flushed, iclass 10, count 2 2006.173.18:37:56.97#ibcon#about to write, iclass 10, count 2 2006.173.18:37:56.97#ibcon#wrote, iclass 10, count 2 2006.173.18:37:56.97#ibcon#about to read 3, iclass 10, count 2 2006.173.18:37:56.99#ibcon#read 3, iclass 10, count 2 2006.173.18:37:56.99#ibcon#about to read 4, iclass 10, count 2 2006.173.18:37:56.99#ibcon#read 4, iclass 10, count 2 2006.173.18:37:56.99#ibcon#about to read 5, iclass 10, count 2 2006.173.18:37:56.99#ibcon#read 5, iclass 10, count 2 2006.173.18:37:56.99#ibcon#about to read 6, iclass 10, count 2 2006.173.18:37:56.99#ibcon#read 6, iclass 10, count 2 2006.173.18:37:56.99#ibcon#end of sib2, iclass 10, count 2 2006.173.18:37:56.99#ibcon#*mode == 0, iclass 10, count 2 2006.173.18:37:56.99#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.18:37:56.99#ibcon#[27=AT04-04\r\n] 2006.173.18:37:56.99#ibcon#*before write, iclass 10, count 2 2006.173.18:37:56.99#ibcon#enter sib2, iclass 10, count 2 2006.173.18:37:56.99#ibcon#flushed, iclass 10, count 2 2006.173.18:37:56.99#ibcon#about to write, iclass 10, count 2 2006.173.18:37:56.99#ibcon#wrote, iclass 10, count 2 2006.173.18:37:56.99#ibcon#about to read 3, iclass 10, count 2 2006.173.18:37:57.02#ibcon#read 3, iclass 10, count 2 2006.173.18:37:57.02#ibcon#about to read 4, iclass 10, count 2 2006.173.18:37:57.02#ibcon#read 4, iclass 10, count 2 2006.173.18:37:57.02#ibcon#about to read 5, iclass 10, count 2 2006.173.18:37:57.02#ibcon#read 5, iclass 10, count 2 2006.173.18:37:57.02#ibcon#about to read 6, iclass 10, count 2 2006.173.18:37:57.02#ibcon#read 6, iclass 10, count 2 2006.173.18:37:57.02#ibcon#end of sib2, iclass 10, count 2 2006.173.18:37:57.02#ibcon#*after write, iclass 10, count 2 2006.173.18:37:57.02#ibcon#*before return 0, iclass 10, count 2 2006.173.18:37:57.02#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.18:37:57.02#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.18:37:57.02#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.18:37:57.02#ibcon#ireg 7 cls_cnt 0 2006.173.18:37:57.02#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.18:37:57.14#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.18:37:57.14#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.18:37:57.14#ibcon#enter wrdev, iclass 10, count 0 2006.173.18:37:57.14#ibcon#first serial, iclass 10, count 0 2006.173.18:37:57.14#ibcon#enter sib2, iclass 10, count 0 2006.173.18:37:57.15#ibcon#flushed, iclass 10, count 0 2006.173.18:37:57.15#ibcon#about to write, iclass 10, count 0 2006.173.18:37:57.15#ibcon#wrote, iclass 10, count 0 2006.173.18:37:57.15#ibcon#about to read 3, iclass 10, count 0 2006.173.18:37:57.16#ibcon#read 3, iclass 10, count 0 2006.173.18:37:57.16#ibcon#about to read 4, iclass 10, count 0 2006.173.18:37:57.16#ibcon#read 4, iclass 10, count 0 2006.173.18:37:57.16#ibcon#about to read 5, iclass 10, count 0 2006.173.18:37:57.16#ibcon#read 5, iclass 10, count 0 2006.173.18:37:57.16#ibcon#about to read 6, iclass 10, count 0 2006.173.18:37:57.16#ibcon#read 6, iclass 10, count 0 2006.173.18:37:57.16#ibcon#end of sib2, iclass 10, count 0 2006.173.18:37:57.16#ibcon#*mode == 0, iclass 10, count 0 2006.173.18:37:57.16#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.18:37:57.16#ibcon#[27=USB\r\n] 2006.173.18:37:57.16#ibcon#*before write, iclass 10, count 0 2006.173.18:37:57.16#ibcon#enter sib2, iclass 10, count 0 2006.173.18:37:57.16#ibcon#flushed, iclass 10, count 0 2006.173.18:37:57.16#ibcon#about to write, iclass 10, count 0 2006.173.18:37:57.16#ibcon#wrote, iclass 10, count 0 2006.173.18:37:57.16#ibcon#about to read 3, iclass 10, count 0 2006.173.18:37:57.19#ibcon#read 3, iclass 10, count 0 2006.173.18:37:57.19#ibcon#about to read 4, iclass 10, count 0 2006.173.18:37:57.19#ibcon#read 4, iclass 10, count 0 2006.173.18:37:57.19#ibcon#about to read 5, iclass 10, count 0 2006.173.18:37:57.19#ibcon#read 5, iclass 10, count 0 2006.173.18:37:57.19#ibcon#about to read 6, iclass 10, count 0 2006.173.18:37:57.19#ibcon#read 6, iclass 10, count 0 2006.173.18:37:57.19#ibcon#end of sib2, iclass 10, count 0 2006.173.18:37:57.19#ibcon#*after write, iclass 10, count 0 2006.173.18:37:57.19#ibcon#*before return 0, iclass 10, count 0 2006.173.18:37:57.19#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.18:37:57.19#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.18:37:57.19#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.18:37:57.19#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.18:37:57.19$vck44/vblo=5,709.99 2006.173.18:37:57.19#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.18:37:57.19#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.18:37:57.19#ibcon#ireg 17 cls_cnt 0 2006.173.18:37:57.19#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.18:37:57.19#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.18:37:57.19#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.18:37:57.19#ibcon#enter wrdev, iclass 12, count 0 2006.173.18:37:57.19#ibcon#first serial, iclass 12, count 0 2006.173.18:37:57.19#ibcon#enter sib2, iclass 12, count 0 2006.173.18:37:57.19#ibcon#flushed, iclass 12, count 0 2006.173.18:37:57.19#ibcon#about to write, iclass 12, count 0 2006.173.18:37:57.20#ibcon#wrote, iclass 12, count 0 2006.173.18:37:57.20#ibcon#about to read 3, iclass 12, count 0 2006.173.18:37:57.21#ibcon#read 3, iclass 12, count 0 2006.173.18:37:57.21#ibcon#about to read 4, iclass 12, count 0 2006.173.18:37:57.21#ibcon#read 4, iclass 12, count 0 2006.173.18:37:57.21#ibcon#about to read 5, iclass 12, count 0 2006.173.18:37:57.21#ibcon#read 5, iclass 12, count 0 2006.173.18:37:57.21#ibcon#about to read 6, iclass 12, count 0 2006.173.18:37:57.21#ibcon#read 6, iclass 12, count 0 2006.173.18:37:57.21#ibcon#end of sib2, iclass 12, count 0 2006.173.18:37:57.21#ibcon#*mode == 0, iclass 12, count 0 2006.173.18:37:57.21#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.18:37:57.21#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.18:37:57.21#ibcon#*before write, iclass 12, count 0 2006.173.18:37:57.21#ibcon#enter sib2, iclass 12, count 0 2006.173.18:37:57.21#ibcon#flushed, iclass 12, count 0 2006.173.18:37:57.21#ibcon#about to write, iclass 12, count 0 2006.173.18:37:57.21#ibcon#wrote, iclass 12, count 0 2006.173.18:37:57.21#ibcon#about to read 3, iclass 12, count 0 2006.173.18:37:57.25#ibcon#read 3, iclass 12, count 0 2006.173.18:37:57.25#ibcon#about to read 4, iclass 12, count 0 2006.173.18:37:57.25#ibcon#read 4, iclass 12, count 0 2006.173.18:37:57.25#ibcon#about to read 5, iclass 12, count 0 2006.173.18:37:57.25#ibcon#read 5, iclass 12, count 0 2006.173.18:37:57.25#ibcon#about to read 6, iclass 12, count 0 2006.173.18:37:57.25#ibcon#read 6, iclass 12, count 0 2006.173.18:37:57.25#ibcon#end of sib2, iclass 12, count 0 2006.173.18:37:57.25#ibcon#*after write, iclass 12, count 0 2006.173.18:37:57.25#ibcon#*before return 0, iclass 12, count 0 2006.173.18:37:57.25#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.18:37:57.25#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.18:37:57.25#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.18:37:57.25#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.18:37:57.25$vck44/vb=5,4 2006.173.18:37:57.25#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.18:37:57.25#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.18:37:57.25#ibcon#ireg 11 cls_cnt 2 2006.173.18:37:57.25#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.18:37:57.31#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.18:37:57.31#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.18:37:57.31#ibcon#enter wrdev, iclass 14, count 2 2006.173.18:37:57.31#ibcon#first serial, iclass 14, count 2 2006.173.18:37:57.31#ibcon#enter sib2, iclass 14, count 2 2006.173.18:37:57.31#ibcon#flushed, iclass 14, count 2 2006.173.18:37:57.31#ibcon#about to write, iclass 14, count 2 2006.173.18:37:57.31#ibcon#wrote, iclass 14, count 2 2006.173.18:37:57.31#ibcon#about to read 3, iclass 14, count 2 2006.173.18:37:57.33#ibcon#read 3, iclass 14, count 2 2006.173.18:37:57.33#ibcon#about to read 4, iclass 14, count 2 2006.173.18:37:57.33#ibcon#read 4, iclass 14, count 2 2006.173.18:37:57.33#ibcon#about to read 5, iclass 14, count 2 2006.173.18:37:57.33#ibcon#read 5, iclass 14, count 2 2006.173.18:37:57.33#ibcon#about to read 6, iclass 14, count 2 2006.173.18:37:57.33#ibcon#read 6, iclass 14, count 2 2006.173.18:37:57.33#ibcon#end of sib2, iclass 14, count 2 2006.173.18:37:57.33#ibcon#*mode == 0, iclass 14, count 2 2006.173.18:37:57.33#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.18:37:57.33#ibcon#[27=AT05-04\r\n] 2006.173.18:37:57.33#ibcon#*before write, iclass 14, count 2 2006.173.18:37:57.33#ibcon#enter sib2, iclass 14, count 2 2006.173.18:37:57.33#ibcon#flushed, iclass 14, count 2 2006.173.18:37:57.33#ibcon#about to write, iclass 14, count 2 2006.173.18:37:57.33#ibcon#wrote, iclass 14, count 2 2006.173.18:37:57.33#ibcon#about to read 3, iclass 14, count 2 2006.173.18:37:57.36#ibcon#read 3, iclass 14, count 2 2006.173.18:37:57.36#ibcon#about to read 4, iclass 14, count 2 2006.173.18:37:57.36#ibcon#read 4, iclass 14, count 2 2006.173.18:37:57.36#ibcon#about to read 5, iclass 14, count 2 2006.173.18:37:57.36#ibcon#read 5, iclass 14, count 2 2006.173.18:37:57.36#ibcon#about to read 6, iclass 14, count 2 2006.173.18:37:57.36#ibcon#read 6, iclass 14, count 2 2006.173.18:37:57.36#ibcon#end of sib2, iclass 14, count 2 2006.173.18:37:57.36#ibcon#*after write, iclass 14, count 2 2006.173.18:37:57.36#ibcon#*before return 0, iclass 14, count 2 2006.173.18:37:57.36#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.18:37:57.36#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.18:37:57.36#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.18:37:57.36#ibcon#ireg 7 cls_cnt 0 2006.173.18:37:57.36#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.18:37:57.48#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.18:37:57.48#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.18:37:57.48#ibcon#enter wrdev, iclass 14, count 0 2006.173.18:37:57.48#ibcon#first serial, iclass 14, count 0 2006.173.18:37:57.48#ibcon#enter sib2, iclass 14, count 0 2006.173.18:37:57.48#ibcon#flushed, iclass 14, count 0 2006.173.18:37:57.48#ibcon#about to write, iclass 14, count 0 2006.173.18:37:57.48#ibcon#wrote, iclass 14, count 0 2006.173.18:37:57.48#ibcon#about to read 3, iclass 14, count 0 2006.173.18:37:57.50#ibcon#read 3, iclass 14, count 0 2006.173.18:37:57.50#ibcon#about to read 4, iclass 14, count 0 2006.173.18:37:57.50#ibcon#read 4, iclass 14, count 0 2006.173.18:37:57.50#ibcon#about to read 5, iclass 14, count 0 2006.173.18:37:57.50#ibcon#read 5, iclass 14, count 0 2006.173.18:37:57.50#ibcon#about to read 6, iclass 14, count 0 2006.173.18:37:57.50#ibcon#read 6, iclass 14, count 0 2006.173.18:37:57.50#ibcon#end of sib2, iclass 14, count 0 2006.173.18:37:57.50#ibcon#*mode == 0, iclass 14, count 0 2006.173.18:37:57.50#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.18:37:57.50#ibcon#[27=USB\r\n] 2006.173.18:37:57.50#ibcon#*before write, iclass 14, count 0 2006.173.18:37:57.50#ibcon#enter sib2, iclass 14, count 0 2006.173.18:37:57.50#ibcon#flushed, iclass 14, count 0 2006.173.18:37:57.50#ibcon#about to write, iclass 14, count 0 2006.173.18:37:57.50#ibcon#wrote, iclass 14, count 0 2006.173.18:37:57.50#ibcon#about to read 3, iclass 14, count 0 2006.173.18:37:57.53#ibcon#read 3, iclass 14, count 0 2006.173.18:37:57.53#ibcon#about to read 4, iclass 14, count 0 2006.173.18:37:57.53#ibcon#read 4, iclass 14, count 0 2006.173.18:37:57.53#ibcon#about to read 5, iclass 14, count 0 2006.173.18:37:57.53#ibcon#read 5, iclass 14, count 0 2006.173.18:37:57.53#ibcon#about to read 6, iclass 14, count 0 2006.173.18:37:57.53#ibcon#read 6, iclass 14, count 0 2006.173.18:37:57.53#ibcon#end of sib2, iclass 14, count 0 2006.173.18:37:57.53#ibcon#*after write, iclass 14, count 0 2006.173.18:37:57.53#ibcon#*before return 0, iclass 14, count 0 2006.173.18:37:57.53#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.18:37:57.53#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.18:37:57.53#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.18:37:57.53#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.18:37:57.53$vck44/vblo=6,719.99 2006.173.18:37:57.53#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.18:37:57.53#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.18:37:57.53#ibcon#ireg 17 cls_cnt 0 2006.173.18:37:57.53#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.18:37:57.53#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.18:37:57.53#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.18:37:57.53#ibcon#enter wrdev, iclass 16, count 0 2006.173.18:37:57.53#ibcon#first serial, iclass 16, count 0 2006.173.18:37:57.53#ibcon#enter sib2, iclass 16, count 0 2006.173.18:37:57.53#ibcon#flushed, iclass 16, count 0 2006.173.18:37:57.53#ibcon#about to write, iclass 16, count 0 2006.173.18:37:57.53#ibcon#wrote, iclass 16, count 0 2006.173.18:37:57.53#ibcon#about to read 3, iclass 16, count 0 2006.173.18:37:57.55#ibcon#read 3, iclass 16, count 0 2006.173.18:37:57.55#ibcon#about to read 4, iclass 16, count 0 2006.173.18:37:57.55#ibcon#read 4, iclass 16, count 0 2006.173.18:37:57.55#ibcon#about to read 5, iclass 16, count 0 2006.173.18:37:57.55#ibcon#read 5, iclass 16, count 0 2006.173.18:37:57.55#ibcon#about to read 6, iclass 16, count 0 2006.173.18:37:57.55#ibcon#read 6, iclass 16, count 0 2006.173.18:37:57.55#ibcon#end of sib2, iclass 16, count 0 2006.173.18:37:57.55#ibcon#*mode == 0, iclass 16, count 0 2006.173.18:37:57.55#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.18:37:57.55#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.18:37:57.55#ibcon#*before write, iclass 16, count 0 2006.173.18:37:57.55#ibcon#enter sib2, iclass 16, count 0 2006.173.18:37:57.55#ibcon#flushed, iclass 16, count 0 2006.173.18:37:57.55#ibcon#about to write, iclass 16, count 0 2006.173.18:37:57.55#ibcon#wrote, iclass 16, count 0 2006.173.18:37:57.55#ibcon#about to read 3, iclass 16, count 0 2006.173.18:37:57.59#ibcon#read 3, iclass 16, count 0 2006.173.18:37:57.59#ibcon#about to read 4, iclass 16, count 0 2006.173.18:37:57.59#ibcon#read 4, iclass 16, count 0 2006.173.18:37:57.59#ibcon#about to read 5, iclass 16, count 0 2006.173.18:37:57.59#ibcon#read 5, iclass 16, count 0 2006.173.18:37:57.59#ibcon#about to read 6, iclass 16, count 0 2006.173.18:37:57.59#ibcon#read 6, iclass 16, count 0 2006.173.18:37:57.59#ibcon#end of sib2, iclass 16, count 0 2006.173.18:37:57.59#ibcon#*after write, iclass 16, count 0 2006.173.18:37:57.59#ibcon#*before return 0, iclass 16, count 0 2006.173.18:37:57.59#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.18:37:57.59#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.18:37:57.59#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.18:37:57.59#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.18:37:57.59$vck44/vb=6,4 2006.173.18:37:57.59#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.18:37:57.59#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.18:37:57.59#ibcon#ireg 11 cls_cnt 2 2006.173.18:37:57.59#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.18:37:57.65#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.18:37:57.65#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.18:37:57.65#ibcon#enter wrdev, iclass 18, count 2 2006.173.18:37:57.65#ibcon#first serial, iclass 18, count 2 2006.173.18:37:57.65#ibcon#enter sib2, iclass 18, count 2 2006.173.18:37:57.65#ibcon#flushed, iclass 18, count 2 2006.173.18:37:57.65#ibcon#about to write, iclass 18, count 2 2006.173.18:37:57.65#ibcon#wrote, iclass 18, count 2 2006.173.18:37:57.65#ibcon#about to read 3, iclass 18, count 2 2006.173.18:37:57.67#ibcon#read 3, iclass 18, count 2 2006.173.18:37:57.67#ibcon#about to read 4, iclass 18, count 2 2006.173.18:37:57.67#ibcon#read 4, iclass 18, count 2 2006.173.18:37:57.67#ibcon#about to read 5, iclass 18, count 2 2006.173.18:37:57.67#ibcon#read 5, iclass 18, count 2 2006.173.18:37:57.67#ibcon#about to read 6, iclass 18, count 2 2006.173.18:37:57.67#ibcon#read 6, iclass 18, count 2 2006.173.18:37:57.67#ibcon#end of sib2, iclass 18, count 2 2006.173.18:37:57.67#ibcon#*mode == 0, iclass 18, count 2 2006.173.18:37:57.67#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.18:37:57.67#ibcon#[27=AT06-04\r\n] 2006.173.18:37:57.67#ibcon#*before write, iclass 18, count 2 2006.173.18:37:57.67#ibcon#enter sib2, iclass 18, count 2 2006.173.18:37:57.67#ibcon#flushed, iclass 18, count 2 2006.173.18:37:57.67#ibcon#about to write, iclass 18, count 2 2006.173.18:37:57.67#ibcon#wrote, iclass 18, count 2 2006.173.18:37:57.67#ibcon#about to read 3, iclass 18, count 2 2006.173.18:37:57.70#ibcon#read 3, iclass 18, count 2 2006.173.18:37:57.70#ibcon#about to read 4, iclass 18, count 2 2006.173.18:37:57.70#ibcon#read 4, iclass 18, count 2 2006.173.18:37:57.70#ibcon#about to read 5, iclass 18, count 2 2006.173.18:37:57.70#ibcon#read 5, iclass 18, count 2 2006.173.18:37:57.70#ibcon#about to read 6, iclass 18, count 2 2006.173.18:37:57.70#ibcon#read 6, iclass 18, count 2 2006.173.18:37:57.70#ibcon#end of sib2, iclass 18, count 2 2006.173.18:37:57.70#ibcon#*after write, iclass 18, count 2 2006.173.18:37:57.70#ibcon#*before return 0, iclass 18, count 2 2006.173.18:37:57.70#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.18:37:57.70#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.18:37:57.70#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.18:37:57.70#ibcon#ireg 7 cls_cnt 0 2006.173.18:37:57.70#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.18:37:57.82#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.18:37:57.82#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.18:37:57.82#ibcon#enter wrdev, iclass 18, count 0 2006.173.18:37:57.82#ibcon#first serial, iclass 18, count 0 2006.173.18:37:57.82#ibcon#enter sib2, iclass 18, count 0 2006.173.18:37:57.82#ibcon#flushed, iclass 18, count 0 2006.173.18:37:57.82#ibcon#about to write, iclass 18, count 0 2006.173.18:37:57.82#ibcon#wrote, iclass 18, count 0 2006.173.18:37:57.82#ibcon#about to read 3, iclass 18, count 0 2006.173.18:37:57.84#ibcon#read 3, iclass 18, count 0 2006.173.18:37:57.84#ibcon#about to read 4, iclass 18, count 0 2006.173.18:37:57.84#ibcon#read 4, iclass 18, count 0 2006.173.18:37:57.84#ibcon#about to read 5, iclass 18, count 0 2006.173.18:37:57.84#ibcon#read 5, iclass 18, count 0 2006.173.18:37:57.84#ibcon#about to read 6, iclass 18, count 0 2006.173.18:37:57.84#ibcon#read 6, iclass 18, count 0 2006.173.18:37:57.84#ibcon#end of sib2, iclass 18, count 0 2006.173.18:37:57.84#ibcon#*mode == 0, iclass 18, count 0 2006.173.18:37:57.84#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.18:37:57.84#ibcon#[27=USB\r\n] 2006.173.18:37:57.84#ibcon#*before write, iclass 18, count 0 2006.173.18:37:57.84#ibcon#enter sib2, iclass 18, count 0 2006.173.18:37:57.84#ibcon#flushed, iclass 18, count 0 2006.173.18:37:57.84#ibcon#about to write, iclass 18, count 0 2006.173.18:37:57.84#ibcon#wrote, iclass 18, count 0 2006.173.18:37:57.84#ibcon#about to read 3, iclass 18, count 0 2006.173.18:37:57.87#ibcon#read 3, iclass 18, count 0 2006.173.18:37:57.87#ibcon#about to read 4, iclass 18, count 0 2006.173.18:37:57.87#ibcon#read 4, iclass 18, count 0 2006.173.18:37:57.87#ibcon#about to read 5, iclass 18, count 0 2006.173.18:37:57.87#ibcon#read 5, iclass 18, count 0 2006.173.18:37:57.87#ibcon#about to read 6, iclass 18, count 0 2006.173.18:37:57.87#ibcon#read 6, iclass 18, count 0 2006.173.18:37:57.87#ibcon#end of sib2, iclass 18, count 0 2006.173.18:37:57.87#ibcon#*after write, iclass 18, count 0 2006.173.18:37:57.87#ibcon#*before return 0, iclass 18, count 0 2006.173.18:37:57.87#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.18:37:57.87#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.18:37:57.87#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.18:37:57.87#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.18:37:57.87$vck44/vblo=7,734.99 2006.173.18:37:57.87#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.18:37:57.87#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.18:37:57.87#ibcon#ireg 17 cls_cnt 0 2006.173.18:37:57.87#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.18:37:57.87#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.18:37:57.87#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.18:37:57.87#ibcon#enter wrdev, iclass 20, count 0 2006.173.18:37:57.87#ibcon#first serial, iclass 20, count 0 2006.173.18:37:57.87#ibcon#enter sib2, iclass 20, count 0 2006.173.18:37:57.87#ibcon#flushed, iclass 20, count 0 2006.173.18:37:57.87#ibcon#about to write, iclass 20, count 0 2006.173.18:37:57.87#ibcon#wrote, iclass 20, count 0 2006.173.18:37:57.87#ibcon#about to read 3, iclass 20, count 0 2006.173.18:37:57.89#ibcon#read 3, iclass 20, count 0 2006.173.18:37:57.89#ibcon#about to read 4, iclass 20, count 0 2006.173.18:37:57.89#ibcon#read 4, iclass 20, count 0 2006.173.18:37:57.89#ibcon#about to read 5, iclass 20, count 0 2006.173.18:37:57.89#ibcon#read 5, iclass 20, count 0 2006.173.18:37:57.89#ibcon#about to read 6, iclass 20, count 0 2006.173.18:37:57.89#ibcon#read 6, iclass 20, count 0 2006.173.18:37:57.89#ibcon#end of sib2, iclass 20, count 0 2006.173.18:37:57.89#ibcon#*mode == 0, iclass 20, count 0 2006.173.18:37:57.89#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.18:37:57.89#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.18:37:57.89#ibcon#*before write, iclass 20, count 0 2006.173.18:37:57.89#ibcon#enter sib2, iclass 20, count 0 2006.173.18:37:57.89#ibcon#flushed, iclass 20, count 0 2006.173.18:37:57.89#ibcon#about to write, iclass 20, count 0 2006.173.18:37:57.89#ibcon#wrote, iclass 20, count 0 2006.173.18:37:57.89#ibcon#about to read 3, iclass 20, count 0 2006.173.18:37:57.93#ibcon#read 3, iclass 20, count 0 2006.173.18:37:57.93#ibcon#about to read 4, iclass 20, count 0 2006.173.18:37:57.93#ibcon#read 4, iclass 20, count 0 2006.173.18:37:57.93#ibcon#about to read 5, iclass 20, count 0 2006.173.18:37:57.93#ibcon#read 5, iclass 20, count 0 2006.173.18:37:57.93#ibcon#about to read 6, iclass 20, count 0 2006.173.18:37:57.93#ibcon#read 6, iclass 20, count 0 2006.173.18:37:57.93#ibcon#end of sib2, iclass 20, count 0 2006.173.18:37:57.93#ibcon#*after write, iclass 20, count 0 2006.173.18:37:57.93#ibcon#*before return 0, iclass 20, count 0 2006.173.18:37:57.93#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.18:37:57.93#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.18:37:57.93#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.18:37:57.93#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.18:37:57.93$vck44/vb=7,4 2006.173.18:37:57.93#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.18:37:57.93#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.18:37:57.93#ibcon#ireg 11 cls_cnt 2 2006.173.18:37:57.93#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.18:37:57.99#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.18:37:57.99#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.18:37:57.99#ibcon#enter wrdev, iclass 22, count 2 2006.173.18:37:57.99#ibcon#first serial, iclass 22, count 2 2006.173.18:37:57.99#ibcon#enter sib2, iclass 22, count 2 2006.173.18:37:57.99#ibcon#flushed, iclass 22, count 2 2006.173.18:37:57.99#ibcon#about to write, iclass 22, count 2 2006.173.18:37:57.99#ibcon#wrote, iclass 22, count 2 2006.173.18:37:57.99#ibcon#about to read 3, iclass 22, count 2 2006.173.18:37:58.01#ibcon#read 3, iclass 22, count 2 2006.173.18:37:58.01#ibcon#about to read 4, iclass 22, count 2 2006.173.18:37:58.01#ibcon#read 4, iclass 22, count 2 2006.173.18:37:58.01#ibcon#about to read 5, iclass 22, count 2 2006.173.18:37:58.01#ibcon#read 5, iclass 22, count 2 2006.173.18:37:58.01#ibcon#about to read 6, iclass 22, count 2 2006.173.18:37:58.01#ibcon#read 6, iclass 22, count 2 2006.173.18:37:58.01#ibcon#end of sib2, iclass 22, count 2 2006.173.18:37:58.01#ibcon#*mode == 0, iclass 22, count 2 2006.173.18:37:58.01#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.18:37:58.01#ibcon#[27=AT07-04\r\n] 2006.173.18:37:58.01#ibcon#*before write, iclass 22, count 2 2006.173.18:37:58.01#ibcon#enter sib2, iclass 22, count 2 2006.173.18:37:58.01#ibcon#flushed, iclass 22, count 2 2006.173.18:37:58.01#ibcon#about to write, iclass 22, count 2 2006.173.18:37:58.01#ibcon#wrote, iclass 22, count 2 2006.173.18:37:58.01#ibcon#about to read 3, iclass 22, count 2 2006.173.18:37:58.04#ibcon#read 3, iclass 22, count 2 2006.173.18:37:58.04#ibcon#about to read 4, iclass 22, count 2 2006.173.18:37:58.04#ibcon#read 4, iclass 22, count 2 2006.173.18:37:58.04#ibcon#about to read 5, iclass 22, count 2 2006.173.18:37:58.04#ibcon#read 5, iclass 22, count 2 2006.173.18:37:58.04#ibcon#about to read 6, iclass 22, count 2 2006.173.18:37:58.04#ibcon#read 6, iclass 22, count 2 2006.173.18:37:58.04#ibcon#end of sib2, iclass 22, count 2 2006.173.18:37:58.04#ibcon#*after write, iclass 22, count 2 2006.173.18:37:58.04#ibcon#*before return 0, iclass 22, count 2 2006.173.18:37:58.04#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.18:37:58.04#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.18:37:58.04#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.18:37:58.04#ibcon#ireg 7 cls_cnt 0 2006.173.18:37:58.04#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.18:37:58.16#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.18:37:58.16#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.18:37:58.16#ibcon#enter wrdev, iclass 22, count 0 2006.173.18:37:58.16#ibcon#first serial, iclass 22, count 0 2006.173.18:37:58.16#ibcon#enter sib2, iclass 22, count 0 2006.173.18:37:58.16#ibcon#flushed, iclass 22, count 0 2006.173.18:37:58.16#ibcon#about to write, iclass 22, count 0 2006.173.18:37:58.16#ibcon#wrote, iclass 22, count 0 2006.173.18:37:58.16#ibcon#about to read 3, iclass 22, count 0 2006.173.18:37:58.18#ibcon#read 3, iclass 22, count 0 2006.173.18:37:58.18#ibcon#about to read 4, iclass 22, count 0 2006.173.18:37:58.18#ibcon#read 4, iclass 22, count 0 2006.173.18:37:58.18#ibcon#about to read 5, iclass 22, count 0 2006.173.18:37:58.18#ibcon#read 5, iclass 22, count 0 2006.173.18:37:58.18#ibcon#about to read 6, iclass 22, count 0 2006.173.18:37:58.18#ibcon#read 6, iclass 22, count 0 2006.173.18:37:58.18#ibcon#end of sib2, iclass 22, count 0 2006.173.18:37:58.18#ibcon#*mode == 0, iclass 22, count 0 2006.173.18:37:58.18#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.18:37:58.18#ibcon#[27=USB\r\n] 2006.173.18:37:58.18#ibcon#*before write, iclass 22, count 0 2006.173.18:37:58.18#ibcon#enter sib2, iclass 22, count 0 2006.173.18:37:58.18#ibcon#flushed, iclass 22, count 0 2006.173.18:37:58.18#ibcon#about to write, iclass 22, count 0 2006.173.18:37:58.18#ibcon#wrote, iclass 22, count 0 2006.173.18:37:58.18#ibcon#about to read 3, iclass 22, count 0 2006.173.18:37:58.21#ibcon#read 3, iclass 22, count 0 2006.173.18:37:58.21#ibcon#about to read 4, iclass 22, count 0 2006.173.18:37:58.21#ibcon#read 4, iclass 22, count 0 2006.173.18:37:58.21#ibcon#about to read 5, iclass 22, count 0 2006.173.18:37:58.21#ibcon#read 5, iclass 22, count 0 2006.173.18:37:58.21#ibcon#about to read 6, iclass 22, count 0 2006.173.18:37:58.21#ibcon#read 6, iclass 22, count 0 2006.173.18:37:58.21#ibcon#end of sib2, iclass 22, count 0 2006.173.18:37:58.21#ibcon#*after write, iclass 22, count 0 2006.173.18:37:58.21#ibcon#*before return 0, iclass 22, count 0 2006.173.18:37:58.21#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.18:37:58.21#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.18:37:58.21#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.18:37:58.21#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.18:37:58.21$vck44/vblo=8,744.99 2006.173.18:37:58.21#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.18:37:58.21#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.18:37:58.21#ibcon#ireg 17 cls_cnt 0 2006.173.18:37:58.21#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.18:37:58.21#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.18:37:58.21#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.18:37:58.21#ibcon#enter wrdev, iclass 24, count 0 2006.173.18:37:58.21#ibcon#first serial, iclass 24, count 0 2006.173.18:37:58.21#ibcon#enter sib2, iclass 24, count 0 2006.173.18:37:58.21#ibcon#flushed, iclass 24, count 0 2006.173.18:37:58.21#ibcon#about to write, iclass 24, count 0 2006.173.18:37:58.22#ibcon#wrote, iclass 24, count 0 2006.173.18:37:58.22#ibcon#about to read 3, iclass 24, count 0 2006.173.18:37:58.23#ibcon#read 3, iclass 24, count 0 2006.173.18:37:58.23#ibcon#about to read 4, iclass 24, count 0 2006.173.18:37:58.23#ibcon#read 4, iclass 24, count 0 2006.173.18:37:58.23#ibcon#about to read 5, iclass 24, count 0 2006.173.18:37:58.23#ibcon#read 5, iclass 24, count 0 2006.173.18:37:58.23#ibcon#about to read 6, iclass 24, count 0 2006.173.18:37:58.23#ibcon#read 6, iclass 24, count 0 2006.173.18:37:58.23#ibcon#end of sib2, iclass 24, count 0 2006.173.18:37:58.23#ibcon#*mode == 0, iclass 24, count 0 2006.173.18:37:58.23#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.18:37:58.23#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.18:37:58.23#ibcon#*before write, iclass 24, count 0 2006.173.18:37:58.23#ibcon#enter sib2, iclass 24, count 0 2006.173.18:37:58.23#ibcon#flushed, iclass 24, count 0 2006.173.18:37:58.23#ibcon#about to write, iclass 24, count 0 2006.173.18:37:58.23#ibcon#wrote, iclass 24, count 0 2006.173.18:37:58.23#ibcon#about to read 3, iclass 24, count 0 2006.173.18:37:58.27#ibcon#read 3, iclass 24, count 0 2006.173.18:37:58.27#ibcon#about to read 4, iclass 24, count 0 2006.173.18:37:58.27#ibcon#read 4, iclass 24, count 0 2006.173.18:37:58.27#ibcon#about to read 5, iclass 24, count 0 2006.173.18:37:58.27#ibcon#read 5, iclass 24, count 0 2006.173.18:37:58.27#ibcon#about to read 6, iclass 24, count 0 2006.173.18:37:58.27#ibcon#read 6, iclass 24, count 0 2006.173.18:37:58.27#ibcon#end of sib2, iclass 24, count 0 2006.173.18:37:58.27#ibcon#*after write, iclass 24, count 0 2006.173.18:37:58.27#ibcon#*before return 0, iclass 24, count 0 2006.173.18:37:58.27#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.18:37:58.27#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.18:37:58.27#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.18:37:58.27#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.18:37:58.27$vck44/vb=8,4 2006.173.18:37:58.27#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.18:37:58.27#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.18:37:58.27#ibcon#ireg 11 cls_cnt 2 2006.173.18:37:58.27#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.18:37:58.33#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.18:37:58.33#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.18:37:58.33#ibcon#enter wrdev, iclass 26, count 2 2006.173.18:37:58.33#ibcon#first serial, iclass 26, count 2 2006.173.18:37:58.33#ibcon#enter sib2, iclass 26, count 2 2006.173.18:37:58.33#ibcon#flushed, iclass 26, count 2 2006.173.18:37:58.33#ibcon#about to write, iclass 26, count 2 2006.173.18:37:58.33#ibcon#wrote, iclass 26, count 2 2006.173.18:37:58.33#ibcon#about to read 3, iclass 26, count 2 2006.173.18:37:58.35#ibcon#read 3, iclass 26, count 2 2006.173.18:37:58.35#ibcon#about to read 4, iclass 26, count 2 2006.173.18:37:58.35#ibcon#read 4, iclass 26, count 2 2006.173.18:37:58.35#ibcon#about to read 5, iclass 26, count 2 2006.173.18:37:58.35#ibcon#read 5, iclass 26, count 2 2006.173.18:37:58.35#ibcon#about to read 6, iclass 26, count 2 2006.173.18:37:58.35#ibcon#read 6, iclass 26, count 2 2006.173.18:37:58.35#ibcon#end of sib2, iclass 26, count 2 2006.173.18:37:58.35#ibcon#*mode == 0, iclass 26, count 2 2006.173.18:37:58.35#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.18:37:58.35#ibcon#[27=AT08-04\r\n] 2006.173.18:37:58.35#ibcon#*before write, iclass 26, count 2 2006.173.18:37:58.35#ibcon#enter sib2, iclass 26, count 2 2006.173.18:37:58.35#ibcon#flushed, iclass 26, count 2 2006.173.18:37:58.35#ibcon#about to write, iclass 26, count 2 2006.173.18:37:58.35#ibcon#wrote, iclass 26, count 2 2006.173.18:37:58.35#ibcon#about to read 3, iclass 26, count 2 2006.173.18:37:58.38#ibcon#read 3, iclass 26, count 2 2006.173.18:37:58.38#ibcon#about to read 4, iclass 26, count 2 2006.173.18:37:58.38#ibcon#read 4, iclass 26, count 2 2006.173.18:37:58.38#ibcon#about to read 5, iclass 26, count 2 2006.173.18:37:58.38#ibcon#read 5, iclass 26, count 2 2006.173.18:37:58.38#ibcon#about to read 6, iclass 26, count 2 2006.173.18:37:58.38#ibcon#read 6, iclass 26, count 2 2006.173.18:37:58.38#ibcon#end of sib2, iclass 26, count 2 2006.173.18:37:58.38#ibcon#*after write, iclass 26, count 2 2006.173.18:37:58.38#ibcon#*before return 0, iclass 26, count 2 2006.173.18:37:58.38#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.18:37:58.38#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.18:37:58.38#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.18:37:58.38#ibcon#ireg 7 cls_cnt 0 2006.173.18:37:58.38#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.18:37:58.50#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.18:37:58.50#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.18:37:58.50#ibcon#enter wrdev, iclass 26, count 0 2006.173.18:37:58.50#ibcon#first serial, iclass 26, count 0 2006.173.18:37:58.50#ibcon#enter sib2, iclass 26, count 0 2006.173.18:37:58.50#ibcon#flushed, iclass 26, count 0 2006.173.18:37:58.50#ibcon#about to write, iclass 26, count 0 2006.173.18:37:58.50#ibcon#wrote, iclass 26, count 0 2006.173.18:37:58.50#ibcon#about to read 3, iclass 26, count 0 2006.173.18:37:58.52#ibcon#read 3, iclass 26, count 0 2006.173.18:37:58.52#ibcon#about to read 4, iclass 26, count 0 2006.173.18:37:58.52#ibcon#read 4, iclass 26, count 0 2006.173.18:37:58.52#ibcon#about to read 5, iclass 26, count 0 2006.173.18:37:58.52#ibcon#read 5, iclass 26, count 0 2006.173.18:37:58.52#ibcon#about to read 6, iclass 26, count 0 2006.173.18:37:58.52#ibcon#read 6, iclass 26, count 0 2006.173.18:37:58.52#ibcon#end of sib2, iclass 26, count 0 2006.173.18:37:58.52#ibcon#*mode == 0, iclass 26, count 0 2006.173.18:37:58.52#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.18:37:58.52#ibcon#[27=USB\r\n] 2006.173.18:37:58.52#ibcon#*before write, iclass 26, count 0 2006.173.18:37:58.52#ibcon#enter sib2, iclass 26, count 0 2006.173.18:37:58.52#ibcon#flushed, iclass 26, count 0 2006.173.18:37:58.52#ibcon#about to write, iclass 26, count 0 2006.173.18:37:58.52#ibcon#wrote, iclass 26, count 0 2006.173.18:37:58.52#ibcon#about to read 3, iclass 26, count 0 2006.173.18:37:58.55#ibcon#read 3, iclass 26, count 0 2006.173.18:37:58.55#ibcon#about to read 4, iclass 26, count 0 2006.173.18:37:58.55#ibcon#read 4, iclass 26, count 0 2006.173.18:37:58.55#ibcon#about to read 5, iclass 26, count 0 2006.173.18:37:58.55#ibcon#read 5, iclass 26, count 0 2006.173.18:37:58.55#ibcon#about to read 6, iclass 26, count 0 2006.173.18:37:58.55#ibcon#read 6, iclass 26, count 0 2006.173.18:37:58.55#ibcon#end of sib2, iclass 26, count 0 2006.173.18:37:58.55#ibcon#*after write, iclass 26, count 0 2006.173.18:37:58.55#ibcon#*before return 0, iclass 26, count 0 2006.173.18:37:58.55#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.18:37:58.55#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.18:37:58.55#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.18:37:58.55#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.18:37:58.55$vck44/vabw=wide 2006.173.18:37:58.55#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.18:37:58.55#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.18:37:58.55#ibcon#ireg 8 cls_cnt 0 2006.173.18:37:58.55#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.18:37:58.55#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.18:37:58.55#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.18:37:58.55#ibcon#enter wrdev, iclass 28, count 0 2006.173.18:37:58.55#ibcon#first serial, iclass 28, count 0 2006.173.18:37:58.55#ibcon#enter sib2, iclass 28, count 0 2006.173.18:37:58.55#ibcon#flushed, iclass 28, count 0 2006.173.18:37:58.55#ibcon#about to write, iclass 28, count 0 2006.173.18:37:58.55#ibcon#wrote, iclass 28, count 0 2006.173.18:37:58.55#ibcon#about to read 3, iclass 28, count 0 2006.173.18:37:58.57#ibcon#read 3, iclass 28, count 0 2006.173.18:37:58.57#ibcon#about to read 4, iclass 28, count 0 2006.173.18:37:58.57#ibcon#read 4, iclass 28, count 0 2006.173.18:37:58.57#ibcon#about to read 5, iclass 28, count 0 2006.173.18:37:58.57#ibcon#read 5, iclass 28, count 0 2006.173.18:37:58.57#ibcon#about to read 6, iclass 28, count 0 2006.173.18:37:58.57#ibcon#read 6, iclass 28, count 0 2006.173.18:37:58.57#ibcon#end of sib2, iclass 28, count 0 2006.173.18:37:58.57#ibcon#*mode == 0, iclass 28, count 0 2006.173.18:37:58.57#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.18:37:58.57#ibcon#[25=BW32\r\n] 2006.173.18:37:58.57#ibcon#*before write, iclass 28, count 0 2006.173.18:37:58.57#ibcon#enter sib2, iclass 28, count 0 2006.173.18:37:58.57#ibcon#flushed, iclass 28, count 0 2006.173.18:37:58.57#ibcon#about to write, iclass 28, count 0 2006.173.18:37:58.57#ibcon#wrote, iclass 28, count 0 2006.173.18:37:58.57#ibcon#about to read 3, iclass 28, count 0 2006.173.18:37:58.60#ibcon#read 3, iclass 28, count 0 2006.173.18:37:58.60#ibcon#about to read 4, iclass 28, count 0 2006.173.18:37:58.60#ibcon#read 4, iclass 28, count 0 2006.173.18:37:58.60#ibcon#about to read 5, iclass 28, count 0 2006.173.18:37:58.60#ibcon#read 5, iclass 28, count 0 2006.173.18:37:58.60#ibcon#about to read 6, iclass 28, count 0 2006.173.18:37:58.60#ibcon#read 6, iclass 28, count 0 2006.173.18:37:58.60#ibcon#end of sib2, iclass 28, count 0 2006.173.18:37:58.60#ibcon#*after write, iclass 28, count 0 2006.173.18:37:58.60#ibcon#*before return 0, iclass 28, count 0 2006.173.18:37:58.60#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.18:37:58.60#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.18:37:58.60#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.18:37:58.60#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.18:37:58.60$vck44/vbbw=wide 2006.173.18:37:58.60#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.18:37:58.60#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.18:37:58.60#ibcon#ireg 8 cls_cnt 0 2006.173.18:37:58.60#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.18:37:58.67#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.18:37:58.67#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.18:37:58.67#ibcon#enter wrdev, iclass 30, count 0 2006.173.18:37:58.67#ibcon#first serial, iclass 30, count 0 2006.173.18:37:58.67#ibcon#enter sib2, iclass 30, count 0 2006.173.18:37:58.67#ibcon#flushed, iclass 30, count 0 2006.173.18:37:58.67#ibcon#about to write, iclass 30, count 0 2006.173.18:37:58.67#ibcon#wrote, iclass 30, count 0 2006.173.18:37:58.67#ibcon#about to read 3, iclass 30, count 0 2006.173.18:37:58.69#ibcon#read 3, iclass 30, count 0 2006.173.18:37:58.69#ibcon#about to read 4, iclass 30, count 0 2006.173.18:37:58.69#ibcon#read 4, iclass 30, count 0 2006.173.18:37:58.69#ibcon#about to read 5, iclass 30, count 0 2006.173.18:37:58.69#ibcon#read 5, iclass 30, count 0 2006.173.18:37:58.69#ibcon#about to read 6, iclass 30, count 0 2006.173.18:37:58.69#ibcon#read 6, iclass 30, count 0 2006.173.18:37:58.69#ibcon#end of sib2, iclass 30, count 0 2006.173.18:37:58.69#ibcon#*mode == 0, iclass 30, count 0 2006.173.18:37:58.69#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.18:37:58.69#ibcon#[27=BW32\r\n] 2006.173.18:37:58.69#ibcon#*before write, iclass 30, count 0 2006.173.18:37:58.69#ibcon#enter sib2, iclass 30, count 0 2006.173.18:37:58.69#ibcon#flushed, iclass 30, count 0 2006.173.18:37:58.69#ibcon#about to write, iclass 30, count 0 2006.173.18:37:58.69#ibcon#wrote, iclass 30, count 0 2006.173.18:37:58.69#ibcon#about to read 3, iclass 30, count 0 2006.173.18:37:58.72#ibcon#read 3, iclass 30, count 0 2006.173.18:37:58.72#ibcon#about to read 4, iclass 30, count 0 2006.173.18:37:58.72#ibcon#read 4, iclass 30, count 0 2006.173.18:37:58.72#ibcon#about to read 5, iclass 30, count 0 2006.173.18:37:58.72#ibcon#read 5, iclass 30, count 0 2006.173.18:37:58.72#ibcon#about to read 6, iclass 30, count 0 2006.173.18:37:58.72#ibcon#read 6, iclass 30, count 0 2006.173.18:37:58.72#ibcon#end of sib2, iclass 30, count 0 2006.173.18:37:58.72#ibcon#*after write, iclass 30, count 0 2006.173.18:37:58.72#ibcon#*before return 0, iclass 30, count 0 2006.173.18:37:58.72#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.18:37:58.72#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.18:37:58.72#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.18:37:58.72#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.18:37:58.72$setupk4/ifdk4 2006.173.18:37:58.72$ifdk4/lo= 2006.173.18:37:58.73$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.18:37:58.73$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.18:37:58.73$ifdk4/patch= 2006.173.18:37:58.73$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.18:37:58.73$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.18:37:58.73$setupk4/!*+20s 2006.173.18:38:05.18#abcon#<5=/14 1.0 1.9 19.821001002.3\r\n> 2006.173.18:38:05.20#abcon#{5=INTERFACE CLEAR} 2006.173.18:38:05.26#abcon#[5=S1D000X0/0*\r\n] 2006.173.18:38:13.25$setupk4/"tpicd 2006.173.18:38:13.25$setupk4/echo=off 2006.173.18:38:13.25$setupk4/xlog=off 2006.173.18:38:13.25:!2006.173.18:42:49 2006.173.18:38:38.14#trakl#Source acquired 2006.173.18:38:39.14#flagr#flagr/antenna,acquired 2006.173.18:42:49.00:preob 2006.173.18:42:49.14/onsource/TRACKING 2006.173.18:42:49.14:!2006.173.18:42:59 2006.173.18:42:59.00:"tape 2006.173.18:42:59.00:"st=record 2006.173.18:42:59.00:data_valid=on 2006.173.18:42:59.00:midob 2006.173.18:43:00.14/onsource/TRACKING 2006.173.18:43:00.14/wx/19.76,1002.4,100 2006.173.18:43:00.24/cable/+6.5153E-03 2006.173.18:43:01.33/va/01,07,usb,yes,35,37 2006.173.18:43:01.33/va/02,06,usb,yes,35,35 2006.173.18:43:01.33/va/03,05,usb,yes,44,46 2006.173.18:43:01.33/va/04,06,usb,yes,35,37 2006.173.18:43:01.33/va/05,04,usb,yes,28,28 2006.173.18:43:01.33/va/06,03,usb,yes,39,39 2006.173.18:43:01.33/va/07,04,usb,yes,31,32 2006.173.18:43:01.33/va/08,04,usb,yes,27,32 2006.173.18:43:01.56/valo/01,524.99,yes,locked 2006.173.18:43:01.56/valo/02,534.99,yes,locked 2006.173.18:43:01.56/valo/03,564.99,yes,locked 2006.173.18:43:01.56/valo/04,624.99,yes,locked 2006.173.18:43:01.56/valo/05,734.99,yes,locked 2006.173.18:43:01.56/valo/06,814.99,yes,locked 2006.173.18:43:01.56/valo/07,864.99,yes,locked 2006.173.18:43:01.56/valo/08,884.99,yes,locked 2006.173.18:43:02.65/vb/01,04,usb,yes,29,27 2006.173.18:43:02.65/vb/02,04,usb,yes,31,31 2006.173.18:43:02.65/vb/03,04,usb,yes,28,31 2006.173.18:43:02.65/vb/04,04,usb,yes,32,31 2006.173.18:43:02.65/vb/05,04,usb,yes,25,27 2006.173.18:43:02.65/vb/06,04,usb,yes,29,26 2006.173.18:43:02.65/vb/07,04,usb,yes,29,29 2006.173.18:43:02.65/vb/08,04,usb,yes,27,30 2006.173.18:43:02.88/vblo/01,629.99,yes,locked 2006.173.18:43:02.88/vblo/02,634.99,yes,locked 2006.173.18:43:02.88/vblo/03,649.99,yes,locked 2006.173.18:43:02.88/vblo/04,679.99,yes,locked 2006.173.18:43:02.88/vblo/05,709.99,yes,locked 2006.173.18:43:02.88/vblo/06,719.99,yes,locked 2006.173.18:43:02.88/vblo/07,734.99,yes,locked 2006.173.18:43:02.88/vblo/08,744.99,yes,locked 2006.173.18:43:03.03/vabw/8 2006.173.18:43:03.18/vbbw/8 2006.173.18:43:03.27/xfe/off,on,14.7 2006.173.18:43:03.68/ifatt/23,28,28,28 2006.173.18:43:04.07/fmout-gps/S +3.88E-07 2006.173.18:43:04.11:!2006.173.18:46:29 2006.173.18:46:29.01:data_valid=off 2006.173.18:46:29.01:"et 2006.173.18:46:29.01:!+3s 2006.173.18:46:32.02:"tape 2006.173.18:46:32.02:postob 2006.173.18:46:32.12/cable/+6.5142E-03 2006.173.18:46:32.12/wx/19.70,1002.3,100 2006.173.18:46:32.18/fmout-gps/S +3.91E-07 2006.173.18:46:32.18:scan_name=173-1847,jd0606,110 2006.173.18:46:32.18:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.173.18:46:33.14#flagr#flagr/antenna,new-source 2006.173.18:46:33.14:checkk5 2006.173.18:46:33.54/chk_autoobs//k5ts1/ autoobs is running! 2006.173.18:46:33.95/chk_autoobs//k5ts2/ autoobs is running! 2006.173.18:46:34.36/chk_autoobs//k5ts3/ autoobs is running! 2006.173.18:46:34.77/chk_autoobs//k5ts4/ autoobs is running! 2006.173.18:46:35.16/chk_obsdata//k5ts1/T1731842??a.dat file size is correct (nominal:840MB, actual:840MB). 2006.173.18:46:35.55/chk_obsdata//k5ts2/T1731842??b.dat file size is correct (nominal:840MB, actual:840MB). 2006.173.18:46:35.96/chk_obsdata//k5ts3/T1731842??c.dat file size is correct (nominal:840MB, actual:840MB). 2006.173.18:46:36.37/chk_obsdata//k5ts4/T1731842??d.dat file size is correct (nominal:840MB, actual:840MB). 2006.173.18:46:37.09/k5log//k5ts1_log_newline 2006.173.18:46:37.79/k5log//k5ts2_log_newline 2006.173.18:46:38.50/k5log//k5ts3_log_newline 2006.173.18:46:39.20/k5log//k5ts4_log_newline 2006.173.18:46:39.22/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.18:46:39.22:setupk4=1 2006.173.18:46:39.22$setupk4/echo=on 2006.173.18:46:39.22$setupk4/pcalon 2006.173.18:46:39.22$pcalon/"no phase cal control is implemented here 2006.173.18:46:39.22$setupk4/"tpicd=stop 2006.173.18:46:39.22$setupk4/"rec=synch_on 2006.173.18:46:39.22$setupk4/"rec_mode=128 2006.173.18:46:39.22$setupk4/!* 2006.173.18:46:39.22$setupk4/recpk4 2006.173.18:46:39.22$recpk4/recpatch= 2006.173.18:46:39.23$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.18:46:39.23$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.18:46:39.23$setupk4/vck44 2006.173.18:46:39.23$vck44/valo=1,524.99 2006.173.18:46:39.23#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.18:46:39.23#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.18:46:39.23#ibcon#ireg 17 cls_cnt 0 2006.173.18:46:39.23#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.18:46:39.23#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.18:46:39.23#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.18:46:39.23#ibcon#enter wrdev, iclass 23, count 0 2006.173.18:46:39.23#ibcon#first serial, iclass 23, count 0 2006.173.18:46:39.23#ibcon#enter sib2, iclass 23, count 0 2006.173.18:46:39.23#ibcon#flushed, iclass 23, count 0 2006.173.18:46:39.23#ibcon#about to write, iclass 23, count 0 2006.173.18:46:39.23#ibcon#wrote, iclass 23, count 0 2006.173.18:46:39.23#ibcon#about to read 3, iclass 23, count 0 2006.173.18:46:39.24#ibcon#read 3, iclass 23, count 0 2006.173.18:46:39.24#ibcon#about to read 4, iclass 23, count 0 2006.173.18:46:39.24#ibcon#read 4, iclass 23, count 0 2006.173.18:46:39.24#ibcon#about to read 5, iclass 23, count 0 2006.173.18:46:39.24#ibcon#read 5, iclass 23, count 0 2006.173.18:46:39.24#ibcon#about to read 6, iclass 23, count 0 2006.173.18:46:39.24#ibcon#read 6, iclass 23, count 0 2006.173.18:46:39.24#ibcon#end of sib2, iclass 23, count 0 2006.173.18:46:39.24#ibcon#*mode == 0, iclass 23, count 0 2006.173.18:46:39.24#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.18:46:39.24#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.18:46:39.24#ibcon#*before write, iclass 23, count 0 2006.173.18:46:39.24#ibcon#enter sib2, iclass 23, count 0 2006.173.18:46:39.24#ibcon#flushed, iclass 23, count 0 2006.173.18:46:39.24#ibcon#about to write, iclass 23, count 0 2006.173.18:46:39.24#ibcon#wrote, iclass 23, count 0 2006.173.18:46:39.24#ibcon#about to read 3, iclass 23, count 0 2006.173.18:46:39.29#ibcon#read 3, iclass 23, count 0 2006.173.18:46:39.29#ibcon#about to read 4, iclass 23, count 0 2006.173.18:46:39.29#ibcon#read 4, iclass 23, count 0 2006.173.18:46:39.29#ibcon#about to read 5, iclass 23, count 0 2006.173.18:46:39.29#ibcon#read 5, iclass 23, count 0 2006.173.18:46:39.29#ibcon#about to read 6, iclass 23, count 0 2006.173.18:46:39.29#ibcon#read 6, iclass 23, count 0 2006.173.18:46:39.29#ibcon#end of sib2, iclass 23, count 0 2006.173.18:46:39.29#ibcon#*after write, iclass 23, count 0 2006.173.18:46:39.29#ibcon#*before return 0, iclass 23, count 0 2006.173.18:46:39.29#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.18:46:39.29#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.18:46:39.29#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.18:46:39.29#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.18:46:39.29$vck44/va=1,7 2006.173.18:46:39.29#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.18:46:39.29#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.18:46:39.29#ibcon#ireg 11 cls_cnt 2 2006.173.18:46:39.29#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.18:46:39.29#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.18:46:39.29#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.18:46:39.29#ibcon#enter wrdev, iclass 25, count 2 2006.173.18:46:39.29#ibcon#first serial, iclass 25, count 2 2006.173.18:46:39.29#ibcon#enter sib2, iclass 25, count 2 2006.173.18:46:39.29#ibcon#flushed, iclass 25, count 2 2006.173.18:46:39.29#ibcon#about to write, iclass 25, count 2 2006.173.18:46:39.29#ibcon#wrote, iclass 25, count 2 2006.173.18:46:39.29#ibcon#about to read 3, iclass 25, count 2 2006.173.18:46:39.31#ibcon#read 3, iclass 25, count 2 2006.173.18:46:39.31#ibcon#about to read 4, iclass 25, count 2 2006.173.18:46:39.31#ibcon#read 4, iclass 25, count 2 2006.173.18:46:39.31#ibcon#about to read 5, iclass 25, count 2 2006.173.18:46:39.31#ibcon#read 5, iclass 25, count 2 2006.173.18:46:39.31#ibcon#about to read 6, iclass 25, count 2 2006.173.18:46:39.31#ibcon#read 6, iclass 25, count 2 2006.173.18:46:39.31#ibcon#end of sib2, iclass 25, count 2 2006.173.18:46:39.31#ibcon#*mode == 0, iclass 25, count 2 2006.173.18:46:39.31#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.18:46:39.31#ibcon#[25=AT01-07\r\n] 2006.173.18:46:39.31#ibcon#*before write, iclass 25, count 2 2006.173.18:46:39.31#ibcon#enter sib2, iclass 25, count 2 2006.173.18:46:39.31#ibcon#flushed, iclass 25, count 2 2006.173.18:46:39.31#ibcon#about to write, iclass 25, count 2 2006.173.18:46:39.31#ibcon#wrote, iclass 25, count 2 2006.173.18:46:39.31#ibcon#about to read 3, iclass 25, count 2 2006.173.18:46:39.34#ibcon#read 3, iclass 25, count 2 2006.173.18:46:39.34#ibcon#about to read 4, iclass 25, count 2 2006.173.18:46:39.34#ibcon#read 4, iclass 25, count 2 2006.173.18:46:39.34#ibcon#about to read 5, iclass 25, count 2 2006.173.18:46:39.34#ibcon#read 5, iclass 25, count 2 2006.173.18:46:39.34#ibcon#about to read 6, iclass 25, count 2 2006.173.18:46:39.34#ibcon#read 6, iclass 25, count 2 2006.173.18:46:39.34#ibcon#end of sib2, iclass 25, count 2 2006.173.18:46:39.34#ibcon#*after write, iclass 25, count 2 2006.173.18:46:39.34#ibcon#*before return 0, iclass 25, count 2 2006.173.18:46:39.34#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.18:46:39.34#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.18:46:39.34#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.18:46:39.34#ibcon#ireg 7 cls_cnt 0 2006.173.18:46:39.34#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.18:46:39.46#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.18:46:39.46#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.18:46:39.46#ibcon#enter wrdev, iclass 25, count 0 2006.173.18:46:39.46#ibcon#first serial, iclass 25, count 0 2006.173.18:46:39.46#ibcon#enter sib2, iclass 25, count 0 2006.173.18:46:39.46#ibcon#flushed, iclass 25, count 0 2006.173.18:46:39.46#ibcon#about to write, iclass 25, count 0 2006.173.18:46:39.46#ibcon#wrote, iclass 25, count 0 2006.173.18:46:39.46#ibcon#about to read 3, iclass 25, count 0 2006.173.18:46:39.48#ibcon#read 3, iclass 25, count 0 2006.173.18:46:39.48#ibcon#about to read 4, iclass 25, count 0 2006.173.18:46:39.48#ibcon#read 4, iclass 25, count 0 2006.173.18:46:39.48#ibcon#about to read 5, iclass 25, count 0 2006.173.18:46:39.48#ibcon#read 5, iclass 25, count 0 2006.173.18:46:39.48#ibcon#about to read 6, iclass 25, count 0 2006.173.18:46:39.48#ibcon#read 6, iclass 25, count 0 2006.173.18:46:39.48#ibcon#end of sib2, iclass 25, count 0 2006.173.18:46:39.48#ibcon#*mode == 0, iclass 25, count 0 2006.173.18:46:39.48#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.18:46:39.48#ibcon#[25=USB\r\n] 2006.173.18:46:39.48#ibcon#*before write, iclass 25, count 0 2006.173.18:46:39.48#ibcon#enter sib2, iclass 25, count 0 2006.173.18:46:39.48#ibcon#flushed, iclass 25, count 0 2006.173.18:46:39.48#ibcon#about to write, iclass 25, count 0 2006.173.18:46:39.48#ibcon#wrote, iclass 25, count 0 2006.173.18:46:39.48#ibcon#about to read 3, iclass 25, count 0 2006.173.18:46:39.51#ibcon#read 3, iclass 25, count 0 2006.173.18:46:39.51#ibcon#about to read 4, iclass 25, count 0 2006.173.18:46:39.51#ibcon#read 4, iclass 25, count 0 2006.173.18:46:39.51#ibcon#about to read 5, iclass 25, count 0 2006.173.18:46:39.51#ibcon#read 5, iclass 25, count 0 2006.173.18:46:39.51#ibcon#about to read 6, iclass 25, count 0 2006.173.18:46:39.51#ibcon#read 6, iclass 25, count 0 2006.173.18:46:39.51#ibcon#end of sib2, iclass 25, count 0 2006.173.18:46:39.51#ibcon#*after write, iclass 25, count 0 2006.173.18:46:39.51#ibcon#*before return 0, iclass 25, count 0 2006.173.18:46:39.51#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.18:46:39.51#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.18:46:39.51#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.18:46:39.51#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.18:46:39.51$vck44/valo=2,534.99 2006.173.18:46:39.51#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.18:46:39.51#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.18:46:39.51#ibcon#ireg 17 cls_cnt 0 2006.173.18:46:39.51#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.18:46:39.51#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.18:46:39.51#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.18:46:39.51#ibcon#enter wrdev, iclass 27, count 0 2006.173.18:46:39.51#ibcon#first serial, iclass 27, count 0 2006.173.18:46:39.51#ibcon#enter sib2, iclass 27, count 0 2006.173.18:46:39.51#ibcon#flushed, iclass 27, count 0 2006.173.18:46:39.51#ibcon#about to write, iclass 27, count 0 2006.173.18:46:39.51#ibcon#wrote, iclass 27, count 0 2006.173.18:46:39.51#ibcon#about to read 3, iclass 27, count 0 2006.173.18:46:39.53#ibcon#read 3, iclass 27, count 0 2006.173.18:46:39.53#ibcon#about to read 4, iclass 27, count 0 2006.173.18:46:39.53#ibcon#read 4, iclass 27, count 0 2006.173.18:46:39.53#ibcon#about to read 5, iclass 27, count 0 2006.173.18:46:39.53#ibcon#read 5, iclass 27, count 0 2006.173.18:46:39.53#ibcon#about to read 6, iclass 27, count 0 2006.173.18:46:39.53#ibcon#read 6, iclass 27, count 0 2006.173.18:46:39.53#ibcon#end of sib2, iclass 27, count 0 2006.173.18:46:39.53#ibcon#*mode == 0, iclass 27, count 0 2006.173.18:46:39.53#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.18:46:39.53#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.18:46:39.53#ibcon#*before write, iclass 27, count 0 2006.173.18:46:39.53#ibcon#enter sib2, iclass 27, count 0 2006.173.18:46:39.53#ibcon#flushed, iclass 27, count 0 2006.173.18:46:39.53#ibcon#about to write, iclass 27, count 0 2006.173.18:46:39.53#ibcon#wrote, iclass 27, count 0 2006.173.18:46:39.53#ibcon#about to read 3, iclass 27, count 0 2006.173.18:46:39.57#ibcon#read 3, iclass 27, count 0 2006.173.18:46:39.57#ibcon#about to read 4, iclass 27, count 0 2006.173.18:46:39.57#ibcon#read 4, iclass 27, count 0 2006.173.18:46:39.57#ibcon#about to read 5, iclass 27, count 0 2006.173.18:46:39.57#ibcon#read 5, iclass 27, count 0 2006.173.18:46:39.57#ibcon#about to read 6, iclass 27, count 0 2006.173.18:46:39.57#ibcon#read 6, iclass 27, count 0 2006.173.18:46:39.57#ibcon#end of sib2, iclass 27, count 0 2006.173.18:46:39.57#ibcon#*after write, iclass 27, count 0 2006.173.18:46:39.57#ibcon#*before return 0, iclass 27, count 0 2006.173.18:46:39.57#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.18:46:39.57#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.18:46:39.57#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.18:46:39.57#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.18:46:39.57$vck44/va=2,6 2006.173.18:46:39.57#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.18:46:39.57#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.18:46:39.57#ibcon#ireg 11 cls_cnt 2 2006.173.18:46:39.57#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.18:46:39.63#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.18:46:39.63#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.18:46:39.63#ibcon#enter wrdev, iclass 29, count 2 2006.173.18:46:39.63#ibcon#first serial, iclass 29, count 2 2006.173.18:46:39.63#ibcon#enter sib2, iclass 29, count 2 2006.173.18:46:39.63#ibcon#flushed, iclass 29, count 2 2006.173.18:46:39.63#ibcon#about to write, iclass 29, count 2 2006.173.18:46:39.63#ibcon#wrote, iclass 29, count 2 2006.173.18:46:39.63#ibcon#about to read 3, iclass 29, count 2 2006.173.18:46:39.65#ibcon#read 3, iclass 29, count 2 2006.173.18:46:39.65#ibcon#about to read 4, iclass 29, count 2 2006.173.18:46:39.65#ibcon#read 4, iclass 29, count 2 2006.173.18:46:39.65#ibcon#about to read 5, iclass 29, count 2 2006.173.18:46:39.65#ibcon#read 5, iclass 29, count 2 2006.173.18:46:39.65#ibcon#about to read 6, iclass 29, count 2 2006.173.18:46:39.65#ibcon#read 6, iclass 29, count 2 2006.173.18:46:39.65#ibcon#end of sib2, iclass 29, count 2 2006.173.18:46:39.65#ibcon#*mode == 0, iclass 29, count 2 2006.173.18:46:39.65#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.18:46:39.65#ibcon#[25=AT02-06\r\n] 2006.173.18:46:39.65#ibcon#*before write, iclass 29, count 2 2006.173.18:46:39.65#ibcon#enter sib2, iclass 29, count 2 2006.173.18:46:39.65#ibcon#flushed, iclass 29, count 2 2006.173.18:46:39.65#ibcon#about to write, iclass 29, count 2 2006.173.18:46:39.65#ibcon#wrote, iclass 29, count 2 2006.173.18:46:39.65#ibcon#about to read 3, iclass 29, count 2 2006.173.18:46:39.68#ibcon#read 3, iclass 29, count 2 2006.173.18:46:39.68#ibcon#about to read 4, iclass 29, count 2 2006.173.18:46:39.68#ibcon#read 4, iclass 29, count 2 2006.173.18:46:39.68#ibcon#about to read 5, iclass 29, count 2 2006.173.18:46:39.68#ibcon#read 5, iclass 29, count 2 2006.173.18:46:39.68#ibcon#about to read 6, iclass 29, count 2 2006.173.18:46:39.68#ibcon#read 6, iclass 29, count 2 2006.173.18:46:39.68#ibcon#end of sib2, iclass 29, count 2 2006.173.18:46:39.68#ibcon#*after write, iclass 29, count 2 2006.173.18:46:39.68#ibcon#*before return 0, iclass 29, count 2 2006.173.18:46:39.68#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.18:46:39.68#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.18:46:39.68#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.18:46:39.68#ibcon#ireg 7 cls_cnt 0 2006.173.18:46:39.68#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.18:46:39.80#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.18:46:39.80#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.18:46:39.80#ibcon#enter wrdev, iclass 29, count 0 2006.173.18:46:39.80#ibcon#first serial, iclass 29, count 0 2006.173.18:46:39.80#ibcon#enter sib2, iclass 29, count 0 2006.173.18:46:39.80#ibcon#flushed, iclass 29, count 0 2006.173.18:46:39.80#ibcon#about to write, iclass 29, count 0 2006.173.18:46:39.80#ibcon#wrote, iclass 29, count 0 2006.173.18:46:39.80#ibcon#about to read 3, iclass 29, count 0 2006.173.18:46:39.82#ibcon#read 3, iclass 29, count 0 2006.173.18:46:39.82#ibcon#about to read 4, iclass 29, count 0 2006.173.18:46:39.82#ibcon#read 4, iclass 29, count 0 2006.173.18:46:39.82#ibcon#about to read 5, iclass 29, count 0 2006.173.18:46:39.82#ibcon#read 5, iclass 29, count 0 2006.173.18:46:39.82#ibcon#about to read 6, iclass 29, count 0 2006.173.18:46:39.82#ibcon#read 6, iclass 29, count 0 2006.173.18:46:39.82#ibcon#end of sib2, iclass 29, count 0 2006.173.18:46:39.82#ibcon#*mode == 0, iclass 29, count 0 2006.173.18:46:39.82#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.18:46:39.82#ibcon#[25=USB\r\n] 2006.173.18:46:39.82#ibcon#*before write, iclass 29, count 0 2006.173.18:46:39.82#ibcon#enter sib2, iclass 29, count 0 2006.173.18:46:39.82#ibcon#flushed, iclass 29, count 0 2006.173.18:46:39.82#ibcon#about to write, iclass 29, count 0 2006.173.18:46:39.82#ibcon#wrote, iclass 29, count 0 2006.173.18:46:39.82#ibcon#about to read 3, iclass 29, count 0 2006.173.18:46:39.85#ibcon#read 3, iclass 29, count 0 2006.173.18:46:39.85#ibcon#about to read 4, iclass 29, count 0 2006.173.18:46:39.85#ibcon#read 4, iclass 29, count 0 2006.173.18:46:39.85#ibcon#about to read 5, iclass 29, count 0 2006.173.18:46:39.85#ibcon#read 5, iclass 29, count 0 2006.173.18:46:39.85#ibcon#about to read 6, iclass 29, count 0 2006.173.18:46:39.85#ibcon#read 6, iclass 29, count 0 2006.173.18:46:39.85#ibcon#end of sib2, iclass 29, count 0 2006.173.18:46:39.85#ibcon#*after write, iclass 29, count 0 2006.173.18:46:39.85#ibcon#*before return 0, iclass 29, count 0 2006.173.18:46:39.85#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.18:46:39.85#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.18:46:39.85#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.18:46:39.85#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.18:46:39.85$vck44/valo=3,564.99 2006.173.18:46:39.85#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.18:46:39.85#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.18:46:39.85#ibcon#ireg 17 cls_cnt 0 2006.173.18:46:39.85#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.18:46:39.85#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.18:46:39.85#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.18:46:39.85#ibcon#enter wrdev, iclass 31, count 0 2006.173.18:46:39.85#ibcon#first serial, iclass 31, count 0 2006.173.18:46:39.85#ibcon#enter sib2, iclass 31, count 0 2006.173.18:46:39.85#ibcon#flushed, iclass 31, count 0 2006.173.18:46:39.85#ibcon#about to write, iclass 31, count 0 2006.173.18:46:39.85#ibcon#wrote, iclass 31, count 0 2006.173.18:46:39.85#ibcon#about to read 3, iclass 31, count 0 2006.173.18:46:39.87#ibcon#read 3, iclass 31, count 0 2006.173.18:46:39.87#ibcon#about to read 4, iclass 31, count 0 2006.173.18:46:39.87#ibcon#read 4, iclass 31, count 0 2006.173.18:46:39.87#ibcon#about to read 5, iclass 31, count 0 2006.173.18:46:39.87#ibcon#read 5, iclass 31, count 0 2006.173.18:46:39.87#ibcon#about to read 6, iclass 31, count 0 2006.173.18:46:39.87#ibcon#read 6, iclass 31, count 0 2006.173.18:46:39.87#ibcon#end of sib2, iclass 31, count 0 2006.173.18:46:39.87#ibcon#*mode == 0, iclass 31, count 0 2006.173.18:46:39.87#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.18:46:39.87#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.18:46:39.87#ibcon#*before write, iclass 31, count 0 2006.173.18:46:39.87#ibcon#enter sib2, iclass 31, count 0 2006.173.18:46:39.87#ibcon#flushed, iclass 31, count 0 2006.173.18:46:39.87#ibcon#about to write, iclass 31, count 0 2006.173.18:46:39.87#ibcon#wrote, iclass 31, count 0 2006.173.18:46:39.87#ibcon#about to read 3, iclass 31, count 0 2006.173.18:46:39.91#ibcon#read 3, iclass 31, count 0 2006.173.18:46:39.91#ibcon#about to read 4, iclass 31, count 0 2006.173.18:46:39.91#ibcon#read 4, iclass 31, count 0 2006.173.18:46:39.91#ibcon#about to read 5, iclass 31, count 0 2006.173.18:46:39.91#ibcon#read 5, iclass 31, count 0 2006.173.18:46:39.91#ibcon#about to read 6, iclass 31, count 0 2006.173.18:46:39.91#ibcon#read 6, iclass 31, count 0 2006.173.18:46:39.91#ibcon#end of sib2, iclass 31, count 0 2006.173.18:46:39.91#ibcon#*after write, iclass 31, count 0 2006.173.18:46:39.91#ibcon#*before return 0, iclass 31, count 0 2006.173.18:46:39.91#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.18:46:39.91#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.18:46:39.91#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.18:46:39.91#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.18:46:39.91$vck44/va=3,5 2006.173.18:46:39.91#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.173.18:46:39.91#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.173.18:46:39.91#ibcon#ireg 11 cls_cnt 2 2006.173.18:46:39.91#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.18:46:39.97#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.18:46:39.97#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.18:46:39.97#ibcon#enter wrdev, iclass 33, count 2 2006.173.18:46:39.97#ibcon#first serial, iclass 33, count 2 2006.173.18:46:39.97#ibcon#enter sib2, iclass 33, count 2 2006.173.18:46:39.97#ibcon#flushed, iclass 33, count 2 2006.173.18:46:39.97#ibcon#about to write, iclass 33, count 2 2006.173.18:46:39.97#ibcon#wrote, iclass 33, count 2 2006.173.18:46:39.97#ibcon#about to read 3, iclass 33, count 2 2006.173.18:46:39.99#ibcon#read 3, iclass 33, count 2 2006.173.18:46:39.99#ibcon#about to read 4, iclass 33, count 2 2006.173.18:46:39.99#ibcon#read 4, iclass 33, count 2 2006.173.18:46:39.99#ibcon#about to read 5, iclass 33, count 2 2006.173.18:46:39.99#ibcon#read 5, iclass 33, count 2 2006.173.18:46:39.99#ibcon#about to read 6, iclass 33, count 2 2006.173.18:46:39.99#ibcon#read 6, iclass 33, count 2 2006.173.18:46:39.99#ibcon#end of sib2, iclass 33, count 2 2006.173.18:46:39.99#ibcon#*mode == 0, iclass 33, count 2 2006.173.18:46:39.99#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.173.18:46:39.99#ibcon#[25=AT03-05\r\n] 2006.173.18:46:39.99#ibcon#*before write, iclass 33, count 2 2006.173.18:46:39.99#ibcon#enter sib2, iclass 33, count 2 2006.173.18:46:39.99#ibcon#flushed, iclass 33, count 2 2006.173.18:46:39.99#ibcon#about to write, iclass 33, count 2 2006.173.18:46:39.99#ibcon#wrote, iclass 33, count 2 2006.173.18:46:39.99#ibcon#about to read 3, iclass 33, count 2 2006.173.18:46:40.02#ibcon#read 3, iclass 33, count 2 2006.173.18:46:40.02#ibcon#about to read 4, iclass 33, count 2 2006.173.18:46:40.02#ibcon#read 4, iclass 33, count 2 2006.173.18:46:40.02#ibcon#about to read 5, iclass 33, count 2 2006.173.18:46:40.02#ibcon#read 5, iclass 33, count 2 2006.173.18:46:40.02#ibcon#about to read 6, iclass 33, count 2 2006.173.18:46:40.02#ibcon#read 6, iclass 33, count 2 2006.173.18:46:40.02#ibcon#end of sib2, iclass 33, count 2 2006.173.18:46:40.02#ibcon#*after write, iclass 33, count 2 2006.173.18:46:40.02#ibcon#*before return 0, iclass 33, count 2 2006.173.18:46:40.02#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.18:46:40.02#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.173.18:46:40.02#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.173.18:46:40.02#ibcon#ireg 7 cls_cnt 0 2006.173.18:46:40.02#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.18:46:40.14#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.18:46:40.14#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.18:46:40.14#ibcon#enter wrdev, iclass 33, count 0 2006.173.18:46:40.14#ibcon#first serial, iclass 33, count 0 2006.173.18:46:40.14#ibcon#enter sib2, iclass 33, count 0 2006.173.18:46:40.14#ibcon#flushed, iclass 33, count 0 2006.173.18:46:40.14#ibcon#about to write, iclass 33, count 0 2006.173.18:46:40.14#ibcon#wrote, iclass 33, count 0 2006.173.18:46:40.14#ibcon#about to read 3, iclass 33, count 0 2006.173.18:46:40.16#ibcon#read 3, iclass 33, count 0 2006.173.18:46:40.16#ibcon#about to read 4, iclass 33, count 0 2006.173.18:46:40.16#ibcon#read 4, iclass 33, count 0 2006.173.18:46:40.16#ibcon#about to read 5, iclass 33, count 0 2006.173.18:46:40.16#ibcon#read 5, iclass 33, count 0 2006.173.18:46:40.16#ibcon#about to read 6, iclass 33, count 0 2006.173.18:46:40.16#ibcon#read 6, iclass 33, count 0 2006.173.18:46:40.16#ibcon#end of sib2, iclass 33, count 0 2006.173.18:46:40.16#ibcon#*mode == 0, iclass 33, count 0 2006.173.18:46:40.16#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.18:46:40.16#ibcon#[25=USB\r\n] 2006.173.18:46:40.16#ibcon#*before write, iclass 33, count 0 2006.173.18:46:40.16#ibcon#enter sib2, iclass 33, count 0 2006.173.18:46:40.16#ibcon#flushed, iclass 33, count 0 2006.173.18:46:40.16#ibcon#about to write, iclass 33, count 0 2006.173.18:46:40.16#ibcon#wrote, iclass 33, count 0 2006.173.18:46:40.16#ibcon#about to read 3, iclass 33, count 0 2006.173.18:46:40.19#ibcon#read 3, iclass 33, count 0 2006.173.18:46:40.19#ibcon#about to read 4, iclass 33, count 0 2006.173.18:46:40.19#ibcon#read 4, iclass 33, count 0 2006.173.18:46:40.19#ibcon#about to read 5, iclass 33, count 0 2006.173.18:46:40.19#ibcon#read 5, iclass 33, count 0 2006.173.18:46:40.19#ibcon#about to read 6, iclass 33, count 0 2006.173.18:46:40.19#ibcon#read 6, iclass 33, count 0 2006.173.18:46:40.19#ibcon#end of sib2, iclass 33, count 0 2006.173.18:46:40.19#ibcon#*after write, iclass 33, count 0 2006.173.18:46:40.19#ibcon#*before return 0, iclass 33, count 0 2006.173.18:46:40.19#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.18:46:40.19#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.173.18:46:40.19#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.18:46:40.19#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.18:46:40.19$vck44/valo=4,624.99 2006.173.18:46:40.19#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.18:46:40.19#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.18:46:40.19#ibcon#ireg 17 cls_cnt 0 2006.173.18:46:40.19#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.18:46:40.19#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.18:46:40.19#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.18:46:40.19#ibcon#enter wrdev, iclass 35, count 0 2006.173.18:46:40.19#ibcon#first serial, iclass 35, count 0 2006.173.18:46:40.19#ibcon#enter sib2, iclass 35, count 0 2006.173.18:46:40.19#ibcon#flushed, iclass 35, count 0 2006.173.18:46:40.19#ibcon#about to write, iclass 35, count 0 2006.173.18:46:40.19#ibcon#wrote, iclass 35, count 0 2006.173.18:46:40.19#ibcon#about to read 3, iclass 35, count 0 2006.173.18:46:40.21#ibcon#read 3, iclass 35, count 0 2006.173.18:46:40.21#ibcon#about to read 4, iclass 35, count 0 2006.173.18:46:40.21#ibcon#read 4, iclass 35, count 0 2006.173.18:46:40.21#ibcon#about to read 5, iclass 35, count 0 2006.173.18:46:40.21#ibcon#read 5, iclass 35, count 0 2006.173.18:46:40.21#ibcon#about to read 6, iclass 35, count 0 2006.173.18:46:40.21#ibcon#read 6, iclass 35, count 0 2006.173.18:46:40.21#ibcon#end of sib2, iclass 35, count 0 2006.173.18:46:40.21#ibcon#*mode == 0, iclass 35, count 0 2006.173.18:46:40.21#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.18:46:40.21#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.18:46:40.21#ibcon#*before write, iclass 35, count 0 2006.173.18:46:40.21#ibcon#enter sib2, iclass 35, count 0 2006.173.18:46:40.21#ibcon#flushed, iclass 35, count 0 2006.173.18:46:40.21#ibcon#about to write, iclass 35, count 0 2006.173.18:46:40.21#ibcon#wrote, iclass 35, count 0 2006.173.18:46:40.21#ibcon#about to read 3, iclass 35, count 0 2006.173.18:46:40.25#ibcon#read 3, iclass 35, count 0 2006.173.18:46:40.25#ibcon#about to read 4, iclass 35, count 0 2006.173.18:46:40.25#ibcon#read 4, iclass 35, count 0 2006.173.18:46:40.25#ibcon#about to read 5, iclass 35, count 0 2006.173.18:46:40.25#ibcon#read 5, iclass 35, count 0 2006.173.18:46:40.25#ibcon#about to read 6, iclass 35, count 0 2006.173.18:46:40.25#ibcon#read 6, iclass 35, count 0 2006.173.18:46:40.25#ibcon#end of sib2, iclass 35, count 0 2006.173.18:46:40.25#ibcon#*after write, iclass 35, count 0 2006.173.18:46:40.25#ibcon#*before return 0, iclass 35, count 0 2006.173.18:46:40.25#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.18:46:40.25#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.18:46:40.25#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.18:46:40.25#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.18:46:40.25$vck44/va=4,6 2006.173.18:46:40.25#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.173.18:46:40.25#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.173.18:46:40.25#ibcon#ireg 11 cls_cnt 2 2006.173.18:46:40.25#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.18:46:40.31#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.18:46:40.31#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.18:46:40.31#ibcon#enter wrdev, iclass 37, count 2 2006.173.18:46:40.31#ibcon#first serial, iclass 37, count 2 2006.173.18:46:40.31#ibcon#enter sib2, iclass 37, count 2 2006.173.18:46:40.31#ibcon#flushed, iclass 37, count 2 2006.173.18:46:40.31#ibcon#about to write, iclass 37, count 2 2006.173.18:46:40.31#ibcon#wrote, iclass 37, count 2 2006.173.18:46:40.31#ibcon#about to read 3, iclass 37, count 2 2006.173.18:46:40.33#ibcon#read 3, iclass 37, count 2 2006.173.18:46:40.33#ibcon#about to read 4, iclass 37, count 2 2006.173.18:46:40.33#ibcon#read 4, iclass 37, count 2 2006.173.18:46:40.33#ibcon#about to read 5, iclass 37, count 2 2006.173.18:46:40.33#ibcon#read 5, iclass 37, count 2 2006.173.18:46:40.33#ibcon#about to read 6, iclass 37, count 2 2006.173.18:46:40.33#ibcon#read 6, iclass 37, count 2 2006.173.18:46:40.33#ibcon#end of sib2, iclass 37, count 2 2006.173.18:46:40.33#ibcon#*mode == 0, iclass 37, count 2 2006.173.18:46:40.33#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.173.18:46:40.33#ibcon#[25=AT04-06\r\n] 2006.173.18:46:40.33#ibcon#*before write, iclass 37, count 2 2006.173.18:46:40.33#ibcon#enter sib2, iclass 37, count 2 2006.173.18:46:40.33#ibcon#flushed, iclass 37, count 2 2006.173.18:46:40.33#ibcon#about to write, iclass 37, count 2 2006.173.18:46:40.33#ibcon#wrote, iclass 37, count 2 2006.173.18:46:40.33#ibcon#about to read 3, iclass 37, count 2 2006.173.18:46:40.36#ibcon#read 3, iclass 37, count 2 2006.173.18:46:40.36#ibcon#about to read 4, iclass 37, count 2 2006.173.18:46:40.36#ibcon#read 4, iclass 37, count 2 2006.173.18:46:40.36#ibcon#about to read 5, iclass 37, count 2 2006.173.18:46:40.36#ibcon#read 5, iclass 37, count 2 2006.173.18:46:40.36#ibcon#about to read 6, iclass 37, count 2 2006.173.18:46:40.36#ibcon#read 6, iclass 37, count 2 2006.173.18:46:40.36#ibcon#end of sib2, iclass 37, count 2 2006.173.18:46:40.36#ibcon#*after write, iclass 37, count 2 2006.173.18:46:40.36#ibcon#*before return 0, iclass 37, count 2 2006.173.18:46:40.36#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.18:46:40.36#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.173.18:46:40.36#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.173.18:46:40.36#ibcon#ireg 7 cls_cnt 0 2006.173.18:46:40.36#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.18:46:40.48#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.18:46:40.48#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.18:46:40.48#ibcon#enter wrdev, iclass 37, count 0 2006.173.18:46:40.48#ibcon#first serial, iclass 37, count 0 2006.173.18:46:40.48#ibcon#enter sib2, iclass 37, count 0 2006.173.18:46:40.48#ibcon#flushed, iclass 37, count 0 2006.173.18:46:40.48#ibcon#about to write, iclass 37, count 0 2006.173.18:46:40.48#ibcon#wrote, iclass 37, count 0 2006.173.18:46:40.48#ibcon#about to read 3, iclass 37, count 0 2006.173.18:46:40.50#ibcon#read 3, iclass 37, count 0 2006.173.18:46:40.50#ibcon#about to read 4, iclass 37, count 0 2006.173.18:46:40.50#ibcon#read 4, iclass 37, count 0 2006.173.18:46:40.50#ibcon#about to read 5, iclass 37, count 0 2006.173.18:46:40.50#ibcon#read 5, iclass 37, count 0 2006.173.18:46:40.50#ibcon#about to read 6, iclass 37, count 0 2006.173.18:46:40.50#ibcon#read 6, iclass 37, count 0 2006.173.18:46:40.50#ibcon#end of sib2, iclass 37, count 0 2006.173.18:46:40.50#ibcon#*mode == 0, iclass 37, count 0 2006.173.18:46:40.50#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.18:46:40.50#ibcon#[25=USB\r\n] 2006.173.18:46:40.50#ibcon#*before write, iclass 37, count 0 2006.173.18:46:40.50#ibcon#enter sib2, iclass 37, count 0 2006.173.18:46:40.50#ibcon#flushed, iclass 37, count 0 2006.173.18:46:40.50#ibcon#about to write, iclass 37, count 0 2006.173.18:46:40.50#ibcon#wrote, iclass 37, count 0 2006.173.18:46:40.50#ibcon#about to read 3, iclass 37, count 0 2006.173.18:46:40.53#ibcon#read 3, iclass 37, count 0 2006.173.18:46:40.53#ibcon#about to read 4, iclass 37, count 0 2006.173.18:46:40.53#ibcon#read 4, iclass 37, count 0 2006.173.18:46:40.53#ibcon#about to read 5, iclass 37, count 0 2006.173.18:46:40.53#ibcon#read 5, iclass 37, count 0 2006.173.18:46:40.53#ibcon#about to read 6, iclass 37, count 0 2006.173.18:46:40.53#ibcon#read 6, iclass 37, count 0 2006.173.18:46:40.53#ibcon#end of sib2, iclass 37, count 0 2006.173.18:46:40.53#ibcon#*after write, iclass 37, count 0 2006.173.18:46:40.53#ibcon#*before return 0, iclass 37, count 0 2006.173.18:46:40.53#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.18:46:40.53#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.173.18:46:40.53#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.18:46:40.53#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.18:46:40.53$vck44/valo=5,734.99 2006.173.18:46:40.53#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.18:46:40.53#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.18:46:40.53#ibcon#ireg 17 cls_cnt 0 2006.173.18:46:40.53#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.18:46:40.53#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.18:46:40.53#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.18:46:40.53#ibcon#enter wrdev, iclass 39, count 0 2006.173.18:46:40.53#ibcon#first serial, iclass 39, count 0 2006.173.18:46:40.53#ibcon#enter sib2, iclass 39, count 0 2006.173.18:46:40.53#ibcon#flushed, iclass 39, count 0 2006.173.18:46:40.53#ibcon#about to write, iclass 39, count 0 2006.173.18:46:40.53#ibcon#wrote, iclass 39, count 0 2006.173.18:46:40.53#ibcon#about to read 3, iclass 39, count 0 2006.173.18:46:40.55#ibcon#read 3, iclass 39, count 0 2006.173.18:46:40.55#ibcon#about to read 4, iclass 39, count 0 2006.173.18:46:40.55#ibcon#read 4, iclass 39, count 0 2006.173.18:46:40.55#ibcon#about to read 5, iclass 39, count 0 2006.173.18:46:40.55#ibcon#read 5, iclass 39, count 0 2006.173.18:46:40.55#ibcon#about to read 6, iclass 39, count 0 2006.173.18:46:40.55#ibcon#read 6, iclass 39, count 0 2006.173.18:46:40.55#ibcon#end of sib2, iclass 39, count 0 2006.173.18:46:40.55#ibcon#*mode == 0, iclass 39, count 0 2006.173.18:46:40.55#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.18:46:40.55#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.18:46:40.55#ibcon#*before write, iclass 39, count 0 2006.173.18:46:40.55#ibcon#enter sib2, iclass 39, count 0 2006.173.18:46:40.55#ibcon#flushed, iclass 39, count 0 2006.173.18:46:40.55#ibcon#about to write, iclass 39, count 0 2006.173.18:46:40.55#ibcon#wrote, iclass 39, count 0 2006.173.18:46:40.55#ibcon#about to read 3, iclass 39, count 0 2006.173.18:46:40.59#ibcon#read 3, iclass 39, count 0 2006.173.18:46:40.59#ibcon#about to read 4, iclass 39, count 0 2006.173.18:46:40.59#ibcon#read 4, iclass 39, count 0 2006.173.18:46:40.59#ibcon#about to read 5, iclass 39, count 0 2006.173.18:46:40.59#ibcon#read 5, iclass 39, count 0 2006.173.18:46:40.59#ibcon#about to read 6, iclass 39, count 0 2006.173.18:46:40.59#ibcon#read 6, iclass 39, count 0 2006.173.18:46:40.59#ibcon#end of sib2, iclass 39, count 0 2006.173.18:46:40.59#ibcon#*after write, iclass 39, count 0 2006.173.18:46:40.59#ibcon#*before return 0, iclass 39, count 0 2006.173.18:46:40.59#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.18:46:40.59#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.18:46:40.59#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.18:46:40.59#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.18:46:40.59$vck44/va=5,4 2006.173.18:46:40.59#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.18:46:40.59#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.18:46:40.59#ibcon#ireg 11 cls_cnt 2 2006.173.18:46:40.59#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.18:46:40.65#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.18:46:40.65#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.18:46:40.65#ibcon#enter wrdev, iclass 3, count 2 2006.173.18:46:40.65#ibcon#first serial, iclass 3, count 2 2006.173.18:46:40.65#ibcon#enter sib2, iclass 3, count 2 2006.173.18:46:40.65#ibcon#flushed, iclass 3, count 2 2006.173.18:46:40.65#ibcon#about to write, iclass 3, count 2 2006.173.18:46:40.65#ibcon#wrote, iclass 3, count 2 2006.173.18:46:40.65#ibcon#about to read 3, iclass 3, count 2 2006.173.18:46:40.67#ibcon#read 3, iclass 3, count 2 2006.173.18:46:40.67#ibcon#about to read 4, iclass 3, count 2 2006.173.18:46:40.67#ibcon#read 4, iclass 3, count 2 2006.173.18:46:40.67#ibcon#about to read 5, iclass 3, count 2 2006.173.18:46:40.67#ibcon#read 5, iclass 3, count 2 2006.173.18:46:40.67#ibcon#about to read 6, iclass 3, count 2 2006.173.18:46:40.67#ibcon#read 6, iclass 3, count 2 2006.173.18:46:40.67#ibcon#end of sib2, iclass 3, count 2 2006.173.18:46:40.67#ibcon#*mode == 0, iclass 3, count 2 2006.173.18:46:40.67#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.18:46:40.67#ibcon#[25=AT05-04\r\n] 2006.173.18:46:40.67#ibcon#*before write, iclass 3, count 2 2006.173.18:46:40.67#ibcon#enter sib2, iclass 3, count 2 2006.173.18:46:40.67#ibcon#flushed, iclass 3, count 2 2006.173.18:46:40.67#ibcon#about to write, iclass 3, count 2 2006.173.18:46:40.67#ibcon#wrote, iclass 3, count 2 2006.173.18:46:40.67#ibcon#about to read 3, iclass 3, count 2 2006.173.18:46:40.70#ibcon#read 3, iclass 3, count 2 2006.173.18:46:40.70#ibcon#about to read 4, iclass 3, count 2 2006.173.18:46:40.70#ibcon#read 4, iclass 3, count 2 2006.173.18:46:40.70#ibcon#about to read 5, iclass 3, count 2 2006.173.18:46:40.70#ibcon#read 5, iclass 3, count 2 2006.173.18:46:40.70#ibcon#about to read 6, iclass 3, count 2 2006.173.18:46:40.70#ibcon#read 6, iclass 3, count 2 2006.173.18:46:40.70#ibcon#end of sib2, iclass 3, count 2 2006.173.18:46:40.70#ibcon#*after write, iclass 3, count 2 2006.173.18:46:40.70#ibcon#*before return 0, iclass 3, count 2 2006.173.18:46:40.70#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.18:46:40.70#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.18:46:40.70#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.18:46:40.70#ibcon#ireg 7 cls_cnt 0 2006.173.18:46:40.70#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.18:46:40.82#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.18:46:40.82#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.18:46:40.82#ibcon#enter wrdev, iclass 3, count 0 2006.173.18:46:40.82#ibcon#first serial, iclass 3, count 0 2006.173.18:46:40.82#ibcon#enter sib2, iclass 3, count 0 2006.173.18:46:40.82#ibcon#flushed, iclass 3, count 0 2006.173.18:46:40.82#ibcon#about to write, iclass 3, count 0 2006.173.18:46:40.82#ibcon#wrote, iclass 3, count 0 2006.173.18:46:40.82#ibcon#about to read 3, iclass 3, count 0 2006.173.18:46:40.84#ibcon#read 3, iclass 3, count 0 2006.173.18:46:40.84#ibcon#about to read 4, iclass 3, count 0 2006.173.18:46:40.84#ibcon#read 4, iclass 3, count 0 2006.173.18:46:40.84#ibcon#about to read 5, iclass 3, count 0 2006.173.18:46:40.84#ibcon#read 5, iclass 3, count 0 2006.173.18:46:40.84#ibcon#about to read 6, iclass 3, count 0 2006.173.18:46:40.84#ibcon#read 6, iclass 3, count 0 2006.173.18:46:40.84#ibcon#end of sib2, iclass 3, count 0 2006.173.18:46:40.84#ibcon#*mode == 0, iclass 3, count 0 2006.173.18:46:40.84#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.18:46:40.84#ibcon#[25=USB\r\n] 2006.173.18:46:40.84#ibcon#*before write, iclass 3, count 0 2006.173.18:46:40.84#ibcon#enter sib2, iclass 3, count 0 2006.173.18:46:40.84#ibcon#flushed, iclass 3, count 0 2006.173.18:46:40.84#ibcon#about to write, iclass 3, count 0 2006.173.18:46:40.84#ibcon#wrote, iclass 3, count 0 2006.173.18:46:40.84#ibcon#about to read 3, iclass 3, count 0 2006.173.18:46:40.87#ibcon#read 3, iclass 3, count 0 2006.173.18:46:40.87#ibcon#about to read 4, iclass 3, count 0 2006.173.18:46:40.87#ibcon#read 4, iclass 3, count 0 2006.173.18:46:40.87#ibcon#about to read 5, iclass 3, count 0 2006.173.18:46:40.87#ibcon#read 5, iclass 3, count 0 2006.173.18:46:40.87#ibcon#about to read 6, iclass 3, count 0 2006.173.18:46:40.87#ibcon#read 6, iclass 3, count 0 2006.173.18:46:40.87#ibcon#end of sib2, iclass 3, count 0 2006.173.18:46:40.87#ibcon#*after write, iclass 3, count 0 2006.173.18:46:40.87#ibcon#*before return 0, iclass 3, count 0 2006.173.18:46:40.87#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.18:46:40.87#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.18:46:40.87#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.18:46:40.87#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.18:46:40.87$vck44/valo=6,814.99 2006.173.18:46:40.87#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.18:46:40.87#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.18:46:40.87#ibcon#ireg 17 cls_cnt 0 2006.173.18:46:40.87#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.18:46:40.87#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.18:46:40.87#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.18:46:40.87#ibcon#enter wrdev, iclass 5, count 0 2006.173.18:46:40.87#ibcon#first serial, iclass 5, count 0 2006.173.18:46:40.87#ibcon#enter sib2, iclass 5, count 0 2006.173.18:46:40.87#ibcon#flushed, iclass 5, count 0 2006.173.18:46:40.87#ibcon#about to write, iclass 5, count 0 2006.173.18:46:40.87#ibcon#wrote, iclass 5, count 0 2006.173.18:46:40.87#ibcon#about to read 3, iclass 5, count 0 2006.173.18:46:40.89#ibcon#read 3, iclass 5, count 0 2006.173.18:46:40.89#ibcon#about to read 4, iclass 5, count 0 2006.173.18:46:40.89#ibcon#read 4, iclass 5, count 0 2006.173.18:46:40.89#ibcon#about to read 5, iclass 5, count 0 2006.173.18:46:40.89#ibcon#read 5, iclass 5, count 0 2006.173.18:46:40.89#ibcon#about to read 6, iclass 5, count 0 2006.173.18:46:40.89#ibcon#read 6, iclass 5, count 0 2006.173.18:46:40.89#ibcon#end of sib2, iclass 5, count 0 2006.173.18:46:40.89#ibcon#*mode == 0, iclass 5, count 0 2006.173.18:46:40.89#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.18:46:40.89#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.18:46:40.89#ibcon#*before write, iclass 5, count 0 2006.173.18:46:40.89#ibcon#enter sib2, iclass 5, count 0 2006.173.18:46:40.89#ibcon#flushed, iclass 5, count 0 2006.173.18:46:40.89#ibcon#about to write, iclass 5, count 0 2006.173.18:46:40.89#ibcon#wrote, iclass 5, count 0 2006.173.18:46:40.89#ibcon#about to read 3, iclass 5, count 0 2006.173.18:46:40.93#ibcon#read 3, iclass 5, count 0 2006.173.18:46:40.93#ibcon#about to read 4, iclass 5, count 0 2006.173.18:46:40.93#ibcon#read 4, iclass 5, count 0 2006.173.18:46:40.93#ibcon#about to read 5, iclass 5, count 0 2006.173.18:46:40.93#ibcon#read 5, iclass 5, count 0 2006.173.18:46:40.93#ibcon#about to read 6, iclass 5, count 0 2006.173.18:46:40.93#ibcon#read 6, iclass 5, count 0 2006.173.18:46:40.93#ibcon#end of sib2, iclass 5, count 0 2006.173.18:46:40.93#ibcon#*after write, iclass 5, count 0 2006.173.18:46:40.93#ibcon#*before return 0, iclass 5, count 0 2006.173.18:46:40.93#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.18:46:40.93#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.18:46:40.93#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.18:46:40.93#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.18:46:40.93$vck44/va=6,3 2006.173.18:46:40.93#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.173.18:46:40.93#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.173.18:46:40.93#ibcon#ireg 11 cls_cnt 2 2006.173.18:46:40.93#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.18:46:40.99#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.18:46:40.99#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.18:46:40.99#ibcon#enter wrdev, iclass 7, count 2 2006.173.18:46:40.99#ibcon#first serial, iclass 7, count 2 2006.173.18:46:40.99#ibcon#enter sib2, iclass 7, count 2 2006.173.18:46:40.99#ibcon#flushed, iclass 7, count 2 2006.173.18:46:40.99#ibcon#about to write, iclass 7, count 2 2006.173.18:46:40.99#ibcon#wrote, iclass 7, count 2 2006.173.18:46:40.99#ibcon#about to read 3, iclass 7, count 2 2006.173.18:46:41.01#ibcon#read 3, iclass 7, count 2 2006.173.18:46:41.01#ibcon#about to read 4, iclass 7, count 2 2006.173.18:46:41.01#ibcon#read 4, iclass 7, count 2 2006.173.18:46:41.01#ibcon#about to read 5, iclass 7, count 2 2006.173.18:46:41.01#ibcon#read 5, iclass 7, count 2 2006.173.18:46:41.01#ibcon#about to read 6, iclass 7, count 2 2006.173.18:46:41.01#ibcon#read 6, iclass 7, count 2 2006.173.18:46:41.01#ibcon#end of sib2, iclass 7, count 2 2006.173.18:46:41.01#ibcon#*mode == 0, iclass 7, count 2 2006.173.18:46:41.01#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.173.18:46:41.01#ibcon#[25=AT06-03\r\n] 2006.173.18:46:41.01#ibcon#*before write, iclass 7, count 2 2006.173.18:46:41.01#ibcon#enter sib2, iclass 7, count 2 2006.173.18:46:41.01#ibcon#flushed, iclass 7, count 2 2006.173.18:46:41.01#ibcon#about to write, iclass 7, count 2 2006.173.18:46:41.01#ibcon#wrote, iclass 7, count 2 2006.173.18:46:41.01#ibcon#about to read 3, iclass 7, count 2 2006.173.18:46:41.04#ibcon#read 3, iclass 7, count 2 2006.173.18:46:41.04#ibcon#about to read 4, iclass 7, count 2 2006.173.18:46:41.04#ibcon#read 4, iclass 7, count 2 2006.173.18:46:41.04#ibcon#about to read 5, iclass 7, count 2 2006.173.18:46:41.04#ibcon#read 5, iclass 7, count 2 2006.173.18:46:41.04#ibcon#about to read 6, iclass 7, count 2 2006.173.18:46:41.04#ibcon#read 6, iclass 7, count 2 2006.173.18:46:41.04#ibcon#end of sib2, iclass 7, count 2 2006.173.18:46:41.04#ibcon#*after write, iclass 7, count 2 2006.173.18:46:41.04#ibcon#*before return 0, iclass 7, count 2 2006.173.18:46:41.04#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.18:46:41.04#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.173.18:46:41.04#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.173.18:46:41.04#ibcon#ireg 7 cls_cnt 0 2006.173.18:46:41.04#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.18:46:41.16#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.18:46:41.16#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.18:46:41.16#ibcon#enter wrdev, iclass 7, count 0 2006.173.18:46:41.16#ibcon#first serial, iclass 7, count 0 2006.173.18:46:41.16#ibcon#enter sib2, iclass 7, count 0 2006.173.18:46:41.16#ibcon#flushed, iclass 7, count 0 2006.173.18:46:41.16#ibcon#about to write, iclass 7, count 0 2006.173.18:46:41.16#ibcon#wrote, iclass 7, count 0 2006.173.18:46:41.16#ibcon#about to read 3, iclass 7, count 0 2006.173.18:46:41.18#ibcon#read 3, iclass 7, count 0 2006.173.18:46:41.18#ibcon#about to read 4, iclass 7, count 0 2006.173.18:46:41.18#ibcon#read 4, iclass 7, count 0 2006.173.18:46:41.18#ibcon#about to read 5, iclass 7, count 0 2006.173.18:46:41.18#ibcon#read 5, iclass 7, count 0 2006.173.18:46:41.18#ibcon#about to read 6, iclass 7, count 0 2006.173.18:46:41.18#ibcon#read 6, iclass 7, count 0 2006.173.18:46:41.18#ibcon#end of sib2, iclass 7, count 0 2006.173.18:46:41.18#ibcon#*mode == 0, iclass 7, count 0 2006.173.18:46:41.18#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.18:46:41.18#ibcon#[25=USB\r\n] 2006.173.18:46:41.18#ibcon#*before write, iclass 7, count 0 2006.173.18:46:41.18#ibcon#enter sib2, iclass 7, count 0 2006.173.18:46:41.18#ibcon#flushed, iclass 7, count 0 2006.173.18:46:41.18#ibcon#about to write, iclass 7, count 0 2006.173.18:46:41.18#ibcon#wrote, iclass 7, count 0 2006.173.18:46:41.18#ibcon#about to read 3, iclass 7, count 0 2006.173.18:46:41.21#ibcon#read 3, iclass 7, count 0 2006.173.18:46:41.21#ibcon#about to read 4, iclass 7, count 0 2006.173.18:46:41.21#ibcon#read 4, iclass 7, count 0 2006.173.18:46:41.21#ibcon#about to read 5, iclass 7, count 0 2006.173.18:46:41.21#ibcon#read 5, iclass 7, count 0 2006.173.18:46:41.21#ibcon#about to read 6, iclass 7, count 0 2006.173.18:46:41.21#ibcon#read 6, iclass 7, count 0 2006.173.18:46:41.21#ibcon#end of sib2, iclass 7, count 0 2006.173.18:46:41.21#ibcon#*after write, iclass 7, count 0 2006.173.18:46:41.21#ibcon#*before return 0, iclass 7, count 0 2006.173.18:46:41.21#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.18:46:41.21#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.173.18:46:41.21#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.18:46:41.21#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.18:46:41.21$vck44/valo=7,864.99 2006.173.18:46:41.21#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.18:46:41.21#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.18:46:41.21#ibcon#ireg 17 cls_cnt 0 2006.173.18:46:41.21#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.18:46:41.21#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.18:46:41.21#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.18:46:41.21#ibcon#enter wrdev, iclass 11, count 0 2006.173.18:46:41.21#ibcon#first serial, iclass 11, count 0 2006.173.18:46:41.21#ibcon#enter sib2, iclass 11, count 0 2006.173.18:46:41.21#ibcon#flushed, iclass 11, count 0 2006.173.18:46:41.21#ibcon#about to write, iclass 11, count 0 2006.173.18:46:41.21#ibcon#wrote, iclass 11, count 0 2006.173.18:46:41.21#ibcon#about to read 3, iclass 11, count 0 2006.173.18:46:41.23#ibcon#read 3, iclass 11, count 0 2006.173.18:46:41.23#ibcon#about to read 4, iclass 11, count 0 2006.173.18:46:41.23#ibcon#read 4, iclass 11, count 0 2006.173.18:46:41.23#ibcon#about to read 5, iclass 11, count 0 2006.173.18:46:41.23#ibcon#read 5, iclass 11, count 0 2006.173.18:46:41.23#ibcon#about to read 6, iclass 11, count 0 2006.173.18:46:41.23#ibcon#read 6, iclass 11, count 0 2006.173.18:46:41.23#ibcon#end of sib2, iclass 11, count 0 2006.173.18:46:41.23#ibcon#*mode == 0, iclass 11, count 0 2006.173.18:46:41.23#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.18:46:41.23#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.18:46:41.23#ibcon#*before write, iclass 11, count 0 2006.173.18:46:41.23#ibcon#enter sib2, iclass 11, count 0 2006.173.18:46:41.23#ibcon#flushed, iclass 11, count 0 2006.173.18:46:41.23#ibcon#about to write, iclass 11, count 0 2006.173.18:46:41.23#ibcon#wrote, iclass 11, count 0 2006.173.18:46:41.23#ibcon#about to read 3, iclass 11, count 0 2006.173.18:46:41.27#ibcon#read 3, iclass 11, count 0 2006.173.18:46:41.27#ibcon#about to read 4, iclass 11, count 0 2006.173.18:46:41.27#ibcon#read 4, iclass 11, count 0 2006.173.18:46:41.27#ibcon#about to read 5, iclass 11, count 0 2006.173.18:46:41.27#ibcon#read 5, iclass 11, count 0 2006.173.18:46:41.27#ibcon#about to read 6, iclass 11, count 0 2006.173.18:46:41.27#ibcon#read 6, iclass 11, count 0 2006.173.18:46:41.27#ibcon#end of sib2, iclass 11, count 0 2006.173.18:46:41.27#ibcon#*after write, iclass 11, count 0 2006.173.18:46:41.27#ibcon#*before return 0, iclass 11, count 0 2006.173.18:46:41.27#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.18:46:41.27#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.18:46:41.27#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.18:46:41.27#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.18:46:41.27$vck44/va=7,4 2006.173.18:46:41.27#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.173.18:46:41.27#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.173.18:46:41.27#ibcon#ireg 11 cls_cnt 2 2006.173.18:46:41.27#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.18:46:41.33#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.18:46:41.33#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.18:46:41.33#ibcon#enter wrdev, iclass 13, count 2 2006.173.18:46:41.33#ibcon#first serial, iclass 13, count 2 2006.173.18:46:41.33#ibcon#enter sib2, iclass 13, count 2 2006.173.18:46:41.33#ibcon#flushed, iclass 13, count 2 2006.173.18:46:41.33#ibcon#about to write, iclass 13, count 2 2006.173.18:46:41.33#ibcon#wrote, iclass 13, count 2 2006.173.18:46:41.33#ibcon#about to read 3, iclass 13, count 2 2006.173.18:46:41.35#ibcon#read 3, iclass 13, count 2 2006.173.18:46:41.35#ibcon#about to read 4, iclass 13, count 2 2006.173.18:46:41.35#ibcon#read 4, iclass 13, count 2 2006.173.18:46:41.35#ibcon#about to read 5, iclass 13, count 2 2006.173.18:46:41.35#ibcon#read 5, iclass 13, count 2 2006.173.18:46:41.35#ibcon#about to read 6, iclass 13, count 2 2006.173.18:46:41.35#ibcon#read 6, iclass 13, count 2 2006.173.18:46:41.35#ibcon#end of sib2, iclass 13, count 2 2006.173.18:46:41.35#ibcon#*mode == 0, iclass 13, count 2 2006.173.18:46:41.35#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.173.18:46:41.35#ibcon#[25=AT07-04\r\n] 2006.173.18:46:41.35#ibcon#*before write, iclass 13, count 2 2006.173.18:46:41.35#ibcon#enter sib2, iclass 13, count 2 2006.173.18:46:41.35#ibcon#flushed, iclass 13, count 2 2006.173.18:46:41.35#ibcon#about to write, iclass 13, count 2 2006.173.18:46:41.35#ibcon#wrote, iclass 13, count 2 2006.173.18:46:41.35#ibcon#about to read 3, iclass 13, count 2 2006.173.18:46:41.38#ibcon#read 3, iclass 13, count 2 2006.173.18:46:41.38#ibcon#about to read 4, iclass 13, count 2 2006.173.18:46:41.38#ibcon#read 4, iclass 13, count 2 2006.173.18:46:41.38#ibcon#about to read 5, iclass 13, count 2 2006.173.18:46:41.38#ibcon#read 5, iclass 13, count 2 2006.173.18:46:41.38#ibcon#about to read 6, iclass 13, count 2 2006.173.18:46:41.38#ibcon#read 6, iclass 13, count 2 2006.173.18:46:41.38#ibcon#end of sib2, iclass 13, count 2 2006.173.18:46:41.38#ibcon#*after write, iclass 13, count 2 2006.173.18:46:41.38#ibcon#*before return 0, iclass 13, count 2 2006.173.18:46:41.38#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.18:46:41.38#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.173.18:46:41.38#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.173.18:46:41.38#ibcon#ireg 7 cls_cnt 0 2006.173.18:46:41.38#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.18:46:41.50#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.18:46:41.50#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.18:46:41.50#ibcon#enter wrdev, iclass 13, count 0 2006.173.18:46:41.50#ibcon#first serial, iclass 13, count 0 2006.173.18:46:41.50#ibcon#enter sib2, iclass 13, count 0 2006.173.18:46:41.50#ibcon#flushed, iclass 13, count 0 2006.173.18:46:41.50#ibcon#about to write, iclass 13, count 0 2006.173.18:46:41.50#ibcon#wrote, iclass 13, count 0 2006.173.18:46:41.50#ibcon#about to read 3, iclass 13, count 0 2006.173.18:46:41.52#ibcon#read 3, iclass 13, count 0 2006.173.18:46:41.52#ibcon#about to read 4, iclass 13, count 0 2006.173.18:46:41.52#ibcon#read 4, iclass 13, count 0 2006.173.18:46:41.52#ibcon#about to read 5, iclass 13, count 0 2006.173.18:46:41.52#ibcon#read 5, iclass 13, count 0 2006.173.18:46:41.52#ibcon#about to read 6, iclass 13, count 0 2006.173.18:46:41.52#ibcon#read 6, iclass 13, count 0 2006.173.18:46:41.52#ibcon#end of sib2, iclass 13, count 0 2006.173.18:46:41.52#ibcon#*mode == 0, iclass 13, count 0 2006.173.18:46:41.52#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.18:46:41.52#ibcon#[25=USB\r\n] 2006.173.18:46:41.52#ibcon#*before write, iclass 13, count 0 2006.173.18:46:41.52#ibcon#enter sib2, iclass 13, count 0 2006.173.18:46:41.52#ibcon#flushed, iclass 13, count 0 2006.173.18:46:41.52#ibcon#about to write, iclass 13, count 0 2006.173.18:46:41.52#ibcon#wrote, iclass 13, count 0 2006.173.18:46:41.52#ibcon#about to read 3, iclass 13, count 0 2006.173.18:46:41.55#ibcon#read 3, iclass 13, count 0 2006.173.18:46:41.55#ibcon#about to read 4, iclass 13, count 0 2006.173.18:46:41.55#ibcon#read 4, iclass 13, count 0 2006.173.18:46:41.55#ibcon#about to read 5, iclass 13, count 0 2006.173.18:46:41.55#ibcon#read 5, iclass 13, count 0 2006.173.18:46:41.55#ibcon#about to read 6, iclass 13, count 0 2006.173.18:46:41.55#ibcon#read 6, iclass 13, count 0 2006.173.18:46:41.55#ibcon#end of sib2, iclass 13, count 0 2006.173.18:46:41.55#ibcon#*after write, iclass 13, count 0 2006.173.18:46:41.55#ibcon#*before return 0, iclass 13, count 0 2006.173.18:46:41.55#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.18:46:41.55#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.173.18:46:41.55#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.18:46:41.55#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.18:46:41.55$vck44/valo=8,884.99 2006.173.18:46:41.55#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.18:46:41.55#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.18:46:41.55#ibcon#ireg 17 cls_cnt 0 2006.173.18:46:41.55#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.18:46:41.55#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.18:46:41.55#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.18:46:41.55#ibcon#enter wrdev, iclass 15, count 0 2006.173.18:46:41.55#ibcon#first serial, iclass 15, count 0 2006.173.18:46:41.55#ibcon#enter sib2, iclass 15, count 0 2006.173.18:46:41.55#ibcon#flushed, iclass 15, count 0 2006.173.18:46:41.55#ibcon#about to write, iclass 15, count 0 2006.173.18:46:41.55#ibcon#wrote, iclass 15, count 0 2006.173.18:46:41.55#ibcon#about to read 3, iclass 15, count 0 2006.173.18:46:41.57#ibcon#read 3, iclass 15, count 0 2006.173.18:46:41.57#ibcon#about to read 4, iclass 15, count 0 2006.173.18:46:41.57#ibcon#read 4, iclass 15, count 0 2006.173.18:46:41.57#ibcon#about to read 5, iclass 15, count 0 2006.173.18:46:41.57#ibcon#read 5, iclass 15, count 0 2006.173.18:46:41.57#ibcon#about to read 6, iclass 15, count 0 2006.173.18:46:41.57#ibcon#read 6, iclass 15, count 0 2006.173.18:46:41.57#ibcon#end of sib2, iclass 15, count 0 2006.173.18:46:41.57#ibcon#*mode == 0, iclass 15, count 0 2006.173.18:46:41.57#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.18:46:41.57#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.18:46:41.57#ibcon#*before write, iclass 15, count 0 2006.173.18:46:41.57#ibcon#enter sib2, iclass 15, count 0 2006.173.18:46:41.57#ibcon#flushed, iclass 15, count 0 2006.173.18:46:41.57#ibcon#about to write, iclass 15, count 0 2006.173.18:46:41.57#ibcon#wrote, iclass 15, count 0 2006.173.18:46:41.57#ibcon#about to read 3, iclass 15, count 0 2006.173.18:46:41.61#ibcon#read 3, iclass 15, count 0 2006.173.18:46:41.61#ibcon#about to read 4, iclass 15, count 0 2006.173.18:46:41.61#ibcon#read 4, iclass 15, count 0 2006.173.18:46:41.61#ibcon#about to read 5, iclass 15, count 0 2006.173.18:46:41.61#ibcon#read 5, iclass 15, count 0 2006.173.18:46:41.61#ibcon#about to read 6, iclass 15, count 0 2006.173.18:46:41.61#ibcon#read 6, iclass 15, count 0 2006.173.18:46:41.61#ibcon#end of sib2, iclass 15, count 0 2006.173.18:46:41.61#ibcon#*after write, iclass 15, count 0 2006.173.18:46:41.61#ibcon#*before return 0, iclass 15, count 0 2006.173.18:46:41.61#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.18:46:41.61#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.18:46:41.61#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.18:46:41.61#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.18:46:41.61$vck44/va=8,4 2006.173.18:46:41.61#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.18:46:41.61#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.18:46:41.61#ibcon#ireg 11 cls_cnt 2 2006.173.18:46:41.61#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.18:46:41.67#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.18:46:41.67#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.18:46:41.67#ibcon#enter wrdev, iclass 17, count 2 2006.173.18:46:41.67#ibcon#first serial, iclass 17, count 2 2006.173.18:46:41.67#ibcon#enter sib2, iclass 17, count 2 2006.173.18:46:41.67#ibcon#flushed, iclass 17, count 2 2006.173.18:46:41.67#ibcon#about to write, iclass 17, count 2 2006.173.18:46:41.67#ibcon#wrote, iclass 17, count 2 2006.173.18:46:41.67#ibcon#about to read 3, iclass 17, count 2 2006.173.18:46:41.69#ibcon#read 3, iclass 17, count 2 2006.173.18:46:41.69#ibcon#about to read 4, iclass 17, count 2 2006.173.18:46:41.69#ibcon#read 4, iclass 17, count 2 2006.173.18:46:41.69#ibcon#about to read 5, iclass 17, count 2 2006.173.18:46:41.69#ibcon#read 5, iclass 17, count 2 2006.173.18:46:41.69#ibcon#about to read 6, iclass 17, count 2 2006.173.18:46:41.69#ibcon#read 6, iclass 17, count 2 2006.173.18:46:41.69#ibcon#end of sib2, iclass 17, count 2 2006.173.18:46:41.69#ibcon#*mode == 0, iclass 17, count 2 2006.173.18:46:41.69#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.18:46:41.69#ibcon#[25=AT08-04\r\n] 2006.173.18:46:41.69#ibcon#*before write, iclass 17, count 2 2006.173.18:46:41.69#ibcon#enter sib2, iclass 17, count 2 2006.173.18:46:41.69#ibcon#flushed, iclass 17, count 2 2006.173.18:46:41.69#ibcon#about to write, iclass 17, count 2 2006.173.18:46:41.69#ibcon#wrote, iclass 17, count 2 2006.173.18:46:41.69#ibcon#about to read 3, iclass 17, count 2 2006.173.18:46:41.72#ibcon#read 3, iclass 17, count 2 2006.173.18:46:41.72#ibcon#about to read 4, iclass 17, count 2 2006.173.18:46:41.72#ibcon#read 4, iclass 17, count 2 2006.173.18:46:41.72#ibcon#about to read 5, iclass 17, count 2 2006.173.18:46:41.72#ibcon#read 5, iclass 17, count 2 2006.173.18:46:41.72#ibcon#about to read 6, iclass 17, count 2 2006.173.18:46:41.72#ibcon#read 6, iclass 17, count 2 2006.173.18:46:41.72#ibcon#end of sib2, iclass 17, count 2 2006.173.18:46:41.72#ibcon#*after write, iclass 17, count 2 2006.173.18:46:41.72#ibcon#*before return 0, iclass 17, count 2 2006.173.18:46:41.72#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.18:46:41.72#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.18:46:41.72#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.18:46:41.72#ibcon#ireg 7 cls_cnt 0 2006.173.18:46:41.72#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.18:46:41.84#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.18:46:41.84#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.18:46:41.84#ibcon#enter wrdev, iclass 17, count 0 2006.173.18:46:41.84#ibcon#first serial, iclass 17, count 0 2006.173.18:46:41.84#ibcon#enter sib2, iclass 17, count 0 2006.173.18:46:41.84#ibcon#flushed, iclass 17, count 0 2006.173.18:46:41.84#ibcon#about to write, iclass 17, count 0 2006.173.18:46:41.84#ibcon#wrote, iclass 17, count 0 2006.173.18:46:41.84#ibcon#about to read 3, iclass 17, count 0 2006.173.18:46:41.86#ibcon#read 3, iclass 17, count 0 2006.173.18:46:41.86#ibcon#about to read 4, iclass 17, count 0 2006.173.18:46:41.86#ibcon#read 4, iclass 17, count 0 2006.173.18:46:41.86#ibcon#about to read 5, iclass 17, count 0 2006.173.18:46:41.86#ibcon#read 5, iclass 17, count 0 2006.173.18:46:41.86#ibcon#about to read 6, iclass 17, count 0 2006.173.18:46:41.86#ibcon#read 6, iclass 17, count 0 2006.173.18:46:41.86#ibcon#end of sib2, iclass 17, count 0 2006.173.18:46:41.86#ibcon#*mode == 0, iclass 17, count 0 2006.173.18:46:41.86#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.18:46:41.86#ibcon#[25=USB\r\n] 2006.173.18:46:41.86#ibcon#*before write, iclass 17, count 0 2006.173.18:46:41.86#ibcon#enter sib2, iclass 17, count 0 2006.173.18:46:41.86#ibcon#flushed, iclass 17, count 0 2006.173.18:46:41.86#ibcon#about to write, iclass 17, count 0 2006.173.18:46:41.86#ibcon#wrote, iclass 17, count 0 2006.173.18:46:41.86#ibcon#about to read 3, iclass 17, count 0 2006.173.18:46:41.89#ibcon#read 3, iclass 17, count 0 2006.173.18:46:41.89#ibcon#about to read 4, iclass 17, count 0 2006.173.18:46:41.89#ibcon#read 4, iclass 17, count 0 2006.173.18:46:41.89#ibcon#about to read 5, iclass 17, count 0 2006.173.18:46:41.89#ibcon#read 5, iclass 17, count 0 2006.173.18:46:41.89#ibcon#about to read 6, iclass 17, count 0 2006.173.18:46:41.89#ibcon#read 6, iclass 17, count 0 2006.173.18:46:41.89#ibcon#end of sib2, iclass 17, count 0 2006.173.18:46:41.89#ibcon#*after write, iclass 17, count 0 2006.173.18:46:41.89#ibcon#*before return 0, iclass 17, count 0 2006.173.18:46:41.89#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.18:46:41.89#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.18:46:41.89#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.18:46:41.89#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.18:46:41.89$vck44/vblo=1,629.99 2006.173.18:46:41.89#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.18:46:41.89#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.18:46:41.89#ibcon#ireg 17 cls_cnt 0 2006.173.18:46:41.89#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.18:46:41.89#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.18:46:41.89#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.18:46:41.89#ibcon#enter wrdev, iclass 19, count 0 2006.173.18:46:41.89#ibcon#first serial, iclass 19, count 0 2006.173.18:46:41.89#ibcon#enter sib2, iclass 19, count 0 2006.173.18:46:41.89#ibcon#flushed, iclass 19, count 0 2006.173.18:46:41.89#ibcon#about to write, iclass 19, count 0 2006.173.18:46:41.89#ibcon#wrote, iclass 19, count 0 2006.173.18:46:41.89#ibcon#about to read 3, iclass 19, count 0 2006.173.18:46:41.91#ibcon#read 3, iclass 19, count 0 2006.173.18:46:41.91#ibcon#about to read 4, iclass 19, count 0 2006.173.18:46:41.91#ibcon#read 4, iclass 19, count 0 2006.173.18:46:41.91#ibcon#about to read 5, iclass 19, count 0 2006.173.18:46:41.91#ibcon#read 5, iclass 19, count 0 2006.173.18:46:41.91#ibcon#about to read 6, iclass 19, count 0 2006.173.18:46:41.91#ibcon#read 6, iclass 19, count 0 2006.173.18:46:41.91#ibcon#end of sib2, iclass 19, count 0 2006.173.18:46:41.91#ibcon#*mode == 0, iclass 19, count 0 2006.173.18:46:41.91#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.18:46:41.91#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.18:46:41.91#ibcon#*before write, iclass 19, count 0 2006.173.18:46:41.91#ibcon#enter sib2, iclass 19, count 0 2006.173.18:46:41.91#ibcon#flushed, iclass 19, count 0 2006.173.18:46:41.91#ibcon#about to write, iclass 19, count 0 2006.173.18:46:41.91#ibcon#wrote, iclass 19, count 0 2006.173.18:46:41.91#ibcon#about to read 3, iclass 19, count 0 2006.173.18:46:41.95#ibcon#read 3, iclass 19, count 0 2006.173.18:46:41.95#ibcon#about to read 4, iclass 19, count 0 2006.173.18:46:41.95#ibcon#read 4, iclass 19, count 0 2006.173.18:46:41.95#ibcon#about to read 5, iclass 19, count 0 2006.173.18:46:41.95#ibcon#read 5, iclass 19, count 0 2006.173.18:46:41.95#ibcon#about to read 6, iclass 19, count 0 2006.173.18:46:41.95#ibcon#read 6, iclass 19, count 0 2006.173.18:46:41.95#ibcon#end of sib2, iclass 19, count 0 2006.173.18:46:41.95#ibcon#*after write, iclass 19, count 0 2006.173.18:46:41.95#ibcon#*before return 0, iclass 19, count 0 2006.173.18:46:41.95#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.18:46:41.95#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.18:46:41.95#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.18:46:41.95#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.18:46:41.95$vck44/vb=1,4 2006.173.18:46:41.95#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.18:46:41.95#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.18:46:41.95#ibcon#ireg 11 cls_cnt 2 2006.173.18:46:41.95#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.18:46:41.95#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.18:46:41.95#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.18:46:41.95#ibcon#enter wrdev, iclass 21, count 2 2006.173.18:46:41.95#ibcon#first serial, iclass 21, count 2 2006.173.18:46:41.95#ibcon#enter sib2, iclass 21, count 2 2006.173.18:46:41.95#ibcon#flushed, iclass 21, count 2 2006.173.18:46:41.95#ibcon#about to write, iclass 21, count 2 2006.173.18:46:41.95#ibcon#wrote, iclass 21, count 2 2006.173.18:46:41.95#ibcon#about to read 3, iclass 21, count 2 2006.173.18:46:41.97#ibcon#read 3, iclass 21, count 2 2006.173.18:46:41.97#ibcon#about to read 4, iclass 21, count 2 2006.173.18:46:41.97#ibcon#read 4, iclass 21, count 2 2006.173.18:46:41.97#ibcon#about to read 5, iclass 21, count 2 2006.173.18:46:41.97#ibcon#read 5, iclass 21, count 2 2006.173.18:46:41.97#ibcon#about to read 6, iclass 21, count 2 2006.173.18:46:41.97#ibcon#read 6, iclass 21, count 2 2006.173.18:46:41.97#ibcon#end of sib2, iclass 21, count 2 2006.173.18:46:41.97#ibcon#*mode == 0, iclass 21, count 2 2006.173.18:46:41.97#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.18:46:41.97#ibcon#[27=AT01-04\r\n] 2006.173.18:46:41.97#ibcon#*before write, iclass 21, count 2 2006.173.18:46:41.97#ibcon#enter sib2, iclass 21, count 2 2006.173.18:46:41.97#ibcon#flushed, iclass 21, count 2 2006.173.18:46:41.97#ibcon#about to write, iclass 21, count 2 2006.173.18:46:41.97#ibcon#wrote, iclass 21, count 2 2006.173.18:46:41.97#ibcon#about to read 3, iclass 21, count 2 2006.173.18:46:42.00#ibcon#read 3, iclass 21, count 2 2006.173.18:46:42.00#ibcon#about to read 4, iclass 21, count 2 2006.173.18:46:42.00#ibcon#read 4, iclass 21, count 2 2006.173.18:46:42.00#ibcon#about to read 5, iclass 21, count 2 2006.173.18:46:42.00#ibcon#read 5, iclass 21, count 2 2006.173.18:46:42.00#ibcon#about to read 6, iclass 21, count 2 2006.173.18:46:42.00#ibcon#read 6, iclass 21, count 2 2006.173.18:46:42.00#ibcon#end of sib2, iclass 21, count 2 2006.173.18:46:42.00#ibcon#*after write, iclass 21, count 2 2006.173.18:46:42.00#ibcon#*before return 0, iclass 21, count 2 2006.173.18:46:42.00#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.18:46:42.00#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.18:46:42.00#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.18:46:42.00#ibcon#ireg 7 cls_cnt 0 2006.173.18:46:42.00#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.18:46:42.12#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.18:46:42.12#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.18:46:42.12#ibcon#enter wrdev, iclass 21, count 0 2006.173.18:46:42.12#ibcon#first serial, iclass 21, count 0 2006.173.18:46:42.12#ibcon#enter sib2, iclass 21, count 0 2006.173.18:46:42.12#ibcon#flushed, iclass 21, count 0 2006.173.18:46:42.12#ibcon#about to write, iclass 21, count 0 2006.173.18:46:42.12#ibcon#wrote, iclass 21, count 0 2006.173.18:46:42.12#ibcon#about to read 3, iclass 21, count 0 2006.173.18:46:42.14#ibcon#read 3, iclass 21, count 0 2006.173.18:46:42.14#ibcon#about to read 4, iclass 21, count 0 2006.173.18:46:42.14#ibcon#read 4, iclass 21, count 0 2006.173.18:46:42.14#ibcon#about to read 5, iclass 21, count 0 2006.173.18:46:42.14#ibcon#read 5, iclass 21, count 0 2006.173.18:46:42.14#ibcon#about to read 6, iclass 21, count 0 2006.173.18:46:42.14#ibcon#read 6, iclass 21, count 0 2006.173.18:46:42.14#ibcon#end of sib2, iclass 21, count 0 2006.173.18:46:42.14#ibcon#*mode == 0, iclass 21, count 0 2006.173.18:46:42.14#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.18:46:42.14#ibcon#[27=USB\r\n] 2006.173.18:46:42.14#ibcon#*before write, iclass 21, count 0 2006.173.18:46:42.14#ibcon#enter sib2, iclass 21, count 0 2006.173.18:46:42.14#ibcon#flushed, iclass 21, count 0 2006.173.18:46:42.14#ibcon#about to write, iclass 21, count 0 2006.173.18:46:42.14#ibcon#wrote, iclass 21, count 0 2006.173.18:46:42.14#ibcon#about to read 3, iclass 21, count 0 2006.173.18:46:42.17#ibcon#read 3, iclass 21, count 0 2006.173.18:46:42.17#ibcon#about to read 4, iclass 21, count 0 2006.173.18:46:42.17#ibcon#read 4, iclass 21, count 0 2006.173.18:46:42.17#ibcon#about to read 5, iclass 21, count 0 2006.173.18:46:42.17#ibcon#read 5, iclass 21, count 0 2006.173.18:46:42.17#ibcon#about to read 6, iclass 21, count 0 2006.173.18:46:42.17#ibcon#read 6, iclass 21, count 0 2006.173.18:46:42.17#ibcon#end of sib2, iclass 21, count 0 2006.173.18:46:42.17#ibcon#*after write, iclass 21, count 0 2006.173.18:46:42.17#ibcon#*before return 0, iclass 21, count 0 2006.173.18:46:42.17#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.18:46:42.17#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.18:46:42.17#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.18:46:42.17#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.18:46:42.17$vck44/vblo=2,634.99 2006.173.18:46:42.17#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.18:46:42.17#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.18:46:42.17#ibcon#ireg 17 cls_cnt 0 2006.173.18:46:42.17#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.18:46:42.17#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.18:46:42.17#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.18:46:42.17#ibcon#enter wrdev, iclass 23, count 0 2006.173.18:46:42.17#ibcon#first serial, iclass 23, count 0 2006.173.18:46:42.17#ibcon#enter sib2, iclass 23, count 0 2006.173.18:46:42.17#ibcon#flushed, iclass 23, count 0 2006.173.18:46:42.17#ibcon#about to write, iclass 23, count 0 2006.173.18:46:42.17#ibcon#wrote, iclass 23, count 0 2006.173.18:46:42.17#ibcon#about to read 3, iclass 23, count 0 2006.173.18:46:42.19#ibcon#read 3, iclass 23, count 0 2006.173.18:46:42.19#ibcon#about to read 4, iclass 23, count 0 2006.173.18:46:42.19#ibcon#read 4, iclass 23, count 0 2006.173.18:46:42.19#ibcon#about to read 5, iclass 23, count 0 2006.173.18:46:42.19#ibcon#read 5, iclass 23, count 0 2006.173.18:46:42.19#ibcon#about to read 6, iclass 23, count 0 2006.173.18:46:42.19#ibcon#read 6, iclass 23, count 0 2006.173.18:46:42.19#ibcon#end of sib2, iclass 23, count 0 2006.173.18:46:42.19#ibcon#*mode == 0, iclass 23, count 0 2006.173.18:46:42.19#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.18:46:42.19#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.18:46:42.19#ibcon#*before write, iclass 23, count 0 2006.173.18:46:42.19#ibcon#enter sib2, iclass 23, count 0 2006.173.18:46:42.19#ibcon#flushed, iclass 23, count 0 2006.173.18:46:42.19#ibcon#about to write, iclass 23, count 0 2006.173.18:46:42.19#ibcon#wrote, iclass 23, count 0 2006.173.18:46:42.19#ibcon#about to read 3, iclass 23, count 0 2006.173.18:46:42.23#ibcon#read 3, iclass 23, count 0 2006.173.18:46:42.23#ibcon#about to read 4, iclass 23, count 0 2006.173.18:46:42.23#ibcon#read 4, iclass 23, count 0 2006.173.18:46:42.23#ibcon#about to read 5, iclass 23, count 0 2006.173.18:46:42.23#ibcon#read 5, iclass 23, count 0 2006.173.18:46:42.23#ibcon#about to read 6, iclass 23, count 0 2006.173.18:46:42.23#ibcon#read 6, iclass 23, count 0 2006.173.18:46:42.23#ibcon#end of sib2, iclass 23, count 0 2006.173.18:46:42.23#ibcon#*after write, iclass 23, count 0 2006.173.18:46:42.23#ibcon#*before return 0, iclass 23, count 0 2006.173.18:46:42.23#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.18:46:42.23#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.18:46:42.23#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.18:46:42.23#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.18:46:42.23$vck44/vb=2,4 2006.173.18:46:42.23#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.18:46:42.23#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.18:46:42.23#ibcon#ireg 11 cls_cnt 2 2006.173.18:46:42.23#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.18:46:42.29#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.18:46:42.29#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.18:46:42.29#ibcon#enter wrdev, iclass 25, count 2 2006.173.18:46:42.29#ibcon#first serial, iclass 25, count 2 2006.173.18:46:42.29#ibcon#enter sib2, iclass 25, count 2 2006.173.18:46:42.29#ibcon#flushed, iclass 25, count 2 2006.173.18:46:42.29#ibcon#about to write, iclass 25, count 2 2006.173.18:46:42.29#ibcon#wrote, iclass 25, count 2 2006.173.18:46:42.29#ibcon#about to read 3, iclass 25, count 2 2006.173.18:46:42.31#ibcon#read 3, iclass 25, count 2 2006.173.18:46:42.31#ibcon#about to read 4, iclass 25, count 2 2006.173.18:46:42.31#ibcon#read 4, iclass 25, count 2 2006.173.18:46:42.31#ibcon#about to read 5, iclass 25, count 2 2006.173.18:46:42.31#ibcon#read 5, iclass 25, count 2 2006.173.18:46:42.31#ibcon#about to read 6, iclass 25, count 2 2006.173.18:46:42.31#ibcon#read 6, iclass 25, count 2 2006.173.18:46:42.31#ibcon#end of sib2, iclass 25, count 2 2006.173.18:46:42.31#ibcon#*mode == 0, iclass 25, count 2 2006.173.18:46:42.31#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.18:46:42.31#ibcon#[27=AT02-04\r\n] 2006.173.18:46:42.31#ibcon#*before write, iclass 25, count 2 2006.173.18:46:42.31#ibcon#enter sib2, iclass 25, count 2 2006.173.18:46:42.31#ibcon#flushed, iclass 25, count 2 2006.173.18:46:42.31#ibcon#about to write, iclass 25, count 2 2006.173.18:46:42.31#ibcon#wrote, iclass 25, count 2 2006.173.18:46:42.31#ibcon#about to read 3, iclass 25, count 2 2006.173.18:46:42.34#ibcon#read 3, iclass 25, count 2 2006.173.18:46:42.34#ibcon#about to read 4, iclass 25, count 2 2006.173.18:46:42.34#ibcon#read 4, iclass 25, count 2 2006.173.18:46:42.34#ibcon#about to read 5, iclass 25, count 2 2006.173.18:46:42.34#ibcon#read 5, iclass 25, count 2 2006.173.18:46:42.34#ibcon#about to read 6, iclass 25, count 2 2006.173.18:46:42.34#ibcon#read 6, iclass 25, count 2 2006.173.18:46:42.34#ibcon#end of sib2, iclass 25, count 2 2006.173.18:46:42.34#ibcon#*after write, iclass 25, count 2 2006.173.18:46:42.34#ibcon#*before return 0, iclass 25, count 2 2006.173.18:46:42.34#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.18:46:42.34#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.18:46:42.34#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.18:46:42.34#ibcon#ireg 7 cls_cnt 0 2006.173.18:46:42.34#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.18:46:42.46#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.18:46:42.46#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.18:46:42.46#ibcon#enter wrdev, iclass 25, count 0 2006.173.18:46:42.46#ibcon#first serial, iclass 25, count 0 2006.173.18:46:42.46#ibcon#enter sib2, iclass 25, count 0 2006.173.18:46:42.46#ibcon#flushed, iclass 25, count 0 2006.173.18:46:42.46#ibcon#about to write, iclass 25, count 0 2006.173.18:46:42.46#ibcon#wrote, iclass 25, count 0 2006.173.18:46:42.46#ibcon#about to read 3, iclass 25, count 0 2006.173.18:46:42.48#ibcon#read 3, iclass 25, count 0 2006.173.18:46:42.48#ibcon#about to read 4, iclass 25, count 0 2006.173.18:46:42.48#ibcon#read 4, iclass 25, count 0 2006.173.18:46:42.48#ibcon#about to read 5, iclass 25, count 0 2006.173.18:46:42.48#ibcon#read 5, iclass 25, count 0 2006.173.18:46:42.48#ibcon#about to read 6, iclass 25, count 0 2006.173.18:46:42.48#ibcon#read 6, iclass 25, count 0 2006.173.18:46:42.48#ibcon#end of sib2, iclass 25, count 0 2006.173.18:46:42.48#ibcon#*mode == 0, iclass 25, count 0 2006.173.18:46:42.48#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.18:46:42.48#ibcon#[27=USB\r\n] 2006.173.18:46:42.48#ibcon#*before write, iclass 25, count 0 2006.173.18:46:42.48#ibcon#enter sib2, iclass 25, count 0 2006.173.18:46:42.48#ibcon#flushed, iclass 25, count 0 2006.173.18:46:42.48#ibcon#about to write, iclass 25, count 0 2006.173.18:46:42.48#ibcon#wrote, iclass 25, count 0 2006.173.18:46:42.48#ibcon#about to read 3, iclass 25, count 0 2006.173.18:46:42.51#ibcon#read 3, iclass 25, count 0 2006.173.18:46:42.51#ibcon#about to read 4, iclass 25, count 0 2006.173.18:46:42.51#ibcon#read 4, iclass 25, count 0 2006.173.18:46:42.51#ibcon#about to read 5, iclass 25, count 0 2006.173.18:46:42.51#ibcon#read 5, iclass 25, count 0 2006.173.18:46:42.51#ibcon#about to read 6, iclass 25, count 0 2006.173.18:46:42.51#ibcon#read 6, iclass 25, count 0 2006.173.18:46:42.51#ibcon#end of sib2, iclass 25, count 0 2006.173.18:46:42.51#ibcon#*after write, iclass 25, count 0 2006.173.18:46:42.51#ibcon#*before return 0, iclass 25, count 0 2006.173.18:46:42.51#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.18:46:42.51#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.18:46:42.51#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.18:46:42.51#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.18:46:42.51$vck44/vblo=3,649.99 2006.173.18:46:42.51#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.18:46:42.51#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.18:46:42.51#ibcon#ireg 17 cls_cnt 0 2006.173.18:46:42.51#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.18:46:42.51#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.18:46:42.51#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.18:46:42.51#ibcon#enter wrdev, iclass 27, count 0 2006.173.18:46:42.51#ibcon#first serial, iclass 27, count 0 2006.173.18:46:42.51#ibcon#enter sib2, iclass 27, count 0 2006.173.18:46:42.51#ibcon#flushed, iclass 27, count 0 2006.173.18:46:42.51#ibcon#about to write, iclass 27, count 0 2006.173.18:46:42.51#ibcon#wrote, iclass 27, count 0 2006.173.18:46:42.51#ibcon#about to read 3, iclass 27, count 0 2006.173.18:46:42.53#ibcon#read 3, iclass 27, count 0 2006.173.18:46:42.53#ibcon#about to read 4, iclass 27, count 0 2006.173.18:46:42.53#ibcon#read 4, iclass 27, count 0 2006.173.18:46:42.53#ibcon#about to read 5, iclass 27, count 0 2006.173.18:46:42.53#ibcon#read 5, iclass 27, count 0 2006.173.18:46:42.53#ibcon#about to read 6, iclass 27, count 0 2006.173.18:46:42.53#ibcon#read 6, iclass 27, count 0 2006.173.18:46:42.53#ibcon#end of sib2, iclass 27, count 0 2006.173.18:46:42.53#ibcon#*mode == 0, iclass 27, count 0 2006.173.18:46:42.53#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.18:46:42.53#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.18:46:42.53#ibcon#*before write, iclass 27, count 0 2006.173.18:46:42.53#ibcon#enter sib2, iclass 27, count 0 2006.173.18:46:42.53#ibcon#flushed, iclass 27, count 0 2006.173.18:46:42.53#ibcon#about to write, iclass 27, count 0 2006.173.18:46:42.53#ibcon#wrote, iclass 27, count 0 2006.173.18:46:42.53#ibcon#about to read 3, iclass 27, count 0 2006.173.18:46:42.57#ibcon#read 3, iclass 27, count 0 2006.173.18:46:42.57#ibcon#about to read 4, iclass 27, count 0 2006.173.18:46:42.57#ibcon#read 4, iclass 27, count 0 2006.173.18:46:42.57#ibcon#about to read 5, iclass 27, count 0 2006.173.18:46:42.57#ibcon#read 5, iclass 27, count 0 2006.173.18:46:42.57#ibcon#about to read 6, iclass 27, count 0 2006.173.18:46:42.57#ibcon#read 6, iclass 27, count 0 2006.173.18:46:42.57#ibcon#end of sib2, iclass 27, count 0 2006.173.18:46:42.57#ibcon#*after write, iclass 27, count 0 2006.173.18:46:42.57#ibcon#*before return 0, iclass 27, count 0 2006.173.18:46:42.57#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.18:46:42.57#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.18:46:42.57#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.18:46:42.57#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.18:46:42.57$vck44/vb=3,4 2006.173.18:46:42.57#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.18:46:42.57#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.18:46:42.57#ibcon#ireg 11 cls_cnt 2 2006.173.18:46:42.57#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.18:46:42.63#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.18:46:42.63#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.18:46:42.63#ibcon#enter wrdev, iclass 29, count 2 2006.173.18:46:42.63#ibcon#first serial, iclass 29, count 2 2006.173.18:46:42.63#ibcon#enter sib2, iclass 29, count 2 2006.173.18:46:42.63#ibcon#flushed, iclass 29, count 2 2006.173.18:46:42.63#ibcon#about to write, iclass 29, count 2 2006.173.18:46:42.63#ibcon#wrote, iclass 29, count 2 2006.173.18:46:42.63#ibcon#about to read 3, iclass 29, count 2 2006.173.18:46:42.65#ibcon#read 3, iclass 29, count 2 2006.173.18:46:42.65#ibcon#about to read 4, iclass 29, count 2 2006.173.18:46:42.65#ibcon#read 4, iclass 29, count 2 2006.173.18:46:42.65#ibcon#about to read 5, iclass 29, count 2 2006.173.18:46:42.65#ibcon#read 5, iclass 29, count 2 2006.173.18:46:42.65#ibcon#about to read 6, iclass 29, count 2 2006.173.18:46:42.65#ibcon#read 6, iclass 29, count 2 2006.173.18:46:42.65#ibcon#end of sib2, iclass 29, count 2 2006.173.18:46:42.65#ibcon#*mode == 0, iclass 29, count 2 2006.173.18:46:42.65#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.18:46:42.65#ibcon#[27=AT03-04\r\n] 2006.173.18:46:42.65#ibcon#*before write, iclass 29, count 2 2006.173.18:46:42.65#ibcon#enter sib2, iclass 29, count 2 2006.173.18:46:42.65#ibcon#flushed, iclass 29, count 2 2006.173.18:46:42.65#ibcon#about to write, iclass 29, count 2 2006.173.18:46:42.65#ibcon#wrote, iclass 29, count 2 2006.173.18:46:42.65#ibcon#about to read 3, iclass 29, count 2 2006.173.18:46:42.68#ibcon#read 3, iclass 29, count 2 2006.173.18:46:42.68#ibcon#about to read 4, iclass 29, count 2 2006.173.18:46:42.68#ibcon#read 4, iclass 29, count 2 2006.173.18:46:42.68#ibcon#about to read 5, iclass 29, count 2 2006.173.18:46:42.68#ibcon#read 5, iclass 29, count 2 2006.173.18:46:42.68#ibcon#about to read 6, iclass 29, count 2 2006.173.18:46:42.68#ibcon#read 6, iclass 29, count 2 2006.173.18:46:42.68#ibcon#end of sib2, iclass 29, count 2 2006.173.18:46:42.68#ibcon#*after write, iclass 29, count 2 2006.173.18:46:42.68#ibcon#*before return 0, iclass 29, count 2 2006.173.18:46:42.68#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.18:46:42.68#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.18:46:42.68#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.18:46:42.68#ibcon#ireg 7 cls_cnt 0 2006.173.18:46:42.68#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.18:46:42.80#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.18:46:42.80#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.18:46:42.80#ibcon#enter wrdev, iclass 29, count 0 2006.173.18:46:42.80#ibcon#first serial, iclass 29, count 0 2006.173.18:46:42.80#ibcon#enter sib2, iclass 29, count 0 2006.173.18:46:42.80#ibcon#flushed, iclass 29, count 0 2006.173.18:46:42.80#ibcon#about to write, iclass 29, count 0 2006.173.18:46:42.80#ibcon#wrote, iclass 29, count 0 2006.173.18:46:42.80#ibcon#about to read 3, iclass 29, count 0 2006.173.18:46:42.82#ibcon#read 3, iclass 29, count 0 2006.173.18:46:42.82#ibcon#about to read 4, iclass 29, count 0 2006.173.18:46:42.82#ibcon#read 4, iclass 29, count 0 2006.173.18:46:42.82#ibcon#about to read 5, iclass 29, count 0 2006.173.18:46:42.82#ibcon#read 5, iclass 29, count 0 2006.173.18:46:42.82#ibcon#about to read 6, iclass 29, count 0 2006.173.18:46:42.82#ibcon#read 6, iclass 29, count 0 2006.173.18:46:42.82#ibcon#end of sib2, iclass 29, count 0 2006.173.18:46:42.82#ibcon#*mode == 0, iclass 29, count 0 2006.173.18:46:42.82#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.18:46:42.82#ibcon#[27=USB\r\n] 2006.173.18:46:42.82#ibcon#*before write, iclass 29, count 0 2006.173.18:46:42.82#ibcon#enter sib2, iclass 29, count 0 2006.173.18:46:42.82#ibcon#flushed, iclass 29, count 0 2006.173.18:46:42.82#ibcon#about to write, iclass 29, count 0 2006.173.18:46:42.82#ibcon#wrote, iclass 29, count 0 2006.173.18:46:42.82#ibcon#about to read 3, iclass 29, count 0 2006.173.18:46:42.85#ibcon#read 3, iclass 29, count 0 2006.173.18:46:42.85#ibcon#about to read 4, iclass 29, count 0 2006.173.18:46:42.85#ibcon#read 4, iclass 29, count 0 2006.173.18:46:42.85#ibcon#about to read 5, iclass 29, count 0 2006.173.18:46:42.85#ibcon#read 5, iclass 29, count 0 2006.173.18:46:42.85#ibcon#about to read 6, iclass 29, count 0 2006.173.18:46:42.85#ibcon#read 6, iclass 29, count 0 2006.173.18:46:42.85#ibcon#end of sib2, iclass 29, count 0 2006.173.18:46:42.85#ibcon#*after write, iclass 29, count 0 2006.173.18:46:42.85#ibcon#*before return 0, iclass 29, count 0 2006.173.18:46:42.85#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.18:46:42.85#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.18:46:42.85#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.18:46:42.85#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.18:46:42.85$vck44/vblo=4,679.99 2006.173.18:46:42.85#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.18:46:42.85#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.18:46:42.85#ibcon#ireg 17 cls_cnt 0 2006.173.18:46:42.85#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.18:46:42.85#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.18:46:42.85#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.18:46:42.85#ibcon#enter wrdev, iclass 31, count 0 2006.173.18:46:42.85#ibcon#first serial, iclass 31, count 0 2006.173.18:46:42.85#ibcon#enter sib2, iclass 31, count 0 2006.173.18:46:42.85#ibcon#flushed, iclass 31, count 0 2006.173.18:46:42.85#ibcon#about to write, iclass 31, count 0 2006.173.18:46:42.85#ibcon#wrote, iclass 31, count 0 2006.173.18:46:42.85#ibcon#about to read 3, iclass 31, count 0 2006.173.18:46:42.87#ibcon#read 3, iclass 31, count 0 2006.173.18:46:42.87#ibcon#about to read 4, iclass 31, count 0 2006.173.18:46:42.87#ibcon#read 4, iclass 31, count 0 2006.173.18:46:42.87#ibcon#about to read 5, iclass 31, count 0 2006.173.18:46:42.87#ibcon#read 5, iclass 31, count 0 2006.173.18:46:42.87#ibcon#about to read 6, iclass 31, count 0 2006.173.18:46:42.87#ibcon#read 6, iclass 31, count 0 2006.173.18:46:42.87#ibcon#end of sib2, iclass 31, count 0 2006.173.18:46:42.87#ibcon#*mode == 0, iclass 31, count 0 2006.173.18:46:42.87#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.18:46:42.87#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.18:46:42.87#ibcon#*before write, iclass 31, count 0 2006.173.18:46:42.87#ibcon#enter sib2, iclass 31, count 0 2006.173.18:46:42.87#ibcon#flushed, iclass 31, count 0 2006.173.18:46:42.87#ibcon#about to write, iclass 31, count 0 2006.173.18:46:42.87#ibcon#wrote, iclass 31, count 0 2006.173.18:46:42.87#ibcon#about to read 3, iclass 31, count 0 2006.173.18:46:42.91#ibcon#read 3, iclass 31, count 0 2006.173.18:46:42.91#ibcon#about to read 4, iclass 31, count 0 2006.173.18:46:42.91#ibcon#read 4, iclass 31, count 0 2006.173.18:46:42.91#ibcon#about to read 5, iclass 31, count 0 2006.173.18:46:42.91#ibcon#read 5, iclass 31, count 0 2006.173.18:46:42.91#ibcon#about to read 6, iclass 31, count 0 2006.173.18:46:42.91#ibcon#read 6, iclass 31, count 0 2006.173.18:46:42.91#ibcon#end of sib2, iclass 31, count 0 2006.173.18:46:42.91#ibcon#*after write, iclass 31, count 0 2006.173.18:46:42.91#ibcon#*before return 0, iclass 31, count 0 2006.173.18:46:42.91#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.18:46:42.91#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.18:46:42.91#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.18:46:42.91#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.18:46:42.91$vck44/vb=4,4 2006.173.18:46:42.91#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.173.18:46:42.91#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.173.18:46:42.91#ibcon#ireg 11 cls_cnt 2 2006.173.18:46:42.91#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.18:46:42.97#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.18:46:42.97#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.18:46:42.97#ibcon#enter wrdev, iclass 33, count 2 2006.173.18:46:42.97#ibcon#first serial, iclass 33, count 2 2006.173.18:46:42.97#ibcon#enter sib2, iclass 33, count 2 2006.173.18:46:42.97#ibcon#flushed, iclass 33, count 2 2006.173.18:46:42.97#ibcon#about to write, iclass 33, count 2 2006.173.18:46:42.97#ibcon#wrote, iclass 33, count 2 2006.173.18:46:42.97#ibcon#about to read 3, iclass 33, count 2 2006.173.18:46:42.99#ibcon#read 3, iclass 33, count 2 2006.173.18:46:42.99#ibcon#about to read 4, iclass 33, count 2 2006.173.18:46:42.99#ibcon#read 4, iclass 33, count 2 2006.173.18:46:42.99#ibcon#about to read 5, iclass 33, count 2 2006.173.18:46:42.99#ibcon#read 5, iclass 33, count 2 2006.173.18:46:42.99#ibcon#about to read 6, iclass 33, count 2 2006.173.18:46:42.99#ibcon#read 6, iclass 33, count 2 2006.173.18:46:42.99#ibcon#end of sib2, iclass 33, count 2 2006.173.18:46:42.99#ibcon#*mode == 0, iclass 33, count 2 2006.173.18:46:42.99#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.173.18:46:42.99#ibcon#[27=AT04-04\r\n] 2006.173.18:46:42.99#ibcon#*before write, iclass 33, count 2 2006.173.18:46:42.99#ibcon#enter sib2, iclass 33, count 2 2006.173.18:46:42.99#ibcon#flushed, iclass 33, count 2 2006.173.18:46:42.99#ibcon#about to write, iclass 33, count 2 2006.173.18:46:42.99#ibcon#wrote, iclass 33, count 2 2006.173.18:46:42.99#ibcon#about to read 3, iclass 33, count 2 2006.173.18:46:43.02#ibcon#read 3, iclass 33, count 2 2006.173.18:46:43.02#ibcon#about to read 4, iclass 33, count 2 2006.173.18:46:43.02#ibcon#read 4, iclass 33, count 2 2006.173.18:46:43.02#ibcon#about to read 5, iclass 33, count 2 2006.173.18:46:43.02#ibcon#read 5, iclass 33, count 2 2006.173.18:46:43.02#ibcon#about to read 6, iclass 33, count 2 2006.173.18:46:43.02#ibcon#read 6, iclass 33, count 2 2006.173.18:46:43.02#ibcon#end of sib2, iclass 33, count 2 2006.173.18:46:43.02#ibcon#*after write, iclass 33, count 2 2006.173.18:46:43.02#ibcon#*before return 0, iclass 33, count 2 2006.173.18:46:43.02#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.18:46:43.02#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.173.18:46:43.02#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.173.18:46:43.02#ibcon#ireg 7 cls_cnt 0 2006.173.18:46:43.02#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.18:46:43.14#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.18:46:43.14#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.18:46:43.14#ibcon#enter wrdev, iclass 33, count 0 2006.173.18:46:43.14#ibcon#first serial, iclass 33, count 0 2006.173.18:46:43.14#ibcon#enter sib2, iclass 33, count 0 2006.173.18:46:43.14#ibcon#flushed, iclass 33, count 0 2006.173.18:46:43.14#ibcon#about to write, iclass 33, count 0 2006.173.18:46:43.14#ibcon#wrote, iclass 33, count 0 2006.173.18:46:43.14#ibcon#about to read 3, iclass 33, count 0 2006.173.18:46:43.16#ibcon#read 3, iclass 33, count 0 2006.173.18:46:43.16#ibcon#about to read 4, iclass 33, count 0 2006.173.18:46:43.16#ibcon#read 4, iclass 33, count 0 2006.173.18:46:43.16#ibcon#about to read 5, iclass 33, count 0 2006.173.18:46:43.16#ibcon#read 5, iclass 33, count 0 2006.173.18:46:43.16#ibcon#about to read 6, iclass 33, count 0 2006.173.18:46:43.16#ibcon#read 6, iclass 33, count 0 2006.173.18:46:43.16#ibcon#end of sib2, iclass 33, count 0 2006.173.18:46:43.16#ibcon#*mode == 0, iclass 33, count 0 2006.173.18:46:43.16#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.18:46:43.16#ibcon#[27=USB\r\n] 2006.173.18:46:43.16#ibcon#*before write, iclass 33, count 0 2006.173.18:46:43.16#ibcon#enter sib2, iclass 33, count 0 2006.173.18:46:43.16#ibcon#flushed, iclass 33, count 0 2006.173.18:46:43.16#ibcon#about to write, iclass 33, count 0 2006.173.18:46:43.16#ibcon#wrote, iclass 33, count 0 2006.173.18:46:43.16#ibcon#about to read 3, iclass 33, count 0 2006.173.18:46:43.19#ibcon#read 3, iclass 33, count 0 2006.173.18:46:43.19#ibcon#about to read 4, iclass 33, count 0 2006.173.18:46:43.19#ibcon#read 4, iclass 33, count 0 2006.173.18:46:43.19#ibcon#about to read 5, iclass 33, count 0 2006.173.18:46:43.19#ibcon#read 5, iclass 33, count 0 2006.173.18:46:43.19#ibcon#about to read 6, iclass 33, count 0 2006.173.18:46:43.19#ibcon#read 6, iclass 33, count 0 2006.173.18:46:43.19#ibcon#end of sib2, iclass 33, count 0 2006.173.18:46:43.19#ibcon#*after write, iclass 33, count 0 2006.173.18:46:43.19#ibcon#*before return 0, iclass 33, count 0 2006.173.18:46:43.19#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.18:46:43.19#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.173.18:46:43.19#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.18:46:43.19#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.18:46:43.19$vck44/vblo=5,709.99 2006.173.18:46:43.19#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.18:46:43.19#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.18:46:43.19#ibcon#ireg 17 cls_cnt 0 2006.173.18:46:43.19#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.18:46:43.19#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.18:46:43.19#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.18:46:43.19#ibcon#enter wrdev, iclass 35, count 0 2006.173.18:46:43.19#ibcon#first serial, iclass 35, count 0 2006.173.18:46:43.19#ibcon#enter sib2, iclass 35, count 0 2006.173.18:46:43.19#ibcon#flushed, iclass 35, count 0 2006.173.18:46:43.19#ibcon#about to write, iclass 35, count 0 2006.173.18:46:43.19#ibcon#wrote, iclass 35, count 0 2006.173.18:46:43.19#ibcon#about to read 3, iclass 35, count 0 2006.173.18:46:43.21#ibcon#read 3, iclass 35, count 0 2006.173.18:46:43.21#ibcon#about to read 4, iclass 35, count 0 2006.173.18:46:43.21#ibcon#read 4, iclass 35, count 0 2006.173.18:46:43.21#ibcon#about to read 5, iclass 35, count 0 2006.173.18:46:43.21#ibcon#read 5, iclass 35, count 0 2006.173.18:46:43.21#ibcon#about to read 6, iclass 35, count 0 2006.173.18:46:43.21#ibcon#read 6, iclass 35, count 0 2006.173.18:46:43.21#ibcon#end of sib2, iclass 35, count 0 2006.173.18:46:43.21#ibcon#*mode == 0, iclass 35, count 0 2006.173.18:46:43.21#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.18:46:43.21#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.18:46:43.21#ibcon#*before write, iclass 35, count 0 2006.173.18:46:43.21#ibcon#enter sib2, iclass 35, count 0 2006.173.18:46:43.21#ibcon#flushed, iclass 35, count 0 2006.173.18:46:43.21#ibcon#about to write, iclass 35, count 0 2006.173.18:46:43.21#ibcon#wrote, iclass 35, count 0 2006.173.18:46:43.21#ibcon#about to read 3, iclass 35, count 0 2006.173.18:46:43.25#ibcon#read 3, iclass 35, count 0 2006.173.18:46:43.25#ibcon#about to read 4, iclass 35, count 0 2006.173.18:46:43.25#ibcon#read 4, iclass 35, count 0 2006.173.18:46:43.25#ibcon#about to read 5, iclass 35, count 0 2006.173.18:46:43.25#ibcon#read 5, iclass 35, count 0 2006.173.18:46:43.25#ibcon#about to read 6, iclass 35, count 0 2006.173.18:46:43.25#ibcon#read 6, iclass 35, count 0 2006.173.18:46:43.25#ibcon#end of sib2, iclass 35, count 0 2006.173.18:46:43.25#ibcon#*after write, iclass 35, count 0 2006.173.18:46:43.25#ibcon#*before return 0, iclass 35, count 0 2006.173.18:46:43.25#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.18:46:43.25#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.18:46:43.25#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.18:46:43.25#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.18:46:43.25$vck44/vb=5,4 2006.173.18:46:43.25#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.173.18:46:43.25#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.173.18:46:43.25#ibcon#ireg 11 cls_cnt 2 2006.173.18:46:43.25#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.18:46:43.31#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.18:46:43.31#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.18:46:43.31#ibcon#enter wrdev, iclass 37, count 2 2006.173.18:46:43.31#ibcon#first serial, iclass 37, count 2 2006.173.18:46:43.31#ibcon#enter sib2, iclass 37, count 2 2006.173.18:46:43.31#ibcon#flushed, iclass 37, count 2 2006.173.18:46:43.31#ibcon#about to write, iclass 37, count 2 2006.173.18:46:43.31#ibcon#wrote, iclass 37, count 2 2006.173.18:46:43.31#ibcon#about to read 3, iclass 37, count 2 2006.173.18:46:43.33#ibcon#read 3, iclass 37, count 2 2006.173.18:46:43.33#ibcon#about to read 4, iclass 37, count 2 2006.173.18:46:43.33#ibcon#read 4, iclass 37, count 2 2006.173.18:46:43.33#ibcon#about to read 5, iclass 37, count 2 2006.173.18:46:43.33#ibcon#read 5, iclass 37, count 2 2006.173.18:46:43.33#ibcon#about to read 6, iclass 37, count 2 2006.173.18:46:43.33#ibcon#read 6, iclass 37, count 2 2006.173.18:46:43.33#ibcon#end of sib2, iclass 37, count 2 2006.173.18:46:43.33#ibcon#*mode == 0, iclass 37, count 2 2006.173.18:46:43.33#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.173.18:46:43.33#ibcon#[27=AT05-04\r\n] 2006.173.18:46:43.33#ibcon#*before write, iclass 37, count 2 2006.173.18:46:43.33#ibcon#enter sib2, iclass 37, count 2 2006.173.18:46:43.33#ibcon#flushed, iclass 37, count 2 2006.173.18:46:43.33#ibcon#about to write, iclass 37, count 2 2006.173.18:46:43.33#ibcon#wrote, iclass 37, count 2 2006.173.18:46:43.33#ibcon#about to read 3, iclass 37, count 2 2006.173.18:46:43.36#ibcon#read 3, iclass 37, count 2 2006.173.18:46:43.36#ibcon#about to read 4, iclass 37, count 2 2006.173.18:46:43.36#ibcon#read 4, iclass 37, count 2 2006.173.18:46:43.36#ibcon#about to read 5, iclass 37, count 2 2006.173.18:46:43.36#ibcon#read 5, iclass 37, count 2 2006.173.18:46:43.36#ibcon#about to read 6, iclass 37, count 2 2006.173.18:46:43.36#ibcon#read 6, iclass 37, count 2 2006.173.18:46:43.36#ibcon#end of sib2, iclass 37, count 2 2006.173.18:46:43.36#ibcon#*after write, iclass 37, count 2 2006.173.18:46:43.36#ibcon#*before return 0, iclass 37, count 2 2006.173.18:46:43.36#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.18:46:43.36#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.173.18:46:43.36#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.173.18:46:43.36#ibcon#ireg 7 cls_cnt 0 2006.173.18:46:43.36#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.18:46:43.48#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.18:46:43.48#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.18:46:43.48#ibcon#enter wrdev, iclass 37, count 0 2006.173.18:46:43.48#ibcon#first serial, iclass 37, count 0 2006.173.18:46:43.48#ibcon#enter sib2, iclass 37, count 0 2006.173.18:46:43.48#ibcon#flushed, iclass 37, count 0 2006.173.18:46:43.48#ibcon#about to write, iclass 37, count 0 2006.173.18:46:43.48#ibcon#wrote, iclass 37, count 0 2006.173.18:46:43.48#ibcon#about to read 3, iclass 37, count 0 2006.173.18:46:43.50#ibcon#read 3, iclass 37, count 0 2006.173.18:46:43.50#ibcon#about to read 4, iclass 37, count 0 2006.173.18:46:43.50#ibcon#read 4, iclass 37, count 0 2006.173.18:46:43.50#ibcon#about to read 5, iclass 37, count 0 2006.173.18:46:43.50#ibcon#read 5, iclass 37, count 0 2006.173.18:46:43.50#ibcon#about to read 6, iclass 37, count 0 2006.173.18:46:43.50#ibcon#read 6, iclass 37, count 0 2006.173.18:46:43.50#ibcon#end of sib2, iclass 37, count 0 2006.173.18:46:43.50#ibcon#*mode == 0, iclass 37, count 0 2006.173.18:46:43.50#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.18:46:43.50#ibcon#[27=USB\r\n] 2006.173.18:46:43.50#ibcon#*before write, iclass 37, count 0 2006.173.18:46:43.50#ibcon#enter sib2, iclass 37, count 0 2006.173.18:46:43.50#ibcon#flushed, iclass 37, count 0 2006.173.18:46:43.50#ibcon#about to write, iclass 37, count 0 2006.173.18:46:43.50#ibcon#wrote, iclass 37, count 0 2006.173.18:46:43.50#ibcon#about to read 3, iclass 37, count 0 2006.173.18:46:43.53#ibcon#read 3, iclass 37, count 0 2006.173.18:46:43.53#ibcon#about to read 4, iclass 37, count 0 2006.173.18:46:43.53#ibcon#read 4, iclass 37, count 0 2006.173.18:46:43.53#ibcon#about to read 5, iclass 37, count 0 2006.173.18:46:43.53#ibcon#read 5, iclass 37, count 0 2006.173.18:46:43.53#ibcon#about to read 6, iclass 37, count 0 2006.173.18:46:43.53#ibcon#read 6, iclass 37, count 0 2006.173.18:46:43.53#ibcon#end of sib2, iclass 37, count 0 2006.173.18:46:43.53#ibcon#*after write, iclass 37, count 0 2006.173.18:46:43.53#ibcon#*before return 0, iclass 37, count 0 2006.173.18:46:43.53#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.18:46:43.53#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.173.18:46:43.53#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.18:46:43.53#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.18:46:43.53$vck44/vblo=6,719.99 2006.173.18:46:43.53#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.18:46:43.53#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.18:46:43.53#ibcon#ireg 17 cls_cnt 0 2006.173.18:46:43.53#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.18:46:43.53#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.18:46:43.53#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.18:46:43.53#ibcon#enter wrdev, iclass 39, count 0 2006.173.18:46:43.53#ibcon#first serial, iclass 39, count 0 2006.173.18:46:43.53#ibcon#enter sib2, iclass 39, count 0 2006.173.18:46:43.53#ibcon#flushed, iclass 39, count 0 2006.173.18:46:43.53#ibcon#about to write, iclass 39, count 0 2006.173.18:46:43.53#ibcon#wrote, iclass 39, count 0 2006.173.18:46:43.53#ibcon#about to read 3, iclass 39, count 0 2006.173.18:46:43.55#ibcon#read 3, iclass 39, count 0 2006.173.18:46:43.55#ibcon#about to read 4, iclass 39, count 0 2006.173.18:46:43.55#ibcon#read 4, iclass 39, count 0 2006.173.18:46:43.55#ibcon#about to read 5, iclass 39, count 0 2006.173.18:46:43.55#ibcon#read 5, iclass 39, count 0 2006.173.18:46:43.55#ibcon#about to read 6, iclass 39, count 0 2006.173.18:46:43.55#ibcon#read 6, iclass 39, count 0 2006.173.18:46:43.55#ibcon#end of sib2, iclass 39, count 0 2006.173.18:46:43.55#ibcon#*mode == 0, iclass 39, count 0 2006.173.18:46:43.55#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.18:46:43.55#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.18:46:43.55#ibcon#*before write, iclass 39, count 0 2006.173.18:46:43.55#ibcon#enter sib2, iclass 39, count 0 2006.173.18:46:43.55#ibcon#flushed, iclass 39, count 0 2006.173.18:46:43.55#ibcon#about to write, iclass 39, count 0 2006.173.18:46:43.55#ibcon#wrote, iclass 39, count 0 2006.173.18:46:43.55#ibcon#about to read 3, iclass 39, count 0 2006.173.18:46:43.59#ibcon#read 3, iclass 39, count 0 2006.173.18:46:43.59#ibcon#about to read 4, iclass 39, count 0 2006.173.18:46:43.59#ibcon#read 4, iclass 39, count 0 2006.173.18:46:43.59#ibcon#about to read 5, iclass 39, count 0 2006.173.18:46:43.59#ibcon#read 5, iclass 39, count 0 2006.173.18:46:43.59#ibcon#about to read 6, iclass 39, count 0 2006.173.18:46:43.59#ibcon#read 6, iclass 39, count 0 2006.173.18:46:43.59#ibcon#end of sib2, iclass 39, count 0 2006.173.18:46:43.59#ibcon#*after write, iclass 39, count 0 2006.173.18:46:43.59#ibcon#*before return 0, iclass 39, count 0 2006.173.18:46:43.59#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.18:46:43.59#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.18:46:43.59#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.18:46:43.59#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.18:46:43.59$vck44/vb=6,4 2006.173.18:46:43.59#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.18:46:43.59#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.18:46:43.59#ibcon#ireg 11 cls_cnt 2 2006.173.18:46:43.59#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.18:46:43.65#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.18:46:43.65#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.18:46:43.65#ibcon#enter wrdev, iclass 3, count 2 2006.173.18:46:43.65#ibcon#first serial, iclass 3, count 2 2006.173.18:46:43.65#ibcon#enter sib2, iclass 3, count 2 2006.173.18:46:43.65#ibcon#flushed, iclass 3, count 2 2006.173.18:46:43.65#ibcon#about to write, iclass 3, count 2 2006.173.18:46:43.65#ibcon#wrote, iclass 3, count 2 2006.173.18:46:43.65#ibcon#about to read 3, iclass 3, count 2 2006.173.18:46:43.67#ibcon#read 3, iclass 3, count 2 2006.173.18:46:43.67#ibcon#about to read 4, iclass 3, count 2 2006.173.18:46:43.67#ibcon#read 4, iclass 3, count 2 2006.173.18:46:43.67#ibcon#about to read 5, iclass 3, count 2 2006.173.18:46:43.67#ibcon#read 5, iclass 3, count 2 2006.173.18:46:43.67#ibcon#about to read 6, iclass 3, count 2 2006.173.18:46:43.67#ibcon#read 6, iclass 3, count 2 2006.173.18:46:43.67#ibcon#end of sib2, iclass 3, count 2 2006.173.18:46:43.67#ibcon#*mode == 0, iclass 3, count 2 2006.173.18:46:43.67#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.18:46:43.67#ibcon#[27=AT06-04\r\n] 2006.173.18:46:43.67#ibcon#*before write, iclass 3, count 2 2006.173.18:46:43.67#ibcon#enter sib2, iclass 3, count 2 2006.173.18:46:43.67#ibcon#flushed, iclass 3, count 2 2006.173.18:46:43.67#ibcon#about to write, iclass 3, count 2 2006.173.18:46:43.67#ibcon#wrote, iclass 3, count 2 2006.173.18:46:43.67#ibcon#about to read 3, iclass 3, count 2 2006.173.18:46:43.70#ibcon#read 3, iclass 3, count 2 2006.173.18:46:43.70#ibcon#about to read 4, iclass 3, count 2 2006.173.18:46:43.70#ibcon#read 4, iclass 3, count 2 2006.173.18:46:43.70#ibcon#about to read 5, iclass 3, count 2 2006.173.18:46:43.70#ibcon#read 5, iclass 3, count 2 2006.173.18:46:43.70#ibcon#about to read 6, iclass 3, count 2 2006.173.18:46:43.70#ibcon#read 6, iclass 3, count 2 2006.173.18:46:43.70#ibcon#end of sib2, iclass 3, count 2 2006.173.18:46:43.70#ibcon#*after write, iclass 3, count 2 2006.173.18:46:43.70#ibcon#*before return 0, iclass 3, count 2 2006.173.18:46:43.70#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.18:46:43.70#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.18:46:43.70#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.18:46:43.70#ibcon#ireg 7 cls_cnt 0 2006.173.18:46:43.70#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.18:46:43.82#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.18:46:43.82#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.18:46:43.82#ibcon#enter wrdev, iclass 3, count 0 2006.173.18:46:43.82#ibcon#first serial, iclass 3, count 0 2006.173.18:46:43.82#ibcon#enter sib2, iclass 3, count 0 2006.173.18:46:43.82#ibcon#flushed, iclass 3, count 0 2006.173.18:46:43.82#ibcon#about to write, iclass 3, count 0 2006.173.18:46:43.82#ibcon#wrote, iclass 3, count 0 2006.173.18:46:43.82#ibcon#about to read 3, iclass 3, count 0 2006.173.18:46:43.84#ibcon#read 3, iclass 3, count 0 2006.173.18:46:43.84#ibcon#about to read 4, iclass 3, count 0 2006.173.18:46:43.84#ibcon#read 4, iclass 3, count 0 2006.173.18:46:43.84#ibcon#about to read 5, iclass 3, count 0 2006.173.18:46:43.84#ibcon#read 5, iclass 3, count 0 2006.173.18:46:43.84#ibcon#about to read 6, iclass 3, count 0 2006.173.18:46:43.84#ibcon#read 6, iclass 3, count 0 2006.173.18:46:43.84#ibcon#end of sib2, iclass 3, count 0 2006.173.18:46:43.84#ibcon#*mode == 0, iclass 3, count 0 2006.173.18:46:43.84#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.18:46:43.84#ibcon#[27=USB\r\n] 2006.173.18:46:43.84#ibcon#*before write, iclass 3, count 0 2006.173.18:46:43.84#ibcon#enter sib2, iclass 3, count 0 2006.173.18:46:43.84#ibcon#flushed, iclass 3, count 0 2006.173.18:46:43.84#ibcon#about to write, iclass 3, count 0 2006.173.18:46:43.84#ibcon#wrote, iclass 3, count 0 2006.173.18:46:43.84#ibcon#about to read 3, iclass 3, count 0 2006.173.18:46:43.87#ibcon#read 3, iclass 3, count 0 2006.173.18:46:43.87#ibcon#about to read 4, iclass 3, count 0 2006.173.18:46:43.87#ibcon#read 4, iclass 3, count 0 2006.173.18:46:43.87#ibcon#about to read 5, iclass 3, count 0 2006.173.18:46:43.87#ibcon#read 5, iclass 3, count 0 2006.173.18:46:43.87#ibcon#about to read 6, iclass 3, count 0 2006.173.18:46:43.87#ibcon#read 6, iclass 3, count 0 2006.173.18:46:43.87#ibcon#end of sib2, iclass 3, count 0 2006.173.18:46:43.87#ibcon#*after write, iclass 3, count 0 2006.173.18:46:43.87#ibcon#*before return 0, iclass 3, count 0 2006.173.18:46:43.87#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.18:46:43.87#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.18:46:43.87#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.18:46:43.87#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.18:46:43.87$vck44/vblo=7,734.99 2006.173.18:46:43.87#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.18:46:43.87#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.18:46:43.87#ibcon#ireg 17 cls_cnt 0 2006.173.18:46:43.87#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.18:46:43.87#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.18:46:43.87#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.18:46:43.87#ibcon#enter wrdev, iclass 5, count 0 2006.173.18:46:43.87#ibcon#first serial, iclass 5, count 0 2006.173.18:46:43.87#ibcon#enter sib2, iclass 5, count 0 2006.173.18:46:43.87#ibcon#flushed, iclass 5, count 0 2006.173.18:46:43.87#ibcon#about to write, iclass 5, count 0 2006.173.18:46:43.87#ibcon#wrote, iclass 5, count 0 2006.173.18:46:43.87#ibcon#about to read 3, iclass 5, count 0 2006.173.18:46:43.89#ibcon#read 3, iclass 5, count 0 2006.173.18:46:43.89#ibcon#about to read 4, iclass 5, count 0 2006.173.18:46:43.89#ibcon#read 4, iclass 5, count 0 2006.173.18:46:43.89#ibcon#about to read 5, iclass 5, count 0 2006.173.18:46:43.89#ibcon#read 5, iclass 5, count 0 2006.173.18:46:43.89#ibcon#about to read 6, iclass 5, count 0 2006.173.18:46:43.89#ibcon#read 6, iclass 5, count 0 2006.173.18:46:43.89#ibcon#end of sib2, iclass 5, count 0 2006.173.18:46:43.89#ibcon#*mode == 0, iclass 5, count 0 2006.173.18:46:43.89#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.18:46:43.89#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.18:46:43.89#ibcon#*before write, iclass 5, count 0 2006.173.18:46:43.89#ibcon#enter sib2, iclass 5, count 0 2006.173.18:46:43.89#ibcon#flushed, iclass 5, count 0 2006.173.18:46:43.89#ibcon#about to write, iclass 5, count 0 2006.173.18:46:43.89#ibcon#wrote, iclass 5, count 0 2006.173.18:46:43.89#ibcon#about to read 3, iclass 5, count 0 2006.173.18:46:43.93#ibcon#read 3, iclass 5, count 0 2006.173.18:46:43.93#ibcon#about to read 4, iclass 5, count 0 2006.173.18:46:43.93#ibcon#read 4, iclass 5, count 0 2006.173.18:46:43.93#ibcon#about to read 5, iclass 5, count 0 2006.173.18:46:43.93#ibcon#read 5, iclass 5, count 0 2006.173.18:46:43.93#ibcon#about to read 6, iclass 5, count 0 2006.173.18:46:43.93#ibcon#read 6, iclass 5, count 0 2006.173.18:46:43.93#ibcon#end of sib2, iclass 5, count 0 2006.173.18:46:43.93#ibcon#*after write, iclass 5, count 0 2006.173.18:46:43.93#ibcon#*before return 0, iclass 5, count 0 2006.173.18:46:43.93#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.18:46:43.93#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.18:46:43.93#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.18:46:43.93#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.18:46:43.93$vck44/vb=7,4 2006.173.18:46:43.93#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.173.18:46:43.93#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.173.18:46:43.93#ibcon#ireg 11 cls_cnt 2 2006.173.18:46:43.93#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.18:46:43.99#abcon#<5=/14 0.9 1.5 19.701001002.3\r\n> 2006.173.18:46:43.99#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.18:46:43.99#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.18:46:43.99#ibcon#enter wrdev, iclass 7, count 2 2006.173.18:46:43.99#ibcon#first serial, iclass 7, count 2 2006.173.18:46:43.99#ibcon#enter sib2, iclass 7, count 2 2006.173.18:46:43.99#ibcon#flushed, iclass 7, count 2 2006.173.18:46:43.99#ibcon#about to write, iclass 7, count 2 2006.173.18:46:43.99#ibcon#wrote, iclass 7, count 2 2006.173.18:46:43.99#ibcon#about to read 3, iclass 7, count 2 2006.173.18:46:44.01#ibcon#read 3, iclass 7, count 2 2006.173.18:46:44.01#ibcon#about to read 4, iclass 7, count 2 2006.173.18:46:44.01#ibcon#read 4, iclass 7, count 2 2006.173.18:46:44.01#ibcon#about to read 5, iclass 7, count 2 2006.173.18:46:44.01#ibcon#read 5, iclass 7, count 2 2006.173.18:46:44.01#ibcon#about to read 6, iclass 7, count 2 2006.173.18:46:44.01#ibcon#read 6, iclass 7, count 2 2006.173.18:46:44.01#ibcon#end of sib2, iclass 7, count 2 2006.173.18:46:44.01#ibcon#*mode == 0, iclass 7, count 2 2006.173.18:46:44.01#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.173.18:46:44.01#ibcon#[27=AT07-04\r\n] 2006.173.18:46:44.01#ibcon#*before write, iclass 7, count 2 2006.173.18:46:44.01#ibcon#enter sib2, iclass 7, count 2 2006.173.18:46:44.01#ibcon#flushed, iclass 7, count 2 2006.173.18:46:44.01#ibcon#about to write, iclass 7, count 2 2006.173.18:46:44.01#ibcon#wrote, iclass 7, count 2 2006.173.18:46:44.01#ibcon#about to read 3, iclass 7, count 2 2006.173.18:46:44.01#abcon#{5=INTERFACE CLEAR} 2006.173.18:46:44.04#ibcon#read 3, iclass 7, count 2 2006.173.18:46:44.04#ibcon#about to read 4, iclass 7, count 2 2006.173.18:46:44.04#ibcon#read 4, iclass 7, count 2 2006.173.18:46:44.04#ibcon#about to read 5, iclass 7, count 2 2006.173.18:46:44.04#ibcon#read 5, iclass 7, count 2 2006.173.18:46:44.04#ibcon#about to read 6, iclass 7, count 2 2006.173.18:46:44.04#ibcon#read 6, iclass 7, count 2 2006.173.18:46:44.04#ibcon#end of sib2, iclass 7, count 2 2006.173.18:46:44.04#ibcon#*after write, iclass 7, count 2 2006.173.18:46:44.04#ibcon#*before return 0, iclass 7, count 2 2006.173.18:46:44.04#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.18:46:44.04#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.173.18:46:44.04#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.173.18:46:44.04#ibcon#ireg 7 cls_cnt 0 2006.173.18:46:44.04#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.18:46:44.07#abcon#[5=S1D000X0/0*\r\n] 2006.173.18:46:44.16#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.18:46:44.16#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.18:46:44.16#ibcon#enter wrdev, iclass 7, count 0 2006.173.18:46:44.16#ibcon#first serial, iclass 7, count 0 2006.173.18:46:44.16#ibcon#enter sib2, iclass 7, count 0 2006.173.18:46:44.16#ibcon#flushed, iclass 7, count 0 2006.173.18:46:44.16#ibcon#about to write, iclass 7, count 0 2006.173.18:46:44.16#ibcon#wrote, iclass 7, count 0 2006.173.18:46:44.16#ibcon#about to read 3, iclass 7, count 0 2006.173.18:46:44.18#ibcon#read 3, iclass 7, count 0 2006.173.18:46:44.18#ibcon#about to read 4, iclass 7, count 0 2006.173.18:46:44.18#ibcon#read 4, iclass 7, count 0 2006.173.18:46:44.18#ibcon#about to read 5, iclass 7, count 0 2006.173.18:46:44.18#ibcon#read 5, iclass 7, count 0 2006.173.18:46:44.18#ibcon#about to read 6, iclass 7, count 0 2006.173.18:46:44.18#ibcon#read 6, iclass 7, count 0 2006.173.18:46:44.18#ibcon#end of sib2, iclass 7, count 0 2006.173.18:46:44.18#ibcon#*mode == 0, iclass 7, count 0 2006.173.18:46:44.18#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.18:46:44.18#ibcon#[27=USB\r\n] 2006.173.18:46:44.18#ibcon#*before write, iclass 7, count 0 2006.173.18:46:44.18#ibcon#enter sib2, iclass 7, count 0 2006.173.18:46:44.18#ibcon#flushed, iclass 7, count 0 2006.173.18:46:44.18#ibcon#about to write, iclass 7, count 0 2006.173.18:46:44.18#ibcon#wrote, iclass 7, count 0 2006.173.18:46:44.18#ibcon#about to read 3, iclass 7, count 0 2006.173.18:46:44.21#ibcon#read 3, iclass 7, count 0 2006.173.18:46:44.21#ibcon#about to read 4, iclass 7, count 0 2006.173.18:46:44.21#ibcon#read 4, iclass 7, count 0 2006.173.18:46:44.21#ibcon#about to read 5, iclass 7, count 0 2006.173.18:46:44.21#ibcon#read 5, iclass 7, count 0 2006.173.18:46:44.21#ibcon#about to read 6, iclass 7, count 0 2006.173.18:46:44.21#ibcon#read 6, iclass 7, count 0 2006.173.18:46:44.21#ibcon#end of sib2, iclass 7, count 0 2006.173.18:46:44.21#ibcon#*after write, iclass 7, count 0 2006.173.18:46:44.21#ibcon#*before return 0, iclass 7, count 0 2006.173.18:46:44.21#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.18:46:44.21#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.173.18:46:44.21#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.18:46:44.21#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.18:46:44.21$vck44/vblo=8,744.99 2006.173.18:46:44.21#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.18:46:44.21#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.18:46:44.21#ibcon#ireg 17 cls_cnt 0 2006.173.18:46:44.21#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.18:46:44.21#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.18:46:44.21#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.18:46:44.21#ibcon#enter wrdev, iclass 15, count 0 2006.173.18:46:44.21#ibcon#first serial, iclass 15, count 0 2006.173.18:46:44.21#ibcon#enter sib2, iclass 15, count 0 2006.173.18:46:44.21#ibcon#flushed, iclass 15, count 0 2006.173.18:46:44.21#ibcon#about to write, iclass 15, count 0 2006.173.18:46:44.21#ibcon#wrote, iclass 15, count 0 2006.173.18:46:44.21#ibcon#about to read 3, iclass 15, count 0 2006.173.18:46:44.23#ibcon#read 3, iclass 15, count 0 2006.173.18:46:44.23#ibcon#about to read 4, iclass 15, count 0 2006.173.18:46:44.23#ibcon#read 4, iclass 15, count 0 2006.173.18:46:44.23#ibcon#about to read 5, iclass 15, count 0 2006.173.18:46:44.23#ibcon#read 5, iclass 15, count 0 2006.173.18:46:44.23#ibcon#about to read 6, iclass 15, count 0 2006.173.18:46:44.23#ibcon#read 6, iclass 15, count 0 2006.173.18:46:44.23#ibcon#end of sib2, iclass 15, count 0 2006.173.18:46:44.23#ibcon#*mode == 0, iclass 15, count 0 2006.173.18:46:44.23#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.18:46:44.23#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.18:46:44.23#ibcon#*before write, iclass 15, count 0 2006.173.18:46:44.23#ibcon#enter sib2, iclass 15, count 0 2006.173.18:46:44.23#ibcon#flushed, iclass 15, count 0 2006.173.18:46:44.23#ibcon#about to write, iclass 15, count 0 2006.173.18:46:44.23#ibcon#wrote, iclass 15, count 0 2006.173.18:46:44.23#ibcon#about to read 3, iclass 15, count 0 2006.173.18:46:44.27#ibcon#read 3, iclass 15, count 0 2006.173.18:46:44.27#ibcon#about to read 4, iclass 15, count 0 2006.173.18:46:44.27#ibcon#read 4, iclass 15, count 0 2006.173.18:46:44.27#ibcon#about to read 5, iclass 15, count 0 2006.173.18:46:44.27#ibcon#read 5, iclass 15, count 0 2006.173.18:46:44.27#ibcon#about to read 6, iclass 15, count 0 2006.173.18:46:44.27#ibcon#read 6, iclass 15, count 0 2006.173.18:46:44.27#ibcon#end of sib2, iclass 15, count 0 2006.173.18:46:44.27#ibcon#*after write, iclass 15, count 0 2006.173.18:46:44.27#ibcon#*before return 0, iclass 15, count 0 2006.173.18:46:44.27#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.18:46:44.27#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.18:46:44.27#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.18:46:44.27#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.18:46:44.27$vck44/vb=8,4 2006.173.18:46:44.27#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.18:46:44.27#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.18:46:44.27#ibcon#ireg 11 cls_cnt 2 2006.173.18:46:44.27#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.18:46:44.33#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.18:46:44.33#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.18:46:44.33#ibcon#enter wrdev, iclass 17, count 2 2006.173.18:46:44.33#ibcon#first serial, iclass 17, count 2 2006.173.18:46:44.33#ibcon#enter sib2, iclass 17, count 2 2006.173.18:46:44.33#ibcon#flushed, iclass 17, count 2 2006.173.18:46:44.33#ibcon#about to write, iclass 17, count 2 2006.173.18:46:44.33#ibcon#wrote, iclass 17, count 2 2006.173.18:46:44.33#ibcon#about to read 3, iclass 17, count 2 2006.173.18:46:44.35#ibcon#read 3, iclass 17, count 2 2006.173.18:46:44.35#ibcon#about to read 4, iclass 17, count 2 2006.173.18:46:44.35#ibcon#read 4, iclass 17, count 2 2006.173.18:46:44.35#ibcon#about to read 5, iclass 17, count 2 2006.173.18:46:44.35#ibcon#read 5, iclass 17, count 2 2006.173.18:46:44.35#ibcon#about to read 6, iclass 17, count 2 2006.173.18:46:44.35#ibcon#read 6, iclass 17, count 2 2006.173.18:46:44.35#ibcon#end of sib2, iclass 17, count 2 2006.173.18:46:44.35#ibcon#*mode == 0, iclass 17, count 2 2006.173.18:46:44.35#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.18:46:44.35#ibcon#[27=AT08-04\r\n] 2006.173.18:46:44.35#ibcon#*before write, iclass 17, count 2 2006.173.18:46:44.35#ibcon#enter sib2, iclass 17, count 2 2006.173.18:46:44.35#ibcon#flushed, iclass 17, count 2 2006.173.18:46:44.35#ibcon#about to write, iclass 17, count 2 2006.173.18:46:44.35#ibcon#wrote, iclass 17, count 2 2006.173.18:46:44.35#ibcon#about to read 3, iclass 17, count 2 2006.173.18:46:44.38#ibcon#read 3, iclass 17, count 2 2006.173.18:46:44.38#ibcon#about to read 4, iclass 17, count 2 2006.173.18:46:44.38#ibcon#read 4, iclass 17, count 2 2006.173.18:46:44.38#ibcon#about to read 5, iclass 17, count 2 2006.173.18:46:44.38#ibcon#read 5, iclass 17, count 2 2006.173.18:46:44.38#ibcon#about to read 6, iclass 17, count 2 2006.173.18:46:44.38#ibcon#read 6, iclass 17, count 2 2006.173.18:46:44.38#ibcon#end of sib2, iclass 17, count 2 2006.173.18:46:44.38#ibcon#*after write, iclass 17, count 2 2006.173.18:46:44.38#ibcon#*before return 0, iclass 17, count 2 2006.173.18:46:44.38#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.18:46:44.38#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.18:46:44.38#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.18:46:44.38#ibcon#ireg 7 cls_cnt 0 2006.173.18:46:44.38#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.18:46:44.50#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.18:46:44.50#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.18:46:44.50#ibcon#enter wrdev, iclass 17, count 0 2006.173.18:46:44.50#ibcon#first serial, iclass 17, count 0 2006.173.18:46:44.50#ibcon#enter sib2, iclass 17, count 0 2006.173.18:46:44.50#ibcon#flushed, iclass 17, count 0 2006.173.18:46:44.50#ibcon#about to write, iclass 17, count 0 2006.173.18:46:44.50#ibcon#wrote, iclass 17, count 0 2006.173.18:46:44.50#ibcon#about to read 3, iclass 17, count 0 2006.173.18:46:44.52#ibcon#read 3, iclass 17, count 0 2006.173.18:46:44.52#ibcon#about to read 4, iclass 17, count 0 2006.173.18:46:44.52#ibcon#read 4, iclass 17, count 0 2006.173.18:46:44.52#ibcon#about to read 5, iclass 17, count 0 2006.173.18:46:44.52#ibcon#read 5, iclass 17, count 0 2006.173.18:46:44.52#ibcon#about to read 6, iclass 17, count 0 2006.173.18:46:44.52#ibcon#read 6, iclass 17, count 0 2006.173.18:46:44.52#ibcon#end of sib2, iclass 17, count 0 2006.173.18:46:44.52#ibcon#*mode == 0, iclass 17, count 0 2006.173.18:46:44.52#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.18:46:44.52#ibcon#[27=USB\r\n] 2006.173.18:46:44.52#ibcon#*before write, iclass 17, count 0 2006.173.18:46:44.52#ibcon#enter sib2, iclass 17, count 0 2006.173.18:46:44.52#ibcon#flushed, iclass 17, count 0 2006.173.18:46:44.52#ibcon#about to write, iclass 17, count 0 2006.173.18:46:44.52#ibcon#wrote, iclass 17, count 0 2006.173.18:46:44.52#ibcon#about to read 3, iclass 17, count 0 2006.173.18:46:44.55#ibcon#read 3, iclass 17, count 0 2006.173.18:46:44.55#ibcon#about to read 4, iclass 17, count 0 2006.173.18:46:44.55#ibcon#read 4, iclass 17, count 0 2006.173.18:46:44.55#ibcon#about to read 5, iclass 17, count 0 2006.173.18:46:44.55#ibcon#read 5, iclass 17, count 0 2006.173.18:46:44.55#ibcon#about to read 6, iclass 17, count 0 2006.173.18:46:44.55#ibcon#read 6, iclass 17, count 0 2006.173.18:46:44.55#ibcon#end of sib2, iclass 17, count 0 2006.173.18:46:44.55#ibcon#*after write, iclass 17, count 0 2006.173.18:46:44.55#ibcon#*before return 0, iclass 17, count 0 2006.173.18:46:44.55#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.18:46:44.55#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.18:46:44.55#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.18:46:44.55#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.18:46:44.55$vck44/vabw=wide 2006.173.18:46:44.55#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.18:46:44.55#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.18:46:44.55#ibcon#ireg 8 cls_cnt 0 2006.173.18:46:44.55#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.18:46:44.55#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.18:46:44.55#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.18:46:44.55#ibcon#enter wrdev, iclass 19, count 0 2006.173.18:46:44.55#ibcon#first serial, iclass 19, count 0 2006.173.18:46:44.55#ibcon#enter sib2, iclass 19, count 0 2006.173.18:46:44.55#ibcon#flushed, iclass 19, count 0 2006.173.18:46:44.55#ibcon#about to write, iclass 19, count 0 2006.173.18:46:44.55#ibcon#wrote, iclass 19, count 0 2006.173.18:46:44.55#ibcon#about to read 3, iclass 19, count 0 2006.173.18:46:44.57#ibcon#read 3, iclass 19, count 0 2006.173.18:46:44.57#ibcon#about to read 4, iclass 19, count 0 2006.173.18:46:44.57#ibcon#read 4, iclass 19, count 0 2006.173.18:46:44.57#ibcon#about to read 5, iclass 19, count 0 2006.173.18:46:44.57#ibcon#read 5, iclass 19, count 0 2006.173.18:46:44.57#ibcon#about to read 6, iclass 19, count 0 2006.173.18:46:44.57#ibcon#read 6, iclass 19, count 0 2006.173.18:46:44.57#ibcon#end of sib2, iclass 19, count 0 2006.173.18:46:44.57#ibcon#*mode == 0, iclass 19, count 0 2006.173.18:46:44.57#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.18:46:44.57#ibcon#[25=BW32\r\n] 2006.173.18:46:44.57#ibcon#*before write, iclass 19, count 0 2006.173.18:46:44.57#ibcon#enter sib2, iclass 19, count 0 2006.173.18:46:44.57#ibcon#flushed, iclass 19, count 0 2006.173.18:46:44.57#ibcon#about to write, iclass 19, count 0 2006.173.18:46:44.57#ibcon#wrote, iclass 19, count 0 2006.173.18:46:44.57#ibcon#about to read 3, iclass 19, count 0 2006.173.18:46:44.60#ibcon#read 3, iclass 19, count 0 2006.173.18:46:44.60#ibcon#about to read 4, iclass 19, count 0 2006.173.18:46:44.60#ibcon#read 4, iclass 19, count 0 2006.173.18:46:44.60#ibcon#about to read 5, iclass 19, count 0 2006.173.18:46:44.60#ibcon#read 5, iclass 19, count 0 2006.173.18:46:44.60#ibcon#about to read 6, iclass 19, count 0 2006.173.18:46:44.60#ibcon#read 6, iclass 19, count 0 2006.173.18:46:44.60#ibcon#end of sib2, iclass 19, count 0 2006.173.18:46:44.60#ibcon#*after write, iclass 19, count 0 2006.173.18:46:44.60#ibcon#*before return 0, iclass 19, count 0 2006.173.18:46:44.60#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.18:46:44.60#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.18:46:44.60#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.18:46:44.60#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.18:46:44.60$vck44/vbbw=wide 2006.173.18:46:44.60#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.18:46:44.60#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.18:46:44.60#ibcon#ireg 8 cls_cnt 0 2006.173.18:46:44.60#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.18:46:44.67#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.18:46:44.67#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.18:46:44.67#ibcon#enter wrdev, iclass 21, count 0 2006.173.18:46:44.67#ibcon#first serial, iclass 21, count 0 2006.173.18:46:44.67#ibcon#enter sib2, iclass 21, count 0 2006.173.18:46:44.67#ibcon#flushed, iclass 21, count 0 2006.173.18:46:44.67#ibcon#about to write, iclass 21, count 0 2006.173.18:46:44.67#ibcon#wrote, iclass 21, count 0 2006.173.18:46:44.67#ibcon#about to read 3, iclass 21, count 0 2006.173.18:46:44.69#ibcon#read 3, iclass 21, count 0 2006.173.18:46:44.69#ibcon#about to read 4, iclass 21, count 0 2006.173.18:46:44.69#ibcon#read 4, iclass 21, count 0 2006.173.18:46:44.69#ibcon#about to read 5, iclass 21, count 0 2006.173.18:46:44.69#ibcon#read 5, iclass 21, count 0 2006.173.18:46:44.69#ibcon#about to read 6, iclass 21, count 0 2006.173.18:46:44.69#ibcon#read 6, iclass 21, count 0 2006.173.18:46:44.69#ibcon#end of sib2, iclass 21, count 0 2006.173.18:46:44.69#ibcon#*mode == 0, iclass 21, count 0 2006.173.18:46:44.69#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.18:46:44.69#ibcon#[27=BW32\r\n] 2006.173.18:46:44.69#ibcon#*before write, iclass 21, count 0 2006.173.18:46:44.69#ibcon#enter sib2, iclass 21, count 0 2006.173.18:46:44.69#ibcon#flushed, iclass 21, count 0 2006.173.18:46:44.69#ibcon#about to write, iclass 21, count 0 2006.173.18:46:44.69#ibcon#wrote, iclass 21, count 0 2006.173.18:46:44.69#ibcon#about to read 3, iclass 21, count 0 2006.173.18:46:44.72#ibcon#read 3, iclass 21, count 0 2006.173.18:46:44.72#ibcon#about to read 4, iclass 21, count 0 2006.173.18:46:44.72#ibcon#read 4, iclass 21, count 0 2006.173.18:46:44.72#ibcon#about to read 5, iclass 21, count 0 2006.173.18:46:44.72#ibcon#read 5, iclass 21, count 0 2006.173.18:46:44.72#ibcon#about to read 6, iclass 21, count 0 2006.173.18:46:44.72#ibcon#read 6, iclass 21, count 0 2006.173.18:46:44.72#ibcon#end of sib2, iclass 21, count 0 2006.173.18:46:44.72#ibcon#*after write, iclass 21, count 0 2006.173.18:46:44.72#ibcon#*before return 0, iclass 21, count 0 2006.173.18:46:44.72#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.18:46:44.72#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.18:46:44.72#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.18:46:44.72#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.18:46:44.72$setupk4/ifdk4 2006.173.18:46:44.72$ifdk4/lo= 2006.173.18:46:44.72$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.18:46:44.72$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.18:46:44.72$ifdk4/patch= 2006.173.18:46:44.72$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.18:46:44.72$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.18:46:44.72$setupk4/!*+20s 2006.173.18:46:54.16#abcon#<5=/14 0.9 1.5 19.691001002.3\r\n> 2006.173.18:46:54.18#abcon#{5=INTERFACE CLEAR} 2006.173.18:46:54.24#abcon#[5=S1D000X0/0*\r\n] 2006.173.18:46:59.23$setupk4/"tpicd 2006.173.18:46:59.23$setupk4/echo=off 2006.173.18:46:59.23$setupk4/xlog=off 2006.173.18:46:59.23:!2006.173.18:47:18 2006.173.18:47:01.13#trakl#Source acquired 2006.173.18:47:02.13#flagr#flagr/antenna,acquired 2006.173.18:47:18.00:preob 2006.173.18:47:18.13/onsource/TRACKING 2006.173.18:47:18.13:!2006.173.18:47:28 2006.173.18:47:28.00:"tape 2006.173.18:47:28.00:"st=record 2006.173.18:47:28.00:data_valid=on 2006.173.18:47:28.00:midob 2006.173.18:47:29.13/onsource/TRACKING 2006.173.18:47:29.13/wx/19.68,1002.3,100 2006.173.18:47:29.33/cable/+6.5148E-03 2006.173.18:47:30.42/va/01,07,usb,yes,45,49 2006.173.18:47:30.42/va/02,06,usb,yes,45,46 2006.173.18:47:30.42/va/03,05,usb,yes,57,60 2006.173.18:47:30.42/va/04,06,usb,yes,46,49 2006.173.18:47:30.42/va/05,04,usb,yes,37,37 2006.173.18:47:30.42/va/06,03,usb,yes,51,51 2006.173.18:47:30.42/va/07,04,usb,yes,41,43 2006.173.18:47:30.42/va/08,04,usb,yes,36,42 2006.173.18:47:30.65/valo/01,524.99,yes,locked 2006.173.18:47:30.65/valo/02,534.99,yes,locked 2006.173.18:47:30.65/valo/03,564.99,yes,locked 2006.173.18:47:30.65/valo/04,624.99,yes,locked 2006.173.18:47:30.65/valo/05,734.99,yes,locked 2006.173.18:47:30.65/valo/06,814.99,yes,locked 2006.173.18:47:30.65/valo/07,864.99,yes,locked 2006.173.18:47:30.65/valo/08,884.99,yes,locked 2006.173.18:47:31.74/vb/01,04,usb,yes,34,31 2006.173.18:47:31.74/vb/02,04,usb,yes,37,36 2006.173.18:47:31.74/vb/03,04,usb,yes,33,37 2006.173.18:47:31.74/vb/04,04,usb,yes,38,37 2006.173.18:47:31.74/vb/05,04,usb,yes,30,33 2006.173.18:47:31.74/vb/06,04,usb,yes,35,31 2006.173.18:47:31.74/vb/07,04,usb,yes,35,35 2006.173.18:47:31.74/vb/08,04,usb,yes,32,36 2006.173.18:47:31.98/vblo/01,629.99,yes,locked 2006.173.18:47:31.98/vblo/02,634.99,yes,locked 2006.173.18:47:31.98/vblo/03,649.99,yes,locked 2006.173.18:47:31.98/vblo/04,679.99,yes,locked 2006.173.18:47:31.98/vblo/05,709.99,yes,locked 2006.173.18:47:31.98/vblo/06,719.99,yes,locked 2006.173.18:47:31.98/vblo/07,734.99,yes,locked 2006.173.18:47:31.98/vblo/08,744.99,yes,locked 2006.173.18:47:32.13/vabw/8 2006.173.18:47:32.28/vbbw/8 2006.173.18:47:32.37/xfe/off,on,14.7 2006.173.18:47:32.74/ifatt/23,28,28,28 2006.173.18:47:33.07/fmout-gps/S +3.92E-07 2006.173.18:47:33.11:!2006.173.18:49:18 2006.173.18:49:18.01:data_valid=off 2006.173.18:49:18.02:"et 2006.173.18:49:18.02:!+3s 2006.173.18:49:21.03:"tape 2006.173.18:49:21.03:postob 2006.173.18:49:21.12/cable/+6.5139E-03 2006.173.18:49:21.13/wx/19.67,1002.4,100 2006.173.18:49:21.18/fmout-gps/S +3.92E-07 2006.173.18:49:21.19:scan_name=173-1849,jd0606,350 2006.173.18:49:21.19:source=nrao150,035929.75,505750.2,2000.0,ccw 2006.173.18:49:22.14#flagr#flagr/antenna,new-source 2006.173.18:49:22.15:checkk5 2006.173.18:49:22.57/chk_autoobs//k5ts1/ autoobs is running! 2006.173.18:49:22.96/chk_autoobs//k5ts2/ autoobs is running! 2006.173.18:49:23.35/chk_autoobs//k5ts3/ autoobs is running! 2006.173.18:49:23.75/chk_autoobs//k5ts4/ autoobs is running! 2006.173.18:49:24.13/chk_obsdata//k5ts1/T1731847??a.dat file size is correct (nominal:440MB, actual:436MB). 2006.173.18:49:24.53/chk_obsdata//k5ts2/T1731847??b.dat file size is correct (nominal:440MB, actual:436MB). 2006.173.18:49:24.92/chk_obsdata//k5ts3/T1731847??c.dat file size is correct (nominal:440MB, actual:436MB). 2006.173.18:49:25.33/chk_obsdata//k5ts4/T1731847??d.dat file size is correct (nominal:440MB, actual:436MB). 2006.173.18:49:26.05/k5log//k5ts1_log_newline 2006.173.18:49:26.77/k5log//k5ts2_log_newline 2006.173.18:49:27.48/k5log//k5ts3_log_newline 2006.173.18:49:28.18/k5log//k5ts4_log_newline 2006.173.18:49:28.21/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.18:49:28.21:setupk4=1 2006.173.18:49:28.21$setupk4/echo=on 2006.173.18:49:28.21$setupk4/pcalon 2006.173.18:49:28.21$pcalon/"no phase cal control is implemented here 2006.173.18:49:28.21$setupk4/"tpicd=stop 2006.173.18:49:28.21$setupk4/"rec=synch_on 2006.173.18:49:28.21$setupk4/"rec_mode=128 2006.173.18:49:28.21$setupk4/!* 2006.173.18:49:28.21$setupk4/recpk4 2006.173.18:49:28.21$recpk4/recpatch= 2006.173.18:49:28.21$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.18:49:28.21$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.18:49:28.21$setupk4/vck44 2006.173.18:49:28.21$vck44/valo=1,524.99 2006.173.18:49:28.21#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.18:49:28.21#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.18:49:28.21#ibcon#ireg 17 cls_cnt 0 2006.173.18:49:28.21#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.18:49:28.21#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.18:49:28.21#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.18:49:28.21#ibcon#enter wrdev, iclass 18, count 0 2006.173.18:49:28.21#ibcon#first serial, iclass 18, count 0 2006.173.18:49:28.21#ibcon#enter sib2, iclass 18, count 0 2006.173.18:49:28.21#ibcon#flushed, iclass 18, count 0 2006.173.18:49:28.21#ibcon#about to write, iclass 18, count 0 2006.173.18:49:28.21#ibcon#wrote, iclass 18, count 0 2006.173.18:49:28.21#ibcon#about to read 3, iclass 18, count 0 2006.173.18:49:28.22#ibcon#read 3, iclass 18, count 0 2006.173.18:49:28.22#ibcon#about to read 4, iclass 18, count 0 2006.173.18:49:28.22#ibcon#read 4, iclass 18, count 0 2006.173.18:49:28.22#ibcon#about to read 5, iclass 18, count 0 2006.173.18:49:28.22#ibcon#read 5, iclass 18, count 0 2006.173.18:49:28.22#ibcon#about to read 6, iclass 18, count 0 2006.173.18:49:28.22#ibcon#read 6, iclass 18, count 0 2006.173.18:49:28.22#ibcon#end of sib2, iclass 18, count 0 2006.173.18:49:28.22#ibcon#*mode == 0, iclass 18, count 0 2006.173.18:49:28.22#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.18:49:28.22#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.18:49:28.22#ibcon#*before write, iclass 18, count 0 2006.173.18:49:28.22#ibcon#enter sib2, iclass 18, count 0 2006.173.18:49:28.22#ibcon#flushed, iclass 18, count 0 2006.173.18:49:28.22#ibcon#about to write, iclass 18, count 0 2006.173.18:49:28.22#ibcon#wrote, iclass 18, count 0 2006.173.18:49:28.22#ibcon#about to read 3, iclass 18, count 0 2006.173.18:49:28.27#ibcon#read 3, iclass 18, count 0 2006.173.18:49:28.27#ibcon#about to read 4, iclass 18, count 0 2006.173.18:49:28.27#ibcon#read 4, iclass 18, count 0 2006.173.18:49:28.27#ibcon#about to read 5, iclass 18, count 0 2006.173.18:49:28.27#ibcon#read 5, iclass 18, count 0 2006.173.18:49:28.27#ibcon#about to read 6, iclass 18, count 0 2006.173.18:49:28.27#ibcon#read 6, iclass 18, count 0 2006.173.18:49:28.27#ibcon#end of sib2, iclass 18, count 0 2006.173.18:49:28.27#ibcon#*after write, iclass 18, count 0 2006.173.18:49:28.27#ibcon#*before return 0, iclass 18, count 0 2006.173.18:49:28.27#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.18:49:28.27#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.18:49:28.27#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.18:49:28.27#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.18:49:28.27$vck44/va=1,7 2006.173.18:49:28.27#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.18:49:28.27#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.18:49:28.27#ibcon#ireg 11 cls_cnt 2 2006.173.18:49:28.27#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.18:49:28.27#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.18:49:28.27#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.18:49:28.27#ibcon#enter wrdev, iclass 20, count 2 2006.173.18:49:28.27#ibcon#first serial, iclass 20, count 2 2006.173.18:49:28.27#ibcon#enter sib2, iclass 20, count 2 2006.173.18:49:28.27#ibcon#flushed, iclass 20, count 2 2006.173.18:49:28.27#ibcon#about to write, iclass 20, count 2 2006.173.18:49:28.27#ibcon#wrote, iclass 20, count 2 2006.173.18:49:28.27#ibcon#about to read 3, iclass 20, count 2 2006.173.18:49:28.29#ibcon#read 3, iclass 20, count 2 2006.173.18:49:28.29#ibcon#about to read 4, iclass 20, count 2 2006.173.18:49:28.29#ibcon#read 4, iclass 20, count 2 2006.173.18:49:28.29#ibcon#about to read 5, iclass 20, count 2 2006.173.18:49:28.29#ibcon#read 5, iclass 20, count 2 2006.173.18:49:28.29#ibcon#about to read 6, iclass 20, count 2 2006.173.18:49:28.29#ibcon#read 6, iclass 20, count 2 2006.173.18:49:28.29#ibcon#end of sib2, iclass 20, count 2 2006.173.18:49:28.29#ibcon#*mode == 0, iclass 20, count 2 2006.173.18:49:28.29#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.18:49:28.29#ibcon#[25=AT01-07\r\n] 2006.173.18:49:28.29#ibcon#*before write, iclass 20, count 2 2006.173.18:49:28.29#ibcon#enter sib2, iclass 20, count 2 2006.173.18:49:28.29#ibcon#flushed, iclass 20, count 2 2006.173.18:49:28.29#ibcon#about to write, iclass 20, count 2 2006.173.18:49:28.29#ibcon#wrote, iclass 20, count 2 2006.173.18:49:28.29#ibcon#about to read 3, iclass 20, count 2 2006.173.18:49:28.32#ibcon#read 3, iclass 20, count 2 2006.173.18:49:28.32#ibcon#about to read 4, iclass 20, count 2 2006.173.18:49:28.32#ibcon#read 4, iclass 20, count 2 2006.173.18:49:28.32#ibcon#about to read 5, iclass 20, count 2 2006.173.18:49:28.32#ibcon#read 5, iclass 20, count 2 2006.173.18:49:28.32#ibcon#about to read 6, iclass 20, count 2 2006.173.18:49:28.32#ibcon#read 6, iclass 20, count 2 2006.173.18:49:28.32#ibcon#end of sib2, iclass 20, count 2 2006.173.18:49:28.32#ibcon#*after write, iclass 20, count 2 2006.173.18:49:28.32#ibcon#*before return 0, iclass 20, count 2 2006.173.18:49:28.32#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.18:49:28.32#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.18:49:28.32#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.18:49:28.32#ibcon#ireg 7 cls_cnt 0 2006.173.18:49:28.32#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.18:49:28.44#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.18:49:28.44#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.18:49:28.44#ibcon#enter wrdev, iclass 20, count 0 2006.173.18:49:28.44#ibcon#first serial, iclass 20, count 0 2006.173.18:49:28.44#ibcon#enter sib2, iclass 20, count 0 2006.173.18:49:28.44#ibcon#flushed, iclass 20, count 0 2006.173.18:49:28.44#ibcon#about to write, iclass 20, count 0 2006.173.18:49:28.44#ibcon#wrote, iclass 20, count 0 2006.173.18:49:28.44#ibcon#about to read 3, iclass 20, count 0 2006.173.18:49:28.46#ibcon#read 3, iclass 20, count 0 2006.173.18:49:28.46#ibcon#about to read 4, iclass 20, count 0 2006.173.18:49:28.46#ibcon#read 4, iclass 20, count 0 2006.173.18:49:28.46#ibcon#about to read 5, iclass 20, count 0 2006.173.18:49:28.46#ibcon#read 5, iclass 20, count 0 2006.173.18:49:28.46#ibcon#about to read 6, iclass 20, count 0 2006.173.18:49:28.46#ibcon#read 6, iclass 20, count 0 2006.173.18:49:28.46#ibcon#end of sib2, iclass 20, count 0 2006.173.18:49:28.46#ibcon#*mode == 0, iclass 20, count 0 2006.173.18:49:28.46#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.18:49:28.46#ibcon#[25=USB\r\n] 2006.173.18:49:28.46#ibcon#*before write, iclass 20, count 0 2006.173.18:49:28.46#ibcon#enter sib2, iclass 20, count 0 2006.173.18:49:28.46#ibcon#flushed, iclass 20, count 0 2006.173.18:49:28.46#ibcon#about to write, iclass 20, count 0 2006.173.18:49:28.46#ibcon#wrote, iclass 20, count 0 2006.173.18:49:28.46#ibcon#about to read 3, iclass 20, count 0 2006.173.18:49:28.49#ibcon#read 3, iclass 20, count 0 2006.173.18:49:28.49#ibcon#about to read 4, iclass 20, count 0 2006.173.18:49:28.49#ibcon#read 4, iclass 20, count 0 2006.173.18:49:28.49#ibcon#about to read 5, iclass 20, count 0 2006.173.18:49:28.49#ibcon#read 5, iclass 20, count 0 2006.173.18:49:28.49#ibcon#about to read 6, iclass 20, count 0 2006.173.18:49:28.49#ibcon#read 6, iclass 20, count 0 2006.173.18:49:28.49#ibcon#end of sib2, iclass 20, count 0 2006.173.18:49:28.49#ibcon#*after write, iclass 20, count 0 2006.173.18:49:28.49#ibcon#*before return 0, iclass 20, count 0 2006.173.18:49:28.49#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.18:49:28.49#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.18:49:28.49#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.18:49:28.49#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.18:49:28.49$vck44/valo=2,534.99 2006.173.18:49:28.49#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.18:49:28.49#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.18:49:28.49#ibcon#ireg 17 cls_cnt 0 2006.173.18:49:28.49#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.18:49:28.49#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.18:49:28.49#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.18:49:28.49#ibcon#enter wrdev, iclass 22, count 0 2006.173.18:49:28.49#ibcon#first serial, iclass 22, count 0 2006.173.18:49:28.49#ibcon#enter sib2, iclass 22, count 0 2006.173.18:49:28.49#ibcon#flushed, iclass 22, count 0 2006.173.18:49:28.49#ibcon#about to write, iclass 22, count 0 2006.173.18:49:28.49#ibcon#wrote, iclass 22, count 0 2006.173.18:49:28.49#ibcon#about to read 3, iclass 22, count 0 2006.173.18:49:28.51#ibcon#read 3, iclass 22, count 0 2006.173.18:49:28.51#ibcon#about to read 4, iclass 22, count 0 2006.173.18:49:28.51#ibcon#read 4, iclass 22, count 0 2006.173.18:49:28.51#ibcon#about to read 5, iclass 22, count 0 2006.173.18:49:28.51#ibcon#read 5, iclass 22, count 0 2006.173.18:49:28.51#ibcon#about to read 6, iclass 22, count 0 2006.173.18:49:28.51#ibcon#read 6, iclass 22, count 0 2006.173.18:49:28.51#ibcon#end of sib2, iclass 22, count 0 2006.173.18:49:28.51#ibcon#*mode == 0, iclass 22, count 0 2006.173.18:49:28.51#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.18:49:28.51#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.18:49:28.51#ibcon#*before write, iclass 22, count 0 2006.173.18:49:28.51#ibcon#enter sib2, iclass 22, count 0 2006.173.18:49:28.51#ibcon#flushed, iclass 22, count 0 2006.173.18:49:28.51#ibcon#about to write, iclass 22, count 0 2006.173.18:49:28.51#ibcon#wrote, iclass 22, count 0 2006.173.18:49:28.51#ibcon#about to read 3, iclass 22, count 0 2006.173.18:49:28.55#ibcon#read 3, iclass 22, count 0 2006.173.18:49:28.55#ibcon#about to read 4, iclass 22, count 0 2006.173.18:49:28.55#ibcon#read 4, iclass 22, count 0 2006.173.18:49:28.55#ibcon#about to read 5, iclass 22, count 0 2006.173.18:49:28.55#ibcon#read 5, iclass 22, count 0 2006.173.18:49:28.55#ibcon#about to read 6, iclass 22, count 0 2006.173.18:49:28.55#ibcon#read 6, iclass 22, count 0 2006.173.18:49:28.55#ibcon#end of sib2, iclass 22, count 0 2006.173.18:49:28.55#ibcon#*after write, iclass 22, count 0 2006.173.18:49:28.55#ibcon#*before return 0, iclass 22, count 0 2006.173.18:49:28.55#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.18:49:28.55#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.18:49:28.55#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.18:49:28.55#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.18:49:28.55$vck44/va=2,6 2006.173.18:49:28.55#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.18:49:28.55#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.18:49:28.55#ibcon#ireg 11 cls_cnt 2 2006.173.18:49:28.55#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.18:49:28.61#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.18:49:28.61#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.18:49:28.61#ibcon#enter wrdev, iclass 24, count 2 2006.173.18:49:28.61#ibcon#first serial, iclass 24, count 2 2006.173.18:49:28.61#ibcon#enter sib2, iclass 24, count 2 2006.173.18:49:28.61#ibcon#flushed, iclass 24, count 2 2006.173.18:49:28.61#ibcon#about to write, iclass 24, count 2 2006.173.18:49:28.61#ibcon#wrote, iclass 24, count 2 2006.173.18:49:28.61#ibcon#about to read 3, iclass 24, count 2 2006.173.18:49:28.63#ibcon#read 3, iclass 24, count 2 2006.173.18:49:28.63#ibcon#about to read 4, iclass 24, count 2 2006.173.18:49:28.63#ibcon#read 4, iclass 24, count 2 2006.173.18:49:28.63#ibcon#about to read 5, iclass 24, count 2 2006.173.18:49:28.63#ibcon#read 5, iclass 24, count 2 2006.173.18:49:28.63#ibcon#about to read 6, iclass 24, count 2 2006.173.18:49:28.63#ibcon#read 6, iclass 24, count 2 2006.173.18:49:28.63#ibcon#end of sib2, iclass 24, count 2 2006.173.18:49:28.63#ibcon#*mode == 0, iclass 24, count 2 2006.173.18:49:28.63#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.18:49:28.63#ibcon#[25=AT02-06\r\n] 2006.173.18:49:28.63#ibcon#*before write, iclass 24, count 2 2006.173.18:49:28.63#ibcon#enter sib2, iclass 24, count 2 2006.173.18:49:28.63#ibcon#flushed, iclass 24, count 2 2006.173.18:49:28.63#ibcon#about to write, iclass 24, count 2 2006.173.18:49:28.63#ibcon#wrote, iclass 24, count 2 2006.173.18:49:28.63#ibcon#about to read 3, iclass 24, count 2 2006.173.18:49:28.66#ibcon#read 3, iclass 24, count 2 2006.173.18:49:28.66#ibcon#about to read 4, iclass 24, count 2 2006.173.18:49:28.66#ibcon#read 4, iclass 24, count 2 2006.173.18:49:28.66#ibcon#about to read 5, iclass 24, count 2 2006.173.18:49:28.66#ibcon#read 5, iclass 24, count 2 2006.173.18:49:28.66#ibcon#about to read 6, iclass 24, count 2 2006.173.18:49:28.66#ibcon#read 6, iclass 24, count 2 2006.173.18:49:28.66#ibcon#end of sib2, iclass 24, count 2 2006.173.18:49:28.66#ibcon#*after write, iclass 24, count 2 2006.173.18:49:28.66#ibcon#*before return 0, iclass 24, count 2 2006.173.18:49:28.66#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.18:49:28.66#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.18:49:28.66#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.18:49:28.66#ibcon#ireg 7 cls_cnt 0 2006.173.18:49:28.66#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.18:49:28.78#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.18:49:28.78#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.18:49:28.78#ibcon#enter wrdev, iclass 24, count 0 2006.173.18:49:28.78#ibcon#first serial, iclass 24, count 0 2006.173.18:49:28.78#ibcon#enter sib2, iclass 24, count 0 2006.173.18:49:28.78#ibcon#flushed, iclass 24, count 0 2006.173.18:49:28.78#ibcon#about to write, iclass 24, count 0 2006.173.18:49:28.78#ibcon#wrote, iclass 24, count 0 2006.173.18:49:28.78#ibcon#about to read 3, iclass 24, count 0 2006.173.18:49:28.80#ibcon#read 3, iclass 24, count 0 2006.173.18:49:28.80#ibcon#about to read 4, iclass 24, count 0 2006.173.18:49:28.80#ibcon#read 4, iclass 24, count 0 2006.173.18:49:28.80#ibcon#about to read 5, iclass 24, count 0 2006.173.18:49:28.80#ibcon#read 5, iclass 24, count 0 2006.173.18:49:28.80#ibcon#about to read 6, iclass 24, count 0 2006.173.18:49:28.80#ibcon#read 6, iclass 24, count 0 2006.173.18:49:28.80#ibcon#end of sib2, iclass 24, count 0 2006.173.18:49:28.80#ibcon#*mode == 0, iclass 24, count 0 2006.173.18:49:28.80#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.18:49:28.80#ibcon#[25=USB\r\n] 2006.173.18:49:28.80#ibcon#*before write, iclass 24, count 0 2006.173.18:49:28.80#ibcon#enter sib2, iclass 24, count 0 2006.173.18:49:28.80#ibcon#flushed, iclass 24, count 0 2006.173.18:49:28.80#ibcon#about to write, iclass 24, count 0 2006.173.18:49:28.80#ibcon#wrote, iclass 24, count 0 2006.173.18:49:28.80#ibcon#about to read 3, iclass 24, count 0 2006.173.18:49:28.83#ibcon#read 3, iclass 24, count 0 2006.173.18:49:28.83#ibcon#about to read 4, iclass 24, count 0 2006.173.18:49:28.83#ibcon#read 4, iclass 24, count 0 2006.173.18:49:28.83#ibcon#about to read 5, iclass 24, count 0 2006.173.18:49:28.83#ibcon#read 5, iclass 24, count 0 2006.173.18:49:28.83#ibcon#about to read 6, iclass 24, count 0 2006.173.18:49:28.83#ibcon#read 6, iclass 24, count 0 2006.173.18:49:28.83#ibcon#end of sib2, iclass 24, count 0 2006.173.18:49:28.83#ibcon#*after write, iclass 24, count 0 2006.173.18:49:28.83#ibcon#*before return 0, iclass 24, count 0 2006.173.18:49:28.83#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.18:49:28.83#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.18:49:28.83#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.18:49:28.83#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.18:49:28.83$vck44/valo=3,564.99 2006.173.18:49:28.83#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.18:49:28.83#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.18:49:28.83#ibcon#ireg 17 cls_cnt 0 2006.173.18:49:28.83#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.18:49:28.83#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.18:49:28.83#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.18:49:28.83#ibcon#enter wrdev, iclass 26, count 0 2006.173.18:49:28.83#ibcon#first serial, iclass 26, count 0 2006.173.18:49:28.83#ibcon#enter sib2, iclass 26, count 0 2006.173.18:49:28.83#ibcon#flushed, iclass 26, count 0 2006.173.18:49:28.83#ibcon#about to write, iclass 26, count 0 2006.173.18:49:28.83#ibcon#wrote, iclass 26, count 0 2006.173.18:49:28.83#ibcon#about to read 3, iclass 26, count 0 2006.173.18:49:28.85#ibcon#read 3, iclass 26, count 0 2006.173.18:49:28.85#ibcon#about to read 4, iclass 26, count 0 2006.173.18:49:28.85#ibcon#read 4, iclass 26, count 0 2006.173.18:49:28.85#ibcon#about to read 5, iclass 26, count 0 2006.173.18:49:28.85#ibcon#read 5, iclass 26, count 0 2006.173.18:49:28.85#ibcon#about to read 6, iclass 26, count 0 2006.173.18:49:28.85#ibcon#read 6, iclass 26, count 0 2006.173.18:49:28.85#ibcon#end of sib2, iclass 26, count 0 2006.173.18:49:28.85#ibcon#*mode == 0, iclass 26, count 0 2006.173.18:49:28.85#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.18:49:28.85#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.18:49:28.85#ibcon#*before write, iclass 26, count 0 2006.173.18:49:28.85#ibcon#enter sib2, iclass 26, count 0 2006.173.18:49:28.85#ibcon#flushed, iclass 26, count 0 2006.173.18:49:28.85#ibcon#about to write, iclass 26, count 0 2006.173.18:49:28.85#ibcon#wrote, iclass 26, count 0 2006.173.18:49:28.85#ibcon#about to read 3, iclass 26, count 0 2006.173.18:49:28.89#ibcon#read 3, iclass 26, count 0 2006.173.18:49:28.89#ibcon#about to read 4, iclass 26, count 0 2006.173.18:49:28.89#ibcon#read 4, iclass 26, count 0 2006.173.18:49:28.89#ibcon#about to read 5, iclass 26, count 0 2006.173.18:49:28.89#ibcon#read 5, iclass 26, count 0 2006.173.18:49:28.89#ibcon#about to read 6, iclass 26, count 0 2006.173.18:49:28.89#ibcon#read 6, iclass 26, count 0 2006.173.18:49:28.89#ibcon#end of sib2, iclass 26, count 0 2006.173.18:49:28.89#ibcon#*after write, iclass 26, count 0 2006.173.18:49:28.89#ibcon#*before return 0, iclass 26, count 0 2006.173.18:49:28.89#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.18:49:28.89#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.18:49:28.89#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.18:49:28.89#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.18:49:28.89$vck44/va=3,5 2006.173.18:49:28.89#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.18:49:28.89#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.18:49:28.89#ibcon#ireg 11 cls_cnt 2 2006.173.18:49:28.89#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.18:49:28.95#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.18:49:28.95#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.18:49:28.95#ibcon#enter wrdev, iclass 28, count 2 2006.173.18:49:28.95#ibcon#first serial, iclass 28, count 2 2006.173.18:49:28.95#ibcon#enter sib2, iclass 28, count 2 2006.173.18:49:28.95#ibcon#flushed, iclass 28, count 2 2006.173.18:49:28.95#ibcon#about to write, iclass 28, count 2 2006.173.18:49:28.95#ibcon#wrote, iclass 28, count 2 2006.173.18:49:28.95#ibcon#about to read 3, iclass 28, count 2 2006.173.18:49:28.97#ibcon#read 3, iclass 28, count 2 2006.173.18:49:28.97#ibcon#about to read 4, iclass 28, count 2 2006.173.18:49:28.97#ibcon#read 4, iclass 28, count 2 2006.173.18:49:28.97#ibcon#about to read 5, iclass 28, count 2 2006.173.18:49:28.97#ibcon#read 5, iclass 28, count 2 2006.173.18:49:28.97#ibcon#about to read 6, iclass 28, count 2 2006.173.18:49:28.97#ibcon#read 6, iclass 28, count 2 2006.173.18:49:28.97#ibcon#end of sib2, iclass 28, count 2 2006.173.18:49:28.97#ibcon#*mode == 0, iclass 28, count 2 2006.173.18:49:28.97#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.18:49:28.97#ibcon#[25=AT03-05\r\n] 2006.173.18:49:28.97#ibcon#*before write, iclass 28, count 2 2006.173.18:49:28.97#ibcon#enter sib2, iclass 28, count 2 2006.173.18:49:28.97#ibcon#flushed, iclass 28, count 2 2006.173.18:49:28.97#ibcon#about to write, iclass 28, count 2 2006.173.18:49:28.97#ibcon#wrote, iclass 28, count 2 2006.173.18:49:28.97#ibcon#about to read 3, iclass 28, count 2 2006.173.18:49:29.00#ibcon#read 3, iclass 28, count 2 2006.173.18:49:29.00#ibcon#about to read 4, iclass 28, count 2 2006.173.18:49:29.00#ibcon#read 4, iclass 28, count 2 2006.173.18:49:29.00#ibcon#about to read 5, iclass 28, count 2 2006.173.18:49:29.00#ibcon#read 5, iclass 28, count 2 2006.173.18:49:29.00#ibcon#about to read 6, iclass 28, count 2 2006.173.18:49:29.00#ibcon#read 6, iclass 28, count 2 2006.173.18:49:29.00#ibcon#end of sib2, iclass 28, count 2 2006.173.18:49:29.00#ibcon#*after write, iclass 28, count 2 2006.173.18:49:29.00#ibcon#*before return 0, iclass 28, count 2 2006.173.18:49:29.00#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.18:49:29.00#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.18:49:29.00#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.18:49:29.00#ibcon#ireg 7 cls_cnt 0 2006.173.18:49:29.00#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.18:49:29.12#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.18:49:29.12#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.18:49:29.12#ibcon#enter wrdev, iclass 28, count 0 2006.173.18:49:29.12#ibcon#first serial, iclass 28, count 0 2006.173.18:49:29.12#ibcon#enter sib2, iclass 28, count 0 2006.173.18:49:29.12#ibcon#flushed, iclass 28, count 0 2006.173.18:49:29.12#ibcon#about to write, iclass 28, count 0 2006.173.18:49:29.12#ibcon#wrote, iclass 28, count 0 2006.173.18:49:29.12#ibcon#about to read 3, iclass 28, count 0 2006.173.18:49:29.14#ibcon#read 3, iclass 28, count 0 2006.173.18:49:29.14#ibcon#about to read 4, iclass 28, count 0 2006.173.18:49:29.14#ibcon#read 4, iclass 28, count 0 2006.173.18:49:29.14#ibcon#about to read 5, iclass 28, count 0 2006.173.18:49:29.14#ibcon#read 5, iclass 28, count 0 2006.173.18:49:29.14#ibcon#about to read 6, iclass 28, count 0 2006.173.18:49:29.14#ibcon#read 6, iclass 28, count 0 2006.173.18:49:29.14#ibcon#end of sib2, iclass 28, count 0 2006.173.18:49:29.14#ibcon#*mode == 0, iclass 28, count 0 2006.173.18:49:29.14#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.18:49:29.14#ibcon#[25=USB\r\n] 2006.173.18:49:29.14#ibcon#*before write, iclass 28, count 0 2006.173.18:49:29.14#ibcon#enter sib2, iclass 28, count 0 2006.173.18:49:29.14#ibcon#flushed, iclass 28, count 0 2006.173.18:49:29.14#ibcon#about to write, iclass 28, count 0 2006.173.18:49:29.14#ibcon#wrote, iclass 28, count 0 2006.173.18:49:29.14#ibcon#about to read 3, iclass 28, count 0 2006.173.18:49:29.17#ibcon#read 3, iclass 28, count 0 2006.173.18:49:29.17#ibcon#about to read 4, iclass 28, count 0 2006.173.18:49:29.17#ibcon#read 4, iclass 28, count 0 2006.173.18:49:29.17#ibcon#about to read 5, iclass 28, count 0 2006.173.18:49:29.17#ibcon#read 5, iclass 28, count 0 2006.173.18:49:29.17#ibcon#about to read 6, iclass 28, count 0 2006.173.18:49:29.17#ibcon#read 6, iclass 28, count 0 2006.173.18:49:29.17#ibcon#end of sib2, iclass 28, count 0 2006.173.18:49:29.17#ibcon#*after write, iclass 28, count 0 2006.173.18:49:29.17#ibcon#*before return 0, iclass 28, count 0 2006.173.18:49:29.17#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.18:49:29.17#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.18:49:29.17#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.18:49:29.17#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.18:49:29.17$vck44/valo=4,624.99 2006.173.18:49:29.17#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.18:49:29.17#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.18:49:29.17#ibcon#ireg 17 cls_cnt 0 2006.173.18:49:29.17#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.18:49:29.17#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.18:49:29.17#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.18:49:29.17#ibcon#enter wrdev, iclass 30, count 0 2006.173.18:49:29.17#ibcon#first serial, iclass 30, count 0 2006.173.18:49:29.17#ibcon#enter sib2, iclass 30, count 0 2006.173.18:49:29.17#ibcon#flushed, iclass 30, count 0 2006.173.18:49:29.17#ibcon#about to write, iclass 30, count 0 2006.173.18:49:29.17#ibcon#wrote, iclass 30, count 0 2006.173.18:49:29.17#ibcon#about to read 3, iclass 30, count 0 2006.173.18:49:29.19#ibcon#read 3, iclass 30, count 0 2006.173.18:49:29.19#ibcon#about to read 4, iclass 30, count 0 2006.173.18:49:29.19#ibcon#read 4, iclass 30, count 0 2006.173.18:49:29.19#ibcon#about to read 5, iclass 30, count 0 2006.173.18:49:29.19#ibcon#read 5, iclass 30, count 0 2006.173.18:49:29.19#ibcon#about to read 6, iclass 30, count 0 2006.173.18:49:29.19#ibcon#read 6, iclass 30, count 0 2006.173.18:49:29.19#ibcon#end of sib2, iclass 30, count 0 2006.173.18:49:29.19#ibcon#*mode == 0, iclass 30, count 0 2006.173.18:49:29.19#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.18:49:29.19#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.18:49:29.19#ibcon#*before write, iclass 30, count 0 2006.173.18:49:29.19#ibcon#enter sib2, iclass 30, count 0 2006.173.18:49:29.19#ibcon#flushed, iclass 30, count 0 2006.173.18:49:29.19#ibcon#about to write, iclass 30, count 0 2006.173.18:49:29.19#ibcon#wrote, iclass 30, count 0 2006.173.18:49:29.19#ibcon#about to read 3, iclass 30, count 0 2006.173.18:49:29.23#ibcon#read 3, iclass 30, count 0 2006.173.18:49:29.23#ibcon#about to read 4, iclass 30, count 0 2006.173.18:49:29.23#ibcon#read 4, iclass 30, count 0 2006.173.18:49:29.23#ibcon#about to read 5, iclass 30, count 0 2006.173.18:49:29.23#ibcon#read 5, iclass 30, count 0 2006.173.18:49:29.23#ibcon#about to read 6, iclass 30, count 0 2006.173.18:49:29.23#ibcon#read 6, iclass 30, count 0 2006.173.18:49:29.23#ibcon#end of sib2, iclass 30, count 0 2006.173.18:49:29.23#ibcon#*after write, iclass 30, count 0 2006.173.18:49:29.23#ibcon#*before return 0, iclass 30, count 0 2006.173.18:49:29.23#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.18:49:29.23#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.18:49:29.23#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.18:49:29.23#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.18:49:29.23$vck44/va=4,6 2006.173.18:49:29.23#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.173.18:49:29.23#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.173.18:49:29.23#ibcon#ireg 11 cls_cnt 2 2006.173.18:49:29.23#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.18:49:29.29#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.18:49:29.29#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.18:49:29.29#ibcon#enter wrdev, iclass 32, count 2 2006.173.18:49:29.29#ibcon#first serial, iclass 32, count 2 2006.173.18:49:29.29#ibcon#enter sib2, iclass 32, count 2 2006.173.18:49:29.29#ibcon#flushed, iclass 32, count 2 2006.173.18:49:29.29#ibcon#about to write, iclass 32, count 2 2006.173.18:49:29.29#ibcon#wrote, iclass 32, count 2 2006.173.18:49:29.29#ibcon#about to read 3, iclass 32, count 2 2006.173.18:49:29.31#ibcon#read 3, iclass 32, count 2 2006.173.18:49:29.31#ibcon#about to read 4, iclass 32, count 2 2006.173.18:49:29.31#ibcon#read 4, iclass 32, count 2 2006.173.18:49:29.31#ibcon#about to read 5, iclass 32, count 2 2006.173.18:49:29.31#ibcon#read 5, iclass 32, count 2 2006.173.18:49:29.31#ibcon#about to read 6, iclass 32, count 2 2006.173.18:49:29.31#ibcon#read 6, iclass 32, count 2 2006.173.18:49:29.31#ibcon#end of sib2, iclass 32, count 2 2006.173.18:49:29.31#ibcon#*mode == 0, iclass 32, count 2 2006.173.18:49:29.31#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.173.18:49:29.31#ibcon#[25=AT04-06\r\n] 2006.173.18:49:29.31#ibcon#*before write, iclass 32, count 2 2006.173.18:49:29.31#ibcon#enter sib2, iclass 32, count 2 2006.173.18:49:29.31#ibcon#flushed, iclass 32, count 2 2006.173.18:49:29.31#ibcon#about to write, iclass 32, count 2 2006.173.18:49:29.31#ibcon#wrote, iclass 32, count 2 2006.173.18:49:29.31#ibcon#about to read 3, iclass 32, count 2 2006.173.18:49:29.34#ibcon#read 3, iclass 32, count 2 2006.173.18:49:29.34#ibcon#about to read 4, iclass 32, count 2 2006.173.18:49:29.34#ibcon#read 4, iclass 32, count 2 2006.173.18:49:29.34#ibcon#about to read 5, iclass 32, count 2 2006.173.18:49:29.34#ibcon#read 5, iclass 32, count 2 2006.173.18:49:29.34#ibcon#about to read 6, iclass 32, count 2 2006.173.18:49:29.34#ibcon#read 6, iclass 32, count 2 2006.173.18:49:29.34#ibcon#end of sib2, iclass 32, count 2 2006.173.18:49:29.34#ibcon#*after write, iclass 32, count 2 2006.173.18:49:29.34#ibcon#*before return 0, iclass 32, count 2 2006.173.18:49:29.34#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.18:49:29.34#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.173.18:49:29.34#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.173.18:49:29.34#ibcon#ireg 7 cls_cnt 0 2006.173.18:49:29.34#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.18:49:29.46#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.18:49:29.46#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.18:49:29.46#ibcon#enter wrdev, iclass 32, count 0 2006.173.18:49:29.46#ibcon#first serial, iclass 32, count 0 2006.173.18:49:29.46#ibcon#enter sib2, iclass 32, count 0 2006.173.18:49:29.46#ibcon#flushed, iclass 32, count 0 2006.173.18:49:29.46#ibcon#about to write, iclass 32, count 0 2006.173.18:49:29.46#ibcon#wrote, iclass 32, count 0 2006.173.18:49:29.46#ibcon#about to read 3, iclass 32, count 0 2006.173.18:49:29.48#ibcon#read 3, iclass 32, count 0 2006.173.18:49:29.48#ibcon#about to read 4, iclass 32, count 0 2006.173.18:49:29.48#ibcon#read 4, iclass 32, count 0 2006.173.18:49:29.48#ibcon#about to read 5, iclass 32, count 0 2006.173.18:49:29.48#ibcon#read 5, iclass 32, count 0 2006.173.18:49:29.48#ibcon#about to read 6, iclass 32, count 0 2006.173.18:49:29.48#ibcon#read 6, iclass 32, count 0 2006.173.18:49:29.48#ibcon#end of sib2, iclass 32, count 0 2006.173.18:49:29.48#ibcon#*mode == 0, iclass 32, count 0 2006.173.18:49:29.48#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.18:49:29.48#ibcon#[25=USB\r\n] 2006.173.18:49:29.48#ibcon#*before write, iclass 32, count 0 2006.173.18:49:29.48#ibcon#enter sib2, iclass 32, count 0 2006.173.18:49:29.48#ibcon#flushed, iclass 32, count 0 2006.173.18:49:29.48#ibcon#about to write, iclass 32, count 0 2006.173.18:49:29.48#ibcon#wrote, iclass 32, count 0 2006.173.18:49:29.48#ibcon#about to read 3, iclass 32, count 0 2006.173.18:49:29.51#ibcon#read 3, iclass 32, count 0 2006.173.18:49:29.51#ibcon#about to read 4, iclass 32, count 0 2006.173.18:49:29.51#ibcon#read 4, iclass 32, count 0 2006.173.18:49:29.51#ibcon#about to read 5, iclass 32, count 0 2006.173.18:49:29.51#ibcon#read 5, iclass 32, count 0 2006.173.18:49:29.51#ibcon#about to read 6, iclass 32, count 0 2006.173.18:49:29.51#ibcon#read 6, iclass 32, count 0 2006.173.18:49:29.51#ibcon#end of sib2, iclass 32, count 0 2006.173.18:49:29.51#ibcon#*after write, iclass 32, count 0 2006.173.18:49:29.51#ibcon#*before return 0, iclass 32, count 0 2006.173.18:49:29.51#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.18:49:29.51#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.173.18:49:29.51#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.18:49:29.51#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.18:49:29.51$vck44/valo=5,734.99 2006.173.18:49:29.51#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.18:49:29.51#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.18:49:29.51#ibcon#ireg 17 cls_cnt 0 2006.173.18:49:29.51#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.18:49:29.51#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.18:49:29.51#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.18:49:29.51#ibcon#enter wrdev, iclass 34, count 0 2006.173.18:49:29.51#ibcon#first serial, iclass 34, count 0 2006.173.18:49:29.51#ibcon#enter sib2, iclass 34, count 0 2006.173.18:49:29.51#ibcon#flushed, iclass 34, count 0 2006.173.18:49:29.51#ibcon#about to write, iclass 34, count 0 2006.173.18:49:29.51#ibcon#wrote, iclass 34, count 0 2006.173.18:49:29.51#ibcon#about to read 3, iclass 34, count 0 2006.173.18:49:29.53#ibcon#read 3, iclass 34, count 0 2006.173.18:49:29.53#ibcon#about to read 4, iclass 34, count 0 2006.173.18:49:29.53#ibcon#read 4, iclass 34, count 0 2006.173.18:49:29.53#ibcon#about to read 5, iclass 34, count 0 2006.173.18:49:29.53#ibcon#read 5, iclass 34, count 0 2006.173.18:49:29.53#ibcon#about to read 6, iclass 34, count 0 2006.173.18:49:29.53#ibcon#read 6, iclass 34, count 0 2006.173.18:49:29.53#ibcon#end of sib2, iclass 34, count 0 2006.173.18:49:29.53#ibcon#*mode == 0, iclass 34, count 0 2006.173.18:49:29.53#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.18:49:29.53#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.18:49:29.53#ibcon#*before write, iclass 34, count 0 2006.173.18:49:29.53#ibcon#enter sib2, iclass 34, count 0 2006.173.18:49:29.53#ibcon#flushed, iclass 34, count 0 2006.173.18:49:29.53#ibcon#about to write, iclass 34, count 0 2006.173.18:49:29.53#ibcon#wrote, iclass 34, count 0 2006.173.18:49:29.53#ibcon#about to read 3, iclass 34, count 0 2006.173.18:49:29.57#ibcon#read 3, iclass 34, count 0 2006.173.18:49:29.57#ibcon#about to read 4, iclass 34, count 0 2006.173.18:49:29.57#ibcon#read 4, iclass 34, count 0 2006.173.18:49:29.57#ibcon#about to read 5, iclass 34, count 0 2006.173.18:49:29.57#ibcon#read 5, iclass 34, count 0 2006.173.18:49:29.57#ibcon#about to read 6, iclass 34, count 0 2006.173.18:49:29.57#ibcon#read 6, iclass 34, count 0 2006.173.18:49:29.57#ibcon#end of sib2, iclass 34, count 0 2006.173.18:49:29.57#ibcon#*after write, iclass 34, count 0 2006.173.18:49:29.57#ibcon#*before return 0, iclass 34, count 0 2006.173.18:49:29.57#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.18:49:29.57#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.18:49:29.57#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.18:49:29.57#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.18:49:29.57$vck44/va=5,4 2006.173.18:49:29.57#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.18:49:29.57#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.18:49:29.57#ibcon#ireg 11 cls_cnt 2 2006.173.18:49:29.57#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.18:49:29.63#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.18:49:29.63#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.18:49:29.63#ibcon#enter wrdev, iclass 36, count 2 2006.173.18:49:29.63#ibcon#first serial, iclass 36, count 2 2006.173.18:49:29.63#ibcon#enter sib2, iclass 36, count 2 2006.173.18:49:29.63#ibcon#flushed, iclass 36, count 2 2006.173.18:49:29.63#ibcon#about to write, iclass 36, count 2 2006.173.18:49:29.63#ibcon#wrote, iclass 36, count 2 2006.173.18:49:29.63#ibcon#about to read 3, iclass 36, count 2 2006.173.18:49:29.65#ibcon#read 3, iclass 36, count 2 2006.173.18:49:29.65#ibcon#about to read 4, iclass 36, count 2 2006.173.18:49:29.65#ibcon#read 4, iclass 36, count 2 2006.173.18:49:29.65#ibcon#about to read 5, iclass 36, count 2 2006.173.18:49:29.65#ibcon#read 5, iclass 36, count 2 2006.173.18:49:29.65#ibcon#about to read 6, iclass 36, count 2 2006.173.18:49:29.65#ibcon#read 6, iclass 36, count 2 2006.173.18:49:29.65#ibcon#end of sib2, iclass 36, count 2 2006.173.18:49:29.65#ibcon#*mode == 0, iclass 36, count 2 2006.173.18:49:29.65#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.18:49:29.65#ibcon#[25=AT05-04\r\n] 2006.173.18:49:29.65#ibcon#*before write, iclass 36, count 2 2006.173.18:49:29.65#ibcon#enter sib2, iclass 36, count 2 2006.173.18:49:29.65#ibcon#flushed, iclass 36, count 2 2006.173.18:49:29.65#ibcon#about to write, iclass 36, count 2 2006.173.18:49:29.65#ibcon#wrote, iclass 36, count 2 2006.173.18:49:29.65#ibcon#about to read 3, iclass 36, count 2 2006.173.18:49:29.68#ibcon#read 3, iclass 36, count 2 2006.173.18:49:29.68#ibcon#about to read 4, iclass 36, count 2 2006.173.18:49:29.68#ibcon#read 4, iclass 36, count 2 2006.173.18:49:29.68#ibcon#about to read 5, iclass 36, count 2 2006.173.18:49:29.68#ibcon#read 5, iclass 36, count 2 2006.173.18:49:29.68#ibcon#about to read 6, iclass 36, count 2 2006.173.18:49:29.68#ibcon#read 6, iclass 36, count 2 2006.173.18:49:29.68#ibcon#end of sib2, iclass 36, count 2 2006.173.18:49:29.68#ibcon#*after write, iclass 36, count 2 2006.173.18:49:29.68#ibcon#*before return 0, iclass 36, count 2 2006.173.18:49:29.68#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.18:49:29.68#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.18:49:29.68#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.18:49:29.68#ibcon#ireg 7 cls_cnt 0 2006.173.18:49:29.68#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.18:49:29.80#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.18:49:29.80#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.18:49:29.80#ibcon#enter wrdev, iclass 36, count 0 2006.173.18:49:29.80#ibcon#first serial, iclass 36, count 0 2006.173.18:49:29.80#ibcon#enter sib2, iclass 36, count 0 2006.173.18:49:29.80#ibcon#flushed, iclass 36, count 0 2006.173.18:49:29.80#ibcon#about to write, iclass 36, count 0 2006.173.18:49:29.80#ibcon#wrote, iclass 36, count 0 2006.173.18:49:29.80#ibcon#about to read 3, iclass 36, count 0 2006.173.18:49:29.82#ibcon#read 3, iclass 36, count 0 2006.173.18:49:29.82#ibcon#about to read 4, iclass 36, count 0 2006.173.18:49:29.82#ibcon#read 4, iclass 36, count 0 2006.173.18:49:29.82#ibcon#about to read 5, iclass 36, count 0 2006.173.18:49:29.82#ibcon#read 5, iclass 36, count 0 2006.173.18:49:29.82#ibcon#about to read 6, iclass 36, count 0 2006.173.18:49:29.82#ibcon#read 6, iclass 36, count 0 2006.173.18:49:29.82#ibcon#end of sib2, iclass 36, count 0 2006.173.18:49:29.82#ibcon#*mode == 0, iclass 36, count 0 2006.173.18:49:29.82#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.18:49:29.82#ibcon#[25=USB\r\n] 2006.173.18:49:29.82#ibcon#*before write, iclass 36, count 0 2006.173.18:49:29.82#ibcon#enter sib2, iclass 36, count 0 2006.173.18:49:29.82#ibcon#flushed, iclass 36, count 0 2006.173.18:49:29.82#ibcon#about to write, iclass 36, count 0 2006.173.18:49:29.82#ibcon#wrote, iclass 36, count 0 2006.173.18:49:29.82#ibcon#about to read 3, iclass 36, count 0 2006.173.18:49:29.85#ibcon#read 3, iclass 36, count 0 2006.173.18:49:29.85#ibcon#about to read 4, iclass 36, count 0 2006.173.18:49:29.85#ibcon#read 4, iclass 36, count 0 2006.173.18:49:29.85#ibcon#about to read 5, iclass 36, count 0 2006.173.18:49:29.85#ibcon#read 5, iclass 36, count 0 2006.173.18:49:29.85#ibcon#about to read 6, iclass 36, count 0 2006.173.18:49:29.85#ibcon#read 6, iclass 36, count 0 2006.173.18:49:29.85#ibcon#end of sib2, iclass 36, count 0 2006.173.18:49:29.85#ibcon#*after write, iclass 36, count 0 2006.173.18:49:29.85#ibcon#*before return 0, iclass 36, count 0 2006.173.18:49:29.85#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.18:49:29.85#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.18:49:29.85#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.18:49:29.85#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.18:49:29.85$vck44/valo=6,814.99 2006.173.18:49:29.85#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.18:49:29.85#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.18:49:29.85#ibcon#ireg 17 cls_cnt 0 2006.173.18:49:29.85#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.18:49:29.85#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.18:49:29.85#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.18:49:29.85#ibcon#enter wrdev, iclass 38, count 0 2006.173.18:49:29.85#ibcon#first serial, iclass 38, count 0 2006.173.18:49:29.85#ibcon#enter sib2, iclass 38, count 0 2006.173.18:49:29.85#ibcon#flushed, iclass 38, count 0 2006.173.18:49:29.85#ibcon#about to write, iclass 38, count 0 2006.173.18:49:29.85#ibcon#wrote, iclass 38, count 0 2006.173.18:49:29.85#ibcon#about to read 3, iclass 38, count 0 2006.173.18:49:29.87#ibcon#read 3, iclass 38, count 0 2006.173.18:49:29.87#ibcon#about to read 4, iclass 38, count 0 2006.173.18:49:29.87#ibcon#read 4, iclass 38, count 0 2006.173.18:49:29.87#ibcon#about to read 5, iclass 38, count 0 2006.173.18:49:29.87#ibcon#read 5, iclass 38, count 0 2006.173.18:49:29.87#ibcon#about to read 6, iclass 38, count 0 2006.173.18:49:29.87#ibcon#read 6, iclass 38, count 0 2006.173.18:49:29.87#ibcon#end of sib2, iclass 38, count 0 2006.173.18:49:29.87#ibcon#*mode == 0, iclass 38, count 0 2006.173.18:49:29.87#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.18:49:29.87#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.18:49:29.87#ibcon#*before write, iclass 38, count 0 2006.173.18:49:29.87#ibcon#enter sib2, iclass 38, count 0 2006.173.18:49:29.87#ibcon#flushed, iclass 38, count 0 2006.173.18:49:29.87#ibcon#about to write, iclass 38, count 0 2006.173.18:49:29.87#ibcon#wrote, iclass 38, count 0 2006.173.18:49:29.87#ibcon#about to read 3, iclass 38, count 0 2006.173.18:49:29.91#ibcon#read 3, iclass 38, count 0 2006.173.18:49:29.91#ibcon#about to read 4, iclass 38, count 0 2006.173.18:49:29.91#ibcon#read 4, iclass 38, count 0 2006.173.18:49:29.91#ibcon#about to read 5, iclass 38, count 0 2006.173.18:49:29.91#ibcon#read 5, iclass 38, count 0 2006.173.18:49:29.91#ibcon#about to read 6, iclass 38, count 0 2006.173.18:49:29.91#ibcon#read 6, iclass 38, count 0 2006.173.18:49:29.91#ibcon#end of sib2, iclass 38, count 0 2006.173.18:49:29.91#ibcon#*after write, iclass 38, count 0 2006.173.18:49:29.91#ibcon#*before return 0, iclass 38, count 0 2006.173.18:49:29.91#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.18:49:29.91#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.18:49:29.91#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.18:49:29.91#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.18:49:29.91$vck44/va=6,3 2006.173.18:49:29.91#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.18:49:29.91#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.18:49:29.91#ibcon#ireg 11 cls_cnt 2 2006.173.18:49:29.91#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.18:49:29.97#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.18:49:29.97#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.18:49:29.97#ibcon#enter wrdev, iclass 40, count 2 2006.173.18:49:29.97#ibcon#first serial, iclass 40, count 2 2006.173.18:49:29.97#ibcon#enter sib2, iclass 40, count 2 2006.173.18:49:29.97#ibcon#flushed, iclass 40, count 2 2006.173.18:49:29.97#ibcon#about to write, iclass 40, count 2 2006.173.18:49:29.97#ibcon#wrote, iclass 40, count 2 2006.173.18:49:29.97#ibcon#about to read 3, iclass 40, count 2 2006.173.18:49:29.99#ibcon#read 3, iclass 40, count 2 2006.173.18:49:29.99#ibcon#about to read 4, iclass 40, count 2 2006.173.18:49:29.99#ibcon#read 4, iclass 40, count 2 2006.173.18:49:29.99#ibcon#about to read 5, iclass 40, count 2 2006.173.18:49:29.99#ibcon#read 5, iclass 40, count 2 2006.173.18:49:29.99#ibcon#about to read 6, iclass 40, count 2 2006.173.18:49:29.99#ibcon#read 6, iclass 40, count 2 2006.173.18:49:29.99#ibcon#end of sib2, iclass 40, count 2 2006.173.18:49:29.99#ibcon#*mode == 0, iclass 40, count 2 2006.173.18:49:29.99#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.18:49:29.99#ibcon#[25=AT06-03\r\n] 2006.173.18:49:29.99#ibcon#*before write, iclass 40, count 2 2006.173.18:49:29.99#ibcon#enter sib2, iclass 40, count 2 2006.173.18:49:29.99#ibcon#flushed, iclass 40, count 2 2006.173.18:49:29.99#ibcon#about to write, iclass 40, count 2 2006.173.18:49:29.99#ibcon#wrote, iclass 40, count 2 2006.173.18:49:29.99#ibcon#about to read 3, iclass 40, count 2 2006.173.18:49:30.02#ibcon#read 3, iclass 40, count 2 2006.173.18:49:30.02#ibcon#about to read 4, iclass 40, count 2 2006.173.18:49:30.02#ibcon#read 4, iclass 40, count 2 2006.173.18:49:30.02#ibcon#about to read 5, iclass 40, count 2 2006.173.18:49:30.02#ibcon#read 5, iclass 40, count 2 2006.173.18:49:30.02#ibcon#about to read 6, iclass 40, count 2 2006.173.18:49:30.02#ibcon#read 6, iclass 40, count 2 2006.173.18:49:30.02#ibcon#end of sib2, iclass 40, count 2 2006.173.18:49:30.02#ibcon#*after write, iclass 40, count 2 2006.173.18:49:30.02#ibcon#*before return 0, iclass 40, count 2 2006.173.18:49:30.02#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.18:49:30.02#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.18:49:30.02#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.18:49:30.02#ibcon#ireg 7 cls_cnt 0 2006.173.18:49:30.02#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.18:49:30.14#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.18:49:30.14#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.18:49:30.14#ibcon#enter wrdev, iclass 40, count 0 2006.173.18:49:30.14#ibcon#first serial, iclass 40, count 0 2006.173.18:49:30.14#ibcon#enter sib2, iclass 40, count 0 2006.173.18:49:30.14#ibcon#flushed, iclass 40, count 0 2006.173.18:49:30.14#ibcon#about to write, iclass 40, count 0 2006.173.18:49:30.14#ibcon#wrote, iclass 40, count 0 2006.173.18:49:30.14#ibcon#about to read 3, iclass 40, count 0 2006.173.18:49:30.16#ibcon#read 3, iclass 40, count 0 2006.173.18:49:30.16#ibcon#about to read 4, iclass 40, count 0 2006.173.18:49:30.16#ibcon#read 4, iclass 40, count 0 2006.173.18:49:30.16#ibcon#about to read 5, iclass 40, count 0 2006.173.18:49:30.16#ibcon#read 5, iclass 40, count 0 2006.173.18:49:30.16#ibcon#about to read 6, iclass 40, count 0 2006.173.18:49:30.16#ibcon#read 6, iclass 40, count 0 2006.173.18:49:30.16#ibcon#end of sib2, iclass 40, count 0 2006.173.18:49:30.16#ibcon#*mode == 0, iclass 40, count 0 2006.173.18:49:30.16#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.18:49:30.16#ibcon#[25=USB\r\n] 2006.173.18:49:30.16#ibcon#*before write, iclass 40, count 0 2006.173.18:49:30.16#ibcon#enter sib2, iclass 40, count 0 2006.173.18:49:30.16#ibcon#flushed, iclass 40, count 0 2006.173.18:49:30.16#ibcon#about to write, iclass 40, count 0 2006.173.18:49:30.16#ibcon#wrote, iclass 40, count 0 2006.173.18:49:30.16#ibcon#about to read 3, iclass 40, count 0 2006.173.18:49:30.19#ibcon#read 3, iclass 40, count 0 2006.173.18:49:30.19#ibcon#about to read 4, iclass 40, count 0 2006.173.18:49:30.19#ibcon#read 4, iclass 40, count 0 2006.173.18:49:30.19#ibcon#about to read 5, iclass 40, count 0 2006.173.18:49:30.19#ibcon#read 5, iclass 40, count 0 2006.173.18:49:30.19#ibcon#about to read 6, iclass 40, count 0 2006.173.18:49:30.19#ibcon#read 6, iclass 40, count 0 2006.173.18:49:30.19#ibcon#end of sib2, iclass 40, count 0 2006.173.18:49:30.19#ibcon#*after write, iclass 40, count 0 2006.173.18:49:30.19#ibcon#*before return 0, iclass 40, count 0 2006.173.18:49:30.19#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.18:49:30.19#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.18:49:30.19#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.18:49:30.19#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.18:49:30.19$vck44/valo=7,864.99 2006.173.18:49:30.19#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.18:49:30.19#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.18:49:30.19#ibcon#ireg 17 cls_cnt 0 2006.173.18:49:30.19#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.18:49:30.19#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.18:49:30.19#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.18:49:30.19#ibcon#enter wrdev, iclass 4, count 0 2006.173.18:49:30.19#ibcon#first serial, iclass 4, count 0 2006.173.18:49:30.19#ibcon#enter sib2, iclass 4, count 0 2006.173.18:49:30.19#ibcon#flushed, iclass 4, count 0 2006.173.18:49:30.19#ibcon#about to write, iclass 4, count 0 2006.173.18:49:30.19#ibcon#wrote, iclass 4, count 0 2006.173.18:49:30.19#ibcon#about to read 3, iclass 4, count 0 2006.173.18:49:30.21#ibcon#read 3, iclass 4, count 0 2006.173.18:49:30.21#ibcon#about to read 4, iclass 4, count 0 2006.173.18:49:30.21#ibcon#read 4, iclass 4, count 0 2006.173.18:49:30.21#ibcon#about to read 5, iclass 4, count 0 2006.173.18:49:30.21#ibcon#read 5, iclass 4, count 0 2006.173.18:49:30.21#ibcon#about to read 6, iclass 4, count 0 2006.173.18:49:30.21#ibcon#read 6, iclass 4, count 0 2006.173.18:49:30.21#ibcon#end of sib2, iclass 4, count 0 2006.173.18:49:30.21#ibcon#*mode == 0, iclass 4, count 0 2006.173.18:49:30.21#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.18:49:30.21#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.18:49:30.21#ibcon#*before write, iclass 4, count 0 2006.173.18:49:30.21#ibcon#enter sib2, iclass 4, count 0 2006.173.18:49:30.21#ibcon#flushed, iclass 4, count 0 2006.173.18:49:30.21#ibcon#about to write, iclass 4, count 0 2006.173.18:49:30.21#ibcon#wrote, iclass 4, count 0 2006.173.18:49:30.21#ibcon#about to read 3, iclass 4, count 0 2006.173.18:49:30.25#ibcon#read 3, iclass 4, count 0 2006.173.18:49:30.25#ibcon#about to read 4, iclass 4, count 0 2006.173.18:49:30.25#ibcon#read 4, iclass 4, count 0 2006.173.18:49:30.25#ibcon#about to read 5, iclass 4, count 0 2006.173.18:49:30.25#ibcon#read 5, iclass 4, count 0 2006.173.18:49:30.25#ibcon#about to read 6, iclass 4, count 0 2006.173.18:49:30.25#ibcon#read 6, iclass 4, count 0 2006.173.18:49:30.25#ibcon#end of sib2, iclass 4, count 0 2006.173.18:49:30.25#ibcon#*after write, iclass 4, count 0 2006.173.18:49:30.25#ibcon#*before return 0, iclass 4, count 0 2006.173.18:49:30.25#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.18:49:30.25#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.18:49:30.25#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.18:49:30.25#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.18:49:30.25$vck44/va=7,4 2006.173.18:49:30.25#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.18:49:30.25#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.18:49:30.25#ibcon#ireg 11 cls_cnt 2 2006.173.18:49:30.25#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.18:49:30.31#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.18:49:30.31#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.18:49:30.31#ibcon#enter wrdev, iclass 6, count 2 2006.173.18:49:30.31#ibcon#first serial, iclass 6, count 2 2006.173.18:49:30.31#ibcon#enter sib2, iclass 6, count 2 2006.173.18:49:30.31#ibcon#flushed, iclass 6, count 2 2006.173.18:49:30.31#ibcon#about to write, iclass 6, count 2 2006.173.18:49:30.31#ibcon#wrote, iclass 6, count 2 2006.173.18:49:30.31#ibcon#about to read 3, iclass 6, count 2 2006.173.18:49:30.33#ibcon#read 3, iclass 6, count 2 2006.173.18:49:30.33#ibcon#about to read 4, iclass 6, count 2 2006.173.18:49:30.33#ibcon#read 4, iclass 6, count 2 2006.173.18:49:30.33#ibcon#about to read 5, iclass 6, count 2 2006.173.18:49:30.33#ibcon#read 5, iclass 6, count 2 2006.173.18:49:30.33#ibcon#about to read 6, iclass 6, count 2 2006.173.18:49:30.33#ibcon#read 6, iclass 6, count 2 2006.173.18:49:30.33#ibcon#end of sib2, iclass 6, count 2 2006.173.18:49:30.33#ibcon#*mode == 0, iclass 6, count 2 2006.173.18:49:30.33#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.18:49:30.33#ibcon#[25=AT07-04\r\n] 2006.173.18:49:30.33#ibcon#*before write, iclass 6, count 2 2006.173.18:49:30.33#ibcon#enter sib2, iclass 6, count 2 2006.173.18:49:30.33#ibcon#flushed, iclass 6, count 2 2006.173.18:49:30.33#ibcon#about to write, iclass 6, count 2 2006.173.18:49:30.33#ibcon#wrote, iclass 6, count 2 2006.173.18:49:30.33#ibcon#about to read 3, iclass 6, count 2 2006.173.18:49:30.36#ibcon#read 3, iclass 6, count 2 2006.173.18:49:30.36#ibcon#about to read 4, iclass 6, count 2 2006.173.18:49:30.36#ibcon#read 4, iclass 6, count 2 2006.173.18:49:30.36#ibcon#about to read 5, iclass 6, count 2 2006.173.18:49:30.36#ibcon#read 5, iclass 6, count 2 2006.173.18:49:30.36#ibcon#about to read 6, iclass 6, count 2 2006.173.18:49:30.36#ibcon#read 6, iclass 6, count 2 2006.173.18:49:30.36#ibcon#end of sib2, iclass 6, count 2 2006.173.18:49:30.36#ibcon#*after write, iclass 6, count 2 2006.173.18:49:30.36#ibcon#*before return 0, iclass 6, count 2 2006.173.18:49:30.36#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.18:49:30.36#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.18:49:30.36#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.18:49:30.36#ibcon#ireg 7 cls_cnt 0 2006.173.18:49:30.36#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.18:49:30.48#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.18:49:30.48#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.18:49:30.48#ibcon#enter wrdev, iclass 6, count 0 2006.173.18:49:30.48#ibcon#first serial, iclass 6, count 0 2006.173.18:49:30.48#ibcon#enter sib2, iclass 6, count 0 2006.173.18:49:30.48#ibcon#flushed, iclass 6, count 0 2006.173.18:49:30.48#ibcon#about to write, iclass 6, count 0 2006.173.18:49:30.48#ibcon#wrote, iclass 6, count 0 2006.173.18:49:30.48#ibcon#about to read 3, iclass 6, count 0 2006.173.18:49:30.50#ibcon#read 3, iclass 6, count 0 2006.173.18:49:30.50#ibcon#about to read 4, iclass 6, count 0 2006.173.18:49:30.50#ibcon#read 4, iclass 6, count 0 2006.173.18:49:30.50#ibcon#about to read 5, iclass 6, count 0 2006.173.18:49:30.50#ibcon#read 5, iclass 6, count 0 2006.173.18:49:30.50#ibcon#about to read 6, iclass 6, count 0 2006.173.18:49:30.50#ibcon#read 6, iclass 6, count 0 2006.173.18:49:30.50#ibcon#end of sib2, iclass 6, count 0 2006.173.18:49:30.50#ibcon#*mode == 0, iclass 6, count 0 2006.173.18:49:30.50#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.18:49:30.50#ibcon#[25=USB\r\n] 2006.173.18:49:30.50#ibcon#*before write, iclass 6, count 0 2006.173.18:49:30.50#ibcon#enter sib2, iclass 6, count 0 2006.173.18:49:30.50#ibcon#flushed, iclass 6, count 0 2006.173.18:49:30.50#ibcon#about to write, iclass 6, count 0 2006.173.18:49:30.50#ibcon#wrote, iclass 6, count 0 2006.173.18:49:30.50#ibcon#about to read 3, iclass 6, count 0 2006.173.18:49:30.53#ibcon#read 3, iclass 6, count 0 2006.173.18:49:30.53#ibcon#about to read 4, iclass 6, count 0 2006.173.18:49:30.53#ibcon#read 4, iclass 6, count 0 2006.173.18:49:30.53#ibcon#about to read 5, iclass 6, count 0 2006.173.18:49:30.53#ibcon#read 5, iclass 6, count 0 2006.173.18:49:30.53#ibcon#about to read 6, iclass 6, count 0 2006.173.18:49:30.53#ibcon#read 6, iclass 6, count 0 2006.173.18:49:30.53#ibcon#end of sib2, iclass 6, count 0 2006.173.18:49:30.53#ibcon#*after write, iclass 6, count 0 2006.173.18:49:30.53#ibcon#*before return 0, iclass 6, count 0 2006.173.18:49:30.53#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.18:49:30.53#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.18:49:30.53#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.18:49:30.53#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.18:49:30.53$vck44/valo=8,884.99 2006.173.18:49:30.53#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.18:49:30.53#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.18:49:30.53#ibcon#ireg 17 cls_cnt 0 2006.173.18:49:30.53#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.18:49:30.53#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.18:49:30.53#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.18:49:30.53#ibcon#enter wrdev, iclass 10, count 0 2006.173.18:49:30.53#ibcon#first serial, iclass 10, count 0 2006.173.18:49:30.53#ibcon#enter sib2, iclass 10, count 0 2006.173.18:49:30.53#ibcon#flushed, iclass 10, count 0 2006.173.18:49:30.53#ibcon#about to write, iclass 10, count 0 2006.173.18:49:30.53#ibcon#wrote, iclass 10, count 0 2006.173.18:49:30.53#ibcon#about to read 3, iclass 10, count 0 2006.173.18:49:30.55#ibcon#read 3, iclass 10, count 0 2006.173.18:49:30.55#ibcon#about to read 4, iclass 10, count 0 2006.173.18:49:30.55#ibcon#read 4, iclass 10, count 0 2006.173.18:49:30.55#ibcon#about to read 5, iclass 10, count 0 2006.173.18:49:30.55#ibcon#read 5, iclass 10, count 0 2006.173.18:49:30.55#ibcon#about to read 6, iclass 10, count 0 2006.173.18:49:30.55#ibcon#read 6, iclass 10, count 0 2006.173.18:49:30.55#ibcon#end of sib2, iclass 10, count 0 2006.173.18:49:30.55#ibcon#*mode == 0, iclass 10, count 0 2006.173.18:49:30.55#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.18:49:30.55#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.18:49:30.55#ibcon#*before write, iclass 10, count 0 2006.173.18:49:30.55#ibcon#enter sib2, iclass 10, count 0 2006.173.18:49:30.55#ibcon#flushed, iclass 10, count 0 2006.173.18:49:30.55#ibcon#about to write, iclass 10, count 0 2006.173.18:49:30.55#ibcon#wrote, iclass 10, count 0 2006.173.18:49:30.55#ibcon#about to read 3, iclass 10, count 0 2006.173.18:49:30.59#ibcon#read 3, iclass 10, count 0 2006.173.18:49:30.59#ibcon#about to read 4, iclass 10, count 0 2006.173.18:49:30.59#ibcon#read 4, iclass 10, count 0 2006.173.18:49:30.59#ibcon#about to read 5, iclass 10, count 0 2006.173.18:49:30.59#ibcon#read 5, iclass 10, count 0 2006.173.18:49:30.59#ibcon#about to read 6, iclass 10, count 0 2006.173.18:49:30.59#ibcon#read 6, iclass 10, count 0 2006.173.18:49:30.59#ibcon#end of sib2, iclass 10, count 0 2006.173.18:49:30.59#ibcon#*after write, iclass 10, count 0 2006.173.18:49:30.59#ibcon#*before return 0, iclass 10, count 0 2006.173.18:49:30.59#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.18:49:30.59#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.18:49:30.59#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.18:49:30.59#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.18:49:30.59$vck44/va=8,4 2006.173.18:49:30.59#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.18:49:30.59#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.18:49:30.59#ibcon#ireg 11 cls_cnt 2 2006.173.18:49:30.59#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.18:49:30.65#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.18:49:30.65#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.18:49:30.65#ibcon#enter wrdev, iclass 12, count 2 2006.173.18:49:30.65#ibcon#first serial, iclass 12, count 2 2006.173.18:49:30.65#ibcon#enter sib2, iclass 12, count 2 2006.173.18:49:30.65#ibcon#flushed, iclass 12, count 2 2006.173.18:49:30.65#ibcon#about to write, iclass 12, count 2 2006.173.18:49:30.65#ibcon#wrote, iclass 12, count 2 2006.173.18:49:30.65#ibcon#about to read 3, iclass 12, count 2 2006.173.18:49:30.67#ibcon#read 3, iclass 12, count 2 2006.173.18:49:30.67#ibcon#about to read 4, iclass 12, count 2 2006.173.18:49:30.67#ibcon#read 4, iclass 12, count 2 2006.173.18:49:30.67#ibcon#about to read 5, iclass 12, count 2 2006.173.18:49:30.67#ibcon#read 5, iclass 12, count 2 2006.173.18:49:30.67#ibcon#about to read 6, iclass 12, count 2 2006.173.18:49:30.67#ibcon#read 6, iclass 12, count 2 2006.173.18:49:30.67#ibcon#end of sib2, iclass 12, count 2 2006.173.18:49:30.67#ibcon#*mode == 0, iclass 12, count 2 2006.173.18:49:30.67#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.18:49:30.67#ibcon#[25=AT08-04\r\n] 2006.173.18:49:30.67#ibcon#*before write, iclass 12, count 2 2006.173.18:49:30.67#ibcon#enter sib2, iclass 12, count 2 2006.173.18:49:30.67#ibcon#flushed, iclass 12, count 2 2006.173.18:49:30.67#ibcon#about to write, iclass 12, count 2 2006.173.18:49:30.67#ibcon#wrote, iclass 12, count 2 2006.173.18:49:30.67#ibcon#about to read 3, iclass 12, count 2 2006.173.18:49:30.70#ibcon#read 3, iclass 12, count 2 2006.173.18:49:30.70#ibcon#about to read 4, iclass 12, count 2 2006.173.18:49:30.70#ibcon#read 4, iclass 12, count 2 2006.173.18:49:30.70#ibcon#about to read 5, iclass 12, count 2 2006.173.18:49:30.70#ibcon#read 5, iclass 12, count 2 2006.173.18:49:30.70#ibcon#about to read 6, iclass 12, count 2 2006.173.18:49:30.70#ibcon#read 6, iclass 12, count 2 2006.173.18:49:30.70#ibcon#end of sib2, iclass 12, count 2 2006.173.18:49:30.70#ibcon#*after write, iclass 12, count 2 2006.173.18:49:30.70#ibcon#*before return 0, iclass 12, count 2 2006.173.18:49:30.70#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.18:49:30.70#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.18:49:30.70#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.18:49:30.70#ibcon#ireg 7 cls_cnt 0 2006.173.18:49:30.70#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.18:49:30.82#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.18:49:30.82#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.18:49:30.82#ibcon#enter wrdev, iclass 12, count 0 2006.173.18:49:30.82#ibcon#first serial, iclass 12, count 0 2006.173.18:49:30.82#ibcon#enter sib2, iclass 12, count 0 2006.173.18:49:30.82#ibcon#flushed, iclass 12, count 0 2006.173.18:49:30.82#ibcon#about to write, iclass 12, count 0 2006.173.18:49:30.82#ibcon#wrote, iclass 12, count 0 2006.173.18:49:30.82#ibcon#about to read 3, iclass 12, count 0 2006.173.18:49:30.84#ibcon#read 3, iclass 12, count 0 2006.173.18:49:30.84#ibcon#about to read 4, iclass 12, count 0 2006.173.18:49:30.84#ibcon#read 4, iclass 12, count 0 2006.173.18:49:30.84#ibcon#about to read 5, iclass 12, count 0 2006.173.18:49:30.84#ibcon#read 5, iclass 12, count 0 2006.173.18:49:30.84#ibcon#about to read 6, iclass 12, count 0 2006.173.18:49:30.84#ibcon#read 6, iclass 12, count 0 2006.173.18:49:30.84#ibcon#end of sib2, iclass 12, count 0 2006.173.18:49:30.84#ibcon#*mode == 0, iclass 12, count 0 2006.173.18:49:30.84#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.18:49:30.84#ibcon#[25=USB\r\n] 2006.173.18:49:30.84#ibcon#*before write, iclass 12, count 0 2006.173.18:49:30.84#ibcon#enter sib2, iclass 12, count 0 2006.173.18:49:30.84#ibcon#flushed, iclass 12, count 0 2006.173.18:49:30.84#ibcon#about to write, iclass 12, count 0 2006.173.18:49:30.84#ibcon#wrote, iclass 12, count 0 2006.173.18:49:30.84#ibcon#about to read 3, iclass 12, count 0 2006.173.18:49:30.87#ibcon#read 3, iclass 12, count 0 2006.173.18:49:30.87#ibcon#about to read 4, iclass 12, count 0 2006.173.18:49:30.87#ibcon#read 4, iclass 12, count 0 2006.173.18:49:30.87#ibcon#about to read 5, iclass 12, count 0 2006.173.18:49:30.87#ibcon#read 5, iclass 12, count 0 2006.173.18:49:30.87#ibcon#about to read 6, iclass 12, count 0 2006.173.18:49:30.87#ibcon#read 6, iclass 12, count 0 2006.173.18:49:30.87#ibcon#end of sib2, iclass 12, count 0 2006.173.18:49:30.87#ibcon#*after write, iclass 12, count 0 2006.173.18:49:30.87#ibcon#*before return 0, iclass 12, count 0 2006.173.18:49:30.87#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.18:49:30.87#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.18:49:30.87#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.18:49:30.87#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.18:49:30.87$vck44/vblo=1,629.99 2006.173.18:49:30.87#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.18:49:30.87#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.18:49:30.87#ibcon#ireg 17 cls_cnt 0 2006.173.18:49:30.87#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.18:49:30.87#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.18:49:30.87#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.18:49:30.87#ibcon#enter wrdev, iclass 14, count 0 2006.173.18:49:30.87#ibcon#first serial, iclass 14, count 0 2006.173.18:49:30.87#ibcon#enter sib2, iclass 14, count 0 2006.173.18:49:30.87#ibcon#flushed, iclass 14, count 0 2006.173.18:49:30.87#ibcon#about to write, iclass 14, count 0 2006.173.18:49:30.87#ibcon#wrote, iclass 14, count 0 2006.173.18:49:30.87#ibcon#about to read 3, iclass 14, count 0 2006.173.18:49:30.89#ibcon#read 3, iclass 14, count 0 2006.173.18:49:30.89#ibcon#about to read 4, iclass 14, count 0 2006.173.18:49:30.89#ibcon#read 4, iclass 14, count 0 2006.173.18:49:30.89#ibcon#about to read 5, iclass 14, count 0 2006.173.18:49:30.89#ibcon#read 5, iclass 14, count 0 2006.173.18:49:30.89#ibcon#about to read 6, iclass 14, count 0 2006.173.18:49:30.89#ibcon#read 6, iclass 14, count 0 2006.173.18:49:30.89#ibcon#end of sib2, iclass 14, count 0 2006.173.18:49:30.89#ibcon#*mode == 0, iclass 14, count 0 2006.173.18:49:30.89#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.18:49:30.89#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.18:49:30.89#ibcon#*before write, iclass 14, count 0 2006.173.18:49:30.89#ibcon#enter sib2, iclass 14, count 0 2006.173.18:49:30.89#ibcon#flushed, iclass 14, count 0 2006.173.18:49:30.89#ibcon#about to write, iclass 14, count 0 2006.173.18:49:30.89#ibcon#wrote, iclass 14, count 0 2006.173.18:49:30.89#ibcon#about to read 3, iclass 14, count 0 2006.173.18:49:30.93#ibcon#read 3, iclass 14, count 0 2006.173.18:49:30.93#ibcon#about to read 4, iclass 14, count 0 2006.173.18:49:30.93#ibcon#read 4, iclass 14, count 0 2006.173.18:49:30.93#ibcon#about to read 5, iclass 14, count 0 2006.173.18:49:30.93#ibcon#read 5, iclass 14, count 0 2006.173.18:49:30.93#ibcon#about to read 6, iclass 14, count 0 2006.173.18:49:30.93#ibcon#read 6, iclass 14, count 0 2006.173.18:49:30.93#ibcon#end of sib2, iclass 14, count 0 2006.173.18:49:30.93#ibcon#*after write, iclass 14, count 0 2006.173.18:49:30.93#ibcon#*before return 0, iclass 14, count 0 2006.173.18:49:30.93#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.18:49:30.93#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.18:49:30.93#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.18:49:30.93#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.18:49:30.93$vck44/vb=1,4 2006.173.18:49:30.93#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.18:49:30.93#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.18:49:30.93#ibcon#ireg 11 cls_cnt 2 2006.173.18:49:30.93#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.18:49:30.93#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.18:49:30.93#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.18:49:30.93#ibcon#enter wrdev, iclass 16, count 2 2006.173.18:49:30.93#ibcon#first serial, iclass 16, count 2 2006.173.18:49:30.93#ibcon#enter sib2, iclass 16, count 2 2006.173.18:49:30.93#ibcon#flushed, iclass 16, count 2 2006.173.18:49:30.93#ibcon#about to write, iclass 16, count 2 2006.173.18:49:30.93#ibcon#wrote, iclass 16, count 2 2006.173.18:49:30.93#ibcon#about to read 3, iclass 16, count 2 2006.173.18:49:30.95#ibcon#read 3, iclass 16, count 2 2006.173.18:49:30.95#ibcon#about to read 4, iclass 16, count 2 2006.173.18:49:30.95#ibcon#read 4, iclass 16, count 2 2006.173.18:49:30.95#ibcon#about to read 5, iclass 16, count 2 2006.173.18:49:30.95#ibcon#read 5, iclass 16, count 2 2006.173.18:49:30.95#ibcon#about to read 6, iclass 16, count 2 2006.173.18:49:30.95#ibcon#read 6, iclass 16, count 2 2006.173.18:49:30.95#ibcon#end of sib2, iclass 16, count 2 2006.173.18:49:30.95#ibcon#*mode == 0, iclass 16, count 2 2006.173.18:49:30.95#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.18:49:30.95#ibcon#[27=AT01-04\r\n] 2006.173.18:49:30.95#ibcon#*before write, iclass 16, count 2 2006.173.18:49:30.95#ibcon#enter sib2, iclass 16, count 2 2006.173.18:49:30.95#ibcon#flushed, iclass 16, count 2 2006.173.18:49:30.95#ibcon#about to write, iclass 16, count 2 2006.173.18:49:30.95#ibcon#wrote, iclass 16, count 2 2006.173.18:49:30.95#ibcon#about to read 3, iclass 16, count 2 2006.173.18:49:30.98#ibcon#read 3, iclass 16, count 2 2006.173.18:49:30.98#ibcon#about to read 4, iclass 16, count 2 2006.173.18:49:30.98#ibcon#read 4, iclass 16, count 2 2006.173.18:49:30.98#ibcon#about to read 5, iclass 16, count 2 2006.173.18:49:30.98#ibcon#read 5, iclass 16, count 2 2006.173.18:49:30.98#ibcon#about to read 6, iclass 16, count 2 2006.173.18:49:30.98#ibcon#read 6, iclass 16, count 2 2006.173.18:49:30.98#ibcon#end of sib2, iclass 16, count 2 2006.173.18:49:30.98#ibcon#*after write, iclass 16, count 2 2006.173.18:49:30.98#ibcon#*before return 0, iclass 16, count 2 2006.173.18:49:30.98#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.18:49:30.98#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.18:49:30.98#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.18:49:30.98#ibcon#ireg 7 cls_cnt 0 2006.173.18:49:30.98#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.18:49:31.10#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.18:49:31.10#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.18:49:31.10#ibcon#enter wrdev, iclass 16, count 0 2006.173.18:49:31.10#ibcon#first serial, iclass 16, count 0 2006.173.18:49:31.10#ibcon#enter sib2, iclass 16, count 0 2006.173.18:49:31.10#ibcon#flushed, iclass 16, count 0 2006.173.18:49:31.10#ibcon#about to write, iclass 16, count 0 2006.173.18:49:31.10#ibcon#wrote, iclass 16, count 0 2006.173.18:49:31.10#ibcon#about to read 3, iclass 16, count 0 2006.173.18:49:31.12#ibcon#read 3, iclass 16, count 0 2006.173.18:49:31.12#ibcon#about to read 4, iclass 16, count 0 2006.173.18:49:31.12#ibcon#read 4, iclass 16, count 0 2006.173.18:49:31.12#ibcon#about to read 5, iclass 16, count 0 2006.173.18:49:31.12#ibcon#read 5, iclass 16, count 0 2006.173.18:49:31.12#ibcon#about to read 6, iclass 16, count 0 2006.173.18:49:31.12#ibcon#read 6, iclass 16, count 0 2006.173.18:49:31.12#ibcon#end of sib2, iclass 16, count 0 2006.173.18:49:31.12#ibcon#*mode == 0, iclass 16, count 0 2006.173.18:49:31.12#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.18:49:31.12#ibcon#[27=USB\r\n] 2006.173.18:49:31.12#ibcon#*before write, iclass 16, count 0 2006.173.18:49:31.12#ibcon#enter sib2, iclass 16, count 0 2006.173.18:49:31.12#ibcon#flushed, iclass 16, count 0 2006.173.18:49:31.12#ibcon#about to write, iclass 16, count 0 2006.173.18:49:31.12#ibcon#wrote, iclass 16, count 0 2006.173.18:49:31.12#ibcon#about to read 3, iclass 16, count 0 2006.173.18:49:31.15#ibcon#read 3, iclass 16, count 0 2006.173.18:49:31.15#ibcon#about to read 4, iclass 16, count 0 2006.173.18:49:31.15#ibcon#read 4, iclass 16, count 0 2006.173.18:49:31.15#ibcon#about to read 5, iclass 16, count 0 2006.173.18:49:31.15#ibcon#read 5, iclass 16, count 0 2006.173.18:49:31.15#ibcon#about to read 6, iclass 16, count 0 2006.173.18:49:31.15#ibcon#read 6, iclass 16, count 0 2006.173.18:49:31.15#ibcon#end of sib2, iclass 16, count 0 2006.173.18:49:31.15#ibcon#*after write, iclass 16, count 0 2006.173.18:49:31.15#ibcon#*before return 0, iclass 16, count 0 2006.173.18:49:31.15#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.18:49:31.15#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.18:49:31.15#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.18:49:31.15#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.18:49:31.15$vck44/vblo=2,634.99 2006.173.18:49:31.15#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.18:49:31.15#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.18:49:31.15#ibcon#ireg 17 cls_cnt 0 2006.173.18:49:31.15#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.18:49:31.15#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.18:49:31.15#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.18:49:31.15#ibcon#enter wrdev, iclass 18, count 0 2006.173.18:49:31.15#ibcon#first serial, iclass 18, count 0 2006.173.18:49:31.15#ibcon#enter sib2, iclass 18, count 0 2006.173.18:49:31.15#ibcon#flushed, iclass 18, count 0 2006.173.18:49:31.15#ibcon#about to write, iclass 18, count 0 2006.173.18:49:31.15#ibcon#wrote, iclass 18, count 0 2006.173.18:49:31.15#ibcon#about to read 3, iclass 18, count 0 2006.173.18:49:31.17#ibcon#read 3, iclass 18, count 0 2006.173.18:49:31.17#ibcon#about to read 4, iclass 18, count 0 2006.173.18:49:31.17#ibcon#read 4, iclass 18, count 0 2006.173.18:49:31.17#ibcon#about to read 5, iclass 18, count 0 2006.173.18:49:31.17#ibcon#read 5, iclass 18, count 0 2006.173.18:49:31.17#ibcon#about to read 6, iclass 18, count 0 2006.173.18:49:31.17#ibcon#read 6, iclass 18, count 0 2006.173.18:49:31.17#ibcon#end of sib2, iclass 18, count 0 2006.173.18:49:31.17#ibcon#*mode == 0, iclass 18, count 0 2006.173.18:49:31.17#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.18:49:31.17#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.18:49:31.17#ibcon#*before write, iclass 18, count 0 2006.173.18:49:31.17#ibcon#enter sib2, iclass 18, count 0 2006.173.18:49:31.17#ibcon#flushed, iclass 18, count 0 2006.173.18:49:31.17#ibcon#about to write, iclass 18, count 0 2006.173.18:49:31.17#ibcon#wrote, iclass 18, count 0 2006.173.18:49:31.17#ibcon#about to read 3, iclass 18, count 0 2006.173.18:49:31.21#ibcon#read 3, iclass 18, count 0 2006.173.18:49:31.21#ibcon#about to read 4, iclass 18, count 0 2006.173.18:49:31.21#ibcon#read 4, iclass 18, count 0 2006.173.18:49:31.21#ibcon#about to read 5, iclass 18, count 0 2006.173.18:49:31.21#ibcon#read 5, iclass 18, count 0 2006.173.18:49:31.21#ibcon#about to read 6, iclass 18, count 0 2006.173.18:49:31.21#ibcon#read 6, iclass 18, count 0 2006.173.18:49:31.21#ibcon#end of sib2, iclass 18, count 0 2006.173.18:49:31.21#ibcon#*after write, iclass 18, count 0 2006.173.18:49:31.21#ibcon#*before return 0, iclass 18, count 0 2006.173.18:49:31.21#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.18:49:31.21#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.18:49:31.21#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.18:49:31.21#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.18:49:31.21$vck44/vb=2,4 2006.173.18:49:31.21#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.18:49:31.21#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.18:49:31.21#ibcon#ireg 11 cls_cnt 2 2006.173.18:49:31.21#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.18:49:31.27#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.18:49:31.27#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.18:49:31.27#ibcon#enter wrdev, iclass 20, count 2 2006.173.18:49:31.27#ibcon#first serial, iclass 20, count 2 2006.173.18:49:31.27#ibcon#enter sib2, iclass 20, count 2 2006.173.18:49:31.27#ibcon#flushed, iclass 20, count 2 2006.173.18:49:31.27#ibcon#about to write, iclass 20, count 2 2006.173.18:49:31.27#ibcon#wrote, iclass 20, count 2 2006.173.18:49:31.27#ibcon#about to read 3, iclass 20, count 2 2006.173.18:49:31.29#ibcon#read 3, iclass 20, count 2 2006.173.18:49:31.29#ibcon#about to read 4, iclass 20, count 2 2006.173.18:49:31.29#ibcon#read 4, iclass 20, count 2 2006.173.18:49:31.29#ibcon#about to read 5, iclass 20, count 2 2006.173.18:49:31.29#ibcon#read 5, iclass 20, count 2 2006.173.18:49:31.29#ibcon#about to read 6, iclass 20, count 2 2006.173.18:49:31.29#ibcon#read 6, iclass 20, count 2 2006.173.18:49:31.29#ibcon#end of sib2, iclass 20, count 2 2006.173.18:49:31.29#ibcon#*mode == 0, iclass 20, count 2 2006.173.18:49:31.29#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.18:49:31.29#ibcon#[27=AT02-04\r\n] 2006.173.18:49:31.29#ibcon#*before write, iclass 20, count 2 2006.173.18:49:31.29#ibcon#enter sib2, iclass 20, count 2 2006.173.18:49:31.29#ibcon#flushed, iclass 20, count 2 2006.173.18:49:31.29#ibcon#about to write, iclass 20, count 2 2006.173.18:49:31.29#ibcon#wrote, iclass 20, count 2 2006.173.18:49:31.29#ibcon#about to read 3, iclass 20, count 2 2006.173.18:49:31.32#ibcon#read 3, iclass 20, count 2 2006.173.18:49:31.32#ibcon#about to read 4, iclass 20, count 2 2006.173.18:49:31.32#ibcon#read 4, iclass 20, count 2 2006.173.18:49:31.32#ibcon#about to read 5, iclass 20, count 2 2006.173.18:49:31.32#ibcon#read 5, iclass 20, count 2 2006.173.18:49:31.32#ibcon#about to read 6, iclass 20, count 2 2006.173.18:49:31.32#ibcon#read 6, iclass 20, count 2 2006.173.18:49:31.32#ibcon#end of sib2, iclass 20, count 2 2006.173.18:49:31.32#ibcon#*after write, iclass 20, count 2 2006.173.18:49:31.32#ibcon#*before return 0, iclass 20, count 2 2006.173.18:49:31.32#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.18:49:31.32#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.18:49:31.32#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.18:49:31.32#ibcon#ireg 7 cls_cnt 0 2006.173.18:49:31.32#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.18:49:31.44#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.18:49:31.44#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.18:49:31.44#ibcon#enter wrdev, iclass 20, count 0 2006.173.18:49:31.44#ibcon#first serial, iclass 20, count 0 2006.173.18:49:31.44#ibcon#enter sib2, iclass 20, count 0 2006.173.18:49:31.44#ibcon#flushed, iclass 20, count 0 2006.173.18:49:31.44#ibcon#about to write, iclass 20, count 0 2006.173.18:49:31.44#ibcon#wrote, iclass 20, count 0 2006.173.18:49:31.44#ibcon#about to read 3, iclass 20, count 0 2006.173.18:49:31.46#ibcon#read 3, iclass 20, count 0 2006.173.18:49:31.46#ibcon#about to read 4, iclass 20, count 0 2006.173.18:49:31.46#ibcon#read 4, iclass 20, count 0 2006.173.18:49:31.46#ibcon#about to read 5, iclass 20, count 0 2006.173.18:49:31.46#ibcon#read 5, iclass 20, count 0 2006.173.18:49:31.46#ibcon#about to read 6, iclass 20, count 0 2006.173.18:49:31.46#ibcon#read 6, iclass 20, count 0 2006.173.18:49:31.46#ibcon#end of sib2, iclass 20, count 0 2006.173.18:49:31.46#ibcon#*mode == 0, iclass 20, count 0 2006.173.18:49:31.46#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.18:49:31.46#ibcon#[27=USB\r\n] 2006.173.18:49:31.46#ibcon#*before write, iclass 20, count 0 2006.173.18:49:31.46#ibcon#enter sib2, iclass 20, count 0 2006.173.18:49:31.46#ibcon#flushed, iclass 20, count 0 2006.173.18:49:31.46#ibcon#about to write, iclass 20, count 0 2006.173.18:49:31.46#ibcon#wrote, iclass 20, count 0 2006.173.18:49:31.46#ibcon#about to read 3, iclass 20, count 0 2006.173.18:49:31.49#ibcon#read 3, iclass 20, count 0 2006.173.18:49:31.49#ibcon#about to read 4, iclass 20, count 0 2006.173.18:49:31.49#ibcon#read 4, iclass 20, count 0 2006.173.18:49:31.49#ibcon#about to read 5, iclass 20, count 0 2006.173.18:49:31.49#ibcon#read 5, iclass 20, count 0 2006.173.18:49:31.49#ibcon#about to read 6, iclass 20, count 0 2006.173.18:49:31.49#ibcon#read 6, iclass 20, count 0 2006.173.18:49:31.49#ibcon#end of sib2, iclass 20, count 0 2006.173.18:49:31.49#ibcon#*after write, iclass 20, count 0 2006.173.18:49:31.49#ibcon#*before return 0, iclass 20, count 0 2006.173.18:49:31.49#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.18:49:31.49#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.18:49:31.49#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.18:49:31.49#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.18:49:31.49$vck44/vblo=3,649.99 2006.173.18:49:31.49#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.18:49:31.49#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.18:49:31.49#ibcon#ireg 17 cls_cnt 0 2006.173.18:49:31.49#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.18:49:31.49#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.18:49:31.49#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.18:49:31.49#ibcon#enter wrdev, iclass 22, count 0 2006.173.18:49:31.49#ibcon#first serial, iclass 22, count 0 2006.173.18:49:31.49#ibcon#enter sib2, iclass 22, count 0 2006.173.18:49:31.49#ibcon#flushed, iclass 22, count 0 2006.173.18:49:31.49#ibcon#about to write, iclass 22, count 0 2006.173.18:49:31.49#ibcon#wrote, iclass 22, count 0 2006.173.18:49:31.49#ibcon#about to read 3, iclass 22, count 0 2006.173.18:49:31.51#ibcon#read 3, iclass 22, count 0 2006.173.18:49:31.51#ibcon#about to read 4, iclass 22, count 0 2006.173.18:49:31.51#ibcon#read 4, iclass 22, count 0 2006.173.18:49:31.51#ibcon#about to read 5, iclass 22, count 0 2006.173.18:49:31.51#ibcon#read 5, iclass 22, count 0 2006.173.18:49:31.51#ibcon#about to read 6, iclass 22, count 0 2006.173.18:49:31.51#ibcon#read 6, iclass 22, count 0 2006.173.18:49:31.51#ibcon#end of sib2, iclass 22, count 0 2006.173.18:49:31.51#ibcon#*mode == 0, iclass 22, count 0 2006.173.18:49:31.51#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.18:49:31.51#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.18:49:31.51#ibcon#*before write, iclass 22, count 0 2006.173.18:49:31.51#ibcon#enter sib2, iclass 22, count 0 2006.173.18:49:31.51#ibcon#flushed, iclass 22, count 0 2006.173.18:49:31.51#ibcon#about to write, iclass 22, count 0 2006.173.18:49:31.51#ibcon#wrote, iclass 22, count 0 2006.173.18:49:31.51#ibcon#about to read 3, iclass 22, count 0 2006.173.18:49:31.55#ibcon#read 3, iclass 22, count 0 2006.173.18:49:31.55#ibcon#about to read 4, iclass 22, count 0 2006.173.18:49:31.55#ibcon#read 4, iclass 22, count 0 2006.173.18:49:31.55#ibcon#about to read 5, iclass 22, count 0 2006.173.18:49:31.55#ibcon#read 5, iclass 22, count 0 2006.173.18:49:31.55#ibcon#about to read 6, iclass 22, count 0 2006.173.18:49:31.55#ibcon#read 6, iclass 22, count 0 2006.173.18:49:31.55#ibcon#end of sib2, iclass 22, count 0 2006.173.18:49:31.55#ibcon#*after write, iclass 22, count 0 2006.173.18:49:31.55#ibcon#*before return 0, iclass 22, count 0 2006.173.18:49:31.55#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.18:49:31.55#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.18:49:31.55#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.18:49:31.55#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.18:49:31.55$vck44/vb=3,4 2006.173.18:49:31.55#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.18:49:31.55#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.18:49:31.55#ibcon#ireg 11 cls_cnt 2 2006.173.18:49:31.55#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.18:49:31.61#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.18:49:31.61#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.18:49:31.61#ibcon#enter wrdev, iclass 24, count 2 2006.173.18:49:31.61#ibcon#first serial, iclass 24, count 2 2006.173.18:49:31.61#ibcon#enter sib2, iclass 24, count 2 2006.173.18:49:31.61#ibcon#flushed, iclass 24, count 2 2006.173.18:49:31.61#ibcon#about to write, iclass 24, count 2 2006.173.18:49:31.61#ibcon#wrote, iclass 24, count 2 2006.173.18:49:31.61#ibcon#about to read 3, iclass 24, count 2 2006.173.18:49:31.63#ibcon#read 3, iclass 24, count 2 2006.173.18:49:31.63#ibcon#about to read 4, iclass 24, count 2 2006.173.18:49:31.63#ibcon#read 4, iclass 24, count 2 2006.173.18:49:31.63#ibcon#about to read 5, iclass 24, count 2 2006.173.18:49:31.63#ibcon#read 5, iclass 24, count 2 2006.173.18:49:31.63#ibcon#about to read 6, iclass 24, count 2 2006.173.18:49:31.63#ibcon#read 6, iclass 24, count 2 2006.173.18:49:31.63#ibcon#end of sib2, iclass 24, count 2 2006.173.18:49:31.63#ibcon#*mode == 0, iclass 24, count 2 2006.173.18:49:31.63#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.18:49:31.63#ibcon#[27=AT03-04\r\n] 2006.173.18:49:31.63#ibcon#*before write, iclass 24, count 2 2006.173.18:49:31.63#ibcon#enter sib2, iclass 24, count 2 2006.173.18:49:31.63#ibcon#flushed, iclass 24, count 2 2006.173.18:49:31.63#ibcon#about to write, iclass 24, count 2 2006.173.18:49:31.63#ibcon#wrote, iclass 24, count 2 2006.173.18:49:31.63#ibcon#about to read 3, iclass 24, count 2 2006.173.18:49:31.66#ibcon#read 3, iclass 24, count 2 2006.173.18:49:31.66#ibcon#about to read 4, iclass 24, count 2 2006.173.18:49:31.66#ibcon#read 4, iclass 24, count 2 2006.173.18:49:31.66#ibcon#about to read 5, iclass 24, count 2 2006.173.18:49:31.66#ibcon#read 5, iclass 24, count 2 2006.173.18:49:31.66#ibcon#about to read 6, iclass 24, count 2 2006.173.18:49:31.66#ibcon#read 6, iclass 24, count 2 2006.173.18:49:31.66#ibcon#end of sib2, iclass 24, count 2 2006.173.18:49:31.66#ibcon#*after write, iclass 24, count 2 2006.173.18:49:31.66#ibcon#*before return 0, iclass 24, count 2 2006.173.18:49:31.66#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.18:49:31.66#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.18:49:31.66#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.18:49:31.66#ibcon#ireg 7 cls_cnt 0 2006.173.18:49:31.66#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.18:49:31.78#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.18:49:31.78#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.18:49:31.78#ibcon#enter wrdev, iclass 24, count 0 2006.173.18:49:31.78#ibcon#first serial, iclass 24, count 0 2006.173.18:49:31.78#ibcon#enter sib2, iclass 24, count 0 2006.173.18:49:31.78#ibcon#flushed, iclass 24, count 0 2006.173.18:49:31.78#ibcon#about to write, iclass 24, count 0 2006.173.18:49:31.78#ibcon#wrote, iclass 24, count 0 2006.173.18:49:31.78#ibcon#about to read 3, iclass 24, count 0 2006.173.18:49:31.80#ibcon#read 3, iclass 24, count 0 2006.173.18:49:31.80#ibcon#about to read 4, iclass 24, count 0 2006.173.18:49:31.80#ibcon#read 4, iclass 24, count 0 2006.173.18:49:31.80#ibcon#about to read 5, iclass 24, count 0 2006.173.18:49:31.80#ibcon#read 5, iclass 24, count 0 2006.173.18:49:31.80#ibcon#about to read 6, iclass 24, count 0 2006.173.18:49:31.80#ibcon#read 6, iclass 24, count 0 2006.173.18:49:31.80#ibcon#end of sib2, iclass 24, count 0 2006.173.18:49:31.80#ibcon#*mode == 0, iclass 24, count 0 2006.173.18:49:31.80#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.18:49:31.80#ibcon#[27=USB\r\n] 2006.173.18:49:31.80#ibcon#*before write, iclass 24, count 0 2006.173.18:49:31.80#ibcon#enter sib2, iclass 24, count 0 2006.173.18:49:31.80#ibcon#flushed, iclass 24, count 0 2006.173.18:49:31.80#ibcon#about to write, iclass 24, count 0 2006.173.18:49:31.80#ibcon#wrote, iclass 24, count 0 2006.173.18:49:31.80#ibcon#about to read 3, iclass 24, count 0 2006.173.18:49:31.83#ibcon#read 3, iclass 24, count 0 2006.173.18:49:31.83#ibcon#about to read 4, iclass 24, count 0 2006.173.18:49:31.83#ibcon#read 4, iclass 24, count 0 2006.173.18:49:31.83#ibcon#about to read 5, iclass 24, count 0 2006.173.18:49:31.83#ibcon#read 5, iclass 24, count 0 2006.173.18:49:31.83#ibcon#about to read 6, iclass 24, count 0 2006.173.18:49:31.83#ibcon#read 6, iclass 24, count 0 2006.173.18:49:31.83#ibcon#end of sib2, iclass 24, count 0 2006.173.18:49:31.83#ibcon#*after write, iclass 24, count 0 2006.173.18:49:31.83#ibcon#*before return 0, iclass 24, count 0 2006.173.18:49:31.83#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.18:49:31.83#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.18:49:31.83#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.18:49:31.83#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.18:49:31.83$vck44/vblo=4,679.99 2006.173.18:49:31.83#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.18:49:31.83#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.18:49:31.83#ibcon#ireg 17 cls_cnt 0 2006.173.18:49:31.83#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.18:49:31.83#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.18:49:31.83#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.18:49:31.83#ibcon#enter wrdev, iclass 26, count 0 2006.173.18:49:31.83#ibcon#first serial, iclass 26, count 0 2006.173.18:49:31.83#ibcon#enter sib2, iclass 26, count 0 2006.173.18:49:31.83#ibcon#flushed, iclass 26, count 0 2006.173.18:49:31.83#ibcon#about to write, iclass 26, count 0 2006.173.18:49:31.83#ibcon#wrote, iclass 26, count 0 2006.173.18:49:31.83#ibcon#about to read 3, iclass 26, count 0 2006.173.18:49:31.85#ibcon#read 3, iclass 26, count 0 2006.173.18:49:31.85#ibcon#about to read 4, iclass 26, count 0 2006.173.18:49:31.85#ibcon#read 4, iclass 26, count 0 2006.173.18:49:31.85#ibcon#about to read 5, iclass 26, count 0 2006.173.18:49:31.85#ibcon#read 5, iclass 26, count 0 2006.173.18:49:31.85#ibcon#about to read 6, iclass 26, count 0 2006.173.18:49:31.85#ibcon#read 6, iclass 26, count 0 2006.173.18:49:31.85#ibcon#end of sib2, iclass 26, count 0 2006.173.18:49:31.85#ibcon#*mode == 0, iclass 26, count 0 2006.173.18:49:31.85#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.18:49:31.85#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.18:49:31.85#ibcon#*before write, iclass 26, count 0 2006.173.18:49:31.85#ibcon#enter sib2, iclass 26, count 0 2006.173.18:49:31.85#ibcon#flushed, iclass 26, count 0 2006.173.18:49:31.85#ibcon#about to write, iclass 26, count 0 2006.173.18:49:31.85#ibcon#wrote, iclass 26, count 0 2006.173.18:49:31.85#ibcon#about to read 3, iclass 26, count 0 2006.173.18:49:31.89#ibcon#read 3, iclass 26, count 0 2006.173.18:49:31.89#ibcon#about to read 4, iclass 26, count 0 2006.173.18:49:31.89#ibcon#read 4, iclass 26, count 0 2006.173.18:49:31.89#ibcon#about to read 5, iclass 26, count 0 2006.173.18:49:31.89#ibcon#read 5, iclass 26, count 0 2006.173.18:49:31.89#ibcon#about to read 6, iclass 26, count 0 2006.173.18:49:31.89#ibcon#read 6, iclass 26, count 0 2006.173.18:49:31.89#ibcon#end of sib2, iclass 26, count 0 2006.173.18:49:31.89#ibcon#*after write, iclass 26, count 0 2006.173.18:49:31.89#ibcon#*before return 0, iclass 26, count 0 2006.173.18:49:31.89#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.18:49:31.89#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.18:49:31.89#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.18:49:31.89#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.18:49:31.89$vck44/vb=4,4 2006.173.18:49:31.89#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.18:49:31.89#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.18:49:31.89#ibcon#ireg 11 cls_cnt 2 2006.173.18:49:31.89#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.18:49:31.95#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.18:49:31.95#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.18:49:31.95#ibcon#enter wrdev, iclass 28, count 2 2006.173.18:49:31.95#ibcon#first serial, iclass 28, count 2 2006.173.18:49:31.95#ibcon#enter sib2, iclass 28, count 2 2006.173.18:49:31.95#ibcon#flushed, iclass 28, count 2 2006.173.18:49:31.95#ibcon#about to write, iclass 28, count 2 2006.173.18:49:31.95#ibcon#wrote, iclass 28, count 2 2006.173.18:49:31.95#ibcon#about to read 3, iclass 28, count 2 2006.173.18:49:31.97#ibcon#read 3, iclass 28, count 2 2006.173.18:49:31.97#ibcon#about to read 4, iclass 28, count 2 2006.173.18:49:31.97#ibcon#read 4, iclass 28, count 2 2006.173.18:49:31.97#ibcon#about to read 5, iclass 28, count 2 2006.173.18:49:31.97#ibcon#read 5, iclass 28, count 2 2006.173.18:49:31.97#ibcon#about to read 6, iclass 28, count 2 2006.173.18:49:31.97#ibcon#read 6, iclass 28, count 2 2006.173.18:49:31.97#ibcon#end of sib2, iclass 28, count 2 2006.173.18:49:31.97#ibcon#*mode == 0, iclass 28, count 2 2006.173.18:49:31.97#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.18:49:31.97#ibcon#[27=AT04-04\r\n] 2006.173.18:49:31.97#ibcon#*before write, iclass 28, count 2 2006.173.18:49:31.97#ibcon#enter sib2, iclass 28, count 2 2006.173.18:49:31.97#ibcon#flushed, iclass 28, count 2 2006.173.18:49:31.97#ibcon#about to write, iclass 28, count 2 2006.173.18:49:31.97#ibcon#wrote, iclass 28, count 2 2006.173.18:49:31.97#ibcon#about to read 3, iclass 28, count 2 2006.173.18:49:32.00#ibcon#read 3, iclass 28, count 2 2006.173.18:49:32.00#ibcon#about to read 4, iclass 28, count 2 2006.173.18:49:32.00#ibcon#read 4, iclass 28, count 2 2006.173.18:49:32.00#ibcon#about to read 5, iclass 28, count 2 2006.173.18:49:32.00#ibcon#read 5, iclass 28, count 2 2006.173.18:49:32.00#ibcon#about to read 6, iclass 28, count 2 2006.173.18:49:32.00#ibcon#read 6, iclass 28, count 2 2006.173.18:49:32.00#ibcon#end of sib2, iclass 28, count 2 2006.173.18:49:32.00#ibcon#*after write, iclass 28, count 2 2006.173.18:49:32.00#ibcon#*before return 0, iclass 28, count 2 2006.173.18:49:32.00#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.18:49:32.00#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.18:49:32.00#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.18:49:32.00#ibcon#ireg 7 cls_cnt 0 2006.173.18:49:32.00#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.18:49:32.12#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.18:49:32.12#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.18:49:32.12#ibcon#enter wrdev, iclass 28, count 0 2006.173.18:49:32.12#ibcon#first serial, iclass 28, count 0 2006.173.18:49:32.12#ibcon#enter sib2, iclass 28, count 0 2006.173.18:49:32.12#ibcon#flushed, iclass 28, count 0 2006.173.18:49:32.12#ibcon#about to write, iclass 28, count 0 2006.173.18:49:32.12#ibcon#wrote, iclass 28, count 0 2006.173.18:49:32.12#ibcon#about to read 3, iclass 28, count 0 2006.173.18:49:32.14#ibcon#read 3, iclass 28, count 0 2006.173.18:49:32.14#ibcon#about to read 4, iclass 28, count 0 2006.173.18:49:32.14#ibcon#read 4, iclass 28, count 0 2006.173.18:49:32.14#ibcon#about to read 5, iclass 28, count 0 2006.173.18:49:32.14#ibcon#read 5, iclass 28, count 0 2006.173.18:49:32.14#ibcon#about to read 6, iclass 28, count 0 2006.173.18:49:32.14#ibcon#read 6, iclass 28, count 0 2006.173.18:49:32.14#ibcon#end of sib2, iclass 28, count 0 2006.173.18:49:32.14#ibcon#*mode == 0, iclass 28, count 0 2006.173.18:49:32.14#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.18:49:32.14#ibcon#[27=USB\r\n] 2006.173.18:49:32.14#ibcon#*before write, iclass 28, count 0 2006.173.18:49:32.14#ibcon#enter sib2, iclass 28, count 0 2006.173.18:49:32.14#ibcon#flushed, iclass 28, count 0 2006.173.18:49:32.14#ibcon#about to write, iclass 28, count 0 2006.173.18:49:32.14#ibcon#wrote, iclass 28, count 0 2006.173.18:49:32.14#ibcon#about to read 3, iclass 28, count 0 2006.173.18:49:32.17#ibcon#read 3, iclass 28, count 0 2006.173.18:49:32.17#ibcon#about to read 4, iclass 28, count 0 2006.173.18:49:32.17#ibcon#read 4, iclass 28, count 0 2006.173.18:49:32.17#ibcon#about to read 5, iclass 28, count 0 2006.173.18:49:32.17#ibcon#read 5, iclass 28, count 0 2006.173.18:49:32.17#ibcon#about to read 6, iclass 28, count 0 2006.173.18:49:32.17#ibcon#read 6, iclass 28, count 0 2006.173.18:49:32.17#ibcon#end of sib2, iclass 28, count 0 2006.173.18:49:32.17#ibcon#*after write, iclass 28, count 0 2006.173.18:49:32.17#ibcon#*before return 0, iclass 28, count 0 2006.173.18:49:32.17#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.18:49:32.17#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.18:49:32.17#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.18:49:32.17#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.18:49:32.17$vck44/vblo=5,709.99 2006.173.18:49:32.17#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.18:49:32.17#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.18:49:32.17#ibcon#ireg 17 cls_cnt 0 2006.173.18:49:32.17#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.18:49:32.17#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.18:49:32.17#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.18:49:32.17#ibcon#enter wrdev, iclass 30, count 0 2006.173.18:49:32.17#ibcon#first serial, iclass 30, count 0 2006.173.18:49:32.17#ibcon#enter sib2, iclass 30, count 0 2006.173.18:49:32.17#ibcon#flushed, iclass 30, count 0 2006.173.18:49:32.17#ibcon#about to write, iclass 30, count 0 2006.173.18:49:32.17#ibcon#wrote, iclass 30, count 0 2006.173.18:49:32.17#ibcon#about to read 3, iclass 30, count 0 2006.173.18:49:32.19#ibcon#read 3, iclass 30, count 0 2006.173.18:49:32.19#ibcon#about to read 4, iclass 30, count 0 2006.173.18:49:32.19#ibcon#read 4, iclass 30, count 0 2006.173.18:49:32.19#ibcon#about to read 5, iclass 30, count 0 2006.173.18:49:32.19#ibcon#read 5, iclass 30, count 0 2006.173.18:49:32.19#ibcon#about to read 6, iclass 30, count 0 2006.173.18:49:32.19#ibcon#read 6, iclass 30, count 0 2006.173.18:49:32.19#ibcon#end of sib2, iclass 30, count 0 2006.173.18:49:32.19#ibcon#*mode == 0, iclass 30, count 0 2006.173.18:49:32.19#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.18:49:32.19#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.18:49:32.19#ibcon#*before write, iclass 30, count 0 2006.173.18:49:32.19#ibcon#enter sib2, iclass 30, count 0 2006.173.18:49:32.19#ibcon#flushed, iclass 30, count 0 2006.173.18:49:32.19#ibcon#about to write, iclass 30, count 0 2006.173.18:49:32.19#ibcon#wrote, iclass 30, count 0 2006.173.18:49:32.19#ibcon#about to read 3, iclass 30, count 0 2006.173.18:49:32.23#ibcon#read 3, iclass 30, count 0 2006.173.18:49:32.23#ibcon#about to read 4, iclass 30, count 0 2006.173.18:49:32.23#ibcon#read 4, iclass 30, count 0 2006.173.18:49:32.23#ibcon#about to read 5, iclass 30, count 0 2006.173.18:49:32.23#ibcon#read 5, iclass 30, count 0 2006.173.18:49:32.23#ibcon#about to read 6, iclass 30, count 0 2006.173.18:49:32.23#ibcon#read 6, iclass 30, count 0 2006.173.18:49:32.23#ibcon#end of sib2, iclass 30, count 0 2006.173.18:49:32.23#ibcon#*after write, iclass 30, count 0 2006.173.18:49:32.23#ibcon#*before return 0, iclass 30, count 0 2006.173.18:49:32.23#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.18:49:32.23#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.18:49:32.23#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.18:49:32.23#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.18:49:32.23$vck44/vb=5,4 2006.173.18:49:32.23#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.173.18:49:32.23#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.173.18:49:32.23#ibcon#ireg 11 cls_cnt 2 2006.173.18:49:32.23#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.18:49:32.29#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.18:49:32.29#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.18:49:32.29#ibcon#enter wrdev, iclass 32, count 2 2006.173.18:49:32.29#ibcon#first serial, iclass 32, count 2 2006.173.18:49:32.29#ibcon#enter sib2, iclass 32, count 2 2006.173.18:49:32.29#ibcon#flushed, iclass 32, count 2 2006.173.18:49:32.29#ibcon#about to write, iclass 32, count 2 2006.173.18:49:32.29#ibcon#wrote, iclass 32, count 2 2006.173.18:49:32.29#ibcon#about to read 3, iclass 32, count 2 2006.173.18:49:32.31#ibcon#read 3, iclass 32, count 2 2006.173.18:49:32.31#ibcon#about to read 4, iclass 32, count 2 2006.173.18:49:32.31#ibcon#read 4, iclass 32, count 2 2006.173.18:49:32.31#ibcon#about to read 5, iclass 32, count 2 2006.173.18:49:32.31#ibcon#read 5, iclass 32, count 2 2006.173.18:49:32.31#ibcon#about to read 6, iclass 32, count 2 2006.173.18:49:32.31#ibcon#read 6, iclass 32, count 2 2006.173.18:49:32.31#ibcon#end of sib2, iclass 32, count 2 2006.173.18:49:32.31#ibcon#*mode == 0, iclass 32, count 2 2006.173.18:49:32.31#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.173.18:49:32.31#ibcon#[27=AT05-04\r\n] 2006.173.18:49:32.31#ibcon#*before write, iclass 32, count 2 2006.173.18:49:32.31#ibcon#enter sib2, iclass 32, count 2 2006.173.18:49:32.31#ibcon#flushed, iclass 32, count 2 2006.173.18:49:32.31#ibcon#about to write, iclass 32, count 2 2006.173.18:49:32.31#ibcon#wrote, iclass 32, count 2 2006.173.18:49:32.31#ibcon#about to read 3, iclass 32, count 2 2006.173.18:49:32.34#ibcon#read 3, iclass 32, count 2 2006.173.18:49:32.34#ibcon#about to read 4, iclass 32, count 2 2006.173.18:49:32.34#ibcon#read 4, iclass 32, count 2 2006.173.18:49:32.34#ibcon#about to read 5, iclass 32, count 2 2006.173.18:49:32.34#ibcon#read 5, iclass 32, count 2 2006.173.18:49:32.34#ibcon#about to read 6, iclass 32, count 2 2006.173.18:49:32.34#ibcon#read 6, iclass 32, count 2 2006.173.18:49:32.34#ibcon#end of sib2, iclass 32, count 2 2006.173.18:49:32.34#ibcon#*after write, iclass 32, count 2 2006.173.18:49:32.34#ibcon#*before return 0, iclass 32, count 2 2006.173.18:49:32.34#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.18:49:32.34#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.173.18:49:32.34#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.173.18:49:32.34#ibcon#ireg 7 cls_cnt 0 2006.173.18:49:32.34#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.18:49:32.46#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.18:49:32.46#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.18:49:32.46#ibcon#enter wrdev, iclass 32, count 0 2006.173.18:49:32.46#ibcon#first serial, iclass 32, count 0 2006.173.18:49:32.46#ibcon#enter sib2, iclass 32, count 0 2006.173.18:49:32.46#ibcon#flushed, iclass 32, count 0 2006.173.18:49:32.46#ibcon#about to write, iclass 32, count 0 2006.173.18:49:32.46#ibcon#wrote, iclass 32, count 0 2006.173.18:49:32.46#ibcon#about to read 3, iclass 32, count 0 2006.173.18:49:32.48#ibcon#read 3, iclass 32, count 0 2006.173.18:49:32.48#ibcon#about to read 4, iclass 32, count 0 2006.173.18:49:32.48#ibcon#read 4, iclass 32, count 0 2006.173.18:49:32.48#ibcon#about to read 5, iclass 32, count 0 2006.173.18:49:32.48#ibcon#read 5, iclass 32, count 0 2006.173.18:49:32.48#ibcon#about to read 6, iclass 32, count 0 2006.173.18:49:32.48#ibcon#read 6, iclass 32, count 0 2006.173.18:49:32.48#ibcon#end of sib2, iclass 32, count 0 2006.173.18:49:32.48#ibcon#*mode == 0, iclass 32, count 0 2006.173.18:49:32.48#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.18:49:32.48#ibcon#[27=USB\r\n] 2006.173.18:49:32.48#ibcon#*before write, iclass 32, count 0 2006.173.18:49:32.48#ibcon#enter sib2, iclass 32, count 0 2006.173.18:49:32.48#ibcon#flushed, iclass 32, count 0 2006.173.18:49:32.48#ibcon#about to write, iclass 32, count 0 2006.173.18:49:32.48#ibcon#wrote, iclass 32, count 0 2006.173.18:49:32.48#ibcon#about to read 3, iclass 32, count 0 2006.173.18:49:32.51#ibcon#read 3, iclass 32, count 0 2006.173.18:49:32.51#ibcon#about to read 4, iclass 32, count 0 2006.173.18:49:32.51#ibcon#read 4, iclass 32, count 0 2006.173.18:49:32.51#ibcon#about to read 5, iclass 32, count 0 2006.173.18:49:32.51#ibcon#read 5, iclass 32, count 0 2006.173.18:49:32.51#ibcon#about to read 6, iclass 32, count 0 2006.173.18:49:32.51#ibcon#read 6, iclass 32, count 0 2006.173.18:49:32.51#ibcon#end of sib2, iclass 32, count 0 2006.173.18:49:32.51#ibcon#*after write, iclass 32, count 0 2006.173.18:49:32.51#ibcon#*before return 0, iclass 32, count 0 2006.173.18:49:32.51#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.18:49:32.51#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.173.18:49:32.51#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.18:49:32.51#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.18:49:32.51$vck44/vblo=6,719.99 2006.173.18:49:32.51#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.18:49:32.51#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.18:49:32.51#ibcon#ireg 17 cls_cnt 0 2006.173.18:49:32.51#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.18:49:32.51#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.18:49:32.51#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.18:49:32.51#ibcon#enter wrdev, iclass 34, count 0 2006.173.18:49:32.51#ibcon#first serial, iclass 34, count 0 2006.173.18:49:32.51#ibcon#enter sib2, iclass 34, count 0 2006.173.18:49:32.51#ibcon#flushed, iclass 34, count 0 2006.173.18:49:32.51#ibcon#about to write, iclass 34, count 0 2006.173.18:49:32.51#ibcon#wrote, iclass 34, count 0 2006.173.18:49:32.51#ibcon#about to read 3, iclass 34, count 0 2006.173.18:49:32.53#ibcon#read 3, iclass 34, count 0 2006.173.18:49:32.53#ibcon#about to read 4, iclass 34, count 0 2006.173.18:49:32.53#ibcon#read 4, iclass 34, count 0 2006.173.18:49:32.53#ibcon#about to read 5, iclass 34, count 0 2006.173.18:49:32.53#ibcon#read 5, iclass 34, count 0 2006.173.18:49:32.53#ibcon#about to read 6, iclass 34, count 0 2006.173.18:49:32.53#ibcon#read 6, iclass 34, count 0 2006.173.18:49:32.53#ibcon#end of sib2, iclass 34, count 0 2006.173.18:49:32.53#ibcon#*mode == 0, iclass 34, count 0 2006.173.18:49:32.53#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.18:49:32.53#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.18:49:32.53#ibcon#*before write, iclass 34, count 0 2006.173.18:49:32.53#ibcon#enter sib2, iclass 34, count 0 2006.173.18:49:32.53#ibcon#flushed, iclass 34, count 0 2006.173.18:49:32.53#ibcon#about to write, iclass 34, count 0 2006.173.18:49:32.53#ibcon#wrote, iclass 34, count 0 2006.173.18:49:32.53#ibcon#about to read 3, iclass 34, count 0 2006.173.18:49:32.57#ibcon#read 3, iclass 34, count 0 2006.173.18:49:32.57#ibcon#about to read 4, iclass 34, count 0 2006.173.18:49:32.57#ibcon#read 4, iclass 34, count 0 2006.173.18:49:32.57#ibcon#about to read 5, iclass 34, count 0 2006.173.18:49:32.57#ibcon#read 5, iclass 34, count 0 2006.173.18:49:32.57#ibcon#about to read 6, iclass 34, count 0 2006.173.18:49:32.57#ibcon#read 6, iclass 34, count 0 2006.173.18:49:32.57#ibcon#end of sib2, iclass 34, count 0 2006.173.18:49:32.57#ibcon#*after write, iclass 34, count 0 2006.173.18:49:32.57#ibcon#*before return 0, iclass 34, count 0 2006.173.18:49:32.57#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.18:49:32.57#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.18:49:32.57#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.18:49:32.57#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.18:49:32.57$vck44/vb=6,4 2006.173.18:49:32.57#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.18:49:32.57#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.18:49:32.57#ibcon#ireg 11 cls_cnt 2 2006.173.18:49:32.57#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.18:49:32.63#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.18:49:32.63#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.18:49:32.63#ibcon#enter wrdev, iclass 36, count 2 2006.173.18:49:32.63#ibcon#first serial, iclass 36, count 2 2006.173.18:49:32.63#ibcon#enter sib2, iclass 36, count 2 2006.173.18:49:32.63#ibcon#flushed, iclass 36, count 2 2006.173.18:49:32.63#ibcon#about to write, iclass 36, count 2 2006.173.18:49:32.63#ibcon#wrote, iclass 36, count 2 2006.173.18:49:32.63#ibcon#about to read 3, iclass 36, count 2 2006.173.18:49:32.65#ibcon#read 3, iclass 36, count 2 2006.173.18:49:32.65#ibcon#about to read 4, iclass 36, count 2 2006.173.18:49:32.65#ibcon#read 4, iclass 36, count 2 2006.173.18:49:32.65#ibcon#about to read 5, iclass 36, count 2 2006.173.18:49:32.65#ibcon#read 5, iclass 36, count 2 2006.173.18:49:32.65#ibcon#about to read 6, iclass 36, count 2 2006.173.18:49:32.65#ibcon#read 6, iclass 36, count 2 2006.173.18:49:32.65#ibcon#end of sib2, iclass 36, count 2 2006.173.18:49:32.65#ibcon#*mode == 0, iclass 36, count 2 2006.173.18:49:32.65#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.18:49:32.65#ibcon#[27=AT06-04\r\n] 2006.173.18:49:32.65#ibcon#*before write, iclass 36, count 2 2006.173.18:49:32.65#ibcon#enter sib2, iclass 36, count 2 2006.173.18:49:32.65#ibcon#flushed, iclass 36, count 2 2006.173.18:49:32.65#ibcon#about to write, iclass 36, count 2 2006.173.18:49:32.65#ibcon#wrote, iclass 36, count 2 2006.173.18:49:32.65#ibcon#about to read 3, iclass 36, count 2 2006.173.18:49:32.68#ibcon#read 3, iclass 36, count 2 2006.173.18:49:32.68#ibcon#about to read 4, iclass 36, count 2 2006.173.18:49:32.68#ibcon#read 4, iclass 36, count 2 2006.173.18:49:32.68#ibcon#about to read 5, iclass 36, count 2 2006.173.18:49:32.68#ibcon#read 5, iclass 36, count 2 2006.173.18:49:32.68#ibcon#about to read 6, iclass 36, count 2 2006.173.18:49:32.68#ibcon#read 6, iclass 36, count 2 2006.173.18:49:32.68#ibcon#end of sib2, iclass 36, count 2 2006.173.18:49:32.68#ibcon#*after write, iclass 36, count 2 2006.173.18:49:32.68#ibcon#*before return 0, iclass 36, count 2 2006.173.18:49:32.68#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.18:49:32.68#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.18:49:32.68#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.18:49:32.68#ibcon#ireg 7 cls_cnt 0 2006.173.18:49:32.68#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.18:49:32.80#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.18:49:32.80#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.18:49:32.80#ibcon#enter wrdev, iclass 36, count 0 2006.173.18:49:32.80#ibcon#first serial, iclass 36, count 0 2006.173.18:49:32.80#ibcon#enter sib2, iclass 36, count 0 2006.173.18:49:32.80#ibcon#flushed, iclass 36, count 0 2006.173.18:49:32.80#ibcon#about to write, iclass 36, count 0 2006.173.18:49:32.80#ibcon#wrote, iclass 36, count 0 2006.173.18:49:32.80#ibcon#about to read 3, iclass 36, count 0 2006.173.18:49:32.82#ibcon#read 3, iclass 36, count 0 2006.173.18:49:32.82#ibcon#about to read 4, iclass 36, count 0 2006.173.18:49:32.82#ibcon#read 4, iclass 36, count 0 2006.173.18:49:32.82#ibcon#about to read 5, iclass 36, count 0 2006.173.18:49:32.82#ibcon#read 5, iclass 36, count 0 2006.173.18:49:32.82#ibcon#about to read 6, iclass 36, count 0 2006.173.18:49:32.82#ibcon#read 6, iclass 36, count 0 2006.173.18:49:32.82#ibcon#end of sib2, iclass 36, count 0 2006.173.18:49:32.82#ibcon#*mode == 0, iclass 36, count 0 2006.173.18:49:32.82#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.18:49:32.82#ibcon#[27=USB\r\n] 2006.173.18:49:32.82#ibcon#*before write, iclass 36, count 0 2006.173.18:49:32.82#ibcon#enter sib2, iclass 36, count 0 2006.173.18:49:32.82#ibcon#flushed, iclass 36, count 0 2006.173.18:49:32.82#ibcon#about to write, iclass 36, count 0 2006.173.18:49:32.82#ibcon#wrote, iclass 36, count 0 2006.173.18:49:32.82#ibcon#about to read 3, iclass 36, count 0 2006.173.18:49:32.85#ibcon#read 3, iclass 36, count 0 2006.173.18:49:32.85#ibcon#about to read 4, iclass 36, count 0 2006.173.18:49:32.85#ibcon#read 4, iclass 36, count 0 2006.173.18:49:32.85#ibcon#about to read 5, iclass 36, count 0 2006.173.18:49:32.85#ibcon#read 5, iclass 36, count 0 2006.173.18:49:32.85#ibcon#about to read 6, iclass 36, count 0 2006.173.18:49:32.85#ibcon#read 6, iclass 36, count 0 2006.173.18:49:32.85#ibcon#end of sib2, iclass 36, count 0 2006.173.18:49:32.85#ibcon#*after write, iclass 36, count 0 2006.173.18:49:32.85#ibcon#*before return 0, iclass 36, count 0 2006.173.18:49:32.85#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.18:49:32.85#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.18:49:32.85#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.18:49:32.85#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.18:49:32.85$vck44/vblo=7,734.99 2006.173.18:49:32.85#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.18:49:32.85#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.18:49:32.85#ibcon#ireg 17 cls_cnt 0 2006.173.18:49:32.85#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.18:49:32.85#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.18:49:32.85#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.18:49:32.85#ibcon#enter wrdev, iclass 38, count 0 2006.173.18:49:32.85#ibcon#first serial, iclass 38, count 0 2006.173.18:49:32.85#ibcon#enter sib2, iclass 38, count 0 2006.173.18:49:32.85#ibcon#flushed, iclass 38, count 0 2006.173.18:49:32.85#ibcon#about to write, iclass 38, count 0 2006.173.18:49:32.85#ibcon#wrote, iclass 38, count 0 2006.173.18:49:32.85#ibcon#about to read 3, iclass 38, count 0 2006.173.18:49:32.87#ibcon#read 3, iclass 38, count 0 2006.173.18:49:32.87#ibcon#about to read 4, iclass 38, count 0 2006.173.18:49:32.87#ibcon#read 4, iclass 38, count 0 2006.173.18:49:32.87#ibcon#about to read 5, iclass 38, count 0 2006.173.18:49:32.87#ibcon#read 5, iclass 38, count 0 2006.173.18:49:32.87#ibcon#about to read 6, iclass 38, count 0 2006.173.18:49:32.87#ibcon#read 6, iclass 38, count 0 2006.173.18:49:32.87#ibcon#end of sib2, iclass 38, count 0 2006.173.18:49:32.87#ibcon#*mode == 0, iclass 38, count 0 2006.173.18:49:32.87#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.18:49:32.87#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.18:49:32.87#ibcon#*before write, iclass 38, count 0 2006.173.18:49:32.87#ibcon#enter sib2, iclass 38, count 0 2006.173.18:49:32.87#ibcon#flushed, iclass 38, count 0 2006.173.18:49:32.87#ibcon#about to write, iclass 38, count 0 2006.173.18:49:32.87#ibcon#wrote, iclass 38, count 0 2006.173.18:49:32.87#ibcon#about to read 3, iclass 38, count 0 2006.173.18:49:32.91#ibcon#read 3, iclass 38, count 0 2006.173.18:49:32.91#ibcon#about to read 4, iclass 38, count 0 2006.173.18:49:32.91#ibcon#read 4, iclass 38, count 0 2006.173.18:49:32.91#ibcon#about to read 5, iclass 38, count 0 2006.173.18:49:32.91#ibcon#read 5, iclass 38, count 0 2006.173.18:49:32.91#ibcon#about to read 6, iclass 38, count 0 2006.173.18:49:32.91#ibcon#read 6, iclass 38, count 0 2006.173.18:49:32.91#ibcon#end of sib2, iclass 38, count 0 2006.173.18:49:32.91#ibcon#*after write, iclass 38, count 0 2006.173.18:49:32.91#ibcon#*before return 0, iclass 38, count 0 2006.173.18:49:32.91#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.18:49:32.91#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.18:49:32.91#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.18:49:32.91#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.18:49:32.91$vck44/vb=7,4 2006.173.18:49:32.91#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.18:49:32.91#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.18:49:32.91#ibcon#ireg 11 cls_cnt 2 2006.173.18:49:32.91#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.18:49:32.97#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.18:49:32.97#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.18:49:32.97#ibcon#enter wrdev, iclass 40, count 2 2006.173.18:49:32.97#ibcon#first serial, iclass 40, count 2 2006.173.18:49:32.97#ibcon#enter sib2, iclass 40, count 2 2006.173.18:49:32.97#ibcon#flushed, iclass 40, count 2 2006.173.18:49:32.97#ibcon#about to write, iclass 40, count 2 2006.173.18:49:32.97#ibcon#wrote, iclass 40, count 2 2006.173.18:49:32.97#ibcon#about to read 3, iclass 40, count 2 2006.173.18:49:32.99#ibcon#read 3, iclass 40, count 2 2006.173.18:49:32.99#ibcon#about to read 4, iclass 40, count 2 2006.173.18:49:32.99#ibcon#read 4, iclass 40, count 2 2006.173.18:49:32.99#ibcon#about to read 5, iclass 40, count 2 2006.173.18:49:32.99#ibcon#read 5, iclass 40, count 2 2006.173.18:49:32.99#ibcon#about to read 6, iclass 40, count 2 2006.173.18:49:32.99#ibcon#read 6, iclass 40, count 2 2006.173.18:49:32.99#ibcon#end of sib2, iclass 40, count 2 2006.173.18:49:32.99#ibcon#*mode == 0, iclass 40, count 2 2006.173.18:49:32.99#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.18:49:32.99#ibcon#[27=AT07-04\r\n] 2006.173.18:49:32.99#ibcon#*before write, iclass 40, count 2 2006.173.18:49:32.99#ibcon#enter sib2, iclass 40, count 2 2006.173.18:49:32.99#ibcon#flushed, iclass 40, count 2 2006.173.18:49:32.99#ibcon#about to write, iclass 40, count 2 2006.173.18:49:32.99#ibcon#wrote, iclass 40, count 2 2006.173.18:49:32.99#ibcon#about to read 3, iclass 40, count 2 2006.173.18:49:33.02#ibcon#read 3, iclass 40, count 2 2006.173.18:49:33.02#ibcon#about to read 4, iclass 40, count 2 2006.173.18:49:33.02#ibcon#read 4, iclass 40, count 2 2006.173.18:49:33.02#ibcon#about to read 5, iclass 40, count 2 2006.173.18:49:33.02#ibcon#read 5, iclass 40, count 2 2006.173.18:49:33.02#ibcon#about to read 6, iclass 40, count 2 2006.173.18:49:33.02#ibcon#read 6, iclass 40, count 2 2006.173.18:49:33.02#ibcon#end of sib2, iclass 40, count 2 2006.173.18:49:33.02#ibcon#*after write, iclass 40, count 2 2006.173.18:49:33.02#ibcon#*before return 0, iclass 40, count 2 2006.173.18:49:33.02#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.18:49:33.02#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.18:49:33.02#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.18:49:33.02#ibcon#ireg 7 cls_cnt 0 2006.173.18:49:33.02#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.18:49:33.14#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.18:49:33.14#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.18:49:33.14#ibcon#enter wrdev, iclass 40, count 0 2006.173.18:49:33.14#ibcon#first serial, iclass 40, count 0 2006.173.18:49:33.14#ibcon#enter sib2, iclass 40, count 0 2006.173.18:49:33.14#ibcon#flushed, iclass 40, count 0 2006.173.18:49:33.14#ibcon#about to write, iclass 40, count 0 2006.173.18:49:33.14#ibcon#wrote, iclass 40, count 0 2006.173.18:49:33.14#ibcon#about to read 3, iclass 40, count 0 2006.173.18:49:33.16#ibcon#read 3, iclass 40, count 0 2006.173.18:49:33.16#ibcon#about to read 4, iclass 40, count 0 2006.173.18:49:33.16#ibcon#read 4, iclass 40, count 0 2006.173.18:49:33.16#ibcon#about to read 5, iclass 40, count 0 2006.173.18:49:33.16#ibcon#read 5, iclass 40, count 0 2006.173.18:49:33.16#ibcon#about to read 6, iclass 40, count 0 2006.173.18:49:33.16#ibcon#read 6, iclass 40, count 0 2006.173.18:49:33.16#ibcon#end of sib2, iclass 40, count 0 2006.173.18:49:33.16#ibcon#*mode == 0, iclass 40, count 0 2006.173.18:49:33.16#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.18:49:33.16#ibcon#[27=USB\r\n] 2006.173.18:49:33.16#ibcon#*before write, iclass 40, count 0 2006.173.18:49:33.16#ibcon#enter sib2, iclass 40, count 0 2006.173.18:49:33.16#ibcon#flushed, iclass 40, count 0 2006.173.18:49:33.16#ibcon#about to write, iclass 40, count 0 2006.173.18:49:33.16#ibcon#wrote, iclass 40, count 0 2006.173.18:49:33.16#ibcon#about to read 3, iclass 40, count 0 2006.173.18:49:33.19#ibcon#read 3, iclass 40, count 0 2006.173.18:49:33.19#ibcon#about to read 4, iclass 40, count 0 2006.173.18:49:33.19#ibcon#read 4, iclass 40, count 0 2006.173.18:49:33.19#ibcon#about to read 5, iclass 40, count 0 2006.173.18:49:33.19#ibcon#read 5, iclass 40, count 0 2006.173.18:49:33.19#ibcon#about to read 6, iclass 40, count 0 2006.173.18:49:33.19#ibcon#read 6, iclass 40, count 0 2006.173.18:49:33.19#ibcon#end of sib2, iclass 40, count 0 2006.173.18:49:33.19#ibcon#*after write, iclass 40, count 0 2006.173.18:49:33.19#ibcon#*before return 0, iclass 40, count 0 2006.173.18:49:33.19#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.18:49:33.19#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.18:49:33.19#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.18:49:33.19#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.18:49:33.19$vck44/vblo=8,744.99 2006.173.18:49:33.19#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.18:49:33.19#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.18:49:33.19#ibcon#ireg 17 cls_cnt 0 2006.173.18:49:33.19#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.18:49:33.19#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.18:49:33.19#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.18:49:33.19#ibcon#enter wrdev, iclass 4, count 0 2006.173.18:49:33.19#ibcon#first serial, iclass 4, count 0 2006.173.18:49:33.19#ibcon#enter sib2, iclass 4, count 0 2006.173.18:49:33.19#ibcon#flushed, iclass 4, count 0 2006.173.18:49:33.19#ibcon#about to write, iclass 4, count 0 2006.173.18:49:33.19#ibcon#wrote, iclass 4, count 0 2006.173.18:49:33.19#ibcon#about to read 3, iclass 4, count 0 2006.173.18:49:33.21#ibcon#read 3, iclass 4, count 0 2006.173.18:49:33.21#ibcon#about to read 4, iclass 4, count 0 2006.173.18:49:33.21#ibcon#read 4, iclass 4, count 0 2006.173.18:49:33.21#ibcon#about to read 5, iclass 4, count 0 2006.173.18:49:33.21#ibcon#read 5, iclass 4, count 0 2006.173.18:49:33.21#ibcon#about to read 6, iclass 4, count 0 2006.173.18:49:33.21#ibcon#read 6, iclass 4, count 0 2006.173.18:49:33.21#ibcon#end of sib2, iclass 4, count 0 2006.173.18:49:33.21#ibcon#*mode == 0, iclass 4, count 0 2006.173.18:49:33.21#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.18:49:33.21#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.18:49:33.21#ibcon#*before write, iclass 4, count 0 2006.173.18:49:33.21#ibcon#enter sib2, iclass 4, count 0 2006.173.18:49:33.21#ibcon#flushed, iclass 4, count 0 2006.173.18:49:33.21#ibcon#about to write, iclass 4, count 0 2006.173.18:49:33.21#ibcon#wrote, iclass 4, count 0 2006.173.18:49:33.21#ibcon#about to read 3, iclass 4, count 0 2006.173.18:49:33.25#ibcon#read 3, iclass 4, count 0 2006.173.18:49:33.25#ibcon#about to read 4, iclass 4, count 0 2006.173.18:49:33.25#ibcon#read 4, iclass 4, count 0 2006.173.18:49:33.25#ibcon#about to read 5, iclass 4, count 0 2006.173.18:49:33.25#ibcon#read 5, iclass 4, count 0 2006.173.18:49:33.25#ibcon#about to read 6, iclass 4, count 0 2006.173.18:49:33.25#ibcon#read 6, iclass 4, count 0 2006.173.18:49:33.25#ibcon#end of sib2, iclass 4, count 0 2006.173.18:49:33.25#ibcon#*after write, iclass 4, count 0 2006.173.18:49:33.25#ibcon#*before return 0, iclass 4, count 0 2006.173.18:49:33.25#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.18:49:33.25#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.18:49:33.25#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.18:49:33.25#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.18:49:33.25$vck44/vb=8,4 2006.173.18:49:33.25#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.18:49:33.25#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.18:49:33.25#ibcon#ireg 11 cls_cnt 2 2006.173.18:49:33.25#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.18:49:33.31#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.18:49:33.31#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.18:49:33.31#ibcon#enter wrdev, iclass 6, count 2 2006.173.18:49:33.31#ibcon#first serial, iclass 6, count 2 2006.173.18:49:33.31#ibcon#enter sib2, iclass 6, count 2 2006.173.18:49:33.31#ibcon#flushed, iclass 6, count 2 2006.173.18:49:33.31#ibcon#about to write, iclass 6, count 2 2006.173.18:49:33.31#ibcon#wrote, iclass 6, count 2 2006.173.18:49:33.31#ibcon#about to read 3, iclass 6, count 2 2006.173.18:49:33.33#ibcon#read 3, iclass 6, count 2 2006.173.18:49:33.33#ibcon#about to read 4, iclass 6, count 2 2006.173.18:49:33.33#ibcon#read 4, iclass 6, count 2 2006.173.18:49:33.33#ibcon#about to read 5, iclass 6, count 2 2006.173.18:49:33.33#ibcon#read 5, iclass 6, count 2 2006.173.18:49:33.33#ibcon#about to read 6, iclass 6, count 2 2006.173.18:49:33.33#ibcon#read 6, iclass 6, count 2 2006.173.18:49:33.33#ibcon#end of sib2, iclass 6, count 2 2006.173.18:49:33.33#ibcon#*mode == 0, iclass 6, count 2 2006.173.18:49:33.33#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.18:49:33.33#ibcon#[27=AT08-04\r\n] 2006.173.18:49:33.33#ibcon#*before write, iclass 6, count 2 2006.173.18:49:33.33#ibcon#enter sib2, iclass 6, count 2 2006.173.18:49:33.33#ibcon#flushed, iclass 6, count 2 2006.173.18:49:33.33#ibcon#about to write, iclass 6, count 2 2006.173.18:49:33.33#ibcon#wrote, iclass 6, count 2 2006.173.18:49:33.33#ibcon#about to read 3, iclass 6, count 2 2006.173.18:49:33.36#ibcon#read 3, iclass 6, count 2 2006.173.18:49:33.36#ibcon#about to read 4, iclass 6, count 2 2006.173.18:49:33.36#ibcon#read 4, iclass 6, count 2 2006.173.18:49:33.36#ibcon#about to read 5, iclass 6, count 2 2006.173.18:49:33.36#ibcon#read 5, iclass 6, count 2 2006.173.18:49:33.36#ibcon#about to read 6, iclass 6, count 2 2006.173.18:49:33.36#ibcon#read 6, iclass 6, count 2 2006.173.18:49:33.36#ibcon#end of sib2, iclass 6, count 2 2006.173.18:49:33.36#ibcon#*after write, iclass 6, count 2 2006.173.18:49:33.36#ibcon#*before return 0, iclass 6, count 2 2006.173.18:49:33.36#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.18:49:33.36#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.18:49:33.36#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.18:49:33.36#ibcon#ireg 7 cls_cnt 0 2006.173.18:49:33.36#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.18:49:33.48#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.18:49:33.48#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.18:49:33.48#ibcon#enter wrdev, iclass 6, count 0 2006.173.18:49:33.48#ibcon#first serial, iclass 6, count 0 2006.173.18:49:33.48#ibcon#enter sib2, iclass 6, count 0 2006.173.18:49:33.48#ibcon#flushed, iclass 6, count 0 2006.173.18:49:33.48#ibcon#about to write, iclass 6, count 0 2006.173.18:49:33.48#ibcon#wrote, iclass 6, count 0 2006.173.18:49:33.48#ibcon#about to read 3, iclass 6, count 0 2006.173.18:49:33.50#ibcon#read 3, iclass 6, count 0 2006.173.18:49:33.50#ibcon#about to read 4, iclass 6, count 0 2006.173.18:49:33.50#ibcon#read 4, iclass 6, count 0 2006.173.18:49:33.50#ibcon#about to read 5, iclass 6, count 0 2006.173.18:49:33.50#ibcon#read 5, iclass 6, count 0 2006.173.18:49:33.50#ibcon#about to read 6, iclass 6, count 0 2006.173.18:49:33.50#ibcon#read 6, iclass 6, count 0 2006.173.18:49:33.50#ibcon#end of sib2, iclass 6, count 0 2006.173.18:49:33.50#ibcon#*mode == 0, iclass 6, count 0 2006.173.18:49:33.50#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.18:49:33.50#ibcon#[27=USB\r\n] 2006.173.18:49:33.50#ibcon#*before write, iclass 6, count 0 2006.173.18:49:33.50#ibcon#enter sib2, iclass 6, count 0 2006.173.18:49:33.50#ibcon#flushed, iclass 6, count 0 2006.173.18:49:33.50#ibcon#about to write, iclass 6, count 0 2006.173.18:49:33.50#ibcon#wrote, iclass 6, count 0 2006.173.18:49:33.50#ibcon#about to read 3, iclass 6, count 0 2006.173.18:49:33.53#ibcon#read 3, iclass 6, count 0 2006.173.18:49:33.53#ibcon#about to read 4, iclass 6, count 0 2006.173.18:49:33.53#ibcon#read 4, iclass 6, count 0 2006.173.18:49:33.53#ibcon#about to read 5, iclass 6, count 0 2006.173.18:49:33.53#ibcon#read 5, iclass 6, count 0 2006.173.18:49:33.53#ibcon#about to read 6, iclass 6, count 0 2006.173.18:49:33.53#ibcon#read 6, iclass 6, count 0 2006.173.18:49:33.53#ibcon#end of sib2, iclass 6, count 0 2006.173.18:49:33.53#ibcon#*after write, iclass 6, count 0 2006.173.18:49:33.53#ibcon#*before return 0, iclass 6, count 0 2006.173.18:49:33.53#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.18:49:33.53#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.18:49:33.53#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.18:49:33.53#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.18:49:33.53$vck44/vabw=wide 2006.173.18:49:33.53#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.18:49:33.53#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.18:49:33.53#ibcon#ireg 8 cls_cnt 0 2006.173.18:49:33.53#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.18:49:33.53#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.18:49:33.53#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.18:49:33.53#ibcon#enter wrdev, iclass 10, count 0 2006.173.18:49:33.53#ibcon#first serial, iclass 10, count 0 2006.173.18:49:33.53#ibcon#enter sib2, iclass 10, count 0 2006.173.18:49:33.53#ibcon#flushed, iclass 10, count 0 2006.173.18:49:33.53#ibcon#about to write, iclass 10, count 0 2006.173.18:49:33.53#ibcon#wrote, iclass 10, count 0 2006.173.18:49:33.53#ibcon#about to read 3, iclass 10, count 0 2006.173.18:49:33.55#ibcon#read 3, iclass 10, count 0 2006.173.18:49:33.55#ibcon#about to read 4, iclass 10, count 0 2006.173.18:49:33.55#ibcon#read 4, iclass 10, count 0 2006.173.18:49:33.55#ibcon#about to read 5, iclass 10, count 0 2006.173.18:49:33.55#ibcon#read 5, iclass 10, count 0 2006.173.18:49:33.55#ibcon#about to read 6, iclass 10, count 0 2006.173.18:49:33.55#ibcon#read 6, iclass 10, count 0 2006.173.18:49:33.55#ibcon#end of sib2, iclass 10, count 0 2006.173.18:49:33.55#ibcon#*mode == 0, iclass 10, count 0 2006.173.18:49:33.55#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.18:49:33.55#ibcon#[25=BW32\r\n] 2006.173.18:49:33.55#ibcon#*before write, iclass 10, count 0 2006.173.18:49:33.55#ibcon#enter sib2, iclass 10, count 0 2006.173.18:49:33.55#ibcon#flushed, iclass 10, count 0 2006.173.18:49:33.55#ibcon#about to write, iclass 10, count 0 2006.173.18:49:33.55#ibcon#wrote, iclass 10, count 0 2006.173.18:49:33.55#ibcon#about to read 3, iclass 10, count 0 2006.173.18:49:33.58#ibcon#read 3, iclass 10, count 0 2006.173.18:49:33.58#ibcon#about to read 4, iclass 10, count 0 2006.173.18:49:33.58#ibcon#read 4, iclass 10, count 0 2006.173.18:49:33.58#ibcon#about to read 5, iclass 10, count 0 2006.173.18:49:33.58#ibcon#read 5, iclass 10, count 0 2006.173.18:49:33.58#ibcon#about to read 6, iclass 10, count 0 2006.173.18:49:33.58#ibcon#read 6, iclass 10, count 0 2006.173.18:49:33.58#ibcon#end of sib2, iclass 10, count 0 2006.173.18:49:33.58#ibcon#*after write, iclass 10, count 0 2006.173.18:49:33.58#ibcon#*before return 0, iclass 10, count 0 2006.173.18:49:33.58#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.18:49:33.58#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.18:49:33.58#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.18:49:33.58#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.18:49:33.58$vck44/vbbw=wide 2006.173.18:49:33.58#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.18:49:33.58#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.18:49:33.58#ibcon#ireg 8 cls_cnt 0 2006.173.18:49:33.58#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.18:49:33.65#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.18:49:33.65#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.18:49:33.65#ibcon#enter wrdev, iclass 12, count 0 2006.173.18:49:33.65#ibcon#first serial, iclass 12, count 0 2006.173.18:49:33.65#ibcon#enter sib2, iclass 12, count 0 2006.173.18:49:33.65#ibcon#flushed, iclass 12, count 0 2006.173.18:49:33.65#ibcon#about to write, iclass 12, count 0 2006.173.18:49:33.65#ibcon#wrote, iclass 12, count 0 2006.173.18:49:33.65#ibcon#about to read 3, iclass 12, count 0 2006.173.18:49:33.67#ibcon#read 3, iclass 12, count 0 2006.173.18:49:33.67#ibcon#about to read 4, iclass 12, count 0 2006.173.18:49:33.67#ibcon#read 4, iclass 12, count 0 2006.173.18:49:33.67#ibcon#about to read 5, iclass 12, count 0 2006.173.18:49:33.67#ibcon#read 5, iclass 12, count 0 2006.173.18:49:33.67#ibcon#about to read 6, iclass 12, count 0 2006.173.18:49:33.67#ibcon#read 6, iclass 12, count 0 2006.173.18:49:33.67#ibcon#end of sib2, iclass 12, count 0 2006.173.18:49:33.67#ibcon#*mode == 0, iclass 12, count 0 2006.173.18:49:33.67#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.18:49:33.67#ibcon#[27=BW32\r\n] 2006.173.18:49:33.67#ibcon#*before write, iclass 12, count 0 2006.173.18:49:33.67#ibcon#enter sib2, iclass 12, count 0 2006.173.18:49:33.67#ibcon#flushed, iclass 12, count 0 2006.173.18:49:33.67#ibcon#about to write, iclass 12, count 0 2006.173.18:49:33.67#ibcon#wrote, iclass 12, count 0 2006.173.18:49:33.67#ibcon#about to read 3, iclass 12, count 0 2006.173.18:49:33.70#ibcon#read 3, iclass 12, count 0 2006.173.18:49:33.70#ibcon#about to read 4, iclass 12, count 0 2006.173.18:49:33.70#ibcon#read 4, iclass 12, count 0 2006.173.18:49:33.70#ibcon#about to read 5, iclass 12, count 0 2006.173.18:49:33.70#ibcon#read 5, iclass 12, count 0 2006.173.18:49:33.70#ibcon#about to read 6, iclass 12, count 0 2006.173.18:49:33.70#ibcon#read 6, iclass 12, count 0 2006.173.18:49:33.70#ibcon#end of sib2, iclass 12, count 0 2006.173.18:49:33.70#ibcon#*after write, iclass 12, count 0 2006.173.18:49:33.70#ibcon#*before return 0, iclass 12, count 0 2006.173.18:49:33.70#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.18:49:33.70#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.18:49:33.70#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.18:49:33.70#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.18:49:33.70$setupk4/ifdk4 2006.173.18:49:33.70$ifdk4/lo= 2006.173.18:49:33.70$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.18:49:33.70$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.18:49:33.70$ifdk4/patch= 2006.173.18:49:33.70$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.18:49:33.70$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.18:49:33.70$setupk4/!*+20s 2006.173.18:49:36.89#abcon#<5=/14 0.8 1.5 19.671001002.4\r\n> 2006.173.18:49:36.91#abcon#{5=INTERFACE CLEAR} 2006.173.18:49:36.97#abcon#[5=S1D000X0/0*\r\n] 2006.173.18:49:40.14#trakl#Source acquired 2006.173.18:49:41.14#flagr#flagr/antenna,acquired 2006.173.18:49:47.06#abcon#<5=/14 0.8 1.5 19.671001002.4\r\n> 2006.173.18:49:47.08#abcon#{5=INTERFACE CLEAR} 2006.173.18:49:47.14#abcon#[5=S1D000X0/0*\r\n] 2006.173.18:49:48.22$setupk4/"tpicd 2006.173.18:49:48.22$setupk4/echo=off 2006.173.18:49:48.22$setupk4/xlog=off 2006.173.18:49:48.22:!2006.173.18:49:45 2006.173.18:49:48.22:preob 2006.173.18:49:49.14/onsource/TRACKING 2006.173.18:49:49.14:!2006.173.18:49:55 2006.173.18:49:55.00:"tape 2006.173.18:49:55.00:"st=record 2006.173.18:49:55.00:data_valid=on 2006.173.18:49:55.00:midob 2006.173.18:49:55.14/onsource/TRACKING 2006.173.18:49:55.14/wx/19.67,1002.4,100 2006.173.18:49:55.32/cable/+6.5143E-03 2006.173.18:49:56.41/va/01,07,usb,yes,36,39 2006.173.18:49:56.41/va/02,06,usb,yes,36,37 2006.173.18:49:56.41/va/03,05,usb,yes,46,48 2006.173.18:49:56.41/va/04,06,usb,yes,37,39 2006.173.18:49:56.41/va/05,04,usb,yes,29,29 2006.173.18:49:56.41/va/06,03,usb,yes,40,40 2006.173.18:49:56.41/va/07,04,usb,yes,33,34 2006.173.18:49:56.41/va/08,04,usb,yes,28,33 2006.173.18:49:56.64/valo/01,524.99,yes,locked 2006.173.18:49:56.64/valo/02,534.99,yes,locked 2006.173.18:49:56.64/valo/03,564.99,yes,locked 2006.173.18:49:56.64/valo/04,624.99,yes,locked 2006.173.18:49:56.64/valo/05,734.99,yes,locked 2006.173.18:49:56.64/valo/06,814.99,yes,locked 2006.173.18:49:56.64/valo/07,864.99,yes,locked 2006.173.18:49:56.64/valo/08,884.99,yes,locked 2006.173.18:49:57.73/vb/01,04,usb,yes,29,27 2006.173.18:49:57.73/vb/02,04,usb,yes,32,32 2006.173.18:49:57.73/vb/03,04,usb,yes,29,32 2006.173.18:49:57.73/vb/04,04,usb,yes,33,32 2006.173.18:49:57.73/vb/05,04,usb,yes,26,28 2006.173.18:49:57.73/vb/06,04,usb,yes,30,26 2006.173.18:49:57.73/vb/07,04,usb,yes,30,30 2006.173.18:49:57.73/vb/08,04,usb,yes,27,31 2006.173.18:49:57.96/vblo/01,629.99,yes,locked 2006.173.18:49:57.96/vblo/02,634.99,yes,locked 2006.173.18:49:57.96/vblo/03,649.99,yes,locked 2006.173.18:49:57.96/vblo/04,679.99,yes,locked 2006.173.18:49:57.96/vblo/05,709.99,yes,locked 2006.173.18:49:57.96/vblo/06,719.99,yes,locked 2006.173.18:49:57.96/vblo/07,734.99,yes,locked 2006.173.18:49:57.96/vblo/08,744.99,yes,locked 2006.173.18:49:58.11/vabw/8 2006.173.18:49:58.26/vbbw/8 2006.173.18:49:58.35/xfe/off,on,15.7 2006.173.18:49:58.73/ifatt/23,28,28,28 2006.173.18:49:59.07/fmout-gps/S +3.93E-07 2006.173.18:49:59.11:!2006.173.18:55:45 2006.173.18:55:45.00:data_valid=off 2006.173.18:55:45.00:"et 2006.173.18:55:45.00:!+3s 2006.173.18:55:48.01:"tape 2006.173.18:55:48.01:postob 2006.173.18:55:48.13/cable/+6.5145E-03 2006.173.18:55:48.13/wx/19.63,1002.5,100 2006.173.18:55:49.08/fmout-gps/S +3.91E-07 2006.173.18:55:49.08:scan_name=173-1900,jd0606,100 2006.173.18:55:49.08:source=cta26,033930.94,-014635.8,2000.0,ccw 2006.173.18:55:49.13#flagr#flagr/antenna,new-source 2006.173.18:55:50.13:checkk5 2006.173.18:55:50.53/chk_autoobs//k5ts1/ autoobs is running! 2006.173.18:55:50.92/chk_autoobs//k5ts2/ autoobs is running! 2006.173.18:55:51.33/chk_autoobs//k5ts3/ autoobs is running! 2006.173.18:55:51.73/chk_autoobs//k5ts4/ autoobs is running! 2006.173.18:55:52.13/chk_obsdata//k5ts1/T1731849??a.dat file size is correct (nominal:1400MB, actual:1396MB). 2006.173.18:55:52.54/chk_obsdata//k5ts2/T1731849??b.dat file size is correct (nominal:1400MB, actual:1396MB). 2006.173.18:55:52.94/chk_obsdata//k5ts3/T1731849??c.dat file size is correct (nominal:1400MB, actual:1396MB). 2006.173.18:55:53.33/chk_obsdata//k5ts4/T1731849??d.dat file size is correct (nominal:1400MB, actual:1396MB). 2006.173.18:55:54.05/k5log//k5ts1_log_newline 2006.173.18:55:54.73/k5log//k5ts2_log_newline 2006.173.18:55:55.46/k5log//k5ts3_log_newline 2006.173.18:55:56.17/k5log//k5ts4_log_newline 2006.173.18:55:56.20/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.18:55:56.20:setupk4=1 2006.173.18:55:56.20$setupk4/echo=on 2006.173.18:55:56.20$setupk4/pcalon 2006.173.18:55:56.20$pcalon/"no phase cal control is implemented here 2006.173.18:55:56.20$setupk4/"tpicd=stop 2006.173.18:55:56.20$setupk4/"rec=synch_on 2006.173.18:55:56.20$setupk4/"rec_mode=128 2006.173.18:55:56.20$setupk4/!* 2006.173.18:55:56.20$setupk4/recpk4 2006.173.18:55:56.20$recpk4/recpatch= 2006.173.18:55:56.20$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.18:55:56.20$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.18:55:56.20$setupk4/vck44 2006.173.18:55:56.20$vck44/valo=1,524.99 2006.173.18:55:56.20#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.18:55:56.20#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.18:55:56.20#ibcon#ireg 17 cls_cnt 0 2006.173.18:55:56.20#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.18:55:56.20#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.18:55:56.20#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.18:55:56.20#ibcon#enter wrdev, iclass 25, count 0 2006.173.18:55:56.20#ibcon#first serial, iclass 25, count 0 2006.173.18:55:56.20#ibcon#enter sib2, iclass 25, count 0 2006.173.18:55:56.20#ibcon#flushed, iclass 25, count 0 2006.173.18:55:56.20#ibcon#about to write, iclass 25, count 0 2006.173.18:55:56.20#ibcon#wrote, iclass 25, count 0 2006.173.18:55:56.20#ibcon#about to read 3, iclass 25, count 0 2006.173.18:55:56.22#ibcon#read 3, iclass 25, count 0 2006.173.18:55:56.22#ibcon#about to read 4, iclass 25, count 0 2006.173.18:55:56.22#ibcon#read 4, iclass 25, count 0 2006.173.18:55:56.22#ibcon#about to read 5, iclass 25, count 0 2006.173.18:55:56.22#ibcon#read 5, iclass 25, count 0 2006.173.18:55:56.22#ibcon#about to read 6, iclass 25, count 0 2006.173.18:55:56.22#ibcon#read 6, iclass 25, count 0 2006.173.18:55:56.22#ibcon#end of sib2, iclass 25, count 0 2006.173.18:55:56.22#ibcon#*mode == 0, iclass 25, count 0 2006.173.18:55:56.22#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.18:55:56.22#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.18:55:56.22#ibcon#*before write, iclass 25, count 0 2006.173.18:55:56.22#ibcon#enter sib2, iclass 25, count 0 2006.173.18:55:56.22#ibcon#flushed, iclass 25, count 0 2006.173.18:55:56.22#ibcon#about to write, iclass 25, count 0 2006.173.18:55:56.22#ibcon#wrote, iclass 25, count 0 2006.173.18:55:56.22#ibcon#about to read 3, iclass 25, count 0 2006.173.18:55:56.27#ibcon#read 3, iclass 25, count 0 2006.173.18:55:56.27#ibcon#about to read 4, iclass 25, count 0 2006.173.18:55:56.27#ibcon#read 4, iclass 25, count 0 2006.173.18:55:56.27#ibcon#about to read 5, iclass 25, count 0 2006.173.18:55:56.27#ibcon#read 5, iclass 25, count 0 2006.173.18:55:56.27#ibcon#about to read 6, iclass 25, count 0 2006.173.18:55:56.27#ibcon#read 6, iclass 25, count 0 2006.173.18:55:56.27#ibcon#end of sib2, iclass 25, count 0 2006.173.18:55:56.27#ibcon#*after write, iclass 25, count 0 2006.173.18:55:56.27#ibcon#*before return 0, iclass 25, count 0 2006.173.18:55:56.27#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.18:55:56.27#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.18:55:56.27#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.18:55:56.27#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.18:55:56.27$vck44/va=1,7 2006.173.18:55:56.27#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.18:55:56.27#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.18:55:56.27#ibcon#ireg 11 cls_cnt 2 2006.173.18:55:56.27#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.18:55:56.27#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.18:55:56.27#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.18:55:56.27#ibcon#enter wrdev, iclass 27, count 2 2006.173.18:55:56.27#ibcon#first serial, iclass 27, count 2 2006.173.18:55:56.27#ibcon#enter sib2, iclass 27, count 2 2006.173.18:55:56.27#ibcon#flushed, iclass 27, count 2 2006.173.18:55:56.27#ibcon#about to write, iclass 27, count 2 2006.173.18:55:56.27#ibcon#wrote, iclass 27, count 2 2006.173.18:55:56.27#ibcon#about to read 3, iclass 27, count 2 2006.173.18:55:56.29#ibcon#read 3, iclass 27, count 2 2006.173.18:55:56.29#ibcon#about to read 4, iclass 27, count 2 2006.173.18:55:56.29#ibcon#read 4, iclass 27, count 2 2006.173.18:55:56.29#ibcon#about to read 5, iclass 27, count 2 2006.173.18:55:56.29#ibcon#read 5, iclass 27, count 2 2006.173.18:55:56.29#ibcon#about to read 6, iclass 27, count 2 2006.173.18:55:56.29#ibcon#read 6, iclass 27, count 2 2006.173.18:55:56.29#ibcon#end of sib2, iclass 27, count 2 2006.173.18:55:56.29#ibcon#*mode == 0, iclass 27, count 2 2006.173.18:55:56.29#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.18:55:56.29#ibcon#[25=AT01-07\r\n] 2006.173.18:55:56.29#ibcon#*before write, iclass 27, count 2 2006.173.18:55:56.29#ibcon#enter sib2, iclass 27, count 2 2006.173.18:55:56.29#ibcon#flushed, iclass 27, count 2 2006.173.18:55:56.29#ibcon#about to write, iclass 27, count 2 2006.173.18:55:56.29#ibcon#wrote, iclass 27, count 2 2006.173.18:55:56.29#ibcon#about to read 3, iclass 27, count 2 2006.173.18:55:56.32#ibcon#read 3, iclass 27, count 2 2006.173.18:55:56.32#ibcon#about to read 4, iclass 27, count 2 2006.173.18:55:56.32#ibcon#read 4, iclass 27, count 2 2006.173.18:55:56.32#ibcon#about to read 5, iclass 27, count 2 2006.173.18:55:56.32#ibcon#read 5, iclass 27, count 2 2006.173.18:55:56.32#ibcon#about to read 6, iclass 27, count 2 2006.173.18:55:56.32#ibcon#read 6, iclass 27, count 2 2006.173.18:55:56.32#ibcon#end of sib2, iclass 27, count 2 2006.173.18:55:56.32#ibcon#*after write, iclass 27, count 2 2006.173.18:55:56.32#ibcon#*before return 0, iclass 27, count 2 2006.173.18:55:56.32#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.18:55:56.32#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.18:55:56.32#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.18:55:56.32#ibcon#ireg 7 cls_cnt 0 2006.173.18:55:56.32#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.18:55:56.44#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.18:55:56.44#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.18:55:56.44#ibcon#enter wrdev, iclass 27, count 0 2006.173.18:55:56.44#ibcon#first serial, iclass 27, count 0 2006.173.18:55:56.44#ibcon#enter sib2, iclass 27, count 0 2006.173.18:55:56.44#ibcon#flushed, iclass 27, count 0 2006.173.18:55:56.44#ibcon#about to write, iclass 27, count 0 2006.173.18:55:56.44#ibcon#wrote, iclass 27, count 0 2006.173.18:55:56.44#ibcon#about to read 3, iclass 27, count 0 2006.173.18:55:56.46#ibcon#read 3, iclass 27, count 0 2006.173.18:55:56.46#ibcon#about to read 4, iclass 27, count 0 2006.173.18:55:56.46#ibcon#read 4, iclass 27, count 0 2006.173.18:55:56.46#ibcon#about to read 5, iclass 27, count 0 2006.173.18:55:56.46#ibcon#read 5, iclass 27, count 0 2006.173.18:55:56.46#ibcon#about to read 6, iclass 27, count 0 2006.173.18:55:56.46#ibcon#read 6, iclass 27, count 0 2006.173.18:55:56.46#ibcon#end of sib2, iclass 27, count 0 2006.173.18:55:56.46#ibcon#*mode == 0, iclass 27, count 0 2006.173.18:55:56.46#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.18:55:56.46#ibcon#[25=USB\r\n] 2006.173.18:55:56.46#ibcon#*before write, iclass 27, count 0 2006.173.18:55:56.46#ibcon#enter sib2, iclass 27, count 0 2006.173.18:55:56.46#ibcon#flushed, iclass 27, count 0 2006.173.18:55:56.46#ibcon#about to write, iclass 27, count 0 2006.173.18:55:56.46#ibcon#wrote, iclass 27, count 0 2006.173.18:55:56.46#ibcon#about to read 3, iclass 27, count 0 2006.173.18:55:56.49#ibcon#read 3, iclass 27, count 0 2006.173.18:55:56.49#ibcon#about to read 4, iclass 27, count 0 2006.173.18:55:56.49#ibcon#read 4, iclass 27, count 0 2006.173.18:55:56.49#ibcon#about to read 5, iclass 27, count 0 2006.173.18:55:56.49#ibcon#read 5, iclass 27, count 0 2006.173.18:55:56.49#ibcon#about to read 6, iclass 27, count 0 2006.173.18:55:56.49#ibcon#read 6, iclass 27, count 0 2006.173.18:55:56.49#ibcon#end of sib2, iclass 27, count 0 2006.173.18:55:56.49#ibcon#*after write, iclass 27, count 0 2006.173.18:55:56.49#ibcon#*before return 0, iclass 27, count 0 2006.173.18:55:56.49#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.18:55:56.49#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.18:55:56.49#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.18:55:56.49#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.18:55:56.49$vck44/valo=2,534.99 2006.173.18:55:56.49#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.18:55:56.49#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.18:55:56.49#ibcon#ireg 17 cls_cnt 0 2006.173.18:55:56.49#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.18:55:56.49#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.18:55:56.49#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.18:55:56.49#ibcon#enter wrdev, iclass 29, count 0 2006.173.18:55:56.49#ibcon#first serial, iclass 29, count 0 2006.173.18:55:56.49#ibcon#enter sib2, iclass 29, count 0 2006.173.18:55:56.49#ibcon#flushed, iclass 29, count 0 2006.173.18:55:56.49#ibcon#about to write, iclass 29, count 0 2006.173.18:55:56.49#ibcon#wrote, iclass 29, count 0 2006.173.18:55:56.49#ibcon#about to read 3, iclass 29, count 0 2006.173.18:55:56.51#ibcon#read 3, iclass 29, count 0 2006.173.18:55:56.51#ibcon#about to read 4, iclass 29, count 0 2006.173.18:55:56.51#ibcon#read 4, iclass 29, count 0 2006.173.18:55:56.51#ibcon#about to read 5, iclass 29, count 0 2006.173.18:55:56.51#ibcon#read 5, iclass 29, count 0 2006.173.18:55:56.51#ibcon#about to read 6, iclass 29, count 0 2006.173.18:55:56.51#ibcon#read 6, iclass 29, count 0 2006.173.18:55:56.51#ibcon#end of sib2, iclass 29, count 0 2006.173.18:55:56.51#ibcon#*mode == 0, iclass 29, count 0 2006.173.18:55:56.51#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.18:55:56.51#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.18:55:56.51#ibcon#*before write, iclass 29, count 0 2006.173.18:55:56.51#ibcon#enter sib2, iclass 29, count 0 2006.173.18:55:56.51#ibcon#flushed, iclass 29, count 0 2006.173.18:55:56.51#ibcon#about to write, iclass 29, count 0 2006.173.18:55:56.51#ibcon#wrote, iclass 29, count 0 2006.173.18:55:56.51#ibcon#about to read 3, iclass 29, count 0 2006.173.18:55:56.55#ibcon#read 3, iclass 29, count 0 2006.173.18:55:56.55#ibcon#about to read 4, iclass 29, count 0 2006.173.18:55:56.55#ibcon#read 4, iclass 29, count 0 2006.173.18:55:56.55#ibcon#about to read 5, iclass 29, count 0 2006.173.18:55:56.55#ibcon#read 5, iclass 29, count 0 2006.173.18:55:56.55#ibcon#about to read 6, iclass 29, count 0 2006.173.18:55:56.55#ibcon#read 6, iclass 29, count 0 2006.173.18:55:56.55#ibcon#end of sib2, iclass 29, count 0 2006.173.18:55:56.55#ibcon#*after write, iclass 29, count 0 2006.173.18:55:56.55#ibcon#*before return 0, iclass 29, count 0 2006.173.18:55:56.55#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.18:55:56.55#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.18:55:56.55#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.18:55:56.55#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.18:55:56.55$vck44/va=2,6 2006.173.18:55:56.55#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.18:55:56.55#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.18:55:56.55#ibcon#ireg 11 cls_cnt 2 2006.173.18:55:56.55#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.18:55:56.61#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.18:55:56.61#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.18:55:56.61#ibcon#enter wrdev, iclass 31, count 2 2006.173.18:55:56.61#ibcon#first serial, iclass 31, count 2 2006.173.18:55:56.61#ibcon#enter sib2, iclass 31, count 2 2006.173.18:55:56.61#ibcon#flushed, iclass 31, count 2 2006.173.18:55:56.61#ibcon#about to write, iclass 31, count 2 2006.173.18:55:56.61#ibcon#wrote, iclass 31, count 2 2006.173.18:55:56.61#ibcon#about to read 3, iclass 31, count 2 2006.173.18:55:56.63#ibcon#read 3, iclass 31, count 2 2006.173.18:55:56.63#ibcon#about to read 4, iclass 31, count 2 2006.173.18:55:56.63#ibcon#read 4, iclass 31, count 2 2006.173.18:55:56.63#ibcon#about to read 5, iclass 31, count 2 2006.173.18:55:56.63#ibcon#read 5, iclass 31, count 2 2006.173.18:55:56.63#ibcon#about to read 6, iclass 31, count 2 2006.173.18:55:56.63#ibcon#read 6, iclass 31, count 2 2006.173.18:55:56.63#ibcon#end of sib2, iclass 31, count 2 2006.173.18:55:56.63#ibcon#*mode == 0, iclass 31, count 2 2006.173.18:55:56.63#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.18:55:56.63#ibcon#[25=AT02-06\r\n] 2006.173.18:55:56.63#ibcon#*before write, iclass 31, count 2 2006.173.18:55:56.63#ibcon#enter sib2, iclass 31, count 2 2006.173.18:55:56.63#ibcon#flushed, iclass 31, count 2 2006.173.18:55:56.63#ibcon#about to write, iclass 31, count 2 2006.173.18:55:56.63#ibcon#wrote, iclass 31, count 2 2006.173.18:55:56.63#ibcon#about to read 3, iclass 31, count 2 2006.173.18:55:56.66#ibcon#read 3, iclass 31, count 2 2006.173.18:55:56.66#ibcon#about to read 4, iclass 31, count 2 2006.173.18:55:56.66#ibcon#read 4, iclass 31, count 2 2006.173.18:55:56.66#ibcon#about to read 5, iclass 31, count 2 2006.173.18:55:56.66#ibcon#read 5, iclass 31, count 2 2006.173.18:55:56.66#ibcon#about to read 6, iclass 31, count 2 2006.173.18:55:56.66#ibcon#read 6, iclass 31, count 2 2006.173.18:55:56.66#ibcon#end of sib2, iclass 31, count 2 2006.173.18:55:56.66#ibcon#*after write, iclass 31, count 2 2006.173.18:55:56.66#ibcon#*before return 0, iclass 31, count 2 2006.173.18:55:56.66#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.18:55:56.66#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.18:55:56.66#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.18:55:56.66#ibcon#ireg 7 cls_cnt 0 2006.173.18:55:56.66#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.18:55:56.78#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.18:55:56.78#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.18:55:56.78#ibcon#enter wrdev, iclass 31, count 0 2006.173.18:55:56.78#ibcon#first serial, iclass 31, count 0 2006.173.18:55:56.78#ibcon#enter sib2, iclass 31, count 0 2006.173.18:55:56.78#ibcon#flushed, iclass 31, count 0 2006.173.18:55:56.78#ibcon#about to write, iclass 31, count 0 2006.173.18:55:56.78#ibcon#wrote, iclass 31, count 0 2006.173.18:55:56.78#ibcon#about to read 3, iclass 31, count 0 2006.173.18:55:56.80#ibcon#read 3, iclass 31, count 0 2006.173.18:55:56.80#ibcon#about to read 4, iclass 31, count 0 2006.173.18:55:56.80#ibcon#read 4, iclass 31, count 0 2006.173.18:55:56.80#ibcon#about to read 5, iclass 31, count 0 2006.173.18:55:56.80#ibcon#read 5, iclass 31, count 0 2006.173.18:55:56.80#ibcon#about to read 6, iclass 31, count 0 2006.173.18:55:56.80#ibcon#read 6, iclass 31, count 0 2006.173.18:55:56.80#ibcon#end of sib2, iclass 31, count 0 2006.173.18:55:56.80#ibcon#*mode == 0, iclass 31, count 0 2006.173.18:55:56.80#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.18:55:56.80#ibcon#[25=USB\r\n] 2006.173.18:55:56.80#ibcon#*before write, iclass 31, count 0 2006.173.18:55:56.80#ibcon#enter sib2, iclass 31, count 0 2006.173.18:55:56.80#ibcon#flushed, iclass 31, count 0 2006.173.18:55:56.80#ibcon#about to write, iclass 31, count 0 2006.173.18:55:56.80#ibcon#wrote, iclass 31, count 0 2006.173.18:55:56.80#ibcon#about to read 3, iclass 31, count 0 2006.173.18:55:56.83#ibcon#read 3, iclass 31, count 0 2006.173.18:55:56.83#ibcon#about to read 4, iclass 31, count 0 2006.173.18:55:56.83#ibcon#read 4, iclass 31, count 0 2006.173.18:55:56.83#ibcon#about to read 5, iclass 31, count 0 2006.173.18:55:56.83#ibcon#read 5, iclass 31, count 0 2006.173.18:55:56.83#ibcon#about to read 6, iclass 31, count 0 2006.173.18:55:56.83#ibcon#read 6, iclass 31, count 0 2006.173.18:55:56.83#ibcon#end of sib2, iclass 31, count 0 2006.173.18:55:56.83#ibcon#*after write, iclass 31, count 0 2006.173.18:55:56.83#ibcon#*before return 0, iclass 31, count 0 2006.173.18:55:56.83#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.18:55:56.83#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.18:55:56.83#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.18:55:56.83#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.18:55:56.83$vck44/valo=3,564.99 2006.173.18:55:56.83#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.18:55:56.83#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.18:55:56.83#ibcon#ireg 17 cls_cnt 0 2006.173.18:55:56.83#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.18:55:56.83#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.18:55:56.83#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.18:55:56.83#ibcon#enter wrdev, iclass 33, count 0 2006.173.18:55:56.83#ibcon#first serial, iclass 33, count 0 2006.173.18:55:56.83#ibcon#enter sib2, iclass 33, count 0 2006.173.18:55:56.83#ibcon#flushed, iclass 33, count 0 2006.173.18:55:56.83#ibcon#about to write, iclass 33, count 0 2006.173.18:55:56.83#ibcon#wrote, iclass 33, count 0 2006.173.18:55:56.83#ibcon#about to read 3, iclass 33, count 0 2006.173.18:55:56.85#ibcon#read 3, iclass 33, count 0 2006.173.18:55:56.85#ibcon#about to read 4, iclass 33, count 0 2006.173.18:55:56.85#ibcon#read 4, iclass 33, count 0 2006.173.18:55:56.85#ibcon#about to read 5, iclass 33, count 0 2006.173.18:55:56.85#ibcon#read 5, iclass 33, count 0 2006.173.18:55:56.85#ibcon#about to read 6, iclass 33, count 0 2006.173.18:55:56.85#ibcon#read 6, iclass 33, count 0 2006.173.18:55:56.85#ibcon#end of sib2, iclass 33, count 0 2006.173.18:55:56.85#ibcon#*mode == 0, iclass 33, count 0 2006.173.18:55:56.85#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.18:55:56.85#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.18:55:56.85#ibcon#*before write, iclass 33, count 0 2006.173.18:55:56.85#ibcon#enter sib2, iclass 33, count 0 2006.173.18:55:56.85#ibcon#flushed, iclass 33, count 0 2006.173.18:55:56.85#ibcon#about to write, iclass 33, count 0 2006.173.18:55:56.85#ibcon#wrote, iclass 33, count 0 2006.173.18:55:56.85#ibcon#about to read 3, iclass 33, count 0 2006.173.18:55:56.89#ibcon#read 3, iclass 33, count 0 2006.173.18:55:56.89#ibcon#about to read 4, iclass 33, count 0 2006.173.18:55:56.89#ibcon#read 4, iclass 33, count 0 2006.173.18:55:56.89#ibcon#about to read 5, iclass 33, count 0 2006.173.18:55:56.89#ibcon#read 5, iclass 33, count 0 2006.173.18:55:56.89#ibcon#about to read 6, iclass 33, count 0 2006.173.18:55:56.89#ibcon#read 6, iclass 33, count 0 2006.173.18:55:56.89#ibcon#end of sib2, iclass 33, count 0 2006.173.18:55:56.89#ibcon#*after write, iclass 33, count 0 2006.173.18:55:56.89#ibcon#*before return 0, iclass 33, count 0 2006.173.18:55:56.89#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.18:55:56.89#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.18:55:56.89#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.18:55:56.89#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.18:55:56.89$vck44/va=3,5 2006.173.18:55:56.89#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.18:55:56.89#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.18:55:56.89#ibcon#ireg 11 cls_cnt 2 2006.173.18:55:56.89#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.18:55:56.95#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.18:55:56.95#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.18:55:56.95#ibcon#enter wrdev, iclass 35, count 2 2006.173.18:55:56.95#ibcon#first serial, iclass 35, count 2 2006.173.18:55:56.95#ibcon#enter sib2, iclass 35, count 2 2006.173.18:55:56.95#ibcon#flushed, iclass 35, count 2 2006.173.18:55:56.95#ibcon#about to write, iclass 35, count 2 2006.173.18:55:56.95#ibcon#wrote, iclass 35, count 2 2006.173.18:55:56.95#ibcon#about to read 3, iclass 35, count 2 2006.173.18:55:56.97#ibcon#read 3, iclass 35, count 2 2006.173.18:55:56.97#ibcon#about to read 4, iclass 35, count 2 2006.173.18:55:56.97#ibcon#read 4, iclass 35, count 2 2006.173.18:55:56.97#ibcon#about to read 5, iclass 35, count 2 2006.173.18:55:56.97#ibcon#read 5, iclass 35, count 2 2006.173.18:55:56.97#ibcon#about to read 6, iclass 35, count 2 2006.173.18:55:56.97#ibcon#read 6, iclass 35, count 2 2006.173.18:55:56.97#ibcon#end of sib2, iclass 35, count 2 2006.173.18:55:56.97#ibcon#*mode == 0, iclass 35, count 2 2006.173.18:55:56.97#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.18:55:56.97#ibcon#[25=AT03-05\r\n] 2006.173.18:55:56.97#ibcon#*before write, iclass 35, count 2 2006.173.18:55:56.97#ibcon#enter sib2, iclass 35, count 2 2006.173.18:55:56.97#ibcon#flushed, iclass 35, count 2 2006.173.18:55:56.97#ibcon#about to write, iclass 35, count 2 2006.173.18:55:56.97#ibcon#wrote, iclass 35, count 2 2006.173.18:55:56.97#ibcon#about to read 3, iclass 35, count 2 2006.173.18:55:57.00#ibcon#read 3, iclass 35, count 2 2006.173.18:55:57.00#ibcon#about to read 4, iclass 35, count 2 2006.173.18:55:57.00#ibcon#read 4, iclass 35, count 2 2006.173.18:55:57.00#ibcon#about to read 5, iclass 35, count 2 2006.173.18:55:57.00#ibcon#read 5, iclass 35, count 2 2006.173.18:55:57.00#ibcon#about to read 6, iclass 35, count 2 2006.173.18:55:57.00#ibcon#read 6, iclass 35, count 2 2006.173.18:55:57.00#ibcon#end of sib2, iclass 35, count 2 2006.173.18:55:57.00#ibcon#*after write, iclass 35, count 2 2006.173.18:55:57.00#ibcon#*before return 0, iclass 35, count 2 2006.173.18:55:57.00#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.18:55:57.00#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.18:55:57.00#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.18:55:57.00#ibcon#ireg 7 cls_cnt 0 2006.173.18:55:57.00#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.18:55:57.12#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.18:55:57.12#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.18:55:57.12#ibcon#enter wrdev, iclass 35, count 0 2006.173.18:55:57.12#ibcon#first serial, iclass 35, count 0 2006.173.18:55:57.12#ibcon#enter sib2, iclass 35, count 0 2006.173.18:55:57.12#ibcon#flushed, iclass 35, count 0 2006.173.18:55:57.12#ibcon#about to write, iclass 35, count 0 2006.173.18:55:57.12#ibcon#wrote, iclass 35, count 0 2006.173.18:55:57.12#ibcon#about to read 3, iclass 35, count 0 2006.173.18:55:57.14#ibcon#read 3, iclass 35, count 0 2006.173.18:55:57.14#ibcon#about to read 4, iclass 35, count 0 2006.173.18:55:57.14#ibcon#read 4, iclass 35, count 0 2006.173.18:55:57.14#ibcon#about to read 5, iclass 35, count 0 2006.173.18:55:57.14#ibcon#read 5, iclass 35, count 0 2006.173.18:55:57.14#ibcon#about to read 6, iclass 35, count 0 2006.173.18:55:57.14#ibcon#read 6, iclass 35, count 0 2006.173.18:55:57.14#ibcon#end of sib2, iclass 35, count 0 2006.173.18:55:57.14#ibcon#*mode == 0, iclass 35, count 0 2006.173.18:55:57.14#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.18:55:57.14#ibcon#[25=USB\r\n] 2006.173.18:55:57.14#ibcon#*before write, iclass 35, count 0 2006.173.18:55:57.14#ibcon#enter sib2, iclass 35, count 0 2006.173.18:55:57.14#ibcon#flushed, iclass 35, count 0 2006.173.18:55:57.14#ibcon#about to write, iclass 35, count 0 2006.173.18:55:57.14#ibcon#wrote, iclass 35, count 0 2006.173.18:55:57.14#ibcon#about to read 3, iclass 35, count 0 2006.173.18:55:57.17#ibcon#read 3, iclass 35, count 0 2006.173.18:55:57.17#ibcon#about to read 4, iclass 35, count 0 2006.173.18:55:57.17#ibcon#read 4, iclass 35, count 0 2006.173.18:55:57.17#ibcon#about to read 5, iclass 35, count 0 2006.173.18:55:57.17#ibcon#read 5, iclass 35, count 0 2006.173.18:55:57.17#ibcon#about to read 6, iclass 35, count 0 2006.173.18:55:57.17#ibcon#read 6, iclass 35, count 0 2006.173.18:55:57.17#ibcon#end of sib2, iclass 35, count 0 2006.173.18:55:57.17#ibcon#*after write, iclass 35, count 0 2006.173.18:55:57.17#ibcon#*before return 0, iclass 35, count 0 2006.173.18:55:57.17#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.18:55:57.17#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.18:55:57.17#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.18:55:57.17#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.18:55:57.17$vck44/valo=4,624.99 2006.173.18:55:57.17#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.18:55:57.17#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.18:55:57.17#ibcon#ireg 17 cls_cnt 0 2006.173.18:55:57.17#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.18:55:57.17#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.18:55:57.17#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.18:55:57.17#ibcon#enter wrdev, iclass 37, count 0 2006.173.18:55:57.17#ibcon#first serial, iclass 37, count 0 2006.173.18:55:57.17#ibcon#enter sib2, iclass 37, count 0 2006.173.18:55:57.17#ibcon#flushed, iclass 37, count 0 2006.173.18:55:57.17#ibcon#about to write, iclass 37, count 0 2006.173.18:55:57.17#ibcon#wrote, iclass 37, count 0 2006.173.18:55:57.17#ibcon#about to read 3, iclass 37, count 0 2006.173.18:55:57.19#ibcon#read 3, iclass 37, count 0 2006.173.18:55:57.19#ibcon#about to read 4, iclass 37, count 0 2006.173.18:55:57.19#ibcon#read 4, iclass 37, count 0 2006.173.18:55:57.19#ibcon#about to read 5, iclass 37, count 0 2006.173.18:55:57.19#ibcon#read 5, iclass 37, count 0 2006.173.18:55:57.19#ibcon#about to read 6, iclass 37, count 0 2006.173.18:55:57.19#ibcon#read 6, iclass 37, count 0 2006.173.18:55:57.19#ibcon#end of sib2, iclass 37, count 0 2006.173.18:55:57.19#ibcon#*mode == 0, iclass 37, count 0 2006.173.18:55:57.19#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.18:55:57.19#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.18:55:57.19#ibcon#*before write, iclass 37, count 0 2006.173.18:55:57.19#ibcon#enter sib2, iclass 37, count 0 2006.173.18:55:57.19#ibcon#flushed, iclass 37, count 0 2006.173.18:55:57.19#ibcon#about to write, iclass 37, count 0 2006.173.18:55:57.19#ibcon#wrote, iclass 37, count 0 2006.173.18:55:57.19#ibcon#about to read 3, iclass 37, count 0 2006.173.18:55:57.23#ibcon#read 3, iclass 37, count 0 2006.173.18:55:57.23#ibcon#about to read 4, iclass 37, count 0 2006.173.18:55:57.23#ibcon#read 4, iclass 37, count 0 2006.173.18:55:57.23#ibcon#about to read 5, iclass 37, count 0 2006.173.18:55:57.23#ibcon#read 5, iclass 37, count 0 2006.173.18:55:57.23#ibcon#about to read 6, iclass 37, count 0 2006.173.18:55:57.23#ibcon#read 6, iclass 37, count 0 2006.173.18:55:57.23#ibcon#end of sib2, iclass 37, count 0 2006.173.18:55:57.23#ibcon#*after write, iclass 37, count 0 2006.173.18:55:57.23#ibcon#*before return 0, iclass 37, count 0 2006.173.18:55:57.23#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.18:55:57.23#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.18:55:57.23#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.18:55:57.23#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.18:55:57.23$vck44/va=4,6 2006.173.18:55:57.23#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.18:55:57.23#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.18:55:57.23#ibcon#ireg 11 cls_cnt 2 2006.173.18:55:57.23#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.18:55:57.29#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.18:55:57.29#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.18:55:57.29#ibcon#enter wrdev, iclass 39, count 2 2006.173.18:55:57.29#ibcon#first serial, iclass 39, count 2 2006.173.18:55:57.29#ibcon#enter sib2, iclass 39, count 2 2006.173.18:55:57.29#ibcon#flushed, iclass 39, count 2 2006.173.18:55:57.29#ibcon#about to write, iclass 39, count 2 2006.173.18:55:57.29#ibcon#wrote, iclass 39, count 2 2006.173.18:55:57.29#ibcon#about to read 3, iclass 39, count 2 2006.173.18:55:57.31#ibcon#read 3, iclass 39, count 2 2006.173.18:55:57.31#ibcon#about to read 4, iclass 39, count 2 2006.173.18:55:57.31#ibcon#read 4, iclass 39, count 2 2006.173.18:55:57.31#ibcon#about to read 5, iclass 39, count 2 2006.173.18:55:57.31#ibcon#read 5, iclass 39, count 2 2006.173.18:55:57.31#ibcon#about to read 6, iclass 39, count 2 2006.173.18:55:57.31#ibcon#read 6, iclass 39, count 2 2006.173.18:55:57.31#ibcon#end of sib2, iclass 39, count 2 2006.173.18:55:57.31#ibcon#*mode == 0, iclass 39, count 2 2006.173.18:55:57.31#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.18:55:57.31#ibcon#[25=AT04-06\r\n] 2006.173.18:55:57.31#ibcon#*before write, iclass 39, count 2 2006.173.18:55:57.31#ibcon#enter sib2, iclass 39, count 2 2006.173.18:55:57.31#ibcon#flushed, iclass 39, count 2 2006.173.18:55:57.31#ibcon#about to write, iclass 39, count 2 2006.173.18:55:57.31#ibcon#wrote, iclass 39, count 2 2006.173.18:55:57.31#ibcon#about to read 3, iclass 39, count 2 2006.173.18:55:57.34#ibcon#read 3, iclass 39, count 2 2006.173.18:55:57.34#ibcon#about to read 4, iclass 39, count 2 2006.173.18:55:57.34#ibcon#read 4, iclass 39, count 2 2006.173.18:55:57.34#ibcon#about to read 5, iclass 39, count 2 2006.173.18:55:57.34#ibcon#read 5, iclass 39, count 2 2006.173.18:55:57.34#ibcon#about to read 6, iclass 39, count 2 2006.173.18:55:57.34#ibcon#read 6, iclass 39, count 2 2006.173.18:55:57.34#ibcon#end of sib2, iclass 39, count 2 2006.173.18:55:57.34#ibcon#*after write, iclass 39, count 2 2006.173.18:55:57.34#ibcon#*before return 0, iclass 39, count 2 2006.173.18:55:57.34#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.18:55:57.34#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.18:55:57.34#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.18:55:57.34#ibcon#ireg 7 cls_cnt 0 2006.173.18:55:57.34#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.18:55:57.46#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.18:55:57.46#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.18:55:57.46#ibcon#enter wrdev, iclass 39, count 0 2006.173.18:55:57.46#ibcon#first serial, iclass 39, count 0 2006.173.18:55:57.46#ibcon#enter sib2, iclass 39, count 0 2006.173.18:55:57.46#ibcon#flushed, iclass 39, count 0 2006.173.18:55:57.46#ibcon#about to write, iclass 39, count 0 2006.173.18:55:57.46#ibcon#wrote, iclass 39, count 0 2006.173.18:55:57.46#ibcon#about to read 3, iclass 39, count 0 2006.173.18:55:57.48#ibcon#read 3, iclass 39, count 0 2006.173.18:55:57.48#ibcon#about to read 4, iclass 39, count 0 2006.173.18:55:57.48#ibcon#read 4, iclass 39, count 0 2006.173.18:55:57.48#ibcon#about to read 5, iclass 39, count 0 2006.173.18:55:57.48#ibcon#read 5, iclass 39, count 0 2006.173.18:55:57.48#ibcon#about to read 6, iclass 39, count 0 2006.173.18:55:57.48#ibcon#read 6, iclass 39, count 0 2006.173.18:55:57.48#ibcon#end of sib2, iclass 39, count 0 2006.173.18:55:57.48#ibcon#*mode == 0, iclass 39, count 0 2006.173.18:55:57.48#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.18:55:57.48#ibcon#[25=USB\r\n] 2006.173.18:55:57.48#ibcon#*before write, iclass 39, count 0 2006.173.18:55:57.48#ibcon#enter sib2, iclass 39, count 0 2006.173.18:55:57.48#ibcon#flushed, iclass 39, count 0 2006.173.18:55:57.48#ibcon#about to write, iclass 39, count 0 2006.173.18:55:57.48#ibcon#wrote, iclass 39, count 0 2006.173.18:55:57.48#ibcon#about to read 3, iclass 39, count 0 2006.173.18:55:57.51#ibcon#read 3, iclass 39, count 0 2006.173.18:55:57.51#ibcon#about to read 4, iclass 39, count 0 2006.173.18:55:57.51#ibcon#read 4, iclass 39, count 0 2006.173.18:55:57.51#ibcon#about to read 5, iclass 39, count 0 2006.173.18:55:57.51#ibcon#read 5, iclass 39, count 0 2006.173.18:55:57.51#ibcon#about to read 6, iclass 39, count 0 2006.173.18:55:57.51#ibcon#read 6, iclass 39, count 0 2006.173.18:55:57.51#ibcon#end of sib2, iclass 39, count 0 2006.173.18:55:57.51#ibcon#*after write, iclass 39, count 0 2006.173.18:55:57.51#ibcon#*before return 0, iclass 39, count 0 2006.173.18:55:57.51#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.18:55:57.51#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.18:55:57.51#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.18:55:57.51#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.18:55:57.51$vck44/valo=5,734.99 2006.173.18:55:57.51#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.18:55:57.51#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.18:55:57.51#ibcon#ireg 17 cls_cnt 0 2006.173.18:55:57.51#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.18:55:57.51#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.18:55:57.51#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.18:55:57.51#ibcon#enter wrdev, iclass 3, count 0 2006.173.18:55:57.51#ibcon#first serial, iclass 3, count 0 2006.173.18:55:57.51#ibcon#enter sib2, iclass 3, count 0 2006.173.18:55:57.51#ibcon#flushed, iclass 3, count 0 2006.173.18:55:57.51#ibcon#about to write, iclass 3, count 0 2006.173.18:55:57.51#ibcon#wrote, iclass 3, count 0 2006.173.18:55:57.51#ibcon#about to read 3, iclass 3, count 0 2006.173.18:55:57.53#ibcon#read 3, iclass 3, count 0 2006.173.18:55:57.53#ibcon#about to read 4, iclass 3, count 0 2006.173.18:55:57.53#ibcon#read 4, iclass 3, count 0 2006.173.18:55:57.53#ibcon#about to read 5, iclass 3, count 0 2006.173.18:55:57.53#ibcon#read 5, iclass 3, count 0 2006.173.18:55:57.53#ibcon#about to read 6, iclass 3, count 0 2006.173.18:55:57.53#ibcon#read 6, iclass 3, count 0 2006.173.18:55:57.53#ibcon#end of sib2, iclass 3, count 0 2006.173.18:55:57.53#ibcon#*mode == 0, iclass 3, count 0 2006.173.18:55:57.53#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.18:55:57.53#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.18:55:57.53#ibcon#*before write, iclass 3, count 0 2006.173.18:55:57.53#ibcon#enter sib2, iclass 3, count 0 2006.173.18:55:57.53#ibcon#flushed, iclass 3, count 0 2006.173.18:55:57.53#ibcon#about to write, iclass 3, count 0 2006.173.18:55:57.53#ibcon#wrote, iclass 3, count 0 2006.173.18:55:57.53#ibcon#about to read 3, iclass 3, count 0 2006.173.18:55:57.57#ibcon#read 3, iclass 3, count 0 2006.173.18:55:57.57#ibcon#about to read 4, iclass 3, count 0 2006.173.18:55:57.57#ibcon#read 4, iclass 3, count 0 2006.173.18:55:57.57#ibcon#about to read 5, iclass 3, count 0 2006.173.18:55:57.57#ibcon#read 5, iclass 3, count 0 2006.173.18:55:57.57#ibcon#about to read 6, iclass 3, count 0 2006.173.18:55:57.57#ibcon#read 6, iclass 3, count 0 2006.173.18:55:57.57#ibcon#end of sib2, iclass 3, count 0 2006.173.18:55:57.57#ibcon#*after write, iclass 3, count 0 2006.173.18:55:57.57#ibcon#*before return 0, iclass 3, count 0 2006.173.18:55:57.57#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.18:55:57.57#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.18:55:57.57#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.18:55:57.57#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.18:55:57.57$vck44/va=5,4 2006.173.18:55:57.57#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.18:55:57.57#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.18:55:57.57#ibcon#ireg 11 cls_cnt 2 2006.173.18:55:57.57#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.18:55:57.63#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.18:55:57.63#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.18:55:57.63#ibcon#enter wrdev, iclass 5, count 2 2006.173.18:55:57.63#ibcon#first serial, iclass 5, count 2 2006.173.18:55:57.63#ibcon#enter sib2, iclass 5, count 2 2006.173.18:55:57.63#ibcon#flushed, iclass 5, count 2 2006.173.18:55:57.63#ibcon#about to write, iclass 5, count 2 2006.173.18:55:57.63#ibcon#wrote, iclass 5, count 2 2006.173.18:55:57.63#ibcon#about to read 3, iclass 5, count 2 2006.173.18:55:57.65#ibcon#read 3, iclass 5, count 2 2006.173.18:55:57.65#ibcon#about to read 4, iclass 5, count 2 2006.173.18:55:57.65#ibcon#read 4, iclass 5, count 2 2006.173.18:55:57.65#ibcon#about to read 5, iclass 5, count 2 2006.173.18:55:57.65#ibcon#read 5, iclass 5, count 2 2006.173.18:55:57.65#ibcon#about to read 6, iclass 5, count 2 2006.173.18:55:57.65#ibcon#read 6, iclass 5, count 2 2006.173.18:55:57.65#ibcon#end of sib2, iclass 5, count 2 2006.173.18:55:57.65#ibcon#*mode == 0, iclass 5, count 2 2006.173.18:55:57.65#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.18:55:57.65#ibcon#[25=AT05-04\r\n] 2006.173.18:55:57.65#ibcon#*before write, iclass 5, count 2 2006.173.18:55:57.65#ibcon#enter sib2, iclass 5, count 2 2006.173.18:55:57.65#ibcon#flushed, iclass 5, count 2 2006.173.18:55:57.65#ibcon#about to write, iclass 5, count 2 2006.173.18:55:57.65#ibcon#wrote, iclass 5, count 2 2006.173.18:55:57.65#ibcon#about to read 3, iclass 5, count 2 2006.173.18:55:57.68#ibcon#read 3, iclass 5, count 2 2006.173.18:55:57.68#ibcon#about to read 4, iclass 5, count 2 2006.173.18:55:57.68#ibcon#read 4, iclass 5, count 2 2006.173.18:55:57.68#ibcon#about to read 5, iclass 5, count 2 2006.173.18:55:57.68#ibcon#read 5, iclass 5, count 2 2006.173.18:55:57.68#ibcon#about to read 6, iclass 5, count 2 2006.173.18:55:57.68#ibcon#read 6, iclass 5, count 2 2006.173.18:55:57.68#ibcon#end of sib2, iclass 5, count 2 2006.173.18:55:57.68#ibcon#*after write, iclass 5, count 2 2006.173.18:55:57.68#ibcon#*before return 0, iclass 5, count 2 2006.173.18:55:57.68#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.18:55:57.68#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.18:55:57.68#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.18:55:57.68#ibcon#ireg 7 cls_cnt 0 2006.173.18:55:57.68#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.18:55:57.80#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.18:55:57.80#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.18:55:57.80#ibcon#enter wrdev, iclass 5, count 0 2006.173.18:55:57.80#ibcon#first serial, iclass 5, count 0 2006.173.18:55:57.80#ibcon#enter sib2, iclass 5, count 0 2006.173.18:55:57.80#ibcon#flushed, iclass 5, count 0 2006.173.18:55:57.80#ibcon#about to write, iclass 5, count 0 2006.173.18:55:57.80#ibcon#wrote, iclass 5, count 0 2006.173.18:55:57.80#ibcon#about to read 3, iclass 5, count 0 2006.173.18:55:57.82#ibcon#read 3, iclass 5, count 0 2006.173.18:55:57.82#ibcon#about to read 4, iclass 5, count 0 2006.173.18:55:57.82#ibcon#read 4, iclass 5, count 0 2006.173.18:55:57.82#ibcon#about to read 5, iclass 5, count 0 2006.173.18:55:57.82#ibcon#read 5, iclass 5, count 0 2006.173.18:55:57.82#ibcon#about to read 6, iclass 5, count 0 2006.173.18:55:57.82#ibcon#read 6, iclass 5, count 0 2006.173.18:55:57.82#ibcon#end of sib2, iclass 5, count 0 2006.173.18:55:57.82#ibcon#*mode == 0, iclass 5, count 0 2006.173.18:55:57.82#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.18:55:57.82#ibcon#[25=USB\r\n] 2006.173.18:55:57.82#ibcon#*before write, iclass 5, count 0 2006.173.18:55:57.82#ibcon#enter sib2, iclass 5, count 0 2006.173.18:55:57.82#ibcon#flushed, iclass 5, count 0 2006.173.18:55:57.82#ibcon#about to write, iclass 5, count 0 2006.173.18:55:57.82#ibcon#wrote, iclass 5, count 0 2006.173.18:55:57.82#ibcon#about to read 3, iclass 5, count 0 2006.173.18:55:57.85#ibcon#read 3, iclass 5, count 0 2006.173.18:55:57.85#ibcon#about to read 4, iclass 5, count 0 2006.173.18:55:57.85#ibcon#read 4, iclass 5, count 0 2006.173.18:55:57.85#ibcon#about to read 5, iclass 5, count 0 2006.173.18:55:57.85#ibcon#read 5, iclass 5, count 0 2006.173.18:55:57.85#ibcon#about to read 6, iclass 5, count 0 2006.173.18:55:57.85#ibcon#read 6, iclass 5, count 0 2006.173.18:55:57.85#ibcon#end of sib2, iclass 5, count 0 2006.173.18:55:57.85#ibcon#*after write, iclass 5, count 0 2006.173.18:55:57.85#ibcon#*before return 0, iclass 5, count 0 2006.173.18:55:57.85#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.18:55:57.85#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.18:55:57.85#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.18:55:57.85#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.18:55:57.85$vck44/valo=6,814.99 2006.173.18:55:57.85#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.18:55:57.85#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.18:55:57.85#ibcon#ireg 17 cls_cnt 0 2006.173.18:55:57.85#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.18:55:57.85#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.18:55:57.85#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.18:55:57.85#ibcon#enter wrdev, iclass 7, count 0 2006.173.18:55:57.85#ibcon#first serial, iclass 7, count 0 2006.173.18:55:57.85#ibcon#enter sib2, iclass 7, count 0 2006.173.18:55:57.85#ibcon#flushed, iclass 7, count 0 2006.173.18:55:57.85#ibcon#about to write, iclass 7, count 0 2006.173.18:55:57.85#ibcon#wrote, iclass 7, count 0 2006.173.18:55:57.85#ibcon#about to read 3, iclass 7, count 0 2006.173.18:55:57.87#ibcon#read 3, iclass 7, count 0 2006.173.18:55:57.87#ibcon#about to read 4, iclass 7, count 0 2006.173.18:55:57.87#ibcon#read 4, iclass 7, count 0 2006.173.18:55:57.87#ibcon#about to read 5, iclass 7, count 0 2006.173.18:55:57.87#ibcon#read 5, iclass 7, count 0 2006.173.18:55:57.87#ibcon#about to read 6, iclass 7, count 0 2006.173.18:55:57.87#ibcon#read 6, iclass 7, count 0 2006.173.18:55:57.87#ibcon#end of sib2, iclass 7, count 0 2006.173.18:55:57.87#ibcon#*mode == 0, iclass 7, count 0 2006.173.18:55:57.87#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.18:55:57.87#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.18:55:57.87#ibcon#*before write, iclass 7, count 0 2006.173.18:55:57.87#ibcon#enter sib2, iclass 7, count 0 2006.173.18:55:57.87#ibcon#flushed, iclass 7, count 0 2006.173.18:55:57.87#ibcon#about to write, iclass 7, count 0 2006.173.18:55:57.87#ibcon#wrote, iclass 7, count 0 2006.173.18:55:57.87#ibcon#about to read 3, iclass 7, count 0 2006.173.18:55:57.91#ibcon#read 3, iclass 7, count 0 2006.173.18:55:57.91#ibcon#about to read 4, iclass 7, count 0 2006.173.18:55:57.91#ibcon#read 4, iclass 7, count 0 2006.173.18:55:57.91#ibcon#about to read 5, iclass 7, count 0 2006.173.18:55:57.91#ibcon#read 5, iclass 7, count 0 2006.173.18:55:57.91#ibcon#about to read 6, iclass 7, count 0 2006.173.18:55:57.91#ibcon#read 6, iclass 7, count 0 2006.173.18:55:57.91#ibcon#end of sib2, iclass 7, count 0 2006.173.18:55:57.91#ibcon#*after write, iclass 7, count 0 2006.173.18:55:57.91#ibcon#*before return 0, iclass 7, count 0 2006.173.18:55:57.91#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.18:55:57.91#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.18:55:57.91#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.18:55:57.91#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.18:55:57.91$vck44/va=6,3 2006.173.18:55:57.91#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.18:55:57.91#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.18:55:57.91#ibcon#ireg 11 cls_cnt 2 2006.173.18:55:57.91#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.18:55:57.97#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.18:55:57.97#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.18:55:57.97#ibcon#enter wrdev, iclass 11, count 2 2006.173.18:55:57.97#ibcon#first serial, iclass 11, count 2 2006.173.18:55:57.97#ibcon#enter sib2, iclass 11, count 2 2006.173.18:55:57.97#ibcon#flushed, iclass 11, count 2 2006.173.18:55:57.97#ibcon#about to write, iclass 11, count 2 2006.173.18:55:57.97#ibcon#wrote, iclass 11, count 2 2006.173.18:55:57.97#ibcon#about to read 3, iclass 11, count 2 2006.173.18:55:57.99#ibcon#read 3, iclass 11, count 2 2006.173.18:55:57.99#ibcon#about to read 4, iclass 11, count 2 2006.173.18:55:57.99#ibcon#read 4, iclass 11, count 2 2006.173.18:55:57.99#ibcon#about to read 5, iclass 11, count 2 2006.173.18:55:57.99#ibcon#read 5, iclass 11, count 2 2006.173.18:55:57.99#ibcon#about to read 6, iclass 11, count 2 2006.173.18:55:57.99#ibcon#read 6, iclass 11, count 2 2006.173.18:55:57.99#ibcon#end of sib2, iclass 11, count 2 2006.173.18:55:57.99#ibcon#*mode == 0, iclass 11, count 2 2006.173.18:55:57.99#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.18:55:57.99#ibcon#[25=AT06-03\r\n] 2006.173.18:55:57.99#ibcon#*before write, iclass 11, count 2 2006.173.18:55:57.99#ibcon#enter sib2, iclass 11, count 2 2006.173.18:55:57.99#ibcon#flushed, iclass 11, count 2 2006.173.18:55:57.99#ibcon#about to write, iclass 11, count 2 2006.173.18:55:57.99#ibcon#wrote, iclass 11, count 2 2006.173.18:55:57.99#ibcon#about to read 3, iclass 11, count 2 2006.173.18:55:58.02#ibcon#read 3, iclass 11, count 2 2006.173.18:55:58.02#ibcon#about to read 4, iclass 11, count 2 2006.173.18:55:58.02#ibcon#read 4, iclass 11, count 2 2006.173.18:55:58.02#ibcon#about to read 5, iclass 11, count 2 2006.173.18:55:58.02#ibcon#read 5, iclass 11, count 2 2006.173.18:55:58.02#ibcon#about to read 6, iclass 11, count 2 2006.173.18:55:58.02#ibcon#read 6, iclass 11, count 2 2006.173.18:55:58.02#ibcon#end of sib2, iclass 11, count 2 2006.173.18:55:58.02#ibcon#*after write, iclass 11, count 2 2006.173.18:55:58.02#ibcon#*before return 0, iclass 11, count 2 2006.173.18:55:58.02#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.18:55:58.02#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.18:55:58.02#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.18:55:58.02#ibcon#ireg 7 cls_cnt 0 2006.173.18:55:58.02#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.18:55:58.14#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.18:55:58.14#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.18:55:58.14#ibcon#enter wrdev, iclass 11, count 0 2006.173.18:55:58.14#ibcon#first serial, iclass 11, count 0 2006.173.18:55:58.14#ibcon#enter sib2, iclass 11, count 0 2006.173.18:55:58.14#ibcon#flushed, iclass 11, count 0 2006.173.18:55:58.14#ibcon#about to write, iclass 11, count 0 2006.173.18:55:58.14#ibcon#wrote, iclass 11, count 0 2006.173.18:55:58.14#ibcon#about to read 3, iclass 11, count 0 2006.173.18:55:58.16#ibcon#read 3, iclass 11, count 0 2006.173.18:55:58.16#ibcon#about to read 4, iclass 11, count 0 2006.173.18:55:58.16#ibcon#read 4, iclass 11, count 0 2006.173.18:55:58.16#ibcon#about to read 5, iclass 11, count 0 2006.173.18:55:58.16#ibcon#read 5, iclass 11, count 0 2006.173.18:55:58.16#ibcon#about to read 6, iclass 11, count 0 2006.173.18:55:58.16#ibcon#read 6, iclass 11, count 0 2006.173.18:55:58.16#ibcon#end of sib2, iclass 11, count 0 2006.173.18:55:58.16#ibcon#*mode == 0, iclass 11, count 0 2006.173.18:55:58.16#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.18:55:58.16#ibcon#[25=USB\r\n] 2006.173.18:55:58.16#ibcon#*before write, iclass 11, count 0 2006.173.18:55:58.16#ibcon#enter sib2, iclass 11, count 0 2006.173.18:55:58.16#ibcon#flushed, iclass 11, count 0 2006.173.18:55:58.16#ibcon#about to write, iclass 11, count 0 2006.173.18:55:58.16#ibcon#wrote, iclass 11, count 0 2006.173.18:55:58.16#ibcon#about to read 3, iclass 11, count 0 2006.173.18:55:58.19#ibcon#read 3, iclass 11, count 0 2006.173.18:55:58.19#ibcon#about to read 4, iclass 11, count 0 2006.173.18:55:58.19#ibcon#read 4, iclass 11, count 0 2006.173.18:55:58.19#ibcon#about to read 5, iclass 11, count 0 2006.173.18:55:58.19#ibcon#read 5, iclass 11, count 0 2006.173.18:55:58.19#ibcon#about to read 6, iclass 11, count 0 2006.173.18:55:58.19#ibcon#read 6, iclass 11, count 0 2006.173.18:55:58.19#ibcon#end of sib2, iclass 11, count 0 2006.173.18:55:58.19#ibcon#*after write, iclass 11, count 0 2006.173.18:55:58.19#ibcon#*before return 0, iclass 11, count 0 2006.173.18:55:58.19#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.18:55:58.19#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.18:55:58.19#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.18:55:58.19#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.18:55:58.19$vck44/valo=7,864.99 2006.173.18:55:58.19#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.18:55:58.19#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.18:55:58.19#ibcon#ireg 17 cls_cnt 0 2006.173.18:55:58.19#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.18:55:58.19#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.18:55:58.19#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.18:55:58.19#ibcon#enter wrdev, iclass 13, count 0 2006.173.18:55:58.19#ibcon#first serial, iclass 13, count 0 2006.173.18:55:58.19#ibcon#enter sib2, iclass 13, count 0 2006.173.18:55:58.19#ibcon#flushed, iclass 13, count 0 2006.173.18:55:58.19#ibcon#about to write, iclass 13, count 0 2006.173.18:55:58.19#ibcon#wrote, iclass 13, count 0 2006.173.18:55:58.19#ibcon#about to read 3, iclass 13, count 0 2006.173.18:55:58.21#ibcon#read 3, iclass 13, count 0 2006.173.18:55:58.21#ibcon#about to read 4, iclass 13, count 0 2006.173.18:55:58.21#ibcon#read 4, iclass 13, count 0 2006.173.18:55:58.21#ibcon#about to read 5, iclass 13, count 0 2006.173.18:55:58.21#ibcon#read 5, iclass 13, count 0 2006.173.18:55:58.21#ibcon#about to read 6, iclass 13, count 0 2006.173.18:55:58.21#ibcon#read 6, iclass 13, count 0 2006.173.18:55:58.21#ibcon#end of sib2, iclass 13, count 0 2006.173.18:55:58.21#ibcon#*mode == 0, iclass 13, count 0 2006.173.18:55:58.21#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.18:55:58.21#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.18:55:58.21#ibcon#*before write, iclass 13, count 0 2006.173.18:55:58.21#ibcon#enter sib2, iclass 13, count 0 2006.173.18:55:58.21#ibcon#flushed, iclass 13, count 0 2006.173.18:55:58.21#ibcon#about to write, iclass 13, count 0 2006.173.18:55:58.21#ibcon#wrote, iclass 13, count 0 2006.173.18:55:58.21#ibcon#about to read 3, iclass 13, count 0 2006.173.18:55:58.25#ibcon#read 3, iclass 13, count 0 2006.173.18:55:58.25#ibcon#about to read 4, iclass 13, count 0 2006.173.18:55:58.25#ibcon#read 4, iclass 13, count 0 2006.173.18:55:58.25#ibcon#about to read 5, iclass 13, count 0 2006.173.18:55:58.25#ibcon#read 5, iclass 13, count 0 2006.173.18:55:58.25#ibcon#about to read 6, iclass 13, count 0 2006.173.18:55:58.25#ibcon#read 6, iclass 13, count 0 2006.173.18:55:58.25#ibcon#end of sib2, iclass 13, count 0 2006.173.18:55:58.25#ibcon#*after write, iclass 13, count 0 2006.173.18:55:58.25#ibcon#*before return 0, iclass 13, count 0 2006.173.18:55:58.25#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.18:55:58.25#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.18:55:58.25#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.18:55:58.25#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.18:55:58.25$vck44/va=7,4 2006.173.18:55:58.25#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.18:55:58.25#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.18:55:58.25#ibcon#ireg 11 cls_cnt 2 2006.173.18:55:58.25#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.18:55:58.31#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.18:55:58.31#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.18:55:58.31#ibcon#enter wrdev, iclass 15, count 2 2006.173.18:55:58.31#ibcon#first serial, iclass 15, count 2 2006.173.18:55:58.31#ibcon#enter sib2, iclass 15, count 2 2006.173.18:55:58.31#ibcon#flushed, iclass 15, count 2 2006.173.18:55:58.31#ibcon#about to write, iclass 15, count 2 2006.173.18:55:58.31#ibcon#wrote, iclass 15, count 2 2006.173.18:55:58.31#ibcon#about to read 3, iclass 15, count 2 2006.173.18:55:58.33#ibcon#read 3, iclass 15, count 2 2006.173.18:55:58.33#ibcon#about to read 4, iclass 15, count 2 2006.173.18:55:58.33#ibcon#read 4, iclass 15, count 2 2006.173.18:55:58.33#ibcon#about to read 5, iclass 15, count 2 2006.173.18:55:58.33#ibcon#read 5, iclass 15, count 2 2006.173.18:55:58.33#ibcon#about to read 6, iclass 15, count 2 2006.173.18:55:58.33#ibcon#read 6, iclass 15, count 2 2006.173.18:55:58.33#ibcon#end of sib2, iclass 15, count 2 2006.173.18:55:58.33#ibcon#*mode == 0, iclass 15, count 2 2006.173.18:55:58.33#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.18:55:58.33#ibcon#[25=AT07-04\r\n] 2006.173.18:55:58.33#ibcon#*before write, iclass 15, count 2 2006.173.18:55:58.33#ibcon#enter sib2, iclass 15, count 2 2006.173.18:55:58.33#ibcon#flushed, iclass 15, count 2 2006.173.18:55:58.33#ibcon#about to write, iclass 15, count 2 2006.173.18:55:58.33#ibcon#wrote, iclass 15, count 2 2006.173.18:55:58.33#ibcon#about to read 3, iclass 15, count 2 2006.173.18:55:58.36#ibcon#read 3, iclass 15, count 2 2006.173.18:55:58.36#ibcon#about to read 4, iclass 15, count 2 2006.173.18:55:58.36#ibcon#read 4, iclass 15, count 2 2006.173.18:55:58.36#ibcon#about to read 5, iclass 15, count 2 2006.173.18:55:58.36#ibcon#read 5, iclass 15, count 2 2006.173.18:55:58.36#ibcon#about to read 6, iclass 15, count 2 2006.173.18:55:58.36#ibcon#read 6, iclass 15, count 2 2006.173.18:55:58.36#ibcon#end of sib2, iclass 15, count 2 2006.173.18:55:58.36#ibcon#*after write, iclass 15, count 2 2006.173.18:55:58.36#ibcon#*before return 0, iclass 15, count 2 2006.173.18:55:58.36#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.18:55:58.36#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.18:55:58.36#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.18:55:58.36#ibcon#ireg 7 cls_cnt 0 2006.173.18:55:58.36#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.18:55:58.48#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.18:55:58.48#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.18:55:58.48#ibcon#enter wrdev, iclass 15, count 0 2006.173.18:55:58.48#ibcon#first serial, iclass 15, count 0 2006.173.18:55:58.48#ibcon#enter sib2, iclass 15, count 0 2006.173.18:55:58.48#ibcon#flushed, iclass 15, count 0 2006.173.18:55:58.48#ibcon#about to write, iclass 15, count 0 2006.173.18:55:58.48#ibcon#wrote, iclass 15, count 0 2006.173.18:55:58.48#ibcon#about to read 3, iclass 15, count 0 2006.173.18:55:58.50#ibcon#read 3, iclass 15, count 0 2006.173.18:55:58.50#ibcon#about to read 4, iclass 15, count 0 2006.173.18:55:58.50#ibcon#read 4, iclass 15, count 0 2006.173.18:55:58.50#ibcon#about to read 5, iclass 15, count 0 2006.173.18:55:58.50#ibcon#read 5, iclass 15, count 0 2006.173.18:55:58.50#ibcon#about to read 6, iclass 15, count 0 2006.173.18:55:58.50#ibcon#read 6, iclass 15, count 0 2006.173.18:55:58.50#ibcon#end of sib2, iclass 15, count 0 2006.173.18:55:58.50#ibcon#*mode == 0, iclass 15, count 0 2006.173.18:55:58.50#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.18:55:58.50#ibcon#[25=USB\r\n] 2006.173.18:55:58.50#ibcon#*before write, iclass 15, count 0 2006.173.18:55:58.50#ibcon#enter sib2, iclass 15, count 0 2006.173.18:55:58.50#ibcon#flushed, iclass 15, count 0 2006.173.18:55:58.50#ibcon#about to write, iclass 15, count 0 2006.173.18:55:58.50#ibcon#wrote, iclass 15, count 0 2006.173.18:55:58.50#ibcon#about to read 3, iclass 15, count 0 2006.173.18:55:58.53#ibcon#read 3, iclass 15, count 0 2006.173.18:55:58.53#ibcon#about to read 4, iclass 15, count 0 2006.173.18:55:58.53#ibcon#read 4, iclass 15, count 0 2006.173.18:55:58.53#ibcon#about to read 5, iclass 15, count 0 2006.173.18:55:58.53#ibcon#read 5, iclass 15, count 0 2006.173.18:55:58.53#ibcon#about to read 6, iclass 15, count 0 2006.173.18:55:58.53#ibcon#read 6, iclass 15, count 0 2006.173.18:55:58.53#ibcon#end of sib2, iclass 15, count 0 2006.173.18:55:58.53#ibcon#*after write, iclass 15, count 0 2006.173.18:55:58.53#ibcon#*before return 0, iclass 15, count 0 2006.173.18:55:58.53#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.18:55:58.53#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.18:55:58.53#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.18:55:58.53#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.18:55:58.53$vck44/valo=8,884.99 2006.173.18:55:58.53#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.18:55:58.53#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.18:55:58.53#ibcon#ireg 17 cls_cnt 0 2006.173.18:55:58.53#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.18:55:58.53#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.18:55:58.53#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.18:55:58.53#ibcon#enter wrdev, iclass 17, count 0 2006.173.18:55:58.53#ibcon#first serial, iclass 17, count 0 2006.173.18:55:58.53#ibcon#enter sib2, iclass 17, count 0 2006.173.18:55:58.53#ibcon#flushed, iclass 17, count 0 2006.173.18:55:58.53#ibcon#about to write, iclass 17, count 0 2006.173.18:55:58.53#ibcon#wrote, iclass 17, count 0 2006.173.18:55:58.53#ibcon#about to read 3, iclass 17, count 0 2006.173.18:55:58.55#ibcon#read 3, iclass 17, count 0 2006.173.18:55:58.55#ibcon#about to read 4, iclass 17, count 0 2006.173.18:55:58.55#ibcon#read 4, iclass 17, count 0 2006.173.18:55:58.55#ibcon#about to read 5, iclass 17, count 0 2006.173.18:55:58.55#ibcon#read 5, iclass 17, count 0 2006.173.18:55:58.55#ibcon#about to read 6, iclass 17, count 0 2006.173.18:55:58.55#ibcon#read 6, iclass 17, count 0 2006.173.18:55:58.55#ibcon#end of sib2, iclass 17, count 0 2006.173.18:55:58.55#ibcon#*mode == 0, iclass 17, count 0 2006.173.18:55:58.55#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.18:55:58.55#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.18:55:58.55#ibcon#*before write, iclass 17, count 0 2006.173.18:55:58.55#ibcon#enter sib2, iclass 17, count 0 2006.173.18:55:58.55#ibcon#flushed, iclass 17, count 0 2006.173.18:55:58.55#ibcon#about to write, iclass 17, count 0 2006.173.18:55:58.55#ibcon#wrote, iclass 17, count 0 2006.173.18:55:58.55#ibcon#about to read 3, iclass 17, count 0 2006.173.18:55:58.59#ibcon#read 3, iclass 17, count 0 2006.173.18:55:58.59#ibcon#about to read 4, iclass 17, count 0 2006.173.18:55:58.59#ibcon#read 4, iclass 17, count 0 2006.173.18:55:58.59#ibcon#about to read 5, iclass 17, count 0 2006.173.18:55:58.59#ibcon#read 5, iclass 17, count 0 2006.173.18:55:58.59#ibcon#about to read 6, iclass 17, count 0 2006.173.18:55:58.59#ibcon#read 6, iclass 17, count 0 2006.173.18:55:58.59#ibcon#end of sib2, iclass 17, count 0 2006.173.18:55:58.59#ibcon#*after write, iclass 17, count 0 2006.173.18:55:58.59#ibcon#*before return 0, iclass 17, count 0 2006.173.18:55:58.59#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.18:55:58.59#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.18:55:58.59#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.18:55:58.59#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.18:55:58.59$vck44/va=8,4 2006.173.18:55:58.59#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.18:55:58.59#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.18:55:58.59#ibcon#ireg 11 cls_cnt 2 2006.173.18:55:58.59#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.18:55:58.65#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.18:55:58.65#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.18:55:58.65#ibcon#enter wrdev, iclass 19, count 2 2006.173.18:55:58.65#ibcon#first serial, iclass 19, count 2 2006.173.18:55:58.65#ibcon#enter sib2, iclass 19, count 2 2006.173.18:55:58.65#ibcon#flushed, iclass 19, count 2 2006.173.18:55:58.65#ibcon#about to write, iclass 19, count 2 2006.173.18:55:58.65#ibcon#wrote, iclass 19, count 2 2006.173.18:55:58.65#ibcon#about to read 3, iclass 19, count 2 2006.173.18:55:58.67#ibcon#read 3, iclass 19, count 2 2006.173.18:55:58.67#ibcon#about to read 4, iclass 19, count 2 2006.173.18:55:58.67#ibcon#read 4, iclass 19, count 2 2006.173.18:55:58.67#ibcon#about to read 5, iclass 19, count 2 2006.173.18:55:58.67#ibcon#read 5, iclass 19, count 2 2006.173.18:55:58.67#ibcon#about to read 6, iclass 19, count 2 2006.173.18:55:58.67#ibcon#read 6, iclass 19, count 2 2006.173.18:55:58.67#ibcon#end of sib2, iclass 19, count 2 2006.173.18:55:58.67#ibcon#*mode == 0, iclass 19, count 2 2006.173.18:55:58.67#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.18:55:58.67#ibcon#[25=AT08-04\r\n] 2006.173.18:55:58.67#ibcon#*before write, iclass 19, count 2 2006.173.18:55:58.67#ibcon#enter sib2, iclass 19, count 2 2006.173.18:55:58.67#ibcon#flushed, iclass 19, count 2 2006.173.18:55:58.67#ibcon#about to write, iclass 19, count 2 2006.173.18:55:58.67#ibcon#wrote, iclass 19, count 2 2006.173.18:55:58.67#ibcon#about to read 3, iclass 19, count 2 2006.173.18:55:58.70#ibcon#read 3, iclass 19, count 2 2006.173.18:55:58.70#ibcon#about to read 4, iclass 19, count 2 2006.173.18:55:58.70#ibcon#read 4, iclass 19, count 2 2006.173.18:55:58.70#ibcon#about to read 5, iclass 19, count 2 2006.173.18:55:58.70#ibcon#read 5, iclass 19, count 2 2006.173.18:55:58.70#ibcon#about to read 6, iclass 19, count 2 2006.173.18:55:58.70#ibcon#read 6, iclass 19, count 2 2006.173.18:55:58.70#ibcon#end of sib2, iclass 19, count 2 2006.173.18:55:58.70#ibcon#*after write, iclass 19, count 2 2006.173.18:55:58.70#ibcon#*before return 0, iclass 19, count 2 2006.173.18:55:58.70#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.18:55:58.70#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.18:55:58.70#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.18:55:58.70#ibcon#ireg 7 cls_cnt 0 2006.173.18:55:58.70#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.18:55:58.82#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.18:55:58.82#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.18:55:58.82#ibcon#enter wrdev, iclass 19, count 0 2006.173.18:55:58.82#ibcon#first serial, iclass 19, count 0 2006.173.18:55:58.82#ibcon#enter sib2, iclass 19, count 0 2006.173.18:55:58.82#ibcon#flushed, iclass 19, count 0 2006.173.18:55:58.82#ibcon#about to write, iclass 19, count 0 2006.173.18:55:58.82#ibcon#wrote, iclass 19, count 0 2006.173.18:55:58.82#ibcon#about to read 3, iclass 19, count 0 2006.173.18:55:58.84#ibcon#read 3, iclass 19, count 0 2006.173.18:55:58.84#ibcon#about to read 4, iclass 19, count 0 2006.173.18:55:58.84#ibcon#read 4, iclass 19, count 0 2006.173.18:55:58.84#ibcon#about to read 5, iclass 19, count 0 2006.173.18:55:58.84#ibcon#read 5, iclass 19, count 0 2006.173.18:55:58.84#ibcon#about to read 6, iclass 19, count 0 2006.173.18:55:58.84#ibcon#read 6, iclass 19, count 0 2006.173.18:55:58.84#ibcon#end of sib2, iclass 19, count 0 2006.173.18:55:58.84#ibcon#*mode == 0, iclass 19, count 0 2006.173.18:55:58.84#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.18:55:58.84#ibcon#[25=USB\r\n] 2006.173.18:55:58.84#ibcon#*before write, iclass 19, count 0 2006.173.18:55:58.84#ibcon#enter sib2, iclass 19, count 0 2006.173.18:55:58.84#ibcon#flushed, iclass 19, count 0 2006.173.18:55:58.84#ibcon#about to write, iclass 19, count 0 2006.173.18:55:58.84#ibcon#wrote, iclass 19, count 0 2006.173.18:55:58.84#ibcon#about to read 3, iclass 19, count 0 2006.173.18:55:58.87#ibcon#read 3, iclass 19, count 0 2006.173.18:55:58.87#ibcon#about to read 4, iclass 19, count 0 2006.173.18:55:58.87#ibcon#read 4, iclass 19, count 0 2006.173.18:55:58.87#ibcon#about to read 5, iclass 19, count 0 2006.173.18:55:58.87#ibcon#read 5, iclass 19, count 0 2006.173.18:55:58.87#ibcon#about to read 6, iclass 19, count 0 2006.173.18:55:58.87#ibcon#read 6, iclass 19, count 0 2006.173.18:55:58.87#ibcon#end of sib2, iclass 19, count 0 2006.173.18:55:58.87#ibcon#*after write, iclass 19, count 0 2006.173.18:55:58.87#ibcon#*before return 0, iclass 19, count 0 2006.173.18:55:58.87#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.18:55:58.87#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.18:55:58.87#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.18:55:58.87#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.18:55:58.87$vck44/vblo=1,629.99 2006.173.18:55:58.87#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.18:55:58.87#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.18:55:58.87#ibcon#ireg 17 cls_cnt 0 2006.173.18:55:58.87#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.18:55:58.87#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.18:55:58.87#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.18:55:58.87#ibcon#enter wrdev, iclass 21, count 0 2006.173.18:55:58.87#ibcon#first serial, iclass 21, count 0 2006.173.18:55:58.87#ibcon#enter sib2, iclass 21, count 0 2006.173.18:55:58.87#ibcon#flushed, iclass 21, count 0 2006.173.18:55:58.87#ibcon#about to write, iclass 21, count 0 2006.173.18:55:58.87#ibcon#wrote, iclass 21, count 0 2006.173.18:55:58.87#ibcon#about to read 3, iclass 21, count 0 2006.173.18:55:58.89#ibcon#read 3, iclass 21, count 0 2006.173.18:55:58.89#ibcon#about to read 4, iclass 21, count 0 2006.173.18:55:58.89#ibcon#read 4, iclass 21, count 0 2006.173.18:55:58.89#ibcon#about to read 5, iclass 21, count 0 2006.173.18:55:58.89#ibcon#read 5, iclass 21, count 0 2006.173.18:55:58.89#ibcon#about to read 6, iclass 21, count 0 2006.173.18:55:58.89#ibcon#read 6, iclass 21, count 0 2006.173.18:55:58.89#ibcon#end of sib2, iclass 21, count 0 2006.173.18:55:58.89#ibcon#*mode == 0, iclass 21, count 0 2006.173.18:55:58.89#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.18:55:58.89#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.18:55:58.89#ibcon#*before write, iclass 21, count 0 2006.173.18:55:58.89#ibcon#enter sib2, iclass 21, count 0 2006.173.18:55:58.89#ibcon#flushed, iclass 21, count 0 2006.173.18:55:58.89#ibcon#about to write, iclass 21, count 0 2006.173.18:55:58.89#ibcon#wrote, iclass 21, count 0 2006.173.18:55:58.89#ibcon#about to read 3, iclass 21, count 0 2006.173.18:55:58.93#ibcon#read 3, iclass 21, count 0 2006.173.18:55:58.93#ibcon#about to read 4, iclass 21, count 0 2006.173.18:55:58.93#ibcon#read 4, iclass 21, count 0 2006.173.18:55:58.93#ibcon#about to read 5, iclass 21, count 0 2006.173.18:55:58.93#ibcon#read 5, iclass 21, count 0 2006.173.18:55:58.93#ibcon#about to read 6, iclass 21, count 0 2006.173.18:55:58.93#ibcon#read 6, iclass 21, count 0 2006.173.18:55:58.93#ibcon#end of sib2, iclass 21, count 0 2006.173.18:55:58.93#ibcon#*after write, iclass 21, count 0 2006.173.18:55:58.93#ibcon#*before return 0, iclass 21, count 0 2006.173.18:55:58.93#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.18:55:58.93#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.18:55:58.93#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.18:55:58.93#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.18:55:58.93$vck44/vb=1,4 2006.173.18:55:58.93#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.18:55:58.93#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.18:55:58.93#ibcon#ireg 11 cls_cnt 2 2006.173.18:55:58.93#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.18:55:58.93#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.18:55:58.93#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.18:55:58.93#ibcon#enter wrdev, iclass 23, count 2 2006.173.18:55:58.93#ibcon#first serial, iclass 23, count 2 2006.173.18:55:58.93#ibcon#enter sib2, iclass 23, count 2 2006.173.18:55:58.93#ibcon#flushed, iclass 23, count 2 2006.173.18:55:58.93#ibcon#about to write, iclass 23, count 2 2006.173.18:55:58.93#ibcon#wrote, iclass 23, count 2 2006.173.18:55:58.93#ibcon#about to read 3, iclass 23, count 2 2006.173.18:55:58.95#ibcon#read 3, iclass 23, count 2 2006.173.18:55:58.95#ibcon#about to read 4, iclass 23, count 2 2006.173.18:55:58.95#ibcon#read 4, iclass 23, count 2 2006.173.18:55:58.95#ibcon#about to read 5, iclass 23, count 2 2006.173.18:55:58.95#ibcon#read 5, iclass 23, count 2 2006.173.18:55:58.95#ibcon#about to read 6, iclass 23, count 2 2006.173.18:55:58.95#ibcon#read 6, iclass 23, count 2 2006.173.18:55:58.95#ibcon#end of sib2, iclass 23, count 2 2006.173.18:55:58.95#ibcon#*mode == 0, iclass 23, count 2 2006.173.18:55:58.95#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.18:55:58.95#ibcon#[27=AT01-04\r\n] 2006.173.18:55:58.95#ibcon#*before write, iclass 23, count 2 2006.173.18:55:58.95#ibcon#enter sib2, iclass 23, count 2 2006.173.18:55:58.95#ibcon#flushed, iclass 23, count 2 2006.173.18:55:58.95#ibcon#about to write, iclass 23, count 2 2006.173.18:55:58.95#ibcon#wrote, iclass 23, count 2 2006.173.18:55:58.95#ibcon#about to read 3, iclass 23, count 2 2006.173.18:55:58.98#ibcon#read 3, iclass 23, count 2 2006.173.18:55:58.98#ibcon#about to read 4, iclass 23, count 2 2006.173.18:55:58.98#ibcon#read 4, iclass 23, count 2 2006.173.18:55:58.98#ibcon#about to read 5, iclass 23, count 2 2006.173.18:55:58.98#ibcon#read 5, iclass 23, count 2 2006.173.18:55:58.98#ibcon#about to read 6, iclass 23, count 2 2006.173.18:55:58.98#ibcon#read 6, iclass 23, count 2 2006.173.18:55:58.98#ibcon#end of sib2, iclass 23, count 2 2006.173.18:55:58.98#ibcon#*after write, iclass 23, count 2 2006.173.18:55:58.98#ibcon#*before return 0, iclass 23, count 2 2006.173.18:55:58.98#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.18:55:58.98#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.18:55:58.98#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.18:55:58.98#ibcon#ireg 7 cls_cnt 0 2006.173.18:55:58.98#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.18:55:59.10#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.18:55:59.10#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.18:55:59.10#ibcon#enter wrdev, iclass 23, count 0 2006.173.18:55:59.10#ibcon#first serial, iclass 23, count 0 2006.173.18:55:59.10#ibcon#enter sib2, iclass 23, count 0 2006.173.18:55:59.10#ibcon#flushed, iclass 23, count 0 2006.173.18:55:59.10#ibcon#about to write, iclass 23, count 0 2006.173.18:55:59.10#ibcon#wrote, iclass 23, count 0 2006.173.18:55:59.10#ibcon#about to read 3, iclass 23, count 0 2006.173.18:55:59.12#ibcon#read 3, iclass 23, count 0 2006.173.18:55:59.12#ibcon#about to read 4, iclass 23, count 0 2006.173.18:55:59.12#ibcon#read 4, iclass 23, count 0 2006.173.18:55:59.12#ibcon#about to read 5, iclass 23, count 0 2006.173.18:55:59.12#ibcon#read 5, iclass 23, count 0 2006.173.18:55:59.12#ibcon#about to read 6, iclass 23, count 0 2006.173.18:55:59.12#ibcon#read 6, iclass 23, count 0 2006.173.18:55:59.12#ibcon#end of sib2, iclass 23, count 0 2006.173.18:55:59.12#ibcon#*mode == 0, iclass 23, count 0 2006.173.18:55:59.12#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.18:55:59.12#ibcon#[27=USB\r\n] 2006.173.18:55:59.12#ibcon#*before write, iclass 23, count 0 2006.173.18:55:59.12#ibcon#enter sib2, iclass 23, count 0 2006.173.18:55:59.12#ibcon#flushed, iclass 23, count 0 2006.173.18:55:59.12#ibcon#about to write, iclass 23, count 0 2006.173.18:55:59.12#ibcon#wrote, iclass 23, count 0 2006.173.18:55:59.12#ibcon#about to read 3, iclass 23, count 0 2006.173.18:55:59.15#ibcon#read 3, iclass 23, count 0 2006.173.18:55:59.15#ibcon#about to read 4, iclass 23, count 0 2006.173.18:55:59.15#ibcon#read 4, iclass 23, count 0 2006.173.18:55:59.15#ibcon#about to read 5, iclass 23, count 0 2006.173.18:55:59.15#ibcon#read 5, iclass 23, count 0 2006.173.18:55:59.15#ibcon#about to read 6, iclass 23, count 0 2006.173.18:55:59.15#ibcon#read 6, iclass 23, count 0 2006.173.18:55:59.15#ibcon#end of sib2, iclass 23, count 0 2006.173.18:55:59.15#ibcon#*after write, iclass 23, count 0 2006.173.18:55:59.15#ibcon#*before return 0, iclass 23, count 0 2006.173.18:55:59.15#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.18:55:59.15#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.18:55:59.15#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.18:55:59.15#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.18:55:59.15$vck44/vblo=2,634.99 2006.173.18:55:59.15#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.18:55:59.15#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.18:55:59.15#ibcon#ireg 17 cls_cnt 0 2006.173.18:55:59.15#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.18:55:59.15#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.18:55:59.15#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.18:55:59.15#ibcon#enter wrdev, iclass 25, count 0 2006.173.18:55:59.15#ibcon#first serial, iclass 25, count 0 2006.173.18:55:59.15#ibcon#enter sib2, iclass 25, count 0 2006.173.18:55:59.15#ibcon#flushed, iclass 25, count 0 2006.173.18:55:59.15#ibcon#about to write, iclass 25, count 0 2006.173.18:55:59.15#ibcon#wrote, iclass 25, count 0 2006.173.18:55:59.15#ibcon#about to read 3, iclass 25, count 0 2006.173.18:55:59.17#ibcon#read 3, iclass 25, count 0 2006.173.18:55:59.17#ibcon#about to read 4, iclass 25, count 0 2006.173.18:55:59.17#ibcon#read 4, iclass 25, count 0 2006.173.18:55:59.17#ibcon#about to read 5, iclass 25, count 0 2006.173.18:55:59.17#ibcon#read 5, iclass 25, count 0 2006.173.18:55:59.17#ibcon#about to read 6, iclass 25, count 0 2006.173.18:55:59.17#ibcon#read 6, iclass 25, count 0 2006.173.18:55:59.17#ibcon#end of sib2, iclass 25, count 0 2006.173.18:55:59.17#ibcon#*mode == 0, iclass 25, count 0 2006.173.18:55:59.17#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.18:55:59.17#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.18:55:59.17#ibcon#*before write, iclass 25, count 0 2006.173.18:55:59.17#ibcon#enter sib2, iclass 25, count 0 2006.173.18:55:59.17#ibcon#flushed, iclass 25, count 0 2006.173.18:55:59.17#ibcon#about to write, iclass 25, count 0 2006.173.18:55:59.17#ibcon#wrote, iclass 25, count 0 2006.173.18:55:59.17#ibcon#about to read 3, iclass 25, count 0 2006.173.18:55:59.21#ibcon#read 3, iclass 25, count 0 2006.173.18:55:59.21#ibcon#about to read 4, iclass 25, count 0 2006.173.18:55:59.21#ibcon#read 4, iclass 25, count 0 2006.173.18:55:59.21#ibcon#about to read 5, iclass 25, count 0 2006.173.18:55:59.21#ibcon#read 5, iclass 25, count 0 2006.173.18:55:59.21#ibcon#about to read 6, iclass 25, count 0 2006.173.18:55:59.21#ibcon#read 6, iclass 25, count 0 2006.173.18:55:59.21#ibcon#end of sib2, iclass 25, count 0 2006.173.18:55:59.21#ibcon#*after write, iclass 25, count 0 2006.173.18:55:59.21#ibcon#*before return 0, iclass 25, count 0 2006.173.18:55:59.21#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.18:55:59.21#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.18:55:59.21#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.18:55:59.21#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.18:55:59.21$vck44/vb=2,4 2006.173.18:55:59.21#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.18:55:59.21#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.18:55:59.21#ibcon#ireg 11 cls_cnt 2 2006.173.18:55:59.21#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.18:55:59.27#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.18:55:59.27#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.18:55:59.27#ibcon#enter wrdev, iclass 27, count 2 2006.173.18:55:59.27#ibcon#first serial, iclass 27, count 2 2006.173.18:55:59.27#ibcon#enter sib2, iclass 27, count 2 2006.173.18:55:59.27#ibcon#flushed, iclass 27, count 2 2006.173.18:55:59.27#ibcon#about to write, iclass 27, count 2 2006.173.18:55:59.27#ibcon#wrote, iclass 27, count 2 2006.173.18:55:59.27#ibcon#about to read 3, iclass 27, count 2 2006.173.18:55:59.29#ibcon#read 3, iclass 27, count 2 2006.173.18:55:59.29#ibcon#about to read 4, iclass 27, count 2 2006.173.18:55:59.29#ibcon#read 4, iclass 27, count 2 2006.173.18:55:59.29#ibcon#about to read 5, iclass 27, count 2 2006.173.18:55:59.29#ibcon#read 5, iclass 27, count 2 2006.173.18:55:59.29#ibcon#about to read 6, iclass 27, count 2 2006.173.18:55:59.29#ibcon#read 6, iclass 27, count 2 2006.173.18:55:59.29#ibcon#end of sib2, iclass 27, count 2 2006.173.18:55:59.29#ibcon#*mode == 0, iclass 27, count 2 2006.173.18:55:59.29#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.18:55:59.29#ibcon#[27=AT02-04\r\n] 2006.173.18:55:59.29#ibcon#*before write, iclass 27, count 2 2006.173.18:55:59.29#ibcon#enter sib2, iclass 27, count 2 2006.173.18:55:59.29#ibcon#flushed, iclass 27, count 2 2006.173.18:55:59.29#ibcon#about to write, iclass 27, count 2 2006.173.18:55:59.29#ibcon#wrote, iclass 27, count 2 2006.173.18:55:59.29#ibcon#about to read 3, iclass 27, count 2 2006.173.18:55:59.32#ibcon#read 3, iclass 27, count 2 2006.173.18:55:59.32#ibcon#about to read 4, iclass 27, count 2 2006.173.18:55:59.32#ibcon#read 4, iclass 27, count 2 2006.173.18:55:59.32#ibcon#about to read 5, iclass 27, count 2 2006.173.18:55:59.32#ibcon#read 5, iclass 27, count 2 2006.173.18:55:59.32#ibcon#about to read 6, iclass 27, count 2 2006.173.18:55:59.32#ibcon#read 6, iclass 27, count 2 2006.173.18:55:59.32#ibcon#end of sib2, iclass 27, count 2 2006.173.18:55:59.32#ibcon#*after write, iclass 27, count 2 2006.173.18:55:59.32#ibcon#*before return 0, iclass 27, count 2 2006.173.18:55:59.32#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.18:55:59.32#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.18:55:59.32#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.18:55:59.32#ibcon#ireg 7 cls_cnt 0 2006.173.18:55:59.32#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.18:55:59.44#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.18:55:59.44#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.18:55:59.44#ibcon#enter wrdev, iclass 27, count 0 2006.173.18:55:59.44#ibcon#first serial, iclass 27, count 0 2006.173.18:55:59.44#ibcon#enter sib2, iclass 27, count 0 2006.173.18:55:59.44#ibcon#flushed, iclass 27, count 0 2006.173.18:55:59.44#ibcon#about to write, iclass 27, count 0 2006.173.18:55:59.44#ibcon#wrote, iclass 27, count 0 2006.173.18:55:59.44#ibcon#about to read 3, iclass 27, count 0 2006.173.18:55:59.46#ibcon#read 3, iclass 27, count 0 2006.173.18:55:59.46#ibcon#about to read 4, iclass 27, count 0 2006.173.18:55:59.46#ibcon#read 4, iclass 27, count 0 2006.173.18:55:59.46#ibcon#about to read 5, iclass 27, count 0 2006.173.18:55:59.46#ibcon#read 5, iclass 27, count 0 2006.173.18:55:59.46#ibcon#about to read 6, iclass 27, count 0 2006.173.18:55:59.46#ibcon#read 6, iclass 27, count 0 2006.173.18:55:59.46#ibcon#end of sib2, iclass 27, count 0 2006.173.18:55:59.46#ibcon#*mode == 0, iclass 27, count 0 2006.173.18:55:59.46#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.18:55:59.46#ibcon#[27=USB\r\n] 2006.173.18:55:59.46#ibcon#*before write, iclass 27, count 0 2006.173.18:55:59.46#ibcon#enter sib2, iclass 27, count 0 2006.173.18:55:59.46#ibcon#flushed, iclass 27, count 0 2006.173.18:55:59.46#ibcon#about to write, iclass 27, count 0 2006.173.18:55:59.46#ibcon#wrote, iclass 27, count 0 2006.173.18:55:59.46#ibcon#about to read 3, iclass 27, count 0 2006.173.18:55:59.49#ibcon#read 3, iclass 27, count 0 2006.173.18:55:59.49#ibcon#about to read 4, iclass 27, count 0 2006.173.18:55:59.49#ibcon#read 4, iclass 27, count 0 2006.173.18:55:59.49#ibcon#about to read 5, iclass 27, count 0 2006.173.18:55:59.49#ibcon#read 5, iclass 27, count 0 2006.173.18:55:59.49#ibcon#about to read 6, iclass 27, count 0 2006.173.18:55:59.49#ibcon#read 6, iclass 27, count 0 2006.173.18:55:59.49#ibcon#end of sib2, iclass 27, count 0 2006.173.18:55:59.49#ibcon#*after write, iclass 27, count 0 2006.173.18:55:59.49#ibcon#*before return 0, iclass 27, count 0 2006.173.18:55:59.49#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.18:55:59.49#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.18:55:59.49#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.18:55:59.49#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.18:55:59.49$vck44/vblo=3,649.99 2006.173.18:55:59.49#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.18:55:59.49#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.18:55:59.49#ibcon#ireg 17 cls_cnt 0 2006.173.18:55:59.49#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.18:55:59.49#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.18:55:59.49#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.18:55:59.49#ibcon#enter wrdev, iclass 29, count 0 2006.173.18:55:59.49#ibcon#first serial, iclass 29, count 0 2006.173.18:55:59.49#ibcon#enter sib2, iclass 29, count 0 2006.173.18:55:59.49#ibcon#flushed, iclass 29, count 0 2006.173.18:55:59.49#ibcon#about to write, iclass 29, count 0 2006.173.18:55:59.49#ibcon#wrote, iclass 29, count 0 2006.173.18:55:59.49#ibcon#about to read 3, iclass 29, count 0 2006.173.18:55:59.51#ibcon#read 3, iclass 29, count 0 2006.173.18:55:59.51#ibcon#about to read 4, iclass 29, count 0 2006.173.18:55:59.51#ibcon#read 4, iclass 29, count 0 2006.173.18:55:59.51#ibcon#about to read 5, iclass 29, count 0 2006.173.18:55:59.51#ibcon#read 5, iclass 29, count 0 2006.173.18:55:59.51#ibcon#about to read 6, iclass 29, count 0 2006.173.18:55:59.51#ibcon#read 6, iclass 29, count 0 2006.173.18:55:59.51#ibcon#end of sib2, iclass 29, count 0 2006.173.18:55:59.51#ibcon#*mode == 0, iclass 29, count 0 2006.173.18:55:59.51#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.18:55:59.51#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.18:55:59.51#ibcon#*before write, iclass 29, count 0 2006.173.18:55:59.51#ibcon#enter sib2, iclass 29, count 0 2006.173.18:55:59.51#ibcon#flushed, iclass 29, count 0 2006.173.18:55:59.51#ibcon#about to write, iclass 29, count 0 2006.173.18:55:59.51#ibcon#wrote, iclass 29, count 0 2006.173.18:55:59.51#ibcon#about to read 3, iclass 29, count 0 2006.173.18:55:59.55#ibcon#read 3, iclass 29, count 0 2006.173.18:55:59.55#ibcon#about to read 4, iclass 29, count 0 2006.173.18:55:59.55#ibcon#read 4, iclass 29, count 0 2006.173.18:55:59.55#ibcon#about to read 5, iclass 29, count 0 2006.173.18:55:59.55#ibcon#read 5, iclass 29, count 0 2006.173.18:55:59.55#ibcon#about to read 6, iclass 29, count 0 2006.173.18:55:59.55#ibcon#read 6, iclass 29, count 0 2006.173.18:55:59.55#ibcon#end of sib2, iclass 29, count 0 2006.173.18:55:59.55#ibcon#*after write, iclass 29, count 0 2006.173.18:55:59.55#ibcon#*before return 0, iclass 29, count 0 2006.173.18:55:59.55#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.18:55:59.55#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.18:55:59.55#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.18:55:59.55#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.18:55:59.55$vck44/vb=3,4 2006.173.18:55:59.55#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.18:55:59.55#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.18:55:59.55#ibcon#ireg 11 cls_cnt 2 2006.173.18:55:59.55#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.18:55:59.61#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.18:55:59.61#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.18:55:59.61#ibcon#enter wrdev, iclass 31, count 2 2006.173.18:55:59.61#ibcon#first serial, iclass 31, count 2 2006.173.18:55:59.61#ibcon#enter sib2, iclass 31, count 2 2006.173.18:55:59.61#ibcon#flushed, iclass 31, count 2 2006.173.18:55:59.61#ibcon#about to write, iclass 31, count 2 2006.173.18:55:59.61#ibcon#wrote, iclass 31, count 2 2006.173.18:55:59.61#ibcon#about to read 3, iclass 31, count 2 2006.173.18:55:59.63#ibcon#read 3, iclass 31, count 2 2006.173.18:55:59.63#ibcon#about to read 4, iclass 31, count 2 2006.173.18:55:59.63#ibcon#read 4, iclass 31, count 2 2006.173.18:55:59.63#ibcon#about to read 5, iclass 31, count 2 2006.173.18:55:59.63#ibcon#read 5, iclass 31, count 2 2006.173.18:55:59.63#ibcon#about to read 6, iclass 31, count 2 2006.173.18:55:59.63#ibcon#read 6, iclass 31, count 2 2006.173.18:55:59.63#ibcon#end of sib2, iclass 31, count 2 2006.173.18:55:59.63#ibcon#*mode == 0, iclass 31, count 2 2006.173.18:55:59.63#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.18:55:59.63#ibcon#[27=AT03-04\r\n] 2006.173.18:55:59.63#ibcon#*before write, iclass 31, count 2 2006.173.18:55:59.63#ibcon#enter sib2, iclass 31, count 2 2006.173.18:55:59.63#ibcon#flushed, iclass 31, count 2 2006.173.18:55:59.63#ibcon#about to write, iclass 31, count 2 2006.173.18:55:59.63#ibcon#wrote, iclass 31, count 2 2006.173.18:55:59.63#ibcon#about to read 3, iclass 31, count 2 2006.173.18:55:59.66#ibcon#read 3, iclass 31, count 2 2006.173.18:55:59.66#ibcon#about to read 4, iclass 31, count 2 2006.173.18:55:59.66#ibcon#read 4, iclass 31, count 2 2006.173.18:55:59.66#ibcon#about to read 5, iclass 31, count 2 2006.173.18:55:59.66#ibcon#read 5, iclass 31, count 2 2006.173.18:55:59.66#ibcon#about to read 6, iclass 31, count 2 2006.173.18:55:59.66#ibcon#read 6, iclass 31, count 2 2006.173.18:55:59.66#ibcon#end of sib2, iclass 31, count 2 2006.173.18:55:59.66#ibcon#*after write, iclass 31, count 2 2006.173.18:55:59.66#ibcon#*before return 0, iclass 31, count 2 2006.173.18:55:59.66#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.18:55:59.66#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.18:55:59.66#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.18:55:59.66#ibcon#ireg 7 cls_cnt 0 2006.173.18:55:59.66#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.18:55:59.78#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.18:55:59.78#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.18:55:59.78#ibcon#enter wrdev, iclass 31, count 0 2006.173.18:55:59.78#ibcon#first serial, iclass 31, count 0 2006.173.18:55:59.78#ibcon#enter sib2, iclass 31, count 0 2006.173.18:55:59.78#ibcon#flushed, iclass 31, count 0 2006.173.18:55:59.78#ibcon#about to write, iclass 31, count 0 2006.173.18:55:59.78#ibcon#wrote, iclass 31, count 0 2006.173.18:55:59.78#ibcon#about to read 3, iclass 31, count 0 2006.173.18:55:59.80#ibcon#read 3, iclass 31, count 0 2006.173.18:55:59.80#ibcon#about to read 4, iclass 31, count 0 2006.173.18:55:59.80#ibcon#read 4, iclass 31, count 0 2006.173.18:55:59.80#ibcon#about to read 5, iclass 31, count 0 2006.173.18:55:59.80#ibcon#read 5, iclass 31, count 0 2006.173.18:55:59.80#ibcon#about to read 6, iclass 31, count 0 2006.173.18:55:59.80#ibcon#read 6, iclass 31, count 0 2006.173.18:55:59.80#ibcon#end of sib2, iclass 31, count 0 2006.173.18:55:59.80#ibcon#*mode == 0, iclass 31, count 0 2006.173.18:55:59.80#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.18:55:59.80#ibcon#[27=USB\r\n] 2006.173.18:55:59.80#ibcon#*before write, iclass 31, count 0 2006.173.18:55:59.80#ibcon#enter sib2, iclass 31, count 0 2006.173.18:55:59.80#ibcon#flushed, iclass 31, count 0 2006.173.18:55:59.80#ibcon#about to write, iclass 31, count 0 2006.173.18:55:59.80#ibcon#wrote, iclass 31, count 0 2006.173.18:55:59.80#ibcon#about to read 3, iclass 31, count 0 2006.173.18:55:59.83#ibcon#read 3, iclass 31, count 0 2006.173.18:55:59.83#ibcon#about to read 4, iclass 31, count 0 2006.173.18:55:59.83#ibcon#read 4, iclass 31, count 0 2006.173.18:55:59.83#ibcon#about to read 5, iclass 31, count 0 2006.173.18:55:59.83#ibcon#read 5, iclass 31, count 0 2006.173.18:55:59.83#ibcon#about to read 6, iclass 31, count 0 2006.173.18:55:59.83#ibcon#read 6, iclass 31, count 0 2006.173.18:55:59.83#ibcon#end of sib2, iclass 31, count 0 2006.173.18:55:59.83#ibcon#*after write, iclass 31, count 0 2006.173.18:55:59.83#ibcon#*before return 0, iclass 31, count 0 2006.173.18:55:59.83#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.18:55:59.83#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.18:55:59.83#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.18:55:59.83#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.18:55:59.83$vck44/vblo=4,679.99 2006.173.18:55:59.83#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.18:55:59.83#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.18:55:59.83#ibcon#ireg 17 cls_cnt 0 2006.173.18:55:59.83#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.18:55:59.83#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.18:55:59.83#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.18:55:59.83#ibcon#enter wrdev, iclass 33, count 0 2006.173.18:55:59.83#ibcon#first serial, iclass 33, count 0 2006.173.18:55:59.83#ibcon#enter sib2, iclass 33, count 0 2006.173.18:55:59.83#ibcon#flushed, iclass 33, count 0 2006.173.18:55:59.83#ibcon#about to write, iclass 33, count 0 2006.173.18:55:59.83#ibcon#wrote, iclass 33, count 0 2006.173.18:55:59.83#ibcon#about to read 3, iclass 33, count 0 2006.173.18:55:59.85#ibcon#read 3, iclass 33, count 0 2006.173.18:55:59.85#ibcon#about to read 4, iclass 33, count 0 2006.173.18:55:59.85#ibcon#read 4, iclass 33, count 0 2006.173.18:55:59.85#ibcon#about to read 5, iclass 33, count 0 2006.173.18:55:59.85#ibcon#read 5, iclass 33, count 0 2006.173.18:55:59.85#ibcon#about to read 6, iclass 33, count 0 2006.173.18:55:59.85#ibcon#read 6, iclass 33, count 0 2006.173.18:55:59.85#ibcon#end of sib2, iclass 33, count 0 2006.173.18:55:59.85#ibcon#*mode == 0, iclass 33, count 0 2006.173.18:55:59.85#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.18:55:59.85#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.18:55:59.85#ibcon#*before write, iclass 33, count 0 2006.173.18:55:59.85#ibcon#enter sib2, iclass 33, count 0 2006.173.18:55:59.85#ibcon#flushed, iclass 33, count 0 2006.173.18:55:59.85#ibcon#about to write, iclass 33, count 0 2006.173.18:55:59.85#ibcon#wrote, iclass 33, count 0 2006.173.18:55:59.85#ibcon#about to read 3, iclass 33, count 0 2006.173.18:55:59.89#ibcon#read 3, iclass 33, count 0 2006.173.18:55:59.89#ibcon#about to read 4, iclass 33, count 0 2006.173.18:55:59.89#ibcon#read 4, iclass 33, count 0 2006.173.18:55:59.89#ibcon#about to read 5, iclass 33, count 0 2006.173.18:55:59.89#ibcon#read 5, iclass 33, count 0 2006.173.18:55:59.89#ibcon#about to read 6, iclass 33, count 0 2006.173.18:55:59.89#ibcon#read 6, iclass 33, count 0 2006.173.18:55:59.89#ibcon#end of sib2, iclass 33, count 0 2006.173.18:55:59.89#ibcon#*after write, iclass 33, count 0 2006.173.18:55:59.89#ibcon#*before return 0, iclass 33, count 0 2006.173.18:55:59.89#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.18:55:59.89#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.18:55:59.89#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.18:55:59.89#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.18:55:59.89$vck44/vb=4,4 2006.173.18:55:59.89#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.18:55:59.89#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.18:55:59.89#ibcon#ireg 11 cls_cnt 2 2006.173.18:55:59.89#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.18:55:59.95#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.18:55:59.95#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.18:55:59.95#ibcon#enter wrdev, iclass 35, count 2 2006.173.18:55:59.95#ibcon#first serial, iclass 35, count 2 2006.173.18:55:59.95#ibcon#enter sib2, iclass 35, count 2 2006.173.18:55:59.95#ibcon#flushed, iclass 35, count 2 2006.173.18:55:59.95#ibcon#about to write, iclass 35, count 2 2006.173.18:55:59.95#ibcon#wrote, iclass 35, count 2 2006.173.18:55:59.95#ibcon#about to read 3, iclass 35, count 2 2006.173.18:55:59.97#ibcon#read 3, iclass 35, count 2 2006.173.18:55:59.97#ibcon#about to read 4, iclass 35, count 2 2006.173.18:55:59.97#ibcon#read 4, iclass 35, count 2 2006.173.18:55:59.97#ibcon#about to read 5, iclass 35, count 2 2006.173.18:55:59.97#ibcon#read 5, iclass 35, count 2 2006.173.18:55:59.97#ibcon#about to read 6, iclass 35, count 2 2006.173.18:55:59.97#ibcon#read 6, iclass 35, count 2 2006.173.18:55:59.97#ibcon#end of sib2, iclass 35, count 2 2006.173.18:55:59.97#ibcon#*mode == 0, iclass 35, count 2 2006.173.18:55:59.97#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.18:55:59.97#ibcon#[27=AT04-04\r\n] 2006.173.18:55:59.97#ibcon#*before write, iclass 35, count 2 2006.173.18:55:59.97#ibcon#enter sib2, iclass 35, count 2 2006.173.18:55:59.97#ibcon#flushed, iclass 35, count 2 2006.173.18:55:59.97#ibcon#about to write, iclass 35, count 2 2006.173.18:55:59.97#ibcon#wrote, iclass 35, count 2 2006.173.18:55:59.97#ibcon#about to read 3, iclass 35, count 2 2006.173.18:56:00.00#ibcon#read 3, iclass 35, count 2 2006.173.18:56:00.00#ibcon#about to read 4, iclass 35, count 2 2006.173.18:56:00.00#ibcon#read 4, iclass 35, count 2 2006.173.18:56:00.00#ibcon#about to read 5, iclass 35, count 2 2006.173.18:56:00.00#ibcon#read 5, iclass 35, count 2 2006.173.18:56:00.00#ibcon#about to read 6, iclass 35, count 2 2006.173.18:56:00.00#ibcon#read 6, iclass 35, count 2 2006.173.18:56:00.00#ibcon#end of sib2, iclass 35, count 2 2006.173.18:56:00.00#ibcon#*after write, iclass 35, count 2 2006.173.18:56:00.00#ibcon#*before return 0, iclass 35, count 2 2006.173.18:56:00.00#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.18:56:00.00#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.18:56:00.00#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.18:56:00.00#ibcon#ireg 7 cls_cnt 0 2006.173.18:56:00.00#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.18:56:00.12#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.18:56:00.12#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.18:56:00.12#ibcon#enter wrdev, iclass 35, count 0 2006.173.18:56:00.12#ibcon#first serial, iclass 35, count 0 2006.173.18:56:00.12#ibcon#enter sib2, iclass 35, count 0 2006.173.18:56:00.12#ibcon#flushed, iclass 35, count 0 2006.173.18:56:00.12#ibcon#about to write, iclass 35, count 0 2006.173.18:56:00.12#ibcon#wrote, iclass 35, count 0 2006.173.18:56:00.12#ibcon#about to read 3, iclass 35, count 0 2006.173.18:56:00.14#ibcon#read 3, iclass 35, count 0 2006.173.18:56:00.14#ibcon#about to read 4, iclass 35, count 0 2006.173.18:56:00.14#ibcon#read 4, iclass 35, count 0 2006.173.18:56:00.14#ibcon#about to read 5, iclass 35, count 0 2006.173.18:56:00.14#ibcon#read 5, iclass 35, count 0 2006.173.18:56:00.14#ibcon#about to read 6, iclass 35, count 0 2006.173.18:56:00.14#ibcon#read 6, iclass 35, count 0 2006.173.18:56:00.14#ibcon#end of sib2, iclass 35, count 0 2006.173.18:56:00.14#ibcon#*mode == 0, iclass 35, count 0 2006.173.18:56:00.14#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.18:56:00.14#ibcon#[27=USB\r\n] 2006.173.18:56:00.14#ibcon#*before write, iclass 35, count 0 2006.173.18:56:00.14#ibcon#enter sib2, iclass 35, count 0 2006.173.18:56:00.14#ibcon#flushed, iclass 35, count 0 2006.173.18:56:00.14#ibcon#about to write, iclass 35, count 0 2006.173.18:56:00.14#ibcon#wrote, iclass 35, count 0 2006.173.18:56:00.14#ibcon#about to read 3, iclass 35, count 0 2006.173.18:56:00.17#ibcon#read 3, iclass 35, count 0 2006.173.18:56:00.17#ibcon#about to read 4, iclass 35, count 0 2006.173.18:56:00.17#ibcon#read 4, iclass 35, count 0 2006.173.18:56:00.17#ibcon#about to read 5, iclass 35, count 0 2006.173.18:56:00.17#ibcon#read 5, iclass 35, count 0 2006.173.18:56:00.17#ibcon#about to read 6, iclass 35, count 0 2006.173.18:56:00.17#ibcon#read 6, iclass 35, count 0 2006.173.18:56:00.17#ibcon#end of sib2, iclass 35, count 0 2006.173.18:56:00.17#ibcon#*after write, iclass 35, count 0 2006.173.18:56:00.17#ibcon#*before return 0, iclass 35, count 0 2006.173.18:56:00.17#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.18:56:00.17#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.18:56:00.17#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.18:56:00.17#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.18:56:00.17$vck44/vblo=5,709.99 2006.173.18:56:00.17#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.18:56:00.17#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.18:56:00.17#ibcon#ireg 17 cls_cnt 0 2006.173.18:56:00.17#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.18:56:00.17#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.18:56:00.17#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.18:56:00.17#ibcon#enter wrdev, iclass 37, count 0 2006.173.18:56:00.17#ibcon#first serial, iclass 37, count 0 2006.173.18:56:00.17#ibcon#enter sib2, iclass 37, count 0 2006.173.18:56:00.17#ibcon#flushed, iclass 37, count 0 2006.173.18:56:00.17#ibcon#about to write, iclass 37, count 0 2006.173.18:56:00.17#ibcon#wrote, iclass 37, count 0 2006.173.18:56:00.17#ibcon#about to read 3, iclass 37, count 0 2006.173.18:56:00.19#ibcon#read 3, iclass 37, count 0 2006.173.18:56:00.19#ibcon#about to read 4, iclass 37, count 0 2006.173.18:56:00.19#ibcon#read 4, iclass 37, count 0 2006.173.18:56:00.19#ibcon#about to read 5, iclass 37, count 0 2006.173.18:56:00.19#ibcon#read 5, iclass 37, count 0 2006.173.18:56:00.19#ibcon#about to read 6, iclass 37, count 0 2006.173.18:56:00.19#ibcon#read 6, iclass 37, count 0 2006.173.18:56:00.19#ibcon#end of sib2, iclass 37, count 0 2006.173.18:56:00.19#ibcon#*mode == 0, iclass 37, count 0 2006.173.18:56:00.19#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.18:56:00.19#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.18:56:00.19#ibcon#*before write, iclass 37, count 0 2006.173.18:56:00.19#ibcon#enter sib2, iclass 37, count 0 2006.173.18:56:00.19#ibcon#flushed, iclass 37, count 0 2006.173.18:56:00.19#ibcon#about to write, iclass 37, count 0 2006.173.18:56:00.19#ibcon#wrote, iclass 37, count 0 2006.173.18:56:00.19#ibcon#about to read 3, iclass 37, count 0 2006.173.18:56:00.23#ibcon#read 3, iclass 37, count 0 2006.173.18:56:00.23#ibcon#about to read 4, iclass 37, count 0 2006.173.18:56:00.23#ibcon#read 4, iclass 37, count 0 2006.173.18:56:00.23#ibcon#about to read 5, iclass 37, count 0 2006.173.18:56:00.23#ibcon#read 5, iclass 37, count 0 2006.173.18:56:00.23#ibcon#about to read 6, iclass 37, count 0 2006.173.18:56:00.23#ibcon#read 6, iclass 37, count 0 2006.173.18:56:00.23#ibcon#end of sib2, iclass 37, count 0 2006.173.18:56:00.23#ibcon#*after write, iclass 37, count 0 2006.173.18:56:00.23#ibcon#*before return 0, iclass 37, count 0 2006.173.18:56:00.23#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.18:56:00.23#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.18:56:00.23#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.18:56:00.23#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.18:56:00.23$vck44/vb=5,4 2006.173.18:56:00.23#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.18:56:00.23#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.18:56:00.23#ibcon#ireg 11 cls_cnt 2 2006.173.18:56:00.23#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.18:56:00.29#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.18:56:00.29#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.18:56:00.29#ibcon#enter wrdev, iclass 39, count 2 2006.173.18:56:00.29#ibcon#first serial, iclass 39, count 2 2006.173.18:56:00.29#ibcon#enter sib2, iclass 39, count 2 2006.173.18:56:00.29#ibcon#flushed, iclass 39, count 2 2006.173.18:56:00.29#ibcon#about to write, iclass 39, count 2 2006.173.18:56:00.29#ibcon#wrote, iclass 39, count 2 2006.173.18:56:00.29#ibcon#about to read 3, iclass 39, count 2 2006.173.18:56:00.31#ibcon#read 3, iclass 39, count 2 2006.173.18:56:00.31#ibcon#about to read 4, iclass 39, count 2 2006.173.18:56:00.31#ibcon#read 4, iclass 39, count 2 2006.173.18:56:00.31#ibcon#about to read 5, iclass 39, count 2 2006.173.18:56:00.31#ibcon#read 5, iclass 39, count 2 2006.173.18:56:00.31#ibcon#about to read 6, iclass 39, count 2 2006.173.18:56:00.31#ibcon#read 6, iclass 39, count 2 2006.173.18:56:00.31#ibcon#end of sib2, iclass 39, count 2 2006.173.18:56:00.31#ibcon#*mode == 0, iclass 39, count 2 2006.173.18:56:00.31#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.18:56:00.31#ibcon#[27=AT05-04\r\n] 2006.173.18:56:00.31#ibcon#*before write, iclass 39, count 2 2006.173.18:56:00.31#ibcon#enter sib2, iclass 39, count 2 2006.173.18:56:00.31#ibcon#flushed, iclass 39, count 2 2006.173.18:56:00.31#ibcon#about to write, iclass 39, count 2 2006.173.18:56:00.31#ibcon#wrote, iclass 39, count 2 2006.173.18:56:00.31#ibcon#about to read 3, iclass 39, count 2 2006.173.18:56:00.34#ibcon#read 3, iclass 39, count 2 2006.173.18:56:00.34#ibcon#about to read 4, iclass 39, count 2 2006.173.18:56:00.34#ibcon#read 4, iclass 39, count 2 2006.173.18:56:00.34#ibcon#about to read 5, iclass 39, count 2 2006.173.18:56:00.34#ibcon#read 5, iclass 39, count 2 2006.173.18:56:00.34#ibcon#about to read 6, iclass 39, count 2 2006.173.18:56:00.34#ibcon#read 6, iclass 39, count 2 2006.173.18:56:00.34#ibcon#end of sib2, iclass 39, count 2 2006.173.18:56:00.34#ibcon#*after write, iclass 39, count 2 2006.173.18:56:00.34#ibcon#*before return 0, iclass 39, count 2 2006.173.18:56:00.34#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.18:56:00.34#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.18:56:00.34#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.18:56:00.34#ibcon#ireg 7 cls_cnt 0 2006.173.18:56:00.34#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.18:56:00.46#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.18:56:00.46#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.18:56:00.46#ibcon#enter wrdev, iclass 39, count 0 2006.173.18:56:00.46#ibcon#first serial, iclass 39, count 0 2006.173.18:56:00.46#ibcon#enter sib2, iclass 39, count 0 2006.173.18:56:00.46#ibcon#flushed, iclass 39, count 0 2006.173.18:56:00.46#ibcon#about to write, iclass 39, count 0 2006.173.18:56:00.46#ibcon#wrote, iclass 39, count 0 2006.173.18:56:00.46#ibcon#about to read 3, iclass 39, count 0 2006.173.18:56:00.48#ibcon#read 3, iclass 39, count 0 2006.173.18:56:00.48#ibcon#about to read 4, iclass 39, count 0 2006.173.18:56:00.48#ibcon#read 4, iclass 39, count 0 2006.173.18:56:00.48#ibcon#about to read 5, iclass 39, count 0 2006.173.18:56:00.48#ibcon#read 5, iclass 39, count 0 2006.173.18:56:00.48#ibcon#about to read 6, iclass 39, count 0 2006.173.18:56:00.48#ibcon#read 6, iclass 39, count 0 2006.173.18:56:00.48#ibcon#end of sib2, iclass 39, count 0 2006.173.18:56:00.48#ibcon#*mode == 0, iclass 39, count 0 2006.173.18:56:00.48#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.18:56:00.48#ibcon#[27=USB\r\n] 2006.173.18:56:00.48#ibcon#*before write, iclass 39, count 0 2006.173.18:56:00.48#ibcon#enter sib2, iclass 39, count 0 2006.173.18:56:00.48#ibcon#flushed, iclass 39, count 0 2006.173.18:56:00.48#ibcon#about to write, iclass 39, count 0 2006.173.18:56:00.48#ibcon#wrote, iclass 39, count 0 2006.173.18:56:00.48#ibcon#about to read 3, iclass 39, count 0 2006.173.18:56:00.51#ibcon#read 3, iclass 39, count 0 2006.173.18:56:00.51#ibcon#about to read 4, iclass 39, count 0 2006.173.18:56:00.51#ibcon#read 4, iclass 39, count 0 2006.173.18:56:00.51#ibcon#about to read 5, iclass 39, count 0 2006.173.18:56:00.51#ibcon#read 5, iclass 39, count 0 2006.173.18:56:00.51#ibcon#about to read 6, iclass 39, count 0 2006.173.18:56:00.51#ibcon#read 6, iclass 39, count 0 2006.173.18:56:00.51#ibcon#end of sib2, iclass 39, count 0 2006.173.18:56:00.51#ibcon#*after write, iclass 39, count 0 2006.173.18:56:00.51#ibcon#*before return 0, iclass 39, count 0 2006.173.18:56:00.51#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.18:56:00.51#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.18:56:00.51#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.18:56:00.51#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.18:56:00.51$vck44/vblo=6,719.99 2006.173.18:56:00.51#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.18:56:00.51#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.18:56:00.51#ibcon#ireg 17 cls_cnt 0 2006.173.18:56:00.51#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.18:56:00.51#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.18:56:00.51#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.18:56:00.51#ibcon#enter wrdev, iclass 3, count 0 2006.173.18:56:00.51#ibcon#first serial, iclass 3, count 0 2006.173.18:56:00.51#ibcon#enter sib2, iclass 3, count 0 2006.173.18:56:00.51#ibcon#flushed, iclass 3, count 0 2006.173.18:56:00.51#ibcon#about to write, iclass 3, count 0 2006.173.18:56:00.51#ibcon#wrote, iclass 3, count 0 2006.173.18:56:00.51#ibcon#about to read 3, iclass 3, count 0 2006.173.18:56:00.53#ibcon#read 3, iclass 3, count 0 2006.173.18:56:00.53#ibcon#about to read 4, iclass 3, count 0 2006.173.18:56:00.53#ibcon#read 4, iclass 3, count 0 2006.173.18:56:00.53#ibcon#about to read 5, iclass 3, count 0 2006.173.18:56:00.53#ibcon#read 5, iclass 3, count 0 2006.173.18:56:00.53#ibcon#about to read 6, iclass 3, count 0 2006.173.18:56:00.53#ibcon#read 6, iclass 3, count 0 2006.173.18:56:00.53#ibcon#end of sib2, iclass 3, count 0 2006.173.18:56:00.53#ibcon#*mode == 0, iclass 3, count 0 2006.173.18:56:00.53#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.18:56:00.53#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.18:56:00.53#ibcon#*before write, iclass 3, count 0 2006.173.18:56:00.53#ibcon#enter sib2, iclass 3, count 0 2006.173.18:56:00.53#ibcon#flushed, iclass 3, count 0 2006.173.18:56:00.53#ibcon#about to write, iclass 3, count 0 2006.173.18:56:00.53#ibcon#wrote, iclass 3, count 0 2006.173.18:56:00.53#ibcon#about to read 3, iclass 3, count 0 2006.173.18:56:00.57#ibcon#read 3, iclass 3, count 0 2006.173.18:56:00.57#ibcon#about to read 4, iclass 3, count 0 2006.173.18:56:00.57#ibcon#read 4, iclass 3, count 0 2006.173.18:56:00.57#ibcon#about to read 5, iclass 3, count 0 2006.173.18:56:00.57#ibcon#read 5, iclass 3, count 0 2006.173.18:56:00.57#ibcon#about to read 6, iclass 3, count 0 2006.173.18:56:00.57#ibcon#read 6, iclass 3, count 0 2006.173.18:56:00.57#ibcon#end of sib2, iclass 3, count 0 2006.173.18:56:00.57#ibcon#*after write, iclass 3, count 0 2006.173.18:56:00.57#ibcon#*before return 0, iclass 3, count 0 2006.173.18:56:00.57#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.18:56:00.57#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.18:56:00.57#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.18:56:00.57#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.18:56:00.57$vck44/vb=6,4 2006.173.18:56:00.57#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.18:56:00.57#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.18:56:00.57#ibcon#ireg 11 cls_cnt 2 2006.173.18:56:00.57#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.18:56:00.63#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.18:56:00.63#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.18:56:00.63#ibcon#enter wrdev, iclass 5, count 2 2006.173.18:56:00.63#ibcon#first serial, iclass 5, count 2 2006.173.18:56:00.63#ibcon#enter sib2, iclass 5, count 2 2006.173.18:56:00.63#ibcon#flushed, iclass 5, count 2 2006.173.18:56:00.63#ibcon#about to write, iclass 5, count 2 2006.173.18:56:00.63#ibcon#wrote, iclass 5, count 2 2006.173.18:56:00.63#ibcon#about to read 3, iclass 5, count 2 2006.173.18:56:00.65#ibcon#read 3, iclass 5, count 2 2006.173.18:56:00.65#ibcon#about to read 4, iclass 5, count 2 2006.173.18:56:00.65#ibcon#read 4, iclass 5, count 2 2006.173.18:56:00.65#ibcon#about to read 5, iclass 5, count 2 2006.173.18:56:00.65#ibcon#read 5, iclass 5, count 2 2006.173.18:56:00.65#ibcon#about to read 6, iclass 5, count 2 2006.173.18:56:00.65#ibcon#read 6, iclass 5, count 2 2006.173.18:56:00.65#ibcon#end of sib2, iclass 5, count 2 2006.173.18:56:00.65#ibcon#*mode == 0, iclass 5, count 2 2006.173.18:56:00.65#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.18:56:00.65#ibcon#[27=AT06-04\r\n] 2006.173.18:56:00.65#ibcon#*before write, iclass 5, count 2 2006.173.18:56:00.65#ibcon#enter sib2, iclass 5, count 2 2006.173.18:56:00.65#ibcon#flushed, iclass 5, count 2 2006.173.18:56:00.65#ibcon#about to write, iclass 5, count 2 2006.173.18:56:00.65#ibcon#wrote, iclass 5, count 2 2006.173.18:56:00.65#ibcon#about to read 3, iclass 5, count 2 2006.173.18:56:00.68#ibcon#read 3, iclass 5, count 2 2006.173.18:56:00.68#ibcon#about to read 4, iclass 5, count 2 2006.173.18:56:00.68#ibcon#read 4, iclass 5, count 2 2006.173.18:56:00.68#ibcon#about to read 5, iclass 5, count 2 2006.173.18:56:00.68#ibcon#read 5, iclass 5, count 2 2006.173.18:56:00.68#ibcon#about to read 6, iclass 5, count 2 2006.173.18:56:00.68#ibcon#read 6, iclass 5, count 2 2006.173.18:56:00.68#ibcon#end of sib2, iclass 5, count 2 2006.173.18:56:00.68#ibcon#*after write, iclass 5, count 2 2006.173.18:56:00.68#ibcon#*before return 0, iclass 5, count 2 2006.173.18:56:00.68#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.18:56:00.68#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.18:56:00.68#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.18:56:00.68#ibcon#ireg 7 cls_cnt 0 2006.173.18:56:00.68#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.18:56:00.80#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.18:56:00.80#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.18:56:00.80#ibcon#enter wrdev, iclass 5, count 0 2006.173.18:56:00.80#ibcon#first serial, iclass 5, count 0 2006.173.18:56:00.80#ibcon#enter sib2, iclass 5, count 0 2006.173.18:56:00.80#ibcon#flushed, iclass 5, count 0 2006.173.18:56:00.80#ibcon#about to write, iclass 5, count 0 2006.173.18:56:00.80#ibcon#wrote, iclass 5, count 0 2006.173.18:56:00.80#ibcon#about to read 3, iclass 5, count 0 2006.173.18:56:00.82#ibcon#read 3, iclass 5, count 0 2006.173.18:56:00.82#ibcon#about to read 4, iclass 5, count 0 2006.173.18:56:00.82#ibcon#read 4, iclass 5, count 0 2006.173.18:56:00.82#ibcon#about to read 5, iclass 5, count 0 2006.173.18:56:00.82#ibcon#read 5, iclass 5, count 0 2006.173.18:56:00.82#ibcon#about to read 6, iclass 5, count 0 2006.173.18:56:00.82#ibcon#read 6, iclass 5, count 0 2006.173.18:56:00.82#ibcon#end of sib2, iclass 5, count 0 2006.173.18:56:00.82#ibcon#*mode == 0, iclass 5, count 0 2006.173.18:56:00.82#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.18:56:00.82#ibcon#[27=USB\r\n] 2006.173.18:56:00.82#ibcon#*before write, iclass 5, count 0 2006.173.18:56:00.82#ibcon#enter sib2, iclass 5, count 0 2006.173.18:56:00.82#ibcon#flushed, iclass 5, count 0 2006.173.18:56:00.82#ibcon#about to write, iclass 5, count 0 2006.173.18:56:00.82#ibcon#wrote, iclass 5, count 0 2006.173.18:56:00.82#ibcon#about to read 3, iclass 5, count 0 2006.173.18:56:00.85#ibcon#read 3, iclass 5, count 0 2006.173.18:56:00.85#ibcon#about to read 4, iclass 5, count 0 2006.173.18:56:00.85#ibcon#read 4, iclass 5, count 0 2006.173.18:56:00.85#ibcon#about to read 5, iclass 5, count 0 2006.173.18:56:00.85#ibcon#read 5, iclass 5, count 0 2006.173.18:56:00.85#ibcon#about to read 6, iclass 5, count 0 2006.173.18:56:00.85#ibcon#read 6, iclass 5, count 0 2006.173.18:56:00.85#ibcon#end of sib2, iclass 5, count 0 2006.173.18:56:00.85#ibcon#*after write, iclass 5, count 0 2006.173.18:56:00.85#ibcon#*before return 0, iclass 5, count 0 2006.173.18:56:00.85#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.18:56:00.85#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.18:56:00.85#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.18:56:00.85#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.18:56:00.85$vck44/vblo=7,734.99 2006.173.18:56:00.85#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.18:56:00.85#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.18:56:00.85#ibcon#ireg 17 cls_cnt 0 2006.173.18:56:00.85#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.18:56:00.85#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.18:56:00.85#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.18:56:00.85#ibcon#enter wrdev, iclass 7, count 0 2006.173.18:56:00.85#ibcon#first serial, iclass 7, count 0 2006.173.18:56:00.85#ibcon#enter sib2, iclass 7, count 0 2006.173.18:56:00.85#ibcon#flushed, iclass 7, count 0 2006.173.18:56:00.85#ibcon#about to write, iclass 7, count 0 2006.173.18:56:00.85#ibcon#wrote, iclass 7, count 0 2006.173.18:56:00.85#ibcon#about to read 3, iclass 7, count 0 2006.173.18:56:00.87#ibcon#read 3, iclass 7, count 0 2006.173.18:56:00.87#ibcon#about to read 4, iclass 7, count 0 2006.173.18:56:00.87#ibcon#read 4, iclass 7, count 0 2006.173.18:56:00.87#ibcon#about to read 5, iclass 7, count 0 2006.173.18:56:00.87#ibcon#read 5, iclass 7, count 0 2006.173.18:56:00.87#ibcon#about to read 6, iclass 7, count 0 2006.173.18:56:00.87#ibcon#read 6, iclass 7, count 0 2006.173.18:56:00.87#ibcon#end of sib2, iclass 7, count 0 2006.173.18:56:00.87#ibcon#*mode == 0, iclass 7, count 0 2006.173.18:56:00.87#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.18:56:00.87#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.18:56:00.87#ibcon#*before write, iclass 7, count 0 2006.173.18:56:00.87#ibcon#enter sib2, iclass 7, count 0 2006.173.18:56:00.87#ibcon#flushed, iclass 7, count 0 2006.173.18:56:00.87#ibcon#about to write, iclass 7, count 0 2006.173.18:56:00.87#ibcon#wrote, iclass 7, count 0 2006.173.18:56:00.87#ibcon#about to read 3, iclass 7, count 0 2006.173.18:56:00.91#ibcon#read 3, iclass 7, count 0 2006.173.18:56:00.91#ibcon#about to read 4, iclass 7, count 0 2006.173.18:56:00.91#ibcon#read 4, iclass 7, count 0 2006.173.18:56:00.91#ibcon#about to read 5, iclass 7, count 0 2006.173.18:56:00.91#ibcon#read 5, iclass 7, count 0 2006.173.18:56:00.91#ibcon#about to read 6, iclass 7, count 0 2006.173.18:56:00.91#ibcon#read 6, iclass 7, count 0 2006.173.18:56:00.91#ibcon#end of sib2, iclass 7, count 0 2006.173.18:56:00.91#ibcon#*after write, iclass 7, count 0 2006.173.18:56:00.91#ibcon#*before return 0, iclass 7, count 0 2006.173.18:56:00.91#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.18:56:00.91#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.18:56:00.91#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.18:56:00.91#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.18:56:00.91$vck44/vb=7,4 2006.173.18:56:00.91#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.18:56:00.91#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.18:56:00.91#ibcon#ireg 11 cls_cnt 2 2006.173.18:56:00.91#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.18:56:00.97#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.18:56:00.97#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.18:56:00.97#ibcon#enter wrdev, iclass 11, count 2 2006.173.18:56:00.97#ibcon#first serial, iclass 11, count 2 2006.173.18:56:00.97#ibcon#enter sib2, iclass 11, count 2 2006.173.18:56:00.97#ibcon#flushed, iclass 11, count 2 2006.173.18:56:00.97#ibcon#about to write, iclass 11, count 2 2006.173.18:56:00.97#ibcon#wrote, iclass 11, count 2 2006.173.18:56:00.97#ibcon#about to read 3, iclass 11, count 2 2006.173.18:56:00.99#ibcon#read 3, iclass 11, count 2 2006.173.18:56:00.99#ibcon#about to read 4, iclass 11, count 2 2006.173.18:56:00.99#ibcon#read 4, iclass 11, count 2 2006.173.18:56:00.99#ibcon#about to read 5, iclass 11, count 2 2006.173.18:56:00.99#ibcon#read 5, iclass 11, count 2 2006.173.18:56:00.99#ibcon#about to read 6, iclass 11, count 2 2006.173.18:56:00.99#ibcon#read 6, iclass 11, count 2 2006.173.18:56:00.99#ibcon#end of sib2, iclass 11, count 2 2006.173.18:56:00.99#ibcon#*mode == 0, iclass 11, count 2 2006.173.18:56:00.99#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.18:56:00.99#ibcon#[27=AT07-04\r\n] 2006.173.18:56:00.99#ibcon#*before write, iclass 11, count 2 2006.173.18:56:00.99#ibcon#enter sib2, iclass 11, count 2 2006.173.18:56:00.99#ibcon#flushed, iclass 11, count 2 2006.173.18:56:00.99#ibcon#about to write, iclass 11, count 2 2006.173.18:56:00.99#ibcon#wrote, iclass 11, count 2 2006.173.18:56:00.99#ibcon#about to read 3, iclass 11, count 2 2006.173.18:56:01.02#ibcon#read 3, iclass 11, count 2 2006.173.18:56:01.02#ibcon#about to read 4, iclass 11, count 2 2006.173.18:56:01.02#ibcon#read 4, iclass 11, count 2 2006.173.18:56:01.02#ibcon#about to read 5, iclass 11, count 2 2006.173.18:56:01.02#ibcon#read 5, iclass 11, count 2 2006.173.18:56:01.02#ibcon#about to read 6, iclass 11, count 2 2006.173.18:56:01.02#ibcon#read 6, iclass 11, count 2 2006.173.18:56:01.02#ibcon#end of sib2, iclass 11, count 2 2006.173.18:56:01.02#ibcon#*after write, iclass 11, count 2 2006.173.18:56:01.02#ibcon#*before return 0, iclass 11, count 2 2006.173.18:56:01.02#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.18:56:01.02#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.18:56:01.02#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.18:56:01.02#ibcon#ireg 7 cls_cnt 0 2006.173.18:56:01.02#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.18:56:01.14#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.18:56:01.14#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.18:56:01.14#ibcon#enter wrdev, iclass 11, count 0 2006.173.18:56:01.14#ibcon#first serial, iclass 11, count 0 2006.173.18:56:01.14#ibcon#enter sib2, iclass 11, count 0 2006.173.18:56:01.14#ibcon#flushed, iclass 11, count 0 2006.173.18:56:01.14#ibcon#about to write, iclass 11, count 0 2006.173.18:56:01.14#ibcon#wrote, iclass 11, count 0 2006.173.18:56:01.14#ibcon#about to read 3, iclass 11, count 0 2006.173.18:56:01.16#ibcon#read 3, iclass 11, count 0 2006.173.18:56:01.16#ibcon#about to read 4, iclass 11, count 0 2006.173.18:56:01.16#ibcon#read 4, iclass 11, count 0 2006.173.18:56:01.16#ibcon#about to read 5, iclass 11, count 0 2006.173.18:56:01.16#ibcon#read 5, iclass 11, count 0 2006.173.18:56:01.16#ibcon#about to read 6, iclass 11, count 0 2006.173.18:56:01.16#ibcon#read 6, iclass 11, count 0 2006.173.18:56:01.16#ibcon#end of sib2, iclass 11, count 0 2006.173.18:56:01.16#ibcon#*mode == 0, iclass 11, count 0 2006.173.18:56:01.16#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.18:56:01.16#ibcon#[27=USB\r\n] 2006.173.18:56:01.16#ibcon#*before write, iclass 11, count 0 2006.173.18:56:01.16#ibcon#enter sib2, iclass 11, count 0 2006.173.18:56:01.16#ibcon#flushed, iclass 11, count 0 2006.173.18:56:01.16#ibcon#about to write, iclass 11, count 0 2006.173.18:56:01.16#ibcon#wrote, iclass 11, count 0 2006.173.18:56:01.16#ibcon#about to read 3, iclass 11, count 0 2006.173.18:56:01.19#ibcon#read 3, iclass 11, count 0 2006.173.18:56:01.19#ibcon#about to read 4, iclass 11, count 0 2006.173.18:56:01.19#ibcon#read 4, iclass 11, count 0 2006.173.18:56:01.19#ibcon#about to read 5, iclass 11, count 0 2006.173.18:56:01.19#ibcon#read 5, iclass 11, count 0 2006.173.18:56:01.19#ibcon#about to read 6, iclass 11, count 0 2006.173.18:56:01.19#ibcon#read 6, iclass 11, count 0 2006.173.18:56:01.19#ibcon#end of sib2, iclass 11, count 0 2006.173.18:56:01.19#ibcon#*after write, iclass 11, count 0 2006.173.18:56:01.19#ibcon#*before return 0, iclass 11, count 0 2006.173.18:56:01.19#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.18:56:01.19#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.18:56:01.19#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.18:56:01.19#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.18:56:01.19$vck44/vblo=8,744.99 2006.173.18:56:01.19#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.18:56:01.19#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.18:56:01.19#ibcon#ireg 17 cls_cnt 0 2006.173.18:56:01.19#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.18:56:01.19#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.18:56:01.19#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.18:56:01.19#ibcon#enter wrdev, iclass 13, count 0 2006.173.18:56:01.19#ibcon#first serial, iclass 13, count 0 2006.173.18:56:01.19#ibcon#enter sib2, iclass 13, count 0 2006.173.18:56:01.19#ibcon#flushed, iclass 13, count 0 2006.173.18:56:01.19#ibcon#about to write, iclass 13, count 0 2006.173.18:56:01.19#ibcon#wrote, iclass 13, count 0 2006.173.18:56:01.19#ibcon#about to read 3, iclass 13, count 0 2006.173.18:56:01.21#ibcon#read 3, iclass 13, count 0 2006.173.18:56:01.21#ibcon#about to read 4, iclass 13, count 0 2006.173.18:56:01.21#ibcon#read 4, iclass 13, count 0 2006.173.18:56:01.21#ibcon#about to read 5, iclass 13, count 0 2006.173.18:56:01.21#ibcon#read 5, iclass 13, count 0 2006.173.18:56:01.21#ibcon#about to read 6, iclass 13, count 0 2006.173.18:56:01.21#ibcon#read 6, iclass 13, count 0 2006.173.18:56:01.21#ibcon#end of sib2, iclass 13, count 0 2006.173.18:56:01.21#ibcon#*mode == 0, iclass 13, count 0 2006.173.18:56:01.21#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.18:56:01.21#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.18:56:01.21#ibcon#*before write, iclass 13, count 0 2006.173.18:56:01.21#ibcon#enter sib2, iclass 13, count 0 2006.173.18:56:01.21#ibcon#flushed, iclass 13, count 0 2006.173.18:56:01.21#ibcon#about to write, iclass 13, count 0 2006.173.18:56:01.21#ibcon#wrote, iclass 13, count 0 2006.173.18:56:01.21#ibcon#about to read 3, iclass 13, count 0 2006.173.18:56:01.25#ibcon#read 3, iclass 13, count 0 2006.173.18:56:01.25#ibcon#about to read 4, iclass 13, count 0 2006.173.18:56:01.25#ibcon#read 4, iclass 13, count 0 2006.173.18:56:01.25#ibcon#about to read 5, iclass 13, count 0 2006.173.18:56:01.25#ibcon#read 5, iclass 13, count 0 2006.173.18:56:01.25#ibcon#about to read 6, iclass 13, count 0 2006.173.18:56:01.25#ibcon#read 6, iclass 13, count 0 2006.173.18:56:01.25#ibcon#end of sib2, iclass 13, count 0 2006.173.18:56:01.25#ibcon#*after write, iclass 13, count 0 2006.173.18:56:01.25#ibcon#*before return 0, iclass 13, count 0 2006.173.18:56:01.25#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.18:56:01.25#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.18:56:01.25#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.18:56:01.25#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.18:56:01.25$vck44/vb=8,4 2006.173.18:56:01.25#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.18:56:01.25#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.18:56:01.25#ibcon#ireg 11 cls_cnt 2 2006.173.18:56:01.25#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.18:56:01.31#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.18:56:01.31#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.18:56:01.31#ibcon#enter wrdev, iclass 15, count 2 2006.173.18:56:01.31#ibcon#first serial, iclass 15, count 2 2006.173.18:56:01.31#ibcon#enter sib2, iclass 15, count 2 2006.173.18:56:01.31#ibcon#flushed, iclass 15, count 2 2006.173.18:56:01.31#ibcon#about to write, iclass 15, count 2 2006.173.18:56:01.31#ibcon#wrote, iclass 15, count 2 2006.173.18:56:01.31#ibcon#about to read 3, iclass 15, count 2 2006.173.18:56:01.33#ibcon#read 3, iclass 15, count 2 2006.173.18:56:01.33#ibcon#about to read 4, iclass 15, count 2 2006.173.18:56:01.33#ibcon#read 4, iclass 15, count 2 2006.173.18:56:01.33#ibcon#about to read 5, iclass 15, count 2 2006.173.18:56:01.33#ibcon#read 5, iclass 15, count 2 2006.173.18:56:01.33#ibcon#about to read 6, iclass 15, count 2 2006.173.18:56:01.33#ibcon#read 6, iclass 15, count 2 2006.173.18:56:01.33#ibcon#end of sib2, iclass 15, count 2 2006.173.18:56:01.33#ibcon#*mode == 0, iclass 15, count 2 2006.173.18:56:01.33#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.18:56:01.33#ibcon#[27=AT08-04\r\n] 2006.173.18:56:01.33#ibcon#*before write, iclass 15, count 2 2006.173.18:56:01.33#ibcon#enter sib2, iclass 15, count 2 2006.173.18:56:01.33#ibcon#flushed, iclass 15, count 2 2006.173.18:56:01.33#ibcon#about to write, iclass 15, count 2 2006.173.18:56:01.33#ibcon#wrote, iclass 15, count 2 2006.173.18:56:01.33#ibcon#about to read 3, iclass 15, count 2 2006.173.18:56:01.36#ibcon#read 3, iclass 15, count 2 2006.173.18:56:01.36#ibcon#about to read 4, iclass 15, count 2 2006.173.18:56:01.36#ibcon#read 4, iclass 15, count 2 2006.173.18:56:01.36#ibcon#about to read 5, iclass 15, count 2 2006.173.18:56:01.36#ibcon#read 5, iclass 15, count 2 2006.173.18:56:01.36#ibcon#about to read 6, iclass 15, count 2 2006.173.18:56:01.36#ibcon#read 6, iclass 15, count 2 2006.173.18:56:01.36#ibcon#end of sib2, iclass 15, count 2 2006.173.18:56:01.36#ibcon#*after write, iclass 15, count 2 2006.173.18:56:01.36#ibcon#*before return 0, iclass 15, count 2 2006.173.18:56:01.36#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.18:56:01.36#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.18:56:01.36#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.18:56:01.36#ibcon#ireg 7 cls_cnt 0 2006.173.18:56:01.36#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.18:56:01.48#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.18:56:01.48#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.18:56:01.48#ibcon#enter wrdev, iclass 15, count 0 2006.173.18:56:01.48#ibcon#first serial, iclass 15, count 0 2006.173.18:56:01.48#ibcon#enter sib2, iclass 15, count 0 2006.173.18:56:01.48#ibcon#flushed, iclass 15, count 0 2006.173.18:56:01.48#ibcon#about to write, iclass 15, count 0 2006.173.18:56:01.48#ibcon#wrote, iclass 15, count 0 2006.173.18:56:01.48#ibcon#about to read 3, iclass 15, count 0 2006.173.18:56:01.50#ibcon#read 3, iclass 15, count 0 2006.173.18:56:01.50#ibcon#about to read 4, iclass 15, count 0 2006.173.18:56:01.50#ibcon#read 4, iclass 15, count 0 2006.173.18:56:01.50#ibcon#about to read 5, iclass 15, count 0 2006.173.18:56:01.50#ibcon#read 5, iclass 15, count 0 2006.173.18:56:01.50#ibcon#about to read 6, iclass 15, count 0 2006.173.18:56:01.50#ibcon#read 6, iclass 15, count 0 2006.173.18:56:01.50#ibcon#end of sib2, iclass 15, count 0 2006.173.18:56:01.50#ibcon#*mode == 0, iclass 15, count 0 2006.173.18:56:01.50#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.18:56:01.50#ibcon#[27=USB\r\n] 2006.173.18:56:01.50#ibcon#*before write, iclass 15, count 0 2006.173.18:56:01.50#ibcon#enter sib2, iclass 15, count 0 2006.173.18:56:01.50#ibcon#flushed, iclass 15, count 0 2006.173.18:56:01.50#ibcon#about to write, iclass 15, count 0 2006.173.18:56:01.50#ibcon#wrote, iclass 15, count 0 2006.173.18:56:01.50#ibcon#about to read 3, iclass 15, count 0 2006.173.18:56:01.53#ibcon#read 3, iclass 15, count 0 2006.173.18:56:01.53#ibcon#about to read 4, iclass 15, count 0 2006.173.18:56:01.53#ibcon#read 4, iclass 15, count 0 2006.173.18:56:01.53#ibcon#about to read 5, iclass 15, count 0 2006.173.18:56:01.53#ibcon#read 5, iclass 15, count 0 2006.173.18:56:01.53#ibcon#about to read 6, iclass 15, count 0 2006.173.18:56:01.53#ibcon#read 6, iclass 15, count 0 2006.173.18:56:01.53#ibcon#end of sib2, iclass 15, count 0 2006.173.18:56:01.53#ibcon#*after write, iclass 15, count 0 2006.173.18:56:01.53#ibcon#*before return 0, iclass 15, count 0 2006.173.18:56:01.53#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.18:56:01.53#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.18:56:01.53#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.18:56:01.53#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.18:56:01.53$vck44/vabw=wide 2006.173.18:56:01.53#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.18:56:01.53#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.18:56:01.53#ibcon#ireg 8 cls_cnt 0 2006.173.18:56:01.53#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.18:56:01.53#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.18:56:01.53#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.18:56:01.53#ibcon#enter wrdev, iclass 17, count 0 2006.173.18:56:01.53#ibcon#first serial, iclass 17, count 0 2006.173.18:56:01.53#ibcon#enter sib2, iclass 17, count 0 2006.173.18:56:01.53#ibcon#flushed, iclass 17, count 0 2006.173.18:56:01.53#ibcon#about to write, iclass 17, count 0 2006.173.18:56:01.53#ibcon#wrote, iclass 17, count 0 2006.173.18:56:01.53#ibcon#about to read 3, iclass 17, count 0 2006.173.18:56:01.55#ibcon#read 3, iclass 17, count 0 2006.173.18:56:01.55#ibcon#about to read 4, iclass 17, count 0 2006.173.18:56:01.55#ibcon#read 4, iclass 17, count 0 2006.173.18:56:01.55#ibcon#about to read 5, iclass 17, count 0 2006.173.18:56:01.55#ibcon#read 5, iclass 17, count 0 2006.173.18:56:01.55#ibcon#about to read 6, iclass 17, count 0 2006.173.18:56:01.55#ibcon#read 6, iclass 17, count 0 2006.173.18:56:01.55#ibcon#end of sib2, iclass 17, count 0 2006.173.18:56:01.55#ibcon#*mode == 0, iclass 17, count 0 2006.173.18:56:01.55#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.18:56:01.55#ibcon#[25=BW32\r\n] 2006.173.18:56:01.55#ibcon#*before write, iclass 17, count 0 2006.173.18:56:01.55#ibcon#enter sib2, iclass 17, count 0 2006.173.18:56:01.55#ibcon#flushed, iclass 17, count 0 2006.173.18:56:01.55#ibcon#about to write, iclass 17, count 0 2006.173.18:56:01.55#ibcon#wrote, iclass 17, count 0 2006.173.18:56:01.55#ibcon#about to read 3, iclass 17, count 0 2006.173.18:56:01.58#ibcon#read 3, iclass 17, count 0 2006.173.18:56:01.58#ibcon#about to read 4, iclass 17, count 0 2006.173.18:56:01.58#ibcon#read 4, iclass 17, count 0 2006.173.18:56:01.58#ibcon#about to read 5, iclass 17, count 0 2006.173.18:56:01.58#ibcon#read 5, iclass 17, count 0 2006.173.18:56:01.58#ibcon#about to read 6, iclass 17, count 0 2006.173.18:56:01.58#ibcon#read 6, iclass 17, count 0 2006.173.18:56:01.58#ibcon#end of sib2, iclass 17, count 0 2006.173.18:56:01.58#ibcon#*after write, iclass 17, count 0 2006.173.18:56:01.58#ibcon#*before return 0, iclass 17, count 0 2006.173.18:56:01.58#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.18:56:01.58#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.18:56:01.58#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.18:56:01.58#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.18:56:01.58$vck44/vbbw=wide 2006.173.18:56:01.58#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.18:56:01.58#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.18:56:01.58#ibcon#ireg 8 cls_cnt 0 2006.173.18:56:01.58#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.18:56:01.65#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.18:56:01.65#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.18:56:01.65#ibcon#enter wrdev, iclass 19, count 0 2006.173.18:56:01.65#ibcon#first serial, iclass 19, count 0 2006.173.18:56:01.65#ibcon#enter sib2, iclass 19, count 0 2006.173.18:56:01.65#ibcon#flushed, iclass 19, count 0 2006.173.18:56:01.65#ibcon#about to write, iclass 19, count 0 2006.173.18:56:01.65#ibcon#wrote, iclass 19, count 0 2006.173.18:56:01.65#ibcon#about to read 3, iclass 19, count 0 2006.173.18:56:01.67#ibcon#read 3, iclass 19, count 0 2006.173.18:56:01.67#ibcon#about to read 4, iclass 19, count 0 2006.173.18:56:01.67#ibcon#read 4, iclass 19, count 0 2006.173.18:56:01.67#ibcon#about to read 5, iclass 19, count 0 2006.173.18:56:01.67#ibcon#read 5, iclass 19, count 0 2006.173.18:56:01.67#ibcon#about to read 6, iclass 19, count 0 2006.173.18:56:01.67#ibcon#read 6, iclass 19, count 0 2006.173.18:56:01.67#ibcon#end of sib2, iclass 19, count 0 2006.173.18:56:01.67#ibcon#*mode == 0, iclass 19, count 0 2006.173.18:56:01.67#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.18:56:01.67#ibcon#[27=BW32\r\n] 2006.173.18:56:01.67#ibcon#*before write, iclass 19, count 0 2006.173.18:56:01.67#ibcon#enter sib2, iclass 19, count 0 2006.173.18:56:01.67#ibcon#flushed, iclass 19, count 0 2006.173.18:56:01.67#ibcon#about to write, iclass 19, count 0 2006.173.18:56:01.67#ibcon#wrote, iclass 19, count 0 2006.173.18:56:01.67#ibcon#about to read 3, iclass 19, count 0 2006.173.18:56:01.70#ibcon#read 3, iclass 19, count 0 2006.173.18:56:01.70#ibcon#about to read 4, iclass 19, count 0 2006.173.18:56:01.70#ibcon#read 4, iclass 19, count 0 2006.173.18:56:01.70#ibcon#about to read 5, iclass 19, count 0 2006.173.18:56:01.70#ibcon#read 5, iclass 19, count 0 2006.173.18:56:01.70#ibcon#about to read 6, iclass 19, count 0 2006.173.18:56:01.70#ibcon#read 6, iclass 19, count 0 2006.173.18:56:01.70#ibcon#end of sib2, iclass 19, count 0 2006.173.18:56:01.70#ibcon#*after write, iclass 19, count 0 2006.173.18:56:01.70#ibcon#*before return 0, iclass 19, count 0 2006.173.18:56:01.70#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.18:56:01.70#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.18:56:01.70#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.18:56:01.70#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.18:56:01.70$setupk4/ifdk4 2006.173.18:56:01.70$ifdk4/lo= 2006.173.18:56:01.70$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.18:56:01.70$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.18:56:01.70$ifdk4/patch= 2006.173.18:56:01.70$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.18:56:01.70$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.18:56:01.70$setupk4/!*+20s 2006.173.18:56:03.57#abcon#<5=/12 0.4 1.0 19.631001002.5\r\n> 2006.173.18:56:03.59#abcon#{5=INTERFACE CLEAR} 2006.173.18:56:03.65#abcon#[5=S1D000X0/0*\r\n] 2006.173.18:56:13.74#abcon#<5=/12 0.4 1.0 19.631001002.5\r\n> 2006.173.18:56:13.76#abcon#{5=INTERFACE CLEAR} 2006.173.18:56:13.82#abcon#[5=S1D000X0/0*\r\n] 2006.173.18:56:15.13#trakl#Source acquired 2006.173.18:56:16.13#flagr#flagr/antenna,acquired 2006.173.18:56:16.21$setupk4/"tpicd 2006.173.18:56:16.21$setupk4/echo=off 2006.173.18:56:16.21$setupk4/xlog=off 2006.173.18:56:16.21:!2006.173.19:00:31 2006.173.19:00:31.00:preob 2006.173.19:00:32.14/onsource/TRACKING 2006.173.19:00:32.14:!2006.173.19:00:41 2006.173.19:00:41.00:"tape 2006.173.19:00:41.00:"st=record 2006.173.19:00:41.00:data_valid=on 2006.173.19:00:41.00:midob 2006.173.19:00:41.14/onsource/TRACKING 2006.173.19:00:41.14/wx/19.58,1002.5,100 2006.173.19:00:41.26/cable/+6.5146E-03 2006.173.19:00:42.35/va/01,07,usb,yes,44,47 2006.173.19:00:42.35/va/02,06,usb,yes,43,44 2006.173.19:00:42.35/va/03,05,usb,yes,55,57 2006.173.19:00:42.35/va/04,06,usb,yes,45,47 2006.173.19:00:42.35/va/05,04,usb,yes,35,36 2006.173.19:00:42.35/va/06,03,usb,yes,49,49 2006.173.19:00:42.35/va/07,04,usb,yes,40,41 2006.173.19:00:42.35/va/08,04,usb,yes,34,41 2006.173.19:00:42.58/valo/01,524.99,yes,locked 2006.173.19:00:42.58/valo/02,534.99,yes,locked 2006.173.19:00:42.58/valo/03,564.99,yes,locked 2006.173.19:00:42.58/valo/04,624.99,yes,locked 2006.173.19:00:42.58/valo/05,734.99,yes,locked 2006.173.19:00:42.58/valo/06,814.99,yes,locked 2006.173.19:00:42.58/valo/07,864.99,yes,locked 2006.173.19:00:42.58/valo/08,884.99,yes,locked 2006.173.19:00:43.67/vb/01,04,usb,yes,32,31 2006.173.19:00:43.67/vb/02,04,usb,yes,35,36 2006.173.19:00:43.67/vb/03,04,usb,yes,31,35 2006.173.19:00:43.67/vb/04,04,usb,yes,36,35 2006.173.19:00:43.67/vb/05,04,usb,yes,28,31 2006.173.19:00:43.67/vb/06,04,usb,yes,33,29 2006.173.19:00:43.67/vb/07,04,usb,yes,33,33 2006.173.19:00:43.67/vb/08,04,usb,yes,30,34 2006.173.19:00:43.91/vblo/01,629.99,yes,locked 2006.173.19:00:43.91/vblo/02,634.99,yes,locked 2006.173.19:00:43.91/vblo/03,649.99,yes,locked 2006.173.19:00:43.91/vblo/04,679.99,yes,locked 2006.173.19:00:43.91/vblo/05,709.99,yes,locked 2006.173.19:00:43.91/vblo/06,719.99,yes,locked 2006.173.19:00:43.91/vblo/07,734.99,yes,locked 2006.173.19:00:43.91/vblo/08,744.99,yes,locked 2006.173.19:00:44.06/vabw/8 2006.173.19:00:44.21/vbbw/8 2006.173.19:00:44.30/xfe/off,on,15.2 2006.173.19:00:44.69/ifatt/23,28,28,28 2006.173.19:00:45.08/fmout-gps/S +3.88E-07 2006.173.19:00:45.12:!2006.173.19:02:21 2006.173.19:02:21.01:data_valid=off 2006.173.19:02:21.01:"et 2006.173.19:02:21.01:!+3s 2006.173.19:02:24.02:"tape 2006.173.19:02:24.02:postob 2006.173.19:02:24.09/cable/+6.5156E-03 2006.173.19:02:24.09/wx/19.58,1002.5,100 2006.173.19:02:25.08/fmout-gps/S +3.88E-07 2006.173.19:02:25.08:scan_name=173-1903,jd0606,570 2006.173.19:02:25.08:source=0133+476,013658.59,475129.1,2000.0,ccw 2006.173.19:02:26.14#flagr#flagr/antenna,new-source 2006.173.19:02:26.14:checkk5 2006.173.19:02:26.54/chk_autoobs//k5ts1/ autoobs is running! 2006.173.19:02:26.93/chk_autoobs//k5ts2/ autoobs is running! 2006.173.19:02:27.34/chk_autoobs//k5ts3/ autoobs is running! 2006.173.19:02:27.72/chk_autoobs//k5ts4/ autoobs is running! 2006.173.19:02:28.12/chk_obsdata//k5ts1/T1731900??a.dat file size is correct (nominal:400MB, actual:400MB). 2006.173.19:02:28.54/chk_obsdata//k5ts2/T1731900??b.dat file size is correct (nominal:400MB, actual:400MB). 2006.173.19:02:28.93/chk_obsdata//k5ts3/T1731900??c.dat file size is correct (nominal:400MB, actual:400MB). 2006.173.19:02:29.33/chk_obsdata//k5ts4/T1731900??d.dat file size is correct (nominal:400MB, actual:400MB). 2006.173.19:02:30.06/k5log//k5ts1_log_newline 2006.173.19:02:30.77/k5log//k5ts2_log_newline 2006.173.19:02:31.49/k5log//k5ts3_log_newline 2006.173.19:02:32.19/k5log//k5ts4_log_newline 2006.173.19:02:32.21/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.19:02:32.21:setupk4=1 2006.173.19:02:32.22$setupk4/echo=on 2006.173.19:02:32.22$setupk4/pcalon 2006.173.19:02:32.22$pcalon/"no phase cal control is implemented here 2006.173.19:02:32.22$setupk4/"tpicd=stop 2006.173.19:02:32.22$setupk4/"rec=synch_on 2006.173.19:02:32.22$setupk4/"rec_mode=128 2006.173.19:02:32.22$setupk4/!* 2006.173.19:02:32.22$setupk4/recpk4 2006.173.19:02:32.22$recpk4/recpatch= 2006.173.19:02:32.22$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.19:02:32.22$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.19:02:32.22$setupk4/vck44 2006.173.19:02:32.22$vck44/valo=1,524.99 2006.173.19:02:32.22#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.19:02:32.22#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.19:02:32.22#ibcon#ireg 17 cls_cnt 0 2006.173.19:02:32.22#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.19:02:32.22#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.19:02:32.22#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.19:02:32.22#ibcon#enter wrdev, iclass 36, count 0 2006.173.19:02:32.22#ibcon#first serial, iclass 36, count 0 2006.173.19:02:32.22#ibcon#enter sib2, iclass 36, count 0 2006.173.19:02:32.22#ibcon#flushed, iclass 36, count 0 2006.173.19:02:32.22#ibcon#about to write, iclass 36, count 0 2006.173.19:02:32.22#ibcon#wrote, iclass 36, count 0 2006.173.19:02:32.22#ibcon#about to read 3, iclass 36, count 0 2006.173.19:02:32.24#ibcon#read 3, iclass 36, count 0 2006.173.19:02:32.24#ibcon#about to read 4, iclass 36, count 0 2006.173.19:02:32.24#ibcon#read 4, iclass 36, count 0 2006.173.19:02:32.24#ibcon#about to read 5, iclass 36, count 0 2006.173.19:02:32.24#ibcon#read 5, iclass 36, count 0 2006.173.19:02:32.24#ibcon#about to read 6, iclass 36, count 0 2006.173.19:02:32.24#ibcon#read 6, iclass 36, count 0 2006.173.19:02:32.24#ibcon#end of sib2, iclass 36, count 0 2006.173.19:02:32.24#ibcon#*mode == 0, iclass 36, count 0 2006.173.19:02:32.24#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.19:02:32.24#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.19:02:32.24#ibcon#*before write, iclass 36, count 0 2006.173.19:02:32.24#ibcon#enter sib2, iclass 36, count 0 2006.173.19:02:32.24#ibcon#flushed, iclass 36, count 0 2006.173.19:02:32.24#ibcon#about to write, iclass 36, count 0 2006.173.19:02:32.24#ibcon#wrote, iclass 36, count 0 2006.173.19:02:32.24#ibcon#about to read 3, iclass 36, count 0 2006.173.19:02:32.29#ibcon#read 3, iclass 36, count 0 2006.173.19:02:32.29#ibcon#about to read 4, iclass 36, count 0 2006.173.19:02:32.29#ibcon#read 4, iclass 36, count 0 2006.173.19:02:32.29#ibcon#about to read 5, iclass 36, count 0 2006.173.19:02:32.29#ibcon#read 5, iclass 36, count 0 2006.173.19:02:32.29#ibcon#about to read 6, iclass 36, count 0 2006.173.19:02:32.29#ibcon#read 6, iclass 36, count 0 2006.173.19:02:32.29#ibcon#end of sib2, iclass 36, count 0 2006.173.19:02:32.29#ibcon#*after write, iclass 36, count 0 2006.173.19:02:32.29#ibcon#*before return 0, iclass 36, count 0 2006.173.19:02:32.29#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.19:02:32.29#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.19:02:32.29#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.19:02:32.29#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.19:02:32.29$vck44/va=1,7 2006.173.19:02:32.29#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.19:02:32.29#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.19:02:32.29#ibcon#ireg 11 cls_cnt 2 2006.173.19:02:32.29#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.19:02:32.29#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.19:02:32.29#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.19:02:32.29#ibcon#enter wrdev, iclass 38, count 2 2006.173.19:02:32.29#ibcon#first serial, iclass 38, count 2 2006.173.19:02:32.29#ibcon#enter sib2, iclass 38, count 2 2006.173.19:02:32.29#ibcon#flushed, iclass 38, count 2 2006.173.19:02:32.29#ibcon#about to write, iclass 38, count 2 2006.173.19:02:32.29#ibcon#wrote, iclass 38, count 2 2006.173.19:02:32.29#ibcon#about to read 3, iclass 38, count 2 2006.173.19:02:32.31#ibcon#read 3, iclass 38, count 2 2006.173.19:02:32.31#ibcon#about to read 4, iclass 38, count 2 2006.173.19:02:32.31#ibcon#read 4, iclass 38, count 2 2006.173.19:02:32.31#ibcon#about to read 5, iclass 38, count 2 2006.173.19:02:32.31#ibcon#read 5, iclass 38, count 2 2006.173.19:02:32.31#ibcon#about to read 6, iclass 38, count 2 2006.173.19:02:32.31#ibcon#read 6, iclass 38, count 2 2006.173.19:02:32.31#ibcon#end of sib2, iclass 38, count 2 2006.173.19:02:32.31#ibcon#*mode == 0, iclass 38, count 2 2006.173.19:02:32.31#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.19:02:32.31#ibcon#[25=AT01-07\r\n] 2006.173.19:02:32.31#ibcon#*before write, iclass 38, count 2 2006.173.19:02:32.31#ibcon#enter sib2, iclass 38, count 2 2006.173.19:02:32.31#ibcon#flushed, iclass 38, count 2 2006.173.19:02:32.31#ibcon#about to write, iclass 38, count 2 2006.173.19:02:32.31#ibcon#wrote, iclass 38, count 2 2006.173.19:02:32.31#ibcon#about to read 3, iclass 38, count 2 2006.173.19:02:32.34#ibcon#read 3, iclass 38, count 2 2006.173.19:02:32.34#ibcon#about to read 4, iclass 38, count 2 2006.173.19:02:32.34#ibcon#read 4, iclass 38, count 2 2006.173.19:02:32.34#ibcon#about to read 5, iclass 38, count 2 2006.173.19:02:32.34#ibcon#read 5, iclass 38, count 2 2006.173.19:02:32.34#ibcon#about to read 6, iclass 38, count 2 2006.173.19:02:32.34#ibcon#read 6, iclass 38, count 2 2006.173.19:02:32.34#ibcon#end of sib2, iclass 38, count 2 2006.173.19:02:32.34#ibcon#*after write, iclass 38, count 2 2006.173.19:02:32.34#ibcon#*before return 0, iclass 38, count 2 2006.173.19:02:32.34#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.19:02:32.34#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.19:02:32.34#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.19:02:32.34#ibcon#ireg 7 cls_cnt 0 2006.173.19:02:32.34#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.19:02:32.46#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.19:02:32.46#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.19:02:32.46#ibcon#enter wrdev, iclass 38, count 0 2006.173.19:02:32.46#ibcon#first serial, iclass 38, count 0 2006.173.19:02:32.46#ibcon#enter sib2, iclass 38, count 0 2006.173.19:02:32.46#ibcon#flushed, iclass 38, count 0 2006.173.19:02:32.46#ibcon#about to write, iclass 38, count 0 2006.173.19:02:32.46#ibcon#wrote, iclass 38, count 0 2006.173.19:02:32.46#ibcon#about to read 3, iclass 38, count 0 2006.173.19:02:32.48#ibcon#read 3, iclass 38, count 0 2006.173.19:02:32.48#ibcon#about to read 4, iclass 38, count 0 2006.173.19:02:32.48#ibcon#read 4, iclass 38, count 0 2006.173.19:02:32.48#ibcon#about to read 5, iclass 38, count 0 2006.173.19:02:32.48#ibcon#read 5, iclass 38, count 0 2006.173.19:02:32.48#ibcon#about to read 6, iclass 38, count 0 2006.173.19:02:32.48#ibcon#read 6, iclass 38, count 0 2006.173.19:02:32.48#ibcon#end of sib2, iclass 38, count 0 2006.173.19:02:32.48#ibcon#*mode == 0, iclass 38, count 0 2006.173.19:02:32.48#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.19:02:32.48#ibcon#[25=USB\r\n] 2006.173.19:02:32.48#ibcon#*before write, iclass 38, count 0 2006.173.19:02:32.48#ibcon#enter sib2, iclass 38, count 0 2006.173.19:02:32.48#ibcon#flushed, iclass 38, count 0 2006.173.19:02:32.48#ibcon#about to write, iclass 38, count 0 2006.173.19:02:32.48#ibcon#wrote, iclass 38, count 0 2006.173.19:02:32.48#ibcon#about to read 3, iclass 38, count 0 2006.173.19:02:32.51#ibcon#read 3, iclass 38, count 0 2006.173.19:02:32.51#ibcon#about to read 4, iclass 38, count 0 2006.173.19:02:32.51#ibcon#read 4, iclass 38, count 0 2006.173.19:02:32.51#ibcon#about to read 5, iclass 38, count 0 2006.173.19:02:32.51#ibcon#read 5, iclass 38, count 0 2006.173.19:02:32.51#ibcon#about to read 6, iclass 38, count 0 2006.173.19:02:32.51#ibcon#read 6, iclass 38, count 0 2006.173.19:02:32.51#ibcon#end of sib2, iclass 38, count 0 2006.173.19:02:32.51#ibcon#*after write, iclass 38, count 0 2006.173.19:02:32.51#ibcon#*before return 0, iclass 38, count 0 2006.173.19:02:32.51#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.19:02:32.51#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.19:02:32.51#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.19:02:32.51#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.19:02:32.51$vck44/valo=2,534.99 2006.173.19:02:32.51#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.19:02:32.51#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.19:02:32.51#ibcon#ireg 17 cls_cnt 0 2006.173.19:02:32.51#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.19:02:32.51#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.19:02:32.51#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.19:02:32.51#ibcon#enter wrdev, iclass 40, count 0 2006.173.19:02:32.51#ibcon#first serial, iclass 40, count 0 2006.173.19:02:32.51#ibcon#enter sib2, iclass 40, count 0 2006.173.19:02:32.51#ibcon#flushed, iclass 40, count 0 2006.173.19:02:32.51#ibcon#about to write, iclass 40, count 0 2006.173.19:02:32.51#ibcon#wrote, iclass 40, count 0 2006.173.19:02:32.51#ibcon#about to read 3, iclass 40, count 0 2006.173.19:02:32.53#ibcon#read 3, iclass 40, count 0 2006.173.19:02:32.53#ibcon#about to read 4, iclass 40, count 0 2006.173.19:02:32.53#ibcon#read 4, iclass 40, count 0 2006.173.19:02:32.53#ibcon#about to read 5, iclass 40, count 0 2006.173.19:02:32.53#ibcon#read 5, iclass 40, count 0 2006.173.19:02:32.53#ibcon#about to read 6, iclass 40, count 0 2006.173.19:02:32.53#ibcon#read 6, iclass 40, count 0 2006.173.19:02:32.53#ibcon#end of sib2, iclass 40, count 0 2006.173.19:02:32.53#ibcon#*mode == 0, iclass 40, count 0 2006.173.19:02:32.53#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.19:02:32.53#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.19:02:32.53#ibcon#*before write, iclass 40, count 0 2006.173.19:02:32.53#ibcon#enter sib2, iclass 40, count 0 2006.173.19:02:32.53#ibcon#flushed, iclass 40, count 0 2006.173.19:02:32.53#ibcon#about to write, iclass 40, count 0 2006.173.19:02:32.53#ibcon#wrote, iclass 40, count 0 2006.173.19:02:32.53#ibcon#about to read 3, iclass 40, count 0 2006.173.19:02:32.57#ibcon#read 3, iclass 40, count 0 2006.173.19:02:32.57#ibcon#about to read 4, iclass 40, count 0 2006.173.19:02:32.57#ibcon#read 4, iclass 40, count 0 2006.173.19:02:32.57#ibcon#about to read 5, iclass 40, count 0 2006.173.19:02:32.57#ibcon#read 5, iclass 40, count 0 2006.173.19:02:32.57#ibcon#about to read 6, iclass 40, count 0 2006.173.19:02:32.57#ibcon#read 6, iclass 40, count 0 2006.173.19:02:32.57#ibcon#end of sib2, iclass 40, count 0 2006.173.19:02:32.57#ibcon#*after write, iclass 40, count 0 2006.173.19:02:32.57#ibcon#*before return 0, iclass 40, count 0 2006.173.19:02:32.57#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.19:02:32.57#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.19:02:32.57#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.19:02:32.57#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.19:02:32.57$vck44/va=2,6 2006.173.19:02:32.57#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.19:02:32.57#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.19:02:32.57#ibcon#ireg 11 cls_cnt 2 2006.173.19:02:32.57#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.19:02:32.63#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.19:02:32.63#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.19:02:32.63#ibcon#enter wrdev, iclass 4, count 2 2006.173.19:02:32.63#ibcon#first serial, iclass 4, count 2 2006.173.19:02:32.63#ibcon#enter sib2, iclass 4, count 2 2006.173.19:02:32.63#ibcon#flushed, iclass 4, count 2 2006.173.19:02:32.63#ibcon#about to write, iclass 4, count 2 2006.173.19:02:32.63#ibcon#wrote, iclass 4, count 2 2006.173.19:02:32.63#ibcon#about to read 3, iclass 4, count 2 2006.173.19:02:32.65#ibcon#read 3, iclass 4, count 2 2006.173.19:02:32.65#ibcon#about to read 4, iclass 4, count 2 2006.173.19:02:32.65#ibcon#read 4, iclass 4, count 2 2006.173.19:02:32.65#ibcon#about to read 5, iclass 4, count 2 2006.173.19:02:32.65#ibcon#read 5, iclass 4, count 2 2006.173.19:02:32.65#ibcon#about to read 6, iclass 4, count 2 2006.173.19:02:32.65#ibcon#read 6, iclass 4, count 2 2006.173.19:02:32.65#ibcon#end of sib2, iclass 4, count 2 2006.173.19:02:32.65#ibcon#*mode == 0, iclass 4, count 2 2006.173.19:02:32.65#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.19:02:32.65#ibcon#[25=AT02-06\r\n] 2006.173.19:02:32.65#ibcon#*before write, iclass 4, count 2 2006.173.19:02:32.65#ibcon#enter sib2, iclass 4, count 2 2006.173.19:02:32.65#ibcon#flushed, iclass 4, count 2 2006.173.19:02:32.65#ibcon#about to write, iclass 4, count 2 2006.173.19:02:32.65#ibcon#wrote, iclass 4, count 2 2006.173.19:02:32.65#ibcon#about to read 3, iclass 4, count 2 2006.173.19:02:32.68#ibcon#read 3, iclass 4, count 2 2006.173.19:02:32.68#ibcon#about to read 4, iclass 4, count 2 2006.173.19:02:32.68#ibcon#read 4, iclass 4, count 2 2006.173.19:02:32.68#ibcon#about to read 5, iclass 4, count 2 2006.173.19:02:32.68#ibcon#read 5, iclass 4, count 2 2006.173.19:02:32.68#ibcon#about to read 6, iclass 4, count 2 2006.173.19:02:32.68#ibcon#read 6, iclass 4, count 2 2006.173.19:02:32.68#ibcon#end of sib2, iclass 4, count 2 2006.173.19:02:32.68#ibcon#*after write, iclass 4, count 2 2006.173.19:02:32.68#ibcon#*before return 0, iclass 4, count 2 2006.173.19:02:32.68#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.19:02:32.68#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.19:02:32.68#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.19:02:32.68#ibcon#ireg 7 cls_cnt 0 2006.173.19:02:32.68#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.19:02:32.80#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.19:02:32.80#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.19:02:32.80#ibcon#enter wrdev, iclass 4, count 0 2006.173.19:02:32.80#ibcon#first serial, iclass 4, count 0 2006.173.19:02:32.80#ibcon#enter sib2, iclass 4, count 0 2006.173.19:02:32.80#ibcon#flushed, iclass 4, count 0 2006.173.19:02:32.80#ibcon#about to write, iclass 4, count 0 2006.173.19:02:32.80#ibcon#wrote, iclass 4, count 0 2006.173.19:02:32.80#ibcon#about to read 3, iclass 4, count 0 2006.173.19:02:32.82#ibcon#read 3, iclass 4, count 0 2006.173.19:02:32.82#ibcon#about to read 4, iclass 4, count 0 2006.173.19:02:32.82#ibcon#read 4, iclass 4, count 0 2006.173.19:02:32.82#ibcon#about to read 5, iclass 4, count 0 2006.173.19:02:32.82#ibcon#read 5, iclass 4, count 0 2006.173.19:02:32.82#ibcon#about to read 6, iclass 4, count 0 2006.173.19:02:32.82#ibcon#read 6, iclass 4, count 0 2006.173.19:02:32.82#ibcon#end of sib2, iclass 4, count 0 2006.173.19:02:32.82#ibcon#*mode == 0, iclass 4, count 0 2006.173.19:02:32.82#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.19:02:32.82#ibcon#[25=USB\r\n] 2006.173.19:02:32.82#ibcon#*before write, iclass 4, count 0 2006.173.19:02:32.82#ibcon#enter sib2, iclass 4, count 0 2006.173.19:02:32.82#ibcon#flushed, iclass 4, count 0 2006.173.19:02:32.82#ibcon#about to write, iclass 4, count 0 2006.173.19:02:32.82#ibcon#wrote, iclass 4, count 0 2006.173.19:02:32.82#ibcon#about to read 3, iclass 4, count 0 2006.173.19:02:32.85#ibcon#read 3, iclass 4, count 0 2006.173.19:02:32.85#ibcon#about to read 4, iclass 4, count 0 2006.173.19:02:32.85#ibcon#read 4, iclass 4, count 0 2006.173.19:02:32.85#ibcon#about to read 5, iclass 4, count 0 2006.173.19:02:32.85#ibcon#read 5, iclass 4, count 0 2006.173.19:02:32.85#ibcon#about to read 6, iclass 4, count 0 2006.173.19:02:32.85#ibcon#read 6, iclass 4, count 0 2006.173.19:02:32.85#ibcon#end of sib2, iclass 4, count 0 2006.173.19:02:32.85#ibcon#*after write, iclass 4, count 0 2006.173.19:02:32.85#ibcon#*before return 0, iclass 4, count 0 2006.173.19:02:32.85#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.19:02:32.85#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.19:02:32.85#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.19:02:32.85#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.19:02:32.85$vck44/valo=3,564.99 2006.173.19:02:32.85#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.19:02:32.85#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.19:02:32.85#ibcon#ireg 17 cls_cnt 0 2006.173.19:02:32.85#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.19:02:32.85#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.19:02:32.85#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.19:02:32.85#ibcon#enter wrdev, iclass 6, count 0 2006.173.19:02:32.85#ibcon#first serial, iclass 6, count 0 2006.173.19:02:32.85#ibcon#enter sib2, iclass 6, count 0 2006.173.19:02:32.85#ibcon#flushed, iclass 6, count 0 2006.173.19:02:32.85#ibcon#about to write, iclass 6, count 0 2006.173.19:02:32.85#ibcon#wrote, iclass 6, count 0 2006.173.19:02:32.85#ibcon#about to read 3, iclass 6, count 0 2006.173.19:02:32.87#ibcon#read 3, iclass 6, count 0 2006.173.19:02:32.87#ibcon#about to read 4, iclass 6, count 0 2006.173.19:02:32.87#ibcon#read 4, iclass 6, count 0 2006.173.19:02:32.87#ibcon#about to read 5, iclass 6, count 0 2006.173.19:02:32.87#ibcon#read 5, iclass 6, count 0 2006.173.19:02:32.87#ibcon#about to read 6, iclass 6, count 0 2006.173.19:02:32.87#ibcon#read 6, iclass 6, count 0 2006.173.19:02:32.87#ibcon#end of sib2, iclass 6, count 0 2006.173.19:02:32.87#ibcon#*mode == 0, iclass 6, count 0 2006.173.19:02:32.87#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.19:02:32.87#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.19:02:32.87#ibcon#*before write, iclass 6, count 0 2006.173.19:02:32.87#ibcon#enter sib2, iclass 6, count 0 2006.173.19:02:32.87#ibcon#flushed, iclass 6, count 0 2006.173.19:02:32.87#ibcon#about to write, iclass 6, count 0 2006.173.19:02:32.87#ibcon#wrote, iclass 6, count 0 2006.173.19:02:32.87#ibcon#about to read 3, iclass 6, count 0 2006.173.19:02:32.91#ibcon#read 3, iclass 6, count 0 2006.173.19:02:32.91#ibcon#about to read 4, iclass 6, count 0 2006.173.19:02:32.91#ibcon#read 4, iclass 6, count 0 2006.173.19:02:32.91#ibcon#about to read 5, iclass 6, count 0 2006.173.19:02:32.91#ibcon#read 5, iclass 6, count 0 2006.173.19:02:32.91#ibcon#about to read 6, iclass 6, count 0 2006.173.19:02:32.91#ibcon#read 6, iclass 6, count 0 2006.173.19:02:32.91#ibcon#end of sib2, iclass 6, count 0 2006.173.19:02:32.91#ibcon#*after write, iclass 6, count 0 2006.173.19:02:32.91#ibcon#*before return 0, iclass 6, count 0 2006.173.19:02:32.91#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.19:02:32.91#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.19:02:32.91#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.19:02:32.91#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.19:02:32.91$vck44/va=3,5 2006.173.19:02:32.91#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.19:02:32.91#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.19:02:32.91#ibcon#ireg 11 cls_cnt 2 2006.173.19:02:32.91#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.19:02:32.97#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.19:02:32.97#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.19:02:32.97#ibcon#enter wrdev, iclass 10, count 2 2006.173.19:02:32.97#ibcon#first serial, iclass 10, count 2 2006.173.19:02:32.97#ibcon#enter sib2, iclass 10, count 2 2006.173.19:02:32.97#ibcon#flushed, iclass 10, count 2 2006.173.19:02:32.97#ibcon#about to write, iclass 10, count 2 2006.173.19:02:32.97#ibcon#wrote, iclass 10, count 2 2006.173.19:02:32.97#ibcon#about to read 3, iclass 10, count 2 2006.173.19:02:32.99#ibcon#read 3, iclass 10, count 2 2006.173.19:02:32.99#ibcon#about to read 4, iclass 10, count 2 2006.173.19:02:32.99#ibcon#read 4, iclass 10, count 2 2006.173.19:02:32.99#ibcon#about to read 5, iclass 10, count 2 2006.173.19:02:32.99#ibcon#read 5, iclass 10, count 2 2006.173.19:02:32.99#ibcon#about to read 6, iclass 10, count 2 2006.173.19:02:32.99#ibcon#read 6, iclass 10, count 2 2006.173.19:02:32.99#ibcon#end of sib2, iclass 10, count 2 2006.173.19:02:32.99#ibcon#*mode == 0, iclass 10, count 2 2006.173.19:02:32.99#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.19:02:32.99#ibcon#[25=AT03-05\r\n] 2006.173.19:02:32.99#ibcon#*before write, iclass 10, count 2 2006.173.19:02:32.99#ibcon#enter sib2, iclass 10, count 2 2006.173.19:02:32.99#ibcon#flushed, iclass 10, count 2 2006.173.19:02:32.99#ibcon#about to write, iclass 10, count 2 2006.173.19:02:32.99#ibcon#wrote, iclass 10, count 2 2006.173.19:02:32.99#ibcon#about to read 3, iclass 10, count 2 2006.173.19:02:33.02#ibcon#read 3, iclass 10, count 2 2006.173.19:02:33.02#ibcon#about to read 4, iclass 10, count 2 2006.173.19:02:33.02#ibcon#read 4, iclass 10, count 2 2006.173.19:02:33.02#ibcon#about to read 5, iclass 10, count 2 2006.173.19:02:33.02#ibcon#read 5, iclass 10, count 2 2006.173.19:02:33.02#ibcon#about to read 6, iclass 10, count 2 2006.173.19:02:33.02#ibcon#read 6, iclass 10, count 2 2006.173.19:02:33.02#ibcon#end of sib2, iclass 10, count 2 2006.173.19:02:33.02#ibcon#*after write, iclass 10, count 2 2006.173.19:02:33.02#ibcon#*before return 0, iclass 10, count 2 2006.173.19:02:33.02#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.19:02:33.02#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.19:02:33.02#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.19:02:33.02#ibcon#ireg 7 cls_cnt 0 2006.173.19:02:33.02#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.19:02:33.14#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.19:02:33.14#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.19:02:33.14#ibcon#enter wrdev, iclass 10, count 0 2006.173.19:02:33.14#ibcon#first serial, iclass 10, count 0 2006.173.19:02:33.14#ibcon#enter sib2, iclass 10, count 0 2006.173.19:02:33.14#ibcon#flushed, iclass 10, count 0 2006.173.19:02:33.14#ibcon#about to write, iclass 10, count 0 2006.173.19:02:33.14#ibcon#wrote, iclass 10, count 0 2006.173.19:02:33.14#ibcon#about to read 3, iclass 10, count 0 2006.173.19:02:33.16#ibcon#read 3, iclass 10, count 0 2006.173.19:02:33.16#ibcon#about to read 4, iclass 10, count 0 2006.173.19:02:33.16#ibcon#read 4, iclass 10, count 0 2006.173.19:02:33.16#ibcon#about to read 5, iclass 10, count 0 2006.173.19:02:33.16#ibcon#read 5, iclass 10, count 0 2006.173.19:02:33.16#ibcon#about to read 6, iclass 10, count 0 2006.173.19:02:33.16#ibcon#read 6, iclass 10, count 0 2006.173.19:02:33.16#ibcon#end of sib2, iclass 10, count 0 2006.173.19:02:33.16#ibcon#*mode == 0, iclass 10, count 0 2006.173.19:02:33.16#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.19:02:33.16#ibcon#[25=USB\r\n] 2006.173.19:02:33.16#ibcon#*before write, iclass 10, count 0 2006.173.19:02:33.16#ibcon#enter sib2, iclass 10, count 0 2006.173.19:02:33.16#ibcon#flushed, iclass 10, count 0 2006.173.19:02:33.16#ibcon#about to write, iclass 10, count 0 2006.173.19:02:33.16#ibcon#wrote, iclass 10, count 0 2006.173.19:02:33.16#ibcon#about to read 3, iclass 10, count 0 2006.173.19:02:33.19#ibcon#read 3, iclass 10, count 0 2006.173.19:02:33.19#ibcon#about to read 4, iclass 10, count 0 2006.173.19:02:33.19#ibcon#read 4, iclass 10, count 0 2006.173.19:02:33.19#ibcon#about to read 5, iclass 10, count 0 2006.173.19:02:33.19#ibcon#read 5, iclass 10, count 0 2006.173.19:02:33.19#ibcon#about to read 6, iclass 10, count 0 2006.173.19:02:33.19#ibcon#read 6, iclass 10, count 0 2006.173.19:02:33.19#ibcon#end of sib2, iclass 10, count 0 2006.173.19:02:33.19#ibcon#*after write, iclass 10, count 0 2006.173.19:02:33.19#ibcon#*before return 0, iclass 10, count 0 2006.173.19:02:33.19#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.19:02:33.19#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.19:02:33.19#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.19:02:33.19#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.19:02:33.19$vck44/valo=4,624.99 2006.173.19:02:33.19#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.19:02:33.19#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.19:02:33.19#ibcon#ireg 17 cls_cnt 0 2006.173.19:02:33.19#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.19:02:33.19#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.19:02:33.19#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.19:02:33.19#ibcon#enter wrdev, iclass 12, count 0 2006.173.19:02:33.19#ibcon#first serial, iclass 12, count 0 2006.173.19:02:33.19#ibcon#enter sib2, iclass 12, count 0 2006.173.19:02:33.19#ibcon#flushed, iclass 12, count 0 2006.173.19:02:33.19#ibcon#about to write, iclass 12, count 0 2006.173.19:02:33.19#ibcon#wrote, iclass 12, count 0 2006.173.19:02:33.19#ibcon#about to read 3, iclass 12, count 0 2006.173.19:02:33.21#ibcon#read 3, iclass 12, count 0 2006.173.19:02:33.21#ibcon#about to read 4, iclass 12, count 0 2006.173.19:02:33.21#ibcon#read 4, iclass 12, count 0 2006.173.19:02:33.21#ibcon#about to read 5, iclass 12, count 0 2006.173.19:02:33.21#ibcon#read 5, iclass 12, count 0 2006.173.19:02:33.21#ibcon#about to read 6, iclass 12, count 0 2006.173.19:02:33.21#ibcon#read 6, iclass 12, count 0 2006.173.19:02:33.21#ibcon#end of sib2, iclass 12, count 0 2006.173.19:02:33.21#ibcon#*mode == 0, iclass 12, count 0 2006.173.19:02:33.21#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.19:02:33.21#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.19:02:33.21#ibcon#*before write, iclass 12, count 0 2006.173.19:02:33.21#ibcon#enter sib2, iclass 12, count 0 2006.173.19:02:33.21#ibcon#flushed, iclass 12, count 0 2006.173.19:02:33.21#ibcon#about to write, iclass 12, count 0 2006.173.19:02:33.21#ibcon#wrote, iclass 12, count 0 2006.173.19:02:33.21#ibcon#about to read 3, iclass 12, count 0 2006.173.19:02:33.25#ibcon#read 3, iclass 12, count 0 2006.173.19:02:33.25#ibcon#about to read 4, iclass 12, count 0 2006.173.19:02:33.25#ibcon#read 4, iclass 12, count 0 2006.173.19:02:33.25#ibcon#about to read 5, iclass 12, count 0 2006.173.19:02:33.25#ibcon#read 5, iclass 12, count 0 2006.173.19:02:33.25#ibcon#about to read 6, iclass 12, count 0 2006.173.19:02:33.25#ibcon#read 6, iclass 12, count 0 2006.173.19:02:33.25#ibcon#end of sib2, iclass 12, count 0 2006.173.19:02:33.25#ibcon#*after write, iclass 12, count 0 2006.173.19:02:33.25#ibcon#*before return 0, iclass 12, count 0 2006.173.19:02:33.25#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.19:02:33.25#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.19:02:33.25#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.19:02:33.25#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.19:02:33.25$vck44/va=4,6 2006.173.19:02:33.25#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.19:02:33.25#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.19:02:33.25#ibcon#ireg 11 cls_cnt 2 2006.173.19:02:33.25#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.19:02:33.31#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.19:02:33.31#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.19:02:33.31#ibcon#enter wrdev, iclass 14, count 2 2006.173.19:02:33.31#ibcon#first serial, iclass 14, count 2 2006.173.19:02:33.31#ibcon#enter sib2, iclass 14, count 2 2006.173.19:02:33.31#ibcon#flushed, iclass 14, count 2 2006.173.19:02:33.31#ibcon#about to write, iclass 14, count 2 2006.173.19:02:33.31#ibcon#wrote, iclass 14, count 2 2006.173.19:02:33.31#ibcon#about to read 3, iclass 14, count 2 2006.173.19:02:33.33#ibcon#read 3, iclass 14, count 2 2006.173.19:02:33.33#ibcon#about to read 4, iclass 14, count 2 2006.173.19:02:33.33#ibcon#read 4, iclass 14, count 2 2006.173.19:02:33.33#ibcon#about to read 5, iclass 14, count 2 2006.173.19:02:33.33#ibcon#read 5, iclass 14, count 2 2006.173.19:02:33.33#ibcon#about to read 6, iclass 14, count 2 2006.173.19:02:33.33#ibcon#read 6, iclass 14, count 2 2006.173.19:02:33.33#ibcon#end of sib2, iclass 14, count 2 2006.173.19:02:33.33#ibcon#*mode == 0, iclass 14, count 2 2006.173.19:02:33.33#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.19:02:33.33#ibcon#[25=AT04-06\r\n] 2006.173.19:02:33.33#ibcon#*before write, iclass 14, count 2 2006.173.19:02:33.33#ibcon#enter sib2, iclass 14, count 2 2006.173.19:02:33.33#ibcon#flushed, iclass 14, count 2 2006.173.19:02:33.33#ibcon#about to write, iclass 14, count 2 2006.173.19:02:33.33#ibcon#wrote, iclass 14, count 2 2006.173.19:02:33.33#ibcon#about to read 3, iclass 14, count 2 2006.173.19:02:33.36#ibcon#read 3, iclass 14, count 2 2006.173.19:02:33.36#ibcon#about to read 4, iclass 14, count 2 2006.173.19:02:33.36#ibcon#read 4, iclass 14, count 2 2006.173.19:02:33.36#ibcon#about to read 5, iclass 14, count 2 2006.173.19:02:33.36#ibcon#read 5, iclass 14, count 2 2006.173.19:02:33.36#ibcon#about to read 6, iclass 14, count 2 2006.173.19:02:33.36#ibcon#read 6, iclass 14, count 2 2006.173.19:02:33.36#ibcon#end of sib2, iclass 14, count 2 2006.173.19:02:33.36#ibcon#*after write, iclass 14, count 2 2006.173.19:02:33.36#ibcon#*before return 0, iclass 14, count 2 2006.173.19:02:33.36#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.19:02:33.36#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.19:02:33.36#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.19:02:33.36#ibcon#ireg 7 cls_cnt 0 2006.173.19:02:33.36#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.19:02:33.48#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.19:02:33.48#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.19:02:33.48#ibcon#enter wrdev, iclass 14, count 0 2006.173.19:02:33.48#ibcon#first serial, iclass 14, count 0 2006.173.19:02:33.48#ibcon#enter sib2, iclass 14, count 0 2006.173.19:02:33.48#ibcon#flushed, iclass 14, count 0 2006.173.19:02:33.48#ibcon#about to write, iclass 14, count 0 2006.173.19:02:33.48#ibcon#wrote, iclass 14, count 0 2006.173.19:02:33.48#ibcon#about to read 3, iclass 14, count 0 2006.173.19:02:33.50#ibcon#read 3, iclass 14, count 0 2006.173.19:02:33.50#ibcon#about to read 4, iclass 14, count 0 2006.173.19:02:33.50#ibcon#read 4, iclass 14, count 0 2006.173.19:02:33.50#ibcon#about to read 5, iclass 14, count 0 2006.173.19:02:33.50#ibcon#read 5, iclass 14, count 0 2006.173.19:02:33.50#ibcon#about to read 6, iclass 14, count 0 2006.173.19:02:33.50#ibcon#read 6, iclass 14, count 0 2006.173.19:02:33.50#ibcon#end of sib2, iclass 14, count 0 2006.173.19:02:33.50#ibcon#*mode == 0, iclass 14, count 0 2006.173.19:02:33.50#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.19:02:33.50#ibcon#[25=USB\r\n] 2006.173.19:02:33.50#ibcon#*before write, iclass 14, count 0 2006.173.19:02:33.50#ibcon#enter sib2, iclass 14, count 0 2006.173.19:02:33.50#ibcon#flushed, iclass 14, count 0 2006.173.19:02:33.50#ibcon#about to write, iclass 14, count 0 2006.173.19:02:33.50#ibcon#wrote, iclass 14, count 0 2006.173.19:02:33.50#ibcon#about to read 3, iclass 14, count 0 2006.173.19:02:33.53#ibcon#read 3, iclass 14, count 0 2006.173.19:02:33.53#ibcon#about to read 4, iclass 14, count 0 2006.173.19:02:33.53#ibcon#read 4, iclass 14, count 0 2006.173.19:02:33.53#ibcon#about to read 5, iclass 14, count 0 2006.173.19:02:33.53#ibcon#read 5, iclass 14, count 0 2006.173.19:02:33.53#ibcon#about to read 6, iclass 14, count 0 2006.173.19:02:33.53#ibcon#read 6, iclass 14, count 0 2006.173.19:02:33.53#ibcon#end of sib2, iclass 14, count 0 2006.173.19:02:33.53#ibcon#*after write, iclass 14, count 0 2006.173.19:02:33.53#ibcon#*before return 0, iclass 14, count 0 2006.173.19:02:33.53#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.19:02:33.53#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.19:02:33.53#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.19:02:33.53#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.19:02:33.53$vck44/valo=5,734.99 2006.173.19:02:33.53#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.19:02:33.53#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.19:02:33.53#ibcon#ireg 17 cls_cnt 0 2006.173.19:02:33.53#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.19:02:33.53#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.19:02:33.53#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.19:02:33.53#ibcon#enter wrdev, iclass 16, count 0 2006.173.19:02:33.53#ibcon#first serial, iclass 16, count 0 2006.173.19:02:33.53#ibcon#enter sib2, iclass 16, count 0 2006.173.19:02:33.53#ibcon#flushed, iclass 16, count 0 2006.173.19:02:33.53#ibcon#about to write, iclass 16, count 0 2006.173.19:02:33.53#ibcon#wrote, iclass 16, count 0 2006.173.19:02:33.53#ibcon#about to read 3, iclass 16, count 0 2006.173.19:02:33.55#ibcon#read 3, iclass 16, count 0 2006.173.19:02:33.55#ibcon#about to read 4, iclass 16, count 0 2006.173.19:02:33.55#ibcon#read 4, iclass 16, count 0 2006.173.19:02:33.55#ibcon#about to read 5, iclass 16, count 0 2006.173.19:02:33.55#ibcon#read 5, iclass 16, count 0 2006.173.19:02:33.55#ibcon#about to read 6, iclass 16, count 0 2006.173.19:02:33.55#ibcon#read 6, iclass 16, count 0 2006.173.19:02:33.55#ibcon#end of sib2, iclass 16, count 0 2006.173.19:02:33.55#ibcon#*mode == 0, iclass 16, count 0 2006.173.19:02:33.55#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.19:02:33.55#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.19:02:33.55#ibcon#*before write, iclass 16, count 0 2006.173.19:02:33.55#ibcon#enter sib2, iclass 16, count 0 2006.173.19:02:33.55#ibcon#flushed, iclass 16, count 0 2006.173.19:02:33.55#ibcon#about to write, iclass 16, count 0 2006.173.19:02:33.55#ibcon#wrote, iclass 16, count 0 2006.173.19:02:33.55#ibcon#about to read 3, iclass 16, count 0 2006.173.19:02:33.59#ibcon#read 3, iclass 16, count 0 2006.173.19:02:33.59#ibcon#about to read 4, iclass 16, count 0 2006.173.19:02:33.59#ibcon#read 4, iclass 16, count 0 2006.173.19:02:33.59#ibcon#about to read 5, iclass 16, count 0 2006.173.19:02:33.59#ibcon#read 5, iclass 16, count 0 2006.173.19:02:33.59#ibcon#about to read 6, iclass 16, count 0 2006.173.19:02:33.59#ibcon#read 6, iclass 16, count 0 2006.173.19:02:33.59#ibcon#end of sib2, iclass 16, count 0 2006.173.19:02:33.59#ibcon#*after write, iclass 16, count 0 2006.173.19:02:33.59#ibcon#*before return 0, iclass 16, count 0 2006.173.19:02:33.59#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.19:02:33.59#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.19:02:33.59#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.19:02:33.59#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.19:02:33.59$vck44/va=5,4 2006.173.19:02:33.59#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.19:02:33.59#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.19:02:33.59#ibcon#ireg 11 cls_cnt 2 2006.173.19:02:33.59#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.19:02:33.65#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.19:02:33.65#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.19:02:33.65#ibcon#enter wrdev, iclass 18, count 2 2006.173.19:02:33.65#ibcon#first serial, iclass 18, count 2 2006.173.19:02:33.65#ibcon#enter sib2, iclass 18, count 2 2006.173.19:02:33.65#ibcon#flushed, iclass 18, count 2 2006.173.19:02:33.65#ibcon#about to write, iclass 18, count 2 2006.173.19:02:33.65#ibcon#wrote, iclass 18, count 2 2006.173.19:02:33.65#ibcon#about to read 3, iclass 18, count 2 2006.173.19:02:33.67#ibcon#read 3, iclass 18, count 2 2006.173.19:02:33.67#ibcon#about to read 4, iclass 18, count 2 2006.173.19:02:33.67#ibcon#read 4, iclass 18, count 2 2006.173.19:02:33.67#ibcon#about to read 5, iclass 18, count 2 2006.173.19:02:33.67#ibcon#read 5, iclass 18, count 2 2006.173.19:02:33.67#ibcon#about to read 6, iclass 18, count 2 2006.173.19:02:33.67#ibcon#read 6, iclass 18, count 2 2006.173.19:02:33.67#ibcon#end of sib2, iclass 18, count 2 2006.173.19:02:33.67#ibcon#*mode == 0, iclass 18, count 2 2006.173.19:02:33.67#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.19:02:33.67#ibcon#[25=AT05-04\r\n] 2006.173.19:02:33.67#ibcon#*before write, iclass 18, count 2 2006.173.19:02:33.67#ibcon#enter sib2, iclass 18, count 2 2006.173.19:02:33.67#ibcon#flushed, iclass 18, count 2 2006.173.19:02:33.67#ibcon#about to write, iclass 18, count 2 2006.173.19:02:33.67#ibcon#wrote, iclass 18, count 2 2006.173.19:02:33.67#ibcon#about to read 3, iclass 18, count 2 2006.173.19:02:33.70#ibcon#read 3, iclass 18, count 2 2006.173.19:02:33.70#ibcon#about to read 4, iclass 18, count 2 2006.173.19:02:33.70#ibcon#read 4, iclass 18, count 2 2006.173.19:02:33.70#ibcon#about to read 5, iclass 18, count 2 2006.173.19:02:33.70#ibcon#read 5, iclass 18, count 2 2006.173.19:02:33.70#ibcon#about to read 6, iclass 18, count 2 2006.173.19:02:33.70#ibcon#read 6, iclass 18, count 2 2006.173.19:02:33.70#ibcon#end of sib2, iclass 18, count 2 2006.173.19:02:33.70#ibcon#*after write, iclass 18, count 2 2006.173.19:02:33.70#ibcon#*before return 0, iclass 18, count 2 2006.173.19:02:33.70#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.19:02:33.70#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.19:02:33.70#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.19:02:33.70#ibcon#ireg 7 cls_cnt 0 2006.173.19:02:33.70#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.19:02:33.82#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.19:02:33.82#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.19:02:33.82#ibcon#enter wrdev, iclass 18, count 0 2006.173.19:02:33.82#ibcon#first serial, iclass 18, count 0 2006.173.19:02:33.82#ibcon#enter sib2, iclass 18, count 0 2006.173.19:02:33.82#ibcon#flushed, iclass 18, count 0 2006.173.19:02:33.82#ibcon#about to write, iclass 18, count 0 2006.173.19:02:33.82#ibcon#wrote, iclass 18, count 0 2006.173.19:02:33.82#ibcon#about to read 3, iclass 18, count 0 2006.173.19:02:33.84#ibcon#read 3, iclass 18, count 0 2006.173.19:02:33.84#ibcon#about to read 4, iclass 18, count 0 2006.173.19:02:33.84#ibcon#read 4, iclass 18, count 0 2006.173.19:02:33.84#ibcon#about to read 5, iclass 18, count 0 2006.173.19:02:33.84#ibcon#read 5, iclass 18, count 0 2006.173.19:02:33.84#ibcon#about to read 6, iclass 18, count 0 2006.173.19:02:33.84#ibcon#read 6, iclass 18, count 0 2006.173.19:02:33.84#ibcon#end of sib2, iclass 18, count 0 2006.173.19:02:33.84#ibcon#*mode == 0, iclass 18, count 0 2006.173.19:02:33.84#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.19:02:33.84#ibcon#[25=USB\r\n] 2006.173.19:02:33.84#ibcon#*before write, iclass 18, count 0 2006.173.19:02:33.84#ibcon#enter sib2, iclass 18, count 0 2006.173.19:02:33.84#ibcon#flushed, iclass 18, count 0 2006.173.19:02:33.84#ibcon#about to write, iclass 18, count 0 2006.173.19:02:33.84#ibcon#wrote, iclass 18, count 0 2006.173.19:02:33.84#ibcon#about to read 3, iclass 18, count 0 2006.173.19:02:33.87#ibcon#read 3, iclass 18, count 0 2006.173.19:02:33.87#ibcon#about to read 4, iclass 18, count 0 2006.173.19:02:33.87#ibcon#read 4, iclass 18, count 0 2006.173.19:02:33.87#ibcon#about to read 5, iclass 18, count 0 2006.173.19:02:33.87#ibcon#read 5, iclass 18, count 0 2006.173.19:02:33.87#ibcon#about to read 6, iclass 18, count 0 2006.173.19:02:33.87#ibcon#read 6, iclass 18, count 0 2006.173.19:02:33.87#ibcon#end of sib2, iclass 18, count 0 2006.173.19:02:33.87#ibcon#*after write, iclass 18, count 0 2006.173.19:02:33.87#ibcon#*before return 0, iclass 18, count 0 2006.173.19:02:33.87#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.19:02:33.87#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.19:02:33.87#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.19:02:33.87#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.19:02:33.87$vck44/valo=6,814.99 2006.173.19:02:33.87#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.19:02:33.87#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.19:02:33.87#ibcon#ireg 17 cls_cnt 0 2006.173.19:02:33.87#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.19:02:33.87#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.19:02:33.87#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.19:02:33.87#ibcon#enter wrdev, iclass 20, count 0 2006.173.19:02:33.87#ibcon#first serial, iclass 20, count 0 2006.173.19:02:33.87#ibcon#enter sib2, iclass 20, count 0 2006.173.19:02:33.87#ibcon#flushed, iclass 20, count 0 2006.173.19:02:33.87#ibcon#about to write, iclass 20, count 0 2006.173.19:02:33.87#ibcon#wrote, iclass 20, count 0 2006.173.19:02:33.87#ibcon#about to read 3, iclass 20, count 0 2006.173.19:02:33.89#ibcon#read 3, iclass 20, count 0 2006.173.19:02:33.89#ibcon#about to read 4, iclass 20, count 0 2006.173.19:02:33.89#ibcon#read 4, iclass 20, count 0 2006.173.19:02:33.89#ibcon#about to read 5, iclass 20, count 0 2006.173.19:02:33.89#ibcon#read 5, iclass 20, count 0 2006.173.19:02:33.89#ibcon#about to read 6, iclass 20, count 0 2006.173.19:02:33.89#ibcon#read 6, iclass 20, count 0 2006.173.19:02:33.89#ibcon#end of sib2, iclass 20, count 0 2006.173.19:02:33.89#ibcon#*mode == 0, iclass 20, count 0 2006.173.19:02:33.89#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.19:02:33.89#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.19:02:33.89#ibcon#*before write, iclass 20, count 0 2006.173.19:02:33.89#ibcon#enter sib2, iclass 20, count 0 2006.173.19:02:33.89#ibcon#flushed, iclass 20, count 0 2006.173.19:02:33.89#ibcon#about to write, iclass 20, count 0 2006.173.19:02:33.89#ibcon#wrote, iclass 20, count 0 2006.173.19:02:33.89#ibcon#about to read 3, iclass 20, count 0 2006.173.19:02:33.93#ibcon#read 3, iclass 20, count 0 2006.173.19:02:33.93#ibcon#about to read 4, iclass 20, count 0 2006.173.19:02:33.93#ibcon#read 4, iclass 20, count 0 2006.173.19:02:33.93#ibcon#about to read 5, iclass 20, count 0 2006.173.19:02:33.93#ibcon#read 5, iclass 20, count 0 2006.173.19:02:33.93#ibcon#about to read 6, iclass 20, count 0 2006.173.19:02:33.93#ibcon#read 6, iclass 20, count 0 2006.173.19:02:33.93#ibcon#end of sib2, iclass 20, count 0 2006.173.19:02:33.93#ibcon#*after write, iclass 20, count 0 2006.173.19:02:33.93#ibcon#*before return 0, iclass 20, count 0 2006.173.19:02:33.93#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.19:02:33.93#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.19:02:33.93#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.19:02:33.93#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.19:02:33.93$vck44/va=6,3 2006.173.19:02:33.93#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.19:02:33.93#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.19:02:33.93#ibcon#ireg 11 cls_cnt 2 2006.173.19:02:33.93#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.19:02:33.99#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.19:02:33.99#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.19:02:33.99#ibcon#enter wrdev, iclass 22, count 2 2006.173.19:02:33.99#ibcon#first serial, iclass 22, count 2 2006.173.19:02:33.99#ibcon#enter sib2, iclass 22, count 2 2006.173.19:02:33.99#ibcon#flushed, iclass 22, count 2 2006.173.19:02:33.99#ibcon#about to write, iclass 22, count 2 2006.173.19:02:33.99#ibcon#wrote, iclass 22, count 2 2006.173.19:02:33.99#ibcon#about to read 3, iclass 22, count 2 2006.173.19:02:34.01#ibcon#read 3, iclass 22, count 2 2006.173.19:02:34.01#ibcon#about to read 4, iclass 22, count 2 2006.173.19:02:34.01#ibcon#read 4, iclass 22, count 2 2006.173.19:02:34.01#ibcon#about to read 5, iclass 22, count 2 2006.173.19:02:34.01#ibcon#read 5, iclass 22, count 2 2006.173.19:02:34.01#ibcon#about to read 6, iclass 22, count 2 2006.173.19:02:34.01#ibcon#read 6, iclass 22, count 2 2006.173.19:02:34.01#ibcon#end of sib2, iclass 22, count 2 2006.173.19:02:34.01#ibcon#*mode == 0, iclass 22, count 2 2006.173.19:02:34.01#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.19:02:34.01#ibcon#[25=AT06-03\r\n] 2006.173.19:02:34.01#ibcon#*before write, iclass 22, count 2 2006.173.19:02:34.01#ibcon#enter sib2, iclass 22, count 2 2006.173.19:02:34.01#ibcon#flushed, iclass 22, count 2 2006.173.19:02:34.01#ibcon#about to write, iclass 22, count 2 2006.173.19:02:34.01#ibcon#wrote, iclass 22, count 2 2006.173.19:02:34.01#ibcon#about to read 3, iclass 22, count 2 2006.173.19:02:34.04#ibcon#read 3, iclass 22, count 2 2006.173.19:02:34.04#ibcon#about to read 4, iclass 22, count 2 2006.173.19:02:34.04#ibcon#read 4, iclass 22, count 2 2006.173.19:02:34.04#ibcon#about to read 5, iclass 22, count 2 2006.173.19:02:34.04#ibcon#read 5, iclass 22, count 2 2006.173.19:02:34.04#ibcon#about to read 6, iclass 22, count 2 2006.173.19:02:34.04#ibcon#read 6, iclass 22, count 2 2006.173.19:02:34.04#ibcon#end of sib2, iclass 22, count 2 2006.173.19:02:34.04#ibcon#*after write, iclass 22, count 2 2006.173.19:02:34.04#ibcon#*before return 0, iclass 22, count 2 2006.173.19:02:34.04#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.19:02:34.04#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.19:02:34.04#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.19:02:34.04#ibcon#ireg 7 cls_cnt 0 2006.173.19:02:34.04#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.19:02:34.16#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.19:02:34.16#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.19:02:34.16#ibcon#enter wrdev, iclass 22, count 0 2006.173.19:02:34.16#ibcon#first serial, iclass 22, count 0 2006.173.19:02:34.16#ibcon#enter sib2, iclass 22, count 0 2006.173.19:02:34.16#ibcon#flushed, iclass 22, count 0 2006.173.19:02:34.16#ibcon#about to write, iclass 22, count 0 2006.173.19:02:34.16#ibcon#wrote, iclass 22, count 0 2006.173.19:02:34.16#ibcon#about to read 3, iclass 22, count 0 2006.173.19:02:34.18#ibcon#read 3, iclass 22, count 0 2006.173.19:02:34.18#ibcon#about to read 4, iclass 22, count 0 2006.173.19:02:34.18#ibcon#read 4, iclass 22, count 0 2006.173.19:02:34.18#ibcon#about to read 5, iclass 22, count 0 2006.173.19:02:34.18#ibcon#read 5, iclass 22, count 0 2006.173.19:02:34.18#ibcon#about to read 6, iclass 22, count 0 2006.173.19:02:34.18#ibcon#read 6, iclass 22, count 0 2006.173.19:02:34.18#ibcon#end of sib2, iclass 22, count 0 2006.173.19:02:34.18#ibcon#*mode == 0, iclass 22, count 0 2006.173.19:02:34.18#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.19:02:34.18#ibcon#[25=USB\r\n] 2006.173.19:02:34.18#ibcon#*before write, iclass 22, count 0 2006.173.19:02:34.18#ibcon#enter sib2, iclass 22, count 0 2006.173.19:02:34.18#ibcon#flushed, iclass 22, count 0 2006.173.19:02:34.18#ibcon#about to write, iclass 22, count 0 2006.173.19:02:34.18#ibcon#wrote, iclass 22, count 0 2006.173.19:02:34.18#ibcon#about to read 3, iclass 22, count 0 2006.173.19:02:34.21#ibcon#read 3, iclass 22, count 0 2006.173.19:02:34.21#ibcon#about to read 4, iclass 22, count 0 2006.173.19:02:34.21#ibcon#read 4, iclass 22, count 0 2006.173.19:02:34.21#ibcon#about to read 5, iclass 22, count 0 2006.173.19:02:34.21#ibcon#read 5, iclass 22, count 0 2006.173.19:02:34.21#ibcon#about to read 6, iclass 22, count 0 2006.173.19:02:34.21#ibcon#read 6, iclass 22, count 0 2006.173.19:02:34.21#ibcon#end of sib2, iclass 22, count 0 2006.173.19:02:34.21#ibcon#*after write, iclass 22, count 0 2006.173.19:02:34.21#ibcon#*before return 0, iclass 22, count 0 2006.173.19:02:34.21#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.19:02:34.21#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.19:02:34.21#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.19:02:34.21#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.19:02:34.21$vck44/valo=7,864.99 2006.173.19:02:34.21#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.19:02:34.21#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.19:02:34.21#ibcon#ireg 17 cls_cnt 0 2006.173.19:02:34.21#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.19:02:34.21#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.19:02:34.21#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.19:02:34.21#ibcon#enter wrdev, iclass 24, count 0 2006.173.19:02:34.21#ibcon#first serial, iclass 24, count 0 2006.173.19:02:34.21#ibcon#enter sib2, iclass 24, count 0 2006.173.19:02:34.21#ibcon#flushed, iclass 24, count 0 2006.173.19:02:34.21#ibcon#about to write, iclass 24, count 0 2006.173.19:02:34.21#ibcon#wrote, iclass 24, count 0 2006.173.19:02:34.21#ibcon#about to read 3, iclass 24, count 0 2006.173.19:02:34.23#ibcon#read 3, iclass 24, count 0 2006.173.19:02:34.23#ibcon#about to read 4, iclass 24, count 0 2006.173.19:02:34.23#ibcon#read 4, iclass 24, count 0 2006.173.19:02:34.23#ibcon#about to read 5, iclass 24, count 0 2006.173.19:02:34.23#ibcon#read 5, iclass 24, count 0 2006.173.19:02:34.23#ibcon#about to read 6, iclass 24, count 0 2006.173.19:02:34.23#ibcon#read 6, iclass 24, count 0 2006.173.19:02:34.23#ibcon#end of sib2, iclass 24, count 0 2006.173.19:02:34.23#ibcon#*mode == 0, iclass 24, count 0 2006.173.19:02:34.23#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.19:02:34.23#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.19:02:34.23#ibcon#*before write, iclass 24, count 0 2006.173.19:02:34.23#ibcon#enter sib2, iclass 24, count 0 2006.173.19:02:34.23#ibcon#flushed, iclass 24, count 0 2006.173.19:02:34.23#ibcon#about to write, iclass 24, count 0 2006.173.19:02:34.23#ibcon#wrote, iclass 24, count 0 2006.173.19:02:34.23#ibcon#about to read 3, iclass 24, count 0 2006.173.19:02:34.27#ibcon#read 3, iclass 24, count 0 2006.173.19:02:34.27#ibcon#about to read 4, iclass 24, count 0 2006.173.19:02:34.27#ibcon#read 4, iclass 24, count 0 2006.173.19:02:34.27#ibcon#about to read 5, iclass 24, count 0 2006.173.19:02:34.27#ibcon#read 5, iclass 24, count 0 2006.173.19:02:34.27#ibcon#about to read 6, iclass 24, count 0 2006.173.19:02:34.27#ibcon#read 6, iclass 24, count 0 2006.173.19:02:34.27#ibcon#end of sib2, iclass 24, count 0 2006.173.19:02:34.27#ibcon#*after write, iclass 24, count 0 2006.173.19:02:34.27#ibcon#*before return 0, iclass 24, count 0 2006.173.19:02:34.27#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.19:02:34.27#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.19:02:34.27#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.19:02:34.27#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.19:02:34.27$vck44/va=7,4 2006.173.19:02:34.27#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.19:02:34.27#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.19:02:34.27#ibcon#ireg 11 cls_cnt 2 2006.173.19:02:34.27#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.19:02:34.33#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.19:02:34.33#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.19:02:34.33#ibcon#enter wrdev, iclass 26, count 2 2006.173.19:02:34.33#ibcon#first serial, iclass 26, count 2 2006.173.19:02:34.33#ibcon#enter sib2, iclass 26, count 2 2006.173.19:02:34.33#ibcon#flushed, iclass 26, count 2 2006.173.19:02:34.33#ibcon#about to write, iclass 26, count 2 2006.173.19:02:34.33#ibcon#wrote, iclass 26, count 2 2006.173.19:02:34.33#ibcon#about to read 3, iclass 26, count 2 2006.173.19:02:34.35#ibcon#read 3, iclass 26, count 2 2006.173.19:02:34.35#ibcon#about to read 4, iclass 26, count 2 2006.173.19:02:34.35#ibcon#read 4, iclass 26, count 2 2006.173.19:02:34.35#ibcon#about to read 5, iclass 26, count 2 2006.173.19:02:34.35#ibcon#read 5, iclass 26, count 2 2006.173.19:02:34.35#ibcon#about to read 6, iclass 26, count 2 2006.173.19:02:34.35#ibcon#read 6, iclass 26, count 2 2006.173.19:02:34.35#ibcon#end of sib2, iclass 26, count 2 2006.173.19:02:34.35#ibcon#*mode == 0, iclass 26, count 2 2006.173.19:02:34.35#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.19:02:34.35#ibcon#[25=AT07-04\r\n] 2006.173.19:02:34.35#ibcon#*before write, iclass 26, count 2 2006.173.19:02:34.35#ibcon#enter sib2, iclass 26, count 2 2006.173.19:02:34.35#ibcon#flushed, iclass 26, count 2 2006.173.19:02:34.35#ibcon#about to write, iclass 26, count 2 2006.173.19:02:34.35#ibcon#wrote, iclass 26, count 2 2006.173.19:02:34.35#ibcon#about to read 3, iclass 26, count 2 2006.173.19:02:34.38#ibcon#read 3, iclass 26, count 2 2006.173.19:02:34.38#ibcon#about to read 4, iclass 26, count 2 2006.173.19:02:34.38#ibcon#read 4, iclass 26, count 2 2006.173.19:02:34.38#ibcon#about to read 5, iclass 26, count 2 2006.173.19:02:34.38#ibcon#read 5, iclass 26, count 2 2006.173.19:02:34.38#ibcon#about to read 6, iclass 26, count 2 2006.173.19:02:34.38#ibcon#read 6, iclass 26, count 2 2006.173.19:02:34.38#ibcon#end of sib2, iclass 26, count 2 2006.173.19:02:34.38#ibcon#*after write, iclass 26, count 2 2006.173.19:02:34.38#ibcon#*before return 0, iclass 26, count 2 2006.173.19:02:34.38#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.19:02:34.38#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.19:02:34.38#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.19:02:34.38#ibcon#ireg 7 cls_cnt 0 2006.173.19:02:34.38#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.19:02:34.50#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.19:02:34.50#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.19:02:34.50#ibcon#enter wrdev, iclass 26, count 0 2006.173.19:02:34.50#ibcon#first serial, iclass 26, count 0 2006.173.19:02:34.50#ibcon#enter sib2, iclass 26, count 0 2006.173.19:02:34.50#ibcon#flushed, iclass 26, count 0 2006.173.19:02:34.50#ibcon#about to write, iclass 26, count 0 2006.173.19:02:34.50#ibcon#wrote, iclass 26, count 0 2006.173.19:02:34.50#ibcon#about to read 3, iclass 26, count 0 2006.173.19:02:34.52#ibcon#read 3, iclass 26, count 0 2006.173.19:02:34.52#ibcon#about to read 4, iclass 26, count 0 2006.173.19:02:34.52#ibcon#read 4, iclass 26, count 0 2006.173.19:02:34.52#ibcon#about to read 5, iclass 26, count 0 2006.173.19:02:34.52#ibcon#read 5, iclass 26, count 0 2006.173.19:02:34.52#ibcon#about to read 6, iclass 26, count 0 2006.173.19:02:34.52#ibcon#read 6, iclass 26, count 0 2006.173.19:02:34.52#ibcon#end of sib2, iclass 26, count 0 2006.173.19:02:34.52#ibcon#*mode == 0, iclass 26, count 0 2006.173.19:02:34.52#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.19:02:34.52#ibcon#[25=USB\r\n] 2006.173.19:02:34.52#ibcon#*before write, iclass 26, count 0 2006.173.19:02:34.52#ibcon#enter sib2, iclass 26, count 0 2006.173.19:02:34.52#ibcon#flushed, iclass 26, count 0 2006.173.19:02:34.52#ibcon#about to write, iclass 26, count 0 2006.173.19:02:34.52#ibcon#wrote, iclass 26, count 0 2006.173.19:02:34.52#ibcon#about to read 3, iclass 26, count 0 2006.173.19:02:34.55#ibcon#read 3, iclass 26, count 0 2006.173.19:02:34.55#ibcon#about to read 4, iclass 26, count 0 2006.173.19:02:34.55#ibcon#read 4, iclass 26, count 0 2006.173.19:02:34.55#ibcon#about to read 5, iclass 26, count 0 2006.173.19:02:34.55#ibcon#read 5, iclass 26, count 0 2006.173.19:02:34.55#ibcon#about to read 6, iclass 26, count 0 2006.173.19:02:34.55#ibcon#read 6, iclass 26, count 0 2006.173.19:02:34.55#ibcon#end of sib2, iclass 26, count 0 2006.173.19:02:34.55#ibcon#*after write, iclass 26, count 0 2006.173.19:02:34.55#ibcon#*before return 0, iclass 26, count 0 2006.173.19:02:34.55#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.19:02:34.55#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.19:02:34.55#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.19:02:34.55#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.19:02:34.55$vck44/valo=8,884.99 2006.173.19:02:34.55#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.19:02:34.55#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.19:02:34.55#ibcon#ireg 17 cls_cnt 0 2006.173.19:02:34.55#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.19:02:34.55#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.19:02:34.55#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.19:02:34.55#ibcon#enter wrdev, iclass 28, count 0 2006.173.19:02:34.55#ibcon#first serial, iclass 28, count 0 2006.173.19:02:34.55#ibcon#enter sib2, iclass 28, count 0 2006.173.19:02:34.55#ibcon#flushed, iclass 28, count 0 2006.173.19:02:34.55#ibcon#about to write, iclass 28, count 0 2006.173.19:02:34.55#ibcon#wrote, iclass 28, count 0 2006.173.19:02:34.55#ibcon#about to read 3, iclass 28, count 0 2006.173.19:02:34.57#ibcon#read 3, iclass 28, count 0 2006.173.19:02:34.57#ibcon#about to read 4, iclass 28, count 0 2006.173.19:02:34.57#ibcon#read 4, iclass 28, count 0 2006.173.19:02:34.57#ibcon#about to read 5, iclass 28, count 0 2006.173.19:02:34.57#ibcon#read 5, iclass 28, count 0 2006.173.19:02:34.57#ibcon#about to read 6, iclass 28, count 0 2006.173.19:02:34.57#ibcon#read 6, iclass 28, count 0 2006.173.19:02:34.57#ibcon#end of sib2, iclass 28, count 0 2006.173.19:02:34.57#ibcon#*mode == 0, iclass 28, count 0 2006.173.19:02:34.57#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.19:02:34.57#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.19:02:34.57#ibcon#*before write, iclass 28, count 0 2006.173.19:02:34.57#ibcon#enter sib2, iclass 28, count 0 2006.173.19:02:34.57#ibcon#flushed, iclass 28, count 0 2006.173.19:02:34.57#ibcon#about to write, iclass 28, count 0 2006.173.19:02:34.57#ibcon#wrote, iclass 28, count 0 2006.173.19:02:34.57#ibcon#about to read 3, iclass 28, count 0 2006.173.19:02:34.61#ibcon#read 3, iclass 28, count 0 2006.173.19:02:34.61#ibcon#about to read 4, iclass 28, count 0 2006.173.19:02:34.61#ibcon#read 4, iclass 28, count 0 2006.173.19:02:34.61#ibcon#about to read 5, iclass 28, count 0 2006.173.19:02:34.61#ibcon#read 5, iclass 28, count 0 2006.173.19:02:34.61#ibcon#about to read 6, iclass 28, count 0 2006.173.19:02:34.61#ibcon#read 6, iclass 28, count 0 2006.173.19:02:34.61#ibcon#end of sib2, iclass 28, count 0 2006.173.19:02:34.61#ibcon#*after write, iclass 28, count 0 2006.173.19:02:34.61#ibcon#*before return 0, iclass 28, count 0 2006.173.19:02:34.61#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.19:02:34.61#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.19:02:34.61#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.19:02:34.61#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.19:02:34.61$vck44/va=8,4 2006.173.19:02:34.61#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.19:02:34.61#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.19:02:34.61#ibcon#ireg 11 cls_cnt 2 2006.173.19:02:34.61#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.19:02:34.67#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.19:02:34.67#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.19:02:34.67#ibcon#enter wrdev, iclass 30, count 2 2006.173.19:02:34.67#ibcon#first serial, iclass 30, count 2 2006.173.19:02:34.67#ibcon#enter sib2, iclass 30, count 2 2006.173.19:02:34.67#ibcon#flushed, iclass 30, count 2 2006.173.19:02:34.67#ibcon#about to write, iclass 30, count 2 2006.173.19:02:34.67#ibcon#wrote, iclass 30, count 2 2006.173.19:02:34.67#ibcon#about to read 3, iclass 30, count 2 2006.173.19:02:34.69#ibcon#read 3, iclass 30, count 2 2006.173.19:02:34.69#ibcon#about to read 4, iclass 30, count 2 2006.173.19:02:34.69#ibcon#read 4, iclass 30, count 2 2006.173.19:02:34.69#ibcon#about to read 5, iclass 30, count 2 2006.173.19:02:34.69#ibcon#read 5, iclass 30, count 2 2006.173.19:02:34.69#ibcon#about to read 6, iclass 30, count 2 2006.173.19:02:34.69#ibcon#read 6, iclass 30, count 2 2006.173.19:02:34.69#ibcon#end of sib2, iclass 30, count 2 2006.173.19:02:34.69#ibcon#*mode == 0, iclass 30, count 2 2006.173.19:02:34.69#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.19:02:34.69#ibcon#[25=AT08-04\r\n] 2006.173.19:02:34.69#ibcon#*before write, iclass 30, count 2 2006.173.19:02:34.69#ibcon#enter sib2, iclass 30, count 2 2006.173.19:02:34.69#ibcon#flushed, iclass 30, count 2 2006.173.19:02:34.69#ibcon#about to write, iclass 30, count 2 2006.173.19:02:34.69#ibcon#wrote, iclass 30, count 2 2006.173.19:02:34.69#ibcon#about to read 3, iclass 30, count 2 2006.173.19:02:34.72#ibcon#read 3, iclass 30, count 2 2006.173.19:02:34.72#ibcon#about to read 4, iclass 30, count 2 2006.173.19:02:34.72#ibcon#read 4, iclass 30, count 2 2006.173.19:02:34.72#ibcon#about to read 5, iclass 30, count 2 2006.173.19:02:34.72#ibcon#read 5, iclass 30, count 2 2006.173.19:02:34.72#ibcon#about to read 6, iclass 30, count 2 2006.173.19:02:34.72#ibcon#read 6, iclass 30, count 2 2006.173.19:02:34.72#ibcon#end of sib2, iclass 30, count 2 2006.173.19:02:34.72#ibcon#*after write, iclass 30, count 2 2006.173.19:02:34.72#ibcon#*before return 0, iclass 30, count 2 2006.173.19:02:34.72#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.19:02:34.72#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.19:02:34.72#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.19:02:34.72#ibcon#ireg 7 cls_cnt 0 2006.173.19:02:34.72#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.19:02:34.84#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.19:02:34.84#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.19:02:34.84#ibcon#enter wrdev, iclass 30, count 0 2006.173.19:02:34.84#ibcon#first serial, iclass 30, count 0 2006.173.19:02:34.84#ibcon#enter sib2, iclass 30, count 0 2006.173.19:02:34.84#ibcon#flushed, iclass 30, count 0 2006.173.19:02:34.84#ibcon#about to write, iclass 30, count 0 2006.173.19:02:34.84#ibcon#wrote, iclass 30, count 0 2006.173.19:02:34.84#ibcon#about to read 3, iclass 30, count 0 2006.173.19:02:34.86#ibcon#read 3, iclass 30, count 0 2006.173.19:02:34.86#ibcon#about to read 4, iclass 30, count 0 2006.173.19:02:34.86#ibcon#read 4, iclass 30, count 0 2006.173.19:02:34.86#ibcon#about to read 5, iclass 30, count 0 2006.173.19:02:34.86#ibcon#read 5, iclass 30, count 0 2006.173.19:02:34.86#ibcon#about to read 6, iclass 30, count 0 2006.173.19:02:34.86#ibcon#read 6, iclass 30, count 0 2006.173.19:02:34.86#ibcon#end of sib2, iclass 30, count 0 2006.173.19:02:34.86#ibcon#*mode == 0, iclass 30, count 0 2006.173.19:02:34.86#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.19:02:34.86#ibcon#[25=USB\r\n] 2006.173.19:02:34.86#ibcon#*before write, iclass 30, count 0 2006.173.19:02:34.86#ibcon#enter sib2, iclass 30, count 0 2006.173.19:02:34.86#ibcon#flushed, iclass 30, count 0 2006.173.19:02:34.86#ibcon#about to write, iclass 30, count 0 2006.173.19:02:34.86#ibcon#wrote, iclass 30, count 0 2006.173.19:02:34.86#ibcon#about to read 3, iclass 30, count 0 2006.173.19:02:34.89#ibcon#read 3, iclass 30, count 0 2006.173.19:02:34.89#ibcon#about to read 4, iclass 30, count 0 2006.173.19:02:34.89#ibcon#read 4, iclass 30, count 0 2006.173.19:02:34.89#ibcon#about to read 5, iclass 30, count 0 2006.173.19:02:34.89#ibcon#read 5, iclass 30, count 0 2006.173.19:02:34.89#ibcon#about to read 6, iclass 30, count 0 2006.173.19:02:34.89#ibcon#read 6, iclass 30, count 0 2006.173.19:02:34.89#ibcon#end of sib2, iclass 30, count 0 2006.173.19:02:34.89#ibcon#*after write, iclass 30, count 0 2006.173.19:02:34.89#ibcon#*before return 0, iclass 30, count 0 2006.173.19:02:34.89#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.19:02:34.89#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.19:02:34.89#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.19:02:34.89#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.19:02:34.89$vck44/vblo=1,629.99 2006.173.19:02:34.89#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.19:02:34.89#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.19:02:34.89#ibcon#ireg 17 cls_cnt 0 2006.173.19:02:34.89#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.19:02:34.89#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.19:02:34.89#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.19:02:34.89#ibcon#enter wrdev, iclass 32, count 0 2006.173.19:02:34.89#ibcon#first serial, iclass 32, count 0 2006.173.19:02:34.89#ibcon#enter sib2, iclass 32, count 0 2006.173.19:02:34.89#ibcon#flushed, iclass 32, count 0 2006.173.19:02:34.89#ibcon#about to write, iclass 32, count 0 2006.173.19:02:34.89#ibcon#wrote, iclass 32, count 0 2006.173.19:02:34.89#ibcon#about to read 3, iclass 32, count 0 2006.173.19:02:34.91#ibcon#read 3, iclass 32, count 0 2006.173.19:02:34.91#ibcon#about to read 4, iclass 32, count 0 2006.173.19:02:34.91#ibcon#read 4, iclass 32, count 0 2006.173.19:02:34.91#ibcon#about to read 5, iclass 32, count 0 2006.173.19:02:34.91#ibcon#read 5, iclass 32, count 0 2006.173.19:02:34.91#ibcon#about to read 6, iclass 32, count 0 2006.173.19:02:34.91#ibcon#read 6, iclass 32, count 0 2006.173.19:02:34.91#ibcon#end of sib2, iclass 32, count 0 2006.173.19:02:34.91#ibcon#*mode == 0, iclass 32, count 0 2006.173.19:02:34.91#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.19:02:34.91#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.19:02:34.91#ibcon#*before write, iclass 32, count 0 2006.173.19:02:34.91#ibcon#enter sib2, iclass 32, count 0 2006.173.19:02:34.91#ibcon#flushed, iclass 32, count 0 2006.173.19:02:34.91#ibcon#about to write, iclass 32, count 0 2006.173.19:02:34.91#ibcon#wrote, iclass 32, count 0 2006.173.19:02:34.91#ibcon#about to read 3, iclass 32, count 0 2006.173.19:02:34.95#ibcon#read 3, iclass 32, count 0 2006.173.19:02:34.95#ibcon#about to read 4, iclass 32, count 0 2006.173.19:02:34.95#ibcon#read 4, iclass 32, count 0 2006.173.19:02:34.95#ibcon#about to read 5, iclass 32, count 0 2006.173.19:02:34.95#ibcon#read 5, iclass 32, count 0 2006.173.19:02:34.95#ibcon#about to read 6, iclass 32, count 0 2006.173.19:02:34.95#ibcon#read 6, iclass 32, count 0 2006.173.19:02:34.95#ibcon#end of sib2, iclass 32, count 0 2006.173.19:02:34.95#ibcon#*after write, iclass 32, count 0 2006.173.19:02:34.95#ibcon#*before return 0, iclass 32, count 0 2006.173.19:02:34.95#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.19:02:34.95#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.19:02:34.95#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.19:02:34.95#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.19:02:34.95$vck44/vb=1,4 2006.173.19:02:34.95#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.19:02:34.95#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.19:02:34.95#ibcon#ireg 11 cls_cnt 2 2006.173.19:02:34.95#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.19:02:34.95#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.19:02:34.95#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.19:02:34.95#ibcon#enter wrdev, iclass 34, count 2 2006.173.19:02:34.95#ibcon#first serial, iclass 34, count 2 2006.173.19:02:34.95#ibcon#enter sib2, iclass 34, count 2 2006.173.19:02:34.95#ibcon#flushed, iclass 34, count 2 2006.173.19:02:34.95#ibcon#about to write, iclass 34, count 2 2006.173.19:02:34.95#ibcon#wrote, iclass 34, count 2 2006.173.19:02:34.95#ibcon#about to read 3, iclass 34, count 2 2006.173.19:02:34.97#ibcon#read 3, iclass 34, count 2 2006.173.19:02:34.97#ibcon#about to read 4, iclass 34, count 2 2006.173.19:02:34.97#ibcon#read 4, iclass 34, count 2 2006.173.19:02:34.97#ibcon#about to read 5, iclass 34, count 2 2006.173.19:02:34.97#ibcon#read 5, iclass 34, count 2 2006.173.19:02:34.97#ibcon#about to read 6, iclass 34, count 2 2006.173.19:02:34.97#ibcon#read 6, iclass 34, count 2 2006.173.19:02:34.97#ibcon#end of sib2, iclass 34, count 2 2006.173.19:02:34.97#ibcon#*mode == 0, iclass 34, count 2 2006.173.19:02:34.97#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.19:02:34.97#ibcon#[27=AT01-04\r\n] 2006.173.19:02:34.97#ibcon#*before write, iclass 34, count 2 2006.173.19:02:34.97#ibcon#enter sib2, iclass 34, count 2 2006.173.19:02:34.97#ibcon#flushed, iclass 34, count 2 2006.173.19:02:34.97#ibcon#about to write, iclass 34, count 2 2006.173.19:02:34.97#ibcon#wrote, iclass 34, count 2 2006.173.19:02:34.97#ibcon#about to read 3, iclass 34, count 2 2006.173.19:02:35.00#ibcon#read 3, iclass 34, count 2 2006.173.19:02:35.00#ibcon#about to read 4, iclass 34, count 2 2006.173.19:02:35.00#ibcon#read 4, iclass 34, count 2 2006.173.19:02:35.00#ibcon#about to read 5, iclass 34, count 2 2006.173.19:02:35.00#ibcon#read 5, iclass 34, count 2 2006.173.19:02:35.00#ibcon#about to read 6, iclass 34, count 2 2006.173.19:02:35.00#ibcon#read 6, iclass 34, count 2 2006.173.19:02:35.00#ibcon#end of sib2, iclass 34, count 2 2006.173.19:02:35.00#ibcon#*after write, iclass 34, count 2 2006.173.19:02:35.00#ibcon#*before return 0, iclass 34, count 2 2006.173.19:02:35.00#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.19:02:35.00#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.19:02:35.00#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.19:02:35.00#ibcon#ireg 7 cls_cnt 0 2006.173.19:02:35.00#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.19:02:35.12#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.19:02:35.12#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.19:02:35.12#ibcon#enter wrdev, iclass 34, count 0 2006.173.19:02:35.12#ibcon#first serial, iclass 34, count 0 2006.173.19:02:35.12#ibcon#enter sib2, iclass 34, count 0 2006.173.19:02:35.12#ibcon#flushed, iclass 34, count 0 2006.173.19:02:35.12#ibcon#about to write, iclass 34, count 0 2006.173.19:02:35.12#ibcon#wrote, iclass 34, count 0 2006.173.19:02:35.12#ibcon#about to read 3, iclass 34, count 0 2006.173.19:02:35.14#ibcon#read 3, iclass 34, count 0 2006.173.19:02:35.14#ibcon#about to read 4, iclass 34, count 0 2006.173.19:02:35.14#ibcon#read 4, iclass 34, count 0 2006.173.19:02:35.14#ibcon#about to read 5, iclass 34, count 0 2006.173.19:02:35.14#ibcon#read 5, iclass 34, count 0 2006.173.19:02:35.14#ibcon#about to read 6, iclass 34, count 0 2006.173.19:02:35.14#ibcon#read 6, iclass 34, count 0 2006.173.19:02:35.14#ibcon#end of sib2, iclass 34, count 0 2006.173.19:02:35.14#ibcon#*mode == 0, iclass 34, count 0 2006.173.19:02:35.14#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.19:02:35.14#ibcon#[27=USB\r\n] 2006.173.19:02:35.14#ibcon#*before write, iclass 34, count 0 2006.173.19:02:35.14#ibcon#enter sib2, iclass 34, count 0 2006.173.19:02:35.14#ibcon#flushed, iclass 34, count 0 2006.173.19:02:35.14#ibcon#about to write, iclass 34, count 0 2006.173.19:02:35.14#ibcon#wrote, iclass 34, count 0 2006.173.19:02:35.14#ibcon#about to read 3, iclass 34, count 0 2006.173.19:02:35.17#ibcon#read 3, iclass 34, count 0 2006.173.19:02:35.17#ibcon#about to read 4, iclass 34, count 0 2006.173.19:02:35.17#ibcon#read 4, iclass 34, count 0 2006.173.19:02:35.17#ibcon#about to read 5, iclass 34, count 0 2006.173.19:02:35.17#ibcon#read 5, iclass 34, count 0 2006.173.19:02:35.17#ibcon#about to read 6, iclass 34, count 0 2006.173.19:02:35.17#ibcon#read 6, iclass 34, count 0 2006.173.19:02:35.17#ibcon#end of sib2, iclass 34, count 0 2006.173.19:02:35.17#ibcon#*after write, iclass 34, count 0 2006.173.19:02:35.17#ibcon#*before return 0, iclass 34, count 0 2006.173.19:02:35.17#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.19:02:35.17#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.19:02:35.17#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.19:02:35.17#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.19:02:35.17$vck44/vblo=2,634.99 2006.173.19:02:35.17#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.19:02:35.17#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.19:02:35.17#ibcon#ireg 17 cls_cnt 0 2006.173.19:02:35.17#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.19:02:35.17#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.19:02:35.17#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.19:02:35.17#ibcon#enter wrdev, iclass 36, count 0 2006.173.19:02:35.17#ibcon#first serial, iclass 36, count 0 2006.173.19:02:35.17#ibcon#enter sib2, iclass 36, count 0 2006.173.19:02:35.17#ibcon#flushed, iclass 36, count 0 2006.173.19:02:35.17#ibcon#about to write, iclass 36, count 0 2006.173.19:02:35.17#ibcon#wrote, iclass 36, count 0 2006.173.19:02:35.17#ibcon#about to read 3, iclass 36, count 0 2006.173.19:02:35.19#ibcon#read 3, iclass 36, count 0 2006.173.19:02:35.19#ibcon#about to read 4, iclass 36, count 0 2006.173.19:02:35.19#ibcon#read 4, iclass 36, count 0 2006.173.19:02:35.19#ibcon#about to read 5, iclass 36, count 0 2006.173.19:02:35.19#ibcon#read 5, iclass 36, count 0 2006.173.19:02:35.19#ibcon#about to read 6, iclass 36, count 0 2006.173.19:02:35.19#ibcon#read 6, iclass 36, count 0 2006.173.19:02:35.19#ibcon#end of sib2, iclass 36, count 0 2006.173.19:02:35.19#ibcon#*mode == 0, iclass 36, count 0 2006.173.19:02:35.19#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.19:02:35.19#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.19:02:35.19#ibcon#*before write, iclass 36, count 0 2006.173.19:02:35.19#ibcon#enter sib2, iclass 36, count 0 2006.173.19:02:35.19#ibcon#flushed, iclass 36, count 0 2006.173.19:02:35.19#ibcon#about to write, iclass 36, count 0 2006.173.19:02:35.19#ibcon#wrote, iclass 36, count 0 2006.173.19:02:35.19#ibcon#about to read 3, iclass 36, count 0 2006.173.19:02:35.23#ibcon#read 3, iclass 36, count 0 2006.173.19:02:35.23#ibcon#about to read 4, iclass 36, count 0 2006.173.19:02:35.23#ibcon#read 4, iclass 36, count 0 2006.173.19:02:35.23#ibcon#about to read 5, iclass 36, count 0 2006.173.19:02:35.23#ibcon#read 5, iclass 36, count 0 2006.173.19:02:35.23#ibcon#about to read 6, iclass 36, count 0 2006.173.19:02:35.23#ibcon#read 6, iclass 36, count 0 2006.173.19:02:35.23#ibcon#end of sib2, iclass 36, count 0 2006.173.19:02:35.23#ibcon#*after write, iclass 36, count 0 2006.173.19:02:35.23#ibcon#*before return 0, iclass 36, count 0 2006.173.19:02:35.23#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.19:02:35.23#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.19:02:35.23#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.19:02:35.23#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.19:02:35.23$vck44/vb=2,4 2006.173.19:02:35.23#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.19:02:35.23#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.19:02:35.23#ibcon#ireg 11 cls_cnt 2 2006.173.19:02:35.23#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.19:02:35.29#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.19:02:35.29#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.19:02:35.29#ibcon#enter wrdev, iclass 38, count 2 2006.173.19:02:35.29#ibcon#first serial, iclass 38, count 2 2006.173.19:02:35.29#ibcon#enter sib2, iclass 38, count 2 2006.173.19:02:35.29#ibcon#flushed, iclass 38, count 2 2006.173.19:02:35.29#ibcon#about to write, iclass 38, count 2 2006.173.19:02:35.29#ibcon#wrote, iclass 38, count 2 2006.173.19:02:35.29#ibcon#about to read 3, iclass 38, count 2 2006.173.19:02:35.31#ibcon#read 3, iclass 38, count 2 2006.173.19:02:35.31#ibcon#about to read 4, iclass 38, count 2 2006.173.19:02:35.31#ibcon#read 4, iclass 38, count 2 2006.173.19:02:35.31#ibcon#about to read 5, iclass 38, count 2 2006.173.19:02:35.31#ibcon#read 5, iclass 38, count 2 2006.173.19:02:35.31#ibcon#about to read 6, iclass 38, count 2 2006.173.19:02:35.31#ibcon#read 6, iclass 38, count 2 2006.173.19:02:35.31#ibcon#end of sib2, iclass 38, count 2 2006.173.19:02:35.31#ibcon#*mode == 0, iclass 38, count 2 2006.173.19:02:35.31#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.19:02:35.31#ibcon#[27=AT02-04\r\n] 2006.173.19:02:35.31#ibcon#*before write, iclass 38, count 2 2006.173.19:02:35.31#ibcon#enter sib2, iclass 38, count 2 2006.173.19:02:35.31#ibcon#flushed, iclass 38, count 2 2006.173.19:02:35.31#ibcon#about to write, iclass 38, count 2 2006.173.19:02:35.31#ibcon#wrote, iclass 38, count 2 2006.173.19:02:35.31#ibcon#about to read 3, iclass 38, count 2 2006.173.19:02:35.34#ibcon#read 3, iclass 38, count 2 2006.173.19:02:35.34#ibcon#about to read 4, iclass 38, count 2 2006.173.19:02:35.34#ibcon#read 4, iclass 38, count 2 2006.173.19:02:35.34#ibcon#about to read 5, iclass 38, count 2 2006.173.19:02:35.34#ibcon#read 5, iclass 38, count 2 2006.173.19:02:35.34#ibcon#about to read 6, iclass 38, count 2 2006.173.19:02:35.34#ibcon#read 6, iclass 38, count 2 2006.173.19:02:35.34#ibcon#end of sib2, iclass 38, count 2 2006.173.19:02:35.34#ibcon#*after write, iclass 38, count 2 2006.173.19:02:35.34#ibcon#*before return 0, iclass 38, count 2 2006.173.19:02:35.34#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.19:02:35.34#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.19:02:35.34#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.19:02:35.34#ibcon#ireg 7 cls_cnt 0 2006.173.19:02:35.34#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.19:02:35.46#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.19:02:35.46#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.19:02:35.46#ibcon#enter wrdev, iclass 38, count 0 2006.173.19:02:35.46#ibcon#first serial, iclass 38, count 0 2006.173.19:02:35.46#ibcon#enter sib2, iclass 38, count 0 2006.173.19:02:35.46#ibcon#flushed, iclass 38, count 0 2006.173.19:02:35.46#ibcon#about to write, iclass 38, count 0 2006.173.19:02:35.46#ibcon#wrote, iclass 38, count 0 2006.173.19:02:35.46#ibcon#about to read 3, iclass 38, count 0 2006.173.19:02:35.48#ibcon#read 3, iclass 38, count 0 2006.173.19:02:35.48#ibcon#about to read 4, iclass 38, count 0 2006.173.19:02:35.48#ibcon#read 4, iclass 38, count 0 2006.173.19:02:35.48#ibcon#about to read 5, iclass 38, count 0 2006.173.19:02:35.48#ibcon#read 5, iclass 38, count 0 2006.173.19:02:35.48#ibcon#about to read 6, iclass 38, count 0 2006.173.19:02:35.48#ibcon#read 6, iclass 38, count 0 2006.173.19:02:35.48#ibcon#end of sib2, iclass 38, count 0 2006.173.19:02:35.48#ibcon#*mode == 0, iclass 38, count 0 2006.173.19:02:35.48#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.19:02:35.48#ibcon#[27=USB\r\n] 2006.173.19:02:35.48#ibcon#*before write, iclass 38, count 0 2006.173.19:02:35.48#ibcon#enter sib2, iclass 38, count 0 2006.173.19:02:35.48#ibcon#flushed, iclass 38, count 0 2006.173.19:02:35.48#ibcon#about to write, iclass 38, count 0 2006.173.19:02:35.48#ibcon#wrote, iclass 38, count 0 2006.173.19:02:35.48#ibcon#about to read 3, iclass 38, count 0 2006.173.19:02:35.51#ibcon#read 3, iclass 38, count 0 2006.173.19:02:35.51#ibcon#about to read 4, iclass 38, count 0 2006.173.19:02:35.51#ibcon#read 4, iclass 38, count 0 2006.173.19:02:35.51#ibcon#about to read 5, iclass 38, count 0 2006.173.19:02:35.51#ibcon#read 5, iclass 38, count 0 2006.173.19:02:35.51#ibcon#about to read 6, iclass 38, count 0 2006.173.19:02:35.51#ibcon#read 6, iclass 38, count 0 2006.173.19:02:35.51#ibcon#end of sib2, iclass 38, count 0 2006.173.19:02:35.51#ibcon#*after write, iclass 38, count 0 2006.173.19:02:35.51#ibcon#*before return 0, iclass 38, count 0 2006.173.19:02:35.51#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.19:02:35.51#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.19:02:35.51#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.19:02:35.51#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.19:02:35.51$vck44/vblo=3,649.99 2006.173.19:02:35.51#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.19:02:35.51#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.19:02:35.51#ibcon#ireg 17 cls_cnt 0 2006.173.19:02:35.51#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.19:02:35.51#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.19:02:35.51#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.19:02:35.51#ibcon#enter wrdev, iclass 40, count 0 2006.173.19:02:35.51#ibcon#first serial, iclass 40, count 0 2006.173.19:02:35.51#ibcon#enter sib2, iclass 40, count 0 2006.173.19:02:35.51#ibcon#flushed, iclass 40, count 0 2006.173.19:02:35.51#ibcon#about to write, iclass 40, count 0 2006.173.19:02:35.51#ibcon#wrote, iclass 40, count 0 2006.173.19:02:35.51#ibcon#about to read 3, iclass 40, count 0 2006.173.19:02:35.53#ibcon#read 3, iclass 40, count 0 2006.173.19:02:35.53#ibcon#about to read 4, iclass 40, count 0 2006.173.19:02:35.53#ibcon#read 4, iclass 40, count 0 2006.173.19:02:35.53#ibcon#about to read 5, iclass 40, count 0 2006.173.19:02:35.53#ibcon#read 5, iclass 40, count 0 2006.173.19:02:35.53#ibcon#about to read 6, iclass 40, count 0 2006.173.19:02:35.53#ibcon#read 6, iclass 40, count 0 2006.173.19:02:35.53#ibcon#end of sib2, iclass 40, count 0 2006.173.19:02:35.53#ibcon#*mode == 0, iclass 40, count 0 2006.173.19:02:35.53#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.19:02:35.53#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.19:02:35.53#ibcon#*before write, iclass 40, count 0 2006.173.19:02:35.53#ibcon#enter sib2, iclass 40, count 0 2006.173.19:02:35.53#ibcon#flushed, iclass 40, count 0 2006.173.19:02:35.53#ibcon#about to write, iclass 40, count 0 2006.173.19:02:35.53#ibcon#wrote, iclass 40, count 0 2006.173.19:02:35.53#ibcon#about to read 3, iclass 40, count 0 2006.173.19:02:35.57#ibcon#read 3, iclass 40, count 0 2006.173.19:02:35.57#ibcon#about to read 4, iclass 40, count 0 2006.173.19:02:35.57#ibcon#read 4, iclass 40, count 0 2006.173.19:02:35.57#ibcon#about to read 5, iclass 40, count 0 2006.173.19:02:35.57#ibcon#read 5, iclass 40, count 0 2006.173.19:02:35.57#ibcon#about to read 6, iclass 40, count 0 2006.173.19:02:35.57#ibcon#read 6, iclass 40, count 0 2006.173.19:02:35.57#ibcon#end of sib2, iclass 40, count 0 2006.173.19:02:35.57#ibcon#*after write, iclass 40, count 0 2006.173.19:02:35.57#ibcon#*before return 0, iclass 40, count 0 2006.173.19:02:35.57#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.19:02:35.57#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.19:02:35.57#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.19:02:35.57#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.19:02:35.57$vck44/vb=3,4 2006.173.19:02:35.57#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.19:02:35.57#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.19:02:35.57#ibcon#ireg 11 cls_cnt 2 2006.173.19:02:35.57#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.19:02:35.63#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.19:02:35.63#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.19:02:35.63#ibcon#enter wrdev, iclass 4, count 2 2006.173.19:02:35.63#ibcon#first serial, iclass 4, count 2 2006.173.19:02:35.63#ibcon#enter sib2, iclass 4, count 2 2006.173.19:02:35.63#ibcon#flushed, iclass 4, count 2 2006.173.19:02:35.63#ibcon#about to write, iclass 4, count 2 2006.173.19:02:35.63#ibcon#wrote, iclass 4, count 2 2006.173.19:02:35.63#ibcon#about to read 3, iclass 4, count 2 2006.173.19:02:35.65#ibcon#read 3, iclass 4, count 2 2006.173.19:02:35.65#ibcon#about to read 4, iclass 4, count 2 2006.173.19:02:35.65#ibcon#read 4, iclass 4, count 2 2006.173.19:02:35.65#ibcon#about to read 5, iclass 4, count 2 2006.173.19:02:35.65#ibcon#read 5, iclass 4, count 2 2006.173.19:02:35.65#ibcon#about to read 6, iclass 4, count 2 2006.173.19:02:35.65#ibcon#read 6, iclass 4, count 2 2006.173.19:02:35.65#ibcon#end of sib2, iclass 4, count 2 2006.173.19:02:35.65#ibcon#*mode == 0, iclass 4, count 2 2006.173.19:02:35.65#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.19:02:35.65#ibcon#[27=AT03-04\r\n] 2006.173.19:02:35.65#ibcon#*before write, iclass 4, count 2 2006.173.19:02:35.65#ibcon#enter sib2, iclass 4, count 2 2006.173.19:02:35.65#ibcon#flushed, iclass 4, count 2 2006.173.19:02:35.65#ibcon#about to write, iclass 4, count 2 2006.173.19:02:35.65#ibcon#wrote, iclass 4, count 2 2006.173.19:02:35.65#ibcon#about to read 3, iclass 4, count 2 2006.173.19:02:35.68#ibcon#read 3, iclass 4, count 2 2006.173.19:02:35.68#ibcon#about to read 4, iclass 4, count 2 2006.173.19:02:35.68#ibcon#read 4, iclass 4, count 2 2006.173.19:02:35.68#ibcon#about to read 5, iclass 4, count 2 2006.173.19:02:35.68#ibcon#read 5, iclass 4, count 2 2006.173.19:02:35.68#ibcon#about to read 6, iclass 4, count 2 2006.173.19:02:35.68#ibcon#read 6, iclass 4, count 2 2006.173.19:02:35.68#ibcon#end of sib2, iclass 4, count 2 2006.173.19:02:35.68#ibcon#*after write, iclass 4, count 2 2006.173.19:02:35.68#ibcon#*before return 0, iclass 4, count 2 2006.173.19:02:35.68#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.19:02:35.68#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.19:02:35.68#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.19:02:35.68#ibcon#ireg 7 cls_cnt 0 2006.173.19:02:35.68#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.19:02:35.80#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.19:02:35.80#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.19:02:35.80#ibcon#enter wrdev, iclass 4, count 0 2006.173.19:02:35.80#ibcon#first serial, iclass 4, count 0 2006.173.19:02:35.80#ibcon#enter sib2, iclass 4, count 0 2006.173.19:02:35.80#ibcon#flushed, iclass 4, count 0 2006.173.19:02:35.80#ibcon#about to write, iclass 4, count 0 2006.173.19:02:35.80#ibcon#wrote, iclass 4, count 0 2006.173.19:02:35.80#ibcon#about to read 3, iclass 4, count 0 2006.173.19:02:35.82#ibcon#read 3, iclass 4, count 0 2006.173.19:02:35.82#ibcon#about to read 4, iclass 4, count 0 2006.173.19:02:35.82#ibcon#read 4, iclass 4, count 0 2006.173.19:02:35.82#ibcon#about to read 5, iclass 4, count 0 2006.173.19:02:35.82#ibcon#read 5, iclass 4, count 0 2006.173.19:02:35.82#ibcon#about to read 6, iclass 4, count 0 2006.173.19:02:35.82#ibcon#read 6, iclass 4, count 0 2006.173.19:02:35.82#ibcon#end of sib2, iclass 4, count 0 2006.173.19:02:35.82#ibcon#*mode == 0, iclass 4, count 0 2006.173.19:02:35.82#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.19:02:35.82#ibcon#[27=USB\r\n] 2006.173.19:02:35.82#ibcon#*before write, iclass 4, count 0 2006.173.19:02:35.82#ibcon#enter sib2, iclass 4, count 0 2006.173.19:02:35.82#ibcon#flushed, iclass 4, count 0 2006.173.19:02:35.82#ibcon#about to write, iclass 4, count 0 2006.173.19:02:35.82#ibcon#wrote, iclass 4, count 0 2006.173.19:02:35.82#ibcon#about to read 3, iclass 4, count 0 2006.173.19:02:35.85#ibcon#read 3, iclass 4, count 0 2006.173.19:02:35.85#ibcon#about to read 4, iclass 4, count 0 2006.173.19:02:35.85#ibcon#read 4, iclass 4, count 0 2006.173.19:02:35.85#ibcon#about to read 5, iclass 4, count 0 2006.173.19:02:35.85#ibcon#read 5, iclass 4, count 0 2006.173.19:02:35.85#ibcon#about to read 6, iclass 4, count 0 2006.173.19:02:35.85#ibcon#read 6, iclass 4, count 0 2006.173.19:02:35.85#ibcon#end of sib2, iclass 4, count 0 2006.173.19:02:35.85#ibcon#*after write, iclass 4, count 0 2006.173.19:02:35.85#ibcon#*before return 0, iclass 4, count 0 2006.173.19:02:35.85#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.19:02:35.85#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.19:02:35.85#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.19:02:35.85#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.19:02:35.85$vck44/vblo=4,679.99 2006.173.19:02:35.85#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.19:02:35.85#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.19:02:35.85#ibcon#ireg 17 cls_cnt 0 2006.173.19:02:35.85#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.19:02:35.85#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.19:02:35.85#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.19:02:35.85#ibcon#enter wrdev, iclass 6, count 0 2006.173.19:02:35.85#ibcon#first serial, iclass 6, count 0 2006.173.19:02:35.85#ibcon#enter sib2, iclass 6, count 0 2006.173.19:02:35.85#ibcon#flushed, iclass 6, count 0 2006.173.19:02:35.85#ibcon#about to write, iclass 6, count 0 2006.173.19:02:35.85#ibcon#wrote, iclass 6, count 0 2006.173.19:02:35.85#ibcon#about to read 3, iclass 6, count 0 2006.173.19:02:35.87#ibcon#read 3, iclass 6, count 0 2006.173.19:02:35.87#ibcon#about to read 4, iclass 6, count 0 2006.173.19:02:35.87#ibcon#read 4, iclass 6, count 0 2006.173.19:02:35.87#ibcon#about to read 5, iclass 6, count 0 2006.173.19:02:35.87#ibcon#read 5, iclass 6, count 0 2006.173.19:02:35.87#ibcon#about to read 6, iclass 6, count 0 2006.173.19:02:35.87#ibcon#read 6, iclass 6, count 0 2006.173.19:02:35.87#ibcon#end of sib2, iclass 6, count 0 2006.173.19:02:35.87#ibcon#*mode == 0, iclass 6, count 0 2006.173.19:02:35.87#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.19:02:35.87#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.19:02:35.87#ibcon#*before write, iclass 6, count 0 2006.173.19:02:35.87#ibcon#enter sib2, iclass 6, count 0 2006.173.19:02:35.87#ibcon#flushed, iclass 6, count 0 2006.173.19:02:35.87#ibcon#about to write, iclass 6, count 0 2006.173.19:02:35.87#ibcon#wrote, iclass 6, count 0 2006.173.19:02:35.87#ibcon#about to read 3, iclass 6, count 0 2006.173.19:02:35.91#ibcon#read 3, iclass 6, count 0 2006.173.19:02:35.91#ibcon#about to read 4, iclass 6, count 0 2006.173.19:02:35.91#ibcon#read 4, iclass 6, count 0 2006.173.19:02:35.91#ibcon#about to read 5, iclass 6, count 0 2006.173.19:02:35.91#ibcon#read 5, iclass 6, count 0 2006.173.19:02:35.91#ibcon#about to read 6, iclass 6, count 0 2006.173.19:02:35.91#ibcon#read 6, iclass 6, count 0 2006.173.19:02:35.91#ibcon#end of sib2, iclass 6, count 0 2006.173.19:02:35.91#ibcon#*after write, iclass 6, count 0 2006.173.19:02:35.91#ibcon#*before return 0, iclass 6, count 0 2006.173.19:02:35.91#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.19:02:35.91#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.19:02:35.91#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.19:02:35.91#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.19:02:35.91$vck44/vb=4,4 2006.173.19:02:35.91#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.19:02:35.91#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.19:02:35.91#ibcon#ireg 11 cls_cnt 2 2006.173.19:02:35.91#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.19:02:35.97#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.19:02:35.97#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.19:02:35.97#ibcon#enter wrdev, iclass 10, count 2 2006.173.19:02:35.97#ibcon#first serial, iclass 10, count 2 2006.173.19:02:35.97#ibcon#enter sib2, iclass 10, count 2 2006.173.19:02:35.97#ibcon#flushed, iclass 10, count 2 2006.173.19:02:35.97#ibcon#about to write, iclass 10, count 2 2006.173.19:02:35.97#ibcon#wrote, iclass 10, count 2 2006.173.19:02:35.97#ibcon#about to read 3, iclass 10, count 2 2006.173.19:02:35.99#ibcon#read 3, iclass 10, count 2 2006.173.19:02:35.99#ibcon#about to read 4, iclass 10, count 2 2006.173.19:02:35.99#ibcon#read 4, iclass 10, count 2 2006.173.19:02:35.99#ibcon#about to read 5, iclass 10, count 2 2006.173.19:02:35.99#ibcon#read 5, iclass 10, count 2 2006.173.19:02:35.99#ibcon#about to read 6, iclass 10, count 2 2006.173.19:02:35.99#ibcon#read 6, iclass 10, count 2 2006.173.19:02:35.99#ibcon#end of sib2, iclass 10, count 2 2006.173.19:02:35.99#ibcon#*mode == 0, iclass 10, count 2 2006.173.19:02:35.99#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.19:02:35.99#ibcon#[27=AT04-04\r\n] 2006.173.19:02:35.99#ibcon#*before write, iclass 10, count 2 2006.173.19:02:35.99#ibcon#enter sib2, iclass 10, count 2 2006.173.19:02:35.99#ibcon#flushed, iclass 10, count 2 2006.173.19:02:35.99#ibcon#about to write, iclass 10, count 2 2006.173.19:02:35.99#ibcon#wrote, iclass 10, count 2 2006.173.19:02:35.99#ibcon#about to read 3, iclass 10, count 2 2006.173.19:02:36.02#ibcon#read 3, iclass 10, count 2 2006.173.19:02:36.02#ibcon#about to read 4, iclass 10, count 2 2006.173.19:02:36.02#ibcon#read 4, iclass 10, count 2 2006.173.19:02:36.02#ibcon#about to read 5, iclass 10, count 2 2006.173.19:02:36.02#ibcon#read 5, iclass 10, count 2 2006.173.19:02:36.02#ibcon#about to read 6, iclass 10, count 2 2006.173.19:02:36.02#ibcon#read 6, iclass 10, count 2 2006.173.19:02:36.02#ibcon#end of sib2, iclass 10, count 2 2006.173.19:02:36.02#ibcon#*after write, iclass 10, count 2 2006.173.19:02:36.02#ibcon#*before return 0, iclass 10, count 2 2006.173.19:02:36.02#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.19:02:36.02#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.19:02:36.02#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.19:02:36.02#ibcon#ireg 7 cls_cnt 0 2006.173.19:02:36.02#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.19:02:36.14#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.19:02:36.14#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.19:02:36.14#ibcon#enter wrdev, iclass 10, count 0 2006.173.19:02:36.14#ibcon#first serial, iclass 10, count 0 2006.173.19:02:36.14#ibcon#enter sib2, iclass 10, count 0 2006.173.19:02:36.14#ibcon#flushed, iclass 10, count 0 2006.173.19:02:36.14#ibcon#about to write, iclass 10, count 0 2006.173.19:02:36.14#ibcon#wrote, iclass 10, count 0 2006.173.19:02:36.14#ibcon#about to read 3, iclass 10, count 0 2006.173.19:02:36.16#ibcon#read 3, iclass 10, count 0 2006.173.19:02:36.16#ibcon#about to read 4, iclass 10, count 0 2006.173.19:02:36.16#ibcon#read 4, iclass 10, count 0 2006.173.19:02:36.16#ibcon#about to read 5, iclass 10, count 0 2006.173.19:02:36.16#ibcon#read 5, iclass 10, count 0 2006.173.19:02:36.16#ibcon#about to read 6, iclass 10, count 0 2006.173.19:02:36.16#ibcon#read 6, iclass 10, count 0 2006.173.19:02:36.16#ibcon#end of sib2, iclass 10, count 0 2006.173.19:02:36.16#ibcon#*mode == 0, iclass 10, count 0 2006.173.19:02:36.16#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.19:02:36.16#ibcon#[27=USB\r\n] 2006.173.19:02:36.16#ibcon#*before write, iclass 10, count 0 2006.173.19:02:36.16#ibcon#enter sib2, iclass 10, count 0 2006.173.19:02:36.16#ibcon#flushed, iclass 10, count 0 2006.173.19:02:36.16#ibcon#about to write, iclass 10, count 0 2006.173.19:02:36.16#ibcon#wrote, iclass 10, count 0 2006.173.19:02:36.16#ibcon#about to read 3, iclass 10, count 0 2006.173.19:02:36.19#ibcon#read 3, iclass 10, count 0 2006.173.19:02:36.19#ibcon#about to read 4, iclass 10, count 0 2006.173.19:02:36.19#ibcon#read 4, iclass 10, count 0 2006.173.19:02:36.19#ibcon#about to read 5, iclass 10, count 0 2006.173.19:02:36.19#ibcon#read 5, iclass 10, count 0 2006.173.19:02:36.19#ibcon#about to read 6, iclass 10, count 0 2006.173.19:02:36.19#ibcon#read 6, iclass 10, count 0 2006.173.19:02:36.19#ibcon#end of sib2, iclass 10, count 0 2006.173.19:02:36.19#ibcon#*after write, iclass 10, count 0 2006.173.19:02:36.19#ibcon#*before return 0, iclass 10, count 0 2006.173.19:02:36.19#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.19:02:36.19#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.19:02:36.19#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.19:02:36.19#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.19:02:36.19$vck44/vblo=5,709.99 2006.173.19:02:36.19#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.19:02:36.19#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.19:02:36.19#ibcon#ireg 17 cls_cnt 0 2006.173.19:02:36.19#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.19:02:36.19#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.19:02:36.19#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.19:02:36.19#ibcon#enter wrdev, iclass 12, count 0 2006.173.19:02:36.19#ibcon#first serial, iclass 12, count 0 2006.173.19:02:36.19#ibcon#enter sib2, iclass 12, count 0 2006.173.19:02:36.19#ibcon#flushed, iclass 12, count 0 2006.173.19:02:36.19#ibcon#about to write, iclass 12, count 0 2006.173.19:02:36.19#ibcon#wrote, iclass 12, count 0 2006.173.19:02:36.19#ibcon#about to read 3, iclass 12, count 0 2006.173.19:02:36.21#ibcon#read 3, iclass 12, count 0 2006.173.19:02:36.21#ibcon#about to read 4, iclass 12, count 0 2006.173.19:02:36.21#ibcon#read 4, iclass 12, count 0 2006.173.19:02:36.21#ibcon#about to read 5, iclass 12, count 0 2006.173.19:02:36.21#ibcon#read 5, iclass 12, count 0 2006.173.19:02:36.21#ibcon#about to read 6, iclass 12, count 0 2006.173.19:02:36.21#ibcon#read 6, iclass 12, count 0 2006.173.19:02:36.21#ibcon#end of sib2, iclass 12, count 0 2006.173.19:02:36.21#ibcon#*mode == 0, iclass 12, count 0 2006.173.19:02:36.21#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.19:02:36.21#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.19:02:36.21#ibcon#*before write, iclass 12, count 0 2006.173.19:02:36.21#ibcon#enter sib2, iclass 12, count 0 2006.173.19:02:36.21#ibcon#flushed, iclass 12, count 0 2006.173.19:02:36.21#ibcon#about to write, iclass 12, count 0 2006.173.19:02:36.21#ibcon#wrote, iclass 12, count 0 2006.173.19:02:36.21#ibcon#about to read 3, iclass 12, count 0 2006.173.19:02:36.25#ibcon#read 3, iclass 12, count 0 2006.173.19:02:36.25#ibcon#about to read 4, iclass 12, count 0 2006.173.19:02:36.25#ibcon#read 4, iclass 12, count 0 2006.173.19:02:36.25#ibcon#about to read 5, iclass 12, count 0 2006.173.19:02:36.25#ibcon#read 5, iclass 12, count 0 2006.173.19:02:36.25#ibcon#about to read 6, iclass 12, count 0 2006.173.19:02:36.25#ibcon#read 6, iclass 12, count 0 2006.173.19:02:36.25#ibcon#end of sib2, iclass 12, count 0 2006.173.19:02:36.25#ibcon#*after write, iclass 12, count 0 2006.173.19:02:36.25#ibcon#*before return 0, iclass 12, count 0 2006.173.19:02:36.25#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.19:02:36.25#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.19:02:36.25#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.19:02:36.25#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.19:02:36.25$vck44/vb=5,4 2006.173.19:02:36.25#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.19:02:36.25#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.19:02:36.25#ibcon#ireg 11 cls_cnt 2 2006.173.19:02:36.25#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.19:02:36.31#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.19:02:36.31#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.19:02:36.31#ibcon#enter wrdev, iclass 14, count 2 2006.173.19:02:36.31#ibcon#first serial, iclass 14, count 2 2006.173.19:02:36.31#ibcon#enter sib2, iclass 14, count 2 2006.173.19:02:36.31#ibcon#flushed, iclass 14, count 2 2006.173.19:02:36.31#ibcon#about to write, iclass 14, count 2 2006.173.19:02:36.31#ibcon#wrote, iclass 14, count 2 2006.173.19:02:36.31#ibcon#about to read 3, iclass 14, count 2 2006.173.19:02:36.33#ibcon#read 3, iclass 14, count 2 2006.173.19:02:36.33#ibcon#about to read 4, iclass 14, count 2 2006.173.19:02:36.33#ibcon#read 4, iclass 14, count 2 2006.173.19:02:36.33#ibcon#about to read 5, iclass 14, count 2 2006.173.19:02:36.33#ibcon#read 5, iclass 14, count 2 2006.173.19:02:36.33#ibcon#about to read 6, iclass 14, count 2 2006.173.19:02:36.33#ibcon#read 6, iclass 14, count 2 2006.173.19:02:36.33#ibcon#end of sib2, iclass 14, count 2 2006.173.19:02:36.33#ibcon#*mode == 0, iclass 14, count 2 2006.173.19:02:36.33#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.19:02:36.33#ibcon#[27=AT05-04\r\n] 2006.173.19:02:36.33#ibcon#*before write, iclass 14, count 2 2006.173.19:02:36.33#ibcon#enter sib2, iclass 14, count 2 2006.173.19:02:36.33#ibcon#flushed, iclass 14, count 2 2006.173.19:02:36.33#ibcon#about to write, iclass 14, count 2 2006.173.19:02:36.33#ibcon#wrote, iclass 14, count 2 2006.173.19:02:36.33#ibcon#about to read 3, iclass 14, count 2 2006.173.19:02:36.36#ibcon#read 3, iclass 14, count 2 2006.173.19:02:36.36#ibcon#about to read 4, iclass 14, count 2 2006.173.19:02:36.36#ibcon#read 4, iclass 14, count 2 2006.173.19:02:36.36#ibcon#about to read 5, iclass 14, count 2 2006.173.19:02:36.36#ibcon#read 5, iclass 14, count 2 2006.173.19:02:36.36#ibcon#about to read 6, iclass 14, count 2 2006.173.19:02:36.36#ibcon#read 6, iclass 14, count 2 2006.173.19:02:36.36#ibcon#end of sib2, iclass 14, count 2 2006.173.19:02:36.36#ibcon#*after write, iclass 14, count 2 2006.173.19:02:36.36#ibcon#*before return 0, iclass 14, count 2 2006.173.19:02:36.36#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.19:02:36.36#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.19:02:36.36#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.19:02:36.36#ibcon#ireg 7 cls_cnt 0 2006.173.19:02:36.36#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.19:02:36.48#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.19:02:36.48#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.19:02:36.48#ibcon#enter wrdev, iclass 14, count 0 2006.173.19:02:36.48#ibcon#first serial, iclass 14, count 0 2006.173.19:02:36.48#ibcon#enter sib2, iclass 14, count 0 2006.173.19:02:36.48#ibcon#flushed, iclass 14, count 0 2006.173.19:02:36.48#ibcon#about to write, iclass 14, count 0 2006.173.19:02:36.48#ibcon#wrote, iclass 14, count 0 2006.173.19:02:36.48#ibcon#about to read 3, iclass 14, count 0 2006.173.19:02:36.50#ibcon#read 3, iclass 14, count 0 2006.173.19:02:36.50#ibcon#about to read 4, iclass 14, count 0 2006.173.19:02:36.50#ibcon#read 4, iclass 14, count 0 2006.173.19:02:36.50#ibcon#about to read 5, iclass 14, count 0 2006.173.19:02:36.50#ibcon#read 5, iclass 14, count 0 2006.173.19:02:36.50#ibcon#about to read 6, iclass 14, count 0 2006.173.19:02:36.50#ibcon#read 6, iclass 14, count 0 2006.173.19:02:36.50#ibcon#end of sib2, iclass 14, count 0 2006.173.19:02:36.50#ibcon#*mode == 0, iclass 14, count 0 2006.173.19:02:36.50#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.19:02:36.50#ibcon#[27=USB\r\n] 2006.173.19:02:36.50#ibcon#*before write, iclass 14, count 0 2006.173.19:02:36.50#ibcon#enter sib2, iclass 14, count 0 2006.173.19:02:36.50#ibcon#flushed, iclass 14, count 0 2006.173.19:02:36.50#ibcon#about to write, iclass 14, count 0 2006.173.19:02:36.50#ibcon#wrote, iclass 14, count 0 2006.173.19:02:36.50#ibcon#about to read 3, iclass 14, count 0 2006.173.19:02:36.53#ibcon#read 3, iclass 14, count 0 2006.173.19:02:36.53#ibcon#about to read 4, iclass 14, count 0 2006.173.19:02:36.53#ibcon#read 4, iclass 14, count 0 2006.173.19:02:36.53#ibcon#about to read 5, iclass 14, count 0 2006.173.19:02:36.53#ibcon#read 5, iclass 14, count 0 2006.173.19:02:36.53#ibcon#about to read 6, iclass 14, count 0 2006.173.19:02:36.53#ibcon#read 6, iclass 14, count 0 2006.173.19:02:36.53#ibcon#end of sib2, iclass 14, count 0 2006.173.19:02:36.53#ibcon#*after write, iclass 14, count 0 2006.173.19:02:36.53#ibcon#*before return 0, iclass 14, count 0 2006.173.19:02:36.53#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.19:02:36.53#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.19:02:36.53#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.19:02:36.53#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.19:02:36.53$vck44/vblo=6,719.99 2006.173.19:02:36.53#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.19:02:36.53#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.19:02:36.53#ibcon#ireg 17 cls_cnt 0 2006.173.19:02:36.53#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.19:02:36.53#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.19:02:36.53#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.19:02:36.53#ibcon#enter wrdev, iclass 16, count 0 2006.173.19:02:36.53#ibcon#first serial, iclass 16, count 0 2006.173.19:02:36.53#ibcon#enter sib2, iclass 16, count 0 2006.173.19:02:36.53#ibcon#flushed, iclass 16, count 0 2006.173.19:02:36.53#ibcon#about to write, iclass 16, count 0 2006.173.19:02:36.53#ibcon#wrote, iclass 16, count 0 2006.173.19:02:36.53#ibcon#about to read 3, iclass 16, count 0 2006.173.19:02:36.55#ibcon#read 3, iclass 16, count 0 2006.173.19:02:36.55#ibcon#about to read 4, iclass 16, count 0 2006.173.19:02:36.55#ibcon#read 4, iclass 16, count 0 2006.173.19:02:36.55#ibcon#about to read 5, iclass 16, count 0 2006.173.19:02:36.55#ibcon#read 5, iclass 16, count 0 2006.173.19:02:36.55#ibcon#about to read 6, iclass 16, count 0 2006.173.19:02:36.55#ibcon#read 6, iclass 16, count 0 2006.173.19:02:36.55#ibcon#end of sib2, iclass 16, count 0 2006.173.19:02:36.55#ibcon#*mode == 0, iclass 16, count 0 2006.173.19:02:36.55#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.19:02:36.55#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.19:02:36.55#ibcon#*before write, iclass 16, count 0 2006.173.19:02:36.55#ibcon#enter sib2, iclass 16, count 0 2006.173.19:02:36.55#ibcon#flushed, iclass 16, count 0 2006.173.19:02:36.55#ibcon#about to write, iclass 16, count 0 2006.173.19:02:36.55#ibcon#wrote, iclass 16, count 0 2006.173.19:02:36.55#ibcon#about to read 3, iclass 16, count 0 2006.173.19:02:36.59#ibcon#read 3, iclass 16, count 0 2006.173.19:02:36.59#ibcon#about to read 4, iclass 16, count 0 2006.173.19:02:36.59#ibcon#read 4, iclass 16, count 0 2006.173.19:02:36.59#ibcon#about to read 5, iclass 16, count 0 2006.173.19:02:36.59#ibcon#read 5, iclass 16, count 0 2006.173.19:02:36.59#ibcon#about to read 6, iclass 16, count 0 2006.173.19:02:36.59#ibcon#read 6, iclass 16, count 0 2006.173.19:02:36.59#ibcon#end of sib2, iclass 16, count 0 2006.173.19:02:36.59#ibcon#*after write, iclass 16, count 0 2006.173.19:02:36.59#ibcon#*before return 0, iclass 16, count 0 2006.173.19:02:36.59#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.19:02:36.59#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.19:02:36.59#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.19:02:36.59#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.19:02:36.59$vck44/vb=6,4 2006.173.19:02:36.59#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.19:02:36.59#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.19:02:36.59#ibcon#ireg 11 cls_cnt 2 2006.173.19:02:36.59#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.19:02:36.65#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.19:02:36.65#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.19:02:36.65#ibcon#enter wrdev, iclass 18, count 2 2006.173.19:02:36.65#ibcon#first serial, iclass 18, count 2 2006.173.19:02:36.65#ibcon#enter sib2, iclass 18, count 2 2006.173.19:02:36.65#ibcon#flushed, iclass 18, count 2 2006.173.19:02:36.65#ibcon#about to write, iclass 18, count 2 2006.173.19:02:36.65#ibcon#wrote, iclass 18, count 2 2006.173.19:02:36.65#ibcon#about to read 3, iclass 18, count 2 2006.173.19:02:36.67#ibcon#read 3, iclass 18, count 2 2006.173.19:02:36.67#ibcon#about to read 4, iclass 18, count 2 2006.173.19:02:36.67#ibcon#read 4, iclass 18, count 2 2006.173.19:02:36.67#ibcon#about to read 5, iclass 18, count 2 2006.173.19:02:36.67#ibcon#read 5, iclass 18, count 2 2006.173.19:02:36.67#ibcon#about to read 6, iclass 18, count 2 2006.173.19:02:36.67#ibcon#read 6, iclass 18, count 2 2006.173.19:02:36.67#ibcon#end of sib2, iclass 18, count 2 2006.173.19:02:36.67#ibcon#*mode == 0, iclass 18, count 2 2006.173.19:02:36.67#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.19:02:36.67#ibcon#[27=AT06-04\r\n] 2006.173.19:02:36.67#ibcon#*before write, iclass 18, count 2 2006.173.19:02:36.67#ibcon#enter sib2, iclass 18, count 2 2006.173.19:02:36.67#ibcon#flushed, iclass 18, count 2 2006.173.19:02:36.67#ibcon#about to write, iclass 18, count 2 2006.173.19:02:36.67#ibcon#wrote, iclass 18, count 2 2006.173.19:02:36.67#ibcon#about to read 3, iclass 18, count 2 2006.173.19:02:36.70#ibcon#read 3, iclass 18, count 2 2006.173.19:02:36.70#ibcon#about to read 4, iclass 18, count 2 2006.173.19:02:36.70#ibcon#read 4, iclass 18, count 2 2006.173.19:02:36.70#ibcon#about to read 5, iclass 18, count 2 2006.173.19:02:36.70#ibcon#read 5, iclass 18, count 2 2006.173.19:02:36.70#ibcon#about to read 6, iclass 18, count 2 2006.173.19:02:36.70#ibcon#read 6, iclass 18, count 2 2006.173.19:02:36.70#ibcon#end of sib2, iclass 18, count 2 2006.173.19:02:36.70#ibcon#*after write, iclass 18, count 2 2006.173.19:02:36.70#ibcon#*before return 0, iclass 18, count 2 2006.173.19:02:36.70#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.19:02:36.70#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.19:02:36.70#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.19:02:36.70#ibcon#ireg 7 cls_cnt 0 2006.173.19:02:36.70#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.19:02:36.82#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.19:02:36.82#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.19:02:36.82#ibcon#enter wrdev, iclass 18, count 0 2006.173.19:02:36.82#ibcon#first serial, iclass 18, count 0 2006.173.19:02:36.82#ibcon#enter sib2, iclass 18, count 0 2006.173.19:02:36.82#ibcon#flushed, iclass 18, count 0 2006.173.19:02:36.82#ibcon#about to write, iclass 18, count 0 2006.173.19:02:36.82#ibcon#wrote, iclass 18, count 0 2006.173.19:02:36.82#ibcon#about to read 3, iclass 18, count 0 2006.173.19:02:36.84#ibcon#read 3, iclass 18, count 0 2006.173.19:02:36.84#ibcon#about to read 4, iclass 18, count 0 2006.173.19:02:36.84#ibcon#read 4, iclass 18, count 0 2006.173.19:02:36.84#ibcon#about to read 5, iclass 18, count 0 2006.173.19:02:36.84#ibcon#read 5, iclass 18, count 0 2006.173.19:02:36.84#ibcon#about to read 6, iclass 18, count 0 2006.173.19:02:36.84#ibcon#read 6, iclass 18, count 0 2006.173.19:02:36.84#ibcon#end of sib2, iclass 18, count 0 2006.173.19:02:36.84#ibcon#*mode == 0, iclass 18, count 0 2006.173.19:02:36.84#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.19:02:36.84#ibcon#[27=USB\r\n] 2006.173.19:02:36.84#ibcon#*before write, iclass 18, count 0 2006.173.19:02:36.84#ibcon#enter sib2, iclass 18, count 0 2006.173.19:02:36.84#ibcon#flushed, iclass 18, count 0 2006.173.19:02:36.84#ibcon#about to write, iclass 18, count 0 2006.173.19:02:36.84#ibcon#wrote, iclass 18, count 0 2006.173.19:02:36.84#ibcon#about to read 3, iclass 18, count 0 2006.173.19:02:36.87#ibcon#read 3, iclass 18, count 0 2006.173.19:02:36.87#ibcon#about to read 4, iclass 18, count 0 2006.173.19:02:36.87#ibcon#read 4, iclass 18, count 0 2006.173.19:02:36.87#ibcon#about to read 5, iclass 18, count 0 2006.173.19:02:36.87#ibcon#read 5, iclass 18, count 0 2006.173.19:02:36.87#ibcon#about to read 6, iclass 18, count 0 2006.173.19:02:36.87#ibcon#read 6, iclass 18, count 0 2006.173.19:02:36.87#ibcon#end of sib2, iclass 18, count 0 2006.173.19:02:36.87#ibcon#*after write, iclass 18, count 0 2006.173.19:02:36.87#ibcon#*before return 0, iclass 18, count 0 2006.173.19:02:36.87#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.19:02:36.87#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.19:02:36.87#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.19:02:36.87#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.19:02:36.87$vck44/vblo=7,734.99 2006.173.19:02:36.87#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.19:02:36.87#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.19:02:36.87#ibcon#ireg 17 cls_cnt 0 2006.173.19:02:36.87#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.19:02:36.87#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.19:02:36.87#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.19:02:36.87#ibcon#enter wrdev, iclass 20, count 0 2006.173.19:02:36.87#ibcon#first serial, iclass 20, count 0 2006.173.19:02:36.87#ibcon#enter sib2, iclass 20, count 0 2006.173.19:02:36.87#ibcon#flushed, iclass 20, count 0 2006.173.19:02:36.87#ibcon#about to write, iclass 20, count 0 2006.173.19:02:36.87#ibcon#wrote, iclass 20, count 0 2006.173.19:02:36.87#ibcon#about to read 3, iclass 20, count 0 2006.173.19:02:36.89#ibcon#read 3, iclass 20, count 0 2006.173.19:02:36.89#ibcon#about to read 4, iclass 20, count 0 2006.173.19:02:36.89#ibcon#read 4, iclass 20, count 0 2006.173.19:02:36.89#ibcon#about to read 5, iclass 20, count 0 2006.173.19:02:36.89#ibcon#read 5, iclass 20, count 0 2006.173.19:02:36.89#ibcon#about to read 6, iclass 20, count 0 2006.173.19:02:36.89#ibcon#read 6, iclass 20, count 0 2006.173.19:02:36.89#ibcon#end of sib2, iclass 20, count 0 2006.173.19:02:36.89#ibcon#*mode == 0, iclass 20, count 0 2006.173.19:02:36.89#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.19:02:36.89#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.19:02:36.89#ibcon#*before write, iclass 20, count 0 2006.173.19:02:36.89#ibcon#enter sib2, iclass 20, count 0 2006.173.19:02:36.89#ibcon#flushed, iclass 20, count 0 2006.173.19:02:36.89#ibcon#about to write, iclass 20, count 0 2006.173.19:02:36.89#ibcon#wrote, iclass 20, count 0 2006.173.19:02:36.89#ibcon#about to read 3, iclass 20, count 0 2006.173.19:02:36.93#ibcon#read 3, iclass 20, count 0 2006.173.19:02:36.93#ibcon#about to read 4, iclass 20, count 0 2006.173.19:02:36.93#ibcon#read 4, iclass 20, count 0 2006.173.19:02:36.93#ibcon#about to read 5, iclass 20, count 0 2006.173.19:02:36.93#ibcon#read 5, iclass 20, count 0 2006.173.19:02:36.93#ibcon#about to read 6, iclass 20, count 0 2006.173.19:02:36.93#ibcon#read 6, iclass 20, count 0 2006.173.19:02:36.93#ibcon#end of sib2, iclass 20, count 0 2006.173.19:02:36.93#ibcon#*after write, iclass 20, count 0 2006.173.19:02:36.93#ibcon#*before return 0, iclass 20, count 0 2006.173.19:02:36.93#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.19:02:36.93#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.19:02:36.93#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.19:02:36.93#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.19:02:36.93$vck44/vb=7,4 2006.173.19:02:36.93#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.19:02:36.93#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.19:02:36.93#ibcon#ireg 11 cls_cnt 2 2006.173.19:02:36.93#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.19:02:36.99#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.19:02:36.99#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.19:02:36.99#ibcon#enter wrdev, iclass 22, count 2 2006.173.19:02:36.99#ibcon#first serial, iclass 22, count 2 2006.173.19:02:36.99#ibcon#enter sib2, iclass 22, count 2 2006.173.19:02:36.99#ibcon#flushed, iclass 22, count 2 2006.173.19:02:36.99#ibcon#about to write, iclass 22, count 2 2006.173.19:02:36.99#ibcon#wrote, iclass 22, count 2 2006.173.19:02:36.99#ibcon#about to read 3, iclass 22, count 2 2006.173.19:02:37.01#ibcon#read 3, iclass 22, count 2 2006.173.19:02:37.01#ibcon#about to read 4, iclass 22, count 2 2006.173.19:02:37.01#ibcon#read 4, iclass 22, count 2 2006.173.19:02:37.01#ibcon#about to read 5, iclass 22, count 2 2006.173.19:02:37.01#ibcon#read 5, iclass 22, count 2 2006.173.19:02:37.01#ibcon#about to read 6, iclass 22, count 2 2006.173.19:02:37.01#ibcon#read 6, iclass 22, count 2 2006.173.19:02:37.01#ibcon#end of sib2, iclass 22, count 2 2006.173.19:02:37.01#ibcon#*mode == 0, iclass 22, count 2 2006.173.19:02:37.01#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.19:02:37.01#ibcon#[27=AT07-04\r\n] 2006.173.19:02:37.01#ibcon#*before write, iclass 22, count 2 2006.173.19:02:37.01#ibcon#enter sib2, iclass 22, count 2 2006.173.19:02:37.01#ibcon#flushed, iclass 22, count 2 2006.173.19:02:37.01#ibcon#about to write, iclass 22, count 2 2006.173.19:02:37.01#ibcon#wrote, iclass 22, count 2 2006.173.19:02:37.01#ibcon#about to read 3, iclass 22, count 2 2006.173.19:02:37.04#ibcon#read 3, iclass 22, count 2 2006.173.19:02:37.04#ibcon#about to read 4, iclass 22, count 2 2006.173.19:02:37.04#ibcon#read 4, iclass 22, count 2 2006.173.19:02:37.04#ibcon#about to read 5, iclass 22, count 2 2006.173.19:02:37.04#ibcon#read 5, iclass 22, count 2 2006.173.19:02:37.04#ibcon#about to read 6, iclass 22, count 2 2006.173.19:02:37.04#ibcon#read 6, iclass 22, count 2 2006.173.19:02:37.04#ibcon#end of sib2, iclass 22, count 2 2006.173.19:02:37.04#ibcon#*after write, iclass 22, count 2 2006.173.19:02:37.04#ibcon#*before return 0, iclass 22, count 2 2006.173.19:02:37.04#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.19:02:37.04#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.19:02:37.04#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.19:02:37.04#ibcon#ireg 7 cls_cnt 0 2006.173.19:02:37.04#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.19:02:37.16#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.19:02:37.16#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.19:02:37.16#ibcon#enter wrdev, iclass 22, count 0 2006.173.19:02:37.16#ibcon#first serial, iclass 22, count 0 2006.173.19:02:37.16#ibcon#enter sib2, iclass 22, count 0 2006.173.19:02:37.16#ibcon#flushed, iclass 22, count 0 2006.173.19:02:37.16#ibcon#about to write, iclass 22, count 0 2006.173.19:02:37.16#ibcon#wrote, iclass 22, count 0 2006.173.19:02:37.16#ibcon#about to read 3, iclass 22, count 0 2006.173.19:02:37.18#ibcon#read 3, iclass 22, count 0 2006.173.19:02:37.18#ibcon#about to read 4, iclass 22, count 0 2006.173.19:02:37.18#ibcon#read 4, iclass 22, count 0 2006.173.19:02:37.18#ibcon#about to read 5, iclass 22, count 0 2006.173.19:02:37.18#ibcon#read 5, iclass 22, count 0 2006.173.19:02:37.18#ibcon#about to read 6, iclass 22, count 0 2006.173.19:02:37.18#ibcon#read 6, iclass 22, count 0 2006.173.19:02:37.18#ibcon#end of sib2, iclass 22, count 0 2006.173.19:02:37.18#ibcon#*mode == 0, iclass 22, count 0 2006.173.19:02:37.18#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.19:02:37.18#ibcon#[27=USB\r\n] 2006.173.19:02:37.18#ibcon#*before write, iclass 22, count 0 2006.173.19:02:37.18#ibcon#enter sib2, iclass 22, count 0 2006.173.19:02:37.18#ibcon#flushed, iclass 22, count 0 2006.173.19:02:37.18#ibcon#about to write, iclass 22, count 0 2006.173.19:02:37.18#ibcon#wrote, iclass 22, count 0 2006.173.19:02:37.18#ibcon#about to read 3, iclass 22, count 0 2006.173.19:02:37.21#ibcon#read 3, iclass 22, count 0 2006.173.19:02:37.21#ibcon#about to read 4, iclass 22, count 0 2006.173.19:02:37.21#ibcon#read 4, iclass 22, count 0 2006.173.19:02:37.21#ibcon#about to read 5, iclass 22, count 0 2006.173.19:02:37.21#ibcon#read 5, iclass 22, count 0 2006.173.19:02:37.21#ibcon#about to read 6, iclass 22, count 0 2006.173.19:02:37.21#ibcon#read 6, iclass 22, count 0 2006.173.19:02:37.21#ibcon#end of sib2, iclass 22, count 0 2006.173.19:02:37.21#ibcon#*after write, iclass 22, count 0 2006.173.19:02:37.21#ibcon#*before return 0, iclass 22, count 0 2006.173.19:02:37.21#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.19:02:37.21#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.19:02:37.21#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.19:02:37.21#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.19:02:37.21$vck44/vblo=8,744.99 2006.173.19:02:37.21#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.19:02:37.21#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.19:02:37.21#ibcon#ireg 17 cls_cnt 0 2006.173.19:02:37.21#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.19:02:37.21#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.19:02:37.21#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.19:02:37.21#ibcon#enter wrdev, iclass 24, count 0 2006.173.19:02:37.21#ibcon#first serial, iclass 24, count 0 2006.173.19:02:37.21#ibcon#enter sib2, iclass 24, count 0 2006.173.19:02:37.21#ibcon#flushed, iclass 24, count 0 2006.173.19:02:37.21#ibcon#about to write, iclass 24, count 0 2006.173.19:02:37.21#ibcon#wrote, iclass 24, count 0 2006.173.19:02:37.21#ibcon#about to read 3, iclass 24, count 0 2006.173.19:02:37.23#ibcon#read 3, iclass 24, count 0 2006.173.19:02:37.23#ibcon#about to read 4, iclass 24, count 0 2006.173.19:02:37.23#ibcon#read 4, iclass 24, count 0 2006.173.19:02:37.23#ibcon#about to read 5, iclass 24, count 0 2006.173.19:02:37.23#ibcon#read 5, iclass 24, count 0 2006.173.19:02:37.23#ibcon#about to read 6, iclass 24, count 0 2006.173.19:02:37.23#ibcon#read 6, iclass 24, count 0 2006.173.19:02:37.23#ibcon#end of sib2, iclass 24, count 0 2006.173.19:02:37.23#ibcon#*mode == 0, iclass 24, count 0 2006.173.19:02:37.23#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.19:02:37.23#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.19:02:37.23#ibcon#*before write, iclass 24, count 0 2006.173.19:02:37.23#ibcon#enter sib2, iclass 24, count 0 2006.173.19:02:37.23#ibcon#flushed, iclass 24, count 0 2006.173.19:02:37.23#ibcon#about to write, iclass 24, count 0 2006.173.19:02:37.23#ibcon#wrote, iclass 24, count 0 2006.173.19:02:37.23#ibcon#about to read 3, iclass 24, count 0 2006.173.19:02:37.27#ibcon#read 3, iclass 24, count 0 2006.173.19:02:37.27#ibcon#about to read 4, iclass 24, count 0 2006.173.19:02:37.27#ibcon#read 4, iclass 24, count 0 2006.173.19:02:37.27#ibcon#about to read 5, iclass 24, count 0 2006.173.19:02:37.27#ibcon#read 5, iclass 24, count 0 2006.173.19:02:37.27#ibcon#about to read 6, iclass 24, count 0 2006.173.19:02:37.27#ibcon#read 6, iclass 24, count 0 2006.173.19:02:37.27#ibcon#end of sib2, iclass 24, count 0 2006.173.19:02:37.27#ibcon#*after write, iclass 24, count 0 2006.173.19:02:37.27#ibcon#*before return 0, iclass 24, count 0 2006.173.19:02:37.27#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.19:02:37.27#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.19:02:37.27#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.19:02:37.27#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.19:02:37.27$vck44/vb=8,4 2006.173.19:02:37.27#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.19:02:37.27#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.19:02:37.27#ibcon#ireg 11 cls_cnt 2 2006.173.19:02:37.27#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.19:02:37.33#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.19:02:37.33#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.19:02:37.33#ibcon#enter wrdev, iclass 26, count 2 2006.173.19:02:37.33#ibcon#first serial, iclass 26, count 2 2006.173.19:02:37.33#ibcon#enter sib2, iclass 26, count 2 2006.173.19:02:37.33#ibcon#flushed, iclass 26, count 2 2006.173.19:02:37.33#ibcon#about to write, iclass 26, count 2 2006.173.19:02:37.33#ibcon#wrote, iclass 26, count 2 2006.173.19:02:37.33#ibcon#about to read 3, iclass 26, count 2 2006.173.19:02:37.35#ibcon#read 3, iclass 26, count 2 2006.173.19:02:37.35#ibcon#about to read 4, iclass 26, count 2 2006.173.19:02:37.35#ibcon#read 4, iclass 26, count 2 2006.173.19:02:37.35#ibcon#about to read 5, iclass 26, count 2 2006.173.19:02:37.35#ibcon#read 5, iclass 26, count 2 2006.173.19:02:37.35#ibcon#about to read 6, iclass 26, count 2 2006.173.19:02:37.35#ibcon#read 6, iclass 26, count 2 2006.173.19:02:37.35#ibcon#end of sib2, iclass 26, count 2 2006.173.19:02:37.35#ibcon#*mode == 0, iclass 26, count 2 2006.173.19:02:37.35#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.19:02:37.35#ibcon#[27=AT08-04\r\n] 2006.173.19:02:37.35#ibcon#*before write, iclass 26, count 2 2006.173.19:02:37.35#ibcon#enter sib2, iclass 26, count 2 2006.173.19:02:37.35#ibcon#flushed, iclass 26, count 2 2006.173.19:02:37.35#ibcon#about to write, iclass 26, count 2 2006.173.19:02:37.35#ibcon#wrote, iclass 26, count 2 2006.173.19:02:37.35#ibcon#about to read 3, iclass 26, count 2 2006.173.19:02:37.38#ibcon#read 3, iclass 26, count 2 2006.173.19:02:37.38#ibcon#about to read 4, iclass 26, count 2 2006.173.19:02:37.38#ibcon#read 4, iclass 26, count 2 2006.173.19:02:37.38#ibcon#about to read 5, iclass 26, count 2 2006.173.19:02:37.38#ibcon#read 5, iclass 26, count 2 2006.173.19:02:37.38#ibcon#about to read 6, iclass 26, count 2 2006.173.19:02:37.38#ibcon#read 6, iclass 26, count 2 2006.173.19:02:37.38#ibcon#end of sib2, iclass 26, count 2 2006.173.19:02:37.38#ibcon#*after write, iclass 26, count 2 2006.173.19:02:37.38#ibcon#*before return 0, iclass 26, count 2 2006.173.19:02:37.38#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.19:02:37.38#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.19:02:37.38#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.19:02:37.38#ibcon#ireg 7 cls_cnt 0 2006.173.19:02:37.38#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.19:02:37.50#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.19:02:37.50#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.19:02:37.50#ibcon#enter wrdev, iclass 26, count 0 2006.173.19:02:37.50#ibcon#first serial, iclass 26, count 0 2006.173.19:02:37.50#ibcon#enter sib2, iclass 26, count 0 2006.173.19:02:37.50#ibcon#flushed, iclass 26, count 0 2006.173.19:02:37.50#ibcon#about to write, iclass 26, count 0 2006.173.19:02:37.50#ibcon#wrote, iclass 26, count 0 2006.173.19:02:37.50#ibcon#about to read 3, iclass 26, count 0 2006.173.19:02:37.52#ibcon#read 3, iclass 26, count 0 2006.173.19:02:37.52#ibcon#about to read 4, iclass 26, count 0 2006.173.19:02:37.52#ibcon#read 4, iclass 26, count 0 2006.173.19:02:37.52#ibcon#about to read 5, iclass 26, count 0 2006.173.19:02:37.52#ibcon#read 5, iclass 26, count 0 2006.173.19:02:37.52#ibcon#about to read 6, iclass 26, count 0 2006.173.19:02:37.52#ibcon#read 6, iclass 26, count 0 2006.173.19:02:37.52#ibcon#end of sib2, iclass 26, count 0 2006.173.19:02:37.52#ibcon#*mode == 0, iclass 26, count 0 2006.173.19:02:37.52#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.19:02:37.52#ibcon#[27=USB\r\n] 2006.173.19:02:37.52#ibcon#*before write, iclass 26, count 0 2006.173.19:02:37.52#ibcon#enter sib2, iclass 26, count 0 2006.173.19:02:37.52#ibcon#flushed, iclass 26, count 0 2006.173.19:02:37.52#ibcon#about to write, iclass 26, count 0 2006.173.19:02:37.52#ibcon#wrote, iclass 26, count 0 2006.173.19:02:37.52#ibcon#about to read 3, iclass 26, count 0 2006.173.19:02:37.55#ibcon#read 3, iclass 26, count 0 2006.173.19:02:37.55#ibcon#about to read 4, iclass 26, count 0 2006.173.19:02:37.55#ibcon#read 4, iclass 26, count 0 2006.173.19:02:37.55#ibcon#about to read 5, iclass 26, count 0 2006.173.19:02:37.55#ibcon#read 5, iclass 26, count 0 2006.173.19:02:37.55#ibcon#about to read 6, iclass 26, count 0 2006.173.19:02:37.55#ibcon#read 6, iclass 26, count 0 2006.173.19:02:37.55#ibcon#end of sib2, iclass 26, count 0 2006.173.19:02:37.55#ibcon#*after write, iclass 26, count 0 2006.173.19:02:37.55#ibcon#*before return 0, iclass 26, count 0 2006.173.19:02:37.55#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.19:02:37.55#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.19:02:37.55#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.19:02:37.55#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.19:02:37.55$vck44/vabw=wide 2006.173.19:02:37.55#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.19:02:37.55#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.19:02:37.55#ibcon#ireg 8 cls_cnt 0 2006.173.19:02:37.55#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.19:02:37.55#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.19:02:37.55#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.19:02:37.55#ibcon#enter wrdev, iclass 28, count 0 2006.173.19:02:37.55#ibcon#first serial, iclass 28, count 0 2006.173.19:02:37.55#ibcon#enter sib2, iclass 28, count 0 2006.173.19:02:37.55#ibcon#flushed, iclass 28, count 0 2006.173.19:02:37.55#ibcon#about to write, iclass 28, count 0 2006.173.19:02:37.55#ibcon#wrote, iclass 28, count 0 2006.173.19:02:37.55#ibcon#about to read 3, iclass 28, count 0 2006.173.19:02:37.57#ibcon#read 3, iclass 28, count 0 2006.173.19:02:37.57#ibcon#about to read 4, iclass 28, count 0 2006.173.19:02:37.57#ibcon#read 4, iclass 28, count 0 2006.173.19:02:37.57#ibcon#about to read 5, iclass 28, count 0 2006.173.19:02:37.57#ibcon#read 5, iclass 28, count 0 2006.173.19:02:37.57#ibcon#about to read 6, iclass 28, count 0 2006.173.19:02:37.57#ibcon#read 6, iclass 28, count 0 2006.173.19:02:37.57#ibcon#end of sib2, iclass 28, count 0 2006.173.19:02:37.57#ibcon#*mode == 0, iclass 28, count 0 2006.173.19:02:37.57#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.19:02:37.57#ibcon#[25=BW32\r\n] 2006.173.19:02:37.57#ibcon#*before write, iclass 28, count 0 2006.173.19:02:37.57#ibcon#enter sib2, iclass 28, count 0 2006.173.19:02:37.57#ibcon#flushed, iclass 28, count 0 2006.173.19:02:37.57#ibcon#about to write, iclass 28, count 0 2006.173.19:02:37.57#ibcon#wrote, iclass 28, count 0 2006.173.19:02:37.57#ibcon#about to read 3, iclass 28, count 0 2006.173.19:02:37.60#ibcon#read 3, iclass 28, count 0 2006.173.19:02:37.60#ibcon#about to read 4, iclass 28, count 0 2006.173.19:02:37.60#ibcon#read 4, iclass 28, count 0 2006.173.19:02:37.60#ibcon#about to read 5, iclass 28, count 0 2006.173.19:02:37.60#ibcon#read 5, iclass 28, count 0 2006.173.19:02:37.60#ibcon#about to read 6, iclass 28, count 0 2006.173.19:02:37.60#ibcon#read 6, iclass 28, count 0 2006.173.19:02:37.60#ibcon#end of sib2, iclass 28, count 0 2006.173.19:02:37.60#ibcon#*after write, iclass 28, count 0 2006.173.19:02:37.60#ibcon#*before return 0, iclass 28, count 0 2006.173.19:02:37.60#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.19:02:37.60#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.19:02:37.60#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.19:02:37.60#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.19:02:37.60$vck44/vbbw=wide 2006.173.19:02:37.60#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.19:02:37.60#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.19:02:37.60#ibcon#ireg 8 cls_cnt 0 2006.173.19:02:37.60#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.19:02:37.67#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.19:02:37.67#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.19:02:37.67#ibcon#enter wrdev, iclass 30, count 0 2006.173.19:02:37.67#ibcon#first serial, iclass 30, count 0 2006.173.19:02:37.67#ibcon#enter sib2, iclass 30, count 0 2006.173.19:02:37.67#ibcon#flushed, iclass 30, count 0 2006.173.19:02:37.67#ibcon#about to write, iclass 30, count 0 2006.173.19:02:37.67#ibcon#wrote, iclass 30, count 0 2006.173.19:02:37.67#ibcon#about to read 3, iclass 30, count 0 2006.173.19:02:37.69#ibcon#read 3, iclass 30, count 0 2006.173.19:02:37.69#ibcon#about to read 4, iclass 30, count 0 2006.173.19:02:37.69#ibcon#read 4, iclass 30, count 0 2006.173.19:02:37.69#ibcon#about to read 5, iclass 30, count 0 2006.173.19:02:37.69#ibcon#read 5, iclass 30, count 0 2006.173.19:02:37.69#ibcon#about to read 6, iclass 30, count 0 2006.173.19:02:37.69#ibcon#read 6, iclass 30, count 0 2006.173.19:02:37.69#ibcon#end of sib2, iclass 30, count 0 2006.173.19:02:37.69#ibcon#*mode == 0, iclass 30, count 0 2006.173.19:02:37.69#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.19:02:37.69#ibcon#[27=BW32\r\n] 2006.173.19:02:37.69#ibcon#*before write, iclass 30, count 0 2006.173.19:02:37.69#ibcon#enter sib2, iclass 30, count 0 2006.173.19:02:37.69#ibcon#flushed, iclass 30, count 0 2006.173.19:02:37.69#ibcon#about to write, iclass 30, count 0 2006.173.19:02:37.69#ibcon#wrote, iclass 30, count 0 2006.173.19:02:37.69#ibcon#about to read 3, iclass 30, count 0 2006.173.19:02:37.72#ibcon#read 3, iclass 30, count 0 2006.173.19:02:37.72#ibcon#about to read 4, iclass 30, count 0 2006.173.19:02:37.72#ibcon#read 4, iclass 30, count 0 2006.173.19:02:37.72#ibcon#about to read 5, iclass 30, count 0 2006.173.19:02:37.72#ibcon#read 5, iclass 30, count 0 2006.173.19:02:37.72#ibcon#about to read 6, iclass 30, count 0 2006.173.19:02:37.72#ibcon#read 6, iclass 30, count 0 2006.173.19:02:37.72#ibcon#end of sib2, iclass 30, count 0 2006.173.19:02:37.72#ibcon#*after write, iclass 30, count 0 2006.173.19:02:37.72#ibcon#*before return 0, iclass 30, count 0 2006.173.19:02:37.72#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.19:02:37.72#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.19:02:37.72#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.19:02:37.72#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.19:02:37.72$setupk4/ifdk4 2006.173.19:02:37.72$ifdk4/lo= 2006.173.19:02:37.72$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.19:02:37.72$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.19:02:37.72$ifdk4/patch= 2006.173.19:02:37.72$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.19:02:37.72$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.19:02:37.72$setupk4/!*+20s 2006.173.19:02:40.34#abcon#<5=/13 0.3 0.8 19.581001002.5\r\n> 2006.173.19:02:40.36#abcon#{5=INTERFACE CLEAR} 2006.173.19:02:40.42#abcon#[5=S1D000X0/0*\r\n] 2006.173.19:02:50.51#abcon#<5=/13 0.3 0.8 19.581001002.5\r\n> 2006.173.19:02:50.53#abcon#{5=INTERFACE CLEAR} 2006.173.19:02:50.59#abcon#[5=S1D000X0/0*\r\n] 2006.173.19:02:51.14#trakl#Source acquired 2006.173.19:02:51.14#flagr#flagr/antenna,acquired 2006.173.19:02:52.23$setupk4/"tpicd 2006.173.19:02:52.23$setupk4/echo=off 2006.173.19:02:52.23$setupk4/xlog=off 2006.173.19:02:52.23:!2006.173.19:02:51 2006.173.19:02:52.23:preob 2006.173.19:02:53.14/onsource/TRACKING 2006.173.19:02:53.14:!2006.173.19:03:01 2006.173.19:03:01.00:"tape 2006.173.19:03:01.00:"st=record 2006.173.19:03:01.00:data_valid=on 2006.173.19:03:01.00:midob 2006.173.19:03:02.14/onsource/TRACKING 2006.173.19:03:02.14/wx/19.58,1002.5,100 2006.173.19:03:02.24/cable/+6.5147E-03 2006.173.19:03:03.33/va/01,07,usb,yes,35,37 2006.173.19:03:03.33/va/02,06,usb,yes,34,35 2006.173.19:03:03.33/va/03,05,usb,yes,44,46 2006.173.19:03:03.33/va/04,06,usb,yes,35,37 2006.173.19:03:03.33/va/05,04,usb,yes,28,28 2006.173.19:03:03.33/va/06,03,usb,yes,39,39 2006.173.19:03:03.33/va/07,04,usb,yes,31,32 2006.173.19:03:03.33/va/08,04,usb,yes,27,32 2006.173.19:03:03.56/valo/01,524.99,yes,locked 2006.173.19:03:03.56/valo/02,534.99,yes,locked 2006.173.19:03:03.56/valo/03,564.99,yes,locked 2006.173.19:03:03.56/valo/04,624.99,yes,locked 2006.173.19:03:03.56/valo/05,734.99,yes,locked 2006.173.19:03:03.56/valo/06,814.99,yes,locked 2006.173.19:03:03.56/valo/07,864.99,yes,locked 2006.173.19:03:03.56/valo/08,884.99,yes,locked 2006.173.19:03:04.65/vb/01,04,usb,yes,28,26 2006.173.19:03:04.65/vb/02,04,usb,yes,31,31 2006.173.19:03:04.65/vb/03,04,usb,yes,28,31 2006.173.19:03:04.65/vb/04,04,usb,yes,32,31 2006.173.19:03:04.65/vb/05,04,usb,yes,25,27 2006.173.19:03:04.65/vb/06,04,usb,yes,29,25 2006.173.19:03:04.65/vb/07,04,usb,yes,29,29 2006.173.19:03:04.65/vb/08,04,usb,yes,27,30 2006.173.19:03:04.88/vblo/01,629.99,yes,locked 2006.173.19:03:04.88/vblo/02,634.99,yes,locked 2006.173.19:03:04.88/vblo/03,649.99,yes,locked 2006.173.19:03:04.88/vblo/04,679.99,yes,locked 2006.173.19:03:04.88/vblo/05,709.99,yes,locked 2006.173.19:03:04.88/vblo/06,719.99,yes,locked 2006.173.19:03:04.88/vblo/07,734.99,yes,locked 2006.173.19:03:04.88/vblo/08,744.99,yes,locked 2006.173.19:03:05.03/vabw/8 2006.173.19:03:05.18/vbbw/8 2006.173.19:03:05.27/xfe/off,on,15.0 2006.173.19:03:05.67/ifatt/23,28,28,28 2006.173.19:03:06.08/fmout-gps/S +3.87E-07 2006.173.19:03:06.12:!2006.173.19:12:31 2006.173.19:12:31.02:data_valid=off 2006.173.19:12:31.02:"et 2006.173.19:12:31.02:!+3s 2006.173.19:12:34.06:"tape 2006.173.19:12:34.06:postob 2006.173.19:12:34.16/cable/+6.5136E-03 2006.173.19:12:34.16/wx/19.56,1002.5,100 2006.173.19:12:34.22/fmout-gps/S +3.87E-07 2006.173.19:12:34.22:scan_name=173-1917,jd0606,170 2006.173.19:12:34.22:source=3c446,222547.26,-045701.4,2000.0,ccw 2006.173.19:12:35.14#flagr#flagr/antenna,new-source 2006.173.19:12:35.14:checkk5 2006.173.19:12:35.56/chk_autoobs//k5ts1/ autoobs is running! 2006.173.19:12:35.97/chk_autoobs//k5ts2/ autoobs is running! 2006.173.19:12:36.37/chk_autoobs//k5ts3/ autoobs is running! 2006.173.19:12:36.77/chk_autoobs//k5ts4/ autoobs is running! 2006.173.19:12:37.50/chk_obsdata//k5ts1/T1731903??a.dat file size is correct (nominal:2280MB, actual:2276MB). 2006.173.19:12:38.21/chk_obsdata//k5ts2/T1731903??b.dat file size is correct (nominal:2280MB, actual:2276MB). 2006.173.19:12:38.91/chk_obsdata//k5ts3/T1731903??c.dat file size is correct (nominal:2280MB, actual:2276MB). 2006.173.19:12:39.62/chk_obsdata//k5ts4/T1731903??d.dat file size is correct (nominal:2280MB, actual:2276MB). 2006.173.19:12:40.33/k5log//k5ts1_log_newline 2006.173.19:12:41.03/k5log//k5ts2_log_newline 2006.173.19:12:41.73/k5log//k5ts3_log_newline 2006.173.19:12:42.44/k5log//k5ts4_log_newline 2006.173.19:12:42.46/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.19:12:42.46:setupk4=1 2006.173.19:12:42.46$setupk4/echo=on 2006.173.19:12:42.46$setupk4/pcalon 2006.173.19:12:42.46$pcalon/"no phase cal control is implemented here 2006.173.19:12:42.46$setupk4/"tpicd=stop 2006.173.19:12:42.46$setupk4/"rec=synch_on 2006.173.19:12:42.46$setupk4/"rec_mode=128 2006.173.19:12:42.46$setupk4/!* 2006.173.19:12:42.46$setupk4/recpk4 2006.173.19:12:42.46$recpk4/recpatch= 2006.173.19:12:42.47$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.19:12:42.47$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.19:12:42.47$setupk4/vck44 2006.173.19:12:42.47$vck44/valo=1,524.99 2006.173.19:12:42.47#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.19:12:42.47#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.19:12:42.47#ibcon#ireg 17 cls_cnt 0 2006.173.19:12:42.47#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.19:12:42.47#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.19:12:42.47#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.19:12:42.47#ibcon#enter wrdev, iclass 14, count 0 2006.173.19:12:42.47#ibcon#first serial, iclass 14, count 0 2006.173.19:12:42.47#ibcon#enter sib2, iclass 14, count 0 2006.173.19:12:42.47#ibcon#flushed, iclass 14, count 0 2006.173.19:12:42.47#ibcon#about to write, iclass 14, count 0 2006.173.19:12:42.47#ibcon#wrote, iclass 14, count 0 2006.173.19:12:42.47#ibcon#about to read 3, iclass 14, count 0 2006.173.19:12:42.48#ibcon#read 3, iclass 14, count 0 2006.173.19:12:42.48#ibcon#about to read 4, iclass 14, count 0 2006.173.19:12:42.48#ibcon#read 4, iclass 14, count 0 2006.173.19:12:42.48#ibcon#about to read 5, iclass 14, count 0 2006.173.19:12:42.48#ibcon#read 5, iclass 14, count 0 2006.173.19:12:42.48#ibcon#about to read 6, iclass 14, count 0 2006.173.19:12:42.48#ibcon#read 6, iclass 14, count 0 2006.173.19:12:42.48#ibcon#end of sib2, iclass 14, count 0 2006.173.19:12:42.48#ibcon#*mode == 0, iclass 14, count 0 2006.173.19:12:42.48#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.19:12:42.49#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.19:12:42.49#ibcon#*before write, iclass 14, count 0 2006.173.19:12:42.49#ibcon#enter sib2, iclass 14, count 0 2006.173.19:12:42.49#ibcon#flushed, iclass 14, count 0 2006.173.19:12:42.49#ibcon#about to write, iclass 14, count 0 2006.173.19:12:42.49#ibcon#wrote, iclass 14, count 0 2006.173.19:12:42.49#ibcon#about to read 3, iclass 14, count 0 2006.173.19:12:42.53#ibcon#read 3, iclass 14, count 0 2006.173.19:12:42.53#ibcon#about to read 4, iclass 14, count 0 2006.173.19:12:42.53#ibcon#read 4, iclass 14, count 0 2006.173.19:12:42.53#ibcon#about to read 5, iclass 14, count 0 2006.173.19:12:42.53#ibcon#read 5, iclass 14, count 0 2006.173.19:12:42.53#ibcon#about to read 6, iclass 14, count 0 2006.173.19:12:42.53#ibcon#read 6, iclass 14, count 0 2006.173.19:12:42.53#ibcon#end of sib2, iclass 14, count 0 2006.173.19:12:42.53#ibcon#*after write, iclass 14, count 0 2006.173.19:12:42.53#ibcon#*before return 0, iclass 14, count 0 2006.173.19:12:42.54#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.19:12:42.54#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.19:12:42.54#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.19:12:42.54#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.19:12:42.54$vck44/va=1,7 2006.173.19:12:42.54#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.19:12:42.54#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.19:12:42.54#ibcon#ireg 11 cls_cnt 2 2006.173.19:12:42.54#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.19:12:42.54#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.19:12:42.54#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.19:12:42.54#ibcon#enter wrdev, iclass 16, count 2 2006.173.19:12:42.54#ibcon#first serial, iclass 16, count 2 2006.173.19:12:42.54#ibcon#enter sib2, iclass 16, count 2 2006.173.19:12:42.54#ibcon#flushed, iclass 16, count 2 2006.173.19:12:42.54#ibcon#about to write, iclass 16, count 2 2006.173.19:12:42.54#ibcon#wrote, iclass 16, count 2 2006.173.19:12:42.54#ibcon#about to read 3, iclass 16, count 2 2006.173.19:12:42.55#ibcon#read 3, iclass 16, count 2 2006.173.19:12:42.55#ibcon#about to read 4, iclass 16, count 2 2006.173.19:12:42.55#ibcon#read 4, iclass 16, count 2 2006.173.19:12:42.55#ibcon#about to read 5, iclass 16, count 2 2006.173.19:12:42.55#ibcon#read 5, iclass 16, count 2 2006.173.19:12:42.55#ibcon#about to read 6, iclass 16, count 2 2006.173.19:12:42.55#ibcon#read 6, iclass 16, count 2 2006.173.19:12:42.55#ibcon#end of sib2, iclass 16, count 2 2006.173.19:12:42.55#ibcon#*mode == 0, iclass 16, count 2 2006.173.19:12:42.55#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.19:12:42.55#ibcon#[25=AT01-07\r\n] 2006.173.19:12:42.55#ibcon#*before write, iclass 16, count 2 2006.173.19:12:42.56#ibcon#enter sib2, iclass 16, count 2 2006.173.19:12:42.56#ibcon#flushed, iclass 16, count 2 2006.173.19:12:42.56#ibcon#about to write, iclass 16, count 2 2006.173.19:12:42.56#ibcon#wrote, iclass 16, count 2 2006.173.19:12:42.56#ibcon#about to read 3, iclass 16, count 2 2006.173.19:12:42.58#ibcon#read 3, iclass 16, count 2 2006.173.19:12:42.58#ibcon#about to read 4, iclass 16, count 2 2006.173.19:12:42.58#ibcon#read 4, iclass 16, count 2 2006.173.19:12:42.58#ibcon#about to read 5, iclass 16, count 2 2006.173.19:12:42.58#ibcon#read 5, iclass 16, count 2 2006.173.19:12:42.58#ibcon#about to read 6, iclass 16, count 2 2006.173.19:12:42.58#ibcon#read 6, iclass 16, count 2 2006.173.19:12:42.58#ibcon#end of sib2, iclass 16, count 2 2006.173.19:12:42.58#ibcon#*after write, iclass 16, count 2 2006.173.19:12:42.58#ibcon#*before return 0, iclass 16, count 2 2006.173.19:12:42.59#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.19:12:42.59#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.19:12:42.59#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.19:12:42.59#ibcon#ireg 7 cls_cnt 0 2006.173.19:12:42.59#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.19:12:42.70#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.19:12:42.70#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.19:12:42.70#ibcon#enter wrdev, iclass 16, count 0 2006.173.19:12:42.70#ibcon#first serial, iclass 16, count 0 2006.173.19:12:42.70#ibcon#enter sib2, iclass 16, count 0 2006.173.19:12:42.70#ibcon#flushed, iclass 16, count 0 2006.173.19:12:42.70#ibcon#about to write, iclass 16, count 0 2006.173.19:12:42.70#ibcon#wrote, iclass 16, count 0 2006.173.19:12:42.70#ibcon#about to read 3, iclass 16, count 0 2006.173.19:12:42.72#ibcon#read 3, iclass 16, count 0 2006.173.19:12:42.72#ibcon#about to read 4, iclass 16, count 0 2006.173.19:12:42.72#ibcon#read 4, iclass 16, count 0 2006.173.19:12:42.72#ibcon#about to read 5, iclass 16, count 0 2006.173.19:12:42.72#ibcon#read 5, iclass 16, count 0 2006.173.19:12:42.72#ibcon#about to read 6, iclass 16, count 0 2006.173.19:12:42.72#ibcon#read 6, iclass 16, count 0 2006.173.19:12:42.72#ibcon#end of sib2, iclass 16, count 0 2006.173.19:12:42.72#ibcon#*mode == 0, iclass 16, count 0 2006.173.19:12:42.72#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.19:12:42.72#ibcon#[25=USB\r\n] 2006.173.19:12:42.73#ibcon#*before write, iclass 16, count 0 2006.173.19:12:42.73#ibcon#enter sib2, iclass 16, count 0 2006.173.19:12:42.73#ibcon#flushed, iclass 16, count 0 2006.173.19:12:42.73#ibcon#about to write, iclass 16, count 0 2006.173.19:12:42.73#ibcon#wrote, iclass 16, count 0 2006.173.19:12:42.73#ibcon#about to read 3, iclass 16, count 0 2006.173.19:12:42.75#ibcon#read 3, iclass 16, count 0 2006.173.19:12:42.75#ibcon#about to read 4, iclass 16, count 0 2006.173.19:12:42.75#ibcon#read 4, iclass 16, count 0 2006.173.19:12:42.75#ibcon#about to read 5, iclass 16, count 0 2006.173.19:12:42.75#ibcon#read 5, iclass 16, count 0 2006.173.19:12:42.75#ibcon#about to read 6, iclass 16, count 0 2006.173.19:12:42.75#ibcon#read 6, iclass 16, count 0 2006.173.19:12:42.75#ibcon#end of sib2, iclass 16, count 0 2006.173.19:12:42.75#ibcon#*after write, iclass 16, count 0 2006.173.19:12:42.75#ibcon#*before return 0, iclass 16, count 0 2006.173.19:12:42.76#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.19:12:42.76#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.19:12:42.76#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.19:12:42.76#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.19:12:42.76$vck44/valo=2,534.99 2006.173.19:12:42.76#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.19:12:42.76#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.19:12:42.76#ibcon#ireg 17 cls_cnt 0 2006.173.19:12:42.76#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.19:12:42.76#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.19:12:42.76#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.19:12:42.76#ibcon#enter wrdev, iclass 18, count 0 2006.173.19:12:42.76#ibcon#first serial, iclass 18, count 0 2006.173.19:12:42.76#ibcon#enter sib2, iclass 18, count 0 2006.173.19:12:42.76#ibcon#flushed, iclass 18, count 0 2006.173.19:12:42.76#ibcon#about to write, iclass 18, count 0 2006.173.19:12:42.76#ibcon#wrote, iclass 18, count 0 2006.173.19:12:42.76#ibcon#about to read 3, iclass 18, count 0 2006.173.19:12:42.77#ibcon#read 3, iclass 18, count 0 2006.173.19:12:42.77#ibcon#about to read 4, iclass 18, count 0 2006.173.19:12:42.77#ibcon#read 4, iclass 18, count 0 2006.173.19:12:42.77#ibcon#about to read 5, iclass 18, count 0 2006.173.19:12:42.77#ibcon#read 5, iclass 18, count 0 2006.173.19:12:42.77#ibcon#about to read 6, iclass 18, count 0 2006.173.19:12:42.77#ibcon#read 6, iclass 18, count 0 2006.173.19:12:42.77#ibcon#end of sib2, iclass 18, count 0 2006.173.19:12:42.77#ibcon#*mode == 0, iclass 18, count 0 2006.173.19:12:42.77#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.19:12:42.77#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.19:12:42.78#ibcon#*before write, iclass 18, count 0 2006.173.19:12:42.78#ibcon#enter sib2, iclass 18, count 0 2006.173.19:12:42.78#ibcon#flushed, iclass 18, count 0 2006.173.19:12:42.78#ibcon#about to write, iclass 18, count 0 2006.173.19:12:42.78#ibcon#wrote, iclass 18, count 0 2006.173.19:12:42.78#ibcon#about to read 3, iclass 18, count 0 2006.173.19:12:42.81#ibcon#read 3, iclass 18, count 0 2006.173.19:12:42.81#ibcon#about to read 4, iclass 18, count 0 2006.173.19:12:42.81#ibcon#read 4, iclass 18, count 0 2006.173.19:12:42.81#ibcon#about to read 5, iclass 18, count 0 2006.173.19:12:42.81#ibcon#read 5, iclass 18, count 0 2006.173.19:12:42.81#ibcon#about to read 6, iclass 18, count 0 2006.173.19:12:42.81#ibcon#read 6, iclass 18, count 0 2006.173.19:12:42.81#ibcon#end of sib2, iclass 18, count 0 2006.173.19:12:42.81#ibcon#*after write, iclass 18, count 0 2006.173.19:12:42.81#ibcon#*before return 0, iclass 18, count 0 2006.173.19:12:42.81#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.19:12:42.82#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.19:12:42.82#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.19:12:42.82#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.19:12:42.82$vck44/va=2,6 2006.173.19:12:42.82#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.19:12:42.82#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.19:12:42.82#ibcon#ireg 11 cls_cnt 2 2006.173.19:12:42.82#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.19:12:42.87#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.19:12:42.87#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.19:12:42.87#ibcon#enter wrdev, iclass 20, count 2 2006.173.19:12:42.87#ibcon#first serial, iclass 20, count 2 2006.173.19:12:42.87#ibcon#enter sib2, iclass 20, count 2 2006.173.19:12:42.87#ibcon#flushed, iclass 20, count 2 2006.173.19:12:42.87#ibcon#about to write, iclass 20, count 2 2006.173.19:12:42.87#ibcon#wrote, iclass 20, count 2 2006.173.19:12:42.87#ibcon#about to read 3, iclass 20, count 2 2006.173.19:12:42.89#ibcon#read 3, iclass 20, count 2 2006.173.19:12:42.89#ibcon#about to read 4, iclass 20, count 2 2006.173.19:12:42.89#ibcon#read 4, iclass 20, count 2 2006.173.19:12:42.89#ibcon#about to read 5, iclass 20, count 2 2006.173.19:12:42.89#ibcon#read 5, iclass 20, count 2 2006.173.19:12:42.89#ibcon#about to read 6, iclass 20, count 2 2006.173.19:12:42.89#ibcon#read 6, iclass 20, count 2 2006.173.19:12:42.89#ibcon#end of sib2, iclass 20, count 2 2006.173.19:12:42.89#ibcon#*mode == 0, iclass 20, count 2 2006.173.19:12:42.89#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.19:12:42.89#ibcon#[25=AT02-06\r\n] 2006.173.19:12:42.89#ibcon#*before write, iclass 20, count 2 2006.173.19:12:42.89#ibcon#enter sib2, iclass 20, count 2 2006.173.19:12:42.90#ibcon#flushed, iclass 20, count 2 2006.173.19:12:42.90#ibcon#about to write, iclass 20, count 2 2006.173.19:12:42.90#ibcon#wrote, iclass 20, count 2 2006.173.19:12:42.90#ibcon#about to read 3, iclass 20, count 2 2006.173.19:12:42.92#ibcon#read 3, iclass 20, count 2 2006.173.19:12:42.92#ibcon#about to read 4, iclass 20, count 2 2006.173.19:12:42.92#ibcon#read 4, iclass 20, count 2 2006.173.19:12:42.92#ibcon#about to read 5, iclass 20, count 2 2006.173.19:12:42.92#ibcon#read 5, iclass 20, count 2 2006.173.19:12:42.92#ibcon#about to read 6, iclass 20, count 2 2006.173.19:12:42.92#ibcon#read 6, iclass 20, count 2 2006.173.19:12:42.92#ibcon#end of sib2, iclass 20, count 2 2006.173.19:12:42.92#ibcon#*after write, iclass 20, count 2 2006.173.19:12:42.92#ibcon#*before return 0, iclass 20, count 2 2006.173.19:12:42.93#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.19:12:42.93#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.19:12:42.93#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.19:12:42.93#ibcon#ireg 7 cls_cnt 0 2006.173.19:12:42.93#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.19:12:43.04#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.19:12:43.04#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.19:12:43.04#ibcon#enter wrdev, iclass 20, count 0 2006.173.19:12:43.04#ibcon#first serial, iclass 20, count 0 2006.173.19:12:43.04#ibcon#enter sib2, iclass 20, count 0 2006.173.19:12:43.04#ibcon#flushed, iclass 20, count 0 2006.173.19:12:43.04#ibcon#about to write, iclass 20, count 0 2006.173.19:12:43.04#ibcon#wrote, iclass 20, count 0 2006.173.19:12:43.04#ibcon#about to read 3, iclass 20, count 0 2006.173.19:12:43.06#ibcon#read 3, iclass 20, count 0 2006.173.19:12:43.06#ibcon#about to read 4, iclass 20, count 0 2006.173.19:12:43.06#ibcon#read 4, iclass 20, count 0 2006.173.19:12:43.06#ibcon#about to read 5, iclass 20, count 0 2006.173.19:12:43.06#ibcon#read 5, iclass 20, count 0 2006.173.19:12:43.06#ibcon#about to read 6, iclass 20, count 0 2006.173.19:12:43.06#ibcon#read 6, iclass 20, count 0 2006.173.19:12:43.06#ibcon#end of sib2, iclass 20, count 0 2006.173.19:12:43.06#ibcon#*mode == 0, iclass 20, count 0 2006.173.19:12:43.06#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.19:12:43.06#ibcon#[25=USB\r\n] 2006.173.19:12:43.06#ibcon#*before write, iclass 20, count 0 2006.173.19:12:43.06#ibcon#enter sib2, iclass 20, count 0 2006.173.19:12:43.06#ibcon#flushed, iclass 20, count 0 2006.173.19:12:43.06#ibcon#about to write, iclass 20, count 0 2006.173.19:12:43.07#ibcon#wrote, iclass 20, count 0 2006.173.19:12:43.07#ibcon#about to read 3, iclass 20, count 0 2006.173.19:12:43.09#ibcon#read 3, iclass 20, count 0 2006.173.19:12:43.09#ibcon#about to read 4, iclass 20, count 0 2006.173.19:12:43.09#ibcon#read 4, iclass 20, count 0 2006.173.19:12:43.09#ibcon#about to read 5, iclass 20, count 0 2006.173.19:12:43.09#ibcon#read 5, iclass 20, count 0 2006.173.19:12:43.09#ibcon#about to read 6, iclass 20, count 0 2006.173.19:12:43.09#ibcon#read 6, iclass 20, count 0 2006.173.19:12:43.09#ibcon#end of sib2, iclass 20, count 0 2006.173.19:12:43.09#ibcon#*after write, iclass 20, count 0 2006.173.19:12:43.09#ibcon#*before return 0, iclass 20, count 0 2006.173.19:12:43.09#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.19:12:43.10#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.19:12:43.10#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.19:12:43.10#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.19:12:43.10$vck44/valo=3,564.99 2006.173.19:12:43.10#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.19:12:43.10#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.19:12:43.10#ibcon#ireg 17 cls_cnt 0 2006.173.19:12:43.10#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.19:12:43.10#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.19:12:43.10#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.19:12:43.10#ibcon#enter wrdev, iclass 22, count 0 2006.173.19:12:43.10#ibcon#first serial, iclass 22, count 0 2006.173.19:12:43.10#ibcon#enter sib2, iclass 22, count 0 2006.173.19:12:43.10#ibcon#flushed, iclass 22, count 0 2006.173.19:12:43.10#ibcon#about to write, iclass 22, count 0 2006.173.19:12:43.10#ibcon#wrote, iclass 22, count 0 2006.173.19:12:43.10#ibcon#about to read 3, iclass 22, count 0 2006.173.19:12:43.11#ibcon#read 3, iclass 22, count 0 2006.173.19:12:43.11#ibcon#about to read 4, iclass 22, count 0 2006.173.19:12:43.11#ibcon#read 4, iclass 22, count 0 2006.173.19:12:43.11#ibcon#about to read 5, iclass 22, count 0 2006.173.19:12:43.11#ibcon#read 5, iclass 22, count 0 2006.173.19:12:43.11#ibcon#about to read 6, iclass 22, count 0 2006.173.19:12:43.11#ibcon#read 6, iclass 22, count 0 2006.173.19:12:43.11#ibcon#end of sib2, iclass 22, count 0 2006.173.19:12:43.11#ibcon#*mode == 0, iclass 22, count 0 2006.173.19:12:43.11#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.19:12:43.11#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.19:12:43.11#ibcon#*before write, iclass 22, count 0 2006.173.19:12:43.12#ibcon#enter sib2, iclass 22, count 0 2006.173.19:12:43.12#ibcon#flushed, iclass 22, count 0 2006.173.19:12:43.12#ibcon#about to write, iclass 22, count 0 2006.173.19:12:43.12#ibcon#wrote, iclass 22, count 0 2006.173.19:12:43.12#ibcon#about to read 3, iclass 22, count 0 2006.173.19:12:43.15#ibcon#read 3, iclass 22, count 0 2006.173.19:12:43.15#ibcon#about to read 4, iclass 22, count 0 2006.173.19:12:43.15#ibcon#read 4, iclass 22, count 0 2006.173.19:12:43.15#ibcon#about to read 5, iclass 22, count 0 2006.173.19:12:43.15#ibcon#read 5, iclass 22, count 0 2006.173.19:12:43.15#ibcon#about to read 6, iclass 22, count 0 2006.173.19:12:43.15#ibcon#read 6, iclass 22, count 0 2006.173.19:12:43.15#ibcon#end of sib2, iclass 22, count 0 2006.173.19:12:43.15#ibcon#*after write, iclass 22, count 0 2006.173.19:12:43.15#ibcon#*before return 0, iclass 22, count 0 2006.173.19:12:43.15#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.19:12:43.16#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.19:12:43.16#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.19:12:43.16#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.19:12:43.16$vck44/va=3,5 2006.173.19:12:43.16#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.19:12:43.16#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.19:12:43.16#ibcon#ireg 11 cls_cnt 2 2006.173.19:12:43.16#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.19:12:43.21#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.19:12:43.21#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.19:12:43.21#ibcon#enter wrdev, iclass 24, count 2 2006.173.19:12:43.21#ibcon#first serial, iclass 24, count 2 2006.173.19:12:43.21#ibcon#enter sib2, iclass 24, count 2 2006.173.19:12:43.21#ibcon#flushed, iclass 24, count 2 2006.173.19:12:43.21#ibcon#about to write, iclass 24, count 2 2006.173.19:12:43.21#ibcon#wrote, iclass 24, count 2 2006.173.19:12:43.21#ibcon#about to read 3, iclass 24, count 2 2006.173.19:12:43.23#ibcon#read 3, iclass 24, count 2 2006.173.19:12:43.23#ibcon#about to read 4, iclass 24, count 2 2006.173.19:12:43.23#ibcon#read 4, iclass 24, count 2 2006.173.19:12:43.23#ibcon#about to read 5, iclass 24, count 2 2006.173.19:12:43.23#ibcon#read 5, iclass 24, count 2 2006.173.19:12:43.23#ibcon#about to read 6, iclass 24, count 2 2006.173.19:12:43.23#ibcon#read 6, iclass 24, count 2 2006.173.19:12:43.23#ibcon#end of sib2, iclass 24, count 2 2006.173.19:12:43.23#ibcon#*mode == 0, iclass 24, count 2 2006.173.19:12:43.23#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.19:12:43.23#ibcon#[25=AT03-05\r\n] 2006.173.19:12:43.23#ibcon#*before write, iclass 24, count 2 2006.173.19:12:43.23#ibcon#enter sib2, iclass 24, count 2 2006.173.19:12:43.23#ibcon#flushed, iclass 24, count 2 2006.173.19:12:43.23#ibcon#about to write, iclass 24, count 2 2006.173.19:12:43.24#ibcon#wrote, iclass 24, count 2 2006.173.19:12:43.24#ibcon#about to read 3, iclass 24, count 2 2006.173.19:12:43.26#ibcon#read 3, iclass 24, count 2 2006.173.19:12:43.26#ibcon#about to read 4, iclass 24, count 2 2006.173.19:12:43.26#ibcon#read 4, iclass 24, count 2 2006.173.19:12:43.26#ibcon#about to read 5, iclass 24, count 2 2006.173.19:12:43.26#ibcon#read 5, iclass 24, count 2 2006.173.19:12:43.26#ibcon#about to read 6, iclass 24, count 2 2006.173.19:12:43.26#ibcon#read 6, iclass 24, count 2 2006.173.19:12:43.26#ibcon#end of sib2, iclass 24, count 2 2006.173.19:12:43.26#ibcon#*after write, iclass 24, count 2 2006.173.19:12:43.26#ibcon#*before return 0, iclass 24, count 2 2006.173.19:12:43.26#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.19:12:43.26#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.19:12:43.26#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.19:12:43.27#ibcon#ireg 7 cls_cnt 0 2006.173.19:12:43.27#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.19:12:43.28#abcon#<5=/10 0.3 1.1 19.561001002.5\r\n> 2006.173.19:12:43.30#abcon#{5=INTERFACE CLEAR} 2006.173.19:12:43.36#abcon#[5=S1D000X0/0*\r\n] 2006.173.19:12:43.37#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.19:12:43.37#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.19:12:43.37#ibcon#enter wrdev, iclass 24, count 0 2006.173.19:12:43.37#ibcon#first serial, iclass 24, count 0 2006.173.19:12:43.37#ibcon#enter sib2, iclass 24, count 0 2006.173.19:12:43.37#ibcon#flushed, iclass 24, count 0 2006.173.19:12:43.37#ibcon#about to write, iclass 24, count 0 2006.173.19:12:43.37#ibcon#wrote, iclass 24, count 0 2006.173.19:12:43.37#ibcon#about to read 3, iclass 24, count 0 2006.173.19:12:43.39#ibcon#read 3, iclass 24, count 0 2006.173.19:12:43.39#ibcon#about to read 4, iclass 24, count 0 2006.173.19:12:43.39#ibcon#read 4, iclass 24, count 0 2006.173.19:12:43.39#ibcon#about to read 5, iclass 24, count 0 2006.173.19:12:43.39#ibcon#read 5, iclass 24, count 0 2006.173.19:12:43.39#ibcon#about to read 6, iclass 24, count 0 2006.173.19:12:43.39#ibcon#read 6, iclass 24, count 0 2006.173.19:12:43.39#ibcon#end of sib2, iclass 24, count 0 2006.173.19:12:43.39#ibcon#*mode == 0, iclass 24, count 0 2006.173.19:12:43.40#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.19:12:43.40#ibcon#[25=USB\r\n] 2006.173.19:12:43.40#ibcon#*before write, iclass 24, count 0 2006.173.19:12:43.40#ibcon#enter sib2, iclass 24, count 0 2006.173.19:12:43.40#ibcon#flushed, iclass 24, count 0 2006.173.19:12:43.40#ibcon#about to write, iclass 24, count 0 2006.173.19:12:43.40#ibcon#wrote, iclass 24, count 0 2006.173.19:12:43.40#ibcon#about to read 3, iclass 24, count 0 2006.173.19:12:43.42#ibcon#read 3, iclass 24, count 0 2006.173.19:12:43.42#ibcon#about to read 4, iclass 24, count 0 2006.173.19:12:43.42#ibcon#read 4, iclass 24, count 0 2006.173.19:12:43.42#ibcon#about to read 5, iclass 24, count 0 2006.173.19:12:43.42#ibcon#read 5, iclass 24, count 0 2006.173.19:12:43.42#ibcon#about to read 6, iclass 24, count 0 2006.173.19:12:43.42#ibcon#read 6, iclass 24, count 0 2006.173.19:12:43.42#ibcon#end of sib2, iclass 24, count 0 2006.173.19:12:43.42#ibcon#*after write, iclass 24, count 0 2006.173.19:12:43.42#ibcon#*before return 0, iclass 24, count 0 2006.173.19:12:43.42#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.19:12:43.43#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.19:12:43.43#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.19:12:43.43#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.19:12:43.43$vck44/valo=4,624.99 2006.173.19:12:43.43#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.19:12:43.43#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.19:12:43.43#ibcon#ireg 17 cls_cnt 0 2006.173.19:12:43.43#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.19:12:43.43#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.19:12:43.43#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.19:12:43.43#ibcon#enter wrdev, iclass 30, count 0 2006.173.19:12:43.43#ibcon#first serial, iclass 30, count 0 2006.173.19:12:43.43#ibcon#enter sib2, iclass 30, count 0 2006.173.19:12:43.43#ibcon#flushed, iclass 30, count 0 2006.173.19:12:43.43#ibcon#about to write, iclass 30, count 0 2006.173.19:12:43.43#ibcon#wrote, iclass 30, count 0 2006.173.19:12:43.43#ibcon#about to read 3, iclass 30, count 0 2006.173.19:12:43.44#ibcon#read 3, iclass 30, count 0 2006.173.19:12:43.44#ibcon#about to read 4, iclass 30, count 0 2006.173.19:12:43.44#ibcon#read 4, iclass 30, count 0 2006.173.19:12:43.44#ibcon#about to read 5, iclass 30, count 0 2006.173.19:12:43.44#ibcon#read 5, iclass 30, count 0 2006.173.19:12:43.44#ibcon#about to read 6, iclass 30, count 0 2006.173.19:12:43.44#ibcon#read 6, iclass 30, count 0 2006.173.19:12:43.44#ibcon#end of sib2, iclass 30, count 0 2006.173.19:12:43.44#ibcon#*mode == 0, iclass 30, count 0 2006.173.19:12:43.44#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.19:12:43.45#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.19:12:43.45#ibcon#*before write, iclass 30, count 0 2006.173.19:12:43.45#ibcon#enter sib2, iclass 30, count 0 2006.173.19:12:43.45#ibcon#flushed, iclass 30, count 0 2006.173.19:12:43.45#ibcon#about to write, iclass 30, count 0 2006.173.19:12:43.45#ibcon#wrote, iclass 30, count 0 2006.173.19:12:43.45#ibcon#about to read 3, iclass 30, count 0 2006.173.19:12:43.48#ibcon#read 3, iclass 30, count 0 2006.173.19:12:43.48#ibcon#about to read 4, iclass 30, count 0 2006.173.19:12:43.48#ibcon#read 4, iclass 30, count 0 2006.173.19:12:43.48#ibcon#about to read 5, iclass 30, count 0 2006.173.19:12:43.48#ibcon#read 5, iclass 30, count 0 2006.173.19:12:43.48#ibcon#about to read 6, iclass 30, count 0 2006.173.19:12:43.48#ibcon#read 6, iclass 30, count 0 2006.173.19:12:43.48#ibcon#end of sib2, iclass 30, count 0 2006.173.19:12:43.48#ibcon#*after write, iclass 30, count 0 2006.173.19:12:43.48#ibcon#*before return 0, iclass 30, count 0 2006.173.19:12:43.49#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.19:12:43.49#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.19:12:43.49#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.19:12:43.49#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.19:12:43.49$vck44/va=4,6 2006.173.19:12:43.49#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.173.19:12:43.49#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.173.19:12:43.49#ibcon#ireg 11 cls_cnt 2 2006.173.19:12:43.49#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.19:12:43.54#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.19:12:43.54#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.19:12:43.54#ibcon#enter wrdev, iclass 32, count 2 2006.173.19:12:43.54#ibcon#first serial, iclass 32, count 2 2006.173.19:12:43.54#ibcon#enter sib2, iclass 32, count 2 2006.173.19:12:43.54#ibcon#flushed, iclass 32, count 2 2006.173.19:12:43.54#ibcon#about to write, iclass 32, count 2 2006.173.19:12:43.54#ibcon#wrote, iclass 32, count 2 2006.173.19:12:43.54#ibcon#about to read 3, iclass 32, count 2 2006.173.19:12:43.56#ibcon#read 3, iclass 32, count 2 2006.173.19:12:43.56#ibcon#about to read 4, iclass 32, count 2 2006.173.19:12:43.56#ibcon#read 4, iclass 32, count 2 2006.173.19:12:43.56#ibcon#about to read 5, iclass 32, count 2 2006.173.19:12:43.56#ibcon#read 5, iclass 32, count 2 2006.173.19:12:43.56#ibcon#about to read 6, iclass 32, count 2 2006.173.19:12:43.56#ibcon#read 6, iclass 32, count 2 2006.173.19:12:43.56#ibcon#end of sib2, iclass 32, count 2 2006.173.19:12:43.56#ibcon#*mode == 0, iclass 32, count 2 2006.173.19:12:43.56#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.173.19:12:43.57#ibcon#[25=AT04-06\r\n] 2006.173.19:12:43.57#ibcon#*before write, iclass 32, count 2 2006.173.19:12:43.57#ibcon#enter sib2, iclass 32, count 2 2006.173.19:12:43.57#ibcon#flushed, iclass 32, count 2 2006.173.19:12:43.57#ibcon#about to write, iclass 32, count 2 2006.173.19:12:43.57#ibcon#wrote, iclass 32, count 2 2006.173.19:12:43.57#ibcon#about to read 3, iclass 32, count 2 2006.173.19:12:43.59#ibcon#read 3, iclass 32, count 2 2006.173.19:12:43.59#ibcon#about to read 4, iclass 32, count 2 2006.173.19:12:43.59#ibcon#read 4, iclass 32, count 2 2006.173.19:12:43.59#ibcon#about to read 5, iclass 32, count 2 2006.173.19:12:43.59#ibcon#read 5, iclass 32, count 2 2006.173.19:12:43.59#ibcon#about to read 6, iclass 32, count 2 2006.173.19:12:43.59#ibcon#read 6, iclass 32, count 2 2006.173.19:12:43.59#ibcon#end of sib2, iclass 32, count 2 2006.173.19:12:43.59#ibcon#*after write, iclass 32, count 2 2006.173.19:12:43.59#ibcon#*before return 0, iclass 32, count 2 2006.173.19:12:43.59#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.19:12:43.60#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.173.19:12:43.60#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.173.19:12:43.60#ibcon#ireg 7 cls_cnt 0 2006.173.19:12:43.60#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.19:12:43.71#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.19:12:43.71#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.19:12:43.71#ibcon#enter wrdev, iclass 32, count 0 2006.173.19:12:43.71#ibcon#first serial, iclass 32, count 0 2006.173.19:12:43.71#ibcon#enter sib2, iclass 32, count 0 2006.173.19:12:43.71#ibcon#flushed, iclass 32, count 0 2006.173.19:12:43.71#ibcon#about to write, iclass 32, count 0 2006.173.19:12:43.71#ibcon#wrote, iclass 32, count 0 2006.173.19:12:43.71#ibcon#about to read 3, iclass 32, count 0 2006.173.19:12:43.73#ibcon#read 3, iclass 32, count 0 2006.173.19:12:43.73#ibcon#about to read 4, iclass 32, count 0 2006.173.19:12:43.73#ibcon#read 4, iclass 32, count 0 2006.173.19:12:43.73#ibcon#about to read 5, iclass 32, count 0 2006.173.19:12:43.73#ibcon#read 5, iclass 32, count 0 2006.173.19:12:43.73#ibcon#about to read 6, iclass 32, count 0 2006.173.19:12:43.73#ibcon#read 6, iclass 32, count 0 2006.173.19:12:43.73#ibcon#end of sib2, iclass 32, count 0 2006.173.19:12:43.73#ibcon#*mode == 0, iclass 32, count 0 2006.173.19:12:43.73#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.19:12:43.74#ibcon#[25=USB\r\n] 2006.173.19:12:43.74#ibcon#*before write, iclass 32, count 0 2006.173.19:12:43.74#ibcon#enter sib2, iclass 32, count 0 2006.173.19:12:43.74#ibcon#flushed, iclass 32, count 0 2006.173.19:12:43.74#ibcon#about to write, iclass 32, count 0 2006.173.19:12:43.74#ibcon#wrote, iclass 32, count 0 2006.173.19:12:43.74#ibcon#about to read 3, iclass 32, count 0 2006.173.19:12:43.76#ibcon#read 3, iclass 32, count 0 2006.173.19:12:43.76#ibcon#about to read 4, iclass 32, count 0 2006.173.19:12:43.76#ibcon#read 4, iclass 32, count 0 2006.173.19:12:43.76#ibcon#about to read 5, iclass 32, count 0 2006.173.19:12:43.76#ibcon#read 5, iclass 32, count 0 2006.173.19:12:43.76#ibcon#about to read 6, iclass 32, count 0 2006.173.19:12:43.76#ibcon#read 6, iclass 32, count 0 2006.173.19:12:43.76#ibcon#end of sib2, iclass 32, count 0 2006.173.19:12:43.76#ibcon#*after write, iclass 32, count 0 2006.173.19:12:43.76#ibcon#*before return 0, iclass 32, count 0 2006.173.19:12:43.77#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.19:12:43.77#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.173.19:12:43.77#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.19:12:43.77#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.19:12:43.77$vck44/valo=5,734.99 2006.173.19:12:43.77#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.19:12:43.77#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.19:12:43.77#ibcon#ireg 17 cls_cnt 0 2006.173.19:12:43.77#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.19:12:43.77#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.19:12:43.77#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.19:12:43.77#ibcon#enter wrdev, iclass 34, count 0 2006.173.19:12:43.77#ibcon#first serial, iclass 34, count 0 2006.173.19:12:43.77#ibcon#enter sib2, iclass 34, count 0 2006.173.19:12:43.77#ibcon#flushed, iclass 34, count 0 2006.173.19:12:43.77#ibcon#about to write, iclass 34, count 0 2006.173.19:12:43.77#ibcon#wrote, iclass 34, count 0 2006.173.19:12:43.77#ibcon#about to read 3, iclass 34, count 0 2006.173.19:12:43.78#ibcon#read 3, iclass 34, count 0 2006.173.19:12:43.78#ibcon#about to read 4, iclass 34, count 0 2006.173.19:12:43.78#ibcon#read 4, iclass 34, count 0 2006.173.19:12:43.78#ibcon#about to read 5, iclass 34, count 0 2006.173.19:12:43.78#ibcon#read 5, iclass 34, count 0 2006.173.19:12:43.78#ibcon#about to read 6, iclass 34, count 0 2006.173.19:12:43.78#ibcon#read 6, iclass 34, count 0 2006.173.19:12:43.78#ibcon#end of sib2, iclass 34, count 0 2006.173.19:12:43.79#ibcon#*mode == 0, iclass 34, count 0 2006.173.19:12:43.79#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.19:12:43.79#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.19:12:43.79#ibcon#*before write, iclass 34, count 0 2006.173.19:12:43.79#ibcon#enter sib2, iclass 34, count 0 2006.173.19:12:43.79#ibcon#flushed, iclass 34, count 0 2006.173.19:12:43.79#ibcon#about to write, iclass 34, count 0 2006.173.19:12:43.79#ibcon#wrote, iclass 34, count 0 2006.173.19:12:43.79#ibcon#about to read 3, iclass 34, count 0 2006.173.19:12:43.82#ibcon#read 3, iclass 34, count 0 2006.173.19:12:43.82#ibcon#about to read 4, iclass 34, count 0 2006.173.19:12:43.82#ibcon#read 4, iclass 34, count 0 2006.173.19:12:43.82#ibcon#about to read 5, iclass 34, count 0 2006.173.19:12:43.82#ibcon#read 5, iclass 34, count 0 2006.173.19:12:43.82#ibcon#about to read 6, iclass 34, count 0 2006.173.19:12:43.82#ibcon#read 6, iclass 34, count 0 2006.173.19:12:43.82#ibcon#end of sib2, iclass 34, count 0 2006.173.19:12:43.82#ibcon#*after write, iclass 34, count 0 2006.173.19:12:43.82#ibcon#*before return 0, iclass 34, count 0 2006.173.19:12:43.83#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.19:12:43.83#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.19:12:43.83#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.19:12:43.83#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.19:12:43.83$vck44/va=5,4 2006.173.19:12:43.83#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.19:12:43.83#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.19:12:43.83#ibcon#ireg 11 cls_cnt 2 2006.173.19:12:43.83#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.19:12:43.88#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.19:12:43.88#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.19:12:43.88#ibcon#enter wrdev, iclass 36, count 2 2006.173.19:12:43.88#ibcon#first serial, iclass 36, count 2 2006.173.19:12:43.88#ibcon#enter sib2, iclass 36, count 2 2006.173.19:12:43.88#ibcon#flushed, iclass 36, count 2 2006.173.19:12:43.88#ibcon#about to write, iclass 36, count 2 2006.173.19:12:43.88#ibcon#wrote, iclass 36, count 2 2006.173.19:12:43.88#ibcon#about to read 3, iclass 36, count 2 2006.173.19:12:43.90#ibcon#read 3, iclass 36, count 2 2006.173.19:12:43.90#ibcon#about to read 4, iclass 36, count 2 2006.173.19:12:43.90#ibcon#read 4, iclass 36, count 2 2006.173.19:12:43.90#ibcon#about to read 5, iclass 36, count 2 2006.173.19:12:43.90#ibcon#read 5, iclass 36, count 2 2006.173.19:12:43.90#ibcon#about to read 6, iclass 36, count 2 2006.173.19:12:43.90#ibcon#read 6, iclass 36, count 2 2006.173.19:12:43.90#ibcon#end of sib2, iclass 36, count 2 2006.173.19:12:43.90#ibcon#*mode == 0, iclass 36, count 2 2006.173.19:12:43.90#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.19:12:43.90#ibcon#[25=AT05-04\r\n] 2006.173.19:12:43.90#ibcon#*before write, iclass 36, count 2 2006.173.19:12:43.90#ibcon#enter sib2, iclass 36, count 2 2006.173.19:12:43.91#ibcon#flushed, iclass 36, count 2 2006.173.19:12:43.91#ibcon#about to write, iclass 36, count 2 2006.173.19:12:43.91#ibcon#wrote, iclass 36, count 2 2006.173.19:12:43.91#ibcon#about to read 3, iclass 36, count 2 2006.173.19:12:43.93#ibcon#read 3, iclass 36, count 2 2006.173.19:12:43.93#ibcon#about to read 4, iclass 36, count 2 2006.173.19:12:43.93#ibcon#read 4, iclass 36, count 2 2006.173.19:12:43.93#ibcon#about to read 5, iclass 36, count 2 2006.173.19:12:43.93#ibcon#read 5, iclass 36, count 2 2006.173.19:12:43.93#ibcon#about to read 6, iclass 36, count 2 2006.173.19:12:43.93#ibcon#read 6, iclass 36, count 2 2006.173.19:12:43.93#ibcon#end of sib2, iclass 36, count 2 2006.173.19:12:43.93#ibcon#*after write, iclass 36, count 2 2006.173.19:12:43.93#ibcon#*before return 0, iclass 36, count 2 2006.173.19:12:43.93#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.19:12:43.93#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.19:12:43.93#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.19:12:43.93#ibcon#ireg 7 cls_cnt 0 2006.173.19:12:43.94#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.19:12:44.04#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.19:12:44.04#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.19:12:44.04#ibcon#enter wrdev, iclass 36, count 0 2006.173.19:12:44.04#ibcon#first serial, iclass 36, count 0 2006.173.19:12:44.04#ibcon#enter sib2, iclass 36, count 0 2006.173.19:12:44.04#ibcon#flushed, iclass 36, count 0 2006.173.19:12:44.04#ibcon#about to write, iclass 36, count 0 2006.173.19:12:44.04#ibcon#wrote, iclass 36, count 0 2006.173.19:12:44.04#ibcon#about to read 3, iclass 36, count 0 2006.173.19:12:44.06#ibcon#read 3, iclass 36, count 0 2006.173.19:12:44.06#ibcon#about to read 4, iclass 36, count 0 2006.173.19:12:44.06#ibcon#read 4, iclass 36, count 0 2006.173.19:12:44.06#ibcon#about to read 5, iclass 36, count 0 2006.173.19:12:44.06#ibcon#read 5, iclass 36, count 0 2006.173.19:12:44.06#ibcon#about to read 6, iclass 36, count 0 2006.173.19:12:44.06#ibcon#read 6, iclass 36, count 0 2006.173.19:12:44.06#ibcon#end of sib2, iclass 36, count 0 2006.173.19:12:44.06#ibcon#*mode == 0, iclass 36, count 0 2006.173.19:12:44.06#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.19:12:44.06#ibcon#[25=USB\r\n] 2006.173.19:12:44.06#ibcon#*before write, iclass 36, count 0 2006.173.19:12:44.06#ibcon#enter sib2, iclass 36, count 0 2006.173.19:12:44.07#ibcon#flushed, iclass 36, count 0 2006.173.19:12:44.07#ibcon#about to write, iclass 36, count 0 2006.173.19:12:44.07#ibcon#wrote, iclass 36, count 0 2006.173.19:12:44.07#ibcon#about to read 3, iclass 36, count 0 2006.173.19:12:44.09#ibcon#read 3, iclass 36, count 0 2006.173.19:12:44.09#ibcon#about to read 4, iclass 36, count 0 2006.173.19:12:44.09#ibcon#read 4, iclass 36, count 0 2006.173.19:12:44.09#ibcon#about to read 5, iclass 36, count 0 2006.173.19:12:44.09#ibcon#read 5, iclass 36, count 0 2006.173.19:12:44.09#ibcon#about to read 6, iclass 36, count 0 2006.173.19:12:44.09#ibcon#read 6, iclass 36, count 0 2006.173.19:12:44.09#ibcon#end of sib2, iclass 36, count 0 2006.173.19:12:44.09#ibcon#*after write, iclass 36, count 0 2006.173.19:12:44.09#ibcon#*before return 0, iclass 36, count 0 2006.173.19:12:44.09#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.19:12:44.09#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.19:12:44.09#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.19:12:44.09#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.19:12:44.10$vck44/valo=6,814.99 2006.173.19:12:44.10#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.19:12:44.10#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.19:12:44.10#ibcon#ireg 17 cls_cnt 0 2006.173.19:12:44.10#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.19:12:44.10#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.19:12:44.10#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.19:12:44.10#ibcon#enter wrdev, iclass 38, count 0 2006.173.19:12:44.10#ibcon#first serial, iclass 38, count 0 2006.173.19:12:44.10#ibcon#enter sib2, iclass 38, count 0 2006.173.19:12:44.10#ibcon#flushed, iclass 38, count 0 2006.173.19:12:44.10#ibcon#about to write, iclass 38, count 0 2006.173.19:12:44.10#ibcon#wrote, iclass 38, count 0 2006.173.19:12:44.10#ibcon#about to read 3, iclass 38, count 0 2006.173.19:12:44.11#ibcon#read 3, iclass 38, count 0 2006.173.19:12:44.11#ibcon#about to read 4, iclass 38, count 0 2006.173.19:12:44.11#ibcon#read 4, iclass 38, count 0 2006.173.19:12:44.11#ibcon#about to read 5, iclass 38, count 0 2006.173.19:12:44.11#ibcon#read 5, iclass 38, count 0 2006.173.19:12:44.11#ibcon#about to read 6, iclass 38, count 0 2006.173.19:12:44.11#ibcon#read 6, iclass 38, count 0 2006.173.19:12:44.11#ibcon#end of sib2, iclass 38, count 0 2006.173.19:12:44.11#ibcon#*mode == 0, iclass 38, count 0 2006.173.19:12:44.11#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.19:12:44.11#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.19:12:44.12#ibcon#*before write, iclass 38, count 0 2006.173.19:12:44.12#ibcon#enter sib2, iclass 38, count 0 2006.173.19:12:44.12#ibcon#flushed, iclass 38, count 0 2006.173.19:12:44.12#ibcon#about to write, iclass 38, count 0 2006.173.19:12:44.12#ibcon#wrote, iclass 38, count 0 2006.173.19:12:44.12#ibcon#about to read 3, iclass 38, count 0 2006.173.19:12:44.15#ibcon#read 3, iclass 38, count 0 2006.173.19:12:44.15#ibcon#about to read 4, iclass 38, count 0 2006.173.19:12:44.15#ibcon#read 4, iclass 38, count 0 2006.173.19:12:44.15#ibcon#about to read 5, iclass 38, count 0 2006.173.19:12:44.15#ibcon#read 5, iclass 38, count 0 2006.173.19:12:44.15#ibcon#about to read 6, iclass 38, count 0 2006.173.19:12:44.15#ibcon#read 6, iclass 38, count 0 2006.173.19:12:44.15#ibcon#end of sib2, iclass 38, count 0 2006.173.19:12:44.15#ibcon#*after write, iclass 38, count 0 2006.173.19:12:44.15#ibcon#*before return 0, iclass 38, count 0 2006.173.19:12:44.16#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.19:12:44.16#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.19:12:44.16#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.19:12:44.16#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.19:12:44.16$vck44/va=6,3 2006.173.19:12:44.16#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.19:12:44.16#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.19:12:44.16#ibcon#ireg 11 cls_cnt 2 2006.173.19:12:44.16#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.19:12:44.20#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.19:12:44.20#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.19:12:44.20#ibcon#enter wrdev, iclass 40, count 2 2006.173.19:12:44.20#ibcon#first serial, iclass 40, count 2 2006.173.19:12:44.20#ibcon#enter sib2, iclass 40, count 2 2006.173.19:12:44.20#ibcon#flushed, iclass 40, count 2 2006.173.19:12:44.20#ibcon#about to write, iclass 40, count 2 2006.173.19:12:44.20#ibcon#wrote, iclass 40, count 2 2006.173.19:12:44.20#ibcon#about to read 3, iclass 40, count 2 2006.173.19:12:44.22#ibcon#read 3, iclass 40, count 2 2006.173.19:12:44.22#ibcon#about to read 4, iclass 40, count 2 2006.173.19:12:44.22#ibcon#read 4, iclass 40, count 2 2006.173.19:12:44.22#ibcon#about to read 5, iclass 40, count 2 2006.173.19:12:44.22#ibcon#read 5, iclass 40, count 2 2006.173.19:12:44.22#ibcon#about to read 6, iclass 40, count 2 2006.173.19:12:44.22#ibcon#read 6, iclass 40, count 2 2006.173.19:12:44.22#ibcon#end of sib2, iclass 40, count 2 2006.173.19:12:44.22#ibcon#*mode == 0, iclass 40, count 2 2006.173.19:12:44.22#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.19:12:44.22#ibcon#[25=AT06-03\r\n] 2006.173.19:12:44.22#ibcon#*before write, iclass 40, count 2 2006.173.19:12:44.22#ibcon#enter sib2, iclass 40, count 2 2006.173.19:12:44.22#ibcon#flushed, iclass 40, count 2 2006.173.19:12:44.22#ibcon#about to write, iclass 40, count 2 2006.173.19:12:44.23#ibcon#wrote, iclass 40, count 2 2006.173.19:12:44.23#ibcon#about to read 3, iclass 40, count 2 2006.173.19:12:44.25#ibcon#read 3, iclass 40, count 2 2006.173.19:12:44.25#ibcon#about to read 4, iclass 40, count 2 2006.173.19:12:44.25#ibcon#read 4, iclass 40, count 2 2006.173.19:12:44.25#ibcon#about to read 5, iclass 40, count 2 2006.173.19:12:44.25#ibcon#read 5, iclass 40, count 2 2006.173.19:12:44.25#ibcon#about to read 6, iclass 40, count 2 2006.173.19:12:44.25#ibcon#read 6, iclass 40, count 2 2006.173.19:12:44.25#ibcon#end of sib2, iclass 40, count 2 2006.173.19:12:44.25#ibcon#*after write, iclass 40, count 2 2006.173.19:12:44.25#ibcon#*before return 0, iclass 40, count 2 2006.173.19:12:44.25#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.19:12:44.25#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.19:12:44.25#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.19:12:44.26#ibcon#ireg 7 cls_cnt 0 2006.173.19:12:44.26#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.19:12:44.36#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.19:12:44.36#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.19:12:44.36#ibcon#enter wrdev, iclass 40, count 0 2006.173.19:12:44.36#ibcon#first serial, iclass 40, count 0 2006.173.19:12:44.36#ibcon#enter sib2, iclass 40, count 0 2006.173.19:12:44.36#ibcon#flushed, iclass 40, count 0 2006.173.19:12:44.36#ibcon#about to write, iclass 40, count 0 2006.173.19:12:44.36#ibcon#wrote, iclass 40, count 0 2006.173.19:12:44.36#ibcon#about to read 3, iclass 40, count 0 2006.173.19:12:44.38#ibcon#read 3, iclass 40, count 0 2006.173.19:12:44.38#ibcon#about to read 4, iclass 40, count 0 2006.173.19:12:44.38#ibcon#read 4, iclass 40, count 0 2006.173.19:12:44.38#ibcon#about to read 5, iclass 40, count 0 2006.173.19:12:44.38#ibcon#read 5, iclass 40, count 0 2006.173.19:12:44.38#ibcon#about to read 6, iclass 40, count 0 2006.173.19:12:44.38#ibcon#read 6, iclass 40, count 0 2006.173.19:12:44.38#ibcon#end of sib2, iclass 40, count 0 2006.173.19:12:44.38#ibcon#*mode == 0, iclass 40, count 0 2006.173.19:12:44.38#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.19:12:44.38#ibcon#[25=USB\r\n] 2006.173.19:12:44.38#ibcon#*before write, iclass 40, count 0 2006.173.19:12:44.39#ibcon#enter sib2, iclass 40, count 0 2006.173.19:12:44.39#ibcon#flushed, iclass 40, count 0 2006.173.19:12:44.39#ibcon#about to write, iclass 40, count 0 2006.173.19:12:44.39#ibcon#wrote, iclass 40, count 0 2006.173.19:12:44.39#ibcon#about to read 3, iclass 40, count 0 2006.173.19:12:44.41#ibcon#read 3, iclass 40, count 0 2006.173.19:12:44.41#ibcon#about to read 4, iclass 40, count 0 2006.173.19:12:44.41#ibcon#read 4, iclass 40, count 0 2006.173.19:12:44.41#ibcon#about to read 5, iclass 40, count 0 2006.173.19:12:44.41#ibcon#read 5, iclass 40, count 0 2006.173.19:12:44.41#ibcon#about to read 6, iclass 40, count 0 2006.173.19:12:44.41#ibcon#read 6, iclass 40, count 0 2006.173.19:12:44.41#ibcon#end of sib2, iclass 40, count 0 2006.173.19:12:44.41#ibcon#*after write, iclass 40, count 0 2006.173.19:12:44.41#ibcon#*before return 0, iclass 40, count 0 2006.173.19:12:44.41#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.19:12:44.42#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.19:12:44.42#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.19:12:44.42#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.19:12:44.42$vck44/valo=7,864.99 2006.173.19:12:44.42#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.19:12:44.42#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.19:12:44.42#ibcon#ireg 17 cls_cnt 0 2006.173.19:12:44.42#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.19:12:44.42#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.19:12:44.42#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.19:12:44.42#ibcon#enter wrdev, iclass 4, count 0 2006.173.19:12:44.42#ibcon#first serial, iclass 4, count 0 2006.173.19:12:44.42#ibcon#enter sib2, iclass 4, count 0 2006.173.19:12:44.42#ibcon#flushed, iclass 4, count 0 2006.173.19:12:44.42#ibcon#about to write, iclass 4, count 0 2006.173.19:12:44.42#ibcon#wrote, iclass 4, count 0 2006.173.19:12:44.42#ibcon#about to read 3, iclass 4, count 0 2006.173.19:12:44.43#ibcon#read 3, iclass 4, count 0 2006.173.19:12:44.43#ibcon#about to read 4, iclass 4, count 0 2006.173.19:12:44.43#ibcon#read 4, iclass 4, count 0 2006.173.19:12:44.43#ibcon#about to read 5, iclass 4, count 0 2006.173.19:12:44.43#ibcon#read 5, iclass 4, count 0 2006.173.19:12:44.43#ibcon#about to read 6, iclass 4, count 0 2006.173.19:12:44.43#ibcon#read 6, iclass 4, count 0 2006.173.19:12:44.43#ibcon#end of sib2, iclass 4, count 0 2006.173.19:12:44.43#ibcon#*mode == 0, iclass 4, count 0 2006.173.19:12:44.43#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.19:12:44.44#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.19:12:44.44#ibcon#*before write, iclass 4, count 0 2006.173.19:12:44.44#ibcon#enter sib2, iclass 4, count 0 2006.173.19:12:44.44#ibcon#flushed, iclass 4, count 0 2006.173.19:12:44.44#ibcon#about to write, iclass 4, count 0 2006.173.19:12:44.44#ibcon#wrote, iclass 4, count 0 2006.173.19:12:44.44#ibcon#about to read 3, iclass 4, count 0 2006.173.19:12:44.47#ibcon#read 3, iclass 4, count 0 2006.173.19:12:44.47#ibcon#about to read 4, iclass 4, count 0 2006.173.19:12:44.47#ibcon#read 4, iclass 4, count 0 2006.173.19:12:44.47#ibcon#about to read 5, iclass 4, count 0 2006.173.19:12:44.47#ibcon#read 5, iclass 4, count 0 2006.173.19:12:44.47#ibcon#about to read 6, iclass 4, count 0 2006.173.19:12:44.47#ibcon#read 6, iclass 4, count 0 2006.173.19:12:44.47#ibcon#end of sib2, iclass 4, count 0 2006.173.19:12:44.47#ibcon#*after write, iclass 4, count 0 2006.173.19:12:44.47#ibcon#*before return 0, iclass 4, count 0 2006.173.19:12:44.47#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.19:12:44.47#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.19:12:44.47#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.19:12:44.48#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.19:12:44.48$vck44/va=7,4 2006.173.19:12:44.48#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.19:12:44.48#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.19:12:44.48#ibcon#ireg 11 cls_cnt 2 2006.173.19:12:44.48#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.19:12:44.53#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.19:12:44.53#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.19:12:44.53#ibcon#enter wrdev, iclass 6, count 2 2006.173.19:12:44.53#ibcon#first serial, iclass 6, count 2 2006.173.19:12:44.53#ibcon#enter sib2, iclass 6, count 2 2006.173.19:12:44.53#ibcon#flushed, iclass 6, count 2 2006.173.19:12:44.53#ibcon#about to write, iclass 6, count 2 2006.173.19:12:44.53#ibcon#wrote, iclass 6, count 2 2006.173.19:12:44.53#ibcon#about to read 3, iclass 6, count 2 2006.173.19:12:44.55#ibcon#read 3, iclass 6, count 2 2006.173.19:12:44.55#ibcon#about to read 4, iclass 6, count 2 2006.173.19:12:44.55#ibcon#read 4, iclass 6, count 2 2006.173.19:12:44.55#ibcon#about to read 5, iclass 6, count 2 2006.173.19:12:44.55#ibcon#read 5, iclass 6, count 2 2006.173.19:12:44.55#ibcon#about to read 6, iclass 6, count 2 2006.173.19:12:44.55#ibcon#read 6, iclass 6, count 2 2006.173.19:12:44.55#ibcon#end of sib2, iclass 6, count 2 2006.173.19:12:44.55#ibcon#*mode == 0, iclass 6, count 2 2006.173.19:12:44.55#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.19:12:44.55#ibcon#[25=AT07-04\r\n] 2006.173.19:12:44.55#ibcon#*before write, iclass 6, count 2 2006.173.19:12:44.55#ibcon#enter sib2, iclass 6, count 2 2006.173.19:12:44.55#ibcon#flushed, iclass 6, count 2 2006.173.19:12:44.55#ibcon#about to write, iclass 6, count 2 2006.173.19:12:44.56#ibcon#wrote, iclass 6, count 2 2006.173.19:12:44.56#ibcon#about to read 3, iclass 6, count 2 2006.173.19:12:44.58#ibcon#read 3, iclass 6, count 2 2006.173.19:12:44.58#ibcon#about to read 4, iclass 6, count 2 2006.173.19:12:44.58#ibcon#read 4, iclass 6, count 2 2006.173.19:12:44.58#ibcon#about to read 5, iclass 6, count 2 2006.173.19:12:44.58#ibcon#read 5, iclass 6, count 2 2006.173.19:12:44.58#ibcon#about to read 6, iclass 6, count 2 2006.173.19:12:44.58#ibcon#read 6, iclass 6, count 2 2006.173.19:12:44.58#ibcon#end of sib2, iclass 6, count 2 2006.173.19:12:44.58#ibcon#*after write, iclass 6, count 2 2006.173.19:12:44.58#ibcon#*before return 0, iclass 6, count 2 2006.173.19:12:44.59#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.19:12:44.59#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.19:12:44.59#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.19:12:44.59#ibcon#ireg 7 cls_cnt 0 2006.173.19:12:44.59#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.19:12:44.70#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.19:12:44.70#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.19:12:44.70#ibcon#enter wrdev, iclass 6, count 0 2006.173.19:12:44.70#ibcon#first serial, iclass 6, count 0 2006.173.19:12:44.70#ibcon#enter sib2, iclass 6, count 0 2006.173.19:12:44.70#ibcon#flushed, iclass 6, count 0 2006.173.19:12:44.70#ibcon#about to write, iclass 6, count 0 2006.173.19:12:44.70#ibcon#wrote, iclass 6, count 0 2006.173.19:12:44.70#ibcon#about to read 3, iclass 6, count 0 2006.173.19:12:44.73#ibcon#read 3, iclass 6, count 0 2006.173.19:12:44.73#ibcon#about to read 4, iclass 6, count 0 2006.173.19:12:44.73#ibcon#read 4, iclass 6, count 0 2006.173.19:12:44.73#ibcon#about to read 5, iclass 6, count 0 2006.173.19:12:44.73#ibcon#read 5, iclass 6, count 0 2006.173.19:12:44.73#ibcon#about to read 6, iclass 6, count 0 2006.173.19:12:44.73#ibcon#read 6, iclass 6, count 0 2006.173.19:12:44.73#ibcon#end of sib2, iclass 6, count 0 2006.173.19:12:44.73#ibcon#*mode == 0, iclass 6, count 0 2006.173.19:12:44.73#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.19:12:44.73#ibcon#[25=USB\r\n] 2006.173.19:12:44.73#ibcon#*before write, iclass 6, count 0 2006.173.19:12:44.73#ibcon#enter sib2, iclass 6, count 0 2006.173.19:12:44.73#ibcon#flushed, iclass 6, count 0 2006.173.19:12:44.73#ibcon#about to write, iclass 6, count 0 2006.173.19:12:44.73#ibcon#wrote, iclass 6, count 0 2006.173.19:12:44.73#ibcon#about to read 3, iclass 6, count 0 2006.173.19:12:44.75#ibcon#read 3, iclass 6, count 0 2006.173.19:12:44.75#ibcon#about to read 4, iclass 6, count 0 2006.173.19:12:44.75#ibcon#read 4, iclass 6, count 0 2006.173.19:12:44.75#ibcon#about to read 5, iclass 6, count 0 2006.173.19:12:44.75#ibcon#read 5, iclass 6, count 0 2006.173.19:12:44.75#ibcon#about to read 6, iclass 6, count 0 2006.173.19:12:44.75#ibcon#read 6, iclass 6, count 0 2006.173.19:12:44.75#ibcon#end of sib2, iclass 6, count 0 2006.173.19:12:44.75#ibcon#*after write, iclass 6, count 0 2006.173.19:12:44.75#ibcon#*before return 0, iclass 6, count 0 2006.173.19:12:44.76#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.19:12:44.76#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.19:12:44.76#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.19:12:44.76#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.19:12:44.76$vck44/valo=8,884.99 2006.173.19:12:44.76#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.19:12:44.76#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.19:12:44.76#ibcon#ireg 17 cls_cnt 0 2006.173.19:12:44.76#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.19:12:44.76#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.19:12:44.76#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.19:12:44.76#ibcon#enter wrdev, iclass 10, count 0 2006.173.19:12:44.76#ibcon#first serial, iclass 10, count 0 2006.173.19:12:44.76#ibcon#enter sib2, iclass 10, count 0 2006.173.19:12:44.76#ibcon#flushed, iclass 10, count 0 2006.173.19:12:44.76#ibcon#about to write, iclass 10, count 0 2006.173.19:12:44.76#ibcon#wrote, iclass 10, count 0 2006.173.19:12:44.76#ibcon#about to read 3, iclass 10, count 0 2006.173.19:12:44.77#ibcon#read 3, iclass 10, count 0 2006.173.19:12:44.77#ibcon#about to read 4, iclass 10, count 0 2006.173.19:12:44.77#ibcon#read 4, iclass 10, count 0 2006.173.19:12:44.77#ibcon#about to read 5, iclass 10, count 0 2006.173.19:12:44.77#ibcon#read 5, iclass 10, count 0 2006.173.19:12:44.77#ibcon#about to read 6, iclass 10, count 0 2006.173.19:12:44.77#ibcon#read 6, iclass 10, count 0 2006.173.19:12:44.77#ibcon#end of sib2, iclass 10, count 0 2006.173.19:12:44.77#ibcon#*mode == 0, iclass 10, count 0 2006.173.19:12:44.77#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.19:12:44.77#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.19:12:44.78#ibcon#*before write, iclass 10, count 0 2006.173.19:12:44.78#ibcon#enter sib2, iclass 10, count 0 2006.173.19:12:44.78#ibcon#flushed, iclass 10, count 0 2006.173.19:12:44.78#ibcon#about to write, iclass 10, count 0 2006.173.19:12:44.78#ibcon#wrote, iclass 10, count 0 2006.173.19:12:44.78#ibcon#about to read 3, iclass 10, count 0 2006.173.19:12:44.81#ibcon#read 3, iclass 10, count 0 2006.173.19:12:44.81#ibcon#about to read 4, iclass 10, count 0 2006.173.19:12:44.81#ibcon#read 4, iclass 10, count 0 2006.173.19:12:44.81#ibcon#about to read 5, iclass 10, count 0 2006.173.19:12:44.81#ibcon#read 5, iclass 10, count 0 2006.173.19:12:44.81#ibcon#about to read 6, iclass 10, count 0 2006.173.19:12:44.81#ibcon#read 6, iclass 10, count 0 2006.173.19:12:44.81#ibcon#end of sib2, iclass 10, count 0 2006.173.19:12:44.81#ibcon#*after write, iclass 10, count 0 2006.173.19:12:44.81#ibcon#*before return 0, iclass 10, count 0 2006.173.19:12:44.82#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.19:12:44.82#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.19:12:44.82#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.19:12:44.82#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.19:12:44.82$vck44/va=8,4 2006.173.19:12:44.82#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.19:12:44.82#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.19:12:44.82#ibcon#ireg 11 cls_cnt 2 2006.173.19:12:44.82#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.19:12:44.87#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.19:12:44.87#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.19:12:44.87#ibcon#enter wrdev, iclass 12, count 2 2006.173.19:12:44.87#ibcon#first serial, iclass 12, count 2 2006.173.19:12:44.87#ibcon#enter sib2, iclass 12, count 2 2006.173.19:12:44.87#ibcon#flushed, iclass 12, count 2 2006.173.19:12:44.87#ibcon#about to write, iclass 12, count 2 2006.173.19:12:44.87#ibcon#wrote, iclass 12, count 2 2006.173.19:12:44.87#ibcon#about to read 3, iclass 12, count 2 2006.173.19:12:44.89#ibcon#read 3, iclass 12, count 2 2006.173.19:12:44.89#ibcon#about to read 4, iclass 12, count 2 2006.173.19:12:44.89#ibcon#read 4, iclass 12, count 2 2006.173.19:12:44.89#ibcon#about to read 5, iclass 12, count 2 2006.173.19:12:44.89#ibcon#read 5, iclass 12, count 2 2006.173.19:12:44.89#ibcon#about to read 6, iclass 12, count 2 2006.173.19:12:44.89#ibcon#read 6, iclass 12, count 2 2006.173.19:12:44.89#ibcon#end of sib2, iclass 12, count 2 2006.173.19:12:44.89#ibcon#*mode == 0, iclass 12, count 2 2006.173.19:12:44.89#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.19:12:44.90#ibcon#[25=AT08-04\r\n] 2006.173.19:12:44.90#ibcon#*before write, iclass 12, count 2 2006.173.19:12:44.90#ibcon#enter sib2, iclass 12, count 2 2006.173.19:12:44.90#ibcon#flushed, iclass 12, count 2 2006.173.19:12:44.90#ibcon#about to write, iclass 12, count 2 2006.173.19:12:44.90#ibcon#wrote, iclass 12, count 2 2006.173.19:12:44.90#ibcon#about to read 3, iclass 12, count 2 2006.173.19:12:44.92#ibcon#read 3, iclass 12, count 2 2006.173.19:12:44.92#ibcon#about to read 4, iclass 12, count 2 2006.173.19:12:44.92#ibcon#read 4, iclass 12, count 2 2006.173.19:12:44.92#ibcon#about to read 5, iclass 12, count 2 2006.173.19:12:44.92#ibcon#read 5, iclass 12, count 2 2006.173.19:12:44.92#ibcon#about to read 6, iclass 12, count 2 2006.173.19:12:44.92#ibcon#read 6, iclass 12, count 2 2006.173.19:12:44.92#ibcon#end of sib2, iclass 12, count 2 2006.173.19:12:44.92#ibcon#*after write, iclass 12, count 2 2006.173.19:12:44.92#ibcon#*before return 0, iclass 12, count 2 2006.173.19:12:44.92#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.19:12:44.93#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.19:12:44.93#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.19:12:44.93#ibcon#ireg 7 cls_cnt 0 2006.173.19:12:44.93#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.19:12:45.04#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.19:12:45.04#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.19:12:45.04#ibcon#enter wrdev, iclass 12, count 0 2006.173.19:12:45.04#ibcon#first serial, iclass 12, count 0 2006.173.19:12:45.04#ibcon#enter sib2, iclass 12, count 0 2006.173.19:12:45.04#ibcon#flushed, iclass 12, count 0 2006.173.19:12:45.04#ibcon#about to write, iclass 12, count 0 2006.173.19:12:45.04#ibcon#wrote, iclass 12, count 0 2006.173.19:12:45.04#ibcon#about to read 3, iclass 12, count 0 2006.173.19:12:45.06#ibcon#read 3, iclass 12, count 0 2006.173.19:12:45.06#ibcon#about to read 4, iclass 12, count 0 2006.173.19:12:45.06#ibcon#read 4, iclass 12, count 0 2006.173.19:12:45.06#ibcon#about to read 5, iclass 12, count 0 2006.173.19:12:45.06#ibcon#read 5, iclass 12, count 0 2006.173.19:12:45.06#ibcon#about to read 6, iclass 12, count 0 2006.173.19:12:45.06#ibcon#read 6, iclass 12, count 0 2006.173.19:12:45.06#ibcon#end of sib2, iclass 12, count 0 2006.173.19:12:45.06#ibcon#*mode == 0, iclass 12, count 0 2006.173.19:12:45.06#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.19:12:45.06#ibcon#[25=USB\r\n] 2006.173.19:12:45.06#ibcon#*before write, iclass 12, count 0 2006.173.19:12:45.06#ibcon#enter sib2, iclass 12, count 0 2006.173.19:12:45.06#ibcon#flushed, iclass 12, count 0 2006.173.19:12:45.06#ibcon#about to write, iclass 12, count 0 2006.173.19:12:45.07#ibcon#wrote, iclass 12, count 0 2006.173.19:12:45.07#ibcon#about to read 3, iclass 12, count 0 2006.173.19:12:45.09#ibcon#read 3, iclass 12, count 0 2006.173.19:12:45.09#ibcon#about to read 4, iclass 12, count 0 2006.173.19:12:45.09#ibcon#read 4, iclass 12, count 0 2006.173.19:12:45.09#ibcon#about to read 5, iclass 12, count 0 2006.173.19:12:45.09#ibcon#read 5, iclass 12, count 0 2006.173.19:12:45.09#ibcon#about to read 6, iclass 12, count 0 2006.173.19:12:45.09#ibcon#read 6, iclass 12, count 0 2006.173.19:12:45.09#ibcon#end of sib2, iclass 12, count 0 2006.173.19:12:45.09#ibcon#*after write, iclass 12, count 0 2006.173.19:12:45.09#ibcon#*before return 0, iclass 12, count 0 2006.173.19:12:45.10#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.19:12:45.10#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.19:12:45.10#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.19:12:45.10#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.19:12:45.10$vck44/vblo=1,629.99 2006.173.19:12:45.10#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.19:12:45.10#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.19:12:45.10#ibcon#ireg 17 cls_cnt 0 2006.173.19:12:45.10#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.19:12:45.10#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.19:12:45.10#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.19:12:45.10#ibcon#enter wrdev, iclass 14, count 0 2006.173.19:12:45.10#ibcon#first serial, iclass 14, count 0 2006.173.19:12:45.10#ibcon#enter sib2, iclass 14, count 0 2006.173.19:12:45.10#ibcon#flushed, iclass 14, count 0 2006.173.19:12:45.10#ibcon#about to write, iclass 14, count 0 2006.173.19:12:45.10#ibcon#wrote, iclass 14, count 0 2006.173.19:12:45.10#ibcon#about to read 3, iclass 14, count 0 2006.173.19:12:45.11#ibcon#read 3, iclass 14, count 0 2006.173.19:12:45.11#ibcon#about to read 4, iclass 14, count 0 2006.173.19:12:45.11#ibcon#read 4, iclass 14, count 0 2006.173.19:12:45.11#ibcon#about to read 5, iclass 14, count 0 2006.173.19:12:45.11#ibcon#read 5, iclass 14, count 0 2006.173.19:12:45.11#ibcon#about to read 6, iclass 14, count 0 2006.173.19:12:45.11#ibcon#read 6, iclass 14, count 0 2006.173.19:12:45.11#ibcon#end of sib2, iclass 14, count 0 2006.173.19:12:45.11#ibcon#*mode == 0, iclass 14, count 0 2006.173.19:12:45.11#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.19:12:45.11#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.19:12:45.11#ibcon#*before write, iclass 14, count 0 2006.173.19:12:45.12#ibcon#enter sib2, iclass 14, count 0 2006.173.19:12:45.12#ibcon#flushed, iclass 14, count 0 2006.173.19:12:45.12#ibcon#about to write, iclass 14, count 0 2006.173.19:12:45.12#ibcon#wrote, iclass 14, count 0 2006.173.19:12:45.12#ibcon#about to read 3, iclass 14, count 0 2006.173.19:12:45.15#ibcon#read 3, iclass 14, count 0 2006.173.19:12:45.15#ibcon#about to read 4, iclass 14, count 0 2006.173.19:12:45.15#ibcon#read 4, iclass 14, count 0 2006.173.19:12:45.15#ibcon#about to read 5, iclass 14, count 0 2006.173.19:12:45.15#ibcon#read 5, iclass 14, count 0 2006.173.19:12:45.15#ibcon#about to read 6, iclass 14, count 0 2006.173.19:12:45.15#ibcon#read 6, iclass 14, count 0 2006.173.19:12:45.15#ibcon#end of sib2, iclass 14, count 0 2006.173.19:12:45.15#ibcon#*after write, iclass 14, count 0 2006.173.19:12:45.15#ibcon#*before return 0, iclass 14, count 0 2006.173.19:12:45.15#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.19:12:45.16#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.19:12:45.16#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.19:12:45.16#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.19:12:45.16$vck44/vb=1,4 2006.173.19:12:45.16#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.19:12:45.16#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.19:12:45.16#ibcon#ireg 11 cls_cnt 2 2006.173.19:12:45.16#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.19:12:45.16#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.19:12:45.16#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.19:12:45.16#ibcon#enter wrdev, iclass 16, count 2 2006.173.19:12:45.16#ibcon#first serial, iclass 16, count 2 2006.173.19:12:45.16#ibcon#enter sib2, iclass 16, count 2 2006.173.19:12:45.16#ibcon#flushed, iclass 16, count 2 2006.173.19:12:45.16#ibcon#about to write, iclass 16, count 2 2006.173.19:12:45.16#ibcon#wrote, iclass 16, count 2 2006.173.19:12:45.16#ibcon#about to read 3, iclass 16, count 2 2006.173.19:12:45.17#ibcon#read 3, iclass 16, count 2 2006.173.19:12:45.17#ibcon#about to read 4, iclass 16, count 2 2006.173.19:12:45.17#ibcon#read 4, iclass 16, count 2 2006.173.19:12:45.17#ibcon#about to read 5, iclass 16, count 2 2006.173.19:12:45.17#ibcon#read 5, iclass 16, count 2 2006.173.19:12:45.17#ibcon#about to read 6, iclass 16, count 2 2006.173.19:12:45.17#ibcon#read 6, iclass 16, count 2 2006.173.19:12:45.17#ibcon#end of sib2, iclass 16, count 2 2006.173.19:12:45.17#ibcon#*mode == 0, iclass 16, count 2 2006.173.19:12:45.17#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.19:12:45.17#ibcon#[27=AT01-04\r\n] 2006.173.19:12:45.17#ibcon#*before write, iclass 16, count 2 2006.173.19:12:45.17#ibcon#enter sib2, iclass 16, count 2 2006.173.19:12:45.17#ibcon#flushed, iclass 16, count 2 2006.173.19:12:45.18#ibcon#about to write, iclass 16, count 2 2006.173.19:12:45.18#ibcon#wrote, iclass 16, count 2 2006.173.19:12:45.18#ibcon#about to read 3, iclass 16, count 2 2006.173.19:12:45.20#ibcon#read 3, iclass 16, count 2 2006.173.19:12:45.20#ibcon#about to read 4, iclass 16, count 2 2006.173.19:12:45.20#ibcon#read 4, iclass 16, count 2 2006.173.19:12:45.20#ibcon#about to read 5, iclass 16, count 2 2006.173.19:12:45.20#ibcon#read 5, iclass 16, count 2 2006.173.19:12:45.20#ibcon#about to read 6, iclass 16, count 2 2006.173.19:12:45.20#ibcon#read 6, iclass 16, count 2 2006.173.19:12:45.20#ibcon#end of sib2, iclass 16, count 2 2006.173.19:12:45.20#ibcon#*after write, iclass 16, count 2 2006.173.19:12:45.20#ibcon#*before return 0, iclass 16, count 2 2006.173.19:12:45.20#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.19:12:45.21#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.19:12:45.21#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.19:12:45.21#ibcon#ireg 7 cls_cnt 0 2006.173.19:12:45.21#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.19:12:45.32#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.19:12:45.32#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.19:12:45.32#ibcon#enter wrdev, iclass 16, count 0 2006.173.19:12:45.32#ibcon#first serial, iclass 16, count 0 2006.173.19:12:45.32#ibcon#enter sib2, iclass 16, count 0 2006.173.19:12:45.32#ibcon#flushed, iclass 16, count 0 2006.173.19:12:45.32#ibcon#about to write, iclass 16, count 0 2006.173.19:12:45.32#ibcon#wrote, iclass 16, count 0 2006.173.19:12:45.32#ibcon#about to read 3, iclass 16, count 0 2006.173.19:12:45.34#ibcon#read 3, iclass 16, count 0 2006.173.19:12:45.34#ibcon#about to read 4, iclass 16, count 0 2006.173.19:12:45.34#ibcon#read 4, iclass 16, count 0 2006.173.19:12:45.34#ibcon#about to read 5, iclass 16, count 0 2006.173.19:12:45.34#ibcon#read 5, iclass 16, count 0 2006.173.19:12:45.34#ibcon#about to read 6, iclass 16, count 0 2006.173.19:12:45.34#ibcon#read 6, iclass 16, count 0 2006.173.19:12:45.34#ibcon#end of sib2, iclass 16, count 0 2006.173.19:12:45.34#ibcon#*mode == 0, iclass 16, count 0 2006.173.19:12:45.34#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.19:12:45.34#ibcon#[27=USB\r\n] 2006.173.19:12:45.34#ibcon#*before write, iclass 16, count 0 2006.173.19:12:45.34#ibcon#enter sib2, iclass 16, count 0 2006.173.19:12:45.34#ibcon#flushed, iclass 16, count 0 2006.173.19:12:45.34#ibcon#about to write, iclass 16, count 0 2006.173.19:12:45.35#ibcon#wrote, iclass 16, count 0 2006.173.19:12:45.35#ibcon#about to read 3, iclass 16, count 0 2006.173.19:12:45.37#ibcon#read 3, iclass 16, count 0 2006.173.19:12:45.37#ibcon#about to read 4, iclass 16, count 0 2006.173.19:12:45.37#ibcon#read 4, iclass 16, count 0 2006.173.19:12:45.37#ibcon#about to read 5, iclass 16, count 0 2006.173.19:12:45.37#ibcon#read 5, iclass 16, count 0 2006.173.19:12:45.37#ibcon#about to read 6, iclass 16, count 0 2006.173.19:12:45.37#ibcon#read 6, iclass 16, count 0 2006.173.19:12:45.37#ibcon#end of sib2, iclass 16, count 0 2006.173.19:12:45.37#ibcon#*after write, iclass 16, count 0 2006.173.19:12:45.37#ibcon#*before return 0, iclass 16, count 0 2006.173.19:12:45.37#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.19:12:45.37#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.19:12:45.37#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.19:12:45.37#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.19:12:45.38$vck44/vblo=2,634.99 2006.173.19:12:45.38#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.19:12:45.38#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.19:12:45.38#ibcon#ireg 17 cls_cnt 0 2006.173.19:12:45.38#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.19:12:45.38#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.19:12:45.38#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.19:12:45.38#ibcon#enter wrdev, iclass 18, count 0 2006.173.19:12:45.38#ibcon#first serial, iclass 18, count 0 2006.173.19:12:45.38#ibcon#enter sib2, iclass 18, count 0 2006.173.19:12:45.38#ibcon#flushed, iclass 18, count 0 2006.173.19:12:45.38#ibcon#about to write, iclass 18, count 0 2006.173.19:12:45.38#ibcon#wrote, iclass 18, count 0 2006.173.19:12:45.38#ibcon#about to read 3, iclass 18, count 0 2006.173.19:12:45.39#ibcon#read 3, iclass 18, count 0 2006.173.19:12:45.39#ibcon#about to read 4, iclass 18, count 0 2006.173.19:12:45.39#ibcon#read 4, iclass 18, count 0 2006.173.19:12:45.39#ibcon#about to read 5, iclass 18, count 0 2006.173.19:12:45.39#ibcon#read 5, iclass 18, count 0 2006.173.19:12:45.39#ibcon#about to read 6, iclass 18, count 0 2006.173.19:12:45.39#ibcon#read 6, iclass 18, count 0 2006.173.19:12:45.39#ibcon#end of sib2, iclass 18, count 0 2006.173.19:12:45.39#ibcon#*mode == 0, iclass 18, count 0 2006.173.19:12:45.39#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.19:12:45.39#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.19:12:45.39#ibcon#*before write, iclass 18, count 0 2006.173.19:12:45.39#ibcon#enter sib2, iclass 18, count 0 2006.173.19:12:45.39#ibcon#flushed, iclass 18, count 0 2006.173.19:12:45.39#ibcon#about to write, iclass 18, count 0 2006.173.19:12:45.40#ibcon#wrote, iclass 18, count 0 2006.173.19:12:45.40#ibcon#about to read 3, iclass 18, count 0 2006.173.19:12:45.43#ibcon#read 3, iclass 18, count 0 2006.173.19:12:45.43#ibcon#about to read 4, iclass 18, count 0 2006.173.19:12:45.43#ibcon#read 4, iclass 18, count 0 2006.173.19:12:45.43#ibcon#about to read 5, iclass 18, count 0 2006.173.19:12:45.43#ibcon#read 5, iclass 18, count 0 2006.173.19:12:45.43#ibcon#about to read 6, iclass 18, count 0 2006.173.19:12:45.43#ibcon#read 6, iclass 18, count 0 2006.173.19:12:45.43#ibcon#end of sib2, iclass 18, count 0 2006.173.19:12:45.43#ibcon#*after write, iclass 18, count 0 2006.173.19:12:45.43#ibcon#*before return 0, iclass 18, count 0 2006.173.19:12:45.43#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.19:12:45.43#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.19:12:45.43#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.19:12:45.44#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.19:12:45.44$vck44/vb=2,4 2006.173.19:12:45.44#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.19:12:45.44#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.19:12:45.44#ibcon#ireg 11 cls_cnt 2 2006.173.19:12:45.44#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.19:12:45.48#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.19:12:45.48#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.19:12:45.48#ibcon#enter wrdev, iclass 20, count 2 2006.173.19:12:45.48#ibcon#first serial, iclass 20, count 2 2006.173.19:12:45.48#ibcon#enter sib2, iclass 20, count 2 2006.173.19:12:45.48#ibcon#flushed, iclass 20, count 2 2006.173.19:12:45.48#ibcon#about to write, iclass 20, count 2 2006.173.19:12:45.48#ibcon#wrote, iclass 20, count 2 2006.173.19:12:45.48#ibcon#about to read 3, iclass 20, count 2 2006.173.19:12:45.50#ibcon#read 3, iclass 20, count 2 2006.173.19:12:45.50#ibcon#about to read 4, iclass 20, count 2 2006.173.19:12:45.50#ibcon#read 4, iclass 20, count 2 2006.173.19:12:45.50#ibcon#about to read 5, iclass 20, count 2 2006.173.19:12:45.50#ibcon#read 5, iclass 20, count 2 2006.173.19:12:45.50#ibcon#about to read 6, iclass 20, count 2 2006.173.19:12:45.50#ibcon#read 6, iclass 20, count 2 2006.173.19:12:45.50#ibcon#end of sib2, iclass 20, count 2 2006.173.19:12:45.50#ibcon#*mode == 0, iclass 20, count 2 2006.173.19:12:45.50#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.19:12:45.50#ibcon#[27=AT02-04\r\n] 2006.173.19:12:45.50#ibcon#*before write, iclass 20, count 2 2006.173.19:12:45.50#ibcon#enter sib2, iclass 20, count 2 2006.173.19:12:45.51#ibcon#flushed, iclass 20, count 2 2006.173.19:12:45.51#ibcon#about to write, iclass 20, count 2 2006.173.19:12:45.51#ibcon#wrote, iclass 20, count 2 2006.173.19:12:45.51#ibcon#about to read 3, iclass 20, count 2 2006.173.19:12:45.53#ibcon#read 3, iclass 20, count 2 2006.173.19:12:45.53#ibcon#about to read 4, iclass 20, count 2 2006.173.19:12:45.53#ibcon#read 4, iclass 20, count 2 2006.173.19:12:45.53#ibcon#about to read 5, iclass 20, count 2 2006.173.19:12:45.53#ibcon#read 5, iclass 20, count 2 2006.173.19:12:45.53#ibcon#about to read 6, iclass 20, count 2 2006.173.19:12:45.53#ibcon#read 6, iclass 20, count 2 2006.173.19:12:45.53#ibcon#end of sib2, iclass 20, count 2 2006.173.19:12:45.53#ibcon#*after write, iclass 20, count 2 2006.173.19:12:45.53#ibcon#*before return 0, iclass 20, count 2 2006.173.19:12:45.53#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.19:12:45.53#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.19:12:45.53#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.19:12:45.54#ibcon#ireg 7 cls_cnt 0 2006.173.19:12:45.54#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.19:12:45.64#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.19:12:45.64#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.19:12:45.64#ibcon#enter wrdev, iclass 20, count 0 2006.173.19:12:45.64#ibcon#first serial, iclass 20, count 0 2006.173.19:12:45.64#ibcon#enter sib2, iclass 20, count 0 2006.173.19:12:45.64#ibcon#flushed, iclass 20, count 0 2006.173.19:12:45.64#ibcon#about to write, iclass 20, count 0 2006.173.19:12:45.64#ibcon#wrote, iclass 20, count 0 2006.173.19:12:45.64#ibcon#about to read 3, iclass 20, count 0 2006.173.19:12:45.66#ibcon#read 3, iclass 20, count 0 2006.173.19:12:45.66#ibcon#about to read 4, iclass 20, count 0 2006.173.19:12:45.66#ibcon#read 4, iclass 20, count 0 2006.173.19:12:45.66#ibcon#about to read 5, iclass 20, count 0 2006.173.19:12:45.66#ibcon#read 5, iclass 20, count 0 2006.173.19:12:45.66#ibcon#about to read 6, iclass 20, count 0 2006.173.19:12:45.66#ibcon#read 6, iclass 20, count 0 2006.173.19:12:45.66#ibcon#end of sib2, iclass 20, count 0 2006.173.19:12:45.66#ibcon#*mode == 0, iclass 20, count 0 2006.173.19:12:45.66#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.19:12:45.66#ibcon#[27=USB\r\n] 2006.173.19:12:45.66#ibcon#*before write, iclass 20, count 0 2006.173.19:12:45.66#ibcon#enter sib2, iclass 20, count 0 2006.173.19:12:45.66#ibcon#flushed, iclass 20, count 0 2006.173.19:12:45.66#ibcon#about to write, iclass 20, count 0 2006.173.19:12:45.67#ibcon#wrote, iclass 20, count 0 2006.173.19:12:45.67#ibcon#about to read 3, iclass 20, count 0 2006.173.19:12:45.69#ibcon#read 3, iclass 20, count 0 2006.173.19:12:45.69#ibcon#about to read 4, iclass 20, count 0 2006.173.19:12:45.69#ibcon#read 4, iclass 20, count 0 2006.173.19:12:45.69#ibcon#about to read 5, iclass 20, count 0 2006.173.19:12:45.69#ibcon#read 5, iclass 20, count 0 2006.173.19:12:45.69#ibcon#about to read 6, iclass 20, count 0 2006.173.19:12:45.69#ibcon#read 6, iclass 20, count 0 2006.173.19:12:45.69#ibcon#end of sib2, iclass 20, count 0 2006.173.19:12:45.69#ibcon#*after write, iclass 20, count 0 2006.173.19:12:45.69#ibcon#*before return 0, iclass 20, count 0 2006.173.19:12:45.69#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.19:12:45.70#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.19:12:45.70#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.19:12:45.70#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.19:12:45.70$vck44/vblo=3,649.99 2006.173.19:12:45.70#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.19:12:45.70#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.19:12:45.70#ibcon#ireg 17 cls_cnt 0 2006.173.19:12:45.70#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.19:12:45.70#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.19:12:45.70#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.19:12:45.70#ibcon#enter wrdev, iclass 22, count 0 2006.173.19:12:45.70#ibcon#first serial, iclass 22, count 0 2006.173.19:12:45.70#ibcon#enter sib2, iclass 22, count 0 2006.173.19:12:45.70#ibcon#flushed, iclass 22, count 0 2006.173.19:12:45.70#ibcon#about to write, iclass 22, count 0 2006.173.19:12:45.70#ibcon#wrote, iclass 22, count 0 2006.173.19:12:45.70#ibcon#about to read 3, iclass 22, count 0 2006.173.19:12:45.71#ibcon#read 3, iclass 22, count 0 2006.173.19:12:45.71#ibcon#about to read 4, iclass 22, count 0 2006.173.19:12:45.71#ibcon#read 4, iclass 22, count 0 2006.173.19:12:45.71#ibcon#about to read 5, iclass 22, count 0 2006.173.19:12:45.71#ibcon#read 5, iclass 22, count 0 2006.173.19:12:45.71#ibcon#about to read 6, iclass 22, count 0 2006.173.19:12:45.71#ibcon#read 6, iclass 22, count 0 2006.173.19:12:45.71#ibcon#end of sib2, iclass 22, count 0 2006.173.19:12:45.71#ibcon#*mode == 0, iclass 22, count 0 2006.173.19:12:45.71#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.19:12:45.71#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.19:12:45.72#ibcon#*before write, iclass 22, count 0 2006.173.19:12:45.72#ibcon#enter sib2, iclass 22, count 0 2006.173.19:12:45.72#ibcon#flushed, iclass 22, count 0 2006.173.19:12:45.72#ibcon#about to write, iclass 22, count 0 2006.173.19:12:45.72#ibcon#wrote, iclass 22, count 0 2006.173.19:12:45.72#ibcon#about to read 3, iclass 22, count 0 2006.173.19:12:45.75#ibcon#read 3, iclass 22, count 0 2006.173.19:12:45.75#ibcon#about to read 4, iclass 22, count 0 2006.173.19:12:45.75#ibcon#read 4, iclass 22, count 0 2006.173.19:12:45.75#ibcon#about to read 5, iclass 22, count 0 2006.173.19:12:45.75#ibcon#read 5, iclass 22, count 0 2006.173.19:12:45.75#ibcon#about to read 6, iclass 22, count 0 2006.173.19:12:45.75#ibcon#read 6, iclass 22, count 0 2006.173.19:12:45.75#ibcon#end of sib2, iclass 22, count 0 2006.173.19:12:45.76#ibcon#*after write, iclass 22, count 0 2006.173.19:12:45.76#ibcon#*before return 0, iclass 22, count 0 2006.173.19:12:45.76#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.19:12:45.76#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.19:12:45.76#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.19:12:45.76#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.19:12:45.76$vck44/vb=3,4 2006.173.19:12:45.76#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.19:12:45.76#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.19:12:45.76#ibcon#ireg 11 cls_cnt 2 2006.173.19:12:45.76#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.19:12:45.81#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.19:12:45.81#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.19:12:45.81#ibcon#enter wrdev, iclass 24, count 2 2006.173.19:12:45.81#ibcon#first serial, iclass 24, count 2 2006.173.19:12:45.81#ibcon#enter sib2, iclass 24, count 2 2006.173.19:12:45.81#ibcon#flushed, iclass 24, count 2 2006.173.19:12:45.81#ibcon#about to write, iclass 24, count 2 2006.173.19:12:45.82#ibcon#wrote, iclass 24, count 2 2006.173.19:12:45.82#ibcon#about to read 3, iclass 24, count 2 2006.173.19:12:45.83#ibcon#read 3, iclass 24, count 2 2006.173.19:12:45.83#ibcon#about to read 4, iclass 24, count 2 2006.173.19:12:45.83#ibcon#read 4, iclass 24, count 2 2006.173.19:12:45.83#ibcon#about to read 5, iclass 24, count 2 2006.173.19:12:45.83#ibcon#read 5, iclass 24, count 2 2006.173.19:12:45.83#ibcon#about to read 6, iclass 24, count 2 2006.173.19:12:45.83#ibcon#read 6, iclass 24, count 2 2006.173.19:12:45.83#ibcon#end of sib2, iclass 24, count 2 2006.173.19:12:45.84#ibcon#*mode == 0, iclass 24, count 2 2006.173.19:12:45.84#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.19:12:45.84#ibcon#[27=AT03-04\r\n] 2006.173.19:12:45.84#ibcon#*before write, iclass 24, count 2 2006.173.19:12:45.84#ibcon#enter sib2, iclass 24, count 2 2006.173.19:12:45.84#ibcon#flushed, iclass 24, count 2 2006.173.19:12:45.84#ibcon#about to write, iclass 24, count 2 2006.173.19:12:45.84#ibcon#wrote, iclass 24, count 2 2006.173.19:12:45.84#ibcon#about to read 3, iclass 24, count 2 2006.173.19:12:45.86#ibcon#read 3, iclass 24, count 2 2006.173.19:12:45.86#ibcon#about to read 4, iclass 24, count 2 2006.173.19:12:45.86#ibcon#read 4, iclass 24, count 2 2006.173.19:12:45.86#ibcon#about to read 5, iclass 24, count 2 2006.173.19:12:45.86#ibcon#read 5, iclass 24, count 2 2006.173.19:12:45.86#ibcon#about to read 6, iclass 24, count 2 2006.173.19:12:45.86#ibcon#read 6, iclass 24, count 2 2006.173.19:12:45.86#ibcon#end of sib2, iclass 24, count 2 2006.173.19:12:45.86#ibcon#*after write, iclass 24, count 2 2006.173.19:12:45.86#ibcon#*before return 0, iclass 24, count 2 2006.173.19:12:45.86#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.19:12:45.87#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.19:12:45.87#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.19:12:45.87#ibcon#ireg 7 cls_cnt 0 2006.173.19:12:45.87#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.19:12:45.98#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.19:12:45.98#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.19:12:45.98#ibcon#enter wrdev, iclass 24, count 0 2006.173.19:12:45.98#ibcon#first serial, iclass 24, count 0 2006.173.19:12:45.98#ibcon#enter sib2, iclass 24, count 0 2006.173.19:12:45.98#ibcon#flushed, iclass 24, count 0 2006.173.19:12:45.98#ibcon#about to write, iclass 24, count 0 2006.173.19:12:45.98#ibcon#wrote, iclass 24, count 0 2006.173.19:12:45.98#ibcon#about to read 3, iclass 24, count 0 2006.173.19:12:46.00#ibcon#read 3, iclass 24, count 0 2006.173.19:12:46.00#ibcon#about to read 4, iclass 24, count 0 2006.173.19:12:46.00#ibcon#read 4, iclass 24, count 0 2006.173.19:12:46.00#ibcon#about to read 5, iclass 24, count 0 2006.173.19:12:46.00#ibcon#read 5, iclass 24, count 0 2006.173.19:12:46.00#ibcon#about to read 6, iclass 24, count 0 2006.173.19:12:46.00#ibcon#read 6, iclass 24, count 0 2006.173.19:12:46.00#ibcon#end of sib2, iclass 24, count 0 2006.173.19:12:46.00#ibcon#*mode == 0, iclass 24, count 0 2006.173.19:12:46.00#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.19:12:46.01#ibcon#[27=USB\r\n] 2006.173.19:12:46.01#ibcon#*before write, iclass 24, count 0 2006.173.19:12:46.01#ibcon#enter sib2, iclass 24, count 0 2006.173.19:12:46.01#ibcon#flushed, iclass 24, count 0 2006.173.19:12:46.01#ibcon#about to write, iclass 24, count 0 2006.173.19:12:46.01#ibcon#wrote, iclass 24, count 0 2006.173.19:12:46.01#ibcon#about to read 3, iclass 24, count 0 2006.173.19:12:46.03#ibcon#read 3, iclass 24, count 0 2006.173.19:12:46.03#ibcon#about to read 4, iclass 24, count 0 2006.173.19:12:46.03#ibcon#read 4, iclass 24, count 0 2006.173.19:12:46.03#ibcon#about to read 5, iclass 24, count 0 2006.173.19:12:46.03#ibcon#read 5, iclass 24, count 0 2006.173.19:12:46.03#ibcon#about to read 6, iclass 24, count 0 2006.173.19:12:46.03#ibcon#read 6, iclass 24, count 0 2006.173.19:12:46.03#ibcon#end of sib2, iclass 24, count 0 2006.173.19:12:46.03#ibcon#*after write, iclass 24, count 0 2006.173.19:12:46.03#ibcon#*before return 0, iclass 24, count 0 2006.173.19:12:46.03#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.19:12:46.04#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.19:12:46.04#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.19:12:46.04#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.19:12:46.04$vck44/vblo=4,679.99 2006.173.19:12:46.04#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.19:12:46.04#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.19:12:46.04#ibcon#ireg 17 cls_cnt 0 2006.173.19:12:46.04#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.19:12:46.04#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.19:12:46.04#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.19:12:46.04#ibcon#enter wrdev, iclass 26, count 0 2006.173.19:12:46.04#ibcon#first serial, iclass 26, count 0 2006.173.19:12:46.04#ibcon#enter sib2, iclass 26, count 0 2006.173.19:12:46.04#ibcon#flushed, iclass 26, count 0 2006.173.19:12:46.04#ibcon#about to write, iclass 26, count 0 2006.173.19:12:46.04#ibcon#wrote, iclass 26, count 0 2006.173.19:12:46.04#ibcon#about to read 3, iclass 26, count 0 2006.173.19:12:46.05#ibcon#read 3, iclass 26, count 0 2006.173.19:12:46.05#ibcon#about to read 4, iclass 26, count 0 2006.173.19:12:46.05#ibcon#read 4, iclass 26, count 0 2006.173.19:12:46.05#ibcon#about to read 5, iclass 26, count 0 2006.173.19:12:46.05#ibcon#read 5, iclass 26, count 0 2006.173.19:12:46.05#ibcon#about to read 6, iclass 26, count 0 2006.173.19:12:46.05#ibcon#read 6, iclass 26, count 0 2006.173.19:12:46.05#ibcon#end of sib2, iclass 26, count 0 2006.173.19:12:46.05#ibcon#*mode == 0, iclass 26, count 0 2006.173.19:12:46.05#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.19:12:46.06#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.19:12:46.06#ibcon#*before write, iclass 26, count 0 2006.173.19:12:46.06#ibcon#enter sib2, iclass 26, count 0 2006.173.19:12:46.06#ibcon#flushed, iclass 26, count 0 2006.173.19:12:46.06#ibcon#about to write, iclass 26, count 0 2006.173.19:12:46.06#ibcon#wrote, iclass 26, count 0 2006.173.19:12:46.06#ibcon#about to read 3, iclass 26, count 0 2006.173.19:12:46.09#ibcon#read 3, iclass 26, count 0 2006.173.19:12:46.09#ibcon#about to read 4, iclass 26, count 0 2006.173.19:12:46.09#ibcon#read 4, iclass 26, count 0 2006.173.19:12:46.09#ibcon#about to read 5, iclass 26, count 0 2006.173.19:12:46.09#ibcon#read 5, iclass 26, count 0 2006.173.19:12:46.09#ibcon#about to read 6, iclass 26, count 0 2006.173.19:12:46.09#ibcon#read 6, iclass 26, count 0 2006.173.19:12:46.09#ibcon#end of sib2, iclass 26, count 0 2006.173.19:12:46.09#ibcon#*after write, iclass 26, count 0 2006.173.19:12:46.09#ibcon#*before return 0, iclass 26, count 0 2006.173.19:12:46.09#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.19:12:46.09#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.19:12:46.10#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.19:12:46.10#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.19:12:46.10$vck44/vb=4,4 2006.173.19:12:46.10#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.19:12:46.10#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.19:12:46.10#ibcon#ireg 11 cls_cnt 2 2006.173.19:12:46.10#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.19:12:46.15#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.19:12:46.15#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.19:12:46.15#ibcon#enter wrdev, iclass 28, count 2 2006.173.19:12:46.15#ibcon#first serial, iclass 28, count 2 2006.173.19:12:46.15#ibcon#enter sib2, iclass 28, count 2 2006.173.19:12:46.15#ibcon#flushed, iclass 28, count 2 2006.173.19:12:46.15#ibcon#about to write, iclass 28, count 2 2006.173.19:12:46.15#ibcon#wrote, iclass 28, count 2 2006.173.19:12:46.15#ibcon#about to read 3, iclass 28, count 2 2006.173.19:12:46.17#ibcon#read 3, iclass 28, count 2 2006.173.19:12:46.17#ibcon#about to read 4, iclass 28, count 2 2006.173.19:12:46.17#ibcon#read 4, iclass 28, count 2 2006.173.19:12:46.17#ibcon#about to read 5, iclass 28, count 2 2006.173.19:12:46.17#ibcon#read 5, iclass 28, count 2 2006.173.19:12:46.17#ibcon#about to read 6, iclass 28, count 2 2006.173.19:12:46.17#ibcon#read 6, iclass 28, count 2 2006.173.19:12:46.17#ibcon#end of sib2, iclass 28, count 2 2006.173.19:12:46.17#ibcon#*mode == 0, iclass 28, count 2 2006.173.19:12:46.17#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.19:12:46.17#ibcon#[27=AT04-04\r\n] 2006.173.19:12:46.17#ibcon#*before write, iclass 28, count 2 2006.173.19:12:46.17#ibcon#enter sib2, iclass 28, count 2 2006.173.19:12:46.17#ibcon#flushed, iclass 28, count 2 2006.173.19:12:46.17#ibcon#about to write, iclass 28, count 2 2006.173.19:12:46.18#ibcon#wrote, iclass 28, count 2 2006.173.19:12:46.18#ibcon#about to read 3, iclass 28, count 2 2006.173.19:12:46.20#ibcon#read 3, iclass 28, count 2 2006.173.19:12:46.20#ibcon#about to read 4, iclass 28, count 2 2006.173.19:12:46.20#ibcon#read 4, iclass 28, count 2 2006.173.19:12:46.20#ibcon#about to read 5, iclass 28, count 2 2006.173.19:12:46.20#ibcon#read 5, iclass 28, count 2 2006.173.19:12:46.20#ibcon#about to read 6, iclass 28, count 2 2006.173.19:12:46.20#ibcon#read 6, iclass 28, count 2 2006.173.19:12:46.20#ibcon#end of sib2, iclass 28, count 2 2006.173.19:12:46.20#ibcon#*after write, iclass 28, count 2 2006.173.19:12:46.20#ibcon#*before return 0, iclass 28, count 2 2006.173.19:12:46.20#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.19:12:46.20#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.19:12:46.20#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.19:12:46.20#ibcon#ireg 7 cls_cnt 0 2006.173.19:12:46.21#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.19:12:46.32#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.19:12:46.32#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.19:12:46.32#ibcon#enter wrdev, iclass 28, count 0 2006.173.19:12:46.32#ibcon#first serial, iclass 28, count 0 2006.173.19:12:46.32#ibcon#enter sib2, iclass 28, count 0 2006.173.19:12:46.32#ibcon#flushed, iclass 28, count 0 2006.173.19:12:46.32#ibcon#about to write, iclass 28, count 0 2006.173.19:12:46.32#ibcon#wrote, iclass 28, count 0 2006.173.19:12:46.32#ibcon#about to read 3, iclass 28, count 0 2006.173.19:12:46.34#ibcon#read 3, iclass 28, count 0 2006.173.19:12:46.34#ibcon#about to read 4, iclass 28, count 0 2006.173.19:12:46.34#ibcon#read 4, iclass 28, count 0 2006.173.19:12:46.34#ibcon#about to read 5, iclass 28, count 0 2006.173.19:12:46.34#ibcon#read 5, iclass 28, count 0 2006.173.19:12:46.34#ibcon#about to read 6, iclass 28, count 0 2006.173.19:12:46.34#ibcon#read 6, iclass 28, count 0 2006.173.19:12:46.34#ibcon#end of sib2, iclass 28, count 0 2006.173.19:12:46.34#ibcon#*mode == 0, iclass 28, count 0 2006.173.19:12:46.34#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.19:12:46.34#ibcon#[27=USB\r\n] 2006.173.19:12:46.34#ibcon#*before write, iclass 28, count 0 2006.173.19:12:46.35#ibcon#enter sib2, iclass 28, count 0 2006.173.19:12:46.35#ibcon#flushed, iclass 28, count 0 2006.173.19:12:46.35#ibcon#about to write, iclass 28, count 0 2006.173.19:12:46.35#ibcon#wrote, iclass 28, count 0 2006.173.19:12:46.35#ibcon#about to read 3, iclass 28, count 0 2006.173.19:12:46.37#ibcon#read 3, iclass 28, count 0 2006.173.19:12:46.37#ibcon#about to read 4, iclass 28, count 0 2006.173.19:12:46.37#ibcon#read 4, iclass 28, count 0 2006.173.19:12:46.37#ibcon#about to read 5, iclass 28, count 0 2006.173.19:12:46.37#ibcon#read 5, iclass 28, count 0 2006.173.19:12:46.37#ibcon#about to read 6, iclass 28, count 0 2006.173.19:12:46.37#ibcon#read 6, iclass 28, count 0 2006.173.19:12:46.37#ibcon#end of sib2, iclass 28, count 0 2006.173.19:12:46.37#ibcon#*after write, iclass 28, count 0 2006.173.19:12:46.37#ibcon#*before return 0, iclass 28, count 0 2006.173.19:12:46.38#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.19:12:46.38#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.19:12:46.38#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.19:12:46.38#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.19:12:46.38$vck44/vblo=5,709.99 2006.173.19:12:46.38#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.19:12:46.38#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.19:12:46.38#ibcon#ireg 17 cls_cnt 0 2006.173.19:12:46.38#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.19:12:46.38#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.19:12:46.38#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.19:12:46.38#ibcon#enter wrdev, iclass 30, count 0 2006.173.19:12:46.38#ibcon#first serial, iclass 30, count 0 2006.173.19:12:46.38#ibcon#enter sib2, iclass 30, count 0 2006.173.19:12:46.38#ibcon#flushed, iclass 30, count 0 2006.173.19:12:46.38#ibcon#about to write, iclass 30, count 0 2006.173.19:12:46.38#ibcon#wrote, iclass 30, count 0 2006.173.19:12:46.38#ibcon#about to read 3, iclass 30, count 0 2006.173.19:12:46.39#ibcon#read 3, iclass 30, count 0 2006.173.19:12:46.39#ibcon#about to read 4, iclass 30, count 0 2006.173.19:12:46.39#ibcon#read 4, iclass 30, count 0 2006.173.19:12:46.39#ibcon#about to read 5, iclass 30, count 0 2006.173.19:12:46.39#ibcon#read 5, iclass 30, count 0 2006.173.19:12:46.39#ibcon#about to read 6, iclass 30, count 0 2006.173.19:12:46.39#ibcon#read 6, iclass 30, count 0 2006.173.19:12:46.39#ibcon#end of sib2, iclass 30, count 0 2006.173.19:12:46.39#ibcon#*mode == 0, iclass 30, count 0 2006.173.19:12:46.39#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.19:12:46.39#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.19:12:46.39#ibcon#*before write, iclass 30, count 0 2006.173.19:12:46.39#ibcon#enter sib2, iclass 30, count 0 2006.173.19:12:46.39#ibcon#flushed, iclass 30, count 0 2006.173.19:12:46.40#ibcon#about to write, iclass 30, count 0 2006.173.19:12:46.40#ibcon#wrote, iclass 30, count 0 2006.173.19:12:46.40#ibcon#about to read 3, iclass 30, count 0 2006.173.19:12:46.43#ibcon#read 3, iclass 30, count 0 2006.173.19:12:46.43#ibcon#about to read 4, iclass 30, count 0 2006.173.19:12:46.43#ibcon#read 4, iclass 30, count 0 2006.173.19:12:46.43#ibcon#about to read 5, iclass 30, count 0 2006.173.19:12:46.43#ibcon#read 5, iclass 30, count 0 2006.173.19:12:46.43#ibcon#about to read 6, iclass 30, count 0 2006.173.19:12:46.43#ibcon#read 6, iclass 30, count 0 2006.173.19:12:46.43#ibcon#end of sib2, iclass 30, count 0 2006.173.19:12:46.43#ibcon#*after write, iclass 30, count 0 2006.173.19:12:46.43#ibcon#*before return 0, iclass 30, count 0 2006.173.19:12:46.43#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.19:12:46.43#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.19:12:46.43#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.19:12:46.44#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.19:12:46.44$vck44/vb=5,4 2006.173.19:12:46.44#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.173.19:12:46.44#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.173.19:12:46.44#ibcon#ireg 11 cls_cnt 2 2006.173.19:12:46.44#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.19:12:46.49#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.19:12:46.49#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.19:12:46.49#ibcon#enter wrdev, iclass 32, count 2 2006.173.19:12:46.49#ibcon#first serial, iclass 32, count 2 2006.173.19:12:46.49#ibcon#enter sib2, iclass 32, count 2 2006.173.19:12:46.49#ibcon#flushed, iclass 32, count 2 2006.173.19:12:46.49#ibcon#about to write, iclass 32, count 2 2006.173.19:12:46.49#ibcon#wrote, iclass 32, count 2 2006.173.19:12:46.49#ibcon#about to read 3, iclass 32, count 2 2006.173.19:12:46.51#ibcon#read 3, iclass 32, count 2 2006.173.19:12:46.51#ibcon#about to read 4, iclass 32, count 2 2006.173.19:12:46.51#ibcon#read 4, iclass 32, count 2 2006.173.19:12:46.51#ibcon#about to read 5, iclass 32, count 2 2006.173.19:12:46.51#ibcon#read 5, iclass 32, count 2 2006.173.19:12:46.51#ibcon#about to read 6, iclass 32, count 2 2006.173.19:12:46.51#ibcon#read 6, iclass 32, count 2 2006.173.19:12:46.51#ibcon#end of sib2, iclass 32, count 2 2006.173.19:12:46.51#ibcon#*mode == 0, iclass 32, count 2 2006.173.19:12:46.51#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.173.19:12:46.51#ibcon#[27=AT05-04\r\n] 2006.173.19:12:46.51#ibcon#*before write, iclass 32, count 2 2006.173.19:12:46.51#ibcon#enter sib2, iclass 32, count 2 2006.173.19:12:46.51#ibcon#flushed, iclass 32, count 2 2006.173.19:12:46.51#ibcon#about to write, iclass 32, count 2 2006.173.19:12:46.51#ibcon#wrote, iclass 32, count 2 2006.173.19:12:46.52#ibcon#about to read 3, iclass 32, count 2 2006.173.19:12:46.54#ibcon#read 3, iclass 32, count 2 2006.173.19:12:46.54#ibcon#about to read 4, iclass 32, count 2 2006.173.19:12:46.54#ibcon#read 4, iclass 32, count 2 2006.173.19:12:46.54#ibcon#about to read 5, iclass 32, count 2 2006.173.19:12:46.54#ibcon#read 5, iclass 32, count 2 2006.173.19:12:46.54#ibcon#about to read 6, iclass 32, count 2 2006.173.19:12:46.54#ibcon#read 6, iclass 32, count 2 2006.173.19:12:46.54#ibcon#end of sib2, iclass 32, count 2 2006.173.19:12:46.54#ibcon#*after write, iclass 32, count 2 2006.173.19:12:46.54#ibcon#*before return 0, iclass 32, count 2 2006.173.19:12:46.54#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.19:12:46.54#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.173.19:12:46.54#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.173.19:12:46.55#ibcon#ireg 7 cls_cnt 0 2006.173.19:12:46.55#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.19:12:46.65#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.19:12:46.65#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.19:12:46.65#ibcon#enter wrdev, iclass 32, count 0 2006.173.19:12:46.65#ibcon#first serial, iclass 32, count 0 2006.173.19:12:46.65#ibcon#enter sib2, iclass 32, count 0 2006.173.19:12:46.65#ibcon#flushed, iclass 32, count 0 2006.173.19:12:46.65#ibcon#about to write, iclass 32, count 0 2006.173.19:12:46.65#ibcon#wrote, iclass 32, count 0 2006.173.19:12:46.65#ibcon#about to read 3, iclass 32, count 0 2006.173.19:12:46.67#ibcon#read 3, iclass 32, count 0 2006.173.19:12:46.67#ibcon#about to read 4, iclass 32, count 0 2006.173.19:12:46.67#ibcon#read 4, iclass 32, count 0 2006.173.19:12:46.67#ibcon#about to read 5, iclass 32, count 0 2006.173.19:12:46.67#ibcon#read 5, iclass 32, count 0 2006.173.19:12:46.67#ibcon#about to read 6, iclass 32, count 0 2006.173.19:12:46.67#ibcon#read 6, iclass 32, count 0 2006.173.19:12:46.67#ibcon#end of sib2, iclass 32, count 0 2006.173.19:12:46.67#ibcon#*mode == 0, iclass 32, count 0 2006.173.19:12:46.67#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.19:12:46.67#ibcon#[27=USB\r\n] 2006.173.19:12:46.68#ibcon#*before write, iclass 32, count 0 2006.173.19:12:46.68#ibcon#enter sib2, iclass 32, count 0 2006.173.19:12:46.68#ibcon#flushed, iclass 32, count 0 2006.173.19:12:46.68#ibcon#about to write, iclass 32, count 0 2006.173.19:12:46.68#ibcon#wrote, iclass 32, count 0 2006.173.19:12:46.68#ibcon#about to read 3, iclass 32, count 0 2006.173.19:12:46.70#ibcon#read 3, iclass 32, count 0 2006.173.19:12:46.70#ibcon#about to read 4, iclass 32, count 0 2006.173.19:12:46.70#ibcon#read 4, iclass 32, count 0 2006.173.19:12:46.70#ibcon#about to read 5, iclass 32, count 0 2006.173.19:12:46.70#ibcon#read 5, iclass 32, count 0 2006.173.19:12:46.70#ibcon#about to read 6, iclass 32, count 0 2006.173.19:12:46.70#ibcon#read 6, iclass 32, count 0 2006.173.19:12:46.70#ibcon#end of sib2, iclass 32, count 0 2006.173.19:12:46.70#ibcon#*after write, iclass 32, count 0 2006.173.19:12:46.70#ibcon#*before return 0, iclass 32, count 0 2006.173.19:12:46.70#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.19:12:46.70#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.173.19:12:46.70#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.19:12:46.71#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.19:12:46.71$vck44/vblo=6,719.99 2006.173.19:12:46.71#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.19:12:46.71#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.19:12:46.71#ibcon#ireg 17 cls_cnt 0 2006.173.19:12:46.71#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.19:12:46.71#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.19:12:46.71#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.19:12:46.71#ibcon#enter wrdev, iclass 34, count 0 2006.173.19:12:46.71#ibcon#first serial, iclass 34, count 0 2006.173.19:12:46.71#ibcon#enter sib2, iclass 34, count 0 2006.173.19:12:46.71#ibcon#flushed, iclass 34, count 0 2006.173.19:12:46.71#ibcon#about to write, iclass 34, count 0 2006.173.19:12:46.71#ibcon#wrote, iclass 34, count 0 2006.173.19:12:46.71#ibcon#about to read 3, iclass 34, count 0 2006.173.19:12:46.72#ibcon#read 3, iclass 34, count 0 2006.173.19:12:46.72#ibcon#about to read 4, iclass 34, count 0 2006.173.19:12:46.72#ibcon#read 4, iclass 34, count 0 2006.173.19:12:46.72#ibcon#about to read 5, iclass 34, count 0 2006.173.19:12:46.72#ibcon#read 5, iclass 34, count 0 2006.173.19:12:46.72#ibcon#about to read 6, iclass 34, count 0 2006.173.19:12:46.72#ibcon#read 6, iclass 34, count 0 2006.173.19:12:46.72#ibcon#end of sib2, iclass 34, count 0 2006.173.19:12:46.72#ibcon#*mode == 0, iclass 34, count 0 2006.173.19:12:46.72#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.19:12:46.72#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.19:12:46.72#ibcon#*before write, iclass 34, count 0 2006.173.19:12:46.72#ibcon#enter sib2, iclass 34, count 0 2006.173.19:12:46.72#ibcon#flushed, iclass 34, count 0 2006.173.19:12:46.72#ibcon#about to write, iclass 34, count 0 2006.173.19:12:46.73#ibcon#wrote, iclass 34, count 0 2006.173.19:12:46.73#ibcon#about to read 3, iclass 34, count 0 2006.173.19:12:46.76#ibcon#read 3, iclass 34, count 0 2006.173.19:12:46.76#ibcon#about to read 4, iclass 34, count 0 2006.173.19:12:46.76#ibcon#read 4, iclass 34, count 0 2006.173.19:12:46.76#ibcon#about to read 5, iclass 34, count 0 2006.173.19:12:46.76#ibcon#read 5, iclass 34, count 0 2006.173.19:12:46.76#ibcon#about to read 6, iclass 34, count 0 2006.173.19:12:46.76#ibcon#read 6, iclass 34, count 0 2006.173.19:12:46.76#ibcon#end of sib2, iclass 34, count 0 2006.173.19:12:46.76#ibcon#*after write, iclass 34, count 0 2006.173.19:12:46.76#ibcon#*before return 0, iclass 34, count 0 2006.173.19:12:46.76#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.19:12:46.77#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.19:12:46.77#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.19:12:46.77#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.19:12:46.77$vck44/vb=6,4 2006.173.19:12:46.77#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.19:12:46.77#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.19:12:46.77#ibcon#ireg 11 cls_cnt 2 2006.173.19:12:46.77#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.19:12:46.81#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.19:12:46.81#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.19:12:46.81#ibcon#enter wrdev, iclass 36, count 2 2006.173.19:12:46.81#ibcon#first serial, iclass 36, count 2 2006.173.19:12:46.81#ibcon#enter sib2, iclass 36, count 2 2006.173.19:12:46.81#ibcon#flushed, iclass 36, count 2 2006.173.19:12:46.81#ibcon#about to write, iclass 36, count 2 2006.173.19:12:46.81#ibcon#wrote, iclass 36, count 2 2006.173.19:12:46.81#ibcon#about to read 3, iclass 36, count 2 2006.173.19:12:46.83#ibcon#read 3, iclass 36, count 2 2006.173.19:12:46.83#ibcon#about to read 4, iclass 36, count 2 2006.173.19:12:46.83#ibcon#read 4, iclass 36, count 2 2006.173.19:12:46.83#ibcon#about to read 5, iclass 36, count 2 2006.173.19:12:46.83#ibcon#read 5, iclass 36, count 2 2006.173.19:12:46.83#ibcon#about to read 6, iclass 36, count 2 2006.173.19:12:46.83#ibcon#read 6, iclass 36, count 2 2006.173.19:12:46.83#ibcon#end of sib2, iclass 36, count 2 2006.173.19:12:46.83#ibcon#*mode == 0, iclass 36, count 2 2006.173.19:12:46.83#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.19:12:46.83#ibcon#[27=AT06-04\r\n] 2006.173.19:12:46.83#ibcon#*before write, iclass 36, count 2 2006.173.19:12:46.83#ibcon#enter sib2, iclass 36, count 2 2006.173.19:12:46.83#ibcon#flushed, iclass 36, count 2 2006.173.19:12:46.83#ibcon#about to write, iclass 36, count 2 2006.173.19:12:46.84#ibcon#wrote, iclass 36, count 2 2006.173.19:12:46.84#ibcon#about to read 3, iclass 36, count 2 2006.173.19:12:46.86#ibcon#read 3, iclass 36, count 2 2006.173.19:12:46.86#ibcon#about to read 4, iclass 36, count 2 2006.173.19:12:46.86#ibcon#read 4, iclass 36, count 2 2006.173.19:12:46.86#ibcon#about to read 5, iclass 36, count 2 2006.173.19:12:46.86#ibcon#read 5, iclass 36, count 2 2006.173.19:12:46.86#ibcon#about to read 6, iclass 36, count 2 2006.173.19:12:46.86#ibcon#read 6, iclass 36, count 2 2006.173.19:12:46.86#ibcon#end of sib2, iclass 36, count 2 2006.173.19:12:46.86#ibcon#*after write, iclass 36, count 2 2006.173.19:12:46.86#ibcon#*before return 0, iclass 36, count 2 2006.173.19:12:46.86#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.19:12:46.87#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.19:12:46.87#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.19:12:46.87#ibcon#ireg 7 cls_cnt 0 2006.173.19:12:46.87#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.19:12:46.98#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.19:12:46.98#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.19:12:46.98#ibcon#enter wrdev, iclass 36, count 0 2006.173.19:12:46.98#ibcon#first serial, iclass 36, count 0 2006.173.19:12:46.98#ibcon#enter sib2, iclass 36, count 0 2006.173.19:12:46.98#ibcon#flushed, iclass 36, count 0 2006.173.19:12:46.98#ibcon#about to write, iclass 36, count 0 2006.173.19:12:46.98#ibcon#wrote, iclass 36, count 0 2006.173.19:12:46.98#ibcon#about to read 3, iclass 36, count 0 2006.173.19:12:47.00#ibcon#read 3, iclass 36, count 0 2006.173.19:12:47.00#ibcon#about to read 4, iclass 36, count 0 2006.173.19:12:47.00#ibcon#read 4, iclass 36, count 0 2006.173.19:12:47.00#ibcon#about to read 5, iclass 36, count 0 2006.173.19:12:47.00#ibcon#read 5, iclass 36, count 0 2006.173.19:12:47.00#ibcon#about to read 6, iclass 36, count 0 2006.173.19:12:47.00#ibcon#read 6, iclass 36, count 0 2006.173.19:12:47.00#ibcon#end of sib2, iclass 36, count 0 2006.173.19:12:47.00#ibcon#*mode == 0, iclass 36, count 0 2006.173.19:12:47.00#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.19:12:47.00#ibcon#[27=USB\r\n] 2006.173.19:12:47.00#ibcon#*before write, iclass 36, count 0 2006.173.19:12:47.01#ibcon#enter sib2, iclass 36, count 0 2006.173.19:12:47.01#ibcon#flushed, iclass 36, count 0 2006.173.19:12:47.01#ibcon#about to write, iclass 36, count 0 2006.173.19:12:47.01#ibcon#wrote, iclass 36, count 0 2006.173.19:12:47.01#ibcon#about to read 3, iclass 36, count 0 2006.173.19:12:47.03#ibcon#read 3, iclass 36, count 0 2006.173.19:12:47.03#ibcon#about to read 4, iclass 36, count 0 2006.173.19:12:47.03#ibcon#read 4, iclass 36, count 0 2006.173.19:12:47.03#ibcon#about to read 5, iclass 36, count 0 2006.173.19:12:47.03#ibcon#read 5, iclass 36, count 0 2006.173.19:12:47.03#ibcon#about to read 6, iclass 36, count 0 2006.173.19:12:47.03#ibcon#read 6, iclass 36, count 0 2006.173.19:12:47.03#ibcon#end of sib2, iclass 36, count 0 2006.173.19:12:47.03#ibcon#*after write, iclass 36, count 0 2006.173.19:12:47.03#ibcon#*before return 0, iclass 36, count 0 2006.173.19:12:47.03#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.19:12:47.04#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.19:12:47.04#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.19:12:47.04#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.19:12:47.04$vck44/vblo=7,734.99 2006.173.19:12:47.04#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.19:12:47.04#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.19:12:47.04#ibcon#ireg 17 cls_cnt 0 2006.173.19:12:47.04#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.19:12:47.04#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.19:12:47.04#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.19:12:47.04#ibcon#enter wrdev, iclass 38, count 0 2006.173.19:12:47.04#ibcon#first serial, iclass 38, count 0 2006.173.19:12:47.04#ibcon#enter sib2, iclass 38, count 0 2006.173.19:12:47.04#ibcon#flushed, iclass 38, count 0 2006.173.19:12:47.04#ibcon#about to write, iclass 38, count 0 2006.173.19:12:47.04#ibcon#wrote, iclass 38, count 0 2006.173.19:12:47.04#ibcon#about to read 3, iclass 38, count 0 2006.173.19:12:47.05#ibcon#read 3, iclass 38, count 0 2006.173.19:12:47.05#ibcon#about to read 4, iclass 38, count 0 2006.173.19:12:47.05#ibcon#read 4, iclass 38, count 0 2006.173.19:12:47.05#ibcon#about to read 5, iclass 38, count 0 2006.173.19:12:47.05#ibcon#read 5, iclass 38, count 0 2006.173.19:12:47.05#ibcon#about to read 6, iclass 38, count 0 2006.173.19:12:47.05#ibcon#read 6, iclass 38, count 0 2006.173.19:12:47.05#ibcon#end of sib2, iclass 38, count 0 2006.173.19:12:47.05#ibcon#*mode == 0, iclass 38, count 0 2006.173.19:12:47.06#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.19:12:47.06#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.19:12:47.06#ibcon#*before write, iclass 38, count 0 2006.173.19:12:47.06#ibcon#enter sib2, iclass 38, count 0 2006.173.19:12:47.06#ibcon#flushed, iclass 38, count 0 2006.173.19:12:47.06#ibcon#about to write, iclass 38, count 0 2006.173.19:12:47.06#ibcon#wrote, iclass 38, count 0 2006.173.19:12:47.06#ibcon#about to read 3, iclass 38, count 0 2006.173.19:12:47.09#ibcon#read 3, iclass 38, count 0 2006.173.19:12:47.09#ibcon#about to read 4, iclass 38, count 0 2006.173.19:12:47.09#ibcon#read 4, iclass 38, count 0 2006.173.19:12:47.09#ibcon#about to read 5, iclass 38, count 0 2006.173.19:12:47.09#ibcon#read 5, iclass 38, count 0 2006.173.19:12:47.09#ibcon#about to read 6, iclass 38, count 0 2006.173.19:12:47.09#ibcon#read 6, iclass 38, count 0 2006.173.19:12:47.09#ibcon#end of sib2, iclass 38, count 0 2006.173.19:12:47.09#ibcon#*after write, iclass 38, count 0 2006.173.19:12:47.09#ibcon#*before return 0, iclass 38, count 0 2006.173.19:12:47.09#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.19:12:47.10#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.19:12:47.10#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.19:12:47.10#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.19:12:47.10$vck44/vb=7,4 2006.173.19:12:47.10#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.19:12:47.10#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.19:12:47.10#ibcon#ireg 11 cls_cnt 2 2006.173.19:12:47.10#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.19:12:47.15#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.19:12:47.15#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.19:12:47.15#ibcon#enter wrdev, iclass 40, count 2 2006.173.19:12:47.15#ibcon#first serial, iclass 40, count 2 2006.173.19:12:47.15#ibcon#enter sib2, iclass 40, count 2 2006.173.19:12:47.15#ibcon#flushed, iclass 40, count 2 2006.173.19:12:47.15#ibcon#about to write, iclass 40, count 2 2006.173.19:12:47.15#ibcon#wrote, iclass 40, count 2 2006.173.19:12:47.15#ibcon#about to read 3, iclass 40, count 2 2006.173.19:12:47.17#ibcon#read 3, iclass 40, count 2 2006.173.19:12:47.17#ibcon#about to read 4, iclass 40, count 2 2006.173.19:12:47.17#ibcon#read 4, iclass 40, count 2 2006.173.19:12:47.17#ibcon#about to read 5, iclass 40, count 2 2006.173.19:12:47.17#ibcon#read 5, iclass 40, count 2 2006.173.19:12:47.17#ibcon#about to read 6, iclass 40, count 2 2006.173.19:12:47.17#ibcon#read 6, iclass 40, count 2 2006.173.19:12:47.17#ibcon#end of sib2, iclass 40, count 2 2006.173.19:12:47.17#ibcon#*mode == 0, iclass 40, count 2 2006.173.19:12:47.17#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.19:12:47.17#ibcon#[27=AT07-04\r\n] 2006.173.19:12:47.17#ibcon#*before write, iclass 40, count 2 2006.173.19:12:47.17#ibcon#enter sib2, iclass 40, count 2 2006.173.19:12:47.18#ibcon#flushed, iclass 40, count 2 2006.173.19:12:47.18#ibcon#about to write, iclass 40, count 2 2006.173.19:12:47.18#ibcon#wrote, iclass 40, count 2 2006.173.19:12:47.18#ibcon#about to read 3, iclass 40, count 2 2006.173.19:12:47.20#ibcon#read 3, iclass 40, count 2 2006.173.19:12:47.20#ibcon#about to read 4, iclass 40, count 2 2006.173.19:12:47.20#ibcon#read 4, iclass 40, count 2 2006.173.19:12:47.20#ibcon#about to read 5, iclass 40, count 2 2006.173.19:12:47.20#ibcon#read 5, iclass 40, count 2 2006.173.19:12:47.20#ibcon#about to read 6, iclass 40, count 2 2006.173.19:12:47.20#ibcon#read 6, iclass 40, count 2 2006.173.19:12:47.20#ibcon#end of sib2, iclass 40, count 2 2006.173.19:12:47.20#ibcon#*after write, iclass 40, count 2 2006.173.19:12:47.20#ibcon#*before return 0, iclass 40, count 2 2006.173.19:12:47.20#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.19:12:47.20#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.19:12:47.20#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.19:12:47.20#ibcon#ireg 7 cls_cnt 0 2006.173.19:12:47.21#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.19:12:47.31#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.19:12:47.31#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.19:12:47.31#ibcon#enter wrdev, iclass 40, count 0 2006.173.19:12:47.31#ibcon#first serial, iclass 40, count 0 2006.173.19:12:47.31#ibcon#enter sib2, iclass 40, count 0 2006.173.19:12:47.31#ibcon#flushed, iclass 40, count 0 2006.173.19:12:47.31#ibcon#about to write, iclass 40, count 0 2006.173.19:12:47.31#ibcon#wrote, iclass 40, count 0 2006.173.19:12:47.31#ibcon#about to read 3, iclass 40, count 0 2006.173.19:12:47.33#ibcon#read 3, iclass 40, count 0 2006.173.19:12:47.33#ibcon#about to read 4, iclass 40, count 0 2006.173.19:12:47.33#ibcon#read 4, iclass 40, count 0 2006.173.19:12:47.33#ibcon#about to read 5, iclass 40, count 0 2006.173.19:12:47.33#ibcon#read 5, iclass 40, count 0 2006.173.19:12:47.33#ibcon#about to read 6, iclass 40, count 0 2006.173.19:12:47.33#ibcon#read 6, iclass 40, count 0 2006.173.19:12:47.33#ibcon#end of sib2, iclass 40, count 0 2006.173.19:12:47.33#ibcon#*mode == 0, iclass 40, count 0 2006.173.19:12:47.33#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.19:12:47.33#ibcon#[27=USB\r\n] 2006.173.19:12:47.33#ibcon#*before write, iclass 40, count 0 2006.173.19:12:47.33#ibcon#enter sib2, iclass 40, count 0 2006.173.19:12:47.33#ibcon#flushed, iclass 40, count 0 2006.173.19:12:47.34#ibcon#about to write, iclass 40, count 0 2006.173.19:12:47.34#ibcon#wrote, iclass 40, count 0 2006.173.19:12:47.34#ibcon#about to read 3, iclass 40, count 0 2006.173.19:12:47.36#ibcon#read 3, iclass 40, count 0 2006.173.19:12:47.36#ibcon#about to read 4, iclass 40, count 0 2006.173.19:12:47.36#ibcon#read 4, iclass 40, count 0 2006.173.19:12:47.36#ibcon#about to read 5, iclass 40, count 0 2006.173.19:12:47.36#ibcon#read 5, iclass 40, count 0 2006.173.19:12:47.36#ibcon#about to read 6, iclass 40, count 0 2006.173.19:12:47.36#ibcon#read 6, iclass 40, count 0 2006.173.19:12:47.36#ibcon#end of sib2, iclass 40, count 0 2006.173.19:12:47.36#ibcon#*after write, iclass 40, count 0 2006.173.19:12:47.36#ibcon#*before return 0, iclass 40, count 0 2006.173.19:12:47.36#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.19:12:47.37#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.19:12:47.37#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.19:12:47.37#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.19:12:47.37$vck44/vblo=8,744.99 2006.173.19:12:47.37#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.19:12:47.37#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.19:12:47.37#ibcon#ireg 17 cls_cnt 0 2006.173.19:12:47.37#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.19:12:47.37#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.19:12:47.37#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.19:12:47.37#ibcon#enter wrdev, iclass 4, count 0 2006.173.19:12:47.37#ibcon#first serial, iclass 4, count 0 2006.173.19:12:47.37#ibcon#enter sib2, iclass 4, count 0 2006.173.19:12:47.37#ibcon#flushed, iclass 4, count 0 2006.173.19:12:47.37#ibcon#about to write, iclass 4, count 0 2006.173.19:12:47.37#ibcon#wrote, iclass 4, count 0 2006.173.19:12:47.37#ibcon#about to read 3, iclass 4, count 0 2006.173.19:12:47.38#ibcon#read 3, iclass 4, count 0 2006.173.19:12:47.38#ibcon#about to read 4, iclass 4, count 0 2006.173.19:12:47.38#ibcon#read 4, iclass 4, count 0 2006.173.19:12:47.38#ibcon#about to read 5, iclass 4, count 0 2006.173.19:12:47.38#ibcon#read 5, iclass 4, count 0 2006.173.19:12:47.38#ibcon#about to read 6, iclass 4, count 0 2006.173.19:12:47.38#ibcon#read 6, iclass 4, count 0 2006.173.19:12:47.38#ibcon#end of sib2, iclass 4, count 0 2006.173.19:12:47.38#ibcon#*mode == 0, iclass 4, count 0 2006.173.19:12:47.38#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.19:12:47.38#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.19:12:47.38#ibcon#*before write, iclass 4, count 0 2006.173.19:12:47.39#ibcon#enter sib2, iclass 4, count 0 2006.173.19:12:47.39#ibcon#flushed, iclass 4, count 0 2006.173.19:12:47.39#ibcon#about to write, iclass 4, count 0 2006.173.19:12:47.39#ibcon#wrote, iclass 4, count 0 2006.173.19:12:47.39#ibcon#about to read 3, iclass 4, count 0 2006.173.19:12:47.42#ibcon#read 3, iclass 4, count 0 2006.173.19:12:47.42#ibcon#about to read 4, iclass 4, count 0 2006.173.19:12:47.42#ibcon#read 4, iclass 4, count 0 2006.173.19:12:47.42#ibcon#about to read 5, iclass 4, count 0 2006.173.19:12:47.42#ibcon#read 5, iclass 4, count 0 2006.173.19:12:47.42#ibcon#about to read 6, iclass 4, count 0 2006.173.19:12:47.42#ibcon#read 6, iclass 4, count 0 2006.173.19:12:47.42#ibcon#end of sib2, iclass 4, count 0 2006.173.19:12:47.42#ibcon#*after write, iclass 4, count 0 2006.173.19:12:47.42#ibcon#*before return 0, iclass 4, count 0 2006.173.19:12:47.42#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.19:12:47.43#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.19:12:47.43#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.19:12:47.43#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.19:12:47.43$vck44/vb=8,4 2006.173.19:12:47.43#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.19:12:47.43#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.19:12:47.43#ibcon#ireg 11 cls_cnt 2 2006.173.19:12:47.43#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.19:12:47.48#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.19:12:47.48#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.19:12:47.48#ibcon#enter wrdev, iclass 6, count 2 2006.173.19:12:47.48#ibcon#first serial, iclass 6, count 2 2006.173.19:12:47.48#ibcon#enter sib2, iclass 6, count 2 2006.173.19:12:47.48#ibcon#flushed, iclass 6, count 2 2006.173.19:12:47.48#ibcon#about to write, iclass 6, count 2 2006.173.19:12:47.48#ibcon#wrote, iclass 6, count 2 2006.173.19:12:47.48#ibcon#about to read 3, iclass 6, count 2 2006.173.19:12:47.50#ibcon#read 3, iclass 6, count 2 2006.173.19:12:47.50#ibcon#about to read 4, iclass 6, count 2 2006.173.19:12:47.50#ibcon#read 4, iclass 6, count 2 2006.173.19:12:47.50#ibcon#about to read 5, iclass 6, count 2 2006.173.19:12:47.50#ibcon#read 5, iclass 6, count 2 2006.173.19:12:47.50#ibcon#about to read 6, iclass 6, count 2 2006.173.19:12:47.50#ibcon#read 6, iclass 6, count 2 2006.173.19:12:47.50#ibcon#end of sib2, iclass 6, count 2 2006.173.19:12:47.50#ibcon#*mode == 0, iclass 6, count 2 2006.173.19:12:47.50#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.19:12:47.50#ibcon#[27=AT08-04\r\n] 2006.173.19:12:47.50#ibcon#*before write, iclass 6, count 2 2006.173.19:12:47.50#ibcon#enter sib2, iclass 6, count 2 2006.173.19:12:47.50#ibcon#flushed, iclass 6, count 2 2006.173.19:12:47.50#ibcon#about to write, iclass 6, count 2 2006.173.19:12:47.51#ibcon#wrote, iclass 6, count 2 2006.173.19:12:47.51#ibcon#about to read 3, iclass 6, count 2 2006.173.19:12:47.53#ibcon#read 3, iclass 6, count 2 2006.173.19:12:47.53#ibcon#about to read 4, iclass 6, count 2 2006.173.19:12:47.53#ibcon#read 4, iclass 6, count 2 2006.173.19:12:47.53#ibcon#about to read 5, iclass 6, count 2 2006.173.19:12:47.53#ibcon#read 5, iclass 6, count 2 2006.173.19:12:47.53#ibcon#about to read 6, iclass 6, count 2 2006.173.19:12:47.53#ibcon#read 6, iclass 6, count 2 2006.173.19:12:47.53#ibcon#end of sib2, iclass 6, count 2 2006.173.19:12:47.53#ibcon#*after write, iclass 6, count 2 2006.173.19:12:47.53#ibcon#*before return 0, iclass 6, count 2 2006.173.19:12:47.53#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.19:12:47.53#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.19:12:47.53#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.19:12:47.54#ibcon#ireg 7 cls_cnt 0 2006.173.19:12:47.54#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.19:12:47.64#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.19:12:47.64#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.19:12:47.64#ibcon#enter wrdev, iclass 6, count 0 2006.173.19:12:47.64#ibcon#first serial, iclass 6, count 0 2006.173.19:12:47.64#ibcon#enter sib2, iclass 6, count 0 2006.173.19:12:47.64#ibcon#flushed, iclass 6, count 0 2006.173.19:12:47.64#ibcon#about to write, iclass 6, count 0 2006.173.19:12:47.64#ibcon#wrote, iclass 6, count 0 2006.173.19:12:47.64#ibcon#about to read 3, iclass 6, count 0 2006.173.19:12:47.66#ibcon#read 3, iclass 6, count 0 2006.173.19:12:47.66#ibcon#about to read 4, iclass 6, count 0 2006.173.19:12:47.66#ibcon#read 4, iclass 6, count 0 2006.173.19:12:47.66#ibcon#about to read 5, iclass 6, count 0 2006.173.19:12:47.66#ibcon#read 5, iclass 6, count 0 2006.173.19:12:47.66#ibcon#about to read 6, iclass 6, count 0 2006.173.19:12:47.66#ibcon#read 6, iclass 6, count 0 2006.173.19:12:47.66#ibcon#end of sib2, iclass 6, count 0 2006.173.19:12:47.66#ibcon#*mode == 0, iclass 6, count 0 2006.173.19:12:47.66#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.19:12:47.66#ibcon#[27=USB\r\n] 2006.173.19:12:47.66#ibcon#*before write, iclass 6, count 0 2006.173.19:12:47.67#ibcon#enter sib2, iclass 6, count 0 2006.173.19:12:47.67#ibcon#flushed, iclass 6, count 0 2006.173.19:12:47.67#ibcon#about to write, iclass 6, count 0 2006.173.19:12:47.67#ibcon#wrote, iclass 6, count 0 2006.173.19:12:47.67#ibcon#about to read 3, iclass 6, count 0 2006.173.19:12:47.69#ibcon#read 3, iclass 6, count 0 2006.173.19:12:47.69#ibcon#about to read 4, iclass 6, count 0 2006.173.19:12:47.69#ibcon#read 4, iclass 6, count 0 2006.173.19:12:47.69#ibcon#about to read 5, iclass 6, count 0 2006.173.19:12:47.69#ibcon#read 5, iclass 6, count 0 2006.173.19:12:47.69#ibcon#about to read 6, iclass 6, count 0 2006.173.19:12:47.69#ibcon#read 6, iclass 6, count 0 2006.173.19:12:47.69#ibcon#end of sib2, iclass 6, count 0 2006.173.19:12:47.69#ibcon#*after write, iclass 6, count 0 2006.173.19:12:47.69#ibcon#*before return 0, iclass 6, count 0 2006.173.19:12:47.69#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.19:12:47.69#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.19:12:47.69#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.19:12:47.69#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.19:12:47.70$vck44/vabw=wide 2006.173.19:12:47.70#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.19:12:47.70#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.19:12:47.70#ibcon#ireg 8 cls_cnt 0 2006.173.19:12:47.70#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.19:12:47.70#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.19:12:47.70#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.19:12:47.70#ibcon#enter wrdev, iclass 10, count 0 2006.173.19:12:47.70#ibcon#first serial, iclass 10, count 0 2006.173.19:12:47.70#ibcon#enter sib2, iclass 10, count 0 2006.173.19:12:47.70#ibcon#flushed, iclass 10, count 0 2006.173.19:12:47.70#ibcon#about to write, iclass 10, count 0 2006.173.19:12:47.70#ibcon#wrote, iclass 10, count 0 2006.173.19:12:47.70#ibcon#about to read 3, iclass 10, count 0 2006.173.19:12:47.71#ibcon#read 3, iclass 10, count 0 2006.173.19:12:47.71#ibcon#about to read 4, iclass 10, count 0 2006.173.19:12:47.71#ibcon#read 4, iclass 10, count 0 2006.173.19:12:47.71#ibcon#about to read 5, iclass 10, count 0 2006.173.19:12:47.71#ibcon#read 5, iclass 10, count 0 2006.173.19:12:47.71#ibcon#about to read 6, iclass 10, count 0 2006.173.19:12:47.71#ibcon#read 6, iclass 10, count 0 2006.173.19:12:47.71#ibcon#end of sib2, iclass 10, count 0 2006.173.19:12:47.71#ibcon#*mode == 0, iclass 10, count 0 2006.173.19:12:47.71#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.19:12:47.71#ibcon#[25=BW32\r\n] 2006.173.19:12:47.71#ibcon#*before write, iclass 10, count 0 2006.173.19:12:47.71#ibcon#enter sib2, iclass 10, count 0 2006.173.19:12:47.71#ibcon#flushed, iclass 10, count 0 2006.173.19:12:47.71#ibcon#about to write, iclass 10, count 0 2006.173.19:12:47.72#ibcon#wrote, iclass 10, count 0 2006.173.19:12:47.72#ibcon#about to read 3, iclass 10, count 0 2006.173.19:12:47.74#ibcon#read 3, iclass 10, count 0 2006.173.19:12:47.74#ibcon#about to read 4, iclass 10, count 0 2006.173.19:12:47.74#ibcon#read 4, iclass 10, count 0 2006.173.19:12:47.74#ibcon#about to read 5, iclass 10, count 0 2006.173.19:12:47.74#ibcon#read 5, iclass 10, count 0 2006.173.19:12:47.74#ibcon#about to read 6, iclass 10, count 0 2006.173.19:12:47.74#ibcon#read 6, iclass 10, count 0 2006.173.19:12:47.74#ibcon#end of sib2, iclass 10, count 0 2006.173.19:12:47.74#ibcon#*after write, iclass 10, count 0 2006.173.19:12:47.74#ibcon#*before return 0, iclass 10, count 0 2006.173.19:12:47.74#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.19:12:47.75#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.19:12:47.75#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.19:12:47.75#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.19:12:47.75$vck44/vbbw=wide 2006.173.19:12:47.75#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.19:12:47.75#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.19:12:47.75#ibcon#ireg 8 cls_cnt 0 2006.173.19:12:47.75#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.19:12:47.80#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.19:12:47.80#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.19:12:47.80#ibcon#enter wrdev, iclass 12, count 0 2006.173.19:12:47.80#ibcon#first serial, iclass 12, count 0 2006.173.19:12:47.80#ibcon#enter sib2, iclass 12, count 0 2006.173.19:12:47.80#ibcon#flushed, iclass 12, count 0 2006.173.19:12:47.80#ibcon#about to write, iclass 12, count 0 2006.173.19:12:47.80#ibcon#wrote, iclass 12, count 0 2006.173.19:12:47.80#ibcon#about to read 3, iclass 12, count 0 2006.173.19:12:47.82#ibcon#read 3, iclass 12, count 0 2006.173.19:12:47.82#ibcon#about to read 4, iclass 12, count 0 2006.173.19:12:47.82#ibcon#read 4, iclass 12, count 0 2006.173.19:12:47.82#ibcon#about to read 5, iclass 12, count 0 2006.173.19:12:47.82#ibcon#read 5, iclass 12, count 0 2006.173.19:12:47.82#ibcon#about to read 6, iclass 12, count 0 2006.173.19:12:47.82#ibcon#read 6, iclass 12, count 0 2006.173.19:12:47.82#ibcon#end of sib2, iclass 12, count 0 2006.173.19:12:47.82#ibcon#*mode == 0, iclass 12, count 0 2006.173.19:12:47.82#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.19:12:47.82#ibcon#[27=BW32\r\n] 2006.173.19:12:47.82#ibcon#*before write, iclass 12, count 0 2006.173.19:12:47.82#ibcon#enter sib2, iclass 12, count 0 2006.173.19:12:47.82#ibcon#flushed, iclass 12, count 0 2006.173.19:12:47.82#ibcon#about to write, iclass 12, count 0 2006.173.19:12:47.83#ibcon#wrote, iclass 12, count 0 2006.173.19:12:47.83#ibcon#about to read 3, iclass 12, count 0 2006.173.19:12:47.85#ibcon#read 3, iclass 12, count 0 2006.173.19:12:47.85#ibcon#about to read 4, iclass 12, count 0 2006.173.19:12:47.85#ibcon#read 4, iclass 12, count 0 2006.173.19:12:47.85#ibcon#about to read 5, iclass 12, count 0 2006.173.19:12:47.85#ibcon#read 5, iclass 12, count 0 2006.173.19:12:47.85#ibcon#about to read 6, iclass 12, count 0 2006.173.19:12:47.85#ibcon#read 6, iclass 12, count 0 2006.173.19:12:47.85#ibcon#end of sib2, iclass 12, count 0 2006.173.19:12:47.85#ibcon#*after write, iclass 12, count 0 2006.173.19:12:47.85#ibcon#*before return 0, iclass 12, count 0 2006.173.19:12:47.86#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.19:12:47.86#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.19:12:47.86#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.19:12:47.86#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.19:12:47.86$setupk4/ifdk4 2006.173.19:12:47.86$ifdk4/lo= 2006.173.19:12:47.86$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.19:12:47.86$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.19:12:47.86$ifdk4/patch= 2006.173.19:12:47.86$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.19:12:47.86$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.19:12:47.86$setupk4/!*+20s 2006.173.19:12:53.45#abcon#<5=/10 0.3 1.1 19.561001002.5\r\n> 2006.173.19:12:53.47#abcon#{5=INTERFACE CLEAR} 2006.173.19:12:53.53#abcon#[5=S1D000X0/0*\r\n] 2006.173.19:13:02.48$setupk4/"tpicd 2006.173.19:13:02.48$setupk4/echo=off 2006.173.19:13:02.49$setupk4/xlog=off 2006.173.19:13:02.49:!2006.173.19:16:54 2006.173.19:13:24.13#trakl#Source acquired 2006.173.19:13:25.14#flagr#flagr/antenna,acquired 2006.173.19:16:54.01:preob 2006.173.19:16:55.14/onsource/TRACKING 2006.173.19:16:55.14:!2006.173.19:17:04 2006.173.19:17:04.00:"tape 2006.173.19:17:04.00:"st=record 2006.173.19:17:04.00:data_valid=on 2006.173.19:17:04.00:midob 2006.173.19:17:04.14/onsource/TRACKING 2006.173.19:17:04.15/wx/19.53,1002.4,100 2006.173.19:17:04.33/cable/+6.5156E-03 2006.173.19:17:05.42/va/01,07,usb,yes,35,38 2006.173.19:17:05.42/va/02,06,usb,yes,35,36 2006.173.19:17:05.42/va/03,05,usb,yes,44,46 2006.173.19:17:05.42/va/04,06,usb,yes,36,38 2006.173.19:17:05.42/va/05,04,usb,yes,28,28 2006.173.19:17:05.42/va/06,03,usb,yes,39,39 2006.173.19:17:05.42/va/07,04,usb,yes,32,33 2006.173.19:17:05.42/va/08,04,usb,yes,27,32 2006.173.19:17:05.65/valo/01,524.99,yes,locked 2006.173.19:17:05.65/valo/02,534.99,yes,locked 2006.173.19:17:05.65/valo/03,564.99,yes,locked 2006.173.19:17:05.65/valo/04,624.99,yes,locked 2006.173.19:17:05.65/valo/05,734.99,yes,locked 2006.173.19:17:05.65/valo/06,814.99,yes,locked 2006.173.19:17:05.65/valo/07,864.99,yes,locked 2006.173.19:17:05.65/valo/08,884.99,yes,locked 2006.173.19:17:06.74/vb/01,04,usb,yes,29,27 2006.173.19:17:06.74/vb/02,04,usb,yes,31,31 2006.173.19:17:06.74/vb/03,04,usb,yes,28,31 2006.173.19:17:06.74/vb/04,04,usb,yes,32,31 2006.173.19:17:06.74/vb/05,04,usb,yes,25,28 2006.173.19:17:06.74/vb/06,04,usb,yes,29,26 2006.173.19:17:06.74/vb/07,04,usb,yes,29,29 2006.173.19:17:06.74/vb/08,04,usb,yes,27,30 2006.173.19:17:06.97/vblo/01,629.99,yes,locked 2006.173.19:17:06.97/vblo/02,634.99,yes,locked 2006.173.19:17:06.97/vblo/03,649.99,yes,locked 2006.173.19:17:06.97/vblo/04,679.99,yes,locked 2006.173.19:17:06.97/vblo/05,709.99,yes,locked 2006.173.19:17:06.97/vblo/06,719.99,yes,locked 2006.173.19:17:06.97/vblo/07,734.99,yes,locked 2006.173.19:17:06.97/vblo/08,744.99,yes,locked 2006.173.19:17:07.12/vabw/8 2006.173.19:17:07.27/vbbw/8 2006.173.19:17:07.36/xfe/off,on,14.2 2006.173.19:17:07.75/ifatt/23,28,28,28 2006.173.19:17:08.07/fmout-gps/S +3.88E-07 2006.173.19:17:08.12:!2006.173.19:19:54 2006.173.19:19:54.01:data_valid=off 2006.173.19:19:54.02:"et 2006.173.19:19:54.02:!+3s 2006.173.19:19:57.03:"tape 2006.173.19:19:57.04:postob 2006.173.19:19:57.25/cable/+6.5164E-03 2006.173.19:19:57.26/wx/19.51,1002.5,100 2006.173.19:19:57.31/fmout-gps/S +3.87E-07 2006.173.19:19:57.32:scan_name=173-1922,jd0606,40 2006.173.19:19:57.32:source=1921-293,192451.06,-291430.1,2000.0,ccw 2006.173.19:19:58.14#flagr#flagr/antenna,new-source 2006.173.19:19:58.14:checkk5 2006.173.19:19:58.50/chk_autoobs//k5ts1/ autoobs is running! 2006.173.19:19:58.89/chk_autoobs//k5ts2/ autoobs is running! 2006.173.19:19:59.33/chk_autoobs//k5ts3/ autoobs is running! 2006.173.19:19:59.72/chk_autoobs//k5ts4/ autoobs is running! 2006.173.19:20:00.10/chk_obsdata//k5ts1/T1731917??a.dat file size is correct (nominal:680MB, actual:676MB). 2006.173.19:20:00.50/chk_obsdata//k5ts2/T1731917??b.dat file size is correct (nominal:680MB, actual:676MB). 2006.173.19:20:00.92/chk_obsdata//k5ts3/T1731917??c.dat file size is correct (nominal:680MB, actual:676MB). 2006.173.19:20:01.32/chk_obsdata//k5ts4/T1731917??d.dat file size is correct (nominal:680MB, actual:676MB). 2006.173.19:20:02.04/k5log//k5ts1_log_newline 2006.173.19:20:02.75/k5log//k5ts2_log_newline 2006.173.19:20:03.46/k5log//k5ts3_log_newline 2006.173.19:20:04.16/k5log//k5ts4_log_newline 2006.173.19:20:04.19/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.19:20:04.19:setupk4=1 2006.173.19:20:04.19$setupk4/echo=on 2006.173.19:20:04.19$setupk4/pcalon 2006.173.19:20:04.19$pcalon/"no phase cal control is implemented here 2006.173.19:20:04.19$setupk4/"tpicd=stop 2006.173.19:20:04.19$setupk4/"rec=synch_on 2006.173.19:20:04.19$setupk4/"rec_mode=128 2006.173.19:20:04.19$setupk4/!* 2006.173.19:20:04.19$setupk4/recpk4 2006.173.19:20:04.19$recpk4/recpatch= 2006.173.19:20:04.19$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.19:20:04.19$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.19:20:04.19$setupk4/vck44 2006.173.19:20:04.19$vck44/valo=1,524.99 2006.173.19:20:04.19#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.19:20:04.19#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.19:20:04.19#ibcon#ireg 17 cls_cnt 0 2006.173.19:20:04.19#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.19:20:04.19#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.19:20:04.19#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.19:20:04.19#ibcon#enter wrdev, iclass 7, count 0 2006.173.19:20:04.19#ibcon#first serial, iclass 7, count 0 2006.173.19:20:04.19#ibcon#enter sib2, iclass 7, count 0 2006.173.19:20:04.19#ibcon#flushed, iclass 7, count 0 2006.173.19:20:04.19#ibcon#about to write, iclass 7, count 0 2006.173.19:20:04.19#ibcon#wrote, iclass 7, count 0 2006.173.19:20:04.19#ibcon#about to read 3, iclass 7, count 0 2006.173.19:20:04.20#ibcon#read 3, iclass 7, count 0 2006.173.19:20:04.20#ibcon#about to read 4, iclass 7, count 0 2006.173.19:20:04.20#ibcon#read 4, iclass 7, count 0 2006.173.19:20:04.20#ibcon#about to read 5, iclass 7, count 0 2006.173.19:20:04.20#ibcon#read 5, iclass 7, count 0 2006.173.19:20:04.20#ibcon#about to read 6, iclass 7, count 0 2006.173.19:20:04.20#ibcon#read 6, iclass 7, count 0 2006.173.19:20:04.20#ibcon#end of sib2, iclass 7, count 0 2006.173.19:20:04.20#ibcon#*mode == 0, iclass 7, count 0 2006.173.19:20:04.20#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.19:20:04.20#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.19:20:04.20#ibcon#*before write, iclass 7, count 0 2006.173.19:20:04.20#ibcon#enter sib2, iclass 7, count 0 2006.173.19:20:04.20#ibcon#flushed, iclass 7, count 0 2006.173.19:20:04.20#ibcon#about to write, iclass 7, count 0 2006.173.19:20:04.20#ibcon#wrote, iclass 7, count 0 2006.173.19:20:04.20#ibcon#about to read 3, iclass 7, count 0 2006.173.19:20:04.25#ibcon#read 3, iclass 7, count 0 2006.173.19:20:04.25#ibcon#about to read 4, iclass 7, count 0 2006.173.19:20:04.25#ibcon#read 4, iclass 7, count 0 2006.173.19:20:04.25#ibcon#about to read 5, iclass 7, count 0 2006.173.19:20:04.25#ibcon#read 5, iclass 7, count 0 2006.173.19:20:04.25#ibcon#about to read 6, iclass 7, count 0 2006.173.19:20:04.25#ibcon#read 6, iclass 7, count 0 2006.173.19:20:04.25#ibcon#end of sib2, iclass 7, count 0 2006.173.19:20:04.25#ibcon#*after write, iclass 7, count 0 2006.173.19:20:04.25#ibcon#*before return 0, iclass 7, count 0 2006.173.19:20:04.25#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.19:20:04.25#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.19:20:04.25#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.19:20:04.25#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.19:20:04.25$vck44/va=1,7 2006.173.19:20:04.25#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.19:20:04.25#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.19:20:04.25#ibcon#ireg 11 cls_cnt 2 2006.173.19:20:04.25#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.19:20:04.25#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.19:20:04.25#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.19:20:04.25#ibcon#enter wrdev, iclass 11, count 2 2006.173.19:20:04.25#ibcon#first serial, iclass 11, count 2 2006.173.19:20:04.25#ibcon#enter sib2, iclass 11, count 2 2006.173.19:20:04.25#ibcon#flushed, iclass 11, count 2 2006.173.19:20:04.25#ibcon#about to write, iclass 11, count 2 2006.173.19:20:04.25#ibcon#wrote, iclass 11, count 2 2006.173.19:20:04.25#ibcon#about to read 3, iclass 11, count 2 2006.173.19:20:04.27#ibcon#read 3, iclass 11, count 2 2006.173.19:20:04.27#ibcon#about to read 4, iclass 11, count 2 2006.173.19:20:04.27#ibcon#read 4, iclass 11, count 2 2006.173.19:20:04.27#ibcon#about to read 5, iclass 11, count 2 2006.173.19:20:04.27#ibcon#read 5, iclass 11, count 2 2006.173.19:20:04.27#ibcon#about to read 6, iclass 11, count 2 2006.173.19:20:04.27#ibcon#read 6, iclass 11, count 2 2006.173.19:20:04.27#ibcon#end of sib2, iclass 11, count 2 2006.173.19:20:04.27#ibcon#*mode == 0, iclass 11, count 2 2006.173.19:20:04.27#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.19:20:04.27#ibcon#[25=AT01-07\r\n] 2006.173.19:20:04.27#ibcon#*before write, iclass 11, count 2 2006.173.19:20:04.27#ibcon#enter sib2, iclass 11, count 2 2006.173.19:20:04.27#ibcon#flushed, iclass 11, count 2 2006.173.19:20:04.27#ibcon#about to write, iclass 11, count 2 2006.173.19:20:04.27#ibcon#wrote, iclass 11, count 2 2006.173.19:20:04.27#ibcon#about to read 3, iclass 11, count 2 2006.173.19:20:04.30#ibcon#read 3, iclass 11, count 2 2006.173.19:20:04.30#ibcon#about to read 4, iclass 11, count 2 2006.173.19:20:04.30#ibcon#read 4, iclass 11, count 2 2006.173.19:20:04.30#ibcon#about to read 5, iclass 11, count 2 2006.173.19:20:04.30#ibcon#read 5, iclass 11, count 2 2006.173.19:20:04.30#ibcon#about to read 6, iclass 11, count 2 2006.173.19:20:04.30#ibcon#read 6, iclass 11, count 2 2006.173.19:20:04.30#ibcon#end of sib2, iclass 11, count 2 2006.173.19:20:04.30#ibcon#*after write, iclass 11, count 2 2006.173.19:20:04.30#ibcon#*before return 0, iclass 11, count 2 2006.173.19:20:04.30#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.19:20:04.30#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.19:20:04.30#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.19:20:04.30#ibcon#ireg 7 cls_cnt 0 2006.173.19:20:04.30#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.19:20:04.42#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.19:20:04.42#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.19:20:04.42#ibcon#enter wrdev, iclass 11, count 0 2006.173.19:20:04.42#ibcon#first serial, iclass 11, count 0 2006.173.19:20:04.42#ibcon#enter sib2, iclass 11, count 0 2006.173.19:20:04.42#ibcon#flushed, iclass 11, count 0 2006.173.19:20:04.42#ibcon#about to write, iclass 11, count 0 2006.173.19:20:04.42#ibcon#wrote, iclass 11, count 0 2006.173.19:20:04.42#ibcon#about to read 3, iclass 11, count 0 2006.173.19:20:04.44#ibcon#read 3, iclass 11, count 0 2006.173.19:20:04.44#ibcon#about to read 4, iclass 11, count 0 2006.173.19:20:04.44#ibcon#read 4, iclass 11, count 0 2006.173.19:20:04.44#ibcon#about to read 5, iclass 11, count 0 2006.173.19:20:04.44#ibcon#read 5, iclass 11, count 0 2006.173.19:20:04.44#ibcon#about to read 6, iclass 11, count 0 2006.173.19:20:04.44#ibcon#read 6, iclass 11, count 0 2006.173.19:20:04.44#ibcon#end of sib2, iclass 11, count 0 2006.173.19:20:04.44#ibcon#*mode == 0, iclass 11, count 0 2006.173.19:20:04.44#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.19:20:04.44#ibcon#[25=USB\r\n] 2006.173.19:20:04.44#ibcon#*before write, iclass 11, count 0 2006.173.19:20:04.44#ibcon#enter sib2, iclass 11, count 0 2006.173.19:20:04.44#ibcon#flushed, iclass 11, count 0 2006.173.19:20:04.44#ibcon#about to write, iclass 11, count 0 2006.173.19:20:04.44#ibcon#wrote, iclass 11, count 0 2006.173.19:20:04.44#ibcon#about to read 3, iclass 11, count 0 2006.173.19:20:04.47#ibcon#read 3, iclass 11, count 0 2006.173.19:20:04.47#ibcon#about to read 4, iclass 11, count 0 2006.173.19:20:04.47#ibcon#read 4, iclass 11, count 0 2006.173.19:20:04.47#ibcon#about to read 5, iclass 11, count 0 2006.173.19:20:04.47#ibcon#read 5, iclass 11, count 0 2006.173.19:20:04.47#ibcon#about to read 6, iclass 11, count 0 2006.173.19:20:04.47#ibcon#read 6, iclass 11, count 0 2006.173.19:20:04.47#ibcon#end of sib2, iclass 11, count 0 2006.173.19:20:04.47#ibcon#*after write, iclass 11, count 0 2006.173.19:20:04.47#ibcon#*before return 0, iclass 11, count 0 2006.173.19:20:04.47#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.19:20:04.47#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.19:20:04.47#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.19:20:04.47#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.19:20:04.47$vck44/valo=2,534.99 2006.173.19:20:04.47#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.19:20:04.47#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.19:20:04.47#ibcon#ireg 17 cls_cnt 0 2006.173.19:20:04.47#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.19:20:04.47#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.19:20:04.47#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.19:20:04.47#ibcon#enter wrdev, iclass 13, count 0 2006.173.19:20:04.47#ibcon#first serial, iclass 13, count 0 2006.173.19:20:04.47#ibcon#enter sib2, iclass 13, count 0 2006.173.19:20:04.47#ibcon#flushed, iclass 13, count 0 2006.173.19:20:04.47#ibcon#about to write, iclass 13, count 0 2006.173.19:20:04.47#ibcon#wrote, iclass 13, count 0 2006.173.19:20:04.47#ibcon#about to read 3, iclass 13, count 0 2006.173.19:20:04.49#ibcon#read 3, iclass 13, count 0 2006.173.19:20:04.49#ibcon#about to read 4, iclass 13, count 0 2006.173.19:20:04.49#ibcon#read 4, iclass 13, count 0 2006.173.19:20:04.49#ibcon#about to read 5, iclass 13, count 0 2006.173.19:20:04.49#ibcon#read 5, iclass 13, count 0 2006.173.19:20:04.49#ibcon#about to read 6, iclass 13, count 0 2006.173.19:20:04.49#ibcon#read 6, iclass 13, count 0 2006.173.19:20:04.49#ibcon#end of sib2, iclass 13, count 0 2006.173.19:20:04.49#ibcon#*mode == 0, iclass 13, count 0 2006.173.19:20:04.49#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.19:20:04.49#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.19:20:04.49#ibcon#*before write, iclass 13, count 0 2006.173.19:20:04.49#ibcon#enter sib2, iclass 13, count 0 2006.173.19:20:04.49#ibcon#flushed, iclass 13, count 0 2006.173.19:20:04.49#ibcon#about to write, iclass 13, count 0 2006.173.19:20:04.49#ibcon#wrote, iclass 13, count 0 2006.173.19:20:04.49#ibcon#about to read 3, iclass 13, count 0 2006.173.19:20:04.53#ibcon#read 3, iclass 13, count 0 2006.173.19:20:04.53#ibcon#about to read 4, iclass 13, count 0 2006.173.19:20:04.53#ibcon#read 4, iclass 13, count 0 2006.173.19:20:04.53#ibcon#about to read 5, iclass 13, count 0 2006.173.19:20:04.53#ibcon#read 5, iclass 13, count 0 2006.173.19:20:04.53#ibcon#about to read 6, iclass 13, count 0 2006.173.19:20:04.53#ibcon#read 6, iclass 13, count 0 2006.173.19:20:04.53#ibcon#end of sib2, iclass 13, count 0 2006.173.19:20:04.53#ibcon#*after write, iclass 13, count 0 2006.173.19:20:04.53#ibcon#*before return 0, iclass 13, count 0 2006.173.19:20:04.53#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.19:20:04.53#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.19:20:04.53#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.19:20:04.53#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.19:20:04.53$vck44/va=2,6 2006.173.19:20:04.53#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.19:20:04.53#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.19:20:04.53#ibcon#ireg 11 cls_cnt 2 2006.173.19:20:04.53#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.19:20:04.59#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.19:20:04.59#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.19:20:04.59#ibcon#enter wrdev, iclass 15, count 2 2006.173.19:20:04.59#ibcon#first serial, iclass 15, count 2 2006.173.19:20:04.59#ibcon#enter sib2, iclass 15, count 2 2006.173.19:20:04.59#ibcon#flushed, iclass 15, count 2 2006.173.19:20:04.59#ibcon#about to write, iclass 15, count 2 2006.173.19:20:04.59#ibcon#wrote, iclass 15, count 2 2006.173.19:20:04.59#ibcon#about to read 3, iclass 15, count 2 2006.173.19:20:04.61#ibcon#read 3, iclass 15, count 2 2006.173.19:20:04.61#ibcon#about to read 4, iclass 15, count 2 2006.173.19:20:04.61#ibcon#read 4, iclass 15, count 2 2006.173.19:20:04.61#ibcon#about to read 5, iclass 15, count 2 2006.173.19:20:04.61#ibcon#read 5, iclass 15, count 2 2006.173.19:20:04.61#ibcon#about to read 6, iclass 15, count 2 2006.173.19:20:04.61#ibcon#read 6, iclass 15, count 2 2006.173.19:20:04.61#ibcon#end of sib2, iclass 15, count 2 2006.173.19:20:04.61#ibcon#*mode == 0, iclass 15, count 2 2006.173.19:20:04.61#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.19:20:04.61#ibcon#[25=AT02-06\r\n] 2006.173.19:20:04.61#ibcon#*before write, iclass 15, count 2 2006.173.19:20:04.61#ibcon#enter sib2, iclass 15, count 2 2006.173.19:20:04.61#ibcon#flushed, iclass 15, count 2 2006.173.19:20:04.61#ibcon#about to write, iclass 15, count 2 2006.173.19:20:04.61#ibcon#wrote, iclass 15, count 2 2006.173.19:20:04.61#ibcon#about to read 3, iclass 15, count 2 2006.173.19:20:04.64#ibcon#read 3, iclass 15, count 2 2006.173.19:20:04.64#ibcon#about to read 4, iclass 15, count 2 2006.173.19:20:04.64#ibcon#read 4, iclass 15, count 2 2006.173.19:20:04.64#ibcon#about to read 5, iclass 15, count 2 2006.173.19:20:04.64#ibcon#read 5, iclass 15, count 2 2006.173.19:20:04.64#ibcon#about to read 6, iclass 15, count 2 2006.173.19:20:04.64#ibcon#read 6, iclass 15, count 2 2006.173.19:20:04.64#ibcon#end of sib2, iclass 15, count 2 2006.173.19:20:04.64#ibcon#*after write, iclass 15, count 2 2006.173.19:20:04.64#ibcon#*before return 0, iclass 15, count 2 2006.173.19:20:04.64#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.19:20:04.64#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.19:20:04.64#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.19:20:04.64#ibcon#ireg 7 cls_cnt 0 2006.173.19:20:04.64#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.19:20:04.76#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.19:20:04.76#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.19:20:04.76#ibcon#enter wrdev, iclass 15, count 0 2006.173.19:20:04.76#ibcon#first serial, iclass 15, count 0 2006.173.19:20:04.76#ibcon#enter sib2, iclass 15, count 0 2006.173.19:20:04.76#ibcon#flushed, iclass 15, count 0 2006.173.19:20:04.76#ibcon#about to write, iclass 15, count 0 2006.173.19:20:04.76#ibcon#wrote, iclass 15, count 0 2006.173.19:20:04.76#ibcon#about to read 3, iclass 15, count 0 2006.173.19:20:04.78#ibcon#read 3, iclass 15, count 0 2006.173.19:20:04.78#ibcon#about to read 4, iclass 15, count 0 2006.173.19:20:04.78#ibcon#read 4, iclass 15, count 0 2006.173.19:20:04.78#ibcon#about to read 5, iclass 15, count 0 2006.173.19:20:04.78#ibcon#read 5, iclass 15, count 0 2006.173.19:20:04.78#ibcon#about to read 6, iclass 15, count 0 2006.173.19:20:04.78#ibcon#read 6, iclass 15, count 0 2006.173.19:20:04.78#ibcon#end of sib2, iclass 15, count 0 2006.173.19:20:04.78#ibcon#*mode == 0, iclass 15, count 0 2006.173.19:20:04.78#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.19:20:04.78#ibcon#[25=USB\r\n] 2006.173.19:20:04.78#ibcon#*before write, iclass 15, count 0 2006.173.19:20:04.78#ibcon#enter sib2, iclass 15, count 0 2006.173.19:20:04.78#ibcon#flushed, iclass 15, count 0 2006.173.19:20:04.78#ibcon#about to write, iclass 15, count 0 2006.173.19:20:04.78#ibcon#wrote, iclass 15, count 0 2006.173.19:20:04.78#ibcon#about to read 3, iclass 15, count 0 2006.173.19:20:04.81#ibcon#read 3, iclass 15, count 0 2006.173.19:20:04.81#ibcon#about to read 4, iclass 15, count 0 2006.173.19:20:04.81#ibcon#read 4, iclass 15, count 0 2006.173.19:20:04.81#ibcon#about to read 5, iclass 15, count 0 2006.173.19:20:04.81#ibcon#read 5, iclass 15, count 0 2006.173.19:20:04.81#ibcon#about to read 6, iclass 15, count 0 2006.173.19:20:04.81#ibcon#read 6, iclass 15, count 0 2006.173.19:20:04.81#ibcon#end of sib2, iclass 15, count 0 2006.173.19:20:04.81#ibcon#*after write, iclass 15, count 0 2006.173.19:20:04.81#ibcon#*before return 0, iclass 15, count 0 2006.173.19:20:04.81#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.19:20:04.81#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.19:20:04.81#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.19:20:04.81#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.19:20:04.81$vck44/valo=3,564.99 2006.173.19:20:04.81#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.19:20:04.81#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.19:20:04.81#ibcon#ireg 17 cls_cnt 0 2006.173.19:20:04.81#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.19:20:04.81#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.19:20:04.81#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.19:20:04.81#ibcon#enter wrdev, iclass 17, count 0 2006.173.19:20:04.81#ibcon#first serial, iclass 17, count 0 2006.173.19:20:04.81#ibcon#enter sib2, iclass 17, count 0 2006.173.19:20:04.81#ibcon#flushed, iclass 17, count 0 2006.173.19:20:04.81#ibcon#about to write, iclass 17, count 0 2006.173.19:20:04.81#ibcon#wrote, iclass 17, count 0 2006.173.19:20:04.81#ibcon#about to read 3, iclass 17, count 0 2006.173.19:20:04.83#ibcon#read 3, iclass 17, count 0 2006.173.19:20:04.83#ibcon#about to read 4, iclass 17, count 0 2006.173.19:20:04.83#ibcon#read 4, iclass 17, count 0 2006.173.19:20:04.83#ibcon#about to read 5, iclass 17, count 0 2006.173.19:20:04.83#ibcon#read 5, iclass 17, count 0 2006.173.19:20:04.83#ibcon#about to read 6, iclass 17, count 0 2006.173.19:20:04.83#ibcon#read 6, iclass 17, count 0 2006.173.19:20:04.83#ibcon#end of sib2, iclass 17, count 0 2006.173.19:20:04.83#ibcon#*mode == 0, iclass 17, count 0 2006.173.19:20:04.83#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.19:20:04.83#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.19:20:04.83#ibcon#*before write, iclass 17, count 0 2006.173.19:20:04.83#ibcon#enter sib2, iclass 17, count 0 2006.173.19:20:04.83#ibcon#flushed, iclass 17, count 0 2006.173.19:20:04.83#ibcon#about to write, iclass 17, count 0 2006.173.19:20:04.83#ibcon#wrote, iclass 17, count 0 2006.173.19:20:04.83#ibcon#about to read 3, iclass 17, count 0 2006.173.19:20:04.87#ibcon#read 3, iclass 17, count 0 2006.173.19:20:04.87#ibcon#about to read 4, iclass 17, count 0 2006.173.19:20:04.87#ibcon#read 4, iclass 17, count 0 2006.173.19:20:04.87#ibcon#about to read 5, iclass 17, count 0 2006.173.19:20:04.87#ibcon#read 5, iclass 17, count 0 2006.173.19:20:04.87#ibcon#about to read 6, iclass 17, count 0 2006.173.19:20:04.87#ibcon#read 6, iclass 17, count 0 2006.173.19:20:04.87#ibcon#end of sib2, iclass 17, count 0 2006.173.19:20:04.87#ibcon#*after write, iclass 17, count 0 2006.173.19:20:04.87#ibcon#*before return 0, iclass 17, count 0 2006.173.19:20:04.87#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.19:20:04.87#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.19:20:04.87#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.19:20:04.87#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.19:20:04.87$vck44/va=3,5 2006.173.19:20:04.87#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.19:20:04.87#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.19:20:04.87#ibcon#ireg 11 cls_cnt 2 2006.173.19:20:04.87#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.19:20:04.93#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.19:20:04.93#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.19:20:04.93#ibcon#enter wrdev, iclass 19, count 2 2006.173.19:20:04.93#ibcon#first serial, iclass 19, count 2 2006.173.19:20:04.93#ibcon#enter sib2, iclass 19, count 2 2006.173.19:20:04.93#ibcon#flushed, iclass 19, count 2 2006.173.19:20:04.93#ibcon#about to write, iclass 19, count 2 2006.173.19:20:04.93#ibcon#wrote, iclass 19, count 2 2006.173.19:20:04.93#ibcon#about to read 3, iclass 19, count 2 2006.173.19:20:04.95#ibcon#read 3, iclass 19, count 2 2006.173.19:20:04.95#ibcon#about to read 4, iclass 19, count 2 2006.173.19:20:04.95#ibcon#read 4, iclass 19, count 2 2006.173.19:20:04.95#ibcon#about to read 5, iclass 19, count 2 2006.173.19:20:04.95#ibcon#read 5, iclass 19, count 2 2006.173.19:20:04.95#ibcon#about to read 6, iclass 19, count 2 2006.173.19:20:04.95#ibcon#read 6, iclass 19, count 2 2006.173.19:20:04.95#ibcon#end of sib2, iclass 19, count 2 2006.173.19:20:04.95#ibcon#*mode == 0, iclass 19, count 2 2006.173.19:20:04.95#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.19:20:04.95#ibcon#[25=AT03-05\r\n] 2006.173.19:20:04.95#ibcon#*before write, iclass 19, count 2 2006.173.19:20:04.95#ibcon#enter sib2, iclass 19, count 2 2006.173.19:20:04.95#ibcon#flushed, iclass 19, count 2 2006.173.19:20:04.95#ibcon#about to write, iclass 19, count 2 2006.173.19:20:04.95#ibcon#wrote, iclass 19, count 2 2006.173.19:20:04.95#ibcon#about to read 3, iclass 19, count 2 2006.173.19:20:04.98#ibcon#read 3, iclass 19, count 2 2006.173.19:20:04.98#ibcon#about to read 4, iclass 19, count 2 2006.173.19:20:04.98#ibcon#read 4, iclass 19, count 2 2006.173.19:20:04.98#ibcon#about to read 5, iclass 19, count 2 2006.173.19:20:04.98#ibcon#read 5, iclass 19, count 2 2006.173.19:20:04.98#ibcon#about to read 6, iclass 19, count 2 2006.173.19:20:04.98#ibcon#read 6, iclass 19, count 2 2006.173.19:20:04.98#ibcon#end of sib2, iclass 19, count 2 2006.173.19:20:04.98#ibcon#*after write, iclass 19, count 2 2006.173.19:20:04.98#ibcon#*before return 0, iclass 19, count 2 2006.173.19:20:04.98#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.19:20:04.98#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.19:20:04.98#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.19:20:04.98#ibcon#ireg 7 cls_cnt 0 2006.173.19:20:04.98#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.19:20:05.10#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.19:20:05.10#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.19:20:05.10#ibcon#enter wrdev, iclass 19, count 0 2006.173.19:20:05.10#ibcon#first serial, iclass 19, count 0 2006.173.19:20:05.10#ibcon#enter sib2, iclass 19, count 0 2006.173.19:20:05.10#ibcon#flushed, iclass 19, count 0 2006.173.19:20:05.10#ibcon#about to write, iclass 19, count 0 2006.173.19:20:05.10#ibcon#wrote, iclass 19, count 0 2006.173.19:20:05.10#ibcon#about to read 3, iclass 19, count 0 2006.173.19:20:05.12#ibcon#read 3, iclass 19, count 0 2006.173.19:20:05.12#ibcon#about to read 4, iclass 19, count 0 2006.173.19:20:05.12#ibcon#read 4, iclass 19, count 0 2006.173.19:20:05.12#ibcon#about to read 5, iclass 19, count 0 2006.173.19:20:05.12#ibcon#read 5, iclass 19, count 0 2006.173.19:20:05.12#ibcon#about to read 6, iclass 19, count 0 2006.173.19:20:05.12#ibcon#read 6, iclass 19, count 0 2006.173.19:20:05.12#ibcon#end of sib2, iclass 19, count 0 2006.173.19:20:05.12#ibcon#*mode == 0, iclass 19, count 0 2006.173.19:20:05.12#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.19:20:05.12#ibcon#[25=USB\r\n] 2006.173.19:20:05.12#ibcon#*before write, iclass 19, count 0 2006.173.19:20:05.12#ibcon#enter sib2, iclass 19, count 0 2006.173.19:20:05.12#ibcon#flushed, iclass 19, count 0 2006.173.19:20:05.12#ibcon#about to write, iclass 19, count 0 2006.173.19:20:05.12#ibcon#wrote, iclass 19, count 0 2006.173.19:20:05.12#ibcon#about to read 3, iclass 19, count 0 2006.173.19:20:05.15#ibcon#read 3, iclass 19, count 0 2006.173.19:20:05.15#ibcon#about to read 4, iclass 19, count 0 2006.173.19:20:05.15#ibcon#read 4, iclass 19, count 0 2006.173.19:20:05.15#ibcon#about to read 5, iclass 19, count 0 2006.173.19:20:05.15#ibcon#read 5, iclass 19, count 0 2006.173.19:20:05.15#ibcon#about to read 6, iclass 19, count 0 2006.173.19:20:05.15#ibcon#read 6, iclass 19, count 0 2006.173.19:20:05.15#ibcon#end of sib2, iclass 19, count 0 2006.173.19:20:05.15#ibcon#*after write, iclass 19, count 0 2006.173.19:20:05.15#ibcon#*before return 0, iclass 19, count 0 2006.173.19:20:05.15#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.19:20:05.15#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.19:20:05.15#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.19:20:05.15#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.19:20:05.15$vck44/valo=4,624.99 2006.173.19:20:05.15#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.19:20:05.15#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.19:20:05.15#ibcon#ireg 17 cls_cnt 0 2006.173.19:20:05.15#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.19:20:05.15#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.19:20:05.15#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.19:20:05.15#ibcon#enter wrdev, iclass 21, count 0 2006.173.19:20:05.15#ibcon#first serial, iclass 21, count 0 2006.173.19:20:05.15#ibcon#enter sib2, iclass 21, count 0 2006.173.19:20:05.15#ibcon#flushed, iclass 21, count 0 2006.173.19:20:05.15#ibcon#about to write, iclass 21, count 0 2006.173.19:20:05.15#ibcon#wrote, iclass 21, count 0 2006.173.19:20:05.15#ibcon#about to read 3, iclass 21, count 0 2006.173.19:20:05.17#ibcon#read 3, iclass 21, count 0 2006.173.19:20:05.17#ibcon#about to read 4, iclass 21, count 0 2006.173.19:20:05.17#ibcon#read 4, iclass 21, count 0 2006.173.19:20:05.17#ibcon#about to read 5, iclass 21, count 0 2006.173.19:20:05.17#ibcon#read 5, iclass 21, count 0 2006.173.19:20:05.17#ibcon#about to read 6, iclass 21, count 0 2006.173.19:20:05.17#ibcon#read 6, iclass 21, count 0 2006.173.19:20:05.17#ibcon#end of sib2, iclass 21, count 0 2006.173.19:20:05.17#ibcon#*mode == 0, iclass 21, count 0 2006.173.19:20:05.17#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.19:20:05.17#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.19:20:05.17#ibcon#*before write, iclass 21, count 0 2006.173.19:20:05.17#ibcon#enter sib2, iclass 21, count 0 2006.173.19:20:05.17#ibcon#flushed, iclass 21, count 0 2006.173.19:20:05.17#ibcon#about to write, iclass 21, count 0 2006.173.19:20:05.17#ibcon#wrote, iclass 21, count 0 2006.173.19:20:05.17#ibcon#about to read 3, iclass 21, count 0 2006.173.19:20:05.21#ibcon#read 3, iclass 21, count 0 2006.173.19:20:05.21#ibcon#about to read 4, iclass 21, count 0 2006.173.19:20:05.21#ibcon#read 4, iclass 21, count 0 2006.173.19:20:05.21#ibcon#about to read 5, iclass 21, count 0 2006.173.19:20:05.21#ibcon#read 5, iclass 21, count 0 2006.173.19:20:05.21#ibcon#about to read 6, iclass 21, count 0 2006.173.19:20:05.21#ibcon#read 6, iclass 21, count 0 2006.173.19:20:05.21#ibcon#end of sib2, iclass 21, count 0 2006.173.19:20:05.21#ibcon#*after write, iclass 21, count 0 2006.173.19:20:05.21#ibcon#*before return 0, iclass 21, count 0 2006.173.19:20:05.21#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.19:20:05.21#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.19:20:05.21#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.19:20:05.21#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.19:20:05.21$vck44/va=4,6 2006.173.19:20:05.21#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.19:20:05.21#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.19:20:05.21#ibcon#ireg 11 cls_cnt 2 2006.173.19:20:05.21#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.19:20:05.27#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.19:20:05.27#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.19:20:05.27#ibcon#enter wrdev, iclass 23, count 2 2006.173.19:20:05.27#ibcon#first serial, iclass 23, count 2 2006.173.19:20:05.27#ibcon#enter sib2, iclass 23, count 2 2006.173.19:20:05.27#ibcon#flushed, iclass 23, count 2 2006.173.19:20:05.27#ibcon#about to write, iclass 23, count 2 2006.173.19:20:05.27#ibcon#wrote, iclass 23, count 2 2006.173.19:20:05.27#ibcon#about to read 3, iclass 23, count 2 2006.173.19:20:05.29#ibcon#read 3, iclass 23, count 2 2006.173.19:20:05.29#ibcon#about to read 4, iclass 23, count 2 2006.173.19:20:05.29#ibcon#read 4, iclass 23, count 2 2006.173.19:20:05.29#ibcon#about to read 5, iclass 23, count 2 2006.173.19:20:05.29#ibcon#read 5, iclass 23, count 2 2006.173.19:20:05.29#ibcon#about to read 6, iclass 23, count 2 2006.173.19:20:05.29#ibcon#read 6, iclass 23, count 2 2006.173.19:20:05.29#ibcon#end of sib2, iclass 23, count 2 2006.173.19:20:05.29#ibcon#*mode == 0, iclass 23, count 2 2006.173.19:20:05.29#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.19:20:05.29#ibcon#[25=AT04-06\r\n] 2006.173.19:20:05.29#ibcon#*before write, iclass 23, count 2 2006.173.19:20:05.29#ibcon#enter sib2, iclass 23, count 2 2006.173.19:20:05.29#ibcon#flushed, iclass 23, count 2 2006.173.19:20:05.29#ibcon#about to write, iclass 23, count 2 2006.173.19:20:05.29#ibcon#wrote, iclass 23, count 2 2006.173.19:20:05.29#ibcon#about to read 3, iclass 23, count 2 2006.173.19:20:05.32#ibcon#read 3, iclass 23, count 2 2006.173.19:20:05.32#ibcon#about to read 4, iclass 23, count 2 2006.173.19:20:05.32#ibcon#read 4, iclass 23, count 2 2006.173.19:20:05.32#ibcon#about to read 5, iclass 23, count 2 2006.173.19:20:05.32#ibcon#read 5, iclass 23, count 2 2006.173.19:20:05.32#ibcon#about to read 6, iclass 23, count 2 2006.173.19:20:05.32#ibcon#read 6, iclass 23, count 2 2006.173.19:20:05.32#ibcon#end of sib2, iclass 23, count 2 2006.173.19:20:05.32#ibcon#*after write, iclass 23, count 2 2006.173.19:20:05.32#ibcon#*before return 0, iclass 23, count 2 2006.173.19:20:05.32#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.19:20:05.32#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.19:20:05.32#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.19:20:05.32#ibcon#ireg 7 cls_cnt 0 2006.173.19:20:05.32#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.19:20:05.44#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.19:20:05.44#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.19:20:05.44#ibcon#enter wrdev, iclass 23, count 0 2006.173.19:20:05.44#ibcon#first serial, iclass 23, count 0 2006.173.19:20:05.44#ibcon#enter sib2, iclass 23, count 0 2006.173.19:20:05.44#ibcon#flushed, iclass 23, count 0 2006.173.19:20:05.44#ibcon#about to write, iclass 23, count 0 2006.173.19:20:05.44#ibcon#wrote, iclass 23, count 0 2006.173.19:20:05.44#ibcon#about to read 3, iclass 23, count 0 2006.173.19:20:05.46#ibcon#read 3, iclass 23, count 0 2006.173.19:20:05.46#ibcon#about to read 4, iclass 23, count 0 2006.173.19:20:05.46#ibcon#read 4, iclass 23, count 0 2006.173.19:20:05.46#ibcon#about to read 5, iclass 23, count 0 2006.173.19:20:05.46#ibcon#read 5, iclass 23, count 0 2006.173.19:20:05.46#ibcon#about to read 6, iclass 23, count 0 2006.173.19:20:05.46#ibcon#read 6, iclass 23, count 0 2006.173.19:20:05.46#ibcon#end of sib2, iclass 23, count 0 2006.173.19:20:05.46#ibcon#*mode == 0, iclass 23, count 0 2006.173.19:20:05.46#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.19:20:05.46#ibcon#[25=USB\r\n] 2006.173.19:20:05.46#ibcon#*before write, iclass 23, count 0 2006.173.19:20:05.46#ibcon#enter sib2, iclass 23, count 0 2006.173.19:20:05.46#ibcon#flushed, iclass 23, count 0 2006.173.19:20:05.46#ibcon#about to write, iclass 23, count 0 2006.173.19:20:05.46#ibcon#wrote, iclass 23, count 0 2006.173.19:20:05.46#ibcon#about to read 3, iclass 23, count 0 2006.173.19:20:05.49#ibcon#read 3, iclass 23, count 0 2006.173.19:20:05.49#ibcon#about to read 4, iclass 23, count 0 2006.173.19:20:05.49#ibcon#read 4, iclass 23, count 0 2006.173.19:20:05.49#ibcon#about to read 5, iclass 23, count 0 2006.173.19:20:05.49#ibcon#read 5, iclass 23, count 0 2006.173.19:20:05.49#ibcon#about to read 6, iclass 23, count 0 2006.173.19:20:05.49#ibcon#read 6, iclass 23, count 0 2006.173.19:20:05.49#ibcon#end of sib2, iclass 23, count 0 2006.173.19:20:05.49#ibcon#*after write, iclass 23, count 0 2006.173.19:20:05.49#ibcon#*before return 0, iclass 23, count 0 2006.173.19:20:05.49#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.19:20:05.49#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.19:20:05.49#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.19:20:05.49#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.19:20:05.49$vck44/valo=5,734.99 2006.173.19:20:05.49#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.19:20:05.49#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.19:20:05.49#ibcon#ireg 17 cls_cnt 0 2006.173.19:20:05.49#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.19:20:05.49#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.19:20:05.49#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.19:20:05.49#ibcon#enter wrdev, iclass 25, count 0 2006.173.19:20:05.49#ibcon#first serial, iclass 25, count 0 2006.173.19:20:05.49#ibcon#enter sib2, iclass 25, count 0 2006.173.19:20:05.49#ibcon#flushed, iclass 25, count 0 2006.173.19:20:05.49#ibcon#about to write, iclass 25, count 0 2006.173.19:20:05.49#ibcon#wrote, iclass 25, count 0 2006.173.19:20:05.49#ibcon#about to read 3, iclass 25, count 0 2006.173.19:20:05.51#ibcon#read 3, iclass 25, count 0 2006.173.19:20:05.51#ibcon#about to read 4, iclass 25, count 0 2006.173.19:20:05.51#ibcon#read 4, iclass 25, count 0 2006.173.19:20:05.51#ibcon#about to read 5, iclass 25, count 0 2006.173.19:20:05.51#ibcon#read 5, iclass 25, count 0 2006.173.19:20:05.51#ibcon#about to read 6, iclass 25, count 0 2006.173.19:20:05.51#ibcon#read 6, iclass 25, count 0 2006.173.19:20:05.51#ibcon#end of sib2, iclass 25, count 0 2006.173.19:20:05.51#ibcon#*mode == 0, iclass 25, count 0 2006.173.19:20:05.51#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.19:20:05.51#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.19:20:05.51#ibcon#*before write, iclass 25, count 0 2006.173.19:20:05.51#ibcon#enter sib2, iclass 25, count 0 2006.173.19:20:05.51#ibcon#flushed, iclass 25, count 0 2006.173.19:20:05.51#ibcon#about to write, iclass 25, count 0 2006.173.19:20:05.51#ibcon#wrote, iclass 25, count 0 2006.173.19:20:05.51#ibcon#about to read 3, iclass 25, count 0 2006.173.19:20:05.55#ibcon#read 3, iclass 25, count 0 2006.173.19:20:05.55#ibcon#about to read 4, iclass 25, count 0 2006.173.19:20:05.55#ibcon#read 4, iclass 25, count 0 2006.173.19:20:05.55#ibcon#about to read 5, iclass 25, count 0 2006.173.19:20:05.55#ibcon#read 5, iclass 25, count 0 2006.173.19:20:05.55#ibcon#about to read 6, iclass 25, count 0 2006.173.19:20:05.55#ibcon#read 6, iclass 25, count 0 2006.173.19:20:05.55#ibcon#end of sib2, iclass 25, count 0 2006.173.19:20:05.55#ibcon#*after write, iclass 25, count 0 2006.173.19:20:05.55#ibcon#*before return 0, iclass 25, count 0 2006.173.19:20:05.55#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.19:20:05.55#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.19:20:05.55#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.19:20:05.55#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.19:20:05.55$vck44/va=5,4 2006.173.19:20:05.55#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.19:20:05.55#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.19:20:05.55#ibcon#ireg 11 cls_cnt 2 2006.173.19:20:05.55#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.19:20:05.61#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.19:20:05.61#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.19:20:05.61#ibcon#enter wrdev, iclass 27, count 2 2006.173.19:20:05.61#ibcon#first serial, iclass 27, count 2 2006.173.19:20:05.61#ibcon#enter sib2, iclass 27, count 2 2006.173.19:20:05.61#ibcon#flushed, iclass 27, count 2 2006.173.19:20:05.61#ibcon#about to write, iclass 27, count 2 2006.173.19:20:05.61#ibcon#wrote, iclass 27, count 2 2006.173.19:20:05.61#ibcon#about to read 3, iclass 27, count 2 2006.173.19:20:05.63#ibcon#read 3, iclass 27, count 2 2006.173.19:20:05.63#ibcon#about to read 4, iclass 27, count 2 2006.173.19:20:05.63#ibcon#read 4, iclass 27, count 2 2006.173.19:20:05.63#ibcon#about to read 5, iclass 27, count 2 2006.173.19:20:05.63#ibcon#read 5, iclass 27, count 2 2006.173.19:20:05.63#ibcon#about to read 6, iclass 27, count 2 2006.173.19:20:05.63#ibcon#read 6, iclass 27, count 2 2006.173.19:20:05.63#ibcon#end of sib2, iclass 27, count 2 2006.173.19:20:05.63#ibcon#*mode == 0, iclass 27, count 2 2006.173.19:20:05.63#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.19:20:05.63#ibcon#[25=AT05-04\r\n] 2006.173.19:20:05.63#ibcon#*before write, iclass 27, count 2 2006.173.19:20:05.63#ibcon#enter sib2, iclass 27, count 2 2006.173.19:20:05.63#ibcon#flushed, iclass 27, count 2 2006.173.19:20:05.63#ibcon#about to write, iclass 27, count 2 2006.173.19:20:05.63#ibcon#wrote, iclass 27, count 2 2006.173.19:20:05.63#ibcon#about to read 3, iclass 27, count 2 2006.173.19:20:05.66#ibcon#read 3, iclass 27, count 2 2006.173.19:20:05.66#ibcon#about to read 4, iclass 27, count 2 2006.173.19:20:05.66#ibcon#read 4, iclass 27, count 2 2006.173.19:20:05.66#ibcon#about to read 5, iclass 27, count 2 2006.173.19:20:05.66#ibcon#read 5, iclass 27, count 2 2006.173.19:20:05.66#ibcon#about to read 6, iclass 27, count 2 2006.173.19:20:05.66#ibcon#read 6, iclass 27, count 2 2006.173.19:20:05.66#ibcon#end of sib2, iclass 27, count 2 2006.173.19:20:05.66#ibcon#*after write, iclass 27, count 2 2006.173.19:20:05.66#ibcon#*before return 0, iclass 27, count 2 2006.173.19:20:05.66#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.19:20:05.66#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.19:20:05.66#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.19:20:05.66#ibcon#ireg 7 cls_cnt 0 2006.173.19:20:05.66#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.19:20:05.78#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.19:20:05.78#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.19:20:05.78#ibcon#enter wrdev, iclass 27, count 0 2006.173.19:20:05.78#ibcon#first serial, iclass 27, count 0 2006.173.19:20:05.78#ibcon#enter sib2, iclass 27, count 0 2006.173.19:20:05.78#ibcon#flushed, iclass 27, count 0 2006.173.19:20:05.78#ibcon#about to write, iclass 27, count 0 2006.173.19:20:05.78#ibcon#wrote, iclass 27, count 0 2006.173.19:20:05.78#ibcon#about to read 3, iclass 27, count 0 2006.173.19:20:05.80#ibcon#read 3, iclass 27, count 0 2006.173.19:20:05.80#ibcon#about to read 4, iclass 27, count 0 2006.173.19:20:05.80#ibcon#read 4, iclass 27, count 0 2006.173.19:20:05.80#ibcon#about to read 5, iclass 27, count 0 2006.173.19:20:05.80#ibcon#read 5, iclass 27, count 0 2006.173.19:20:05.80#ibcon#about to read 6, iclass 27, count 0 2006.173.19:20:05.80#ibcon#read 6, iclass 27, count 0 2006.173.19:20:05.80#ibcon#end of sib2, iclass 27, count 0 2006.173.19:20:05.80#ibcon#*mode == 0, iclass 27, count 0 2006.173.19:20:05.80#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.19:20:05.80#ibcon#[25=USB\r\n] 2006.173.19:20:05.80#ibcon#*before write, iclass 27, count 0 2006.173.19:20:05.80#ibcon#enter sib2, iclass 27, count 0 2006.173.19:20:05.80#ibcon#flushed, iclass 27, count 0 2006.173.19:20:05.80#ibcon#about to write, iclass 27, count 0 2006.173.19:20:05.80#ibcon#wrote, iclass 27, count 0 2006.173.19:20:05.80#ibcon#about to read 3, iclass 27, count 0 2006.173.19:20:05.83#ibcon#read 3, iclass 27, count 0 2006.173.19:20:05.83#ibcon#about to read 4, iclass 27, count 0 2006.173.19:20:05.83#ibcon#read 4, iclass 27, count 0 2006.173.19:20:05.83#ibcon#about to read 5, iclass 27, count 0 2006.173.19:20:05.83#ibcon#read 5, iclass 27, count 0 2006.173.19:20:05.83#ibcon#about to read 6, iclass 27, count 0 2006.173.19:20:05.83#ibcon#read 6, iclass 27, count 0 2006.173.19:20:05.83#ibcon#end of sib2, iclass 27, count 0 2006.173.19:20:05.83#ibcon#*after write, iclass 27, count 0 2006.173.19:20:05.83#ibcon#*before return 0, iclass 27, count 0 2006.173.19:20:05.83#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.19:20:05.83#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.19:20:05.83#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.19:20:05.83#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.19:20:05.83$vck44/valo=6,814.99 2006.173.19:20:05.83#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.19:20:05.83#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.19:20:05.83#ibcon#ireg 17 cls_cnt 0 2006.173.19:20:05.83#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.19:20:05.83#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.19:20:05.83#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.19:20:05.83#ibcon#enter wrdev, iclass 29, count 0 2006.173.19:20:05.83#ibcon#first serial, iclass 29, count 0 2006.173.19:20:05.83#ibcon#enter sib2, iclass 29, count 0 2006.173.19:20:05.83#ibcon#flushed, iclass 29, count 0 2006.173.19:20:05.83#ibcon#about to write, iclass 29, count 0 2006.173.19:20:05.83#ibcon#wrote, iclass 29, count 0 2006.173.19:20:05.83#ibcon#about to read 3, iclass 29, count 0 2006.173.19:20:05.85#ibcon#read 3, iclass 29, count 0 2006.173.19:20:05.85#ibcon#about to read 4, iclass 29, count 0 2006.173.19:20:05.85#ibcon#read 4, iclass 29, count 0 2006.173.19:20:05.85#ibcon#about to read 5, iclass 29, count 0 2006.173.19:20:05.85#ibcon#read 5, iclass 29, count 0 2006.173.19:20:05.85#ibcon#about to read 6, iclass 29, count 0 2006.173.19:20:05.85#ibcon#read 6, iclass 29, count 0 2006.173.19:20:05.85#ibcon#end of sib2, iclass 29, count 0 2006.173.19:20:05.85#ibcon#*mode == 0, iclass 29, count 0 2006.173.19:20:05.85#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.19:20:05.85#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.19:20:05.85#ibcon#*before write, iclass 29, count 0 2006.173.19:20:05.85#ibcon#enter sib2, iclass 29, count 0 2006.173.19:20:05.85#ibcon#flushed, iclass 29, count 0 2006.173.19:20:05.85#ibcon#about to write, iclass 29, count 0 2006.173.19:20:05.85#ibcon#wrote, iclass 29, count 0 2006.173.19:20:05.85#ibcon#about to read 3, iclass 29, count 0 2006.173.19:20:05.89#ibcon#read 3, iclass 29, count 0 2006.173.19:20:05.89#ibcon#about to read 4, iclass 29, count 0 2006.173.19:20:05.89#ibcon#read 4, iclass 29, count 0 2006.173.19:20:05.89#ibcon#about to read 5, iclass 29, count 0 2006.173.19:20:05.89#ibcon#read 5, iclass 29, count 0 2006.173.19:20:05.89#ibcon#about to read 6, iclass 29, count 0 2006.173.19:20:05.89#ibcon#read 6, iclass 29, count 0 2006.173.19:20:05.89#ibcon#end of sib2, iclass 29, count 0 2006.173.19:20:05.89#ibcon#*after write, iclass 29, count 0 2006.173.19:20:05.89#ibcon#*before return 0, iclass 29, count 0 2006.173.19:20:05.89#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.19:20:05.89#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.19:20:05.89#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.19:20:05.89#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.19:20:05.89$vck44/va=6,3 2006.173.19:20:05.89#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.19:20:05.89#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.19:20:05.89#ibcon#ireg 11 cls_cnt 2 2006.173.19:20:05.89#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.19:20:05.95#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.19:20:05.95#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.19:20:05.95#ibcon#enter wrdev, iclass 31, count 2 2006.173.19:20:05.95#ibcon#first serial, iclass 31, count 2 2006.173.19:20:05.95#ibcon#enter sib2, iclass 31, count 2 2006.173.19:20:05.95#ibcon#flushed, iclass 31, count 2 2006.173.19:20:05.95#ibcon#about to write, iclass 31, count 2 2006.173.19:20:05.95#ibcon#wrote, iclass 31, count 2 2006.173.19:20:05.95#ibcon#about to read 3, iclass 31, count 2 2006.173.19:20:05.97#ibcon#read 3, iclass 31, count 2 2006.173.19:20:05.97#ibcon#about to read 4, iclass 31, count 2 2006.173.19:20:05.97#ibcon#read 4, iclass 31, count 2 2006.173.19:20:05.97#ibcon#about to read 5, iclass 31, count 2 2006.173.19:20:05.97#ibcon#read 5, iclass 31, count 2 2006.173.19:20:05.97#ibcon#about to read 6, iclass 31, count 2 2006.173.19:20:05.97#ibcon#read 6, iclass 31, count 2 2006.173.19:20:05.97#ibcon#end of sib2, iclass 31, count 2 2006.173.19:20:05.97#ibcon#*mode == 0, iclass 31, count 2 2006.173.19:20:05.97#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.19:20:05.97#ibcon#[25=AT06-03\r\n] 2006.173.19:20:05.97#ibcon#*before write, iclass 31, count 2 2006.173.19:20:05.97#ibcon#enter sib2, iclass 31, count 2 2006.173.19:20:05.97#ibcon#flushed, iclass 31, count 2 2006.173.19:20:05.97#ibcon#about to write, iclass 31, count 2 2006.173.19:20:05.97#ibcon#wrote, iclass 31, count 2 2006.173.19:20:05.97#ibcon#about to read 3, iclass 31, count 2 2006.173.19:20:06.00#ibcon#read 3, iclass 31, count 2 2006.173.19:20:06.00#ibcon#about to read 4, iclass 31, count 2 2006.173.19:20:06.00#ibcon#read 4, iclass 31, count 2 2006.173.19:20:06.00#ibcon#about to read 5, iclass 31, count 2 2006.173.19:20:06.00#ibcon#read 5, iclass 31, count 2 2006.173.19:20:06.00#ibcon#about to read 6, iclass 31, count 2 2006.173.19:20:06.00#ibcon#read 6, iclass 31, count 2 2006.173.19:20:06.00#ibcon#end of sib2, iclass 31, count 2 2006.173.19:20:06.00#ibcon#*after write, iclass 31, count 2 2006.173.19:20:06.00#ibcon#*before return 0, iclass 31, count 2 2006.173.19:20:06.00#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.19:20:06.00#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.19:20:06.00#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.19:20:06.00#ibcon#ireg 7 cls_cnt 0 2006.173.19:20:06.00#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.19:20:06.12#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.19:20:06.12#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.19:20:06.12#ibcon#enter wrdev, iclass 31, count 0 2006.173.19:20:06.12#ibcon#first serial, iclass 31, count 0 2006.173.19:20:06.12#ibcon#enter sib2, iclass 31, count 0 2006.173.19:20:06.12#ibcon#flushed, iclass 31, count 0 2006.173.19:20:06.12#ibcon#about to write, iclass 31, count 0 2006.173.19:20:06.12#ibcon#wrote, iclass 31, count 0 2006.173.19:20:06.12#ibcon#about to read 3, iclass 31, count 0 2006.173.19:20:06.14#ibcon#read 3, iclass 31, count 0 2006.173.19:20:06.14#ibcon#about to read 4, iclass 31, count 0 2006.173.19:20:06.14#ibcon#read 4, iclass 31, count 0 2006.173.19:20:06.14#ibcon#about to read 5, iclass 31, count 0 2006.173.19:20:06.14#ibcon#read 5, iclass 31, count 0 2006.173.19:20:06.14#ibcon#about to read 6, iclass 31, count 0 2006.173.19:20:06.14#ibcon#read 6, iclass 31, count 0 2006.173.19:20:06.14#ibcon#end of sib2, iclass 31, count 0 2006.173.19:20:06.14#ibcon#*mode == 0, iclass 31, count 0 2006.173.19:20:06.14#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.19:20:06.14#ibcon#[25=USB\r\n] 2006.173.19:20:06.14#ibcon#*before write, iclass 31, count 0 2006.173.19:20:06.14#ibcon#enter sib2, iclass 31, count 0 2006.173.19:20:06.14#ibcon#flushed, iclass 31, count 0 2006.173.19:20:06.14#ibcon#about to write, iclass 31, count 0 2006.173.19:20:06.14#ibcon#wrote, iclass 31, count 0 2006.173.19:20:06.14#ibcon#about to read 3, iclass 31, count 0 2006.173.19:20:06.17#ibcon#read 3, iclass 31, count 0 2006.173.19:20:06.17#ibcon#about to read 4, iclass 31, count 0 2006.173.19:20:06.17#ibcon#read 4, iclass 31, count 0 2006.173.19:20:06.17#ibcon#about to read 5, iclass 31, count 0 2006.173.19:20:06.17#ibcon#read 5, iclass 31, count 0 2006.173.19:20:06.17#ibcon#about to read 6, iclass 31, count 0 2006.173.19:20:06.17#ibcon#read 6, iclass 31, count 0 2006.173.19:20:06.17#ibcon#end of sib2, iclass 31, count 0 2006.173.19:20:06.17#ibcon#*after write, iclass 31, count 0 2006.173.19:20:06.17#ibcon#*before return 0, iclass 31, count 0 2006.173.19:20:06.17#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.19:20:06.17#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.19:20:06.17#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.19:20:06.17#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.19:20:06.17$vck44/valo=7,864.99 2006.173.19:20:06.17#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.19:20:06.17#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.19:20:06.17#ibcon#ireg 17 cls_cnt 0 2006.173.19:20:06.17#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.19:20:06.17#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.19:20:06.17#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.19:20:06.17#ibcon#enter wrdev, iclass 33, count 0 2006.173.19:20:06.17#ibcon#first serial, iclass 33, count 0 2006.173.19:20:06.17#ibcon#enter sib2, iclass 33, count 0 2006.173.19:20:06.17#ibcon#flushed, iclass 33, count 0 2006.173.19:20:06.17#ibcon#about to write, iclass 33, count 0 2006.173.19:20:06.17#ibcon#wrote, iclass 33, count 0 2006.173.19:20:06.17#ibcon#about to read 3, iclass 33, count 0 2006.173.19:20:06.19#ibcon#read 3, iclass 33, count 0 2006.173.19:20:06.19#ibcon#about to read 4, iclass 33, count 0 2006.173.19:20:06.19#ibcon#read 4, iclass 33, count 0 2006.173.19:20:06.19#ibcon#about to read 5, iclass 33, count 0 2006.173.19:20:06.19#ibcon#read 5, iclass 33, count 0 2006.173.19:20:06.19#ibcon#about to read 6, iclass 33, count 0 2006.173.19:20:06.19#ibcon#read 6, iclass 33, count 0 2006.173.19:20:06.19#ibcon#end of sib2, iclass 33, count 0 2006.173.19:20:06.19#ibcon#*mode == 0, iclass 33, count 0 2006.173.19:20:06.19#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.19:20:06.19#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.19:20:06.19#ibcon#*before write, iclass 33, count 0 2006.173.19:20:06.19#ibcon#enter sib2, iclass 33, count 0 2006.173.19:20:06.19#ibcon#flushed, iclass 33, count 0 2006.173.19:20:06.19#ibcon#about to write, iclass 33, count 0 2006.173.19:20:06.19#ibcon#wrote, iclass 33, count 0 2006.173.19:20:06.19#ibcon#about to read 3, iclass 33, count 0 2006.173.19:20:06.23#ibcon#read 3, iclass 33, count 0 2006.173.19:20:06.23#ibcon#about to read 4, iclass 33, count 0 2006.173.19:20:06.23#ibcon#read 4, iclass 33, count 0 2006.173.19:20:06.23#ibcon#about to read 5, iclass 33, count 0 2006.173.19:20:06.23#ibcon#read 5, iclass 33, count 0 2006.173.19:20:06.23#ibcon#about to read 6, iclass 33, count 0 2006.173.19:20:06.23#ibcon#read 6, iclass 33, count 0 2006.173.19:20:06.23#ibcon#end of sib2, iclass 33, count 0 2006.173.19:20:06.23#ibcon#*after write, iclass 33, count 0 2006.173.19:20:06.23#ibcon#*before return 0, iclass 33, count 0 2006.173.19:20:06.23#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.19:20:06.23#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.19:20:06.23#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.19:20:06.23#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.19:20:06.23$vck44/va=7,4 2006.173.19:20:06.23#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.19:20:06.23#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.19:20:06.23#ibcon#ireg 11 cls_cnt 2 2006.173.19:20:06.23#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.19:20:06.29#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.19:20:06.29#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.19:20:06.29#ibcon#enter wrdev, iclass 35, count 2 2006.173.19:20:06.29#ibcon#first serial, iclass 35, count 2 2006.173.19:20:06.29#ibcon#enter sib2, iclass 35, count 2 2006.173.19:20:06.29#ibcon#flushed, iclass 35, count 2 2006.173.19:20:06.29#ibcon#about to write, iclass 35, count 2 2006.173.19:20:06.29#ibcon#wrote, iclass 35, count 2 2006.173.19:20:06.29#ibcon#about to read 3, iclass 35, count 2 2006.173.19:20:06.31#ibcon#read 3, iclass 35, count 2 2006.173.19:20:06.31#ibcon#about to read 4, iclass 35, count 2 2006.173.19:20:06.31#ibcon#read 4, iclass 35, count 2 2006.173.19:20:06.31#ibcon#about to read 5, iclass 35, count 2 2006.173.19:20:06.31#ibcon#read 5, iclass 35, count 2 2006.173.19:20:06.31#ibcon#about to read 6, iclass 35, count 2 2006.173.19:20:06.31#ibcon#read 6, iclass 35, count 2 2006.173.19:20:06.31#ibcon#end of sib2, iclass 35, count 2 2006.173.19:20:06.31#ibcon#*mode == 0, iclass 35, count 2 2006.173.19:20:06.31#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.19:20:06.31#ibcon#[25=AT07-04\r\n] 2006.173.19:20:06.31#ibcon#*before write, iclass 35, count 2 2006.173.19:20:06.31#ibcon#enter sib2, iclass 35, count 2 2006.173.19:20:06.31#ibcon#flushed, iclass 35, count 2 2006.173.19:20:06.31#ibcon#about to write, iclass 35, count 2 2006.173.19:20:06.31#ibcon#wrote, iclass 35, count 2 2006.173.19:20:06.31#ibcon#about to read 3, iclass 35, count 2 2006.173.19:20:06.34#ibcon#read 3, iclass 35, count 2 2006.173.19:20:06.34#ibcon#about to read 4, iclass 35, count 2 2006.173.19:20:06.34#ibcon#read 4, iclass 35, count 2 2006.173.19:20:06.34#ibcon#about to read 5, iclass 35, count 2 2006.173.19:20:06.34#ibcon#read 5, iclass 35, count 2 2006.173.19:20:06.34#ibcon#about to read 6, iclass 35, count 2 2006.173.19:20:06.34#ibcon#read 6, iclass 35, count 2 2006.173.19:20:06.34#ibcon#end of sib2, iclass 35, count 2 2006.173.19:20:06.34#ibcon#*after write, iclass 35, count 2 2006.173.19:20:06.34#ibcon#*before return 0, iclass 35, count 2 2006.173.19:20:06.34#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.19:20:06.34#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.19:20:06.34#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.19:20:06.34#ibcon#ireg 7 cls_cnt 0 2006.173.19:20:06.34#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.19:20:06.46#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.19:20:06.46#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.19:20:06.46#ibcon#enter wrdev, iclass 35, count 0 2006.173.19:20:06.46#ibcon#first serial, iclass 35, count 0 2006.173.19:20:06.46#ibcon#enter sib2, iclass 35, count 0 2006.173.19:20:06.46#ibcon#flushed, iclass 35, count 0 2006.173.19:20:06.46#ibcon#about to write, iclass 35, count 0 2006.173.19:20:06.46#ibcon#wrote, iclass 35, count 0 2006.173.19:20:06.46#ibcon#about to read 3, iclass 35, count 0 2006.173.19:20:06.48#ibcon#read 3, iclass 35, count 0 2006.173.19:20:06.48#ibcon#about to read 4, iclass 35, count 0 2006.173.19:20:06.48#ibcon#read 4, iclass 35, count 0 2006.173.19:20:06.48#ibcon#about to read 5, iclass 35, count 0 2006.173.19:20:06.48#ibcon#read 5, iclass 35, count 0 2006.173.19:20:06.48#ibcon#about to read 6, iclass 35, count 0 2006.173.19:20:06.48#ibcon#read 6, iclass 35, count 0 2006.173.19:20:06.48#ibcon#end of sib2, iclass 35, count 0 2006.173.19:20:06.48#ibcon#*mode == 0, iclass 35, count 0 2006.173.19:20:06.48#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.19:20:06.48#ibcon#[25=USB\r\n] 2006.173.19:20:06.48#ibcon#*before write, iclass 35, count 0 2006.173.19:20:06.48#ibcon#enter sib2, iclass 35, count 0 2006.173.19:20:06.48#ibcon#flushed, iclass 35, count 0 2006.173.19:20:06.48#ibcon#about to write, iclass 35, count 0 2006.173.19:20:06.48#ibcon#wrote, iclass 35, count 0 2006.173.19:20:06.48#ibcon#about to read 3, iclass 35, count 0 2006.173.19:20:06.51#ibcon#read 3, iclass 35, count 0 2006.173.19:20:06.51#ibcon#about to read 4, iclass 35, count 0 2006.173.19:20:06.51#ibcon#read 4, iclass 35, count 0 2006.173.19:20:06.51#ibcon#about to read 5, iclass 35, count 0 2006.173.19:20:06.51#ibcon#read 5, iclass 35, count 0 2006.173.19:20:06.51#ibcon#about to read 6, iclass 35, count 0 2006.173.19:20:06.51#ibcon#read 6, iclass 35, count 0 2006.173.19:20:06.51#ibcon#end of sib2, iclass 35, count 0 2006.173.19:20:06.51#ibcon#*after write, iclass 35, count 0 2006.173.19:20:06.51#ibcon#*before return 0, iclass 35, count 0 2006.173.19:20:06.51#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.19:20:06.51#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.19:20:06.51#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.19:20:06.51#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.19:20:06.51$vck44/valo=8,884.99 2006.173.19:20:06.51#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.19:20:06.51#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.19:20:06.51#ibcon#ireg 17 cls_cnt 0 2006.173.19:20:06.51#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.19:20:06.51#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.19:20:06.51#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.19:20:06.51#ibcon#enter wrdev, iclass 37, count 0 2006.173.19:20:06.51#ibcon#first serial, iclass 37, count 0 2006.173.19:20:06.51#ibcon#enter sib2, iclass 37, count 0 2006.173.19:20:06.51#ibcon#flushed, iclass 37, count 0 2006.173.19:20:06.51#ibcon#about to write, iclass 37, count 0 2006.173.19:20:06.51#ibcon#wrote, iclass 37, count 0 2006.173.19:20:06.51#ibcon#about to read 3, iclass 37, count 0 2006.173.19:20:06.53#ibcon#read 3, iclass 37, count 0 2006.173.19:20:06.53#ibcon#about to read 4, iclass 37, count 0 2006.173.19:20:06.53#ibcon#read 4, iclass 37, count 0 2006.173.19:20:06.53#ibcon#about to read 5, iclass 37, count 0 2006.173.19:20:06.53#ibcon#read 5, iclass 37, count 0 2006.173.19:20:06.53#ibcon#about to read 6, iclass 37, count 0 2006.173.19:20:06.53#ibcon#read 6, iclass 37, count 0 2006.173.19:20:06.53#ibcon#end of sib2, iclass 37, count 0 2006.173.19:20:06.53#ibcon#*mode == 0, iclass 37, count 0 2006.173.19:20:06.53#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.19:20:06.53#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.19:20:06.53#ibcon#*before write, iclass 37, count 0 2006.173.19:20:06.53#ibcon#enter sib2, iclass 37, count 0 2006.173.19:20:06.53#ibcon#flushed, iclass 37, count 0 2006.173.19:20:06.53#ibcon#about to write, iclass 37, count 0 2006.173.19:20:06.53#ibcon#wrote, iclass 37, count 0 2006.173.19:20:06.53#ibcon#about to read 3, iclass 37, count 0 2006.173.19:20:06.57#ibcon#read 3, iclass 37, count 0 2006.173.19:20:06.57#ibcon#about to read 4, iclass 37, count 0 2006.173.19:20:06.57#ibcon#read 4, iclass 37, count 0 2006.173.19:20:06.57#ibcon#about to read 5, iclass 37, count 0 2006.173.19:20:06.57#ibcon#read 5, iclass 37, count 0 2006.173.19:20:06.57#ibcon#about to read 6, iclass 37, count 0 2006.173.19:20:06.57#ibcon#read 6, iclass 37, count 0 2006.173.19:20:06.57#ibcon#end of sib2, iclass 37, count 0 2006.173.19:20:06.57#ibcon#*after write, iclass 37, count 0 2006.173.19:20:06.57#ibcon#*before return 0, iclass 37, count 0 2006.173.19:20:06.57#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.19:20:06.57#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.19:20:06.57#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.19:20:06.57#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.19:20:06.57$vck44/va=8,4 2006.173.19:20:06.57#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.19:20:06.57#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.19:20:06.57#ibcon#ireg 11 cls_cnt 2 2006.173.19:20:06.57#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.19:20:06.63#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.19:20:06.63#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.19:20:06.63#ibcon#enter wrdev, iclass 39, count 2 2006.173.19:20:06.63#ibcon#first serial, iclass 39, count 2 2006.173.19:20:06.63#ibcon#enter sib2, iclass 39, count 2 2006.173.19:20:06.63#ibcon#flushed, iclass 39, count 2 2006.173.19:20:06.63#ibcon#about to write, iclass 39, count 2 2006.173.19:20:06.63#ibcon#wrote, iclass 39, count 2 2006.173.19:20:06.63#ibcon#about to read 3, iclass 39, count 2 2006.173.19:20:06.65#ibcon#read 3, iclass 39, count 2 2006.173.19:20:06.65#ibcon#about to read 4, iclass 39, count 2 2006.173.19:20:06.65#ibcon#read 4, iclass 39, count 2 2006.173.19:20:06.65#ibcon#about to read 5, iclass 39, count 2 2006.173.19:20:06.65#ibcon#read 5, iclass 39, count 2 2006.173.19:20:06.65#ibcon#about to read 6, iclass 39, count 2 2006.173.19:20:06.65#ibcon#read 6, iclass 39, count 2 2006.173.19:20:06.65#ibcon#end of sib2, iclass 39, count 2 2006.173.19:20:06.65#ibcon#*mode == 0, iclass 39, count 2 2006.173.19:20:06.65#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.19:20:06.65#ibcon#[25=AT08-04\r\n] 2006.173.19:20:06.65#ibcon#*before write, iclass 39, count 2 2006.173.19:20:06.65#ibcon#enter sib2, iclass 39, count 2 2006.173.19:20:06.65#ibcon#flushed, iclass 39, count 2 2006.173.19:20:06.65#ibcon#about to write, iclass 39, count 2 2006.173.19:20:06.65#ibcon#wrote, iclass 39, count 2 2006.173.19:20:06.65#ibcon#about to read 3, iclass 39, count 2 2006.173.19:20:06.68#ibcon#read 3, iclass 39, count 2 2006.173.19:20:06.68#ibcon#about to read 4, iclass 39, count 2 2006.173.19:20:06.68#ibcon#read 4, iclass 39, count 2 2006.173.19:20:06.68#ibcon#about to read 5, iclass 39, count 2 2006.173.19:20:06.68#ibcon#read 5, iclass 39, count 2 2006.173.19:20:06.68#ibcon#about to read 6, iclass 39, count 2 2006.173.19:20:06.68#ibcon#read 6, iclass 39, count 2 2006.173.19:20:06.68#ibcon#end of sib2, iclass 39, count 2 2006.173.19:20:06.68#ibcon#*after write, iclass 39, count 2 2006.173.19:20:06.68#ibcon#*before return 0, iclass 39, count 2 2006.173.19:20:06.68#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.19:20:06.68#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.19:20:06.68#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.19:20:06.68#ibcon#ireg 7 cls_cnt 0 2006.173.19:20:06.68#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.19:20:06.80#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.19:20:06.80#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.19:20:06.80#ibcon#enter wrdev, iclass 39, count 0 2006.173.19:20:06.80#ibcon#first serial, iclass 39, count 0 2006.173.19:20:06.80#ibcon#enter sib2, iclass 39, count 0 2006.173.19:20:06.80#ibcon#flushed, iclass 39, count 0 2006.173.19:20:06.80#ibcon#about to write, iclass 39, count 0 2006.173.19:20:06.80#ibcon#wrote, iclass 39, count 0 2006.173.19:20:06.80#ibcon#about to read 3, iclass 39, count 0 2006.173.19:20:06.82#ibcon#read 3, iclass 39, count 0 2006.173.19:20:06.82#ibcon#about to read 4, iclass 39, count 0 2006.173.19:20:06.82#ibcon#read 4, iclass 39, count 0 2006.173.19:20:06.82#ibcon#about to read 5, iclass 39, count 0 2006.173.19:20:06.82#ibcon#read 5, iclass 39, count 0 2006.173.19:20:06.82#ibcon#about to read 6, iclass 39, count 0 2006.173.19:20:06.82#ibcon#read 6, iclass 39, count 0 2006.173.19:20:06.82#ibcon#end of sib2, iclass 39, count 0 2006.173.19:20:06.82#ibcon#*mode == 0, iclass 39, count 0 2006.173.19:20:06.82#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.19:20:06.82#ibcon#[25=USB\r\n] 2006.173.19:20:06.82#ibcon#*before write, iclass 39, count 0 2006.173.19:20:06.82#ibcon#enter sib2, iclass 39, count 0 2006.173.19:20:06.82#ibcon#flushed, iclass 39, count 0 2006.173.19:20:06.82#ibcon#about to write, iclass 39, count 0 2006.173.19:20:06.82#ibcon#wrote, iclass 39, count 0 2006.173.19:20:06.82#ibcon#about to read 3, iclass 39, count 0 2006.173.19:20:06.85#ibcon#read 3, iclass 39, count 0 2006.173.19:20:06.85#ibcon#about to read 4, iclass 39, count 0 2006.173.19:20:06.85#ibcon#read 4, iclass 39, count 0 2006.173.19:20:06.85#ibcon#about to read 5, iclass 39, count 0 2006.173.19:20:06.85#ibcon#read 5, iclass 39, count 0 2006.173.19:20:06.85#ibcon#about to read 6, iclass 39, count 0 2006.173.19:20:06.85#ibcon#read 6, iclass 39, count 0 2006.173.19:20:06.85#ibcon#end of sib2, iclass 39, count 0 2006.173.19:20:06.85#ibcon#*after write, iclass 39, count 0 2006.173.19:20:06.85#ibcon#*before return 0, iclass 39, count 0 2006.173.19:20:06.85#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.19:20:06.85#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.19:20:06.85#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.19:20:06.85#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.19:20:06.85$vck44/vblo=1,629.99 2006.173.19:20:06.85#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.19:20:06.85#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.19:20:06.85#ibcon#ireg 17 cls_cnt 0 2006.173.19:20:06.85#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.19:20:06.85#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.19:20:06.85#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.19:20:06.85#ibcon#enter wrdev, iclass 3, count 0 2006.173.19:20:06.85#ibcon#first serial, iclass 3, count 0 2006.173.19:20:06.85#ibcon#enter sib2, iclass 3, count 0 2006.173.19:20:06.85#ibcon#flushed, iclass 3, count 0 2006.173.19:20:06.85#ibcon#about to write, iclass 3, count 0 2006.173.19:20:06.85#ibcon#wrote, iclass 3, count 0 2006.173.19:20:06.85#ibcon#about to read 3, iclass 3, count 0 2006.173.19:20:06.87#ibcon#read 3, iclass 3, count 0 2006.173.19:20:06.87#ibcon#about to read 4, iclass 3, count 0 2006.173.19:20:06.87#ibcon#read 4, iclass 3, count 0 2006.173.19:20:06.87#ibcon#about to read 5, iclass 3, count 0 2006.173.19:20:06.87#ibcon#read 5, iclass 3, count 0 2006.173.19:20:06.87#ibcon#about to read 6, iclass 3, count 0 2006.173.19:20:06.87#ibcon#read 6, iclass 3, count 0 2006.173.19:20:06.87#ibcon#end of sib2, iclass 3, count 0 2006.173.19:20:06.87#ibcon#*mode == 0, iclass 3, count 0 2006.173.19:20:06.87#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.19:20:06.87#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.19:20:06.87#ibcon#*before write, iclass 3, count 0 2006.173.19:20:06.87#ibcon#enter sib2, iclass 3, count 0 2006.173.19:20:06.87#ibcon#flushed, iclass 3, count 0 2006.173.19:20:06.87#ibcon#about to write, iclass 3, count 0 2006.173.19:20:06.87#ibcon#wrote, iclass 3, count 0 2006.173.19:20:06.87#ibcon#about to read 3, iclass 3, count 0 2006.173.19:20:06.91#ibcon#read 3, iclass 3, count 0 2006.173.19:20:06.91#ibcon#about to read 4, iclass 3, count 0 2006.173.19:20:06.91#ibcon#read 4, iclass 3, count 0 2006.173.19:20:06.91#ibcon#about to read 5, iclass 3, count 0 2006.173.19:20:06.91#ibcon#read 5, iclass 3, count 0 2006.173.19:20:06.91#ibcon#about to read 6, iclass 3, count 0 2006.173.19:20:06.91#ibcon#read 6, iclass 3, count 0 2006.173.19:20:06.91#ibcon#end of sib2, iclass 3, count 0 2006.173.19:20:06.91#ibcon#*after write, iclass 3, count 0 2006.173.19:20:06.91#ibcon#*before return 0, iclass 3, count 0 2006.173.19:20:06.91#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.19:20:06.91#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.19:20:06.91#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.19:20:06.91#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.19:20:06.91$vck44/vb=1,4 2006.173.19:20:06.91#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.19:20:06.91#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.19:20:06.91#ibcon#ireg 11 cls_cnt 2 2006.173.19:20:06.91#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.19:20:06.91#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.19:20:06.91#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.19:20:06.91#ibcon#enter wrdev, iclass 5, count 2 2006.173.19:20:06.91#ibcon#first serial, iclass 5, count 2 2006.173.19:20:06.91#ibcon#enter sib2, iclass 5, count 2 2006.173.19:20:06.91#ibcon#flushed, iclass 5, count 2 2006.173.19:20:06.91#ibcon#about to write, iclass 5, count 2 2006.173.19:20:06.91#ibcon#wrote, iclass 5, count 2 2006.173.19:20:06.91#ibcon#about to read 3, iclass 5, count 2 2006.173.19:20:06.93#ibcon#read 3, iclass 5, count 2 2006.173.19:20:06.93#ibcon#about to read 4, iclass 5, count 2 2006.173.19:20:06.93#ibcon#read 4, iclass 5, count 2 2006.173.19:20:06.93#ibcon#about to read 5, iclass 5, count 2 2006.173.19:20:06.93#ibcon#read 5, iclass 5, count 2 2006.173.19:20:06.93#ibcon#about to read 6, iclass 5, count 2 2006.173.19:20:06.93#ibcon#read 6, iclass 5, count 2 2006.173.19:20:06.93#ibcon#end of sib2, iclass 5, count 2 2006.173.19:20:06.93#ibcon#*mode == 0, iclass 5, count 2 2006.173.19:20:06.93#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.19:20:06.93#ibcon#[27=AT01-04\r\n] 2006.173.19:20:06.93#ibcon#*before write, iclass 5, count 2 2006.173.19:20:06.93#ibcon#enter sib2, iclass 5, count 2 2006.173.19:20:06.93#ibcon#flushed, iclass 5, count 2 2006.173.19:20:06.93#ibcon#about to write, iclass 5, count 2 2006.173.19:20:06.93#ibcon#wrote, iclass 5, count 2 2006.173.19:20:06.93#ibcon#about to read 3, iclass 5, count 2 2006.173.19:20:06.96#ibcon#read 3, iclass 5, count 2 2006.173.19:20:06.96#ibcon#about to read 4, iclass 5, count 2 2006.173.19:20:06.96#ibcon#read 4, iclass 5, count 2 2006.173.19:20:06.96#ibcon#about to read 5, iclass 5, count 2 2006.173.19:20:06.96#ibcon#read 5, iclass 5, count 2 2006.173.19:20:06.96#ibcon#about to read 6, iclass 5, count 2 2006.173.19:20:06.96#ibcon#read 6, iclass 5, count 2 2006.173.19:20:06.96#ibcon#end of sib2, iclass 5, count 2 2006.173.19:20:06.96#ibcon#*after write, iclass 5, count 2 2006.173.19:20:06.96#ibcon#*before return 0, iclass 5, count 2 2006.173.19:20:06.96#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.19:20:06.96#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.19:20:06.96#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.19:20:06.96#ibcon#ireg 7 cls_cnt 0 2006.173.19:20:06.96#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.19:20:07.08#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.19:20:07.08#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.19:20:07.08#ibcon#enter wrdev, iclass 5, count 0 2006.173.19:20:07.08#ibcon#first serial, iclass 5, count 0 2006.173.19:20:07.08#ibcon#enter sib2, iclass 5, count 0 2006.173.19:20:07.08#ibcon#flushed, iclass 5, count 0 2006.173.19:20:07.08#ibcon#about to write, iclass 5, count 0 2006.173.19:20:07.08#ibcon#wrote, iclass 5, count 0 2006.173.19:20:07.08#ibcon#about to read 3, iclass 5, count 0 2006.173.19:20:07.10#ibcon#read 3, iclass 5, count 0 2006.173.19:20:07.10#ibcon#about to read 4, iclass 5, count 0 2006.173.19:20:07.10#ibcon#read 4, iclass 5, count 0 2006.173.19:20:07.10#ibcon#about to read 5, iclass 5, count 0 2006.173.19:20:07.10#ibcon#read 5, iclass 5, count 0 2006.173.19:20:07.10#ibcon#about to read 6, iclass 5, count 0 2006.173.19:20:07.10#ibcon#read 6, iclass 5, count 0 2006.173.19:20:07.10#ibcon#end of sib2, iclass 5, count 0 2006.173.19:20:07.10#ibcon#*mode == 0, iclass 5, count 0 2006.173.19:20:07.10#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.19:20:07.10#ibcon#[27=USB\r\n] 2006.173.19:20:07.10#ibcon#*before write, iclass 5, count 0 2006.173.19:20:07.10#ibcon#enter sib2, iclass 5, count 0 2006.173.19:20:07.10#ibcon#flushed, iclass 5, count 0 2006.173.19:20:07.10#ibcon#about to write, iclass 5, count 0 2006.173.19:20:07.10#ibcon#wrote, iclass 5, count 0 2006.173.19:20:07.10#ibcon#about to read 3, iclass 5, count 0 2006.173.19:20:07.13#ibcon#read 3, iclass 5, count 0 2006.173.19:20:07.13#ibcon#about to read 4, iclass 5, count 0 2006.173.19:20:07.13#ibcon#read 4, iclass 5, count 0 2006.173.19:20:07.13#ibcon#about to read 5, iclass 5, count 0 2006.173.19:20:07.13#ibcon#read 5, iclass 5, count 0 2006.173.19:20:07.13#ibcon#about to read 6, iclass 5, count 0 2006.173.19:20:07.13#ibcon#read 6, iclass 5, count 0 2006.173.19:20:07.13#ibcon#end of sib2, iclass 5, count 0 2006.173.19:20:07.13#ibcon#*after write, iclass 5, count 0 2006.173.19:20:07.13#ibcon#*before return 0, iclass 5, count 0 2006.173.19:20:07.13#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.19:20:07.13#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.19:20:07.13#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.19:20:07.13#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.19:20:07.13$vck44/vblo=2,634.99 2006.173.19:20:07.13#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.19:20:07.13#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.19:20:07.13#ibcon#ireg 17 cls_cnt 0 2006.173.19:20:07.13#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.19:20:07.13#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.19:20:07.13#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.19:20:07.13#ibcon#enter wrdev, iclass 7, count 0 2006.173.19:20:07.13#ibcon#first serial, iclass 7, count 0 2006.173.19:20:07.13#ibcon#enter sib2, iclass 7, count 0 2006.173.19:20:07.13#ibcon#flushed, iclass 7, count 0 2006.173.19:20:07.13#ibcon#about to write, iclass 7, count 0 2006.173.19:20:07.13#ibcon#wrote, iclass 7, count 0 2006.173.19:20:07.13#ibcon#about to read 3, iclass 7, count 0 2006.173.19:20:07.15#ibcon#read 3, iclass 7, count 0 2006.173.19:20:07.15#ibcon#about to read 4, iclass 7, count 0 2006.173.19:20:07.15#ibcon#read 4, iclass 7, count 0 2006.173.19:20:07.15#ibcon#about to read 5, iclass 7, count 0 2006.173.19:20:07.15#ibcon#read 5, iclass 7, count 0 2006.173.19:20:07.15#ibcon#about to read 6, iclass 7, count 0 2006.173.19:20:07.15#ibcon#read 6, iclass 7, count 0 2006.173.19:20:07.15#ibcon#end of sib2, iclass 7, count 0 2006.173.19:20:07.15#ibcon#*mode == 0, iclass 7, count 0 2006.173.19:20:07.15#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.19:20:07.15#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.19:20:07.15#ibcon#*before write, iclass 7, count 0 2006.173.19:20:07.15#ibcon#enter sib2, iclass 7, count 0 2006.173.19:20:07.15#ibcon#flushed, iclass 7, count 0 2006.173.19:20:07.15#ibcon#about to write, iclass 7, count 0 2006.173.19:20:07.15#ibcon#wrote, iclass 7, count 0 2006.173.19:20:07.15#ibcon#about to read 3, iclass 7, count 0 2006.173.19:20:07.19#ibcon#read 3, iclass 7, count 0 2006.173.19:20:07.19#ibcon#about to read 4, iclass 7, count 0 2006.173.19:20:07.19#ibcon#read 4, iclass 7, count 0 2006.173.19:20:07.19#ibcon#about to read 5, iclass 7, count 0 2006.173.19:20:07.19#ibcon#read 5, iclass 7, count 0 2006.173.19:20:07.19#ibcon#about to read 6, iclass 7, count 0 2006.173.19:20:07.19#ibcon#read 6, iclass 7, count 0 2006.173.19:20:07.19#ibcon#end of sib2, iclass 7, count 0 2006.173.19:20:07.19#ibcon#*after write, iclass 7, count 0 2006.173.19:20:07.19#ibcon#*before return 0, iclass 7, count 0 2006.173.19:20:07.19#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.19:20:07.19#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.19:20:07.19#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.19:20:07.19#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.19:20:07.19$vck44/vb=2,4 2006.173.19:20:07.19#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.19:20:07.19#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.19:20:07.19#ibcon#ireg 11 cls_cnt 2 2006.173.19:20:07.19#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.19:20:07.25#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.19:20:07.25#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.19:20:07.25#ibcon#enter wrdev, iclass 11, count 2 2006.173.19:20:07.25#ibcon#first serial, iclass 11, count 2 2006.173.19:20:07.25#ibcon#enter sib2, iclass 11, count 2 2006.173.19:20:07.25#ibcon#flushed, iclass 11, count 2 2006.173.19:20:07.25#ibcon#about to write, iclass 11, count 2 2006.173.19:20:07.25#ibcon#wrote, iclass 11, count 2 2006.173.19:20:07.25#ibcon#about to read 3, iclass 11, count 2 2006.173.19:20:07.27#ibcon#read 3, iclass 11, count 2 2006.173.19:20:07.27#ibcon#about to read 4, iclass 11, count 2 2006.173.19:20:07.27#ibcon#read 4, iclass 11, count 2 2006.173.19:20:07.27#ibcon#about to read 5, iclass 11, count 2 2006.173.19:20:07.27#ibcon#read 5, iclass 11, count 2 2006.173.19:20:07.27#ibcon#about to read 6, iclass 11, count 2 2006.173.19:20:07.27#ibcon#read 6, iclass 11, count 2 2006.173.19:20:07.27#ibcon#end of sib2, iclass 11, count 2 2006.173.19:20:07.27#ibcon#*mode == 0, iclass 11, count 2 2006.173.19:20:07.27#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.19:20:07.27#ibcon#[27=AT02-04\r\n] 2006.173.19:20:07.27#ibcon#*before write, iclass 11, count 2 2006.173.19:20:07.27#ibcon#enter sib2, iclass 11, count 2 2006.173.19:20:07.27#ibcon#flushed, iclass 11, count 2 2006.173.19:20:07.27#ibcon#about to write, iclass 11, count 2 2006.173.19:20:07.27#ibcon#wrote, iclass 11, count 2 2006.173.19:20:07.27#ibcon#about to read 3, iclass 11, count 2 2006.173.19:20:07.30#ibcon#read 3, iclass 11, count 2 2006.173.19:20:07.30#ibcon#about to read 4, iclass 11, count 2 2006.173.19:20:07.30#ibcon#read 4, iclass 11, count 2 2006.173.19:20:07.30#ibcon#about to read 5, iclass 11, count 2 2006.173.19:20:07.30#ibcon#read 5, iclass 11, count 2 2006.173.19:20:07.30#ibcon#about to read 6, iclass 11, count 2 2006.173.19:20:07.30#ibcon#read 6, iclass 11, count 2 2006.173.19:20:07.30#ibcon#end of sib2, iclass 11, count 2 2006.173.19:20:07.30#ibcon#*after write, iclass 11, count 2 2006.173.19:20:07.30#ibcon#*before return 0, iclass 11, count 2 2006.173.19:20:07.30#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.19:20:07.30#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.19:20:07.30#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.19:20:07.30#ibcon#ireg 7 cls_cnt 0 2006.173.19:20:07.30#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.19:20:07.42#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.19:20:07.42#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.19:20:07.42#ibcon#enter wrdev, iclass 11, count 0 2006.173.19:20:07.42#ibcon#first serial, iclass 11, count 0 2006.173.19:20:07.42#ibcon#enter sib2, iclass 11, count 0 2006.173.19:20:07.42#ibcon#flushed, iclass 11, count 0 2006.173.19:20:07.42#ibcon#about to write, iclass 11, count 0 2006.173.19:20:07.42#ibcon#wrote, iclass 11, count 0 2006.173.19:20:07.42#ibcon#about to read 3, iclass 11, count 0 2006.173.19:20:07.44#ibcon#read 3, iclass 11, count 0 2006.173.19:20:07.44#ibcon#about to read 4, iclass 11, count 0 2006.173.19:20:07.44#ibcon#read 4, iclass 11, count 0 2006.173.19:20:07.44#ibcon#about to read 5, iclass 11, count 0 2006.173.19:20:07.44#ibcon#read 5, iclass 11, count 0 2006.173.19:20:07.44#ibcon#about to read 6, iclass 11, count 0 2006.173.19:20:07.44#ibcon#read 6, iclass 11, count 0 2006.173.19:20:07.44#ibcon#end of sib2, iclass 11, count 0 2006.173.19:20:07.44#ibcon#*mode == 0, iclass 11, count 0 2006.173.19:20:07.44#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.19:20:07.44#ibcon#[27=USB\r\n] 2006.173.19:20:07.44#ibcon#*before write, iclass 11, count 0 2006.173.19:20:07.44#ibcon#enter sib2, iclass 11, count 0 2006.173.19:20:07.44#ibcon#flushed, iclass 11, count 0 2006.173.19:20:07.44#ibcon#about to write, iclass 11, count 0 2006.173.19:20:07.44#ibcon#wrote, iclass 11, count 0 2006.173.19:20:07.44#ibcon#about to read 3, iclass 11, count 0 2006.173.19:20:07.47#ibcon#read 3, iclass 11, count 0 2006.173.19:20:07.47#ibcon#about to read 4, iclass 11, count 0 2006.173.19:20:07.47#ibcon#read 4, iclass 11, count 0 2006.173.19:20:07.47#ibcon#about to read 5, iclass 11, count 0 2006.173.19:20:07.47#ibcon#read 5, iclass 11, count 0 2006.173.19:20:07.47#ibcon#about to read 6, iclass 11, count 0 2006.173.19:20:07.47#ibcon#read 6, iclass 11, count 0 2006.173.19:20:07.47#ibcon#end of sib2, iclass 11, count 0 2006.173.19:20:07.47#ibcon#*after write, iclass 11, count 0 2006.173.19:20:07.47#ibcon#*before return 0, iclass 11, count 0 2006.173.19:20:07.47#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.19:20:07.47#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.19:20:07.47#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.19:20:07.47#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.19:20:07.47$vck44/vblo=3,649.99 2006.173.19:20:07.47#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.19:20:07.47#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.19:20:07.47#ibcon#ireg 17 cls_cnt 0 2006.173.19:20:07.47#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.19:20:07.47#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.19:20:07.47#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.19:20:07.47#ibcon#enter wrdev, iclass 13, count 0 2006.173.19:20:07.47#ibcon#first serial, iclass 13, count 0 2006.173.19:20:07.47#ibcon#enter sib2, iclass 13, count 0 2006.173.19:20:07.47#ibcon#flushed, iclass 13, count 0 2006.173.19:20:07.47#ibcon#about to write, iclass 13, count 0 2006.173.19:20:07.47#ibcon#wrote, iclass 13, count 0 2006.173.19:20:07.47#ibcon#about to read 3, iclass 13, count 0 2006.173.19:20:07.49#ibcon#read 3, iclass 13, count 0 2006.173.19:20:07.49#ibcon#about to read 4, iclass 13, count 0 2006.173.19:20:07.49#ibcon#read 4, iclass 13, count 0 2006.173.19:20:07.49#ibcon#about to read 5, iclass 13, count 0 2006.173.19:20:07.49#ibcon#read 5, iclass 13, count 0 2006.173.19:20:07.49#ibcon#about to read 6, iclass 13, count 0 2006.173.19:20:07.49#ibcon#read 6, iclass 13, count 0 2006.173.19:20:07.49#ibcon#end of sib2, iclass 13, count 0 2006.173.19:20:07.49#ibcon#*mode == 0, iclass 13, count 0 2006.173.19:20:07.49#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.19:20:07.49#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.19:20:07.49#ibcon#*before write, iclass 13, count 0 2006.173.19:20:07.49#ibcon#enter sib2, iclass 13, count 0 2006.173.19:20:07.49#ibcon#flushed, iclass 13, count 0 2006.173.19:20:07.49#ibcon#about to write, iclass 13, count 0 2006.173.19:20:07.49#ibcon#wrote, iclass 13, count 0 2006.173.19:20:07.49#ibcon#about to read 3, iclass 13, count 0 2006.173.19:20:07.53#ibcon#read 3, iclass 13, count 0 2006.173.19:20:07.53#ibcon#about to read 4, iclass 13, count 0 2006.173.19:20:07.53#ibcon#read 4, iclass 13, count 0 2006.173.19:20:07.53#ibcon#about to read 5, iclass 13, count 0 2006.173.19:20:07.53#ibcon#read 5, iclass 13, count 0 2006.173.19:20:07.53#ibcon#about to read 6, iclass 13, count 0 2006.173.19:20:07.53#ibcon#read 6, iclass 13, count 0 2006.173.19:20:07.53#ibcon#end of sib2, iclass 13, count 0 2006.173.19:20:07.53#ibcon#*after write, iclass 13, count 0 2006.173.19:20:07.53#ibcon#*before return 0, iclass 13, count 0 2006.173.19:20:07.53#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.19:20:07.53#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.19:20:07.53#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.19:20:07.53#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.19:20:07.53$vck44/vb=3,4 2006.173.19:20:07.53#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.19:20:07.53#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.19:20:07.53#ibcon#ireg 11 cls_cnt 2 2006.173.19:20:07.53#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.19:20:07.59#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.19:20:07.59#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.19:20:07.59#ibcon#enter wrdev, iclass 15, count 2 2006.173.19:20:07.59#ibcon#first serial, iclass 15, count 2 2006.173.19:20:07.59#ibcon#enter sib2, iclass 15, count 2 2006.173.19:20:07.59#ibcon#flushed, iclass 15, count 2 2006.173.19:20:07.59#ibcon#about to write, iclass 15, count 2 2006.173.19:20:07.59#ibcon#wrote, iclass 15, count 2 2006.173.19:20:07.59#ibcon#about to read 3, iclass 15, count 2 2006.173.19:20:07.61#ibcon#read 3, iclass 15, count 2 2006.173.19:20:07.61#ibcon#about to read 4, iclass 15, count 2 2006.173.19:20:07.61#ibcon#read 4, iclass 15, count 2 2006.173.19:20:07.61#ibcon#about to read 5, iclass 15, count 2 2006.173.19:20:07.61#ibcon#read 5, iclass 15, count 2 2006.173.19:20:07.61#ibcon#about to read 6, iclass 15, count 2 2006.173.19:20:07.61#ibcon#read 6, iclass 15, count 2 2006.173.19:20:07.61#ibcon#end of sib2, iclass 15, count 2 2006.173.19:20:07.61#ibcon#*mode == 0, iclass 15, count 2 2006.173.19:20:07.61#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.19:20:07.61#ibcon#[27=AT03-04\r\n] 2006.173.19:20:07.61#ibcon#*before write, iclass 15, count 2 2006.173.19:20:07.61#ibcon#enter sib2, iclass 15, count 2 2006.173.19:20:07.61#ibcon#flushed, iclass 15, count 2 2006.173.19:20:07.61#ibcon#about to write, iclass 15, count 2 2006.173.19:20:07.61#ibcon#wrote, iclass 15, count 2 2006.173.19:20:07.61#ibcon#about to read 3, iclass 15, count 2 2006.173.19:20:07.64#ibcon#read 3, iclass 15, count 2 2006.173.19:20:07.64#ibcon#about to read 4, iclass 15, count 2 2006.173.19:20:07.64#ibcon#read 4, iclass 15, count 2 2006.173.19:20:07.64#ibcon#about to read 5, iclass 15, count 2 2006.173.19:20:07.64#ibcon#read 5, iclass 15, count 2 2006.173.19:20:07.64#ibcon#about to read 6, iclass 15, count 2 2006.173.19:20:07.64#ibcon#read 6, iclass 15, count 2 2006.173.19:20:07.64#ibcon#end of sib2, iclass 15, count 2 2006.173.19:20:07.64#ibcon#*after write, iclass 15, count 2 2006.173.19:20:07.64#ibcon#*before return 0, iclass 15, count 2 2006.173.19:20:07.64#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.19:20:07.64#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.19:20:07.64#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.19:20:07.64#ibcon#ireg 7 cls_cnt 0 2006.173.19:20:07.64#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.19:20:07.76#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.19:20:07.76#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.19:20:07.76#ibcon#enter wrdev, iclass 15, count 0 2006.173.19:20:07.76#ibcon#first serial, iclass 15, count 0 2006.173.19:20:07.76#ibcon#enter sib2, iclass 15, count 0 2006.173.19:20:07.76#ibcon#flushed, iclass 15, count 0 2006.173.19:20:07.76#ibcon#about to write, iclass 15, count 0 2006.173.19:20:07.76#ibcon#wrote, iclass 15, count 0 2006.173.19:20:07.76#ibcon#about to read 3, iclass 15, count 0 2006.173.19:20:07.78#ibcon#read 3, iclass 15, count 0 2006.173.19:20:07.78#ibcon#about to read 4, iclass 15, count 0 2006.173.19:20:07.78#ibcon#read 4, iclass 15, count 0 2006.173.19:20:07.78#ibcon#about to read 5, iclass 15, count 0 2006.173.19:20:07.78#ibcon#read 5, iclass 15, count 0 2006.173.19:20:07.78#ibcon#about to read 6, iclass 15, count 0 2006.173.19:20:07.78#ibcon#read 6, iclass 15, count 0 2006.173.19:20:07.78#ibcon#end of sib2, iclass 15, count 0 2006.173.19:20:07.78#ibcon#*mode == 0, iclass 15, count 0 2006.173.19:20:07.78#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.19:20:07.78#ibcon#[27=USB\r\n] 2006.173.19:20:07.78#ibcon#*before write, iclass 15, count 0 2006.173.19:20:07.78#ibcon#enter sib2, iclass 15, count 0 2006.173.19:20:07.78#ibcon#flushed, iclass 15, count 0 2006.173.19:20:07.78#ibcon#about to write, iclass 15, count 0 2006.173.19:20:07.78#ibcon#wrote, iclass 15, count 0 2006.173.19:20:07.78#ibcon#about to read 3, iclass 15, count 0 2006.173.19:20:07.81#ibcon#read 3, iclass 15, count 0 2006.173.19:20:07.81#ibcon#about to read 4, iclass 15, count 0 2006.173.19:20:07.81#ibcon#read 4, iclass 15, count 0 2006.173.19:20:07.81#ibcon#about to read 5, iclass 15, count 0 2006.173.19:20:07.81#ibcon#read 5, iclass 15, count 0 2006.173.19:20:07.81#ibcon#about to read 6, iclass 15, count 0 2006.173.19:20:07.81#ibcon#read 6, iclass 15, count 0 2006.173.19:20:07.81#ibcon#end of sib2, iclass 15, count 0 2006.173.19:20:07.81#ibcon#*after write, iclass 15, count 0 2006.173.19:20:07.81#ibcon#*before return 0, iclass 15, count 0 2006.173.19:20:07.81#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.19:20:07.81#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.19:20:07.81#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.19:20:07.81#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.19:20:07.81$vck44/vblo=4,679.99 2006.173.19:20:07.81#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.19:20:07.81#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.19:20:07.81#ibcon#ireg 17 cls_cnt 0 2006.173.19:20:07.81#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.19:20:07.81#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.19:20:07.81#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.19:20:07.81#ibcon#enter wrdev, iclass 17, count 0 2006.173.19:20:07.81#ibcon#first serial, iclass 17, count 0 2006.173.19:20:07.81#ibcon#enter sib2, iclass 17, count 0 2006.173.19:20:07.81#ibcon#flushed, iclass 17, count 0 2006.173.19:20:07.81#ibcon#about to write, iclass 17, count 0 2006.173.19:20:07.81#ibcon#wrote, iclass 17, count 0 2006.173.19:20:07.81#ibcon#about to read 3, iclass 17, count 0 2006.173.19:20:07.83#ibcon#read 3, iclass 17, count 0 2006.173.19:20:07.83#ibcon#about to read 4, iclass 17, count 0 2006.173.19:20:07.83#ibcon#read 4, iclass 17, count 0 2006.173.19:20:07.83#ibcon#about to read 5, iclass 17, count 0 2006.173.19:20:07.83#ibcon#read 5, iclass 17, count 0 2006.173.19:20:07.83#ibcon#about to read 6, iclass 17, count 0 2006.173.19:20:07.83#ibcon#read 6, iclass 17, count 0 2006.173.19:20:07.83#ibcon#end of sib2, iclass 17, count 0 2006.173.19:20:07.83#ibcon#*mode == 0, iclass 17, count 0 2006.173.19:20:07.83#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.19:20:07.83#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.19:20:07.83#ibcon#*before write, iclass 17, count 0 2006.173.19:20:07.83#ibcon#enter sib2, iclass 17, count 0 2006.173.19:20:07.83#ibcon#flushed, iclass 17, count 0 2006.173.19:20:07.83#ibcon#about to write, iclass 17, count 0 2006.173.19:20:07.83#ibcon#wrote, iclass 17, count 0 2006.173.19:20:07.83#ibcon#about to read 3, iclass 17, count 0 2006.173.19:20:07.87#ibcon#read 3, iclass 17, count 0 2006.173.19:20:07.87#ibcon#about to read 4, iclass 17, count 0 2006.173.19:20:07.87#ibcon#read 4, iclass 17, count 0 2006.173.19:20:07.87#ibcon#about to read 5, iclass 17, count 0 2006.173.19:20:07.87#ibcon#read 5, iclass 17, count 0 2006.173.19:20:07.87#ibcon#about to read 6, iclass 17, count 0 2006.173.19:20:07.87#ibcon#read 6, iclass 17, count 0 2006.173.19:20:07.87#ibcon#end of sib2, iclass 17, count 0 2006.173.19:20:07.87#ibcon#*after write, iclass 17, count 0 2006.173.19:20:07.87#ibcon#*before return 0, iclass 17, count 0 2006.173.19:20:07.87#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.19:20:07.87#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.19:20:07.87#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.19:20:07.87#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.19:20:07.87$vck44/vb=4,4 2006.173.19:20:07.87#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.19:20:07.87#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.19:20:07.87#ibcon#ireg 11 cls_cnt 2 2006.173.19:20:07.87#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.19:20:07.93#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.19:20:07.93#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.19:20:07.93#ibcon#enter wrdev, iclass 19, count 2 2006.173.19:20:07.93#ibcon#first serial, iclass 19, count 2 2006.173.19:20:07.93#ibcon#enter sib2, iclass 19, count 2 2006.173.19:20:07.93#ibcon#flushed, iclass 19, count 2 2006.173.19:20:07.93#ibcon#about to write, iclass 19, count 2 2006.173.19:20:07.93#ibcon#wrote, iclass 19, count 2 2006.173.19:20:07.93#ibcon#about to read 3, iclass 19, count 2 2006.173.19:20:07.95#ibcon#read 3, iclass 19, count 2 2006.173.19:20:07.95#ibcon#about to read 4, iclass 19, count 2 2006.173.19:20:07.95#ibcon#read 4, iclass 19, count 2 2006.173.19:20:07.95#ibcon#about to read 5, iclass 19, count 2 2006.173.19:20:07.95#ibcon#read 5, iclass 19, count 2 2006.173.19:20:07.95#ibcon#about to read 6, iclass 19, count 2 2006.173.19:20:07.95#ibcon#read 6, iclass 19, count 2 2006.173.19:20:07.95#ibcon#end of sib2, iclass 19, count 2 2006.173.19:20:07.95#ibcon#*mode == 0, iclass 19, count 2 2006.173.19:20:07.95#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.19:20:07.95#ibcon#[27=AT04-04\r\n] 2006.173.19:20:07.95#ibcon#*before write, iclass 19, count 2 2006.173.19:20:07.95#ibcon#enter sib2, iclass 19, count 2 2006.173.19:20:07.95#ibcon#flushed, iclass 19, count 2 2006.173.19:20:07.95#ibcon#about to write, iclass 19, count 2 2006.173.19:20:07.95#ibcon#wrote, iclass 19, count 2 2006.173.19:20:07.95#ibcon#about to read 3, iclass 19, count 2 2006.173.19:20:07.98#ibcon#read 3, iclass 19, count 2 2006.173.19:20:07.98#ibcon#about to read 4, iclass 19, count 2 2006.173.19:20:07.98#ibcon#read 4, iclass 19, count 2 2006.173.19:20:07.98#ibcon#about to read 5, iclass 19, count 2 2006.173.19:20:07.98#ibcon#read 5, iclass 19, count 2 2006.173.19:20:07.98#ibcon#about to read 6, iclass 19, count 2 2006.173.19:20:07.98#ibcon#read 6, iclass 19, count 2 2006.173.19:20:07.98#ibcon#end of sib2, iclass 19, count 2 2006.173.19:20:07.98#ibcon#*after write, iclass 19, count 2 2006.173.19:20:07.98#ibcon#*before return 0, iclass 19, count 2 2006.173.19:20:07.98#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.19:20:07.98#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.19:20:07.98#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.19:20:07.98#ibcon#ireg 7 cls_cnt 0 2006.173.19:20:07.98#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.19:20:08.10#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.19:20:08.10#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.19:20:08.10#ibcon#enter wrdev, iclass 19, count 0 2006.173.19:20:08.10#ibcon#first serial, iclass 19, count 0 2006.173.19:20:08.10#ibcon#enter sib2, iclass 19, count 0 2006.173.19:20:08.10#ibcon#flushed, iclass 19, count 0 2006.173.19:20:08.10#ibcon#about to write, iclass 19, count 0 2006.173.19:20:08.10#ibcon#wrote, iclass 19, count 0 2006.173.19:20:08.10#ibcon#about to read 3, iclass 19, count 0 2006.173.19:20:08.12#ibcon#read 3, iclass 19, count 0 2006.173.19:20:08.12#ibcon#about to read 4, iclass 19, count 0 2006.173.19:20:08.12#ibcon#read 4, iclass 19, count 0 2006.173.19:20:08.12#ibcon#about to read 5, iclass 19, count 0 2006.173.19:20:08.12#ibcon#read 5, iclass 19, count 0 2006.173.19:20:08.12#ibcon#about to read 6, iclass 19, count 0 2006.173.19:20:08.12#ibcon#read 6, iclass 19, count 0 2006.173.19:20:08.12#ibcon#end of sib2, iclass 19, count 0 2006.173.19:20:08.12#ibcon#*mode == 0, iclass 19, count 0 2006.173.19:20:08.12#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.19:20:08.12#ibcon#[27=USB\r\n] 2006.173.19:20:08.12#ibcon#*before write, iclass 19, count 0 2006.173.19:20:08.12#ibcon#enter sib2, iclass 19, count 0 2006.173.19:20:08.12#ibcon#flushed, iclass 19, count 0 2006.173.19:20:08.12#ibcon#about to write, iclass 19, count 0 2006.173.19:20:08.12#ibcon#wrote, iclass 19, count 0 2006.173.19:20:08.12#ibcon#about to read 3, iclass 19, count 0 2006.173.19:20:08.15#ibcon#read 3, iclass 19, count 0 2006.173.19:20:08.15#ibcon#about to read 4, iclass 19, count 0 2006.173.19:20:08.15#ibcon#read 4, iclass 19, count 0 2006.173.19:20:08.15#ibcon#about to read 5, iclass 19, count 0 2006.173.19:20:08.15#ibcon#read 5, iclass 19, count 0 2006.173.19:20:08.15#ibcon#about to read 6, iclass 19, count 0 2006.173.19:20:08.15#ibcon#read 6, iclass 19, count 0 2006.173.19:20:08.15#ibcon#end of sib2, iclass 19, count 0 2006.173.19:20:08.15#ibcon#*after write, iclass 19, count 0 2006.173.19:20:08.15#ibcon#*before return 0, iclass 19, count 0 2006.173.19:20:08.15#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.19:20:08.15#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.19:20:08.15#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.19:20:08.15#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.19:20:08.15$vck44/vblo=5,709.99 2006.173.19:20:08.15#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.19:20:08.15#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.19:20:08.15#ibcon#ireg 17 cls_cnt 0 2006.173.19:20:08.15#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.19:20:08.15#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.19:20:08.15#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.19:20:08.15#ibcon#enter wrdev, iclass 21, count 0 2006.173.19:20:08.15#ibcon#first serial, iclass 21, count 0 2006.173.19:20:08.15#ibcon#enter sib2, iclass 21, count 0 2006.173.19:20:08.15#ibcon#flushed, iclass 21, count 0 2006.173.19:20:08.15#ibcon#about to write, iclass 21, count 0 2006.173.19:20:08.15#ibcon#wrote, iclass 21, count 0 2006.173.19:20:08.15#ibcon#about to read 3, iclass 21, count 0 2006.173.19:20:08.17#ibcon#read 3, iclass 21, count 0 2006.173.19:20:08.17#ibcon#about to read 4, iclass 21, count 0 2006.173.19:20:08.17#ibcon#read 4, iclass 21, count 0 2006.173.19:20:08.17#ibcon#about to read 5, iclass 21, count 0 2006.173.19:20:08.17#ibcon#read 5, iclass 21, count 0 2006.173.19:20:08.17#ibcon#about to read 6, iclass 21, count 0 2006.173.19:20:08.17#ibcon#read 6, iclass 21, count 0 2006.173.19:20:08.17#ibcon#end of sib2, iclass 21, count 0 2006.173.19:20:08.17#ibcon#*mode == 0, iclass 21, count 0 2006.173.19:20:08.17#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.19:20:08.17#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.19:20:08.17#ibcon#*before write, iclass 21, count 0 2006.173.19:20:08.17#ibcon#enter sib2, iclass 21, count 0 2006.173.19:20:08.17#ibcon#flushed, iclass 21, count 0 2006.173.19:20:08.17#ibcon#about to write, iclass 21, count 0 2006.173.19:20:08.17#ibcon#wrote, iclass 21, count 0 2006.173.19:20:08.17#ibcon#about to read 3, iclass 21, count 0 2006.173.19:20:08.21#ibcon#read 3, iclass 21, count 0 2006.173.19:20:08.21#ibcon#about to read 4, iclass 21, count 0 2006.173.19:20:08.21#ibcon#read 4, iclass 21, count 0 2006.173.19:20:08.21#ibcon#about to read 5, iclass 21, count 0 2006.173.19:20:08.21#ibcon#read 5, iclass 21, count 0 2006.173.19:20:08.21#ibcon#about to read 6, iclass 21, count 0 2006.173.19:20:08.21#ibcon#read 6, iclass 21, count 0 2006.173.19:20:08.21#ibcon#end of sib2, iclass 21, count 0 2006.173.19:20:08.21#ibcon#*after write, iclass 21, count 0 2006.173.19:20:08.21#ibcon#*before return 0, iclass 21, count 0 2006.173.19:20:08.21#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.19:20:08.21#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.19:20:08.21#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.19:20:08.21#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.19:20:08.21$vck44/vb=5,4 2006.173.19:20:08.21#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.19:20:08.21#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.19:20:08.21#ibcon#ireg 11 cls_cnt 2 2006.173.19:20:08.21#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.19:20:08.27#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.19:20:08.27#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.19:20:08.27#ibcon#enter wrdev, iclass 23, count 2 2006.173.19:20:08.27#ibcon#first serial, iclass 23, count 2 2006.173.19:20:08.27#ibcon#enter sib2, iclass 23, count 2 2006.173.19:20:08.27#ibcon#flushed, iclass 23, count 2 2006.173.19:20:08.27#ibcon#about to write, iclass 23, count 2 2006.173.19:20:08.27#ibcon#wrote, iclass 23, count 2 2006.173.19:20:08.27#ibcon#about to read 3, iclass 23, count 2 2006.173.19:20:08.29#ibcon#read 3, iclass 23, count 2 2006.173.19:20:08.29#ibcon#about to read 4, iclass 23, count 2 2006.173.19:20:08.29#ibcon#read 4, iclass 23, count 2 2006.173.19:20:08.29#ibcon#about to read 5, iclass 23, count 2 2006.173.19:20:08.29#ibcon#read 5, iclass 23, count 2 2006.173.19:20:08.29#ibcon#about to read 6, iclass 23, count 2 2006.173.19:20:08.29#ibcon#read 6, iclass 23, count 2 2006.173.19:20:08.29#ibcon#end of sib2, iclass 23, count 2 2006.173.19:20:08.29#ibcon#*mode == 0, iclass 23, count 2 2006.173.19:20:08.29#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.19:20:08.29#ibcon#[27=AT05-04\r\n] 2006.173.19:20:08.29#ibcon#*before write, iclass 23, count 2 2006.173.19:20:08.29#ibcon#enter sib2, iclass 23, count 2 2006.173.19:20:08.29#ibcon#flushed, iclass 23, count 2 2006.173.19:20:08.29#ibcon#about to write, iclass 23, count 2 2006.173.19:20:08.29#ibcon#wrote, iclass 23, count 2 2006.173.19:20:08.29#ibcon#about to read 3, iclass 23, count 2 2006.173.19:20:08.32#ibcon#read 3, iclass 23, count 2 2006.173.19:20:08.32#ibcon#about to read 4, iclass 23, count 2 2006.173.19:20:08.32#ibcon#read 4, iclass 23, count 2 2006.173.19:20:08.32#ibcon#about to read 5, iclass 23, count 2 2006.173.19:20:08.32#ibcon#read 5, iclass 23, count 2 2006.173.19:20:08.32#ibcon#about to read 6, iclass 23, count 2 2006.173.19:20:08.32#ibcon#read 6, iclass 23, count 2 2006.173.19:20:08.32#ibcon#end of sib2, iclass 23, count 2 2006.173.19:20:08.32#ibcon#*after write, iclass 23, count 2 2006.173.19:20:08.32#ibcon#*before return 0, iclass 23, count 2 2006.173.19:20:08.32#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.19:20:08.32#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.19:20:08.32#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.19:20:08.32#ibcon#ireg 7 cls_cnt 0 2006.173.19:20:08.32#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.19:20:08.44#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.19:20:08.44#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.19:20:08.44#ibcon#enter wrdev, iclass 23, count 0 2006.173.19:20:08.44#ibcon#first serial, iclass 23, count 0 2006.173.19:20:08.44#ibcon#enter sib2, iclass 23, count 0 2006.173.19:20:08.44#ibcon#flushed, iclass 23, count 0 2006.173.19:20:08.44#ibcon#about to write, iclass 23, count 0 2006.173.19:20:08.44#ibcon#wrote, iclass 23, count 0 2006.173.19:20:08.44#ibcon#about to read 3, iclass 23, count 0 2006.173.19:20:08.46#ibcon#read 3, iclass 23, count 0 2006.173.19:20:08.46#ibcon#about to read 4, iclass 23, count 0 2006.173.19:20:08.46#ibcon#read 4, iclass 23, count 0 2006.173.19:20:08.46#ibcon#about to read 5, iclass 23, count 0 2006.173.19:20:08.46#ibcon#read 5, iclass 23, count 0 2006.173.19:20:08.46#ibcon#about to read 6, iclass 23, count 0 2006.173.19:20:08.46#ibcon#read 6, iclass 23, count 0 2006.173.19:20:08.46#ibcon#end of sib2, iclass 23, count 0 2006.173.19:20:08.46#ibcon#*mode == 0, iclass 23, count 0 2006.173.19:20:08.46#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.19:20:08.46#ibcon#[27=USB\r\n] 2006.173.19:20:08.46#ibcon#*before write, iclass 23, count 0 2006.173.19:20:08.46#ibcon#enter sib2, iclass 23, count 0 2006.173.19:20:08.46#ibcon#flushed, iclass 23, count 0 2006.173.19:20:08.46#ibcon#about to write, iclass 23, count 0 2006.173.19:20:08.46#ibcon#wrote, iclass 23, count 0 2006.173.19:20:08.46#ibcon#about to read 3, iclass 23, count 0 2006.173.19:20:08.49#ibcon#read 3, iclass 23, count 0 2006.173.19:20:08.49#ibcon#about to read 4, iclass 23, count 0 2006.173.19:20:08.49#ibcon#read 4, iclass 23, count 0 2006.173.19:20:08.49#ibcon#about to read 5, iclass 23, count 0 2006.173.19:20:08.49#ibcon#read 5, iclass 23, count 0 2006.173.19:20:08.49#ibcon#about to read 6, iclass 23, count 0 2006.173.19:20:08.49#ibcon#read 6, iclass 23, count 0 2006.173.19:20:08.49#ibcon#end of sib2, iclass 23, count 0 2006.173.19:20:08.49#ibcon#*after write, iclass 23, count 0 2006.173.19:20:08.49#ibcon#*before return 0, iclass 23, count 0 2006.173.19:20:08.49#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.19:20:08.49#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.19:20:08.49#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.19:20:08.49#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.19:20:08.49$vck44/vblo=6,719.99 2006.173.19:20:08.49#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.19:20:08.49#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.19:20:08.49#ibcon#ireg 17 cls_cnt 0 2006.173.19:20:08.49#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.19:20:08.49#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.19:20:08.49#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.19:20:08.49#ibcon#enter wrdev, iclass 25, count 0 2006.173.19:20:08.49#ibcon#first serial, iclass 25, count 0 2006.173.19:20:08.49#ibcon#enter sib2, iclass 25, count 0 2006.173.19:20:08.49#ibcon#flushed, iclass 25, count 0 2006.173.19:20:08.49#ibcon#about to write, iclass 25, count 0 2006.173.19:20:08.49#ibcon#wrote, iclass 25, count 0 2006.173.19:20:08.49#ibcon#about to read 3, iclass 25, count 0 2006.173.19:20:08.51#ibcon#read 3, iclass 25, count 0 2006.173.19:20:08.51#ibcon#about to read 4, iclass 25, count 0 2006.173.19:20:08.51#ibcon#read 4, iclass 25, count 0 2006.173.19:20:08.51#ibcon#about to read 5, iclass 25, count 0 2006.173.19:20:08.51#ibcon#read 5, iclass 25, count 0 2006.173.19:20:08.51#ibcon#about to read 6, iclass 25, count 0 2006.173.19:20:08.51#ibcon#read 6, iclass 25, count 0 2006.173.19:20:08.51#ibcon#end of sib2, iclass 25, count 0 2006.173.19:20:08.51#ibcon#*mode == 0, iclass 25, count 0 2006.173.19:20:08.51#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.19:20:08.51#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.19:20:08.51#ibcon#*before write, iclass 25, count 0 2006.173.19:20:08.51#ibcon#enter sib2, iclass 25, count 0 2006.173.19:20:08.51#ibcon#flushed, iclass 25, count 0 2006.173.19:20:08.51#ibcon#about to write, iclass 25, count 0 2006.173.19:20:08.51#ibcon#wrote, iclass 25, count 0 2006.173.19:20:08.51#ibcon#about to read 3, iclass 25, count 0 2006.173.19:20:08.55#ibcon#read 3, iclass 25, count 0 2006.173.19:20:08.55#ibcon#about to read 4, iclass 25, count 0 2006.173.19:20:08.55#ibcon#read 4, iclass 25, count 0 2006.173.19:20:08.55#ibcon#about to read 5, iclass 25, count 0 2006.173.19:20:08.55#ibcon#read 5, iclass 25, count 0 2006.173.19:20:08.55#ibcon#about to read 6, iclass 25, count 0 2006.173.19:20:08.55#ibcon#read 6, iclass 25, count 0 2006.173.19:20:08.55#ibcon#end of sib2, iclass 25, count 0 2006.173.19:20:08.55#ibcon#*after write, iclass 25, count 0 2006.173.19:20:08.55#ibcon#*before return 0, iclass 25, count 0 2006.173.19:20:08.55#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.19:20:08.55#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.19:20:08.55#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.19:20:08.55#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.19:20:08.55$vck44/vb=6,4 2006.173.19:20:08.55#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.19:20:08.55#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.19:20:08.55#ibcon#ireg 11 cls_cnt 2 2006.173.19:20:08.55#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.19:20:08.61#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.19:20:08.61#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.19:20:08.61#ibcon#enter wrdev, iclass 27, count 2 2006.173.19:20:08.61#ibcon#first serial, iclass 27, count 2 2006.173.19:20:08.61#ibcon#enter sib2, iclass 27, count 2 2006.173.19:20:08.61#ibcon#flushed, iclass 27, count 2 2006.173.19:20:08.61#ibcon#about to write, iclass 27, count 2 2006.173.19:20:08.61#ibcon#wrote, iclass 27, count 2 2006.173.19:20:08.61#ibcon#about to read 3, iclass 27, count 2 2006.173.19:20:08.63#ibcon#read 3, iclass 27, count 2 2006.173.19:20:08.63#ibcon#about to read 4, iclass 27, count 2 2006.173.19:20:08.63#ibcon#read 4, iclass 27, count 2 2006.173.19:20:08.63#ibcon#about to read 5, iclass 27, count 2 2006.173.19:20:08.63#ibcon#read 5, iclass 27, count 2 2006.173.19:20:08.63#ibcon#about to read 6, iclass 27, count 2 2006.173.19:20:08.63#ibcon#read 6, iclass 27, count 2 2006.173.19:20:08.63#ibcon#end of sib2, iclass 27, count 2 2006.173.19:20:08.63#ibcon#*mode == 0, iclass 27, count 2 2006.173.19:20:08.63#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.19:20:08.63#ibcon#[27=AT06-04\r\n] 2006.173.19:20:08.63#ibcon#*before write, iclass 27, count 2 2006.173.19:20:08.63#ibcon#enter sib2, iclass 27, count 2 2006.173.19:20:08.63#ibcon#flushed, iclass 27, count 2 2006.173.19:20:08.63#ibcon#about to write, iclass 27, count 2 2006.173.19:20:08.63#ibcon#wrote, iclass 27, count 2 2006.173.19:20:08.63#ibcon#about to read 3, iclass 27, count 2 2006.173.19:20:08.66#ibcon#read 3, iclass 27, count 2 2006.173.19:20:08.66#ibcon#about to read 4, iclass 27, count 2 2006.173.19:20:08.66#ibcon#read 4, iclass 27, count 2 2006.173.19:20:08.66#ibcon#about to read 5, iclass 27, count 2 2006.173.19:20:08.66#ibcon#read 5, iclass 27, count 2 2006.173.19:20:08.66#ibcon#about to read 6, iclass 27, count 2 2006.173.19:20:08.66#ibcon#read 6, iclass 27, count 2 2006.173.19:20:08.66#ibcon#end of sib2, iclass 27, count 2 2006.173.19:20:08.66#ibcon#*after write, iclass 27, count 2 2006.173.19:20:08.66#ibcon#*before return 0, iclass 27, count 2 2006.173.19:20:08.66#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.19:20:08.66#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.19:20:08.66#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.19:20:08.66#ibcon#ireg 7 cls_cnt 0 2006.173.19:20:08.66#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.19:20:08.78#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.19:20:08.78#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.19:20:08.78#ibcon#enter wrdev, iclass 27, count 0 2006.173.19:20:08.78#ibcon#first serial, iclass 27, count 0 2006.173.19:20:08.78#ibcon#enter sib2, iclass 27, count 0 2006.173.19:20:08.78#ibcon#flushed, iclass 27, count 0 2006.173.19:20:08.78#ibcon#about to write, iclass 27, count 0 2006.173.19:20:08.78#ibcon#wrote, iclass 27, count 0 2006.173.19:20:08.78#ibcon#about to read 3, iclass 27, count 0 2006.173.19:20:08.80#ibcon#read 3, iclass 27, count 0 2006.173.19:20:08.80#ibcon#about to read 4, iclass 27, count 0 2006.173.19:20:08.80#ibcon#read 4, iclass 27, count 0 2006.173.19:20:08.80#ibcon#about to read 5, iclass 27, count 0 2006.173.19:20:08.80#ibcon#read 5, iclass 27, count 0 2006.173.19:20:08.80#ibcon#about to read 6, iclass 27, count 0 2006.173.19:20:08.80#ibcon#read 6, iclass 27, count 0 2006.173.19:20:08.80#ibcon#end of sib2, iclass 27, count 0 2006.173.19:20:08.80#ibcon#*mode == 0, iclass 27, count 0 2006.173.19:20:08.80#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.19:20:08.80#ibcon#[27=USB\r\n] 2006.173.19:20:08.80#ibcon#*before write, iclass 27, count 0 2006.173.19:20:08.80#ibcon#enter sib2, iclass 27, count 0 2006.173.19:20:08.80#ibcon#flushed, iclass 27, count 0 2006.173.19:20:08.80#ibcon#about to write, iclass 27, count 0 2006.173.19:20:08.80#ibcon#wrote, iclass 27, count 0 2006.173.19:20:08.80#ibcon#about to read 3, iclass 27, count 0 2006.173.19:20:08.83#ibcon#read 3, iclass 27, count 0 2006.173.19:20:08.83#ibcon#about to read 4, iclass 27, count 0 2006.173.19:20:08.83#ibcon#read 4, iclass 27, count 0 2006.173.19:20:08.83#ibcon#about to read 5, iclass 27, count 0 2006.173.19:20:08.83#ibcon#read 5, iclass 27, count 0 2006.173.19:20:08.83#ibcon#about to read 6, iclass 27, count 0 2006.173.19:20:08.83#ibcon#read 6, iclass 27, count 0 2006.173.19:20:08.83#ibcon#end of sib2, iclass 27, count 0 2006.173.19:20:08.83#ibcon#*after write, iclass 27, count 0 2006.173.19:20:08.83#ibcon#*before return 0, iclass 27, count 0 2006.173.19:20:08.83#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.19:20:08.83#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.19:20:08.83#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.19:20:08.83#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.19:20:08.83$vck44/vblo=7,734.99 2006.173.19:20:08.83#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.19:20:08.83#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.19:20:08.83#ibcon#ireg 17 cls_cnt 0 2006.173.19:20:08.83#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.19:20:08.83#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.19:20:08.83#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.19:20:08.83#ibcon#enter wrdev, iclass 29, count 0 2006.173.19:20:08.83#ibcon#first serial, iclass 29, count 0 2006.173.19:20:08.83#ibcon#enter sib2, iclass 29, count 0 2006.173.19:20:08.83#ibcon#flushed, iclass 29, count 0 2006.173.19:20:08.83#ibcon#about to write, iclass 29, count 0 2006.173.19:20:08.83#ibcon#wrote, iclass 29, count 0 2006.173.19:20:08.83#ibcon#about to read 3, iclass 29, count 0 2006.173.19:20:08.85#ibcon#read 3, iclass 29, count 0 2006.173.19:20:08.85#ibcon#about to read 4, iclass 29, count 0 2006.173.19:20:08.85#ibcon#read 4, iclass 29, count 0 2006.173.19:20:08.85#ibcon#about to read 5, iclass 29, count 0 2006.173.19:20:08.85#ibcon#read 5, iclass 29, count 0 2006.173.19:20:08.85#ibcon#about to read 6, iclass 29, count 0 2006.173.19:20:08.85#ibcon#read 6, iclass 29, count 0 2006.173.19:20:08.85#ibcon#end of sib2, iclass 29, count 0 2006.173.19:20:08.85#ibcon#*mode == 0, iclass 29, count 0 2006.173.19:20:08.85#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.19:20:08.85#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.19:20:08.85#ibcon#*before write, iclass 29, count 0 2006.173.19:20:08.85#ibcon#enter sib2, iclass 29, count 0 2006.173.19:20:08.85#ibcon#flushed, iclass 29, count 0 2006.173.19:20:08.85#ibcon#about to write, iclass 29, count 0 2006.173.19:20:08.85#ibcon#wrote, iclass 29, count 0 2006.173.19:20:08.85#ibcon#about to read 3, iclass 29, count 0 2006.173.19:20:08.89#ibcon#read 3, iclass 29, count 0 2006.173.19:20:08.89#ibcon#about to read 4, iclass 29, count 0 2006.173.19:20:08.89#ibcon#read 4, iclass 29, count 0 2006.173.19:20:08.89#ibcon#about to read 5, iclass 29, count 0 2006.173.19:20:08.89#ibcon#read 5, iclass 29, count 0 2006.173.19:20:08.89#ibcon#about to read 6, iclass 29, count 0 2006.173.19:20:08.89#ibcon#read 6, iclass 29, count 0 2006.173.19:20:08.89#ibcon#end of sib2, iclass 29, count 0 2006.173.19:20:08.89#ibcon#*after write, iclass 29, count 0 2006.173.19:20:08.89#ibcon#*before return 0, iclass 29, count 0 2006.173.19:20:08.89#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.19:20:08.89#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.19:20:08.89#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.19:20:08.89#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.19:20:08.89$vck44/vb=7,4 2006.173.19:20:08.89#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.19:20:08.89#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.19:20:08.89#ibcon#ireg 11 cls_cnt 2 2006.173.19:20:08.89#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.19:20:08.95#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.19:20:08.95#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.19:20:08.95#ibcon#enter wrdev, iclass 31, count 2 2006.173.19:20:08.95#ibcon#first serial, iclass 31, count 2 2006.173.19:20:08.95#ibcon#enter sib2, iclass 31, count 2 2006.173.19:20:08.95#ibcon#flushed, iclass 31, count 2 2006.173.19:20:08.95#ibcon#about to write, iclass 31, count 2 2006.173.19:20:08.95#ibcon#wrote, iclass 31, count 2 2006.173.19:20:08.95#ibcon#about to read 3, iclass 31, count 2 2006.173.19:20:08.97#ibcon#read 3, iclass 31, count 2 2006.173.19:20:08.97#ibcon#about to read 4, iclass 31, count 2 2006.173.19:20:08.97#ibcon#read 4, iclass 31, count 2 2006.173.19:20:08.97#ibcon#about to read 5, iclass 31, count 2 2006.173.19:20:08.97#ibcon#read 5, iclass 31, count 2 2006.173.19:20:08.97#ibcon#about to read 6, iclass 31, count 2 2006.173.19:20:08.97#ibcon#read 6, iclass 31, count 2 2006.173.19:20:08.97#ibcon#end of sib2, iclass 31, count 2 2006.173.19:20:08.97#ibcon#*mode == 0, iclass 31, count 2 2006.173.19:20:08.97#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.19:20:08.97#ibcon#[27=AT07-04\r\n] 2006.173.19:20:08.97#ibcon#*before write, iclass 31, count 2 2006.173.19:20:08.97#ibcon#enter sib2, iclass 31, count 2 2006.173.19:20:08.97#ibcon#flushed, iclass 31, count 2 2006.173.19:20:08.97#ibcon#about to write, iclass 31, count 2 2006.173.19:20:08.97#ibcon#wrote, iclass 31, count 2 2006.173.19:20:08.97#ibcon#about to read 3, iclass 31, count 2 2006.173.19:20:09.00#ibcon#read 3, iclass 31, count 2 2006.173.19:20:09.00#ibcon#about to read 4, iclass 31, count 2 2006.173.19:20:09.00#ibcon#read 4, iclass 31, count 2 2006.173.19:20:09.00#ibcon#about to read 5, iclass 31, count 2 2006.173.19:20:09.00#ibcon#read 5, iclass 31, count 2 2006.173.19:20:09.00#ibcon#about to read 6, iclass 31, count 2 2006.173.19:20:09.00#ibcon#read 6, iclass 31, count 2 2006.173.19:20:09.00#ibcon#end of sib2, iclass 31, count 2 2006.173.19:20:09.00#ibcon#*after write, iclass 31, count 2 2006.173.19:20:09.00#ibcon#*before return 0, iclass 31, count 2 2006.173.19:20:09.00#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.19:20:09.00#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.19:20:09.00#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.19:20:09.00#ibcon#ireg 7 cls_cnt 0 2006.173.19:20:09.00#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.19:20:09.12#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.19:20:09.12#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.19:20:09.12#ibcon#enter wrdev, iclass 31, count 0 2006.173.19:20:09.12#ibcon#first serial, iclass 31, count 0 2006.173.19:20:09.12#ibcon#enter sib2, iclass 31, count 0 2006.173.19:20:09.12#ibcon#flushed, iclass 31, count 0 2006.173.19:20:09.12#ibcon#about to write, iclass 31, count 0 2006.173.19:20:09.12#ibcon#wrote, iclass 31, count 0 2006.173.19:20:09.12#ibcon#about to read 3, iclass 31, count 0 2006.173.19:20:09.14#ibcon#read 3, iclass 31, count 0 2006.173.19:20:09.14#ibcon#about to read 4, iclass 31, count 0 2006.173.19:20:09.14#ibcon#read 4, iclass 31, count 0 2006.173.19:20:09.14#ibcon#about to read 5, iclass 31, count 0 2006.173.19:20:09.14#ibcon#read 5, iclass 31, count 0 2006.173.19:20:09.14#ibcon#about to read 6, iclass 31, count 0 2006.173.19:20:09.14#ibcon#read 6, iclass 31, count 0 2006.173.19:20:09.14#ibcon#end of sib2, iclass 31, count 0 2006.173.19:20:09.14#ibcon#*mode == 0, iclass 31, count 0 2006.173.19:20:09.14#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.19:20:09.14#ibcon#[27=USB\r\n] 2006.173.19:20:09.14#ibcon#*before write, iclass 31, count 0 2006.173.19:20:09.14#ibcon#enter sib2, iclass 31, count 0 2006.173.19:20:09.14#ibcon#flushed, iclass 31, count 0 2006.173.19:20:09.14#ibcon#about to write, iclass 31, count 0 2006.173.19:20:09.14#ibcon#wrote, iclass 31, count 0 2006.173.19:20:09.14#ibcon#about to read 3, iclass 31, count 0 2006.173.19:20:09.17#ibcon#read 3, iclass 31, count 0 2006.173.19:20:09.17#ibcon#about to read 4, iclass 31, count 0 2006.173.19:20:09.17#ibcon#read 4, iclass 31, count 0 2006.173.19:20:09.17#ibcon#about to read 5, iclass 31, count 0 2006.173.19:20:09.17#ibcon#read 5, iclass 31, count 0 2006.173.19:20:09.17#ibcon#about to read 6, iclass 31, count 0 2006.173.19:20:09.17#ibcon#read 6, iclass 31, count 0 2006.173.19:20:09.17#ibcon#end of sib2, iclass 31, count 0 2006.173.19:20:09.17#ibcon#*after write, iclass 31, count 0 2006.173.19:20:09.17#ibcon#*before return 0, iclass 31, count 0 2006.173.19:20:09.17#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.19:20:09.17#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.19:20:09.17#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.19:20:09.17#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.19:20:09.17$vck44/vblo=8,744.99 2006.173.19:20:09.17#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.19:20:09.17#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.19:20:09.17#ibcon#ireg 17 cls_cnt 0 2006.173.19:20:09.17#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.19:20:09.17#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.19:20:09.17#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.19:20:09.17#ibcon#enter wrdev, iclass 33, count 0 2006.173.19:20:09.17#ibcon#first serial, iclass 33, count 0 2006.173.19:20:09.17#ibcon#enter sib2, iclass 33, count 0 2006.173.19:20:09.17#ibcon#flushed, iclass 33, count 0 2006.173.19:20:09.17#ibcon#about to write, iclass 33, count 0 2006.173.19:20:09.17#ibcon#wrote, iclass 33, count 0 2006.173.19:20:09.17#ibcon#about to read 3, iclass 33, count 0 2006.173.19:20:09.19#ibcon#read 3, iclass 33, count 0 2006.173.19:20:09.19#ibcon#about to read 4, iclass 33, count 0 2006.173.19:20:09.19#ibcon#read 4, iclass 33, count 0 2006.173.19:20:09.19#ibcon#about to read 5, iclass 33, count 0 2006.173.19:20:09.19#ibcon#read 5, iclass 33, count 0 2006.173.19:20:09.19#ibcon#about to read 6, iclass 33, count 0 2006.173.19:20:09.19#ibcon#read 6, iclass 33, count 0 2006.173.19:20:09.19#ibcon#end of sib2, iclass 33, count 0 2006.173.19:20:09.19#ibcon#*mode == 0, iclass 33, count 0 2006.173.19:20:09.19#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.19:20:09.19#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.19:20:09.19#ibcon#*before write, iclass 33, count 0 2006.173.19:20:09.19#ibcon#enter sib2, iclass 33, count 0 2006.173.19:20:09.19#ibcon#flushed, iclass 33, count 0 2006.173.19:20:09.19#ibcon#about to write, iclass 33, count 0 2006.173.19:20:09.19#ibcon#wrote, iclass 33, count 0 2006.173.19:20:09.19#ibcon#about to read 3, iclass 33, count 0 2006.173.19:20:09.23#ibcon#read 3, iclass 33, count 0 2006.173.19:20:09.23#ibcon#about to read 4, iclass 33, count 0 2006.173.19:20:09.23#ibcon#read 4, iclass 33, count 0 2006.173.19:20:09.23#ibcon#about to read 5, iclass 33, count 0 2006.173.19:20:09.23#ibcon#read 5, iclass 33, count 0 2006.173.19:20:09.23#ibcon#about to read 6, iclass 33, count 0 2006.173.19:20:09.23#ibcon#read 6, iclass 33, count 0 2006.173.19:20:09.23#ibcon#end of sib2, iclass 33, count 0 2006.173.19:20:09.23#ibcon#*after write, iclass 33, count 0 2006.173.19:20:09.23#ibcon#*before return 0, iclass 33, count 0 2006.173.19:20:09.23#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.19:20:09.23#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.19:20:09.23#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.19:20:09.23#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.19:20:09.23$vck44/vb=8,4 2006.173.19:20:09.23#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.19:20:09.23#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.19:20:09.23#ibcon#ireg 11 cls_cnt 2 2006.173.19:20:09.23#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.19:20:09.29#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.19:20:09.29#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.19:20:09.29#ibcon#enter wrdev, iclass 35, count 2 2006.173.19:20:09.29#ibcon#first serial, iclass 35, count 2 2006.173.19:20:09.29#ibcon#enter sib2, iclass 35, count 2 2006.173.19:20:09.29#ibcon#flushed, iclass 35, count 2 2006.173.19:20:09.29#ibcon#about to write, iclass 35, count 2 2006.173.19:20:09.29#ibcon#wrote, iclass 35, count 2 2006.173.19:20:09.29#ibcon#about to read 3, iclass 35, count 2 2006.173.19:20:09.31#ibcon#read 3, iclass 35, count 2 2006.173.19:20:09.31#ibcon#about to read 4, iclass 35, count 2 2006.173.19:20:09.31#ibcon#read 4, iclass 35, count 2 2006.173.19:20:09.31#ibcon#about to read 5, iclass 35, count 2 2006.173.19:20:09.31#ibcon#read 5, iclass 35, count 2 2006.173.19:20:09.31#ibcon#about to read 6, iclass 35, count 2 2006.173.19:20:09.31#ibcon#read 6, iclass 35, count 2 2006.173.19:20:09.31#ibcon#end of sib2, iclass 35, count 2 2006.173.19:20:09.31#ibcon#*mode == 0, iclass 35, count 2 2006.173.19:20:09.31#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.19:20:09.31#ibcon#[27=AT08-04\r\n] 2006.173.19:20:09.31#ibcon#*before write, iclass 35, count 2 2006.173.19:20:09.31#ibcon#enter sib2, iclass 35, count 2 2006.173.19:20:09.31#ibcon#flushed, iclass 35, count 2 2006.173.19:20:09.31#ibcon#about to write, iclass 35, count 2 2006.173.19:20:09.31#ibcon#wrote, iclass 35, count 2 2006.173.19:20:09.31#ibcon#about to read 3, iclass 35, count 2 2006.173.19:20:09.34#ibcon#read 3, iclass 35, count 2 2006.173.19:20:09.34#ibcon#about to read 4, iclass 35, count 2 2006.173.19:20:09.34#ibcon#read 4, iclass 35, count 2 2006.173.19:20:09.34#ibcon#about to read 5, iclass 35, count 2 2006.173.19:20:09.34#ibcon#read 5, iclass 35, count 2 2006.173.19:20:09.34#ibcon#about to read 6, iclass 35, count 2 2006.173.19:20:09.34#ibcon#read 6, iclass 35, count 2 2006.173.19:20:09.34#ibcon#end of sib2, iclass 35, count 2 2006.173.19:20:09.34#ibcon#*after write, iclass 35, count 2 2006.173.19:20:09.34#ibcon#*before return 0, iclass 35, count 2 2006.173.19:20:09.34#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.19:20:09.34#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.19:20:09.34#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.19:20:09.34#ibcon#ireg 7 cls_cnt 0 2006.173.19:20:09.34#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.19:20:09.46#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.19:20:09.46#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.19:20:09.46#ibcon#enter wrdev, iclass 35, count 0 2006.173.19:20:09.46#ibcon#first serial, iclass 35, count 0 2006.173.19:20:09.46#ibcon#enter sib2, iclass 35, count 0 2006.173.19:20:09.46#ibcon#flushed, iclass 35, count 0 2006.173.19:20:09.46#ibcon#about to write, iclass 35, count 0 2006.173.19:20:09.46#ibcon#wrote, iclass 35, count 0 2006.173.19:20:09.46#ibcon#about to read 3, iclass 35, count 0 2006.173.19:20:09.48#ibcon#read 3, iclass 35, count 0 2006.173.19:20:09.48#ibcon#about to read 4, iclass 35, count 0 2006.173.19:20:09.48#ibcon#read 4, iclass 35, count 0 2006.173.19:20:09.48#ibcon#about to read 5, iclass 35, count 0 2006.173.19:20:09.48#ibcon#read 5, iclass 35, count 0 2006.173.19:20:09.48#ibcon#about to read 6, iclass 35, count 0 2006.173.19:20:09.48#ibcon#read 6, iclass 35, count 0 2006.173.19:20:09.48#ibcon#end of sib2, iclass 35, count 0 2006.173.19:20:09.48#ibcon#*mode == 0, iclass 35, count 0 2006.173.19:20:09.48#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.19:20:09.48#ibcon#[27=USB\r\n] 2006.173.19:20:09.48#ibcon#*before write, iclass 35, count 0 2006.173.19:20:09.48#ibcon#enter sib2, iclass 35, count 0 2006.173.19:20:09.48#ibcon#flushed, iclass 35, count 0 2006.173.19:20:09.48#ibcon#about to write, iclass 35, count 0 2006.173.19:20:09.48#ibcon#wrote, iclass 35, count 0 2006.173.19:20:09.48#ibcon#about to read 3, iclass 35, count 0 2006.173.19:20:09.51#ibcon#read 3, iclass 35, count 0 2006.173.19:20:09.51#ibcon#about to read 4, iclass 35, count 0 2006.173.19:20:09.51#ibcon#read 4, iclass 35, count 0 2006.173.19:20:09.51#ibcon#about to read 5, iclass 35, count 0 2006.173.19:20:09.51#ibcon#read 5, iclass 35, count 0 2006.173.19:20:09.51#ibcon#about to read 6, iclass 35, count 0 2006.173.19:20:09.51#ibcon#read 6, iclass 35, count 0 2006.173.19:20:09.51#ibcon#end of sib2, iclass 35, count 0 2006.173.19:20:09.51#ibcon#*after write, iclass 35, count 0 2006.173.19:20:09.51#ibcon#*before return 0, iclass 35, count 0 2006.173.19:20:09.51#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.19:20:09.51#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.19:20:09.51#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.19:20:09.51#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.19:20:09.51$vck44/vabw=wide 2006.173.19:20:09.51#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.19:20:09.51#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.19:20:09.51#ibcon#ireg 8 cls_cnt 0 2006.173.19:20:09.51#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.19:20:09.51#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.19:20:09.51#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.19:20:09.51#ibcon#enter wrdev, iclass 37, count 0 2006.173.19:20:09.51#ibcon#first serial, iclass 37, count 0 2006.173.19:20:09.51#ibcon#enter sib2, iclass 37, count 0 2006.173.19:20:09.51#ibcon#flushed, iclass 37, count 0 2006.173.19:20:09.51#ibcon#about to write, iclass 37, count 0 2006.173.19:20:09.51#ibcon#wrote, iclass 37, count 0 2006.173.19:20:09.51#ibcon#about to read 3, iclass 37, count 0 2006.173.19:20:09.53#ibcon#read 3, iclass 37, count 0 2006.173.19:20:09.53#ibcon#about to read 4, iclass 37, count 0 2006.173.19:20:09.53#ibcon#read 4, iclass 37, count 0 2006.173.19:20:09.53#ibcon#about to read 5, iclass 37, count 0 2006.173.19:20:09.53#ibcon#read 5, iclass 37, count 0 2006.173.19:20:09.53#ibcon#about to read 6, iclass 37, count 0 2006.173.19:20:09.53#ibcon#read 6, iclass 37, count 0 2006.173.19:20:09.53#ibcon#end of sib2, iclass 37, count 0 2006.173.19:20:09.53#ibcon#*mode == 0, iclass 37, count 0 2006.173.19:20:09.53#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.19:20:09.53#ibcon#[25=BW32\r\n] 2006.173.19:20:09.53#ibcon#*before write, iclass 37, count 0 2006.173.19:20:09.53#ibcon#enter sib2, iclass 37, count 0 2006.173.19:20:09.53#ibcon#flushed, iclass 37, count 0 2006.173.19:20:09.53#ibcon#about to write, iclass 37, count 0 2006.173.19:20:09.53#ibcon#wrote, iclass 37, count 0 2006.173.19:20:09.53#ibcon#about to read 3, iclass 37, count 0 2006.173.19:20:09.56#ibcon#read 3, iclass 37, count 0 2006.173.19:20:09.56#ibcon#about to read 4, iclass 37, count 0 2006.173.19:20:09.56#ibcon#read 4, iclass 37, count 0 2006.173.19:20:09.56#ibcon#about to read 5, iclass 37, count 0 2006.173.19:20:09.56#ibcon#read 5, iclass 37, count 0 2006.173.19:20:09.56#ibcon#about to read 6, iclass 37, count 0 2006.173.19:20:09.56#ibcon#read 6, iclass 37, count 0 2006.173.19:20:09.56#ibcon#end of sib2, iclass 37, count 0 2006.173.19:20:09.56#ibcon#*after write, iclass 37, count 0 2006.173.19:20:09.56#ibcon#*before return 0, iclass 37, count 0 2006.173.19:20:09.56#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.19:20:09.56#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.19:20:09.56#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.19:20:09.56#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.19:20:09.56$vck44/vbbw=wide 2006.173.19:20:09.56#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.19:20:09.56#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.19:20:09.56#ibcon#ireg 8 cls_cnt 0 2006.173.19:20:09.56#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.19:20:09.63#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.19:20:09.63#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.19:20:09.63#ibcon#enter wrdev, iclass 39, count 0 2006.173.19:20:09.63#ibcon#first serial, iclass 39, count 0 2006.173.19:20:09.63#ibcon#enter sib2, iclass 39, count 0 2006.173.19:20:09.63#ibcon#flushed, iclass 39, count 0 2006.173.19:20:09.63#ibcon#about to write, iclass 39, count 0 2006.173.19:20:09.63#ibcon#wrote, iclass 39, count 0 2006.173.19:20:09.63#ibcon#about to read 3, iclass 39, count 0 2006.173.19:20:09.65#ibcon#read 3, iclass 39, count 0 2006.173.19:20:09.65#ibcon#about to read 4, iclass 39, count 0 2006.173.19:20:09.65#ibcon#read 4, iclass 39, count 0 2006.173.19:20:09.65#ibcon#about to read 5, iclass 39, count 0 2006.173.19:20:09.65#ibcon#read 5, iclass 39, count 0 2006.173.19:20:09.65#ibcon#about to read 6, iclass 39, count 0 2006.173.19:20:09.65#ibcon#read 6, iclass 39, count 0 2006.173.19:20:09.65#ibcon#end of sib2, iclass 39, count 0 2006.173.19:20:09.65#ibcon#*mode == 0, iclass 39, count 0 2006.173.19:20:09.65#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.19:20:09.65#ibcon#[27=BW32\r\n] 2006.173.19:20:09.65#ibcon#*before write, iclass 39, count 0 2006.173.19:20:09.65#ibcon#enter sib2, iclass 39, count 0 2006.173.19:20:09.65#ibcon#flushed, iclass 39, count 0 2006.173.19:20:09.65#ibcon#about to write, iclass 39, count 0 2006.173.19:20:09.65#ibcon#wrote, iclass 39, count 0 2006.173.19:20:09.65#ibcon#about to read 3, iclass 39, count 0 2006.173.19:20:09.68#ibcon#read 3, iclass 39, count 0 2006.173.19:20:09.68#ibcon#about to read 4, iclass 39, count 0 2006.173.19:20:09.68#ibcon#read 4, iclass 39, count 0 2006.173.19:20:09.68#ibcon#about to read 5, iclass 39, count 0 2006.173.19:20:09.68#ibcon#read 5, iclass 39, count 0 2006.173.19:20:09.68#ibcon#about to read 6, iclass 39, count 0 2006.173.19:20:09.68#ibcon#read 6, iclass 39, count 0 2006.173.19:20:09.68#ibcon#end of sib2, iclass 39, count 0 2006.173.19:20:09.68#ibcon#*after write, iclass 39, count 0 2006.173.19:20:09.68#ibcon#*before return 0, iclass 39, count 0 2006.173.19:20:09.68#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.19:20:09.68#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.19:20:09.68#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.19:20:09.68#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.19:20:09.68$setupk4/ifdk4 2006.173.19:20:09.68$ifdk4/lo= 2006.173.19:20:09.68$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.19:20:09.68$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.19:20:09.68$ifdk4/patch= 2006.173.19:20:09.68$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.19:20:09.68$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.19:20:09.68$setupk4/!*+20s 2006.173.19:20:10.95#abcon#<5=/06 0.5 1.3 19.511001002.4\r\n> 2006.173.19:20:10.97#abcon#{5=INTERFACE CLEAR} 2006.173.19:20:11.03#abcon#[5=S1D000X0/0*\r\n] 2006.173.19:20:21.12#abcon#<5=/06 0.5 1.3 19.511001002.4\r\n> 2006.173.19:20:21.14#abcon#{5=INTERFACE CLEAR} 2006.173.19:20:21.20#abcon#[5=S1D000X0/0*\r\n] 2006.173.19:20:23.14#trakl#Source acquired 2006.173.19:20:24.14#flagr#flagr/antenna,acquired 2006.173.19:20:24.20$setupk4/"tpicd 2006.173.19:20:24.20$setupk4/echo=off 2006.173.19:20:24.20$setupk4/xlog=off 2006.173.19:20:24.20:!2006.173.19:22:10 2006.173.19:22:10.00:preob 2006.173.19:22:10.13/onsource/TRACKING 2006.173.19:22:10.13:!2006.173.19:22:20 2006.173.19:22:20.00:"tape 2006.173.19:22:20.00:"st=record 2006.173.19:22:20.00:data_valid=on 2006.173.19:22:20.00:midob 2006.173.19:22:21.13/onsource/TRACKING 2006.173.19:22:21.13/wx/19.49,1002.4,100 2006.173.19:22:21.32/cable/+6.5163E-03 2006.173.19:22:22.41/va/01,07,usb,yes,43,46 2006.173.19:22:22.41/va/02,06,usb,yes,42,43 2006.173.19:22:22.41/va/03,05,usb,yes,54,56 2006.173.19:22:22.41/va/04,06,usb,yes,43,46 2006.173.19:22:22.41/va/05,04,usb,yes,34,35 2006.173.19:22:22.41/va/06,03,usb,yes,48,47 2006.173.19:22:22.41/va/07,04,usb,yes,39,40 2006.173.19:22:22.41/va/08,04,usb,yes,33,40 2006.173.19:22:22.64/valo/01,524.99,yes,locked 2006.173.19:22:22.64/valo/02,534.99,yes,locked 2006.173.19:22:22.64/valo/03,564.99,yes,locked 2006.173.19:22:22.64/valo/04,624.99,yes,locked 2006.173.19:22:22.64/valo/05,734.99,yes,locked 2006.173.19:22:22.64/valo/06,814.99,yes,locked 2006.173.19:22:22.64/valo/07,864.99,yes,locked 2006.173.19:22:22.64/valo/08,884.99,yes,locked 2006.173.19:22:23.73/vb/01,04,usb,yes,33,30 2006.173.19:22:23.73/vb/02,04,usb,yes,35,35 2006.173.19:22:23.73/vb/03,04,usb,yes,32,35 2006.173.19:22:23.73/vb/04,04,usb,yes,37,35 2006.173.19:22:23.73/vb/05,04,usb,yes,29,31 2006.173.19:22:23.73/vb/06,04,usb,yes,33,29 2006.173.19:22:23.73/vb/07,04,usb,yes,33,33 2006.173.19:22:23.73/vb/08,04,usb,yes,31,34 2006.173.19:22:23.96/vblo/01,629.99,yes,locked 2006.173.19:22:23.96/vblo/02,634.99,yes,locked 2006.173.19:22:23.96/vblo/03,649.99,yes,locked 2006.173.19:22:23.96/vblo/04,679.99,yes,locked 2006.173.19:22:23.96/vblo/05,709.99,yes,locked 2006.173.19:22:23.96/vblo/06,719.99,yes,locked 2006.173.19:22:23.96/vblo/07,734.99,yes,locked 2006.173.19:22:23.96/vblo/08,744.99,yes,locked 2006.173.19:22:24.11/vabw/8 2006.173.19:22:24.26/vbbw/8 2006.173.19:22:24.35/xfe/off,on,15.5 2006.173.19:22:24.74/ifatt/23,28,28,28 2006.173.19:22:25.07/fmout-gps/S +3.87E-07 2006.173.19:22:25.11:!2006.173.19:23:00 2006.173.19:23:00.01:data_valid=off 2006.173.19:23:00.01:"et 2006.173.19:23:00.01:!+3s 2006.173.19:23:03.02:"tape 2006.173.19:23:03.02:postob 2006.173.19:23:03.12/cable/+6.5179E-03 2006.173.19:23:03.12/wx/19.48,1002.5,100 2006.173.19:23:03.18/fmout-gps/S +3.87E-07 2006.173.19:23:03.18:scan_name=173-1923,jd0606,40 2006.173.19:23:03.18:source=1741-038,174358.86,-035004.6,2000.0,ccw 2006.173.19:23:05.14#flagr#flagr/antenna,new-source 2006.173.19:23:05.14:checkk5 2006.173.19:23:05.55/chk_autoobs//k5ts1/ autoobs is running! 2006.173.19:23:05.95/chk_autoobs//k5ts2/ autoobs is running! 2006.173.19:23:06.36/chk_autoobs//k5ts3/ autoobs is running! 2006.173.19:23:06.75/chk_autoobs//k5ts4/ autoobs is running! 2006.173.19:23:07.14/chk_obsdata//k5ts1/T1731922??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.19:23:07.55/chk_obsdata//k5ts2/T1731922??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.19:23:07.97/chk_obsdata//k5ts3/T1731922??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.19:23:08.37/chk_obsdata//k5ts4/T1731922??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.19:23:09.09/k5log//k5ts1_log_newline 2006.173.19:23:09.80/k5log//k5ts2_log_newline 2006.173.19:23:10.51/k5log//k5ts3_log_newline 2006.173.19:23:11.21/k5log//k5ts4_log_newline 2006.173.19:23:11.24/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.19:23:11.24:setupk4=1 2006.173.19:23:11.24$setupk4/echo=on 2006.173.19:23:11.24$setupk4/pcalon 2006.173.19:23:11.24$pcalon/"no phase cal control is implemented here 2006.173.19:23:11.24$setupk4/"tpicd=stop 2006.173.19:23:11.24$setupk4/"rec=synch_on 2006.173.19:23:11.24$setupk4/"rec_mode=128 2006.173.19:23:11.24$setupk4/!* 2006.173.19:23:11.24$setupk4/recpk4 2006.173.19:23:11.24$recpk4/recpatch= 2006.173.19:23:11.24$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.19:23:11.24$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.19:23:11.24$setupk4/vck44 2006.173.19:23:11.24$vck44/valo=1,524.99 2006.173.19:23:11.24#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.19:23:11.24#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.19:23:11.24#ibcon#ireg 17 cls_cnt 0 2006.173.19:23:11.24#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.19:23:11.24#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.19:23:11.24#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.19:23:11.24#ibcon#enter wrdev, iclass 6, count 0 2006.173.19:23:11.24#ibcon#first serial, iclass 6, count 0 2006.173.19:23:11.24#ibcon#enter sib2, iclass 6, count 0 2006.173.19:23:11.24#ibcon#flushed, iclass 6, count 0 2006.173.19:23:11.24#ibcon#about to write, iclass 6, count 0 2006.173.19:23:11.24#ibcon#wrote, iclass 6, count 0 2006.173.19:23:11.24#ibcon#about to read 3, iclass 6, count 0 2006.173.19:23:11.26#ibcon#read 3, iclass 6, count 0 2006.173.19:23:11.26#ibcon#about to read 4, iclass 6, count 0 2006.173.19:23:11.26#ibcon#read 4, iclass 6, count 0 2006.173.19:23:11.26#ibcon#about to read 5, iclass 6, count 0 2006.173.19:23:11.26#ibcon#read 5, iclass 6, count 0 2006.173.19:23:11.26#ibcon#about to read 6, iclass 6, count 0 2006.173.19:23:11.26#ibcon#read 6, iclass 6, count 0 2006.173.19:23:11.26#ibcon#end of sib2, iclass 6, count 0 2006.173.19:23:11.26#ibcon#*mode == 0, iclass 6, count 0 2006.173.19:23:11.26#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.19:23:11.26#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.19:23:11.26#ibcon#*before write, iclass 6, count 0 2006.173.19:23:11.26#ibcon#enter sib2, iclass 6, count 0 2006.173.19:23:11.26#ibcon#flushed, iclass 6, count 0 2006.173.19:23:11.26#ibcon#about to write, iclass 6, count 0 2006.173.19:23:11.26#ibcon#wrote, iclass 6, count 0 2006.173.19:23:11.26#ibcon#about to read 3, iclass 6, count 0 2006.173.19:23:11.31#ibcon#read 3, iclass 6, count 0 2006.173.19:23:11.31#ibcon#about to read 4, iclass 6, count 0 2006.173.19:23:11.31#ibcon#read 4, iclass 6, count 0 2006.173.19:23:11.31#ibcon#about to read 5, iclass 6, count 0 2006.173.19:23:11.31#ibcon#read 5, iclass 6, count 0 2006.173.19:23:11.31#ibcon#about to read 6, iclass 6, count 0 2006.173.19:23:11.31#ibcon#read 6, iclass 6, count 0 2006.173.19:23:11.31#ibcon#end of sib2, iclass 6, count 0 2006.173.19:23:11.31#ibcon#*after write, iclass 6, count 0 2006.173.19:23:11.31#ibcon#*before return 0, iclass 6, count 0 2006.173.19:23:11.31#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.19:23:11.31#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.19:23:11.31#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.19:23:11.31#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.19:23:11.31$vck44/va=1,7 2006.173.19:23:11.31#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.19:23:11.31#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.19:23:11.31#ibcon#ireg 11 cls_cnt 2 2006.173.19:23:11.31#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.19:23:11.31#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.19:23:11.31#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.19:23:11.31#ibcon#enter wrdev, iclass 10, count 2 2006.173.19:23:11.31#ibcon#first serial, iclass 10, count 2 2006.173.19:23:11.31#ibcon#enter sib2, iclass 10, count 2 2006.173.19:23:11.31#ibcon#flushed, iclass 10, count 2 2006.173.19:23:11.31#ibcon#about to write, iclass 10, count 2 2006.173.19:23:11.31#ibcon#wrote, iclass 10, count 2 2006.173.19:23:11.31#ibcon#about to read 3, iclass 10, count 2 2006.173.19:23:11.33#ibcon#read 3, iclass 10, count 2 2006.173.19:23:11.33#ibcon#about to read 4, iclass 10, count 2 2006.173.19:23:11.33#ibcon#read 4, iclass 10, count 2 2006.173.19:23:11.33#ibcon#about to read 5, iclass 10, count 2 2006.173.19:23:11.33#ibcon#read 5, iclass 10, count 2 2006.173.19:23:11.33#ibcon#about to read 6, iclass 10, count 2 2006.173.19:23:11.33#ibcon#read 6, iclass 10, count 2 2006.173.19:23:11.33#ibcon#end of sib2, iclass 10, count 2 2006.173.19:23:11.33#ibcon#*mode == 0, iclass 10, count 2 2006.173.19:23:11.33#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.19:23:11.33#ibcon#[25=AT01-07\r\n] 2006.173.19:23:11.33#ibcon#*before write, iclass 10, count 2 2006.173.19:23:11.33#ibcon#enter sib2, iclass 10, count 2 2006.173.19:23:11.33#ibcon#flushed, iclass 10, count 2 2006.173.19:23:11.33#ibcon#about to write, iclass 10, count 2 2006.173.19:23:11.33#ibcon#wrote, iclass 10, count 2 2006.173.19:23:11.33#ibcon#about to read 3, iclass 10, count 2 2006.173.19:23:11.36#ibcon#read 3, iclass 10, count 2 2006.173.19:23:11.36#ibcon#about to read 4, iclass 10, count 2 2006.173.19:23:11.36#ibcon#read 4, iclass 10, count 2 2006.173.19:23:11.36#ibcon#about to read 5, iclass 10, count 2 2006.173.19:23:11.36#ibcon#read 5, iclass 10, count 2 2006.173.19:23:11.36#ibcon#about to read 6, iclass 10, count 2 2006.173.19:23:11.36#ibcon#read 6, iclass 10, count 2 2006.173.19:23:11.36#ibcon#end of sib2, iclass 10, count 2 2006.173.19:23:11.36#ibcon#*after write, iclass 10, count 2 2006.173.19:23:11.36#ibcon#*before return 0, iclass 10, count 2 2006.173.19:23:11.36#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.19:23:11.36#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.19:23:11.36#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.19:23:11.36#ibcon#ireg 7 cls_cnt 0 2006.173.19:23:11.36#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.19:23:11.48#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.19:23:11.48#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.19:23:11.48#ibcon#enter wrdev, iclass 10, count 0 2006.173.19:23:11.48#ibcon#first serial, iclass 10, count 0 2006.173.19:23:11.48#ibcon#enter sib2, iclass 10, count 0 2006.173.19:23:11.48#ibcon#flushed, iclass 10, count 0 2006.173.19:23:11.48#ibcon#about to write, iclass 10, count 0 2006.173.19:23:11.48#ibcon#wrote, iclass 10, count 0 2006.173.19:23:11.48#ibcon#about to read 3, iclass 10, count 0 2006.173.19:23:11.50#ibcon#read 3, iclass 10, count 0 2006.173.19:23:11.50#ibcon#about to read 4, iclass 10, count 0 2006.173.19:23:11.50#ibcon#read 4, iclass 10, count 0 2006.173.19:23:11.50#ibcon#about to read 5, iclass 10, count 0 2006.173.19:23:11.50#ibcon#read 5, iclass 10, count 0 2006.173.19:23:11.50#ibcon#about to read 6, iclass 10, count 0 2006.173.19:23:11.50#ibcon#read 6, iclass 10, count 0 2006.173.19:23:11.50#ibcon#end of sib2, iclass 10, count 0 2006.173.19:23:11.50#ibcon#*mode == 0, iclass 10, count 0 2006.173.19:23:11.50#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.19:23:11.50#ibcon#[25=USB\r\n] 2006.173.19:23:11.50#ibcon#*before write, iclass 10, count 0 2006.173.19:23:11.50#ibcon#enter sib2, iclass 10, count 0 2006.173.19:23:11.50#ibcon#flushed, iclass 10, count 0 2006.173.19:23:11.50#ibcon#about to write, iclass 10, count 0 2006.173.19:23:11.50#ibcon#wrote, iclass 10, count 0 2006.173.19:23:11.50#ibcon#about to read 3, iclass 10, count 0 2006.173.19:23:11.53#ibcon#read 3, iclass 10, count 0 2006.173.19:23:11.53#ibcon#about to read 4, iclass 10, count 0 2006.173.19:23:11.53#ibcon#read 4, iclass 10, count 0 2006.173.19:23:11.53#ibcon#about to read 5, iclass 10, count 0 2006.173.19:23:11.53#ibcon#read 5, iclass 10, count 0 2006.173.19:23:11.53#ibcon#about to read 6, iclass 10, count 0 2006.173.19:23:11.53#ibcon#read 6, iclass 10, count 0 2006.173.19:23:11.53#ibcon#end of sib2, iclass 10, count 0 2006.173.19:23:11.53#ibcon#*after write, iclass 10, count 0 2006.173.19:23:11.53#ibcon#*before return 0, iclass 10, count 0 2006.173.19:23:11.53#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.19:23:11.53#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.19:23:11.53#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.19:23:11.53#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.19:23:11.53$vck44/valo=2,534.99 2006.173.19:23:11.53#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.19:23:11.53#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.19:23:11.53#ibcon#ireg 17 cls_cnt 0 2006.173.19:23:11.53#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.19:23:11.53#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.19:23:11.53#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.19:23:11.53#ibcon#enter wrdev, iclass 12, count 0 2006.173.19:23:11.53#ibcon#first serial, iclass 12, count 0 2006.173.19:23:11.53#ibcon#enter sib2, iclass 12, count 0 2006.173.19:23:11.53#ibcon#flushed, iclass 12, count 0 2006.173.19:23:11.53#ibcon#about to write, iclass 12, count 0 2006.173.19:23:11.53#ibcon#wrote, iclass 12, count 0 2006.173.19:23:11.53#ibcon#about to read 3, iclass 12, count 0 2006.173.19:23:11.55#ibcon#read 3, iclass 12, count 0 2006.173.19:23:11.55#ibcon#about to read 4, iclass 12, count 0 2006.173.19:23:11.55#ibcon#read 4, iclass 12, count 0 2006.173.19:23:11.55#ibcon#about to read 5, iclass 12, count 0 2006.173.19:23:11.55#ibcon#read 5, iclass 12, count 0 2006.173.19:23:11.55#ibcon#about to read 6, iclass 12, count 0 2006.173.19:23:11.55#ibcon#read 6, iclass 12, count 0 2006.173.19:23:11.55#ibcon#end of sib2, iclass 12, count 0 2006.173.19:23:11.55#ibcon#*mode == 0, iclass 12, count 0 2006.173.19:23:11.55#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.19:23:11.55#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.19:23:11.55#ibcon#*before write, iclass 12, count 0 2006.173.19:23:11.55#ibcon#enter sib2, iclass 12, count 0 2006.173.19:23:11.55#ibcon#flushed, iclass 12, count 0 2006.173.19:23:11.55#ibcon#about to write, iclass 12, count 0 2006.173.19:23:11.55#ibcon#wrote, iclass 12, count 0 2006.173.19:23:11.55#ibcon#about to read 3, iclass 12, count 0 2006.173.19:23:11.59#ibcon#read 3, iclass 12, count 0 2006.173.19:23:11.59#ibcon#about to read 4, iclass 12, count 0 2006.173.19:23:11.59#ibcon#read 4, iclass 12, count 0 2006.173.19:23:11.59#ibcon#about to read 5, iclass 12, count 0 2006.173.19:23:11.59#ibcon#read 5, iclass 12, count 0 2006.173.19:23:11.59#ibcon#about to read 6, iclass 12, count 0 2006.173.19:23:11.59#ibcon#read 6, iclass 12, count 0 2006.173.19:23:11.59#ibcon#end of sib2, iclass 12, count 0 2006.173.19:23:11.59#ibcon#*after write, iclass 12, count 0 2006.173.19:23:11.59#ibcon#*before return 0, iclass 12, count 0 2006.173.19:23:11.59#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.19:23:11.59#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.19:23:11.59#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.19:23:11.59#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.19:23:11.59$vck44/va=2,6 2006.173.19:23:11.59#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.19:23:11.59#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.19:23:11.59#ibcon#ireg 11 cls_cnt 2 2006.173.19:23:11.59#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.19:23:11.65#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.19:23:11.65#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.19:23:11.65#ibcon#enter wrdev, iclass 14, count 2 2006.173.19:23:11.65#ibcon#first serial, iclass 14, count 2 2006.173.19:23:11.65#ibcon#enter sib2, iclass 14, count 2 2006.173.19:23:11.65#ibcon#flushed, iclass 14, count 2 2006.173.19:23:11.65#ibcon#about to write, iclass 14, count 2 2006.173.19:23:11.65#ibcon#wrote, iclass 14, count 2 2006.173.19:23:11.65#ibcon#about to read 3, iclass 14, count 2 2006.173.19:23:11.67#ibcon#read 3, iclass 14, count 2 2006.173.19:23:11.67#ibcon#about to read 4, iclass 14, count 2 2006.173.19:23:11.67#ibcon#read 4, iclass 14, count 2 2006.173.19:23:11.67#ibcon#about to read 5, iclass 14, count 2 2006.173.19:23:11.67#ibcon#read 5, iclass 14, count 2 2006.173.19:23:11.67#ibcon#about to read 6, iclass 14, count 2 2006.173.19:23:11.67#ibcon#read 6, iclass 14, count 2 2006.173.19:23:11.67#ibcon#end of sib2, iclass 14, count 2 2006.173.19:23:11.67#ibcon#*mode == 0, iclass 14, count 2 2006.173.19:23:11.67#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.19:23:11.67#ibcon#[25=AT02-06\r\n] 2006.173.19:23:11.67#ibcon#*before write, iclass 14, count 2 2006.173.19:23:11.67#ibcon#enter sib2, iclass 14, count 2 2006.173.19:23:11.67#ibcon#flushed, iclass 14, count 2 2006.173.19:23:11.67#ibcon#about to write, iclass 14, count 2 2006.173.19:23:11.67#ibcon#wrote, iclass 14, count 2 2006.173.19:23:11.67#ibcon#about to read 3, iclass 14, count 2 2006.173.19:23:11.70#ibcon#read 3, iclass 14, count 2 2006.173.19:23:11.70#ibcon#about to read 4, iclass 14, count 2 2006.173.19:23:11.70#ibcon#read 4, iclass 14, count 2 2006.173.19:23:11.70#ibcon#about to read 5, iclass 14, count 2 2006.173.19:23:11.70#ibcon#read 5, iclass 14, count 2 2006.173.19:23:11.70#ibcon#about to read 6, iclass 14, count 2 2006.173.19:23:11.70#ibcon#read 6, iclass 14, count 2 2006.173.19:23:11.70#ibcon#end of sib2, iclass 14, count 2 2006.173.19:23:11.70#ibcon#*after write, iclass 14, count 2 2006.173.19:23:11.70#ibcon#*before return 0, iclass 14, count 2 2006.173.19:23:11.70#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.19:23:11.70#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.19:23:11.70#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.19:23:11.70#ibcon#ireg 7 cls_cnt 0 2006.173.19:23:11.70#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.19:23:11.82#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.19:23:11.82#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.19:23:11.82#ibcon#enter wrdev, iclass 14, count 0 2006.173.19:23:11.82#ibcon#first serial, iclass 14, count 0 2006.173.19:23:11.82#ibcon#enter sib2, iclass 14, count 0 2006.173.19:23:11.82#ibcon#flushed, iclass 14, count 0 2006.173.19:23:11.82#ibcon#about to write, iclass 14, count 0 2006.173.19:23:11.82#ibcon#wrote, iclass 14, count 0 2006.173.19:23:11.82#ibcon#about to read 3, iclass 14, count 0 2006.173.19:23:11.84#ibcon#read 3, iclass 14, count 0 2006.173.19:23:11.84#ibcon#about to read 4, iclass 14, count 0 2006.173.19:23:11.84#ibcon#read 4, iclass 14, count 0 2006.173.19:23:11.84#ibcon#about to read 5, iclass 14, count 0 2006.173.19:23:11.84#ibcon#read 5, iclass 14, count 0 2006.173.19:23:11.84#ibcon#about to read 6, iclass 14, count 0 2006.173.19:23:11.84#ibcon#read 6, iclass 14, count 0 2006.173.19:23:11.84#ibcon#end of sib2, iclass 14, count 0 2006.173.19:23:11.84#ibcon#*mode == 0, iclass 14, count 0 2006.173.19:23:11.84#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.19:23:11.84#ibcon#[25=USB\r\n] 2006.173.19:23:11.84#ibcon#*before write, iclass 14, count 0 2006.173.19:23:11.84#ibcon#enter sib2, iclass 14, count 0 2006.173.19:23:11.84#ibcon#flushed, iclass 14, count 0 2006.173.19:23:11.84#ibcon#about to write, iclass 14, count 0 2006.173.19:23:11.84#ibcon#wrote, iclass 14, count 0 2006.173.19:23:11.84#ibcon#about to read 3, iclass 14, count 0 2006.173.19:23:11.87#ibcon#read 3, iclass 14, count 0 2006.173.19:23:11.87#ibcon#about to read 4, iclass 14, count 0 2006.173.19:23:11.87#ibcon#read 4, iclass 14, count 0 2006.173.19:23:11.87#ibcon#about to read 5, iclass 14, count 0 2006.173.19:23:11.87#ibcon#read 5, iclass 14, count 0 2006.173.19:23:11.87#ibcon#about to read 6, iclass 14, count 0 2006.173.19:23:11.87#ibcon#read 6, iclass 14, count 0 2006.173.19:23:11.87#ibcon#end of sib2, iclass 14, count 0 2006.173.19:23:11.87#ibcon#*after write, iclass 14, count 0 2006.173.19:23:11.87#ibcon#*before return 0, iclass 14, count 0 2006.173.19:23:11.87#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.19:23:11.87#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.19:23:11.87#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.19:23:11.87#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.19:23:11.87$vck44/valo=3,564.99 2006.173.19:23:11.87#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.19:23:11.87#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.19:23:11.87#ibcon#ireg 17 cls_cnt 0 2006.173.19:23:11.87#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.19:23:11.87#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.19:23:11.87#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.19:23:11.87#ibcon#enter wrdev, iclass 16, count 0 2006.173.19:23:11.87#ibcon#first serial, iclass 16, count 0 2006.173.19:23:11.87#ibcon#enter sib2, iclass 16, count 0 2006.173.19:23:11.87#ibcon#flushed, iclass 16, count 0 2006.173.19:23:11.87#ibcon#about to write, iclass 16, count 0 2006.173.19:23:11.87#ibcon#wrote, iclass 16, count 0 2006.173.19:23:11.87#ibcon#about to read 3, iclass 16, count 0 2006.173.19:23:11.89#ibcon#read 3, iclass 16, count 0 2006.173.19:23:11.89#ibcon#about to read 4, iclass 16, count 0 2006.173.19:23:11.89#ibcon#read 4, iclass 16, count 0 2006.173.19:23:11.89#ibcon#about to read 5, iclass 16, count 0 2006.173.19:23:11.89#ibcon#read 5, iclass 16, count 0 2006.173.19:23:11.89#ibcon#about to read 6, iclass 16, count 0 2006.173.19:23:11.89#ibcon#read 6, iclass 16, count 0 2006.173.19:23:11.89#ibcon#end of sib2, iclass 16, count 0 2006.173.19:23:11.89#ibcon#*mode == 0, iclass 16, count 0 2006.173.19:23:11.89#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.19:23:11.89#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.19:23:11.89#ibcon#*before write, iclass 16, count 0 2006.173.19:23:11.89#ibcon#enter sib2, iclass 16, count 0 2006.173.19:23:11.89#ibcon#flushed, iclass 16, count 0 2006.173.19:23:11.89#ibcon#about to write, iclass 16, count 0 2006.173.19:23:11.89#ibcon#wrote, iclass 16, count 0 2006.173.19:23:11.89#ibcon#about to read 3, iclass 16, count 0 2006.173.19:23:11.93#ibcon#read 3, iclass 16, count 0 2006.173.19:23:11.93#ibcon#about to read 4, iclass 16, count 0 2006.173.19:23:11.93#ibcon#read 4, iclass 16, count 0 2006.173.19:23:11.93#ibcon#about to read 5, iclass 16, count 0 2006.173.19:23:11.93#ibcon#read 5, iclass 16, count 0 2006.173.19:23:11.93#ibcon#about to read 6, iclass 16, count 0 2006.173.19:23:11.93#ibcon#read 6, iclass 16, count 0 2006.173.19:23:11.93#ibcon#end of sib2, iclass 16, count 0 2006.173.19:23:11.93#ibcon#*after write, iclass 16, count 0 2006.173.19:23:11.93#ibcon#*before return 0, iclass 16, count 0 2006.173.19:23:11.93#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.19:23:11.93#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.19:23:11.93#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.19:23:11.93#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.19:23:11.93$vck44/va=3,5 2006.173.19:23:11.93#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.19:23:11.93#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.19:23:11.93#ibcon#ireg 11 cls_cnt 2 2006.173.19:23:11.93#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.19:23:11.99#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.19:23:11.99#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.19:23:11.99#ibcon#enter wrdev, iclass 18, count 2 2006.173.19:23:11.99#ibcon#first serial, iclass 18, count 2 2006.173.19:23:11.99#ibcon#enter sib2, iclass 18, count 2 2006.173.19:23:11.99#ibcon#flushed, iclass 18, count 2 2006.173.19:23:11.99#ibcon#about to write, iclass 18, count 2 2006.173.19:23:11.99#ibcon#wrote, iclass 18, count 2 2006.173.19:23:11.99#ibcon#about to read 3, iclass 18, count 2 2006.173.19:23:12.01#ibcon#read 3, iclass 18, count 2 2006.173.19:23:12.01#ibcon#about to read 4, iclass 18, count 2 2006.173.19:23:12.01#ibcon#read 4, iclass 18, count 2 2006.173.19:23:12.01#ibcon#about to read 5, iclass 18, count 2 2006.173.19:23:12.01#ibcon#read 5, iclass 18, count 2 2006.173.19:23:12.01#ibcon#about to read 6, iclass 18, count 2 2006.173.19:23:12.01#ibcon#read 6, iclass 18, count 2 2006.173.19:23:12.01#ibcon#end of sib2, iclass 18, count 2 2006.173.19:23:12.01#ibcon#*mode == 0, iclass 18, count 2 2006.173.19:23:12.01#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.19:23:12.01#ibcon#[25=AT03-05\r\n] 2006.173.19:23:12.01#ibcon#*before write, iclass 18, count 2 2006.173.19:23:12.01#ibcon#enter sib2, iclass 18, count 2 2006.173.19:23:12.01#ibcon#flushed, iclass 18, count 2 2006.173.19:23:12.01#ibcon#about to write, iclass 18, count 2 2006.173.19:23:12.01#ibcon#wrote, iclass 18, count 2 2006.173.19:23:12.01#ibcon#about to read 3, iclass 18, count 2 2006.173.19:23:12.04#ibcon#read 3, iclass 18, count 2 2006.173.19:23:12.04#ibcon#about to read 4, iclass 18, count 2 2006.173.19:23:12.04#ibcon#read 4, iclass 18, count 2 2006.173.19:23:12.04#ibcon#about to read 5, iclass 18, count 2 2006.173.19:23:12.04#ibcon#read 5, iclass 18, count 2 2006.173.19:23:12.04#ibcon#about to read 6, iclass 18, count 2 2006.173.19:23:12.04#ibcon#read 6, iclass 18, count 2 2006.173.19:23:12.04#ibcon#end of sib2, iclass 18, count 2 2006.173.19:23:12.04#ibcon#*after write, iclass 18, count 2 2006.173.19:23:12.04#ibcon#*before return 0, iclass 18, count 2 2006.173.19:23:12.04#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.19:23:12.04#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.19:23:12.04#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.19:23:12.04#ibcon#ireg 7 cls_cnt 0 2006.173.19:23:12.04#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.19:23:12.16#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.19:23:12.16#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.19:23:12.16#ibcon#enter wrdev, iclass 18, count 0 2006.173.19:23:12.16#ibcon#first serial, iclass 18, count 0 2006.173.19:23:12.16#ibcon#enter sib2, iclass 18, count 0 2006.173.19:23:12.16#ibcon#flushed, iclass 18, count 0 2006.173.19:23:12.16#ibcon#about to write, iclass 18, count 0 2006.173.19:23:12.16#ibcon#wrote, iclass 18, count 0 2006.173.19:23:12.16#ibcon#about to read 3, iclass 18, count 0 2006.173.19:23:12.18#ibcon#read 3, iclass 18, count 0 2006.173.19:23:12.18#ibcon#about to read 4, iclass 18, count 0 2006.173.19:23:12.18#ibcon#read 4, iclass 18, count 0 2006.173.19:23:12.18#ibcon#about to read 5, iclass 18, count 0 2006.173.19:23:12.18#ibcon#read 5, iclass 18, count 0 2006.173.19:23:12.18#ibcon#about to read 6, iclass 18, count 0 2006.173.19:23:12.18#ibcon#read 6, iclass 18, count 0 2006.173.19:23:12.18#ibcon#end of sib2, iclass 18, count 0 2006.173.19:23:12.18#ibcon#*mode == 0, iclass 18, count 0 2006.173.19:23:12.18#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.19:23:12.18#ibcon#[25=USB\r\n] 2006.173.19:23:12.18#ibcon#*before write, iclass 18, count 0 2006.173.19:23:12.18#ibcon#enter sib2, iclass 18, count 0 2006.173.19:23:12.18#ibcon#flushed, iclass 18, count 0 2006.173.19:23:12.18#ibcon#about to write, iclass 18, count 0 2006.173.19:23:12.18#ibcon#wrote, iclass 18, count 0 2006.173.19:23:12.18#ibcon#about to read 3, iclass 18, count 0 2006.173.19:23:12.21#ibcon#read 3, iclass 18, count 0 2006.173.19:23:12.21#ibcon#about to read 4, iclass 18, count 0 2006.173.19:23:12.21#ibcon#read 4, iclass 18, count 0 2006.173.19:23:12.21#ibcon#about to read 5, iclass 18, count 0 2006.173.19:23:12.21#ibcon#read 5, iclass 18, count 0 2006.173.19:23:12.21#ibcon#about to read 6, iclass 18, count 0 2006.173.19:23:12.21#ibcon#read 6, iclass 18, count 0 2006.173.19:23:12.21#ibcon#end of sib2, iclass 18, count 0 2006.173.19:23:12.21#ibcon#*after write, iclass 18, count 0 2006.173.19:23:12.21#ibcon#*before return 0, iclass 18, count 0 2006.173.19:23:12.21#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.19:23:12.21#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.19:23:12.21#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.19:23:12.21#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.19:23:12.21$vck44/valo=4,624.99 2006.173.19:23:12.21#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.19:23:12.21#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.19:23:12.21#ibcon#ireg 17 cls_cnt 0 2006.173.19:23:12.21#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.19:23:12.21#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.19:23:12.21#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.19:23:12.21#ibcon#enter wrdev, iclass 20, count 0 2006.173.19:23:12.21#ibcon#first serial, iclass 20, count 0 2006.173.19:23:12.21#ibcon#enter sib2, iclass 20, count 0 2006.173.19:23:12.21#ibcon#flushed, iclass 20, count 0 2006.173.19:23:12.21#ibcon#about to write, iclass 20, count 0 2006.173.19:23:12.21#ibcon#wrote, iclass 20, count 0 2006.173.19:23:12.21#ibcon#about to read 3, iclass 20, count 0 2006.173.19:23:12.23#ibcon#read 3, iclass 20, count 0 2006.173.19:23:12.23#ibcon#about to read 4, iclass 20, count 0 2006.173.19:23:12.23#ibcon#read 4, iclass 20, count 0 2006.173.19:23:12.23#ibcon#about to read 5, iclass 20, count 0 2006.173.19:23:12.23#ibcon#read 5, iclass 20, count 0 2006.173.19:23:12.23#ibcon#about to read 6, iclass 20, count 0 2006.173.19:23:12.23#ibcon#read 6, iclass 20, count 0 2006.173.19:23:12.23#ibcon#end of sib2, iclass 20, count 0 2006.173.19:23:12.23#ibcon#*mode == 0, iclass 20, count 0 2006.173.19:23:12.23#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.19:23:12.23#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.19:23:12.23#ibcon#*before write, iclass 20, count 0 2006.173.19:23:12.23#ibcon#enter sib2, iclass 20, count 0 2006.173.19:23:12.23#ibcon#flushed, iclass 20, count 0 2006.173.19:23:12.23#ibcon#about to write, iclass 20, count 0 2006.173.19:23:12.23#ibcon#wrote, iclass 20, count 0 2006.173.19:23:12.23#ibcon#about to read 3, iclass 20, count 0 2006.173.19:23:12.27#ibcon#read 3, iclass 20, count 0 2006.173.19:23:12.27#ibcon#about to read 4, iclass 20, count 0 2006.173.19:23:12.27#ibcon#read 4, iclass 20, count 0 2006.173.19:23:12.27#ibcon#about to read 5, iclass 20, count 0 2006.173.19:23:12.27#ibcon#read 5, iclass 20, count 0 2006.173.19:23:12.27#ibcon#about to read 6, iclass 20, count 0 2006.173.19:23:12.27#ibcon#read 6, iclass 20, count 0 2006.173.19:23:12.27#ibcon#end of sib2, iclass 20, count 0 2006.173.19:23:12.27#ibcon#*after write, iclass 20, count 0 2006.173.19:23:12.27#ibcon#*before return 0, iclass 20, count 0 2006.173.19:23:12.27#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.19:23:12.27#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.19:23:12.27#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.19:23:12.27#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.19:23:12.27$vck44/va=4,6 2006.173.19:23:12.27#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.19:23:12.27#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.19:23:12.27#ibcon#ireg 11 cls_cnt 2 2006.173.19:23:12.27#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.19:23:12.33#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.19:23:12.33#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.19:23:12.33#ibcon#enter wrdev, iclass 22, count 2 2006.173.19:23:12.33#ibcon#first serial, iclass 22, count 2 2006.173.19:23:12.33#ibcon#enter sib2, iclass 22, count 2 2006.173.19:23:12.33#ibcon#flushed, iclass 22, count 2 2006.173.19:23:12.33#ibcon#about to write, iclass 22, count 2 2006.173.19:23:12.33#ibcon#wrote, iclass 22, count 2 2006.173.19:23:12.33#ibcon#about to read 3, iclass 22, count 2 2006.173.19:23:12.35#ibcon#read 3, iclass 22, count 2 2006.173.19:23:12.35#ibcon#about to read 4, iclass 22, count 2 2006.173.19:23:12.35#ibcon#read 4, iclass 22, count 2 2006.173.19:23:12.35#ibcon#about to read 5, iclass 22, count 2 2006.173.19:23:12.35#ibcon#read 5, iclass 22, count 2 2006.173.19:23:12.35#ibcon#about to read 6, iclass 22, count 2 2006.173.19:23:12.35#ibcon#read 6, iclass 22, count 2 2006.173.19:23:12.35#ibcon#end of sib2, iclass 22, count 2 2006.173.19:23:12.35#ibcon#*mode == 0, iclass 22, count 2 2006.173.19:23:12.35#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.19:23:12.35#ibcon#[25=AT04-06\r\n] 2006.173.19:23:12.35#ibcon#*before write, iclass 22, count 2 2006.173.19:23:12.35#ibcon#enter sib2, iclass 22, count 2 2006.173.19:23:12.35#ibcon#flushed, iclass 22, count 2 2006.173.19:23:12.35#ibcon#about to write, iclass 22, count 2 2006.173.19:23:12.35#ibcon#wrote, iclass 22, count 2 2006.173.19:23:12.35#ibcon#about to read 3, iclass 22, count 2 2006.173.19:23:12.38#ibcon#read 3, iclass 22, count 2 2006.173.19:23:12.38#ibcon#about to read 4, iclass 22, count 2 2006.173.19:23:12.38#ibcon#read 4, iclass 22, count 2 2006.173.19:23:12.38#ibcon#about to read 5, iclass 22, count 2 2006.173.19:23:12.38#ibcon#read 5, iclass 22, count 2 2006.173.19:23:12.38#ibcon#about to read 6, iclass 22, count 2 2006.173.19:23:12.38#ibcon#read 6, iclass 22, count 2 2006.173.19:23:12.38#ibcon#end of sib2, iclass 22, count 2 2006.173.19:23:12.38#ibcon#*after write, iclass 22, count 2 2006.173.19:23:12.38#ibcon#*before return 0, iclass 22, count 2 2006.173.19:23:12.38#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.19:23:12.38#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.19:23:12.38#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.19:23:12.38#ibcon#ireg 7 cls_cnt 0 2006.173.19:23:12.38#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.19:23:12.50#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.19:23:12.50#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.19:23:12.50#ibcon#enter wrdev, iclass 22, count 0 2006.173.19:23:12.50#ibcon#first serial, iclass 22, count 0 2006.173.19:23:12.50#ibcon#enter sib2, iclass 22, count 0 2006.173.19:23:12.50#ibcon#flushed, iclass 22, count 0 2006.173.19:23:12.50#ibcon#about to write, iclass 22, count 0 2006.173.19:23:12.50#ibcon#wrote, iclass 22, count 0 2006.173.19:23:12.50#ibcon#about to read 3, iclass 22, count 0 2006.173.19:23:12.52#ibcon#read 3, iclass 22, count 0 2006.173.19:23:12.52#ibcon#about to read 4, iclass 22, count 0 2006.173.19:23:12.52#ibcon#read 4, iclass 22, count 0 2006.173.19:23:12.52#ibcon#about to read 5, iclass 22, count 0 2006.173.19:23:12.52#ibcon#read 5, iclass 22, count 0 2006.173.19:23:12.52#ibcon#about to read 6, iclass 22, count 0 2006.173.19:23:12.52#ibcon#read 6, iclass 22, count 0 2006.173.19:23:12.52#ibcon#end of sib2, iclass 22, count 0 2006.173.19:23:12.52#ibcon#*mode == 0, iclass 22, count 0 2006.173.19:23:12.52#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.19:23:12.52#ibcon#[25=USB\r\n] 2006.173.19:23:12.52#ibcon#*before write, iclass 22, count 0 2006.173.19:23:12.52#ibcon#enter sib2, iclass 22, count 0 2006.173.19:23:12.52#ibcon#flushed, iclass 22, count 0 2006.173.19:23:12.52#ibcon#about to write, iclass 22, count 0 2006.173.19:23:12.52#ibcon#wrote, iclass 22, count 0 2006.173.19:23:12.52#ibcon#about to read 3, iclass 22, count 0 2006.173.19:23:12.55#ibcon#read 3, iclass 22, count 0 2006.173.19:23:12.55#ibcon#about to read 4, iclass 22, count 0 2006.173.19:23:12.55#ibcon#read 4, iclass 22, count 0 2006.173.19:23:12.55#ibcon#about to read 5, iclass 22, count 0 2006.173.19:23:12.55#ibcon#read 5, iclass 22, count 0 2006.173.19:23:12.55#ibcon#about to read 6, iclass 22, count 0 2006.173.19:23:12.55#ibcon#read 6, iclass 22, count 0 2006.173.19:23:12.55#ibcon#end of sib2, iclass 22, count 0 2006.173.19:23:12.55#ibcon#*after write, iclass 22, count 0 2006.173.19:23:12.55#ibcon#*before return 0, iclass 22, count 0 2006.173.19:23:12.55#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.19:23:12.55#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.19:23:12.55#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.19:23:12.55#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.19:23:12.55$vck44/valo=5,734.99 2006.173.19:23:12.55#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.19:23:12.55#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.19:23:12.55#ibcon#ireg 17 cls_cnt 0 2006.173.19:23:12.55#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.19:23:12.55#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.19:23:12.55#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.19:23:12.55#ibcon#enter wrdev, iclass 24, count 0 2006.173.19:23:12.55#ibcon#first serial, iclass 24, count 0 2006.173.19:23:12.55#ibcon#enter sib2, iclass 24, count 0 2006.173.19:23:12.55#ibcon#flushed, iclass 24, count 0 2006.173.19:23:12.55#ibcon#about to write, iclass 24, count 0 2006.173.19:23:12.55#ibcon#wrote, iclass 24, count 0 2006.173.19:23:12.55#ibcon#about to read 3, iclass 24, count 0 2006.173.19:23:12.57#ibcon#read 3, iclass 24, count 0 2006.173.19:23:12.57#ibcon#about to read 4, iclass 24, count 0 2006.173.19:23:12.57#ibcon#read 4, iclass 24, count 0 2006.173.19:23:12.57#ibcon#about to read 5, iclass 24, count 0 2006.173.19:23:12.57#ibcon#read 5, iclass 24, count 0 2006.173.19:23:12.57#ibcon#about to read 6, iclass 24, count 0 2006.173.19:23:12.57#ibcon#read 6, iclass 24, count 0 2006.173.19:23:12.57#ibcon#end of sib2, iclass 24, count 0 2006.173.19:23:12.57#ibcon#*mode == 0, iclass 24, count 0 2006.173.19:23:12.57#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.19:23:12.57#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.19:23:12.57#ibcon#*before write, iclass 24, count 0 2006.173.19:23:12.57#ibcon#enter sib2, iclass 24, count 0 2006.173.19:23:12.57#ibcon#flushed, iclass 24, count 0 2006.173.19:23:12.57#ibcon#about to write, iclass 24, count 0 2006.173.19:23:12.57#ibcon#wrote, iclass 24, count 0 2006.173.19:23:12.57#ibcon#about to read 3, iclass 24, count 0 2006.173.19:23:12.61#ibcon#read 3, iclass 24, count 0 2006.173.19:23:12.61#ibcon#about to read 4, iclass 24, count 0 2006.173.19:23:12.61#ibcon#read 4, iclass 24, count 0 2006.173.19:23:12.61#ibcon#about to read 5, iclass 24, count 0 2006.173.19:23:12.61#ibcon#read 5, iclass 24, count 0 2006.173.19:23:12.61#ibcon#about to read 6, iclass 24, count 0 2006.173.19:23:12.61#ibcon#read 6, iclass 24, count 0 2006.173.19:23:12.61#ibcon#end of sib2, iclass 24, count 0 2006.173.19:23:12.61#ibcon#*after write, iclass 24, count 0 2006.173.19:23:12.61#ibcon#*before return 0, iclass 24, count 0 2006.173.19:23:12.61#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.19:23:12.61#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.19:23:12.61#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.19:23:12.61#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.19:23:12.61$vck44/va=5,4 2006.173.19:23:12.61#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.19:23:12.61#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.19:23:12.61#ibcon#ireg 11 cls_cnt 2 2006.173.19:23:12.61#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.19:23:12.67#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.19:23:12.67#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.19:23:12.67#ibcon#enter wrdev, iclass 26, count 2 2006.173.19:23:12.67#ibcon#first serial, iclass 26, count 2 2006.173.19:23:12.67#ibcon#enter sib2, iclass 26, count 2 2006.173.19:23:12.67#ibcon#flushed, iclass 26, count 2 2006.173.19:23:12.67#ibcon#about to write, iclass 26, count 2 2006.173.19:23:12.67#ibcon#wrote, iclass 26, count 2 2006.173.19:23:12.67#ibcon#about to read 3, iclass 26, count 2 2006.173.19:23:12.69#ibcon#read 3, iclass 26, count 2 2006.173.19:23:12.69#ibcon#about to read 4, iclass 26, count 2 2006.173.19:23:12.69#ibcon#read 4, iclass 26, count 2 2006.173.19:23:12.69#ibcon#about to read 5, iclass 26, count 2 2006.173.19:23:12.69#ibcon#read 5, iclass 26, count 2 2006.173.19:23:12.69#ibcon#about to read 6, iclass 26, count 2 2006.173.19:23:12.69#ibcon#read 6, iclass 26, count 2 2006.173.19:23:12.69#ibcon#end of sib2, iclass 26, count 2 2006.173.19:23:12.69#ibcon#*mode == 0, iclass 26, count 2 2006.173.19:23:12.69#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.19:23:12.69#ibcon#[25=AT05-04\r\n] 2006.173.19:23:12.69#ibcon#*before write, iclass 26, count 2 2006.173.19:23:12.69#ibcon#enter sib2, iclass 26, count 2 2006.173.19:23:12.69#ibcon#flushed, iclass 26, count 2 2006.173.19:23:12.69#ibcon#about to write, iclass 26, count 2 2006.173.19:23:12.69#ibcon#wrote, iclass 26, count 2 2006.173.19:23:12.69#ibcon#about to read 3, iclass 26, count 2 2006.173.19:23:12.72#ibcon#read 3, iclass 26, count 2 2006.173.19:23:12.72#ibcon#about to read 4, iclass 26, count 2 2006.173.19:23:12.72#ibcon#read 4, iclass 26, count 2 2006.173.19:23:12.72#ibcon#about to read 5, iclass 26, count 2 2006.173.19:23:12.72#ibcon#read 5, iclass 26, count 2 2006.173.19:23:12.72#ibcon#about to read 6, iclass 26, count 2 2006.173.19:23:12.72#ibcon#read 6, iclass 26, count 2 2006.173.19:23:12.72#ibcon#end of sib2, iclass 26, count 2 2006.173.19:23:12.72#ibcon#*after write, iclass 26, count 2 2006.173.19:23:12.72#ibcon#*before return 0, iclass 26, count 2 2006.173.19:23:12.72#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.19:23:12.72#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.19:23:12.72#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.19:23:12.72#ibcon#ireg 7 cls_cnt 0 2006.173.19:23:12.72#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.19:23:12.84#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.19:23:12.84#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.19:23:12.84#ibcon#enter wrdev, iclass 26, count 0 2006.173.19:23:12.84#ibcon#first serial, iclass 26, count 0 2006.173.19:23:12.84#ibcon#enter sib2, iclass 26, count 0 2006.173.19:23:12.84#ibcon#flushed, iclass 26, count 0 2006.173.19:23:12.84#ibcon#about to write, iclass 26, count 0 2006.173.19:23:12.84#ibcon#wrote, iclass 26, count 0 2006.173.19:23:12.84#ibcon#about to read 3, iclass 26, count 0 2006.173.19:23:12.86#ibcon#read 3, iclass 26, count 0 2006.173.19:23:12.86#ibcon#about to read 4, iclass 26, count 0 2006.173.19:23:12.86#ibcon#read 4, iclass 26, count 0 2006.173.19:23:12.86#ibcon#about to read 5, iclass 26, count 0 2006.173.19:23:12.86#ibcon#read 5, iclass 26, count 0 2006.173.19:23:12.86#ibcon#about to read 6, iclass 26, count 0 2006.173.19:23:12.86#ibcon#read 6, iclass 26, count 0 2006.173.19:23:12.86#ibcon#end of sib2, iclass 26, count 0 2006.173.19:23:12.86#ibcon#*mode == 0, iclass 26, count 0 2006.173.19:23:12.86#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.19:23:12.86#ibcon#[25=USB\r\n] 2006.173.19:23:12.86#ibcon#*before write, iclass 26, count 0 2006.173.19:23:12.86#ibcon#enter sib2, iclass 26, count 0 2006.173.19:23:12.86#ibcon#flushed, iclass 26, count 0 2006.173.19:23:12.86#ibcon#about to write, iclass 26, count 0 2006.173.19:23:12.86#ibcon#wrote, iclass 26, count 0 2006.173.19:23:12.86#ibcon#about to read 3, iclass 26, count 0 2006.173.19:23:12.89#ibcon#read 3, iclass 26, count 0 2006.173.19:23:12.89#ibcon#about to read 4, iclass 26, count 0 2006.173.19:23:12.89#ibcon#read 4, iclass 26, count 0 2006.173.19:23:12.89#ibcon#about to read 5, iclass 26, count 0 2006.173.19:23:12.89#ibcon#read 5, iclass 26, count 0 2006.173.19:23:12.89#ibcon#about to read 6, iclass 26, count 0 2006.173.19:23:12.89#ibcon#read 6, iclass 26, count 0 2006.173.19:23:12.89#ibcon#end of sib2, iclass 26, count 0 2006.173.19:23:12.89#ibcon#*after write, iclass 26, count 0 2006.173.19:23:12.89#ibcon#*before return 0, iclass 26, count 0 2006.173.19:23:12.89#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.19:23:12.89#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.19:23:12.89#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.19:23:12.89#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.19:23:12.89$vck44/valo=6,814.99 2006.173.19:23:12.89#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.19:23:12.89#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.19:23:12.89#ibcon#ireg 17 cls_cnt 0 2006.173.19:23:12.89#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.19:23:12.89#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.19:23:12.89#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.19:23:12.89#ibcon#enter wrdev, iclass 28, count 0 2006.173.19:23:12.89#ibcon#first serial, iclass 28, count 0 2006.173.19:23:12.89#ibcon#enter sib2, iclass 28, count 0 2006.173.19:23:12.89#ibcon#flushed, iclass 28, count 0 2006.173.19:23:12.89#ibcon#about to write, iclass 28, count 0 2006.173.19:23:12.89#ibcon#wrote, iclass 28, count 0 2006.173.19:23:12.89#ibcon#about to read 3, iclass 28, count 0 2006.173.19:23:12.91#ibcon#read 3, iclass 28, count 0 2006.173.19:23:12.91#ibcon#about to read 4, iclass 28, count 0 2006.173.19:23:12.91#ibcon#read 4, iclass 28, count 0 2006.173.19:23:12.91#ibcon#about to read 5, iclass 28, count 0 2006.173.19:23:12.91#ibcon#read 5, iclass 28, count 0 2006.173.19:23:12.91#ibcon#about to read 6, iclass 28, count 0 2006.173.19:23:12.91#ibcon#read 6, iclass 28, count 0 2006.173.19:23:12.91#ibcon#end of sib2, iclass 28, count 0 2006.173.19:23:12.91#ibcon#*mode == 0, iclass 28, count 0 2006.173.19:23:12.91#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.19:23:12.91#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.19:23:12.91#ibcon#*before write, iclass 28, count 0 2006.173.19:23:12.91#ibcon#enter sib2, iclass 28, count 0 2006.173.19:23:12.91#ibcon#flushed, iclass 28, count 0 2006.173.19:23:12.91#ibcon#about to write, iclass 28, count 0 2006.173.19:23:12.91#ibcon#wrote, iclass 28, count 0 2006.173.19:23:12.91#ibcon#about to read 3, iclass 28, count 0 2006.173.19:23:12.95#ibcon#read 3, iclass 28, count 0 2006.173.19:23:12.95#ibcon#about to read 4, iclass 28, count 0 2006.173.19:23:12.95#ibcon#read 4, iclass 28, count 0 2006.173.19:23:12.95#ibcon#about to read 5, iclass 28, count 0 2006.173.19:23:12.95#ibcon#read 5, iclass 28, count 0 2006.173.19:23:12.95#ibcon#about to read 6, iclass 28, count 0 2006.173.19:23:12.95#ibcon#read 6, iclass 28, count 0 2006.173.19:23:12.95#ibcon#end of sib2, iclass 28, count 0 2006.173.19:23:12.95#ibcon#*after write, iclass 28, count 0 2006.173.19:23:12.95#ibcon#*before return 0, iclass 28, count 0 2006.173.19:23:12.95#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.19:23:12.95#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.19:23:12.95#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.19:23:12.95#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.19:23:12.95$vck44/va=6,3 2006.173.19:23:12.95#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.19:23:12.95#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.19:23:12.95#ibcon#ireg 11 cls_cnt 2 2006.173.19:23:12.95#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.19:23:13.01#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.19:23:13.01#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.19:23:13.01#ibcon#enter wrdev, iclass 30, count 2 2006.173.19:23:13.01#ibcon#first serial, iclass 30, count 2 2006.173.19:23:13.01#ibcon#enter sib2, iclass 30, count 2 2006.173.19:23:13.01#ibcon#flushed, iclass 30, count 2 2006.173.19:23:13.01#ibcon#about to write, iclass 30, count 2 2006.173.19:23:13.01#ibcon#wrote, iclass 30, count 2 2006.173.19:23:13.01#ibcon#about to read 3, iclass 30, count 2 2006.173.19:23:13.03#ibcon#read 3, iclass 30, count 2 2006.173.19:23:13.03#ibcon#about to read 4, iclass 30, count 2 2006.173.19:23:13.03#ibcon#read 4, iclass 30, count 2 2006.173.19:23:13.03#ibcon#about to read 5, iclass 30, count 2 2006.173.19:23:13.03#ibcon#read 5, iclass 30, count 2 2006.173.19:23:13.03#ibcon#about to read 6, iclass 30, count 2 2006.173.19:23:13.03#ibcon#read 6, iclass 30, count 2 2006.173.19:23:13.03#ibcon#end of sib2, iclass 30, count 2 2006.173.19:23:13.03#ibcon#*mode == 0, iclass 30, count 2 2006.173.19:23:13.03#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.19:23:13.03#ibcon#[25=AT06-03\r\n] 2006.173.19:23:13.03#ibcon#*before write, iclass 30, count 2 2006.173.19:23:13.03#ibcon#enter sib2, iclass 30, count 2 2006.173.19:23:13.03#ibcon#flushed, iclass 30, count 2 2006.173.19:23:13.03#ibcon#about to write, iclass 30, count 2 2006.173.19:23:13.03#ibcon#wrote, iclass 30, count 2 2006.173.19:23:13.03#ibcon#about to read 3, iclass 30, count 2 2006.173.19:23:13.06#ibcon#read 3, iclass 30, count 2 2006.173.19:23:13.06#ibcon#about to read 4, iclass 30, count 2 2006.173.19:23:13.06#ibcon#read 4, iclass 30, count 2 2006.173.19:23:13.06#ibcon#about to read 5, iclass 30, count 2 2006.173.19:23:13.06#ibcon#read 5, iclass 30, count 2 2006.173.19:23:13.06#ibcon#about to read 6, iclass 30, count 2 2006.173.19:23:13.06#ibcon#read 6, iclass 30, count 2 2006.173.19:23:13.06#ibcon#end of sib2, iclass 30, count 2 2006.173.19:23:13.06#ibcon#*after write, iclass 30, count 2 2006.173.19:23:13.06#ibcon#*before return 0, iclass 30, count 2 2006.173.19:23:13.06#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.19:23:13.06#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.19:23:13.06#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.19:23:13.06#ibcon#ireg 7 cls_cnt 0 2006.173.19:23:13.06#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.19:23:13.18#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.19:23:13.18#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.19:23:13.18#ibcon#enter wrdev, iclass 30, count 0 2006.173.19:23:13.18#ibcon#first serial, iclass 30, count 0 2006.173.19:23:13.18#ibcon#enter sib2, iclass 30, count 0 2006.173.19:23:13.18#ibcon#flushed, iclass 30, count 0 2006.173.19:23:13.18#ibcon#about to write, iclass 30, count 0 2006.173.19:23:13.18#ibcon#wrote, iclass 30, count 0 2006.173.19:23:13.18#ibcon#about to read 3, iclass 30, count 0 2006.173.19:23:13.20#ibcon#read 3, iclass 30, count 0 2006.173.19:23:13.20#ibcon#about to read 4, iclass 30, count 0 2006.173.19:23:13.20#ibcon#read 4, iclass 30, count 0 2006.173.19:23:13.20#ibcon#about to read 5, iclass 30, count 0 2006.173.19:23:13.20#ibcon#read 5, iclass 30, count 0 2006.173.19:23:13.20#ibcon#about to read 6, iclass 30, count 0 2006.173.19:23:13.20#ibcon#read 6, iclass 30, count 0 2006.173.19:23:13.20#ibcon#end of sib2, iclass 30, count 0 2006.173.19:23:13.20#ibcon#*mode == 0, iclass 30, count 0 2006.173.19:23:13.20#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.19:23:13.20#ibcon#[25=USB\r\n] 2006.173.19:23:13.20#ibcon#*before write, iclass 30, count 0 2006.173.19:23:13.20#ibcon#enter sib2, iclass 30, count 0 2006.173.19:23:13.20#ibcon#flushed, iclass 30, count 0 2006.173.19:23:13.20#ibcon#about to write, iclass 30, count 0 2006.173.19:23:13.20#ibcon#wrote, iclass 30, count 0 2006.173.19:23:13.20#ibcon#about to read 3, iclass 30, count 0 2006.173.19:23:13.23#ibcon#read 3, iclass 30, count 0 2006.173.19:23:13.23#ibcon#about to read 4, iclass 30, count 0 2006.173.19:23:13.23#ibcon#read 4, iclass 30, count 0 2006.173.19:23:13.23#ibcon#about to read 5, iclass 30, count 0 2006.173.19:23:13.23#ibcon#read 5, iclass 30, count 0 2006.173.19:23:13.23#ibcon#about to read 6, iclass 30, count 0 2006.173.19:23:13.23#ibcon#read 6, iclass 30, count 0 2006.173.19:23:13.23#ibcon#end of sib2, iclass 30, count 0 2006.173.19:23:13.23#ibcon#*after write, iclass 30, count 0 2006.173.19:23:13.23#ibcon#*before return 0, iclass 30, count 0 2006.173.19:23:13.23#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.19:23:13.23#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.19:23:13.23#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.19:23:13.23#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.19:23:13.23$vck44/valo=7,864.99 2006.173.19:23:13.23#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.19:23:13.23#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.19:23:13.23#ibcon#ireg 17 cls_cnt 0 2006.173.19:23:13.23#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.19:23:13.23#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.19:23:13.23#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.19:23:13.23#ibcon#enter wrdev, iclass 32, count 0 2006.173.19:23:13.23#ibcon#first serial, iclass 32, count 0 2006.173.19:23:13.23#ibcon#enter sib2, iclass 32, count 0 2006.173.19:23:13.23#ibcon#flushed, iclass 32, count 0 2006.173.19:23:13.23#ibcon#about to write, iclass 32, count 0 2006.173.19:23:13.23#ibcon#wrote, iclass 32, count 0 2006.173.19:23:13.23#ibcon#about to read 3, iclass 32, count 0 2006.173.19:23:13.25#ibcon#read 3, iclass 32, count 0 2006.173.19:23:13.25#ibcon#about to read 4, iclass 32, count 0 2006.173.19:23:13.25#ibcon#read 4, iclass 32, count 0 2006.173.19:23:13.25#ibcon#about to read 5, iclass 32, count 0 2006.173.19:23:13.25#ibcon#read 5, iclass 32, count 0 2006.173.19:23:13.25#ibcon#about to read 6, iclass 32, count 0 2006.173.19:23:13.25#ibcon#read 6, iclass 32, count 0 2006.173.19:23:13.25#ibcon#end of sib2, iclass 32, count 0 2006.173.19:23:13.25#ibcon#*mode == 0, iclass 32, count 0 2006.173.19:23:13.25#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.19:23:13.25#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.19:23:13.25#ibcon#*before write, iclass 32, count 0 2006.173.19:23:13.25#ibcon#enter sib2, iclass 32, count 0 2006.173.19:23:13.25#ibcon#flushed, iclass 32, count 0 2006.173.19:23:13.25#ibcon#about to write, iclass 32, count 0 2006.173.19:23:13.25#ibcon#wrote, iclass 32, count 0 2006.173.19:23:13.25#ibcon#about to read 3, iclass 32, count 0 2006.173.19:23:13.29#ibcon#read 3, iclass 32, count 0 2006.173.19:23:13.29#ibcon#about to read 4, iclass 32, count 0 2006.173.19:23:13.29#ibcon#read 4, iclass 32, count 0 2006.173.19:23:13.29#ibcon#about to read 5, iclass 32, count 0 2006.173.19:23:13.29#ibcon#read 5, iclass 32, count 0 2006.173.19:23:13.29#ibcon#about to read 6, iclass 32, count 0 2006.173.19:23:13.29#ibcon#read 6, iclass 32, count 0 2006.173.19:23:13.29#ibcon#end of sib2, iclass 32, count 0 2006.173.19:23:13.29#ibcon#*after write, iclass 32, count 0 2006.173.19:23:13.29#ibcon#*before return 0, iclass 32, count 0 2006.173.19:23:13.29#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.19:23:13.29#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.19:23:13.29#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.19:23:13.29#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.19:23:13.29$vck44/va=7,4 2006.173.19:23:13.29#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.19:23:13.29#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.19:23:13.29#ibcon#ireg 11 cls_cnt 2 2006.173.19:23:13.29#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.19:23:13.35#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.19:23:13.35#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.19:23:13.35#ibcon#enter wrdev, iclass 34, count 2 2006.173.19:23:13.35#ibcon#first serial, iclass 34, count 2 2006.173.19:23:13.35#ibcon#enter sib2, iclass 34, count 2 2006.173.19:23:13.35#ibcon#flushed, iclass 34, count 2 2006.173.19:23:13.35#ibcon#about to write, iclass 34, count 2 2006.173.19:23:13.35#ibcon#wrote, iclass 34, count 2 2006.173.19:23:13.35#ibcon#about to read 3, iclass 34, count 2 2006.173.19:23:13.37#ibcon#read 3, iclass 34, count 2 2006.173.19:23:13.37#ibcon#about to read 4, iclass 34, count 2 2006.173.19:23:13.37#ibcon#read 4, iclass 34, count 2 2006.173.19:23:13.37#ibcon#about to read 5, iclass 34, count 2 2006.173.19:23:13.37#ibcon#read 5, iclass 34, count 2 2006.173.19:23:13.37#ibcon#about to read 6, iclass 34, count 2 2006.173.19:23:13.37#ibcon#read 6, iclass 34, count 2 2006.173.19:23:13.37#ibcon#end of sib2, iclass 34, count 2 2006.173.19:23:13.37#ibcon#*mode == 0, iclass 34, count 2 2006.173.19:23:13.37#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.19:23:13.37#ibcon#[25=AT07-04\r\n] 2006.173.19:23:13.37#ibcon#*before write, iclass 34, count 2 2006.173.19:23:13.37#ibcon#enter sib2, iclass 34, count 2 2006.173.19:23:13.37#ibcon#flushed, iclass 34, count 2 2006.173.19:23:13.37#ibcon#about to write, iclass 34, count 2 2006.173.19:23:13.37#ibcon#wrote, iclass 34, count 2 2006.173.19:23:13.37#ibcon#about to read 3, iclass 34, count 2 2006.173.19:23:13.40#ibcon#read 3, iclass 34, count 2 2006.173.19:23:13.40#ibcon#about to read 4, iclass 34, count 2 2006.173.19:23:13.40#ibcon#read 4, iclass 34, count 2 2006.173.19:23:13.40#ibcon#about to read 5, iclass 34, count 2 2006.173.19:23:13.40#ibcon#read 5, iclass 34, count 2 2006.173.19:23:13.40#ibcon#about to read 6, iclass 34, count 2 2006.173.19:23:13.40#ibcon#read 6, iclass 34, count 2 2006.173.19:23:13.40#ibcon#end of sib2, iclass 34, count 2 2006.173.19:23:13.40#ibcon#*after write, iclass 34, count 2 2006.173.19:23:13.40#ibcon#*before return 0, iclass 34, count 2 2006.173.19:23:13.40#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.19:23:13.40#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.19:23:13.40#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.19:23:13.40#ibcon#ireg 7 cls_cnt 0 2006.173.19:23:13.40#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.19:23:13.52#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.19:23:13.52#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.19:23:13.52#ibcon#enter wrdev, iclass 34, count 0 2006.173.19:23:13.52#ibcon#first serial, iclass 34, count 0 2006.173.19:23:13.52#ibcon#enter sib2, iclass 34, count 0 2006.173.19:23:13.52#ibcon#flushed, iclass 34, count 0 2006.173.19:23:13.52#ibcon#about to write, iclass 34, count 0 2006.173.19:23:13.52#ibcon#wrote, iclass 34, count 0 2006.173.19:23:13.52#ibcon#about to read 3, iclass 34, count 0 2006.173.19:23:13.54#ibcon#read 3, iclass 34, count 0 2006.173.19:23:13.54#ibcon#about to read 4, iclass 34, count 0 2006.173.19:23:13.54#ibcon#read 4, iclass 34, count 0 2006.173.19:23:13.54#ibcon#about to read 5, iclass 34, count 0 2006.173.19:23:13.54#ibcon#read 5, iclass 34, count 0 2006.173.19:23:13.54#ibcon#about to read 6, iclass 34, count 0 2006.173.19:23:13.54#ibcon#read 6, iclass 34, count 0 2006.173.19:23:13.54#ibcon#end of sib2, iclass 34, count 0 2006.173.19:23:13.54#ibcon#*mode == 0, iclass 34, count 0 2006.173.19:23:13.54#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.19:23:13.54#ibcon#[25=USB\r\n] 2006.173.19:23:13.54#ibcon#*before write, iclass 34, count 0 2006.173.19:23:13.54#ibcon#enter sib2, iclass 34, count 0 2006.173.19:23:13.54#ibcon#flushed, iclass 34, count 0 2006.173.19:23:13.54#ibcon#about to write, iclass 34, count 0 2006.173.19:23:13.54#ibcon#wrote, iclass 34, count 0 2006.173.19:23:13.54#ibcon#about to read 3, iclass 34, count 0 2006.173.19:23:13.57#ibcon#read 3, iclass 34, count 0 2006.173.19:23:13.57#ibcon#about to read 4, iclass 34, count 0 2006.173.19:23:13.57#ibcon#read 4, iclass 34, count 0 2006.173.19:23:13.57#ibcon#about to read 5, iclass 34, count 0 2006.173.19:23:13.57#ibcon#read 5, iclass 34, count 0 2006.173.19:23:13.57#ibcon#about to read 6, iclass 34, count 0 2006.173.19:23:13.57#ibcon#read 6, iclass 34, count 0 2006.173.19:23:13.57#ibcon#end of sib2, iclass 34, count 0 2006.173.19:23:13.57#ibcon#*after write, iclass 34, count 0 2006.173.19:23:13.57#ibcon#*before return 0, iclass 34, count 0 2006.173.19:23:13.57#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.19:23:13.57#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.19:23:13.57#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.19:23:13.57#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.19:23:13.57$vck44/valo=8,884.99 2006.173.19:23:13.57#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.19:23:13.57#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.19:23:13.57#ibcon#ireg 17 cls_cnt 0 2006.173.19:23:13.57#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.19:23:13.57#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.19:23:13.57#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.19:23:13.57#ibcon#enter wrdev, iclass 36, count 0 2006.173.19:23:13.57#ibcon#first serial, iclass 36, count 0 2006.173.19:23:13.57#ibcon#enter sib2, iclass 36, count 0 2006.173.19:23:13.57#ibcon#flushed, iclass 36, count 0 2006.173.19:23:13.57#ibcon#about to write, iclass 36, count 0 2006.173.19:23:13.57#ibcon#wrote, iclass 36, count 0 2006.173.19:23:13.57#ibcon#about to read 3, iclass 36, count 0 2006.173.19:23:13.59#ibcon#read 3, iclass 36, count 0 2006.173.19:23:13.59#ibcon#about to read 4, iclass 36, count 0 2006.173.19:23:13.59#ibcon#read 4, iclass 36, count 0 2006.173.19:23:13.59#ibcon#about to read 5, iclass 36, count 0 2006.173.19:23:13.59#ibcon#read 5, iclass 36, count 0 2006.173.19:23:13.59#ibcon#about to read 6, iclass 36, count 0 2006.173.19:23:13.59#ibcon#read 6, iclass 36, count 0 2006.173.19:23:13.59#ibcon#end of sib2, iclass 36, count 0 2006.173.19:23:13.59#ibcon#*mode == 0, iclass 36, count 0 2006.173.19:23:13.59#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.19:23:13.59#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.19:23:13.59#ibcon#*before write, iclass 36, count 0 2006.173.19:23:13.59#ibcon#enter sib2, iclass 36, count 0 2006.173.19:23:13.59#ibcon#flushed, iclass 36, count 0 2006.173.19:23:13.59#ibcon#about to write, iclass 36, count 0 2006.173.19:23:13.59#ibcon#wrote, iclass 36, count 0 2006.173.19:23:13.59#ibcon#about to read 3, iclass 36, count 0 2006.173.19:23:13.63#ibcon#read 3, iclass 36, count 0 2006.173.19:23:13.63#ibcon#about to read 4, iclass 36, count 0 2006.173.19:23:13.63#ibcon#read 4, iclass 36, count 0 2006.173.19:23:13.63#ibcon#about to read 5, iclass 36, count 0 2006.173.19:23:13.63#ibcon#read 5, iclass 36, count 0 2006.173.19:23:13.63#ibcon#about to read 6, iclass 36, count 0 2006.173.19:23:13.63#ibcon#read 6, iclass 36, count 0 2006.173.19:23:13.63#ibcon#end of sib2, iclass 36, count 0 2006.173.19:23:13.63#ibcon#*after write, iclass 36, count 0 2006.173.19:23:13.63#ibcon#*before return 0, iclass 36, count 0 2006.173.19:23:13.63#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.19:23:13.63#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.19:23:13.63#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.19:23:13.63#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.19:23:13.63$vck44/va=8,4 2006.173.19:23:13.63#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.19:23:13.63#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.19:23:13.63#ibcon#ireg 11 cls_cnt 2 2006.173.19:23:13.63#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.19:23:13.69#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.19:23:13.69#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.19:23:13.69#ibcon#enter wrdev, iclass 38, count 2 2006.173.19:23:13.69#ibcon#first serial, iclass 38, count 2 2006.173.19:23:13.69#ibcon#enter sib2, iclass 38, count 2 2006.173.19:23:13.69#ibcon#flushed, iclass 38, count 2 2006.173.19:23:13.69#ibcon#about to write, iclass 38, count 2 2006.173.19:23:13.69#ibcon#wrote, iclass 38, count 2 2006.173.19:23:13.69#ibcon#about to read 3, iclass 38, count 2 2006.173.19:23:13.71#ibcon#read 3, iclass 38, count 2 2006.173.19:23:13.71#ibcon#about to read 4, iclass 38, count 2 2006.173.19:23:13.71#ibcon#read 4, iclass 38, count 2 2006.173.19:23:13.71#ibcon#about to read 5, iclass 38, count 2 2006.173.19:23:13.71#ibcon#read 5, iclass 38, count 2 2006.173.19:23:13.71#ibcon#about to read 6, iclass 38, count 2 2006.173.19:23:13.71#ibcon#read 6, iclass 38, count 2 2006.173.19:23:13.71#ibcon#end of sib2, iclass 38, count 2 2006.173.19:23:13.71#ibcon#*mode == 0, iclass 38, count 2 2006.173.19:23:13.71#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.19:23:13.71#ibcon#[25=AT08-04\r\n] 2006.173.19:23:13.71#ibcon#*before write, iclass 38, count 2 2006.173.19:23:13.71#ibcon#enter sib2, iclass 38, count 2 2006.173.19:23:13.71#ibcon#flushed, iclass 38, count 2 2006.173.19:23:13.71#ibcon#about to write, iclass 38, count 2 2006.173.19:23:13.71#ibcon#wrote, iclass 38, count 2 2006.173.19:23:13.71#ibcon#about to read 3, iclass 38, count 2 2006.173.19:23:13.74#ibcon#read 3, iclass 38, count 2 2006.173.19:23:13.74#ibcon#about to read 4, iclass 38, count 2 2006.173.19:23:13.74#ibcon#read 4, iclass 38, count 2 2006.173.19:23:13.74#ibcon#about to read 5, iclass 38, count 2 2006.173.19:23:13.74#ibcon#read 5, iclass 38, count 2 2006.173.19:23:13.74#ibcon#about to read 6, iclass 38, count 2 2006.173.19:23:13.74#ibcon#read 6, iclass 38, count 2 2006.173.19:23:13.74#ibcon#end of sib2, iclass 38, count 2 2006.173.19:23:13.74#ibcon#*after write, iclass 38, count 2 2006.173.19:23:13.74#ibcon#*before return 0, iclass 38, count 2 2006.173.19:23:13.74#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.19:23:13.74#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.19:23:13.74#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.19:23:13.74#ibcon#ireg 7 cls_cnt 0 2006.173.19:23:13.74#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.19:23:13.86#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.19:23:13.86#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.19:23:13.86#ibcon#enter wrdev, iclass 38, count 0 2006.173.19:23:13.86#ibcon#first serial, iclass 38, count 0 2006.173.19:23:13.86#ibcon#enter sib2, iclass 38, count 0 2006.173.19:23:13.86#ibcon#flushed, iclass 38, count 0 2006.173.19:23:13.86#ibcon#about to write, iclass 38, count 0 2006.173.19:23:13.86#ibcon#wrote, iclass 38, count 0 2006.173.19:23:13.86#ibcon#about to read 3, iclass 38, count 0 2006.173.19:23:13.88#ibcon#read 3, iclass 38, count 0 2006.173.19:23:13.88#ibcon#about to read 4, iclass 38, count 0 2006.173.19:23:13.88#ibcon#read 4, iclass 38, count 0 2006.173.19:23:13.88#ibcon#about to read 5, iclass 38, count 0 2006.173.19:23:13.88#ibcon#read 5, iclass 38, count 0 2006.173.19:23:13.88#ibcon#about to read 6, iclass 38, count 0 2006.173.19:23:13.88#ibcon#read 6, iclass 38, count 0 2006.173.19:23:13.88#ibcon#end of sib2, iclass 38, count 0 2006.173.19:23:13.88#ibcon#*mode == 0, iclass 38, count 0 2006.173.19:23:13.88#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.19:23:13.88#ibcon#[25=USB\r\n] 2006.173.19:23:13.88#ibcon#*before write, iclass 38, count 0 2006.173.19:23:13.88#ibcon#enter sib2, iclass 38, count 0 2006.173.19:23:13.88#ibcon#flushed, iclass 38, count 0 2006.173.19:23:13.88#ibcon#about to write, iclass 38, count 0 2006.173.19:23:13.88#ibcon#wrote, iclass 38, count 0 2006.173.19:23:13.88#ibcon#about to read 3, iclass 38, count 0 2006.173.19:23:13.91#ibcon#read 3, iclass 38, count 0 2006.173.19:23:13.91#ibcon#about to read 4, iclass 38, count 0 2006.173.19:23:13.91#ibcon#read 4, iclass 38, count 0 2006.173.19:23:13.91#ibcon#about to read 5, iclass 38, count 0 2006.173.19:23:13.91#ibcon#read 5, iclass 38, count 0 2006.173.19:23:13.91#ibcon#about to read 6, iclass 38, count 0 2006.173.19:23:13.91#ibcon#read 6, iclass 38, count 0 2006.173.19:23:13.91#ibcon#end of sib2, iclass 38, count 0 2006.173.19:23:13.91#ibcon#*after write, iclass 38, count 0 2006.173.19:23:13.91#ibcon#*before return 0, iclass 38, count 0 2006.173.19:23:13.91#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.19:23:13.91#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.19:23:13.91#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.19:23:13.91#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.19:23:13.91$vck44/vblo=1,629.99 2006.173.19:23:13.91#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.19:23:13.91#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.19:23:13.91#ibcon#ireg 17 cls_cnt 0 2006.173.19:23:13.91#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.19:23:13.91#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.19:23:13.91#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.19:23:13.91#ibcon#enter wrdev, iclass 40, count 0 2006.173.19:23:13.91#ibcon#first serial, iclass 40, count 0 2006.173.19:23:13.91#ibcon#enter sib2, iclass 40, count 0 2006.173.19:23:13.91#ibcon#flushed, iclass 40, count 0 2006.173.19:23:13.91#ibcon#about to write, iclass 40, count 0 2006.173.19:23:13.91#ibcon#wrote, iclass 40, count 0 2006.173.19:23:13.91#ibcon#about to read 3, iclass 40, count 0 2006.173.19:23:13.93#ibcon#read 3, iclass 40, count 0 2006.173.19:23:13.93#ibcon#about to read 4, iclass 40, count 0 2006.173.19:23:13.93#ibcon#read 4, iclass 40, count 0 2006.173.19:23:13.93#ibcon#about to read 5, iclass 40, count 0 2006.173.19:23:13.93#ibcon#read 5, iclass 40, count 0 2006.173.19:23:13.93#ibcon#about to read 6, iclass 40, count 0 2006.173.19:23:13.93#ibcon#read 6, iclass 40, count 0 2006.173.19:23:13.93#ibcon#end of sib2, iclass 40, count 0 2006.173.19:23:13.93#ibcon#*mode == 0, iclass 40, count 0 2006.173.19:23:13.93#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.19:23:13.93#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.19:23:13.93#ibcon#*before write, iclass 40, count 0 2006.173.19:23:13.93#ibcon#enter sib2, iclass 40, count 0 2006.173.19:23:13.93#ibcon#flushed, iclass 40, count 0 2006.173.19:23:13.93#ibcon#about to write, iclass 40, count 0 2006.173.19:23:13.93#ibcon#wrote, iclass 40, count 0 2006.173.19:23:13.93#ibcon#about to read 3, iclass 40, count 0 2006.173.19:23:13.97#ibcon#read 3, iclass 40, count 0 2006.173.19:23:13.97#ibcon#about to read 4, iclass 40, count 0 2006.173.19:23:13.97#ibcon#read 4, iclass 40, count 0 2006.173.19:23:13.97#ibcon#about to read 5, iclass 40, count 0 2006.173.19:23:13.97#ibcon#read 5, iclass 40, count 0 2006.173.19:23:13.97#ibcon#about to read 6, iclass 40, count 0 2006.173.19:23:13.97#ibcon#read 6, iclass 40, count 0 2006.173.19:23:13.97#ibcon#end of sib2, iclass 40, count 0 2006.173.19:23:13.97#ibcon#*after write, iclass 40, count 0 2006.173.19:23:13.97#ibcon#*before return 0, iclass 40, count 0 2006.173.19:23:13.97#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.19:23:13.97#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.19:23:13.97#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.19:23:13.97#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.19:23:13.97$vck44/vb=1,4 2006.173.19:23:13.97#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.19:23:13.97#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.19:23:13.97#ibcon#ireg 11 cls_cnt 2 2006.173.19:23:13.97#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.19:23:13.97#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.19:23:13.97#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.19:23:13.97#ibcon#enter wrdev, iclass 5, count 2 2006.173.19:23:13.97#ibcon#first serial, iclass 5, count 2 2006.173.19:23:13.97#ibcon#enter sib2, iclass 5, count 2 2006.173.19:23:13.97#ibcon#flushed, iclass 5, count 2 2006.173.19:23:13.97#ibcon#about to write, iclass 5, count 2 2006.173.19:23:13.97#ibcon#wrote, iclass 5, count 2 2006.173.19:23:13.97#ibcon#about to read 3, iclass 5, count 2 2006.173.19:23:13.99#ibcon#read 3, iclass 5, count 2 2006.173.19:23:13.99#ibcon#about to read 4, iclass 5, count 2 2006.173.19:23:13.99#ibcon#read 4, iclass 5, count 2 2006.173.19:23:13.99#ibcon#about to read 5, iclass 5, count 2 2006.173.19:23:13.99#ibcon#read 5, iclass 5, count 2 2006.173.19:23:13.99#ibcon#about to read 6, iclass 5, count 2 2006.173.19:23:13.99#ibcon#read 6, iclass 5, count 2 2006.173.19:23:13.99#ibcon#end of sib2, iclass 5, count 2 2006.173.19:23:13.99#ibcon#*mode == 0, iclass 5, count 2 2006.173.19:23:13.99#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.19:23:13.99#ibcon#[27=AT01-04\r\n] 2006.173.19:23:13.99#ibcon#*before write, iclass 5, count 2 2006.173.19:23:13.99#ibcon#enter sib2, iclass 5, count 2 2006.173.19:23:13.99#ibcon#flushed, iclass 5, count 2 2006.173.19:23:13.99#ibcon#about to write, iclass 5, count 2 2006.173.19:23:13.99#ibcon#wrote, iclass 5, count 2 2006.173.19:23:13.99#ibcon#about to read 3, iclass 5, count 2 2006.173.19:23:14.01#abcon#<5=/05 0.7 1.3 19.481001002.4\r\n> 2006.173.19:23:14.02#ibcon#read 3, iclass 5, count 2 2006.173.19:23:14.02#ibcon#about to read 4, iclass 5, count 2 2006.173.19:23:14.02#ibcon#read 4, iclass 5, count 2 2006.173.19:23:14.02#ibcon#about to read 5, iclass 5, count 2 2006.173.19:23:14.02#ibcon#read 5, iclass 5, count 2 2006.173.19:23:14.02#ibcon#about to read 6, iclass 5, count 2 2006.173.19:23:14.02#ibcon#read 6, iclass 5, count 2 2006.173.19:23:14.02#ibcon#end of sib2, iclass 5, count 2 2006.173.19:23:14.02#ibcon#*after write, iclass 5, count 2 2006.173.19:23:14.02#ibcon#*before return 0, iclass 5, count 2 2006.173.19:23:14.02#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.19:23:14.02#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.19:23:14.02#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.19:23:14.02#ibcon#ireg 7 cls_cnt 0 2006.173.19:23:14.02#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.19:23:14.03#abcon#{5=INTERFACE CLEAR} 2006.173.19:23:14.09#abcon#[5=S1D000X0/0*\r\n] 2006.173.19:23:14.14#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.19:23:14.14#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.19:23:14.14#ibcon#enter wrdev, iclass 5, count 0 2006.173.19:23:14.14#ibcon#first serial, iclass 5, count 0 2006.173.19:23:14.14#ibcon#enter sib2, iclass 5, count 0 2006.173.19:23:14.14#ibcon#flushed, iclass 5, count 0 2006.173.19:23:14.14#ibcon#about to write, iclass 5, count 0 2006.173.19:23:14.14#ibcon#wrote, iclass 5, count 0 2006.173.19:23:14.14#ibcon#about to read 3, iclass 5, count 0 2006.173.19:23:14.16#ibcon#read 3, iclass 5, count 0 2006.173.19:23:14.16#ibcon#about to read 4, iclass 5, count 0 2006.173.19:23:14.16#ibcon#read 4, iclass 5, count 0 2006.173.19:23:14.16#ibcon#about to read 5, iclass 5, count 0 2006.173.19:23:14.16#ibcon#read 5, iclass 5, count 0 2006.173.19:23:14.16#ibcon#about to read 6, iclass 5, count 0 2006.173.19:23:14.16#ibcon#read 6, iclass 5, count 0 2006.173.19:23:14.16#ibcon#end of sib2, iclass 5, count 0 2006.173.19:23:14.16#ibcon#*mode == 0, iclass 5, count 0 2006.173.19:23:14.16#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.19:23:14.16#ibcon#[27=USB\r\n] 2006.173.19:23:14.16#ibcon#*before write, iclass 5, count 0 2006.173.19:23:14.16#ibcon#enter sib2, iclass 5, count 0 2006.173.19:23:14.16#ibcon#flushed, iclass 5, count 0 2006.173.19:23:14.16#ibcon#about to write, iclass 5, count 0 2006.173.19:23:14.16#ibcon#wrote, iclass 5, count 0 2006.173.19:23:14.16#ibcon#about to read 3, iclass 5, count 0 2006.173.19:23:14.19#ibcon#read 3, iclass 5, count 0 2006.173.19:23:14.19#ibcon#about to read 4, iclass 5, count 0 2006.173.19:23:14.19#ibcon#read 4, iclass 5, count 0 2006.173.19:23:14.19#ibcon#about to read 5, iclass 5, count 0 2006.173.19:23:14.19#ibcon#read 5, iclass 5, count 0 2006.173.19:23:14.19#ibcon#about to read 6, iclass 5, count 0 2006.173.19:23:14.19#ibcon#read 6, iclass 5, count 0 2006.173.19:23:14.19#ibcon#end of sib2, iclass 5, count 0 2006.173.19:23:14.19#ibcon#*after write, iclass 5, count 0 2006.173.19:23:14.19#ibcon#*before return 0, iclass 5, count 0 2006.173.19:23:14.19#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.19:23:14.19#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.19:23:14.19#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.19:23:14.19#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.19:23:14.19$vck44/vblo=2,634.99 2006.173.19:23:14.19#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.19:23:14.19#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.19:23:14.19#ibcon#ireg 17 cls_cnt 0 2006.173.19:23:14.19#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.19:23:14.19#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.19:23:14.19#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.19:23:14.19#ibcon#enter wrdev, iclass 12, count 0 2006.173.19:23:14.19#ibcon#first serial, iclass 12, count 0 2006.173.19:23:14.19#ibcon#enter sib2, iclass 12, count 0 2006.173.19:23:14.19#ibcon#flushed, iclass 12, count 0 2006.173.19:23:14.19#ibcon#about to write, iclass 12, count 0 2006.173.19:23:14.19#ibcon#wrote, iclass 12, count 0 2006.173.19:23:14.19#ibcon#about to read 3, iclass 12, count 0 2006.173.19:23:14.21#ibcon#read 3, iclass 12, count 0 2006.173.19:23:14.21#ibcon#about to read 4, iclass 12, count 0 2006.173.19:23:14.21#ibcon#read 4, iclass 12, count 0 2006.173.19:23:14.21#ibcon#about to read 5, iclass 12, count 0 2006.173.19:23:14.21#ibcon#read 5, iclass 12, count 0 2006.173.19:23:14.21#ibcon#about to read 6, iclass 12, count 0 2006.173.19:23:14.21#ibcon#read 6, iclass 12, count 0 2006.173.19:23:14.21#ibcon#end of sib2, iclass 12, count 0 2006.173.19:23:14.21#ibcon#*mode == 0, iclass 12, count 0 2006.173.19:23:14.21#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.19:23:14.21#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.19:23:14.21#ibcon#*before write, iclass 12, count 0 2006.173.19:23:14.21#ibcon#enter sib2, iclass 12, count 0 2006.173.19:23:14.21#ibcon#flushed, iclass 12, count 0 2006.173.19:23:14.21#ibcon#about to write, iclass 12, count 0 2006.173.19:23:14.21#ibcon#wrote, iclass 12, count 0 2006.173.19:23:14.21#ibcon#about to read 3, iclass 12, count 0 2006.173.19:23:14.25#ibcon#read 3, iclass 12, count 0 2006.173.19:23:14.25#ibcon#about to read 4, iclass 12, count 0 2006.173.19:23:14.25#ibcon#read 4, iclass 12, count 0 2006.173.19:23:14.25#ibcon#about to read 5, iclass 12, count 0 2006.173.19:23:14.25#ibcon#read 5, iclass 12, count 0 2006.173.19:23:14.25#ibcon#about to read 6, iclass 12, count 0 2006.173.19:23:14.25#ibcon#read 6, iclass 12, count 0 2006.173.19:23:14.25#ibcon#end of sib2, iclass 12, count 0 2006.173.19:23:14.25#ibcon#*after write, iclass 12, count 0 2006.173.19:23:14.25#ibcon#*before return 0, iclass 12, count 0 2006.173.19:23:14.25#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.19:23:14.25#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.19:23:14.25#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.19:23:14.25#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.19:23:14.25$vck44/vb=2,4 2006.173.19:23:14.25#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.19:23:14.25#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.19:23:14.25#ibcon#ireg 11 cls_cnt 2 2006.173.19:23:14.25#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.19:23:14.31#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.19:23:14.31#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.19:23:14.31#ibcon#enter wrdev, iclass 14, count 2 2006.173.19:23:14.31#ibcon#first serial, iclass 14, count 2 2006.173.19:23:14.31#ibcon#enter sib2, iclass 14, count 2 2006.173.19:23:14.31#ibcon#flushed, iclass 14, count 2 2006.173.19:23:14.31#ibcon#about to write, iclass 14, count 2 2006.173.19:23:14.31#ibcon#wrote, iclass 14, count 2 2006.173.19:23:14.31#ibcon#about to read 3, iclass 14, count 2 2006.173.19:23:14.33#ibcon#read 3, iclass 14, count 2 2006.173.19:23:14.33#ibcon#about to read 4, iclass 14, count 2 2006.173.19:23:14.33#ibcon#read 4, iclass 14, count 2 2006.173.19:23:14.33#ibcon#about to read 5, iclass 14, count 2 2006.173.19:23:14.33#ibcon#read 5, iclass 14, count 2 2006.173.19:23:14.33#ibcon#about to read 6, iclass 14, count 2 2006.173.19:23:14.33#ibcon#read 6, iclass 14, count 2 2006.173.19:23:14.33#ibcon#end of sib2, iclass 14, count 2 2006.173.19:23:14.33#ibcon#*mode == 0, iclass 14, count 2 2006.173.19:23:14.33#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.19:23:14.33#ibcon#[27=AT02-04\r\n] 2006.173.19:23:14.33#ibcon#*before write, iclass 14, count 2 2006.173.19:23:14.33#ibcon#enter sib2, iclass 14, count 2 2006.173.19:23:14.33#ibcon#flushed, iclass 14, count 2 2006.173.19:23:14.33#ibcon#about to write, iclass 14, count 2 2006.173.19:23:14.33#ibcon#wrote, iclass 14, count 2 2006.173.19:23:14.33#ibcon#about to read 3, iclass 14, count 2 2006.173.19:23:14.36#ibcon#read 3, iclass 14, count 2 2006.173.19:23:14.36#ibcon#about to read 4, iclass 14, count 2 2006.173.19:23:14.36#ibcon#read 4, iclass 14, count 2 2006.173.19:23:14.36#ibcon#about to read 5, iclass 14, count 2 2006.173.19:23:14.36#ibcon#read 5, iclass 14, count 2 2006.173.19:23:14.36#ibcon#about to read 6, iclass 14, count 2 2006.173.19:23:14.36#ibcon#read 6, iclass 14, count 2 2006.173.19:23:14.36#ibcon#end of sib2, iclass 14, count 2 2006.173.19:23:14.36#ibcon#*after write, iclass 14, count 2 2006.173.19:23:14.36#ibcon#*before return 0, iclass 14, count 2 2006.173.19:23:14.36#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.19:23:14.36#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.19:23:14.36#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.19:23:14.36#ibcon#ireg 7 cls_cnt 0 2006.173.19:23:14.36#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.19:23:14.48#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.19:23:14.48#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.19:23:14.48#ibcon#enter wrdev, iclass 14, count 0 2006.173.19:23:14.48#ibcon#first serial, iclass 14, count 0 2006.173.19:23:14.48#ibcon#enter sib2, iclass 14, count 0 2006.173.19:23:14.48#ibcon#flushed, iclass 14, count 0 2006.173.19:23:14.48#ibcon#about to write, iclass 14, count 0 2006.173.19:23:14.48#ibcon#wrote, iclass 14, count 0 2006.173.19:23:14.48#ibcon#about to read 3, iclass 14, count 0 2006.173.19:23:14.50#ibcon#read 3, iclass 14, count 0 2006.173.19:23:14.50#ibcon#about to read 4, iclass 14, count 0 2006.173.19:23:14.50#ibcon#read 4, iclass 14, count 0 2006.173.19:23:14.50#ibcon#about to read 5, iclass 14, count 0 2006.173.19:23:14.50#ibcon#read 5, iclass 14, count 0 2006.173.19:23:14.50#ibcon#about to read 6, iclass 14, count 0 2006.173.19:23:14.50#ibcon#read 6, iclass 14, count 0 2006.173.19:23:14.50#ibcon#end of sib2, iclass 14, count 0 2006.173.19:23:14.50#ibcon#*mode == 0, iclass 14, count 0 2006.173.19:23:14.50#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.19:23:14.50#ibcon#[27=USB\r\n] 2006.173.19:23:14.50#ibcon#*before write, iclass 14, count 0 2006.173.19:23:14.50#ibcon#enter sib2, iclass 14, count 0 2006.173.19:23:14.50#ibcon#flushed, iclass 14, count 0 2006.173.19:23:14.50#ibcon#about to write, iclass 14, count 0 2006.173.19:23:14.50#ibcon#wrote, iclass 14, count 0 2006.173.19:23:14.50#ibcon#about to read 3, iclass 14, count 0 2006.173.19:23:14.53#ibcon#read 3, iclass 14, count 0 2006.173.19:23:14.53#ibcon#about to read 4, iclass 14, count 0 2006.173.19:23:14.53#ibcon#read 4, iclass 14, count 0 2006.173.19:23:14.53#ibcon#about to read 5, iclass 14, count 0 2006.173.19:23:14.53#ibcon#read 5, iclass 14, count 0 2006.173.19:23:14.53#ibcon#about to read 6, iclass 14, count 0 2006.173.19:23:14.53#ibcon#read 6, iclass 14, count 0 2006.173.19:23:14.53#ibcon#end of sib2, iclass 14, count 0 2006.173.19:23:14.53#ibcon#*after write, iclass 14, count 0 2006.173.19:23:14.53#ibcon#*before return 0, iclass 14, count 0 2006.173.19:23:14.53#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.19:23:14.53#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.19:23:14.53#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.19:23:14.53#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.19:23:14.53$vck44/vblo=3,649.99 2006.173.19:23:14.53#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.19:23:14.53#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.19:23:14.53#ibcon#ireg 17 cls_cnt 0 2006.173.19:23:14.53#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.19:23:14.53#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.19:23:14.53#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.19:23:14.53#ibcon#enter wrdev, iclass 16, count 0 2006.173.19:23:14.53#ibcon#first serial, iclass 16, count 0 2006.173.19:23:14.53#ibcon#enter sib2, iclass 16, count 0 2006.173.19:23:14.53#ibcon#flushed, iclass 16, count 0 2006.173.19:23:14.53#ibcon#about to write, iclass 16, count 0 2006.173.19:23:14.53#ibcon#wrote, iclass 16, count 0 2006.173.19:23:14.53#ibcon#about to read 3, iclass 16, count 0 2006.173.19:23:14.55#ibcon#read 3, iclass 16, count 0 2006.173.19:23:14.55#ibcon#about to read 4, iclass 16, count 0 2006.173.19:23:14.55#ibcon#read 4, iclass 16, count 0 2006.173.19:23:14.55#ibcon#about to read 5, iclass 16, count 0 2006.173.19:23:14.55#ibcon#read 5, iclass 16, count 0 2006.173.19:23:14.55#ibcon#about to read 6, iclass 16, count 0 2006.173.19:23:14.55#ibcon#read 6, iclass 16, count 0 2006.173.19:23:14.55#ibcon#end of sib2, iclass 16, count 0 2006.173.19:23:14.55#ibcon#*mode == 0, iclass 16, count 0 2006.173.19:23:14.55#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.19:23:14.55#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.19:23:14.55#ibcon#*before write, iclass 16, count 0 2006.173.19:23:14.55#ibcon#enter sib2, iclass 16, count 0 2006.173.19:23:14.55#ibcon#flushed, iclass 16, count 0 2006.173.19:23:14.55#ibcon#about to write, iclass 16, count 0 2006.173.19:23:14.55#ibcon#wrote, iclass 16, count 0 2006.173.19:23:14.55#ibcon#about to read 3, iclass 16, count 0 2006.173.19:23:14.59#ibcon#read 3, iclass 16, count 0 2006.173.19:23:14.59#ibcon#about to read 4, iclass 16, count 0 2006.173.19:23:14.59#ibcon#read 4, iclass 16, count 0 2006.173.19:23:14.59#ibcon#about to read 5, iclass 16, count 0 2006.173.19:23:14.59#ibcon#read 5, iclass 16, count 0 2006.173.19:23:14.59#ibcon#about to read 6, iclass 16, count 0 2006.173.19:23:14.59#ibcon#read 6, iclass 16, count 0 2006.173.19:23:14.59#ibcon#end of sib2, iclass 16, count 0 2006.173.19:23:14.59#ibcon#*after write, iclass 16, count 0 2006.173.19:23:14.59#ibcon#*before return 0, iclass 16, count 0 2006.173.19:23:14.59#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.19:23:14.59#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.19:23:14.59#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.19:23:14.59#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.19:23:14.59$vck44/vb=3,4 2006.173.19:23:14.59#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.19:23:14.59#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.19:23:14.59#ibcon#ireg 11 cls_cnt 2 2006.173.19:23:14.59#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.19:23:14.65#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.19:23:14.65#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.19:23:14.65#ibcon#enter wrdev, iclass 18, count 2 2006.173.19:23:14.65#ibcon#first serial, iclass 18, count 2 2006.173.19:23:14.65#ibcon#enter sib2, iclass 18, count 2 2006.173.19:23:14.65#ibcon#flushed, iclass 18, count 2 2006.173.19:23:14.65#ibcon#about to write, iclass 18, count 2 2006.173.19:23:14.65#ibcon#wrote, iclass 18, count 2 2006.173.19:23:14.65#ibcon#about to read 3, iclass 18, count 2 2006.173.19:23:14.67#ibcon#read 3, iclass 18, count 2 2006.173.19:23:14.67#ibcon#about to read 4, iclass 18, count 2 2006.173.19:23:14.67#ibcon#read 4, iclass 18, count 2 2006.173.19:23:14.67#ibcon#about to read 5, iclass 18, count 2 2006.173.19:23:14.67#ibcon#read 5, iclass 18, count 2 2006.173.19:23:14.67#ibcon#about to read 6, iclass 18, count 2 2006.173.19:23:14.67#ibcon#read 6, iclass 18, count 2 2006.173.19:23:14.67#ibcon#end of sib2, iclass 18, count 2 2006.173.19:23:14.67#ibcon#*mode == 0, iclass 18, count 2 2006.173.19:23:14.67#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.19:23:14.67#ibcon#[27=AT03-04\r\n] 2006.173.19:23:14.67#ibcon#*before write, iclass 18, count 2 2006.173.19:23:14.67#ibcon#enter sib2, iclass 18, count 2 2006.173.19:23:14.67#ibcon#flushed, iclass 18, count 2 2006.173.19:23:14.67#ibcon#about to write, iclass 18, count 2 2006.173.19:23:14.67#ibcon#wrote, iclass 18, count 2 2006.173.19:23:14.67#ibcon#about to read 3, iclass 18, count 2 2006.173.19:23:14.70#ibcon#read 3, iclass 18, count 2 2006.173.19:23:14.70#ibcon#about to read 4, iclass 18, count 2 2006.173.19:23:14.70#ibcon#read 4, iclass 18, count 2 2006.173.19:23:14.70#ibcon#about to read 5, iclass 18, count 2 2006.173.19:23:14.70#ibcon#read 5, iclass 18, count 2 2006.173.19:23:14.70#ibcon#about to read 6, iclass 18, count 2 2006.173.19:23:14.70#ibcon#read 6, iclass 18, count 2 2006.173.19:23:14.70#ibcon#end of sib2, iclass 18, count 2 2006.173.19:23:14.70#ibcon#*after write, iclass 18, count 2 2006.173.19:23:14.70#ibcon#*before return 0, iclass 18, count 2 2006.173.19:23:14.70#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.19:23:14.70#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.19:23:14.70#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.19:23:14.70#ibcon#ireg 7 cls_cnt 0 2006.173.19:23:14.70#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.19:23:14.82#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.19:23:14.82#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.19:23:14.82#ibcon#enter wrdev, iclass 18, count 0 2006.173.19:23:14.82#ibcon#first serial, iclass 18, count 0 2006.173.19:23:14.82#ibcon#enter sib2, iclass 18, count 0 2006.173.19:23:14.82#ibcon#flushed, iclass 18, count 0 2006.173.19:23:14.82#ibcon#about to write, iclass 18, count 0 2006.173.19:23:14.82#ibcon#wrote, iclass 18, count 0 2006.173.19:23:14.82#ibcon#about to read 3, iclass 18, count 0 2006.173.19:23:14.84#ibcon#read 3, iclass 18, count 0 2006.173.19:23:14.84#ibcon#about to read 4, iclass 18, count 0 2006.173.19:23:14.84#ibcon#read 4, iclass 18, count 0 2006.173.19:23:14.84#ibcon#about to read 5, iclass 18, count 0 2006.173.19:23:14.84#ibcon#read 5, iclass 18, count 0 2006.173.19:23:14.84#ibcon#about to read 6, iclass 18, count 0 2006.173.19:23:14.84#ibcon#read 6, iclass 18, count 0 2006.173.19:23:14.84#ibcon#end of sib2, iclass 18, count 0 2006.173.19:23:14.84#ibcon#*mode == 0, iclass 18, count 0 2006.173.19:23:14.84#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.19:23:14.84#ibcon#[27=USB\r\n] 2006.173.19:23:14.84#ibcon#*before write, iclass 18, count 0 2006.173.19:23:14.84#ibcon#enter sib2, iclass 18, count 0 2006.173.19:23:14.84#ibcon#flushed, iclass 18, count 0 2006.173.19:23:14.84#ibcon#about to write, iclass 18, count 0 2006.173.19:23:14.84#ibcon#wrote, iclass 18, count 0 2006.173.19:23:14.84#ibcon#about to read 3, iclass 18, count 0 2006.173.19:23:14.87#ibcon#read 3, iclass 18, count 0 2006.173.19:23:14.87#ibcon#about to read 4, iclass 18, count 0 2006.173.19:23:14.87#ibcon#read 4, iclass 18, count 0 2006.173.19:23:14.87#ibcon#about to read 5, iclass 18, count 0 2006.173.19:23:14.87#ibcon#read 5, iclass 18, count 0 2006.173.19:23:14.87#ibcon#about to read 6, iclass 18, count 0 2006.173.19:23:14.87#ibcon#read 6, iclass 18, count 0 2006.173.19:23:14.87#ibcon#end of sib2, iclass 18, count 0 2006.173.19:23:14.87#ibcon#*after write, iclass 18, count 0 2006.173.19:23:14.87#ibcon#*before return 0, iclass 18, count 0 2006.173.19:23:14.87#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.19:23:14.87#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.19:23:14.87#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.19:23:14.87#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.19:23:14.87$vck44/vblo=4,679.99 2006.173.19:23:14.87#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.19:23:14.87#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.19:23:14.87#ibcon#ireg 17 cls_cnt 0 2006.173.19:23:14.87#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.19:23:14.87#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.19:23:14.87#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.19:23:14.87#ibcon#enter wrdev, iclass 20, count 0 2006.173.19:23:14.87#ibcon#first serial, iclass 20, count 0 2006.173.19:23:14.87#ibcon#enter sib2, iclass 20, count 0 2006.173.19:23:14.87#ibcon#flushed, iclass 20, count 0 2006.173.19:23:14.87#ibcon#about to write, iclass 20, count 0 2006.173.19:23:14.87#ibcon#wrote, iclass 20, count 0 2006.173.19:23:14.87#ibcon#about to read 3, iclass 20, count 0 2006.173.19:23:14.89#ibcon#read 3, iclass 20, count 0 2006.173.19:23:14.89#ibcon#about to read 4, iclass 20, count 0 2006.173.19:23:14.89#ibcon#read 4, iclass 20, count 0 2006.173.19:23:14.89#ibcon#about to read 5, iclass 20, count 0 2006.173.19:23:14.89#ibcon#read 5, iclass 20, count 0 2006.173.19:23:14.89#ibcon#about to read 6, iclass 20, count 0 2006.173.19:23:14.89#ibcon#read 6, iclass 20, count 0 2006.173.19:23:14.89#ibcon#end of sib2, iclass 20, count 0 2006.173.19:23:14.89#ibcon#*mode == 0, iclass 20, count 0 2006.173.19:23:14.89#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.19:23:14.89#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.19:23:14.89#ibcon#*before write, iclass 20, count 0 2006.173.19:23:14.89#ibcon#enter sib2, iclass 20, count 0 2006.173.19:23:14.89#ibcon#flushed, iclass 20, count 0 2006.173.19:23:14.89#ibcon#about to write, iclass 20, count 0 2006.173.19:23:14.89#ibcon#wrote, iclass 20, count 0 2006.173.19:23:14.89#ibcon#about to read 3, iclass 20, count 0 2006.173.19:23:14.93#ibcon#read 3, iclass 20, count 0 2006.173.19:23:14.93#ibcon#about to read 4, iclass 20, count 0 2006.173.19:23:14.93#ibcon#read 4, iclass 20, count 0 2006.173.19:23:14.93#ibcon#about to read 5, iclass 20, count 0 2006.173.19:23:14.93#ibcon#read 5, iclass 20, count 0 2006.173.19:23:14.93#ibcon#about to read 6, iclass 20, count 0 2006.173.19:23:14.93#ibcon#read 6, iclass 20, count 0 2006.173.19:23:14.93#ibcon#end of sib2, iclass 20, count 0 2006.173.19:23:14.93#ibcon#*after write, iclass 20, count 0 2006.173.19:23:14.93#ibcon#*before return 0, iclass 20, count 0 2006.173.19:23:14.93#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.19:23:14.93#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.19:23:14.93#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.19:23:14.93#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.19:23:14.93$vck44/vb=4,4 2006.173.19:23:14.93#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.19:23:14.93#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.19:23:14.93#ibcon#ireg 11 cls_cnt 2 2006.173.19:23:14.93#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.19:23:14.99#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.19:23:14.99#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.19:23:14.99#ibcon#enter wrdev, iclass 22, count 2 2006.173.19:23:14.99#ibcon#first serial, iclass 22, count 2 2006.173.19:23:14.99#ibcon#enter sib2, iclass 22, count 2 2006.173.19:23:14.99#ibcon#flushed, iclass 22, count 2 2006.173.19:23:14.99#ibcon#about to write, iclass 22, count 2 2006.173.19:23:14.99#ibcon#wrote, iclass 22, count 2 2006.173.19:23:14.99#ibcon#about to read 3, iclass 22, count 2 2006.173.19:23:15.01#ibcon#read 3, iclass 22, count 2 2006.173.19:23:15.01#ibcon#about to read 4, iclass 22, count 2 2006.173.19:23:15.01#ibcon#read 4, iclass 22, count 2 2006.173.19:23:15.01#ibcon#about to read 5, iclass 22, count 2 2006.173.19:23:15.01#ibcon#read 5, iclass 22, count 2 2006.173.19:23:15.01#ibcon#about to read 6, iclass 22, count 2 2006.173.19:23:15.01#ibcon#read 6, iclass 22, count 2 2006.173.19:23:15.01#ibcon#end of sib2, iclass 22, count 2 2006.173.19:23:15.01#ibcon#*mode == 0, iclass 22, count 2 2006.173.19:23:15.01#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.19:23:15.01#ibcon#[27=AT04-04\r\n] 2006.173.19:23:15.01#ibcon#*before write, iclass 22, count 2 2006.173.19:23:15.01#ibcon#enter sib2, iclass 22, count 2 2006.173.19:23:15.01#ibcon#flushed, iclass 22, count 2 2006.173.19:23:15.01#ibcon#about to write, iclass 22, count 2 2006.173.19:23:15.01#ibcon#wrote, iclass 22, count 2 2006.173.19:23:15.01#ibcon#about to read 3, iclass 22, count 2 2006.173.19:23:15.04#ibcon#read 3, iclass 22, count 2 2006.173.19:23:15.04#ibcon#about to read 4, iclass 22, count 2 2006.173.19:23:15.04#ibcon#read 4, iclass 22, count 2 2006.173.19:23:15.04#ibcon#about to read 5, iclass 22, count 2 2006.173.19:23:15.04#ibcon#read 5, iclass 22, count 2 2006.173.19:23:15.04#ibcon#about to read 6, iclass 22, count 2 2006.173.19:23:15.04#ibcon#read 6, iclass 22, count 2 2006.173.19:23:15.04#ibcon#end of sib2, iclass 22, count 2 2006.173.19:23:15.04#ibcon#*after write, iclass 22, count 2 2006.173.19:23:15.04#ibcon#*before return 0, iclass 22, count 2 2006.173.19:23:15.04#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.19:23:15.04#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.19:23:15.04#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.19:23:15.04#ibcon#ireg 7 cls_cnt 0 2006.173.19:23:15.04#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.19:23:15.16#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.19:23:15.16#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.19:23:15.16#ibcon#enter wrdev, iclass 22, count 0 2006.173.19:23:15.16#ibcon#first serial, iclass 22, count 0 2006.173.19:23:15.16#ibcon#enter sib2, iclass 22, count 0 2006.173.19:23:15.16#ibcon#flushed, iclass 22, count 0 2006.173.19:23:15.16#ibcon#about to write, iclass 22, count 0 2006.173.19:23:15.16#ibcon#wrote, iclass 22, count 0 2006.173.19:23:15.16#ibcon#about to read 3, iclass 22, count 0 2006.173.19:23:15.18#ibcon#read 3, iclass 22, count 0 2006.173.19:23:15.18#ibcon#about to read 4, iclass 22, count 0 2006.173.19:23:15.18#ibcon#read 4, iclass 22, count 0 2006.173.19:23:15.18#ibcon#about to read 5, iclass 22, count 0 2006.173.19:23:15.18#ibcon#read 5, iclass 22, count 0 2006.173.19:23:15.18#ibcon#about to read 6, iclass 22, count 0 2006.173.19:23:15.18#ibcon#read 6, iclass 22, count 0 2006.173.19:23:15.18#ibcon#end of sib2, iclass 22, count 0 2006.173.19:23:15.18#ibcon#*mode == 0, iclass 22, count 0 2006.173.19:23:15.18#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.19:23:15.18#ibcon#[27=USB\r\n] 2006.173.19:23:15.18#ibcon#*before write, iclass 22, count 0 2006.173.19:23:15.18#ibcon#enter sib2, iclass 22, count 0 2006.173.19:23:15.18#ibcon#flushed, iclass 22, count 0 2006.173.19:23:15.18#ibcon#about to write, iclass 22, count 0 2006.173.19:23:15.18#ibcon#wrote, iclass 22, count 0 2006.173.19:23:15.18#ibcon#about to read 3, iclass 22, count 0 2006.173.19:23:15.21#ibcon#read 3, iclass 22, count 0 2006.173.19:23:15.21#ibcon#about to read 4, iclass 22, count 0 2006.173.19:23:15.21#ibcon#read 4, iclass 22, count 0 2006.173.19:23:15.21#ibcon#about to read 5, iclass 22, count 0 2006.173.19:23:15.21#ibcon#read 5, iclass 22, count 0 2006.173.19:23:15.21#ibcon#about to read 6, iclass 22, count 0 2006.173.19:23:15.21#ibcon#read 6, iclass 22, count 0 2006.173.19:23:15.21#ibcon#end of sib2, iclass 22, count 0 2006.173.19:23:15.21#ibcon#*after write, iclass 22, count 0 2006.173.19:23:15.21#ibcon#*before return 0, iclass 22, count 0 2006.173.19:23:15.21#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.19:23:15.21#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.19:23:15.21#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.19:23:15.21#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.19:23:15.21$vck44/vblo=5,709.99 2006.173.19:23:15.21#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.19:23:15.21#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.19:23:15.21#ibcon#ireg 17 cls_cnt 0 2006.173.19:23:15.21#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.19:23:15.21#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.19:23:15.21#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.19:23:15.21#ibcon#enter wrdev, iclass 24, count 0 2006.173.19:23:15.21#ibcon#first serial, iclass 24, count 0 2006.173.19:23:15.21#ibcon#enter sib2, iclass 24, count 0 2006.173.19:23:15.21#ibcon#flushed, iclass 24, count 0 2006.173.19:23:15.21#ibcon#about to write, iclass 24, count 0 2006.173.19:23:15.21#ibcon#wrote, iclass 24, count 0 2006.173.19:23:15.21#ibcon#about to read 3, iclass 24, count 0 2006.173.19:23:15.23#ibcon#read 3, iclass 24, count 0 2006.173.19:23:15.23#ibcon#about to read 4, iclass 24, count 0 2006.173.19:23:15.23#ibcon#read 4, iclass 24, count 0 2006.173.19:23:15.23#ibcon#about to read 5, iclass 24, count 0 2006.173.19:23:15.23#ibcon#read 5, iclass 24, count 0 2006.173.19:23:15.23#ibcon#about to read 6, iclass 24, count 0 2006.173.19:23:15.23#ibcon#read 6, iclass 24, count 0 2006.173.19:23:15.23#ibcon#end of sib2, iclass 24, count 0 2006.173.19:23:15.23#ibcon#*mode == 0, iclass 24, count 0 2006.173.19:23:15.23#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.19:23:15.23#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.19:23:15.23#ibcon#*before write, iclass 24, count 0 2006.173.19:23:15.23#ibcon#enter sib2, iclass 24, count 0 2006.173.19:23:15.23#ibcon#flushed, iclass 24, count 0 2006.173.19:23:15.23#ibcon#about to write, iclass 24, count 0 2006.173.19:23:15.23#ibcon#wrote, iclass 24, count 0 2006.173.19:23:15.23#ibcon#about to read 3, iclass 24, count 0 2006.173.19:23:15.27#ibcon#read 3, iclass 24, count 0 2006.173.19:23:15.27#ibcon#about to read 4, iclass 24, count 0 2006.173.19:23:15.27#ibcon#read 4, iclass 24, count 0 2006.173.19:23:15.27#ibcon#about to read 5, iclass 24, count 0 2006.173.19:23:15.27#ibcon#read 5, iclass 24, count 0 2006.173.19:23:15.27#ibcon#about to read 6, iclass 24, count 0 2006.173.19:23:15.27#ibcon#read 6, iclass 24, count 0 2006.173.19:23:15.27#ibcon#end of sib2, iclass 24, count 0 2006.173.19:23:15.27#ibcon#*after write, iclass 24, count 0 2006.173.19:23:15.27#ibcon#*before return 0, iclass 24, count 0 2006.173.19:23:15.27#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.19:23:15.27#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.19:23:15.27#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.19:23:15.27#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.19:23:15.27$vck44/vb=5,4 2006.173.19:23:15.27#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.19:23:15.27#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.19:23:15.27#ibcon#ireg 11 cls_cnt 2 2006.173.19:23:15.27#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.19:23:15.33#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.19:23:15.33#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.19:23:15.33#ibcon#enter wrdev, iclass 26, count 2 2006.173.19:23:15.33#ibcon#first serial, iclass 26, count 2 2006.173.19:23:15.33#ibcon#enter sib2, iclass 26, count 2 2006.173.19:23:15.33#ibcon#flushed, iclass 26, count 2 2006.173.19:23:15.33#ibcon#about to write, iclass 26, count 2 2006.173.19:23:15.33#ibcon#wrote, iclass 26, count 2 2006.173.19:23:15.33#ibcon#about to read 3, iclass 26, count 2 2006.173.19:23:15.35#ibcon#read 3, iclass 26, count 2 2006.173.19:23:15.35#ibcon#about to read 4, iclass 26, count 2 2006.173.19:23:15.35#ibcon#read 4, iclass 26, count 2 2006.173.19:23:15.35#ibcon#about to read 5, iclass 26, count 2 2006.173.19:23:15.35#ibcon#read 5, iclass 26, count 2 2006.173.19:23:15.35#ibcon#about to read 6, iclass 26, count 2 2006.173.19:23:15.35#ibcon#read 6, iclass 26, count 2 2006.173.19:23:15.35#ibcon#end of sib2, iclass 26, count 2 2006.173.19:23:15.35#ibcon#*mode == 0, iclass 26, count 2 2006.173.19:23:15.35#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.19:23:15.35#ibcon#[27=AT05-04\r\n] 2006.173.19:23:15.35#ibcon#*before write, iclass 26, count 2 2006.173.19:23:15.35#ibcon#enter sib2, iclass 26, count 2 2006.173.19:23:15.35#ibcon#flushed, iclass 26, count 2 2006.173.19:23:15.35#ibcon#about to write, iclass 26, count 2 2006.173.19:23:15.35#ibcon#wrote, iclass 26, count 2 2006.173.19:23:15.35#ibcon#about to read 3, iclass 26, count 2 2006.173.19:23:15.38#ibcon#read 3, iclass 26, count 2 2006.173.19:23:15.38#ibcon#about to read 4, iclass 26, count 2 2006.173.19:23:15.38#ibcon#read 4, iclass 26, count 2 2006.173.19:23:15.38#ibcon#about to read 5, iclass 26, count 2 2006.173.19:23:15.38#ibcon#read 5, iclass 26, count 2 2006.173.19:23:15.38#ibcon#about to read 6, iclass 26, count 2 2006.173.19:23:15.38#ibcon#read 6, iclass 26, count 2 2006.173.19:23:15.38#ibcon#end of sib2, iclass 26, count 2 2006.173.19:23:15.38#ibcon#*after write, iclass 26, count 2 2006.173.19:23:15.38#ibcon#*before return 0, iclass 26, count 2 2006.173.19:23:15.38#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.19:23:15.38#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.19:23:15.38#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.19:23:15.38#ibcon#ireg 7 cls_cnt 0 2006.173.19:23:15.38#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.19:23:15.50#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.19:23:15.50#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.19:23:15.50#ibcon#enter wrdev, iclass 26, count 0 2006.173.19:23:15.50#ibcon#first serial, iclass 26, count 0 2006.173.19:23:15.50#ibcon#enter sib2, iclass 26, count 0 2006.173.19:23:15.50#ibcon#flushed, iclass 26, count 0 2006.173.19:23:15.50#ibcon#about to write, iclass 26, count 0 2006.173.19:23:15.50#ibcon#wrote, iclass 26, count 0 2006.173.19:23:15.50#ibcon#about to read 3, iclass 26, count 0 2006.173.19:23:15.52#ibcon#read 3, iclass 26, count 0 2006.173.19:23:15.52#ibcon#about to read 4, iclass 26, count 0 2006.173.19:23:15.52#ibcon#read 4, iclass 26, count 0 2006.173.19:23:15.52#ibcon#about to read 5, iclass 26, count 0 2006.173.19:23:15.52#ibcon#read 5, iclass 26, count 0 2006.173.19:23:15.52#ibcon#about to read 6, iclass 26, count 0 2006.173.19:23:15.52#ibcon#read 6, iclass 26, count 0 2006.173.19:23:15.52#ibcon#end of sib2, iclass 26, count 0 2006.173.19:23:15.52#ibcon#*mode == 0, iclass 26, count 0 2006.173.19:23:15.52#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.19:23:15.52#ibcon#[27=USB\r\n] 2006.173.19:23:15.52#ibcon#*before write, iclass 26, count 0 2006.173.19:23:15.52#ibcon#enter sib2, iclass 26, count 0 2006.173.19:23:15.52#ibcon#flushed, iclass 26, count 0 2006.173.19:23:15.52#ibcon#about to write, iclass 26, count 0 2006.173.19:23:15.52#ibcon#wrote, iclass 26, count 0 2006.173.19:23:15.52#ibcon#about to read 3, iclass 26, count 0 2006.173.19:23:15.55#ibcon#read 3, iclass 26, count 0 2006.173.19:23:15.55#ibcon#about to read 4, iclass 26, count 0 2006.173.19:23:15.55#ibcon#read 4, iclass 26, count 0 2006.173.19:23:15.55#ibcon#about to read 5, iclass 26, count 0 2006.173.19:23:15.55#ibcon#read 5, iclass 26, count 0 2006.173.19:23:15.55#ibcon#about to read 6, iclass 26, count 0 2006.173.19:23:15.55#ibcon#read 6, iclass 26, count 0 2006.173.19:23:15.55#ibcon#end of sib2, iclass 26, count 0 2006.173.19:23:15.55#ibcon#*after write, iclass 26, count 0 2006.173.19:23:15.55#ibcon#*before return 0, iclass 26, count 0 2006.173.19:23:15.55#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.19:23:15.55#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.19:23:15.55#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.19:23:15.55#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.19:23:15.55$vck44/vblo=6,719.99 2006.173.19:23:15.55#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.19:23:15.55#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.19:23:15.55#ibcon#ireg 17 cls_cnt 0 2006.173.19:23:15.55#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.19:23:15.55#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.19:23:15.55#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.19:23:15.55#ibcon#enter wrdev, iclass 28, count 0 2006.173.19:23:15.55#ibcon#first serial, iclass 28, count 0 2006.173.19:23:15.55#ibcon#enter sib2, iclass 28, count 0 2006.173.19:23:15.55#ibcon#flushed, iclass 28, count 0 2006.173.19:23:15.55#ibcon#about to write, iclass 28, count 0 2006.173.19:23:15.55#ibcon#wrote, iclass 28, count 0 2006.173.19:23:15.55#ibcon#about to read 3, iclass 28, count 0 2006.173.19:23:15.57#ibcon#read 3, iclass 28, count 0 2006.173.19:23:15.57#ibcon#about to read 4, iclass 28, count 0 2006.173.19:23:15.57#ibcon#read 4, iclass 28, count 0 2006.173.19:23:15.57#ibcon#about to read 5, iclass 28, count 0 2006.173.19:23:15.57#ibcon#read 5, iclass 28, count 0 2006.173.19:23:15.57#ibcon#about to read 6, iclass 28, count 0 2006.173.19:23:15.57#ibcon#read 6, iclass 28, count 0 2006.173.19:23:15.57#ibcon#end of sib2, iclass 28, count 0 2006.173.19:23:15.57#ibcon#*mode == 0, iclass 28, count 0 2006.173.19:23:15.57#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.19:23:15.57#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.19:23:15.57#ibcon#*before write, iclass 28, count 0 2006.173.19:23:15.57#ibcon#enter sib2, iclass 28, count 0 2006.173.19:23:15.57#ibcon#flushed, iclass 28, count 0 2006.173.19:23:15.57#ibcon#about to write, iclass 28, count 0 2006.173.19:23:15.57#ibcon#wrote, iclass 28, count 0 2006.173.19:23:15.57#ibcon#about to read 3, iclass 28, count 0 2006.173.19:23:15.61#ibcon#read 3, iclass 28, count 0 2006.173.19:23:15.61#ibcon#about to read 4, iclass 28, count 0 2006.173.19:23:15.61#ibcon#read 4, iclass 28, count 0 2006.173.19:23:15.61#ibcon#about to read 5, iclass 28, count 0 2006.173.19:23:15.61#ibcon#read 5, iclass 28, count 0 2006.173.19:23:15.61#ibcon#about to read 6, iclass 28, count 0 2006.173.19:23:15.61#ibcon#read 6, iclass 28, count 0 2006.173.19:23:15.61#ibcon#end of sib2, iclass 28, count 0 2006.173.19:23:15.61#ibcon#*after write, iclass 28, count 0 2006.173.19:23:15.61#ibcon#*before return 0, iclass 28, count 0 2006.173.19:23:15.61#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.19:23:15.61#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.19:23:15.61#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.19:23:15.61#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.19:23:15.61$vck44/vb=6,4 2006.173.19:23:15.61#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.19:23:15.61#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.19:23:15.61#ibcon#ireg 11 cls_cnt 2 2006.173.19:23:15.61#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.19:23:15.67#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.19:23:15.67#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.19:23:15.67#ibcon#enter wrdev, iclass 30, count 2 2006.173.19:23:15.67#ibcon#first serial, iclass 30, count 2 2006.173.19:23:15.67#ibcon#enter sib2, iclass 30, count 2 2006.173.19:23:15.67#ibcon#flushed, iclass 30, count 2 2006.173.19:23:15.67#ibcon#about to write, iclass 30, count 2 2006.173.19:23:15.67#ibcon#wrote, iclass 30, count 2 2006.173.19:23:15.67#ibcon#about to read 3, iclass 30, count 2 2006.173.19:23:15.69#ibcon#read 3, iclass 30, count 2 2006.173.19:23:15.69#ibcon#about to read 4, iclass 30, count 2 2006.173.19:23:15.69#ibcon#read 4, iclass 30, count 2 2006.173.19:23:15.69#ibcon#about to read 5, iclass 30, count 2 2006.173.19:23:15.69#ibcon#read 5, iclass 30, count 2 2006.173.19:23:15.69#ibcon#about to read 6, iclass 30, count 2 2006.173.19:23:15.69#ibcon#read 6, iclass 30, count 2 2006.173.19:23:15.69#ibcon#end of sib2, iclass 30, count 2 2006.173.19:23:15.69#ibcon#*mode == 0, iclass 30, count 2 2006.173.19:23:15.69#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.19:23:15.69#ibcon#[27=AT06-04\r\n] 2006.173.19:23:15.69#ibcon#*before write, iclass 30, count 2 2006.173.19:23:15.69#ibcon#enter sib2, iclass 30, count 2 2006.173.19:23:15.69#ibcon#flushed, iclass 30, count 2 2006.173.19:23:15.69#ibcon#about to write, iclass 30, count 2 2006.173.19:23:15.69#ibcon#wrote, iclass 30, count 2 2006.173.19:23:15.69#ibcon#about to read 3, iclass 30, count 2 2006.173.19:23:15.72#ibcon#read 3, iclass 30, count 2 2006.173.19:23:15.72#ibcon#about to read 4, iclass 30, count 2 2006.173.19:23:15.72#ibcon#read 4, iclass 30, count 2 2006.173.19:23:15.72#ibcon#about to read 5, iclass 30, count 2 2006.173.19:23:15.72#ibcon#read 5, iclass 30, count 2 2006.173.19:23:15.72#ibcon#about to read 6, iclass 30, count 2 2006.173.19:23:15.72#ibcon#read 6, iclass 30, count 2 2006.173.19:23:15.72#ibcon#end of sib2, iclass 30, count 2 2006.173.19:23:15.72#ibcon#*after write, iclass 30, count 2 2006.173.19:23:15.72#ibcon#*before return 0, iclass 30, count 2 2006.173.19:23:15.72#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.19:23:15.72#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.19:23:15.72#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.19:23:15.72#ibcon#ireg 7 cls_cnt 0 2006.173.19:23:15.72#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.19:23:15.84#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.19:23:15.84#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.19:23:15.84#ibcon#enter wrdev, iclass 30, count 0 2006.173.19:23:15.84#ibcon#first serial, iclass 30, count 0 2006.173.19:23:15.84#ibcon#enter sib2, iclass 30, count 0 2006.173.19:23:15.84#ibcon#flushed, iclass 30, count 0 2006.173.19:23:15.84#ibcon#about to write, iclass 30, count 0 2006.173.19:23:15.84#ibcon#wrote, iclass 30, count 0 2006.173.19:23:15.84#ibcon#about to read 3, iclass 30, count 0 2006.173.19:23:15.86#ibcon#read 3, iclass 30, count 0 2006.173.19:23:15.86#ibcon#about to read 4, iclass 30, count 0 2006.173.19:23:15.86#ibcon#read 4, iclass 30, count 0 2006.173.19:23:15.86#ibcon#about to read 5, iclass 30, count 0 2006.173.19:23:15.86#ibcon#read 5, iclass 30, count 0 2006.173.19:23:15.86#ibcon#about to read 6, iclass 30, count 0 2006.173.19:23:15.86#ibcon#read 6, iclass 30, count 0 2006.173.19:23:15.86#ibcon#end of sib2, iclass 30, count 0 2006.173.19:23:15.86#ibcon#*mode == 0, iclass 30, count 0 2006.173.19:23:15.86#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.19:23:15.86#ibcon#[27=USB\r\n] 2006.173.19:23:15.86#ibcon#*before write, iclass 30, count 0 2006.173.19:23:15.86#ibcon#enter sib2, iclass 30, count 0 2006.173.19:23:15.86#ibcon#flushed, iclass 30, count 0 2006.173.19:23:15.86#ibcon#about to write, iclass 30, count 0 2006.173.19:23:15.86#ibcon#wrote, iclass 30, count 0 2006.173.19:23:15.86#ibcon#about to read 3, iclass 30, count 0 2006.173.19:23:15.89#ibcon#read 3, iclass 30, count 0 2006.173.19:23:15.89#ibcon#about to read 4, iclass 30, count 0 2006.173.19:23:15.89#ibcon#read 4, iclass 30, count 0 2006.173.19:23:15.89#ibcon#about to read 5, iclass 30, count 0 2006.173.19:23:15.89#ibcon#read 5, iclass 30, count 0 2006.173.19:23:15.89#ibcon#about to read 6, iclass 30, count 0 2006.173.19:23:15.89#ibcon#read 6, iclass 30, count 0 2006.173.19:23:15.89#ibcon#end of sib2, iclass 30, count 0 2006.173.19:23:15.89#ibcon#*after write, iclass 30, count 0 2006.173.19:23:15.89#ibcon#*before return 0, iclass 30, count 0 2006.173.19:23:15.89#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.19:23:15.89#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.19:23:15.89#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.19:23:15.89#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.19:23:15.89$vck44/vblo=7,734.99 2006.173.19:23:15.89#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.19:23:15.89#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.19:23:15.89#ibcon#ireg 17 cls_cnt 0 2006.173.19:23:15.89#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.19:23:15.89#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.19:23:15.89#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.19:23:15.89#ibcon#enter wrdev, iclass 32, count 0 2006.173.19:23:15.89#ibcon#first serial, iclass 32, count 0 2006.173.19:23:15.89#ibcon#enter sib2, iclass 32, count 0 2006.173.19:23:15.89#ibcon#flushed, iclass 32, count 0 2006.173.19:23:15.89#ibcon#about to write, iclass 32, count 0 2006.173.19:23:15.89#ibcon#wrote, iclass 32, count 0 2006.173.19:23:15.89#ibcon#about to read 3, iclass 32, count 0 2006.173.19:23:15.91#ibcon#read 3, iclass 32, count 0 2006.173.19:23:15.91#ibcon#about to read 4, iclass 32, count 0 2006.173.19:23:15.91#ibcon#read 4, iclass 32, count 0 2006.173.19:23:15.91#ibcon#about to read 5, iclass 32, count 0 2006.173.19:23:15.91#ibcon#read 5, iclass 32, count 0 2006.173.19:23:15.91#ibcon#about to read 6, iclass 32, count 0 2006.173.19:23:15.91#ibcon#read 6, iclass 32, count 0 2006.173.19:23:15.91#ibcon#end of sib2, iclass 32, count 0 2006.173.19:23:15.91#ibcon#*mode == 0, iclass 32, count 0 2006.173.19:23:15.91#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.19:23:15.91#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.19:23:15.91#ibcon#*before write, iclass 32, count 0 2006.173.19:23:15.91#ibcon#enter sib2, iclass 32, count 0 2006.173.19:23:15.91#ibcon#flushed, iclass 32, count 0 2006.173.19:23:15.91#ibcon#about to write, iclass 32, count 0 2006.173.19:23:15.91#ibcon#wrote, iclass 32, count 0 2006.173.19:23:15.91#ibcon#about to read 3, iclass 32, count 0 2006.173.19:23:15.95#ibcon#read 3, iclass 32, count 0 2006.173.19:23:15.95#ibcon#about to read 4, iclass 32, count 0 2006.173.19:23:15.95#ibcon#read 4, iclass 32, count 0 2006.173.19:23:15.95#ibcon#about to read 5, iclass 32, count 0 2006.173.19:23:15.95#ibcon#read 5, iclass 32, count 0 2006.173.19:23:15.95#ibcon#about to read 6, iclass 32, count 0 2006.173.19:23:15.95#ibcon#read 6, iclass 32, count 0 2006.173.19:23:15.95#ibcon#end of sib2, iclass 32, count 0 2006.173.19:23:15.95#ibcon#*after write, iclass 32, count 0 2006.173.19:23:15.95#ibcon#*before return 0, iclass 32, count 0 2006.173.19:23:15.95#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.19:23:15.95#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.19:23:15.95#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.19:23:15.95#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.19:23:15.95$vck44/vb=7,4 2006.173.19:23:15.95#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.19:23:15.95#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.19:23:15.95#ibcon#ireg 11 cls_cnt 2 2006.173.19:23:15.95#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.19:23:16.01#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.19:23:16.01#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.19:23:16.01#ibcon#enter wrdev, iclass 34, count 2 2006.173.19:23:16.01#ibcon#first serial, iclass 34, count 2 2006.173.19:23:16.01#ibcon#enter sib2, iclass 34, count 2 2006.173.19:23:16.01#ibcon#flushed, iclass 34, count 2 2006.173.19:23:16.01#ibcon#about to write, iclass 34, count 2 2006.173.19:23:16.01#ibcon#wrote, iclass 34, count 2 2006.173.19:23:16.01#ibcon#about to read 3, iclass 34, count 2 2006.173.19:23:16.03#ibcon#read 3, iclass 34, count 2 2006.173.19:23:16.03#ibcon#about to read 4, iclass 34, count 2 2006.173.19:23:16.03#ibcon#read 4, iclass 34, count 2 2006.173.19:23:16.03#ibcon#about to read 5, iclass 34, count 2 2006.173.19:23:16.03#ibcon#read 5, iclass 34, count 2 2006.173.19:23:16.03#ibcon#about to read 6, iclass 34, count 2 2006.173.19:23:16.03#ibcon#read 6, iclass 34, count 2 2006.173.19:23:16.03#ibcon#end of sib2, iclass 34, count 2 2006.173.19:23:16.03#ibcon#*mode == 0, iclass 34, count 2 2006.173.19:23:16.03#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.19:23:16.03#ibcon#[27=AT07-04\r\n] 2006.173.19:23:16.03#ibcon#*before write, iclass 34, count 2 2006.173.19:23:16.03#ibcon#enter sib2, iclass 34, count 2 2006.173.19:23:16.03#ibcon#flushed, iclass 34, count 2 2006.173.19:23:16.03#ibcon#about to write, iclass 34, count 2 2006.173.19:23:16.03#ibcon#wrote, iclass 34, count 2 2006.173.19:23:16.03#ibcon#about to read 3, iclass 34, count 2 2006.173.19:23:16.06#ibcon#read 3, iclass 34, count 2 2006.173.19:23:16.06#ibcon#about to read 4, iclass 34, count 2 2006.173.19:23:16.06#ibcon#read 4, iclass 34, count 2 2006.173.19:23:16.06#ibcon#about to read 5, iclass 34, count 2 2006.173.19:23:16.06#ibcon#read 5, iclass 34, count 2 2006.173.19:23:16.06#ibcon#about to read 6, iclass 34, count 2 2006.173.19:23:16.06#ibcon#read 6, iclass 34, count 2 2006.173.19:23:16.06#ibcon#end of sib2, iclass 34, count 2 2006.173.19:23:16.06#ibcon#*after write, iclass 34, count 2 2006.173.19:23:16.06#ibcon#*before return 0, iclass 34, count 2 2006.173.19:23:16.06#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.19:23:16.06#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.19:23:16.06#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.19:23:16.06#ibcon#ireg 7 cls_cnt 0 2006.173.19:23:16.06#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.19:23:16.18#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.19:23:16.18#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.19:23:16.18#ibcon#enter wrdev, iclass 34, count 0 2006.173.19:23:16.18#ibcon#first serial, iclass 34, count 0 2006.173.19:23:16.18#ibcon#enter sib2, iclass 34, count 0 2006.173.19:23:16.18#ibcon#flushed, iclass 34, count 0 2006.173.19:23:16.18#ibcon#about to write, iclass 34, count 0 2006.173.19:23:16.18#ibcon#wrote, iclass 34, count 0 2006.173.19:23:16.18#ibcon#about to read 3, iclass 34, count 0 2006.173.19:23:16.20#ibcon#read 3, iclass 34, count 0 2006.173.19:23:16.20#ibcon#about to read 4, iclass 34, count 0 2006.173.19:23:16.20#ibcon#read 4, iclass 34, count 0 2006.173.19:23:16.20#ibcon#about to read 5, iclass 34, count 0 2006.173.19:23:16.20#ibcon#read 5, iclass 34, count 0 2006.173.19:23:16.20#ibcon#about to read 6, iclass 34, count 0 2006.173.19:23:16.20#ibcon#read 6, iclass 34, count 0 2006.173.19:23:16.20#ibcon#end of sib2, iclass 34, count 0 2006.173.19:23:16.20#ibcon#*mode == 0, iclass 34, count 0 2006.173.19:23:16.20#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.19:23:16.20#ibcon#[27=USB\r\n] 2006.173.19:23:16.20#ibcon#*before write, iclass 34, count 0 2006.173.19:23:16.20#ibcon#enter sib2, iclass 34, count 0 2006.173.19:23:16.20#ibcon#flushed, iclass 34, count 0 2006.173.19:23:16.20#ibcon#about to write, iclass 34, count 0 2006.173.19:23:16.20#ibcon#wrote, iclass 34, count 0 2006.173.19:23:16.20#ibcon#about to read 3, iclass 34, count 0 2006.173.19:23:16.23#ibcon#read 3, iclass 34, count 0 2006.173.19:23:16.23#ibcon#about to read 4, iclass 34, count 0 2006.173.19:23:16.23#ibcon#read 4, iclass 34, count 0 2006.173.19:23:16.23#ibcon#about to read 5, iclass 34, count 0 2006.173.19:23:16.23#ibcon#read 5, iclass 34, count 0 2006.173.19:23:16.23#ibcon#about to read 6, iclass 34, count 0 2006.173.19:23:16.23#ibcon#read 6, iclass 34, count 0 2006.173.19:23:16.23#ibcon#end of sib2, iclass 34, count 0 2006.173.19:23:16.23#ibcon#*after write, iclass 34, count 0 2006.173.19:23:16.23#ibcon#*before return 0, iclass 34, count 0 2006.173.19:23:16.23#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.19:23:16.23#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.19:23:16.23#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.19:23:16.23#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.19:23:16.23$vck44/vblo=8,744.99 2006.173.19:23:16.23#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.19:23:16.23#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.19:23:16.23#ibcon#ireg 17 cls_cnt 0 2006.173.19:23:16.23#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.19:23:16.23#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.19:23:16.23#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.19:23:16.23#ibcon#enter wrdev, iclass 36, count 0 2006.173.19:23:16.23#ibcon#first serial, iclass 36, count 0 2006.173.19:23:16.23#ibcon#enter sib2, iclass 36, count 0 2006.173.19:23:16.23#ibcon#flushed, iclass 36, count 0 2006.173.19:23:16.23#ibcon#about to write, iclass 36, count 0 2006.173.19:23:16.23#ibcon#wrote, iclass 36, count 0 2006.173.19:23:16.23#ibcon#about to read 3, iclass 36, count 0 2006.173.19:23:16.25#ibcon#read 3, iclass 36, count 0 2006.173.19:23:16.25#ibcon#about to read 4, iclass 36, count 0 2006.173.19:23:16.25#ibcon#read 4, iclass 36, count 0 2006.173.19:23:16.25#ibcon#about to read 5, iclass 36, count 0 2006.173.19:23:16.25#ibcon#read 5, iclass 36, count 0 2006.173.19:23:16.25#ibcon#about to read 6, iclass 36, count 0 2006.173.19:23:16.25#ibcon#read 6, iclass 36, count 0 2006.173.19:23:16.25#ibcon#end of sib2, iclass 36, count 0 2006.173.19:23:16.25#ibcon#*mode == 0, iclass 36, count 0 2006.173.19:23:16.25#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.19:23:16.25#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.19:23:16.25#ibcon#*before write, iclass 36, count 0 2006.173.19:23:16.25#ibcon#enter sib2, iclass 36, count 0 2006.173.19:23:16.25#ibcon#flushed, iclass 36, count 0 2006.173.19:23:16.25#ibcon#about to write, iclass 36, count 0 2006.173.19:23:16.25#ibcon#wrote, iclass 36, count 0 2006.173.19:23:16.25#ibcon#about to read 3, iclass 36, count 0 2006.173.19:23:16.29#ibcon#read 3, iclass 36, count 0 2006.173.19:23:16.29#ibcon#about to read 4, iclass 36, count 0 2006.173.19:23:16.29#ibcon#read 4, iclass 36, count 0 2006.173.19:23:16.29#ibcon#about to read 5, iclass 36, count 0 2006.173.19:23:16.29#ibcon#read 5, iclass 36, count 0 2006.173.19:23:16.29#ibcon#about to read 6, iclass 36, count 0 2006.173.19:23:16.29#ibcon#read 6, iclass 36, count 0 2006.173.19:23:16.29#ibcon#end of sib2, iclass 36, count 0 2006.173.19:23:16.29#ibcon#*after write, iclass 36, count 0 2006.173.19:23:16.29#ibcon#*before return 0, iclass 36, count 0 2006.173.19:23:16.29#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.19:23:16.29#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.19:23:16.29#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.19:23:16.29#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.19:23:16.29$vck44/vb=8,4 2006.173.19:23:16.29#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.19:23:16.29#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.19:23:16.29#ibcon#ireg 11 cls_cnt 2 2006.173.19:23:16.29#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.19:23:16.35#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.19:23:16.35#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.19:23:16.35#ibcon#enter wrdev, iclass 38, count 2 2006.173.19:23:16.35#ibcon#first serial, iclass 38, count 2 2006.173.19:23:16.35#ibcon#enter sib2, iclass 38, count 2 2006.173.19:23:16.35#ibcon#flushed, iclass 38, count 2 2006.173.19:23:16.35#ibcon#about to write, iclass 38, count 2 2006.173.19:23:16.35#ibcon#wrote, iclass 38, count 2 2006.173.19:23:16.35#ibcon#about to read 3, iclass 38, count 2 2006.173.19:23:16.37#ibcon#read 3, iclass 38, count 2 2006.173.19:23:16.37#ibcon#about to read 4, iclass 38, count 2 2006.173.19:23:16.37#ibcon#read 4, iclass 38, count 2 2006.173.19:23:16.37#ibcon#about to read 5, iclass 38, count 2 2006.173.19:23:16.37#ibcon#read 5, iclass 38, count 2 2006.173.19:23:16.37#ibcon#about to read 6, iclass 38, count 2 2006.173.19:23:16.37#ibcon#read 6, iclass 38, count 2 2006.173.19:23:16.37#ibcon#end of sib2, iclass 38, count 2 2006.173.19:23:16.37#ibcon#*mode == 0, iclass 38, count 2 2006.173.19:23:16.37#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.19:23:16.37#ibcon#[27=AT08-04\r\n] 2006.173.19:23:16.37#ibcon#*before write, iclass 38, count 2 2006.173.19:23:16.37#ibcon#enter sib2, iclass 38, count 2 2006.173.19:23:16.37#ibcon#flushed, iclass 38, count 2 2006.173.19:23:16.37#ibcon#about to write, iclass 38, count 2 2006.173.19:23:16.37#ibcon#wrote, iclass 38, count 2 2006.173.19:23:16.37#ibcon#about to read 3, iclass 38, count 2 2006.173.19:23:16.40#ibcon#read 3, iclass 38, count 2 2006.173.19:23:16.40#ibcon#about to read 4, iclass 38, count 2 2006.173.19:23:16.40#ibcon#read 4, iclass 38, count 2 2006.173.19:23:16.40#ibcon#about to read 5, iclass 38, count 2 2006.173.19:23:16.40#ibcon#read 5, iclass 38, count 2 2006.173.19:23:16.40#ibcon#about to read 6, iclass 38, count 2 2006.173.19:23:16.40#ibcon#read 6, iclass 38, count 2 2006.173.19:23:16.40#ibcon#end of sib2, iclass 38, count 2 2006.173.19:23:16.40#ibcon#*after write, iclass 38, count 2 2006.173.19:23:16.40#ibcon#*before return 0, iclass 38, count 2 2006.173.19:23:16.40#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.19:23:16.40#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.19:23:16.40#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.19:23:16.40#ibcon#ireg 7 cls_cnt 0 2006.173.19:23:16.40#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.19:23:16.52#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.19:23:16.52#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.19:23:16.52#ibcon#enter wrdev, iclass 38, count 0 2006.173.19:23:16.52#ibcon#first serial, iclass 38, count 0 2006.173.19:23:16.52#ibcon#enter sib2, iclass 38, count 0 2006.173.19:23:16.52#ibcon#flushed, iclass 38, count 0 2006.173.19:23:16.52#ibcon#about to write, iclass 38, count 0 2006.173.19:23:16.52#ibcon#wrote, iclass 38, count 0 2006.173.19:23:16.52#ibcon#about to read 3, iclass 38, count 0 2006.173.19:23:16.54#ibcon#read 3, iclass 38, count 0 2006.173.19:23:16.54#ibcon#about to read 4, iclass 38, count 0 2006.173.19:23:16.54#ibcon#read 4, iclass 38, count 0 2006.173.19:23:16.54#ibcon#about to read 5, iclass 38, count 0 2006.173.19:23:16.54#ibcon#read 5, iclass 38, count 0 2006.173.19:23:16.54#ibcon#about to read 6, iclass 38, count 0 2006.173.19:23:16.54#ibcon#read 6, iclass 38, count 0 2006.173.19:23:16.54#ibcon#end of sib2, iclass 38, count 0 2006.173.19:23:16.54#ibcon#*mode == 0, iclass 38, count 0 2006.173.19:23:16.54#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.19:23:16.54#ibcon#[27=USB\r\n] 2006.173.19:23:16.54#ibcon#*before write, iclass 38, count 0 2006.173.19:23:16.54#ibcon#enter sib2, iclass 38, count 0 2006.173.19:23:16.54#ibcon#flushed, iclass 38, count 0 2006.173.19:23:16.54#ibcon#about to write, iclass 38, count 0 2006.173.19:23:16.54#ibcon#wrote, iclass 38, count 0 2006.173.19:23:16.54#ibcon#about to read 3, iclass 38, count 0 2006.173.19:23:16.57#ibcon#read 3, iclass 38, count 0 2006.173.19:23:16.57#ibcon#about to read 4, iclass 38, count 0 2006.173.19:23:16.57#ibcon#read 4, iclass 38, count 0 2006.173.19:23:16.57#ibcon#about to read 5, iclass 38, count 0 2006.173.19:23:16.57#ibcon#read 5, iclass 38, count 0 2006.173.19:23:16.57#ibcon#about to read 6, iclass 38, count 0 2006.173.19:23:16.57#ibcon#read 6, iclass 38, count 0 2006.173.19:23:16.57#ibcon#end of sib2, iclass 38, count 0 2006.173.19:23:16.57#ibcon#*after write, iclass 38, count 0 2006.173.19:23:16.57#ibcon#*before return 0, iclass 38, count 0 2006.173.19:23:16.57#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.19:23:16.57#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.19:23:16.57#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.19:23:16.57#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.19:23:16.57$vck44/vabw=wide 2006.173.19:23:16.57#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.19:23:16.57#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.19:23:16.57#ibcon#ireg 8 cls_cnt 0 2006.173.19:23:16.57#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.19:23:16.57#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.19:23:16.57#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.19:23:16.57#ibcon#enter wrdev, iclass 40, count 0 2006.173.19:23:16.57#ibcon#first serial, iclass 40, count 0 2006.173.19:23:16.57#ibcon#enter sib2, iclass 40, count 0 2006.173.19:23:16.57#ibcon#flushed, iclass 40, count 0 2006.173.19:23:16.57#ibcon#about to write, iclass 40, count 0 2006.173.19:23:16.57#ibcon#wrote, iclass 40, count 0 2006.173.19:23:16.57#ibcon#about to read 3, iclass 40, count 0 2006.173.19:23:16.59#ibcon#read 3, iclass 40, count 0 2006.173.19:23:16.59#ibcon#about to read 4, iclass 40, count 0 2006.173.19:23:16.59#ibcon#read 4, iclass 40, count 0 2006.173.19:23:16.59#ibcon#about to read 5, iclass 40, count 0 2006.173.19:23:16.59#ibcon#read 5, iclass 40, count 0 2006.173.19:23:16.59#ibcon#about to read 6, iclass 40, count 0 2006.173.19:23:16.59#ibcon#read 6, iclass 40, count 0 2006.173.19:23:16.59#ibcon#end of sib2, iclass 40, count 0 2006.173.19:23:16.59#ibcon#*mode == 0, iclass 40, count 0 2006.173.19:23:16.59#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.19:23:16.59#ibcon#[25=BW32\r\n] 2006.173.19:23:16.59#ibcon#*before write, iclass 40, count 0 2006.173.19:23:16.59#ibcon#enter sib2, iclass 40, count 0 2006.173.19:23:16.59#ibcon#flushed, iclass 40, count 0 2006.173.19:23:16.59#ibcon#about to write, iclass 40, count 0 2006.173.19:23:16.59#ibcon#wrote, iclass 40, count 0 2006.173.19:23:16.59#ibcon#about to read 3, iclass 40, count 0 2006.173.19:23:16.62#ibcon#read 3, iclass 40, count 0 2006.173.19:23:16.62#ibcon#about to read 4, iclass 40, count 0 2006.173.19:23:16.62#ibcon#read 4, iclass 40, count 0 2006.173.19:23:16.62#ibcon#about to read 5, iclass 40, count 0 2006.173.19:23:16.62#ibcon#read 5, iclass 40, count 0 2006.173.19:23:16.62#ibcon#about to read 6, iclass 40, count 0 2006.173.19:23:16.62#ibcon#read 6, iclass 40, count 0 2006.173.19:23:16.62#ibcon#end of sib2, iclass 40, count 0 2006.173.19:23:16.62#ibcon#*after write, iclass 40, count 0 2006.173.19:23:16.62#ibcon#*before return 0, iclass 40, count 0 2006.173.19:23:16.62#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.19:23:16.62#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.19:23:16.62#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.19:23:16.62#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.19:23:16.62$vck44/vbbw=wide 2006.173.19:23:16.62#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.19:23:16.62#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.19:23:16.62#ibcon#ireg 8 cls_cnt 0 2006.173.19:23:16.62#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.19:23:16.69#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.19:23:16.69#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.19:23:16.69#ibcon#enter wrdev, iclass 4, count 0 2006.173.19:23:16.69#ibcon#first serial, iclass 4, count 0 2006.173.19:23:16.69#ibcon#enter sib2, iclass 4, count 0 2006.173.19:23:16.69#ibcon#flushed, iclass 4, count 0 2006.173.19:23:16.69#ibcon#about to write, iclass 4, count 0 2006.173.19:23:16.69#ibcon#wrote, iclass 4, count 0 2006.173.19:23:16.69#ibcon#about to read 3, iclass 4, count 0 2006.173.19:23:16.71#ibcon#read 3, iclass 4, count 0 2006.173.19:23:16.71#ibcon#about to read 4, iclass 4, count 0 2006.173.19:23:16.71#ibcon#read 4, iclass 4, count 0 2006.173.19:23:16.71#ibcon#about to read 5, iclass 4, count 0 2006.173.19:23:16.71#ibcon#read 5, iclass 4, count 0 2006.173.19:23:16.71#ibcon#about to read 6, iclass 4, count 0 2006.173.19:23:16.71#ibcon#read 6, iclass 4, count 0 2006.173.19:23:16.71#ibcon#end of sib2, iclass 4, count 0 2006.173.19:23:16.71#ibcon#*mode == 0, iclass 4, count 0 2006.173.19:23:16.71#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.19:23:16.71#ibcon#[27=BW32\r\n] 2006.173.19:23:16.71#ibcon#*before write, iclass 4, count 0 2006.173.19:23:16.71#ibcon#enter sib2, iclass 4, count 0 2006.173.19:23:16.71#ibcon#flushed, iclass 4, count 0 2006.173.19:23:16.71#ibcon#about to write, iclass 4, count 0 2006.173.19:23:16.71#ibcon#wrote, iclass 4, count 0 2006.173.19:23:16.71#ibcon#about to read 3, iclass 4, count 0 2006.173.19:23:16.74#ibcon#read 3, iclass 4, count 0 2006.173.19:23:16.74#ibcon#about to read 4, iclass 4, count 0 2006.173.19:23:16.74#ibcon#read 4, iclass 4, count 0 2006.173.19:23:16.74#ibcon#about to read 5, iclass 4, count 0 2006.173.19:23:16.74#ibcon#read 5, iclass 4, count 0 2006.173.19:23:16.74#ibcon#about to read 6, iclass 4, count 0 2006.173.19:23:16.74#ibcon#read 6, iclass 4, count 0 2006.173.19:23:16.74#ibcon#end of sib2, iclass 4, count 0 2006.173.19:23:16.74#ibcon#*after write, iclass 4, count 0 2006.173.19:23:16.74#ibcon#*before return 0, iclass 4, count 0 2006.173.19:23:16.74#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.19:23:16.74#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.19:23:16.74#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.19:23:16.74#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.19:23:16.74$setupk4/ifdk4 2006.173.19:23:16.74$ifdk4/lo= 2006.173.19:23:16.74$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.19:23:16.74$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.19:23:16.74$ifdk4/patch= 2006.173.19:23:16.74$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.19:23:16.74$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.19:23:16.74$setupk4/!*+20s 2006.173.19:23:24.18#abcon#<5=/05 0.7 1.3 19.481001002.5\r\n> 2006.173.19:23:24.20#abcon#{5=INTERFACE CLEAR} 2006.173.19:23:24.26#abcon#[5=S1D000X0/0*\r\n] 2006.173.19:23:26.14#trakl#Source acquired 2006.173.19:23:27.14#flagr#flagr/antenna,acquired 2006.173.19:23:31.25$setupk4/"tpicd 2006.173.19:23:31.25$setupk4/echo=off 2006.173.19:23:31.25$setupk4/xlog=off 2006.173.19:23:31.25:!2006.173.19:23:26 2006.173.19:23:31.25:preob 2006.173.19:23:32.14/onsource/TRACKING 2006.173.19:23:32.14:!2006.173.19:23:36 2006.173.19:23:36.00:"tape 2006.173.19:23:36.00:"st=record 2006.173.19:23:36.00:data_valid=on 2006.173.19:23:36.00:midob 2006.173.19:23:36.14/onsource/TRACKING 2006.173.19:23:36.14/wx/19.48,1002.5,100 2006.173.19:23:36.21/cable/+6.5173E-03 2006.173.19:23:37.30/va/01,07,usb,yes,42,45 2006.173.19:23:37.30/va/02,06,usb,yes,41,42 2006.173.19:23:37.30/va/03,05,usb,yes,52,55 2006.173.19:23:37.30/va/04,06,usb,yes,43,45 2006.173.19:23:37.30/va/05,04,usb,yes,34,34 2006.173.19:23:37.30/va/06,03,usb,yes,47,46 2006.173.19:23:37.30/va/07,04,usb,yes,38,39 2006.173.19:23:37.30/va/08,04,usb,yes,32,39 2006.173.19:23:37.53/valo/01,524.99,yes,locked 2006.173.19:23:37.53/valo/02,534.99,yes,locked 2006.173.19:23:37.53/valo/03,564.99,yes,locked 2006.173.19:23:37.53/valo/04,624.99,yes,locked 2006.173.19:23:37.53/valo/05,734.99,yes,locked 2006.173.19:23:37.53/valo/06,814.99,yes,locked 2006.173.19:23:37.53/valo/07,864.99,yes,locked 2006.173.19:23:37.53/valo/08,884.99,yes,locked 2006.173.19:23:38.62/vb/01,04,usb,yes,27,25 2006.173.19:23:38.62/vb/02,04,usb,yes,30,30 2006.173.19:23:38.62/vb/03,04,usb,yes,27,30 2006.173.19:23:38.62/vb/04,04,usb,yes,31,30 2006.173.19:23:38.62/vb/05,04,usb,yes,24,27 2006.173.19:23:38.62/vb/06,04,usb,yes,28,25 2006.173.19:23:38.62/vb/07,04,usb,yes,28,28 2006.173.19:23:38.62/vb/08,04,usb,yes,26,29 2006.173.19:23:38.86/vblo/01,629.99,yes,locked 2006.173.19:23:38.86/vblo/02,634.99,yes,locked 2006.173.19:23:38.86/vblo/03,649.99,yes,locked 2006.173.19:23:38.86/vblo/04,679.99,yes,locked 2006.173.19:23:38.86/vblo/05,709.99,yes,locked 2006.173.19:23:38.86/vblo/06,719.99,yes,locked 2006.173.19:23:38.86/vblo/07,734.99,yes,locked 2006.173.19:23:38.86/vblo/08,744.99,yes,locked 2006.173.19:23:39.01/vabw/8 2006.173.19:23:39.16/vbbw/8 2006.173.19:23:39.25/xfe/off,on,15.2 2006.173.19:23:39.64/ifatt/23,28,28,28 2006.173.19:23:40.07/fmout-gps/S +3.88E-07 2006.173.19:23:40.12:!2006.173.19:24:16 2006.173.19:24:16.01:data_valid=off 2006.173.19:24:16.02:"et 2006.173.19:24:16.02:!+3s 2006.173.19:24:19.03:"tape 2006.173.19:24:19.04:postob 2006.173.19:24:19.16/cable/+6.5163E-03 2006.173.19:24:19.17/wx/19.48,1002.5,100 2006.173.19:24:19.22/fmout-gps/S +3.87E-07 2006.173.19:24:19.23:scan_name=173-1926,jd0606,80 2006.173.19:24:19.23:source=2136+141,213901.31,142336.0,2000.0,ccw 2006.173.19:24:21.14#flagr#flagr/antenna,new-source 2006.173.19:24:21.15:checkk5 2006.173.19:24:21.56/chk_autoobs//k5ts1/ autoobs is running! 2006.173.19:24:21.95/chk_autoobs//k5ts2/ autoobs is running! 2006.173.19:24:22.37/chk_autoobs//k5ts3/ autoobs is running! 2006.173.19:24:22.77/chk_autoobs//k5ts4/ autoobs is running! 2006.173.19:24:23.15/chk_obsdata//k5ts1/T1731923??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.19:24:23.55/chk_obsdata//k5ts2/T1731923??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.19:24:23.94/chk_obsdata//k5ts3/T1731923??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.19:24:24.33/chk_obsdata//k5ts4/T1731923??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.19:24:25.06/k5log//k5ts1_log_newline 2006.173.19:24:25.77/k5log//k5ts2_log_newline 2006.173.19:24:26.49/k5log//k5ts3_log_newline 2006.173.19:24:27.19/k5log//k5ts4_log_newline 2006.173.19:24:27.22/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.19:24:27.22:setupk4=1 2006.173.19:24:27.22$setupk4/echo=on 2006.173.19:24:27.22$setupk4/pcalon 2006.173.19:24:27.22$pcalon/"no phase cal control is implemented here 2006.173.19:24:27.22$setupk4/"tpicd=stop 2006.173.19:24:27.22$setupk4/"rec=synch_on 2006.173.19:24:27.22$setupk4/"rec_mode=128 2006.173.19:24:27.22$setupk4/!* 2006.173.19:24:27.22$setupk4/recpk4 2006.173.19:24:27.22$recpk4/recpatch= 2006.173.19:24:27.22$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.19:24:27.22$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.19:24:27.22$setupk4/vck44 2006.173.19:24:27.22$vck44/valo=1,524.99 2006.173.19:24:27.22#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.19:24:27.22#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.19:24:27.22#ibcon#ireg 17 cls_cnt 0 2006.173.19:24:27.22#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.19:24:27.22#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.19:24:27.22#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.19:24:27.22#ibcon#enter wrdev, iclass 39, count 0 2006.173.19:24:27.22#ibcon#first serial, iclass 39, count 0 2006.173.19:24:27.22#ibcon#enter sib2, iclass 39, count 0 2006.173.19:24:27.22#ibcon#flushed, iclass 39, count 0 2006.173.19:24:27.22#ibcon#about to write, iclass 39, count 0 2006.173.19:24:27.22#ibcon#wrote, iclass 39, count 0 2006.173.19:24:27.22#ibcon#about to read 3, iclass 39, count 0 2006.173.19:24:27.24#ibcon#read 3, iclass 39, count 0 2006.173.19:24:27.24#ibcon#about to read 4, iclass 39, count 0 2006.173.19:24:27.24#ibcon#read 4, iclass 39, count 0 2006.173.19:24:27.24#ibcon#about to read 5, iclass 39, count 0 2006.173.19:24:27.24#ibcon#read 5, iclass 39, count 0 2006.173.19:24:27.24#ibcon#about to read 6, iclass 39, count 0 2006.173.19:24:27.24#ibcon#read 6, iclass 39, count 0 2006.173.19:24:27.24#ibcon#end of sib2, iclass 39, count 0 2006.173.19:24:27.24#ibcon#*mode == 0, iclass 39, count 0 2006.173.19:24:27.24#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.19:24:27.24#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.19:24:27.24#ibcon#*before write, iclass 39, count 0 2006.173.19:24:27.24#ibcon#enter sib2, iclass 39, count 0 2006.173.19:24:27.24#ibcon#flushed, iclass 39, count 0 2006.173.19:24:27.24#ibcon#about to write, iclass 39, count 0 2006.173.19:24:27.24#ibcon#wrote, iclass 39, count 0 2006.173.19:24:27.24#ibcon#about to read 3, iclass 39, count 0 2006.173.19:24:27.29#ibcon#read 3, iclass 39, count 0 2006.173.19:24:27.29#ibcon#about to read 4, iclass 39, count 0 2006.173.19:24:27.29#ibcon#read 4, iclass 39, count 0 2006.173.19:24:27.29#ibcon#about to read 5, iclass 39, count 0 2006.173.19:24:27.29#ibcon#read 5, iclass 39, count 0 2006.173.19:24:27.29#ibcon#about to read 6, iclass 39, count 0 2006.173.19:24:27.29#ibcon#read 6, iclass 39, count 0 2006.173.19:24:27.29#ibcon#end of sib2, iclass 39, count 0 2006.173.19:24:27.29#ibcon#*after write, iclass 39, count 0 2006.173.19:24:27.29#ibcon#*before return 0, iclass 39, count 0 2006.173.19:24:27.29#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.19:24:27.29#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.19:24:27.29#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.19:24:27.29#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.19:24:27.29$vck44/va=1,7 2006.173.19:24:27.29#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.19:24:27.29#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.19:24:27.29#ibcon#ireg 11 cls_cnt 2 2006.173.19:24:27.29#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.19:24:27.29#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.19:24:27.29#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.19:24:27.29#ibcon#enter wrdev, iclass 3, count 2 2006.173.19:24:27.29#ibcon#first serial, iclass 3, count 2 2006.173.19:24:27.29#ibcon#enter sib2, iclass 3, count 2 2006.173.19:24:27.29#ibcon#flushed, iclass 3, count 2 2006.173.19:24:27.29#ibcon#about to write, iclass 3, count 2 2006.173.19:24:27.29#ibcon#wrote, iclass 3, count 2 2006.173.19:24:27.29#ibcon#about to read 3, iclass 3, count 2 2006.173.19:24:27.31#ibcon#read 3, iclass 3, count 2 2006.173.19:24:27.31#ibcon#about to read 4, iclass 3, count 2 2006.173.19:24:27.31#ibcon#read 4, iclass 3, count 2 2006.173.19:24:27.31#ibcon#about to read 5, iclass 3, count 2 2006.173.19:24:27.31#ibcon#read 5, iclass 3, count 2 2006.173.19:24:27.31#ibcon#about to read 6, iclass 3, count 2 2006.173.19:24:27.31#ibcon#read 6, iclass 3, count 2 2006.173.19:24:27.31#ibcon#end of sib2, iclass 3, count 2 2006.173.19:24:27.31#ibcon#*mode == 0, iclass 3, count 2 2006.173.19:24:27.31#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.19:24:27.31#ibcon#[25=AT01-07\r\n] 2006.173.19:24:27.31#ibcon#*before write, iclass 3, count 2 2006.173.19:24:27.31#ibcon#enter sib2, iclass 3, count 2 2006.173.19:24:27.31#ibcon#flushed, iclass 3, count 2 2006.173.19:24:27.31#ibcon#about to write, iclass 3, count 2 2006.173.19:24:27.31#ibcon#wrote, iclass 3, count 2 2006.173.19:24:27.31#ibcon#about to read 3, iclass 3, count 2 2006.173.19:24:27.34#ibcon#read 3, iclass 3, count 2 2006.173.19:24:27.34#ibcon#about to read 4, iclass 3, count 2 2006.173.19:24:27.34#ibcon#read 4, iclass 3, count 2 2006.173.19:24:27.34#ibcon#about to read 5, iclass 3, count 2 2006.173.19:24:27.34#ibcon#read 5, iclass 3, count 2 2006.173.19:24:27.34#ibcon#about to read 6, iclass 3, count 2 2006.173.19:24:27.34#ibcon#read 6, iclass 3, count 2 2006.173.19:24:27.34#ibcon#end of sib2, iclass 3, count 2 2006.173.19:24:27.34#ibcon#*after write, iclass 3, count 2 2006.173.19:24:27.34#ibcon#*before return 0, iclass 3, count 2 2006.173.19:24:27.34#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.19:24:27.34#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.19:24:27.34#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.19:24:27.34#ibcon#ireg 7 cls_cnt 0 2006.173.19:24:27.34#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.19:24:27.46#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.19:24:27.46#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.19:24:27.46#ibcon#enter wrdev, iclass 3, count 0 2006.173.19:24:27.46#ibcon#first serial, iclass 3, count 0 2006.173.19:24:27.46#ibcon#enter sib2, iclass 3, count 0 2006.173.19:24:27.46#ibcon#flushed, iclass 3, count 0 2006.173.19:24:27.46#ibcon#about to write, iclass 3, count 0 2006.173.19:24:27.46#ibcon#wrote, iclass 3, count 0 2006.173.19:24:27.46#ibcon#about to read 3, iclass 3, count 0 2006.173.19:24:27.48#ibcon#read 3, iclass 3, count 0 2006.173.19:24:27.48#ibcon#about to read 4, iclass 3, count 0 2006.173.19:24:27.48#ibcon#read 4, iclass 3, count 0 2006.173.19:24:27.48#ibcon#about to read 5, iclass 3, count 0 2006.173.19:24:27.48#ibcon#read 5, iclass 3, count 0 2006.173.19:24:27.48#ibcon#about to read 6, iclass 3, count 0 2006.173.19:24:27.48#ibcon#read 6, iclass 3, count 0 2006.173.19:24:27.48#ibcon#end of sib2, iclass 3, count 0 2006.173.19:24:27.48#ibcon#*mode == 0, iclass 3, count 0 2006.173.19:24:27.48#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.19:24:27.48#ibcon#[25=USB\r\n] 2006.173.19:24:27.48#ibcon#*before write, iclass 3, count 0 2006.173.19:24:27.48#ibcon#enter sib2, iclass 3, count 0 2006.173.19:24:27.48#ibcon#flushed, iclass 3, count 0 2006.173.19:24:27.48#ibcon#about to write, iclass 3, count 0 2006.173.19:24:27.48#ibcon#wrote, iclass 3, count 0 2006.173.19:24:27.48#ibcon#about to read 3, iclass 3, count 0 2006.173.19:24:27.51#ibcon#read 3, iclass 3, count 0 2006.173.19:24:27.51#ibcon#about to read 4, iclass 3, count 0 2006.173.19:24:27.51#ibcon#read 4, iclass 3, count 0 2006.173.19:24:27.51#ibcon#about to read 5, iclass 3, count 0 2006.173.19:24:27.51#ibcon#read 5, iclass 3, count 0 2006.173.19:24:27.51#ibcon#about to read 6, iclass 3, count 0 2006.173.19:24:27.51#ibcon#read 6, iclass 3, count 0 2006.173.19:24:27.51#ibcon#end of sib2, iclass 3, count 0 2006.173.19:24:27.51#ibcon#*after write, iclass 3, count 0 2006.173.19:24:27.51#ibcon#*before return 0, iclass 3, count 0 2006.173.19:24:27.51#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.19:24:27.51#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.19:24:27.51#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.19:24:27.51#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.19:24:27.51$vck44/valo=2,534.99 2006.173.19:24:27.51#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.19:24:27.51#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.19:24:27.51#ibcon#ireg 17 cls_cnt 0 2006.173.19:24:27.51#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.19:24:27.51#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.19:24:27.51#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.19:24:27.51#ibcon#enter wrdev, iclass 5, count 0 2006.173.19:24:27.51#ibcon#first serial, iclass 5, count 0 2006.173.19:24:27.51#ibcon#enter sib2, iclass 5, count 0 2006.173.19:24:27.51#ibcon#flushed, iclass 5, count 0 2006.173.19:24:27.51#ibcon#about to write, iclass 5, count 0 2006.173.19:24:27.51#ibcon#wrote, iclass 5, count 0 2006.173.19:24:27.51#ibcon#about to read 3, iclass 5, count 0 2006.173.19:24:27.53#ibcon#read 3, iclass 5, count 0 2006.173.19:24:27.53#ibcon#about to read 4, iclass 5, count 0 2006.173.19:24:27.53#ibcon#read 4, iclass 5, count 0 2006.173.19:24:27.53#ibcon#about to read 5, iclass 5, count 0 2006.173.19:24:27.53#ibcon#read 5, iclass 5, count 0 2006.173.19:24:27.53#ibcon#about to read 6, iclass 5, count 0 2006.173.19:24:27.53#ibcon#read 6, iclass 5, count 0 2006.173.19:24:27.53#ibcon#end of sib2, iclass 5, count 0 2006.173.19:24:27.53#ibcon#*mode == 0, iclass 5, count 0 2006.173.19:24:27.53#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.19:24:27.53#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.19:24:27.53#ibcon#*before write, iclass 5, count 0 2006.173.19:24:27.53#ibcon#enter sib2, iclass 5, count 0 2006.173.19:24:27.53#ibcon#flushed, iclass 5, count 0 2006.173.19:24:27.53#ibcon#about to write, iclass 5, count 0 2006.173.19:24:27.53#ibcon#wrote, iclass 5, count 0 2006.173.19:24:27.53#ibcon#about to read 3, iclass 5, count 0 2006.173.19:24:27.57#ibcon#read 3, iclass 5, count 0 2006.173.19:24:27.57#ibcon#about to read 4, iclass 5, count 0 2006.173.19:24:27.57#ibcon#read 4, iclass 5, count 0 2006.173.19:24:27.57#ibcon#about to read 5, iclass 5, count 0 2006.173.19:24:27.57#ibcon#read 5, iclass 5, count 0 2006.173.19:24:27.57#ibcon#about to read 6, iclass 5, count 0 2006.173.19:24:27.57#ibcon#read 6, iclass 5, count 0 2006.173.19:24:27.57#ibcon#end of sib2, iclass 5, count 0 2006.173.19:24:27.57#ibcon#*after write, iclass 5, count 0 2006.173.19:24:27.57#ibcon#*before return 0, iclass 5, count 0 2006.173.19:24:27.57#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.19:24:27.57#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.19:24:27.57#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.19:24:27.57#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.19:24:27.57$vck44/va=2,6 2006.173.19:24:27.57#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.173.19:24:27.57#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.173.19:24:27.57#ibcon#ireg 11 cls_cnt 2 2006.173.19:24:27.57#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.19:24:27.63#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.19:24:27.63#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.19:24:27.63#ibcon#enter wrdev, iclass 7, count 2 2006.173.19:24:27.63#ibcon#first serial, iclass 7, count 2 2006.173.19:24:27.63#ibcon#enter sib2, iclass 7, count 2 2006.173.19:24:27.63#ibcon#flushed, iclass 7, count 2 2006.173.19:24:27.63#ibcon#about to write, iclass 7, count 2 2006.173.19:24:27.63#ibcon#wrote, iclass 7, count 2 2006.173.19:24:27.63#ibcon#about to read 3, iclass 7, count 2 2006.173.19:24:27.65#ibcon#read 3, iclass 7, count 2 2006.173.19:24:27.65#ibcon#about to read 4, iclass 7, count 2 2006.173.19:24:27.65#ibcon#read 4, iclass 7, count 2 2006.173.19:24:27.65#ibcon#about to read 5, iclass 7, count 2 2006.173.19:24:27.65#ibcon#read 5, iclass 7, count 2 2006.173.19:24:27.65#ibcon#about to read 6, iclass 7, count 2 2006.173.19:24:27.65#ibcon#read 6, iclass 7, count 2 2006.173.19:24:27.65#ibcon#end of sib2, iclass 7, count 2 2006.173.19:24:27.65#ibcon#*mode == 0, iclass 7, count 2 2006.173.19:24:27.65#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.173.19:24:27.65#ibcon#[25=AT02-06\r\n] 2006.173.19:24:27.65#ibcon#*before write, iclass 7, count 2 2006.173.19:24:27.65#ibcon#enter sib2, iclass 7, count 2 2006.173.19:24:27.65#ibcon#flushed, iclass 7, count 2 2006.173.19:24:27.65#ibcon#about to write, iclass 7, count 2 2006.173.19:24:27.65#ibcon#wrote, iclass 7, count 2 2006.173.19:24:27.65#ibcon#about to read 3, iclass 7, count 2 2006.173.19:24:27.68#ibcon#read 3, iclass 7, count 2 2006.173.19:24:27.68#ibcon#about to read 4, iclass 7, count 2 2006.173.19:24:27.68#ibcon#read 4, iclass 7, count 2 2006.173.19:24:27.68#ibcon#about to read 5, iclass 7, count 2 2006.173.19:24:27.68#ibcon#read 5, iclass 7, count 2 2006.173.19:24:27.68#ibcon#about to read 6, iclass 7, count 2 2006.173.19:24:27.68#ibcon#read 6, iclass 7, count 2 2006.173.19:24:27.68#ibcon#end of sib2, iclass 7, count 2 2006.173.19:24:27.68#ibcon#*after write, iclass 7, count 2 2006.173.19:24:27.68#ibcon#*before return 0, iclass 7, count 2 2006.173.19:24:27.68#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.19:24:27.68#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.173.19:24:27.68#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.173.19:24:27.68#ibcon#ireg 7 cls_cnt 0 2006.173.19:24:27.68#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.19:24:27.80#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.19:24:27.80#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.19:24:27.80#ibcon#enter wrdev, iclass 7, count 0 2006.173.19:24:27.80#ibcon#first serial, iclass 7, count 0 2006.173.19:24:27.80#ibcon#enter sib2, iclass 7, count 0 2006.173.19:24:27.80#ibcon#flushed, iclass 7, count 0 2006.173.19:24:27.80#ibcon#about to write, iclass 7, count 0 2006.173.19:24:27.80#ibcon#wrote, iclass 7, count 0 2006.173.19:24:27.80#ibcon#about to read 3, iclass 7, count 0 2006.173.19:24:27.82#ibcon#read 3, iclass 7, count 0 2006.173.19:24:27.82#ibcon#about to read 4, iclass 7, count 0 2006.173.19:24:27.82#ibcon#read 4, iclass 7, count 0 2006.173.19:24:27.82#ibcon#about to read 5, iclass 7, count 0 2006.173.19:24:27.82#ibcon#read 5, iclass 7, count 0 2006.173.19:24:27.82#ibcon#about to read 6, iclass 7, count 0 2006.173.19:24:27.82#ibcon#read 6, iclass 7, count 0 2006.173.19:24:27.82#ibcon#end of sib2, iclass 7, count 0 2006.173.19:24:27.82#ibcon#*mode == 0, iclass 7, count 0 2006.173.19:24:27.82#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.19:24:27.82#ibcon#[25=USB\r\n] 2006.173.19:24:27.82#ibcon#*before write, iclass 7, count 0 2006.173.19:24:27.82#ibcon#enter sib2, iclass 7, count 0 2006.173.19:24:27.82#ibcon#flushed, iclass 7, count 0 2006.173.19:24:27.82#ibcon#about to write, iclass 7, count 0 2006.173.19:24:27.82#ibcon#wrote, iclass 7, count 0 2006.173.19:24:27.82#ibcon#about to read 3, iclass 7, count 0 2006.173.19:24:27.85#ibcon#read 3, iclass 7, count 0 2006.173.19:24:27.85#ibcon#about to read 4, iclass 7, count 0 2006.173.19:24:27.85#ibcon#read 4, iclass 7, count 0 2006.173.19:24:27.85#ibcon#about to read 5, iclass 7, count 0 2006.173.19:24:27.85#ibcon#read 5, iclass 7, count 0 2006.173.19:24:27.85#ibcon#about to read 6, iclass 7, count 0 2006.173.19:24:27.85#ibcon#read 6, iclass 7, count 0 2006.173.19:24:27.85#ibcon#end of sib2, iclass 7, count 0 2006.173.19:24:27.85#ibcon#*after write, iclass 7, count 0 2006.173.19:24:27.85#ibcon#*before return 0, iclass 7, count 0 2006.173.19:24:27.85#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.19:24:27.85#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.173.19:24:27.85#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.19:24:27.85#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.19:24:27.85$vck44/valo=3,564.99 2006.173.19:24:27.85#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.19:24:27.85#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.19:24:27.85#ibcon#ireg 17 cls_cnt 0 2006.173.19:24:27.85#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.19:24:27.85#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.19:24:27.85#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.19:24:27.85#ibcon#enter wrdev, iclass 11, count 0 2006.173.19:24:27.85#ibcon#first serial, iclass 11, count 0 2006.173.19:24:27.85#ibcon#enter sib2, iclass 11, count 0 2006.173.19:24:27.85#ibcon#flushed, iclass 11, count 0 2006.173.19:24:27.85#ibcon#about to write, iclass 11, count 0 2006.173.19:24:27.85#ibcon#wrote, iclass 11, count 0 2006.173.19:24:27.85#ibcon#about to read 3, iclass 11, count 0 2006.173.19:24:27.87#ibcon#read 3, iclass 11, count 0 2006.173.19:24:27.87#ibcon#about to read 4, iclass 11, count 0 2006.173.19:24:27.87#ibcon#read 4, iclass 11, count 0 2006.173.19:24:27.87#ibcon#about to read 5, iclass 11, count 0 2006.173.19:24:27.87#ibcon#read 5, iclass 11, count 0 2006.173.19:24:27.87#ibcon#about to read 6, iclass 11, count 0 2006.173.19:24:27.87#ibcon#read 6, iclass 11, count 0 2006.173.19:24:27.87#ibcon#end of sib2, iclass 11, count 0 2006.173.19:24:27.87#ibcon#*mode == 0, iclass 11, count 0 2006.173.19:24:27.87#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.19:24:27.87#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.19:24:27.87#ibcon#*before write, iclass 11, count 0 2006.173.19:24:27.87#ibcon#enter sib2, iclass 11, count 0 2006.173.19:24:27.87#ibcon#flushed, iclass 11, count 0 2006.173.19:24:27.87#ibcon#about to write, iclass 11, count 0 2006.173.19:24:27.87#ibcon#wrote, iclass 11, count 0 2006.173.19:24:27.87#ibcon#about to read 3, iclass 11, count 0 2006.173.19:24:27.91#ibcon#read 3, iclass 11, count 0 2006.173.19:24:27.91#ibcon#about to read 4, iclass 11, count 0 2006.173.19:24:27.91#ibcon#read 4, iclass 11, count 0 2006.173.19:24:27.91#ibcon#about to read 5, iclass 11, count 0 2006.173.19:24:27.91#ibcon#read 5, iclass 11, count 0 2006.173.19:24:27.91#ibcon#about to read 6, iclass 11, count 0 2006.173.19:24:27.91#ibcon#read 6, iclass 11, count 0 2006.173.19:24:27.91#ibcon#end of sib2, iclass 11, count 0 2006.173.19:24:27.91#ibcon#*after write, iclass 11, count 0 2006.173.19:24:27.91#ibcon#*before return 0, iclass 11, count 0 2006.173.19:24:27.91#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.19:24:27.91#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.19:24:27.91#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.19:24:27.91#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.19:24:27.91$vck44/va=3,5 2006.173.19:24:27.91#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.173.19:24:27.91#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.173.19:24:27.91#ibcon#ireg 11 cls_cnt 2 2006.173.19:24:27.91#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.19:24:27.97#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.19:24:27.97#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.19:24:27.97#ibcon#enter wrdev, iclass 13, count 2 2006.173.19:24:27.97#ibcon#first serial, iclass 13, count 2 2006.173.19:24:27.97#ibcon#enter sib2, iclass 13, count 2 2006.173.19:24:27.97#ibcon#flushed, iclass 13, count 2 2006.173.19:24:27.97#ibcon#about to write, iclass 13, count 2 2006.173.19:24:27.97#ibcon#wrote, iclass 13, count 2 2006.173.19:24:27.97#ibcon#about to read 3, iclass 13, count 2 2006.173.19:24:27.99#ibcon#read 3, iclass 13, count 2 2006.173.19:24:27.99#ibcon#about to read 4, iclass 13, count 2 2006.173.19:24:27.99#ibcon#read 4, iclass 13, count 2 2006.173.19:24:27.99#ibcon#about to read 5, iclass 13, count 2 2006.173.19:24:27.99#ibcon#read 5, iclass 13, count 2 2006.173.19:24:27.99#ibcon#about to read 6, iclass 13, count 2 2006.173.19:24:27.99#ibcon#read 6, iclass 13, count 2 2006.173.19:24:27.99#ibcon#end of sib2, iclass 13, count 2 2006.173.19:24:27.99#ibcon#*mode == 0, iclass 13, count 2 2006.173.19:24:27.99#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.173.19:24:27.99#ibcon#[25=AT03-05\r\n] 2006.173.19:24:27.99#ibcon#*before write, iclass 13, count 2 2006.173.19:24:27.99#ibcon#enter sib2, iclass 13, count 2 2006.173.19:24:27.99#ibcon#flushed, iclass 13, count 2 2006.173.19:24:27.99#ibcon#about to write, iclass 13, count 2 2006.173.19:24:27.99#ibcon#wrote, iclass 13, count 2 2006.173.19:24:27.99#ibcon#about to read 3, iclass 13, count 2 2006.173.19:24:28.02#ibcon#read 3, iclass 13, count 2 2006.173.19:24:28.02#ibcon#about to read 4, iclass 13, count 2 2006.173.19:24:28.02#ibcon#read 4, iclass 13, count 2 2006.173.19:24:28.02#ibcon#about to read 5, iclass 13, count 2 2006.173.19:24:28.02#ibcon#read 5, iclass 13, count 2 2006.173.19:24:28.02#ibcon#about to read 6, iclass 13, count 2 2006.173.19:24:28.02#ibcon#read 6, iclass 13, count 2 2006.173.19:24:28.02#ibcon#end of sib2, iclass 13, count 2 2006.173.19:24:28.02#ibcon#*after write, iclass 13, count 2 2006.173.19:24:28.02#ibcon#*before return 0, iclass 13, count 2 2006.173.19:24:28.02#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.19:24:28.02#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.173.19:24:28.02#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.173.19:24:28.02#ibcon#ireg 7 cls_cnt 0 2006.173.19:24:28.02#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.19:24:28.14#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.19:24:28.14#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.19:24:28.14#ibcon#enter wrdev, iclass 13, count 0 2006.173.19:24:28.14#ibcon#first serial, iclass 13, count 0 2006.173.19:24:28.14#ibcon#enter sib2, iclass 13, count 0 2006.173.19:24:28.14#ibcon#flushed, iclass 13, count 0 2006.173.19:24:28.14#ibcon#about to write, iclass 13, count 0 2006.173.19:24:28.14#ibcon#wrote, iclass 13, count 0 2006.173.19:24:28.14#ibcon#about to read 3, iclass 13, count 0 2006.173.19:24:28.16#ibcon#read 3, iclass 13, count 0 2006.173.19:24:28.16#ibcon#about to read 4, iclass 13, count 0 2006.173.19:24:28.16#ibcon#read 4, iclass 13, count 0 2006.173.19:24:28.16#ibcon#about to read 5, iclass 13, count 0 2006.173.19:24:28.16#ibcon#read 5, iclass 13, count 0 2006.173.19:24:28.16#ibcon#about to read 6, iclass 13, count 0 2006.173.19:24:28.16#ibcon#read 6, iclass 13, count 0 2006.173.19:24:28.16#ibcon#end of sib2, iclass 13, count 0 2006.173.19:24:28.16#ibcon#*mode == 0, iclass 13, count 0 2006.173.19:24:28.16#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.19:24:28.16#ibcon#[25=USB\r\n] 2006.173.19:24:28.16#ibcon#*before write, iclass 13, count 0 2006.173.19:24:28.16#ibcon#enter sib2, iclass 13, count 0 2006.173.19:24:28.16#ibcon#flushed, iclass 13, count 0 2006.173.19:24:28.16#ibcon#about to write, iclass 13, count 0 2006.173.19:24:28.16#ibcon#wrote, iclass 13, count 0 2006.173.19:24:28.16#ibcon#about to read 3, iclass 13, count 0 2006.173.19:24:28.19#ibcon#read 3, iclass 13, count 0 2006.173.19:24:28.19#ibcon#about to read 4, iclass 13, count 0 2006.173.19:24:28.19#ibcon#read 4, iclass 13, count 0 2006.173.19:24:28.19#ibcon#about to read 5, iclass 13, count 0 2006.173.19:24:28.19#ibcon#read 5, iclass 13, count 0 2006.173.19:24:28.19#ibcon#about to read 6, iclass 13, count 0 2006.173.19:24:28.19#ibcon#read 6, iclass 13, count 0 2006.173.19:24:28.19#ibcon#end of sib2, iclass 13, count 0 2006.173.19:24:28.19#ibcon#*after write, iclass 13, count 0 2006.173.19:24:28.19#ibcon#*before return 0, iclass 13, count 0 2006.173.19:24:28.19#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.19:24:28.19#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.173.19:24:28.19#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.19:24:28.19#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.19:24:28.19$vck44/valo=4,624.99 2006.173.19:24:28.19#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.19:24:28.19#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.19:24:28.19#ibcon#ireg 17 cls_cnt 0 2006.173.19:24:28.19#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.19:24:28.19#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.19:24:28.19#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.19:24:28.19#ibcon#enter wrdev, iclass 15, count 0 2006.173.19:24:28.19#ibcon#first serial, iclass 15, count 0 2006.173.19:24:28.19#ibcon#enter sib2, iclass 15, count 0 2006.173.19:24:28.19#ibcon#flushed, iclass 15, count 0 2006.173.19:24:28.19#ibcon#about to write, iclass 15, count 0 2006.173.19:24:28.19#ibcon#wrote, iclass 15, count 0 2006.173.19:24:28.19#ibcon#about to read 3, iclass 15, count 0 2006.173.19:24:28.21#ibcon#read 3, iclass 15, count 0 2006.173.19:24:28.21#ibcon#about to read 4, iclass 15, count 0 2006.173.19:24:28.21#ibcon#read 4, iclass 15, count 0 2006.173.19:24:28.21#ibcon#about to read 5, iclass 15, count 0 2006.173.19:24:28.21#ibcon#read 5, iclass 15, count 0 2006.173.19:24:28.21#ibcon#about to read 6, iclass 15, count 0 2006.173.19:24:28.21#ibcon#read 6, iclass 15, count 0 2006.173.19:24:28.21#ibcon#end of sib2, iclass 15, count 0 2006.173.19:24:28.21#ibcon#*mode == 0, iclass 15, count 0 2006.173.19:24:28.21#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.19:24:28.21#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.19:24:28.21#ibcon#*before write, iclass 15, count 0 2006.173.19:24:28.21#ibcon#enter sib2, iclass 15, count 0 2006.173.19:24:28.21#ibcon#flushed, iclass 15, count 0 2006.173.19:24:28.21#ibcon#about to write, iclass 15, count 0 2006.173.19:24:28.21#ibcon#wrote, iclass 15, count 0 2006.173.19:24:28.21#ibcon#about to read 3, iclass 15, count 0 2006.173.19:24:28.25#ibcon#read 3, iclass 15, count 0 2006.173.19:24:28.25#ibcon#about to read 4, iclass 15, count 0 2006.173.19:24:28.25#ibcon#read 4, iclass 15, count 0 2006.173.19:24:28.25#ibcon#about to read 5, iclass 15, count 0 2006.173.19:24:28.25#ibcon#read 5, iclass 15, count 0 2006.173.19:24:28.25#ibcon#about to read 6, iclass 15, count 0 2006.173.19:24:28.25#ibcon#read 6, iclass 15, count 0 2006.173.19:24:28.25#ibcon#end of sib2, iclass 15, count 0 2006.173.19:24:28.25#ibcon#*after write, iclass 15, count 0 2006.173.19:24:28.25#ibcon#*before return 0, iclass 15, count 0 2006.173.19:24:28.25#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.19:24:28.25#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.19:24:28.25#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.19:24:28.25#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.19:24:28.25$vck44/va=4,6 2006.173.19:24:28.25#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.19:24:28.25#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.19:24:28.25#ibcon#ireg 11 cls_cnt 2 2006.173.19:24:28.25#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.19:24:28.31#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.19:24:28.31#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.19:24:28.31#ibcon#enter wrdev, iclass 17, count 2 2006.173.19:24:28.31#ibcon#first serial, iclass 17, count 2 2006.173.19:24:28.31#ibcon#enter sib2, iclass 17, count 2 2006.173.19:24:28.31#ibcon#flushed, iclass 17, count 2 2006.173.19:24:28.31#ibcon#about to write, iclass 17, count 2 2006.173.19:24:28.31#ibcon#wrote, iclass 17, count 2 2006.173.19:24:28.31#ibcon#about to read 3, iclass 17, count 2 2006.173.19:24:28.33#ibcon#read 3, iclass 17, count 2 2006.173.19:24:28.33#ibcon#about to read 4, iclass 17, count 2 2006.173.19:24:28.33#ibcon#read 4, iclass 17, count 2 2006.173.19:24:28.33#ibcon#about to read 5, iclass 17, count 2 2006.173.19:24:28.33#ibcon#read 5, iclass 17, count 2 2006.173.19:24:28.33#ibcon#about to read 6, iclass 17, count 2 2006.173.19:24:28.33#ibcon#read 6, iclass 17, count 2 2006.173.19:24:28.33#ibcon#end of sib2, iclass 17, count 2 2006.173.19:24:28.33#ibcon#*mode == 0, iclass 17, count 2 2006.173.19:24:28.33#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.19:24:28.33#ibcon#[25=AT04-06\r\n] 2006.173.19:24:28.33#ibcon#*before write, iclass 17, count 2 2006.173.19:24:28.33#ibcon#enter sib2, iclass 17, count 2 2006.173.19:24:28.33#ibcon#flushed, iclass 17, count 2 2006.173.19:24:28.33#ibcon#about to write, iclass 17, count 2 2006.173.19:24:28.33#ibcon#wrote, iclass 17, count 2 2006.173.19:24:28.33#ibcon#about to read 3, iclass 17, count 2 2006.173.19:24:28.36#ibcon#read 3, iclass 17, count 2 2006.173.19:24:28.36#ibcon#about to read 4, iclass 17, count 2 2006.173.19:24:28.36#ibcon#read 4, iclass 17, count 2 2006.173.19:24:28.36#ibcon#about to read 5, iclass 17, count 2 2006.173.19:24:28.36#ibcon#read 5, iclass 17, count 2 2006.173.19:24:28.36#ibcon#about to read 6, iclass 17, count 2 2006.173.19:24:28.36#ibcon#read 6, iclass 17, count 2 2006.173.19:24:28.36#ibcon#end of sib2, iclass 17, count 2 2006.173.19:24:28.36#ibcon#*after write, iclass 17, count 2 2006.173.19:24:28.36#ibcon#*before return 0, iclass 17, count 2 2006.173.19:24:28.36#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.19:24:28.36#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.19:24:28.36#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.19:24:28.36#ibcon#ireg 7 cls_cnt 0 2006.173.19:24:28.36#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.19:24:28.48#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.19:24:28.48#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.19:24:28.48#ibcon#enter wrdev, iclass 17, count 0 2006.173.19:24:28.48#ibcon#first serial, iclass 17, count 0 2006.173.19:24:28.48#ibcon#enter sib2, iclass 17, count 0 2006.173.19:24:28.48#ibcon#flushed, iclass 17, count 0 2006.173.19:24:28.48#ibcon#about to write, iclass 17, count 0 2006.173.19:24:28.48#ibcon#wrote, iclass 17, count 0 2006.173.19:24:28.48#ibcon#about to read 3, iclass 17, count 0 2006.173.19:24:28.50#ibcon#read 3, iclass 17, count 0 2006.173.19:24:28.50#ibcon#about to read 4, iclass 17, count 0 2006.173.19:24:28.50#ibcon#read 4, iclass 17, count 0 2006.173.19:24:28.50#ibcon#about to read 5, iclass 17, count 0 2006.173.19:24:28.50#ibcon#read 5, iclass 17, count 0 2006.173.19:24:28.50#ibcon#about to read 6, iclass 17, count 0 2006.173.19:24:28.50#ibcon#read 6, iclass 17, count 0 2006.173.19:24:28.50#ibcon#end of sib2, iclass 17, count 0 2006.173.19:24:28.50#ibcon#*mode == 0, iclass 17, count 0 2006.173.19:24:28.50#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.19:24:28.50#ibcon#[25=USB\r\n] 2006.173.19:24:28.50#ibcon#*before write, iclass 17, count 0 2006.173.19:24:28.50#ibcon#enter sib2, iclass 17, count 0 2006.173.19:24:28.50#ibcon#flushed, iclass 17, count 0 2006.173.19:24:28.50#ibcon#about to write, iclass 17, count 0 2006.173.19:24:28.50#ibcon#wrote, iclass 17, count 0 2006.173.19:24:28.50#ibcon#about to read 3, iclass 17, count 0 2006.173.19:24:28.53#ibcon#read 3, iclass 17, count 0 2006.173.19:24:28.53#ibcon#about to read 4, iclass 17, count 0 2006.173.19:24:28.53#ibcon#read 4, iclass 17, count 0 2006.173.19:24:28.53#ibcon#about to read 5, iclass 17, count 0 2006.173.19:24:28.53#ibcon#read 5, iclass 17, count 0 2006.173.19:24:28.53#ibcon#about to read 6, iclass 17, count 0 2006.173.19:24:28.53#ibcon#read 6, iclass 17, count 0 2006.173.19:24:28.53#ibcon#end of sib2, iclass 17, count 0 2006.173.19:24:28.53#ibcon#*after write, iclass 17, count 0 2006.173.19:24:28.53#ibcon#*before return 0, iclass 17, count 0 2006.173.19:24:28.53#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.19:24:28.53#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.19:24:28.53#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.19:24:28.53#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.19:24:28.53$vck44/valo=5,734.99 2006.173.19:24:28.53#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.19:24:28.53#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.19:24:28.53#ibcon#ireg 17 cls_cnt 0 2006.173.19:24:28.53#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.19:24:28.53#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.19:24:28.53#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.19:24:28.53#ibcon#enter wrdev, iclass 19, count 0 2006.173.19:24:28.53#ibcon#first serial, iclass 19, count 0 2006.173.19:24:28.53#ibcon#enter sib2, iclass 19, count 0 2006.173.19:24:28.53#ibcon#flushed, iclass 19, count 0 2006.173.19:24:28.53#ibcon#about to write, iclass 19, count 0 2006.173.19:24:28.53#ibcon#wrote, iclass 19, count 0 2006.173.19:24:28.53#ibcon#about to read 3, iclass 19, count 0 2006.173.19:24:28.55#ibcon#read 3, iclass 19, count 0 2006.173.19:24:28.55#ibcon#about to read 4, iclass 19, count 0 2006.173.19:24:28.55#ibcon#read 4, iclass 19, count 0 2006.173.19:24:28.55#ibcon#about to read 5, iclass 19, count 0 2006.173.19:24:28.55#ibcon#read 5, iclass 19, count 0 2006.173.19:24:28.55#ibcon#about to read 6, iclass 19, count 0 2006.173.19:24:28.55#ibcon#read 6, iclass 19, count 0 2006.173.19:24:28.55#ibcon#end of sib2, iclass 19, count 0 2006.173.19:24:28.55#ibcon#*mode == 0, iclass 19, count 0 2006.173.19:24:28.55#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.19:24:28.55#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.19:24:28.55#ibcon#*before write, iclass 19, count 0 2006.173.19:24:28.55#ibcon#enter sib2, iclass 19, count 0 2006.173.19:24:28.55#ibcon#flushed, iclass 19, count 0 2006.173.19:24:28.55#ibcon#about to write, iclass 19, count 0 2006.173.19:24:28.55#ibcon#wrote, iclass 19, count 0 2006.173.19:24:28.55#ibcon#about to read 3, iclass 19, count 0 2006.173.19:24:28.59#ibcon#read 3, iclass 19, count 0 2006.173.19:24:28.59#ibcon#about to read 4, iclass 19, count 0 2006.173.19:24:28.59#ibcon#read 4, iclass 19, count 0 2006.173.19:24:28.59#ibcon#about to read 5, iclass 19, count 0 2006.173.19:24:28.59#ibcon#read 5, iclass 19, count 0 2006.173.19:24:28.59#ibcon#about to read 6, iclass 19, count 0 2006.173.19:24:28.59#ibcon#read 6, iclass 19, count 0 2006.173.19:24:28.59#ibcon#end of sib2, iclass 19, count 0 2006.173.19:24:28.59#ibcon#*after write, iclass 19, count 0 2006.173.19:24:28.59#ibcon#*before return 0, iclass 19, count 0 2006.173.19:24:28.59#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.19:24:28.59#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.19:24:28.59#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.19:24:28.59#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.19:24:28.59$vck44/va=5,4 2006.173.19:24:28.59#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.19:24:28.59#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.19:24:28.59#ibcon#ireg 11 cls_cnt 2 2006.173.19:24:28.59#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.19:24:28.65#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.19:24:28.65#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.19:24:28.65#ibcon#enter wrdev, iclass 21, count 2 2006.173.19:24:28.65#ibcon#first serial, iclass 21, count 2 2006.173.19:24:28.65#ibcon#enter sib2, iclass 21, count 2 2006.173.19:24:28.65#ibcon#flushed, iclass 21, count 2 2006.173.19:24:28.65#ibcon#about to write, iclass 21, count 2 2006.173.19:24:28.65#ibcon#wrote, iclass 21, count 2 2006.173.19:24:28.65#ibcon#about to read 3, iclass 21, count 2 2006.173.19:24:28.67#ibcon#read 3, iclass 21, count 2 2006.173.19:24:28.67#ibcon#about to read 4, iclass 21, count 2 2006.173.19:24:28.67#ibcon#read 4, iclass 21, count 2 2006.173.19:24:28.67#ibcon#about to read 5, iclass 21, count 2 2006.173.19:24:28.67#ibcon#read 5, iclass 21, count 2 2006.173.19:24:28.67#ibcon#about to read 6, iclass 21, count 2 2006.173.19:24:28.67#ibcon#read 6, iclass 21, count 2 2006.173.19:24:28.67#ibcon#end of sib2, iclass 21, count 2 2006.173.19:24:28.67#ibcon#*mode == 0, iclass 21, count 2 2006.173.19:24:28.67#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.19:24:28.67#ibcon#[25=AT05-04\r\n] 2006.173.19:24:28.67#ibcon#*before write, iclass 21, count 2 2006.173.19:24:28.67#ibcon#enter sib2, iclass 21, count 2 2006.173.19:24:28.67#ibcon#flushed, iclass 21, count 2 2006.173.19:24:28.67#ibcon#about to write, iclass 21, count 2 2006.173.19:24:28.67#ibcon#wrote, iclass 21, count 2 2006.173.19:24:28.67#ibcon#about to read 3, iclass 21, count 2 2006.173.19:24:28.70#ibcon#read 3, iclass 21, count 2 2006.173.19:24:28.70#ibcon#about to read 4, iclass 21, count 2 2006.173.19:24:28.70#ibcon#read 4, iclass 21, count 2 2006.173.19:24:28.70#ibcon#about to read 5, iclass 21, count 2 2006.173.19:24:28.70#ibcon#read 5, iclass 21, count 2 2006.173.19:24:28.70#ibcon#about to read 6, iclass 21, count 2 2006.173.19:24:28.70#ibcon#read 6, iclass 21, count 2 2006.173.19:24:28.70#ibcon#end of sib2, iclass 21, count 2 2006.173.19:24:28.70#ibcon#*after write, iclass 21, count 2 2006.173.19:24:28.70#ibcon#*before return 0, iclass 21, count 2 2006.173.19:24:28.70#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.19:24:28.70#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.19:24:28.70#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.19:24:28.70#ibcon#ireg 7 cls_cnt 0 2006.173.19:24:28.70#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.19:24:28.82#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.19:24:28.82#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.19:24:28.82#ibcon#enter wrdev, iclass 21, count 0 2006.173.19:24:28.82#ibcon#first serial, iclass 21, count 0 2006.173.19:24:28.82#ibcon#enter sib2, iclass 21, count 0 2006.173.19:24:28.82#ibcon#flushed, iclass 21, count 0 2006.173.19:24:28.82#ibcon#about to write, iclass 21, count 0 2006.173.19:24:28.82#ibcon#wrote, iclass 21, count 0 2006.173.19:24:28.82#ibcon#about to read 3, iclass 21, count 0 2006.173.19:24:28.84#ibcon#read 3, iclass 21, count 0 2006.173.19:24:28.84#ibcon#about to read 4, iclass 21, count 0 2006.173.19:24:28.84#ibcon#read 4, iclass 21, count 0 2006.173.19:24:28.84#ibcon#about to read 5, iclass 21, count 0 2006.173.19:24:28.84#ibcon#read 5, iclass 21, count 0 2006.173.19:24:28.84#ibcon#about to read 6, iclass 21, count 0 2006.173.19:24:28.84#ibcon#read 6, iclass 21, count 0 2006.173.19:24:28.84#ibcon#end of sib2, iclass 21, count 0 2006.173.19:24:28.84#ibcon#*mode == 0, iclass 21, count 0 2006.173.19:24:28.84#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.19:24:28.84#ibcon#[25=USB\r\n] 2006.173.19:24:28.84#ibcon#*before write, iclass 21, count 0 2006.173.19:24:28.84#ibcon#enter sib2, iclass 21, count 0 2006.173.19:24:28.84#ibcon#flushed, iclass 21, count 0 2006.173.19:24:28.84#ibcon#about to write, iclass 21, count 0 2006.173.19:24:28.84#ibcon#wrote, iclass 21, count 0 2006.173.19:24:28.84#ibcon#about to read 3, iclass 21, count 0 2006.173.19:24:28.87#ibcon#read 3, iclass 21, count 0 2006.173.19:24:28.87#ibcon#about to read 4, iclass 21, count 0 2006.173.19:24:28.87#ibcon#read 4, iclass 21, count 0 2006.173.19:24:28.87#ibcon#about to read 5, iclass 21, count 0 2006.173.19:24:28.87#ibcon#read 5, iclass 21, count 0 2006.173.19:24:28.87#ibcon#about to read 6, iclass 21, count 0 2006.173.19:24:28.87#ibcon#read 6, iclass 21, count 0 2006.173.19:24:28.87#ibcon#end of sib2, iclass 21, count 0 2006.173.19:24:28.87#ibcon#*after write, iclass 21, count 0 2006.173.19:24:28.87#ibcon#*before return 0, iclass 21, count 0 2006.173.19:24:28.87#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.19:24:28.87#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.19:24:28.87#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.19:24:28.87#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.19:24:28.87$vck44/valo=6,814.99 2006.173.19:24:28.87#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.19:24:28.87#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.19:24:28.87#ibcon#ireg 17 cls_cnt 0 2006.173.19:24:28.87#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.19:24:28.87#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.19:24:28.87#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.19:24:28.87#ibcon#enter wrdev, iclass 23, count 0 2006.173.19:24:28.87#ibcon#first serial, iclass 23, count 0 2006.173.19:24:28.87#ibcon#enter sib2, iclass 23, count 0 2006.173.19:24:28.87#ibcon#flushed, iclass 23, count 0 2006.173.19:24:28.87#ibcon#about to write, iclass 23, count 0 2006.173.19:24:28.87#ibcon#wrote, iclass 23, count 0 2006.173.19:24:28.87#ibcon#about to read 3, iclass 23, count 0 2006.173.19:24:28.89#ibcon#read 3, iclass 23, count 0 2006.173.19:24:28.89#ibcon#about to read 4, iclass 23, count 0 2006.173.19:24:28.89#ibcon#read 4, iclass 23, count 0 2006.173.19:24:28.89#ibcon#about to read 5, iclass 23, count 0 2006.173.19:24:28.89#ibcon#read 5, iclass 23, count 0 2006.173.19:24:28.89#ibcon#about to read 6, iclass 23, count 0 2006.173.19:24:28.89#ibcon#read 6, iclass 23, count 0 2006.173.19:24:28.89#ibcon#end of sib2, iclass 23, count 0 2006.173.19:24:28.89#ibcon#*mode == 0, iclass 23, count 0 2006.173.19:24:28.89#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.19:24:28.89#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.19:24:28.89#ibcon#*before write, iclass 23, count 0 2006.173.19:24:28.89#ibcon#enter sib2, iclass 23, count 0 2006.173.19:24:28.89#ibcon#flushed, iclass 23, count 0 2006.173.19:24:28.89#ibcon#about to write, iclass 23, count 0 2006.173.19:24:28.89#ibcon#wrote, iclass 23, count 0 2006.173.19:24:28.89#ibcon#about to read 3, iclass 23, count 0 2006.173.19:24:28.93#ibcon#read 3, iclass 23, count 0 2006.173.19:24:28.93#ibcon#about to read 4, iclass 23, count 0 2006.173.19:24:28.93#ibcon#read 4, iclass 23, count 0 2006.173.19:24:28.93#ibcon#about to read 5, iclass 23, count 0 2006.173.19:24:28.93#ibcon#read 5, iclass 23, count 0 2006.173.19:24:28.93#ibcon#about to read 6, iclass 23, count 0 2006.173.19:24:28.93#ibcon#read 6, iclass 23, count 0 2006.173.19:24:28.93#ibcon#end of sib2, iclass 23, count 0 2006.173.19:24:28.93#ibcon#*after write, iclass 23, count 0 2006.173.19:24:28.93#ibcon#*before return 0, iclass 23, count 0 2006.173.19:24:28.93#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.19:24:28.93#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.19:24:28.93#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.19:24:28.93#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.19:24:28.93$vck44/va=6,3 2006.173.19:24:28.93#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.19:24:28.93#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.19:24:28.93#ibcon#ireg 11 cls_cnt 2 2006.173.19:24:28.93#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.19:24:28.99#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.19:24:28.99#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.19:24:28.99#ibcon#enter wrdev, iclass 25, count 2 2006.173.19:24:28.99#ibcon#first serial, iclass 25, count 2 2006.173.19:24:28.99#ibcon#enter sib2, iclass 25, count 2 2006.173.19:24:28.99#ibcon#flushed, iclass 25, count 2 2006.173.19:24:28.99#ibcon#about to write, iclass 25, count 2 2006.173.19:24:28.99#ibcon#wrote, iclass 25, count 2 2006.173.19:24:28.99#ibcon#about to read 3, iclass 25, count 2 2006.173.19:24:29.01#ibcon#read 3, iclass 25, count 2 2006.173.19:24:29.01#ibcon#about to read 4, iclass 25, count 2 2006.173.19:24:29.01#ibcon#read 4, iclass 25, count 2 2006.173.19:24:29.01#ibcon#about to read 5, iclass 25, count 2 2006.173.19:24:29.01#ibcon#read 5, iclass 25, count 2 2006.173.19:24:29.01#ibcon#about to read 6, iclass 25, count 2 2006.173.19:24:29.01#ibcon#read 6, iclass 25, count 2 2006.173.19:24:29.01#ibcon#end of sib2, iclass 25, count 2 2006.173.19:24:29.01#ibcon#*mode == 0, iclass 25, count 2 2006.173.19:24:29.01#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.19:24:29.01#ibcon#[25=AT06-03\r\n] 2006.173.19:24:29.01#ibcon#*before write, iclass 25, count 2 2006.173.19:24:29.01#ibcon#enter sib2, iclass 25, count 2 2006.173.19:24:29.01#ibcon#flushed, iclass 25, count 2 2006.173.19:24:29.01#ibcon#about to write, iclass 25, count 2 2006.173.19:24:29.01#ibcon#wrote, iclass 25, count 2 2006.173.19:24:29.01#ibcon#about to read 3, iclass 25, count 2 2006.173.19:24:29.04#ibcon#read 3, iclass 25, count 2 2006.173.19:24:29.04#ibcon#about to read 4, iclass 25, count 2 2006.173.19:24:29.04#ibcon#read 4, iclass 25, count 2 2006.173.19:24:29.04#ibcon#about to read 5, iclass 25, count 2 2006.173.19:24:29.04#ibcon#read 5, iclass 25, count 2 2006.173.19:24:29.04#ibcon#about to read 6, iclass 25, count 2 2006.173.19:24:29.04#ibcon#read 6, iclass 25, count 2 2006.173.19:24:29.04#ibcon#end of sib2, iclass 25, count 2 2006.173.19:24:29.04#ibcon#*after write, iclass 25, count 2 2006.173.19:24:29.04#ibcon#*before return 0, iclass 25, count 2 2006.173.19:24:29.04#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.19:24:29.04#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.19:24:29.04#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.19:24:29.04#ibcon#ireg 7 cls_cnt 0 2006.173.19:24:29.04#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.19:24:29.16#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.19:24:29.16#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.19:24:29.16#ibcon#enter wrdev, iclass 25, count 0 2006.173.19:24:29.16#ibcon#first serial, iclass 25, count 0 2006.173.19:24:29.16#ibcon#enter sib2, iclass 25, count 0 2006.173.19:24:29.16#ibcon#flushed, iclass 25, count 0 2006.173.19:24:29.16#ibcon#about to write, iclass 25, count 0 2006.173.19:24:29.16#ibcon#wrote, iclass 25, count 0 2006.173.19:24:29.16#ibcon#about to read 3, iclass 25, count 0 2006.173.19:24:29.18#ibcon#read 3, iclass 25, count 0 2006.173.19:24:29.18#ibcon#about to read 4, iclass 25, count 0 2006.173.19:24:29.18#ibcon#read 4, iclass 25, count 0 2006.173.19:24:29.18#ibcon#about to read 5, iclass 25, count 0 2006.173.19:24:29.18#ibcon#read 5, iclass 25, count 0 2006.173.19:24:29.18#ibcon#about to read 6, iclass 25, count 0 2006.173.19:24:29.18#ibcon#read 6, iclass 25, count 0 2006.173.19:24:29.18#ibcon#end of sib2, iclass 25, count 0 2006.173.19:24:29.18#ibcon#*mode == 0, iclass 25, count 0 2006.173.19:24:29.18#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.19:24:29.18#ibcon#[25=USB\r\n] 2006.173.19:24:29.18#ibcon#*before write, iclass 25, count 0 2006.173.19:24:29.18#ibcon#enter sib2, iclass 25, count 0 2006.173.19:24:29.18#ibcon#flushed, iclass 25, count 0 2006.173.19:24:29.18#ibcon#about to write, iclass 25, count 0 2006.173.19:24:29.18#ibcon#wrote, iclass 25, count 0 2006.173.19:24:29.18#ibcon#about to read 3, iclass 25, count 0 2006.173.19:24:29.21#ibcon#read 3, iclass 25, count 0 2006.173.19:24:29.21#ibcon#about to read 4, iclass 25, count 0 2006.173.19:24:29.21#ibcon#read 4, iclass 25, count 0 2006.173.19:24:29.21#ibcon#about to read 5, iclass 25, count 0 2006.173.19:24:29.21#ibcon#read 5, iclass 25, count 0 2006.173.19:24:29.21#ibcon#about to read 6, iclass 25, count 0 2006.173.19:24:29.21#ibcon#read 6, iclass 25, count 0 2006.173.19:24:29.21#ibcon#end of sib2, iclass 25, count 0 2006.173.19:24:29.21#ibcon#*after write, iclass 25, count 0 2006.173.19:24:29.21#ibcon#*before return 0, iclass 25, count 0 2006.173.19:24:29.21#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.19:24:29.21#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.19:24:29.21#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.19:24:29.21#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.19:24:29.21$vck44/valo=7,864.99 2006.173.19:24:29.21#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.19:24:29.21#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.19:24:29.21#ibcon#ireg 17 cls_cnt 0 2006.173.19:24:29.21#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.19:24:29.21#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.19:24:29.21#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.19:24:29.21#ibcon#enter wrdev, iclass 27, count 0 2006.173.19:24:29.21#ibcon#first serial, iclass 27, count 0 2006.173.19:24:29.21#ibcon#enter sib2, iclass 27, count 0 2006.173.19:24:29.21#ibcon#flushed, iclass 27, count 0 2006.173.19:24:29.21#ibcon#about to write, iclass 27, count 0 2006.173.19:24:29.21#ibcon#wrote, iclass 27, count 0 2006.173.19:24:29.21#ibcon#about to read 3, iclass 27, count 0 2006.173.19:24:29.23#ibcon#read 3, iclass 27, count 0 2006.173.19:24:29.23#ibcon#about to read 4, iclass 27, count 0 2006.173.19:24:29.23#ibcon#read 4, iclass 27, count 0 2006.173.19:24:29.23#ibcon#about to read 5, iclass 27, count 0 2006.173.19:24:29.23#ibcon#read 5, iclass 27, count 0 2006.173.19:24:29.23#ibcon#about to read 6, iclass 27, count 0 2006.173.19:24:29.23#ibcon#read 6, iclass 27, count 0 2006.173.19:24:29.23#ibcon#end of sib2, iclass 27, count 0 2006.173.19:24:29.23#ibcon#*mode == 0, iclass 27, count 0 2006.173.19:24:29.23#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.19:24:29.23#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.19:24:29.23#ibcon#*before write, iclass 27, count 0 2006.173.19:24:29.23#ibcon#enter sib2, iclass 27, count 0 2006.173.19:24:29.23#ibcon#flushed, iclass 27, count 0 2006.173.19:24:29.23#ibcon#about to write, iclass 27, count 0 2006.173.19:24:29.23#ibcon#wrote, iclass 27, count 0 2006.173.19:24:29.23#ibcon#about to read 3, iclass 27, count 0 2006.173.19:24:29.27#ibcon#read 3, iclass 27, count 0 2006.173.19:24:29.27#ibcon#about to read 4, iclass 27, count 0 2006.173.19:24:29.27#ibcon#read 4, iclass 27, count 0 2006.173.19:24:29.27#ibcon#about to read 5, iclass 27, count 0 2006.173.19:24:29.27#ibcon#read 5, iclass 27, count 0 2006.173.19:24:29.27#ibcon#about to read 6, iclass 27, count 0 2006.173.19:24:29.27#ibcon#read 6, iclass 27, count 0 2006.173.19:24:29.27#ibcon#end of sib2, iclass 27, count 0 2006.173.19:24:29.27#ibcon#*after write, iclass 27, count 0 2006.173.19:24:29.27#ibcon#*before return 0, iclass 27, count 0 2006.173.19:24:29.27#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.19:24:29.27#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.19:24:29.27#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.19:24:29.27#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.19:24:29.27$vck44/va=7,4 2006.173.19:24:29.27#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.19:24:29.27#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.19:24:29.27#ibcon#ireg 11 cls_cnt 2 2006.173.19:24:29.27#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.19:24:29.33#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.19:24:29.33#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.19:24:29.33#ibcon#enter wrdev, iclass 29, count 2 2006.173.19:24:29.33#ibcon#first serial, iclass 29, count 2 2006.173.19:24:29.33#ibcon#enter sib2, iclass 29, count 2 2006.173.19:24:29.33#ibcon#flushed, iclass 29, count 2 2006.173.19:24:29.33#ibcon#about to write, iclass 29, count 2 2006.173.19:24:29.33#ibcon#wrote, iclass 29, count 2 2006.173.19:24:29.33#ibcon#about to read 3, iclass 29, count 2 2006.173.19:24:29.35#ibcon#read 3, iclass 29, count 2 2006.173.19:24:29.35#ibcon#about to read 4, iclass 29, count 2 2006.173.19:24:29.35#ibcon#read 4, iclass 29, count 2 2006.173.19:24:29.35#ibcon#about to read 5, iclass 29, count 2 2006.173.19:24:29.35#ibcon#read 5, iclass 29, count 2 2006.173.19:24:29.35#ibcon#about to read 6, iclass 29, count 2 2006.173.19:24:29.35#ibcon#read 6, iclass 29, count 2 2006.173.19:24:29.35#ibcon#end of sib2, iclass 29, count 2 2006.173.19:24:29.35#ibcon#*mode == 0, iclass 29, count 2 2006.173.19:24:29.35#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.19:24:29.35#ibcon#[25=AT07-04\r\n] 2006.173.19:24:29.35#ibcon#*before write, iclass 29, count 2 2006.173.19:24:29.35#ibcon#enter sib2, iclass 29, count 2 2006.173.19:24:29.35#ibcon#flushed, iclass 29, count 2 2006.173.19:24:29.35#ibcon#about to write, iclass 29, count 2 2006.173.19:24:29.35#ibcon#wrote, iclass 29, count 2 2006.173.19:24:29.35#ibcon#about to read 3, iclass 29, count 2 2006.173.19:24:29.38#ibcon#read 3, iclass 29, count 2 2006.173.19:24:29.38#ibcon#about to read 4, iclass 29, count 2 2006.173.19:24:29.38#ibcon#read 4, iclass 29, count 2 2006.173.19:24:29.38#ibcon#about to read 5, iclass 29, count 2 2006.173.19:24:29.38#ibcon#read 5, iclass 29, count 2 2006.173.19:24:29.38#ibcon#about to read 6, iclass 29, count 2 2006.173.19:24:29.38#ibcon#read 6, iclass 29, count 2 2006.173.19:24:29.38#ibcon#end of sib2, iclass 29, count 2 2006.173.19:24:29.38#ibcon#*after write, iclass 29, count 2 2006.173.19:24:29.38#ibcon#*before return 0, iclass 29, count 2 2006.173.19:24:29.38#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.19:24:29.38#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.19:24:29.38#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.19:24:29.38#ibcon#ireg 7 cls_cnt 0 2006.173.19:24:29.38#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.19:24:29.50#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.19:24:29.50#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.19:24:29.50#ibcon#enter wrdev, iclass 29, count 0 2006.173.19:24:29.50#ibcon#first serial, iclass 29, count 0 2006.173.19:24:29.50#ibcon#enter sib2, iclass 29, count 0 2006.173.19:24:29.50#ibcon#flushed, iclass 29, count 0 2006.173.19:24:29.50#ibcon#about to write, iclass 29, count 0 2006.173.19:24:29.50#ibcon#wrote, iclass 29, count 0 2006.173.19:24:29.50#ibcon#about to read 3, iclass 29, count 0 2006.173.19:24:29.52#ibcon#read 3, iclass 29, count 0 2006.173.19:24:29.52#ibcon#about to read 4, iclass 29, count 0 2006.173.19:24:29.52#ibcon#read 4, iclass 29, count 0 2006.173.19:24:29.52#ibcon#about to read 5, iclass 29, count 0 2006.173.19:24:29.52#ibcon#read 5, iclass 29, count 0 2006.173.19:24:29.52#ibcon#about to read 6, iclass 29, count 0 2006.173.19:24:29.52#ibcon#read 6, iclass 29, count 0 2006.173.19:24:29.52#ibcon#end of sib2, iclass 29, count 0 2006.173.19:24:29.52#ibcon#*mode == 0, iclass 29, count 0 2006.173.19:24:29.52#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.19:24:29.52#ibcon#[25=USB\r\n] 2006.173.19:24:29.52#ibcon#*before write, iclass 29, count 0 2006.173.19:24:29.52#ibcon#enter sib2, iclass 29, count 0 2006.173.19:24:29.52#ibcon#flushed, iclass 29, count 0 2006.173.19:24:29.52#ibcon#about to write, iclass 29, count 0 2006.173.19:24:29.52#ibcon#wrote, iclass 29, count 0 2006.173.19:24:29.52#ibcon#about to read 3, iclass 29, count 0 2006.173.19:24:29.55#ibcon#read 3, iclass 29, count 0 2006.173.19:24:29.55#ibcon#about to read 4, iclass 29, count 0 2006.173.19:24:29.55#ibcon#read 4, iclass 29, count 0 2006.173.19:24:29.55#ibcon#about to read 5, iclass 29, count 0 2006.173.19:24:29.55#ibcon#read 5, iclass 29, count 0 2006.173.19:24:29.55#ibcon#about to read 6, iclass 29, count 0 2006.173.19:24:29.55#ibcon#read 6, iclass 29, count 0 2006.173.19:24:29.55#ibcon#end of sib2, iclass 29, count 0 2006.173.19:24:29.55#ibcon#*after write, iclass 29, count 0 2006.173.19:24:29.55#ibcon#*before return 0, iclass 29, count 0 2006.173.19:24:29.55#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.19:24:29.55#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.19:24:29.55#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.19:24:29.55#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.19:24:29.55$vck44/valo=8,884.99 2006.173.19:24:29.55#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.19:24:29.55#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.19:24:29.55#ibcon#ireg 17 cls_cnt 0 2006.173.19:24:29.55#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.19:24:29.55#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.19:24:29.55#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.19:24:29.55#ibcon#enter wrdev, iclass 31, count 0 2006.173.19:24:29.55#ibcon#first serial, iclass 31, count 0 2006.173.19:24:29.55#ibcon#enter sib2, iclass 31, count 0 2006.173.19:24:29.55#ibcon#flushed, iclass 31, count 0 2006.173.19:24:29.55#ibcon#about to write, iclass 31, count 0 2006.173.19:24:29.55#ibcon#wrote, iclass 31, count 0 2006.173.19:24:29.55#ibcon#about to read 3, iclass 31, count 0 2006.173.19:24:29.57#ibcon#read 3, iclass 31, count 0 2006.173.19:24:29.57#ibcon#about to read 4, iclass 31, count 0 2006.173.19:24:29.57#ibcon#read 4, iclass 31, count 0 2006.173.19:24:29.57#ibcon#about to read 5, iclass 31, count 0 2006.173.19:24:29.57#ibcon#read 5, iclass 31, count 0 2006.173.19:24:29.57#ibcon#about to read 6, iclass 31, count 0 2006.173.19:24:29.57#ibcon#read 6, iclass 31, count 0 2006.173.19:24:29.57#ibcon#end of sib2, iclass 31, count 0 2006.173.19:24:29.57#ibcon#*mode == 0, iclass 31, count 0 2006.173.19:24:29.57#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.19:24:29.57#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.19:24:29.57#ibcon#*before write, iclass 31, count 0 2006.173.19:24:29.57#ibcon#enter sib2, iclass 31, count 0 2006.173.19:24:29.57#ibcon#flushed, iclass 31, count 0 2006.173.19:24:29.57#ibcon#about to write, iclass 31, count 0 2006.173.19:24:29.57#ibcon#wrote, iclass 31, count 0 2006.173.19:24:29.57#ibcon#about to read 3, iclass 31, count 0 2006.173.19:24:29.61#ibcon#read 3, iclass 31, count 0 2006.173.19:24:29.61#ibcon#about to read 4, iclass 31, count 0 2006.173.19:24:29.61#ibcon#read 4, iclass 31, count 0 2006.173.19:24:29.61#ibcon#about to read 5, iclass 31, count 0 2006.173.19:24:29.61#ibcon#read 5, iclass 31, count 0 2006.173.19:24:29.61#ibcon#about to read 6, iclass 31, count 0 2006.173.19:24:29.61#ibcon#read 6, iclass 31, count 0 2006.173.19:24:29.61#ibcon#end of sib2, iclass 31, count 0 2006.173.19:24:29.61#ibcon#*after write, iclass 31, count 0 2006.173.19:24:29.61#ibcon#*before return 0, iclass 31, count 0 2006.173.19:24:29.61#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.19:24:29.61#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.19:24:29.61#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.19:24:29.61#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.19:24:29.61$vck44/va=8,4 2006.173.19:24:29.61#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.173.19:24:29.61#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.173.19:24:29.61#ibcon#ireg 11 cls_cnt 2 2006.173.19:24:29.61#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.19:24:29.67#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.19:24:29.67#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.19:24:29.67#ibcon#enter wrdev, iclass 33, count 2 2006.173.19:24:29.67#ibcon#first serial, iclass 33, count 2 2006.173.19:24:29.67#ibcon#enter sib2, iclass 33, count 2 2006.173.19:24:29.67#ibcon#flushed, iclass 33, count 2 2006.173.19:24:29.67#ibcon#about to write, iclass 33, count 2 2006.173.19:24:29.67#ibcon#wrote, iclass 33, count 2 2006.173.19:24:29.67#ibcon#about to read 3, iclass 33, count 2 2006.173.19:24:29.69#ibcon#read 3, iclass 33, count 2 2006.173.19:24:29.69#ibcon#about to read 4, iclass 33, count 2 2006.173.19:24:29.69#ibcon#read 4, iclass 33, count 2 2006.173.19:24:29.69#ibcon#about to read 5, iclass 33, count 2 2006.173.19:24:29.69#ibcon#read 5, iclass 33, count 2 2006.173.19:24:29.69#ibcon#about to read 6, iclass 33, count 2 2006.173.19:24:29.69#ibcon#read 6, iclass 33, count 2 2006.173.19:24:29.69#ibcon#end of sib2, iclass 33, count 2 2006.173.19:24:29.69#ibcon#*mode == 0, iclass 33, count 2 2006.173.19:24:29.69#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.173.19:24:29.69#ibcon#[25=AT08-04\r\n] 2006.173.19:24:29.69#ibcon#*before write, iclass 33, count 2 2006.173.19:24:29.69#ibcon#enter sib2, iclass 33, count 2 2006.173.19:24:29.69#ibcon#flushed, iclass 33, count 2 2006.173.19:24:29.69#ibcon#about to write, iclass 33, count 2 2006.173.19:24:29.69#ibcon#wrote, iclass 33, count 2 2006.173.19:24:29.69#ibcon#about to read 3, iclass 33, count 2 2006.173.19:24:29.72#ibcon#read 3, iclass 33, count 2 2006.173.19:24:29.72#ibcon#about to read 4, iclass 33, count 2 2006.173.19:24:29.72#ibcon#read 4, iclass 33, count 2 2006.173.19:24:29.72#ibcon#about to read 5, iclass 33, count 2 2006.173.19:24:29.72#ibcon#read 5, iclass 33, count 2 2006.173.19:24:29.72#ibcon#about to read 6, iclass 33, count 2 2006.173.19:24:29.72#ibcon#read 6, iclass 33, count 2 2006.173.19:24:29.72#ibcon#end of sib2, iclass 33, count 2 2006.173.19:24:29.72#ibcon#*after write, iclass 33, count 2 2006.173.19:24:29.72#ibcon#*before return 0, iclass 33, count 2 2006.173.19:24:29.72#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.19:24:29.72#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.173.19:24:29.72#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.173.19:24:29.72#ibcon#ireg 7 cls_cnt 0 2006.173.19:24:29.72#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.19:24:29.84#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.19:24:29.84#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.19:24:29.84#ibcon#enter wrdev, iclass 33, count 0 2006.173.19:24:29.84#ibcon#first serial, iclass 33, count 0 2006.173.19:24:29.84#ibcon#enter sib2, iclass 33, count 0 2006.173.19:24:29.84#ibcon#flushed, iclass 33, count 0 2006.173.19:24:29.84#ibcon#about to write, iclass 33, count 0 2006.173.19:24:29.84#ibcon#wrote, iclass 33, count 0 2006.173.19:24:29.84#ibcon#about to read 3, iclass 33, count 0 2006.173.19:24:29.86#ibcon#read 3, iclass 33, count 0 2006.173.19:24:29.86#ibcon#about to read 4, iclass 33, count 0 2006.173.19:24:29.86#ibcon#read 4, iclass 33, count 0 2006.173.19:24:29.86#ibcon#about to read 5, iclass 33, count 0 2006.173.19:24:29.86#ibcon#read 5, iclass 33, count 0 2006.173.19:24:29.86#ibcon#about to read 6, iclass 33, count 0 2006.173.19:24:29.86#ibcon#read 6, iclass 33, count 0 2006.173.19:24:29.86#ibcon#end of sib2, iclass 33, count 0 2006.173.19:24:29.86#ibcon#*mode == 0, iclass 33, count 0 2006.173.19:24:29.86#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.19:24:29.86#ibcon#[25=USB\r\n] 2006.173.19:24:29.86#ibcon#*before write, iclass 33, count 0 2006.173.19:24:29.86#ibcon#enter sib2, iclass 33, count 0 2006.173.19:24:29.86#ibcon#flushed, iclass 33, count 0 2006.173.19:24:29.86#ibcon#about to write, iclass 33, count 0 2006.173.19:24:29.86#ibcon#wrote, iclass 33, count 0 2006.173.19:24:29.86#ibcon#about to read 3, iclass 33, count 0 2006.173.19:24:29.89#ibcon#read 3, iclass 33, count 0 2006.173.19:24:29.89#ibcon#about to read 4, iclass 33, count 0 2006.173.19:24:29.89#ibcon#read 4, iclass 33, count 0 2006.173.19:24:29.89#ibcon#about to read 5, iclass 33, count 0 2006.173.19:24:29.89#ibcon#read 5, iclass 33, count 0 2006.173.19:24:29.89#ibcon#about to read 6, iclass 33, count 0 2006.173.19:24:29.89#ibcon#read 6, iclass 33, count 0 2006.173.19:24:29.89#ibcon#end of sib2, iclass 33, count 0 2006.173.19:24:29.89#ibcon#*after write, iclass 33, count 0 2006.173.19:24:29.89#ibcon#*before return 0, iclass 33, count 0 2006.173.19:24:29.89#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.19:24:29.89#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.173.19:24:29.89#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.19:24:29.89#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.19:24:29.89$vck44/vblo=1,629.99 2006.173.19:24:29.89#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.19:24:29.89#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.19:24:29.89#ibcon#ireg 17 cls_cnt 0 2006.173.19:24:29.89#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.19:24:29.89#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.19:24:29.89#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.19:24:29.89#ibcon#enter wrdev, iclass 35, count 0 2006.173.19:24:29.89#ibcon#first serial, iclass 35, count 0 2006.173.19:24:29.89#ibcon#enter sib2, iclass 35, count 0 2006.173.19:24:29.89#ibcon#flushed, iclass 35, count 0 2006.173.19:24:29.89#ibcon#about to write, iclass 35, count 0 2006.173.19:24:29.89#ibcon#wrote, iclass 35, count 0 2006.173.19:24:29.89#ibcon#about to read 3, iclass 35, count 0 2006.173.19:24:29.91#ibcon#read 3, iclass 35, count 0 2006.173.19:24:29.91#ibcon#about to read 4, iclass 35, count 0 2006.173.19:24:29.91#ibcon#read 4, iclass 35, count 0 2006.173.19:24:29.91#ibcon#about to read 5, iclass 35, count 0 2006.173.19:24:29.91#ibcon#read 5, iclass 35, count 0 2006.173.19:24:29.91#ibcon#about to read 6, iclass 35, count 0 2006.173.19:24:29.91#ibcon#read 6, iclass 35, count 0 2006.173.19:24:29.91#ibcon#end of sib2, iclass 35, count 0 2006.173.19:24:29.91#ibcon#*mode == 0, iclass 35, count 0 2006.173.19:24:29.91#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.19:24:29.91#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.19:24:29.91#ibcon#*before write, iclass 35, count 0 2006.173.19:24:29.91#ibcon#enter sib2, iclass 35, count 0 2006.173.19:24:29.91#ibcon#flushed, iclass 35, count 0 2006.173.19:24:29.91#ibcon#about to write, iclass 35, count 0 2006.173.19:24:29.91#ibcon#wrote, iclass 35, count 0 2006.173.19:24:29.91#ibcon#about to read 3, iclass 35, count 0 2006.173.19:24:29.95#ibcon#read 3, iclass 35, count 0 2006.173.19:24:29.95#ibcon#about to read 4, iclass 35, count 0 2006.173.19:24:29.95#ibcon#read 4, iclass 35, count 0 2006.173.19:24:29.95#ibcon#about to read 5, iclass 35, count 0 2006.173.19:24:29.95#ibcon#read 5, iclass 35, count 0 2006.173.19:24:29.95#ibcon#about to read 6, iclass 35, count 0 2006.173.19:24:29.95#ibcon#read 6, iclass 35, count 0 2006.173.19:24:29.95#ibcon#end of sib2, iclass 35, count 0 2006.173.19:24:29.95#ibcon#*after write, iclass 35, count 0 2006.173.19:24:29.95#ibcon#*before return 0, iclass 35, count 0 2006.173.19:24:29.95#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.19:24:29.95#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.19:24:29.95#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.19:24:29.95#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.19:24:29.95$vck44/vb=1,4 2006.173.19:24:29.95#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.173.19:24:29.95#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.173.19:24:29.95#ibcon#ireg 11 cls_cnt 2 2006.173.19:24:29.95#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.19:24:29.95#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.19:24:29.95#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.19:24:29.95#ibcon#enter wrdev, iclass 37, count 2 2006.173.19:24:29.95#ibcon#first serial, iclass 37, count 2 2006.173.19:24:29.95#ibcon#enter sib2, iclass 37, count 2 2006.173.19:24:29.95#ibcon#flushed, iclass 37, count 2 2006.173.19:24:29.95#ibcon#about to write, iclass 37, count 2 2006.173.19:24:29.95#ibcon#wrote, iclass 37, count 2 2006.173.19:24:29.95#ibcon#about to read 3, iclass 37, count 2 2006.173.19:24:29.97#ibcon#read 3, iclass 37, count 2 2006.173.19:24:29.97#ibcon#about to read 4, iclass 37, count 2 2006.173.19:24:29.97#ibcon#read 4, iclass 37, count 2 2006.173.19:24:29.97#ibcon#about to read 5, iclass 37, count 2 2006.173.19:24:29.97#ibcon#read 5, iclass 37, count 2 2006.173.19:24:29.97#ibcon#about to read 6, iclass 37, count 2 2006.173.19:24:29.97#ibcon#read 6, iclass 37, count 2 2006.173.19:24:29.97#ibcon#end of sib2, iclass 37, count 2 2006.173.19:24:29.97#ibcon#*mode == 0, iclass 37, count 2 2006.173.19:24:29.97#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.173.19:24:29.97#ibcon#[27=AT01-04\r\n] 2006.173.19:24:29.97#ibcon#*before write, iclass 37, count 2 2006.173.19:24:29.97#ibcon#enter sib2, iclass 37, count 2 2006.173.19:24:29.97#ibcon#flushed, iclass 37, count 2 2006.173.19:24:29.97#ibcon#about to write, iclass 37, count 2 2006.173.19:24:29.97#ibcon#wrote, iclass 37, count 2 2006.173.19:24:29.97#ibcon#about to read 3, iclass 37, count 2 2006.173.19:24:30.00#ibcon#read 3, iclass 37, count 2 2006.173.19:24:30.00#ibcon#about to read 4, iclass 37, count 2 2006.173.19:24:30.00#ibcon#read 4, iclass 37, count 2 2006.173.19:24:30.00#ibcon#about to read 5, iclass 37, count 2 2006.173.19:24:30.00#ibcon#read 5, iclass 37, count 2 2006.173.19:24:30.00#ibcon#about to read 6, iclass 37, count 2 2006.173.19:24:30.00#ibcon#read 6, iclass 37, count 2 2006.173.19:24:30.00#ibcon#end of sib2, iclass 37, count 2 2006.173.19:24:30.00#ibcon#*after write, iclass 37, count 2 2006.173.19:24:30.00#ibcon#*before return 0, iclass 37, count 2 2006.173.19:24:30.00#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.19:24:30.00#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.173.19:24:30.00#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.173.19:24:30.00#ibcon#ireg 7 cls_cnt 0 2006.173.19:24:30.00#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.19:24:30.12#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.19:24:30.12#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.19:24:30.12#ibcon#enter wrdev, iclass 37, count 0 2006.173.19:24:30.12#ibcon#first serial, iclass 37, count 0 2006.173.19:24:30.12#ibcon#enter sib2, iclass 37, count 0 2006.173.19:24:30.12#ibcon#flushed, iclass 37, count 0 2006.173.19:24:30.12#ibcon#about to write, iclass 37, count 0 2006.173.19:24:30.12#ibcon#wrote, iclass 37, count 0 2006.173.19:24:30.12#ibcon#about to read 3, iclass 37, count 0 2006.173.19:24:30.14#ibcon#read 3, iclass 37, count 0 2006.173.19:24:30.14#ibcon#about to read 4, iclass 37, count 0 2006.173.19:24:30.14#ibcon#read 4, iclass 37, count 0 2006.173.19:24:30.14#ibcon#about to read 5, iclass 37, count 0 2006.173.19:24:30.14#ibcon#read 5, iclass 37, count 0 2006.173.19:24:30.14#ibcon#about to read 6, iclass 37, count 0 2006.173.19:24:30.14#ibcon#read 6, iclass 37, count 0 2006.173.19:24:30.14#ibcon#end of sib2, iclass 37, count 0 2006.173.19:24:30.14#ibcon#*mode == 0, iclass 37, count 0 2006.173.19:24:30.14#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.19:24:30.14#ibcon#[27=USB\r\n] 2006.173.19:24:30.14#ibcon#*before write, iclass 37, count 0 2006.173.19:24:30.14#ibcon#enter sib2, iclass 37, count 0 2006.173.19:24:30.14#ibcon#flushed, iclass 37, count 0 2006.173.19:24:30.14#ibcon#about to write, iclass 37, count 0 2006.173.19:24:30.14#ibcon#wrote, iclass 37, count 0 2006.173.19:24:30.14#ibcon#about to read 3, iclass 37, count 0 2006.173.19:24:30.17#ibcon#read 3, iclass 37, count 0 2006.173.19:24:30.17#ibcon#about to read 4, iclass 37, count 0 2006.173.19:24:30.17#ibcon#read 4, iclass 37, count 0 2006.173.19:24:30.17#ibcon#about to read 5, iclass 37, count 0 2006.173.19:24:30.17#ibcon#read 5, iclass 37, count 0 2006.173.19:24:30.17#ibcon#about to read 6, iclass 37, count 0 2006.173.19:24:30.17#ibcon#read 6, iclass 37, count 0 2006.173.19:24:30.17#ibcon#end of sib2, iclass 37, count 0 2006.173.19:24:30.17#ibcon#*after write, iclass 37, count 0 2006.173.19:24:30.17#ibcon#*before return 0, iclass 37, count 0 2006.173.19:24:30.17#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.19:24:30.17#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.173.19:24:30.17#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.19:24:30.17#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.19:24:30.17$vck44/vblo=2,634.99 2006.173.19:24:30.17#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.19:24:30.17#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.19:24:30.17#ibcon#ireg 17 cls_cnt 0 2006.173.19:24:30.17#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.19:24:30.17#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.19:24:30.17#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.19:24:30.17#ibcon#enter wrdev, iclass 39, count 0 2006.173.19:24:30.17#ibcon#first serial, iclass 39, count 0 2006.173.19:24:30.17#ibcon#enter sib2, iclass 39, count 0 2006.173.19:24:30.17#ibcon#flushed, iclass 39, count 0 2006.173.19:24:30.17#ibcon#about to write, iclass 39, count 0 2006.173.19:24:30.17#ibcon#wrote, iclass 39, count 0 2006.173.19:24:30.17#ibcon#about to read 3, iclass 39, count 0 2006.173.19:24:30.19#ibcon#read 3, iclass 39, count 0 2006.173.19:24:30.19#ibcon#about to read 4, iclass 39, count 0 2006.173.19:24:30.19#ibcon#read 4, iclass 39, count 0 2006.173.19:24:30.19#ibcon#about to read 5, iclass 39, count 0 2006.173.19:24:30.19#ibcon#read 5, iclass 39, count 0 2006.173.19:24:30.19#ibcon#about to read 6, iclass 39, count 0 2006.173.19:24:30.19#ibcon#read 6, iclass 39, count 0 2006.173.19:24:30.19#ibcon#end of sib2, iclass 39, count 0 2006.173.19:24:30.19#ibcon#*mode == 0, iclass 39, count 0 2006.173.19:24:30.19#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.19:24:30.19#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.19:24:30.19#ibcon#*before write, iclass 39, count 0 2006.173.19:24:30.19#ibcon#enter sib2, iclass 39, count 0 2006.173.19:24:30.19#ibcon#flushed, iclass 39, count 0 2006.173.19:24:30.19#ibcon#about to write, iclass 39, count 0 2006.173.19:24:30.19#ibcon#wrote, iclass 39, count 0 2006.173.19:24:30.19#ibcon#about to read 3, iclass 39, count 0 2006.173.19:24:30.23#ibcon#read 3, iclass 39, count 0 2006.173.19:24:30.23#ibcon#about to read 4, iclass 39, count 0 2006.173.19:24:30.23#ibcon#read 4, iclass 39, count 0 2006.173.19:24:30.23#ibcon#about to read 5, iclass 39, count 0 2006.173.19:24:30.23#ibcon#read 5, iclass 39, count 0 2006.173.19:24:30.23#ibcon#about to read 6, iclass 39, count 0 2006.173.19:24:30.23#ibcon#read 6, iclass 39, count 0 2006.173.19:24:30.23#ibcon#end of sib2, iclass 39, count 0 2006.173.19:24:30.23#ibcon#*after write, iclass 39, count 0 2006.173.19:24:30.23#ibcon#*before return 0, iclass 39, count 0 2006.173.19:24:30.23#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.19:24:30.23#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.19:24:30.23#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.19:24:30.23#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.19:24:30.23$vck44/vb=2,4 2006.173.19:24:30.23#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.19:24:30.23#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.19:24:30.23#ibcon#ireg 11 cls_cnt 2 2006.173.19:24:30.23#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.19:24:30.29#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.19:24:30.29#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.19:24:30.29#ibcon#enter wrdev, iclass 3, count 2 2006.173.19:24:30.29#ibcon#first serial, iclass 3, count 2 2006.173.19:24:30.29#ibcon#enter sib2, iclass 3, count 2 2006.173.19:24:30.29#ibcon#flushed, iclass 3, count 2 2006.173.19:24:30.29#ibcon#about to write, iclass 3, count 2 2006.173.19:24:30.29#ibcon#wrote, iclass 3, count 2 2006.173.19:24:30.29#ibcon#about to read 3, iclass 3, count 2 2006.173.19:24:30.31#ibcon#read 3, iclass 3, count 2 2006.173.19:24:30.31#ibcon#about to read 4, iclass 3, count 2 2006.173.19:24:30.31#ibcon#read 4, iclass 3, count 2 2006.173.19:24:30.31#ibcon#about to read 5, iclass 3, count 2 2006.173.19:24:30.31#ibcon#read 5, iclass 3, count 2 2006.173.19:24:30.31#ibcon#about to read 6, iclass 3, count 2 2006.173.19:24:30.31#ibcon#read 6, iclass 3, count 2 2006.173.19:24:30.31#ibcon#end of sib2, iclass 3, count 2 2006.173.19:24:30.31#ibcon#*mode == 0, iclass 3, count 2 2006.173.19:24:30.31#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.19:24:30.31#ibcon#[27=AT02-04\r\n] 2006.173.19:24:30.31#ibcon#*before write, iclass 3, count 2 2006.173.19:24:30.31#ibcon#enter sib2, iclass 3, count 2 2006.173.19:24:30.31#ibcon#flushed, iclass 3, count 2 2006.173.19:24:30.31#ibcon#about to write, iclass 3, count 2 2006.173.19:24:30.31#ibcon#wrote, iclass 3, count 2 2006.173.19:24:30.31#ibcon#about to read 3, iclass 3, count 2 2006.173.19:24:30.34#ibcon#read 3, iclass 3, count 2 2006.173.19:24:30.34#ibcon#about to read 4, iclass 3, count 2 2006.173.19:24:30.34#ibcon#read 4, iclass 3, count 2 2006.173.19:24:30.34#ibcon#about to read 5, iclass 3, count 2 2006.173.19:24:30.34#ibcon#read 5, iclass 3, count 2 2006.173.19:24:30.34#ibcon#about to read 6, iclass 3, count 2 2006.173.19:24:30.34#ibcon#read 6, iclass 3, count 2 2006.173.19:24:30.34#ibcon#end of sib2, iclass 3, count 2 2006.173.19:24:30.34#ibcon#*after write, iclass 3, count 2 2006.173.19:24:30.34#ibcon#*before return 0, iclass 3, count 2 2006.173.19:24:30.34#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.19:24:30.34#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.19:24:30.34#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.19:24:30.34#ibcon#ireg 7 cls_cnt 0 2006.173.19:24:30.34#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.19:24:30.46#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.19:24:30.46#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.19:24:30.46#ibcon#enter wrdev, iclass 3, count 0 2006.173.19:24:30.46#ibcon#first serial, iclass 3, count 0 2006.173.19:24:30.46#ibcon#enter sib2, iclass 3, count 0 2006.173.19:24:30.46#ibcon#flushed, iclass 3, count 0 2006.173.19:24:30.46#ibcon#about to write, iclass 3, count 0 2006.173.19:24:30.46#ibcon#wrote, iclass 3, count 0 2006.173.19:24:30.46#ibcon#about to read 3, iclass 3, count 0 2006.173.19:24:30.48#ibcon#read 3, iclass 3, count 0 2006.173.19:24:30.48#ibcon#about to read 4, iclass 3, count 0 2006.173.19:24:30.48#ibcon#read 4, iclass 3, count 0 2006.173.19:24:30.48#ibcon#about to read 5, iclass 3, count 0 2006.173.19:24:30.48#ibcon#read 5, iclass 3, count 0 2006.173.19:24:30.48#ibcon#about to read 6, iclass 3, count 0 2006.173.19:24:30.48#ibcon#read 6, iclass 3, count 0 2006.173.19:24:30.48#ibcon#end of sib2, iclass 3, count 0 2006.173.19:24:30.48#ibcon#*mode == 0, iclass 3, count 0 2006.173.19:24:30.48#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.19:24:30.48#ibcon#[27=USB\r\n] 2006.173.19:24:30.48#ibcon#*before write, iclass 3, count 0 2006.173.19:24:30.48#ibcon#enter sib2, iclass 3, count 0 2006.173.19:24:30.48#ibcon#flushed, iclass 3, count 0 2006.173.19:24:30.48#ibcon#about to write, iclass 3, count 0 2006.173.19:24:30.48#ibcon#wrote, iclass 3, count 0 2006.173.19:24:30.48#ibcon#about to read 3, iclass 3, count 0 2006.173.19:24:30.51#ibcon#read 3, iclass 3, count 0 2006.173.19:24:30.51#ibcon#about to read 4, iclass 3, count 0 2006.173.19:24:30.51#ibcon#read 4, iclass 3, count 0 2006.173.19:24:30.51#ibcon#about to read 5, iclass 3, count 0 2006.173.19:24:30.51#ibcon#read 5, iclass 3, count 0 2006.173.19:24:30.51#ibcon#about to read 6, iclass 3, count 0 2006.173.19:24:30.51#ibcon#read 6, iclass 3, count 0 2006.173.19:24:30.51#ibcon#end of sib2, iclass 3, count 0 2006.173.19:24:30.51#ibcon#*after write, iclass 3, count 0 2006.173.19:24:30.51#ibcon#*before return 0, iclass 3, count 0 2006.173.19:24:30.51#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.19:24:30.51#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.19:24:30.51#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.19:24:30.51#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.19:24:30.51$vck44/vblo=3,649.99 2006.173.19:24:30.51#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.19:24:30.51#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.19:24:30.51#ibcon#ireg 17 cls_cnt 0 2006.173.19:24:30.51#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.19:24:30.51#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.19:24:30.51#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.19:24:30.51#ibcon#enter wrdev, iclass 5, count 0 2006.173.19:24:30.51#ibcon#first serial, iclass 5, count 0 2006.173.19:24:30.51#ibcon#enter sib2, iclass 5, count 0 2006.173.19:24:30.51#ibcon#flushed, iclass 5, count 0 2006.173.19:24:30.51#ibcon#about to write, iclass 5, count 0 2006.173.19:24:30.51#ibcon#wrote, iclass 5, count 0 2006.173.19:24:30.51#ibcon#about to read 3, iclass 5, count 0 2006.173.19:24:30.53#ibcon#read 3, iclass 5, count 0 2006.173.19:24:30.53#ibcon#about to read 4, iclass 5, count 0 2006.173.19:24:30.53#ibcon#read 4, iclass 5, count 0 2006.173.19:24:30.53#ibcon#about to read 5, iclass 5, count 0 2006.173.19:24:30.53#ibcon#read 5, iclass 5, count 0 2006.173.19:24:30.53#ibcon#about to read 6, iclass 5, count 0 2006.173.19:24:30.53#ibcon#read 6, iclass 5, count 0 2006.173.19:24:30.53#ibcon#end of sib2, iclass 5, count 0 2006.173.19:24:30.53#ibcon#*mode == 0, iclass 5, count 0 2006.173.19:24:30.53#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.19:24:30.53#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.19:24:30.53#ibcon#*before write, iclass 5, count 0 2006.173.19:24:30.53#ibcon#enter sib2, iclass 5, count 0 2006.173.19:24:30.53#ibcon#flushed, iclass 5, count 0 2006.173.19:24:30.53#ibcon#about to write, iclass 5, count 0 2006.173.19:24:30.53#ibcon#wrote, iclass 5, count 0 2006.173.19:24:30.53#ibcon#about to read 3, iclass 5, count 0 2006.173.19:24:30.57#ibcon#read 3, iclass 5, count 0 2006.173.19:24:30.57#ibcon#about to read 4, iclass 5, count 0 2006.173.19:24:30.57#ibcon#read 4, iclass 5, count 0 2006.173.19:24:30.57#ibcon#about to read 5, iclass 5, count 0 2006.173.19:24:30.57#ibcon#read 5, iclass 5, count 0 2006.173.19:24:30.57#ibcon#about to read 6, iclass 5, count 0 2006.173.19:24:30.57#ibcon#read 6, iclass 5, count 0 2006.173.19:24:30.57#ibcon#end of sib2, iclass 5, count 0 2006.173.19:24:30.57#ibcon#*after write, iclass 5, count 0 2006.173.19:24:30.57#ibcon#*before return 0, iclass 5, count 0 2006.173.19:24:30.57#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.19:24:30.57#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.19:24:30.57#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.19:24:30.57#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.19:24:30.57$vck44/vb=3,4 2006.173.19:24:30.57#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.173.19:24:30.57#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.173.19:24:30.57#ibcon#ireg 11 cls_cnt 2 2006.173.19:24:30.57#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.19:24:30.63#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.19:24:30.63#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.19:24:30.63#ibcon#enter wrdev, iclass 7, count 2 2006.173.19:24:30.63#ibcon#first serial, iclass 7, count 2 2006.173.19:24:30.63#ibcon#enter sib2, iclass 7, count 2 2006.173.19:24:30.63#ibcon#flushed, iclass 7, count 2 2006.173.19:24:30.63#ibcon#about to write, iclass 7, count 2 2006.173.19:24:30.63#ibcon#wrote, iclass 7, count 2 2006.173.19:24:30.63#ibcon#about to read 3, iclass 7, count 2 2006.173.19:24:30.65#ibcon#read 3, iclass 7, count 2 2006.173.19:24:30.65#ibcon#about to read 4, iclass 7, count 2 2006.173.19:24:30.65#ibcon#read 4, iclass 7, count 2 2006.173.19:24:30.65#ibcon#about to read 5, iclass 7, count 2 2006.173.19:24:30.65#ibcon#read 5, iclass 7, count 2 2006.173.19:24:30.65#ibcon#about to read 6, iclass 7, count 2 2006.173.19:24:30.65#ibcon#read 6, iclass 7, count 2 2006.173.19:24:30.65#ibcon#end of sib2, iclass 7, count 2 2006.173.19:24:30.65#ibcon#*mode == 0, iclass 7, count 2 2006.173.19:24:30.65#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.173.19:24:30.65#ibcon#[27=AT03-04\r\n] 2006.173.19:24:30.65#ibcon#*before write, iclass 7, count 2 2006.173.19:24:30.65#ibcon#enter sib2, iclass 7, count 2 2006.173.19:24:30.65#ibcon#flushed, iclass 7, count 2 2006.173.19:24:30.65#ibcon#about to write, iclass 7, count 2 2006.173.19:24:30.65#ibcon#wrote, iclass 7, count 2 2006.173.19:24:30.65#ibcon#about to read 3, iclass 7, count 2 2006.173.19:24:30.68#ibcon#read 3, iclass 7, count 2 2006.173.19:24:30.68#ibcon#about to read 4, iclass 7, count 2 2006.173.19:24:30.68#ibcon#read 4, iclass 7, count 2 2006.173.19:24:30.68#ibcon#about to read 5, iclass 7, count 2 2006.173.19:24:30.68#ibcon#read 5, iclass 7, count 2 2006.173.19:24:30.68#ibcon#about to read 6, iclass 7, count 2 2006.173.19:24:30.68#ibcon#read 6, iclass 7, count 2 2006.173.19:24:30.68#ibcon#end of sib2, iclass 7, count 2 2006.173.19:24:30.68#ibcon#*after write, iclass 7, count 2 2006.173.19:24:30.68#ibcon#*before return 0, iclass 7, count 2 2006.173.19:24:30.68#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.19:24:30.68#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.173.19:24:30.68#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.173.19:24:30.68#ibcon#ireg 7 cls_cnt 0 2006.173.19:24:30.68#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.19:24:30.80#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.19:24:30.80#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.19:24:30.80#ibcon#enter wrdev, iclass 7, count 0 2006.173.19:24:30.80#ibcon#first serial, iclass 7, count 0 2006.173.19:24:30.80#ibcon#enter sib2, iclass 7, count 0 2006.173.19:24:30.80#ibcon#flushed, iclass 7, count 0 2006.173.19:24:30.80#ibcon#about to write, iclass 7, count 0 2006.173.19:24:30.80#ibcon#wrote, iclass 7, count 0 2006.173.19:24:30.80#ibcon#about to read 3, iclass 7, count 0 2006.173.19:24:30.82#ibcon#read 3, iclass 7, count 0 2006.173.19:24:30.82#ibcon#about to read 4, iclass 7, count 0 2006.173.19:24:30.82#ibcon#read 4, iclass 7, count 0 2006.173.19:24:30.82#ibcon#about to read 5, iclass 7, count 0 2006.173.19:24:30.82#ibcon#read 5, iclass 7, count 0 2006.173.19:24:30.82#ibcon#about to read 6, iclass 7, count 0 2006.173.19:24:30.82#ibcon#read 6, iclass 7, count 0 2006.173.19:24:30.82#ibcon#end of sib2, iclass 7, count 0 2006.173.19:24:30.82#ibcon#*mode == 0, iclass 7, count 0 2006.173.19:24:30.82#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.19:24:30.82#ibcon#[27=USB\r\n] 2006.173.19:24:30.82#ibcon#*before write, iclass 7, count 0 2006.173.19:24:30.82#ibcon#enter sib2, iclass 7, count 0 2006.173.19:24:30.82#ibcon#flushed, iclass 7, count 0 2006.173.19:24:30.82#ibcon#about to write, iclass 7, count 0 2006.173.19:24:30.82#ibcon#wrote, iclass 7, count 0 2006.173.19:24:30.82#ibcon#about to read 3, iclass 7, count 0 2006.173.19:24:30.85#ibcon#read 3, iclass 7, count 0 2006.173.19:24:30.85#ibcon#about to read 4, iclass 7, count 0 2006.173.19:24:30.85#ibcon#read 4, iclass 7, count 0 2006.173.19:24:30.85#ibcon#about to read 5, iclass 7, count 0 2006.173.19:24:30.85#ibcon#read 5, iclass 7, count 0 2006.173.19:24:30.85#ibcon#about to read 6, iclass 7, count 0 2006.173.19:24:30.85#ibcon#read 6, iclass 7, count 0 2006.173.19:24:30.85#ibcon#end of sib2, iclass 7, count 0 2006.173.19:24:30.85#ibcon#*after write, iclass 7, count 0 2006.173.19:24:30.85#ibcon#*before return 0, iclass 7, count 0 2006.173.19:24:30.85#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.19:24:30.85#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.173.19:24:30.85#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.19:24:30.85#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.19:24:30.85$vck44/vblo=4,679.99 2006.173.19:24:30.85#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.19:24:30.85#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.19:24:30.85#ibcon#ireg 17 cls_cnt 0 2006.173.19:24:30.85#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.19:24:30.85#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.19:24:30.85#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.19:24:30.85#ibcon#enter wrdev, iclass 11, count 0 2006.173.19:24:30.85#ibcon#first serial, iclass 11, count 0 2006.173.19:24:30.85#ibcon#enter sib2, iclass 11, count 0 2006.173.19:24:30.85#ibcon#flushed, iclass 11, count 0 2006.173.19:24:30.85#ibcon#about to write, iclass 11, count 0 2006.173.19:24:30.85#ibcon#wrote, iclass 11, count 0 2006.173.19:24:30.85#ibcon#about to read 3, iclass 11, count 0 2006.173.19:24:30.87#ibcon#read 3, iclass 11, count 0 2006.173.19:24:30.87#ibcon#about to read 4, iclass 11, count 0 2006.173.19:24:30.87#ibcon#read 4, iclass 11, count 0 2006.173.19:24:30.87#ibcon#about to read 5, iclass 11, count 0 2006.173.19:24:30.87#ibcon#read 5, iclass 11, count 0 2006.173.19:24:30.87#ibcon#about to read 6, iclass 11, count 0 2006.173.19:24:30.87#ibcon#read 6, iclass 11, count 0 2006.173.19:24:30.87#ibcon#end of sib2, iclass 11, count 0 2006.173.19:24:30.87#ibcon#*mode == 0, iclass 11, count 0 2006.173.19:24:30.87#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.19:24:30.87#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.19:24:30.87#ibcon#*before write, iclass 11, count 0 2006.173.19:24:30.87#ibcon#enter sib2, iclass 11, count 0 2006.173.19:24:30.87#ibcon#flushed, iclass 11, count 0 2006.173.19:24:30.87#ibcon#about to write, iclass 11, count 0 2006.173.19:24:30.87#ibcon#wrote, iclass 11, count 0 2006.173.19:24:30.87#ibcon#about to read 3, iclass 11, count 0 2006.173.19:24:30.91#ibcon#read 3, iclass 11, count 0 2006.173.19:24:30.91#ibcon#about to read 4, iclass 11, count 0 2006.173.19:24:30.91#ibcon#read 4, iclass 11, count 0 2006.173.19:24:30.91#ibcon#about to read 5, iclass 11, count 0 2006.173.19:24:30.91#ibcon#read 5, iclass 11, count 0 2006.173.19:24:30.91#ibcon#about to read 6, iclass 11, count 0 2006.173.19:24:30.91#ibcon#read 6, iclass 11, count 0 2006.173.19:24:30.91#ibcon#end of sib2, iclass 11, count 0 2006.173.19:24:30.91#ibcon#*after write, iclass 11, count 0 2006.173.19:24:30.91#ibcon#*before return 0, iclass 11, count 0 2006.173.19:24:30.91#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.19:24:30.91#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.19:24:30.91#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.19:24:30.91#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.19:24:30.91$vck44/vb=4,4 2006.173.19:24:30.91#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.173.19:24:30.91#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.173.19:24:30.91#ibcon#ireg 11 cls_cnt 2 2006.173.19:24:30.91#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.19:24:30.97#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.19:24:30.97#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.19:24:30.97#ibcon#enter wrdev, iclass 13, count 2 2006.173.19:24:30.97#ibcon#first serial, iclass 13, count 2 2006.173.19:24:30.97#ibcon#enter sib2, iclass 13, count 2 2006.173.19:24:30.97#ibcon#flushed, iclass 13, count 2 2006.173.19:24:30.97#ibcon#about to write, iclass 13, count 2 2006.173.19:24:30.97#ibcon#wrote, iclass 13, count 2 2006.173.19:24:30.97#ibcon#about to read 3, iclass 13, count 2 2006.173.19:24:30.99#ibcon#read 3, iclass 13, count 2 2006.173.19:24:30.99#ibcon#about to read 4, iclass 13, count 2 2006.173.19:24:30.99#ibcon#read 4, iclass 13, count 2 2006.173.19:24:30.99#ibcon#about to read 5, iclass 13, count 2 2006.173.19:24:30.99#ibcon#read 5, iclass 13, count 2 2006.173.19:24:30.99#ibcon#about to read 6, iclass 13, count 2 2006.173.19:24:30.99#ibcon#read 6, iclass 13, count 2 2006.173.19:24:30.99#ibcon#end of sib2, iclass 13, count 2 2006.173.19:24:30.99#ibcon#*mode == 0, iclass 13, count 2 2006.173.19:24:30.99#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.173.19:24:30.99#ibcon#[27=AT04-04\r\n] 2006.173.19:24:30.99#ibcon#*before write, iclass 13, count 2 2006.173.19:24:30.99#ibcon#enter sib2, iclass 13, count 2 2006.173.19:24:30.99#ibcon#flushed, iclass 13, count 2 2006.173.19:24:30.99#ibcon#about to write, iclass 13, count 2 2006.173.19:24:30.99#ibcon#wrote, iclass 13, count 2 2006.173.19:24:30.99#ibcon#about to read 3, iclass 13, count 2 2006.173.19:24:31.02#ibcon#read 3, iclass 13, count 2 2006.173.19:24:31.02#ibcon#about to read 4, iclass 13, count 2 2006.173.19:24:31.02#ibcon#read 4, iclass 13, count 2 2006.173.19:24:31.02#ibcon#about to read 5, iclass 13, count 2 2006.173.19:24:31.02#ibcon#read 5, iclass 13, count 2 2006.173.19:24:31.02#ibcon#about to read 6, iclass 13, count 2 2006.173.19:24:31.02#ibcon#read 6, iclass 13, count 2 2006.173.19:24:31.02#ibcon#end of sib2, iclass 13, count 2 2006.173.19:24:31.02#ibcon#*after write, iclass 13, count 2 2006.173.19:24:31.02#ibcon#*before return 0, iclass 13, count 2 2006.173.19:24:31.02#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.19:24:31.02#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.173.19:24:31.02#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.173.19:24:31.02#ibcon#ireg 7 cls_cnt 0 2006.173.19:24:31.02#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.19:24:31.14#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.19:24:31.14#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.19:24:31.14#ibcon#enter wrdev, iclass 13, count 0 2006.173.19:24:31.14#ibcon#first serial, iclass 13, count 0 2006.173.19:24:31.14#ibcon#enter sib2, iclass 13, count 0 2006.173.19:24:31.14#ibcon#flushed, iclass 13, count 0 2006.173.19:24:31.14#ibcon#about to write, iclass 13, count 0 2006.173.19:24:31.14#ibcon#wrote, iclass 13, count 0 2006.173.19:24:31.14#ibcon#about to read 3, iclass 13, count 0 2006.173.19:24:31.16#ibcon#read 3, iclass 13, count 0 2006.173.19:24:31.16#ibcon#about to read 4, iclass 13, count 0 2006.173.19:24:31.16#ibcon#read 4, iclass 13, count 0 2006.173.19:24:31.16#ibcon#about to read 5, iclass 13, count 0 2006.173.19:24:31.16#ibcon#read 5, iclass 13, count 0 2006.173.19:24:31.16#ibcon#about to read 6, iclass 13, count 0 2006.173.19:24:31.16#ibcon#read 6, iclass 13, count 0 2006.173.19:24:31.16#ibcon#end of sib2, iclass 13, count 0 2006.173.19:24:31.16#ibcon#*mode == 0, iclass 13, count 0 2006.173.19:24:31.16#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.19:24:31.16#ibcon#[27=USB\r\n] 2006.173.19:24:31.16#ibcon#*before write, iclass 13, count 0 2006.173.19:24:31.16#ibcon#enter sib2, iclass 13, count 0 2006.173.19:24:31.16#ibcon#flushed, iclass 13, count 0 2006.173.19:24:31.16#ibcon#about to write, iclass 13, count 0 2006.173.19:24:31.16#ibcon#wrote, iclass 13, count 0 2006.173.19:24:31.16#ibcon#about to read 3, iclass 13, count 0 2006.173.19:24:31.19#ibcon#read 3, iclass 13, count 0 2006.173.19:24:31.19#ibcon#about to read 4, iclass 13, count 0 2006.173.19:24:31.19#ibcon#read 4, iclass 13, count 0 2006.173.19:24:31.19#ibcon#about to read 5, iclass 13, count 0 2006.173.19:24:31.19#ibcon#read 5, iclass 13, count 0 2006.173.19:24:31.19#ibcon#about to read 6, iclass 13, count 0 2006.173.19:24:31.19#ibcon#read 6, iclass 13, count 0 2006.173.19:24:31.19#ibcon#end of sib2, iclass 13, count 0 2006.173.19:24:31.19#ibcon#*after write, iclass 13, count 0 2006.173.19:24:31.19#ibcon#*before return 0, iclass 13, count 0 2006.173.19:24:31.19#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.19:24:31.19#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.173.19:24:31.19#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.19:24:31.19#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.19:24:31.19$vck44/vblo=5,709.99 2006.173.19:24:31.19#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.19:24:31.19#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.19:24:31.19#ibcon#ireg 17 cls_cnt 0 2006.173.19:24:31.19#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.19:24:31.19#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.19:24:31.19#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.19:24:31.19#ibcon#enter wrdev, iclass 15, count 0 2006.173.19:24:31.19#ibcon#first serial, iclass 15, count 0 2006.173.19:24:31.19#ibcon#enter sib2, iclass 15, count 0 2006.173.19:24:31.19#ibcon#flushed, iclass 15, count 0 2006.173.19:24:31.19#ibcon#about to write, iclass 15, count 0 2006.173.19:24:31.19#ibcon#wrote, iclass 15, count 0 2006.173.19:24:31.19#ibcon#about to read 3, iclass 15, count 0 2006.173.19:24:31.21#ibcon#read 3, iclass 15, count 0 2006.173.19:24:31.21#ibcon#about to read 4, iclass 15, count 0 2006.173.19:24:31.21#ibcon#read 4, iclass 15, count 0 2006.173.19:24:31.21#ibcon#about to read 5, iclass 15, count 0 2006.173.19:24:31.21#ibcon#read 5, iclass 15, count 0 2006.173.19:24:31.21#ibcon#about to read 6, iclass 15, count 0 2006.173.19:24:31.21#ibcon#read 6, iclass 15, count 0 2006.173.19:24:31.21#ibcon#end of sib2, iclass 15, count 0 2006.173.19:24:31.21#ibcon#*mode == 0, iclass 15, count 0 2006.173.19:24:31.21#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.19:24:31.21#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.19:24:31.21#ibcon#*before write, iclass 15, count 0 2006.173.19:24:31.21#ibcon#enter sib2, iclass 15, count 0 2006.173.19:24:31.21#ibcon#flushed, iclass 15, count 0 2006.173.19:24:31.21#ibcon#about to write, iclass 15, count 0 2006.173.19:24:31.21#ibcon#wrote, iclass 15, count 0 2006.173.19:24:31.21#ibcon#about to read 3, iclass 15, count 0 2006.173.19:24:31.25#ibcon#read 3, iclass 15, count 0 2006.173.19:24:31.25#ibcon#about to read 4, iclass 15, count 0 2006.173.19:24:31.25#ibcon#read 4, iclass 15, count 0 2006.173.19:24:31.25#ibcon#about to read 5, iclass 15, count 0 2006.173.19:24:31.25#ibcon#read 5, iclass 15, count 0 2006.173.19:24:31.25#ibcon#about to read 6, iclass 15, count 0 2006.173.19:24:31.25#ibcon#read 6, iclass 15, count 0 2006.173.19:24:31.25#ibcon#end of sib2, iclass 15, count 0 2006.173.19:24:31.25#ibcon#*after write, iclass 15, count 0 2006.173.19:24:31.25#ibcon#*before return 0, iclass 15, count 0 2006.173.19:24:31.25#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.19:24:31.25#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.19:24:31.25#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.19:24:31.25#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.19:24:31.25$vck44/vb=5,4 2006.173.19:24:31.25#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.19:24:31.25#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.19:24:31.25#ibcon#ireg 11 cls_cnt 2 2006.173.19:24:31.25#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.19:24:31.31#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.19:24:31.31#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.19:24:31.31#ibcon#enter wrdev, iclass 17, count 2 2006.173.19:24:31.31#ibcon#first serial, iclass 17, count 2 2006.173.19:24:31.31#ibcon#enter sib2, iclass 17, count 2 2006.173.19:24:31.31#ibcon#flushed, iclass 17, count 2 2006.173.19:24:31.31#ibcon#about to write, iclass 17, count 2 2006.173.19:24:31.31#ibcon#wrote, iclass 17, count 2 2006.173.19:24:31.31#ibcon#about to read 3, iclass 17, count 2 2006.173.19:24:31.33#ibcon#read 3, iclass 17, count 2 2006.173.19:24:31.33#ibcon#about to read 4, iclass 17, count 2 2006.173.19:24:31.33#ibcon#read 4, iclass 17, count 2 2006.173.19:24:31.33#ibcon#about to read 5, iclass 17, count 2 2006.173.19:24:31.33#ibcon#read 5, iclass 17, count 2 2006.173.19:24:31.33#ibcon#about to read 6, iclass 17, count 2 2006.173.19:24:31.33#ibcon#read 6, iclass 17, count 2 2006.173.19:24:31.33#ibcon#end of sib2, iclass 17, count 2 2006.173.19:24:31.33#ibcon#*mode == 0, iclass 17, count 2 2006.173.19:24:31.33#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.19:24:31.33#ibcon#[27=AT05-04\r\n] 2006.173.19:24:31.33#ibcon#*before write, iclass 17, count 2 2006.173.19:24:31.33#ibcon#enter sib2, iclass 17, count 2 2006.173.19:24:31.33#ibcon#flushed, iclass 17, count 2 2006.173.19:24:31.33#ibcon#about to write, iclass 17, count 2 2006.173.19:24:31.33#ibcon#wrote, iclass 17, count 2 2006.173.19:24:31.33#ibcon#about to read 3, iclass 17, count 2 2006.173.19:24:31.36#ibcon#read 3, iclass 17, count 2 2006.173.19:24:31.36#ibcon#about to read 4, iclass 17, count 2 2006.173.19:24:31.36#ibcon#read 4, iclass 17, count 2 2006.173.19:24:31.36#ibcon#about to read 5, iclass 17, count 2 2006.173.19:24:31.36#ibcon#read 5, iclass 17, count 2 2006.173.19:24:31.36#ibcon#about to read 6, iclass 17, count 2 2006.173.19:24:31.36#ibcon#read 6, iclass 17, count 2 2006.173.19:24:31.36#ibcon#end of sib2, iclass 17, count 2 2006.173.19:24:31.36#ibcon#*after write, iclass 17, count 2 2006.173.19:24:31.36#ibcon#*before return 0, iclass 17, count 2 2006.173.19:24:31.36#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.19:24:31.36#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.19:24:31.36#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.19:24:31.36#ibcon#ireg 7 cls_cnt 0 2006.173.19:24:31.36#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.19:24:31.48#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.19:24:31.48#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.19:24:31.48#ibcon#enter wrdev, iclass 17, count 0 2006.173.19:24:31.48#ibcon#first serial, iclass 17, count 0 2006.173.19:24:31.48#ibcon#enter sib2, iclass 17, count 0 2006.173.19:24:31.48#ibcon#flushed, iclass 17, count 0 2006.173.19:24:31.48#ibcon#about to write, iclass 17, count 0 2006.173.19:24:31.48#ibcon#wrote, iclass 17, count 0 2006.173.19:24:31.48#ibcon#about to read 3, iclass 17, count 0 2006.173.19:24:31.50#ibcon#read 3, iclass 17, count 0 2006.173.19:24:31.50#ibcon#about to read 4, iclass 17, count 0 2006.173.19:24:31.50#ibcon#read 4, iclass 17, count 0 2006.173.19:24:31.50#ibcon#about to read 5, iclass 17, count 0 2006.173.19:24:31.50#ibcon#read 5, iclass 17, count 0 2006.173.19:24:31.50#ibcon#about to read 6, iclass 17, count 0 2006.173.19:24:31.50#ibcon#read 6, iclass 17, count 0 2006.173.19:24:31.50#ibcon#end of sib2, iclass 17, count 0 2006.173.19:24:31.50#ibcon#*mode == 0, iclass 17, count 0 2006.173.19:24:31.50#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.19:24:31.50#ibcon#[27=USB\r\n] 2006.173.19:24:31.50#ibcon#*before write, iclass 17, count 0 2006.173.19:24:31.50#ibcon#enter sib2, iclass 17, count 0 2006.173.19:24:31.50#ibcon#flushed, iclass 17, count 0 2006.173.19:24:31.50#ibcon#about to write, iclass 17, count 0 2006.173.19:24:31.50#ibcon#wrote, iclass 17, count 0 2006.173.19:24:31.50#ibcon#about to read 3, iclass 17, count 0 2006.173.19:24:31.53#ibcon#read 3, iclass 17, count 0 2006.173.19:24:31.53#ibcon#about to read 4, iclass 17, count 0 2006.173.19:24:31.53#ibcon#read 4, iclass 17, count 0 2006.173.19:24:31.53#ibcon#about to read 5, iclass 17, count 0 2006.173.19:24:31.53#ibcon#read 5, iclass 17, count 0 2006.173.19:24:31.53#ibcon#about to read 6, iclass 17, count 0 2006.173.19:24:31.53#ibcon#read 6, iclass 17, count 0 2006.173.19:24:31.53#ibcon#end of sib2, iclass 17, count 0 2006.173.19:24:31.53#ibcon#*after write, iclass 17, count 0 2006.173.19:24:31.53#ibcon#*before return 0, iclass 17, count 0 2006.173.19:24:31.53#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.19:24:31.53#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.19:24:31.53#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.19:24:31.53#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.19:24:31.53$vck44/vblo=6,719.99 2006.173.19:24:31.53#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.19:24:31.53#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.19:24:31.53#ibcon#ireg 17 cls_cnt 0 2006.173.19:24:31.53#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.19:24:31.53#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.19:24:31.53#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.19:24:31.53#ibcon#enter wrdev, iclass 19, count 0 2006.173.19:24:31.53#ibcon#first serial, iclass 19, count 0 2006.173.19:24:31.53#ibcon#enter sib2, iclass 19, count 0 2006.173.19:24:31.53#ibcon#flushed, iclass 19, count 0 2006.173.19:24:31.53#ibcon#about to write, iclass 19, count 0 2006.173.19:24:31.53#ibcon#wrote, iclass 19, count 0 2006.173.19:24:31.53#ibcon#about to read 3, iclass 19, count 0 2006.173.19:24:31.55#ibcon#read 3, iclass 19, count 0 2006.173.19:24:31.55#ibcon#about to read 4, iclass 19, count 0 2006.173.19:24:31.55#ibcon#read 4, iclass 19, count 0 2006.173.19:24:31.55#ibcon#about to read 5, iclass 19, count 0 2006.173.19:24:31.55#ibcon#read 5, iclass 19, count 0 2006.173.19:24:31.55#ibcon#about to read 6, iclass 19, count 0 2006.173.19:24:31.55#ibcon#read 6, iclass 19, count 0 2006.173.19:24:31.55#ibcon#end of sib2, iclass 19, count 0 2006.173.19:24:31.55#ibcon#*mode == 0, iclass 19, count 0 2006.173.19:24:31.55#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.19:24:31.55#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.19:24:31.55#ibcon#*before write, iclass 19, count 0 2006.173.19:24:31.55#ibcon#enter sib2, iclass 19, count 0 2006.173.19:24:31.55#ibcon#flushed, iclass 19, count 0 2006.173.19:24:31.55#ibcon#about to write, iclass 19, count 0 2006.173.19:24:31.55#ibcon#wrote, iclass 19, count 0 2006.173.19:24:31.55#ibcon#about to read 3, iclass 19, count 0 2006.173.19:24:31.59#ibcon#read 3, iclass 19, count 0 2006.173.19:24:31.59#ibcon#about to read 4, iclass 19, count 0 2006.173.19:24:31.59#ibcon#read 4, iclass 19, count 0 2006.173.19:24:31.59#ibcon#about to read 5, iclass 19, count 0 2006.173.19:24:31.59#ibcon#read 5, iclass 19, count 0 2006.173.19:24:31.59#ibcon#about to read 6, iclass 19, count 0 2006.173.19:24:31.59#ibcon#read 6, iclass 19, count 0 2006.173.19:24:31.59#ibcon#end of sib2, iclass 19, count 0 2006.173.19:24:31.59#ibcon#*after write, iclass 19, count 0 2006.173.19:24:31.59#ibcon#*before return 0, iclass 19, count 0 2006.173.19:24:31.59#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.19:24:31.59#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.19:24:31.59#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.19:24:31.59#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.19:24:31.59$vck44/vb=6,4 2006.173.19:24:31.59#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.19:24:31.59#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.19:24:31.59#ibcon#ireg 11 cls_cnt 2 2006.173.19:24:31.59#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.19:24:31.65#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.19:24:31.65#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.19:24:31.65#ibcon#enter wrdev, iclass 21, count 2 2006.173.19:24:31.65#ibcon#first serial, iclass 21, count 2 2006.173.19:24:31.65#ibcon#enter sib2, iclass 21, count 2 2006.173.19:24:31.65#ibcon#flushed, iclass 21, count 2 2006.173.19:24:31.65#ibcon#about to write, iclass 21, count 2 2006.173.19:24:31.65#ibcon#wrote, iclass 21, count 2 2006.173.19:24:31.65#ibcon#about to read 3, iclass 21, count 2 2006.173.19:24:31.67#ibcon#read 3, iclass 21, count 2 2006.173.19:24:31.67#ibcon#about to read 4, iclass 21, count 2 2006.173.19:24:31.67#ibcon#read 4, iclass 21, count 2 2006.173.19:24:31.67#ibcon#about to read 5, iclass 21, count 2 2006.173.19:24:31.67#ibcon#read 5, iclass 21, count 2 2006.173.19:24:31.67#ibcon#about to read 6, iclass 21, count 2 2006.173.19:24:31.67#ibcon#read 6, iclass 21, count 2 2006.173.19:24:31.67#ibcon#end of sib2, iclass 21, count 2 2006.173.19:24:31.67#ibcon#*mode == 0, iclass 21, count 2 2006.173.19:24:31.67#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.19:24:31.67#ibcon#[27=AT06-04\r\n] 2006.173.19:24:31.67#ibcon#*before write, iclass 21, count 2 2006.173.19:24:31.67#ibcon#enter sib2, iclass 21, count 2 2006.173.19:24:31.67#ibcon#flushed, iclass 21, count 2 2006.173.19:24:31.67#ibcon#about to write, iclass 21, count 2 2006.173.19:24:31.67#ibcon#wrote, iclass 21, count 2 2006.173.19:24:31.67#ibcon#about to read 3, iclass 21, count 2 2006.173.19:24:31.70#ibcon#read 3, iclass 21, count 2 2006.173.19:24:31.70#ibcon#about to read 4, iclass 21, count 2 2006.173.19:24:31.70#ibcon#read 4, iclass 21, count 2 2006.173.19:24:31.70#ibcon#about to read 5, iclass 21, count 2 2006.173.19:24:31.70#ibcon#read 5, iclass 21, count 2 2006.173.19:24:31.70#ibcon#about to read 6, iclass 21, count 2 2006.173.19:24:31.70#ibcon#read 6, iclass 21, count 2 2006.173.19:24:31.70#ibcon#end of sib2, iclass 21, count 2 2006.173.19:24:31.70#ibcon#*after write, iclass 21, count 2 2006.173.19:24:31.70#ibcon#*before return 0, iclass 21, count 2 2006.173.19:24:31.70#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.19:24:31.70#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.19:24:31.70#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.19:24:31.70#ibcon#ireg 7 cls_cnt 0 2006.173.19:24:31.70#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.19:24:31.82#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.19:24:31.82#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.19:24:31.82#ibcon#enter wrdev, iclass 21, count 0 2006.173.19:24:31.82#ibcon#first serial, iclass 21, count 0 2006.173.19:24:31.82#ibcon#enter sib2, iclass 21, count 0 2006.173.19:24:31.82#ibcon#flushed, iclass 21, count 0 2006.173.19:24:31.82#ibcon#about to write, iclass 21, count 0 2006.173.19:24:31.82#ibcon#wrote, iclass 21, count 0 2006.173.19:24:31.82#ibcon#about to read 3, iclass 21, count 0 2006.173.19:24:31.84#ibcon#read 3, iclass 21, count 0 2006.173.19:24:31.84#ibcon#about to read 4, iclass 21, count 0 2006.173.19:24:31.84#ibcon#read 4, iclass 21, count 0 2006.173.19:24:31.84#ibcon#about to read 5, iclass 21, count 0 2006.173.19:24:31.84#ibcon#read 5, iclass 21, count 0 2006.173.19:24:31.84#ibcon#about to read 6, iclass 21, count 0 2006.173.19:24:31.84#ibcon#read 6, iclass 21, count 0 2006.173.19:24:31.84#ibcon#end of sib2, iclass 21, count 0 2006.173.19:24:31.84#ibcon#*mode == 0, iclass 21, count 0 2006.173.19:24:31.84#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.19:24:31.84#ibcon#[27=USB\r\n] 2006.173.19:24:31.84#ibcon#*before write, iclass 21, count 0 2006.173.19:24:31.84#ibcon#enter sib2, iclass 21, count 0 2006.173.19:24:31.84#ibcon#flushed, iclass 21, count 0 2006.173.19:24:31.84#ibcon#about to write, iclass 21, count 0 2006.173.19:24:31.84#ibcon#wrote, iclass 21, count 0 2006.173.19:24:31.84#ibcon#about to read 3, iclass 21, count 0 2006.173.19:24:31.87#ibcon#read 3, iclass 21, count 0 2006.173.19:24:31.87#ibcon#about to read 4, iclass 21, count 0 2006.173.19:24:31.87#ibcon#read 4, iclass 21, count 0 2006.173.19:24:31.87#ibcon#about to read 5, iclass 21, count 0 2006.173.19:24:31.87#ibcon#read 5, iclass 21, count 0 2006.173.19:24:31.87#ibcon#about to read 6, iclass 21, count 0 2006.173.19:24:31.87#ibcon#read 6, iclass 21, count 0 2006.173.19:24:31.87#ibcon#end of sib2, iclass 21, count 0 2006.173.19:24:31.87#ibcon#*after write, iclass 21, count 0 2006.173.19:24:31.87#ibcon#*before return 0, iclass 21, count 0 2006.173.19:24:31.87#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.19:24:31.87#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.19:24:31.87#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.19:24:31.87#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.19:24:31.87$vck44/vblo=7,734.99 2006.173.19:24:31.87#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.19:24:31.87#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.19:24:31.87#ibcon#ireg 17 cls_cnt 0 2006.173.19:24:31.87#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.19:24:31.87#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.19:24:31.87#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.19:24:31.87#ibcon#enter wrdev, iclass 23, count 0 2006.173.19:24:31.87#ibcon#first serial, iclass 23, count 0 2006.173.19:24:31.87#ibcon#enter sib2, iclass 23, count 0 2006.173.19:24:31.87#ibcon#flushed, iclass 23, count 0 2006.173.19:24:31.87#ibcon#about to write, iclass 23, count 0 2006.173.19:24:31.87#ibcon#wrote, iclass 23, count 0 2006.173.19:24:31.87#ibcon#about to read 3, iclass 23, count 0 2006.173.19:24:31.89#ibcon#read 3, iclass 23, count 0 2006.173.19:24:31.89#ibcon#about to read 4, iclass 23, count 0 2006.173.19:24:31.89#ibcon#read 4, iclass 23, count 0 2006.173.19:24:31.89#ibcon#about to read 5, iclass 23, count 0 2006.173.19:24:31.89#ibcon#read 5, iclass 23, count 0 2006.173.19:24:31.89#ibcon#about to read 6, iclass 23, count 0 2006.173.19:24:31.89#ibcon#read 6, iclass 23, count 0 2006.173.19:24:31.89#ibcon#end of sib2, iclass 23, count 0 2006.173.19:24:31.89#ibcon#*mode == 0, iclass 23, count 0 2006.173.19:24:31.89#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.19:24:31.89#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.19:24:31.89#ibcon#*before write, iclass 23, count 0 2006.173.19:24:31.89#ibcon#enter sib2, iclass 23, count 0 2006.173.19:24:31.89#ibcon#flushed, iclass 23, count 0 2006.173.19:24:31.89#ibcon#about to write, iclass 23, count 0 2006.173.19:24:31.89#ibcon#wrote, iclass 23, count 0 2006.173.19:24:31.89#ibcon#about to read 3, iclass 23, count 0 2006.173.19:24:31.93#ibcon#read 3, iclass 23, count 0 2006.173.19:24:31.93#ibcon#about to read 4, iclass 23, count 0 2006.173.19:24:31.93#ibcon#read 4, iclass 23, count 0 2006.173.19:24:31.93#ibcon#about to read 5, iclass 23, count 0 2006.173.19:24:31.93#ibcon#read 5, iclass 23, count 0 2006.173.19:24:31.93#ibcon#about to read 6, iclass 23, count 0 2006.173.19:24:31.93#ibcon#read 6, iclass 23, count 0 2006.173.19:24:31.93#ibcon#end of sib2, iclass 23, count 0 2006.173.19:24:31.93#ibcon#*after write, iclass 23, count 0 2006.173.19:24:31.93#ibcon#*before return 0, iclass 23, count 0 2006.173.19:24:31.93#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.19:24:31.93#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.19:24:31.93#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.19:24:31.93#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.19:24:31.93$vck44/vb=7,4 2006.173.19:24:31.93#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.19:24:31.93#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.19:24:31.93#ibcon#ireg 11 cls_cnt 2 2006.173.19:24:31.93#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.19:24:31.99#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.19:24:31.99#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.19:24:31.99#ibcon#enter wrdev, iclass 25, count 2 2006.173.19:24:31.99#ibcon#first serial, iclass 25, count 2 2006.173.19:24:31.99#ibcon#enter sib2, iclass 25, count 2 2006.173.19:24:31.99#ibcon#flushed, iclass 25, count 2 2006.173.19:24:31.99#ibcon#about to write, iclass 25, count 2 2006.173.19:24:31.99#ibcon#wrote, iclass 25, count 2 2006.173.19:24:31.99#ibcon#about to read 3, iclass 25, count 2 2006.173.19:24:32.01#ibcon#read 3, iclass 25, count 2 2006.173.19:24:32.01#ibcon#about to read 4, iclass 25, count 2 2006.173.19:24:32.01#ibcon#read 4, iclass 25, count 2 2006.173.19:24:32.01#ibcon#about to read 5, iclass 25, count 2 2006.173.19:24:32.01#ibcon#read 5, iclass 25, count 2 2006.173.19:24:32.01#ibcon#about to read 6, iclass 25, count 2 2006.173.19:24:32.01#ibcon#read 6, iclass 25, count 2 2006.173.19:24:32.01#ibcon#end of sib2, iclass 25, count 2 2006.173.19:24:32.01#ibcon#*mode == 0, iclass 25, count 2 2006.173.19:24:32.01#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.19:24:32.01#ibcon#[27=AT07-04\r\n] 2006.173.19:24:32.01#ibcon#*before write, iclass 25, count 2 2006.173.19:24:32.01#ibcon#enter sib2, iclass 25, count 2 2006.173.19:24:32.01#ibcon#flushed, iclass 25, count 2 2006.173.19:24:32.01#ibcon#about to write, iclass 25, count 2 2006.173.19:24:32.01#ibcon#wrote, iclass 25, count 2 2006.173.19:24:32.01#ibcon#about to read 3, iclass 25, count 2 2006.173.19:24:32.04#ibcon#read 3, iclass 25, count 2 2006.173.19:24:32.04#ibcon#about to read 4, iclass 25, count 2 2006.173.19:24:32.04#ibcon#read 4, iclass 25, count 2 2006.173.19:24:32.04#ibcon#about to read 5, iclass 25, count 2 2006.173.19:24:32.04#ibcon#read 5, iclass 25, count 2 2006.173.19:24:32.04#ibcon#about to read 6, iclass 25, count 2 2006.173.19:24:32.04#ibcon#read 6, iclass 25, count 2 2006.173.19:24:32.04#ibcon#end of sib2, iclass 25, count 2 2006.173.19:24:32.04#ibcon#*after write, iclass 25, count 2 2006.173.19:24:32.04#ibcon#*before return 0, iclass 25, count 2 2006.173.19:24:32.04#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.19:24:32.04#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.19:24:32.04#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.19:24:32.04#ibcon#ireg 7 cls_cnt 0 2006.173.19:24:32.04#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.19:24:32.16#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.19:24:32.16#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.19:24:32.16#ibcon#enter wrdev, iclass 25, count 0 2006.173.19:24:32.16#ibcon#first serial, iclass 25, count 0 2006.173.19:24:32.16#ibcon#enter sib2, iclass 25, count 0 2006.173.19:24:32.16#ibcon#flushed, iclass 25, count 0 2006.173.19:24:32.16#ibcon#about to write, iclass 25, count 0 2006.173.19:24:32.16#ibcon#wrote, iclass 25, count 0 2006.173.19:24:32.16#ibcon#about to read 3, iclass 25, count 0 2006.173.19:24:32.18#ibcon#read 3, iclass 25, count 0 2006.173.19:24:32.18#ibcon#about to read 4, iclass 25, count 0 2006.173.19:24:32.18#ibcon#read 4, iclass 25, count 0 2006.173.19:24:32.18#ibcon#about to read 5, iclass 25, count 0 2006.173.19:24:32.18#ibcon#read 5, iclass 25, count 0 2006.173.19:24:32.18#ibcon#about to read 6, iclass 25, count 0 2006.173.19:24:32.18#ibcon#read 6, iclass 25, count 0 2006.173.19:24:32.18#ibcon#end of sib2, iclass 25, count 0 2006.173.19:24:32.18#ibcon#*mode == 0, iclass 25, count 0 2006.173.19:24:32.18#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.19:24:32.18#ibcon#[27=USB\r\n] 2006.173.19:24:32.18#ibcon#*before write, iclass 25, count 0 2006.173.19:24:32.18#ibcon#enter sib2, iclass 25, count 0 2006.173.19:24:32.18#ibcon#flushed, iclass 25, count 0 2006.173.19:24:32.18#ibcon#about to write, iclass 25, count 0 2006.173.19:24:32.18#ibcon#wrote, iclass 25, count 0 2006.173.19:24:32.18#ibcon#about to read 3, iclass 25, count 0 2006.173.19:24:32.21#ibcon#read 3, iclass 25, count 0 2006.173.19:24:32.21#ibcon#about to read 4, iclass 25, count 0 2006.173.19:24:32.21#ibcon#read 4, iclass 25, count 0 2006.173.19:24:32.21#ibcon#about to read 5, iclass 25, count 0 2006.173.19:24:32.21#ibcon#read 5, iclass 25, count 0 2006.173.19:24:32.21#ibcon#about to read 6, iclass 25, count 0 2006.173.19:24:32.21#ibcon#read 6, iclass 25, count 0 2006.173.19:24:32.21#ibcon#end of sib2, iclass 25, count 0 2006.173.19:24:32.21#ibcon#*after write, iclass 25, count 0 2006.173.19:24:32.21#ibcon#*before return 0, iclass 25, count 0 2006.173.19:24:32.21#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.19:24:32.21#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.19:24:32.21#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.19:24:32.21#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.19:24:32.21$vck44/vblo=8,744.99 2006.173.19:24:32.21#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.19:24:32.21#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.19:24:32.21#ibcon#ireg 17 cls_cnt 0 2006.173.19:24:32.21#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.19:24:32.21#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.19:24:32.21#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.19:24:32.21#ibcon#enter wrdev, iclass 27, count 0 2006.173.19:24:32.21#ibcon#first serial, iclass 27, count 0 2006.173.19:24:32.21#ibcon#enter sib2, iclass 27, count 0 2006.173.19:24:32.21#ibcon#flushed, iclass 27, count 0 2006.173.19:24:32.21#ibcon#about to write, iclass 27, count 0 2006.173.19:24:32.21#ibcon#wrote, iclass 27, count 0 2006.173.19:24:32.21#ibcon#about to read 3, iclass 27, count 0 2006.173.19:24:32.23#ibcon#read 3, iclass 27, count 0 2006.173.19:24:32.23#ibcon#about to read 4, iclass 27, count 0 2006.173.19:24:32.23#ibcon#read 4, iclass 27, count 0 2006.173.19:24:32.23#ibcon#about to read 5, iclass 27, count 0 2006.173.19:24:32.23#ibcon#read 5, iclass 27, count 0 2006.173.19:24:32.23#ibcon#about to read 6, iclass 27, count 0 2006.173.19:24:32.23#ibcon#read 6, iclass 27, count 0 2006.173.19:24:32.23#ibcon#end of sib2, iclass 27, count 0 2006.173.19:24:32.23#ibcon#*mode == 0, iclass 27, count 0 2006.173.19:24:32.23#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.19:24:32.23#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.19:24:32.23#ibcon#*before write, iclass 27, count 0 2006.173.19:24:32.23#ibcon#enter sib2, iclass 27, count 0 2006.173.19:24:32.23#ibcon#flushed, iclass 27, count 0 2006.173.19:24:32.23#ibcon#about to write, iclass 27, count 0 2006.173.19:24:32.23#ibcon#wrote, iclass 27, count 0 2006.173.19:24:32.23#ibcon#about to read 3, iclass 27, count 0 2006.173.19:24:32.27#ibcon#read 3, iclass 27, count 0 2006.173.19:24:32.27#ibcon#about to read 4, iclass 27, count 0 2006.173.19:24:32.27#ibcon#read 4, iclass 27, count 0 2006.173.19:24:32.27#ibcon#about to read 5, iclass 27, count 0 2006.173.19:24:32.27#ibcon#read 5, iclass 27, count 0 2006.173.19:24:32.27#ibcon#about to read 6, iclass 27, count 0 2006.173.19:24:32.27#ibcon#read 6, iclass 27, count 0 2006.173.19:24:32.27#ibcon#end of sib2, iclass 27, count 0 2006.173.19:24:32.27#ibcon#*after write, iclass 27, count 0 2006.173.19:24:32.27#ibcon#*before return 0, iclass 27, count 0 2006.173.19:24:32.27#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.19:24:32.27#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.19:24:32.27#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.19:24:32.27#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.19:24:32.27$vck44/vb=8,4 2006.173.19:24:32.27#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.19:24:32.27#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.19:24:32.27#ibcon#ireg 11 cls_cnt 2 2006.173.19:24:32.27#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.19:24:32.33#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.19:24:32.33#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.19:24:32.33#ibcon#enter wrdev, iclass 29, count 2 2006.173.19:24:32.33#ibcon#first serial, iclass 29, count 2 2006.173.19:24:32.33#ibcon#enter sib2, iclass 29, count 2 2006.173.19:24:32.33#ibcon#flushed, iclass 29, count 2 2006.173.19:24:32.33#ibcon#about to write, iclass 29, count 2 2006.173.19:24:32.33#ibcon#wrote, iclass 29, count 2 2006.173.19:24:32.33#ibcon#about to read 3, iclass 29, count 2 2006.173.19:24:32.35#ibcon#read 3, iclass 29, count 2 2006.173.19:24:32.35#ibcon#about to read 4, iclass 29, count 2 2006.173.19:24:32.35#ibcon#read 4, iclass 29, count 2 2006.173.19:24:32.35#ibcon#about to read 5, iclass 29, count 2 2006.173.19:24:32.35#ibcon#read 5, iclass 29, count 2 2006.173.19:24:32.35#ibcon#about to read 6, iclass 29, count 2 2006.173.19:24:32.35#ibcon#read 6, iclass 29, count 2 2006.173.19:24:32.35#ibcon#end of sib2, iclass 29, count 2 2006.173.19:24:32.35#ibcon#*mode == 0, iclass 29, count 2 2006.173.19:24:32.35#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.19:24:32.35#ibcon#[27=AT08-04\r\n] 2006.173.19:24:32.35#ibcon#*before write, iclass 29, count 2 2006.173.19:24:32.35#ibcon#enter sib2, iclass 29, count 2 2006.173.19:24:32.35#ibcon#flushed, iclass 29, count 2 2006.173.19:24:32.35#ibcon#about to write, iclass 29, count 2 2006.173.19:24:32.35#ibcon#wrote, iclass 29, count 2 2006.173.19:24:32.35#ibcon#about to read 3, iclass 29, count 2 2006.173.19:24:32.38#ibcon#read 3, iclass 29, count 2 2006.173.19:24:32.38#ibcon#about to read 4, iclass 29, count 2 2006.173.19:24:32.38#ibcon#read 4, iclass 29, count 2 2006.173.19:24:32.38#ibcon#about to read 5, iclass 29, count 2 2006.173.19:24:32.38#ibcon#read 5, iclass 29, count 2 2006.173.19:24:32.38#ibcon#about to read 6, iclass 29, count 2 2006.173.19:24:32.38#ibcon#read 6, iclass 29, count 2 2006.173.19:24:32.38#ibcon#end of sib2, iclass 29, count 2 2006.173.19:24:32.38#ibcon#*after write, iclass 29, count 2 2006.173.19:24:32.38#ibcon#*before return 0, iclass 29, count 2 2006.173.19:24:32.38#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.19:24:32.38#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.19:24:32.38#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.19:24:32.38#ibcon#ireg 7 cls_cnt 0 2006.173.19:24:32.38#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.19:24:32.50#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.19:24:32.50#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.19:24:32.50#ibcon#enter wrdev, iclass 29, count 0 2006.173.19:24:32.50#ibcon#first serial, iclass 29, count 0 2006.173.19:24:32.50#ibcon#enter sib2, iclass 29, count 0 2006.173.19:24:32.50#ibcon#flushed, iclass 29, count 0 2006.173.19:24:32.50#ibcon#about to write, iclass 29, count 0 2006.173.19:24:32.50#ibcon#wrote, iclass 29, count 0 2006.173.19:24:32.50#ibcon#about to read 3, iclass 29, count 0 2006.173.19:24:32.52#ibcon#read 3, iclass 29, count 0 2006.173.19:24:32.52#ibcon#about to read 4, iclass 29, count 0 2006.173.19:24:32.52#ibcon#read 4, iclass 29, count 0 2006.173.19:24:32.52#ibcon#about to read 5, iclass 29, count 0 2006.173.19:24:32.52#ibcon#read 5, iclass 29, count 0 2006.173.19:24:32.52#ibcon#about to read 6, iclass 29, count 0 2006.173.19:24:32.52#ibcon#read 6, iclass 29, count 0 2006.173.19:24:32.52#ibcon#end of sib2, iclass 29, count 0 2006.173.19:24:32.52#ibcon#*mode == 0, iclass 29, count 0 2006.173.19:24:32.52#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.19:24:32.52#ibcon#[27=USB\r\n] 2006.173.19:24:32.52#ibcon#*before write, iclass 29, count 0 2006.173.19:24:32.52#ibcon#enter sib2, iclass 29, count 0 2006.173.19:24:32.52#ibcon#flushed, iclass 29, count 0 2006.173.19:24:32.52#ibcon#about to write, iclass 29, count 0 2006.173.19:24:32.52#ibcon#wrote, iclass 29, count 0 2006.173.19:24:32.52#ibcon#about to read 3, iclass 29, count 0 2006.173.19:24:32.55#ibcon#read 3, iclass 29, count 0 2006.173.19:24:32.55#ibcon#about to read 4, iclass 29, count 0 2006.173.19:24:32.55#ibcon#read 4, iclass 29, count 0 2006.173.19:24:32.55#ibcon#about to read 5, iclass 29, count 0 2006.173.19:24:32.55#ibcon#read 5, iclass 29, count 0 2006.173.19:24:32.55#ibcon#about to read 6, iclass 29, count 0 2006.173.19:24:32.55#ibcon#read 6, iclass 29, count 0 2006.173.19:24:32.55#ibcon#end of sib2, iclass 29, count 0 2006.173.19:24:32.55#ibcon#*after write, iclass 29, count 0 2006.173.19:24:32.55#ibcon#*before return 0, iclass 29, count 0 2006.173.19:24:32.55#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.19:24:32.55#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.19:24:32.55#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.19:24:32.55#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.19:24:32.55$vck44/vabw=wide 2006.173.19:24:32.55#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.19:24:32.55#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.19:24:32.55#ibcon#ireg 8 cls_cnt 0 2006.173.19:24:32.55#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.19:24:32.55#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.19:24:32.55#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.19:24:32.55#ibcon#enter wrdev, iclass 31, count 0 2006.173.19:24:32.55#ibcon#first serial, iclass 31, count 0 2006.173.19:24:32.55#ibcon#enter sib2, iclass 31, count 0 2006.173.19:24:32.55#ibcon#flushed, iclass 31, count 0 2006.173.19:24:32.55#ibcon#about to write, iclass 31, count 0 2006.173.19:24:32.55#ibcon#wrote, iclass 31, count 0 2006.173.19:24:32.55#ibcon#about to read 3, iclass 31, count 0 2006.173.19:24:32.57#ibcon#read 3, iclass 31, count 0 2006.173.19:24:32.57#ibcon#about to read 4, iclass 31, count 0 2006.173.19:24:32.57#ibcon#read 4, iclass 31, count 0 2006.173.19:24:32.57#ibcon#about to read 5, iclass 31, count 0 2006.173.19:24:32.57#ibcon#read 5, iclass 31, count 0 2006.173.19:24:32.57#ibcon#about to read 6, iclass 31, count 0 2006.173.19:24:32.57#ibcon#read 6, iclass 31, count 0 2006.173.19:24:32.57#ibcon#end of sib2, iclass 31, count 0 2006.173.19:24:32.57#ibcon#*mode == 0, iclass 31, count 0 2006.173.19:24:32.57#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.19:24:32.57#ibcon#[25=BW32\r\n] 2006.173.19:24:32.57#ibcon#*before write, iclass 31, count 0 2006.173.19:24:32.57#ibcon#enter sib2, iclass 31, count 0 2006.173.19:24:32.57#ibcon#flushed, iclass 31, count 0 2006.173.19:24:32.57#ibcon#about to write, iclass 31, count 0 2006.173.19:24:32.57#ibcon#wrote, iclass 31, count 0 2006.173.19:24:32.57#ibcon#about to read 3, iclass 31, count 0 2006.173.19:24:32.60#ibcon#read 3, iclass 31, count 0 2006.173.19:24:32.60#ibcon#about to read 4, iclass 31, count 0 2006.173.19:24:32.60#ibcon#read 4, iclass 31, count 0 2006.173.19:24:32.60#ibcon#about to read 5, iclass 31, count 0 2006.173.19:24:32.60#ibcon#read 5, iclass 31, count 0 2006.173.19:24:32.60#ibcon#about to read 6, iclass 31, count 0 2006.173.19:24:32.60#ibcon#read 6, iclass 31, count 0 2006.173.19:24:32.60#ibcon#end of sib2, iclass 31, count 0 2006.173.19:24:32.60#ibcon#*after write, iclass 31, count 0 2006.173.19:24:32.60#ibcon#*before return 0, iclass 31, count 0 2006.173.19:24:32.60#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.19:24:32.60#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.19:24:32.60#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.19:24:32.60#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.19:24:32.60$vck44/vbbw=wide 2006.173.19:24:32.60#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.19:24:32.60#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.19:24:32.60#ibcon#ireg 8 cls_cnt 0 2006.173.19:24:32.60#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.19:24:32.67#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.19:24:32.67#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.19:24:32.67#ibcon#enter wrdev, iclass 33, count 0 2006.173.19:24:32.67#ibcon#first serial, iclass 33, count 0 2006.173.19:24:32.67#ibcon#enter sib2, iclass 33, count 0 2006.173.19:24:32.67#ibcon#flushed, iclass 33, count 0 2006.173.19:24:32.67#ibcon#about to write, iclass 33, count 0 2006.173.19:24:32.67#ibcon#wrote, iclass 33, count 0 2006.173.19:24:32.67#ibcon#about to read 3, iclass 33, count 0 2006.173.19:24:32.69#ibcon#read 3, iclass 33, count 0 2006.173.19:24:32.69#ibcon#about to read 4, iclass 33, count 0 2006.173.19:24:32.69#ibcon#read 4, iclass 33, count 0 2006.173.19:24:32.69#ibcon#about to read 5, iclass 33, count 0 2006.173.19:24:32.69#ibcon#read 5, iclass 33, count 0 2006.173.19:24:32.69#ibcon#about to read 6, iclass 33, count 0 2006.173.19:24:32.69#ibcon#read 6, iclass 33, count 0 2006.173.19:24:32.69#ibcon#end of sib2, iclass 33, count 0 2006.173.19:24:32.69#ibcon#*mode == 0, iclass 33, count 0 2006.173.19:24:32.69#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.19:24:32.69#ibcon#[27=BW32\r\n] 2006.173.19:24:32.69#ibcon#*before write, iclass 33, count 0 2006.173.19:24:32.69#ibcon#enter sib2, iclass 33, count 0 2006.173.19:24:32.69#ibcon#flushed, iclass 33, count 0 2006.173.19:24:32.69#ibcon#about to write, iclass 33, count 0 2006.173.19:24:32.69#ibcon#wrote, iclass 33, count 0 2006.173.19:24:32.69#ibcon#about to read 3, iclass 33, count 0 2006.173.19:24:32.72#ibcon#read 3, iclass 33, count 0 2006.173.19:24:32.72#ibcon#about to read 4, iclass 33, count 0 2006.173.19:24:32.72#ibcon#read 4, iclass 33, count 0 2006.173.19:24:32.72#ibcon#about to read 5, iclass 33, count 0 2006.173.19:24:32.72#ibcon#read 5, iclass 33, count 0 2006.173.19:24:32.72#ibcon#about to read 6, iclass 33, count 0 2006.173.19:24:32.72#ibcon#read 6, iclass 33, count 0 2006.173.19:24:32.72#ibcon#end of sib2, iclass 33, count 0 2006.173.19:24:32.72#ibcon#*after write, iclass 33, count 0 2006.173.19:24:32.72#ibcon#*before return 0, iclass 33, count 0 2006.173.19:24:32.72#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.19:24:32.72#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.19:24:32.72#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.19:24:32.72#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.19:24:32.72$setupk4/ifdk4 2006.173.19:24:32.72$ifdk4/lo= 2006.173.19:24:32.72$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.19:24:32.72$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.19:24:32.72$ifdk4/patch= 2006.173.19:24:32.72$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.19:24:32.72$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.19:24:32.72$setupk4/!*+20s 2006.173.19:24:35.37#abcon#<5=/05 0.6 1.3 19.471001002.5\r\n> 2006.173.19:24:35.39#abcon#{5=INTERFACE CLEAR} 2006.173.19:24:35.45#abcon#[5=S1D000X0/0*\r\n] 2006.173.19:24:45.54#abcon#<5=/05 0.6 1.2 19.471001002.5\r\n> 2006.173.19:24:45.56#abcon#{5=INTERFACE CLEAR} 2006.173.19:24:45.62#abcon#[5=S1D000X0/0*\r\n] 2006.173.19:24:47.23$setupk4/"tpicd 2006.173.19:24:47.23$setupk4/echo=off 2006.173.19:24:47.23$setupk4/xlog=off 2006.173.19:24:47.23:!2006.173.19:26:12 2006.173.19:24:49.14#trakl#Source acquired 2006.173.19:24:49.14#flagr#flagr/antenna,acquired 2006.173.19:26:12.00:preob 2006.173.19:26:12.14/onsource/TRACKING 2006.173.19:26:12.14:!2006.173.19:26:22 2006.173.19:26:22.00:"tape 2006.173.19:26:22.00:"st=record 2006.173.19:26:22.00:data_valid=on 2006.173.19:26:22.00:midob 2006.173.19:26:22.14/onsource/TRACKING 2006.173.19:26:22.14/wx/19.45,1002.4,100 2006.173.19:26:22.29/cable/+6.5180E-03 2006.173.19:26:23.38/va/01,07,usb,yes,35,37 2006.173.19:26:23.38/va/02,06,usb,yes,35,35 2006.173.19:26:23.38/va/03,05,usb,yes,44,46 2006.173.19:26:23.38/va/04,06,usb,yes,35,37 2006.173.19:26:23.38/va/05,04,usb,yes,28,28 2006.173.19:26:23.38/va/06,03,usb,yes,39,39 2006.173.19:26:23.38/va/07,04,usb,yes,31,32 2006.173.19:26:23.38/va/08,04,usb,yes,27,32 2006.173.19:26:23.61/valo/01,524.99,yes,locked 2006.173.19:26:23.61/valo/02,534.99,yes,locked 2006.173.19:26:23.61/valo/03,564.99,yes,locked 2006.173.19:26:23.61/valo/04,624.99,yes,locked 2006.173.19:26:23.61/valo/05,734.99,yes,locked 2006.173.19:26:23.61/valo/06,814.99,yes,locked 2006.173.19:26:23.61/valo/07,864.99,yes,locked 2006.173.19:26:23.61/valo/08,884.99,yes,locked 2006.173.19:26:24.70/vb/01,04,usb,yes,28,26 2006.173.19:26:24.70/vb/02,04,usb,yes,31,31 2006.173.19:26:24.70/vb/03,04,usb,yes,28,31 2006.173.19:26:24.70/vb/04,04,usb,yes,32,31 2006.173.19:26:24.70/vb/05,04,usb,yes,25,27 2006.173.19:26:24.70/vb/06,04,usb,yes,29,25 2006.173.19:26:24.70/vb/07,04,usb,yes,29,29 2006.173.19:26:24.70/vb/08,04,usb,yes,27,30 2006.173.19:26:24.93/vblo/01,629.99,yes,locked 2006.173.19:26:24.93/vblo/02,634.99,yes,locked 2006.173.19:26:24.93/vblo/03,649.99,yes,locked 2006.173.19:26:24.93/vblo/04,679.99,yes,locked 2006.173.19:26:24.93/vblo/05,709.99,yes,locked 2006.173.19:26:24.93/vblo/06,719.99,yes,locked 2006.173.19:26:24.93/vblo/07,734.99,yes,locked 2006.173.19:26:24.93/vblo/08,744.99,yes,locked 2006.173.19:26:25.08/vabw/8 2006.173.19:26:25.23/vbbw/8 2006.173.19:26:25.32/xfe/off,on,14.7 2006.173.19:26:25.72/ifatt/23,28,28,28 2006.173.19:26:26.07/fmout-gps/S +3.89E-07 2006.173.19:26:26.11:!2006.173.19:27:42 2006.173.19:27:42.01:data_valid=off 2006.173.19:27:42.01:"et 2006.173.19:27:42.01:!+3s 2006.173.19:27:45.02:"tape 2006.173.19:27:45.02:postob 2006.173.19:27:45.12/cable/+6.5152E-03 2006.173.19:27:45.12/wx/19.44,1002.4,100 2006.173.19:27:45.18/fmout-gps/S +3.88E-07 2006.173.19:27:45.18:scan_name=173-1931,jd0606,40 2006.173.19:27:45.18:source=3c454.3,225357.75,160853.6,2000.0,ccw 2006.173.19:27:46.14#flagr#flagr/antenna,new-source 2006.173.19:27:46.14:checkk5 2006.173.19:27:46.55/chk_autoobs//k5ts1/ autoobs is running! 2006.173.19:27:46.95/chk_autoobs//k5ts2/ autoobs is running! 2006.173.19:27:47.37/chk_autoobs//k5ts3/ autoobs is running! 2006.173.19:27:47.77/chk_autoobs//k5ts4/ autoobs is running! 2006.173.19:27:48.15/chk_obsdata//k5ts1/T1731926??a.dat file size is correct (nominal:320MB, actual:320MB). 2006.173.19:27:48.55/chk_obsdata//k5ts2/T1731926??b.dat file size is correct (nominal:320MB, actual:320MB). 2006.173.19:27:48.93/chk_obsdata//k5ts3/T1731926??c.dat file size is correct (nominal:320MB, actual:320MB). 2006.173.19:27:49.32/chk_obsdata//k5ts4/T1731926??d.dat file size is correct (nominal:320MB, actual:320MB). 2006.173.19:27:50.05/k5log//k5ts1_log_newline 2006.173.19:27:50.75/k5log//k5ts2_log_newline 2006.173.19:27:51.45/k5log//k5ts3_log_newline 2006.173.19:27:52.15/k5log//k5ts4_log_newline 2006.173.19:27:52.18/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.19:27:52.18:setupk4=1 2006.173.19:27:52.18$setupk4/echo=on 2006.173.19:27:52.18$setupk4/pcalon 2006.173.19:27:52.18$pcalon/"no phase cal control is implemented here 2006.173.19:27:52.18$setupk4/"tpicd=stop 2006.173.19:27:52.18$setupk4/"rec=synch_on 2006.173.19:27:52.18$setupk4/"rec_mode=128 2006.173.19:27:52.18$setupk4/!* 2006.173.19:27:52.18$setupk4/recpk4 2006.173.19:27:52.18$recpk4/recpatch= 2006.173.19:27:52.19$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.19:27:52.19$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.19:27:52.19$setupk4/vck44 2006.173.19:27:52.19$vck44/valo=1,524.99 2006.173.19:27:52.19#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.19:27:52.19#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.19:27:52.19#ibcon#ireg 17 cls_cnt 0 2006.173.19:27:52.19#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.19:27:52.19#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.19:27:52.19#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.19:27:52.19#ibcon#enter wrdev, iclass 10, count 0 2006.173.19:27:52.19#ibcon#first serial, iclass 10, count 0 2006.173.19:27:52.19#ibcon#enter sib2, iclass 10, count 0 2006.173.19:27:52.19#ibcon#flushed, iclass 10, count 0 2006.173.19:27:52.19#ibcon#about to write, iclass 10, count 0 2006.173.19:27:52.19#ibcon#wrote, iclass 10, count 0 2006.173.19:27:52.19#ibcon#about to read 3, iclass 10, count 0 2006.173.19:27:52.20#ibcon#read 3, iclass 10, count 0 2006.173.19:27:52.20#ibcon#about to read 4, iclass 10, count 0 2006.173.19:27:52.20#ibcon#read 4, iclass 10, count 0 2006.173.19:27:52.20#ibcon#about to read 5, iclass 10, count 0 2006.173.19:27:52.20#ibcon#read 5, iclass 10, count 0 2006.173.19:27:52.20#ibcon#about to read 6, iclass 10, count 0 2006.173.19:27:52.20#ibcon#read 6, iclass 10, count 0 2006.173.19:27:52.20#ibcon#end of sib2, iclass 10, count 0 2006.173.19:27:52.20#ibcon#*mode == 0, iclass 10, count 0 2006.173.19:27:52.20#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.19:27:52.20#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.19:27:52.20#ibcon#*before write, iclass 10, count 0 2006.173.19:27:52.20#ibcon#enter sib2, iclass 10, count 0 2006.173.19:27:52.20#ibcon#flushed, iclass 10, count 0 2006.173.19:27:52.20#ibcon#about to write, iclass 10, count 0 2006.173.19:27:52.20#ibcon#wrote, iclass 10, count 0 2006.173.19:27:52.20#ibcon#about to read 3, iclass 10, count 0 2006.173.19:27:52.25#ibcon#read 3, iclass 10, count 0 2006.173.19:27:52.25#ibcon#about to read 4, iclass 10, count 0 2006.173.19:27:52.25#ibcon#read 4, iclass 10, count 0 2006.173.19:27:52.25#ibcon#about to read 5, iclass 10, count 0 2006.173.19:27:52.25#ibcon#read 5, iclass 10, count 0 2006.173.19:27:52.25#ibcon#about to read 6, iclass 10, count 0 2006.173.19:27:52.25#ibcon#read 6, iclass 10, count 0 2006.173.19:27:52.25#ibcon#end of sib2, iclass 10, count 0 2006.173.19:27:52.25#ibcon#*after write, iclass 10, count 0 2006.173.19:27:52.25#ibcon#*before return 0, iclass 10, count 0 2006.173.19:27:52.25#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.19:27:52.25#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.19:27:52.25#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.19:27:52.25#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.19:27:52.25$vck44/va=1,7 2006.173.19:27:52.25#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.19:27:52.25#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.19:27:52.25#ibcon#ireg 11 cls_cnt 2 2006.173.19:27:52.25#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.19:27:52.25#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.19:27:52.25#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.19:27:52.25#ibcon#enter wrdev, iclass 12, count 2 2006.173.19:27:52.25#ibcon#first serial, iclass 12, count 2 2006.173.19:27:52.25#ibcon#enter sib2, iclass 12, count 2 2006.173.19:27:52.25#ibcon#flushed, iclass 12, count 2 2006.173.19:27:52.25#ibcon#about to write, iclass 12, count 2 2006.173.19:27:52.25#ibcon#wrote, iclass 12, count 2 2006.173.19:27:52.25#ibcon#about to read 3, iclass 12, count 2 2006.173.19:27:52.27#ibcon#read 3, iclass 12, count 2 2006.173.19:27:52.27#ibcon#about to read 4, iclass 12, count 2 2006.173.19:27:52.27#ibcon#read 4, iclass 12, count 2 2006.173.19:27:52.27#ibcon#about to read 5, iclass 12, count 2 2006.173.19:27:52.27#ibcon#read 5, iclass 12, count 2 2006.173.19:27:52.27#ibcon#about to read 6, iclass 12, count 2 2006.173.19:27:52.27#ibcon#read 6, iclass 12, count 2 2006.173.19:27:52.27#ibcon#end of sib2, iclass 12, count 2 2006.173.19:27:52.27#ibcon#*mode == 0, iclass 12, count 2 2006.173.19:27:52.27#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.19:27:52.27#ibcon#[25=AT01-07\r\n] 2006.173.19:27:52.27#ibcon#*before write, iclass 12, count 2 2006.173.19:27:52.27#ibcon#enter sib2, iclass 12, count 2 2006.173.19:27:52.27#ibcon#flushed, iclass 12, count 2 2006.173.19:27:52.27#ibcon#about to write, iclass 12, count 2 2006.173.19:27:52.27#ibcon#wrote, iclass 12, count 2 2006.173.19:27:52.27#ibcon#about to read 3, iclass 12, count 2 2006.173.19:27:52.30#ibcon#read 3, iclass 12, count 2 2006.173.19:27:52.30#ibcon#about to read 4, iclass 12, count 2 2006.173.19:27:52.30#ibcon#read 4, iclass 12, count 2 2006.173.19:27:52.30#ibcon#about to read 5, iclass 12, count 2 2006.173.19:27:52.30#ibcon#read 5, iclass 12, count 2 2006.173.19:27:52.30#ibcon#about to read 6, iclass 12, count 2 2006.173.19:27:52.30#ibcon#read 6, iclass 12, count 2 2006.173.19:27:52.30#ibcon#end of sib2, iclass 12, count 2 2006.173.19:27:52.30#ibcon#*after write, iclass 12, count 2 2006.173.19:27:52.30#ibcon#*before return 0, iclass 12, count 2 2006.173.19:27:52.30#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.19:27:52.30#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.19:27:52.30#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.19:27:52.30#ibcon#ireg 7 cls_cnt 0 2006.173.19:27:52.30#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.19:27:52.42#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.19:27:52.42#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.19:27:52.42#ibcon#enter wrdev, iclass 12, count 0 2006.173.19:27:52.42#ibcon#first serial, iclass 12, count 0 2006.173.19:27:52.42#ibcon#enter sib2, iclass 12, count 0 2006.173.19:27:52.42#ibcon#flushed, iclass 12, count 0 2006.173.19:27:52.42#ibcon#about to write, iclass 12, count 0 2006.173.19:27:52.42#ibcon#wrote, iclass 12, count 0 2006.173.19:27:52.42#ibcon#about to read 3, iclass 12, count 0 2006.173.19:27:52.44#ibcon#read 3, iclass 12, count 0 2006.173.19:27:52.44#ibcon#about to read 4, iclass 12, count 0 2006.173.19:27:52.44#ibcon#read 4, iclass 12, count 0 2006.173.19:27:52.44#ibcon#about to read 5, iclass 12, count 0 2006.173.19:27:52.44#ibcon#read 5, iclass 12, count 0 2006.173.19:27:52.44#ibcon#about to read 6, iclass 12, count 0 2006.173.19:27:52.44#ibcon#read 6, iclass 12, count 0 2006.173.19:27:52.44#ibcon#end of sib2, iclass 12, count 0 2006.173.19:27:52.44#ibcon#*mode == 0, iclass 12, count 0 2006.173.19:27:52.44#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.19:27:52.44#ibcon#[25=USB\r\n] 2006.173.19:27:52.44#ibcon#*before write, iclass 12, count 0 2006.173.19:27:52.44#ibcon#enter sib2, iclass 12, count 0 2006.173.19:27:52.44#ibcon#flushed, iclass 12, count 0 2006.173.19:27:52.44#ibcon#about to write, iclass 12, count 0 2006.173.19:27:52.44#ibcon#wrote, iclass 12, count 0 2006.173.19:27:52.44#ibcon#about to read 3, iclass 12, count 0 2006.173.19:27:52.47#ibcon#read 3, iclass 12, count 0 2006.173.19:27:52.47#ibcon#about to read 4, iclass 12, count 0 2006.173.19:27:52.47#ibcon#read 4, iclass 12, count 0 2006.173.19:27:52.47#ibcon#about to read 5, iclass 12, count 0 2006.173.19:27:52.47#ibcon#read 5, iclass 12, count 0 2006.173.19:27:52.47#ibcon#about to read 6, iclass 12, count 0 2006.173.19:27:52.47#ibcon#read 6, iclass 12, count 0 2006.173.19:27:52.47#ibcon#end of sib2, iclass 12, count 0 2006.173.19:27:52.47#ibcon#*after write, iclass 12, count 0 2006.173.19:27:52.47#ibcon#*before return 0, iclass 12, count 0 2006.173.19:27:52.47#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.19:27:52.47#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.19:27:52.47#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.19:27:52.47#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.19:27:52.47$vck44/valo=2,534.99 2006.173.19:27:52.47#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.19:27:52.47#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.19:27:52.47#ibcon#ireg 17 cls_cnt 0 2006.173.19:27:52.47#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.19:27:52.47#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.19:27:52.47#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.19:27:52.47#ibcon#enter wrdev, iclass 14, count 0 2006.173.19:27:52.47#ibcon#first serial, iclass 14, count 0 2006.173.19:27:52.47#ibcon#enter sib2, iclass 14, count 0 2006.173.19:27:52.47#ibcon#flushed, iclass 14, count 0 2006.173.19:27:52.47#ibcon#about to write, iclass 14, count 0 2006.173.19:27:52.47#ibcon#wrote, iclass 14, count 0 2006.173.19:27:52.47#ibcon#about to read 3, iclass 14, count 0 2006.173.19:27:52.49#ibcon#read 3, iclass 14, count 0 2006.173.19:27:52.49#ibcon#about to read 4, iclass 14, count 0 2006.173.19:27:52.49#ibcon#read 4, iclass 14, count 0 2006.173.19:27:52.49#ibcon#about to read 5, iclass 14, count 0 2006.173.19:27:52.49#ibcon#read 5, iclass 14, count 0 2006.173.19:27:52.49#ibcon#about to read 6, iclass 14, count 0 2006.173.19:27:52.49#ibcon#read 6, iclass 14, count 0 2006.173.19:27:52.49#ibcon#end of sib2, iclass 14, count 0 2006.173.19:27:52.49#ibcon#*mode == 0, iclass 14, count 0 2006.173.19:27:52.49#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.19:27:52.49#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.19:27:52.49#ibcon#*before write, iclass 14, count 0 2006.173.19:27:52.49#ibcon#enter sib2, iclass 14, count 0 2006.173.19:27:52.49#ibcon#flushed, iclass 14, count 0 2006.173.19:27:52.49#ibcon#about to write, iclass 14, count 0 2006.173.19:27:52.49#ibcon#wrote, iclass 14, count 0 2006.173.19:27:52.49#ibcon#about to read 3, iclass 14, count 0 2006.173.19:27:52.53#ibcon#read 3, iclass 14, count 0 2006.173.19:27:52.53#ibcon#about to read 4, iclass 14, count 0 2006.173.19:27:52.53#ibcon#read 4, iclass 14, count 0 2006.173.19:27:52.53#ibcon#about to read 5, iclass 14, count 0 2006.173.19:27:52.53#ibcon#read 5, iclass 14, count 0 2006.173.19:27:52.53#ibcon#about to read 6, iclass 14, count 0 2006.173.19:27:52.53#ibcon#read 6, iclass 14, count 0 2006.173.19:27:52.53#ibcon#end of sib2, iclass 14, count 0 2006.173.19:27:52.53#ibcon#*after write, iclass 14, count 0 2006.173.19:27:52.53#ibcon#*before return 0, iclass 14, count 0 2006.173.19:27:52.53#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.19:27:52.53#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.19:27:52.53#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.19:27:52.53#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.19:27:52.53$vck44/va=2,6 2006.173.19:27:52.53#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.19:27:52.53#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.19:27:52.53#ibcon#ireg 11 cls_cnt 2 2006.173.19:27:52.53#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.19:27:52.59#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.19:27:52.59#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.19:27:52.59#ibcon#enter wrdev, iclass 16, count 2 2006.173.19:27:52.59#ibcon#first serial, iclass 16, count 2 2006.173.19:27:52.59#ibcon#enter sib2, iclass 16, count 2 2006.173.19:27:52.59#ibcon#flushed, iclass 16, count 2 2006.173.19:27:52.59#ibcon#about to write, iclass 16, count 2 2006.173.19:27:52.59#ibcon#wrote, iclass 16, count 2 2006.173.19:27:52.59#ibcon#about to read 3, iclass 16, count 2 2006.173.19:27:52.61#ibcon#read 3, iclass 16, count 2 2006.173.19:27:52.61#ibcon#about to read 4, iclass 16, count 2 2006.173.19:27:52.61#ibcon#read 4, iclass 16, count 2 2006.173.19:27:52.61#ibcon#about to read 5, iclass 16, count 2 2006.173.19:27:52.61#ibcon#read 5, iclass 16, count 2 2006.173.19:27:52.61#ibcon#about to read 6, iclass 16, count 2 2006.173.19:27:52.61#ibcon#read 6, iclass 16, count 2 2006.173.19:27:52.61#ibcon#end of sib2, iclass 16, count 2 2006.173.19:27:52.61#ibcon#*mode == 0, iclass 16, count 2 2006.173.19:27:52.61#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.19:27:52.61#ibcon#[25=AT02-06\r\n] 2006.173.19:27:52.61#ibcon#*before write, iclass 16, count 2 2006.173.19:27:52.61#ibcon#enter sib2, iclass 16, count 2 2006.173.19:27:52.61#ibcon#flushed, iclass 16, count 2 2006.173.19:27:52.61#ibcon#about to write, iclass 16, count 2 2006.173.19:27:52.61#ibcon#wrote, iclass 16, count 2 2006.173.19:27:52.61#ibcon#about to read 3, iclass 16, count 2 2006.173.19:27:52.64#ibcon#read 3, iclass 16, count 2 2006.173.19:27:52.64#ibcon#about to read 4, iclass 16, count 2 2006.173.19:27:52.64#ibcon#read 4, iclass 16, count 2 2006.173.19:27:52.64#ibcon#about to read 5, iclass 16, count 2 2006.173.19:27:52.64#ibcon#read 5, iclass 16, count 2 2006.173.19:27:52.64#ibcon#about to read 6, iclass 16, count 2 2006.173.19:27:52.64#ibcon#read 6, iclass 16, count 2 2006.173.19:27:52.64#ibcon#end of sib2, iclass 16, count 2 2006.173.19:27:52.64#ibcon#*after write, iclass 16, count 2 2006.173.19:27:52.64#ibcon#*before return 0, iclass 16, count 2 2006.173.19:27:52.64#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.19:27:52.64#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.19:27:52.64#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.19:27:52.64#ibcon#ireg 7 cls_cnt 0 2006.173.19:27:52.64#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.19:27:52.76#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.19:27:52.76#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.19:27:52.76#ibcon#enter wrdev, iclass 16, count 0 2006.173.19:27:52.76#ibcon#first serial, iclass 16, count 0 2006.173.19:27:52.76#ibcon#enter sib2, iclass 16, count 0 2006.173.19:27:52.76#ibcon#flushed, iclass 16, count 0 2006.173.19:27:52.76#ibcon#about to write, iclass 16, count 0 2006.173.19:27:52.76#ibcon#wrote, iclass 16, count 0 2006.173.19:27:52.76#ibcon#about to read 3, iclass 16, count 0 2006.173.19:27:52.78#ibcon#read 3, iclass 16, count 0 2006.173.19:27:52.78#ibcon#about to read 4, iclass 16, count 0 2006.173.19:27:52.78#ibcon#read 4, iclass 16, count 0 2006.173.19:27:52.78#ibcon#about to read 5, iclass 16, count 0 2006.173.19:27:52.78#ibcon#read 5, iclass 16, count 0 2006.173.19:27:52.78#ibcon#about to read 6, iclass 16, count 0 2006.173.19:27:52.78#ibcon#read 6, iclass 16, count 0 2006.173.19:27:52.78#ibcon#end of sib2, iclass 16, count 0 2006.173.19:27:52.78#ibcon#*mode == 0, iclass 16, count 0 2006.173.19:27:52.78#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.19:27:52.78#ibcon#[25=USB\r\n] 2006.173.19:27:52.78#ibcon#*before write, iclass 16, count 0 2006.173.19:27:52.78#ibcon#enter sib2, iclass 16, count 0 2006.173.19:27:52.78#ibcon#flushed, iclass 16, count 0 2006.173.19:27:52.78#ibcon#about to write, iclass 16, count 0 2006.173.19:27:52.78#ibcon#wrote, iclass 16, count 0 2006.173.19:27:52.78#ibcon#about to read 3, iclass 16, count 0 2006.173.19:27:52.81#ibcon#read 3, iclass 16, count 0 2006.173.19:27:52.81#ibcon#about to read 4, iclass 16, count 0 2006.173.19:27:52.81#ibcon#read 4, iclass 16, count 0 2006.173.19:27:52.81#ibcon#about to read 5, iclass 16, count 0 2006.173.19:27:52.81#ibcon#read 5, iclass 16, count 0 2006.173.19:27:52.81#ibcon#about to read 6, iclass 16, count 0 2006.173.19:27:52.81#ibcon#read 6, iclass 16, count 0 2006.173.19:27:52.81#ibcon#end of sib2, iclass 16, count 0 2006.173.19:27:52.81#ibcon#*after write, iclass 16, count 0 2006.173.19:27:52.81#ibcon#*before return 0, iclass 16, count 0 2006.173.19:27:52.81#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.19:27:52.81#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.19:27:52.81#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.19:27:52.81#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.19:27:52.81$vck44/valo=3,564.99 2006.173.19:27:52.81#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.19:27:52.81#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.19:27:52.81#ibcon#ireg 17 cls_cnt 0 2006.173.19:27:52.81#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.19:27:52.81#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.19:27:52.81#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.19:27:52.81#ibcon#enter wrdev, iclass 18, count 0 2006.173.19:27:52.81#ibcon#first serial, iclass 18, count 0 2006.173.19:27:52.81#ibcon#enter sib2, iclass 18, count 0 2006.173.19:27:52.81#ibcon#flushed, iclass 18, count 0 2006.173.19:27:52.81#ibcon#about to write, iclass 18, count 0 2006.173.19:27:52.81#ibcon#wrote, iclass 18, count 0 2006.173.19:27:52.81#ibcon#about to read 3, iclass 18, count 0 2006.173.19:27:52.83#ibcon#read 3, iclass 18, count 0 2006.173.19:27:52.83#ibcon#about to read 4, iclass 18, count 0 2006.173.19:27:52.83#ibcon#read 4, iclass 18, count 0 2006.173.19:27:52.83#ibcon#about to read 5, iclass 18, count 0 2006.173.19:27:52.83#ibcon#read 5, iclass 18, count 0 2006.173.19:27:52.83#ibcon#about to read 6, iclass 18, count 0 2006.173.19:27:52.83#ibcon#read 6, iclass 18, count 0 2006.173.19:27:52.83#ibcon#end of sib2, iclass 18, count 0 2006.173.19:27:52.83#ibcon#*mode == 0, iclass 18, count 0 2006.173.19:27:52.83#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.19:27:52.83#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.19:27:52.83#ibcon#*before write, iclass 18, count 0 2006.173.19:27:52.83#ibcon#enter sib2, iclass 18, count 0 2006.173.19:27:52.83#ibcon#flushed, iclass 18, count 0 2006.173.19:27:52.83#ibcon#about to write, iclass 18, count 0 2006.173.19:27:52.83#ibcon#wrote, iclass 18, count 0 2006.173.19:27:52.83#ibcon#about to read 3, iclass 18, count 0 2006.173.19:27:52.87#ibcon#read 3, iclass 18, count 0 2006.173.19:27:52.87#ibcon#about to read 4, iclass 18, count 0 2006.173.19:27:52.87#ibcon#read 4, iclass 18, count 0 2006.173.19:27:52.87#ibcon#about to read 5, iclass 18, count 0 2006.173.19:27:52.87#ibcon#read 5, iclass 18, count 0 2006.173.19:27:52.87#ibcon#about to read 6, iclass 18, count 0 2006.173.19:27:52.87#ibcon#read 6, iclass 18, count 0 2006.173.19:27:52.87#ibcon#end of sib2, iclass 18, count 0 2006.173.19:27:52.87#ibcon#*after write, iclass 18, count 0 2006.173.19:27:52.87#ibcon#*before return 0, iclass 18, count 0 2006.173.19:27:52.87#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.19:27:52.87#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.19:27:52.87#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.19:27:52.87#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.19:27:52.87$vck44/va=3,5 2006.173.19:27:52.87#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.19:27:52.87#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.19:27:52.87#ibcon#ireg 11 cls_cnt 2 2006.173.19:27:52.87#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.19:27:52.93#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.19:27:52.93#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.19:27:52.93#ibcon#enter wrdev, iclass 20, count 2 2006.173.19:27:52.93#ibcon#first serial, iclass 20, count 2 2006.173.19:27:52.93#ibcon#enter sib2, iclass 20, count 2 2006.173.19:27:52.93#ibcon#flushed, iclass 20, count 2 2006.173.19:27:52.93#ibcon#about to write, iclass 20, count 2 2006.173.19:27:52.93#ibcon#wrote, iclass 20, count 2 2006.173.19:27:52.93#ibcon#about to read 3, iclass 20, count 2 2006.173.19:27:52.95#ibcon#read 3, iclass 20, count 2 2006.173.19:27:52.95#ibcon#about to read 4, iclass 20, count 2 2006.173.19:27:52.95#ibcon#read 4, iclass 20, count 2 2006.173.19:27:52.95#ibcon#about to read 5, iclass 20, count 2 2006.173.19:27:52.95#ibcon#read 5, iclass 20, count 2 2006.173.19:27:52.95#ibcon#about to read 6, iclass 20, count 2 2006.173.19:27:52.95#ibcon#read 6, iclass 20, count 2 2006.173.19:27:52.95#ibcon#end of sib2, iclass 20, count 2 2006.173.19:27:52.95#ibcon#*mode == 0, iclass 20, count 2 2006.173.19:27:52.95#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.19:27:52.95#ibcon#[25=AT03-05\r\n] 2006.173.19:27:52.95#ibcon#*before write, iclass 20, count 2 2006.173.19:27:52.95#ibcon#enter sib2, iclass 20, count 2 2006.173.19:27:52.95#ibcon#flushed, iclass 20, count 2 2006.173.19:27:52.95#ibcon#about to write, iclass 20, count 2 2006.173.19:27:52.95#ibcon#wrote, iclass 20, count 2 2006.173.19:27:52.95#ibcon#about to read 3, iclass 20, count 2 2006.173.19:27:52.98#ibcon#read 3, iclass 20, count 2 2006.173.19:27:52.98#ibcon#about to read 4, iclass 20, count 2 2006.173.19:27:52.98#ibcon#read 4, iclass 20, count 2 2006.173.19:27:52.98#ibcon#about to read 5, iclass 20, count 2 2006.173.19:27:52.98#ibcon#read 5, iclass 20, count 2 2006.173.19:27:52.98#ibcon#about to read 6, iclass 20, count 2 2006.173.19:27:52.98#ibcon#read 6, iclass 20, count 2 2006.173.19:27:52.98#ibcon#end of sib2, iclass 20, count 2 2006.173.19:27:52.98#ibcon#*after write, iclass 20, count 2 2006.173.19:27:52.98#ibcon#*before return 0, iclass 20, count 2 2006.173.19:27:52.98#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.19:27:52.98#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.19:27:52.98#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.19:27:52.98#ibcon#ireg 7 cls_cnt 0 2006.173.19:27:52.98#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.19:27:53.10#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.19:27:53.10#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.19:27:53.10#ibcon#enter wrdev, iclass 20, count 0 2006.173.19:27:53.10#ibcon#first serial, iclass 20, count 0 2006.173.19:27:53.10#ibcon#enter sib2, iclass 20, count 0 2006.173.19:27:53.10#ibcon#flushed, iclass 20, count 0 2006.173.19:27:53.10#ibcon#about to write, iclass 20, count 0 2006.173.19:27:53.10#ibcon#wrote, iclass 20, count 0 2006.173.19:27:53.10#ibcon#about to read 3, iclass 20, count 0 2006.173.19:27:53.12#ibcon#read 3, iclass 20, count 0 2006.173.19:27:53.12#ibcon#about to read 4, iclass 20, count 0 2006.173.19:27:53.12#ibcon#read 4, iclass 20, count 0 2006.173.19:27:53.12#ibcon#about to read 5, iclass 20, count 0 2006.173.19:27:53.12#ibcon#read 5, iclass 20, count 0 2006.173.19:27:53.12#ibcon#about to read 6, iclass 20, count 0 2006.173.19:27:53.12#ibcon#read 6, iclass 20, count 0 2006.173.19:27:53.12#ibcon#end of sib2, iclass 20, count 0 2006.173.19:27:53.12#ibcon#*mode == 0, iclass 20, count 0 2006.173.19:27:53.12#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.19:27:53.12#ibcon#[25=USB\r\n] 2006.173.19:27:53.12#ibcon#*before write, iclass 20, count 0 2006.173.19:27:53.12#ibcon#enter sib2, iclass 20, count 0 2006.173.19:27:53.12#ibcon#flushed, iclass 20, count 0 2006.173.19:27:53.12#ibcon#about to write, iclass 20, count 0 2006.173.19:27:53.12#ibcon#wrote, iclass 20, count 0 2006.173.19:27:53.12#ibcon#about to read 3, iclass 20, count 0 2006.173.19:27:53.15#ibcon#read 3, iclass 20, count 0 2006.173.19:27:53.15#ibcon#about to read 4, iclass 20, count 0 2006.173.19:27:53.15#ibcon#read 4, iclass 20, count 0 2006.173.19:27:53.15#ibcon#about to read 5, iclass 20, count 0 2006.173.19:27:53.15#ibcon#read 5, iclass 20, count 0 2006.173.19:27:53.15#ibcon#about to read 6, iclass 20, count 0 2006.173.19:27:53.15#ibcon#read 6, iclass 20, count 0 2006.173.19:27:53.15#ibcon#end of sib2, iclass 20, count 0 2006.173.19:27:53.15#ibcon#*after write, iclass 20, count 0 2006.173.19:27:53.15#ibcon#*before return 0, iclass 20, count 0 2006.173.19:27:53.15#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.19:27:53.15#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.19:27:53.15#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.19:27:53.15#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.19:27:53.15$vck44/valo=4,624.99 2006.173.19:27:53.15#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.19:27:53.15#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.19:27:53.15#ibcon#ireg 17 cls_cnt 0 2006.173.19:27:53.15#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.19:27:53.15#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.19:27:53.15#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.19:27:53.15#ibcon#enter wrdev, iclass 22, count 0 2006.173.19:27:53.15#ibcon#first serial, iclass 22, count 0 2006.173.19:27:53.15#ibcon#enter sib2, iclass 22, count 0 2006.173.19:27:53.15#ibcon#flushed, iclass 22, count 0 2006.173.19:27:53.15#ibcon#about to write, iclass 22, count 0 2006.173.19:27:53.15#ibcon#wrote, iclass 22, count 0 2006.173.19:27:53.15#ibcon#about to read 3, iclass 22, count 0 2006.173.19:27:53.17#ibcon#read 3, iclass 22, count 0 2006.173.19:27:53.17#ibcon#about to read 4, iclass 22, count 0 2006.173.19:27:53.17#ibcon#read 4, iclass 22, count 0 2006.173.19:27:53.17#ibcon#about to read 5, iclass 22, count 0 2006.173.19:27:53.17#ibcon#read 5, iclass 22, count 0 2006.173.19:27:53.17#ibcon#about to read 6, iclass 22, count 0 2006.173.19:27:53.17#ibcon#read 6, iclass 22, count 0 2006.173.19:27:53.17#ibcon#end of sib2, iclass 22, count 0 2006.173.19:27:53.17#ibcon#*mode == 0, iclass 22, count 0 2006.173.19:27:53.17#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.19:27:53.17#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.19:27:53.17#ibcon#*before write, iclass 22, count 0 2006.173.19:27:53.17#ibcon#enter sib2, iclass 22, count 0 2006.173.19:27:53.17#ibcon#flushed, iclass 22, count 0 2006.173.19:27:53.17#ibcon#about to write, iclass 22, count 0 2006.173.19:27:53.17#ibcon#wrote, iclass 22, count 0 2006.173.19:27:53.17#ibcon#about to read 3, iclass 22, count 0 2006.173.19:27:53.21#ibcon#read 3, iclass 22, count 0 2006.173.19:27:53.21#ibcon#about to read 4, iclass 22, count 0 2006.173.19:27:53.21#ibcon#read 4, iclass 22, count 0 2006.173.19:27:53.21#ibcon#about to read 5, iclass 22, count 0 2006.173.19:27:53.21#ibcon#read 5, iclass 22, count 0 2006.173.19:27:53.21#ibcon#about to read 6, iclass 22, count 0 2006.173.19:27:53.21#ibcon#read 6, iclass 22, count 0 2006.173.19:27:53.21#ibcon#end of sib2, iclass 22, count 0 2006.173.19:27:53.21#ibcon#*after write, iclass 22, count 0 2006.173.19:27:53.21#ibcon#*before return 0, iclass 22, count 0 2006.173.19:27:53.21#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.19:27:53.21#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.19:27:53.21#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.19:27:53.21#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.19:27:53.21$vck44/va=4,6 2006.173.19:27:53.21#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.19:27:53.21#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.19:27:53.21#ibcon#ireg 11 cls_cnt 2 2006.173.19:27:53.21#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.19:27:53.27#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.19:27:53.27#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.19:27:53.27#ibcon#enter wrdev, iclass 24, count 2 2006.173.19:27:53.27#ibcon#first serial, iclass 24, count 2 2006.173.19:27:53.27#ibcon#enter sib2, iclass 24, count 2 2006.173.19:27:53.27#ibcon#flushed, iclass 24, count 2 2006.173.19:27:53.27#ibcon#about to write, iclass 24, count 2 2006.173.19:27:53.27#ibcon#wrote, iclass 24, count 2 2006.173.19:27:53.27#ibcon#about to read 3, iclass 24, count 2 2006.173.19:27:53.29#ibcon#read 3, iclass 24, count 2 2006.173.19:27:53.29#ibcon#about to read 4, iclass 24, count 2 2006.173.19:27:53.29#ibcon#read 4, iclass 24, count 2 2006.173.19:27:53.29#ibcon#about to read 5, iclass 24, count 2 2006.173.19:27:53.29#ibcon#read 5, iclass 24, count 2 2006.173.19:27:53.29#ibcon#about to read 6, iclass 24, count 2 2006.173.19:27:53.29#ibcon#read 6, iclass 24, count 2 2006.173.19:27:53.29#ibcon#end of sib2, iclass 24, count 2 2006.173.19:27:53.29#ibcon#*mode == 0, iclass 24, count 2 2006.173.19:27:53.29#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.19:27:53.29#ibcon#[25=AT04-06\r\n] 2006.173.19:27:53.29#ibcon#*before write, iclass 24, count 2 2006.173.19:27:53.29#ibcon#enter sib2, iclass 24, count 2 2006.173.19:27:53.29#ibcon#flushed, iclass 24, count 2 2006.173.19:27:53.29#ibcon#about to write, iclass 24, count 2 2006.173.19:27:53.29#ibcon#wrote, iclass 24, count 2 2006.173.19:27:53.29#ibcon#about to read 3, iclass 24, count 2 2006.173.19:27:53.32#ibcon#read 3, iclass 24, count 2 2006.173.19:27:53.32#ibcon#about to read 4, iclass 24, count 2 2006.173.19:27:53.32#ibcon#read 4, iclass 24, count 2 2006.173.19:27:53.32#ibcon#about to read 5, iclass 24, count 2 2006.173.19:27:53.32#ibcon#read 5, iclass 24, count 2 2006.173.19:27:53.32#ibcon#about to read 6, iclass 24, count 2 2006.173.19:27:53.32#ibcon#read 6, iclass 24, count 2 2006.173.19:27:53.32#ibcon#end of sib2, iclass 24, count 2 2006.173.19:27:53.32#ibcon#*after write, iclass 24, count 2 2006.173.19:27:53.32#ibcon#*before return 0, iclass 24, count 2 2006.173.19:27:53.32#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.19:27:53.32#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.19:27:53.32#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.19:27:53.32#ibcon#ireg 7 cls_cnt 0 2006.173.19:27:53.32#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.19:27:53.44#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.19:27:53.44#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.19:27:53.44#ibcon#enter wrdev, iclass 24, count 0 2006.173.19:27:53.44#ibcon#first serial, iclass 24, count 0 2006.173.19:27:53.44#ibcon#enter sib2, iclass 24, count 0 2006.173.19:27:53.44#ibcon#flushed, iclass 24, count 0 2006.173.19:27:53.44#ibcon#about to write, iclass 24, count 0 2006.173.19:27:53.44#ibcon#wrote, iclass 24, count 0 2006.173.19:27:53.44#ibcon#about to read 3, iclass 24, count 0 2006.173.19:27:53.46#ibcon#read 3, iclass 24, count 0 2006.173.19:27:53.46#ibcon#about to read 4, iclass 24, count 0 2006.173.19:27:53.46#ibcon#read 4, iclass 24, count 0 2006.173.19:27:53.46#ibcon#about to read 5, iclass 24, count 0 2006.173.19:27:53.46#ibcon#read 5, iclass 24, count 0 2006.173.19:27:53.46#ibcon#about to read 6, iclass 24, count 0 2006.173.19:27:53.46#ibcon#read 6, iclass 24, count 0 2006.173.19:27:53.46#ibcon#end of sib2, iclass 24, count 0 2006.173.19:27:53.46#ibcon#*mode == 0, iclass 24, count 0 2006.173.19:27:53.46#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.19:27:53.46#ibcon#[25=USB\r\n] 2006.173.19:27:53.46#ibcon#*before write, iclass 24, count 0 2006.173.19:27:53.46#ibcon#enter sib2, iclass 24, count 0 2006.173.19:27:53.46#ibcon#flushed, iclass 24, count 0 2006.173.19:27:53.46#ibcon#about to write, iclass 24, count 0 2006.173.19:27:53.46#ibcon#wrote, iclass 24, count 0 2006.173.19:27:53.46#ibcon#about to read 3, iclass 24, count 0 2006.173.19:27:53.49#ibcon#read 3, iclass 24, count 0 2006.173.19:27:53.49#ibcon#about to read 4, iclass 24, count 0 2006.173.19:27:53.49#ibcon#read 4, iclass 24, count 0 2006.173.19:27:53.49#ibcon#about to read 5, iclass 24, count 0 2006.173.19:27:53.49#ibcon#read 5, iclass 24, count 0 2006.173.19:27:53.49#ibcon#about to read 6, iclass 24, count 0 2006.173.19:27:53.49#ibcon#read 6, iclass 24, count 0 2006.173.19:27:53.49#ibcon#end of sib2, iclass 24, count 0 2006.173.19:27:53.49#ibcon#*after write, iclass 24, count 0 2006.173.19:27:53.49#ibcon#*before return 0, iclass 24, count 0 2006.173.19:27:53.49#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.19:27:53.49#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.19:27:53.49#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.19:27:53.49#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.19:27:53.49$vck44/valo=5,734.99 2006.173.19:27:53.49#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.19:27:53.49#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.19:27:53.49#ibcon#ireg 17 cls_cnt 0 2006.173.19:27:53.49#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.19:27:53.49#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.19:27:53.49#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.19:27:53.49#ibcon#enter wrdev, iclass 26, count 0 2006.173.19:27:53.49#ibcon#first serial, iclass 26, count 0 2006.173.19:27:53.49#ibcon#enter sib2, iclass 26, count 0 2006.173.19:27:53.49#ibcon#flushed, iclass 26, count 0 2006.173.19:27:53.49#ibcon#about to write, iclass 26, count 0 2006.173.19:27:53.49#ibcon#wrote, iclass 26, count 0 2006.173.19:27:53.49#ibcon#about to read 3, iclass 26, count 0 2006.173.19:27:53.51#ibcon#read 3, iclass 26, count 0 2006.173.19:27:53.51#ibcon#about to read 4, iclass 26, count 0 2006.173.19:27:53.51#ibcon#read 4, iclass 26, count 0 2006.173.19:27:53.51#ibcon#about to read 5, iclass 26, count 0 2006.173.19:27:53.51#ibcon#read 5, iclass 26, count 0 2006.173.19:27:53.51#ibcon#about to read 6, iclass 26, count 0 2006.173.19:27:53.51#ibcon#read 6, iclass 26, count 0 2006.173.19:27:53.51#ibcon#end of sib2, iclass 26, count 0 2006.173.19:27:53.51#ibcon#*mode == 0, iclass 26, count 0 2006.173.19:27:53.51#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.19:27:53.51#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.19:27:53.51#ibcon#*before write, iclass 26, count 0 2006.173.19:27:53.51#ibcon#enter sib2, iclass 26, count 0 2006.173.19:27:53.51#ibcon#flushed, iclass 26, count 0 2006.173.19:27:53.51#ibcon#about to write, iclass 26, count 0 2006.173.19:27:53.51#ibcon#wrote, iclass 26, count 0 2006.173.19:27:53.51#ibcon#about to read 3, iclass 26, count 0 2006.173.19:27:53.55#ibcon#read 3, iclass 26, count 0 2006.173.19:27:53.55#ibcon#about to read 4, iclass 26, count 0 2006.173.19:27:53.55#ibcon#read 4, iclass 26, count 0 2006.173.19:27:53.55#ibcon#about to read 5, iclass 26, count 0 2006.173.19:27:53.55#ibcon#read 5, iclass 26, count 0 2006.173.19:27:53.55#ibcon#about to read 6, iclass 26, count 0 2006.173.19:27:53.55#ibcon#read 6, iclass 26, count 0 2006.173.19:27:53.55#ibcon#end of sib2, iclass 26, count 0 2006.173.19:27:53.55#ibcon#*after write, iclass 26, count 0 2006.173.19:27:53.55#ibcon#*before return 0, iclass 26, count 0 2006.173.19:27:53.55#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.19:27:53.55#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.19:27:53.55#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.19:27:53.55#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.19:27:53.55$vck44/va=5,4 2006.173.19:27:53.55#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.19:27:53.55#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.19:27:53.55#ibcon#ireg 11 cls_cnt 2 2006.173.19:27:53.55#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.19:27:53.61#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.19:27:53.61#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.19:27:53.61#ibcon#enter wrdev, iclass 28, count 2 2006.173.19:27:53.61#ibcon#first serial, iclass 28, count 2 2006.173.19:27:53.61#ibcon#enter sib2, iclass 28, count 2 2006.173.19:27:53.61#ibcon#flushed, iclass 28, count 2 2006.173.19:27:53.61#ibcon#about to write, iclass 28, count 2 2006.173.19:27:53.61#ibcon#wrote, iclass 28, count 2 2006.173.19:27:53.61#ibcon#about to read 3, iclass 28, count 2 2006.173.19:27:53.63#ibcon#read 3, iclass 28, count 2 2006.173.19:27:53.63#ibcon#about to read 4, iclass 28, count 2 2006.173.19:27:53.63#ibcon#read 4, iclass 28, count 2 2006.173.19:27:53.63#ibcon#about to read 5, iclass 28, count 2 2006.173.19:27:53.63#ibcon#read 5, iclass 28, count 2 2006.173.19:27:53.63#ibcon#about to read 6, iclass 28, count 2 2006.173.19:27:53.63#ibcon#read 6, iclass 28, count 2 2006.173.19:27:53.63#ibcon#end of sib2, iclass 28, count 2 2006.173.19:27:53.63#ibcon#*mode == 0, iclass 28, count 2 2006.173.19:27:53.63#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.19:27:53.63#ibcon#[25=AT05-04\r\n] 2006.173.19:27:53.63#ibcon#*before write, iclass 28, count 2 2006.173.19:27:53.63#ibcon#enter sib2, iclass 28, count 2 2006.173.19:27:53.63#ibcon#flushed, iclass 28, count 2 2006.173.19:27:53.63#ibcon#about to write, iclass 28, count 2 2006.173.19:27:53.63#ibcon#wrote, iclass 28, count 2 2006.173.19:27:53.63#ibcon#about to read 3, iclass 28, count 2 2006.173.19:27:53.66#ibcon#read 3, iclass 28, count 2 2006.173.19:27:53.66#ibcon#about to read 4, iclass 28, count 2 2006.173.19:27:53.66#ibcon#read 4, iclass 28, count 2 2006.173.19:27:53.66#ibcon#about to read 5, iclass 28, count 2 2006.173.19:27:53.66#ibcon#read 5, iclass 28, count 2 2006.173.19:27:53.66#ibcon#about to read 6, iclass 28, count 2 2006.173.19:27:53.66#ibcon#read 6, iclass 28, count 2 2006.173.19:27:53.66#ibcon#end of sib2, iclass 28, count 2 2006.173.19:27:53.66#ibcon#*after write, iclass 28, count 2 2006.173.19:27:53.66#ibcon#*before return 0, iclass 28, count 2 2006.173.19:27:53.66#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.19:27:53.66#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.19:27:53.66#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.19:27:53.66#ibcon#ireg 7 cls_cnt 0 2006.173.19:27:53.66#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.19:27:53.78#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.19:27:53.78#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.19:27:53.78#ibcon#enter wrdev, iclass 28, count 0 2006.173.19:27:53.78#ibcon#first serial, iclass 28, count 0 2006.173.19:27:53.78#ibcon#enter sib2, iclass 28, count 0 2006.173.19:27:53.78#ibcon#flushed, iclass 28, count 0 2006.173.19:27:53.78#ibcon#about to write, iclass 28, count 0 2006.173.19:27:53.78#ibcon#wrote, iclass 28, count 0 2006.173.19:27:53.78#ibcon#about to read 3, iclass 28, count 0 2006.173.19:27:53.80#ibcon#read 3, iclass 28, count 0 2006.173.19:27:53.80#ibcon#about to read 4, iclass 28, count 0 2006.173.19:27:53.80#ibcon#read 4, iclass 28, count 0 2006.173.19:27:53.80#ibcon#about to read 5, iclass 28, count 0 2006.173.19:27:53.80#ibcon#read 5, iclass 28, count 0 2006.173.19:27:53.80#ibcon#about to read 6, iclass 28, count 0 2006.173.19:27:53.80#ibcon#read 6, iclass 28, count 0 2006.173.19:27:53.80#ibcon#end of sib2, iclass 28, count 0 2006.173.19:27:53.80#ibcon#*mode == 0, iclass 28, count 0 2006.173.19:27:53.80#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.19:27:53.80#ibcon#[25=USB\r\n] 2006.173.19:27:53.80#ibcon#*before write, iclass 28, count 0 2006.173.19:27:53.80#ibcon#enter sib2, iclass 28, count 0 2006.173.19:27:53.80#ibcon#flushed, iclass 28, count 0 2006.173.19:27:53.80#ibcon#about to write, iclass 28, count 0 2006.173.19:27:53.80#ibcon#wrote, iclass 28, count 0 2006.173.19:27:53.80#ibcon#about to read 3, iclass 28, count 0 2006.173.19:27:53.83#ibcon#read 3, iclass 28, count 0 2006.173.19:27:53.83#ibcon#about to read 4, iclass 28, count 0 2006.173.19:27:53.83#ibcon#read 4, iclass 28, count 0 2006.173.19:27:53.83#ibcon#about to read 5, iclass 28, count 0 2006.173.19:27:53.83#ibcon#read 5, iclass 28, count 0 2006.173.19:27:53.83#ibcon#about to read 6, iclass 28, count 0 2006.173.19:27:53.83#ibcon#read 6, iclass 28, count 0 2006.173.19:27:53.83#ibcon#end of sib2, iclass 28, count 0 2006.173.19:27:53.83#ibcon#*after write, iclass 28, count 0 2006.173.19:27:53.83#ibcon#*before return 0, iclass 28, count 0 2006.173.19:27:53.83#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.19:27:53.83#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.19:27:53.83#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.19:27:53.83#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.19:27:53.83$vck44/valo=6,814.99 2006.173.19:27:53.83#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.19:27:53.83#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.19:27:53.83#ibcon#ireg 17 cls_cnt 0 2006.173.19:27:53.83#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.19:27:53.83#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.19:27:53.83#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.19:27:53.83#ibcon#enter wrdev, iclass 30, count 0 2006.173.19:27:53.83#ibcon#first serial, iclass 30, count 0 2006.173.19:27:53.83#ibcon#enter sib2, iclass 30, count 0 2006.173.19:27:53.83#ibcon#flushed, iclass 30, count 0 2006.173.19:27:53.83#ibcon#about to write, iclass 30, count 0 2006.173.19:27:53.83#ibcon#wrote, iclass 30, count 0 2006.173.19:27:53.83#ibcon#about to read 3, iclass 30, count 0 2006.173.19:27:53.85#ibcon#read 3, iclass 30, count 0 2006.173.19:27:53.85#ibcon#about to read 4, iclass 30, count 0 2006.173.19:27:53.85#ibcon#read 4, iclass 30, count 0 2006.173.19:27:53.85#ibcon#about to read 5, iclass 30, count 0 2006.173.19:27:53.85#ibcon#read 5, iclass 30, count 0 2006.173.19:27:53.85#ibcon#about to read 6, iclass 30, count 0 2006.173.19:27:53.85#ibcon#read 6, iclass 30, count 0 2006.173.19:27:53.85#ibcon#end of sib2, iclass 30, count 0 2006.173.19:27:53.85#ibcon#*mode == 0, iclass 30, count 0 2006.173.19:27:53.85#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.19:27:53.85#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.19:27:53.85#ibcon#*before write, iclass 30, count 0 2006.173.19:27:53.85#ibcon#enter sib2, iclass 30, count 0 2006.173.19:27:53.85#ibcon#flushed, iclass 30, count 0 2006.173.19:27:53.85#ibcon#about to write, iclass 30, count 0 2006.173.19:27:53.85#ibcon#wrote, iclass 30, count 0 2006.173.19:27:53.85#ibcon#about to read 3, iclass 30, count 0 2006.173.19:27:53.89#ibcon#read 3, iclass 30, count 0 2006.173.19:27:53.89#ibcon#about to read 4, iclass 30, count 0 2006.173.19:27:53.89#ibcon#read 4, iclass 30, count 0 2006.173.19:27:53.89#ibcon#about to read 5, iclass 30, count 0 2006.173.19:27:53.89#ibcon#read 5, iclass 30, count 0 2006.173.19:27:53.89#ibcon#about to read 6, iclass 30, count 0 2006.173.19:27:53.89#ibcon#read 6, iclass 30, count 0 2006.173.19:27:53.89#ibcon#end of sib2, iclass 30, count 0 2006.173.19:27:53.89#ibcon#*after write, iclass 30, count 0 2006.173.19:27:53.89#ibcon#*before return 0, iclass 30, count 0 2006.173.19:27:53.89#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.19:27:53.89#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.19:27:53.89#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.19:27:53.89#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.19:27:53.89$vck44/va=6,3 2006.173.19:27:53.89#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.173.19:27:53.89#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.173.19:27:53.89#ibcon#ireg 11 cls_cnt 2 2006.173.19:27:53.89#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.19:27:53.95#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.19:27:53.95#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.19:27:53.95#ibcon#enter wrdev, iclass 32, count 2 2006.173.19:27:53.95#ibcon#first serial, iclass 32, count 2 2006.173.19:27:53.95#ibcon#enter sib2, iclass 32, count 2 2006.173.19:27:53.95#ibcon#flushed, iclass 32, count 2 2006.173.19:27:53.95#ibcon#about to write, iclass 32, count 2 2006.173.19:27:53.95#ibcon#wrote, iclass 32, count 2 2006.173.19:27:53.95#ibcon#about to read 3, iclass 32, count 2 2006.173.19:27:53.97#ibcon#read 3, iclass 32, count 2 2006.173.19:27:53.97#ibcon#about to read 4, iclass 32, count 2 2006.173.19:27:53.97#ibcon#read 4, iclass 32, count 2 2006.173.19:27:53.97#ibcon#about to read 5, iclass 32, count 2 2006.173.19:27:53.97#ibcon#read 5, iclass 32, count 2 2006.173.19:27:53.97#ibcon#about to read 6, iclass 32, count 2 2006.173.19:27:53.97#ibcon#read 6, iclass 32, count 2 2006.173.19:27:53.97#ibcon#end of sib2, iclass 32, count 2 2006.173.19:27:53.97#ibcon#*mode == 0, iclass 32, count 2 2006.173.19:27:53.97#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.173.19:27:53.97#ibcon#[25=AT06-03\r\n] 2006.173.19:27:53.97#ibcon#*before write, iclass 32, count 2 2006.173.19:27:53.97#ibcon#enter sib2, iclass 32, count 2 2006.173.19:27:53.97#ibcon#flushed, iclass 32, count 2 2006.173.19:27:53.97#ibcon#about to write, iclass 32, count 2 2006.173.19:27:53.97#ibcon#wrote, iclass 32, count 2 2006.173.19:27:53.97#ibcon#about to read 3, iclass 32, count 2 2006.173.19:27:54.00#ibcon#read 3, iclass 32, count 2 2006.173.19:27:54.00#ibcon#about to read 4, iclass 32, count 2 2006.173.19:27:54.00#ibcon#read 4, iclass 32, count 2 2006.173.19:27:54.00#ibcon#about to read 5, iclass 32, count 2 2006.173.19:27:54.00#ibcon#read 5, iclass 32, count 2 2006.173.19:27:54.00#ibcon#about to read 6, iclass 32, count 2 2006.173.19:27:54.00#ibcon#read 6, iclass 32, count 2 2006.173.19:27:54.00#ibcon#end of sib2, iclass 32, count 2 2006.173.19:27:54.00#ibcon#*after write, iclass 32, count 2 2006.173.19:27:54.00#ibcon#*before return 0, iclass 32, count 2 2006.173.19:27:54.00#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.19:27:54.00#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.173.19:27:54.00#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.173.19:27:54.00#ibcon#ireg 7 cls_cnt 0 2006.173.19:27:54.00#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.19:27:54.12#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.19:27:54.12#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.19:27:54.12#ibcon#enter wrdev, iclass 32, count 0 2006.173.19:27:54.12#ibcon#first serial, iclass 32, count 0 2006.173.19:27:54.12#ibcon#enter sib2, iclass 32, count 0 2006.173.19:27:54.12#ibcon#flushed, iclass 32, count 0 2006.173.19:27:54.12#ibcon#about to write, iclass 32, count 0 2006.173.19:27:54.12#ibcon#wrote, iclass 32, count 0 2006.173.19:27:54.12#ibcon#about to read 3, iclass 32, count 0 2006.173.19:27:54.14#ibcon#read 3, iclass 32, count 0 2006.173.19:27:54.14#ibcon#about to read 4, iclass 32, count 0 2006.173.19:27:54.14#ibcon#read 4, iclass 32, count 0 2006.173.19:27:54.14#ibcon#about to read 5, iclass 32, count 0 2006.173.19:27:54.14#ibcon#read 5, iclass 32, count 0 2006.173.19:27:54.14#ibcon#about to read 6, iclass 32, count 0 2006.173.19:27:54.14#ibcon#read 6, iclass 32, count 0 2006.173.19:27:54.14#ibcon#end of sib2, iclass 32, count 0 2006.173.19:27:54.14#ibcon#*mode == 0, iclass 32, count 0 2006.173.19:27:54.14#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.19:27:54.14#ibcon#[25=USB\r\n] 2006.173.19:27:54.14#ibcon#*before write, iclass 32, count 0 2006.173.19:27:54.14#ibcon#enter sib2, iclass 32, count 0 2006.173.19:27:54.14#ibcon#flushed, iclass 32, count 0 2006.173.19:27:54.14#ibcon#about to write, iclass 32, count 0 2006.173.19:27:54.14#ibcon#wrote, iclass 32, count 0 2006.173.19:27:54.14#ibcon#about to read 3, iclass 32, count 0 2006.173.19:27:54.17#ibcon#read 3, iclass 32, count 0 2006.173.19:27:54.17#ibcon#about to read 4, iclass 32, count 0 2006.173.19:27:54.17#ibcon#read 4, iclass 32, count 0 2006.173.19:27:54.17#ibcon#about to read 5, iclass 32, count 0 2006.173.19:27:54.17#ibcon#read 5, iclass 32, count 0 2006.173.19:27:54.17#ibcon#about to read 6, iclass 32, count 0 2006.173.19:27:54.17#ibcon#read 6, iclass 32, count 0 2006.173.19:27:54.17#ibcon#end of sib2, iclass 32, count 0 2006.173.19:27:54.17#ibcon#*after write, iclass 32, count 0 2006.173.19:27:54.17#ibcon#*before return 0, iclass 32, count 0 2006.173.19:27:54.17#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.19:27:54.17#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.173.19:27:54.17#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.19:27:54.17#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.19:27:54.17$vck44/valo=7,864.99 2006.173.19:27:54.17#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.19:27:54.17#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.19:27:54.17#ibcon#ireg 17 cls_cnt 0 2006.173.19:27:54.17#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.19:27:54.17#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.19:27:54.17#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.19:27:54.17#ibcon#enter wrdev, iclass 34, count 0 2006.173.19:27:54.17#ibcon#first serial, iclass 34, count 0 2006.173.19:27:54.17#ibcon#enter sib2, iclass 34, count 0 2006.173.19:27:54.17#ibcon#flushed, iclass 34, count 0 2006.173.19:27:54.17#ibcon#about to write, iclass 34, count 0 2006.173.19:27:54.17#ibcon#wrote, iclass 34, count 0 2006.173.19:27:54.17#ibcon#about to read 3, iclass 34, count 0 2006.173.19:27:54.19#ibcon#read 3, iclass 34, count 0 2006.173.19:27:54.19#ibcon#about to read 4, iclass 34, count 0 2006.173.19:27:54.19#ibcon#read 4, iclass 34, count 0 2006.173.19:27:54.19#ibcon#about to read 5, iclass 34, count 0 2006.173.19:27:54.19#ibcon#read 5, iclass 34, count 0 2006.173.19:27:54.19#ibcon#about to read 6, iclass 34, count 0 2006.173.19:27:54.19#ibcon#read 6, iclass 34, count 0 2006.173.19:27:54.19#ibcon#end of sib2, iclass 34, count 0 2006.173.19:27:54.19#ibcon#*mode == 0, iclass 34, count 0 2006.173.19:27:54.19#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.19:27:54.19#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.19:27:54.19#ibcon#*before write, iclass 34, count 0 2006.173.19:27:54.19#ibcon#enter sib2, iclass 34, count 0 2006.173.19:27:54.19#ibcon#flushed, iclass 34, count 0 2006.173.19:27:54.19#ibcon#about to write, iclass 34, count 0 2006.173.19:27:54.19#ibcon#wrote, iclass 34, count 0 2006.173.19:27:54.19#ibcon#about to read 3, iclass 34, count 0 2006.173.19:27:54.23#ibcon#read 3, iclass 34, count 0 2006.173.19:27:54.23#ibcon#about to read 4, iclass 34, count 0 2006.173.19:27:54.23#ibcon#read 4, iclass 34, count 0 2006.173.19:27:54.23#ibcon#about to read 5, iclass 34, count 0 2006.173.19:27:54.23#ibcon#read 5, iclass 34, count 0 2006.173.19:27:54.23#ibcon#about to read 6, iclass 34, count 0 2006.173.19:27:54.23#ibcon#read 6, iclass 34, count 0 2006.173.19:27:54.23#ibcon#end of sib2, iclass 34, count 0 2006.173.19:27:54.23#ibcon#*after write, iclass 34, count 0 2006.173.19:27:54.23#ibcon#*before return 0, iclass 34, count 0 2006.173.19:27:54.23#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.19:27:54.23#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.19:27:54.23#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.19:27:54.23#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.19:27:54.23$vck44/va=7,4 2006.173.19:27:54.23#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.19:27:54.23#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.19:27:54.23#ibcon#ireg 11 cls_cnt 2 2006.173.19:27:54.23#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.19:27:54.29#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.19:27:54.29#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.19:27:54.29#ibcon#enter wrdev, iclass 36, count 2 2006.173.19:27:54.29#ibcon#first serial, iclass 36, count 2 2006.173.19:27:54.29#ibcon#enter sib2, iclass 36, count 2 2006.173.19:27:54.29#ibcon#flushed, iclass 36, count 2 2006.173.19:27:54.29#ibcon#about to write, iclass 36, count 2 2006.173.19:27:54.29#ibcon#wrote, iclass 36, count 2 2006.173.19:27:54.29#ibcon#about to read 3, iclass 36, count 2 2006.173.19:27:54.31#ibcon#read 3, iclass 36, count 2 2006.173.19:27:54.31#ibcon#about to read 4, iclass 36, count 2 2006.173.19:27:54.31#ibcon#read 4, iclass 36, count 2 2006.173.19:27:54.31#ibcon#about to read 5, iclass 36, count 2 2006.173.19:27:54.31#ibcon#read 5, iclass 36, count 2 2006.173.19:27:54.31#ibcon#about to read 6, iclass 36, count 2 2006.173.19:27:54.31#ibcon#read 6, iclass 36, count 2 2006.173.19:27:54.31#ibcon#end of sib2, iclass 36, count 2 2006.173.19:27:54.31#ibcon#*mode == 0, iclass 36, count 2 2006.173.19:27:54.31#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.19:27:54.31#ibcon#[25=AT07-04\r\n] 2006.173.19:27:54.31#ibcon#*before write, iclass 36, count 2 2006.173.19:27:54.31#ibcon#enter sib2, iclass 36, count 2 2006.173.19:27:54.31#ibcon#flushed, iclass 36, count 2 2006.173.19:27:54.31#ibcon#about to write, iclass 36, count 2 2006.173.19:27:54.31#ibcon#wrote, iclass 36, count 2 2006.173.19:27:54.31#ibcon#about to read 3, iclass 36, count 2 2006.173.19:27:54.34#ibcon#read 3, iclass 36, count 2 2006.173.19:27:54.34#ibcon#about to read 4, iclass 36, count 2 2006.173.19:27:54.34#ibcon#read 4, iclass 36, count 2 2006.173.19:27:54.34#ibcon#about to read 5, iclass 36, count 2 2006.173.19:27:54.34#ibcon#read 5, iclass 36, count 2 2006.173.19:27:54.34#ibcon#about to read 6, iclass 36, count 2 2006.173.19:27:54.34#ibcon#read 6, iclass 36, count 2 2006.173.19:27:54.34#ibcon#end of sib2, iclass 36, count 2 2006.173.19:27:54.34#ibcon#*after write, iclass 36, count 2 2006.173.19:27:54.34#ibcon#*before return 0, iclass 36, count 2 2006.173.19:27:54.34#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.19:27:54.34#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.19:27:54.34#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.19:27:54.34#ibcon#ireg 7 cls_cnt 0 2006.173.19:27:54.34#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.19:27:54.46#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.19:27:54.46#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.19:27:54.46#ibcon#enter wrdev, iclass 36, count 0 2006.173.19:27:54.46#ibcon#first serial, iclass 36, count 0 2006.173.19:27:54.46#ibcon#enter sib2, iclass 36, count 0 2006.173.19:27:54.46#ibcon#flushed, iclass 36, count 0 2006.173.19:27:54.46#ibcon#about to write, iclass 36, count 0 2006.173.19:27:54.46#ibcon#wrote, iclass 36, count 0 2006.173.19:27:54.46#ibcon#about to read 3, iclass 36, count 0 2006.173.19:27:54.48#ibcon#read 3, iclass 36, count 0 2006.173.19:27:54.48#ibcon#about to read 4, iclass 36, count 0 2006.173.19:27:54.48#ibcon#read 4, iclass 36, count 0 2006.173.19:27:54.48#ibcon#about to read 5, iclass 36, count 0 2006.173.19:27:54.48#ibcon#read 5, iclass 36, count 0 2006.173.19:27:54.48#ibcon#about to read 6, iclass 36, count 0 2006.173.19:27:54.48#ibcon#read 6, iclass 36, count 0 2006.173.19:27:54.48#ibcon#end of sib2, iclass 36, count 0 2006.173.19:27:54.48#ibcon#*mode == 0, iclass 36, count 0 2006.173.19:27:54.48#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.19:27:54.48#ibcon#[25=USB\r\n] 2006.173.19:27:54.48#ibcon#*before write, iclass 36, count 0 2006.173.19:27:54.48#ibcon#enter sib2, iclass 36, count 0 2006.173.19:27:54.48#ibcon#flushed, iclass 36, count 0 2006.173.19:27:54.48#ibcon#about to write, iclass 36, count 0 2006.173.19:27:54.48#ibcon#wrote, iclass 36, count 0 2006.173.19:27:54.48#ibcon#about to read 3, iclass 36, count 0 2006.173.19:27:54.51#ibcon#read 3, iclass 36, count 0 2006.173.19:27:54.51#ibcon#about to read 4, iclass 36, count 0 2006.173.19:27:54.51#ibcon#read 4, iclass 36, count 0 2006.173.19:27:54.51#ibcon#about to read 5, iclass 36, count 0 2006.173.19:27:54.51#ibcon#read 5, iclass 36, count 0 2006.173.19:27:54.51#ibcon#about to read 6, iclass 36, count 0 2006.173.19:27:54.51#ibcon#read 6, iclass 36, count 0 2006.173.19:27:54.51#ibcon#end of sib2, iclass 36, count 0 2006.173.19:27:54.51#ibcon#*after write, iclass 36, count 0 2006.173.19:27:54.51#ibcon#*before return 0, iclass 36, count 0 2006.173.19:27:54.51#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.19:27:54.51#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.19:27:54.51#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.19:27:54.51#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.19:27:54.51$vck44/valo=8,884.99 2006.173.19:27:54.51#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.19:27:54.51#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.19:27:54.51#ibcon#ireg 17 cls_cnt 0 2006.173.19:27:54.51#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.19:27:54.51#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.19:27:54.51#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.19:27:54.51#ibcon#enter wrdev, iclass 38, count 0 2006.173.19:27:54.51#ibcon#first serial, iclass 38, count 0 2006.173.19:27:54.51#ibcon#enter sib2, iclass 38, count 0 2006.173.19:27:54.51#ibcon#flushed, iclass 38, count 0 2006.173.19:27:54.51#ibcon#about to write, iclass 38, count 0 2006.173.19:27:54.51#ibcon#wrote, iclass 38, count 0 2006.173.19:27:54.51#ibcon#about to read 3, iclass 38, count 0 2006.173.19:27:54.53#ibcon#read 3, iclass 38, count 0 2006.173.19:27:54.53#ibcon#about to read 4, iclass 38, count 0 2006.173.19:27:54.53#ibcon#read 4, iclass 38, count 0 2006.173.19:27:54.53#ibcon#about to read 5, iclass 38, count 0 2006.173.19:27:54.53#ibcon#read 5, iclass 38, count 0 2006.173.19:27:54.53#ibcon#about to read 6, iclass 38, count 0 2006.173.19:27:54.53#ibcon#read 6, iclass 38, count 0 2006.173.19:27:54.53#ibcon#end of sib2, iclass 38, count 0 2006.173.19:27:54.53#ibcon#*mode == 0, iclass 38, count 0 2006.173.19:27:54.53#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.19:27:54.53#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.19:27:54.53#ibcon#*before write, iclass 38, count 0 2006.173.19:27:54.53#ibcon#enter sib2, iclass 38, count 0 2006.173.19:27:54.53#ibcon#flushed, iclass 38, count 0 2006.173.19:27:54.53#ibcon#about to write, iclass 38, count 0 2006.173.19:27:54.53#ibcon#wrote, iclass 38, count 0 2006.173.19:27:54.53#ibcon#about to read 3, iclass 38, count 0 2006.173.19:27:54.57#ibcon#read 3, iclass 38, count 0 2006.173.19:27:54.57#ibcon#about to read 4, iclass 38, count 0 2006.173.19:27:54.57#ibcon#read 4, iclass 38, count 0 2006.173.19:27:54.57#ibcon#about to read 5, iclass 38, count 0 2006.173.19:27:54.57#ibcon#read 5, iclass 38, count 0 2006.173.19:27:54.57#ibcon#about to read 6, iclass 38, count 0 2006.173.19:27:54.57#ibcon#read 6, iclass 38, count 0 2006.173.19:27:54.57#ibcon#end of sib2, iclass 38, count 0 2006.173.19:27:54.57#ibcon#*after write, iclass 38, count 0 2006.173.19:27:54.57#ibcon#*before return 0, iclass 38, count 0 2006.173.19:27:54.57#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.19:27:54.57#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.19:27:54.57#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.19:27:54.57#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.19:27:54.57$vck44/va=8,4 2006.173.19:27:54.57#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.19:27:54.57#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.19:27:54.57#ibcon#ireg 11 cls_cnt 2 2006.173.19:27:54.57#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.19:27:54.63#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.19:27:54.63#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.19:27:54.63#ibcon#enter wrdev, iclass 40, count 2 2006.173.19:27:54.63#ibcon#first serial, iclass 40, count 2 2006.173.19:27:54.63#ibcon#enter sib2, iclass 40, count 2 2006.173.19:27:54.63#ibcon#flushed, iclass 40, count 2 2006.173.19:27:54.63#ibcon#about to write, iclass 40, count 2 2006.173.19:27:54.63#ibcon#wrote, iclass 40, count 2 2006.173.19:27:54.63#ibcon#about to read 3, iclass 40, count 2 2006.173.19:27:54.65#ibcon#read 3, iclass 40, count 2 2006.173.19:27:54.65#ibcon#about to read 4, iclass 40, count 2 2006.173.19:27:54.65#ibcon#read 4, iclass 40, count 2 2006.173.19:27:54.65#ibcon#about to read 5, iclass 40, count 2 2006.173.19:27:54.65#ibcon#read 5, iclass 40, count 2 2006.173.19:27:54.65#ibcon#about to read 6, iclass 40, count 2 2006.173.19:27:54.65#ibcon#read 6, iclass 40, count 2 2006.173.19:27:54.65#ibcon#end of sib2, iclass 40, count 2 2006.173.19:27:54.65#ibcon#*mode == 0, iclass 40, count 2 2006.173.19:27:54.65#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.19:27:54.65#ibcon#[25=AT08-04\r\n] 2006.173.19:27:54.65#ibcon#*before write, iclass 40, count 2 2006.173.19:27:54.65#ibcon#enter sib2, iclass 40, count 2 2006.173.19:27:54.65#ibcon#flushed, iclass 40, count 2 2006.173.19:27:54.65#ibcon#about to write, iclass 40, count 2 2006.173.19:27:54.65#ibcon#wrote, iclass 40, count 2 2006.173.19:27:54.65#ibcon#about to read 3, iclass 40, count 2 2006.173.19:27:54.68#ibcon#read 3, iclass 40, count 2 2006.173.19:27:54.68#ibcon#about to read 4, iclass 40, count 2 2006.173.19:27:54.68#ibcon#read 4, iclass 40, count 2 2006.173.19:27:54.68#ibcon#about to read 5, iclass 40, count 2 2006.173.19:27:54.68#ibcon#read 5, iclass 40, count 2 2006.173.19:27:54.68#ibcon#about to read 6, iclass 40, count 2 2006.173.19:27:54.68#ibcon#read 6, iclass 40, count 2 2006.173.19:27:54.68#ibcon#end of sib2, iclass 40, count 2 2006.173.19:27:54.68#ibcon#*after write, iclass 40, count 2 2006.173.19:27:54.68#ibcon#*before return 0, iclass 40, count 2 2006.173.19:27:54.68#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.19:27:54.68#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.19:27:54.68#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.19:27:54.68#ibcon#ireg 7 cls_cnt 0 2006.173.19:27:54.68#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.19:27:54.80#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.19:27:54.80#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.19:27:54.80#ibcon#enter wrdev, iclass 40, count 0 2006.173.19:27:54.80#ibcon#first serial, iclass 40, count 0 2006.173.19:27:54.80#ibcon#enter sib2, iclass 40, count 0 2006.173.19:27:54.80#ibcon#flushed, iclass 40, count 0 2006.173.19:27:54.80#ibcon#about to write, iclass 40, count 0 2006.173.19:27:54.80#ibcon#wrote, iclass 40, count 0 2006.173.19:27:54.80#ibcon#about to read 3, iclass 40, count 0 2006.173.19:27:54.82#ibcon#read 3, iclass 40, count 0 2006.173.19:27:54.82#ibcon#about to read 4, iclass 40, count 0 2006.173.19:27:54.82#ibcon#read 4, iclass 40, count 0 2006.173.19:27:54.82#ibcon#about to read 5, iclass 40, count 0 2006.173.19:27:54.82#ibcon#read 5, iclass 40, count 0 2006.173.19:27:54.82#ibcon#about to read 6, iclass 40, count 0 2006.173.19:27:54.82#ibcon#read 6, iclass 40, count 0 2006.173.19:27:54.82#ibcon#end of sib2, iclass 40, count 0 2006.173.19:27:54.82#ibcon#*mode == 0, iclass 40, count 0 2006.173.19:27:54.82#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.19:27:54.82#ibcon#[25=USB\r\n] 2006.173.19:27:54.82#ibcon#*before write, iclass 40, count 0 2006.173.19:27:54.82#ibcon#enter sib2, iclass 40, count 0 2006.173.19:27:54.82#ibcon#flushed, iclass 40, count 0 2006.173.19:27:54.82#ibcon#about to write, iclass 40, count 0 2006.173.19:27:54.82#ibcon#wrote, iclass 40, count 0 2006.173.19:27:54.82#ibcon#about to read 3, iclass 40, count 0 2006.173.19:27:54.85#ibcon#read 3, iclass 40, count 0 2006.173.19:27:54.85#ibcon#about to read 4, iclass 40, count 0 2006.173.19:27:54.85#ibcon#read 4, iclass 40, count 0 2006.173.19:27:54.85#ibcon#about to read 5, iclass 40, count 0 2006.173.19:27:54.85#ibcon#read 5, iclass 40, count 0 2006.173.19:27:54.85#ibcon#about to read 6, iclass 40, count 0 2006.173.19:27:54.85#ibcon#read 6, iclass 40, count 0 2006.173.19:27:54.85#ibcon#end of sib2, iclass 40, count 0 2006.173.19:27:54.85#ibcon#*after write, iclass 40, count 0 2006.173.19:27:54.85#ibcon#*before return 0, iclass 40, count 0 2006.173.19:27:54.85#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.19:27:54.85#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.19:27:54.85#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.19:27:54.85#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.19:27:54.85$vck44/vblo=1,629.99 2006.173.19:27:54.85#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.19:27:54.85#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.19:27:54.85#ibcon#ireg 17 cls_cnt 0 2006.173.19:27:54.85#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.19:27:54.85#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.19:27:54.85#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.19:27:54.85#ibcon#enter wrdev, iclass 4, count 0 2006.173.19:27:54.85#ibcon#first serial, iclass 4, count 0 2006.173.19:27:54.85#ibcon#enter sib2, iclass 4, count 0 2006.173.19:27:54.85#ibcon#flushed, iclass 4, count 0 2006.173.19:27:54.85#ibcon#about to write, iclass 4, count 0 2006.173.19:27:54.85#ibcon#wrote, iclass 4, count 0 2006.173.19:27:54.85#ibcon#about to read 3, iclass 4, count 0 2006.173.19:27:54.87#ibcon#read 3, iclass 4, count 0 2006.173.19:27:54.87#ibcon#about to read 4, iclass 4, count 0 2006.173.19:27:54.87#ibcon#read 4, iclass 4, count 0 2006.173.19:27:54.87#ibcon#about to read 5, iclass 4, count 0 2006.173.19:27:54.87#ibcon#read 5, iclass 4, count 0 2006.173.19:27:54.87#ibcon#about to read 6, iclass 4, count 0 2006.173.19:27:54.87#ibcon#read 6, iclass 4, count 0 2006.173.19:27:54.87#ibcon#end of sib2, iclass 4, count 0 2006.173.19:27:54.87#ibcon#*mode == 0, iclass 4, count 0 2006.173.19:27:54.87#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.19:27:54.87#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.19:27:54.87#ibcon#*before write, iclass 4, count 0 2006.173.19:27:54.87#ibcon#enter sib2, iclass 4, count 0 2006.173.19:27:54.87#ibcon#flushed, iclass 4, count 0 2006.173.19:27:54.87#ibcon#about to write, iclass 4, count 0 2006.173.19:27:54.87#ibcon#wrote, iclass 4, count 0 2006.173.19:27:54.87#ibcon#about to read 3, iclass 4, count 0 2006.173.19:27:54.91#ibcon#read 3, iclass 4, count 0 2006.173.19:27:54.91#ibcon#about to read 4, iclass 4, count 0 2006.173.19:27:54.91#ibcon#read 4, iclass 4, count 0 2006.173.19:27:54.91#ibcon#about to read 5, iclass 4, count 0 2006.173.19:27:54.91#ibcon#read 5, iclass 4, count 0 2006.173.19:27:54.91#ibcon#about to read 6, iclass 4, count 0 2006.173.19:27:54.91#ibcon#read 6, iclass 4, count 0 2006.173.19:27:54.91#ibcon#end of sib2, iclass 4, count 0 2006.173.19:27:54.91#ibcon#*after write, iclass 4, count 0 2006.173.19:27:54.91#ibcon#*before return 0, iclass 4, count 0 2006.173.19:27:54.91#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.19:27:54.91#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.19:27:54.91#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.19:27:54.91#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.19:27:54.91$vck44/vb=1,4 2006.173.19:27:54.91#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.19:27:54.91#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.19:27:54.91#ibcon#ireg 11 cls_cnt 2 2006.173.19:27:54.91#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.19:27:54.91#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.19:27:54.91#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.19:27:54.91#ibcon#enter wrdev, iclass 6, count 2 2006.173.19:27:54.91#ibcon#first serial, iclass 6, count 2 2006.173.19:27:54.91#ibcon#enter sib2, iclass 6, count 2 2006.173.19:27:54.91#ibcon#flushed, iclass 6, count 2 2006.173.19:27:54.91#ibcon#about to write, iclass 6, count 2 2006.173.19:27:54.91#ibcon#wrote, iclass 6, count 2 2006.173.19:27:54.91#ibcon#about to read 3, iclass 6, count 2 2006.173.19:27:54.93#ibcon#read 3, iclass 6, count 2 2006.173.19:27:54.93#ibcon#about to read 4, iclass 6, count 2 2006.173.19:27:54.93#ibcon#read 4, iclass 6, count 2 2006.173.19:27:54.93#ibcon#about to read 5, iclass 6, count 2 2006.173.19:27:54.93#ibcon#read 5, iclass 6, count 2 2006.173.19:27:54.93#ibcon#about to read 6, iclass 6, count 2 2006.173.19:27:54.93#ibcon#read 6, iclass 6, count 2 2006.173.19:27:54.93#ibcon#end of sib2, iclass 6, count 2 2006.173.19:27:54.93#ibcon#*mode == 0, iclass 6, count 2 2006.173.19:27:54.93#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.19:27:54.93#ibcon#[27=AT01-04\r\n] 2006.173.19:27:54.93#ibcon#*before write, iclass 6, count 2 2006.173.19:27:54.93#ibcon#enter sib2, iclass 6, count 2 2006.173.19:27:54.93#ibcon#flushed, iclass 6, count 2 2006.173.19:27:54.93#ibcon#about to write, iclass 6, count 2 2006.173.19:27:54.93#ibcon#wrote, iclass 6, count 2 2006.173.19:27:54.93#ibcon#about to read 3, iclass 6, count 2 2006.173.19:27:54.96#ibcon#read 3, iclass 6, count 2 2006.173.19:27:54.96#ibcon#about to read 4, iclass 6, count 2 2006.173.19:27:54.96#ibcon#read 4, iclass 6, count 2 2006.173.19:27:54.96#ibcon#about to read 5, iclass 6, count 2 2006.173.19:27:54.96#ibcon#read 5, iclass 6, count 2 2006.173.19:27:54.96#ibcon#about to read 6, iclass 6, count 2 2006.173.19:27:54.96#ibcon#read 6, iclass 6, count 2 2006.173.19:27:54.96#ibcon#end of sib2, iclass 6, count 2 2006.173.19:27:54.96#ibcon#*after write, iclass 6, count 2 2006.173.19:27:54.96#ibcon#*before return 0, iclass 6, count 2 2006.173.19:27:54.96#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.19:27:54.96#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.19:27:54.96#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.19:27:54.96#ibcon#ireg 7 cls_cnt 0 2006.173.19:27:54.96#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.19:27:55.08#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.19:27:55.08#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.19:27:55.08#ibcon#enter wrdev, iclass 6, count 0 2006.173.19:27:55.08#ibcon#first serial, iclass 6, count 0 2006.173.19:27:55.08#ibcon#enter sib2, iclass 6, count 0 2006.173.19:27:55.08#ibcon#flushed, iclass 6, count 0 2006.173.19:27:55.08#ibcon#about to write, iclass 6, count 0 2006.173.19:27:55.08#ibcon#wrote, iclass 6, count 0 2006.173.19:27:55.08#ibcon#about to read 3, iclass 6, count 0 2006.173.19:27:55.10#ibcon#read 3, iclass 6, count 0 2006.173.19:27:55.10#ibcon#about to read 4, iclass 6, count 0 2006.173.19:27:55.10#ibcon#read 4, iclass 6, count 0 2006.173.19:27:55.10#ibcon#about to read 5, iclass 6, count 0 2006.173.19:27:55.10#ibcon#read 5, iclass 6, count 0 2006.173.19:27:55.10#ibcon#about to read 6, iclass 6, count 0 2006.173.19:27:55.10#ibcon#read 6, iclass 6, count 0 2006.173.19:27:55.10#ibcon#end of sib2, iclass 6, count 0 2006.173.19:27:55.10#ibcon#*mode == 0, iclass 6, count 0 2006.173.19:27:55.10#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.19:27:55.10#ibcon#[27=USB\r\n] 2006.173.19:27:55.10#ibcon#*before write, iclass 6, count 0 2006.173.19:27:55.10#ibcon#enter sib2, iclass 6, count 0 2006.173.19:27:55.10#ibcon#flushed, iclass 6, count 0 2006.173.19:27:55.10#ibcon#about to write, iclass 6, count 0 2006.173.19:27:55.10#ibcon#wrote, iclass 6, count 0 2006.173.19:27:55.10#ibcon#about to read 3, iclass 6, count 0 2006.173.19:27:55.13#ibcon#read 3, iclass 6, count 0 2006.173.19:27:55.13#ibcon#about to read 4, iclass 6, count 0 2006.173.19:27:55.13#ibcon#read 4, iclass 6, count 0 2006.173.19:27:55.13#ibcon#about to read 5, iclass 6, count 0 2006.173.19:27:55.13#ibcon#read 5, iclass 6, count 0 2006.173.19:27:55.13#ibcon#about to read 6, iclass 6, count 0 2006.173.19:27:55.13#ibcon#read 6, iclass 6, count 0 2006.173.19:27:55.13#ibcon#end of sib2, iclass 6, count 0 2006.173.19:27:55.13#ibcon#*after write, iclass 6, count 0 2006.173.19:27:55.13#ibcon#*before return 0, iclass 6, count 0 2006.173.19:27:55.13#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.19:27:55.13#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.19:27:55.13#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.19:27:55.13#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.19:27:55.13$vck44/vblo=2,634.99 2006.173.19:27:55.13#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.19:27:55.13#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.19:27:55.13#ibcon#ireg 17 cls_cnt 0 2006.173.19:27:55.13#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.19:27:55.13#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.19:27:55.13#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.19:27:55.13#ibcon#enter wrdev, iclass 10, count 0 2006.173.19:27:55.13#ibcon#first serial, iclass 10, count 0 2006.173.19:27:55.13#ibcon#enter sib2, iclass 10, count 0 2006.173.19:27:55.13#ibcon#flushed, iclass 10, count 0 2006.173.19:27:55.13#ibcon#about to write, iclass 10, count 0 2006.173.19:27:55.13#ibcon#wrote, iclass 10, count 0 2006.173.19:27:55.13#ibcon#about to read 3, iclass 10, count 0 2006.173.19:27:55.15#ibcon#read 3, iclass 10, count 0 2006.173.19:27:55.15#ibcon#about to read 4, iclass 10, count 0 2006.173.19:27:55.15#ibcon#read 4, iclass 10, count 0 2006.173.19:27:55.15#ibcon#about to read 5, iclass 10, count 0 2006.173.19:27:55.15#ibcon#read 5, iclass 10, count 0 2006.173.19:27:55.15#ibcon#about to read 6, iclass 10, count 0 2006.173.19:27:55.15#ibcon#read 6, iclass 10, count 0 2006.173.19:27:55.15#ibcon#end of sib2, iclass 10, count 0 2006.173.19:27:55.15#ibcon#*mode == 0, iclass 10, count 0 2006.173.19:27:55.15#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.19:27:55.15#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.19:27:55.15#ibcon#*before write, iclass 10, count 0 2006.173.19:27:55.15#ibcon#enter sib2, iclass 10, count 0 2006.173.19:27:55.15#ibcon#flushed, iclass 10, count 0 2006.173.19:27:55.15#ibcon#about to write, iclass 10, count 0 2006.173.19:27:55.15#ibcon#wrote, iclass 10, count 0 2006.173.19:27:55.15#ibcon#about to read 3, iclass 10, count 0 2006.173.19:27:55.19#ibcon#read 3, iclass 10, count 0 2006.173.19:27:55.19#ibcon#about to read 4, iclass 10, count 0 2006.173.19:27:55.19#ibcon#read 4, iclass 10, count 0 2006.173.19:27:55.19#ibcon#about to read 5, iclass 10, count 0 2006.173.19:27:55.19#ibcon#read 5, iclass 10, count 0 2006.173.19:27:55.19#ibcon#about to read 6, iclass 10, count 0 2006.173.19:27:55.19#ibcon#read 6, iclass 10, count 0 2006.173.19:27:55.19#ibcon#end of sib2, iclass 10, count 0 2006.173.19:27:55.19#ibcon#*after write, iclass 10, count 0 2006.173.19:27:55.19#ibcon#*before return 0, iclass 10, count 0 2006.173.19:27:55.19#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.19:27:55.19#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.19:27:55.19#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.19:27:55.19#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.19:27:55.19$vck44/vb=2,4 2006.173.19:27:55.19#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.19:27:55.19#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.19:27:55.19#ibcon#ireg 11 cls_cnt 2 2006.173.19:27:55.19#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.19:27:55.25#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.19:27:55.25#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.19:27:55.25#ibcon#enter wrdev, iclass 12, count 2 2006.173.19:27:55.25#ibcon#first serial, iclass 12, count 2 2006.173.19:27:55.25#ibcon#enter sib2, iclass 12, count 2 2006.173.19:27:55.25#ibcon#flushed, iclass 12, count 2 2006.173.19:27:55.25#ibcon#about to write, iclass 12, count 2 2006.173.19:27:55.25#ibcon#wrote, iclass 12, count 2 2006.173.19:27:55.25#ibcon#about to read 3, iclass 12, count 2 2006.173.19:27:55.27#ibcon#read 3, iclass 12, count 2 2006.173.19:27:55.27#ibcon#about to read 4, iclass 12, count 2 2006.173.19:27:55.27#ibcon#read 4, iclass 12, count 2 2006.173.19:27:55.27#ibcon#about to read 5, iclass 12, count 2 2006.173.19:27:55.27#ibcon#read 5, iclass 12, count 2 2006.173.19:27:55.27#ibcon#about to read 6, iclass 12, count 2 2006.173.19:27:55.27#ibcon#read 6, iclass 12, count 2 2006.173.19:27:55.27#ibcon#end of sib2, iclass 12, count 2 2006.173.19:27:55.27#ibcon#*mode == 0, iclass 12, count 2 2006.173.19:27:55.27#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.19:27:55.27#ibcon#[27=AT02-04\r\n] 2006.173.19:27:55.27#ibcon#*before write, iclass 12, count 2 2006.173.19:27:55.27#ibcon#enter sib2, iclass 12, count 2 2006.173.19:27:55.27#ibcon#flushed, iclass 12, count 2 2006.173.19:27:55.27#ibcon#about to write, iclass 12, count 2 2006.173.19:27:55.27#ibcon#wrote, iclass 12, count 2 2006.173.19:27:55.27#ibcon#about to read 3, iclass 12, count 2 2006.173.19:27:55.30#ibcon#read 3, iclass 12, count 2 2006.173.19:27:55.30#ibcon#about to read 4, iclass 12, count 2 2006.173.19:27:55.30#ibcon#read 4, iclass 12, count 2 2006.173.19:27:55.30#ibcon#about to read 5, iclass 12, count 2 2006.173.19:27:55.30#ibcon#read 5, iclass 12, count 2 2006.173.19:27:55.30#ibcon#about to read 6, iclass 12, count 2 2006.173.19:27:55.30#ibcon#read 6, iclass 12, count 2 2006.173.19:27:55.30#ibcon#end of sib2, iclass 12, count 2 2006.173.19:27:55.30#ibcon#*after write, iclass 12, count 2 2006.173.19:27:55.30#ibcon#*before return 0, iclass 12, count 2 2006.173.19:27:55.30#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.19:27:55.30#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.19:27:55.30#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.19:27:55.30#ibcon#ireg 7 cls_cnt 0 2006.173.19:27:55.30#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.19:27:55.42#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.19:27:55.42#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.19:27:55.42#ibcon#enter wrdev, iclass 12, count 0 2006.173.19:27:55.42#ibcon#first serial, iclass 12, count 0 2006.173.19:27:55.42#ibcon#enter sib2, iclass 12, count 0 2006.173.19:27:55.42#ibcon#flushed, iclass 12, count 0 2006.173.19:27:55.42#ibcon#about to write, iclass 12, count 0 2006.173.19:27:55.42#ibcon#wrote, iclass 12, count 0 2006.173.19:27:55.42#ibcon#about to read 3, iclass 12, count 0 2006.173.19:27:55.44#ibcon#read 3, iclass 12, count 0 2006.173.19:27:55.44#ibcon#about to read 4, iclass 12, count 0 2006.173.19:27:55.44#ibcon#read 4, iclass 12, count 0 2006.173.19:27:55.44#ibcon#about to read 5, iclass 12, count 0 2006.173.19:27:55.44#ibcon#read 5, iclass 12, count 0 2006.173.19:27:55.44#ibcon#about to read 6, iclass 12, count 0 2006.173.19:27:55.44#ibcon#read 6, iclass 12, count 0 2006.173.19:27:55.44#ibcon#end of sib2, iclass 12, count 0 2006.173.19:27:55.44#ibcon#*mode == 0, iclass 12, count 0 2006.173.19:27:55.44#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.19:27:55.44#ibcon#[27=USB\r\n] 2006.173.19:27:55.44#ibcon#*before write, iclass 12, count 0 2006.173.19:27:55.44#ibcon#enter sib2, iclass 12, count 0 2006.173.19:27:55.44#ibcon#flushed, iclass 12, count 0 2006.173.19:27:55.44#ibcon#about to write, iclass 12, count 0 2006.173.19:27:55.44#ibcon#wrote, iclass 12, count 0 2006.173.19:27:55.44#ibcon#about to read 3, iclass 12, count 0 2006.173.19:27:55.47#ibcon#read 3, iclass 12, count 0 2006.173.19:27:55.47#ibcon#about to read 4, iclass 12, count 0 2006.173.19:27:55.47#ibcon#read 4, iclass 12, count 0 2006.173.19:27:55.47#ibcon#about to read 5, iclass 12, count 0 2006.173.19:27:55.47#ibcon#read 5, iclass 12, count 0 2006.173.19:27:55.47#ibcon#about to read 6, iclass 12, count 0 2006.173.19:27:55.47#ibcon#read 6, iclass 12, count 0 2006.173.19:27:55.47#ibcon#end of sib2, iclass 12, count 0 2006.173.19:27:55.47#ibcon#*after write, iclass 12, count 0 2006.173.19:27:55.47#ibcon#*before return 0, iclass 12, count 0 2006.173.19:27:55.47#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.19:27:55.47#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.19:27:55.47#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.19:27:55.47#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.19:27:55.47$vck44/vblo=3,649.99 2006.173.19:27:55.47#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.19:27:55.47#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.19:27:55.47#ibcon#ireg 17 cls_cnt 0 2006.173.19:27:55.47#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.19:27:55.47#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.19:27:55.47#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.19:27:55.47#ibcon#enter wrdev, iclass 14, count 0 2006.173.19:27:55.47#ibcon#first serial, iclass 14, count 0 2006.173.19:27:55.47#ibcon#enter sib2, iclass 14, count 0 2006.173.19:27:55.47#ibcon#flushed, iclass 14, count 0 2006.173.19:27:55.47#ibcon#about to write, iclass 14, count 0 2006.173.19:27:55.47#ibcon#wrote, iclass 14, count 0 2006.173.19:27:55.47#ibcon#about to read 3, iclass 14, count 0 2006.173.19:27:55.49#ibcon#read 3, iclass 14, count 0 2006.173.19:27:55.49#ibcon#about to read 4, iclass 14, count 0 2006.173.19:27:55.49#ibcon#read 4, iclass 14, count 0 2006.173.19:27:55.49#ibcon#about to read 5, iclass 14, count 0 2006.173.19:27:55.49#ibcon#read 5, iclass 14, count 0 2006.173.19:27:55.49#ibcon#about to read 6, iclass 14, count 0 2006.173.19:27:55.49#ibcon#read 6, iclass 14, count 0 2006.173.19:27:55.49#ibcon#end of sib2, iclass 14, count 0 2006.173.19:27:55.49#ibcon#*mode == 0, iclass 14, count 0 2006.173.19:27:55.49#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.19:27:55.49#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.19:27:55.49#ibcon#*before write, iclass 14, count 0 2006.173.19:27:55.49#ibcon#enter sib2, iclass 14, count 0 2006.173.19:27:55.49#ibcon#flushed, iclass 14, count 0 2006.173.19:27:55.49#ibcon#about to write, iclass 14, count 0 2006.173.19:27:55.49#ibcon#wrote, iclass 14, count 0 2006.173.19:27:55.49#ibcon#about to read 3, iclass 14, count 0 2006.173.19:27:55.53#ibcon#read 3, iclass 14, count 0 2006.173.19:27:55.53#ibcon#about to read 4, iclass 14, count 0 2006.173.19:27:55.53#ibcon#read 4, iclass 14, count 0 2006.173.19:27:55.53#ibcon#about to read 5, iclass 14, count 0 2006.173.19:27:55.53#ibcon#read 5, iclass 14, count 0 2006.173.19:27:55.53#ibcon#about to read 6, iclass 14, count 0 2006.173.19:27:55.53#ibcon#read 6, iclass 14, count 0 2006.173.19:27:55.53#ibcon#end of sib2, iclass 14, count 0 2006.173.19:27:55.53#ibcon#*after write, iclass 14, count 0 2006.173.19:27:55.53#ibcon#*before return 0, iclass 14, count 0 2006.173.19:27:55.53#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.19:27:55.53#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.19:27:55.53#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.19:27:55.53#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.19:27:55.53$vck44/vb=3,4 2006.173.19:27:55.53#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.19:27:55.53#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.19:27:55.53#ibcon#ireg 11 cls_cnt 2 2006.173.19:27:55.53#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.19:27:55.59#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.19:27:55.59#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.19:27:55.59#ibcon#enter wrdev, iclass 16, count 2 2006.173.19:27:55.59#ibcon#first serial, iclass 16, count 2 2006.173.19:27:55.59#ibcon#enter sib2, iclass 16, count 2 2006.173.19:27:55.59#ibcon#flushed, iclass 16, count 2 2006.173.19:27:55.59#ibcon#about to write, iclass 16, count 2 2006.173.19:27:55.59#ibcon#wrote, iclass 16, count 2 2006.173.19:27:55.59#ibcon#about to read 3, iclass 16, count 2 2006.173.19:27:55.61#ibcon#read 3, iclass 16, count 2 2006.173.19:27:55.61#ibcon#about to read 4, iclass 16, count 2 2006.173.19:27:55.61#ibcon#read 4, iclass 16, count 2 2006.173.19:27:55.61#ibcon#about to read 5, iclass 16, count 2 2006.173.19:27:55.61#ibcon#read 5, iclass 16, count 2 2006.173.19:27:55.61#ibcon#about to read 6, iclass 16, count 2 2006.173.19:27:55.61#ibcon#read 6, iclass 16, count 2 2006.173.19:27:55.61#ibcon#end of sib2, iclass 16, count 2 2006.173.19:27:55.61#ibcon#*mode == 0, iclass 16, count 2 2006.173.19:27:55.61#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.19:27:55.61#ibcon#[27=AT03-04\r\n] 2006.173.19:27:55.61#ibcon#*before write, iclass 16, count 2 2006.173.19:27:55.61#ibcon#enter sib2, iclass 16, count 2 2006.173.19:27:55.61#ibcon#flushed, iclass 16, count 2 2006.173.19:27:55.61#ibcon#about to write, iclass 16, count 2 2006.173.19:27:55.61#ibcon#wrote, iclass 16, count 2 2006.173.19:27:55.61#ibcon#about to read 3, iclass 16, count 2 2006.173.19:27:55.64#ibcon#read 3, iclass 16, count 2 2006.173.19:27:55.64#ibcon#about to read 4, iclass 16, count 2 2006.173.19:27:55.64#ibcon#read 4, iclass 16, count 2 2006.173.19:27:55.64#ibcon#about to read 5, iclass 16, count 2 2006.173.19:27:55.64#ibcon#read 5, iclass 16, count 2 2006.173.19:27:55.64#ibcon#about to read 6, iclass 16, count 2 2006.173.19:27:55.64#ibcon#read 6, iclass 16, count 2 2006.173.19:27:55.64#ibcon#end of sib2, iclass 16, count 2 2006.173.19:27:55.64#ibcon#*after write, iclass 16, count 2 2006.173.19:27:55.64#ibcon#*before return 0, iclass 16, count 2 2006.173.19:27:55.64#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.19:27:55.64#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.19:27:55.64#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.19:27:55.64#ibcon#ireg 7 cls_cnt 0 2006.173.19:27:55.64#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.19:27:55.76#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.19:27:55.76#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.19:27:55.76#ibcon#enter wrdev, iclass 16, count 0 2006.173.19:27:55.76#ibcon#first serial, iclass 16, count 0 2006.173.19:27:55.76#ibcon#enter sib2, iclass 16, count 0 2006.173.19:27:55.76#ibcon#flushed, iclass 16, count 0 2006.173.19:27:55.76#ibcon#about to write, iclass 16, count 0 2006.173.19:27:55.76#ibcon#wrote, iclass 16, count 0 2006.173.19:27:55.76#ibcon#about to read 3, iclass 16, count 0 2006.173.19:27:55.78#ibcon#read 3, iclass 16, count 0 2006.173.19:27:55.78#ibcon#about to read 4, iclass 16, count 0 2006.173.19:27:55.78#ibcon#read 4, iclass 16, count 0 2006.173.19:27:55.78#ibcon#about to read 5, iclass 16, count 0 2006.173.19:27:55.78#ibcon#read 5, iclass 16, count 0 2006.173.19:27:55.78#ibcon#about to read 6, iclass 16, count 0 2006.173.19:27:55.78#ibcon#read 6, iclass 16, count 0 2006.173.19:27:55.78#ibcon#end of sib2, iclass 16, count 0 2006.173.19:27:55.78#ibcon#*mode == 0, iclass 16, count 0 2006.173.19:27:55.78#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.19:27:55.78#ibcon#[27=USB\r\n] 2006.173.19:27:55.78#ibcon#*before write, iclass 16, count 0 2006.173.19:27:55.78#ibcon#enter sib2, iclass 16, count 0 2006.173.19:27:55.78#ibcon#flushed, iclass 16, count 0 2006.173.19:27:55.78#ibcon#about to write, iclass 16, count 0 2006.173.19:27:55.78#ibcon#wrote, iclass 16, count 0 2006.173.19:27:55.78#ibcon#about to read 3, iclass 16, count 0 2006.173.19:27:55.81#ibcon#read 3, iclass 16, count 0 2006.173.19:27:55.81#ibcon#about to read 4, iclass 16, count 0 2006.173.19:27:55.81#ibcon#read 4, iclass 16, count 0 2006.173.19:27:55.81#ibcon#about to read 5, iclass 16, count 0 2006.173.19:27:55.81#ibcon#read 5, iclass 16, count 0 2006.173.19:27:55.81#ibcon#about to read 6, iclass 16, count 0 2006.173.19:27:55.81#ibcon#read 6, iclass 16, count 0 2006.173.19:27:55.81#ibcon#end of sib2, iclass 16, count 0 2006.173.19:27:55.81#ibcon#*after write, iclass 16, count 0 2006.173.19:27:55.81#ibcon#*before return 0, iclass 16, count 0 2006.173.19:27:55.81#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.19:27:55.81#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.19:27:55.81#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.19:27:55.81#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.19:27:55.81$vck44/vblo=4,679.99 2006.173.19:27:55.81#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.19:27:55.81#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.19:27:55.81#ibcon#ireg 17 cls_cnt 0 2006.173.19:27:55.81#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.19:27:55.81#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.19:27:55.81#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.19:27:55.81#ibcon#enter wrdev, iclass 18, count 0 2006.173.19:27:55.81#ibcon#first serial, iclass 18, count 0 2006.173.19:27:55.81#ibcon#enter sib2, iclass 18, count 0 2006.173.19:27:55.81#ibcon#flushed, iclass 18, count 0 2006.173.19:27:55.81#ibcon#about to write, iclass 18, count 0 2006.173.19:27:55.81#ibcon#wrote, iclass 18, count 0 2006.173.19:27:55.81#ibcon#about to read 3, iclass 18, count 0 2006.173.19:27:55.83#ibcon#read 3, iclass 18, count 0 2006.173.19:27:55.83#ibcon#about to read 4, iclass 18, count 0 2006.173.19:27:55.83#ibcon#read 4, iclass 18, count 0 2006.173.19:27:55.83#ibcon#about to read 5, iclass 18, count 0 2006.173.19:27:55.83#ibcon#read 5, iclass 18, count 0 2006.173.19:27:55.83#ibcon#about to read 6, iclass 18, count 0 2006.173.19:27:55.83#ibcon#read 6, iclass 18, count 0 2006.173.19:27:55.83#ibcon#end of sib2, iclass 18, count 0 2006.173.19:27:55.83#ibcon#*mode == 0, iclass 18, count 0 2006.173.19:27:55.83#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.19:27:55.83#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.19:27:55.83#ibcon#*before write, iclass 18, count 0 2006.173.19:27:55.83#ibcon#enter sib2, iclass 18, count 0 2006.173.19:27:55.83#ibcon#flushed, iclass 18, count 0 2006.173.19:27:55.83#ibcon#about to write, iclass 18, count 0 2006.173.19:27:55.83#ibcon#wrote, iclass 18, count 0 2006.173.19:27:55.83#ibcon#about to read 3, iclass 18, count 0 2006.173.19:27:55.87#ibcon#read 3, iclass 18, count 0 2006.173.19:27:55.87#ibcon#about to read 4, iclass 18, count 0 2006.173.19:27:55.87#ibcon#read 4, iclass 18, count 0 2006.173.19:27:55.87#ibcon#about to read 5, iclass 18, count 0 2006.173.19:27:55.87#ibcon#read 5, iclass 18, count 0 2006.173.19:27:55.87#ibcon#about to read 6, iclass 18, count 0 2006.173.19:27:55.87#ibcon#read 6, iclass 18, count 0 2006.173.19:27:55.87#ibcon#end of sib2, iclass 18, count 0 2006.173.19:27:55.87#ibcon#*after write, iclass 18, count 0 2006.173.19:27:55.87#ibcon#*before return 0, iclass 18, count 0 2006.173.19:27:55.87#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.19:27:55.87#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.19:27:55.87#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.19:27:55.87#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.19:27:55.87$vck44/vb=4,4 2006.173.19:27:55.87#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.19:27:55.87#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.19:27:55.87#ibcon#ireg 11 cls_cnt 2 2006.173.19:27:55.87#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.19:27:55.93#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.19:27:55.93#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.19:27:55.93#ibcon#enter wrdev, iclass 20, count 2 2006.173.19:27:55.93#ibcon#first serial, iclass 20, count 2 2006.173.19:27:55.93#ibcon#enter sib2, iclass 20, count 2 2006.173.19:27:55.93#ibcon#flushed, iclass 20, count 2 2006.173.19:27:55.93#ibcon#about to write, iclass 20, count 2 2006.173.19:27:55.93#ibcon#wrote, iclass 20, count 2 2006.173.19:27:55.93#ibcon#about to read 3, iclass 20, count 2 2006.173.19:27:55.95#ibcon#read 3, iclass 20, count 2 2006.173.19:27:55.95#ibcon#about to read 4, iclass 20, count 2 2006.173.19:27:55.95#ibcon#read 4, iclass 20, count 2 2006.173.19:27:55.95#ibcon#about to read 5, iclass 20, count 2 2006.173.19:27:55.95#ibcon#read 5, iclass 20, count 2 2006.173.19:27:55.95#ibcon#about to read 6, iclass 20, count 2 2006.173.19:27:55.95#ibcon#read 6, iclass 20, count 2 2006.173.19:27:55.95#ibcon#end of sib2, iclass 20, count 2 2006.173.19:27:55.95#ibcon#*mode == 0, iclass 20, count 2 2006.173.19:27:55.95#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.19:27:55.95#ibcon#[27=AT04-04\r\n] 2006.173.19:27:55.95#ibcon#*before write, iclass 20, count 2 2006.173.19:27:55.95#ibcon#enter sib2, iclass 20, count 2 2006.173.19:27:55.95#ibcon#flushed, iclass 20, count 2 2006.173.19:27:55.95#ibcon#about to write, iclass 20, count 2 2006.173.19:27:55.95#ibcon#wrote, iclass 20, count 2 2006.173.19:27:55.95#ibcon#about to read 3, iclass 20, count 2 2006.173.19:27:55.98#ibcon#read 3, iclass 20, count 2 2006.173.19:27:55.98#ibcon#about to read 4, iclass 20, count 2 2006.173.19:27:55.98#ibcon#read 4, iclass 20, count 2 2006.173.19:27:55.98#ibcon#about to read 5, iclass 20, count 2 2006.173.19:27:55.98#ibcon#read 5, iclass 20, count 2 2006.173.19:27:55.98#ibcon#about to read 6, iclass 20, count 2 2006.173.19:27:55.98#ibcon#read 6, iclass 20, count 2 2006.173.19:27:55.98#ibcon#end of sib2, iclass 20, count 2 2006.173.19:27:55.98#ibcon#*after write, iclass 20, count 2 2006.173.19:27:55.98#ibcon#*before return 0, iclass 20, count 2 2006.173.19:27:55.98#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.19:27:55.98#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.19:27:55.98#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.19:27:55.98#ibcon#ireg 7 cls_cnt 0 2006.173.19:27:55.98#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.19:27:56.10#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.19:27:56.10#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.19:27:56.10#ibcon#enter wrdev, iclass 20, count 0 2006.173.19:27:56.10#ibcon#first serial, iclass 20, count 0 2006.173.19:27:56.10#ibcon#enter sib2, iclass 20, count 0 2006.173.19:27:56.10#ibcon#flushed, iclass 20, count 0 2006.173.19:27:56.10#ibcon#about to write, iclass 20, count 0 2006.173.19:27:56.10#ibcon#wrote, iclass 20, count 0 2006.173.19:27:56.10#ibcon#about to read 3, iclass 20, count 0 2006.173.19:27:56.12#ibcon#read 3, iclass 20, count 0 2006.173.19:27:56.12#ibcon#about to read 4, iclass 20, count 0 2006.173.19:27:56.12#ibcon#read 4, iclass 20, count 0 2006.173.19:27:56.12#ibcon#about to read 5, iclass 20, count 0 2006.173.19:27:56.12#ibcon#read 5, iclass 20, count 0 2006.173.19:27:56.12#ibcon#about to read 6, iclass 20, count 0 2006.173.19:27:56.12#ibcon#read 6, iclass 20, count 0 2006.173.19:27:56.12#ibcon#end of sib2, iclass 20, count 0 2006.173.19:27:56.12#ibcon#*mode == 0, iclass 20, count 0 2006.173.19:27:56.12#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.19:27:56.12#ibcon#[27=USB\r\n] 2006.173.19:27:56.12#ibcon#*before write, iclass 20, count 0 2006.173.19:27:56.12#ibcon#enter sib2, iclass 20, count 0 2006.173.19:27:56.12#ibcon#flushed, iclass 20, count 0 2006.173.19:27:56.12#ibcon#about to write, iclass 20, count 0 2006.173.19:27:56.12#ibcon#wrote, iclass 20, count 0 2006.173.19:27:56.12#ibcon#about to read 3, iclass 20, count 0 2006.173.19:27:56.15#ibcon#read 3, iclass 20, count 0 2006.173.19:27:56.15#ibcon#about to read 4, iclass 20, count 0 2006.173.19:27:56.15#ibcon#read 4, iclass 20, count 0 2006.173.19:27:56.15#ibcon#about to read 5, iclass 20, count 0 2006.173.19:27:56.15#ibcon#read 5, iclass 20, count 0 2006.173.19:27:56.15#ibcon#about to read 6, iclass 20, count 0 2006.173.19:27:56.15#ibcon#read 6, iclass 20, count 0 2006.173.19:27:56.15#ibcon#end of sib2, iclass 20, count 0 2006.173.19:27:56.15#ibcon#*after write, iclass 20, count 0 2006.173.19:27:56.15#ibcon#*before return 0, iclass 20, count 0 2006.173.19:27:56.15#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.19:27:56.15#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.19:27:56.15#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.19:27:56.15#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.19:27:56.15$vck44/vblo=5,709.99 2006.173.19:27:56.15#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.19:27:56.15#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.19:27:56.15#ibcon#ireg 17 cls_cnt 0 2006.173.19:27:56.15#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.19:27:56.15#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.19:27:56.15#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.19:27:56.15#ibcon#enter wrdev, iclass 22, count 0 2006.173.19:27:56.15#ibcon#first serial, iclass 22, count 0 2006.173.19:27:56.15#ibcon#enter sib2, iclass 22, count 0 2006.173.19:27:56.15#ibcon#flushed, iclass 22, count 0 2006.173.19:27:56.15#ibcon#about to write, iclass 22, count 0 2006.173.19:27:56.15#ibcon#wrote, iclass 22, count 0 2006.173.19:27:56.15#ibcon#about to read 3, iclass 22, count 0 2006.173.19:27:56.17#ibcon#read 3, iclass 22, count 0 2006.173.19:27:56.17#ibcon#about to read 4, iclass 22, count 0 2006.173.19:27:56.17#ibcon#read 4, iclass 22, count 0 2006.173.19:27:56.17#ibcon#about to read 5, iclass 22, count 0 2006.173.19:27:56.17#ibcon#read 5, iclass 22, count 0 2006.173.19:27:56.17#ibcon#about to read 6, iclass 22, count 0 2006.173.19:27:56.17#ibcon#read 6, iclass 22, count 0 2006.173.19:27:56.17#ibcon#end of sib2, iclass 22, count 0 2006.173.19:27:56.17#ibcon#*mode == 0, iclass 22, count 0 2006.173.19:27:56.17#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.19:27:56.17#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.19:27:56.17#ibcon#*before write, iclass 22, count 0 2006.173.19:27:56.17#ibcon#enter sib2, iclass 22, count 0 2006.173.19:27:56.17#ibcon#flushed, iclass 22, count 0 2006.173.19:27:56.17#ibcon#about to write, iclass 22, count 0 2006.173.19:27:56.17#ibcon#wrote, iclass 22, count 0 2006.173.19:27:56.17#ibcon#about to read 3, iclass 22, count 0 2006.173.19:27:56.21#ibcon#read 3, iclass 22, count 0 2006.173.19:27:56.21#ibcon#about to read 4, iclass 22, count 0 2006.173.19:27:56.21#ibcon#read 4, iclass 22, count 0 2006.173.19:27:56.21#ibcon#about to read 5, iclass 22, count 0 2006.173.19:27:56.21#ibcon#read 5, iclass 22, count 0 2006.173.19:27:56.21#ibcon#about to read 6, iclass 22, count 0 2006.173.19:27:56.21#ibcon#read 6, iclass 22, count 0 2006.173.19:27:56.21#ibcon#end of sib2, iclass 22, count 0 2006.173.19:27:56.21#ibcon#*after write, iclass 22, count 0 2006.173.19:27:56.21#ibcon#*before return 0, iclass 22, count 0 2006.173.19:27:56.21#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.19:27:56.21#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.19:27:56.21#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.19:27:56.21#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.19:27:56.21$vck44/vb=5,4 2006.173.19:27:56.21#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.19:27:56.21#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.19:27:56.21#ibcon#ireg 11 cls_cnt 2 2006.173.19:27:56.21#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.19:27:56.27#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.19:27:56.27#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.19:27:56.27#ibcon#enter wrdev, iclass 24, count 2 2006.173.19:27:56.27#ibcon#first serial, iclass 24, count 2 2006.173.19:27:56.27#ibcon#enter sib2, iclass 24, count 2 2006.173.19:27:56.27#ibcon#flushed, iclass 24, count 2 2006.173.19:27:56.27#ibcon#about to write, iclass 24, count 2 2006.173.19:27:56.27#ibcon#wrote, iclass 24, count 2 2006.173.19:27:56.27#ibcon#about to read 3, iclass 24, count 2 2006.173.19:27:56.29#ibcon#read 3, iclass 24, count 2 2006.173.19:27:56.29#ibcon#about to read 4, iclass 24, count 2 2006.173.19:27:56.29#ibcon#read 4, iclass 24, count 2 2006.173.19:27:56.29#ibcon#about to read 5, iclass 24, count 2 2006.173.19:27:56.29#ibcon#read 5, iclass 24, count 2 2006.173.19:27:56.29#ibcon#about to read 6, iclass 24, count 2 2006.173.19:27:56.29#ibcon#read 6, iclass 24, count 2 2006.173.19:27:56.29#ibcon#end of sib2, iclass 24, count 2 2006.173.19:27:56.29#ibcon#*mode == 0, iclass 24, count 2 2006.173.19:27:56.29#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.19:27:56.29#ibcon#[27=AT05-04\r\n] 2006.173.19:27:56.29#ibcon#*before write, iclass 24, count 2 2006.173.19:27:56.29#ibcon#enter sib2, iclass 24, count 2 2006.173.19:27:56.29#ibcon#flushed, iclass 24, count 2 2006.173.19:27:56.29#ibcon#about to write, iclass 24, count 2 2006.173.19:27:56.29#ibcon#wrote, iclass 24, count 2 2006.173.19:27:56.29#ibcon#about to read 3, iclass 24, count 2 2006.173.19:27:56.32#ibcon#read 3, iclass 24, count 2 2006.173.19:27:56.32#ibcon#about to read 4, iclass 24, count 2 2006.173.19:27:56.32#ibcon#read 4, iclass 24, count 2 2006.173.19:27:56.32#ibcon#about to read 5, iclass 24, count 2 2006.173.19:27:56.32#ibcon#read 5, iclass 24, count 2 2006.173.19:27:56.32#ibcon#about to read 6, iclass 24, count 2 2006.173.19:27:56.32#ibcon#read 6, iclass 24, count 2 2006.173.19:27:56.32#ibcon#end of sib2, iclass 24, count 2 2006.173.19:27:56.32#ibcon#*after write, iclass 24, count 2 2006.173.19:27:56.32#ibcon#*before return 0, iclass 24, count 2 2006.173.19:27:56.32#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.19:27:56.32#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.19:27:56.32#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.19:27:56.32#ibcon#ireg 7 cls_cnt 0 2006.173.19:27:56.32#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.19:27:56.44#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.19:27:56.44#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.19:27:56.44#ibcon#enter wrdev, iclass 24, count 0 2006.173.19:27:56.44#ibcon#first serial, iclass 24, count 0 2006.173.19:27:56.44#ibcon#enter sib2, iclass 24, count 0 2006.173.19:27:56.44#ibcon#flushed, iclass 24, count 0 2006.173.19:27:56.44#ibcon#about to write, iclass 24, count 0 2006.173.19:27:56.44#ibcon#wrote, iclass 24, count 0 2006.173.19:27:56.44#ibcon#about to read 3, iclass 24, count 0 2006.173.19:27:56.46#ibcon#read 3, iclass 24, count 0 2006.173.19:27:56.46#ibcon#about to read 4, iclass 24, count 0 2006.173.19:27:56.46#ibcon#read 4, iclass 24, count 0 2006.173.19:27:56.46#ibcon#about to read 5, iclass 24, count 0 2006.173.19:27:56.46#ibcon#read 5, iclass 24, count 0 2006.173.19:27:56.46#ibcon#about to read 6, iclass 24, count 0 2006.173.19:27:56.46#ibcon#read 6, iclass 24, count 0 2006.173.19:27:56.46#ibcon#end of sib2, iclass 24, count 0 2006.173.19:27:56.46#ibcon#*mode == 0, iclass 24, count 0 2006.173.19:27:56.46#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.19:27:56.46#ibcon#[27=USB\r\n] 2006.173.19:27:56.46#ibcon#*before write, iclass 24, count 0 2006.173.19:27:56.46#ibcon#enter sib2, iclass 24, count 0 2006.173.19:27:56.46#ibcon#flushed, iclass 24, count 0 2006.173.19:27:56.46#ibcon#about to write, iclass 24, count 0 2006.173.19:27:56.46#ibcon#wrote, iclass 24, count 0 2006.173.19:27:56.46#ibcon#about to read 3, iclass 24, count 0 2006.173.19:27:56.49#ibcon#read 3, iclass 24, count 0 2006.173.19:27:56.49#ibcon#about to read 4, iclass 24, count 0 2006.173.19:27:56.49#ibcon#read 4, iclass 24, count 0 2006.173.19:27:56.49#ibcon#about to read 5, iclass 24, count 0 2006.173.19:27:56.49#ibcon#read 5, iclass 24, count 0 2006.173.19:27:56.49#ibcon#about to read 6, iclass 24, count 0 2006.173.19:27:56.49#ibcon#read 6, iclass 24, count 0 2006.173.19:27:56.49#ibcon#end of sib2, iclass 24, count 0 2006.173.19:27:56.49#ibcon#*after write, iclass 24, count 0 2006.173.19:27:56.49#ibcon#*before return 0, iclass 24, count 0 2006.173.19:27:56.49#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.19:27:56.49#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.19:27:56.49#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.19:27:56.49#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.19:27:56.49$vck44/vblo=6,719.99 2006.173.19:27:56.49#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.19:27:56.49#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.19:27:56.49#ibcon#ireg 17 cls_cnt 0 2006.173.19:27:56.49#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.19:27:56.49#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.19:27:56.49#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.19:27:56.49#ibcon#enter wrdev, iclass 26, count 0 2006.173.19:27:56.49#ibcon#first serial, iclass 26, count 0 2006.173.19:27:56.49#ibcon#enter sib2, iclass 26, count 0 2006.173.19:27:56.49#ibcon#flushed, iclass 26, count 0 2006.173.19:27:56.49#ibcon#about to write, iclass 26, count 0 2006.173.19:27:56.49#ibcon#wrote, iclass 26, count 0 2006.173.19:27:56.49#ibcon#about to read 3, iclass 26, count 0 2006.173.19:27:56.51#ibcon#read 3, iclass 26, count 0 2006.173.19:27:56.51#ibcon#about to read 4, iclass 26, count 0 2006.173.19:27:56.51#ibcon#read 4, iclass 26, count 0 2006.173.19:27:56.51#ibcon#about to read 5, iclass 26, count 0 2006.173.19:27:56.51#ibcon#read 5, iclass 26, count 0 2006.173.19:27:56.51#ibcon#about to read 6, iclass 26, count 0 2006.173.19:27:56.51#ibcon#read 6, iclass 26, count 0 2006.173.19:27:56.51#ibcon#end of sib2, iclass 26, count 0 2006.173.19:27:56.51#ibcon#*mode == 0, iclass 26, count 0 2006.173.19:27:56.51#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.19:27:56.51#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.19:27:56.51#ibcon#*before write, iclass 26, count 0 2006.173.19:27:56.51#ibcon#enter sib2, iclass 26, count 0 2006.173.19:27:56.51#ibcon#flushed, iclass 26, count 0 2006.173.19:27:56.51#ibcon#about to write, iclass 26, count 0 2006.173.19:27:56.51#ibcon#wrote, iclass 26, count 0 2006.173.19:27:56.51#ibcon#about to read 3, iclass 26, count 0 2006.173.19:27:56.55#ibcon#read 3, iclass 26, count 0 2006.173.19:27:56.55#ibcon#about to read 4, iclass 26, count 0 2006.173.19:27:56.55#ibcon#read 4, iclass 26, count 0 2006.173.19:27:56.55#ibcon#about to read 5, iclass 26, count 0 2006.173.19:27:56.55#ibcon#read 5, iclass 26, count 0 2006.173.19:27:56.55#ibcon#about to read 6, iclass 26, count 0 2006.173.19:27:56.55#ibcon#read 6, iclass 26, count 0 2006.173.19:27:56.55#ibcon#end of sib2, iclass 26, count 0 2006.173.19:27:56.55#ibcon#*after write, iclass 26, count 0 2006.173.19:27:56.55#ibcon#*before return 0, iclass 26, count 0 2006.173.19:27:56.55#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.19:27:56.55#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.19:27:56.55#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.19:27:56.55#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.19:27:56.55$vck44/vb=6,4 2006.173.19:27:56.55#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.19:27:56.55#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.19:27:56.55#ibcon#ireg 11 cls_cnt 2 2006.173.19:27:56.55#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.19:27:56.61#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.19:27:56.61#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.19:27:56.61#ibcon#enter wrdev, iclass 28, count 2 2006.173.19:27:56.61#ibcon#first serial, iclass 28, count 2 2006.173.19:27:56.61#ibcon#enter sib2, iclass 28, count 2 2006.173.19:27:56.61#ibcon#flushed, iclass 28, count 2 2006.173.19:27:56.61#ibcon#about to write, iclass 28, count 2 2006.173.19:27:56.61#ibcon#wrote, iclass 28, count 2 2006.173.19:27:56.61#ibcon#about to read 3, iclass 28, count 2 2006.173.19:27:56.63#ibcon#read 3, iclass 28, count 2 2006.173.19:27:56.63#ibcon#about to read 4, iclass 28, count 2 2006.173.19:27:56.63#ibcon#read 4, iclass 28, count 2 2006.173.19:27:56.63#ibcon#about to read 5, iclass 28, count 2 2006.173.19:27:56.63#ibcon#read 5, iclass 28, count 2 2006.173.19:27:56.63#ibcon#about to read 6, iclass 28, count 2 2006.173.19:27:56.63#ibcon#read 6, iclass 28, count 2 2006.173.19:27:56.63#ibcon#end of sib2, iclass 28, count 2 2006.173.19:27:56.63#ibcon#*mode == 0, iclass 28, count 2 2006.173.19:27:56.63#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.19:27:56.63#ibcon#[27=AT06-04\r\n] 2006.173.19:27:56.63#ibcon#*before write, iclass 28, count 2 2006.173.19:27:56.63#ibcon#enter sib2, iclass 28, count 2 2006.173.19:27:56.63#ibcon#flushed, iclass 28, count 2 2006.173.19:27:56.63#ibcon#about to write, iclass 28, count 2 2006.173.19:27:56.63#ibcon#wrote, iclass 28, count 2 2006.173.19:27:56.63#ibcon#about to read 3, iclass 28, count 2 2006.173.19:27:56.66#ibcon#read 3, iclass 28, count 2 2006.173.19:27:56.66#ibcon#about to read 4, iclass 28, count 2 2006.173.19:27:56.66#ibcon#read 4, iclass 28, count 2 2006.173.19:27:56.66#ibcon#about to read 5, iclass 28, count 2 2006.173.19:27:56.66#ibcon#read 5, iclass 28, count 2 2006.173.19:27:56.66#ibcon#about to read 6, iclass 28, count 2 2006.173.19:27:56.66#ibcon#read 6, iclass 28, count 2 2006.173.19:27:56.66#ibcon#end of sib2, iclass 28, count 2 2006.173.19:27:56.66#ibcon#*after write, iclass 28, count 2 2006.173.19:27:56.66#ibcon#*before return 0, iclass 28, count 2 2006.173.19:27:56.66#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.19:27:56.66#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.19:27:56.66#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.19:27:56.66#ibcon#ireg 7 cls_cnt 0 2006.173.19:27:56.66#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.19:27:56.78#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.19:27:56.78#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.19:27:56.78#ibcon#enter wrdev, iclass 28, count 0 2006.173.19:27:56.78#ibcon#first serial, iclass 28, count 0 2006.173.19:27:56.78#ibcon#enter sib2, iclass 28, count 0 2006.173.19:27:56.78#ibcon#flushed, iclass 28, count 0 2006.173.19:27:56.78#ibcon#about to write, iclass 28, count 0 2006.173.19:27:56.78#ibcon#wrote, iclass 28, count 0 2006.173.19:27:56.78#ibcon#about to read 3, iclass 28, count 0 2006.173.19:27:56.80#ibcon#read 3, iclass 28, count 0 2006.173.19:27:56.80#ibcon#about to read 4, iclass 28, count 0 2006.173.19:27:56.80#ibcon#read 4, iclass 28, count 0 2006.173.19:27:56.80#ibcon#about to read 5, iclass 28, count 0 2006.173.19:27:56.80#ibcon#read 5, iclass 28, count 0 2006.173.19:27:56.80#ibcon#about to read 6, iclass 28, count 0 2006.173.19:27:56.80#ibcon#read 6, iclass 28, count 0 2006.173.19:27:56.80#ibcon#end of sib2, iclass 28, count 0 2006.173.19:27:56.80#ibcon#*mode == 0, iclass 28, count 0 2006.173.19:27:56.80#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.19:27:56.80#ibcon#[27=USB\r\n] 2006.173.19:27:56.80#ibcon#*before write, iclass 28, count 0 2006.173.19:27:56.80#ibcon#enter sib2, iclass 28, count 0 2006.173.19:27:56.80#ibcon#flushed, iclass 28, count 0 2006.173.19:27:56.80#ibcon#about to write, iclass 28, count 0 2006.173.19:27:56.80#ibcon#wrote, iclass 28, count 0 2006.173.19:27:56.80#ibcon#about to read 3, iclass 28, count 0 2006.173.19:27:56.83#ibcon#read 3, iclass 28, count 0 2006.173.19:27:56.83#ibcon#about to read 4, iclass 28, count 0 2006.173.19:27:56.83#ibcon#read 4, iclass 28, count 0 2006.173.19:27:56.83#ibcon#about to read 5, iclass 28, count 0 2006.173.19:27:56.83#ibcon#read 5, iclass 28, count 0 2006.173.19:27:56.83#ibcon#about to read 6, iclass 28, count 0 2006.173.19:27:56.83#ibcon#read 6, iclass 28, count 0 2006.173.19:27:56.83#ibcon#end of sib2, iclass 28, count 0 2006.173.19:27:56.83#ibcon#*after write, iclass 28, count 0 2006.173.19:27:56.83#ibcon#*before return 0, iclass 28, count 0 2006.173.19:27:56.83#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.19:27:56.83#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.19:27:56.83#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.19:27:56.83#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.19:27:56.83$vck44/vblo=7,734.99 2006.173.19:27:56.83#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.19:27:56.83#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.19:27:56.83#ibcon#ireg 17 cls_cnt 0 2006.173.19:27:56.83#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.19:27:56.83#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.19:27:56.83#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.19:27:56.83#ibcon#enter wrdev, iclass 30, count 0 2006.173.19:27:56.83#ibcon#first serial, iclass 30, count 0 2006.173.19:27:56.83#ibcon#enter sib2, iclass 30, count 0 2006.173.19:27:56.83#ibcon#flushed, iclass 30, count 0 2006.173.19:27:56.83#ibcon#about to write, iclass 30, count 0 2006.173.19:27:56.83#ibcon#wrote, iclass 30, count 0 2006.173.19:27:56.83#ibcon#about to read 3, iclass 30, count 0 2006.173.19:27:56.85#ibcon#read 3, iclass 30, count 0 2006.173.19:27:56.85#ibcon#about to read 4, iclass 30, count 0 2006.173.19:27:56.85#ibcon#read 4, iclass 30, count 0 2006.173.19:27:56.85#ibcon#about to read 5, iclass 30, count 0 2006.173.19:27:56.85#ibcon#read 5, iclass 30, count 0 2006.173.19:27:56.85#ibcon#about to read 6, iclass 30, count 0 2006.173.19:27:56.85#ibcon#read 6, iclass 30, count 0 2006.173.19:27:56.85#ibcon#end of sib2, iclass 30, count 0 2006.173.19:27:56.85#ibcon#*mode == 0, iclass 30, count 0 2006.173.19:27:56.85#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.19:27:56.85#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.19:27:56.85#ibcon#*before write, iclass 30, count 0 2006.173.19:27:56.85#ibcon#enter sib2, iclass 30, count 0 2006.173.19:27:56.85#ibcon#flushed, iclass 30, count 0 2006.173.19:27:56.85#ibcon#about to write, iclass 30, count 0 2006.173.19:27:56.85#ibcon#wrote, iclass 30, count 0 2006.173.19:27:56.85#ibcon#about to read 3, iclass 30, count 0 2006.173.19:27:56.89#ibcon#read 3, iclass 30, count 0 2006.173.19:27:56.89#ibcon#about to read 4, iclass 30, count 0 2006.173.19:27:56.89#ibcon#read 4, iclass 30, count 0 2006.173.19:27:56.89#ibcon#about to read 5, iclass 30, count 0 2006.173.19:27:56.89#ibcon#read 5, iclass 30, count 0 2006.173.19:27:56.89#ibcon#about to read 6, iclass 30, count 0 2006.173.19:27:56.89#ibcon#read 6, iclass 30, count 0 2006.173.19:27:56.89#ibcon#end of sib2, iclass 30, count 0 2006.173.19:27:56.89#ibcon#*after write, iclass 30, count 0 2006.173.19:27:56.89#ibcon#*before return 0, iclass 30, count 0 2006.173.19:27:56.89#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.19:27:56.89#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.19:27:56.89#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.19:27:56.89#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.19:27:56.89$vck44/vb=7,4 2006.173.19:27:56.89#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.173.19:27:56.89#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.173.19:27:56.89#ibcon#ireg 11 cls_cnt 2 2006.173.19:27:56.89#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.19:27:56.95#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.19:27:56.95#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.19:27:56.95#ibcon#enter wrdev, iclass 32, count 2 2006.173.19:27:56.95#ibcon#first serial, iclass 32, count 2 2006.173.19:27:56.95#ibcon#enter sib2, iclass 32, count 2 2006.173.19:27:56.95#ibcon#flushed, iclass 32, count 2 2006.173.19:27:56.95#ibcon#about to write, iclass 32, count 2 2006.173.19:27:56.95#ibcon#wrote, iclass 32, count 2 2006.173.19:27:56.95#ibcon#about to read 3, iclass 32, count 2 2006.173.19:27:56.97#ibcon#read 3, iclass 32, count 2 2006.173.19:27:56.97#ibcon#about to read 4, iclass 32, count 2 2006.173.19:27:56.97#ibcon#read 4, iclass 32, count 2 2006.173.19:27:56.97#ibcon#about to read 5, iclass 32, count 2 2006.173.19:27:56.97#ibcon#read 5, iclass 32, count 2 2006.173.19:27:56.97#ibcon#about to read 6, iclass 32, count 2 2006.173.19:27:56.97#ibcon#read 6, iclass 32, count 2 2006.173.19:27:56.97#ibcon#end of sib2, iclass 32, count 2 2006.173.19:27:56.97#ibcon#*mode == 0, iclass 32, count 2 2006.173.19:27:56.97#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.173.19:27:56.97#ibcon#[27=AT07-04\r\n] 2006.173.19:27:56.97#ibcon#*before write, iclass 32, count 2 2006.173.19:27:56.97#ibcon#enter sib2, iclass 32, count 2 2006.173.19:27:56.97#ibcon#flushed, iclass 32, count 2 2006.173.19:27:56.97#ibcon#about to write, iclass 32, count 2 2006.173.19:27:56.97#ibcon#wrote, iclass 32, count 2 2006.173.19:27:56.97#ibcon#about to read 3, iclass 32, count 2 2006.173.19:27:57.00#ibcon#read 3, iclass 32, count 2 2006.173.19:27:57.00#ibcon#about to read 4, iclass 32, count 2 2006.173.19:27:57.00#ibcon#read 4, iclass 32, count 2 2006.173.19:27:57.00#ibcon#about to read 5, iclass 32, count 2 2006.173.19:27:57.00#ibcon#read 5, iclass 32, count 2 2006.173.19:27:57.00#ibcon#about to read 6, iclass 32, count 2 2006.173.19:27:57.00#ibcon#read 6, iclass 32, count 2 2006.173.19:27:57.00#ibcon#end of sib2, iclass 32, count 2 2006.173.19:27:57.00#ibcon#*after write, iclass 32, count 2 2006.173.19:27:57.00#ibcon#*before return 0, iclass 32, count 2 2006.173.19:27:57.00#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.19:27:57.00#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.173.19:27:57.00#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.173.19:27:57.00#ibcon#ireg 7 cls_cnt 0 2006.173.19:27:57.00#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.19:27:57.12#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.19:27:57.12#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.19:27:57.12#ibcon#enter wrdev, iclass 32, count 0 2006.173.19:27:57.12#ibcon#first serial, iclass 32, count 0 2006.173.19:27:57.12#ibcon#enter sib2, iclass 32, count 0 2006.173.19:27:57.12#ibcon#flushed, iclass 32, count 0 2006.173.19:27:57.12#ibcon#about to write, iclass 32, count 0 2006.173.19:27:57.12#ibcon#wrote, iclass 32, count 0 2006.173.19:27:57.12#ibcon#about to read 3, iclass 32, count 0 2006.173.19:27:57.14#ibcon#read 3, iclass 32, count 0 2006.173.19:27:57.14#ibcon#about to read 4, iclass 32, count 0 2006.173.19:27:57.14#ibcon#read 4, iclass 32, count 0 2006.173.19:27:57.14#ibcon#about to read 5, iclass 32, count 0 2006.173.19:27:57.14#ibcon#read 5, iclass 32, count 0 2006.173.19:27:57.14#ibcon#about to read 6, iclass 32, count 0 2006.173.19:27:57.14#ibcon#read 6, iclass 32, count 0 2006.173.19:27:57.14#ibcon#end of sib2, iclass 32, count 0 2006.173.19:27:57.14#ibcon#*mode == 0, iclass 32, count 0 2006.173.19:27:57.14#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.19:27:57.14#ibcon#[27=USB\r\n] 2006.173.19:27:57.14#ibcon#*before write, iclass 32, count 0 2006.173.19:27:57.14#ibcon#enter sib2, iclass 32, count 0 2006.173.19:27:57.14#ibcon#flushed, iclass 32, count 0 2006.173.19:27:57.14#ibcon#about to write, iclass 32, count 0 2006.173.19:27:57.14#ibcon#wrote, iclass 32, count 0 2006.173.19:27:57.14#ibcon#about to read 3, iclass 32, count 0 2006.173.19:27:57.17#ibcon#read 3, iclass 32, count 0 2006.173.19:27:57.17#ibcon#about to read 4, iclass 32, count 0 2006.173.19:27:57.17#ibcon#read 4, iclass 32, count 0 2006.173.19:27:57.17#ibcon#about to read 5, iclass 32, count 0 2006.173.19:27:57.17#ibcon#read 5, iclass 32, count 0 2006.173.19:27:57.17#ibcon#about to read 6, iclass 32, count 0 2006.173.19:27:57.17#ibcon#read 6, iclass 32, count 0 2006.173.19:27:57.17#ibcon#end of sib2, iclass 32, count 0 2006.173.19:27:57.17#ibcon#*after write, iclass 32, count 0 2006.173.19:27:57.17#ibcon#*before return 0, iclass 32, count 0 2006.173.19:27:57.17#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.19:27:57.17#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.173.19:27:57.17#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.19:27:57.17#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.19:27:57.17$vck44/vblo=8,744.99 2006.173.19:27:57.17#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.19:27:57.17#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.19:27:57.17#ibcon#ireg 17 cls_cnt 0 2006.173.19:27:57.17#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.19:27:57.17#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.19:27:57.17#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.19:27:57.17#ibcon#enter wrdev, iclass 34, count 0 2006.173.19:27:57.17#ibcon#first serial, iclass 34, count 0 2006.173.19:27:57.17#ibcon#enter sib2, iclass 34, count 0 2006.173.19:27:57.17#ibcon#flushed, iclass 34, count 0 2006.173.19:27:57.17#ibcon#about to write, iclass 34, count 0 2006.173.19:27:57.17#ibcon#wrote, iclass 34, count 0 2006.173.19:27:57.17#ibcon#about to read 3, iclass 34, count 0 2006.173.19:27:57.19#ibcon#read 3, iclass 34, count 0 2006.173.19:27:57.19#ibcon#about to read 4, iclass 34, count 0 2006.173.19:27:57.19#ibcon#read 4, iclass 34, count 0 2006.173.19:27:57.19#ibcon#about to read 5, iclass 34, count 0 2006.173.19:27:57.19#ibcon#read 5, iclass 34, count 0 2006.173.19:27:57.19#ibcon#about to read 6, iclass 34, count 0 2006.173.19:27:57.19#ibcon#read 6, iclass 34, count 0 2006.173.19:27:57.19#ibcon#end of sib2, iclass 34, count 0 2006.173.19:27:57.19#ibcon#*mode == 0, iclass 34, count 0 2006.173.19:27:57.19#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.19:27:57.19#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.19:27:57.19#ibcon#*before write, iclass 34, count 0 2006.173.19:27:57.19#ibcon#enter sib2, iclass 34, count 0 2006.173.19:27:57.19#ibcon#flushed, iclass 34, count 0 2006.173.19:27:57.19#ibcon#about to write, iclass 34, count 0 2006.173.19:27:57.19#ibcon#wrote, iclass 34, count 0 2006.173.19:27:57.19#ibcon#about to read 3, iclass 34, count 0 2006.173.19:27:57.23#ibcon#read 3, iclass 34, count 0 2006.173.19:27:57.23#ibcon#about to read 4, iclass 34, count 0 2006.173.19:27:57.23#ibcon#read 4, iclass 34, count 0 2006.173.19:27:57.23#ibcon#about to read 5, iclass 34, count 0 2006.173.19:27:57.23#ibcon#read 5, iclass 34, count 0 2006.173.19:27:57.23#ibcon#about to read 6, iclass 34, count 0 2006.173.19:27:57.23#ibcon#read 6, iclass 34, count 0 2006.173.19:27:57.23#ibcon#end of sib2, iclass 34, count 0 2006.173.19:27:57.23#ibcon#*after write, iclass 34, count 0 2006.173.19:27:57.23#ibcon#*before return 0, iclass 34, count 0 2006.173.19:27:57.23#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.19:27:57.23#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.19:27:57.23#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.19:27:57.23#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.19:27:57.23$vck44/vb=8,4 2006.173.19:27:57.23#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.19:27:57.23#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.19:27:57.23#ibcon#ireg 11 cls_cnt 2 2006.173.19:27:57.23#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.19:27:57.29#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.19:27:57.29#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.19:27:57.29#ibcon#enter wrdev, iclass 36, count 2 2006.173.19:27:57.29#ibcon#first serial, iclass 36, count 2 2006.173.19:27:57.29#ibcon#enter sib2, iclass 36, count 2 2006.173.19:27:57.29#ibcon#flushed, iclass 36, count 2 2006.173.19:27:57.29#ibcon#about to write, iclass 36, count 2 2006.173.19:27:57.29#ibcon#wrote, iclass 36, count 2 2006.173.19:27:57.29#ibcon#about to read 3, iclass 36, count 2 2006.173.19:27:57.31#ibcon#read 3, iclass 36, count 2 2006.173.19:27:57.31#ibcon#about to read 4, iclass 36, count 2 2006.173.19:27:57.31#ibcon#read 4, iclass 36, count 2 2006.173.19:27:57.31#ibcon#about to read 5, iclass 36, count 2 2006.173.19:27:57.31#ibcon#read 5, iclass 36, count 2 2006.173.19:27:57.31#ibcon#about to read 6, iclass 36, count 2 2006.173.19:27:57.31#ibcon#read 6, iclass 36, count 2 2006.173.19:27:57.31#ibcon#end of sib2, iclass 36, count 2 2006.173.19:27:57.31#ibcon#*mode == 0, iclass 36, count 2 2006.173.19:27:57.31#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.19:27:57.31#ibcon#[27=AT08-04\r\n] 2006.173.19:27:57.31#ibcon#*before write, iclass 36, count 2 2006.173.19:27:57.31#ibcon#enter sib2, iclass 36, count 2 2006.173.19:27:57.31#ibcon#flushed, iclass 36, count 2 2006.173.19:27:57.31#ibcon#about to write, iclass 36, count 2 2006.173.19:27:57.31#ibcon#wrote, iclass 36, count 2 2006.173.19:27:57.31#ibcon#about to read 3, iclass 36, count 2 2006.173.19:27:57.34#ibcon#read 3, iclass 36, count 2 2006.173.19:27:57.34#ibcon#about to read 4, iclass 36, count 2 2006.173.19:27:57.34#ibcon#read 4, iclass 36, count 2 2006.173.19:27:57.34#ibcon#about to read 5, iclass 36, count 2 2006.173.19:27:57.34#ibcon#read 5, iclass 36, count 2 2006.173.19:27:57.34#ibcon#about to read 6, iclass 36, count 2 2006.173.19:27:57.34#ibcon#read 6, iclass 36, count 2 2006.173.19:27:57.34#ibcon#end of sib2, iclass 36, count 2 2006.173.19:27:57.34#ibcon#*after write, iclass 36, count 2 2006.173.19:27:57.34#ibcon#*before return 0, iclass 36, count 2 2006.173.19:27:57.34#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.19:27:57.34#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.19:27:57.34#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.19:27:57.34#ibcon#ireg 7 cls_cnt 0 2006.173.19:27:57.34#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.19:27:57.46#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.19:27:57.46#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.19:27:57.46#ibcon#enter wrdev, iclass 36, count 0 2006.173.19:27:57.46#ibcon#first serial, iclass 36, count 0 2006.173.19:27:57.46#ibcon#enter sib2, iclass 36, count 0 2006.173.19:27:57.46#ibcon#flushed, iclass 36, count 0 2006.173.19:27:57.46#ibcon#about to write, iclass 36, count 0 2006.173.19:27:57.46#ibcon#wrote, iclass 36, count 0 2006.173.19:27:57.46#ibcon#about to read 3, iclass 36, count 0 2006.173.19:27:57.48#ibcon#read 3, iclass 36, count 0 2006.173.19:27:57.48#ibcon#about to read 4, iclass 36, count 0 2006.173.19:27:57.48#ibcon#read 4, iclass 36, count 0 2006.173.19:27:57.48#ibcon#about to read 5, iclass 36, count 0 2006.173.19:27:57.48#ibcon#read 5, iclass 36, count 0 2006.173.19:27:57.48#ibcon#about to read 6, iclass 36, count 0 2006.173.19:27:57.48#ibcon#read 6, iclass 36, count 0 2006.173.19:27:57.48#ibcon#end of sib2, iclass 36, count 0 2006.173.19:27:57.48#ibcon#*mode == 0, iclass 36, count 0 2006.173.19:27:57.48#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.19:27:57.48#ibcon#[27=USB\r\n] 2006.173.19:27:57.48#ibcon#*before write, iclass 36, count 0 2006.173.19:27:57.48#ibcon#enter sib2, iclass 36, count 0 2006.173.19:27:57.48#ibcon#flushed, iclass 36, count 0 2006.173.19:27:57.48#ibcon#about to write, iclass 36, count 0 2006.173.19:27:57.48#ibcon#wrote, iclass 36, count 0 2006.173.19:27:57.48#ibcon#about to read 3, iclass 36, count 0 2006.173.19:27:57.51#ibcon#read 3, iclass 36, count 0 2006.173.19:27:57.51#ibcon#about to read 4, iclass 36, count 0 2006.173.19:27:57.51#ibcon#read 4, iclass 36, count 0 2006.173.19:27:57.51#ibcon#about to read 5, iclass 36, count 0 2006.173.19:27:57.51#ibcon#read 5, iclass 36, count 0 2006.173.19:27:57.51#ibcon#about to read 6, iclass 36, count 0 2006.173.19:27:57.51#ibcon#read 6, iclass 36, count 0 2006.173.19:27:57.51#ibcon#end of sib2, iclass 36, count 0 2006.173.19:27:57.51#ibcon#*after write, iclass 36, count 0 2006.173.19:27:57.51#ibcon#*before return 0, iclass 36, count 0 2006.173.19:27:57.51#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.19:27:57.51#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.19:27:57.51#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.19:27:57.51#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.19:27:57.51$vck44/vabw=wide 2006.173.19:27:57.51#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.19:27:57.51#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.19:27:57.51#ibcon#ireg 8 cls_cnt 0 2006.173.19:27:57.51#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.19:27:57.51#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.19:27:57.51#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.19:27:57.51#ibcon#enter wrdev, iclass 38, count 0 2006.173.19:27:57.51#ibcon#first serial, iclass 38, count 0 2006.173.19:27:57.51#ibcon#enter sib2, iclass 38, count 0 2006.173.19:27:57.51#ibcon#flushed, iclass 38, count 0 2006.173.19:27:57.51#ibcon#about to write, iclass 38, count 0 2006.173.19:27:57.51#ibcon#wrote, iclass 38, count 0 2006.173.19:27:57.51#ibcon#about to read 3, iclass 38, count 0 2006.173.19:27:57.53#ibcon#read 3, iclass 38, count 0 2006.173.19:27:57.53#ibcon#about to read 4, iclass 38, count 0 2006.173.19:27:57.53#ibcon#read 4, iclass 38, count 0 2006.173.19:27:57.53#ibcon#about to read 5, iclass 38, count 0 2006.173.19:27:57.53#ibcon#read 5, iclass 38, count 0 2006.173.19:27:57.53#ibcon#about to read 6, iclass 38, count 0 2006.173.19:27:57.53#ibcon#read 6, iclass 38, count 0 2006.173.19:27:57.53#ibcon#end of sib2, iclass 38, count 0 2006.173.19:27:57.53#ibcon#*mode == 0, iclass 38, count 0 2006.173.19:27:57.53#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.19:27:57.53#ibcon#[25=BW32\r\n] 2006.173.19:27:57.53#ibcon#*before write, iclass 38, count 0 2006.173.19:27:57.53#ibcon#enter sib2, iclass 38, count 0 2006.173.19:27:57.53#ibcon#flushed, iclass 38, count 0 2006.173.19:27:57.53#ibcon#about to write, iclass 38, count 0 2006.173.19:27:57.53#ibcon#wrote, iclass 38, count 0 2006.173.19:27:57.53#ibcon#about to read 3, iclass 38, count 0 2006.173.19:27:57.56#ibcon#read 3, iclass 38, count 0 2006.173.19:27:57.56#ibcon#about to read 4, iclass 38, count 0 2006.173.19:27:57.56#ibcon#read 4, iclass 38, count 0 2006.173.19:27:57.56#ibcon#about to read 5, iclass 38, count 0 2006.173.19:27:57.56#ibcon#read 5, iclass 38, count 0 2006.173.19:27:57.56#ibcon#about to read 6, iclass 38, count 0 2006.173.19:27:57.56#ibcon#read 6, iclass 38, count 0 2006.173.19:27:57.56#ibcon#end of sib2, iclass 38, count 0 2006.173.19:27:57.56#ibcon#*after write, iclass 38, count 0 2006.173.19:27:57.56#ibcon#*before return 0, iclass 38, count 0 2006.173.19:27:57.56#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.19:27:57.56#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.19:27:57.56#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.19:27:57.56#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.19:27:57.56$vck44/vbbw=wide 2006.173.19:27:57.56#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.19:27:57.56#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.19:27:57.56#ibcon#ireg 8 cls_cnt 0 2006.173.19:27:57.56#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.19:27:57.63#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.19:27:57.63#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.19:27:57.63#ibcon#enter wrdev, iclass 40, count 0 2006.173.19:27:57.63#ibcon#first serial, iclass 40, count 0 2006.173.19:27:57.63#ibcon#enter sib2, iclass 40, count 0 2006.173.19:27:57.63#ibcon#flushed, iclass 40, count 0 2006.173.19:27:57.63#ibcon#about to write, iclass 40, count 0 2006.173.19:27:57.63#ibcon#wrote, iclass 40, count 0 2006.173.19:27:57.63#ibcon#about to read 3, iclass 40, count 0 2006.173.19:27:57.65#ibcon#read 3, iclass 40, count 0 2006.173.19:27:57.65#ibcon#about to read 4, iclass 40, count 0 2006.173.19:27:57.65#ibcon#read 4, iclass 40, count 0 2006.173.19:27:57.65#ibcon#about to read 5, iclass 40, count 0 2006.173.19:27:57.65#ibcon#read 5, iclass 40, count 0 2006.173.19:27:57.65#ibcon#about to read 6, iclass 40, count 0 2006.173.19:27:57.65#ibcon#read 6, iclass 40, count 0 2006.173.19:27:57.65#ibcon#end of sib2, iclass 40, count 0 2006.173.19:27:57.65#ibcon#*mode == 0, iclass 40, count 0 2006.173.19:27:57.65#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.19:27:57.65#ibcon#[27=BW32\r\n] 2006.173.19:27:57.65#ibcon#*before write, iclass 40, count 0 2006.173.19:27:57.65#ibcon#enter sib2, iclass 40, count 0 2006.173.19:27:57.65#ibcon#flushed, iclass 40, count 0 2006.173.19:27:57.65#ibcon#about to write, iclass 40, count 0 2006.173.19:27:57.65#ibcon#wrote, iclass 40, count 0 2006.173.19:27:57.65#ibcon#about to read 3, iclass 40, count 0 2006.173.19:27:57.68#ibcon#read 3, iclass 40, count 0 2006.173.19:27:57.68#ibcon#about to read 4, iclass 40, count 0 2006.173.19:27:57.68#ibcon#read 4, iclass 40, count 0 2006.173.19:27:57.68#ibcon#about to read 5, iclass 40, count 0 2006.173.19:27:57.68#ibcon#read 5, iclass 40, count 0 2006.173.19:27:57.68#ibcon#about to read 6, iclass 40, count 0 2006.173.19:27:57.68#ibcon#read 6, iclass 40, count 0 2006.173.19:27:57.68#ibcon#end of sib2, iclass 40, count 0 2006.173.19:27:57.68#ibcon#*after write, iclass 40, count 0 2006.173.19:27:57.68#ibcon#*before return 0, iclass 40, count 0 2006.173.19:27:57.68#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.19:27:57.68#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.19:27:57.68#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.19:27:57.68#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.19:27:57.68$setupk4/ifdk4 2006.173.19:27:57.68$ifdk4/lo= 2006.173.19:27:57.68$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.19:27:57.68$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.19:27:57.68$ifdk4/patch= 2006.173.19:27:57.68$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.19:27:57.68$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.19:27:57.68$setupk4/!*+20s 2006.173.19:27:58.97#abcon#<5=/05 0.4 1.0 19.431001002.4\r\n> 2006.173.19:27:58.99#abcon#{5=INTERFACE CLEAR} 2006.173.19:27:59.05#abcon#[5=S1D000X0/0*\r\n] 2006.173.19:28:09.14#trakl#Source acquired 2006.173.19:28:09.14#abcon#<5=/05 0.5 1.0 19.441001002.4\r\n> 2006.173.19:28:09.16#abcon#{5=INTERFACE CLEAR} 2006.173.19:28:09.22#abcon#[5=S1D000X0/0*\r\n] 2006.173.19:28:11.14#flagr#flagr/antenna,acquired 2006.173.19:28:12.19$setupk4/"tpicd 2006.173.19:28:12.19$setupk4/echo=off 2006.173.19:28:12.19$setupk4/xlog=off 2006.173.19:28:12.19:!2006.173.19:31:08 2006.173.19:31:08.00:preob 2006.173.19:31:09.14/onsource/TRACKING 2006.173.19:31:09.14:!2006.173.19:31:18 2006.173.19:31:18.00:"tape 2006.173.19:31:18.00:"st=record 2006.173.19:31:18.00:data_valid=on 2006.173.19:31:18.00:midob 2006.173.19:31:18.14/onsource/TRACKING 2006.173.19:31:18.14/wx/19.41,1002.5,100 2006.173.19:31:18.24/cable/+6.5164E-03 2006.173.19:31:19.33/va/01,07,usb,yes,35,38 2006.173.19:31:19.33/va/02,06,usb,yes,35,36 2006.173.19:31:19.33/va/03,05,usb,yes,45,47 2006.173.19:31:19.33/va/04,06,usb,yes,36,38 2006.173.19:31:19.33/va/05,04,usb,yes,28,29 2006.173.19:31:19.33/va/06,03,usb,yes,39,39 2006.173.19:31:19.33/va/07,04,usb,yes,32,33 2006.173.19:31:19.33/va/08,04,usb,yes,27,33 2006.173.19:31:19.56/valo/01,524.99,yes,locked 2006.173.19:31:19.56/valo/02,534.99,yes,locked 2006.173.19:31:19.56/valo/03,564.99,yes,locked 2006.173.19:31:19.56/valo/04,624.99,yes,locked 2006.173.19:31:19.56/valo/05,734.99,yes,locked 2006.173.19:31:19.56/valo/06,814.99,yes,locked 2006.173.19:31:19.56/valo/07,864.99,yes,locked 2006.173.19:31:19.56/valo/08,884.99,yes,locked 2006.173.19:31:20.65/vb/01,04,usb,yes,29,27 2006.173.19:31:20.65/vb/02,04,usb,yes,31,31 2006.173.19:31:20.65/vb/03,04,usb,yes,28,31 2006.173.19:31:20.65/vb/04,04,usb,yes,33,32 2006.173.19:31:20.65/vb/05,04,usb,yes,25,28 2006.173.19:31:20.65/vb/06,04,usb,yes,30,26 2006.173.19:31:20.65/vb/07,04,usb,yes,29,29 2006.173.19:31:20.65/vb/08,04,usb,yes,27,30 2006.173.19:31:20.88/vblo/01,629.99,yes,locked 2006.173.19:31:20.88/vblo/02,634.99,yes,locked 2006.173.19:31:20.88/vblo/03,649.99,yes,locked 2006.173.19:31:20.88/vblo/04,679.99,yes,locked 2006.173.19:31:20.88/vblo/05,709.99,yes,locked 2006.173.19:31:20.88/vblo/06,719.99,yes,locked 2006.173.19:31:20.88/vblo/07,734.99,yes,locked 2006.173.19:31:20.88/vblo/08,744.99,yes,locked 2006.173.19:31:21.03/vabw/8 2006.173.19:31:21.18/vbbw/8 2006.173.19:31:21.27/xfe/off,on,14.7 2006.173.19:31:21.65/ifatt/23,28,28,28 2006.173.19:31:22.07/fmout-gps/S +3.87E-07 2006.173.19:31:22.11:!2006.173.19:31:58 2006.173.19:31:58.00:data_valid=off 2006.173.19:31:58.00:"et 2006.173.19:31:58.00:!+3s 2006.173.19:32:01.01:"tape 2006.173.19:32:01.01:postob 2006.173.19:32:01.20/cable/+6.5145E-03 2006.173.19:32:01.20/wx/19.40,1002.5,100 2006.173.19:32:02.07/fmout-gps/S +3.87E-07 2006.173.19:32:02.07:scan_name=173-1932,jd0606,120 2006.173.19:32:02.07:source=2201+315,220314.98,314538.3,2000.0,ccw 2006.173.19:32:03.14#flagr#flagr/antenna,new-source 2006.173.19:32:03.14:checkk5 2006.173.19:32:03.56/chk_autoobs//k5ts1/ autoobs is running! 2006.173.19:32:03.95/chk_autoobs//k5ts2/ autoobs is running! 2006.173.19:32:04.34/chk_autoobs//k5ts3/ autoobs is running! 2006.173.19:32:04.74/chk_autoobs//k5ts4/ autoobs is running! 2006.173.19:32:05.11/chk_obsdata//k5ts1/T1731931??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.19:32:05.50/chk_obsdata//k5ts2/T1731931??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.19:32:05.89/chk_obsdata//k5ts3/T1731931??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.19:32:06.30/chk_obsdata//k5ts4/T1731931??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.19:32:07.03/k5log//k5ts1_log_newline 2006.173.19:32:07.73/k5log//k5ts2_log_newline 2006.173.19:32:08.43/k5log//k5ts3_log_newline 2006.173.19:32:09.14/k5log//k5ts4_log_newline 2006.173.19:32:09.16/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.19:32:09.16:setupk4=1 2006.173.19:32:09.16$setupk4/echo=on 2006.173.19:32:09.16$setupk4/pcalon 2006.173.19:32:09.16$pcalon/"no phase cal control is implemented here 2006.173.19:32:09.16$setupk4/"tpicd=stop 2006.173.19:32:09.16$setupk4/"rec=synch_on 2006.173.19:32:09.16$setupk4/"rec_mode=128 2006.173.19:32:09.16$setupk4/!* 2006.173.19:32:09.16$setupk4/recpk4 2006.173.19:32:09.16$recpk4/recpatch= 2006.173.19:32:09.17$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.19:32:09.17$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.19:32:09.17$setupk4/vck44 2006.173.19:32:09.17$vck44/valo=1,524.99 2006.173.19:32:09.17#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.19:32:09.17#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.19:32:09.17#ibcon#ireg 17 cls_cnt 0 2006.173.19:32:09.17#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.19:32:09.17#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.19:32:09.17#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.19:32:09.17#ibcon#enter wrdev, iclass 37, count 0 2006.173.19:32:09.17#ibcon#first serial, iclass 37, count 0 2006.173.19:32:09.17#ibcon#enter sib2, iclass 37, count 0 2006.173.19:32:09.17#ibcon#flushed, iclass 37, count 0 2006.173.19:32:09.17#ibcon#about to write, iclass 37, count 0 2006.173.19:32:09.17#ibcon#wrote, iclass 37, count 0 2006.173.19:32:09.17#ibcon#about to read 3, iclass 37, count 0 2006.173.19:32:09.19#ibcon#read 3, iclass 37, count 0 2006.173.19:32:09.19#ibcon#about to read 4, iclass 37, count 0 2006.173.19:32:09.19#ibcon#read 4, iclass 37, count 0 2006.173.19:32:09.19#ibcon#about to read 5, iclass 37, count 0 2006.173.19:32:09.19#ibcon#read 5, iclass 37, count 0 2006.173.19:32:09.19#ibcon#about to read 6, iclass 37, count 0 2006.173.19:32:09.19#ibcon#read 6, iclass 37, count 0 2006.173.19:32:09.19#ibcon#end of sib2, iclass 37, count 0 2006.173.19:32:09.19#ibcon#*mode == 0, iclass 37, count 0 2006.173.19:32:09.19#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.19:32:09.19#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.19:32:09.19#ibcon#*before write, iclass 37, count 0 2006.173.19:32:09.19#ibcon#enter sib2, iclass 37, count 0 2006.173.19:32:09.19#ibcon#flushed, iclass 37, count 0 2006.173.19:32:09.19#ibcon#about to write, iclass 37, count 0 2006.173.19:32:09.19#ibcon#wrote, iclass 37, count 0 2006.173.19:32:09.19#ibcon#about to read 3, iclass 37, count 0 2006.173.19:32:09.24#ibcon#read 3, iclass 37, count 0 2006.173.19:32:09.24#ibcon#about to read 4, iclass 37, count 0 2006.173.19:32:09.24#ibcon#read 4, iclass 37, count 0 2006.173.19:32:09.24#ibcon#about to read 5, iclass 37, count 0 2006.173.19:32:09.24#ibcon#read 5, iclass 37, count 0 2006.173.19:32:09.24#ibcon#about to read 6, iclass 37, count 0 2006.173.19:32:09.24#ibcon#read 6, iclass 37, count 0 2006.173.19:32:09.24#ibcon#end of sib2, iclass 37, count 0 2006.173.19:32:09.24#ibcon#*after write, iclass 37, count 0 2006.173.19:32:09.24#ibcon#*before return 0, iclass 37, count 0 2006.173.19:32:09.24#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.19:32:09.24#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.19:32:09.24#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.19:32:09.24#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.19:32:09.24$vck44/va=1,7 2006.173.19:32:09.24#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.19:32:09.24#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.19:32:09.24#ibcon#ireg 11 cls_cnt 2 2006.173.19:32:09.24#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.19:32:09.24#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.19:32:09.24#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.19:32:09.24#ibcon#enter wrdev, iclass 39, count 2 2006.173.19:32:09.24#ibcon#first serial, iclass 39, count 2 2006.173.19:32:09.24#ibcon#enter sib2, iclass 39, count 2 2006.173.19:32:09.24#ibcon#flushed, iclass 39, count 2 2006.173.19:32:09.24#ibcon#about to write, iclass 39, count 2 2006.173.19:32:09.24#ibcon#wrote, iclass 39, count 2 2006.173.19:32:09.24#ibcon#about to read 3, iclass 39, count 2 2006.173.19:32:09.26#ibcon#read 3, iclass 39, count 2 2006.173.19:32:09.26#ibcon#about to read 4, iclass 39, count 2 2006.173.19:32:09.26#ibcon#read 4, iclass 39, count 2 2006.173.19:32:09.26#ibcon#about to read 5, iclass 39, count 2 2006.173.19:32:09.26#ibcon#read 5, iclass 39, count 2 2006.173.19:32:09.26#ibcon#about to read 6, iclass 39, count 2 2006.173.19:32:09.26#ibcon#read 6, iclass 39, count 2 2006.173.19:32:09.26#ibcon#end of sib2, iclass 39, count 2 2006.173.19:32:09.26#ibcon#*mode == 0, iclass 39, count 2 2006.173.19:32:09.26#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.19:32:09.26#ibcon#[25=AT01-07\r\n] 2006.173.19:32:09.26#ibcon#*before write, iclass 39, count 2 2006.173.19:32:09.26#ibcon#enter sib2, iclass 39, count 2 2006.173.19:32:09.26#ibcon#flushed, iclass 39, count 2 2006.173.19:32:09.26#ibcon#about to write, iclass 39, count 2 2006.173.19:32:09.26#ibcon#wrote, iclass 39, count 2 2006.173.19:32:09.26#ibcon#about to read 3, iclass 39, count 2 2006.173.19:32:09.29#ibcon#read 3, iclass 39, count 2 2006.173.19:32:09.29#ibcon#about to read 4, iclass 39, count 2 2006.173.19:32:09.29#ibcon#read 4, iclass 39, count 2 2006.173.19:32:09.29#ibcon#about to read 5, iclass 39, count 2 2006.173.19:32:09.29#ibcon#read 5, iclass 39, count 2 2006.173.19:32:09.29#ibcon#about to read 6, iclass 39, count 2 2006.173.19:32:09.29#ibcon#read 6, iclass 39, count 2 2006.173.19:32:09.29#ibcon#end of sib2, iclass 39, count 2 2006.173.19:32:09.29#ibcon#*after write, iclass 39, count 2 2006.173.19:32:09.29#ibcon#*before return 0, iclass 39, count 2 2006.173.19:32:09.29#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.19:32:09.29#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.19:32:09.29#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.19:32:09.29#ibcon#ireg 7 cls_cnt 0 2006.173.19:32:09.29#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.19:32:09.41#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.19:32:09.41#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.19:32:09.41#ibcon#enter wrdev, iclass 39, count 0 2006.173.19:32:09.41#ibcon#first serial, iclass 39, count 0 2006.173.19:32:09.41#ibcon#enter sib2, iclass 39, count 0 2006.173.19:32:09.41#ibcon#flushed, iclass 39, count 0 2006.173.19:32:09.41#ibcon#about to write, iclass 39, count 0 2006.173.19:32:09.41#ibcon#wrote, iclass 39, count 0 2006.173.19:32:09.41#ibcon#about to read 3, iclass 39, count 0 2006.173.19:32:09.43#ibcon#read 3, iclass 39, count 0 2006.173.19:32:09.43#ibcon#about to read 4, iclass 39, count 0 2006.173.19:32:09.43#ibcon#read 4, iclass 39, count 0 2006.173.19:32:09.43#ibcon#about to read 5, iclass 39, count 0 2006.173.19:32:09.43#ibcon#read 5, iclass 39, count 0 2006.173.19:32:09.43#ibcon#about to read 6, iclass 39, count 0 2006.173.19:32:09.43#ibcon#read 6, iclass 39, count 0 2006.173.19:32:09.43#ibcon#end of sib2, iclass 39, count 0 2006.173.19:32:09.43#ibcon#*mode == 0, iclass 39, count 0 2006.173.19:32:09.43#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.19:32:09.43#ibcon#[25=USB\r\n] 2006.173.19:32:09.43#ibcon#*before write, iclass 39, count 0 2006.173.19:32:09.43#ibcon#enter sib2, iclass 39, count 0 2006.173.19:32:09.43#ibcon#flushed, iclass 39, count 0 2006.173.19:32:09.43#ibcon#about to write, iclass 39, count 0 2006.173.19:32:09.43#ibcon#wrote, iclass 39, count 0 2006.173.19:32:09.43#ibcon#about to read 3, iclass 39, count 0 2006.173.19:32:09.46#ibcon#read 3, iclass 39, count 0 2006.173.19:32:09.46#ibcon#about to read 4, iclass 39, count 0 2006.173.19:32:09.46#ibcon#read 4, iclass 39, count 0 2006.173.19:32:09.46#ibcon#about to read 5, iclass 39, count 0 2006.173.19:32:09.46#ibcon#read 5, iclass 39, count 0 2006.173.19:32:09.46#ibcon#about to read 6, iclass 39, count 0 2006.173.19:32:09.46#ibcon#read 6, iclass 39, count 0 2006.173.19:32:09.46#ibcon#end of sib2, iclass 39, count 0 2006.173.19:32:09.46#ibcon#*after write, iclass 39, count 0 2006.173.19:32:09.46#ibcon#*before return 0, iclass 39, count 0 2006.173.19:32:09.46#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.19:32:09.46#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.19:32:09.46#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.19:32:09.46#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.19:32:09.46$vck44/valo=2,534.99 2006.173.19:32:09.46#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.19:32:09.46#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.19:32:09.46#ibcon#ireg 17 cls_cnt 0 2006.173.19:32:09.46#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.19:32:09.46#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.19:32:09.46#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.19:32:09.46#ibcon#enter wrdev, iclass 3, count 0 2006.173.19:32:09.46#ibcon#first serial, iclass 3, count 0 2006.173.19:32:09.46#ibcon#enter sib2, iclass 3, count 0 2006.173.19:32:09.46#ibcon#flushed, iclass 3, count 0 2006.173.19:32:09.46#ibcon#about to write, iclass 3, count 0 2006.173.19:32:09.46#ibcon#wrote, iclass 3, count 0 2006.173.19:32:09.46#ibcon#about to read 3, iclass 3, count 0 2006.173.19:32:09.48#ibcon#read 3, iclass 3, count 0 2006.173.19:32:09.48#ibcon#about to read 4, iclass 3, count 0 2006.173.19:32:09.48#ibcon#read 4, iclass 3, count 0 2006.173.19:32:09.48#ibcon#about to read 5, iclass 3, count 0 2006.173.19:32:09.48#ibcon#read 5, iclass 3, count 0 2006.173.19:32:09.48#ibcon#about to read 6, iclass 3, count 0 2006.173.19:32:09.48#ibcon#read 6, iclass 3, count 0 2006.173.19:32:09.48#ibcon#end of sib2, iclass 3, count 0 2006.173.19:32:09.48#ibcon#*mode == 0, iclass 3, count 0 2006.173.19:32:09.48#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.19:32:09.48#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.19:32:09.48#ibcon#*before write, iclass 3, count 0 2006.173.19:32:09.48#ibcon#enter sib2, iclass 3, count 0 2006.173.19:32:09.48#ibcon#flushed, iclass 3, count 0 2006.173.19:32:09.48#ibcon#about to write, iclass 3, count 0 2006.173.19:32:09.48#ibcon#wrote, iclass 3, count 0 2006.173.19:32:09.48#ibcon#about to read 3, iclass 3, count 0 2006.173.19:32:09.52#ibcon#read 3, iclass 3, count 0 2006.173.19:32:09.52#ibcon#about to read 4, iclass 3, count 0 2006.173.19:32:09.52#ibcon#read 4, iclass 3, count 0 2006.173.19:32:09.52#ibcon#about to read 5, iclass 3, count 0 2006.173.19:32:09.52#ibcon#read 5, iclass 3, count 0 2006.173.19:32:09.52#ibcon#about to read 6, iclass 3, count 0 2006.173.19:32:09.52#ibcon#read 6, iclass 3, count 0 2006.173.19:32:09.52#ibcon#end of sib2, iclass 3, count 0 2006.173.19:32:09.52#ibcon#*after write, iclass 3, count 0 2006.173.19:32:09.52#ibcon#*before return 0, iclass 3, count 0 2006.173.19:32:09.52#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.19:32:09.52#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.19:32:09.52#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.19:32:09.52#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.19:32:09.52$vck44/va=2,6 2006.173.19:32:09.52#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.19:32:09.52#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.19:32:09.52#ibcon#ireg 11 cls_cnt 2 2006.173.19:32:09.52#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.19:32:09.58#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.19:32:09.58#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.19:32:09.58#ibcon#enter wrdev, iclass 5, count 2 2006.173.19:32:09.58#ibcon#first serial, iclass 5, count 2 2006.173.19:32:09.58#ibcon#enter sib2, iclass 5, count 2 2006.173.19:32:09.58#ibcon#flushed, iclass 5, count 2 2006.173.19:32:09.58#ibcon#about to write, iclass 5, count 2 2006.173.19:32:09.58#ibcon#wrote, iclass 5, count 2 2006.173.19:32:09.58#ibcon#about to read 3, iclass 5, count 2 2006.173.19:32:09.60#ibcon#read 3, iclass 5, count 2 2006.173.19:32:09.60#ibcon#about to read 4, iclass 5, count 2 2006.173.19:32:09.60#ibcon#read 4, iclass 5, count 2 2006.173.19:32:09.60#ibcon#about to read 5, iclass 5, count 2 2006.173.19:32:09.60#ibcon#read 5, iclass 5, count 2 2006.173.19:32:09.60#ibcon#about to read 6, iclass 5, count 2 2006.173.19:32:09.60#ibcon#read 6, iclass 5, count 2 2006.173.19:32:09.60#ibcon#end of sib2, iclass 5, count 2 2006.173.19:32:09.60#ibcon#*mode == 0, iclass 5, count 2 2006.173.19:32:09.60#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.19:32:09.60#ibcon#[25=AT02-06\r\n] 2006.173.19:32:09.60#ibcon#*before write, iclass 5, count 2 2006.173.19:32:09.60#ibcon#enter sib2, iclass 5, count 2 2006.173.19:32:09.60#ibcon#flushed, iclass 5, count 2 2006.173.19:32:09.60#ibcon#about to write, iclass 5, count 2 2006.173.19:32:09.60#ibcon#wrote, iclass 5, count 2 2006.173.19:32:09.60#ibcon#about to read 3, iclass 5, count 2 2006.173.19:32:09.63#ibcon#read 3, iclass 5, count 2 2006.173.19:32:09.63#ibcon#about to read 4, iclass 5, count 2 2006.173.19:32:09.63#ibcon#read 4, iclass 5, count 2 2006.173.19:32:09.63#ibcon#about to read 5, iclass 5, count 2 2006.173.19:32:09.63#ibcon#read 5, iclass 5, count 2 2006.173.19:32:09.63#ibcon#about to read 6, iclass 5, count 2 2006.173.19:32:09.63#ibcon#read 6, iclass 5, count 2 2006.173.19:32:09.63#ibcon#end of sib2, iclass 5, count 2 2006.173.19:32:09.63#ibcon#*after write, iclass 5, count 2 2006.173.19:32:09.63#ibcon#*before return 0, iclass 5, count 2 2006.173.19:32:09.63#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.19:32:09.63#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.19:32:09.63#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.19:32:09.63#ibcon#ireg 7 cls_cnt 0 2006.173.19:32:09.63#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.19:32:09.75#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.19:32:09.75#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.19:32:09.75#ibcon#enter wrdev, iclass 5, count 0 2006.173.19:32:09.75#ibcon#first serial, iclass 5, count 0 2006.173.19:32:09.75#ibcon#enter sib2, iclass 5, count 0 2006.173.19:32:09.75#ibcon#flushed, iclass 5, count 0 2006.173.19:32:09.75#ibcon#about to write, iclass 5, count 0 2006.173.19:32:09.75#ibcon#wrote, iclass 5, count 0 2006.173.19:32:09.75#ibcon#about to read 3, iclass 5, count 0 2006.173.19:32:09.77#ibcon#read 3, iclass 5, count 0 2006.173.19:32:09.77#ibcon#about to read 4, iclass 5, count 0 2006.173.19:32:09.77#ibcon#read 4, iclass 5, count 0 2006.173.19:32:09.77#ibcon#about to read 5, iclass 5, count 0 2006.173.19:32:09.77#ibcon#read 5, iclass 5, count 0 2006.173.19:32:09.77#ibcon#about to read 6, iclass 5, count 0 2006.173.19:32:09.77#ibcon#read 6, iclass 5, count 0 2006.173.19:32:09.77#ibcon#end of sib2, iclass 5, count 0 2006.173.19:32:09.77#ibcon#*mode == 0, iclass 5, count 0 2006.173.19:32:09.77#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.19:32:09.77#ibcon#[25=USB\r\n] 2006.173.19:32:09.77#ibcon#*before write, iclass 5, count 0 2006.173.19:32:09.77#ibcon#enter sib2, iclass 5, count 0 2006.173.19:32:09.77#ibcon#flushed, iclass 5, count 0 2006.173.19:32:09.77#ibcon#about to write, iclass 5, count 0 2006.173.19:32:09.77#ibcon#wrote, iclass 5, count 0 2006.173.19:32:09.77#ibcon#about to read 3, iclass 5, count 0 2006.173.19:32:09.80#ibcon#read 3, iclass 5, count 0 2006.173.19:32:09.80#ibcon#about to read 4, iclass 5, count 0 2006.173.19:32:09.80#ibcon#read 4, iclass 5, count 0 2006.173.19:32:09.80#ibcon#about to read 5, iclass 5, count 0 2006.173.19:32:09.80#ibcon#read 5, iclass 5, count 0 2006.173.19:32:09.80#ibcon#about to read 6, iclass 5, count 0 2006.173.19:32:09.80#ibcon#read 6, iclass 5, count 0 2006.173.19:32:09.80#ibcon#end of sib2, iclass 5, count 0 2006.173.19:32:09.80#ibcon#*after write, iclass 5, count 0 2006.173.19:32:09.80#ibcon#*before return 0, iclass 5, count 0 2006.173.19:32:09.80#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.19:32:09.80#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.19:32:09.80#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.19:32:09.80#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.19:32:09.80$vck44/valo=3,564.99 2006.173.19:32:09.80#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.19:32:09.80#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.19:32:09.80#ibcon#ireg 17 cls_cnt 0 2006.173.19:32:09.80#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.19:32:09.80#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.19:32:09.80#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.19:32:09.80#ibcon#enter wrdev, iclass 7, count 0 2006.173.19:32:09.80#ibcon#first serial, iclass 7, count 0 2006.173.19:32:09.80#ibcon#enter sib2, iclass 7, count 0 2006.173.19:32:09.80#ibcon#flushed, iclass 7, count 0 2006.173.19:32:09.80#ibcon#about to write, iclass 7, count 0 2006.173.19:32:09.80#ibcon#wrote, iclass 7, count 0 2006.173.19:32:09.80#ibcon#about to read 3, iclass 7, count 0 2006.173.19:32:09.82#ibcon#read 3, iclass 7, count 0 2006.173.19:32:09.82#ibcon#about to read 4, iclass 7, count 0 2006.173.19:32:09.82#ibcon#read 4, iclass 7, count 0 2006.173.19:32:09.82#ibcon#about to read 5, iclass 7, count 0 2006.173.19:32:09.82#ibcon#read 5, iclass 7, count 0 2006.173.19:32:09.82#ibcon#about to read 6, iclass 7, count 0 2006.173.19:32:09.82#ibcon#read 6, iclass 7, count 0 2006.173.19:32:09.82#ibcon#end of sib2, iclass 7, count 0 2006.173.19:32:09.82#ibcon#*mode == 0, iclass 7, count 0 2006.173.19:32:09.82#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.19:32:09.82#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.19:32:09.82#ibcon#*before write, iclass 7, count 0 2006.173.19:32:09.82#ibcon#enter sib2, iclass 7, count 0 2006.173.19:32:09.82#ibcon#flushed, iclass 7, count 0 2006.173.19:32:09.82#ibcon#about to write, iclass 7, count 0 2006.173.19:32:09.82#ibcon#wrote, iclass 7, count 0 2006.173.19:32:09.82#ibcon#about to read 3, iclass 7, count 0 2006.173.19:32:09.86#ibcon#read 3, iclass 7, count 0 2006.173.19:32:09.86#ibcon#about to read 4, iclass 7, count 0 2006.173.19:32:09.86#ibcon#read 4, iclass 7, count 0 2006.173.19:32:09.86#ibcon#about to read 5, iclass 7, count 0 2006.173.19:32:09.86#ibcon#read 5, iclass 7, count 0 2006.173.19:32:09.86#ibcon#about to read 6, iclass 7, count 0 2006.173.19:32:09.86#ibcon#read 6, iclass 7, count 0 2006.173.19:32:09.86#ibcon#end of sib2, iclass 7, count 0 2006.173.19:32:09.86#ibcon#*after write, iclass 7, count 0 2006.173.19:32:09.86#ibcon#*before return 0, iclass 7, count 0 2006.173.19:32:09.86#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.19:32:09.86#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.19:32:09.86#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.19:32:09.86#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.19:32:09.86$vck44/va=3,5 2006.173.19:32:09.86#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.19:32:09.86#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.19:32:09.86#ibcon#ireg 11 cls_cnt 2 2006.173.19:32:09.86#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.19:32:09.92#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.19:32:09.92#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.19:32:09.92#ibcon#enter wrdev, iclass 11, count 2 2006.173.19:32:09.92#ibcon#first serial, iclass 11, count 2 2006.173.19:32:09.92#ibcon#enter sib2, iclass 11, count 2 2006.173.19:32:09.92#ibcon#flushed, iclass 11, count 2 2006.173.19:32:09.92#ibcon#about to write, iclass 11, count 2 2006.173.19:32:09.92#ibcon#wrote, iclass 11, count 2 2006.173.19:32:09.92#ibcon#about to read 3, iclass 11, count 2 2006.173.19:32:09.94#ibcon#read 3, iclass 11, count 2 2006.173.19:32:09.94#ibcon#about to read 4, iclass 11, count 2 2006.173.19:32:09.94#ibcon#read 4, iclass 11, count 2 2006.173.19:32:09.94#ibcon#about to read 5, iclass 11, count 2 2006.173.19:32:09.94#ibcon#read 5, iclass 11, count 2 2006.173.19:32:09.94#ibcon#about to read 6, iclass 11, count 2 2006.173.19:32:09.94#ibcon#read 6, iclass 11, count 2 2006.173.19:32:09.94#ibcon#end of sib2, iclass 11, count 2 2006.173.19:32:09.94#ibcon#*mode == 0, iclass 11, count 2 2006.173.19:32:09.94#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.19:32:09.94#ibcon#[25=AT03-05\r\n] 2006.173.19:32:09.94#ibcon#*before write, iclass 11, count 2 2006.173.19:32:09.94#ibcon#enter sib2, iclass 11, count 2 2006.173.19:32:09.94#ibcon#flushed, iclass 11, count 2 2006.173.19:32:09.94#ibcon#about to write, iclass 11, count 2 2006.173.19:32:09.94#ibcon#wrote, iclass 11, count 2 2006.173.19:32:09.94#ibcon#about to read 3, iclass 11, count 2 2006.173.19:32:09.97#ibcon#read 3, iclass 11, count 2 2006.173.19:32:09.97#ibcon#about to read 4, iclass 11, count 2 2006.173.19:32:09.97#ibcon#read 4, iclass 11, count 2 2006.173.19:32:09.97#ibcon#about to read 5, iclass 11, count 2 2006.173.19:32:09.97#ibcon#read 5, iclass 11, count 2 2006.173.19:32:09.97#ibcon#about to read 6, iclass 11, count 2 2006.173.19:32:09.97#ibcon#read 6, iclass 11, count 2 2006.173.19:32:09.97#ibcon#end of sib2, iclass 11, count 2 2006.173.19:32:09.97#ibcon#*after write, iclass 11, count 2 2006.173.19:32:09.97#ibcon#*before return 0, iclass 11, count 2 2006.173.19:32:09.97#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.19:32:09.97#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.19:32:09.97#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.19:32:09.97#ibcon#ireg 7 cls_cnt 0 2006.173.19:32:09.97#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.19:32:10.09#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.19:32:10.09#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.19:32:10.09#ibcon#enter wrdev, iclass 11, count 0 2006.173.19:32:10.09#ibcon#first serial, iclass 11, count 0 2006.173.19:32:10.09#ibcon#enter sib2, iclass 11, count 0 2006.173.19:32:10.09#ibcon#flushed, iclass 11, count 0 2006.173.19:32:10.09#ibcon#about to write, iclass 11, count 0 2006.173.19:32:10.09#ibcon#wrote, iclass 11, count 0 2006.173.19:32:10.09#ibcon#about to read 3, iclass 11, count 0 2006.173.19:32:10.11#ibcon#read 3, iclass 11, count 0 2006.173.19:32:10.11#ibcon#about to read 4, iclass 11, count 0 2006.173.19:32:10.11#ibcon#read 4, iclass 11, count 0 2006.173.19:32:10.11#ibcon#about to read 5, iclass 11, count 0 2006.173.19:32:10.11#ibcon#read 5, iclass 11, count 0 2006.173.19:32:10.11#ibcon#about to read 6, iclass 11, count 0 2006.173.19:32:10.11#ibcon#read 6, iclass 11, count 0 2006.173.19:32:10.11#ibcon#end of sib2, iclass 11, count 0 2006.173.19:32:10.11#ibcon#*mode == 0, iclass 11, count 0 2006.173.19:32:10.11#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.19:32:10.11#ibcon#[25=USB\r\n] 2006.173.19:32:10.11#ibcon#*before write, iclass 11, count 0 2006.173.19:32:10.11#ibcon#enter sib2, iclass 11, count 0 2006.173.19:32:10.11#ibcon#flushed, iclass 11, count 0 2006.173.19:32:10.11#ibcon#about to write, iclass 11, count 0 2006.173.19:32:10.11#ibcon#wrote, iclass 11, count 0 2006.173.19:32:10.11#ibcon#about to read 3, iclass 11, count 0 2006.173.19:32:10.14#ibcon#read 3, iclass 11, count 0 2006.173.19:32:10.14#ibcon#about to read 4, iclass 11, count 0 2006.173.19:32:10.14#ibcon#read 4, iclass 11, count 0 2006.173.19:32:10.14#ibcon#about to read 5, iclass 11, count 0 2006.173.19:32:10.14#ibcon#read 5, iclass 11, count 0 2006.173.19:32:10.14#ibcon#about to read 6, iclass 11, count 0 2006.173.19:32:10.14#ibcon#read 6, iclass 11, count 0 2006.173.19:32:10.14#ibcon#end of sib2, iclass 11, count 0 2006.173.19:32:10.14#ibcon#*after write, iclass 11, count 0 2006.173.19:32:10.14#ibcon#*before return 0, iclass 11, count 0 2006.173.19:32:10.14#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.19:32:10.14#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.19:32:10.14#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.19:32:10.14#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.19:32:10.14$vck44/valo=4,624.99 2006.173.19:32:10.14#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.19:32:10.14#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.19:32:10.14#ibcon#ireg 17 cls_cnt 0 2006.173.19:32:10.14#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.19:32:10.14#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.19:32:10.14#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.19:32:10.14#ibcon#enter wrdev, iclass 13, count 0 2006.173.19:32:10.14#ibcon#first serial, iclass 13, count 0 2006.173.19:32:10.14#ibcon#enter sib2, iclass 13, count 0 2006.173.19:32:10.14#ibcon#flushed, iclass 13, count 0 2006.173.19:32:10.14#ibcon#about to write, iclass 13, count 0 2006.173.19:32:10.14#ibcon#wrote, iclass 13, count 0 2006.173.19:32:10.14#ibcon#about to read 3, iclass 13, count 0 2006.173.19:32:10.16#ibcon#read 3, iclass 13, count 0 2006.173.19:32:10.16#ibcon#about to read 4, iclass 13, count 0 2006.173.19:32:10.16#ibcon#read 4, iclass 13, count 0 2006.173.19:32:10.16#ibcon#about to read 5, iclass 13, count 0 2006.173.19:32:10.16#ibcon#read 5, iclass 13, count 0 2006.173.19:32:10.16#ibcon#about to read 6, iclass 13, count 0 2006.173.19:32:10.16#ibcon#read 6, iclass 13, count 0 2006.173.19:32:10.16#ibcon#end of sib2, iclass 13, count 0 2006.173.19:32:10.16#ibcon#*mode == 0, iclass 13, count 0 2006.173.19:32:10.16#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.19:32:10.16#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.19:32:10.16#ibcon#*before write, iclass 13, count 0 2006.173.19:32:10.16#ibcon#enter sib2, iclass 13, count 0 2006.173.19:32:10.16#ibcon#flushed, iclass 13, count 0 2006.173.19:32:10.16#ibcon#about to write, iclass 13, count 0 2006.173.19:32:10.16#ibcon#wrote, iclass 13, count 0 2006.173.19:32:10.16#ibcon#about to read 3, iclass 13, count 0 2006.173.19:32:10.20#ibcon#read 3, iclass 13, count 0 2006.173.19:32:10.20#ibcon#about to read 4, iclass 13, count 0 2006.173.19:32:10.20#ibcon#read 4, iclass 13, count 0 2006.173.19:32:10.20#ibcon#about to read 5, iclass 13, count 0 2006.173.19:32:10.20#ibcon#read 5, iclass 13, count 0 2006.173.19:32:10.20#ibcon#about to read 6, iclass 13, count 0 2006.173.19:32:10.20#ibcon#read 6, iclass 13, count 0 2006.173.19:32:10.20#ibcon#end of sib2, iclass 13, count 0 2006.173.19:32:10.20#ibcon#*after write, iclass 13, count 0 2006.173.19:32:10.20#ibcon#*before return 0, iclass 13, count 0 2006.173.19:32:10.20#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.19:32:10.20#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.19:32:10.20#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.19:32:10.20#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.19:32:10.20$vck44/va=4,6 2006.173.19:32:10.20#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.19:32:10.20#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.19:32:10.20#ibcon#ireg 11 cls_cnt 2 2006.173.19:32:10.20#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.19:32:10.26#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.19:32:10.26#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.19:32:10.26#ibcon#enter wrdev, iclass 15, count 2 2006.173.19:32:10.26#ibcon#first serial, iclass 15, count 2 2006.173.19:32:10.26#ibcon#enter sib2, iclass 15, count 2 2006.173.19:32:10.26#ibcon#flushed, iclass 15, count 2 2006.173.19:32:10.26#ibcon#about to write, iclass 15, count 2 2006.173.19:32:10.26#ibcon#wrote, iclass 15, count 2 2006.173.19:32:10.26#ibcon#about to read 3, iclass 15, count 2 2006.173.19:32:10.28#ibcon#read 3, iclass 15, count 2 2006.173.19:32:10.28#ibcon#about to read 4, iclass 15, count 2 2006.173.19:32:10.28#ibcon#read 4, iclass 15, count 2 2006.173.19:32:10.28#ibcon#about to read 5, iclass 15, count 2 2006.173.19:32:10.28#ibcon#read 5, iclass 15, count 2 2006.173.19:32:10.28#ibcon#about to read 6, iclass 15, count 2 2006.173.19:32:10.28#ibcon#read 6, iclass 15, count 2 2006.173.19:32:10.28#ibcon#end of sib2, iclass 15, count 2 2006.173.19:32:10.28#ibcon#*mode == 0, iclass 15, count 2 2006.173.19:32:10.28#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.19:32:10.28#ibcon#[25=AT04-06\r\n] 2006.173.19:32:10.28#ibcon#*before write, iclass 15, count 2 2006.173.19:32:10.28#ibcon#enter sib2, iclass 15, count 2 2006.173.19:32:10.28#ibcon#flushed, iclass 15, count 2 2006.173.19:32:10.28#ibcon#about to write, iclass 15, count 2 2006.173.19:32:10.28#ibcon#wrote, iclass 15, count 2 2006.173.19:32:10.28#ibcon#about to read 3, iclass 15, count 2 2006.173.19:32:10.31#ibcon#read 3, iclass 15, count 2 2006.173.19:32:10.31#ibcon#about to read 4, iclass 15, count 2 2006.173.19:32:10.31#ibcon#read 4, iclass 15, count 2 2006.173.19:32:10.31#ibcon#about to read 5, iclass 15, count 2 2006.173.19:32:10.31#ibcon#read 5, iclass 15, count 2 2006.173.19:32:10.31#ibcon#about to read 6, iclass 15, count 2 2006.173.19:32:10.31#ibcon#read 6, iclass 15, count 2 2006.173.19:32:10.31#ibcon#end of sib2, iclass 15, count 2 2006.173.19:32:10.31#ibcon#*after write, iclass 15, count 2 2006.173.19:32:10.31#ibcon#*before return 0, iclass 15, count 2 2006.173.19:32:10.31#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.19:32:10.31#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.19:32:10.31#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.19:32:10.31#ibcon#ireg 7 cls_cnt 0 2006.173.19:32:10.31#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.19:32:10.43#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.19:32:10.43#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.19:32:10.43#ibcon#enter wrdev, iclass 15, count 0 2006.173.19:32:10.43#ibcon#first serial, iclass 15, count 0 2006.173.19:32:10.43#ibcon#enter sib2, iclass 15, count 0 2006.173.19:32:10.43#ibcon#flushed, iclass 15, count 0 2006.173.19:32:10.43#ibcon#about to write, iclass 15, count 0 2006.173.19:32:10.43#ibcon#wrote, iclass 15, count 0 2006.173.19:32:10.43#ibcon#about to read 3, iclass 15, count 0 2006.173.19:32:10.45#ibcon#read 3, iclass 15, count 0 2006.173.19:32:10.45#ibcon#about to read 4, iclass 15, count 0 2006.173.19:32:10.45#ibcon#read 4, iclass 15, count 0 2006.173.19:32:10.45#ibcon#about to read 5, iclass 15, count 0 2006.173.19:32:10.45#ibcon#read 5, iclass 15, count 0 2006.173.19:32:10.45#ibcon#about to read 6, iclass 15, count 0 2006.173.19:32:10.45#ibcon#read 6, iclass 15, count 0 2006.173.19:32:10.45#ibcon#end of sib2, iclass 15, count 0 2006.173.19:32:10.45#ibcon#*mode == 0, iclass 15, count 0 2006.173.19:32:10.45#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.19:32:10.45#ibcon#[25=USB\r\n] 2006.173.19:32:10.45#ibcon#*before write, iclass 15, count 0 2006.173.19:32:10.45#ibcon#enter sib2, iclass 15, count 0 2006.173.19:32:10.45#ibcon#flushed, iclass 15, count 0 2006.173.19:32:10.45#ibcon#about to write, iclass 15, count 0 2006.173.19:32:10.45#ibcon#wrote, iclass 15, count 0 2006.173.19:32:10.45#ibcon#about to read 3, iclass 15, count 0 2006.173.19:32:10.48#ibcon#read 3, iclass 15, count 0 2006.173.19:32:10.48#ibcon#about to read 4, iclass 15, count 0 2006.173.19:32:10.48#ibcon#read 4, iclass 15, count 0 2006.173.19:32:10.48#ibcon#about to read 5, iclass 15, count 0 2006.173.19:32:10.48#ibcon#read 5, iclass 15, count 0 2006.173.19:32:10.48#ibcon#about to read 6, iclass 15, count 0 2006.173.19:32:10.48#ibcon#read 6, iclass 15, count 0 2006.173.19:32:10.48#ibcon#end of sib2, iclass 15, count 0 2006.173.19:32:10.48#ibcon#*after write, iclass 15, count 0 2006.173.19:32:10.48#ibcon#*before return 0, iclass 15, count 0 2006.173.19:32:10.48#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.19:32:10.48#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.19:32:10.48#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.19:32:10.48#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.19:32:10.48$vck44/valo=5,734.99 2006.173.19:32:10.48#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.19:32:10.48#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.19:32:10.48#ibcon#ireg 17 cls_cnt 0 2006.173.19:32:10.48#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.19:32:10.48#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.19:32:10.48#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.19:32:10.48#ibcon#enter wrdev, iclass 17, count 0 2006.173.19:32:10.48#ibcon#first serial, iclass 17, count 0 2006.173.19:32:10.48#ibcon#enter sib2, iclass 17, count 0 2006.173.19:32:10.48#ibcon#flushed, iclass 17, count 0 2006.173.19:32:10.48#ibcon#about to write, iclass 17, count 0 2006.173.19:32:10.48#ibcon#wrote, iclass 17, count 0 2006.173.19:32:10.48#ibcon#about to read 3, iclass 17, count 0 2006.173.19:32:10.50#ibcon#read 3, iclass 17, count 0 2006.173.19:32:10.50#ibcon#about to read 4, iclass 17, count 0 2006.173.19:32:10.50#ibcon#read 4, iclass 17, count 0 2006.173.19:32:10.50#ibcon#about to read 5, iclass 17, count 0 2006.173.19:32:10.50#ibcon#read 5, iclass 17, count 0 2006.173.19:32:10.50#ibcon#about to read 6, iclass 17, count 0 2006.173.19:32:10.50#ibcon#read 6, iclass 17, count 0 2006.173.19:32:10.50#ibcon#end of sib2, iclass 17, count 0 2006.173.19:32:10.50#ibcon#*mode == 0, iclass 17, count 0 2006.173.19:32:10.50#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.19:32:10.50#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.19:32:10.50#ibcon#*before write, iclass 17, count 0 2006.173.19:32:10.50#ibcon#enter sib2, iclass 17, count 0 2006.173.19:32:10.50#ibcon#flushed, iclass 17, count 0 2006.173.19:32:10.50#ibcon#about to write, iclass 17, count 0 2006.173.19:32:10.50#ibcon#wrote, iclass 17, count 0 2006.173.19:32:10.50#ibcon#about to read 3, iclass 17, count 0 2006.173.19:32:10.54#ibcon#read 3, iclass 17, count 0 2006.173.19:32:10.54#ibcon#about to read 4, iclass 17, count 0 2006.173.19:32:10.54#ibcon#read 4, iclass 17, count 0 2006.173.19:32:10.54#ibcon#about to read 5, iclass 17, count 0 2006.173.19:32:10.54#ibcon#read 5, iclass 17, count 0 2006.173.19:32:10.54#ibcon#about to read 6, iclass 17, count 0 2006.173.19:32:10.54#ibcon#read 6, iclass 17, count 0 2006.173.19:32:10.54#ibcon#end of sib2, iclass 17, count 0 2006.173.19:32:10.54#ibcon#*after write, iclass 17, count 0 2006.173.19:32:10.54#ibcon#*before return 0, iclass 17, count 0 2006.173.19:32:10.54#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.19:32:10.54#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.19:32:10.54#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.19:32:10.54#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.19:32:10.54$vck44/va=5,4 2006.173.19:32:10.54#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.19:32:10.54#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.19:32:10.54#ibcon#ireg 11 cls_cnt 2 2006.173.19:32:10.54#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.19:32:10.60#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.19:32:10.60#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.19:32:10.60#ibcon#enter wrdev, iclass 19, count 2 2006.173.19:32:10.60#ibcon#first serial, iclass 19, count 2 2006.173.19:32:10.60#ibcon#enter sib2, iclass 19, count 2 2006.173.19:32:10.60#ibcon#flushed, iclass 19, count 2 2006.173.19:32:10.60#ibcon#about to write, iclass 19, count 2 2006.173.19:32:10.60#ibcon#wrote, iclass 19, count 2 2006.173.19:32:10.60#ibcon#about to read 3, iclass 19, count 2 2006.173.19:32:10.62#ibcon#read 3, iclass 19, count 2 2006.173.19:32:10.62#ibcon#about to read 4, iclass 19, count 2 2006.173.19:32:10.62#ibcon#read 4, iclass 19, count 2 2006.173.19:32:10.62#ibcon#about to read 5, iclass 19, count 2 2006.173.19:32:10.62#ibcon#read 5, iclass 19, count 2 2006.173.19:32:10.62#ibcon#about to read 6, iclass 19, count 2 2006.173.19:32:10.62#ibcon#read 6, iclass 19, count 2 2006.173.19:32:10.62#ibcon#end of sib2, iclass 19, count 2 2006.173.19:32:10.62#ibcon#*mode == 0, iclass 19, count 2 2006.173.19:32:10.62#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.19:32:10.62#ibcon#[25=AT05-04\r\n] 2006.173.19:32:10.62#ibcon#*before write, iclass 19, count 2 2006.173.19:32:10.62#ibcon#enter sib2, iclass 19, count 2 2006.173.19:32:10.62#ibcon#flushed, iclass 19, count 2 2006.173.19:32:10.62#ibcon#about to write, iclass 19, count 2 2006.173.19:32:10.62#ibcon#wrote, iclass 19, count 2 2006.173.19:32:10.62#ibcon#about to read 3, iclass 19, count 2 2006.173.19:32:10.65#ibcon#read 3, iclass 19, count 2 2006.173.19:32:10.65#ibcon#about to read 4, iclass 19, count 2 2006.173.19:32:10.65#ibcon#read 4, iclass 19, count 2 2006.173.19:32:10.65#ibcon#about to read 5, iclass 19, count 2 2006.173.19:32:10.65#ibcon#read 5, iclass 19, count 2 2006.173.19:32:10.65#ibcon#about to read 6, iclass 19, count 2 2006.173.19:32:10.65#ibcon#read 6, iclass 19, count 2 2006.173.19:32:10.65#ibcon#end of sib2, iclass 19, count 2 2006.173.19:32:10.65#ibcon#*after write, iclass 19, count 2 2006.173.19:32:10.65#ibcon#*before return 0, iclass 19, count 2 2006.173.19:32:10.65#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.19:32:10.65#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.19:32:10.65#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.19:32:10.65#ibcon#ireg 7 cls_cnt 0 2006.173.19:32:10.65#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.19:32:10.77#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.19:32:10.77#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.19:32:10.77#ibcon#enter wrdev, iclass 19, count 0 2006.173.19:32:10.77#ibcon#first serial, iclass 19, count 0 2006.173.19:32:10.77#ibcon#enter sib2, iclass 19, count 0 2006.173.19:32:10.77#ibcon#flushed, iclass 19, count 0 2006.173.19:32:10.77#ibcon#about to write, iclass 19, count 0 2006.173.19:32:10.77#ibcon#wrote, iclass 19, count 0 2006.173.19:32:10.77#ibcon#about to read 3, iclass 19, count 0 2006.173.19:32:10.79#ibcon#read 3, iclass 19, count 0 2006.173.19:32:10.79#ibcon#about to read 4, iclass 19, count 0 2006.173.19:32:10.79#ibcon#read 4, iclass 19, count 0 2006.173.19:32:10.79#ibcon#about to read 5, iclass 19, count 0 2006.173.19:32:10.79#ibcon#read 5, iclass 19, count 0 2006.173.19:32:10.79#ibcon#about to read 6, iclass 19, count 0 2006.173.19:32:10.79#ibcon#read 6, iclass 19, count 0 2006.173.19:32:10.79#ibcon#end of sib2, iclass 19, count 0 2006.173.19:32:10.79#ibcon#*mode == 0, iclass 19, count 0 2006.173.19:32:10.79#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.19:32:10.79#ibcon#[25=USB\r\n] 2006.173.19:32:10.79#ibcon#*before write, iclass 19, count 0 2006.173.19:32:10.79#ibcon#enter sib2, iclass 19, count 0 2006.173.19:32:10.79#ibcon#flushed, iclass 19, count 0 2006.173.19:32:10.79#ibcon#about to write, iclass 19, count 0 2006.173.19:32:10.79#ibcon#wrote, iclass 19, count 0 2006.173.19:32:10.79#ibcon#about to read 3, iclass 19, count 0 2006.173.19:32:10.82#ibcon#read 3, iclass 19, count 0 2006.173.19:32:10.82#ibcon#about to read 4, iclass 19, count 0 2006.173.19:32:10.82#ibcon#read 4, iclass 19, count 0 2006.173.19:32:10.82#ibcon#about to read 5, iclass 19, count 0 2006.173.19:32:10.82#ibcon#read 5, iclass 19, count 0 2006.173.19:32:10.82#ibcon#about to read 6, iclass 19, count 0 2006.173.19:32:10.82#ibcon#read 6, iclass 19, count 0 2006.173.19:32:10.82#ibcon#end of sib2, iclass 19, count 0 2006.173.19:32:10.82#ibcon#*after write, iclass 19, count 0 2006.173.19:32:10.82#ibcon#*before return 0, iclass 19, count 0 2006.173.19:32:10.82#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.19:32:10.82#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.19:32:10.82#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.19:32:10.82#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.19:32:10.82$vck44/valo=6,814.99 2006.173.19:32:10.82#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.19:32:10.82#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.19:32:10.82#ibcon#ireg 17 cls_cnt 0 2006.173.19:32:10.82#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.19:32:10.82#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.19:32:10.82#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.19:32:10.82#ibcon#enter wrdev, iclass 21, count 0 2006.173.19:32:10.82#ibcon#first serial, iclass 21, count 0 2006.173.19:32:10.82#ibcon#enter sib2, iclass 21, count 0 2006.173.19:32:10.82#ibcon#flushed, iclass 21, count 0 2006.173.19:32:10.82#ibcon#about to write, iclass 21, count 0 2006.173.19:32:10.82#ibcon#wrote, iclass 21, count 0 2006.173.19:32:10.82#ibcon#about to read 3, iclass 21, count 0 2006.173.19:32:10.84#ibcon#read 3, iclass 21, count 0 2006.173.19:32:10.84#ibcon#about to read 4, iclass 21, count 0 2006.173.19:32:10.84#ibcon#read 4, iclass 21, count 0 2006.173.19:32:10.84#ibcon#about to read 5, iclass 21, count 0 2006.173.19:32:10.84#ibcon#read 5, iclass 21, count 0 2006.173.19:32:10.84#ibcon#about to read 6, iclass 21, count 0 2006.173.19:32:10.84#ibcon#read 6, iclass 21, count 0 2006.173.19:32:10.84#ibcon#end of sib2, iclass 21, count 0 2006.173.19:32:10.84#ibcon#*mode == 0, iclass 21, count 0 2006.173.19:32:10.84#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.19:32:10.84#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.19:32:10.84#ibcon#*before write, iclass 21, count 0 2006.173.19:32:10.84#ibcon#enter sib2, iclass 21, count 0 2006.173.19:32:10.84#ibcon#flushed, iclass 21, count 0 2006.173.19:32:10.84#ibcon#about to write, iclass 21, count 0 2006.173.19:32:10.84#ibcon#wrote, iclass 21, count 0 2006.173.19:32:10.84#ibcon#about to read 3, iclass 21, count 0 2006.173.19:32:10.88#ibcon#read 3, iclass 21, count 0 2006.173.19:32:10.88#ibcon#about to read 4, iclass 21, count 0 2006.173.19:32:10.88#ibcon#read 4, iclass 21, count 0 2006.173.19:32:10.88#ibcon#about to read 5, iclass 21, count 0 2006.173.19:32:10.88#ibcon#read 5, iclass 21, count 0 2006.173.19:32:10.88#ibcon#about to read 6, iclass 21, count 0 2006.173.19:32:10.88#ibcon#read 6, iclass 21, count 0 2006.173.19:32:10.88#ibcon#end of sib2, iclass 21, count 0 2006.173.19:32:10.88#ibcon#*after write, iclass 21, count 0 2006.173.19:32:10.88#ibcon#*before return 0, iclass 21, count 0 2006.173.19:32:10.88#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.19:32:10.88#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.19:32:10.88#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.19:32:10.88#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.19:32:10.88$vck44/va=6,3 2006.173.19:32:10.88#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.19:32:10.88#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.19:32:10.88#ibcon#ireg 11 cls_cnt 2 2006.173.19:32:10.88#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.19:32:10.94#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.19:32:10.94#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.19:32:10.94#ibcon#enter wrdev, iclass 23, count 2 2006.173.19:32:10.94#ibcon#first serial, iclass 23, count 2 2006.173.19:32:10.94#ibcon#enter sib2, iclass 23, count 2 2006.173.19:32:10.94#ibcon#flushed, iclass 23, count 2 2006.173.19:32:10.94#ibcon#about to write, iclass 23, count 2 2006.173.19:32:10.94#ibcon#wrote, iclass 23, count 2 2006.173.19:32:10.94#ibcon#about to read 3, iclass 23, count 2 2006.173.19:32:10.96#ibcon#read 3, iclass 23, count 2 2006.173.19:32:10.96#ibcon#about to read 4, iclass 23, count 2 2006.173.19:32:10.96#ibcon#read 4, iclass 23, count 2 2006.173.19:32:10.96#ibcon#about to read 5, iclass 23, count 2 2006.173.19:32:10.96#ibcon#read 5, iclass 23, count 2 2006.173.19:32:10.96#ibcon#about to read 6, iclass 23, count 2 2006.173.19:32:10.96#ibcon#read 6, iclass 23, count 2 2006.173.19:32:10.96#ibcon#end of sib2, iclass 23, count 2 2006.173.19:32:10.96#ibcon#*mode == 0, iclass 23, count 2 2006.173.19:32:10.96#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.19:32:10.96#ibcon#[25=AT06-03\r\n] 2006.173.19:32:10.96#ibcon#*before write, iclass 23, count 2 2006.173.19:32:10.96#ibcon#enter sib2, iclass 23, count 2 2006.173.19:32:10.96#ibcon#flushed, iclass 23, count 2 2006.173.19:32:10.96#ibcon#about to write, iclass 23, count 2 2006.173.19:32:10.96#ibcon#wrote, iclass 23, count 2 2006.173.19:32:10.96#ibcon#about to read 3, iclass 23, count 2 2006.173.19:32:10.99#ibcon#read 3, iclass 23, count 2 2006.173.19:32:10.99#ibcon#about to read 4, iclass 23, count 2 2006.173.19:32:10.99#ibcon#read 4, iclass 23, count 2 2006.173.19:32:10.99#ibcon#about to read 5, iclass 23, count 2 2006.173.19:32:10.99#ibcon#read 5, iclass 23, count 2 2006.173.19:32:10.99#ibcon#about to read 6, iclass 23, count 2 2006.173.19:32:10.99#ibcon#read 6, iclass 23, count 2 2006.173.19:32:10.99#ibcon#end of sib2, iclass 23, count 2 2006.173.19:32:10.99#ibcon#*after write, iclass 23, count 2 2006.173.19:32:10.99#ibcon#*before return 0, iclass 23, count 2 2006.173.19:32:10.99#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.19:32:10.99#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.19:32:10.99#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.19:32:10.99#ibcon#ireg 7 cls_cnt 0 2006.173.19:32:10.99#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.19:32:11.11#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.19:32:11.11#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.19:32:11.11#ibcon#enter wrdev, iclass 23, count 0 2006.173.19:32:11.11#ibcon#first serial, iclass 23, count 0 2006.173.19:32:11.11#ibcon#enter sib2, iclass 23, count 0 2006.173.19:32:11.11#ibcon#flushed, iclass 23, count 0 2006.173.19:32:11.11#ibcon#about to write, iclass 23, count 0 2006.173.19:32:11.11#ibcon#wrote, iclass 23, count 0 2006.173.19:32:11.11#ibcon#about to read 3, iclass 23, count 0 2006.173.19:32:11.13#ibcon#read 3, iclass 23, count 0 2006.173.19:32:11.13#ibcon#about to read 4, iclass 23, count 0 2006.173.19:32:11.13#ibcon#read 4, iclass 23, count 0 2006.173.19:32:11.13#ibcon#about to read 5, iclass 23, count 0 2006.173.19:32:11.13#ibcon#read 5, iclass 23, count 0 2006.173.19:32:11.13#ibcon#about to read 6, iclass 23, count 0 2006.173.19:32:11.13#ibcon#read 6, iclass 23, count 0 2006.173.19:32:11.13#ibcon#end of sib2, iclass 23, count 0 2006.173.19:32:11.13#ibcon#*mode == 0, iclass 23, count 0 2006.173.19:32:11.13#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.19:32:11.13#ibcon#[25=USB\r\n] 2006.173.19:32:11.13#ibcon#*before write, iclass 23, count 0 2006.173.19:32:11.13#ibcon#enter sib2, iclass 23, count 0 2006.173.19:32:11.13#ibcon#flushed, iclass 23, count 0 2006.173.19:32:11.13#ibcon#about to write, iclass 23, count 0 2006.173.19:32:11.13#ibcon#wrote, iclass 23, count 0 2006.173.19:32:11.13#ibcon#about to read 3, iclass 23, count 0 2006.173.19:32:11.16#ibcon#read 3, iclass 23, count 0 2006.173.19:32:11.16#ibcon#about to read 4, iclass 23, count 0 2006.173.19:32:11.16#ibcon#read 4, iclass 23, count 0 2006.173.19:32:11.16#ibcon#about to read 5, iclass 23, count 0 2006.173.19:32:11.16#ibcon#read 5, iclass 23, count 0 2006.173.19:32:11.16#ibcon#about to read 6, iclass 23, count 0 2006.173.19:32:11.16#ibcon#read 6, iclass 23, count 0 2006.173.19:32:11.16#ibcon#end of sib2, iclass 23, count 0 2006.173.19:32:11.16#ibcon#*after write, iclass 23, count 0 2006.173.19:32:11.16#ibcon#*before return 0, iclass 23, count 0 2006.173.19:32:11.16#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.19:32:11.16#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.19:32:11.16#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.19:32:11.16#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.19:32:11.16$vck44/valo=7,864.99 2006.173.19:32:11.16#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.19:32:11.16#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.19:32:11.16#ibcon#ireg 17 cls_cnt 0 2006.173.19:32:11.16#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.19:32:11.16#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.19:32:11.16#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.19:32:11.16#ibcon#enter wrdev, iclass 25, count 0 2006.173.19:32:11.16#ibcon#first serial, iclass 25, count 0 2006.173.19:32:11.16#ibcon#enter sib2, iclass 25, count 0 2006.173.19:32:11.16#ibcon#flushed, iclass 25, count 0 2006.173.19:32:11.16#ibcon#about to write, iclass 25, count 0 2006.173.19:32:11.16#ibcon#wrote, iclass 25, count 0 2006.173.19:32:11.16#ibcon#about to read 3, iclass 25, count 0 2006.173.19:32:11.18#ibcon#read 3, iclass 25, count 0 2006.173.19:32:11.18#ibcon#about to read 4, iclass 25, count 0 2006.173.19:32:11.18#ibcon#read 4, iclass 25, count 0 2006.173.19:32:11.18#ibcon#about to read 5, iclass 25, count 0 2006.173.19:32:11.18#ibcon#read 5, iclass 25, count 0 2006.173.19:32:11.18#ibcon#about to read 6, iclass 25, count 0 2006.173.19:32:11.18#ibcon#read 6, iclass 25, count 0 2006.173.19:32:11.18#ibcon#end of sib2, iclass 25, count 0 2006.173.19:32:11.18#ibcon#*mode == 0, iclass 25, count 0 2006.173.19:32:11.18#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.19:32:11.18#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.19:32:11.18#ibcon#*before write, iclass 25, count 0 2006.173.19:32:11.18#ibcon#enter sib2, iclass 25, count 0 2006.173.19:32:11.18#ibcon#flushed, iclass 25, count 0 2006.173.19:32:11.18#ibcon#about to write, iclass 25, count 0 2006.173.19:32:11.18#ibcon#wrote, iclass 25, count 0 2006.173.19:32:11.18#ibcon#about to read 3, iclass 25, count 0 2006.173.19:32:11.22#ibcon#read 3, iclass 25, count 0 2006.173.19:32:11.22#ibcon#about to read 4, iclass 25, count 0 2006.173.19:32:11.22#ibcon#read 4, iclass 25, count 0 2006.173.19:32:11.22#ibcon#about to read 5, iclass 25, count 0 2006.173.19:32:11.22#ibcon#read 5, iclass 25, count 0 2006.173.19:32:11.22#ibcon#about to read 6, iclass 25, count 0 2006.173.19:32:11.22#ibcon#read 6, iclass 25, count 0 2006.173.19:32:11.22#ibcon#end of sib2, iclass 25, count 0 2006.173.19:32:11.22#ibcon#*after write, iclass 25, count 0 2006.173.19:32:11.22#ibcon#*before return 0, iclass 25, count 0 2006.173.19:32:11.22#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.19:32:11.22#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.19:32:11.22#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.19:32:11.22#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.19:32:11.22$vck44/va=7,4 2006.173.19:32:11.22#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.19:32:11.22#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.19:32:11.22#ibcon#ireg 11 cls_cnt 2 2006.173.19:32:11.22#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.19:32:11.28#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.19:32:11.28#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.19:32:11.28#ibcon#enter wrdev, iclass 27, count 2 2006.173.19:32:11.28#ibcon#first serial, iclass 27, count 2 2006.173.19:32:11.28#ibcon#enter sib2, iclass 27, count 2 2006.173.19:32:11.28#ibcon#flushed, iclass 27, count 2 2006.173.19:32:11.28#ibcon#about to write, iclass 27, count 2 2006.173.19:32:11.28#ibcon#wrote, iclass 27, count 2 2006.173.19:32:11.28#ibcon#about to read 3, iclass 27, count 2 2006.173.19:32:11.30#ibcon#read 3, iclass 27, count 2 2006.173.19:32:11.30#ibcon#about to read 4, iclass 27, count 2 2006.173.19:32:11.30#ibcon#read 4, iclass 27, count 2 2006.173.19:32:11.30#ibcon#about to read 5, iclass 27, count 2 2006.173.19:32:11.30#ibcon#read 5, iclass 27, count 2 2006.173.19:32:11.30#ibcon#about to read 6, iclass 27, count 2 2006.173.19:32:11.30#ibcon#read 6, iclass 27, count 2 2006.173.19:32:11.30#ibcon#end of sib2, iclass 27, count 2 2006.173.19:32:11.30#ibcon#*mode == 0, iclass 27, count 2 2006.173.19:32:11.30#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.19:32:11.30#ibcon#[25=AT07-04\r\n] 2006.173.19:32:11.30#ibcon#*before write, iclass 27, count 2 2006.173.19:32:11.30#ibcon#enter sib2, iclass 27, count 2 2006.173.19:32:11.30#ibcon#flushed, iclass 27, count 2 2006.173.19:32:11.30#ibcon#about to write, iclass 27, count 2 2006.173.19:32:11.30#ibcon#wrote, iclass 27, count 2 2006.173.19:32:11.30#ibcon#about to read 3, iclass 27, count 2 2006.173.19:32:11.33#ibcon#read 3, iclass 27, count 2 2006.173.19:32:11.33#ibcon#about to read 4, iclass 27, count 2 2006.173.19:32:11.33#ibcon#read 4, iclass 27, count 2 2006.173.19:32:11.33#ibcon#about to read 5, iclass 27, count 2 2006.173.19:32:11.33#ibcon#read 5, iclass 27, count 2 2006.173.19:32:11.33#ibcon#about to read 6, iclass 27, count 2 2006.173.19:32:11.33#ibcon#read 6, iclass 27, count 2 2006.173.19:32:11.33#ibcon#end of sib2, iclass 27, count 2 2006.173.19:32:11.33#ibcon#*after write, iclass 27, count 2 2006.173.19:32:11.33#ibcon#*before return 0, iclass 27, count 2 2006.173.19:32:11.33#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.19:32:11.33#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.19:32:11.33#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.19:32:11.33#ibcon#ireg 7 cls_cnt 0 2006.173.19:32:11.33#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.19:32:11.45#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.19:32:11.45#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.19:32:11.45#ibcon#enter wrdev, iclass 27, count 0 2006.173.19:32:11.45#ibcon#first serial, iclass 27, count 0 2006.173.19:32:11.45#ibcon#enter sib2, iclass 27, count 0 2006.173.19:32:11.45#ibcon#flushed, iclass 27, count 0 2006.173.19:32:11.45#ibcon#about to write, iclass 27, count 0 2006.173.19:32:11.45#ibcon#wrote, iclass 27, count 0 2006.173.19:32:11.45#ibcon#about to read 3, iclass 27, count 0 2006.173.19:32:11.47#ibcon#read 3, iclass 27, count 0 2006.173.19:32:11.47#ibcon#about to read 4, iclass 27, count 0 2006.173.19:32:11.47#ibcon#read 4, iclass 27, count 0 2006.173.19:32:11.47#ibcon#about to read 5, iclass 27, count 0 2006.173.19:32:11.47#ibcon#read 5, iclass 27, count 0 2006.173.19:32:11.47#ibcon#about to read 6, iclass 27, count 0 2006.173.19:32:11.47#ibcon#read 6, iclass 27, count 0 2006.173.19:32:11.47#ibcon#end of sib2, iclass 27, count 0 2006.173.19:32:11.47#ibcon#*mode == 0, iclass 27, count 0 2006.173.19:32:11.47#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.19:32:11.47#ibcon#[25=USB\r\n] 2006.173.19:32:11.47#ibcon#*before write, iclass 27, count 0 2006.173.19:32:11.47#ibcon#enter sib2, iclass 27, count 0 2006.173.19:32:11.47#ibcon#flushed, iclass 27, count 0 2006.173.19:32:11.47#ibcon#about to write, iclass 27, count 0 2006.173.19:32:11.47#ibcon#wrote, iclass 27, count 0 2006.173.19:32:11.47#ibcon#about to read 3, iclass 27, count 0 2006.173.19:32:11.50#ibcon#read 3, iclass 27, count 0 2006.173.19:32:11.50#ibcon#about to read 4, iclass 27, count 0 2006.173.19:32:11.50#ibcon#read 4, iclass 27, count 0 2006.173.19:32:11.50#ibcon#about to read 5, iclass 27, count 0 2006.173.19:32:11.50#ibcon#read 5, iclass 27, count 0 2006.173.19:32:11.50#ibcon#about to read 6, iclass 27, count 0 2006.173.19:32:11.50#ibcon#read 6, iclass 27, count 0 2006.173.19:32:11.50#ibcon#end of sib2, iclass 27, count 0 2006.173.19:32:11.50#ibcon#*after write, iclass 27, count 0 2006.173.19:32:11.50#ibcon#*before return 0, iclass 27, count 0 2006.173.19:32:11.50#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.19:32:11.50#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.19:32:11.50#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.19:32:11.50#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.19:32:11.50$vck44/valo=8,884.99 2006.173.19:32:11.50#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.19:32:11.50#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.19:32:11.50#ibcon#ireg 17 cls_cnt 0 2006.173.19:32:11.50#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.19:32:11.50#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.19:32:11.50#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.19:32:11.50#ibcon#enter wrdev, iclass 29, count 0 2006.173.19:32:11.50#ibcon#first serial, iclass 29, count 0 2006.173.19:32:11.50#ibcon#enter sib2, iclass 29, count 0 2006.173.19:32:11.50#ibcon#flushed, iclass 29, count 0 2006.173.19:32:11.50#ibcon#about to write, iclass 29, count 0 2006.173.19:32:11.50#ibcon#wrote, iclass 29, count 0 2006.173.19:32:11.50#ibcon#about to read 3, iclass 29, count 0 2006.173.19:32:11.52#ibcon#read 3, iclass 29, count 0 2006.173.19:32:11.52#ibcon#about to read 4, iclass 29, count 0 2006.173.19:32:11.52#ibcon#read 4, iclass 29, count 0 2006.173.19:32:11.52#ibcon#about to read 5, iclass 29, count 0 2006.173.19:32:11.52#ibcon#read 5, iclass 29, count 0 2006.173.19:32:11.52#ibcon#about to read 6, iclass 29, count 0 2006.173.19:32:11.52#ibcon#read 6, iclass 29, count 0 2006.173.19:32:11.52#ibcon#end of sib2, iclass 29, count 0 2006.173.19:32:11.52#ibcon#*mode == 0, iclass 29, count 0 2006.173.19:32:11.52#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.19:32:11.52#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.19:32:11.52#ibcon#*before write, iclass 29, count 0 2006.173.19:32:11.52#ibcon#enter sib2, iclass 29, count 0 2006.173.19:32:11.52#ibcon#flushed, iclass 29, count 0 2006.173.19:32:11.52#ibcon#about to write, iclass 29, count 0 2006.173.19:32:11.52#ibcon#wrote, iclass 29, count 0 2006.173.19:32:11.52#ibcon#about to read 3, iclass 29, count 0 2006.173.19:32:11.56#ibcon#read 3, iclass 29, count 0 2006.173.19:32:11.56#ibcon#about to read 4, iclass 29, count 0 2006.173.19:32:11.56#ibcon#read 4, iclass 29, count 0 2006.173.19:32:11.56#ibcon#about to read 5, iclass 29, count 0 2006.173.19:32:11.56#ibcon#read 5, iclass 29, count 0 2006.173.19:32:11.56#ibcon#about to read 6, iclass 29, count 0 2006.173.19:32:11.56#ibcon#read 6, iclass 29, count 0 2006.173.19:32:11.56#ibcon#end of sib2, iclass 29, count 0 2006.173.19:32:11.56#ibcon#*after write, iclass 29, count 0 2006.173.19:32:11.56#ibcon#*before return 0, iclass 29, count 0 2006.173.19:32:11.56#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.19:32:11.56#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.19:32:11.56#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.19:32:11.56#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.19:32:11.56$vck44/va=8,4 2006.173.19:32:11.56#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.19:32:11.56#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.19:32:11.56#ibcon#ireg 11 cls_cnt 2 2006.173.19:32:11.56#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.19:32:11.62#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.19:32:11.62#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.19:32:11.62#ibcon#enter wrdev, iclass 31, count 2 2006.173.19:32:11.62#ibcon#first serial, iclass 31, count 2 2006.173.19:32:11.62#ibcon#enter sib2, iclass 31, count 2 2006.173.19:32:11.62#ibcon#flushed, iclass 31, count 2 2006.173.19:32:11.62#ibcon#about to write, iclass 31, count 2 2006.173.19:32:11.62#ibcon#wrote, iclass 31, count 2 2006.173.19:32:11.62#ibcon#about to read 3, iclass 31, count 2 2006.173.19:32:11.64#ibcon#read 3, iclass 31, count 2 2006.173.19:32:11.64#ibcon#about to read 4, iclass 31, count 2 2006.173.19:32:11.64#ibcon#read 4, iclass 31, count 2 2006.173.19:32:11.64#ibcon#about to read 5, iclass 31, count 2 2006.173.19:32:11.64#ibcon#read 5, iclass 31, count 2 2006.173.19:32:11.64#ibcon#about to read 6, iclass 31, count 2 2006.173.19:32:11.64#ibcon#read 6, iclass 31, count 2 2006.173.19:32:11.64#ibcon#end of sib2, iclass 31, count 2 2006.173.19:32:11.64#ibcon#*mode == 0, iclass 31, count 2 2006.173.19:32:11.64#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.19:32:11.64#ibcon#[25=AT08-04\r\n] 2006.173.19:32:11.64#ibcon#*before write, iclass 31, count 2 2006.173.19:32:11.64#ibcon#enter sib2, iclass 31, count 2 2006.173.19:32:11.64#ibcon#flushed, iclass 31, count 2 2006.173.19:32:11.64#ibcon#about to write, iclass 31, count 2 2006.173.19:32:11.64#ibcon#wrote, iclass 31, count 2 2006.173.19:32:11.64#ibcon#about to read 3, iclass 31, count 2 2006.173.19:32:11.67#ibcon#read 3, iclass 31, count 2 2006.173.19:32:11.67#ibcon#about to read 4, iclass 31, count 2 2006.173.19:32:11.67#ibcon#read 4, iclass 31, count 2 2006.173.19:32:11.67#ibcon#about to read 5, iclass 31, count 2 2006.173.19:32:11.67#ibcon#read 5, iclass 31, count 2 2006.173.19:32:11.67#ibcon#about to read 6, iclass 31, count 2 2006.173.19:32:11.67#ibcon#read 6, iclass 31, count 2 2006.173.19:32:11.67#ibcon#end of sib2, iclass 31, count 2 2006.173.19:32:11.67#ibcon#*after write, iclass 31, count 2 2006.173.19:32:11.67#ibcon#*before return 0, iclass 31, count 2 2006.173.19:32:11.67#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.19:32:11.67#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.19:32:11.67#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.19:32:11.67#ibcon#ireg 7 cls_cnt 0 2006.173.19:32:11.67#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.19:32:11.79#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.19:32:11.79#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.19:32:11.79#ibcon#enter wrdev, iclass 31, count 0 2006.173.19:32:11.79#ibcon#first serial, iclass 31, count 0 2006.173.19:32:11.79#ibcon#enter sib2, iclass 31, count 0 2006.173.19:32:11.79#ibcon#flushed, iclass 31, count 0 2006.173.19:32:11.79#ibcon#about to write, iclass 31, count 0 2006.173.19:32:11.79#ibcon#wrote, iclass 31, count 0 2006.173.19:32:11.79#ibcon#about to read 3, iclass 31, count 0 2006.173.19:32:11.81#ibcon#read 3, iclass 31, count 0 2006.173.19:32:11.81#ibcon#about to read 4, iclass 31, count 0 2006.173.19:32:11.81#ibcon#read 4, iclass 31, count 0 2006.173.19:32:11.81#ibcon#about to read 5, iclass 31, count 0 2006.173.19:32:11.81#ibcon#read 5, iclass 31, count 0 2006.173.19:32:11.81#ibcon#about to read 6, iclass 31, count 0 2006.173.19:32:11.81#ibcon#read 6, iclass 31, count 0 2006.173.19:32:11.81#ibcon#end of sib2, iclass 31, count 0 2006.173.19:32:11.81#ibcon#*mode == 0, iclass 31, count 0 2006.173.19:32:11.81#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.19:32:11.81#ibcon#[25=USB\r\n] 2006.173.19:32:11.81#ibcon#*before write, iclass 31, count 0 2006.173.19:32:11.81#ibcon#enter sib2, iclass 31, count 0 2006.173.19:32:11.81#ibcon#flushed, iclass 31, count 0 2006.173.19:32:11.81#ibcon#about to write, iclass 31, count 0 2006.173.19:32:11.81#ibcon#wrote, iclass 31, count 0 2006.173.19:32:11.81#ibcon#about to read 3, iclass 31, count 0 2006.173.19:32:11.84#ibcon#read 3, iclass 31, count 0 2006.173.19:32:11.84#ibcon#about to read 4, iclass 31, count 0 2006.173.19:32:11.84#ibcon#read 4, iclass 31, count 0 2006.173.19:32:11.84#ibcon#about to read 5, iclass 31, count 0 2006.173.19:32:11.84#ibcon#read 5, iclass 31, count 0 2006.173.19:32:11.84#ibcon#about to read 6, iclass 31, count 0 2006.173.19:32:11.84#ibcon#read 6, iclass 31, count 0 2006.173.19:32:11.84#ibcon#end of sib2, iclass 31, count 0 2006.173.19:32:11.84#ibcon#*after write, iclass 31, count 0 2006.173.19:32:11.84#ibcon#*before return 0, iclass 31, count 0 2006.173.19:32:11.84#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.19:32:11.84#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.19:32:11.84#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.19:32:11.84#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.19:32:11.84$vck44/vblo=1,629.99 2006.173.19:32:11.84#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.19:32:11.84#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.19:32:11.84#ibcon#ireg 17 cls_cnt 0 2006.173.19:32:11.84#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.19:32:11.84#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.19:32:11.84#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.19:32:11.84#ibcon#enter wrdev, iclass 33, count 0 2006.173.19:32:11.84#ibcon#first serial, iclass 33, count 0 2006.173.19:32:11.84#ibcon#enter sib2, iclass 33, count 0 2006.173.19:32:11.84#ibcon#flushed, iclass 33, count 0 2006.173.19:32:11.84#ibcon#about to write, iclass 33, count 0 2006.173.19:32:11.84#ibcon#wrote, iclass 33, count 0 2006.173.19:32:11.84#ibcon#about to read 3, iclass 33, count 0 2006.173.19:32:11.86#ibcon#read 3, iclass 33, count 0 2006.173.19:32:11.86#ibcon#about to read 4, iclass 33, count 0 2006.173.19:32:11.86#ibcon#read 4, iclass 33, count 0 2006.173.19:32:11.86#ibcon#about to read 5, iclass 33, count 0 2006.173.19:32:11.86#ibcon#read 5, iclass 33, count 0 2006.173.19:32:11.86#ibcon#about to read 6, iclass 33, count 0 2006.173.19:32:11.86#ibcon#read 6, iclass 33, count 0 2006.173.19:32:11.86#ibcon#end of sib2, iclass 33, count 0 2006.173.19:32:11.86#ibcon#*mode == 0, iclass 33, count 0 2006.173.19:32:11.86#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.19:32:11.86#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.19:32:11.86#ibcon#*before write, iclass 33, count 0 2006.173.19:32:11.86#ibcon#enter sib2, iclass 33, count 0 2006.173.19:32:11.86#ibcon#flushed, iclass 33, count 0 2006.173.19:32:11.86#ibcon#about to write, iclass 33, count 0 2006.173.19:32:11.86#ibcon#wrote, iclass 33, count 0 2006.173.19:32:11.86#ibcon#about to read 3, iclass 33, count 0 2006.173.19:32:11.90#ibcon#read 3, iclass 33, count 0 2006.173.19:32:11.90#ibcon#about to read 4, iclass 33, count 0 2006.173.19:32:11.90#ibcon#read 4, iclass 33, count 0 2006.173.19:32:11.90#ibcon#about to read 5, iclass 33, count 0 2006.173.19:32:11.90#ibcon#read 5, iclass 33, count 0 2006.173.19:32:11.90#ibcon#about to read 6, iclass 33, count 0 2006.173.19:32:11.90#ibcon#read 6, iclass 33, count 0 2006.173.19:32:11.90#ibcon#end of sib2, iclass 33, count 0 2006.173.19:32:11.90#ibcon#*after write, iclass 33, count 0 2006.173.19:32:11.90#ibcon#*before return 0, iclass 33, count 0 2006.173.19:32:11.90#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.19:32:11.90#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.19:32:11.90#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.19:32:11.90#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.19:32:11.90$vck44/vb=1,4 2006.173.19:32:11.90#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.19:32:11.90#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.19:32:11.90#ibcon#ireg 11 cls_cnt 2 2006.173.19:32:11.90#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.19:32:11.90#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.19:32:11.90#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.19:32:11.90#ibcon#enter wrdev, iclass 35, count 2 2006.173.19:32:11.90#ibcon#first serial, iclass 35, count 2 2006.173.19:32:11.90#ibcon#enter sib2, iclass 35, count 2 2006.173.19:32:11.90#ibcon#flushed, iclass 35, count 2 2006.173.19:32:11.90#ibcon#about to write, iclass 35, count 2 2006.173.19:32:11.90#ibcon#wrote, iclass 35, count 2 2006.173.19:32:11.90#ibcon#about to read 3, iclass 35, count 2 2006.173.19:32:11.92#ibcon#read 3, iclass 35, count 2 2006.173.19:32:11.92#ibcon#about to read 4, iclass 35, count 2 2006.173.19:32:11.92#ibcon#read 4, iclass 35, count 2 2006.173.19:32:11.92#ibcon#about to read 5, iclass 35, count 2 2006.173.19:32:11.92#ibcon#read 5, iclass 35, count 2 2006.173.19:32:11.92#ibcon#about to read 6, iclass 35, count 2 2006.173.19:32:11.92#ibcon#read 6, iclass 35, count 2 2006.173.19:32:11.92#ibcon#end of sib2, iclass 35, count 2 2006.173.19:32:11.92#ibcon#*mode == 0, iclass 35, count 2 2006.173.19:32:11.92#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.19:32:11.92#ibcon#[27=AT01-04\r\n] 2006.173.19:32:11.92#ibcon#*before write, iclass 35, count 2 2006.173.19:32:11.92#ibcon#enter sib2, iclass 35, count 2 2006.173.19:32:11.92#ibcon#flushed, iclass 35, count 2 2006.173.19:32:11.92#ibcon#about to write, iclass 35, count 2 2006.173.19:32:11.92#ibcon#wrote, iclass 35, count 2 2006.173.19:32:11.92#ibcon#about to read 3, iclass 35, count 2 2006.173.19:32:11.95#ibcon#read 3, iclass 35, count 2 2006.173.19:32:11.95#ibcon#about to read 4, iclass 35, count 2 2006.173.19:32:11.95#ibcon#read 4, iclass 35, count 2 2006.173.19:32:11.95#ibcon#about to read 5, iclass 35, count 2 2006.173.19:32:11.95#ibcon#read 5, iclass 35, count 2 2006.173.19:32:11.95#ibcon#about to read 6, iclass 35, count 2 2006.173.19:32:11.95#ibcon#read 6, iclass 35, count 2 2006.173.19:32:11.95#ibcon#end of sib2, iclass 35, count 2 2006.173.19:32:11.95#ibcon#*after write, iclass 35, count 2 2006.173.19:32:11.95#ibcon#*before return 0, iclass 35, count 2 2006.173.19:32:11.95#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.19:32:11.95#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.19:32:11.95#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.19:32:11.95#ibcon#ireg 7 cls_cnt 0 2006.173.19:32:11.95#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.19:32:12.07#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.19:32:12.07#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.19:32:12.07#ibcon#enter wrdev, iclass 35, count 0 2006.173.19:32:12.07#ibcon#first serial, iclass 35, count 0 2006.173.19:32:12.07#ibcon#enter sib2, iclass 35, count 0 2006.173.19:32:12.07#ibcon#flushed, iclass 35, count 0 2006.173.19:32:12.07#ibcon#about to write, iclass 35, count 0 2006.173.19:32:12.07#ibcon#wrote, iclass 35, count 0 2006.173.19:32:12.07#ibcon#about to read 3, iclass 35, count 0 2006.173.19:32:12.09#ibcon#read 3, iclass 35, count 0 2006.173.19:32:12.09#ibcon#about to read 4, iclass 35, count 0 2006.173.19:32:12.09#ibcon#read 4, iclass 35, count 0 2006.173.19:32:12.09#ibcon#about to read 5, iclass 35, count 0 2006.173.19:32:12.09#ibcon#read 5, iclass 35, count 0 2006.173.19:32:12.09#ibcon#about to read 6, iclass 35, count 0 2006.173.19:32:12.09#ibcon#read 6, iclass 35, count 0 2006.173.19:32:12.09#ibcon#end of sib2, iclass 35, count 0 2006.173.19:32:12.09#ibcon#*mode == 0, iclass 35, count 0 2006.173.19:32:12.09#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.19:32:12.09#ibcon#[27=USB\r\n] 2006.173.19:32:12.09#ibcon#*before write, iclass 35, count 0 2006.173.19:32:12.09#ibcon#enter sib2, iclass 35, count 0 2006.173.19:32:12.09#ibcon#flushed, iclass 35, count 0 2006.173.19:32:12.09#ibcon#about to write, iclass 35, count 0 2006.173.19:32:12.09#ibcon#wrote, iclass 35, count 0 2006.173.19:32:12.09#ibcon#about to read 3, iclass 35, count 0 2006.173.19:32:12.12#ibcon#read 3, iclass 35, count 0 2006.173.19:32:12.12#ibcon#about to read 4, iclass 35, count 0 2006.173.19:32:12.12#ibcon#read 4, iclass 35, count 0 2006.173.19:32:12.12#ibcon#about to read 5, iclass 35, count 0 2006.173.19:32:12.12#ibcon#read 5, iclass 35, count 0 2006.173.19:32:12.12#ibcon#about to read 6, iclass 35, count 0 2006.173.19:32:12.12#ibcon#read 6, iclass 35, count 0 2006.173.19:32:12.12#ibcon#end of sib2, iclass 35, count 0 2006.173.19:32:12.12#ibcon#*after write, iclass 35, count 0 2006.173.19:32:12.12#ibcon#*before return 0, iclass 35, count 0 2006.173.19:32:12.12#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.19:32:12.12#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.19:32:12.12#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.19:32:12.12#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.19:32:12.12$vck44/vblo=2,634.99 2006.173.19:32:12.12#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.19:32:12.12#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.19:32:12.12#ibcon#ireg 17 cls_cnt 0 2006.173.19:32:12.12#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.19:32:12.12#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.19:32:12.12#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.19:32:12.12#ibcon#enter wrdev, iclass 37, count 0 2006.173.19:32:12.12#ibcon#first serial, iclass 37, count 0 2006.173.19:32:12.12#ibcon#enter sib2, iclass 37, count 0 2006.173.19:32:12.12#ibcon#flushed, iclass 37, count 0 2006.173.19:32:12.12#ibcon#about to write, iclass 37, count 0 2006.173.19:32:12.12#ibcon#wrote, iclass 37, count 0 2006.173.19:32:12.12#ibcon#about to read 3, iclass 37, count 0 2006.173.19:32:12.14#ibcon#read 3, iclass 37, count 0 2006.173.19:32:12.14#ibcon#about to read 4, iclass 37, count 0 2006.173.19:32:12.14#ibcon#read 4, iclass 37, count 0 2006.173.19:32:12.14#ibcon#about to read 5, iclass 37, count 0 2006.173.19:32:12.14#ibcon#read 5, iclass 37, count 0 2006.173.19:32:12.14#ibcon#about to read 6, iclass 37, count 0 2006.173.19:32:12.14#ibcon#read 6, iclass 37, count 0 2006.173.19:32:12.14#ibcon#end of sib2, iclass 37, count 0 2006.173.19:32:12.14#ibcon#*mode == 0, iclass 37, count 0 2006.173.19:32:12.14#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.19:32:12.14#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.19:32:12.14#ibcon#*before write, iclass 37, count 0 2006.173.19:32:12.14#ibcon#enter sib2, iclass 37, count 0 2006.173.19:32:12.14#ibcon#flushed, iclass 37, count 0 2006.173.19:32:12.14#ibcon#about to write, iclass 37, count 0 2006.173.19:32:12.14#ibcon#wrote, iclass 37, count 0 2006.173.19:32:12.14#ibcon#about to read 3, iclass 37, count 0 2006.173.19:32:12.18#ibcon#read 3, iclass 37, count 0 2006.173.19:32:12.18#ibcon#about to read 4, iclass 37, count 0 2006.173.19:32:12.18#ibcon#read 4, iclass 37, count 0 2006.173.19:32:12.18#ibcon#about to read 5, iclass 37, count 0 2006.173.19:32:12.18#ibcon#read 5, iclass 37, count 0 2006.173.19:32:12.18#ibcon#about to read 6, iclass 37, count 0 2006.173.19:32:12.18#ibcon#read 6, iclass 37, count 0 2006.173.19:32:12.18#ibcon#end of sib2, iclass 37, count 0 2006.173.19:32:12.18#ibcon#*after write, iclass 37, count 0 2006.173.19:32:12.18#ibcon#*before return 0, iclass 37, count 0 2006.173.19:32:12.18#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.19:32:12.18#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.19:32:12.18#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.19:32:12.18#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.19:32:12.18$vck44/vb=2,4 2006.173.19:32:12.18#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.19:32:12.18#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.19:32:12.18#ibcon#ireg 11 cls_cnt 2 2006.173.19:32:12.18#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.19:32:12.24#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.19:32:12.24#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.19:32:12.24#ibcon#enter wrdev, iclass 39, count 2 2006.173.19:32:12.24#ibcon#first serial, iclass 39, count 2 2006.173.19:32:12.24#ibcon#enter sib2, iclass 39, count 2 2006.173.19:32:12.24#ibcon#flushed, iclass 39, count 2 2006.173.19:32:12.24#ibcon#about to write, iclass 39, count 2 2006.173.19:32:12.24#ibcon#wrote, iclass 39, count 2 2006.173.19:32:12.24#ibcon#about to read 3, iclass 39, count 2 2006.173.19:32:12.26#ibcon#read 3, iclass 39, count 2 2006.173.19:32:12.26#ibcon#about to read 4, iclass 39, count 2 2006.173.19:32:12.26#ibcon#read 4, iclass 39, count 2 2006.173.19:32:12.26#ibcon#about to read 5, iclass 39, count 2 2006.173.19:32:12.26#ibcon#read 5, iclass 39, count 2 2006.173.19:32:12.26#ibcon#about to read 6, iclass 39, count 2 2006.173.19:32:12.26#ibcon#read 6, iclass 39, count 2 2006.173.19:32:12.26#ibcon#end of sib2, iclass 39, count 2 2006.173.19:32:12.26#ibcon#*mode == 0, iclass 39, count 2 2006.173.19:32:12.26#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.19:32:12.26#ibcon#[27=AT02-04\r\n] 2006.173.19:32:12.26#ibcon#*before write, iclass 39, count 2 2006.173.19:32:12.26#ibcon#enter sib2, iclass 39, count 2 2006.173.19:32:12.26#ibcon#flushed, iclass 39, count 2 2006.173.19:32:12.26#ibcon#about to write, iclass 39, count 2 2006.173.19:32:12.26#ibcon#wrote, iclass 39, count 2 2006.173.19:32:12.26#ibcon#about to read 3, iclass 39, count 2 2006.173.19:32:12.29#ibcon#read 3, iclass 39, count 2 2006.173.19:32:12.29#ibcon#about to read 4, iclass 39, count 2 2006.173.19:32:12.29#ibcon#read 4, iclass 39, count 2 2006.173.19:32:12.29#ibcon#about to read 5, iclass 39, count 2 2006.173.19:32:12.29#ibcon#read 5, iclass 39, count 2 2006.173.19:32:12.29#ibcon#about to read 6, iclass 39, count 2 2006.173.19:32:12.29#ibcon#read 6, iclass 39, count 2 2006.173.19:32:12.29#ibcon#end of sib2, iclass 39, count 2 2006.173.19:32:12.29#ibcon#*after write, iclass 39, count 2 2006.173.19:32:12.29#ibcon#*before return 0, iclass 39, count 2 2006.173.19:32:12.29#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.19:32:12.29#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.19:32:12.29#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.19:32:12.29#ibcon#ireg 7 cls_cnt 0 2006.173.19:32:12.29#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.19:32:12.41#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.19:32:12.41#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.19:32:12.41#ibcon#enter wrdev, iclass 39, count 0 2006.173.19:32:12.41#ibcon#first serial, iclass 39, count 0 2006.173.19:32:12.41#ibcon#enter sib2, iclass 39, count 0 2006.173.19:32:12.41#ibcon#flushed, iclass 39, count 0 2006.173.19:32:12.41#ibcon#about to write, iclass 39, count 0 2006.173.19:32:12.41#ibcon#wrote, iclass 39, count 0 2006.173.19:32:12.41#ibcon#about to read 3, iclass 39, count 0 2006.173.19:32:12.43#ibcon#read 3, iclass 39, count 0 2006.173.19:32:12.43#ibcon#about to read 4, iclass 39, count 0 2006.173.19:32:12.43#ibcon#read 4, iclass 39, count 0 2006.173.19:32:12.43#ibcon#about to read 5, iclass 39, count 0 2006.173.19:32:12.43#ibcon#read 5, iclass 39, count 0 2006.173.19:32:12.43#ibcon#about to read 6, iclass 39, count 0 2006.173.19:32:12.43#ibcon#read 6, iclass 39, count 0 2006.173.19:32:12.43#ibcon#end of sib2, iclass 39, count 0 2006.173.19:32:12.43#ibcon#*mode == 0, iclass 39, count 0 2006.173.19:32:12.43#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.19:32:12.43#ibcon#[27=USB\r\n] 2006.173.19:32:12.43#ibcon#*before write, iclass 39, count 0 2006.173.19:32:12.43#ibcon#enter sib2, iclass 39, count 0 2006.173.19:32:12.43#ibcon#flushed, iclass 39, count 0 2006.173.19:32:12.43#ibcon#about to write, iclass 39, count 0 2006.173.19:32:12.43#ibcon#wrote, iclass 39, count 0 2006.173.19:32:12.43#ibcon#about to read 3, iclass 39, count 0 2006.173.19:32:12.46#ibcon#read 3, iclass 39, count 0 2006.173.19:32:12.46#ibcon#about to read 4, iclass 39, count 0 2006.173.19:32:12.46#ibcon#read 4, iclass 39, count 0 2006.173.19:32:12.46#ibcon#about to read 5, iclass 39, count 0 2006.173.19:32:12.46#ibcon#read 5, iclass 39, count 0 2006.173.19:32:12.46#ibcon#about to read 6, iclass 39, count 0 2006.173.19:32:12.46#ibcon#read 6, iclass 39, count 0 2006.173.19:32:12.46#ibcon#end of sib2, iclass 39, count 0 2006.173.19:32:12.46#ibcon#*after write, iclass 39, count 0 2006.173.19:32:12.46#ibcon#*before return 0, iclass 39, count 0 2006.173.19:32:12.46#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.19:32:12.46#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.19:32:12.46#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.19:32:12.46#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.19:32:12.46$vck44/vblo=3,649.99 2006.173.19:32:12.46#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.19:32:12.46#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.19:32:12.46#ibcon#ireg 17 cls_cnt 0 2006.173.19:32:12.46#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.19:32:12.46#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.19:32:12.46#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.19:32:12.46#ibcon#enter wrdev, iclass 3, count 0 2006.173.19:32:12.46#ibcon#first serial, iclass 3, count 0 2006.173.19:32:12.46#ibcon#enter sib2, iclass 3, count 0 2006.173.19:32:12.46#ibcon#flushed, iclass 3, count 0 2006.173.19:32:12.46#ibcon#about to write, iclass 3, count 0 2006.173.19:32:12.46#ibcon#wrote, iclass 3, count 0 2006.173.19:32:12.46#ibcon#about to read 3, iclass 3, count 0 2006.173.19:32:12.48#ibcon#read 3, iclass 3, count 0 2006.173.19:32:12.48#ibcon#about to read 4, iclass 3, count 0 2006.173.19:32:12.48#ibcon#read 4, iclass 3, count 0 2006.173.19:32:12.48#ibcon#about to read 5, iclass 3, count 0 2006.173.19:32:12.48#ibcon#read 5, iclass 3, count 0 2006.173.19:32:12.48#ibcon#about to read 6, iclass 3, count 0 2006.173.19:32:12.48#ibcon#read 6, iclass 3, count 0 2006.173.19:32:12.48#ibcon#end of sib2, iclass 3, count 0 2006.173.19:32:12.48#ibcon#*mode == 0, iclass 3, count 0 2006.173.19:32:12.48#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.19:32:12.48#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.19:32:12.48#ibcon#*before write, iclass 3, count 0 2006.173.19:32:12.48#ibcon#enter sib2, iclass 3, count 0 2006.173.19:32:12.48#ibcon#flushed, iclass 3, count 0 2006.173.19:32:12.48#ibcon#about to write, iclass 3, count 0 2006.173.19:32:12.48#ibcon#wrote, iclass 3, count 0 2006.173.19:32:12.48#ibcon#about to read 3, iclass 3, count 0 2006.173.19:32:12.52#ibcon#read 3, iclass 3, count 0 2006.173.19:32:12.52#ibcon#about to read 4, iclass 3, count 0 2006.173.19:32:12.52#ibcon#read 4, iclass 3, count 0 2006.173.19:32:12.52#ibcon#about to read 5, iclass 3, count 0 2006.173.19:32:12.52#ibcon#read 5, iclass 3, count 0 2006.173.19:32:12.52#ibcon#about to read 6, iclass 3, count 0 2006.173.19:32:12.52#ibcon#read 6, iclass 3, count 0 2006.173.19:32:12.52#ibcon#end of sib2, iclass 3, count 0 2006.173.19:32:12.52#ibcon#*after write, iclass 3, count 0 2006.173.19:32:12.52#ibcon#*before return 0, iclass 3, count 0 2006.173.19:32:12.52#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.19:32:12.52#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.19:32:12.52#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.19:32:12.52#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.19:32:12.52$vck44/vb=3,4 2006.173.19:32:12.52#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.19:32:12.52#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.19:32:12.52#ibcon#ireg 11 cls_cnt 2 2006.173.19:32:12.52#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.19:32:12.58#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.19:32:12.58#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.19:32:12.58#ibcon#enter wrdev, iclass 5, count 2 2006.173.19:32:12.58#ibcon#first serial, iclass 5, count 2 2006.173.19:32:12.58#ibcon#enter sib2, iclass 5, count 2 2006.173.19:32:12.58#ibcon#flushed, iclass 5, count 2 2006.173.19:32:12.58#ibcon#about to write, iclass 5, count 2 2006.173.19:32:12.58#ibcon#wrote, iclass 5, count 2 2006.173.19:32:12.58#ibcon#about to read 3, iclass 5, count 2 2006.173.19:32:12.60#ibcon#read 3, iclass 5, count 2 2006.173.19:32:12.60#ibcon#about to read 4, iclass 5, count 2 2006.173.19:32:12.60#ibcon#read 4, iclass 5, count 2 2006.173.19:32:12.60#ibcon#about to read 5, iclass 5, count 2 2006.173.19:32:12.60#ibcon#read 5, iclass 5, count 2 2006.173.19:32:12.60#ibcon#about to read 6, iclass 5, count 2 2006.173.19:32:12.60#ibcon#read 6, iclass 5, count 2 2006.173.19:32:12.60#ibcon#end of sib2, iclass 5, count 2 2006.173.19:32:12.60#ibcon#*mode == 0, iclass 5, count 2 2006.173.19:32:12.60#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.19:32:12.60#ibcon#[27=AT03-04\r\n] 2006.173.19:32:12.60#ibcon#*before write, iclass 5, count 2 2006.173.19:32:12.60#ibcon#enter sib2, iclass 5, count 2 2006.173.19:32:12.60#ibcon#flushed, iclass 5, count 2 2006.173.19:32:12.60#ibcon#about to write, iclass 5, count 2 2006.173.19:32:12.60#ibcon#wrote, iclass 5, count 2 2006.173.19:32:12.60#ibcon#about to read 3, iclass 5, count 2 2006.173.19:32:12.63#ibcon#read 3, iclass 5, count 2 2006.173.19:32:12.63#ibcon#about to read 4, iclass 5, count 2 2006.173.19:32:12.63#ibcon#read 4, iclass 5, count 2 2006.173.19:32:12.63#ibcon#about to read 5, iclass 5, count 2 2006.173.19:32:12.63#ibcon#read 5, iclass 5, count 2 2006.173.19:32:12.63#ibcon#about to read 6, iclass 5, count 2 2006.173.19:32:12.63#ibcon#read 6, iclass 5, count 2 2006.173.19:32:12.63#ibcon#end of sib2, iclass 5, count 2 2006.173.19:32:12.63#ibcon#*after write, iclass 5, count 2 2006.173.19:32:12.63#ibcon#*before return 0, iclass 5, count 2 2006.173.19:32:12.63#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.19:32:12.63#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.19:32:12.63#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.19:32:12.63#ibcon#ireg 7 cls_cnt 0 2006.173.19:32:12.63#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.19:32:12.75#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.19:32:12.75#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.19:32:12.75#ibcon#enter wrdev, iclass 5, count 0 2006.173.19:32:12.75#ibcon#first serial, iclass 5, count 0 2006.173.19:32:12.75#ibcon#enter sib2, iclass 5, count 0 2006.173.19:32:12.75#ibcon#flushed, iclass 5, count 0 2006.173.19:32:12.75#ibcon#about to write, iclass 5, count 0 2006.173.19:32:12.75#ibcon#wrote, iclass 5, count 0 2006.173.19:32:12.75#ibcon#about to read 3, iclass 5, count 0 2006.173.19:32:12.77#ibcon#read 3, iclass 5, count 0 2006.173.19:32:12.77#ibcon#about to read 4, iclass 5, count 0 2006.173.19:32:12.77#ibcon#read 4, iclass 5, count 0 2006.173.19:32:12.77#ibcon#about to read 5, iclass 5, count 0 2006.173.19:32:12.77#ibcon#read 5, iclass 5, count 0 2006.173.19:32:12.77#ibcon#about to read 6, iclass 5, count 0 2006.173.19:32:12.77#ibcon#read 6, iclass 5, count 0 2006.173.19:32:12.77#ibcon#end of sib2, iclass 5, count 0 2006.173.19:32:12.77#ibcon#*mode == 0, iclass 5, count 0 2006.173.19:32:12.77#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.19:32:12.77#ibcon#[27=USB\r\n] 2006.173.19:32:12.77#ibcon#*before write, iclass 5, count 0 2006.173.19:32:12.77#ibcon#enter sib2, iclass 5, count 0 2006.173.19:32:12.77#ibcon#flushed, iclass 5, count 0 2006.173.19:32:12.77#ibcon#about to write, iclass 5, count 0 2006.173.19:32:12.77#ibcon#wrote, iclass 5, count 0 2006.173.19:32:12.77#ibcon#about to read 3, iclass 5, count 0 2006.173.19:32:12.80#ibcon#read 3, iclass 5, count 0 2006.173.19:32:12.80#ibcon#about to read 4, iclass 5, count 0 2006.173.19:32:12.80#ibcon#read 4, iclass 5, count 0 2006.173.19:32:12.80#ibcon#about to read 5, iclass 5, count 0 2006.173.19:32:12.80#ibcon#read 5, iclass 5, count 0 2006.173.19:32:12.80#ibcon#about to read 6, iclass 5, count 0 2006.173.19:32:12.80#ibcon#read 6, iclass 5, count 0 2006.173.19:32:12.80#ibcon#end of sib2, iclass 5, count 0 2006.173.19:32:12.80#ibcon#*after write, iclass 5, count 0 2006.173.19:32:12.80#ibcon#*before return 0, iclass 5, count 0 2006.173.19:32:12.80#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.19:32:12.80#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.19:32:12.80#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.19:32:12.80#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.19:32:12.80$vck44/vblo=4,679.99 2006.173.19:32:12.80#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.19:32:12.80#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.19:32:12.80#ibcon#ireg 17 cls_cnt 0 2006.173.19:32:12.80#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.19:32:12.80#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.19:32:12.80#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.19:32:12.80#ibcon#enter wrdev, iclass 7, count 0 2006.173.19:32:12.80#ibcon#first serial, iclass 7, count 0 2006.173.19:32:12.80#ibcon#enter sib2, iclass 7, count 0 2006.173.19:32:12.80#ibcon#flushed, iclass 7, count 0 2006.173.19:32:12.80#ibcon#about to write, iclass 7, count 0 2006.173.19:32:12.80#ibcon#wrote, iclass 7, count 0 2006.173.19:32:12.80#ibcon#about to read 3, iclass 7, count 0 2006.173.19:32:12.82#ibcon#read 3, iclass 7, count 0 2006.173.19:32:12.82#ibcon#about to read 4, iclass 7, count 0 2006.173.19:32:12.82#ibcon#read 4, iclass 7, count 0 2006.173.19:32:12.82#ibcon#about to read 5, iclass 7, count 0 2006.173.19:32:12.82#ibcon#read 5, iclass 7, count 0 2006.173.19:32:12.82#ibcon#about to read 6, iclass 7, count 0 2006.173.19:32:12.82#ibcon#read 6, iclass 7, count 0 2006.173.19:32:12.82#ibcon#end of sib2, iclass 7, count 0 2006.173.19:32:12.82#ibcon#*mode == 0, iclass 7, count 0 2006.173.19:32:12.82#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.19:32:12.82#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.19:32:12.82#ibcon#*before write, iclass 7, count 0 2006.173.19:32:12.82#ibcon#enter sib2, iclass 7, count 0 2006.173.19:32:12.82#ibcon#flushed, iclass 7, count 0 2006.173.19:32:12.82#ibcon#about to write, iclass 7, count 0 2006.173.19:32:12.82#ibcon#wrote, iclass 7, count 0 2006.173.19:32:12.82#ibcon#about to read 3, iclass 7, count 0 2006.173.19:32:12.86#ibcon#read 3, iclass 7, count 0 2006.173.19:32:12.86#ibcon#about to read 4, iclass 7, count 0 2006.173.19:32:12.86#ibcon#read 4, iclass 7, count 0 2006.173.19:32:12.86#ibcon#about to read 5, iclass 7, count 0 2006.173.19:32:12.86#ibcon#read 5, iclass 7, count 0 2006.173.19:32:12.86#ibcon#about to read 6, iclass 7, count 0 2006.173.19:32:12.86#ibcon#read 6, iclass 7, count 0 2006.173.19:32:12.86#ibcon#end of sib2, iclass 7, count 0 2006.173.19:32:12.86#ibcon#*after write, iclass 7, count 0 2006.173.19:32:12.86#ibcon#*before return 0, iclass 7, count 0 2006.173.19:32:12.86#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.19:32:12.86#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.19:32:12.86#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.19:32:12.86#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.19:32:12.86$vck44/vb=4,4 2006.173.19:32:12.86#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.19:32:12.86#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.19:32:12.86#ibcon#ireg 11 cls_cnt 2 2006.173.19:32:12.86#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.19:32:12.92#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.19:32:12.92#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.19:32:12.92#ibcon#enter wrdev, iclass 11, count 2 2006.173.19:32:12.92#ibcon#first serial, iclass 11, count 2 2006.173.19:32:12.92#ibcon#enter sib2, iclass 11, count 2 2006.173.19:32:12.92#ibcon#flushed, iclass 11, count 2 2006.173.19:32:12.92#ibcon#about to write, iclass 11, count 2 2006.173.19:32:12.92#ibcon#wrote, iclass 11, count 2 2006.173.19:32:12.92#ibcon#about to read 3, iclass 11, count 2 2006.173.19:32:12.94#ibcon#read 3, iclass 11, count 2 2006.173.19:32:12.94#ibcon#about to read 4, iclass 11, count 2 2006.173.19:32:12.94#ibcon#read 4, iclass 11, count 2 2006.173.19:32:12.94#ibcon#about to read 5, iclass 11, count 2 2006.173.19:32:12.94#ibcon#read 5, iclass 11, count 2 2006.173.19:32:12.94#ibcon#about to read 6, iclass 11, count 2 2006.173.19:32:12.94#ibcon#read 6, iclass 11, count 2 2006.173.19:32:12.94#ibcon#end of sib2, iclass 11, count 2 2006.173.19:32:12.94#ibcon#*mode == 0, iclass 11, count 2 2006.173.19:32:12.94#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.19:32:12.94#ibcon#[27=AT04-04\r\n] 2006.173.19:32:12.94#ibcon#*before write, iclass 11, count 2 2006.173.19:32:12.94#ibcon#enter sib2, iclass 11, count 2 2006.173.19:32:12.94#ibcon#flushed, iclass 11, count 2 2006.173.19:32:12.94#ibcon#about to write, iclass 11, count 2 2006.173.19:32:12.94#ibcon#wrote, iclass 11, count 2 2006.173.19:32:12.94#ibcon#about to read 3, iclass 11, count 2 2006.173.19:32:12.97#ibcon#read 3, iclass 11, count 2 2006.173.19:32:12.97#ibcon#about to read 4, iclass 11, count 2 2006.173.19:32:12.97#ibcon#read 4, iclass 11, count 2 2006.173.19:32:12.97#ibcon#about to read 5, iclass 11, count 2 2006.173.19:32:12.97#ibcon#read 5, iclass 11, count 2 2006.173.19:32:12.97#ibcon#about to read 6, iclass 11, count 2 2006.173.19:32:12.97#ibcon#read 6, iclass 11, count 2 2006.173.19:32:12.97#ibcon#end of sib2, iclass 11, count 2 2006.173.19:32:12.97#ibcon#*after write, iclass 11, count 2 2006.173.19:32:12.97#ibcon#*before return 0, iclass 11, count 2 2006.173.19:32:12.97#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.19:32:12.97#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.19:32:12.97#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.19:32:12.97#ibcon#ireg 7 cls_cnt 0 2006.173.19:32:12.97#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.19:32:13.09#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.19:32:13.09#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.19:32:13.09#ibcon#enter wrdev, iclass 11, count 0 2006.173.19:32:13.09#ibcon#first serial, iclass 11, count 0 2006.173.19:32:13.09#ibcon#enter sib2, iclass 11, count 0 2006.173.19:32:13.09#ibcon#flushed, iclass 11, count 0 2006.173.19:32:13.09#ibcon#about to write, iclass 11, count 0 2006.173.19:32:13.09#ibcon#wrote, iclass 11, count 0 2006.173.19:32:13.09#ibcon#about to read 3, iclass 11, count 0 2006.173.19:32:13.11#ibcon#read 3, iclass 11, count 0 2006.173.19:32:13.11#ibcon#about to read 4, iclass 11, count 0 2006.173.19:32:13.11#ibcon#read 4, iclass 11, count 0 2006.173.19:32:13.11#ibcon#about to read 5, iclass 11, count 0 2006.173.19:32:13.11#ibcon#read 5, iclass 11, count 0 2006.173.19:32:13.11#ibcon#about to read 6, iclass 11, count 0 2006.173.19:32:13.11#ibcon#read 6, iclass 11, count 0 2006.173.19:32:13.11#ibcon#end of sib2, iclass 11, count 0 2006.173.19:32:13.11#ibcon#*mode == 0, iclass 11, count 0 2006.173.19:32:13.11#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.19:32:13.11#ibcon#[27=USB\r\n] 2006.173.19:32:13.11#ibcon#*before write, iclass 11, count 0 2006.173.19:32:13.11#ibcon#enter sib2, iclass 11, count 0 2006.173.19:32:13.11#ibcon#flushed, iclass 11, count 0 2006.173.19:32:13.11#ibcon#about to write, iclass 11, count 0 2006.173.19:32:13.11#ibcon#wrote, iclass 11, count 0 2006.173.19:32:13.11#ibcon#about to read 3, iclass 11, count 0 2006.173.19:32:13.14#ibcon#read 3, iclass 11, count 0 2006.173.19:32:13.14#ibcon#about to read 4, iclass 11, count 0 2006.173.19:32:13.14#ibcon#read 4, iclass 11, count 0 2006.173.19:32:13.14#ibcon#about to read 5, iclass 11, count 0 2006.173.19:32:13.14#ibcon#read 5, iclass 11, count 0 2006.173.19:32:13.14#ibcon#about to read 6, iclass 11, count 0 2006.173.19:32:13.14#ibcon#read 6, iclass 11, count 0 2006.173.19:32:13.14#ibcon#end of sib2, iclass 11, count 0 2006.173.19:32:13.14#ibcon#*after write, iclass 11, count 0 2006.173.19:32:13.14#ibcon#*before return 0, iclass 11, count 0 2006.173.19:32:13.14#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.19:32:13.14#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.19:32:13.14#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.19:32:13.14#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.19:32:13.14$vck44/vblo=5,709.99 2006.173.19:32:13.14#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.19:32:13.14#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.19:32:13.14#ibcon#ireg 17 cls_cnt 0 2006.173.19:32:13.14#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.19:32:13.14#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.19:32:13.14#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.19:32:13.14#ibcon#enter wrdev, iclass 13, count 0 2006.173.19:32:13.14#ibcon#first serial, iclass 13, count 0 2006.173.19:32:13.14#ibcon#enter sib2, iclass 13, count 0 2006.173.19:32:13.14#ibcon#flushed, iclass 13, count 0 2006.173.19:32:13.14#ibcon#about to write, iclass 13, count 0 2006.173.19:32:13.14#ibcon#wrote, iclass 13, count 0 2006.173.19:32:13.14#ibcon#about to read 3, iclass 13, count 0 2006.173.19:32:13.16#ibcon#read 3, iclass 13, count 0 2006.173.19:32:13.16#ibcon#about to read 4, iclass 13, count 0 2006.173.19:32:13.16#ibcon#read 4, iclass 13, count 0 2006.173.19:32:13.16#ibcon#about to read 5, iclass 13, count 0 2006.173.19:32:13.16#ibcon#read 5, iclass 13, count 0 2006.173.19:32:13.16#ibcon#about to read 6, iclass 13, count 0 2006.173.19:32:13.16#ibcon#read 6, iclass 13, count 0 2006.173.19:32:13.16#ibcon#end of sib2, iclass 13, count 0 2006.173.19:32:13.16#ibcon#*mode == 0, iclass 13, count 0 2006.173.19:32:13.16#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.19:32:13.16#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.19:32:13.16#ibcon#*before write, iclass 13, count 0 2006.173.19:32:13.16#ibcon#enter sib2, iclass 13, count 0 2006.173.19:32:13.16#ibcon#flushed, iclass 13, count 0 2006.173.19:32:13.16#ibcon#about to write, iclass 13, count 0 2006.173.19:32:13.16#ibcon#wrote, iclass 13, count 0 2006.173.19:32:13.16#ibcon#about to read 3, iclass 13, count 0 2006.173.19:32:13.20#ibcon#read 3, iclass 13, count 0 2006.173.19:32:13.20#ibcon#about to read 4, iclass 13, count 0 2006.173.19:32:13.20#ibcon#read 4, iclass 13, count 0 2006.173.19:32:13.20#ibcon#about to read 5, iclass 13, count 0 2006.173.19:32:13.20#ibcon#read 5, iclass 13, count 0 2006.173.19:32:13.20#ibcon#about to read 6, iclass 13, count 0 2006.173.19:32:13.20#ibcon#read 6, iclass 13, count 0 2006.173.19:32:13.20#ibcon#end of sib2, iclass 13, count 0 2006.173.19:32:13.20#ibcon#*after write, iclass 13, count 0 2006.173.19:32:13.20#ibcon#*before return 0, iclass 13, count 0 2006.173.19:32:13.20#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.19:32:13.20#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.19:32:13.20#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.19:32:13.20#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.19:32:13.20$vck44/vb=5,4 2006.173.19:32:13.20#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.19:32:13.20#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.19:32:13.20#ibcon#ireg 11 cls_cnt 2 2006.173.19:32:13.20#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.19:32:13.22#abcon#<5=/00 0.2 0.6 19.391001002.5\r\n> 2006.173.19:32:13.24#abcon#{5=INTERFACE CLEAR} 2006.173.19:32:13.26#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.19:32:13.26#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.19:32:13.26#ibcon#enter wrdev, iclass 16, count 2 2006.173.19:32:13.26#ibcon#first serial, iclass 16, count 2 2006.173.19:32:13.26#ibcon#enter sib2, iclass 16, count 2 2006.173.19:32:13.26#ibcon#flushed, iclass 16, count 2 2006.173.19:32:13.26#ibcon#about to write, iclass 16, count 2 2006.173.19:32:13.26#ibcon#wrote, iclass 16, count 2 2006.173.19:32:13.26#ibcon#about to read 3, iclass 16, count 2 2006.173.19:32:13.28#ibcon#read 3, iclass 16, count 2 2006.173.19:32:13.28#ibcon#about to read 4, iclass 16, count 2 2006.173.19:32:13.28#ibcon#read 4, iclass 16, count 2 2006.173.19:32:13.28#ibcon#about to read 5, iclass 16, count 2 2006.173.19:32:13.28#ibcon#read 5, iclass 16, count 2 2006.173.19:32:13.28#ibcon#about to read 6, iclass 16, count 2 2006.173.19:32:13.28#ibcon#read 6, iclass 16, count 2 2006.173.19:32:13.28#ibcon#end of sib2, iclass 16, count 2 2006.173.19:32:13.28#ibcon#*mode == 0, iclass 16, count 2 2006.173.19:32:13.28#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.19:32:13.28#ibcon#[27=AT05-04\r\n] 2006.173.19:32:13.28#ibcon#*before write, iclass 16, count 2 2006.173.19:32:13.28#ibcon#enter sib2, iclass 16, count 2 2006.173.19:32:13.28#ibcon#flushed, iclass 16, count 2 2006.173.19:32:13.28#ibcon#about to write, iclass 16, count 2 2006.173.19:32:13.28#ibcon#wrote, iclass 16, count 2 2006.173.19:32:13.28#ibcon#about to read 3, iclass 16, count 2 2006.173.19:32:13.30#abcon#[5=S1D000X0/0*\r\n] 2006.173.19:32:13.31#ibcon#read 3, iclass 16, count 2 2006.173.19:32:13.31#ibcon#about to read 4, iclass 16, count 2 2006.173.19:32:13.31#ibcon#read 4, iclass 16, count 2 2006.173.19:32:13.31#ibcon#about to read 5, iclass 16, count 2 2006.173.19:32:13.31#ibcon#read 5, iclass 16, count 2 2006.173.19:32:13.31#ibcon#about to read 6, iclass 16, count 2 2006.173.19:32:13.31#ibcon#read 6, iclass 16, count 2 2006.173.19:32:13.31#ibcon#end of sib2, iclass 16, count 2 2006.173.19:32:13.31#ibcon#*after write, iclass 16, count 2 2006.173.19:32:13.31#ibcon#*before return 0, iclass 16, count 2 2006.173.19:32:13.31#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.19:32:13.31#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.19:32:13.31#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.19:32:13.31#ibcon#ireg 7 cls_cnt 0 2006.173.19:32:13.31#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.19:32:13.43#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.19:32:13.43#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.19:32:13.43#ibcon#enter wrdev, iclass 16, count 0 2006.173.19:32:13.43#ibcon#first serial, iclass 16, count 0 2006.173.19:32:13.43#ibcon#enter sib2, iclass 16, count 0 2006.173.19:32:13.43#ibcon#flushed, iclass 16, count 0 2006.173.19:32:13.43#ibcon#about to write, iclass 16, count 0 2006.173.19:32:13.43#ibcon#wrote, iclass 16, count 0 2006.173.19:32:13.43#ibcon#about to read 3, iclass 16, count 0 2006.173.19:32:13.45#ibcon#read 3, iclass 16, count 0 2006.173.19:32:13.45#ibcon#about to read 4, iclass 16, count 0 2006.173.19:32:13.45#ibcon#read 4, iclass 16, count 0 2006.173.19:32:13.45#ibcon#about to read 5, iclass 16, count 0 2006.173.19:32:13.45#ibcon#read 5, iclass 16, count 0 2006.173.19:32:13.45#ibcon#about to read 6, iclass 16, count 0 2006.173.19:32:13.45#ibcon#read 6, iclass 16, count 0 2006.173.19:32:13.45#ibcon#end of sib2, iclass 16, count 0 2006.173.19:32:13.45#ibcon#*mode == 0, iclass 16, count 0 2006.173.19:32:13.45#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.19:32:13.45#ibcon#[27=USB\r\n] 2006.173.19:32:13.45#ibcon#*before write, iclass 16, count 0 2006.173.19:32:13.45#ibcon#enter sib2, iclass 16, count 0 2006.173.19:32:13.45#ibcon#flushed, iclass 16, count 0 2006.173.19:32:13.45#ibcon#about to write, iclass 16, count 0 2006.173.19:32:13.45#ibcon#wrote, iclass 16, count 0 2006.173.19:32:13.45#ibcon#about to read 3, iclass 16, count 0 2006.173.19:32:13.48#ibcon#read 3, iclass 16, count 0 2006.173.19:32:13.48#ibcon#about to read 4, iclass 16, count 0 2006.173.19:32:13.48#ibcon#read 4, iclass 16, count 0 2006.173.19:32:13.48#ibcon#about to read 5, iclass 16, count 0 2006.173.19:32:13.48#ibcon#read 5, iclass 16, count 0 2006.173.19:32:13.48#ibcon#about to read 6, iclass 16, count 0 2006.173.19:32:13.48#ibcon#read 6, iclass 16, count 0 2006.173.19:32:13.48#ibcon#end of sib2, iclass 16, count 0 2006.173.19:32:13.48#ibcon#*after write, iclass 16, count 0 2006.173.19:32:13.48#ibcon#*before return 0, iclass 16, count 0 2006.173.19:32:13.48#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.19:32:13.48#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.19:32:13.48#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.19:32:13.48#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.19:32:13.48$vck44/vblo=6,719.99 2006.173.19:32:13.48#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.19:32:13.48#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.19:32:13.48#ibcon#ireg 17 cls_cnt 0 2006.173.19:32:13.48#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.19:32:13.48#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.19:32:13.48#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.19:32:13.48#ibcon#enter wrdev, iclass 21, count 0 2006.173.19:32:13.48#ibcon#first serial, iclass 21, count 0 2006.173.19:32:13.48#ibcon#enter sib2, iclass 21, count 0 2006.173.19:32:13.48#ibcon#flushed, iclass 21, count 0 2006.173.19:32:13.48#ibcon#about to write, iclass 21, count 0 2006.173.19:32:13.48#ibcon#wrote, iclass 21, count 0 2006.173.19:32:13.48#ibcon#about to read 3, iclass 21, count 0 2006.173.19:32:13.50#ibcon#read 3, iclass 21, count 0 2006.173.19:32:13.50#ibcon#about to read 4, iclass 21, count 0 2006.173.19:32:13.50#ibcon#read 4, iclass 21, count 0 2006.173.19:32:13.50#ibcon#about to read 5, iclass 21, count 0 2006.173.19:32:13.50#ibcon#read 5, iclass 21, count 0 2006.173.19:32:13.50#ibcon#about to read 6, iclass 21, count 0 2006.173.19:32:13.50#ibcon#read 6, iclass 21, count 0 2006.173.19:32:13.50#ibcon#end of sib2, iclass 21, count 0 2006.173.19:32:13.50#ibcon#*mode == 0, iclass 21, count 0 2006.173.19:32:13.50#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.19:32:13.50#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.19:32:13.50#ibcon#*before write, iclass 21, count 0 2006.173.19:32:13.50#ibcon#enter sib2, iclass 21, count 0 2006.173.19:32:13.50#ibcon#flushed, iclass 21, count 0 2006.173.19:32:13.50#ibcon#about to write, iclass 21, count 0 2006.173.19:32:13.50#ibcon#wrote, iclass 21, count 0 2006.173.19:32:13.50#ibcon#about to read 3, iclass 21, count 0 2006.173.19:32:13.54#ibcon#read 3, iclass 21, count 0 2006.173.19:32:13.54#ibcon#about to read 4, iclass 21, count 0 2006.173.19:32:13.54#ibcon#read 4, iclass 21, count 0 2006.173.19:32:13.54#ibcon#about to read 5, iclass 21, count 0 2006.173.19:32:13.54#ibcon#read 5, iclass 21, count 0 2006.173.19:32:13.54#ibcon#about to read 6, iclass 21, count 0 2006.173.19:32:13.54#ibcon#read 6, iclass 21, count 0 2006.173.19:32:13.54#ibcon#end of sib2, iclass 21, count 0 2006.173.19:32:13.54#ibcon#*after write, iclass 21, count 0 2006.173.19:32:13.54#ibcon#*before return 0, iclass 21, count 0 2006.173.19:32:13.54#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.19:32:13.54#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.19:32:13.54#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.19:32:13.54#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.19:32:13.54$vck44/vb=6,4 2006.173.19:32:13.54#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.19:32:13.54#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.19:32:13.54#ibcon#ireg 11 cls_cnt 2 2006.173.19:32:13.54#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.19:32:13.60#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.19:32:13.60#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.19:32:13.60#ibcon#enter wrdev, iclass 23, count 2 2006.173.19:32:13.60#ibcon#first serial, iclass 23, count 2 2006.173.19:32:13.60#ibcon#enter sib2, iclass 23, count 2 2006.173.19:32:13.60#ibcon#flushed, iclass 23, count 2 2006.173.19:32:13.60#ibcon#about to write, iclass 23, count 2 2006.173.19:32:13.60#ibcon#wrote, iclass 23, count 2 2006.173.19:32:13.60#ibcon#about to read 3, iclass 23, count 2 2006.173.19:32:13.62#ibcon#read 3, iclass 23, count 2 2006.173.19:32:13.62#ibcon#about to read 4, iclass 23, count 2 2006.173.19:32:13.62#ibcon#read 4, iclass 23, count 2 2006.173.19:32:13.62#ibcon#about to read 5, iclass 23, count 2 2006.173.19:32:13.62#ibcon#read 5, iclass 23, count 2 2006.173.19:32:13.62#ibcon#about to read 6, iclass 23, count 2 2006.173.19:32:13.62#ibcon#read 6, iclass 23, count 2 2006.173.19:32:13.62#ibcon#end of sib2, iclass 23, count 2 2006.173.19:32:13.62#ibcon#*mode == 0, iclass 23, count 2 2006.173.19:32:13.62#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.19:32:13.62#ibcon#[27=AT06-04\r\n] 2006.173.19:32:13.62#ibcon#*before write, iclass 23, count 2 2006.173.19:32:13.62#ibcon#enter sib2, iclass 23, count 2 2006.173.19:32:13.62#ibcon#flushed, iclass 23, count 2 2006.173.19:32:13.62#ibcon#about to write, iclass 23, count 2 2006.173.19:32:13.62#ibcon#wrote, iclass 23, count 2 2006.173.19:32:13.62#ibcon#about to read 3, iclass 23, count 2 2006.173.19:32:13.65#ibcon#read 3, iclass 23, count 2 2006.173.19:32:13.65#ibcon#about to read 4, iclass 23, count 2 2006.173.19:32:13.65#ibcon#read 4, iclass 23, count 2 2006.173.19:32:13.65#ibcon#about to read 5, iclass 23, count 2 2006.173.19:32:13.65#ibcon#read 5, iclass 23, count 2 2006.173.19:32:13.65#ibcon#about to read 6, iclass 23, count 2 2006.173.19:32:13.65#ibcon#read 6, iclass 23, count 2 2006.173.19:32:13.65#ibcon#end of sib2, iclass 23, count 2 2006.173.19:32:13.65#ibcon#*after write, iclass 23, count 2 2006.173.19:32:13.65#ibcon#*before return 0, iclass 23, count 2 2006.173.19:32:13.65#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.19:32:13.65#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.19:32:13.65#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.19:32:13.65#ibcon#ireg 7 cls_cnt 0 2006.173.19:32:13.65#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.19:32:13.77#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.19:32:13.77#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.19:32:13.77#ibcon#enter wrdev, iclass 23, count 0 2006.173.19:32:13.77#ibcon#first serial, iclass 23, count 0 2006.173.19:32:13.77#ibcon#enter sib2, iclass 23, count 0 2006.173.19:32:13.77#ibcon#flushed, iclass 23, count 0 2006.173.19:32:13.77#ibcon#about to write, iclass 23, count 0 2006.173.19:32:13.77#ibcon#wrote, iclass 23, count 0 2006.173.19:32:13.77#ibcon#about to read 3, iclass 23, count 0 2006.173.19:32:13.79#ibcon#read 3, iclass 23, count 0 2006.173.19:32:13.79#ibcon#about to read 4, iclass 23, count 0 2006.173.19:32:13.79#ibcon#read 4, iclass 23, count 0 2006.173.19:32:13.79#ibcon#about to read 5, iclass 23, count 0 2006.173.19:32:13.79#ibcon#read 5, iclass 23, count 0 2006.173.19:32:13.79#ibcon#about to read 6, iclass 23, count 0 2006.173.19:32:13.79#ibcon#read 6, iclass 23, count 0 2006.173.19:32:13.79#ibcon#end of sib2, iclass 23, count 0 2006.173.19:32:13.79#ibcon#*mode == 0, iclass 23, count 0 2006.173.19:32:13.79#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.19:32:13.79#ibcon#[27=USB\r\n] 2006.173.19:32:13.79#ibcon#*before write, iclass 23, count 0 2006.173.19:32:13.79#ibcon#enter sib2, iclass 23, count 0 2006.173.19:32:13.79#ibcon#flushed, iclass 23, count 0 2006.173.19:32:13.79#ibcon#about to write, iclass 23, count 0 2006.173.19:32:13.79#ibcon#wrote, iclass 23, count 0 2006.173.19:32:13.79#ibcon#about to read 3, iclass 23, count 0 2006.173.19:32:13.82#ibcon#read 3, iclass 23, count 0 2006.173.19:32:13.82#ibcon#about to read 4, iclass 23, count 0 2006.173.19:32:13.82#ibcon#read 4, iclass 23, count 0 2006.173.19:32:13.82#ibcon#about to read 5, iclass 23, count 0 2006.173.19:32:13.82#ibcon#read 5, iclass 23, count 0 2006.173.19:32:13.82#ibcon#about to read 6, iclass 23, count 0 2006.173.19:32:13.82#ibcon#read 6, iclass 23, count 0 2006.173.19:32:13.82#ibcon#end of sib2, iclass 23, count 0 2006.173.19:32:13.82#ibcon#*after write, iclass 23, count 0 2006.173.19:32:13.82#ibcon#*before return 0, iclass 23, count 0 2006.173.19:32:13.82#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.19:32:13.82#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.19:32:13.82#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.19:32:13.82#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.19:32:13.82$vck44/vblo=7,734.99 2006.173.19:32:13.82#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.19:32:13.82#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.19:32:13.82#ibcon#ireg 17 cls_cnt 0 2006.173.19:32:13.82#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.19:32:13.82#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.19:32:13.82#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.19:32:13.82#ibcon#enter wrdev, iclass 25, count 0 2006.173.19:32:13.82#ibcon#first serial, iclass 25, count 0 2006.173.19:32:13.82#ibcon#enter sib2, iclass 25, count 0 2006.173.19:32:13.82#ibcon#flushed, iclass 25, count 0 2006.173.19:32:13.82#ibcon#about to write, iclass 25, count 0 2006.173.19:32:13.82#ibcon#wrote, iclass 25, count 0 2006.173.19:32:13.82#ibcon#about to read 3, iclass 25, count 0 2006.173.19:32:13.84#ibcon#read 3, iclass 25, count 0 2006.173.19:32:13.84#ibcon#about to read 4, iclass 25, count 0 2006.173.19:32:13.84#ibcon#read 4, iclass 25, count 0 2006.173.19:32:13.84#ibcon#about to read 5, iclass 25, count 0 2006.173.19:32:13.84#ibcon#read 5, iclass 25, count 0 2006.173.19:32:13.84#ibcon#about to read 6, iclass 25, count 0 2006.173.19:32:13.84#ibcon#read 6, iclass 25, count 0 2006.173.19:32:13.84#ibcon#end of sib2, iclass 25, count 0 2006.173.19:32:13.84#ibcon#*mode == 0, iclass 25, count 0 2006.173.19:32:13.84#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.19:32:13.84#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.19:32:13.84#ibcon#*before write, iclass 25, count 0 2006.173.19:32:13.84#ibcon#enter sib2, iclass 25, count 0 2006.173.19:32:13.84#ibcon#flushed, iclass 25, count 0 2006.173.19:32:13.84#ibcon#about to write, iclass 25, count 0 2006.173.19:32:13.84#ibcon#wrote, iclass 25, count 0 2006.173.19:32:13.84#ibcon#about to read 3, iclass 25, count 0 2006.173.19:32:13.88#ibcon#read 3, iclass 25, count 0 2006.173.19:32:13.88#ibcon#about to read 4, iclass 25, count 0 2006.173.19:32:13.88#ibcon#read 4, iclass 25, count 0 2006.173.19:32:13.88#ibcon#about to read 5, iclass 25, count 0 2006.173.19:32:13.88#ibcon#read 5, iclass 25, count 0 2006.173.19:32:13.88#ibcon#about to read 6, iclass 25, count 0 2006.173.19:32:13.88#ibcon#read 6, iclass 25, count 0 2006.173.19:32:13.88#ibcon#end of sib2, iclass 25, count 0 2006.173.19:32:13.88#ibcon#*after write, iclass 25, count 0 2006.173.19:32:13.88#ibcon#*before return 0, iclass 25, count 0 2006.173.19:32:13.88#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.19:32:13.88#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.19:32:13.88#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.19:32:13.88#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.19:32:13.88$vck44/vb=7,4 2006.173.19:32:13.88#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.19:32:13.88#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.19:32:13.88#ibcon#ireg 11 cls_cnt 2 2006.173.19:32:13.88#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.19:32:13.94#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.19:32:13.94#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.19:32:13.94#ibcon#enter wrdev, iclass 27, count 2 2006.173.19:32:13.94#ibcon#first serial, iclass 27, count 2 2006.173.19:32:13.94#ibcon#enter sib2, iclass 27, count 2 2006.173.19:32:13.94#ibcon#flushed, iclass 27, count 2 2006.173.19:32:13.94#ibcon#about to write, iclass 27, count 2 2006.173.19:32:13.94#ibcon#wrote, iclass 27, count 2 2006.173.19:32:13.94#ibcon#about to read 3, iclass 27, count 2 2006.173.19:32:13.96#ibcon#read 3, iclass 27, count 2 2006.173.19:32:13.96#ibcon#about to read 4, iclass 27, count 2 2006.173.19:32:13.96#ibcon#read 4, iclass 27, count 2 2006.173.19:32:13.96#ibcon#about to read 5, iclass 27, count 2 2006.173.19:32:13.96#ibcon#read 5, iclass 27, count 2 2006.173.19:32:13.96#ibcon#about to read 6, iclass 27, count 2 2006.173.19:32:13.96#ibcon#read 6, iclass 27, count 2 2006.173.19:32:13.96#ibcon#end of sib2, iclass 27, count 2 2006.173.19:32:13.96#ibcon#*mode == 0, iclass 27, count 2 2006.173.19:32:13.96#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.19:32:13.96#ibcon#[27=AT07-04\r\n] 2006.173.19:32:13.96#ibcon#*before write, iclass 27, count 2 2006.173.19:32:13.96#ibcon#enter sib2, iclass 27, count 2 2006.173.19:32:13.96#ibcon#flushed, iclass 27, count 2 2006.173.19:32:13.96#ibcon#about to write, iclass 27, count 2 2006.173.19:32:13.96#ibcon#wrote, iclass 27, count 2 2006.173.19:32:13.96#ibcon#about to read 3, iclass 27, count 2 2006.173.19:32:13.99#ibcon#read 3, iclass 27, count 2 2006.173.19:32:13.99#ibcon#about to read 4, iclass 27, count 2 2006.173.19:32:13.99#ibcon#read 4, iclass 27, count 2 2006.173.19:32:13.99#ibcon#about to read 5, iclass 27, count 2 2006.173.19:32:13.99#ibcon#read 5, iclass 27, count 2 2006.173.19:32:13.99#ibcon#about to read 6, iclass 27, count 2 2006.173.19:32:13.99#ibcon#read 6, iclass 27, count 2 2006.173.19:32:13.99#ibcon#end of sib2, iclass 27, count 2 2006.173.19:32:13.99#ibcon#*after write, iclass 27, count 2 2006.173.19:32:13.99#ibcon#*before return 0, iclass 27, count 2 2006.173.19:32:13.99#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.19:32:13.99#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.19:32:13.99#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.19:32:13.99#ibcon#ireg 7 cls_cnt 0 2006.173.19:32:13.99#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.19:32:14.11#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.19:32:14.11#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.19:32:14.11#ibcon#enter wrdev, iclass 27, count 0 2006.173.19:32:14.11#ibcon#first serial, iclass 27, count 0 2006.173.19:32:14.11#ibcon#enter sib2, iclass 27, count 0 2006.173.19:32:14.11#ibcon#flushed, iclass 27, count 0 2006.173.19:32:14.11#ibcon#about to write, iclass 27, count 0 2006.173.19:32:14.11#ibcon#wrote, iclass 27, count 0 2006.173.19:32:14.11#ibcon#about to read 3, iclass 27, count 0 2006.173.19:32:14.13#ibcon#read 3, iclass 27, count 0 2006.173.19:32:14.13#ibcon#about to read 4, iclass 27, count 0 2006.173.19:32:14.13#ibcon#read 4, iclass 27, count 0 2006.173.19:32:14.13#ibcon#about to read 5, iclass 27, count 0 2006.173.19:32:14.13#ibcon#read 5, iclass 27, count 0 2006.173.19:32:14.13#ibcon#about to read 6, iclass 27, count 0 2006.173.19:32:14.13#ibcon#read 6, iclass 27, count 0 2006.173.19:32:14.13#ibcon#end of sib2, iclass 27, count 0 2006.173.19:32:14.13#ibcon#*mode == 0, iclass 27, count 0 2006.173.19:32:14.13#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.19:32:14.13#ibcon#[27=USB\r\n] 2006.173.19:32:14.13#ibcon#*before write, iclass 27, count 0 2006.173.19:32:14.13#ibcon#enter sib2, iclass 27, count 0 2006.173.19:32:14.13#ibcon#flushed, iclass 27, count 0 2006.173.19:32:14.13#ibcon#about to write, iclass 27, count 0 2006.173.19:32:14.13#ibcon#wrote, iclass 27, count 0 2006.173.19:32:14.13#ibcon#about to read 3, iclass 27, count 0 2006.173.19:32:14.16#ibcon#read 3, iclass 27, count 0 2006.173.19:32:14.16#ibcon#about to read 4, iclass 27, count 0 2006.173.19:32:14.16#ibcon#read 4, iclass 27, count 0 2006.173.19:32:14.16#ibcon#about to read 5, iclass 27, count 0 2006.173.19:32:14.16#ibcon#read 5, iclass 27, count 0 2006.173.19:32:14.16#ibcon#about to read 6, iclass 27, count 0 2006.173.19:32:14.16#ibcon#read 6, iclass 27, count 0 2006.173.19:32:14.16#ibcon#end of sib2, iclass 27, count 0 2006.173.19:32:14.16#ibcon#*after write, iclass 27, count 0 2006.173.19:32:14.16#ibcon#*before return 0, iclass 27, count 0 2006.173.19:32:14.16#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.19:32:14.16#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.19:32:14.16#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.19:32:14.16#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.19:32:14.16$vck44/vblo=8,744.99 2006.173.19:32:14.16#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.19:32:14.16#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.19:32:14.16#ibcon#ireg 17 cls_cnt 0 2006.173.19:32:14.16#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.19:32:14.16#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.19:32:14.16#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.19:32:14.16#ibcon#enter wrdev, iclass 29, count 0 2006.173.19:32:14.16#ibcon#first serial, iclass 29, count 0 2006.173.19:32:14.16#ibcon#enter sib2, iclass 29, count 0 2006.173.19:32:14.16#ibcon#flushed, iclass 29, count 0 2006.173.19:32:14.16#ibcon#about to write, iclass 29, count 0 2006.173.19:32:14.16#ibcon#wrote, iclass 29, count 0 2006.173.19:32:14.16#ibcon#about to read 3, iclass 29, count 0 2006.173.19:32:14.18#ibcon#read 3, iclass 29, count 0 2006.173.19:32:14.18#ibcon#about to read 4, iclass 29, count 0 2006.173.19:32:14.18#ibcon#read 4, iclass 29, count 0 2006.173.19:32:14.18#ibcon#about to read 5, iclass 29, count 0 2006.173.19:32:14.18#ibcon#read 5, iclass 29, count 0 2006.173.19:32:14.18#ibcon#about to read 6, iclass 29, count 0 2006.173.19:32:14.18#ibcon#read 6, iclass 29, count 0 2006.173.19:32:14.18#ibcon#end of sib2, iclass 29, count 0 2006.173.19:32:14.18#ibcon#*mode == 0, iclass 29, count 0 2006.173.19:32:14.18#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.19:32:14.18#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.19:32:14.18#ibcon#*before write, iclass 29, count 0 2006.173.19:32:14.18#ibcon#enter sib2, iclass 29, count 0 2006.173.19:32:14.18#ibcon#flushed, iclass 29, count 0 2006.173.19:32:14.18#ibcon#about to write, iclass 29, count 0 2006.173.19:32:14.18#ibcon#wrote, iclass 29, count 0 2006.173.19:32:14.18#ibcon#about to read 3, iclass 29, count 0 2006.173.19:32:14.22#ibcon#read 3, iclass 29, count 0 2006.173.19:32:14.22#ibcon#about to read 4, iclass 29, count 0 2006.173.19:32:14.22#ibcon#read 4, iclass 29, count 0 2006.173.19:32:14.22#ibcon#about to read 5, iclass 29, count 0 2006.173.19:32:14.22#ibcon#read 5, iclass 29, count 0 2006.173.19:32:14.22#ibcon#about to read 6, iclass 29, count 0 2006.173.19:32:14.22#ibcon#read 6, iclass 29, count 0 2006.173.19:32:14.22#ibcon#end of sib2, iclass 29, count 0 2006.173.19:32:14.22#ibcon#*after write, iclass 29, count 0 2006.173.19:32:14.22#ibcon#*before return 0, iclass 29, count 0 2006.173.19:32:14.22#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.19:32:14.22#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.19:32:14.22#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.19:32:14.22#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.19:32:14.22$vck44/vb=8,4 2006.173.19:32:14.22#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.19:32:14.22#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.19:32:14.22#ibcon#ireg 11 cls_cnt 2 2006.173.19:32:14.22#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.19:32:14.28#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.19:32:14.28#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.19:32:14.28#ibcon#enter wrdev, iclass 31, count 2 2006.173.19:32:14.28#ibcon#first serial, iclass 31, count 2 2006.173.19:32:14.28#ibcon#enter sib2, iclass 31, count 2 2006.173.19:32:14.28#ibcon#flushed, iclass 31, count 2 2006.173.19:32:14.28#ibcon#about to write, iclass 31, count 2 2006.173.19:32:14.28#ibcon#wrote, iclass 31, count 2 2006.173.19:32:14.28#ibcon#about to read 3, iclass 31, count 2 2006.173.19:32:14.30#ibcon#read 3, iclass 31, count 2 2006.173.19:32:14.30#ibcon#about to read 4, iclass 31, count 2 2006.173.19:32:14.30#ibcon#read 4, iclass 31, count 2 2006.173.19:32:14.30#ibcon#about to read 5, iclass 31, count 2 2006.173.19:32:14.30#ibcon#read 5, iclass 31, count 2 2006.173.19:32:14.30#ibcon#about to read 6, iclass 31, count 2 2006.173.19:32:14.30#ibcon#read 6, iclass 31, count 2 2006.173.19:32:14.30#ibcon#end of sib2, iclass 31, count 2 2006.173.19:32:14.30#ibcon#*mode == 0, iclass 31, count 2 2006.173.19:32:14.30#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.19:32:14.30#ibcon#[27=AT08-04\r\n] 2006.173.19:32:14.30#ibcon#*before write, iclass 31, count 2 2006.173.19:32:14.30#ibcon#enter sib2, iclass 31, count 2 2006.173.19:32:14.30#ibcon#flushed, iclass 31, count 2 2006.173.19:32:14.30#ibcon#about to write, iclass 31, count 2 2006.173.19:32:14.30#ibcon#wrote, iclass 31, count 2 2006.173.19:32:14.30#ibcon#about to read 3, iclass 31, count 2 2006.173.19:32:14.33#ibcon#read 3, iclass 31, count 2 2006.173.19:32:14.33#ibcon#about to read 4, iclass 31, count 2 2006.173.19:32:14.33#ibcon#read 4, iclass 31, count 2 2006.173.19:32:14.33#ibcon#about to read 5, iclass 31, count 2 2006.173.19:32:14.33#ibcon#read 5, iclass 31, count 2 2006.173.19:32:14.33#ibcon#about to read 6, iclass 31, count 2 2006.173.19:32:14.33#ibcon#read 6, iclass 31, count 2 2006.173.19:32:14.33#ibcon#end of sib2, iclass 31, count 2 2006.173.19:32:14.33#ibcon#*after write, iclass 31, count 2 2006.173.19:32:14.33#ibcon#*before return 0, iclass 31, count 2 2006.173.19:32:14.33#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.19:32:14.33#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.19:32:14.33#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.19:32:14.33#ibcon#ireg 7 cls_cnt 0 2006.173.19:32:14.33#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.19:32:14.45#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.19:32:14.45#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.19:32:14.45#ibcon#enter wrdev, iclass 31, count 0 2006.173.19:32:14.45#ibcon#first serial, iclass 31, count 0 2006.173.19:32:14.45#ibcon#enter sib2, iclass 31, count 0 2006.173.19:32:14.45#ibcon#flushed, iclass 31, count 0 2006.173.19:32:14.45#ibcon#about to write, iclass 31, count 0 2006.173.19:32:14.45#ibcon#wrote, iclass 31, count 0 2006.173.19:32:14.45#ibcon#about to read 3, iclass 31, count 0 2006.173.19:32:14.47#ibcon#read 3, iclass 31, count 0 2006.173.19:32:14.47#ibcon#about to read 4, iclass 31, count 0 2006.173.19:32:14.47#ibcon#read 4, iclass 31, count 0 2006.173.19:32:14.47#ibcon#about to read 5, iclass 31, count 0 2006.173.19:32:14.47#ibcon#read 5, iclass 31, count 0 2006.173.19:32:14.47#ibcon#about to read 6, iclass 31, count 0 2006.173.19:32:14.47#ibcon#read 6, iclass 31, count 0 2006.173.19:32:14.47#ibcon#end of sib2, iclass 31, count 0 2006.173.19:32:14.47#ibcon#*mode == 0, iclass 31, count 0 2006.173.19:32:14.47#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.19:32:14.47#ibcon#[27=USB\r\n] 2006.173.19:32:14.47#ibcon#*before write, iclass 31, count 0 2006.173.19:32:14.47#ibcon#enter sib2, iclass 31, count 0 2006.173.19:32:14.47#ibcon#flushed, iclass 31, count 0 2006.173.19:32:14.47#ibcon#about to write, iclass 31, count 0 2006.173.19:32:14.47#ibcon#wrote, iclass 31, count 0 2006.173.19:32:14.47#ibcon#about to read 3, iclass 31, count 0 2006.173.19:32:14.50#ibcon#read 3, iclass 31, count 0 2006.173.19:32:14.50#ibcon#about to read 4, iclass 31, count 0 2006.173.19:32:14.50#ibcon#read 4, iclass 31, count 0 2006.173.19:32:14.50#ibcon#about to read 5, iclass 31, count 0 2006.173.19:32:14.50#ibcon#read 5, iclass 31, count 0 2006.173.19:32:14.50#ibcon#about to read 6, iclass 31, count 0 2006.173.19:32:14.50#ibcon#read 6, iclass 31, count 0 2006.173.19:32:14.50#ibcon#end of sib2, iclass 31, count 0 2006.173.19:32:14.50#ibcon#*after write, iclass 31, count 0 2006.173.19:32:14.50#ibcon#*before return 0, iclass 31, count 0 2006.173.19:32:14.50#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.19:32:14.50#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.19:32:14.50#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.19:32:14.50#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.19:32:14.50$vck44/vabw=wide 2006.173.19:32:14.50#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.19:32:14.50#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.19:32:14.50#ibcon#ireg 8 cls_cnt 0 2006.173.19:32:14.50#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.19:32:14.50#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.19:32:14.50#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.19:32:14.50#ibcon#enter wrdev, iclass 33, count 0 2006.173.19:32:14.50#ibcon#first serial, iclass 33, count 0 2006.173.19:32:14.50#ibcon#enter sib2, iclass 33, count 0 2006.173.19:32:14.50#ibcon#flushed, iclass 33, count 0 2006.173.19:32:14.50#ibcon#about to write, iclass 33, count 0 2006.173.19:32:14.50#ibcon#wrote, iclass 33, count 0 2006.173.19:32:14.50#ibcon#about to read 3, iclass 33, count 0 2006.173.19:32:14.52#ibcon#read 3, iclass 33, count 0 2006.173.19:32:14.52#ibcon#about to read 4, iclass 33, count 0 2006.173.19:32:14.52#ibcon#read 4, iclass 33, count 0 2006.173.19:32:14.52#ibcon#about to read 5, iclass 33, count 0 2006.173.19:32:14.52#ibcon#read 5, iclass 33, count 0 2006.173.19:32:14.52#ibcon#about to read 6, iclass 33, count 0 2006.173.19:32:14.52#ibcon#read 6, iclass 33, count 0 2006.173.19:32:14.52#ibcon#end of sib2, iclass 33, count 0 2006.173.19:32:14.52#ibcon#*mode == 0, iclass 33, count 0 2006.173.19:32:14.52#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.19:32:14.52#ibcon#[25=BW32\r\n] 2006.173.19:32:14.52#ibcon#*before write, iclass 33, count 0 2006.173.19:32:14.52#ibcon#enter sib2, iclass 33, count 0 2006.173.19:32:14.52#ibcon#flushed, iclass 33, count 0 2006.173.19:32:14.52#ibcon#about to write, iclass 33, count 0 2006.173.19:32:14.52#ibcon#wrote, iclass 33, count 0 2006.173.19:32:14.52#ibcon#about to read 3, iclass 33, count 0 2006.173.19:32:14.55#ibcon#read 3, iclass 33, count 0 2006.173.19:32:14.55#ibcon#about to read 4, iclass 33, count 0 2006.173.19:32:14.55#ibcon#read 4, iclass 33, count 0 2006.173.19:32:14.55#ibcon#about to read 5, iclass 33, count 0 2006.173.19:32:14.55#ibcon#read 5, iclass 33, count 0 2006.173.19:32:14.55#ibcon#about to read 6, iclass 33, count 0 2006.173.19:32:14.55#ibcon#read 6, iclass 33, count 0 2006.173.19:32:14.55#ibcon#end of sib2, iclass 33, count 0 2006.173.19:32:14.55#ibcon#*after write, iclass 33, count 0 2006.173.19:32:14.55#ibcon#*before return 0, iclass 33, count 0 2006.173.19:32:14.55#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.19:32:14.55#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.19:32:14.55#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.19:32:14.55#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.19:32:14.55$vck44/vbbw=wide 2006.173.19:32:14.55#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.19:32:14.55#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.19:32:14.55#ibcon#ireg 8 cls_cnt 0 2006.173.19:32:14.55#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.19:32:14.62#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.19:32:14.62#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.19:32:14.62#ibcon#enter wrdev, iclass 35, count 0 2006.173.19:32:14.62#ibcon#first serial, iclass 35, count 0 2006.173.19:32:14.62#ibcon#enter sib2, iclass 35, count 0 2006.173.19:32:14.62#ibcon#flushed, iclass 35, count 0 2006.173.19:32:14.62#ibcon#about to write, iclass 35, count 0 2006.173.19:32:14.62#ibcon#wrote, iclass 35, count 0 2006.173.19:32:14.62#ibcon#about to read 3, iclass 35, count 0 2006.173.19:32:14.64#ibcon#read 3, iclass 35, count 0 2006.173.19:32:14.64#ibcon#about to read 4, iclass 35, count 0 2006.173.19:32:14.64#ibcon#read 4, iclass 35, count 0 2006.173.19:32:14.64#ibcon#about to read 5, iclass 35, count 0 2006.173.19:32:14.64#ibcon#read 5, iclass 35, count 0 2006.173.19:32:14.64#ibcon#about to read 6, iclass 35, count 0 2006.173.19:32:14.64#ibcon#read 6, iclass 35, count 0 2006.173.19:32:14.64#ibcon#end of sib2, iclass 35, count 0 2006.173.19:32:14.64#ibcon#*mode == 0, iclass 35, count 0 2006.173.19:32:14.64#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.19:32:14.64#ibcon#[27=BW32\r\n] 2006.173.19:32:14.64#ibcon#*before write, iclass 35, count 0 2006.173.19:32:14.64#ibcon#enter sib2, iclass 35, count 0 2006.173.19:32:14.64#ibcon#flushed, iclass 35, count 0 2006.173.19:32:14.64#ibcon#about to write, iclass 35, count 0 2006.173.19:32:14.64#ibcon#wrote, iclass 35, count 0 2006.173.19:32:14.64#ibcon#about to read 3, iclass 35, count 0 2006.173.19:32:14.67#ibcon#read 3, iclass 35, count 0 2006.173.19:32:14.67#ibcon#about to read 4, iclass 35, count 0 2006.173.19:32:14.67#ibcon#read 4, iclass 35, count 0 2006.173.19:32:14.67#ibcon#about to read 5, iclass 35, count 0 2006.173.19:32:14.67#ibcon#read 5, iclass 35, count 0 2006.173.19:32:14.67#ibcon#about to read 6, iclass 35, count 0 2006.173.19:32:14.67#ibcon#read 6, iclass 35, count 0 2006.173.19:32:14.67#ibcon#end of sib2, iclass 35, count 0 2006.173.19:32:14.67#ibcon#*after write, iclass 35, count 0 2006.173.19:32:14.67#ibcon#*before return 0, iclass 35, count 0 2006.173.19:32:14.67#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.19:32:14.67#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.19:32:14.67#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.19:32:14.67#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.19:32:14.67$setupk4/ifdk4 2006.173.19:32:14.67$ifdk4/lo= 2006.173.19:32:14.67$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.19:32:14.67$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.19:32:14.67$ifdk4/patch= 2006.173.19:32:14.67$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.19:32:14.67$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.19:32:14.67$setupk4/!*+20s 2006.173.19:32:23.39#abcon#<5=/00 0.2 0.6 19.391001002.5\r\n> 2006.173.19:32:23.41#abcon#{5=INTERFACE CLEAR} 2006.173.19:32:23.47#abcon#[5=S1D000X0/0*\r\n] 2006.173.19:32:29.17$setupk4/"tpicd 2006.173.19:32:29.17$setupk4/echo=off 2006.173.19:32:29.17$setupk4/xlog=off 2006.173.19:32:29.17:!2006.173.19:32:44 2006.173.19:32:34.14#trakl#Source acquired 2006.173.19:32:34.14#flagr#flagr/antenna,acquired 2006.173.19:32:44.00:preob 2006.173.19:32:44.14/onsource/TRACKING 2006.173.19:32:44.14:!2006.173.19:32:54 2006.173.19:32:54.00:"tape 2006.173.19:32:54.00:"st=record 2006.173.19:32:54.00:data_valid=on 2006.173.19:32:54.00:midob 2006.173.19:32:55.14/onsource/TRACKING 2006.173.19:32:55.14/wx/19.38,1002.5,100 2006.173.19:32:55.24/cable/+6.5164E-03 2006.173.19:32:56.33/va/01,07,usb,yes,35,37 2006.173.19:32:56.33/va/02,06,usb,yes,34,35 2006.173.19:32:56.33/va/03,05,usb,yes,44,46 2006.173.19:32:56.33/va/04,06,usb,yes,35,37 2006.173.19:32:56.33/va/05,04,usb,yes,28,28 2006.173.19:32:56.33/va/06,03,usb,yes,39,39 2006.173.19:32:56.33/va/07,04,usb,yes,31,32 2006.173.19:32:56.33/va/08,04,usb,yes,27,32 2006.173.19:32:56.56/valo/01,524.99,yes,locked 2006.173.19:32:56.56/valo/02,534.99,yes,locked 2006.173.19:32:56.56/valo/03,564.99,yes,locked 2006.173.19:32:56.56/valo/04,624.99,yes,locked 2006.173.19:32:56.56/valo/05,734.99,yes,locked 2006.173.19:32:56.56/valo/06,814.99,yes,locked 2006.173.19:32:56.56/valo/07,864.99,yes,locked 2006.173.19:32:56.56/valo/08,884.99,yes,locked 2006.173.19:32:57.65/vb/01,04,usb,yes,29,27 2006.173.19:32:57.65/vb/02,04,usb,yes,31,31 2006.173.19:32:57.65/vb/03,04,usb,yes,28,31 2006.173.19:32:57.65/vb/04,04,usb,yes,32,31 2006.173.19:32:57.65/vb/05,04,usb,yes,25,27 2006.173.19:32:57.65/vb/06,04,usb,yes,29,26 2006.173.19:32:57.65/vb/07,04,usb,yes,29,29 2006.173.19:32:57.65/vb/08,04,usb,yes,27,30 2006.173.19:32:57.89/vblo/01,629.99,yes,locked 2006.173.19:32:57.89/vblo/02,634.99,yes,locked 2006.173.19:32:57.89/vblo/03,649.99,yes,locked 2006.173.19:32:57.89/vblo/04,679.99,yes,locked 2006.173.19:32:57.89/vblo/05,709.99,yes,locked 2006.173.19:32:57.89/vblo/06,719.99,yes,locked 2006.173.19:32:57.89/vblo/07,734.99,yes,locked 2006.173.19:32:57.89/vblo/08,744.99,yes,locked 2006.173.19:32:58.04/vabw/8 2006.173.19:32:58.19/vbbw/8 2006.173.19:32:58.28/xfe/off,on,15.2 2006.173.19:32:58.66/ifatt/23,28,28,28 2006.173.19:32:59.07/fmout-gps/S +3.87E-07 2006.173.19:32:59.11:!2006.173.19:34:54 2006.173.19:34:54.01:data_valid=off 2006.173.19:34:54.01:"et 2006.173.19:34:54.02:!+3s 2006.173.19:34:57.03:"tape 2006.173.19:34:57.03:postob 2006.173.19:34:57.17/cable/+6.5183E-03 2006.173.19:34:57.17/wx/19.35,1002.5,100 2006.173.19:34:57.23/fmout-gps/S +3.88E-07 2006.173.19:34:57.23:scan_name=173-1940,jd0606,40 2006.173.19:34:57.24:source=1908-201,191109.65,-200655.1,2000.0,ccw 2006.173.19:34:58.14#flagr#flagr/antenna,new-source 2006.173.19:34:58.14:checkk5 2006.173.19:34:58.54/chk_autoobs//k5ts1/ autoobs is running! 2006.173.19:34:58.94/chk_autoobs//k5ts2/ autoobs is running! 2006.173.19:34:59.34/chk_autoobs//k5ts3/ autoobs is running! 2006.173.19:34:59.74/chk_autoobs//k5ts4/ autoobs is running! 2006.173.19:35:00.12/chk_obsdata//k5ts1/T1731932??a.dat file size is correct (nominal:480MB, actual:476MB). 2006.173.19:35:00.53/chk_obsdata//k5ts2/T1731932??b.dat file size is correct (nominal:480MB, actual:476MB). 2006.173.19:35:00.93/chk_obsdata//k5ts3/T1731932??c.dat file size is correct (nominal:480MB, actual:476MB). 2006.173.19:35:01.34/chk_obsdata//k5ts4/T1731932??d.dat file size is correct (nominal:480MB, actual:476MB). 2006.173.19:35:02.05/k5log//k5ts1_log_newline 2006.173.19:35:02.76/k5log//k5ts2_log_newline 2006.173.19:35:03.49/k5log//k5ts3_log_newline 2006.173.19:35:04.18/k5log//k5ts4_log_newline 2006.173.19:35:04.21/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.19:35:04.21:setupk4=1 2006.173.19:35:04.21$setupk4/echo=on 2006.173.19:35:04.21$setupk4/pcalon 2006.173.19:35:04.21$pcalon/"no phase cal control is implemented here 2006.173.19:35:04.21$setupk4/"tpicd=stop 2006.173.19:35:04.21$setupk4/"rec=synch_on 2006.173.19:35:04.21$setupk4/"rec_mode=128 2006.173.19:35:04.21$setupk4/!* 2006.173.19:35:04.21$setupk4/recpk4 2006.173.19:35:04.21$recpk4/recpatch= 2006.173.19:35:04.22$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.19:35:04.22$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.19:35:04.22$setupk4/vck44 2006.173.19:35:04.22$vck44/valo=1,524.99 2006.173.19:35:04.22#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.19:35:04.22#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.19:35:04.22#ibcon#ireg 17 cls_cnt 0 2006.173.19:35:04.22#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.19:35:04.22#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.19:35:04.22#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.19:35:04.22#ibcon#enter wrdev, iclass 32, count 0 2006.173.19:35:04.22#ibcon#first serial, iclass 32, count 0 2006.173.19:35:04.22#ibcon#enter sib2, iclass 32, count 0 2006.173.19:35:04.22#ibcon#flushed, iclass 32, count 0 2006.173.19:35:04.22#ibcon#about to write, iclass 32, count 0 2006.173.19:35:04.22#ibcon#wrote, iclass 32, count 0 2006.173.19:35:04.22#ibcon#about to read 3, iclass 32, count 0 2006.173.19:35:04.24#ibcon#read 3, iclass 32, count 0 2006.173.19:35:04.24#ibcon#about to read 4, iclass 32, count 0 2006.173.19:35:04.24#ibcon#read 4, iclass 32, count 0 2006.173.19:35:04.24#ibcon#about to read 5, iclass 32, count 0 2006.173.19:35:04.24#ibcon#read 5, iclass 32, count 0 2006.173.19:35:04.24#ibcon#about to read 6, iclass 32, count 0 2006.173.19:35:04.24#ibcon#read 6, iclass 32, count 0 2006.173.19:35:04.24#ibcon#end of sib2, iclass 32, count 0 2006.173.19:35:04.24#ibcon#*mode == 0, iclass 32, count 0 2006.173.19:35:04.24#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.19:35:04.24#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.19:35:04.24#ibcon#*before write, iclass 32, count 0 2006.173.19:35:04.24#ibcon#enter sib2, iclass 32, count 0 2006.173.19:35:04.24#ibcon#flushed, iclass 32, count 0 2006.173.19:35:04.24#ibcon#about to write, iclass 32, count 0 2006.173.19:35:04.24#ibcon#wrote, iclass 32, count 0 2006.173.19:35:04.24#ibcon#about to read 3, iclass 32, count 0 2006.173.19:35:04.29#ibcon#read 3, iclass 32, count 0 2006.173.19:35:04.29#ibcon#about to read 4, iclass 32, count 0 2006.173.19:35:04.29#ibcon#read 4, iclass 32, count 0 2006.173.19:35:04.29#ibcon#about to read 5, iclass 32, count 0 2006.173.19:35:04.29#ibcon#read 5, iclass 32, count 0 2006.173.19:35:04.29#ibcon#about to read 6, iclass 32, count 0 2006.173.19:35:04.29#ibcon#read 6, iclass 32, count 0 2006.173.19:35:04.29#ibcon#end of sib2, iclass 32, count 0 2006.173.19:35:04.29#ibcon#*after write, iclass 32, count 0 2006.173.19:35:04.29#ibcon#*before return 0, iclass 32, count 0 2006.173.19:35:04.29#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.19:35:04.29#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.19:35:04.29#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.19:35:04.29#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.19:35:04.29$vck44/va=1,7 2006.173.19:35:04.29#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.19:35:04.29#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.19:35:04.29#ibcon#ireg 11 cls_cnt 2 2006.173.19:35:04.29#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.19:35:04.29#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.19:35:04.29#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.19:35:04.29#ibcon#enter wrdev, iclass 34, count 2 2006.173.19:35:04.29#ibcon#first serial, iclass 34, count 2 2006.173.19:35:04.29#ibcon#enter sib2, iclass 34, count 2 2006.173.19:35:04.29#ibcon#flushed, iclass 34, count 2 2006.173.19:35:04.29#ibcon#about to write, iclass 34, count 2 2006.173.19:35:04.29#ibcon#wrote, iclass 34, count 2 2006.173.19:35:04.29#ibcon#about to read 3, iclass 34, count 2 2006.173.19:35:04.31#ibcon#read 3, iclass 34, count 2 2006.173.19:35:04.31#ibcon#about to read 4, iclass 34, count 2 2006.173.19:35:04.31#ibcon#read 4, iclass 34, count 2 2006.173.19:35:04.31#ibcon#about to read 5, iclass 34, count 2 2006.173.19:35:04.31#ibcon#read 5, iclass 34, count 2 2006.173.19:35:04.31#ibcon#about to read 6, iclass 34, count 2 2006.173.19:35:04.31#ibcon#read 6, iclass 34, count 2 2006.173.19:35:04.31#ibcon#end of sib2, iclass 34, count 2 2006.173.19:35:04.31#ibcon#*mode == 0, iclass 34, count 2 2006.173.19:35:04.31#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.19:35:04.31#ibcon#[25=AT01-07\r\n] 2006.173.19:35:04.31#ibcon#*before write, iclass 34, count 2 2006.173.19:35:04.31#ibcon#enter sib2, iclass 34, count 2 2006.173.19:35:04.31#ibcon#flushed, iclass 34, count 2 2006.173.19:35:04.31#ibcon#about to write, iclass 34, count 2 2006.173.19:35:04.31#ibcon#wrote, iclass 34, count 2 2006.173.19:35:04.31#ibcon#about to read 3, iclass 34, count 2 2006.173.19:35:04.34#ibcon#read 3, iclass 34, count 2 2006.173.19:35:04.34#ibcon#about to read 4, iclass 34, count 2 2006.173.19:35:04.34#ibcon#read 4, iclass 34, count 2 2006.173.19:35:04.34#ibcon#about to read 5, iclass 34, count 2 2006.173.19:35:04.34#ibcon#read 5, iclass 34, count 2 2006.173.19:35:04.34#ibcon#about to read 6, iclass 34, count 2 2006.173.19:35:04.34#ibcon#read 6, iclass 34, count 2 2006.173.19:35:04.34#ibcon#end of sib2, iclass 34, count 2 2006.173.19:35:04.34#ibcon#*after write, iclass 34, count 2 2006.173.19:35:04.34#ibcon#*before return 0, iclass 34, count 2 2006.173.19:35:04.34#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.19:35:04.34#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.19:35:04.34#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.19:35:04.34#ibcon#ireg 7 cls_cnt 0 2006.173.19:35:04.34#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.19:35:04.46#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.19:35:04.46#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.19:35:04.46#ibcon#enter wrdev, iclass 34, count 0 2006.173.19:35:04.46#ibcon#first serial, iclass 34, count 0 2006.173.19:35:04.46#ibcon#enter sib2, iclass 34, count 0 2006.173.19:35:04.46#ibcon#flushed, iclass 34, count 0 2006.173.19:35:04.46#ibcon#about to write, iclass 34, count 0 2006.173.19:35:04.46#ibcon#wrote, iclass 34, count 0 2006.173.19:35:04.46#ibcon#about to read 3, iclass 34, count 0 2006.173.19:35:04.48#ibcon#read 3, iclass 34, count 0 2006.173.19:35:04.48#ibcon#about to read 4, iclass 34, count 0 2006.173.19:35:04.48#ibcon#read 4, iclass 34, count 0 2006.173.19:35:04.48#ibcon#about to read 5, iclass 34, count 0 2006.173.19:35:04.48#ibcon#read 5, iclass 34, count 0 2006.173.19:35:04.48#ibcon#about to read 6, iclass 34, count 0 2006.173.19:35:04.48#ibcon#read 6, iclass 34, count 0 2006.173.19:35:04.48#ibcon#end of sib2, iclass 34, count 0 2006.173.19:35:04.48#ibcon#*mode == 0, iclass 34, count 0 2006.173.19:35:04.48#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.19:35:04.48#ibcon#[25=USB\r\n] 2006.173.19:35:04.48#ibcon#*before write, iclass 34, count 0 2006.173.19:35:04.48#ibcon#enter sib2, iclass 34, count 0 2006.173.19:35:04.48#ibcon#flushed, iclass 34, count 0 2006.173.19:35:04.48#ibcon#about to write, iclass 34, count 0 2006.173.19:35:04.48#ibcon#wrote, iclass 34, count 0 2006.173.19:35:04.48#ibcon#about to read 3, iclass 34, count 0 2006.173.19:35:04.51#ibcon#read 3, iclass 34, count 0 2006.173.19:35:04.51#ibcon#about to read 4, iclass 34, count 0 2006.173.19:35:04.51#ibcon#read 4, iclass 34, count 0 2006.173.19:35:04.51#ibcon#about to read 5, iclass 34, count 0 2006.173.19:35:04.51#ibcon#read 5, iclass 34, count 0 2006.173.19:35:04.51#ibcon#about to read 6, iclass 34, count 0 2006.173.19:35:04.51#ibcon#read 6, iclass 34, count 0 2006.173.19:35:04.51#ibcon#end of sib2, iclass 34, count 0 2006.173.19:35:04.51#ibcon#*after write, iclass 34, count 0 2006.173.19:35:04.51#ibcon#*before return 0, iclass 34, count 0 2006.173.19:35:04.51#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.19:35:04.51#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.19:35:04.51#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.19:35:04.51#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.19:35:04.51$vck44/valo=2,534.99 2006.173.19:35:04.51#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.19:35:04.51#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.19:35:04.51#ibcon#ireg 17 cls_cnt 0 2006.173.19:35:04.51#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.19:35:04.51#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.19:35:04.51#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.19:35:04.51#ibcon#enter wrdev, iclass 36, count 0 2006.173.19:35:04.51#ibcon#first serial, iclass 36, count 0 2006.173.19:35:04.51#ibcon#enter sib2, iclass 36, count 0 2006.173.19:35:04.51#ibcon#flushed, iclass 36, count 0 2006.173.19:35:04.51#ibcon#about to write, iclass 36, count 0 2006.173.19:35:04.51#ibcon#wrote, iclass 36, count 0 2006.173.19:35:04.51#ibcon#about to read 3, iclass 36, count 0 2006.173.19:35:04.53#ibcon#read 3, iclass 36, count 0 2006.173.19:35:04.53#ibcon#about to read 4, iclass 36, count 0 2006.173.19:35:04.53#ibcon#read 4, iclass 36, count 0 2006.173.19:35:04.53#ibcon#about to read 5, iclass 36, count 0 2006.173.19:35:04.53#ibcon#read 5, iclass 36, count 0 2006.173.19:35:04.53#ibcon#about to read 6, iclass 36, count 0 2006.173.19:35:04.53#ibcon#read 6, iclass 36, count 0 2006.173.19:35:04.53#ibcon#end of sib2, iclass 36, count 0 2006.173.19:35:04.53#ibcon#*mode == 0, iclass 36, count 0 2006.173.19:35:04.53#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.19:35:04.53#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.19:35:04.53#ibcon#*before write, iclass 36, count 0 2006.173.19:35:04.53#ibcon#enter sib2, iclass 36, count 0 2006.173.19:35:04.53#ibcon#flushed, iclass 36, count 0 2006.173.19:35:04.53#ibcon#about to write, iclass 36, count 0 2006.173.19:35:04.53#ibcon#wrote, iclass 36, count 0 2006.173.19:35:04.53#ibcon#about to read 3, iclass 36, count 0 2006.173.19:35:04.57#ibcon#read 3, iclass 36, count 0 2006.173.19:35:04.57#ibcon#about to read 4, iclass 36, count 0 2006.173.19:35:04.57#ibcon#read 4, iclass 36, count 0 2006.173.19:35:04.57#ibcon#about to read 5, iclass 36, count 0 2006.173.19:35:04.57#ibcon#read 5, iclass 36, count 0 2006.173.19:35:04.57#ibcon#about to read 6, iclass 36, count 0 2006.173.19:35:04.57#ibcon#read 6, iclass 36, count 0 2006.173.19:35:04.57#ibcon#end of sib2, iclass 36, count 0 2006.173.19:35:04.57#ibcon#*after write, iclass 36, count 0 2006.173.19:35:04.57#ibcon#*before return 0, iclass 36, count 0 2006.173.19:35:04.57#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.19:35:04.57#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.19:35:04.57#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.19:35:04.57#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.19:35:04.57$vck44/va=2,6 2006.173.19:35:04.57#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.19:35:04.57#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.19:35:04.57#ibcon#ireg 11 cls_cnt 2 2006.173.19:35:04.57#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.19:35:04.63#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.19:35:04.63#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.19:35:04.63#ibcon#enter wrdev, iclass 38, count 2 2006.173.19:35:04.63#ibcon#first serial, iclass 38, count 2 2006.173.19:35:04.63#ibcon#enter sib2, iclass 38, count 2 2006.173.19:35:04.63#ibcon#flushed, iclass 38, count 2 2006.173.19:35:04.63#ibcon#about to write, iclass 38, count 2 2006.173.19:35:04.63#ibcon#wrote, iclass 38, count 2 2006.173.19:35:04.63#ibcon#about to read 3, iclass 38, count 2 2006.173.19:35:04.65#ibcon#read 3, iclass 38, count 2 2006.173.19:35:04.65#ibcon#about to read 4, iclass 38, count 2 2006.173.19:35:04.65#ibcon#read 4, iclass 38, count 2 2006.173.19:35:04.65#ibcon#about to read 5, iclass 38, count 2 2006.173.19:35:04.65#ibcon#read 5, iclass 38, count 2 2006.173.19:35:04.65#ibcon#about to read 6, iclass 38, count 2 2006.173.19:35:04.65#ibcon#read 6, iclass 38, count 2 2006.173.19:35:04.65#ibcon#end of sib2, iclass 38, count 2 2006.173.19:35:04.65#ibcon#*mode == 0, iclass 38, count 2 2006.173.19:35:04.65#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.19:35:04.65#ibcon#[25=AT02-06\r\n] 2006.173.19:35:04.65#ibcon#*before write, iclass 38, count 2 2006.173.19:35:04.65#ibcon#enter sib2, iclass 38, count 2 2006.173.19:35:04.65#ibcon#flushed, iclass 38, count 2 2006.173.19:35:04.65#ibcon#about to write, iclass 38, count 2 2006.173.19:35:04.65#ibcon#wrote, iclass 38, count 2 2006.173.19:35:04.65#ibcon#about to read 3, iclass 38, count 2 2006.173.19:35:04.68#ibcon#read 3, iclass 38, count 2 2006.173.19:35:04.68#ibcon#about to read 4, iclass 38, count 2 2006.173.19:35:04.68#ibcon#read 4, iclass 38, count 2 2006.173.19:35:04.68#ibcon#about to read 5, iclass 38, count 2 2006.173.19:35:04.68#ibcon#read 5, iclass 38, count 2 2006.173.19:35:04.68#ibcon#about to read 6, iclass 38, count 2 2006.173.19:35:04.68#ibcon#read 6, iclass 38, count 2 2006.173.19:35:04.68#ibcon#end of sib2, iclass 38, count 2 2006.173.19:35:04.68#ibcon#*after write, iclass 38, count 2 2006.173.19:35:04.68#ibcon#*before return 0, iclass 38, count 2 2006.173.19:35:04.68#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.19:35:04.68#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.19:35:04.68#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.19:35:04.68#ibcon#ireg 7 cls_cnt 0 2006.173.19:35:04.68#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.19:35:04.80#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.19:35:04.80#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.19:35:04.80#ibcon#enter wrdev, iclass 38, count 0 2006.173.19:35:04.80#ibcon#first serial, iclass 38, count 0 2006.173.19:35:04.80#ibcon#enter sib2, iclass 38, count 0 2006.173.19:35:04.80#ibcon#flushed, iclass 38, count 0 2006.173.19:35:04.80#ibcon#about to write, iclass 38, count 0 2006.173.19:35:04.80#ibcon#wrote, iclass 38, count 0 2006.173.19:35:04.80#ibcon#about to read 3, iclass 38, count 0 2006.173.19:35:04.82#ibcon#read 3, iclass 38, count 0 2006.173.19:35:04.82#ibcon#about to read 4, iclass 38, count 0 2006.173.19:35:04.82#ibcon#read 4, iclass 38, count 0 2006.173.19:35:04.82#ibcon#about to read 5, iclass 38, count 0 2006.173.19:35:04.82#ibcon#read 5, iclass 38, count 0 2006.173.19:35:04.82#ibcon#about to read 6, iclass 38, count 0 2006.173.19:35:04.82#ibcon#read 6, iclass 38, count 0 2006.173.19:35:04.82#ibcon#end of sib2, iclass 38, count 0 2006.173.19:35:04.82#ibcon#*mode == 0, iclass 38, count 0 2006.173.19:35:04.82#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.19:35:04.82#ibcon#[25=USB\r\n] 2006.173.19:35:04.82#ibcon#*before write, iclass 38, count 0 2006.173.19:35:04.82#ibcon#enter sib2, iclass 38, count 0 2006.173.19:35:04.82#ibcon#flushed, iclass 38, count 0 2006.173.19:35:04.82#ibcon#about to write, iclass 38, count 0 2006.173.19:35:04.82#ibcon#wrote, iclass 38, count 0 2006.173.19:35:04.82#ibcon#about to read 3, iclass 38, count 0 2006.173.19:35:04.85#ibcon#read 3, iclass 38, count 0 2006.173.19:35:04.85#ibcon#about to read 4, iclass 38, count 0 2006.173.19:35:04.85#ibcon#read 4, iclass 38, count 0 2006.173.19:35:04.85#ibcon#about to read 5, iclass 38, count 0 2006.173.19:35:04.85#ibcon#read 5, iclass 38, count 0 2006.173.19:35:04.85#ibcon#about to read 6, iclass 38, count 0 2006.173.19:35:04.85#ibcon#read 6, iclass 38, count 0 2006.173.19:35:04.85#ibcon#end of sib2, iclass 38, count 0 2006.173.19:35:04.85#ibcon#*after write, iclass 38, count 0 2006.173.19:35:04.85#ibcon#*before return 0, iclass 38, count 0 2006.173.19:35:04.85#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.19:35:04.85#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.19:35:04.85#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.19:35:04.85#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.19:35:04.85$vck44/valo=3,564.99 2006.173.19:35:04.85#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.19:35:04.85#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.19:35:04.85#ibcon#ireg 17 cls_cnt 0 2006.173.19:35:04.85#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.19:35:04.85#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.19:35:04.85#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.19:35:04.85#ibcon#enter wrdev, iclass 40, count 0 2006.173.19:35:04.85#ibcon#first serial, iclass 40, count 0 2006.173.19:35:04.85#ibcon#enter sib2, iclass 40, count 0 2006.173.19:35:04.85#ibcon#flushed, iclass 40, count 0 2006.173.19:35:04.85#ibcon#about to write, iclass 40, count 0 2006.173.19:35:04.85#ibcon#wrote, iclass 40, count 0 2006.173.19:35:04.85#ibcon#about to read 3, iclass 40, count 0 2006.173.19:35:04.87#ibcon#read 3, iclass 40, count 0 2006.173.19:35:04.87#ibcon#about to read 4, iclass 40, count 0 2006.173.19:35:04.87#ibcon#read 4, iclass 40, count 0 2006.173.19:35:04.87#ibcon#about to read 5, iclass 40, count 0 2006.173.19:35:04.87#ibcon#read 5, iclass 40, count 0 2006.173.19:35:04.87#ibcon#about to read 6, iclass 40, count 0 2006.173.19:35:04.87#ibcon#read 6, iclass 40, count 0 2006.173.19:35:04.87#ibcon#end of sib2, iclass 40, count 0 2006.173.19:35:04.87#ibcon#*mode == 0, iclass 40, count 0 2006.173.19:35:04.87#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.19:35:04.87#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.19:35:04.87#ibcon#*before write, iclass 40, count 0 2006.173.19:35:04.87#ibcon#enter sib2, iclass 40, count 0 2006.173.19:35:04.87#ibcon#flushed, iclass 40, count 0 2006.173.19:35:04.87#ibcon#about to write, iclass 40, count 0 2006.173.19:35:04.87#ibcon#wrote, iclass 40, count 0 2006.173.19:35:04.87#ibcon#about to read 3, iclass 40, count 0 2006.173.19:35:04.91#ibcon#read 3, iclass 40, count 0 2006.173.19:35:04.91#ibcon#about to read 4, iclass 40, count 0 2006.173.19:35:04.91#ibcon#read 4, iclass 40, count 0 2006.173.19:35:04.91#ibcon#about to read 5, iclass 40, count 0 2006.173.19:35:04.91#ibcon#read 5, iclass 40, count 0 2006.173.19:35:04.91#ibcon#about to read 6, iclass 40, count 0 2006.173.19:35:04.91#ibcon#read 6, iclass 40, count 0 2006.173.19:35:04.91#ibcon#end of sib2, iclass 40, count 0 2006.173.19:35:04.91#ibcon#*after write, iclass 40, count 0 2006.173.19:35:04.91#ibcon#*before return 0, iclass 40, count 0 2006.173.19:35:04.91#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.19:35:04.91#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.19:35:04.91#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.19:35:04.91#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.19:35:04.91$vck44/va=3,5 2006.173.19:35:04.91#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.19:35:04.91#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.19:35:04.91#ibcon#ireg 11 cls_cnt 2 2006.173.19:35:04.91#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.19:35:04.97#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.19:35:04.97#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.19:35:04.97#ibcon#enter wrdev, iclass 4, count 2 2006.173.19:35:04.97#ibcon#first serial, iclass 4, count 2 2006.173.19:35:04.97#ibcon#enter sib2, iclass 4, count 2 2006.173.19:35:04.97#ibcon#flushed, iclass 4, count 2 2006.173.19:35:04.97#ibcon#about to write, iclass 4, count 2 2006.173.19:35:04.97#ibcon#wrote, iclass 4, count 2 2006.173.19:35:04.97#ibcon#about to read 3, iclass 4, count 2 2006.173.19:35:04.99#ibcon#read 3, iclass 4, count 2 2006.173.19:35:04.99#ibcon#about to read 4, iclass 4, count 2 2006.173.19:35:04.99#ibcon#read 4, iclass 4, count 2 2006.173.19:35:04.99#ibcon#about to read 5, iclass 4, count 2 2006.173.19:35:04.99#ibcon#read 5, iclass 4, count 2 2006.173.19:35:04.99#ibcon#about to read 6, iclass 4, count 2 2006.173.19:35:04.99#ibcon#read 6, iclass 4, count 2 2006.173.19:35:04.99#ibcon#end of sib2, iclass 4, count 2 2006.173.19:35:04.99#ibcon#*mode == 0, iclass 4, count 2 2006.173.19:35:04.99#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.19:35:04.99#ibcon#[25=AT03-05\r\n] 2006.173.19:35:04.99#ibcon#*before write, iclass 4, count 2 2006.173.19:35:04.99#ibcon#enter sib2, iclass 4, count 2 2006.173.19:35:04.99#ibcon#flushed, iclass 4, count 2 2006.173.19:35:04.99#ibcon#about to write, iclass 4, count 2 2006.173.19:35:04.99#ibcon#wrote, iclass 4, count 2 2006.173.19:35:04.99#ibcon#about to read 3, iclass 4, count 2 2006.173.19:35:05.02#ibcon#read 3, iclass 4, count 2 2006.173.19:35:05.02#ibcon#about to read 4, iclass 4, count 2 2006.173.19:35:05.02#ibcon#read 4, iclass 4, count 2 2006.173.19:35:05.02#ibcon#about to read 5, iclass 4, count 2 2006.173.19:35:05.02#ibcon#read 5, iclass 4, count 2 2006.173.19:35:05.02#ibcon#about to read 6, iclass 4, count 2 2006.173.19:35:05.02#ibcon#read 6, iclass 4, count 2 2006.173.19:35:05.02#ibcon#end of sib2, iclass 4, count 2 2006.173.19:35:05.02#ibcon#*after write, iclass 4, count 2 2006.173.19:35:05.02#ibcon#*before return 0, iclass 4, count 2 2006.173.19:35:05.02#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.19:35:05.02#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.19:35:05.02#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.19:35:05.02#ibcon#ireg 7 cls_cnt 0 2006.173.19:35:05.02#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.19:35:05.14#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.19:35:05.14#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.19:35:05.14#ibcon#enter wrdev, iclass 4, count 0 2006.173.19:35:05.14#ibcon#first serial, iclass 4, count 0 2006.173.19:35:05.14#ibcon#enter sib2, iclass 4, count 0 2006.173.19:35:05.14#ibcon#flushed, iclass 4, count 0 2006.173.19:35:05.14#ibcon#about to write, iclass 4, count 0 2006.173.19:35:05.14#ibcon#wrote, iclass 4, count 0 2006.173.19:35:05.14#ibcon#about to read 3, iclass 4, count 0 2006.173.19:35:05.16#ibcon#read 3, iclass 4, count 0 2006.173.19:35:05.16#ibcon#about to read 4, iclass 4, count 0 2006.173.19:35:05.16#ibcon#read 4, iclass 4, count 0 2006.173.19:35:05.16#ibcon#about to read 5, iclass 4, count 0 2006.173.19:35:05.16#ibcon#read 5, iclass 4, count 0 2006.173.19:35:05.16#ibcon#about to read 6, iclass 4, count 0 2006.173.19:35:05.16#ibcon#read 6, iclass 4, count 0 2006.173.19:35:05.16#ibcon#end of sib2, iclass 4, count 0 2006.173.19:35:05.16#ibcon#*mode == 0, iclass 4, count 0 2006.173.19:35:05.16#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.19:35:05.16#ibcon#[25=USB\r\n] 2006.173.19:35:05.16#ibcon#*before write, iclass 4, count 0 2006.173.19:35:05.16#ibcon#enter sib2, iclass 4, count 0 2006.173.19:35:05.16#ibcon#flushed, iclass 4, count 0 2006.173.19:35:05.16#ibcon#about to write, iclass 4, count 0 2006.173.19:35:05.16#ibcon#wrote, iclass 4, count 0 2006.173.19:35:05.16#ibcon#about to read 3, iclass 4, count 0 2006.173.19:35:05.19#ibcon#read 3, iclass 4, count 0 2006.173.19:35:05.19#ibcon#about to read 4, iclass 4, count 0 2006.173.19:35:05.19#ibcon#read 4, iclass 4, count 0 2006.173.19:35:05.19#ibcon#about to read 5, iclass 4, count 0 2006.173.19:35:05.19#ibcon#read 5, iclass 4, count 0 2006.173.19:35:05.19#ibcon#about to read 6, iclass 4, count 0 2006.173.19:35:05.19#ibcon#read 6, iclass 4, count 0 2006.173.19:35:05.19#ibcon#end of sib2, iclass 4, count 0 2006.173.19:35:05.19#ibcon#*after write, iclass 4, count 0 2006.173.19:35:05.19#ibcon#*before return 0, iclass 4, count 0 2006.173.19:35:05.19#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.19:35:05.19#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.19:35:05.19#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.19:35:05.19#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.19:35:05.19$vck44/valo=4,624.99 2006.173.19:35:05.19#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.19:35:05.19#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.19:35:05.19#ibcon#ireg 17 cls_cnt 0 2006.173.19:35:05.19#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.19:35:05.19#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.19:35:05.19#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.19:35:05.19#ibcon#enter wrdev, iclass 6, count 0 2006.173.19:35:05.19#ibcon#first serial, iclass 6, count 0 2006.173.19:35:05.19#ibcon#enter sib2, iclass 6, count 0 2006.173.19:35:05.19#ibcon#flushed, iclass 6, count 0 2006.173.19:35:05.19#ibcon#about to write, iclass 6, count 0 2006.173.19:35:05.19#ibcon#wrote, iclass 6, count 0 2006.173.19:35:05.19#ibcon#about to read 3, iclass 6, count 0 2006.173.19:35:05.21#ibcon#read 3, iclass 6, count 0 2006.173.19:35:05.21#ibcon#about to read 4, iclass 6, count 0 2006.173.19:35:05.21#ibcon#read 4, iclass 6, count 0 2006.173.19:35:05.21#ibcon#about to read 5, iclass 6, count 0 2006.173.19:35:05.21#ibcon#read 5, iclass 6, count 0 2006.173.19:35:05.21#ibcon#about to read 6, iclass 6, count 0 2006.173.19:35:05.21#ibcon#read 6, iclass 6, count 0 2006.173.19:35:05.21#ibcon#end of sib2, iclass 6, count 0 2006.173.19:35:05.21#ibcon#*mode == 0, iclass 6, count 0 2006.173.19:35:05.21#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.19:35:05.21#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.19:35:05.21#ibcon#*before write, iclass 6, count 0 2006.173.19:35:05.21#ibcon#enter sib2, iclass 6, count 0 2006.173.19:35:05.21#ibcon#flushed, iclass 6, count 0 2006.173.19:35:05.21#ibcon#about to write, iclass 6, count 0 2006.173.19:35:05.21#ibcon#wrote, iclass 6, count 0 2006.173.19:35:05.21#ibcon#about to read 3, iclass 6, count 0 2006.173.19:35:05.25#ibcon#read 3, iclass 6, count 0 2006.173.19:35:05.25#ibcon#about to read 4, iclass 6, count 0 2006.173.19:35:05.25#ibcon#read 4, iclass 6, count 0 2006.173.19:35:05.25#ibcon#about to read 5, iclass 6, count 0 2006.173.19:35:05.25#ibcon#read 5, iclass 6, count 0 2006.173.19:35:05.25#ibcon#about to read 6, iclass 6, count 0 2006.173.19:35:05.25#ibcon#read 6, iclass 6, count 0 2006.173.19:35:05.25#ibcon#end of sib2, iclass 6, count 0 2006.173.19:35:05.25#ibcon#*after write, iclass 6, count 0 2006.173.19:35:05.25#ibcon#*before return 0, iclass 6, count 0 2006.173.19:35:05.25#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.19:35:05.25#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.19:35:05.25#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.19:35:05.25#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.19:35:05.25$vck44/va=4,6 2006.173.19:35:05.25#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.19:35:05.25#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.19:35:05.25#ibcon#ireg 11 cls_cnt 2 2006.173.19:35:05.25#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.19:35:05.31#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.19:35:05.31#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.19:35:05.31#ibcon#enter wrdev, iclass 10, count 2 2006.173.19:35:05.31#ibcon#first serial, iclass 10, count 2 2006.173.19:35:05.31#ibcon#enter sib2, iclass 10, count 2 2006.173.19:35:05.31#ibcon#flushed, iclass 10, count 2 2006.173.19:35:05.31#ibcon#about to write, iclass 10, count 2 2006.173.19:35:05.31#ibcon#wrote, iclass 10, count 2 2006.173.19:35:05.31#ibcon#about to read 3, iclass 10, count 2 2006.173.19:35:05.33#ibcon#read 3, iclass 10, count 2 2006.173.19:35:05.33#ibcon#about to read 4, iclass 10, count 2 2006.173.19:35:05.33#ibcon#read 4, iclass 10, count 2 2006.173.19:35:05.33#ibcon#about to read 5, iclass 10, count 2 2006.173.19:35:05.33#ibcon#read 5, iclass 10, count 2 2006.173.19:35:05.33#ibcon#about to read 6, iclass 10, count 2 2006.173.19:35:05.33#ibcon#read 6, iclass 10, count 2 2006.173.19:35:05.33#ibcon#end of sib2, iclass 10, count 2 2006.173.19:35:05.33#ibcon#*mode == 0, iclass 10, count 2 2006.173.19:35:05.33#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.19:35:05.33#ibcon#[25=AT04-06\r\n] 2006.173.19:35:05.33#ibcon#*before write, iclass 10, count 2 2006.173.19:35:05.33#ibcon#enter sib2, iclass 10, count 2 2006.173.19:35:05.33#ibcon#flushed, iclass 10, count 2 2006.173.19:35:05.33#ibcon#about to write, iclass 10, count 2 2006.173.19:35:05.33#ibcon#wrote, iclass 10, count 2 2006.173.19:35:05.33#ibcon#about to read 3, iclass 10, count 2 2006.173.19:35:05.36#ibcon#read 3, iclass 10, count 2 2006.173.19:35:05.36#ibcon#about to read 4, iclass 10, count 2 2006.173.19:35:05.36#ibcon#read 4, iclass 10, count 2 2006.173.19:35:05.36#ibcon#about to read 5, iclass 10, count 2 2006.173.19:35:05.36#ibcon#read 5, iclass 10, count 2 2006.173.19:35:05.36#ibcon#about to read 6, iclass 10, count 2 2006.173.19:35:05.36#ibcon#read 6, iclass 10, count 2 2006.173.19:35:05.36#ibcon#end of sib2, iclass 10, count 2 2006.173.19:35:05.36#ibcon#*after write, iclass 10, count 2 2006.173.19:35:05.36#ibcon#*before return 0, iclass 10, count 2 2006.173.19:35:05.36#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.19:35:05.36#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.19:35:05.36#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.19:35:05.36#ibcon#ireg 7 cls_cnt 0 2006.173.19:35:05.36#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.19:35:05.48#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.19:35:05.48#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.19:35:05.48#ibcon#enter wrdev, iclass 10, count 0 2006.173.19:35:05.48#ibcon#first serial, iclass 10, count 0 2006.173.19:35:05.48#ibcon#enter sib2, iclass 10, count 0 2006.173.19:35:05.48#ibcon#flushed, iclass 10, count 0 2006.173.19:35:05.48#ibcon#about to write, iclass 10, count 0 2006.173.19:35:05.48#ibcon#wrote, iclass 10, count 0 2006.173.19:35:05.48#ibcon#about to read 3, iclass 10, count 0 2006.173.19:35:05.50#ibcon#read 3, iclass 10, count 0 2006.173.19:35:05.50#ibcon#about to read 4, iclass 10, count 0 2006.173.19:35:05.50#ibcon#read 4, iclass 10, count 0 2006.173.19:35:05.50#ibcon#about to read 5, iclass 10, count 0 2006.173.19:35:05.50#ibcon#read 5, iclass 10, count 0 2006.173.19:35:05.50#ibcon#about to read 6, iclass 10, count 0 2006.173.19:35:05.50#ibcon#read 6, iclass 10, count 0 2006.173.19:35:05.50#ibcon#end of sib2, iclass 10, count 0 2006.173.19:35:05.50#ibcon#*mode == 0, iclass 10, count 0 2006.173.19:35:05.50#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.19:35:05.50#ibcon#[25=USB\r\n] 2006.173.19:35:05.50#ibcon#*before write, iclass 10, count 0 2006.173.19:35:05.50#ibcon#enter sib2, iclass 10, count 0 2006.173.19:35:05.50#ibcon#flushed, iclass 10, count 0 2006.173.19:35:05.50#ibcon#about to write, iclass 10, count 0 2006.173.19:35:05.50#ibcon#wrote, iclass 10, count 0 2006.173.19:35:05.50#ibcon#about to read 3, iclass 10, count 0 2006.173.19:35:05.53#ibcon#read 3, iclass 10, count 0 2006.173.19:35:05.53#ibcon#about to read 4, iclass 10, count 0 2006.173.19:35:05.53#ibcon#read 4, iclass 10, count 0 2006.173.19:35:05.53#ibcon#about to read 5, iclass 10, count 0 2006.173.19:35:05.53#ibcon#read 5, iclass 10, count 0 2006.173.19:35:05.53#ibcon#about to read 6, iclass 10, count 0 2006.173.19:35:05.53#ibcon#read 6, iclass 10, count 0 2006.173.19:35:05.53#ibcon#end of sib2, iclass 10, count 0 2006.173.19:35:05.53#ibcon#*after write, iclass 10, count 0 2006.173.19:35:05.53#ibcon#*before return 0, iclass 10, count 0 2006.173.19:35:05.53#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.19:35:05.53#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.19:35:05.53#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.19:35:05.53#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.19:35:05.53$vck44/valo=5,734.99 2006.173.19:35:05.53#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.19:35:05.53#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.19:35:05.53#ibcon#ireg 17 cls_cnt 0 2006.173.19:35:05.53#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.19:35:05.53#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.19:35:05.53#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.19:35:05.53#ibcon#enter wrdev, iclass 12, count 0 2006.173.19:35:05.53#ibcon#first serial, iclass 12, count 0 2006.173.19:35:05.53#ibcon#enter sib2, iclass 12, count 0 2006.173.19:35:05.53#ibcon#flushed, iclass 12, count 0 2006.173.19:35:05.53#ibcon#about to write, iclass 12, count 0 2006.173.19:35:05.53#ibcon#wrote, iclass 12, count 0 2006.173.19:35:05.53#ibcon#about to read 3, iclass 12, count 0 2006.173.19:35:05.55#ibcon#read 3, iclass 12, count 0 2006.173.19:35:05.55#ibcon#about to read 4, iclass 12, count 0 2006.173.19:35:05.55#ibcon#read 4, iclass 12, count 0 2006.173.19:35:05.55#ibcon#about to read 5, iclass 12, count 0 2006.173.19:35:05.55#ibcon#read 5, iclass 12, count 0 2006.173.19:35:05.55#ibcon#about to read 6, iclass 12, count 0 2006.173.19:35:05.55#ibcon#read 6, iclass 12, count 0 2006.173.19:35:05.55#ibcon#end of sib2, iclass 12, count 0 2006.173.19:35:05.55#ibcon#*mode == 0, iclass 12, count 0 2006.173.19:35:05.55#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.19:35:05.55#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.19:35:05.55#ibcon#*before write, iclass 12, count 0 2006.173.19:35:05.55#ibcon#enter sib2, iclass 12, count 0 2006.173.19:35:05.55#ibcon#flushed, iclass 12, count 0 2006.173.19:35:05.55#ibcon#about to write, iclass 12, count 0 2006.173.19:35:05.55#ibcon#wrote, iclass 12, count 0 2006.173.19:35:05.55#ibcon#about to read 3, iclass 12, count 0 2006.173.19:35:05.59#ibcon#read 3, iclass 12, count 0 2006.173.19:35:05.59#ibcon#about to read 4, iclass 12, count 0 2006.173.19:35:05.59#ibcon#read 4, iclass 12, count 0 2006.173.19:35:05.59#ibcon#about to read 5, iclass 12, count 0 2006.173.19:35:05.59#ibcon#read 5, iclass 12, count 0 2006.173.19:35:05.59#ibcon#about to read 6, iclass 12, count 0 2006.173.19:35:05.59#ibcon#read 6, iclass 12, count 0 2006.173.19:35:05.59#ibcon#end of sib2, iclass 12, count 0 2006.173.19:35:05.59#ibcon#*after write, iclass 12, count 0 2006.173.19:35:05.59#ibcon#*before return 0, iclass 12, count 0 2006.173.19:35:05.59#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.19:35:05.59#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.19:35:05.59#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.19:35:05.59#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.19:35:05.59$vck44/va=5,4 2006.173.19:35:05.59#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.19:35:05.59#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.19:35:05.59#ibcon#ireg 11 cls_cnt 2 2006.173.19:35:05.59#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.19:35:05.65#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.19:35:05.65#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.19:35:05.65#ibcon#enter wrdev, iclass 14, count 2 2006.173.19:35:05.65#ibcon#first serial, iclass 14, count 2 2006.173.19:35:05.65#ibcon#enter sib2, iclass 14, count 2 2006.173.19:35:05.65#ibcon#flushed, iclass 14, count 2 2006.173.19:35:05.65#ibcon#about to write, iclass 14, count 2 2006.173.19:35:05.65#ibcon#wrote, iclass 14, count 2 2006.173.19:35:05.65#ibcon#about to read 3, iclass 14, count 2 2006.173.19:35:05.67#ibcon#read 3, iclass 14, count 2 2006.173.19:35:05.67#ibcon#about to read 4, iclass 14, count 2 2006.173.19:35:05.67#ibcon#read 4, iclass 14, count 2 2006.173.19:35:05.67#ibcon#about to read 5, iclass 14, count 2 2006.173.19:35:05.67#ibcon#read 5, iclass 14, count 2 2006.173.19:35:05.67#ibcon#about to read 6, iclass 14, count 2 2006.173.19:35:05.67#ibcon#read 6, iclass 14, count 2 2006.173.19:35:05.67#ibcon#end of sib2, iclass 14, count 2 2006.173.19:35:05.67#ibcon#*mode == 0, iclass 14, count 2 2006.173.19:35:05.67#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.19:35:05.67#ibcon#[25=AT05-04\r\n] 2006.173.19:35:05.67#ibcon#*before write, iclass 14, count 2 2006.173.19:35:05.67#ibcon#enter sib2, iclass 14, count 2 2006.173.19:35:05.67#ibcon#flushed, iclass 14, count 2 2006.173.19:35:05.67#ibcon#about to write, iclass 14, count 2 2006.173.19:35:05.67#ibcon#wrote, iclass 14, count 2 2006.173.19:35:05.67#ibcon#about to read 3, iclass 14, count 2 2006.173.19:35:05.70#ibcon#read 3, iclass 14, count 2 2006.173.19:35:05.70#ibcon#about to read 4, iclass 14, count 2 2006.173.19:35:05.70#ibcon#read 4, iclass 14, count 2 2006.173.19:35:05.70#ibcon#about to read 5, iclass 14, count 2 2006.173.19:35:05.70#ibcon#read 5, iclass 14, count 2 2006.173.19:35:05.70#ibcon#about to read 6, iclass 14, count 2 2006.173.19:35:05.70#ibcon#read 6, iclass 14, count 2 2006.173.19:35:05.70#ibcon#end of sib2, iclass 14, count 2 2006.173.19:35:05.70#ibcon#*after write, iclass 14, count 2 2006.173.19:35:05.70#ibcon#*before return 0, iclass 14, count 2 2006.173.19:35:05.70#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.19:35:05.70#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.19:35:05.70#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.19:35:05.70#ibcon#ireg 7 cls_cnt 0 2006.173.19:35:05.70#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.19:35:05.82#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.19:35:05.82#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.19:35:05.82#ibcon#enter wrdev, iclass 14, count 0 2006.173.19:35:05.82#ibcon#first serial, iclass 14, count 0 2006.173.19:35:05.82#ibcon#enter sib2, iclass 14, count 0 2006.173.19:35:05.82#ibcon#flushed, iclass 14, count 0 2006.173.19:35:05.82#ibcon#about to write, iclass 14, count 0 2006.173.19:35:05.82#ibcon#wrote, iclass 14, count 0 2006.173.19:35:05.82#ibcon#about to read 3, iclass 14, count 0 2006.173.19:35:05.84#ibcon#read 3, iclass 14, count 0 2006.173.19:35:05.84#ibcon#about to read 4, iclass 14, count 0 2006.173.19:35:05.84#ibcon#read 4, iclass 14, count 0 2006.173.19:35:05.84#ibcon#about to read 5, iclass 14, count 0 2006.173.19:35:05.84#ibcon#read 5, iclass 14, count 0 2006.173.19:35:05.84#ibcon#about to read 6, iclass 14, count 0 2006.173.19:35:05.84#ibcon#read 6, iclass 14, count 0 2006.173.19:35:05.84#ibcon#end of sib2, iclass 14, count 0 2006.173.19:35:05.84#ibcon#*mode == 0, iclass 14, count 0 2006.173.19:35:05.84#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.19:35:05.84#ibcon#[25=USB\r\n] 2006.173.19:35:05.84#ibcon#*before write, iclass 14, count 0 2006.173.19:35:05.84#ibcon#enter sib2, iclass 14, count 0 2006.173.19:35:05.84#ibcon#flushed, iclass 14, count 0 2006.173.19:35:05.84#ibcon#about to write, iclass 14, count 0 2006.173.19:35:05.84#ibcon#wrote, iclass 14, count 0 2006.173.19:35:05.84#ibcon#about to read 3, iclass 14, count 0 2006.173.19:35:05.87#ibcon#read 3, iclass 14, count 0 2006.173.19:35:05.87#ibcon#about to read 4, iclass 14, count 0 2006.173.19:35:05.87#ibcon#read 4, iclass 14, count 0 2006.173.19:35:05.87#ibcon#about to read 5, iclass 14, count 0 2006.173.19:35:05.87#ibcon#read 5, iclass 14, count 0 2006.173.19:35:05.87#ibcon#about to read 6, iclass 14, count 0 2006.173.19:35:05.87#ibcon#read 6, iclass 14, count 0 2006.173.19:35:05.87#ibcon#end of sib2, iclass 14, count 0 2006.173.19:35:05.87#ibcon#*after write, iclass 14, count 0 2006.173.19:35:05.87#ibcon#*before return 0, iclass 14, count 0 2006.173.19:35:05.87#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.19:35:05.87#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.19:35:05.87#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.19:35:05.87#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.19:35:05.87$vck44/valo=6,814.99 2006.173.19:35:05.87#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.19:35:05.87#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.19:35:05.87#ibcon#ireg 17 cls_cnt 0 2006.173.19:35:05.87#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.19:35:05.87#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.19:35:05.87#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.19:35:05.87#ibcon#enter wrdev, iclass 16, count 0 2006.173.19:35:05.87#ibcon#first serial, iclass 16, count 0 2006.173.19:35:05.87#ibcon#enter sib2, iclass 16, count 0 2006.173.19:35:05.87#ibcon#flushed, iclass 16, count 0 2006.173.19:35:05.87#ibcon#about to write, iclass 16, count 0 2006.173.19:35:05.87#ibcon#wrote, iclass 16, count 0 2006.173.19:35:05.87#ibcon#about to read 3, iclass 16, count 0 2006.173.19:35:05.89#ibcon#read 3, iclass 16, count 0 2006.173.19:35:05.89#ibcon#about to read 4, iclass 16, count 0 2006.173.19:35:05.89#ibcon#read 4, iclass 16, count 0 2006.173.19:35:05.89#ibcon#about to read 5, iclass 16, count 0 2006.173.19:35:05.89#ibcon#read 5, iclass 16, count 0 2006.173.19:35:05.89#ibcon#about to read 6, iclass 16, count 0 2006.173.19:35:05.89#ibcon#read 6, iclass 16, count 0 2006.173.19:35:05.89#ibcon#end of sib2, iclass 16, count 0 2006.173.19:35:05.89#ibcon#*mode == 0, iclass 16, count 0 2006.173.19:35:05.89#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.19:35:05.89#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.19:35:05.89#ibcon#*before write, iclass 16, count 0 2006.173.19:35:05.89#ibcon#enter sib2, iclass 16, count 0 2006.173.19:35:05.89#ibcon#flushed, iclass 16, count 0 2006.173.19:35:05.89#ibcon#about to write, iclass 16, count 0 2006.173.19:35:05.89#ibcon#wrote, iclass 16, count 0 2006.173.19:35:05.89#ibcon#about to read 3, iclass 16, count 0 2006.173.19:35:05.93#ibcon#read 3, iclass 16, count 0 2006.173.19:35:05.93#ibcon#about to read 4, iclass 16, count 0 2006.173.19:35:05.93#ibcon#read 4, iclass 16, count 0 2006.173.19:35:05.93#ibcon#about to read 5, iclass 16, count 0 2006.173.19:35:05.93#ibcon#read 5, iclass 16, count 0 2006.173.19:35:05.93#ibcon#about to read 6, iclass 16, count 0 2006.173.19:35:05.93#ibcon#read 6, iclass 16, count 0 2006.173.19:35:05.93#ibcon#end of sib2, iclass 16, count 0 2006.173.19:35:05.93#ibcon#*after write, iclass 16, count 0 2006.173.19:35:05.93#ibcon#*before return 0, iclass 16, count 0 2006.173.19:35:05.93#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.19:35:05.93#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.19:35:05.93#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.19:35:05.93#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.19:35:05.93$vck44/va=6,3 2006.173.19:35:05.93#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.19:35:05.93#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.19:35:05.93#ibcon#ireg 11 cls_cnt 2 2006.173.19:35:05.93#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.19:35:05.99#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.19:35:05.99#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.19:35:05.99#ibcon#enter wrdev, iclass 18, count 2 2006.173.19:35:05.99#ibcon#first serial, iclass 18, count 2 2006.173.19:35:05.99#ibcon#enter sib2, iclass 18, count 2 2006.173.19:35:05.99#ibcon#flushed, iclass 18, count 2 2006.173.19:35:05.99#ibcon#about to write, iclass 18, count 2 2006.173.19:35:05.99#ibcon#wrote, iclass 18, count 2 2006.173.19:35:05.99#ibcon#about to read 3, iclass 18, count 2 2006.173.19:35:06.01#ibcon#read 3, iclass 18, count 2 2006.173.19:35:06.01#ibcon#about to read 4, iclass 18, count 2 2006.173.19:35:06.01#ibcon#read 4, iclass 18, count 2 2006.173.19:35:06.01#ibcon#about to read 5, iclass 18, count 2 2006.173.19:35:06.01#ibcon#read 5, iclass 18, count 2 2006.173.19:35:06.01#ibcon#about to read 6, iclass 18, count 2 2006.173.19:35:06.01#ibcon#read 6, iclass 18, count 2 2006.173.19:35:06.01#ibcon#end of sib2, iclass 18, count 2 2006.173.19:35:06.01#ibcon#*mode == 0, iclass 18, count 2 2006.173.19:35:06.01#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.19:35:06.01#ibcon#[25=AT06-03\r\n] 2006.173.19:35:06.01#ibcon#*before write, iclass 18, count 2 2006.173.19:35:06.01#ibcon#enter sib2, iclass 18, count 2 2006.173.19:35:06.01#ibcon#flushed, iclass 18, count 2 2006.173.19:35:06.01#ibcon#about to write, iclass 18, count 2 2006.173.19:35:06.01#ibcon#wrote, iclass 18, count 2 2006.173.19:35:06.01#ibcon#about to read 3, iclass 18, count 2 2006.173.19:35:06.04#ibcon#read 3, iclass 18, count 2 2006.173.19:35:06.04#ibcon#about to read 4, iclass 18, count 2 2006.173.19:35:06.04#ibcon#read 4, iclass 18, count 2 2006.173.19:35:06.04#ibcon#about to read 5, iclass 18, count 2 2006.173.19:35:06.04#ibcon#read 5, iclass 18, count 2 2006.173.19:35:06.04#ibcon#about to read 6, iclass 18, count 2 2006.173.19:35:06.04#ibcon#read 6, iclass 18, count 2 2006.173.19:35:06.04#ibcon#end of sib2, iclass 18, count 2 2006.173.19:35:06.04#ibcon#*after write, iclass 18, count 2 2006.173.19:35:06.04#ibcon#*before return 0, iclass 18, count 2 2006.173.19:35:06.04#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.19:35:06.04#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.19:35:06.04#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.19:35:06.04#ibcon#ireg 7 cls_cnt 0 2006.173.19:35:06.04#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.19:35:06.11#abcon#<5=/00 0.1 0.4 19.351001002.5\r\n> 2006.173.19:35:06.13#abcon#{5=INTERFACE CLEAR} 2006.173.19:35:06.16#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.19:35:06.16#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.19:35:06.16#ibcon#enter wrdev, iclass 18, count 0 2006.173.19:35:06.16#ibcon#first serial, iclass 18, count 0 2006.173.19:35:06.16#ibcon#enter sib2, iclass 18, count 0 2006.173.19:35:06.16#ibcon#flushed, iclass 18, count 0 2006.173.19:35:06.16#ibcon#about to write, iclass 18, count 0 2006.173.19:35:06.16#ibcon#wrote, iclass 18, count 0 2006.173.19:35:06.16#ibcon#about to read 3, iclass 18, count 0 2006.173.19:35:06.18#ibcon#read 3, iclass 18, count 0 2006.173.19:35:06.18#ibcon#about to read 4, iclass 18, count 0 2006.173.19:35:06.18#ibcon#read 4, iclass 18, count 0 2006.173.19:35:06.18#ibcon#about to read 5, iclass 18, count 0 2006.173.19:35:06.18#ibcon#read 5, iclass 18, count 0 2006.173.19:35:06.18#ibcon#about to read 6, iclass 18, count 0 2006.173.19:35:06.18#ibcon#read 6, iclass 18, count 0 2006.173.19:35:06.18#ibcon#end of sib2, iclass 18, count 0 2006.173.19:35:06.18#ibcon#*mode == 0, iclass 18, count 0 2006.173.19:35:06.18#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.19:35:06.18#ibcon#[25=USB\r\n] 2006.173.19:35:06.18#ibcon#*before write, iclass 18, count 0 2006.173.19:35:06.18#ibcon#enter sib2, iclass 18, count 0 2006.173.19:35:06.18#ibcon#flushed, iclass 18, count 0 2006.173.19:35:06.18#ibcon#about to write, iclass 18, count 0 2006.173.19:35:06.18#ibcon#wrote, iclass 18, count 0 2006.173.19:35:06.18#ibcon#about to read 3, iclass 18, count 0 2006.173.19:35:06.19#abcon#[5=S1D000X0/0*\r\n] 2006.173.19:35:06.21#ibcon#read 3, iclass 18, count 0 2006.173.19:35:06.21#ibcon#about to read 4, iclass 18, count 0 2006.173.19:35:06.21#ibcon#read 4, iclass 18, count 0 2006.173.19:35:06.21#ibcon#about to read 5, iclass 18, count 0 2006.173.19:35:06.21#ibcon#read 5, iclass 18, count 0 2006.173.19:35:06.21#ibcon#about to read 6, iclass 18, count 0 2006.173.19:35:06.21#ibcon#read 6, iclass 18, count 0 2006.173.19:35:06.21#ibcon#end of sib2, iclass 18, count 0 2006.173.19:35:06.21#ibcon#*after write, iclass 18, count 0 2006.173.19:35:06.21#ibcon#*before return 0, iclass 18, count 0 2006.173.19:35:06.21#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.19:35:06.21#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.19:35:06.21#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.19:35:06.21#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.19:35:06.21$vck44/valo=7,864.99 2006.173.19:35:06.21#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.19:35:06.21#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.19:35:06.21#ibcon#ireg 17 cls_cnt 0 2006.173.19:35:06.21#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.19:35:06.21#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.19:35:06.21#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.19:35:06.21#ibcon#enter wrdev, iclass 24, count 0 2006.173.19:35:06.21#ibcon#first serial, iclass 24, count 0 2006.173.19:35:06.21#ibcon#enter sib2, iclass 24, count 0 2006.173.19:35:06.21#ibcon#flushed, iclass 24, count 0 2006.173.19:35:06.21#ibcon#about to write, iclass 24, count 0 2006.173.19:35:06.21#ibcon#wrote, iclass 24, count 0 2006.173.19:35:06.21#ibcon#about to read 3, iclass 24, count 0 2006.173.19:35:06.23#ibcon#read 3, iclass 24, count 0 2006.173.19:35:06.23#ibcon#about to read 4, iclass 24, count 0 2006.173.19:35:06.23#ibcon#read 4, iclass 24, count 0 2006.173.19:35:06.23#ibcon#about to read 5, iclass 24, count 0 2006.173.19:35:06.23#ibcon#read 5, iclass 24, count 0 2006.173.19:35:06.23#ibcon#about to read 6, iclass 24, count 0 2006.173.19:35:06.23#ibcon#read 6, iclass 24, count 0 2006.173.19:35:06.23#ibcon#end of sib2, iclass 24, count 0 2006.173.19:35:06.23#ibcon#*mode == 0, iclass 24, count 0 2006.173.19:35:06.23#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.19:35:06.23#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.19:35:06.23#ibcon#*before write, iclass 24, count 0 2006.173.19:35:06.23#ibcon#enter sib2, iclass 24, count 0 2006.173.19:35:06.23#ibcon#flushed, iclass 24, count 0 2006.173.19:35:06.23#ibcon#about to write, iclass 24, count 0 2006.173.19:35:06.23#ibcon#wrote, iclass 24, count 0 2006.173.19:35:06.23#ibcon#about to read 3, iclass 24, count 0 2006.173.19:35:06.27#ibcon#read 3, iclass 24, count 0 2006.173.19:35:06.27#ibcon#about to read 4, iclass 24, count 0 2006.173.19:35:06.27#ibcon#read 4, iclass 24, count 0 2006.173.19:35:06.27#ibcon#about to read 5, iclass 24, count 0 2006.173.19:35:06.27#ibcon#read 5, iclass 24, count 0 2006.173.19:35:06.27#ibcon#about to read 6, iclass 24, count 0 2006.173.19:35:06.27#ibcon#read 6, iclass 24, count 0 2006.173.19:35:06.27#ibcon#end of sib2, iclass 24, count 0 2006.173.19:35:06.27#ibcon#*after write, iclass 24, count 0 2006.173.19:35:06.27#ibcon#*before return 0, iclass 24, count 0 2006.173.19:35:06.27#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.19:35:06.27#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.19:35:06.27#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.19:35:06.27#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.19:35:06.27$vck44/va=7,4 2006.173.19:35:06.27#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.19:35:06.27#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.19:35:06.27#ibcon#ireg 11 cls_cnt 2 2006.173.19:35:06.27#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.19:35:06.33#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.19:35:06.33#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.19:35:06.33#ibcon#enter wrdev, iclass 26, count 2 2006.173.19:35:06.33#ibcon#first serial, iclass 26, count 2 2006.173.19:35:06.33#ibcon#enter sib2, iclass 26, count 2 2006.173.19:35:06.33#ibcon#flushed, iclass 26, count 2 2006.173.19:35:06.33#ibcon#about to write, iclass 26, count 2 2006.173.19:35:06.33#ibcon#wrote, iclass 26, count 2 2006.173.19:35:06.33#ibcon#about to read 3, iclass 26, count 2 2006.173.19:35:06.35#ibcon#read 3, iclass 26, count 2 2006.173.19:35:06.35#ibcon#about to read 4, iclass 26, count 2 2006.173.19:35:06.35#ibcon#read 4, iclass 26, count 2 2006.173.19:35:06.35#ibcon#about to read 5, iclass 26, count 2 2006.173.19:35:06.35#ibcon#read 5, iclass 26, count 2 2006.173.19:35:06.35#ibcon#about to read 6, iclass 26, count 2 2006.173.19:35:06.35#ibcon#read 6, iclass 26, count 2 2006.173.19:35:06.35#ibcon#end of sib2, iclass 26, count 2 2006.173.19:35:06.35#ibcon#*mode == 0, iclass 26, count 2 2006.173.19:35:06.35#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.19:35:06.35#ibcon#[25=AT07-04\r\n] 2006.173.19:35:06.35#ibcon#*before write, iclass 26, count 2 2006.173.19:35:06.35#ibcon#enter sib2, iclass 26, count 2 2006.173.19:35:06.35#ibcon#flushed, iclass 26, count 2 2006.173.19:35:06.35#ibcon#about to write, iclass 26, count 2 2006.173.19:35:06.35#ibcon#wrote, iclass 26, count 2 2006.173.19:35:06.35#ibcon#about to read 3, iclass 26, count 2 2006.173.19:35:06.38#ibcon#read 3, iclass 26, count 2 2006.173.19:35:06.38#ibcon#about to read 4, iclass 26, count 2 2006.173.19:35:06.38#ibcon#read 4, iclass 26, count 2 2006.173.19:35:06.38#ibcon#about to read 5, iclass 26, count 2 2006.173.19:35:06.38#ibcon#read 5, iclass 26, count 2 2006.173.19:35:06.38#ibcon#about to read 6, iclass 26, count 2 2006.173.19:35:06.38#ibcon#read 6, iclass 26, count 2 2006.173.19:35:06.38#ibcon#end of sib2, iclass 26, count 2 2006.173.19:35:06.38#ibcon#*after write, iclass 26, count 2 2006.173.19:35:06.38#ibcon#*before return 0, iclass 26, count 2 2006.173.19:35:06.38#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.19:35:06.38#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.19:35:06.38#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.19:35:06.38#ibcon#ireg 7 cls_cnt 0 2006.173.19:35:06.38#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.19:35:06.50#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.19:35:06.50#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.19:35:06.50#ibcon#enter wrdev, iclass 26, count 0 2006.173.19:35:06.50#ibcon#first serial, iclass 26, count 0 2006.173.19:35:06.50#ibcon#enter sib2, iclass 26, count 0 2006.173.19:35:06.50#ibcon#flushed, iclass 26, count 0 2006.173.19:35:06.50#ibcon#about to write, iclass 26, count 0 2006.173.19:35:06.50#ibcon#wrote, iclass 26, count 0 2006.173.19:35:06.50#ibcon#about to read 3, iclass 26, count 0 2006.173.19:35:06.52#ibcon#read 3, iclass 26, count 0 2006.173.19:35:06.52#ibcon#about to read 4, iclass 26, count 0 2006.173.19:35:06.52#ibcon#read 4, iclass 26, count 0 2006.173.19:35:06.52#ibcon#about to read 5, iclass 26, count 0 2006.173.19:35:06.52#ibcon#read 5, iclass 26, count 0 2006.173.19:35:06.52#ibcon#about to read 6, iclass 26, count 0 2006.173.19:35:06.52#ibcon#read 6, iclass 26, count 0 2006.173.19:35:06.52#ibcon#end of sib2, iclass 26, count 0 2006.173.19:35:06.52#ibcon#*mode == 0, iclass 26, count 0 2006.173.19:35:06.52#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.19:35:06.52#ibcon#[25=USB\r\n] 2006.173.19:35:06.52#ibcon#*before write, iclass 26, count 0 2006.173.19:35:06.52#ibcon#enter sib2, iclass 26, count 0 2006.173.19:35:06.52#ibcon#flushed, iclass 26, count 0 2006.173.19:35:06.52#ibcon#about to write, iclass 26, count 0 2006.173.19:35:06.52#ibcon#wrote, iclass 26, count 0 2006.173.19:35:06.52#ibcon#about to read 3, iclass 26, count 0 2006.173.19:35:06.55#ibcon#read 3, iclass 26, count 0 2006.173.19:35:06.55#ibcon#about to read 4, iclass 26, count 0 2006.173.19:35:06.55#ibcon#read 4, iclass 26, count 0 2006.173.19:35:06.55#ibcon#about to read 5, iclass 26, count 0 2006.173.19:35:06.55#ibcon#read 5, iclass 26, count 0 2006.173.19:35:06.55#ibcon#about to read 6, iclass 26, count 0 2006.173.19:35:06.55#ibcon#read 6, iclass 26, count 0 2006.173.19:35:06.55#ibcon#end of sib2, iclass 26, count 0 2006.173.19:35:06.55#ibcon#*after write, iclass 26, count 0 2006.173.19:35:06.55#ibcon#*before return 0, iclass 26, count 0 2006.173.19:35:06.55#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.19:35:06.55#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.19:35:06.55#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.19:35:06.55#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.19:35:06.55$vck44/valo=8,884.99 2006.173.19:35:06.55#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.19:35:06.55#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.19:35:06.55#ibcon#ireg 17 cls_cnt 0 2006.173.19:35:06.55#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.19:35:06.55#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.19:35:06.55#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.19:35:06.55#ibcon#enter wrdev, iclass 28, count 0 2006.173.19:35:06.55#ibcon#first serial, iclass 28, count 0 2006.173.19:35:06.55#ibcon#enter sib2, iclass 28, count 0 2006.173.19:35:06.55#ibcon#flushed, iclass 28, count 0 2006.173.19:35:06.55#ibcon#about to write, iclass 28, count 0 2006.173.19:35:06.55#ibcon#wrote, iclass 28, count 0 2006.173.19:35:06.55#ibcon#about to read 3, iclass 28, count 0 2006.173.19:35:06.57#ibcon#read 3, iclass 28, count 0 2006.173.19:35:06.57#ibcon#about to read 4, iclass 28, count 0 2006.173.19:35:06.57#ibcon#read 4, iclass 28, count 0 2006.173.19:35:06.57#ibcon#about to read 5, iclass 28, count 0 2006.173.19:35:06.57#ibcon#read 5, iclass 28, count 0 2006.173.19:35:06.57#ibcon#about to read 6, iclass 28, count 0 2006.173.19:35:06.57#ibcon#read 6, iclass 28, count 0 2006.173.19:35:06.57#ibcon#end of sib2, iclass 28, count 0 2006.173.19:35:06.57#ibcon#*mode == 0, iclass 28, count 0 2006.173.19:35:06.57#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.19:35:06.57#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.19:35:06.57#ibcon#*before write, iclass 28, count 0 2006.173.19:35:06.57#ibcon#enter sib2, iclass 28, count 0 2006.173.19:35:06.57#ibcon#flushed, iclass 28, count 0 2006.173.19:35:06.57#ibcon#about to write, iclass 28, count 0 2006.173.19:35:06.57#ibcon#wrote, iclass 28, count 0 2006.173.19:35:06.57#ibcon#about to read 3, iclass 28, count 0 2006.173.19:35:06.61#ibcon#read 3, iclass 28, count 0 2006.173.19:35:06.61#ibcon#about to read 4, iclass 28, count 0 2006.173.19:35:06.61#ibcon#read 4, iclass 28, count 0 2006.173.19:35:06.61#ibcon#about to read 5, iclass 28, count 0 2006.173.19:35:06.61#ibcon#read 5, iclass 28, count 0 2006.173.19:35:06.61#ibcon#about to read 6, iclass 28, count 0 2006.173.19:35:06.61#ibcon#read 6, iclass 28, count 0 2006.173.19:35:06.61#ibcon#end of sib2, iclass 28, count 0 2006.173.19:35:06.61#ibcon#*after write, iclass 28, count 0 2006.173.19:35:06.61#ibcon#*before return 0, iclass 28, count 0 2006.173.19:35:06.61#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.19:35:06.61#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.19:35:06.61#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.19:35:06.61#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.19:35:06.61$vck44/va=8,4 2006.173.19:35:06.61#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.19:35:06.61#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.19:35:06.61#ibcon#ireg 11 cls_cnt 2 2006.173.19:35:06.61#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.19:35:06.67#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.19:35:06.67#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.19:35:06.67#ibcon#enter wrdev, iclass 30, count 2 2006.173.19:35:06.67#ibcon#first serial, iclass 30, count 2 2006.173.19:35:06.67#ibcon#enter sib2, iclass 30, count 2 2006.173.19:35:06.67#ibcon#flushed, iclass 30, count 2 2006.173.19:35:06.67#ibcon#about to write, iclass 30, count 2 2006.173.19:35:06.67#ibcon#wrote, iclass 30, count 2 2006.173.19:35:06.67#ibcon#about to read 3, iclass 30, count 2 2006.173.19:35:06.69#ibcon#read 3, iclass 30, count 2 2006.173.19:35:06.69#ibcon#about to read 4, iclass 30, count 2 2006.173.19:35:06.69#ibcon#read 4, iclass 30, count 2 2006.173.19:35:06.69#ibcon#about to read 5, iclass 30, count 2 2006.173.19:35:06.69#ibcon#read 5, iclass 30, count 2 2006.173.19:35:06.69#ibcon#about to read 6, iclass 30, count 2 2006.173.19:35:06.69#ibcon#read 6, iclass 30, count 2 2006.173.19:35:06.69#ibcon#end of sib2, iclass 30, count 2 2006.173.19:35:06.69#ibcon#*mode == 0, iclass 30, count 2 2006.173.19:35:06.69#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.19:35:06.69#ibcon#[25=AT08-04\r\n] 2006.173.19:35:06.69#ibcon#*before write, iclass 30, count 2 2006.173.19:35:06.69#ibcon#enter sib2, iclass 30, count 2 2006.173.19:35:06.69#ibcon#flushed, iclass 30, count 2 2006.173.19:35:06.69#ibcon#about to write, iclass 30, count 2 2006.173.19:35:06.69#ibcon#wrote, iclass 30, count 2 2006.173.19:35:06.69#ibcon#about to read 3, iclass 30, count 2 2006.173.19:35:06.72#ibcon#read 3, iclass 30, count 2 2006.173.19:35:06.72#ibcon#about to read 4, iclass 30, count 2 2006.173.19:35:06.72#ibcon#read 4, iclass 30, count 2 2006.173.19:35:06.72#ibcon#about to read 5, iclass 30, count 2 2006.173.19:35:06.72#ibcon#read 5, iclass 30, count 2 2006.173.19:35:06.72#ibcon#about to read 6, iclass 30, count 2 2006.173.19:35:06.72#ibcon#read 6, iclass 30, count 2 2006.173.19:35:06.72#ibcon#end of sib2, iclass 30, count 2 2006.173.19:35:06.72#ibcon#*after write, iclass 30, count 2 2006.173.19:35:06.72#ibcon#*before return 0, iclass 30, count 2 2006.173.19:35:06.72#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.19:35:06.72#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.19:35:06.72#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.19:35:06.72#ibcon#ireg 7 cls_cnt 0 2006.173.19:35:06.72#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.19:35:06.84#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.19:35:06.84#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.19:35:06.84#ibcon#enter wrdev, iclass 30, count 0 2006.173.19:35:06.84#ibcon#first serial, iclass 30, count 0 2006.173.19:35:06.84#ibcon#enter sib2, iclass 30, count 0 2006.173.19:35:06.84#ibcon#flushed, iclass 30, count 0 2006.173.19:35:06.84#ibcon#about to write, iclass 30, count 0 2006.173.19:35:06.84#ibcon#wrote, iclass 30, count 0 2006.173.19:35:06.84#ibcon#about to read 3, iclass 30, count 0 2006.173.19:35:06.86#ibcon#read 3, iclass 30, count 0 2006.173.19:35:06.86#ibcon#about to read 4, iclass 30, count 0 2006.173.19:35:06.86#ibcon#read 4, iclass 30, count 0 2006.173.19:35:06.86#ibcon#about to read 5, iclass 30, count 0 2006.173.19:35:06.86#ibcon#read 5, iclass 30, count 0 2006.173.19:35:06.86#ibcon#about to read 6, iclass 30, count 0 2006.173.19:35:06.86#ibcon#read 6, iclass 30, count 0 2006.173.19:35:06.86#ibcon#end of sib2, iclass 30, count 0 2006.173.19:35:06.86#ibcon#*mode == 0, iclass 30, count 0 2006.173.19:35:06.86#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.19:35:06.86#ibcon#[25=USB\r\n] 2006.173.19:35:06.86#ibcon#*before write, iclass 30, count 0 2006.173.19:35:06.86#ibcon#enter sib2, iclass 30, count 0 2006.173.19:35:06.86#ibcon#flushed, iclass 30, count 0 2006.173.19:35:06.86#ibcon#about to write, iclass 30, count 0 2006.173.19:35:06.86#ibcon#wrote, iclass 30, count 0 2006.173.19:35:06.86#ibcon#about to read 3, iclass 30, count 0 2006.173.19:35:06.89#ibcon#read 3, iclass 30, count 0 2006.173.19:35:06.89#ibcon#about to read 4, iclass 30, count 0 2006.173.19:35:06.89#ibcon#read 4, iclass 30, count 0 2006.173.19:35:06.89#ibcon#about to read 5, iclass 30, count 0 2006.173.19:35:06.89#ibcon#read 5, iclass 30, count 0 2006.173.19:35:06.89#ibcon#about to read 6, iclass 30, count 0 2006.173.19:35:06.89#ibcon#read 6, iclass 30, count 0 2006.173.19:35:06.89#ibcon#end of sib2, iclass 30, count 0 2006.173.19:35:06.89#ibcon#*after write, iclass 30, count 0 2006.173.19:35:06.89#ibcon#*before return 0, iclass 30, count 0 2006.173.19:35:06.89#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.19:35:06.89#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.19:35:06.89#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.19:35:06.89#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.19:35:06.89$vck44/vblo=1,629.99 2006.173.19:35:06.89#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.19:35:06.89#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.19:35:06.89#ibcon#ireg 17 cls_cnt 0 2006.173.19:35:06.89#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.19:35:06.89#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.19:35:06.89#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.19:35:06.89#ibcon#enter wrdev, iclass 32, count 0 2006.173.19:35:06.89#ibcon#first serial, iclass 32, count 0 2006.173.19:35:06.89#ibcon#enter sib2, iclass 32, count 0 2006.173.19:35:06.89#ibcon#flushed, iclass 32, count 0 2006.173.19:35:06.89#ibcon#about to write, iclass 32, count 0 2006.173.19:35:06.89#ibcon#wrote, iclass 32, count 0 2006.173.19:35:06.89#ibcon#about to read 3, iclass 32, count 0 2006.173.19:35:06.91#ibcon#read 3, iclass 32, count 0 2006.173.19:35:06.91#ibcon#about to read 4, iclass 32, count 0 2006.173.19:35:06.91#ibcon#read 4, iclass 32, count 0 2006.173.19:35:06.91#ibcon#about to read 5, iclass 32, count 0 2006.173.19:35:06.91#ibcon#read 5, iclass 32, count 0 2006.173.19:35:06.91#ibcon#about to read 6, iclass 32, count 0 2006.173.19:35:06.91#ibcon#read 6, iclass 32, count 0 2006.173.19:35:06.91#ibcon#end of sib2, iclass 32, count 0 2006.173.19:35:06.91#ibcon#*mode == 0, iclass 32, count 0 2006.173.19:35:06.91#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.19:35:06.91#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.19:35:06.91#ibcon#*before write, iclass 32, count 0 2006.173.19:35:06.91#ibcon#enter sib2, iclass 32, count 0 2006.173.19:35:06.91#ibcon#flushed, iclass 32, count 0 2006.173.19:35:06.91#ibcon#about to write, iclass 32, count 0 2006.173.19:35:06.91#ibcon#wrote, iclass 32, count 0 2006.173.19:35:06.91#ibcon#about to read 3, iclass 32, count 0 2006.173.19:35:06.95#ibcon#read 3, iclass 32, count 0 2006.173.19:35:06.95#ibcon#about to read 4, iclass 32, count 0 2006.173.19:35:06.95#ibcon#read 4, iclass 32, count 0 2006.173.19:35:06.95#ibcon#about to read 5, iclass 32, count 0 2006.173.19:35:06.95#ibcon#read 5, iclass 32, count 0 2006.173.19:35:06.95#ibcon#about to read 6, iclass 32, count 0 2006.173.19:35:06.95#ibcon#read 6, iclass 32, count 0 2006.173.19:35:06.95#ibcon#end of sib2, iclass 32, count 0 2006.173.19:35:06.95#ibcon#*after write, iclass 32, count 0 2006.173.19:35:06.95#ibcon#*before return 0, iclass 32, count 0 2006.173.19:35:06.95#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.19:35:06.95#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.19:35:06.95#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.19:35:06.95#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.19:35:06.95$vck44/vb=1,4 2006.173.19:35:06.95#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.19:35:06.95#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.19:35:06.95#ibcon#ireg 11 cls_cnt 2 2006.173.19:35:06.95#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.19:35:06.95#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.19:35:06.95#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.19:35:06.95#ibcon#enter wrdev, iclass 34, count 2 2006.173.19:35:06.95#ibcon#first serial, iclass 34, count 2 2006.173.19:35:06.95#ibcon#enter sib2, iclass 34, count 2 2006.173.19:35:06.95#ibcon#flushed, iclass 34, count 2 2006.173.19:35:06.95#ibcon#about to write, iclass 34, count 2 2006.173.19:35:06.95#ibcon#wrote, iclass 34, count 2 2006.173.19:35:06.95#ibcon#about to read 3, iclass 34, count 2 2006.173.19:35:06.97#ibcon#read 3, iclass 34, count 2 2006.173.19:35:06.97#ibcon#about to read 4, iclass 34, count 2 2006.173.19:35:06.97#ibcon#read 4, iclass 34, count 2 2006.173.19:35:06.97#ibcon#about to read 5, iclass 34, count 2 2006.173.19:35:06.97#ibcon#read 5, iclass 34, count 2 2006.173.19:35:06.97#ibcon#about to read 6, iclass 34, count 2 2006.173.19:35:06.97#ibcon#read 6, iclass 34, count 2 2006.173.19:35:06.97#ibcon#end of sib2, iclass 34, count 2 2006.173.19:35:06.97#ibcon#*mode == 0, iclass 34, count 2 2006.173.19:35:06.97#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.19:35:06.97#ibcon#[27=AT01-04\r\n] 2006.173.19:35:06.97#ibcon#*before write, iclass 34, count 2 2006.173.19:35:06.97#ibcon#enter sib2, iclass 34, count 2 2006.173.19:35:06.97#ibcon#flushed, iclass 34, count 2 2006.173.19:35:06.97#ibcon#about to write, iclass 34, count 2 2006.173.19:35:06.97#ibcon#wrote, iclass 34, count 2 2006.173.19:35:06.97#ibcon#about to read 3, iclass 34, count 2 2006.173.19:35:07.00#ibcon#read 3, iclass 34, count 2 2006.173.19:35:07.00#ibcon#about to read 4, iclass 34, count 2 2006.173.19:35:07.00#ibcon#read 4, iclass 34, count 2 2006.173.19:35:07.00#ibcon#about to read 5, iclass 34, count 2 2006.173.19:35:07.00#ibcon#read 5, iclass 34, count 2 2006.173.19:35:07.00#ibcon#about to read 6, iclass 34, count 2 2006.173.19:35:07.00#ibcon#read 6, iclass 34, count 2 2006.173.19:35:07.00#ibcon#end of sib2, iclass 34, count 2 2006.173.19:35:07.00#ibcon#*after write, iclass 34, count 2 2006.173.19:35:07.00#ibcon#*before return 0, iclass 34, count 2 2006.173.19:35:07.00#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.19:35:07.00#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.19:35:07.00#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.19:35:07.00#ibcon#ireg 7 cls_cnt 0 2006.173.19:35:07.00#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.19:35:07.12#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.19:35:07.12#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.19:35:07.12#ibcon#enter wrdev, iclass 34, count 0 2006.173.19:35:07.12#ibcon#first serial, iclass 34, count 0 2006.173.19:35:07.12#ibcon#enter sib2, iclass 34, count 0 2006.173.19:35:07.12#ibcon#flushed, iclass 34, count 0 2006.173.19:35:07.12#ibcon#about to write, iclass 34, count 0 2006.173.19:35:07.12#ibcon#wrote, iclass 34, count 0 2006.173.19:35:07.12#ibcon#about to read 3, iclass 34, count 0 2006.173.19:35:07.14#ibcon#read 3, iclass 34, count 0 2006.173.19:35:07.14#ibcon#about to read 4, iclass 34, count 0 2006.173.19:35:07.14#ibcon#read 4, iclass 34, count 0 2006.173.19:35:07.14#ibcon#about to read 5, iclass 34, count 0 2006.173.19:35:07.14#ibcon#read 5, iclass 34, count 0 2006.173.19:35:07.14#ibcon#about to read 6, iclass 34, count 0 2006.173.19:35:07.14#ibcon#read 6, iclass 34, count 0 2006.173.19:35:07.14#ibcon#end of sib2, iclass 34, count 0 2006.173.19:35:07.14#ibcon#*mode == 0, iclass 34, count 0 2006.173.19:35:07.14#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.19:35:07.14#ibcon#[27=USB\r\n] 2006.173.19:35:07.14#ibcon#*before write, iclass 34, count 0 2006.173.19:35:07.14#ibcon#enter sib2, iclass 34, count 0 2006.173.19:35:07.14#ibcon#flushed, iclass 34, count 0 2006.173.19:35:07.14#ibcon#about to write, iclass 34, count 0 2006.173.19:35:07.14#ibcon#wrote, iclass 34, count 0 2006.173.19:35:07.14#ibcon#about to read 3, iclass 34, count 0 2006.173.19:35:07.17#ibcon#read 3, iclass 34, count 0 2006.173.19:35:07.17#ibcon#about to read 4, iclass 34, count 0 2006.173.19:35:07.17#ibcon#read 4, iclass 34, count 0 2006.173.19:35:07.17#ibcon#about to read 5, iclass 34, count 0 2006.173.19:35:07.17#ibcon#read 5, iclass 34, count 0 2006.173.19:35:07.17#ibcon#about to read 6, iclass 34, count 0 2006.173.19:35:07.17#ibcon#read 6, iclass 34, count 0 2006.173.19:35:07.17#ibcon#end of sib2, iclass 34, count 0 2006.173.19:35:07.17#ibcon#*after write, iclass 34, count 0 2006.173.19:35:07.17#ibcon#*before return 0, iclass 34, count 0 2006.173.19:35:07.17#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.19:35:07.17#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.19:35:07.17#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.19:35:07.17#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.19:35:07.17$vck44/vblo=2,634.99 2006.173.19:35:07.17#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.19:35:07.17#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.19:35:07.17#ibcon#ireg 17 cls_cnt 0 2006.173.19:35:07.17#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.19:35:07.17#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.19:35:07.17#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.19:35:07.17#ibcon#enter wrdev, iclass 36, count 0 2006.173.19:35:07.17#ibcon#first serial, iclass 36, count 0 2006.173.19:35:07.17#ibcon#enter sib2, iclass 36, count 0 2006.173.19:35:07.17#ibcon#flushed, iclass 36, count 0 2006.173.19:35:07.17#ibcon#about to write, iclass 36, count 0 2006.173.19:35:07.17#ibcon#wrote, iclass 36, count 0 2006.173.19:35:07.17#ibcon#about to read 3, iclass 36, count 0 2006.173.19:35:07.19#ibcon#read 3, iclass 36, count 0 2006.173.19:35:07.19#ibcon#about to read 4, iclass 36, count 0 2006.173.19:35:07.19#ibcon#read 4, iclass 36, count 0 2006.173.19:35:07.19#ibcon#about to read 5, iclass 36, count 0 2006.173.19:35:07.19#ibcon#read 5, iclass 36, count 0 2006.173.19:35:07.19#ibcon#about to read 6, iclass 36, count 0 2006.173.19:35:07.19#ibcon#read 6, iclass 36, count 0 2006.173.19:35:07.19#ibcon#end of sib2, iclass 36, count 0 2006.173.19:35:07.19#ibcon#*mode == 0, iclass 36, count 0 2006.173.19:35:07.19#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.19:35:07.19#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.19:35:07.19#ibcon#*before write, iclass 36, count 0 2006.173.19:35:07.19#ibcon#enter sib2, iclass 36, count 0 2006.173.19:35:07.19#ibcon#flushed, iclass 36, count 0 2006.173.19:35:07.19#ibcon#about to write, iclass 36, count 0 2006.173.19:35:07.19#ibcon#wrote, iclass 36, count 0 2006.173.19:35:07.19#ibcon#about to read 3, iclass 36, count 0 2006.173.19:35:07.23#ibcon#read 3, iclass 36, count 0 2006.173.19:35:07.23#ibcon#about to read 4, iclass 36, count 0 2006.173.19:35:07.23#ibcon#read 4, iclass 36, count 0 2006.173.19:35:07.23#ibcon#about to read 5, iclass 36, count 0 2006.173.19:35:07.23#ibcon#read 5, iclass 36, count 0 2006.173.19:35:07.23#ibcon#about to read 6, iclass 36, count 0 2006.173.19:35:07.23#ibcon#read 6, iclass 36, count 0 2006.173.19:35:07.23#ibcon#end of sib2, iclass 36, count 0 2006.173.19:35:07.23#ibcon#*after write, iclass 36, count 0 2006.173.19:35:07.23#ibcon#*before return 0, iclass 36, count 0 2006.173.19:35:07.23#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.19:35:07.23#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.19:35:07.23#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.19:35:07.23#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.19:35:07.23$vck44/vb=2,4 2006.173.19:35:07.23#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.19:35:07.23#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.19:35:07.23#ibcon#ireg 11 cls_cnt 2 2006.173.19:35:07.23#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.19:35:07.29#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.19:35:07.29#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.19:35:07.29#ibcon#enter wrdev, iclass 38, count 2 2006.173.19:35:07.29#ibcon#first serial, iclass 38, count 2 2006.173.19:35:07.29#ibcon#enter sib2, iclass 38, count 2 2006.173.19:35:07.29#ibcon#flushed, iclass 38, count 2 2006.173.19:35:07.29#ibcon#about to write, iclass 38, count 2 2006.173.19:35:07.29#ibcon#wrote, iclass 38, count 2 2006.173.19:35:07.29#ibcon#about to read 3, iclass 38, count 2 2006.173.19:35:07.31#ibcon#read 3, iclass 38, count 2 2006.173.19:35:07.31#ibcon#about to read 4, iclass 38, count 2 2006.173.19:35:07.31#ibcon#read 4, iclass 38, count 2 2006.173.19:35:07.31#ibcon#about to read 5, iclass 38, count 2 2006.173.19:35:07.31#ibcon#read 5, iclass 38, count 2 2006.173.19:35:07.31#ibcon#about to read 6, iclass 38, count 2 2006.173.19:35:07.31#ibcon#read 6, iclass 38, count 2 2006.173.19:35:07.31#ibcon#end of sib2, iclass 38, count 2 2006.173.19:35:07.31#ibcon#*mode == 0, iclass 38, count 2 2006.173.19:35:07.31#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.19:35:07.31#ibcon#[27=AT02-04\r\n] 2006.173.19:35:07.31#ibcon#*before write, iclass 38, count 2 2006.173.19:35:07.31#ibcon#enter sib2, iclass 38, count 2 2006.173.19:35:07.31#ibcon#flushed, iclass 38, count 2 2006.173.19:35:07.31#ibcon#about to write, iclass 38, count 2 2006.173.19:35:07.31#ibcon#wrote, iclass 38, count 2 2006.173.19:35:07.31#ibcon#about to read 3, iclass 38, count 2 2006.173.19:35:07.34#ibcon#read 3, iclass 38, count 2 2006.173.19:35:07.34#ibcon#about to read 4, iclass 38, count 2 2006.173.19:35:07.34#ibcon#read 4, iclass 38, count 2 2006.173.19:35:07.34#ibcon#about to read 5, iclass 38, count 2 2006.173.19:35:07.34#ibcon#read 5, iclass 38, count 2 2006.173.19:35:07.34#ibcon#about to read 6, iclass 38, count 2 2006.173.19:35:07.34#ibcon#read 6, iclass 38, count 2 2006.173.19:35:07.34#ibcon#end of sib2, iclass 38, count 2 2006.173.19:35:07.34#ibcon#*after write, iclass 38, count 2 2006.173.19:35:07.34#ibcon#*before return 0, iclass 38, count 2 2006.173.19:35:07.34#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.19:35:07.34#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.19:35:07.34#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.19:35:07.34#ibcon#ireg 7 cls_cnt 0 2006.173.19:35:07.34#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.19:35:07.46#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.19:35:07.46#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.19:35:07.46#ibcon#enter wrdev, iclass 38, count 0 2006.173.19:35:07.46#ibcon#first serial, iclass 38, count 0 2006.173.19:35:07.46#ibcon#enter sib2, iclass 38, count 0 2006.173.19:35:07.46#ibcon#flushed, iclass 38, count 0 2006.173.19:35:07.46#ibcon#about to write, iclass 38, count 0 2006.173.19:35:07.46#ibcon#wrote, iclass 38, count 0 2006.173.19:35:07.46#ibcon#about to read 3, iclass 38, count 0 2006.173.19:35:07.48#ibcon#read 3, iclass 38, count 0 2006.173.19:35:07.48#ibcon#about to read 4, iclass 38, count 0 2006.173.19:35:07.48#ibcon#read 4, iclass 38, count 0 2006.173.19:35:07.48#ibcon#about to read 5, iclass 38, count 0 2006.173.19:35:07.48#ibcon#read 5, iclass 38, count 0 2006.173.19:35:07.48#ibcon#about to read 6, iclass 38, count 0 2006.173.19:35:07.48#ibcon#read 6, iclass 38, count 0 2006.173.19:35:07.48#ibcon#end of sib2, iclass 38, count 0 2006.173.19:35:07.48#ibcon#*mode == 0, iclass 38, count 0 2006.173.19:35:07.48#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.19:35:07.48#ibcon#[27=USB\r\n] 2006.173.19:35:07.48#ibcon#*before write, iclass 38, count 0 2006.173.19:35:07.48#ibcon#enter sib2, iclass 38, count 0 2006.173.19:35:07.48#ibcon#flushed, iclass 38, count 0 2006.173.19:35:07.48#ibcon#about to write, iclass 38, count 0 2006.173.19:35:07.48#ibcon#wrote, iclass 38, count 0 2006.173.19:35:07.48#ibcon#about to read 3, iclass 38, count 0 2006.173.19:35:07.51#ibcon#read 3, iclass 38, count 0 2006.173.19:35:07.51#ibcon#about to read 4, iclass 38, count 0 2006.173.19:35:07.51#ibcon#read 4, iclass 38, count 0 2006.173.19:35:07.51#ibcon#about to read 5, iclass 38, count 0 2006.173.19:35:07.51#ibcon#read 5, iclass 38, count 0 2006.173.19:35:07.51#ibcon#about to read 6, iclass 38, count 0 2006.173.19:35:07.51#ibcon#read 6, iclass 38, count 0 2006.173.19:35:07.51#ibcon#end of sib2, iclass 38, count 0 2006.173.19:35:07.51#ibcon#*after write, iclass 38, count 0 2006.173.19:35:07.51#ibcon#*before return 0, iclass 38, count 0 2006.173.19:35:07.51#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.19:35:07.51#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.19:35:07.51#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.19:35:07.51#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.19:35:07.51$vck44/vblo=3,649.99 2006.173.19:35:07.51#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.19:35:07.51#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.19:35:07.51#ibcon#ireg 17 cls_cnt 0 2006.173.19:35:07.51#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.19:35:07.51#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.19:35:07.51#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.19:35:07.51#ibcon#enter wrdev, iclass 40, count 0 2006.173.19:35:07.51#ibcon#first serial, iclass 40, count 0 2006.173.19:35:07.51#ibcon#enter sib2, iclass 40, count 0 2006.173.19:35:07.51#ibcon#flushed, iclass 40, count 0 2006.173.19:35:07.51#ibcon#about to write, iclass 40, count 0 2006.173.19:35:07.51#ibcon#wrote, iclass 40, count 0 2006.173.19:35:07.51#ibcon#about to read 3, iclass 40, count 0 2006.173.19:35:07.53#ibcon#read 3, iclass 40, count 0 2006.173.19:35:07.53#ibcon#about to read 4, iclass 40, count 0 2006.173.19:35:07.53#ibcon#read 4, iclass 40, count 0 2006.173.19:35:07.53#ibcon#about to read 5, iclass 40, count 0 2006.173.19:35:07.53#ibcon#read 5, iclass 40, count 0 2006.173.19:35:07.53#ibcon#about to read 6, iclass 40, count 0 2006.173.19:35:07.53#ibcon#read 6, iclass 40, count 0 2006.173.19:35:07.53#ibcon#end of sib2, iclass 40, count 0 2006.173.19:35:07.53#ibcon#*mode == 0, iclass 40, count 0 2006.173.19:35:07.53#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.19:35:07.53#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.19:35:07.53#ibcon#*before write, iclass 40, count 0 2006.173.19:35:07.53#ibcon#enter sib2, iclass 40, count 0 2006.173.19:35:07.53#ibcon#flushed, iclass 40, count 0 2006.173.19:35:07.53#ibcon#about to write, iclass 40, count 0 2006.173.19:35:07.53#ibcon#wrote, iclass 40, count 0 2006.173.19:35:07.53#ibcon#about to read 3, iclass 40, count 0 2006.173.19:35:07.57#ibcon#read 3, iclass 40, count 0 2006.173.19:35:07.57#ibcon#about to read 4, iclass 40, count 0 2006.173.19:35:07.57#ibcon#read 4, iclass 40, count 0 2006.173.19:35:07.57#ibcon#about to read 5, iclass 40, count 0 2006.173.19:35:07.57#ibcon#read 5, iclass 40, count 0 2006.173.19:35:07.57#ibcon#about to read 6, iclass 40, count 0 2006.173.19:35:07.57#ibcon#read 6, iclass 40, count 0 2006.173.19:35:07.57#ibcon#end of sib2, iclass 40, count 0 2006.173.19:35:07.57#ibcon#*after write, iclass 40, count 0 2006.173.19:35:07.57#ibcon#*before return 0, iclass 40, count 0 2006.173.19:35:07.57#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.19:35:07.57#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.19:35:07.57#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.19:35:07.57#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.19:35:07.57$vck44/vb=3,4 2006.173.19:35:07.57#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.19:35:07.57#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.19:35:07.57#ibcon#ireg 11 cls_cnt 2 2006.173.19:35:07.57#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.19:35:07.63#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.19:35:07.63#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.19:35:07.63#ibcon#enter wrdev, iclass 4, count 2 2006.173.19:35:07.63#ibcon#first serial, iclass 4, count 2 2006.173.19:35:07.63#ibcon#enter sib2, iclass 4, count 2 2006.173.19:35:07.63#ibcon#flushed, iclass 4, count 2 2006.173.19:35:07.63#ibcon#about to write, iclass 4, count 2 2006.173.19:35:07.63#ibcon#wrote, iclass 4, count 2 2006.173.19:35:07.63#ibcon#about to read 3, iclass 4, count 2 2006.173.19:35:07.65#ibcon#read 3, iclass 4, count 2 2006.173.19:35:07.65#ibcon#about to read 4, iclass 4, count 2 2006.173.19:35:07.65#ibcon#read 4, iclass 4, count 2 2006.173.19:35:07.65#ibcon#about to read 5, iclass 4, count 2 2006.173.19:35:07.65#ibcon#read 5, iclass 4, count 2 2006.173.19:35:07.65#ibcon#about to read 6, iclass 4, count 2 2006.173.19:35:07.65#ibcon#read 6, iclass 4, count 2 2006.173.19:35:07.65#ibcon#end of sib2, iclass 4, count 2 2006.173.19:35:07.65#ibcon#*mode == 0, iclass 4, count 2 2006.173.19:35:07.65#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.19:35:07.65#ibcon#[27=AT03-04\r\n] 2006.173.19:35:07.65#ibcon#*before write, iclass 4, count 2 2006.173.19:35:07.65#ibcon#enter sib2, iclass 4, count 2 2006.173.19:35:07.65#ibcon#flushed, iclass 4, count 2 2006.173.19:35:07.65#ibcon#about to write, iclass 4, count 2 2006.173.19:35:07.65#ibcon#wrote, iclass 4, count 2 2006.173.19:35:07.65#ibcon#about to read 3, iclass 4, count 2 2006.173.19:35:07.68#ibcon#read 3, iclass 4, count 2 2006.173.19:35:07.68#ibcon#about to read 4, iclass 4, count 2 2006.173.19:35:07.68#ibcon#read 4, iclass 4, count 2 2006.173.19:35:07.68#ibcon#about to read 5, iclass 4, count 2 2006.173.19:35:07.68#ibcon#read 5, iclass 4, count 2 2006.173.19:35:07.68#ibcon#about to read 6, iclass 4, count 2 2006.173.19:35:07.68#ibcon#read 6, iclass 4, count 2 2006.173.19:35:07.68#ibcon#end of sib2, iclass 4, count 2 2006.173.19:35:07.68#ibcon#*after write, iclass 4, count 2 2006.173.19:35:07.68#ibcon#*before return 0, iclass 4, count 2 2006.173.19:35:07.68#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.19:35:07.68#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.19:35:07.68#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.19:35:07.68#ibcon#ireg 7 cls_cnt 0 2006.173.19:35:07.68#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.19:35:07.80#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.19:35:07.80#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.19:35:07.80#ibcon#enter wrdev, iclass 4, count 0 2006.173.19:35:07.80#ibcon#first serial, iclass 4, count 0 2006.173.19:35:07.80#ibcon#enter sib2, iclass 4, count 0 2006.173.19:35:07.80#ibcon#flushed, iclass 4, count 0 2006.173.19:35:07.80#ibcon#about to write, iclass 4, count 0 2006.173.19:35:07.80#ibcon#wrote, iclass 4, count 0 2006.173.19:35:07.80#ibcon#about to read 3, iclass 4, count 0 2006.173.19:35:07.82#ibcon#read 3, iclass 4, count 0 2006.173.19:35:07.82#ibcon#about to read 4, iclass 4, count 0 2006.173.19:35:07.82#ibcon#read 4, iclass 4, count 0 2006.173.19:35:07.82#ibcon#about to read 5, iclass 4, count 0 2006.173.19:35:07.82#ibcon#read 5, iclass 4, count 0 2006.173.19:35:07.82#ibcon#about to read 6, iclass 4, count 0 2006.173.19:35:07.82#ibcon#read 6, iclass 4, count 0 2006.173.19:35:07.82#ibcon#end of sib2, iclass 4, count 0 2006.173.19:35:07.82#ibcon#*mode == 0, iclass 4, count 0 2006.173.19:35:07.82#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.19:35:07.82#ibcon#[27=USB\r\n] 2006.173.19:35:07.82#ibcon#*before write, iclass 4, count 0 2006.173.19:35:07.82#ibcon#enter sib2, iclass 4, count 0 2006.173.19:35:07.82#ibcon#flushed, iclass 4, count 0 2006.173.19:35:07.82#ibcon#about to write, iclass 4, count 0 2006.173.19:35:07.82#ibcon#wrote, iclass 4, count 0 2006.173.19:35:07.82#ibcon#about to read 3, iclass 4, count 0 2006.173.19:35:07.85#ibcon#read 3, iclass 4, count 0 2006.173.19:35:07.85#ibcon#about to read 4, iclass 4, count 0 2006.173.19:35:07.85#ibcon#read 4, iclass 4, count 0 2006.173.19:35:07.85#ibcon#about to read 5, iclass 4, count 0 2006.173.19:35:07.85#ibcon#read 5, iclass 4, count 0 2006.173.19:35:07.85#ibcon#about to read 6, iclass 4, count 0 2006.173.19:35:07.85#ibcon#read 6, iclass 4, count 0 2006.173.19:35:07.85#ibcon#end of sib2, iclass 4, count 0 2006.173.19:35:07.85#ibcon#*after write, iclass 4, count 0 2006.173.19:35:07.85#ibcon#*before return 0, iclass 4, count 0 2006.173.19:35:07.85#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.19:35:07.85#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.19:35:07.85#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.19:35:07.85#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.19:35:07.85$vck44/vblo=4,679.99 2006.173.19:35:07.85#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.19:35:07.85#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.19:35:07.85#ibcon#ireg 17 cls_cnt 0 2006.173.19:35:07.85#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.19:35:07.85#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.19:35:07.85#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.19:35:07.85#ibcon#enter wrdev, iclass 6, count 0 2006.173.19:35:07.85#ibcon#first serial, iclass 6, count 0 2006.173.19:35:07.85#ibcon#enter sib2, iclass 6, count 0 2006.173.19:35:07.85#ibcon#flushed, iclass 6, count 0 2006.173.19:35:07.85#ibcon#about to write, iclass 6, count 0 2006.173.19:35:07.85#ibcon#wrote, iclass 6, count 0 2006.173.19:35:07.85#ibcon#about to read 3, iclass 6, count 0 2006.173.19:35:07.87#ibcon#read 3, iclass 6, count 0 2006.173.19:35:07.87#ibcon#about to read 4, iclass 6, count 0 2006.173.19:35:07.87#ibcon#read 4, iclass 6, count 0 2006.173.19:35:07.87#ibcon#about to read 5, iclass 6, count 0 2006.173.19:35:07.87#ibcon#read 5, iclass 6, count 0 2006.173.19:35:07.87#ibcon#about to read 6, iclass 6, count 0 2006.173.19:35:07.87#ibcon#read 6, iclass 6, count 0 2006.173.19:35:07.87#ibcon#end of sib2, iclass 6, count 0 2006.173.19:35:07.87#ibcon#*mode == 0, iclass 6, count 0 2006.173.19:35:07.87#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.19:35:07.87#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.19:35:07.87#ibcon#*before write, iclass 6, count 0 2006.173.19:35:07.87#ibcon#enter sib2, iclass 6, count 0 2006.173.19:35:07.87#ibcon#flushed, iclass 6, count 0 2006.173.19:35:07.87#ibcon#about to write, iclass 6, count 0 2006.173.19:35:07.87#ibcon#wrote, iclass 6, count 0 2006.173.19:35:07.87#ibcon#about to read 3, iclass 6, count 0 2006.173.19:35:07.91#ibcon#read 3, iclass 6, count 0 2006.173.19:35:07.91#ibcon#about to read 4, iclass 6, count 0 2006.173.19:35:07.91#ibcon#read 4, iclass 6, count 0 2006.173.19:35:07.91#ibcon#about to read 5, iclass 6, count 0 2006.173.19:35:07.91#ibcon#read 5, iclass 6, count 0 2006.173.19:35:07.91#ibcon#about to read 6, iclass 6, count 0 2006.173.19:35:07.91#ibcon#read 6, iclass 6, count 0 2006.173.19:35:07.91#ibcon#end of sib2, iclass 6, count 0 2006.173.19:35:07.91#ibcon#*after write, iclass 6, count 0 2006.173.19:35:07.91#ibcon#*before return 0, iclass 6, count 0 2006.173.19:35:07.91#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.19:35:07.91#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.19:35:07.91#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.19:35:07.91#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.19:35:07.91$vck44/vb=4,4 2006.173.19:35:07.91#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.19:35:07.91#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.19:35:07.91#ibcon#ireg 11 cls_cnt 2 2006.173.19:35:07.91#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.19:35:07.97#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.19:35:07.97#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.19:35:07.97#ibcon#enter wrdev, iclass 10, count 2 2006.173.19:35:07.97#ibcon#first serial, iclass 10, count 2 2006.173.19:35:07.97#ibcon#enter sib2, iclass 10, count 2 2006.173.19:35:07.97#ibcon#flushed, iclass 10, count 2 2006.173.19:35:07.97#ibcon#about to write, iclass 10, count 2 2006.173.19:35:07.97#ibcon#wrote, iclass 10, count 2 2006.173.19:35:07.97#ibcon#about to read 3, iclass 10, count 2 2006.173.19:35:07.99#ibcon#read 3, iclass 10, count 2 2006.173.19:35:07.99#ibcon#about to read 4, iclass 10, count 2 2006.173.19:35:07.99#ibcon#read 4, iclass 10, count 2 2006.173.19:35:07.99#ibcon#about to read 5, iclass 10, count 2 2006.173.19:35:07.99#ibcon#read 5, iclass 10, count 2 2006.173.19:35:07.99#ibcon#about to read 6, iclass 10, count 2 2006.173.19:35:07.99#ibcon#read 6, iclass 10, count 2 2006.173.19:35:07.99#ibcon#end of sib2, iclass 10, count 2 2006.173.19:35:07.99#ibcon#*mode == 0, iclass 10, count 2 2006.173.19:35:07.99#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.19:35:07.99#ibcon#[27=AT04-04\r\n] 2006.173.19:35:07.99#ibcon#*before write, iclass 10, count 2 2006.173.19:35:07.99#ibcon#enter sib2, iclass 10, count 2 2006.173.19:35:07.99#ibcon#flushed, iclass 10, count 2 2006.173.19:35:07.99#ibcon#about to write, iclass 10, count 2 2006.173.19:35:07.99#ibcon#wrote, iclass 10, count 2 2006.173.19:35:07.99#ibcon#about to read 3, iclass 10, count 2 2006.173.19:35:08.02#ibcon#read 3, iclass 10, count 2 2006.173.19:35:08.02#ibcon#about to read 4, iclass 10, count 2 2006.173.19:35:08.02#ibcon#read 4, iclass 10, count 2 2006.173.19:35:08.02#ibcon#about to read 5, iclass 10, count 2 2006.173.19:35:08.02#ibcon#read 5, iclass 10, count 2 2006.173.19:35:08.02#ibcon#about to read 6, iclass 10, count 2 2006.173.19:35:08.02#ibcon#read 6, iclass 10, count 2 2006.173.19:35:08.02#ibcon#end of sib2, iclass 10, count 2 2006.173.19:35:08.02#ibcon#*after write, iclass 10, count 2 2006.173.19:35:08.02#ibcon#*before return 0, iclass 10, count 2 2006.173.19:35:08.02#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.19:35:08.02#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.19:35:08.02#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.19:35:08.02#ibcon#ireg 7 cls_cnt 0 2006.173.19:35:08.02#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.19:35:08.14#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.19:35:08.14#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.19:35:08.14#ibcon#enter wrdev, iclass 10, count 0 2006.173.19:35:08.14#ibcon#first serial, iclass 10, count 0 2006.173.19:35:08.14#ibcon#enter sib2, iclass 10, count 0 2006.173.19:35:08.14#ibcon#flushed, iclass 10, count 0 2006.173.19:35:08.14#ibcon#about to write, iclass 10, count 0 2006.173.19:35:08.14#ibcon#wrote, iclass 10, count 0 2006.173.19:35:08.14#ibcon#about to read 3, iclass 10, count 0 2006.173.19:35:08.16#ibcon#read 3, iclass 10, count 0 2006.173.19:35:08.16#ibcon#about to read 4, iclass 10, count 0 2006.173.19:35:08.16#ibcon#read 4, iclass 10, count 0 2006.173.19:35:08.16#ibcon#about to read 5, iclass 10, count 0 2006.173.19:35:08.16#ibcon#read 5, iclass 10, count 0 2006.173.19:35:08.16#ibcon#about to read 6, iclass 10, count 0 2006.173.19:35:08.16#ibcon#read 6, iclass 10, count 0 2006.173.19:35:08.16#ibcon#end of sib2, iclass 10, count 0 2006.173.19:35:08.16#ibcon#*mode == 0, iclass 10, count 0 2006.173.19:35:08.16#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.19:35:08.16#ibcon#[27=USB\r\n] 2006.173.19:35:08.16#ibcon#*before write, iclass 10, count 0 2006.173.19:35:08.16#ibcon#enter sib2, iclass 10, count 0 2006.173.19:35:08.16#ibcon#flushed, iclass 10, count 0 2006.173.19:35:08.16#ibcon#about to write, iclass 10, count 0 2006.173.19:35:08.16#ibcon#wrote, iclass 10, count 0 2006.173.19:35:08.16#ibcon#about to read 3, iclass 10, count 0 2006.173.19:35:08.19#ibcon#read 3, iclass 10, count 0 2006.173.19:35:08.19#ibcon#about to read 4, iclass 10, count 0 2006.173.19:35:08.19#ibcon#read 4, iclass 10, count 0 2006.173.19:35:08.19#ibcon#about to read 5, iclass 10, count 0 2006.173.19:35:08.19#ibcon#read 5, iclass 10, count 0 2006.173.19:35:08.19#ibcon#about to read 6, iclass 10, count 0 2006.173.19:35:08.19#ibcon#read 6, iclass 10, count 0 2006.173.19:35:08.19#ibcon#end of sib2, iclass 10, count 0 2006.173.19:35:08.19#ibcon#*after write, iclass 10, count 0 2006.173.19:35:08.19#ibcon#*before return 0, iclass 10, count 0 2006.173.19:35:08.19#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.19:35:08.19#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.19:35:08.19#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.19:35:08.19#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.19:35:08.19$vck44/vblo=5,709.99 2006.173.19:35:08.19#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.19:35:08.19#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.19:35:08.19#ibcon#ireg 17 cls_cnt 0 2006.173.19:35:08.19#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.19:35:08.19#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.19:35:08.19#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.19:35:08.19#ibcon#enter wrdev, iclass 12, count 0 2006.173.19:35:08.19#ibcon#first serial, iclass 12, count 0 2006.173.19:35:08.19#ibcon#enter sib2, iclass 12, count 0 2006.173.19:35:08.19#ibcon#flushed, iclass 12, count 0 2006.173.19:35:08.19#ibcon#about to write, iclass 12, count 0 2006.173.19:35:08.19#ibcon#wrote, iclass 12, count 0 2006.173.19:35:08.19#ibcon#about to read 3, iclass 12, count 0 2006.173.19:35:08.21#ibcon#read 3, iclass 12, count 0 2006.173.19:35:08.21#ibcon#about to read 4, iclass 12, count 0 2006.173.19:35:08.21#ibcon#read 4, iclass 12, count 0 2006.173.19:35:08.21#ibcon#about to read 5, iclass 12, count 0 2006.173.19:35:08.21#ibcon#read 5, iclass 12, count 0 2006.173.19:35:08.21#ibcon#about to read 6, iclass 12, count 0 2006.173.19:35:08.21#ibcon#read 6, iclass 12, count 0 2006.173.19:35:08.21#ibcon#end of sib2, iclass 12, count 0 2006.173.19:35:08.21#ibcon#*mode == 0, iclass 12, count 0 2006.173.19:35:08.21#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.19:35:08.21#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.19:35:08.21#ibcon#*before write, iclass 12, count 0 2006.173.19:35:08.21#ibcon#enter sib2, iclass 12, count 0 2006.173.19:35:08.21#ibcon#flushed, iclass 12, count 0 2006.173.19:35:08.21#ibcon#about to write, iclass 12, count 0 2006.173.19:35:08.21#ibcon#wrote, iclass 12, count 0 2006.173.19:35:08.21#ibcon#about to read 3, iclass 12, count 0 2006.173.19:35:08.25#ibcon#read 3, iclass 12, count 0 2006.173.19:35:08.25#ibcon#about to read 4, iclass 12, count 0 2006.173.19:35:08.25#ibcon#read 4, iclass 12, count 0 2006.173.19:35:08.25#ibcon#about to read 5, iclass 12, count 0 2006.173.19:35:08.25#ibcon#read 5, iclass 12, count 0 2006.173.19:35:08.25#ibcon#about to read 6, iclass 12, count 0 2006.173.19:35:08.25#ibcon#read 6, iclass 12, count 0 2006.173.19:35:08.25#ibcon#end of sib2, iclass 12, count 0 2006.173.19:35:08.25#ibcon#*after write, iclass 12, count 0 2006.173.19:35:08.25#ibcon#*before return 0, iclass 12, count 0 2006.173.19:35:08.25#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.19:35:08.25#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.19:35:08.25#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.19:35:08.25#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.19:35:08.25$vck44/vb=5,4 2006.173.19:35:08.25#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.19:35:08.25#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.19:35:08.25#ibcon#ireg 11 cls_cnt 2 2006.173.19:35:08.25#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.19:35:08.31#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.19:35:08.31#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.19:35:08.31#ibcon#enter wrdev, iclass 14, count 2 2006.173.19:35:08.31#ibcon#first serial, iclass 14, count 2 2006.173.19:35:08.31#ibcon#enter sib2, iclass 14, count 2 2006.173.19:35:08.31#ibcon#flushed, iclass 14, count 2 2006.173.19:35:08.31#ibcon#about to write, iclass 14, count 2 2006.173.19:35:08.31#ibcon#wrote, iclass 14, count 2 2006.173.19:35:08.31#ibcon#about to read 3, iclass 14, count 2 2006.173.19:35:08.33#ibcon#read 3, iclass 14, count 2 2006.173.19:35:08.33#ibcon#about to read 4, iclass 14, count 2 2006.173.19:35:08.33#ibcon#read 4, iclass 14, count 2 2006.173.19:35:08.33#ibcon#about to read 5, iclass 14, count 2 2006.173.19:35:08.33#ibcon#read 5, iclass 14, count 2 2006.173.19:35:08.33#ibcon#about to read 6, iclass 14, count 2 2006.173.19:35:08.33#ibcon#read 6, iclass 14, count 2 2006.173.19:35:08.33#ibcon#end of sib2, iclass 14, count 2 2006.173.19:35:08.33#ibcon#*mode == 0, iclass 14, count 2 2006.173.19:35:08.33#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.19:35:08.33#ibcon#[27=AT05-04\r\n] 2006.173.19:35:08.33#ibcon#*before write, iclass 14, count 2 2006.173.19:35:08.33#ibcon#enter sib2, iclass 14, count 2 2006.173.19:35:08.33#ibcon#flushed, iclass 14, count 2 2006.173.19:35:08.33#ibcon#about to write, iclass 14, count 2 2006.173.19:35:08.33#ibcon#wrote, iclass 14, count 2 2006.173.19:35:08.33#ibcon#about to read 3, iclass 14, count 2 2006.173.19:35:08.36#ibcon#read 3, iclass 14, count 2 2006.173.19:35:08.36#ibcon#about to read 4, iclass 14, count 2 2006.173.19:35:08.36#ibcon#read 4, iclass 14, count 2 2006.173.19:35:08.36#ibcon#about to read 5, iclass 14, count 2 2006.173.19:35:08.36#ibcon#read 5, iclass 14, count 2 2006.173.19:35:08.36#ibcon#about to read 6, iclass 14, count 2 2006.173.19:35:08.36#ibcon#read 6, iclass 14, count 2 2006.173.19:35:08.36#ibcon#end of sib2, iclass 14, count 2 2006.173.19:35:08.36#ibcon#*after write, iclass 14, count 2 2006.173.19:35:08.36#ibcon#*before return 0, iclass 14, count 2 2006.173.19:35:08.36#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.19:35:08.36#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.19:35:08.36#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.19:35:08.36#ibcon#ireg 7 cls_cnt 0 2006.173.19:35:08.36#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.19:35:08.48#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.19:35:08.48#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.19:35:08.48#ibcon#enter wrdev, iclass 14, count 0 2006.173.19:35:08.48#ibcon#first serial, iclass 14, count 0 2006.173.19:35:08.48#ibcon#enter sib2, iclass 14, count 0 2006.173.19:35:08.48#ibcon#flushed, iclass 14, count 0 2006.173.19:35:08.48#ibcon#about to write, iclass 14, count 0 2006.173.19:35:08.48#ibcon#wrote, iclass 14, count 0 2006.173.19:35:08.48#ibcon#about to read 3, iclass 14, count 0 2006.173.19:35:08.50#ibcon#read 3, iclass 14, count 0 2006.173.19:35:08.50#ibcon#about to read 4, iclass 14, count 0 2006.173.19:35:08.50#ibcon#read 4, iclass 14, count 0 2006.173.19:35:08.50#ibcon#about to read 5, iclass 14, count 0 2006.173.19:35:08.50#ibcon#read 5, iclass 14, count 0 2006.173.19:35:08.50#ibcon#about to read 6, iclass 14, count 0 2006.173.19:35:08.50#ibcon#read 6, iclass 14, count 0 2006.173.19:35:08.50#ibcon#end of sib2, iclass 14, count 0 2006.173.19:35:08.50#ibcon#*mode == 0, iclass 14, count 0 2006.173.19:35:08.50#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.19:35:08.50#ibcon#[27=USB\r\n] 2006.173.19:35:08.50#ibcon#*before write, iclass 14, count 0 2006.173.19:35:08.50#ibcon#enter sib2, iclass 14, count 0 2006.173.19:35:08.50#ibcon#flushed, iclass 14, count 0 2006.173.19:35:08.50#ibcon#about to write, iclass 14, count 0 2006.173.19:35:08.50#ibcon#wrote, iclass 14, count 0 2006.173.19:35:08.50#ibcon#about to read 3, iclass 14, count 0 2006.173.19:35:08.53#ibcon#read 3, iclass 14, count 0 2006.173.19:35:08.53#ibcon#about to read 4, iclass 14, count 0 2006.173.19:35:08.53#ibcon#read 4, iclass 14, count 0 2006.173.19:35:08.53#ibcon#about to read 5, iclass 14, count 0 2006.173.19:35:08.53#ibcon#read 5, iclass 14, count 0 2006.173.19:35:08.53#ibcon#about to read 6, iclass 14, count 0 2006.173.19:35:08.53#ibcon#read 6, iclass 14, count 0 2006.173.19:35:08.53#ibcon#end of sib2, iclass 14, count 0 2006.173.19:35:08.53#ibcon#*after write, iclass 14, count 0 2006.173.19:35:08.53#ibcon#*before return 0, iclass 14, count 0 2006.173.19:35:08.53#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.19:35:08.53#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.19:35:08.53#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.19:35:08.53#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.19:35:08.53$vck44/vblo=6,719.99 2006.173.19:35:08.53#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.19:35:08.53#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.19:35:08.53#ibcon#ireg 17 cls_cnt 0 2006.173.19:35:08.53#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.19:35:08.53#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.19:35:08.53#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.19:35:08.53#ibcon#enter wrdev, iclass 16, count 0 2006.173.19:35:08.53#ibcon#first serial, iclass 16, count 0 2006.173.19:35:08.53#ibcon#enter sib2, iclass 16, count 0 2006.173.19:35:08.53#ibcon#flushed, iclass 16, count 0 2006.173.19:35:08.53#ibcon#about to write, iclass 16, count 0 2006.173.19:35:08.53#ibcon#wrote, iclass 16, count 0 2006.173.19:35:08.53#ibcon#about to read 3, iclass 16, count 0 2006.173.19:35:08.55#ibcon#read 3, iclass 16, count 0 2006.173.19:35:08.55#ibcon#about to read 4, iclass 16, count 0 2006.173.19:35:08.55#ibcon#read 4, iclass 16, count 0 2006.173.19:35:08.55#ibcon#about to read 5, iclass 16, count 0 2006.173.19:35:08.55#ibcon#read 5, iclass 16, count 0 2006.173.19:35:08.55#ibcon#about to read 6, iclass 16, count 0 2006.173.19:35:08.55#ibcon#read 6, iclass 16, count 0 2006.173.19:35:08.55#ibcon#end of sib2, iclass 16, count 0 2006.173.19:35:08.55#ibcon#*mode == 0, iclass 16, count 0 2006.173.19:35:08.55#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.19:35:08.55#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.19:35:08.55#ibcon#*before write, iclass 16, count 0 2006.173.19:35:08.55#ibcon#enter sib2, iclass 16, count 0 2006.173.19:35:08.55#ibcon#flushed, iclass 16, count 0 2006.173.19:35:08.55#ibcon#about to write, iclass 16, count 0 2006.173.19:35:08.55#ibcon#wrote, iclass 16, count 0 2006.173.19:35:08.55#ibcon#about to read 3, iclass 16, count 0 2006.173.19:35:08.59#ibcon#read 3, iclass 16, count 0 2006.173.19:35:08.59#ibcon#about to read 4, iclass 16, count 0 2006.173.19:35:08.59#ibcon#read 4, iclass 16, count 0 2006.173.19:35:08.59#ibcon#about to read 5, iclass 16, count 0 2006.173.19:35:08.59#ibcon#read 5, iclass 16, count 0 2006.173.19:35:08.59#ibcon#about to read 6, iclass 16, count 0 2006.173.19:35:08.59#ibcon#read 6, iclass 16, count 0 2006.173.19:35:08.59#ibcon#end of sib2, iclass 16, count 0 2006.173.19:35:08.59#ibcon#*after write, iclass 16, count 0 2006.173.19:35:08.59#ibcon#*before return 0, iclass 16, count 0 2006.173.19:35:08.59#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.19:35:08.59#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.19:35:08.59#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.19:35:08.59#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.19:35:08.59$vck44/vb=6,4 2006.173.19:35:08.59#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.19:35:08.59#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.19:35:08.59#ibcon#ireg 11 cls_cnt 2 2006.173.19:35:08.59#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.19:35:08.65#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.19:35:08.65#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.19:35:08.65#ibcon#enter wrdev, iclass 18, count 2 2006.173.19:35:08.65#ibcon#first serial, iclass 18, count 2 2006.173.19:35:08.65#ibcon#enter sib2, iclass 18, count 2 2006.173.19:35:08.65#ibcon#flushed, iclass 18, count 2 2006.173.19:35:08.65#ibcon#about to write, iclass 18, count 2 2006.173.19:35:08.65#ibcon#wrote, iclass 18, count 2 2006.173.19:35:08.65#ibcon#about to read 3, iclass 18, count 2 2006.173.19:35:08.67#ibcon#read 3, iclass 18, count 2 2006.173.19:35:08.67#ibcon#about to read 4, iclass 18, count 2 2006.173.19:35:08.67#ibcon#read 4, iclass 18, count 2 2006.173.19:35:08.67#ibcon#about to read 5, iclass 18, count 2 2006.173.19:35:08.67#ibcon#read 5, iclass 18, count 2 2006.173.19:35:08.67#ibcon#about to read 6, iclass 18, count 2 2006.173.19:35:08.67#ibcon#read 6, iclass 18, count 2 2006.173.19:35:08.67#ibcon#end of sib2, iclass 18, count 2 2006.173.19:35:08.67#ibcon#*mode == 0, iclass 18, count 2 2006.173.19:35:08.67#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.19:35:08.67#ibcon#[27=AT06-04\r\n] 2006.173.19:35:08.67#ibcon#*before write, iclass 18, count 2 2006.173.19:35:08.67#ibcon#enter sib2, iclass 18, count 2 2006.173.19:35:08.67#ibcon#flushed, iclass 18, count 2 2006.173.19:35:08.67#ibcon#about to write, iclass 18, count 2 2006.173.19:35:08.67#ibcon#wrote, iclass 18, count 2 2006.173.19:35:08.67#ibcon#about to read 3, iclass 18, count 2 2006.173.19:35:08.70#ibcon#read 3, iclass 18, count 2 2006.173.19:35:08.70#ibcon#about to read 4, iclass 18, count 2 2006.173.19:35:08.70#ibcon#read 4, iclass 18, count 2 2006.173.19:35:08.70#ibcon#about to read 5, iclass 18, count 2 2006.173.19:35:08.70#ibcon#read 5, iclass 18, count 2 2006.173.19:35:08.70#ibcon#about to read 6, iclass 18, count 2 2006.173.19:35:08.70#ibcon#read 6, iclass 18, count 2 2006.173.19:35:08.70#ibcon#end of sib2, iclass 18, count 2 2006.173.19:35:08.70#ibcon#*after write, iclass 18, count 2 2006.173.19:35:08.77#ibcon#*before return 0, iclass 18, count 2 2006.173.19:35:08.77#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.19:35:08.77#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.19:35:08.77#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.19:35:08.77#ibcon#ireg 7 cls_cnt 0 2006.173.19:35:08.77#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.19:35:08.89#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.19:35:08.89#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.19:35:08.89#ibcon#enter wrdev, iclass 18, count 0 2006.173.19:35:08.89#ibcon#first serial, iclass 18, count 0 2006.173.19:35:08.89#ibcon#enter sib2, iclass 18, count 0 2006.173.19:35:08.89#ibcon#flushed, iclass 18, count 0 2006.173.19:35:08.89#ibcon#about to write, iclass 18, count 0 2006.173.19:35:08.89#ibcon#wrote, iclass 18, count 0 2006.173.19:35:08.89#ibcon#about to read 3, iclass 18, count 0 2006.173.19:35:08.91#ibcon#read 3, iclass 18, count 0 2006.173.19:35:08.91#ibcon#about to read 4, iclass 18, count 0 2006.173.19:35:08.91#ibcon#read 4, iclass 18, count 0 2006.173.19:35:08.91#ibcon#about to read 5, iclass 18, count 0 2006.173.19:35:08.91#ibcon#read 5, iclass 18, count 0 2006.173.19:35:08.91#ibcon#about to read 6, iclass 18, count 0 2006.173.19:35:08.91#ibcon#read 6, iclass 18, count 0 2006.173.19:35:08.91#ibcon#end of sib2, iclass 18, count 0 2006.173.19:35:08.91#ibcon#*mode == 0, iclass 18, count 0 2006.173.19:35:08.91#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.19:35:08.91#ibcon#[27=USB\r\n] 2006.173.19:35:08.91#ibcon#*before write, iclass 18, count 0 2006.173.19:35:08.91#ibcon#enter sib2, iclass 18, count 0 2006.173.19:35:08.91#ibcon#flushed, iclass 18, count 0 2006.173.19:35:08.91#ibcon#about to write, iclass 18, count 0 2006.173.19:35:08.91#ibcon#wrote, iclass 18, count 0 2006.173.19:35:08.91#ibcon#about to read 3, iclass 18, count 0 2006.173.19:35:08.94#ibcon#read 3, iclass 18, count 0 2006.173.19:35:08.94#ibcon#about to read 4, iclass 18, count 0 2006.173.19:35:08.94#ibcon#read 4, iclass 18, count 0 2006.173.19:35:08.94#ibcon#about to read 5, iclass 18, count 0 2006.173.19:35:08.94#ibcon#read 5, iclass 18, count 0 2006.173.19:35:08.94#ibcon#about to read 6, iclass 18, count 0 2006.173.19:35:08.94#ibcon#read 6, iclass 18, count 0 2006.173.19:35:08.94#ibcon#end of sib2, iclass 18, count 0 2006.173.19:35:08.94#ibcon#*after write, iclass 18, count 0 2006.173.19:35:08.94#ibcon#*before return 0, iclass 18, count 0 2006.173.19:35:08.94#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.19:35:08.94#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.19:35:08.94#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.19:35:08.94#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.19:35:08.94$vck44/vblo=7,734.99 2006.173.19:35:08.94#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.19:35:08.94#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.19:35:08.94#ibcon#ireg 17 cls_cnt 0 2006.173.19:35:08.94#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.19:35:08.94#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.19:35:08.94#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.19:35:08.94#ibcon#enter wrdev, iclass 20, count 0 2006.173.19:35:08.94#ibcon#first serial, iclass 20, count 0 2006.173.19:35:08.94#ibcon#enter sib2, iclass 20, count 0 2006.173.19:35:08.94#ibcon#flushed, iclass 20, count 0 2006.173.19:35:08.94#ibcon#about to write, iclass 20, count 0 2006.173.19:35:08.94#ibcon#wrote, iclass 20, count 0 2006.173.19:35:08.94#ibcon#about to read 3, iclass 20, count 0 2006.173.19:35:08.96#ibcon#read 3, iclass 20, count 0 2006.173.19:35:08.96#ibcon#about to read 4, iclass 20, count 0 2006.173.19:35:08.96#ibcon#read 4, iclass 20, count 0 2006.173.19:35:08.96#ibcon#about to read 5, iclass 20, count 0 2006.173.19:35:08.96#ibcon#read 5, iclass 20, count 0 2006.173.19:35:08.96#ibcon#about to read 6, iclass 20, count 0 2006.173.19:35:08.96#ibcon#read 6, iclass 20, count 0 2006.173.19:35:08.96#ibcon#end of sib2, iclass 20, count 0 2006.173.19:35:08.96#ibcon#*mode == 0, iclass 20, count 0 2006.173.19:35:08.96#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.19:35:08.96#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.19:35:08.96#ibcon#*before write, iclass 20, count 0 2006.173.19:35:08.96#ibcon#enter sib2, iclass 20, count 0 2006.173.19:35:08.96#ibcon#flushed, iclass 20, count 0 2006.173.19:35:08.96#ibcon#about to write, iclass 20, count 0 2006.173.19:35:08.96#ibcon#wrote, iclass 20, count 0 2006.173.19:35:08.96#ibcon#about to read 3, iclass 20, count 0 2006.173.19:35:09.00#ibcon#read 3, iclass 20, count 0 2006.173.19:35:09.00#ibcon#about to read 4, iclass 20, count 0 2006.173.19:35:09.00#ibcon#read 4, iclass 20, count 0 2006.173.19:35:09.00#ibcon#about to read 5, iclass 20, count 0 2006.173.19:35:09.00#ibcon#read 5, iclass 20, count 0 2006.173.19:35:09.00#ibcon#about to read 6, iclass 20, count 0 2006.173.19:35:09.00#ibcon#read 6, iclass 20, count 0 2006.173.19:35:09.00#ibcon#end of sib2, iclass 20, count 0 2006.173.19:35:09.00#ibcon#*after write, iclass 20, count 0 2006.173.19:35:09.00#ibcon#*before return 0, iclass 20, count 0 2006.173.19:35:09.00#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.19:35:09.00#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.19:35:09.00#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.19:35:09.00#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.19:35:09.00$vck44/vb=7,4 2006.173.19:35:09.00#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.19:35:09.00#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.19:35:09.00#ibcon#ireg 11 cls_cnt 2 2006.173.19:35:09.00#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.19:35:09.06#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.19:35:09.06#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.19:35:09.06#ibcon#enter wrdev, iclass 22, count 2 2006.173.19:35:09.06#ibcon#first serial, iclass 22, count 2 2006.173.19:35:09.06#ibcon#enter sib2, iclass 22, count 2 2006.173.19:35:09.06#ibcon#flushed, iclass 22, count 2 2006.173.19:35:09.06#ibcon#about to write, iclass 22, count 2 2006.173.19:35:09.06#ibcon#wrote, iclass 22, count 2 2006.173.19:35:09.06#ibcon#about to read 3, iclass 22, count 2 2006.173.19:35:09.08#ibcon#read 3, iclass 22, count 2 2006.173.19:35:09.08#ibcon#about to read 4, iclass 22, count 2 2006.173.19:35:09.08#ibcon#read 4, iclass 22, count 2 2006.173.19:35:09.08#ibcon#about to read 5, iclass 22, count 2 2006.173.19:35:09.08#ibcon#read 5, iclass 22, count 2 2006.173.19:35:09.08#ibcon#about to read 6, iclass 22, count 2 2006.173.19:35:09.08#ibcon#read 6, iclass 22, count 2 2006.173.19:35:09.08#ibcon#end of sib2, iclass 22, count 2 2006.173.19:35:09.08#ibcon#*mode == 0, iclass 22, count 2 2006.173.19:35:09.08#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.19:35:09.08#ibcon#[27=AT07-04\r\n] 2006.173.19:35:09.08#ibcon#*before write, iclass 22, count 2 2006.173.19:35:09.08#ibcon#enter sib2, iclass 22, count 2 2006.173.19:35:09.08#ibcon#flushed, iclass 22, count 2 2006.173.19:35:09.08#ibcon#about to write, iclass 22, count 2 2006.173.19:35:09.08#ibcon#wrote, iclass 22, count 2 2006.173.19:35:09.08#ibcon#about to read 3, iclass 22, count 2 2006.173.19:35:09.11#ibcon#read 3, iclass 22, count 2 2006.173.19:35:09.11#ibcon#about to read 4, iclass 22, count 2 2006.173.19:35:09.11#ibcon#read 4, iclass 22, count 2 2006.173.19:35:09.11#ibcon#about to read 5, iclass 22, count 2 2006.173.19:35:09.11#ibcon#read 5, iclass 22, count 2 2006.173.19:35:09.11#ibcon#about to read 6, iclass 22, count 2 2006.173.19:35:09.11#ibcon#read 6, iclass 22, count 2 2006.173.19:35:09.11#ibcon#end of sib2, iclass 22, count 2 2006.173.19:35:09.11#ibcon#*after write, iclass 22, count 2 2006.173.19:35:09.11#ibcon#*before return 0, iclass 22, count 2 2006.173.19:35:09.11#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.19:35:09.11#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.19:35:09.11#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.19:35:09.11#ibcon#ireg 7 cls_cnt 0 2006.173.19:35:09.11#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.19:35:09.23#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.19:35:09.23#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.19:35:09.23#ibcon#enter wrdev, iclass 22, count 0 2006.173.19:35:09.23#ibcon#first serial, iclass 22, count 0 2006.173.19:35:09.23#ibcon#enter sib2, iclass 22, count 0 2006.173.19:35:09.23#ibcon#flushed, iclass 22, count 0 2006.173.19:35:09.23#ibcon#about to write, iclass 22, count 0 2006.173.19:35:09.23#ibcon#wrote, iclass 22, count 0 2006.173.19:35:09.23#ibcon#about to read 3, iclass 22, count 0 2006.173.19:35:09.25#ibcon#read 3, iclass 22, count 0 2006.173.19:35:09.25#ibcon#about to read 4, iclass 22, count 0 2006.173.19:35:09.25#ibcon#read 4, iclass 22, count 0 2006.173.19:35:09.25#ibcon#about to read 5, iclass 22, count 0 2006.173.19:35:09.25#ibcon#read 5, iclass 22, count 0 2006.173.19:35:09.25#ibcon#about to read 6, iclass 22, count 0 2006.173.19:35:09.25#ibcon#read 6, iclass 22, count 0 2006.173.19:35:09.25#ibcon#end of sib2, iclass 22, count 0 2006.173.19:35:09.25#ibcon#*mode == 0, iclass 22, count 0 2006.173.19:35:09.25#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.19:35:09.25#ibcon#[27=USB\r\n] 2006.173.19:35:09.25#ibcon#*before write, iclass 22, count 0 2006.173.19:35:09.25#ibcon#enter sib2, iclass 22, count 0 2006.173.19:35:09.25#ibcon#flushed, iclass 22, count 0 2006.173.19:35:09.25#ibcon#about to write, iclass 22, count 0 2006.173.19:35:09.25#ibcon#wrote, iclass 22, count 0 2006.173.19:35:09.25#ibcon#about to read 3, iclass 22, count 0 2006.173.19:35:09.28#ibcon#read 3, iclass 22, count 0 2006.173.19:35:09.28#ibcon#about to read 4, iclass 22, count 0 2006.173.19:35:09.28#ibcon#read 4, iclass 22, count 0 2006.173.19:35:09.28#ibcon#about to read 5, iclass 22, count 0 2006.173.19:35:09.28#ibcon#read 5, iclass 22, count 0 2006.173.19:35:09.28#ibcon#about to read 6, iclass 22, count 0 2006.173.19:35:09.28#ibcon#read 6, iclass 22, count 0 2006.173.19:35:09.28#ibcon#end of sib2, iclass 22, count 0 2006.173.19:35:09.28#ibcon#*after write, iclass 22, count 0 2006.173.19:35:09.28#ibcon#*before return 0, iclass 22, count 0 2006.173.19:35:09.28#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.19:35:09.28#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.19:35:09.28#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.19:35:09.28#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.19:35:09.28$vck44/vblo=8,744.99 2006.173.19:35:09.28#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.19:35:09.28#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.19:35:09.28#ibcon#ireg 17 cls_cnt 0 2006.173.19:35:09.28#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.19:35:09.28#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.19:35:09.28#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.19:35:09.28#ibcon#enter wrdev, iclass 24, count 0 2006.173.19:35:09.28#ibcon#first serial, iclass 24, count 0 2006.173.19:35:09.28#ibcon#enter sib2, iclass 24, count 0 2006.173.19:35:09.28#ibcon#flushed, iclass 24, count 0 2006.173.19:35:09.28#ibcon#about to write, iclass 24, count 0 2006.173.19:35:09.28#ibcon#wrote, iclass 24, count 0 2006.173.19:35:09.28#ibcon#about to read 3, iclass 24, count 0 2006.173.19:35:09.30#ibcon#read 3, iclass 24, count 0 2006.173.19:35:09.30#ibcon#about to read 4, iclass 24, count 0 2006.173.19:35:09.30#ibcon#read 4, iclass 24, count 0 2006.173.19:35:09.30#ibcon#about to read 5, iclass 24, count 0 2006.173.19:35:09.30#ibcon#read 5, iclass 24, count 0 2006.173.19:35:09.30#ibcon#about to read 6, iclass 24, count 0 2006.173.19:35:09.30#ibcon#read 6, iclass 24, count 0 2006.173.19:35:09.30#ibcon#end of sib2, iclass 24, count 0 2006.173.19:35:09.30#ibcon#*mode == 0, iclass 24, count 0 2006.173.19:35:09.30#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.19:35:09.30#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.19:35:09.30#ibcon#*before write, iclass 24, count 0 2006.173.19:35:09.30#ibcon#enter sib2, iclass 24, count 0 2006.173.19:35:09.30#ibcon#flushed, iclass 24, count 0 2006.173.19:35:09.30#ibcon#about to write, iclass 24, count 0 2006.173.19:35:09.30#ibcon#wrote, iclass 24, count 0 2006.173.19:35:09.30#ibcon#about to read 3, iclass 24, count 0 2006.173.19:35:09.34#ibcon#read 3, iclass 24, count 0 2006.173.19:35:09.34#ibcon#about to read 4, iclass 24, count 0 2006.173.19:35:09.34#ibcon#read 4, iclass 24, count 0 2006.173.19:35:09.34#ibcon#about to read 5, iclass 24, count 0 2006.173.19:35:09.34#ibcon#read 5, iclass 24, count 0 2006.173.19:35:09.34#ibcon#about to read 6, iclass 24, count 0 2006.173.19:35:09.34#ibcon#read 6, iclass 24, count 0 2006.173.19:35:09.34#ibcon#end of sib2, iclass 24, count 0 2006.173.19:35:09.34#ibcon#*after write, iclass 24, count 0 2006.173.19:35:09.34#ibcon#*before return 0, iclass 24, count 0 2006.173.19:35:09.34#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.19:35:09.34#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.19:35:09.34#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.19:35:09.34#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.19:35:09.34$vck44/vb=8,4 2006.173.19:35:09.34#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.19:35:09.34#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.19:35:09.34#ibcon#ireg 11 cls_cnt 2 2006.173.19:35:09.34#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.19:35:09.40#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.19:35:09.40#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.19:35:09.40#ibcon#enter wrdev, iclass 26, count 2 2006.173.19:35:09.40#ibcon#first serial, iclass 26, count 2 2006.173.19:35:09.40#ibcon#enter sib2, iclass 26, count 2 2006.173.19:35:09.40#ibcon#flushed, iclass 26, count 2 2006.173.19:35:09.40#ibcon#about to write, iclass 26, count 2 2006.173.19:35:09.40#ibcon#wrote, iclass 26, count 2 2006.173.19:35:09.40#ibcon#about to read 3, iclass 26, count 2 2006.173.19:35:09.42#ibcon#read 3, iclass 26, count 2 2006.173.19:35:09.42#ibcon#about to read 4, iclass 26, count 2 2006.173.19:35:09.42#ibcon#read 4, iclass 26, count 2 2006.173.19:35:09.42#ibcon#about to read 5, iclass 26, count 2 2006.173.19:35:09.42#ibcon#read 5, iclass 26, count 2 2006.173.19:35:09.42#ibcon#about to read 6, iclass 26, count 2 2006.173.19:35:09.42#ibcon#read 6, iclass 26, count 2 2006.173.19:35:09.42#ibcon#end of sib2, iclass 26, count 2 2006.173.19:35:09.42#ibcon#*mode == 0, iclass 26, count 2 2006.173.19:35:09.42#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.19:35:09.42#ibcon#[27=AT08-04\r\n] 2006.173.19:35:09.42#ibcon#*before write, iclass 26, count 2 2006.173.19:35:09.42#ibcon#enter sib2, iclass 26, count 2 2006.173.19:35:09.42#ibcon#flushed, iclass 26, count 2 2006.173.19:35:09.42#ibcon#about to write, iclass 26, count 2 2006.173.19:35:09.42#ibcon#wrote, iclass 26, count 2 2006.173.19:35:09.42#ibcon#about to read 3, iclass 26, count 2 2006.173.19:35:09.45#ibcon#read 3, iclass 26, count 2 2006.173.19:35:09.45#ibcon#about to read 4, iclass 26, count 2 2006.173.19:35:09.45#ibcon#read 4, iclass 26, count 2 2006.173.19:35:09.45#ibcon#about to read 5, iclass 26, count 2 2006.173.19:35:09.45#ibcon#read 5, iclass 26, count 2 2006.173.19:35:09.45#ibcon#about to read 6, iclass 26, count 2 2006.173.19:35:09.45#ibcon#read 6, iclass 26, count 2 2006.173.19:35:09.45#ibcon#end of sib2, iclass 26, count 2 2006.173.19:35:09.45#ibcon#*after write, iclass 26, count 2 2006.173.19:35:09.45#ibcon#*before return 0, iclass 26, count 2 2006.173.19:35:09.45#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.19:35:09.45#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.19:35:09.45#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.19:35:09.45#ibcon#ireg 7 cls_cnt 0 2006.173.19:35:09.45#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.19:35:09.57#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.19:35:09.57#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.19:35:09.57#ibcon#enter wrdev, iclass 26, count 0 2006.173.19:35:09.57#ibcon#first serial, iclass 26, count 0 2006.173.19:35:09.57#ibcon#enter sib2, iclass 26, count 0 2006.173.19:35:09.57#ibcon#flushed, iclass 26, count 0 2006.173.19:35:09.57#ibcon#about to write, iclass 26, count 0 2006.173.19:35:09.57#ibcon#wrote, iclass 26, count 0 2006.173.19:35:09.57#ibcon#about to read 3, iclass 26, count 0 2006.173.19:35:09.59#ibcon#read 3, iclass 26, count 0 2006.173.19:35:09.59#ibcon#about to read 4, iclass 26, count 0 2006.173.19:35:09.59#ibcon#read 4, iclass 26, count 0 2006.173.19:35:09.59#ibcon#about to read 5, iclass 26, count 0 2006.173.19:35:09.59#ibcon#read 5, iclass 26, count 0 2006.173.19:35:09.59#ibcon#about to read 6, iclass 26, count 0 2006.173.19:35:09.59#ibcon#read 6, iclass 26, count 0 2006.173.19:35:09.59#ibcon#end of sib2, iclass 26, count 0 2006.173.19:35:09.59#ibcon#*mode == 0, iclass 26, count 0 2006.173.19:35:09.59#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.19:35:09.59#ibcon#[27=USB\r\n] 2006.173.19:35:09.59#ibcon#*before write, iclass 26, count 0 2006.173.19:35:09.59#ibcon#enter sib2, iclass 26, count 0 2006.173.19:35:09.59#ibcon#flushed, iclass 26, count 0 2006.173.19:35:09.59#ibcon#about to write, iclass 26, count 0 2006.173.19:35:09.59#ibcon#wrote, iclass 26, count 0 2006.173.19:35:09.59#ibcon#about to read 3, iclass 26, count 0 2006.173.19:35:09.62#ibcon#read 3, iclass 26, count 0 2006.173.19:35:09.62#ibcon#about to read 4, iclass 26, count 0 2006.173.19:35:09.62#ibcon#read 4, iclass 26, count 0 2006.173.19:35:09.62#ibcon#about to read 5, iclass 26, count 0 2006.173.19:35:09.62#ibcon#read 5, iclass 26, count 0 2006.173.19:35:09.62#ibcon#about to read 6, iclass 26, count 0 2006.173.19:35:09.62#ibcon#read 6, iclass 26, count 0 2006.173.19:35:09.62#ibcon#end of sib2, iclass 26, count 0 2006.173.19:35:09.62#ibcon#*after write, iclass 26, count 0 2006.173.19:35:09.62#ibcon#*before return 0, iclass 26, count 0 2006.173.19:35:09.62#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.19:35:09.62#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.19:35:09.62#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.19:35:09.62#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.19:35:09.62$vck44/vabw=wide 2006.173.19:35:09.62#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.19:35:09.62#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.19:35:09.62#ibcon#ireg 8 cls_cnt 0 2006.173.19:35:09.62#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.19:35:09.62#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.19:35:09.62#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.19:35:09.62#ibcon#enter wrdev, iclass 28, count 0 2006.173.19:35:09.62#ibcon#first serial, iclass 28, count 0 2006.173.19:35:09.62#ibcon#enter sib2, iclass 28, count 0 2006.173.19:35:09.62#ibcon#flushed, iclass 28, count 0 2006.173.19:35:09.62#ibcon#about to write, iclass 28, count 0 2006.173.19:35:09.62#ibcon#wrote, iclass 28, count 0 2006.173.19:35:09.62#ibcon#about to read 3, iclass 28, count 0 2006.173.19:35:09.64#ibcon#read 3, iclass 28, count 0 2006.173.19:35:09.64#ibcon#about to read 4, iclass 28, count 0 2006.173.19:35:09.64#ibcon#read 4, iclass 28, count 0 2006.173.19:35:09.64#ibcon#about to read 5, iclass 28, count 0 2006.173.19:35:09.64#ibcon#read 5, iclass 28, count 0 2006.173.19:35:09.64#ibcon#about to read 6, iclass 28, count 0 2006.173.19:35:09.64#ibcon#read 6, iclass 28, count 0 2006.173.19:35:09.64#ibcon#end of sib2, iclass 28, count 0 2006.173.19:35:09.64#ibcon#*mode == 0, iclass 28, count 0 2006.173.19:35:09.64#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.19:35:09.64#ibcon#[25=BW32\r\n] 2006.173.19:35:09.64#ibcon#*before write, iclass 28, count 0 2006.173.19:35:09.64#ibcon#enter sib2, iclass 28, count 0 2006.173.19:35:09.64#ibcon#flushed, iclass 28, count 0 2006.173.19:35:09.64#ibcon#about to write, iclass 28, count 0 2006.173.19:35:09.64#ibcon#wrote, iclass 28, count 0 2006.173.19:35:09.64#ibcon#about to read 3, iclass 28, count 0 2006.173.19:35:09.67#ibcon#read 3, iclass 28, count 0 2006.173.19:35:09.67#ibcon#about to read 4, iclass 28, count 0 2006.173.19:35:09.67#ibcon#read 4, iclass 28, count 0 2006.173.19:35:09.67#ibcon#about to read 5, iclass 28, count 0 2006.173.19:35:09.67#ibcon#read 5, iclass 28, count 0 2006.173.19:35:09.67#ibcon#about to read 6, iclass 28, count 0 2006.173.19:35:09.67#ibcon#read 6, iclass 28, count 0 2006.173.19:35:09.67#ibcon#end of sib2, iclass 28, count 0 2006.173.19:35:09.67#ibcon#*after write, iclass 28, count 0 2006.173.19:35:09.67#ibcon#*before return 0, iclass 28, count 0 2006.173.19:35:09.67#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.19:35:09.67#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.19:35:09.67#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.19:35:09.67#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.19:35:09.67$vck44/vbbw=wide 2006.173.19:35:09.67#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.19:35:09.67#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.19:35:09.67#ibcon#ireg 8 cls_cnt 0 2006.173.19:35:09.67#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.19:35:09.74#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.19:35:09.74#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.19:35:09.74#ibcon#enter wrdev, iclass 30, count 0 2006.173.19:35:09.74#ibcon#first serial, iclass 30, count 0 2006.173.19:35:09.74#ibcon#enter sib2, iclass 30, count 0 2006.173.19:35:09.74#ibcon#flushed, iclass 30, count 0 2006.173.19:35:09.74#ibcon#about to write, iclass 30, count 0 2006.173.19:35:09.74#ibcon#wrote, iclass 30, count 0 2006.173.19:35:09.74#ibcon#about to read 3, iclass 30, count 0 2006.173.19:35:09.76#ibcon#read 3, iclass 30, count 0 2006.173.19:35:09.76#ibcon#about to read 4, iclass 30, count 0 2006.173.19:35:09.76#ibcon#read 4, iclass 30, count 0 2006.173.19:35:09.76#ibcon#about to read 5, iclass 30, count 0 2006.173.19:35:09.76#ibcon#read 5, iclass 30, count 0 2006.173.19:35:09.76#ibcon#about to read 6, iclass 30, count 0 2006.173.19:35:09.76#ibcon#read 6, iclass 30, count 0 2006.173.19:35:09.76#ibcon#end of sib2, iclass 30, count 0 2006.173.19:35:09.76#ibcon#*mode == 0, iclass 30, count 0 2006.173.19:35:09.76#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.19:35:09.76#ibcon#[27=BW32\r\n] 2006.173.19:35:09.76#ibcon#*before write, iclass 30, count 0 2006.173.19:35:09.76#ibcon#enter sib2, iclass 30, count 0 2006.173.19:35:09.76#ibcon#flushed, iclass 30, count 0 2006.173.19:35:09.76#ibcon#about to write, iclass 30, count 0 2006.173.19:35:09.76#ibcon#wrote, iclass 30, count 0 2006.173.19:35:09.76#ibcon#about to read 3, iclass 30, count 0 2006.173.19:35:09.79#ibcon#read 3, iclass 30, count 0 2006.173.19:35:09.79#ibcon#about to read 4, iclass 30, count 0 2006.173.19:35:09.79#ibcon#read 4, iclass 30, count 0 2006.173.19:35:09.79#ibcon#about to read 5, iclass 30, count 0 2006.173.19:35:09.79#ibcon#read 5, iclass 30, count 0 2006.173.19:35:09.79#ibcon#about to read 6, iclass 30, count 0 2006.173.19:35:09.79#ibcon#read 6, iclass 30, count 0 2006.173.19:35:09.79#ibcon#end of sib2, iclass 30, count 0 2006.173.19:35:09.79#ibcon#*after write, iclass 30, count 0 2006.173.19:35:09.79#ibcon#*before return 0, iclass 30, count 0 2006.173.19:35:09.79#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.19:35:09.79#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.19:35:09.79#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.19:35:09.79#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.19:35:09.79$setupk4/ifdk4 2006.173.19:35:09.79$ifdk4/lo= 2006.173.19:35:09.79$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.19:35:09.79$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.19:35:09.79$ifdk4/patch= 2006.173.19:35:09.79$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.19:35:09.79$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.19:35:09.79$setupk4/!*+20s 2006.173.19:35:16.28#abcon#<5=/00 0.1 0.4 19.351001002.5\r\n> 2006.173.19:35:16.30#abcon#{5=INTERFACE CLEAR} 2006.173.19:35:16.36#abcon#[5=S1D000X0/0*\r\n] 2006.173.19:35:24.22$setupk4/"tpicd 2006.173.19:35:24.22$setupk4/echo=off 2006.173.19:35:24.22$setupk4/xlog=off 2006.173.19:35:24.22:!2006.173.19:40:00 2006.173.19:35:31.14#trakl#Source acquired 2006.173.19:35:33.14#flagr#flagr/antenna,acquired 2006.173.19:40:00.00:preob 2006.173.19:40:01.14/onsource/TRACKING 2006.173.19:40:01.14:!2006.173.19:40:10 2006.173.19:40:10.00:"tape 2006.173.19:40:10.00:"st=record 2006.173.19:40:10.00:data_valid=on 2006.173.19:40:10.00:midob 2006.173.19:40:10.14/onsource/TRACKING 2006.173.19:40:10.14/wx/19.34,1002.5,100 2006.173.19:40:10.29/cable/+6.5164E-03 2006.173.19:40:11.38/va/01,07,usb,yes,41,44 2006.173.19:40:11.38/va/02,06,usb,yes,40,41 2006.173.19:40:11.38/va/03,05,usb,yes,51,53 2006.173.19:40:11.38/va/04,06,usb,yes,41,44 2006.173.19:40:11.38/va/05,04,usb,yes,33,33 2006.173.19:40:11.38/va/06,03,usb,yes,45,45 2006.173.19:40:11.38/va/07,04,usb,yes,37,38 2006.173.19:40:11.38/va/08,04,usb,yes,32,38 2006.173.19:40:11.61/valo/01,524.99,yes,locked 2006.173.19:40:11.61/valo/02,534.99,yes,locked 2006.173.19:40:11.61/valo/03,564.99,yes,locked 2006.173.19:40:11.61/valo/04,624.99,yes,locked 2006.173.19:40:11.61/valo/05,734.99,yes,locked 2006.173.19:40:11.61/valo/06,814.99,yes,locked 2006.173.19:40:11.61/valo/07,864.99,yes,locked 2006.173.19:40:11.61/valo/08,884.99,yes,locked 2006.173.19:40:12.70/vb/01,04,usb,yes,32,29 2006.173.19:40:12.70/vb/02,04,usb,yes,34,34 2006.173.19:40:12.70/vb/03,04,usb,yes,31,34 2006.173.19:40:12.70/vb/04,04,usb,yes,35,34 2006.173.19:40:12.70/vb/05,04,usb,yes,27,30 2006.173.19:40:12.70/vb/06,04,usb,yes,32,28 2006.173.19:40:12.70/vb/07,04,usb,yes,32,31 2006.173.19:40:12.70/vb/08,04,usb,yes,29,33 2006.173.19:40:12.93/vblo/01,629.99,yes,locked 2006.173.19:40:12.93/vblo/02,634.99,yes,locked 2006.173.19:40:12.93/vblo/03,649.99,yes,locked 2006.173.19:40:12.93/vblo/04,679.99,yes,locked 2006.173.19:40:12.93/vblo/05,709.99,yes,locked 2006.173.19:40:12.93/vblo/06,719.99,yes,locked 2006.173.19:40:12.93/vblo/07,734.99,yes,locked 2006.173.19:40:12.93/vblo/08,744.99,yes,locked 2006.173.19:40:13.08/vabw/8 2006.173.19:40:13.23/vbbw/8 2006.173.19:40:13.32/xfe/off,on,14.7 2006.173.19:40:13.70/ifatt/23,28,28,28 2006.173.19:40:14.08/fmout-gps/S +3.90E-07 2006.173.19:40:14.12:!2006.173.19:40:50 2006.173.19:40:50.01:data_valid=off 2006.173.19:40:50.01:"et 2006.173.19:40:50.02:!+3s 2006.173.19:40:53.03:"tape 2006.173.19:40:53.03:postob 2006.173.19:40:53.22/cable/+6.5178E-03 2006.173.19:40:53.22/wx/19.34,1002.5,100 2006.173.19:40:53.28/fmout-gps/S +3.90E-07 2006.173.19:40:53.28:scan_name=173-1946,jd0606,70 2006.173.19:40:53.29:source=2121+053,212344.52,053522.1,2000.0,ccw 2006.173.19:40:55.14#flagr#flagr/antenna,new-source 2006.173.19:40:55.14:checkk5 2006.173.19:40:55.56/chk_autoobs//k5ts1/ autoobs is running! 2006.173.19:40:55.95/chk_autoobs//k5ts2/ autoobs is running! 2006.173.19:40:56.35/chk_autoobs//k5ts3/ autoobs is running! 2006.173.19:40:56.74/chk_autoobs//k5ts4/ autoobs is running! 2006.173.19:40:57.14/chk_obsdata//k5ts1/T1731940??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.19:40:57.53/chk_obsdata//k5ts2/T1731940??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.19:40:57.93/chk_obsdata//k5ts3/T1731940??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.19:40:58.32/chk_obsdata//k5ts4/T1731940??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.19:40:59.04/k5log//k5ts1_log_newline 2006.173.19:40:59.74/k5log//k5ts2_log_newline 2006.173.19:41:00.46/k5log//k5ts3_log_newline 2006.173.19:41:01.17/k5log//k5ts4_log_newline 2006.173.19:41:01.20/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.19:41:01.20:setupk4=1 2006.173.19:41:01.20$setupk4/echo=on 2006.173.19:41:01.20$setupk4/pcalon 2006.173.19:41:01.20$pcalon/"no phase cal control is implemented here 2006.173.19:41:01.20$setupk4/"tpicd=stop 2006.173.19:41:01.20$setupk4/"rec=synch_on 2006.173.19:41:01.20$setupk4/"rec_mode=128 2006.173.19:41:01.20$setupk4/!* 2006.173.19:41:01.20$setupk4/recpk4 2006.173.19:41:01.20$recpk4/recpatch= 2006.173.19:41:01.21$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.19:41:01.21$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.19:41:01.21$setupk4/vck44 2006.173.19:41:01.21$vck44/valo=1,524.99 2006.173.19:41:01.21#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.19:41:01.21#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.19:41:01.21#ibcon#ireg 17 cls_cnt 0 2006.173.19:41:01.21#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.19:41:01.21#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.19:41:01.21#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.19:41:01.21#ibcon#enter wrdev, iclass 22, count 0 2006.173.19:41:01.21#ibcon#first serial, iclass 22, count 0 2006.173.19:41:01.21#ibcon#enter sib2, iclass 22, count 0 2006.173.19:41:01.21#ibcon#flushed, iclass 22, count 0 2006.173.19:41:01.21#ibcon#about to write, iclass 22, count 0 2006.173.19:41:01.21#ibcon#wrote, iclass 22, count 0 2006.173.19:41:01.21#ibcon#about to read 3, iclass 22, count 0 2006.173.19:41:01.23#ibcon#read 3, iclass 22, count 0 2006.173.19:41:01.23#ibcon#about to read 4, iclass 22, count 0 2006.173.19:41:01.23#ibcon#read 4, iclass 22, count 0 2006.173.19:41:01.23#ibcon#about to read 5, iclass 22, count 0 2006.173.19:41:01.23#ibcon#read 5, iclass 22, count 0 2006.173.19:41:01.23#ibcon#about to read 6, iclass 22, count 0 2006.173.19:41:01.23#ibcon#read 6, iclass 22, count 0 2006.173.19:41:01.23#ibcon#end of sib2, iclass 22, count 0 2006.173.19:41:01.23#ibcon#*mode == 0, iclass 22, count 0 2006.173.19:41:01.23#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.19:41:01.23#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.19:41:01.23#ibcon#*before write, iclass 22, count 0 2006.173.19:41:01.23#ibcon#enter sib2, iclass 22, count 0 2006.173.19:41:01.23#ibcon#flushed, iclass 22, count 0 2006.173.19:41:01.23#ibcon#about to write, iclass 22, count 0 2006.173.19:41:01.23#ibcon#wrote, iclass 22, count 0 2006.173.19:41:01.23#ibcon#about to read 3, iclass 22, count 0 2006.173.19:41:01.28#ibcon#read 3, iclass 22, count 0 2006.173.19:41:01.28#ibcon#about to read 4, iclass 22, count 0 2006.173.19:41:01.28#ibcon#read 4, iclass 22, count 0 2006.173.19:41:01.28#ibcon#about to read 5, iclass 22, count 0 2006.173.19:41:01.28#ibcon#read 5, iclass 22, count 0 2006.173.19:41:01.28#ibcon#about to read 6, iclass 22, count 0 2006.173.19:41:01.28#ibcon#read 6, iclass 22, count 0 2006.173.19:41:01.28#ibcon#end of sib2, iclass 22, count 0 2006.173.19:41:01.28#ibcon#*after write, iclass 22, count 0 2006.173.19:41:01.28#ibcon#*before return 0, iclass 22, count 0 2006.173.19:41:01.28#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.19:41:01.28#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.19:41:01.28#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.19:41:01.28#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.19:41:01.28$vck44/va=1,7 2006.173.19:41:01.28#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.19:41:01.28#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.19:41:01.28#ibcon#ireg 11 cls_cnt 2 2006.173.19:41:01.28#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.19:41:01.28#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.19:41:01.28#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.19:41:01.28#ibcon#enter wrdev, iclass 24, count 2 2006.173.19:41:01.28#ibcon#first serial, iclass 24, count 2 2006.173.19:41:01.28#ibcon#enter sib2, iclass 24, count 2 2006.173.19:41:01.28#ibcon#flushed, iclass 24, count 2 2006.173.19:41:01.28#ibcon#about to write, iclass 24, count 2 2006.173.19:41:01.28#ibcon#wrote, iclass 24, count 2 2006.173.19:41:01.28#ibcon#about to read 3, iclass 24, count 2 2006.173.19:41:01.30#ibcon#read 3, iclass 24, count 2 2006.173.19:41:01.30#ibcon#about to read 4, iclass 24, count 2 2006.173.19:41:01.30#ibcon#read 4, iclass 24, count 2 2006.173.19:41:01.30#ibcon#about to read 5, iclass 24, count 2 2006.173.19:41:01.30#ibcon#read 5, iclass 24, count 2 2006.173.19:41:01.30#ibcon#about to read 6, iclass 24, count 2 2006.173.19:41:01.30#ibcon#read 6, iclass 24, count 2 2006.173.19:41:01.30#ibcon#end of sib2, iclass 24, count 2 2006.173.19:41:01.30#ibcon#*mode == 0, iclass 24, count 2 2006.173.19:41:01.30#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.19:41:01.30#ibcon#[25=AT01-07\r\n] 2006.173.19:41:01.30#ibcon#*before write, iclass 24, count 2 2006.173.19:41:01.30#ibcon#enter sib2, iclass 24, count 2 2006.173.19:41:01.30#ibcon#flushed, iclass 24, count 2 2006.173.19:41:01.30#ibcon#about to write, iclass 24, count 2 2006.173.19:41:01.30#ibcon#wrote, iclass 24, count 2 2006.173.19:41:01.30#ibcon#about to read 3, iclass 24, count 2 2006.173.19:41:01.33#ibcon#read 3, iclass 24, count 2 2006.173.19:41:01.33#ibcon#about to read 4, iclass 24, count 2 2006.173.19:41:01.33#ibcon#read 4, iclass 24, count 2 2006.173.19:41:01.33#ibcon#about to read 5, iclass 24, count 2 2006.173.19:41:01.33#ibcon#read 5, iclass 24, count 2 2006.173.19:41:01.33#ibcon#about to read 6, iclass 24, count 2 2006.173.19:41:01.33#ibcon#read 6, iclass 24, count 2 2006.173.19:41:01.33#ibcon#end of sib2, iclass 24, count 2 2006.173.19:41:01.33#ibcon#*after write, iclass 24, count 2 2006.173.19:41:01.33#ibcon#*before return 0, iclass 24, count 2 2006.173.19:41:01.33#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.19:41:01.33#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.19:41:01.33#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.19:41:01.33#ibcon#ireg 7 cls_cnt 0 2006.173.19:41:01.33#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.19:41:01.45#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.19:41:01.45#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.19:41:01.45#ibcon#enter wrdev, iclass 24, count 0 2006.173.19:41:01.45#ibcon#first serial, iclass 24, count 0 2006.173.19:41:01.45#ibcon#enter sib2, iclass 24, count 0 2006.173.19:41:01.45#ibcon#flushed, iclass 24, count 0 2006.173.19:41:01.45#ibcon#about to write, iclass 24, count 0 2006.173.19:41:01.45#ibcon#wrote, iclass 24, count 0 2006.173.19:41:01.45#ibcon#about to read 3, iclass 24, count 0 2006.173.19:41:01.47#ibcon#read 3, iclass 24, count 0 2006.173.19:41:01.47#ibcon#about to read 4, iclass 24, count 0 2006.173.19:41:01.47#ibcon#read 4, iclass 24, count 0 2006.173.19:41:01.47#ibcon#about to read 5, iclass 24, count 0 2006.173.19:41:01.47#ibcon#read 5, iclass 24, count 0 2006.173.19:41:01.47#ibcon#about to read 6, iclass 24, count 0 2006.173.19:41:01.47#ibcon#read 6, iclass 24, count 0 2006.173.19:41:01.47#ibcon#end of sib2, iclass 24, count 0 2006.173.19:41:01.47#ibcon#*mode == 0, iclass 24, count 0 2006.173.19:41:01.47#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.19:41:01.47#ibcon#[25=USB\r\n] 2006.173.19:41:01.47#ibcon#*before write, iclass 24, count 0 2006.173.19:41:01.47#ibcon#enter sib2, iclass 24, count 0 2006.173.19:41:01.47#ibcon#flushed, iclass 24, count 0 2006.173.19:41:01.47#ibcon#about to write, iclass 24, count 0 2006.173.19:41:01.47#ibcon#wrote, iclass 24, count 0 2006.173.19:41:01.47#ibcon#about to read 3, iclass 24, count 0 2006.173.19:41:01.50#ibcon#read 3, iclass 24, count 0 2006.173.19:41:01.50#ibcon#about to read 4, iclass 24, count 0 2006.173.19:41:01.50#ibcon#read 4, iclass 24, count 0 2006.173.19:41:01.50#ibcon#about to read 5, iclass 24, count 0 2006.173.19:41:01.50#ibcon#read 5, iclass 24, count 0 2006.173.19:41:01.50#ibcon#about to read 6, iclass 24, count 0 2006.173.19:41:01.50#ibcon#read 6, iclass 24, count 0 2006.173.19:41:01.50#ibcon#end of sib2, iclass 24, count 0 2006.173.19:41:01.50#ibcon#*after write, iclass 24, count 0 2006.173.19:41:01.50#ibcon#*before return 0, iclass 24, count 0 2006.173.19:41:01.50#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.19:41:01.50#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.19:41:01.50#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.19:41:01.50#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.19:41:01.50$vck44/valo=2,534.99 2006.173.19:41:01.50#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.19:41:01.50#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.19:41:01.50#ibcon#ireg 17 cls_cnt 0 2006.173.19:41:01.50#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.19:41:01.50#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.19:41:01.50#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.19:41:01.50#ibcon#enter wrdev, iclass 26, count 0 2006.173.19:41:01.50#ibcon#first serial, iclass 26, count 0 2006.173.19:41:01.50#ibcon#enter sib2, iclass 26, count 0 2006.173.19:41:01.50#ibcon#flushed, iclass 26, count 0 2006.173.19:41:01.50#ibcon#about to write, iclass 26, count 0 2006.173.19:41:01.50#ibcon#wrote, iclass 26, count 0 2006.173.19:41:01.50#ibcon#about to read 3, iclass 26, count 0 2006.173.19:41:01.52#ibcon#read 3, iclass 26, count 0 2006.173.19:41:01.52#ibcon#about to read 4, iclass 26, count 0 2006.173.19:41:01.52#ibcon#read 4, iclass 26, count 0 2006.173.19:41:01.52#ibcon#about to read 5, iclass 26, count 0 2006.173.19:41:01.52#ibcon#read 5, iclass 26, count 0 2006.173.19:41:01.52#ibcon#about to read 6, iclass 26, count 0 2006.173.19:41:01.52#ibcon#read 6, iclass 26, count 0 2006.173.19:41:01.52#ibcon#end of sib2, iclass 26, count 0 2006.173.19:41:01.52#ibcon#*mode == 0, iclass 26, count 0 2006.173.19:41:01.52#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.19:41:01.52#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.19:41:01.52#ibcon#*before write, iclass 26, count 0 2006.173.19:41:01.52#ibcon#enter sib2, iclass 26, count 0 2006.173.19:41:01.52#ibcon#flushed, iclass 26, count 0 2006.173.19:41:01.52#ibcon#about to write, iclass 26, count 0 2006.173.19:41:01.52#ibcon#wrote, iclass 26, count 0 2006.173.19:41:01.52#ibcon#about to read 3, iclass 26, count 0 2006.173.19:41:01.56#ibcon#read 3, iclass 26, count 0 2006.173.19:41:01.56#ibcon#about to read 4, iclass 26, count 0 2006.173.19:41:01.56#ibcon#read 4, iclass 26, count 0 2006.173.19:41:01.56#ibcon#about to read 5, iclass 26, count 0 2006.173.19:41:01.56#ibcon#read 5, iclass 26, count 0 2006.173.19:41:01.56#ibcon#about to read 6, iclass 26, count 0 2006.173.19:41:01.56#ibcon#read 6, iclass 26, count 0 2006.173.19:41:01.56#ibcon#end of sib2, iclass 26, count 0 2006.173.19:41:01.56#ibcon#*after write, iclass 26, count 0 2006.173.19:41:01.56#ibcon#*before return 0, iclass 26, count 0 2006.173.19:41:01.56#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.19:41:01.56#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.19:41:01.56#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.19:41:01.56#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.19:41:01.56$vck44/va=2,6 2006.173.19:41:01.56#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.19:41:01.56#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.19:41:01.56#ibcon#ireg 11 cls_cnt 2 2006.173.19:41:01.56#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.19:41:01.62#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.19:41:01.62#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.19:41:01.62#ibcon#enter wrdev, iclass 28, count 2 2006.173.19:41:01.62#ibcon#first serial, iclass 28, count 2 2006.173.19:41:01.62#ibcon#enter sib2, iclass 28, count 2 2006.173.19:41:01.62#ibcon#flushed, iclass 28, count 2 2006.173.19:41:01.62#ibcon#about to write, iclass 28, count 2 2006.173.19:41:01.62#ibcon#wrote, iclass 28, count 2 2006.173.19:41:01.62#ibcon#about to read 3, iclass 28, count 2 2006.173.19:41:01.64#ibcon#read 3, iclass 28, count 2 2006.173.19:41:01.64#ibcon#about to read 4, iclass 28, count 2 2006.173.19:41:01.64#ibcon#read 4, iclass 28, count 2 2006.173.19:41:01.64#ibcon#about to read 5, iclass 28, count 2 2006.173.19:41:01.64#ibcon#read 5, iclass 28, count 2 2006.173.19:41:01.64#ibcon#about to read 6, iclass 28, count 2 2006.173.19:41:01.64#ibcon#read 6, iclass 28, count 2 2006.173.19:41:01.64#ibcon#end of sib2, iclass 28, count 2 2006.173.19:41:01.64#ibcon#*mode == 0, iclass 28, count 2 2006.173.19:41:01.64#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.19:41:01.64#ibcon#[25=AT02-06\r\n] 2006.173.19:41:01.64#ibcon#*before write, iclass 28, count 2 2006.173.19:41:01.64#ibcon#enter sib2, iclass 28, count 2 2006.173.19:41:01.64#ibcon#flushed, iclass 28, count 2 2006.173.19:41:01.64#ibcon#about to write, iclass 28, count 2 2006.173.19:41:01.64#ibcon#wrote, iclass 28, count 2 2006.173.19:41:01.64#ibcon#about to read 3, iclass 28, count 2 2006.173.19:41:01.67#ibcon#read 3, iclass 28, count 2 2006.173.19:41:01.67#ibcon#about to read 4, iclass 28, count 2 2006.173.19:41:01.67#ibcon#read 4, iclass 28, count 2 2006.173.19:41:01.67#ibcon#about to read 5, iclass 28, count 2 2006.173.19:41:01.67#ibcon#read 5, iclass 28, count 2 2006.173.19:41:01.67#ibcon#about to read 6, iclass 28, count 2 2006.173.19:41:01.67#ibcon#read 6, iclass 28, count 2 2006.173.19:41:01.67#ibcon#end of sib2, iclass 28, count 2 2006.173.19:41:01.67#ibcon#*after write, iclass 28, count 2 2006.173.19:41:01.67#ibcon#*before return 0, iclass 28, count 2 2006.173.19:41:01.67#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.19:41:01.67#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.19:41:01.67#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.19:41:01.67#ibcon#ireg 7 cls_cnt 0 2006.173.19:41:01.67#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.19:41:01.79#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.19:41:01.79#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.19:41:01.79#ibcon#enter wrdev, iclass 28, count 0 2006.173.19:41:01.79#ibcon#first serial, iclass 28, count 0 2006.173.19:41:01.79#ibcon#enter sib2, iclass 28, count 0 2006.173.19:41:01.79#ibcon#flushed, iclass 28, count 0 2006.173.19:41:01.79#ibcon#about to write, iclass 28, count 0 2006.173.19:41:01.79#ibcon#wrote, iclass 28, count 0 2006.173.19:41:01.79#ibcon#about to read 3, iclass 28, count 0 2006.173.19:41:01.81#ibcon#read 3, iclass 28, count 0 2006.173.19:41:01.81#ibcon#about to read 4, iclass 28, count 0 2006.173.19:41:01.81#ibcon#read 4, iclass 28, count 0 2006.173.19:41:01.81#ibcon#about to read 5, iclass 28, count 0 2006.173.19:41:01.81#ibcon#read 5, iclass 28, count 0 2006.173.19:41:01.81#ibcon#about to read 6, iclass 28, count 0 2006.173.19:41:01.81#ibcon#read 6, iclass 28, count 0 2006.173.19:41:01.81#ibcon#end of sib2, iclass 28, count 0 2006.173.19:41:01.81#ibcon#*mode == 0, iclass 28, count 0 2006.173.19:41:01.81#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.19:41:01.81#ibcon#[25=USB\r\n] 2006.173.19:41:01.81#ibcon#*before write, iclass 28, count 0 2006.173.19:41:01.81#ibcon#enter sib2, iclass 28, count 0 2006.173.19:41:01.81#ibcon#flushed, iclass 28, count 0 2006.173.19:41:01.81#ibcon#about to write, iclass 28, count 0 2006.173.19:41:01.81#ibcon#wrote, iclass 28, count 0 2006.173.19:41:01.81#ibcon#about to read 3, iclass 28, count 0 2006.173.19:41:01.84#ibcon#read 3, iclass 28, count 0 2006.173.19:41:01.84#ibcon#about to read 4, iclass 28, count 0 2006.173.19:41:01.84#ibcon#read 4, iclass 28, count 0 2006.173.19:41:01.84#ibcon#about to read 5, iclass 28, count 0 2006.173.19:41:01.84#ibcon#read 5, iclass 28, count 0 2006.173.19:41:01.84#ibcon#about to read 6, iclass 28, count 0 2006.173.19:41:01.84#ibcon#read 6, iclass 28, count 0 2006.173.19:41:01.84#ibcon#end of sib2, iclass 28, count 0 2006.173.19:41:01.84#ibcon#*after write, iclass 28, count 0 2006.173.19:41:01.84#ibcon#*before return 0, iclass 28, count 0 2006.173.19:41:01.84#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.19:41:01.84#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.19:41:01.84#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.19:41:01.84#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.19:41:01.84$vck44/valo=3,564.99 2006.173.19:41:01.84#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.19:41:01.84#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.19:41:01.84#ibcon#ireg 17 cls_cnt 0 2006.173.19:41:01.84#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.19:41:01.84#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.19:41:01.84#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.19:41:01.84#ibcon#enter wrdev, iclass 30, count 0 2006.173.19:41:01.84#ibcon#first serial, iclass 30, count 0 2006.173.19:41:01.84#ibcon#enter sib2, iclass 30, count 0 2006.173.19:41:01.84#ibcon#flushed, iclass 30, count 0 2006.173.19:41:01.84#ibcon#about to write, iclass 30, count 0 2006.173.19:41:01.84#ibcon#wrote, iclass 30, count 0 2006.173.19:41:01.84#ibcon#about to read 3, iclass 30, count 0 2006.173.19:41:01.86#ibcon#read 3, iclass 30, count 0 2006.173.19:41:01.86#ibcon#about to read 4, iclass 30, count 0 2006.173.19:41:01.86#ibcon#read 4, iclass 30, count 0 2006.173.19:41:01.86#ibcon#about to read 5, iclass 30, count 0 2006.173.19:41:01.86#ibcon#read 5, iclass 30, count 0 2006.173.19:41:01.86#ibcon#about to read 6, iclass 30, count 0 2006.173.19:41:01.86#ibcon#read 6, iclass 30, count 0 2006.173.19:41:01.86#ibcon#end of sib2, iclass 30, count 0 2006.173.19:41:01.86#ibcon#*mode == 0, iclass 30, count 0 2006.173.19:41:01.86#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.19:41:01.86#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.19:41:01.86#ibcon#*before write, iclass 30, count 0 2006.173.19:41:01.86#ibcon#enter sib2, iclass 30, count 0 2006.173.19:41:01.86#ibcon#flushed, iclass 30, count 0 2006.173.19:41:01.86#ibcon#about to write, iclass 30, count 0 2006.173.19:41:01.86#ibcon#wrote, iclass 30, count 0 2006.173.19:41:01.86#ibcon#about to read 3, iclass 30, count 0 2006.173.19:41:01.90#ibcon#read 3, iclass 30, count 0 2006.173.19:41:01.90#ibcon#about to read 4, iclass 30, count 0 2006.173.19:41:01.90#ibcon#read 4, iclass 30, count 0 2006.173.19:41:01.90#ibcon#about to read 5, iclass 30, count 0 2006.173.19:41:01.90#ibcon#read 5, iclass 30, count 0 2006.173.19:41:01.90#ibcon#about to read 6, iclass 30, count 0 2006.173.19:41:01.90#ibcon#read 6, iclass 30, count 0 2006.173.19:41:01.90#ibcon#end of sib2, iclass 30, count 0 2006.173.19:41:01.90#ibcon#*after write, iclass 30, count 0 2006.173.19:41:01.90#ibcon#*before return 0, iclass 30, count 0 2006.173.19:41:01.90#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.19:41:01.90#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.19:41:01.90#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.19:41:01.90#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.19:41:01.90$vck44/va=3,5 2006.173.19:41:01.90#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.173.19:41:01.90#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.173.19:41:01.90#ibcon#ireg 11 cls_cnt 2 2006.173.19:41:01.90#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.19:41:01.96#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.19:41:01.96#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.19:41:01.96#ibcon#enter wrdev, iclass 32, count 2 2006.173.19:41:01.96#ibcon#first serial, iclass 32, count 2 2006.173.19:41:01.96#ibcon#enter sib2, iclass 32, count 2 2006.173.19:41:01.96#ibcon#flushed, iclass 32, count 2 2006.173.19:41:01.96#ibcon#about to write, iclass 32, count 2 2006.173.19:41:01.96#ibcon#wrote, iclass 32, count 2 2006.173.19:41:01.96#ibcon#about to read 3, iclass 32, count 2 2006.173.19:41:01.98#ibcon#read 3, iclass 32, count 2 2006.173.19:41:01.98#ibcon#about to read 4, iclass 32, count 2 2006.173.19:41:01.98#ibcon#read 4, iclass 32, count 2 2006.173.19:41:01.98#ibcon#about to read 5, iclass 32, count 2 2006.173.19:41:01.98#ibcon#read 5, iclass 32, count 2 2006.173.19:41:01.98#ibcon#about to read 6, iclass 32, count 2 2006.173.19:41:01.98#ibcon#read 6, iclass 32, count 2 2006.173.19:41:01.98#ibcon#end of sib2, iclass 32, count 2 2006.173.19:41:01.98#ibcon#*mode == 0, iclass 32, count 2 2006.173.19:41:01.98#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.173.19:41:01.98#ibcon#[25=AT03-05\r\n] 2006.173.19:41:01.98#ibcon#*before write, iclass 32, count 2 2006.173.19:41:01.98#ibcon#enter sib2, iclass 32, count 2 2006.173.19:41:01.98#ibcon#flushed, iclass 32, count 2 2006.173.19:41:01.98#ibcon#about to write, iclass 32, count 2 2006.173.19:41:01.98#ibcon#wrote, iclass 32, count 2 2006.173.19:41:01.98#ibcon#about to read 3, iclass 32, count 2 2006.173.19:41:02.01#ibcon#read 3, iclass 32, count 2 2006.173.19:41:02.01#ibcon#about to read 4, iclass 32, count 2 2006.173.19:41:02.01#ibcon#read 4, iclass 32, count 2 2006.173.19:41:02.01#ibcon#about to read 5, iclass 32, count 2 2006.173.19:41:02.01#ibcon#read 5, iclass 32, count 2 2006.173.19:41:02.01#ibcon#about to read 6, iclass 32, count 2 2006.173.19:41:02.01#ibcon#read 6, iclass 32, count 2 2006.173.19:41:02.01#ibcon#end of sib2, iclass 32, count 2 2006.173.19:41:02.01#ibcon#*after write, iclass 32, count 2 2006.173.19:41:02.01#ibcon#*before return 0, iclass 32, count 2 2006.173.19:41:02.01#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.19:41:02.01#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.173.19:41:02.01#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.173.19:41:02.01#ibcon#ireg 7 cls_cnt 0 2006.173.19:41:02.01#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.19:41:02.13#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.19:41:02.13#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.19:41:02.13#ibcon#enter wrdev, iclass 32, count 0 2006.173.19:41:02.13#ibcon#first serial, iclass 32, count 0 2006.173.19:41:02.13#ibcon#enter sib2, iclass 32, count 0 2006.173.19:41:02.13#ibcon#flushed, iclass 32, count 0 2006.173.19:41:02.13#ibcon#about to write, iclass 32, count 0 2006.173.19:41:02.13#ibcon#wrote, iclass 32, count 0 2006.173.19:41:02.13#ibcon#about to read 3, iclass 32, count 0 2006.173.19:41:02.15#ibcon#read 3, iclass 32, count 0 2006.173.19:41:02.15#ibcon#about to read 4, iclass 32, count 0 2006.173.19:41:02.15#ibcon#read 4, iclass 32, count 0 2006.173.19:41:02.15#ibcon#about to read 5, iclass 32, count 0 2006.173.19:41:02.15#ibcon#read 5, iclass 32, count 0 2006.173.19:41:02.15#ibcon#about to read 6, iclass 32, count 0 2006.173.19:41:02.15#ibcon#read 6, iclass 32, count 0 2006.173.19:41:02.15#ibcon#end of sib2, iclass 32, count 0 2006.173.19:41:02.15#ibcon#*mode == 0, iclass 32, count 0 2006.173.19:41:02.15#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.19:41:02.15#ibcon#[25=USB\r\n] 2006.173.19:41:02.15#ibcon#*before write, iclass 32, count 0 2006.173.19:41:02.15#ibcon#enter sib2, iclass 32, count 0 2006.173.19:41:02.15#ibcon#flushed, iclass 32, count 0 2006.173.19:41:02.15#ibcon#about to write, iclass 32, count 0 2006.173.19:41:02.15#ibcon#wrote, iclass 32, count 0 2006.173.19:41:02.15#ibcon#about to read 3, iclass 32, count 0 2006.173.19:41:02.18#ibcon#read 3, iclass 32, count 0 2006.173.19:41:02.18#ibcon#about to read 4, iclass 32, count 0 2006.173.19:41:02.18#ibcon#read 4, iclass 32, count 0 2006.173.19:41:02.18#ibcon#about to read 5, iclass 32, count 0 2006.173.19:41:02.18#ibcon#read 5, iclass 32, count 0 2006.173.19:41:02.18#ibcon#about to read 6, iclass 32, count 0 2006.173.19:41:02.18#ibcon#read 6, iclass 32, count 0 2006.173.19:41:02.18#ibcon#end of sib2, iclass 32, count 0 2006.173.19:41:02.18#ibcon#*after write, iclass 32, count 0 2006.173.19:41:02.18#ibcon#*before return 0, iclass 32, count 0 2006.173.19:41:02.18#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.19:41:02.18#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.173.19:41:02.18#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.19:41:02.18#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.19:41:02.18$vck44/valo=4,624.99 2006.173.19:41:02.18#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.19:41:02.18#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.19:41:02.18#ibcon#ireg 17 cls_cnt 0 2006.173.19:41:02.18#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.19:41:02.18#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.19:41:02.18#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.19:41:02.18#ibcon#enter wrdev, iclass 34, count 0 2006.173.19:41:02.18#ibcon#first serial, iclass 34, count 0 2006.173.19:41:02.18#ibcon#enter sib2, iclass 34, count 0 2006.173.19:41:02.18#ibcon#flushed, iclass 34, count 0 2006.173.19:41:02.18#ibcon#about to write, iclass 34, count 0 2006.173.19:41:02.18#ibcon#wrote, iclass 34, count 0 2006.173.19:41:02.18#ibcon#about to read 3, iclass 34, count 0 2006.173.19:41:02.20#ibcon#read 3, iclass 34, count 0 2006.173.19:41:02.20#ibcon#about to read 4, iclass 34, count 0 2006.173.19:41:02.20#ibcon#read 4, iclass 34, count 0 2006.173.19:41:02.20#ibcon#about to read 5, iclass 34, count 0 2006.173.19:41:02.20#ibcon#read 5, iclass 34, count 0 2006.173.19:41:02.20#ibcon#about to read 6, iclass 34, count 0 2006.173.19:41:02.20#ibcon#read 6, iclass 34, count 0 2006.173.19:41:02.20#ibcon#end of sib2, iclass 34, count 0 2006.173.19:41:02.20#ibcon#*mode == 0, iclass 34, count 0 2006.173.19:41:02.20#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.19:41:02.20#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.19:41:02.20#ibcon#*before write, iclass 34, count 0 2006.173.19:41:02.20#ibcon#enter sib2, iclass 34, count 0 2006.173.19:41:02.20#ibcon#flushed, iclass 34, count 0 2006.173.19:41:02.20#ibcon#about to write, iclass 34, count 0 2006.173.19:41:02.20#ibcon#wrote, iclass 34, count 0 2006.173.19:41:02.20#ibcon#about to read 3, iclass 34, count 0 2006.173.19:41:02.24#ibcon#read 3, iclass 34, count 0 2006.173.19:41:02.24#ibcon#about to read 4, iclass 34, count 0 2006.173.19:41:02.24#ibcon#read 4, iclass 34, count 0 2006.173.19:41:02.24#ibcon#about to read 5, iclass 34, count 0 2006.173.19:41:02.24#ibcon#read 5, iclass 34, count 0 2006.173.19:41:02.24#ibcon#about to read 6, iclass 34, count 0 2006.173.19:41:02.24#ibcon#read 6, iclass 34, count 0 2006.173.19:41:02.24#ibcon#end of sib2, iclass 34, count 0 2006.173.19:41:02.24#ibcon#*after write, iclass 34, count 0 2006.173.19:41:02.24#ibcon#*before return 0, iclass 34, count 0 2006.173.19:41:02.24#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.19:41:02.24#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.19:41:02.24#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.19:41:02.24#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.19:41:02.24$vck44/va=4,6 2006.173.19:41:02.24#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.19:41:02.24#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.19:41:02.24#ibcon#ireg 11 cls_cnt 2 2006.173.19:41:02.24#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.19:41:02.30#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.19:41:02.30#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.19:41:02.30#ibcon#enter wrdev, iclass 36, count 2 2006.173.19:41:02.30#ibcon#first serial, iclass 36, count 2 2006.173.19:41:02.30#ibcon#enter sib2, iclass 36, count 2 2006.173.19:41:02.30#ibcon#flushed, iclass 36, count 2 2006.173.19:41:02.30#ibcon#about to write, iclass 36, count 2 2006.173.19:41:02.30#ibcon#wrote, iclass 36, count 2 2006.173.19:41:02.30#ibcon#about to read 3, iclass 36, count 2 2006.173.19:41:02.32#ibcon#read 3, iclass 36, count 2 2006.173.19:41:02.32#ibcon#about to read 4, iclass 36, count 2 2006.173.19:41:02.32#ibcon#read 4, iclass 36, count 2 2006.173.19:41:02.32#ibcon#about to read 5, iclass 36, count 2 2006.173.19:41:02.32#ibcon#read 5, iclass 36, count 2 2006.173.19:41:02.32#ibcon#about to read 6, iclass 36, count 2 2006.173.19:41:02.32#ibcon#read 6, iclass 36, count 2 2006.173.19:41:02.32#ibcon#end of sib2, iclass 36, count 2 2006.173.19:41:02.32#ibcon#*mode == 0, iclass 36, count 2 2006.173.19:41:02.32#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.19:41:02.32#ibcon#[25=AT04-06\r\n] 2006.173.19:41:02.32#ibcon#*before write, iclass 36, count 2 2006.173.19:41:02.32#ibcon#enter sib2, iclass 36, count 2 2006.173.19:41:02.32#ibcon#flushed, iclass 36, count 2 2006.173.19:41:02.32#ibcon#about to write, iclass 36, count 2 2006.173.19:41:02.32#ibcon#wrote, iclass 36, count 2 2006.173.19:41:02.32#ibcon#about to read 3, iclass 36, count 2 2006.173.19:41:02.35#ibcon#read 3, iclass 36, count 2 2006.173.19:41:02.35#ibcon#about to read 4, iclass 36, count 2 2006.173.19:41:02.35#ibcon#read 4, iclass 36, count 2 2006.173.19:41:02.35#ibcon#about to read 5, iclass 36, count 2 2006.173.19:41:02.35#ibcon#read 5, iclass 36, count 2 2006.173.19:41:02.35#ibcon#about to read 6, iclass 36, count 2 2006.173.19:41:02.35#ibcon#read 6, iclass 36, count 2 2006.173.19:41:02.35#ibcon#end of sib2, iclass 36, count 2 2006.173.19:41:02.35#ibcon#*after write, iclass 36, count 2 2006.173.19:41:02.35#ibcon#*before return 0, iclass 36, count 2 2006.173.19:41:02.35#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.19:41:02.35#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.19:41:02.35#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.19:41:02.35#ibcon#ireg 7 cls_cnt 0 2006.173.19:41:02.35#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.19:41:02.47#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.19:41:02.47#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.19:41:02.47#ibcon#enter wrdev, iclass 36, count 0 2006.173.19:41:02.47#ibcon#first serial, iclass 36, count 0 2006.173.19:41:02.47#ibcon#enter sib2, iclass 36, count 0 2006.173.19:41:02.47#ibcon#flushed, iclass 36, count 0 2006.173.19:41:02.47#ibcon#about to write, iclass 36, count 0 2006.173.19:41:02.47#ibcon#wrote, iclass 36, count 0 2006.173.19:41:02.47#ibcon#about to read 3, iclass 36, count 0 2006.173.19:41:02.49#ibcon#read 3, iclass 36, count 0 2006.173.19:41:02.49#ibcon#about to read 4, iclass 36, count 0 2006.173.19:41:02.49#ibcon#read 4, iclass 36, count 0 2006.173.19:41:02.49#ibcon#about to read 5, iclass 36, count 0 2006.173.19:41:02.49#ibcon#read 5, iclass 36, count 0 2006.173.19:41:02.49#ibcon#about to read 6, iclass 36, count 0 2006.173.19:41:02.49#ibcon#read 6, iclass 36, count 0 2006.173.19:41:02.49#ibcon#end of sib2, iclass 36, count 0 2006.173.19:41:02.49#ibcon#*mode == 0, iclass 36, count 0 2006.173.19:41:02.49#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.19:41:02.49#ibcon#[25=USB\r\n] 2006.173.19:41:02.49#ibcon#*before write, iclass 36, count 0 2006.173.19:41:02.49#ibcon#enter sib2, iclass 36, count 0 2006.173.19:41:02.49#ibcon#flushed, iclass 36, count 0 2006.173.19:41:02.49#ibcon#about to write, iclass 36, count 0 2006.173.19:41:02.49#ibcon#wrote, iclass 36, count 0 2006.173.19:41:02.49#ibcon#about to read 3, iclass 36, count 0 2006.173.19:41:02.52#ibcon#read 3, iclass 36, count 0 2006.173.19:41:02.52#ibcon#about to read 4, iclass 36, count 0 2006.173.19:41:02.52#ibcon#read 4, iclass 36, count 0 2006.173.19:41:02.52#ibcon#about to read 5, iclass 36, count 0 2006.173.19:41:02.52#ibcon#read 5, iclass 36, count 0 2006.173.19:41:02.52#ibcon#about to read 6, iclass 36, count 0 2006.173.19:41:02.52#ibcon#read 6, iclass 36, count 0 2006.173.19:41:02.52#ibcon#end of sib2, iclass 36, count 0 2006.173.19:41:02.52#ibcon#*after write, iclass 36, count 0 2006.173.19:41:02.52#ibcon#*before return 0, iclass 36, count 0 2006.173.19:41:02.52#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.19:41:02.52#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.19:41:02.52#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.19:41:02.52#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.19:41:02.52$vck44/valo=5,734.99 2006.173.19:41:02.52#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.19:41:02.52#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.19:41:02.52#ibcon#ireg 17 cls_cnt 0 2006.173.19:41:02.52#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.19:41:02.52#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.19:41:02.52#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.19:41:02.52#ibcon#enter wrdev, iclass 38, count 0 2006.173.19:41:02.52#ibcon#first serial, iclass 38, count 0 2006.173.19:41:02.52#ibcon#enter sib2, iclass 38, count 0 2006.173.19:41:02.52#ibcon#flushed, iclass 38, count 0 2006.173.19:41:02.52#ibcon#about to write, iclass 38, count 0 2006.173.19:41:02.52#ibcon#wrote, iclass 38, count 0 2006.173.19:41:02.52#ibcon#about to read 3, iclass 38, count 0 2006.173.19:41:02.54#ibcon#read 3, iclass 38, count 0 2006.173.19:41:02.54#ibcon#about to read 4, iclass 38, count 0 2006.173.19:41:02.54#ibcon#read 4, iclass 38, count 0 2006.173.19:41:02.54#ibcon#about to read 5, iclass 38, count 0 2006.173.19:41:02.54#ibcon#read 5, iclass 38, count 0 2006.173.19:41:02.54#ibcon#about to read 6, iclass 38, count 0 2006.173.19:41:02.54#ibcon#read 6, iclass 38, count 0 2006.173.19:41:02.54#ibcon#end of sib2, iclass 38, count 0 2006.173.19:41:02.54#ibcon#*mode == 0, iclass 38, count 0 2006.173.19:41:02.54#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.19:41:02.54#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.19:41:02.54#ibcon#*before write, iclass 38, count 0 2006.173.19:41:02.54#ibcon#enter sib2, iclass 38, count 0 2006.173.19:41:02.54#ibcon#flushed, iclass 38, count 0 2006.173.19:41:02.54#ibcon#about to write, iclass 38, count 0 2006.173.19:41:02.54#ibcon#wrote, iclass 38, count 0 2006.173.19:41:02.54#ibcon#about to read 3, iclass 38, count 0 2006.173.19:41:02.58#ibcon#read 3, iclass 38, count 0 2006.173.19:41:02.58#ibcon#about to read 4, iclass 38, count 0 2006.173.19:41:02.58#ibcon#read 4, iclass 38, count 0 2006.173.19:41:02.58#ibcon#about to read 5, iclass 38, count 0 2006.173.19:41:02.58#ibcon#read 5, iclass 38, count 0 2006.173.19:41:02.58#ibcon#about to read 6, iclass 38, count 0 2006.173.19:41:02.58#ibcon#read 6, iclass 38, count 0 2006.173.19:41:02.58#ibcon#end of sib2, iclass 38, count 0 2006.173.19:41:02.58#ibcon#*after write, iclass 38, count 0 2006.173.19:41:02.58#ibcon#*before return 0, iclass 38, count 0 2006.173.19:41:02.58#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.19:41:02.58#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.19:41:02.58#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.19:41:02.58#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.19:41:02.58$vck44/va=5,4 2006.173.19:41:02.58#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.19:41:02.58#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.19:41:02.58#ibcon#ireg 11 cls_cnt 2 2006.173.19:41:02.58#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.19:41:02.64#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.19:41:02.64#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.19:41:02.64#ibcon#enter wrdev, iclass 40, count 2 2006.173.19:41:02.64#ibcon#first serial, iclass 40, count 2 2006.173.19:41:02.64#ibcon#enter sib2, iclass 40, count 2 2006.173.19:41:02.64#ibcon#flushed, iclass 40, count 2 2006.173.19:41:02.64#ibcon#about to write, iclass 40, count 2 2006.173.19:41:02.64#ibcon#wrote, iclass 40, count 2 2006.173.19:41:02.64#ibcon#about to read 3, iclass 40, count 2 2006.173.19:41:02.66#ibcon#read 3, iclass 40, count 2 2006.173.19:41:02.66#ibcon#about to read 4, iclass 40, count 2 2006.173.19:41:02.66#ibcon#read 4, iclass 40, count 2 2006.173.19:41:02.66#ibcon#about to read 5, iclass 40, count 2 2006.173.19:41:02.66#ibcon#read 5, iclass 40, count 2 2006.173.19:41:02.66#ibcon#about to read 6, iclass 40, count 2 2006.173.19:41:02.66#ibcon#read 6, iclass 40, count 2 2006.173.19:41:02.66#ibcon#end of sib2, iclass 40, count 2 2006.173.19:41:02.66#ibcon#*mode == 0, iclass 40, count 2 2006.173.19:41:02.66#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.19:41:02.66#ibcon#[25=AT05-04\r\n] 2006.173.19:41:02.66#ibcon#*before write, iclass 40, count 2 2006.173.19:41:02.66#ibcon#enter sib2, iclass 40, count 2 2006.173.19:41:02.66#ibcon#flushed, iclass 40, count 2 2006.173.19:41:02.66#ibcon#about to write, iclass 40, count 2 2006.173.19:41:02.66#ibcon#wrote, iclass 40, count 2 2006.173.19:41:02.66#ibcon#about to read 3, iclass 40, count 2 2006.173.19:41:02.69#ibcon#read 3, iclass 40, count 2 2006.173.19:41:02.69#ibcon#about to read 4, iclass 40, count 2 2006.173.19:41:02.69#ibcon#read 4, iclass 40, count 2 2006.173.19:41:02.69#ibcon#about to read 5, iclass 40, count 2 2006.173.19:41:02.69#ibcon#read 5, iclass 40, count 2 2006.173.19:41:02.69#ibcon#about to read 6, iclass 40, count 2 2006.173.19:41:02.69#ibcon#read 6, iclass 40, count 2 2006.173.19:41:02.69#ibcon#end of sib2, iclass 40, count 2 2006.173.19:41:02.69#ibcon#*after write, iclass 40, count 2 2006.173.19:41:02.69#ibcon#*before return 0, iclass 40, count 2 2006.173.19:41:02.69#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.19:41:02.69#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.19:41:02.69#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.19:41:02.69#ibcon#ireg 7 cls_cnt 0 2006.173.19:41:02.69#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.19:41:02.81#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.19:41:02.81#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.19:41:02.81#ibcon#enter wrdev, iclass 40, count 0 2006.173.19:41:02.81#ibcon#first serial, iclass 40, count 0 2006.173.19:41:02.81#ibcon#enter sib2, iclass 40, count 0 2006.173.19:41:02.81#ibcon#flushed, iclass 40, count 0 2006.173.19:41:02.81#ibcon#about to write, iclass 40, count 0 2006.173.19:41:02.81#ibcon#wrote, iclass 40, count 0 2006.173.19:41:02.81#ibcon#about to read 3, iclass 40, count 0 2006.173.19:41:02.83#ibcon#read 3, iclass 40, count 0 2006.173.19:41:02.83#ibcon#about to read 4, iclass 40, count 0 2006.173.19:41:02.83#ibcon#read 4, iclass 40, count 0 2006.173.19:41:02.83#ibcon#about to read 5, iclass 40, count 0 2006.173.19:41:02.83#ibcon#read 5, iclass 40, count 0 2006.173.19:41:02.83#ibcon#about to read 6, iclass 40, count 0 2006.173.19:41:02.83#ibcon#read 6, iclass 40, count 0 2006.173.19:41:02.83#ibcon#end of sib2, iclass 40, count 0 2006.173.19:41:02.83#ibcon#*mode == 0, iclass 40, count 0 2006.173.19:41:02.83#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.19:41:02.83#ibcon#[25=USB\r\n] 2006.173.19:41:02.83#ibcon#*before write, iclass 40, count 0 2006.173.19:41:02.83#ibcon#enter sib2, iclass 40, count 0 2006.173.19:41:02.83#ibcon#flushed, iclass 40, count 0 2006.173.19:41:02.83#ibcon#about to write, iclass 40, count 0 2006.173.19:41:02.83#ibcon#wrote, iclass 40, count 0 2006.173.19:41:02.83#ibcon#about to read 3, iclass 40, count 0 2006.173.19:41:02.86#ibcon#read 3, iclass 40, count 0 2006.173.19:41:02.86#ibcon#about to read 4, iclass 40, count 0 2006.173.19:41:02.86#ibcon#read 4, iclass 40, count 0 2006.173.19:41:02.86#ibcon#about to read 5, iclass 40, count 0 2006.173.19:41:02.86#ibcon#read 5, iclass 40, count 0 2006.173.19:41:02.86#ibcon#about to read 6, iclass 40, count 0 2006.173.19:41:02.86#ibcon#read 6, iclass 40, count 0 2006.173.19:41:02.86#ibcon#end of sib2, iclass 40, count 0 2006.173.19:41:02.86#ibcon#*after write, iclass 40, count 0 2006.173.19:41:02.86#ibcon#*before return 0, iclass 40, count 0 2006.173.19:41:02.86#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.19:41:02.86#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.19:41:02.86#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.19:41:02.86#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.19:41:02.86$vck44/valo=6,814.99 2006.173.19:41:02.86#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.19:41:02.86#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.19:41:02.86#ibcon#ireg 17 cls_cnt 0 2006.173.19:41:02.86#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.19:41:02.86#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.19:41:02.86#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.19:41:02.86#ibcon#enter wrdev, iclass 4, count 0 2006.173.19:41:02.86#ibcon#first serial, iclass 4, count 0 2006.173.19:41:02.86#ibcon#enter sib2, iclass 4, count 0 2006.173.19:41:02.86#ibcon#flushed, iclass 4, count 0 2006.173.19:41:02.86#ibcon#about to write, iclass 4, count 0 2006.173.19:41:02.86#ibcon#wrote, iclass 4, count 0 2006.173.19:41:02.86#ibcon#about to read 3, iclass 4, count 0 2006.173.19:41:02.88#ibcon#read 3, iclass 4, count 0 2006.173.19:41:02.88#ibcon#about to read 4, iclass 4, count 0 2006.173.19:41:02.88#ibcon#read 4, iclass 4, count 0 2006.173.19:41:02.88#ibcon#about to read 5, iclass 4, count 0 2006.173.19:41:02.88#ibcon#read 5, iclass 4, count 0 2006.173.19:41:02.88#ibcon#about to read 6, iclass 4, count 0 2006.173.19:41:02.88#ibcon#read 6, iclass 4, count 0 2006.173.19:41:02.88#ibcon#end of sib2, iclass 4, count 0 2006.173.19:41:02.88#ibcon#*mode == 0, iclass 4, count 0 2006.173.19:41:02.88#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.19:41:02.88#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.19:41:02.88#ibcon#*before write, iclass 4, count 0 2006.173.19:41:02.88#ibcon#enter sib2, iclass 4, count 0 2006.173.19:41:02.88#ibcon#flushed, iclass 4, count 0 2006.173.19:41:02.88#ibcon#about to write, iclass 4, count 0 2006.173.19:41:02.88#ibcon#wrote, iclass 4, count 0 2006.173.19:41:02.88#ibcon#about to read 3, iclass 4, count 0 2006.173.19:41:02.92#ibcon#read 3, iclass 4, count 0 2006.173.19:41:02.92#ibcon#about to read 4, iclass 4, count 0 2006.173.19:41:02.92#ibcon#read 4, iclass 4, count 0 2006.173.19:41:02.92#ibcon#about to read 5, iclass 4, count 0 2006.173.19:41:02.92#ibcon#read 5, iclass 4, count 0 2006.173.19:41:02.92#ibcon#about to read 6, iclass 4, count 0 2006.173.19:41:02.92#ibcon#read 6, iclass 4, count 0 2006.173.19:41:02.92#ibcon#end of sib2, iclass 4, count 0 2006.173.19:41:02.92#ibcon#*after write, iclass 4, count 0 2006.173.19:41:02.92#ibcon#*before return 0, iclass 4, count 0 2006.173.19:41:02.92#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.19:41:02.92#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.19:41:02.92#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.19:41:02.92#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.19:41:02.92$vck44/va=6,3 2006.173.19:41:02.92#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.19:41:02.92#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.19:41:02.92#ibcon#ireg 11 cls_cnt 2 2006.173.19:41:02.92#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.19:41:02.98#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.19:41:02.98#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.19:41:02.98#ibcon#enter wrdev, iclass 6, count 2 2006.173.19:41:02.98#ibcon#first serial, iclass 6, count 2 2006.173.19:41:02.98#ibcon#enter sib2, iclass 6, count 2 2006.173.19:41:02.98#ibcon#flushed, iclass 6, count 2 2006.173.19:41:02.98#ibcon#about to write, iclass 6, count 2 2006.173.19:41:02.98#ibcon#wrote, iclass 6, count 2 2006.173.19:41:02.98#ibcon#about to read 3, iclass 6, count 2 2006.173.19:41:03.00#ibcon#read 3, iclass 6, count 2 2006.173.19:41:03.00#ibcon#about to read 4, iclass 6, count 2 2006.173.19:41:03.00#ibcon#read 4, iclass 6, count 2 2006.173.19:41:03.00#ibcon#about to read 5, iclass 6, count 2 2006.173.19:41:03.00#ibcon#read 5, iclass 6, count 2 2006.173.19:41:03.00#ibcon#about to read 6, iclass 6, count 2 2006.173.19:41:03.00#ibcon#read 6, iclass 6, count 2 2006.173.19:41:03.00#ibcon#end of sib2, iclass 6, count 2 2006.173.19:41:03.00#ibcon#*mode == 0, iclass 6, count 2 2006.173.19:41:03.00#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.19:41:03.00#ibcon#[25=AT06-03\r\n] 2006.173.19:41:03.00#ibcon#*before write, iclass 6, count 2 2006.173.19:41:03.00#ibcon#enter sib2, iclass 6, count 2 2006.173.19:41:03.00#ibcon#flushed, iclass 6, count 2 2006.173.19:41:03.00#ibcon#about to write, iclass 6, count 2 2006.173.19:41:03.00#ibcon#wrote, iclass 6, count 2 2006.173.19:41:03.00#ibcon#about to read 3, iclass 6, count 2 2006.173.19:41:03.03#ibcon#read 3, iclass 6, count 2 2006.173.19:41:03.03#ibcon#about to read 4, iclass 6, count 2 2006.173.19:41:03.03#ibcon#read 4, iclass 6, count 2 2006.173.19:41:03.03#ibcon#about to read 5, iclass 6, count 2 2006.173.19:41:03.03#ibcon#read 5, iclass 6, count 2 2006.173.19:41:03.03#ibcon#about to read 6, iclass 6, count 2 2006.173.19:41:03.03#ibcon#read 6, iclass 6, count 2 2006.173.19:41:03.03#ibcon#end of sib2, iclass 6, count 2 2006.173.19:41:03.03#ibcon#*after write, iclass 6, count 2 2006.173.19:41:03.03#ibcon#*before return 0, iclass 6, count 2 2006.173.19:41:03.03#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.19:41:03.03#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.19:41:03.03#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.19:41:03.03#ibcon#ireg 7 cls_cnt 0 2006.173.19:41:03.03#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.19:41:03.15#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.19:41:03.15#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.19:41:03.15#ibcon#enter wrdev, iclass 6, count 0 2006.173.19:41:03.15#ibcon#first serial, iclass 6, count 0 2006.173.19:41:03.15#ibcon#enter sib2, iclass 6, count 0 2006.173.19:41:03.15#ibcon#flushed, iclass 6, count 0 2006.173.19:41:03.15#ibcon#about to write, iclass 6, count 0 2006.173.19:41:03.15#ibcon#wrote, iclass 6, count 0 2006.173.19:41:03.15#ibcon#about to read 3, iclass 6, count 0 2006.173.19:41:03.17#ibcon#read 3, iclass 6, count 0 2006.173.19:41:03.17#ibcon#about to read 4, iclass 6, count 0 2006.173.19:41:03.17#ibcon#read 4, iclass 6, count 0 2006.173.19:41:03.17#ibcon#about to read 5, iclass 6, count 0 2006.173.19:41:03.17#ibcon#read 5, iclass 6, count 0 2006.173.19:41:03.17#ibcon#about to read 6, iclass 6, count 0 2006.173.19:41:03.17#ibcon#read 6, iclass 6, count 0 2006.173.19:41:03.17#ibcon#end of sib2, iclass 6, count 0 2006.173.19:41:03.17#ibcon#*mode == 0, iclass 6, count 0 2006.173.19:41:03.17#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.19:41:03.17#ibcon#[25=USB\r\n] 2006.173.19:41:03.17#ibcon#*before write, iclass 6, count 0 2006.173.19:41:03.17#ibcon#enter sib2, iclass 6, count 0 2006.173.19:41:03.17#ibcon#flushed, iclass 6, count 0 2006.173.19:41:03.17#ibcon#about to write, iclass 6, count 0 2006.173.19:41:03.17#ibcon#wrote, iclass 6, count 0 2006.173.19:41:03.17#ibcon#about to read 3, iclass 6, count 0 2006.173.19:41:03.20#ibcon#read 3, iclass 6, count 0 2006.173.19:41:03.20#ibcon#about to read 4, iclass 6, count 0 2006.173.19:41:03.20#ibcon#read 4, iclass 6, count 0 2006.173.19:41:03.20#ibcon#about to read 5, iclass 6, count 0 2006.173.19:41:03.20#ibcon#read 5, iclass 6, count 0 2006.173.19:41:03.20#ibcon#about to read 6, iclass 6, count 0 2006.173.19:41:03.20#ibcon#read 6, iclass 6, count 0 2006.173.19:41:03.20#ibcon#end of sib2, iclass 6, count 0 2006.173.19:41:03.20#ibcon#*after write, iclass 6, count 0 2006.173.19:41:03.20#ibcon#*before return 0, iclass 6, count 0 2006.173.19:41:03.20#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.19:41:03.20#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.19:41:03.20#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.19:41:03.20#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.19:41:03.20$vck44/valo=7,864.99 2006.173.19:41:03.20#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.19:41:03.20#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.19:41:03.20#ibcon#ireg 17 cls_cnt 0 2006.173.19:41:03.20#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.19:41:03.20#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.19:41:03.20#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.19:41:03.20#ibcon#enter wrdev, iclass 10, count 0 2006.173.19:41:03.20#ibcon#first serial, iclass 10, count 0 2006.173.19:41:03.20#ibcon#enter sib2, iclass 10, count 0 2006.173.19:41:03.20#ibcon#flushed, iclass 10, count 0 2006.173.19:41:03.20#ibcon#about to write, iclass 10, count 0 2006.173.19:41:03.20#ibcon#wrote, iclass 10, count 0 2006.173.19:41:03.20#ibcon#about to read 3, iclass 10, count 0 2006.173.19:41:03.22#ibcon#read 3, iclass 10, count 0 2006.173.19:41:03.22#ibcon#about to read 4, iclass 10, count 0 2006.173.19:41:03.22#ibcon#read 4, iclass 10, count 0 2006.173.19:41:03.22#ibcon#about to read 5, iclass 10, count 0 2006.173.19:41:03.22#ibcon#read 5, iclass 10, count 0 2006.173.19:41:03.22#ibcon#about to read 6, iclass 10, count 0 2006.173.19:41:03.22#ibcon#read 6, iclass 10, count 0 2006.173.19:41:03.22#ibcon#end of sib2, iclass 10, count 0 2006.173.19:41:03.22#ibcon#*mode == 0, iclass 10, count 0 2006.173.19:41:03.22#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.19:41:03.22#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.19:41:03.22#ibcon#*before write, iclass 10, count 0 2006.173.19:41:03.22#ibcon#enter sib2, iclass 10, count 0 2006.173.19:41:03.22#ibcon#flushed, iclass 10, count 0 2006.173.19:41:03.22#ibcon#about to write, iclass 10, count 0 2006.173.19:41:03.22#ibcon#wrote, iclass 10, count 0 2006.173.19:41:03.22#ibcon#about to read 3, iclass 10, count 0 2006.173.19:41:03.26#ibcon#read 3, iclass 10, count 0 2006.173.19:41:03.26#ibcon#about to read 4, iclass 10, count 0 2006.173.19:41:03.26#ibcon#read 4, iclass 10, count 0 2006.173.19:41:03.26#ibcon#about to read 5, iclass 10, count 0 2006.173.19:41:03.26#ibcon#read 5, iclass 10, count 0 2006.173.19:41:03.26#ibcon#about to read 6, iclass 10, count 0 2006.173.19:41:03.26#ibcon#read 6, iclass 10, count 0 2006.173.19:41:03.26#ibcon#end of sib2, iclass 10, count 0 2006.173.19:41:03.26#ibcon#*after write, iclass 10, count 0 2006.173.19:41:03.26#ibcon#*before return 0, iclass 10, count 0 2006.173.19:41:03.26#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.19:41:03.26#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.19:41:03.26#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.19:41:03.26#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.19:41:03.26$vck44/va=7,4 2006.173.19:41:03.26#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.19:41:03.26#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.19:41:03.26#ibcon#ireg 11 cls_cnt 2 2006.173.19:41:03.26#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.19:41:03.32#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.19:41:03.32#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.19:41:03.32#ibcon#enter wrdev, iclass 12, count 2 2006.173.19:41:03.32#ibcon#first serial, iclass 12, count 2 2006.173.19:41:03.32#ibcon#enter sib2, iclass 12, count 2 2006.173.19:41:03.32#ibcon#flushed, iclass 12, count 2 2006.173.19:41:03.32#ibcon#about to write, iclass 12, count 2 2006.173.19:41:03.32#ibcon#wrote, iclass 12, count 2 2006.173.19:41:03.32#ibcon#about to read 3, iclass 12, count 2 2006.173.19:41:03.34#ibcon#read 3, iclass 12, count 2 2006.173.19:41:03.34#ibcon#about to read 4, iclass 12, count 2 2006.173.19:41:03.34#ibcon#read 4, iclass 12, count 2 2006.173.19:41:03.34#ibcon#about to read 5, iclass 12, count 2 2006.173.19:41:03.34#ibcon#read 5, iclass 12, count 2 2006.173.19:41:03.34#ibcon#about to read 6, iclass 12, count 2 2006.173.19:41:03.34#ibcon#read 6, iclass 12, count 2 2006.173.19:41:03.34#ibcon#end of sib2, iclass 12, count 2 2006.173.19:41:03.34#ibcon#*mode == 0, iclass 12, count 2 2006.173.19:41:03.34#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.19:41:03.34#ibcon#[25=AT07-04\r\n] 2006.173.19:41:03.34#ibcon#*before write, iclass 12, count 2 2006.173.19:41:03.34#ibcon#enter sib2, iclass 12, count 2 2006.173.19:41:03.34#ibcon#flushed, iclass 12, count 2 2006.173.19:41:03.34#ibcon#about to write, iclass 12, count 2 2006.173.19:41:03.34#ibcon#wrote, iclass 12, count 2 2006.173.19:41:03.34#ibcon#about to read 3, iclass 12, count 2 2006.173.19:41:03.37#ibcon#read 3, iclass 12, count 2 2006.173.19:41:03.37#ibcon#about to read 4, iclass 12, count 2 2006.173.19:41:03.37#ibcon#read 4, iclass 12, count 2 2006.173.19:41:03.37#ibcon#about to read 5, iclass 12, count 2 2006.173.19:41:03.37#ibcon#read 5, iclass 12, count 2 2006.173.19:41:03.37#ibcon#about to read 6, iclass 12, count 2 2006.173.19:41:03.37#ibcon#read 6, iclass 12, count 2 2006.173.19:41:03.37#ibcon#end of sib2, iclass 12, count 2 2006.173.19:41:03.37#ibcon#*after write, iclass 12, count 2 2006.173.19:41:03.37#ibcon#*before return 0, iclass 12, count 2 2006.173.19:41:03.37#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.19:41:03.37#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.19:41:03.37#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.19:41:03.37#ibcon#ireg 7 cls_cnt 0 2006.173.19:41:03.37#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.19:41:03.49#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.19:41:03.49#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.19:41:03.49#ibcon#enter wrdev, iclass 12, count 0 2006.173.19:41:03.49#ibcon#first serial, iclass 12, count 0 2006.173.19:41:03.49#ibcon#enter sib2, iclass 12, count 0 2006.173.19:41:03.49#ibcon#flushed, iclass 12, count 0 2006.173.19:41:03.49#ibcon#about to write, iclass 12, count 0 2006.173.19:41:03.49#ibcon#wrote, iclass 12, count 0 2006.173.19:41:03.49#ibcon#about to read 3, iclass 12, count 0 2006.173.19:41:03.51#ibcon#read 3, iclass 12, count 0 2006.173.19:41:03.51#ibcon#about to read 4, iclass 12, count 0 2006.173.19:41:03.51#ibcon#read 4, iclass 12, count 0 2006.173.19:41:03.51#ibcon#about to read 5, iclass 12, count 0 2006.173.19:41:03.51#ibcon#read 5, iclass 12, count 0 2006.173.19:41:03.51#ibcon#about to read 6, iclass 12, count 0 2006.173.19:41:03.51#ibcon#read 6, iclass 12, count 0 2006.173.19:41:03.51#ibcon#end of sib2, iclass 12, count 0 2006.173.19:41:03.51#ibcon#*mode == 0, iclass 12, count 0 2006.173.19:41:03.51#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.19:41:03.51#ibcon#[25=USB\r\n] 2006.173.19:41:03.51#ibcon#*before write, iclass 12, count 0 2006.173.19:41:03.51#ibcon#enter sib2, iclass 12, count 0 2006.173.19:41:03.51#ibcon#flushed, iclass 12, count 0 2006.173.19:41:03.51#ibcon#about to write, iclass 12, count 0 2006.173.19:41:03.51#ibcon#wrote, iclass 12, count 0 2006.173.19:41:03.51#ibcon#about to read 3, iclass 12, count 0 2006.173.19:41:03.54#ibcon#read 3, iclass 12, count 0 2006.173.19:41:03.54#ibcon#about to read 4, iclass 12, count 0 2006.173.19:41:03.54#ibcon#read 4, iclass 12, count 0 2006.173.19:41:03.54#ibcon#about to read 5, iclass 12, count 0 2006.173.19:41:03.54#ibcon#read 5, iclass 12, count 0 2006.173.19:41:03.54#ibcon#about to read 6, iclass 12, count 0 2006.173.19:41:03.54#ibcon#read 6, iclass 12, count 0 2006.173.19:41:03.54#ibcon#end of sib2, iclass 12, count 0 2006.173.19:41:03.54#ibcon#*after write, iclass 12, count 0 2006.173.19:41:03.54#ibcon#*before return 0, iclass 12, count 0 2006.173.19:41:03.54#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.19:41:03.54#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.19:41:03.54#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.19:41:03.54#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.19:41:03.54$vck44/valo=8,884.99 2006.173.19:41:03.54#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.19:41:03.54#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.19:41:03.54#ibcon#ireg 17 cls_cnt 0 2006.173.19:41:03.54#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.19:41:03.54#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.19:41:03.54#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.19:41:03.54#ibcon#enter wrdev, iclass 14, count 0 2006.173.19:41:03.54#ibcon#first serial, iclass 14, count 0 2006.173.19:41:03.54#ibcon#enter sib2, iclass 14, count 0 2006.173.19:41:03.54#ibcon#flushed, iclass 14, count 0 2006.173.19:41:03.54#ibcon#about to write, iclass 14, count 0 2006.173.19:41:03.54#ibcon#wrote, iclass 14, count 0 2006.173.19:41:03.54#ibcon#about to read 3, iclass 14, count 0 2006.173.19:41:03.56#ibcon#read 3, iclass 14, count 0 2006.173.19:41:03.56#ibcon#about to read 4, iclass 14, count 0 2006.173.19:41:03.56#ibcon#read 4, iclass 14, count 0 2006.173.19:41:03.56#ibcon#about to read 5, iclass 14, count 0 2006.173.19:41:03.56#ibcon#read 5, iclass 14, count 0 2006.173.19:41:03.56#ibcon#about to read 6, iclass 14, count 0 2006.173.19:41:03.56#ibcon#read 6, iclass 14, count 0 2006.173.19:41:03.56#ibcon#end of sib2, iclass 14, count 0 2006.173.19:41:03.56#ibcon#*mode == 0, iclass 14, count 0 2006.173.19:41:03.56#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.19:41:03.56#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.19:41:03.56#ibcon#*before write, iclass 14, count 0 2006.173.19:41:03.56#ibcon#enter sib2, iclass 14, count 0 2006.173.19:41:03.56#ibcon#flushed, iclass 14, count 0 2006.173.19:41:03.56#ibcon#about to write, iclass 14, count 0 2006.173.19:41:03.56#ibcon#wrote, iclass 14, count 0 2006.173.19:41:03.56#ibcon#about to read 3, iclass 14, count 0 2006.173.19:41:03.60#ibcon#read 3, iclass 14, count 0 2006.173.19:41:03.60#ibcon#about to read 4, iclass 14, count 0 2006.173.19:41:03.60#ibcon#read 4, iclass 14, count 0 2006.173.19:41:03.60#ibcon#about to read 5, iclass 14, count 0 2006.173.19:41:03.60#ibcon#read 5, iclass 14, count 0 2006.173.19:41:03.60#ibcon#about to read 6, iclass 14, count 0 2006.173.19:41:03.60#ibcon#read 6, iclass 14, count 0 2006.173.19:41:03.60#ibcon#end of sib2, iclass 14, count 0 2006.173.19:41:03.60#ibcon#*after write, iclass 14, count 0 2006.173.19:41:03.60#ibcon#*before return 0, iclass 14, count 0 2006.173.19:41:03.60#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.19:41:03.60#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.19:41:03.60#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.19:41:03.60#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.19:41:03.60$vck44/va=8,4 2006.173.19:41:03.60#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.19:41:03.60#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.19:41:03.60#ibcon#ireg 11 cls_cnt 2 2006.173.19:41:03.60#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.19:41:03.66#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.19:41:03.66#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.19:41:03.66#ibcon#enter wrdev, iclass 16, count 2 2006.173.19:41:03.66#ibcon#first serial, iclass 16, count 2 2006.173.19:41:03.66#ibcon#enter sib2, iclass 16, count 2 2006.173.19:41:03.66#ibcon#flushed, iclass 16, count 2 2006.173.19:41:03.66#ibcon#about to write, iclass 16, count 2 2006.173.19:41:03.66#ibcon#wrote, iclass 16, count 2 2006.173.19:41:03.66#ibcon#about to read 3, iclass 16, count 2 2006.173.19:41:03.68#ibcon#read 3, iclass 16, count 2 2006.173.19:41:03.68#ibcon#about to read 4, iclass 16, count 2 2006.173.19:41:03.68#ibcon#read 4, iclass 16, count 2 2006.173.19:41:03.68#ibcon#about to read 5, iclass 16, count 2 2006.173.19:41:03.68#ibcon#read 5, iclass 16, count 2 2006.173.19:41:03.68#ibcon#about to read 6, iclass 16, count 2 2006.173.19:41:03.68#ibcon#read 6, iclass 16, count 2 2006.173.19:41:03.68#ibcon#end of sib2, iclass 16, count 2 2006.173.19:41:03.68#ibcon#*mode == 0, iclass 16, count 2 2006.173.19:41:03.68#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.19:41:03.68#ibcon#[25=AT08-04\r\n] 2006.173.19:41:03.68#ibcon#*before write, iclass 16, count 2 2006.173.19:41:03.68#ibcon#enter sib2, iclass 16, count 2 2006.173.19:41:03.68#ibcon#flushed, iclass 16, count 2 2006.173.19:41:03.68#ibcon#about to write, iclass 16, count 2 2006.173.19:41:03.68#ibcon#wrote, iclass 16, count 2 2006.173.19:41:03.68#ibcon#about to read 3, iclass 16, count 2 2006.173.19:41:03.71#ibcon#read 3, iclass 16, count 2 2006.173.19:41:03.71#ibcon#about to read 4, iclass 16, count 2 2006.173.19:41:03.71#ibcon#read 4, iclass 16, count 2 2006.173.19:41:03.71#ibcon#about to read 5, iclass 16, count 2 2006.173.19:41:03.71#ibcon#read 5, iclass 16, count 2 2006.173.19:41:03.71#ibcon#about to read 6, iclass 16, count 2 2006.173.19:41:03.71#ibcon#read 6, iclass 16, count 2 2006.173.19:41:03.71#ibcon#end of sib2, iclass 16, count 2 2006.173.19:41:03.71#ibcon#*after write, iclass 16, count 2 2006.173.19:41:03.71#ibcon#*before return 0, iclass 16, count 2 2006.173.19:41:03.71#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.19:41:03.71#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.19:41:03.71#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.19:41:03.71#ibcon#ireg 7 cls_cnt 0 2006.173.19:41:03.71#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.19:41:03.83#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.19:41:03.83#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.19:41:03.83#ibcon#enter wrdev, iclass 16, count 0 2006.173.19:41:03.83#ibcon#first serial, iclass 16, count 0 2006.173.19:41:03.83#ibcon#enter sib2, iclass 16, count 0 2006.173.19:41:03.83#ibcon#flushed, iclass 16, count 0 2006.173.19:41:03.83#ibcon#about to write, iclass 16, count 0 2006.173.19:41:03.83#ibcon#wrote, iclass 16, count 0 2006.173.19:41:03.83#ibcon#about to read 3, iclass 16, count 0 2006.173.19:41:03.85#ibcon#read 3, iclass 16, count 0 2006.173.19:41:03.85#ibcon#about to read 4, iclass 16, count 0 2006.173.19:41:03.85#ibcon#read 4, iclass 16, count 0 2006.173.19:41:03.85#ibcon#about to read 5, iclass 16, count 0 2006.173.19:41:03.85#ibcon#read 5, iclass 16, count 0 2006.173.19:41:03.85#ibcon#about to read 6, iclass 16, count 0 2006.173.19:41:03.85#ibcon#read 6, iclass 16, count 0 2006.173.19:41:03.85#ibcon#end of sib2, iclass 16, count 0 2006.173.19:41:03.85#ibcon#*mode == 0, iclass 16, count 0 2006.173.19:41:03.85#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.19:41:03.85#ibcon#[25=USB\r\n] 2006.173.19:41:03.85#ibcon#*before write, iclass 16, count 0 2006.173.19:41:03.85#ibcon#enter sib2, iclass 16, count 0 2006.173.19:41:03.85#ibcon#flushed, iclass 16, count 0 2006.173.19:41:03.85#ibcon#about to write, iclass 16, count 0 2006.173.19:41:03.85#ibcon#wrote, iclass 16, count 0 2006.173.19:41:03.85#ibcon#about to read 3, iclass 16, count 0 2006.173.19:41:03.88#ibcon#read 3, iclass 16, count 0 2006.173.19:41:03.88#ibcon#about to read 4, iclass 16, count 0 2006.173.19:41:03.88#ibcon#read 4, iclass 16, count 0 2006.173.19:41:03.88#ibcon#about to read 5, iclass 16, count 0 2006.173.19:41:03.88#ibcon#read 5, iclass 16, count 0 2006.173.19:41:03.88#ibcon#about to read 6, iclass 16, count 0 2006.173.19:41:03.88#ibcon#read 6, iclass 16, count 0 2006.173.19:41:03.88#ibcon#end of sib2, iclass 16, count 0 2006.173.19:41:03.88#ibcon#*after write, iclass 16, count 0 2006.173.19:41:03.88#ibcon#*before return 0, iclass 16, count 0 2006.173.19:41:03.88#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.19:41:03.88#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.19:41:03.88#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.19:41:03.88#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.19:41:03.88$vck44/vblo=1,629.99 2006.173.19:41:03.88#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.19:41:03.88#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.19:41:03.88#ibcon#ireg 17 cls_cnt 0 2006.173.19:41:03.88#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.19:41:03.88#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.19:41:03.88#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.19:41:03.88#ibcon#enter wrdev, iclass 18, count 0 2006.173.19:41:03.88#ibcon#first serial, iclass 18, count 0 2006.173.19:41:03.88#ibcon#enter sib2, iclass 18, count 0 2006.173.19:41:03.88#ibcon#flushed, iclass 18, count 0 2006.173.19:41:03.88#ibcon#about to write, iclass 18, count 0 2006.173.19:41:03.88#ibcon#wrote, iclass 18, count 0 2006.173.19:41:03.88#ibcon#about to read 3, iclass 18, count 0 2006.173.19:41:03.90#ibcon#read 3, iclass 18, count 0 2006.173.19:41:03.90#ibcon#about to read 4, iclass 18, count 0 2006.173.19:41:03.90#ibcon#read 4, iclass 18, count 0 2006.173.19:41:03.90#ibcon#about to read 5, iclass 18, count 0 2006.173.19:41:03.90#ibcon#read 5, iclass 18, count 0 2006.173.19:41:03.90#ibcon#about to read 6, iclass 18, count 0 2006.173.19:41:03.90#ibcon#read 6, iclass 18, count 0 2006.173.19:41:03.90#ibcon#end of sib2, iclass 18, count 0 2006.173.19:41:03.90#ibcon#*mode == 0, iclass 18, count 0 2006.173.19:41:03.90#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.19:41:03.90#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.19:41:03.90#ibcon#*before write, iclass 18, count 0 2006.173.19:41:03.90#ibcon#enter sib2, iclass 18, count 0 2006.173.19:41:03.90#ibcon#flushed, iclass 18, count 0 2006.173.19:41:03.90#ibcon#about to write, iclass 18, count 0 2006.173.19:41:03.90#ibcon#wrote, iclass 18, count 0 2006.173.19:41:03.90#ibcon#about to read 3, iclass 18, count 0 2006.173.19:41:03.94#ibcon#read 3, iclass 18, count 0 2006.173.19:41:03.94#ibcon#about to read 4, iclass 18, count 0 2006.173.19:41:03.94#ibcon#read 4, iclass 18, count 0 2006.173.19:41:03.94#ibcon#about to read 5, iclass 18, count 0 2006.173.19:41:03.94#ibcon#read 5, iclass 18, count 0 2006.173.19:41:03.94#ibcon#about to read 6, iclass 18, count 0 2006.173.19:41:03.94#ibcon#read 6, iclass 18, count 0 2006.173.19:41:03.94#ibcon#end of sib2, iclass 18, count 0 2006.173.19:41:03.94#ibcon#*after write, iclass 18, count 0 2006.173.19:41:03.94#ibcon#*before return 0, iclass 18, count 0 2006.173.19:41:03.94#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.19:41:03.94#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.19:41:03.94#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.19:41:03.94#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.19:41:03.94$vck44/vb=1,4 2006.173.19:41:03.94#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.19:41:03.94#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.19:41:03.94#ibcon#ireg 11 cls_cnt 2 2006.173.19:41:03.94#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.19:41:03.94#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.19:41:03.94#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.19:41:03.94#ibcon#enter wrdev, iclass 20, count 2 2006.173.19:41:03.94#ibcon#first serial, iclass 20, count 2 2006.173.19:41:03.94#ibcon#enter sib2, iclass 20, count 2 2006.173.19:41:03.94#ibcon#flushed, iclass 20, count 2 2006.173.19:41:03.94#ibcon#about to write, iclass 20, count 2 2006.173.19:41:03.94#ibcon#wrote, iclass 20, count 2 2006.173.19:41:03.94#ibcon#about to read 3, iclass 20, count 2 2006.173.19:41:03.96#ibcon#read 3, iclass 20, count 2 2006.173.19:41:03.96#ibcon#about to read 4, iclass 20, count 2 2006.173.19:41:03.96#ibcon#read 4, iclass 20, count 2 2006.173.19:41:03.96#ibcon#about to read 5, iclass 20, count 2 2006.173.19:41:03.96#ibcon#read 5, iclass 20, count 2 2006.173.19:41:03.96#ibcon#about to read 6, iclass 20, count 2 2006.173.19:41:03.96#ibcon#read 6, iclass 20, count 2 2006.173.19:41:03.96#ibcon#end of sib2, iclass 20, count 2 2006.173.19:41:03.96#ibcon#*mode == 0, iclass 20, count 2 2006.173.19:41:03.96#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.19:41:03.96#ibcon#[27=AT01-04\r\n] 2006.173.19:41:03.96#ibcon#*before write, iclass 20, count 2 2006.173.19:41:03.96#ibcon#enter sib2, iclass 20, count 2 2006.173.19:41:03.96#ibcon#flushed, iclass 20, count 2 2006.173.19:41:03.96#ibcon#about to write, iclass 20, count 2 2006.173.19:41:03.96#ibcon#wrote, iclass 20, count 2 2006.173.19:41:03.96#ibcon#about to read 3, iclass 20, count 2 2006.173.19:41:03.99#ibcon#read 3, iclass 20, count 2 2006.173.19:41:03.99#ibcon#about to read 4, iclass 20, count 2 2006.173.19:41:03.99#ibcon#read 4, iclass 20, count 2 2006.173.19:41:03.99#ibcon#about to read 5, iclass 20, count 2 2006.173.19:41:03.99#ibcon#read 5, iclass 20, count 2 2006.173.19:41:03.99#ibcon#about to read 6, iclass 20, count 2 2006.173.19:41:03.99#ibcon#read 6, iclass 20, count 2 2006.173.19:41:03.99#ibcon#end of sib2, iclass 20, count 2 2006.173.19:41:03.99#ibcon#*after write, iclass 20, count 2 2006.173.19:41:03.99#ibcon#*before return 0, iclass 20, count 2 2006.173.19:41:03.99#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.19:41:03.99#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.19:41:03.99#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.19:41:03.99#ibcon#ireg 7 cls_cnt 0 2006.173.19:41:03.99#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.19:41:04.11#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.19:41:04.11#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.19:41:04.11#ibcon#enter wrdev, iclass 20, count 0 2006.173.19:41:04.11#ibcon#first serial, iclass 20, count 0 2006.173.19:41:04.11#ibcon#enter sib2, iclass 20, count 0 2006.173.19:41:04.11#ibcon#flushed, iclass 20, count 0 2006.173.19:41:04.11#ibcon#about to write, iclass 20, count 0 2006.173.19:41:04.11#ibcon#wrote, iclass 20, count 0 2006.173.19:41:04.11#ibcon#about to read 3, iclass 20, count 0 2006.173.19:41:04.13#ibcon#read 3, iclass 20, count 0 2006.173.19:41:04.13#ibcon#about to read 4, iclass 20, count 0 2006.173.19:41:04.13#ibcon#read 4, iclass 20, count 0 2006.173.19:41:04.13#ibcon#about to read 5, iclass 20, count 0 2006.173.19:41:04.13#ibcon#read 5, iclass 20, count 0 2006.173.19:41:04.13#ibcon#about to read 6, iclass 20, count 0 2006.173.19:41:04.13#ibcon#read 6, iclass 20, count 0 2006.173.19:41:04.13#ibcon#end of sib2, iclass 20, count 0 2006.173.19:41:04.13#ibcon#*mode == 0, iclass 20, count 0 2006.173.19:41:04.13#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.19:41:04.13#ibcon#[27=USB\r\n] 2006.173.19:41:04.13#ibcon#*before write, iclass 20, count 0 2006.173.19:41:04.13#ibcon#enter sib2, iclass 20, count 0 2006.173.19:41:04.13#ibcon#flushed, iclass 20, count 0 2006.173.19:41:04.13#ibcon#about to write, iclass 20, count 0 2006.173.19:41:04.13#ibcon#wrote, iclass 20, count 0 2006.173.19:41:04.13#ibcon#about to read 3, iclass 20, count 0 2006.173.19:41:04.16#ibcon#read 3, iclass 20, count 0 2006.173.19:41:04.16#ibcon#about to read 4, iclass 20, count 0 2006.173.19:41:04.16#ibcon#read 4, iclass 20, count 0 2006.173.19:41:04.16#ibcon#about to read 5, iclass 20, count 0 2006.173.19:41:04.16#ibcon#read 5, iclass 20, count 0 2006.173.19:41:04.16#ibcon#about to read 6, iclass 20, count 0 2006.173.19:41:04.16#ibcon#read 6, iclass 20, count 0 2006.173.19:41:04.16#ibcon#end of sib2, iclass 20, count 0 2006.173.19:41:04.16#ibcon#*after write, iclass 20, count 0 2006.173.19:41:04.16#ibcon#*before return 0, iclass 20, count 0 2006.173.19:41:04.16#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.19:41:04.16#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.19:41:04.16#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.19:41:04.16#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.19:41:04.16$vck44/vblo=2,634.99 2006.173.19:41:04.16#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.19:41:04.16#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.19:41:04.16#ibcon#ireg 17 cls_cnt 0 2006.173.19:41:04.16#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.19:41:04.16#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.19:41:04.16#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.19:41:04.16#ibcon#enter wrdev, iclass 22, count 0 2006.173.19:41:04.16#ibcon#first serial, iclass 22, count 0 2006.173.19:41:04.16#ibcon#enter sib2, iclass 22, count 0 2006.173.19:41:04.16#ibcon#flushed, iclass 22, count 0 2006.173.19:41:04.16#ibcon#about to write, iclass 22, count 0 2006.173.19:41:04.16#ibcon#wrote, iclass 22, count 0 2006.173.19:41:04.16#ibcon#about to read 3, iclass 22, count 0 2006.173.19:41:04.18#ibcon#read 3, iclass 22, count 0 2006.173.19:41:04.18#ibcon#about to read 4, iclass 22, count 0 2006.173.19:41:04.18#ibcon#read 4, iclass 22, count 0 2006.173.19:41:04.18#ibcon#about to read 5, iclass 22, count 0 2006.173.19:41:04.18#ibcon#read 5, iclass 22, count 0 2006.173.19:41:04.18#ibcon#about to read 6, iclass 22, count 0 2006.173.19:41:04.18#ibcon#read 6, iclass 22, count 0 2006.173.19:41:04.18#ibcon#end of sib2, iclass 22, count 0 2006.173.19:41:04.18#ibcon#*mode == 0, iclass 22, count 0 2006.173.19:41:04.18#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.19:41:04.18#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.19:41:04.18#ibcon#*before write, iclass 22, count 0 2006.173.19:41:04.18#ibcon#enter sib2, iclass 22, count 0 2006.173.19:41:04.18#ibcon#flushed, iclass 22, count 0 2006.173.19:41:04.18#ibcon#about to write, iclass 22, count 0 2006.173.19:41:04.18#ibcon#wrote, iclass 22, count 0 2006.173.19:41:04.18#ibcon#about to read 3, iclass 22, count 0 2006.173.19:41:04.22#ibcon#read 3, iclass 22, count 0 2006.173.19:41:04.22#ibcon#about to read 4, iclass 22, count 0 2006.173.19:41:04.22#ibcon#read 4, iclass 22, count 0 2006.173.19:41:04.22#ibcon#about to read 5, iclass 22, count 0 2006.173.19:41:04.22#ibcon#read 5, iclass 22, count 0 2006.173.19:41:04.22#ibcon#about to read 6, iclass 22, count 0 2006.173.19:41:04.22#ibcon#read 6, iclass 22, count 0 2006.173.19:41:04.22#ibcon#end of sib2, iclass 22, count 0 2006.173.19:41:04.22#ibcon#*after write, iclass 22, count 0 2006.173.19:41:04.22#ibcon#*before return 0, iclass 22, count 0 2006.173.19:41:04.22#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.19:41:04.22#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.19:41:04.22#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.19:41:04.22#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.19:41:04.22$vck44/vb=2,4 2006.173.19:41:04.22#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.19:41:04.22#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.19:41:04.22#ibcon#ireg 11 cls_cnt 2 2006.173.19:41:04.22#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.19:41:04.28#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.19:41:04.28#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.19:41:04.28#ibcon#enter wrdev, iclass 24, count 2 2006.173.19:41:04.28#ibcon#first serial, iclass 24, count 2 2006.173.19:41:04.28#ibcon#enter sib2, iclass 24, count 2 2006.173.19:41:04.28#ibcon#flushed, iclass 24, count 2 2006.173.19:41:04.28#ibcon#about to write, iclass 24, count 2 2006.173.19:41:04.28#ibcon#wrote, iclass 24, count 2 2006.173.19:41:04.28#ibcon#about to read 3, iclass 24, count 2 2006.173.19:41:04.30#ibcon#read 3, iclass 24, count 2 2006.173.19:41:04.30#ibcon#about to read 4, iclass 24, count 2 2006.173.19:41:04.30#ibcon#read 4, iclass 24, count 2 2006.173.19:41:04.30#ibcon#about to read 5, iclass 24, count 2 2006.173.19:41:04.30#ibcon#read 5, iclass 24, count 2 2006.173.19:41:04.30#ibcon#about to read 6, iclass 24, count 2 2006.173.19:41:04.30#ibcon#read 6, iclass 24, count 2 2006.173.19:41:04.30#ibcon#end of sib2, iclass 24, count 2 2006.173.19:41:04.30#ibcon#*mode == 0, iclass 24, count 2 2006.173.19:41:04.30#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.19:41:04.30#ibcon#[27=AT02-04\r\n] 2006.173.19:41:04.30#ibcon#*before write, iclass 24, count 2 2006.173.19:41:04.30#ibcon#enter sib2, iclass 24, count 2 2006.173.19:41:04.30#ibcon#flushed, iclass 24, count 2 2006.173.19:41:04.30#ibcon#about to write, iclass 24, count 2 2006.173.19:41:04.30#ibcon#wrote, iclass 24, count 2 2006.173.19:41:04.30#ibcon#about to read 3, iclass 24, count 2 2006.173.19:41:04.33#ibcon#read 3, iclass 24, count 2 2006.173.19:41:04.33#ibcon#about to read 4, iclass 24, count 2 2006.173.19:41:04.33#ibcon#read 4, iclass 24, count 2 2006.173.19:41:04.33#ibcon#about to read 5, iclass 24, count 2 2006.173.19:41:04.33#ibcon#read 5, iclass 24, count 2 2006.173.19:41:04.33#ibcon#about to read 6, iclass 24, count 2 2006.173.19:41:04.33#ibcon#read 6, iclass 24, count 2 2006.173.19:41:04.33#ibcon#end of sib2, iclass 24, count 2 2006.173.19:41:04.33#ibcon#*after write, iclass 24, count 2 2006.173.19:41:04.33#ibcon#*before return 0, iclass 24, count 2 2006.173.19:41:04.33#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.19:41:04.33#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.19:41:04.33#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.19:41:04.33#ibcon#ireg 7 cls_cnt 0 2006.173.19:41:04.33#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.19:41:04.45#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.19:41:04.45#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.19:41:04.45#ibcon#enter wrdev, iclass 24, count 0 2006.173.19:41:04.45#ibcon#first serial, iclass 24, count 0 2006.173.19:41:04.45#ibcon#enter sib2, iclass 24, count 0 2006.173.19:41:04.45#ibcon#flushed, iclass 24, count 0 2006.173.19:41:04.45#ibcon#about to write, iclass 24, count 0 2006.173.19:41:04.45#ibcon#wrote, iclass 24, count 0 2006.173.19:41:04.45#ibcon#about to read 3, iclass 24, count 0 2006.173.19:41:04.47#ibcon#read 3, iclass 24, count 0 2006.173.19:41:04.47#ibcon#about to read 4, iclass 24, count 0 2006.173.19:41:04.47#ibcon#read 4, iclass 24, count 0 2006.173.19:41:04.47#ibcon#about to read 5, iclass 24, count 0 2006.173.19:41:04.47#ibcon#read 5, iclass 24, count 0 2006.173.19:41:04.47#ibcon#about to read 6, iclass 24, count 0 2006.173.19:41:04.47#ibcon#read 6, iclass 24, count 0 2006.173.19:41:04.47#ibcon#end of sib2, iclass 24, count 0 2006.173.19:41:04.47#ibcon#*mode == 0, iclass 24, count 0 2006.173.19:41:04.47#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.19:41:04.47#ibcon#[27=USB\r\n] 2006.173.19:41:04.47#ibcon#*before write, iclass 24, count 0 2006.173.19:41:04.47#ibcon#enter sib2, iclass 24, count 0 2006.173.19:41:04.47#ibcon#flushed, iclass 24, count 0 2006.173.19:41:04.47#ibcon#about to write, iclass 24, count 0 2006.173.19:41:04.47#ibcon#wrote, iclass 24, count 0 2006.173.19:41:04.47#ibcon#about to read 3, iclass 24, count 0 2006.173.19:41:04.50#ibcon#read 3, iclass 24, count 0 2006.173.19:41:04.50#ibcon#about to read 4, iclass 24, count 0 2006.173.19:41:04.50#ibcon#read 4, iclass 24, count 0 2006.173.19:41:04.50#ibcon#about to read 5, iclass 24, count 0 2006.173.19:41:04.50#ibcon#read 5, iclass 24, count 0 2006.173.19:41:04.50#ibcon#about to read 6, iclass 24, count 0 2006.173.19:41:04.50#ibcon#read 6, iclass 24, count 0 2006.173.19:41:04.50#ibcon#end of sib2, iclass 24, count 0 2006.173.19:41:04.50#ibcon#*after write, iclass 24, count 0 2006.173.19:41:04.50#ibcon#*before return 0, iclass 24, count 0 2006.173.19:41:04.50#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.19:41:04.50#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.19:41:04.50#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.19:41:04.50#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.19:41:04.50$vck44/vblo=3,649.99 2006.173.19:41:04.50#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.19:41:04.50#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.19:41:04.50#ibcon#ireg 17 cls_cnt 0 2006.173.19:41:04.50#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.19:41:04.50#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.19:41:04.50#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.19:41:04.50#ibcon#enter wrdev, iclass 26, count 0 2006.173.19:41:04.50#ibcon#first serial, iclass 26, count 0 2006.173.19:41:04.50#ibcon#enter sib2, iclass 26, count 0 2006.173.19:41:04.50#ibcon#flushed, iclass 26, count 0 2006.173.19:41:04.50#ibcon#about to write, iclass 26, count 0 2006.173.19:41:04.50#ibcon#wrote, iclass 26, count 0 2006.173.19:41:04.50#ibcon#about to read 3, iclass 26, count 0 2006.173.19:41:04.52#ibcon#read 3, iclass 26, count 0 2006.173.19:41:04.52#ibcon#about to read 4, iclass 26, count 0 2006.173.19:41:04.52#ibcon#read 4, iclass 26, count 0 2006.173.19:41:04.52#ibcon#about to read 5, iclass 26, count 0 2006.173.19:41:04.52#ibcon#read 5, iclass 26, count 0 2006.173.19:41:04.52#ibcon#about to read 6, iclass 26, count 0 2006.173.19:41:04.52#ibcon#read 6, iclass 26, count 0 2006.173.19:41:04.52#ibcon#end of sib2, iclass 26, count 0 2006.173.19:41:04.52#ibcon#*mode == 0, iclass 26, count 0 2006.173.19:41:04.52#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.19:41:04.52#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.19:41:04.52#ibcon#*before write, iclass 26, count 0 2006.173.19:41:04.52#ibcon#enter sib2, iclass 26, count 0 2006.173.19:41:04.52#ibcon#flushed, iclass 26, count 0 2006.173.19:41:04.52#ibcon#about to write, iclass 26, count 0 2006.173.19:41:04.52#ibcon#wrote, iclass 26, count 0 2006.173.19:41:04.52#ibcon#about to read 3, iclass 26, count 0 2006.173.19:41:04.56#ibcon#read 3, iclass 26, count 0 2006.173.19:41:04.56#ibcon#about to read 4, iclass 26, count 0 2006.173.19:41:04.56#ibcon#read 4, iclass 26, count 0 2006.173.19:41:04.56#ibcon#about to read 5, iclass 26, count 0 2006.173.19:41:04.56#ibcon#read 5, iclass 26, count 0 2006.173.19:41:04.56#ibcon#about to read 6, iclass 26, count 0 2006.173.19:41:04.56#ibcon#read 6, iclass 26, count 0 2006.173.19:41:04.56#ibcon#end of sib2, iclass 26, count 0 2006.173.19:41:04.56#ibcon#*after write, iclass 26, count 0 2006.173.19:41:04.56#ibcon#*before return 0, iclass 26, count 0 2006.173.19:41:04.56#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.19:41:04.56#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.19:41:04.56#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.19:41:04.56#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.19:41:04.56$vck44/vb=3,4 2006.173.19:41:04.56#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.19:41:04.56#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.19:41:04.56#ibcon#ireg 11 cls_cnt 2 2006.173.19:41:04.56#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.19:41:04.62#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.19:41:04.62#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.19:41:04.62#ibcon#enter wrdev, iclass 28, count 2 2006.173.19:41:04.62#ibcon#first serial, iclass 28, count 2 2006.173.19:41:04.62#ibcon#enter sib2, iclass 28, count 2 2006.173.19:41:04.62#ibcon#flushed, iclass 28, count 2 2006.173.19:41:04.62#ibcon#about to write, iclass 28, count 2 2006.173.19:41:04.62#ibcon#wrote, iclass 28, count 2 2006.173.19:41:04.62#ibcon#about to read 3, iclass 28, count 2 2006.173.19:41:04.64#ibcon#read 3, iclass 28, count 2 2006.173.19:41:04.64#ibcon#about to read 4, iclass 28, count 2 2006.173.19:41:04.64#ibcon#read 4, iclass 28, count 2 2006.173.19:41:04.64#ibcon#about to read 5, iclass 28, count 2 2006.173.19:41:04.64#ibcon#read 5, iclass 28, count 2 2006.173.19:41:04.64#ibcon#about to read 6, iclass 28, count 2 2006.173.19:41:04.64#ibcon#read 6, iclass 28, count 2 2006.173.19:41:04.64#ibcon#end of sib2, iclass 28, count 2 2006.173.19:41:04.64#ibcon#*mode == 0, iclass 28, count 2 2006.173.19:41:04.64#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.19:41:04.64#ibcon#[27=AT03-04\r\n] 2006.173.19:41:04.64#ibcon#*before write, iclass 28, count 2 2006.173.19:41:04.64#ibcon#enter sib2, iclass 28, count 2 2006.173.19:41:04.64#ibcon#flushed, iclass 28, count 2 2006.173.19:41:04.64#ibcon#about to write, iclass 28, count 2 2006.173.19:41:04.64#ibcon#wrote, iclass 28, count 2 2006.173.19:41:04.64#ibcon#about to read 3, iclass 28, count 2 2006.173.19:41:04.67#ibcon#read 3, iclass 28, count 2 2006.173.19:41:04.67#ibcon#about to read 4, iclass 28, count 2 2006.173.19:41:04.67#ibcon#read 4, iclass 28, count 2 2006.173.19:41:04.67#ibcon#about to read 5, iclass 28, count 2 2006.173.19:41:04.67#ibcon#read 5, iclass 28, count 2 2006.173.19:41:04.67#ibcon#about to read 6, iclass 28, count 2 2006.173.19:41:04.67#ibcon#read 6, iclass 28, count 2 2006.173.19:41:04.67#ibcon#end of sib2, iclass 28, count 2 2006.173.19:41:04.67#ibcon#*after write, iclass 28, count 2 2006.173.19:41:04.67#ibcon#*before return 0, iclass 28, count 2 2006.173.19:41:04.67#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.19:41:04.67#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.19:41:04.67#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.19:41:04.67#ibcon#ireg 7 cls_cnt 0 2006.173.19:41:04.67#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.19:41:04.79#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.19:41:04.79#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.19:41:04.79#ibcon#enter wrdev, iclass 28, count 0 2006.173.19:41:04.79#ibcon#first serial, iclass 28, count 0 2006.173.19:41:04.79#ibcon#enter sib2, iclass 28, count 0 2006.173.19:41:04.79#ibcon#flushed, iclass 28, count 0 2006.173.19:41:04.79#ibcon#about to write, iclass 28, count 0 2006.173.19:41:04.79#ibcon#wrote, iclass 28, count 0 2006.173.19:41:04.79#ibcon#about to read 3, iclass 28, count 0 2006.173.19:41:04.81#ibcon#read 3, iclass 28, count 0 2006.173.19:41:04.81#ibcon#about to read 4, iclass 28, count 0 2006.173.19:41:04.81#ibcon#read 4, iclass 28, count 0 2006.173.19:41:04.81#ibcon#about to read 5, iclass 28, count 0 2006.173.19:41:04.81#ibcon#read 5, iclass 28, count 0 2006.173.19:41:04.81#ibcon#about to read 6, iclass 28, count 0 2006.173.19:41:04.81#ibcon#read 6, iclass 28, count 0 2006.173.19:41:04.81#ibcon#end of sib2, iclass 28, count 0 2006.173.19:41:04.81#ibcon#*mode == 0, iclass 28, count 0 2006.173.19:41:04.81#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.19:41:04.81#ibcon#[27=USB\r\n] 2006.173.19:41:04.81#ibcon#*before write, iclass 28, count 0 2006.173.19:41:04.81#ibcon#enter sib2, iclass 28, count 0 2006.173.19:41:04.81#ibcon#flushed, iclass 28, count 0 2006.173.19:41:04.81#ibcon#about to write, iclass 28, count 0 2006.173.19:41:04.81#ibcon#wrote, iclass 28, count 0 2006.173.19:41:04.81#ibcon#about to read 3, iclass 28, count 0 2006.173.19:41:04.84#ibcon#read 3, iclass 28, count 0 2006.173.19:41:04.84#ibcon#about to read 4, iclass 28, count 0 2006.173.19:41:04.84#ibcon#read 4, iclass 28, count 0 2006.173.19:41:04.84#ibcon#about to read 5, iclass 28, count 0 2006.173.19:41:04.84#ibcon#read 5, iclass 28, count 0 2006.173.19:41:04.84#ibcon#about to read 6, iclass 28, count 0 2006.173.19:41:04.84#ibcon#read 6, iclass 28, count 0 2006.173.19:41:04.84#ibcon#end of sib2, iclass 28, count 0 2006.173.19:41:04.84#ibcon#*after write, iclass 28, count 0 2006.173.19:41:04.84#ibcon#*before return 0, iclass 28, count 0 2006.173.19:41:04.84#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.19:41:04.84#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.19:41:04.84#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.19:41:04.84#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.19:41:04.84$vck44/vblo=4,679.99 2006.173.19:41:04.84#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.19:41:04.84#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.19:41:04.84#ibcon#ireg 17 cls_cnt 0 2006.173.19:41:04.84#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.19:41:04.84#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.19:41:04.84#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.19:41:04.84#ibcon#enter wrdev, iclass 30, count 0 2006.173.19:41:04.84#ibcon#first serial, iclass 30, count 0 2006.173.19:41:04.84#ibcon#enter sib2, iclass 30, count 0 2006.173.19:41:04.84#ibcon#flushed, iclass 30, count 0 2006.173.19:41:04.84#ibcon#about to write, iclass 30, count 0 2006.173.19:41:04.84#ibcon#wrote, iclass 30, count 0 2006.173.19:41:04.84#ibcon#about to read 3, iclass 30, count 0 2006.173.19:41:04.86#ibcon#read 3, iclass 30, count 0 2006.173.19:41:04.86#ibcon#about to read 4, iclass 30, count 0 2006.173.19:41:04.86#ibcon#read 4, iclass 30, count 0 2006.173.19:41:04.86#ibcon#about to read 5, iclass 30, count 0 2006.173.19:41:04.86#ibcon#read 5, iclass 30, count 0 2006.173.19:41:04.86#ibcon#about to read 6, iclass 30, count 0 2006.173.19:41:04.86#ibcon#read 6, iclass 30, count 0 2006.173.19:41:04.86#ibcon#end of sib2, iclass 30, count 0 2006.173.19:41:04.86#ibcon#*mode == 0, iclass 30, count 0 2006.173.19:41:04.86#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.19:41:04.86#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.19:41:04.86#ibcon#*before write, iclass 30, count 0 2006.173.19:41:04.86#ibcon#enter sib2, iclass 30, count 0 2006.173.19:41:04.86#ibcon#flushed, iclass 30, count 0 2006.173.19:41:04.86#ibcon#about to write, iclass 30, count 0 2006.173.19:41:04.86#ibcon#wrote, iclass 30, count 0 2006.173.19:41:04.86#ibcon#about to read 3, iclass 30, count 0 2006.173.19:41:04.90#ibcon#read 3, iclass 30, count 0 2006.173.19:41:04.90#ibcon#about to read 4, iclass 30, count 0 2006.173.19:41:04.90#ibcon#read 4, iclass 30, count 0 2006.173.19:41:04.90#ibcon#about to read 5, iclass 30, count 0 2006.173.19:41:04.90#ibcon#read 5, iclass 30, count 0 2006.173.19:41:04.90#ibcon#about to read 6, iclass 30, count 0 2006.173.19:41:04.90#ibcon#read 6, iclass 30, count 0 2006.173.19:41:04.90#ibcon#end of sib2, iclass 30, count 0 2006.173.19:41:04.90#ibcon#*after write, iclass 30, count 0 2006.173.19:41:04.90#ibcon#*before return 0, iclass 30, count 0 2006.173.19:41:04.90#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.19:41:04.90#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.19:41:04.90#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.19:41:04.90#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.19:41:04.90$vck44/vb=4,4 2006.173.19:41:04.90#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.173.19:41:04.90#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.173.19:41:04.90#ibcon#ireg 11 cls_cnt 2 2006.173.19:41:04.90#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.19:41:04.96#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.19:41:04.96#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.19:41:04.96#ibcon#enter wrdev, iclass 32, count 2 2006.173.19:41:04.96#ibcon#first serial, iclass 32, count 2 2006.173.19:41:04.96#ibcon#enter sib2, iclass 32, count 2 2006.173.19:41:04.96#ibcon#flushed, iclass 32, count 2 2006.173.19:41:04.96#ibcon#about to write, iclass 32, count 2 2006.173.19:41:04.96#ibcon#wrote, iclass 32, count 2 2006.173.19:41:04.96#ibcon#about to read 3, iclass 32, count 2 2006.173.19:41:04.98#ibcon#read 3, iclass 32, count 2 2006.173.19:41:04.98#ibcon#about to read 4, iclass 32, count 2 2006.173.19:41:04.98#ibcon#read 4, iclass 32, count 2 2006.173.19:41:04.98#ibcon#about to read 5, iclass 32, count 2 2006.173.19:41:04.98#ibcon#read 5, iclass 32, count 2 2006.173.19:41:04.98#ibcon#about to read 6, iclass 32, count 2 2006.173.19:41:04.98#ibcon#read 6, iclass 32, count 2 2006.173.19:41:04.98#ibcon#end of sib2, iclass 32, count 2 2006.173.19:41:04.98#ibcon#*mode == 0, iclass 32, count 2 2006.173.19:41:04.98#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.173.19:41:04.98#ibcon#[27=AT04-04\r\n] 2006.173.19:41:04.98#ibcon#*before write, iclass 32, count 2 2006.173.19:41:04.98#ibcon#enter sib2, iclass 32, count 2 2006.173.19:41:04.98#ibcon#flushed, iclass 32, count 2 2006.173.19:41:04.98#ibcon#about to write, iclass 32, count 2 2006.173.19:41:04.98#ibcon#wrote, iclass 32, count 2 2006.173.19:41:04.98#ibcon#about to read 3, iclass 32, count 2 2006.173.19:41:04.98#abcon#<5=/00 0.1 0.5 19.341001002.5\r\n> 2006.173.19:41:05.00#abcon#{5=INTERFACE CLEAR} 2006.173.19:41:05.01#ibcon#read 3, iclass 32, count 2 2006.173.19:41:05.01#ibcon#about to read 4, iclass 32, count 2 2006.173.19:41:05.01#ibcon#read 4, iclass 32, count 2 2006.173.19:41:05.01#ibcon#about to read 5, iclass 32, count 2 2006.173.19:41:05.01#ibcon#read 5, iclass 32, count 2 2006.173.19:41:05.01#ibcon#about to read 6, iclass 32, count 2 2006.173.19:41:05.01#ibcon#read 6, iclass 32, count 2 2006.173.19:41:05.01#ibcon#end of sib2, iclass 32, count 2 2006.173.19:41:05.01#ibcon#*after write, iclass 32, count 2 2006.173.19:41:05.01#ibcon#*before return 0, iclass 32, count 2 2006.173.19:41:05.01#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.19:41:05.01#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.173.19:41:05.01#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.173.19:41:05.01#ibcon#ireg 7 cls_cnt 0 2006.173.19:41:05.01#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.19:41:05.06#abcon#[5=S1D000X0/0*\r\n] 2006.173.19:41:05.13#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.19:41:05.13#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.19:41:05.13#ibcon#enter wrdev, iclass 32, count 0 2006.173.19:41:05.13#ibcon#first serial, iclass 32, count 0 2006.173.19:41:05.13#ibcon#enter sib2, iclass 32, count 0 2006.173.19:41:05.13#ibcon#flushed, iclass 32, count 0 2006.173.19:41:05.13#ibcon#about to write, iclass 32, count 0 2006.173.19:41:05.13#ibcon#wrote, iclass 32, count 0 2006.173.19:41:05.13#ibcon#about to read 3, iclass 32, count 0 2006.173.19:41:05.15#ibcon#read 3, iclass 32, count 0 2006.173.19:41:05.15#ibcon#about to read 4, iclass 32, count 0 2006.173.19:41:05.15#ibcon#read 4, iclass 32, count 0 2006.173.19:41:05.15#ibcon#about to read 5, iclass 32, count 0 2006.173.19:41:05.15#ibcon#read 5, iclass 32, count 0 2006.173.19:41:05.15#ibcon#about to read 6, iclass 32, count 0 2006.173.19:41:05.15#ibcon#read 6, iclass 32, count 0 2006.173.19:41:05.15#ibcon#end of sib2, iclass 32, count 0 2006.173.19:41:05.15#ibcon#*mode == 0, iclass 32, count 0 2006.173.19:41:05.15#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.19:41:05.15#ibcon#[27=USB\r\n] 2006.173.19:41:05.15#ibcon#*before write, iclass 32, count 0 2006.173.19:41:05.15#ibcon#enter sib2, iclass 32, count 0 2006.173.19:41:05.15#ibcon#flushed, iclass 32, count 0 2006.173.19:41:05.15#ibcon#about to write, iclass 32, count 0 2006.173.19:41:05.15#ibcon#wrote, iclass 32, count 0 2006.173.19:41:05.15#ibcon#about to read 3, iclass 32, count 0 2006.173.19:41:05.18#ibcon#read 3, iclass 32, count 0 2006.173.19:41:05.18#ibcon#about to read 4, iclass 32, count 0 2006.173.19:41:05.18#ibcon#read 4, iclass 32, count 0 2006.173.19:41:05.18#ibcon#about to read 5, iclass 32, count 0 2006.173.19:41:05.18#ibcon#read 5, iclass 32, count 0 2006.173.19:41:05.18#ibcon#about to read 6, iclass 32, count 0 2006.173.19:41:05.18#ibcon#read 6, iclass 32, count 0 2006.173.19:41:05.18#ibcon#end of sib2, iclass 32, count 0 2006.173.19:41:05.18#ibcon#*after write, iclass 32, count 0 2006.173.19:41:05.18#ibcon#*before return 0, iclass 32, count 0 2006.173.19:41:05.18#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.19:41:05.18#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.173.19:41:05.18#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.19:41:05.18#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.19:41:05.18$vck44/vblo=5,709.99 2006.173.19:41:05.18#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.19:41:05.18#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.19:41:05.18#ibcon#ireg 17 cls_cnt 0 2006.173.19:41:05.18#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.19:41:05.18#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.19:41:05.18#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.19:41:05.18#ibcon#enter wrdev, iclass 38, count 0 2006.173.19:41:05.18#ibcon#first serial, iclass 38, count 0 2006.173.19:41:05.18#ibcon#enter sib2, iclass 38, count 0 2006.173.19:41:05.18#ibcon#flushed, iclass 38, count 0 2006.173.19:41:05.18#ibcon#about to write, iclass 38, count 0 2006.173.19:41:05.18#ibcon#wrote, iclass 38, count 0 2006.173.19:41:05.18#ibcon#about to read 3, iclass 38, count 0 2006.173.19:41:05.20#ibcon#read 3, iclass 38, count 0 2006.173.19:41:05.20#ibcon#about to read 4, iclass 38, count 0 2006.173.19:41:05.20#ibcon#read 4, iclass 38, count 0 2006.173.19:41:05.20#ibcon#about to read 5, iclass 38, count 0 2006.173.19:41:05.20#ibcon#read 5, iclass 38, count 0 2006.173.19:41:05.20#ibcon#about to read 6, iclass 38, count 0 2006.173.19:41:05.20#ibcon#read 6, iclass 38, count 0 2006.173.19:41:05.20#ibcon#end of sib2, iclass 38, count 0 2006.173.19:41:05.20#ibcon#*mode == 0, iclass 38, count 0 2006.173.19:41:05.20#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.19:41:05.20#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.19:41:05.20#ibcon#*before write, iclass 38, count 0 2006.173.19:41:05.20#ibcon#enter sib2, iclass 38, count 0 2006.173.19:41:05.20#ibcon#flushed, iclass 38, count 0 2006.173.19:41:05.20#ibcon#about to write, iclass 38, count 0 2006.173.19:41:05.20#ibcon#wrote, iclass 38, count 0 2006.173.19:41:05.20#ibcon#about to read 3, iclass 38, count 0 2006.173.19:41:05.24#ibcon#read 3, iclass 38, count 0 2006.173.19:41:05.24#ibcon#about to read 4, iclass 38, count 0 2006.173.19:41:05.24#ibcon#read 4, iclass 38, count 0 2006.173.19:41:05.24#ibcon#about to read 5, iclass 38, count 0 2006.173.19:41:05.24#ibcon#read 5, iclass 38, count 0 2006.173.19:41:05.24#ibcon#about to read 6, iclass 38, count 0 2006.173.19:41:05.24#ibcon#read 6, iclass 38, count 0 2006.173.19:41:05.24#ibcon#end of sib2, iclass 38, count 0 2006.173.19:41:05.24#ibcon#*after write, iclass 38, count 0 2006.173.19:41:05.24#ibcon#*before return 0, iclass 38, count 0 2006.173.19:41:05.24#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.19:41:05.24#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.19:41:05.24#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.19:41:05.24#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.19:41:05.24$vck44/vb=5,4 2006.173.19:41:05.24#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.19:41:05.24#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.19:41:05.24#ibcon#ireg 11 cls_cnt 2 2006.173.19:41:05.24#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.19:41:05.30#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.19:41:05.30#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.19:41:05.30#ibcon#enter wrdev, iclass 40, count 2 2006.173.19:41:05.30#ibcon#first serial, iclass 40, count 2 2006.173.19:41:05.30#ibcon#enter sib2, iclass 40, count 2 2006.173.19:41:05.30#ibcon#flushed, iclass 40, count 2 2006.173.19:41:05.30#ibcon#about to write, iclass 40, count 2 2006.173.19:41:05.30#ibcon#wrote, iclass 40, count 2 2006.173.19:41:05.30#ibcon#about to read 3, iclass 40, count 2 2006.173.19:41:05.32#ibcon#read 3, iclass 40, count 2 2006.173.19:41:05.32#ibcon#about to read 4, iclass 40, count 2 2006.173.19:41:05.32#ibcon#read 4, iclass 40, count 2 2006.173.19:41:05.32#ibcon#about to read 5, iclass 40, count 2 2006.173.19:41:05.32#ibcon#read 5, iclass 40, count 2 2006.173.19:41:05.32#ibcon#about to read 6, iclass 40, count 2 2006.173.19:41:05.32#ibcon#read 6, iclass 40, count 2 2006.173.19:41:05.32#ibcon#end of sib2, iclass 40, count 2 2006.173.19:41:05.32#ibcon#*mode == 0, iclass 40, count 2 2006.173.19:41:05.32#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.19:41:05.32#ibcon#[27=AT05-04\r\n] 2006.173.19:41:05.32#ibcon#*before write, iclass 40, count 2 2006.173.19:41:05.32#ibcon#enter sib2, iclass 40, count 2 2006.173.19:41:05.32#ibcon#flushed, iclass 40, count 2 2006.173.19:41:05.32#ibcon#about to write, iclass 40, count 2 2006.173.19:41:05.32#ibcon#wrote, iclass 40, count 2 2006.173.19:41:05.32#ibcon#about to read 3, iclass 40, count 2 2006.173.19:41:05.35#ibcon#read 3, iclass 40, count 2 2006.173.19:41:05.35#ibcon#about to read 4, iclass 40, count 2 2006.173.19:41:05.35#ibcon#read 4, iclass 40, count 2 2006.173.19:41:05.35#ibcon#about to read 5, iclass 40, count 2 2006.173.19:41:05.35#ibcon#read 5, iclass 40, count 2 2006.173.19:41:05.35#ibcon#about to read 6, iclass 40, count 2 2006.173.19:41:05.35#ibcon#read 6, iclass 40, count 2 2006.173.19:41:05.35#ibcon#end of sib2, iclass 40, count 2 2006.173.19:41:05.35#ibcon#*after write, iclass 40, count 2 2006.173.19:41:05.35#ibcon#*before return 0, iclass 40, count 2 2006.173.19:41:05.35#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.19:41:05.35#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.19:41:05.35#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.19:41:05.35#ibcon#ireg 7 cls_cnt 0 2006.173.19:41:05.35#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.19:41:05.47#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.19:41:05.47#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.19:41:05.47#ibcon#enter wrdev, iclass 40, count 0 2006.173.19:41:05.47#ibcon#first serial, iclass 40, count 0 2006.173.19:41:05.47#ibcon#enter sib2, iclass 40, count 0 2006.173.19:41:05.47#ibcon#flushed, iclass 40, count 0 2006.173.19:41:05.47#ibcon#about to write, iclass 40, count 0 2006.173.19:41:05.47#ibcon#wrote, iclass 40, count 0 2006.173.19:41:05.47#ibcon#about to read 3, iclass 40, count 0 2006.173.19:41:05.49#ibcon#read 3, iclass 40, count 0 2006.173.19:41:05.49#ibcon#about to read 4, iclass 40, count 0 2006.173.19:41:05.49#ibcon#read 4, iclass 40, count 0 2006.173.19:41:05.49#ibcon#about to read 5, iclass 40, count 0 2006.173.19:41:05.49#ibcon#read 5, iclass 40, count 0 2006.173.19:41:05.49#ibcon#about to read 6, iclass 40, count 0 2006.173.19:41:05.49#ibcon#read 6, iclass 40, count 0 2006.173.19:41:05.49#ibcon#end of sib2, iclass 40, count 0 2006.173.19:41:05.49#ibcon#*mode == 0, iclass 40, count 0 2006.173.19:41:05.49#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.19:41:05.49#ibcon#[27=USB\r\n] 2006.173.19:41:05.49#ibcon#*before write, iclass 40, count 0 2006.173.19:41:05.49#ibcon#enter sib2, iclass 40, count 0 2006.173.19:41:05.49#ibcon#flushed, iclass 40, count 0 2006.173.19:41:05.49#ibcon#about to write, iclass 40, count 0 2006.173.19:41:05.49#ibcon#wrote, iclass 40, count 0 2006.173.19:41:05.49#ibcon#about to read 3, iclass 40, count 0 2006.173.19:41:05.52#ibcon#read 3, iclass 40, count 0 2006.173.19:41:05.52#ibcon#about to read 4, iclass 40, count 0 2006.173.19:41:05.52#ibcon#read 4, iclass 40, count 0 2006.173.19:41:05.52#ibcon#about to read 5, iclass 40, count 0 2006.173.19:41:05.52#ibcon#read 5, iclass 40, count 0 2006.173.19:41:05.52#ibcon#about to read 6, iclass 40, count 0 2006.173.19:41:05.52#ibcon#read 6, iclass 40, count 0 2006.173.19:41:05.52#ibcon#end of sib2, iclass 40, count 0 2006.173.19:41:05.52#ibcon#*after write, iclass 40, count 0 2006.173.19:41:05.52#ibcon#*before return 0, iclass 40, count 0 2006.173.19:41:05.52#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.19:41:05.52#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.19:41:05.52#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.19:41:05.52#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.19:41:05.52$vck44/vblo=6,719.99 2006.173.19:41:05.52#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.19:41:05.52#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.19:41:05.52#ibcon#ireg 17 cls_cnt 0 2006.173.19:41:05.52#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.19:41:05.52#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.19:41:05.52#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.19:41:05.52#ibcon#enter wrdev, iclass 4, count 0 2006.173.19:41:05.52#ibcon#first serial, iclass 4, count 0 2006.173.19:41:05.52#ibcon#enter sib2, iclass 4, count 0 2006.173.19:41:05.52#ibcon#flushed, iclass 4, count 0 2006.173.19:41:05.52#ibcon#about to write, iclass 4, count 0 2006.173.19:41:05.52#ibcon#wrote, iclass 4, count 0 2006.173.19:41:05.52#ibcon#about to read 3, iclass 4, count 0 2006.173.19:41:05.54#ibcon#read 3, iclass 4, count 0 2006.173.19:41:05.54#ibcon#about to read 4, iclass 4, count 0 2006.173.19:41:05.54#ibcon#read 4, iclass 4, count 0 2006.173.19:41:05.54#ibcon#about to read 5, iclass 4, count 0 2006.173.19:41:05.54#ibcon#read 5, iclass 4, count 0 2006.173.19:41:05.54#ibcon#about to read 6, iclass 4, count 0 2006.173.19:41:05.54#ibcon#read 6, iclass 4, count 0 2006.173.19:41:05.54#ibcon#end of sib2, iclass 4, count 0 2006.173.19:41:05.54#ibcon#*mode == 0, iclass 4, count 0 2006.173.19:41:05.54#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.19:41:05.54#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.19:41:05.54#ibcon#*before write, iclass 4, count 0 2006.173.19:41:05.54#ibcon#enter sib2, iclass 4, count 0 2006.173.19:41:05.54#ibcon#flushed, iclass 4, count 0 2006.173.19:41:05.54#ibcon#about to write, iclass 4, count 0 2006.173.19:41:05.54#ibcon#wrote, iclass 4, count 0 2006.173.19:41:05.54#ibcon#about to read 3, iclass 4, count 0 2006.173.19:41:05.58#ibcon#read 3, iclass 4, count 0 2006.173.19:41:05.58#ibcon#about to read 4, iclass 4, count 0 2006.173.19:41:05.58#ibcon#read 4, iclass 4, count 0 2006.173.19:41:05.58#ibcon#about to read 5, iclass 4, count 0 2006.173.19:41:05.58#ibcon#read 5, iclass 4, count 0 2006.173.19:41:05.58#ibcon#about to read 6, iclass 4, count 0 2006.173.19:41:05.58#ibcon#read 6, iclass 4, count 0 2006.173.19:41:05.58#ibcon#end of sib2, iclass 4, count 0 2006.173.19:41:05.58#ibcon#*after write, iclass 4, count 0 2006.173.19:41:05.58#ibcon#*before return 0, iclass 4, count 0 2006.173.19:41:05.58#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.19:41:05.58#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.19:41:05.58#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.19:41:05.58#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.19:41:05.58$vck44/vb=6,4 2006.173.19:41:05.58#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.19:41:05.58#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.19:41:05.58#ibcon#ireg 11 cls_cnt 2 2006.173.19:41:05.58#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.19:41:05.64#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.19:41:05.64#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.19:41:05.64#ibcon#enter wrdev, iclass 6, count 2 2006.173.19:41:05.64#ibcon#first serial, iclass 6, count 2 2006.173.19:41:05.64#ibcon#enter sib2, iclass 6, count 2 2006.173.19:41:05.64#ibcon#flushed, iclass 6, count 2 2006.173.19:41:05.64#ibcon#about to write, iclass 6, count 2 2006.173.19:41:05.64#ibcon#wrote, iclass 6, count 2 2006.173.19:41:05.64#ibcon#about to read 3, iclass 6, count 2 2006.173.19:41:05.66#ibcon#read 3, iclass 6, count 2 2006.173.19:41:05.66#ibcon#about to read 4, iclass 6, count 2 2006.173.19:41:05.66#ibcon#read 4, iclass 6, count 2 2006.173.19:41:05.66#ibcon#about to read 5, iclass 6, count 2 2006.173.19:41:05.66#ibcon#read 5, iclass 6, count 2 2006.173.19:41:05.66#ibcon#about to read 6, iclass 6, count 2 2006.173.19:41:05.66#ibcon#read 6, iclass 6, count 2 2006.173.19:41:05.66#ibcon#end of sib2, iclass 6, count 2 2006.173.19:41:05.66#ibcon#*mode == 0, iclass 6, count 2 2006.173.19:41:05.66#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.19:41:05.66#ibcon#[27=AT06-04\r\n] 2006.173.19:41:05.66#ibcon#*before write, iclass 6, count 2 2006.173.19:41:05.66#ibcon#enter sib2, iclass 6, count 2 2006.173.19:41:05.66#ibcon#flushed, iclass 6, count 2 2006.173.19:41:05.66#ibcon#about to write, iclass 6, count 2 2006.173.19:41:05.66#ibcon#wrote, iclass 6, count 2 2006.173.19:41:05.66#ibcon#about to read 3, iclass 6, count 2 2006.173.19:41:05.69#ibcon#read 3, iclass 6, count 2 2006.173.19:41:05.69#ibcon#about to read 4, iclass 6, count 2 2006.173.19:41:05.69#ibcon#read 4, iclass 6, count 2 2006.173.19:41:05.69#ibcon#about to read 5, iclass 6, count 2 2006.173.19:41:05.69#ibcon#read 5, iclass 6, count 2 2006.173.19:41:05.69#ibcon#about to read 6, iclass 6, count 2 2006.173.19:41:05.69#ibcon#read 6, iclass 6, count 2 2006.173.19:41:05.69#ibcon#end of sib2, iclass 6, count 2 2006.173.19:41:05.69#ibcon#*after write, iclass 6, count 2 2006.173.19:41:05.69#ibcon#*before return 0, iclass 6, count 2 2006.173.19:41:05.69#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.19:41:05.69#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.19:41:05.69#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.19:41:05.69#ibcon#ireg 7 cls_cnt 0 2006.173.19:41:05.69#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.19:41:05.81#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.19:41:05.81#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.19:41:05.81#ibcon#enter wrdev, iclass 6, count 0 2006.173.19:41:05.81#ibcon#first serial, iclass 6, count 0 2006.173.19:41:05.81#ibcon#enter sib2, iclass 6, count 0 2006.173.19:41:05.81#ibcon#flushed, iclass 6, count 0 2006.173.19:41:05.81#ibcon#about to write, iclass 6, count 0 2006.173.19:41:05.81#ibcon#wrote, iclass 6, count 0 2006.173.19:41:05.81#ibcon#about to read 3, iclass 6, count 0 2006.173.19:41:05.83#ibcon#read 3, iclass 6, count 0 2006.173.19:41:05.83#ibcon#about to read 4, iclass 6, count 0 2006.173.19:41:05.83#ibcon#read 4, iclass 6, count 0 2006.173.19:41:05.83#ibcon#about to read 5, iclass 6, count 0 2006.173.19:41:05.83#ibcon#read 5, iclass 6, count 0 2006.173.19:41:05.83#ibcon#about to read 6, iclass 6, count 0 2006.173.19:41:05.83#ibcon#read 6, iclass 6, count 0 2006.173.19:41:05.83#ibcon#end of sib2, iclass 6, count 0 2006.173.19:41:05.83#ibcon#*mode == 0, iclass 6, count 0 2006.173.19:41:05.83#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.19:41:05.83#ibcon#[27=USB\r\n] 2006.173.19:41:05.83#ibcon#*before write, iclass 6, count 0 2006.173.19:41:05.83#ibcon#enter sib2, iclass 6, count 0 2006.173.19:41:05.83#ibcon#flushed, iclass 6, count 0 2006.173.19:41:05.83#ibcon#about to write, iclass 6, count 0 2006.173.19:41:05.83#ibcon#wrote, iclass 6, count 0 2006.173.19:41:05.83#ibcon#about to read 3, iclass 6, count 0 2006.173.19:41:05.86#ibcon#read 3, iclass 6, count 0 2006.173.19:41:05.86#ibcon#about to read 4, iclass 6, count 0 2006.173.19:41:05.86#ibcon#read 4, iclass 6, count 0 2006.173.19:41:05.86#ibcon#about to read 5, iclass 6, count 0 2006.173.19:41:05.86#ibcon#read 5, iclass 6, count 0 2006.173.19:41:05.86#ibcon#about to read 6, iclass 6, count 0 2006.173.19:41:05.86#ibcon#read 6, iclass 6, count 0 2006.173.19:41:05.86#ibcon#end of sib2, iclass 6, count 0 2006.173.19:41:05.86#ibcon#*after write, iclass 6, count 0 2006.173.19:41:05.86#ibcon#*before return 0, iclass 6, count 0 2006.173.19:41:05.86#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.19:41:05.86#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.19:41:05.86#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.19:41:05.86#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.19:41:05.86$vck44/vblo=7,734.99 2006.173.19:41:05.86#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.19:41:05.86#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.19:41:05.86#ibcon#ireg 17 cls_cnt 0 2006.173.19:41:05.86#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.19:41:05.86#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.19:41:05.86#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.19:41:05.86#ibcon#enter wrdev, iclass 10, count 0 2006.173.19:41:05.86#ibcon#first serial, iclass 10, count 0 2006.173.19:41:05.86#ibcon#enter sib2, iclass 10, count 0 2006.173.19:41:05.86#ibcon#flushed, iclass 10, count 0 2006.173.19:41:05.86#ibcon#about to write, iclass 10, count 0 2006.173.19:41:05.86#ibcon#wrote, iclass 10, count 0 2006.173.19:41:05.86#ibcon#about to read 3, iclass 10, count 0 2006.173.19:41:05.88#ibcon#read 3, iclass 10, count 0 2006.173.19:41:05.88#ibcon#about to read 4, iclass 10, count 0 2006.173.19:41:05.88#ibcon#read 4, iclass 10, count 0 2006.173.19:41:05.88#ibcon#about to read 5, iclass 10, count 0 2006.173.19:41:05.88#ibcon#read 5, iclass 10, count 0 2006.173.19:41:05.88#ibcon#about to read 6, iclass 10, count 0 2006.173.19:41:05.88#ibcon#read 6, iclass 10, count 0 2006.173.19:41:05.88#ibcon#end of sib2, iclass 10, count 0 2006.173.19:41:05.88#ibcon#*mode == 0, iclass 10, count 0 2006.173.19:41:05.88#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.19:41:05.88#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.19:41:05.88#ibcon#*before write, iclass 10, count 0 2006.173.19:41:05.88#ibcon#enter sib2, iclass 10, count 0 2006.173.19:41:05.88#ibcon#flushed, iclass 10, count 0 2006.173.19:41:05.88#ibcon#about to write, iclass 10, count 0 2006.173.19:41:05.88#ibcon#wrote, iclass 10, count 0 2006.173.19:41:05.88#ibcon#about to read 3, iclass 10, count 0 2006.173.19:41:05.92#ibcon#read 3, iclass 10, count 0 2006.173.19:41:05.92#ibcon#about to read 4, iclass 10, count 0 2006.173.19:41:05.92#ibcon#read 4, iclass 10, count 0 2006.173.19:41:05.92#ibcon#about to read 5, iclass 10, count 0 2006.173.19:41:05.92#ibcon#read 5, iclass 10, count 0 2006.173.19:41:05.92#ibcon#about to read 6, iclass 10, count 0 2006.173.19:41:05.92#ibcon#read 6, iclass 10, count 0 2006.173.19:41:05.92#ibcon#end of sib2, iclass 10, count 0 2006.173.19:41:05.92#ibcon#*after write, iclass 10, count 0 2006.173.19:41:05.92#ibcon#*before return 0, iclass 10, count 0 2006.173.19:41:05.92#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.19:41:05.92#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.19:41:05.92#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.19:41:05.92#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.19:41:05.92$vck44/vb=7,4 2006.173.19:41:05.92#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.19:41:05.92#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.19:41:05.92#ibcon#ireg 11 cls_cnt 2 2006.173.19:41:05.92#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.19:41:05.98#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.19:41:05.98#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.19:41:05.98#ibcon#enter wrdev, iclass 12, count 2 2006.173.19:41:05.98#ibcon#first serial, iclass 12, count 2 2006.173.19:41:05.98#ibcon#enter sib2, iclass 12, count 2 2006.173.19:41:05.98#ibcon#flushed, iclass 12, count 2 2006.173.19:41:05.98#ibcon#about to write, iclass 12, count 2 2006.173.19:41:05.98#ibcon#wrote, iclass 12, count 2 2006.173.19:41:05.98#ibcon#about to read 3, iclass 12, count 2 2006.173.19:41:06.00#ibcon#read 3, iclass 12, count 2 2006.173.19:41:06.00#ibcon#about to read 4, iclass 12, count 2 2006.173.19:41:06.00#ibcon#read 4, iclass 12, count 2 2006.173.19:41:06.00#ibcon#about to read 5, iclass 12, count 2 2006.173.19:41:06.00#ibcon#read 5, iclass 12, count 2 2006.173.19:41:06.00#ibcon#about to read 6, iclass 12, count 2 2006.173.19:41:06.00#ibcon#read 6, iclass 12, count 2 2006.173.19:41:06.00#ibcon#end of sib2, iclass 12, count 2 2006.173.19:41:06.00#ibcon#*mode == 0, iclass 12, count 2 2006.173.19:41:06.00#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.19:41:06.00#ibcon#[27=AT07-04\r\n] 2006.173.19:41:06.00#ibcon#*before write, iclass 12, count 2 2006.173.19:41:06.00#ibcon#enter sib2, iclass 12, count 2 2006.173.19:41:06.00#ibcon#flushed, iclass 12, count 2 2006.173.19:41:06.00#ibcon#about to write, iclass 12, count 2 2006.173.19:41:06.00#ibcon#wrote, iclass 12, count 2 2006.173.19:41:06.00#ibcon#about to read 3, iclass 12, count 2 2006.173.19:41:06.03#ibcon#read 3, iclass 12, count 2 2006.173.19:41:06.03#ibcon#about to read 4, iclass 12, count 2 2006.173.19:41:06.03#ibcon#read 4, iclass 12, count 2 2006.173.19:41:06.03#ibcon#about to read 5, iclass 12, count 2 2006.173.19:41:06.03#ibcon#read 5, iclass 12, count 2 2006.173.19:41:06.03#ibcon#about to read 6, iclass 12, count 2 2006.173.19:41:06.03#ibcon#read 6, iclass 12, count 2 2006.173.19:41:06.03#ibcon#end of sib2, iclass 12, count 2 2006.173.19:41:06.03#ibcon#*after write, iclass 12, count 2 2006.173.19:41:06.03#ibcon#*before return 0, iclass 12, count 2 2006.173.19:41:06.03#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.19:41:06.03#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.19:41:06.03#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.19:41:06.03#ibcon#ireg 7 cls_cnt 0 2006.173.19:41:06.03#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.19:41:06.15#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.19:41:06.15#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.19:41:06.15#ibcon#enter wrdev, iclass 12, count 0 2006.173.19:41:06.15#ibcon#first serial, iclass 12, count 0 2006.173.19:41:06.15#ibcon#enter sib2, iclass 12, count 0 2006.173.19:41:06.15#ibcon#flushed, iclass 12, count 0 2006.173.19:41:06.15#ibcon#about to write, iclass 12, count 0 2006.173.19:41:06.15#ibcon#wrote, iclass 12, count 0 2006.173.19:41:06.15#ibcon#about to read 3, iclass 12, count 0 2006.173.19:41:06.17#ibcon#read 3, iclass 12, count 0 2006.173.19:41:06.17#ibcon#about to read 4, iclass 12, count 0 2006.173.19:41:06.17#ibcon#read 4, iclass 12, count 0 2006.173.19:41:06.17#ibcon#about to read 5, iclass 12, count 0 2006.173.19:41:06.17#ibcon#read 5, iclass 12, count 0 2006.173.19:41:06.17#ibcon#about to read 6, iclass 12, count 0 2006.173.19:41:06.17#ibcon#read 6, iclass 12, count 0 2006.173.19:41:06.17#ibcon#end of sib2, iclass 12, count 0 2006.173.19:41:06.17#ibcon#*mode == 0, iclass 12, count 0 2006.173.19:41:06.17#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.19:41:06.17#ibcon#[27=USB\r\n] 2006.173.19:41:06.17#ibcon#*before write, iclass 12, count 0 2006.173.19:41:06.17#ibcon#enter sib2, iclass 12, count 0 2006.173.19:41:06.17#ibcon#flushed, iclass 12, count 0 2006.173.19:41:06.17#ibcon#about to write, iclass 12, count 0 2006.173.19:41:06.17#ibcon#wrote, iclass 12, count 0 2006.173.19:41:06.17#ibcon#about to read 3, iclass 12, count 0 2006.173.19:41:06.20#ibcon#read 3, iclass 12, count 0 2006.173.19:41:06.20#ibcon#about to read 4, iclass 12, count 0 2006.173.19:41:06.20#ibcon#read 4, iclass 12, count 0 2006.173.19:41:06.20#ibcon#about to read 5, iclass 12, count 0 2006.173.19:41:06.20#ibcon#read 5, iclass 12, count 0 2006.173.19:41:06.20#ibcon#about to read 6, iclass 12, count 0 2006.173.19:41:06.20#ibcon#read 6, iclass 12, count 0 2006.173.19:41:06.20#ibcon#end of sib2, iclass 12, count 0 2006.173.19:41:06.20#ibcon#*after write, iclass 12, count 0 2006.173.19:41:06.20#ibcon#*before return 0, iclass 12, count 0 2006.173.19:41:06.20#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.19:41:06.20#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.19:41:06.20#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.19:41:06.20#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.19:41:06.20$vck44/vblo=8,744.99 2006.173.19:41:06.20#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.19:41:06.20#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.19:41:06.20#ibcon#ireg 17 cls_cnt 0 2006.173.19:41:06.20#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.19:41:06.20#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.19:41:06.20#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.19:41:06.20#ibcon#enter wrdev, iclass 14, count 0 2006.173.19:41:06.20#ibcon#first serial, iclass 14, count 0 2006.173.19:41:06.20#ibcon#enter sib2, iclass 14, count 0 2006.173.19:41:06.20#ibcon#flushed, iclass 14, count 0 2006.173.19:41:06.20#ibcon#about to write, iclass 14, count 0 2006.173.19:41:06.20#ibcon#wrote, iclass 14, count 0 2006.173.19:41:06.20#ibcon#about to read 3, iclass 14, count 0 2006.173.19:41:06.22#ibcon#read 3, iclass 14, count 0 2006.173.19:41:06.22#ibcon#about to read 4, iclass 14, count 0 2006.173.19:41:06.22#ibcon#read 4, iclass 14, count 0 2006.173.19:41:06.22#ibcon#about to read 5, iclass 14, count 0 2006.173.19:41:06.22#ibcon#read 5, iclass 14, count 0 2006.173.19:41:06.22#ibcon#about to read 6, iclass 14, count 0 2006.173.19:41:06.22#ibcon#read 6, iclass 14, count 0 2006.173.19:41:06.22#ibcon#end of sib2, iclass 14, count 0 2006.173.19:41:06.22#ibcon#*mode == 0, iclass 14, count 0 2006.173.19:41:06.22#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.19:41:06.22#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.19:41:06.22#ibcon#*before write, iclass 14, count 0 2006.173.19:41:06.22#ibcon#enter sib2, iclass 14, count 0 2006.173.19:41:06.22#ibcon#flushed, iclass 14, count 0 2006.173.19:41:06.22#ibcon#about to write, iclass 14, count 0 2006.173.19:41:06.22#ibcon#wrote, iclass 14, count 0 2006.173.19:41:06.22#ibcon#about to read 3, iclass 14, count 0 2006.173.19:41:06.26#ibcon#read 3, iclass 14, count 0 2006.173.19:41:06.26#ibcon#about to read 4, iclass 14, count 0 2006.173.19:41:06.26#ibcon#read 4, iclass 14, count 0 2006.173.19:41:06.26#ibcon#about to read 5, iclass 14, count 0 2006.173.19:41:06.26#ibcon#read 5, iclass 14, count 0 2006.173.19:41:06.26#ibcon#about to read 6, iclass 14, count 0 2006.173.19:41:06.26#ibcon#read 6, iclass 14, count 0 2006.173.19:41:06.26#ibcon#end of sib2, iclass 14, count 0 2006.173.19:41:06.26#ibcon#*after write, iclass 14, count 0 2006.173.19:41:06.26#ibcon#*before return 0, iclass 14, count 0 2006.173.19:41:06.26#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.19:41:06.26#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.19:41:06.26#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.19:41:06.26#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.19:41:06.26$vck44/vb=8,4 2006.173.19:41:06.26#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.19:41:06.26#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.19:41:06.26#ibcon#ireg 11 cls_cnt 2 2006.173.19:41:06.26#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.19:41:06.32#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.19:41:06.32#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.19:41:06.32#ibcon#enter wrdev, iclass 16, count 2 2006.173.19:41:06.32#ibcon#first serial, iclass 16, count 2 2006.173.19:41:06.32#ibcon#enter sib2, iclass 16, count 2 2006.173.19:41:06.32#ibcon#flushed, iclass 16, count 2 2006.173.19:41:06.32#ibcon#about to write, iclass 16, count 2 2006.173.19:41:06.32#ibcon#wrote, iclass 16, count 2 2006.173.19:41:06.32#ibcon#about to read 3, iclass 16, count 2 2006.173.19:41:06.34#ibcon#read 3, iclass 16, count 2 2006.173.19:41:06.34#ibcon#about to read 4, iclass 16, count 2 2006.173.19:41:06.34#ibcon#read 4, iclass 16, count 2 2006.173.19:41:06.34#ibcon#about to read 5, iclass 16, count 2 2006.173.19:41:06.34#ibcon#read 5, iclass 16, count 2 2006.173.19:41:06.34#ibcon#about to read 6, iclass 16, count 2 2006.173.19:41:06.34#ibcon#read 6, iclass 16, count 2 2006.173.19:41:06.34#ibcon#end of sib2, iclass 16, count 2 2006.173.19:41:06.34#ibcon#*mode == 0, iclass 16, count 2 2006.173.19:41:06.34#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.19:41:06.34#ibcon#[27=AT08-04\r\n] 2006.173.19:41:06.34#ibcon#*before write, iclass 16, count 2 2006.173.19:41:06.34#ibcon#enter sib2, iclass 16, count 2 2006.173.19:41:06.34#ibcon#flushed, iclass 16, count 2 2006.173.19:41:06.34#ibcon#about to write, iclass 16, count 2 2006.173.19:41:06.34#ibcon#wrote, iclass 16, count 2 2006.173.19:41:06.34#ibcon#about to read 3, iclass 16, count 2 2006.173.19:41:06.37#ibcon#read 3, iclass 16, count 2 2006.173.19:41:06.37#ibcon#about to read 4, iclass 16, count 2 2006.173.19:41:06.37#ibcon#read 4, iclass 16, count 2 2006.173.19:41:06.37#ibcon#about to read 5, iclass 16, count 2 2006.173.19:41:06.37#ibcon#read 5, iclass 16, count 2 2006.173.19:41:06.37#ibcon#about to read 6, iclass 16, count 2 2006.173.19:41:06.37#ibcon#read 6, iclass 16, count 2 2006.173.19:41:06.37#ibcon#end of sib2, iclass 16, count 2 2006.173.19:41:06.37#ibcon#*after write, iclass 16, count 2 2006.173.19:41:06.37#ibcon#*before return 0, iclass 16, count 2 2006.173.19:41:06.37#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.19:41:06.37#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.19:41:06.37#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.19:41:06.37#ibcon#ireg 7 cls_cnt 0 2006.173.19:41:06.37#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.19:41:06.49#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.19:41:06.49#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.19:41:06.49#ibcon#enter wrdev, iclass 16, count 0 2006.173.19:41:06.49#ibcon#first serial, iclass 16, count 0 2006.173.19:41:06.49#ibcon#enter sib2, iclass 16, count 0 2006.173.19:41:06.49#ibcon#flushed, iclass 16, count 0 2006.173.19:41:06.49#ibcon#about to write, iclass 16, count 0 2006.173.19:41:06.49#ibcon#wrote, iclass 16, count 0 2006.173.19:41:06.49#ibcon#about to read 3, iclass 16, count 0 2006.173.19:41:06.51#ibcon#read 3, iclass 16, count 0 2006.173.19:41:06.51#ibcon#about to read 4, iclass 16, count 0 2006.173.19:41:06.51#ibcon#read 4, iclass 16, count 0 2006.173.19:41:06.51#ibcon#about to read 5, iclass 16, count 0 2006.173.19:41:06.51#ibcon#read 5, iclass 16, count 0 2006.173.19:41:06.51#ibcon#about to read 6, iclass 16, count 0 2006.173.19:41:06.51#ibcon#read 6, iclass 16, count 0 2006.173.19:41:06.51#ibcon#end of sib2, iclass 16, count 0 2006.173.19:41:06.51#ibcon#*mode == 0, iclass 16, count 0 2006.173.19:41:06.51#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.19:41:06.51#ibcon#[27=USB\r\n] 2006.173.19:41:06.51#ibcon#*before write, iclass 16, count 0 2006.173.19:41:06.51#ibcon#enter sib2, iclass 16, count 0 2006.173.19:41:06.51#ibcon#flushed, iclass 16, count 0 2006.173.19:41:06.51#ibcon#about to write, iclass 16, count 0 2006.173.19:41:06.51#ibcon#wrote, iclass 16, count 0 2006.173.19:41:06.51#ibcon#about to read 3, iclass 16, count 0 2006.173.19:41:06.54#ibcon#read 3, iclass 16, count 0 2006.173.19:41:06.54#ibcon#about to read 4, iclass 16, count 0 2006.173.19:41:06.54#ibcon#read 4, iclass 16, count 0 2006.173.19:41:06.54#ibcon#about to read 5, iclass 16, count 0 2006.173.19:41:06.54#ibcon#read 5, iclass 16, count 0 2006.173.19:41:06.54#ibcon#about to read 6, iclass 16, count 0 2006.173.19:41:06.54#ibcon#read 6, iclass 16, count 0 2006.173.19:41:06.54#ibcon#end of sib2, iclass 16, count 0 2006.173.19:41:06.54#ibcon#*after write, iclass 16, count 0 2006.173.19:41:06.54#ibcon#*before return 0, iclass 16, count 0 2006.173.19:41:06.54#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.19:41:06.54#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.19:41:06.54#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.19:41:06.54#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.19:41:06.54$vck44/vabw=wide 2006.173.19:41:06.54#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.19:41:06.54#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.19:41:06.54#ibcon#ireg 8 cls_cnt 0 2006.173.19:41:06.54#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.19:41:06.54#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.19:41:06.54#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.19:41:06.54#ibcon#enter wrdev, iclass 18, count 0 2006.173.19:41:06.54#ibcon#first serial, iclass 18, count 0 2006.173.19:41:06.54#ibcon#enter sib2, iclass 18, count 0 2006.173.19:41:06.54#ibcon#flushed, iclass 18, count 0 2006.173.19:41:06.54#ibcon#about to write, iclass 18, count 0 2006.173.19:41:06.54#ibcon#wrote, iclass 18, count 0 2006.173.19:41:06.54#ibcon#about to read 3, iclass 18, count 0 2006.173.19:41:06.56#ibcon#read 3, iclass 18, count 0 2006.173.19:41:06.56#ibcon#about to read 4, iclass 18, count 0 2006.173.19:41:06.56#ibcon#read 4, iclass 18, count 0 2006.173.19:41:06.56#ibcon#about to read 5, iclass 18, count 0 2006.173.19:41:06.56#ibcon#read 5, iclass 18, count 0 2006.173.19:41:06.56#ibcon#about to read 6, iclass 18, count 0 2006.173.19:41:06.56#ibcon#read 6, iclass 18, count 0 2006.173.19:41:06.56#ibcon#end of sib2, iclass 18, count 0 2006.173.19:41:06.56#ibcon#*mode == 0, iclass 18, count 0 2006.173.19:41:06.56#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.19:41:06.56#ibcon#[25=BW32\r\n] 2006.173.19:41:06.56#ibcon#*before write, iclass 18, count 0 2006.173.19:41:06.56#ibcon#enter sib2, iclass 18, count 0 2006.173.19:41:06.56#ibcon#flushed, iclass 18, count 0 2006.173.19:41:06.56#ibcon#about to write, iclass 18, count 0 2006.173.19:41:06.56#ibcon#wrote, iclass 18, count 0 2006.173.19:41:06.56#ibcon#about to read 3, iclass 18, count 0 2006.173.19:41:06.59#ibcon#read 3, iclass 18, count 0 2006.173.19:41:06.59#ibcon#about to read 4, iclass 18, count 0 2006.173.19:41:06.59#ibcon#read 4, iclass 18, count 0 2006.173.19:41:06.59#ibcon#about to read 5, iclass 18, count 0 2006.173.19:41:06.59#ibcon#read 5, iclass 18, count 0 2006.173.19:41:06.59#ibcon#about to read 6, iclass 18, count 0 2006.173.19:41:06.59#ibcon#read 6, iclass 18, count 0 2006.173.19:41:06.59#ibcon#end of sib2, iclass 18, count 0 2006.173.19:41:06.59#ibcon#*after write, iclass 18, count 0 2006.173.19:41:06.59#ibcon#*before return 0, iclass 18, count 0 2006.173.19:41:06.59#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.19:41:06.59#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.19:41:06.59#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.19:41:06.59#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.19:41:06.59$vck44/vbbw=wide 2006.173.19:41:06.59#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.19:41:06.59#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.19:41:06.59#ibcon#ireg 8 cls_cnt 0 2006.173.19:41:06.59#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.19:41:06.66#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.19:41:06.66#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.19:41:06.66#ibcon#enter wrdev, iclass 20, count 0 2006.173.19:41:06.66#ibcon#first serial, iclass 20, count 0 2006.173.19:41:06.66#ibcon#enter sib2, iclass 20, count 0 2006.173.19:41:06.66#ibcon#flushed, iclass 20, count 0 2006.173.19:41:06.66#ibcon#about to write, iclass 20, count 0 2006.173.19:41:06.66#ibcon#wrote, iclass 20, count 0 2006.173.19:41:06.66#ibcon#about to read 3, iclass 20, count 0 2006.173.19:41:06.68#ibcon#read 3, iclass 20, count 0 2006.173.19:41:06.68#ibcon#about to read 4, iclass 20, count 0 2006.173.19:41:06.68#ibcon#read 4, iclass 20, count 0 2006.173.19:41:06.68#ibcon#about to read 5, iclass 20, count 0 2006.173.19:41:06.68#ibcon#read 5, iclass 20, count 0 2006.173.19:41:06.68#ibcon#about to read 6, iclass 20, count 0 2006.173.19:41:06.68#ibcon#read 6, iclass 20, count 0 2006.173.19:41:06.68#ibcon#end of sib2, iclass 20, count 0 2006.173.19:41:06.68#ibcon#*mode == 0, iclass 20, count 0 2006.173.19:41:06.68#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.19:41:06.68#ibcon#[27=BW32\r\n] 2006.173.19:41:06.68#ibcon#*before write, iclass 20, count 0 2006.173.19:41:06.68#ibcon#enter sib2, iclass 20, count 0 2006.173.19:41:06.68#ibcon#flushed, iclass 20, count 0 2006.173.19:41:06.68#ibcon#about to write, iclass 20, count 0 2006.173.19:41:06.68#ibcon#wrote, iclass 20, count 0 2006.173.19:41:06.68#ibcon#about to read 3, iclass 20, count 0 2006.173.19:41:06.71#ibcon#read 3, iclass 20, count 0 2006.173.19:41:06.71#ibcon#about to read 4, iclass 20, count 0 2006.173.19:41:06.71#ibcon#read 4, iclass 20, count 0 2006.173.19:41:06.71#ibcon#about to read 5, iclass 20, count 0 2006.173.19:41:06.71#ibcon#read 5, iclass 20, count 0 2006.173.19:41:06.71#ibcon#about to read 6, iclass 20, count 0 2006.173.19:41:06.71#ibcon#read 6, iclass 20, count 0 2006.173.19:41:06.71#ibcon#end of sib2, iclass 20, count 0 2006.173.19:41:06.71#ibcon#*after write, iclass 20, count 0 2006.173.19:41:06.71#ibcon#*before return 0, iclass 20, count 0 2006.173.19:41:06.71#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.19:41:06.71#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.19:41:06.71#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.19:41:06.71#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.19:41:06.71$setupk4/ifdk4 2006.173.19:41:06.71$ifdk4/lo= 2006.173.19:41:06.71$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.19:41:06.71$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.19:41:06.71$ifdk4/patch= 2006.173.19:41:06.71$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.19:41:06.71$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.19:41:06.71$setupk4/!*+20s 2006.173.19:41:15.15#abcon#<5=/00 0.2 0.5 19.341001002.5\r\n> 2006.173.19:41:15.17#abcon#{5=INTERFACE CLEAR} 2006.173.19:41:15.23#abcon#[5=S1D000X0/0*\r\n] 2006.173.19:41:19.14#trakl#Source acquired 2006.173.19:41:20.14#flagr#flagr/antenna,acquired 2006.173.19:41:21.21$setupk4/"tpicd 2006.173.19:41:21.21$setupk4/echo=off 2006.173.19:41:21.21$setupk4/xlog=off 2006.173.19:41:21.21:!2006.173.19:46:06 2006.173.19:46:06.00:preob 2006.173.19:46:06.13/onsource/TRACKING 2006.173.19:46:06.13:!2006.173.19:46:16 2006.173.19:46:16.00:"tape 2006.173.19:46:16.00:"st=record 2006.173.19:46:16.00:data_valid=on 2006.173.19:46:16.00:midob 2006.173.19:46:17.13/onsource/TRACKING 2006.173.19:46:17.13/wx/19.33,1002.5,100 2006.173.19:46:17.28/cable/+6.5147E-03 2006.173.19:46:18.37/va/01,07,usb,yes,35,38 2006.173.19:46:18.37/va/02,06,usb,yes,35,36 2006.173.19:46:18.37/va/03,05,usb,yes,44,46 2006.173.19:46:18.37/va/04,06,usb,yes,36,37 2006.173.19:46:18.37/va/05,04,usb,yes,28,28 2006.173.19:46:18.37/va/06,03,usb,yes,39,39 2006.173.19:46:18.37/va/07,04,usb,yes,32,33 2006.173.19:46:18.37/va/08,04,usb,yes,27,32 2006.173.19:46:18.60/valo/01,524.99,yes,locked 2006.173.19:46:18.60/valo/02,534.99,yes,locked 2006.173.19:46:18.60/valo/03,564.99,yes,locked 2006.173.19:46:18.60/valo/04,624.99,yes,locked 2006.173.19:46:18.60/valo/05,734.99,yes,locked 2006.173.19:46:18.60/valo/06,814.99,yes,locked 2006.173.19:46:18.60/valo/07,864.99,yes,locked 2006.173.19:46:18.60/valo/08,884.99,yes,locked 2006.173.19:46:19.69/vb/01,04,usb,yes,29,27 2006.173.19:46:19.69/vb/02,04,usb,yes,31,31 2006.173.19:46:19.69/vb/03,04,usb,yes,28,31 2006.173.19:46:19.69/vb/04,04,usb,yes,32,31 2006.173.19:46:19.69/vb/05,04,usb,yes,25,27 2006.173.19:46:19.69/vb/06,04,usb,yes,29,26 2006.173.19:46:19.69/vb/07,04,usb,yes,29,29 2006.173.19:46:19.69/vb/08,04,usb,yes,27,30 2006.173.19:46:19.92/vblo/01,629.99,yes,locked 2006.173.19:46:19.92/vblo/02,634.99,yes,locked 2006.173.19:46:19.92/vblo/03,649.99,yes,locked 2006.173.19:46:19.92/vblo/04,679.99,yes,locked 2006.173.19:46:19.92/vblo/05,709.99,yes,locked 2006.173.19:46:19.92/vblo/06,719.99,yes,locked 2006.173.19:46:19.92/vblo/07,734.99,yes,locked 2006.173.19:46:19.92/vblo/08,744.99,yes,locked 2006.173.19:46:20.07/vabw/8 2006.173.19:46:20.22/vbbw/8 2006.173.19:46:20.31/xfe/off,on,15.2 2006.173.19:46:20.70/ifatt/23,28,28,28 2006.173.19:46:21.08/fmout-gps/S +3.88E-07 2006.173.19:46:21.12:!2006.173.19:47:26 2006.173.19:47:26.00:data_valid=off 2006.173.19:47:26.00:"et 2006.173.19:47:26.00:!+3s 2006.173.19:47:29.01:"tape 2006.173.19:47:29.01:postob 2006.173.19:47:29.20/cable/+6.5160E-03 2006.173.19:47:29.20/wx/19.32,1002.5,100 2006.173.19:47:30.08/fmout-gps/S +3.88E-07 2006.173.19:47:30.08:scan_name=173-1949,jd0606,340 2006.173.19:47:30.08:source=cta26,033930.94,-014635.8,2000.0,ccw 2006.173.19:47:31.13#flagr#flagr/antenna,new-source 2006.173.19:47:31.13:checkk5 2006.173.19:47:31.49/chk_autoobs//k5ts1/ autoobs is running! 2006.173.19:47:31.89/chk_autoobs//k5ts2/ autoobs is running! 2006.173.19:47:32.33/chk_autoobs//k5ts3/ autoobs is running! 2006.173.19:47:32.72/chk_autoobs//k5ts4/ autoobs is running! 2006.173.19:47:33.10/chk_obsdata//k5ts1/T1731946??a.dat file size is correct (nominal:280MB, actual:276MB). 2006.173.19:47:33.52/chk_obsdata//k5ts2/T1731946??b.dat file size is correct (nominal:280MB, actual:276MB). 2006.173.19:47:33.92/chk_obsdata//k5ts3/T1731946??c.dat file size is correct (nominal:280MB, actual:276MB). 2006.173.19:47:34.35/chk_obsdata//k5ts4/T1731946??d.dat file size is correct (nominal:280MB, actual:276MB). 2006.173.19:47:35.06/k5log//k5ts1_log_newline 2006.173.19:47:35.76/k5log//k5ts2_log_newline 2006.173.19:47:36.48/k5log//k5ts3_log_newline 2006.173.19:47:37.18/k5log//k5ts4_log_newline 2006.173.19:47:37.20/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.19:47:37.20:setupk4=1 2006.173.19:47:37.20$setupk4/echo=on 2006.173.19:47:37.20$setupk4/pcalon 2006.173.19:47:37.20$pcalon/"no phase cal control is implemented here 2006.173.19:47:37.20$setupk4/"tpicd=stop 2006.173.19:47:37.20$setupk4/"rec=synch_on 2006.173.19:47:37.20$setupk4/"rec_mode=128 2006.173.19:47:37.20$setupk4/!* 2006.173.19:47:37.20$setupk4/recpk4 2006.173.19:47:37.20$recpk4/recpatch= 2006.173.19:47:37.21$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.19:47:37.21$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.19:47:37.21$setupk4/vck44 2006.173.19:47:37.21$vck44/valo=1,524.99 2006.173.19:47:37.21#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.19:47:37.21#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.19:47:37.21#ibcon#ireg 17 cls_cnt 0 2006.173.19:47:37.21#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.19:47:37.21#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.19:47:37.21#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.19:47:37.21#ibcon#enter wrdev, iclass 28, count 0 2006.173.19:47:37.21#ibcon#first serial, iclass 28, count 0 2006.173.19:47:37.21#ibcon#enter sib2, iclass 28, count 0 2006.173.19:47:37.21#ibcon#flushed, iclass 28, count 0 2006.173.19:47:37.21#ibcon#about to write, iclass 28, count 0 2006.173.19:47:37.21#ibcon#wrote, iclass 28, count 0 2006.173.19:47:37.21#ibcon#about to read 3, iclass 28, count 0 2006.173.19:47:37.23#ibcon#read 3, iclass 28, count 0 2006.173.19:47:37.23#ibcon#about to read 4, iclass 28, count 0 2006.173.19:47:37.23#ibcon#read 4, iclass 28, count 0 2006.173.19:47:37.23#ibcon#about to read 5, iclass 28, count 0 2006.173.19:47:37.23#ibcon#read 5, iclass 28, count 0 2006.173.19:47:37.23#ibcon#about to read 6, iclass 28, count 0 2006.173.19:47:37.23#ibcon#read 6, iclass 28, count 0 2006.173.19:47:37.23#ibcon#end of sib2, iclass 28, count 0 2006.173.19:47:37.23#ibcon#*mode == 0, iclass 28, count 0 2006.173.19:47:37.23#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.19:47:37.23#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.19:47:37.23#ibcon#*before write, iclass 28, count 0 2006.173.19:47:37.23#ibcon#enter sib2, iclass 28, count 0 2006.173.19:47:37.23#ibcon#flushed, iclass 28, count 0 2006.173.19:47:37.23#ibcon#about to write, iclass 28, count 0 2006.173.19:47:37.23#ibcon#wrote, iclass 28, count 0 2006.173.19:47:37.23#ibcon#about to read 3, iclass 28, count 0 2006.173.19:47:37.28#ibcon#read 3, iclass 28, count 0 2006.173.19:47:37.28#ibcon#about to read 4, iclass 28, count 0 2006.173.19:47:37.28#ibcon#read 4, iclass 28, count 0 2006.173.19:47:37.28#ibcon#about to read 5, iclass 28, count 0 2006.173.19:47:37.28#ibcon#read 5, iclass 28, count 0 2006.173.19:47:37.28#ibcon#about to read 6, iclass 28, count 0 2006.173.19:47:37.28#ibcon#read 6, iclass 28, count 0 2006.173.19:47:37.28#ibcon#end of sib2, iclass 28, count 0 2006.173.19:47:37.28#ibcon#*after write, iclass 28, count 0 2006.173.19:47:37.28#ibcon#*before return 0, iclass 28, count 0 2006.173.19:47:37.28#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.19:47:37.28#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.19:47:37.28#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.19:47:37.28#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.19:47:37.28$vck44/va=1,7 2006.173.19:47:37.28#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.19:47:37.28#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.19:47:37.28#ibcon#ireg 11 cls_cnt 2 2006.173.19:47:37.28#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.19:47:37.28#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.19:47:37.28#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.19:47:37.28#ibcon#enter wrdev, iclass 30, count 2 2006.173.19:47:37.28#ibcon#first serial, iclass 30, count 2 2006.173.19:47:37.28#ibcon#enter sib2, iclass 30, count 2 2006.173.19:47:37.28#ibcon#flushed, iclass 30, count 2 2006.173.19:47:37.28#ibcon#about to write, iclass 30, count 2 2006.173.19:47:37.28#ibcon#wrote, iclass 30, count 2 2006.173.19:47:37.28#ibcon#about to read 3, iclass 30, count 2 2006.173.19:47:37.30#ibcon#read 3, iclass 30, count 2 2006.173.19:47:37.30#ibcon#about to read 4, iclass 30, count 2 2006.173.19:47:37.30#ibcon#read 4, iclass 30, count 2 2006.173.19:47:37.30#ibcon#about to read 5, iclass 30, count 2 2006.173.19:47:37.30#ibcon#read 5, iclass 30, count 2 2006.173.19:47:37.30#ibcon#about to read 6, iclass 30, count 2 2006.173.19:47:37.30#ibcon#read 6, iclass 30, count 2 2006.173.19:47:37.30#ibcon#end of sib2, iclass 30, count 2 2006.173.19:47:37.30#ibcon#*mode == 0, iclass 30, count 2 2006.173.19:47:37.30#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.19:47:37.30#ibcon#[25=AT01-07\r\n] 2006.173.19:47:37.30#ibcon#*before write, iclass 30, count 2 2006.173.19:47:37.30#ibcon#enter sib2, iclass 30, count 2 2006.173.19:47:37.30#ibcon#flushed, iclass 30, count 2 2006.173.19:47:37.30#ibcon#about to write, iclass 30, count 2 2006.173.19:47:37.30#ibcon#wrote, iclass 30, count 2 2006.173.19:47:37.30#ibcon#about to read 3, iclass 30, count 2 2006.173.19:47:37.33#ibcon#read 3, iclass 30, count 2 2006.173.19:47:37.33#ibcon#about to read 4, iclass 30, count 2 2006.173.19:47:37.33#ibcon#read 4, iclass 30, count 2 2006.173.19:47:37.33#ibcon#about to read 5, iclass 30, count 2 2006.173.19:47:37.33#ibcon#read 5, iclass 30, count 2 2006.173.19:47:37.33#ibcon#about to read 6, iclass 30, count 2 2006.173.19:47:37.33#ibcon#read 6, iclass 30, count 2 2006.173.19:47:37.33#ibcon#end of sib2, iclass 30, count 2 2006.173.19:47:37.33#ibcon#*after write, iclass 30, count 2 2006.173.19:47:37.33#ibcon#*before return 0, iclass 30, count 2 2006.173.19:47:37.33#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.19:47:37.33#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.19:47:37.33#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.19:47:37.33#ibcon#ireg 7 cls_cnt 0 2006.173.19:47:37.33#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.19:47:37.45#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.19:47:37.45#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.19:47:37.45#ibcon#enter wrdev, iclass 30, count 0 2006.173.19:47:37.45#ibcon#first serial, iclass 30, count 0 2006.173.19:47:37.45#ibcon#enter sib2, iclass 30, count 0 2006.173.19:47:37.45#ibcon#flushed, iclass 30, count 0 2006.173.19:47:37.45#ibcon#about to write, iclass 30, count 0 2006.173.19:47:37.45#ibcon#wrote, iclass 30, count 0 2006.173.19:47:37.45#ibcon#about to read 3, iclass 30, count 0 2006.173.19:47:37.47#ibcon#read 3, iclass 30, count 0 2006.173.19:47:37.47#ibcon#about to read 4, iclass 30, count 0 2006.173.19:47:37.47#ibcon#read 4, iclass 30, count 0 2006.173.19:47:37.47#ibcon#about to read 5, iclass 30, count 0 2006.173.19:47:37.47#ibcon#read 5, iclass 30, count 0 2006.173.19:47:37.47#ibcon#about to read 6, iclass 30, count 0 2006.173.19:47:37.47#ibcon#read 6, iclass 30, count 0 2006.173.19:47:37.47#ibcon#end of sib2, iclass 30, count 0 2006.173.19:47:37.47#ibcon#*mode == 0, iclass 30, count 0 2006.173.19:47:37.47#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.19:47:37.47#ibcon#[25=USB\r\n] 2006.173.19:47:37.47#ibcon#*before write, iclass 30, count 0 2006.173.19:47:37.47#ibcon#enter sib2, iclass 30, count 0 2006.173.19:47:37.47#ibcon#flushed, iclass 30, count 0 2006.173.19:47:37.47#ibcon#about to write, iclass 30, count 0 2006.173.19:47:37.47#ibcon#wrote, iclass 30, count 0 2006.173.19:47:37.47#ibcon#about to read 3, iclass 30, count 0 2006.173.19:47:37.50#ibcon#read 3, iclass 30, count 0 2006.173.19:47:37.50#ibcon#about to read 4, iclass 30, count 0 2006.173.19:47:37.50#ibcon#read 4, iclass 30, count 0 2006.173.19:47:37.50#ibcon#about to read 5, iclass 30, count 0 2006.173.19:47:37.50#ibcon#read 5, iclass 30, count 0 2006.173.19:47:37.50#ibcon#about to read 6, iclass 30, count 0 2006.173.19:47:37.50#ibcon#read 6, iclass 30, count 0 2006.173.19:47:37.50#ibcon#end of sib2, iclass 30, count 0 2006.173.19:47:37.50#ibcon#*after write, iclass 30, count 0 2006.173.19:47:37.50#ibcon#*before return 0, iclass 30, count 0 2006.173.19:47:37.50#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.19:47:37.50#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.19:47:37.50#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.19:47:37.50#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.19:47:37.50$vck44/valo=2,534.99 2006.173.19:47:37.50#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.19:47:37.50#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.19:47:37.50#ibcon#ireg 17 cls_cnt 0 2006.173.19:47:37.50#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.19:47:37.50#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.19:47:37.50#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.19:47:37.50#ibcon#enter wrdev, iclass 32, count 0 2006.173.19:47:37.50#ibcon#first serial, iclass 32, count 0 2006.173.19:47:37.50#ibcon#enter sib2, iclass 32, count 0 2006.173.19:47:37.50#ibcon#flushed, iclass 32, count 0 2006.173.19:47:37.50#ibcon#about to write, iclass 32, count 0 2006.173.19:47:37.50#ibcon#wrote, iclass 32, count 0 2006.173.19:47:37.50#ibcon#about to read 3, iclass 32, count 0 2006.173.19:47:37.52#ibcon#read 3, iclass 32, count 0 2006.173.19:47:37.52#ibcon#about to read 4, iclass 32, count 0 2006.173.19:47:37.52#ibcon#read 4, iclass 32, count 0 2006.173.19:47:37.52#ibcon#about to read 5, iclass 32, count 0 2006.173.19:47:37.52#ibcon#read 5, iclass 32, count 0 2006.173.19:47:37.52#ibcon#about to read 6, iclass 32, count 0 2006.173.19:47:37.52#ibcon#read 6, iclass 32, count 0 2006.173.19:47:37.52#ibcon#end of sib2, iclass 32, count 0 2006.173.19:47:37.52#ibcon#*mode == 0, iclass 32, count 0 2006.173.19:47:37.52#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.19:47:37.52#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.19:47:37.52#ibcon#*before write, iclass 32, count 0 2006.173.19:47:37.52#ibcon#enter sib2, iclass 32, count 0 2006.173.19:47:37.52#ibcon#flushed, iclass 32, count 0 2006.173.19:47:37.52#ibcon#about to write, iclass 32, count 0 2006.173.19:47:37.52#ibcon#wrote, iclass 32, count 0 2006.173.19:47:37.52#ibcon#about to read 3, iclass 32, count 0 2006.173.19:47:37.56#ibcon#read 3, iclass 32, count 0 2006.173.19:47:37.56#ibcon#about to read 4, iclass 32, count 0 2006.173.19:47:37.56#ibcon#read 4, iclass 32, count 0 2006.173.19:47:37.56#ibcon#about to read 5, iclass 32, count 0 2006.173.19:47:37.56#ibcon#read 5, iclass 32, count 0 2006.173.19:47:37.56#ibcon#about to read 6, iclass 32, count 0 2006.173.19:47:37.56#ibcon#read 6, iclass 32, count 0 2006.173.19:47:37.56#ibcon#end of sib2, iclass 32, count 0 2006.173.19:47:37.56#ibcon#*after write, iclass 32, count 0 2006.173.19:47:37.56#ibcon#*before return 0, iclass 32, count 0 2006.173.19:47:37.56#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.19:47:37.56#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.19:47:37.56#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.19:47:37.56#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.19:47:37.56$vck44/va=2,6 2006.173.19:47:37.56#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.19:47:37.56#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.19:47:37.56#ibcon#ireg 11 cls_cnt 2 2006.173.19:47:37.56#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.19:47:37.62#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.19:47:37.62#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.19:47:37.62#ibcon#enter wrdev, iclass 34, count 2 2006.173.19:47:37.62#ibcon#first serial, iclass 34, count 2 2006.173.19:47:37.62#ibcon#enter sib2, iclass 34, count 2 2006.173.19:47:37.62#ibcon#flushed, iclass 34, count 2 2006.173.19:47:37.62#ibcon#about to write, iclass 34, count 2 2006.173.19:47:37.62#ibcon#wrote, iclass 34, count 2 2006.173.19:47:37.62#ibcon#about to read 3, iclass 34, count 2 2006.173.19:47:37.64#ibcon#read 3, iclass 34, count 2 2006.173.19:47:37.64#ibcon#about to read 4, iclass 34, count 2 2006.173.19:47:37.64#ibcon#read 4, iclass 34, count 2 2006.173.19:47:37.64#ibcon#about to read 5, iclass 34, count 2 2006.173.19:47:37.64#ibcon#read 5, iclass 34, count 2 2006.173.19:47:37.64#ibcon#about to read 6, iclass 34, count 2 2006.173.19:47:37.64#ibcon#read 6, iclass 34, count 2 2006.173.19:47:37.64#ibcon#end of sib2, iclass 34, count 2 2006.173.19:47:37.64#ibcon#*mode == 0, iclass 34, count 2 2006.173.19:47:37.64#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.19:47:37.64#ibcon#[25=AT02-06\r\n] 2006.173.19:47:37.64#ibcon#*before write, iclass 34, count 2 2006.173.19:47:37.64#ibcon#enter sib2, iclass 34, count 2 2006.173.19:47:37.64#ibcon#flushed, iclass 34, count 2 2006.173.19:47:37.64#ibcon#about to write, iclass 34, count 2 2006.173.19:47:37.64#ibcon#wrote, iclass 34, count 2 2006.173.19:47:37.64#ibcon#about to read 3, iclass 34, count 2 2006.173.19:47:37.67#ibcon#read 3, iclass 34, count 2 2006.173.19:47:37.67#ibcon#about to read 4, iclass 34, count 2 2006.173.19:47:37.67#ibcon#read 4, iclass 34, count 2 2006.173.19:47:37.67#ibcon#about to read 5, iclass 34, count 2 2006.173.19:47:37.67#ibcon#read 5, iclass 34, count 2 2006.173.19:47:37.67#ibcon#about to read 6, iclass 34, count 2 2006.173.19:47:37.67#ibcon#read 6, iclass 34, count 2 2006.173.19:47:37.67#ibcon#end of sib2, iclass 34, count 2 2006.173.19:47:37.67#ibcon#*after write, iclass 34, count 2 2006.173.19:47:37.67#ibcon#*before return 0, iclass 34, count 2 2006.173.19:47:37.67#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.19:47:37.67#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.19:47:37.67#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.19:47:37.67#ibcon#ireg 7 cls_cnt 0 2006.173.19:47:37.67#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.19:47:37.79#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.19:47:37.79#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.19:47:37.79#ibcon#enter wrdev, iclass 34, count 0 2006.173.19:47:37.79#ibcon#first serial, iclass 34, count 0 2006.173.19:47:37.79#ibcon#enter sib2, iclass 34, count 0 2006.173.19:47:37.79#ibcon#flushed, iclass 34, count 0 2006.173.19:47:37.79#ibcon#about to write, iclass 34, count 0 2006.173.19:47:37.79#ibcon#wrote, iclass 34, count 0 2006.173.19:47:37.79#ibcon#about to read 3, iclass 34, count 0 2006.173.19:47:37.81#ibcon#read 3, iclass 34, count 0 2006.173.19:47:37.81#ibcon#about to read 4, iclass 34, count 0 2006.173.19:47:37.81#ibcon#read 4, iclass 34, count 0 2006.173.19:47:37.81#ibcon#about to read 5, iclass 34, count 0 2006.173.19:47:37.81#ibcon#read 5, iclass 34, count 0 2006.173.19:47:37.81#ibcon#about to read 6, iclass 34, count 0 2006.173.19:47:37.81#ibcon#read 6, iclass 34, count 0 2006.173.19:47:37.81#ibcon#end of sib2, iclass 34, count 0 2006.173.19:47:37.81#ibcon#*mode == 0, iclass 34, count 0 2006.173.19:47:37.81#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.19:47:37.81#ibcon#[25=USB\r\n] 2006.173.19:47:37.81#ibcon#*before write, iclass 34, count 0 2006.173.19:47:37.81#ibcon#enter sib2, iclass 34, count 0 2006.173.19:47:37.81#ibcon#flushed, iclass 34, count 0 2006.173.19:47:37.81#ibcon#about to write, iclass 34, count 0 2006.173.19:47:37.81#ibcon#wrote, iclass 34, count 0 2006.173.19:47:37.81#ibcon#about to read 3, iclass 34, count 0 2006.173.19:47:37.84#ibcon#read 3, iclass 34, count 0 2006.173.19:47:37.84#ibcon#about to read 4, iclass 34, count 0 2006.173.19:47:37.84#ibcon#read 4, iclass 34, count 0 2006.173.19:47:37.84#ibcon#about to read 5, iclass 34, count 0 2006.173.19:47:37.84#ibcon#read 5, iclass 34, count 0 2006.173.19:47:37.84#ibcon#about to read 6, iclass 34, count 0 2006.173.19:47:37.84#ibcon#read 6, iclass 34, count 0 2006.173.19:47:37.84#ibcon#end of sib2, iclass 34, count 0 2006.173.19:47:37.84#ibcon#*after write, iclass 34, count 0 2006.173.19:47:37.84#ibcon#*before return 0, iclass 34, count 0 2006.173.19:47:37.84#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.19:47:37.84#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.19:47:37.84#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.19:47:37.84#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.19:47:37.84$vck44/valo=3,564.99 2006.173.19:47:37.84#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.19:47:37.84#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.19:47:37.84#ibcon#ireg 17 cls_cnt 0 2006.173.19:47:37.84#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.19:47:37.84#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.19:47:37.84#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.19:47:37.84#ibcon#enter wrdev, iclass 36, count 0 2006.173.19:47:37.84#ibcon#first serial, iclass 36, count 0 2006.173.19:47:37.84#ibcon#enter sib2, iclass 36, count 0 2006.173.19:47:37.84#ibcon#flushed, iclass 36, count 0 2006.173.19:47:37.84#ibcon#about to write, iclass 36, count 0 2006.173.19:47:37.84#ibcon#wrote, iclass 36, count 0 2006.173.19:47:37.84#ibcon#about to read 3, iclass 36, count 0 2006.173.19:47:37.86#ibcon#read 3, iclass 36, count 0 2006.173.19:47:37.86#ibcon#about to read 4, iclass 36, count 0 2006.173.19:47:37.86#ibcon#read 4, iclass 36, count 0 2006.173.19:47:37.86#ibcon#about to read 5, iclass 36, count 0 2006.173.19:47:37.86#ibcon#read 5, iclass 36, count 0 2006.173.19:47:37.86#ibcon#about to read 6, iclass 36, count 0 2006.173.19:47:37.86#ibcon#read 6, iclass 36, count 0 2006.173.19:47:37.86#ibcon#end of sib2, iclass 36, count 0 2006.173.19:47:37.86#ibcon#*mode == 0, iclass 36, count 0 2006.173.19:47:37.86#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.19:47:37.86#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.19:47:37.86#ibcon#*before write, iclass 36, count 0 2006.173.19:47:37.86#ibcon#enter sib2, iclass 36, count 0 2006.173.19:47:37.86#ibcon#flushed, iclass 36, count 0 2006.173.19:47:37.86#ibcon#about to write, iclass 36, count 0 2006.173.19:47:37.86#ibcon#wrote, iclass 36, count 0 2006.173.19:47:37.86#ibcon#about to read 3, iclass 36, count 0 2006.173.19:47:37.90#ibcon#read 3, iclass 36, count 0 2006.173.19:47:37.90#ibcon#about to read 4, iclass 36, count 0 2006.173.19:47:37.90#ibcon#read 4, iclass 36, count 0 2006.173.19:47:37.90#ibcon#about to read 5, iclass 36, count 0 2006.173.19:47:37.90#ibcon#read 5, iclass 36, count 0 2006.173.19:47:37.90#ibcon#about to read 6, iclass 36, count 0 2006.173.19:47:37.90#ibcon#read 6, iclass 36, count 0 2006.173.19:47:37.90#ibcon#end of sib2, iclass 36, count 0 2006.173.19:47:37.90#ibcon#*after write, iclass 36, count 0 2006.173.19:47:37.90#ibcon#*before return 0, iclass 36, count 0 2006.173.19:47:37.90#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.19:47:37.90#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.19:47:37.90#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.19:47:37.90#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.19:47:37.90$vck44/va=3,5 2006.173.19:47:37.90#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.19:47:37.90#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.19:47:37.90#ibcon#ireg 11 cls_cnt 2 2006.173.19:47:37.90#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.19:47:37.96#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.19:47:37.96#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.19:47:37.96#ibcon#enter wrdev, iclass 38, count 2 2006.173.19:47:37.96#ibcon#first serial, iclass 38, count 2 2006.173.19:47:37.96#ibcon#enter sib2, iclass 38, count 2 2006.173.19:47:37.96#ibcon#flushed, iclass 38, count 2 2006.173.19:47:37.96#ibcon#about to write, iclass 38, count 2 2006.173.19:47:37.96#ibcon#wrote, iclass 38, count 2 2006.173.19:47:37.96#ibcon#about to read 3, iclass 38, count 2 2006.173.19:47:37.98#ibcon#read 3, iclass 38, count 2 2006.173.19:47:37.98#ibcon#about to read 4, iclass 38, count 2 2006.173.19:47:37.98#ibcon#read 4, iclass 38, count 2 2006.173.19:47:37.98#ibcon#about to read 5, iclass 38, count 2 2006.173.19:47:37.98#ibcon#read 5, iclass 38, count 2 2006.173.19:47:37.98#ibcon#about to read 6, iclass 38, count 2 2006.173.19:47:37.98#ibcon#read 6, iclass 38, count 2 2006.173.19:47:37.98#ibcon#end of sib2, iclass 38, count 2 2006.173.19:47:37.98#ibcon#*mode == 0, iclass 38, count 2 2006.173.19:47:37.98#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.19:47:37.98#ibcon#[25=AT03-05\r\n] 2006.173.19:47:37.98#ibcon#*before write, iclass 38, count 2 2006.173.19:47:37.98#ibcon#enter sib2, iclass 38, count 2 2006.173.19:47:37.98#ibcon#flushed, iclass 38, count 2 2006.173.19:47:37.98#ibcon#about to write, iclass 38, count 2 2006.173.19:47:37.98#ibcon#wrote, iclass 38, count 2 2006.173.19:47:37.98#ibcon#about to read 3, iclass 38, count 2 2006.173.19:47:38.01#ibcon#read 3, iclass 38, count 2 2006.173.19:47:38.01#ibcon#about to read 4, iclass 38, count 2 2006.173.19:47:38.01#ibcon#read 4, iclass 38, count 2 2006.173.19:47:38.01#ibcon#about to read 5, iclass 38, count 2 2006.173.19:47:38.01#ibcon#read 5, iclass 38, count 2 2006.173.19:47:38.01#ibcon#about to read 6, iclass 38, count 2 2006.173.19:47:38.01#ibcon#read 6, iclass 38, count 2 2006.173.19:47:38.01#ibcon#end of sib2, iclass 38, count 2 2006.173.19:47:38.01#ibcon#*after write, iclass 38, count 2 2006.173.19:47:38.01#ibcon#*before return 0, iclass 38, count 2 2006.173.19:47:38.01#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.19:47:38.01#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.19:47:38.01#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.19:47:38.01#ibcon#ireg 7 cls_cnt 0 2006.173.19:47:38.01#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.19:47:38.13#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.19:47:38.13#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.19:47:38.13#ibcon#enter wrdev, iclass 38, count 0 2006.173.19:47:38.13#ibcon#first serial, iclass 38, count 0 2006.173.19:47:38.13#ibcon#enter sib2, iclass 38, count 0 2006.173.19:47:38.13#ibcon#flushed, iclass 38, count 0 2006.173.19:47:38.13#ibcon#about to write, iclass 38, count 0 2006.173.19:47:38.13#ibcon#wrote, iclass 38, count 0 2006.173.19:47:38.13#ibcon#about to read 3, iclass 38, count 0 2006.173.19:47:38.15#ibcon#read 3, iclass 38, count 0 2006.173.19:47:38.15#ibcon#about to read 4, iclass 38, count 0 2006.173.19:47:38.15#ibcon#read 4, iclass 38, count 0 2006.173.19:47:38.15#ibcon#about to read 5, iclass 38, count 0 2006.173.19:47:38.15#ibcon#read 5, iclass 38, count 0 2006.173.19:47:38.15#ibcon#about to read 6, iclass 38, count 0 2006.173.19:47:38.15#ibcon#read 6, iclass 38, count 0 2006.173.19:47:38.15#ibcon#end of sib2, iclass 38, count 0 2006.173.19:47:38.15#ibcon#*mode == 0, iclass 38, count 0 2006.173.19:47:38.15#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.19:47:38.15#ibcon#[25=USB\r\n] 2006.173.19:47:38.15#ibcon#*before write, iclass 38, count 0 2006.173.19:47:38.15#ibcon#enter sib2, iclass 38, count 0 2006.173.19:47:38.15#ibcon#flushed, iclass 38, count 0 2006.173.19:47:38.15#ibcon#about to write, iclass 38, count 0 2006.173.19:47:38.15#ibcon#wrote, iclass 38, count 0 2006.173.19:47:38.15#ibcon#about to read 3, iclass 38, count 0 2006.173.19:47:38.18#ibcon#read 3, iclass 38, count 0 2006.173.19:47:38.18#ibcon#about to read 4, iclass 38, count 0 2006.173.19:47:38.18#ibcon#read 4, iclass 38, count 0 2006.173.19:47:38.18#ibcon#about to read 5, iclass 38, count 0 2006.173.19:47:38.18#ibcon#read 5, iclass 38, count 0 2006.173.19:47:38.18#ibcon#about to read 6, iclass 38, count 0 2006.173.19:47:38.18#ibcon#read 6, iclass 38, count 0 2006.173.19:47:38.18#ibcon#end of sib2, iclass 38, count 0 2006.173.19:47:38.18#ibcon#*after write, iclass 38, count 0 2006.173.19:47:38.18#ibcon#*before return 0, iclass 38, count 0 2006.173.19:47:38.18#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.19:47:38.18#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.19:47:38.18#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.19:47:38.18#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.19:47:38.18$vck44/valo=4,624.99 2006.173.19:47:38.18#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.19:47:38.18#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.19:47:38.18#ibcon#ireg 17 cls_cnt 0 2006.173.19:47:38.18#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.19:47:38.18#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.19:47:38.18#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.19:47:38.18#ibcon#enter wrdev, iclass 40, count 0 2006.173.19:47:38.18#ibcon#first serial, iclass 40, count 0 2006.173.19:47:38.18#ibcon#enter sib2, iclass 40, count 0 2006.173.19:47:38.18#ibcon#flushed, iclass 40, count 0 2006.173.19:47:38.18#ibcon#about to write, iclass 40, count 0 2006.173.19:47:38.18#ibcon#wrote, iclass 40, count 0 2006.173.19:47:38.18#ibcon#about to read 3, iclass 40, count 0 2006.173.19:47:38.20#ibcon#read 3, iclass 40, count 0 2006.173.19:47:38.20#ibcon#about to read 4, iclass 40, count 0 2006.173.19:47:38.20#ibcon#read 4, iclass 40, count 0 2006.173.19:47:38.20#ibcon#about to read 5, iclass 40, count 0 2006.173.19:47:38.20#ibcon#read 5, iclass 40, count 0 2006.173.19:47:38.20#ibcon#about to read 6, iclass 40, count 0 2006.173.19:47:38.20#ibcon#read 6, iclass 40, count 0 2006.173.19:47:38.20#ibcon#end of sib2, iclass 40, count 0 2006.173.19:47:38.20#ibcon#*mode == 0, iclass 40, count 0 2006.173.19:47:38.20#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.19:47:38.20#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.19:47:38.20#ibcon#*before write, iclass 40, count 0 2006.173.19:47:38.20#ibcon#enter sib2, iclass 40, count 0 2006.173.19:47:38.20#ibcon#flushed, iclass 40, count 0 2006.173.19:47:38.20#ibcon#about to write, iclass 40, count 0 2006.173.19:47:38.20#ibcon#wrote, iclass 40, count 0 2006.173.19:47:38.20#ibcon#about to read 3, iclass 40, count 0 2006.173.19:47:38.24#ibcon#read 3, iclass 40, count 0 2006.173.19:47:38.24#ibcon#about to read 4, iclass 40, count 0 2006.173.19:47:38.24#ibcon#read 4, iclass 40, count 0 2006.173.19:47:38.24#ibcon#about to read 5, iclass 40, count 0 2006.173.19:47:38.24#ibcon#read 5, iclass 40, count 0 2006.173.19:47:38.24#ibcon#about to read 6, iclass 40, count 0 2006.173.19:47:38.24#ibcon#read 6, iclass 40, count 0 2006.173.19:47:38.24#ibcon#end of sib2, iclass 40, count 0 2006.173.19:47:38.24#ibcon#*after write, iclass 40, count 0 2006.173.19:47:38.24#ibcon#*before return 0, iclass 40, count 0 2006.173.19:47:38.24#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.19:47:38.24#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.19:47:38.24#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.19:47:38.24#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.19:47:38.24$vck44/va=4,6 2006.173.19:47:38.24#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.19:47:38.24#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.19:47:38.24#ibcon#ireg 11 cls_cnt 2 2006.173.19:47:38.24#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.19:47:38.30#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.19:47:38.30#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.19:47:38.30#ibcon#enter wrdev, iclass 4, count 2 2006.173.19:47:38.30#ibcon#first serial, iclass 4, count 2 2006.173.19:47:38.30#ibcon#enter sib2, iclass 4, count 2 2006.173.19:47:38.30#ibcon#flushed, iclass 4, count 2 2006.173.19:47:38.30#ibcon#about to write, iclass 4, count 2 2006.173.19:47:38.30#ibcon#wrote, iclass 4, count 2 2006.173.19:47:38.30#ibcon#about to read 3, iclass 4, count 2 2006.173.19:47:38.32#ibcon#read 3, iclass 4, count 2 2006.173.19:47:38.32#ibcon#about to read 4, iclass 4, count 2 2006.173.19:47:38.32#ibcon#read 4, iclass 4, count 2 2006.173.19:47:38.32#ibcon#about to read 5, iclass 4, count 2 2006.173.19:47:38.32#ibcon#read 5, iclass 4, count 2 2006.173.19:47:38.32#ibcon#about to read 6, iclass 4, count 2 2006.173.19:47:38.32#ibcon#read 6, iclass 4, count 2 2006.173.19:47:38.32#ibcon#end of sib2, iclass 4, count 2 2006.173.19:47:38.32#ibcon#*mode == 0, iclass 4, count 2 2006.173.19:47:38.32#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.19:47:38.32#ibcon#[25=AT04-06\r\n] 2006.173.19:47:38.32#ibcon#*before write, iclass 4, count 2 2006.173.19:47:38.32#ibcon#enter sib2, iclass 4, count 2 2006.173.19:47:38.32#ibcon#flushed, iclass 4, count 2 2006.173.19:47:38.32#ibcon#about to write, iclass 4, count 2 2006.173.19:47:38.32#ibcon#wrote, iclass 4, count 2 2006.173.19:47:38.32#ibcon#about to read 3, iclass 4, count 2 2006.173.19:47:38.35#ibcon#read 3, iclass 4, count 2 2006.173.19:47:38.35#ibcon#about to read 4, iclass 4, count 2 2006.173.19:47:38.35#ibcon#read 4, iclass 4, count 2 2006.173.19:47:38.35#ibcon#about to read 5, iclass 4, count 2 2006.173.19:47:38.35#ibcon#read 5, iclass 4, count 2 2006.173.19:47:38.35#ibcon#about to read 6, iclass 4, count 2 2006.173.19:47:38.35#ibcon#read 6, iclass 4, count 2 2006.173.19:47:38.35#ibcon#end of sib2, iclass 4, count 2 2006.173.19:47:38.35#ibcon#*after write, iclass 4, count 2 2006.173.19:47:38.35#ibcon#*before return 0, iclass 4, count 2 2006.173.19:47:38.35#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.19:47:38.35#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.19:47:38.35#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.19:47:38.35#ibcon#ireg 7 cls_cnt 0 2006.173.19:47:38.35#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.19:47:38.47#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.19:47:38.47#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.19:47:38.47#ibcon#enter wrdev, iclass 4, count 0 2006.173.19:47:38.47#ibcon#first serial, iclass 4, count 0 2006.173.19:47:38.47#ibcon#enter sib2, iclass 4, count 0 2006.173.19:47:38.47#ibcon#flushed, iclass 4, count 0 2006.173.19:47:38.47#ibcon#about to write, iclass 4, count 0 2006.173.19:47:38.47#ibcon#wrote, iclass 4, count 0 2006.173.19:47:38.47#ibcon#about to read 3, iclass 4, count 0 2006.173.19:47:38.49#ibcon#read 3, iclass 4, count 0 2006.173.19:47:38.49#ibcon#about to read 4, iclass 4, count 0 2006.173.19:47:38.49#ibcon#read 4, iclass 4, count 0 2006.173.19:47:38.49#ibcon#about to read 5, iclass 4, count 0 2006.173.19:47:38.49#ibcon#read 5, iclass 4, count 0 2006.173.19:47:38.49#ibcon#about to read 6, iclass 4, count 0 2006.173.19:47:38.49#ibcon#read 6, iclass 4, count 0 2006.173.19:47:38.49#ibcon#end of sib2, iclass 4, count 0 2006.173.19:47:38.49#ibcon#*mode == 0, iclass 4, count 0 2006.173.19:47:38.49#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.19:47:38.49#ibcon#[25=USB\r\n] 2006.173.19:47:38.49#ibcon#*before write, iclass 4, count 0 2006.173.19:47:38.49#ibcon#enter sib2, iclass 4, count 0 2006.173.19:47:38.49#ibcon#flushed, iclass 4, count 0 2006.173.19:47:38.49#ibcon#about to write, iclass 4, count 0 2006.173.19:47:38.49#ibcon#wrote, iclass 4, count 0 2006.173.19:47:38.49#ibcon#about to read 3, iclass 4, count 0 2006.173.19:47:38.52#ibcon#read 3, iclass 4, count 0 2006.173.19:47:38.52#ibcon#about to read 4, iclass 4, count 0 2006.173.19:47:38.52#ibcon#read 4, iclass 4, count 0 2006.173.19:47:38.52#ibcon#about to read 5, iclass 4, count 0 2006.173.19:47:38.52#ibcon#read 5, iclass 4, count 0 2006.173.19:47:38.52#ibcon#about to read 6, iclass 4, count 0 2006.173.19:47:38.52#ibcon#read 6, iclass 4, count 0 2006.173.19:47:38.52#ibcon#end of sib2, iclass 4, count 0 2006.173.19:47:38.52#ibcon#*after write, iclass 4, count 0 2006.173.19:47:38.52#ibcon#*before return 0, iclass 4, count 0 2006.173.19:47:38.52#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.19:47:38.52#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.19:47:38.52#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.19:47:38.52#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.19:47:38.52$vck44/valo=5,734.99 2006.173.19:47:38.52#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.19:47:38.52#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.19:47:38.52#ibcon#ireg 17 cls_cnt 0 2006.173.19:47:38.52#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.19:47:38.52#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.19:47:38.52#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.19:47:38.52#ibcon#enter wrdev, iclass 6, count 0 2006.173.19:47:38.52#ibcon#first serial, iclass 6, count 0 2006.173.19:47:38.52#ibcon#enter sib2, iclass 6, count 0 2006.173.19:47:38.52#ibcon#flushed, iclass 6, count 0 2006.173.19:47:38.52#ibcon#about to write, iclass 6, count 0 2006.173.19:47:38.52#ibcon#wrote, iclass 6, count 0 2006.173.19:47:38.52#ibcon#about to read 3, iclass 6, count 0 2006.173.19:47:38.54#ibcon#read 3, iclass 6, count 0 2006.173.19:47:38.54#ibcon#about to read 4, iclass 6, count 0 2006.173.19:47:38.54#ibcon#read 4, iclass 6, count 0 2006.173.19:47:38.54#ibcon#about to read 5, iclass 6, count 0 2006.173.19:47:38.54#ibcon#read 5, iclass 6, count 0 2006.173.19:47:38.54#ibcon#about to read 6, iclass 6, count 0 2006.173.19:47:38.54#ibcon#read 6, iclass 6, count 0 2006.173.19:47:38.54#ibcon#end of sib2, iclass 6, count 0 2006.173.19:47:38.54#ibcon#*mode == 0, iclass 6, count 0 2006.173.19:47:38.54#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.19:47:38.54#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.19:47:38.54#ibcon#*before write, iclass 6, count 0 2006.173.19:47:38.54#ibcon#enter sib2, iclass 6, count 0 2006.173.19:47:38.54#ibcon#flushed, iclass 6, count 0 2006.173.19:47:38.54#ibcon#about to write, iclass 6, count 0 2006.173.19:47:38.54#ibcon#wrote, iclass 6, count 0 2006.173.19:47:38.54#ibcon#about to read 3, iclass 6, count 0 2006.173.19:47:38.58#ibcon#read 3, iclass 6, count 0 2006.173.19:47:38.58#ibcon#about to read 4, iclass 6, count 0 2006.173.19:47:38.58#ibcon#read 4, iclass 6, count 0 2006.173.19:47:38.58#ibcon#about to read 5, iclass 6, count 0 2006.173.19:47:38.58#ibcon#read 5, iclass 6, count 0 2006.173.19:47:38.58#ibcon#about to read 6, iclass 6, count 0 2006.173.19:47:38.58#ibcon#read 6, iclass 6, count 0 2006.173.19:47:38.58#ibcon#end of sib2, iclass 6, count 0 2006.173.19:47:38.58#ibcon#*after write, iclass 6, count 0 2006.173.19:47:38.58#ibcon#*before return 0, iclass 6, count 0 2006.173.19:47:38.58#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.19:47:38.58#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.19:47:38.58#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.19:47:38.58#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.19:47:38.58$vck44/va=5,4 2006.173.19:47:38.58#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.19:47:38.58#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.19:47:38.58#ibcon#ireg 11 cls_cnt 2 2006.173.19:47:38.58#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.19:47:38.64#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.19:47:38.64#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.19:47:38.64#ibcon#enter wrdev, iclass 10, count 2 2006.173.19:47:38.64#ibcon#first serial, iclass 10, count 2 2006.173.19:47:38.64#ibcon#enter sib2, iclass 10, count 2 2006.173.19:47:38.64#ibcon#flushed, iclass 10, count 2 2006.173.19:47:38.64#ibcon#about to write, iclass 10, count 2 2006.173.19:47:38.64#ibcon#wrote, iclass 10, count 2 2006.173.19:47:38.64#ibcon#about to read 3, iclass 10, count 2 2006.173.19:47:38.66#ibcon#read 3, iclass 10, count 2 2006.173.19:47:38.66#ibcon#about to read 4, iclass 10, count 2 2006.173.19:47:38.66#ibcon#read 4, iclass 10, count 2 2006.173.19:47:38.66#ibcon#about to read 5, iclass 10, count 2 2006.173.19:47:38.66#ibcon#read 5, iclass 10, count 2 2006.173.19:47:38.66#ibcon#about to read 6, iclass 10, count 2 2006.173.19:47:38.66#ibcon#read 6, iclass 10, count 2 2006.173.19:47:38.66#ibcon#end of sib2, iclass 10, count 2 2006.173.19:47:38.66#ibcon#*mode == 0, iclass 10, count 2 2006.173.19:47:38.66#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.19:47:38.66#ibcon#[25=AT05-04\r\n] 2006.173.19:47:38.66#ibcon#*before write, iclass 10, count 2 2006.173.19:47:38.66#ibcon#enter sib2, iclass 10, count 2 2006.173.19:47:38.66#ibcon#flushed, iclass 10, count 2 2006.173.19:47:38.66#ibcon#about to write, iclass 10, count 2 2006.173.19:47:38.66#ibcon#wrote, iclass 10, count 2 2006.173.19:47:38.66#ibcon#about to read 3, iclass 10, count 2 2006.173.19:47:38.69#ibcon#read 3, iclass 10, count 2 2006.173.19:47:38.69#ibcon#about to read 4, iclass 10, count 2 2006.173.19:47:38.69#ibcon#read 4, iclass 10, count 2 2006.173.19:47:38.69#ibcon#about to read 5, iclass 10, count 2 2006.173.19:47:38.69#ibcon#read 5, iclass 10, count 2 2006.173.19:47:38.69#ibcon#about to read 6, iclass 10, count 2 2006.173.19:47:38.69#ibcon#read 6, iclass 10, count 2 2006.173.19:47:38.69#ibcon#end of sib2, iclass 10, count 2 2006.173.19:47:38.69#ibcon#*after write, iclass 10, count 2 2006.173.19:47:38.69#ibcon#*before return 0, iclass 10, count 2 2006.173.19:47:38.69#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.19:47:38.69#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.19:47:38.69#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.19:47:38.69#ibcon#ireg 7 cls_cnt 0 2006.173.19:47:38.69#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.19:47:38.81#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.19:47:38.81#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.19:47:38.81#ibcon#enter wrdev, iclass 10, count 0 2006.173.19:47:38.81#ibcon#first serial, iclass 10, count 0 2006.173.19:47:38.81#ibcon#enter sib2, iclass 10, count 0 2006.173.19:47:38.81#ibcon#flushed, iclass 10, count 0 2006.173.19:47:38.81#ibcon#about to write, iclass 10, count 0 2006.173.19:47:38.81#ibcon#wrote, iclass 10, count 0 2006.173.19:47:38.81#ibcon#about to read 3, iclass 10, count 0 2006.173.19:47:38.83#ibcon#read 3, iclass 10, count 0 2006.173.19:47:38.83#ibcon#about to read 4, iclass 10, count 0 2006.173.19:47:38.83#ibcon#read 4, iclass 10, count 0 2006.173.19:47:38.83#ibcon#about to read 5, iclass 10, count 0 2006.173.19:47:38.83#ibcon#read 5, iclass 10, count 0 2006.173.19:47:38.83#ibcon#about to read 6, iclass 10, count 0 2006.173.19:47:38.83#ibcon#read 6, iclass 10, count 0 2006.173.19:47:38.83#ibcon#end of sib2, iclass 10, count 0 2006.173.19:47:38.83#ibcon#*mode == 0, iclass 10, count 0 2006.173.19:47:38.83#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.19:47:38.83#ibcon#[25=USB\r\n] 2006.173.19:47:38.83#ibcon#*before write, iclass 10, count 0 2006.173.19:47:38.83#ibcon#enter sib2, iclass 10, count 0 2006.173.19:47:38.83#ibcon#flushed, iclass 10, count 0 2006.173.19:47:38.83#ibcon#about to write, iclass 10, count 0 2006.173.19:47:38.83#ibcon#wrote, iclass 10, count 0 2006.173.19:47:38.83#ibcon#about to read 3, iclass 10, count 0 2006.173.19:47:38.86#ibcon#read 3, iclass 10, count 0 2006.173.19:47:38.86#ibcon#about to read 4, iclass 10, count 0 2006.173.19:47:38.86#ibcon#read 4, iclass 10, count 0 2006.173.19:47:38.86#ibcon#about to read 5, iclass 10, count 0 2006.173.19:47:38.86#ibcon#read 5, iclass 10, count 0 2006.173.19:47:38.86#ibcon#about to read 6, iclass 10, count 0 2006.173.19:47:38.86#ibcon#read 6, iclass 10, count 0 2006.173.19:47:38.86#ibcon#end of sib2, iclass 10, count 0 2006.173.19:47:38.86#ibcon#*after write, iclass 10, count 0 2006.173.19:47:38.86#ibcon#*before return 0, iclass 10, count 0 2006.173.19:47:38.86#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.19:47:38.86#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.19:47:38.86#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.19:47:38.86#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.19:47:38.86$vck44/valo=6,814.99 2006.173.19:47:38.86#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.19:47:38.86#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.19:47:38.86#ibcon#ireg 17 cls_cnt 0 2006.173.19:47:38.86#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.19:47:38.86#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.19:47:38.86#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.19:47:38.86#ibcon#enter wrdev, iclass 12, count 0 2006.173.19:47:38.86#ibcon#first serial, iclass 12, count 0 2006.173.19:47:38.86#ibcon#enter sib2, iclass 12, count 0 2006.173.19:47:38.86#ibcon#flushed, iclass 12, count 0 2006.173.19:47:38.86#ibcon#about to write, iclass 12, count 0 2006.173.19:47:38.86#ibcon#wrote, iclass 12, count 0 2006.173.19:47:38.86#ibcon#about to read 3, iclass 12, count 0 2006.173.19:47:38.88#ibcon#read 3, iclass 12, count 0 2006.173.19:47:38.88#ibcon#about to read 4, iclass 12, count 0 2006.173.19:47:38.88#ibcon#read 4, iclass 12, count 0 2006.173.19:47:38.88#ibcon#about to read 5, iclass 12, count 0 2006.173.19:47:38.88#ibcon#read 5, iclass 12, count 0 2006.173.19:47:38.88#ibcon#about to read 6, iclass 12, count 0 2006.173.19:47:38.88#ibcon#read 6, iclass 12, count 0 2006.173.19:47:38.88#ibcon#end of sib2, iclass 12, count 0 2006.173.19:47:38.88#ibcon#*mode == 0, iclass 12, count 0 2006.173.19:47:38.88#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.19:47:38.88#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.19:47:38.88#ibcon#*before write, iclass 12, count 0 2006.173.19:47:38.88#ibcon#enter sib2, iclass 12, count 0 2006.173.19:47:38.88#ibcon#flushed, iclass 12, count 0 2006.173.19:47:38.88#ibcon#about to write, iclass 12, count 0 2006.173.19:47:38.88#ibcon#wrote, iclass 12, count 0 2006.173.19:47:38.88#ibcon#about to read 3, iclass 12, count 0 2006.173.19:47:38.92#ibcon#read 3, iclass 12, count 0 2006.173.19:47:38.92#ibcon#about to read 4, iclass 12, count 0 2006.173.19:47:38.92#ibcon#read 4, iclass 12, count 0 2006.173.19:47:38.92#ibcon#about to read 5, iclass 12, count 0 2006.173.19:47:38.92#ibcon#read 5, iclass 12, count 0 2006.173.19:47:38.92#ibcon#about to read 6, iclass 12, count 0 2006.173.19:47:38.92#ibcon#read 6, iclass 12, count 0 2006.173.19:47:38.92#ibcon#end of sib2, iclass 12, count 0 2006.173.19:47:38.92#ibcon#*after write, iclass 12, count 0 2006.173.19:47:38.92#ibcon#*before return 0, iclass 12, count 0 2006.173.19:47:38.92#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.19:47:38.92#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.19:47:38.92#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.19:47:38.92#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.19:47:38.92$vck44/va=6,3 2006.173.19:47:38.92#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.19:47:38.92#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.19:47:38.92#ibcon#ireg 11 cls_cnt 2 2006.173.19:47:38.92#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.19:47:38.98#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.19:47:38.98#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.19:47:38.98#ibcon#enter wrdev, iclass 14, count 2 2006.173.19:47:38.98#ibcon#first serial, iclass 14, count 2 2006.173.19:47:38.98#ibcon#enter sib2, iclass 14, count 2 2006.173.19:47:38.98#ibcon#flushed, iclass 14, count 2 2006.173.19:47:38.98#ibcon#about to write, iclass 14, count 2 2006.173.19:47:38.98#ibcon#wrote, iclass 14, count 2 2006.173.19:47:38.98#ibcon#about to read 3, iclass 14, count 2 2006.173.19:47:39.00#ibcon#read 3, iclass 14, count 2 2006.173.19:47:39.00#ibcon#about to read 4, iclass 14, count 2 2006.173.19:47:39.00#ibcon#read 4, iclass 14, count 2 2006.173.19:47:39.00#ibcon#about to read 5, iclass 14, count 2 2006.173.19:47:39.00#ibcon#read 5, iclass 14, count 2 2006.173.19:47:39.00#ibcon#about to read 6, iclass 14, count 2 2006.173.19:47:39.00#ibcon#read 6, iclass 14, count 2 2006.173.19:47:39.00#ibcon#end of sib2, iclass 14, count 2 2006.173.19:47:39.00#ibcon#*mode == 0, iclass 14, count 2 2006.173.19:47:39.00#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.19:47:39.00#ibcon#[25=AT06-03\r\n] 2006.173.19:47:39.00#ibcon#*before write, iclass 14, count 2 2006.173.19:47:39.00#ibcon#enter sib2, iclass 14, count 2 2006.173.19:47:39.00#ibcon#flushed, iclass 14, count 2 2006.173.19:47:39.00#ibcon#about to write, iclass 14, count 2 2006.173.19:47:39.00#ibcon#wrote, iclass 14, count 2 2006.173.19:47:39.00#ibcon#about to read 3, iclass 14, count 2 2006.173.19:47:39.03#ibcon#read 3, iclass 14, count 2 2006.173.19:47:39.03#ibcon#about to read 4, iclass 14, count 2 2006.173.19:47:39.03#ibcon#read 4, iclass 14, count 2 2006.173.19:47:39.03#ibcon#about to read 5, iclass 14, count 2 2006.173.19:47:39.03#ibcon#read 5, iclass 14, count 2 2006.173.19:47:39.03#ibcon#about to read 6, iclass 14, count 2 2006.173.19:47:39.03#ibcon#read 6, iclass 14, count 2 2006.173.19:47:39.03#ibcon#end of sib2, iclass 14, count 2 2006.173.19:47:39.03#ibcon#*after write, iclass 14, count 2 2006.173.19:47:39.03#ibcon#*before return 0, iclass 14, count 2 2006.173.19:47:39.03#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.19:47:39.03#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.19:47:39.03#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.19:47:39.03#ibcon#ireg 7 cls_cnt 0 2006.173.19:47:39.03#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.19:47:39.15#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.19:47:39.15#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.19:47:39.15#ibcon#enter wrdev, iclass 14, count 0 2006.173.19:47:39.15#ibcon#first serial, iclass 14, count 0 2006.173.19:47:39.15#ibcon#enter sib2, iclass 14, count 0 2006.173.19:47:39.15#ibcon#flushed, iclass 14, count 0 2006.173.19:47:39.15#ibcon#about to write, iclass 14, count 0 2006.173.19:47:39.15#ibcon#wrote, iclass 14, count 0 2006.173.19:47:39.15#ibcon#about to read 3, iclass 14, count 0 2006.173.19:47:39.17#ibcon#read 3, iclass 14, count 0 2006.173.19:47:39.17#ibcon#about to read 4, iclass 14, count 0 2006.173.19:47:39.17#ibcon#read 4, iclass 14, count 0 2006.173.19:47:39.17#ibcon#about to read 5, iclass 14, count 0 2006.173.19:47:39.17#ibcon#read 5, iclass 14, count 0 2006.173.19:47:39.17#ibcon#about to read 6, iclass 14, count 0 2006.173.19:47:39.17#ibcon#read 6, iclass 14, count 0 2006.173.19:47:39.17#ibcon#end of sib2, iclass 14, count 0 2006.173.19:47:39.17#ibcon#*mode == 0, iclass 14, count 0 2006.173.19:47:39.17#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.19:47:39.17#ibcon#[25=USB\r\n] 2006.173.19:47:39.17#ibcon#*before write, iclass 14, count 0 2006.173.19:47:39.17#ibcon#enter sib2, iclass 14, count 0 2006.173.19:47:39.17#ibcon#flushed, iclass 14, count 0 2006.173.19:47:39.17#ibcon#about to write, iclass 14, count 0 2006.173.19:47:39.17#ibcon#wrote, iclass 14, count 0 2006.173.19:47:39.17#ibcon#about to read 3, iclass 14, count 0 2006.173.19:47:39.20#ibcon#read 3, iclass 14, count 0 2006.173.19:47:39.20#ibcon#about to read 4, iclass 14, count 0 2006.173.19:47:39.20#ibcon#read 4, iclass 14, count 0 2006.173.19:47:39.20#ibcon#about to read 5, iclass 14, count 0 2006.173.19:47:39.20#ibcon#read 5, iclass 14, count 0 2006.173.19:47:39.20#ibcon#about to read 6, iclass 14, count 0 2006.173.19:47:39.20#ibcon#read 6, iclass 14, count 0 2006.173.19:47:39.20#ibcon#end of sib2, iclass 14, count 0 2006.173.19:47:39.20#ibcon#*after write, iclass 14, count 0 2006.173.19:47:39.20#ibcon#*before return 0, iclass 14, count 0 2006.173.19:47:39.20#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.19:47:39.20#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.19:47:39.20#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.19:47:39.20#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.19:47:39.20$vck44/valo=7,864.99 2006.173.19:47:39.20#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.19:47:39.20#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.19:47:39.20#ibcon#ireg 17 cls_cnt 0 2006.173.19:47:39.20#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.19:47:39.20#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.19:47:39.20#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.19:47:39.20#ibcon#enter wrdev, iclass 16, count 0 2006.173.19:47:39.20#ibcon#first serial, iclass 16, count 0 2006.173.19:47:39.20#ibcon#enter sib2, iclass 16, count 0 2006.173.19:47:39.20#ibcon#flushed, iclass 16, count 0 2006.173.19:47:39.20#ibcon#about to write, iclass 16, count 0 2006.173.19:47:39.20#ibcon#wrote, iclass 16, count 0 2006.173.19:47:39.20#ibcon#about to read 3, iclass 16, count 0 2006.173.19:47:39.22#ibcon#read 3, iclass 16, count 0 2006.173.19:47:39.22#ibcon#about to read 4, iclass 16, count 0 2006.173.19:47:39.22#ibcon#read 4, iclass 16, count 0 2006.173.19:47:39.22#ibcon#about to read 5, iclass 16, count 0 2006.173.19:47:39.22#ibcon#read 5, iclass 16, count 0 2006.173.19:47:39.22#ibcon#about to read 6, iclass 16, count 0 2006.173.19:47:39.22#ibcon#read 6, iclass 16, count 0 2006.173.19:47:39.22#ibcon#end of sib2, iclass 16, count 0 2006.173.19:47:39.22#ibcon#*mode == 0, iclass 16, count 0 2006.173.19:47:39.22#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.19:47:39.22#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.19:47:39.22#ibcon#*before write, iclass 16, count 0 2006.173.19:47:39.22#ibcon#enter sib2, iclass 16, count 0 2006.173.19:47:39.22#ibcon#flushed, iclass 16, count 0 2006.173.19:47:39.22#ibcon#about to write, iclass 16, count 0 2006.173.19:47:39.22#ibcon#wrote, iclass 16, count 0 2006.173.19:47:39.22#ibcon#about to read 3, iclass 16, count 0 2006.173.19:47:39.26#ibcon#read 3, iclass 16, count 0 2006.173.19:47:39.26#ibcon#about to read 4, iclass 16, count 0 2006.173.19:47:39.26#ibcon#read 4, iclass 16, count 0 2006.173.19:47:39.26#ibcon#about to read 5, iclass 16, count 0 2006.173.19:47:39.26#ibcon#read 5, iclass 16, count 0 2006.173.19:47:39.26#ibcon#about to read 6, iclass 16, count 0 2006.173.19:47:39.26#ibcon#read 6, iclass 16, count 0 2006.173.19:47:39.26#ibcon#end of sib2, iclass 16, count 0 2006.173.19:47:39.26#ibcon#*after write, iclass 16, count 0 2006.173.19:47:39.26#ibcon#*before return 0, iclass 16, count 0 2006.173.19:47:39.26#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.19:47:39.26#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.19:47:39.26#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.19:47:39.26#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.19:47:39.26$vck44/va=7,4 2006.173.19:47:39.26#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.19:47:39.26#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.19:47:39.26#ibcon#ireg 11 cls_cnt 2 2006.173.19:47:39.26#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.19:47:39.32#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.19:47:39.32#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.19:47:39.32#ibcon#enter wrdev, iclass 18, count 2 2006.173.19:47:39.32#ibcon#first serial, iclass 18, count 2 2006.173.19:47:39.32#ibcon#enter sib2, iclass 18, count 2 2006.173.19:47:39.32#ibcon#flushed, iclass 18, count 2 2006.173.19:47:39.32#ibcon#about to write, iclass 18, count 2 2006.173.19:47:39.32#ibcon#wrote, iclass 18, count 2 2006.173.19:47:39.32#ibcon#about to read 3, iclass 18, count 2 2006.173.19:47:39.34#ibcon#read 3, iclass 18, count 2 2006.173.19:47:39.34#ibcon#about to read 4, iclass 18, count 2 2006.173.19:47:39.34#ibcon#read 4, iclass 18, count 2 2006.173.19:47:39.34#ibcon#about to read 5, iclass 18, count 2 2006.173.19:47:39.34#ibcon#read 5, iclass 18, count 2 2006.173.19:47:39.34#ibcon#about to read 6, iclass 18, count 2 2006.173.19:47:39.34#ibcon#read 6, iclass 18, count 2 2006.173.19:47:39.34#ibcon#end of sib2, iclass 18, count 2 2006.173.19:47:39.34#ibcon#*mode == 0, iclass 18, count 2 2006.173.19:47:39.34#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.19:47:39.34#ibcon#[25=AT07-04\r\n] 2006.173.19:47:39.34#ibcon#*before write, iclass 18, count 2 2006.173.19:47:39.34#ibcon#enter sib2, iclass 18, count 2 2006.173.19:47:39.34#ibcon#flushed, iclass 18, count 2 2006.173.19:47:39.34#ibcon#about to write, iclass 18, count 2 2006.173.19:47:39.34#ibcon#wrote, iclass 18, count 2 2006.173.19:47:39.34#ibcon#about to read 3, iclass 18, count 2 2006.173.19:47:39.37#ibcon#read 3, iclass 18, count 2 2006.173.19:47:39.37#ibcon#about to read 4, iclass 18, count 2 2006.173.19:47:39.37#ibcon#read 4, iclass 18, count 2 2006.173.19:47:39.37#ibcon#about to read 5, iclass 18, count 2 2006.173.19:47:39.37#ibcon#read 5, iclass 18, count 2 2006.173.19:47:39.37#ibcon#about to read 6, iclass 18, count 2 2006.173.19:47:39.37#ibcon#read 6, iclass 18, count 2 2006.173.19:47:39.37#ibcon#end of sib2, iclass 18, count 2 2006.173.19:47:39.37#ibcon#*after write, iclass 18, count 2 2006.173.19:47:39.37#ibcon#*before return 0, iclass 18, count 2 2006.173.19:47:39.37#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.19:47:39.37#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.19:47:39.37#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.19:47:39.37#ibcon#ireg 7 cls_cnt 0 2006.173.19:47:39.37#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.19:47:39.49#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.19:47:39.49#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.19:47:39.49#ibcon#enter wrdev, iclass 18, count 0 2006.173.19:47:39.49#ibcon#first serial, iclass 18, count 0 2006.173.19:47:39.49#ibcon#enter sib2, iclass 18, count 0 2006.173.19:47:39.49#ibcon#flushed, iclass 18, count 0 2006.173.19:47:39.49#ibcon#about to write, iclass 18, count 0 2006.173.19:47:39.49#ibcon#wrote, iclass 18, count 0 2006.173.19:47:39.49#ibcon#about to read 3, iclass 18, count 0 2006.173.19:47:39.51#ibcon#read 3, iclass 18, count 0 2006.173.19:47:39.51#ibcon#about to read 4, iclass 18, count 0 2006.173.19:47:39.51#ibcon#read 4, iclass 18, count 0 2006.173.19:47:39.51#ibcon#about to read 5, iclass 18, count 0 2006.173.19:47:39.51#ibcon#read 5, iclass 18, count 0 2006.173.19:47:39.51#ibcon#about to read 6, iclass 18, count 0 2006.173.19:47:39.51#ibcon#read 6, iclass 18, count 0 2006.173.19:47:39.51#ibcon#end of sib2, iclass 18, count 0 2006.173.19:47:39.51#ibcon#*mode == 0, iclass 18, count 0 2006.173.19:47:39.51#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.19:47:39.51#ibcon#[25=USB\r\n] 2006.173.19:47:39.51#ibcon#*before write, iclass 18, count 0 2006.173.19:47:39.51#ibcon#enter sib2, iclass 18, count 0 2006.173.19:47:39.51#ibcon#flushed, iclass 18, count 0 2006.173.19:47:39.51#ibcon#about to write, iclass 18, count 0 2006.173.19:47:39.51#ibcon#wrote, iclass 18, count 0 2006.173.19:47:39.51#ibcon#about to read 3, iclass 18, count 0 2006.173.19:47:39.54#ibcon#read 3, iclass 18, count 0 2006.173.19:47:39.54#ibcon#about to read 4, iclass 18, count 0 2006.173.19:47:39.54#ibcon#read 4, iclass 18, count 0 2006.173.19:47:39.54#ibcon#about to read 5, iclass 18, count 0 2006.173.19:47:39.54#ibcon#read 5, iclass 18, count 0 2006.173.19:47:39.54#ibcon#about to read 6, iclass 18, count 0 2006.173.19:47:39.54#ibcon#read 6, iclass 18, count 0 2006.173.19:47:39.54#ibcon#end of sib2, iclass 18, count 0 2006.173.19:47:39.54#ibcon#*after write, iclass 18, count 0 2006.173.19:47:39.54#ibcon#*before return 0, iclass 18, count 0 2006.173.19:47:39.54#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.19:47:39.54#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.19:47:39.54#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.19:47:39.54#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.19:47:39.54$vck44/valo=8,884.99 2006.173.19:47:39.54#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.19:47:39.54#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.19:47:39.54#ibcon#ireg 17 cls_cnt 0 2006.173.19:47:39.54#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.19:47:39.54#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.19:47:39.54#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.19:47:39.54#ibcon#enter wrdev, iclass 20, count 0 2006.173.19:47:39.54#ibcon#first serial, iclass 20, count 0 2006.173.19:47:39.54#ibcon#enter sib2, iclass 20, count 0 2006.173.19:47:39.54#ibcon#flushed, iclass 20, count 0 2006.173.19:47:39.54#ibcon#about to write, iclass 20, count 0 2006.173.19:47:39.54#ibcon#wrote, iclass 20, count 0 2006.173.19:47:39.54#ibcon#about to read 3, iclass 20, count 0 2006.173.19:47:39.56#ibcon#read 3, iclass 20, count 0 2006.173.19:47:39.56#ibcon#about to read 4, iclass 20, count 0 2006.173.19:47:39.56#ibcon#read 4, iclass 20, count 0 2006.173.19:47:39.56#ibcon#about to read 5, iclass 20, count 0 2006.173.19:47:39.56#ibcon#read 5, iclass 20, count 0 2006.173.19:47:39.56#ibcon#about to read 6, iclass 20, count 0 2006.173.19:47:39.56#ibcon#read 6, iclass 20, count 0 2006.173.19:47:39.56#ibcon#end of sib2, iclass 20, count 0 2006.173.19:47:39.56#ibcon#*mode == 0, iclass 20, count 0 2006.173.19:47:39.56#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.19:47:39.56#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.19:47:39.56#ibcon#*before write, iclass 20, count 0 2006.173.19:47:39.56#ibcon#enter sib2, iclass 20, count 0 2006.173.19:47:39.56#ibcon#flushed, iclass 20, count 0 2006.173.19:47:39.56#ibcon#about to write, iclass 20, count 0 2006.173.19:47:39.56#ibcon#wrote, iclass 20, count 0 2006.173.19:47:39.56#ibcon#about to read 3, iclass 20, count 0 2006.173.19:47:39.60#ibcon#read 3, iclass 20, count 0 2006.173.19:47:39.60#ibcon#about to read 4, iclass 20, count 0 2006.173.19:47:39.60#ibcon#read 4, iclass 20, count 0 2006.173.19:47:39.60#ibcon#about to read 5, iclass 20, count 0 2006.173.19:47:39.60#ibcon#read 5, iclass 20, count 0 2006.173.19:47:39.60#ibcon#about to read 6, iclass 20, count 0 2006.173.19:47:39.60#ibcon#read 6, iclass 20, count 0 2006.173.19:47:39.60#ibcon#end of sib2, iclass 20, count 0 2006.173.19:47:39.60#ibcon#*after write, iclass 20, count 0 2006.173.19:47:39.60#ibcon#*before return 0, iclass 20, count 0 2006.173.19:47:39.60#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.19:47:39.60#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.19:47:39.60#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.19:47:39.60#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.19:47:39.60$vck44/va=8,4 2006.173.19:47:39.60#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.19:47:39.60#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.19:47:39.60#ibcon#ireg 11 cls_cnt 2 2006.173.19:47:39.60#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.19:47:39.66#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.19:47:39.66#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.19:47:39.66#ibcon#enter wrdev, iclass 22, count 2 2006.173.19:47:39.66#ibcon#first serial, iclass 22, count 2 2006.173.19:47:39.66#ibcon#enter sib2, iclass 22, count 2 2006.173.19:47:39.66#ibcon#flushed, iclass 22, count 2 2006.173.19:47:39.66#ibcon#about to write, iclass 22, count 2 2006.173.19:47:39.66#ibcon#wrote, iclass 22, count 2 2006.173.19:47:39.66#ibcon#about to read 3, iclass 22, count 2 2006.173.19:47:39.68#ibcon#read 3, iclass 22, count 2 2006.173.19:47:39.68#ibcon#about to read 4, iclass 22, count 2 2006.173.19:47:39.68#ibcon#read 4, iclass 22, count 2 2006.173.19:47:39.68#ibcon#about to read 5, iclass 22, count 2 2006.173.19:47:39.68#ibcon#read 5, iclass 22, count 2 2006.173.19:47:39.68#ibcon#about to read 6, iclass 22, count 2 2006.173.19:47:39.68#ibcon#read 6, iclass 22, count 2 2006.173.19:47:39.68#ibcon#end of sib2, iclass 22, count 2 2006.173.19:47:39.68#ibcon#*mode == 0, iclass 22, count 2 2006.173.19:47:39.68#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.19:47:39.68#ibcon#[25=AT08-04\r\n] 2006.173.19:47:39.68#ibcon#*before write, iclass 22, count 2 2006.173.19:47:39.68#ibcon#enter sib2, iclass 22, count 2 2006.173.19:47:39.68#ibcon#flushed, iclass 22, count 2 2006.173.19:47:39.68#ibcon#about to write, iclass 22, count 2 2006.173.19:47:39.68#ibcon#wrote, iclass 22, count 2 2006.173.19:47:39.68#ibcon#about to read 3, iclass 22, count 2 2006.173.19:47:39.71#ibcon#read 3, iclass 22, count 2 2006.173.19:47:39.71#ibcon#about to read 4, iclass 22, count 2 2006.173.19:47:39.71#ibcon#read 4, iclass 22, count 2 2006.173.19:47:39.71#ibcon#about to read 5, iclass 22, count 2 2006.173.19:47:39.71#ibcon#read 5, iclass 22, count 2 2006.173.19:47:39.71#ibcon#about to read 6, iclass 22, count 2 2006.173.19:47:39.71#ibcon#read 6, iclass 22, count 2 2006.173.19:47:39.71#ibcon#end of sib2, iclass 22, count 2 2006.173.19:47:39.71#ibcon#*after write, iclass 22, count 2 2006.173.19:47:39.71#ibcon#*before return 0, iclass 22, count 2 2006.173.19:47:39.71#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.19:47:39.71#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.19:47:39.71#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.19:47:39.71#ibcon#ireg 7 cls_cnt 0 2006.173.19:47:39.71#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.19:47:39.83#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.19:47:39.83#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.19:47:39.83#ibcon#enter wrdev, iclass 22, count 0 2006.173.19:47:39.83#ibcon#first serial, iclass 22, count 0 2006.173.19:47:39.83#ibcon#enter sib2, iclass 22, count 0 2006.173.19:47:39.83#ibcon#flushed, iclass 22, count 0 2006.173.19:47:39.83#ibcon#about to write, iclass 22, count 0 2006.173.19:47:39.83#ibcon#wrote, iclass 22, count 0 2006.173.19:47:39.83#ibcon#about to read 3, iclass 22, count 0 2006.173.19:47:39.85#ibcon#read 3, iclass 22, count 0 2006.173.19:47:39.85#ibcon#about to read 4, iclass 22, count 0 2006.173.19:47:39.85#ibcon#read 4, iclass 22, count 0 2006.173.19:47:39.85#ibcon#about to read 5, iclass 22, count 0 2006.173.19:47:39.85#ibcon#read 5, iclass 22, count 0 2006.173.19:47:39.85#ibcon#about to read 6, iclass 22, count 0 2006.173.19:47:39.85#ibcon#read 6, iclass 22, count 0 2006.173.19:47:39.85#ibcon#end of sib2, iclass 22, count 0 2006.173.19:47:39.85#ibcon#*mode == 0, iclass 22, count 0 2006.173.19:47:39.85#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.19:47:39.85#ibcon#[25=USB\r\n] 2006.173.19:47:39.85#ibcon#*before write, iclass 22, count 0 2006.173.19:47:39.85#ibcon#enter sib2, iclass 22, count 0 2006.173.19:47:39.85#ibcon#flushed, iclass 22, count 0 2006.173.19:47:39.85#ibcon#about to write, iclass 22, count 0 2006.173.19:47:39.85#ibcon#wrote, iclass 22, count 0 2006.173.19:47:39.85#ibcon#about to read 3, iclass 22, count 0 2006.173.19:47:39.88#ibcon#read 3, iclass 22, count 0 2006.173.19:47:39.88#ibcon#about to read 4, iclass 22, count 0 2006.173.19:47:39.88#ibcon#read 4, iclass 22, count 0 2006.173.19:47:39.88#ibcon#about to read 5, iclass 22, count 0 2006.173.19:47:39.88#ibcon#read 5, iclass 22, count 0 2006.173.19:47:39.88#ibcon#about to read 6, iclass 22, count 0 2006.173.19:47:39.88#ibcon#read 6, iclass 22, count 0 2006.173.19:47:39.88#ibcon#end of sib2, iclass 22, count 0 2006.173.19:47:39.88#ibcon#*after write, iclass 22, count 0 2006.173.19:47:39.88#ibcon#*before return 0, iclass 22, count 0 2006.173.19:47:39.88#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.19:47:39.88#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.19:47:39.88#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.19:47:39.88#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.19:47:39.88$vck44/vblo=1,629.99 2006.173.19:47:39.88#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.19:47:39.88#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.19:47:39.88#ibcon#ireg 17 cls_cnt 0 2006.173.19:47:39.88#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.19:47:39.88#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.19:47:39.88#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.19:47:39.88#ibcon#enter wrdev, iclass 24, count 0 2006.173.19:47:39.88#ibcon#first serial, iclass 24, count 0 2006.173.19:47:39.88#ibcon#enter sib2, iclass 24, count 0 2006.173.19:47:39.88#ibcon#flushed, iclass 24, count 0 2006.173.19:47:39.88#ibcon#about to write, iclass 24, count 0 2006.173.19:47:39.88#ibcon#wrote, iclass 24, count 0 2006.173.19:47:39.88#ibcon#about to read 3, iclass 24, count 0 2006.173.19:47:39.90#ibcon#read 3, iclass 24, count 0 2006.173.19:47:39.90#ibcon#about to read 4, iclass 24, count 0 2006.173.19:47:39.90#ibcon#read 4, iclass 24, count 0 2006.173.19:47:39.90#ibcon#about to read 5, iclass 24, count 0 2006.173.19:47:39.90#ibcon#read 5, iclass 24, count 0 2006.173.19:47:39.90#ibcon#about to read 6, iclass 24, count 0 2006.173.19:47:39.90#ibcon#read 6, iclass 24, count 0 2006.173.19:47:39.90#ibcon#end of sib2, iclass 24, count 0 2006.173.19:47:39.90#ibcon#*mode == 0, iclass 24, count 0 2006.173.19:47:39.90#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.19:47:39.90#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.19:47:39.90#ibcon#*before write, iclass 24, count 0 2006.173.19:47:39.90#ibcon#enter sib2, iclass 24, count 0 2006.173.19:47:39.90#ibcon#flushed, iclass 24, count 0 2006.173.19:47:39.90#ibcon#about to write, iclass 24, count 0 2006.173.19:47:39.90#ibcon#wrote, iclass 24, count 0 2006.173.19:47:39.90#ibcon#about to read 3, iclass 24, count 0 2006.173.19:47:39.94#ibcon#read 3, iclass 24, count 0 2006.173.19:47:39.94#ibcon#about to read 4, iclass 24, count 0 2006.173.19:47:39.94#ibcon#read 4, iclass 24, count 0 2006.173.19:47:39.94#ibcon#about to read 5, iclass 24, count 0 2006.173.19:47:39.94#ibcon#read 5, iclass 24, count 0 2006.173.19:47:39.94#ibcon#about to read 6, iclass 24, count 0 2006.173.19:47:39.94#ibcon#read 6, iclass 24, count 0 2006.173.19:47:39.94#ibcon#end of sib2, iclass 24, count 0 2006.173.19:47:39.94#ibcon#*after write, iclass 24, count 0 2006.173.19:47:39.94#ibcon#*before return 0, iclass 24, count 0 2006.173.19:47:39.94#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.19:47:39.94#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.19:47:39.94#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.19:47:39.94#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.19:47:39.94$vck44/vb=1,4 2006.173.19:47:39.94#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.19:47:39.94#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.19:47:39.94#ibcon#ireg 11 cls_cnt 2 2006.173.19:47:39.94#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.19:47:39.94#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.19:47:39.94#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.19:47:39.94#ibcon#enter wrdev, iclass 26, count 2 2006.173.19:47:39.94#ibcon#first serial, iclass 26, count 2 2006.173.19:47:39.94#ibcon#enter sib2, iclass 26, count 2 2006.173.19:47:39.94#ibcon#flushed, iclass 26, count 2 2006.173.19:47:39.94#ibcon#about to write, iclass 26, count 2 2006.173.19:47:39.94#ibcon#wrote, iclass 26, count 2 2006.173.19:47:39.94#ibcon#about to read 3, iclass 26, count 2 2006.173.19:47:39.96#ibcon#read 3, iclass 26, count 2 2006.173.19:47:39.96#ibcon#about to read 4, iclass 26, count 2 2006.173.19:47:39.96#ibcon#read 4, iclass 26, count 2 2006.173.19:47:39.96#ibcon#about to read 5, iclass 26, count 2 2006.173.19:47:39.96#ibcon#read 5, iclass 26, count 2 2006.173.19:47:39.96#ibcon#about to read 6, iclass 26, count 2 2006.173.19:47:39.96#ibcon#read 6, iclass 26, count 2 2006.173.19:47:39.96#ibcon#end of sib2, iclass 26, count 2 2006.173.19:47:39.96#ibcon#*mode == 0, iclass 26, count 2 2006.173.19:47:39.96#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.19:47:39.96#ibcon#[27=AT01-04\r\n] 2006.173.19:47:39.96#ibcon#*before write, iclass 26, count 2 2006.173.19:47:39.96#ibcon#enter sib2, iclass 26, count 2 2006.173.19:47:39.96#ibcon#flushed, iclass 26, count 2 2006.173.19:47:39.96#ibcon#about to write, iclass 26, count 2 2006.173.19:47:39.96#ibcon#wrote, iclass 26, count 2 2006.173.19:47:39.96#ibcon#about to read 3, iclass 26, count 2 2006.173.19:47:39.99#ibcon#read 3, iclass 26, count 2 2006.173.19:47:39.99#ibcon#about to read 4, iclass 26, count 2 2006.173.19:47:39.99#ibcon#read 4, iclass 26, count 2 2006.173.19:47:39.99#ibcon#about to read 5, iclass 26, count 2 2006.173.19:47:39.99#ibcon#read 5, iclass 26, count 2 2006.173.19:47:39.99#ibcon#about to read 6, iclass 26, count 2 2006.173.19:47:39.99#ibcon#read 6, iclass 26, count 2 2006.173.19:47:39.99#ibcon#end of sib2, iclass 26, count 2 2006.173.19:47:39.99#ibcon#*after write, iclass 26, count 2 2006.173.19:47:39.99#ibcon#*before return 0, iclass 26, count 2 2006.173.19:47:39.99#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.19:47:39.99#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.19:47:39.99#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.19:47:39.99#ibcon#ireg 7 cls_cnt 0 2006.173.19:47:39.99#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.19:47:40.11#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.19:47:40.11#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.19:47:40.11#ibcon#enter wrdev, iclass 26, count 0 2006.173.19:47:40.11#ibcon#first serial, iclass 26, count 0 2006.173.19:47:40.11#ibcon#enter sib2, iclass 26, count 0 2006.173.19:47:40.11#ibcon#flushed, iclass 26, count 0 2006.173.19:47:40.11#ibcon#about to write, iclass 26, count 0 2006.173.19:47:40.11#ibcon#wrote, iclass 26, count 0 2006.173.19:47:40.11#ibcon#about to read 3, iclass 26, count 0 2006.173.19:47:40.13#ibcon#read 3, iclass 26, count 0 2006.173.19:47:40.13#ibcon#about to read 4, iclass 26, count 0 2006.173.19:47:40.13#ibcon#read 4, iclass 26, count 0 2006.173.19:47:40.13#ibcon#about to read 5, iclass 26, count 0 2006.173.19:47:40.13#ibcon#read 5, iclass 26, count 0 2006.173.19:47:40.13#ibcon#about to read 6, iclass 26, count 0 2006.173.19:47:40.13#ibcon#read 6, iclass 26, count 0 2006.173.19:47:40.13#ibcon#end of sib2, iclass 26, count 0 2006.173.19:47:40.13#ibcon#*mode == 0, iclass 26, count 0 2006.173.19:47:40.13#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.19:47:40.13#ibcon#[27=USB\r\n] 2006.173.19:47:40.13#ibcon#*before write, iclass 26, count 0 2006.173.19:47:40.13#ibcon#enter sib2, iclass 26, count 0 2006.173.19:47:40.13#ibcon#flushed, iclass 26, count 0 2006.173.19:47:40.13#ibcon#about to write, iclass 26, count 0 2006.173.19:47:40.13#ibcon#wrote, iclass 26, count 0 2006.173.19:47:40.13#ibcon#about to read 3, iclass 26, count 0 2006.173.19:47:40.16#ibcon#read 3, iclass 26, count 0 2006.173.19:47:40.16#ibcon#about to read 4, iclass 26, count 0 2006.173.19:47:40.16#ibcon#read 4, iclass 26, count 0 2006.173.19:47:40.16#ibcon#about to read 5, iclass 26, count 0 2006.173.19:47:40.16#ibcon#read 5, iclass 26, count 0 2006.173.19:47:40.16#ibcon#about to read 6, iclass 26, count 0 2006.173.19:47:40.16#ibcon#read 6, iclass 26, count 0 2006.173.19:47:40.16#ibcon#end of sib2, iclass 26, count 0 2006.173.19:47:40.16#ibcon#*after write, iclass 26, count 0 2006.173.19:47:40.16#ibcon#*before return 0, iclass 26, count 0 2006.173.19:47:40.16#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.19:47:40.16#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.19:47:40.16#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.19:47:40.16#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.19:47:40.16$vck44/vblo=2,634.99 2006.173.19:47:40.16#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.19:47:40.16#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.19:47:40.16#ibcon#ireg 17 cls_cnt 0 2006.173.19:47:40.16#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.19:47:40.16#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.19:47:40.16#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.19:47:40.16#ibcon#enter wrdev, iclass 28, count 0 2006.173.19:47:40.16#ibcon#first serial, iclass 28, count 0 2006.173.19:47:40.16#ibcon#enter sib2, iclass 28, count 0 2006.173.19:47:40.16#ibcon#flushed, iclass 28, count 0 2006.173.19:47:40.16#ibcon#about to write, iclass 28, count 0 2006.173.19:47:40.16#ibcon#wrote, iclass 28, count 0 2006.173.19:47:40.16#ibcon#about to read 3, iclass 28, count 0 2006.173.19:47:40.18#ibcon#read 3, iclass 28, count 0 2006.173.19:47:40.18#ibcon#about to read 4, iclass 28, count 0 2006.173.19:47:40.18#ibcon#read 4, iclass 28, count 0 2006.173.19:47:40.18#ibcon#about to read 5, iclass 28, count 0 2006.173.19:47:40.18#ibcon#read 5, iclass 28, count 0 2006.173.19:47:40.18#ibcon#about to read 6, iclass 28, count 0 2006.173.19:47:40.18#ibcon#read 6, iclass 28, count 0 2006.173.19:47:40.18#ibcon#end of sib2, iclass 28, count 0 2006.173.19:47:40.18#ibcon#*mode == 0, iclass 28, count 0 2006.173.19:47:40.18#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.19:47:40.18#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.19:47:40.18#ibcon#*before write, iclass 28, count 0 2006.173.19:47:40.18#ibcon#enter sib2, iclass 28, count 0 2006.173.19:47:40.18#ibcon#flushed, iclass 28, count 0 2006.173.19:47:40.18#ibcon#about to write, iclass 28, count 0 2006.173.19:47:40.18#ibcon#wrote, iclass 28, count 0 2006.173.19:47:40.18#ibcon#about to read 3, iclass 28, count 0 2006.173.19:47:40.22#ibcon#read 3, iclass 28, count 0 2006.173.19:47:40.22#ibcon#about to read 4, iclass 28, count 0 2006.173.19:47:40.22#ibcon#read 4, iclass 28, count 0 2006.173.19:47:40.22#ibcon#about to read 5, iclass 28, count 0 2006.173.19:47:40.22#ibcon#read 5, iclass 28, count 0 2006.173.19:47:40.22#ibcon#about to read 6, iclass 28, count 0 2006.173.19:47:40.22#ibcon#read 6, iclass 28, count 0 2006.173.19:47:40.22#ibcon#end of sib2, iclass 28, count 0 2006.173.19:47:40.22#ibcon#*after write, iclass 28, count 0 2006.173.19:47:40.22#ibcon#*before return 0, iclass 28, count 0 2006.173.19:47:40.22#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.19:47:40.22#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.19:47:40.22#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.19:47:40.22#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.19:47:40.22$vck44/vb=2,4 2006.173.19:47:40.22#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.19:47:40.22#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.19:47:40.22#ibcon#ireg 11 cls_cnt 2 2006.173.19:47:40.22#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.19:47:40.28#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.19:47:40.28#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.19:47:40.28#ibcon#enter wrdev, iclass 30, count 2 2006.173.19:47:40.28#ibcon#first serial, iclass 30, count 2 2006.173.19:47:40.28#ibcon#enter sib2, iclass 30, count 2 2006.173.19:47:40.28#ibcon#flushed, iclass 30, count 2 2006.173.19:47:40.28#ibcon#about to write, iclass 30, count 2 2006.173.19:47:40.28#ibcon#wrote, iclass 30, count 2 2006.173.19:47:40.28#ibcon#about to read 3, iclass 30, count 2 2006.173.19:47:40.30#ibcon#read 3, iclass 30, count 2 2006.173.19:47:40.30#ibcon#about to read 4, iclass 30, count 2 2006.173.19:47:40.30#ibcon#read 4, iclass 30, count 2 2006.173.19:47:40.30#ibcon#about to read 5, iclass 30, count 2 2006.173.19:47:40.30#ibcon#read 5, iclass 30, count 2 2006.173.19:47:40.30#ibcon#about to read 6, iclass 30, count 2 2006.173.19:47:40.30#ibcon#read 6, iclass 30, count 2 2006.173.19:47:40.30#ibcon#end of sib2, iclass 30, count 2 2006.173.19:47:40.30#ibcon#*mode == 0, iclass 30, count 2 2006.173.19:47:40.30#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.19:47:40.30#ibcon#[27=AT02-04\r\n] 2006.173.19:47:40.30#ibcon#*before write, iclass 30, count 2 2006.173.19:47:40.30#ibcon#enter sib2, iclass 30, count 2 2006.173.19:47:40.30#ibcon#flushed, iclass 30, count 2 2006.173.19:47:40.30#ibcon#about to write, iclass 30, count 2 2006.173.19:47:40.30#ibcon#wrote, iclass 30, count 2 2006.173.19:47:40.30#ibcon#about to read 3, iclass 30, count 2 2006.173.19:47:40.33#ibcon#read 3, iclass 30, count 2 2006.173.19:47:40.33#ibcon#about to read 4, iclass 30, count 2 2006.173.19:47:40.33#ibcon#read 4, iclass 30, count 2 2006.173.19:47:40.33#ibcon#about to read 5, iclass 30, count 2 2006.173.19:47:40.33#ibcon#read 5, iclass 30, count 2 2006.173.19:47:40.33#ibcon#about to read 6, iclass 30, count 2 2006.173.19:47:40.33#ibcon#read 6, iclass 30, count 2 2006.173.19:47:40.33#ibcon#end of sib2, iclass 30, count 2 2006.173.19:47:40.33#ibcon#*after write, iclass 30, count 2 2006.173.19:47:40.33#ibcon#*before return 0, iclass 30, count 2 2006.173.19:47:40.33#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.19:47:40.33#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.19:47:40.33#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.19:47:40.33#ibcon#ireg 7 cls_cnt 0 2006.173.19:47:40.33#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.19:47:40.45#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.19:47:40.45#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.19:47:40.45#ibcon#enter wrdev, iclass 30, count 0 2006.173.19:47:40.45#ibcon#first serial, iclass 30, count 0 2006.173.19:47:40.45#ibcon#enter sib2, iclass 30, count 0 2006.173.19:47:40.45#ibcon#flushed, iclass 30, count 0 2006.173.19:47:40.45#ibcon#about to write, iclass 30, count 0 2006.173.19:47:40.45#ibcon#wrote, iclass 30, count 0 2006.173.19:47:40.45#ibcon#about to read 3, iclass 30, count 0 2006.173.19:47:40.47#ibcon#read 3, iclass 30, count 0 2006.173.19:47:40.47#ibcon#about to read 4, iclass 30, count 0 2006.173.19:47:40.47#ibcon#read 4, iclass 30, count 0 2006.173.19:47:40.47#ibcon#about to read 5, iclass 30, count 0 2006.173.19:47:40.47#ibcon#read 5, iclass 30, count 0 2006.173.19:47:40.47#ibcon#about to read 6, iclass 30, count 0 2006.173.19:47:40.47#ibcon#read 6, iclass 30, count 0 2006.173.19:47:40.47#ibcon#end of sib2, iclass 30, count 0 2006.173.19:47:40.47#ibcon#*mode == 0, iclass 30, count 0 2006.173.19:47:40.47#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.19:47:40.47#ibcon#[27=USB\r\n] 2006.173.19:47:40.47#ibcon#*before write, iclass 30, count 0 2006.173.19:47:40.47#ibcon#enter sib2, iclass 30, count 0 2006.173.19:47:40.47#ibcon#flushed, iclass 30, count 0 2006.173.19:47:40.47#ibcon#about to write, iclass 30, count 0 2006.173.19:47:40.47#ibcon#wrote, iclass 30, count 0 2006.173.19:47:40.47#ibcon#about to read 3, iclass 30, count 0 2006.173.19:47:40.50#ibcon#read 3, iclass 30, count 0 2006.173.19:47:40.50#ibcon#about to read 4, iclass 30, count 0 2006.173.19:47:40.50#ibcon#read 4, iclass 30, count 0 2006.173.19:47:40.50#ibcon#about to read 5, iclass 30, count 0 2006.173.19:47:40.50#ibcon#read 5, iclass 30, count 0 2006.173.19:47:40.50#ibcon#about to read 6, iclass 30, count 0 2006.173.19:47:40.50#ibcon#read 6, iclass 30, count 0 2006.173.19:47:40.50#ibcon#end of sib2, iclass 30, count 0 2006.173.19:47:40.50#ibcon#*after write, iclass 30, count 0 2006.173.19:47:40.50#ibcon#*before return 0, iclass 30, count 0 2006.173.19:47:40.50#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.19:47:40.50#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.19:47:40.50#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.19:47:40.50#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.19:47:40.50$vck44/vblo=3,649.99 2006.173.19:47:40.50#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.19:47:40.50#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.19:47:40.50#ibcon#ireg 17 cls_cnt 0 2006.173.19:47:40.50#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.19:47:40.50#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.19:47:40.50#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.19:47:40.50#ibcon#enter wrdev, iclass 32, count 0 2006.173.19:47:40.50#ibcon#first serial, iclass 32, count 0 2006.173.19:47:40.50#ibcon#enter sib2, iclass 32, count 0 2006.173.19:47:40.50#ibcon#flushed, iclass 32, count 0 2006.173.19:47:40.50#ibcon#about to write, iclass 32, count 0 2006.173.19:47:40.50#ibcon#wrote, iclass 32, count 0 2006.173.19:47:40.50#ibcon#about to read 3, iclass 32, count 0 2006.173.19:47:40.52#ibcon#read 3, iclass 32, count 0 2006.173.19:47:40.52#ibcon#about to read 4, iclass 32, count 0 2006.173.19:47:40.52#ibcon#read 4, iclass 32, count 0 2006.173.19:47:40.52#ibcon#about to read 5, iclass 32, count 0 2006.173.19:47:40.52#ibcon#read 5, iclass 32, count 0 2006.173.19:47:40.52#ibcon#about to read 6, iclass 32, count 0 2006.173.19:47:40.52#ibcon#read 6, iclass 32, count 0 2006.173.19:47:40.52#ibcon#end of sib2, iclass 32, count 0 2006.173.19:47:40.52#ibcon#*mode == 0, iclass 32, count 0 2006.173.19:47:40.52#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.19:47:40.52#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.19:47:40.52#ibcon#*before write, iclass 32, count 0 2006.173.19:47:40.52#ibcon#enter sib2, iclass 32, count 0 2006.173.19:47:40.52#ibcon#flushed, iclass 32, count 0 2006.173.19:47:40.52#ibcon#about to write, iclass 32, count 0 2006.173.19:47:40.52#ibcon#wrote, iclass 32, count 0 2006.173.19:47:40.52#ibcon#about to read 3, iclass 32, count 0 2006.173.19:47:40.56#ibcon#read 3, iclass 32, count 0 2006.173.19:47:40.56#ibcon#about to read 4, iclass 32, count 0 2006.173.19:47:40.56#ibcon#read 4, iclass 32, count 0 2006.173.19:47:40.56#ibcon#about to read 5, iclass 32, count 0 2006.173.19:47:40.56#ibcon#read 5, iclass 32, count 0 2006.173.19:47:40.56#ibcon#about to read 6, iclass 32, count 0 2006.173.19:47:40.56#ibcon#read 6, iclass 32, count 0 2006.173.19:47:40.56#ibcon#end of sib2, iclass 32, count 0 2006.173.19:47:40.56#ibcon#*after write, iclass 32, count 0 2006.173.19:47:40.56#ibcon#*before return 0, iclass 32, count 0 2006.173.19:47:40.56#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.19:47:40.56#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.19:47:40.56#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.19:47:40.56#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.19:47:40.56$vck44/vb=3,4 2006.173.19:47:40.56#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.19:47:40.56#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.19:47:40.56#ibcon#ireg 11 cls_cnt 2 2006.173.19:47:40.56#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.19:47:40.62#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.19:47:40.62#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.19:47:40.62#ibcon#enter wrdev, iclass 34, count 2 2006.173.19:47:40.62#ibcon#first serial, iclass 34, count 2 2006.173.19:47:40.62#ibcon#enter sib2, iclass 34, count 2 2006.173.19:47:40.62#ibcon#flushed, iclass 34, count 2 2006.173.19:47:40.62#ibcon#about to write, iclass 34, count 2 2006.173.19:47:40.62#ibcon#wrote, iclass 34, count 2 2006.173.19:47:40.62#ibcon#about to read 3, iclass 34, count 2 2006.173.19:47:40.64#ibcon#read 3, iclass 34, count 2 2006.173.19:47:40.64#ibcon#about to read 4, iclass 34, count 2 2006.173.19:47:40.64#ibcon#read 4, iclass 34, count 2 2006.173.19:47:40.64#ibcon#about to read 5, iclass 34, count 2 2006.173.19:47:40.64#ibcon#read 5, iclass 34, count 2 2006.173.19:47:40.64#ibcon#about to read 6, iclass 34, count 2 2006.173.19:47:40.64#ibcon#read 6, iclass 34, count 2 2006.173.19:47:40.64#ibcon#end of sib2, iclass 34, count 2 2006.173.19:47:40.64#ibcon#*mode == 0, iclass 34, count 2 2006.173.19:47:40.64#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.19:47:40.64#ibcon#[27=AT03-04\r\n] 2006.173.19:47:40.64#ibcon#*before write, iclass 34, count 2 2006.173.19:47:40.64#ibcon#enter sib2, iclass 34, count 2 2006.173.19:47:40.64#ibcon#flushed, iclass 34, count 2 2006.173.19:47:40.64#ibcon#about to write, iclass 34, count 2 2006.173.19:47:40.64#ibcon#wrote, iclass 34, count 2 2006.173.19:47:40.64#ibcon#about to read 3, iclass 34, count 2 2006.173.19:47:40.67#ibcon#read 3, iclass 34, count 2 2006.173.19:47:40.67#ibcon#about to read 4, iclass 34, count 2 2006.173.19:47:40.67#ibcon#read 4, iclass 34, count 2 2006.173.19:47:40.67#ibcon#about to read 5, iclass 34, count 2 2006.173.19:47:40.67#ibcon#read 5, iclass 34, count 2 2006.173.19:47:40.67#ibcon#about to read 6, iclass 34, count 2 2006.173.19:47:40.67#ibcon#read 6, iclass 34, count 2 2006.173.19:47:40.67#ibcon#end of sib2, iclass 34, count 2 2006.173.19:47:40.67#ibcon#*after write, iclass 34, count 2 2006.173.19:47:40.67#ibcon#*before return 0, iclass 34, count 2 2006.173.19:47:40.67#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.19:47:40.67#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.19:47:40.67#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.19:47:40.67#ibcon#ireg 7 cls_cnt 0 2006.173.19:47:40.67#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.19:47:40.79#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.19:47:40.79#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.19:47:40.79#ibcon#enter wrdev, iclass 34, count 0 2006.173.19:47:40.79#ibcon#first serial, iclass 34, count 0 2006.173.19:47:40.79#ibcon#enter sib2, iclass 34, count 0 2006.173.19:47:40.79#ibcon#flushed, iclass 34, count 0 2006.173.19:47:40.79#ibcon#about to write, iclass 34, count 0 2006.173.19:47:40.79#ibcon#wrote, iclass 34, count 0 2006.173.19:47:40.79#ibcon#about to read 3, iclass 34, count 0 2006.173.19:47:40.81#ibcon#read 3, iclass 34, count 0 2006.173.19:47:40.81#ibcon#about to read 4, iclass 34, count 0 2006.173.19:47:40.81#ibcon#read 4, iclass 34, count 0 2006.173.19:47:40.81#ibcon#about to read 5, iclass 34, count 0 2006.173.19:47:40.81#ibcon#read 5, iclass 34, count 0 2006.173.19:47:40.81#ibcon#about to read 6, iclass 34, count 0 2006.173.19:47:40.81#ibcon#read 6, iclass 34, count 0 2006.173.19:47:40.81#ibcon#end of sib2, iclass 34, count 0 2006.173.19:47:40.81#ibcon#*mode == 0, iclass 34, count 0 2006.173.19:47:40.81#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.19:47:40.81#ibcon#[27=USB\r\n] 2006.173.19:47:40.81#ibcon#*before write, iclass 34, count 0 2006.173.19:47:40.81#ibcon#enter sib2, iclass 34, count 0 2006.173.19:47:40.81#ibcon#flushed, iclass 34, count 0 2006.173.19:47:40.81#ibcon#about to write, iclass 34, count 0 2006.173.19:47:40.81#ibcon#wrote, iclass 34, count 0 2006.173.19:47:40.81#ibcon#about to read 3, iclass 34, count 0 2006.173.19:47:40.84#ibcon#read 3, iclass 34, count 0 2006.173.19:47:40.84#ibcon#about to read 4, iclass 34, count 0 2006.173.19:47:40.84#ibcon#read 4, iclass 34, count 0 2006.173.19:47:40.84#ibcon#about to read 5, iclass 34, count 0 2006.173.19:47:40.84#ibcon#read 5, iclass 34, count 0 2006.173.19:47:40.84#ibcon#about to read 6, iclass 34, count 0 2006.173.19:47:40.84#ibcon#read 6, iclass 34, count 0 2006.173.19:47:40.84#ibcon#end of sib2, iclass 34, count 0 2006.173.19:47:40.84#ibcon#*after write, iclass 34, count 0 2006.173.19:47:40.84#ibcon#*before return 0, iclass 34, count 0 2006.173.19:47:40.84#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.19:47:40.84#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.19:47:40.84#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.19:47:40.84#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.19:47:40.84$vck44/vblo=4,679.99 2006.173.19:47:40.84#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.19:47:40.84#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.19:47:40.84#ibcon#ireg 17 cls_cnt 0 2006.173.19:47:40.84#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.19:47:40.84#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.19:47:40.84#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.19:47:40.84#ibcon#enter wrdev, iclass 36, count 0 2006.173.19:47:40.84#ibcon#first serial, iclass 36, count 0 2006.173.19:47:40.84#ibcon#enter sib2, iclass 36, count 0 2006.173.19:47:40.84#ibcon#flushed, iclass 36, count 0 2006.173.19:47:40.84#ibcon#about to write, iclass 36, count 0 2006.173.19:47:40.84#ibcon#wrote, iclass 36, count 0 2006.173.19:47:40.84#ibcon#about to read 3, iclass 36, count 0 2006.173.19:47:40.86#ibcon#read 3, iclass 36, count 0 2006.173.19:47:40.86#ibcon#about to read 4, iclass 36, count 0 2006.173.19:47:40.86#ibcon#read 4, iclass 36, count 0 2006.173.19:47:40.86#ibcon#about to read 5, iclass 36, count 0 2006.173.19:47:40.86#ibcon#read 5, iclass 36, count 0 2006.173.19:47:40.86#ibcon#about to read 6, iclass 36, count 0 2006.173.19:47:40.86#ibcon#read 6, iclass 36, count 0 2006.173.19:47:40.86#ibcon#end of sib2, iclass 36, count 0 2006.173.19:47:40.86#ibcon#*mode == 0, iclass 36, count 0 2006.173.19:47:40.86#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.19:47:40.86#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.19:47:40.86#ibcon#*before write, iclass 36, count 0 2006.173.19:47:40.86#ibcon#enter sib2, iclass 36, count 0 2006.173.19:47:40.86#ibcon#flushed, iclass 36, count 0 2006.173.19:47:40.86#ibcon#about to write, iclass 36, count 0 2006.173.19:47:40.86#ibcon#wrote, iclass 36, count 0 2006.173.19:47:40.86#ibcon#about to read 3, iclass 36, count 0 2006.173.19:47:40.90#ibcon#read 3, iclass 36, count 0 2006.173.19:47:40.90#ibcon#about to read 4, iclass 36, count 0 2006.173.19:47:40.90#ibcon#read 4, iclass 36, count 0 2006.173.19:47:40.90#ibcon#about to read 5, iclass 36, count 0 2006.173.19:47:40.90#ibcon#read 5, iclass 36, count 0 2006.173.19:47:40.90#ibcon#about to read 6, iclass 36, count 0 2006.173.19:47:40.90#ibcon#read 6, iclass 36, count 0 2006.173.19:47:40.90#ibcon#end of sib2, iclass 36, count 0 2006.173.19:47:40.90#ibcon#*after write, iclass 36, count 0 2006.173.19:47:40.90#ibcon#*before return 0, iclass 36, count 0 2006.173.19:47:40.90#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.19:47:40.90#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.19:47:40.90#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.19:47:40.90#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.19:47:40.90$vck44/vb=4,4 2006.173.19:47:40.90#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.19:47:40.90#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.19:47:40.90#ibcon#ireg 11 cls_cnt 2 2006.173.19:47:40.90#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.19:47:40.96#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.19:47:40.96#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.19:47:40.96#ibcon#enter wrdev, iclass 38, count 2 2006.173.19:47:40.96#ibcon#first serial, iclass 38, count 2 2006.173.19:47:40.96#ibcon#enter sib2, iclass 38, count 2 2006.173.19:47:40.96#ibcon#flushed, iclass 38, count 2 2006.173.19:47:40.96#ibcon#about to write, iclass 38, count 2 2006.173.19:47:40.96#ibcon#wrote, iclass 38, count 2 2006.173.19:47:40.96#ibcon#about to read 3, iclass 38, count 2 2006.173.19:47:40.98#ibcon#read 3, iclass 38, count 2 2006.173.19:47:40.98#ibcon#about to read 4, iclass 38, count 2 2006.173.19:47:40.98#ibcon#read 4, iclass 38, count 2 2006.173.19:47:40.98#ibcon#about to read 5, iclass 38, count 2 2006.173.19:47:40.98#ibcon#read 5, iclass 38, count 2 2006.173.19:47:40.98#ibcon#about to read 6, iclass 38, count 2 2006.173.19:47:40.98#ibcon#read 6, iclass 38, count 2 2006.173.19:47:40.98#ibcon#end of sib2, iclass 38, count 2 2006.173.19:47:40.98#ibcon#*mode == 0, iclass 38, count 2 2006.173.19:47:40.98#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.19:47:40.98#ibcon#[27=AT04-04\r\n] 2006.173.19:47:40.98#ibcon#*before write, iclass 38, count 2 2006.173.19:47:40.98#ibcon#enter sib2, iclass 38, count 2 2006.173.19:47:40.98#ibcon#flushed, iclass 38, count 2 2006.173.19:47:40.98#ibcon#about to write, iclass 38, count 2 2006.173.19:47:40.98#ibcon#wrote, iclass 38, count 2 2006.173.19:47:40.98#ibcon#about to read 3, iclass 38, count 2 2006.173.19:47:41.01#ibcon#read 3, iclass 38, count 2 2006.173.19:47:41.01#ibcon#about to read 4, iclass 38, count 2 2006.173.19:47:41.01#ibcon#read 4, iclass 38, count 2 2006.173.19:47:41.01#ibcon#about to read 5, iclass 38, count 2 2006.173.19:47:41.01#ibcon#read 5, iclass 38, count 2 2006.173.19:47:41.01#ibcon#about to read 6, iclass 38, count 2 2006.173.19:47:41.01#ibcon#read 6, iclass 38, count 2 2006.173.19:47:41.01#ibcon#end of sib2, iclass 38, count 2 2006.173.19:47:41.01#ibcon#*after write, iclass 38, count 2 2006.173.19:47:41.01#ibcon#*before return 0, iclass 38, count 2 2006.173.19:47:41.01#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.19:47:41.01#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.19:47:41.01#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.19:47:41.01#ibcon#ireg 7 cls_cnt 0 2006.173.19:47:41.01#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.19:47:41.13#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.19:47:41.13#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.19:47:41.13#ibcon#enter wrdev, iclass 38, count 0 2006.173.19:47:41.13#ibcon#first serial, iclass 38, count 0 2006.173.19:47:41.13#ibcon#enter sib2, iclass 38, count 0 2006.173.19:47:41.13#ibcon#flushed, iclass 38, count 0 2006.173.19:47:41.13#ibcon#about to write, iclass 38, count 0 2006.173.19:47:41.13#ibcon#wrote, iclass 38, count 0 2006.173.19:47:41.13#ibcon#about to read 3, iclass 38, count 0 2006.173.19:47:41.15#ibcon#read 3, iclass 38, count 0 2006.173.19:47:41.15#ibcon#about to read 4, iclass 38, count 0 2006.173.19:47:41.15#ibcon#read 4, iclass 38, count 0 2006.173.19:47:41.15#ibcon#about to read 5, iclass 38, count 0 2006.173.19:47:41.15#ibcon#read 5, iclass 38, count 0 2006.173.19:47:41.15#ibcon#about to read 6, iclass 38, count 0 2006.173.19:47:41.15#ibcon#read 6, iclass 38, count 0 2006.173.19:47:41.15#ibcon#end of sib2, iclass 38, count 0 2006.173.19:47:41.15#ibcon#*mode == 0, iclass 38, count 0 2006.173.19:47:41.15#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.19:47:41.15#ibcon#[27=USB\r\n] 2006.173.19:47:41.15#ibcon#*before write, iclass 38, count 0 2006.173.19:47:41.15#ibcon#enter sib2, iclass 38, count 0 2006.173.19:47:41.15#ibcon#flushed, iclass 38, count 0 2006.173.19:47:41.15#ibcon#about to write, iclass 38, count 0 2006.173.19:47:41.15#ibcon#wrote, iclass 38, count 0 2006.173.19:47:41.15#ibcon#about to read 3, iclass 38, count 0 2006.173.19:47:41.18#ibcon#read 3, iclass 38, count 0 2006.173.19:47:41.18#ibcon#about to read 4, iclass 38, count 0 2006.173.19:47:41.18#ibcon#read 4, iclass 38, count 0 2006.173.19:47:41.18#ibcon#about to read 5, iclass 38, count 0 2006.173.19:47:41.18#ibcon#read 5, iclass 38, count 0 2006.173.19:47:41.18#ibcon#about to read 6, iclass 38, count 0 2006.173.19:47:41.18#ibcon#read 6, iclass 38, count 0 2006.173.19:47:41.18#ibcon#end of sib2, iclass 38, count 0 2006.173.19:47:41.18#ibcon#*after write, iclass 38, count 0 2006.173.19:47:41.18#ibcon#*before return 0, iclass 38, count 0 2006.173.19:47:41.18#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.19:47:41.18#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.19:47:41.18#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.19:47:41.18#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.19:47:41.18$vck44/vblo=5,709.99 2006.173.19:47:41.18#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.19:47:41.18#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.19:47:41.18#ibcon#ireg 17 cls_cnt 0 2006.173.19:47:41.18#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.19:47:41.18#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.19:47:41.18#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.19:47:41.18#ibcon#enter wrdev, iclass 40, count 0 2006.173.19:47:41.18#ibcon#first serial, iclass 40, count 0 2006.173.19:47:41.18#ibcon#enter sib2, iclass 40, count 0 2006.173.19:47:41.18#ibcon#flushed, iclass 40, count 0 2006.173.19:47:41.18#ibcon#about to write, iclass 40, count 0 2006.173.19:47:41.18#ibcon#wrote, iclass 40, count 0 2006.173.19:47:41.18#ibcon#about to read 3, iclass 40, count 0 2006.173.19:47:41.20#ibcon#read 3, iclass 40, count 0 2006.173.19:47:41.20#ibcon#about to read 4, iclass 40, count 0 2006.173.19:47:41.20#ibcon#read 4, iclass 40, count 0 2006.173.19:47:41.20#ibcon#about to read 5, iclass 40, count 0 2006.173.19:47:41.20#ibcon#read 5, iclass 40, count 0 2006.173.19:47:41.20#ibcon#about to read 6, iclass 40, count 0 2006.173.19:47:41.20#ibcon#read 6, iclass 40, count 0 2006.173.19:47:41.20#ibcon#end of sib2, iclass 40, count 0 2006.173.19:47:41.20#ibcon#*mode == 0, iclass 40, count 0 2006.173.19:47:41.20#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.19:47:41.20#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.19:47:41.20#ibcon#*before write, iclass 40, count 0 2006.173.19:47:41.20#ibcon#enter sib2, iclass 40, count 0 2006.173.19:47:41.20#ibcon#flushed, iclass 40, count 0 2006.173.19:47:41.20#ibcon#about to write, iclass 40, count 0 2006.173.19:47:41.20#ibcon#wrote, iclass 40, count 0 2006.173.19:47:41.20#ibcon#about to read 3, iclass 40, count 0 2006.173.19:47:41.24#ibcon#read 3, iclass 40, count 0 2006.173.19:47:41.24#ibcon#about to read 4, iclass 40, count 0 2006.173.19:47:41.24#ibcon#read 4, iclass 40, count 0 2006.173.19:47:41.24#ibcon#about to read 5, iclass 40, count 0 2006.173.19:47:41.24#ibcon#read 5, iclass 40, count 0 2006.173.19:47:41.24#ibcon#about to read 6, iclass 40, count 0 2006.173.19:47:41.24#ibcon#read 6, iclass 40, count 0 2006.173.19:47:41.24#ibcon#end of sib2, iclass 40, count 0 2006.173.19:47:41.24#ibcon#*after write, iclass 40, count 0 2006.173.19:47:41.24#ibcon#*before return 0, iclass 40, count 0 2006.173.19:47:41.24#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.19:47:41.24#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.19:47:41.24#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.19:47:41.24#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.19:47:41.24$vck44/vb=5,4 2006.173.19:47:41.24#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.19:47:41.24#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.19:47:41.24#ibcon#ireg 11 cls_cnt 2 2006.173.19:47:41.24#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.19:47:41.30#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.19:47:41.30#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.19:47:41.30#ibcon#enter wrdev, iclass 4, count 2 2006.173.19:47:41.30#ibcon#first serial, iclass 4, count 2 2006.173.19:47:41.30#ibcon#enter sib2, iclass 4, count 2 2006.173.19:47:41.30#ibcon#flushed, iclass 4, count 2 2006.173.19:47:41.30#ibcon#about to write, iclass 4, count 2 2006.173.19:47:41.30#ibcon#wrote, iclass 4, count 2 2006.173.19:47:41.30#ibcon#about to read 3, iclass 4, count 2 2006.173.19:47:41.32#ibcon#read 3, iclass 4, count 2 2006.173.19:47:41.32#ibcon#about to read 4, iclass 4, count 2 2006.173.19:47:41.32#ibcon#read 4, iclass 4, count 2 2006.173.19:47:41.32#ibcon#about to read 5, iclass 4, count 2 2006.173.19:47:41.32#ibcon#read 5, iclass 4, count 2 2006.173.19:47:41.32#ibcon#about to read 6, iclass 4, count 2 2006.173.19:47:41.32#ibcon#read 6, iclass 4, count 2 2006.173.19:47:41.32#ibcon#end of sib2, iclass 4, count 2 2006.173.19:47:41.32#ibcon#*mode == 0, iclass 4, count 2 2006.173.19:47:41.32#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.19:47:41.32#ibcon#[27=AT05-04\r\n] 2006.173.19:47:41.32#ibcon#*before write, iclass 4, count 2 2006.173.19:47:41.32#ibcon#enter sib2, iclass 4, count 2 2006.173.19:47:41.32#ibcon#flushed, iclass 4, count 2 2006.173.19:47:41.32#ibcon#about to write, iclass 4, count 2 2006.173.19:47:41.32#ibcon#wrote, iclass 4, count 2 2006.173.19:47:41.32#ibcon#about to read 3, iclass 4, count 2 2006.173.19:47:41.35#ibcon#read 3, iclass 4, count 2 2006.173.19:47:41.35#ibcon#about to read 4, iclass 4, count 2 2006.173.19:47:41.35#ibcon#read 4, iclass 4, count 2 2006.173.19:47:41.35#ibcon#about to read 5, iclass 4, count 2 2006.173.19:47:41.35#ibcon#read 5, iclass 4, count 2 2006.173.19:47:41.35#ibcon#about to read 6, iclass 4, count 2 2006.173.19:47:41.35#ibcon#read 6, iclass 4, count 2 2006.173.19:47:41.35#ibcon#end of sib2, iclass 4, count 2 2006.173.19:47:41.35#ibcon#*after write, iclass 4, count 2 2006.173.19:47:41.35#ibcon#*before return 0, iclass 4, count 2 2006.173.19:47:41.35#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.19:47:41.35#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.19:47:41.35#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.19:47:41.35#ibcon#ireg 7 cls_cnt 0 2006.173.19:47:41.35#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.19:47:41.47#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.19:47:41.47#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.19:47:41.47#ibcon#enter wrdev, iclass 4, count 0 2006.173.19:47:41.47#ibcon#first serial, iclass 4, count 0 2006.173.19:47:41.47#ibcon#enter sib2, iclass 4, count 0 2006.173.19:47:41.47#ibcon#flushed, iclass 4, count 0 2006.173.19:47:41.47#ibcon#about to write, iclass 4, count 0 2006.173.19:47:41.47#ibcon#wrote, iclass 4, count 0 2006.173.19:47:41.47#ibcon#about to read 3, iclass 4, count 0 2006.173.19:47:41.49#ibcon#read 3, iclass 4, count 0 2006.173.19:47:41.49#ibcon#about to read 4, iclass 4, count 0 2006.173.19:47:41.49#ibcon#read 4, iclass 4, count 0 2006.173.19:47:41.49#ibcon#about to read 5, iclass 4, count 0 2006.173.19:47:41.49#ibcon#read 5, iclass 4, count 0 2006.173.19:47:41.49#ibcon#about to read 6, iclass 4, count 0 2006.173.19:47:41.49#ibcon#read 6, iclass 4, count 0 2006.173.19:47:41.49#ibcon#end of sib2, iclass 4, count 0 2006.173.19:47:41.49#ibcon#*mode == 0, iclass 4, count 0 2006.173.19:47:41.49#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.19:47:41.49#ibcon#[27=USB\r\n] 2006.173.19:47:41.49#ibcon#*before write, iclass 4, count 0 2006.173.19:47:41.49#ibcon#enter sib2, iclass 4, count 0 2006.173.19:47:41.49#ibcon#flushed, iclass 4, count 0 2006.173.19:47:41.49#ibcon#about to write, iclass 4, count 0 2006.173.19:47:41.49#ibcon#wrote, iclass 4, count 0 2006.173.19:47:41.49#ibcon#about to read 3, iclass 4, count 0 2006.173.19:47:41.52#ibcon#read 3, iclass 4, count 0 2006.173.19:47:41.52#ibcon#about to read 4, iclass 4, count 0 2006.173.19:47:41.52#ibcon#read 4, iclass 4, count 0 2006.173.19:47:41.52#ibcon#about to read 5, iclass 4, count 0 2006.173.19:47:41.52#ibcon#read 5, iclass 4, count 0 2006.173.19:47:41.52#ibcon#about to read 6, iclass 4, count 0 2006.173.19:47:41.52#ibcon#read 6, iclass 4, count 0 2006.173.19:47:41.52#ibcon#end of sib2, iclass 4, count 0 2006.173.19:47:41.52#ibcon#*after write, iclass 4, count 0 2006.173.19:47:41.52#ibcon#*before return 0, iclass 4, count 0 2006.173.19:47:41.52#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.19:47:41.52#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.19:47:41.52#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.19:47:41.52#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.19:47:41.52$vck44/vblo=6,719.99 2006.173.19:47:41.52#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.19:47:41.52#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.19:47:41.52#ibcon#ireg 17 cls_cnt 0 2006.173.19:47:41.52#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.19:47:41.52#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.19:47:41.52#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.19:47:41.52#ibcon#enter wrdev, iclass 6, count 0 2006.173.19:47:41.52#ibcon#first serial, iclass 6, count 0 2006.173.19:47:41.52#ibcon#enter sib2, iclass 6, count 0 2006.173.19:47:41.52#ibcon#flushed, iclass 6, count 0 2006.173.19:47:41.52#ibcon#about to write, iclass 6, count 0 2006.173.19:47:41.52#ibcon#wrote, iclass 6, count 0 2006.173.19:47:41.52#ibcon#about to read 3, iclass 6, count 0 2006.173.19:47:41.54#ibcon#read 3, iclass 6, count 0 2006.173.19:47:41.54#ibcon#about to read 4, iclass 6, count 0 2006.173.19:47:41.54#ibcon#read 4, iclass 6, count 0 2006.173.19:47:41.54#ibcon#about to read 5, iclass 6, count 0 2006.173.19:47:41.54#ibcon#read 5, iclass 6, count 0 2006.173.19:47:41.54#ibcon#about to read 6, iclass 6, count 0 2006.173.19:47:41.54#ibcon#read 6, iclass 6, count 0 2006.173.19:47:41.54#ibcon#end of sib2, iclass 6, count 0 2006.173.19:47:41.54#ibcon#*mode == 0, iclass 6, count 0 2006.173.19:47:41.54#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.19:47:41.54#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.19:47:41.54#ibcon#*before write, iclass 6, count 0 2006.173.19:47:41.54#ibcon#enter sib2, iclass 6, count 0 2006.173.19:47:41.54#ibcon#flushed, iclass 6, count 0 2006.173.19:47:41.54#ibcon#about to write, iclass 6, count 0 2006.173.19:47:41.54#ibcon#wrote, iclass 6, count 0 2006.173.19:47:41.54#ibcon#about to read 3, iclass 6, count 0 2006.173.19:47:41.58#ibcon#read 3, iclass 6, count 0 2006.173.19:47:41.58#ibcon#about to read 4, iclass 6, count 0 2006.173.19:47:41.58#ibcon#read 4, iclass 6, count 0 2006.173.19:47:41.58#ibcon#about to read 5, iclass 6, count 0 2006.173.19:47:41.58#ibcon#read 5, iclass 6, count 0 2006.173.19:47:41.58#ibcon#about to read 6, iclass 6, count 0 2006.173.19:47:41.58#ibcon#read 6, iclass 6, count 0 2006.173.19:47:41.58#ibcon#end of sib2, iclass 6, count 0 2006.173.19:47:41.58#ibcon#*after write, iclass 6, count 0 2006.173.19:47:41.58#ibcon#*before return 0, iclass 6, count 0 2006.173.19:47:41.58#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.19:47:41.58#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.19:47:41.58#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.19:47:41.58#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.19:47:41.58$vck44/vb=6,4 2006.173.19:47:41.58#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.19:47:41.58#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.19:47:41.58#ibcon#ireg 11 cls_cnt 2 2006.173.19:47:41.58#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.19:47:41.64#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.19:47:41.64#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.19:47:41.64#ibcon#enter wrdev, iclass 10, count 2 2006.173.19:47:41.64#ibcon#first serial, iclass 10, count 2 2006.173.19:47:41.64#ibcon#enter sib2, iclass 10, count 2 2006.173.19:47:41.64#ibcon#flushed, iclass 10, count 2 2006.173.19:47:41.64#ibcon#about to write, iclass 10, count 2 2006.173.19:47:41.64#ibcon#wrote, iclass 10, count 2 2006.173.19:47:41.64#ibcon#about to read 3, iclass 10, count 2 2006.173.19:47:41.66#ibcon#read 3, iclass 10, count 2 2006.173.19:47:41.66#ibcon#about to read 4, iclass 10, count 2 2006.173.19:47:41.66#ibcon#read 4, iclass 10, count 2 2006.173.19:47:41.66#ibcon#about to read 5, iclass 10, count 2 2006.173.19:47:41.66#ibcon#read 5, iclass 10, count 2 2006.173.19:47:41.66#ibcon#about to read 6, iclass 10, count 2 2006.173.19:47:41.66#ibcon#read 6, iclass 10, count 2 2006.173.19:47:41.66#ibcon#end of sib2, iclass 10, count 2 2006.173.19:47:41.66#ibcon#*mode == 0, iclass 10, count 2 2006.173.19:47:41.66#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.19:47:41.66#ibcon#[27=AT06-04\r\n] 2006.173.19:47:41.66#ibcon#*before write, iclass 10, count 2 2006.173.19:47:41.66#ibcon#enter sib2, iclass 10, count 2 2006.173.19:47:41.66#ibcon#flushed, iclass 10, count 2 2006.173.19:47:41.66#ibcon#about to write, iclass 10, count 2 2006.173.19:47:41.66#ibcon#wrote, iclass 10, count 2 2006.173.19:47:41.66#ibcon#about to read 3, iclass 10, count 2 2006.173.19:47:41.69#ibcon#read 3, iclass 10, count 2 2006.173.19:47:41.69#ibcon#about to read 4, iclass 10, count 2 2006.173.19:47:41.69#ibcon#read 4, iclass 10, count 2 2006.173.19:47:41.69#ibcon#about to read 5, iclass 10, count 2 2006.173.19:47:41.69#ibcon#read 5, iclass 10, count 2 2006.173.19:47:41.69#ibcon#about to read 6, iclass 10, count 2 2006.173.19:47:41.69#ibcon#read 6, iclass 10, count 2 2006.173.19:47:41.69#ibcon#end of sib2, iclass 10, count 2 2006.173.19:47:41.69#ibcon#*after write, iclass 10, count 2 2006.173.19:47:41.69#ibcon#*before return 0, iclass 10, count 2 2006.173.19:47:41.69#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.19:47:41.69#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.19:47:41.69#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.19:47:41.69#ibcon#ireg 7 cls_cnt 0 2006.173.19:47:41.69#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.19:47:41.81#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.19:47:41.81#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.19:47:41.81#ibcon#enter wrdev, iclass 10, count 0 2006.173.19:47:41.81#ibcon#first serial, iclass 10, count 0 2006.173.19:47:41.81#ibcon#enter sib2, iclass 10, count 0 2006.173.19:47:41.81#ibcon#flushed, iclass 10, count 0 2006.173.19:47:41.81#ibcon#about to write, iclass 10, count 0 2006.173.19:47:41.81#ibcon#wrote, iclass 10, count 0 2006.173.19:47:41.81#ibcon#about to read 3, iclass 10, count 0 2006.173.19:47:41.83#ibcon#read 3, iclass 10, count 0 2006.173.19:47:41.83#ibcon#about to read 4, iclass 10, count 0 2006.173.19:47:41.83#ibcon#read 4, iclass 10, count 0 2006.173.19:47:41.83#ibcon#about to read 5, iclass 10, count 0 2006.173.19:47:41.83#ibcon#read 5, iclass 10, count 0 2006.173.19:47:41.83#ibcon#about to read 6, iclass 10, count 0 2006.173.19:47:41.83#ibcon#read 6, iclass 10, count 0 2006.173.19:47:41.83#ibcon#end of sib2, iclass 10, count 0 2006.173.19:47:41.83#ibcon#*mode == 0, iclass 10, count 0 2006.173.19:47:41.83#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.19:47:41.83#ibcon#[27=USB\r\n] 2006.173.19:47:41.83#ibcon#*before write, iclass 10, count 0 2006.173.19:47:41.83#ibcon#enter sib2, iclass 10, count 0 2006.173.19:47:41.83#ibcon#flushed, iclass 10, count 0 2006.173.19:47:41.83#ibcon#about to write, iclass 10, count 0 2006.173.19:47:41.83#ibcon#wrote, iclass 10, count 0 2006.173.19:47:41.83#ibcon#about to read 3, iclass 10, count 0 2006.173.19:47:41.86#ibcon#read 3, iclass 10, count 0 2006.173.19:47:41.86#ibcon#about to read 4, iclass 10, count 0 2006.173.19:47:41.86#ibcon#read 4, iclass 10, count 0 2006.173.19:47:41.86#ibcon#about to read 5, iclass 10, count 0 2006.173.19:47:41.86#ibcon#read 5, iclass 10, count 0 2006.173.19:47:41.86#ibcon#about to read 6, iclass 10, count 0 2006.173.19:47:41.86#ibcon#read 6, iclass 10, count 0 2006.173.19:47:41.86#ibcon#end of sib2, iclass 10, count 0 2006.173.19:47:41.86#ibcon#*after write, iclass 10, count 0 2006.173.19:47:41.86#ibcon#*before return 0, iclass 10, count 0 2006.173.19:47:41.86#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.19:47:41.86#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.19:47:41.86#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.19:47:41.86#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.19:47:41.86$vck44/vblo=7,734.99 2006.173.19:47:41.86#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.19:47:41.86#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.19:47:41.86#ibcon#ireg 17 cls_cnt 0 2006.173.19:47:41.86#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.19:47:41.86#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.19:47:41.86#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.19:47:41.86#ibcon#enter wrdev, iclass 12, count 0 2006.173.19:47:41.86#ibcon#first serial, iclass 12, count 0 2006.173.19:47:41.86#ibcon#enter sib2, iclass 12, count 0 2006.173.19:47:41.86#ibcon#flushed, iclass 12, count 0 2006.173.19:47:41.86#ibcon#about to write, iclass 12, count 0 2006.173.19:47:41.86#ibcon#wrote, iclass 12, count 0 2006.173.19:47:41.86#ibcon#about to read 3, iclass 12, count 0 2006.173.19:47:41.88#ibcon#read 3, iclass 12, count 0 2006.173.19:47:41.88#ibcon#about to read 4, iclass 12, count 0 2006.173.19:47:41.88#ibcon#read 4, iclass 12, count 0 2006.173.19:47:41.88#ibcon#about to read 5, iclass 12, count 0 2006.173.19:47:41.88#ibcon#read 5, iclass 12, count 0 2006.173.19:47:41.88#ibcon#about to read 6, iclass 12, count 0 2006.173.19:47:41.88#ibcon#read 6, iclass 12, count 0 2006.173.19:47:41.88#ibcon#end of sib2, iclass 12, count 0 2006.173.19:47:41.88#ibcon#*mode == 0, iclass 12, count 0 2006.173.19:47:41.88#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.19:47:41.88#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.19:47:41.88#ibcon#*before write, iclass 12, count 0 2006.173.19:47:41.88#ibcon#enter sib2, iclass 12, count 0 2006.173.19:47:41.88#ibcon#flushed, iclass 12, count 0 2006.173.19:47:41.88#ibcon#about to write, iclass 12, count 0 2006.173.19:47:41.88#ibcon#wrote, iclass 12, count 0 2006.173.19:47:41.88#ibcon#about to read 3, iclass 12, count 0 2006.173.19:47:41.92#ibcon#read 3, iclass 12, count 0 2006.173.19:47:41.92#ibcon#about to read 4, iclass 12, count 0 2006.173.19:47:41.92#ibcon#read 4, iclass 12, count 0 2006.173.19:47:41.92#ibcon#about to read 5, iclass 12, count 0 2006.173.19:47:41.92#ibcon#read 5, iclass 12, count 0 2006.173.19:47:41.92#ibcon#about to read 6, iclass 12, count 0 2006.173.19:47:41.92#ibcon#read 6, iclass 12, count 0 2006.173.19:47:41.92#ibcon#end of sib2, iclass 12, count 0 2006.173.19:47:41.92#ibcon#*after write, iclass 12, count 0 2006.173.19:47:41.92#ibcon#*before return 0, iclass 12, count 0 2006.173.19:47:41.92#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.19:47:41.92#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.19:47:41.92#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.19:47:41.92#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.19:47:41.92$vck44/vb=7,4 2006.173.19:47:41.92#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.19:47:41.92#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.19:47:41.92#ibcon#ireg 11 cls_cnt 2 2006.173.19:47:41.92#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.19:47:41.98#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.19:47:41.98#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.19:47:41.98#ibcon#enter wrdev, iclass 14, count 2 2006.173.19:47:41.98#ibcon#first serial, iclass 14, count 2 2006.173.19:47:41.98#ibcon#enter sib2, iclass 14, count 2 2006.173.19:47:41.98#ibcon#flushed, iclass 14, count 2 2006.173.19:47:41.98#ibcon#about to write, iclass 14, count 2 2006.173.19:47:41.98#ibcon#wrote, iclass 14, count 2 2006.173.19:47:41.98#ibcon#about to read 3, iclass 14, count 2 2006.173.19:47:42.00#ibcon#read 3, iclass 14, count 2 2006.173.19:47:42.00#ibcon#about to read 4, iclass 14, count 2 2006.173.19:47:42.00#ibcon#read 4, iclass 14, count 2 2006.173.19:47:42.00#ibcon#about to read 5, iclass 14, count 2 2006.173.19:47:42.00#ibcon#read 5, iclass 14, count 2 2006.173.19:47:42.00#ibcon#about to read 6, iclass 14, count 2 2006.173.19:47:42.00#ibcon#read 6, iclass 14, count 2 2006.173.19:47:42.00#ibcon#end of sib2, iclass 14, count 2 2006.173.19:47:42.00#ibcon#*mode == 0, iclass 14, count 2 2006.173.19:47:42.00#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.19:47:42.00#ibcon#[27=AT07-04\r\n] 2006.173.19:47:42.00#ibcon#*before write, iclass 14, count 2 2006.173.19:47:42.00#ibcon#enter sib2, iclass 14, count 2 2006.173.19:47:42.00#ibcon#flushed, iclass 14, count 2 2006.173.19:47:42.00#ibcon#about to write, iclass 14, count 2 2006.173.19:47:42.00#ibcon#wrote, iclass 14, count 2 2006.173.19:47:42.00#ibcon#about to read 3, iclass 14, count 2 2006.173.19:47:42.03#ibcon#read 3, iclass 14, count 2 2006.173.19:47:42.03#ibcon#about to read 4, iclass 14, count 2 2006.173.19:47:42.03#ibcon#read 4, iclass 14, count 2 2006.173.19:47:42.03#ibcon#about to read 5, iclass 14, count 2 2006.173.19:47:42.03#ibcon#read 5, iclass 14, count 2 2006.173.19:47:42.03#ibcon#about to read 6, iclass 14, count 2 2006.173.19:47:42.03#ibcon#read 6, iclass 14, count 2 2006.173.19:47:42.03#ibcon#end of sib2, iclass 14, count 2 2006.173.19:47:42.03#ibcon#*after write, iclass 14, count 2 2006.173.19:47:42.03#ibcon#*before return 0, iclass 14, count 2 2006.173.19:47:42.03#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.19:47:42.03#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.19:47:42.03#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.19:47:42.03#ibcon#ireg 7 cls_cnt 0 2006.173.19:47:42.03#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.19:47:42.15#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.19:47:42.15#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.19:47:42.15#ibcon#enter wrdev, iclass 14, count 0 2006.173.19:47:42.15#ibcon#first serial, iclass 14, count 0 2006.173.19:47:42.15#ibcon#enter sib2, iclass 14, count 0 2006.173.19:47:42.15#ibcon#flushed, iclass 14, count 0 2006.173.19:47:42.15#ibcon#about to write, iclass 14, count 0 2006.173.19:47:42.15#ibcon#wrote, iclass 14, count 0 2006.173.19:47:42.15#ibcon#about to read 3, iclass 14, count 0 2006.173.19:47:42.17#ibcon#read 3, iclass 14, count 0 2006.173.19:47:42.17#ibcon#about to read 4, iclass 14, count 0 2006.173.19:47:42.17#ibcon#read 4, iclass 14, count 0 2006.173.19:47:42.17#ibcon#about to read 5, iclass 14, count 0 2006.173.19:47:42.17#ibcon#read 5, iclass 14, count 0 2006.173.19:47:42.17#ibcon#about to read 6, iclass 14, count 0 2006.173.19:47:42.17#ibcon#read 6, iclass 14, count 0 2006.173.19:47:42.17#ibcon#end of sib2, iclass 14, count 0 2006.173.19:47:42.17#ibcon#*mode == 0, iclass 14, count 0 2006.173.19:47:42.17#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.19:47:42.17#ibcon#[27=USB\r\n] 2006.173.19:47:42.17#ibcon#*before write, iclass 14, count 0 2006.173.19:47:42.17#ibcon#enter sib2, iclass 14, count 0 2006.173.19:47:42.17#ibcon#flushed, iclass 14, count 0 2006.173.19:47:42.17#ibcon#about to write, iclass 14, count 0 2006.173.19:47:42.17#ibcon#wrote, iclass 14, count 0 2006.173.19:47:42.17#ibcon#about to read 3, iclass 14, count 0 2006.173.19:47:42.20#ibcon#read 3, iclass 14, count 0 2006.173.19:47:42.20#ibcon#about to read 4, iclass 14, count 0 2006.173.19:47:42.20#ibcon#read 4, iclass 14, count 0 2006.173.19:47:42.20#ibcon#about to read 5, iclass 14, count 0 2006.173.19:47:42.20#ibcon#read 5, iclass 14, count 0 2006.173.19:47:42.20#ibcon#about to read 6, iclass 14, count 0 2006.173.19:47:42.20#ibcon#read 6, iclass 14, count 0 2006.173.19:47:42.20#ibcon#end of sib2, iclass 14, count 0 2006.173.19:47:42.20#ibcon#*after write, iclass 14, count 0 2006.173.19:47:42.20#ibcon#*before return 0, iclass 14, count 0 2006.173.19:47:42.20#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.19:47:42.20#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.19:47:42.20#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.19:47:42.20#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.19:47:42.20$vck44/vblo=8,744.99 2006.173.19:47:42.20#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.19:47:42.20#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.19:47:42.20#ibcon#ireg 17 cls_cnt 0 2006.173.19:47:42.20#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.19:47:42.20#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.19:47:42.20#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.19:47:42.20#ibcon#enter wrdev, iclass 16, count 0 2006.173.19:47:42.20#ibcon#first serial, iclass 16, count 0 2006.173.19:47:42.20#ibcon#enter sib2, iclass 16, count 0 2006.173.19:47:42.20#ibcon#flushed, iclass 16, count 0 2006.173.19:47:42.20#ibcon#about to write, iclass 16, count 0 2006.173.19:47:42.20#ibcon#wrote, iclass 16, count 0 2006.173.19:47:42.20#ibcon#about to read 3, iclass 16, count 0 2006.173.19:47:42.22#ibcon#read 3, iclass 16, count 0 2006.173.19:47:42.22#ibcon#about to read 4, iclass 16, count 0 2006.173.19:47:42.22#ibcon#read 4, iclass 16, count 0 2006.173.19:47:42.22#ibcon#about to read 5, iclass 16, count 0 2006.173.19:47:42.22#ibcon#read 5, iclass 16, count 0 2006.173.19:47:42.22#ibcon#about to read 6, iclass 16, count 0 2006.173.19:47:42.22#ibcon#read 6, iclass 16, count 0 2006.173.19:47:42.22#ibcon#end of sib2, iclass 16, count 0 2006.173.19:47:42.22#ibcon#*mode == 0, iclass 16, count 0 2006.173.19:47:42.22#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.19:47:42.22#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.19:47:42.22#ibcon#*before write, iclass 16, count 0 2006.173.19:47:42.22#ibcon#enter sib2, iclass 16, count 0 2006.173.19:47:42.22#ibcon#flushed, iclass 16, count 0 2006.173.19:47:42.22#ibcon#about to write, iclass 16, count 0 2006.173.19:47:42.22#ibcon#wrote, iclass 16, count 0 2006.173.19:47:42.22#ibcon#about to read 3, iclass 16, count 0 2006.173.19:47:42.26#ibcon#read 3, iclass 16, count 0 2006.173.19:47:42.26#ibcon#about to read 4, iclass 16, count 0 2006.173.19:47:42.26#ibcon#read 4, iclass 16, count 0 2006.173.19:47:42.26#ibcon#about to read 5, iclass 16, count 0 2006.173.19:47:42.26#ibcon#read 5, iclass 16, count 0 2006.173.19:47:42.26#ibcon#about to read 6, iclass 16, count 0 2006.173.19:47:42.26#ibcon#read 6, iclass 16, count 0 2006.173.19:47:42.26#ibcon#end of sib2, iclass 16, count 0 2006.173.19:47:42.26#ibcon#*after write, iclass 16, count 0 2006.173.19:47:42.26#ibcon#*before return 0, iclass 16, count 0 2006.173.19:47:42.26#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.19:47:42.26#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.19:47:42.26#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.19:47:42.26#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.19:47:42.26$vck44/vb=8,4 2006.173.19:47:42.26#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.19:47:42.26#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.19:47:42.26#ibcon#ireg 11 cls_cnt 2 2006.173.19:47:42.26#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.19:47:42.32#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.19:47:42.32#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.19:47:42.32#ibcon#enter wrdev, iclass 18, count 2 2006.173.19:47:42.32#ibcon#first serial, iclass 18, count 2 2006.173.19:47:42.32#ibcon#enter sib2, iclass 18, count 2 2006.173.19:47:42.32#ibcon#flushed, iclass 18, count 2 2006.173.19:47:42.32#ibcon#about to write, iclass 18, count 2 2006.173.19:47:42.32#ibcon#wrote, iclass 18, count 2 2006.173.19:47:42.32#ibcon#about to read 3, iclass 18, count 2 2006.173.19:47:42.34#ibcon#read 3, iclass 18, count 2 2006.173.19:47:42.34#ibcon#about to read 4, iclass 18, count 2 2006.173.19:47:42.34#ibcon#read 4, iclass 18, count 2 2006.173.19:47:42.34#ibcon#about to read 5, iclass 18, count 2 2006.173.19:47:42.34#ibcon#read 5, iclass 18, count 2 2006.173.19:47:42.34#ibcon#about to read 6, iclass 18, count 2 2006.173.19:47:42.34#ibcon#read 6, iclass 18, count 2 2006.173.19:47:42.34#ibcon#end of sib2, iclass 18, count 2 2006.173.19:47:42.34#ibcon#*mode == 0, iclass 18, count 2 2006.173.19:47:42.34#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.19:47:42.34#ibcon#[27=AT08-04\r\n] 2006.173.19:47:42.34#ibcon#*before write, iclass 18, count 2 2006.173.19:47:42.34#ibcon#enter sib2, iclass 18, count 2 2006.173.19:47:42.34#ibcon#flushed, iclass 18, count 2 2006.173.19:47:42.34#ibcon#about to write, iclass 18, count 2 2006.173.19:47:42.34#ibcon#wrote, iclass 18, count 2 2006.173.19:47:42.34#ibcon#about to read 3, iclass 18, count 2 2006.173.19:47:42.37#ibcon#read 3, iclass 18, count 2 2006.173.19:47:42.37#ibcon#about to read 4, iclass 18, count 2 2006.173.19:47:42.37#ibcon#read 4, iclass 18, count 2 2006.173.19:47:42.37#ibcon#about to read 5, iclass 18, count 2 2006.173.19:47:42.37#ibcon#read 5, iclass 18, count 2 2006.173.19:47:42.37#ibcon#about to read 6, iclass 18, count 2 2006.173.19:47:42.37#ibcon#read 6, iclass 18, count 2 2006.173.19:47:42.37#ibcon#end of sib2, iclass 18, count 2 2006.173.19:47:42.37#ibcon#*after write, iclass 18, count 2 2006.173.19:47:42.37#ibcon#*before return 0, iclass 18, count 2 2006.173.19:47:42.37#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.19:47:42.37#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.19:47:42.37#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.19:47:42.37#ibcon#ireg 7 cls_cnt 0 2006.173.19:47:42.37#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.19:47:42.49#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.19:47:42.49#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.19:47:42.49#ibcon#enter wrdev, iclass 18, count 0 2006.173.19:47:42.49#ibcon#first serial, iclass 18, count 0 2006.173.19:47:42.49#ibcon#enter sib2, iclass 18, count 0 2006.173.19:47:42.49#ibcon#flushed, iclass 18, count 0 2006.173.19:47:42.49#ibcon#about to write, iclass 18, count 0 2006.173.19:47:42.49#ibcon#wrote, iclass 18, count 0 2006.173.19:47:42.49#ibcon#about to read 3, iclass 18, count 0 2006.173.19:47:42.51#ibcon#read 3, iclass 18, count 0 2006.173.19:47:42.51#ibcon#about to read 4, iclass 18, count 0 2006.173.19:47:42.51#ibcon#read 4, iclass 18, count 0 2006.173.19:47:42.51#ibcon#about to read 5, iclass 18, count 0 2006.173.19:47:42.51#ibcon#read 5, iclass 18, count 0 2006.173.19:47:42.51#ibcon#about to read 6, iclass 18, count 0 2006.173.19:47:42.51#ibcon#read 6, iclass 18, count 0 2006.173.19:47:42.51#ibcon#end of sib2, iclass 18, count 0 2006.173.19:47:42.51#ibcon#*mode == 0, iclass 18, count 0 2006.173.19:47:42.51#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.19:47:42.51#ibcon#[27=USB\r\n] 2006.173.19:47:42.51#ibcon#*before write, iclass 18, count 0 2006.173.19:47:42.51#ibcon#enter sib2, iclass 18, count 0 2006.173.19:47:42.51#ibcon#flushed, iclass 18, count 0 2006.173.19:47:42.51#ibcon#about to write, iclass 18, count 0 2006.173.19:47:42.51#ibcon#wrote, iclass 18, count 0 2006.173.19:47:42.51#ibcon#about to read 3, iclass 18, count 0 2006.173.19:47:42.54#ibcon#read 3, iclass 18, count 0 2006.173.19:47:42.54#ibcon#about to read 4, iclass 18, count 0 2006.173.19:47:42.54#ibcon#read 4, iclass 18, count 0 2006.173.19:47:42.54#ibcon#about to read 5, iclass 18, count 0 2006.173.19:47:42.54#ibcon#read 5, iclass 18, count 0 2006.173.19:47:42.54#ibcon#about to read 6, iclass 18, count 0 2006.173.19:47:42.54#ibcon#read 6, iclass 18, count 0 2006.173.19:47:42.54#ibcon#end of sib2, iclass 18, count 0 2006.173.19:47:42.54#ibcon#*after write, iclass 18, count 0 2006.173.19:47:42.54#ibcon#*before return 0, iclass 18, count 0 2006.173.19:47:42.54#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.19:47:42.54#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.19:47:42.54#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.19:47:42.54#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.19:47:42.54$vck44/vabw=wide 2006.173.19:47:42.54#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.19:47:42.54#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.19:47:42.54#ibcon#ireg 8 cls_cnt 0 2006.173.19:47:42.54#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.19:47:42.54#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.19:47:42.54#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.19:47:42.54#ibcon#enter wrdev, iclass 20, count 0 2006.173.19:47:42.54#ibcon#first serial, iclass 20, count 0 2006.173.19:47:42.54#ibcon#enter sib2, iclass 20, count 0 2006.173.19:47:42.54#ibcon#flushed, iclass 20, count 0 2006.173.19:47:42.54#ibcon#about to write, iclass 20, count 0 2006.173.19:47:42.54#ibcon#wrote, iclass 20, count 0 2006.173.19:47:42.54#ibcon#about to read 3, iclass 20, count 0 2006.173.19:47:42.56#ibcon#read 3, iclass 20, count 0 2006.173.19:47:42.56#ibcon#about to read 4, iclass 20, count 0 2006.173.19:47:42.56#ibcon#read 4, iclass 20, count 0 2006.173.19:47:42.56#ibcon#about to read 5, iclass 20, count 0 2006.173.19:47:42.56#ibcon#read 5, iclass 20, count 0 2006.173.19:47:42.56#ibcon#about to read 6, iclass 20, count 0 2006.173.19:47:42.56#ibcon#read 6, iclass 20, count 0 2006.173.19:47:42.56#ibcon#end of sib2, iclass 20, count 0 2006.173.19:47:42.56#ibcon#*mode == 0, iclass 20, count 0 2006.173.19:47:42.56#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.19:47:42.56#ibcon#[25=BW32\r\n] 2006.173.19:47:42.56#ibcon#*before write, iclass 20, count 0 2006.173.19:47:42.56#ibcon#enter sib2, iclass 20, count 0 2006.173.19:47:42.56#ibcon#flushed, iclass 20, count 0 2006.173.19:47:42.56#ibcon#about to write, iclass 20, count 0 2006.173.19:47:42.56#ibcon#wrote, iclass 20, count 0 2006.173.19:47:42.56#ibcon#about to read 3, iclass 20, count 0 2006.173.19:47:42.59#ibcon#read 3, iclass 20, count 0 2006.173.19:47:42.59#ibcon#about to read 4, iclass 20, count 0 2006.173.19:47:42.59#ibcon#read 4, iclass 20, count 0 2006.173.19:47:42.59#ibcon#about to read 5, iclass 20, count 0 2006.173.19:47:42.59#ibcon#read 5, iclass 20, count 0 2006.173.19:47:42.59#ibcon#about to read 6, iclass 20, count 0 2006.173.19:47:42.59#ibcon#read 6, iclass 20, count 0 2006.173.19:47:42.59#ibcon#end of sib2, iclass 20, count 0 2006.173.19:47:42.59#ibcon#*after write, iclass 20, count 0 2006.173.19:47:42.59#ibcon#*before return 0, iclass 20, count 0 2006.173.19:47:42.59#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.19:47:42.59#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.19:47:42.59#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.19:47:42.59#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.19:47:42.59$vck44/vbbw=wide 2006.173.19:47:42.59#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.19:47:42.59#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.19:47:42.59#ibcon#ireg 8 cls_cnt 0 2006.173.19:47:42.59#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.19:47:42.66#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.19:47:42.66#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.19:47:42.66#ibcon#enter wrdev, iclass 22, count 0 2006.173.19:47:42.66#ibcon#first serial, iclass 22, count 0 2006.173.19:47:42.66#ibcon#enter sib2, iclass 22, count 0 2006.173.19:47:42.66#ibcon#flushed, iclass 22, count 0 2006.173.19:47:42.66#ibcon#about to write, iclass 22, count 0 2006.173.19:47:42.66#ibcon#wrote, iclass 22, count 0 2006.173.19:47:42.66#ibcon#about to read 3, iclass 22, count 0 2006.173.19:47:42.68#ibcon#read 3, iclass 22, count 0 2006.173.19:47:42.68#ibcon#about to read 4, iclass 22, count 0 2006.173.19:47:42.68#ibcon#read 4, iclass 22, count 0 2006.173.19:47:42.68#ibcon#about to read 5, iclass 22, count 0 2006.173.19:47:42.68#ibcon#read 5, iclass 22, count 0 2006.173.19:47:42.68#ibcon#about to read 6, iclass 22, count 0 2006.173.19:47:42.68#ibcon#read 6, iclass 22, count 0 2006.173.19:47:42.68#ibcon#end of sib2, iclass 22, count 0 2006.173.19:47:42.68#ibcon#*mode == 0, iclass 22, count 0 2006.173.19:47:42.68#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.19:47:42.68#ibcon#[27=BW32\r\n] 2006.173.19:47:42.68#ibcon#*before write, iclass 22, count 0 2006.173.19:47:42.68#ibcon#enter sib2, iclass 22, count 0 2006.173.19:47:42.68#ibcon#flushed, iclass 22, count 0 2006.173.19:47:42.68#ibcon#about to write, iclass 22, count 0 2006.173.19:47:42.68#ibcon#wrote, iclass 22, count 0 2006.173.19:47:42.68#ibcon#about to read 3, iclass 22, count 0 2006.173.19:47:42.71#ibcon#read 3, iclass 22, count 0 2006.173.19:47:42.71#ibcon#about to read 4, iclass 22, count 0 2006.173.19:47:42.71#ibcon#read 4, iclass 22, count 0 2006.173.19:47:42.71#ibcon#about to read 5, iclass 22, count 0 2006.173.19:47:42.71#ibcon#read 5, iclass 22, count 0 2006.173.19:47:42.71#ibcon#about to read 6, iclass 22, count 0 2006.173.19:47:42.71#ibcon#read 6, iclass 22, count 0 2006.173.19:47:42.71#ibcon#end of sib2, iclass 22, count 0 2006.173.19:47:42.71#ibcon#*after write, iclass 22, count 0 2006.173.19:47:42.71#ibcon#*before return 0, iclass 22, count 0 2006.173.19:47:42.71#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.19:47:42.71#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.19:47:42.71#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.19:47:42.71#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.19:47:42.71$setupk4/ifdk4 2006.173.19:47:42.71$ifdk4/lo= 2006.173.19:47:42.71$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.19:47:42.71$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.19:47:42.71$ifdk4/patch= 2006.173.19:47:42.71$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.19:47:42.71$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.19:47:42.71$setupk4/!*+20s 2006.173.19:47:44.55#abcon#<5=/00 0.2 0.8 19.321001002.5\r\n> 2006.173.19:47:44.57#abcon#{5=INTERFACE CLEAR} 2006.173.19:47:44.63#abcon#[5=S1D000X0/0*\r\n] 2006.173.19:47:54.72#abcon#<5=/00 0.2 0.8 19.321001002.5\r\n> 2006.173.19:47:54.74#abcon#{5=INTERFACE CLEAR} 2006.173.19:47:54.80#abcon#[5=S1D000X0/0*\r\n] 2006.173.19:47:57.21$setupk4/"tpicd 2006.173.19:47:57.21$setupk4/echo=off 2006.173.19:47:57.21$setupk4/xlog=off 2006.173.19:47:57.21:!2006.173.19:49:41 2006.173.19:48:18.14#trakl#Source acquired 2006.173.19:48:20.14#flagr#flagr/antenna,acquired 2006.173.19:49:41.00:preob 2006.173.19:49:42.14/onsource/TRACKING 2006.173.19:49:42.14:!2006.173.19:49:51 2006.173.19:49:51.00:"tape 2006.173.19:49:51.00:"st=record 2006.173.19:49:51.00:data_valid=on 2006.173.19:49:51.00:midob 2006.173.19:49:51.14/onsource/TRACKING 2006.173.19:49:51.14/wx/19.30,1002.5,100 2006.173.19:49:51.30/cable/+6.5148E-03 2006.173.19:49:52.39/va/01,07,usb,yes,38,41 2006.173.19:49:52.39/va/02,06,usb,yes,38,39 2006.173.19:49:52.39/va/03,05,usb,yes,48,50 2006.173.19:49:52.39/va/04,06,usb,yes,39,41 2006.173.19:49:52.39/va/05,04,usb,yes,30,31 2006.173.19:49:52.39/va/06,03,usb,yes,42,42 2006.173.19:49:52.39/va/07,04,usb,yes,34,35 2006.173.19:49:52.39/va/08,04,usb,yes,29,35 2006.173.19:49:52.62/valo/01,524.99,yes,locked 2006.173.19:49:52.62/valo/02,534.99,yes,locked 2006.173.19:49:52.62/valo/03,564.99,yes,locked 2006.173.19:49:52.62/valo/04,624.99,yes,locked 2006.173.19:49:52.62/valo/05,734.99,yes,locked 2006.173.19:49:52.62/valo/06,814.99,yes,locked 2006.173.19:49:52.62/valo/07,864.99,yes,locked 2006.173.19:49:52.62/valo/08,884.99,yes,locked 2006.173.19:49:53.71/vb/01,04,usb,yes,30,28 2006.173.19:49:53.71/vb/02,04,usb,yes,32,32 2006.173.19:49:53.71/vb/03,04,usb,yes,29,32 2006.173.19:49:53.71/vb/04,04,usb,yes,34,33 2006.173.19:49:53.71/vb/05,04,usb,yes,26,29 2006.173.19:49:53.71/vb/06,04,usb,yes,31,27 2006.173.19:49:53.71/vb/07,04,usb,yes,31,30 2006.173.19:49:53.71/vb/08,04,usb,yes,28,32 2006.173.19:49:53.94/vblo/01,629.99,yes,locked 2006.173.19:49:53.94/vblo/02,634.99,yes,locked 2006.173.19:49:53.94/vblo/03,649.99,yes,locked 2006.173.19:49:53.94/vblo/04,679.99,yes,locked 2006.173.19:49:53.94/vblo/05,709.99,yes,locked 2006.173.19:49:53.94/vblo/06,719.99,yes,locked 2006.173.19:49:53.94/vblo/07,734.99,yes,locked 2006.173.19:49:53.94/vblo/08,744.99,yes,locked 2006.173.19:49:54.09/vabw/8 2006.173.19:49:54.24/vbbw/8 2006.173.19:49:54.33/xfe/off,on,14.5 2006.173.19:49:54.71/ifatt/23,28,28,28 2006.173.19:49:55.08/fmout-gps/S +3.86E-07 2006.173.19:49:55.12:!2006.173.19:55:31 2006.173.19:55:31.00:data_valid=off 2006.173.19:55:31.01:"et 2006.173.19:55:31.01:!+3s 2006.173.19:55:34.04:"tape 2006.173.19:55:34.05:postob 2006.173.19:55:34.24/cable/+6.5151E-03 2006.173.19:55:34.25/wx/19.29,1002.6,100 2006.173.19:55:34.30/fmout-gps/S +3.88E-07 2006.173.19:55:34.31:scan_name=173-2003,jd0606,60 2006.173.19:55:34.31:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.173.19:55:36.13#flagr#flagr/antenna,new-source 2006.173.19:55:36.13:checkk5 2006.173.19:55:36.55/chk_autoobs//k5ts1/ autoobs is running! 2006.173.19:55:36.96/chk_autoobs//k5ts2/ autoobs is running! 2006.173.19:55:37.34/chk_autoobs//k5ts3/ autoobs is running! 2006.173.19:55:37.74/chk_autoobs//k5ts4/ autoobs is running! 2006.173.19:55:38.12/chk_obsdata//k5ts1/T1731949??a.dat file size is correct (nominal:1360MB, actual:1356MB). 2006.173.19:55:38.51/chk_obsdata//k5ts2/T1731949??b.dat file size is correct (nominal:1360MB, actual:1356MB). 2006.173.19:55:38.92/chk_obsdata//k5ts3/T1731949??c.dat file size is correct (nominal:1360MB, actual:1356MB). 2006.173.19:55:39.32/chk_obsdata//k5ts4/T1731949??d.dat file size is correct (nominal:1360MB, actual:1356MB). 2006.173.19:55:40.04/k5log//k5ts1_log_newline 2006.173.19:55:40.75/k5log//k5ts2_log_newline 2006.173.19:55:41.48/k5log//k5ts3_log_newline 2006.173.19:55:42.18/k5log//k5ts4_log_newline 2006.173.19:55:42.20/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.19:55:42.20:setupk4=1 2006.173.19:55:42.21$setupk4/echo=on 2006.173.19:55:42.21$setupk4/pcalon 2006.173.19:55:42.21$pcalon/"no phase cal control is implemented here 2006.173.19:55:42.21$setupk4/"tpicd=stop 2006.173.19:55:42.21$setupk4/"rec=synch_on 2006.173.19:55:42.21$setupk4/"rec_mode=128 2006.173.19:55:42.21$setupk4/!* 2006.173.19:55:42.21$setupk4/recpk4 2006.173.19:55:42.21$recpk4/recpatch= 2006.173.19:55:42.21$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.19:55:42.21$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.19:55:42.21$setupk4/vck44 2006.173.19:55:42.21$vck44/valo=1,524.99 2006.173.19:55:42.21#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.19:55:42.21#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.19:55:42.21#ibcon#ireg 17 cls_cnt 0 2006.173.19:55:42.21#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.19:55:42.21#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.19:55:42.21#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.19:55:42.21#ibcon#enter wrdev, iclass 35, count 0 2006.173.19:55:42.21#ibcon#first serial, iclass 35, count 0 2006.173.19:55:42.21#ibcon#enter sib2, iclass 35, count 0 2006.173.19:55:42.22#ibcon#flushed, iclass 35, count 0 2006.173.19:55:42.22#ibcon#about to write, iclass 35, count 0 2006.173.19:55:42.22#ibcon#wrote, iclass 35, count 0 2006.173.19:55:42.22#ibcon#about to read 3, iclass 35, count 0 2006.173.19:55:42.23#ibcon#read 3, iclass 35, count 0 2006.173.19:55:42.23#ibcon#about to read 4, iclass 35, count 0 2006.173.19:55:42.23#ibcon#read 4, iclass 35, count 0 2006.173.19:55:42.23#ibcon#about to read 5, iclass 35, count 0 2006.173.19:55:42.23#ibcon#read 5, iclass 35, count 0 2006.173.19:55:42.23#ibcon#about to read 6, iclass 35, count 0 2006.173.19:55:42.23#ibcon#read 6, iclass 35, count 0 2006.173.19:55:42.23#ibcon#end of sib2, iclass 35, count 0 2006.173.19:55:42.23#ibcon#*mode == 0, iclass 35, count 0 2006.173.19:55:42.23#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.19:55:42.23#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.19:55:42.23#ibcon#*before write, iclass 35, count 0 2006.173.19:55:42.23#ibcon#enter sib2, iclass 35, count 0 2006.173.19:55:42.23#ibcon#flushed, iclass 35, count 0 2006.173.19:55:42.23#ibcon#about to write, iclass 35, count 0 2006.173.19:55:42.23#ibcon#wrote, iclass 35, count 0 2006.173.19:55:42.23#ibcon#about to read 3, iclass 35, count 0 2006.173.19:55:42.28#ibcon#read 3, iclass 35, count 0 2006.173.19:55:42.28#ibcon#about to read 4, iclass 35, count 0 2006.173.19:55:42.28#ibcon#read 4, iclass 35, count 0 2006.173.19:55:42.28#ibcon#about to read 5, iclass 35, count 0 2006.173.19:55:42.28#ibcon#read 5, iclass 35, count 0 2006.173.19:55:42.28#ibcon#about to read 6, iclass 35, count 0 2006.173.19:55:42.28#ibcon#read 6, iclass 35, count 0 2006.173.19:55:42.28#ibcon#end of sib2, iclass 35, count 0 2006.173.19:55:42.28#ibcon#*after write, iclass 35, count 0 2006.173.19:55:42.28#ibcon#*before return 0, iclass 35, count 0 2006.173.19:55:42.28#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.19:55:42.28#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.19:55:42.28#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.19:55:42.28#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.19:55:42.28$vck44/va=1,7 2006.173.19:55:42.28#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.173.19:55:42.28#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.173.19:55:42.28#ibcon#ireg 11 cls_cnt 2 2006.173.19:55:42.28#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.19:55:42.28#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.19:55:42.28#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.19:55:42.28#ibcon#enter wrdev, iclass 37, count 2 2006.173.19:55:42.28#ibcon#first serial, iclass 37, count 2 2006.173.19:55:42.28#ibcon#enter sib2, iclass 37, count 2 2006.173.19:55:42.28#ibcon#flushed, iclass 37, count 2 2006.173.19:55:42.28#ibcon#about to write, iclass 37, count 2 2006.173.19:55:42.28#ibcon#wrote, iclass 37, count 2 2006.173.19:55:42.28#ibcon#about to read 3, iclass 37, count 2 2006.173.19:55:42.30#ibcon#read 3, iclass 37, count 2 2006.173.19:55:42.30#ibcon#about to read 4, iclass 37, count 2 2006.173.19:55:42.30#ibcon#read 4, iclass 37, count 2 2006.173.19:55:42.30#ibcon#about to read 5, iclass 37, count 2 2006.173.19:55:42.30#ibcon#read 5, iclass 37, count 2 2006.173.19:55:42.30#ibcon#about to read 6, iclass 37, count 2 2006.173.19:55:42.30#ibcon#read 6, iclass 37, count 2 2006.173.19:55:42.30#ibcon#end of sib2, iclass 37, count 2 2006.173.19:55:42.30#ibcon#*mode == 0, iclass 37, count 2 2006.173.19:55:42.30#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.173.19:55:42.30#ibcon#[25=AT01-07\r\n] 2006.173.19:55:42.30#ibcon#*before write, iclass 37, count 2 2006.173.19:55:42.30#ibcon#enter sib2, iclass 37, count 2 2006.173.19:55:42.30#ibcon#flushed, iclass 37, count 2 2006.173.19:55:42.30#ibcon#about to write, iclass 37, count 2 2006.173.19:55:42.30#ibcon#wrote, iclass 37, count 2 2006.173.19:55:42.30#ibcon#about to read 3, iclass 37, count 2 2006.173.19:55:42.33#ibcon#read 3, iclass 37, count 2 2006.173.19:55:42.33#ibcon#about to read 4, iclass 37, count 2 2006.173.19:55:42.33#ibcon#read 4, iclass 37, count 2 2006.173.19:55:42.33#ibcon#about to read 5, iclass 37, count 2 2006.173.19:55:42.33#ibcon#read 5, iclass 37, count 2 2006.173.19:55:42.33#ibcon#about to read 6, iclass 37, count 2 2006.173.19:55:42.33#ibcon#read 6, iclass 37, count 2 2006.173.19:55:42.33#ibcon#end of sib2, iclass 37, count 2 2006.173.19:55:42.33#ibcon#*after write, iclass 37, count 2 2006.173.19:55:42.33#ibcon#*before return 0, iclass 37, count 2 2006.173.19:55:42.33#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.19:55:42.33#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.173.19:55:42.33#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.173.19:55:42.33#ibcon#ireg 7 cls_cnt 0 2006.173.19:55:42.33#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.19:55:42.45#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.19:55:42.45#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.19:55:42.45#ibcon#enter wrdev, iclass 37, count 0 2006.173.19:55:42.45#ibcon#first serial, iclass 37, count 0 2006.173.19:55:42.45#ibcon#enter sib2, iclass 37, count 0 2006.173.19:55:42.45#ibcon#flushed, iclass 37, count 0 2006.173.19:55:42.45#ibcon#about to write, iclass 37, count 0 2006.173.19:55:42.45#ibcon#wrote, iclass 37, count 0 2006.173.19:55:42.45#ibcon#about to read 3, iclass 37, count 0 2006.173.19:55:42.47#ibcon#read 3, iclass 37, count 0 2006.173.19:55:42.47#ibcon#about to read 4, iclass 37, count 0 2006.173.19:55:42.47#ibcon#read 4, iclass 37, count 0 2006.173.19:55:42.47#ibcon#about to read 5, iclass 37, count 0 2006.173.19:55:42.47#ibcon#read 5, iclass 37, count 0 2006.173.19:55:42.47#ibcon#about to read 6, iclass 37, count 0 2006.173.19:55:42.47#ibcon#read 6, iclass 37, count 0 2006.173.19:55:42.47#ibcon#end of sib2, iclass 37, count 0 2006.173.19:55:42.47#ibcon#*mode == 0, iclass 37, count 0 2006.173.19:55:42.47#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.19:55:42.47#ibcon#[25=USB\r\n] 2006.173.19:55:42.47#ibcon#*before write, iclass 37, count 0 2006.173.19:55:42.47#ibcon#enter sib2, iclass 37, count 0 2006.173.19:55:42.47#ibcon#flushed, iclass 37, count 0 2006.173.19:55:42.47#ibcon#about to write, iclass 37, count 0 2006.173.19:55:42.47#ibcon#wrote, iclass 37, count 0 2006.173.19:55:42.47#ibcon#about to read 3, iclass 37, count 0 2006.173.19:55:42.50#ibcon#read 3, iclass 37, count 0 2006.173.19:55:42.50#ibcon#about to read 4, iclass 37, count 0 2006.173.19:55:42.50#ibcon#read 4, iclass 37, count 0 2006.173.19:55:42.50#ibcon#about to read 5, iclass 37, count 0 2006.173.19:55:42.50#ibcon#read 5, iclass 37, count 0 2006.173.19:55:42.50#ibcon#about to read 6, iclass 37, count 0 2006.173.19:55:42.50#ibcon#read 6, iclass 37, count 0 2006.173.19:55:42.50#ibcon#end of sib2, iclass 37, count 0 2006.173.19:55:42.50#ibcon#*after write, iclass 37, count 0 2006.173.19:55:42.50#ibcon#*before return 0, iclass 37, count 0 2006.173.19:55:42.50#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.19:55:42.50#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.173.19:55:42.50#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.19:55:42.50#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.19:55:42.50$vck44/valo=2,534.99 2006.173.19:55:42.50#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.19:55:42.50#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.19:55:42.50#ibcon#ireg 17 cls_cnt 0 2006.173.19:55:42.50#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.19:55:42.50#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.19:55:42.50#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.19:55:42.50#ibcon#enter wrdev, iclass 39, count 0 2006.173.19:55:42.50#ibcon#first serial, iclass 39, count 0 2006.173.19:55:42.50#ibcon#enter sib2, iclass 39, count 0 2006.173.19:55:42.50#ibcon#flushed, iclass 39, count 0 2006.173.19:55:42.50#ibcon#about to write, iclass 39, count 0 2006.173.19:55:42.50#ibcon#wrote, iclass 39, count 0 2006.173.19:55:42.50#ibcon#about to read 3, iclass 39, count 0 2006.173.19:55:42.52#ibcon#read 3, iclass 39, count 0 2006.173.19:55:42.52#ibcon#about to read 4, iclass 39, count 0 2006.173.19:55:42.52#ibcon#read 4, iclass 39, count 0 2006.173.19:55:42.52#ibcon#about to read 5, iclass 39, count 0 2006.173.19:55:42.52#ibcon#read 5, iclass 39, count 0 2006.173.19:55:42.52#ibcon#about to read 6, iclass 39, count 0 2006.173.19:55:42.52#ibcon#read 6, iclass 39, count 0 2006.173.19:55:42.52#ibcon#end of sib2, iclass 39, count 0 2006.173.19:55:42.52#ibcon#*mode == 0, iclass 39, count 0 2006.173.19:55:42.52#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.19:55:42.52#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.19:55:42.52#ibcon#*before write, iclass 39, count 0 2006.173.19:55:42.52#ibcon#enter sib2, iclass 39, count 0 2006.173.19:55:42.52#ibcon#flushed, iclass 39, count 0 2006.173.19:55:42.52#ibcon#about to write, iclass 39, count 0 2006.173.19:55:42.52#ibcon#wrote, iclass 39, count 0 2006.173.19:55:42.52#ibcon#about to read 3, iclass 39, count 0 2006.173.19:55:42.56#ibcon#read 3, iclass 39, count 0 2006.173.19:55:42.56#ibcon#about to read 4, iclass 39, count 0 2006.173.19:55:42.56#ibcon#read 4, iclass 39, count 0 2006.173.19:55:42.56#ibcon#about to read 5, iclass 39, count 0 2006.173.19:55:42.56#ibcon#read 5, iclass 39, count 0 2006.173.19:55:42.56#ibcon#about to read 6, iclass 39, count 0 2006.173.19:55:42.56#ibcon#read 6, iclass 39, count 0 2006.173.19:55:42.56#ibcon#end of sib2, iclass 39, count 0 2006.173.19:55:42.56#ibcon#*after write, iclass 39, count 0 2006.173.19:55:42.56#ibcon#*before return 0, iclass 39, count 0 2006.173.19:55:42.56#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.19:55:42.56#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.19:55:42.56#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.19:55:42.56#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.19:55:42.56$vck44/va=2,6 2006.173.19:55:42.56#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.19:55:42.56#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.19:55:42.56#ibcon#ireg 11 cls_cnt 2 2006.173.19:55:42.56#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.19:55:42.62#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.19:55:42.62#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.19:55:42.62#ibcon#enter wrdev, iclass 3, count 2 2006.173.19:55:42.62#ibcon#first serial, iclass 3, count 2 2006.173.19:55:42.62#ibcon#enter sib2, iclass 3, count 2 2006.173.19:55:42.62#ibcon#flushed, iclass 3, count 2 2006.173.19:55:42.62#ibcon#about to write, iclass 3, count 2 2006.173.19:55:42.62#ibcon#wrote, iclass 3, count 2 2006.173.19:55:42.62#ibcon#about to read 3, iclass 3, count 2 2006.173.19:55:42.64#ibcon#read 3, iclass 3, count 2 2006.173.19:55:42.64#ibcon#about to read 4, iclass 3, count 2 2006.173.19:55:42.64#ibcon#read 4, iclass 3, count 2 2006.173.19:55:42.64#ibcon#about to read 5, iclass 3, count 2 2006.173.19:55:42.64#ibcon#read 5, iclass 3, count 2 2006.173.19:55:42.64#ibcon#about to read 6, iclass 3, count 2 2006.173.19:55:42.64#ibcon#read 6, iclass 3, count 2 2006.173.19:55:42.64#ibcon#end of sib2, iclass 3, count 2 2006.173.19:55:42.64#ibcon#*mode == 0, iclass 3, count 2 2006.173.19:55:42.64#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.19:55:42.64#ibcon#[25=AT02-06\r\n] 2006.173.19:55:42.64#ibcon#*before write, iclass 3, count 2 2006.173.19:55:42.64#ibcon#enter sib2, iclass 3, count 2 2006.173.19:55:42.64#ibcon#flushed, iclass 3, count 2 2006.173.19:55:42.64#ibcon#about to write, iclass 3, count 2 2006.173.19:55:42.64#ibcon#wrote, iclass 3, count 2 2006.173.19:55:42.64#ibcon#about to read 3, iclass 3, count 2 2006.173.19:55:42.67#ibcon#read 3, iclass 3, count 2 2006.173.19:55:42.67#ibcon#about to read 4, iclass 3, count 2 2006.173.19:55:42.67#ibcon#read 4, iclass 3, count 2 2006.173.19:55:42.67#ibcon#about to read 5, iclass 3, count 2 2006.173.19:55:42.67#ibcon#read 5, iclass 3, count 2 2006.173.19:55:42.67#ibcon#about to read 6, iclass 3, count 2 2006.173.19:55:42.67#ibcon#read 6, iclass 3, count 2 2006.173.19:55:42.67#ibcon#end of sib2, iclass 3, count 2 2006.173.19:55:42.67#ibcon#*after write, iclass 3, count 2 2006.173.19:55:42.67#ibcon#*before return 0, iclass 3, count 2 2006.173.19:55:42.67#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.19:55:42.67#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.19:55:42.67#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.19:55:42.67#ibcon#ireg 7 cls_cnt 0 2006.173.19:55:42.67#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.19:55:42.70#abcon#<5=/06 0.7 1.2 19.291001002.6\r\n> 2006.173.19:55:42.72#abcon#{5=INTERFACE CLEAR} 2006.173.19:55:42.78#abcon#[5=S1D000X0/0*\r\n] 2006.173.19:55:42.79#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.19:55:42.79#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.19:55:42.79#ibcon#enter wrdev, iclass 3, count 0 2006.173.19:55:42.79#ibcon#first serial, iclass 3, count 0 2006.173.19:55:42.79#ibcon#enter sib2, iclass 3, count 0 2006.173.19:55:42.79#ibcon#flushed, iclass 3, count 0 2006.173.19:55:42.79#ibcon#about to write, iclass 3, count 0 2006.173.19:55:42.79#ibcon#wrote, iclass 3, count 0 2006.173.19:55:42.79#ibcon#about to read 3, iclass 3, count 0 2006.173.19:55:42.81#ibcon#read 3, iclass 3, count 0 2006.173.19:55:42.81#ibcon#about to read 4, iclass 3, count 0 2006.173.19:55:42.81#ibcon#read 4, iclass 3, count 0 2006.173.19:55:42.81#ibcon#about to read 5, iclass 3, count 0 2006.173.19:55:42.81#ibcon#read 5, iclass 3, count 0 2006.173.19:55:42.81#ibcon#about to read 6, iclass 3, count 0 2006.173.19:55:42.81#ibcon#read 6, iclass 3, count 0 2006.173.19:55:42.81#ibcon#end of sib2, iclass 3, count 0 2006.173.19:55:42.81#ibcon#*mode == 0, iclass 3, count 0 2006.173.19:55:42.81#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.19:55:42.81#ibcon#[25=USB\r\n] 2006.173.19:55:42.81#ibcon#*before write, iclass 3, count 0 2006.173.19:55:42.81#ibcon#enter sib2, iclass 3, count 0 2006.173.19:55:42.81#ibcon#flushed, iclass 3, count 0 2006.173.19:55:42.81#ibcon#about to write, iclass 3, count 0 2006.173.19:55:42.81#ibcon#wrote, iclass 3, count 0 2006.173.19:55:42.81#ibcon#about to read 3, iclass 3, count 0 2006.173.19:55:42.84#ibcon#read 3, iclass 3, count 0 2006.173.19:55:42.84#ibcon#about to read 4, iclass 3, count 0 2006.173.19:55:42.84#ibcon#read 4, iclass 3, count 0 2006.173.19:55:42.84#ibcon#about to read 5, iclass 3, count 0 2006.173.19:55:42.84#ibcon#read 5, iclass 3, count 0 2006.173.19:55:42.84#ibcon#about to read 6, iclass 3, count 0 2006.173.19:55:42.84#ibcon#read 6, iclass 3, count 0 2006.173.19:55:42.84#ibcon#end of sib2, iclass 3, count 0 2006.173.19:55:42.84#ibcon#*after write, iclass 3, count 0 2006.173.19:55:42.84#ibcon#*before return 0, iclass 3, count 0 2006.173.19:55:42.84#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.19:55:42.84#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.19:55:42.84#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.19:55:42.84#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.19:55:42.84$vck44/valo=3,564.99 2006.173.19:55:42.84#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.19:55:42.84#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.19:55:42.84#ibcon#ireg 17 cls_cnt 0 2006.173.19:55:42.84#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.19:55:42.84#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.19:55:42.84#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.19:55:42.84#ibcon#enter wrdev, iclass 11, count 0 2006.173.19:55:42.84#ibcon#first serial, iclass 11, count 0 2006.173.19:55:42.84#ibcon#enter sib2, iclass 11, count 0 2006.173.19:55:42.84#ibcon#flushed, iclass 11, count 0 2006.173.19:55:42.84#ibcon#about to write, iclass 11, count 0 2006.173.19:55:42.84#ibcon#wrote, iclass 11, count 0 2006.173.19:55:42.84#ibcon#about to read 3, iclass 11, count 0 2006.173.19:55:42.86#ibcon#read 3, iclass 11, count 0 2006.173.19:55:42.86#ibcon#about to read 4, iclass 11, count 0 2006.173.19:55:42.86#ibcon#read 4, iclass 11, count 0 2006.173.19:55:42.86#ibcon#about to read 5, iclass 11, count 0 2006.173.19:55:42.86#ibcon#read 5, iclass 11, count 0 2006.173.19:55:42.86#ibcon#about to read 6, iclass 11, count 0 2006.173.19:55:42.86#ibcon#read 6, iclass 11, count 0 2006.173.19:55:42.86#ibcon#end of sib2, iclass 11, count 0 2006.173.19:55:42.86#ibcon#*mode == 0, iclass 11, count 0 2006.173.19:55:42.86#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.19:55:42.86#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.19:55:42.86#ibcon#*before write, iclass 11, count 0 2006.173.19:55:42.86#ibcon#enter sib2, iclass 11, count 0 2006.173.19:55:42.86#ibcon#flushed, iclass 11, count 0 2006.173.19:55:42.86#ibcon#about to write, iclass 11, count 0 2006.173.19:55:42.86#ibcon#wrote, iclass 11, count 0 2006.173.19:55:42.86#ibcon#about to read 3, iclass 11, count 0 2006.173.19:55:42.90#ibcon#read 3, iclass 11, count 0 2006.173.19:55:42.90#ibcon#about to read 4, iclass 11, count 0 2006.173.19:55:42.90#ibcon#read 4, iclass 11, count 0 2006.173.19:55:42.90#ibcon#about to read 5, iclass 11, count 0 2006.173.19:55:42.90#ibcon#read 5, iclass 11, count 0 2006.173.19:55:42.90#ibcon#about to read 6, iclass 11, count 0 2006.173.19:55:42.90#ibcon#read 6, iclass 11, count 0 2006.173.19:55:42.90#ibcon#end of sib2, iclass 11, count 0 2006.173.19:55:42.90#ibcon#*after write, iclass 11, count 0 2006.173.19:55:42.90#ibcon#*before return 0, iclass 11, count 0 2006.173.19:55:42.90#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.19:55:42.90#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.19:55:42.90#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.19:55:42.90#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.19:55:42.90$vck44/va=3,5 2006.173.19:55:42.90#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.173.19:55:42.90#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.173.19:55:42.90#ibcon#ireg 11 cls_cnt 2 2006.173.19:55:42.90#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.19:55:42.96#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.19:55:42.96#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.19:55:42.96#ibcon#enter wrdev, iclass 13, count 2 2006.173.19:55:42.96#ibcon#first serial, iclass 13, count 2 2006.173.19:55:42.96#ibcon#enter sib2, iclass 13, count 2 2006.173.19:55:42.96#ibcon#flushed, iclass 13, count 2 2006.173.19:55:42.96#ibcon#about to write, iclass 13, count 2 2006.173.19:55:42.96#ibcon#wrote, iclass 13, count 2 2006.173.19:55:42.96#ibcon#about to read 3, iclass 13, count 2 2006.173.19:55:42.98#ibcon#read 3, iclass 13, count 2 2006.173.19:55:42.98#ibcon#about to read 4, iclass 13, count 2 2006.173.19:55:42.98#ibcon#read 4, iclass 13, count 2 2006.173.19:55:42.98#ibcon#about to read 5, iclass 13, count 2 2006.173.19:55:42.98#ibcon#read 5, iclass 13, count 2 2006.173.19:55:42.98#ibcon#about to read 6, iclass 13, count 2 2006.173.19:55:42.98#ibcon#read 6, iclass 13, count 2 2006.173.19:55:42.98#ibcon#end of sib2, iclass 13, count 2 2006.173.19:55:42.98#ibcon#*mode == 0, iclass 13, count 2 2006.173.19:55:42.98#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.173.19:55:42.98#ibcon#[25=AT03-05\r\n] 2006.173.19:55:42.98#ibcon#*before write, iclass 13, count 2 2006.173.19:55:42.98#ibcon#enter sib2, iclass 13, count 2 2006.173.19:55:42.98#ibcon#flushed, iclass 13, count 2 2006.173.19:55:42.98#ibcon#about to write, iclass 13, count 2 2006.173.19:55:42.98#ibcon#wrote, iclass 13, count 2 2006.173.19:55:42.98#ibcon#about to read 3, iclass 13, count 2 2006.173.19:55:43.01#ibcon#read 3, iclass 13, count 2 2006.173.19:55:43.01#ibcon#about to read 4, iclass 13, count 2 2006.173.19:55:43.01#ibcon#read 4, iclass 13, count 2 2006.173.19:55:43.01#ibcon#about to read 5, iclass 13, count 2 2006.173.19:55:43.01#ibcon#read 5, iclass 13, count 2 2006.173.19:55:43.01#ibcon#about to read 6, iclass 13, count 2 2006.173.19:55:43.01#ibcon#read 6, iclass 13, count 2 2006.173.19:55:43.01#ibcon#end of sib2, iclass 13, count 2 2006.173.19:55:43.01#ibcon#*after write, iclass 13, count 2 2006.173.19:55:43.01#ibcon#*before return 0, iclass 13, count 2 2006.173.19:55:43.01#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.19:55:43.01#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.173.19:55:43.01#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.173.19:55:43.01#ibcon#ireg 7 cls_cnt 0 2006.173.19:55:43.01#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.19:55:43.13#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.19:55:43.13#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.19:55:43.13#ibcon#enter wrdev, iclass 13, count 0 2006.173.19:55:43.13#ibcon#first serial, iclass 13, count 0 2006.173.19:55:43.13#ibcon#enter sib2, iclass 13, count 0 2006.173.19:55:43.13#ibcon#flushed, iclass 13, count 0 2006.173.19:55:43.13#ibcon#about to write, iclass 13, count 0 2006.173.19:55:43.13#ibcon#wrote, iclass 13, count 0 2006.173.19:55:43.13#ibcon#about to read 3, iclass 13, count 0 2006.173.19:55:43.15#ibcon#read 3, iclass 13, count 0 2006.173.19:55:43.15#ibcon#about to read 4, iclass 13, count 0 2006.173.19:55:43.15#ibcon#read 4, iclass 13, count 0 2006.173.19:55:43.15#ibcon#about to read 5, iclass 13, count 0 2006.173.19:55:43.15#ibcon#read 5, iclass 13, count 0 2006.173.19:55:43.15#ibcon#about to read 6, iclass 13, count 0 2006.173.19:55:43.15#ibcon#read 6, iclass 13, count 0 2006.173.19:55:43.15#ibcon#end of sib2, iclass 13, count 0 2006.173.19:55:43.15#ibcon#*mode == 0, iclass 13, count 0 2006.173.19:55:43.15#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.19:55:43.15#ibcon#[25=USB\r\n] 2006.173.19:55:43.15#ibcon#*before write, iclass 13, count 0 2006.173.19:55:43.15#ibcon#enter sib2, iclass 13, count 0 2006.173.19:55:43.15#ibcon#flushed, iclass 13, count 0 2006.173.19:55:43.15#ibcon#about to write, iclass 13, count 0 2006.173.19:55:43.15#ibcon#wrote, iclass 13, count 0 2006.173.19:55:43.15#ibcon#about to read 3, iclass 13, count 0 2006.173.19:55:43.18#ibcon#read 3, iclass 13, count 0 2006.173.19:55:43.18#ibcon#about to read 4, iclass 13, count 0 2006.173.19:55:43.18#ibcon#read 4, iclass 13, count 0 2006.173.19:55:43.18#ibcon#about to read 5, iclass 13, count 0 2006.173.19:55:43.18#ibcon#read 5, iclass 13, count 0 2006.173.19:55:43.18#ibcon#about to read 6, iclass 13, count 0 2006.173.19:55:43.18#ibcon#read 6, iclass 13, count 0 2006.173.19:55:43.18#ibcon#end of sib2, iclass 13, count 0 2006.173.19:55:43.18#ibcon#*after write, iclass 13, count 0 2006.173.19:55:43.18#ibcon#*before return 0, iclass 13, count 0 2006.173.19:55:43.18#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.19:55:43.19#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.173.19:55:43.19#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.19:55:43.19#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.19:55:43.19$vck44/valo=4,624.99 2006.173.19:55:43.19#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.19:55:43.19#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.19:55:43.19#ibcon#ireg 17 cls_cnt 0 2006.173.19:55:43.19#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.19:55:43.19#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.19:55:43.19#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.19:55:43.19#ibcon#enter wrdev, iclass 15, count 0 2006.173.19:55:43.19#ibcon#first serial, iclass 15, count 0 2006.173.19:55:43.19#ibcon#enter sib2, iclass 15, count 0 2006.173.19:55:43.19#ibcon#flushed, iclass 15, count 0 2006.173.19:55:43.19#ibcon#about to write, iclass 15, count 0 2006.173.19:55:43.19#ibcon#wrote, iclass 15, count 0 2006.173.19:55:43.19#ibcon#about to read 3, iclass 15, count 0 2006.173.19:55:43.20#ibcon#read 3, iclass 15, count 0 2006.173.19:55:43.20#ibcon#about to read 4, iclass 15, count 0 2006.173.19:55:43.20#ibcon#read 4, iclass 15, count 0 2006.173.19:55:43.20#ibcon#about to read 5, iclass 15, count 0 2006.173.19:55:43.20#ibcon#read 5, iclass 15, count 0 2006.173.19:55:43.20#ibcon#about to read 6, iclass 15, count 0 2006.173.19:55:43.20#ibcon#read 6, iclass 15, count 0 2006.173.19:55:43.20#ibcon#end of sib2, iclass 15, count 0 2006.173.19:55:43.20#ibcon#*mode == 0, iclass 15, count 0 2006.173.19:55:43.20#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.19:55:43.20#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.19:55:43.20#ibcon#*before write, iclass 15, count 0 2006.173.19:55:43.20#ibcon#enter sib2, iclass 15, count 0 2006.173.19:55:43.20#ibcon#flushed, iclass 15, count 0 2006.173.19:55:43.20#ibcon#about to write, iclass 15, count 0 2006.173.19:55:43.20#ibcon#wrote, iclass 15, count 0 2006.173.19:55:43.20#ibcon#about to read 3, iclass 15, count 0 2006.173.19:55:43.24#ibcon#read 3, iclass 15, count 0 2006.173.19:55:43.24#ibcon#about to read 4, iclass 15, count 0 2006.173.19:55:43.24#ibcon#read 4, iclass 15, count 0 2006.173.19:55:43.24#ibcon#about to read 5, iclass 15, count 0 2006.173.19:55:43.24#ibcon#read 5, iclass 15, count 0 2006.173.19:55:43.24#ibcon#about to read 6, iclass 15, count 0 2006.173.19:55:43.24#ibcon#read 6, iclass 15, count 0 2006.173.19:55:43.24#ibcon#end of sib2, iclass 15, count 0 2006.173.19:55:43.24#ibcon#*after write, iclass 15, count 0 2006.173.19:55:43.24#ibcon#*before return 0, iclass 15, count 0 2006.173.19:55:43.24#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.19:55:43.24#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.19:55:43.24#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.19:55:43.24#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.19:55:43.24$vck44/va=4,6 2006.173.19:55:43.24#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.19:55:43.24#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.19:55:43.24#ibcon#ireg 11 cls_cnt 2 2006.173.19:55:43.24#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.19:55:43.31#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.19:55:43.31#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.19:55:43.31#ibcon#enter wrdev, iclass 17, count 2 2006.173.19:55:43.31#ibcon#first serial, iclass 17, count 2 2006.173.19:55:43.31#ibcon#enter sib2, iclass 17, count 2 2006.173.19:55:43.31#ibcon#flushed, iclass 17, count 2 2006.173.19:55:43.31#ibcon#about to write, iclass 17, count 2 2006.173.19:55:43.31#ibcon#wrote, iclass 17, count 2 2006.173.19:55:43.31#ibcon#about to read 3, iclass 17, count 2 2006.173.19:55:43.33#ibcon#read 3, iclass 17, count 2 2006.173.19:55:43.33#ibcon#about to read 4, iclass 17, count 2 2006.173.19:55:43.33#ibcon#read 4, iclass 17, count 2 2006.173.19:55:43.33#ibcon#about to read 5, iclass 17, count 2 2006.173.19:55:43.33#ibcon#read 5, iclass 17, count 2 2006.173.19:55:43.33#ibcon#about to read 6, iclass 17, count 2 2006.173.19:55:43.33#ibcon#read 6, iclass 17, count 2 2006.173.19:55:43.33#ibcon#end of sib2, iclass 17, count 2 2006.173.19:55:43.33#ibcon#*mode == 0, iclass 17, count 2 2006.173.19:55:43.33#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.19:55:43.33#ibcon#[25=AT04-06\r\n] 2006.173.19:55:43.33#ibcon#*before write, iclass 17, count 2 2006.173.19:55:43.33#ibcon#enter sib2, iclass 17, count 2 2006.173.19:55:43.33#ibcon#flushed, iclass 17, count 2 2006.173.19:55:43.33#ibcon#about to write, iclass 17, count 2 2006.173.19:55:43.33#ibcon#wrote, iclass 17, count 2 2006.173.19:55:43.33#ibcon#about to read 3, iclass 17, count 2 2006.173.19:55:43.36#ibcon#read 3, iclass 17, count 2 2006.173.19:55:43.36#ibcon#about to read 4, iclass 17, count 2 2006.173.19:55:43.36#ibcon#read 4, iclass 17, count 2 2006.173.19:55:43.36#ibcon#about to read 5, iclass 17, count 2 2006.173.19:55:43.36#ibcon#read 5, iclass 17, count 2 2006.173.19:55:43.36#ibcon#about to read 6, iclass 17, count 2 2006.173.19:55:43.36#ibcon#read 6, iclass 17, count 2 2006.173.19:55:43.36#ibcon#end of sib2, iclass 17, count 2 2006.173.19:55:43.36#ibcon#*after write, iclass 17, count 2 2006.173.19:55:43.36#ibcon#*before return 0, iclass 17, count 2 2006.173.19:55:43.36#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.19:55:43.36#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.19:55:43.36#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.19:55:43.36#ibcon#ireg 7 cls_cnt 0 2006.173.19:55:43.36#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.19:55:43.48#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.19:55:43.48#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.19:55:43.48#ibcon#enter wrdev, iclass 17, count 0 2006.173.19:55:43.48#ibcon#first serial, iclass 17, count 0 2006.173.19:55:43.48#ibcon#enter sib2, iclass 17, count 0 2006.173.19:55:43.48#ibcon#flushed, iclass 17, count 0 2006.173.19:55:43.48#ibcon#about to write, iclass 17, count 0 2006.173.19:55:43.48#ibcon#wrote, iclass 17, count 0 2006.173.19:55:43.48#ibcon#about to read 3, iclass 17, count 0 2006.173.19:55:43.50#ibcon#read 3, iclass 17, count 0 2006.173.19:55:43.50#ibcon#about to read 4, iclass 17, count 0 2006.173.19:55:43.50#ibcon#read 4, iclass 17, count 0 2006.173.19:55:43.50#ibcon#about to read 5, iclass 17, count 0 2006.173.19:55:43.50#ibcon#read 5, iclass 17, count 0 2006.173.19:55:43.50#ibcon#about to read 6, iclass 17, count 0 2006.173.19:55:43.50#ibcon#read 6, iclass 17, count 0 2006.173.19:55:43.50#ibcon#end of sib2, iclass 17, count 0 2006.173.19:55:43.50#ibcon#*mode == 0, iclass 17, count 0 2006.173.19:55:43.50#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.19:55:43.50#ibcon#[25=USB\r\n] 2006.173.19:55:43.50#ibcon#*before write, iclass 17, count 0 2006.173.19:55:43.50#ibcon#enter sib2, iclass 17, count 0 2006.173.19:55:43.50#ibcon#flushed, iclass 17, count 0 2006.173.19:55:43.50#ibcon#about to write, iclass 17, count 0 2006.173.19:55:43.50#ibcon#wrote, iclass 17, count 0 2006.173.19:55:43.50#ibcon#about to read 3, iclass 17, count 0 2006.173.19:55:43.53#ibcon#read 3, iclass 17, count 0 2006.173.19:55:43.53#ibcon#about to read 4, iclass 17, count 0 2006.173.19:55:43.53#ibcon#read 4, iclass 17, count 0 2006.173.19:55:43.53#ibcon#about to read 5, iclass 17, count 0 2006.173.19:55:43.53#ibcon#read 5, iclass 17, count 0 2006.173.19:55:43.53#ibcon#about to read 6, iclass 17, count 0 2006.173.19:55:43.53#ibcon#read 6, iclass 17, count 0 2006.173.19:55:43.53#ibcon#end of sib2, iclass 17, count 0 2006.173.19:55:43.53#ibcon#*after write, iclass 17, count 0 2006.173.19:55:43.53#ibcon#*before return 0, iclass 17, count 0 2006.173.19:55:43.53#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.19:55:43.53#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.19:55:43.53#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.19:55:43.53#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.19:55:43.53$vck44/valo=5,734.99 2006.173.19:55:43.53#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.19:55:43.53#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.19:55:43.53#ibcon#ireg 17 cls_cnt 0 2006.173.19:55:43.53#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.19:55:43.53#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.19:55:43.53#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.19:55:43.53#ibcon#enter wrdev, iclass 19, count 0 2006.173.19:55:43.53#ibcon#first serial, iclass 19, count 0 2006.173.19:55:43.53#ibcon#enter sib2, iclass 19, count 0 2006.173.19:55:43.53#ibcon#flushed, iclass 19, count 0 2006.173.19:55:43.53#ibcon#about to write, iclass 19, count 0 2006.173.19:55:43.53#ibcon#wrote, iclass 19, count 0 2006.173.19:55:43.53#ibcon#about to read 3, iclass 19, count 0 2006.173.19:55:43.55#ibcon#read 3, iclass 19, count 0 2006.173.19:55:43.55#ibcon#about to read 4, iclass 19, count 0 2006.173.19:55:43.55#ibcon#read 4, iclass 19, count 0 2006.173.19:55:43.55#ibcon#about to read 5, iclass 19, count 0 2006.173.19:55:43.55#ibcon#read 5, iclass 19, count 0 2006.173.19:55:43.55#ibcon#about to read 6, iclass 19, count 0 2006.173.19:55:43.55#ibcon#read 6, iclass 19, count 0 2006.173.19:55:43.55#ibcon#end of sib2, iclass 19, count 0 2006.173.19:55:43.55#ibcon#*mode == 0, iclass 19, count 0 2006.173.19:55:43.55#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.19:55:43.55#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.19:55:43.55#ibcon#*before write, iclass 19, count 0 2006.173.19:55:43.55#ibcon#enter sib2, iclass 19, count 0 2006.173.19:55:43.55#ibcon#flushed, iclass 19, count 0 2006.173.19:55:43.55#ibcon#about to write, iclass 19, count 0 2006.173.19:55:43.55#ibcon#wrote, iclass 19, count 0 2006.173.19:55:43.55#ibcon#about to read 3, iclass 19, count 0 2006.173.19:55:43.59#ibcon#read 3, iclass 19, count 0 2006.173.19:55:43.59#ibcon#about to read 4, iclass 19, count 0 2006.173.19:55:43.59#ibcon#read 4, iclass 19, count 0 2006.173.19:55:43.59#ibcon#about to read 5, iclass 19, count 0 2006.173.19:55:43.59#ibcon#read 5, iclass 19, count 0 2006.173.19:55:43.59#ibcon#about to read 6, iclass 19, count 0 2006.173.19:55:43.59#ibcon#read 6, iclass 19, count 0 2006.173.19:55:43.59#ibcon#end of sib2, iclass 19, count 0 2006.173.19:55:43.59#ibcon#*after write, iclass 19, count 0 2006.173.19:55:43.59#ibcon#*before return 0, iclass 19, count 0 2006.173.19:55:43.59#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.19:55:43.59#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.19:55:43.59#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.19:55:43.59#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.19:55:43.59$vck44/va=5,4 2006.173.19:55:43.59#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.19:55:43.59#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.19:55:43.59#ibcon#ireg 11 cls_cnt 2 2006.173.19:55:43.59#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.19:55:43.65#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.19:55:43.65#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.19:55:43.65#ibcon#enter wrdev, iclass 21, count 2 2006.173.19:55:43.65#ibcon#first serial, iclass 21, count 2 2006.173.19:55:43.65#ibcon#enter sib2, iclass 21, count 2 2006.173.19:55:43.65#ibcon#flushed, iclass 21, count 2 2006.173.19:55:43.65#ibcon#about to write, iclass 21, count 2 2006.173.19:55:43.65#ibcon#wrote, iclass 21, count 2 2006.173.19:55:43.65#ibcon#about to read 3, iclass 21, count 2 2006.173.19:55:43.67#ibcon#read 3, iclass 21, count 2 2006.173.19:55:43.67#ibcon#about to read 4, iclass 21, count 2 2006.173.19:55:43.67#ibcon#read 4, iclass 21, count 2 2006.173.19:55:43.67#ibcon#about to read 5, iclass 21, count 2 2006.173.19:55:43.67#ibcon#read 5, iclass 21, count 2 2006.173.19:55:43.67#ibcon#about to read 6, iclass 21, count 2 2006.173.19:55:43.67#ibcon#read 6, iclass 21, count 2 2006.173.19:55:43.67#ibcon#end of sib2, iclass 21, count 2 2006.173.19:55:43.67#ibcon#*mode == 0, iclass 21, count 2 2006.173.19:55:43.67#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.19:55:43.67#ibcon#[25=AT05-04\r\n] 2006.173.19:55:43.67#ibcon#*before write, iclass 21, count 2 2006.173.19:55:43.67#ibcon#enter sib2, iclass 21, count 2 2006.173.19:55:43.67#ibcon#flushed, iclass 21, count 2 2006.173.19:55:43.67#ibcon#about to write, iclass 21, count 2 2006.173.19:55:43.67#ibcon#wrote, iclass 21, count 2 2006.173.19:55:43.67#ibcon#about to read 3, iclass 21, count 2 2006.173.19:55:43.70#ibcon#read 3, iclass 21, count 2 2006.173.19:55:43.70#ibcon#about to read 4, iclass 21, count 2 2006.173.19:55:43.70#ibcon#read 4, iclass 21, count 2 2006.173.19:55:43.70#ibcon#about to read 5, iclass 21, count 2 2006.173.19:55:43.70#ibcon#read 5, iclass 21, count 2 2006.173.19:55:43.70#ibcon#about to read 6, iclass 21, count 2 2006.173.19:55:43.70#ibcon#read 6, iclass 21, count 2 2006.173.19:55:43.70#ibcon#end of sib2, iclass 21, count 2 2006.173.19:55:43.70#ibcon#*after write, iclass 21, count 2 2006.173.19:55:43.70#ibcon#*before return 0, iclass 21, count 2 2006.173.19:55:43.70#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.19:55:43.70#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.19:55:43.70#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.19:55:43.70#ibcon#ireg 7 cls_cnt 0 2006.173.19:55:43.70#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.19:55:43.82#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.19:55:43.82#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.19:55:43.82#ibcon#enter wrdev, iclass 21, count 0 2006.173.19:55:43.82#ibcon#first serial, iclass 21, count 0 2006.173.19:55:43.82#ibcon#enter sib2, iclass 21, count 0 2006.173.19:55:43.82#ibcon#flushed, iclass 21, count 0 2006.173.19:55:43.82#ibcon#about to write, iclass 21, count 0 2006.173.19:55:43.82#ibcon#wrote, iclass 21, count 0 2006.173.19:55:43.82#ibcon#about to read 3, iclass 21, count 0 2006.173.19:55:43.84#ibcon#read 3, iclass 21, count 0 2006.173.19:55:43.84#ibcon#about to read 4, iclass 21, count 0 2006.173.19:55:43.84#ibcon#read 4, iclass 21, count 0 2006.173.19:55:43.84#ibcon#about to read 5, iclass 21, count 0 2006.173.19:55:43.84#ibcon#read 5, iclass 21, count 0 2006.173.19:55:43.84#ibcon#about to read 6, iclass 21, count 0 2006.173.19:55:43.84#ibcon#read 6, iclass 21, count 0 2006.173.19:55:43.84#ibcon#end of sib2, iclass 21, count 0 2006.173.19:55:43.84#ibcon#*mode == 0, iclass 21, count 0 2006.173.19:55:43.84#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.19:55:43.84#ibcon#[25=USB\r\n] 2006.173.19:55:43.84#ibcon#*before write, iclass 21, count 0 2006.173.19:55:43.84#ibcon#enter sib2, iclass 21, count 0 2006.173.19:55:43.84#ibcon#flushed, iclass 21, count 0 2006.173.19:55:43.84#ibcon#about to write, iclass 21, count 0 2006.173.19:55:43.84#ibcon#wrote, iclass 21, count 0 2006.173.19:55:43.84#ibcon#about to read 3, iclass 21, count 0 2006.173.19:55:43.87#ibcon#read 3, iclass 21, count 0 2006.173.19:55:43.87#ibcon#about to read 4, iclass 21, count 0 2006.173.19:55:43.87#ibcon#read 4, iclass 21, count 0 2006.173.19:55:43.87#ibcon#about to read 5, iclass 21, count 0 2006.173.19:55:43.87#ibcon#read 5, iclass 21, count 0 2006.173.19:55:43.87#ibcon#about to read 6, iclass 21, count 0 2006.173.19:55:43.87#ibcon#read 6, iclass 21, count 0 2006.173.19:55:43.87#ibcon#end of sib2, iclass 21, count 0 2006.173.19:55:43.87#ibcon#*after write, iclass 21, count 0 2006.173.19:55:43.87#ibcon#*before return 0, iclass 21, count 0 2006.173.19:55:43.87#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.19:55:43.87#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.19:55:43.87#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.19:55:43.87#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.19:55:43.87$vck44/valo=6,814.99 2006.173.19:55:43.87#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.19:55:43.87#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.19:55:43.87#ibcon#ireg 17 cls_cnt 0 2006.173.19:55:43.87#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.19:55:43.87#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.19:55:43.87#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.19:55:43.87#ibcon#enter wrdev, iclass 23, count 0 2006.173.19:55:43.87#ibcon#first serial, iclass 23, count 0 2006.173.19:55:43.87#ibcon#enter sib2, iclass 23, count 0 2006.173.19:55:43.87#ibcon#flushed, iclass 23, count 0 2006.173.19:55:43.87#ibcon#about to write, iclass 23, count 0 2006.173.19:55:43.87#ibcon#wrote, iclass 23, count 0 2006.173.19:55:43.87#ibcon#about to read 3, iclass 23, count 0 2006.173.19:55:43.89#ibcon#read 3, iclass 23, count 0 2006.173.19:55:43.89#ibcon#about to read 4, iclass 23, count 0 2006.173.19:55:43.89#ibcon#read 4, iclass 23, count 0 2006.173.19:55:43.89#ibcon#about to read 5, iclass 23, count 0 2006.173.19:55:43.89#ibcon#read 5, iclass 23, count 0 2006.173.19:55:43.89#ibcon#about to read 6, iclass 23, count 0 2006.173.19:55:43.89#ibcon#read 6, iclass 23, count 0 2006.173.19:55:43.89#ibcon#end of sib2, iclass 23, count 0 2006.173.19:55:43.89#ibcon#*mode == 0, iclass 23, count 0 2006.173.19:55:43.89#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.19:55:43.89#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.19:55:43.89#ibcon#*before write, iclass 23, count 0 2006.173.19:55:43.89#ibcon#enter sib2, iclass 23, count 0 2006.173.19:55:43.89#ibcon#flushed, iclass 23, count 0 2006.173.19:55:43.89#ibcon#about to write, iclass 23, count 0 2006.173.19:55:43.89#ibcon#wrote, iclass 23, count 0 2006.173.19:55:43.89#ibcon#about to read 3, iclass 23, count 0 2006.173.19:55:43.93#ibcon#read 3, iclass 23, count 0 2006.173.19:55:43.93#ibcon#about to read 4, iclass 23, count 0 2006.173.19:55:43.93#ibcon#read 4, iclass 23, count 0 2006.173.19:55:43.93#ibcon#about to read 5, iclass 23, count 0 2006.173.19:55:43.93#ibcon#read 5, iclass 23, count 0 2006.173.19:55:43.93#ibcon#about to read 6, iclass 23, count 0 2006.173.19:55:43.93#ibcon#read 6, iclass 23, count 0 2006.173.19:55:43.93#ibcon#end of sib2, iclass 23, count 0 2006.173.19:55:43.93#ibcon#*after write, iclass 23, count 0 2006.173.19:55:43.93#ibcon#*before return 0, iclass 23, count 0 2006.173.19:55:43.93#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.19:55:43.93#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.19:55:43.93#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.19:55:43.93#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.19:55:43.93$vck44/va=6,3 2006.173.19:55:43.93#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.19:55:43.93#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.19:55:43.93#ibcon#ireg 11 cls_cnt 2 2006.173.19:55:43.93#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.19:55:43.99#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.19:55:43.99#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.19:55:43.99#ibcon#enter wrdev, iclass 25, count 2 2006.173.19:55:43.99#ibcon#first serial, iclass 25, count 2 2006.173.19:55:43.99#ibcon#enter sib2, iclass 25, count 2 2006.173.19:55:43.99#ibcon#flushed, iclass 25, count 2 2006.173.19:55:43.99#ibcon#about to write, iclass 25, count 2 2006.173.19:55:43.99#ibcon#wrote, iclass 25, count 2 2006.173.19:55:43.99#ibcon#about to read 3, iclass 25, count 2 2006.173.19:55:44.01#ibcon#read 3, iclass 25, count 2 2006.173.19:55:44.01#ibcon#about to read 4, iclass 25, count 2 2006.173.19:55:44.01#ibcon#read 4, iclass 25, count 2 2006.173.19:55:44.01#ibcon#about to read 5, iclass 25, count 2 2006.173.19:55:44.01#ibcon#read 5, iclass 25, count 2 2006.173.19:55:44.01#ibcon#about to read 6, iclass 25, count 2 2006.173.19:55:44.01#ibcon#read 6, iclass 25, count 2 2006.173.19:55:44.01#ibcon#end of sib2, iclass 25, count 2 2006.173.19:55:44.01#ibcon#*mode == 0, iclass 25, count 2 2006.173.19:55:44.01#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.19:55:44.01#ibcon#[25=AT06-03\r\n] 2006.173.19:55:44.01#ibcon#*before write, iclass 25, count 2 2006.173.19:55:44.01#ibcon#enter sib2, iclass 25, count 2 2006.173.19:55:44.01#ibcon#flushed, iclass 25, count 2 2006.173.19:55:44.01#ibcon#about to write, iclass 25, count 2 2006.173.19:55:44.01#ibcon#wrote, iclass 25, count 2 2006.173.19:55:44.01#ibcon#about to read 3, iclass 25, count 2 2006.173.19:55:44.04#ibcon#read 3, iclass 25, count 2 2006.173.19:55:44.04#ibcon#about to read 4, iclass 25, count 2 2006.173.19:55:44.04#ibcon#read 4, iclass 25, count 2 2006.173.19:55:44.04#ibcon#about to read 5, iclass 25, count 2 2006.173.19:55:44.04#ibcon#read 5, iclass 25, count 2 2006.173.19:55:44.04#ibcon#about to read 6, iclass 25, count 2 2006.173.19:55:44.04#ibcon#read 6, iclass 25, count 2 2006.173.19:55:44.04#ibcon#end of sib2, iclass 25, count 2 2006.173.19:55:44.04#ibcon#*after write, iclass 25, count 2 2006.173.19:55:44.04#ibcon#*before return 0, iclass 25, count 2 2006.173.19:55:44.04#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.19:55:44.04#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.19:55:44.04#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.19:55:44.04#ibcon#ireg 7 cls_cnt 0 2006.173.19:55:44.04#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.19:55:44.16#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.19:55:44.16#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.19:55:44.16#ibcon#enter wrdev, iclass 25, count 0 2006.173.19:55:44.16#ibcon#first serial, iclass 25, count 0 2006.173.19:55:44.16#ibcon#enter sib2, iclass 25, count 0 2006.173.19:55:44.16#ibcon#flushed, iclass 25, count 0 2006.173.19:55:44.16#ibcon#about to write, iclass 25, count 0 2006.173.19:55:44.16#ibcon#wrote, iclass 25, count 0 2006.173.19:55:44.16#ibcon#about to read 3, iclass 25, count 0 2006.173.19:55:44.18#ibcon#read 3, iclass 25, count 0 2006.173.19:55:44.18#ibcon#about to read 4, iclass 25, count 0 2006.173.19:55:44.18#ibcon#read 4, iclass 25, count 0 2006.173.19:55:44.18#ibcon#about to read 5, iclass 25, count 0 2006.173.19:55:44.18#ibcon#read 5, iclass 25, count 0 2006.173.19:55:44.18#ibcon#about to read 6, iclass 25, count 0 2006.173.19:55:44.18#ibcon#read 6, iclass 25, count 0 2006.173.19:55:44.18#ibcon#end of sib2, iclass 25, count 0 2006.173.19:55:44.18#ibcon#*mode == 0, iclass 25, count 0 2006.173.19:55:44.18#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.19:55:44.18#ibcon#[25=USB\r\n] 2006.173.19:55:44.18#ibcon#*before write, iclass 25, count 0 2006.173.19:55:44.18#ibcon#enter sib2, iclass 25, count 0 2006.173.19:55:44.18#ibcon#flushed, iclass 25, count 0 2006.173.19:55:44.18#ibcon#about to write, iclass 25, count 0 2006.173.19:55:44.18#ibcon#wrote, iclass 25, count 0 2006.173.19:55:44.18#ibcon#about to read 3, iclass 25, count 0 2006.173.19:55:44.21#ibcon#read 3, iclass 25, count 0 2006.173.19:55:44.21#ibcon#about to read 4, iclass 25, count 0 2006.173.19:55:44.21#ibcon#read 4, iclass 25, count 0 2006.173.19:55:44.21#ibcon#about to read 5, iclass 25, count 0 2006.173.19:55:44.21#ibcon#read 5, iclass 25, count 0 2006.173.19:55:44.21#ibcon#about to read 6, iclass 25, count 0 2006.173.19:55:44.21#ibcon#read 6, iclass 25, count 0 2006.173.19:55:44.21#ibcon#end of sib2, iclass 25, count 0 2006.173.19:55:44.21#ibcon#*after write, iclass 25, count 0 2006.173.19:55:44.21#ibcon#*before return 0, iclass 25, count 0 2006.173.19:55:44.21#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.19:55:44.21#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.19:55:44.21#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.19:55:44.21#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.19:55:44.21$vck44/valo=7,864.99 2006.173.19:55:44.21#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.19:55:44.21#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.19:55:44.21#ibcon#ireg 17 cls_cnt 0 2006.173.19:55:44.21#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.19:55:44.21#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.19:55:44.21#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.19:55:44.21#ibcon#enter wrdev, iclass 27, count 0 2006.173.19:55:44.21#ibcon#first serial, iclass 27, count 0 2006.173.19:55:44.21#ibcon#enter sib2, iclass 27, count 0 2006.173.19:55:44.21#ibcon#flushed, iclass 27, count 0 2006.173.19:55:44.21#ibcon#about to write, iclass 27, count 0 2006.173.19:55:44.21#ibcon#wrote, iclass 27, count 0 2006.173.19:55:44.21#ibcon#about to read 3, iclass 27, count 0 2006.173.19:55:44.23#ibcon#read 3, iclass 27, count 0 2006.173.19:55:44.23#ibcon#about to read 4, iclass 27, count 0 2006.173.19:55:44.23#ibcon#read 4, iclass 27, count 0 2006.173.19:55:44.23#ibcon#about to read 5, iclass 27, count 0 2006.173.19:55:44.23#ibcon#read 5, iclass 27, count 0 2006.173.19:55:44.23#ibcon#about to read 6, iclass 27, count 0 2006.173.19:55:44.23#ibcon#read 6, iclass 27, count 0 2006.173.19:55:44.23#ibcon#end of sib2, iclass 27, count 0 2006.173.19:55:44.23#ibcon#*mode == 0, iclass 27, count 0 2006.173.19:55:44.23#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.19:55:44.23#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.19:55:44.23#ibcon#*before write, iclass 27, count 0 2006.173.19:55:44.23#ibcon#enter sib2, iclass 27, count 0 2006.173.19:55:44.23#ibcon#flushed, iclass 27, count 0 2006.173.19:55:44.23#ibcon#about to write, iclass 27, count 0 2006.173.19:55:44.23#ibcon#wrote, iclass 27, count 0 2006.173.19:55:44.23#ibcon#about to read 3, iclass 27, count 0 2006.173.19:55:44.27#ibcon#read 3, iclass 27, count 0 2006.173.19:55:44.27#ibcon#about to read 4, iclass 27, count 0 2006.173.19:55:44.27#ibcon#read 4, iclass 27, count 0 2006.173.19:55:44.27#ibcon#about to read 5, iclass 27, count 0 2006.173.19:55:44.27#ibcon#read 5, iclass 27, count 0 2006.173.19:55:44.27#ibcon#about to read 6, iclass 27, count 0 2006.173.19:55:44.27#ibcon#read 6, iclass 27, count 0 2006.173.19:55:44.27#ibcon#end of sib2, iclass 27, count 0 2006.173.19:55:44.27#ibcon#*after write, iclass 27, count 0 2006.173.19:55:44.27#ibcon#*before return 0, iclass 27, count 0 2006.173.19:55:44.27#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.19:55:44.27#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.19:55:44.27#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.19:55:44.27#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.19:55:44.27$vck44/va=7,4 2006.173.19:55:44.27#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.19:55:44.27#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.19:55:44.27#ibcon#ireg 11 cls_cnt 2 2006.173.19:55:44.27#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.19:55:44.33#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.19:55:44.33#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.19:55:44.33#ibcon#enter wrdev, iclass 29, count 2 2006.173.19:55:44.33#ibcon#first serial, iclass 29, count 2 2006.173.19:55:44.33#ibcon#enter sib2, iclass 29, count 2 2006.173.19:55:44.33#ibcon#flushed, iclass 29, count 2 2006.173.19:55:44.33#ibcon#about to write, iclass 29, count 2 2006.173.19:55:44.33#ibcon#wrote, iclass 29, count 2 2006.173.19:55:44.33#ibcon#about to read 3, iclass 29, count 2 2006.173.19:55:44.35#ibcon#read 3, iclass 29, count 2 2006.173.19:55:44.35#ibcon#about to read 4, iclass 29, count 2 2006.173.19:55:44.35#ibcon#read 4, iclass 29, count 2 2006.173.19:55:44.35#ibcon#about to read 5, iclass 29, count 2 2006.173.19:55:44.35#ibcon#read 5, iclass 29, count 2 2006.173.19:55:44.35#ibcon#about to read 6, iclass 29, count 2 2006.173.19:55:44.35#ibcon#read 6, iclass 29, count 2 2006.173.19:55:44.35#ibcon#end of sib2, iclass 29, count 2 2006.173.19:55:44.35#ibcon#*mode == 0, iclass 29, count 2 2006.173.19:55:44.35#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.19:55:44.35#ibcon#[25=AT07-04\r\n] 2006.173.19:55:44.35#ibcon#*before write, iclass 29, count 2 2006.173.19:55:44.35#ibcon#enter sib2, iclass 29, count 2 2006.173.19:55:44.35#ibcon#flushed, iclass 29, count 2 2006.173.19:55:44.35#ibcon#about to write, iclass 29, count 2 2006.173.19:55:44.35#ibcon#wrote, iclass 29, count 2 2006.173.19:55:44.35#ibcon#about to read 3, iclass 29, count 2 2006.173.19:55:44.38#ibcon#read 3, iclass 29, count 2 2006.173.19:55:44.38#ibcon#about to read 4, iclass 29, count 2 2006.173.19:55:44.38#ibcon#read 4, iclass 29, count 2 2006.173.19:55:44.38#ibcon#about to read 5, iclass 29, count 2 2006.173.19:55:44.38#ibcon#read 5, iclass 29, count 2 2006.173.19:55:44.38#ibcon#about to read 6, iclass 29, count 2 2006.173.19:55:44.38#ibcon#read 6, iclass 29, count 2 2006.173.19:55:44.38#ibcon#end of sib2, iclass 29, count 2 2006.173.19:55:44.38#ibcon#*after write, iclass 29, count 2 2006.173.19:55:44.38#ibcon#*before return 0, iclass 29, count 2 2006.173.19:55:44.38#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.19:55:44.38#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.19:55:44.38#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.19:55:44.38#ibcon#ireg 7 cls_cnt 0 2006.173.19:55:44.38#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.19:55:44.50#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.19:55:44.50#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.19:55:44.50#ibcon#enter wrdev, iclass 29, count 0 2006.173.19:55:44.50#ibcon#first serial, iclass 29, count 0 2006.173.19:55:44.50#ibcon#enter sib2, iclass 29, count 0 2006.173.19:55:44.50#ibcon#flushed, iclass 29, count 0 2006.173.19:55:44.50#ibcon#about to write, iclass 29, count 0 2006.173.19:55:44.50#ibcon#wrote, iclass 29, count 0 2006.173.19:55:44.50#ibcon#about to read 3, iclass 29, count 0 2006.173.19:55:44.52#ibcon#read 3, iclass 29, count 0 2006.173.19:55:44.52#ibcon#about to read 4, iclass 29, count 0 2006.173.19:55:44.52#ibcon#read 4, iclass 29, count 0 2006.173.19:55:44.52#ibcon#about to read 5, iclass 29, count 0 2006.173.19:55:44.52#ibcon#read 5, iclass 29, count 0 2006.173.19:55:44.52#ibcon#about to read 6, iclass 29, count 0 2006.173.19:55:44.52#ibcon#read 6, iclass 29, count 0 2006.173.19:55:44.52#ibcon#end of sib2, iclass 29, count 0 2006.173.19:55:44.52#ibcon#*mode == 0, iclass 29, count 0 2006.173.19:55:44.52#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.19:55:44.52#ibcon#[25=USB\r\n] 2006.173.19:55:44.52#ibcon#*before write, iclass 29, count 0 2006.173.19:55:44.52#ibcon#enter sib2, iclass 29, count 0 2006.173.19:55:44.52#ibcon#flushed, iclass 29, count 0 2006.173.19:55:44.52#ibcon#about to write, iclass 29, count 0 2006.173.19:55:44.52#ibcon#wrote, iclass 29, count 0 2006.173.19:55:44.52#ibcon#about to read 3, iclass 29, count 0 2006.173.19:55:44.55#ibcon#read 3, iclass 29, count 0 2006.173.19:55:44.55#ibcon#about to read 4, iclass 29, count 0 2006.173.19:55:44.55#ibcon#read 4, iclass 29, count 0 2006.173.19:55:44.55#ibcon#about to read 5, iclass 29, count 0 2006.173.19:55:44.55#ibcon#read 5, iclass 29, count 0 2006.173.19:55:44.55#ibcon#about to read 6, iclass 29, count 0 2006.173.19:55:44.55#ibcon#read 6, iclass 29, count 0 2006.173.19:55:44.55#ibcon#end of sib2, iclass 29, count 0 2006.173.19:55:44.55#ibcon#*after write, iclass 29, count 0 2006.173.19:55:44.55#ibcon#*before return 0, iclass 29, count 0 2006.173.19:55:44.55#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.19:55:44.55#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.19:55:44.55#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.19:55:44.55#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.19:55:44.55$vck44/valo=8,884.99 2006.173.19:55:44.55#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.19:55:44.55#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.19:55:44.55#ibcon#ireg 17 cls_cnt 0 2006.173.19:55:44.55#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.19:55:44.55#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.19:55:44.55#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.19:55:44.55#ibcon#enter wrdev, iclass 31, count 0 2006.173.19:55:44.55#ibcon#first serial, iclass 31, count 0 2006.173.19:55:44.55#ibcon#enter sib2, iclass 31, count 0 2006.173.19:55:44.55#ibcon#flushed, iclass 31, count 0 2006.173.19:55:44.55#ibcon#about to write, iclass 31, count 0 2006.173.19:55:44.55#ibcon#wrote, iclass 31, count 0 2006.173.19:55:44.55#ibcon#about to read 3, iclass 31, count 0 2006.173.19:55:44.57#ibcon#read 3, iclass 31, count 0 2006.173.19:55:44.57#ibcon#about to read 4, iclass 31, count 0 2006.173.19:55:44.57#ibcon#read 4, iclass 31, count 0 2006.173.19:55:44.57#ibcon#about to read 5, iclass 31, count 0 2006.173.19:55:44.57#ibcon#read 5, iclass 31, count 0 2006.173.19:55:44.57#ibcon#about to read 6, iclass 31, count 0 2006.173.19:55:44.57#ibcon#read 6, iclass 31, count 0 2006.173.19:55:44.57#ibcon#end of sib2, iclass 31, count 0 2006.173.19:55:44.57#ibcon#*mode == 0, iclass 31, count 0 2006.173.19:55:44.57#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.19:55:44.57#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.19:55:44.57#ibcon#*before write, iclass 31, count 0 2006.173.19:55:44.57#ibcon#enter sib2, iclass 31, count 0 2006.173.19:55:44.57#ibcon#flushed, iclass 31, count 0 2006.173.19:55:44.57#ibcon#about to write, iclass 31, count 0 2006.173.19:55:44.57#ibcon#wrote, iclass 31, count 0 2006.173.19:55:44.57#ibcon#about to read 3, iclass 31, count 0 2006.173.19:55:44.61#ibcon#read 3, iclass 31, count 0 2006.173.19:55:44.61#ibcon#about to read 4, iclass 31, count 0 2006.173.19:55:44.61#ibcon#read 4, iclass 31, count 0 2006.173.19:55:44.61#ibcon#about to read 5, iclass 31, count 0 2006.173.19:55:44.61#ibcon#read 5, iclass 31, count 0 2006.173.19:55:44.61#ibcon#about to read 6, iclass 31, count 0 2006.173.19:55:44.61#ibcon#read 6, iclass 31, count 0 2006.173.19:55:44.61#ibcon#end of sib2, iclass 31, count 0 2006.173.19:55:44.61#ibcon#*after write, iclass 31, count 0 2006.173.19:55:44.61#ibcon#*before return 0, iclass 31, count 0 2006.173.19:55:44.61#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.19:55:44.61#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.19:55:44.61#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.19:55:44.61#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.19:55:44.61$vck44/va=8,4 2006.173.19:55:44.61#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.173.19:55:44.61#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.173.19:55:44.61#ibcon#ireg 11 cls_cnt 2 2006.173.19:55:44.61#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.19:55:44.67#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.19:55:44.67#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.19:55:44.67#ibcon#enter wrdev, iclass 33, count 2 2006.173.19:55:44.67#ibcon#first serial, iclass 33, count 2 2006.173.19:55:44.67#ibcon#enter sib2, iclass 33, count 2 2006.173.19:55:44.67#ibcon#flushed, iclass 33, count 2 2006.173.19:55:44.67#ibcon#about to write, iclass 33, count 2 2006.173.19:55:44.67#ibcon#wrote, iclass 33, count 2 2006.173.19:55:44.67#ibcon#about to read 3, iclass 33, count 2 2006.173.19:55:44.69#ibcon#read 3, iclass 33, count 2 2006.173.19:55:44.69#ibcon#about to read 4, iclass 33, count 2 2006.173.19:55:44.69#ibcon#read 4, iclass 33, count 2 2006.173.19:55:44.69#ibcon#about to read 5, iclass 33, count 2 2006.173.19:55:44.69#ibcon#read 5, iclass 33, count 2 2006.173.19:55:44.69#ibcon#about to read 6, iclass 33, count 2 2006.173.19:55:44.69#ibcon#read 6, iclass 33, count 2 2006.173.19:55:44.69#ibcon#end of sib2, iclass 33, count 2 2006.173.19:55:44.69#ibcon#*mode == 0, iclass 33, count 2 2006.173.19:55:44.69#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.173.19:55:44.69#ibcon#[25=AT08-04\r\n] 2006.173.19:55:44.69#ibcon#*before write, iclass 33, count 2 2006.173.19:55:44.69#ibcon#enter sib2, iclass 33, count 2 2006.173.19:55:44.69#ibcon#flushed, iclass 33, count 2 2006.173.19:55:44.69#ibcon#about to write, iclass 33, count 2 2006.173.19:55:44.69#ibcon#wrote, iclass 33, count 2 2006.173.19:55:44.69#ibcon#about to read 3, iclass 33, count 2 2006.173.19:55:44.72#ibcon#read 3, iclass 33, count 2 2006.173.19:55:44.72#ibcon#about to read 4, iclass 33, count 2 2006.173.19:55:44.72#ibcon#read 4, iclass 33, count 2 2006.173.19:55:44.72#ibcon#about to read 5, iclass 33, count 2 2006.173.19:55:44.72#ibcon#read 5, iclass 33, count 2 2006.173.19:55:44.72#ibcon#about to read 6, iclass 33, count 2 2006.173.19:55:44.72#ibcon#read 6, iclass 33, count 2 2006.173.19:55:44.72#ibcon#end of sib2, iclass 33, count 2 2006.173.19:55:44.72#ibcon#*after write, iclass 33, count 2 2006.173.19:55:44.72#ibcon#*before return 0, iclass 33, count 2 2006.173.19:55:44.72#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.19:55:44.72#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.173.19:55:44.72#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.173.19:55:44.72#ibcon#ireg 7 cls_cnt 0 2006.173.19:55:44.72#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.19:55:44.84#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.19:55:44.84#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.19:55:44.84#ibcon#enter wrdev, iclass 33, count 0 2006.173.19:55:44.84#ibcon#first serial, iclass 33, count 0 2006.173.19:55:44.84#ibcon#enter sib2, iclass 33, count 0 2006.173.19:55:44.84#ibcon#flushed, iclass 33, count 0 2006.173.19:55:44.84#ibcon#about to write, iclass 33, count 0 2006.173.19:55:44.84#ibcon#wrote, iclass 33, count 0 2006.173.19:55:44.84#ibcon#about to read 3, iclass 33, count 0 2006.173.19:55:44.86#ibcon#read 3, iclass 33, count 0 2006.173.19:55:44.86#ibcon#about to read 4, iclass 33, count 0 2006.173.19:55:44.86#ibcon#read 4, iclass 33, count 0 2006.173.19:55:44.86#ibcon#about to read 5, iclass 33, count 0 2006.173.19:55:44.86#ibcon#read 5, iclass 33, count 0 2006.173.19:55:44.86#ibcon#about to read 6, iclass 33, count 0 2006.173.19:55:44.86#ibcon#read 6, iclass 33, count 0 2006.173.19:55:44.86#ibcon#end of sib2, iclass 33, count 0 2006.173.19:55:44.86#ibcon#*mode == 0, iclass 33, count 0 2006.173.19:55:44.86#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.19:55:44.86#ibcon#[25=USB\r\n] 2006.173.19:55:44.86#ibcon#*before write, iclass 33, count 0 2006.173.19:55:44.86#ibcon#enter sib2, iclass 33, count 0 2006.173.19:55:44.86#ibcon#flushed, iclass 33, count 0 2006.173.19:55:44.86#ibcon#about to write, iclass 33, count 0 2006.173.19:55:44.86#ibcon#wrote, iclass 33, count 0 2006.173.19:55:44.86#ibcon#about to read 3, iclass 33, count 0 2006.173.19:55:44.89#ibcon#read 3, iclass 33, count 0 2006.173.19:55:44.89#ibcon#about to read 4, iclass 33, count 0 2006.173.19:55:44.89#ibcon#read 4, iclass 33, count 0 2006.173.19:55:44.89#ibcon#about to read 5, iclass 33, count 0 2006.173.19:55:44.89#ibcon#read 5, iclass 33, count 0 2006.173.19:55:44.89#ibcon#about to read 6, iclass 33, count 0 2006.173.19:55:44.89#ibcon#read 6, iclass 33, count 0 2006.173.19:55:44.89#ibcon#end of sib2, iclass 33, count 0 2006.173.19:55:44.89#ibcon#*after write, iclass 33, count 0 2006.173.19:55:44.89#ibcon#*before return 0, iclass 33, count 0 2006.173.19:55:44.89#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.19:55:44.89#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.173.19:55:44.89#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.19:55:44.89#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.19:55:44.89$vck44/vblo=1,629.99 2006.173.19:55:44.89#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.19:55:44.89#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.19:55:44.89#ibcon#ireg 17 cls_cnt 0 2006.173.19:55:44.89#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.19:55:44.89#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.19:55:44.89#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.19:55:44.89#ibcon#enter wrdev, iclass 35, count 0 2006.173.19:55:44.89#ibcon#first serial, iclass 35, count 0 2006.173.19:55:44.89#ibcon#enter sib2, iclass 35, count 0 2006.173.19:55:44.89#ibcon#flushed, iclass 35, count 0 2006.173.19:55:44.89#ibcon#about to write, iclass 35, count 0 2006.173.19:55:44.89#ibcon#wrote, iclass 35, count 0 2006.173.19:55:44.89#ibcon#about to read 3, iclass 35, count 0 2006.173.19:55:44.91#ibcon#read 3, iclass 35, count 0 2006.173.19:55:44.91#ibcon#about to read 4, iclass 35, count 0 2006.173.19:55:44.91#ibcon#read 4, iclass 35, count 0 2006.173.19:55:44.91#ibcon#about to read 5, iclass 35, count 0 2006.173.19:55:44.91#ibcon#read 5, iclass 35, count 0 2006.173.19:55:44.91#ibcon#about to read 6, iclass 35, count 0 2006.173.19:55:44.91#ibcon#read 6, iclass 35, count 0 2006.173.19:55:44.91#ibcon#end of sib2, iclass 35, count 0 2006.173.19:55:44.91#ibcon#*mode == 0, iclass 35, count 0 2006.173.19:55:44.91#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.19:55:44.91#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.19:55:44.91#ibcon#*before write, iclass 35, count 0 2006.173.19:55:44.91#ibcon#enter sib2, iclass 35, count 0 2006.173.19:55:44.91#ibcon#flushed, iclass 35, count 0 2006.173.19:55:44.91#ibcon#about to write, iclass 35, count 0 2006.173.19:55:44.91#ibcon#wrote, iclass 35, count 0 2006.173.19:55:44.91#ibcon#about to read 3, iclass 35, count 0 2006.173.19:55:44.95#ibcon#read 3, iclass 35, count 0 2006.173.19:55:44.95#ibcon#about to read 4, iclass 35, count 0 2006.173.19:55:44.95#ibcon#read 4, iclass 35, count 0 2006.173.19:55:44.95#ibcon#about to read 5, iclass 35, count 0 2006.173.19:55:44.95#ibcon#read 5, iclass 35, count 0 2006.173.19:55:44.95#ibcon#about to read 6, iclass 35, count 0 2006.173.19:55:44.95#ibcon#read 6, iclass 35, count 0 2006.173.19:55:44.95#ibcon#end of sib2, iclass 35, count 0 2006.173.19:55:44.95#ibcon#*after write, iclass 35, count 0 2006.173.19:55:44.95#ibcon#*before return 0, iclass 35, count 0 2006.173.19:55:44.95#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.19:55:44.95#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.19:55:44.95#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.19:55:44.95#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.19:55:44.95$vck44/vb=1,4 2006.173.19:55:44.95#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.173.19:55:44.95#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.173.19:55:44.95#ibcon#ireg 11 cls_cnt 2 2006.173.19:55:44.95#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.19:55:44.95#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.19:55:44.95#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.19:55:44.95#ibcon#enter wrdev, iclass 37, count 2 2006.173.19:55:44.95#ibcon#first serial, iclass 37, count 2 2006.173.19:55:44.95#ibcon#enter sib2, iclass 37, count 2 2006.173.19:55:44.95#ibcon#flushed, iclass 37, count 2 2006.173.19:55:44.95#ibcon#about to write, iclass 37, count 2 2006.173.19:55:44.95#ibcon#wrote, iclass 37, count 2 2006.173.19:55:44.95#ibcon#about to read 3, iclass 37, count 2 2006.173.19:55:44.97#ibcon#read 3, iclass 37, count 2 2006.173.19:55:44.97#ibcon#about to read 4, iclass 37, count 2 2006.173.19:55:44.97#ibcon#read 4, iclass 37, count 2 2006.173.19:55:44.97#ibcon#about to read 5, iclass 37, count 2 2006.173.19:55:44.97#ibcon#read 5, iclass 37, count 2 2006.173.19:55:44.97#ibcon#about to read 6, iclass 37, count 2 2006.173.19:55:44.97#ibcon#read 6, iclass 37, count 2 2006.173.19:55:44.97#ibcon#end of sib2, iclass 37, count 2 2006.173.19:55:44.97#ibcon#*mode == 0, iclass 37, count 2 2006.173.19:55:44.97#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.173.19:55:44.97#ibcon#[27=AT01-04\r\n] 2006.173.19:55:44.97#ibcon#*before write, iclass 37, count 2 2006.173.19:55:44.97#ibcon#enter sib2, iclass 37, count 2 2006.173.19:55:44.97#ibcon#flushed, iclass 37, count 2 2006.173.19:55:44.97#ibcon#about to write, iclass 37, count 2 2006.173.19:55:44.97#ibcon#wrote, iclass 37, count 2 2006.173.19:55:44.97#ibcon#about to read 3, iclass 37, count 2 2006.173.19:55:45.00#ibcon#read 3, iclass 37, count 2 2006.173.19:55:45.00#ibcon#about to read 4, iclass 37, count 2 2006.173.19:55:45.00#ibcon#read 4, iclass 37, count 2 2006.173.19:55:45.00#ibcon#about to read 5, iclass 37, count 2 2006.173.19:55:45.00#ibcon#read 5, iclass 37, count 2 2006.173.19:55:45.00#ibcon#about to read 6, iclass 37, count 2 2006.173.19:55:45.00#ibcon#read 6, iclass 37, count 2 2006.173.19:55:45.00#ibcon#end of sib2, iclass 37, count 2 2006.173.19:55:45.00#ibcon#*after write, iclass 37, count 2 2006.173.19:55:45.00#ibcon#*before return 0, iclass 37, count 2 2006.173.19:55:45.00#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.19:55:45.00#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.173.19:55:45.00#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.173.19:55:45.00#ibcon#ireg 7 cls_cnt 0 2006.173.19:55:45.00#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.19:55:45.12#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.19:55:45.12#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.19:55:45.12#ibcon#enter wrdev, iclass 37, count 0 2006.173.19:55:45.12#ibcon#first serial, iclass 37, count 0 2006.173.19:55:45.12#ibcon#enter sib2, iclass 37, count 0 2006.173.19:55:45.12#ibcon#flushed, iclass 37, count 0 2006.173.19:55:45.12#ibcon#about to write, iclass 37, count 0 2006.173.19:55:45.12#ibcon#wrote, iclass 37, count 0 2006.173.19:55:45.12#ibcon#about to read 3, iclass 37, count 0 2006.173.19:55:45.14#ibcon#read 3, iclass 37, count 0 2006.173.19:55:45.14#ibcon#about to read 4, iclass 37, count 0 2006.173.19:55:45.14#ibcon#read 4, iclass 37, count 0 2006.173.19:55:45.14#ibcon#about to read 5, iclass 37, count 0 2006.173.19:55:45.14#ibcon#read 5, iclass 37, count 0 2006.173.19:55:45.14#ibcon#about to read 6, iclass 37, count 0 2006.173.19:55:45.14#ibcon#read 6, iclass 37, count 0 2006.173.19:55:45.14#ibcon#end of sib2, iclass 37, count 0 2006.173.19:55:45.14#ibcon#*mode == 0, iclass 37, count 0 2006.173.19:55:45.14#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.19:55:45.14#ibcon#[27=USB\r\n] 2006.173.19:55:45.14#ibcon#*before write, iclass 37, count 0 2006.173.19:55:45.14#ibcon#enter sib2, iclass 37, count 0 2006.173.19:55:45.14#ibcon#flushed, iclass 37, count 0 2006.173.19:55:45.14#ibcon#about to write, iclass 37, count 0 2006.173.19:55:45.14#ibcon#wrote, iclass 37, count 0 2006.173.19:55:45.14#ibcon#about to read 3, iclass 37, count 0 2006.173.19:55:45.17#ibcon#read 3, iclass 37, count 0 2006.173.19:55:45.17#ibcon#about to read 4, iclass 37, count 0 2006.173.19:55:45.17#ibcon#read 4, iclass 37, count 0 2006.173.19:55:45.17#ibcon#about to read 5, iclass 37, count 0 2006.173.19:55:45.17#ibcon#read 5, iclass 37, count 0 2006.173.19:55:45.17#ibcon#about to read 6, iclass 37, count 0 2006.173.19:55:45.17#ibcon#read 6, iclass 37, count 0 2006.173.19:55:45.17#ibcon#end of sib2, iclass 37, count 0 2006.173.19:55:45.17#ibcon#*after write, iclass 37, count 0 2006.173.19:55:45.17#ibcon#*before return 0, iclass 37, count 0 2006.173.19:55:45.17#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.19:55:45.17#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.173.19:55:45.17#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.19:55:45.17#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.19:55:45.17$vck44/vblo=2,634.99 2006.173.19:55:45.17#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.19:55:45.17#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.19:55:45.17#ibcon#ireg 17 cls_cnt 0 2006.173.19:55:45.17#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.19:55:45.17#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.19:55:45.17#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.19:55:45.17#ibcon#enter wrdev, iclass 39, count 0 2006.173.19:55:45.17#ibcon#first serial, iclass 39, count 0 2006.173.19:55:45.17#ibcon#enter sib2, iclass 39, count 0 2006.173.19:55:45.17#ibcon#flushed, iclass 39, count 0 2006.173.19:55:45.17#ibcon#about to write, iclass 39, count 0 2006.173.19:55:45.17#ibcon#wrote, iclass 39, count 0 2006.173.19:55:45.17#ibcon#about to read 3, iclass 39, count 0 2006.173.19:55:45.19#ibcon#read 3, iclass 39, count 0 2006.173.19:55:45.19#ibcon#about to read 4, iclass 39, count 0 2006.173.19:55:45.19#ibcon#read 4, iclass 39, count 0 2006.173.19:55:45.19#ibcon#about to read 5, iclass 39, count 0 2006.173.19:55:45.19#ibcon#read 5, iclass 39, count 0 2006.173.19:55:45.19#ibcon#about to read 6, iclass 39, count 0 2006.173.19:55:45.19#ibcon#read 6, iclass 39, count 0 2006.173.19:55:45.19#ibcon#end of sib2, iclass 39, count 0 2006.173.19:55:45.19#ibcon#*mode == 0, iclass 39, count 0 2006.173.19:55:45.19#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.19:55:45.19#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.19:55:45.19#ibcon#*before write, iclass 39, count 0 2006.173.19:55:45.19#ibcon#enter sib2, iclass 39, count 0 2006.173.19:55:45.19#ibcon#flushed, iclass 39, count 0 2006.173.19:55:45.19#ibcon#about to write, iclass 39, count 0 2006.173.19:55:45.19#ibcon#wrote, iclass 39, count 0 2006.173.19:55:45.19#ibcon#about to read 3, iclass 39, count 0 2006.173.19:55:45.23#ibcon#read 3, iclass 39, count 0 2006.173.19:55:45.23#ibcon#about to read 4, iclass 39, count 0 2006.173.19:55:45.23#ibcon#read 4, iclass 39, count 0 2006.173.19:55:45.23#ibcon#about to read 5, iclass 39, count 0 2006.173.19:55:45.23#ibcon#read 5, iclass 39, count 0 2006.173.19:55:45.23#ibcon#about to read 6, iclass 39, count 0 2006.173.19:55:45.23#ibcon#read 6, iclass 39, count 0 2006.173.19:55:45.23#ibcon#end of sib2, iclass 39, count 0 2006.173.19:55:45.23#ibcon#*after write, iclass 39, count 0 2006.173.19:55:45.23#ibcon#*before return 0, iclass 39, count 0 2006.173.19:55:45.23#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.19:55:45.23#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.19:55:45.23#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.19:55:45.23#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.19:55:45.23$vck44/vb=2,4 2006.173.19:55:45.23#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.19:55:45.23#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.19:55:45.23#ibcon#ireg 11 cls_cnt 2 2006.173.19:55:45.23#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.19:55:45.29#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.19:55:45.29#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.19:55:45.29#ibcon#enter wrdev, iclass 3, count 2 2006.173.19:55:45.29#ibcon#first serial, iclass 3, count 2 2006.173.19:55:45.29#ibcon#enter sib2, iclass 3, count 2 2006.173.19:55:45.29#ibcon#flushed, iclass 3, count 2 2006.173.19:55:45.29#ibcon#about to write, iclass 3, count 2 2006.173.19:55:45.29#ibcon#wrote, iclass 3, count 2 2006.173.19:55:45.29#ibcon#about to read 3, iclass 3, count 2 2006.173.19:55:45.31#ibcon#read 3, iclass 3, count 2 2006.173.19:55:45.31#ibcon#about to read 4, iclass 3, count 2 2006.173.19:55:45.31#ibcon#read 4, iclass 3, count 2 2006.173.19:55:45.31#ibcon#about to read 5, iclass 3, count 2 2006.173.19:55:45.31#ibcon#read 5, iclass 3, count 2 2006.173.19:55:45.31#ibcon#about to read 6, iclass 3, count 2 2006.173.19:55:45.31#ibcon#read 6, iclass 3, count 2 2006.173.19:55:45.31#ibcon#end of sib2, iclass 3, count 2 2006.173.19:55:45.31#ibcon#*mode == 0, iclass 3, count 2 2006.173.19:55:45.31#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.19:55:45.31#ibcon#[27=AT02-04\r\n] 2006.173.19:55:45.31#ibcon#*before write, iclass 3, count 2 2006.173.19:55:45.31#ibcon#enter sib2, iclass 3, count 2 2006.173.19:55:45.31#ibcon#flushed, iclass 3, count 2 2006.173.19:55:45.31#ibcon#about to write, iclass 3, count 2 2006.173.19:55:45.31#ibcon#wrote, iclass 3, count 2 2006.173.19:55:45.31#ibcon#about to read 3, iclass 3, count 2 2006.173.19:55:45.34#ibcon#read 3, iclass 3, count 2 2006.173.19:55:45.34#ibcon#about to read 4, iclass 3, count 2 2006.173.19:55:45.34#ibcon#read 4, iclass 3, count 2 2006.173.19:55:45.34#ibcon#about to read 5, iclass 3, count 2 2006.173.19:55:45.34#ibcon#read 5, iclass 3, count 2 2006.173.19:55:45.34#ibcon#about to read 6, iclass 3, count 2 2006.173.19:55:45.34#ibcon#read 6, iclass 3, count 2 2006.173.19:55:45.34#ibcon#end of sib2, iclass 3, count 2 2006.173.19:55:45.34#ibcon#*after write, iclass 3, count 2 2006.173.19:55:45.34#ibcon#*before return 0, iclass 3, count 2 2006.173.19:55:45.34#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.19:55:45.34#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.19:55:45.34#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.19:55:45.34#ibcon#ireg 7 cls_cnt 0 2006.173.19:55:45.34#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.19:55:45.46#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.19:55:45.46#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.19:55:45.46#ibcon#enter wrdev, iclass 3, count 0 2006.173.19:55:45.46#ibcon#first serial, iclass 3, count 0 2006.173.19:55:45.46#ibcon#enter sib2, iclass 3, count 0 2006.173.19:55:45.46#ibcon#flushed, iclass 3, count 0 2006.173.19:55:45.46#ibcon#about to write, iclass 3, count 0 2006.173.19:55:45.46#ibcon#wrote, iclass 3, count 0 2006.173.19:55:45.46#ibcon#about to read 3, iclass 3, count 0 2006.173.19:55:45.48#ibcon#read 3, iclass 3, count 0 2006.173.19:55:45.48#ibcon#about to read 4, iclass 3, count 0 2006.173.19:55:45.48#ibcon#read 4, iclass 3, count 0 2006.173.19:55:45.48#ibcon#about to read 5, iclass 3, count 0 2006.173.19:55:45.48#ibcon#read 5, iclass 3, count 0 2006.173.19:55:45.48#ibcon#about to read 6, iclass 3, count 0 2006.173.19:55:45.48#ibcon#read 6, iclass 3, count 0 2006.173.19:55:45.48#ibcon#end of sib2, iclass 3, count 0 2006.173.19:55:45.48#ibcon#*mode == 0, iclass 3, count 0 2006.173.19:55:45.48#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.19:55:45.48#ibcon#[27=USB\r\n] 2006.173.19:55:45.48#ibcon#*before write, iclass 3, count 0 2006.173.19:55:45.48#ibcon#enter sib2, iclass 3, count 0 2006.173.19:55:45.48#ibcon#flushed, iclass 3, count 0 2006.173.19:55:45.48#ibcon#about to write, iclass 3, count 0 2006.173.19:55:45.48#ibcon#wrote, iclass 3, count 0 2006.173.19:55:45.48#ibcon#about to read 3, iclass 3, count 0 2006.173.19:55:45.51#ibcon#read 3, iclass 3, count 0 2006.173.19:55:45.51#ibcon#about to read 4, iclass 3, count 0 2006.173.19:55:45.51#ibcon#read 4, iclass 3, count 0 2006.173.19:55:45.51#ibcon#about to read 5, iclass 3, count 0 2006.173.19:55:45.51#ibcon#read 5, iclass 3, count 0 2006.173.19:55:45.51#ibcon#about to read 6, iclass 3, count 0 2006.173.19:55:45.51#ibcon#read 6, iclass 3, count 0 2006.173.19:55:45.51#ibcon#end of sib2, iclass 3, count 0 2006.173.19:55:45.51#ibcon#*after write, iclass 3, count 0 2006.173.19:55:45.51#ibcon#*before return 0, iclass 3, count 0 2006.173.19:55:45.51#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.19:55:45.51#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.19:55:45.51#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.19:55:45.51#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.19:55:45.51$vck44/vblo=3,649.99 2006.173.19:55:45.51#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.19:55:45.51#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.19:55:45.51#ibcon#ireg 17 cls_cnt 0 2006.173.19:55:45.51#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.19:55:45.51#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.19:55:45.51#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.19:55:45.51#ibcon#enter wrdev, iclass 5, count 0 2006.173.19:55:45.51#ibcon#first serial, iclass 5, count 0 2006.173.19:55:45.51#ibcon#enter sib2, iclass 5, count 0 2006.173.19:55:45.51#ibcon#flushed, iclass 5, count 0 2006.173.19:55:45.51#ibcon#about to write, iclass 5, count 0 2006.173.19:55:45.51#ibcon#wrote, iclass 5, count 0 2006.173.19:55:45.51#ibcon#about to read 3, iclass 5, count 0 2006.173.19:55:45.53#ibcon#read 3, iclass 5, count 0 2006.173.19:55:45.53#ibcon#about to read 4, iclass 5, count 0 2006.173.19:55:45.53#ibcon#read 4, iclass 5, count 0 2006.173.19:55:45.53#ibcon#about to read 5, iclass 5, count 0 2006.173.19:55:45.53#ibcon#read 5, iclass 5, count 0 2006.173.19:55:45.53#ibcon#about to read 6, iclass 5, count 0 2006.173.19:55:45.53#ibcon#read 6, iclass 5, count 0 2006.173.19:55:45.53#ibcon#end of sib2, iclass 5, count 0 2006.173.19:55:45.53#ibcon#*mode == 0, iclass 5, count 0 2006.173.19:55:45.53#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.19:55:45.53#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.19:55:45.53#ibcon#*before write, iclass 5, count 0 2006.173.19:55:45.53#ibcon#enter sib2, iclass 5, count 0 2006.173.19:55:45.53#ibcon#flushed, iclass 5, count 0 2006.173.19:55:45.53#ibcon#about to write, iclass 5, count 0 2006.173.19:55:45.53#ibcon#wrote, iclass 5, count 0 2006.173.19:55:45.53#ibcon#about to read 3, iclass 5, count 0 2006.173.19:55:45.57#ibcon#read 3, iclass 5, count 0 2006.173.19:55:45.57#ibcon#about to read 4, iclass 5, count 0 2006.173.19:55:45.57#ibcon#read 4, iclass 5, count 0 2006.173.19:55:45.57#ibcon#about to read 5, iclass 5, count 0 2006.173.19:55:45.57#ibcon#read 5, iclass 5, count 0 2006.173.19:55:45.57#ibcon#about to read 6, iclass 5, count 0 2006.173.19:55:45.57#ibcon#read 6, iclass 5, count 0 2006.173.19:55:45.57#ibcon#end of sib2, iclass 5, count 0 2006.173.19:55:45.57#ibcon#*after write, iclass 5, count 0 2006.173.19:55:45.57#ibcon#*before return 0, iclass 5, count 0 2006.173.19:55:45.57#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.19:55:45.57#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.19:55:45.57#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.19:55:45.57#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.19:55:45.57$vck44/vb=3,4 2006.173.19:55:45.57#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.173.19:55:45.57#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.173.19:55:45.57#ibcon#ireg 11 cls_cnt 2 2006.173.19:55:45.57#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.19:55:45.63#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.19:55:45.63#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.19:55:45.63#ibcon#enter wrdev, iclass 7, count 2 2006.173.19:55:45.63#ibcon#first serial, iclass 7, count 2 2006.173.19:55:45.63#ibcon#enter sib2, iclass 7, count 2 2006.173.19:55:45.63#ibcon#flushed, iclass 7, count 2 2006.173.19:55:45.63#ibcon#about to write, iclass 7, count 2 2006.173.19:55:45.63#ibcon#wrote, iclass 7, count 2 2006.173.19:55:45.63#ibcon#about to read 3, iclass 7, count 2 2006.173.19:55:45.65#ibcon#read 3, iclass 7, count 2 2006.173.19:55:45.65#ibcon#about to read 4, iclass 7, count 2 2006.173.19:55:45.65#ibcon#read 4, iclass 7, count 2 2006.173.19:55:45.65#ibcon#about to read 5, iclass 7, count 2 2006.173.19:55:45.65#ibcon#read 5, iclass 7, count 2 2006.173.19:55:45.65#ibcon#about to read 6, iclass 7, count 2 2006.173.19:55:45.65#ibcon#read 6, iclass 7, count 2 2006.173.19:55:45.65#ibcon#end of sib2, iclass 7, count 2 2006.173.19:55:45.65#ibcon#*mode == 0, iclass 7, count 2 2006.173.19:55:45.65#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.173.19:55:45.65#ibcon#[27=AT03-04\r\n] 2006.173.19:55:45.65#ibcon#*before write, iclass 7, count 2 2006.173.19:55:45.65#ibcon#enter sib2, iclass 7, count 2 2006.173.19:55:45.65#ibcon#flushed, iclass 7, count 2 2006.173.19:55:45.65#ibcon#about to write, iclass 7, count 2 2006.173.19:55:45.65#ibcon#wrote, iclass 7, count 2 2006.173.19:55:45.65#ibcon#about to read 3, iclass 7, count 2 2006.173.19:55:45.68#ibcon#read 3, iclass 7, count 2 2006.173.19:55:45.68#ibcon#about to read 4, iclass 7, count 2 2006.173.19:55:45.68#ibcon#read 4, iclass 7, count 2 2006.173.19:55:45.68#ibcon#about to read 5, iclass 7, count 2 2006.173.19:55:45.68#ibcon#read 5, iclass 7, count 2 2006.173.19:55:45.68#ibcon#about to read 6, iclass 7, count 2 2006.173.19:55:45.68#ibcon#read 6, iclass 7, count 2 2006.173.19:55:45.68#ibcon#end of sib2, iclass 7, count 2 2006.173.19:55:45.68#ibcon#*after write, iclass 7, count 2 2006.173.19:55:45.68#ibcon#*before return 0, iclass 7, count 2 2006.173.19:55:45.68#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.19:55:45.68#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.173.19:55:45.68#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.173.19:55:45.68#ibcon#ireg 7 cls_cnt 0 2006.173.19:55:45.68#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.19:55:45.80#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.19:55:45.80#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.19:55:45.80#ibcon#enter wrdev, iclass 7, count 0 2006.173.19:55:45.80#ibcon#first serial, iclass 7, count 0 2006.173.19:55:45.80#ibcon#enter sib2, iclass 7, count 0 2006.173.19:55:45.80#ibcon#flushed, iclass 7, count 0 2006.173.19:55:45.80#ibcon#about to write, iclass 7, count 0 2006.173.19:55:45.80#ibcon#wrote, iclass 7, count 0 2006.173.19:55:45.80#ibcon#about to read 3, iclass 7, count 0 2006.173.19:55:45.82#ibcon#read 3, iclass 7, count 0 2006.173.19:55:45.82#ibcon#about to read 4, iclass 7, count 0 2006.173.19:55:45.82#ibcon#read 4, iclass 7, count 0 2006.173.19:55:45.82#ibcon#about to read 5, iclass 7, count 0 2006.173.19:55:45.82#ibcon#read 5, iclass 7, count 0 2006.173.19:55:45.82#ibcon#about to read 6, iclass 7, count 0 2006.173.19:55:45.82#ibcon#read 6, iclass 7, count 0 2006.173.19:55:45.82#ibcon#end of sib2, iclass 7, count 0 2006.173.19:55:45.82#ibcon#*mode == 0, iclass 7, count 0 2006.173.19:55:45.82#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.19:55:45.82#ibcon#[27=USB\r\n] 2006.173.19:55:45.82#ibcon#*before write, iclass 7, count 0 2006.173.19:55:45.82#ibcon#enter sib2, iclass 7, count 0 2006.173.19:55:45.82#ibcon#flushed, iclass 7, count 0 2006.173.19:55:45.82#ibcon#about to write, iclass 7, count 0 2006.173.19:55:45.82#ibcon#wrote, iclass 7, count 0 2006.173.19:55:45.82#ibcon#about to read 3, iclass 7, count 0 2006.173.19:55:45.85#ibcon#read 3, iclass 7, count 0 2006.173.19:55:45.85#ibcon#about to read 4, iclass 7, count 0 2006.173.19:55:45.85#ibcon#read 4, iclass 7, count 0 2006.173.19:55:45.85#ibcon#about to read 5, iclass 7, count 0 2006.173.19:55:45.85#ibcon#read 5, iclass 7, count 0 2006.173.19:55:45.85#ibcon#about to read 6, iclass 7, count 0 2006.173.19:55:45.85#ibcon#read 6, iclass 7, count 0 2006.173.19:55:45.85#ibcon#end of sib2, iclass 7, count 0 2006.173.19:55:45.85#ibcon#*after write, iclass 7, count 0 2006.173.19:55:45.85#ibcon#*before return 0, iclass 7, count 0 2006.173.19:55:45.85#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.19:55:45.85#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.173.19:55:45.85#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.19:55:45.85#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.19:55:45.85$vck44/vblo=4,679.99 2006.173.19:55:45.85#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.19:55:45.85#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.19:55:45.85#ibcon#ireg 17 cls_cnt 0 2006.173.19:55:45.85#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.19:55:45.85#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.19:55:45.85#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.19:55:45.85#ibcon#enter wrdev, iclass 11, count 0 2006.173.19:55:45.85#ibcon#first serial, iclass 11, count 0 2006.173.19:55:45.85#ibcon#enter sib2, iclass 11, count 0 2006.173.19:55:45.85#ibcon#flushed, iclass 11, count 0 2006.173.19:55:45.85#ibcon#about to write, iclass 11, count 0 2006.173.19:55:45.85#ibcon#wrote, iclass 11, count 0 2006.173.19:55:45.85#ibcon#about to read 3, iclass 11, count 0 2006.173.19:55:45.87#ibcon#read 3, iclass 11, count 0 2006.173.19:55:45.87#ibcon#about to read 4, iclass 11, count 0 2006.173.19:55:45.87#ibcon#read 4, iclass 11, count 0 2006.173.19:55:45.87#ibcon#about to read 5, iclass 11, count 0 2006.173.19:55:45.87#ibcon#read 5, iclass 11, count 0 2006.173.19:55:45.87#ibcon#about to read 6, iclass 11, count 0 2006.173.19:55:45.87#ibcon#read 6, iclass 11, count 0 2006.173.19:55:45.87#ibcon#end of sib2, iclass 11, count 0 2006.173.19:55:45.87#ibcon#*mode == 0, iclass 11, count 0 2006.173.19:55:45.87#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.19:55:45.87#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.19:55:45.87#ibcon#*before write, iclass 11, count 0 2006.173.19:55:45.87#ibcon#enter sib2, iclass 11, count 0 2006.173.19:55:45.87#ibcon#flushed, iclass 11, count 0 2006.173.19:55:45.87#ibcon#about to write, iclass 11, count 0 2006.173.19:55:45.87#ibcon#wrote, iclass 11, count 0 2006.173.19:55:45.87#ibcon#about to read 3, iclass 11, count 0 2006.173.19:55:45.91#ibcon#read 3, iclass 11, count 0 2006.173.19:55:45.91#ibcon#about to read 4, iclass 11, count 0 2006.173.19:55:45.91#ibcon#read 4, iclass 11, count 0 2006.173.19:55:45.91#ibcon#about to read 5, iclass 11, count 0 2006.173.19:55:45.91#ibcon#read 5, iclass 11, count 0 2006.173.19:55:45.91#ibcon#about to read 6, iclass 11, count 0 2006.173.19:55:45.91#ibcon#read 6, iclass 11, count 0 2006.173.19:55:45.91#ibcon#end of sib2, iclass 11, count 0 2006.173.19:55:45.91#ibcon#*after write, iclass 11, count 0 2006.173.19:55:45.91#ibcon#*before return 0, iclass 11, count 0 2006.173.19:55:45.91#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.19:55:45.91#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.19:55:45.91#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.19:55:45.91#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.19:55:45.91$vck44/vb=4,4 2006.173.19:55:45.91#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.173.19:55:45.91#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.173.19:55:45.91#ibcon#ireg 11 cls_cnt 2 2006.173.19:55:45.91#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.19:55:45.97#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.19:55:45.97#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.19:55:45.97#ibcon#enter wrdev, iclass 13, count 2 2006.173.19:55:45.97#ibcon#first serial, iclass 13, count 2 2006.173.19:55:45.97#ibcon#enter sib2, iclass 13, count 2 2006.173.19:55:45.97#ibcon#flushed, iclass 13, count 2 2006.173.19:55:45.97#ibcon#about to write, iclass 13, count 2 2006.173.19:55:45.97#ibcon#wrote, iclass 13, count 2 2006.173.19:55:45.97#ibcon#about to read 3, iclass 13, count 2 2006.173.19:55:45.99#ibcon#read 3, iclass 13, count 2 2006.173.19:55:45.99#ibcon#about to read 4, iclass 13, count 2 2006.173.19:55:45.99#ibcon#read 4, iclass 13, count 2 2006.173.19:55:45.99#ibcon#about to read 5, iclass 13, count 2 2006.173.19:55:45.99#ibcon#read 5, iclass 13, count 2 2006.173.19:55:45.99#ibcon#about to read 6, iclass 13, count 2 2006.173.19:55:45.99#ibcon#read 6, iclass 13, count 2 2006.173.19:55:45.99#ibcon#end of sib2, iclass 13, count 2 2006.173.19:55:45.99#ibcon#*mode == 0, iclass 13, count 2 2006.173.19:55:45.99#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.173.19:55:45.99#ibcon#[27=AT04-04\r\n] 2006.173.19:55:45.99#ibcon#*before write, iclass 13, count 2 2006.173.19:55:45.99#ibcon#enter sib2, iclass 13, count 2 2006.173.19:55:45.99#ibcon#flushed, iclass 13, count 2 2006.173.19:55:45.99#ibcon#about to write, iclass 13, count 2 2006.173.19:55:45.99#ibcon#wrote, iclass 13, count 2 2006.173.19:55:45.99#ibcon#about to read 3, iclass 13, count 2 2006.173.19:55:46.02#ibcon#read 3, iclass 13, count 2 2006.173.19:55:46.02#ibcon#about to read 4, iclass 13, count 2 2006.173.19:55:46.02#ibcon#read 4, iclass 13, count 2 2006.173.19:55:46.02#ibcon#about to read 5, iclass 13, count 2 2006.173.19:55:46.02#ibcon#read 5, iclass 13, count 2 2006.173.19:55:46.02#ibcon#about to read 6, iclass 13, count 2 2006.173.19:55:46.02#ibcon#read 6, iclass 13, count 2 2006.173.19:55:46.02#ibcon#end of sib2, iclass 13, count 2 2006.173.19:55:46.02#ibcon#*after write, iclass 13, count 2 2006.173.19:55:46.02#ibcon#*before return 0, iclass 13, count 2 2006.173.19:55:46.02#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.19:55:46.02#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.173.19:55:46.02#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.173.19:55:46.02#ibcon#ireg 7 cls_cnt 0 2006.173.19:55:46.02#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.19:55:46.14#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.19:55:46.14#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.19:55:46.14#ibcon#enter wrdev, iclass 13, count 0 2006.173.19:55:46.14#ibcon#first serial, iclass 13, count 0 2006.173.19:55:46.14#ibcon#enter sib2, iclass 13, count 0 2006.173.19:55:46.14#ibcon#flushed, iclass 13, count 0 2006.173.19:55:46.14#ibcon#about to write, iclass 13, count 0 2006.173.19:55:46.14#ibcon#wrote, iclass 13, count 0 2006.173.19:55:46.14#ibcon#about to read 3, iclass 13, count 0 2006.173.19:55:46.16#ibcon#read 3, iclass 13, count 0 2006.173.19:55:46.16#ibcon#about to read 4, iclass 13, count 0 2006.173.19:55:46.16#ibcon#read 4, iclass 13, count 0 2006.173.19:55:46.16#ibcon#about to read 5, iclass 13, count 0 2006.173.19:55:46.16#ibcon#read 5, iclass 13, count 0 2006.173.19:55:46.16#ibcon#about to read 6, iclass 13, count 0 2006.173.19:55:46.16#ibcon#read 6, iclass 13, count 0 2006.173.19:55:46.16#ibcon#end of sib2, iclass 13, count 0 2006.173.19:55:46.16#ibcon#*mode == 0, iclass 13, count 0 2006.173.19:55:46.16#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.19:55:46.16#ibcon#[27=USB\r\n] 2006.173.19:55:46.16#ibcon#*before write, iclass 13, count 0 2006.173.19:55:46.16#ibcon#enter sib2, iclass 13, count 0 2006.173.19:55:46.16#ibcon#flushed, iclass 13, count 0 2006.173.19:55:46.16#ibcon#about to write, iclass 13, count 0 2006.173.19:55:46.16#ibcon#wrote, iclass 13, count 0 2006.173.19:55:46.16#ibcon#about to read 3, iclass 13, count 0 2006.173.19:55:46.19#ibcon#read 3, iclass 13, count 0 2006.173.19:55:46.19#ibcon#about to read 4, iclass 13, count 0 2006.173.19:55:46.19#ibcon#read 4, iclass 13, count 0 2006.173.19:55:46.19#ibcon#about to read 5, iclass 13, count 0 2006.173.19:55:46.19#ibcon#read 5, iclass 13, count 0 2006.173.19:55:46.19#ibcon#about to read 6, iclass 13, count 0 2006.173.19:55:46.19#ibcon#read 6, iclass 13, count 0 2006.173.19:55:46.19#ibcon#end of sib2, iclass 13, count 0 2006.173.19:55:46.19#ibcon#*after write, iclass 13, count 0 2006.173.19:55:46.19#ibcon#*before return 0, iclass 13, count 0 2006.173.19:55:46.19#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.19:55:46.19#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.173.19:55:46.19#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.19:55:46.19#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.19:55:46.19$vck44/vblo=5,709.99 2006.173.19:55:46.19#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.19:55:46.19#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.19:55:46.19#ibcon#ireg 17 cls_cnt 0 2006.173.19:55:46.19#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.19:55:46.19#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.19:55:46.19#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.19:55:46.19#ibcon#enter wrdev, iclass 15, count 0 2006.173.19:55:46.19#ibcon#first serial, iclass 15, count 0 2006.173.19:55:46.19#ibcon#enter sib2, iclass 15, count 0 2006.173.19:55:46.19#ibcon#flushed, iclass 15, count 0 2006.173.19:55:46.19#ibcon#about to write, iclass 15, count 0 2006.173.19:55:46.19#ibcon#wrote, iclass 15, count 0 2006.173.19:55:46.19#ibcon#about to read 3, iclass 15, count 0 2006.173.19:55:46.21#ibcon#read 3, iclass 15, count 0 2006.173.19:55:46.21#ibcon#about to read 4, iclass 15, count 0 2006.173.19:55:46.21#ibcon#read 4, iclass 15, count 0 2006.173.19:55:46.21#ibcon#about to read 5, iclass 15, count 0 2006.173.19:55:46.21#ibcon#read 5, iclass 15, count 0 2006.173.19:55:46.21#ibcon#about to read 6, iclass 15, count 0 2006.173.19:55:46.21#ibcon#read 6, iclass 15, count 0 2006.173.19:55:46.21#ibcon#end of sib2, iclass 15, count 0 2006.173.19:55:46.21#ibcon#*mode == 0, iclass 15, count 0 2006.173.19:55:46.21#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.19:55:46.21#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.19:55:46.21#ibcon#*before write, iclass 15, count 0 2006.173.19:55:46.21#ibcon#enter sib2, iclass 15, count 0 2006.173.19:55:46.21#ibcon#flushed, iclass 15, count 0 2006.173.19:55:46.21#ibcon#about to write, iclass 15, count 0 2006.173.19:55:46.21#ibcon#wrote, iclass 15, count 0 2006.173.19:55:46.21#ibcon#about to read 3, iclass 15, count 0 2006.173.19:55:46.25#ibcon#read 3, iclass 15, count 0 2006.173.19:55:46.25#ibcon#about to read 4, iclass 15, count 0 2006.173.19:55:46.25#ibcon#read 4, iclass 15, count 0 2006.173.19:55:46.25#ibcon#about to read 5, iclass 15, count 0 2006.173.19:55:46.25#ibcon#read 5, iclass 15, count 0 2006.173.19:55:46.25#ibcon#about to read 6, iclass 15, count 0 2006.173.19:55:46.25#ibcon#read 6, iclass 15, count 0 2006.173.19:55:46.25#ibcon#end of sib2, iclass 15, count 0 2006.173.19:55:46.25#ibcon#*after write, iclass 15, count 0 2006.173.19:55:46.25#ibcon#*before return 0, iclass 15, count 0 2006.173.19:55:46.25#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.19:55:46.25#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.19:55:46.25#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.19:55:46.25#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.19:55:46.25$vck44/vb=5,4 2006.173.19:55:46.25#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.19:55:46.25#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.19:55:46.25#ibcon#ireg 11 cls_cnt 2 2006.173.19:55:46.25#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.19:55:46.31#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.19:55:46.31#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.19:55:46.31#ibcon#enter wrdev, iclass 17, count 2 2006.173.19:55:46.31#ibcon#first serial, iclass 17, count 2 2006.173.19:55:46.31#ibcon#enter sib2, iclass 17, count 2 2006.173.19:55:46.31#ibcon#flushed, iclass 17, count 2 2006.173.19:55:46.31#ibcon#about to write, iclass 17, count 2 2006.173.19:55:46.31#ibcon#wrote, iclass 17, count 2 2006.173.19:55:46.31#ibcon#about to read 3, iclass 17, count 2 2006.173.19:55:46.33#ibcon#read 3, iclass 17, count 2 2006.173.19:55:46.33#ibcon#about to read 4, iclass 17, count 2 2006.173.19:55:46.33#ibcon#read 4, iclass 17, count 2 2006.173.19:55:46.33#ibcon#about to read 5, iclass 17, count 2 2006.173.19:55:46.33#ibcon#read 5, iclass 17, count 2 2006.173.19:55:46.33#ibcon#about to read 6, iclass 17, count 2 2006.173.19:55:46.33#ibcon#read 6, iclass 17, count 2 2006.173.19:55:46.33#ibcon#end of sib2, iclass 17, count 2 2006.173.19:55:46.33#ibcon#*mode == 0, iclass 17, count 2 2006.173.19:55:46.33#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.19:55:46.33#ibcon#[27=AT05-04\r\n] 2006.173.19:55:46.33#ibcon#*before write, iclass 17, count 2 2006.173.19:55:46.33#ibcon#enter sib2, iclass 17, count 2 2006.173.19:55:46.33#ibcon#flushed, iclass 17, count 2 2006.173.19:55:46.33#ibcon#about to write, iclass 17, count 2 2006.173.19:55:46.33#ibcon#wrote, iclass 17, count 2 2006.173.19:55:46.33#ibcon#about to read 3, iclass 17, count 2 2006.173.19:55:46.36#ibcon#read 3, iclass 17, count 2 2006.173.19:55:46.36#ibcon#about to read 4, iclass 17, count 2 2006.173.19:55:46.36#ibcon#read 4, iclass 17, count 2 2006.173.19:55:46.36#ibcon#about to read 5, iclass 17, count 2 2006.173.19:55:46.36#ibcon#read 5, iclass 17, count 2 2006.173.19:55:46.36#ibcon#about to read 6, iclass 17, count 2 2006.173.19:55:46.36#ibcon#read 6, iclass 17, count 2 2006.173.19:55:46.36#ibcon#end of sib2, iclass 17, count 2 2006.173.19:55:46.36#ibcon#*after write, iclass 17, count 2 2006.173.19:55:46.36#ibcon#*before return 0, iclass 17, count 2 2006.173.19:55:46.36#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.19:55:46.36#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.19:55:46.36#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.19:55:46.36#ibcon#ireg 7 cls_cnt 0 2006.173.19:55:46.36#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.19:55:46.48#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.19:55:46.48#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.19:55:46.48#ibcon#enter wrdev, iclass 17, count 0 2006.173.19:55:46.48#ibcon#first serial, iclass 17, count 0 2006.173.19:55:46.48#ibcon#enter sib2, iclass 17, count 0 2006.173.19:55:46.48#ibcon#flushed, iclass 17, count 0 2006.173.19:55:46.48#ibcon#about to write, iclass 17, count 0 2006.173.19:55:46.48#ibcon#wrote, iclass 17, count 0 2006.173.19:55:46.48#ibcon#about to read 3, iclass 17, count 0 2006.173.19:55:46.50#ibcon#read 3, iclass 17, count 0 2006.173.19:55:46.50#ibcon#about to read 4, iclass 17, count 0 2006.173.19:55:46.50#ibcon#read 4, iclass 17, count 0 2006.173.19:55:46.50#ibcon#about to read 5, iclass 17, count 0 2006.173.19:55:46.50#ibcon#read 5, iclass 17, count 0 2006.173.19:55:46.50#ibcon#about to read 6, iclass 17, count 0 2006.173.19:55:46.50#ibcon#read 6, iclass 17, count 0 2006.173.19:55:46.50#ibcon#end of sib2, iclass 17, count 0 2006.173.19:55:46.50#ibcon#*mode == 0, iclass 17, count 0 2006.173.19:55:46.50#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.19:55:46.50#ibcon#[27=USB\r\n] 2006.173.19:55:46.50#ibcon#*before write, iclass 17, count 0 2006.173.19:55:46.50#ibcon#enter sib2, iclass 17, count 0 2006.173.19:55:46.50#ibcon#flushed, iclass 17, count 0 2006.173.19:55:46.50#ibcon#about to write, iclass 17, count 0 2006.173.19:55:46.50#ibcon#wrote, iclass 17, count 0 2006.173.19:55:46.50#ibcon#about to read 3, iclass 17, count 0 2006.173.19:55:46.53#ibcon#read 3, iclass 17, count 0 2006.173.19:55:46.53#ibcon#about to read 4, iclass 17, count 0 2006.173.19:55:46.53#ibcon#read 4, iclass 17, count 0 2006.173.19:55:46.53#ibcon#about to read 5, iclass 17, count 0 2006.173.19:55:46.53#ibcon#read 5, iclass 17, count 0 2006.173.19:55:46.53#ibcon#about to read 6, iclass 17, count 0 2006.173.19:55:46.53#ibcon#read 6, iclass 17, count 0 2006.173.19:55:46.53#ibcon#end of sib2, iclass 17, count 0 2006.173.19:55:46.53#ibcon#*after write, iclass 17, count 0 2006.173.19:55:46.53#ibcon#*before return 0, iclass 17, count 0 2006.173.19:55:46.53#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.19:55:46.53#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.19:55:46.53#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.19:55:46.53#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.19:55:46.53$vck44/vblo=6,719.99 2006.173.19:55:46.53#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.19:55:46.53#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.19:55:46.53#ibcon#ireg 17 cls_cnt 0 2006.173.19:55:46.53#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.19:55:46.53#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.19:55:46.53#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.19:55:46.53#ibcon#enter wrdev, iclass 19, count 0 2006.173.19:55:46.53#ibcon#first serial, iclass 19, count 0 2006.173.19:55:46.53#ibcon#enter sib2, iclass 19, count 0 2006.173.19:55:46.53#ibcon#flushed, iclass 19, count 0 2006.173.19:55:46.53#ibcon#about to write, iclass 19, count 0 2006.173.19:55:46.53#ibcon#wrote, iclass 19, count 0 2006.173.19:55:46.53#ibcon#about to read 3, iclass 19, count 0 2006.173.19:55:46.55#ibcon#read 3, iclass 19, count 0 2006.173.19:55:46.55#ibcon#about to read 4, iclass 19, count 0 2006.173.19:55:46.55#ibcon#read 4, iclass 19, count 0 2006.173.19:55:46.55#ibcon#about to read 5, iclass 19, count 0 2006.173.19:55:46.55#ibcon#read 5, iclass 19, count 0 2006.173.19:55:46.55#ibcon#about to read 6, iclass 19, count 0 2006.173.19:55:46.55#ibcon#read 6, iclass 19, count 0 2006.173.19:55:46.55#ibcon#end of sib2, iclass 19, count 0 2006.173.19:55:46.55#ibcon#*mode == 0, iclass 19, count 0 2006.173.19:55:46.55#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.19:55:46.55#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.19:55:46.55#ibcon#*before write, iclass 19, count 0 2006.173.19:55:46.55#ibcon#enter sib2, iclass 19, count 0 2006.173.19:55:46.55#ibcon#flushed, iclass 19, count 0 2006.173.19:55:46.55#ibcon#about to write, iclass 19, count 0 2006.173.19:55:46.55#ibcon#wrote, iclass 19, count 0 2006.173.19:55:46.55#ibcon#about to read 3, iclass 19, count 0 2006.173.19:55:46.59#ibcon#read 3, iclass 19, count 0 2006.173.19:55:46.59#ibcon#about to read 4, iclass 19, count 0 2006.173.19:55:46.59#ibcon#read 4, iclass 19, count 0 2006.173.19:55:46.59#ibcon#about to read 5, iclass 19, count 0 2006.173.19:55:46.59#ibcon#read 5, iclass 19, count 0 2006.173.19:55:46.59#ibcon#about to read 6, iclass 19, count 0 2006.173.19:55:46.59#ibcon#read 6, iclass 19, count 0 2006.173.19:55:46.59#ibcon#end of sib2, iclass 19, count 0 2006.173.19:55:46.59#ibcon#*after write, iclass 19, count 0 2006.173.19:55:46.59#ibcon#*before return 0, iclass 19, count 0 2006.173.19:55:46.59#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.19:55:46.59#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.19:55:46.59#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.19:55:46.59#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.19:55:46.59$vck44/vb=6,4 2006.173.19:55:46.59#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.19:55:46.59#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.19:55:46.59#ibcon#ireg 11 cls_cnt 2 2006.173.19:55:46.59#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.19:55:46.65#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.19:55:46.65#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.19:55:46.65#ibcon#enter wrdev, iclass 21, count 2 2006.173.19:55:46.65#ibcon#first serial, iclass 21, count 2 2006.173.19:55:46.65#ibcon#enter sib2, iclass 21, count 2 2006.173.19:55:46.65#ibcon#flushed, iclass 21, count 2 2006.173.19:55:46.65#ibcon#about to write, iclass 21, count 2 2006.173.19:55:46.65#ibcon#wrote, iclass 21, count 2 2006.173.19:55:46.65#ibcon#about to read 3, iclass 21, count 2 2006.173.19:55:46.67#ibcon#read 3, iclass 21, count 2 2006.173.19:55:46.67#ibcon#about to read 4, iclass 21, count 2 2006.173.19:55:46.67#ibcon#read 4, iclass 21, count 2 2006.173.19:55:46.67#ibcon#about to read 5, iclass 21, count 2 2006.173.19:55:46.67#ibcon#read 5, iclass 21, count 2 2006.173.19:55:46.67#ibcon#about to read 6, iclass 21, count 2 2006.173.19:55:46.67#ibcon#read 6, iclass 21, count 2 2006.173.19:55:46.67#ibcon#end of sib2, iclass 21, count 2 2006.173.19:55:46.67#ibcon#*mode == 0, iclass 21, count 2 2006.173.19:55:46.67#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.19:55:46.67#ibcon#[27=AT06-04\r\n] 2006.173.19:55:46.67#ibcon#*before write, iclass 21, count 2 2006.173.19:55:46.67#ibcon#enter sib2, iclass 21, count 2 2006.173.19:55:46.67#ibcon#flushed, iclass 21, count 2 2006.173.19:55:46.67#ibcon#about to write, iclass 21, count 2 2006.173.19:55:46.67#ibcon#wrote, iclass 21, count 2 2006.173.19:55:46.67#ibcon#about to read 3, iclass 21, count 2 2006.173.19:55:46.70#ibcon#read 3, iclass 21, count 2 2006.173.19:55:46.70#ibcon#about to read 4, iclass 21, count 2 2006.173.19:55:46.70#ibcon#read 4, iclass 21, count 2 2006.173.19:55:46.70#ibcon#about to read 5, iclass 21, count 2 2006.173.19:55:46.70#ibcon#read 5, iclass 21, count 2 2006.173.19:55:46.70#ibcon#about to read 6, iclass 21, count 2 2006.173.19:55:46.70#ibcon#read 6, iclass 21, count 2 2006.173.19:55:46.70#ibcon#end of sib2, iclass 21, count 2 2006.173.19:55:46.70#ibcon#*after write, iclass 21, count 2 2006.173.19:55:46.70#ibcon#*before return 0, iclass 21, count 2 2006.173.19:55:46.70#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.19:55:46.70#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.19:55:46.70#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.19:55:46.70#ibcon#ireg 7 cls_cnt 0 2006.173.19:55:46.70#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.19:55:46.82#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.19:55:46.82#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.19:55:46.82#ibcon#enter wrdev, iclass 21, count 0 2006.173.19:55:46.82#ibcon#first serial, iclass 21, count 0 2006.173.19:55:46.82#ibcon#enter sib2, iclass 21, count 0 2006.173.19:55:46.82#ibcon#flushed, iclass 21, count 0 2006.173.19:55:46.82#ibcon#about to write, iclass 21, count 0 2006.173.19:55:46.82#ibcon#wrote, iclass 21, count 0 2006.173.19:55:46.82#ibcon#about to read 3, iclass 21, count 0 2006.173.19:55:46.84#ibcon#read 3, iclass 21, count 0 2006.173.19:55:46.84#ibcon#about to read 4, iclass 21, count 0 2006.173.19:55:46.84#ibcon#read 4, iclass 21, count 0 2006.173.19:55:46.84#ibcon#about to read 5, iclass 21, count 0 2006.173.19:55:46.84#ibcon#read 5, iclass 21, count 0 2006.173.19:55:46.84#ibcon#about to read 6, iclass 21, count 0 2006.173.19:55:46.84#ibcon#read 6, iclass 21, count 0 2006.173.19:55:46.84#ibcon#end of sib2, iclass 21, count 0 2006.173.19:55:46.84#ibcon#*mode == 0, iclass 21, count 0 2006.173.19:55:46.84#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.19:55:46.84#ibcon#[27=USB\r\n] 2006.173.19:55:46.84#ibcon#*before write, iclass 21, count 0 2006.173.19:55:46.84#ibcon#enter sib2, iclass 21, count 0 2006.173.19:55:46.84#ibcon#flushed, iclass 21, count 0 2006.173.19:55:46.84#ibcon#about to write, iclass 21, count 0 2006.173.19:55:46.84#ibcon#wrote, iclass 21, count 0 2006.173.19:55:46.84#ibcon#about to read 3, iclass 21, count 0 2006.173.19:55:46.87#ibcon#read 3, iclass 21, count 0 2006.173.19:55:46.87#ibcon#about to read 4, iclass 21, count 0 2006.173.19:55:46.87#ibcon#read 4, iclass 21, count 0 2006.173.19:55:46.87#ibcon#about to read 5, iclass 21, count 0 2006.173.19:55:46.87#ibcon#read 5, iclass 21, count 0 2006.173.19:55:46.87#ibcon#about to read 6, iclass 21, count 0 2006.173.19:55:46.87#ibcon#read 6, iclass 21, count 0 2006.173.19:55:46.87#ibcon#end of sib2, iclass 21, count 0 2006.173.19:55:46.87#ibcon#*after write, iclass 21, count 0 2006.173.19:55:46.87#ibcon#*before return 0, iclass 21, count 0 2006.173.19:55:46.87#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.19:55:46.87#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.19:55:46.87#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.19:55:46.87#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.19:55:46.87$vck44/vblo=7,734.99 2006.173.19:55:46.87#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.19:55:46.87#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.19:55:46.87#ibcon#ireg 17 cls_cnt 0 2006.173.19:55:46.87#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.19:55:46.87#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.19:55:46.87#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.19:55:46.87#ibcon#enter wrdev, iclass 23, count 0 2006.173.19:55:46.87#ibcon#first serial, iclass 23, count 0 2006.173.19:55:46.87#ibcon#enter sib2, iclass 23, count 0 2006.173.19:55:46.87#ibcon#flushed, iclass 23, count 0 2006.173.19:55:46.87#ibcon#about to write, iclass 23, count 0 2006.173.19:55:46.87#ibcon#wrote, iclass 23, count 0 2006.173.19:55:46.87#ibcon#about to read 3, iclass 23, count 0 2006.173.19:55:46.89#ibcon#read 3, iclass 23, count 0 2006.173.19:55:46.89#ibcon#about to read 4, iclass 23, count 0 2006.173.19:55:46.89#ibcon#read 4, iclass 23, count 0 2006.173.19:55:46.89#ibcon#about to read 5, iclass 23, count 0 2006.173.19:55:46.89#ibcon#read 5, iclass 23, count 0 2006.173.19:55:46.89#ibcon#about to read 6, iclass 23, count 0 2006.173.19:55:46.89#ibcon#read 6, iclass 23, count 0 2006.173.19:55:46.89#ibcon#end of sib2, iclass 23, count 0 2006.173.19:55:46.89#ibcon#*mode == 0, iclass 23, count 0 2006.173.19:55:46.89#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.19:55:46.89#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.19:55:46.89#ibcon#*before write, iclass 23, count 0 2006.173.19:55:46.89#ibcon#enter sib2, iclass 23, count 0 2006.173.19:55:46.89#ibcon#flushed, iclass 23, count 0 2006.173.19:55:46.89#ibcon#about to write, iclass 23, count 0 2006.173.19:55:46.89#ibcon#wrote, iclass 23, count 0 2006.173.19:55:46.89#ibcon#about to read 3, iclass 23, count 0 2006.173.19:55:46.93#ibcon#read 3, iclass 23, count 0 2006.173.19:55:46.93#ibcon#about to read 4, iclass 23, count 0 2006.173.19:55:46.93#ibcon#read 4, iclass 23, count 0 2006.173.19:55:46.93#ibcon#about to read 5, iclass 23, count 0 2006.173.19:55:46.93#ibcon#read 5, iclass 23, count 0 2006.173.19:55:46.93#ibcon#about to read 6, iclass 23, count 0 2006.173.19:55:46.93#ibcon#read 6, iclass 23, count 0 2006.173.19:55:46.93#ibcon#end of sib2, iclass 23, count 0 2006.173.19:55:46.93#ibcon#*after write, iclass 23, count 0 2006.173.19:55:46.93#ibcon#*before return 0, iclass 23, count 0 2006.173.19:55:46.93#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.19:55:46.93#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.19:55:46.93#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.19:55:46.93#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.19:55:46.93$vck44/vb=7,4 2006.173.19:55:46.93#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.19:55:46.93#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.19:55:46.93#ibcon#ireg 11 cls_cnt 2 2006.173.19:55:46.93#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.19:55:46.99#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.19:55:46.99#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.19:55:46.99#ibcon#enter wrdev, iclass 25, count 2 2006.173.19:55:46.99#ibcon#first serial, iclass 25, count 2 2006.173.19:55:46.99#ibcon#enter sib2, iclass 25, count 2 2006.173.19:55:46.99#ibcon#flushed, iclass 25, count 2 2006.173.19:55:46.99#ibcon#about to write, iclass 25, count 2 2006.173.19:55:46.99#ibcon#wrote, iclass 25, count 2 2006.173.19:55:46.99#ibcon#about to read 3, iclass 25, count 2 2006.173.19:55:47.01#ibcon#read 3, iclass 25, count 2 2006.173.19:55:47.01#ibcon#about to read 4, iclass 25, count 2 2006.173.19:55:47.01#ibcon#read 4, iclass 25, count 2 2006.173.19:55:47.01#ibcon#about to read 5, iclass 25, count 2 2006.173.19:55:47.01#ibcon#read 5, iclass 25, count 2 2006.173.19:55:47.01#ibcon#about to read 6, iclass 25, count 2 2006.173.19:55:47.01#ibcon#read 6, iclass 25, count 2 2006.173.19:55:47.01#ibcon#end of sib2, iclass 25, count 2 2006.173.19:55:47.01#ibcon#*mode == 0, iclass 25, count 2 2006.173.19:55:47.01#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.19:55:47.01#ibcon#[27=AT07-04\r\n] 2006.173.19:55:47.01#ibcon#*before write, iclass 25, count 2 2006.173.19:55:47.01#ibcon#enter sib2, iclass 25, count 2 2006.173.19:55:47.01#ibcon#flushed, iclass 25, count 2 2006.173.19:55:47.01#ibcon#about to write, iclass 25, count 2 2006.173.19:55:47.01#ibcon#wrote, iclass 25, count 2 2006.173.19:55:47.01#ibcon#about to read 3, iclass 25, count 2 2006.173.19:55:47.04#ibcon#read 3, iclass 25, count 2 2006.173.19:55:47.04#ibcon#about to read 4, iclass 25, count 2 2006.173.19:55:47.04#ibcon#read 4, iclass 25, count 2 2006.173.19:55:47.04#ibcon#about to read 5, iclass 25, count 2 2006.173.19:55:47.04#ibcon#read 5, iclass 25, count 2 2006.173.19:55:47.04#ibcon#about to read 6, iclass 25, count 2 2006.173.19:55:47.04#ibcon#read 6, iclass 25, count 2 2006.173.19:55:47.04#ibcon#end of sib2, iclass 25, count 2 2006.173.19:55:47.04#ibcon#*after write, iclass 25, count 2 2006.173.19:55:47.04#ibcon#*before return 0, iclass 25, count 2 2006.173.19:55:47.04#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.19:55:47.04#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.19:55:47.04#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.19:55:47.04#ibcon#ireg 7 cls_cnt 0 2006.173.19:55:47.04#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.19:55:47.16#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.19:55:47.16#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.19:55:47.16#ibcon#enter wrdev, iclass 25, count 0 2006.173.19:55:47.16#ibcon#first serial, iclass 25, count 0 2006.173.19:55:47.16#ibcon#enter sib2, iclass 25, count 0 2006.173.19:55:47.16#ibcon#flushed, iclass 25, count 0 2006.173.19:55:47.16#ibcon#about to write, iclass 25, count 0 2006.173.19:55:47.16#ibcon#wrote, iclass 25, count 0 2006.173.19:55:47.16#ibcon#about to read 3, iclass 25, count 0 2006.173.19:55:47.18#ibcon#read 3, iclass 25, count 0 2006.173.19:55:47.18#ibcon#about to read 4, iclass 25, count 0 2006.173.19:55:47.18#ibcon#read 4, iclass 25, count 0 2006.173.19:55:47.18#ibcon#about to read 5, iclass 25, count 0 2006.173.19:55:47.18#ibcon#read 5, iclass 25, count 0 2006.173.19:55:47.18#ibcon#about to read 6, iclass 25, count 0 2006.173.19:55:47.18#ibcon#read 6, iclass 25, count 0 2006.173.19:55:47.18#ibcon#end of sib2, iclass 25, count 0 2006.173.19:55:47.18#ibcon#*mode == 0, iclass 25, count 0 2006.173.19:55:47.18#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.19:55:47.18#ibcon#[27=USB\r\n] 2006.173.19:55:47.18#ibcon#*before write, iclass 25, count 0 2006.173.19:55:47.18#ibcon#enter sib2, iclass 25, count 0 2006.173.19:55:47.18#ibcon#flushed, iclass 25, count 0 2006.173.19:55:47.18#ibcon#about to write, iclass 25, count 0 2006.173.19:55:47.18#ibcon#wrote, iclass 25, count 0 2006.173.19:55:47.18#ibcon#about to read 3, iclass 25, count 0 2006.173.19:55:47.21#ibcon#read 3, iclass 25, count 0 2006.173.19:55:47.21#ibcon#about to read 4, iclass 25, count 0 2006.173.19:55:47.21#ibcon#read 4, iclass 25, count 0 2006.173.19:55:47.21#ibcon#about to read 5, iclass 25, count 0 2006.173.19:55:47.21#ibcon#read 5, iclass 25, count 0 2006.173.19:55:47.21#ibcon#about to read 6, iclass 25, count 0 2006.173.19:55:47.21#ibcon#read 6, iclass 25, count 0 2006.173.19:55:47.21#ibcon#end of sib2, iclass 25, count 0 2006.173.19:55:47.21#ibcon#*after write, iclass 25, count 0 2006.173.19:55:47.21#ibcon#*before return 0, iclass 25, count 0 2006.173.19:55:47.21#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.19:55:47.21#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.19:55:47.21#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.19:55:47.21#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.19:55:47.21$vck44/vblo=8,744.99 2006.173.19:55:47.21#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.19:55:47.21#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.19:55:47.21#ibcon#ireg 17 cls_cnt 0 2006.173.19:55:47.21#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.19:55:47.21#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.19:55:47.21#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.19:55:47.21#ibcon#enter wrdev, iclass 27, count 0 2006.173.19:55:47.21#ibcon#first serial, iclass 27, count 0 2006.173.19:55:47.21#ibcon#enter sib2, iclass 27, count 0 2006.173.19:55:47.21#ibcon#flushed, iclass 27, count 0 2006.173.19:55:47.21#ibcon#about to write, iclass 27, count 0 2006.173.19:55:47.21#ibcon#wrote, iclass 27, count 0 2006.173.19:55:47.21#ibcon#about to read 3, iclass 27, count 0 2006.173.19:55:47.23#ibcon#read 3, iclass 27, count 0 2006.173.19:55:47.23#ibcon#about to read 4, iclass 27, count 0 2006.173.19:55:47.23#ibcon#read 4, iclass 27, count 0 2006.173.19:55:47.23#ibcon#about to read 5, iclass 27, count 0 2006.173.19:55:47.23#ibcon#read 5, iclass 27, count 0 2006.173.19:55:47.23#ibcon#about to read 6, iclass 27, count 0 2006.173.19:55:47.23#ibcon#read 6, iclass 27, count 0 2006.173.19:55:47.23#ibcon#end of sib2, iclass 27, count 0 2006.173.19:55:47.23#ibcon#*mode == 0, iclass 27, count 0 2006.173.19:55:47.23#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.19:55:47.23#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.19:55:47.23#ibcon#*before write, iclass 27, count 0 2006.173.19:55:47.23#ibcon#enter sib2, iclass 27, count 0 2006.173.19:55:47.23#ibcon#flushed, iclass 27, count 0 2006.173.19:55:47.23#ibcon#about to write, iclass 27, count 0 2006.173.19:55:47.23#ibcon#wrote, iclass 27, count 0 2006.173.19:55:47.23#ibcon#about to read 3, iclass 27, count 0 2006.173.19:55:47.27#ibcon#read 3, iclass 27, count 0 2006.173.19:55:47.27#ibcon#about to read 4, iclass 27, count 0 2006.173.19:55:47.27#ibcon#read 4, iclass 27, count 0 2006.173.19:55:47.27#ibcon#about to read 5, iclass 27, count 0 2006.173.19:55:47.27#ibcon#read 5, iclass 27, count 0 2006.173.19:55:47.27#ibcon#about to read 6, iclass 27, count 0 2006.173.19:55:47.27#ibcon#read 6, iclass 27, count 0 2006.173.19:55:47.27#ibcon#end of sib2, iclass 27, count 0 2006.173.19:55:47.27#ibcon#*after write, iclass 27, count 0 2006.173.19:55:47.27#ibcon#*before return 0, iclass 27, count 0 2006.173.19:55:47.27#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.19:55:47.27#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.19:55:47.27#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.19:55:47.27#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.19:55:47.27$vck44/vb=8,4 2006.173.19:55:47.27#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.19:55:47.27#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.19:55:47.27#ibcon#ireg 11 cls_cnt 2 2006.173.19:55:47.27#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.19:55:47.33#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.19:55:47.33#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.19:55:47.33#ibcon#enter wrdev, iclass 29, count 2 2006.173.19:55:47.33#ibcon#first serial, iclass 29, count 2 2006.173.19:55:47.33#ibcon#enter sib2, iclass 29, count 2 2006.173.19:55:47.33#ibcon#flushed, iclass 29, count 2 2006.173.19:55:47.33#ibcon#about to write, iclass 29, count 2 2006.173.19:55:47.33#ibcon#wrote, iclass 29, count 2 2006.173.19:55:47.33#ibcon#about to read 3, iclass 29, count 2 2006.173.19:55:47.35#ibcon#read 3, iclass 29, count 2 2006.173.19:55:47.35#ibcon#about to read 4, iclass 29, count 2 2006.173.19:55:47.35#ibcon#read 4, iclass 29, count 2 2006.173.19:55:47.35#ibcon#about to read 5, iclass 29, count 2 2006.173.19:55:47.35#ibcon#read 5, iclass 29, count 2 2006.173.19:55:47.35#ibcon#about to read 6, iclass 29, count 2 2006.173.19:55:47.35#ibcon#read 6, iclass 29, count 2 2006.173.19:55:47.35#ibcon#end of sib2, iclass 29, count 2 2006.173.19:55:47.35#ibcon#*mode == 0, iclass 29, count 2 2006.173.19:55:47.35#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.19:55:47.35#ibcon#[27=AT08-04\r\n] 2006.173.19:55:47.35#ibcon#*before write, iclass 29, count 2 2006.173.19:55:47.35#ibcon#enter sib2, iclass 29, count 2 2006.173.19:55:47.35#ibcon#flushed, iclass 29, count 2 2006.173.19:55:47.35#ibcon#about to write, iclass 29, count 2 2006.173.19:55:47.35#ibcon#wrote, iclass 29, count 2 2006.173.19:55:47.35#ibcon#about to read 3, iclass 29, count 2 2006.173.19:55:47.38#ibcon#read 3, iclass 29, count 2 2006.173.19:55:47.38#ibcon#about to read 4, iclass 29, count 2 2006.173.19:55:47.38#ibcon#read 4, iclass 29, count 2 2006.173.19:55:47.38#ibcon#about to read 5, iclass 29, count 2 2006.173.19:55:47.38#ibcon#read 5, iclass 29, count 2 2006.173.19:55:47.38#ibcon#about to read 6, iclass 29, count 2 2006.173.19:55:47.38#ibcon#read 6, iclass 29, count 2 2006.173.19:55:47.38#ibcon#end of sib2, iclass 29, count 2 2006.173.19:55:47.38#ibcon#*after write, iclass 29, count 2 2006.173.19:55:47.38#ibcon#*before return 0, iclass 29, count 2 2006.173.19:55:47.38#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.19:55:47.38#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.19:55:47.38#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.19:55:47.38#ibcon#ireg 7 cls_cnt 0 2006.173.19:55:47.38#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.19:55:47.50#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.19:55:47.50#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.19:55:47.50#ibcon#enter wrdev, iclass 29, count 0 2006.173.19:55:47.50#ibcon#first serial, iclass 29, count 0 2006.173.19:55:47.50#ibcon#enter sib2, iclass 29, count 0 2006.173.19:55:47.50#ibcon#flushed, iclass 29, count 0 2006.173.19:55:47.50#ibcon#about to write, iclass 29, count 0 2006.173.19:55:47.50#ibcon#wrote, iclass 29, count 0 2006.173.19:55:47.50#ibcon#about to read 3, iclass 29, count 0 2006.173.19:55:47.52#ibcon#read 3, iclass 29, count 0 2006.173.19:55:47.52#ibcon#about to read 4, iclass 29, count 0 2006.173.19:55:47.52#ibcon#read 4, iclass 29, count 0 2006.173.19:55:47.52#ibcon#about to read 5, iclass 29, count 0 2006.173.19:55:47.52#ibcon#read 5, iclass 29, count 0 2006.173.19:55:47.52#ibcon#about to read 6, iclass 29, count 0 2006.173.19:55:47.52#ibcon#read 6, iclass 29, count 0 2006.173.19:55:47.52#ibcon#end of sib2, iclass 29, count 0 2006.173.19:55:47.52#ibcon#*mode == 0, iclass 29, count 0 2006.173.19:55:47.52#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.19:55:47.52#ibcon#[27=USB\r\n] 2006.173.19:55:47.52#ibcon#*before write, iclass 29, count 0 2006.173.19:55:47.52#ibcon#enter sib2, iclass 29, count 0 2006.173.19:55:47.52#ibcon#flushed, iclass 29, count 0 2006.173.19:55:47.52#ibcon#about to write, iclass 29, count 0 2006.173.19:55:47.52#ibcon#wrote, iclass 29, count 0 2006.173.19:55:47.52#ibcon#about to read 3, iclass 29, count 0 2006.173.19:55:47.55#ibcon#read 3, iclass 29, count 0 2006.173.19:55:47.55#ibcon#about to read 4, iclass 29, count 0 2006.173.19:55:47.55#ibcon#read 4, iclass 29, count 0 2006.173.19:55:47.55#ibcon#about to read 5, iclass 29, count 0 2006.173.19:55:47.55#ibcon#read 5, iclass 29, count 0 2006.173.19:55:47.55#ibcon#about to read 6, iclass 29, count 0 2006.173.19:55:47.55#ibcon#read 6, iclass 29, count 0 2006.173.19:55:47.55#ibcon#end of sib2, iclass 29, count 0 2006.173.19:55:47.55#ibcon#*after write, iclass 29, count 0 2006.173.19:55:47.55#ibcon#*before return 0, iclass 29, count 0 2006.173.19:55:47.55#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.19:55:47.55#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.19:55:47.55#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.19:55:47.55#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.19:55:47.55$vck44/vabw=wide 2006.173.19:55:47.55#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.19:55:47.55#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.19:55:47.55#ibcon#ireg 8 cls_cnt 0 2006.173.19:55:47.55#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.19:55:47.55#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.19:55:47.55#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.19:55:47.55#ibcon#enter wrdev, iclass 31, count 0 2006.173.19:55:47.55#ibcon#first serial, iclass 31, count 0 2006.173.19:55:47.55#ibcon#enter sib2, iclass 31, count 0 2006.173.19:55:47.55#ibcon#flushed, iclass 31, count 0 2006.173.19:55:47.55#ibcon#about to write, iclass 31, count 0 2006.173.19:55:47.55#ibcon#wrote, iclass 31, count 0 2006.173.19:55:47.55#ibcon#about to read 3, iclass 31, count 0 2006.173.19:55:47.57#ibcon#read 3, iclass 31, count 0 2006.173.19:55:47.57#ibcon#about to read 4, iclass 31, count 0 2006.173.19:55:47.57#ibcon#read 4, iclass 31, count 0 2006.173.19:55:47.57#ibcon#about to read 5, iclass 31, count 0 2006.173.19:55:47.57#ibcon#read 5, iclass 31, count 0 2006.173.19:55:47.57#ibcon#about to read 6, iclass 31, count 0 2006.173.19:55:47.57#ibcon#read 6, iclass 31, count 0 2006.173.19:55:47.57#ibcon#end of sib2, iclass 31, count 0 2006.173.19:55:47.57#ibcon#*mode == 0, iclass 31, count 0 2006.173.19:55:47.57#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.19:55:47.57#ibcon#[25=BW32\r\n] 2006.173.19:55:47.57#ibcon#*before write, iclass 31, count 0 2006.173.19:55:47.57#ibcon#enter sib2, iclass 31, count 0 2006.173.19:55:47.57#ibcon#flushed, iclass 31, count 0 2006.173.19:55:47.57#ibcon#about to write, iclass 31, count 0 2006.173.19:55:47.57#ibcon#wrote, iclass 31, count 0 2006.173.19:55:47.57#ibcon#about to read 3, iclass 31, count 0 2006.173.19:55:47.60#ibcon#read 3, iclass 31, count 0 2006.173.19:55:47.60#ibcon#about to read 4, iclass 31, count 0 2006.173.19:55:47.60#ibcon#read 4, iclass 31, count 0 2006.173.19:55:47.60#ibcon#about to read 5, iclass 31, count 0 2006.173.19:55:47.60#ibcon#read 5, iclass 31, count 0 2006.173.19:55:47.60#ibcon#about to read 6, iclass 31, count 0 2006.173.19:55:47.60#ibcon#read 6, iclass 31, count 0 2006.173.19:55:47.60#ibcon#end of sib2, iclass 31, count 0 2006.173.19:55:47.60#ibcon#*after write, iclass 31, count 0 2006.173.19:55:47.60#ibcon#*before return 0, iclass 31, count 0 2006.173.19:55:47.60#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.19:55:47.60#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.19:55:47.60#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.19:55:47.60#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.19:55:47.60$vck44/vbbw=wide 2006.173.19:55:47.60#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.19:55:47.60#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.19:55:47.60#ibcon#ireg 8 cls_cnt 0 2006.173.19:55:47.60#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.19:55:47.67#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.19:55:47.67#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.19:55:47.67#ibcon#enter wrdev, iclass 33, count 0 2006.173.19:55:47.67#ibcon#first serial, iclass 33, count 0 2006.173.19:55:47.67#ibcon#enter sib2, iclass 33, count 0 2006.173.19:55:47.67#ibcon#flushed, iclass 33, count 0 2006.173.19:55:47.67#ibcon#about to write, iclass 33, count 0 2006.173.19:55:47.67#ibcon#wrote, iclass 33, count 0 2006.173.19:55:47.67#ibcon#about to read 3, iclass 33, count 0 2006.173.19:55:47.69#ibcon#read 3, iclass 33, count 0 2006.173.19:55:47.69#ibcon#about to read 4, iclass 33, count 0 2006.173.19:55:47.69#ibcon#read 4, iclass 33, count 0 2006.173.19:55:47.69#ibcon#about to read 5, iclass 33, count 0 2006.173.19:55:47.69#ibcon#read 5, iclass 33, count 0 2006.173.19:55:47.69#ibcon#about to read 6, iclass 33, count 0 2006.173.19:55:47.69#ibcon#read 6, iclass 33, count 0 2006.173.19:55:47.69#ibcon#end of sib2, iclass 33, count 0 2006.173.19:55:47.69#ibcon#*mode == 0, iclass 33, count 0 2006.173.19:55:47.69#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.19:55:47.69#ibcon#[27=BW32\r\n] 2006.173.19:55:47.69#ibcon#*before write, iclass 33, count 0 2006.173.19:55:47.69#ibcon#enter sib2, iclass 33, count 0 2006.173.19:55:47.69#ibcon#flushed, iclass 33, count 0 2006.173.19:55:47.69#ibcon#about to write, iclass 33, count 0 2006.173.19:55:47.69#ibcon#wrote, iclass 33, count 0 2006.173.19:55:47.69#ibcon#about to read 3, iclass 33, count 0 2006.173.19:55:47.72#ibcon#read 3, iclass 33, count 0 2006.173.19:55:47.72#ibcon#about to read 4, iclass 33, count 0 2006.173.19:55:47.72#ibcon#read 4, iclass 33, count 0 2006.173.19:55:47.72#ibcon#about to read 5, iclass 33, count 0 2006.173.19:55:47.72#ibcon#read 5, iclass 33, count 0 2006.173.19:55:47.72#ibcon#about to read 6, iclass 33, count 0 2006.173.19:55:47.72#ibcon#read 6, iclass 33, count 0 2006.173.19:55:47.72#ibcon#end of sib2, iclass 33, count 0 2006.173.19:55:47.72#ibcon#*after write, iclass 33, count 0 2006.173.19:55:47.72#ibcon#*before return 0, iclass 33, count 0 2006.173.19:55:47.72#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.19:55:47.72#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.19:55:47.72#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.19:55:47.72#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.19:55:47.72$setupk4/ifdk4 2006.173.19:55:47.72$ifdk4/lo= 2006.173.19:55:47.72$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.19:55:47.72$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.19:55:47.72$ifdk4/patch= 2006.173.19:55:47.73$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.19:55:47.73$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.19:55:47.73$setupk4/!*+20s 2006.173.19:55:52.87#abcon#<5=/06 0.7 1.2 19.291001002.6\r\n> 2006.173.19:55:52.89#abcon#{5=INTERFACE CLEAR} 2006.173.19:55:52.95#abcon#[5=S1D000X0/0*\r\n] 2006.173.19:56:02.23$setupk4/"tpicd 2006.173.19:56:02.23$setupk4/echo=off 2006.173.19:56:02.23$setupk4/xlog=off 2006.173.19:56:02.23:!2006.173.20:03:21 2006.173.19:56:03.13#trakl#Source acquired 2006.173.19:56:04.13#flagr#flagr/antenna,acquired 2006.173.20:03:21.00:preob 2006.173.20:03:21.13/onsource/TRACKING 2006.173.20:03:21.13:!2006.173.20:03:31 2006.173.20:03:31.00:"tape 2006.173.20:03:31.00:"st=record 2006.173.20:03:31.00:data_valid=on 2006.173.20:03:31.00:midob 2006.173.20:03:31.13/onsource/TRACKING 2006.173.20:03:31.13/wx/19.37,1002.7,100 2006.173.20:03:31.33/cable/+6.5158E-03 2006.173.20:03:32.42/va/01,07,usb,yes,38,41 2006.173.20:03:32.42/va/02,06,usb,yes,38,39 2006.173.20:03:32.42/va/03,05,usb,yes,48,50 2006.173.20:03:32.42/va/04,06,usb,yes,39,41 2006.173.20:03:32.42/va/05,04,usb,yes,30,31 2006.173.20:03:32.42/va/06,03,usb,yes,42,42 2006.173.20:03:32.42/va/07,04,usb,yes,34,36 2006.173.20:03:32.42/va/08,04,usb,yes,29,35 2006.173.20:03:32.65/valo/01,524.99,yes,locked 2006.173.20:03:32.65/valo/02,534.99,yes,locked 2006.173.20:03:32.65/valo/03,564.99,yes,locked 2006.173.20:03:32.65/valo/04,624.99,yes,locked 2006.173.20:03:32.65/valo/05,734.99,yes,locked 2006.173.20:03:32.65/valo/06,814.99,yes,locked 2006.173.20:03:32.65/valo/07,864.99,yes,locked 2006.173.20:03:32.65/valo/08,884.99,yes,locked 2006.173.20:03:33.74/vb/01,04,usb,yes,30,28 2006.173.20:03:33.74/vb/02,04,usb,yes,33,33 2006.173.20:03:33.74/vb/03,04,usb,yes,30,33 2006.173.20:03:33.74/vb/04,04,usb,yes,34,33 2006.173.20:03:33.74/vb/05,04,usb,yes,27,29 2006.173.20:03:33.74/vb/06,04,usb,yes,31,27 2006.173.20:03:33.74/vb/07,04,usb,yes,31,31 2006.173.20:03:33.74/vb/08,04,usb,yes,28,32 2006.173.20:03:33.98/vblo/01,629.99,yes,locked 2006.173.20:03:33.98/vblo/02,634.99,yes,locked 2006.173.20:03:33.98/vblo/03,649.99,yes,locked 2006.173.20:03:33.98/vblo/04,679.99,yes,locked 2006.173.20:03:33.98/vblo/05,709.99,yes,locked 2006.173.20:03:33.98/vblo/06,719.99,yes,locked 2006.173.20:03:33.98/vblo/07,734.99,yes,locked 2006.173.20:03:33.98/vblo/08,744.99,yes,locked 2006.173.20:03:34.13/vabw/8 2006.173.20:03:34.28/vbbw/8 2006.173.20:03:34.37/xfe/off,on,15.5 2006.173.20:03:34.75/ifatt/23,28,28,28 2006.173.20:03:35.07/fmout-gps/S +3.87E-07 2006.173.20:03:35.11:!2006.173.20:04:31 2006.173.20:04:31.00:data_valid=off 2006.173.20:04:31.00:"et 2006.173.20:04:31.00:!+3s 2006.173.20:04:34.01:"tape 2006.173.20:04:34.01:postob 2006.173.20:04:34.13/cable/+6.5142E-03 2006.173.20:04:34.13/wx/19.39,1002.7,100 2006.173.20:04:35.07/fmout-gps/S +3.87E-07 2006.173.20:04:35.07:scan_name=173-2009,jd0606,210 2006.173.20:04:35.07:source=0059+581,010245.76,582411.1,2000.0,ccw 2006.173.20:04:35.13#flagr#flagr/antenna,new-source 2006.173.20:04:36.14:checkk5 2006.173.20:04:36.50/chk_autoobs//k5ts1/ autoobs is running! 2006.173.20:04:36.88/chk_autoobs//k5ts2/ autoobs is running! 2006.173.20:04:37.29/chk_autoobs//k5ts3/ autoobs is running! 2006.173.20:04:37.69/chk_autoobs//k5ts4/ autoobs is running! 2006.173.20:04:38.08/chk_obsdata//k5ts1/T1732003??a.dat file size is correct (nominal:240MB, actual:236MB). 2006.173.20:04:38.49/chk_obsdata//k5ts2/T1732003??b.dat file size is correct (nominal:240MB, actual:236MB). 2006.173.20:04:38.90/chk_obsdata//k5ts3/T1732003??c.dat file size is correct (nominal:240MB, actual:236MB). 2006.173.20:04:39.31/chk_obsdata//k5ts4/T1732003??d.dat file size is correct (nominal:240MB, actual:236MB). 2006.173.20:04:40.05/k5log//k5ts1_log_newline 2006.173.20:04:40.74/k5log//k5ts2_log_newline 2006.173.20:04:41.48/k5log//k5ts3_log_newline 2006.173.20:04:42.20/k5log//k5ts4_log_newline 2006.173.20:04:42.23/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.20:04:42.23:setupk4=1 2006.173.20:04:42.23$setupk4/echo=on 2006.173.20:04:42.23$setupk4/pcalon 2006.173.20:04:42.23$pcalon/"no phase cal control is implemented here 2006.173.20:04:42.23$setupk4/"tpicd=stop 2006.173.20:04:42.23$setupk4/"rec=synch_on 2006.173.20:04:42.23$setupk4/"rec_mode=128 2006.173.20:04:42.23$setupk4/!* 2006.173.20:04:42.23$setupk4/recpk4 2006.173.20:04:42.23$recpk4/recpatch= 2006.173.20:04:42.23$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.20:04:42.23$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.20:04:42.23$setupk4/vck44 2006.173.20:04:42.23$vck44/valo=1,524.99 2006.173.20:04:42.23#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.20:04:42.23#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.20:04:42.23#ibcon#ireg 17 cls_cnt 0 2006.173.20:04:42.23#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.20:04:42.23#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.20:04:42.23#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.20:04:42.23#ibcon#enter wrdev, iclass 34, count 0 2006.173.20:04:42.23#ibcon#first serial, iclass 34, count 0 2006.173.20:04:42.23#ibcon#enter sib2, iclass 34, count 0 2006.173.20:04:42.23#ibcon#flushed, iclass 34, count 0 2006.173.20:04:42.23#ibcon#about to write, iclass 34, count 0 2006.173.20:04:42.23#ibcon#wrote, iclass 34, count 0 2006.173.20:04:42.23#ibcon#about to read 3, iclass 34, count 0 2006.173.20:04:42.25#ibcon#read 3, iclass 34, count 0 2006.173.20:04:42.25#ibcon#about to read 4, iclass 34, count 0 2006.173.20:04:42.25#ibcon#read 4, iclass 34, count 0 2006.173.20:04:42.25#ibcon#about to read 5, iclass 34, count 0 2006.173.20:04:42.25#ibcon#read 5, iclass 34, count 0 2006.173.20:04:42.25#ibcon#about to read 6, iclass 34, count 0 2006.173.20:04:42.25#ibcon#read 6, iclass 34, count 0 2006.173.20:04:42.25#ibcon#end of sib2, iclass 34, count 0 2006.173.20:04:42.25#ibcon#*mode == 0, iclass 34, count 0 2006.173.20:04:42.25#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.20:04:42.25#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.20:04:42.25#ibcon#*before write, iclass 34, count 0 2006.173.20:04:42.25#ibcon#enter sib2, iclass 34, count 0 2006.173.20:04:42.25#ibcon#flushed, iclass 34, count 0 2006.173.20:04:42.25#ibcon#about to write, iclass 34, count 0 2006.173.20:04:42.25#ibcon#wrote, iclass 34, count 0 2006.173.20:04:42.25#ibcon#about to read 3, iclass 34, count 0 2006.173.20:04:42.30#ibcon#read 3, iclass 34, count 0 2006.173.20:04:42.30#ibcon#about to read 4, iclass 34, count 0 2006.173.20:04:42.30#ibcon#read 4, iclass 34, count 0 2006.173.20:04:42.30#ibcon#about to read 5, iclass 34, count 0 2006.173.20:04:42.30#ibcon#read 5, iclass 34, count 0 2006.173.20:04:42.30#ibcon#about to read 6, iclass 34, count 0 2006.173.20:04:42.30#ibcon#read 6, iclass 34, count 0 2006.173.20:04:42.30#ibcon#end of sib2, iclass 34, count 0 2006.173.20:04:42.30#ibcon#*after write, iclass 34, count 0 2006.173.20:04:42.30#ibcon#*before return 0, iclass 34, count 0 2006.173.20:04:42.30#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.20:04:42.30#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.20:04:42.30#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.20:04:42.30#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.20:04:42.30$vck44/va=1,7 2006.173.20:04:42.30#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.20:04:42.30#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.20:04:42.30#ibcon#ireg 11 cls_cnt 2 2006.173.20:04:42.30#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.20:04:42.30#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.20:04:42.30#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.20:04:42.30#ibcon#enter wrdev, iclass 36, count 2 2006.173.20:04:42.30#ibcon#first serial, iclass 36, count 2 2006.173.20:04:42.30#ibcon#enter sib2, iclass 36, count 2 2006.173.20:04:42.30#ibcon#flushed, iclass 36, count 2 2006.173.20:04:42.30#ibcon#about to write, iclass 36, count 2 2006.173.20:04:42.30#ibcon#wrote, iclass 36, count 2 2006.173.20:04:42.30#ibcon#about to read 3, iclass 36, count 2 2006.173.20:04:42.32#ibcon#read 3, iclass 36, count 2 2006.173.20:04:42.32#ibcon#about to read 4, iclass 36, count 2 2006.173.20:04:42.32#ibcon#read 4, iclass 36, count 2 2006.173.20:04:42.32#ibcon#about to read 5, iclass 36, count 2 2006.173.20:04:42.32#ibcon#read 5, iclass 36, count 2 2006.173.20:04:42.32#ibcon#about to read 6, iclass 36, count 2 2006.173.20:04:42.32#ibcon#read 6, iclass 36, count 2 2006.173.20:04:42.32#ibcon#end of sib2, iclass 36, count 2 2006.173.20:04:42.32#ibcon#*mode == 0, iclass 36, count 2 2006.173.20:04:42.32#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.20:04:42.32#ibcon#[25=AT01-07\r\n] 2006.173.20:04:42.32#ibcon#*before write, iclass 36, count 2 2006.173.20:04:42.32#ibcon#enter sib2, iclass 36, count 2 2006.173.20:04:42.32#ibcon#flushed, iclass 36, count 2 2006.173.20:04:42.32#ibcon#about to write, iclass 36, count 2 2006.173.20:04:42.32#ibcon#wrote, iclass 36, count 2 2006.173.20:04:42.32#ibcon#about to read 3, iclass 36, count 2 2006.173.20:04:42.35#ibcon#read 3, iclass 36, count 2 2006.173.20:04:42.35#ibcon#about to read 4, iclass 36, count 2 2006.173.20:04:42.35#ibcon#read 4, iclass 36, count 2 2006.173.20:04:42.35#ibcon#about to read 5, iclass 36, count 2 2006.173.20:04:42.35#ibcon#read 5, iclass 36, count 2 2006.173.20:04:42.35#ibcon#about to read 6, iclass 36, count 2 2006.173.20:04:42.35#ibcon#read 6, iclass 36, count 2 2006.173.20:04:42.35#ibcon#end of sib2, iclass 36, count 2 2006.173.20:04:42.35#ibcon#*after write, iclass 36, count 2 2006.173.20:04:42.35#ibcon#*before return 0, iclass 36, count 2 2006.173.20:04:42.35#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.20:04:42.35#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.20:04:42.35#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.20:04:42.35#ibcon#ireg 7 cls_cnt 0 2006.173.20:04:42.35#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.20:04:42.47#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.20:04:42.47#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.20:04:42.47#ibcon#enter wrdev, iclass 36, count 0 2006.173.20:04:42.47#ibcon#first serial, iclass 36, count 0 2006.173.20:04:42.47#ibcon#enter sib2, iclass 36, count 0 2006.173.20:04:42.47#ibcon#flushed, iclass 36, count 0 2006.173.20:04:42.47#ibcon#about to write, iclass 36, count 0 2006.173.20:04:42.47#ibcon#wrote, iclass 36, count 0 2006.173.20:04:42.47#ibcon#about to read 3, iclass 36, count 0 2006.173.20:04:42.49#ibcon#read 3, iclass 36, count 0 2006.173.20:04:42.49#ibcon#about to read 4, iclass 36, count 0 2006.173.20:04:42.49#ibcon#read 4, iclass 36, count 0 2006.173.20:04:42.49#ibcon#about to read 5, iclass 36, count 0 2006.173.20:04:42.49#ibcon#read 5, iclass 36, count 0 2006.173.20:04:42.49#ibcon#about to read 6, iclass 36, count 0 2006.173.20:04:42.49#ibcon#read 6, iclass 36, count 0 2006.173.20:04:42.49#ibcon#end of sib2, iclass 36, count 0 2006.173.20:04:42.49#ibcon#*mode == 0, iclass 36, count 0 2006.173.20:04:42.49#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.20:04:42.49#ibcon#[25=USB\r\n] 2006.173.20:04:42.49#ibcon#*before write, iclass 36, count 0 2006.173.20:04:42.49#ibcon#enter sib2, iclass 36, count 0 2006.173.20:04:42.49#ibcon#flushed, iclass 36, count 0 2006.173.20:04:42.49#ibcon#about to write, iclass 36, count 0 2006.173.20:04:42.49#ibcon#wrote, iclass 36, count 0 2006.173.20:04:42.49#ibcon#about to read 3, iclass 36, count 0 2006.173.20:04:42.52#ibcon#read 3, iclass 36, count 0 2006.173.20:04:42.52#ibcon#about to read 4, iclass 36, count 0 2006.173.20:04:42.52#ibcon#read 4, iclass 36, count 0 2006.173.20:04:42.52#ibcon#about to read 5, iclass 36, count 0 2006.173.20:04:42.52#ibcon#read 5, iclass 36, count 0 2006.173.20:04:42.52#ibcon#about to read 6, iclass 36, count 0 2006.173.20:04:42.52#ibcon#read 6, iclass 36, count 0 2006.173.20:04:42.52#ibcon#end of sib2, iclass 36, count 0 2006.173.20:04:42.52#ibcon#*after write, iclass 36, count 0 2006.173.20:04:42.52#ibcon#*before return 0, iclass 36, count 0 2006.173.20:04:42.52#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.20:04:42.52#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.20:04:42.52#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.20:04:42.52#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.20:04:42.52$vck44/valo=2,534.99 2006.173.20:04:42.52#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.20:04:42.52#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.20:04:42.52#ibcon#ireg 17 cls_cnt 0 2006.173.20:04:42.52#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.20:04:42.52#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.20:04:42.52#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.20:04:42.52#ibcon#enter wrdev, iclass 38, count 0 2006.173.20:04:42.52#ibcon#first serial, iclass 38, count 0 2006.173.20:04:42.52#ibcon#enter sib2, iclass 38, count 0 2006.173.20:04:42.52#ibcon#flushed, iclass 38, count 0 2006.173.20:04:42.52#ibcon#about to write, iclass 38, count 0 2006.173.20:04:42.52#ibcon#wrote, iclass 38, count 0 2006.173.20:04:42.52#ibcon#about to read 3, iclass 38, count 0 2006.173.20:04:42.54#ibcon#read 3, iclass 38, count 0 2006.173.20:04:42.54#ibcon#about to read 4, iclass 38, count 0 2006.173.20:04:42.54#ibcon#read 4, iclass 38, count 0 2006.173.20:04:42.54#ibcon#about to read 5, iclass 38, count 0 2006.173.20:04:42.54#ibcon#read 5, iclass 38, count 0 2006.173.20:04:42.54#ibcon#about to read 6, iclass 38, count 0 2006.173.20:04:42.54#ibcon#read 6, iclass 38, count 0 2006.173.20:04:42.54#ibcon#end of sib2, iclass 38, count 0 2006.173.20:04:42.54#ibcon#*mode == 0, iclass 38, count 0 2006.173.20:04:42.54#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.20:04:42.54#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.20:04:42.54#ibcon#*before write, iclass 38, count 0 2006.173.20:04:42.54#ibcon#enter sib2, iclass 38, count 0 2006.173.20:04:42.54#ibcon#flushed, iclass 38, count 0 2006.173.20:04:42.54#ibcon#about to write, iclass 38, count 0 2006.173.20:04:42.54#ibcon#wrote, iclass 38, count 0 2006.173.20:04:42.54#ibcon#about to read 3, iclass 38, count 0 2006.173.20:04:42.58#ibcon#read 3, iclass 38, count 0 2006.173.20:04:42.58#ibcon#about to read 4, iclass 38, count 0 2006.173.20:04:42.58#ibcon#read 4, iclass 38, count 0 2006.173.20:04:42.58#ibcon#about to read 5, iclass 38, count 0 2006.173.20:04:42.58#ibcon#read 5, iclass 38, count 0 2006.173.20:04:42.58#ibcon#about to read 6, iclass 38, count 0 2006.173.20:04:42.58#ibcon#read 6, iclass 38, count 0 2006.173.20:04:42.58#ibcon#end of sib2, iclass 38, count 0 2006.173.20:04:42.58#ibcon#*after write, iclass 38, count 0 2006.173.20:04:42.58#ibcon#*before return 0, iclass 38, count 0 2006.173.20:04:42.58#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.20:04:42.58#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.20:04:42.58#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.20:04:42.58#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.20:04:42.58$vck44/va=2,6 2006.173.20:04:42.58#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.20:04:42.58#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.20:04:42.58#ibcon#ireg 11 cls_cnt 2 2006.173.20:04:42.58#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.20:04:42.64#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.20:04:42.64#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.20:04:42.64#ibcon#enter wrdev, iclass 40, count 2 2006.173.20:04:42.64#ibcon#first serial, iclass 40, count 2 2006.173.20:04:42.64#ibcon#enter sib2, iclass 40, count 2 2006.173.20:04:42.64#ibcon#flushed, iclass 40, count 2 2006.173.20:04:42.64#ibcon#about to write, iclass 40, count 2 2006.173.20:04:42.64#ibcon#wrote, iclass 40, count 2 2006.173.20:04:42.64#ibcon#about to read 3, iclass 40, count 2 2006.173.20:04:42.66#ibcon#read 3, iclass 40, count 2 2006.173.20:04:42.66#ibcon#about to read 4, iclass 40, count 2 2006.173.20:04:42.66#ibcon#read 4, iclass 40, count 2 2006.173.20:04:42.66#ibcon#about to read 5, iclass 40, count 2 2006.173.20:04:42.66#ibcon#read 5, iclass 40, count 2 2006.173.20:04:42.66#ibcon#about to read 6, iclass 40, count 2 2006.173.20:04:42.66#ibcon#read 6, iclass 40, count 2 2006.173.20:04:42.66#ibcon#end of sib2, iclass 40, count 2 2006.173.20:04:42.66#ibcon#*mode == 0, iclass 40, count 2 2006.173.20:04:42.66#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.20:04:42.66#ibcon#[25=AT02-06\r\n] 2006.173.20:04:42.66#ibcon#*before write, iclass 40, count 2 2006.173.20:04:42.66#ibcon#enter sib2, iclass 40, count 2 2006.173.20:04:42.66#ibcon#flushed, iclass 40, count 2 2006.173.20:04:42.66#ibcon#about to write, iclass 40, count 2 2006.173.20:04:42.66#ibcon#wrote, iclass 40, count 2 2006.173.20:04:42.66#ibcon#about to read 3, iclass 40, count 2 2006.173.20:04:42.69#ibcon#read 3, iclass 40, count 2 2006.173.20:04:42.69#ibcon#about to read 4, iclass 40, count 2 2006.173.20:04:42.69#ibcon#read 4, iclass 40, count 2 2006.173.20:04:42.69#ibcon#about to read 5, iclass 40, count 2 2006.173.20:04:42.69#ibcon#read 5, iclass 40, count 2 2006.173.20:04:42.69#ibcon#about to read 6, iclass 40, count 2 2006.173.20:04:42.69#ibcon#read 6, iclass 40, count 2 2006.173.20:04:42.69#ibcon#end of sib2, iclass 40, count 2 2006.173.20:04:42.69#ibcon#*after write, iclass 40, count 2 2006.173.20:04:42.69#ibcon#*before return 0, iclass 40, count 2 2006.173.20:04:42.69#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.20:04:42.69#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.20:04:42.69#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.20:04:42.69#ibcon#ireg 7 cls_cnt 0 2006.173.20:04:42.69#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.20:04:42.81#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.20:04:42.81#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.20:04:42.81#ibcon#enter wrdev, iclass 40, count 0 2006.173.20:04:42.81#ibcon#first serial, iclass 40, count 0 2006.173.20:04:42.81#ibcon#enter sib2, iclass 40, count 0 2006.173.20:04:42.81#ibcon#flushed, iclass 40, count 0 2006.173.20:04:42.81#ibcon#about to write, iclass 40, count 0 2006.173.20:04:42.81#ibcon#wrote, iclass 40, count 0 2006.173.20:04:42.81#ibcon#about to read 3, iclass 40, count 0 2006.173.20:04:42.83#ibcon#read 3, iclass 40, count 0 2006.173.20:04:42.83#ibcon#about to read 4, iclass 40, count 0 2006.173.20:04:42.83#ibcon#read 4, iclass 40, count 0 2006.173.20:04:42.83#ibcon#about to read 5, iclass 40, count 0 2006.173.20:04:42.83#ibcon#read 5, iclass 40, count 0 2006.173.20:04:42.83#ibcon#about to read 6, iclass 40, count 0 2006.173.20:04:42.83#ibcon#read 6, iclass 40, count 0 2006.173.20:04:42.83#ibcon#end of sib2, iclass 40, count 0 2006.173.20:04:42.83#ibcon#*mode == 0, iclass 40, count 0 2006.173.20:04:42.83#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.20:04:42.83#ibcon#[25=USB\r\n] 2006.173.20:04:42.83#ibcon#*before write, iclass 40, count 0 2006.173.20:04:42.83#ibcon#enter sib2, iclass 40, count 0 2006.173.20:04:42.83#ibcon#flushed, iclass 40, count 0 2006.173.20:04:42.83#ibcon#about to write, iclass 40, count 0 2006.173.20:04:42.83#ibcon#wrote, iclass 40, count 0 2006.173.20:04:42.83#ibcon#about to read 3, iclass 40, count 0 2006.173.20:04:42.86#ibcon#read 3, iclass 40, count 0 2006.173.20:04:42.86#ibcon#about to read 4, iclass 40, count 0 2006.173.20:04:42.86#ibcon#read 4, iclass 40, count 0 2006.173.20:04:42.86#ibcon#about to read 5, iclass 40, count 0 2006.173.20:04:42.86#ibcon#read 5, iclass 40, count 0 2006.173.20:04:42.86#ibcon#about to read 6, iclass 40, count 0 2006.173.20:04:42.86#ibcon#read 6, iclass 40, count 0 2006.173.20:04:42.86#ibcon#end of sib2, iclass 40, count 0 2006.173.20:04:42.86#ibcon#*after write, iclass 40, count 0 2006.173.20:04:42.86#ibcon#*before return 0, iclass 40, count 0 2006.173.20:04:42.86#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.20:04:42.86#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.20:04:42.86#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.20:04:42.86#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.20:04:42.86$vck44/valo=3,564.99 2006.173.20:04:42.86#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.20:04:42.86#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.20:04:42.86#ibcon#ireg 17 cls_cnt 0 2006.173.20:04:42.86#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.20:04:42.86#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.20:04:42.86#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.20:04:42.86#ibcon#enter wrdev, iclass 4, count 0 2006.173.20:04:42.86#ibcon#first serial, iclass 4, count 0 2006.173.20:04:42.86#ibcon#enter sib2, iclass 4, count 0 2006.173.20:04:42.86#ibcon#flushed, iclass 4, count 0 2006.173.20:04:42.86#ibcon#about to write, iclass 4, count 0 2006.173.20:04:42.86#ibcon#wrote, iclass 4, count 0 2006.173.20:04:42.86#ibcon#about to read 3, iclass 4, count 0 2006.173.20:04:42.88#ibcon#read 3, iclass 4, count 0 2006.173.20:04:42.88#ibcon#about to read 4, iclass 4, count 0 2006.173.20:04:42.88#ibcon#read 4, iclass 4, count 0 2006.173.20:04:42.88#ibcon#about to read 5, iclass 4, count 0 2006.173.20:04:42.88#ibcon#read 5, iclass 4, count 0 2006.173.20:04:42.88#ibcon#about to read 6, iclass 4, count 0 2006.173.20:04:42.88#ibcon#read 6, iclass 4, count 0 2006.173.20:04:42.88#ibcon#end of sib2, iclass 4, count 0 2006.173.20:04:42.88#ibcon#*mode == 0, iclass 4, count 0 2006.173.20:04:42.88#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.20:04:42.88#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.20:04:42.88#ibcon#*before write, iclass 4, count 0 2006.173.20:04:42.88#ibcon#enter sib2, iclass 4, count 0 2006.173.20:04:42.88#ibcon#flushed, iclass 4, count 0 2006.173.20:04:42.88#ibcon#about to write, iclass 4, count 0 2006.173.20:04:42.88#ibcon#wrote, iclass 4, count 0 2006.173.20:04:42.88#ibcon#about to read 3, iclass 4, count 0 2006.173.20:04:42.92#ibcon#read 3, iclass 4, count 0 2006.173.20:04:42.92#ibcon#about to read 4, iclass 4, count 0 2006.173.20:04:42.92#ibcon#read 4, iclass 4, count 0 2006.173.20:04:42.92#ibcon#about to read 5, iclass 4, count 0 2006.173.20:04:42.92#ibcon#read 5, iclass 4, count 0 2006.173.20:04:42.92#ibcon#about to read 6, iclass 4, count 0 2006.173.20:04:42.92#ibcon#read 6, iclass 4, count 0 2006.173.20:04:42.92#ibcon#end of sib2, iclass 4, count 0 2006.173.20:04:42.92#ibcon#*after write, iclass 4, count 0 2006.173.20:04:42.92#ibcon#*before return 0, iclass 4, count 0 2006.173.20:04:42.92#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.20:04:42.92#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.20:04:42.92#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.20:04:42.92#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.20:04:42.92$vck44/va=3,5 2006.173.20:04:42.92#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.20:04:42.92#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.20:04:42.92#ibcon#ireg 11 cls_cnt 2 2006.173.20:04:42.92#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.20:04:42.98#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.20:04:42.98#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.20:04:42.98#ibcon#enter wrdev, iclass 6, count 2 2006.173.20:04:42.98#ibcon#first serial, iclass 6, count 2 2006.173.20:04:42.98#ibcon#enter sib2, iclass 6, count 2 2006.173.20:04:42.98#ibcon#flushed, iclass 6, count 2 2006.173.20:04:42.98#ibcon#about to write, iclass 6, count 2 2006.173.20:04:42.98#ibcon#wrote, iclass 6, count 2 2006.173.20:04:42.98#ibcon#about to read 3, iclass 6, count 2 2006.173.20:04:43.00#ibcon#read 3, iclass 6, count 2 2006.173.20:04:43.00#ibcon#about to read 4, iclass 6, count 2 2006.173.20:04:43.00#ibcon#read 4, iclass 6, count 2 2006.173.20:04:43.00#ibcon#about to read 5, iclass 6, count 2 2006.173.20:04:43.00#ibcon#read 5, iclass 6, count 2 2006.173.20:04:43.00#ibcon#about to read 6, iclass 6, count 2 2006.173.20:04:43.00#ibcon#read 6, iclass 6, count 2 2006.173.20:04:43.00#ibcon#end of sib2, iclass 6, count 2 2006.173.20:04:43.00#ibcon#*mode == 0, iclass 6, count 2 2006.173.20:04:43.00#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.20:04:43.00#ibcon#[25=AT03-05\r\n] 2006.173.20:04:43.00#ibcon#*before write, iclass 6, count 2 2006.173.20:04:43.00#ibcon#enter sib2, iclass 6, count 2 2006.173.20:04:43.00#ibcon#flushed, iclass 6, count 2 2006.173.20:04:43.00#ibcon#about to write, iclass 6, count 2 2006.173.20:04:43.00#ibcon#wrote, iclass 6, count 2 2006.173.20:04:43.00#ibcon#about to read 3, iclass 6, count 2 2006.173.20:04:43.03#ibcon#read 3, iclass 6, count 2 2006.173.20:04:43.03#ibcon#about to read 4, iclass 6, count 2 2006.173.20:04:43.03#ibcon#read 4, iclass 6, count 2 2006.173.20:04:43.03#ibcon#about to read 5, iclass 6, count 2 2006.173.20:04:43.03#ibcon#read 5, iclass 6, count 2 2006.173.20:04:43.03#ibcon#about to read 6, iclass 6, count 2 2006.173.20:04:43.03#ibcon#read 6, iclass 6, count 2 2006.173.20:04:43.03#ibcon#end of sib2, iclass 6, count 2 2006.173.20:04:43.03#ibcon#*after write, iclass 6, count 2 2006.173.20:04:43.03#ibcon#*before return 0, iclass 6, count 2 2006.173.20:04:43.03#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.20:04:43.03#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.20:04:43.03#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.20:04:43.03#ibcon#ireg 7 cls_cnt 0 2006.173.20:04:43.03#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.20:04:43.15#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.20:04:43.15#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.20:04:43.15#ibcon#enter wrdev, iclass 6, count 0 2006.173.20:04:43.15#ibcon#first serial, iclass 6, count 0 2006.173.20:04:43.15#ibcon#enter sib2, iclass 6, count 0 2006.173.20:04:43.15#ibcon#flushed, iclass 6, count 0 2006.173.20:04:43.15#ibcon#about to write, iclass 6, count 0 2006.173.20:04:43.15#ibcon#wrote, iclass 6, count 0 2006.173.20:04:43.15#ibcon#about to read 3, iclass 6, count 0 2006.173.20:04:43.17#ibcon#read 3, iclass 6, count 0 2006.173.20:04:43.17#ibcon#about to read 4, iclass 6, count 0 2006.173.20:04:43.17#ibcon#read 4, iclass 6, count 0 2006.173.20:04:43.17#ibcon#about to read 5, iclass 6, count 0 2006.173.20:04:43.17#ibcon#read 5, iclass 6, count 0 2006.173.20:04:43.17#ibcon#about to read 6, iclass 6, count 0 2006.173.20:04:43.17#ibcon#read 6, iclass 6, count 0 2006.173.20:04:43.17#ibcon#end of sib2, iclass 6, count 0 2006.173.20:04:43.17#ibcon#*mode == 0, iclass 6, count 0 2006.173.20:04:43.17#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.20:04:43.17#ibcon#[25=USB\r\n] 2006.173.20:04:43.17#ibcon#*before write, iclass 6, count 0 2006.173.20:04:43.17#ibcon#enter sib2, iclass 6, count 0 2006.173.20:04:43.17#ibcon#flushed, iclass 6, count 0 2006.173.20:04:43.17#ibcon#about to write, iclass 6, count 0 2006.173.20:04:43.17#ibcon#wrote, iclass 6, count 0 2006.173.20:04:43.17#ibcon#about to read 3, iclass 6, count 0 2006.173.20:04:43.20#ibcon#read 3, iclass 6, count 0 2006.173.20:04:43.20#ibcon#about to read 4, iclass 6, count 0 2006.173.20:04:43.20#ibcon#read 4, iclass 6, count 0 2006.173.20:04:43.20#ibcon#about to read 5, iclass 6, count 0 2006.173.20:04:43.20#ibcon#read 5, iclass 6, count 0 2006.173.20:04:43.20#ibcon#about to read 6, iclass 6, count 0 2006.173.20:04:43.20#ibcon#read 6, iclass 6, count 0 2006.173.20:04:43.20#ibcon#end of sib2, iclass 6, count 0 2006.173.20:04:43.20#ibcon#*after write, iclass 6, count 0 2006.173.20:04:43.20#ibcon#*before return 0, iclass 6, count 0 2006.173.20:04:43.20#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.20:04:43.20#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.20:04:43.20#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.20:04:43.20#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.20:04:43.20$vck44/valo=4,624.99 2006.173.20:04:43.20#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.20:04:43.20#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.20:04:43.20#ibcon#ireg 17 cls_cnt 0 2006.173.20:04:43.20#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.20:04:43.20#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.20:04:43.20#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.20:04:43.20#ibcon#enter wrdev, iclass 10, count 0 2006.173.20:04:43.20#ibcon#first serial, iclass 10, count 0 2006.173.20:04:43.20#ibcon#enter sib2, iclass 10, count 0 2006.173.20:04:43.20#ibcon#flushed, iclass 10, count 0 2006.173.20:04:43.20#ibcon#about to write, iclass 10, count 0 2006.173.20:04:43.20#ibcon#wrote, iclass 10, count 0 2006.173.20:04:43.20#ibcon#about to read 3, iclass 10, count 0 2006.173.20:04:43.22#ibcon#read 3, iclass 10, count 0 2006.173.20:04:43.22#ibcon#about to read 4, iclass 10, count 0 2006.173.20:04:43.22#ibcon#read 4, iclass 10, count 0 2006.173.20:04:43.22#ibcon#about to read 5, iclass 10, count 0 2006.173.20:04:43.22#ibcon#read 5, iclass 10, count 0 2006.173.20:04:43.22#ibcon#about to read 6, iclass 10, count 0 2006.173.20:04:43.22#ibcon#read 6, iclass 10, count 0 2006.173.20:04:43.22#ibcon#end of sib2, iclass 10, count 0 2006.173.20:04:43.22#ibcon#*mode == 0, iclass 10, count 0 2006.173.20:04:43.22#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.20:04:43.22#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.20:04:43.22#ibcon#*before write, iclass 10, count 0 2006.173.20:04:43.22#ibcon#enter sib2, iclass 10, count 0 2006.173.20:04:43.22#ibcon#flushed, iclass 10, count 0 2006.173.20:04:43.22#ibcon#about to write, iclass 10, count 0 2006.173.20:04:43.22#ibcon#wrote, iclass 10, count 0 2006.173.20:04:43.22#ibcon#about to read 3, iclass 10, count 0 2006.173.20:04:43.26#ibcon#read 3, iclass 10, count 0 2006.173.20:04:43.26#ibcon#about to read 4, iclass 10, count 0 2006.173.20:04:43.26#ibcon#read 4, iclass 10, count 0 2006.173.20:04:43.26#ibcon#about to read 5, iclass 10, count 0 2006.173.20:04:43.26#ibcon#read 5, iclass 10, count 0 2006.173.20:04:43.26#ibcon#about to read 6, iclass 10, count 0 2006.173.20:04:43.26#ibcon#read 6, iclass 10, count 0 2006.173.20:04:43.26#ibcon#end of sib2, iclass 10, count 0 2006.173.20:04:43.26#ibcon#*after write, iclass 10, count 0 2006.173.20:04:43.26#ibcon#*before return 0, iclass 10, count 0 2006.173.20:04:43.26#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.20:04:43.26#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.20:04:43.26#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.20:04:43.26#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.20:04:43.26$vck44/va=4,6 2006.173.20:04:43.26#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.20:04:43.26#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.20:04:43.26#ibcon#ireg 11 cls_cnt 2 2006.173.20:04:43.26#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.20:04:43.32#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.20:04:43.32#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.20:04:43.32#ibcon#enter wrdev, iclass 12, count 2 2006.173.20:04:43.32#ibcon#first serial, iclass 12, count 2 2006.173.20:04:43.32#ibcon#enter sib2, iclass 12, count 2 2006.173.20:04:43.32#ibcon#flushed, iclass 12, count 2 2006.173.20:04:43.32#ibcon#about to write, iclass 12, count 2 2006.173.20:04:43.32#ibcon#wrote, iclass 12, count 2 2006.173.20:04:43.32#ibcon#about to read 3, iclass 12, count 2 2006.173.20:04:43.34#ibcon#read 3, iclass 12, count 2 2006.173.20:04:43.34#ibcon#about to read 4, iclass 12, count 2 2006.173.20:04:43.34#ibcon#read 4, iclass 12, count 2 2006.173.20:04:43.34#ibcon#about to read 5, iclass 12, count 2 2006.173.20:04:43.34#ibcon#read 5, iclass 12, count 2 2006.173.20:04:43.34#ibcon#about to read 6, iclass 12, count 2 2006.173.20:04:43.34#ibcon#read 6, iclass 12, count 2 2006.173.20:04:43.34#ibcon#end of sib2, iclass 12, count 2 2006.173.20:04:43.34#ibcon#*mode == 0, iclass 12, count 2 2006.173.20:04:43.34#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.20:04:43.34#ibcon#[25=AT04-06\r\n] 2006.173.20:04:43.34#ibcon#*before write, iclass 12, count 2 2006.173.20:04:43.34#ibcon#enter sib2, iclass 12, count 2 2006.173.20:04:43.34#ibcon#flushed, iclass 12, count 2 2006.173.20:04:43.34#ibcon#about to write, iclass 12, count 2 2006.173.20:04:43.34#ibcon#wrote, iclass 12, count 2 2006.173.20:04:43.34#ibcon#about to read 3, iclass 12, count 2 2006.173.20:04:43.37#ibcon#read 3, iclass 12, count 2 2006.173.20:04:43.37#ibcon#about to read 4, iclass 12, count 2 2006.173.20:04:43.37#ibcon#read 4, iclass 12, count 2 2006.173.20:04:43.37#ibcon#about to read 5, iclass 12, count 2 2006.173.20:04:43.37#ibcon#read 5, iclass 12, count 2 2006.173.20:04:43.37#ibcon#about to read 6, iclass 12, count 2 2006.173.20:04:43.37#ibcon#read 6, iclass 12, count 2 2006.173.20:04:43.37#ibcon#end of sib2, iclass 12, count 2 2006.173.20:04:43.37#ibcon#*after write, iclass 12, count 2 2006.173.20:04:43.37#ibcon#*before return 0, iclass 12, count 2 2006.173.20:04:43.37#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.20:04:43.37#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.20:04:43.37#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.20:04:43.37#ibcon#ireg 7 cls_cnt 0 2006.173.20:04:43.37#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.20:04:43.49#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.20:04:43.49#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.20:04:43.49#ibcon#enter wrdev, iclass 12, count 0 2006.173.20:04:43.49#ibcon#first serial, iclass 12, count 0 2006.173.20:04:43.49#ibcon#enter sib2, iclass 12, count 0 2006.173.20:04:43.49#ibcon#flushed, iclass 12, count 0 2006.173.20:04:43.49#ibcon#about to write, iclass 12, count 0 2006.173.20:04:43.49#ibcon#wrote, iclass 12, count 0 2006.173.20:04:43.49#ibcon#about to read 3, iclass 12, count 0 2006.173.20:04:43.51#ibcon#read 3, iclass 12, count 0 2006.173.20:04:43.51#ibcon#about to read 4, iclass 12, count 0 2006.173.20:04:43.51#ibcon#read 4, iclass 12, count 0 2006.173.20:04:43.51#ibcon#about to read 5, iclass 12, count 0 2006.173.20:04:43.51#ibcon#read 5, iclass 12, count 0 2006.173.20:04:43.51#ibcon#about to read 6, iclass 12, count 0 2006.173.20:04:43.51#ibcon#read 6, iclass 12, count 0 2006.173.20:04:43.51#ibcon#end of sib2, iclass 12, count 0 2006.173.20:04:43.51#ibcon#*mode == 0, iclass 12, count 0 2006.173.20:04:43.51#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.20:04:43.51#ibcon#[25=USB\r\n] 2006.173.20:04:43.51#ibcon#*before write, iclass 12, count 0 2006.173.20:04:43.51#ibcon#enter sib2, iclass 12, count 0 2006.173.20:04:43.51#ibcon#flushed, iclass 12, count 0 2006.173.20:04:43.51#ibcon#about to write, iclass 12, count 0 2006.173.20:04:43.51#ibcon#wrote, iclass 12, count 0 2006.173.20:04:43.51#ibcon#about to read 3, iclass 12, count 0 2006.173.20:04:43.54#ibcon#read 3, iclass 12, count 0 2006.173.20:04:43.54#ibcon#about to read 4, iclass 12, count 0 2006.173.20:04:43.54#ibcon#read 4, iclass 12, count 0 2006.173.20:04:43.54#ibcon#about to read 5, iclass 12, count 0 2006.173.20:04:43.54#ibcon#read 5, iclass 12, count 0 2006.173.20:04:43.54#ibcon#about to read 6, iclass 12, count 0 2006.173.20:04:43.54#ibcon#read 6, iclass 12, count 0 2006.173.20:04:43.54#ibcon#end of sib2, iclass 12, count 0 2006.173.20:04:43.54#ibcon#*after write, iclass 12, count 0 2006.173.20:04:43.54#ibcon#*before return 0, iclass 12, count 0 2006.173.20:04:43.54#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.20:04:43.54#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.20:04:43.54#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.20:04:43.54#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.20:04:43.54$vck44/valo=5,734.99 2006.173.20:04:43.54#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.20:04:43.54#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.20:04:43.54#ibcon#ireg 17 cls_cnt 0 2006.173.20:04:43.54#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.20:04:43.54#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.20:04:43.54#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.20:04:43.54#ibcon#enter wrdev, iclass 14, count 0 2006.173.20:04:43.54#ibcon#first serial, iclass 14, count 0 2006.173.20:04:43.54#ibcon#enter sib2, iclass 14, count 0 2006.173.20:04:43.54#ibcon#flushed, iclass 14, count 0 2006.173.20:04:43.54#ibcon#about to write, iclass 14, count 0 2006.173.20:04:43.54#ibcon#wrote, iclass 14, count 0 2006.173.20:04:43.54#ibcon#about to read 3, iclass 14, count 0 2006.173.20:04:43.56#ibcon#read 3, iclass 14, count 0 2006.173.20:04:43.56#ibcon#about to read 4, iclass 14, count 0 2006.173.20:04:43.56#ibcon#read 4, iclass 14, count 0 2006.173.20:04:43.56#ibcon#about to read 5, iclass 14, count 0 2006.173.20:04:43.56#ibcon#read 5, iclass 14, count 0 2006.173.20:04:43.56#ibcon#about to read 6, iclass 14, count 0 2006.173.20:04:43.56#ibcon#read 6, iclass 14, count 0 2006.173.20:04:43.56#ibcon#end of sib2, iclass 14, count 0 2006.173.20:04:43.56#ibcon#*mode == 0, iclass 14, count 0 2006.173.20:04:43.56#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.20:04:43.56#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.20:04:43.56#ibcon#*before write, iclass 14, count 0 2006.173.20:04:43.56#ibcon#enter sib2, iclass 14, count 0 2006.173.20:04:43.56#ibcon#flushed, iclass 14, count 0 2006.173.20:04:43.56#ibcon#about to write, iclass 14, count 0 2006.173.20:04:43.56#ibcon#wrote, iclass 14, count 0 2006.173.20:04:43.56#ibcon#about to read 3, iclass 14, count 0 2006.173.20:04:43.60#ibcon#read 3, iclass 14, count 0 2006.173.20:04:43.60#ibcon#about to read 4, iclass 14, count 0 2006.173.20:04:43.60#ibcon#read 4, iclass 14, count 0 2006.173.20:04:43.60#ibcon#about to read 5, iclass 14, count 0 2006.173.20:04:43.60#ibcon#read 5, iclass 14, count 0 2006.173.20:04:43.60#ibcon#about to read 6, iclass 14, count 0 2006.173.20:04:43.60#ibcon#read 6, iclass 14, count 0 2006.173.20:04:43.60#ibcon#end of sib2, iclass 14, count 0 2006.173.20:04:43.60#ibcon#*after write, iclass 14, count 0 2006.173.20:04:43.60#ibcon#*before return 0, iclass 14, count 0 2006.173.20:04:43.60#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.20:04:43.60#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.20:04:43.60#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.20:04:43.60#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.20:04:43.60$vck44/va=5,4 2006.173.20:04:43.60#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.20:04:43.60#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.20:04:43.60#ibcon#ireg 11 cls_cnt 2 2006.173.20:04:43.60#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.20:04:43.66#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.20:04:43.66#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.20:04:43.66#ibcon#enter wrdev, iclass 16, count 2 2006.173.20:04:43.66#ibcon#first serial, iclass 16, count 2 2006.173.20:04:43.66#ibcon#enter sib2, iclass 16, count 2 2006.173.20:04:43.66#ibcon#flushed, iclass 16, count 2 2006.173.20:04:43.66#ibcon#about to write, iclass 16, count 2 2006.173.20:04:43.66#ibcon#wrote, iclass 16, count 2 2006.173.20:04:43.66#ibcon#about to read 3, iclass 16, count 2 2006.173.20:04:43.68#ibcon#read 3, iclass 16, count 2 2006.173.20:04:43.68#ibcon#about to read 4, iclass 16, count 2 2006.173.20:04:43.68#ibcon#read 4, iclass 16, count 2 2006.173.20:04:43.68#ibcon#about to read 5, iclass 16, count 2 2006.173.20:04:43.68#ibcon#read 5, iclass 16, count 2 2006.173.20:04:43.68#ibcon#about to read 6, iclass 16, count 2 2006.173.20:04:43.68#ibcon#read 6, iclass 16, count 2 2006.173.20:04:43.68#ibcon#end of sib2, iclass 16, count 2 2006.173.20:04:43.68#ibcon#*mode == 0, iclass 16, count 2 2006.173.20:04:43.68#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.20:04:43.68#ibcon#[25=AT05-04\r\n] 2006.173.20:04:43.68#ibcon#*before write, iclass 16, count 2 2006.173.20:04:43.68#ibcon#enter sib2, iclass 16, count 2 2006.173.20:04:43.68#ibcon#flushed, iclass 16, count 2 2006.173.20:04:43.68#ibcon#about to write, iclass 16, count 2 2006.173.20:04:43.68#ibcon#wrote, iclass 16, count 2 2006.173.20:04:43.68#ibcon#about to read 3, iclass 16, count 2 2006.173.20:04:43.71#ibcon#read 3, iclass 16, count 2 2006.173.20:04:43.71#ibcon#about to read 4, iclass 16, count 2 2006.173.20:04:43.71#ibcon#read 4, iclass 16, count 2 2006.173.20:04:43.71#ibcon#about to read 5, iclass 16, count 2 2006.173.20:04:43.71#ibcon#read 5, iclass 16, count 2 2006.173.20:04:43.71#ibcon#about to read 6, iclass 16, count 2 2006.173.20:04:43.71#ibcon#read 6, iclass 16, count 2 2006.173.20:04:43.71#ibcon#end of sib2, iclass 16, count 2 2006.173.20:04:43.71#ibcon#*after write, iclass 16, count 2 2006.173.20:04:43.71#ibcon#*before return 0, iclass 16, count 2 2006.173.20:04:43.71#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.20:04:43.71#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.20:04:43.71#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.20:04:43.71#ibcon#ireg 7 cls_cnt 0 2006.173.20:04:43.71#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.20:04:43.83#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.20:04:43.83#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.20:04:43.83#ibcon#enter wrdev, iclass 16, count 0 2006.173.20:04:43.83#ibcon#first serial, iclass 16, count 0 2006.173.20:04:43.83#ibcon#enter sib2, iclass 16, count 0 2006.173.20:04:43.83#ibcon#flushed, iclass 16, count 0 2006.173.20:04:43.83#ibcon#about to write, iclass 16, count 0 2006.173.20:04:43.83#ibcon#wrote, iclass 16, count 0 2006.173.20:04:43.83#ibcon#about to read 3, iclass 16, count 0 2006.173.20:04:43.85#ibcon#read 3, iclass 16, count 0 2006.173.20:04:43.85#ibcon#about to read 4, iclass 16, count 0 2006.173.20:04:43.85#ibcon#read 4, iclass 16, count 0 2006.173.20:04:43.85#ibcon#about to read 5, iclass 16, count 0 2006.173.20:04:43.85#ibcon#read 5, iclass 16, count 0 2006.173.20:04:43.85#ibcon#about to read 6, iclass 16, count 0 2006.173.20:04:43.85#ibcon#read 6, iclass 16, count 0 2006.173.20:04:43.85#ibcon#end of sib2, iclass 16, count 0 2006.173.20:04:43.85#ibcon#*mode == 0, iclass 16, count 0 2006.173.20:04:43.85#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.20:04:43.85#ibcon#[25=USB\r\n] 2006.173.20:04:43.85#ibcon#*before write, iclass 16, count 0 2006.173.20:04:43.85#ibcon#enter sib2, iclass 16, count 0 2006.173.20:04:43.85#ibcon#flushed, iclass 16, count 0 2006.173.20:04:43.85#ibcon#about to write, iclass 16, count 0 2006.173.20:04:43.85#ibcon#wrote, iclass 16, count 0 2006.173.20:04:43.85#ibcon#about to read 3, iclass 16, count 0 2006.173.20:04:43.88#ibcon#read 3, iclass 16, count 0 2006.173.20:04:43.88#ibcon#about to read 4, iclass 16, count 0 2006.173.20:04:43.88#ibcon#read 4, iclass 16, count 0 2006.173.20:04:43.88#ibcon#about to read 5, iclass 16, count 0 2006.173.20:04:43.88#ibcon#read 5, iclass 16, count 0 2006.173.20:04:43.88#ibcon#about to read 6, iclass 16, count 0 2006.173.20:04:43.88#ibcon#read 6, iclass 16, count 0 2006.173.20:04:43.88#ibcon#end of sib2, iclass 16, count 0 2006.173.20:04:43.88#ibcon#*after write, iclass 16, count 0 2006.173.20:04:43.88#ibcon#*before return 0, iclass 16, count 0 2006.173.20:04:43.88#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.20:04:43.88#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.20:04:43.88#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.20:04:43.88#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.20:04:43.88$vck44/valo=6,814.99 2006.173.20:04:43.88#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.20:04:43.88#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.20:04:43.88#ibcon#ireg 17 cls_cnt 0 2006.173.20:04:43.88#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.20:04:43.88#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.20:04:43.88#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.20:04:43.88#ibcon#enter wrdev, iclass 18, count 0 2006.173.20:04:43.88#ibcon#first serial, iclass 18, count 0 2006.173.20:04:43.88#ibcon#enter sib2, iclass 18, count 0 2006.173.20:04:43.88#ibcon#flushed, iclass 18, count 0 2006.173.20:04:43.88#ibcon#about to write, iclass 18, count 0 2006.173.20:04:43.88#ibcon#wrote, iclass 18, count 0 2006.173.20:04:43.88#ibcon#about to read 3, iclass 18, count 0 2006.173.20:04:43.90#ibcon#read 3, iclass 18, count 0 2006.173.20:04:43.90#ibcon#about to read 4, iclass 18, count 0 2006.173.20:04:43.90#ibcon#read 4, iclass 18, count 0 2006.173.20:04:43.90#ibcon#about to read 5, iclass 18, count 0 2006.173.20:04:43.90#ibcon#read 5, iclass 18, count 0 2006.173.20:04:43.90#ibcon#about to read 6, iclass 18, count 0 2006.173.20:04:43.90#ibcon#read 6, iclass 18, count 0 2006.173.20:04:43.90#ibcon#end of sib2, iclass 18, count 0 2006.173.20:04:43.90#ibcon#*mode == 0, iclass 18, count 0 2006.173.20:04:43.90#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.20:04:43.90#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.20:04:43.90#ibcon#*before write, iclass 18, count 0 2006.173.20:04:43.90#ibcon#enter sib2, iclass 18, count 0 2006.173.20:04:43.90#ibcon#flushed, iclass 18, count 0 2006.173.20:04:43.90#ibcon#about to write, iclass 18, count 0 2006.173.20:04:43.90#ibcon#wrote, iclass 18, count 0 2006.173.20:04:43.90#ibcon#about to read 3, iclass 18, count 0 2006.173.20:04:43.94#ibcon#read 3, iclass 18, count 0 2006.173.20:04:43.94#ibcon#about to read 4, iclass 18, count 0 2006.173.20:04:43.94#ibcon#read 4, iclass 18, count 0 2006.173.20:04:43.94#ibcon#about to read 5, iclass 18, count 0 2006.173.20:04:43.94#ibcon#read 5, iclass 18, count 0 2006.173.20:04:43.94#ibcon#about to read 6, iclass 18, count 0 2006.173.20:04:43.94#ibcon#read 6, iclass 18, count 0 2006.173.20:04:43.94#ibcon#end of sib2, iclass 18, count 0 2006.173.20:04:43.94#ibcon#*after write, iclass 18, count 0 2006.173.20:04:43.94#ibcon#*before return 0, iclass 18, count 0 2006.173.20:04:43.94#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.20:04:43.94#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.20:04:43.94#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.20:04:43.94#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.20:04:43.94$vck44/va=6,3 2006.173.20:04:43.94#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.20:04:43.94#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.20:04:43.94#ibcon#ireg 11 cls_cnt 2 2006.173.20:04:43.94#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.20:04:44.00#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.20:04:44.00#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.20:04:44.00#ibcon#enter wrdev, iclass 20, count 2 2006.173.20:04:44.00#ibcon#first serial, iclass 20, count 2 2006.173.20:04:44.00#ibcon#enter sib2, iclass 20, count 2 2006.173.20:04:44.00#ibcon#flushed, iclass 20, count 2 2006.173.20:04:44.00#ibcon#about to write, iclass 20, count 2 2006.173.20:04:44.00#ibcon#wrote, iclass 20, count 2 2006.173.20:04:44.00#ibcon#about to read 3, iclass 20, count 2 2006.173.20:04:44.02#ibcon#read 3, iclass 20, count 2 2006.173.20:04:44.02#ibcon#about to read 4, iclass 20, count 2 2006.173.20:04:44.02#ibcon#read 4, iclass 20, count 2 2006.173.20:04:44.02#ibcon#about to read 5, iclass 20, count 2 2006.173.20:04:44.02#ibcon#read 5, iclass 20, count 2 2006.173.20:04:44.02#ibcon#about to read 6, iclass 20, count 2 2006.173.20:04:44.02#ibcon#read 6, iclass 20, count 2 2006.173.20:04:44.02#ibcon#end of sib2, iclass 20, count 2 2006.173.20:04:44.02#ibcon#*mode == 0, iclass 20, count 2 2006.173.20:04:44.02#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.20:04:44.02#ibcon#[25=AT06-03\r\n] 2006.173.20:04:44.02#ibcon#*before write, iclass 20, count 2 2006.173.20:04:44.02#ibcon#enter sib2, iclass 20, count 2 2006.173.20:04:44.02#ibcon#flushed, iclass 20, count 2 2006.173.20:04:44.02#ibcon#about to write, iclass 20, count 2 2006.173.20:04:44.02#ibcon#wrote, iclass 20, count 2 2006.173.20:04:44.02#ibcon#about to read 3, iclass 20, count 2 2006.173.20:04:44.05#ibcon#read 3, iclass 20, count 2 2006.173.20:04:44.05#ibcon#about to read 4, iclass 20, count 2 2006.173.20:04:44.05#ibcon#read 4, iclass 20, count 2 2006.173.20:04:44.05#ibcon#about to read 5, iclass 20, count 2 2006.173.20:04:44.05#ibcon#read 5, iclass 20, count 2 2006.173.20:04:44.05#ibcon#about to read 6, iclass 20, count 2 2006.173.20:04:44.05#ibcon#read 6, iclass 20, count 2 2006.173.20:04:44.05#ibcon#end of sib2, iclass 20, count 2 2006.173.20:04:44.05#ibcon#*after write, iclass 20, count 2 2006.173.20:04:44.05#ibcon#*before return 0, iclass 20, count 2 2006.173.20:04:44.05#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.20:04:44.05#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.20:04:44.05#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.20:04:44.05#ibcon#ireg 7 cls_cnt 0 2006.173.20:04:44.05#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.20:04:44.17#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.20:04:44.17#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.20:04:44.17#ibcon#enter wrdev, iclass 20, count 0 2006.173.20:04:44.17#ibcon#first serial, iclass 20, count 0 2006.173.20:04:44.17#ibcon#enter sib2, iclass 20, count 0 2006.173.20:04:44.17#ibcon#flushed, iclass 20, count 0 2006.173.20:04:44.17#ibcon#about to write, iclass 20, count 0 2006.173.20:04:44.17#ibcon#wrote, iclass 20, count 0 2006.173.20:04:44.17#ibcon#about to read 3, iclass 20, count 0 2006.173.20:04:44.19#ibcon#read 3, iclass 20, count 0 2006.173.20:04:44.19#ibcon#about to read 4, iclass 20, count 0 2006.173.20:04:44.19#ibcon#read 4, iclass 20, count 0 2006.173.20:04:44.19#ibcon#about to read 5, iclass 20, count 0 2006.173.20:04:44.19#ibcon#read 5, iclass 20, count 0 2006.173.20:04:44.19#ibcon#about to read 6, iclass 20, count 0 2006.173.20:04:44.19#ibcon#read 6, iclass 20, count 0 2006.173.20:04:44.19#ibcon#end of sib2, iclass 20, count 0 2006.173.20:04:44.19#ibcon#*mode == 0, iclass 20, count 0 2006.173.20:04:44.19#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.20:04:44.19#ibcon#[25=USB\r\n] 2006.173.20:04:44.19#ibcon#*before write, iclass 20, count 0 2006.173.20:04:44.19#ibcon#enter sib2, iclass 20, count 0 2006.173.20:04:44.19#ibcon#flushed, iclass 20, count 0 2006.173.20:04:44.19#ibcon#about to write, iclass 20, count 0 2006.173.20:04:44.19#ibcon#wrote, iclass 20, count 0 2006.173.20:04:44.19#ibcon#about to read 3, iclass 20, count 0 2006.173.20:04:44.22#ibcon#read 3, iclass 20, count 0 2006.173.20:04:44.22#ibcon#about to read 4, iclass 20, count 0 2006.173.20:04:44.22#ibcon#read 4, iclass 20, count 0 2006.173.20:04:44.22#ibcon#about to read 5, iclass 20, count 0 2006.173.20:04:44.22#ibcon#read 5, iclass 20, count 0 2006.173.20:04:44.22#ibcon#about to read 6, iclass 20, count 0 2006.173.20:04:44.22#ibcon#read 6, iclass 20, count 0 2006.173.20:04:44.22#ibcon#end of sib2, iclass 20, count 0 2006.173.20:04:44.22#ibcon#*after write, iclass 20, count 0 2006.173.20:04:44.22#ibcon#*before return 0, iclass 20, count 0 2006.173.20:04:44.22#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.20:04:44.22#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.20:04:44.22#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.20:04:44.22#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.20:04:44.22$vck44/valo=7,864.99 2006.173.20:04:44.22#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.20:04:44.22#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.20:04:44.22#ibcon#ireg 17 cls_cnt 0 2006.173.20:04:44.22#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.20:04:44.22#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.20:04:44.22#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.20:04:44.22#ibcon#enter wrdev, iclass 22, count 0 2006.173.20:04:44.22#ibcon#first serial, iclass 22, count 0 2006.173.20:04:44.22#ibcon#enter sib2, iclass 22, count 0 2006.173.20:04:44.22#ibcon#flushed, iclass 22, count 0 2006.173.20:04:44.22#ibcon#about to write, iclass 22, count 0 2006.173.20:04:44.22#ibcon#wrote, iclass 22, count 0 2006.173.20:04:44.22#ibcon#about to read 3, iclass 22, count 0 2006.173.20:04:44.24#ibcon#read 3, iclass 22, count 0 2006.173.20:04:44.24#ibcon#about to read 4, iclass 22, count 0 2006.173.20:04:44.24#ibcon#read 4, iclass 22, count 0 2006.173.20:04:44.24#ibcon#about to read 5, iclass 22, count 0 2006.173.20:04:44.24#ibcon#read 5, iclass 22, count 0 2006.173.20:04:44.24#ibcon#about to read 6, iclass 22, count 0 2006.173.20:04:44.24#ibcon#read 6, iclass 22, count 0 2006.173.20:04:44.24#ibcon#end of sib2, iclass 22, count 0 2006.173.20:04:44.24#ibcon#*mode == 0, iclass 22, count 0 2006.173.20:04:44.24#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.20:04:44.24#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.20:04:44.24#ibcon#*before write, iclass 22, count 0 2006.173.20:04:44.24#ibcon#enter sib2, iclass 22, count 0 2006.173.20:04:44.24#ibcon#flushed, iclass 22, count 0 2006.173.20:04:44.24#ibcon#about to write, iclass 22, count 0 2006.173.20:04:44.24#ibcon#wrote, iclass 22, count 0 2006.173.20:04:44.24#ibcon#about to read 3, iclass 22, count 0 2006.173.20:04:44.28#ibcon#read 3, iclass 22, count 0 2006.173.20:04:44.28#ibcon#about to read 4, iclass 22, count 0 2006.173.20:04:44.28#ibcon#read 4, iclass 22, count 0 2006.173.20:04:44.28#ibcon#about to read 5, iclass 22, count 0 2006.173.20:04:44.28#ibcon#read 5, iclass 22, count 0 2006.173.20:04:44.28#ibcon#about to read 6, iclass 22, count 0 2006.173.20:04:44.28#ibcon#read 6, iclass 22, count 0 2006.173.20:04:44.28#ibcon#end of sib2, iclass 22, count 0 2006.173.20:04:44.28#ibcon#*after write, iclass 22, count 0 2006.173.20:04:44.28#ibcon#*before return 0, iclass 22, count 0 2006.173.20:04:44.28#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.20:04:44.28#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.20:04:44.28#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.20:04:44.28#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.20:04:44.28$vck44/va=7,4 2006.173.20:04:44.28#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.20:04:44.28#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.20:04:44.28#ibcon#ireg 11 cls_cnt 2 2006.173.20:04:44.28#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.20:04:44.34#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.20:04:44.34#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.20:04:44.34#ibcon#enter wrdev, iclass 24, count 2 2006.173.20:04:44.34#ibcon#first serial, iclass 24, count 2 2006.173.20:04:44.34#ibcon#enter sib2, iclass 24, count 2 2006.173.20:04:44.34#ibcon#flushed, iclass 24, count 2 2006.173.20:04:44.34#ibcon#about to write, iclass 24, count 2 2006.173.20:04:44.34#ibcon#wrote, iclass 24, count 2 2006.173.20:04:44.34#ibcon#about to read 3, iclass 24, count 2 2006.173.20:04:44.36#ibcon#read 3, iclass 24, count 2 2006.173.20:04:44.36#ibcon#about to read 4, iclass 24, count 2 2006.173.20:04:44.36#ibcon#read 4, iclass 24, count 2 2006.173.20:04:44.36#ibcon#about to read 5, iclass 24, count 2 2006.173.20:04:44.36#ibcon#read 5, iclass 24, count 2 2006.173.20:04:44.36#ibcon#about to read 6, iclass 24, count 2 2006.173.20:04:44.36#ibcon#read 6, iclass 24, count 2 2006.173.20:04:44.36#ibcon#end of sib2, iclass 24, count 2 2006.173.20:04:44.36#ibcon#*mode == 0, iclass 24, count 2 2006.173.20:04:44.36#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.20:04:44.36#ibcon#[25=AT07-04\r\n] 2006.173.20:04:44.36#ibcon#*before write, iclass 24, count 2 2006.173.20:04:44.36#ibcon#enter sib2, iclass 24, count 2 2006.173.20:04:44.36#ibcon#flushed, iclass 24, count 2 2006.173.20:04:44.36#ibcon#about to write, iclass 24, count 2 2006.173.20:04:44.36#ibcon#wrote, iclass 24, count 2 2006.173.20:04:44.36#ibcon#about to read 3, iclass 24, count 2 2006.173.20:04:44.39#ibcon#read 3, iclass 24, count 2 2006.173.20:04:44.39#ibcon#about to read 4, iclass 24, count 2 2006.173.20:04:44.39#ibcon#read 4, iclass 24, count 2 2006.173.20:04:44.39#ibcon#about to read 5, iclass 24, count 2 2006.173.20:04:44.39#ibcon#read 5, iclass 24, count 2 2006.173.20:04:44.39#ibcon#about to read 6, iclass 24, count 2 2006.173.20:04:44.39#ibcon#read 6, iclass 24, count 2 2006.173.20:04:44.39#ibcon#end of sib2, iclass 24, count 2 2006.173.20:04:44.39#ibcon#*after write, iclass 24, count 2 2006.173.20:04:44.39#ibcon#*before return 0, iclass 24, count 2 2006.173.20:04:44.39#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.20:04:44.39#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.20:04:44.39#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.20:04:44.39#ibcon#ireg 7 cls_cnt 0 2006.173.20:04:44.39#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.20:04:44.51#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.20:04:44.51#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.20:04:44.51#ibcon#enter wrdev, iclass 24, count 0 2006.173.20:04:44.51#ibcon#first serial, iclass 24, count 0 2006.173.20:04:44.51#ibcon#enter sib2, iclass 24, count 0 2006.173.20:04:44.51#ibcon#flushed, iclass 24, count 0 2006.173.20:04:44.51#ibcon#about to write, iclass 24, count 0 2006.173.20:04:44.51#ibcon#wrote, iclass 24, count 0 2006.173.20:04:44.51#ibcon#about to read 3, iclass 24, count 0 2006.173.20:04:44.53#ibcon#read 3, iclass 24, count 0 2006.173.20:04:44.53#ibcon#about to read 4, iclass 24, count 0 2006.173.20:04:44.53#ibcon#read 4, iclass 24, count 0 2006.173.20:04:44.53#ibcon#about to read 5, iclass 24, count 0 2006.173.20:04:44.53#ibcon#read 5, iclass 24, count 0 2006.173.20:04:44.53#ibcon#about to read 6, iclass 24, count 0 2006.173.20:04:44.53#ibcon#read 6, iclass 24, count 0 2006.173.20:04:44.53#ibcon#end of sib2, iclass 24, count 0 2006.173.20:04:44.53#ibcon#*mode == 0, iclass 24, count 0 2006.173.20:04:44.53#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.20:04:44.53#ibcon#[25=USB\r\n] 2006.173.20:04:44.53#ibcon#*before write, iclass 24, count 0 2006.173.20:04:44.53#ibcon#enter sib2, iclass 24, count 0 2006.173.20:04:44.53#ibcon#flushed, iclass 24, count 0 2006.173.20:04:44.53#ibcon#about to write, iclass 24, count 0 2006.173.20:04:44.53#ibcon#wrote, iclass 24, count 0 2006.173.20:04:44.53#ibcon#about to read 3, iclass 24, count 0 2006.173.20:04:44.56#ibcon#read 3, iclass 24, count 0 2006.173.20:04:44.56#ibcon#about to read 4, iclass 24, count 0 2006.173.20:04:44.56#ibcon#read 4, iclass 24, count 0 2006.173.20:04:44.56#ibcon#about to read 5, iclass 24, count 0 2006.173.20:04:44.56#ibcon#read 5, iclass 24, count 0 2006.173.20:04:44.56#ibcon#about to read 6, iclass 24, count 0 2006.173.20:04:44.56#ibcon#read 6, iclass 24, count 0 2006.173.20:04:44.56#ibcon#end of sib2, iclass 24, count 0 2006.173.20:04:44.56#ibcon#*after write, iclass 24, count 0 2006.173.20:04:44.56#ibcon#*before return 0, iclass 24, count 0 2006.173.20:04:44.56#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.20:04:44.56#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.20:04:44.56#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.20:04:44.56#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.20:04:44.56$vck44/valo=8,884.99 2006.173.20:04:44.56#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.20:04:44.56#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.20:04:44.56#ibcon#ireg 17 cls_cnt 0 2006.173.20:04:44.56#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.20:04:44.56#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.20:04:44.56#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.20:04:44.56#ibcon#enter wrdev, iclass 26, count 0 2006.173.20:04:44.56#ibcon#first serial, iclass 26, count 0 2006.173.20:04:44.56#ibcon#enter sib2, iclass 26, count 0 2006.173.20:04:44.56#ibcon#flushed, iclass 26, count 0 2006.173.20:04:44.56#ibcon#about to write, iclass 26, count 0 2006.173.20:04:44.56#ibcon#wrote, iclass 26, count 0 2006.173.20:04:44.56#ibcon#about to read 3, iclass 26, count 0 2006.173.20:04:44.58#ibcon#read 3, iclass 26, count 0 2006.173.20:04:44.58#ibcon#about to read 4, iclass 26, count 0 2006.173.20:04:44.58#ibcon#read 4, iclass 26, count 0 2006.173.20:04:44.58#ibcon#about to read 5, iclass 26, count 0 2006.173.20:04:44.58#ibcon#read 5, iclass 26, count 0 2006.173.20:04:44.58#ibcon#about to read 6, iclass 26, count 0 2006.173.20:04:44.58#ibcon#read 6, iclass 26, count 0 2006.173.20:04:44.58#ibcon#end of sib2, iclass 26, count 0 2006.173.20:04:44.58#ibcon#*mode == 0, iclass 26, count 0 2006.173.20:04:44.58#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.20:04:44.58#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.20:04:44.58#ibcon#*before write, iclass 26, count 0 2006.173.20:04:44.58#ibcon#enter sib2, iclass 26, count 0 2006.173.20:04:44.58#ibcon#flushed, iclass 26, count 0 2006.173.20:04:44.58#ibcon#about to write, iclass 26, count 0 2006.173.20:04:44.58#ibcon#wrote, iclass 26, count 0 2006.173.20:04:44.58#ibcon#about to read 3, iclass 26, count 0 2006.173.20:04:44.62#ibcon#read 3, iclass 26, count 0 2006.173.20:04:44.62#ibcon#about to read 4, iclass 26, count 0 2006.173.20:04:44.62#ibcon#read 4, iclass 26, count 0 2006.173.20:04:44.62#ibcon#about to read 5, iclass 26, count 0 2006.173.20:04:44.62#ibcon#read 5, iclass 26, count 0 2006.173.20:04:44.62#ibcon#about to read 6, iclass 26, count 0 2006.173.20:04:44.62#ibcon#read 6, iclass 26, count 0 2006.173.20:04:44.62#ibcon#end of sib2, iclass 26, count 0 2006.173.20:04:44.62#ibcon#*after write, iclass 26, count 0 2006.173.20:04:44.62#ibcon#*before return 0, iclass 26, count 0 2006.173.20:04:44.62#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.20:04:44.62#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.20:04:44.62#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.20:04:44.62#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.20:04:44.62$vck44/va=8,4 2006.173.20:04:44.62#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.20:04:44.62#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.20:04:44.62#ibcon#ireg 11 cls_cnt 2 2006.173.20:04:44.62#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.20:04:44.68#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.20:04:44.68#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.20:04:44.68#ibcon#enter wrdev, iclass 28, count 2 2006.173.20:04:44.68#ibcon#first serial, iclass 28, count 2 2006.173.20:04:44.68#ibcon#enter sib2, iclass 28, count 2 2006.173.20:04:44.68#ibcon#flushed, iclass 28, count 2 2006.173.20:04:44.68#ibcon#about to write, iclass 28, count 2 2006.173.20:04:44.68#ibcon#wrote, iclass 28, count 2 2006.173.20:04:44.68#ibcon#about to read 3, iclass 28, count 2 2006.173.20:04:44.70#ibcon#read 3, iclass 28, count 2 2006.173.20:04:44.70#ibcon#about to read 4, iclass 28, count 2 2006.173.20:04:44.70#ibcon#read 4, iclass 28, count 2 2006.173.20:04:44.70#ibcon#about to read 5, iclass 28, count 2 2006.173.20:04:44.70#ibcon#read 5, iclass 28, count 2 2006.173.20:04:44.70#ibcon#about to read 6, iclass 28, count 2 2006.173.20:04:44.70#ibcon#read 6, iclass 28, count 2 2006.173.20:04:44.70#ibcon#end of sib2, iclass 28, count 2 2006.173.20:04:44.70#ibcon#*mode == 0, iclass 28, count 2 2006.173.20:04:44.70#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.20:04:44.70#ibcon#[25=AT08-04\r\n] 2006.173.20:04:44.70#ibcon#*before write, iclass 28, count 2 2006.173.20:04:44.70#ibcon#enter sib2, iclass 28, count 2 2006.173.20:04:44.70#ibcon#flushed, iclass 28, count 2 2006.173.20:04:44.70#ibcon#about to write, iclass 28, count 2 2006.173.20:04:44.70#ibcon#wrote, iclass 28, count 2 2006.173.20:04:44.70#ibcon#about to read 3, iclass 28, count 2 2006.173.20:04:44.73#ibcon#read 3, iclass 28, count 2 2006.173.20:04:44.73#ibcon#about to read 4, iclass 28, count 2 2006.173.20:04:44.73#ibcon#read 4, iclass 28, count 2 2006.173.20:04:44.73#ibcon#about to read 5, iclass 28, count 2 2006.173.20:04:44.73#ibcon#read 5, iclass 28, count 2 2006.173.20:04:44.73#ibcon#about to read 6, iclass 28, count 2 2006.173.20:04:44.73#ibcon#read 6, iclass 28, count 2 2006.173.20:04:44.73#ibcon#end of sib2, iclass 28, count 2 2006.173.20:04:44.73#ibcon#*after write, iclass 28, count 2 2006.173.20:04:44.73#ibcon#*before return 0, iclass 28, count 2 2006.173.20:04:44.73#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.20:04:44.73#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.20:04:44.73#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.20:04:44.73#ibcon#ireg 7 cls_cnt 0 2006.173.20:04:44.73#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.20:04:44.85#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.20:04:44.85#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.20:04:44.85#ibcon#enter wrdev, iclass 28, count 0 2006.173.20:04:44.85#ibcon#first serial, iclass 28, count 0 2006.173.20:04:44.85#ibcon#enter sib2, iclass 28, count 0 2006.173.20:04:44.85#ibcon#flushed, iclass 28, count 0 2006.173.20:04:44.85#ibcon#about to write, iclass 28, count 0 2006.173.20:04:44.85#ibcon#wrote, iclass 28, count 0 2006.173.20:04:44.85#ibcon#about to read 3, iclass 28, count 0 2006.173.20:04:44.87#ibcon#read 3, iclass 28, count 0 2006.173.20:04:44.87#ibcon#about to read 4, iclass 28, count 0 2006.173.20:04:44.87#ibcon#read 4, iclass 28, count 0 2006.173.20:04:44.87#ibcon#about to read 5, iclass 28, count 0 2006.173.20:04:44.87#ibcon#read 5, iclass 28, count 0 2006.173.20:04:44.87#ibcon#about to read 6, iclass 28, count 0 2006.173.20:04:44.87#ibcon#read 6, iclass 28, count 0 2006.173.20:04:44.87#ibcon#end of sib2, iclass 28, count 0 2006.173.20:04:44.87#ibcon#*mode == 0, iclass 28, count 0 2006.173.20:04:44.87#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.20:04:44.87#ibcon#[25=USB\r\n] 2006.173.20:04:44.87#ibcon#*before write, iclass 28, count 0 2006.173.20:04:44.87#ibcon#enter sib2, iclass 28, count 0 2006.173.20:04:44.87#ibcon#flushed, iclass 28, count 0 2006.173.20:04:44.87#ibcon#about to write, iclass 28, count 0 2006.173.20:04:44.87#ibcon#wrote, iclass 28, count 0 2006.173.20:04:44.87#ibcon#about to read 3, iclass 28, count 0 2006.173.20:04:44.90#ibcon#read 3, iclass 28, count 0 2006.173.20:04:44.90#ibcon#about to read 4, iclass 28, count 0 2006.173.20:04:44.90#ibcon#read 4, iclass 28, count 0 2006.173.20:04:44.90#ibcon#about to read 5, iclass 28, count 0 2006.173.20:04:44.90#ibcon#read 5, iclass 28, count 0 2006.173.20:04:44.90#ibcon#about to read 6, iclass 28, count 0 2006.173.20:04:44.90#ibcon#read 6, iclass 28, count 0 2006.173.20:04:44.90#ibcon#end of sib2, iclass 28, count 0 2006.173.20:04:44.90#ibcon#*after write, iclass 28, count 0 2006.173.20:04:44.90#ibcon#*before return 0, iclass 28, count 0 2006.173.20:04:44.90#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.20:04:44.90#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.20:04:44.90#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.20:04:44.90#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.20:04:44.90$vck44/vblo=1,629.99 2006.173.20:04:44.90#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.20:04:44.90#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.20:04:44.90#ibcon#ireg 17 cls_cnt 0 2006.173.20:04:44.90#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.20:04:44.90#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.20:04:44.90#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.20:04:44.90#ibcon#enter wrdev, iclass 30, count 0 2006.173.20:04:44.90#ibcon#first serial, iclass 30, count 0 2006.173.20:04:44.90#ibcon#enter sib2, iclass 30, count 0 2006.173.20:04:44.90#ibcon#flushed, iclass 30, count 0 2006.173.20:04:44.90#ibcon#about to write, iclass 30, count 0 2006.173.20:04:44.90#ibcon#wrote, iclass 30, count 0 2006.173.20:04:44.90#ibcon#about to read 3, iclass 30, count 0 2006.173.20:04:44.92#ibcon#read 3, iclass 30, count 0 2006.173.20:04:44.92#ibcon#about to read 4, iclass 30, count 0 2006.173.20:04:44.92#ibcon#read 4, iclass 30, count 0 2006.173.20:04:44.92#ibcon#about to read 5, iclass 30, count 0 2006.173.20:04:44.92#ibcon#read 5, iclass 30, count 0 2006.173.20:04:44.92#ibcon#about to read 6, iclass 30, count 0 2006.173.20:04:44.92#ibcon#read 6, iclass 30, count 0 2006.173.20:04:44.92#ibcon#end of sib2, iclass 30, count 0 2006.173.20:04:44.92#ibcon#*mode == 0, iclass 30, count 0 2006.173.20:04:44.92#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.20:04:44.92#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.20:04:44.92#ibcon#*before write, iclass 30, count 0 2006.173.20:04:44.92#ibcon#enter sib2, iclass 30, count 0 2006.173.20:04:44.92#ibcon#flushed, iclass 30, count 0 2006.173.20:04:44.92#ibcon#about to write, iclass 30, count 0 2006.173.20:04:44.92#ibcon#wrote, iclass 30, count 0 2006.173.20:04:44.92#ibcon#about to read 3, iclass 30, count 0 2006.173.20:04:44.96#ibcon#read 3, iclass 30, count 0 2006.173.20:04:44.96#ibcon#about to read 4, iclass 30, count 0 2006.173.20:04:44.96#ibcon#read 4, iclass 30, count 0 2006.173.20:04:44.96#ibcon#about to read 5, iclass 30, count 0 2006.173.20:04:44.96#ibcon#read 5, iclass 30, count 0 2006.173.20:04:44.96#ibcon#about to read 6, iclass 30, count 0 2006.173.20:04:44.96#ibcon#read 6, iclass 30, count 0 2006.173.20:04:44.96#ibcon#end of sib2, iclass 30, count 0 2006.173.20:04:44.96#ibcon#*after write, iclass 30, count 0 2006.173.20:04:44.96#ibcon#*before return 0, iclass 30, count 0 2006.173.20:04:44.96#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.20:04:44.96#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.20:04:44.96#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.20:04:44.96#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.20:04:44.96$vck44/vb=1,4 2006.173.20:04:44.96#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.173.20:04:44.96#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.173.20:04:44.96#ibcon#ireg 11 cls_cnt 2 2006.173.20:04:44.96#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.20:04:44.96#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.20:04:44.96#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.20:04:44.96#ibcon#enter wrdev, iclass 32, count 2 2006.173.20:04:44.96#ibcon#first serial, iclass 32, count 2 2006.173.20:04:44.96#ibcon#enter sib2, iclass 32, count 2 2006.173.20:04:44.96#ibcon#flushed, iclass 32, count 2 2006.173.20:04:44.96#ibcon#about to write, iclass 32, count 2 2006.173.20:04:44.96#ibcon#wrote, iclass 32, count 2 2006.173.20:04:44.96#ibcon#about to read 3, iclass 32, count 2 2006.173.20:04:44.98#ibcon#read 3, iclass 32, count 2 2006.173.20:04:44.98#ibcon#about to read 4, iclass 32, count 2 2006.173.20:04:44.98#ibcon#read 4, iclass 32, count 2 2006.173.20:04:44.98#ibcon#about to read 5, iclass 32, count 2 2006.173.20:04:44.98#ibcon#read 5, iclass 32, count 2 2006.173.20:04:44.98#ibcon#about to read 6, iclass 32, count 2 2006.173.20:04:44.98#ibcon#read 6, iclass 32, count 2 2006.173.20:04:44.98#ibcon#end of sib2, iclass 32, count 2 2006.173.20:04:44.98#ibcon#*mode == 0, iclass 32, count 2 2006.173.20:04:44.98#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.173.20:04:44.98#ibcon#[27=AT01-04\r\n] 2006.173.20:04:44.98#ibcon#*before write, iclass 32, count 2 2006.173.20:04:44.98#ibcon#enter sib2, iclass 32, count 2 2006.173.20:04:44.98#ibcon#flushed, iclass 32, count 2 2006.173.20:04:44.98#ibcon#about to write, iclass 32, count 2 2006.173.20:04:44.98#ibcon#wrote, iclass 32, count 2 2006.173.20:04:44.98#ibcon#about to read 3, iclass 32, count 2 2006.173.20:04:45.01#ibcon#read 3, iclass 32, count 2 2006.173.20:04:45.01#ibcon#about to read 4, iclass 32, count 2 2006.173.20:04:45.01#ibcon#read 4, iclass 32, count 2 2006.173.20:04:45.01#ibcon#about to read 5, iclass 32, count 2 2006.173.20:04:45.01#ibcon#read 5, iclass 32, count 2 2006.173.20:04:45.01#ibcon#about to read 6, iclass 32, count 2 2006.173.20:04:45.01#ibcon#read 6, iclass 32, count 2 2006.173.20:04:45.01#ibcon#end of sib2, iclass 32, count 2 2006.173.20:04:45.01#ibcon#*after write, iclass 32, count 2 2006.173.20:04:45.01#ibcon#*before return 0, iclass 32, count 2 2006.173.20:04:45.01#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.20:04:45.01#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.173.20:04:45.01#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.173.20:04:45.01#ibcon#ireg 7 cls_cnt 0 2006.173.20:04:45.01#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.20:04:45.13#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.20:04:45.13#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.20:04:45.13#ibcon#enter wrdev, iclass 32, count 0 2006.173.20:04:45.13#ibcon#first serial, iclass 32, count 0 2006.173.20:04:45.13#ibcon#enter sib2, iclass 32, count 0 2006.173.20:04:45.13#ibcon#flushed, iclass 32, count 0 2006.173.20:04:45.13#ibcon#about to write, iclass 32, count 0 2006.173.20:04:45.13#ibcon#wrote, iclass 32, count 0 2006.173.20:04:45.13#ibcon#about to read 3, iclass 32, count 0 2006.173.20:04:45.15#ibcon#read 3, iclass 32, count 0 2006.173.20:04:45.15#ibcon#about to read 4, iclass 32, count 0 2006.173.20:04:45.15#ibcon#read 4, iclass 32, count 0 2006.173.20:04:45.15#ibcon#about to read 5, iclass 32, count 0 2006.173.20:04:45.15#ibcon#read 5, iclass 32, count 0 2006.173.20:04:45.15#ibcon#about to read 6, iclass 32, count 0 2006.173.20:04:45.15#ibcon#read 6, iclass 32, count 0 2006.173.20:04:45.15#ibcon#end of sib2, iclass 32, count 0 2006.173.20:04:45.15#ibcon#*mode == 0, iclass 32, count 0 2006.173.20:04:45.15#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.20:04:45.15#ibcon#[27=USB\r\n] 2006.173.20:04:45.15#ibcon#*before write, iclass 32, count 0 2006.173.20:04:45.15#ibcon#enter sib2, iclass 32, count 0 2006.173.20:04:45.15#ibcon#flushed, iclass 32, count 0 2006.173.20:04:45.15#ibcon#about to write, iclass 32, count 0 2006.173.20:04:45.15#ibcon#wrote, iclass 32, count 0 2006.173.20:04:45.15#ibcon#about to read 3, iclass 32, count 0 2006.173.20:04:45.18#ibcon#read 3, iclass 32, count 0 2006.173.20:04:45.18#ibcon#about to read 4, iclass 32, count 0 2006.173.20:04:45.18#ibcon#read 4, iclass 32, count 0 2006.173.20:04:45.18#ibcon#about to read 5, iclass 32, count 0 2006.173.20:04:45.18#ibcon#read 5, iclass 32, count 0 2006.173.20:04:45.18#ibcon#about to read 6, iclass 32, count 0 2006.173.20:04:45.18#ibcon#read 6, iclass 32, count 0 2006.173.20:04:45.18#ibcon#end of sib2, iclass 32, count 0 2006.173.20:04:45.18#ibcon#*after write, iclass 32, count 0 2006.173.20:04:45.18#ibcon#*before return 0, iclass 32, count 0 2006.173.20:04:45.18#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.20:04:45.18#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.173.20:04:45.18#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.20:04:45.18#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.20:04:45.18$vck44/vblo=2,634.99 2006.173.20:04:45.18#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.20:04:45.18#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.20:04:45.18#ibcon#ireg 17 cls_cnt 0 2006.173.20:04:45.18#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.20:04:45.18#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.20:04:45.18#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.20:04:45.18#ibcon#enter wrdev, iclass 34, count 0 2006.173.20:04:45.18#ibcon#first serial, iclass 34, count 0 2006.173.20:04:45.18#ibcon#enter sib2, iclass 34, count 0 2006.173.20:04:45.18#ibcon#flushed, iclass 34, count 0 2006.173.20:04:45.18#ibcon#about to write, iclass 34, count 0 2006.173.20:04:45.18#ibcon#wrote, iclass 34, count 0 2006.173.20:04:45.18#ibcon#about to read 3, iclass 34, count 0 2006.173.20:04:45.20#ibcon#read 3, iclass 34, count 0 2006.173.20:04:45.20#ibcon#about to read 4, iclass 34, count 0 2006.173.20:04:45.20#ibcon#read 4, iclass 34, count 0 2006.173.20:04:45.20#ibcon#about to read 5, iclass 34, count 0 2006.173.20:04:45.20#ibcon#read 5, iclass 34, count 0 2006.173.20:04:45.20#ibcon#about to read 6, iclass 34, count 0 2006.173.20:04:45.20#ibcon#read 6, iclass 34, count 0 2006.173.20:04:45.20#ibcon#end of sib2, iclass 34, count 0 2006.173.20:04:45.20#ibcon#*mode == 0, iclass 34, count 0 2006.173.20:04:45.20#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.20:04:45.20#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.20:04:45.20#ibcon#*before write, iclass 34, count 0 2006.173.20:04:45.20#ibcon#enter sib2, iclass 34, count 0 2006.173.20:04:45.20#ibcon#flushed, iclass 34, count 0 2006.173.20:04:45.20#ibcon#about to write, iclass 34, count 0 2006.173.20:04:45.20#ibcon#wrote, iclass 34, count 0 2006.173.20:04:45.20#ibcon#about to read 3, iclass 34, count 0 2006.173.20:04:45.24#ibcon#read 3, iclass 34, count 0 2006.173.20:04:45.24#ibcon#about to read 4, iclass 34, count 0 2006.173.20:04:45.24#ibcon#read 4, iclass 34, count 0 2006.173.20:04:45.24#ibcon#about to read 5, iclass 34, count 0 2006.173.20:04:45.24#ibcon#read 5, iclass 34, count 0 2006.173.20:04:45.24#ibcon#about to read 6, iclass 34, count 0 2006.173.20:04:45.24#ibcon#read 6, iclass 34, count 0 2006.173.20:04:45.24#ibcon#end of sib2, iclass 34, count 0 2006.173.20:04:45.24#ibcon#*after write, iclass 34, count 0 2006.173.20:04:45.24#ibcon#*before return 0, iclass 34, count 0 2006.173.20:04:45.24#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.20:04:45.24#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.20:04:45.24#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.20:04:45.24#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.20:04:45.24$vck44/vb=2,4 2006.173.20:04:45.24#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.20:04:45.24#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.20:04:45.24#ibcon#ireg 11 cls_cnt 2 2006.173.20:04:45.24#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.20:04:45.30#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.20:04:45.30#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.20:04:45.30#ibcon#enter wrdev, iclass 36, count 2 2006.173.20:04:45.30#ibcon#first serial, iclass 36, count 2 2006.173.20:04:45.30#ibcon#enter sib2, iclass 36, count 2 2006.173.20:04:45.30#ibcon#flushed, iclass 36, count 2 2006.173.20:04:45.30#ibcon#about to write, iclass 36, count 2 2006.173.20:04:45.30#ibcon#wrote, iclass 36, count 2 2006.173.20:04:45.30#ibcon#about to read 3, iclass 36, count 2 2006.173.20:04:45.32#ibcon#read 3, iclass 36, count 2 2006.173.20:04:45.32#ibcon#about to read 4, iclass 36, count 2 2006.173.20:04:45.32#ibcon#read 4, iclass 36, count 2 2006.173.20:04:45.32#ibcon#about to read 5, iclass 36, count 2 2006.173.20:04:45.32#ibcon#read 5, iclass 36, count 2 2006.173.20:04:45.32#ibcon#about to read 6, iclass 36, count 2 2006.173.20:04:45.32#ibcon#read 6, iclass 36, count 2 2006.173.20:04:45.32#ibcon#end of sib2, iclass 36, count 2 2006.173.20:04:45.32#ibcon#*mode == 0, iclass 36, count 2 2006.173.20:04:45.32#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.20:04:45.32#ibcon#[27=AT02-04\r\n] 2006.173.20:04:45.32#ibcon#*before write, iclass 36, count 2 2006.173.20:04:45.32#ibcon#enter sib2, iclass 36, count 2 2006.173.20:04:45.32#ibcon#flushed, iclass 36, count 2 2006.173.20:04:45.32#ibcon#about to write, iclass 36, count 2 2006.173.20:04:45.32#ibcon#wrote, iclass 36, count 2 2006.173.20:04:45.32#ibcon#about to read 3, iclass 36, count 2 2006.173.20:04:45.35#ibcon#read 3, iclass 36, count 2 2006.173.20:04:45.35#ibcon#about to read 4, iclass 36, count 2 2006.173.20:04:45.35#ibcon#read 4, iclass 36, count 2 2006.173.20:04:45.35#ibcon#about to read 5, iclass 36, count 2 2006.173.20:04:45.35#ibcon#read 5, iclass 36, count 2 2006.173.20:04:45.35#ibcon#about to read 6, iclass 36, count 2 2006.173.20:04:45.35#ibcon#read 6, iclass 36, count 2 2006.173.20:04:45.35#ibcon#end of sib2, iclass 36, count 2 2006.173.20:04:45.35#ibcon#*after write, iclass 36, count 2 2006.173.20:04:45.35#ibcon#*before return 0, iclass 36, count 2 2006.173.20:04:45.35#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.20:04:45.35#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.20:04:45.35#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.20:04:45.35#ibcon#ireg 7 cls_cnt 0 2006.173.20:04:45.35#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.20:04:45.47#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.20:04:45.47#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.20:04:45.47#ibcon#enter wrdev, iclass 36, count 0 2006.173.20:04:45.47#ibcon#first serial, iclass 36, count 0 2006.173.20:04:45.47#ibcon#enter sib2, iclass 36, count 0 2006.173.20:04:45.47#ibcon#flushed, iclass 36, count 0 2006.173.20:04:45.47#ibcon#about to write, iclass 36, count 0 2006.173.20:04:45.47#ibcon#wrote, iclass 36, count 0 2006.173.20:04:45.47#ibcon#about to read 3, iclass 36, count 0 2006.173.20:04:45.49#ibcon#read 3, iclass 36, count 0 2006.173.20:04:45.49#ibcon#about to read 4, iclass 36, count 0 2006.173.20:04:45.49#ibcon#read 4, iclass 36, count 0 2006.173.20:04:45.49#ibcon#about to read 5, iclass 36, count 0 2006.173.20:04:45.49#ibcon#read 5, iclass 36, count 0 2006.173.20:04:45.49#ibcon#about to read 6, iclass 36, count 0 2006.173.20:04:45.49#ibcon#read 6, iclass 36, count 0 2006.173.20:04:45.49#ibcon#end of sib2, iclass 36, count 0 2006.173.20:04:45.49#ibcon#*mode == 0, iclass 36, count 0 2006.173.20:04:45.49#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.20:04:45.49#ibcon#[27=USB\r\n] 2006.173.20:04:45.49#ibcon#*before write, iclass 36, count 0 2006.173.20:04:45.49#ibcon#enter sib2, iclass 36, count 0 2006.173.20:04:45.49#ibcon#flushed, iclass 36, count 0 2006.173.20:04:45.49#ibcon#about to write, iclass 36, count 0 2006.173.20:04:45.49#ibcon#wrote, iclass 36, count 0 2006.173.20:04:45.49#ibcon#about to read 3, iclass 36, count 0 2006.173.20:04:45.52#ibcon#read 3, iclass 36, count 0 2006.173.20:04:45.52#ibcon#about to read 4, iclass 36, count 0 2006.173.20:04:45.52#ibcon#read 4, iclass 36, count 0 2006.173.20:04:45.52#ibcon#about to read 5, iclass 36, count 0 2006.173.20:04:45.52#ibcon#read 5, iclass 36, count 0 2006.173.20:04:45.52#ibcon#about to read 6, iclass 36, count 0 2006.173.20:04:45.52#ibcon#read 6, iclass 36, count 0 2006.173.20:04:45.52#ibcon#end of sib2, iclass 36, count 0 2006.173.20:04:45.52#ibcon#*after write, iclass 36, count 0 2006.173.20:04:45.52#ibcon#*before return 0, iclass 36, count 0 2006.173.20:04:45.52#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.20:04:45.52#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.20:04:45.52#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.20:04:45.52#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.20:04:45.52$vck44/vblo=3,649.99 2006.173.20:04:45.52#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.20:04:45.52#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.20:04:45.52#ibcon#ireg 17 cls_cnt 0 2006.173.20:04:45.52#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.20:04:45.52#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.20:04:45.52#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.20:04:45.52#ibcon#enter wrdev, iclass 38, count 0 2006.173.20:04:45.52#ibcon#first serial, iclass 38, count 0 2006.173.20:04:45.52#ibcon#enter sib2, iclass 38, count 0 2006.173.20:04:45.52#ibcon#flushed, iclass 38, count 0 2006.173.20:04:45.52#ibcon#about to write, iclass 38, count 0 2006.173.20:04:45.52#ibcon#wrote, iclass 38, count 0 2006.173.20:04:45.52#ibcon#about to read 3, iclass 38, count 0 2006.173.20:04:45.54#ibcon#read 3, iclass 38, count 0 2006.173.20:04:45.54#ibcon#about to read 4, iclass 38, count 0 2006.173.20:04:45.54#ibcon#read 4, iclass 38, count 0 2006.173.20:04:45.54#ibcon#about to read 5, iclass 38, count 0 2006.173.20:04:45.54#ibcon#read 5, iclass 38, count 0 2006.173.20:04:45.54#ibcon#about to read 6, iclass 38, count 0 2006.173.20:04:45.54#ibcon#read 6, iclass 38, count 0 2006.173.20:04:45.54#ibcon#end of sib2, iclass 38, count 0 2006.173.20:04:45.54#ibcon#*mode == 0, iclass 38, count 0 2006.173.20:04:45.54#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.20:04:45.54#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.20:04:45.54#ibcon#*before write, iclass 38, count 0 2006.173.20:04:45.54#ibcon#enter sib2, iclass 38, count 0 2006.173.20:04:45.54#ibcon#flushed, iclass 38, count 0 2006.173.20:04:45.54#ibcon#about to write, iclass 38, count 0 2006.173.20:04:45.54#ibcon#wrote, iclass 38, count 0 2006.173.20:04:45.54#ibcon#about to read 3, iclass 38, count 0 2006.173.20:04:45.58#ibcon#read 3, iclass 38, count 0 2006.173.20:04:45.58#ibcon#about to read 4, iclass 38, count 0 2006.173.20:04:45.58#ibcon#read 4, iclass 38, count 0 2006.173.20:04:45.58#ibcon#about to read 5, iclass 38, count 0 2006.173.20:04:45.58#ibcon#read 5, iclass 38, count 0 2006.173.20:04:45.58#ibcon#about to read 6, iclass 38, count 0 2006.173.20:04:45.58#ibcon#read 6, iclass 38, count 0 2006.173.20:04:45.58#ibcon#end of sib2, iclass 38, count 0 2006.173.20:04:45.58#ibcon#*after write, iclass 38, count 0 2006.173.20:04:45.58#ibcon#*before return 0, iclass 38, count 0 2006.173.20:04:45.58#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.20:04:45.58#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.20:04:45.58#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.20:04:45.58#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.20:04:45.58$vck44/vb=3,4 2006.173.20:04:45.58#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.20:04:45.58#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.20:04:45.58#ibcon#ireg 11 cls_cnt 2 2006.173.20:04:45.58#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.20:04:45.64#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.20:04:45.64#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.20:04:45.64#ibcon#enter wrdev, iclass 40, count 2 2006.173.20:04:45.64#ibcon#first serial, iclass 40, count 2 2006.173.20:04:45.64#ibcon#enter sib2, iclass 40, count 2 2006.173.20:04:45.64#ibcon#flushed, iclass 40, count 2 2006.173.20:04:45.64#ibcon#about to write, iclass 40, count 2 2006.173.20:04:45.64#ibcon#wrote, iclass 40, count 2 2006.173.20:04:45.64#ibcon#about to read 3, iclass 40, count 2 2006.173.20:04:45.66#ibcon#read 3, iclass 40, count 2 2006.173.20:04:45.66#ibcon#about to read 4, iclass 40, count 2 2006.173.20:04:45.66#ibcon#read 4, iclass 40, count 2 2006.173.20:04:45.66#ibcon#about to read 5, iclass 40, count 2 2006.173.20:04:45.66#ibcon#read 5, iclass 40, count 2 2006.173.20:04:45.66#ibcon#about to read 6, iclass 40, count 2 2006.173.20:04:45.66#ibcon#read 6, iclass 40, count 2 2006.173.20:04:45.66#ibcon#end of sib2, iclass 40, count 2 2006.173.20:04:45.66#ibcon#*mode == 0, iclass 40, count 2 2006.173.20:04:45.66#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.20:04:45.66#ibcon#[27=AT03-04\r\n] 2006.173.20:04:45.66#ibcon#*before write, iclass 40, count 2 2006.173.20:04:45.66#ibcon#enter sib2, iclass 40, count 2 2006.173.20:04:45.66#ibcon#flushed, iclass 40, count 2 2006.173.20:04:45.66#ibcon#about to write, iclass 40, count 2 2006.173.20:04:45.66#ibcon#wrote, iclass 40, count 2 2006.173.20:04:45.66#ibcon#about to read 3, iclass 40, count 2 2006.173.20:04:45.69#ibcon#read 3, iclass 40, count 2 2006.173.20:04:45.69#ibcon#about to read 4, iclass 40, count 2 2006.173.20:04:45.69#ibcon#read 4, iclass 40, count 2 2006.173.20:04:45.69#ibcon#about to read 5, iclass 40, count 2 2006.173.20:04:45.69#ibcon#read 5, iclass 40, count 2 2006.173.20:04:45.69#ibcon#about to read 6, iclass 40, count 2 2006.173.20:04:45.69#ibcon#read 6, iclass 40, count 2 2006.173.20:04:45.69#ibcon#end of sib2, iclass 40, count 2 2006.173.20:04:45.69#ibcon#*after write, iclass 40, count 2 2006.173.20:04:45.69#ibcon#*before return 0, iclass 40, count 2 2006.173.20:04:45.69#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.20:04:45.69#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.20:04:45.69#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.20:04:45.69#ibcon#ireg 7 cls_cnt 0 2006.173.20:04:45.69#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.20:04:45.81#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.20:04:45.81#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.20:04:45.81#ibcon#enter wrdev, iclass 40, count 0 2006.173.20:04:45.81#ibcon#first serial, iclass 40, count 0 2006.173.20:04:45.81#ibcon#enter sib2, iclass 40, count 0 2006.173.20:04:45.81#ibcon#flushed, iclass 40, count 0 2006.173.20:04:45.81#ibcon#about to write, iclass 40, count 0 2006.173.20:04:45.81#ibcon#wrote, iclass 40, count 0 2006.173.20:04:45.81#ibcon#about to read 3, iclass 40, count 0 2006.173.20:04:45.83#ibcon#read 3, iclass 40, count 0 2006.173.20:04:45.83#ibcon#about to read 4, iclass 40, count 0 2006.173.20:04:45.83#ibcon#read 4, iclass 40, count 0 2006.173.20:04:45.83#ibcon#about to read 5, iclass 40, count 0 2006.173.20:04:45.83#ibcon#read 5, iclass 40, count 0 2006.173.20:04:45.83#ibcon#about to read 6, iclass 40, count 0 2006.173.20:04:45.83#ibcon#read 6, iclass 40, count 0 2006.173.20:04:45.83#ibcon#end of sib2, iclass 40, count 0 2006.173.20:04:45.83#ibcon#*mode == 0, iclass 40, count 0 2006.173.20:04:45.83#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.20:04:45.83#ibcon#[27=USB\r\n] 2006.173.20:04:45.83#ibcon#*before write, iclass 40, count 0 2006.173.20:04:45.83#ibcon#enter sib2, iclass 40, count 0 2006.173.20:04:45.83#ibcon#flushed, iclass 40, count 0 2006.173.20:04:45.83#ibcon#about to write, iclass 40, count 0 2006.173.20:04:45.83#ibcon#wrote, iclass 40, count 0 2006.173.20:04:45.83#ibcon#about to read 3, iclass 40, count 0 2006.173.20:04:45.86#ibcon#read 3, iclass 40, count 0 2006.173.20:04:45.86#ibcon#about to read 4, iclass 40, count 0 2006.173.20:04:45.86#ibcon#read 4, iclass 40, count 0 2006.173.20:04:45.86#ibcon#about to read 5, iclass 40, count 0 2006.173.20:04:45.86#ibcon#read 5, iclass 40, count 0 2006.173.20:04:45.86#ibcon#about to read 6, iclass 40, count 0 2006.173.20:04:45.86#ibcon#read 6, iclass 40, count 0 2006.173.20:04:45.86#ibcon#end of sib2, iclass 40, count 0 2006.173.20:04:45.86#ibcon#*after write, iclass 40, count 0 2006.173.20:04:45.86#ibcon#*before return 0, iclass 40, count 0 2006.173.20:04:45.86#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.20:04:45.86#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.20:04:45.86#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.20:04:45.86#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.20:04:45.86$vck44/vblo=4,679.99 2006.173.20:04:45.86#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.20:04:45.86#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.20:04:45.86#ibcon#ireg 17 cls_cnt 0 2006.173.20:04:45.86#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.20:04:45.86#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.20:04:45.86#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.20:04:45.86#ibcon#enter wrdev, iclass 4, count 0 2006.173.20:04:45.86#ibcon#first serial, iclass 4, count 0 2006.173.20:04:45.86#ibcon#enter sib2, iclass 4, count 0 2006.173.20:04:45.86#ibcon#flushed, iclass 4, count 0 2006.173.20:04:45.86#ibcon#about to write, iclass 4, count 0 2006.173.20:04:45.86#ibcon#wrote, iclass 4, count 0 2006.173.20:04:45.86#ibcon#about to read 3, iclass 4, count 0 2006.173.20:04:45.88#ibcon#read 3, iclass 4, count 0 2006.173.20:04:45.88#ibcon#about to read 4, iclass 4, count 0 2006.173.20:04:45.88#ibcon#read 4, iclass 4, count 0 2006.173.20:04:45.88#ibcon#about to read 5, iclass 4, count 0 2006.173.20:04:45.88#ibcon#read 5, iclass 4, count 0 2006.173.20:04:45.88#ibcon#about to read 6, iclass 4, count 0 2006.173.20:04:45.88#ibcon#read 6, iclass 4, count 0 2006.173.20:04:45.88#ibcon#end of sib2, iclass 4, count 0 2006.173.20:04:45.88#ibcon#*mode == 0, iclass 4, count 0 2006.173.20:04:45.88#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.20:04:45.88#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.20:04:45.88#ibcon#*before write, iclass 4, count 0 2006.173.20:04:45.88#ibcon#enter sib2, iclass 4, count 0 2006.173.20:04:45.88#ibcon#flushed, iclass 4, count 0 2006.173.20:04:45.88#ibcon#about to write, iclass 4, count 0 2006.173.20:04:45.88#ibcon#wrote, iclass 4, count 0 2006.173.20:04:45.88#ibcon#about to read 3, iclass 4, count 0 2006.173.20:04:45.92#ibcon#read 3, iclass 4, count 0 2006.173.20:04:45.92#ibcon#about to read 4, iclass 4, count 0 2006.173.20:04:45.92#ibcon#read 4, iclass 4, count 0 2006.173.20:04:45.92#ibcon#about to read 5, iclass 4, count 0 2006.173.20:04:45.92#ibcon#read 5, iclass 4, count 0 2006.173.20:04:45.92#ibcon#about to read 6, iclass 4, count 0 2006.173.20:04:45.92#ibcon#read 6, iclass 4, count 0 2006.173.20:04:45.92#ibcon#end of sib2, iclass 4, count 0 2006.173.20:04:45.92#ibcon#*after write, iclass 4, count 0 2006.173.20:04:45.92#ibcon#*before return 0, iclass 4, count 0 2006.173.20:04:45.92#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.20:04:45.92#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.20:04:45.92#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.20:04:45.92#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.20:04:45.92$vck44/vb=4,4 2006.173.20:04:45.92#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.20:04:45.92#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.20:04:45.92#ibcon#ireg 11 cls_cnt 2 2006.173.20:04:45.92#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.20:04:45.98#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.20:04:45.98#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.20:04:45.98#ibcon#enter wrdev, iclass 6, count 2 2006.173.20:04:45.98#ibcon#first serial, iclass 6, count 2 2006.173.20:04:45.98#ibcon#enter sib2, iclass 6, count 2 2006.173.20:04:45.98#ibcon#flushed, iclass 6, count 2 2006.173.20:04:45.98#ibcon#about to write, iclass 6, count 2 2006.173.20:04:45.98#ibcon#wrote, iclass 6, count 2 2006.173.20:04:45.98#ibcon#about to read 3, iclass 6, count 2 2006.173.20:04:46.00#ibcon#read 3, iclass 6, count 2 2006.173.20:04:46.00#ibcon#about to read 4, iclass 6, count 2 2006.173.20:04:46.00#ibcon#read 4, iclass 6, count 2 2006.173.20:04:46.00#ibcon#about to read 5, iclass 6, count 2 2006.173.20:04:46.00#ibcon#read 5, iclass 6, count 2 2006.173.20:04:46.00#ibcon#about to read 6, iclass 6, count 2 2006.173.20:04:46.00#ibcon#read 6, iclass 6, count 2 2006.173.20:04:46.00#ibcon#end of sib2, iclass 6, count 2 2006.173.20:04:46.00#ibcon#*mode == 0, iclass 6, count 2 2006.173.20:04:46.00#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.20:04:46.00#ibcon#[27=AT04-04\r\n] 2006.173.20:04:46.00#ibcon#*before write, iclass 6, count 2 2006.173.20:04:46.00#ibcon#enter sib2, iclass 6, count 2 2006.173.20:04:46.00#ibcon#flushed, iclass 6, count 2 2006.173.20:04:46.00#ibcon#about to write, iclass 6, count 2 2006.173.20:04:46.00#ibcon#wrote, iclass 6, count 2 2006.173.20:04:46.00#ibcon#about to read 3, iclass 6, count 2 2006.173.20:04:46.03#ibcon#read 3, iclass 6, count 2 2006.173.20:04:46.03#ibcon#about to read 4, iclass 6, count 2 2006.173.20:04:46.03#ibcon#read 4, iclass 6, count 2 2006.173.20:04:46.03#ibcon#about to read 5, iclass 6, count 2 2006.173.20:04:46.03#ibcon#read 5, iclass 6, count 2 2006.173.20:04:46.03#ibcon#about to read 6, iclass 6, count 2 2006.173.20:04:46.03#ibcon#read 6, iclass 6, count 2 2006.173.20:04:46.03#ibcon#end of sib2, iclass 6, count 2 2006.173.20:04:46.03#ibcon#*after write, iclass 6, count 2 2006.173.20:04:46.03#ibcon#*before return 0, iclass 6, count 2 2006.173.20:04:46.03#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.20:04:46.03#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.20:04:46.03#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.20:04:46.03#ibcon#ireg 7 cls_cnt 0 2006.173.20:04:46.03#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.20:04:46.15#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.20:04:46.15#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.20:04:46.15#ibcon#enter wrdev, iclass 6, count 0 2006.173.20:04:46.15#ibcon#first serial, iclass 6, count 0 2006.173.20:04:46.15#ibcon#enter sib2, iclass 6, count 0 2006.173.20:04:46.15#ibcon#flushed, iclass 6, count 0 2006.173.20:04:46.15#ibcon#about to write, iclass 6, count 0 2006.173.20:04:46.15#ibcon#wrote, iclass 6, count 0 2006.173.20:04:46.15#ibcon#about to read 3, iclass 6, count 0 2006.173.20:04:46.17#ibcon#read 3, iclass 6, count 0 2006.173.20:04:46.17#ibcon#about to read 4, iclass 6, count 0 2006.173.20:04:46.17#ibcon#read 4, iclass 6, count 0 2006.173.20:04:46.17#ibcon#about to read 5, iclass 6, count 0 2006.173.20:04:46.17#ibcon#read 5, iclass 6, count 0 2006.173.20:04:46.17#ibcon#about to read 6, iclass 6, count 0 2006.173.20:04:46.17#ibcon#read 6, iclass 6, count 0 2006.173.20:04:46.17#ibcon#end of sib2, iclass 6, count 0 2006.173.20:04:46.17#ibcon#*mode == 0, iclass 6, count 0 2006.173.20:04:46.17#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.20:04:46.17#ibcon#[27=USB\r\n] 2006.173.20:04:46.17#ibcon#*before write, iclass 6, count 0 2006.173.20:04:46.17#ibcon#enter sib2, iclass 6, count 0 2006.173.20:04:46.17#ibcon#flushed, iclass 6, count 0 2006.173.20:04:46.17#ibcon#about to write, iclass 6, count 0 2006.173.20:04:46.17#ibcon#wrote, iclass 6, count 0 2006.173.20:04:46.17#ibcon#about to read 3, iclass 6, count 0 2006.173.20:04:46.20#ibcon#read 3, iclass 6, count 0 2006.173.20:04:46.20#ibcon#about to read 4, iclass 6, count 0 2006.173.20:04:46.20#ibcon#read 4, iclass 6, count 0 2006.173.20:04:46.20#ibcon#about to read 5, iclass 6, count 0 2006.173.20:04:46.20#ibcon#read 5, iclass 6, count 0 2006.173.20:04:46.20#ibcon#about to read 6, iclass 6, count 0 2006.173.20:04:46.20#ibcon#read 6, iclass 6, count 0 2006.173.20:04:46.20#ibcon#end of sib2, iclass 6, count 0 2006.173.20:04:46.20#ibcon#*after write, iclass 6, count 0 2006.173.20:04:46.20#ibcon#*before return 0, iclass 6, count 0 2006.173.20:04:46.20#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.20:04:46.20#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.20:04:46.20#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.20:04:46.20#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.20:04:46.20$vck44/vblo=5,709.99 2006.173.20:04:46.20#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.20:04:46.20#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.20:04:46.20#ibcon#ireg 17 cls_cnt 0 2006.173.20:04:46.20#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.20:04:46.20#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.20:04:46.20#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.20:04:46.20#ibcon#enter wrdev, iclass 10, count 0 2006.173.20:04:46.20#ibcon#first serial, iclass 10, count 0 2006.173.20:04:46.20#ibcon#enter sib2, iclass 10, count 0 2006.173.20:04:46.20#ibcon#flushed, iclass 10, count 0 2006.173.20:04:46.20#ibcon#about to write, iclass 10, count 0 2006.173.20:04:46.20#ibcon#wrote, iclass 10, count 0 2006.173.20:04:46.20#ibcon#about to read 3, iclass 10, count 0 2006.173.20:04:46.22#ibcon#read 3, iclass 10, count 0 2006.173.20:04:46.22#ibcon#about to read 4, iclass 10, count 0 2006.173.20:04:46.22#ibcon#read 4, iclass 10, count 0 2006.173.20:04:46.22#ibcon#about to read 5, iclass 10, count 0 2006.173.20:04:46.22#ibcon#read 5, iclass 10, count 0 2006.173.20:04:46.22#ibcon#about to read 6, iclass 10, count 0 2006.173.20:04:46.22#ibcon#read 6, iclass 10, count 0 2006.173.20:04:46.22#ibcon#end of sib2, iclass 10, count 0 2006.173.20:04:46.22#ibcon#*mode == 0, iclass 10, count 0 2006.173.20:04:46.22#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.20:04:46.22#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.20:04:46.22#ibcon#*before write, iclass 10, count 0 2006.173.20:04:46.22#ibcon#enter sib2, iclass 10, count 0 2006.173.20:04:46.22#ibcon#flushed, iclass 10, count 0 2006.173.20:04:46.22#ibcon#about to write, iclass 10, count 0 2006.173.20:04:46.22#ibcon#wrote, iclass 10, count 0 2006.173.20:04:46.22#ibcon#about to read 3, iclass 10, count 0 2006.173.20:04:46.26#ibcon#read 3, iclass 10, count 0 2006.173.20:04:46.26#ibcon#about to read 4, iclass 10, count 0 2006.173.20:04:46.26#ibcon#read 4, iclass 10, count 0 2006.173.20:04:46.26#ibcon#about to read 5, iclass 10, count 0 2006.173.20:04:46.26#ibcon#read 5, iclass 10, count 0 2006.173.20:04:46.26#ibcon#about to read 6, iclass 10, count 0 2006.173.20:04:46.26#ibcon#read 6, iclass 10, count 0 2006.173.20:04:46.26#ibcon#end of sib2, iclass 10, count 0 2006.173.20:04:46.26#ibcon#*after write, iclass 10, count 0 2006.173.20:04:46.26#ibcon#*before return 0, iclass 10, count 0 2006.173.20:04:46.26#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.20:04:46.26#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.20:04:46.26#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.20:04:46.26#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.20:04:46.26$vck44/vb=5,4 2006.173.20:04:46.26#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.20:04:46.26#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.20:04:46.26#ibcon#ireg 11 cls_cnt 2 2006.173.20:04:46.26#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.20:04:46.32#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.20:04:46.32#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.20:04:46.32#ibcon#enter wrdev, iclass 12, count 2 2006.173.20:04:46.32#ibcon#first serial, iclass 12, count 2 2006.173.20:04:46.32#ibcon#enter sib2, iclass 12, count 2 2006.173.20:04:46.32#ibcon#flushed, iclass 12, count 2 2006.173.20:04:46.32#ibcon#about to write, iclass 12, count 2 2006.173.20:04:46.32#ibcon#wrote, iclass 12, count 2 2006.173.20:04:46.32#ibcon#about to read 3, iclass 12, count 2 2006.173.20:04:46.34#ibcon#read 3, iclass 12, count 2 2006.173.20:04:46.34#ibcon#about to read 4, iclass 12, count 2 2006.173.20:04:46.34#ibcon#read 4, iclass 12, count 2 2006.173.20:04:46.34#ibcon#about to read 5, iclass 12, count 2 2006.173.20:04:46.34#ibcon#read 5, iclass 12, count 2 2006.173.20:04:46.34#ibcon#about to read 6, iclass 12, count 2 2006.173.20:04:46.34#ibcon#read 6, iclass 12, count 2 2006.173.20:04:46.34#ibcon#end of sib2, iclass 12, count 2 2006.173.20:04:46.34#ibcon#*mode == 0, iclass 12, count 2 2006.173.20:04:46.34#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.20:04:46.34#ibcon#[27=AT05-04\r\n] 2006.173.20:04:46.34#ibcon#*before write, iclass 12, count 2 2006.173.20:04:46.34#ibcon#enter sib2, iclass 12, count 2 2006.173.20:04:46.34#ibcon#flushed, iclass 12, count 2 2006.173.20:04:46.34#ibcon#about to write, iclass 12, count 2 2006.173.20:04:46.34#ibcon#wrote, iclass 12, count 2 2006.173.20:04:46.34#ibcon#about to read 3, iclass 12, count 2 2006.173.20:04:46.37#ibcon#read 3, iclass 12, count 2 2006.173.20:04:46.37#ibcon#about to read 4, iclass 12, count 2 2006.173.20:04:46.37#ibcon#read 4, iclass 12, count 2 2006.173.20:04:46.37#ibcon#about to read 5, iclass 12, count 2 2006.173.20:04:46.37#ibcon#read 5, iclass 12, count 2 2006.173.20:04:46.37#ibcon#about to read 6, iclass 12, count 2 2006.173.20:04:46.37#ibcon#read 6, iclass 12, count 2 2006.173.20:04:46.37#ibcon#end of sib2, iclass 12, count 2 2006.173.20:04:46.37#ibcon#*after write, iclass 12, count 2 2006.173.20:04:46.37#ibcon#*before return 0, iclass 12, count 2 2006.173.20:04:46.37#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.20:04:46.37#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.20:04:46.37#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.20:04:46.37#ibcon#ireg 7 cls_cnt 0 2006.173.20:04:46.37#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.20:04:46.49#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.20:04:46.49#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.20:04:46.49#ibcon#enter wrdev, iclass 12, count 0 2006.173.20:04:46.49#ibcon#first serial, iclass 12, count 0 2006.173.20:04:46.49#ibcon#enter sib2, iclass 12, count 0 2006.173.20:04:46.49#ibcon#flushed, iclass 12, count 0 2006.173.20:04:46.49#ibcon#about to write, iclass 12, count 0 2006.173.20:04:46.49#ibcon#wrote, iclass 12, count 0 2006.173.20:04:46.49#ibcon#about to read 3, iclass 12, count 0 2006.173.20:04:46.51#ibcon#read 3, iclass 12, count 0 2006.173.20:04:46.51#ibcon#about to read 4, iclass 12, count 0 2006.173.20:04:46.51#ibcon#read 4, iclass 12, count 0 2006.173.20:04:46.51#ibcon#about to read 5, iclass 12, count 0 2006.173.20:04:46.51#ibcon#read 5, iclass 12, count 0 2006.173.20:04:46.51#ibcon#about to read 6, iclass 12, count 0 2006.173.20:04:46.51#ibcon#read 6, iclass 12, count 0 2006.173.20:04:46.51#ibcon#end of sib2, iclass 12, count 0 2006.173.20:04:46.51#ibcon#*mode == 0, iclass 12, count 0 2006.173.20:04:46.51#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.20:04:46.51#ibcon#[27=USB\r\n] 2006.173.20:04:46.51#ibcon#*before write, iclass 12, count 0 2006.173.20:04:46.51#ibcon#enter sib2, iclass 12, count 0 2006.173.20:04:46.51#ibcon#flushed, iclass 12, count 0 2006.173.20:04:46.51#ibcon#about to write, iclass 12, count 0 2006.173.20:04:46.51#ibcon#wrote, iclass 12, count 0 2006.173.20:04:46.51#ibcon#about to read 3, iclass 12, count 0 2006.173.20:04:46.54#ibcon#read 3, iclass 12, count 0 2006.173.20:04:46.54#ibcon#about to read 4, iclass 12, count 0 2006.173.20:04:46.54#ibcon#read 4, iclass 12, count 0 2006.173.20:04:46.54#ibcon#about to read 5, iclass 12, count 0 2006.173.20:04:46.54#ibcon#read 5, iclass 12, count 0 2006.173.20:04:46.54#ibcon#about to read 6, iclass 12, count 0 2006.173.20:04:46.54#ibcon#read 6, iclass 12, count 0 2006.173.20:04:46.54#ibcon#end of sib2, iclass 12, count 0 2006.173.20:04:46.54#ibcon#*after write, iclass 12, count 0 2006.173.20:04:46.54#ibcon#*before return 0, iclass 12, count 0 2006.173.20:04:46.54#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.20:04:46.54#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.20:04:46.54#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.20:04:46.54#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.20:04:46.54$vck44/vblo=6,719.99 2006.173.20:04:46.54#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.20:04:46.54#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.20:04:46.54#ibcon#ireg 17 cls_cnt 0 2006.173.20:04:46.54#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.20:04:46.54#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.20:04:46.54#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.20:04:46.54#ibcon#enter wrdev, iclass 14, count 0 2006.173.20:04:46.54#ibcon#first serial, iclass 14, count 0 2006.173.20:04:46.54#ibcon#enter sib2, iclass 14, count 0 2006.173.20:04:46.54#ibcon#flushed, iclass 14, count 0 2006.173.20:04:46.54#ibcon#about to write, iclass 14, count 0 2006.173.20:04:46.54#ibcon#wrote, iclass 14, count 0 2006.173.20:04:46.54#ibcon#about to read 3, iclass 14, count 0 2006.173.20:04:46.56#ibcon#read 3, iclass 14, count 0 2006.173.20:04:46.56#ibcon#about to read 4, iclass 14, count 0 2006.173.20:04:46.56#ibcon#read 4, iclass 14, count 0 2006.173.20:04:46.56#ibcon#about to read 5, iclass 14, count 0 2006.173.20:04:46.56#ibcon#read 5, iclass 14, count 0 2006.173.20:04:46.56#ibcon#about to read 6, iclass 14, count 0 2006.173.20:04:46.56#ibcon#read 6, iclass 14, count 0 2006.173.20:04:46.56#ibcon#end of sib2, iclass 14, count 0 2006.173.20:04:46.56#ibcon#*mode == 0, iclass 14, count 0 2006.173.20:04:46.56#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.20:04:46.56#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.20:04:46.56#ibcon#*before write, iclass 14, count 0 2006.173.20:04:46.56#ibcon#enter sib2, iclass 14, count 0 2006.173.20:04:46.56#ibcon#flushed, iclass 14, count 0 2006.173.20:04:46.56#ibcon#about to write, iclass 14, count 0 2006.173.20:04:46.56#ibcon#wrote, iclass 14, count 0 2006.173.20:04:46.56#ibcon#about to read 3, iclass 14, count 0 2006.173.20:04:46.60#ibcon#read 3, iclass 14, count 0 2006.173.20:04:46.60#ibcon#about to read 4, iclass 14, count 0 2006.173.20:04:46.60#ibcon#read 4, iclass 14, count 0 2006.173.20:04:46.60#ibcon#about to read 5, iclass 14, count 0 2006.173.20:04:46.60#ibcon#read 5, iclass 14, count 0 2006.173.20:04:46.60#ibcon#about to read 6, iclass 14, count 0 2006.173.20:04:46.60#ibcon#read 6, iclass 14, count 0 2006.173.20:04:46.60#ibcon#end of sib2, iclass 14, count 0 2006.173.20:04:46.60#ibcon#*after write, iclass 14, count 0 2006.173.20:04:46.60#ibcon#*before return 0, iclass 14, count 0 2006.173.20:04:46.60#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.20:04:46.60#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.20:04:46.60#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.20:04:46.60#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.20:04:46.60$vck44/vb=6,4 2006.173.20:04:46.60#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.20:04:46.60#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.20:04:46.60#ibcon#ireg 11 cls_cnt 2 2006.173.20:04:46.60#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.20:04:46.66#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.20:04:46.66#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.20:04:46.66#ibcon#enter wrdev, iclass 16, count 2 2006.173.20:04:46.66#ibcon#first serial, iclass 16, count 2 2006.173.20:04:46.66#ibcon#enter sib2, iclass 16, count 2 2006.173.20:04:46.66#ibcon#flushed, iclass 16, count 2 2006.173.20:04:46.66#ibcon#about to write, iclass 16, count 2 2006.173.20:04:46.66#ibcon#wrote, iclass 16, count 2 2006.173.20:04:46.66#ibcon#about to read 3, iclass 16, count 2 2006.173.20:04:46.68#ibcon#read 3, iclass 16, count 2 2006.173.20:04:46.68#ibcon#about to read 4, iclass 16, count 2 2006.173.20:04:46.68#ibcon#read 4, iclass 16, count 2 2006.173.20:04:46.68#ibcon#about to read 5, iclass 16, count 2 2006.173.20:04:46.68#ibcon#read 5, iclass 16, count 2 2006.173.20:04:46.68#ibcon#about to read 6, iclass 16, count 2 2006.173.20:04:46.68#ibcon#read 6, iclass 16, count 2 2006.173.20:04:46.68#ibcon#end of sib2, iclass 16, count 2 2006.173.20:04:46.68#ibcon#*mode == 0, iclass 16, count 2 2006.173.20:04:46.68#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.20:04:46.68#ibcon#[27=AT06-04\r\n] 2006.173.20:04:46.68#ibcon#*before write, iclass 16, count 2 2006.173.20:04:46.68#ibcon#enter sib2, iclass 16, count 2 2006.173.20:04:46.68#ibcon#flushed, iclass 16, count 2 2006.173.20:04:46.68#ibcon#about to write, iclass 16, count 2 2006.173.20:04:46.68#ibcon#wrote, iclass 16, count 2 2006.173.20:04:46.68#ibcon#about to read 3, iclass 16, count 2 2006.173.20:04:46.71#ibcon#read 3, iclass 16, count 2 2006.173.20:04:46.71#ibcon#about to read 4, iclass 16, count 2 2006.173.20:04:46.71#ibcon#read 4, iclass 16, count 2 2006.173.20:04:46.71#ibcon#about to read 5, iclass 16, count 2 2006.173.20:04:46.71#ibcon#read 5, iclass 16, count 2 2006.173.20:04:46.71#ibcon#about to read 6, iclass 16, count 2 2006.173.20:04:46.71#ibcon#read 6, iclass 16, count 2 2006.173.20:04:46.71#ibcon#end of sib2, iclass 16, count 2 2006.173.20:04:46.71#ibcon#*after write, iclass 16, count 2 2006.173.20:04:46.71#ibcon#*before return 0, iclass 16, count 2 2006.173.20:04:46.71#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.20:04:46.71#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.20:04:46.71#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.20:04:46.71#ibcon#ireg 7 cls_cnt 0 2006.173.20:04:46.71#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.20:04:46.83#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.20:04:46.83#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.20:04:46.83#ibcon#enter wrdev, iclass 16, count 0 2006.173.20:04:46.83#ibcon#first serial, iclass 16, count 0 2006.173.20:04:46.83#ibcon#enter sib2, iclass 16, count 0 2006.173.20:04:46.83#ibcon#flushed, iclass 16, count 0 2006.173.20:04:46.83#ibcon#about to write, iclass 16, count 0 2006.173.20:04:46.83#ibcon#wrote, iclass 16, count 0 2006.173.20:04:46.83#ibcon#about to read 3, iclass 16, count 0 2006.173.20:04:46.85#ibcon#read 3, iclass 16, count 0 2006.173.20:04:46.85#ibcon#about to read 4, iclass 16, count 0 2006.173.20:04:46.85#ibcon#read 4, iclass 16, count 0 2006.173.20:04:46.85#ibcon#about to read 5, iclass 16, count 0 2006.173.20:04:46.85#ibcon#read 5, iclass 16, count 0 2006.173.20:04:46.85#ibcon#about to read 6, iclass 16, count 0 2006.173.20:04:46.85#ibcon#read 6, iclass 16, count 0 2006.173.20:04:46.85#ibcon#end of sib2, iclass 16, count 0 2006.173.20:04:46.85#ibcon#*mode == 0, iclass 16, count 0 2006.173.20:04:46.85#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.20:04:46.85#ibcon#[27=USB\r\n] 2006.173.20:04:46.85#ibcon#*before write, iclass 16, count 0 2006.173.20:04:46.85#ibcon#enter sib2, iclass 16, count 0 2006.173.20:04:46.85#ibcon#flushed, iclass 16, count 0 2006.173.20:04:46.85#ibcon#about to write, iclass 16, count 0 2006.173.20:04:46.85#ibcon#wrote, iclass 16, count 0 2006.173.20:04:46.85#ibcon#about to read 3, iclass 16, count 0 2006.173.20:04:46.88#ibcon#read 3, iclass 16, count 0 2006.173.20:04:46.88#ibcon#about to read 4, iclass 16, count 0 2006.173.20:04:46.88#ibcon#read 4, iclass 16, count 0 2006.173.20:04:46.88#ibcon#about to read 5, iclass 16, count 0 2006.173.20:04:46.88#ibcon#read 5, iclass 16, count 0 2006.173.20:04:46.88#ibcon#about to read 6, iclass 16, count 0 2006.173.20:04:46.88#ibcon#read 6, iclass 16, count 0 2006.173.20:04:46.88#ibcon#end of sib2, iclass 16, count 0 2006.173.20:04:46.88#ibcon#*after write, iclass 16, count 0 2006.173.20:04:46.88#ibcon#*before return 0, iclass 16, count 0 2006.173.20:04:46.88#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.20:04:46.88#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.20:04:46.88#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.20:04:46.88#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.20:04:46.88$vck44/vblo=7,734.99 2006.173.20:04:46.88#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.20:04:46.88#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.20:04:46.88#ibcon#ireg 17 cls_cnt 0 2006.173.20:04:46.88#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.20:04:46.88#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.20:04:46.88#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.20:04:46.88#ibcon#enter wrdev, iclass 18, count 0 2006.173.20:04:46.88#ibcon#first serial, iclass 18, count 0 2006.173.20:04:46.88#ibcon#enter sib2, iclass 18, count 0 2006.173.20:04:46.88#ibcon#flushed, iclass 18, count 0 2006.173.20:04:46.88#ibcon#about to write, iclass 18, count 0 2006.173.20:04:46.88#ibcon#wrote, iclass 18, count 0 2006.173.20:04:46.88#ibcon#about to read 3, iclass 18, count 0 2006.173.20:04:46.90#ibcon#read 3, iclass 18, count 0 2006.173.20:04:46.90#ibcon#about to read 4, iclass 18, count 0 2006.173.20:04:46.90#ibcon#read 4, iclass 18, count 0 2006.173.20:04:46.90#ibcon#about to read 5, iclass 18, count 0 2006.173.20:04:46.90#ibcon#read 5, iclass 18, count 0 2006.173.20:04:46.90#ibcon#about to read 6, iclass 18, count 0 2006.173.20:04:46.90#ibcon#read 6, iclass 18, count 0 2006.173.20:04:46.90#ibcon#end of sib2, iclass 18, count 0 2006.173.20:04:46.90#ibcon#*mode == 0, iclass 18, count 0 2006.173.20:04:46.90#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.20:04:46.90#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.20:04:46.90#ibcon#*before write, iclass 18, count 0 2006.173.20:04:46.90#ibcon#enter sib2, iclass 18, count 0 2006.173.20:04:46.90#ibcon#flushed, iclass 18, count 0 2006.173.20:04:46.90#ibcon#about to write, iclass 18, count 0 2006.173.20:04:46.90#ibcon#wrote, iclass 18, count 0 2006.173.20:04:46.90#ibcon#about to read 3, iclass 18, count 0 2006.173.20:04:46.94#ibcon#read 3, iclass 18, count 0 2006.173.20:04:46.94#ibcon#about to read 4, iclass 18, count 0 2006.173.20:04:46.94#ibcon#read 4, iclass 18, count 0 2006.173.20:04:46.94#ibcon#about to read 5, iclass 18, count 0 2006.173.20:04:46.94#ibcon#read 5, iclass 18, count 0 2006.173.20:04:46.94#ibcon#about to read 6, iclass 18, count 0 2006.173.20:04:46.94#ibcon#read 6, iclass 18, count 0 2006.173.20:04:46.94#ibcon#end of sib2, iclass 18, count 0 2006.173.20:04:46.94#ibcon#*after write, iclass 18, count 0 2006.173.20:04:46.94#ibcon#*before return 0, iclass 18, count 0 2006.173.20:04:46.94#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.20:04:46.94#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.20:04:46.94#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.20:04:46.94#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.20:04:46.94$vck44/vb=7,4 2006.173.20:04:46.94#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.20:04:46.94#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.20:04:46.94#ibcon#ireg 11 cls_cnt 2 2006.173.20:04:46.94#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.20:04:47.00#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.20:04:47.00#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.20:04:47.00#ibcon#enter wrdev, iclass 20, count 2 2006.173.20:04:47.00#ibcon#first serial, iclass 20, count 2 2006.173.20:04:47.00#ibcon#enter sib2, iclass 20, count 2 2006.173.20:04:47.00#ibcon#flushed, iclass 20, count 2 2006.173.20:04:47.00#ibcon#about to write, iclass 20, count 2 2006.173.20:04:47.00#ibcon#wrote, iclass 20, count 2 2006.173.20:04:47.00#ibcon#about to read 3, iclass 20, count 2 2006.173.20:04:47.02#ibcon#read 3, iclass 20, count 2 2006.173.20:04:47.02#ibcon#about to read 4, iclass 20, count 2 2006.173.20:04:47.02#ibcon#read 4, iclass 20, count 2 2006.173.20:04:47.02#ibcon#about to read 5, iclass 20, count 2 2006.173.20:04:47.02#ibcon#read 5, iclass 20, count 2 2006.173.20:04:47.02#ibcon#about to read 6, iclass 20, count 2 2006.173.20:04:47.02#ibcon#read 6, iclass 20, count 2 2006.173.20:04:47.02#ibcon#end of sib2, iclass 20, count 2 2006.173.20:04:47.02#ibcon#*mode == 0, iclass 20, count 2 2006.173.20:04:47.02#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.20:04:47.02#ibcon#[27=AT07-04\r\n] 2006.173.20:04:47.02#ibcon#*before write, iclass 20, count 2 2006.173.20:04:47.02#ibcon#enter sib2, iclass 20, count 2 2006.173.20:04:47.02#ibcon#flushed, iclass 20, count 2 2006.173.20:04:47.02#ibcon#about to write, iclass 20, count 2 2006.173.20:04:47.02#ibcon#wrote, iclass 20, count 2 2006.173.20:04:47.02#ibcon#about to read 3, iclass 20, count 2 2006.173.20:04:47.05#ibcon#read 3, iclass 20, count 2 2006.173.20:04:47.05#ibcon#about to read 4, iclass 20, count 2 2006.173.20:04:47.05#ibcon#read 4, iclass 20, count 2 2006.173.20:04:47.05#ibcon#about to read 5, iclass 20, count 2 2006.173.20:04:47.05#ibcon#read 5, iclass 20, count 2 2006.173.20:04:47.05#ibcon#about to read 6, iclass 20, count 2 2006.173.20:04:47.05#ibcon#read 6, iclass 20, count 2 2006.173.20:04:47.05#ibcon#end of sib2, iclass 20, count 2 2006.173.20:04:47.05#ibcon#*after write, iclass 20, count 2 2006.173.20:04:47.05#ibcon#*before return 0, iclass 20, count 2 2006.173.20:04:47.05#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.20:04:47.05#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.20:04:47.05#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.20:04:47.05#ibcon#ireg 7 cls_cnt 0 2006.173.20:04:47.05#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.20:04:47.17#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.20:04:47.17#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.20:04:47.17#ibcon#enter wrdev, iclass 20, count 0 2006.173.20:04:47.17#ibcon#first serial, iclass 20, count 0 2006.173.20:04:47.17#ibcon#enter sib2, iclass 20, count 0 2006.173.20:04:47.17#ibcon#flushed, iclass 20, count 0 2006.173.20:04:47.17#ibcon#about to write, iclass 20, count 0 2006.173.20:04:47.17#ibcon#wrote, iclass 20, count 0 2006.173.20:04:47.17#ibcon#about to read 3, iclass 20, count 0 2006.173.20:04:47.19#ibcon#read 3, iclass 20, count 0 2006.173.20:04:47.19#ibcon#about to read 4, iclass 20, count 0 2006.173.20:04:47.19#ibcon#read 4, iclass 20, count 0 2006.173.20:04:47.19#ibcon#about to read 5, iclass 20, count 0 2006.173.20:04:47.19#ibcon#read 5, iclass 20, count 0 2006.173.20:04:47.19#ibcon#about to read 6, iclass 20, count 0 2006.173.20:04:47.19#ibcon#read 6, iclass 20, count 0 2006.173.20:04:47.19#ibcon#end of sib2, iclass 20, count 0 2006.173.20:04:47.19#ibcon#*mode == 0, iclass 20, count 0 2006.173.20:04:47.19#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.20:04:47.19#ibcon#[27=USB\r\n] 2006.173.20:04:47.19#ibcon#*before write, iclass 20, count 0 2006.173.20:04:47.19#ibcon#enter sib2, iclass 20, count 0 2006.173.20:04:47.19#ibcon#flushed, iclass 20, count 0 2006.173.20:04:47.19#ibcon#about to write, iclass 20, count 0 2006.173.20:04:47.19#ibcon#wrote, iclass 20, count 0 2006.173.20:04:47.19#ibcon#about to read 3, iclass 20, count 0 2006.173.20:04:47.22#ibcon#read 3, iclass 20, count 0 2006.173.20:04:47.22#ibcon#about to read 4, iclass 20, count 0 2006.173.20:04:47.22#ibcon#read 4, iclass 20, count 0 2006.173.20:04:47.22#ibcon#about to read 5, iclass 20, count 0 2006.173.20:04:47.22#ibcon#read 5, iclass 20, count 0 2006.173.20:04:47.22#ibcon#about to read 6, iclass 20, count 0 2006.173.20:04:47.22#ibcon#read 6, iclass 20, count 0 2006.173.20:04:47.22#ibcon#end of sib2, iclass 20, count 0 2006.173.20:04:47.22#ibcon#*after write, iclass 20, count 0 2006.173.20:04:47.22#ibcon#*before return 0, iclass 20, count 0 2006.173.20:04:47.22#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.20:04:47.22#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.20:04:47.22#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.20:04:47.22#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.20:04:47.22$vck44/vblo=8,744.99 2006.173.20:04:47.22#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.20:04:47.22#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.20:04:47.22#ibcon#ireg 17 cls_cnt 0 2006.173.20:04:47.22#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.20:04:47.22#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.20:04:47.22#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.20:04:47.22#ibcon#enter wrdev, iclass 22, count 0 2006.173.20:04:47.22#ibcon#first serial, iclass 22, count 0 2006.173.20:04:47.22#ibcon#enter sib2, iclass 22, count 0 2006.173.20:04:47.22#ibcon#flushed, iclass 22, count 0 2006.173.20:04:47.22#ibcon#about to write, iclass 22, count 0 2006.173.20:04:47.22#ibcon#wrote, iclass 22, count 0 2006.173.20:04:47.22#ibcon#about to read 3, iclass 22, count 0 2006.173.20:04:47.24#ibcon#read 3, iclass 22, count 0 2006.173.20:04:47.24#ibcon#about to read 4, iclass 22, count 0 2006.173.20:04:47.24#ibcon#read 4, iclass 22, count 0 2006.173.20:04:47.24#ibcon#about to read 5, iclass 22, count 0 2006.173.20:04:47.24#ibcon#read 5, iclass 22, count 0 2006.173.20:04:47.24#ibcon#about to read 6, iclass 22, count 0 2006.173.20:04:47.24#ibcon#read 6, iclass 22, count 0 2006.173.20:04:47.24#ibcon#end of sib2, iclass 22, count 0 2006.173.20:04:47.24#ibcon#*mode == 0, iclass 22, count 0 2006.173.20:04:47.24#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.20:04:47.24#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.20:04:47.24#ibcon#*before write, iclass 22, count 0 2006.173.20:04:47.24#ibcon#enter sib2, iclass 22, count 0 2006.173.20:04:47.24#ibcon#flushed, iclass 22, count 0 2006.173.20:04:47.24#ibcon#about to write, iclass 22, count 0 2006.173.20:04:47.24#ibcon#wrote, iclass 22, count 0 2006.173.20:04:47.24#ibcon#about to read 3, iclass 22, count 0 2006.173.20:04:47.28#ibcon#read 3, iclass 22, count 0 2006.173.20:04:47.28#ibcon#about to read 4, iclass 22, count 0 2006.173.20:04:47.28#ibcon#read 4, iclass 22, count 0 2006.173.20:04:47.28#ibcon#about to read 5, iclass 22, count 0 2006.173.20:04:47.28#ibcon#read 5, iclass 22, count 0 2006.173.20:04:47.28#ibcon#about to read 6, iclass 22, count 0 2006.173.20:04:47.28#ibcon#read 6, iclass 22, count 0 2006.173.20:04:47.28#ibcon#end of sib2, iclass 22, count 0 2006.173.20:04:47.28#ibcon#*after write, iclass 22, count 0 2006.173.20:04:47.28#ibcon#*before return 0, iclass 22, count 0 2006.173.20:04:47.28#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.20:04:47.28#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.20:04:47.28#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.20:04:47.28#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.20:04:47.28$vck44/vb=8,4 2006.173.20:04:47.28#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.20:04:47.28#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.20:04:47.28#ibcon#ireg 11 cls_cnt 2 2006.173.20:04:47.28#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.20:04:47.34#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.20:04:47.34#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.20:04:47.34#ibcon#enter wrdev, iclass 24, count 2 2006.173.20:04:47.34#ibcon#first serial, iclass 24, count 2 2006.173.20:04:47.34#ibcon#enter sib2, iclass 24, count 2 2006.173.20:04:47.34#ibcon#flushed, iclass 24, count 2 2006.173.20:04:47.34#ibcon#about to write, iclass 24, count 2 2006.173.20:04:47.34#ibcon#wrote, iclass 24, count 2 2006.173.20:04:47.34#ibcon#about to read 3, iclass 24, count 2 2006.173.20:04:47.36#ibcon#read 3, iclass 24, count 2 2006.173.20:04:47.36#ibcon#about to read 4, iclass 24, count 2 2006.173.20:04:47.36#ibcon#read 4, iclass 24, count 2 2006.173.20:04:47.36#ibcon#about to read 5, iclass 24, count 2 2006.173.20:04:47.36#ibcon#read 5, iclass 24, count 2 2006.173.20:04:47.36#ibcon#about to read 6, iclass 24, count 2 2006.173.20:04:47.36#ibcon#read 6, iclass 24, count 2 2006.173.20:04:47.36#ibcon#end of sib2, iclass 24, count 2 2006.173.20:04:47.36#ibcon#*mode == 0, iclass 24, count 2 2006.173.20:04:47.36#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.20:04:47.36#ibcon#[27=AT08-04\r\n] 2006.173.20:04:47.36#ibcon#*before write, iclass 24, count 2 2006.173.20:04:47.36#ibcon#enter sib2, iclass 24, count 2 2006.173.20:04:47.36#ibcon#flushed, iclass 24, count 2 2006.173.20:04:47.36#ibcon#about to write, iclass 24, count 2 2006.173.20:04:47.36#ibcon#wrote, iclass 24, count 2 2006.173.20:04:47.36#ibcon#about to read 3, iclass 24, count 2 2006.173.20:04:47.39#ibcon#read 3, iclass 24, count 2 2006.173.20:04:47.39#ibcon#about to read 4, iclass 24, count 2 2006.173.20:04:47.39#ibcon#read 4, iclass 24, count 2 2006.173.20:04:47.39#ibcon#about to read 5, iclass 24, count 2 2006.173.20:04:47.39#ibcon#read 5, iclass 24, count 2 2006.173.20:04:47.39#ibcon#about to read 6, iclass 24, count 2 2006.173.20:04:47.39#ibcon#read 6, iclass 24, count 2 2006.173.20:04:47.39#ibcon#end of sib2, iclass 24, count 2 2006.173.20:04:47.39#ibcon#*after write, iclass 24, count 2 2006.173.20:04:47.39#ibcon#*before return 0, iclass 24, count 2 2006.173.20:04:47.39#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.20:04:47.39#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.20:04:47.39#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.20:04:47.39#ibcon#ireg 7 cls_cnt 0 2006.173.20:04:47.39#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.20:04:47.51#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.20:04:47.51#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.20:04:47.51#ibcon#enter wrdev, iclass 24, count 0 2006.173.20:04:47.51#ibcon#first serial, iclass 24, count 0 2006.173.20:04:47.51#ibcon#enter sib2, iclass 24, count 0 2006.173.20:04:47.51#ibcon#flushed, iclass 24, count 0 2006.173.20:04:47.51#ibcon#about to write, iclass 24, count 0 2006.173.20:04:47.51#ibcon#wrote, iclass 24, count 0 2006.173.20:04:47.51#ibcon#about to read 3, iclass 24, count 0 2006.173.20:04:47.53#ibcon#read 3, iclass 24, count 0 2006.173.20:04:47.53#ibcon#about to read 4, iclass 24, count 0 2006.173.20:04:47.53#ibcon#read 4, iclass 24, count 0 2006.173.20:04:47.53#ibcon#about to read 5, iclass 24, count 0 2006.173.20:04:47.53#ibcon#read 5, iclass 24, count 0 2006.173.20:04:47.53#ibcon#about to read 6, iclass 24, count 0 2006.173.20:04:47.53#ibcon#read 6, iclass 24, count 0 2006.173.20:04:47.53#ibcon#end of sib2, iclass 24, count 0 2006.173.20:04:47.53#ibcon#*mode == 0, iclass 24, count 0 2006.173.20:04:47.53#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.20:04:47.53#ibcon#[27=USB\r\n] 2006.173.20:04:47.53#ibcon#*before write, iclass 24, count 0 2006.173.20:04:47.53#ibcon#enter sib2, iclass 24, count 0 2006.173.20:04:47.53#ibcon#flushed, iclass 24, count 0 2006.173.20:04:47.53#ibcon#about to write, iclass 24, count 0 2006.173.20:04:47.53#ibcon#wrote, iclass 24, count 0 2006.173.20:04:47.53#ibcon#about to read 3, iclass 24, count 0 2006.173.20:04:47.56#ibcon#read 3, iclass 24, count 0 2006.173.20:04:47.56#ibcon#about to read 4, iclass 24, count 0 2006.173.20:04:47.56#ibcon#read 4, iclass 24, count 0 2006.173.20:04:47.56#ibcon#about to read 5, iclass 24, count 0 2006.173.20:04:47.56#ibcon#read 5, iclass 24, count 0 2006.173.20:04:47.56#ibcon#about to read 6, iclass 24, count 0 2006.173.20:04:47.56#ibcon#read 6, iclass 24, count 0 2006.173.20:04:47.56#ibcon#end of sib2, iclass 24, count 0 2006.173.20:04:47.56#ibcon#*after write, iclass 24, count 0 2006.173.20:04:47.56#ibcon#*before return 0, iclass 24, count 0 2006.173.20:04:47.56#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.20:04:47.56#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.20:04:47.56#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.20:04:47.56#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.20:04:47.56$vck44/vabw=wide 2006.173.20:04:47.56#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.20:04:47.56#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.20:04:47.56#ibcon#ireg 8 cls_cnt 0 2006.173.20:04:47.56#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.20:04:47.56#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.20:04:47.56#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.20:04:47.56#ibcon#enter wrdev, iclass 26, count 0 2006.173.20:04:47.56#ibcon#first serial, iclass 26, count 0 2006.173.20:04:47.56#ibcon#enter sib2, iclass 26, count 0 2006.173.20:04:47.56#ibcon#flushed, iclass 26, count 0 2006.173.20:04:47.56#ibcon#about to write, iclass 26, count 0 2006.173.20:04:47.56#ibcon#wrote, iclass 26, count 0 2006.173.20:04:47.56#ibcon#about to read 3, iclass 26, count 0 2006.173.20:04:47.58#ibcon#read 3, iclass 26, count 0 2006.173.20:04:47.58#ibcon#about to read 4, iclass 26, count 0 2006.173.20:04:47.58#ibcon#read 4, iclass 26, count 0 2006.173.20:04:47.58#ibcon#about to read 5, iclass 26, count 0 2006.173.20:04:47.58#ibcon#read 5, iclass 26, count 0 2006.173.20:04:47.58#ibcon#about to read 6, iclass 26, count 0 2006.173.20:04:47.58#ibcon#read 6, iclass 26, count 0 2006.173.20:04:47.58#ibcon#end of sib2, iclass 26, count 0 2006.173.20:04:47.58#ibcon#*mode == 0, iclass 26, count 0 2006.173.20:04:47.58#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.20:04:47.58#ibcon#[25=BW32\r\n] 2006.173.20:04:47.58#ibcon#*before write, iclass 26, count 0 2006.173.20:04:47.58#ibcon#enter sib2, iclass 26, count 0 2006.173.20:04:47.58#ibcon#flushed, iclass 26, count 0 2006.173.20:04:47.58#ibcon#about to write, iclass 26, count 0 2006.173.20:04:47.58#ibcon#wrote, iclass 26, count 0 2006.173.20:04:47.58#ibcon#about to read 3, iclass 26, count 0 2006.173.20:04:47.61#ibcon#read 3, iclass 26, count 0 2006.173.20:04:47.61#ibcon#about to read 4, iclass 26, count 0 2006.173.20:04:47.61#ibcon#read 4, iclass 26, count 0 2006.173.20:04:47.61#ibcon#about to read 5, iclass 26, count 0 2006.173.20:04:47.61#ibcon#read 5, iclass 26, count 0 2006.173.20:04:47.61#ibcon#about to read 6, iclass 26, count 0 2006.173.20:04:47.61#ibcon#read 6, iclass 26, count 0 2006.173.20:04:47.61#ibcon#end of sib2, iclass 26, count 0 2006.173.20:04:47.61#ibcon#*after write, iclass 26, count 0 2006.173.20:04:47.61#ibcon#*before return 0, iclass 26, count 0 2006.173.20:04:47.61#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.20:04:47.61#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.20:04:47.61#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.20:04:47.61#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.20:04:47.61$vck44/vbbw=wide 2006.173.20:04:47.61#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.20:04:47.61#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.20:04:47.61#ibcon#ireg 8 cls_cnt 0 2006.173.20:04:47.61#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.20:04:47.68#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.20:04:47.68#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.20:04:47.68#ibcon#enter wrdev, iclass 28, count 0 2006.173.20:04:47.68#ibcon#first serial, iclass 28, count 0 2006.173.20:04:47.68#ibcon#enter sib2, iclass 28, count 0 2006.173.20:04:47.68#ibcon#flushed, iclass 28, count 0 2006.173.20:04:47.68#ibcon#about to write, iclass 28, count 0 2006.173.20:04:47.68#ibcon#wrote, iclass 28, count 0 2006.173.20:04:47.68#ibcon#about to read 3, iclass 28, count 0 2006.173.20:04:47.70#ibcon#read 3, iclass 28, count 0 2006.173.20:04:47.70#ibcon#about to read 4, iclass 28, count 0 2006.173.20:04:47.70#ibcon#read 4, iclass 28, count 0 2006.173.20:04:47.70#ibcon#about to read 5, iclass 28, count 0 2006.173.20:04:47.70#ibcon#read 5, iclass 28, count 0 2006.173.20:04:47.70#ibcon#about to read 6, iclass 28, count 0 2006.173.20:04:47.70#ibcon#read 6, iclass 28, count 0 2006.173.20:04:47.70#ibcon#end of sib2, iclass 28, count 0 2006.173.20:04:47.70#ibcon#*mode == 0, iclass 28, count 0 2006.173.20:04:47.70#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.20:04:47.70#ibcon#[27=BW32\r\n] 2006.173.20:04:47.70#ibcon#*before write, iclass 28, count 0 2006.173.20:04:47.70#ibcon#enter sib2, iclass 28, count 0 2006.173.20:04:47.70#ibcon#flushed, iclass 28, count 0 2006.173.20:04:47.70#ibcon#about to write, iclass 28, count 0 2006.173.20:04:47.70#ibcon#wrote, iclass 28, count 0 2006.173.20:04:47.70#ibcon#about to read 3, iclass 28, count 0 2006.173.20:04:47.73#ibcon#read 3, iclass 28, count 0 2006.173.20:04:47.73#ibcon#about to read 4, iclass 28, count 0 2006.173.20:04:47.73#ibcon#read 4, iclass 28, count 0 2006.173.20:04:47.73#ibcon#about to read 5, iclass 28, count 0 2006.173.20:04:47.73#ibcon#read 5, iclass 28, count 0 2006.173.20:04:47.73#ibcon#about to read 6, iclass 28, count 0 2006.173.20:04:47.73#ibcon#read 6, iclass 28, count 0 2006.173.20:04:47.73#ibcon#end of sib2, iclass 28, count 0 2006.173.20:04:47.73#ibcon#*after write, iclass 28, count 0 2006.173.20:04:47.73#ibcon#*before return 0, iclass 28, count 0 2006.173.20:04:47.73#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.20:04:47.73#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.20:04:47.73#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.20:04:47.73#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.20:04:47.73$setupk4/ifdk4 2006.173.20:04:47.73$ifdk4/lo= 2006.173.20:04:47.73$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.20:04:47.73$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.20:04:47.73$ifdk4/patch= 2006.173.20:04:47.73$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.20:04:47.73$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.20:04:47.73$setupk4/!*+20s 2006.173.20:04:52.03#abcon#<5=/06 0.5 0.9 19.401001002.7\r\n> 2006.173.20:04:52.05#abcon#{5=INTERFACE CLEAR} 2006.173.20:04:52.11#abcon#[5=S1D000X0/0*\r\n] 2006.173.20:05:01.14#trakl#Source acquired 2006.173.20:05:02.14#flagr#flagr/antenna,acquired 2006.173.20:05:02.20#abcon#<5=/06 0.5 0.8 19.401001002.7\r\n> 2006.173.20:05:02.22#abcon#{5=INTERFACE CLEAR} 2006.173.20:05:02.24$setupk4/"tpicd 2006.173.20:05:02.24$setupk4/echo=off 2006.173.20:05:02.24$setupk4/xlog=off 2006.173.20:05:02.24:!2006.173.20:09:27 2006.173.20:09:27.00:preob 2006.173.20:09:27.14/onsource/TRACKING 2006.173.20:09:27.14:!2006.173.20:09:37 2006.173.20:09:37.00:"tape 2006.173.20:09:37.00:"st=record 2006.173.20:09:37.00:data_valid=on 2006.173.20:09:37.00:midob 2006.173.20:09:38.14/onsource/TRACKING 2006.173.20:09:38.14/wx/19.48,1002.7,100 2006.173.20:09:38.36/cable/+6.5163E-03 2006.173.20:09:39.45/va/01,07,usb,yes,35,37 2006.173.20:09:39.45/va/02,06,usb,yes,34,35 2006.173.20:09:39.45/va/03,05,usb,yes,44,46 2006.173.20:09:39.45/va/04,06,usb,yes,35,37 2006.173.20:09:39.45/va/05,04,usb,yes,27,28 2006.173.20:09:39.45/va/06,03,usb,yes,39,38 2006.173.20:09:39.45/va/07,04,usb,yes,31,32 2006.173.20:09:39.45/va/08,04,usb,yes,27,32 2006.173.20:09:39.68/valo/01,524.99,yes,locked 2006.173.20:09:39.68/valo/02,534.99,yes,locked 2006.173.20:09:39.68/valo/03,564.99,yes,locked 2006.173.20:09:39.68/valo/04,624.99,yes,locked 2006.173.20:09:39.68/valo/05,734.99,yes,locked 2006.173.20:09:39.68/valo/06,814.99,yes,locked 2006.173.20:09:39.68/valo/07,864.99,yes,locked 2006.173.20:09:39.68/valo/08,884.99,yes,locked 2006.173.20:09:40.77/vb/01,04,usb,yes,28,26 2006.173.20:09:40.77/vb/02,04,usb,yes,31,31 2006.173.20:09:40.77/vb/03,04,usb,yes,28,31 2006.173.20:09:40.77/vb/04,04,usb,yes,32,31 2006.173.20:09:40.77/vb/05,04,usb,yes,25,27 2006.173.20:09:40.77/vb/06,04,usb,yes,29,25 2006.173.20:09:40.77/vb/07,04,usb,yes,29,29 2006.173.20:09:40.77/vb/08,04,usb,yes,26,30 2006.173.20:09:41.00/vblo/01,629.99,yes,locked 2006.173.20:09:41.00/vblo/02,634.99,yes,locked 2006.173.20:09:41.00/vblo/03,649.99,yes,locked 2006.173.20:09:41.00/vblo/04,679.99,yes,locked 2006.173.20:09:41.00/vblo/05,709.99,yes,locked 2006.173.20:09:41.00/vblo/06,719.99,yes,locked 2006.173.20:09:41.00/vblo/07,734.99,yes,locked 2006.173.20:09:41.00/vblo/08,744.99,yes,locked 2006.173.20:09:41.15/vabw/8 2006.173.20:09:41.30/vbbw/8 2006.173.20:09:41.39/xfe/off,on,14.7 2006.173.20:09:41.76/ifatt/23,28,28,28 2006.173.20:09:42.07/fmout-gps/S +3.88E-07 2006.173.20:09:42.11:!2006.173.20:13:07 2006.173.20:13:07.01:data_valid=off 2006.173.20:13:07.01:"et 2006.173.20:13:07.02:!+3s 2006.173.20:13:10.03:"tape 2006.173.20:13:10.03:postob 2006.173.20:13:10.17/cable/+6.5145E-03 2006.173.20:13:10.17/wx/19.57,1002.7,100 2006.173.20:13:10.23/fmout-gps/S +3.88E-07 2006.173.20:13:10.23:scan_name=173-2016,jd0606,170 2006.173.20:13:10.24:source=3c446,222547.26,-045701.4,2000.0,ccw 2006.173.20:13:11.14#flagr#flagr/antenna,new-source 2006.173.20:13:11.14:checkk5 2006.173.20:13:11.54/chk_autoobs//k5ts1/ autoobs is running! 2006.173.20:13:11.93/chk_autoobs//k5ts2/ autoobs is running! 2006.173.20:13:12.34/chk_autoobs//k5ts3/ autoobs is running! 2006.173.20:13:12.73/chk_autoobs//k5ts4/ autoobs is running! 2006.173.20:13:13.11/chk_obsdata//k5ts1/T1732009??a.dat file size is correct (nominal:840MB, actual:836MB). 2006.173.20:13:13.51/chk_obsdata//k5ts2/T1732009??b.dat file size is correct (nominal:840MB, actual:836MB). 2006.173.20:13:13.90/chk_obsdata//k5ts3/T1732009??c.dat file size is correct (nominal:840MB, actual:836MB). 2006.173.20:13:14.30/chk_obsdata//k5ts4/T1732009??d.dat file size is correct (nominal:840MB, actual:836MB). 2006.173.20:13:15.03/k5log//k5ts1_log_newline 2006.173.20:13:15.75/k5log//k5ts2_log_newline 2006.173.20:13:16.48/k5log//k5ts3_log_newline 2006.173.20:13:17.18/k5log//k5ts4_log_newline 2006.173.20:13:17.21/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.20:13:17.21:setupk4=1 2006.173.20:13:17.21$setupk4/echo=on 2006.173.20:13:17.21$setupk4/pcalon 2006.173.20:13:17.21$pcalon/"no phase cal control is implemented here 2006.173.20:13:17.21$setupk4/"tpicd=stop 2006.173.20:13:17.21$setupk4/"rec=synch_on 2006.173.20:13:17.21$setupk4/"rec_mode=128 2006.173.20:13:17.21$setupk4/!* 2006.173.20:13:17.21$setupk4/recpk4 2006.173.20:13:17.21$recpk4/recpatch= 2006.173.20:13:17.22$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.20:13:17.22$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.20:13:17.22$setupk4/vck44 2006.173.20:13:17.22$vck44/valo=1,524.99 2006.173.20:13:17.22#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.20:13:17.22#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.20:13:17.22#ibcon#ireg 17 cls_cnt 0 2006.173.20:13:17.22#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.20:13:17.22#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.20:13:17.22#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.20:13:17.22#ibcon#enter wrdev, iclass 17, count 0 2006.173.20:13:17.22#ibcon#first serial, iclass 17, count 0 2006.173.20:13:17.22#ibcon#enter sib2, iclass 17, count 0 2006.173.20:13:17.22#ibcon#flushed, iclass 17, count 0 2006.173.20:13:17.22#ibcon#about to write, iclass 17, count 0 2006.173.20:13:17.22#ibcon#wrote, iclass 17, count 0 2006.173.20:13:17.22#ibcon#about to read 3, iclass 17, count 0 2006.173.20:13:17.24#ibcon#read 3, iclass 17, count 0 2006.173.20:13:17.24#ibcon#about to read 4, iclass 17, count 0 2006.173.20:13:17.24#ibcon#read 4, iclass 17, count 0 2006.173.20:13:17.24#ibcon#about to read 5, iclass 17, count 0 2006.173.20:13:17.24#ibcon#read 5, iclass 17, count 0 2006.173.20:13:17.24#ibcon#about to read 6, iclass 17, count 0 2006.173.20:13:17.24#ibcon#read 6, iclass 17, count 0 2006.173.20:13:17.24#ibcon#end of sib2, iclass 17, count 0 2006.173.20:13:17.24#ibcon#*mode == 0, iclass 17, count 0 2006.173.20:13:17.24#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.20:13:17.24#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.20:13:17.24#ibcon#*before write, iclass 17, count 0 2006.173.20:13:17.24#ibcon#enter sib2, iclass 17, count 0 2006.173.20:13:17.24#ibcon#flushed, iclass 17, count 0 2006.173.20:13:17.24#ibcon#about to write, iclass 17, count 0 2006.173.20:13:17.24#ibcon#wrote, iclass 17, count 0 2006.173.20:13:17.24#ibcon#about to read 3, iclass 17, count 0 2006.173.20:13:17.29#ibcon#read 3, iclass 17, count 0 2006.173.20:13:17.29#ibcon#about to read 4, iclass 17, count 0 2006.173.20:13:17.29#ibcon#read 4, iclass 17, count 0 2006.173.20:13:17.29#ibcon#about to read 5, iclass 17, count 0 2006.173.20:13:17.29#ibcon#read 5, iclass 17, count 0 2006.173.20:13:17.29#ibcon#about to read 6, iclass 17, count 0 2006.173.20:13:17.29#ibcon#read 6, iclass 17, count 0 2006.173.20:13:17.29#ibcon#end of sib2, iclass 17, count 0 2006.173.20:13:17.29#ibcon#*after write, iclass 17, count 0 2006.173.20:13:17.29#ibcon#*before return 0, iclass 17, count 0 2006.173.20:13:17.29#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.20:13:17.29#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.20:13:17.29#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.20:13:17.29#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.20:13:17.29$vck44/va=1,7 2006.173.20:13:17.29#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.20:13:17.29#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.20:13:17.29#ibcon#ireg 11 cls_cnt 2 2006.173.20:13:17.29#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.20:13:17.29#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.20:13:17.29#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.20:13:17.29#ibcon#enter wrdev, iclass 19, count 2 2006.173.20:13:17.29#ibcon#first serial, iclass 19, count 2 2006.173.20:13:17.29#ibcon#enter sib2, iclass 19, count 2 2006.173.20:13:17.29#ibcon#flushed, iclass 19, count 2 2006.173.20:13:17.29#ibcon#about to write, iclass 19, count 2 2006.173.20:13:17.29#ibcon#wrote, iclass 19, count 2 2006.173.20:13:17.29#ibcon#about to read 3, iclass 19, count 2 2006.173.20:13:17.31#ibcon#read 3, iclass 19, count 2 2006.173.20:13:17.31#ibcon#about to read 4, iclass 19, count 2 2006.173.20:13:17.31#ibcon#read 4, iclass 19, count 2 2006.173.20:13:17.31#ibcon#about to read 5, iclass 19, count 2 2006.173.20:13:17.31#ibcon#read 5, iclass 19, count 2 2006.173.20:13:17.31#ibcon#about to read 6, iclass 19, count 2 2006.173.20:13:17.31#ibcon#read 6, iclass 19, count 2 2006.173.20:13:17.31#ibcon#end of sib2, iclass 19, count 2 2006.173.20:13:17.31#ibcon#*mode == 0, iclass 19, count 2 2006.173.20:13:17.31#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.20:13:17.31#ibcon#[25=AT01-07\r\n] 2006.173.20:13:17.31#ibcon#*before write, iclass 19, count 2 2006.173.20:13:17.31#ibcon#enter sib2, iclass 19, count 2 2006.173.20:13:17.31#ibcon#flushed, iclass 19, count 2 2006.173.20:13:17.31#ibcon#about to write, iclass 19, count 2 2006.173.20:13:17.31#ibcon#wrote, iclass 19, count 2 2006.173.20:13:17.31#ibcon#about to read 3, iclass 19, count 2 2006.173.20:13:17.34#ibcon#read 3, iclass 19, count 2 2006.173.20:13:17.34#ibcon#about to read 4, iclass 19, count 2 2006.173.20:13:17.34#ibcon#read 4, iclass 19, count 2 2006.173.20:13:17.34#ibcon#about to read 5, iclass 19, count 2 2006.173.20:13:17.34#ibcon#read 5, iclass 19, count 2 2006.173.20:13:17.34#ibcon#about to read 6, iclass 19, count 2 2006.173.20:13:17.34#ibcon#read 6, iclass 19, count 2 2006.173.20:13:17.34#ibcon#end of sib2, iclass 19, count 2 2006.173.20:13:17.34#ibcon#*after write, iclass 19, count 2 2006.173.20:13:17.34#ibcon#*before return 0, iclass 19, count 2 2006.173.20:13:17.34#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.20:13:17.34#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.20:13:17.34#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.20:13:17.34#ibcon#ireg 7 cls_cnt 0 2006.173.20:13:17.34#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.20:13:17.46#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.20:13:17.46#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.20:13:17.46#ibcon#enter wrdev, iclass 19, count 0 2006.173.20:13:17.46#ibcon#first serial, iclass 19, count 0 2006.173.20:13:17.46#ibcon#enter sib2, iclass 19, count 0 2006.173.20:13:17.46#ibcon#flushed, iclass 19, count 0 2006.173.20:13:17.46#ibcon#about to write, iclass 19, count 0 2006.173.20:13:17.46#ibcon#wrote, iclass 19, count 0 2006.173.20:13:17.46#ibcon#about to read 3, iclass 19, count 0 2006.173.20:13:17.48#ibcon#read 3, iclass 19, count 0 2006.173.20:13:17.48#ibcon#about to read 4, iclass 19, count 0 2006.173.20:13:17.48#ibcon#read 4, iclass 19, count 0 2006.173.20:13:17.48#ibcon#about to read 5, iclass 19, count 0 2006.173.20:13:17.48#ibcon#read 5, iclass 19, count 0 2006.173.20:13:17.48#ibcon#about to read 6, iclass 19, count 0 2006.173.20:13:17.48#ibcon#read 6, iclass 19, count 0 2006.173.20:13:17.48#ibcon#end of sib2, iclass 19, count 0 2006.173.20:13:17.48#ibcon#*mode == 0, iclass 19, count 0 2006.173.20:13:17.48#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.20:13:17.48#ibcon#[25=USB\r\n] 2006.173.20:13:17.48#ibcon#*before write, iclass 19, count 0 2006.173.20:13:17.48#ibcon#enter sib2, iclass 19, count 0 2006.173.20:13:17.48#ibcon#flushed, iclass 19, count 0 2006.173.20:13:17.48#ibcon#about to write, iclass 19, count 0 2006.173.20:13:17.48#ibcon#wrote, iclass 19, count 0 2006.173.20:13:17.48#ibcon#about to read 3, iclass 19, count 0 2006.173.20:13:17.51#ibcon#read 3, iclass 19, count 0 2006.173.20:13:17.51#ibcon#about to read 4, iclass 19, count 0 2006.173.20:13:17.51#ibcon#read 4, iclass 19, count 0 2006.173.20:13:17.51#ibcon#about to read 5, iclass 19, count 0 2006.173.20:13:17.51#ibcon#read 5, iclass 19, count 0 2006.173.20:13:17.51#ibcon#about to read 6, iclass 19, count 0 2006.173.20:13:17.51#ibcon#read 6, iclass 19, count 0 2006.173.20:13:17.51#ibcon#end of sib2, iclass 19, count 0 2006.173.20:13:17.51#ibcon#*after write, iclass 19, count 0 2006.173.20:13:17.51#ibcon#*before return 0, iclass 19, count 0 2006.173.20:13:17.51#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.20:13:17.51#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.20:13:17.51#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.20:13:17.51#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.20:13:17.51$vck44/valo=2,534.99 2006.173.20:13:17.51#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.20:13:17.51#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.20:13:17.51#ibcon#ireg 17 cls_cnt 0 2006.173.20:13:17.51#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.20:13:17.51#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.20:13:17.51#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.20:13:17.51#ibcon#enter wrdev, iclass 21, count 0 2006.173.20:13:17.51#ibcon#first serial, iclass 21, count 0 2006.173.20:13:17.51#ibcon#enter sib2, iclass 21, count 0 2006.173.20:13:17.51#ibcon#flushed, iclass 21, count 0 2006.173.20:13:17.51#ibcon#about to write, iclass 21, count 0 2006.173.20:13:17.51#ibcon#wrote, iclass 21, count 0 2006.173.20:13:17.51#ibcon#about to read 3, iclass 21, count 0 2006.173.20:13:17.53#ibcon#read 3, iclass 21, count 0 2006.173.20:13:17.53#ibcon#about to read 4, iclass 21, count 0 2006.173.20:13:17.53#ibcon#read 4, iclass 21, count 0 2006.173.20:13:17.53#ibcon#about to read 5, iclass 21, count 0 2006.173.20:13:17.53#ibcon#read 5, iclass 21, count 0 2006.173.20:13:17.53#ibcon#about to read 6, iclass 21, count 0 2006.173.20:13:17.53#ibcon#read 6, iclass 21, count 0 2006.173.20:13:17.53#ibcon#end of sib2, iclass 21, count 0 2006.173.20:13:17.53#ibcon#*mode == 0, iclass 21, count 0 2006.173.20:13:17.53#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.20:13:17.53#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.20:13:17.53#ibcon#*before write, iclass 21, count 0 2006.173.20:13:17.53#ibcon#enter sib2, iclass 21, count 0 2006.173.20:13:17.53#ibcon#flushed, iclass 21, count 0 2006.173.20:13:17.53#ibcon#about to write, iclass 21, count 0 2006.173.20:13:17.53#ibcon#wrote, iclass 21, count 0 2006.173.20:13:17.53#ibcon#about to read 3, iclass 21, count 0 2006.173.20:13:17.57#ibcon#read 3, iclass 21, count 0 2006.173.20:13:17.57#ibcon#about to read 4, iclass 21, count 0 2006.173.20:13:17.57#ibcon#read 4, iclass 21, count 0 2006.173.20:13:17.57#ibcon#about to read 5, iclass 21, count 0 2006.173.20:13:17.57#ibcon#read 5, iclass 21, count 0 2006.173.20:13:17.57#ibcon#about to read 6, iclass 21, count 0 2006.173.20:13:17.57#ibcon#read 6, iclass 21, count 0 2006.173.20:13:17.57#ibcon#end of sib2, iclass 21, count 0 2006.173.20:13:17.57#ibcon#*after write, iclass 21, count 0 2006.173.20:13:17.57#ibcon#*before return 0, iclass 21, count 0 2006.173.20:13:17.57#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.20:13:17.57#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.20:13:17.57#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.20:13:17.57#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.20:13:17.57$vck44/va=2,6 2006.173.20:13:17.57#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.20:13:17.57#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.20:13:17.57#ibcon#ireg 11 cls_cnt 2 2006.173.20:13:17.57#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.20:13:17.63#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.20:13:17.63#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.20:13:17.63#ibcon#enter wrdev, iclass 23, count 2 2006.173.20:13:17.63#ibcon#first serial, iclass 23, count 2 2006.173.20:13:17.63#ibcon#enter sib2, iclass 23, count 2 2006.173.20:13:17.63#ibcon#flushed, iclass 23, count 2 2006.173.20:13:17.63#ibcon#about to write, iclass 23, count 2 2006.173.20:13:17.63#ibcon#wrote, iclass 23, count 2 2006.173.20:13:17.63#ibcon#about to read 3, iclass 23, count 2 2006.173.20:13:17.65#ibcon#read 3, iclass 23, count 2 2006.173.20:13:17.65#ibcon#about to read 4, iclass 23, count 2 2006.173.20:13:17.65#ibcon#read 4, iclass 23, count 2 2006.173.20:13:17.65#ibcon#about to read 5, iclass 23, count 2 2006.173.20:13:17.65#ibcon#read 5, iclass 23, count 2 2006.173.20:13:17.65#ibcon#about to read 6, iclass 23, count 2 2006.173.20:13:17.65#ibcon#read 6, iclass 23, count 2 2006.173.20:13:17.65#ibcon#end of sib2, iclass 23, count 2 2006.173.20:13:17.65#ibcon#*mode == 0, iclass 23, count 2 2006.173.20:13:17.65#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.20:13:17.65#ibcon#[25=AT02-06\r\n] 2006.173.20:13:17.65#ibcon#*before write, iclass 23, count 2 2006.173.20:13:17.65#ibcon#enter sib2, iclass 23, count 2 2006.173.20:13:17.65#ibcon#flushed, iclass 23, count 2 2006.173.20:13:17.65#ibcon#about to write, iclass 23, count 2 2006.173.20:13:17.65#ibcon#wrote, iclass 23, count 2 2006.173.20:13:17.65#ibcon#about to read 3, iclass 23, count 2 2006.173.20:13:17.68#ibcon#read 3, iclass 23, count 2 2006.173.20:13:17.68#ibcon#about to read 4, iclass 23, count 2 2006.173.20:13:17.68#ibcon#read 4, iclass 23, count 2 2006.173.20:13:17.68#ibcon#about to read 5, iclass 23, count 2 2006.173.20:13:17.68#ibcon#read 5, iclass 23, count 2 2006.173.20:13:17.68#ibcon#about to read 6, iclass 23, count 2 2006.173.20:13:17.68#ibcon#read 6, iclass 23, count 2 2006.173.20:13:17.68#ibcon#end of sib2, iclass 23, count 2 2006.173.20:13:17.68#ibcon#*after write, iclass 23, count 2 2006.173.20:13:17.68#ibcon#*before return 0, iclass 23, count 2 2006.173.20:13:17.68#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.20:13:17.68#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.20:13:17.68#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.20:13:17.68#ibcon#ireg 7 cls_cnt 0 2006.173.20:13:17.68#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.20:13:17.80#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.20:13:17.80#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.20:13:17.80#ibcon#enter wrdev, iclass 23, count 0 2006.173.20:13:17.80#ibcon#first serial, iclass 23, count 0 2006.173.20:13:17.80#ibcon#enter sib2, iclass 23, count 0 2006.173.20:13:17.80#ibcon#flushed, iclass 23, count 0 2006.173.20:13:17.80#ibcon#about to write, iclass 23, count 0 2006.173.20:13:17.80#ibcon#wrote, iclass 23, count 0 2006.173.20:13:17.80#ibcon#about to read 3, iclass 23, count 0 2006.173.20:13:17.82#ibcon#read 3, iclass 23, count 0 2006.173.20:13:17.82#ibcon#about to read 4, iclass 23, count 0 2006.173.20:13:17.82#ibcon#read 4, iclass 23, count 0 2006.173.20:13:17.82#ibcon#about to read 5, iclass 23, count 0 2006.173.20:13:17.82#ibcon#read 5, iclass 23, count 0 2006.173.20:13:17.82#ibcon#about to read 6, iclass 23, count 0 2006.173.20:13:17.82#ibcon#read 6, iclass 23, count 0 2006.173.20:13:17.82#ibcon#end of sib2, iclass 23, count 0 2006.173.20:13:17.82#ibcon#*mode == 0, iclass 23, count 0 2006.173.20:13:17.82#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.20:13:17.82#ibcon#[25=USB\r\n] 2006.173.20:13:17.82#ibcon#*before write, iclass 23, count 0 2006.173.20:13:17.82#ibcon#enter sib2, iclass 23, count 0 2006.173.20:13:17.82#ibcon#flushed, iclass 23, count 0 2006.173.20:13:17.82#ibcon#about to write, iclass 23, count 0 2006.173.20:13:17.82#ibcon#wrote, iclass 23, count 0 2006.173.20:13:17.82#ibcon#about to read 3, iclass 23, count 0 2006.173.20:13:17.85#ibcon#read 3, iclass 23, count 0 2006.173.20:13:17.85#ibcon#about to read 4, iclass 23, count 0 2006.173.20:13:17.85#ibcon#read 4, iclass 23, count 0 2006.173.20:13:17.85#ibcon#about to read 5, iclass 23, count 0 2006.173.20:13:17.85#ibcon#read 5, iclass 23, count 0 2006.173.20:13:17.85#ibcon#about to read 6, iclass 23, count 0 2006.173.20:13:17.85#ibcon#read 6, iclass 23, count 0 2006.173.20:13:17.85#ibcon#end of sib2, iclass 23, count 0 2006.173.20:13:17.85#ibcon#*after write, iclass 23, count 0 2006.173.20:13:17.85#ibcon#*before return 0, iclass 23, count 0 2006.173.20:13:17.85#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.20:13:17.85#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.20:13:17.85#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.20:13:17.85#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.20:13:17.85$vck44/valo=3,564.99 2006.173.20:13:17.85#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.20:13:17.85#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.20:13:17.85#ibcon#ireg 17 cls_cnt 0 2006.173.20:13:17.85#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.20:13:17.85#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.20:13:17.85#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.20:13:17.85#ibcon#enter wrdev, iclass 25, count 0 2006.173.20:13:17.85#ibcon#first serial, iclass 25, count 0 2006.173.20:13:17.85#ibcon#enter sib2, iclass 25, count 0 2006.173.20:13:17.85#ibcon#flushed, iclass 25, count 0 2006.173.20:13:17.85#ibcon#about to write, iclass 25, count 0 2006.173.20:13:17.85#ibcon#wrote, iclass 25, count 0 2006.173.20:13:17.85#ibcon#about to read 3, iclass 25, count 0 2006.173.20:13:17.87#ibcon#read 3, iclass 25, count 0 2006.173.20:13:17.87#ibcon#about to read 4, iclass 25, count 0 2006.173.20:13:17.87#ibcon#read 4, iclass 25, count 0 2006.173.20:13:17.87#ibcon#about to read 5, iclass 25, count 0 2006.173.20:13:17.87#ibcon#read 5, iclass 25, count 0 2006.173.20:13:17.87#ibcon#about to read 6, iclass 25, count 0 2006.173.20:13:17.87#ibcon#read 6, iclass 25, count 0 2006.173.20:13:17.87#ibcon#end of sib2, iclass 25, count 0 2006.173.20:13:17.87#ibcon#*mode == 0, iclass 25, count 0 2006.173.20:13:17.87#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.20:13:17.87#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.20:13:17.87#ibcon#*before write, iclass 25, count 0 2006.173.20:13:17.87#ibcon#enter sib2, iclass 25, count 0 2006.173.20:13:17.87#ibcon#flushed, iclass 25, count 0 2006.173.20:13:17.87#ibcon#about to write, iclass 25, count 0 2006.173.20:13:17.87#ibcon#wrote, iclass 25, count 0 2006.173.20:13:17.87#ibcon#about to read 3, iclass 25, count 0 2006.173.20:13:17.91#ibcon#read 3, iclass 25, count 0 2006.173.20:13:17.91#ibcon#about to read 4, iclass 25, count 0 2006.173.20:13:17.91#ibcon#read 4, iclass 25, count 0 2006.173.20:13:17.91#ibcon#about to read 5, iclass 25, count 0 2006.173.20:13:17.91#ibcon#read 5, iclass 25, count 0 2006.173.20:13:17.91#ibcon#about to read 6, iclass 25, count 0 2006.173.20:13:17.91#ibcon#read 6, iclass 25, count 0 2006.173.20:13:17.91#ibcon#end of sib2, iclass 25, count 0 2006.173.20:13:17.91#ibcon#*after write, iclass 25, count 0 2006.173.20:13:17.91#ibcon#*before return 0, iclass 25, count 0 2006.173.20:13:17.91#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.20:13:17.91#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.20:13:17.91#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.20:13:17.91#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.20:13:17.91$vck44/va=3,5 2006.173.20:13:17.91#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.20:13:17.91#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.20:13:17.91#ibcon#ireg 11 cls_cnt 2 2006.173.20:13:17.91#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.20:13:17.97#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.20:13:17.97#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.20:13:17.97#ibcon#enter wrdev, iclass 27, count 2 2006.173.20:13:17.97#ibcon#first serial, iclass 27, count 2 2006.173.20:13:17.97#ibcon#enter sib2, iclass 27, count 2 2006.173.20:13:17.97#ibcon#flushed, iclass 27, count 2 2006.173.20:13:17.97#ibcon#about to write, iclass 27, count 2 2006.173.20:13:17.97#ibcon#wrote, iclass 27, count 2 2006.173.20:13:17.97#ibcon#about to read 3, iclass 27, count 2 2006.173.20:13:17.99#ibcon#read 3, iclass 27, count 2 2006.173.20:13:17.99#ibcon#about to read 4, iclass 27, count 2 2006.173.20:13:17.99#ibcon#read 4, iclass 27, count 2 2006.173.20:13:17.99#ibcon#about to read 5, iclass 27, count 2 2006.173.20:13:17.99#ibcon#read 5, iclass 27, count 2 2006.173.20:13:17.99#ibcon#about to read 6, iclass 27, count 2 2006.173.20:13:17.99#ibcon#read 6, iclass 27, count 2 2006.173.20:13:17.99#ibcon#end of sib2, iclass 27, count 2 2006.173.20:13:17.99#ibcon#*mode == 0, iclass 27, count 2 2006.173.20:13:17.99#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.20:13:17.99#ibcon#[25=AT03-05\r\n] 2006.173.20:13:17.99#ibcon#*before write, iclass 27, count 2 2006.173.20:13:17.99#ibcon#enter sib2, iclass 27, count 2 2006.173.20:13:17.99#ibcon#flushed, iclass 27, count 2 2006.173.20:13:17.99#ibcon#about to write, iclass 27, count 2 2006.173.20:13:17.99#ibcon#wrote, iclass 27, count 2 2006.173.20:13:17.99#ibcon#about to read 3, iclass 27, count 2 2006.173.20:13:18.02#ibcon#read 3, iclass 27, count 2 2006.173.20:13:18.02#ibcon#about to read 4, iclass 27, count 2 2006.173.20:13:18.02#ibcon#read 4, iclass 27, count 2 2006.173.20:13:18.02#ibcon#about to read 5, iclass 27, count 2 2006.173.20:13:18.02#ibcon#read 5, iclass 27, count 2 2006.173.20:13:18.02#ibcon#about to read 6, iclass 27, count 2 2006.173.20:13:18.02#ibcon#read 6, iclass 27, count 2 2006.173.20:13:18.02#ibcon#end of sib2, iclass 27, count 2 2006.173.20:13:18.02#ibcon#*after write, iclass 27, count 2 2006.173.20:13:18.02#ibcon#*before return 0, iclass 27, count 2 2006.173.20:13:18.02#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.20:13:18.02#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.20:13:18.02#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.20:13:18.02#ibcon#ireg 7 cls_cnt 0 2006.173.20:13:18.02#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.20:13:18.14#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.20:13:18.14#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.20:13:18.14#ibcon#enter wrdev, iclass 27, count 0 2006.173.20:13:18.14#ibcon#first serial, iclass 27, count 0 2006.173.20:13:18.14#ibcon#enter sib2, iclass 27, count 0 2006.173.20:13:18.14#ibcon#flushed, iclass 27, count 0 2006.173.20:13:18.14#ibcon#about to write, iclass 27, count 0 2006.173.20:13:18.14#ibcon#wrote, iclass 27, count 0 2006.173.20:13:18.14#ibcon#about to read 3, iclass 27, count 0 2006.173.20:13:18.16#ibcon#read 3, iclass 27, count 0 2006.173.20:13:18.16#ibcon#about to read 4, iclass 27, count 0 2006.173.20:13:18.16#ibcon#read 4, iclass 27, count 0 2006.173.20:13:18.16#ibcon#about to read 5, iclass 27, count 0 2006.173.20:13:18.16#ibcon#read 5, iclass 27, count 0 2006.173.20:13:18.16#ibcon#about to read 6, iclass 27, count 0 2006.173.20:13:18.16#ibcon#read 6, iclass 27, count 0 2006.173.20:13:18.16#ibcon#end of sib2, iclass 27, count 0 2006.173.20:13:18.16#ibcon#*mode == 0, iclass 27, count 0 2006.173.20:13:18.16#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.20:13:18.16#ibcon#[25=USB\r\n] 2006.173.20:13:18.16#ibcon#*before write, iclass 27, count 0 2006.173.20:13:18.16#ibcon#enter sib2, iclass 27, count 0 2006.173.20:13:18.16#ibcon#flushed, iclass 27, count 0 2006.173.20:13:18.16#ibcon#about to write, iclass 27, count 0 2006.173.20:13:18.16#ibcon#wrote, iclass 27, count 0 2006.173.20:13:18.16#ibcon#about to read 3, iclass 27, count 0 2006.173.20:13:18.19#ibcon#read 3, iclass 27, count 0 2006.173.20:13:18.19#ibcon#about to read 4, iclass 27, count 0 2006.173.20:13:18.19#ibcon#read 4, iclass 27, count 0 2006.173.20:13:18.19#ibcon#about to read 5, iclass 27, count 0 2006.173.20:13:18.19#ibcon#read 5, iclass 27, count 0 2006.173.20:13:18.19#ibcon#about to read 6, iclass 27, count 0 2006.173.20:13:18.19#ibcon#read 6, iclass 27, count 0 2006.173.20:13:18.19#ibcon#end of sib2, iclass 27, count 0 2006.173.20:13:18.19#ibcon#*after write, iclass 27, count 0 2006.173.20:13:18.19#ibcon#*before return 0, iclass 27, count 0 2006.173.20:13:18.19#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.20:13:18.19#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.20:13:18.19#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.20:13:18.19#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.20:13:18.19$vck44/valo=4,624.99 2006.173.20:13:18.19#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.20:13:18.19#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.20:13:18.19#ibcon#ireg 17 cls_cnt 0 2006.173.20:13:18.19#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.20:13:18.19#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.20:13:18.19#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.20:13:18.19#ibcon#enter wrdev, iclass 29, count 0 2006.173.20:13:18.19#ibcon#first serial, iclass 29, count 0 2006.173.20:13:18.19#ibcon#enter sib2, iclass 29, count 0 2006.173.20:13:18.19#ibcon#flushed, iclass 29, count 0 2006.173.20:13:18.19#ibcon#about to write, iclass 29, count 0 2006.173.20:13:18.19#ibcon#wrote, iclass 29, count 0 2006.173.20:13:18.19#ibcon#about to read 3, iclass 29, count 0 2006.173.20:13:18.21#ibcon#read 3, iclass 29, count 0 2006.173.20:13:18.21#ibcon#about to read 4, iclass 29, count 0 2006.173.20:13:18.21#ibcon#read 4, iclass 29, count 0 2006.173.20:13:18.21#ibcon#about to read 5, iclass 29, count 0 2006.173.20:13:18.21#ibcon#read 5, iclass 29, count 0 2006.173.20:13:18.21#ibcon#about to read 6, iclass 29, count 0 2006.173.20:13:18.21#ibcon#read 6, iclass 29, count 0 2006.173.20:13:18.21#ibcon#end of sib2, iclass 29, count 0 2006.173.20:13:18.21#ibcon#*mode == 0, iclass 29, count 0 2006.173.20:13:18.21#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.20:13:18.21#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.20:13:18.21#ibcon#*before write, iclass 29, count 0 2006.173.20:13:18.21#ibcon#enter sib2, iclass 29, count 0 2006.173.20:13:18.21#ibcon#flushed, iclass 29, count 0 2006.173.20:13:18.21#ibcon#about to write, iclass 29, count 0 2006.173.20:13:18.21#ibcon#wrote, iclass 29, count 0 2006.173.20:13:18.21#ibcon#about to read 3, iclass 29, count 0 2006.173.20:13:18.25#ibcon#read 3, iclass 29, count 0 2006.173.20:13:18.25#ibcon#about to read 4, iclass 29, count 0 2006.173.20:13:18.25#ibcon#read 4, iclass 29, count 0 2006.173.20:13:18.25#ibcon#about to read 5, iclass 29, count 0 2006.173.20:13:18.25#ibcon#read 5, iclass 29, count 0 2006.173.20:13:18.25#ibcon#about to read 6, iclass 29, count 0 2006.173.20:13:18.25#ibcon#read 6, iclass 29, count 0 2006.173.20:13:18.25#ibcon#end of sib2, iclass 29, count 0 2006.173.20:13:18.25#ibcon#*after write, iclass 29, count 0 2006.173.20:13:18.25#ibcon#*before return 0, iclass 29, count 0 2006.173.20:13:18.25#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.20:13:18.25#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.20:13:18.25#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.20:13:18.25#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.20:13:18.25$vck44/va=4,6 2006.173.20:13:18.25#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.20:13:18.25#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.20:13:18.25#ibcon#ireg 11 cls_cnt 2 2006.173.20:13:18.25#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.20:13:18.31#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.20:13:18.31#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.20:13:18.31#ibcon#enter wrdev, iclass 31, count 2 2006.173.20:13:18.31#ibcon#first serial, iclass 31, count 2 2006.173.20:13:18.31#ibcon#enter sib2, iclass 31, count 2 2006.173.20:13:18.31#ibcon#flushed, iclass 31, count 2 2006.173.20:13:18.31#ibcon#about to write, iclass 31, count 2 2006.173.20:13:18.31#ibcon#wrote, iclass 31, count 2 2006.173.20:13:18.31#ibcon#about to read 3, iclass 31, count 2 2006.173.20:13:18.33#ibcon#read 3, iclass 31, count 2 2006.173.20:13:18.33#ibcon#about to read 4, iclass 31, count 2 2006.173.20:13:18.33#ibcon#read 4, iclass 31, count 2 2006.173.20:13:18.33#ibcon#about to read 5, iclass 31, count 2 2006.173.20:13:18.33#ibcon#read 5, iclass 31, count 2 2006.173.20:13:18.33#ibcon#about to read 6, iclass 31, count 2 2006.173.20:13:18.33#ibcon#read 6, iclass 31, count 2 2006.173.20:13:18.33#ibcon#end of sib2, iclass 31, count 2 2006.173.20:13:18.33#ibcon#*mode == 0, iclass 31, count 2 2006.173.20:13:18.33#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.20:13:18.33#ibcon#[25=AT04-06\r\n] 2006.173.20:13:18.33#ibcon#*before write, iclass 31, count 2 2006.173.20:13:18.33#ibcon#enter sib2, iclass 31, count 2 2006.173.20:13:18.33#ibcon#flushed, iclass 31, count 2 2006.173.20:13:18.33#ibcon#about to write, iclass 31, count 2 2006.173.20:13:18.33#ibcon#wrote, iclass 31, count 2 2006.173.20:13:18.33#ibcon#about to read 3, iclass 31, count 2 2006.173.20:13:18.36#ibcon#read 3, iclass 31, count 2 2006.173.20:13:18.36#ibcon#about to read 4, iclass 31, count 2 2006.173.20:13:18.36#ibcon#read 4, iclass 31, count 2 2006.173.20:13:18.36#ibcon#about to read 5, iclass 31, count 2 2006.173.20:13:18.36#ibcon#read 5, iclass 31, count 2 2006.173.20:13:18.36#ibcon#about to read 6, iclass 31, count 2 2006.173.20:13:18.36#ibcon#read 6, iclass 31, count 2 2006.173.20:13:18.36#ibcon#end of sib2, iclass 31, count 2 2006.173.20:13:18.36#ibcon#*after write, iclass 31, count 2 2006.173.20:13:18.36#ibcon#*before return 0, iclass 31, count 2 2006.173.20:13:18.36#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.20:13:18.36#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.20:13:18.36#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.20:13:18.36#ibcon#ireg 7 cls_cnt 0 2006.173.20:13:18.36#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.20:13:18.48#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.20:13:18.48#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.20:13:18.48#ibcon#enter wrdev, iclass 31, count 0 2006.173.20:13:18.48#ibcon#first serial, iclass 31, count 0 2006.173.20:13:18.48#ibcon#enter sib2, iclass 31, count 0 2006.173.20:13:18.48#ibcon#flushed, iclass 31, count 0 2006.173.20:13:18.48#ibcon#about to write, iclass 31, count 0 2006.173.20:13:18.48#ibcon#wrote, iclass 31, count 0 2006.173.20:13:18.48#ibcon#about to read 3, iclass 31, count 0 2006.173.20:13:18.50#ibcon#read 3, iclass 31, count 0 2006.173.20:13:18.50#ibcon#about to read 4, iclass 31, count 0 2006.173.20:13:18.50#ibcon#read 4, iclass 31, count 0 2006.173.20:13:18.50#ibcon#about to read 5, iclass 31, count 0 2006.173.20:13:18.50#ibcon#read 5, iclass 31, count 0 2006.173.20:13:18.50#ibcon#about to read 6, iclass 31, count 0 2006.173.20:13:18.50#ibcon#read 6, iclass 31, count 0 2006.173.20:13:18.50#ibcon#end of sib2, iclass 31, count 0 2006.173.20:13:18.50#ibcon#*mode == 0, iclass 31, count 0 2006.173.20:13:18.50#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.20:13:18.50#ibcon#[25=USB\r\n] 2006.173.20:13:18.50#ibcon#*before write, iclass 31, count 0 2006.173.20:13:18.50#ibcon#enter sib2, iclass 31, count 0 2006.173.20:13:18.50#ibcon#flushed, iclass 31, count 0 2006.173.20:13:18.50#ibcon#about to write, iclass 31, count 0 2006.173.20:13:18.50#ibcon#wrote, iclass 31, count 0 2006.173.20:13:18.50#ibcon#about to read 3, iclass 31, count 0 2006.173.20:13:18.53#ibcon#read 3, iclass 31, count 0 2006.173.20:13:18.53#ibcon#about to read 4, iclass 31, count 0 2006.173.20:13:18.53#ibcon#read 4, iclass 31, count 0 2006.173.20:13:18.53#ibcon#about to read 5, iclass 31, count 0 2006.173.20:13:18.53#ibcon#read 5, iclass 31, count 0 2006.173.20:13:18.53#ibcon#about to read 6, iclass 31, count 0 2006.173.20:13:18.53#ibcon#read 6, iclass 31, count 0 2006.173.20:13:18.53#ibcon#end of sib2, iclass 31, count 0 2006.173.20:13:18.53#ibcon#*after write, iclass 31, count 0 2006.173.20:13:18.53#ibcon#*before return 0, iclass 31, count 0 2006.173.20:13:18.53#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.20:13:18.53#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.20:13:18.53#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.20:13:18.53#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.20:13:18.53$vck44/valo=5,734.99 2006.173.20:13:18.53#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.20:13:18.53#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.20:13:18.53#ibcon#ireg 17 cls_cnt 0 2006.173.20:13:18.53#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.20:13:18.53#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.20:13:18.53#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.20:13:18.53#ibcon#enter wrdev, iclass 33, count 0 2006.173.20:13:18.53#ibcon#first serial, iclass 33, count 0 2006.173.20:13:18.53#ibcon#enter sib2, iclass 33, count 0 2006.173.20:13:18.53#ibcon#flushed, iclass 33, count 0 2006.173.20:13:18.53#ibcon#about to write, iclass 33, count 0 2006.173.20:13:18.53#ibcon#wrote, iclass 33, count 0 2006.173.20:13:18.53#ibcon#about to read 3, iclass 33, count 0 2006.173.20:13:18.55#ibcon#read 3, iclass 33, count 0 2006.173.20:13:18.55#ibcon#about to read 4, iclass 33, count 0 2006.173.20:13:18.55#ibcon#read 4, iclass 33, count 0 2006.173.20:13:18.55#ibcon#about to read 5, iclass 33, count 0 2006.173.20:13:18.55#ibcon#read 5, iclass 33, count 0 2006.173.20:13:18.55#ibcon#about to read 6, iclass 33, count 0 2006.173.20:13:18.55#ibcon#read 6, iclass 33, count 0 2006.173.20:13:18.55#ibcon#end of sib2, iclass 33, count 0 2006.173.20:13:18.55#ibcon#*mode == 0, iclass 33, count 0 2006.173.20:13:18.55#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.20:13:18.55#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.20:13:18.55#ibcon#*before write, iclass 33, count 0 2006.173.20:13:18.55#ibcon#enter sib2, iclass 33, count 0 2006.173.20:13:18.55#ibcon#flushed, iclass 33, count 0 2006.173.20:13:18.55#ibcon#about to write, iclass 33, count 0 2006.173.20:13:18.55#ibcon#wrote, iclass 33, count 0 2006.173.20:13:18.55#ibcon#about to read 3, iclass 33, count 0 2006.173.20:13:18.59#ibcon#read 3, iclass 33, count 0 2006.173.20:13:18.59#ibcon#about to read 4, iclass 33, count 0 2006.173.20:13:18.59#ibcon#read 4, iclass 33, count 0 2006.173.20:13:18.59#ibcon#about to read 5, iclass 33, count 0 2006.173.20:13:18.59#ibcon#read 5, iclass 33, count 0 2006.173.20:13:18.59#ibcon#about to read 6, iclass 33, count 0 2006.173.20:13:18.59#ibcon#read 6, iclass 33, count 0 2006.173.20:13:18.59#ibcon#end of sib2, iclass 33, count 0 2006.173.20:13:18.59#ibcon#*after write, iclass 33, count 0 2006.173.20:13:18.59#ibcon#*before return 0, iclass 33, count 0 2006.173.20:13:18.59#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.20:13:18.59#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.20:13:18.59#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.20:13:18.59#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.20:13:18.59$vck44/va=5,4 2006.173.20:13:18.59#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.20:13:18.59#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.20:13:18.59#ibcon#ireg 11 cls_cnt 2 2006.173.20:13:18.59#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.20:13:18.65#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.20:13:18.65#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.20:13:18.65#ibcon#enter wrdev, iclass 35, count 2 2006.173.20:13:18.65#ibcon#first serial, iclass 35, count 2 2006.173.20:13:18.65#ibcon#enter sib2, iclass 35, count 2 2006.173.20:13:18.65#ibcon#flushed, iclass 35, count 2 2006.173.20:13:18.65#ibcon#about to write, iclass 35, count 2 2006.173.20:13:18.65#ibcon#wrote, iclass 35, count 2 2006.173.20:13:18.65#ibcon#about to read 3, iclass 35, count 2 2006.173.20:13:18.67#ibcon#read 3, iclass 35, count 2 2006.173.20:13:18.67#ibcon#about to read 4, iclass 35, count 2 2006.173.20:13:18.67#ibcon#read 4, iclass 35, count 2 2006.173.20:13:18.67#ibcon#about to read 5, iclass 35, count 2 2006.173.20:13:18.67#ibcon#read 5, iclass 35, count 2 2006.173.20:13:18.67#ibcon#about to read 6, iclass 35, count 2 2006.173.20:13:18.67#ibcon#read 6, iclass 35, count 2 2006.173.20:13:18.67#ibcon#end of sib2, iclass 35, count 2 2006.173.20:13:18.67#ibcon#*mode == 0, iclass 35, count 2 2006.173.20:13:18.67#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.20:13:18.67#ibcon#[25=AT05-04\r\n] 2006.173.20:13:18.67#ibcon#*before write, iclass 35, count 2 2006.173.20:13:18.67#ibcon#enter sib2, iclass 35, count 2 2006.173.20:13:18.67#ibcon#flushed, iclass 35, count 2 2006.173.20:13:18.67#ibcon#about to write, iclass 35, count 2 2006.173.20:13:18.67#ibcon#wrote, iclass 35, count 2 2006.173.20:13:18.67#ibcon#about to read 3, iclass 35, count 2 2006.173.20:13:18.70#ibcon#read 3, iclass 35, count 2 2006.173.20:13:18.70#ibcon#about to read 4, iclass 35, count 2 2006.173.20:13:18.70#ibcon#read 4, iclass 35, count 2 2006.173.20:13:18.70#ibcon#about to read 5, iclass 35, count 2 2006.173.20:13:18.70#ibcon#read 5, iclass 35, count 2 2006.173.20:13:18.70#ibcon#about to read 6, iclass 35, count 2 2006.173.20:13:18.70#ibcon#read 6, iclass 35, count 2 2006.173.20:13:18.70#ibcon#end of sib2, iclass 35, count 2 2006.173.20:13:18.70#ibcon#*after write, iclass 35, count 2 2006.173.20:13:18.70#ibcon#*before return 0, iclass 35, count 2 2006.173.20:13:18.70#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.20:13:18.70#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.20:13:18.70#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.20:13:18.70#ibcon#ireg 7 cls_cnt 0 2006.173.20:13:18.70#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.20:13:18.82#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.20:13:18.82#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.20:13:18.82#ibcon#enter wrdev, iclass 35, count 0 2006.173.20:13:18.82#ibcon#first serial, iclass 35, count 0 2006.173.20:13:18.82#ibcon#enter sib2, iclass 35, count 0 2006.173.20:13:18.82#ibcon#flushed, iclass 35, count 0 2006.173.20:13:18.82#ibcon#about to write, iclass 35, count 0 2006.173.20:13:18.82#ibcon#wrote, iclass 35, count 0 2006.173.20:13:18.82#ibcon#about to read 3, iclass 35, count 0 2006.173.20:13:18.84#ibcon#read 3, iclass 35, count 0 2006.173.20:13:18.84#ibcon#about to read 4, iclass 35, count 0 2006.173.20:13:18.84#ibcon#read 4, iclass 35, count 0 2006.173.20:13:18.84#ibcon#about to read 5, iclass 35, count 0 2006.173.20:13:18.84#ibcon#read 5, iclass 35, count 0 2006.173.20:13:18.84#ibcon#about to read 6, iclass 35, count 0 2006.173.20:13:18.84#ibcon#read 6, iclass 35, count 0 2006.173.20:13:18.84#ibcon#end of sib2, iclass 35, count 0 2006.173.20:13:18.84#ibcon#*mode == 0, iclass 35, count 0 2006.173.20:13:18.84#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.20:13:18.84#ibcon#[25=USB\r\n] 2006.173.20:13:18.84#ibcon#*before write, iclass 35, count 0 2006.173.20:13:18.84#ibcon#enter sib2, iclass 35, count 0 2006.173.20:13:18.84#ibcon#flushed, iclass 35, count 0 2006.173.20:13:18.84#ibcon#about to write, iclass 35, count 0 2006.173.20:13:18.84#ibcon#wrote, iclass 35, count 0 2006.173.20:13:18.84#ibcon#about to read 3, iclass 35, count 0 2006.173.20:13:18.87#ibcon#read 3, iclass 35, count 0 2006.173.20:13:18.87#ibcon#about to read 4, iclass 35, count 0 2006.173.20:13:18.87#ibcon#read 4, iclass 35, count 0 2006.173.20:13:18.87#ibcon#about to read 5, iclass 35, count 0 2006.173.20:13:18.87#ibcon#read 5, iclass 35, count 0 2006.173.20:13:18.87#ibcon#about to read 6, iclass 35, count 0 2006.173.20:13:18.87#ibcon#read 6, iclass 35, count 0 2006.173.20:13:18.87#ibcon#end of sib2, iclass 35, count 0 2006.173.20:13:18.87#ibcon#*after write, iclass 35, count 0 2006.173.20:13:18.87#ibcon#*before return 0, iclass 35, count 0 2006.173.20:13:18.87#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.20:13:18.87#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.20:13:18.87#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.20:13:18.87#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.20:13:18.87$vck44/valo=6,814.99 2006.173.20:13:18.87#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.20:13:18.87#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.20:13:18.87#ibcon#ireg 17 cls_cnt 0 2006.173.20:13:18.87#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.20:13:18.87#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.20:13:18.87#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.20:13:18.87#ibcon#enter wrdev, iclass 37, count 0 2006.173.20:13:18.87#ibcon#first serial, iclass 37, count 0 2006.173.20:13:18.87#ibcon#enter sib2, iclass 37, count 0 2006.173.20:13:18.87#ibcon#flushed, iclass 37, count 0 2006.173.20:13:18.87#ibcon#about to write, iclass 37, count 0 2006.173.20:13:18.87#ibcon#wrote, iclass 37, count 0 2006.173.20:13:18.87#ibcon#about to read 3, iclass 37, count 0 2006.173.20:13:18.89#ibcon#read 3, iclass 37, count 0 2006.173.20:13:18.89#ibcon#about to read 4, iclass 37, count 0 2006.173.20:13:18.89#ibcon#read 4, iclass 37, count 0 2006.173.20:13:18.89#ibcon#about to read 5, iclass 37, count 0 2006.173.20:13:18.89#ibcon#read 5, iclass 37, count 0 2006.173.20:13:18.89#ibcon#about to read 6, iclass 37, count 0 2006.173.20:13:18.89#ibcon#read 6, iclass 37, count 0 2006.173.20:13:18.89#ibcon#end of sib2, iclass 37, count 0 2006.173.20:13:18.89#ibcon#*mode == 0, iclass 37, count 0 2006.173.20:13:18.89#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.20:13:18.89#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.20:13:18.89#ibcon#*before write, iclass 37, count 0 2006.173.20:13:18.89#ibcon#enter sib2, iclass 37, count 0 2006.173.20:13:18.89#ibcon#flushed, iclass 37, count 0 2006.173.20:13:18.89#ibcon#about to write, iclass 37, count 0 2006.173.20:13:18.89#ibcon#wrote, iclass 37, count 0 2006.173.20:13:18.89#ibcon#about to read 3, iclass 37, count 0 2006.173.20:13:18.93#ibcon#read 3, iclass 37, count 0 2006.173.20:13:18.93#ibcon#about to read 4, iclass 37, count 0 2006.173.20:13:18.93#ibcon#read 4, iclass 37, count 0 2006.173.20:13:18.93#ibcon#about to read 5, iclass 37, count 0 2006.173.20:13:18.93#ibcon#read 5, iclass 37, count 0 2006.173.20:13:18.93#ibcon#about to read 6, iclass 37, count 0 2006.173.20:13:18.93#ibcon#read 6, iclass 37, count 0 2006.173.20:13:18.93#ibcon#end of sib2, iclass 37, count 0 2006.173.20:13:18.93#ibcon#*after write, iclass 37, count 0 2006.173.20:13:18.93#ibcon#*before return 0, iclass 37, count 0 2006.173.20:13:18.93#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.20:13:18.93#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.20:13:18.93#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.20:13:18.93#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.20:13:18.93$vck44/va=6,3 2006.173.20:13:18.93#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.20:13:18.93#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.20:13:18.93#ibcon#ireg 11 cls_cnt 2 2006.173.20:13:18.93#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.20:13:18.99#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.20:13:18.99#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.20:13:18.99#ibcon#enter wrdev, iclass 39, count 2 2006.173.20:13:18.99#ibcon#first serial, iclass 39, count 2 2006.173.20:13:18.99#ibcon#enter sib2, iclass 39, count 2 2006.173.20:13:18.99#ibcon#flushed, iclass 39, count 2 2006.173.20:13:18.99#ibcon#about to write, iclass 39, count 2 2006.173.20:13:18.99#ibcon#wrote, iclass 39, count 2 2006.173.20:13:18.99#ibcon#about to read 3, iclass 39, count 2 2006.173.20:13:19.01#ibcon#read 3, iclass 39, count 2 2006.173.20:13:19.01#ibcon#about to read 4, iclass 39, count 2 2006.173.20:13:19.01#ibcon#read 4, iclass 39, count 2 2006.173.20:13:19.01#ibcon#about to read 5, iclass 39, count 2 2006.173.20:13:19.01#ibcon#read 5, iclass 39, count 2 2006.173.20:13:19.01#ibcon#about to read 6, iclass 39, count 2 2006.173.20:13:19.01#ibcon#read 6, iclass 39, count 2 2006.173.20:13:19.01#ibcon#end of sib2, iclass 39, count 2 2006.173.20:13:19.01#ibcon#*mode == 0, iclass 39, count 2 2006.173.20:13:19.01#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.20:13:19.01#ibcon#[25=AT06-03\r\n] 2006.173.20:13:19.01#ibcon#*before write, iclass 39, count 2 2006.173.20:13:19.01#ibcon#enter sib2, iclass 39, count 2 2006.173.20:13:19.01#ibcon#flushed, iclass 39, count 2 2006.173.20:13:19.01#ibcon#about to write, iclass 39, count 2 2006.173.20:13:19.01#ibcon#wrote, iclass 39, count 2 2006.173.20:13:19.01#ibcon#about to read 3, iclass 39, count 2 2006.173.20:13:19.04#ibcon#read 3, iclass 39, count 2 2006.173.20:13:19.04#ibcon#about to read 4, iclass 39, count 2 2006.173.20:13:19.04#ibcon#read 4, iclass 39, count 2 2006.173.20:13:19.04#ibcon#about to read 5, iclass 39, count 2 2006.173.20:13:19.04#ibcon#read 5, iclass 39, count 2 2006.173.20:13:19.04#ibcon#about to read 6, iclass 39, count 2 2006.173.20:13:19.04#ibcon#read 6, iclass 39, count 2 2006.173.20:13:19.04#ibcon#end of sib2, iclass 39, count 2 2006.173.20:13:19.04#ibcon#*after write, iclass 39, count 2 2006.173.20:13:19.04#ibcon#*before return 0, iclass 39, count 2 2006.173.20:13:19.04#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.20:13:19.04#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.20:13:19.04#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.20:13:19.04#ibcon#ireg 7 cls_cnt 0 2006.173.20:13:19.04#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.20:13:19.16#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.20:13:19.16#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.20:13:19.16#ibcon#enter wrdev, iclass 39, count 0 2006.173.20:13:19.16#ibcon#first serial, iclass 39, count 0 2006.173.20:13:19.16#ibcon#enter sib2, iclass 39, count 0 2006.173.20:13:19.16#ibcon#flushed, iclass 39, count 0 2006.173.20:13:19.16#ibcon#about to write, iclass 39, count 0 2006.173.20:13:19.16#ibcon#wrote, iclass 39, count 0 2006.173.20:13:19.16#ibcon#about to read 3, iclass 39, count 0 2006.173.20:13:19.18#ibcon#read 3, iclass 39, count 0 2006.173.20:13:19.18#ibcon#about to read 4, iclass 39, count 0 2006.173.20:13:19.18#ibcon#read 4, iclass 39, count 0 2006.173.20:13:19.18#ibcon#about to read 5, iclass 39, count 0 2006.173.20:13:19.18#ibcon#read 5, iclass 39, count 0 2006.173.20:13:19.18#ibcon#about to read 6, iclass 39, count 0 2006.173.20:13:19.18#ibcon#read 6, iclass 39, count 0 2006.173.20:13:19.18#ibcon#end of sib2, iclass 39, count 0 2006.173.20:13:19.18#ibcon#*mode == 0, iclass 39, count 0 2006.173.20:13:19.18#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.20:13:19.18#ibcon#[25=USB\r\n] 2006.173.20:13:19.18#ibcon#*before write, iclass 39, count 0 2006.173.20:13:19.18#ibcon#enter sib2, iclass 39, count 0 2006.173.20:13:19.18#ibcon#flushed, iclass 39, count 0 2006.173.20:13:19.18#ibcon#about to write, iclass 39, count 0 2006.173.20:13:19.18#ibcon#wrote, iclass 39, count 0 2006.173.20:13:19.18#ibcon#about to read 3, iclass 39, count 0 2006.173.20:13:19.21#ibcon#read 3, iclass 39, count 0 2006.173.20:13:19.21#ibcon#about to read 4, iclass 39, count 0 2006.173.20:13:19.21#ibcon#read 4, iclass 39, count 0 2006.173.20:13:19.21#ibcon#about to read 5, iclass 39, count 0 2006.173.20:13:19.21#ibcon#read 5, iclass 39, count 0 2006.173.20:13:19.21#ibcon#about to read 6, iclass 39, count 0 2006.173.20:13:19.21#ibcon#read 6, iclass 39, count 0 2006.173.20:13:19.21#ibcon#end of sib2, iclass 39, count 0 2006.173.20:13:19.21#ibcon#*after write, iclass 39, count 0 2006.173.20:13:19.21#ibcon#*before return 0, iclass 39, count 0 2006.173.20:13:19.21#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.20:13:19.21#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.20:13:19.21#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.20:13:19.21#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.20:13:19.21$vck44/valo=7,864.99 2006.173.20:13:19.21#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.20:13:19.21#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.20:13:19.21#ibcon#ireg 17 cls_cnt 0 2006.173.20:13:19.21#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.20:13:19.21#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.20:13:19.21#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.20:13:19.21#ibcon#enter wrdev, iclass 3, count 0 2006.173.20:13:19.21#ibcon#first serial, iclass 3, count 0 2006.173.20:13:19.21#ibcon#enter sib2, iclass 3, count 0 2006.173.20:13:19.21#ibcon#flushed, iclass 3, count 0 2006.173.20:13:19.21#ibcon#about to write, iclass 3, count 0 2006.173.20:13:19.21#ibcon#wrote, iclass 3, count 0 2006.173.20:13:19.21#ibcon#about to read 3, iclass 3, count 0 2006.173.20:13:19.23#ibcon#read 3, iclass 3, count 0 2006.173.20:13:19.23#ibcon#about to read 4, iclass 3, count 0 2006.173.20:13:19.23#ibcon#read 4, iclass 3, count 0 2006.173.20:13:19.23#ibcon#about to read 5, iclass 3, count 0 2006.173.20:13:19.23#ibcon#read 5, iclass 3, count 0 2006.173.20:13:19.23#ibcon#about to read 6, iclass 3, count 0 2006.173.20:13:19.23#ibcon#read 6, iclass 3, count 0 2006.173.20:13:19.23#ibcon#end of sib2, iclass 3, count 0 2006.173.20:13:19.23#ibcon#*mode == 0, iclass 3, count 0 2006.173.20:13:19.23#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.20:13:19.23#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.20:13:19.23#ibcon#*before write, iclass 3, count 0 2006.173.20:13:19.23#ibcon#enter sib2, iclass 3, count 0 2006.173.20:13:19.23#ibcon#flushed, iclass 3, count 0 2006.173.20:13:19.23#ibcon#about to write, iclass 3, count 0 2006.173.20:13:19.23#ibcon#wrote, iclass 3, count 0 2006.173.20:13:19.23#ibcon#about to read 3, iclass 3, count 0 2006.173.20:13:19.27#ibcon#read 3, iclass 3, count 0 2006.173.20:13:19.27#ibcon#about to read 4, iclass 3, count 0 2006.173.20:13:19.27#ibcon#read 4, iclass 3, count 0 2006.173.20:13:19.27#ibcon#about to read 5, iclass 3, count 0 2006.173.20:13:19.27#ibcon#read 5, iclass 3, count 0 2006.173.20:13:19.27#ibcon#about to read 6, iclass 3, count 0 2006.173.20:13:19.27#ibcon#read 6, iclass 3, count 0 2006.173.20:13:19.27#ibcon#end of sib2, iclass 3, count 0 2006.173.20:13:19.27#ibcon#*after write, iclass 3, count 0 2006.173.20:13:19.27#ibcon#*before return 0, iclass 3, count 0 2006.173.20:13:19.27#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.20:13:19.27#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.20:13:19.27#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.20:13:19.27#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.20:13:19.27$vck44/va=7,4 2006.173.20:13:19.27#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.20:13:19.27#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.20:13:19.27#ibcon#ireg 11 cls_cnt 2 2006.173.20:13:19.27#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.20:13:19.33#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.20:13:19.33#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.20:13:19.33#ibcon#enter wrdev, iclass 5, count 2 2006.173.20:13:19.33#ibcon#first serial, iclass 5, count 2 2006.173.20:13:19.33#ibcon#enter sib2, iclass 5, count 2 2006.173.20:13:19.33#ibcon#flushed, iclass 5, count 2 2006.173.20:13:19.33#ibcon#about to write, iclass 5, count 2 2006.173.20:13:19.33#ibcon#wrote, iclass 5, count 2 2006.173.20:13:19.33#ibcon#about to read 3, iclass 5, count 2 2006.173.20:13:19.35#ibcon#read 3, iclass 5, count 2 2006.173.20:13:19.35#ibcon#about to read 4, iclass 5, count 2 2006.173.20:13:19.35#ibcon#read 4, iclass 5, count 2 2006.173.20:13:19.35#ibcon#about to read 5, iclass 5, count 2 2006.173.20:13:19.35#ibcon#read 5, iclass 5, count 2 2006.173.20:13:19.35#ibcon#about to read 6, iclass 5, count 2 2006.173.20:13:19.35#ibcon#read 6, iclass 5, count 2 2006.173.20:13:19.35#ibcon#end of sib2, iclass 5, count 2 2006.173.20:13:19.35#ibcon#*mode == 0, iclass 5, count 2 2006.173.20:13:19.35#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.20:13:19.35#ibcon#[25=AT07-04\r\n] 2006.173.20:13:19.35#ibcon#*before write, iclass 5, count 2 2006.173.20:13:19.35#ibcon#enter sib2, iclass 5, count 2 2006.173.20:13:19.35#ibcon#flushed, iclass 5, count 2 2006.173.20:13:19.35#ibcon#about to write, iclass 5, count 2 2006.173.20:13:19.35#ibcon#wrote, iclass 5, count 2 2006.173.20:13:19.35#ibcon#about to read 3, iclass 5, count 2 2006.173.20:13:19.38#ibcon#read 3, iclass 5, count 2 2006.173.20:13:19.38#ibcon#about to read 4, iclass 5, count 2 2006.173.20:13:19.38#ibcon#read 4, iclass 5, count 2 2006.173.20:13:19.38#ibcon#about to read 5, iclass 5, count 2 2006.173.20:13:19.38#ibcon#read 5, iclass 5, count 2 2006.173.20:13:19.38#ibcon#about to read 6, iclass 5, count 2 2006.173.20:13:19.38#ibcon#read 6, iclass 5, count 2 2006.173.20:13:19.38#ibcon#end of sib2, iclass 5, count 2 2006.173.20:13:19.38#ibcon#*after write, iclass 5, count 2 2006.173.20:13:19.38#ibcon#*before return 0, iclass 5, count 2 2006.173.20:13:19.38#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.20:13:19.38#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.20:13:19.38#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.20:13:19.38#ibcon#ireg 7 cls_cnt 0 2006.173.20:13:19.38#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.20:13:19.50#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.20:13:19.50#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.20:13:19.50#ibcon#enter wrdev, iclass 5, count 0 2006.173.20:13:19.50#ibcon#first serial, iclass 5, count 0 2006.173.20:13:19.50#ibcon#enter sib2, iclass 5, count 0 2006.173.20:13:19.50#ibcon#flushed, iclass 5, count 0 2006.173.20:13:19.50#ibcon#about to write, iclass 5, count 0 2006.173.20:13:19.50#ibcon#wrote, iclass 5, count 0 2006.173.20:13:19.50#ibcon#about to read 3, iclass 5, count 0 2006.173.20:13:19.52#ibcon#read 3, iclass 5, count 0 2006.173.20:13:19.52#ibcon#about to read 4, iclass 5, count 0 2006.173.20:13:19.52#ibcon#read 4, iclass 5, count 0 2006.173.20:13:19.52#ibcon#about to read 5, iclass 5, count 0 2006.173.20:13:19.52#ibcon#read 5, iclass 5, count 0 2006.173.20:13:19.52#ibcon#about to read 6, iclass 5, count 0 2006.173.20:13:19.52#ibcon#read 6, iclass 5, count 0 2006.173.20:13:19.52#ibcon#end of sib2, iclass 5, count 0 2006.173.20:13:19.52#ibcon#*mode == 0, iclass 5, count 0 2006.173.20:13:19.52#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.20:13:19.52#ibcon#[25=USB\r\n] 2006.173.20:13:19.52#ibcon#*before write, iclass 5, count 0 2006.173.20:13:19.52#ibcon#enter sib2, iclass 5, count 0 2006.173.20:13:19.52#ibcon#flushed, iclass 5, count 0 2006.173.20:13:19.52#ibcon#about to write, iclass 5, count 0 2006.173.20:13:19.52#ibcon#wrote, iclass 5, count 0 2006.173.20:13:19.52#ibcon#about to read 3, iclass 5, count 0 2006.173.20:13:19.55#ibcon#read 3, iclass 5, count 0 2006.173.20:13:19.55#ibcon#about to read 4, iclass 5, count 0 2006.173.20:13:19.55#ibcon#read 4, iclass 5, count 0 2006.173.20:13:19.55#ibcon#about to read 5, iclass 5, count 0 2006.173.20:13:19.55#ibcon#read 5, iclass 5, count 0 2006.173.20:13:19.55#ibcon#about to read 6, iclass 5, count 0 2006.173.20:13:19.55#ibcon#read 6, iclass 5, count 0 2006.173.20:13:19.55#ibcon#end of sib2, iclass 5, count 0 2006.173.20:13:19.55#ibcon#*after write, iclass 5, count 0 2006.173.20:13:19.55#ibcon#*before return 0, iclass 5, count 0 2006.173.20:13:19.55#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.20:13:19.55#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.20:13:19.55#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.20:13:19.55#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.20:13:19.55$vck44/valo=8,884.99 2006.173.20:13:19.55#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.20:13:19.55#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.20:13:19.55#ibcon#ireg 17 cls_cnt 0 2006.173.20:13:19.55#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.20:13:19.55#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.20:13:19.55#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.20:13:19.55#ibcon#enter wrdev, iclass 7, count 0 2006.173.20:13:19.55#ibcon#first serial, iclass 7, count 0 2006.173.20:13:19.55#ibcon#enter sib2, iclass 7, count 0 2006.173.20:13:19.55#ibcon#flushed, iclass 7, count 0 2006.173.20:13:19.55#ibcon#about to write, iclass 7, count 0 2006.173.20:13:19.55#ibcon#wrote, iclass 7, count 0 2006.173.20:13:19.55#ibcon#about to read 3, iclass 7, count 0 2006.173.20:13:19.57#ibcon#read 3, iclass 7, count 0 2006.173.20:13:19.57#ibcon#about to read 4, iclass 7, count 0 2006.173.20:13:19.57#ibcon#read 4, iclass 7, count 0 2006.173.20:13:19.57#ibcon#about to read 5, iclass 7, count 0 2006.173.20:13:19.57#ibcon#read 5, iclass 7, count 0 2006.173.20:13:19.57#ibcon#about to read 6, iclass 7, count 0 2006.173.20:13:19.57#ibcon#read 6, iclass 7, count 0 2006.173.20:13:19.57#ibcon#end of sib2, iclass 7, count 0 2006.173.20:13:19.57#ibcon#*mode == 0, iclass 7, count 0 2006.173.20:13:19.57#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.20:13:19.57#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.20:13:19.57#ibcon#*before write, iclass 7, count 0 2006.173.20:13:19.57#ibcon#enter sib2, iclass 7, count 0 2006.173.20:13:19.57#ibcon#flushed, iclass 7, count 0 2006.173.20:13:19.57#ibcon#about to write, iclass 7, count 0 2006.173.20:13:19.57#ibcon#wrote, iclass 7, count 0 2006.173.20:13:19.57#ibcon#about to read 3, iclass 7, count 0 2006.173.20:13:19.61#ibcon#read 3, iclass 7, count 0 2006.173.20:13:19.61#ibcon#about to read 4, iclass 7, count 0 2006.173.20:13:19.61#ibcon#read 4, iclass 7, count 0 2006.173.20:13:19.61#ibcon#about to read 5, iclass 7, count 0 2006.173.20:13:19.61#ibcon#read 5, iclass 7, count 0 2006.173.20:13:19.61#ibcon#about to read 6, iclass 7, count 0 2006.173.20:13:19.61#ibcon#read 6, iclass 7, count 0 2006.173.20:13:19.61#ibcon#end of sib2, iclass 7, count 0 2006.173.20:13:19.61#ibcon#*after write, iclass 7, count 0 2006.173.20:13:19.61#ibcon#*before return 0, iclass 7, count 0 2006.173.20:13:19.61#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.20:13:19.61#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.20:13:19.61#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.20:13:19.61#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.20:13:19.61$vck44/va=8,4 2006.173.20:13:19.61#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.20:13:19.61#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.20:13:19.61#ibcon#ireg 11 cls_cnt 2 2006.173.20:13:19.61#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.20:13:19.67#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.20:13:19.67#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.20:13:19.67#ibcon#enter wrdev, iclass 11, count 2 2006.173.20:13:19.67#ibcon#first serial, iclass 11, count 2 2006.173.20:13:19.67#ibcon#enter sib2, iclass 11, count 2 2006.173.20:13:19.67#ibcon#flushed, iclass 11, count 2 2006.173.20:13:19.67#ibcon#about to write, iclass 11, count 2 2006.173.20:13:19.67#ibcon#wrote, iclass 11, count 2 2006.173.20:13:19.67#ibcon#about to read 3, iclass 11, count 2 2006.173.20:13:19.69#ibcon#read 3, iclass 11, count 2 2006.173.20:13:19.69#ibcon#about to read 4, iclass 11, count 2 2006.173.20:13:19.69#ibcon#read 4, iclass 11, count 2 2006.173.20:13:19.69#ibcon#about to read 5, iclass 11, count 2 2006.173.20:13:19.69#ibcon#read 5, iclass 11, count 2 2006.173.20:13:19.69#ibcon#about to read 6, iclass 11, count 2 2006.173.20:13:19.69#ibcon#read 6, iclass 11, count 2 2006.173.20:13:19.69#ibcon#end of sib2, iclass 11, count 2 2006.173.20:13:19.69#ibcon#*mode == 0, iclass 11, count 2 2006.173.20:13:19.69#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.20:13:19.69#ibcon#[25=AT08-04\r\n] 2006.173.20:13:19.69#ibcon#*before write, iclass 11, count 2 2006.173.20:13:19.69#ibcon#enter sib2, iclass 11, count 2 2006.173.20:13:19.69#ibcon#flushed, iclass 11, count 2 2006.173.20:13:19.69#ibcon#about to write, iclass 11, count 2 2006.173.20:13:19.69#ibcon#wrote, iclass 11, count 2 2006.173.20:13:19.69#ibcon#about to read 3, iclass 11, count 2 2006.173.20:13:19.72#ibcon#read 3, iclass 11, count 2 2006.173.20:13:19.72#ibcon#about to read 4, iclass 11, count 2 2006.173.20:13:19.72#ibcon#read 4, iclass 11, count 2 2006.173.20:13:19.72#ibcon#about to read 5, iclass 11, count 2 2006.173.20:13:19.72#ibcon#read 5, iclass 11, count 2 2006.173.20:13:19.72#ibcon#about to read 6, iclass 11, count 2 2006.173.20:13:19.72#ibcon#read 6, iclass 11, count 2 2006.173.20:13:19.72#ibcon#end of sib2, iclass 11, count 2 2006.173.20:13:19.72#ibcon#*after write, iclass 11, count 2 2006.173.20:13:19.72#ibcon#*before return 0, iclass 11, count 2 2006.173.20:13:19.72#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.20:13:19.72#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.20:13:19.72#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.20:13:19.72#ibcon#ireg 7 cls_cnt 0 2006.173.20:13:19.72#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.20:13:19.84#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.20:13:19.84#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.20:13:19.84#ibcon#enter wrdev, iclass 11, count 0 2006.173.20:13:19.84#ibcon#first serial, iclass 11, count 0 2006.173.20:13:19.84#ibcon#enter sib2, iclass 11, count 0 2006.173.20:13:19.84#ibcon#flushed, iclass 11, count 0 2006.173.20:13:19.84#ibcon#about to write, iclass 11, count 0 2006.173.20:13:19.84#ibcon#wrote, iclass 11, count 0 2006.173.20:13:19.84#ibcon#about to read 3, iclass 11, count 0 2006.173.20:13:19.86#ibcon#read 3, iclass 11, count 0 2006.173.20:13:19.86#ibcon#about to read 4, iclass 11, count 0 2006.173.20:13:19.86#ibcon#read 4, iclass 11, count 0 2006.173.20:13:19.86#ibcon#about to read 5, iclass 11, count 0 2006.173.20:13:19.86#ibcon#read 5, iclass 11, count 0 2006.173.20:13:19.86#ibcon#about to read 6, iclass 11, count 0 2006.173.20:13:19.86#ibcon#read 6, iclass 11, count 0 2006.173.20:13:19.86#ibcon#end of sib2, iclass 11, count 0 2006.173.20:13:19.86#ibcon#*mode == 0, iclass 11, count 0 2006.173.20:13:19.86#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.20:13:19.86#ibcon#[25=USB\r\n] 2006.173.20:13:19.86#ibcon#*before write, iclass 11, count 0 2006.173.20:13:19.86#ibcon#enter sib2, iclass 11, count 0 2006.173.20:13:19.86#ibcon#flushed, iclass 11, count 0 2006.173.20:13:19.86#ibcon#about to write, iclass 11, count 0 2006.173.20:13:19.86#ibcon#wrote, iclass 11, count 0 2006.173.20:13:19.86#ibcon#about to read 3, iclass 11, count 0 2006.173.20:13:19.89#ibcon#read 3, iclass 11, count 0 2006.173.20:13:19.89#ibcon#about to read 4, iclass 11, count 0 2006.173.20:13:19.89#ibcon#read 4, iclass 11, count 0 2006.173.20:13:19.89#ibcon#about to read 5, iclass 11, count 0 2006.173.20:13:19.89#ibcon#read 5, iclass 11, count 0 2006.173.20:13:19.89#ibcon#about to read 6, iclass 11, count 0 2006.173.20:13:19.89#ibcon#read 6, iclass 11, count 0 2006.173.20:13:19.89#ibcon#end of sib2, iclass 11, count 0 2006.173.20:13:19.89#ibcon#*after write, iclass 11, count 0 2006.173.20:13:19.89#ibcon#*before return 0, iclass 11, count 0 2006.173.20:13:19.89#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.20:13:19.89#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.20:13:19.89#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.20:13:19.89#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.20:13:19.89$vck44/vblo=1,629.99 2006.173.20:13:19.89#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.20:13:19.89#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.20:13:19.89#ibcon#ireg 17 cls_cnt 0 2006.173.20:13:19.89#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.20:13:19.89#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.20:13:19.89#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.20:13:19.89#ibcon#enter wrdev, iclass 13, count 0 2006.173.20:13:19.89#ibcon#first serial, iclass 13, count 0 2006.173.20:13:19.89#ibcon#enter sib2, iclass 13, count 0 2006.173.20:13:19.89#ibcon#flushed, iclass 13, count 0 2006.173.20:13:19.89#ibcon#about to write, iclass 13, count 0 2006.173.20:13:19.89#ibcon#wrote, iclass 13, count 0 2006.173.20:13:19.89#ibcon#about to read 3, iclass 13, count 0 2006.173.20:13:19.91#ibcon#read 3, iclass 13, count 0 2006.173.20:13:19.91#ibcon#about to read 4, iclass 13, count 0 2006.173.20:13:19.91#ibcon#read 4, iclass 13, count 0 2006.173.20:13:19.91#ibcon#about to read 5, iclass 13, count 0 2006.173.20:13:19.91#ibcon#read 5, iclass 13, count 0 2006.173.20:13:19.91#ibcon#about to read 6, iclass 13, count 0 2006.173.20:13:19.91#ibcon#read 6, iclass 13, count 0 2006.173.20:13:19.91#ibcon#end of sib2, iclass 13, count 0 2006.173.20:13:19.91#ibcon#*mode == 0, iclass 13, count 0 2006.173.20:13:19.91#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.20:13:19.91#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.20:13:19.91#ibcon#*before write, iclass 13, count 0 2006.173.20:13:19.91#ibcon#enter sib2, iclass 13, count 0 2006.173.20:13:19.91#ibcon#flushed, iclass 13, count 0 2006.173.20:13:19.91#ibcon#about to write, iclass 13, count 0 2006.173.20:13:19.91#ibcon#wrote, iclass 13, count 0 2006.173.20:13:19.91#ibcon#about to read 3, iclass 13, count 0 2006.173.20:13:19.95#ibcon#read 3, iclass 13, count 0 2006.173.20:13:19.95#ibcon#about to read 4, iclass 13, count 0 2006.173.20:13:19.95#ibcon#read 4, iclass 13, count 0 2006.173.20:13:19.95#ibcon#about to read 5, iclass 13, count 0 2006.173.20:13:19.95#ibcon#read 5, iclass 13, count 0 2006.173.20:13:19.95#ibcon#about to read 6, iclass 13, count 0 2006.173.20:13:19.95#ibcon#read 6, iclass 13, count 0 2006.173.20:13:19.95#ibcon#end of sib2, iclass 13, count 0 2006.173.20:13:19.95#ibcon#*after write, iclass 13, count 0 2006.173.20:13:19.95#ibcon#*before return 0, iclass 13, count 0 2006.173.20:13:19.95#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.20:13:19.95#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.20:13:19.95#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.20:13:19.95#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.20:13:19.95$vck44/vb=1,4 2006.173.20:13:19.95#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.20:13:19.95#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.20:13:19.95#ibcon#ireg 11 cls_cnt 2 2006.173.20:13:19.95#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.20:13:19.95#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.20:13:19.95#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.20:13:19.95#ibcon#enter wrdev, iclass 15, count 2 2006.173.20:13:19.95#ibcon#first serial, iclass 15, count 2 2006.173.20:13:19.95#ibcon#enter sib2, iclass 15, count 2 2006.173.20:13:19.95#ibcon#flushed, iclass 15, count 2 2006.173.20:13:19.95#ibcon#about to write, iclass 15, count 2 2006.173.20:13:19.95#ibcon#wrote, iclass 15, count 2 2006.173.20:13:19.95#ibcon#about to read 3, iclass 15, count 2 2006.173.20:13:19.97#ibcon#read 3, iclass 15, count 2 2006.173.20:13:19.97#ibcon#about to read 4, iclass 15, count 2 2006.173.20:13:19.97#ibcon#read 4, iclass 15, count 2 2006.173.20:13:19.97#ibcon#about to read 5, iclass 15, count 2 2006.173.20:13:19.97#ibcon#read 5, iclass 15, count 2 2006.173.20:13:19.97#ibcon#about to read 6, iclass 15, count 2 2006.173.20:13:19.97#ibcon#read 6, iclass 15, count 2 2006.173.20:13:19.97#ibcon#end of sib2, iclass 15, count 2 2006.173.20:13:19.97#ibcon#*mode == 0, iclass 15, count 2 2006.173.20:13:19.97#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.20:13:19.97#ibcon#[27=AT01-04\r\n] 2006.173.20:13:19.97#ibcon#*before write, iclass 15, count 2 2006.173.20:13:19.97#ibcon#enter sib2, iclass 15, count 2 2006.173.20:13:19.97#ibcon#flushed, iclass 15, count 2 2006.173.20:13:19.97#ibcon#about to write, iclass 15, count 2 2006.173.20:13:19.97#ibcon#wrote, iclass 15, count 2 2006.173.20:13:19.97#ibcon#about to read 3, iclass 15, count 2 2006.173.20:13:20.00#ibcon#read 3, iclass 15, count 2 2006.173.20:13:20.00#ibcon#about to read 4, iclass 15, count 2 2006.173.20:13:20.00#ibcon#read 4, iclass 15, count 2 2006.173.20:13:20.00#ibcon#about to read 5, iclass 15, count 2 2006.173.20:13:20.00#ibcon#read 5, iclass 15, count 2 2006.173.20:13:20.00#ibcon#about to read 6, iclass 15, count 2 2006.173.20:13:20.00#ibcon#read 6, iclass 15, count 2 2006.173.20:13:20.00#ibcon#end of sib2, iclass 15, count 2 2006.173.20:13:20.00#ibcon#*after write, iclass 15, count 2 2006.173.20:13:20.00#ibcon#*before return 0, iclass 15, count 2 2006.173.20:13:20.00#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.20:13:20.00#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.20:13:20.00#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.20:13:20.00#ibcon#ireg 7 cls_cnt 0 2006.173.20:13:20.00#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.20:13:20.12#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.20:13:20.12#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.20:13:20.12#ibcon#enter wrdev, iclass 15, count 0 2006.173.20:13:20.12#ibcon#first serial, iclass 15, count 0 2006.173.20:13:20.12#ibcon#enter sib2, iclass 15, count 0 2006.173.20:13:20.12#ibcon#flushed, iclass 15, count 0 2006.173.20:13:20.12#ibcon#about to write, iclass 15, count 0 2006.173.20:13:20.12#ibcon#wrote, iclass 15, count 0 2006.173.20:13:20.12#ibcon#about to read 3, iclass 15, count 0 2006.173.20:13:20.14#ibcon#read 3, iclass 15, count 0 2006.173.20:13:20.14#ibcon#about to read 4, iclass 15, count 0 2006.173.20:13:20.14#ibcon#read 4, iclass 15, count 0 2006.173.20:13:20.14#ibcon#about to read 5, iclass 15, count 0 2006.173.20:13:20.14#ibcon#read 5, iclass 15, count 0 2006.173.20:13:20.14#ibcon#about to read 6, iclass 15, count 0 2006.173.20:13:20.14#ibcon#read 6, iclass 15, count 0 2006.173.20:13:20.14#ibcon#end of sib2, iclass 15, count 0 2006.173.20:13:20.14#ibcon#*mode == 0, iclass 15, count 0 2006.173.20:13:20.14#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.20:13:20.14#ibcon#[27=USB\r\n] 2006.173.20:13:20.14#ibcon#*before write, iclass 15, count 0 2006.173.20:13:20.14#ibcon#enter sib2, iclass 15, count 0 2006.173.20:13:20.14#ibcon#flushed, iclass 15, count 0 2006.173.20:13:20.14#ibcon#about to write, iclass 15, count 0 2006.173.20:13:20.14#ibcon#wrote, iclass 15, count 0 2006.173.20:13:20.14#ibcon#about to read 3, iclass 15, count 0 2006.173.20:13:20.17#ibcon#read 3, iclass 15, count 0 2006.173.20:13:20.17#ibcon#about to read 4, iclass 15, count 0 2006.173.20:13:20.17#ibcon#read 4, iclass 15, count 0 2006.173.20:13:20.17#ibcon#about to read 5, iclass 15, count 0 2006.173.20:13:20.17#ibcon#read 5, iclass 15, count 0 2006.173.20:13:20.17#ibcon#about to read 6, iclass 15, count 0 2006.173.20:13:20.17#ibcon#read 6, iclass 15, count 0 2006.173.20:13:20.17#ibcon#end of sib2, iclass 15, count 0 2006.173.20:13:20.17#ibcon#*after write, iclass 15, count 0 2006.173.20:13:20.17#ibcon#*before return 0, iclass 15, count 0 2006.173.20:13:20.17#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.20:13:20.17#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.20:13:20.17#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.20:13:20.17#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.20:13:20.17$vck44/vblo=2,634.99 2006.173.20:13:20.17#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.20:13:20.17#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.20:13:20.17#ibcon#ireg 17 cls_cnt 0 2006.173.20:13:20.17#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.20:13:20.17#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.20:13:20.17#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.20:13:20.17#ibcon#enter wrdev, iclass 17, count 0 2006.173.20:13:20.17#ibcon#first serial, iclass 17, count 0 2006.173.20:13:20.17#ibcon#enter sib2, iclass 17, count 0 2006.173.20:13:20.17#ibcon#flushed, iclass 17, count 0 2006.173.20:13:20.17#ibcon#about to write, iclass 17, count 0 2006.173.20:13:20.17#ibcon#wrote, iclass 17, count 0 2006.173.20:13:20.17#ibcon#about to read 3, iclass 17, count 0 2006.173.20:13:20.19#ibcon#read 3, iclass 17, count 0 2006.173.20:13:20.19#ibcon#about to read 4, iclass 17, count 0 2006.173.20:13:20.19#ibcon#read 4, iclass 17, count 0 2006.173.20:13:20.19#ibcon#about to read 5, iclass 17, count 0 2006.173.20:13:20.19#ibcon#read 5, iclass 17, count 0 2006.173.20:13:20.19#ibcon#about to read 6, iclass 17, count 0 2006.173.20:13:20.19#ibcon#read 6, iclass 17, count 0 2006.173.20:13:20.19#ibcon#end of sib2, iclass 17, count 0 2006.173.20:13:20.19#ibcon#*mode == 0, iclass 17, count 0 2006.173.20:13:20.19#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.20:13:20.19#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.20:13:20.19#ibcon#*before write, iclass 17, count 0 2006.173.20:13:20.19#ibcon#enter sib2, iclass 17, count 0 2006.173.20:13:20.19#ibcon#flushed, iclass 17, count 0 2006.173.20:13:20.19#ibcon#about to write, iclass 17, count 0 2006.173.20:13:20.19#ibcon#wrote, iclass 17, count 0 2006.173.20:13:20.19#ibcon#about to read 3, iclass 17, count 0 2006.173.20:13:20.23#ibcon#read 3, iclass 17, count 0 2006.173.20:13:20.23#ibcon#about to read 4, iclass 17, count 0 2006.173.20:13:20.23#ibcon#read 4, iclass 17, count 0 2006.173.20:13:20.23#ibcon#about to read 5, iclass 17, count 0 2006.173.20:13:20.23#ibcon#read 5, iclass 17, count 0 2006.173.20:13:20.23#ibcon#about to read 6, iclass 17, count 0 2006.173.20:13:20.23#ibcon#read 6, iclass 17, count 0 2006.173.20:13:20.23#ibcon#end of sib2, iclass 17, count 0 2006.173.20:13:20.23#ibcon#*after write, iclass 17, count 0 2006.173.20:13:20.23#ibcon#*before return 0, iclass 17, count 0 2006.173.20:13:20.23#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.20:13:20.23#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.20:13:20.23#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.20:13:20.23#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.20:13:20.23$vck44/vb=2,4 2006.173.20:13:20.23#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.20:13:20.23#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.20:13:20.23#ibcon#ireg 11 cls_cnt 2 2006.173.20:13:20.23#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.20:13:20.29#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.20:13:20.29#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.20:13:20.29#ibcon#enter wrdev, iclass 19, count 2 2006.173.20:13:20.29#ibcon#first serial, iclass 19, count 2 2006.173.20:13:20.29#ibcon#enter sib2, iclass 19, count 2 2006.173.20:13:20.29#ibcon#flushed, iclass 19, count 2 2006.173.20:13:20.29#ibcon#about to write, iclass 19, count 2 2006.173.20:13:20.29#ibcon#wrote, iclass 19, count 2 2006.173.20:13:20.29#ibcon#about to read 3, iclass 19, count 2 2006.173.20:13:20.31#ibcon#read 3, iclass 19, count 2 2006.173.20:13:20.31#ibcon#about to read 4, iclass 19, count 2 2006.173.20:13:20.31#ibcon#read 4, iclass 19, count 2 2006.173.20:13:20.31#ibcon#about to read 5, iclass 19, count 2 2006.173.20:13:20.31#ibcon#read 5, iclass 19, count 2 2006.173.20:13:20.31#ibcon#about to read 6, iclass 19, count 2 2006.173.20:13:20.31#ibcon#read 6, iclass 19, count 2 2006.173.20:13:20.31#ibcon#end of sib2, iclass 19, count 2 2006.173.20:13:20.31#ibcon#*mode == 0, iclass 19, count 2 2006.173.20:13:20.31#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.20:13:20.31#ibcon#[27=AT02-04\r\n] 2006.173.20:13:20.31#ibcon#*before write, iclass 19, count 2 2006.173.20:13:20.31#ibcon#enter sib2, iclass 19, count 2 2006.173.20:13:20.31#ibcon#flushed, iclass 19, count 2 2006.173.20:13:20.31#ibcon#about to write, iclass 19, count 2 2006.173.20:13:20.31#ibcon#wrote, iclass 19, count 2 2006.173.20:13:20.31#ibcon#about to read 3, iclass 19, count 2 2006.173.20:13:20.34#ibcon#read 3, iclass 19, count 2 2006.173.20:13:20.34#ibcon#about to read 4, iclass 19, count 2 2006.173.20:13:20.34#ibcon#read 4, iclass 19, count 2 2006.173.20:13:20.34#ibcon#about to read 5, iclass 19, count 2 2006.173.20:13:20.34#ibcon#read 5, iclass 19, count 2 2006.173.20:13:20.34#ibcon#about to read 6, iclass 19, count 2 2006.173.20:13:20.34#ibcon#read 6, iclass 19, count 2 2006.173.20:13:20.34#ibcon#end of sib2, iclass 19, count 2 2006.173.20:13:20.34#ibcon#*after write, iclass 19, count 2 2006.173.20:13:20.34#ibcon#*before return 0, iclass 19, count 2 2006.173.20:13:20.34#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.20:13:20.34#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.20:13:20.34#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.20:13:20.34#ibcon#ireg 7 cls_cnt 0 2006.173.20:13:20.34#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.20:13:20.46#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.20:13:20.46#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.20:13:20.46#ibcon#enter wrdev, iclass 19, count 0 2006.173.20:13:20.46#ibcon#first serial, iclass 19, count 0 2006.173.20:13:20.46#ibcon#enter sib2, iclass 19, count 0 2006.173.20:13:20.46#ibcon#flushed, iclass 19, count 0 2006.173.20:13:20.46#ibcon#about to write, iclass 19, count 0 2006.173.20:13:20.46#ibcon#wrote, iclass 19, count 0 2006.173.20:13:20.46#ibcon#about to read 3, iclass 19, count 0 2006.173.20:13:20.48#ibcon#read 3, iclass 19, count 0 2006.173.20:13:20.48#ibcon#about to read 4, iclass 19, count 0 2006.173.20:13:20.48#ibcon#read 4, iclass 19, count 0 2006.173.20:13:20.48#ibcon#about to read 5, iclass 19, count 0 2006.173.20:13:20.48#ibcon#read 5, iclass 19, count 0 2006.173.20:13:20.48#ibcon#about to read 6, iclass 19, count 0 2006.173.20:13:20.48#ibcon#read 6, iclass 19, count 0 2006.173.20:13:20.48#ibcon#end of sib2, iclass 19, count 0 2006.173.20:13:20.48#ibcon#*mode == 0, iclass 19, count 0 2006.173.20:13:20.48#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.20:13:20.48#ibcon#[27=USB\r\n] 2006.173.20:13:20.48#ibcon#*before write, iclass 19, count 0 2006.173.20:13:20.48#ibcon#enter sib2, iclass 19, count 0 2006.173.20:13:20.48#ibcon#flushed, iclass 19, count 0 2006.173.20:13:20.48#ibcon#about to write, iclass 19, count 0 2006.173.20:13:20.48#ibcon#wrote, iclass 19, count 0 2006.173.20:13:20.48#ibcon#about to read 3, iclass 19, count 0 2006.173.20:13:20.51#ibcon#read 3, iclass 19, count 0 2006.173.20:13:20.51#ibcon#about to read 4, iclass 19, count 0 2006.173.20:13:20.51#ibcon#read 4, iclass 19, count 0 2006.173.20:13:20.51#ibcon#about to read 5, iclass 19, count 0 2006.173.20:13:20.51#ibcon#read 5, iclass 19, count 0 2006.173.20:13:20.51#ibcon#about to read 6, iclass 19, count 0 2006.173.20:13:20.51#ibcon#read 6, iclass 19, count 0 2006.173.20:13:20.51#ibcon#end of sib2, iclass 19, count 0 2006.173.20:13:20.51#ibcon#*after write, iclass 19, count 0 2006.173.20:13:20.51#ibcon#*before return 0, iclass 19, count 0 2006.173.20:13:20.51#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.20:13:20.51#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.20:13:20.51#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.20:13:20.51#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.20:13:20.51$vck44/vblo=3,649.99 2006.173.20:13:20.51#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.20:13:20.51#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.20:13:20.51#ibcon#ireg 17 cls_cnt 0 2006.173.20:13:20.51#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.20:13:20.51#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.20:13:20.51#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.20:13:20.51#ibcon#enter wrdev, iclass 21, count 0 2006.173.20:13:20.51#ibcon#first serial, iclass 21, count 0 2006.173.20:13:20.51#ibcon#enter sib2, iclass 21, count 0 2006.173.20:13:20.51#ibcon#flushed, iclass 21, count 0 2006.173.20:13:20.51#ibcon#about to write, iclass 21, count 0 2006.173.20:13:20.51#ibcon#wrote, iclass 21, count 0 2006.173.20:13:20.51#ibcon#about to read 3, iclass 21, count 0 2006.173.20:13:20.53#ibcon#read 3, iclass 21, count 0 2006.173.20:13:20.53#ibcon#about to read 4, iclass 21, count 0 2006.173.20:13:20.53#ibcon#read 4, iclass 21, count 0 2006.173.20:13:20.53#ibcon#about to read 5, iclass 21, count 0 2006.173.20:13:20.53#ibcon#read 5, iclass 21, count 0 2006.173.20:13:20.53#ibcon#about to read 6, iclass 21, count 0 2006.173.20:13:20.53#ibcon#read 6, iclass 21, count 0 2006.173.20:13:20.53#ibcon#end of sib2, iclass 21, count 0 2006.173.20:13:20.53#ibcon#*mode == 0, iclass 21, count 0 2006.173.20:13:20.53#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.20:13:20.53#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.20:13:20.53#ibcon#*before write, iclass 21, count 0 2006.173.20:13:20.53#ibcon#enter sib2, iclass 21, count 0 2006.173.20:13:20.53#ibcon#flushed, iclass 21, count 0 2006.173.20:13:20.53#ibcon#about to write, iclass 21, count 0 2006.173.20:13:20.53#ibcon#wrote, iclass 21, count 0 2006.173.20:13:20.53#ibcon#about to read 3, iclass 21, count 0 2006.173.20:13:20.57#ibcon#read 3, iclass 21, count 0 2006.173.20:13:20.57#ibcon#about to read 4, iclass 21, count 0 2006.173.20:13:20.57#ibcon#read 4, iclass 21, count 0 2006.173.20:13:20.57#ibcon#about to read 5, iclass 21, count 0 2006.173.20:13:20.57#ibcon#read 5, iclass 21, count 0 2006.173.20:13:20.57#ibcon#about to read 6, iclass 21, count 0 2006.173.20:13:20.57#ibcon#read 6, iclass 21, count 0 2006.173.20:13:20.57#ibcon#end of sib2, iclass 21, count 0 2006.173.20:13:20.57#ibcon#*after write, iclass 21, count 0 2006.173.20:13:20.57#ibcon#*before return 0, iclass 21, count 0 2006.173.20:13:20.57#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.20:13:20.57#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.20:13:20.57#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.20:13:20.57#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.20:13:20.57$vck44/vb=3,4 2006.173.20:13:20.57#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.20:13:20.57#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.20:13:20.57#ibcon#ireg 11 cls_cnt 2 2006.173.20:13:20.57#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.20:13:20.63#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.20:13:20.63#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.20:13:20.63#ibcon#enter wrdev, iclass 23, count 2 2006.173.20:13:20.63#ibcon#first serial, iclass 23, count 2 2006.173.20:13:20.63#ibcon#enter sib2, iclass 23, count 2 2006.173.20:13:20.63#ibcon#flushed, iclass 23, count 2 2006.173.20:13:20.63#ibcon#about to write, iclass 23, count 2 2006.173.20:13:20.63#ibcon#wrote, iclass 23, count 2 2006.173.20:13:20.63#ibcon#about to read 3, iclass 23, count 2 2006.173.20:13:20.65#ibcon#read 3, iclass 23, count 2 2006.173.20:13:20.65#ibcon#about to read 4, iclass 23, count 2 2006.173.20:13:20.65#ibcon#read 4, iclass 23, count 2 2006.173.20:13:20.65#ibcon#about to read 5, iclass 23, count 2 2006.173.20:13:20.65#ibcon#read 5, iclass 23, count 2 2006.173.20:13:20.65#ibcon#about to read 6, iclass 23, count 2 2006.173.20:13:20.65#ibcon#read 6, iclass 23, count 2 2006.173.20:13:20.65#ibcon#end of sib2, iclass 23, count 2 2006.173.20:13:20.65#ibcon#*mode == 0, iclass 23, count 2 2006.173.20:13:20.65#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.20:13:20.65#ibcon#[27=AT03-04\r\n] 2006.173.20:13:20.65#ibcon#*before write, iclass 23, count 2 2006.173.20:13:20.65#ibcon#enter sib2, iclass 23, count 2 2006.173.20:13:20.65#ibcon#flushed, iclass 23, count 2 2006.173.20:13:20.65#ibcon#about to write, iclass 23, count 2 2006.173.20:13:20.65#ibcon#wrote, iclass 23, count 2 2006.173.20:13:20.65#ibcon#about to read 3, iclass 23, count 2 2006.173.20:13:20.68#abcon#<5=/07 0.3 0.9 19.571001002.7\r\n> 2006.173.20:13:20.68#ibcon#read 3, iclass 23, count 2 2006.173.20:13:20.68#ibcon#about to read 4, iclass 23, count 2 2006.173.20:13:20.68#ibcon#read 4, iclass 23, count 2 2006.173.20:13:20.68#ibcon#about to read 5, iclass 23, count 2 2006.173.20:13:20.68#ibcon#read 5, iclass 23, count 2 2006.173.20:13:20.68#ibcon#about to read 6, iclass 23, count 2 2006.173.20:13:20.68#ibcon#read 6, iclass 23, count 2 2006.173.20:13:20.68#ibcon#end of sib2, iclass 23, count 2 2006.173.20:13:20.68#ibcon#*after write, iclass 23, count 2 2006.173.20:13:20.68#ibcon#*before return 0, iclass 23, count 2 2006.173.20:13:20.68#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.20:13:20.68#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.20:13:20.68#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.20:13:20.68#ibcon#ireg 7 cls_cnt 0 2006.173.20:13:20.68#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.20:13:20.70#abcon#{5=INTERFACE CLEAR} 2006.173.20:13:20.76#abcon#[5=S1D000X0/0*\r\n] 2006.173.20:13:20.80#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.20:13:20.80#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.20:13:20.80#ibcon#enter wrdev, iclass 23, count 0 2006.173.20:13:20.80#ibcon#first serial, iclass 23, count 0 2006.173.20:13:20.80#ibcon#enter sib2, iclass 23, count 0 2006.173.20:13:20.80#ibcon#flushed, iclass 23, count 0 2006.173.20:13:20.80#ibcon#about to write, iclass 23, count 0 2006.173.20:13:20.80#ibcon#wrote, iclass 23, count 0 2006.173.20:13:20.80#ibcon#about to read 3, iclass 23, count 0 2006.173.20:13:20.82#ibcon#read 3, iclass 23, count 0 2006.173.20:13:20.82#ibcon#about to read 4, iclass 23, count 0 2006.173.20:13:20.82#ibcon#read 4, iclass 23, count 0 2006.173.20:13:20.82#ibcon#about to read 5, iclass 23, count 0 2006.173.20:13:20.82#ibcon#read 5, iclass 23, count 0 2006.173.20:13:20.82#ibcon#about to read 6, iclass 23, count 0 2006.173.20:13:20.82#ibcon#read 6, iclass 23, count 0 2006.173.20:13:20.82#ibcon#end of sib2, iclass 23, count 0 2006.173.20:13:20.82#ibcon#*mode == 0, iclass 23, count 0 2006.173.20:13:20.82#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.20:13:20.82#ibcon#[27=USB\r\n] 2006.173.20:13:20.82#ibcon#*before write, iclass 23, count 0 2006.173.20:13:20.82#ibcon#enter sib2, iclass 23, count 0 2006.173.20:13:20.82#ibcon#flushed, iclass 23, count 0 2006.173.20:13:20.82#ibcon#about to write, iclass 23, count 0 2006.173.20:13:20.82#ibcon#wrote, iclass 23, count 0 2006.173.20:13:20.82#ibcon#about to read 3, iclass 23, count 0 2006.173.20:13:20.85#ibcon#read 3, iclass 23, count 0 2006.173.20:13:20.85#ibcon#about to read 4, iclass 23, count 0 2006.173.20:13:20.85#ibcon#read 4, iclass 23, count 0 2006.173.20:13:20.85#ibcon#about to read 5, iclass 23, count 0 2006.173.20:13:20.85#ibcon#read 5, iclass 23, count 0 2006.173.20:13:20.85#ibcon#about to read 6, iclass 23, count 0 2006.173.20:13:20.85#ibcon#read 6, iclass 23, count 0 2006.173.20:13:20.85#ibcon#end of sib2, iclass 23, count 0 2006.173.20:13:20.85#ibcon#*after write, iclass 23, count 0 2006.173.20:13:20.85#ibcon#*before return 0, iclass 23, count 0 2006.173.20:13:20.85#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.20:13:20.85#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.20:13:20.85#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.20:13:20.85#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.20:13:20.85$vck44/vblo=4,679.99 2006.173.20:13:20.85#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.20:13:20.85#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.20:13:20.85#ibcon#ireg 17 cls_cnt 0 2006.173.20:13:20.85#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.20:13:20.85#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.20:13:20.85#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.20:13:20.85#ibcon#enter wrdev, iclass 29, count 0 2006.173.20:13:20.85#ibcon#first serial, iclass 29, count 0 2006.173.20:13:20.85#ibcon#enter sib2, iclass 29, count 0 2006.173.20:13:20.85#ibcon#flushed, iclass 29, count 0 2006.173.20:13:20.85#ibcon#about to write, iclass 29, count 0 2006.173.20:13:20.85#ibcon#wrote, iclass 29, count 0 2006.173.20:13:20.85#ibcon#about to read 3, iclass 29, count 0 2006.173.20:13:20.87#ibcon#read 3, iclass 29, count 0 2006.173.20:13:20.87#ibcon#about to read 4, iclass 29, count 0 2006.173.20:13:20.87#ibcon#read 4, iclass 29, count 0 2006.173.20:13:20.87#ibcon#about to read 5, iclass 29, count 0 2006.173.20:13:20.87#ibcon#read 5, iclass 29, count 0 2006.173.20:13:20.87#ibcon#about to read 6, iclass 29, count 0 2006.173.20:13:20.87#ibcon#read 6, iclass 29, count 0 2006.173.20:13:20.87#ibcon#end of sib2, iclass 29, count 0 2006.173.20:13:20.87#ibcon#*mode == 0, iclass 29, count 0 2006.173.20:13:20.87#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.20:13:20.87#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.20:13:20.87#ibcon#*before write, iclass 29, count 0 2006.173.20:13:20.87#ibcon#enter sib2, iclass 29, count 0 2006.173.20:13:20.87#ibcon#flushed, iclass 29, count 0 2006.173.20:13:20.87#ibcon#about to write, iclass 29, count 0 2006.173.20:13:20.87#ibcon#wrote, iclass 29, count 0 2006.173.20:13:20.87#ibcon#about to read 3, iclass 29, count 0 2006.173.20:13:20.91#ibcon#read 3, iclass 29, count 0 2006.173.20:13:20.91#ibcon#about to read 4, iclass 29, count 0 2006.173.20:13:20.91#ibcon#read 4, iclass 29, count 0 2006.173.20:13:20.91#ibcon#about to read 5, iclass 29, count 0 2006.173.20:13:20.91#ibcon#read 5, iclass 29, count 0 2006.173.20:13:20.91#ibcon#about to read 6, iclass 29, count 0 2006.173.20:13:20.91#ibcon#read 6, iclass 29, count 0 2006.173.20:13:20.91#ibcon#end of sib2, iclass 29, count 0 2006.173.20:13:20.91#ibcon#*after write, iclass 29, count 0 2006.173.20:13:20.91#ibcon#*before return 0, iclass 29, count 0 2006.173.20:13:20.91#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.20:13:20.91#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.20:13:20.91#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.20:13:20.91#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.20:13:20.91$vck44/vb=4,4 2006.173.20:13:20.91#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.20:13:20.91#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.20:13:20.91#ibcon#ireg 11 cls_cnt 2 2006.173.20:13:20.91#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.20:13:20.97#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.20:13:20.97#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.20:13:20.97#ibcon#enter wrdev, iclass 31, count 2 2006.173.20:13:20.97#ibcon#first serial, iclass 31, count 2 2006.173.20:13:20.97#ibcon#enter sib2, iclass 31, count 2 2006.173.20:13:20.97#ibcon#flushed, iclass 31, count 2 2006.173.20:13:20.97#ibcon#about to write, iclass 31, count 2 2006.173.20:13:20.97#ibcon#wrote, iclass 31, count 2 2006.173.20:13:20.97#ibcon#about to read 3, iclass 31, count 2 2006.173.20:13:20.99#ibcon#read 3, iclass 31, count 2 2006.173.20:13:20.99#ibcon#about to read 4, iclass 31, count 2 2006.173.20:13:20.99#ibcon#read 4, iclass 31, count 2 2006.173.20:13:20.99#ibcon#about to read 5, iclass 31, count 2 2006.173.20:13:20.99#ibcon#read 5, iclass 31, count 2 2006.173.20:13:20.99#ibcon#about to read 6, iclass 31, count 2 2006.173.20:13:20.99#ibcon#read 6, iclass 31, count 2 2006.173.20:13:20.99#ibcon#end of sib2, iclass 31, count 2 2006.173.20:13:20.99#ibcon#*mode == 0, iclass 31, count 2 2006.173.20:13:20.99#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.20:13:20.99#ibcon#[27=AT04-04\r\n] 2006.173.20:13:20.99#ibcon#*before write, iclass 31, count 2 2006.173.20:13:20.99#ibcon#enter sib2, iclass 31, count 2 2006.173.20:13:20.99#ibcon#flushed, iclass 31, count 2 2006.173.20:13:20.99#ibcon#about to write, iclass 31, count 2 2006.173.20:13:20.99#ibcon#wrote, iclass 31, count 2 2006.173.20:13:20.99#ibcon#about to read 3, iclass 31, count 2 2006.173.20:13:21.02#ibcon#read 3, iclass 31, count 2 2006.173.20:13:21.02#ibcon#about to read 4, iclass 31, count 2 2006.173.20:13:21.02#ibcon#read 4, iclass 31, count 2 2006.173.20:13:21.02#ibcon#about to read 5, iclass 31, count 2 2006.173.20:13:21.02#ibcon#read 5, iclass 31, count 2 2006.173.20:13:21.02#ibcon#about to read 6, iclass 31, count 2 2006.173.20:13:21.02#ibcon#read 6, iclass 31, count 2 2006.173.20:13:21.02#ibcon#end of sib2, iclass 31, count 2 2006.173.20:13:21.02#ibcon#*after write, iclass 31, count 2 2006.173.20:13:21.02#ibcon#*before return 0, iclass 31, count 2 2006.173.20:13:21.02#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.20:13:21.02#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.20:13:21.02#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.20:13:21.02#ibcon#ireg 7 cls_cnt 0 2006.173.20:13:21.02#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.20:13:21.14#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.20:13:21.14#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.20:13:21.14#ibcon#enter wrdev, iclass 31, count 0 2006.173.20:13:21.14#ibcon#first serial, iclass 31, count 0 2006.173.20:13:21.14#ibcon#enter sib2, iclass 31, count 0 2006.173.20:13:21.14#ibcon#flushed, iclass 31, count 0 2006.173.20:13:21.14#ibcon#about to write, iclass 31, count 0 2006.173.20:13:21.14#ibcon#wrote, iclass 31, count 0 2006.173.20:13:21.14#ibcon#about to read 3, iclass 31, count 0 2006.173.20:13:21.16#ibcon#read 3, iclass 31, count 0 2006.173.20:13:21.16#ibcon#about to read 4, iclass 31, count 0 2006.173.20:13:21.16#ibcon#read 4, iclass 31, count 0 2006.173.20:13:21.16#ibcon#about to read 5, iclass 31, count 0 2006.173.20:13:21.16#ibcon#read 5, iclass 31, count 0 2006.173.20:13:21.16#ibcon#about to read 6, iclass 31, count 0 2006.173.20:13:21.16#ibcon#read 6, iclass 31, count 0 2006.173.20:13:21.16#ibcon#end of sib2, iclass 31, count 0 2006.173.20:13:21.16#ibcon#*mode == 0, iclass 31, count 0 2006.173.20:13:21.16#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.20:13:21.16#ibcon#[27=USB\r\n] 2006.173.20:13:21.16#ibcon#*before write, iclass 31, count 0 2006.173.20:13:21.16#ibcon#enter sib2, iclass 31, count 0 2006.173.20:13:21.16#ibcon#flushed, iclass 31, count 0 2006.173.20:13:21.16#ibcon#about to write, iclass 31, count 0 2006.173.20:13:21.16#ibcon#wrote, iclass 31, count 0 2006.173.20:13:21.16#ibcon#about to read 3, iclass 31, count 0 2006.173.20:13:21.19#ibcon#read 3, iclass 31, count 0 2006.173.20:13:21.19#ibcon#about to read 4, iclass 31, count 0 2006.173.20:13:21.19#ibcon#read 4, iclass 31, count 0 2006.173.20:13:21.19#ibcon#about to read 5, iclass 31, count 0 2006.173.20:13:21.19#ibcon#read 5, iclass 31, count 0 2006.173.20:13:21.19#ibcon#about to read 6, iclass 31, count 0 2006.173.20:13:21.19#ibcon#read 6, iclass 31, count 0 2006.173.20:13:21.19#ibcon#end of sib2, iclass 31, count 0 2006.173.20:13:21.19#ibcon#*after write, iclass 31, count 0 2006.173.20:13:21.19#ibcon#*before return 0, iclass 31, count 0 2006.173.20:13:21.19#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.20:13:21.19#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.20:13:21.19#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.20:13:21.19#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.20:13:21.19$vck44/vblo=5,709.99 2006.173.20:13:21.19#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.20:13:21.19#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.20:13:21.19#ibcon#ireg 17 cls_cnt 0 2006.173.20:13:21.19#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.20:13:21.19#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.20:13:21.19#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.20:13:21.19#ibcon#enter wrdev, iclass 33, count 0 2006.173.20:13:21.19#ibcon#first serial, iclass 33, count 0 2006.173.20:13:21.19#ibcon#enter sib2, iclass 33, count 0 2006.173.20:13:21.19#ibcon#flushed, iclass 33, count 0 2006.173.20:13:21.19#ibcon#about to write, iclass 33, count 0 2006.173.20:13:21.19#ibcon#wrote, iclass 33, count 0 2006.173.20:13:21.19#ibcon#about to read 3, iclass 33, count 0 2006.173.20:13:21.21#ibcon#read 3, iclass 33, count 0 2006.173.20:13:21.21#ibcon#about to read 4, iclass 33, count 0 2006.173.20:13:21.21#ibcon#read 4, iclass 33, count 0 2006.173.20:13:21.21#ibcon#about to read 5, iclass 33, count 0 2006.173.20:13:21.21#ibcon#read 5, iclass 33, count 0 2006.173.20:13:21.21#ibcon#about to read 6, iclass 33, count 0 2006.173.20:13:21.21#ibcon#read 6, iclass 33, count 0 2006.173.20:13:21.21#ibcon#end of sib2, iclass 33, count 0 2006.173.20:13:21.21#ibcon#*mode == 0, iclass 33, count 0 2006.173.20:13:21.21#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.20:13:21.21#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.20:13:21.21#ibcon#*before write, iclass 33, count 0 2006.173.20:13:21.21#ibcon#enter sib2, iclass 33, count 0 2006.173.20:13:21.21#ibcon#flushed, iclass 33, count 0 2006.173.20:13:21.21#ibcon#about to write, iclass 33, count 0 2006.173.20:13:21.21#ibcon#wrote, iclass 33, count 0 2006.173.20:13:21.21#ibcon#about to read 3, iclass 33, count 0 2006.173.20:13:21.25#ibcon#read 3, iclass 33, count 0 2006.173.20:13:21.25#ibcon#about to read 4, iclass 33, count 0 2006.173.20:13:21.25#ibcon#read 4, iclass 33, count 0 2006.173.20:13:21.25#ibcon#about to read 5, iclass 33, count 0 2006.173.20:13:21.25#ibcon#read 5, iclass 33, count 0 2006.173.20:13:21.25#ibcon#about to read 6, iclass 33, count 0 2006.173.20:13:21.25#ibcon#read 6, iclass 33, count 0 2006.173.20:13:21.25#ibcon#end of sib2, iclass 33, count 0 2006.173.20:13:21.25#ibcon#*after write, iclass 33, count 0 2006.173.20:13:21.25#ibcon#*before return 0, iclass 33, count 0 2006.173.20:13:21.25#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.20:13:21.25#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.20:13:21.25#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.20:13:21.25#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.20:13:21.25$vck44/vb=5,4 2006.173.20:13:21.25#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.20:13:21.25#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.20:13:21.25#ibcon#ireg 11 cls_cnt 2 2006.173.20:13:21.25#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.20:13:21.31#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.20:13:21.31#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.20:13:21.31#ibcon#enter wrdev, iclass 35, count 2 2006.173.20:13:21.31#ibcon#first serial, iclass 35, count 2 2006.173.20:13:21.31#ibcon#enter sib2, iclass 35, count 2 2006.173.20:13:21.31#ibcon#flushed, iclass 35, count 2 2006.173.20:13:21.31#ibcon#about to write, iclass 35, count 2 2006.173.20:13:21.31#ibcon#wrote, iclass 35, count 2 2006.173.20:13:21.31#ibcon#about to read 3, iclass 35, count 2 2006.173.20:13:21.33#ibcon#read 3, iclass 35, count 2 2006.173.20:13:21.33#ibcon#about to read 4, iclass 35, count 2 2006.173.20:13:21.33#ibcon#read 4, iclass 35, count 2 2006.173.20:13:21.33#ibcon#about to read 5, iclass 35, count 2 2006.173.20:13:21.33#ibcon#read 5, iclass 35, count 2 2006.173.20:13:21.33#ibcon#about to read 6, iclass 35, count 2 2006.173.20:13:21.33#ibcon#read 6, iclass 35, count 2 2006.173.20:13:21.33#ibcon#end of sib2, iclass 35, count 2 2006.173.20:13:21.33#ibcon#*mode == 0, iclass 35, count 2 2006.173.20:13:21.33#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.20:13:21.33#ibcon#[27=AT05-04\r\n] 2006.173.20:13:21.33#ibcon#*before write, iclass 35, count 2 2006.173.20:13:21.33#ibcon#enter sib2, iclass 35, count 2 2006.173.20:13:21.33#ibcon#flushed, iclass 35, count 2 2006.173.20:13:21.33#ibcon#about to write, iclass 35, count 2 2006.173.20:13:21.33#ibcon#wrote, iclass 35, count 2 2006.173.20:13:21.33#ibcon#about to read 3, iclass 35, count 2 2006.173.20:13:21.36#ibcon#read 3, iclass 35, count 2 2006.173.20:13:21.36#ibcon#about to read 4, iclass 35, count 2 2006.173.20:13:21.36#ibcon#read 4, iclass 35, count 2 2006.173.20:13:21.36#ibcon#about to read 5, iclass 35, count 2 2006.173.20:13:21.36#ibcon#read 5, iclass 35, count 2 2006.173.20:13:21.36#ibcon#about to read 6, iclass 35, count 2 2006.173.20:13:21.36#ibcon#read 6, iclass 35, count 2 2006.173.20:13:21.36#ibcon#end of sib2, iclass 35, count 2 2006.173.20:13:21.36#ibcon#*after write, iclass 35, count 2 2006.173.20:13:21.36#ibcon#*before return 0, iclass 35, count 2 2006.173.20:13:21.36#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.20:13:21.36#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.20:13:21.36#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.20:13:21.36#ibcon#ireg 7 cls_cnt 0 2006.173.20:13:21.36#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.20:13:21.48#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.20:13:21.48#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.20:13:21.48#ibcon#enter wrdev, iclass 35, count 0 2006.173.20:13:21.48#ibcon#first serial, iclass 35, count 0 2006.173.20:13:21.48#ibcon#enter sib2, iclass 35, count 0 2006.173.20:13:21.48#ibcon#flushed, iclass 35, count 0 2006.173.20:13:21.48#ibcon#about to write, iclass 35, count 0 2006.173.20:13:21.48#ibcon#wrote, iclass 35, count 0 2006.173.20:13:21.48#ibcon#about to read 3, iclass 35, count 0 2006.173.20:13:21.50#ibcon#read 3, iclass 35, count 0 2006.173.20:13:21.50#ibcon#about to read 4, iclass 35, count 0 2006.173.20:13:21.50#ibcon#read 4, iclass 35, count 0 2006.173.20:13:21.50#ibcon#about to read 5, iclass 35, count 0 2006.173.20:13:21.50#ibcon#read 5, iclass 35, count 0 2006.173.20:13:21.50#ibcon#about to read 6, iclass 35, count 0 2006.173.20:13:21.50#ibcon#read 6, iclass 35, count 0 2006.173.20:13:21.50#ibcon#end of sib2, iclass 35, count 0 2006.173.20:13:21.50#ibcon#*mode == 0, iclass 35, count 0 2006.173.20:13:21.50#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.20:13:21.50#ibcon#[27=USB\r\n] 2006.173.20:13:21.50#ibcon#*before write, iclass 35, count 0 2006.173.20:13:21.50#ibcon#enter sib2, iclass 35, count 0 2006.173.20:13:21.50#ibcon#flushed, iclass 35, count 0 2006.173.20:13:21.50#ibcon#about to write, iclass 35, count 0 2006.173.20:13:21.50#ibcon#wrote, iclass 35, count 0 2006.173.20:13:21.50#ibcon#about to read 3, iclass 35, count 0 2006.173.20:13:21.53#ibcon#read 3, iclass 35, count 0 2006.173.20:13:21.53#ibcon#about to read 4, iclass 35, count 0 2006.173.20:13:21.53#ibcon#read 4, iclass 35, count 0 2006.173.20:13:21.53#ibcon#about to read 5, iclass 35, count 0 2006.173.20:13:21.53#ibcon#read 5, iclass 35, count 0 2006.173.20:13:21.53#ibcon#about to read 6, iclass 35, count 0 2006.173.20:13:21.53#ibcon#read 6, iclass 35, count 0 2006.173.20:13:21.53#ibcon#end of sib2, iclass 35, count 0 2006.173.20:13:21.53#ibcon#*after write, iclass 35, count 0 2006.173.20:13:21.53#ibcon#*before return 0, iclass 35, count 0 2006.173.20:13:21.53#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.20:13:21.53#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.20:13:21.53#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.20:13:21.53#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.20:13:21.53$vck44/vblo=6,719.99 2006.173.20:13:21.53#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.20:13:21.53#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.20:13:21.53#ibcon#ireg 17 cls_cnt 0 2006.173.20:13:21.53#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.20:13:21.53#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.20:13:21.53#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.20:13:21.53#ibcon#enter wrdev, iclass 37, count 0 2006.173.20:13:21.53#ibcon#first serial, iclass 37, count 0 2006.173.20:13:21.53#ibcon#enter sib2, iclass 37, count 0 2006.173.20:13:21.53#ibcon#flushed, iclass 37, count 0 2006.173.20:13:21.53#ibcon#about to write, iclass 37, count 0 2006.173.20:13:21.53#ibcon#wrote, iclass 37, count 0 2006.173.20:13:21.53#ibcon#about to read 3, iclass 37, count 0 2006.173.20:13:21.55#ibcon#read 3, iclass 37, count 0 2006.173.20:13:21.55#ibcon#about to read 4, iclass 37, count 0 2006.173.20:13:21.55#ibcon#read 4, iclass 37, count 0 2006.173.20:13:21.55#ibcon#about to read 5, iclass 37, count 0 2006.173.20:13:21.55#ibcon#read 5, iclass 37, count 0 2006.173.20:13:21.55#ibcon#about to read 6, iclass 37, count 0 2006.173.20:13:21.55#ibcon#read 6, iclass 37, count 0 2006.173.20:13:21.55#ibcon#end of sib2, iclass 37, count 0 2006.173.20:13:21.55#ibcon#*mode == 0, iclass 37, count 0 2006.173.20:13:21.55#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.20:13:21.55#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.20:13:21.55#ibcon#*before write, iclass 37, count 0 2006.173.20:13:21.55#ibcon#enter sib2, iclass 37, count 0 2006.173.20:13:21.55#ibcon#flushed, iclass 37, count 0 2006.173.20:13:21.55#ibcon#about to write, iclass 37, count 0 2006.173.20:13:21.55#ibcon#wrote, iclass 37, count 0 2006.173.20:13:21.55#ibcon#about to read 3, iclass 37, count 0 2006.173.20:13:21.59#ibcon#read 3, iclass 37, count 0 2006.173.20:13:21.59#ibcon#about to read 4, iclass 37, count 0 2006.173.20:13:21.59#ibcon#read 4, iclass 37, count 0 2006.173.20:13:21.59#ibcon#about to read 5, iclass 37, count 0 2006.173.20:13:21.59#ibcon#read 5, iclass 37, count 0 2006.173.20:13:21.59#ibcon#about to read 6, iclass 37, count 0 2006.173.20:13:21.59#ibcon#read 6, iclass 37, count 0 2006.173.20:13:21.59#ibcon#end of sib2, iclass 37, count 0 2006.173.20:13:21.59#ibcon#*after write, iclass 37, count 0 2006.173.20:13:21.59#ibcon#*before return 0, iclass 37, count 0 2006.173.20:13:21.59#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.20:13:21.59#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.20:13:21.59#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.20:13:21.59#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.20:13:21.59$vck44/vb=6,4 2006.173.20:13:21.59#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.20:13:21.59#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.20:13:21.59#ibcon#ireg 11 cls_cnt 2 2006.173.20:13:21.59#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.20:13:21.65#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.20:13:21.65#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.20:13:21.65#ibcon#enter wrdev, iclass 39, count 2 2006.173.20:13:21.65#ibcon#first serial, iclass 39, count 2 2006.173.20:13:21.65#ibcon#enter sib2, iclass 39, count 2 2006.173.20:13:21.65#ibcon#flushed, iclass 39, count 2 2006.173.20:13:21.65#ibcon#about to write, iclass 39, count 2 2006.173.20:13:21.65#ibcon#wrote, iclass 39, count 2 2006.173.20:13:21.65#ibcon#about to read 3, iclass 39, count 2 2006.173.20:13:21.67#ibcon#read 3, iclass 39, count 2 2006.173.20:13:21.67#ibcon#about to read 4, iclass 39, count 2 2006.173.20:13:21.67#ibcon#read 4, iclass 39, count 2 2006.173.20:13:21.67#ibcon#about to read 5, iclass 39, count 2 2006.173.20:13:21.67#ibcon#read 5, iclass 39, count 2 2006.173.20:13:21.67#ibcon#about to read 6, iclass 39, count 2 2006.173.20:13:21.67#ibcon#read 6, iclass 39, count 2 2006.173.20:13:21.67#ibcon#end of sib2, iclass 39, count 2 2006.173.20:13:21.67#ibcon#*mode == 0, iclass 39, count 2 2006.173.20:13:21.67#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.20:13:21.67#ibcon#[27=AT06-04\r\n] 2006.173.20:13:21.67#ibcon#*before write, iclass 39, count 2 2006.173.20:13:21.67#ibcon#enter sib2, iclass 39, count 2 2006.173.20:13:21.67#ibcon#flushed, iclass 39, count 2 2006.173.20:13:21.67#ibcon#about to write, iclass 39, count 2 2006.173.20:13:21.67#ibcon#wrote, iclass 39, count 2 2006.173.20:13:21.67#ibcon#about to read 3, iclass 39, count 2 2006.173.20:13:21.70#ibcon#read 3, iclass 39, count 2 2006.173.20:13:21.70#ibcon#about to read 4, iclass 39, count 2 2006.173.20:13:21.70#ibcon#read 4, iclass 39, count 2 2006.173.20:13:21.70#ibcon#about to read 5, iclass 39, count 2 2006.173.20:13:21.70#ibcon#read 5, iclass 39, count 2 2006.173.20:13:21.70#ibcon#about to read 6, iclass 39, count 2 2006.173.20:13:21.70#ibcon#read 6, iclass 39, count 2 2006.173.20:13:21.70#ibcon#end of sib2, iclass 39, count 2 2006.173.20:13:21.70#ibcon#*after write, iclass 39, count 2 2006.173.20:13:21.70#ibcon#*before return 0, iclass 39, count 2 2006.173.20:13:21.70#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.20:13:21.70#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.20:13:21.70#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.20:13:21.70#ibcon#ireg 7 cls_cnt 0 2006.173.20:13:21.70#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.20:13:21.82#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.20:13:21.82#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.20:13:21.82#ibcon#enter wrdev, iclass 39, count 0 2006.173.20:13:21.82#ibcon#first serial, iclass 39, count 0 2006.173.20:13:21.82#ibcon#enter sib2, iclass 39, count 0 2006.173.20:13:21.82#ibcon#flushed, iclass 39, count 0 2006.173.20:13:21.82#ibcon#about to write, iclass 39, count 0 2006.173.20:13:21.82#ibcon#wrote, iclass 39, count 0 2006.173.20:13:21.82#ibcon#about to read 3, iclass 39, count 0 2006.173.20:13:21.84#ibcon#read 3, iclass 39, count 0 2006.173.20:13:21.84#ibcon#about to read 4, iclass 39, count 0 2006.173.20:13:21.84#ibcon#read 4, iclass 39, count 0 2006.173.20:13:21.84#ibcon#about to read 5, iclass 39, count 0 2006.173.20:13:21.84#ibcon#read 5, iclass 39, count 0 2006.173.20:13:21.84#ibcon#about to read 6, iclass 39, count 0 2006.173.20:13:21.84#ibcon#read 6, iclass 39, count 0 2006.173.20:13:21.84#ibcon#end of sib2, iclass 39, count 0 2006.173.20:13:21.84#ibcon#*mode == 0, iclass 39, count 0 2006.173.20:13:21.84#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.20:13:21.84#ibcon#[27=USB\r\n] 2006.173.20:13:21.84#ibcon#*before write, iclass 39, count 0 2006.173.20:13:21.84#ibcon#enter sib2, iclass 39, count 0 2006.173.20:13:21.84#ibcon#flushed, iclass 39, count 0 2006.173.20:13:21.84#ibcon#about to write, iclass 39, count 0 2006.173.20:13:21.84#ibcon#wrote, iclass 39, count 0 2006.173.20:13:21.84#ibcon#about to read 3, iclass 39, count 0 2006.173.20:13:21.87#ibcon#read 3, iclass 39, count 0 2006.173.20:13:21.87#ibcon#about to read 4, iclass 39, count 0 2006.173.20:13:21.87#ibcon#read 4, iclass 39, count 0 2006.173.20:13:21.87#ibcon#about to read 5, iclass 39, count 0 2006.173.20:13:21.87#ibcon#read 5, iclass 39, count 0 2006.173.20:13:21.87#ibcon#about to read 6, iclass 39, count 0 2006.173.20:13:21.87#ibcon#read 6, iclass 39, count 0 2006.173.20:13:21.87#ibcon#end of sib2, iclass 39, count 0 2006.173.20:13:21.87#ibcon#*after write, iclass 39, count 0 2006.173.20:13:21.87#ibcon#*before return 0, iclass 39, count 0 2006.173.20:13:21.87#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.20:13:21.87#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.20:13:21.87#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.20:13:21.87#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.20:13:21.87$vck44/vblo=7,734.99 2006.173.20:13:21.87#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.20:13:21.87#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.20:13:21.87#ibcon#ireg 17 cls_cnt 0 2006.173.20:13:21.87#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.20:13:21.87#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.20:13:21.87#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.20:13:21.87#ibcon#enter wrdev, iclass 3, count 0 2006.173.20:13:21.87#ibcon#first serial, iclass 3, count 0 2006.173.20:13:21.87#ibcon#enter sib2, iclass 3, count 0 2006.173.20:13:21.87#ibcon#flushed, iclass 3, count 0 2006.173.20:13:21.87#ibcon#about to write, iclass 3, count 0 2006.173.20:13:21.87#ibcon#wrote, iclass 3, count 0 2006.173.20:13:21.87#ibcon#about to read 3, iclass 3, count 0 2006.173.20:13:21.89#ibcon#read 3, iclass 3, count 0 2006.173.20:13:21.89#ibcon#about to read 4, iclass 3, count 0 2006.173.20:13:21.89#ibcon#read 4, iclass 3, count 0 2006.173.20:13:21.89#ibcon#about to read 5, iclass 3, count 0 2006.173.20:13:21.89#ibcon#read 5, iclass 3, count 0 2006.173.20:13:21.89#ibcon#about to read 6, iclass 3, count 0 2006.173.20:13:21.89#ibcon#read 6, iclass 3, count 0 2006.173.20:13:21.89#ibcon#end of sib2, iclass 3, count 0 2006.173.20:13:21.89#ibcon#*mode == 0, iclass 3, count 0 2006.173.20:13:21.89#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.20:13:21.89#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.20:13:21.89#ibcon#*before write, iclass 3, count 0 2006.173.20:13:21.89#ibcon#enter sib2, iclass 3, count 0 2006.173.20:13:21.89#ibcon#flushed, iclass 3, count 0 2006.173.20:13:21.89#ibcon#about to write, iclass 3, count 0 2006.173.20:13:21.89#ibcon#wrote, iclass 3, count 0 2006.173.20:13:21.89#ibcon#about to read 3, iclass 3, count 0 2006.173.20:13:21.93#ibcon#read 3, iclass 3, count 0 2006.173.20:13:21.93#ibcon#about to read 4, iclass 3, count 0 2006.173.20:13:21.93#ibcon#read 4, iclass 3, count 0 2006.173.20:13:21.93#ibcon#about to read 5, iclass 3, count 0 2006.173.20:13:21.93#ibcon#read 5, iclass 3, count 0 2006.173.20:13:21.93#ibcon#about to read 6, iclass 3, count 0 2006.173.20:13:21.93#ibcon#read 6, iclass 3, count 0 2006.173.20:13:21.93#ibcon#end of sib2, iclass 3, count 0 2006.173.20:13:21.93#ibcon#*after write, iclass 3, count 0 2006.173.20:13:21.93#ibcon#*before return 0, iclass 3, count 0 2006.173.20:13:21.93#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.20:13:21.93#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.20:13:21.93#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.20:13:21.93#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.20:13:21.93$vck44/vb=7,4 2006.173.20:13:21.93#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.20:13:21.93#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.20:13:21.93#ibcon#ireg 11 cls_cnt 2 2006.173.20:13:21.93#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.20:13:21.99#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.20:13:21.99#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.20:13:21.99#ibcon#enter wrdev, iclass 5, count 2 2006.173.20:13:21.99#ibcon#first serial, iclass 5, count 2 2006.173.20:13:21.99#ibcon#enter sib2, iclass 5, count 2 2006.173.20:13:21.99#ibcon#flushed, iclass 5, count 2 2006.173.20:13:21.99#ibcon#about to write, iclass 5, count 2 2006.173.20:13:21.99#ibcon#wrote, iclass 5, count 2 2006.173.20:13:21.99#ibcon#about to read 3, iclass 5, count 2 2006.173.20:13:22.01#ibcon#read 3, iclass 5, count 2 2006.173.20:13:22.01#ibcon#about to read 4, iclass 5, count 2 2006.173.20:13:22.01#ibcon#read 4, iclass 5, count 2 2006.173.20:13:22.01#ibcon#about to read 5, iclass 5, count 2 2006.173.20:13:22.01#ibcon#read 5, iclass 5, count 2 2006.173.20:13:22.01#ibcon#about to read 6, iclass 5, count 2 2006.173.20:13:22.01#ibcon#read 6, iclass 5, count 2 2006.173.20:13:22.01#ibcon#end of sib2, iclass 5, count 2 2006.173.20:13:22.01#ibcon#*mode == 0, iclass 5, count 2 2006.173.20:13:22.01#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.20:13:22.01#ibcon#[27=AT07-04\r\n] 2006.173.20:13:22.01#ibcon#*before write, iclass 5, count 2 2006.173.20:13:22.01#ibcon#enter sib2, iclass 5, count 2 2006.173.20:13:22.01#ibcon#flushed, iclass 5, count 2 2006.173.20:13:22.01#ibcon#about to write, iclass 5, count 2 2006.173.20:13:22.01#ibcon#wrote, iclass 5, count 2 2006.173.20:13:22.01#ibcon#about to read 3, iclass 5, count 2 2006.173.20:13:22.04#ibcon#read 3, iclass 5, count 2 2006.173.20:13:22.04#ibcon#about to read 4, iclass 5, count 2 2006.173.20:13:22.04#ibcon#read 4, iclass 5, count 2 2006.173.20:13:22.04#ibcon#about to read 5, iclass 5, count 2 2006.173.20:13:22.04#ibcon#read 5, iclass 5, count 2 2006.173.20:13:22.04#ibcon#about to read 6, iclass 5, count 2 2006.173.20:13:22.04#ibcon#read 6, iclass 5, count 2 2006.173.20:13:22.04#ibcon#end of sib2, iclass 5, count 2 2006.173.20:13:22.04#ibcon#*after write, iclass 5, count 2 2006.173.20:13:22.04#ibcon#*before return 0, iclass 5, count 2 2006.173.20:13:22.04#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.20:13:22.04#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.20:13:22.04#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.20:13:22.04#ibcon#ireg 7 cls_cnt 0 2006.173.20:13:22.04#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.20:13:22.16#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.20:13:22.16#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.20:13:22.16#ibcon#enter wrdev, iclass 5, count 0 2006.173.20:13:22.16#ibcon#first serial, iclass 5, count 0 2006.173.20:13:22.16#ibcon#enter sib2, iclass 5, count 0 2006.173.20:13:22.16#ibcon#flushed, iclass 5, count 0 2006.173.20:13:22.16#ibcon#about to write, iclass 5, count 0 2006.173.20:13:22.16#ibcon#wrote, iclass 5, count 0 2006.173.20:13:22.16#ibcon#about to read 3, iclass 5, count 0 2006.173.20:13:22.18#ibcon#read 3, iclass 5, count 0 2006.173.20:13:22.18#ibcon#about to read 4, iclass 5, count 0 2006.173.20:13:22.18#ibcon#read 4, iclass 5, count 0 2006.173.20:13:22.18#ibcon#about to read 5, iclass 5, count 0 2006.173.20:13:22.18#ibcon#read 5, iclass 5, count 0 2006.173.20:13:22.18#ibcon#about to read 6, iclass 5, count 0 2006.173.20:13:22.18#ibcon#read 6, iclass 5, count 0 2006.173.20:13:22.18#ibcon#end of sib2, iclass 5, count 0 2006.173.20:13:22.18#ibcon#*mode == 0, iclass 5, count 0 2006.173.20:13:22.18#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.20:13:22.18#ibcon#[27=USB\r\n] 2006.173.20:13:22.18#ibcon#*before write, iclass 5, count 0 2006.173.20:13:22.18#ibcon#enter sib2, iclass 5, count 0 2006.173.20:13:22.18#ibcon#flushed, iclass 5, count 0 2006.173.20:13:22.18#ibcon#about to write, iclass 5, count 0 2006.173.20:13:22.18#ibcon#wrote, iclass 5, count 0 2006.173.20:13:22.18#ibcon#about to read 3, iclass 5, count 0 2006.173.20:13:22.21#ibcon#read 3, iclass 5, count 0 2006.173.20:13:22.21#ibcon#about to read 4, iclass 5, count 0 2006.173.20:13:22.21#ibcon#read 4, iclass 5, count 0 2006.173.20:13:22.21#ibcon#about to read 5, iclass 5, count 0 2006.173.20:13:22.21#ibcon#read 5, iclass 5, count 0 2006.173.20:13:22.21#ibcon#about to read 6, iclass 5, count 0 2006.173.20:13:22.21#ibcon#read 6, iclass 5, count 0 2006.173.20:13:22.21#ibcon#end of sib2, iclass 5, count 0 2006.173.20:13:22.21#ibcon#*after write, iclass 5, count 0 2006.173.20:13:22.21#ibcon#*before return 0, iclass 5, count 0 2006.173.20:13:22.21#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.20:13:22.21#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.20:13:22.21#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.20:13:22.21#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.20:13:22.21$vck44/vblo=8,744.99 2006.173.20:13:22.21#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.20:13:22.21#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.20:13:22.21#ibcon#ireg 17 cls_cnt 0 2006.173.20:13:22.21#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.20:13:22.21#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.20:13:22.21#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.20:13:22.21#ibcon#enter wrdev, iclass 7, count 0 2006.173.20:13:22.21#ibcon#first serial, iclass 7, count 0 2006.173.20:13:22.21#ibcon#enter sib2, iclass 7, count 0 2006.173.20:13:22.21#ibcon#flushed, iclass 7, count 0 2006.173.20:13:22.21#ibcon#about to write, iclass 7, count 0 2006.173.20:13:22.21#ibcon#wrote, iclass 7, count 0 2006.173.20:13:22.21#ibcon#about to read 3, iclass 7, count 0 2006.173.20:13:22.23#ibcon#read 3, iclass 7, count 0 2006.173.20:13:22.23#ibcon#about to read 4, iclass 7, count 0 2006.173.20:13:22.23#ibcon#read 4, iclass 7, count 0 2006.173.20:13:22.23#ibcon#about to read 5, iclass 7, count 0 2006.173.20:13:22.23#ibcon#read 5, iclass 7, count 0 2006.173.20:13:22.23#ibcon#about to read 6, iclass 7, count 0 2006.173.20:13:22.23#ibcon#read 6, iclass 7, count 0 2006.173.20:13:22.23#ibcon#end of sib2, iclass 7, count 0 2006.173.20:13:22.23#ibcon#*mode == 0, iclass 7, count 0 2006.173.20:13:22.23#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.20:13:22.23#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.20:13:22.23#ibcon#*before write, iclass 7, count 0 2006.173.20:13:22.23#ibcon#enter sib2, iclass 7, count 0 2006.173.20:13:22.23#ibcon#flushed, iclass 7, count 0 2006.173.20:13:22.23#ibcon#about to write, iclass 7, count 0 2006.173.20:13:22.23#ibcon#wrote, iclass 7, count 0 2006.173.20:13:22.23#ibcon#about to read 3, iclass 7, count 0 2006.173.20:13:22.27#ibcon#read 3, iclass 7, count 0 2006.173.20:13:22.27#ibcon#about to read 4, iclass 7, count 0 2006.173.20:13:22.27#ibcon#read 4, iclass 7, count 0 2006.173.20:13:22.27#ibcon#about to read 5, iclass 7, count 0 2006.173.20:13:22.27#ibcon#read 5, iclass 7, count 0 2006.173.20:13:22.27#ibcon#about to read 6, iclass 7, count 0 2006.173.20:13:22.27#ibcon#read 6, iclass 7, count 0 2006.173.20:13:22.27#ibcon#end of sib2, iclass 7, count 0 2006.173.20:13:22.27#ibcon#*after write, iclass 7, count 0 2006.173.20:13:22.27#ibcon#*before return 0, iclass 7, count 0 2006.173.20:13:22.27#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.20:13:22.27#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.20:13:22.27#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.20:13:22.27#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.20:13:22.27$vck44/vb=8,4 2006.173.20:13:22.27#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.20:13:22.27#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.20:13:22.27#ibcon#ireg 11 cls_cnt 2 2006.173.20:13:22.27#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.20:13:22.33#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.20:13:22.33#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.20:13:22.33#ibcon#enter wrdev, iclass 11, count 2 2006.173.20:13:22.33#ibcon#first serial, iclass 11, count 2 2006.173.20:13:22.33#ibcon#enter sib2, iclass 11, count 2 2006.173.20:13:22.33#ibcon#flushed, iclass 11, count 2 2006.173.20:13:22.33#ibcon#about to write, iclass 11, count 2 2006.173.20:13:22.33#ibcon#wrote, iclass 11, count 2 2006.173.20:13:22.33#ibcon#about to read 3, iclass 11, count 2 2006.173.20:13:22.35#ibcon#read 3, iclass 11, count 2 2006.173.20:13:22.35#ibcon#about to read 4, iclass 11, count 2 2006.173.20:13:22.35#ibcon#read 4, iclass 11, count 2 2006.173.20:13:22.35#ibcon#about to read 5, iclass 11, count 2 2006.173.20:13:22.35#ibcon#read 5, iclass 11, count 2 2006.173.20:13:22.35#ibcon#about to read 6, iclass 11, count 2 2006.173.20:13:22.35#ibcon#read 6, iclass 11, count 2 2006.173.20:13:22.35#ibcon#end of sib2, iclass 11, count 2 2006.173.20:13:22.35#ibcon#*mode == 0, iclass 11, count 2 2006.173.20:13:22.35#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.20:13:22.35#ibcon#[27=AT08-04\r\n] 2006.173.20:13:22.35#ibcon#*before write, iclass 11, count 2 2006.173.20:13:22.35#ibcon#enter sib2, iclass 11, count 2 2006.173.20:13:22.35#ibcon#flushed, iclass 11, count 2 2006.173.20:13:22.35#ibcon#about to write, iclass 11, count 2 2006.173.20:13:22.35#ibcon#wrote, iclass 11, count 2 2006.173.20:13:22.35#ibcon#about to read 3, iclass 11, count 2 2006.173.20:13:22.38#ibcon#read 3, iclass 11, count 2 2006.173.20:13:22.38#ibcon#about to read 4, iclass 11, count 2 2006.173.20:13:22.38#ibcon#read 4, iclass 11, count 2 2006.173.20:13:22.38#ibcon#about to read 5, iclass 11, count 2 2006.173.20:13:22.38#ibcon#read 5, iclass 11, count 2 2006.173.20:13:22.38#ibcon#about to read 6, iclass 11, count 2 2006.173.20:13:22.38#ibcon#read 6, iclass 11, count 2 2006.173.20:13:22.38#ibcon#end of sib2, iclass 11, count 2 2006.173.20:13:22.38#ibcon#*after write, iclass 11, count 2 2006.173.20:13:22.38#ibcon#*before return 0, iclass 11, count 2 2006.173.20:13:22.38#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.20:13:22.38#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.20:13:22.38#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.20:13:22.38#ibcon#ireg 7 cls_cnt 0 2006.173.20:13:22.38#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.20:13:22.50#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.20:13:22.50#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.20:13:22.50#ibcon#enter wrdev, iclass 11, count 0 2006.173.20:13:22.50#ibcon#first serial, iclass 11, count 0 2006.173.20:13:22.50#ibcon#enter sib2, iclass 11, count 0 2006.173.20:13:22.50#ibcon#flushed, iclass 11, count 0 2006.173.20:13:22.50#ibcon#about to write, iclass 11, count 0 2006.173.20:13:22.50#ibcon#wrote, iclass 11, count 0 2006.173.20:13:22.50#ibcon#about to read 3, iclass 11, count 0 2006.173.20:13:22.52#ibcon#read 3, iclass 11, count 0 2006.173.20:13:22.52#ibcon#about to read 4, iclass 11, count 0 2006.173.20:13:22.52#ibcon#read 4, iclass 11, count 0 2006.173.20:13:22.52#ibcon#about to read 5, iclass 11, count 0 2006.173.20:13:22.52#ibcon#read 5, iclass 11, count 0 2006.173.20:13:22.52#ibcon#about to read 6, iclass 11, count 0 2006.173.20:13:22.52#ibcon#read 6, iclass 11, count 0 2006.173.20:13:22.52#ibcon#end of sib2, iclass 11, count 0 2006.173.20:13:22.52#ibcon#*mode == 0, iclass 11, count 0 2006.173.20:13:22.52#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.20:13:22.52#ibcon#[27=USB\r\n] 2006.173.20:13:22.52#ibcon#*before write, iclass 11, count 0 2006.173.20:13:22.52#ibcon#enter sib2, iclass 11, count 0 2006.173.20:13:22.52#ibcon#flushed, iclass 11, count 0 2006.173.20:13:22.52#ibcon#about to write, iclass 11, count 0 2006.173.20:13:22.52#ibcon#wrote, iclass 11, count 0 2006.173.20:13:22.52#ibcon#about to read 3, iclass 11, count 0 2006.173.20:13:22.55#ibcon#read 3, iclass 11, count 0 2006.173.20:13:22.55#ibcon#about to read 4, iclass 11, count 0 2006.173.20:13:22.55#ibcon#read 4, iclass 11, count 0 2006.173.20:13:22.55#ibcon#about to read 5, iclass 11, count 0 2006.173.20:13:22.55#ibcon#read 5, iclass 11, count 0 2006.173.20:13:22.55#ibcon#about to read 6, iclass 11, count 0 2006.173.20:13:22.55#ibcon#read 6, iclass 11, count 0 2006.173.20:13:22.55#ibcon#end of sib2, iclass 11, count 0 2006.173.20:13:22.55#ibcon#*after write, iclass 11, count 0 2006.173.20:13:22.55#ibcon#*before return 0, iclass 11, count 0 2006.173.20:13:22.55#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.20:13:22.55#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.20:13:22.55#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.20:13:22.55#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.20:13:22.55$vck44/vabw=wide 2006.173.20:13:22.55#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.20:13:22.55#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.20:13:22.55#ibcon#ireg 8 cls_cnt 0 2006.173.20:13:22.55#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.20:13:22.55#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.20:13:22.55#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.20:13:22.55#ibcon#enter wrdev, iclass 13, count 0 2006.173.20:13:22.55#ibcon#first serial, iclass 13, count 0 2006.173.20:13:22.55#ibcon#enter sib2, iclass 13, count 0 2006.173.20:13:22.55#ibcon#flushed, iclass 13, count 0 2006.173.20:13:22.55#ibcon#about to write, iclass 13, count 0 2006.173.20:13:22.55#ibcon#wrote, iclass 13, count 0 2006.173.20:13:22.55#ibcon#about to read 3, iclass 13, count 0 2006.173.20:13:22.57#ibcon#read 3, iclass 13, count 0 2006.173.20:13:22.57#ibcon#about to read 4, iclass 13, count 0 2006.173.20:13:22.57#ibcon#read 4, iclass 13, count 0 2006.173.20:13:22.57#ibcon#about to read 5, iclass 13, count 0 2006.173.20:13:22.57#ibcon#read 5, iclass 13, count 0 2006.173.20:13:22.57#ibcon#about to read 6, iclass 13, count 0 2006.173.20:13:22.57#ibcon#read 6, iclass 13, count 0 2006.173.20:13:22.57#ibcon#end of sib2, iclass 13, count 0 2006.173.20:13:22.57#ibcon#*mode == 0, iclass 13, count 0 2006.173.20:13:22.57#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.20:13:22.57#ibcon#[25=BW32\r\n] 2006.173.20:13:22.57#ibcon#*before write, iclass 13, count 0 2006.173.20:13:22.57#ibcon#enter sib2, iclass 13, count 0 2006.173.20:13:22.57#ibcon#flushed, iclass 13, count 0 2006.173.20:13:22.57#ibcon#about to write, iclass 13, count 0 2006.173.20:13:22.57#ibcon#wrote, iclass 13, count 0 2006.173.20:13:22.57#ibcon#about to read 3, iclass 13, count 0 2006.173.20:13:22.60#ibcon#read 3, iclass 13, count 0 2006.173.20:13:22.60#ibcon#about to read 4, iclass 13, count 0 2006.173.20:13:22.60#ibcon#read 4, iclass 13, count 0 2006.173.20:13:22.60#ibcon#about to read 5, iclass 13, count 0 2006.173.20:13:22.60#ibcon#read 5, iclass 13, count 0 2006.173.20:13:22.60#ibcon#about to read 6, iclass 13, count 0 2006.173.20:13:22.60#ibcon#read 6, iclass 13, count 0 2006.173.20:13:22.60#ibcon#end of sib2, iclass 13, count 0 2006.173.20:13:22.60#ibcon#*after write, iclass 13, count 0 2006.173.20:13:22.60#ibcon#*before return 0, iclass 13, count 0 2006.173.20:13:22.60#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.20:13:22.60#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.20:13:22.60#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.20:13:22.60#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.20:13:22.60$vck44/vbbw=wide 2006.173.20:13:22.60#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.20:13:22.60#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.20:13:22.60#ibcon#ireg 8 cls_cnt 0 2006.173.20:13:22.60#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.20:13:22.67#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.20:13:22.67#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.20:13:22.67#ibcon#enter wrdev, iclass 15, count 0 2006.173.20:13:22.67#ibcon#first serial, iclass 15, count 0 2006.173.20:13:22.67#ibcon#enter sib2, iclass 15, count 0 2006.173.20:13:22.67#ibcon#flushed, iclass 15, count 0 2006.173.20:13:22.67#ibcon#about to write, iclass 15, count 0 2006.173.20:13:22.67#ibcon#wrote, iclass 15, count 0 2006.173.20:13:22.67#ibcon#about to read 3, iclass 15, count 0 2006.173.20:13:22.69#ibcon#read 3, iclass 15, count 0 2006.173.20:13:22.69#ibcon#about to read 4, iclass 15, count 0 2006.173.20:13:22.69#ibcon#read 4, iclass 15, count 0 2006.173.20:13:22.69#ibcon#about to read 5, iclass 15, count 0 2006.173.20:13:22.69#ibcon#read 5, iclass 15, count 0 2006.173.20:13:22.69#ibcon#about to read 6, iclass 15, count 0 2006.173.20:13:22.69#ibcon#read 6, iclass 15, count 0 2006.173.20:13:22.69#ibcon#end of sib2, iclass 15, count 0 2006.173.20:13:22.69#ibcon#*mode == 0, iclass 15, count 0 2006.173.20:13:22.69#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.20:13:22.69#ibcon#[27=BW32\r\n] 2006.173.20:13:22.69#ibcon#*before write, iclass 15, count 0 2006.173.20:13:22.69#ibcon#enter sib2, iclass 15, count 0 2006.173.20:13:22.69#ibcon#flushed, iclass 15, count 0 2006.173.20:13:22.69#ibcon#about to write, iclass 15, count 0 2006.173.20:13:22.69#ibcon#wrote, iclass 15, count 0 2006.173.20:13:22.69#ibcon#about to read 3, iclass 15, count 0 2006.173.20:13:22.72#ibcon#read 3, iclass 15, count 0 2006.173.20:13:22.72#ibcon#about to read 4, iclass 15, count 0 2006.173.20:13:22.72#ibcon#read 4, iclass 15, count 0 2006.173.20:13:22.72#ibcon#about to read 5, iclass 15, count 0 2006.173.20:13:22.72#ibcon#read 5, iclass 15, count 0 2006.173.20:13:22.72#ibcon#about to read 6, iclass 15, count 0 2006.173.20:13:22.72#ibcon#read 6, iclass 15, count 0 2006.173.20:13:22.72#ibcon#end of sib2, iclass 15, count 0 2006.173.20:13:22.72#ibcon#*after write, iclass 15, count 0 2006.173.20:13:22.72#ibcon#*before return 0, iclass 15, count 0 2006.173.20:13:22.72#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.20:13:22.72#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.20:13:22.72#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.20:13:22.72#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.20:13:22.72$setupk4/ifdk4 2006.173.20:13:22.72$ifdk4/lo= 2006.173.20:13:22.72$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.20:13:22.72$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.20:13:22.72$ifdk4/patch= 2006.173.20:13:22.72$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.20:13:22.72$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.20:13:22.72$setupk4/!*+20s 2006.173.20:13:30.85#abcon#<5=/07 0.4 0.9 19.571001002.7\r\n> 2006.173.20:13:30.87#abcon#{5=INTERFACE CLEAR} 2006.173.20:13:30.93#abcon#[5=S1D000X0/0*\r\n] 2006.173.20:13:37.22$setupk4/"tpicd 2006.173.20:13:37.22$setupk4/echo=off 2006.173.20:13:37.22$setupk4/xlog=off 2006.173.20:13:37.22:!2006.173.20:16:43 2006.173.20:14:16.14#trakl#Source acquired 2006.173.20:14:16.14#flagr#flagr/antenna,acquired 2006.173.20:16:43.00:preob 2006.173.20:16:44.14/onsource/TRACKING 2006.173.20:16:44.14:!2006.173.20:16:53 2006.173.20:16:53.00:"tape 2006.173.20:16:53.00:"st=record 2006.173.20:16:53.00:data_valid=on 2006.173.20:16:53.00:midob 2006.173.20:16:53.14/onsource/TRACKING 2006.173.20:16:53.14/wx/19.60,1002.8,100 2006.173.20:16:53.29/cable/+6.5185E-03 2006.173.20:16:54.38/va/01,07,usb,yes,35,38 2006.173.20:16:54.38/va/02,06,usb,yes,35,36 2006.173.20:16:54.38/va/03,05,usb,yes,45,47 2006.173.20:16:54.38/va/04,06,usb,yes,36,38 2006.173.20:16:54.38/va/05,04,usb,yes,28,29 2006.173.20:16:54.38/va/06,03,usb,yes,40,39 2006.173.20:16:54.38/va/07,04,usb,yes,32,33 2006.173.20:16:54.38/va/08,04,usb,yes,27,33 2006.173.20:16:54.61/valo/01,524.99,yes,locked 2006.173.20:16:54.61/valo/02,534.99,yes,locked 2006.173.20:16:54.61/valo/03,564.99,yes,locked 2006.173.20:16:54.61/valo/04,624.99,yes,locked 2006.173.20:16:54.61/valo/05,734.99,yes,locked 2006.173.20:16:54.61/valo/06,814.99,yes,locked 2006.173.20:16:54.61/valo/07,864.99,yes,locked 2006.173.20:16:54.61/valo/08,884.99,yes,locked 2006.173.20:16:55.70/vb/01,04,usb,yes,29,27 2006.173.20:16:55.70/vb/02,04,usb,yes,31,31 2006.173.20:16:55.70/vb/03,04,usb,yes,28,31 2006.173.20:16:55.70/vb/04,04,usb,yes,32,31 2006.173.20:16:55.70/vb/05,04,usb,yes,25,27 2006.173.20:16:55.70/vb/06,04,usb,yes,29,26 2006.173.20:16:55.70/vb/07,04,usb,yes,29,29 2006.173.20:16:55.70/vb/08,04,usb,yes,27,30 2006.173.20:16:55.93/vblo/01,629.99,yes,locked 2006.173.20:16:55.93/vblo/02,634.99,yes,locked 2006.173.20:16:55.93/vblo/03,649.99,yes,locked 2006.173.20:16:55.93/vblo/04,679.99,yes,locked 2006.173.20:16:55.93/vblo/05,709.99,yes,locked 2006.173.20:16:55.93/vblo/06,719.99,yes,locked 2006.173.20:16:55.93/vblo/07,734.99,yes,locked 2006.173.20:16:55.93/vblo/08,744.99,yes,locked 2006.173.20:16:56.08/vabw/8 2006.173.20:16:56.23/vbbw/8 2006.173.20:16:56.32/xfe/off,on,15.2 2006.173.20:16:56.70/ifatt/23,28,28,28 2006.173.20:16:57.08/fmout-gps/S +3.88E-07 2006.173.20:16:57.12:!2006.173.20:19:43 2006.173.20:19:43.00:data_valid=off 2006.173.20:19:43.00:"et 2006.173.20:19:43.00:!+3s 2006.173.20:19:46.01:"tape 2006.173.20:19:46.01:postob 2006.173.20:19:46.21/cable/+6.5172E-03 2006.173.20:19:46.21/wx/19.65,1002.9,100 2006.173.20:19:47.08/fmout-gps/S +3.89E-07 2006.173.20:19:47.08:scan_name=173-2022,jd0606,120 2006.173.20:19:47.08:source=2201+315,220314.98,314538.3,2000.0,ccw 2006.173.20:19:48.13#flagr#flagr/antenna,new-source 2006.173.20:19:48.13:checkk5 2006.173.20:19:48.49/chk_autoobs//k5ts1/ autoobs is running! 2006.173.20:19:48.88/chk_autoobs//k5ts2/ autoobs is running! 2006.173.20:19:49.30/chk_autoobs//k5ts3/ autoobs is running! 2006.173.20:19:49.71/chk_autoobs//k5ts4/ autoobs is running! 2006.173.20:19:50.09/chk_obsdata//k5ts1/T1732016??a.dat file size is correct (nominal:680MB, actual:676MB). 2006.173.20:19:50.49/chk_obsdata//k5ts2/T1732016??b.dat file size is correct (nominal:680MB, actual:676MB). 2006.173.20:19:50.87/chk_obsdata//k5ts3/T1732016??c.dat file size is correct (nominal:680MB, actual:676MB). 2006.173.20:19:51.30/chk_obsdata//k5ts4/T1732016??d.dat file size is correct (nominal:680MB, actual:676MB). 2006.173.20:19:52.03/k5log//k5ts1_log_newline 2006.173.20:19:52.74/k5log//k5ts2_log_newline 2006.173.20:19:53.46/k5log//k5ts3_log_newline 2006.173.20:19:54.16/k5log//k5ts4_log_newline 2006.173.20:19:54.19/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.20:19:54.19:setupk4=1 2006.173.20:19:54.19$setupk4/echo=on 2006.173.20:19:54.19$setupk4/pcalon 2006.173.20:19:54.19$pcalon/"no phase cal control is implemented here 2006.173.20:19:54.19$setupk4/"tpicd=stop 2006.173.20:19:54.19$setupk4/"rec=synch_on 2006.173.20:19:54.19$setupk4/"rec_mode=128 2006.173.20:19:54.19$setupk4/!* 2006.173.20:19:54.19$setupk4/recpk4 2006.173.20:19:54.19$recpk4/recpatch= 2006.173.20:19:54.20$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.20:19:54.20$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.20:19:54.20$setupk4/vck44 2006.173.20:19:54.20$vck44/valo=1,524.99 2006.173.20:19:54.20#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.20:19:54.20#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.20:19:54.20#ibcon#ireg 17 cls_cnt 0 2006.173.20:19:54.20#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.20:19:54.20#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.20:19:54.20#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.20:19:54.20#ibcon#enter wrdev, iclass 28, count 0 2006.173.20:19:54.20#ibcon#first serial, iclass 28, count 0 2006.173.20:19:54.20#ibcon#enter sib2, iclass 28, count 0 2006.173.20:19:54.20#ibcon#flushed, iclass 28, count 0 2006.173.20:19:54.20#ibcon#about to write, iclass 28, count 0 2006.173.20:19:54.20#ibcon#wrote, iclass 28, count 0 2006.173.20:19:54.20#ibcon#about to read 3, iclass 28, count 0 2006.173.20:19:54.22#ibcon#read 3, iclass 28, count 0 2006.173.20:19:54.22#ibcon#about to read 4, iclass 28, count 0 2006.173.20:19:54.22#ibcon#read 4, iclass 28, count 0 2006.173.20:19:54.22#ibcon#about to read 5, iclass 28, count 0 2006.173.20:19:54.22#ibcon#read 5, iclass 28, count 0 2006.173.20:19:54.22#ibcon#about to read 6, iclass 28, count 0 2006.173.20:19:54.22#ibcon#read 6, iclass 28, count 0 2006.173.20:19:54.22#ibcon#end of sib2, iclass 28, count 0 2006.173.20:19:54.22#ibcon#*mode == 0, iclass 28, count 0 2006.173.20:19:54.22#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.20:19:54.22#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.20:19:54.22#ibcon#*before write, iclass 28, count 0 2006.173.20:19:54.22#ibcon#enter sib2, iclass 28, count 0 2006.173.20:19:54.22#ibcon#flushed, iclass 28, count 0 2006.173.20:19:54.22#ibcon#about to write, iclass 28, count 0 2006.173.20:19:54.22#ibcon#wrote, iclass 28, count 0 2006.173.20:19:54.22#ibcon#about to read 3, iclass 28, count 0 2006.173.20:19:54.27#ibcon#read 3, iclass 28, count 0 2006.173.20:19:54.27#ibcon#about to read 4, iclass 28, count 0 2006.173.20:19:54.27#ibcon#read 4, iclass 28, count 0 2006.173.20:19:54.27#ibcon#about to read 5, iclass 28, count 0 2006.173.20:19:54.27#ibcon#read 5, iclass 28, count 0 2006.173.20:19:54.27#ibcon#about to read 6, iclass 28, count 0 2006.173.20:19:54.27#ibcon#read 6, iclass 28, count 0 2006.173.20:19:54.27#ibcon#end of sib2, iclass 28, count 0 2006.173.20:19:54.27#ibcon#*after write, iclass 28, count 0 2006.173.20:19:54.27#ibcon#*before return 0, iclass 28, count 0 2006.173.20:19:54.27#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.20:19:54.27#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.20:19:54.27#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.20:19:54.27#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.20:19:54.27$vck44/va=1,7 2006.173.20:19:54.27#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.20:19:54.27#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.20:19:54.27#ibcon#ireg 11 cls_cnt 2 2006.173.20:19:54.27#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.20:19:54.27#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.20:19:54.27#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.20:19:54.27#ibcon#enter wrdev, iclass 30, count 2 2006.173.20:19:54.27#ibcon#first serial, iclass 30, count 2 2006.173.20:19:54.27#ibcon#enter sib2, iclass 30, count 2 2006.173.20:19:54.27#ibcon#flushed, iclass 30, count 2 2006.173.20:19:54.27#ibcon#about to write, iclass 30, count 2 2006.173.20:19:54.27#ibcon#wrote, iclass 30, count 2 2006.173.20:19:54.27#ibcon#about to read 3, iclass 30, count 2 2006.173.20:19:54.29#ibcon#read 3, iclass 30, count 2 2006.173.20:19:54.29#ibcon#about to read 4, iclass 30, count 2 2006.173.20:19:54.29#ibcon#read 4, iclass 30, count 2 2006.173.20:19:54.29#ibcon#about to read 5, iclass 30, count 2 2006.173.20:19:54.29#ibcon#read 5, iclass 30, count 2 2006.173.20:19:54.29#ibcon#about to read 6, iclass 30, count 2 2006.173.20:19:54.29#ibcon#read 6, iclass 30, count 2 2006.173.20:19:54.29#ibcon#end of sib2, iclass 30, count 2 2006.173.20:19:54.29#ibcon#*mode == 0, iclass 30, count 2 2006.173.20:19:54.29#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.20:19:54.29#ibcon#[25=AT01-07\r\n] 2006.173.20:19:54.29#ibcon#*before write, iclass 30, count 2 2006.173.20:19:54.29#ibcon#enter sib2, iclass 30, count 2 2006.173.20:19:54.29#ibcon#flushed, iclass 30, count 2 2006.173.20:19:54.29#ibcon#about to write, iclass 30, count 2 2006.173.20:19:54.29#ibcon#wrote, iclass 30, count 2 2006.173.20:19:54.29#ibcon#about to read 3, iclass 30, count 2 2006.173.20:19:54.32#ibcon#read 3, iclass 30, count 2 2006.173.20:19:54.32#ibcon#about to read 4, iclass 30, count 2 2006.173.20:19:54.32#ibcon#read 4, iclass 30, count 2 2006.173.20:19:54.32#ibcon#about to read 5, iclass 30, count 2 2006.173.20:19:54.32#ibcon#read 5, iclass 30, count 2 2006.173.20:19:54.32#ibcon#about to read 6, iclass 30, count 2 2006.173.20:19:54.32#ibcon#read 6, iclass 30, count 2 2006.173.20:19:54.32#ibcon#end of sib2, iclass 30, count 2 2006.173.20:19:54.32#ibcon#*after write, iclass 30, count 2 2006.173.20:19:54.32#ibcon#*before return 0, iclass 30, count 2 2006.173.20:19:54.32#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.20:19:54.32#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.20:19:54.32#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.20:19:54.32#ibcon#ireg 7 cls_cnt 0 2006.173.20:19:54.32#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.20:19:54.44#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.20:19:54.44#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.20:19:54.44#ibcon#enter wrdev, iclass 30, count 0 2006.173.20:19:54.44#ibcon#first serial, iclass 30, count 0 2006.173.20:19:54.44#ibcon#enter sib2, iclass 30, count 0 2006.173.20:19:54.44#ibcon#flushed, iclass 30, count 0 2006.173.20:19:54.44#ibcon#about to write, iclass 30, count 0 2006.173.20:19:54.44#ibcon#wrote, iclass 30, count 0 2006.173.20:19:54.44#ibcon#about to read 3, iclass 30, count 0 2006.173.20:19:54.46#ibcon#read 3, iclass 30, count 0 2006.173.20:19:54.46#ibcon#about to read 4, iclass 30, count 0 2006.173.20:19:54.46#ibcon#read 4, iclass 30, count 0 2006.173.20:19:54.46#ibcon#about to read 5, iclass 30, count 0 2006.173.20:19:54.46#ibcon#read 5, iclass 30, count 0 2006.173.20:19:54.46#ibcon#about to read 6, iclass 30, count 0 2006.173.20:19:54.46#ibcon#read 6, iclass 30, count 0 2006.173.20:19:54.46#ibcon#end of sib2, iclass 30, count 0 2006.173.20:19:54.46#ibcon#*mode == 0, iclass 30, count 0 2006.173.20:19:54.46#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.20:19:54.46#ibcon#[25=USB\r\n] 2006.173.20:19:54.46#ibcon#*before write, iclass 30, count 0 2006.173.20:19:54.46#ibcon#enter sib2, iclass 30, count 0 2006.173.20:19:54.46#ibcon#flushed, iclass 30, count 0 2006.173.20:19:54.46#ibcon#about to write, iclass 30, count 0 2006.173.20:19:54.46#ibcon#wrote, iclass 30, count 0 2006.173.20:19:54.46#ibcon#about to read 3, iclass 30, count 0 2006.173.20:19:54.49#ibcon#read 3, iclass 30, count 0 2006.173.20:19:54.49#ibcon#about to read 4, iclass 30, count 0 2006.173.20:19:54.49#ibcon#read 4, iclass 30, count 0 2006.173.20:19:54.49#ibcon#about to read 5, iclass 30, count 0 2006.173.20:19:54.49#ibcon#read 5, iclass 30, count 0 2006.173.20:19:54.49#ibcon#about to read 6, iclass 30, count 0 2006.173.20:19:54.49#ibcon#read 6, iclass 30, count 0 2006.173.20:19:54.49#ibcon#end of sib2, iclass 30, count 0 2006.173.20:19:54.49#ibcon#*after write, iclass 30, count 0 2006.173.20:19:54.49#ibcon#*before return 0, iclass 30, count 0 2006.173.20:19:54.49#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.20:19:54.49#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.20:19:54.49#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.20:19:54.49#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.20:19:54.49$vck44/valo=2,534.99 2006.173.20:19:54.49#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.20:19:54.49#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.20:19:54.49#ibcon#ireg 17 cls_cnt 0 2006.173.20:19:54.49#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.20:19:54.49#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.20:19:54.49#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.20:19:54.49#ibcon#enter wrdev, iclass 32, count 0 2006.173.20:19:54.49#ibcon#first serial, iclass 32, count 0 2006.173.20:19:54.49#ibcon#enter sib2, iclass 32, count 0 2006.173.20:19:54.49#ibcon#flushed, iclass 32, count 0 2006.173.20:19:54.49#ibcon#about to write, iclass 32, count 0 2006.173.20:19:54.49#ibcon#wrote, iclass 32, count 0 2006.173.20:19:54.49#ibcon#about to read 3, iclass 32, count 0 2006.173.20:19:54.51#ibcon#read 3, iclass 32, count 0 2006.173.20:19:54.51#ibcon#about to read 4, iclass 32, count 0 2006.173.20:19:54.51#ibcon#read 4, iclass 32, count 0 2006.173.20:19:54.51#ibcon#about to read 5, iclass 32, count 0 2006.173.20:19:54.51#ibcon#read 5, iclass 32, count 0 2006.173.20:19:54.51#ibcon#about to read 6, iclass 32, count 0 2006.173.20:19:54.51#ibcon#read 6, iclass 32, count 0 2006.173.20:19:54.51#ibcon#end of sib2, iclass 32, count 0 2006.173.20:19:54.51#ibcon#*mode == 0, iclass 32, count 0 2006.173.20:19:54.51#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.20:19:54.51#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.20:19:54.51#ibcon#*before write, iclass 32, count 0 2006.173.20:19:54.51#ibcon#enter sib2, iclass 32, count 0 2006.173.20:19:54.51#ibcon#flushed, iclass 32, count 0 2006.173.20:19:54.51#ibcon#about to write, iclass 32, count 0 2006.173.20:19:54.51#ibcon#wrote, iclass 32, count 0 2006.173.20:19:54.51#ibcon#about to read 3, iclass 32, count 0 2006.173.20:19:54.55#ibcon#read 3, iclass 32, count 0 2006.173.20:19:54.55#ibcon#about to read 4, iclass 32, count 0 2006.173.20:19:54.55#ibcon#read 4, iclass 32, count 0 2006.173.20:19:54.55#ibcon#about to read 5, iclass 32, count 0 2006.173.20:19:54.55#ibcon#read 5, iclass 32, count 0 2006.173.20:19:54.55#ibcon#about to read 6, iclass 32, count 0 2006.173.20:19:54.55#ibcon#read 6, iclass 32, count 0 2006.173.20:19:54.55#ibcon#end of sib2, iclass 32, count 0 2006.173.20:19:54.55#ibcon#*after write, iclass 32, count 0 2006.173.20:19:54.55#ibcon#*before return 0, iclass 32, count 0 2006.173.20:19:54.55#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.20:19:54.55#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.20:19:54.55#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.20:19:54.55#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.20:19:54.55$vck44/va=2,6 2006.173.20:19:54.55#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.20:19:54.55#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.20:19:54.55#ibcon#ireg 11 cls_cnt 2 2006.173.20:19:54.55#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.20:19:54.61#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.20:19:54.61#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.20:19:54.61#ibcon#enter wrdev, iclass 34, count 2 2006.173.20:19:54.61#ibcon#first serial, iclass 34, count 2 2006.173.20:19:54.61#ibcon#enter sib2, iclass 34, count 2 2006.173.20:19:54.61#ibcon#flushed, iclass 34, count 2 2006.173.20:19:54.61#ibcon#about to write, iclass 34, count 2 2006.173.20:19:54.61#ibcon#wrote, iclass 34, count 2 2006.173.20:19:54.61#ibcon#about to read 3, iclass 34, count 2 2006.173.20:19:54.63#ibcon#read 3, iclass 34, count 2 2006.173.20:19:54.63#ibcon#about to read 4, iclass 34, count 2 2006.173.20:19:54.63#ibcon#read 4, iclass 34, count 2 2006.173.20:19:54.63#ibcon#about to read 5, iclass 34, count 2 2006.173.20:19:54.63#ibcon#read 5, iclass 34, count 2 2006.173.20:19:54.63#ibcon#about to read 6, iclass 34, count 2 2006.173.20:19:54.63#ibcon#read 6, iclass 34, count 2 2006.173.20:19:54.63#ibcon#end of sib2, iclass 34, count 2 2006.173.20:19:54.63#ibcon#*mode == 0, iclass 34, count 2 2006.173.20:19:54.63#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.20:19:54.63#ibcon#[25=AT02-06\r\n] 2006.173.20:19:54.63#ibcon#*before write, iclass 34, count 2 2006.173.20:19:54.63#ibcon#enter sib2, iclass 34, count 2 2006.173.20:19:54.63#ibcon#flushed, iclass 34, count 2 2006.173.20:19:54.63#ibcon#about to write, iclass 34, count 2 2006.173.20:19:54.63#ibcon#wrote, iclass 34, count 2 2006.173.20:19:54.63#ibcon#about to read 3, iclass 34, count 2 2006.173.20:19:54.66#ibcon#read 3, iclass 34, count 2 2006.173.20:19:54.66#ibcon#about to read 4, iclass 34, count 2 2006.173.20:19:54.66#ibcon#read 4, iclass 34, count 2 2006.173.20:19:54.66#ibcon#about to read 5, iclass 34, count 2 2006.173.20:19:54.66#ibcon#read 5, iclass 34, count 2 2006.173.20:19:54.66#ibcon#about to read 6, iclass 34, count 2 2006.173.20:19:54.66#ibcon#read 6, iclass 34, count 2 2006.173.20:19:54.66#ibcon#end of sib2, iclass 34, count 2 2006.173.20:19:54.66#ibcon#*after write, iclass 34, count 2 2006.173.20:19:54.66#ibcon#*before return 0, iclass 34, count 2 2006.173.20:19:54.66#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.20:19:54.66#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.20:19:54.66#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.20:19:54.66#ibcon#ireg 7 cls_cnt 0 2006.173.20:19:54.66#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.20:19:54.78#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.20:19:54.78#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.20:19:54.78#ibcon#enter wrdev, iclass 34, count 0 2006.173.20:19:54.78#ibcon#first serial, iclass 34, count 0 2006.173.20:19:54.78#ibcon#enter sib2, iclass 34, count 0 2006.173.20:19:54.78#ibcon#flushed, iclass 34, count 0 2006.173.20:19:54.78#ibcon#about to write, iclass 34, count 0 2006.173.20:19:54.78#ibcon#wrote, iclass 34, count 0 2006.173.20:19:54.78#ibcon#about to read 3, iclass 34, count 0 2006.173.20:19:54.80#ibcon#read 3, iclass 34, count 0 2006.173.20:19:54.80#ibcon#about to read 4, iclass 34, count 0 2006.173.20:19:54.80#ibcon#read 4, iclass 34, count 0 2006.173.20:19:54.80#ibcon#about to read 5, iclass 34, count 0 2006.173.20:19:54.80#ibcon#read 5, iclass 34, count 0 2006.173.20:19:54.80#ibcon#about to read 6, iclass 34, count 0 2006.173.20:19:54.80#ibcon#read 6, iclass 34, count 0 2006.173.20:19:54.80#ibcon#end of sib2, iclass 34, count 0 2006.173.20:19:54.80#ibcon#*mode == 0, iclass 34, count 0 2006.173.20:19:54.80#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.20:19:54.80#ibcon#[25=USB\r\n] 2006.173.20:19:54.80#ibcon#*before write, iclass 34, count 0 2006.173.20:19:54.80#ibcon#enter sib2, iclass 34, count 0 2006.173.20:19:54.80#ibcon#flushed, iclass 34, count 0 2006.173.20:19:54.80#ibcon#about to write, iclass 34, count 0 2006.173.20:19:54.80#ibcon#wrote, iclass 34, count 0 2006.173.20:19:54.80#ibcon#about to read 3, iclass 34, count 0 2006.173.20:19:54.83#ibcon#read 3, iclass 34, count 0 2006.173.20:19:54.83#ibcon#about to read 4, iclass 34, count 0 2006.173.20:19:54.83#ibcon#read 4, iclass 34, count 0 2006.173.20:19:54.83#ibcon#about to read 5, iclass 34, count 0 2006.173.20:19:54.83#ibcon#read 5, iclass 34, count 0 2006.173.20:19:54.83#ibcon#about to read 6, iclass 34, count 0 2006.173.20:19:54.83#ibcon#read 6, iclass 34, count 0 2006.173.20:19:54.83#ibcon#end of sib2, iclass 34, count 0 2006.173.20:19:54.83#ibcon#*after write, iclass 34, count 0 2006.173.20:19:54.83#ibcon#*before return 0, iclass 34, count 0 2006.173.20:19:54.83#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.20:19:54.83#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.20:19:54.83#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.20:19:54.83#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.20:19:54.83$vck44/valo=3,564.99 2006.173.20:19:54.83#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.20:19:54.83#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.20:19:54.83#ibcon#ireg 17 cls_cnt 0 2006.173.20:19:54.83#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.20:19:54.83#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.20:19:54.83#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.20:19:54.83#ibcon#enter wrdev, iclass 36, count 0 2006.173.20:19:54.83#ibcon#first serial, iclass 36, count 0 2006.173.20:19:54.83#ibcon#enter sib2, iclass 36, count 0 2006.173.20:19:54.83#ibcon#flushed, iclass 36, count 0 2006.173.20:19:54.83#ibcon#about to write, iclass 36, count 0 2006.173.20:19:54.83#ibcon#wrote, iclass 36, count 0 2006.173.20:19:54.83#ibcon#about to read 3, iclass 36, count 0 2006.173.20:19:54.85#ibcon#read 3, iclass 36, count 0 2006.173.20:19:54.85#ibcon#about to read 4, iclass 36, count 0 2006.173.20:19:54.85#ibcon#read 4, iclass 36, count 0 2006.173.20:19:54.85#ibcon#about to read 5, iclass 36, count 0 2006.173.20:19:54.85#ibcon#read 5, iclass 36, count 0 2006.173.20:19:54.85#ibcon#about to read 6, iclass 36, count 0 2006.173.20:19:54.85#ibcon#read 6, iclass 36, count 0 2006.173.20:19:54.85#ibcon#end of sib2, iclass 36, count 0 2006.173.20:19:54.85#ibcon#*mode == 0, iclass 36, count 0 2006.173.20:19:54.85#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.20:19:54.85#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.20:19:54.85#ibcon#*before write, iclass 36, count 0 2006.173.20:19:54.85#ibcon#enter sib2, iclass 36, count 0 2006.173.20:19:54.85#ibcon#flushed, iclass 36, count 0 2006.173.20:19:54.85#ibcon#about to write, iclass 36, count 0 2006.173.20:19:54.85#ibcon#wrote, iclass 36, count 0 2006.173.20:19:54.85#ibcon#about to read 3, iclass 36, count 0 2006.173.20:19:54.89#ibcon#read 3, iclass 36, count 0 2006.173.20:19:54.89#ibcon#about to read 4, iclass 36, count 0 2006.173.20:19:54.89#ibcon#read 4, iclass 36, count 0 2006.173.20:19:54.89#ibcon#about to read 5, iclass 36, count 0 2006.173.20:19:54.89#ibcon#read 5, iclass 36, count 0 2006.173.20:19:54.89#ibcon#about to read 6, iclass 36, count 0 2006.173.20:19:54.89#ibcon#read 6, iclass 36, count 0 2006.173.20:19:54.89#ibcon#end of sib2, iclass 36, count 0 2006.173.20:19:54.89#ibcon#*after write, iclass 36, count 0 2006.173.20:19:54.89#ibcon#*before return 0, iclass 36, count 0 2006.173.20:19:54.89#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.20:19:54.89#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.20:19:54.89#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.20:19:54.89#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.20:19:54.89$vck44/va=3,5 2006.173.20:19:54.89#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.20:19:54.89#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.20:19:54.89#ibcon#ireg 11 cls_cnt 2 2006.173.20:19:54.89#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.20:19:54.95#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.20:19:54.95#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.20:19:54.95#ibcon#enter wrdev, iclass 38, count 2 2006.173.20:19:54.95#ibcon#first serial, iclass 38, count 2 2006.173.20:19:54.95#ibcon#enter sib2, iclass 38, count 2 2006.173.20:19:54.95#ibcon#flushed, iclass 38, count 2 2006.173.20:19:54.95#ibcon#about to write, iclass 38, count 2 2006.173.20:19:54.95#ibcon#wrote, iclass 38, count 2 2006.173.20:19:54.95#ibcon#about to read 3, iclass 38, count 2 2006.173.20:19:54.97#ibcon#read 3, iclass 38, count 2 2006.173.20:19:54.97#ibcon#about to read 4, iclass 38, count 2 2006.173.20:19:54.97#ibcon#read 4, iclass 38, count 2 2006.173.20:19:54.97#ibcon#about to read 5, iclass 38, count 2 2006.173.20:19:54.97#ibcon#read 5, iclass 38, count 2 2006.173.20:19:54.97#ibcon#about to read 6, iclass 38, count 2 2006.173.20:19:54.97#ibcon#read 6, iclass 38, count 2 2006.173.20:19:54.97#ibcon#end of sib2, iclass 38, count 2 2006.173.20:19:54.97#ibcon#*mode == 0, iclass 38, count 2 2006.173.20:19:54.97#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.20:19:54.97#ibcon#[25=AT03-05\r\n] 2006.173.20:19:54.97#ibcon#*before write, iclass 38, count 2 2006.173.20:19:54.97#ibcon#enter sib2, iclass 38, count 2 2006.173.20:19:54.97#ibcon#flushed, iclass 38, count 2 2006.173.20:19:54.97#ibcon#about to write, iclass 38, count 2 2006.173.20:19:54.97#ibcon#wrote, iclass 38, count 2 2006.173.20:19:54.97#ibcon#about to read 3, iclass 38, count 2 2006.173.20:19:55.00#ibcon#read 3, iclass 38, count 2 2006.173.20:19:55.00#ibcon#about to read 4, iclass 38, count 2 2006.173.20:19:55.00#ibcon#read 4, iclass 38, count 2 2006.173.20:19:55.00#ibcon#about to read 5, iclass 38, count 2 2006.173.20:19:55.00#ibcon#read 5, iclass 38, count 2 2006.173.20:19:55.00#ibcon#about to read 6, iclass 38, count 2 2006.173.20:19:55.00#ibcon#read 6, iclass 38, count 2 2006.173.20:19:55.00#ibcon#end of sib2, iclass 38, count 2 2006.173.20:19:55.00#ibcon#*after write, iclass 38, count 2 2006.173.20:19:55.00#ibcon#*before return 0, iclass 38, count 2 2006.173.20:19:55.00#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.20:19:55.00#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.20:19:55.00#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.20:19:55.00#ibcon#ireg 7 cls_cnt 0 2006.173.20:19:55.00#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.20:19:55.12#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.20:19:55.12#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.20:19:55.12#ibcon#enter wrdev, iclass 38, count 0 2006.173.20:19:55.12#ibcon#first serial, iclass 38, count 0 2006.173.20:19:55.12#ibcon#enter sib2, iclass 38, count 0 2006.173.20:19:55.12#ibcon#flushed, iclass 38, count 0 2006.173.20:19:55.12#ibcon#about to write, iclass 38, count 0 2006.173.20:19:55.12#ibcon#wrote, iclass 38, count 0 2006.173.20:19:55.12#ibcon#about to read 3, iclass 38, count 0 2006.173.20:19:55.14#ibcon#read 3, iclass 38, count 0 2006.173.20:19:55.14#ibcon#about to read 4, iclass 38, count 0 2006.173.20:19:55.14#ibcon#read 4, iclass 38, count 0 2006.173.20:19:55.14#ibcon#about to read 5, iclass 38, count 0 2006.173.20:19:55.14#ibcon#read 5, iclass 38, count 0 2006.173.20:19:55.14#ibcon#about to read 6, iclass 38, count 0 2006.173.20:19:55.14#ibcon#read 6, iclass 38, count 0 2006.173.20:19:55.14#ibcon#end of sib2, iclass 38, count 0 2006.173.20:19:55.14#ibcon#*mode == 0, iclass 38, count 0 2006.173.20:19:55.14#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.20:19:55.14#ibcon#[25=USB\r\n] 2006.173.20:19:55.14#ibcon#*before write, iclass 38, count 0 2006.173.20:19:55.14#ibcon#enter sib2, iclass 38, count 0 2006.173.20:19:55.14#ibcon#flushed, iclass 38, count 0 2006.173.20:19:55.14#ibcon#about to write, iclass 38, count 0 2006.173.20:19:55.14#ibcon#wrote, iclass 38, count 0 2006.173.20:19:55.14#ibcon#about to read 3, iclass 38, count 0 2006.173.20:19:55.17#ibcon#read 3, iclass 38, count 0 2006.173.20:19:55.17#ibcon#about to read 4, iclass 38, count 0 2006.173.20:19:55.17#ibcon#read 4, iclass 38, count 0 2006.173.20:19:55.17#ibcon#about to read 5, iclass 38, count 0 2006.173.20:19:55.17#ibcon#read 5, iclass 38, count 0 2006.173.20:19:55.17#ibcon#about to read 6, iclass 38, count 0 2006.173.20:19:55.17#ibcon#read 6, iclass 38, count 0 2006.173.20:19:55.17#ibcon#end of sib2, iclass 38, count 0 2006.173.20:19:55.17#ibcon#*after write, iclass 38, count 0 2006.173.20:19:55.17#ibcon#*before return 0, iclass 38, count 0 2006.173.20:19:55.17#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.20:19:55.17#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.20:19:55.17#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.20:19:55.17#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.20:19:55.17$vck44/valo=4,624.99 2006.173.20:19:55.17#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.20:19:55.17#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.20:19:55.17#ibcon#ireg 17 cls_cnt 0 2006.173.20:19:55.17#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.20:19:55.17#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.20:19:55.17#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.20:19:55.17#ibcon#enter wrdev, iclass 40, count 0 2006.173.20:19:55.17#ibcon#first serial, iclass 40, count 0 2006.173.20:19:55.17#ibcon#enter sib2, iclass 40, count 0 2006.173.20:19:55.17#ibcon#flushed, iclass 40, count 0 2006.173.20:19:55.17#ibcon#about to write, iclass 40, count 0 2006.173.20:19:55.17#ibcon#wrote, iclass 40, count 0 2006.173.20:19:55.17#ibcon#about to read 3, iclass 40, count 0 2006.173.20:19:55.19#ibcon#read 3, iclass 40, count 0 2006.173.20:19:55.19#ibcon#about to read 4, iclass 40, count 0 2006.173.20:19:55.19#ibcon#read 4, iclass 40, count 0 2006.173.20:19:55.19#ibcon#about to read 5, iclass 40, count 0 2006.173.20:19:55.19#ibcon#read 5, iclass 40, count 0 2006.173.20:19:55.19#ibcon#about to read 6, iclass 40, count 0 2006.173.20:19:55.19#ibcon#read 6, iclass 40, count 0 2006.173.20:19:55.19#ibcon#end of sib2, iclass 40, count 0 2006.173.20:19:55.19#ibcon#*mode == 0, iclass 40, count 0 2006.173.20:19:55.19#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.20:19:55.19#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.20:19:55.19#ibcon#*before write, iclass 40, count 0 2006.173.20:19:55.19#ibcon#enter sib2, iclass 40, count 0 2006.173.20:19:55.19#ibcon#flushed, iclass 40, count 0 2006.173.20:19:55.19#ibcon#about to write, iclass 40, count 0 2006.173.20:19:55.19#ibcon#wrote, iclass 40, count 0 2006.173.20:19:55.19#ibcon#about to read 3, iclass 40, count 0 2006.173.20:19:55.23#ibcon#read 3, iclass 40, count 0 2006.173.20:19:55.23#ibcon#about to read 4, iclass 40, count 0 2006.173.20:19:55.23#ibcon#read 4, iclass 40, count 0 2006.173.20:19:55.23#ibcon#about to read 5, iclass 40, count 0 2006.173.20:19:55.23#ibcon#read 5, iclass 40, count 0 2006.173.20:19:55.23#ibcon#about to read 6, iclass 40, count 0 2006.173.20:19:55.23#ibcon#read 6, iclass 40, count 0 2006.173.20:19:55.23#ibcon#end of sib2, iclass 40, count 0 2006.173.20:19:55.23#ibcon#*after write, iclass 40, count 0 2006.173.20:19:55.23#ibcon#*before return 0, iclass 40, count 0 2006.173.20:19:55.23#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.20:19:55.23#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.20:19:55.23#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.20:19:55.23#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.20:19:55.23$vck44/va=4,6 2006.173.20:19:55.23#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.20:19:55.23#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.20:19:55.23#ibcon#ireg 11 cls_cnt 2 2006.173.20:19:55.23#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.20:19:55.29#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.20:19:55.29#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.20:19:55.29#ibcon#enter wrdev, iclass 4, count 2 2006.173.20:19:55.29#ibcon#first serial, iclass 4, count 2 2006.173.20:19:55.29#ibcon#enter sib2, iclass 4, count 2 2006.173.20:19:55.29#ibcon#flushed, iclass 4, count 2 2006.173.20:19:55.29#ibcon#about to write, iclass 4, count 2 2006.173.20:19:55.29#ibcon#wrote, iclass 4, count 2 2006.173.20:19:55.29#ibcon#about to read 3, iclass 4, count 2 2006.173.20:19:55.31#ibcon#read 3, iclass 4, count 2 2006.173.20:19:55.31#ibcon#about to read 4, iclass 4, count 2 2006.173.20:19:55.31#ibcon#read 4, iclass 4, count 2 2006.173.20:19:55.31#ibcon#about to read 5, iclass 4, count 2 2006.173.20:19:55.31#ibcon#read 5, iclass 4, count 2 2006.173.20:19:55.31#ibcon#about to read 6, iclass 4, count 2 2006.173.20:19:55.31#ibcon#read 6, iclass 4, count 2 2006.173.20:19:55.31#ibcon#end of sib2, iclass 4, count 2 2006.173.20:19:55.31#ibcon#*mode == 0, iclass 4, count 2 2006.173.20:19:55.31#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.20:19:55.31#ibcon#[25=AT04-06\r\n] 2006.173.20:19:55.31#ibcon#*before write, iclass 4, count 2 2006.173.20:19:55.31#ibcon#enter sib2, iclass 4, count 2 2006.173.20:19:55.31#ibcon#flushed, iclass 4, count 2 2006.173.20:19:55.31#ibcon#about to write, iclass 4, count 2 2006.173.20:19:55.31#ibcon#wrote, iclass 4, count 2 2006.173.20:19:55.31#ibcon#about to read 3, iclass 4, count 2 2006.173.20:19:55.34#ibcon#read 3, iclass 4, count 2 2006.173.20:19:55.34#ibcon#about to read 4, iclass 4, count 2 2006.173.20:19:55.34#ibcon#read 4, iclass 4, count 2 2006.173.20:19:55.34#ibcon#about to read 5, iclass 4, count 2 2006.173.20:19:55.34#ibcon#read 5, iclass 4, count 2 2006.173.20:19:55.34#ibcon#about to read 6, iclass 4, count 2 2006.173.20:19:55.34#ibcon#read 6, iclass 4, count 2 2006.173.20:19:55.34#ibcon#end of sib2, iclass 4, count 2 2006.173.20:19:55.34#ibcon#*after write, iclass 4, count 2 2006.173.20:19:55.34#ibcon#*before return 0, iclass 4, count 2 2006.173.20:19:55.34#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.20:19:55.34#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.20:19:55.34#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.20:19:55.34#ibcon#ireg 7 cls_cnt 0 2006.173.20:19:55.34#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.20:19:55.46#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.20:19:55.46#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.20:19:55.46#ibcon#enter wrdev, iclass 4, count 0 2006.173.20:19:55.46#ibcon#first serial, iclass 4, count 0 2006.173.20:19:55.46#ibcon#enter sib2, iclass 4, count 0 2006.173.20:19:55.46#ibcon#flushed, iclass 4, count 0 2006.173.20:19:55.46#ibcon#about to write, iclass 4, count 0 2006.173.20:19:55.46#ibcon#wrote, iclass 4, count 0 2006.173.20:19:55.46#ibcon#about to read 3, iclass 4, count 0 2006.173.20:19:55.48#ibcon#read 3, iclass 4, count 0 2006.173.20:19:55.48#ibcon#about to read 4, iclass 4, count 0 2006.173.20:19:55.48#ibcon#read 4, iclass 4, count 0 2006.173.20:19:55.48#ibcon#about to read 5, iclass 4, count 0 2006.173.20:19:55.48#ibcon#read 5, iclass 4, count 0 2006.173.20:19:55.48#ibcon#about to read 6, iclass 4, count 0 2006.173.20:19:55.48#ibcon#read 6, iclass 4, count 0 2006.173.20:19:55.48#ibcon#end of sib2, iclass 4, count 0 2006.173.20:19:55.48#ibcon#*mode == 0, iclass 4, count 0 2006.173.20:19:55.48#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.20:19:55.48#ibcon#[25=USB\r\n] 2006.173.20:19:55.48#ibcon#*before write, iclass 4, count 0 2006.173.20:19:55.48#ibcon#enter sib2, iclass 4, count 0 2006.173.20:19:55.48#ibcon#flushed, iclass 4, count 0 2006.173.20:19:55.48#ibcon#about to write, iclass 4, count 0 2006.173.20:19:55.48#ibcon#wrote, iclass 4, count 0 2006.173.20:19:55.48#ibcon#about to read 3, iclass 4, count 0 2006.173.20:19:55.51#ibcon#read 3, iclass 4, count 0 2006.173.20:19:55.51#ibcon#about to read 4, iclass 4, count 0 2006.173.20:19:55.51#ibcon#read 4, iclass 4, count 0 2006.173.20:19:55.51#ibcon#about to read 5, iclass 4, count 0 2006.173.20:19:55.51#ibcon#read 5, iclass 4, count 0 2006.173.20:19:55.51#ibcon#about to read 6, iclass 4, count 0 2006.173.20:19:55.51#ibcon#read 6, iclass 4, count 0 2006.173.20:19:55.51#ibcon#end of sib2, iclass 4, count 0 2006.173.20:19:55.51#ibcon#*after write, iclass 4, count 0 2006.173.20:19:55.51#ibcon#*before return 0, iclass 4, count 0 2006.173.20:19:55.51#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.20:19:55.51#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.20:19:55.51#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.20:19:55.51#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.20:19:55.51$vck44/valo=5,734.99 2006.173.20:19:55.51#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.20:19:55.51#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.20:19:55.51#ibcon#ireg 17 cls_cnt 0 2006.173.20:19:55.51#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.20:19:55.51#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.20:19:55.51#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.20:19:55.51#ibcon#enter wrdev, iclass 6, count 0 2006.173.20:19:55.51#ibcon#first serial, iclass 6, count 0 2006.173.20:19:55.51#ibcon#enter sib2, iclass 6, count 0 2006.173.20:19:55.51#ibcon#flushed, iclass 6, count 0 2006.173.20:19:55.51#ibcon#about to write, iclass 6, count 0 2006.173.20:19:55.51#ibcon#wrote, iclass 6, count 0 2006.173.20:19:55.51#ibcon#about to read 3, iclass 6, count 0 2006.173.20:19:55.53#ibcon#read 3, iclass 6, count 0 2006.173.20:19:55.53#ibcon#about to read 4, iclass 6, count 0 2006.173.20:19:55.53#ibcon#read 4, iclass 6, count 0 2006.173.20:19:55.53#ibcon#about to read 5, iclass 6, count 0 2006.173.20:19:55.53#ibcon#read 5, iclass 6, count 0 2006.173.20:19:55.53#ibcon#about to read 6, iclass 6, count 0 2006.173.20:19:55.53#ibcon#read 6, iclass 6, count 0 2006.173.20:19:55.53#ibcon#end of sib2, iclass 6, count 0 2006.173.20:19:55.53#ibcon#*mode == 0, iclass 6, count 0 2006.173.20:19:55.53#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.20:19:55.53#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.20:19:55.53#ibcon#*before write, iclass 6, count 0 2006.173.20:19:55.53#ibcon#enter sib2, iclass 6, count 0 2006.173.20:19:55.53#ibcon#flushed, iclass 6, count 0 2006.173.20:19:55.53#ibcon#about to write, iclass 6, count 0 2006.173.20:19:55.53#ibcon#wrote, iclass 6, count 0 2006.173.20:19:55.53#ibcon#about to read 3, iclass 6, count 0 2006.173.20:19:55.57#ibcon#read 3, iclass 6, count 0 2006.173.20:19:55.57#ibcon#about to read 4, iclass 6, count 0 2006.173.20:19:55.57#ibcon#read 4, iclass 6, count 0 2006.173.20:19:55.57#ibcon#about to read 5, iclass 6, count 0 2006.173.20:19:55.57#ibcon#read 5, iclass 6, count 0 2006.173.20:19:55.57#ibcon#about to read 6, iclass 6, count 0 2006.173.20:19:55.57#ibcon#read 6, iclass 6, count 0 2006.173.20:19:55.57#ibcon#end of sib2, iclass 6, count 0 2006.173.20:19:55.57#ibcon#*after write, iclass 6, count 0 2006.173.20:19:55.57#ibcon#*before return 0, iclass 6, count 0 2006.173.20:19:55.57#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.20:19:55.57#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.20:19:55.57#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.20:19:55.57#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.20:19:55.57$vck44/va=5,4 2006.173.20:19:55.57#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.20:19:55.57#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.20:19:55.57#ibcon#ireg 11 cls_cnt 2 2006.173.20:19:55.57#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.20:19:55.63#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.20:19:55.63#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.20:19:55.63#ibcon#enter wrdev, iclass 10, count 2 2006.173.20:19:55.63#ibcon#first serial, iclass 10, count 2 2006.173.20:19:55.63#ibcon#enter sib2, iclass 10, count 2 2006.173.20:19:55.63#ibcon#flushed, iclass 10, count 2 2006.173.20:19:55.63#ibcon#about to write, iclass 10, count 2 2006.173.20:19:55.63#ibcon#wrote, iclass 10, count 2 2006.173.20:19:55.63#ibcon#about to read 3, iclass 10, count 2 2006.173.20:19:55.65#ibcon#read 3, iclass 10, count 2 2006.173.20:19:55.65#ibcon#about to read 4, iclass 10, count 2 2006.173.20:19:55.65#ibcon#read 4, iclass 10, count 2 2006.173.20:19:55.65#ibcon#about to read 5, iclass 10, count 2 2006.173.20:19:55.65#ibcon#read 5, iclass 10, count 2 2006.173.20:19:55.65#ibcon#about to read 6, iclass 10, count 2 2006.173.20:19:55.65#ibcon#read 6, iclass 10, count 2 2006.173.20:19:55.65#ibcon#end of sib2, iclass 10, count 2 2006.173.20:19:55.65#ibcon#*mode == 0, iclass 10, count 2 2006.173.20:19:55.65#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.20:19:55.65#ibcon#[25=AT05-04\r\n] 2006.173.20:19:55.65#ibcon#*before write, iclass 10, count 2 2006.173.20:19:55.65#ibcon#enter sib2, iclass 10, count 2 2006.173.20:19:55.65#ibcon#flushed, iclass 10, count 2 2006.173.20:19:55.65#ibcon#about to write, iclass 10, count 2 2006.173.20:19:55.65#ibcon#wrote, iclass 10, count 2 2006.173.20:19:55.65#ibcon#about to read 3, iclass 10, count 2 2006.173.20:19:55.68#ibcon#read 3, iclass 10, count 2 2006.173.20:19:55.68#ibcon#about to read 4, iclass 10, count 2 2006.173.20:19:55.68#ibcon#read 4, iclass 10, count 2 2006.173.20:19:55.68#ibcon#about to read 5, iclass 10, count 2 2006.173.20:19:55.68#ibcon#read 5, iclass 10, count 2 2006.173.20:19:55.68#ibcon#about to read 6, iclass 10, count 2 2006.173.20:19:55.68#ibcon#read 6, iclass 10, count 2 2006.173.20:19:55.68#ibcon#end of sib2, iclass 10, count 2 2006.173.20:19:55.68#ibcon#*after write, iclass 10, count 2 2006.173.20:19:55.68#ibcon#*before return 0, iclass 10, count 2 2006.173.20:19:55.68#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.20:19:55.68#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.20:19:55.68#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.20:19:55.68#ibcon#ireg 7 cls_cnt 0 2006.173.20:19:55.68#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.20:19:55.80#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.20:19:55.80#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.20:19:55.80#ibcon#enter wrdev, iclass 10, count 0 2006.173.20:19:55.80#ibcon#first serial, iclass 10, count 0 2006.173.20:19:55.80#ibcon#enter sib2, iclass 10, count 0 2006.173.20:19:55.80#ibcon#flushed, iclass 10, count 0 2006.173.20:19:55.80#ibcon#about to write, iclass 10, count 0 2006.173.20:19:55.80#ibcon#wrote, iclass 10, count 0 2006.173.20:19:55.80#ibcon#about to read 3, iclass 10, count 0 2006.173.20:19:55.82#ibcon#read 3, iclass 10, count 0 2006.173.20:19:55.82#ibcon#about to read 4, iclass 10, count 0 2006.173.20:19:55.82#ibcon#read 4, iclass 10, count 0 2006.173.20:19:55.82#ibcon#about to read 5, iclass 10, count 0 2006.173.20:19:55.82#ibcon#read 5, iclass 10, count 0 2006.173.20:19:55.82#ibcon#about to read 6, iclass 10, count 0 2006.173.20:19:55.82#ibcon#read 6, iclass 10, count 0 2006.173.20:19:55.82#ibcon#end of sib2, iclass 10, count 0 2006.173.20:19:55.82#ibcon#*mode == 0, iclass 10, count 0 2006.173.20:19:55.82#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.20:19:55.82#ibcon#[25=USB\r\n] 2006.173.20:19:55.82#ibcon#*before write, iclass 10, count 0 2006.173.20:19:55.82#ibcon#enter sib2, iclass 10, count 0 2006.173.20:19:55.82#ibcon#flushed, iclass 10, count 0 2006.173.20:19:55.82#ibcon#about to write, iclass 10, count 0 2006.173.20:19:55.82#ibcon#wrote, iclass 10, count 0 2006.173.20:19:55.82#ibcon#about to read 3, iclass 10, count 0 2006.173.20:19:55.85#ibcon#read 3, iclass 10, count 0 2006.173.20:19:55.85#ibcon#about to read 4, iclass 10, count 0 2006.173.20:19:55.85#ibcon#read 4, iclass 10, count 0 2006.173.20:19:55.85#ibcon#about to read 5, iclass 10, count 0 2006.173.20:19:55.85#ibcon#read 5, iclass 10, count 0 2006.173.20:19:55.85#ibcon#about to read 6, iclass 10, count 0 2006.173.20:19:55.85#ibcon#read 6, iclass 10, count 0 2006.173.20:19:55.85#ibcon#end of sib2, iclass 10, count 0 2006.173.20:19:55.85#ibcon#*after write, iclass 10, count 0 2006.173.20:19:55.85#ibcon#*before return 0, iclass 10, count 0 2006.173.20:19:55.85#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.20:19:55.85#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.20:19:55.85#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.20:19:55.85#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.20:19:55.85$vck44/valo=6,814.99 2006.173.20:19:55.85#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.20:19:55.85#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.20:19:55.85#ibcon#ireg 17 cls_cnt 0 2006.173.20:19:55.85#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.20:19:55.85#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.20:19:55.85#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.20:19:55.85#ibcon#enter wrdev, iclass 12, count 0 2006.173.20:19:55.85#ibcon#first serial, iclass 12, count 0 2006.173.20:19:55.85#ibcon#enter sib2, iclass 12, count 0 2006.173.20:19:55.85#ibcon#flushed, iclass 12, count 0 2006.173.20:19:55.85#ibcon#about to write, iclass 12, count 0 2006.173.20:19:55.85#ibcon#wrote, iclass 12, count 0 2006.173.20:19:55.85#ibcon#about to read 3, iclass 12, count 0 2006.173.20:19:55.87#ibcon#read 3, iclass 12, count 0 2006.173.20:19:55.87#ibcon#about to read 4, iclass 12, count 0 2006.173.20:19:55.87#ibcon#read 4, iclass 12, count 0 2006.173.20:19:55.87#ibcon#about to read 5, iclass 12, count 0 2006.173.20:19:55.87#ibcon#read 5, iclass 12, count 0 2006.173.20:19:55.87#ibcon#about to read 6, iclass 12, count 0 2006.173.20:19:55.87#ibcon#read 6, iclass 12, count 0 2006.173.20:19:55.87#ibcon#end of sib2, iclass 12, count 0 2006.173.20:19:55.87#ibcon#*mode == 0, iclass 12, count 0 2006.173.20:19:55.87#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.20:19:55.87#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.20:19:55.87#ibcon#*before write, iclass 12, count 0 2006.173.20:19:55.87#ibcon#enter sib2, iclass 12, count 0 2006.173.20:19:55.87#ibcon#flushed, iclass 12, count 0 2006.173.20:19:55.87#ibcon#about to write, iclass 12, count 0 2006.173.20:19:55.87#ibcon#wrote, iclass 12, count 0 2006.173.20:19:55.87#ibcon#about to read 3, iclass 12, count 0 2006.173.20:19:55.91#ibcon#read 3, iclass 12, count 0 2006.173.20:19:55.91#ibcon#about to read 4, iclass 12, count 0 2006.173.20:19:55.91#ibcon#read 4, iclass 12, count 0 2006.173.20:19:55.91#ibcon#about to read 5, iclass 12, count 0 2006.173.20:19:55.91#ibcon#read 5, iclass 12, count 0 2006.173.20:19:55.91#ibcon#about to read 6, iclass 12, count 0 2006.173.20:19:55.91#ibcon#read 6, iclass 12, count 0 2006.173.20:19:55.91#ibcon#end of sib2, iclass 12, count 0 2006.173.20:19:55.91#ibcon#*after write, iclass 12, count 0 2006.173.20:19:55.91#ibcon#*before return 0, iclass 12, count 0 2006.173.20:19:55.91#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.20:19:55.91#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.20:19:55.91#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.20:19:55.91#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.20:19:55.91$vck44/va=6,3 2006.173.20:19:55.91#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.20:19:55.91#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.20:19:55.91#ibcon#ireg 11 cls_cnt 2 2006.173.20:19:55.91#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.20:19:55.97#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.20:19:55.97#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.20:19:55.97#ibcon#enter wrdev, iclass 14, count 2 2006.173.20:19:55.97#ibcon#first serial, iclass 14, count 2 2006.173.20:19:55.97#ibcon#enter sib2, iclass 14, count 2 2006.173.20:19:55.97#ibcon#flushed, iclass 14, count 2 2006.173.20:19:55.97#ibcon#about to write, iclass 14, count 2 2006.173.20:19:55.97#ibcon#wrote, iclass 14, count 2 2006.173.20:19:55.97#ibcon#about to read 3, iclass 14, count 2 2006.173.20:19:55.99#ibcon#read 3, iclass 14, count 2 2006.173.20:19:55.99#ibcon#about to read 4, iclass 14, count 2 2006.173.20:19:55.99#ibcon#read 4, iclass 14, count 2 2006.173.20:19:55.99#ibcon#about to read 5, iclass 14, count 2 2006.173.20:19:55.99#ibcon#read 5, iclass 14, count 2 2006.173.20:19:55.99#ibcon#about to read 6, iclass 14, count 2 2006.173.20:19:55.99#ibcon#read 6, iclass 14, count 2 2006.173.20:19:55.99#ibcon#end of sib2, iclass 14, count 2 2006.173.20:19:55.99#ibcon#*mode == 0, iclass 14, count 2 2006.173.20:19:55.99#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.20:19:55.99#ibcon#[25=AT06-03\r\n] 2006.173.20:19:55.99#ibcon#*before write, iclass 14, count 2 2006.173.20:19:55.99#ibcon#enter sib2, iclass 14, count 2 2006.173.20:19:55.99#ibcon#flushed, iclass 14, count 2 2006.173.20:19:55.99#ibcon#about to write, iclass 14, count 2 2006.173.20:19:55.99#ibcon#wrote, iclass 14, count 2 2006.173.20:19:55.99#ibcon#about to read 3, iclass 14, count 2 2006.173.20:19:56.02#ibcon#read 3, iclass 14, count 2 2006.173.20:19:56.02#ibcon#about to read 4, iclass 14, count 2 2006.173.20:19:56.02#ibcon#read 4, iclass 14, count 2 2006.173.20:19:56.02#ibcon#about to read 5, iclass 14, count 2 2006.173.20:19:56.02#ibcon#read 5, iclass 14, count 2 2006.173.20:19:56.02#ibcon#about to read 6, iclass 14, count 2 2006.173.20:19:56.02#ibcon#read 6, iclass 14, count 2 2006.173.20:19:56.02#ibcon#end of sib2, iclass 14, count 2 2006.173.20:19:56.02#ibcon#*after write, iclass 14, count 2 2006.173.20:19:56.02#ibcon#*before return 0, iclass 14, count 2 2006.173.20:19:56.02#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.20:19:56.02#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.20:19:56.02#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.20:19:56.02#ibcon#ireg 7 cls_cnt 0 2006.173.20:19:56.02#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.20:19:56.14#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.20:19:56.14#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.20:19:56.14#ibcon#enter wrdev, iclass 14, count 0 2006.173.20:19:56.14#ibcon#first serial, iclass 14, count 0 2006.173.20:19:56.14#ibcon#enter sib2, iclass 14, count 0 2006.173.20:19:56.14#ibcon#flushed, iclass 14, count 0 2006.173.20:19:56.14#ibcon#about to write, iclass 14, count 0 2006.173.20:19:56.14#ibcon#wrote, iclass 14, count 0 2006.173.20:19:56.14#ibcon#about to read 3, iclass 14, count 0 2006.173.20:19:56.16#ibcon#read 3, iclass 14, count 0 2006.173.20:19:56.16#ibcon#about to read 4, iclass 14, count 0 2006.173.20:19:56.16#ibcon#read 4, iclass 14, count 0 2006.173.20:19:56.16#ibcon#about to read 5, iclass 14, count 0 2006.173.20:19:56.16#ibcon#read 5, iclass 14, count 0 2006.173.20:19:56.16#ibcon#about to read 6, iclass 14, count 0 2006.173.20:19:56.16#ibcon#read 6, iclass 14, count 0 2006.173.20:19:56.16#ibcon#end of sib2, iclass 14, count 0 2006.173.20:19:56.16#ibcon#*mode == 0, iclass 14, count 0 2006.173.20:19:56.16#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.20:19:56.16#ibcon#[25=USB\r\n] 2006.173.20:19:56.16#ibcon#*before write, iclass 14, count 0 2006.173.20:19:56.16#ibcon#enter sib2, iclass 14, count 0 2006.173.20:19:56.16#ibcon#flushed, iclass 14, count 0 2006.173.20:19:56.16#ibcon#about to write, iclass 14, count 0 2006.173.20:19:56.16#ibcon#wrote, iclass 14, count 0 2006.173.20:19:56.16#ibcon#about to read 3, iclass 14, count 0 2006.173.20:19:56.19#ibcon#read 3, iclass 14, count 0 2006.173.20:19:56.19#ibcon#about to read 4, iclass 14, count 0 2006.173.20:19:56.19#ibcon#read 4, iclass 14, count 0 2006.173.20:19:56.19#ibcon#about to read 5, iclass 14, count 0 2006.173.20:19:56.19#ibcon#read 5, iclass 14, count 0 2006.173.20:19:56.19#ibcon#about to read 6, iclass 14, count 0 2006.173.20:19:56.19#ibcon#read 6, iclass 14, count 0 2006.173.20:19:56.19#ibcon#end of sib2, iclass 14, count 0 2006.173.20:19:56.19#ibcon#*after write, iclass 14, count 0 2006.173.20:19:56.19#ibcon#*before return 0, iclass 14, count 0 2006.173.20:19:56.19#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.20:19:56.19#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.20:19:56.19#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.20:19:56.19#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.20:19:56.19$vck44/valo=7,864.99 2006.173.20:19:56.19#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.20:19:56.19#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.20:19:56.19#ibcon#ireg 17 cls_cnt 0 2006.173.20:19:56.19#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.20:19:56.19#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.20:19:56.19#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.20:19:56.19#ibcon#enter wrdev, iclass 16, count 0 2006.173.20:19:56.19#ibcon#first serial, iclass 16, count 0 2006.173.20:19:56.19#ibcon#enter sib2, iclass 16, count 0 2006.173.20:19:56.19#ibcon#flushed, iclass 16, count 0 2006.173.20:19:56.19#ibcon#about to write, iclass 16, count 0 2006.173.20:19:56.19#ibcon#wrote, iclass 16, count 0 2006.173.20:19:56.19#ibcon#about to read 3, iclass 16, count 0 2006.173.20:19:56.21#ibcon#read 3, iclass 16, count 0 2006.173.20:19:56.21#ibcon#about to read 4, iclass 16, count 0 2006.173.20:19:56.21#ibcon#read 4, iclass 16, count 0 2006.173.20:19:56.21#ibcon#about to read 5, iclass 16, count 0 2006.173.20:19:56.21#ibcon#read 5, iclass 16, count 0 2006.173.20:19:56.21#ibcon#about to read 6, iclass 16, count 0 2006.173.20:19:56.21#ibcon#read 6, iclass 16, count 0 2006.173.20:19:56.21#ibcon#end of sib2, iclass 16, count 0 2006.173.20:19:56.21#ibcon#*mode == 0, iclass 16, count 0 2006.173.20:19:56.21#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.20:19:56.21#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.20:19:56.21#ibcon#*before write, iclass 16, count 0 2006.173.20:19:56.21#ibcon#enter sib2, iclass 16, count 0 2006.173.20:19:56.21#ibcon#flushed, iclass 16, count 0 2006.173.20:19:56.21#ibcon#about to write, iclass 16, count 0 2006.173.20:19:56.21#ibcon#wrote, iclass 16, count 0 2006.173.20:19:56.21#ibcon#about to read 3, iclass 16, count 0 2006.173.20:19:56.25#ibcon#read 3, iclass 16, count 0 2006.173.20:19:56.25#ibcon#about to read 4, iclass 16, count 0 2006.173.20:19:56.25#ibcon#read 4, iclass 16, count 0 2006.173.20:19:56.25#ibcon#about to read 5, iclass 16, count 0 2006.173.20:19:56.25#ibcon#read 5, iclass 16, count 0 2006.173.20:19:56.25#ibcon#about to read 6, iclass 16, count 0 2006.173.20:19:56.25#ibcon#read 6, iclass 16, count 0 2006.173.20:19:56.25#ibcon#end of sib2, iclass 16, count 0 2006.173.20:19:56.25#ibcon#*after write, iclass 16, count 0 2006.173.20:19:56.25#ibcon#*before return 0, iclass 16, count 0 2006.173.20:19:56.25#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.20:19:56.25#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.20:19:56.25#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.20:19:56.25#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.20:19:56.25$vck44/va=7,4 2006.173.20:19:56.25#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.20:19:56.25#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.20:19:56.25#ibcon#ireg 11 cls_cnt 2 2006.173.20:19:56.25#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.20:19:56.31#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.20:19:56.31#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.20:19:56.31#ibcon#enter wrdev, iclass 18, count 2 2006.173.20:19:56.31#ibcon#first serial, iclass 18, count 2 2006.173.20:19:56.31#ibcon#enter sib2, iclass 18, count 2 2006.173.20:19:56.31#ibcon#flushed, iclass 18, count 2 2006.173.20:19:56.31#ibcon#about to write, iclass 18, count 2 2006.173.20:19:56.31#ibcon#wrote, iclass 18, count 2 2006.173.20:19:56.31#ibcon#about to read 3, iclass 18, count 2 2006.173.20:19:56.33#ibcon#read 3, iclass 18, count 2 2006.173.20:19:56.33#ibcon#about to read 4, iclass 18, count 2 2006.173.20:19:56.33#ibcon#read 4, iclass 18, count 2 2006.173.20:19:56.33#ibcon#about to read 5, iclass 18, count 2 2006.173.20:19:56.33#ibcon#read 5, iclass 18, count 2 2006.173.20:19:56.33#ibcon#about to read 6, iclass 18, count 2 2006.173.20:19:56.33#ibcon#read 6, iclass 18, count 2 2006.173.20:19:56.33#ibcon#end of sib2, iclass 18, count 2 2006.173.20:19:56.33#ibcon#*mode == 0, iclass 18, count 2 2006.173.20:19:56.33#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.20:19:56.33#ibcon#[25=AT07-04\r\n] 2006.173.20:19:56.33#ibcon#*before write, iclass 18, count 2 2006.173.20:19:56.33#ibcon#enter sib2, iclass 18, count 2 2006.173.20:19:56.33#ibcon#flushed, iclass 18, count 2 2006.173.20:19:56.33#ibcon#about to write, iclass 18, count 2 2006.173.20:19:56.33#ibcon#wrote, iclass 18, count 2 2006.173.20:19:56.33#ibcon#about to read 3, iclass 18, count 2 2006.173.20:19:56.36#ibcon#read 3, iclass 18, count 2 2006.173.20:19:56.36#ibcon#about to read 4, iclass 18, count 2 2006.173.20:19:56.36#ibcon#read 4, iclass 18, count 2 2006.173.20:19:56.36#ibcon#about to read 5, iclass 18, count 2 2006.173.20:19:56.36#ibcon#read 5, iclass 18, count 2 2006.173.20:19:56.36#ibcon#about to read 6, iclass 18, count 2 2006.173.20:19:56.36#ibcon#read 6, iclass 18, count 2 2006.173.20:19:56.36#ibcon#end of sib2, iclass 18, count 2 2006.173.20:19:56.36#ibcon#*after write, iclass 18, count 2 2006.173.20:19:56.36#ibcon#*before return 0, iclass 18, count 2 2006.173.20:19:56.36#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.20:19:56.36#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.20:19:56.36#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.20:19:56.36#ibcon#ireg 7 cls_cnt 0 2006.173.20:19:56.36#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.20:19:56.48#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.20:19:56.48#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.20:19:56.48#ibcon#enter wrdev, iclass 18, count 0 2006.173.20:19:56.48#ibcon#first serial, iclass 18, count 0 2006.173.20:19:56.48#ibcon#enter sib2, iclass 18, count 0 2006.173.20:19:56.48#ibcon#flushed, iclass 18, count 0 2006.173.20:19:56.48#ibcon#about to write, iclass 18, count 0 2006.173.20:19:56.48#ibcon#wrote, iclass 18, count 0 2006.173.20:19:56.48#ibcon#about to read 3, iclass 18, count 0 2006.173.20:19:56.50#ibcon#read 3, iclass 18, count 0 2006.173.20:19:56.50#ibcon#about to read 4, iclass 18, count 0 2006.173.20:19:56.50#ibcon#read 4, iclass 18, count 0 2006.173.20:19:56.50#ibcon#about to read 5, iclass 18, count 0 2006.173.20:19:56.50#ibcon#read 5, iclass 18, count 0 2006.173.20:19:56.50#ibcon#about to read 6, iclass 18, count 0 2006.173.20:19:56.50#ibcon#read 6, iclass 18, count 0 2006.173.20:19:56.50#ibcon#end of sib2, iclass 18, count 0 2006.173.20:19:56.50#ibcon#*mode == 0, iclass 18, count 0 2006.173.20:19:56.50#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.20:19:56.50#ibcon#[25=USB\r\n] 2006.173.20:19:56.50#ibcon#*before write, iclass 18, count 0 2006.173.20:19:56.50#ibcon#enter sib2, iclass 18, count 0 2006.173.20:19:56.50#ibcon#flushed, iclass 18, count 0 2006.173.20:19:56.50#ibcon#about to write, iclass 18, count 0 2006.173.20:19:56.50#ibcon#wrote, iclass 18, count 0 2006.173.20:19:56.50#ibcon#about to read 3, iclass 18, count 0 2006.173.20:19:56.53#ibcon#read 3, iclass 18, count 0 2006.173.20:19:56.53#ibcon#about to read 4, iclass 18, count 0 2006.173.20:19:56.53#ibcon#read 4, iclass 18, count 0 2006.173.20:19:56.53#ibcon#about to read 5, iclass 18, count 0 2006.173.20:19:56.53#ibcon#read 5, iclass 18, count 0 2006.173.20:19:56.53#ibcon#about to read 6, iclass 18, count 0 2006.173.20:19:56.53#ibcon#read 6, iclass 18, count 0 2006.173.20:19:56.53#ibcon#end of sib2, iclass 18, count 0 2006.173.20:19:56.53#ibcon#*after write, iclass 18, count 0 2006.173.20:19:56.53#ibcon#*before return 0, iclass 18, count 0 2006.173.20:19:56.53#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.20:19:56.53#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.20:19:56.53#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.20:19:56.53#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.20:19:56.53$vck44/valo=8,884.99 2006.173.20:19:56.53#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.20:19:56.53#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.20:19:56.53#ibcon#ireg 17 cls_cnt 0 2006.173.20:19:56.53#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.20:19:56.53#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.20:19:56.53#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.20:19:56.53#ibcon#enter wrdev, iclass 20, count 0 2006.173.20:19:56.53#ibcon#first serial, iclass 20, count 0 2006.173.20:19:56.53#ibcon#enter sib2, iclass 20, count 0 2006.173.20:19:56.53#ibcon#flushed, iclass 20, count 0 2006.173.20:19:56.53#ibcon#about to write, iclass 20, count 0 2006.173.20:19:56.53#ibcon#wrote, iclass 20, count 0 2006.173.20:19:56.53#ibcon#about to read 3, iclass 20, count 0 2006.173.20:19:56.55#ibcon#read 3, iclass 20, count 0 2006.173.20:19:56.55#ibcon#about to read 4, iclass 20, count 0 2006.173.20:19:56.55#ibcon#read 4, iclass 20, count 0 2006.173.20:19:56.55#ibcon#about to read 5, iclass 20, count 0 2006.173.20:19:56.55#ibcon#read 5, iclass 20, count 0 2006.173.20:19:56.55#ibcon#about to read 6, iclass 20, count 0 2006.173.20:19:56.55#ibcon#read 6, iclass 20, count 0 2006.173.20:19:56.55#ibcon#end of sib2, iclass 20, count 0 2006.173.20:19:56.55#ibcon#*mode == 0, iclass 20, count 0 2006.173.20:19:56.55#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.20:19:56.55#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.20:19:56.55#ibcon#*before write, iclass 20, count 0 2006.173.20:19:56.55#ibcon#enter sib2, iclass 20, count 0 2006.173.20:19:56.55#ibcon#flushed, iclass 20, count 0 2006.173.20:19:56.55#ibcon#about to write, iclass 20, count 0 2006.173.20:19:56.55#ibcon#wrote, iclass 20, count 0 2006.173.20:19:56.55#ibcon#about to read 3, iclass 20, count 0 2006.173.20:19:56.59#ibcon#read 3, iclass 20, count 0 2006.173.20:19:56.59#ibcon#about to read 4, iclass 20, count 0 2006.173.20:19:56.59#ibcon#read 4, iclass 20, count 0 2006.173.20:19:56.59#ibcon#about to read 5, iclass 20, count 0 2006.173.20:19:56.59#ibcon#read 5, iclass 20, count 0 2006.173.20:19:56.59#ibcon#about to read 6, iclass 20, count 0 2006.173.20:19:56.59#ibcon#read 6, iclass 20, count 0 2006.173.20:19:56.59#ibcon#end of sib2, iclass 20, count 0 2006.173.20:19:56.59#ibcon#*after write, iclass 20, count 0 2006.173.20:19:56.59#ibcon#*before return 0, iclass 20, count 0 2006.173.20:19:56.59#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.20:19:56.59#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.20:19:56.59#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.20:19:56.59#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.20:19:56.59$vck44/va=8,4 2006.173.20:19:56.59#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.20:19:56.59#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.20:19:56.59#ibcon#ireg 11 cls_cnt 2 2006.173.20:19:56.59#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.20:19:56.65#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.20:19:56.65#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.20:19:56.65#ibcon#enter wrdev, iclass 22, count 2 2006.173.20:19:56.65#ibcon#first serial, iclass 22, count 2 2006.173.20:19:56.65#ibcon#enter sib2, iclass 22, count 2 2006.173.20:19:56.65#ibcon#flushed, iclass 22, count 2 2006.173.20:19:56.65#ibcon#about to write, iclass 22, count 2 2006.173.20:19:56.65#ibcon#wrote, iclass 22, count 2 2006.173.20:19:56.65#ibcon#about to read 3, iclass 22, count 2 2006.173.20:19:56.67#ibcon#read 3, iclass 22, count 2 2006.173.20:19:56.67#ibcon#about to read 4, iclass 22, count 2 2006.173.20:19:56.67#ibcon#read 4, iclass 22, count 2 2006.173.20:19:56.67#ibcon#about to read 5, iclass 22, count 2 2006.173.20:19:56.67#ibcon#read 5, iclass 22, count 2 2006.173.20:19:56.67#ibcon#about to read 6, iclass 22, count 2 2006.173.20:19:56.67#ibcon#read 6, iclass 22, count 2 2006.173.20:19:56.67#ibcon#end of sib2, iclass 22, count 2 2006.173.20:19:56.67#ibcon#*mode == 0, iclass 22, count 2 2006.173.20:19:56.67#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.20:19:56.67#ibcon#[25=AT08-04\r\n] 2006.173.20:19:56.67#ibcon#*before write, iclass 22, count 2 2006.173.20:19:56.67#ibcon#enter sib2, iclass 22, count 2 2006.173.20:19:56.67#ibcon#flushed, iclass 22, count 2 2006.173.20:19:56.67#ibcon#about to write, iclass 22, count 2 2006.173.20:19:56.67#ibcon#wrote, iclass 22, count 2 2006.173.20:19:56.67#ibcon#about to read 3, iclass 22, count 2 2006.173.20:19:56.70#ibcon#read 3, iclass 22, count 2 2006.173.20:19:56.70#ibcon#about to read 4, iclass 22, count 2 2006.173.20:19:56.70#ibcon#read 4, iclass 22, count 2 2006.173.20:19:56.70#ibcon#about to read 5, iclass 22, count 2 2006.173.20:19:56.70#ibcon#read 5, iclass 22, count 2 2006.173.20:19:56.70#ibcon#about to read 6, iclass 22, count 2 2006.173.20:19:56.70#ibcon#read 6, iclass 22, count 2 2006.173.20:19:56.70#ibcon#end of sib2, iclass 22, count 2 2006.173.20:19:56.70#ibcon#*after write, iclass 22, count 2 2006.173.20:19:56.70#ibcon#*before return 0, iclass 22, count 2 2006.173.20:19:56.70#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.20:19:56.70#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.20:19:56.70#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.20:19:56.70#ibcon#ireg 7 cls_cnt 0 2006.173.20:19:56.70#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.20:19:56.82#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.20:19:56.82#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.20:19:56.82#ibcon#enter wrdev, iclass 22, count 0 2006.173.20:19:56.82#ibcon#first serial, iclass 22, count 0 2006.173.20:19:56.82#ibcon#enter sib2, iclass 22, count 0 2006.173.20:19:56.82#ibcon#flushed, iclass 22, count 0 2006.173.20:19:56.82#ibcon#about to write, iclass 22, count 0 2006.173.20:19:56.82#ibcon#wrote, iclass 22, count 0 2006.173.20:19:56.82#ibcon#about to read 3, iclass 22, count 0 2006.173.20:19:56.84#ibcon#read 3, iclass 22, count 0 2006.173.20:19:56.84#ibcon#about to read 4, iclass 22, count 0 2006.173.20:19:56.84#ibcon#read 4, iclass 22, count 0 2006.173.20:19:56.84#ibcon#about to read 5, iclass 22, count 0 2006.173.20:19:56.84#ibcon#read 5, iclass 22, count 0 2006.173.20:19:56.84#ibcon#about to read 6, iclass 22, count 0 2006.173.20:19:56.84#ibcon#read 6, iclass 22, count 0 2006.173.20:19:56.84#ibcon#end of sib2, iclass 22, count 0 2006.173.20:19:56.84#ibcon#*mode == 0, iclass 22, count 0 2006.173.20:19:56.84#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.20:19:56.84#ibcon#[25=USB\r\n] 2006.173.20:19:56.84#ibcon#*before write, iclass 22, count 0 2006.173.20:19:56.84#ibcon#enter sib2, iclass 22, count 0 2006.173.20:19:56.84#ibcon#flushed, iclass 22, count 0 2006.173.20:19:56.84#ibcon#about to write, iclass 22, count 0 2006.173.20:19:56.84#ibcon#wrote, iclass 22, count 0 2006.173.20:19:56.84#ibcon#about to read 3, iclass 22, count 0 2006.173.20:19:56.87#ibcon#read 3, iclass 22, count 0 2006.173.20:19:56.87#ibcon#about to read 4, iclass 22, count 0 2006.173.20:19:56.87#ibcon#read 4, iclass 22, count 0 2006.173.20:19:56.87#ibcon#about to read 5, iclass 22, count 0 2006.173.20:19:56.87#ibcon#read 5, iclass 22, count 0 2006.173.20:19:56.87#ibcon#about to read 6, iclass 22, count 0 2006.173.20:19:56.87#ibcon#read 6, iclass 22, count 0 2006.173.20:19:56.87#ibcon#end of sib2, iclass 22, count 0 2006.173.20:19:56.87#ibcon#*after write, iclass 22, count 0 2006.173.20:19:56.87#ibcon#*before return 0, iclass 22, count 0 2006.173.20:19:56.87#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.20:19:56.87#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.20:19:56.87#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.20:19:56.87#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.20:19:56.87$vck44/vblo=1,629.99 2006.173.20:19:56.87#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.20:19:56.87#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.20:19:56.87#ibcon#ireg 17 cls_cnt 0 2006.173.20:19:56.87#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.20:19:56.87#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.20:19:56.87#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.20:19:56.87#ibcon#enter wrdev, iclass 24, count 0 2006.173.20:19:56.87#ibcon#first serial, iclass 24, count 0 2006.173.20:19:56.87#ibcon#enter sib2, iclass 24, count 0 2006.173.20:19:56.87#ibcon#flushed, iclass 24, count 0 2006.173.20:19:56.87#ibcon#about to write, iclass 24, count 0 2006.173.20:19:56.87#ibcon#wrote, iclass 24, count 0 2006.173.20:19:56.87#ibcon#about to read 3, iclass 24, count 0 2006.173.20:19:56.89#ibcon#read 3, iclass 24, count 0 2006.173.20:19:56.89#ibcon#about to read 4, iclass 24, count 0 2006.173.20:19:56.89#ibcon#read 4, iclass 24, count 0 2006.173.20:19:56.89#ibcon#about to read 5, iclass 24, count 0 2006.173.20:19:56.89#ibcon#read 5, iclass 24, count 0 2006.173.20:19:56.89#ibcon#about to read 6, iclass 24, count 0 2006.173.20:19:56.89#ibcon#read 6, iclass 24, count 0 2006.173.20:19:56.89#ibcon#end of sib2, iclass 24, count 0 2006.173.20:19:56.89#ibcon#*mode == 0, iclass 24, count 0 2006.173.20:19:56.89#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.20:19:56.89#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.20:19:56.89#ibcon#*before write, iclass 24, count 0 2006.173.20:19:56.89#ibcon#enter sib2, iclass 24, count 0 2006.173.20:19:56.89#ibcon#flushed, iclass 24, count 0 2006.173.20:19:56.89#ibcon#about to write, iclass 24, count 0 2006.173.20:19:56.89#ibcon#wrote, iclass 24, count 0 2006.173.20:19:56.89#ibcon#about to read 3, iclass 24, count 0 2006.173.20:19:56.93#ibcon#read 3, iclass 24, count 0 2006.173.20:19:56.93#ibcon#about to read 4, iclass 24, count 0 2006.173.20:19:56.93#ibcon#read 4, iclass 24, count 0 2006.173.20:19:56.93#ibcon#about to read 5, iclass 24, count 0 2006.173.20:19:56.93#ibcon#read 5, iclass 24, count 0 2006.173.20:19:56.93#ibcon#about to read 6, iclass 24, count 0 2006.173.20:19:56.93#ibcon#read 6, iclass 24, count 0 2006.173.20:19:56.93#ibcon#end of sib2, iclass 24, count 0 2006.173.20:19:56.93#ibcon#*after write, iclass 24, count 0 2006.173.20:19:56.93#ibcon#*before return 0, iclass 24, count 0 2006.173.20:19:56.93#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.20:19:56.93#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.20:19:56.93#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.20:19:56.93#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.20:19:56.93$vck44/vb=1,4 2006.173.20:19:56.93#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.20:19:56.93#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.20:19:56.93#ibcon#ireg 11 cls_cnt 2 2006.173.20:19:56.93#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.20:19:56.93#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.20:19:56.93#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.20:19:56.93#ibcon#enter wrdev, iclass 26, count 2 2006.173.20:19:56.93#ibcon#first serial, iclass 26, count 2 2006.173.20:19:56.93#ibcon#enter sib2, iclass 26, count 2 2006.173.20:19:56.93#ibcon#flushed, iclass 26, count 2 2006.173.20:19:56.93#ibcon#about to write, iclass 26, count 2 2006.173.20:19:56.93#ibcon#wrote, iclass 26, count 2 2006.173.20:19:56.93#ibcon#about to read 3, iclass 26, count 2 2006.173.20:19:56.95#ibcon#read 3, iclass 26, count 2 2006.173.20:19:56.95#ibcon#about to read 4, iclass 26, count 2 2006.173.20:19:56.95#ibcon#read 4, iclass 26, count 2 2006.173.20:19:56.95#ibcon#about to read 5, iclass 26, count 2 2006.173.20:19:56.95#ibcon#read 5, iclass 26, count 2 2006.173.20:19:56.95#ibcon#about to read 6, iclass 26, count 2 2006.173.20:19:56.95#ibcon#read 6, iclass 26, count 2 2006.173.20:19:56.95#ibcon#end of sib2, iclass 26, count 2 2006.173.20:19:56.95#ibcon#*mode == 0, iclass 26, count 2 2006.173.20:19:56.95#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.20:19:56.95#ibcon#[27=AT01-04\r\n] 2006.173.20:19:56.95#ibcon#*before write, iclass 26, count 2 2006.173.20:19:56.95#ibcon#enter sib2, iclass 26, count 2 2006.173.20:19:56.95#ibcon#flushed, iclass 26, count 2 2006.173.20:19:56.95#ibcon#about to write, iclass 26, count 2 2006.173.20:19:56.95#ibcon#wrote, iclass 26, count 2 2006.173.20:19:56.95#ibcon#about to read 3, iclass 26, count 2 2006.173.20:19:56.98#ibcon#read 3, iclass 26, count 2 2006.173.20:19:56.98#ibcon#about to read 4, iclass 26, count 2 2006.173.20:19:56.98#ibcon#read 4, iclass 26, count 2 2006.173.20:19:56.98#ibcon#about to read 5, iclass 26, count 2 2006.173.20:19:56.98#ibcon#read 5, iclass 26, count 2 2006.173.20:19:56.98#ibcon#about to read 6, iclass 26, count 2 2006.173.20:19:56.98#ibcon#read 6, iclass 26, count 2 2006.173.20:19:56.98#ibcon#end of sib2, iclass 26, count 2 2006.173.20:19:56.98#ibcon#*after write, iclass 26, count 2 2006.173.20:19:56.98#ibcon#*before return 0, iclass 26, count 2 2006.173.20:19:56.98#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.20:19:56.98#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.20:19:56.98#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.20:19:56.98#ibcon#ireg 7 cls_cnt 0 2006.173.20:19:56.98#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.20:19:57.10#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.20:19:57.10#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.20:19:57.10#ibcon#enter wrdev, iclass 26, count 0 2006.173.20:19:57.10#ibcon#first serial, iclass 26, count 0 2006.173.20:19:57.10#ibcon#enter sib2, iclass 26, count 0 2006.173.20:19:57.10#ibcon#flushed, iclass 26, count 0 2006.173.20:19:57.10#ibcon#about to write, iclass 26, count 0 2006.173.20:19:57.10#ibcon#wrote, iclass 26, count 0 2006.173.20:19:57.10#ibcon#about to read 3, iclass 26, count 0 2006.173.20:19:57.12#ibcon#read 3, iclass 26, count 0 2006.173.20:19:57.12#ibcon#about to read 4, iclass 26, count 0 2006.173.20:19:57.12#ibcon#read 4, iclass 26, count 0 2006.173.20:19:57.12#ibcon#about to read 5, iclass 26, count 0 2006.173.20:19:57.12#ibcon#read 5, iclass 26, count 0 2006.173.20:19:57.12#ibcon#about to read 6, iclass 26, count 0 2006.173.20:19:57.12#ibcon#read 6, iclass 26, count 0 2006.173.20:19:57.12#ibcon#end of sib2, iclass 26, count 0 2006.173.20:19:57.12#ibcon#*mode == 0, iclass 26, count 0 2006.173.20:19:57.12#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.20:19:57.12#ibcon#[27=USB\r\n] 2006.173.20:19:57.12#ibcon#*before write, iclass 26, count 0 2006.173.20:19:57.12#ibcon#enter sib2, iclass 26, count 0 2006.173.20:19:57.12#ibcon#flushed, iclass 26, count 0 2006.173.20:19:57.12#ibcon#about to write, iclass 26, count 0 2006.173.20:19:57.12#ibcon#wrote, iclass 26, count 0 2006.173.20:19:57.12#ibcon#about to read 3, iclass 26, count 0 2006.173.20:19:57.15#ibcon#read 3, iclass 26, count 0 2006.173.20:19:57.15#ibcon#about to read 4, iclass 26, count 0 2006.173.20:19:57.15#ibcon#read 4, iclass 26, count 0 2006.173.20:19:57.15#ibcon#about to read 5, iclass 26, count 0 2006.173.20:19:57.15#ibcon#read 5, iclass 26, count 0 2006.173.20:19:57.15#ibcon#about to read 6, iclass 26, count 0 2006.173.20:19:57.15#ibcon#read 6, iclass 26, count 0 2006.173.20:19:57.15#ibcon#end of sib2, iclass 26, count 0 2006.173.20:19:57.15#ibcon#*after write, iclass 26, count 0 2006.173.20:19:57.15#ibcon#*before return 0, iclass 26, count 0 2006.173.20:19:57.15#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.20:19:57.15#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.20:19:57.15#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.20:19:57.15#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.20:19:57.15$vck44/vblo=2,634.99 2006.173.20:19:57.15#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.20:19:57.15#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.20:19:57.15#ibcon#ireg 17 cls_cnt 0 2006.173.20:19:57.15#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.20:19:57.15#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.20:19:57.15#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.20:19:57.15#ibcon#enter wrdev, iclass 28, count 0 2006.173.20:19:57.15#ibcon#first serial, iclass 28, count 0 2006.173.20:19:57.15#ibcon#enter sib2, iclass 28, count 0 2006.173.20:19:57.15#ibcon#flushed, iclass 28, count 0 2006.173.20:19:57.15#ibcon#about to write, iclass 28, count 0 2006.173.20:19:57.15#ibcon#wrote, iclass 28, count 0 2006.173.20:19:57.15#ibcon#about to read 3, iclass 28, count 0 2006.173.20:19:57.17#ibcon#read 3, iclass 28, count 0 2006.173.20:19:57.17#ibcon#about to read 4, iclass 28, count 0 2006.173.20:19:57.17#ibcon#read 4, iclass 28, count 0 2006.173.20:19:57.17#ibcon#about to read 5, iclass 28, count 0 2006.173.20:19:57.17#ibcon#read 5, iclass 28, count 0 2006.173.20:19:57.17#ibcon#about to read 6, iclass 28, count 0 2006.173.20:19:57.17#ibcon#read 6, iclass 28, count 0 2006.173.20:19:57.17#ibcon#end of sib2, iclass 28, count 0 2006.173.20:19:57.17#ibcon#*mode == 0, iclass 28, count 0 2006.173.20:19:57.17#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.20:19:57.17#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.20:19:57.17#ibcon#*before write, iclass 28, count 0 2006.173.20:19:57.17#ibcon#enter sib2, iclass 28, count 0 2006.173.20:19:57.17#ibcon#flushed, iclass 28, count 0 2006.173.20:19:57.17#ibcon#about to write, iclass 28, count 0 2006.173.20:19:57.17#ibcon#wrote, iclass 28, count 0 2006.173.20:19:57.17#ibcon#about to read 3, iclass 28, count 0 2006.173.20:19:57.21#ibcon#read 3, iclass 28, count 0 2006.173.20:19:57.21#ibcon#about to read 4, iclass 28, count 0 2006.173.20:19:57.21#ibcon#read 4, iclass 28, count 0 2006.173.20:19:57.21#ibcon#about to read 5, iclass 28, count 0 2006.173.20:19:57.21#ibcon#read 5, iclass 28, count 0 2006.173.20:19:57.21#ibcon#about to read 6, iclass 28, count 0 2006.173.20:19:57.21#ibcon#read 6, iclass 28, count 0 2006.173.20:19:57.21#ibcon#end of sib2, iclass 28, count 0 2006.173.20:19:57.21#ibcon#*after write, iclass 28, count 0 2006.173.20:19:57.21#ibcon#*before return 0, iclass 28, count 0 2006.173.20:19:57.21#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.20:19:57.21#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.20:19:57.21#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.20:19:57.21#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.20:19:57.21$vck44/vb=2,4 2006.173.20:19:57.21#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.20:19:57.21#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.20:19:57.21#ibcon#ireg 11 cls_cnt 2 2006.173.20:19:57.21#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.20:19:57.27#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.20:19:57.27#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.20:19:57.27#ibcon#enter wrdev, iclass 30, count 2 2006.173.20:19:57.27#ibcon#first serial, iclass 30, count 2 2006.173.20:19:57.27#ibcon#enter sib2, iclass 30, count 2 2006.173.20:19:57.27#ibcon#flushed, iclass 30, count 2 2006.173.20:19:57.27#ibcon#about to write, iclass 30, count 2 2006.173.20:19:57.27#ibcon#wrote, iclass 30, count 2 2006.173.20:19:57.27#ibcon#about to read 3, iclass 30, count 2 2006.173.20:19:57.29#ibcon#read 3, iclass 30, count 2 2006.173.20:19:57.29#ibcon#about to read 4, iclass 30, count 2 2006.173.20:19:57.29#ibcon#read 4, iclass 30, count 2 2006.173.20:19:57.29#ibcon#about to read 5, iclass 30, count 2 2006.173.20:19:57.29#ibcon#read 5, iclass 30, count 2 2006.173.20:19:57.29#ibcon#about to read 6, iclass 30, count 2 2006.173.20:19:57.29#ibcon#read 6, iclass 30, count 2 2006.173.20:19:57.29#ibcon#end of sib2, iclass 30, count 2 2006.173.20:19:57.29#ibcon#*mode == 0, iclass 30, count 2 2006.173.20:19:57.29#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.20:19:57.29#ibcon#[27=AT02-04\r\n] 2006.173.20:19:57.29#ibcon#*before write, iclass 30, count 2 2006.173.20:19:57.29#ibcon#enter sib2, iclass 30, count 2 2006.173.20:19:57.29#ibcon#flushed, iclass 30, count 2 2006.173.20:19:57.29#ibcon#about to write, iclass 30, count 2 2006.173.20:19:57.29#ibcon#wrote, iclass 30, count 2 2006.173.20:19:57.29#ibcon#about to read 3, iclass 30, count 2 2006.173.20:19:57.31#abcon#<5=/07 0.5 0.9 19.661001002.9\r\n> 2006.173.20:19:57.32#ibcon#read 3, iclass 30, count 2 2006.173.20:19:57.32#ibcon#about to read 4, iclass 30, count 2 2006.173.20:19:57.32#ibcon#read 4, iclass 30, count 2 2006.173.20:19:57.32#ibcon#about to read 5, iclass 30, count 2 2006.173.20:19:57.32#ibcon#read 5, iclass 30, count 2 2006.173.20:19:57.32#ibcon#about to read 6, iclass 30, count 2 2006.173.20:19:57.32#ibcon#read 6, iclass 30, count 2 2006.173.20:19:57.32#ibcon#end of sib2, iclass 30, count 2 2006.173.20:19:57.32#ibcon#*after write, iclass 30, count 2 2006.173.20:19:57.32#ibcon#*before return 0, iclass 30, count 2 2006.173.20:19:57.32#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.20:19:57.32#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.20:19:57.32#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.20:19:57.32#ibcon#ireg 7 cls_cnt 0 2006.173.20:19:57.32#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.20:19:57.33#abcon#{5=INTERFACE CLEAR} 2006.173.20:19:57.39#abcon#[5=S1D000X0/0*\r\n] 2006.173.20:19:57.44#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.20:19:57.44#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.20:19:57.44#ibcon#enter wrdev, iclass 30, count 0 2006.173.20:19:57.44#ibcon#first serial, iclass 30, count 0 2006.173.20:19:57.44#ibcon#enter sib2, iclass 30, count 0 2006.173.20:19:57.44#ibcon#flushed, iclass 30, count 0 2006.173.20:19:57.44#ibcon#about to write, iclass 30, count 0 2006.173.20:19:57.44#ibcon#wrote, iclass 30, count 0 2006.173.20:19:57.44#ibcon#about to read 3, iclass 30, count 0 2006.173.20:19:57.46#ibcon#read 3, iclass 30, count 0 2006.173.20:19:57.46#ibcon#about to read 4, iclass 30, count 0 2006.173.20:19:57.46#ibcon#read 4, iclass 30, count 0 2006.173.20:19:57.46#ibcon#about to read 5, iclass 30, count 0 2006.173.20:19:57.46#ibcon#read 5, iclass 30, count 0 2006.173.20:19:57.46#ibcon#about to read 6, iclass 30, count 0 2006.173.20:19:57.46#ibcon#read 6, iclass 30, count 0 2006.173.20:19:57.46#ibcon#end of sib2, iclass 30, count 0 2006.173.20:19:57.46#ibcon#*mode == 0, iclass 30, count 0 2006.173.20:19:57.46#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.20:19:57.46#ibcon#[27=USB\r\n] 2006.173.20:19:57.46#ibcon#*before write, iclass 30, count 0 2006.173.20:19:57.46#ibcon#enter sib2, iclass 30, count 0 2006.173.20:19:57.46#ibcon#flushed, iclass 30, count 0 2006.173.20:19:57.46#ibcon#about to write, iclass 30, count 0 2006.173.20:19:57.46#ibcon#wrote, iclass 30, count 0 2006.173.20:19:57.46#ibcon#about to read 3, iclass 30, count 0 2006.173.20:19:57.49#ibcon#read 3, iclass 30, count 0 2006.173.20:19:57.49#ibcon#about to read 4, iclass 30, count 0 2006.173.20:19:57.49#ibcon#read 4, iclass 30, count 0 2006.173.20:19:57.49#ibcon#about to read 5, iclass 30, count 0 2006.173.20:19:57.49#ibcon#read 5, iclass 30, count 0 2006.173.20:19:57.49#ibcon#about to read 6, iclass 30, count 0 2006.173.20:19:57.49#ibcon#read 6, iclass 30, count 0 2006.173.20:19:57.49#ibcon#end of sib2, iclass 30, count 0 2006.173.20:19:57.49#ibcon#*after write, iclass 30, count 0 2006.173.20:19:57.49#ibcon#*before return 0, iclass 30, count 0 2006.173.20:19:57.49#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.20:19:57.49#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.20:19:57.49#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.20:19:57.49#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.20:19:57.49$vck44/vblo=3,649.99 2006.173.20:19:57.49#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.20:19:57.49#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.20:19:57.49#ibcon#ireg 17 cls_cnt 0 2006.173.20:19:57.49#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.20:19:57.49#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.20:19:57.49#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.20:19:57.49#ibcon#enter wrdev, iclass 36, count 0 2006.173.20:19:57.49#ibcon#first serial, iclass 36, count 0 2006.173.20:19:57.49#ibcon#enter sib2, iclass 36, count 0 2006.173.20:19:57.49#ibcon#flushed, iclass 36, count 0 2006.173.20:19:57.49#ibcon#about to write, iclass 36, count 0 2006.173.20:19:57.49#ibcon#wrote, iclass 36, count 0 2006.173.20:19:57.49#ibcon#about to read 3, iclass 36, count 0 2006.173.20:19:57.51#ibcon#read 3, iclass 36, count 0 2006.173.20:19:57.51#ibcon#about to read 4, iclass 36, count 0 2006.173.20:19:57.51#ibcon#read 4, iclass 36, count 0 2006.173.20:19:57.51#ibcon#about to read 5, iclass 36, count 0 2006.173.20:19:57.51#ibcon#read 5, iclass 36, count 0 2006.173.20:19:57.51#ibcon#about to read 6, iclass 36, count 0 2006.173.20:19:57.51#ibcon#read 6, iclass 36, count 0 2006.173.20:19:57.51#ibcon#end of sib2, iclass 36, count 0 2006.173.20:19:57.51#ibcon#*mode == 0, iclass 36, count 0 2006.173.20:19:57.51#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.20:19:57.51#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.20:19:57.51#ibcon#*before write, iclass 36, count 0 2006.173.20:19:57.51#ibcon#enter sib2, iclass 36, count 0 2006.173.20:19:57.51#ibcon#flushed, iclass 36, count 0 2006.173.20:19:57.51#ibcon#about to write, iclass 36, count 0 2006.173.20:19:57.51#ibcon#wrote, iclass 36, count 0 2006.173.20:19:57.51#ibcon#about to read 3, iclass 36, count 0 2006.173.20:19:57.55#ibcon#read 3, iclass 36, count 0 2006.173.20:19:57.55#ibcon#about to read 4, iclass 36, count 0 2006.173.20:19:57.55#ibcon#read 4, iclass 36, count 0 2006.173.20:19:57.55#ibcon#about to read 5, iclass 36, count 0 2006.173.20:19:57.55#ibcon#read 5, iclass 36, count 0 2006.173.20:19:57.55#ibcon#about to read 6, iclass 36, count 0 2006.173.20:19:57.55#ibcon#read 6, iclass 36, count 0 2006.173.20:19:57.55#ibcon#end of sib2, iclass 36, count 0 2006.173.20:19:57.55#ibcon#*after write, iclass 36, count 0 2006.173.20:19:57.55#ibcon#*before return 0, iclass 36, count 0 2006.173.20:19:57.55#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.20:19:57.55#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.20:19:57.55#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.20:19:57.55#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.20:19:57.55$vck44/vb=3,4 2006.173.20:19:57.55#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.20:19:57.55#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.20:19:57.55#ibcon#ireg 11 cls_cnt 2 2006.173.20:19:57.55#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.20:19:57.61#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.20:19:57.61#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.20:19:57.61#ibcon#enter wrdev, iclass 38, count 2 2006.173.20:19:57.61#ibcon#first serial, iclass 38, count 2 2006.173.20:19:57.61#ibcon#enter sib2, iclass 38, count 2 2006.173.20:19:57.61#ibcon#flushed, iclass 38, count 2 2006.173.20:19:57.61#ibcon#about to write, iclass 38, count 2 2006.173.20:19:57.61#ibcon#wrote, iclass 38, count 2 2006.173.20:19:57.61#ibcon#about to read 3, iclass 38, count 2 2006.173.20:19:57.63#ibcon#read 3, iclass 38, count 2 2006.173.20:19:57.63#ibcon#about to read 4, iclass 38, count 2 2006.173.20:19:57.63#ibcon#read 4, iclass 38, count 2 2006.173.20:19:57.63#ibcon#about to read 5, iclass 38, count 2 2006.173.20:19:57.63#ibcon#read 5, iclass 38, count 2 2006.173.20:19:57.63#ibcon#about to read 6, iclass 38, count 2 2006.173.20:19:57.63#ibcon#read 6, iclass 38, count 2 2006.173.20:19:57.63#ibcon#end of sib2, iclass 38, count 2 2006.173.20:19:57.63#ibcon#*mode == 0, iclass 38, count 2 2006.173.20:19:57.63#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.20:19:57.63#ibcon#[27=AT03-04\r\n] 2006.173.20:19:57.63#ibcon#*before write, iclass 38, count 2 2006.173.20:19:57.63#ibcon#enter sib2, iclass 38, count 2 2006.173.20:19:57.63#ibcon#flushed, iclass 38, count 2 2006.173.20:19:57.63#ibcon#about to write, iclass 38, count 2 2006.173.20:19:57.63#ibcon#wrote, iclass 38, count 2 2006.173.20:19:57.63#ibcon#about to read 3, iclass 38, count 2 2006.173.20:19:57.66#ibcon#read 3, iclass 38, count 2 2006.173.20:19:57.66#ibcon#about to read 4, iclass 38, count 2 2006.173.20:19:57.66#ibcon#read 4, iclass 38, count 2 2006.173.20:19:57.66#ibcon#about to read 5, iclass 38, count 2 2006.173.20:19:57.66#ibcon#read 5, iclass 38, count 2 2006.173.20:19:57.66#ibcon#about to read 6, iclass 38, count 2 2006.173.20:19:57.66#ibcon#read 6, iclass 38, count 2 2006.173.20:19:57.66#ibcon#end of sib2, iclass 38, count 2 2006.173.20:19:57.66#ibcon#*after write, iclass 38, count 2 2006.173.20:19:57.66#ibcon#*before return 0, iclass 38, count 2 2006.173.20:19:57.66#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.20:19:57.66#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.20:19:57.66#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.20:19:57.66#ibcon#ireg 7 cls_cnt 0 2006.173.20:19:57.66#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.20:19:57.78#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.20:19:57.78#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.20:19:57.78#ibcon#enter wrdev, iclass 38, count 0 2006.173.20:19:57.78#ibcon#first serial, iclass 38, count 0 2006.173.20:19:57.78#ibcon#enter sib2, iclass 38, count 0 2006.173.20:19:57.78#ibcon#flushed, iclass 38, count 0 2006.173.20:19:57.78#ibcon#about to write, iclass 38, count 0 2006.173.20:19:57.78#ibcon#wrote, iclass 38, count 0 2006.173.20:19:57.78#ibcon#about to read 3, iclass 38, count 0 2006.173.20:19:57.80#ibcon#read 3, iclass 38, count 0 2006.173.20:19:57.80#ibcon#about to read 4, iclass 38, count 0 2006.173.20:19:57.80#ibcon#read 4, iclass 38, count 0 2006.173.20:19:57.80#ibcon#about to read 5, iclass 38, count 0 2006.173.20:19:57.80#ibcon#read 5, iclass 38, count 0 2006.173.20:19:57.80#ibcon#about to read 6, iclass 38, count 0 2006.173.20:19:57.80#ibcon#read 6, iclass 38, count 0 2006.173.20:19:57.80#ibcon#end of sib2, iclass 38, count 0 2006.173.20:19:57.80#ibcon#*mode == 0, iclass 38, count 0 2006.173.20:19:57.80#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.20:19:57.80#ibcon#[27=USB\r\n] 2006.173.20:19:57.80#ibcon#*before write, iclass 38, count 0 2006.173.20:19:57.80#ibcon#enter sib2, iclass 38, count 0 2006.173.20:19:57.80#ibcon#flushed, iclass 38, count 0 2006.173.20:19:57.80#ibcon#about to write, iclass 38, count 0 2006.173.20:19:57.80#ibcon#wrote, iclass 38, count 0 2006.173.20:19:57.80#ibcon#about to read 3, iclass 38, count 0 2006.173.20:19:57.83#ibcon#read 3, iclass 38, count 0 2006.173.20:19:57.83#ibcon#about to read 4, iclass 38, count 0 2006.173.20:19:57.83#ibcon#read 4, iclass 38, count 0 2006.173.20:19:57.83#ibcon#about to read 5, iclass 38, count 0 2006.173.20:19:57.83#ibcon#read 5, iclass 38, count 0 2006.173.20:19:57.83#ibcon#about to read 6, iclass 38, count 0 2006.173.20:19:57.83#ibcon#read 6, iclass 38, count 0 2006.173.20:19:57.83#ibcon#end of sib2, iclass 38, count 0 2006.173.20:19:57.83#ibcon#*after write, iclass 38, count 0 2006.173.20:19:57.83#ibcon#*before return 0, iclass 38, count 0 2006.173.20:19:57.83#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.20:19:57.83#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.20:19:57.83#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.20:19:57.83#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.20:19:57.83$vck44/vblo=4,679.99 2006.173.20:19:57.83#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.20:19:57.83#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.20:19:57.83#ibcon#ireg 17 cls_cnt 0 2006.173.20:19:57.83#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.20:19:57.83#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.20:19:57.83#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.20:19:57.83#ibcon#enter wrdev, iclass 40, count 0 2006.173.20:19:57.83#ibcon#first serial, iclass 40, count 0 2006.173.20:19:57.83#ibcon#enter sib2, iclass 40, count 0 2006.173.20:19:57.83#ibcon#flushed, iclass 40, count 0 2006.173.20:19:57.83#ibcon#about to write, iclass 40, count 0 2006.173.20:19:57.83#ibcon#wrote, iclass 40, count 0 2006.173.20:19:57.83#ibcon#about to read 3, iclass 40, count 0 2006.173.20:19:57.85#ibcon#read 3, iclass 40, count 0 2006.173.20:19:57.85#ibcon#about to read 4, iclass 40, count 0 2006.173.20:19:57.85#ibcon#read 4, iclass 40, count 0 2006.173.20:19:57.85#ibcon#about to read 5, iclass 40, count 0 2006.173.20:19:57.85#ibcon#read 5, iclass 40, count 0 2006.173.20:19:57.85#ibcon#about to read 6, iclass 40, count 0 2006.173.20:19:57.85#ibcon#read 6, iclass 40, count 0 2006.173.20:19:57.85#ibcon#end of sib2, iclass 40, count 0 2006.173.20:19:57.85#ibcon#*mode == 0, iclass 40, count 0 2006.173.20:19:57.85#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.20:19:57.85#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.20:19:57.85#ibcon#*before write, iclass 40, count 0 2006.173.20:19:57.85#ibcon#enter sib2, iclass 40, count 0 2006.173.20:19:57.85#ibcon#flushed, iclass 40, count 0 2006.173.20:19:57.85#ibcon#about to write, iclass 40, count 0 2006.173.20:19:57.85#ibcon#wrote, iclass 40, count 0 2006.173.20:19:57.85#ibcon#about to read 3, iclass 40, count 0 2006.173.20:19:57.89#ibcon#read 3, iclass 40, count 0 2006.173.20:19:57.89#ibcon#about to read 4, iclass 40, count 0 2006.173.20:19:57.89#ibcon#read 4, iclass 40, count 0 2006.173.20:19:57.89#ibcon#about to read 5, iclass 40, count 0 2006.173.20:19:57.89#ibcon#read 5, iclass 40, count 0 2006.173.20:19:57.89#ibcon#about to read 6, iclass 40, count 0 2006.173.20:19:57.89#ibcon#read 6, iclass 40, count 0 2006.173.20:19:57.89#ibcon#end of sib2, iclass 40, count 0 2006.173.20:19:57.89#ibcon#*after write, iclass 40, count 0 2006.173.20:19:57.89#ibcon#*before return 0, iclass 40, count 0 2006.173.20:19:57.89#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.20:19:57.89#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.20:19:57.89#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.20:19:57.89#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.20:19:57.89$vck44/vb=4,4 2006.173.20:19:57.89#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.20:19:57.89#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.20:19:57.89#ibcon#ireg 11 cls_cnt 2 2006.173.20:19:57.89#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.20:19:57.95#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.20:19:57.95#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.20:19:57.95#ibcon#enter wrdev, iclass 4, count 2 2006.173.20:19:57.95#ibcon#first serial, iclass 4, count 2 2006.173.20:19:57.95#ibcon#enter sib2, iclass 4, count 2 2006.173.20:19:57.95#ibcon#flushed, iclass 4, count 2 2006.173.20:19:57.95#ibcon#about to write, iclass 4, count 2 2006.173.20:19:57.95#ibcon#wrote, iclass 4, count 2 2006.173.20:19:57.95#ibcon#about to read 3, iclass 4, count 2 2006.173.20:19:57.97#ibcon#read 3, iclass 4, count 2 2006.173.20:19:57.97#ibcon#about to read 4, iclass 4, count 2 2006.173.20:19:57.97#ibcon#read 4, iclass 4, count 2 2006.173.20:19:57.97#ibcon#about to read 5, iclass 4, count 2 2006.173.20:19:57.97#ibcon#read 5, iclass 4, count 2 2006.173.20:19:57.97#ibcon#about to read 6, iclass 4, count 2 2006.173.20:19:57.97#ibcon#read 6, iclass 4, count 2 2006.173.20:19:57.97#ibcon#end of sib2, iclass 4, count 2 2006.173.20:19:57.97#ibcon#*mode == 0, iclass 4, count 2 2006.173.20:19:57.97#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.20:19:57.97#ibcon#[27=AT04-04\r\n] 2006.173.20:19:57.97#ibcon#*before write, iclass 4, count 2 2006.173.20:19:57.97#ibcon#enter sib2, iclass 4, count 2 2006.173.20:19:57.97#ibcon#flushed, iclass 4, count 2 2006.173.20:19:57.97#ibcon#about to write, iclass 4, count 2 2006.173.20:19:57.97#ibcon#wrote, iclass 4, count 2 2006.173.20:19:57.97#ibcon#about to read 3, iclass 4, count 2 2006.173.20:19:58.00#ibcon#read 3, iclass 4, count 2 2006.173.20:19:58.00#ibcon#about to read 4, iclass 4, count 2 2006.173.20:19:58.00#ibcon#read 4, iclass 4, count 2 2006.173.20:19:58.00#ibcon#about to read 5, iclass 4, count 2 2006.173.20:19:58.00#ibcon#read 5, iclass 4, count 2 2006.173.20:19:58.00#ibcon#about to read 6, iclass 4, count 2 2006.173.20:19:58.00#ibcon#read 6, iclass 4, count 2 2006.173.20:19:58.00#ibcon#end of sib2, iclass 4, count 2 2006.173.20:19:58.00#ibcon#*after write, iclass 4, count 2 2006.173.20:19:58.00#ibcon#*before return 0, iclass 4, count 2 2006.173.20:19:58.00#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.20:19:58.00#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.20:19:58.00#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.20:19:58.00#ibcon#ireg 7 cls_cnt 0 2006.173.20:19:58.00#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.20:19:58.12#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.20:19:58.12#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.20:19:58.12#ibcon#enter wrdev, iclass 4, count 0 2006.173.20:19:58.12#ibcon#first serial, iclass 4, count 0 2006.173.20:19:58.12#ibcon#enter sib2, iclass 4, count 0 2006.173.20:19:58.12#ibcon#flushed, iclass 4, count 0 2006.173.20:19:58.12#ibcon#about to write, iclass 4, count 0 2006.173.20:19:58.12#ibcon#wrote, iclass 4, count 0 2006.173.20:19:58.12#ibcon#about to read 3, iclass 4, count 0 2006.173.20:19:58.14#ibcon#read 3, iclass 4, count 0 2006.173.20:19:58.14#ibcon#about to read 4, iclass 4, count 0 2006.173.20:19:58.14#ibcon#read 4, iclass 4, count 0 2006.173.20:19:58.14#ibcon#about to read 5, iclass 4, count 0 2006.173.20:19:58.14#ibcon#read 5, iclass 4, count 0 2006.173.20:19:58.14#ibcon#about to read 6, iclass 4, count 0 2006.173.20:19:58.14#ibcon#read 6, iclass 4, count 0 2006.173.20:19:58.14#ibcon#end of sib2, iclass 4, count 0 2006.173.20:19:58.14#ibcon#*mode == 0, iclass 4, count 0 2006.173.20:19:58.14#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.20:19:58.14#ibcon#[27=USB\r\n] 2006.173.20:19:58.14#ibcon#*before write, iclass 4, count 0 2006.173.20:19:58.14#ibcon#enter sib2, iclass 4, count 0 2006.173.20:19:58.14#ibcon#flushed, iclass 4, count 0 2006.173.20:19:58.14#ibcon#about to write, iclass 4, count 0 2006.173.20:19:58.14#ibcon#wrote, iclass 4, count 0 2006.173.20:19:58.14#ibcon#about to read 3, iclass 4, count 0 2006.173.20:19:58.17#ibcon#read 3, iclass 4, count 0 2006.173.20:19:58.17#ibcon#about to read 4, iclass 4, count 0 2006.173.20:19:58.17#ibcon#read 4, iclass 4, count 0 2006.173.20:19:58.17#ibcon#about to read 5, iclass 4, count 0 2006.173.20:19:58.17#ibcon#read 5, iclass 4, count 0 2006.173.20:19:58.17#ibcon#about to read 6, iclass 4, count 0 2006.173.20:19:58.17#ibcon#read 6, iclass 4, count 0 2006.173.20:19:58.17#ibcon#end of sib2, iclass 4, count 0 2006.173.20:19:58.17#ibcon#*after write, iclass 4, count 0 2006.173.20:19:58.17#ibcon#*before return 0, iclass 4, count 0 2006.173.20:19:58.17#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.20:19:58.17#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.20:19:58.17#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.20:19:58.17#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.20:19:58.17$vck44/vblo=5,709.99 2006.173.20:19:58.17#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.20:19:58.17#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.20:19:58.17#ibcon#ireg 17 cls_cnt 0 2006.173.20:19:58.17#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.20:19:58.17#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.20:19:58.17#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.20:19:58.17#ibcon#enter wrdev, iclass 6, count 0 2006.173.20:19:58.17#ibcon#first serial, iclass 6, count 0 2006.173.20:19:58.17#ibcon#enter sib2, iclass 6, count 0 2006.173.20:19:58.17#ibcon#flushed, iclass 6, count 0 2006.173.20:19:58.17#ibcon#about to write, iclass 6, count 0 2006.173.20:19:58.17#ibcon#wrote, iclass 6, count 0 2006.173.20:19:58.17#ibcon#about to read 3, iclass 6, count 0 2006.173.20:19:58.19#ibcon#read 3, iclass 6, count 0 2006.173.20:19:58.19#ibcon#about to read 4, iclass 6, count 0 2006.173.20:19:58.19#ibcon#read 4, iclass 6, count 0 2006.173.20:19:58.19#ibcon#about to read 5, iclass 6, count 0 2006.173.20:19:58.19#ibcon#read 5, iclass 6, count 0 2006.173.20:19:58.19#ibcon#about to read 6, iclass 6, count 0 2006.173.20:19:58.19#ibcon#read 6, iclass 6, count 0 2006.173.20:19:58.19#ibcon#end of sib2, iclass 6, count 0 2006.173.20:19:58.19#ibcon#*mode == 0, iclass 6, count 0 2006.173.20:19:58.19#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.20:19:58.19#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.20:19:58.19#ibcon#*before write, iclass 6, count 0 2006.173.20:19:58.19#ibcon#enter sib2, iclass 6, count 0 2006.173.20:19:58.19#ibcon#flushed, iclass 6, count 0 2006.173.20:19:58.19#ibcon#about to write, iclass 6, count 0 2006.173.20:19:58.19#ibcon#wrote, iclass 6, count 0 2006.173.20:19:58.19#ibcon#about to read 3, iclass 6, count 0 2006.173.20:19:58.23#ibcon#read 3, iclass 6, count 0 2006.173.20:19:58.23#ibcon#about to read 4, iclass 6, count 0 2006.173.20:19:58.23#ibcon#read 4, iclass 6, count 0 2006.173.20:19:58.23#ibcon#about to read 5, iclass 6, count 0 2006.173.20:19:58.23#ibcon#read 5, iclass 6, count 0 2006.173.20:19:58.23#ibcon#about to read 6, iclass 6, count 0 2006.173.20:19:58.23#ibcon#read 6, iclass 6, count 0 2006.173.20:19:58.23#ibcon#end of sib2, iclass 6, count 0 2006.173.20:19:58.23#ibcon#*after write, iclass 6, count 0 2006.173.20:19:58.23#ibcon#*before return 0, iclass 6, count 0 2006.173.20:19:58.23#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.20:19:58.23#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.20:19:58.23#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.20:19:58.23#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.20:19:58.23$vck44/vb=5,4 2006.173.20:19:58.23#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.20:19:58.23#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.20:19:58.23#ibcon#ireg 11 cls_cnt 2 2006.173.20:19:58.23#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.20:19:58.29#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.20:19:58.29#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.20:19:58.29#ibcon#enter wrdev, iclass 10, count 2 2006.173.20:19:58.29#ibcon#first serial, iclass 10, count 2 2006.173.20:19:58.29#ibcon#enter sib2, iclass 10, count 2 2006.173.20:19:58.29#ibcon#flushed, iclass 10, count 2 2006.173.20:19:58.29#ibcon#about to write, iclass 10, count 2 2006.173.20:19:58.29#ibcon#wrote, iclass 10, count 2 2006.173.20:19:58.29#ibcon#about to read 3, iclass 10, count 2 2006.173.20:19:58.31#ibcon#read 3, iclass 10, count 2 2006.173.20:19:58.31#ibcon#about to read 4, iclass 10, count 2 2006.173.20:19:58.31#ibcon#read 4, iclass 10, count 2 2006.173.20:19:58.31#ibcon#about to read 5, iclass 10, count 2 2006.173.20:19:58.31#ibcon#read 5, iclass 10, count 2 2006.173.20:19:58.31#ibcon#about to read 6, iclass 10, count 2 2006.173.20:19:58.31#ibcon#read 6, iclass 10, count 2 2006.173.20:19:58.31#ibcon#end of sib2, iclass 10, count 2 2006.173.20:19:58.31#ibcon#*mode == 0, iclass 10, count 2 2006.173.20:19:58.31#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.20:19:58.31#ibcon#[27=AT05-04\r\n] 2006.173.20:19:58.31#ibcon#*before write, iclass 10, count 2 2006.173.20:19:58.31#ibcon#enter sib2, iclass 10, count 2 2006.173.20:19:58.31#ibcon#flushed, iclass 10, count 2 2006.173.20:19:58.31#ibcon#about to write, iclass 10, count 2 2006.173.20:19:58.31#ibcon#wrote, iclass 10, count 2 2006.173.20:19:58.31#ibcon#about to read 3, iclass 10, count 2 2006.173.20:19:58.34#ibcon#read 3, iclass 10, count 2 2006.173.20:19:58.34#ibcon#about to read 4, iclass 10, count 2 2006.173.20:19:58.34#ibcon#read 4, iclass 10, count 2 2006.173.20:19:58.34#ibcon#about to read 5, iclass 10, count 2 2006.173.20:19:58.34#ibcon#read 5, iclass 10, count 2 2006.173.20:19:58.34#ibcon#about to read 6, iclass 10, count 2 2006.173.20:19:58.34#ibcon#read 6, iclass 10, count 2 2006.173.20:19:58.34#ibcon#end of sib2, iclass 10, count 2 2006.173.20:19:58.34#ibcon#*after write, iclass 10, count 2 2006.173.20:19:58.34#ibcon#*before return 0, iclass 10, count 2 2006.173.20:19:58.34#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.20:19:58.34#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.20:19:58.34#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.20:19:58.34#ibcon#ireg 7 cls_cnt 0 2006.173.20:19:58.34#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.20:19:58.46#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.20:19:58.46#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.20:19:58.46#ibcon#enter wrdev, iclass 10, count 0 2006.173.20:19:58.46#ibcon#first serial, iclass 10, count 0 2006.173.20:19:58.46#ibcon#enter sib2, iclass 10, count 0 2006.173.20:19:58.46#ibcon#flushed, iclass 10, count 0 2006.173.20:19:58.46#ibcon#about to write, iclass 10, count 0 2006.173.20:19:58.46#ibcon#wrote, iclass 10, count 0 2006.173.20:19:58.46#ibcon#about to read 3, iclass 10, count 0 2006.173.20:19:58.48#ibcon#read 3, iclass 10, count 0 2006.173.20:19:58.48#ibcon#about to read 4, iclass 10, count 0 2006.173.20:19:58.48#ibcon#read 4, iclass 10, count 0 2006.173.20:19:58.48#ibcon#about to read 5, iclass 10, count 0 2006.173.20:19:58.48#ibcon#read 5, iclass 10, count 0 2006.173.20:19:58.48#ibcon#about to read 6, iclass 10, count 0 2006.173.20:19:58.48#ibcon#read 6, iclass 10, count 0 2006.173.20:19:58.48#ibcon#end of sib2, iclass 10, count 0 2006.173.20:19:58.48#ibcon#*mode == 0, iclass 10, count 0 2006.173.20:19:58.48#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.20:19:58.48#ibcon#[27=USB\r\n] 2006.173.20:19:58.48#ibcon#*before write, iclass 10, count 0 2006.173.20:19:58.48#ibcon#enter sib2, iclass 10, count 0 2006.173.20:19:58.48#ibcon#flushed, iclass 10, count 0 2006.173.20:19:58.48#ibcon#about to write, iclass 10, count 0 2006.173.20:19:58.48#ibcon#wrote, iclass 10, count 0 2006.173.20:19:58.48#ibcon#about to read 3, iclass 10, count 0 2006.173.20:19:58.51#ibcon#read 3, iclass 10, count 0 2006.173.20:19:58.51#ibcon#about to read 4, iclass 10, count 0 2006.173.20:19:58.51#ibcon#read 4, iclass 10, count 0 2006.173.20:19:58.51#ibcon#about to read 5, iclass 10, count 0 2006.173.20:19:58.51#ibcon#read 5, iclass 10, count 0 2006.173.20:19:58.51#ibcon#about to read 6, iclass 10, count 0 2006.173.20:19:58.51#ibcon#read 6, iclass 10, count 0 2006.173.20:19:58.51#ibcon#end of sib2, iclass 10, count 0 2006.173.20:19:58.51#ibcon#*after write, iclass 10, count 0 2006.173.20:19:58.51#ibcon#*before return 0, iclass 10, count 0 2006.173.20:19:58.51#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.20:19:58.51#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.20:19:58.51#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.20:19:58.51#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.20:19:58.51$vck44/vblo=6,719.99 2006.173.20:19:58.51#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.20:19:58.51#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.20:19:58.51#ibcon#ireg 17 cls_cnt 0 2006.173.20:19:58.51#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.20:19:58.51#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.20:19:58.51#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.20:19:58.51#ibcon#enter wrdev, iclass 12, count 0 2006.173.20:19:58.51#ibcon#first serial, iclass 12, count 0 2006.173.20:19:58.51#ibcon#enter sib2, iclass 12, count 0 2006.173.20:19:58.51#ibcon#flushed, iclass 12, count 0 2006.173.20:19:58.51#ibcon#about to write, iclass 12, count 0 2006.173.20:19:58.51#ibcon#wrote, iclass 12, count 0 2006.173.20:19:58.51#ibcon#about to read 3, iclass 12, count 0 2006.173.20:19:58.53#ibcon#read 3, iclass 12, count 0 2006.173.20:19:58.53#ibcon#about to read 4, iclass 12, count 0 2006.173.20:19:58.53#ibcon#read 4, iclass 12, count 0 2006.173.20:19:58.53#ibcon#about to read 5, iclass 12, count 0 2006.173.20:19:58.53#ibcon#read 5, iclass 12, count 0 2006.173.20:19:58.53#ibcon#about to read 6, iclass 12, count 0 2006.173.20:19:58.53#ibcon#read 6, iclass 12, count 0 2006.173.20:19:58.53#ibcon#end of sib2, iclass 12, count 0 2006.173.20:19:58.53#ibcon#*mode == 0, iclass 12, count 0 2006.173.20:19:58.53#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.20:19:58.53#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.20:19:58.53#ibcon#*before write, iclass 12, count 0 2006.173.20:19:58.53#ibcon#enter sib2, iclass 12, count 0 2006.173.20:19:58.53#ibcon#flushed, iclass 12, count 0 2006.173.20:19:58.53#ibcon#about to write, iclass 12, count 0 2006.173.20:19:58.53#ibcon#wrote, iclass 12, count 0 2006.173.20:19:58.53#ibcon#about to read 3, iclass 12, count 0 2006.173.20:19:58.57#ibcon#read 3, iclass 12, count 0 2006.173.20:19:58.57#ibcon#about to read 4, iclass 12, count 0 2006.173.20:19:58.57#ibcon#read 4, iclass 12, count 0 2006.173.20:19:58.57#ibcon#about to read 5, iclass 12, count 0 2006.173.20:19:58.57#ibcon#read 5, iclass 12, count 0 2006.173.20:19:58.57#ibcon#about to read 6, iclass 12, count 0 2006.173.20:19:58.57#ibcon#read 6, iclass 12, count 0 2006.173.20:19:58.57#ibcon#end of sib2, iclass 12, count 0 2006.173.20:19:58.57#ibcon#*after write, iclass 12, count 0 2006.173.20:19:58.57#ibcon#*before return 0, iclass 12, count 0 2006.173.20:19:58.57#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.20:19:58.57#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.20:19:58.57#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.20:19:58.57#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.20:19:58.57$vck44/vb=6,4 2006.173.20:19:58.57#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.20:19:58.57#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.20:19:58.57#ibcon#ireg 11 cls_cnt 2 2006.173.20:19:58.57#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.20:19:58.63#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.20:19:58.63#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.20:19:58.63#ibcon#enter wrdev, iclass 14, count 2 2006.173.20:19:58.63#ibcon#first serial, iclass 14, count 2 2006.173.20:19:58.63#ibcon#enter sib2, iclass 14, count 2 2006.173.20:19:58.63#ibcon#flushed, iclass 14, count 2 2006.173.20:19:58.63#ibcon#about to write, iclass 14, count 2 2006.173.20:19:58.63#ibcon#wrote, iclass 14, count 2 2006.173.20:19:58.63#ibcon#about to read 3, iclass 14, count 2 2006.173.20:19:58.65#ibcon#read 3, iclass 14, count 2 2006.173.20:19:58.65#ibcon#about to read 4, iclass 14, count 2 2006.173.20:19:58.65#ibcon#read 4, iclass 14, count 2 2006.173.20:19:58.65#ibcon#about to read 5, iclass 14, count 2 2006.173.20:19:58.65#ibcon#read 5, iclass 14, count 2 2006.173.20:19:58.65#ibcon#about to read 6, iclass 14, count 2 2006.173.20:19:58.65#ibcon#read 6, iclass 14, count 2 2006.173.20:19:58.65#ibcon#end of sib2, iclass 14, count 2 2006.173.20:19:58.65#ibcon#*mode == 0, iclass 14, count 2 2006.173.20:19:58.65#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.20:19:58.65#ibcon#[27=AT06-04\r\n] 2006.173.20:19:58.65#ibcon#*before write, iclass 14, count 2 2006.173.20:19:58.65#ibcon#enter sib2, iclass 14, count 2 2006.173.20:19:58.65#ibcon#flushed, iclass 14, count 2 2006.173.20:19:58.65#ibcon#about to write, iclass 14, count 2 2006.173.20:19:58.65#ibcon#wrote, iclass 14, count 2 2006.173.20:19:58.65#ibcon#about to read 3, iclass 14, count 2 2006.173.20:19:58.68#ibcon#read 3, iclass 14, count 2 2006.173.20:19:58.68#ibcon#about to read 4, iclass 14, count 2 2006.173.20:19:58.68#ibcon#read 4, iclass 14, count 2 2006.173.20:19:58.68#ibcon#about to read 5, iclass 14, count 2 2006.173.20:19:58.68#ibcon#read 5, iclass 14, count 2 2006.173.20:19:58.68#ibcon#about to read 6, iclass 14, count 2 2006.173.20:19:58.68#ibcon#read 6, iclass 14, count 2 2006.173.20:19:58.68#ibcon#end of sib2, iclass 14, count 2 2006.173.20:19:58.68#ibcon#*after write, iclass 14, count 2 2006.173.20:19:58.68#ibcon#*before return 0, iclass 14, count 2 2006.173.20:19:58.68#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.20:19:58.68#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.20:19:58.68#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.20:19:58.68#ibcon#ireg 7 cls_cnt 0 2006.173.20:19:58.68#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.20:19:58.80#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.20:19:58.80#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.20:19:58.80#ibcon#enter wrdev, iclass 14, count 0 2006.173.20:19:58.80#ibcon#first serial, iclass 14, count 0 2006.173.20:19:58.80#ibcon#enter sib2, iclass 14, count 0 2006.173.20:19:58.80#ibcon#flushed, iclass 14, count 0 2006.173.20:19:58.80#ibcon#about to write, iclass 14, count 0 2006.173.20:19:58.80#ibcon#wrote, iclass 14, count 0 2006.173.20:19:58.80#ibcon#about to read 3, iclass 14, count 0 2006.173.20:19:58.82#ibcon#read 3, iclass 14, count 0 2006.173.20:19:58.82#ibcon#about to read 4, iclass 14, count 0 2006.173.20:19:58.82#ibcon#read 4, iclass 14, count 0 2006.173.20:19:58.82#ibcon#about to read 5, iclass 14, count 0 2006.173.20:19:58.82#ibcon#read 5, iclass 14, count 0 2006.173.20:19:58.82#ibcon#about to read 6, iclass 14, count 0 2006.173.20:19:58.82#ibcon#read 6, iclass 14, count 0 2006.173.20:19:58.82#ibcon#end of sib2, iclass 14, count 0 2006.173.20:19:58.82#ibcon#*mode == 0, iclass 14, count 0 2006.173.20:19:58.82#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.20:19:58.82#ibcon#[27=USB\r\n] 2006.173.20:19:58.82#ibcon#*before write, iclass 14, count 0 2006.173.20:19:58.82#ibcon#enter sib2, iclass 14, count 0 2006.173.20:19:58.82#ibcon#flushed, iclass 14, count 0 2006.173.20:19:58.82#ibcon#about to write, iclass 14, count 0 2006.173.20:19:58.82#ibcon#wrote, iclass 14, count 0 2006.173.20:19:58.82#ibcon#about to read 3, iclass 14, count 0 2006.173.20:19:58.85#ibcon#read 3, iclass 14, count 0 2006.173.20:19:58.85#ibcon#about to read 4, iclass 14, count 0 2006.173.20:19:58.85#ibcon#read 4, iclass 14, count 0 2006.173.20:19:58.85#ibcon#about to read 5, iclass 14, count 0 2006.173.20:19:58.85#ibcon#read 5, iclass 14, count 0 2006.173.20:19:58.85#ibcon#about to read 6, iclass 14, count 0 2006.173.20:19:58.85#ibcon#read 6, iclass 14, count 0 2006.173.20:19:58.85#ibcon#end of sib2, iclass 14, count 0 2006.173.20:19:58.85#ibcon#*after write, iclass 14, count 0 2006.173.20:19:58.85#ibcon#*before return 0, iclass 14, count 0 2006.173.20:19:58.85#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.20:19:58.85#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.20:19:58.85#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.20:19:58.85#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.20:19:58.85$vck44/vblo=7,734.99 2006.173.20:19:58.85#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.20:19:58.85#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.20:19:58.85#ibcon#ireg 17 cls_cnt 0 2006.173.20:19:58.85#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.20:19:58.85#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.20:19:58.85#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.20:19:58.85#ibcon#enter wrdev, iclass 16, count 0 2006.173.20:19:58.85#ibcon#first serial, iclass 16, count 0 2006.173.20:19:58.85#ibcon#enter sib2, iclass 16, count 0 2006.173.20:19:58.85#ibcon#flushed, iclass 16, count 0 2006.173.20:19:58.85#ibcon#about to write, iclass 16, count 0 2006.173.20:19:58.85#ibcon#wrote, iclass 16, count 0 2006.173.20:19:58.85#ibcon#about to read 3, iclass 16, count 0 2006.173.20:19:58.87#ibcon#read 3, iclass 16, count 0 2006.173.20:19:58.87#ibcon#about to read 4, iclass 16, count 0 2006.173.20:19:58.87#ibcon#read 4, iclass 16, count 0 2006.173.20:19:58.87#ibcon#about to read 5, iclass 16, count 0 2006.173.20:19:58.87#ibcon#read 5, iclass 16, count 0 2006.173.20:19:58.87#ibcon#about to read 6, iclass 16, count 0 2006.173.20:19:58.87#ibcon#read 6, iclass 16, count 0 2006.173.20:19:58.87#ibcon#end of sib2, iclass 16, count 0 2006.173.20:19:58.87#ibcon#*mode == 0, iclass 16, count 0 2006.173.20:19:58.87#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.20:19:58.87#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.20:19:58.87#ibcon#*before write, iclass 16, count 0 2006.173.20:19:58.87#ibcon#enter sib2, iclass 16, count 0 2006.173.20:19:58.87#ibcon#flushed, iclass 16, count 0 2006.173.20:19:58.87#ibcon#about to write, iclass 16, count 0 2006.173.20:19:58.87#ibcon#wrote, iclass 16, count 0 2006.173.20:19:58.87#ibcon#about to read 3, iclass 16, count 0 2006.173.20:19:58.91#ibcon#read 3, iclass 16, count 0 2006.173.20:19:58.91#ibcon#about to read 4, iclass 16, count 0 2006.173.20:19:58.91#ibcon#read 4, iclass 16, count 0 2006.173.20:19:58.91#ibcon#about to read 5, iclass 16, count 0 2006.173.20:19:58.91#ibcon#read 5, iclass 16, count 0 2006.173.20:19:58.91#ibcon#about to read 6, iclass 16, count 0 2006.173.20:19:58.91#ibcon#read 6, iclass 16, count 0 2006.173.20:19:58.91#ibcon#end of sib2, iclass 16, count 0 2006.173.20:19:58.91#ibcon#*after write, iclass 16, count 0 2006.173.20:19:58.91#ibcon#*before return 0, iclass 16, count 0 2006.173.20:19:58.91#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.20:19:58.91#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.20:19:58.91#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.20:19:58.91#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.20:19:58.91$vck44/vb=7,4 2006.173.20:19:58.91#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.20:19:58.91#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.20:19:58.91#ibcon#ireg 11 cls_cnt 2 2006.173.20:19:58.91#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.20:19:58.97#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.20:19:58.97#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.20:19:58.97#ibcon#enter wrdev, iclass 18, count 2 2006.173.20:19:58.97#ibcon#first serial, iclass 18, count 2 2006.173.20:19:58.97#ibcon#enter sib2, iclass 18, count 2 2006.173.20:19:58.97#ibcon#flushed, iclass 18, count 2 2006.173.20:19:58.97#ibcon#about to write, iclass 18, count 2 2006.173.20:19:58.97#ibcon#wrote, iclass 18, count 2 2006.173.20:19:58.97#ibcon#about to read 3, iclass 18, count 2 2006.173.20:19:58.99#ibcon#read 3, iclass 18, count 2 2006.173.20:19:58.99#ibcon#about to read 4, iclass 18, count 2 2006.173.20:19:58.99#ibcon#read 4, iclass 18, count 2 2006.173.20:19:58.99#ibcon#about to read 5, iclass 18, count 2 2006.173.20:19:58.99#ibcon#read 5, iclass 18, count 2 2006.173.20:19:58.99#ibcon#about to read 6, iclass 18, count 2 2006.173.20:19:58.99#ibcon#read 6, iclass 18, count 2 2006.173.20:19:58.99#ibcon#end of sib2, iclass 18, count 2 2006.173.20:19:58.99#ibcon#*mode == 0, iclass 18, count 2 2006.173.20:19:58.99#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.20:19:58.99#ibcon#[27=AT07-04\r\n] 2006.173.20:19:58.99#ibcon#*before write, iclass 18, count 2 2006.173.20:19:58.99#ibcon#enter sib2, iclass 18, count 2 2006.173.20:19:58.99#ibcon#flushed, iclass 18, count 2 2006.173.20:19:58.99#ibcon#about to write, iclass 18, count 2 2006.173.20:19:58.99#ibcon#wrote, iclass 18, count 2 2006.173.20:19:58.99#ibcon#about to read 3, iclass 18, count 2 2006.173.20:19:59.02#ibcon#read 3, iclass 18, count 2 2006.173.20:19:59.02#ibcon#about to read 4, iclass 18, count 2 2006.173.20:19:59.02#ibcon#read 4, iclass 18, count 2 2006.173.20:19:59.02#ibcon#about to read 5, iclass 18, count 2 2006.173.20:19:59.02#ibcon#read 5, iclass 18, count 2 2006.173.20:19:59.02#ibcon#about to read 6, iclass 18, count 2 2006.173.20:19:59.02#ibcon#read 6, iclass 18, count 2 2006.173.20:19:59.02#ibcon#end of sib2, iclass 18, count 2 2006.173.20:19:59.02#ibcon#*after write, iclass 18, count 2 2006.173.20:19:59.02#ibcon#*before return 0, iclass 18, count 2 2006.173.20:19:59.02#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.20:19:59.02#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.20:19:59.02#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.20:19:59.02#ibcon#ireg 7 cls_cnt 0 2006.173.20:19:59.02#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.20:19:59.14#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.20:19:59.14#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.20:19:59.14#ibcon#enter wrdev, iclass 18, count 0 2006.173.20:19:59.14#ibcon#first serial, iclass 18, count 0 2006.173.20:19:59.14#ibcon#enter sib2, iclass 18, count 0 2006.173.20:19:59.14#ibcon#flushed, iclass 18, count 0 2006.173.20:19:59.14#ibcon#about to write, iclass 18, count 0 2006.173.20:19:59.14#ibcon#wrote, iclass 18, count 0 2006.173.20:19:59.14#ibcon#about to read 3, iclass 18, count 0 2006.173.20:19:59.16#ibcon#read 3, iclass 18, count 0 2006.173.20:19:59.16#ibcon#about to read 4, iclass 18, count 0 2006.173.20:19:59.16#ibcon#read 4, iclass 18, count 0 2006.173.20:19:59.16#ibcon#about to read 5, iclass 18, count 0 2006.173.20:19:59.16#ibcon#read 5, iclass 18, count 0 2006.173.20:19:59.16#ibcon#about to read 6, iclass 18, count 0 2006.173.20:19:59.16#ibcon#read 6, iclass 18, count 0 2006.173.20:19:59.16#ibcon#end of sib2, iclass 18, count 0 2006.173.20:19:59.16#ibcon#*mode == 0, iclass 18, count 0 2006.173.20:19:59.16#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.20:19:59.16#ibcon#[27=USB\r\n] 2006.173.20:19:59.16#ibcon#*before write, iclass 18, count 0 2006.173.20:19:59.16#ibcon#enter sib2, iclass 18, count 0 2006.173.20:19:59.16#ibcon#flushed, iclass 18, count 0 2006.173.20:19:59.16#ibcon#about to write, iclass 18, count 0 2006.173.20:19:59.16#ibcon#wrote, iclass 18, count 0 2006.173.20:19:59.16#ibcon#about to read 3, iclass 18, count 0 2006.173.20:19:59.19#ibcon#read 3, iclass 18, count 0 2006.173.20:19:59.19#ibcon#about to read 4, iclass 18, count 0 2006.173.20:19:59.19#ibcon#read 4, iclass 18, count 0 2006.173.20:19:59.19#ibcon#about to read 5, iclass 18, count 0 2006.173.20:19:59.19#ibcon#read 5, iclass 18, count 0 2006.173.20:19:59.19#ibcon#about to read 6, iclass 18, count 0 2006.173.20:19:59.19#ibcon#read 6, iclass 18, count 0 2006.173.20:19:59.19#ibcon#end of sib2, iclass 18, count 0 2006.173.20:19:59.19#ibcon#*after write, iclass 18, count 0 2006.173.20:19:59.19#ibcon#*before return 0, iclass 18, count 0 2006.173.20:19:59.19#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.20:19:59.19#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.20:19:59.19#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.20:19:59.19#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.20:19:59.19$vck44/vblo=8,744.99 2006.173.20:19:59.19#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.20:19:59.19#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.20:19:59.19#ibcon#ireg 17 cls_cnt 0 2006.173.20:19:59.19#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.20:19:59.19#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.20:19:59.19#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.20:19:59.19#ibcon#enter wrdev, iclass 20, count 0 2006.173.20:19:59.19#ibcon#first serial, iclass 20, count 0 2006.173.20:19:59.19#ibcon#enter sib2, iclass 20, count 0 2006.173.20:19:59.19#ibcon#flushed, iclass 20, count 0 2006.173.20:19:59.19#ibcon#about to write, iclass 20, count 0 2006.173.20:19:59.19#ibcon#wrote, iclass 20, count 0 2006.173.20:19:59.19#ibcon#about to read 3, iclass 20, count 0 2006.173.20:19:59.21#ibcon#read 3, iclass 20, count 0 2006.173.20:19:59.21#ibcon#about to read 4, iclass 20, count 0 2006.173.20:19:59.21#ibcon#read 4, iclass 20, count 0 2006.173.20:19:59.21#ibcon#about to read 5, iclass 20, count 0 2006.173.20:19:59.21#ibcon#read 5, iclass 20, count 0 2006.173.20:19:59.21#ibcon#about to read 6, iclass 20, count 0 2006.173.20:19:59.21#ibcon#read 6, iclass 20, count 0 2006.173.20:19:59.21#ibcon#end of sib2, iclass 20, count 0 2006.173.20:19:59.21#ibcon#*mode == 0, iclass 20, count 0 2006.173.20:19:59.21#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.20:19:59.21#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.20:19:59.21#ibcon#*before write, iclass 20, count 0 2006.173.20:19:59.21#ibcon#enter sib2, iclass 20, count 0 2006.173.20:19:59.21#ibcon#flushed, iclass 20, count 0 2006.173.20:19:59.21#ibcon#about to write, iclass 20, count 0 2006.173.20:19:59.21#ibcon#wrote, iclass 20, count 0 2006.173.20:19:59.21#ibcon#about to read 3, iclass 20, count 0 2006.173.20:19:59.25#ibcon#read 3, iclass 20, count 0 2006.173.20:19:59.25#ibcon#about to read 4, iclass 20, count 0 2006.173.20:19:59.25#ibcon#read 4, iclass 20, count 0 2006.173.20:19:59.25#ibcon#about to read 5, iclass 20, count 0 2006.173.20:19:59.25#ibcon#read 5, iclass 20, count 0 2006.173.20:19:59.25#ibcon#about to read 6, iclass 20, count 0 2006.173.20:19:59.25#ibcon#read 6, iclass 20, count 0 2006.173.20:19:59.25#ibcon#end of sib2, iclass 20, count 0 2006.173.20:19:59.25#ibcon#*after write, iclass 20, count 0 2006.173.20:19:59.25#ibcon#*before return 0, iclass 20, count 0 2006.173.20:19:59.25#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.20:19:59.25#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.20:19:59.25#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.20:19:59.25#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.20:19:59.25$vck44/vb=8,4 2006.173.20:19:59.25#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.20:19:59.25#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.20:19:59.25#ibcon#ireg 11 cls_cnt 2 2006.173.20:19:59.25#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.20:19:59.31#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.20:19:59.31#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.20:19:59.31#ibcon#enter wrdev, iclass 22, count 2 2006.173.20:19:59.31#ibcon#first serial, iclass 22, count 2 2006.173.20:19:59.31#ibcon#enter sib2, iclass 22, count 2 2006.173.20:19:59.31#ibcon#flushed, iclass 22, count 2 2006.173.20:19:59.31#ibcon#about to write, iclass 22, count 2 2006.173.20:19:59.31#ibcon#wrote, iclass 22, count 2 2006.173.20:19:59.31#ibcon#about to read 3, iclass 22, count 2 2006.173.20:19:59.33#ibcon#read 3, iclass 22, count 2 2006.173.20:19:59.33#ibcon#about to read 4, iclass 22, count 2 2006.173.20:19:59.33#ibcon#read 4, iclass 22, count 2 2006.173.20:19:59.33#ibcon#about to read 5, iclass 22, count 2 2006.173.20:19:59.33#ibcon#read 5, iclass 22, count 2 2006.173.20:19:59.33#ibcon#about to read 6, iclass 22, count 2 2006.173.20:19:59.33#ibcon#read 6, iclass 22, count 2 2006.173.20:19:59.33#ibcon#end of sib2, iclass 22, count 2 2006.173.20:19:59.33#ibcon#*mode == 0, iclass 22, count 2 2006.173.20:19:59.33#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.20:19:59.33#ibcon#[27=AT08-04\r\n] 2006.173.20:19:59.33#ibcon#*before write, iclass 22, count 2 2006.173.20:19:59.33#ibcon#enter sib2, iclass 22, count 2 2006.173.20:19:59.33#ibcon#flushed, iclass 22, count 2 2006.173.20:19:59.33#ibcon#about to write, iclass 22, count 2 2006.173.20:19:59.33#ibcon#wrote, iclass 22, count 2 2006.173.20:19:59.33#ibcon#about to read 3, iclass 22, count 2 2006.173.20:19:59.36#ibcon#read 3, iclass 22, count 2 2006.173.20:19:59.36#ibcon#about to read 4, iclass 22, count 2 2006.173.20:19:59.36#ibcon#read 4, iclass 22, count 2 2006.173.20:19:59.36#ibcon#about to read 5, iclass 22, count 2 2006.173.20:19:59.36#ibcon#read 5, iclass 22, count 2 2006.173.20:19:59.36#ibcon#about to read 6, iclass 22, count 2 2006.173.20:19:59.36#ibcon#read 6, iclass 22, count 2 2006.173.20:19:59.36#ibcon#end of sib2, iclass 22, count 2 2006.173.20:19:59.36#ibcon#*after write, iclass 22, count 2 2006.173.20:19:59.36#ibcon#*before return 0, iclass 22, count 2 2006.173.20:19:59.36#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.20:19:59.36#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.20:19:59.36#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.20:19:59.36#ibcon#ireg 7 cls_cnt 0 2006.173.20:19:59.36#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.20:19:59.48#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.20:19:59.48#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.20:19:59.48#ibcon#enter wrdev, iclass 22, count 0 2006.173.20:19:59.48#ibcon#first serial, iclass 22, count 0 2006.173.20:19:59.48#ibcon#enter sib2, iclass 22, count 0 2006.173.20:19:59.48#ibcon#flushed, iclass 22, count 0 2006.173.20:19:59.48#ibcon#about to write, iclass 22, count 0 2006.173.20:19:59.48#ibcon#wrote, iclass 22, count 0 2006.173.20:19:59.48#ibcon#about to read 3, iclass 22, count 0 2006.173.20:19:59.50#ibcon#read 3, iclass 22, count 0 2006.173.20:19:59.50#ibcon#about to read 4, iclass 22, count 0 2006.173.20:19:59.50#ibcon#read 4, iclass 22, count 0 2006.173.20:19:59.50#ibcon#about to read 5, iclass 22, count 0 2006.173.20:19:59.50#ibcon#read 5, iclass 22, count 0 2006.173.20:19:59.50#ibcon#about to read 6, iclass 22, count 0 2006.173.20:19:59.50#ibcon#read 6, iclass 22, count 0 2006.173.20:19:59.50#ibcon#end of sib2, iclass 22, count 0 2006.173.20:19:59.50#ibcon#*mode == 0, iclass 22, count 0 2006.173.20:19:59.50#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.20:19:59.50#ibcon#[27=USB\r\n] 2006.173.20:19:59.50#ibcon#*before write, iclass 22, count 0 2006.173.20:19:59.50#ibcon#enter sib2, iclass 22, count 0 2006.173.20:19:59.50#ibcon#flushed, iclass 22, count 0 2006.173.20:19:59.50#ibcon#about to write, iclass 22, count 0 2006.173.20:19:59.50#ibcon#wrote, iclass 22, count 0 2006.173.20:19:59.50#ibcon#about to read 3, iclass 22, count 0 2006.173.20:19:59.53#ibcon#read 3, iclass 22, count 0 2006.173.20:19:59.53#ibcon#about to read 4, iclass 22, count 0 2006.173.20:19:59.53#ibcon#read 4, iclass 22, count 0 2006.173.20:19:59.53#ibcon#about to read 5, iclass 22, count 0 2006.173.20:19:59.53#ibcon#read 5, iclass 22, count 0 2006.173.20:19:59.53#ibcon#about to read 6, iclass 22, count 0 2006.173.20:19:59.53#ibcon#read 6, iclass 22, count 0 2006.173.20:19:59.53#ibcon#end of sib2, iclass 22, count 0 2006.173.20:19:59.53#ibcon#*after write, iclass 22, count 0 2006.173.20:19:59.53#ibcon#*before return 0, iclass 22, count 0 2006.173.20:19:59.53#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.20:19:59.53#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.20:19:59.53#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.20:19:59.53#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.20:19:59.53$vck44/vabw=wide 2006.173.20:19:59.53#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.20:19:59.53#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.20:19:59.53#ibcon#ireg 8 cls_cnt 0 2006.173.20:19:59.53#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.20:19:59.53#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.20:19:59.53#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.20:19:59.53#ibcon#enter wrdev, iclass 24, count 0 2006.173.20:19:59.53#ibcon#first serial, iclass 24, count 0 2006.173.20:19:59.53#ibcon#enter sib2, iclass 24, count 0 2006.173.20:19:59.53#ibcon#flushed, iclass 24, count 0 2006.173.20:19:59.53#ibcon#about to write, iclass 24, count 0 2006.173.20:19:59.53#ibcon#wrote, iclass 24, count 0 2006.173.20:19:59.53#ibcon#about to read 3, iclass 24, count 0 2006.173.20:19:59.55#ibcon#read 3, iclass 24, count 0 2006.173.20:19:59.55#ibcon#about to read 4, iclass 24, count 0 2006.173.20:19:59.55#ibcon#read 4, iclass 24, count 0 2006.173.20:19:59.55#ibcon#about to read 5, iclass 24, count 0 2006.173.20:19:59.55#ibcon#read 5, iclass 24, count 0 2006.173.20:19:59.55#ibcon#about to read 6, iclass 24, count 0 2006.173.20:19:59.55#ibcon#read 6, iclass 24, count 0 2006.173.20:19:59.55#ibcon#end of sib2, iclass 24, count 0 2006.173.20:19:59.55#ibcon#*mode == 0, iclass 24, count 0 2006.173.20:19:59.55#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.20:19:59.55#ibcon#[25=BW32\r\n] 2006.173.20:19:59.55#ibcon#*before write, iclass 24, count 0 2006.173.20:19:59.55#ibcon#enter sib2, iclass 24, count 0 2006.173.20:19:59.55#ibcon#flushed, iclass 24, count 0 2006.173.20:19:59.55#ibcon#about to write, iclass 24, count 0 2006.173.20:19:59.55#ibcon#wrote, iclass 24, count 0 2006.173.20:19:59.55#ibcon#about to read 3, iclass 24, count 0 2006.173.20:19:59.58#ibcon#read 3, iclass 24, count 0 2006.173.20:19:59.58#ibcon#about to read 4, iclass 24, count 0 2006.173.20:19:59.58#ibcon#read 4, iclass 24, count 0 2006.173.20:19:59.58#ibcon#about to read 5, iclass 24, count 0 2006.173.20:19:59.58#ibcon#read 5, iclass 24, count 0 2006.173.20:19:59.58#ibcon#about to read 6, iclass 24, count 0 2006.173.20:19:59.58#ibcon#read 6, iclass 24, count 0 2006.173.20:19:59.58#ibcon#end of sib2, iclass 24, count 0 2006.173.20:19:59.58#ibcon#*after write, iclass 24, count 0 2006.173.20:19:59.58#ibcon#*before return 0, iclass 24, count 0 2006.173.20:19:59.58#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.20:19:59.58#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.20:19:59.58#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.20:19:59.58#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.20:19:59.58$vck44/vbbw=wide 2006.173.20:19:59.58#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.20:19:59.58#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.20:19:59.58#ibcon#ireg 8 cls_cnt 0 2006.173.20:19:59.58#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.20:19:59.65#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.20:19:59.65#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.20:19:59.65#ibcon#enter wrdev, iclass 26, count 0 2006.173.20:19:59.65#ibcon#first serial, iclass 26, count 0 2006.173.20:19:59.65#ibcon#enter sib2, iclass 26, count 0 2006.173.20:19:59.65#ibcon#flushed, iclass 26, count 0 2006.173.20:19:59.65#ibcon#about to write, iclass 26, count 0 2006.173.20:19:59.65#ibcon#wrote, iclass 26, count 0 2006.173.20:19:59.65#ibcon#about to read 3, iclass 26, count 0 2006.173.20:19:59.67#ibcon#read 3, iclass 26, count 0 2006.173.20:19:59.67#ibcon#about to read 4, iclass 26, count 0 2006.173.20:19:59.67#ibcon#read 4, iclass 26, count 0 2006.173.20:19:59.67#ibcon#about to read 5, iclass 26, count 0 2006.173.20:19:59.67#ibcon#read 5, iclass 26, count 0 2006.173.20:19:59.67#ibcon#about to read 6, iclass 26, count 0 2006.173.20:19:59.67#ibcon#read 6, iclass 26, count 0 2006.173.20:19:59.67#ibcon#end of sib2, iclass 26, count 0 2006.173.20:19:59.67#ibcon#*mode == 0, iclass 26, count 0 2006.173.20:19:59.67#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.20:19:59.67#ibcon#[27=BW32\r\n] 2006.173.20:19:59.67#ibcon#*before write, iclass 26, count 0 2006.173.20:19:59.67#ibcon#enter sib2, iclass 26, count 0 2006.173.20:19:59.67#ibcon#flushed, iclass 26, count 0 2006.173.20:19:59.67#ibcon#about to write, iclass 26, count 0 2006.173.20:19:59.67#ibcon#wrote, iclass 26, count 0 2006.173.20:19:59.67#ibcon#about to read 3, iclass 26, count 0 2006.173.20:19:59.70#ibcon#read 3, iclass 26, count 0 2006.173.20:19:59.70#ibcon#about to read 4, iclass 26, count 0 2006.173.20:19:59.70#ibcon#read 4, iclass 26, count 0 2006.173.20:19:59.70#ibcon#about to read 5, iclass 26, count 0 2006.173.20:19:59.70#ibcon#read 5, iclass 26, count 0 2006.173.20:19:59.70#ibcon#about to read 6, iclass 26, count 0 2006.173.20:19:59.70#ibcon#read 6, iclass 26, count 0 2006.173.20:19:59.70#ibcon#end of sib2, iclass 26, count 0 2006.173.20:19:59.70#ibcon#*after write, iclass 26, count 0 2006.173.20:19:59.70#ibcon#*before return 0, iclass 26, count 0 2006.173.20:19:59.70#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.20:19:59.70#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.20:19:59.70#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.20:19:59.70#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.20:19:59.70$setupk4/ifdk4 2006.173.20:19:59.70$ifdk4/lo= 2006.173.20:19:59.70$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.20:19:59.70$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.20:19:59.70$ifdk4/patch= 2006.173.20:19:59.70$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.20:19:59.70$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.20:19:59.70$setupk4/!*+20s 2006.173.20:20:07.48#abcon#<5=/07 0.5 0.9 19.661001002.9\r\n> 2006.173.20:20:07.50#abcon#{5=INTERFACE CLEAR} 2006.173.20:20:07.56#abcon#[5=S1D000X0/0*\r\n] 2006.173.20:20:14.20$setupk4/"tpicd 2006.173.20:20:14.20$setupk4/echo=off 2006.173.20:20:14.20$setupk4/xlog=off 2006.173.20:20:14.20:!2006.173.20:21:59 2006.173.20:20:15.13#trakl#Source acquired 2006.173.20:20:17.13#flagr#flagr/antenna,acquired 2006.173.20:21:59.00:preob 2006.173.20:22:00.14/onsource/TRACKING 2006.173.20:22:00.14:!2006.173.20:22:09 2006.173.20:22:09.00:"tape 2006.173.20:22:09.00:"st=record 2006.173.20:22:09.00:data_valid=on 2006.173.20:22:09.00:midob 2006.173.20:22:09.14/onsource/TRACKING 2006.173.20:22:09.14/wx/19.76,1002.9,100 2006.173.20:22:09.24/cable/+6.5165E-03 2006.173.20:22:10.33/va/01,07,usb,yes,35,37 2006.173.20:22:10.33/va/02,06,usb,yes,34,35 2006.173.20:22:10.33/va/03,05,usb,yes,44,46 2006.173.20:22:10.33/va/04,06,usb,yes,35,37 2006.173.20:22:10.33/va/05,04,usb,yes,27,28 2006.173.20:22:10.33/va/06,03,usb,yes,38,38 2006.173.20:22:10.33/va/07,04,usb,yes,31,32 2006.173.20:22:10.33/va/08,04,usb,yes,26,32 2006.173.20:22:10.56/valo/01,524.99,yes,locked 2006.173.20:22:10.56/valo/02,534.99,yes,locked 2006.173.20:22:10.56/valo/03,564.99,yes,locked 2006.173.20:22:10.56/valo/04,624.99,yes,locked 2006.173.20:22:10.56/valo/05,734.99,yes,locked 2006.173.20:22:10.56/valo/06,814.99,yes,locked 2006.173.20:22:10.56/valo/07,864.99,yes,locked 2006.173.20:22:10.56/valo/08,884.99,yes,locked 2006.173.20:22:11.65/vb/01,04,usb,yes,29,27 2006.173.20:22:11.65/vb/02,04,usb,yes,31,31 2006.173.20:22:11.65/vb/03,04,usb,yes,28,31 2006.173.20:22:11.65/vb/04,04,usb,yes,32,31 2006.173.20:22:11.65/vb/05,04,usb,yes,25,27 2006.173.20:22:11.65/vb/06,04,usb,yes,29,26 2006.173.20:22:11.65/vb/07,04,usb,yes,29,29 2006.173.20:22:11.65/vb/08,04,usb,yes,27,30 2006.173.20:22:11.88/vblo/01,629.99,yes,locked 2006.173.20:22:11.88/vblo/02,634.99,yes,locked 2006.173.20:22:11.88/vblo/03,649.99,yes,locked 2006.173.20:22:11.88/vblo/04,679.99,yes,locked 2006.173.20:22:11.88/vblo/05,709.99,yes,locked 2006.173.20:22:11.88/vblo/06,719.99,yes,locked 2006.173.20:22:11.88/vblo/07,734.99,yes,locked 2006.173.20:22:11.88/vblo/08,744.99,yes,locked 2006.173.20:22:12.03/vabw/8 2006.173.20:22:12.18/vbbw/8 2006.173.20:22:12.27/xfe/off,on,14.0 2006.173.20:22:12.66/ifatt/23,28,28,28 2006.173.20:22:13.08/fmout-gps/S +3.88E-07 2006.173.20:22:13.12:!2006.173.20:24:09 2006.173.20:24:09.00:data_valid=off 2006.173.20:24:09.00:"et 2006.173.20:24:09.00:!+3s 2006.173.20:24:12.02:"tape 2006.173.20:24:12.02:postob 2006.173.20:24:12.13/cable/+6.5163E-03 2006.173.20:24:12.13/wx/19.85,1002.8,100 2006.173.20:24:13.08/fmout-gps/S +3.89E-07 2006.173.20:24:13.08:scan_name=173-2029,jd0606,40 2006.173.20:24:13.08:source=3c345,164258.81,394837.0,2000.0,ccw 2006.173.20:24:13.14#flagr#flagr/antenna,new-source 2006.173.20:24:14.14:checkk5 2006.173.20:24:14.55/chk_autoobs//k5ts1/ autoobs is running! 2006.173.20:24:14.96/chk_autoobs//k5ts2/ autoobs is running! 2006.173.20:24:15.36/chk_autoobs//k5ts3/ autoobs is running! 2006.173.20:24:15.77/chk_autoobs//k5ts4/ autoobs is running! 2006.173.20:24:16.15/chk_obsdata//k5ts1/T1732022??a.dat file size is correct (nominal:480MB, actual:476MB). 2006.173.20:24:16.57/chk_obsdata//k5ts2/T1732022??b.dat file size is correct (nominal:480MB, actual:476MB). 2006.173.20:24:16.96/chk_obsdata//k5ts3/T1732022??c.dat file size is correct (nominal:480MB, actual:476MB). 2006.173.20:24:17.34/chk_obsdata//k5ts4/T1732022??d.dat file size is correct (nominal:480MB, actual:476MB). 2006.173.20:24:18.05/k5log//k5ts1_log_newline 2006.173.20:24:18.76/k5log//k5ts2_log_newline 2006.173.20:24:19.48/k5log//k5ts3_log_newline 2006.173.20:24:20.17/k5log//k5ts4_log_newline 2006.173.20:24:20.20/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.20:24:20.20:setupk4=1 2006.173.20:24:20.20$setupk4/echo=on 2006.173.20:24:20.20$setupk4/pcalon 2006.173.20:24:20.20$pcalon/"no phase cal control is implemented here 2006.173.20:24:20.20$setupk4/"tpicd=stop 2006.173.20:24:20.20$setupk4/"rec=synch_on 2006.173.20:24:20.20$setupk4/"rec_mode=128 2006.173.20:24:20.20$setupk4/!* 2006.173.20:24:20.20$setupk4/recpk4 2006.173.20:24:20.20$recpk4/recpatch= 2006.173.20:24:20.20$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.20:24:20.20$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.20:24:20.20$setupk4/vck44 2006.173.20:24:20.20$vck44/valo=1,524.99 2006.173.20:24:20.20#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.20:24:20.20#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.20:24:20.20#ibcon#ireg 17 cls_cnt 0 2006.173.20:24:20.20#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.20:24:20.20#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.20:24:20.20#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.20:24:20.20#ibcon#enter wrdev, iclass 23, count 0 2006.173.20:24:20.20#ibcon#first serial, iclass 23, count 0 2006.173.20:24:20.20#ibcon#enter sib2, iclass 23, count 0 2006.173.20:24:20.20#ibcon#flushed, iclass 23, count 0 2006.173.20:24:20.20#ibcon#about to write, iclass 23, count 0 2006.173.20:24:20.20#ibcon#wrote, iclass 23, count 0 2006.173.20:24:20.20#ibcon#about to read 3, iclass 23, count 0 2006.173.20:24:20.22#ibcon#read 3, iclass 23, count 0 2006.173.20:24:20.22#ibcon#about to read 4, iclass 23, count 0 2006.173.20:24:20.22#ibcon#read 4, iclass 23, count 0 2006.173.20:24:20.22#ibcon#about to read 5, iclass 23, count 0 2006.173.20:24:20.22#ibcon#read 5, iclass 23, count 0 2006.173.20:24:20.22#ibcon#about to read 6, iclass 23, count 0 2006.173.20:24:20.22#ibcon#read 6, iclass 23, count 0 2006.173.20:24:20.22#ibcon#end of sib2, iclass 23, count 0 2006.173.20:24:20.22#ibcon#*mode == 0, iclass 23, count 0 2006.173.20:24:20.22#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.20:24:20.22#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.20:24:20.22#ibcon#*before write, iclass 23, count 0 2006.173.20:24:20.22#ibcon#enter sib2, iclass 23, count 0 2006.173.20:24:20.22#ibcon#flushed, iclass 23, count 0 2006.173.20:24:20.22#ibcon#about to write, iclass 23, count 0 2006.173.20:24:20.22#ibcon#wrote, iclass 23, count 0 2006.173.20:24:20.22#ibcon#about to read 3, iclass 23, count 0 2006.173.20:24:20.27#ibcon#read 3, iclass 23, count 0 2006.173.20:24:20.27#ibcon#about to read 4, iclass 23, count 0 2006.173.20:24:20.27#ibcon#read 4, iclass 23, count 0 2006.173.20:24:20.27#ibcon#about to read 5, iclass 23, count 0 2006.173.20:24:20.27#ibcon#read 5, iclass 23, count 0 2006.173.20:24:20.27#ibcon#about to read 6, iclass 23, count 0 2006.173.20:24:20.27#ibcon#read 6, iclass 23, count 0 2006.173.20:24:20.27#ibcon#end of sib2, iclass 23, count 0 2006.173.20:24:20.27#ibcon#*after write, iclass 23, count 0 2006.173.20:24:20.27#ibcon#*before return 0, iclass 23, count 0 2006.173.20:24:20.27#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.20:24:20.27#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.20:24:20.27#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.20:24:20.27#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.20:24:20.27$vck44/va=1,7 2006.173.20:24:20.27#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.20:24:20.27#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.20:24:20.27#ibcon#ireg 11 cls_cnt 2 2006.173.20:24:20.27#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.20:24:20.27#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.20:24:20.27#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.20:24:20.27#ibcon#enter wrdev, iclass 25, count 2 2006.173.20:24:20.27#ibcon#first serial, iclass 25, count 2 2006.173.20:24:20.27#ibcon#enter sib2, iclass 25, count 2 2006.173.20:24:20.27#ibcon#flushed, iclass 25, count 2 2006.173.20:24:20.27#ibcon#about to write, iclass 25, count 2 2006.173.20:24:20.27#ibcon#wrote, iclass 25, count 2 2006.173.20:24:20.27#ibcon#about to read 3, iclass 25, count 2 2006.173.20:24:20.29#ibcon#read 3, iclass 25, count 2 2006.173.20:24:20.29#ibcon#about to read 4, iclass 25, count 2 2006.173.20:24:20.29#ibcon#read 4, iclass 25, count 2 2006.173.20:24:20.29#ibcon#about to read 5, iclass 25, count 2 2006.173.20:24:20.29#ibcon#read 5, iclass 25, count 2 2006.173.20:24:20.29#ibcon#about to read 6, iclass 25, count 2 2006.173.20:24:20.29#ibcon#read 6, iclass 25, count 2 2006.173.20:24:20.29#ibcon#end of sib2, iclass 25, count 2 2006.173.20:24:20.29#ibcon#*mode == 0, iclass 25, count 2 2006.173.20:24:20.29#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.20:24:20.29#ibcon#[25=AT01-07\r\n] 2006.173.20:24:20.29#ibcon#*before write, iclass 25, count 2 2006.173.20:24:20.29#ibcon#enter sib2, iclass 25, count 2 2006.173.20:24:20.29#ibcon#flushed, iclass 25, count 2 2006.173.20:24:20.29#ibcon#about to write, iclass 25, count 2 2006.173.20:24:20.29#ibcon#wrote, iclass 25, count 2 2006.173.20:24:20.29#ibcon#about to read 3, iclass 25, count 2 2006.173.20:24:20.32#ibcon#read 3, iclass 25, count 2 2006.173.20:24:20.32#ibcon#about to read 4, iclass 25, count 2 2006.173.20:24:20.32#ibcon#read 4, iclass 25, count 2 2006.173.20:24:20.32#ibcon#about to read 5, iclass 25, count 2 2006.173.20:24:20.32#ibcon#read 5, iclass 25, count 2 2006.173.20:24:20.32#ibcon#about to read 6, iclass 25, count 2 2006.173.20:24:20.32#ibcon#read 6, iclass 25, count 2 2006.173.20:24:20.32#ibcon#end of sib2, iclass 25, count 2 2006.173.20:24:20.32#ibcon#*after write, iclass 25, count 2 2006.173.20:24:20.32#ibcon#*before return 0, iclass 25, count 2 2006.173.20:24:20.32#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.20:24:20.32#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.20:24:20.32#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.20:24:20.32#ibcon#ireg 7 cls_cnt 0 2006.173.20:24:20.32#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.20:24:20.44#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.20:24:20.44#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.20:24:20.44#ibcon#enter wrdev, iclass 25, count 0 2006.173.20:24:20.44#ibcon#first serial, iclass 25, count 0 2006.173.20:24:20.44#ibcon#enter sib2, iclass 25, count 0 2006.173.20:24:20.44#ibcon#flushed, iclass 25, count 0 2006.173.20:24:20.44#ibcon#about to write, iclass 25, count 0 2006.173.20:24:20.44#ibcon#wrote, iclass 25, count 0 2006.173.20:24:20.44#ibcon#about to read 3, iclass 25, count 0 2006.173.20:24:20.46#ibcon#read 3, iclass 25, count 0 2006.173.20:24:20.46#ibcon#about to read 4, iclass 25, count 0 2006.173.20:24:20.46#ibcon#read 4, iclass 25, count 0 2006.173.20:24:20.46#ibcon#about to read 5, iclass 25, count 0 2006.173.20:24:20.46#ibcon#read 5, iclass 25, count 0 2006.173.20:24:20.46#ibcon#about to read 6, iclass 25, count 0 2006.173.20:24:20.46#ibcon#read 6, iclass 25, count 0 2006.173.20:24:20.46#ibcon#end of sib2, iclass 25, count 0 2006.173.20:24:20.46#ibcon#*mode == 0, iclass 25, count 0 2006.173.20:24:20.46#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.20:24:20.46#ibcon#[25=USB\r\n] 2006.173.20:24:20.46#ibcon#*before write, iclass 25, count 0 2006.173.20:24:20.46#ibcon#enter sib2, iclass 25, count 0 2006.173.20:24:20.46#ibcon#flushed, iclass 25, count 0 2006.173.20:24:20.46#ibcon#about to write, iclass 25, count 0 2006.173.20:24:20.46#ibcon#wrote, iclass 25, count 0 2006.173.20:24:20.46#ibcon#about to read 3, iclass 25, count 0 2006.173.20:24:20.49#ibcon#read 3, iclass 25, count 0 2006.173.20:24:20.49#ibcon#about to read 4, iclass 25, count 0 2006.173.20:24:20.49#ibcon#read 4, iclass 25, count 0 2006.173.20:24:20.49#ibcon#about to read 5, iclass 25, count 0 2006.173.20:24:20.49#ibcon#read 5, iclass 25, count 0 2006.173.20:24:20.49#ibcon#about to read 6, iclass 25, count 0 2006.173.20:24:20.49#ibcon#read 6, iclass 25, count 0 2006.173.20:24:20.49#ibcon#end of sib2, iclass 25, count 0 2006.173.20:24:20.49#ibcon#*after write, iclass 25, count 0 2006.173.20:24:20.49#ibcon#*before return 0, iclass 25, count 0 2006.173.20:24:20.49#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.20:24:20.49#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.20:24:20.49#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.20:24:20.49#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.20:24:20.49$vck44/valo=2,534.99 2006.173.20:24:20.49#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.20:24:20.49#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.20:24:20.49#ibcon#ireg 17 cls_cnt 0 2006.173.20:24:20.49#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.20:24:20.49#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.20:24:20.49#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.20:24:20.49#ibcon#enter wrdev, iclass 27, count 0 2006.173.20:24:20.49#ibcon#first serial, iclass 27, count 0 2006.173.20:24:20.49#ibcon#enter sib2, iclass 27, count 0 2006.173.20:24:20.49#ibcon#flushed, iclass 27, count 0 2006.173.20:24:20.49#ibcon#about to write, iclass 27, count 0 2006.173.20:24:20.49#ibcon#wrote, iclass 27, count 0 2006.173.20:24:20.49#ibcon#about to read 3, iclass 27, count 0 2006.173.20:24:20.51#ibcon#read 3, iclass 27, count 0 2006.173.20:24:20.51#ibcon#about to read 4, iclass 27, count 0 2006.173.20:24:20.51#ibcon#read 4, iclass 27, count 0 2006.173.20:24:20.51#ibcon#about to read 5, iclass 27, count 0 2006.173.20:24:20.51#ibcon#read 5, iclass 27, count 0 2006.173.20:24:20.51#ibcon#about to read 6, iclass 27, count 0 2006.173.20:24:20.51#ibcon#read 6, iclass 27, count 0 2006.173.20:24:20.51#ibcon#end of sib2, iclass 27, count 0 2006.173.20:24:20.51#ibcon#*mode == 0, iclass 27, count 0 2006.173.20:24:20.51#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.20:24:20.51#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.20:24:20.51#ibcon#*before write, iclass 27, count 0 2006.173.20:24:20.51#ibcon#enter sib2, iclass 27, count 0 2006.173.20:24:20.51#ibcon#flushed, iclass 27, count 0 2006.173.20:24:20.51#ibcon#about to write, iclass 27, count 0 2006.173.20:24:20.51#ibcon#wrote, iclass 27, count 0 2006.173.20:24:20.51#ibcon#about to read 3, iclass 27, count 0 2006.173.20:24:20.55#ibcon#read 3, iclass 27, count 0 2006.173.20:24:20.55#ibcon#about to read 4, iclass 27, count 0 2006.173.20:24:20.55#ibcon#read 4, iclass 27, count 0 2006.173.20:24:20.55#ibcon#about to read 5, iclass 27, count 0 2006.173.20:24:20.55#ibcon#read 5, iclass 27, count 0 2006.173.20:24:20.55#ibcon#about to read 6, iclass 27, count 0 2006.173.20:24:20.55#ibcon#read 6, iclass 27, count 0 2006.173.20:24:20.55#ibcon#end of sib2, iclass 27, count 0 2006.173.20:24:20.55#ibcon#*after write, iclass 27, count 0 2006.173.20:24:20.55#ibcon#*before return 0, iclass 27, count 0 2006.173.20:24:20.55#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.20:24:20.55#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.20:24:20.55#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.20:24:20.55#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.20:24:20.55$vck44/va=2,6 2006.173.20:24:20.55#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.20:24:20.55#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.20:24:20.55#ibcon#ireg 11 cls_cnt 2 2006.173.20:24:20.55#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.20:24:20.61#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.20:24:20.61#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.20:24:20.61#ibcon#enter wrdev, iclass 29, count 2 2006.173.20:24:20.61#ibcon#first serial, iclass 29, count 2 2006.173.20:24:20.61#ibcon#enter sib2, iclass 29, count 2 2006.173.20:24:20.61#ibcon#flushed, iclass 29, count 2 2006.173.20:24:20.61#ibcon#about to write, iclass 29, count 2 2006.173.20:24:20.61#ibcon#wrote, iclass 29, count 2 2006.173.20:24:20.61#ibcon#about to read 3, iclass 29, count 2 2006.173.20:24:20.63#ibcon#read 3, iclass 29, count 2 2006.173.20:24:20.63#ibcon#about to read 4, iclass 29, count 2 2006.173.20:24:20.63#ibcon#read 4, iclass 29, count 2 2006.173.20:24:20.63#ibcon#about to read 5, iclass 29, count 2 2006.173.20:24:20.63#ibcon#read 5, iclass 29, count 2 2006.173.20:24:20.63#ibcon#about to read 6, iclass 29, count 2 2006.173.20:24:20.63#ibcon#read 6, iclass 29, count 2 2006.173.20:24:20.63#ibcon#end of sib2, iclass 29, count 2 2006.173.20:24:20.63#ibcon#*mode == 0, iclass 29, count 2 2006.173.20:24:20.63#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.20:24:20.63#ibcon#[25=AT02-06\r\n] 2006.173.20:24:20.63#ibcon#*before write, iclass 29, count 2 2006.173.20:24:20.63#ibcon#enter sib2, iclass 29, count 2 2006.173.20:24:20.63#ibcon#flushed, iclass 29, count 2 2006.173.20:24:20.63#ibcon#about to write, iclass 29, count 2 2006.173.20:24:20.63#ibcon#wrote, iclass 29, count 2 2006.173.20:24:20.63#ibcon#about to read 3, iclass 29, count 2 2006.173.20:24:20.66#ibcon#read 3, iclass 29, count 2 2006.173.20:24:20.66#ibcon#about to read 4, iclass 29, count 2 2006.173.20:24:20.66#ibcon#read 4, iclass 29, count 2 2006.173.20:24:20.66#ibcon#about to read 5, iclass 29, count 2 2006.173.20:24:20.66#ibcon#read 5, iclass 29, count 2 2006.173.20:24:20.66#ibcon#about to read 6, iclass 29, count 2 2006.173.20:24:20.66#ibcon#read 6, iclass 29, count 2 2006.173.20:24:20.66#ibcon#end of sib2, iclass 29, count 2 2006.173.20:24:20.66#ibcon#*after write, iclass 29, count 2 2006.173.20:24:20.66#ibcon#*before return 0, iclass 29, count 2 2006.173.20:24:20.66#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.20:24:20.66#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.20:24:20.66#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.20:24:20.66#ibcon#ireg 7 cls_cnt 0 2006.173.20:24:20.66#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.20:24:20.78#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.20:24:20.78#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.20:24:20.78#ibcon#enter wrdev, iclass 29, count 0 2006.173.20:24:20.78#ibcon#first serial, iclass 29, count 0 2006.173.20:24:20.78#ibcon#enter sib2, iclass 29, count 0 2006.173.20:24:20.78#ibcon#flushed, iclass 29, count 0 2006.173.20:24:20.78#ibcon#about to write, iclass 29, count 0 2006.173.20:24:20.78#ibcon#wrote, iclass 29, count 0 2006.173.20:24:20.78#ibcon#about to read 3, iclass 29, count 0 2006.173.20:24:20.80#ibcon#read 3, iclass 29, count 0 2006.173.20:24:20.80#ibcon#about to read 4, iclass 29, count 0 2006.173.20:24:20.80#ibcon#read 4, iclass 29, count 0 2006.173.20:24:20.80#ibcon#about to read 5, iclass 29, count 0 2006.173.20:24:20.80#ibcon#read 5, iclass 29, count 0 2006.173.20:24:20.80#ibcon#about to read 6, iclass 29, count 0 2006.173.20:24:20.80#ibcon#read 6, iclass 29, count 0 2006.173.20:24:20.80#ibcon#end of sib2, iclass 29, count 0 2006.173.20:24:20.80#ibcon#*mode == 0, iclass 29, count 0 2006.173.20:24:20.80#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.20:24:20.80#ibcon#[25=USB\r\n] 2006.173.20:24:20.80#ibcon#*before write, iclass 29, count 0 2006.173.20:24:20.80#ibcon#enter sib2, iclass 29, count 0 2006.173.20:24:20.80#ibcon#flushed, iclass 29, count 0 2006.173.20:24:20.80#ibcon#about to write, iclass 29, count 0 2006.173.20:24:20.80#ibcon#wrote, iclass 29, count 0 2006.173.20:24:20.80#ibcon#about to read 3, iclass 29, count 0 2006.173.20:24:20.83#ibcon#read 3, iclass 29, count 0 2006.173.20:24:20.83#ibcon#about to read 4, iclass 29, count 0 2006.173.20:24:20.83#ibcon#read 4, iclass 29, count 0 2006.173.20:24:20.83#ibcon#about to read 5, iclass 29, count 0 2006.173.20:24:20.83#ibcon#read 5, iclass 29, count 0 2006.173.20:24:20.83#ibcon#about to read 6, iclass 29, count 0 2006.173.20:24:20.83#ibcon#read 6, iclass 29, count 0 2006.173.20:24:20.83#ibcon#end of sib2, iclass 29, count 0 2006.173.20:24:20.83#ibcon#*after write, iclass 29, count 0 2006.173.20:24:20.83#ibcon#*before return 0, iclass 29, count 0 2006.173.20:24:20.83#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.20:24:20.83#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.20:24:20.83#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.20:24:20.83#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.20:24:20.83$vck44/valo=3,564.99 2006.173.20:24:20.83#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.20:24:20.83#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.20:24:20.83#ibcon#ireg 17 cls_cnt 0 2006.173.20:24:20.83#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.20:24:20.83#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.20:24:20.83#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.20:24:20.83#ibcon#enter wrdev, iclass 31, count 0 2006.173.20:24:20.83#ibcon#first serial, iclass 31, count 0 2006.173.20:24:20.83#ibcon#enter sib2, iclass 31, count 0 2006.173.20:24:20.83#ibcon#flushed, iclass 31, count 0 2006.173.20:24:20.83#ibcon#about to write, iclass 31, count 0 2006.173.20:24:20.83#ibcon#wrote, iclass 31, count 0 2006.173.20:24:20.83#ibcon#about to read 3, iclass 31, count 0 2006.173.20:24:20.85#ibcon#read 3, iclass 31, count 0 2006.173.20:24:20.85#ibcon#about to read 4, iclass 31, count 0 2006.173.20:24:20.85#ibcon#read 4, iclass 31, count 0 2006.173.20:24:20.85#ibcon#about to read 5, iclass 31, count 0 2006.173.20:24:20.85#ibcon#read 5, iclass 31, count 0 2006.173.20:24:20.85#ibcon#about to read 6, iclass 31, count 0 2006.173.20:24:20.85#ibcon#read 6, iclass 31, count 0 2006.173.20:24:20.85#ibcon#end of sib2, iclass 31, count 0 2006.173.20:24:20.85#ibcon#*mode == 0, iclass 31, count 0 2006.173.20:24:20.85#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.20:24:20.85#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.20:24:20.85#ibcon#*before write, iclass 31, count 0 2006.173.20:24:20.85#ibcon#enter sib2, iclass 31, count 0 2006.173.20:24:20.85#ibcon#flushed, iclass 31, count 0 2006.173.20:24:20.85#ibcon#about to write, iclass 31, count 0 2006.173.20:24:20.85#ibcon#wrote, iclass 31, count 0 2006.173.20:24:20.85#ibcon#about to read 3, iclass 31, count 0 2006.173.20:24:20.89#ibcon#read 3, iclass 31, count 0 2006.173.20:24:20.89#ibcon#about to read 4, iclass 31, count 0 2006.173.20:24:20.89#ibcon#read 4, iclass 31, count 0 2006.173.20:24:20.89#ibcon#about to read 5, iclass 31, count 0 2006.173.20:24:20.89#ibcon#read 5, iclass 31, count 0 2006.173.20:24:20.89#ibcon#about to read 6, iclass 31, count 0 2006.173.20:24:20.89#ibcon#read 6, iclass 31, count 0 2006.173.20:24:20.89#ibcon#end of sib2, iclass 31, count 0 2006.173.20:24:20.89#ibcon#*after write, iclass 31, count 0 2006.173.20:24:20.89#ibcon#*before return 0, iclass 31, count 0 2006.173.20:24:20.89#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.20:24:20.89#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.20:24:20.89#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.20:24:20.89#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.20:24:20.89$vck44/va=3,5 2006.173.20:24:20.89#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.173.20:24:20.89#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.173.20:24:20.89#ibcon#ireg 11 cls_cnt 2 2006.173.20:24:20.89#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.20:24:20.95#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.20:24:20.95#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.20:24:20.95#ibcon#enter wrdev, iclass 33, count 2 2006.173.20:24:20.95#ibcon#first serial, iclass 33, count 2 2006.173.20:24:20.95#ibcon#enter sib2, iclass 33, count 2 2006.173.20:24:20.95#ibcon#flushed, iclass 33, count 2 2006.173.20:24:20.95#ibcon#about to write, iclass 33, count 2 2006.173.20:24:20.95#ibcon#wrote, iclass 33, count 2 2006.173.20:24:20.95#ibcon#about to read 3, iclass 33, count 2 2006.173.20:24:20.97#ibcon#read 3, iclass 33, count 2 2006.173.20:24:20.97#ibcon#about to read 4, iclass 33, count 2 2006.173.20:24:20.97#ibcon#read 4, iclass 33, count 2 2006.173.20:24:20.97#ibcon#about to read 5, iclass 33, count 2 2006.173.20:24:20.97#ibcon#read 5, iclass 33, count 2 2006.173.20:24:20.97#ibcon#about to read 6, iclass 33, count 2 2006.173.20:24:20.97#ibcon#read 6, iclass 33, count 2 2006.173.20:24:20.97#ibcon#end of sib2, iclass 33, count 2 2006.173.20:24:20.97#ibcon#*mode == 0, iclass 33, count 2 2006.173.20:24:20.97#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.173.20:24:20.97#ibcon#[25=AT03-05\r\n] 2006.173.20:24:20.97#ibcon#*before write, iclass 33, count 2 2006.173.20:24:20.97#ibcon#enter sib2, iclass 33, count 2 2006.173.20:24:20.97#ibcon#flushed, iclass 33, count 2 2006.173.20:24:20.97#ibcon#about to write, iclass 33, count 2 2006.173.20:24:20.97#ibcon#wrote, iclass 33, count 2 2006.173.20:24:20.97#ibcon#about to read 3, iclass 33, count 2 2006.173.20:24:21.00#ibcon#read 3, iclass 33, count 2 2006.173.20:24:21.00#ibcon#about to read 4, iclass 33, count 2 2006.173.20:24:21.00#ibcon#read 4, iclass 33, count 2 2006.173.20:24:21.00#ibcon#about to read 5, iclass 33, count 2 2006.173.20:24:21.00#ibcon#read 5, iclass 33, count 2 2006.173.20:24:21.00#ibcon#about to read 6, iclass 33, count 2 2006.173.20:24:21.00#ibcon#read 6, iclass 33, count 2 2006.173.20:24:21.00#ibcon#end of sib2, iclass 33, count 2 2006.173.20:24:21.00#ibcon#*after write, iclass 33, count 2 2006.173.20:24:21.00#ibcon#*before return 0, iclass 33, count 2 2006.173.20:24:21.00#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.20:24:21.00#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.173.20:24:21.00#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.173.20:24:21.00#ibcon#ireg 7 cls_cnt 0 2006.173.20:24:21.00#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.20:24:21.12#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.20:24:21.12#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.20:24:21.12#ibcon#enter wrdev, iclass 33, count 0 2006.173.20:24:21.12#ibcon#first serial, iclass 33, count 0 2006.173.20:24:21.12#ibcon#enter sib2, iclass 33, count 0 2006.173.20:24:21.12#ibcon#flushed, iclass 33, count 0 2006.173.20:24:21.12#ibcon#about to write, iclass 33, count 0 2006.173.20:24:21.12#ibcon#wrote, iclass 33, count 0 2006.173.20:24:21.12#ibcon#about to read 3, iclass 33, count 0 2006.173.20:24:21.14#ibcon#read 3, iclass 33, count 0 2006.173.20:24:21.14#ibcon#about to read 4, iclass 33, count 0 2006.173.20:24:21.14#ibcon#read 4, iclass 33, count 0 2006.173.20:24:21.14#ibcon#about to read 5, iclass 33, count 0 2006.173.20:24:21.14#ibcon#read 5, iclass 33, count 0 2006.173.20:24:21.14#ibcon#about to read 6, iclass 33, count 0 2006.173.20:24:21.14#ibcon#read 6, iclass 33, count 0 2006.173.20:24:21.14#ibcon#end of sib2, iclass 33, count 0 2006.173.20:24:21.14#ibcon#*mode == 0, iclass 33, count 0 2006.173.20:24:21.14#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.20:24:21.14#ibcon#[25=USB\r\n] 2006.173.20:24:21.14#ibcon#*before write, iclass 33, count 0 2006.173.20:24:21.14#ibcon#enter sib2, iclass 33, count 0 2006.173.20:24:21.14#ibcon#flushed, iclass 33, count 0 2006.173.20:24:21.14#ibcon#about to write, iclass 33, count 0 2006.173.20:24:21.14#ibcon#wrote, iclass 33, count 0 2006.173.20:24:21.14#ibcon#about to read 3, iclass 33, count 0 2006.173.20:24:21.17#ibcon#read 3, iclass 33, count 0 2006.173.20:24:21.17#ibcon#about to read 4, iclass 33, count 0 2006.173.20:24:21.17#ibcon#read 4, iclass 33, count 0 2006.173.20:24:21.17#ibcon#about to read 5, iclass 33, count 0 2006.173.20:24:21.17#ibcon#read 5, iclass 33, count 0 2006.173.20:24:21.17#ibcon#about to read 6, iclass 33, count 0 2006.173.20:24:21.17#ibcon#read 6, iclass 33, count 0 2006.173.20:24:21.17#ibcon#end of sib2, iclass 33, count 0 2006.173.20:24:21.17#ibcon#*after write, iclass 33, count 0 2006.173.20:24:21.17#ibcon#*before return 0, iclass 33, count 0 2006.173.20:24:21.17#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.20:24:21.17#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.173.20:24:21.17#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.20:24:21.17#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.20:24:21.17$vck44/valo=4,624.99 2006.173.20:24:21.17#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.20:24:21.17#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.20:24:21.17#ibcon#ireg 17 cls_cnt 0 2006.173.20:24:21.17#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.20:24:21.17#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.20:24:21.17#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.20:24:21.17#ibcon#enter wrdev, iclass 35, count 0 2006.173.20:24:21.17#ibcon#first serial, iclass 35, count 0 2006.173.20:24:21.17#ibcon#enter sib2, iclass 35, count 0 2006.173.20:24:21.17#ibcon#flushed, iclass 35, count 0 2006.173.20:24:21.17#ibcon#about to write, iclass 35, count 0 2006.173.20:24:21.17#ibcon#wrote, iclass 35, count 0 2006.173.20:24:21.17#ibcon#about to read 3, iclass 35, count 0 2006.173.20:24:21.19#ibcon#read 3, iclass 35, count 0 2006.173.20:24:21.19#ibcon#about to read 4, iclass 35, count 0 2006.173.20:24:21.19#ibcon#read 4, iclass 35, count 0 2006.173.20:24:21.19#ibcon#about to read 5, iclass 35, count 0 2006.173.20:24:21.19#ibcon#read 5, iclass 35, count 0 2006.173.20:24:21.19#ibcon#about to read 6, iclass 35, count 0 2006.173.20:24:21.19#ibcon#read 6, iclass 35, count 0 2006.173.20:24:21.19#ibcon#end of sib2, iclass 35, count 0 2006.173.20:24:21.19#ibcon#*mode == 0, iclass 35, count 0 2006.173.20:24:21.19#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.20:24:21.19#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.20:24:21.19#ibcon#*before write, iclass 35, count 0 2006.173.20:24:21.19#ibcon#enter sib2, iclass 35, count 0 2006.173.20:24:21.19#ibcon#flushed, iclass 35, count 0 2006.173.20:24:21.19#ibcon#about to write, iclass 35, count 0 2006.173.20:24:21.19#ibcon#wrote, iclass 35, count 0 2006.173.20:24:21.19#ibcon#about to read 3, iclass 35, count 0 2006.173.20:24:21.23#ibcon#read 3, iclass 35, count 0 2006.173.20:24:21.23#ibcon#about to read 4, iclass 35, count 0 2006.173.20:24:21.23#ibcon#read 4, iclass 35, count 0 2006.173.20:24:21.23#ibcon#about to read 5, iclass 35, count 0 2006.173.20:24:21.23#ibcon#read 5, iclass 35, count 0 2006.173.20:24:21.23#ibcon#about to read 6, iclass 35, count 0 2006.173.20:24:21.23#ibcon#read 6, iclass 35, count 0 2006.173.20:24:21.23#ibcon#end of sib2, iclass 35, count 0 2006.173.20:24:21.23#ibcon#*after write, iclass 35, count 0 2006.173.20:24:21.23#ibcon#*before return 0, iclass 35, count 0 2006.173.20:24:21.23#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.20:24:21.23#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.20:24:21.23#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.20:24:21.23#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.20:24:21.23$vck44/va=4,6 2006.173.20:24:21.23#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.173.20:24:21.23#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.173.20:24:21.23#ibcon#ireg 11 cls_cnt 2 2006.173.20:24:21.23#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.20:24:21.29#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.20:24:21.29#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.20:24:21.29#ibcon#enter wrdev, iclass 37, count 2 2006.173.20:24:21.29#ibcon#first serial, iclass 37, count 2 2006.173.20:24:21.29#ibcon#enter sib2, iclass 37, count 2 2006.173.20:24:21.29#ibcon#flushed, iclass 37, count 2 2006.173.20:24:21.29#ibcon#about to write, iclass 37, count 2 2006.173.20:24:21.29#ibcon#wrote, iclass 37, count 2 2006.173.20:24:21.29#ibcon#about to read 3, iclass 37, count 2 2006.173.20:24:21.31#ibcon#read 3, iclass 37, count 2 2006.173.20:24:21.31#ibcon#about to read 4, iclass 37, count 2 2006.173.20:24:21.31#ibcon#read 4, iclass 37, count 2 2006.173.20:24:21.31#ibcon#about to read 5, iclass 37, count 2 2006.173.20:24:21.31#ibcon#read 5, iclass 37, count 2 2006.173.20:24:21.31#ibcon#about to read 6, iclass 37, count 2 2006.173.20:24:21.31#ibcon#read 6, iclass 37, count 2 2006.173.20:24:21.31#ibcon#end of sib2, iclass 37, count 2 2006.173.20:24:21.31#ibcon#*mode == 0, iclass 37, count 2 2006.173.20:24:21.31#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.173.20:24:21.31#ibcon#[25=AT04-06\r\n] 2006.173.20:24:21.31#ibcon#*before write, iclass 37, count 2 2006.173.20:24:21.31#ibcon#enter sib2, iclass 37, count 2 2006.173.20:24:21.31#ibcon#flushed, iclass 37, count 2 2006.173.20:24:21.31#ibcon#about to write, iclass 37, count 2 2006.173.20:24:21.31#ibcon#wrote, iclass 37, count 2 2006.173.20:24:21.31#ibcon#about to read 3, iclass 37, count 2 2006.173.20:24:21.34#ibcon#read 3, iclass 37, count 2 2006.173.20:24:21.34#ibcon#about to read 4, iclass 37, count 2 2006.173.20:24:21.34#ibcon#read 4, iclass 37, count 2 2006.173.20:24:21.34#ibcon#about to read 5, iclass 37, count 2 2006.173.20:24:21.34#ibcon#read 5, iclass 37, count 2 2006.173.20:24:21.34#ibcon#about to read 6, iclass 37, count 2 2006.173.20:24:21.34#ibcon#read 6, iclass 37, count 2 2006.173.20:24:21.34#ibcon#end of sib2, iclass 37, count 2 2006.173.20:24:21.34#ibcon#*after write, iclass 37, count 2 2006.173.20:24:21.34#ibcon#*before return 0, iclass 37, count 2 2006.173.20:24:21.34#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.20:24:21.34#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.173.20:24:21.34#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.173.20:24:21.34#ibcon#ireg 7 cls_cnt 0 2006.173.20:24:21.34#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.20:24:21.46#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.20:24:21.46#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.20:24:21.46#ibcon#enter wrdev, iclass 37, count 0 2006.173.20:24:21.46#ibcon#first serial, iclass 37, count 0 2006.173.20:24:21.46#ibcon#enter sib2, iclass 37, count 0 2006.173.20:24:21.46#ibcon#flushed, iclass 37, count 0 2006.173.20:24:21.46#ibcon#about to write, iclass 37, count 0 2006.173.20:24:21.46#ibcon#wrote, iclass 37, count 0 2006.173.20:24:21.46#ibcon#about to read 3, iclass 37, count 0 2006.173.20:24:21.48#ibcon#read 3, iclass 37, count 0 2006.173.20:24:21.48#ibcon#about to read 4, iclass 37, count 0 2006.173.20:24:21.48#ibcon#read 4, iclass 37, count 0 2006.173.20:24:21.48#ibcon#about to read 5, iclass 37, count 0 2006.173.20:24:21.48#ibcon#read 5, iclass 37, count 0 2006.173.20:24:21.48#ibcon#about to read 6, iclass 37, count 0 2006.173.20:24:21.48#ibcon#read 6, iclass 37, count 0 2006.173.20:24:21.48#ibcon#end of sib2, iclass 37, count 0 2006.173.20:24:21.48#ibcon#*mode == 0, iclass 37, count 0 2006.173.20:24:21.48#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.20:24:21.48#ibcon#[25=USB\r\n] 2006.173.20:24:21.48#ibcon#*before write, iclass 37, count 0 2006.173.20:24:21.48#ibcon#enter sib2, iclass 37, count 0 2006.173.20:24:21.48#ibcon#flushed, iclass 37, count 0 2006.173.20:24:21.48#ibcon#about to write, iclass 37, count 0 2006.173.20:24:21.48#ibcon#wrote, iclass 37, count 0 2006.173.20:24:21.48#ibcon#about to read 3, iclass 37, count 0 2006.173.20:24:21.51#ibcon#read 3, iclass 37, count 0 2006.173.20:24:21.51#ibcon#about to read 4, iclass 37, count 0 2006.173.20:24:21.51#ibcon#read 4, iclass 37, count 0 2006.173.20:24:21.51#ibcon#about to read 5, iclass 37, count 0 2006.173.20:24:21.51#ibcon#read 5, iclass 37, count 0 2006.173.20:24:21.51#ibcon#about to read 6, iclass 37, count 0 2006.173.20:24:21.51#ibcon#read 6, iclass 37, count 0 2006.173.20:24:21.51#ibcon#end of sib2, iclass 37, count 0 2006.173.20:24:21.51#ibcon#*after write, iclass 37, count 0 2006.173.20:24:21.51#ibcon#*before return 0, iclass 37, count 0 2006.173.20:24:21.51#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.20:24:21.51#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.173.20:24:21.51#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.20:24:21.51#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.20:24:21.51$vck44/valo=5,734.99 2006.173.20:24:21.51#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.20:24:21.51#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.20:24:21.51#ibcon#ireg 17 cls_cnt 0 2006.173.20:24:21.51#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.20:24:21.51#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.20:24:21.51#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.20:24:21.51#ibcon#enter wrdev, iclass 39, count 0 2006.173.20:24:21.51#ibcon#first serial, iclass 39, count 0 2006.173.20:24:21.51#ibcon#enter sib2, iclass 39, count 0 2006.173.20:24:21.51#ibcon#flushed, iclass 39, count 0 2006.173.20:24:21.51#ibcon#about to write, iclass 39, count 0 2006.173.20:24:21.51#ibcon#wrote, iclass 39, count 0 2006.173.20:24:21.51#ibcon#about to read 3, iclass 39, count 0 2006.173.20:24:21.53#ibcon#read 3, iclass 39, count 0 2006.173.20:24:21.53#ibcon#about to read 4, iclass 39, count 0 2006.173.20:24:21.53#ibcon#read 4, iclass 39, count 0 2006.173.20:24:21.53#ibcon#about to read 5, iclass 39, count 0 2006.173.20:24:21.53#ibcon#read 5, iclass 39, count 0 2006.173.20:24:21.53#ibcon#about to read 6, iclass 39, count 0 2006.173.20:24:21.53#ibcon#read 6, iclass 39, count 0 2006.173.20:24:21.53#ibcon#end of sib2, iclass 39, count 0 2006.173.20:24:21.53#ibcon#*mode == 0, iclass 39, count 0 2006.173.20:24:21.53#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.20:24:21.53#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.20:24:21.53#ibcon#*before write, iclass 39, count 0 2006.173.20:24:21.53#ibcon#enter sib2, iclass 39, count 0 2006.173.20:24:21.53#ibcon#flushed, iclass 39, count 0 2006.173.20:24:21.53#ibcon#about to write, iclass 39, count 0 2006.173.20:24:21.53#ibcon#wrote, iclass 39, count 0 2006.173.20:24:21.53#ibcon#about to read 3, iclass 39, count 0 2006.173.20:24:21.57#ibcon#read 3, iclass 39, count 0 2006.173.20:24:21.57#ibcon#about to read 4, iclass 39, count 0 2006.173.20:24:21.57#ibcon#read 4, iclass 39, count 0 2006.173.20:24:21.57#ibcon#about to read 5, iclass 39, count 0 2006.173.20:24:21.57#ibcon#read 5, iclass 39, count 0 2006.173.20:24:21.57#ibcon#about to read 6, iclass 39, count 0 2006.173.20:24:21.57#ibcon#read 6, iclass 39, count 0 2006.173.20:24:21.57#ibcon#end of sib2, iclass 39, count 0 2006.173.20:24:21.57#ibcon#*after write, iclass 39, count 0 2006.173.20:24:21.57#ibcon#*before return 0, iclass 39, count 0 2006.173.20:24:21.57#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.20:24:21.57#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.20:24:21.57#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.20:24:21.57#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.20:24:21.57$vck44/va=5,4 2006.173.20:24:21.57#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.20:24:21.57#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.20:24:21.57#ibcon#ireg 11 cls_cnt 2 2006.173.20:24:21.57#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.20:24:21.63#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.20:24:21.63#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.20:24:21.63#ibcon#enter wrdev, iclass 3, count 2 2006.173.20:24:21.63#ibcon#first serial, iclass 3, count 2 2006.173.20:24:21.63#ibcon#enter sib2, iclass 3, count 2 2006.173.20:24:21.63#ibcon#flushed, iclass 3, count 2 2006.173.20:24:21.63#ibcon#about to write, iclass 3, count 2 2006.173.20:24:21.63#ibcon#wrote, iclass 3, count 2 2006.173.20:24:21.63#ibcon#about to read 3, iclass 3, count 2 2006.173.20:24:21.65#ibcon#read 3, iclass 3, count 2 2006.173.20:24:21.65#ibcon#about to read 4, iclass 3, count 2 2006.173.20:24:21.65#ibcon#read 4, iclass 3, count 2 2006.173.20:24:21.65#ibcon#about to read 5, iclass 3, count 2 2006.173.20:24:21.65#ibcon#read 5, iclass 3, count 2 2006.173.20:24:21.65#ibcon#about to read 6, iclass 3, count 2 2006.173.20:24:21.65#ibcon#read 6, iclass 3, count 2 2006.173.20:24:21.65#ibcon#end of sib2, iclass 3, count 2 2006.173.20:24:21.65#ibcon#*mode == 0, iclass 3, count 2 2006.173.20:24:21.65#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.20:24:21.65#ibcon#[25=AT05-04\r\n] 2006.173.20:24:21.65#ibcon#*before write, iclass 3, count 2 2006.173.20:24:21.65#ibcon#enter sib2, iclass 3, count 2 2006.173.20:24:21.65#ibcon#flushed, iclass 3, count 2 2006.173.20:24:21.65#ibcon#about to write, iclass 3, count 2 2006.173.20:24:21.65#ibcon#wrote, iclass 3, count 2 2006.173.20:24:21.65#ibcon#about to read 3, iclass 3, count 2 2006.173.20:24:21.68#ibcon#read 3, iclass 3, count 2 2006.173.20:24:21.68#ibcon#about to read 4, iclass 3, count 2 2006.173.20:24:21.68#ibcon#read 4, iclass 3, count 2 2006.173.20:24:21.68#ibcon#about to read 5, iclass 3, count 2 2006.173.20:24:21.68#ibcon#read 5, iclass 3, count 2 2006.173.20:24:21.68#ibcon#about to read 6, iclass 3, count 2 2006.173.20:24:21.68#ibcon#read 6, iclass 3, count 2 2006.173.20:24:21.68#ibcon#end of sib2, iclass 3, count 2 2006.173.20:24:21.68#ibcon#*after write, iclass 3, count 2 2006.173.20:24:21.68#ibcon#*before return 0, iclass 3, count 2 2006.173.20:24:21.68#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.20:24:21.68#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.20:24:21.68#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.20:24:21.68#ibcon#ireg 7 cls_cnt 0 2006.173.20:24:21.68#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.20:24:21.80#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.20:24:21.80#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.20:24:21.80#ibcon#enter wrdev, iclass 3, count 0 2006.173.20:24:21.80#ibcon#first serial, iclass 3, count 0 2006.173.20:24:21.80#ibcon#enter sib2, iclass 3, count 0 2006.173.20:24:21.80#ibcon#flushed, iclass 3, count 0 2006.173.20:24:21.80#ibcon#about to write, iclass 3, count 0 2006.173.20:24:21.80#ibcon#wrote, iclass 3, count 0 2006.173.20:24:21.80#ibcon#about to read 3, iclass 3, count 0 2006.173.20:24:21.82#ibcon#read 3, iclass 3, count 0 2006.173.20:24:21.82#ibcon#about to read 4, iclass 3, count 0 2006.173.20:24:21.82#ibcon#read 4, iclass 3, count 0 2006.173.20:24:21.82#ibcon#about to read 5, iclass 3, count 0 2006.173.20:24:21.82#ibcon#read 5, iclass 3, count 0 2006.173.20:24:21.82#ibcon#about to read 6, iclass 3, count 0 2006.173.20:24:21.82#ibcon#read 6, iclass 3, count 0 2006.173.20:24:21.82#ibcon#end of sib2, iclass 3, count 0 2006.173.20:24:21.82#ibcon#*mode == 0, iclass 3, count 0 2006.173.20:24:21.82#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.20:24:21.82#ibcon#[25=USB\r\n] 2006.173.20:24:21.82#ibcon#*before write, iclass 3, count 0 2006.173.20:24:21.82#ibcon#enter sib2, iclass 3, count 0 2006.173.20:24:21.82#ibcon#flushed, iclass 3, count 0 2006.173.20:24:21.82#ibcon#about to write, iclass 3, count 0 2006.173.20:24:21.82#ibcon#wrote, iclass 3, count 0 2006.173.20:24:21.82#ibcon#about to read 3, iclass 3, count 0 2006.173.20:24:21.85#ibcon#read 3, iclass 3, count 0 2006.173.20:24:21.85#ibcon#about to read 4, iclass 3, count 0 2006.173.20:24:21.85#ibcon#read 4, iclass 3, count 0 2006.173.20:24:21.85#ibcon#about to read 5, iclass 3, count 0 2006.173.20:24:21.85#ibcon#read 5, iclass 3, count 0 2006.173.20:24:21.85#ibcon#about to read 6, iclass 3, count 0 2006.173.20:24:21.85#ibcon#read 6, iclass 3, count 0 2006.173.20:24:21.85#ibcon#end of sib2, iclass 3, count 0 2006.173.20:24:21.85#ibcon#*after write, iclass 3, count 0 2006.173.20:24:21.85#ibcon#*before return 0, iclass 3, count 0 2006.173.20:24:21.85#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.20:24:21.85#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.20:24:21.85#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.20:24:21.85#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.20:24:21.85$vck44/valo=6,814.99 2006.173.20:24:21.85#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.20:24:21.85#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.20:24:21.85#ibcon#ireg 17 cls_cnt 0 2006.173.20:24:21.85#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.20:24:21.85#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.20:24:21.85#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.20:24:21.85#ibcon#enter wrdev, iclass 6, count 0 2006.173.20:24:21.85#ibcon#first serial, iclass 6, count 0 2006.173.20:24:21.85#ibcon#enter sib2, iclass 6, count 0 2006.173.20:24:21.85#ibcon#flushed, iclass 6, count 0 2006.173.20:24:21.85#ibcon#about to write, iclass 6, count 0 2006.173.20:24:21.85#ibcon#wrote, iclass 6, count 0 2006.173.20:24:21.85#ibcon#about to read 3, iclass 6, count 0 2006.173.20:24:21.86#abcon#<5=/07 0.4 1.0 19.861001002.8\r\n> 2006.173.20:24:21.87#ibcon#read 3, iclass 6, count 0 2006.173.20:24:21.87#ibcon#about to read 4, iclass 6, count 0 2006.173.20:24:21.87#ibcon#read 4, iclass 6, count 0 2006.173.20:24:21.87#ibcon#about to read 5, iclass 6, count 0 2006.173.20:24:21.87#ibcon#read 5, iclass 6, count 0 2006.173.20:24:21.87#ibcon#about to read 6, iclass 6, count 0 2006.173.20:24:21.87#ibcon#read 6, iclass 6, count 0 2006.173.20:24:21.87#ibcon#end of sib2, iclass 6, count 0 2006.173.20:24:21.87#ibcon#*mode == 0, iclass 6, count 0 2006.173.20:24:21.87#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.20:24:21.87#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.20:24:21.87#ibcon#*before write, iclass 6, count 0 2006.173.20:24:21.87#ibcon#enter sib2, iclass 6, count 0 2006.173.20:24:21.87#ibcon#flushed, iclass 6, count 0 2006.173.20:24:21.87#ibcon#about to write, iclass 6, count 0 2006.173.20:24:21.87#ibcon#wrote, iclass 6, count 0 2006.173.20:24:21.87#ibcon#about to read 3, iclass 6, count 0 2006.173.20:24:21.88#abcon#{5=INTERFACE CLEAR} 2006.173.20:24:21.91#ibcon#read 3, iclass 6, count 0 2006.173.20:24:21.91#ibcon#about to read 4, iclass 6, count 0 2006.173.20:24:21.91#ibcon#read 4, iclass 6, count 0 2006.173.20:24:21.91#ibcon#about to read 5, iclass 6, count 0 2006.173.20:24:21.91#ibcon#read 5, iclass 6, count 0 2006.173.20:24:21.91#ibcon#about to read 6, iclass 6, count 0 2006.173.20:24:21.91#ibcon#read 6, iclass 6, count 0 2006.173.20:24:21.91#ibcon#end of sib2, iclass 6, count 0 2006.173.20:24:21.91#ibcon#*after write, iclass 6, count 0 2006.173.20:24:21.91#ibcon#*before return 0, iclass 6, count 0 2006.173.20:24:21.91#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.20:24:21.91#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.20:24:21.91#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.20:24:21.91#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.20:24:21.91$vck44/va=6,3 2006.173.20:24:21.91#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.20:24:21.91#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.20:24:21.91#ibcon#ireg 11 cls_cnt 2 2006.173.20:24:21.91#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.20:24:21.94#abcon#[5=S1D000X0/0*\r\n] 2006.173.20:24:21.97#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.20:24:21.97#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.20:24:21.97#ibcon#enter wrdev, iclass 12, count 2 2006.173.20:24:21.97#ibcon#first serial, iclass 12, count 2 2006.173.20:24:21.97#ibcon#enter sib2, iclass 12, count 2 2006.173.20:24:21.97#ibcon#flushed, iclass 12, count 2 2006.173.20:24:21.97#ibcon#about to write, iclass 12, count 2 2006.173.20:24:21.97#ibcon#wrote, iclass 12, count 2 2006.173.20:24:21.97#ibcon#about to read 3, iclass 12, count 2 2006.173.20:24:21.99#ibcon#read 3, iclass 12, count 2 2006.173.20:24:21.99#ibcon#about to read 4, iclass 12, count 2 2006.173.20:24:21.99#ibcon#read 4, iclass 12, count 2 2006.173.20:24:21.99#ibcon#about to read 5, iclass 12, count 2 2006.173.20:24:21.99#ibcon#read 5, iclass 12, count 2 2006.173.20:24:21.99#ibcon#about to read 6, iclass 12, count 2 2006.173.20:24:21.99#ibcon#read 6, iclass 12, count 2 2006.173.20:24:21.99#ibcon#end of sib2, iclass 12, count 2 2006.173.20:24:21.99#ibcon#*mode == 0, iclass 12, count 2 2006.173.20:24:21.99#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.20:24:21.99#ibcon#[25=AT06-03\r\n] 2006.173.20:24:21.99#ibcon#*before write, iclass 12, count 2 2006.173.20:24:21.99#ibcon#enter sib2, iclass 12, count 2 2006.173.20:24:21.99#ibcon#flushed, iclass 12, count 2 2006.173.20:24:21.99#ibcon#about to write, iclass 12, count 2 2006.173.20:24:21.99#ibcon#wrote, iclass 12, count 2 2006.173.20:24:21.99#ibcon#about to read 3, iclass 12, count 2 2006.173.20:24:22.02#ibcon#read 3, iclass 12, count 2 2006.173.20:24:22.02#ibcon#about to read 4, iclass 12, count 2 2006.173.20:24:22.02#ibcon#read 4, iclass 12, count 2 2006.173.20:24:22.02#ibcon#about to read 5, iclass 12, count 2 2006.173.20:24:22.02#ibcon#read 5, iclass 12, count 2 2006.173.20:24:22.02#ibcon#about to read 6, iclass 12, count 2 2006.173.20:24:22.02#ibcon#read 6, iclass 12, count 2 2006.173.20:24:22.02#ibcon#end of sib2, iclass 12, count 2 2006.173.20:24:22.02#ibcon#*after write, iclass 12, count 2 2006.173.20:24:22.02#ibcon#*before return 0, iclass 12, count 2 2006.173.20:24:22.02#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.20:24:22.02#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.20:24:22.02#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.20:24:22.02#ibcon#ireg 7 cls_cnt 0 2006.173.20:24:22.02#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.20:24:22.14#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.20:24:22.14#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.20:24:22.14#ibcon#enter wrdev, iclass 12, count 0 2006.173.20:24:22.14#ibcon#first serial, iclass 12, count 0 2006.173.20:24:22.14#ibcon#enter sib2, iclass 12, count 0 2006.173.20:24:22.14#ibcon#flushed, iclass 12, count 0 2006.173.20:24:22.14#ibcon#about to write, iclass 12, count 0 2006.173.20:24:22.14#ibcon#wrote, iclass 12, count 0 2006.173.20:24:22.14#ibcon#about to read 3, iclass 12, count 0 2006.173.20:24:22.16#ibcon#read 3, iclass 12, count 0 2006.173.20:24:22.16#ibcon#about to read 4, iclass 12, count 0 2006.173.20:24:22.16#ibcon#read 4, iclass 12, count 0 2006.173.20:24:22.16#ibcon#about to read 5, iclass 12, count 0 2006.173.20:24:22.16#ibcon#read 5, iclass 12, count 0 2006.173.20:24:22.16#ibcon#about to read 6, iclass 12, count 0 2006.173.20:24:22.16#ibcon#read 6, iclass 12, count 0 2006.173.20:24:22.16#ibcon#end of sib2, iclass 12, count 0 2006.173.20:24:22.16#ibcon#*mode == 0, iclass 12, count 0 2006.173.20:24:22.16#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.20:24:22.16#ibcon#[25=USB\r\n] 2006.173.20:24:22.16#ibcon#*before write, iclass 12, count 0 2006.173.20:24:22.16#ibcon#enter sib2, iclass 12, count 0 2006.173.20:24:22.16#ibcon#flushed, iclass 12, count 0 2006.173.20:24:22.16#ibcon#about to write, iclass 12, count 0 2006.173.20:24:22.16#ibcon#wrote, iclass 12, count 0 2006.173.20:24:22.16#ibcon#about to read 3, iclass 12, count 0 2006.173.20:24:22.19#ibcon#read 3, iclass 12, count 0 2006.173.20:24:22.19#ibcon#about to read 4, iclass 12, count 0 2006.173.20:24:22.19#ibcon#read 4, iclass 12, count 0 2006.173.20:24:22.19#ibcon#about to read 5, iclass 12, count 0 2006.173.20:24:22.19#ibcon#read 5, iclass 12, count 0 2006.173.20:24:22.19#ibcon#about to read 6, iclass 12, count 0 2006.173.20:24:22.19#ibcon#read 6, iclass 12, count 0 2006.173.20:24:22.19#ibcon#end of sib2, iclass 12, count 0 2006.173.20:24:22.19#ibcon#*after write, iclass 12, count 0 2006.173.20:24:22.19#ibcon#*before return 0, iclass 12, count 0 2006.173.20:24:22.19#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.20:24:22.19#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.20:24:22.19#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.20:24:22.19#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.20:24:22.19$vck44/valo=7,864.99 2006.173.20:24:22.19#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.20:24:22.19#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.20:24:22.19#ibcon#ireg 17 cls_cnt 0 2006.173.20:24:22.19#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.20:24:22.19#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.20:24:22.19#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.20:24:22.19#ibcon#enter wrdev, iclass 15, count 0 2006.173.20:24:22.19#ibcon#first serial, iclass 15, count 0 2006.173.20:24:22.19#ibcon#enter sib2, iclass 15, count 0 2006.173.20:24:22.19#ibcon#flushed, iclass 15, count 0 2006.173.20:24:22.19#ibcon#about to write, iclass 15, count 0 2006.173.20:24:22.19#ibcon#wrote, iclass 15, count 0 2006.173.20:24:22.19#ibcon#about to read 3, iclass 15, count 0 2006.173.20:24:22.21#ibcon#read 3, iclass 15, count 0 2006.173.20:24:22.21#ibcon#about to read 4, iclass 15, count 0 2006.173.20:24:22.21#ibcon#read 4, iclass 15, count 0 2006.173.20:24:22.21#ibcon#about to read 5, iclass 15, count 0 2006.173.20:24:22.21#ibcon#read 5, iclass 15, count 0 2006.173.20:24:22.21#ibcon#about to read 6, iclass 15, count 0 2006.173.20:24:22.21#ibcon#read 6, iclass 15, count 0 2006.173.20:24:22.21#ibcon#end of sib2, iclass 15, count 0 2006.173.20:24:22.21#ibcon#*mode == 0, iclass 15, count 0 2006.173.20:24:22.21#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.20:24:22.21#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.20:24:22.21#ibcon#*before write, iclass 15, count 0 2006.173.20:24:22.21#ibcon#enter sib2, iclass 15, count 0 2006.173.20:24:22.21#ibcon#flushed, iclass 15, count 0 2006.173.20:24:22.21#ibcon#about to write, iclass 15, count 0 2006.173.20:24:22.21#ibcon#wrote, iclass 15, count 0 2006.173.20:24:22.21#ibcon#about to read 3, iclass 15, count 0 2006.173.20:24:22.25#ibcon#read 3, iclass 15, count 0 2006.173.20:24:22.25#ibcon#about to read 4, iclass 15, count 0 2006.173.20:24:22.25#ibcon#read 4, iclass 15, count 0 2006.173.20:24:22.25#ibcon#about to read 5, iclass 15, count 0 2006.173.20:24:22.25#ibcon#read 5, iclass 15, count 0 2006.173.20:24:22.25#ibcon#about to read 6, iclass 15, count 0 2006.173.20:24:22.25#ibcon#read 6, iclass 15, count 0 2006.173.20:24:22.25#ibcon#end of sib2, iclass 15, count 0 2006.173.20:24:22.25#ibcon#*after write, iclass 15, count 0 2006.173.20:24:22.25#ibcon#*before return 0, iclass 15, count 0 2006.173.20:24:22.25#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.20:24:22.25#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.20:24:22.25#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.20:24:22.25#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.20:24:22.25$vck44/va=7,4 2006.173.20:24:22.25#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.20:24:22.25#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.20:24:22.25#ibcon#ireg 11 cls_cnt 2 2006.173.20:24:22.25#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.20:24:22.31#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.20:24:22.31#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.20:24:22.31#ibcon#enter wrdev, iclass 17, count 2 2006.173.20:24:22.31#ibcon#first serial, iclass 17, count 2 2006.173.20:24:22.31#ibcon#enter sib2, iclass 17, count 2 2006.173.20:24:22.31#ibcon#flushed, iclass 17, count 2 2006.173.20:24:22.31#ibcon#about to write, iclass 17, count 2 2006.173.20:24:22.31#ibcon#wrote, iclass 17, count 2 2006.173.20:24:22.31#ibcon#about to read 3, iclass 17, count 2 2006.173.20:24:22.33#ibcon#read 3, iclass 17, count 2 2006.173.20:24:22.33#ibcon#about to read 4, iclass 17, count 2 2006.173.20:24:22.33#ibcon#read 4, iclass 17, count 2 2006.173.20:24:22.33#ibcon#about to read 5, iclass 17, count 2 2006.173.20:24:22.33#ibcon#read 5, iclass 17, count 2 2006.173.20:24:22.33#ibcon#about to read 6, iclass 17, count 2 2006.173.20:24:22.33#ibcon#read 6, iclass 17, count 2 2006.173.20:24:22.33#ibcon#end of sib2, iclass 17, count 2 2006.173.20:24:22.33#ibcon#*mode == 0, iclass 17, count 2 2006.173.20:24:22.33#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.20:24:22.33#ibcon#[25=AT07-04\r\n] 2006.173.20:24:22.33#ibcon#*before write, iclass 17, count 2 2006.173.20:24:22.33#ibcon#enter sib2, iclass 17, count 2 2006.173.20:24:22.33#ibcon#flushed, iclass 17, count 2 2006.173.20:24:22.33#ibcon#about to write, iclass 17, count 2 2006.173.20:24:22.33#ibcon#wrote, iclass 17, count 2 2006.173.20:24:22.33#ibcon#about to read 3, iclass 17, count 2 2006.173.20:24:22.36#ibcon#read 3, iclass 17, count 2 2006.173.20:24:22.36#ibcon#about to read 4, iclass 17, count 2 2006.173.20:24:22.36#ibcon#read 4, iclass 17, count 2 2006.173.20:24:22.36#ibcon#about to read 5, iclass 17, count 2 2006.173.20:24:22.36#ibcon#read 5, iclass 17, count 2 2006.173.20:24:22.36#ibcon#about to read 6, iclass 17, count 2 2006.173.20:24:22.36#ibcon#read 6, iclass 17, count 2 2006.173.20:24:22.36#ibcon#end of sib2, iclass 17, count 2 2006.173.20:24:22.36#ibcon#*after write, iclass 17, count 2 2006.173.20:24:22.36#ibcon#*before return 0, iclass 17, count 2 2006.173.20:24:22.36#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.20:24:22.36#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.20:24:22.36#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.20:24:22.36#ibcon#ireg 7 cls_cnt 0 2006.173.20:24:22.36#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.20:24:22.48#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.20:24:22.48#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.20:24:22.48#ibcon#enter wrdev, iclass 17, count 0 2006.173.20:24:22.48#ibcon#first serial, iclass 17, count 0 2006.173.20:24:22.48#ibcon#enter sib2, iclass 17, count 0 2006.173.20:24:22.48#ibcon#flushed, iclass 17, count 0 2006.173.20:24:22.48#ibcon#about to write, iclass 17, count 0 2006.173.20:24:22.48#ibcon#wrote, iclass 17, count 0 2006.173.20:24:22.48#ibcon#about to read 3, iclass 17, count 0 2006.173.20:24:22.50#ibcon#read 3, iclass 17, count 0 2006.173.20:24:22.50#ibcon#about to read 4, iclass 17, count 0 2006.173.20:24:22.50#ibcon#read 4, iclass 17, count 0 2006.173.20:24:22.50#ibcon#about to read 5, iclass 17, count 0 2006.173.20:24:22.50#ibcon#read 5, iclass 17, count 0 2006.173.20:24:22.50#ibcon#about to read 6, iclass 17, count 0 2006.173.20:24:22.50#ibcon#read 6, iclass 17, count 0 2006.173.20:24:22.50#ibcon#end of sib2, iclass 17, count 0 2006.173.20:24:22.50#ibcon#*mode == 0, iclass 17, count 0 2006.173.20:24:22.50#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.20:24:22.50#ibcon#[25=USB\r\n] 2006.173.20:24:22.50#ibcon#*before write, iclass 17, count 0 2006.173.20:24:22.50#ibcon#enter sib2, iclass 17, count 0 2006.173.20:24:22.50#ibcon#flushed, iclass 17, count 0 2006.173.20:24:22.50#ibcon#about to write, iclass 17, count 0 2006.173.20:24:22.50#ibcon#wrote, iclass 17, count 0 2006.173.20:24:22.50#ibcon#about to read 3, iclass 17, count 0 2006.173.20:24:22.53#ibcon#read 3, iclass 17, count 0 2006.173.20:24:22.53#ibcon#about to read 4, iclass 17, count 0 2006.173.20:24:22.53#ibcon#read 4, iclass 17, count 0 2006.173.20:24:22.53#ibcon#about to read 5, iclass 17, count 0 2006.173.20:24:22.53#ibcon#read 5, iclass 17, count 0 2006.173.20:24:22.53#ibcon#about to read 6, iclass 17, count 0 2006.173.20:24:22.53#ibcon#read 6, iclass 17, count 0 2006.173.20:24:22.53#ibcon#end of sib2, iclass 17, count 0 2006.173.20:24:22.53#ibcon#*after write, iclass 17, count 0 2006.173.20:24:22.53#ibcon#*before return 0, iclass 17, count 0 2006.173.20:24:22.53#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.20:24:22.53#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.20:24:22.53#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.20:24:22.53#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.20:24:22.53$vck44/valo=8,884.99 2006.173.20:24:22.53#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.20:24:22.53#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.20:24:22.53#ibcon#ireg 17 cls_cnt 0 2006.173.20:24:22.53#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.20:24:22.53#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.20:24:22.53#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.20:24:22.53#ibcon#enter wrdev, iclass 19, count 0 2006.173.20:24:22.53#ibcon#first serial, iclass 19, count 0 2006.173.20:24:22.53#ibcon#enter sib2, iclass 19, count 0 2006.173.20:24:22.53#ibcon#flushed, iclass 19, count 0 2006.173.20:24:22.53#ibcon#about to write, iclass 19, count 0 2006.173.20:24:22.53#ibcon#wrote, iclass 19, count 0 2006.173.20:24:22.53#ibcon#about to read 3, iclass 19, count 0 2006.173.20:24:22.55#ibcon#read 3, iclass 19, count 0 2006.173.20:24:22.55#ibcon#about to read 4, iclass 19, count 0 2006.173.20:24:22.55#ibcon#read 4, iclass 19, count 0 2006.173.20:24:22.55#ibcon#about to read 5, iclass 19, count 0 2006.173.20:24:22.55#ibcon#read 5, iclass 19, count 0 2006.173.20:24:22.55#ibcon#about to read 6, iclass 19, count 0 2006.173.20:24:22.55#ibcon#read 6, iclass 19, count 0 2006.173.20:24:22.55#ibcon#end of sib2, iclass 19, count 0 2006.173.20:24:22.55#ibcon#*mode == 0, iclass 19, count 0 2006.173.20:24:22.55#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.20:24:22.55#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.20:24:22.55#ibcon#*before write, iclass 19, count 0 2006.173.20:24:22.55#ibcon#enter sib2, iclass 19, count 0 2006.173.20:24:22.55#ibcon#flushed, iclass 19, count 0 2006.173.20:24:22.55#ibcon#about to write, iclass 19, count 0 2006.173.20:24:22.55#ibcon#wrote, iclass 19, count 0 2006.173.20:24:22.55#ibcon#about to read 3, iclass 19, count 0 2006.173.20:24:22.59#ibcon#read 3, iclass 19, count 0 2006.173.20:24:22.59#ibcon#about to read 4, iclass 19, count 0 2006.173.20:24:22.59#ibcon#read 4, iclass 19, count 0 2006.173.20:24:22.59#ibcon#about to read 5, iclass 19, count 0 2006.173.20:24:22.59#ibcon#read 5, iclass 19, count 0 2006.173.20:24:22.59#ibcon#about to read 6, iclass 19, count 0 2006.173.20:24:22.59#ibcon#read 6, iclass 19, count 0 2006.173.20:24:22.59#ibcon#end of sib2, iclass 19, count 0 2006.173.20:24:22.59#ibcon#*after write, iclass 19, count 0 2006.173.20:24:22.59#ibcon#*before return 0, iclass 19, count 0 2006.173.20:24:22.59#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.20:24:22.59#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.20:24:22.59#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.20:24:22.59#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.20:24:22.59$vck44/va=8,4 2006.173.20:24:22.59#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.20:24:22.59#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.20:24:22.59#ibcon#ireg 11 cls_cnt 2 2006.173.20:24:22.59#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.20:24:22.65#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.20:24:22.65#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.20:24:22.65#ibcon#enter wrdev, iclass 21, count 2 2006.173.20:24:22.65#ibcon#first serial, iclass 21, count 2 2006.173.20:24:22.65#ibcon#enter sib2, iclass 21, count 2 2006.173.20:24:22.65#ibcon#flushed, iclass 21, count 2 2006.173.20:24:22.65#ibcon#about to write, iclass 21, count 2 2006.173.20:24:22.65#ibcon#wrote, iclass 21, count 2 2006.173.20:24:22.65#ibcon#about to read 3, iclass 21, count 2 2006.173.20:24:22.67#ibcon#read 3, iclass 21, count 2 2006.173.20:24:22.67#ibcon#about to read 4, iclass 21, count 2 2006.173.20:24:22.67#ibcon#read 4, iclass 21, count 2 2006.173.20:24:22.67#ibcon#about to read 5, iclass 21, count 2 2006.173.20:24:22.67#ibcon#read 5, iclass 21, count 2 2006.173.20:24:22.67#ibcon#about to read 6, iclass 21, count 2 2006.173.20:24:22.67#ibcon#read 6, iclass 21, count 2 2006.173.20:24:22.67#ibcon#end of sib2, iclass 21, count 2 2006.173.20:24:22.67#ibcon#*mode == 0, iclass 21, count 2 2006.173.20:24:22.67#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.20:24:22.67#ibcon#[25=AT08-04\r\n] 2006.173.20:24:22.67#ibcon#*before write, iclass 21, count 2 2006.173.20:24:22.67#ibcon#enter sib2, iclass 21, count 2 2006.173.20:24:22.67#ibcon#flushed, iclass 21, count 2 2006.173.20:24:22.67#ibcon#about to write, iclass 21, count 2 2006.173.20:24:22.67#ibcon#wrote, iclass 21, count 2 2006.173.20:24:22.67#ibcon#about to read 3, iclass 21, count 2 2006.173.20:24:22.70#ibcon#read 3, iclass 21, count 2 2006.173.20:24:22.70#ibcon#about to read 4, iclass 21, count 2 2006.173.20:24:22.70#ibcon#read 4, iclass 21, count 2 2006.173.20:24:22.70#ibcon#about to read 5, iclass 21, count 2 2006.173.20:24:22.70#ibcon#read 5, iclass 21, count 2 2006.173.20:24:22.70#ibcon#about to read 6, iclass 21, count 2 2006.173.20:24:22.70#ibcon#read 6, iclass 21, count 2 2006.173.20:24:22.70#ibcon#end of sib2, iclass 21, count 2 2006.173.20:24:22.70#ibcon#*after write, iclass 21, count 2 2006.173.20:24:22.70#ibcon#*before return 0, iclass 21, count 2 2006.173.20:24:22.70#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.20:24:22.70#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.20:24:22.70#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.20:24:22.70#ibcon#ireg 7 cls_cnt 0 2006.173.20:24:22.70#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.20:24:22.82#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.20:24:22.82#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.20:24:22.82#ibcon#enter wrdev, iclass 21, count 0 2006.173.20:24:22.82#ibcon#first serial, iclass 21, count 0 2006.173.20:24:22.82#ibcon#enter sib2, iclass 21, count 0 2006.173.20:24:22.82#ibcon#flushed, iclass 21, count 0 2006.173.20:24:22.82#ibcon#about to write, iclass 21, count 0 2006.173.20:24:22.82#ibcon#wrote, iclass 21, count 0 2006.173.20:24:22.82#ibcon#about to read 3, iclass 21, count 0 2006.173.20:24:22.84#ibcon#read 3, iclass 21, count 0 2006.173.20:24:22.84#ibcon#about to read 4, iclass 21, count 0 2006.173.20:24:22.84#ibcon#read 4, iclass 21, count 0 2006.173.20:24:22.84#ibcon#about to read 5, iclass 21, count 0 2006.173.20:24:22.84#ibcon#read 5, iclass 21, count 0 2006.173.20:24:22.84#ibcon#about to read 6, iclass 21, count 0 2006.173.20:24:22.84#ibcon#read 6, iclass 21, count 0 2006.173.20:24:22.84#ibcon#end of sib2, iclass 21, count 0 2006.173.20:24:22.84#ibcon#*mode == 0, iclass 21, count 0 2006.173.20:24:22.84#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.20:24:22.84#ibcon#[25=USB\r\n] 2006.173.20:24:22.84#ibcon#*before write, iclass 21, count 0 2006.173.20:24:22.84#ibcon#enter sib2, iclass 21, count 0 2006.173.20:24:22.84#ibcon#flushed, iclass 21, count 0 2006.173.20:24:22.84#ibcon#about to write, iclass 21, count 0 2006.173.20:24:22.84#ibcon#wrote, iclass 21, count 0 2006.173.20:24:22.84#ibcon#about to read 3, iclass 21, count 0 2006.173.20:24:22.87#ibcon#read 3, iclass 21, count 0 2006.173.20:24:22.87#ibcon#about to read 4, iclass 21, count 0 2006.173.20:24:22.87#ibcon#read 4, iclass 21, count 0 2006.173.20:24:22.87#ibcon#about to read 5, iclass 21, count 0 2006.173.20:24:22.87#ibcon#read 5, iclass 21, count 0 2006.173.20:24:22.87#ibcon#about to read 6, iclass 21, count 0 2006.173.20:24:22.87#ibcon#read 6, iclass 21, count 0 2006.173.20:24:22.87#ibcon#end of sib2, iclass 21, count 0 2006.173.20:24:22.87#ibcon#*after write, iclass 21, count 0 2006.173.20:24:22.87#ibcon#*before return 0, iclass 21, count 0 2006.173.20:24:22.87#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.20:24:22.87#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.20:24:22.87#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.20:24:22.87#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.20:24:22.87$vck44/vblo=1,629.99 2006.173.20:24:22.87#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.20:24:22.87#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.20:24:22.87#ibcon#ireg 17 cls_cnt 0 2006.173.20:24:22.87#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.20:24:22.87#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.20:24:22.87#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.20:24:22.87#ibcon#enter wrdev, iclass 23, count 0 2006.173.20:24:22.87#ibcon#first serial, iclass 23, count 0 2006.173.20:24:22.87#ibcon#enter sib2, iclass 23, count 0 2006.173.20:24:22.87#ibcon#flushed, iclass 23, count 0 2006.173.20:24:22.87#ibcon#about to write, iclass 23, count 0 2006.173.20:24:22.87#ibcon#wrote, iclass 23, count 0 2006.173.20:24:22.87#ibcon#about to read 3, iclass 23, count 0 2006.173.20:24:22.89#ibcon#read 3, iclass 23, count 0 2006.173.20:24:22.89#ibcon#about to read 4, iclass 23, count 0 2006.173.20:24:22.89#ibcon#read 4, iclass 23, count 0 2006.173.20:24:22.89#ibcon#about to read 5, iclass 23, count 0 2006.173.20:24:22.89#ibcon#read 5, iclass 23, count 0 2006.173.20:24:22.89#ibcon#about to read 6, iclass 23, count 0 2006.173.20:24:22.89#ibcon#read 6, iclass 23, count 0 2006.173.20:24:22.89#ibcon#end of sib2, iclass 23, count 0 2006.173.20:24:22.89#ibcon#*mode == 0, iclass 23, count 0 2006.173.20:24:22.89#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.20:24:22.89#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.20:24:22.89#ibcon#*before write, iclass 23, count 0 2006.173.20:24:22.89#ibcon#enter sib2, iclass 23, count 0 2006.173.20:24:22.89#ibcon#flushed, iclass 23, count 0 2006.173.20:24:22.89#ibcon#about to write, iclass 23, count 0 2006.173.20:24:22.89#ibcon#wrote, iclass 23, count 0 2006.173.20:24:22.89#ibcon#about to read 3, iclass 23, count 0 2006.173.20:24:22.93#ibcon#read 3, iclass 23, count 0 2006.173.20:24:22.93#ibcon#about to read 4, iclass 23, count 0 2006.173.20:24:22.93#ibcon#read 4, iclass 23, count 0 2006.173.20:24:22.93#ibcon#about to read 5, iclass 23, count 0 2006.173.20:24:22.93#ibcon#read 5, iclass 23, count 0 2006.173.20:24:22.93#ibcon#about to read 6, iclass 23, count 0 2006.173.20:24:22.93#ibcon#read 6, iclass 23, count 0 2006.173.20:24:22.93#ibcon#end of sib2, iclass 23, count 0 2006.173.20:24:22.93#ibcon#*after write, iclass 23, count 0 2006.173.20:24:22.93#ibcon#*before return 0, iclass 23, count 0 2006.173.20:24:22.93#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.20:24:22.93#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.20:24:22.93#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.20:24:22.93#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.20:24:22.93$vck44/vb=1,4 2006.173.20:24:22.93#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.20:24:22.93#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.20:24:22.93#ibcon#ireg 11 cls_cnt 2 2006.173.20:24:22.93#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.20:24:22.93#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.20:24:22.93#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.20:24:22.93#ibcon#enter wrdev, iclass 25, count 2 2006.173.20:24:22.93#ibcon#first serial, iclass 25, count 2 2006.173.20:24:22.93#ibcon#enter sib2, iclass 25, count 2 2006.173.20:24:22.93#ibcon#flushed, iclass 25, count 2 2006.173.20:24:22.93#ibcon#about to write, iclass 25, count 2 2006.173.20:24:22.93#ibcon#wrote, iclass 25, count 2 2006.173.20:24:22.93#ibcon#about to read 3, iclass 25, count 2 2006.173.20:24:22.95#ibcon#read 3, iclass 25, count 2 2006.173.20:24:22.95#ibcon#about to read 4, iclass 25, count 2 2006.173.20:24:22.95#ibcon#read 4, iclass 25, count 2 2006.173.20:24:22.95#ibcon#about to read 5, iclass 25, count 2 2006.173.20:24:22.95#ibcon#read 5, iclass 25, count 2 2006.173.20:24:22.95#ibcon#about to read 6, iclass 25, count 2 2006.173.20:24:22.95#ibcon#read 6, iclass 25, count 2 2006.173.20:24:22.95#ibcon#end of sib2, iclass 25, count 2 2006.173.20:24:22.95#ibcon#*mode == 0, iclass 25, count 2 2006.173.20:24:22.95#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.20:24:22.95#ibcon#[27=AT01-04\r\n] 2006.173.20:24:22.95#ibcon#*before write, iclass 25, count 2 2006.173.20:24:22.95#ibcon#enter sib2, iclass 25, count 2 2006.173.20:24:22.95#ibcon#flushed, iclass 25, count 2 2006.173.20:24:22.95#ibcon#about to write, iclass 25, count 2 2006.173.20:24:22.95#ibcon#wrote, iclass 25, count 2 2006.173.20:24:22.95#ibcon#about to read 3, iclass 25, count 2 2006.173.20:24:22.98#ibcon#read 3, iclass 25, count 2 2006.173.20:24:22.98#ibcon#about to read 4, iclass 25, count 2 2006.173.20:24:22.98#ibcon#read 4, iclass 25, count 2 2006.173.20:24:22.98#ibcon#about to read 5, iclass 25, count 2 2006.173.20:24:22.98#ibcon#read 5, iclass 25, count 2 2006.173.20:24:22.98#ibcon#about to read 6, iclass 25, count 2 2006.173.20:24:22.98#ibcon#read 6, iclass 25, count 2 2006.173.20:24:22.98#ibcon#end of sib2, iclass 25, count 2 2006.173.20:24:22.98#ibcon#*after write, iclass 25, count 2 2006.173.20:24:22.98#ibcon#*before return 0, iclass 25, count 2 2006.173.20:24:22.98#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.20:24:22.98#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.20:24:22.98#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.20:24:22.98#ibcon#ireg 7 cls_cnt 0 2006.173.20:24:22.98#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.20:24:23.10#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.20:24:23.10#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.20:24:23.10#ibcon#enter wrdev, iclass 25, count 0 2006.173.20:24:23.10#ibcon#first serial, iclass 25, count 0 2006.173.20:24:23.10#ibcon#enter sib2, iclass 25, count 0 2006.173.20:24:23.10#ibcon#flushed, iclass 25, count 0 2006.173.20:24:23.10#ibcon#about to write, iclass 25, count 0 2006.173.20:24:23.10#ibcon#wrote, iclass 25, count 0 2006.173.20:24:23.10#ibcon#about to read 3, iclass 25, count 0 2006.173.20:24:23.12#ibcon#read 3, iclass 25, count 0 2006.173.20:24:23.12#ibcon#about to read 4, iclass 25, count 0 2006.173.20:24:23.12#ibcon#read 4, iclass 25, count 0 2006.173.20:24:23.12#ibcon#about to read 5, iclass 25, count 0 2006.173.20:24:23.12#ibcon#read 5, iclass 25, count 0 2006.173.20:24:23.12#ibcon#about to read 6, iclass 25, count 0 2006.173.20:24:23.12#ibcon#read 6, iclass 25, count 0 2006.173.20:24:23.12#ibcon#end of sib2, iclass 25, count 0 2006.173.20:24:23.12#ibcon#*mode == 0, iclass 25, count 0 2006.173.20:24:23.12#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.20:24:23.12#ibcon#[27=USB\r\n] 2006.173.20:24:23.12#ibcon#*before write, iclass 25, count 0 2006.173.20:24:23.12#ibcon#enter sib2, iclass 25, count 0 2006.173.20:24:23.12#ibcon#flushed, iclass 25, count 0 2006.173.20:24:23.12#ibcon#about to write, iclass 25, count 0 2006.173.20:24:23.12#ibcon#wrote, iclass 25, count 0 2006.173.20:24:23.12#ibcon#about to read 3, iclass 25, count 0 2006.173.20:24:23.15#ibcon#read 3, iclass 25, count 0 2006.173.20:24:23.15#ibcon#about to read 4, iclass 25, count 0 2006.173.20:24:23.15#ibcon#read 4, iclass 25, count 0 2006.173.20:24:23.15#ibcon#about to read 5, iclass 25, count 0 2006.173.20:24:23.15#ibcon#read 5, iclass 25, count 0 2006.173.20:24:23.15#ibcon#about to read 6, iclass 25, count 0 2006.173.20:24:23.15#ibcon#read 6, iclass 25, count 0 2006.173.20:24:23.15#ibcon#end of sib2, iclass 25, count 0 2006.173.20:24:23.15#ibcon#*after write, iclass 25, count 0 2006.173.20:24:23.15#ibcon#*before return 0, iclass 25, count 0 2006.173.20:24:23.15#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.20:24:23.15#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.20:24:23.15#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.20:24:23.15#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.20:24:23.15$vck44/vblo=2,634.99 2006.173.20:24:23.15#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.20:24:23.15#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.20:24:23.15#ibcon#ireg 17 cls_cnt 0 2006.173.20:24:23.15#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.20:24:23.15#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.20:24:23.15#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.20:24:23.15#ibcon#enter wrdev, iclass 27, count 0 2006.173.20:24:23.15#ibcon#first serial, iclass 27, count 0 2006.173.20:24:23.15#ibcon#enter sib2, iclass 27, count 0 2006.173.20:24:23.15#ibcon#flushed, iclass 27, count 0 2006.173.20:24:23.15#ibcon#about to write, iclass 27, count 0 2006.173.20:24:23.15#ibcon#wrote, iclass 27, count 0 2006.173.20:24:23.15#ibcon#about to read 3, iclass 27, count 0 2006.173.20:24:23.17#ibcon#read 3, iclass 27, count 0 2006.173.20:24:23.17#ibcon#about to read 4, iclass 27, count 0 2006.173.20:24:23.17#ibcon#read 4, iclass 27, count 0 2006.173.20:24:23.17#ibcon#about to read 5, iclass 27, count 0 2006.173.20:24:23.17#ibcon#read 5, iclass 27, count 0 2006.173.20:24:23.17#ibcon#about to read 6, iclass 27, count 0 2006.173.20:24:23.17#ibcon#read 6, iclass 27, count 0 2006.173.20:24:23.17#ibcon#end of sib2, iclass 27, count 0 2006.173.20:24:23.17#ibcon#*mode == 0, iclass 27, count 0 2006.173.20:24:23.17#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.20:24:23.17#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.20:24:23.17#ibcon#*before write, iclass 27, count 0 2006.173.20:24:23.17#ibcon#enter sib2, iclass 27, count 0 2006.173.20:24:23.17#ibcon#flushed, iclass 27, count 0 2006.173.20:24:23.17#ibcon#about to write, iclass 27, count 0 2006.173.20:24:23.17#ibcon#wrote, iclass 27, count 0 2006.173.20:24:23.17#ibcon#about to read 3, iclass 27, count 0 2006.173.20:24:23.21#ibcon#read 3, iclass 27, count 0 2006.173.20:24:23.21#ibcon#about to read 4, iclass 27, count 0 2006.173.20:24:23.21#ibcon#read 4, iclass 27, count 0 2006.173.20:24:23.21#ibcon#about to read 5, iclass 27, count 0 2006.173.20:24:23.21#ibcon#read 5, iclass 27, count 0 2006.173.20:24:23.21#ibcon#about to read 6, iclass 27, count 0 2006.173.20:24:23.21#ibcon#read 6, iclass 27, count 0 2006.173.20:24:23.21#ibcon#end of sib2, iclass 27, count 0 2006.173.20:24:23.21#ibcon#*after write, iclass 27, count 0 2006.173.20:24:23.21#ibcon#*before return 0, iclass 27, count 0 2006.173.20:24:23.21#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.20:24:23.21#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.20:24:23.21#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.20:24:23.21#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.20:24:23.21$vck44/vb=2,4 2006.173.20:24:23.21#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.20:24:23.21#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.20:24:23.21#ibcon#ireg 11 cls_cnt 2 2006.173.20:24:23.21#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.20:24:23.27#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.20:24:23.27#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.20:24:23.27#ibcon#enter wrdev, iclass 29, count 2 2006.173.20:24:23.27#ibcon#first serial, iclass 29, count 2 2006.173.20:24:23.27#ibcon#enter sib2, iclass 29, count 2 2006.173.20:24:23.27#ibcon#flushed, iclass 29, count 2 2006.173.20:24:23.27#ibcon#about to write, iclass 29, count 2 2006.173.20:24:23.27#ibcon#wrote, iclass 29, count 2 2006.173.20:24:23.27#ibcon#about to read 3, iclass 29, count 2 2006.173.20:24:23.29#ibcon#read 3, iclass 29, count 2 2006.173.20:24:23.29#ibcon#about to read 4, iclass 29, count 2 2006.173.20:24:23.29#ibcon#read 4, iclass 29, count 2 2006.173.20:24:23.29#ibcon#about to read 5, iclass 29, count 2 2006.173.20:24:23.29#ibcon#read 5, iclass 29, count 2 2006.173.20:24:23.29#ibcon#about to read 6, iclass 29, count 2 2006.173.20:24:23.29#ibcon#read 6, iclass 29, count 2 2006.173.20:24:23.29#ibcon#end of sib2, iclass 29, count 2 2006.173.20:24:23.29#ibcon#*mode == 0, iclass 29, count 2 2006.173.20:24:23.29#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.20:24:23.29#ibcon#[27=AT02-04\r\n] 2006.173.20:24:23.29#ibcon#*before write, iclass 29, count 2 2006.173.20:24:23.29#ibcon#enter sib2, iclass 29, count 2 2006.173.20:24:23.29#ibcon#flushed, iclass 29, count 2 2006.173.20:24:23.29#ibcon#about to write, iclass 29, count 2 2006.173.20:24:23.29#ibcon#wrote, iclass 29, count 2 2006.173.20:24:23.29#ibcon#about to read 3, iclass 29, count 2 2006.173.20:24:23.32#ibcon#read 3, iclass 29, count 2 2006.173.20:24:23.32#ibcon#about to read 4, iclass 29, count 2 2006.173.20:24:23.32#ibcon#read 4, iclass 29, count 2 2006.173.20:24:23.32#ibcon#about to read 5, iclass 29, count 2 2006.173.20:24:23.32#ibcon#read 5, iclass 29, count 2 2006.173.20:24:23.32#ibcon#about to read 6, iclass 29, count 2 2006.173.20:24:23.32#ibcon#read 6, iclass 29, count 2 2006.173.20:24:23.32#ibcon#end of sib2, iclass 29, count 2 2006.173.20:24:23.32#ibcon#*after write, iclass 29, count 2 2006.173.20:24:23.32#ibcon#*before return 0, iclass 29, count 2 2006.173.20:24:23.32#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.20:24:23.32#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.20:24:23.32#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.20:24:23.32#ibcon#ireg 7 cls_cnt 0 2006.173.20:24:23.32#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.20:24:23.44#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.20:24:23.44#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.20:24:23.44#ibcon#enter wrdev, iclass 29, count 0 2006.173.20:24:23.44#ibcon#first serial, iclass 29, count 0 2006.173.20:24:23.44#ibcon#enter sib2, iclass 29, count 0 2006.173.20:24:23.44#ibcon#flushed, iclass 29, count 0 2006.173.20:24:23.44#ibcon#about to write, iclass 29, count 0 2006.173.20:24:23.44#ibcon#wrote, iclass 29, count 0 2006.173.20:24:23.44#ibcon#about to read 3, iclass 29, count 0 2006.173.20:24:23.46#ibcon#read 3, iclass 29, count 0 2006.173.20:24:23.46#ibcon#about to read 4, iclass 29, count 0 2006.173.20:24:23.46#ibcon#read 4, iclass 29, count 0 2006.173.20:24:23.46#ibcon#about to read 5, iclass 29, count 0 2006.173.20:24:23.46#ibcon#read 5, iclass 29, count 0 2006.173.20:24:23.46#ibcon#about to read 6, iclass 29, count 0 2006.173.20:24:23.46#ibcon#read 6, iclass 29, count 0 2006.173.20:24:23.46#ibcon#end of sib2, iclass 29, count 0 2006.173.20:24:23.46#ibcon#*mode == 0, iclass 29, count 0 2006.173.20:24:23.46#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.20:24:23.46#ibcon#[27=USB\r\n] 2006.173.20:24:23.46#ibcon#*before write, iclass 29, count 0 2006.173.20:24:23.46#ibcon#enter sib2, iclass 29, count 0 2006.173.20:24:23.46#ibcon#flushed, iclass 29, count 0 2006.173.20:24:23.46#ibcon#about to write, iclass 29, count 0 2006.173.20:24:23.46#ibcon#wrote, iclass 29, count 0 2006.173.20:24:23.46#ibcon#about to read 3, iclass 29, count 0 2006.173.20:24:23.49#ibcon#read 3, iclass 29, count 0 2006.173.20:24:23.49#ibcon#about to read 4, iclass 29, count 0 2006.173.20:24:23.49#ibcon#read 4, iclass 29, count 0 2006.173.20:24:23.49#ibcon#about to read 5, iclass 29, count 0 2006.173.20:24:23.49#ibcon#read 5, iclass 29, count 0 2006.173.20:24:23.49#ibcon#about to read 6, iclass 29, count 0 2006.173.20:24:23.49#ibcon#read 6, iclass 29, count 0 2006.173.20:24:23.49#ibcon#end of sib2, iclass 29, count 0 2006.173.20:24:23.49#ibcon#*after write, iclass 29, count 0 2006.173.20:24:23.49#ibcon#*before return 0, iclass 29, count 0 2006.173.20:24:23.49#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.20:24:23.49#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.20:24:23.49#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.20:24:23.49#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.20:24:23.49$vck44/vblo=3,649.99 2006.173.20:24:23.49#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.20:24:23.49#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.20:24:23.49#ibcon#ireg 17 cls_cnt 0 2006.173.20:24:23.49#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.20:24:23.49#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.20:24:23.49#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.20:24:23.49#ibcon#enter wrdev, iclass 31, count 0 2006.173.20:24:23.49#ibcon#first serial, iclass 31, count 0 2006.173.20:24:23.49#ibcon#enter sib2, iclass 31, count 0 2006.173.20:24:23.49#ibcon#flushed, iclass 31, count 0 2006.173.20:24:23.49#ibcon#about to write, iclass 31, count 0 2006.173.20:24:23.49#ibcon#wrote, iclass 31, count 0 2006.173.20:24:23.49#ibcon#about to read 3, iclass 31, count 0 2006.173.20:24:23.51#ibcon#read 3, iclass 31, count 0 2006.173.20:24:23.51#ibcon#about to read 4, iclass 31, count 0 2006.173.20:24:23.51#ibcon#read 4, iclass 31, count 0 2006.173.20:24:23.51#ibcon#about to read 5, iclass 31, count 0 2006.173.20:24:23.51#ibcon#read 5, iclass 31, count 0 2006.173.20:24:23.51#ibcon#about to read 6, iclass 31, count 0 2006.173.20:24:23.51#ibcon#read 6, iclass 31, count 0 2006.173.20:24:23.51#ibcon#end of sib2, iclass 31, count 0 2006.173.20:24:23.51#ibcon#*mode == 0, iclass 31, count 0 2006.173.20:24:23.51#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.20:24:23.51#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.20:24:23.51#ibcon#*before write, iclass 31, count 0 2006.173.20:24:23.51#ibcon#enter sib2, iclass 31, count 0 2006.173.20:24:23.51#ibcon#flushed, iclass 31, count 0 2006.173.20:24:23.51#ibcon#about to write, iclass 31, count 0 2006.173.20:24:23.51#ibcon#wrote, iclass 31, count 0 2006.173.20:24:23.51#ibcon#about to read 3, iclass 31, count 0 2006.173.20:24:23.55#ibcon#read 3, iclass 31, count 0 2006.173.20:24:23.55#ibcon#about to read 4, iclass 31, count 0 2006.173.20:24:23.55#ibcon#read 4, iclass 31, count 0 2006.173.20:24:23.55#ibcon#about to read 5, iclass 31, count 0 2006.173.20:24:23.55#ibcon#read 5, iclass 31, count 0 2006.173.20:24:23.55#ibcon#about to read 6, iclass 31, count 0 2006.173.20:24:23.55#ibcon#read 6, iclass 31, count 0 2006.173.20:24:23.55#ibcon#end of sib2, iclass 31, count 0 2006.173.20:24:23.55#ibcon#*after write, iclass 31, count 0 2006.173.20:24:23.55#ibcon#*before return 0, iclass 31, count 0 2006.173.20:24:23.55#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.20:24:23.55#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.20:24:23.55#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.20:24:23.55#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.20:24:23.55$vck44/vb=3,4 2006.173.20:24:23.55#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.173.20:24:23.55#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.173.20:24:23.55#ibcon#ireg 11 cls_cnt 2 2006.173.20:24:23.55#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.20:24:23.61#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.20:24:23.61#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.20:24:23.61#ibcon#enter wrdev, iclass 33, count 2 2006.173.20:24:23.61#ibcon#first serial, iclass 33, count 2 2006.173.20:24:23.61#ibcon#enter sib2, iclass 33, count 2 2006.173.20:24:23.61#ibcon#flushed, iclass 33, count 2 2006.173.20:24:23.61#ibcon#about to write, iclass 33, count 2 2006.173.20:24:23.61#ibcon#wrote, iclass 33, count 2 2006.173.20:24:23.61#ibcon#about to read 3, iclass 33, count 2 2006.173.20:24:23.63#ibcon#read 3, iclass 33, count 2 2006.173.20:24:23.63#ibcon#about to read 4, iclass 33, count 2 2006.173.20:24:23.63#ibcon#read 4, iclass 33, count 2 2006.173.20:24:23.63#ibcon#about to read 5, iclass 33, count 2 2006.173.20:24:23.63#ibcon#read 5, iclass 33, count 2 2006.173.20:24:23.63#ibcon#about to read 6, iclass 33, count 2 2006.173.20:24:23.63#ibcon#read 6, iclass 33, count 2 2006.173.20:24:23.63#ibcon#end of sib2, iclass 33, count 2 2006.173.20:24:23.63#ibcon#*mode == 0, iclass 33, count 2 2006.173.20:24:23.63#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.173.20:24:23.63#ibcon#[27=AT03-04\r\n] 2006.173.20:24:23.63#ibcon#*before write, iclass 33, count 2 2006.173.20:24:23.63#ibcon#enter sib2, iclass 33, count 2 2006.173.20:24:23.63#ibcon#flushed, iclass 33, count 2 2006.173.20:24:23.63#ibcon#about to write, iclass 33, count 2 2006.173.20:24:23.63#ibcon#wrote, iclass 33, count 2 2006.173.20:24:23.63#ibcon#about to read 3, iclass 33, count 2 2006.173.20:24:23.66#ibcon#read 3, iclass 33, count 2 2006.173.20:24:23.66#ibcon#about to read 4, iclass 33, count 2 2006.173.20:24:23.66#ibcon#read 4, iclass 33, count 2 2006.173.20:24:23.66#ibcon#about to read 5, iclass 33, count 2 2006.173.20:24:23.66#ibcon#read 5, iclass 33, count 2 2006.173.20:24:23.66#ibcon#about to read 6, iclass 33, count 2 2006.173.20:24:23.66#ibcon#read 6, iclass 33, count 2 2006.173.20:24:23.66#ibcon#end of sib2, iclass 33, count 2 2006.173.20:24:23.66#ibcon#*after write, iclass 33, count 2 2006.173.20:24:23.66#ibcon#*before return 0, iclass 33, count 2 2006.173.20:24:23.66#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.20:24:23.66#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.173.20:24:23.66#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.173.20:24:23.66#ibcon#ireg 7 cls_cnt 0 2006.173.20:24:23.66#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.20:24:23.78#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.20:24:23.78#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.20:24:23.78#ibcon#enter wrdev, iclass 33, count 0 2006.173.20:24:23.78#ibcon#first serial, iclass 33, count 0 2006.173.20:24:23.78#ibcon#enter sib2, iclass 33, count 0 2006.173.20:24:23.78#ibcon#flushed, iclass 33, count 0 2006.173.20:24:23.78#ibcon#about to write, iclass 33, count 0 2006.173.20:24:23.78#ibcon#wrote, iclass 33, count 0 2006.173.20:24:23.78#ibcon#about to read 3, iclass 33, count 0 2006.173.20:24:23.80#ibcon#read 3, iclass 33, count 0 2006.173.20:24:23.80#ibcon#about to read 4, iclass 33, count 0 2006.173.20:24:23.80#ibcon#read 4, iclass 33, count 0 2006.173.20:24:23.80#ibcon#about to read 5, iclass 33, count 0 2006.173.20:24:23.80#ibcon#read 5, iclass 33, count 0 2006.173.20:24:23.80#ibcon#about to read 6, iclass 33, count 0 2006.173.20:24:23.80#ibcon#read 6, iclass 33, count 0 2006.173.20:24:23.80#ibcon#end of sib2, iclass 33, count 0 2006.173.20:24:23.80#ibcon#*mode == 0, iclass 33, count 0 2006.173.20:24:23.80#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.20:24:23.80#ibcon#[27=USB\r\n] 2006.173.20:24:23.80#ibcon#*before write, iclass 33, count 0 2006.173.20:24:23.80#ibcon#enter sib2, iclass 33, count 0 2006.173.20:24:23.80#ibcon#flushed, iclass 33, count 0 2006.173.20:24:23.80#ibcon#about to write, iclass 33, count 0 2006.173.20:24:23.80#ibcon#wrote, iclass 33, count 0 2006.173.20:24:23.80#ibcon#about to read 3, iclass 33, count 0 2006.173.20:24:23.83#ibcon#read 3, iclass 33, count 0 2006.173.20:24:23.83#ibcon#about to read 4, iclass 33, count 0 2006.173.20:24:23.83#ibcon#read 4, iclass 33, count 0 2006.173.20:24:23.83#ibcon#about to read 5, iclass 33, count 0 2006.173.20:24:23.83#ibcon#read 5, iclass 33, count 0 2006.173.20:24:23.83#ibcon#about to read 6, iclass 33, count 0 2006.173.20:24:23.83#ibcon#read 6, iclass 33, count 0 2006.173.20:24:23.83#ibcon#end of sib2, iclass 33, count 0 2006.173.20:24:23.83#ibcon#*after write, iclass 33, count 0 2006.173.20:24:23.83#ibcon#*before return 0, iclass 33, count 0 2006.173.20:24:23.83#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.20:24:23.83#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.173.20:24:23.83#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.20:24:23.83#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.20:24:23.83$vck44/vblo=4,679.99 2006.173.20:24:23.83#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.20:24:23.83#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.20:24:23.83#ibcon#ireg 17 cls_cnt 0 2006.173.20:24:23.83#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.20:24:23.83#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.20:24:23.83#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.20:24:23.83#ibcon#enter wrdev, iclass 35, count 0 2006.173.20:24:23.83#ibcon#first serial, iclass 35, count 0 2006.173.20:24:23.83#ibcon#enter sib2, iclass 35, count 0 2006.173.20:24:23.83#ibcon#flushed, iclass 35, count 0 2006.173.20:24:23.83#ibcon#about to write, iclass 35, count 0 2006.173.20:24:23.83#ibcon#wrote, iclass 35, count 0 2006.173.20:24:23.83#ibcon#about to read 3, iclass 35, count 0 2006.173.20:24:23.85#ibcon#read 3, iclass 35, count 0 2006.173.20:24:23.85#ibcon#about to read 4, iclass 35, count 0 2006.173.20:24:23.85#ibcon#read 4, iclass 35, count 0 2006.173.20:24:23.85#ibcon#about to read 5, iclass 35, count 0 2006.173.20:24:23.85#ibcon#read 5, iclass 35, count 0 2006.173.20:24:23.85#ibcon#about to read 6, iclass 35, count 0 2006.173.20:24:23.85#ibcon#read 6, iclass 35, count 0 2006.173.20:24:23.85#ibcon#end of sib2, iclass 35, count 0 2006.173.20:24:23.85#ibcon#*mode == 0, iclass 35, count 0 2006.173.20:24:23.85#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.20:24:23.85#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.20:24:23.85#ibcon#*before write, iclass 35, count 0 2006.173.20:24:23.85#ibcon#enter sib2, iclass 35, count 0 2006.173.20:24:23.85#ibcon#flushed, iclass 35, count 0 2006.173.20:24:23.85#ibcon#about to write, iclass 35, count 0 2006.173.20:24:23.85#ibcon#wrote, iclass 35, count 0 2006.173.20:24:23.85#ibcon#about to read 3, iclass 35, count 0 2006.173.20:24:23.89#ibcon#read 3, iclass 35, count 0 2006.173.20:24:23.91#ibcon#about to read 4, iclass 35, count 0 2006.173.20:24:23.91#ibcon#read 4, iclass 35, count 0 2006.173.20:24:23.91#ibcon#about to read 5, iclass 35, count 0 2006.173.20:24:23.91#ibcon#read 5, iclass 35, count 0 2006.173.20:24:23.91#ibcon#about to read 6, iclass 35, count 0 2006.173.20:24:23.91#ibcon#read 6, iclass 35, count 0 2006.173.20:24:23.91#ibcon#end of sib2, iclass 35, count 0 2006.173.20:24:23.92#ibcon#*after write, iclass 35, count 0 2006.173.20:24:23.92#ibcon#*before return 0, iclass 35, count 0 2006.173.20:24:23.92#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.20:24:23.92#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.20:24:23.92#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.20:24:23.92#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.20:24:23.92$vck44/vb=4,4 2006.173.20:24:23.92#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.173.20:24:23.92#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.173.20:24:23.92#ibcon#ireg 11 cls_cnt 2 2006.173.20:24:23.92#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.20:24:23.95#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.20:24:23.95#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.20:24:23.95#ibcon#enter wrdev, iclass 37, count 2 2006.173.20:24:23.95#ibcon#first serial, iclass 37, count 2 2006.173.20:24:23.95#ibcon#enter sib2, iclass 37, count 2 2006.173.20:24:23.95#ibcon#flushed, iclass 37, count 2 2006.173.20:24:23.95#ibcon#about to write, iclass 37, count 2 2006.173.20:24:23.95#ibcon#wrote, iclass 37, count 2 2006.173.20:24:23.95#ibcon#about to read 3, iclass 37, count 2 2006.173.20:24:23.97#ibcon#read 3, iclass 37, count 2 2006.173.20:24:23.97#ibcon#about to read 4, iclass 37, count 2 2006.173.20:24:23.97#ibcon#read 4, iclass 37, count 2 2006.173.20:24:23.97#ibcon#about to read 5, iclass 37, count 2 2006.173.20:24:23.97#ibcon#read 5, iclass 37, count 2 2006.173.20:24:23.97#ibcon#about to read 6, iclass 37, count 2 2006.173.20:24:23.97#ibcon#read 6, iclass 37, count 2 2006.173.20:24:23.97#ibcon#end of sib2, iclass 37, count 2 2006.173.20:24:23.97#ibcon#*mode == 0, iclass 37, count 2 2006.173.20:24:23.97#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.173.20:24:23.97#ibcon#[27=AT04-04\r\n] 2006.173.20:24:23.97#ibcon#*before write, iclass 37, count 2 2006.173.20:24:23.97#ibcon#enter sib2, iclass 37, count 2 2006.173.20:24:23.97#ibcon#flushed, iclass 37, count 2 2006.173.20:24:23.97#ibcon#about to write, iclass 37, count 2 2006.173.20:24:23.97#ibcon#wrote, iclass 37, count 2 2006.173.20:24:23.97#ibcon#about to read 3, iclass 37, count 2 2006.173.20:24:24.00#ibcon#read 3, iclass 37, count 2 2006.173.20:24:24.00#ibcon#about to read 4, iclass 37, count 2 2006.173.20:24:24.00#ibcon#read 4, iclass 37, count 2 2006.173.20:24:24.00#ibcon#about to read 5, iclass 37, count 2 2006.173.20:24:24.00#ibcon#read 5, iclass 37, count 2 2006.173.20:24:24.00#ibcon#about to read 6, iclass 37, count 2 2006.173.20:24:24.00#ibcon#read 6, iclass 37, count 2 2006.173.20:24:24.00#ibcon#end of sib2, iclass 37, count 2 2006.173.20:24:24.00#ibcon#*after write, iclass 37, count 2 2006.173.20:24:24.00#ibcon#*before return 0, iclass 37, count 2 2006.173.20:24:24.00#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.20:24:24.00#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.173.20:24:24.00#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.173.20:24:24.00#ibcon#ireg 7 cls_cnt 0 2006.173.20:24:24.00#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.20:24:24.12#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.20:24:24.12#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.20:24:24.12#ibcon#enter wrdev, iclass 37, count 0 2006.173.20:24:24.12#ibcon#first serial, iclass 37, count 0 2006.173.20:24:24.12#ibcon#enter sib2, iclass 37, count 0 2006.173.20:24:24.12#ibcon#flushed, iclass 37, count 0 2006.173.20:24:24.12#ibcon#about to write, iclass 37, count 0 2006.173.20:24:24.12#ibcon#wrote, iclass 37, count 0 2006.173.20:24:24.12#ibcon#about to read 3, iclass 37, count 0 2006.173.20:24:24.14#ibcon#read 3, iclass 37, count 0 2006.173.20:24:24.14#ibcon#about to read 4, iclass 37, count 0 2006.173.20:24:24.14#ibcon#read 4, iclass 37, count 0 2006.173.20:24:24.14#ibcon#about to read 5, iclass 37, count 0 2006.173.20:24:24.14#ibcon#read 5, iclass 37, count 0 2006.173.20:24:24.14#ibcon#about to read 6, iclass 37, count 0 2006.173.20:24:24.14#ibcon#read 6, iclass 37, count 0 2006.173.20:24:24.14#ibcon#end of sib2, iclass 37, count 0 2006.173.20:24:24.14#ibcon#*mode == 0, iclass 37, count 0 2006.173.20:24:24.14#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.20:24:24.14#ibcon#[27=USB\r\n] 2006.173.20:24:24.14#ibcon#*before write, iclass 37, count 0 2006.173.20:24:24.14#ibcon#enter sib2, iclass 37, count 0 2006.173.20:24:24.14#ibcon#flushed, iclass 37, count 0 2006.173.20:24:24.14#ibcon#about to write, iclass 37, count 0 2006.173.20:24:24.14#ibcon#wrote, iclass 37, count 0 2006.173.20:24:24.14#ibcon#about to read 3, iclass 37, count 0 2006.173.20:24:24.17#ibcon#read 3, iclass 37, count 0 2006.173.20:24:24.17#ibcon#about to read 4, iclass 37, count 0 2006.173.20:24:24.17#ibcon#read 4, iclass 37, count 0 2006.173.20:24:24.17#ibcon#about to read 5, iclass 37, count 0 2006.173.20:24:24.17#ibcon#read 5, iclass 37, count 0 2006.173.20:24:24.17#ibcon#about to read 6, iclass 37, count 0 2006.173.20:24:24.17#ibcon#read 6, iclass 37, count 0 2006.173.20:24:24.17#ibcon#end of sib2, iclass 37, count 0 2006.173.20:24:24.17#ibcon#*after write, iclass 37, count 0 2006.173.20:24:24.17#ibcon#*before return 0, iclass 37, count 0 2006.173.20:24:24.17#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.20:24:24.17#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.173.20:24:24.17#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.20:24:24.17#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.20:24:24.17$vck44/vblo=5,709.99 2006.173.20:24:24.17#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.20:24:24.17#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.20:24:24.17#ibcon#ireg 17 cls_cnt 0 2006.173.20:24:24.17#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.20:24:24.17#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.20:24:24.17#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.20:24:24.17#ibcon#enter wrdev, iclass 39, count 0 2006.173.20:24:24.17#ibcon#first serial, iclass 39, count 0 2006.173.20:24:24.17#ibcon#enter sib2, iclass 39, count 0 2006.173.20:24:24.17#ibcon#flushed, iclass 39, count 0 2006.173.20:24:24.17#ibcon#about to write, iclass 39, count 0 2006.173.20:24:24.17#ibcon#wrote, iclass 39, count 0 2006.173.20:24:24.17#ibcon#about to read 3, iclass 39, count 0 2006.173.20:24:24.19#ibcon#read 3, iclass 39, count 0 2006.173.20:24:24.19#ibcon#about to read 4, iclass 39, count 0 2006.173.20:24:24.19#ibcon#read 4, iclass 39, count 0 2006.173.20:24:24.19#ibcon#about to read 5, iclass 39, count 0 2006.173.20:24:24.19#ibcon#read 5, iclass 39, count 0 2006.173.20:24:24.19#ibcon#about to read 6, iclass 39, count 0 2006.173.20:24:24.19#ibcon#read 6, iclass 39, count 0 2006.173.20:24:24.19#ibcon#end of sib2, iclass 39, count 0 2006.173.20:24:24.19#ibcon#*mode == 0, iclass 39, count 0 2006.173.20:24:24.19#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.20:24:24.19#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.20:24:24.19#ibcon#*before write, iclass 39, count 0 2006.173.20:24:24.19#ibcon#enter sib2, iclass 39, count 0 2006.173.20:24:24.19#ibcon#flushed, iclass 39, count 0 2006.173.20:24:24.19#ibcon#about to write, iclass 39, count 0 2006.173.20:24:24.19#ibcon#wrote, iclass 39, count 0 2006.173.20:24:24.19#ibcon#about to read 3, iclass 39, count 0 2006.173.20:24:24.23#ibcon#read 3, iclass 39, count 0 2006.173.20:24:24.23#ibcon#about to read 4, iclass 39, count 0 2006.173.20:24:24.23#ibcon#read 4, iclass 39, count 0 2006.173.20:24:24.23#ibcon#about to read 5, iclass 39, count 0 2006.173.20:24:24.23#ibcon#read 5, iclass 39, count 0 2006.173.20:24:24.23#ibcon#about to read 6, iclass 39, count 0 2006.173.20:24:24.23#ibcon#read 6, iclass 39, count 0 2006.173.20:24:24.23#ibcon#end of sib2, iclass 39, count 0 2006.173.20:24:24.23#ibcon#*after write, iclass 39, count 0 2006.173.20:24:24.23#ibcon#*before return 0, iclass 39, count 0 2006.173.20:24:24.23#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.20:24:24.23#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.20:24:24.23#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.20:24:24.23#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.20:24:24.23$vck44/vb=5,4 2006.173.20:24:24.23#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.20:24:24.23#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.20:24:24.23#ibcon#ireg 11 cls_cnt 2 2006.173.20:24:24.23#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.20:24:24.29#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.20:24:24.29#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.20:24:24.29#ibcon#enter wrdev, iclass 3, count 2 2006.173.20:24:24.29#ibcon#first serial, iclass 3, count 2 2006.173.20:24:24.29#ibcon#enter sib2, iclass 3, count 2 2006.173.20:24:24.29#ibcon#flushed, iclass 3, count 2 2006.173.20:24:24.29#ibcon#about to write, iclass 3, count 2 2006.173.20:24:24.29#ibcon#wrote, iclass 3, count 2 2006.173.20:24:24.29#ibcon#about to read 3, iclass 3, count 2 2006.173.20:24:24.31#ibcon#read 3, iclass 3, count 2 2006.173.20:24:24.31#ibcon#about to read 4, iclass 3, count 2 2006.173.20:24:24.31#ibcon#read 4, iclass 3, count 2 2006.173.20:24:24.31#ibcon#about to read 5, iclass 3, count 2 2006.173.20:24:24.31#ibcon#read 5, iclass 3, count 2 2006.173.20:24:24.31#ibcon#about to read 6, iclass 3, count 2 2006.173.20:24:24.31#ibcon#read 6, iclass 3, count 2 2006.173.20:24:24.31#ibcon#end of sib2, iclass 3, count 2 2006.173.20:24:24.31#ibcon#*mode == 0, iclass 3, count 2 2006.173.20:24:24.31#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.20:24:24.31#ibcon#[27=AT05-04\r\n] 2006.173.20:24:24.31#ibcon#*before write, iclass 3, count 2 2006.173.20:24:24.31#ibcon#enter sib2, iclass 3, count 2 2006.173.20:24:24.31#ibcon#flushed, iclass 3, count 2 2006.173.20:24:24.31#ibcon#about to write, iclass 3, count 2 2006.173.20:24:24.31#ibcon#wrote, iclass 3, count 2 2006.173.20:24:24.31#ibcon#about to read 3, iclass 3, count 2 2006.173.20:24:24.34#ibcon#read 3, iclass 3, count 2 2006.173.20:24:24.34#ibcon#about to read 4, iclass 3, count 2 2006.173.20:24:24.34#ibcon#read 4, iclass 3, count 2 2006.173.20:24:24.34#ibcon#about to read 5, iclass 3, count 2 2006.173.20:24:24.34#ibcon#read 5, iclass 3, count 2 2006.173.20:24:24.34#ibcon#about to read 6, iclass 3, count 2 2006.173.20:24:24.34#ibcon#read 6, iclass 3, count 2 2006.173.20:24:24.34#ibcon#end of sib2, iclass 3, count 2 2006.173.20:24:24.34#ibcon#*after write, iclass 3, count 2 2006.173.20:24:24.34#ibcon#*before return 0, iclass 3, count 2 2006.173.20:24:24.34#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.20:24:24.34#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.20:24:24.34#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.20:24:24.34#ibcon#ireg 7 cls_cnt 0 2006.173.20:24:24.34#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.20:24:24.46#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.20:24:24.46#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.20:24:24.46#ibcon#enter wrdev, iclass 3, count 0 2006.173.20:24:24.46#ibcon#first serial, iclass 3, count 0 2006.173.20:24:24.46#ibcon#enter sib2, iclass 3, count 0 2006.173.20:24:24.46#ibcon#flushed, iclass 3, count 0 2006.173.20:24:24.46#ibcon#about to write, iclass 3, count 0 2006.173.20:24:24.46#ibcon#wrote, iclass 3, count 0 2006.173.20:24:24.46#ibcon#about to read 3, iclass 3, count 0 2006.173.20:24:24.48#ibcon#read 3, iclass 3, count 0 2006.173.20:24:24.48#ibcon#about to read 4, iclass 3, count 0 2006.173.20:24:24.48#ibcon#read 4, iclass 3, count 0 2006.173.20:24:24.48#ibcon#about to read 5, iclass 3, count 0 2006.173.20:24:24.48#ibcon#read 5, iclass 3, count 0 2006.173.20:24:24.48#ibcon#about to read 6, iclass 3, count 0 2006.173.20:24:24.48#ibcon#read 6, iclass 3, count 0 2006.173.20:24:24.48#ibcon#end of sib2, iclass 3, count 0 2006.173.20:24:24.48#ibcon#*mode == 0, iclass 3, count 0 2006.173.20:24:24.48#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.20:24:24.48#ibcon#[27=USB\r\n] 2006.173.20:24:24.48#ibcon#*before write, iclass 3, count 0 2006.173.20:24:24.48#ibcon#enter sib2, iclass 3, count 0 2006.173.20:24:24.48#ibcon#flushed, iclass 3, count 0 2006.173.20:24:24.48#ibcon#about to write, iclass 3, count 0 2006.173.20:24:24.48#ibcon#wrote, iclass 3, count 0 2006.173.20:24:24.48#ibcon#about to read 3, iclass 3, count 0 2006.173.20:24:24.51#ibcon#read 3, iclass 3, count 0 2006.173.20:24:24.51#ibcon#about to read 4, iclass 3, count 0 2006.173.20:24:24.51#ibcon#read 4, iclass 3, count 0 2006.173.20:24:24.51#ibcon#about to read 5, iclass 3, count 0 2006.173.20:24:24.51#ibcon#read 5, iclass 3, count 0 2006.173.20:24:24.51#ibcon#about to read 6, iclass 3, count 0 2006.173.20:24:24.51#ibcon#read 6, iclass 3, count 0 2006.173.20:24:24.51#ibcon#end of sib2, iclass 3, count 0 2006.173.20:24:24.51#ibcon#*after write, iclass 3, count 0 2006.173.20:24:24.51#ibcon#*before return 0, iclass 3, count 0 2006.173.20:24:24.51#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.20:24:24.51#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.20:24:24.51#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.20:24:24.51#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.20:24:24.51$vck44/vblo=6,719.99 2006.173.20:24:24.51#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.20:24:24.51#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.20:24:24.51#ibcon#ireg 17 cls_cnt 0 2006.173.20:24:24.51#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.20:24:24.51#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.20:24:24.51#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.20:24:24.51#ibcon#enter wrdev, iclass 5, count 0 2006.173.20:24:24.51#ibcon#first serial, iclass 5, count 0 2006.173.20:24:24.51#ibcon#enter sib2, iclass 5, count 0 2006.173.20:24:24.51#ibcon#flushed, iclass 5, count 0 2006.173.20:24:24.51#ibcon#about to write, iclass 5, count 0 2006.173.20:24:24.51#ibcon#wrote, iclass 5, count 0 2006.173.20:24:24.51#ibcon#about to read 3, iclass 5, count 0 2006.173.20:24:24.53#ibcon#read 3, iclass 5, count 0 2006.173.20:24:24.53#ibcon#about to read 4, iclass 5, count 0 2006.173.20:24:24.53#ibcon#read 4, iclass 5, count 0 2006.173.20:24:24.53#ibcon#about to read 5, iclass 5, count 0 2006.173.20:24:24.53#ibcon#read 5, iclass 5, count 0 2006.173.20:24:24.53#ibcon#about to read 6, iclass 5, count 0 2006.173.20:24:24.53#ibcon#read 6, iclass 5, count 0 2006.173.20:24:24.53#ibcon#end of sib2, iclass 5, count 0 2006.173.20:24:24.53#ibcon#*mode == 0, iclass 5, count 0 2006.173.20:24:24.53#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.20:24:24.53#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.20:24:24.53#ibcon#*before write, iclass 5, count 0 2006.173.20:24:24.53#ibcon#enter sib2, iclass 5, count 0 2006.173.20:24:24.53#ibcon#flushed, iclass 5, count 0 2006.173.20:24:24.53#ibcon#about to write, iclass 5, count 0 2006.173.20:24:24.53#ibcon#wrote, iclass 5, count 0 2006.173.20:24:24.53#ibcon#about to read 3, iclass 5, count 0 2006.173.20:24:24.57#ibcon#read 3, iclass 5, count 0 2006.173.20:24:24.57#ibcon#about to read 4, iclass 5, count 0 2006.173.20:24:24.57#ibcon#read 4, iclass 5, count 0 2006.173.20:24:24.57#ibcon#about to read 5, iclass 5, count 0 2006.173.20:24:24.57#ibcon#read 5, iclass 5, count 0 2006.173.20:24:24.57#ibcon#about to read 6, iclass 5, count 0 2006.173.20:24:24.57#ibcon#read 6, iclass 5, count 0 2006.173.20:24:24.57#ibcon#end of sib2, iclass 5, count 0 2006.173.20:24:24.57#ibcon#*after write, iclass 5, count 0 2006.173.20:24:24.57#ibcon#*before return 0, iclass 5, count 0 2006.173.20:24:24.57#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.20:24:24.57#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.20:24:24.57#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.20:24:24.57#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.20:24:24.57$vck44/vb=6,4 2006.173.20:24:24.57#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.173.20:24:24.57#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.173.20:24:24.57#ibcon#ireg 11 cls_cnt 2 2006.173.20:24:24.57#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.20:24:24.63#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.20:24:24.63#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.20:24:24.63#ibcon#enter wrdev, iclass 7, count 2 2006.173.20:24:24.63#ibcon#first serial, iclass 7, count 2 2006.173.20:24:24.63#ibcon#enter sib2, iclass 7, count 2 2006.173.20:24:24.63#ibcon#flushed, iclass 7, count 2 2006.173.20:24:24.63#ibcon#about to write, iclass 7, count 2 2006.173.20:24:24.63#ibcon#wrote, iclass 7, count 2 2006.173.20:24:24.63#ibcon#about to read 3, iclass 7, count 2 2006.173.20:24:24.65#ibcon#read 3, iclass 7, count 2 2006.173.20:24:24.65#ibcon#about to read 4, iclass 7, count 2 2006.173.20:24:24.65#ibcon#read 4, iclass 7, count 2 2006.173.20:24:24.65#ibcon#about to read 5, iclass 7, count 2 2006.173.20:24:24.65#ibcon#read 5, iclass 7, count 2 2006.173.20:24:24.65#ibcon#about to read 6, iclass 7, count 2 2006.173.20:24:24.65#ibcon#read 6, iclass 7, count 2 2006.173.20:24:24.65#ibcon#end of sib2, iclass 7, count 2 2006.173.20:24:24.65#ibcon#*mode == 0, iclass 7, count 2 2006.173.20:24:24.65#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.173.20:24:24.65#ibcon#[27=AT06-04\r\n] 2006.173.20:24:24.65#ibcon#*before write, iclass 7, count 2 2006.173.20:24:24.65#ibcon#enter sib2, iclass 7, count 2 2006.173.20:24:24.65#ibcon#flushed, iclass 7, count 2 2006.173.20:24:24.65#ibcon#about to write, iclass 7, count 2 2006.173.20:24:24.65#ibcon#wrote, iclass 7, count 2 2006.173.20:24:24.65#ibcon#about to read 3, iclass 7, count 2 2006.173.20:24:24.68#ibcon#read 3, iclass 7, count 2 2006.173.20:24:24.68#ibcon#about to read 4, iclass 7, count 2 2006.173.20:24:24.68#ibcon#read 4, iclass 7, count 2 2006.173.20:24:24.68#ibcon#about to read 5, iclass 7, count 2 2006.173.20:24:24.68#ibcon#read 5, iclass 7, count 2 2006.173.20:24:24.68#ibcon#about to read 6, iclass 7, count 2 2006.173.20:24:24.68#ibcon#read 6, iclass 7, count 2 2006.173.20:24:24.68#ibcon#end of sib2, iclass 7, count 2 2006.173.20:24:24.68#ibcon#*after write, iclass 7, count 2 2006.173.20:24:24.68#ibcon#*before return 0, iclass 7, count 2 2006.173.20:24:24.68#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.20:24:24.68#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.173.20:24:24.68#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.173.20:24:24.68#ibcon#ireg 7 cls_cnt 0 2006.173.20:24:24.68#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.20:24:24.80#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.20:24:24.80#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.20:24:24.80#ibcon#enter wrdev, iclass 7, count 0 2006.173.20:24:24.80#ibcon#first serial, iclass 7, count 0 2006.173.20:24:24.80#ibcon#enter sib2, iclass 7, count 0 2006.173.20:24:24.80#ibcon#flushed, iclass 7, count 0 2006.173.20:24:24.80#ibcon#about to write, iclass 7, count 0 2006.173.20:24:24.80#ibcon#wrote, iclass 7, count 0 2006.173.20:24:24.80#ibcon#about to read 3, iclass 7, count 0 2006.173.20:24:24.82#ibcon#read 3, iclass 7, count 0 2006.173.20:24:24.82#ibcon#about to read 4, iclass 7, count 0 2006.173.20:24:24.82#ibcon#read 4, iclass 7, count 0 2006.173.20:24:24.82#ibcon#about to read 5, iclass 7, count 0 2006.173.20:24:24.82#ibcon#read 5, iclass 7, count 0 2006.173.20:24:24.82#ibcon#about to read 6, iclass 7, count 0 2006.173.20:24:24.82#ibcon#read 6, iclass 7, count 0 2006.173.20:24:24.82#ibcon#end of sib2, iclass 7, count 0 2006.173.20:24:24.82#ibcon#*mode == 0, iclass 7, count 0 2006.173.20:24:24.82#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.20:24:24.82#ibcon#[27=USB\r\n] 2006.173.20:24:24.82#ibcon#*before write, iclass 7, count 0 2006.173.20:24:24.82#ibcon#enter sib2, iclass 7, count 0 2006.173.20:24:24.82#ibcon#flushed, iclass 7, count 0 2006.173.20:24:24.82#ibcon#about to write, iclass 7, count 0 2006.173.20:24:24.82#ibcon#wrote, iclass 7, count 0 2006.173.20:24:24.82#ibcon#about to read 3, iclass 7, count 0 2006.173.20:24:24.85#ibcon#read 3, iclass 7, count 0 2006.173.20:24:24.85#ibcon#about to read 4, iclass 7, count 0 2006.173.20:24:24.85#ibcon#read 4, iclass 7, count 0 2006.173.20:24:24.85#ibcon#about to read 5, iclass 7, count 0 2006.173.20:24:24.85#ibcon#read 5, iclass 7, count 0 2006.173.20:24:24.85#ibcon#about to read 6, iclass 7, count 0 2006.173.20:24:24.85#ibcon#read 6, iclass 7, count 0 2006.173.20:24:24.85#ibcon#end of sib2, iclass 7, count 0 2006.173.20:24:24.85#ibcon#*after write, iclass 7, count 0 2006.173.20:24:24.85#ibcon#*before return 0, iclass 7, count 0 2006.173.20:24:24.85#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.20:24:24.85#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.173.20:24:24.85#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.20:24:24.85#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.20:24:24.85$vck44/vblo=7,734.99 2006.173.20:24:24.85#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.20:24:24.85#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.20:24:24.85#ibcon#ireg 17 cls_cnt 0 2006.173.20:24:24.85#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.20:24:24.85#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.20:24:24.85#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.20:24:24.85#ibcon#enter wrdev, iclass 11, count 0 2006.173.20:24:24.85#ibcon#first serial, iclass 11, count 0 2006.173.20:24:24.85#ibcon#enter sib2, iclass 11, count 0 2006.173.20:24:24.85#ibcon#flushed, iclass 11, count 0 2006.173.20:24:24.85#ibcon#about to write, iclass 11, count 0 2006.173.20:24:24.85#ibcon#wrote, iclass 11, count 0 2006.173.20:24:24.85#ibcon#about to read 3, iclass 11, count 0 2006.173.20:24:24.87#ibcon#read 3, iclass 11, count 0 2006.173.20:24:24.87#ibcon#about to read 4, iclass 11, count 0 2006.173.20:24:24.87#ibcon#read 4, iclass 11, count 0 2006.173.20:24:24.87#ibcon#about to read 5, iclass 11, count 0 2006.173.20:24:24.87#ibcon#read 5, iclass 11, count 0 2006.173.20:24:24.87#ibcon#about to read 6, iclass 11, count 0 2006.173.20:24:24.87#ibcon#read 6, iclass 11, count 0 2006.173.20:24:24.87#ibcon#end of sib2, iclass 11, count 0 2006.173.20:24:24.87#ibcon#*mode == 0, iclass 11, count 0 2006.173.20:24:24.87#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.20:24:24.87#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.20:24:24.87#ibcon#*before write, iclass 11, count 0 2006.173.20:24:24.87#ibcon#enter sib2, iclass 11, count 0 2006.173.20:24:24.87#ibcon#flushed, iclass 11, count 0 2006.173.20:24:24.87#ibcon#about to write, iclass 11, count 0 2006.173.20:24:24.87#ibcon#wrote, iclass 11, count 0 2006.173.20:24:24.87#ibcon#about to read 3, iclass 11, count 0 2006.173.20:24:24.91#ibcon#read 3, iclass 11, count 0 2006.173.20:24:24.91#ibcon#about to read 4, iclass 11, count 0 2006.173.20:24:24.91#ibcon#read 4, iclass 11, count 0 2006.173.20:24:24.91#ibcon#about to read 5, iclass 11, count 0 2006.173.20:24:24.91#ibcon#read 5, iclass 11, count 0 2006.173.20:24:24.91#ibcon#about to read 6, iclass 11, count 0 2006.173.20:24:24.91#ibcon#read 6, iclass 11, count 0 2006.173.20:24:24.91#ibcon#end of sib2, iclass 11, count 0 2006.173.20:24:24.91#ibcon#*after write, iclass 11, count 0 2006.173.20:24:24.91#ibcon#*before return 0, iclass 11, count 0 2006.173.20:24:24.91#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.20:24:24.91#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.20:24:24.91#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.20:24:24.91#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.20:24:24.91$vck44/vb=7,4 2006.173.20:24:24.91#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.173.20:24:24.91#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.173.20:24:24.91#ibcon#ireg 11 cls_cnt 2 2006.173.20:24:24.91#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.20:24:24.97#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.20:24:24.97#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.20:24:24.97#ibcon#enter wrdev, iclass 13, count 2 2006.173.20:24:24.97#ibcon#first serial, iclass 13, count 2 2006.173.20:24:24.97#ibcon#enter sib2, iclass 13, count 2 2006.173.20:24:24.97#ibcon#flushed, iclass 13, count 2 2006.173.20:24:24.97#ibcon#about to write, iclass 13, count 2 2006.173.20:24:24.97#ibcon#wrote, iclass 13, count 2 2006.173.20:24:24.97#ibcon#about to read 3, iclass 13, count 2 2006.173.20:24:24.99#ibcon#read 3, iclass 13, count 2 2006.173.20:24:24.99#ibcon#about to read 4, iclass 13, count 2 2006.173.20:24:24.99#ibcon#read 4, iclass 13, count 2 2006.173.20:24:24.99#ibcon#about to read 5, iclass 13, count 2 2006.173.20:24:24.99#ibcon#read 5, iclass 13, count 2 2006.173.20:24:24.99#ibcon#about to read 6, iclass 13, count 2 2006.173.20:24:24.99#ibcon#read 6, iclass 13, count 2 2006.173.20:24:24.99#ibcon#end of sib2, iclass 13, count 2 2006.173.20:24:24.99#ibcon#*mode == 0, iclass 13, count 2 2006.173.20:24:24.99#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.173.20:24:24.99#ibcon#[27=AT07-04\r\n] 2006.173.20:24:24.99#ibcon#*before write, iclass 13, count 2 2006.173.20:24:24.99#ibcon#enter sib2, iclass 13, count 2 2006.173.20:24:24.99#ibcon#flushed, iclass 13, count 2 2006.173.20:24:24.99#ibcon#about to write, iclass 13, count 2 2006.173.20:24:24.99#ibcon#wrote, iclass 13, count 2 2006.173.20:24:24.99#ibcon#about to read 3, iclass 13, count 2 2006.173.20:24:25.02#ibcon#read 3, iclass 13, count 2 2006.173.20:24:25.02#ibcon#about to read 4, iclass 13, count 2 2006.173.20:24:25.02#ibcon#read 4, iclass 13, count 2 2006.173.20:24:25.02#ibcon#about to read 5, iclass 13, count 2 2006.173.20:24:25.02#ibcon#read 5, iclass 13, count 2 2006.173.20:24:25.02#ibcon#about to read 6, iclass 13, count 2 2006.173.20:24:25.02#ibcon#read 6, iclass 13, count 2 2006.173.20:24:25.02#ibcon#end of sib2, iclass 13, count 2 2006.173.20:24:25.02#ibcon#*after write, iclass 13, count 2 2006.173.20:24:25.02#ibcon#*before return 0, iclass 13, count 2 2006.173.20:24:25.02#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.20:24:25.02#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.173.20:24:25.02#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.173.20:24:25.02#ibcon#ireg 7 cls_cnt 0 2006.173.20:24:25.02#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.20:24:25.14#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.20:24:25.14#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.20:24:25.14#ibcon#enter wrdev, iclass 13, count 0 2006.173.20:24:25.14#ibcon#first serial, iclass 13, count 0 2006.173.20:24:25.14#ibcon#enter sib2, iclass 13, count 0 2006.173.20:24:25.14#ibcon#flushed, iclass 13, count 0 2006.173.20:24:25.14#ibcon#about to write, iclass 13, count 0 2006.173.20:24:25.14#ibcon#wrote, iclass 13, count 0 2006.173.20:24:25.14#ibcon#about to read 3, iclass 13, count 0 2006.173.20:24:25.16#ibcon#read 3, iclass 13, count 0 2006.173.20:24:25.16#ibcon#about to read 4, iclass 13, count 0 2006.173.20:24:25.16#ibcon#read 4, iclass 13, count 0 2006.173.20:24:25.16#ibcon#about to read 5, iclass 13, count 0 2006.173.20:24:25.16#ibcon#read 5, iclass 13, count 0 2006.173.20:24:25.16#ibcon#about to read 6, iclass 13, count 0 2006.173.20:24:25.16#ibcon#read 6, iclass 13, count 0 2006.173.20:24:25.16#ibcon#end of sib2, iclass 13, count 0 2006.173.20:24:25.16#ibcon#*mode == 0, iclass 13, count 0 2006.173.20:24:25.16#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.20:24:25.16#ibcon#[27=USB\r\n] 2006.173.20:24:25.16#ibcon#*before write, iclass 13, count 0 2006.173.20:24:25.16#ibcon#enter sib2, iclass 13, count 0 2006.173.20:24:25.16#ibcon#flushed, iclass 13, count 0 2006.173.20:24:25.16#ibcon#about to write, iclass 13, count 0 2006.173.20:24:25.16#ibcon#wrote, iclass 13, count 0 2006.173.20:24:25.16#ibcon#about to read 3, iclass 13, count 0 2006.173.20:24:25.19#ibcon#read 3, iclass 13, count 0 2006.173.20:24:25.19#ibcon#about to read 4, iclass 13, count 0 2006.173.20:24:25.19#ibcon#read 4, iclass 13, count 0 2006.173.20:24:25.19#ibcon#about to read 5, iclass 13, count 0 2006.173.20:24:25.19#ibcon#read 5, iclass 13, count 0 2006.173.20:24:25.19#ibcon#about to read 6, iclass 13, count 0 2006.173.20:24:25.19#ibcon#read 6, iclass 13, count 0 2006.173.20:24:25.19#ibcon#end of sib2, iclass 13, count 0 2006.173.20:24:25.19#ibcon#*after write, iclass 13, count 0 2006.173.20:24:25.19#ibcon#*before return 0, iclass 13, count 0 2006.173.20:24:25.19#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.20:24:25.19#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.173.20:24:25.19#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.20:24:25.19#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.20:24:25.19$vck44/vblo=8,744.99 2006.173.20:24:25.19#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.20:24:25.19#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.20:24:25.19#ibcon#ireg 17 cls_cnt 0 2006.173.20:24:25.19#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.20:24:25.19#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.20:24:25.19#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.20:24:25.19#ibcon#enter wrdev, iclass 15, count 0 2006.173.20:24:25.19#ibcon#first serial, iclass 15, count 0 2006.173.20:24:25.19#ibcon#enter sib2, iclass 15, count 0 2006.173.20:24:25.19#ibcon#flushed, iclass 15, count 0 2006.173.20:24:25.19#ibcon#about to write, iclass 15, count 0 2006.173.20:24:25.19#ibcon#wrote, iclass 15, count 0 2006.173.20:24:25.19#ibcon#about to read 3, iclass 15, count 0 2006.173.20:24:25.21#ibcon#read 3, iclass 15, count 0 2006.173.20:24:25.21#ibcon#about to read 4, iclass 15, count 0 2006.173.20:24:25.21#ibcon#read 4, iclass 15, count 0 2006.173.20:24:25.21#ibcon#about to read 5, iclass 15, count 0 2006.173.20:24:25.21#ibcon#read 5, iclass 15, count 0 2006.173.20:24:25.21#ibcon#about to read 6, iclass 15, count 0 2006.173.20:24:25.21#ibcon#read 6, iclass 15, count 0 2006.173.20:24:25.21#ibcon#end of sib2, iclass 15, count 0 2006.173.20:24:25.21#ibcon#*mode == 0, iclass 15, count 0 2006.173.20:24:25.21#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.20:24:25.21#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.20:24:25.21#ibcon#*before write, iclass 15, count 0 2006.173.20:24:25.21#ibcon#enter sib2, iclass 15, count 0 2006.173.20:24:25.21#ibcon#flushed, iclass 15, count 0 2006.173.20:24:25.21#ibcon#about to write, iclass 15, count 0 2006.173.20:24:25.21#ibcon#wrote, iclass 15, count 0 2006.173.20:24:25.21#ibcon#about to read 3, iclass 15, count 0 2006.173.20:24:25.25#ibcon#read 3, iclass 15, count 0 2006.173.20:24:25.25#ibcon#about to read 4, iclass 15, count 0 2006.173.20:24:25.25#ibcon#read 4, iclass 15, count 0 2006.173.20:24:25.25#ibcon#about to read 5, iclass 15, count 0 2006.173.20:24:25.25#ibcon#read 5, iclass 15, count 0 2006.173.20:24:25.25#ibcon#about to read 6, iclass 15, count 0 2006.173.20:24:25.25#ibcon#read 6, iclass 15, count 0 2006.173.20:24:25.25#ibcon#end of sib2, iclass 15, count 0 2006.173.20:24:25.25#ibcon#*after write, iclass 15, count 0 2006.173.20:24:25.25#ibcon#*before return 0, iclass 15, count 0 2006.173.20:24:25.25#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.20:24:25.25#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.20:24:25.25#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.20:24:25.25#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.20:24:25.25$vck44/vb=8,4 2006.173.20:24:25.25#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.20:24:25.25#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.20:24:25.25#ibcon#ireg 11 cls_cnt 2 2006.173.20:24:25.25#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.20:24:25.31#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.20:24:25.31#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.20:24:25.31#ibcon#enter wrdev, iclass 17, count 2 2006.173.20:24:25.31#ibcon#first serial, iclass 17, count 2 2006.173.20:24:25.31#ibcon#enter sib2, iclass 17, count 2 2006.173.20:24:25.31#ibcon#flushed, iclass 17, count 2 2006.173.20:24:25.31#ibcon#about to write, iclass 17, count 2 2006.173.20:24:25.31#ibcon#wrote, iclass 17, count 2 2006.173.20:24:25.31#ibcon#about to read 3, iclass 17, count 2 2006.173.20:24:25.33#ibcon#read 3, iclass 17, count 2 2006.173.20:24:25.33#ibcon#about to read 4, iclass 17, count 2 2006.173.20:24:25.33#ibcon#read 4, iclass 17, count 2 2006.173.20:24:25.33#ibcon#about to read 5, iclass 17, count 2 2006.173.20:24:25.33#ibcon#read 5, iclass 17, count 2 2006.173.20:24:25.33#ibcon#about to read 6, iclass 17, count 2 2006.173.20:24:25.33#ibcon#read 6, iclass 17, count 2 2006.173.20:24:25.33#ibcon#end of sib2, iclass 17, count 2 2006.173.20:24:25.33#ibcon#*mode == 0, iclass 17, count 2 2006.173.20:24:25.33#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.20:24:25.33#ibcon#[27=AT08-04\r\n] 2006.173.20:24:25.33#ibcon#*before write, iclass 17, count 2 2006.173.20:24:25.33#ibcon#enter sib2, iclass 17, count 2 2006.173.20:24:25.33#ibcon#flushed, iclass 17, count 2 2006.173.20:24:25.33#ibcon#about to write, iclass 17, count 2 2006.173.20:24:25.33#ibcon#wrote, iclass 17, count 2 2006.173.20:24:25.33#ibcon#about to read 3, iclass 17, count 2 2006.173.20:24:25.36#ibcon#read 3, iclass 17, count 2 2006.173.20:24:25.36#ibcon#about to read 4, iclass 17, count 2 2006.173.20:24:25.36#ibcon#read 4, iclass 17, count 2 2006.173.20:24:25.36#ibcon#about to read 5, iclass 17, count 2 2006.173.20:24:25.36#ibcon#read 5, iclass 17, count 2 2006.173.20:24:25.36#ibcon#about to read 6, iclass 17, count 2 2006.173.20:24:25.36#ibcon#read 6, iclass 17, count 2 2006.173.20:24:25.36#ibcon#end of sib2, iclass 17, count 2 2006.173.20:24:25.36#ibcon#*after write, iclass 17, count 2 2006.173.20:24:25.36#ibcon#*before return 0, iclass 17, count 2 2006.173.20:24:25.36#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.20:24:25.36#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.20:24:25.36#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.20:24:25.36#ibcon#ireg 7 cls_cnt 0 2006.173.20:24:25.36#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.20:24:25.48#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.20:24:25.48#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.20:24:25.48#ibcon#enter wrdev, iclass 17, count 0 2006.173.20:24:25.48#ibcon#first serial, iclass 17, count 0 2006.173.20:24:25.48#ibcon#enter sib2, iclass 17, count 0 2006.173.20:24:25.48#ibcon#flushed, iclass 17, count 0 2006.173.20:24:25.48#ibcon#about to write, iclass 17, count 0 2006.173.20:24:25.48#ibcon#wrote, iclass 17, count 0 2006.173.20:24:25.48#ibcon#about to read 3, iclass 17, count 0 2006.173.20:24:25.50#ibcon#read 3, iclass 17, count 0 2006.173.20:24:25.50#ibcon#about to read 4, iclass 17, count 0 2006.173.20:24:25.50#ibcon#read 4, iclass 17, count 0 2006.173.20:24:25.50#ibcon#about to read 5, iclass 17, count 0 2006.173.20:24:25.50#ibcon#read 5, iclass 17, count 0 2006.173.20:24:25.50#ibcon#about to read 6, iclass 17, count 0 2006.173.20:24:25.50#ibcon#read 6, iclass 17, count 0 2006.173.20:24:25.50#ibcon#end of sib2, iclass 17, count 0 2006.173.20:24:25.50#ibcon#*mode == 0, iclass 17, count 0 2006.173.20:24:25.50#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.20:24:25.50#ibcon#[27=USB\r\n] 2006.173.20:24:25.50#ibcon#*before write, iclass 17, count 0 2006.173.20:24:25.50#ibcon#enter sib2, iclass 17, count 0 2006.173.20:24:25.50#ibcon#flushed, iclass 17, count 0 2006.173.20:24:25.50#ibcon#about to write, iclass 17, count 0 2006.173.20:24:25.50#ibcon#wrote, iclass 17, count 0 2006.173.20:24:25.50#ibcon#about to read 3, iclass 17, count 0 2006.173.20:24:25.53#ibcon#read 3, iclass 17, count 0 2006.173.20:24:25.53#ibcon#about to read 4, iclass 17, count 0 2006.173.20:24:25.53#ibcon#read 4, iclass 17, count 0 2006.173.20:24:25.53#ibcon#about to read 5, iclass 17, count 0 2006.173.20:24:25.53#ibcon#read 5, iclass 17, count 0 2006.173.20:24:25.53#ibcon#about to read 6, iclass 17, count 0 2006.173.20:24:25.53#ibcon#read 6, iclass 17, count 0 2006.173.20:24:25.53#ibcon#end of sib2, iclass 17, count 0 2006.173.20:24:25.53#ibcon#*after write, iclass 17, count 0 2006.173.20:24:25.53#ibcon#*before return 0, iclass 17, count 0 2006.173.20:24:25.53#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.20:24:25.53#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.20:24:25.53#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.20:24:25.53#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.20:24:25.53$vck44/vabw=wide 2006.173.20:24:25.53#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.20:24:25.53#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.20:24:25.53#ibcon#ireg 8 cls_cnt 0 2006.173.20:24:25.53#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.20:24:25.53#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.20:24:25.53#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.20:24:25.53#ibcon#enter wrdev, iclass 19, count 0 2006.173.20:24:25.53#ibcon#first serial, iclass 19, count 0 2006.173.20:24:25.53#ibcon#enter sib2, iclass 19, count 0 2006.173.20:24:25.53#ibcon#flushed, iclass 19, count 0 2006.173.20:24:25.53#ibcon#about to write, iclass 19, count 0 2006.173.20:24:25.53#ibcon#wrote, iclass 19, count 0 2006.173.20:24:25.53#ibcon#about to read 3, iclass 19, count 0 2006.173.20:24:25.55#ibcon#read 3, iclass 19, count 0 2006.173.20:24:25.55#ibcon#about to read 4, iclass 19, count 0 2006.173.20:24:25.55#ibcon#read 4, iclass 19, count 0 2006.173.20:24:25.55#ibcon#about to read 5, iclass 19, count 0 2006.173.20:24:25.55#ibcon#read 5, iclass 19, count 0 2006.173.20:24:25.55#ibcon#about to read 6, iclass 19, count 0 2006.173.20:24:25.55#ibcon#read 6, iclass 19, count 0 2006.173.20:24:25.55#ibcon#end of sib2, iclass 19, count 0 2006.173.20:24:25.55#ibcon#*mode == 0, iclass 19, count 0 2006.173.20:24:25.55#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.20:24:25.55#ibcon#[25=BW32\r\n] 2006.173.20:24:25.55#ibcon#*before write, iclass 19, count 0 2006.173.20:24:25.55#ibcon#enter sib2, iclass 19, count 0 2006.173.20:24:25.55#ibcon#flushed, iclass 19, count 0 2006.173.20:24:25.55#ibcon#about to write, iclass 19, count 0 2006.173.20:24:25.55#ibcon#wrote, iclass 19, count 0 2006.173.20:24:25.55#ibcon#about to read 3, iclass 19, count 0 2006.173.20:24:25.58#ibcon#read 3, iclass 19, count 0 2006.173.20:24:25.58#ibcon#about to read 4, iclass 19, count 0 2006.173.20:24:25.58#ibcon#read 4, iclass 19, count 0 2006.173.20:24:25.58#ibcon#about to read 5, iclass 19, count 0 2006.173.20:24:25.58#ibcon#read 5, iclass 19, count 0 2006.173.20:24:25.58#ibcon#about to read 6, iclass 19, count 0 2006.173.20:24:25.58#ibcon#read 6, iclass 19, count 0 2006.173.20:24:25.58#ibcon#end of sib2, iclass 19, count 0 2006.173.20:24:25.58#ibcon#*after write, iclass 19, count 0 2006.173.20:24:25.58#ibcon#*before return 0, iclass 19, count 0 2006.173.20:24:25.58#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.20:24:25.58#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.20:24:25.58#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.20:24:25.58#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.20:24:25.58$vck44/vbbw=wide 2006.173.20:24:25.58#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.20:24:25.58#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.20:24:25.58#ibcon#ireg 8 cls_cnt 0 2006.173.20:24:25.58#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.20:24:25.65#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.20:24:25.65#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.20:24:25.65#ibcon#enter wrdev, iclass 21, count 0 2006.173.20:24:25.65#ibcon#first serial, iclass 21, count 0 2006.173.20:24:25.65#ibcon#enter sib2, iclass 21, count 0 2006.173.20:24:25.65#ibcon#flushed, iclass 21, count 0 2006.173.20:24:25.65#ibcon#about to write, iclass 21, count 0 2006.173.20:24:25.65#ibcon#wrote, iclass 21, count 0 2006.173.20:24:25.65#ibcon#about to read 3, iclass 21, count 0 2006.173.20:24:25.67#ibcon#read 3, iclass 21, count 0 2006.173.20:24:25.67#ibcon#about to read 4, iclass 21, count 0 2006.173.20:24:25.67#ibcon#read 4, iclass 21, count 0 2006.173.20:24:25.67#ibcon#about to read 5, iclass 21, count 0 2006.173.20:24:25.67#ibcon#read 5, iclass 21, count 0 2006.173.20:24:25.67#ibcon#about to read 6, iclass 21, count 0 2006.173.20:24:25.67#ibcon#read 6, iclass 21, count 0 2006.173.20:24:25.67#ibcon#end of sib2, iclass 21, count 0 2006.173.20:24:25.67#ibcon#*mode == 0, iclass 21, count 0 2006.173.20:24:25.67#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.20:24:25.67#ibcon#[27=BW32\r\n] 2006.173.20:24:25.67#ibcon#*before write, iclass 21, count 0 2006.173.20:24:25.67#ibcon#enter sib2, iclass 21, count 0 2006.173.20:24:25.67#ibcon#flushed, iclass 21, count 0 2006.173.20:24:25.67#ibcon#about to write, iclass 21, count 0 2006.173.20:24:25.67#ibcon#wrote, iclass 21, count 0 2006.173.20:24:25.67#ibcon#about to read 3, iclass 21, count 0 2006.173.20:24:25.70#ibcon#read 3, iclass 21, count 0 2006.173.20:24:25.70#ibcon#about to read 4, iclass 21, count 0 2006.173.20:24:25.70#ibcon#read 4, iclass 21, count 0 2006.173.20:24:25.70#ibcon#about to read 5, iclass 21, count 0 2006.173.20:24:25.70#ibcon#read 5, iclass 21, count 0 2006.173.20:24:25.70#ibcon#about to read 6, iclass 21, count 0 2006.173.20:24:25.70#ibcon#read 6, iclass 21, count 0 2006.173.20:24:25.70#ibcon#end of sib2, iclass 21, count 0 2006.173.20:24:25.70#ibcon#*after write, iclass 21, count 0 2006.173.20:24:25.70#ibcon#*before return 0, iclass 21, count 0 2006.173.20:24:25.70#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.20:24:25.70#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.20:24:25.70#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.20:24:25.70#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.20:24:25.70$setupk4/ifdk4 2006.173.20:24:25.70$ifdk4/lo= 2006.173.20:24:25.70$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.20:24:25.70$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.20:24:25.70$ifdk4/patch= 2006.173.20:24:25.70$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.20:24:25.70$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.20:24:25.70$setupk4/!*+20s 2006.173.20:24:32.03#abcon#<5=/07 0.4 1.1 19.861001002.8\r\n> 2006.173.20:24:32.05#abcon#{5=INTERFACE CLEAR} 2006.173.20:24:32.11#abcon#[5=S1D000X0/0*\r\n] 2006.173.20:24:40.21$setupk4/"tpicd 2006.173.20:24:40.21$setupk4/echo=off 2006.173.20:24:40.21$setupk4/xlog=off 2006.173.20:24:40.21:!2006.173.20:29:25 2006.173.20:24:45.14#trakl#Source acquired 2006.173.20:24:46.14#flagr#flagr/antenna,acquired 2006.173.20:29:25.02:preob 2006.173.20:29:26.14/onsource/TRACKING 2006.173.20:29:26.14:!2006.173.20:29:35 2006.173.20:29:35.01:"tape 2006.173.20:29:35.02:"st=record 2006.173.20:29:35.02:data_valid=on 2006.173.20:29:35.02:midob 2006.173.20:29:36.14/onsource/TRACKING 2006.173.20:29:36.14/wx/19.93,1003.0,100 2006.173.20:29:36.19/cable/+6.5171E-03 2006.173.20:29:37.28/va/01,07,usb,yes,52,56 2006.173.20:29:37.28/va/02,06,usb,yes,52,53 2006.173.20:29:37.28/va/03,05,usb,yes,65,68 2006.173.20:29:37.28/va/04,06,usb,yes,53,56 2006.173.20:29:37.28/va/05,04,usb,yes,42,43 2006.173.20:29:37.28/va/06,03,usb,yes,58,58 2006.173.20:29:37.28/va/07,04,usb,yes,48,49 2006.173.20:29:37.28/va/08,04,usb,yes,41,48 2006.173.20:29:37.52/valo/01,524.99,yes,locked 2006.173.20:29:37.52/valo/02,534.99,yes,locked 2006.173.20:29:37.52/valo/03,564.99,yes,locked 2006.173.20:29:37.52/valo/04,624.99,yes,locked 2006.173.20:29:37.52/valo/05,734.99,yes,locked 2006.173.20:29:37.52/valo/06,814.99,yes,locked 2006.173.20:29:37.52/valo/07,864.99,yes,locked 2006.173.20:29:37.52/valo/08,884.99,yes,locked 2006.173.20:29:38.60/vb/01,04,usb,yes,40,37 2006.173.20:29:38.60/vb/02,04,usb,yes,43,42 2006.173.20:29:38.61/vb/03,04,usb,yes,39,43 2006.173.20:29:38.61/vb/04,04,usb,yes,44,43 2006.173.20:29:38.61/vb/05,04,usb,yes,35,38 2006.173.20:29:38.61/vb/06,04,usb,yes,41,36 2006.173.20:29:38.61/vb/07,04,usb,yes,40,40 2006.173.20:29:38.61/vb/08,04,usb,yes,37,41 2006.173.20:29:38.83/vblo/01,629.99,yes,locked 2006.173.20:29:38.84/vblo/02,634.99,yes,locked 2006.173.20:29:38.84/vblo/03,649.99,yes,locked 2006.173.20:29:38.84/vblo/04,679.99,yes,locked 2006.173.20:29:38.84/vblo/05,709.99,yes,locked 2006.173.20:29:38.84/vblo/06,719.99,yes,locked 2006.173.20:29:38.84/vblo/07,734.99,yes,locked 2006.173.20:29:38.84/vblo/08,744.99,yes,locked 2006.173.20:29:38.98/vabw/8 2006.173.20:29:39.13/vbbw/8 2006.173.20:29:39.23/xfe/off,on,15.2 2006.173.20:29:39.61/ifatt/23,28,28,28 2006.173.20:29:40.07/fmout-gps/S +3.89E-07 2006.173.20:29:40.11:!2006.173.20:30:15 2006.173.20:30:15.02:data_valid=off 2006.173.20:30:15.02:"et 2006.173.20:30:15.02:!+3s 2006.173.20:30:18.04:"tape 2006.173.20:30:18.05:postob 2006.173.20:30:18.13/cable/+6.5175E-03 2006.173.20:30:18.14/wx/19.96,1003.0,100 2006.173.20:30:18.19/fmout-gps/S +3.90E-07 2006.173.20:30:18.20:scan_name=173-2031,jd0606,260 2006.173.20:30:18.20:source=1044+719,104827.62,714335.9,2000.0,neutral 2006.173.20:30:19.15#flagr#flagr/antenna,new-source 2006.173.20:30:19.15:checkk5 2006.173.20:30:19.57/chk_autoobs//k5ts1/ autoobs is running! 2006.173.20:30:19.94/chk_autoobs//k5ts2/ autoobs is running! 2006.173.20:30:20.34/chk_autoobs//k5ts3/ autoobs is running! 2006.173.20:30:20.75/chk_autoobs//k5ts4/ autoobs is running! 2006.173.20:30:21.13/chk_obsdata//k5ts1/T1732029??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.20:30:21.51/chk_obsdata//k5ts2/T1732029??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.20:30:21.90/chk_obsdata//k5ts3/T1732029??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.20:30:22.31/chk_obsdata//k5ts4/T1732029??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.20:30:23.02/k5log//k5ts1_log_newline 2006.173.20:30:23.74/k5log//k5ts2_log_newline 2006.173.20:30:24.43/k5log//k5ts3_log_newline 2006.173.20:30:25.13/k5log//k5ts4_log_newline 2006.173.20:30:25.15/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.20:30:25.15:setupk4=1 2006.173.20:30:25.15$setupk4/echo=on 2006.173.20:30:25.15$setupk4/pcalon 2006.173.20:30:25.15$pcalon/"no phase cal control is implemented here 2006.173.20:30:25.15$setupk4/"tpicd=stop 2006.173.20:30:25.15$setupk4/"rec=synch_on 2006.173.20:30:25.15$setupk4/"rec_mode=128 2006.173.20:30:25.15$setupk4/!* 2006.173.20:30:25.15$setupk4/recpk4 2006.173.20:30:25.15$recpk4/recpatch= 2006.173.20:30:25.16$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.20:30:25.16$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.20:30:25.16$setupk4/vck44 2006.173.20:30:25.16$vck44/valo=1,524.99 2006.173.20:30:25.16#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.20:30:25.16#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.20:30:25.16#ibcon#ireg 17 cls_cnt 0 2006.173.20:30:25.16#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.20:30:25.16#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.20:30:25.16#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.20:30:25.16#ibcon#enter wrdev, iclass 22, count 0 2006.173.20:30:25.16#ibcon#first serial, iclass 22, count 0 2006.173.20:30:25.16#ibcon#enter sib2, iclass 22, count 0 2006.173.20:30:25.16#ibcon#flushed, iclass 22, count 0 2006.173.20:30:25.16#ibcon#about to write, iclass 22, count 0 2006.173.20:30:25.16#ibcon#wrote, iclass 22, count 0 2006.173.20:30:25.16#ibcon#about to read 3, iclass 22, count 0 2006.173.20:30:25.17#ibcon#read 3, iclass 22, count 0 2006.173.20:30:25.17#ibcon#about to read 4, iclass 22, count 0 2006.173.20:30:25.17#ibcon#read 4, iclass 22, count 0 2006.173.20:30:25.17#ibcon#about to read 5, iclass 22, count 0 2006.173.20:30:25.17#ibcon#read 5, iclass 22, count 0 2006.173.20:30:25.17#ibcon#about to read 6, iclass 22, count 0 2006.173.20:30:25.17#ibcon#read 6, iclass 22, count 0 2006.173.20:30:25.17#ibcon#end of sib2, iclass 22, count 0 2006.173.20:30:25.17#ibcon#*mode == 0, iclass 22, count 0 2006.173.20:30:25.17#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.20:30:25.17#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.20:30:25.17#ibcon#*before write, iclass 22, count 0 2006.173.20:30:25.17#ibcon#enter sib2, iclass 22, count 0 2006.173.20:30:25.17#ibcon#flushed, iclass 22, count 0 2006.173.20:30:25.17#ibcon#about to write, iclass 22, count 0 2006.173.20:30:25.17#ibcon#wrote, iclass 22, count 0 2006.173.20:30:25.17#ibcon#about to read 3, iclass 22, count 0 2006.173.20:30:25.22#ibcon#read 3, iclass 22, count 0 2006.173.20:30:25.22#ibcon#about to read 4, iclass 22, count 0 2006.173.20:30:25.22#ibcon#read 4, iclass 22, count 0 2006.173.20:30:25.22#ibcon#about to read 5, iclass 22, count 0 2006.173.20:30:25.22#ibcon#read 5, iclass 22, count 0 2006.173.20:30:25.22#ibcon#about to read 6, iclass 22, count 0 2006.173.20:30:25.22#ibcon#read 6, iclass 22, count 0 2006.173.20:30:25.22#ibcon#end of sib2, iclass 22, count 0 2006.173.20:30:25.22#ibcon#*after write, iclass 22, count 0 2006.173.20:30:25.22#ibcon#*before return 0, iclass 22, count 0 2006.173.20:30:25.22#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.20:30:25.22#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.20:30:25.22#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.20:30:25.22#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.20:30:25.23$vck44/va=1,7 2006.173.20:30:25.23#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.20:30:25.23#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.20:30:25.23#ibcon#ireg 11 cls_cnt 2 2006.173.20:30:25.23#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.20:30:25.23#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.20:30:25.23#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.20:30:25.23#ibcon#enter wrdev, iclass 24, count 2 2006.173.20:30:25.23#ibcon#first serial, iclass 24, count 2 2006.173.20:30:25.23#ibcon#enter sib2, iclass 24, count 2 2006.173.20:30:25.23#ibcon#flushed, iclass 24, count 2 2006.173.20:30:25.23#ibcon#about to write, iclass 24, count 2 2006.173.20:30:25.23#ibcon#wrote, iclass 24, count 2 2006.173.20:30:25.23#ibcon#about to read 3, iclass 24, count 2 2006.173.20:30:25.24#ibcon#read 3, iclass 24, count 2 2006.173.20:30:25.24#ibcon#about to read 4, iclass 24, count 2 2006.173.20:30:25.24#ibcon#read 4, iclass 24, count 2 2006.173.20:30:25.24#ibcon#about to read 5, iclass 24, count 2 2006.173.20:30:25.24#ibcon#read 5, iclass 24, count 2 2006.173.20:30:25.24#ibcon#about to read 6, iclass 24, count 2 2006.173.20:30:25.24#ibcon#read 6, iclass 24, count 2 2006.173.20:30:25.24#ibcon#end of sib2, iclass 24, count 2 2006.173.20:30:25.24#ibcon#*mode == 0, iclass 24, count 2 2006.173.20:30:25.24#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.20:30:25.24#ibcon#[25=AT01-07\r\n] 2006.173.20:30:25.24#ibcon#*before write, iclass 24, count 2 2006.173.20:30:25.24#ibcon#enter sib2, iclass 24, count 2 2006.173.20:30:25.24#ibcon#flushed, iclass 24, count 2 2006.173.20:30:25.24#ibcon#about to write, iclass 24, count 2 2006.173.20:30:25.24#ibcon#wrote, iclass 24, count 2 2006.173.20:30:25.24#ibcon#about to read 3, iclass 24, count 2 2006.173.20:30:25.27#ibcon#read 3, iclass 24, count 2 2006.173.20:30:25.27#ibcon#about to read 4, iclass 24, count 2 2006.173.20:30:25.27#ibcon#read 4, iclass 24, count 2 2006.173.20:30:25.27#ibcon#about to read 5, iclass 24, count 2 2006.173.20:30:25.27#ibcon#read 5, iclass 24, count 2 2006.173.20:30:25.27#ibcon#about to read 6, iclass 24, count 2 2006.173.20:30:25.27#ibcon#read 6, iclass 24, count 2 2006.173.20:30:25.27#ibcon#end of sib2, iclass 24, count 2 2006.173.20:30:25.27#ibcon#*after write, iclass 24, count 2 2006.173.20:30:25.27#ibcon#*before return 0, iclass 24, count 2 2006.173.20:30:25.27#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.20:30:25.27#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.20:30:25.27#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.20:30:25.27#ibcon#ireg 7 cls_cnt 0 2006.173.20:30:25.27#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.20:30:25.39#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.20:30:25.39#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.20:30:25.39#ibcon#enter wrdev, iclass 24, count 0 2006.173.20:30:25.39#ibcon#first serial, iclass 24, count 0 2006.173.20:30:25.39#ibcon#enter sib2, iclass 24, count 0 2006.173.20:30:25.39#ibcon#flushed, iclass 24, count 0 2006.173.20:30:25.39#ibcon#about to write, iclass 24, count 0 2006.173.20:30:25.39#ibcon#wrote, iclass 24, count 0 2006.173.20:30:25.39#ibcon#about to read 3, iclass 24, count 0 2006.173.20:30:25.41#ibcon#read 3, iclass 24, count 0 2006.173.20:30:25.41#ibcon#about to read 4, iclass 24, count 0 2006.173.20:30:25.41#ibcon#read 4, iclass 24, count 0 2006.173.20:30:25.41#ibcon#about to read 5, iclass 24, count 0 2006.173.20:30:25.41#ibcon#read 5, iclass 24, count 0 2006.173.20:30:25.41#ibcon#about to read 6, iclass 24, count 0 2006.173.20:30:25.41#ibcon#read 6, iclass 24, count 0 2006.173.20:30:25.41#ibcon#end of sib2, iclass 24, count 0 2006.173.20:30:25.41#ibcon#*mode == 0, iclass 24, count 0 2006.173.20:30:25.41#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.20:30:25.41#ibcon#[25=USB\r\n] 2006.173.20:30:25.41#ibcon#*before write, iclass 24, count 0 2006.173.20:30:25.41#ibcon#enter sib2, iclass 24, count 0 2006.173.20:30:25.41#ibcon#flushed, iclass 24, count 0 2006.173.20:30:25.41#ibcon#about to write, iclass 24, count 0 2006.173.20:30:25.41#ibcon#wrote, iclass 24, count 0 2006.173.20:30:25.41#ibcon#about to read 3, iclass 24, count 0 2006.173.20:30:25.44#ibcon#read 3, iclass 24, count 0 2006.173.20:30:25.44#ibcon#about to read 4, iclass 24, count 0 2006.173.20:30:25.44#ibcon#read 4, iclass 24, count 0 2006.173.20:30:25.44#ibcon#about to read 5, iclass 24, count 0 2006.173.20:30:25.44#ibcon#read 5, iclass 24, count 0 2006.173.20:30:25.44#ibcon#about to read 6, iclass 24, count 0 2006.173.20:30:25.44#ibcon#read 6, iclass 24, count 0 2006.173.20:30:25.44#ibcon#end of sib2, iclass 24, count 0 2006.173.20:30:25.44#ibcon#*after write, iclass 24, count 0 2006.173.20:30:25.44#ibcon#*before return 0, iclass 24, count 0 2006.173.20:30:25.44#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.20:30:25.44#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.20:30:25.44#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.20:30:25.44#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.20:30:25.45$vck44/valo=2,534.99 2006.173.20:30:25.45#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.20:30:25.45#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.20:30:25.45#ibcon#ireg 17 cls_cnt 0 2006.173.20:30:25.45#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.20:30:25.45#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.20:30:25.45#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.20:30:25.45#ibcon#enter wrdev, iclass 26, count 0 2006.173.20:30:25.45#ibcon#first serial, iclass 26, count 0 2006.173.20:30:25.45#ibcon#enter sib2, iclass 26, count 0 2006.173.20:30:25.45#ibcon#flushed, iclass 26, count 0 2006.173.20:30:25.45#ibcon#about to write, iclass 26, count 0 2006.173.20:30:25.45#ibcon#wrote, iclass 26, count 0 2006.173.20:30:25.45#ibcon#about to read 3, iclass 26, count 0 2006.173.20:30:25.46#ibcon#read 3, iclass 26, count 0 2006.173.20:30:25.46#ibcon#about to read 4, iclass 26, count 0 2006.173.20:30:25.46#ibcon#read 4, iclass 26, count 0 2006.173.20:30:25.46#ibcon#about to read 5, iclass 26, count 0 2006.173.20:30:25.46#ibcon#read 5, iclass 26, count 0 2006.173.20:30:25.46#ibcon#about to read 6, iclass 26, count 0 2006.173.20:30:25.46#ibcon#read 6, iclass 26, count 0 2006.173.20:30:25.46#ibcon#end of sib2, iclass 26, count 0 2006.173.20:30:25.46#ibcon#*mode == 0, iclass 26, count 0 2006.173.20:30:25.46#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.20:30:25.46#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.20:30:25.46#ibcon#*before write, iclass 26, count 0 2006.173.20:30:25.46#ibcon#enter sib2, iclass 26, count 0 2006.173.20:30:25.46#ibcon#flushed, iclass 26, count 0 2006.173.20:30:25.46#ibcon#about to write, iclass 26, count 0 2006.173.20:30:25.46#ibcon#wrote, iclass 26, count 0 2006.173.20:30:25.46#ibcon#about to read 3, iclass 26, count 0 2006.173.20:30:25.50#ibcon#read 3, iclass 26, count 0 2006.173.20:30:25.50#ibcon#about to read 4, iclass 26, count 0 2006.173.20:30:25.50#ibcon#read 4, iclass 26, count 0 2006.173.20:30:25.50#ibcon#about to read 5, iclass 26, count 0 2006.173.20:30:25.50#ibcon#read 5, iclass 26, count 0 2006.173.20:30:25.50#ibcon#about to read 6, iclass 26, count 0 2006.173.20:30:25.50#ibcon#read 6, iclass 26, count 0 2006.173.20:30:25.50#ibcon#end of sib2, iclass 26, count 0 2006.173.20:30:25.50#ibcon#*after write, iclass 26, count 0 2006.173.20:30:25.50#ibcon#*before return 0, iclass 26, count 0 2006.173.20:30:25.50#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.20:30:25.50#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.20:30:25.50#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.20:30:25.50#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.20:30:25.50$vck44/va=2,6 2006.173.20:30:25.50#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.20:30:25.50#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.20:30:25.50#ibcon#ireg 11 cls_cnt 2 2006.173.20:30:25.51#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.20:30:25.55#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.20:30:25.55#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.20:30:25.55#ibcon#enter wrdev, iclass 28, count 2 2006.173.20:30:25.55#ibcon#first serial, iclass 28, count 2 2006.173.20:30:25.55#ibcon#enter sib2, iclass 28, count 2 2006.173.20:30:25.55#ibcon#flushed, iclass 28, count 2 2006.173.20:30:25.55#ibcon#about to write, iclass 28, count 2 2006.173.20:30:25.55#ibcon#wrote, iclass 28, count 2 2006.173.20:30:25.55#ibcon#about to read 3, iclass 28, count 2 2006.173.20:30:25.57#ibcon#read 3, iclass 28, count 2 2006.173.20:30:25.57#ibcon#about to read 4, iclass 28, count 2 2006.173.20:30:25.57#ibcon#read 4, iclass 28, count 2 2006.173.20:30:25.57#ibcon#about to read 5, iclass 28, count 2 2006.173.20:30:25.57#ibcon#read 5, iclass 28, count 2 2006.173.20:30:25.57#ibcon#about to read 6, iclass 28, count 2 2006.173.20:30:25.57#ibcon#read 6, iclass 28, count 2 2006.173.20:30:25.57#ibcon#end of sib2, iclass 28, count 2 2006.173.20:30:25.57#ibcon#*mode == 0, iclass 28, count 2 2006.173.20:30:25.57#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.20:30:25.57#ibcon#[25=AT02-06\r\n] 2006.173.20:30:25.57#ibcon#*before write, iclass 28, count 2 2006.173.20:30:25.57#ibcon#enter sib2, iclass 28, count 2 2006.173.20:30:25.57#ibcon#flushed, iclass 28, count 2 2006.173.20:30:25.57#ibcon#about to write, iclass 28, count 2 2006.173.20:30:25.57#ibcon#wrote, iclass 28, count 2 2006.173.20:30:25.57#ibcon#about to read 3, iclass 28, count 2 2006.173.20:30:25.60#ibcon#read 3, iclass 28, count 2 2006.173.20:30:25.60#ibcon#about to read 4, iclass 28, count 2 2006.173.20:30:25.60#ibcon#read 4, iclass 28, count 2 2006.173.20:30:25.60#ibcon#about to read 5, iclass 28, count 2 2006.173.20:30:25.60#ibcon#read 5, iclass 28, count 2 2006.173.20:30:25.60#ibcon#about to read 6, iclass 28, count 2 2006.173.20:30:25.60#ibcon#read 6, iclass 28, count 2 2006.173.20:30:25.60#ibcon#end of sib2, iclass 28, count 2 2006.173.20:30:25.60#ibcon#*after write, iclass 28, count 2 2006.173.20:30:25.60#ibcon#*before return 0, iclass 28, count 2 2006.173.20:30:25.60#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.20:30:25.60#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.20:30:25.60#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.20:30:25.60#ibcon#ireg 7 cls_cnt 0 2006.173.20:30:25.60#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.20:30:25.72#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.20:30:25.72#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.20:30:25.72#ibcon#enter wrdev, iclass 28, count 0 2006.173.20:30:25.72#ibcon#first serial, iclass 28, count 0 2006.173.20:30:25.72#ibcon#enter sib2, iclass 28, count 0 2006.173.20:30:25.72#ibcon#flushed, iclass 28, count 0 2006.173.20:30:25.72#ibcon#about to write, iclass 28, count 0 2006.173.20:30:25.72#ibcon#wrote, iclass 28, count 0 2006.173.20:30:25.72#ibcon#about to read 3, iclass 28, count 0 2006.173.20:30:25.74#ibcon#read 3, iclass 28, count 0 2006.173.20:30:25.74#ibcon#about to read 4, iclass 28, count 0 2006.173.20:30:25.74#ibcon#read 4, iclass 28, count 0 2006.173.20:30:25.74#ibcon#about to read 5, iclass 28, count 0 2006.173.20:30:25.74#ibcon#read 5, iclass 28, count 0 2006.173.20:30:25.74#ibcon#about to read 6, iclass 28, count 0 2006.173.20:30:25.74#ibcon#read 6, iclass 28, count 0 2006.173.20:30:25.74#ibcon#end of sib2, iclass 28, count 0 2006.173.20:30:25.74#ibcon#*mode == 0, iclass 28, count 0 2006.173.20:30:25.74#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.20:30:25.74#ibcon#[25=USB\r\n] 2006.173.20:30:25.74#ibcon#*before write, iclass 28, count 0 2006.173.20:30:25.74#ibcon#enter sib2, iclass 28, count 0 2006.173.20:30:25.74#ibcon#flushed, iclass 28, count 0 2006.173.20:30:25.74#ibcon#about to write, iclass 28, count 0 2006.173.20:30:25.74#ibcon#wrote, iclass 28, count 0 2006.173.20:30:25.74#ibcon#about to read 3, iclass 28, count 0 2006.173.20:30:25.77#ibcon#read 3, iclass 28, count 0 2006.173.20:30:25.77#ibcon#about to read 4, iclass 28, count 0 2006.173.20:30:25.77#ibcon#read 4, iclass 28, count 0 2006.173.20:30:25.77#ibcon#about to read 5, iclass 28, count 0 2006.173.20:30:25.77#ibcon#read 5, iclass 28, count 0 2006.173.20:30:25.77#ibcon#about to read 6, iclass 28, count 0 2006.173.20:30:25.77#ibcon#read 6, iclass 28, count 0 2006.173.20:30:25.77#ibcon#end of sib2, iclass 28, count 0 2006.173.20:30:25.77#ibcon#*after write, iclass 28, count 0 2006.173.20:30:25.77#ibcon#*before return 0, iclass 28, count 0 2006.173.20:30:25.77#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.20:30:25.77#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.20:30:25.77#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.20:30:25.77#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.20:30:25.77$vck44/valo=3,564.99 2006.173.20:30:25.78#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.20:30:25.78#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.20:30:25.78#ibcon#ireg 17 cls_cnt 0 2006.173.20:30:25.78#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.20:30:25.78#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.20:30:25.78#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.20:30:25.78#ibcon#enter wrdev, iclass 30, count 0 2006.173.20:30:25.78#ibcon#first serial, iclass 30, count 0 2006.173.20:30:25.78#ibcon#enter sib2, iclass 30, count 0 2006.173.20:30:25.78#ibcon#flushed, iclass 30, count 0 2006.173.20:30:25.78#ibcon#about to write, iclass 30, count 0 2006.173.20:30:25.78#ibcon#wrote, iclass 30, count 0 2006.173.20:30:25.78#ibcon#about to read 3, iclass 30, count 0 2006.173.20:30:25.79#ibcon#read 3, iclass 30, count 0 2006.173.20:30:25.79#ibcon#about to read 4, iclass 30, count 0 2006.173.20:30:25.79#ibcon#read 4, iclass 30, count 0 2006.173.20:30:25.79#ibcon#about to read 5, iclass 30, count 0 2006.173.20:30:25.79#ibcon#read 5, iclass 30, count 0 2006.173.20:30:25.79#ibcon#about to read 6, iclass 30, count 0 2006.173.20:30:25.79#ibcon#read 6, iclass 30, count 0 2006.173.20:30:25.79#ibcon#end of sib2, iclass 30, count 0 2006.173.20:30:25.79#ibcon#*mode == 0, iclass 30, count 0 2006.173.20:30:25.79#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.20:30:25.79#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.20:30:25.79#ibcon#*before write, iclass 30, count 0 2006.173.20:30:25.79#ibcon#enter sib2, iclass 30, count 0 2006.173.20:30:25.79#ibcon#flushed, iclass 30, count 0 2006.173.20:30:25.79#ibcon#about to write, iclass 30, count 0 2006.173.20:30:25.79#ibcon#wrote, iclass 30, count 0 2006.173.20:30:25.79#ibcon#about to read 3, iclass 30, count 0 2006.173.20:30:25.83#ibcon#read 3, iclass 30, count 0 2006.173.20:30:25.83#ibcon#about to read 4, iclass 30, count 0 2006.173.20:30:25.83#ibcon#read 4, iclass 30, count 0 2006.173.20:30:25.83#ibcon#about to read 5, iclass 30, count 0 2006.173.20:30:25.83#ibcon#read 5, iclass 30, count 0 2006.173.20:30:25.83#ibcon#about to read 6, iclass 30, count 0 2006.173.20:30:25.83#ibcon#read 6, iclass 30, count 0 2006.173.20:30:25.83#ibcon#end of sib2, iclass 30, count 0 2006.173.20:30:25.83#ibcon#*after write, iclass 30, count 0 2006.173.20:30:25.83#ibcon#*before return 0, iclass 30, count 0 2006.173.20:30:25.83#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.20:30:25.83#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.20:30:25.83#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.20:30:25.83#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.20:30:25.83$vck44/va=3,5 2006.173.20:30:25.83#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.173.20:30:25.83#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.173.20:30:25.83#ibcon#ireg 11 cls_cnt 2 2006.173.20:30:25.83#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.20:30:25.89#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.20:30:25.89#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.20:30:25.89#ibcon#enter wrdev, iclass 32, count 2 2006.173.20:30:25.89#ibcon#first serial, iclass 32, count 2 2006.173.20:30:25.89#ibcon#enter sib2, iclass 32, count 2 2006.173.20:30:25.89#ibcon#flushed, iclass 32, count 2 2006.173.20:30:25.89#ibcon#about to write, iclass 32, count 2 2006.173.20:30:25.89#ibcon#wrote, iclass 32, count 2 2006.173.20:30:25.89#ibcon#about to read 3, iclass 32, count 2 2006.173.20:30:25.91#ibcon#read 3, iclass 32, count 2 2006.173.20:30:25.91#ibcon#about to read 4, iclass 32, count 2 2006.173.20:30:25.91#ibcon#read 4, iclass 32, count 2 2006.173.20:30:25.91#ibcon#about to read 5, iclass 32, count 2 2006.173.20:30:25.91#ibcon#read 5, iclass 32, count 2 2006.173.20:30:25.91#ibcon#about to read 6, iclass 32, count 2 2006.173.20:30:25.91#ibcon#read 6, iclass 32, count 2 2006.173.20:30:25.91#ibcon#end of sib2, iclass 32, count 2 2006.173.20:30:25.91#ibcon#*mode == 0, iclass 32, count 2 2006.173.20:30:25.91#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.173.20:30:25.91#ibcon#[25=AT03-05\r\n] 2006.173.20:30:25.91#ibcon#*before write, iclass 32, count 2 2006.173.20:30:25.91#ibcon#enter sib2, iclass 32, count 2 2006.173.20:30:25.91#ibcon#flushed, iclass 32, count 2 2006.173.20:30:25.91#ibcon#about to write, iclass 32, count 2 2006.173.20:30:25.91#ibcon#wrote, iclass 32, count 2 2006.173.20:30:25.91#ibcon#about to read 3, iclass 32, count 2 2006.173.20:30:25.94#ibcon#read 3, iclass 32, count 2 2006.173.20:30:25.94#ibcon#about to read 4, iclass 32, count 2 2006.173.20:30:25.94#ibcon#read 4, iclass 32, count 2 2006.173.20:30:25.94#ibcon#about to read 5, iclass 32, count 2 2006.173.20:30:25.94#ibcon#read 5, iclass 32, count 2 2006.173.20:30:25.94#ibcon#about to read 6, iclass 32, count 2 2006.173.20:30:25.94#ibcon#read 6, iclass 32, count 2 2006.173.20:30:25.94#ibcon#end of sib2, iclass 32, count 2 2006.173.20:30:25.94#ibcon#*after write, iclass 32, count 2 2006.173.20:30:25.94#ibcon#*before return 0, iclass 32, count 2 2006.173.20:30:25.94#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.20:30:25.94#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.173.20:30:25.94#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.173.20:30:25.94#ibcon#ireg 7 cls_cnt 0 2006.173.20:30:25.94#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.20:30:26.06#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.20:30:26.06#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.20:30:26.06#ibcon#enter wrdev, iclass 32, count 0 2006.173.20:30:26.06#ibcon#first serial, iclass 32, count 0 2006.173.20:30:26.06#ibcon#enter sib2, iclass 32, count 0 2006.173.20:30:26.06#ibcon#flushed, iclass 32, count 0 2006.173.20:30:26.06#ibcon#about to write, iclass 32, count 0 2006.173.20:30:26.06#ibcon#wrote, iclass 32, count 0 2006.173.20:30:26.06#ibcon#about to read 3, iclass 32, count 0 2006.173.20:30:26.08#ibcon#read 3, iclass 32, count 0 2006.173.20:30:26.08#ibcon#about to read 4, iclass 32, count 0 2006.173.20:30:26.08#ibcon#read 4, iclass 32, count 0 2006.173.20:30:26.08#ibcon#about to read 5, iclass 32, count 0 2006.173.20:30:26.08#ibcon#read 5, iclass 32, count 0 2006.173.20:30:26.08#ibcon#about to read 6, iclass 32, count 0 2006.173.20:30:26.08#ibcon#read 6, iclass 32, count 0 2006.173.20:30:26.08#ibcon#end of sib2, iclass 32, count 0 2006.173.20:30:26.08#ibcon#*mode == 0, iclass 32, count 0 2006.173.20:30:26.08#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.20:30:26.08#ibcon#[25=USB\r\n] 2006.173.20:30:26.08#ibcon#*before write, iclass 32, count 0 2006.173.20:30:26.08#ibcon#enter sib2, iclass 32, count 0 2006.173.20:30:26.08#ibcon#flushed, iclass 32, count 0 2006.173.20:30:26.08#ibcon#about to write, iclass 32, count 0 2006.173.20:30:26.08#ibcon#wrote, iclass 32, count 0 2006.173.20:30:26.08#ibcon#about to read 3, iclass 32, count 0 2006.173.20:30:26.11#ibcon#read 3, iclass 32, count 0 2006.173.20:30:26.11#ibcon#about to read 4, iclass 32, count 0 2006.173.20:30:26.11#ibcon#read 4, iclass 32, count 0 2006.173.20:30:26.11#ibcon#about to read 5, iclass 32, count 0 2006.173.20:30:26.11#ibcon#read 5, iclass 32, count 0 2006.173.20:30:26.11#ibcon#about to read 6, iclass 32, count 0 2006.173.20:30:26.11#ibcon#read 6, iclass 32, count 0 2006.173.20:30:26.11#ibcon#end of sib2, iclass 32, count 0 2006.173.20:30:26.11#ibcon#*after write, iclass 32, count 0 2006.173.20:30:26.11#ibcon#*before return 0, iclass 32, count 0 2006.173.20:30:26.11#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.20:30:26.11#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.173.20:30:26.11#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.20:30:26.11#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.20:30:26.12$vck44/valo=4,624.99 2006.173.20:30:26.12#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.20:30:26.12#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.20:30:26.12#ibcon#ireg 17 cls_cnt 0 2006.173.20:30:26.12#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.20:30:26.12#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.20:30:26.12#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.20:30:26.12#ibcon#enter wrdev, iclass 34, count 0 2006.173.20:30:26.12#ibcon#first serial, iclass 34, count 0 2006.173.20:30:26.12#ibcon#enter sib2, iclass 34, count 0 2006.173.20:30:26.12#ibcon#flushed, iclass 34, count 0 2006.173.20:30:26.12#ibcon#about to write, iclass 34, count 0 2006.173.20:30:26.12#ibcon#wrote, iclass 34, count 0 2006.173.20:30:26.12#ibcon#about to read 3, iclass 34, count 0 2006.173.20:30:26.13#ibcon#read 3, iclass 34, count 0 2006.173.20:30:26.13#ibcon#about to read 4, iclass 34, count 0 2006.173.20:30:26.13#ibcon#read 4, iclass 34, count 0 2006.173.20:30:26.13#ibcon#about to read 5, iclass 34, count 0 2006.173.20:30:26.13#ibcon#read 5, iclass 34, count 0 2006.173.20:30:26.13#ibcon#about to read 6, iclass 34, count 0 2006.173.20:30:26.13#ibcon#read 6, iclass 34, count 0 2006.173.20:30:26.13#ibcon#end of sib2, iclass 34, count 0 2006.173.20:30:26.13#ibcon#*mode == 0, iclass 34, count 0 2006.173.20:30:26.13#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.20:30:26.13#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.20:30:26.13#ibcon#*before write, iclass 34, count 0 2006.173.20:30:26.13#ibcon#enter sib2, iclass 34, count 0 2006.173.20:30:26.13#ibcon#flushed, iclass 34, count 0 2006.173.20:30:26.13#ibcon#about to write, iclass 34, count 0 2006.173.20:30:26.13#ibcon#wrote, iclass 34, count 0 2006.173.20:30:26.13#ibcon#about to read 3, iclass 34, count 0 2006.173.20:30:26.17#ibcon#read 3, iclass 34, count 0 2006.173.20:30:26.17#ibcon#about to read 4, iclass 34, count 0 2006.173.20:30:26.17#ibcon#read 4, iclass 34, count 0 2006.173.20:30:26.17#ibcon#about to read 5, iclass 34, count 0 2006.173.20:30:26.17#ibcon#read 5, iclass 34, count 0 2006.173.20:30:26.17#ibcon#about to read 6, iclass 34, count 0 2006.173.20:30:26.17#ibcon#read 6, iclass 34, count 0 2006.173.20:30:26.17#ibcon#end of sib2, iclass 34, count 0 2006.173.20:30:26.17#ibcon#*after write, iclass 34, count 0 2006.173.20:30:26.17#ibcon#*before return 0, iclass 34, count 0 2006.173.20:30:26.17#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.20:30:26.17#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.20:30:26.17#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.20:30:26.17#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.20:30:26.18$vck44/va=4,6 2006.173.20:30:26.18#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.20:30:26.18#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.20:30:26.18#ibcon#ireg 11 cls_cnt 2 2006.173.20:30:26.18#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.20:30:26.22#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.20:30:26.22#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.20:30:26.22#ibcon#enter wrdev, iclass 36, count 2 2006.173.20:30:26.22#ibcon#first serial, iclass 36, count 2 2006.173.20:30:26.22#ibcon#enter sib2, iclass 36, count 2 2006.173.20:30:26.22#ibcon#flushed, iclass 36, count 2 2006.173.20:30:26.22#ibcon#about to write, iclass 36, count 2 2006.173.20:30:26.22#ibcon#wrote, iclass 36, count 2 2006.173.20:30:26.22#ibcon#about to read 3, iclass 36, count 2 2006.173.20:30:26.24#ibcon#read 3, iclass 36, count 2 2006.173.20:30:26.24#ibcon#about to read 4, iclass 36, count 2 2006.173.20:30:26.24#ibcon#read 4, iclass 36, count 2 2006.173.20:30:26.24#ibcon#about to read 5, iclass 36, count 2 2006.173.20:30:26.24#ibcon#read 5, iclass 36, count 2 2006.173.20:30:26.24#ibcon#about to read 6, iclass 36, count 2 2006.173.20:30:26.24#ibcon#read 6, iclass 36, count 2 2006.173.20:30:26.24#ibcon#end of sib2, iclass 36, count 2 2006.173.20:30:26.24#ibcon#*mode == 0, iclass 36, count 2 2006.173.20:30:26.24#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.20:30:26.24#ibcon#[25=AT04-06\r\n] 2006.173.20:30:26.24#ibcon#*before write, iclass 36, count 2 2006.173.20:30:26.24#ibcon#enter sib2, iclass 36, count 2 2006.173.20:30:26.24#ibcon#flushed, iclass 36, count 2 2006.173.20:30:26.24#ibcon#about to write, iclass 36, count 2 2006.173.20:30:26.24#ibcon#wrote, iclass 36, count 2 2006.173.20:30:26.24#ibcon#about to read 3, iclass 36, count 2 2006.173.20:30:26.27#ibcon#read 3, iclass 36, count 2 2006.173.20:30:26.27#ibcon#about to read 4, iclass 36, count 2 2006.173.20:30:26.27#ibcon#read 4, iclass 36, count 2 2006.173.20:30:26.27#ibcon#about to read 5, iclass 36, count 2 2006.173.20:30:26.27#ibcon#read 5, iclass 36, count 2 2006.173.20:30:26.27#ibcon#about to read 6, iclass 36, count 2 2006.173.20:30:26.27#ibcon#read 6, iclass 36, count 2 2006.173.20:30:26.27#ibcon#end of sib2, iclass 36, count 2 2006.173.20:30:26.27#ibcon#*after write, iclass 36, count 2 2006.173.20:30:26.96#ibcon#*before return 0, iclass 36, count 2 2006.173.20:30:26.96#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.20:30:26.96#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.20:30:26.96#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.20:30:26.96#ibcon#ireg 7 cls_cnt 0 2006.173.20:30:26.96#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.20:30:27.07#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.20:30:27.07#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.20:30:27.07#ibcon#enter wrdev, iclass 36, count 0 2006.173.20:30:27.07#ibcon#first serial, iclass 36, count 0 2006.173.20:30:27.07#ibcon#enter sib2, iclass 36, count 0 2006.173.20:30:27.07#ibcon#flushed, iclass 36, count 0 2006.173.20:30:27.07#ibcon#about to write, iclass 36, count 0 2006.173.20:30:27.07#ibcon#wrote, iclass 36, count 0 2006.173.20:30:27.07#ibcon#about to read 3, iclass 36, count 0 2006.173.20:30:27.09#ibcon#read 3, iclass 36, count 0 2006.173.20:30:27.09#ibcon#about to read 4, iclass 36, count 0 2006.173.20:30:27.09#ibcon#read 4, iclass 36, count 0 2006.173.20:30:27.09#ibcon#about to read 5, iclass 36, count 0 2006.173.20:30:27.09#ibcon#read 5, iclass 36, count 0 2006.173.20:30:27.09#ibcon#about to read 6, iclass 36, count 0 2006.173.20:30:27.09#ibcon#read 6, iclass 36, count 0 2006.173.20:30:27.09#ibcon#end of sib2, iclass 36, count 0 2006.173.20:30:27.09#ibcon#*mode == 0, iclass 36, count 0 2006.173.20:30:27.09#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.20:30:27.09#ibcon#[25=USB\r\n] 2006.173.20:30:27.09#ibcon#*before write, iclass 36, count 0 2006.173.20:30:27.09#ibcon#enter sib2, iclass 36, count 0 2006.173.20:30:27.09#ibcon#flushed, iclass 36, count 0 2006.173.20:30:27.09#ibcon#about to write, iclass 36, count 0 2006.173.20:30:27.09#ibcon#wrote, iclass 36, count 0 2006.173.20:30:27.09#ibcon#about to read 3, iclass 36, count 0 2006.173.20:30:27.12#ibcon#read 3, iclass 36, count 0 2006.173.20:30:27.12#ibcon#about to read 4, iclass 36, count 0 2006.173.20:30:27.12#ibcon#read 4, iclass 36, count 0 2006.173.20:30:27.12#ibcon#about to read 5, iclass 36, count 0 2006.173.20:30:27.12#ibcon#read 5, iclass 36, count 0 2006.173.20:30:27.12#ibcon#about to read 6, iclass 36, count 0 2006.173.20:30:27.12#ibcon#read 6, iclass 36, count 0 2006.173.20:30:27.12#ibcon#end of sib2, iclass 36, count 0 2006.173.20:30:27.12#ibcon#*after write, iclass 36, count 0 2006.173.20:30:27.12#ibcon#*before return 0, iclass 36, count 0 2006.173.20:30:27.12#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.20:30:27.12#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.20:30:27.12#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.20:30:27.12#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.20:30:27.13$vck44/valo=5,734.99 2006.173.20:30:27.13#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.20:30:27.13#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.20:30:27.13#ibcon#ireg 17 cls_cnt 0 2006.173.20:30:27.13#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.20:30:27.13#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.20:30:27.13#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.20:30:27.13#ibcon#enter wrdev, iclass 38, count 0 2006.173.20:30:27.13#ibcon#first serial, iclass 38, count 0 2006.173.20:30:27.13#ibcon#enter sib2, iclass 38, count 0 2006.173.20:30:27.13#ibcon#flushed, iclass 38, count 0 2006.173.20:30:27.13#ibcon#about to write, iclass 38, count 0 2006.173.20:30:27.13#ibcon#wrote, iclass 38, count 0 2006.173.20:30:27.13#ibcon#about to read 3, iclass 38, count 0 2006.173.20:30:27.14#ibcon#read 3, iclass 38, count 0 2006.173.20:30:27.14#ibcon#about to read 4, iclass 38, count 0 2006.173.20:30:27.14#ibcon#read 4, iclass 38, count 0 2006.173.20:30:27.14#ibcon#about to read 5, iclass 38, count 0 2006.173.20:30:27.14#ibcon#read 5, iclass 38, count 0 2006.173.20:30:27.14#ibcon#about to read 6, iclass 38, count 0 2006.173.20:30:27.14#ibcon#read 6, iclass 38, count 0 2006.173.20:30:27.14#ibcon#end of sib2, iclass 38, count 0 2006.173.20:30:27.14#ibcon#*mode == 0, iclass 38, count 0 2006.173.20:30:27.14#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.20:30:27.14#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.20:30:27.14#ibcon#*before write, iclass 38, count 0 2006.173.20:30:27.14#ibcon#enter sib2, iclass 38, count 0 2006.173.20:30:27.14#ibcon#flushed, iclass 38, count 0 2006.173.20:30:27.14#ibcon#about to write, iclass 38, count 0 2006.173.20:30:27.14#ibcon#wrote, iclass 38, count 0 2006.173.20:30:27.14#ibcon#about to read 3, iclass 38, count 0 2006.173.20:30:27.18#ibcon#read 3, iclass 38, count 0 2006.173.20:30:27.18#ibcon#about to read 4, iclass 38, count 0 2006.173.20:30:27.18#ibcon#read 4, iclass 38, count 0 2006.173.20:30:27.18#ibcon#about to read 5, iclass 38, count 0 2006.173.20:30:27.18#ibcon#read 5, iclass 38, count 0 2006.173.20:30:27.18#ibcon#about to read 6, iclass 38, count 0 2006.173.20:30:27.18#ibcon#read 6, iclass 38, count 0 2006.173.20:30:27.18#ibcon#end of sib2, iclass 38, count 0 2006.173.20:30:27.18#ibcon#*after write, iclass 38, count 0 2006.173.20:30:27.18#ibcon#*before return 0, iclass 38, count 0 2006.173.20:30:27.18#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.20:30:27.18#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.20:30:27.18#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.20:30:27.18#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.20:30:27.19$vck44/va=5,4 2006.173.20:30:27.19#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.20:30:27.19#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.20:30:27.19#ibcon#ireg 11 cls_cnt 2 2006.173.20:30:27.19#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.20:30:27.23#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.20:30:27.23#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.20:30:27.23#ibcon#enter wrdev, iclass 40, count 2 2006.173.20:30:27.23#ibcon#first serial, iclass 40, count 2 2006.173.20:30:27.23#ibcon#enter sib2, iclass 40, count 2 2006.173.20:30:27.23#ibcon#flushed, iclass 40, count 2 2006.173.20:30:27.23#ibcon#about to write, iclass 40, count 2 2006.173.20:30:27.23#ibcon#wrote, iclass 40, count 2 2006.173.20:30:27.23#ibcon#about to read 3, iclass 40, count 2 2006.173.20:30:27.25#ibcon#read 3, iclass 40, count 2 2006.173.20:30:27.25#ibcon#about to read 4, iclass 40, count 2 2006.173.20:30:27.25#ibcon#read 4, iclass 40, count 2 2006.173.20:30:27.25#ibcon#about to read 5, iclass 40, count 2 2006.173.20:30:27.25#ibcon#read 5, iclass 40, count 2 2006.173.20:30:27.25#ibcon#about to read 6, iclass 40, count 2 2006.173.20:30:27.25#ibcon#read 6, iclass 40, count 2 2006.173.20:30:27.25#ibcon#end of sib2, iclass 40, count 2 2006.173.20:30:27.25#ibcon#*mode == 0, iclass 40, count 2 2006.173.20:30:27.25#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.20:30:27.25#ibcon#[25=AT05-04\r\n] 2006.173.20:30:27.25#ibcon#*before write, iclass 40, count 2 2006.173.20:30:27.25#ibcon#enter sib2, iclass 40, count 2 2006.173.20:30:27.25#ibcon#flushed, iclass 40, count 2 2006.173.20:30:27.25#ibcon#about to write, iclass 40, count 2 2006.173.20:30:27.25#ibcon#wrote, iclass 40, count 2 2006.173.20:30:27.25#ibcon#about to read 3, iclass 40, count 2 2006.173.20:30:27.28#ibcon#read 3, iclass 40, count 2 2006.173.20:30:27.28#ibcon#about to read 4, iclass 40, count 2 2006.173.20:30:27.28#ibcon#read 4, iclass 40, count 2 2006.173.20:30:27.28#ibcon#about to read 5, iclass 40, count 2 2006.173.20:30:27.28#ibcon#read 5, iclass 40, count 2 2006.173.20:30:27.28#ibcon#about to read 6, iclass 40, count 2 2006.173.20:30:27.28#ibcon#read 6, iclass 40, count 2 2006.173.20:30:27.28#ibcon#end of sib2, iclass 40, count 2 2006.173.20:30:27.28#ibcon#*after write, iclass 40, count 2 2006.173.20:30:27.28#ibcon#*before return 0, iclass 40, count 2 2006.173.20:30:27.28#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.20:30:27.28#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.20:30:27.28#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.20:30:27.28#ibcon#ireg 7 cls_cnt 0 2006.173.20:30:27.28#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.20:30:27.40#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.20:30:27.40#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.20:30:27.40#ibcon#enter wrdev, iclass 40, count 0 2006.173.20:30:27.40#ibcon#first serial, iclass 40, count 0 2006.173.20:30:27.40#ibcon#enter sib2, iclass 40, count 0 2006.173.20:30:27.40#ibcon#flushed, iclass 40, count 0 2006.173.20:30:27.40#ibcon#about to write, iclass 40, count 0 2006.173.20:30:27.40#ibcon#wrote, iclass 40, count 0 2006.173.20:30:27.40#ibcon#about to read 3, iclass 40, count 0 2006.173.20:30:27.42#ibcon#read 3, iclass 40, count 0 2006.173.20:30:27.42#ibcon#about to read 4, iclass 40, count 0 2006.173.20:30:27.42#ibcon#read 4, iclass 40, count 0 2006.173.20:30:27.42#ibcon#about to read 5, iclass 40, count 0 2006.173.20:30:27.42#ibcon#read 5, iclass 40, count 0 2006.173.20:30:27.42#ibcon#about to read 6, iclass 40, count 0 2006.173.20:30:27.42#ibcon#read 6, iclass 40, count 0 2006.173.20:30:27.42#ibcon#end of sib2, iclass 40, count 0 2006.173.20:30:27.42#ibcon#*mode == 0, iclass 40, count 0 2006.173.20:30:27.42#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.20:30:27.42#ibcon#[25=USB\r\n] 2006.173.20:30:27.42#ibcon#*before write, iclass 40, count 0 2006.173.20:30:27.42#ibcon#enter sib2, iclass 40, count 0 2006.173.20:30:27.42#ibcon#flushed, iclass 40, count 0 2006.173.20:30:27.42#ibcon#about to write, iclass 40, count 0 2006.173.20:30:27.42#ibcon#wrote, iclass 40, count 0 2006.173.20:30:27.42#ibcon#about to read 3, iclass 40, count 0 2006.173.20:30:27.45#ibcon#read 3, iclass 40, count 0 2006.173.20:30:27.45#ibcon#about to read 4, iclass 40, count 0 2006.173.20:30:27.45#ibcon#read 4, iclass 40, count 0 2006.173.20:30:27.45#ibcon#about to read 5, iclass 40, count 0 2006.173.20:30:27.45#ibcon#read 5, iclass 40, count 0 2006.173.20:30:27.45#ibcon#about to read 6, iclass 40, count 0 2006.173.20:30:27.45#ibcon#read 6, iclass 40, count 0 2006.173.20:30:27.45#ibcon#end of sib2, iclass 40, count 0 2006.173.20:30:27.45#ibcon#*after write, iclass 40, count 0 2006.173.20:30:27.45#ibcon#*before return 0, iclass 40, count 0 2006.173.20:30:27.45#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.20:30:27.45#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.20:30:27.45#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.20:30:27.45#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.20:30:27.46$vck44/valo=6,814.99 2006.173.20:30:27.46#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.20:30:27.46#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.20:30:27.46#ibcon#ireg 17 cls_cnt 0 2006.173.20:30:27.46#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.20:30:27.46#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.20:30:27.46#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.20:30:27.46#ibcon#enter wrdev, iclass 4, count 0 2006.173.20:30:27.46#ibcon#first serial, iclass 4, count 0 2006.173.20:30:27.46#ibcon#enter sib2, iclass 4, count 0 2006.173.20:30:27.46#ibcon#flushed, iclass 4, count 0 2006.173.20:30:27.46#ibcon#about to write, iclass 4, count 0 2006.173.20:30:27.46#ibcon#wrote, iclass 4, count 0 2006.173.20:30:27.46#ibcon#about to read 3, iclass 4, count 0 2006.173.20:30:27.47#ibcon#read 3, iclass 4, count 0 2006.173.20:30:27.47#ibcon#about to read 4, iclass 4, count 0 2006.173.20:30:27.47#ibcon#read 4, iclass 4, count 0 2006.173.20:30:27.47#ibcon#about to read 5, iclass 4, count 0 2006.173.20:30:27.47#ibcon#read 5, iclass 4, count 0 2006.173.20:30:27.47#ibcon#about to read 6, iclass 4, count 0 2006.173.20:30:27.47#ibcon#read 6, iclass 4, count 0 2006.173.20:30:27.47#ibcon#end of sib2, iclass 4, count 0 2006.173.20:30:27.47#ibcon#*mode == 0, iclass 4, count 0 2006.173.20:30:27.47#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.20:30:27.47#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.20:30:27.47#ibcon#*before write, iclass 4, count 0 2006.173.20:30:27.47#ibcon#enter sib2, iclass 4, count 0 2006.173.20:30:27.47#ibcon#flushed, iclass 4, count 0 2006.173.20:30:27.47#ibcon#about to write, iclass 4, count 0 2006.173.20:30:27.47#ibcon#wrote, iclass 4, count 0 2006.173.20:30:27.47#ibcon#about to read 3, iclass 4, count 0 2006.173.20:30:27.51#ibcon#read 3, iclass 4, count 0 2006.173.20:30:27.51#ibcon#about to read 4, iclass 4, count 0 2006.173.20:30:27.51#ibcon#read 4, iclass 4, count 0 2006.173.20:30:27.51#ibcon#about to read 5, iclass 4, count 0 2006.173.20:30:27.51#ibcon#read 5, iclass 4, count 0 2006.173.20:30:27.51#ibcon#about to read 6, iclass 4, count 0 2006.173.20:30:27.51#ibcon#read 6, iclass 4, count 0 2006.173.20:30:27.51#ibcon#end of sib2, iclass 4, count 0 2006.173.20:30:27.51#ibcon#*after write, iclass 4, count 0 2006.173.20:30:27.51#ibcon#*before return 0, iclass 4, count 0 2006.173.20:30:27.51#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.20:30:27.51#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.20:30:27.51#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.20:30:27.51#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.20:30:27.52$vck44/va=6,3 2006.173.20:30:27.52#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.20:30:27.52#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.20:30:27.52#ibcon#ireg 11 cls_cnt 2 2006.173.20:30:27.52#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.20:30:27.56#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.20:30:27.56#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.20:30:27.56#ibcon#enter wrdev, iclass 6, count 2 2006.173.20:30:27.56#ibcon#first serial, iclass 6, count 2 2006.173.20:30:27.56#ibcon#enter sib2, iclass 6, count 2 2006.173.20:30:27.56#ibcon#flushed, iclass 6, count 2 2006.173.20:30:27.56#ibcon#about to write, iclass 6, count 2 2006.173.20:30:27.56#ibcon#wrote, iclass 6, count 2 2006.173.20:30:27.56#ibcon#about to read 3, iclass 6, count 2 2006.173.20:30:27.58#ibcon#read 3, iclass 6, count 2 2006.173.20:30:27.58#ibcon#about to read 4, iclass 6, count 2 2006.173.20:30:27.58#ibcon#read 4, iclass 6, count 2 2006.173.20:30:27.58#ibcon#about to read 5, iclass 6, count 2 2006.173.20:30:27.58#ibcon#read 5, iclass 6, count 2 2006.173.20:30:27.58#ibcon#about to read 6, iclass 6, count 2 2006.173.20:30:27.58#ibcon#read 6, iclass 6, count 2 2006.173.20:30:27.58#ibcon#end of sib2, iclass 6, count 2 2006.173.20:30:27.58#ibcon#*mode == 0, iclass 6, count 2 2006.173.20:30:27.58#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.20:30:27.58#ibcon#[25=AT06-03\r\n] 2006.173.20:30:27.58#ibcon#*before write, iclass 6, count 2 2006.173.20:30:27.58#ibcon#enter sib2, iclass 6, count 2 2006.173.20:30:27.58#ibcon#flushed, iclass 6, count 2 2006.173.20:30:27.58#ibcon#about to write, iclass 6, count 2 2006.173.20:30:27.58#ibcon#wrote, iclass 6, count 2 2006.173.20:30:27.58#ibcon#about to read 3, iclass 6, count 2 2006.173.20:30:27.61#ibcon#read 3, iclass 6, count 2 2006.173.20:30:27.61#ibcon#about to read 4, iclass 6, count 2 2006.173.20:30:27.61#ibcon#read 4, iclass 6, count 2 2006.173.20:30:27.61#ibcon#about to read 5, iclass 6, count 2 2006.173.20:30:27.61#ibcon#read 5, iclass 6, count 2 2006.173.20:30:27.61#ibcon#about to read 6, iclass 6, count 2 2006.173.20:30:27.61#ibcon#read 6, iclass 6, count 2 2006.173.20:30:27.61#ibcon#end of sib2, iclass 6, count 2 2006.173.20:30:27.61#ibcon#*after write, iclass 6, count 2 2006.173.20:30:27.61#ibcon#*before return 0, iclass 6, count 2 2006.173.20:30:27.61#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.20:30:27.61#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.20:30:27.61#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.20:30:27.61#ibcon#ireg 7 cls_cnt 0 2006.173.20:30:27.61#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.20:30:27.73#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.20:30:27.73#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.20:30:27.73#ibcon#enter wrdev, iclass 6, count 0 2006.173.20:30:27.73#ibcon#first serial, iclass 6, count 0 2006.173.20:30:27.73#ibcon#enter sib2, iclass 6, count 0 2006.173.20:30:27.73#ibcon#flushed, iclass 6, count 0 2006.173.20:30:27.73#ibcon#about to write, iclass 6, count 0 2006.173.20:30:27.73#ibcon#wrote, iclass 6, count 0 2006.173.20:30:27.73#ibcon#about to read 3, iclass 6, count 0 2006.173.20:30:27.75#ibcon#read 3, iclass 6, count 0 2006.173.20:30:27.75#ibcon#about to read 4, iclass 6, count 0 2006.173.20:30:27.75#ibcon#read 4, iclass 6, count 0 2006.173.20:30:27.75#ibcon#about to read 5, iclass 6, count 0 2006.173.20:30:27.75#ibcon#read 5, iclass 6, count 0 2006.173.20:30:27.75#ibcon#about to read 6, iclass 6, count 0 2006.173.20:30:27.75#ibcon#read 6, iclass 6, count 0 2006.173.20:30:27.75#ibcon#end of sib2, iclass 6, count 0 2006.173.20:30:27.75#ibcon#*mode == 0, iclass 6, count 0 2006.173.20:30:27.75#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.20:30:27.75#ibcon#[25=USB\r\n] 2006.173.20:30:27.75#ibcon#*before write, iclass 6, count 0 2006.173.20:30:27.75#ibcon#enter sib2, iclass 6, count 0 2006.173.20:30:27.75#ibcon#flushed, iclass 6, count 0 2006.173.20:30:27.75#ibcon#about to write, iclass 6, count 0 2006.173.20:30:27.75#ibcon#wrote, iclass 6, count 0 2006.173.20:30:27.75#ibcon#about to read 3, iclass 6, count 0 2006.173.20:30:27.78#ibcon#read 3, iclass 6, count 0 2006.173.20:30:27.78#ibcon#about to read 4, iclass 6, count 0 2006.173.20:30:27.78#ibcon#read 4, iclass 6, count 0 2006.173.20:30:27.78#ibcon#about to read 5, iclass 6, count 0 2006.173.20:30:27.78#ibcon#read 5, iclass 6, count 0 2006.173.20:30:27.78#ibcon#about to read 6, iclass 6, count 0 2006.173.20:30:27.78#ibcon#read 6, iclass 6, count 0 2006.173.20:30:27.78#ibcon#end of sib2, iclass 6, count 0 2006.173.20:30:27.78#ibcon#*after write, iclass 6, count 0 2006.173.20:30:27.78#ibcon#*before return 0, iclass 6, count 0 2006.173.20:30:27.78#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.20:30:27.78#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.20:30:27.78#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.20:30:27.78#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.20:30:27.79$vck44/valo=7,864.99 2006.173.20:30:27.79#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.20:30:27.79#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.20:30:27.79#ibcon#ireg 17 cls_cnt 0 2006.173.20:30:27.79#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.20:30:27.79#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.20:30:27.79#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.20:30:27.79#ibcon#enter wrdev, iclass 10, count 0 2006.173.20:30:27.79#ibcon#first serial, iclass 10, count 0 2006.173.20:30:27.79#ibcon#enter sib2, iclass 10, count 0 2006.173.20:30:27.79#ibcon#flushed, iclass 10, count 0 2006.173.20:30:27.79#ibcon#about to write, iclass 10, count 0 2006.173.20:30:27.79#ibcon#wrote, iclass 10, count 0 2006.173.20:30:27.79#ibcon#about to read 3, iclass 10, count 0 2006.173.20:30:27.80#ibcon#read 3, iclass 10, count 0 2006.173.20:30:27.80#ibcon#about to read 4, iclass 10, count 0 2006.173.20:30:27.80#ibcon#read 4, iclass 10, count 0 2006.173.20:30:27.80#ibcon#about to read 5, iclass 10, count 0 2006.173.20:30:27.80#ibcon#read 5, iclass 10, count 0 2006.173.20:30:27.80#ibcon#about to read 6, iclass 10, count 0 2006.173.20:30:27.80#ibcon#read 6, iclass 10, count 0 2006.173.20:30:27.80#ibcon#end of sib2, iclass 10, count 0 2006.173.20:30:27.80#ibcon#*mode == 0, iclass 10, count 0 2006.173.20:30:27.80#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.20:30:27.80#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.20:30:27.80#ibcon#*before write, iclass 10, count 0 2006.173.20:30:27.80#ibcon#enter sib2, iclass 10, count 0 2006.173.20:30:27.80#ibcon#flushed, iclass 10, count 0 2006.173.20:30:27.80#ibcon#about to write, iclass 10, count 0 2006.173.20:30:27.80#ibcon#wrote, iclass 10, count 0 2006.173.20:30:27.80#ibcon#about to read 3, iclass 10, count 0 2006.173.20:30:27.84#ibcon#read 3, iclass 10, count 0 2006.173.20:30:27.84#ibcon#about to read 4, iclass 10, count 0 2006.173.20:30:27.84#ibcon#read 4, iclass 10, count 0 2006.173.20:30:27.84#ibcon#about to read 5, iclass 10, count 0 2006.173.20:30:27.84#ibcon#read 5, iclass 10, count 0 2006.173.20:30:27.84#ibcon#about to read 6, iclass 10, count 0 2006.173.20:30:27.84#ibcon#read 6, iclass 10, count 0 2006.173.20:30:27.84#ibcon#end of sib2, iclass 10, count 0 2006.173.20:30:27.84#ibcon#*after write, iclass 10, count 0 2006.173.20:30:27.84#ibcon#*before return 0, iclass 10, count 0 2006.173.20:30:27.84#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.20:30:27.84#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.20:30:27.84#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.20:30:27.84#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.20:30:27.85$vck44/va=7,4 2006.173.20:30:27.85#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.20:30:27.85#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.20:30:27.85#ibcon#ireg 11 cls_cnt 2 2006.173.20:30:27.85#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.20:30:27.89#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.20:30:27.89#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.20:30:27.89#ibcon#enter wrdev, iclass 12, count 2 2006.173.20:30:27.89#ibcon#first serial, iclass 12, count 2 2006.173.20:30:27.89#ibcon#enter sib2, iclass 12, count 2 2006.173.20:30:27.89#ibcon#flushed, iclass 12, count 2 2006.173.20:30:27.89#ibcon#about to write, iclass 12, count 2 2006.173.20:30:27.89#ibcon#wrote, iclass 12, count 2 2006.173.20:30:27.89#ibcon#about to read 3, iclass 12, count 2 2006.173.20:30:27.91#ibcon#read 3, iclass 12, count 2 2006.173.20:30:27.91#ibcon#about to read 4, iclass 12, count 2 2006.173.20:30:27.91#ibcon#read 4, iclass 12, count 2 2006.173.20:30:27.91#ibcon#about to read 5, iclass 12, count 2 2006.173.20:30:27.91#ibcon#read 5, iclass 12, count 2 2006.173.20:30:27.91#ibcon#about to read 6, iclass 12, count 2 2006.173.20:30:27.91#ibcon#read 6, iclass 12, count 2 2006.173.20:30:27.91#ibcon#end of sib2, iclass 12, count 2 2006.173.20:30:27.91#ibcon#*mode == 0, iclass 12, count 2 2006.173.20:30:27.91#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.20:30:27.91#ibcon#[25=AT07-04\r\n] 2006.173.20:30:27.91#ibcon#*before write, iclass 12, count 2 2006.173.20:30:27.91#ibcon#enter sib2, iclass 12, count 2 2006.173.20:30:27.91#ibcon#flushed, iclass 12, count 2 2006.173.20:30:27.91#ibcon#about to write, iclass 12, count 2 2006.173.20:30:27.91#ibcon#wrote, iclass 12, count 2 2006.173.20:30:27.91#ibcon#about to read 3, iclass 12, count 2 2006.173.20:30:27.94#ibcon#read 3, iclass 12, count 2 2006.173.20:30:27.94#ibcon#about to read 4, iclass 12, count 2 2006.173.20:30:27.94#ibcon#read 4, iclass 12, count 2 2006.173.20:30:27.94#ibcon#about to read 5, iclass 12, count 2 2006.173.20:30:27.94#ibcon#read 5, iclass 12, count 2 2006.173.20:30:27.94#ibcon#about to read 6, iclass 12, count 2 2006.173.20:30:27.94#ibcon#read 6, iclass 12, count 2 2006.173.20:30:27.94#ibcon#end of sib2, iclass 12, count 2 2006.173.20:30:27.94#ibcon#*after write, iclass 12, count 2 2006.173.20:30:27.94#ibcon#*before return 0, iclass 12, count 2 2006.173.20:30:27.94#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.20:30:27.94#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.20:30:27.94#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.20:30:27.94#ibcon#ireg 7 cls_cnt 0 2006.173.20:30:27.94#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.20:30:28.06#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.20:30:28.06#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.20:30:28.06#ibcon#enter wrdev, iclass 12, count 0 2006.173.20:30:28.06#ibcon#first serial, iclass 12, count 0 2006.173.20:30:28.06#ibcon#enter sib2, iclass 12, count 0 2006.173.20:30:28.06#ibcon#flushed, iclass 12, count 0 2006.173.20:30:28.06#ibcon#about to write, iclass 12, count 0 2006.173.20:30:28.06#ibcon#wrote, iclass 12, count 0 2006.173.20:30:28.06#ibcon#about to read 3, iclass 12, count 0 2006.173.20:30:28.08#ibcon#read 3, iclass 12, count 0 2006.173.20:30:28.08#ibcon#about to read 4, iclass 12, count 0 2006.173.20:30:28.08#ibcon#read 4, iclass 12, count 0 2006.173.20:30:28.08#ibcon#about to read 5, iclass 12, count 0 2006.173.20:30:28.08#ibcon#read 5, iclass 12, count 0 2006.173.20:30:28.08#ibcon#about to read 6, iclass 12, count 0 2006.173.20:30:28.08#ibcon#read 6, iclass 12, count 0 2006.173.20:30:28.08#ibcon#end of sib2, iclass 12, count 0 2006.173.20:30:28.08#ibcon#*mode == 0, iclass 12, count 0 2006.173.20:30:28.08#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.20:30:28.08#ibcon#[25=USB\r\n] 2006.173.20:30:28.08#ibcon#*before write, iclass 12, count 0 2006.173.20:30:28.08#ibcon#enter sib2, iclass 12, count 0 2006.173.20:30:28.08#ibcon#flushed, iclass 12, count 0 2006.173.20:30:28.08#ibcon#about to write, iclass 12, count 0 2006.173.20:30:28.08#ibcon#wrote, iclass 12, count 0 2006.173.20:30:28.08#ibcon#about to read 3, iclass 12, count 0 2006.173.20:30:28.11#ibcon#read 3, iclass 12, count 0 2006.173.20:30:28.11#ibcon#about to read 4, iclass 12, count 0 2006.173.20:30:28.11#ibcon#read 4, iclass 12, count 0 2006.173.20:30:28.11#ibcon#about to read 5, iclass 12, count 0 2006.173.20:30:28.11#ibcon#read 5, iclass 12, count 0 2006.173.20:30:28.11#ibcon#about to read 6, iclass 12, count 0 2006.173.20:30:28.11#ibcon#read 6, iclass 12, count 0 2006.173.20:30:28.11#ibcon#end of sib2, iclass 12, count 0 2006.173.20:30:28.11#ibcon#*after write, iclass 12, count 0 2006.173.20:30:28.11#ibcon#*before return 0, iclass 12, count 0 2006.173.20:30:28.11#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.20:30:28.11#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.20:30:28.11#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.20:30:28.11#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.20:30:28.11$vck44/valo=8,884.99 2006.173.20:30:28.12#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.20:30:28.12#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.20:30:28.12#ibcon#ireg 17 cls_cnt 0 2006.173.20:30:28.12#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.20:30:28.12#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.20:30:28.12#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.20:30:28.12#ibcon#enter wrdev, iclass 15, count 0 2006.173.20:30:28.12#ibcon#first serial, iclass 15, count 0 2006.173.20:30:28.12#ibcon#enter sib2, iclass 15, count 0 2006.173.20:30:28.12#ibcon#flushed, iclass 15, count 0 2006.173.20:30:28.12#ibcon#about to write, iclass 15, count 0 2006.173.20:30:28.12#ibcon#wrote, iclass 15, count 0 2006.173.20:30:28.12#ibcon#about to read 3, iclass 15, count 0 2006.173.20:30:28.12#abcon#<5=/06 0.6 1.3 19.961001003.0\r\n> 2006.173.20:30:28.13#ibcon#read 3, iclass 15, count 0 2006.173.20:30:28.13#ibcon#about to read 4, iclass 15, count 0 2006.173.20:30:28.13#ibcon#read 4, iclass 15, count 0 2006.173.20:30:28.13#ibcon#about to read 5, iclass 15, count 0 2006.173.20:30:28.13#ibcon#read 5, iclass 15, count 0 2006.173.20:30:28.13#ibcon#about to read 6, iclass 15, count 0 2006.173.20:30:28.13#ibcon#read 6, iclass 15, count 0 2006.173.20:30:28.13#ibcon#end of sib2, iclass 15, count 0 2006.173.20:30:28.13#ibcon#*mode == 0, iclass 15, count 0 2006.173.20:30:28.13#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.20:30:28.13#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.20:30:28.13#ibcon#*before write, iclass 15, count 0 2006.173.20:30:28.13#ibcon#enter sib2, iclass 15, count 0 2006.173.20:30:28.13#ibcon#flushed, iclass 15, count 0 2006.173.20:30:28.13#ibcon#about to write, iclass 15, count 0 2006.173.20:30:28.13#ibcon#wrote, iclass 15, count 0 2006.173.20:30:28.13#ibcon#about to read 3, iclass 15, count 0 2006.173.20:30:28.14#abcon#{5=INTERFACE CLEAR} 2006.173.20:30:28.17#ibcon#read 3, iclass 15, count 0 2006.173.20:30:28.17#ibcon#about to read 4, iclass 15, count 0 2006.173.20:30:28.17#ibcon#read 4, iclass 15, count 0 2006.173.20:30:28.17#ibcon#about to read 5, iclass 15, count 0 2006.173.20:30:28.17#ibcon#read 5, iclass 15, count 0 2006.173.20:30:28.17#ibcon#about to read 6, iclass 15, count 0 2006.173.20:30:28.17#ibcon#read 6, iclass 15, count 0 2006.173.20:30:28.17#ibcon#end of sib2, iclass 15, count 0 2006.173.20:30:28.17#ibcon#*after write, iclass 15, count 0 2006.173.20:30:28.17#ibcon#*before return 0, iclass 15, count 0 2006.173.20:30:28.17#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.20:30:28.17#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.20:30:28.17#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.20:30:28.17#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.20:30:28.17$vck44/va=8,4 2006.173.20:30:28.18#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.20:30:28.18#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.20:30:28.18#ibcon#ireg 11 cls_cnt 2 2006.173.20:30:28.18#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.20:30:28.20#abcon#[5=S1D000X0/0*\r\n] 2006.173.20:30:28.22#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.20:30:28.22#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.20:30:28.22#ibcon#enter wrdev, iclass 19, count 2 2006.173.20:30:28.22#ibcon#first serial, iclass 19, count 2 2006.173.20:30:28.22#ibcon#enter sib2, iclass 19, count 2 2006.173.20:30:28.22#ibcon#flushed, iclass 19, count 2 2006.173.20:30:28.22#ibcon#about to write, iclass 19, count 2 2006.173.20:30:28.22#ibcon#wrote, iclass 19, count 2 2006.173.20:30:28.22#ibcon#about to read 3, iclass 19, count 2 2006.173.20:30:28.24#ibcon#read 3, iclass 19, count 2 2006.173.20:30:28.24#ibcon#about to read 4, iclass 19, count 2 2006.173.20:30:28.24#ibcon#read 4, iclass 19, count 2 2006.173.20:30:28.24#ibcon#about to read 5, iclass 19, count 2 2006.173.20:30:28.24#ibcon#read 5, iclass 19, count 2 2006.173.20:30:28.24#ibcon#about to read 6, iclass 19, count 2 2006.173.20:30:28.24#ibcon#read 6, iclass 19, count 2 2006.173.20:30:28.24#ibcon#end of sib2, iclass 19, count 2 2006.173.20:30:28.24#ibcon#*mode == 0, iclass 19, count 2 2006.173.20:30:28.24#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.20:30:28.24#ibcon#[25=AT08-04\r\n] 2006.173.20:30:28.24#ibcon#*before write, iclass 19, count 2 2006.173.20:30:28.24#ibcon#enter sib2, iclass 19, count 2 2006.173.20:30:28.24#ibcon#flushed, iclass 19, count 2 2006.173.20:30:28.24#ibcon#about to write, iclass 19, count 2 2006.173.20:30:28.24#ibcon#wrote, iclass 19, count 2 2006.173.20:30:28.24#ibcon#about to read 3, iclass 19, count 2 2006.173.20:30:28.27#ibcon#read 3, iclass 19, count 2 2006.173.20:30:28.27#ibcon#about to read 4, iclass 19, count 2 2006.173.20:30:28.27#ibcon#read 4, iclass 19, count 2 2006.173.20:30:28.27#ibcon#about to read 5, iclass 19, count 2 2006.173.20:30:28.27#ibcon#read 5, iclass 19, count 2 2006.173.20:30:28.27#ibcon#about to read 6, iclass 19, count 2 2006.173.20:30:28.27#ibcon#read 6, iclass 19, count 2 2006.173.20:30:28.27#ibcon#end of sib2, iclass 19, count 2 2006.173.20:30:28.27#ibcon#*after write, iclass 19, count 2 2006.173.20:30:28.27#ibcon#*before return 0, iclass 19, count 2 2006.173.20:30:28.27#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.20:30:28.27#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.20:30:28.27#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.20:30:28.27#ibcon#ireg 7 cls_cnt 0 2006.173.20:30:28.27#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.20:30:28.39#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.20:30:28.39#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.20:30:28.39#ibcon#enter wrdev, iclass 19, count 0 2006.173.20:30:28.39#ibcon#first serial, iclass 19, count 0 2006.173.20:30:28.39#ibcon#enter sib2, iclass 19, count 0 2006.173.20:30:28.39#ibcon#flushed, iclass 19, count 0 2006.173.20:30:28.39#ibcon#about to write, iclass 19, count 0 2006.173.20:30:28.39#ibcon#wrote, iclass 19, count 0 2006.173.20:30:28.39#ibcon#about to read 3, iclass 19, count 0 2006.173.20:30:28.41#ibcon#read 3, iclass 19, count 0 2006.173.20:30:28.41#ibcon#about to read 4, iclass 19, count 0 2006.173.20:30:28.41#ibcon#read 4, iclass 19, count 0 2006.173.20:30:28.41#ibcon#about to read 5, iclass 19, count 0 2006.173.20:30:28.41#ibcon#read 5, iclass 19, count 0 2006.173.20:30:28.41#ibcon#about to read 6, iclass 19, count 0 2006.173.20:30:28.41#ibcon#read 6, iclass 19, count 0 2006.173.20:30:28.41#ibcon#end of sib2, iclass 19, count 0 2006.173.20:30:28.41#ibcon#*mode == 0, iclass 19, count 0 2006.173.20:30:28.41#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.20:30:28.41#ibcon#[25=USB\r\n] 2006.173.20:30:28.41#ibcon#*before write, iclass 19, count 0 2006.173.20:30:28.41#ibcon#enter sib2, iclass 19, count 0 2006.173.20:30:28.41#ibcon#flushed, iclass 19, count 0 2006.173.20:30:28.41#ibcon#about to write, iclass 19, count 0 2006.173.20:30:28.41#ibcon#wrote, iclass 19, count 0 2006.173.20:30:28.41#ibcon#about to read 3, iclass 19, count 0 2006.173.20:30:28.44#ibcon#read 3, iclass 19, count 0 2006.173.20:30:28.44#ibcon#about to read 4, iclass 19, count 0 2006.173.20:30:28.44#ibcon#read 4, iclass 19, count 0 2006.173.20:30:28.44#ibcon#about to read 5, iclass 19, count 0 2006.173.20:30:28.44#ibcon#read 5, iclass 19, count 0 2006.173.20:30:28.44#ibcon#about to read 6, iclass 19, count 0 2006.173.20:30:28.44#ibcon#read 6, iclass 19, count 0 2006.173.20:30:28.44#ibcon#end of sib2, iclass 19, count 0 2006.173.20:30:28.44#ibcon#*after write, iclass 19, count 0 2006.173.20:30:28.44#ibcon#*before return 0, iclass 19, count 0 2006.173.20:30:28.44#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.20:30:28.44#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.20:30:28.44#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.20:30:28.44#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.20:30:28.45$vck44/vblo=1,629.99 2006.173.20:30:28.45#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.20:30:28.45#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.20:30:28.45#ibcon#ireg 17 cls_cnt 0 2006.173.20:30:28.45#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.20:30:28.45#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.20:30:28.45#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.20:30:28.45#ibcon#enter wrdev, iclass 22, count 0 2006.173.20:30:28.45#ibcon#first serial, iclass 22, count 0 2006.173.20:30:28.45#ibcon#enter sib2, iclass 22, count 0 2006.173.20:30:28.45#ibcon#flushed, iclass 22, count 0 2006.173.20:30:28.45#ibcon#about to write, iclass 22, count 0 2006.173.20:30:28.45#ibcon#wrote, iclass 22, count 0 2006.173.20:30:28.45#ibcon#about to read 3, iclass 22, count 0 2006.173.20:30:28.46#ibcon#read 3, iclass 22, count 0 2006.173.20:30:28.46#ibcon#about to read 4, iclass 22, count 0 2006.173.20:30:28.46#ibcon#read 4, iclass 22, count 0 2006.173.20:30:28.46#ibcon#about to read 5, iclass 22, count 0 2006.173.20:30:28.46#ibcon#read 5, iclass 22, count 0 2006.173.20:30:28.46#ibcon#about to read 6, iclass 22, count 0 2006.173.20:30:28.46#ibcon#read 6, iclass 22, count 0 2006.173.20:30:28.46#ibcon#end of sib2, iclass 22, count 0 2006.173.20:30:28.46#ibcon#*mode == 0, iclass 22, count 0 2006.173.20:30:28.46#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.20:30:28.46#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.20:30:28.46#ibcon#*before write, iclass 22, count 0 2006.173.20:30:28.46#ibcon#enter sib2, iclass 22, count 0 2006.173.20:30:28.46#ibcon#flushed, iclass 22, count 0 2006.173.20:30:28.46#ibcon#about to write, iclass 22, count 0 2006.173.20:30:28.46#ibcon#wrote, iclass 22, count 0 2006.173.20:30:28.46#ibcon#about to read 3, iclass 22, count 0 2006.173.20:30:28.50#ibcon#read 3, iclass 22, count 0 2006.173.20:30:28.50#ibcon#about to read 4, iclass 22, count 0 2006.173.20:30:28.50#ibcon#read 4, iclass 22, count 0 2006.173.20:30:28.50#ibcon#about to read 5, iclass 22, count 0 2006.173.20:30:28.50#ibcon#read 5, iclass 22, count 0 2006.173.20:30:28.50#ibcon#about to read 6, iclass 22, count 0 2006.173.20:30:28.50#ibcon#read 6, iclass 22, count 0 2006.173.20:30:28.50#ibcon#end of sib2, iclass 22, count 0 2006.173.20:30:28.50#ibcon#*after write, iclass 22, count 0 2006.173.20:30:28.50#ibcon#*before return 0, iclass 22, count 0 2006.173.20:30:28.50#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.20:30:28.50#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.20:30:28.50#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.20:30:28.50#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.20:30:28.50$vck44/vb=1,4 2006.173.20:30:28.50#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.20:30:28.51#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.20:30:28.51#ibcon#ireg 11 cls_cnt 2 2006.173.20:30:28.51#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.20:30:28.51#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.20:30:28.51#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.20:30:28.51#ibcon#enter wrdev, iclass 24, count 2 2006.173.20:30:28.51#ibcon#first serial, iclass 24, count 2 2006.173.20:30:28.51#ibcon#enter sib2, iclass 24, count 2 2006.173.20:30:28.51#ibcon#flushed, iclass 24, count 2 2006.173.20:30:28.51#ibcon#about to write, iclass 24, count 2 2006.173.20:30:28.51#ibcon#wrote, iclass 24, count 2 2006.173.20:30:28.51#ibcon#about to read 3, iclass 24, count 2 2006.173.20:30:28.52#ibcon#read 3, iclass 24, count 2 2006.173.20:30:28.52#ibcon#about to read 4, iclass 24, count 2 2006.173.20:30:28.52#ibcon#read 4, iclass 24, count 2 2006.173.20:30:28.52#ibcon#about to read 5, iclass 24, count 2 2006.173.20:30:28.52#ibcon#read 5, iclass 24, count 2 2006.173.20:30:28.52#ibcon#about to read 6, iclass 24, count 2 2006.173.20:30:28.52#ibcon#read 6, iclass 24, count 2 2006.173.20:30:28.52#ibcon#end of sib2, iclass 24, count 2 2006.173.20:30:28.52#ibcon#*mode == 0, iclass 24, count 2 2006.173.20:30:28.52#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.20:30:28.52#ibcon#[27=AT01-04\r\n] 2006.173.20:30:28.52#ibcon#*before write, iclass 24, count 2 2006.173.20:30:28.52#ibcon#enter sib2, iclass 24, count 2 2006.173.20:30:28.52#ibcon#flushed, iclass 24, count 2 2006.173.20:30:28.52#ibcon#about to write, iclass 24, count 2 2006.173.20:30:28.52#ibcon#wrote, iclass 24, count 2 2006.173.20:30:28.52#ibcon#about to read 3, iclass 24, count 2 2006.173.20:30:28.55#ibcon#read 3, iclass 24, count 2 2006.173.20:30:28.55#ibcon#about to read 4, iclass 24, count 2 2006.173.20:30:28.55#ibcon#read 4, iclass 24, count 2 2006.173.20:30:28.55#ibcon#about to read 5, iclass 24, count 2 2006.173.20:30:28.55#ibcon#read 5, iclass 24, count 2 2006.173.20:30:28.55#ibcon#about to read 6, iclass 24, count 2 2006.173.20:30:28.55#ibcon#read 6, iclass 24, count 2 2006.173.20:30:28.55#ibcon#end of sib2, iclass 24, count 2 2006.173.20:30:28.55#ibcon#*after write, iclass 24, count 2 2006.173.20:30:28.55#ibcon#*before return 0, iclass 24, count 2 2006.173.20:30:28.55#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.20:30:28.55#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.20:30:28.55#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.20:30:28.55#ibcon#ireg 7 cls_cnt 0 2006.173.20:30:28.55#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.20:30:28.67#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.20:30:28.67#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.20:30:28.67#ibcon#enter wrdev, iclass 24, count 0 2006.173.20:30:28.67#ibcon#first serial, iclass 24, count 0 2006.173.20:30:28.67#ibcon#enter sib2, iclass 24, count 0 2006.173.20:30:28.67#ibcon#flushed, iclass 24, count 0 2006.173.20:30:28.67#ibcon#about to write, iclass 24, count 0 2006.173.20:30:28.67#ibcon#wrote, iclass 24, count 0 2006.173.20:30:28.67#ibcon#about to read 3, iclass 24, count 0 2006.173.20:30:28.69#ibcon#read 3, iclass 24, count 0 2006.173.20:30:28.69#ibcon#about to read 4, iclass 24, count 0 2006.173.20:30:28.69#ibcon#read 4, iclass 24, count 0 2006.173.20:30:28.69#ibcon#about to read 5, iclass 24, count 0 2006.173.20:30:28.69#ibcon#read 5, iclass 24, count 0 2006.173.20:30:28.69#ibcon#about to read 6, iclass 24, count 0 2006.173.20:30:28.69#ibcon#read 6, iclass 24, count 0 2006.173.20:30:28.69#ibcon#end of sib2, iclass 24, count 0 2006.173.20:30:28.69#ibcon#*mode == 0, iclass 24, count 0 2006.173.20:30:28.69#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.20:30:28.69#ibcon#[27=USB\r\n] 2006.173.20:30:28.69#ibcon#*before write, iclass 24, count 0 2006.173.20:30:28.69#ibcon#enter sib2, iclass 24, count 0 2006.173.20:30:28.69#ibcon#flushed, iclass 24, count 0 2006.173.20:30:28.69#ibcon#about to write, iclass 24, count 0 2006.173.20:30:28.69#ibcon#wrote, iclass 24, count 0 2006.173.20:30:28.69#ibcon#about to read 3, iclass 24, count 0 2006.173.20:30:28.72#ibcon#read 3, iclass 24, count 0 2006.173.20:30:28.72#ibcon#about to read 4, iclass 24, count 0 2006.173.20:30:28.72#ibcon#read 4, iclass 24, count 0 2006.173.20:30:28.72#ibcon#about to read 5, iclass 24, count 0 2006.173.20:30:28.72#ibcon#read 5, iclass 24, count 0 2006.173.20:30:28.72#ibcon#about to read 6, iclass 24, count 0 2006.173.20:30:28.72#ibcon#read 6, iclass 24, count 0 2006.173.20:30:28.72#ibcon#end of sib2, iclass 24, count 0 2006.173.20:30:28.72#ibcon#*after write, iclass 24, count 0 2006.173.20:30:28.72#ibcon#*before return 0, iclass 24, count 0 2006.173.20:30:28.72#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.20:30:28.72#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.20:30:28.72#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.20:30:28.72#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.20:30:28.73$vck44/vblo=2,634.99 2006.173.20:30:28.73#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.20:30:28.73#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.20:30:28.73#ibcon#ireg 17 cls_cnt 0 2006.173.20:30:28.73#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.20:30:28.73#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.20:30:28.73#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.20:30:28.73#ibcon#enter wrdev, iclass 26, count 0 2006.173.20:30:28.73#ibcon#first serial, iclass 26, count 0 2006.173.20:30:28.73#ibcon#enter sib2, iclass 26, count 0 2006.173.20:30:28.73#ibcon#flushed, iclass 26, count 0 2006.173.20:30:28.73#ibcon#about to write, iclass 26, count 0 2006.173.20:30:28.73#ibcon#wrote, iclass 26, count 0 2006.173.20:30:28.73#ibcon#about to read 3, iclass 26, count 0 2006.173.20:30:28.74#ibcon#read 3, iclass 26, count 0 2006.173.20:30:28.74#ibcon#about to read 4, iclass 26, count 0 2006.173.20:30:28.74#ibcon#read 4, iclass 26, count 0 2006.173.20:30:28.74#ibcon#about to read 5, iclass 26, count 0 2006.173.20:30:28.74#ibcon#read 5, iclass 26, count 0 2006.173.20:30:28.74#ibcon#about to read 6, iclass 26, count 0 2006.173.20:30:28.74#ibcon#read 6, iclass 26, count 0 2006.173.20:30:28.74#ibcon#end of sib2, iclass 26, count 0 2006.173.20:30:28.74#ibcon#*mode == 0, iclass 26, count 0 2006.173.20:30:28.74#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.20:30:28.74#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.20:30:28.74#ibcon#*before write, iclass 26, count 0 2006.173.20:30:28.74#ibcon#enter sib2, iclass 26, count 0 2006.173.20:30:28.74#ibcon#flushed, iclass 26, count 0 2006.173.20:30:28.74#ibcon#about to write, iclass 26, count 0 2006.173.20:30:28.74#ibcon#wrote, iclass 26, count 0 2006.173.20:30:28.74#ibcon#about to read 3, iclass 26, count 0 2006.173.20:30:28.78#ibcon#read 3, iclass 26, count 0 2006.173.20:30:28.78#ibcon#about to read 4, iclass 26, count 0 2006.173.20:30:28.78#ibcon#read 4, iclass 26, count 0 2006.173.20:30:28.78#ibcon#about to read 5, iclass 26, count 0 2006.173.20:30:28.78#ibcon#read 5, iclass 26, count 0 2006.173.20:30:28.78#ibcon#about to read 6, iclass 26, count 0 2006.173.20:30:28.78#ibcon#read 6, iclass 26, count 0 2006.173.20:30:28.78#ibcon#end of sib2, iclass 26, count 0 2006.173.20:30:28.78#ibcon#*after write, iclass 26, count 0 2006.173.20:30:28.78#ibcon#*before return 0, iclass 26, count 0 2006.173.20:30:28.78#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.20:30:28.78#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.20:30:28.78#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.20:30:28.78#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.20:30:28.78$vck44/vb=2,4 2006.173.20:30:28.78#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.20:30:28.78#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.20:30:28.78#ibcon#ireg 11 cls_cnt 2 2006.173.20:30:28.78#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.20:30:28.84#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.20:30:28.84#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.20:30:28.84#ibcon#enter wrdev, iclass 28, count 2 2006.173.20:30:28.84#ibcon#first serial, iclass 28, count 2 2006.173.20:30:28.84#ibcon#enter sib2, iclass 28, count 2 2006.173.20:30:29.64#ibcon#flushed, iclass 28, count 2 2006.173.20:30:29.64#ibcon#about to write, iclass 28, count 2 2006.173.20:30:29.64#ibcon#wrote, iclass 28, count 2 2006.173.20:30:29.64#ibcon#about to read 3, iclass 28, count 2 2006.173.20:30:29.65#ibcon#read 3, iclass 28, count 2 2006.173.20:30:29.65#ibcon#about to read 4, iclass 28, count 2 2006.173.20:30:29.65#ibcon#read 4, iclass 28, count 2 2006.173.20:30:29.65#ibcon#about to read 5, iclass 28, count 2 2006.173.20:30:29.65#ibcon#read 5, iclass 28, count 2 2006.173.20:30:29.65#ibcon#about to read 6, iclass 28, count 2 2006.173.20:30:29.65#ibcon#read 6, iclass 28, count 2 2006.173.20:30:29.65#ibcon#end of sib2, iclass 28, count 2 2006.173.20:30:29.65#ibcon#*mode == 0, iclass 28, count 2 2006.173.20:30:29.65#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.20:30:29.65#ibcon#[27=AT02-04\r\n] 2006.173.20:30:29.65#ibcon#*before write, iclass 28, count 2 2006.173.20:30:29.65#ibcon#enter sib2, iclass 28, count 2 2006.173.20:30:29.65#ibcon#flushed, iclass 28, count 2 2006.173.20:30:29.65#ibcon#about to write, iclass 28, count 2 2006.173.20:30:29.65#ibcon#wrote, iclass 28, count 2 2006.173.20:30:29.65#ibcon#about to read 3, iclass 28, count 2 2006.173.20:30:29.68#ibcon#read 3, iclass 28, count 2 2006.173.20:30:29.68#ibcon#about to read 4, iclass 28, count 2 2006.173.20:30:29.68#ibcon#read 4, iclass 28, count 2 2006.173.20:30:29.68#ibcon#about to read 5, iclass 28, count 2 2006.173.20:30:29.68#ibcon#read 5, iclass 28, count 2 2006.173.20:30:29.68#ibcon#about to read 6, iclass 28, count 2 2006.173.20:30:29.68#ibcon#read 6, iclass 28, count 2 2006.173.20:30:29.68#ibcon#end of sib2, iclass 28, count 2 2006.173.20:30:29.68#ibcon#*after write, iclass 28, count 2 2006.173.20:30:29.68#ibcon#*before return 0, iclass 28, count 2 2006.173.20:30:29.68#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.20:30:29.68#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.20:30:29.68#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.20:30:29.68#ibcon#ireg 7 cls_cnt 0 2006.173.20:30:29.68#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.20:30:29.80#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.20:30:29.80#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.20:30:29.80#ibcon#enter wrdev, iclass 28, count 0 2006.173.20:30:29.80#ibcon#first serial, iclass 28, count 0 2006.173.20:30:29.80#ibcon#enter sib2, iclass 28, count 0 2006.173.20:30:29.80#ibcon#flushed, iclass 28, count 0 2006.173.20:30:29.80#ibcon#about to write, iclass 28, count 0 2006.173.20:30:29.80#ibcon#wrote, iclass 28, count 0 2006.173.20:30:29.80#ibcon#about to read 3, iclass 28, count 0 2006.173.20:30:29.82#ibcon#read 3, iclass 28, count 0 2006.173.20:30:29.82#ibcon#about to read 4, iclass 28, count 0 2006.173.20:30:29.82#ibcon#read 4, iclass 28, count 0 2006.173.20:30:29.82#ibcon#about to read 5, iclass 28, count 0 2006.173.20:30:29.82#ibcon#read 5, iclass 28, count 0 2006.173.20:30:29.82#ibcon#about to read 6, iclass 28, count 0 2006.173.20:30:29.82#ibcon#read 6, iclass 28, count 0 2006.173.20:30:29.82#ibcon#end of sib2, iclass 28, count 0 2006.173.20:30:29.82#ibcon#*mode == 0, iclass 28, count 0 2006.173.20:30:29.82#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.20:30:29.82#ibcon#[27=USB\r\n] 2006.173.20:30:29.82#ibcon#*before write, iclass 28, count 0 2006.173.20:30:29.82#ibcon#enter sib2, iclass 28, count 0 2006.173.20:30:29.82#ibcon#flushed, iclass 28, count 0 2006.173.20:30:29.82#ibcon#about to write, iclass 28, count 0 2006.173.20:30:29.82#ibcon#wrote, iclass 28, count 0 2006.173.20:30:29.82#ibcon#about to read 3, iclass 28, count 0 2006.173.20:30:29.85#ibcon#read 3, iclass 28, count 0 2006.173.20:30:29.85#ibcon#about to read 4, iclass 28, count 0 2006.173.20:30:29.85#ibcon#read 4, iclass 28, count 0 2006.173.20:30:29.85#ibcon#about to read 5, iclass 28, count 0 2006.173.20:30:29.85#ibcon#read 5, iclass 28, count 0 2006.173.20:30:29.85#ibcon#about to read 6, iclass 28, count 0 2006.173.20:30:29.85#ibcon#read 6, iclass 28, count 0 2006.173.20:30:29.85#ibcon#end of sib2, iclass 28, count 0 2006.173.20:30:29.85#ibcon#*after write, iclass 28, count 0 2006.173.20:30:29.85#ibcon#*before return 0, iclass 28, count 0 2006.173.20:30:29.85#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.20:30:29.85#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.20:30:29.85#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.20:30:29.85#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.20:30:29.86$vck44/vblo=3,649.99 2006.173.20:30:29.86#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.20:30:29.86#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.20:30:29.86#ibcon#ireg 17 cls_cnt 0 2006.173.20:30:29.86#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.20:30:29.86#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.20:30:29.86#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.20:30:29.86#ibcon#enter wrdev, iclass 30, count 0 2006.173.20:30:29.86#ibcon#first serial, iclass 30, count 0 2006.173.20:30:29.86#ibcon#enter sib2, iclass 30, count 0 2006.173.20:30:29.86#ibcon#flushed, iclass 30, count 0 2006.173.20:30:29.86#ibcon#about to write, iclass 30, count 0 2006.173.20:30:29.86#ibcon#wrote, iclass 30, count 0 2006.173.20:30:29.86#ibcon#about to read 3, iclass 30, count 0 2006.173.20:30:29.87#ibcon#read 3, iclass 30, count 0 2006.173.20:30:29.87#ibcon#about to read 4, iclass 30, count 0 2006.173.20:30:29.87#ibcon#read 4, iclass 30, count 0 2006.173.20:30:29.87#ibcon#about to read 5, iclass 30, count 0 2006.173.20:30:29.87#ibcon#read 5, iclass 30, count 0 2006.173.20:30:29.87#ibcon#about to read 6, iclass 30, count 0 2006.173.20:30:29.87#ibcon#read 6, iclass 30, count 0 2006.173.20:30:29.87#ibcon#end of sib2, iclass 30, count 0 2006.173.20:30:29.87#ibcon#*mode == 0, iclass 30, count 0 2006.173.20:30:29.87#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.20:30:29.87#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.20:30:29.87#ibcon#*before write, iclass 30, count 0 2006.173.20:30:29.87#ibcon#enter sib2, iclass 30, count 0 2006.173.20:30:29.87#ibcon#flushed, iclass 30, count 0 2006.173.20:30:29.87#ibcon#about to write, iclass 30, count 0 2006.173.20:30:29.87#ibcon#wrote, iclass 30, count 0 2006.173.20:30:29.87#ibcon#about to read 3, iclass 30, count 0 2006.173.20:30:29.91#ibcon#read 3, iclass 30, count 0 2006.173.20:30:29.91#ibcon#about to read 4, iclass 30, count 0 2006.173.20:30:29.91#ibcon#read 4, iclass 30, count 0 2006.173.20:30:29.91#ibcon#about to read 5, iclass 30, count 0 2006.173.20:30:29.91#ibcon#read 5, iclass 30, count 0 2006.173.20:30:29.91#ibcon#about to read 6, iclass 30, count 0 2006.173.20:30:29.91#ibcon#read 6, iclass 30, count 0 2006.173.20:30:29.91#ibcon#end of sib2, iclass 30, count 0 2006.173.20:30:29.91#ibcon#*after write, iclass 30, count 0 2006.173.20:30:29.91#ibcon#*before return 0, iclass 30, count 0 2006.173.20:30:29.91#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.20:30:29.91#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.20:30:29.91#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.20:30:29.91#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.20:30:29.92$vck44/vb=3,4 2006.173.20:30:29.92#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.173.20:30:29.92#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.173.20:30:29.92#ibcon#ireg 11 cls_cnt 2 2006.173.20:30:29.92#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.20:30:29.96#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.20:30:29.96#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.20:30:29.96#ibcon#enter wrdev, iclass 32, count 2 2006.173.20:30:29.96#ibcon#first serial, iclass 32, count 2 2006.173.20:30:29.96#ibcon#enter sib2, iclass 32, count 2 2006.173.20:30:29.96#ibcon#flushed, iclass 32, count 2 2006.173.20:30:29.96#ibcon#about to write, iclass 32, count 2 2006.173.20:30:29.96#ibcon#wrote, iclass 32, count 2 2006.173.20:30:29.96#ibcon#about to read 3, iclass 32, count 2 2006.173.20:30:29.98#ibcon#read 3, iclass 32, count 2 2006.173.20:30:29.98#ibcon#about to read 4, iclass 32, count 2 2006.173.20:30:29.98#ibcon#read 4, iclass 32, count 2 2006.173.20:30:29.98#ibcon#about to read 5, iclass 32, count 2 2006.173.20:30:29.98#ibcon#read 5, iclass 32, count 2 2006.173.20:30:29.98#ibcon#about to read 6, iclass 32, count 2 2006.173.20:30:29.98#ibcon#read 6, iclass 32, count 2 2006.173.20:30:29.98#ibcon#end of sib2, iclass 32, count 2 2006.173.20:30:29.98#ibcon#*mode == 0, iclass 32, count 2 2006.173.20:30:29.98#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.173.20:30:29.98#ibcon#[27=AT03-04\r\n] 2006.173.20:30:29.98#ibcon#*before write, iclass 32, count 2 2006.173.20:30:29.98#ibcon#enter sib2, iclass 32, count 2 2006.173.20:30:29.98#ibcon#flushed, iclass 32, count 2 2006.173.20:30:29.98#ibcon#about to write, iclass 32, count 2 2006.173.20:30:29.98#ibcon#wrote, iclass 32, count 2 2006.173.20:30:29.98#ibcon#about to read 3, iclass 32, count 2 2006.173.20:30:30.01#ibcon#read 3, iclass 32, count 2 2006.173.20:30:30.01#ibcon#about to read 4, iclass 32, count 2 2006.173.20:30:30.01#ibcon#read 4, iclass 32, count 2 2006.173.20:30:30.01#ibcon#about to read 5, iclass 32, count 2 2006.173.20:30:30.01#ibcon#read 5, iclass 32, count 2 2006.173.20:30:30.01#ibcon#about to read 6, iclass 32, count 2 2006.173.20:30:30.01#ibcon#read 6, iclass 32, count 2 2006.173.20:30:30.01#ibcon#end of sib2, iclass 32, count 2 2006.173.20:30:30.01#ibcon#*after write, iclass 32, count 2 2006.173.20:30:30.01#ibcon#*before return 0, iclass 32, count 2 2006.173.20:30:30.01#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.20:30:30.01#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.173.20:30:30.01#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.173.20:30:30.01#ibcon#ireg 7 cls_cnt 0 2006.173.20:30:30.01#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.20:30:30.13#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.20:30:30.13#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.20:30:30.13#ibcon#enter wrdev, iclass 32, count 0 2006.173.20:30:30.13#ibcon#first serial, iclass 32, count 0 2006.173.20:30:30.13#ibcon#enter sib2, iclass 32, count 0 2006.173.20:30:30.13#ibcon#flushed, iclass 32, count 0 2006.173.20:30:30.13#ibcon#about to write, iclass 32, count 0 2006.173.20:30:30.13#ibcon#wrote, iclass 32, count 0 2006.173.20:30:30.13#ibcon#about to read 3, iclass 32, count 0 2006.173.20:30:30.15#ibcon#read 3, iclass 32, count 0 2006.173.20:30:30.15#ibcon#about to read 4, iclass 32, count 0 2006.173.20:30:30.15#ibcon#read 4, iclass 32, count 0 2006.173.20:30:30.15#ibcon#about to read 5, iclass 32, count 0 2006.173.20:30:30.15#ibcon#read 5, iclass 32, count 0 2006.173.20:30:30.15#ibcon#about to read 6, iclass 32, count 0 2006.173.20:30:30.15#ibcon#read 6, iclass 32, count 0 2006.173.20:30:30.15#ibcon#end of sib2, iclass 32, count 0 2006.173.20:30:30.15#ibcon#*mode == 0, iclass 32, count 0 2006.173.20:30:30.15#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.20:30:30.15#ibcon#[27=USB\r\n] 2006.173.20:30:30.15#ibcon#*before write, iclass 32, count 0 2006.173.20:30:30.15#ibcon#enter sib2, iclass 32, count 0 2006.173.20:30:30.15#ibcon#flushed, iclass 32, count 0 2006.173.20:30:30.15#ibcon#about to write, iclass 32, count 0 2006.173.20:30:30.15#ibcon#wrote, iclass 32, count 0 2006.173.20:30:30.15#ibcon#about to read 3, iclass 32, count 0 2006.173.20:30:30.18#ibcon#read 3, iclass 32, count 0 2006.173.20:30:30.18#ibcon#about to read 4, iclass 32, count 0 2006.173.20:30:30.18#ibcon#read 4, iclass 32, count 0 2006.173.20:30:30.18#ibcon#about to read 5, iclass 32, count 0 2006.173.20:30:30.18#ibcon#read 5, iclass 32, count 0 2006.173.20:30:30.18#ibcon#about to read 6, iclass 32, count 0 2006.173.20:30:30.18#ibcon#read 6, iclass 32, count 0 2006.173.20:30:30.18#ibcon#end of sib2, iclass 32, count 0 2006.173.20:30:30.18#ibcon#*after write, iclass 32, count 0 2006.173.20:30:30.18#ibcon#*before return 0, iclass 32, count 0 2006.173.20:30:30.18#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.20:30:30.18#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.173.20:30:30.18#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.20:30:30.18#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.20:30:30.18$vck44/vblo=4,679.99 2006.173.20:30:30.19#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.20:30:30.19#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.20:30:30.19#ibcon#ireg 17 cls_cnt 0 2006.173.20:30:30.19#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.20:30:30.19#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.20:30:30.19#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.20:30:30.19#ibcon#enter wrdev, iclass 34, count 0 2006.173.20:30:30.19#ibcon#first serial, iclass 34, count 0 2006.173.20:30:30.19#ibcon#enter sib2, iclass 34, count 0 2006.173.20:30:30.19#ibcon#flushed, iclass 34, count 0 2006.173.20:30:30.19#ibcon#about to write, iclass 34, count 0 2006.173.20:30:30.19#ibcon#wrote, iclass 34, count 0 2006.173.20:30:30.19#ibcon#about to read 3, iclass 34, count 0 2006.173.20:30:30.20#ibcon#read 3, iclass 34, count 0 2006.173.20:30:30.20#ibcon#about to read 4, iclass 34, count 0 2006.173.20:30:30.20#ibcon#read 4, iclass 34, count 0 2006.173.20:30:30.20#ibcon#about to read 5, iclass 34, count 0 2006.173.20:30:30.20#ibcon#read 5, iclass 34, count 0 2006.173.20:30:30.20#ibcon#about to read 6, iclass 34, count 0 2006.173.20:30:30.20#ibcon#read 6, iclass 34, count 0 2006.173.20:30:30.20#ibcon#end of sib2, iclass 34, count 0 2006.173.20:30:30.20#ibcon#*mode == 0, iclass 34, count 0 2006.173.20:30:30.20#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.20:30:30.20#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.20:30:30.20#ibcon#*before write, iclass 34, count 0 2006.173.20:30:30.20#ibcon#enter sib2, iclass 34, count 0 2006.173.20:30:30.20#ibcon#flushed, iclass 34, count 0 2006.173.20:30:30.20#ibcon#about to write, iclass 34, count 0 2006.173.20:30:30.20#ibcon#wrote, iclass 34, count 0 2006.173.20:30:30.20#ibcon#about to read 3, iclass 34, count 0 2006.173.20:30:30.24#ibcon#read 3, iclass 34, count 0 2006.173.20:30:30.24#ibcon#about to read 4, iclass 34, count 0 2006.173.20:30:30.24#ibcon#read 4, iclass 34, count 0 2006.173.20:30:30.24#ibcon#about to read 5, iclass 34, count 0 2006.173.20:30:30.24#ibcon#read 5, iclass 34, count 0 2006.173.20:30:30.24#ibcon#about to read 6, iclass 34, count 0 2006.173.20:30:30.24#ibcon#read 6, iclass 34, count 0 2006.173.20:30:30.24#ibcon#end of sib2, iclass 34, count 0 2006.173.20:30:30.24#ibcon#*after write, iclass 34, count 0 2006.173.20:30:30.24#ibcon#*before return 0, iclass 34, count 0 2006.173.20:30:30.24#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.20:30:30.24#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.20:30:30.24#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.20:30:30.24#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.20:30:30.24$vck44/vb=4,4 2006.173.20:30:30.24#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.20:30:30.24#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.20:30:30.24#ibcon#ireg 11 cls_cnt 2 2006.173.20:30:30.24#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.20:30:30.30#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.20:30:30.30#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.20:30:30.30#ibcon#enter wrdev, iclass 36, count 2 2006.173.20:30:30.30#ibcon#first serial, iclass 36, count 2 2006.173.20:30:30.30#ibcon#enter sib2, iclass 36, count 2 2006.173.20:30:30.30#ibcon#flushed, iclass 36, count 2 2006.173.20:30:30.30#ibcon#about to write, iclass 36, count 2 2006.173.20:30:30.30#ibcon#wrote, iclass 36, count 2 2006.173.20:30:30.30#ibcon#about to read 3, iclass 36, count 2 2006.173.20:30:30.32#ibcon#read 3, iclass 36, count 2 2006.173.20:30:30.32#ibcon#about to read 4, iclass 36, count 2 2006.173.20:30:30.32#ibcon#read 4, iclass 36, count 2 2006.173.20:30:30.32#ibcon#about to read 5, iclass 36, count 2 2006.173.20:30:30.32#ibcon#read 5, iclass 36, count 2 2006.173.20:30:30.32#ibcon#about to read 6, iclass 36, count 2 2006.173.20:30:30.32#ibcon#read 6, iclass 36, count 2 2006.173.20:30:30.32#ibcon#end of sib2, iclass 36, count 2 2006.173.20:30:30.32#ibcon#*mode == 0, iclass 36, count 2 2006.173.20:30:30.32#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.20:30:30.32#ibcon#[27=AT04-04\r\n] 2006.173.20:30:30.32#ibcon#*before write, iclass 36, count 2 2006.173.20:30:30.32#ibcon#enter sib2, iclass 36, count 2 2006.173.20:30:30.32#ibcon#flushed, iclass 36, count 2 2006.173.20:30:30.32#ibcon#about to write, iclass 36, count 2 2006.173.20:30:30.32#ibcon#wrote, iclass 36, count 2 2006.173.20:30:30.32#ibcon#about to read 3, iclass 36, count 2 2006.173.20:30:30.35#ibcon#read 3, iclass 36, count 2 2006.173.20:30:30.35#ibcon#about to read 4, iclass 36, count 2 2006.173.20:30:30.35#ibcon#read 4, iclass 36, count 2 2006.173.20:30:30.35#ibcon#about to read 5, iclass 36, count 2 2006.173.20:30:30.35#ibcon#read 5, iclass 36, count 2 2006.173.20:30:30.35#ibcon#about to read 6, iclass 36, count 2 2006.173.20:30:30.35#ibcon#read 6, iclass 36, count 2 2006.173.20:30:30.35#ibcon#end of sib2, iclass 36, count 2 2006.173.20:30:30.35#ibcon#*after write, iclass 36, count 2 2006.173.20:30:30.35#ibcon#*before return 0, iclass 36, count 2 2006.173.20:30:30.35#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.20:30:30.35#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.20:30:30.35#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.20:30:30.35#ibcon#ireg 7 cls_cnt 0 2006.173.20:30:30.35#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.20:30:30.47#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.20:30:30.47#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.20:30:30.47#ibcon#enter wrdev, iclass 36, count 0 2006.173.20:30:30.47#ibcon#first serial, iclass 36, count 0 2006.173.20:30:30.47#ibcon#enter sib2, iclass 36, count 0 2006.173.20:30:30.47#ibcon#flushed, iclass 36, count 0 2006.173.20:30:30.47#ibcon#about to write, iclass 36, count 0 2006.173.20:30:30.47#ibcon#wrote, iclass 36, count 0 2006.173.20:30:30.47#ibcon#about to read 3, iclass 36, count 0 2006.173.20:30:30.49#ibcon#read 3, iclass 36, count 0 2006.173.20:30:30.49#ibcon#about to read 4, iclass 36, count 0 2006.173.20:30:30.49#ibcon#read 4, iclass 36, count 0 2006.173.20:30:30.49#ibcon#about to read 5, iclass 36, count 0 2006.173.20:30:30.49#ibcon#read 5, iclass 36, count 0 2006.173.20:30:30.49#ibcon#about to read 6, iclass 36, count 0 2006.173.20:30:30.49#ibcon#read 6, iclass 36, count 0 2006.173.20:30:30.49#ibcon#end of sib2, iclass 36, count 0 2006.173.20:30:30.49#ibcon#*mode == 0, iclass 36, count 0 2006.173.20:30:30.49#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.20:30:30.49#ibcon#[27=USB\r\n] 2006.173.20:30:30.49#ibcon#*before write, iclass 36, count 0 2006.173.20:30:30.49#ibcon#enter sib2, iclass 36, count 0 2006.173.20:30:30.49#ibcon#flushed, iclass 36, count 0 2006.173.20:30:30.49#ibcon#about to write, iclass 36, count 0 2006.173.20:30:30.49#ibcon#wrote, iclass 36, count 0 2006.173.20:30:30.49#ibcon#about to read 3, iclass 36, count 0 2006.173.20:30:30.52#ibcon#read 3, iclass 36, count 0 2006.173.20:30:30.52#ibcon#about to read 4, iclass 36, count 0 2006.173.20:30:30.52#ibcon#read 4, iclass 36, count 0 2006.173.20:30:30.52#ibcon#about to read 5, iclass 36, count 0 2006.173.20:30:30.52#ibcon#read 5, iclass 36, count 0 2006.173.20:30:30.52#ibcon#about to read 6, iclass 36, count 0 2006.173.20:30:30.52#ibcon#read 6, iclass 36, count 0 2006.173.20:30:30.52#ibcon#end of sib2, iclass 36, count 0 2006.173.20:30:30.52#ibcon#*after write, iclass 36, count 0 2006.173.20:30:30.52#ibcon#*before return 0, iclass 36, count 0 2006.173.20:30:30.52#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.20:30:30.52#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.20:30:30.52#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.20:30:30.52#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.20:30:30.52$vck44/vblo=5,709.99 2006.173.20:30:30.53#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.20:30:30.53#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.20:30:30.53#ibcon#ireg 17 cls_cnt 0 2006.173.20:30:30.53#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.20:30:30.53#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.20:30:30.53#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.20:30:30.53#ibcon#enter wrdev, iclass 38, count 0 2006.173.20:30:30.53#ibcon#first serial, iclass 38, count 0 2006.173.20:30:30.53#ibcon#enter sib2, iclass 38, count 0 2006.173.20:30:30.53#ibcon#flushed, iclass 38, count 0 2006.173.20:30:30.53#ibcon#about to write, iclass 38, count 0 2006.173.20:30:30.53#ibcon#wrote, iclass 38, count 0 2006.173.20:30:30.53#ibcon#about to read 3, iclass 38, count 0 2006.173.20:30:30.54#ibcon#read 3, iclass 38, count 0 2006.173.20:30:30.54#ibcon#about to read 4, iclass 38, count 0 2006.173.20:30:30.54#ibcon#read 4, iclass 38, count 0 2006.173.20:30:30.54#ibcon#about to read 5, iclass 38, count 0 2006.173.20:30:30.54#ibcon#read 5, iclass 38, count 0 2006.173.20:30:30.54#ibcon#about to read 6, iclass 38, count 0 2006.173.20:30:30.54#ibcon#read 6, iclass 38, count 0 2006.173.20:30:30.54#ibcon#end of sib2, iclass 38, count 0 2006.173.20:30:30.54#ibcon#*mode == 0, iclass 38, count 0 2006.173.20:30:30.54#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.20:30:30.54#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.20:30:30.54#ibcon#*before write, iclass 38, count 0 2006.173.20:30:30.54#ibcon#enter sib2, iclass 38, count 0 2006.173.20:30:30.54#ibcon#flushed, iclass 38, count 0 2006.173.20:30:30.54#ibcon#about to write, iclass 38, count 0 2006.173.20:30:30.54#ibcon#wrote, iclass 38, count 0 2006.173.20:30:30.54#ibcon#about to read 3, iclass 38, count 0 2006.173.20:30:30.58#ibcon#read 3, iclass 38, count 0 2006.173.20:30:30.58#ibcon#about to read 4, iclass 38, count 0 2006.173.20:30:30.58#ibcon#read 4, iclass 38, count 0 2006.173.20:30:30.58#ibcon#about to read 5, iclass 38, count 0 2006.173.20:30:30.58#ibcon#read 5, iclass 38, count 0 2006.173.20:30:30.58#ibcon#about to read 6, iclass 38, count 0 2006.173.20:30:30.58#ibcon#read 6, iclass 38, count 0 2006.173.20:30:30.58#ibcon#end of sib2, iclass 38, count 0 2006.173.20:30:30.58#ibcon#*after write, iclass 38, count 0 2006.173.20:30:30.58#ibcon#*before return 0, iclass 38, count 0 2006.173.20:30:30.58#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.20:30:30.58#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.20:30:30.58#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.20:30:30.58#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.20:30:30.58$vck44/vb=5,4 2006.173.20:30:30.58#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.20:30:30.58#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.20:30:30.58#ibcon#ireg 11 cls_cnt 2 2006.173.20:30:30.58#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.20:30:30.64#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.20:30:30.64#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.20:30:30.64#ibcon#enter wrdev, iclass 40, count 2 2006.173.20:30:30.64#ibcon#first serial, iclass 40, count 2 2006.173.20:30:30.64#ibcon#enter sib2, iclass 40, count 2 2006.173.20:30:30.64#ibcon#flushed, iclass 40, count 2 2006.173.20:30:30.64#ibcon#about to write, iclass 40, count 2 2006.173.20:30:30.64#ibcon#wrote, iclass 40, count 2 2006.173.20:30:30.64#ibcon#about to read 3, iclass 40, count 2 2006.173.20:30:30.66#ibcon#read 3, iclass 40, count 2 2006.173.20:30:30.66#ibcon#about to read 4, iclass 40, count 2 2006.173.20:30:30.66#ibcon#read 4, iclass 40, count 2 2006.173.20:30:30.66#ibcon#about to read 5, iclass 40, count 2 2006.173.20:30:30.66#ibcon#read 5, iclass 40, count 2 2006.173.20:30:30.66#ibcon#about to read 6, iclass 40, count 2 2006.173.20:30:30.66#ibcon#read 6, iclass 40, count 2 2006.173.20:30:30.66#ibcon#end of sib2, iclass 40, count 2 2006.173.20:30:30.66#ibcon#*mode == 0, iclass 40, count 2 2006.173.20:30:30.66#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.20:30:30.66#ibcon#[27=AT05-04\r\n] 2006.173.20:30:30.66#ibcon#*before write, iclass 40, count 2 2006.173.20:30:30.66#ibcon#enter sib2, iclass 40, count 2 2006.173.20:30:30.66#ibcon#flushed, iclass 40, count 2 2006.173.20:30:30.66#ibcon#about to write, iclass 40, count 2 2006.173.20:30:30.66#ibcon#wrote, iclass 40, count 2 2006.173.20:30:30.66#ibcon#about to read 3, iclass 40, count 2 2006.173.20:30:30.69#ibcon#read 3, iclass 40, count 2 2006.173.20:30:30.69#ibcon#about to read 4, iclass 40, count 2 2006.173.20:30:30.69#ibcon#read 4, iclass 40, count 2 2006.173.20:30:30.69#ibcon#about to read 5, iclass 40, count 2 2006.173.20:30:30.69#ibcon#read 5, iclass 40, count 2 2006.173.20:30:30.69#ibcon#about to read 6, iclass 40, count 2 2006.173.20:30:30.69#ibcon#read 6, iclass 40, count 2 2006.173.20:30:30.69#ibcon#end of sib2, iclass 40, count 2 2006.173.20:30:30.69#ibcon#*after write, iclass 40, count 2 2006.173.20:30:30.69#ibcon#*before return 0, iclass 40, count 2 2006.173.20:30:30.69#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.20:30:30.69#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.20:30:30.69#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.20:30:30.69#ibcon#ireg 7 cls_cnt 0 2006.173.20:30:30.69#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.20:30:30.81#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.20:30:30.81#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.20:30:30.81#ibcon#enter wrdev, iclass 40, count 0 2006.173.20:30:30.81#ibcon#first serial, iclass 40, count 0 2006.173.20:30:30.81#ibcon#enter sib2, iclass 40, count 0 2006.173.20:30:30.81#ibcon#flushed, iclass 40, count 0 2006.173.20:30:30.81#ibcon#about to write, iclass 40, count 0 2006.173.20:30:30.81#ibcon#wrote, iclass 40, count 0 2006.173.20:30:30.81#ibcon#about to read 3, iclass 40, count 0 2006.173.20:30:30.83#ibcon#read 3, iclass 40, count 0 2006.173.20:30:30.83#ibcon#about to read 4, iclass 40, count 0 2006.173.20:30:30.83#ibcon#read 4, iclass 40, count 0 2006.173.20:30:30.83#ibcon#about to read 5, iclass 40, count 0 2006.173.20:30:30.83#ibcon#read 5, iclass 40, count 0 2006.173.20:30:30.83#ibcon#about to read 6, iclass 40, count 0 2006.173.20:30:30.83#ibcon#read 6, iclass 40, count 0 2006.173.20:30:30.83#ibcon#end of sib2, iclass 40, count 0 2006.173.20:30:30.83#ibcon#*mode == 0, iclass 40, count 0 2006.173.20:30:30.83#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.20:30:30.83#ibcon#[27=USB\r\n] 2006.173.20:30:30.83#ibcon#*before write, iclass 40, count 0 2006.173.20:30:30.83#ibcon#enter sib2, iclass 40, count 0 2006.173.20:30:30.83#ibcon#flushed, iclass 40, count 0 2006.173.20:30:30.83#ibcon#about to write, iclass 40, count 0 2006.173.20:30:30.83#ibcon#wrote, iclass 40, count 0 2006.173.20:30:30.83#ibcon#about to read 3, iclass 40, count 0 2006.173.20:30:30.86#ibcon#read 3, iclass 40, count 0 2006.173.20:30:30.86#ibcon#about to read 4, iclass 40, count 0 2006.173.20:30:30.86#ibcon#read 4, iclass 40, count 0 2006.173.20:30:30.86#ibcon#about to read 5, iclass 40, count 0 2006.173.20:30:30.86#ibcon#read 5, iclass 40, count 0 2006.173.20:30:30.86#ibcon#about to read 6, iclass 40, count 0 2006.173.20:30:30.86#ibcon#read 6, iclass 40, count 0 2006.173.20:30:30.86#ibcon#end of sib2, iclass 40, count 0 2006.173.20:30:30.86#ibcon#*after write, iclass 40, count 0 2006.173.20:30:30.86#ibcon#*before return 0, iclass 40, count 0 2006.173.20:30:30.86#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.20:30:30.86#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.20:30:30.86#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.20:30:30.86#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.20:30:30.87$vck44/vblo=6,719.99 2006.173.20:30:30.87#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.20:30:30.87#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.20:30:30.87#ibcon#ireg 17 cls_cnt 0 2006.173.20:30:30.87#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.20:30:30.87#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.20:30:30.87#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.20:30:30.87#ibcon#enter wrdev, iclass 4, count 0 2006.173.20:30:30.87#ibcon#first serial, iclass 4, count 0 2006.173.20:30:30.87#ibcon#enter sib2, iclass 4, count 0 2006.173.20:30:30.87#ibcon#flushed, iclass 4, count 0 2006.173.20:30:30.87#ibcon#about to write, iclass 4, count 0 2006.173.20:30:30.87#ibcon#wrote, iclass 4, count 0 2006.173.20:30:30.87#ibcon#about to read 3, iclass 4, count 0 2006.173.20:30:30.88#ibcon#read 3, iclass 4, count 0 2006.173.20:30:30.88#ibcon#about to read 4, iclass 4, count 0 2006.173.20:30:30.88#ibcon#read 4, iclass 4, count 0 2006.173.20:30:30.88#ibcon#about to read 5, iclass 4, count 0 2006.173.20:30:30.88#ibcon#read 5, iclass 4, count 0 2006.173.20:30:30.88#ibcon#about to read 6, iclass 4, count 0 2006.173.20:30:30.88#ibcon#read 6, iclass 4, count 0 2006.173.20:30:30.88#ibcon#end of sib2, iclass 4, count 0 2006.173.20:30:30.88#ibcon#*mode == 0, iclass 4, count 0 2006.173.20:30:30.88#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.20:30:30.88#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.20:30:30.88#ibcon#*before write, iclass 4, count 0 2006.173.20:30:30.88#ibcon#enter sib2, iclass 4, count 0 2006.173.20:30:30.88#ibcon#flushed, iclass 4, count 0 2006.173.20:30:30.88#ibcon#about to write, iclass 4, count 0 2006.173.20:30:30.88#ibcon#wrote, iclass 4, count 0 2006.173.20:30:30.88#ibcon#about to read 3, iclass 4, count 0 2006.173.20:30:30.92#ibcon#read 3, iclass 4, count 0 2006.173.20:30:30.92#ibcon#about to read 4, iclass 4, count 0 2006.173.20:30:30.92#ibcon#read 4, iclass 4, count 0 2006.173.20:30:30.92#ibcon#about to read 5, iclass 4, count 0 2006.173.20:30:30.92#ibcon#read 5, iclass 4, count 0 2006.173.20:30:30.92#ibcon#about to read 6, iclass 4, count 0 2006.173.20:30:30.92#ibcon#read 6, iclass 4, count 0 2006.173.20:30:30.92#ibcon#end of sib2, iclass 4, count 0 2006.173.20:30:30.92#ibcon#*after write, iclass 4, count 0 2006.173.20:30:30.92#ibcon#*before return 0, iclass 4, count 0 2006.173.20:30:30.92#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.20:30:30.92#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.20:30:30.92#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.20:30:30.92#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.20:30:30.92$vck44/vb=6,4 2006.173.20:30:30.92#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.20:30:30.92#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.20:30:30.92#ibcon#ireg 11 cls_cnt 2 2006.173.20:30:30.93#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.20:30:30.97#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.20:30:30.97#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.20:30:30.97#ibcon#enter wrdev, iclass 6, count 2 2006.173.20:30:30.97#ibcon#first serial, iclass 6, count 2 2006.173.20:30:30.97#ibcon#enter sib2, iclass 6, count 2 2006.173.20:30:30.97#ibcon#flushed, iclass 6, count 2 2006.173.20:30:30.97#ibcon#about to write, iclass 6, count 2 2006.173.20:30:30.97#ibcon#wrote, iclass 6, count 2 2006.173.20:30:30.97#ibcon#about to read 3, iclass 6, count 2 2006.173.20:30:30.99#ibcon#read 3, iclass 6, count 2 2006.173.20:30:30.99#ibcon#about to read 4, iclass 6, count 2 2006.173.20:30:30.99#ibcon#read 4, iclass 6, count 2 2006.173.20:30:30.99#ibcon#about to read 5, iclass 6, count 2 2006.173.20:30:30.99#ibcon#read 5, iclass 6, count 2 2006.173.20:30:30.99#ibcon#about to read 6, iclass 6, count 2 2006.173.20:30:30.99#ibcon#read 6, iclass 6, count 2 2006.173.20:30:30.99#ibcon#end of sib2, iclass 6, count 2 2006.173.20:30:30.99#ibcon#*mode == 0, iclass 6, count 2 2006.173.20:30:30.99#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.20:30:30.99#ibcon#[27=AT06-04\r\n] 2006.173.20:30:30.99#ibcon#*before write, iclass 6, count 2 2006.173.20:30:30.99#ibcon#enter sib2, iclass 6, count 2 2006.173.20:30:30.99#ibcon#flushed, iclass 6, count 2 2006.173.20:30:30.99#ibcon#about to write, iclass 6, count 2 2006.173.20:30:30.99#ibcon#wrote, iclass 6, count 2 2006.173.20:30:30.99#ibcon#about to read 3, iclass 6, count 2 2006.173.20:30:31.02#ibcon#read 3, iclass 6, count 2 2006.173.20:30:31.02#ibcon#about to read 4, iclass 6, count 2 2006.173.20:30:31.02#ibcon#read 4, iclass 6, count 2 2006.173.20:30:31.02#ibcon#about to read 5, iclass 6, count 2 2006.173.20:30:31.02#ibcon#read 5, iclass 6, count 2 2006.173.20:30:31.02#ibcon#about to read 6, iclass 6, count 2 2006.173.20:30:31.02#ibcon#read 6, iclass 6, count 2 2006.173.20:30:31.02#ibcon#end of sib2, iclass 6, count 2 2006.173.20:30:31.02#ibcon#*after write, iclass 6, count 2 2006.173.20:30:31.02#ibcon#*before return 0, iclass 6, count 2 2006.173.20:30:32.14#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.20:30:32.14#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.20:30:32.14#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.20:30:32.14#ibcon#ireg 7 cls_cnt 0 2006.173.20:30:32.14#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.20:30:32.25#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.20:30:32.25#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.20:30:32.25#ibcon#enter wrdev, iclass 6, count 0 2006.173.20:30:32.25#ibcon#first serial, iclass 6, count 0 2006.173.20:30:32.25#ibcon#enter sib2, iclass 6, count 0 2006.173.20:30:32.25#ibcon#flushed, iclass 6, count 0 2006.173.20:30:32.25#ibcon#about to write, iclass 6, count 0 2006.173.20:30:32.25#ibcon#wrote, iclass 6, count 0 2006.173.20:30:32.25#ibcon#about to read 3, iclass 6, count 0 2006.173.20:30:32.27#ibcon#read 3, iclass 6, count 0 2006.173.20:30:32.27#ibcon#about to read 4, iclass 6, count 0 2006.173.20:30:32.27#ibcon#read 4, iclass 6, count 0 2006.173.20:30:32.27#ibcon#about to read 5, iclass 6, count 0 2006.173.20:30:32.27#ibcon#read 5, iclass 6, count 0 2006.173.20:30:32.27#ibcon#about to read 6, iclass 6, count 0 2006.173.20:30:32.27#ibcon#read 6, iclass 6, count 0 2006.173.20:30:32.27#ibcon#end of sib2, iclass 6, count 0 2006.173.20:30:32.27#ibcon#*mode == 0, iclass 6, count 0 2006.173.20:30:32.27#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.20:30:32.27#ibcon#[27=USB\r\n] 2006.173.20:30:32.27#ibcon#*before write, iclass 6, count 0 2006.173.20:30:32.27#ibcon#enter sib2, iclass 6, count 0 2006.173.20:30:32.27#ibcon#flushed, iclass 6, count 0 2006.173.20:30:32.27#ibcon#about to write, iclass 6, count 0 2006.173.20:30:32.27#ibcon#wrote, iclass 6, count 0 2006.173.20:30:32.27#ibcon#about to read 3, iclass 6, count 0 2006.173.20:30:32.30#ibcon#read 3, iclass 6, count 0 2006.173.20:30:32.30#ibcon#about to read 4, iclass 6, count 0 2006.173.20:30:32.30#ibcon#read 4, iclass 6, count 0 2006.173.20:30:32.30#ibcon#about to read 5, iclass 6, count 0 2006.173.20:30:32.30#ibcon#read 5, iclass 6, count 0 2006.173.20:30:32.30#ibcon#about to read 6, iclass 6, count 0 2006.173.20:30:32.30#ibcon#read 6, iclass 6, count 0 2006.173.20:30:32.30#ibcon#end of sib2, iclass 6, count 0 2006.173.20:30:32.30#ibcon#*after write, iclass 6, count 0 2006.173.20:30:32.30#ibcon#*before return 0, iclass 6, count 0 2006.173.20:30:32.30#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.20:30:32.30#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.20:30:32.30#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.20:30:32.30#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.20:30:32.31$vck44/vblo=7,734.99 2006.173.20:30:32.31#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.20:30:32.31#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.20:30:32.31#ibcon#ireg 17 cls_cnt 0 2006.173.20:30:32.31#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.20:30:32.31#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.20:30:32.31#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.20:30:32.31#ibcon#enter wrdev, iclass 10, count 0 2006.173.20:30:32.31#ibcon#first serial, iclass 10, count 0 2006.173.20:30:32.31#ibcon#enter sib2, iclass 10, count 0 2006.173.20:30:32.31#ibcon#flushed, iclass 10, count 0 2006.173.20:30:32.31#ibcon#about to write, iclass 10, count 0 2006.173.20:30:32.31#ibcon#wrote, iclass 10, count 0 2006.173.20:30:32.31#ibcon#about to read 3, iclass 10, count 0 2006.173.20:30:32.32#ibcon#read 3, iclass 10, count 0 2006.173.20:30:32.32#ibcon#about to read 4, iclass 10, count 0 2006.173.20:30:32.32#ibcon#read 4, iclass 10, count 0 2006.173.20:30:32.32#ibcon#about to read 5, iclass 10, count 0 2006.173.20:30:32.32#ibcon#read 5, iclass 10, count 0 2006.173.20:30:32.32#ibcon#about to read 6, iclass 10, count 0 2006.173.20:30:32.32#ibcon#read 6, iclass 10, count 0 2006.173.20:30:32.32#ibcon#end of sib2, iclass 10, count 0 2006.173.20:30:32.32#ibcon#*mode == 0, iclass 10, count 0 2006.173.20:30:32.32#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.20:30:32.32#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.20:30:32.32#ibcon#*before write, iclass 10, count 0 2006.173.20:30:32.32#ibcon#enter sib2, iclass 10, count 0 2006.173.20:30:32.32#ibcon#flushed, iclass 10, count 0 2006.173.20:30:32.32#ibcon#about to write, iclass 10, count 0 2006.173.20:30:32.32#ibcon#wrote, iclass 10, count 0 2006.173.20:30:32.32#ibcon#about to read 3, iclass 10, count 0 2006.173.20:30:32.36#ibcon#read 3, iclass 10, count 0 2006.173.20:30:32.36#ibcon#about to read 4, iclass 10, count 0 2006.173.20:30:32.36#ibcon#read 4, iclass 10, count 0 2006.173.20:30:32.36#ibcon#about to read 5, iclass 10, count 0 2006.173.20:30:32.36#ibcon#read 5, iclass 10, count 0 2006.173.20:30:32.36#ibcon#about to read 6, iclass 10, count 0 2006.173.20:30:32.36#ibcon#read 6, iclass 10, count 0 2006.173.20:30:32.36#ibcon#end of sib2, iclass 10, count 0 2006.173.20:30:32.36#ibcon#*after write, iclass 10, count 0 2006.173.20:30:32.36#ibcon#*before return 0, iclass 10, count 0 2006.173.20:30:32.36#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.20:30:32.36#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.20:30:32.36#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.20:30:32.36#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.20:30:32.37$vck44/vb=7,4 2006.173.20:30:32.37#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.20:30:32.37#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.20:30:32.37#ibcon#ireg 11 cls_cnt 2 2006.173.20:30:32.37#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.20:30:32.41#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.20:30:32.41#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.20:30:32.41#ibcon#enter wrdev, iclass 12, count 2 2006.173.20:30:32.41#ibcon#first serial, iclass 12, count 2 2006.173.20:30:32.41#ibcon#enter sib2, iclass 12, count 2 2006.173.20:30:32.41#ibcon#flushed, iclass 12, count 2 2006.173.20:30:32.41#ibcon#about to write, iclass 12, count 2 2006.173.20:30:32.41#ibcon#wrote, iclass 12, count 2 2006.173.20:30:32.41#ibcon#about to read 3, iclass 12, count 2 2006.173.20:30:32.43#ibcon#read 3, iclass 12, count 2 2006.173.20:30:32.43#ibcon#about to read 4, iclass 12, count 2 2006.173.20:30:32.43#ibcon#read 4, iclass 12, count 2 2006.173.20:30:32.43#ibcon#about to read 5, iclass 12, count 2 2006.173.20:30:32.43#ibcon#read 5, iclass 12, count 2 2006.173.20:30:32.43#ibcon#about to read 6, iclass 12, count 2 2006.173.20:30:32.43#ibcon#read 6, iclass 12, count 2 2006.173.20:30:32.43#ibcon#end of sib2, iclass 12, count 2 2006.173.20:30:32.43#ibcon#*mode == 0, iclass 12, count 2 2006.173.20:30:32.43#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.20:30:32.43#ibcon#[27=AT07-04\r\n] 2006.173.20:30:32.43#ibcon#*before write, iclass 12, count 2 2006.173.20:30:32.43#ibcon#enter sib2, iclass 12, count 2 2006.173.20:30:32.43#ibcon#flushed, iclass 12, count 2 2006.173.20:30:32.43#ibcon#about to write, iclass 12, count 2 2006.173.20:30:32.43#ibcon#wrote, iclass 12, count 2 2006.173.20:30:32.43#ibcon#about to read 3, iclass 12, count 2 2006.173.20:30:32.46#ibcon#read 3, iclass 12, count 2 2006.173.20:30:32.46#ibcon#about to read 4, iclass 12, count 2 2006.173.20:30:32.46#ibcon#read 4, iclass 12, count 2 2006.173.20:30:32.46#ibcon#about to read 5, iclass 12, count 2 2006.173.20:30:32.46#ibcon#read 5, iclass 12, count 2 2006.173.20:30:32.46#ibcon#about to read 6, iclass 12, count 2 2006.173.20:30:32.46#ibcon#read 6, iclass 12, count 2 2006.173.20:30:32.46#ibcon#end of sib2, iclass 12, count 2 2006.173.20:30:32.46#ibcon#*after write, iclass 12, count 2 2006.173.20:30:32.46#ibcon#*before return 0, iclass 12, count 2 2006.173.20:30:32.46#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.20:30:32.46#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.20:30:32.46#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.20:30:32.46#ibcon#ireg 7 cls_cnt 0 2006.173.20:30:32.46#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.20:30:32.58#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.20:30:32.58#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.20:30:32.58#ibcon#enter wrdev, iclass 12, count 0 2006.173.20:30:32.58#ibcon#first serial, iclass 12, count 0 2006.173.20:30:32.58#ibcon#enter sib2, iclass 12, count 0 2006.173.20:30:32.58#ibcon#flushed, iclass 12, count 0 2006.173.20:30:32.58#ibcon#about to write, iclass 12, count 0 2006.173.20:30:32.58#ibcon#wrote, iclass 12, count 0 2006.173.20:30:32.58#ibcon#about to read 3, iclass 12, count 0 2006.173.20:30:32.60#ibcon#read 3, iclass 12, count 0 2006.173.20:30:32.60#ibcon#about to read 4, iclass 12, count 0 2006.173.20:30:32.60#ibcon#read 4, iclass 12, count 0 2006.173.20:30:32.60#ibcon#about to read 5, iclass 12, count 0 2006.173.20:30:32.60#ibcon#read 5, iclass 12, count 0 2006.173.20:30:32.60#ibcon#about to read 6, iclass 12, count 0 2006.173.20:30:32.60#ibcon#read 6, iclass 12, count 0 2006.173.20:30:32.60#ibcon#end of sib2, iclass 12, count 0 2006.173.20:30:32.60#ibcon#*mode == 0, iclass 12, count 0 2006.173.20:30:32.60#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.20:30:32.60#ibcon#[27=USB\r\n] 2006.173.20:30:32.60#ibcon#*before write, iclass 12, count 0 2006.173.20:30:32.60#ibcon#enter sib2, iclass 12, count 0 2006.173.20:30:32.60#ibcon#flushed, iclass 12, count 0 2006.173.20:30:32.60#ibcon#about to write, iclass 12, count 0 2006.173.20:30:32.60#ibcon#wrote, iclass 12, count 0 2006.173.20:30:32.60#ibcon#about to read 3, iclass 12, count 0 2006.173.20:30:32.63#ibcon#read 3, iclass 12, count 0 2006.173.20:30:32.63#ibcon#about to read 4, iclass 12, count 0 2006.173.20:30:32.63#ibcon#read 4, iclass 12, count 0 2006.173.20:30:32.63#ibcon#about to read 5, iclass 12, count 0 2006.173.20:30:32.63#ibcon#read 5, iclass 12, count 0 2006.173.20:30:32.63#ibcon#about to read 6, iclass 12, count 0 2006.173.20:30:32.63#ibcon#read 6, iclass 12, count 0 2006.173.20:30:32.63#ibcon#end of sib2, iclass 12, count 0 2006.173.20:30:32.63#ibcon#*after write, iclass 12, count 0 2006.173.20:30:32.63#ibcon#*before return 0, iclass 12, count 0 2006.173.20:30:32.63#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.20:30:32.63#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.20:30:32.63#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.20:30:32.63#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.20:30:32.63$vck44/vblo=8,744.99 2006.173.20:30:32.64#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.20:30:32.64#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.20:30:32.64#ibcon#ireg 17 cls_cnt 0 2006.173.20:30:32.64#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.20:30:32.64#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.20:30:32.64#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.20:30:32.64#ibcon#enter wrdev, iclass 14, count 0 2006.173.20:30:32.64#ibcon#first serial, iclass 14, count 0 2006.173.20:30:32.64#ibcon#enter sib2, iclass 14, count 0 2006.173.20:30:32.64#ibcon#flushed, iclass 14, count 0 2006.173.20:30:32.64#ibcon#about to write, iclass 14, count 0 2006.173.20:30:32.64#ibcon#wrote, iclass 14, count 0 2006.173.20:30:32.64#ibcon#about to read 3, iclass 14, count 0 2006.173.20:30:32.65#ibcon#read 3, iclass 14, count 0 2006.173.20:30:32.65#ibcon#about to read 4, iclass 14, count 0 2006.173.20:30:32.65#ibcon#read 4, iclass 14, count 0 2006.173.20:30:32.65#ibcon#about to read 5, iclass 14, count 0 2006.173.20:30:32.65#ibcon#read 5, iclass 14, count 0 2006.173.20:30:32.65#ibcon#about to read 6, iclass 14, count 0 2006.173.20:30:32.65#ibcon#read 6, iclass 14, count 0 2006.173.20:30:32.65#ibcon#end of sib2, iclass 14, count 0 2006.173.20:30:32.65#ibcon#*mode == 0, iclass 14, count 0 2006.173.20:30:32.65#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.20:30:32.65#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.20:30:32.65#ibcon#*before write, iclass 14, count 0 2006.173.20:30:32.65#ibcon#enter sib2, iclass 14, count 0 2006.173.20:30:32.65#ibcon#flushed, iclass 14, count 0 2006.173.20:30:32.65#ibcon#about to write, iclass 14, count 0 2006.173.20:30:32.65#ibcon#wrote, iclass 14, count 0 2006.173.20:30:32.65#ibcon#about to read 3, iclass 14, count 0 2006.173.20:30:32.69#ibcon#read 3, iclass 14, count 0 2006.173.20:30:32.69#ibcon#about to read 4, iclass 14, count 0 2006.173.20:30:32.69#ibcon#read 4, iclass 14, count 0 2006.173.20:30:32.69#ibcon#about to read 5, iclass 14, count 0 2006.173.20:30:32.69#ibcon#read 5, iclass 14, count 0 2006.173.20:30:32.69#ibcon#about to read 6, iclass 14, count 0 2006.173.20:30:32.69#ibcon#read 6, iclass 14, count 0 2006.173.20:30:32.69#ibcon#end of sib2, iclass 14, count 0 2006.173.20:30:32.69#ibcon#*after write, iclass 14, count 0 2006.173.20:30:32.69#ibcon#*before return 0, iclass 14, count 0 2006.173.20:30:32.69#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.20:30:32.69#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.20:30:32.69#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.20:30:32.69#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.20:30:32.69$vck44/vb=8,4 2006.173.20:30:32.69#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.20:30:32.69#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.20:30:32.69#ibcon#ireg 11 cls_cnt 2 2006.173.20:30:32.69#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.20:30:32.75#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.20:30:32.75#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.20:30:32.75#ibcon#enter wrdev, iclass 16, count 2 2006.173.20:30:32.75#ibcon#first serial, iclass 16, count 2 2006.173.20:30:32.75#ibcon#enter sib2, iclass 16, count 2 2006.173.20:30:32.75#ibcon#flushed, iclass 16, count 2 2006.173.20:30:32.75#ibcon#about to write, iclass 16, count 2 2006.173.20:30:32.75#ibcon#wrote, iclass 16, count 2 2006.173.20:30:32.75#ibcon#about to read 3, iclass 16, count 2 2006.173.20:30:32.77#ibcon#read 3, iclass 16, count 2 2006.173.20:30:32.77#ibcon#about to read 4, iclass 16, count 2 2006.173.20:30:32.77#ibcon#read 4, iclass 16, count 2 2006.173.20:30:32.77#ibcon#about to read 5, iclass 16, count 2 2006.173.20:30:32.77#ibcon#read 5, iclass 16, count 2 2006.173.20:30:32.77#ibcon#about to read 6, iclass 16, count 2 2006.173.20:30:32.77#ibcon#read 6, iclass 16, count 2 2006.173.20:30:32.77#ibcon#end of sib2, iclass 16, count 2 2006.173.20:30:32.77#ibcon#*mode == 0, iclass 16, count 2 2006.173.20:30:32.77#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.20:30:32.77#ibcon#[27=AT08-04\r\n] 2006.173.20:30:32.77#ibcon#*before write, iclass 16, count 2 2006.173.20:30:32.77#ibcon#enter sib2, iclass 16, count 2 2006.173.20:30:32.77#ibcon#flushed, iclass 16, count 2 2006.173.20:30:32.77#ibcon#about to write, iclass 16, count 2 2006.173.20:30:32.77#ibcon#wrote, iclass 16, count 2 2006.173.20:30:32.77#ibcon#about to read 3, iclass 16, count 2 2006.173.20:30:32.80#ibcon#read 3, iclass 16, count 2 2006.173.20:30:32.80#ibcon#about to read 4, iclass 16, count 2 2006.173.20:30:32.80#ibcon#read 4, iclass 16, count 2 2006.173.20:30:32.80#ibcon#about to read 5, iclass 16, count 2 2006.173.20:30:32.80#ibcon#read 5, iclass 16, count 2 2006.173.20:30:32.80#ibcon#about to read 6, iclass 16, count 2 2006.173.20:30:32.80#ibcon#read 6, iclass 16, count 2 2006.173.20:30:32.80#ibcon#end of sib2, iclass 16, count 2 2006.173.20:30:32.80#ibcon#*after write, iclass 16, count 2 2006.173.20:30:32.80#ibcon#*before return 0, iclass 16, count 2 2006.173.20:30:32.80#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.20:30:32.80#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.20:30:32.80#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.20:30:32.80#ibcon#ireg 7 cls_cnt 0 2006.173.20:30:32.80#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.20:30:32.92#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.20:30:32.92#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.20:30:32.92#ibcon#enter wrdev, iclass 16, count 0 2006.173.20:30:32.92#ibcon#first serial, iclass 16, count 0 2006.173.20:30:32.92#ibcon#enter sib2, iclass 16, count 0 2006.173.20:30:32.92#ibcon#flushed, iclass 16, count 0 2006.173.20:30:32.92#ibcon#about to write, iclass 16, count 0 2006.173.20:30:32.92#ibcon#wrote, iclass 16, count 0 2006.173.20:30:32.92#ibcon#about to read 3, iclass 16, count 0 2006.173.20:30:32.94#ibcon#read 3, iclass 16, count 0 2006.173.20:30:32.94#ibcon#about to read 4, iclass 16, count 0 2006.173.20:30:32.94#ibcon#read 4, iclass 16, count 0 2006.173.20:30:32.94#ibcon#about to read 5, iclass 16, count 0 2006.173.20:30:32.94#ibcon#read 5, iclass 16, count 0 2006.173.20:30:32.94#ibcon#about to read 6, iclass 16, count 0 2006.173.20:30:32.94#ibcon#read 6, iclass 16, count 0 2006.173.20:30:32.94#ibcon#end of sib2, iclass 16, count 0 2006.173.20:30:32.94#ibcon#*mode == 0, iclass 16, count 0 2006.173.20:30:32.94#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.20:30:32.94#ibcon#[27=USB\r\n] 2006.173.20:30:32.94#ibcon#*before write, iclass 16, count 0 2006.173.20:30:32.94#ibcon#enter sib2, iclass 16, count 0 2006.173.20:30:32.94#ibcon#flushed, iclass 16, count 0 2006.173.20:30:32.94#ibcon#about to write, iclass 16, count 0 2006.173.20:30:32.94#ibcon#wrote, iclass 16, count 0 2006.173.20:30:32.94#ibcon#about to read 3, iclass 16, count 0 2006.173.20:30:32.97#ibcon#read 3, iclass 16, count 0 2006.173.20:30:32.97#ibcon#about to read 4, iclass 16, count 0 2006.173.20:30:32.97#ibcon#read 4, iclass 16, count 0 2006.173.20:30:32.97#ibcon#about to read 5, iclass 16, count 0 2006.173.20:30:32.97#ibcon#read 5, iclass 16, count 0 2006.173.20:30:32.97#ibcon#about to read 6, iclass 16, count 0 2006.173.20:30:32.97#ibcon#read 6, iclass 16, count 0 2006.173.20:30:32.97#ibcon#end of sib2, iclass 16, count 0 2006.173.20:30:32.97#ibcon#*after write, iclass 16, count 0 2006.173.20:30:32.97#ibcon#*before return 0, iclass 16, count 0 2006.173.20:30:32.97#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.20:30:32.97#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.20:30:32.97#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.20:30:32.97#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.20:30:32.97$vck44/vabw=wide 2006.173.20:30:32.98#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.20:30:32.98#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.20:30:32.98#ibcon#ireg 8 cls_cnt 0 2006.173.20:30:32.98#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.20:30:32.98#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.20:30:32.98#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.20:30:32.98#ibcon#enter wrdev, iclass 18, count 0 2006.173.20:30:32.98#ibcon#first serial, iclass 18, count 0 2006.173.20:30:32.98#ibcon#enter sib2, iclass 18, count 0 2006.173.20:30:32.98#ibcon#flushed, iclass 18, count 0 2006.173.20:30:32.98#ibcon#about to write, iclass 18, count 0 2006.173.20:30:32.98#ibcon#wrote, iclass 18, count 0 2006.173.20:30:32.98#ibcon#about to read 3, iclass 18, count 0 2006.173.20:30:32.99#ibcon#read 3, iclass 18, count 0 2006.173.20:30:32.99#ibcon#about to read 4, iclass 18, count 0 2006.173.20:30:32.99#ibcon#read 4, iclass 18, count 0 2006.173.20:30:32.99#ibcon#about to read 5, iclass 18, count 0 2006.173.20:30:32.99#ibcon#read 5, iclass 18, count 0 2006.173.20:30:32.99#ibcon#about to read 6, iclass 18, count 0 2006.173.20:30:32.99#ibcon#read 6, iclass 18, count 0 2006.173.20:30:32.99#ibcon#end of sib2, iclass 18, count 0 2006.173.20:30:32.99#ibcon#*mode == 0, iclass 18, count 0 2006.173.20:30:32.99#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.20:30:32.99#ibcon#[25=BW32\r\n] 2006.173.20:30:32.99#ibcon#*before write, iclass 18, count 0 2006.173.20:30:32.99#ibcon#enter sib2, iclass 18, count 0 2006.173.20:30:32.99#ibcon#flushed, iclass 18, count 0 2006.173.20:30:32.99#ibcon#about to write, iclass 18, count 0 2006.173.20:30:32.99#ibcon#wrote, iclass 18, count 0 2006.173.20:30:32.99#ibcon#about to read 3, iclass 18, count 0 2006.173.20:30:33.02#ibcon#read 3, iclass 18, count 0 2006.173.20:30:33.02#ibcon#about to read 4, iclass 18, count 0 2006.173.20:30:33.02#ibcon#read 4, iclass 18, count 0 2006.173.20:30:33.02#ibcon#about to read 5, iclass 18, count 0 2006.173.20:30:33.02#ibcon#read 5, iclass 18, count 0 2006.173.20:30:33.02#ibcon#about to read 6, iclass 18, count 0 2006.173.20:30:33.02#ibcon#read 6, iclass 18, count 0 2006.173.20:30:33.02#ibcon#end of sib2, iclass 18, count 0 2006.173.20:30:33.02#ibcon#*after write, iclass 18, count 0 2006.173.20:30:33.02#ibcon#*before return 0, iclass 18, count 0 2006.173.20:30:33.02#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.20:30:33.02#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.20:30:33.02#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.20:30:33.02#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.20:30:33.02$vck44/vbbw=wide 2006.173.20:30:33.03#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.20:30:33.03#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.20:30:33.03#ibcon#ireg 8 cls_cnt 0 2006.173.20:30:33.03#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.20:30:33.08#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.20:30:33.08#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.20:30:33.08#ibcon#enter wrdev, iclass 20, count 0 2006.173.20:30:33.08#ibcon#first serial, iclass 20, count 0 2006.173.20:30:33.08#ibcon#enter sib2, iclass 20, count 0 2006.173.20:30:33.08#ibcon#flushed, iclass 20, count 0 2006.173.20:30:33.08#ibcon#about to write, iclass 20, count 0 2006.173.20:30:33.08#ibcon#wrote, iclass 20, count 0 2006.173.20:30:33.08#ibcon#about to read 3, iclass 20, count 0 2006.173.20:30:33.10#ibcon#read 3, iclass 20, count 0 2006.173.20:30:33.10#ibcon#about to read 4, iclass 20, count 0 2006.173.20:30:33.10#ibcon#read 4, iclass 20, count 0 2006.173.20:30:33.10#ibcon#about to read 5, iclass 20, count 0 2006.173.20:30:33.10#ibcon#read 5, iclass 20, count 0 2006.173.20:30:33.10#ibcon#about to read 6, iclass 20, count 0 2006.173.20:30:33.10#ibcon#read 6, iclass 20, count 0 2006.173.20:30:33.10#ibcon#end of sib2, iclass 20, count 0 2006.173.20:30:33.10#ibcon#*mode == 0, iclass 20, count 0 2006.173.20:30:33.10#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.20:30:33.10#ibcon#[27=BW32\r\n] 2006.173.20:30:33.10#ibcon#*before write, iclass 20, count 0 2006.173.20:30:33.10#ibcon#enter sib2, iclass 20, count 0 2006.173.20:30:33.10#ibcon#flushed, iclass 20, count 0 2006.173.20:30:33.10#ibcon#about to write, iclass 20, count 0 2006.173.20:30:33.10#ibcon#wrote, iclass 20, count 0 2006.173.20:30:33.10#ibcon#about to read 3, iclass 20, count 0 2006.173.20:30:33.13#ibcon#read 3, iclass 20, count 0 2006.173.20:30:33.13#ibcon#about to read 4, iclass 20, count 0 2006.173.20:30:33.13#ibcon#read 4, iclass 20, count 0 2006.173.20:30:33.13#ibcon#about to read 5, iclass 20, count 0 2006.173.20:30:33.13#ibcon#read 5, iclass 20, count 0 2006.173.20:30:33.13#ibcon#about to read 6, iclass 20, count 0 2006.173.20:30:33.13#ibcon#read 6, iclass 20, count 0 2006.173.20:30:33.13#ibcon#end of sib2, iclass 20, count 0 2006.173.20:30:33.13#ibcon#*after write, iclass 20, count 0 2006.173.20:30:33.13#ibcon#*before return 0, iclass 20, count 0 2006.173.20:30:33.13#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.20:30:33.13#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.20:30:33.13#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.20:30:33.13#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.20:30:33.13$setupk4/ifdk4 2006.173.20:30:33.14$ifdk4/lo= 2006.173.20:30:33.14$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.20:30:33.14$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.20:30:33.14$ifdk4/patch= 2006.173.20:30:33.14$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.20:30:33.14$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.20:30:33.14$setupk4/!*+20s 2006.173.20:30:38.29#abcon#<5=/06 0.7 1.3 19.961001003.0\r\n> 2006.173.20:30:38.31#abcon#{5=INTERFACE CLEAR} 2006.173.20:30:38.37#abcon#[5=S1D000X0/0*\r\n] 2006.173.20:30:45.14#trakl#Source acquired 2006.173.20:30:45.15#flagr#flagr/antenna,acquired 2006.173.20:30:45.17$setupk4/"tpicd 2006.173.20:30:45.17$setupk4/echo=off 2006.173.20:30:45.17$setupk4/xlog=off 2006.173.20:30:45.17:!2006.173.20:31:10 2006.173.20:31:10.02:preob 2006.173.20:31:11.15/onsource/TRACKING 2006.173.20:31:11.15:!2006.173.20:31:20 2006.173.20:31:20.01:"tape 2006.173.20:31:20.02:"st=record 2006.173.20:31:20.02:data_valid=on 2006.173.20:31:20.02:midob 2006.173.20:31:21.15/onsource/TRACKING 2006.173.20:31:21.15/wx/19.98,1003.0,100 2006.173.20:31:21.32/cable/+6.5166E-03 2006.173.20:31:22.41/va/01,07,usb,yes,38,40 2006.173.20:31:22.41/va/02,06,usb,yes,37,38 2006.173.20:31:22.41/va/03,05,usb,yes,47,49 2006.173.20:31:22.41/va/04,06,usb,yes,38,40 2006.173.20:31:22.41/va/05,04,usb,yes,30,30 2006.173.20:31:22.41/va/06,03,usb,yes,42,42 2006.173.20:31:22.41/va/07,04,usb,yes,34,35 2006.173.20:31:22.41/va/08,04,usb,yes,29,35 2006.173.20:31:22.64/valo/01,524.99,yes,locked 2006.173.20:31:22.64/valo/02,534.99,yes,locked 2006.173.20:31:22.64/valo/03,564.99,yes,locked 2006.173.20:31:22.64/valo/04,624.99,yes,locked 2006.173.20:31:22.64/valo/05,734.99,yes,locked 2006.173.20:31:22.64/valo/06,814.99,yes,locked 2006.173.20:31:22.64/valo/07,864.99,yes,locked 2006.173.20:31:22.64/valo/08,884.99,yes,locked 2006.173.20:31:23.73/vb/01,04,usb,yes,29,32 2006.173.20:31:23.73/vb/02,04,usb,yes,32,35 2006.173.20:31:23.73/vb/03,04,usb,yes,29,32 2006.173.20:31:23.73/vb/04,04,usb,yes,33,32 2006.173.20:31:23.73/vb/05,04,usb,yes,26,28 2006.173.20:31:23.73/vb/06,04,usb,yes,31,27 2006.173.20:31:23.73/vb/07,04,usb,yes,30,30 2006.173.20:31:23.73/vb/08,04,usb,yes,28,31 2006.173.20:31:23.96/vblo/01,629.99,yes,locked 2006.173.20:31:23.96/vblo/02,634.99,yes,locked 2006.173.20:31:23.96/vblo/03,649.99,yes,locked 2006.173.20:31:23.96/vblo/04,679.99,yes,locked 2006.173.20:31:23.96/vblo/05,709.99,yes,locked 2006.173.20:31:23.96/vblo/06,719.99,yes,locked 2006.173.20:31:23.96/vblo/07,734.99,yes,locked 2006.173.20:31:23.96/vblo/08,744.99,yes,locked 2006.173.20:31:24.11/vabw/8 2006.173.20:31:24.26/vbbw/8 2006.173.20:31:24.35/xfe/off,on,14.7 2006.173.20:31:24.74/ifatt/23,28,28,28 2006.173.20:31:25.07/fmout-gps/S +3.89E-07 2006.173.20:31:25.13:!2006.173.20:35:40 2006.173.20:35:40.01:data_valid=off 2006.173.20:35:40.01:"et 2006.173.20:35:40.01:!+3s 2006.173.20:35:43.02:"tape 2006.173.20:35:43.02:postob 2006.173.20:35:43.17/cable/+6.5154E-03 2006.173.20:35:43.17/wx/20.12,1002.9,100 2006.173.20:35:43.23/fmout-gps/S +3.89E-07 2006.173.20:35:43.23:scan_name=173-2036,jd0606,220 2006.173.20:35:43.23:source=0014+813,001708.47,813508.1,2000.0,neutral 2006.173.20:35:45.14#flagr#flagr/antenna,new-source 2006.173.20:35:45.14:checkk5 2006.173.20:35:45.51/chk_autoobs//k5ts1/ autoobs is running! 2006.173.20:35:45.90/chk_autoobs//k5ts2/ autoobs is running! 2006.173.20:35:46.29/chk_autoobs//k5ts3/ autoobs is running! 2006.173.20:35:46.65/chk_autoobs//k5ts4/ autoobs is running! 2006.173.20:35:47.03/chk_obsdata//k5ts1/T1732031??a.dat file size is correct (nominal:1040MB, actual:1036MB). 2006.173.20:35:47.40/chk_obsdata//k5ts2/T1732031??b.dat file size is correct (nominal:1040MB, actual:1036MB). 2006.173.20:35:47.79/chk_obsdata//k5ts3/T1732031??c.dat file size is correct (nominal:1040MB, actual:1036MB). 2006.173.20:35:48.22/chk_obsdata//k5ts4/T1732031??d.dat file size is correct (nominal:1040MB, actual:1036MB). 2006.173.20:35:48.91/k5log//k5ts1_log_newline 2006.173.20:35:49.60/k5log//k5ts2_log_newline 2006.173.20:35:50.31/k5log//k5ts3_log_newline 2006.173.20:35:50.99/k5log//k5ts4_log_newline 2006.173.20:35:51.02/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.20:35:51.02:setupk4=1 2006.173.20:35:51.02$setupk4/echo=on 2006.173.20:35:51.02$setupk4/pcalon 2006.173.20:35:51.02$pcalon/"no phase cal control is implemented here 2006.173.20:35:51.02$setupk4/"tpicd=stop 2006.173.20:35:51.02$setupk4/"rec=synch_on 2006.173.20:35:51.02$setupk4/"rec_mode=128 2006.173.20:35:51.02$setupk4/!* 2006.173.20:35:51.02$setupk4/recpk4 2006.173.20:35:51.02$recpk4/recpatch= 2006.173.20:35:51.02$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.20:35:51.02$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.20:35:51.02$setupk4/vck44 2006.173.20:35:51.02$vck44/valo=1,524.99 2006.173.20:35:51.02#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.20:35:51.02#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.20:35:51.02#ibcon#ireg 17 cls_cnt 0 2006.173.20:35:51.02#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.20:35:51.02#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.20:35:51.02#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.20:35:51.02#ibcon#enter wrdev, iclass 3, count 0 2006.173.20:35:51.02#ibcon#first serial, iclass 3, count 0 2006.173.20:35:51.02#ibcon#enter sib2, iclass 3, count 0 2006.173.20:35:51.02#ibcon#flushed, iclass 3, count 0 2006.173.20:35:51.02#ibcon#about to write, iclass 3, count 0 2006.173.20:35:51.02#ibcon#wrote, iclass 3, count 0 2006.173.20:35:51.02#ibcon#about to read 3, iclass 3, count 0 2006.173.20:35:51.03#ibcon#read 3, iclass 3, count 0 2006.173.20:35:51.03#ibcon#about to read 4, iclass 3, count 0 2006.173.20:35:51.03#ibcon#read 4, iclass 3, count 0 2006.173.20:35:51.03#ibcon#about to read 5, iclass 3, count 0 2006.173.20:35:51.03#ibcon#read 5, iclass 3, count 0 2006.173.20:35:51.03#ibcon#about to read 6, iclass 3, count 0 2006.173.20:35:51.03#ibcon#read 6, iclass 3, count 0 2006.173.20:35:51.03#ibcon#end of sib2, iclass 3, count 0 2006.173.20:35:51.03#ibcon#*mode == 0, iclass 3, count 0 2006.173.20:35:51.03#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.20:35:51.03#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.20:35:51.03#ibcon#*before write, iclass 3, count 0 2006.173.20:35:51.03#ibcon#enter sib2, iclass 3, count 0 2006.173.20:35:51.03#ibcon#flushed, iclass 3, count 0 2006.173.20:35:51.03#ibcon#about to write, iclass 3, count 0 2006.173.20:35:51.03#ibcon#wrote, iclass 3, count 0 2006.173.20:35:51.03#ibcon#about to read 3, iclass 3, count 0 2006.173.20:35:51.08#ibcon#read 3, iclass 3, count 0 2006.173.20:35:51.08#ibcon#about to read 4, iclass 3, count 0 2006.173.20:35:51.08#ibcon#read 4, iclass 3, count 0 2006.173.20:35:51.08#ibcon#about to read 5, iclass 3, count 0 2006.173.20:35:51.08#ibcon#read 5, iclass 3, count 0 2006.173.20:35:51.08#ibcon#about to read 6, iclass 3, count 0 2006.173.20:35:51.08#ibcon#read 6, iclass 3, count 0 2006.173.20:35:51.08#ibcon#end of sib2, iclass 3, count 0 2006.173.20:35:51.08#ibcon#*after write, iclass 3, count 0 2006.173.20:35:51.08#ibcon#*before return 0, iclass 3, count 0 2006.173.20:35:51.08#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.20:35:51.08#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.20:35:51.08#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.20:35:51.08#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.20:35:51.08$vck44/va=1,7 2006.173.20:35:51.08#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.20:35:51.08#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.20:35:51.08#ibcon#ireg 11 cls_cnt 2 2006.173.20:35:51.08#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.20:35:51.08#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.20:35:51.08#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.20:35:51.08#ibcon#enter wrdev, iclass 5, count 2 2006.173.20:35:51.08#ibcon#first serial, iclass 5, count 2 2006.173.20:35:51.08#ibcon#enter sib2, iclass 5, count 2 2006.173.20:35:51.08#ibcon#flushed, iclass 5, count 2 2006.173.20:35:51.08#ibcon#about to write, iclass 5, count 2 2006.173.20:35:51.08#ibcon#wrote, iclass 5, count 2 2006.173.20:35:51.08#ibcon#about to read 3, iclass 5, count 2 2006.173.20:35:51.10#ibcon#read 3, iclass 5, count 2 2006.173.20:35:51.10#ibcon#about to read 4, iclass 5, count 2 2006.173.20:35:51.10#ibcon#read 4, iclass 5, count 2 2006.173.20:35:51.10#ibcon#about to read 5, iclass 5, count 2 2006.173.20:35:51.10#ibcon#read 5, iclass 5, count 2 2006.173.20:35:51.10#ibcon#about to read 6, iclass 5, count 2 2006.173.20:35:51.10#ibcon#read 6, iclass 5, count 2 2006.173.20:35:51.10#ibcon#end of sib2, iclass 5, count 2 2006.173.20:35:51.10#ibcon#*mode == 0, iclass 5, count 2 2006.173.20:35:51.10#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.20:35:51.10#ibcon#[25=AT01-07\r\n] 2006.173.20:35:51.10#ibcon#*before write, iclass 5, count 2 2006.173.20:35:51.10#ibcon#enter sib2, iclass 5, count 2 2006.173.20:35:51.10#ibcon#flushed, iclass 5, count 2 2006.173.20:35:51.10#ibcon#about to write, iclass 5, count 2 2006.173.20:35:51.10#ibcon#wrote, iclass 5, count 2 2006.173.20:35:51.10#ibcon#about to read 3, iclass 5, count 2 2006.173.20:35:51.13#ibcon#read 3, iclass 5, count 2 2006.173.20:35:51.13#ibcon#about to read 4, iclass 5, count 2 2006.173.20:35:51.13#ibcon#read 4, iclass 5, count 2 2006.173.20:35:51.13#ibcon#about to read 5, iclass 5, count 2 2006.173.20:35:51.13#ibcon#read 5, iclass 5, count 2 2006.173.20:35:51.13#ibcon#about to read 6, iclass 5, count 2 2006.173.20:35:51.13#ibcon#read 6, iclass 5, count 2 2006.173.20:35:51.13#ibcon#end of sib2, iclass 5, count 2 2006.173.20:35:51.13#ibcon#*after write, iclass 5, count 2 2006.173.20:35:51.13#ibcon#*before return 0, iclass 5, count 2 2006.173.20:35:51.13#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.20:35:51.13#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.20:35:51.13#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.20:35:51.13#ibcon#ireg 7 cls_cnt 0 2006.173.20:35:51.13#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.20:35:51.25#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.20:35:51.25#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.20:35:51.25#ibcon#enter wrdev, iclass 5, count 0 2006.173.20:35:51.25#ibcon#first serial, iclass 5, count 0 2006.173.20:35:51.25#ibcon#enter sib2, iclass 5, count 0 2006.173.20:35:51.25#ibcon#flushed, iclass 5, count 0 2006.173.20:35:51.25#ibcon#about to write, iclass 5, count 0 2006.173.20:35:51.25#ibcon#wrote, iclass 5, count 0 2006.173.20:35:51.25#ibcon#about to read 3, iclass 5, count 0 2006.173.20:35:51.27#ibcon#read 3, iclass 5, count 0 2006.173.20:35:51.27#ibcon#about to read 4, iclass 5, count 0 2006.173.20:35:51.27#ibcon#read 4, iclass 5, count 0 2006.173.20:35:51.27#ibcon#about to read 5, iclass 5, count 0 2006.173.20:35:51.27#ibcon#read 5, iclass 5, count 0 2006.173.20:35:51.27#ibcon#about to read 6, iclass 5, count 0 2006.173.20:35:51.27#ibcon#read 6, iclass 5, count 0 2006.173.20:35:51.27#ibcon#end of sib2, iclass 5, count 0 2006.173.20:35:51.27#ibcon#*mode == 0, iclass 5, count 0 2006.173.20:35:51.27#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.20:35:51.27#ibcon#[25=USB\r\n] 2006.173.20:35:51.27#ibcon#*before write, iclass 5, count 0 2006.173.20:35:51.27#ibcon#enter sib2, iclass 5, count 0 2006.173.20:35:51.27#ibcon#flushed, iclass 5, count 0 2006.173.20:35:51.27#ibcon#about to write, iclass 5, count 0 2006.173.20:35:51.27#ibcon#wrote, iclass 5, count 0 2006.173.20:35:51.27#ibcon#about to read 3, iclass 5, count 0 2006.173.20:35:51.30#ibcon#read 3, iclass 5, count 0 2006.173.20:35:51.30#ibcon#about to read 4, iclass 5, count 0 2006.173.20:35:51.30#ibcon#read 4, iclass 5, count 0 2006.173.20:35:51.30#ibcon#about to read 5, iclass 5, count 0 2006.173.20:35:51.30#ibcon#read 5, iclass 5, count 0 2006.173.20:35:51.30#ibcon#about to read 6, iclass 5, count 0 2006.173.20:35:51.30#ibcon#read 6, iclass 5, count 0 2006.173.20:35:51.30#ibcon#end of sib2, iclass 5, count 0 2006.173.20:35:51.30#ibcon#*after write, iclass 5, count 0 2006.173.20:35:51.30#ibcon#*before return 0, iclass 5, count 0 2006.173.20:35:51.30#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.20:35:51.30#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.20:35:51.30#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.20:35:51.30#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.20:35:51.30$vck44/valo=2,534.99 2006.173.20:35:51.30#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.20:35:51.30#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.20:35:51.30#ibcon#ireg 17 cls_cnt 0 2006.173.20:35:51.30#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.20:35:51.30#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.20:35:51.30#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.20:35:51.30#ibcon#enter wrdev, iclass 7, count 0 2006.173.20:35:51.30#ibcon#first serial, iclass 7, count 0 2006.173.20:35:51.30#ibcon#enter sib2, iclass 7, count 0 2006.173.20:35:51.30#ibcon#flushed, iclass 7, count 0 2006.173.20:35:51.30#ibcon#about to write, iclass 7, count 0 2006.173.20:35:51.30#ibcon#wrote, iclass 7, count 0 2006.173.20:35:51.30#ibcon#about to read 3, iclass 7, count 0 2006.173.20:35:51.32#ibcon#read 3, iclass 7, count 0 2006.173.20:35:51.32#ibcon#about to read 4, iclass 7, count 0 2006.173.20:35:51.32#ibcon#read 4, iclass 7, count 0 2006.173.20:35:51.32#ibcon#about to read 5, iclass 7, count 0 2006.173.20:35:51.32#ibcon#read 5, iclass 7, count 0 2006.173.20:35:51.32#ibcon#about to read 6, iclass 7, count 0 2006.173.20:35:51.32#ibcon#read 6, iclass 7, count 0 2006.173.20:35:51.32#ibcon#end of sib2, iclass 7, count 0 2006.173.20:35:51.32#ibcon#*mode == 0, iclass 7, count 0 2006.173.20:35:51.32#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.20:35:51.32#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.20:35:51.32#ibcon#*before write, iclass 7, count 0 2006.173.20:35:51.32#ibcon#enter sib2, iclass 7, count 0 2006.173.20:35:51.32#ibcon#flushed, iclass 7, count 0 2006.173.20:35:51.32#ibcon#about to write, iclass 7, count 0 2006.173.20:35:51.32#ibcon#wrote, iclass 7, count 0 2006.173.20:35:51.32#ibcon#about to read 3, iclass 7, count 0 2006.173.20:35:51.36#ibcon#read 3, iclass 7, count 0 2006.173.20:35:51.36#ibcon#about to read 4, iclass 7, count 0 2006.173.20:35:51.36#ibcon#read 4, iclass 7, count 0 2006.173.20:35:51.36#ibcon#about to read 5, iclass 7, count 0 2006.173.20:35:51.36#ibcon#read 5, iclass 7, count 0 2006.173.20:35:51.36#ibcon#about to read 6, iclass 7, count 0 2006.173.20:35:51.36#ibcon#read 6, iclass 7, count 0 2006.173.20:35:51.36#ibcon#end of sib2, iclass 7, count 0 2006.173.20:35:51.36#ibcon#*after write, iclass 7, count 0 2006.173.20:35:51.36#ibcon#*before return 0, iclass 7, count 0 2006.173.20:35:51.36#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.20:35:51.36#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.20:35:51.36#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.20:35:51.36#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.20:35:51.36$vck44/va=2,6 2006.173.20:35:51.36#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.20:35:51.36#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.20:35:51.36#ibcon#ireg 11 cls_cnt 2 2006.173.20:35:51.36#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.20:35:51.42#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.20:35:51.42#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.20:35:51.42#ibcon#enter wrdev, iclass 11, count 2 2006.173.20:35:51.42#ibcon#first serial, iclass 11, count 2 2006.173.20:35:51.42#ibcon#enter sib2, iclass 11, count 2 2006.173.20:35:51.42#ibcon#flushed, iclass 11, count 2 2006.173.20:35:51.42#ibcon#about to write, iclass 11, count 2 2006.173.20:35:51.42#ibcon#wrote, iclass 11, count 2 2006.173.20:35:51.42#ibcon#about to read 3, iclass 11, count 2 2006.173.20:35:51.44#ibcon#read 3, iclass 11, count 2 2006.173.20:35:51.44#ibcon#about to read 4, iclass 11, count 2 2006.173.20:35:51.44#ibcon#read 4, iclass 11, count 2 2006.173.20:35:51.44#ibcon#about to read 5, iclass 11, count 2 2006.173.20:35:51.44#ibcon#read 5, iclass 11, count 2 2006.173.20:35:51.44#ibcon#about to read 6, iclass 11, count 2 2006.173.20:35:51.44#ibcon#read 6, iclass 11, count 2 2006.173.20:35:51.44#ibcon#end of sib2, iclass 11, count 2 2006.173.20:35:51.44#ibcon#*mode == 0, iclass 11, count 2 2006.173.20:35:51.44#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.20:35:51.44#ibcon#[25=AT02-06\r\n] 2006.173.20:35:51.44#ibcon#*before write, iclass 11, count 2 2006.173.20:35:51.44#ibcon#enter sib2, iclass 11, count 2 2006.173.20:35:51.44#ibcon#flushed, iclass 11, count 2 2006.173.20:35:51.44#ibcon#about to write, iclass 11, count 2 2006.173.20:35:51.44#ibcon#wrote, iclass 11, count 2 2006.173.20:35:51.44#ibcon#about to read 3, iclass 11, count 2 2006.173.20:35:51.47#ibcon#read 3, iclass 11, count 2 2006.173.20:35:51.47#ibcon#about to read 4, iclass 11, count 2 2006.173.20:35:51.47#ibcon#read 4, iclass 11, count 2 2006.173.20:35:51.47#ibcon#about to read 5, iclass 11, count 2 2006.173.20:35:51.47#ibcon#read 5, iclass 11, count 2 2006.173.20:35:51.47#ibcon#about to read 6, iclass 11, count 2 2006.173.20:35:51.47#ibcon#read 6, iclass 11, count 2 2006.173.20:35:51.47#ibcon#end of sib2, iclass 11, count 2 2006.173.20:35:51.47#ibcon#*after write, iclass 11, count 2 2006.173.20:35:51.47#ibcon#*before return 0, iclass 11, count 2 2006.173.20:35:51.47#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.20:35:51.47#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.20:35:51.47#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.20:35:51.47#ibcon#ireg 7 cls_cnt 0 2006.173.20:35:51.47#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.20:35:51.59#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.20:35:51.59#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.20:35:51.59#ibcon#enter wrdev, iclass 11, count 0 2006.173.20:35:51.59#ibcon#first serial, iclass 11, count 0 2006.173.20:35:51.59#ibcon#enter sib2, iclass 11, count 0 2006.173.20:35:51.59#ibcon#flushed, iclass 11, count 0 2006.173.20:35:51.59#ibcon#about to write, iclass 11, count 0 2006.173.20:35:51.59#ibcon#wrote, iclass 11, count 0 2006.173.20:35:51.59#ibcon#about to read 3, iclass 11, count 0 2006.173.20:35:51.61#ibcon#read 3, iclass 11, count 0 2006.173.20:35:51.61#ibcon#about to read 4, iclass 11, count 0 2006.173.20:35:51.61#ibcon#read 4, iclass 11, count 0 2006.173.20:35:51.61#ibcon#about to read 5, iclass 11, count 0 2006.173.20:35:51.61#ibcon#read 5, iclass 11, count 0 2006.173.20:35:51.61#ibcon#about to read 6, iclass 11, count 0 2006.173.20:35:51.61#ibcon#read 6, iclass 11, count 0 2006.173.20:35:51.61#ibcon#end of sib2, iclass 11, count 0 2006.173.20:35:51.61#ibcon#*mode == 0, iclass 11, count 0 2006.173.20:35:51.61#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.20:35:51.61#ibcon#[25=USB\r\n] 2006.173.20:35:51.61#ibcon#*before write, iclass 11, count 0 2006.173.20:35:51.61#ibcon#enter sib2, iclass 11, count 0 2006.173.20:35:51.61#ibcon#flushed, iclass 11, count 0 2006.173.20:35:51.61#ibcon#about to write, iclass 11, count 0 2006.173.20:35:51.61#ibcon#wrote, iclass 11, count 0 2006.173.20:35:51.61#ibcon#about to read 3, iclass 11, count 0 2006.173.20:35:51.64#ibcon#read 3, iclass 11, count 0 2006.173.20:35:51.64#ibcon#about to read 4, iclass 11, count 0 2006.173.20:35:51.64#ibcon#read 4, iclass 11, count 0 2006.173.20:35:51.64#ibcon#about to read 5, iclass 11, count 0 2006.173.20:35:51.64#ibcon#read 5, iclass 11, count 0 2006.173.20:35:51.64#ibcon#about to read 6, iclass 11, count 0 2006.173.20:35:51.64#ibcon#read 6, iclass 11, count 0 2006.173.20:35:51.64#ibcon#end of sib2, iclass 11, count 0 2006.173.20:35:51.64#ibcon#*after write, iclass 11, count 0 2006.173.20:35:51.64#ibcon#*before return 0, iclass 11, count 0 2006.173.20:35:51.64#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.20:35:51.64#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.20:35:51.64#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.20:35:51.64#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.20:35:51.64$vck44/valo=3,564.99 2006.173.20:35:51.64#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.20:35:51.64#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.20:35:51.64#ibcon#ireg 17 cls_cnt 0 2006.173.20:35:51.64#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.20:35:51.64#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.20:35:51.64#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.20:35:51.64#ibcon#enter wrdev, iclass 13, count 0 2006.173.20:35:51.64#ibcon#first serial, iclass 13, count 0 2006.173.20:35:51.64#ibcon#enter sib2, iclass 13, count 0 2006.173.20:35:51.64#ibcon#flushed, iclass 13, count 0 2006.173.20:35:51.64#ibcon#about to write, iclass 13, count 0 2006.173.20:35:51.64#ibcon#wrote, iclass 13, count 0 2006.173.20:35:51.64#ibcon#about to read 3, iclass 13, count 0 2006.173.20:35:51.66#ibcon#read 3, iclass 13, count 0 2006.173.20:35:51.66#ibcon#about to read 4, iclass 13, count 0 2006.173.20:35:51.66#ibcon#read 4, iclass 13, count 0 2006.173.20:35:51.66#ibcon#about to read 5, iclass 13, count 0 2006.173.20:35:51.66#ibcon#read 5, iclass 13, count 0 2006.173.20:35:51.66#ibcon#about to read 6, iclass 13, count 0 2006.173.20:35:51.66#ibcon#read 6, iclass 13, count 0 2006.173.20:35:51.66#ibcon#end of sib2, iclass 13, count 0 2006.173.20:35:51.66#ibcon#*mode == 0, iclass 13, count 0 2006.173.20:35:51.66#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.20:35:51.66#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.20:35:51.66#ibcon#*before write, iclass 13, count 0 2006.173.20:35:51.66#ibcon#enter sib2, iclass 13, count 0 2006.173.20:35:51.66#ibcon#flushed, iclass 13, count 0 2006.173.20:35:51.66#ibcon#about to write, iclass 13, count 0 2006.173.20:35:51.66#ibcon#wrote, iclass 13, count 0 2006.173.20:35:51.66#ibcon#about to read 3, iclass 13, count 0 2006.173.20:35:51.70#ibcon#read 3, iclass 13, count 0 2006.173.20:35:51.70#ibcon#about to read 4, iclass 13, count 0 2006.173.20:35:51.70#ibcon#read 4, iclass 13, count 0 2006.173.20:35:51.70#ibcon#about to read 5, iclass 13, count 0 2006.173.20:35:51.70#ibcon#read 5, iclass 13, count 0 2006.173.20:35:51.70#ibcon#about to read 6, iclass 13, count 0 2006.173.20:35:51.70#ibcon#read 6, iclass 13, count 0 2006.173.20:35:51.70#ibcon#end of sib2, iclass 13, count 0 2006.173.20:35:51.70#ibcon#*after write, iclass 13, count 0 2006.173.20:35:51.70#ibcon#*before return 0, iclass 13, count 0 2006.173.20:35:51.70#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.20:35:51.70#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.20:35:51.70#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.20:35:51.70#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.20:35:51.70$vck44/va=3,5 2006.173.20:35:51.70#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.20:35:51.70#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.20:35:51.70#ibcon#ireg 11 cls_cnt 2 2006.173.20:35:51.70#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.20:35:51.76#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.20:35:51.76#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.20:35:51.76#ibcon#enter wrdev, iclass 15, count 2 2006.173.20:35:51.76#ibcon#first serial, iclass 15, count 2 2006.173.20:35:51.76#ibcon#enter sib2, iclass 15, count 2 2006.173.20:35:51.76#ibcon#flushed, iclass 15, count 2 2006.173.20:35:51.76#ibcon#about to write, iclass 15, count 2 2006.173.20:35:51.76#ibcon#wrote, iclass 15, count 2 2006.173.20:35:51.76#ibcon#about to read 3, iclass 15, count 2 2006.173.20:35:51.78#ibcon#read 3, iclass 15, count 2 2006.173.20:35:51.78#ibcon#about to read 4, iclass 15, count 2 2006.173.20:35:51.78#ibcon#read 4, iclass 15, count 2 2006.173.20:35:51.78#ibcon#about to read 5, iclass 15, count 2 2006.173.20:35:51.78#ibcon#read 5, iclass 15, count 2 2006.173.20:35:51.78#ibcon#about to read 6, iclass 15, count 2 2006.173.20:35:51.78#ibcon#read 6, iclass 15, count 2 2006.173.20:35:51.78#ibcon#end of sib2, iclass 15, count 2 2006.173.20:35:51.78#ibcon#*mode == 0, iclass 15, count 2 2006.173.20:35:51.78#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.20:35:51.78#ibcon#[25=AT03-05\r\n] 2006.173.20:35:51.78#ibcon#*before write, iclass 15, count 2 2006.173.20:35:51.78#ibcon#enter sib2, iclass 15, count 2 2006.173.20:35:51.78#ibcon#flushed, iclass 15, count 2 2006.173.20:35:51.78#ibcon#about to write, iclass 15, count 2 2006.173.20:35:51.78#ibcon#wrote, iclass 15, count 2 2006.173.20:35:51.78#ibcon#about to read 3, iclass 15, count 2 2006.173.20:35:51.81#ibcon#read 3, iclass 15, count 2 2006.173.20:35:51.81#ibcon#about to read 4, iclass 15, count 2 2006.173.20:35:51.81#ibcon#read 4, iclass 15, count 2 2006.173.20:35:51.81#ibcon#about to read 5, iclass 15, count 2 2006.173.20:35:51.81#ibcon#read 5, iclass 15, count 2 2006.173.20:35:51.81#ibcon#about to read 6, iclass 15, count 2 2006.173.20:35:51.81#ibcon#read 6, iclass 15, count 2 2006.173.20:35:51.81#ibcon#end of sib2, iclass 15, count 2 2006.173.20:35:51.81#ibcon#*after write, iclass 15, count 2 2006.173.20:35:51.81#ibcon#*before return 0, iclass 15, count 2 2006.173.20:35:51.81#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.20:35:51.81#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.20:35:51.81#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.20:35:51.81#ibcon#ireg 7 cls_cnt 0 2006.173.20:35:51.81#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.20:35:51.93#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.20:35:51.93#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.20:35:51.93#ibcon#enter wrdev, iclass 15, count 0 2006.173.20:35:51.93#ibcon#first serial, iclass 15, count 0 2006.173.20:35:51.93#ibcon#enter sib2, iclass 15, count 0 2006.173.20:35:51.93#ibcon#flushed, iclass 15, count 0 2006.173.20:35:51.93#ibcon#about to write, iclass 15, count 0 2006.173.20:35:51.93#ibcon#wrote, iclass 15, count 0 2006.173.20:35:51.93#ibcon#about to read 3, iclass 15, count 0 2006.173.20:35:51.95#ibcon#read 3, iclass 15, count 0 2006.173.20:35:51.95#ibcon#about to read 4, iclass 15, count 0 2006.173.20:35:51.95#ibcon#read 4, iclass 15, count 0 2006.173.20:35:51.95#ibcon#about to read 5, iclass 15, count 0 2006.173.20:35:51.95#ibcon#read 5, iclass 15, count 0 2006.173.20:35:51.95#ibcon#about to read 6, iclass 15, count 0 2006.173.20:35:51.95#ibcon#read 6, iclass 15, count 0 2006.173.20:35:51.95#ibcon#end of sib2, iclass 15, count 0 2006.173.20:35:51.95#ibcon#*mode == 0, iclass 15, count 0 2006.173.20:35:51.95#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.20:35:51.95#ibcon#[25=USB\r\n] 2006.173.20:35:51.95#ibcon#*before write, iclass 15, count 0 2006.173.20:35:51.95#ibcon#enter sib2, iclass 15, count 0 2006.173.20:35:51.95#ibcon#flushed, iclass 15, count 0 2006.173.20:35:51.95#ibcon#about to write, iclass 15, count 0 2006.173.20:35:51.95#ibcon#wrote, iclass 15, count 0 2006.173.20:35:51.95#ibcon#about to read 3, iclass 15, count 0 2006.173.20:35:51.98#ibcon#read 3, iclass 15, count 0 2006.173.20:35:51.98#ibcon#about to read 4, iclass 15, count 0 2006.173.20:35:51.98#ibcon#read 4, iclass 15, count 0 2006.173.20:35:51.98#ibcon#about to read 5, iclass 15, count 0 2006.173.20:35:51.98#ibcon#read 5, iclass 15, count 0 2006.173.20:35:51.98#ibcon#about to read 6, iclass 15, count 0 2006.173.20:35:51.98#ibcon#read 6, iclass 15, count 0 2006.173.20:35:51.98#ibcon#end of sib2, iclass 15, count 0 2006.173.20:35:51.98#ibcon#*after write, iclass 15, count 0 2006.173.20:35:51.98#ibcon#*before return 0, iclass 15, count 0 2006.173.20:35:51.98#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.20:35:51.98#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.20:35:51.98#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.20:35:51.98#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.20:35:51.98$vck44/valo=4,624.99 2006.173.20:35:51.98#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.20:35:51.98#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.20:35:51.98#ibcon#ireg 17 cls_cnt 0 2006.173.20:35:51.98#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.20:35:51.98#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.20:35:51.98#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.20:35:51.98#ibcon#enter wrdev, iclass 17, count 0 2006.173.20:35:51.98#ibcon#first serial, iclass 17, count 0 2006.173.20:35:51.98#ibcon#enter sib2, iclass 17, count 0 2006.173.20:35:51.98#ibcon#flushed, iclass 17, count 0 2006.173.20:35:51.98#ibcon#about to write, iclass 17, count 0 2006.173.20:35:51.98#ibcon#wrote, iclass 17, count 0 2006.173.20:35:51.98#ibcon#about to read 3, iclass 17, count 0 2006.173.20:35:52.00#ibcon#read 3, iclass 17, count 0 2006.173.20:35:52.00#ibcon#about to read 4, iclass 17, count 0 2006.173.20:35:52.00#ibcon#read 4, iclass 17, count 0 2006.173.20:35:52.00#ibcon#about to read 5, iclass 17, count 0 2006.173.20:35:52.00#ibcon#read 5, iclass 17, count 0 2006.173.20:35:52.00#ibcon#about to read 6, iclass 17, count 0 2006.173.20:35:52.00#ibcon#read 6, iclass 17, count 0 2006.173.20:35:52.00#ibcon#end of sib2, iclass 17, count 0 2006.173.20:35:52.00#ibcon#*mode == 0, iclass 17, count 0 2006.173.20:35:52.00#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.20:35:52.00#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.20:35:52.00#ibcon#*before write, iclass 17, count 0 2006.173.20:35:52.00#ibcon#enter sib2, iclass 17, count 0 2006.173.20:35:52.00#ibcon#flushed, iclass 17, count 0 2006.173.20:35:52.00#ibcon#about to write, iclass 17, count 0 2006.173.20:35:52.00#ibcon#wrote, iclass 17, count 0 2006.173.20:35:52.00#ibcon#about to read 3, iclass 17, count 0 2006.173.20:35:52.04#ibcon#read 3, iclass 17, count 0 2006.173.20:35:52.04#ibcon#about to read 4, iclass 17, count 0 2006.173.20:35:52.04#ibcon#read 4, iclass 17, count 0 2006.173.20:35:52.04#ibcon#about to read 5, iclass 17, count 0 2006.173.20:35:52.04#ibcon#read 5, iclass 17, count 0 2006.173.20:35:52.04#ibcon#about to read 6, iclass 17, count 0 2006.173.20:35:52.04#ibcon#read 6, iclass 17, count 0 2006.173.20:35:52.04#ibcon#end of sib2, iclass 17, count 0 2006.173.20:35:52.04#ibcon#*after write, iclass 17, count 0 2006.173.20:35:52.04#ibcon#*before return 0, iclass 17, count 0 2006.173.20:35:52.04#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.20:35:52.04#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.20:35:52.04#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.20:35:52.04#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.20:35:52.04$vck44/va=4,6 2006.173.20:35:52.04#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.20:35:52.04#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.20:35:52.04#ibcon#ireg 11 cls_cnt 2 2006.173.20:35:52.04#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.20:35:52.10#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.20:35:52.10#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.20:35:52.10#ibcon#enter wrdev, iclass 19, count 2 2006.173.20:35:52.10#ibcon#first serial, iclass 19, count 2 2006.173.20:35:52.10#ibcon#enter sib2, iclass 19, count 2 2006.173.20:35:52.10#ibcon#flushed, iclass 19, count 2 2006.173.20:35:52.10#ibcon#about to write, iclass 19, count 2 2006.173.20:35:52.10#ibcon#wrote, iclass 19, count 2 2006.173.20:35:52.10#ibcon#about to read 3, iclass 19, count 2 2006.173.20:35:52.12#ibcon#read 3, iclass 19, count 2 2006.173.20:35:52.12#ibcon#about to read 4, iclass 19, count 2 2006.173.20:35:52.12#ibcon#read 4, iclass 19, count 2 2006.173.20:35:52.12#ibcon#about to read 5, iclass 19, count 2 2006.173.20:35:52.12#ibcon#read 5, iclass 19, count 2 2006.173.20:35:52.12#ibcon#about to read 6, iclass 19, count 2 2006.173.20:35:52.12#ibcon#read 6, iclass 19, count 2 2006.173.20:35:52.12#ibcon#end of sib2, iclass 19, count 2 2006.173.20:35:52.12#ibcon#*mode == 0, iclass 19, count 2 2006.173.20:35:52.12#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.20:35:52.12#ibcon#[25=AT04-06\r\n] 2006.173.20:35:52.12#ibcon#*before write, iclass 19, count 2 2006.173.20:35:52.12#ibcon#enter sib2, iclass 19, count 2 2006.173.20:35:52.12#ibcon#flushed, iclass 19, count 2 2006.173.20:35:52.12#ibcon#about to write, iclass 19, count 2 2006.173.20:35:52.12#ibcon#wrote, iclass 19, count 2 2006.173.20:35:52.12#ibcon#about to read 3, iclass 19, count 2 2006.173.20:35:52.15#ibcon#read 3, iclass 19, count 2 2006.173.20:35:52.15#ibcon#about to read 4, iclass 19, count 2 2006.173.20:35:52.15#ibcon#read 4, iclass 19, count 2 2006.173.20:35:52.15#ibcon#about to read 5, iclass 19, count 2 2006.173.20:35:52.15#ibcon#read 5, iclass 19, count 2 2006.173.20:35:52.15#ibcon#about to read 6, iclass 19, count 2 2006.173.20:35:52.15#ibcon#read 6, iclass 19, count 2 2006.173.20:35:52.15#ibcon#end of sib2, iclass 19, count 2 2006.173.20:35:52.15#ibcon#*after write, iclass 19, count 2 2006.173.20:35:52.15#ibcon#*before return 0, iclass 19, count 2 2006.173.20:35:52.15#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.20:35:52.15#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.20:35:52.15#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.20:35:52.15#ibcon#ireg 7 cls_cnt 0 2006.173.20:35:52.15#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.20:35:52.27#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.20:35:52.27#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.20:35:52.27#ibcon#enter wrdev, iclass 19, count 0 2006.173.20:35:52.27#ibcon#first serial, iclass 19, count 0 2006.173.20:35:52.27#ibcon#enter sib2, iclass 19, count 0 2006.173.20:35:52.27#ibcon#flushed, iclass 19, count 0 2006.173.20:35:52.27#ibcon#about to write, iclass 19, count 0 2006.173.20:35:52.27#ibcon#wrote, iclass 19, count 0 2006.173.20:35:52.27#ibcon#about to read 3, iclass 19, count 0 2006.173.20:35:52.29#ibcon#read 3, iclass 19, count 0 2006.173.20:35:52.29#ibcon#about to read 4, iclass 19, count 0 2006.173.20:35:52.29#ibcon#read 4, iclass 19, count 0 2006.173.20:35:52.29#ibcon#about to read 5, iclass 19, count 0 2006.173.20:35:52.29#ibcon#read 5, iclass 19, count 0 2006.173.20:35:52.29#ibcon#about to read 6, iclass 19, count 0 2006.173.20:35:52.29#ibcon#read 6, iclass 19, count 0 2006.173.20:35:52.29#ibcon#end of sib2, iclass 19, count 0 2006.173.20:35:52.29#ibcon#*mode == 0, iclass 19, count 0 2006.173.20:35:52.29#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.20:35:52.29#ibcon#[25=USB\r\n] 2006.173.20:35:52.29#ibcon#*before write, iclass 19, count 0 2006.173.20:35:52.29#ibcon#enter sib2, iclass 19, count 0 2006.173.20:35:52.29#ibcon#flushed, iclass 19, count 0 2006.173.20:35:52.29#ibcon#about to write, iclass 19, count 0 2006.173.20:35:52.29#ibcon#wrote, iclass 19, count 0 2006.173.20:35:52.29#ibcon#about to read 3, iclass 19, count 0 2006.173.20:35:52.32#ibcon#read 3, iclass 19, count 0 2006.173.20:35:52.32#ibcon#about to read 4, iclass 19, count 0 2006.173.20:35:52.32#ibcon#read 4, iclass 19, count 0 2006.173.20:35:52.32#ibcon#about to read 5, iclass 19, count 0 2006.173.20:35:52.32#ibcon#read 5, iclass 19, count 0 2006.173.20:35:52.32#ibcon#about to read 6, iclass 19, count 0 2006.173.20:35:52.32#ibcon#read 6, iclass 19, count 0 2006.173.20:35:52.32#ibcon#end of sib2, iclass 19, count 0 2006.173.20:35:52.32#ibcon#*after write, iclass 19, count 0 2006.173.20:35:52.32#ibcon#*before return 0, iclass 19, count 0 2006.173.20:35:52.32#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.20:35:52.32#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.20:35:52.32#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.20:35:52.32#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.20:35:52.32$vck44/valo=5,734.99 2006.173.20:35:52.32#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.20:35:52.32#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.20:35:52.32#ibcon#ireg 17 cls_cnt 0 2006.173.20:35:52.32#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.20:35:52.32#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.20:35:52.32#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.20:35:52.32#ibcon#enter wrdev, iclass 21, count 0 2006.173.20:35:52.32#ibcon#first serial, iclass 21, count 0 2006.173.20:35:52.32#ibcon#enter sib2, iclass 21, count 0 2006.173.20:35:52.32#ibcon#flushed, iclass 21, count 0 2006.173.20:35:52.32#ibcon#about to write, iclass 21, count 0 2006.173.20:35:52.32#ibcon#wrote, iclass 21, count 0 2006.173.20:35:52.32#ibcon#about to read 3, iclass 21, count 0 2006.173.20:35:52.34#ibcon#read 3, iclass 21, count 0 2006.173.20:35:52.34#ibcon#about to read 4, iclass 21, count 0 2006.173.20:35:52.34#ibcon#read 4, iclass 21, count 0 2006.173.20:35:52.34#ibcon#about to read 5, iclass 21, count 0 2006.173.20:35:52.34#ibcon#read 5, iclass 21, count 0 2006.173.20:35:52.34#ibcon#about to read 6, iclass 21, count 0 2006.173.20:35:52.34#ibcon#read 6, iclass 21, count 0 2006.173.20:35:52.34#ibcon#end of sib2, iclass 21, count 0 2006.173.20:35:52.34#ibcon#*mode == 0, iclass 21, count 0 2006.173.20:35:52.34#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.20:35:52.34#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.20:35:52.34#ibcon#*before write, iclass 21, count 0 2006.173.20:35:52.34#ibcon#enter sib2, iclass 21, count 0 2006.173.20:35:52.34#ibcon#flushed, iclass 21, count 0 2006.173.20:35:52.34#ibcon#about to write, iclass 21, count 0 2006.173.20:35:52.34#ibcon#wrote, iclass 21, count 0 2006.173.20:35:52.34#ibcon#about to read 3, iclass 21, count 0 2006.173.20:35:52.38#ibcon#read 3, iclass 21, count 0 2006.173.20:35:52.38#ibcon#about to read 4, iclass 21, count 0 2006.173.20:35:52.38#ibcon#read 4, iclass 21, count 0 2006.173.20:35:52.38#ibcon#about to read 5, iclass 21, count 0 2006.173.20:35:52.38#ibcon#read 5, iclass 21, count 0 2006.173.20:35:52.38#ibcon#about to read 6, iclass 21, count 0 2006.173.20:35:52.38#ibcon#read 6, iclass 21, count 0 2006.173.20:35:52.38#ibcon#end of sib2, iclass 21, count 0 2006.173.20:35:52.38#ibcon#*after write, iclass 21, count 0 2006.173.20:35:52.38#ibcon#*before return 0, iclass 21, count 0 2006.173.20:35:52.38#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.20:35:52.38#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.20:35:52.38#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.20:35:52.38#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.20:35:52.38$vck44/va=5,4 2006.173.20:35:52.38#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.20:35:52.38#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.20:35:52.38#ibcon#ireg 11 cls_cnt 2 2006.173.20:35:52.38#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.20:35:52.44#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.20:35:52.44#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.20:35:52.44#ibcon#enter wrdev, iclass 23, count 2 2006.173.20:35:52.44#ibcon#first serial, iclass 23, count 2 2006.173.20:35:52.44#ibcon#enter sib2, iclass 23, count 2 2006.173.20:35:52.44#ibcon#flushed, iclass 23, count 2 2006.173.20:35:52.44#ibcon#about to write, iclass 23, count 2 2006.173.20:35:52.44#ibcon#wrote, iclass 23, count 2 2006.173.20:35:52.44#ibcon#about to read 3, iclass 23, count 2 2006.173.20:35:52.46#ibcon#read 3, iclass 23, count 2 2006.173.20:35:52.46#ibcon#about to read 4, iclass 23, count 2 2006.173.20:35:52.46#ibcon#read 4, iclass 23, count 2 2006.173.20:35:52.46#ibcon#about to read 5, iclass 23, count 2 2006.173.20:35:52.46#ibcon#read 5, iclass 23, count 2 2006.173.20:35:52.46#ibcon#about to read 6, iclass 23, count 2 2006.173.20:35:52.46#ibcon#read 6, iclass 23, count 2 2006.173.20:35:52.46#ibcon#end of sib2, iclass 23, count 2 2006.173.20:35:52.46#ibcon#*mode == 0, iclass 23, count 2 2006.173.20:35:52.46#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.20:35:52.46#ibcon#[25=AT05-04\r\n] 2006.173.20:35:52.46#ibcon#*before write, iclass 23, count 2 2006.173.20:35:52.46#ibcon#enter sib2, iclass 23, count 2 2006.173.20:35:52.46#ibcon#flushed, iclass 23, count 2 2006.173.20:35:52.46#ibcon#about to write, iclass 23, count 2 2006.173.20:35:52.46#ibcon#wrote, iclass 23, count 2 2006.173.20:35:52.46#ibcon#about to read 3, iclass 23, count 2 2006.173.20:35:52.49#ibcon#read 3, iclass 23, count 2 2006.173.20:35:52.49#ibcon#about to read 4, iclass 23, count 2 2006.173.20:35:52.49#ibcon#read 4, iclass 23, count 2 2006.173.20:35:52.49#ibcon#about to read 5, iclass 23, count 2 2006.173.20:35:52.49#ibcon#read 5, iclass 23, count 2 2006.173.20:35:52.49#ibcon#about to read 6, iclass 23, count 2 2006.173.20:35:52.49#ibcon#read 6, iclass 23, count 2 2006.173.20:35:52.49#ibcon#end of sib2, iclass 23, count 2 2006.173.20:35:52.49#ibcon#*after write, iclass 23, count 2 2006.173.20:35:52.49#ibcon#*before return 0, iclass 23, count 2 2006.173.20:35:52.49#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.20:35:52.49#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.20:35:52.49#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.20:35:52.49#ibcon#ireg 7 cls_cnt 0 2006.173.20:35:52.49#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.20:35:52.61#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.20:35:52.61#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.20:35:52.61#ibcon#enter wrdev, iclass 23, count 0 2006.173.20:35:52.61#ibcon#first serial, iclass 23, count 0 2006.173.20:35:52.61#ibcon#enter sib2, iclass 23, count 0 2006.173.20:35:52.61#ibcon#flushed, iclass 23, count 0 2006.173.20:35:52.61#ibcon#about to write, iclass 23, count 0 2006.173.20:35:52.61#ibcon#wrote, iclass 23, count 0 2006.173.20:35:52.61#ibcon#about to read 3, iclass 23, count 0 2006.173.20:35:52.63#ibcon#read 3, iclass 23, count 0 2006.173.20:35:52.63#ibcon#about to read 4, iclass 23, count 0 2006.173.20:35:52.63#ibcon#read 4, iclass 23, count 0 2006.173.20:35:52.63#ibcon#about to read 5, iclass 23, count 0 2006.173.20:35:52.63#ibcon#read 5, iclass 23, count 0 2006.173.20:35:52.63#ibcon#about to read 6, iclass 23, count 0 2006.173.20:35:52.63#ibcon#read 6, iclass 23, count 0 2006.173.20:35:52.63#ibcon#end of sib2, iclass 23, count 0 2006.173.20:35:52.63#ibcon#*mode == 0, iclass 23, count 0 2006.173.20:35:52.63#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.20:35:52.63#ibcon#[25=USB\r\n] 2006.173.20:35:52.63#ibcon#*before write, iclass 23, count 0 2006.173.20:35:52.63#ibcon#enter sib2, iclass 23, count 0 2006.173.20:35:52.63#ibcon#flushed, iclass 23, count 0 2006.173.20:35:52.63#ibcon#about to write, iclass 23, count 0 2006.173.20:35:52.63#ibcon#wrote, iclass 23, count 0 2006.173.20:35:52.63#ibcon#about to read 3, iclass 23, count 0 2006.173.20:35:52.66#ibcon#read 3, iclass 23, count 0 2006.173.20:35:52.66#ibcon#about to read 4, iclass 23, count 0 2006.173.20:35:52.66#ibcon#read 4, iclass 23, count 0 2006.173.20:35:52.66#ibcon#about to read 5, iclass 23, count 0 2006.173.20:35:52.66#ibcon#read 5, iclass 23, count 0 2006.173.20:35:52.66#ibcon#about to read 6, iclass 23, count 0 2006.173.20:35:52.66#ibcon#read 6, iclass 23, count 0 2006.173.20:35:52.66#ibcon#end of sib2, iclass 23, count 0 2006.173.20:35:52.66#ibcon#*after write, iclass 23, count 0 2006.173.20:35:52.66#ibcon#*before return 0, iclass 23, count 0 2006.173.20:35:52.66#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.20:35:52.66#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.20:35:52.66#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.20:35:52.66#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.20:35:52.66$vck44/valo=6,814.99 2006.173.20:35:52.66#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.20:35:52.66#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.20:35:52.66#ibcon#ireg 17 cls_cnt 0 2006.173.20:35:52.66#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.20:35:52.66#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.20:35:52.66#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.20:35:52.66#ibcon#enter wrdev, iclass 25, count 0 2006.173.20:35:52.66#ibcon#first serial, iclass 25, count 0 2006.173.20:35:52.66#ibcon#enter sib2, iclass 25, count 0 2006.173.20:35:52.66#ibcon#flushed, iclass 25, count 0 2006.173.20:35:52.66#ibcon#about to write, iclass 25, count 0 2006.173.20:35:52.66#ibcon#wrote, iclass 25, count 0 2006.173.20:35:52.66#ibcon#about to read 3, iclass 25, count 0 2006.173.20:35:53.19#ibcon#read 3, iclass 25, count 0 2006.173.20:35:53.19#ibcon#about to read 4, iclass 25, count 0 2006.173.20:35:53.19#ibcon#read 4, iclass 25, count 0 2006.173.20:35:53.19#ibcon#about to read 5, iclass 25, count 0 2006.173.20:35:53.19#ibcon#read 5, iclass 25, count 0 2006.173.20:35:53.19#ibcon#about to read 6, iclass 25, count 0 2006.173.20:35:53.19#ibcon#read 6, iclass 25, count 0 2006.173.20:35:53.19#ibcon#end of sib2, iclass 25, count 0 2006.173.20:35:53.19#ibcon#*mode == 0, iclass 25, count 0 2006.173.20:35:53.19#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.20:35:53.19#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.20:35:53.19#ibcon#*before write, iclass 25, count 0 2006.173.20:35:53.20#ibcon#enter sib2, iclass 25, count 0 2006.173.20:35:53.20#ibcon#flushed, iclass 25, count 0 2006.173.20:35:53.20#ibcon#about to write, iclass 25, count 0 2006.173.20:35:53.20#ibcon#wrote, iclass 25, count 0 2006.173.20:35:53.20#ibcon#about to read 3, iclass 25, count 0 2006.173.20:35:53.23#ibcon#read 3, iclass 25, count 0 2006.173.20:35:53.23#ibcon#about to read 4, iclass 25, count 0 2006.173.20:35:53.23#ibcon#read 4, iclass 25, count 0 2006.173.20:35:53.23#ibcon#about to read 5, iclass 25, count 0 2006.173.20:35:53.23#ibcon#read 5, iclass 25, count 0 2006.173.20:35:53.23#ibcon#about to read 6, iclass 25, count 0 2006.173.20:35:53.23#ibcon#read 6, iclass 25, count 0 2006.173.20:35:53.23#ibcon#end of sib2, iclass 25, count 0 2006.173.20:35:53.23#ibcon#*after write, iclass 25, count 0 2006.173.20:35:53.23#ibcon#*before return 0, iclass 25, count 0 2006.173.20:35:53.23#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.20:35:53.23#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.20:35:53.23#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.20:35:53.23#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.20:35:53.23$vck44/va=6,3 2006.173.20:35:53.23#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.20:35:53.23#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.20:35:53.23#ibcon#ireg 11 cls_cnt 2 2006.173.20:35:53.23#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.20:35:53.23#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.20:35:53.23#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.20:35:53.23#ibcon#enter wrdev, iclass 27, count 2 2006.173.20:35:53.23#ibcon#first serial, iclass 27, count 2 2006.173.20:35:53.23#ibcon#enter sib2, iclass 27, count 2 2006.173.20:35:53.23#ibcon#flushed, iclass 27, count 2 2006.173.20:35:53.23#ibcon#about to write, iclass 27, count 2 2006.173.20:35:53.23#ibcon#wrote, iclass 27, count 2 2006.173.20:35:53.23#ibcon#about to read 3, iclass 27, count 2 2006.173.20:35:53.25#ibcon#read 3, iclass 27, count 2 2006.173.20:35:53.25#ibcon#about to read 4, iclass 27, count 2 2006.173.20:35:53.25#ibcon#read 4, iclass 27, count 2 2006.173.20:35:53.25#ibcon#about to read 5, iclass 27, count 2 2006.173.20:35:53.25#ibcon#read 5, iclass 27, count 2 2006.173.20:35:53.25#ibcon#about to read 6, iclass 27, count 2 2006.173.20:35:53.25#ibcon#read 6, iclass 27, count 2 2006.173.20:35:53.25#ibcon#end of sib2, iclass 27, count 2 2006.173.20:35:53.25#ibcon#*mode == 0, iclass 27, count 2 2006.173.20:35:53.25#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.20:35:53.25#ibcon#[25=AT06-03\r\n] 2006.173.20:35:53.25#ibcon#*before write, iclass 27, count 2 2006.173.20:35:53.25#ibcon#enter sib2, iclass 27, count 2 2006.173.20:35:53.25#ibcon#flushed, iclass 27, count 2 2006.173.20:35:53.25#ibcon#about to write, iclass 27, count 2 2006.173.20:35:53.25#ibcon#wrote, iclass 27, count 2 2006.173.20:35:53.25#ibcon#about to read 3, iclass 27, count 2 2006.173.20:35:53.28#ibcon#read 3, iclass 27, count 2 2006.173.20:35:53.28#ibcon#about to read 4, iclass 27, count 2 2006.173.20:35:53.28#ibcon#read 4, iclass 27, count 2 2006.173.20:35:53.28#ibcon#about to read 5, iclass 27, count 2 2006.173.20:35:53.28#ibcon#read 5, iclass 27, count 2 2006.173.20:35:53.28#ibcon#about to read 6, iclass 27, count 2 2006.173.20:35:53.28#ibcon#read 6, iclass 27, count 2 2006.173.20:35:53.28#ibcon#end of sib2, iclass 27, count 2 2006.173.20:35:53.28#ibcon#*after write, iclass 27, count 2 2006.173.20:35:53.28#ibcon#*before return 0, iclass 27, count 2 2006.173.20:35:53.28#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.20:35:53.28#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.20:35:53.28#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.20:35:53.28#ibcon#ireg 7 cls_cnt 0 2006.173.20:35:53.28#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.20:35:53.40#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.20:35:53.40#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.20:35:53.40#ibcon#enter wrdev, iclass 27, count 0 2006.173.20:35:53.40#ibcon#first serial, iclass 27, count 0 2006.173.20:35:53.40#ibcon#enter sib2, iclass 27, count 0 2006.173.20:35:53.40#ibcon#flushed, iclass 27, count 0 2006.173.20:35:53.40#ibcon#about to write, iclass 27, count 0 2006.173.20:35:53.40#ibcon#wrote, iclass 27, count 0 2006.173.20:35:53.40#ibcon#about to read 3, iclass 27, count 0 2006.173.20:35:53.42#ibcon#read 3, iclass 27, count 0 2006.173.20:35:53.42#ibcon#about to read 4, iclass 27, count 0 2006.173.20:35:53.42#ibcon#read 4, iclass 27, count 0 2006.173.20:35:53.42#ibcon#about to read 5, iclass 27, count 0 2006.173.20:35:53.42#ibcon#read 5, iclass 27, count 0 2006.173.20:35:53.42#ibcon#about to read 6, iclass 27, count 0 2006.173.20:35:53.42#ibcon#read 6, iclass 27, count 0 2006.173.20:35:53.42#ibcon#end of sib2, iclass 27, count 0 2006.173.20:35:53.42#ibcon#*mode == 0, iclass 27, count 0 2006.173.20:35:53.42#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.20:35:53.42#ibcon#[25=USB\r\n] 2006.173.20:35:53.42#ibcon#*before write, iclass 27, count 0 2006.173.20:35:53.42#ibcon#enter sib2, iclass 27, count 0 2006.173.20:35:53.42#ibcon#flushed, iclass 27, count 0 2006.173.20:35:53.42#ibcon#about to write, iclass 27, count 0 2006.173.20:35:53.42#ibcon#wrote, iclass 27, count 0 2006.173.20:35:53.42#ibcon#about to read 3, iclass 27, count 0 2006.173.20:35:53.45#ibcon#read 3, iclass 27, count 0 2006.173.20:35:53.45#ibcon#about to read 4, iclass 27, count 0 2006.173.20:35:53.45#ibcon#read 4, iclass 27, count 0 2006.173.20:35:53.45#ibcon#about to read 5, iclass 27, count 0 2006.173.20:35:53.45#ibcon#read 5, iclass 27, count 0 2006.173.20:35:53.45#ibcon#about to read 6, iclass 27, count 0 2006.173.20:35:53.45#ibcon#read 6, iclass 27, count 0 2006.173.20:35:53.45#ibcon#end of sib2, iclass 27, count 0 2006.173.20:35:53.45#ibcon#*after write, iclass 27, count 0 2006.173.20:35:53.45#ibcon#*before return 0, iclass 27, count 0 2006.173.20:35:53.45#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.20:35:53.45#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.20:35:53.45#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.20:35:53.45#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.20:35:53.45$vck44/valo=7,864.99 2006.173.20:35:53.45#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.20:35:53.45#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.20:35:53.45#ibcon#ireg 17 cls_cnt 0 2006.173.20:35:53.45#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.20:35:53.45#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.20:35:53.45#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.20:35:53.45#ibcon#enter wrdev, iclass 29, count 0 2006.173.20:35:53.45#ibcon#first serial, iclass 29, count 0 2006.173.20:35:53.45#ibcon#enter sib2, iclass 29, count 0 2006.173.20:35:53.45#ibcon#flushed, iclass 29, count 0 2006.173.20:35:53.45#ibcon#about to write, iclass 29, count 0 2006.173.20:35:53.45#ibcon#wrote, iclass 29, count 0 2006.173.20:35:53.45#ibcon#about to read 3, iclass 29, count 0 2006.173.20:35:53.47#ibcon#read 3, iclass 29, count 0 2006.173.20:35:53.47#ibcon#about to read 4, iclass 29, count 0 2006.173.20:35:53.47#ibcon#read 4, iclass 29, count 0 2006.173.20:35:53.47#ibcon#about to read 5, iclass 29, count 0 2006.173.20:35:53.47#ibcon#read 5, iclass 29, count 0 2006.173.20:35:53.47#ibcon#about to read 6, iclass 29, count 0 2006.173.20:35:53.47#ibcon#read 6, iclass 29, count 0 2006.173.20:35:53.47#ibcon#end of sib2, iclass 29, count 0 2006.173.20:35:53.47#ibcon#*mode == 0, iclass 29, count 0 2006.173.20:35:53.47#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.20:35:53.47#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.20:35:53.47#ibcon#*before write, iclass 29, count 0 2006.173.20:35:53.47#ibcon#enter sib2, iclass 29, count 0 2006.173.20:35:53.47#ibcon#flushed, iclass 29, count 0 2006.173.20:35:53.47#ibcon#about to write, iclass 29, count 0 2006.173.20:35:53.47#ibcon#wrote, iclass 29, count 0 2006.173.20:35:53.47#ibcon#about to read 3, iclass 29, count 0 2006.173.20:35:53.51#ibcon#read 3, iclass 29, count 0 2006.173.20:35:53.51#ibcon#about to read 4, iclass 29, count 0 2006.173.20:35:53.51#ibcon#read 4, iclass 29, count 0 2006.173.20:35:53.51#ibcon#about to read 5, iclass 29, count 0 2006.173.20:35:53.51#ibcon#read 5, iclass 29, count 0 2006.173.20:35:53.51#ibcon#about to read 6, iclass 29, count 0 2006.173.20:35:53.51#ibcon#read 6, iclass 29, count 0 2006.173.20:35:53.51#ibcon#end of sib2, iclass 29, count 0 2006.173.20:35:53.51#ibcon#*after write, iclass 29, count 0 2006.173.20:35:53.51#ibcon#*before return 0, iclass 29, count 0 2006.173.20:35:53.51#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.20:35:53.51#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.20:35:53.51#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.20:35:53.51#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.20:35:53.51$vck44/va=7,4 2006.173.20:35:53.51#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.20:35:53.51#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.20:35:53.51#ibcon#ireg 11 cls_cnt 2 2006.173.20:35:53.51#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.20:35:53.57#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.20:35:53.57#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.20:35:53.57#ibcon#enter wrdev, iclass 31, count 2 2006.173.20:35:53.57#ibcon#first serial, iclass 31, count 2 2006.173.20:35:53.57#ibcon#enter sib2, iclass 31, count 2 2006.173.20:35:53.57#ibcon#flushed, iclass 31, count 2 2006.173.20:35:53.57#ibcon#about to write, iclass 31, count 2 2006.173.20:35:53.57#ibcon#wrote, iclass 31, count 2 2006.173.20:35:53.57#ibcon#about to read 3, iclass 31, count 2 2006.173.20:35:53.59#ibcon#read 3, iclass 31, count 2 2006.173.20:35:53.59#ibcon#about to read 4, iclass 31, count 2 2006.173.20:35:53.59#ibcon#read 4, iclass 31, count 2 2006.173.20:35:53.59#ibcon#about to read 5, iclass 31, count 2 2006.173.20:35:53.59#ibcon#read 5, iclass 31, count 2 2006.173.20:35:53.59#ibcon#about to read 6, iclass 31, count 2 2006.173.20:35:53.59#ibcon#read 6, iclass 31, count 2 2006.173.20:35:53.59#ibcon#end of sib2, iclass 31, count 2 2006.173.20:35:53.59#ibcon#*mode == 0, iclass 31, count 2 2006.173.20:35:53.59#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.20:35:53.59#ibcon#[25=AT07-04\r\n] 2006.173.20:35:53.59#ibcon#*before write, iclass 31, count 2 2006.173.20:35:53.59#ibcon#enter sib2, iclass 31, count 2 2006.173.20:35:53.59#ibcon#flushed, iclass 31, count 2 2006.173.20:35:53.59#ibcon#about to write, iclass 31, count 2 2006.173.20:35:53.59#ibcon#wrote, iclass 31, count 2 2006.173.20:35:53.59#ibcon#about to read 3, iclass 31, count 2 2006.173.20:35:53.62#ibcon#read 3, iclass 31, count 2 2006.173.20:35:53.62#ibcon#about to read 4, iclass 31, count 2 2006.173.20:35:53.62#ibcon#read 4, iclass 31, count 2 2006.173.20:35:53.62#ibcon#about to read 5, iclass 31, count 2 2006.173.20:35:53.62#ibcon#read 5, iclass 31, count 2 2006.173.20:35:53.62#ibcon#about to read 6, iclass 31, count 2 2006.173.20:35:53.62#ibcon#read 6, iclass 31, count 2 2006.173.20:35:53.62#ibcon#end of sib2, iclass 31, count 2 2006.173.20:35:53.62#ibcon#*after write, iclass 31, count 2 2006.173.20:35:53.62#ibcon#*before return 0, iclass 31, count 2 2006.173.20:35:53.62#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.20:35:53.62#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.20:35:53.62#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.20:35:53.62#ibcon#ireg 7 cls_cnt 0 2006.173.20:35:53.62#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.20:35:53.65#abcon#<5=/06 0.8 1.3 20.141001002.9\r\n> 2006.173.20:35:53.67#abcon#{5=INTERFACE CLEAR} 2006.173.20:35:53.73#abcon#[5=S1D000X0/0*\r\n] 2006.173.20:35:53.74#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.20:35:53.74#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.20:35:53.74#ibcon#enter wrdev, iclass 31, count 0 2006.173.20:35:53.74#ibcon#first serial, iclass 31, count 0 2006.173.20:35:53.74#ibcon#enter sib2, iclass 31, count 0 2006.173.20:35:53.74#ibcon#flushed, iclass 31, count 0 2006.173.20:35:53.74#ibcon#about to write, iclass 31, count 0 2006.173.20:35:53.74#ibcon#wrote, iclass 31, count 0 2006.173.20:35:53.74#ibcon#about to read 3, iclass 31, count 0 2006.173.20:35:53.76#ibcon#read 3, iclass 31, count 0 2006.173.20:35:53.76#ibcon#about to read 4, iclass 31, count 0 2006.173.20:35:53.76#ibcon#read 4, iclass 31, count 0 2006.173.20:35:53.76#ibcon#about to read 5, iclass 31, count 0 2006.173.20:35:53.76#ibcon#read 5, iclass 31, count 0 2006.173.20:35:53.76#ibcon#about to read 6, iclass 31, count 0 2006.173.20:35:53.76#ibcon#read 6, iclass 31, count 0 2006.173.20:35:53.76#ibcon#end of sib2, iclass 31, count 0 2006.173.20:35:53.76#ibcon#*mode == 0, iclass 31, count 0 2006.173.20:35:53.76#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.20:35:53.76#ibcon#[25=USB\r\n] 2006.173.20:35:53.76#ibcon#*before write, iclass 31, count 0 2006.173.20:35:53.76#ibcon#enter sib2, iclass 31, count 0 2006.173.20:35:53.76#ibcon#flushed, iclass 31, count 0 2006.173.20:35:53.76#ibcon#about to write, iclass 31, count 0 2006.173.20:35:53.76#ibcon#wrote, iclass 31, count 0 2006.173.20:35:53.76#ibcon#about to read 3, iclass 31, count 0 2006.173.20:35:53.79#ibcon#read 3, iclass 31, count 0 2006.173.20:35:53.79#ibcon#about to read 4, iclass 31, count 0 2006.173.20:35:53.79#ibcon#read 4, iclass 31, count 0 2006.173.20:35:53.79#ibcon#about to read 5, iclass 31, count 0 2006.173.20:35:53.79#ibcon#read 5, iclass 31, count 0 2006.173.20:35:53.79#ibcon#about to read 6, iclass 31, count 0 2006.173.20:35:53.79#ibcon#read 6, iclass 31, count 0 2006.173.20:35:53.79#ibcon#end of sib2, iclass 31, count 0 2006.173.20:35:53.79#ibcon#*after write, iclass 31, count 0 2006.173.20:35:53.79#ibcon#*before return 0, iclass 31, count 0 2006.173.20:35:53.79#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.20:35:53.79#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.20:35:53.79#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.20:35:53.79#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.20:35:53.79$vck44/valo=8,884.99 2006.173.20:35:53.79#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.20:35:53.79#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.20:35:53.79#ibcon#ireg 17 cls_cnt 0 2006.173.20:35:53.79#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.20:35:53.79#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.20:35:53.79#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.20:35:53.79#ibcon#enter wrdev, iclass 37, count 0 2006.173.20:35:53.79#ibcon#first serial, iclass 37, count 0 2006.173.20:35:53.79#ibcon#enter sib2, iclass 37, count 0 2006.173.20:35:53.79#ibcon#flushed, iclass 37, count 0 2006.173.20:35:53.79#ibcon#about to write, iclass 37, count 0 2006.173.20:35:53.79#ibcon#wrote, iclass 37, count 0 2006.173.20:35:53.79#ibcon#about to read 3, iclass 37, count 0 2006.173.20:35:53.81#ibcon#read 3, iclass 37, count 0 2006.173.20:35:53.81#ibcon#about to read 4, iclass 37, count 0 2006.173.20:35:53.81#ibcon#read 4, iclass 37, count 0 2006.173.20:35:53.81#ibcon#about to read 5, iclass 37, count 0 2006.173.20:35:53.81#ibcon#read 5, iclass 37, count 0 2006.173.20:35:53.81#ibcon#about to read 6, iclass 37, count 0 2006.173.20:35:53.81#ibcon#read 6, iclass 37, count 0 2006.173.20:35:53.81#ibcon#end of sib2, iclass 37, count 0 2006.173.20:35:53.81#ibcon#*mode == 0, iclass 37, count 0 2006.173.20:35:53.81#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.20:35:53.81#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.20:35:53.81#ibcon#*before write, iclass 37, count 0 2006.173.20:35:53.81#ibcon#enter sib2, iclass 37, count 0 2006.173.20:35:53.81#ibcon#flushed, iclass 37, count 0 2006.173.20:35:53.81#ibcon#about to write, iclass 37, count 0 2006.173.20:35:53.81#ibcon#wrote, iclass 37, count 0 2006.173.20:35:53.81#ibcon#about to read 3, iclass 37, count 0 2006.173.20:35:53.85#ibcon#read 3, iclass 37, count 0 2006.173.20:35:53.85#ibcon#about to read 4, iclass 37, count 0 2006.173.20:35:53.85#ibcon#read 4, iclass 37, count 0 2006.173.20:35:53.85#ibcon#about to read 5, iclass 37, count 0 2006.173.20:35:53.85#ibcon#read 5, iclass 37, count 0 2006.173.20:35:53.85#ibcon#about to read 6, iclass 37, count 0 2006.173.20:35:53.85#ibcon#read 6, iclass 37, count 0 2006.173.20:35:53.85#ibcon#end of sib2, iclass 37, count 0 2006.173.20:35:53.85#ibcon#*after write, iclass 37, count 0 2006.173.20:35:53.85#ibcon#*before return 0, iclass 37, count 0 2006.173.20:35:53.85#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.20:35:53.85#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.20:35:53.85#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.20:35:53.85#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.20:35:53.85$vck44/va=8,4 2006.173.20:35:53.85#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.20:35:53.85#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.20:35:53.85#ibcon#ireg 11 cls_cnt 2 2006.173.20:35:53.85#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.20:35:53.91#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.20:35:53.91#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.20:35:53.91#ibcon#enter wrdev, iclass 39, count 2 2006.173.20:35:53.91#ibcon#first serial, iclass 39, count 2 2006.173.20:35:53.91#ibcon#enter sib2, iclass 39, count 2 2006.173.20:35:53.91#ibcon#flushed, iclass 39, count 2 2006.173.20:35:53.91#ibcon#about to write, iclass 39, count 2 2006.173.20:35:53.91#ibcon#wrote, iclass 39, count 2 2006.173.20:35:53.91#ibcon#about to read 3, iclass 39, count 2 2006.173.20:35:53.93#ibcon#read 3, iclass 39, count 2 2006.173.20:35:53.93#ibcon#about to read 4, iclass 39, count 2 2006.173.20:35:53.93#ibcon#read 4, iclass 39, count 2 2006.173.20:35:53.93#ibcon#about to read 5, iclass 39, count 2 2006.173.20:35:53.93#ibcon#read 5, iclass 39, count 2 2006.173.20:35:53.93#ibcon#about to read 6, iclass 39, count 2 2006.173.20:35:53.93#ibcon#read 6, iclass 39, count 2 2006.173.20:35:53.93#ibcon#end of sib2, iclass 39, count 2 2006.173.20:35:53.93#ibcon#*mode == 0, iclass 39, count 2 2006.173.20:35:53.93#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.20:35:53.93#ibcon#[25=AT08-04\r\n] 2006.173.20:35:53.93#ibcon#*before write, iclass 39, count 2 2006.173.20:35:53.93#ibcon#enter sib2, iclass 39, count 2 2006.173.20:35:53.93#ibcon#flushed, iclass 39, count 2 2006.173.20:35:53.93#ibcon#about to write, iclass 39, count 2 2006.173.20:35:53.93#ibcon#wrote, iclass 39, count 2 2006.173.20:35:53.93#ibcon#about to read 3, iclass 39, count 2 2006.173.20:35:53.96#ibcon#read 3, iclass 39, count 2 2006.173.20:35:53.96#ibcon#about to read 4, iclass 39, count 2 2006.173.20:35:53.96#ibcon#read 4, iclass 39, count 2 2006.173.20:35:53.96#ibcon#about to read 5, iclass 39, count 2 2006.173.20:35:53.96#ibcon#read 5, iclass 39, count 2 2006.173.20:35:53.96#ibcon#about to read 6, iclass 39, count 2 2006.173.20:35:53.96#ibcon#read 6, iclass 39, count 2 2006.173.20:35:53.96#ibcon#end of sib2, iclass 39, count 2 2006.173.20:35:53.96#ibcon#*after write, iclass 39, count 2 2006.173.20:35:53.96#ibcon#*before return 0, iclass 39, count 2 2006.173.20:35:53.96#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.20:35:53.96#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.20:35:53.96#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.20:35:53.96#ibcon#ireg 7 cls_cnt 0 2006.173.20:35:53.96#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.20:35:54.08#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.20:35:54.08#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.20:35:54.08#ibcon#enter wrdev, iclass 39, count 0 2006.173.20:35:54.08#ibcon#first serial, iclass 39, count 0 2006.173.20:35:54.08#ibcon#enter sib2, iclass 39, count 0 2006.173.20:35:54.08#ibcon#flushed, iclass 39, count 0 2006.173.20:35:54.08#ibcon#about to write, iclass 39, count 0 2006.173.20:35:54.08#ibcon#wrote, iclass 39, count 0 2006.173.20:35:54.08#ibcon#about to read 3, iclass 39, count 0 2006.173.20:35:54.10#ibcon#read 3, iclass 39, count 0 2006.173.20:35:54.10#ibcon#about to read 4, iclass 39, count 0 2006.173.20:35:54.10#ibcon#read 4, iclass 39, count 0 2006.173.20:35:54.10#ibcon#about to read 5, iclass 39, count 0 2006.173.20:35:54.10#ibcon#read 5, iclass 39, count 0 2006.173.20:35:54.10#ibcon#about to read 6, iclass 39, count 0 2006.173.20:35:54.10#ibcon#read 6, iclass 39, count 0 2006.173.20:35:54.10#ibcon#end of sib2, iclass 39, count 0 2006.173.20:35:54.10#ibcon#*mode == 0, iclass 39, count 0 2006.173.20:35:54.10#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.20:35:54.10#ibcon#[25=USB\r\n] 2006.173.20:35:54.10#ibcon#*before write, iclass 39, count 0 2006.173.20:35:54.10#ibcon#enter sib2, iclass 39, count 0 2006.173.20:35:54.10#ibcon#flushed, iclass 39, count 0 2006.173.20:35:54.10#ibcon#about to write, iclass 39, count 0 2006.173.20:35:54.10#ibcon#wrote, iclass 39, count 0 2006.173.20:35:54.10#ibcon#about to read 3, iclass 39, count 0 2006.173.20:35:54.13#ibcon#read 3, iclass 39, count 0 2006.173.20:35:54.13#ibcon#about to read 4, iclass 39, count 0 2006.173.20:35:54.13#ibcon#read 4, iclass 39, count 0 2006.173.20:35:54.13#ibcon#about to read 5, iclass 39, count 0 2006.173.20:35:54.13#ibcon#read 5, iclass 39, count 0 2006.173.20:35:54.13#ibcon#about to read 6, iclass 39, count 0 2006.173.20:35:54.13#ibcon#read 6, iclass 39, count 0 2006.173.20:35:54.13#ibcon#end of sib2, iclass 39, count 0 2006.173.20:35:54.13#ibcon#*after write, iclass 39, count 0 2006.173.20:35:54.13#ibcon#*before return 0, iclass 39, count 0 2006.173.20:35:54.13#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.20:35:54.13#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.20:35:54.13#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.20:35:54.13#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.20:35:54.13$vck44/vblo=1,629.99 2006.173.20:35:54.13#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.20:35:54.13#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.20:35:54.13#ibcon#ireg 17 cls_cnt 0 2006.173.20:35:54.13#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.20:35:54.13#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.20:35:54.13#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.20:35:54.13#ibcon#enter wrdev, iclass 3, count 0 2006.173.20:35:54.13#ibcon#first serial, iclass 3, count 0 2006.173.20:35:54.13#ibcon#enter sib2, iclass 3, count 0 2006.173.20:35:54.13#ibcon#flushed, iclass 3, count 0 2006.173.20:35:54.13#ibcon#about to write, iclass 3, count 0 2006.173.20:35:54.13#ibcon#wrote, iclass 3, count 0 2006.173.20:35:54.13#ibcon#about to read 3, iclass 3, count 0 2006.173.20:35:54.15#ibcon#read 3, iclass 3, count 0 2006.173.20:35:54.15#ibcon#about to read 4, iclass 3, count 0 2006.173.20:35:54.15#ibcon#read 4, iclass 3, count 0 2006.173.20:35:54.15#ibcon#about to read 5, iclass 3, count 0 2006.173.20:35:54.15#ibcon#read 5, iclass 3, count 0 2006.173.20:35:54.15#ibcon#about to read 6, iclass 3, count 0 2006.173.20:35:54.15#ibcon#read 6, iclass 3, count 0 2006.173.20:35:54.15#ibcon#end of sib2, iclass 3, count 0 2006.173.20:35:54.15#ibcon#*mode == 0, iclass 3, count 0 2006.173.20:35:54.15#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.20:35:54.15#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.20:35:54.15#ibcon#*before write, iclass 3, count 0 2006.173.20:35:54.15#ibcon#enter sib2, iclass 3, count 0 2006.173.20:35:54.15#ibcon#flushed, iclass 3, count 0 2006.173.20:35:54.15#ibcon#about to write, iclass 3, count 0 2006.173.20:35:54.15#ibcon#wrote, iclass 3, count 0 2006.173.20:35:54.15#ibcon#about to read 3, iclass 3, count 0 2006.173.20:35:54.19#ibcon#read 3, iclass 3, count 0 2006.173.20:35:54.19#ibcon#about to read 4, iclass 3, count 0 2006.173.20:35:54.19#ibcon#read 4, iclass 3, count 0 2006.173.20:35:54.19#ibcon#about to read 5, iclass 3, count 0 2006.173.20:35:54.19#ibcon#read 5, iclass 3, count 0 2006.173.20:35:54.19#ibcon#about to read 6, iclass 3, count 0 2006.173.20:35:54.19#ibcon#read 6, iclass 3, count 0 2006.173.20:35:54.19#ibcon#end of sib2, iclass 3, count 0 2006.173.20:35:54.19#ibcon#*after write, iclass 3, count 0 2006.173.20:35:54.19#ibcon#*before return 0, iclass 3, count 0 2006.173.20:35:54.19#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.20:35:54.19#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.20:35:54.19#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.20:35:54.19#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.20:35:54.19$vck44/vb=1,4 2006.173.20:35:54.19#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.20:35:54.19#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.20:35:54.19#ibcon#ireg 11 cls_cnt 2 2006.173.20:35:54.19#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.20:35:54.19#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.20:35:54.19#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.20:35:54.19#ibcon#enter wrdev, iclass 5, count 2 2006.173.20:35:54.19#ibcon#first serial, iclass 5, count 2 2006.173.20:35:54.19#ibcon#enter sib2, iclass 5, count 2 2006.173.20:35:54.19#ibcon#flushed, iclass 5, count 2 2006.173.20:35:54.19#ibcon#about to write, iclass 5, count 2 2006.173.20:35:54.19#ibcon#wrote, iclass 5, count 2 2006.173.20:35:54.19#ibcon#about to read 3, iclass 5, count 2 2006.173.20:35:54.21#ibcon#read 3, iclass 5, count 2 2006.173.20:35:54.21#ibcon#about to read 4, iclass 5, count 2 2006.173.20:35:54.21#ibcon#read 4, iclass 5, count 2 2006.173.20:35:54.21#ibcon#about to read 5, iclass 5, count 2 2006.173.20:35:54.21#ibcon#read 5, iclass 5, count 2 2006.173.20:35:54.21#ibcon#about to read 6, iclass 5, count 2 2006.173.20:35:54.21#ibcon#read 6, iclass 5, count 2 2006.173.20:35:54.21#ibcon#end of sib2, iclass 5, count 2 2006.173.20:35:54.21#ibcon#*mode == 0, iclass 5, count 2 2006.173.20:35:54.21#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.20:35:54.21#ibcon#[27=AT01-04\r\n] 2006.173.20:35:54.21#ibcon#*before write, iclass 5, count 2 2006.173.20:35:54.21#ibcon#enter sib2, iclass 5, count 2 2006.173.20:35:54.21#ibcon#flushed, iclass 5, count 2 2006.173.20:35:54.21#ibcon#about to write, iclass 5, count 2 2006.173.20:35:54.21#ibcon#wrote, iclass 5, count 2 2006.173.20:35:54.21#ibcon#about to read 3, iclass 5, count 2 2006.173.20:35:54.24#ibcon#read 3, iclass 5, count 2 2006.173.20:35:54.24#ibcon#about to read 4, iclass 5, count 2 2006.173.20:35:54.24#ibcon#read 4, iclass 5, count 2 2006.173.20:35:54.24#ibcon#about to read 5, iclass 5, count 2 2006.173.20:35:54.24#ibcon#read 5, iclass 5, count 2 2006.173.20:35:54.24#ibcon#about to read 6, iclass 5, count 2 2006.173.20:35:54.24#ibcon#read 6, iclass 5, count 2 2006.173.20:35:54.24#ibcon#end of sib2, iclass 5, count 2 2006.173.20:35:54.24#ibcon#*after write, iclass 5, count 2 2006.173.20:35:54.24#ibcon#*before return 0, iclass 5, count 2 2006.173.20:35:54.24#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.20:35:54.24#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.20:35:54.24#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.20:35:54.24#ibcon#ireg 7 cls_cnt 0 2006.173.20:35:54.24#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.20:35:54.36#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.20:35:54.36#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.20:35:54.36#ibcon#enter wrdev, iclass 5, count 0 2006.173.20:35:54.36#ibcon#first serial, iclass 5, count 0 2006.173.20:35:54.36#ibcon#enter sib2, iclass 5, count 0 2006.173.20:35:54.36#ibcon#flushed, iclass 5, count 0 2006.173.20:35:54.36#ibcon#about to write, iclass 5, count 0 2006.173.20:35:54.36#ibcon#wrote, iclass 5, count 0 2006.173.20:35:54.36#ibcon#about to read 3, iclass 5, count 0 2006.173.20:35:54.38#ibcon#read 3, iclass 5, count 0 2006.173.20:35:54.38#ibcon#about to read 4, iclass 5, count 0 2006.173.20:35:54.38#ibcon#read 4, iclass 5, count 0 2006.173.20:35:54.38#ibcon#about to read 5, iclass 5, count 0 2006.173.20:35:54.38#ibcon#read 5, iclass 5, count 0 2006.173.20:35:54.38#ibcon#about to read 6, iclass 5, count 0 2006.173.20:35:54.38#ibcon#read 6, iclass 5, count 0 2006.173.20:35:54.38#ibcon#end of sib2, iclass 5, count 0 2006.173.20:35:54.38#ibcon#*mode == 0, iclass 5, count 0 2006.173.20:35:54.38#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.20:35:54.38#ibcon#[27=USB\r\n] 2006.173.20:35:54.38#ibcon#*before write, iclass 5, count 0 2006.173.20:35:54.38#ibcon#enter sib2, iclass 5, count 0 2006.173.20:35:54.38#ibcon#flushed, iclass 5, count 0 2006.173.20:35:54.38#ibcon#about to write, iclass 5, count 0 2006.173.20:35:54.38#ibcon#wrote, iclass 5, count 0 2006.173.20:35:54.38#ibcon#about to read 3, iclass 5, count 0 2006.173.20:35:54.41#ibcon#read 3, iclass 5, count 0 2006.173.20:35:54.41#ibcon#about to read 4, iclass 5, count 0 2006.173.20:35:54.41#ibcon#read 4, iclass 5, count 0 2006.173.20:35:54.41#ibcon#about to read 5, iclass 5, count 0 2006.173.20:35:54.41#ibcon#read 5, iclass 5, count 0 2006.173.20:35:54.41#ibcon#about to read 6, iclass 5, count 0 2006.173.20:35:54.41#ibcon#read 6, iclass 5, count 0 2006.173.20:35:54.41#ibcon#end of sib2, iclass 5, count 0 2006.173.20:35:54.41#ibcon#*after write, iclass 5, count 0 2006.173.20:35:54.41#ibcon#*before return 0, iclass 5, count 0 2006.173.20:35:54.41#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.20:35:54.41#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.20:35:54.41#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.20:35:54.41#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.20:35:54.41$vck44/vblo=2,634.99 2006.173.20:35:54.41#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.20:35:54.41#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.20:35:54.41#ibcon#ireg 17 cls_cnt 0 2006.173.20:35:54.41#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.20:35:54.41#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.20:35:54.41#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.20:35:54.41#ibcon#enter wrdev, iclass 7, count 0 2006.173.20:35:54.41#ibcon#first serial, iclass 7, count 0 2006.173.20:35:54.41#ibcon#enter sib2, iclass 7, count 0 2006.173.20:35:54.41#ibcon#flushed, iclass 7, count 0 2006.173.20:35:54.41#ibcon#about to write, iclass 7, count 0 2006.173.20:35:54.41#ibcon#wrote, iclass 7, count 0 2006.173.20:35:54.41#ibcon#about to read 3, iclass 7, count 0 2006.173.20:35:54.43#ibcon#read 3, iclass 7, count 0 2006.173.20:35:54.43#ibcon#about to read 4, iclass 7, count 0 2006.173.20:35:54.43#ibcon#read 4, iclass 7, count 0 2006.173.20:35:54.43#ibcon#about to read 5, iclass 7, count 0 2006.173.20:35:54.43#ibcon#read 5, iclass 7, count 0 2006.173.20:35:54.43#ibcon#about to read 6, iclass 7, count 0 2006.173.20:35:54.43#ibcon#read 6, iclass 7, count 0 2006.173.20:35:54.43#ibcon#end of sib2, iclass 7, count 0 2006.173.20:35:54.43#ibcon#*mode == 0, iclass 7, count 0 2006.173.20:35:54.43#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.20:35:54.43#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.20:35:54.43#ibcon#*before write, iclass 7, count 0 2006.173.20:35:54.43#ibcon#enter sib2, iclass 7, count 0 2006.173.20:35:54.43#ibcon#flushed, iclass 7, count 0 2006.173.20:35:54.43#ibcon#about to write, iclass 7, count 0 2006.173.20:35:54.43#ibcon#wrote, iclass 7, count 0 2006.173.20:35:54.43#ibcon#about to read 3, iclass 7, count 0 2006.173.20:35:54.47#ibcon#read 3, iclass 7, count 0 2006.173.20:35:54.47#ibcon#about to read 4, iclass 7, count 0 2006.173.20:35:54.47#ibcon#read 4, iclass 7, count 0 2006.173.20:35:54.47#ibcon#about to read 5, iclass 7, count 0 2006.173.20:35:57.65#ibcon#read 5, iclass 7, count 0 2006.173.20:35:57.65#ibcon#about to read 6, iclass 7, count 0 2006.173.20:35:57.65#ibcon#read 6, iclass 7, count 0 2006.173.20:35:57.65#ibcon#end of sib2, iclass 7, count 0 2006.173.20:35:57.65#ibcon#*after write, iclass 7, count 0 2006.173.20:35:57.65#ibcon#*before return 0, iclass 7, count 0 2006.173.20:35:57.65#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.20:35:57.65#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.20:35:57.65#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.20:35:57.66#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.20:35:57.66$vck44/vb=2,4 2006.173.20:35:57.66#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.20:35:57.66#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.20:35:57.66#ibcon#ireg 11 cls_cnt 2 2006.173.20:35:57.66#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.20:35:57.66#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.20:35:57.66#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.20:35:57.66#ibcon#enter wrdev, iclass 11, count 2 2006.173.20:35:57.66#ibcon#first serial, iclass 11, count 2 2006.173.20:35:57.66#ibcon#enter sib2, iclass 11, count 2 2006.173.20:35:57.66#ibcon#flushed, iclass 11, count 2 2006.173.20:35:57.66#ibcon#about to write, iclass 11, count 2 2006.173.20:35:57.66#ibcon#wrote, iclass 11, count 2 2006.173.20:35:57.66#ibcon#about to read 3, iclass 11, count 2 2006.173.20:35:57.67#ibcon#read 3, iclass 11, count 2 2006.173.20:35:57.67#ibcon#about to read 4, iclass 11, count 2 2006.173.20:35:57.67#ibcon#read 4, iclass 11, count 2 2006.173.20:35:57.67#ibcon#about to read 5, iclass 11, count 2 2006.173.20:35:57.67#ibcon#read 5, iclass 11, count 2 2006.173.20:35:57.67#ibcon#about to read 6, iclass 11, count 2 2006.173.20:35:57.67#ibcon#read 6, iclass 11, count 2 2006.173.20:35:57.67#ibcon#end of sib2, iclass 11, count 2 2006.173.20:35:57.67#ibcon#*mode == 0, iclass 11, count 2 2006.173.20:35:57.67#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.20:35:57.67#ibcon#[27=AT02-04\r\n] 2006.173.20:35:57.67#ibcon#*before write, iclass 11, count 2 2006.173.20:35:57.67#ibcon#enter sib2, iclass 11, count 2 2006.173.20:35:57.67#ibcon#flushed, iclass 11, count 2 2006.173.20:35:57.67#ibcon#about to write, iclass 11, count 2 2006.173.20:35:57.67#ibcon#wrote, iclass 11, count 2 2006.173.20:35:57.67#ibcon#about to read 3, iclass 11, count 2 2006.173.20:35:57.70#ibcon#read 3, iclass 11, count 2 2006.173.20:35:57.70#ibcon#about to read 4, iclass 11, count 2 2006.173.20:35:57.70#ibcon#read 4, iclass 11, count 2 2006.173.20:35:57.70#ibcon#about to read 5, iclass 11, count 2 2006.173.20:35:57.70#ibcon#read 5, iclass 11, count 2 2006.173.20:35:57.70#ibcon#about to read 6, iclass 11, count 2 2006.173.20:35:57.70#ibcon#read 6, iclass 11, count 2 2006.173.20:35:57.70#ibcon#end of sib2, iclass 11, count 2 2006.173.20:35:57.70#ibcon#*after write, iclass 11, count 2 2006.173.20:35:57.70#ibcon#*before return 0, iclass 11, count 2 2006.173.20:35:57.70#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.20:35:57.70#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.20:35:57.70#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.20:35:57.70#ibcon#ireg 7 cls_cnt 0 2006.173.20:35:57.70#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.20:35:57.82#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.20:35:57.82#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.20:35:57.82#ibcon#enter wrdev, iclass 11, count 0 2006.173.20:35:57.82#ibcon#first serial, iclass 11, count 0 2006.173.20:35:57.82#ibcon#enter sib2, iclass 11, count 0 2006.173.20:35:57.82#ibcon#flushed, iclass 11, count 0 2006.173.20:35:57.82#ibcon#about to write, iclass 11, count 0 2006.173.20:35:57.82#ibcon#wrote, iclass 11, count 0 2006.173.20:35:57.82#ibcon#about to read 3, iclass 11, count 0 2006.173.20:35:57.84#ibcon#read 3, iclass 11, count 0 2006.173.20:35:57.84#ibcon#about to read 4, iclass 11, count 0 2006.173.20:35:57.84#ibcon#read 4, iclass 11, count 0 2006.173.20:35:57.84#ibcon#about to read 5, iclass 11, count 0 2006.173.20:35:57.84#ibcon#read 5, iclass 11, count 0 2006.173.20:35:57.84#ibcon#about to read 6, iclass 11, count 0 2006.173.20:35:57.84#ibcon#read 6, iclass 11, count 0 2006.173.20:35:57.84#ibcon#end of sib2, iclass 11, count 0 2006.173.20:35:57.84#ibcon#*mode == 0, iclass 11, count 0 2006.173.20:35:57.84#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.20:35:57.84#ibcon#[27=USB\r\n] 2006.173.20:35:57.84#ibcon#*before write, iclass 11, count 0 2006.173.20:35:57.84#ibcon#enter sib2, iclass 11, count 0 2006.173.20:35:57.84#ibcon#flushed, iclass 11, count 0 2006.173.20:35:57.84#ibcon#about to write, iclass 11, count 0 2006.173.20:35:57.84#ibcon#wrote, iclass 11, count 0 2006.173.20:35:57.84#ibcon#about to read 3, iclass 11, count 0 2006.173.20:35:57.87#ibcon#read 3, iclass 11, count 0 2006.173.20:35:57.87#ibcon#about to read 4, iclass 11, count 0 2006.173.20:35:57.87#ibcon#read 4, iclass 11, count 0 2006.173.20:35:57.87#ibcon#about to read 5, iclass 11, count 0 2006.173.20:35:57.87#ibcon#read 5, iclass 11, count 0 2006.173.20:35:57.87#ibcon#about to read 6, iclass 11, count 0 2006.173.20:35:57.87#ibcon#read 6, iclass 11, count 0 2006.173.20:35:57.87#ibcon#end of sib2, iclass 11, count 0 2006.173.20:35:57.87#ibcon#*after write, iclass 11, count 0 2006.173.20:35:57.87#ibcon#*before return 0, iclass 11, count 0 2006.173.20:35:57.87#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.20:35:57.87#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.20:35:57.87#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.20:35:57.87#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.20:35:57.87$vck44/vblo=3,649.99 2006.173.20:35:57.87#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.20:35:57.87#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.20:35:57.87#ibcon#ireg 17 cls_cnt 0 2006.173.20:35:57.87#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.20:35:57.87#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.20:35:57.87#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.20:35:57.87#ibcon#enter wrdev, iclass 13, count 0 2006.173.20:35:57.87#ibcon#first serial, iclass 13, count 0 2006.173.20:35:57.87#ibcon#enter sib2, iclass 13, count 0 2006.173.20:35:57.87#ibcon#flushed, iclass 13, count 0 2006.173.20:35:57.87#ibcon#about to write, iclass 13, count 0 2006.173.20:35:57.87#ibcon#wrote, iclass 13, count 0 2006.173.20:35:57.87#ibcon#about to read 3, iclass 13, count 0 2006.173.20:35:57.89#ibcon#read 3, iclass 13, count 0 2006.173.20:35:57.89#ibcon#about to read 4, iclass 13, count 0 2006.173.20:35:57.89#ibcon#read 4, iclass 13, count 0 2006.173.20:35:57.89#ibcon#about to read 5, iclass 13, count 0 2006.173.20:35:57.89#ibcon#read 5, iclass 13, count 0 2006.173.20:35:57.89#ibcon#about to read 6, iclass 13, count 0 2006.173.20:35:57.89#ibcon#read 6, iclass 13, count 0 2006.173.20:35:57.89#ibcon#end of sib2, iclass 13, count 0 2006.173.20:35:57.89#ibcon#*mode == 0, iclass 13, count 0 2006.173.20:35:57.89#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.20:35:57.89#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.20:35:57.89#ibcon#*before write, iclass 13, count 0 2006.173.20:35:57.89#ibcon#enter sib2, iclass 13, count 0 2006.173.20:35:57.89#ibcon#flushed, iclass 13, count 0 2006.173.20:35:57.89#ibcon#about to write, iclass 13, count 0 2006.173.20:35:57.89#ibcon#wrote, iclass 13, count 0 2006.173.20:35:57.89#ibcon#about to read 3, iclass 13, count 0 2006.173.20:35:57.93#ibcon#read 3, iclass 13, count 0 2006.173.20:35:57.93#ibcon#about to read 4, iclass 13, count 0 2006.173.20:35:57.93#ibcon#read 4, iclass 13, count 0 2006.173.20:35:57.93#ibcon#about to read 5, iclass 13, count 0 2006.173.20:35:57.93#ibcon#read 5, iclass 13, count 0 2006.173.20:35:57.93#ibcon#about to read 6, iclass 13, count 0 2006.173.20:35:57.93#ibcon#read 6, iclass 13, count 0 2006.173.20:35:57.93#ibcon#end of sib2, iclass 13, count 0 2006.173.20:35:57.93#ibcon#*after write, iclass 13, count 0 2006.173.20:35:57.93#ibcon#*before return 0, iclass 13, count 0 2006.173.20:35:57.93#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.20:35:57.93#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.20:35:57.93#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.20:35:57.93#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.20:35:57.93$vck44/vb=3,4 2006.173.20:35:57.93#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.20:35:57.93#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.20:35:57.93#ibcon#ireg 11 cls_cnt 2 2006.173.20:35:57.93#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.20:35:57.99#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.20:35:57.99#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.20:35:57.99#ibcon#enter wrdev, iclass 15, count 2 2006.173.20:35:57.99#ibcon#first serial, iclass 15, count 2 2006.173.20:35:57.99#ibcon#enter sib2, iclass 15, count 2 2006.173.20:35:57.99#ibcon#flushed, iclass 15, count 2 2006.173.20:35:57.99#ibcon#about to write, iclass 15, count 2 2006.173.20:35:57.99#ibcon#wrote, iclass 15, count 2 2006.173.20:35:57.99#ibcon#about to read 3, iclass 15, count 2 2006.173.20:35:58.01#ibcon#read 3, iclass 15, count 2 2006.173.20:35:58.01#ibcon#about to read 4, iclass 15, count 2 2006.173.20:35:58.01#ibcon#read 4, iclass 15, count 2 2006.173.20:35:58.01#ibcon#about to read 5, iclass 15, count 2 2006.173.20:35:58.01#ibcon#read 5, iclass 15, count 2 2006.173.20:35:58.01#ibcon#about to read 6, iclass 15, count 2 2006.173.20:35:58.01#ibcon#read 6, iclass 15, count 2 2006.173.20:35:58.01#ibcon#end of sib2, iclass 15, count 2 2006.173.20:35:58.01#ibcon#*mode == 0, iclass 15, count 2 2006.173.20:35:58.01#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.20:35:58.01#ibcon#[27=AT03-04\r\n] 2006.173.20:35:58.01#ibcon#*before write, iclass 15, count 2 2006.173.20:35:58.01#ibcon#enter sib2, iclass 15, count 2 2006.173.20:35:58.01#ibcon#flushed, iclass 15, count 2 2006.173.20:35:58.01#ibcon#about to write, iclass 15, count 2 2006.173.20:35:58.01#ibcon#wrote, iclass 15, count 2 2006.173.20:35:58.01#ibcon#about to read 3, iclass 15, count 2 2006.173.20:35:58.04#ibcon#read 3, iclass 15, count 2 2006.173.20:35:58.04#ibcon#about to read 4, iclass 15, count 2 2006.173.20:35:58.04#ibcon#read 4, iclass 15, count 2 2006.173.20:35:58.04#ibcon#about to read 5, iclass 15, count 2 2006.173.20:35:58.04#ibcon#read 5, iclass 15, count 2 2006.173.20:35:58.04#ibcon#about to read 6, iclass 15, count 2 2006.173.20:35:58.04#ibcon#read 6, iclass 15, count 2 2006.173.20:35:58.04#ibcon#end of sib2, iclass 15, count 2 2006.173.20:35:58.04#ibcon#*after write, iclass 15, count 2 2006.173.20:35:58.04#ibcon#*before return 0, iclass 15, count 2 2006.173.20:35:58.04#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.20:35:58.04#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.20:35:58.04#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.20:35:58.04#ibcon#ireg 7 cls_cnt 0 2006.173.20:35:58.04#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.20:35:58.16#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.20:35:58.16#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.20:35:58.16#ibcon#enter wrdev, iclass 15, count 0 2006.173.20:35:58.16#ibcon#first serial, iclass 15, count 0 2006.173.20:35:58.16#ibcon#enter sib2, iclass 15, count 0 2006.173.20:35:58.16#ibcon#flushed, iclass 15, count 0 2006.173.20:35:58.16#ibcon#about to write, iclass 15, count 0 2006.173.20:35:58.16#ibcon#wrote, iclass 15, count 0 2006.173.20:35:58.16#ibcon#about to read 3, iclass 15, count 0 2006.173.20:35:58.18#ibcon#read 3, iclass 15, count 0 2006.173.20:35:58.18#ibcon#about to read 4, iclass 15, count 0 2006.173.20:35:58.18#ibcon#read 4, iclass 15, count 0 2006.173.20:35:58.18#ibcon#about to read 5, iclass 15, count 0 2006.173.20:35:58.18#ibcon#read 5, iclass 15, count 0 2006.173.20:35:58.18#ibcon#about to read 6, iclass 15, count 0 2006.173.20:35:58.18#ibcon#read 6, iclass 15, count 0 2006.173.20:35:58.18#ibcon#end of sib2, iclass 15, count 0 2006.173.20:35:58.18#ibcon#*mode == 0, iclass 15, count 0 2006.173.20:35:58.18#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.20:35:58.18#ibcon#[27=USB\r\n] 2006.173.20:35:58.18#ibcon#*before write, iclass 15, count 0 2006.173.20:35:58.18#ibcon#enter sib2, iclass 15, count 0 2006.173.20:35:58.18#ibcon#flushed, iclass 15, count 0 2006.173.20:35:58.18#ibcon#about to write, iclass 15, count 0 2006.173.20:35:58.18#ibcon#wrote, iclass 15, count 0 2006.173.20:35:58.18#ibcon#about to read 3, iclass 15, count 0 2006.173.20:35:58.21#ibcon#read 3, iclass 15, count 0 2006.173.20:35:58.21#ibcon#about to read 4, iclass 15, count 0 2006.173.20:35:58.21#ibcon#read 4, iclass 15, count 0 2006.173.20:35:58.21#ibcon#about to read 5, iclass 15, count 0 2006.173.20:35:58.21#ibcon#read 5, iclass 15, count 0 2006.173.20:35:58.21#ibcon#about to read 6, iclass 15, count 0 2006.173.20:35:58.21#ibcon#read 6, iclass 15, count 0 2006.173.20:35:58.21#ibcon#end of sib2, iclass 15, count 0 2006.173.20:35:58.21#ibcon#*after write, iclass 15, count 0 2006.173.20:35:58.21#ibcon#*before return 0, iclass 15, count 0 2006.173.20:35:58.21#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.20:35:58.21#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.20:35:58.21#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.20:35:58.21#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.20:35:58.21$vck44/vblo=4,679.99 2006.173.20:35:58.21#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.20:35:58.21#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.20:35:58.21#ibcon#ireg 17 cls_cnt 0 2006.173.20:35:58.21#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.20:35:58.21#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.20:35:58.21#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.20:35:58.21#ibcon#enter wrdev, iclass 17, count 0 2006.173.20:35:58.21#ibcon#first serial, iclass 17, count 0 2006.173.20:35:58.21#ibcon#enter sib2, iclass 17, count 0 2006.173.20:35:58.21#ibcon#flushed, iclass 17, count 0 2006.173.20:35:58.21#ibcon#about to write, iclass 17, count 0 2006.173.20:35:58.21#ibcon#wrote, iclass 17, count 0 2006.173.20:35:58.21#ibcon#about to read 3, iclass 17, count 0 2006.173.20:35:58.23#ibcon#read 3, iclass 17, count 0 2006.173.20:35:58.23#ibcon#about to read 4, iclass 17, count 0 2006.173.20:35:58.23#ibcon#read 4, iclass 17, count 0 2006.173.20:35:58.23#ibcon#about to read 5, iclass 17, count 0 2006.173.20:35:58.23#ibcon#read 5, iclass 17, count 0 2006.173.20:35:58.23#ibcon#about to read 6, iclass 17, count 0 2006.173.20:35:58.23#ibcon#read 6, iclass 17, count 0 2006.173.20:35:58.23#ibcon#end of sib2, iclass 17, count 0 2006.173.20:35:58.23#ibcon#*mode == 0, iclass 17, count 0 2006.173.20:35:58.23#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.20:35:58.23#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.20:35:58.23#ibcon#*before write, iclass 17, count 0 2006.173.20:35:58.23#ibcon#enter sib2, iclass 17, count 0 2006.173.20:35:58.23#ibcon#flushed, iclass 17, count 0 2006.173.20:35:58.23#ibcon#about to write, iclass 17, count 0 2006.173.20:35:58.23#ibcon#wrote, iclass 17, count 0 2006.173.20:35:58.23#ibcon#about to read 3, iclass 17, count 0 2006.173.20:35:58.27#ibcon#read 3, iclass 17, count 0 2006.173.20:35:58.27#ibcon#about to read 4, iclass 17, count 0 2006.173.20:35:58.27#ibcon#read 4, iclass 17, count 0 2006.173.20:35:58.27#ibcon#about to read 5, iclass 17, count 0 2006.173.20:35:58.27#ibcon#read 5, iclass 17, count 0 2006.173.20:35:58.27#ibcon#about to read 6, iclass 17, count 0 2006.173.20:35:58.27#ibcon#read 6, iclass 17, count 0 2006.173.20:35:58.27#ibcon#end of sib2, iclass 17, count 0 2006.173.20:35:58.27#ibcon#*after write, iclass 17, count 0 2006.173.20:35:58.27#ibcon#*before return 0, iclass 17, count 0 2006.173.20:35:58.27#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.20:35:58.27#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.20:35:58.27#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.20:35:58.27#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.20:35:58.27$vck44/vb=4,4 2006.173.20:35:58.27#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.20:35:58.27#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.20:35:58.27#ibcon#ireg 11 cls_cnt 2 2006.173.20:35:58.27#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.20:35:58.33#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.20:35:58.33#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.20:35:58.33#ibcon#enter wrdev, iclass 19, count 2 2006.173.20:35:58.33#ibcon#first serial, iclass 19, count 2 2006.173.20:35:58.33#ibcon#enter sib2, iclass 19, count 2 2006.173.20:35:58.33#ibcon#flushed, iclass 19, count 2 2006.173.20:35:58.33#ibcon#about to write, iclass 19, count 2 2006.173.20:35:58.33#ibcon#wrote, iclass 19, count 2 2006.173.20:35:58.33#ibcon#about to read 3, iclass 19, count 2 2006.173.20:35:58.35#ibcon#read 3, iclass 19, count 2 2006.173.20:35:58.35#ibcon#about to read 4, iclass 19, count 2 2006.173.20:35:58.35#ibcon#read 4, iclass 19, count 2 2006.173.20:35:58.35#ibcon#about to read 5, iclass 19, count 2 2006.173.20:35:58.35#ibcon#read 5, iclass 19, count 2 2006.173.20:35:58.35#ibcon#about to read 6, iclass 19, count 2 2006.173.20:35:58.35#ibcon#read 6, iclass 19, count 2 2006.173.20:35:58.35#ibcon#end of sib2, iclass 19, count 2 2006.173.20:35:58.35#ibcon#*mode == 0, iclass 19, count 2 2006.173.20:35:58.35#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.20:35:58.35#ibcon#[27=AT04-04\r\n] 2006.173.20:35:58.35#ibcon#*before write, iclass 19, count 2 2006.173.20:35:58.35#ibcon#enter sib2, iclass 19, count 2 2006.173.20:35:58.35#ibcon#flushed, iclass 19, count 2 2006.173.20:35:58.35#ibcon#about to write, iclass 19, count 2 2006.173.20:35:58.35#ibcon#wrote, iclass 19, count 2 2006.173.20:35:58.35#ibcon#about to read 3, iclass 19, count 2 2006.173.20:35:58.38#ibcon#read 3, iclass 19, count 2 2006.173.20:35:58.38#ibcon#about to read 4, iclass 19, count 2 2006.173.20:35:58.38#ibcon#read 4, iclass 19, count 2 2006.173.20:35:58.38#ibcon#about to read 5, iclass 19, count 2 2006.173.20:35:58.38#ibcon#read 5, iclass 19, count 2 2006.173.20:35:58.38#ibcon#about to read 6, iclass 19, count 2 2006.173.20:35:58.38#ibcon#read 6, iclass 19, count 2 2006.173.20:35:58.38#ibcon#end of sib2, iclass 19, count 2 2006.173.20:35:58.38#ibcon#*after write, iclass 19, count 2 2006.173.20:35:58.38#ibcon#*before return 0, iclass 19, count 2 2006.173.20:35:58.38#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.20:35:58.38#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.20:35:58.38#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.20:35:58.38#ibcon#ireg 7 cls_cnt 0 2006.173.20:35:58.38#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.20:35:58.50#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.20:35:58.50#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.20:35:58.50#ibcon#enter wrdev, iclass 19, count 0 2006.173.20:35:58.50#ibcon#first serial, iclass 19, count 0 2006.173.20:35:58.50#ibcon#enter sib2, iclass 19, count 0 2006.173.20:35:58.50#ibcon#flushed, iclass 19, count 0 2006.173.20:35:58.50#ibcon#about to write, iclass 19, count 0 2006.173.20:35:58.50#ibcon#wrote, iclass 19, count 0 2006.173.20:35:58.50#ibcon#about to read 3, iclass 19, count 0 2006.173.20:35:58.52#ibcon#read 3, iclass 19, count 0 2006.173.20:35:58.52#ibcon#about to read 4, iclass 19, count 0 2006.173.20:35:58.52#ibcon#read 4, iclass 19, count 0 2006.173.20:35:58.52#ibcon#about to read 5, iclass 19, count 0 2006.173.20:35:58.52#ibcon#read 5, iclass 19, count 0 2006.173.20:35:58.52#ibcon#about to read 6, iclass 19, count 0 2006.173.20:35:58.52#ibcon#read 6, iclass 19, count 0 2006.173.20:35:58.52#ibcon#end of sib2, iclass 19, count 0 2006.173.20:35:58.52#ibcon#*mode == 0, iclass 19, count 0 2006.173.20:35:58.52#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.20:35:58.52#ibcon#[27=USB\r\n] 2006.173.20:35:58.52#ibcon#*before write, iclass 19, count 0 2006.173.20:35:58.52#ibcon#enter sib2, iclass 19, count 0 2006.173.20:35:58.52#ibcon#flushed, iclass 19, count 0 2006.173.20:35:58.52#ibcon#about to write, iclass 19, count 0 2006.173.20:35:58.52#ibcon#wrote, iclass 19, count 0 2006.173.20:35:58.52#ibcon#about to read 3, iclass 19, count 0 2006.173.20:35:58.55#ibcon#read 3, iclass 19, count 0 2006.173.20:35:58.55#ibcon#about to read 4, iclass 19, count 0 2006.173.20:35:58.55#ibcon#read 4, iclass 19, count 0 2006.173.20:35:58.55#ibcon#about to read 5, iclass 19, count 0 2006.173.20:35:58.55#ibcon#read 5, iclass 19, count 0 2006.173.20:35:58.55#ibcon#about to read 6, iclass 19, count 0 2006.173.20:35:58.55#ibcon#read 6, iclass 19, count 0 2006.173.20:35:58.55#ibcon#end of sib2, iclass 19, count 0 2006.173.20:35:58.55#ibcon#*after write, iclass 19, count 0 2006.173.20:35:58.55#ibcon#*before return 0, iclass 19, count 0 2006.173.20:35:58.55#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.20:35:58.55#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.20:35:58.55#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.20:35:58.55#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.20:35:58.55$vck44/vblo=5,709.99 2006.173.20:35:58.55#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.20:35:58.55#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.20:35:58.55#ibcon#ireg 17 cls_cnt 0 2006.173.20:35:58.55#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.20:35:58.55#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.20:35:58.55#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.20:35:58.55#ibcon#enter wrdev, iclass 21, count 0 2006.173.20:35:58.55#ibcon#first serial, iclass 21, count 0 2006.173.20:35:58.55#ibcon#enter sib2, iclass 21, count 0 2006.173.20:35:58.55#ibcon#flushed, iclass 21, count 0 2006.173.20:35:58.55#ibcon#about to write, iclass 21, count 0 2006.173.20:35:58.55#ibcon#wrote, iclass 21, count 0 2006.173.20:35:58.55#ibcon#about to read 3, iclass 21, count 0 2006.173.20:35:58.57#ibcon#read 3, iclass 21, count 0 2006.173.20:35:58.57#ibcon#about to read 4, iclass 21, count 0 2006.173.20:35:58.57#ibcon#read 4, iclass 21, count 0 2006.173.20:35:58.57#ibcon#about to read 5, iclass 21, count 0 2006.173.20:35:58.57#ibcon#read 5, iclass 21, count 0 2006.173.20:35:58.57#ibcon#about to read 6, iclass 21, count 0 2006.173.20:35:58.57#ibcon#read 6, iclass 21, count 0 2006.173.20:35:58.57#ibcon#end of sib2, iclass 21, count 0 2006.173.20:35:58.57#ibcon#*mode == 0, iclass 21, count 0 2006.173.20:35:58.57#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.20:35:58.57#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.20:35:58.57#ibcon#*before write, iclass 21, count 0 2006.173.20:35:58.57#ibcon#enter sib2, iclass 21, count 0 2006.173.20:35:58.57#ibcon#flushed, iclass 21, count 0 2006.173.20:35:58.57#ibcon#about to write, iclass 21, count 0 2006.173.20:35:58.57#ibcon#wrote, iclass 21, count 0 2006.173.20:35:58.57#ibcon#about to read 3, iclass 21, count 0 2006.173.20:35:58.61#ibcon#read 3, iclass 21, count 0 2006.173.20:35:58.61#ibcon#about to read 4, iclass 21, count 0 2006.173.20:35:58.61#ibcon#read 4, iclass 21, count 0 2006.173.20:35:58.61#ibcon#about to read 5, iclass 21, count 0 2006.173.20:35:58.61#ibcon#read 5, iclass 21, count 0 2006.173.20:35:58.61#ibcon#about to read 6, iclass 21, count 0 2006.173.20:35:58.61#ibcon#read 6, iclass 21, count 0 2006.173.20:35:58.61#ibcon#end of sib2, iclass 21, count 0 2006.173.20:35:58.61#ibcon#*after write, iclass 21, count 0 2006.173.20:35:58.61#ibcon#*before return 0, iclass 21, count 0 2006.173.20:35:58.61#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.20:35:58.61#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.20:35:58.61#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.20:35:58.61#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.20:35:58.61$vck44/vb=5,4 2006.173.20:35:58.61#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.20:35:58.61#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.20:35:58.61#ibcon#ireg 11 cls_cnt 2 2006.173.20:35:58.61#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.20:35:58.67#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.20:35:58.67#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.20:35:58.67#ibcon#enter wrdev, iclass 23, count 2 2006.173.20:35:58.67#ibcon#first serial, iclass 23, count 2 2006.173.20:35:58.67#ibcon#enter sib2, iclass 23, count 2 2006.173.20:35:58.67#ibcon#flushed, iclass 23, count 2 2006.173.20:35:58.67#ibcon#about to write, iclass 23, count 2 2006.173.20:35:58.67#ibcon#wrote, iclass 23, count 2 2006.173.20:35:58.67#ibcon#about to read 3, iclass 23, count 2 2006.173.20:35:58.69#ibcon#read 3, iclass 23, count 2 2006.173.20:35:58.69#ibcon#about to read 4, iclass 23, count 2 2006.173.20:35:58.69#ibcon#read 4, iclass 23, count 2 2006.173.20:35:58.69#ibcon#about to read 5, iclass 23, count 2 2006.173.20:35:58.69#ibcon#read 5, iclass 23, count 2 2006.173.20:35:58.69#ibcon#about to read 6, iclass 23, count 2 2006.173.20:35:58.69#ibcon#read 6, iclass 23, count 2 2006.173.20:35:58.69#ibcon#end of sib2, iclass 23, count 2 2006.173.20:35:58.69#ibcon#*mode == 0, iclass 23, count 2 2006.173.20:35:58.69#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.20:35:58.69#ibcon#[27=AT05-04\r\n] 2006.173.20:35:58.69#ibcon#*before write, iclass 23, count 2 2006.173.20:35:58.69#ibcon#enter sib2, iclass 23, count 2 2006.173.20:35:58.69#ibcon#flushed, iclass 23, count 2 2006.173.20:35:58.69#ibcon#about to write, iclass 23, count 2 2006.173.20:35:58.69#ibcon#wrote, iclass 23, count 2 2006.173.20:35:58.69#ibcon#about to read 3, iclass 23, count 2 2006.173.20:35:58.72#ibcon#read 3, iclass 23, count 2 2006.173.20:35:58.72#ibcon#about to read 4, iclass 23, count 2 2006.173.20:35:58.72#ibcon#read 4, iclass 23, count 2 2006.173.20:35:58.72#ibcon#about to read 5, iclass 23, count 2 2006.173.20:35:58.72#ibcon#read 5, iclass 23, count 2 2006.173.20:35:58.72#ibcon#about to read 6, iclass 23, count 2 2006.173.20:35:58.72#ibcon#read 6, iclass 23, count 2 2006.173.20:35:58.72#ibcon#end of sib2, iclass 23, count 2 2006.173.20:35:58.72#ibcon#*after write, iclass 23, count 2 2006.173.20:35:58.72#ibcon#*before return 0, iclass 23, count 2 2006.173.20:35:58.72#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.20:35:58.72#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.20:35:58.72#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.20:35:58.72#ibcon#ireg 7 cls_cnt 0 2006.173.20:35:58.72#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.20:35:58.84#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.20:35:58.84#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.20:35:58.84#ibcon#enter wrdev, iclass 23, count 0 2006.173.20:35:58.84#ibcon#first serial, iclass 23, count 0 2006.173.20:35:58.84#ibcon#enter sib2, iclass 23, count 0 2006.173.20:35:58.84#ibcon#flushed, iclass 23, count 0 2006.173.20:35:58.84#ibcon#about to write, iclass 23, count 0 2006.173.20:35:58.84#ibcon#wrote, iclass 23, count 0 2006.173.20:35:58.84#ibcon#about to read 3, iclass 23, count 0 2006.173.20:35:58.86#ibcon#read 3, iclass 23, count 0 2006.173.20:35:58.86#ibcon#about to read 4, iclass 23, count 0 2006.173.20:35:58.86#ibcon#read 4, iclass 23, count 0 2006.173.20:35:58.86#ibcon#about to read 5, iclass 23, count 0 2006.173.20:35:58.86#ibcon#read 5, iclass 23, count 0 2006.173.20:35:58.86#ibcon#about to read 6, iclass 23, count 0 2006.173.20:35:58.86#ibcon#read 6, iclass 23, count 0 2006.173.20:35:58.86#ibcon#end of sib2, iclass 23, count 0 2006.173.20:35:58.86#ibcon#*mode == 0, iclass 23, count 0 2006.173.20:35:58.86#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.20:35:58.86#ibcon#[27=USB\r\n] 2006.173.20:35:58.86#ibcon#*before write, iclass 23, count 0 2006.173.20:35:58.86#ibcon#enter sib2, iclass 23, count 0 2006.173.20:35:58.86#ibcon#flushed, iclass 23, count 0 2006.173.20:35:58.86#ibcon#about to write, iclass 23, count 0 2006.173.20:35:58.86#ibcon#wrote, iclass 23, count 0 2006.173.20:35:58.86#ibcon#about to read 3, iclass 23, count 0 2006.173.20:35:58.89#ibcon#read 3, iclass 23, count 0 2006.173.20:35:58.89#ibcon#about to read 4, iclass 23, count 0 2006.173.20:35:58.89#ibcon#read 4, iclass 23, count 0 2006.173.20:35:58.89#ibcon#about to read 5, iclass 23, count 0 2006.173.20:35:58.89#ibcon#read 5, iclass 23, count 0 2006.173.20:35:58.89#ibcon#about to read 6, iclass 23, count 0 2006.173.20:35:58.89#ibcon#read 6, iclass 23, count 0 2006.173.20:35:58.89#ibcon#end of sib2, iclass 23, count 0 2006.173.20:35:58.89#ibcon#*after write, iclass 23, count 0 2006.173.20:35:58.89#ibcon#*before return 0, iclass 23, count 0 2006.173.20:35:58.89#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.20:35:58.89#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.20:35:58.89#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.20:35:58.89#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.20:35:58.89$vck44/vblo=6,719.99 2006.173.20:35:58.89#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.20:35:58.89#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.20:35:58.89#ibcon#ireg 17 cls_cnt 0 2006.173.20:35:58.89#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.20:35:58.89#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.20:35:58.89#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.20:35:58.89#ibcon#enter wrdev, iclass 25, count 0 2006.173.20:35:58.89#ibcon#first serial, iclass 25, count 0 2006.173.20:35:58.89#ibcon#enter sib2, iclass 25, count 0 2006.173.20:35:58.89#ibcon#flushed, iclass 25, count 0 2006.173.20:35:58.89#ibcon#about to write, iclass 25, count 0 2006.173.20:35:58.89#ibcon#wrote, iclass 25, count 0 2006.173.20:35:58.89#ibcon#about to read 3, iclass 25, count 0 2006.173.20:35:58.91#ibcon#read 3, iclass 25, count 0 2006.173.20:35:58.91#ibcon#about to read 4, iclass 25, count 0 2006.173.20:35:58.91#ibcon#read 4, iclass 25, count 0 2006.173.20:35:58.91#ibcon#about to read 5, iclass 25, count 0 2006.173.20:35:58.91#ibcon#read 5, iclass 25, count 0 2006.173.20:35:58.91#ibcon#about to read 6, iclass 25, count 0 2006.173.20:35:58.91#ibcon#read 6, iclass 25, count 0 2006.173.20:35:58.91#ibcon#end of sib2, iclass 25, count 0 2006.173.20:35:58.91#ibcon#*mode == 0, iclass 25, count 0 2006.173.20:35:58.91#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.20:35:58.91#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.20:35:58.91#ibcon#*before write, iclass 25, count 0 2006.173.20:35:58.91#ibcon#enter sib2, iclass 25, count 0 2006.173.20:35:58.91#ibcon#flushed, iclass 25, count 0 2006.173.20:35:58.91#ibcon#about to write, iclass 25, count 0 2006.173.20:35:58.91#ibcon#wrote, iclass 25, count 0 2006.173.20:35:58.91#ibcon#about to read 3, iclass 25, count 0 2006.173.20:35:58.95#ibcon#read 3, iclass 25, count 0 2006.173.20:35:58.95#ibcon#about to read 4, iclass 25, count 0 2006.173.20:35:58.95#ibcon#read 4, iclass 25, count 0 2006.173.20:35:58.95#ibcon#about to read 5, iclass 25, count 0 2006.173.20:35:58.95#ibcon#read 5, iclass 25, count 0 2006.173.20:35:58.95#ibcon#about to read 6, iclass 25, count 0 2006.173.20:35:58.95#ibcon#read 6, iclass 25, count 0 2006.173.20:35:58.95#ibcon#end of sib2, iclass 25, count 0 2006.173.20:35:58.95#ibcon#*after write, iclass 25, count 0 2006.173.20:35:58.95#ibcon#*before return 0, iclass 25, count 0 2006.173.20:35:58.95#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.20:35:58.95#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.20:35:58.95#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.20:35:58.95#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.20:35:58.95$vck44/vb=6,4 2006.173.20:35:58.95#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.20:35:58.95#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.20:35:58.95#ibcon#ireg 11 cls_cnt 2 2006.173.20:35:58.95#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.20:35:59.01#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.20:35:59.01#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.20:35:59.01#ibcon#enter wrdev, iclass 27, count 2 2006.173.20:35:59.01#ibcon#first serial, iclass 27, count 2 2006.173.20:35:59.01#ibcon#enter sib2, iclass 27, count 2 2006.173.20:35:59.01#ibcon#flushed, iclass 27, count 2 2006.173.20:35:59.01#ibcon#about to write, iclass 27, count 2 2006.173.20:35:59.01#ibcon#wrote, iclass 27, count 2 2006.173.20:35:59.01#ibcon#about to read 3, iclass 27, count 2 2006.173.20:35:59.74#ibcon#read 3, iclass 27, count 2 2006.173.20:35:59.74#ibcon#about to read 4, iclass 27, count 2 2006.173.20:35:59.74#ibcon#read 4, iclass 27, count 2 2006.173.20:35:59.74#ibcon#about to read 5, iclass 27, count 2 2006.173.20:35:59.74#ibcon#read 5, iclass 27, count 2 2006.173.20:35:59.74#ibcon#about to read 6, iclass 27, count 2 2006.173.20:35:59.74#ibcon#read 6, iclass 27, count 2 2006.173.20:35:59.74#ibcon#end of sib2, iclass 27, count 2 2006.173.20:35:59.75#ibcon#*mode == 0, iclass 27, count 2 2006.173.20:35:59.75#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.20:35:59.75#ibcon#[27=AT06-04\r\n] 2006.173.20:35:59.75#ibcon#*before write, iclass 27, count 2 2006.173.20:35:59.75#ibcon#enter sib2, iclass 27, count 2 2006.173.20:35:59.75#ibcon#flushed, iclass 27, count 2 2006.173.20:35:59.75#ibcon#about to write, iclass 27, count 2 2006.173.20:35:59.75#ibcon#wrote, iclass 27, count 2 2006.173.20:35:59.75#ibcon#about to read 3, iclass 27, count 2 2006.173.20:35:59.77#ibcon#read 3, iclass 27, count 2 2006.173.20:35:59.77#ibcon#about to read 4, iclass 27, count 2 2006.173.20:35:59.77#ibcon#read 4, iclass 27, count 2 2006.173.20:35:59.77#ibcon#about to read 5, iclass 27, count 2 2006.173.20:35:59.77#ibcon#read 5, iclass 27, count 2 2006.173.20:35:59.77#ibcon#about to read 6, iclass 27, count 2 2006.173.20:35:59.77#ibcon#read 6, iclass 27, count 2 2006.173.20:35:59.77#ibcon#end of sib2, iclass 27, count 2 2006.173.20:35:59.77#ibcon#*after write, iclass 27, count 2 2006.173.20:35:59.77#ibcon#*before return 0, iclass 27, count 2 2006.173.20:35:59.77#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.20:35:59.77#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.20:35:59.77#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.20:35:59.77#ibcon#ireg 7 cls_cnt 0 2006.173.20:35:59.77#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.20:35:59.89#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.20:35:59.89#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.20:35:59.89#ibcon#enter wrdev, iclass 27, count 0 2006.173.20:35:59.89#ibcon#first serial, iclass 27, count 0 2006.173.20:35:59.89#ibcon#enter sib2, iclass 27, count 0 2006.173.20:35:59.89#ibcon#flushed, iclass 27, count 0 2006.173.20:35:59.89#ibcon#about to write, iclass 27, count 0 2006.173.20:35:59.89#ibcon#wrote, iclass 27, count 0 2006.173.20:35:59.89#ibcon#about to read 3, iclass 27, count 0 2006.173.20:35:59.91#ibcon#read 3, iclass 27, count 0 2006.173.20:35:59.91#ibcon#about to read 4, iclass 27, count 0 2006.173.20:35:59.91#ibcon#read 4, iclass 27, count 0 2006.173.20:35:59.91#ibcon#about to read 5, iclass 27, count 0 2006.173.20:35:59.91#ibcon#read 5, iclass 27, count 0 2006.173.20:35:59.91#ibcon#about to read 6, iclass 27, count 0 2006.173.20:35:59.91#ibcon#read 6, iclass 27, count 0 2006.173.20:35:59.91#ibcon#end of sib2, iclass 27, count 0 2006.173.20:35:59.91#ibcon#*mode == 0, iclass 27, count 0 2006.173.20:35:59.91#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.20:35:59.91#ibcon#[27=USB\r\n] 2006.173.20:35:59.91#ibcon#*before write, iclass 27, count 0 2006.173.20:35:59.91#ibcon#enter sib2, iclass 27, count 0 2006.173.20:35:59.91#ibcon#flushed, iclass 27, count 0 2006.173.20:35:59.91#ibcon#about to write, iclass 27, count 0 2006.173.20:35:59.91#ibcon#wrote, iclass 27, count 0 2006.173.20:35:59.91#ibcon#about to read 3, iclass 27, count 0 2006.173.20:35:59.94#ibcon#read 3, iclass 27, count 0 2006.173.20:35:59.94#ibcon#about to read 4, iclass 27, count 0 2006.173.20:35:59.94#ibcon#read 4, iclass 27, count 0 2006.173.20:35:59.94#ibcon#about to read 5, iclass 27, count 0 2006.173.20:35:59.94#ibcon#read 5, iclass 27, count 0 2006.173.20:35:59.94#ibcon#about to read 6, iclass 27, count 0 2006.173.20:35:59.94#ibcon#read 6, iclass 27, count 0 2006.173.20:35:59.94#ibcon#end of sib2, iclass 27, count 0 2006.173.20:35:59.94#ibcon#*after write, iclass 27, count 0 2006.173.20:35:59.94#ibcon#*before return 0, iclass 27, count 0 2006.173.20:35:59.94#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.20:35:59.94#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.20:35:59.94#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.20:35:59.94#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.20:35:59.94$vck44/vblo=7,734.99 2006.173.20:35:59.94#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.20:35:59.94#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.20:35:59.94#ibcon#ireg 17 cls_cnt 0 2006.173.20:35:59.94#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.20:35:59.94#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.20:35:59.94#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.20:35:59.94#ibcon#enter wrdev, iclass 29, count 0 2006.173.20:35:59.94#ibcon#first serial, iclass 29, count 0 2006.173.20:35:59.94#ibcon#enter sib2, iclass 29, count 0 2006.173.20:35:59.94#ibcon#flushed, iclass 29, count 0 2006.173.20:35:59.94#ibcon#about to write, iclass 29, count 0 2006.173.20:35:59.94#ibcon#wrote, iclass 29, count 0 2006.173.20:35:59.94#ibcon#about to read 3, iclass 29, count 0 2006.173.20:35:59.96#ibcon#read 3, iclass 29, count 0 2006.173.20:35:59.96#ibcon#about to read 4, iclass 29, count 0 2006.173.20:35:59.96#ibcon#read 4, iclass 29, count 0 2006.173.20:35:59.96#ibcon#about to read 5, iclass 29, count 0 2006.173.20:35:59.96#ibcon#read 5, iclass 29, count 0 2006.173.20:35:59.96#ibcon#about to read 6, iclass 29, count 0 2006.173.20:35:59.96#ibcon#read 6, iclass 29, count 0 2006.173.20:35:59.96#ibcon#end of sib2, iclass 29, count 0 2006.173.20:35:59.96#ibcon#*mode == 0, iclass 29, count 0 2006.173.20:35:59.96#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.20:35:59.96#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.20:35:59.96#ibcon#*before write, iclass 29, count 0 2006.173.20:35:59.96#ibcon#enter sib2, iclass 29, count 0 2006.173.20:35:59.96#ibcon#flushed, iclass 29, count 0 2006.173.20:35:59.96#ibcon#about to write, iclass 29, count 0 2006.173.20:35:59.96#ibcon#wrote, iclass 29, count 0 2006.173.20:35:59.96#ibcon#about to read 3, iclass 29, count 0 2006.173.20:36:00.00#ibcon#read 3, iclass 29, count 0 2006.173.20:36:00.00#ibcon#about to read 4, iclass 29, count 0 2006.173.20:36:00.00#ibcon#read 4, iclass 29, count 0 2006.173.20:36:00.00#ibcon#about to read 5, iclass 29, count 0 2006.173.20:36:00.00#ibcon#read 5, iclass 29, count 0 2006.173.20:36:00.00#ibcon#about to read 6, iclass 29, count 0 2006.173.20:36:00.00#ibcon#read 6, iclass 29, count 0 2006.173.20:36:00.00#ibcon#end of sib2, iclass 29, count 0 2006.173.20:36:00.00#ibcon#*after write, iclass 29, count 0 2006.173.20:36:00.00#ibcon#*before return 0, iclass 29, count 0 2006.173.20:36:00.00#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.20:36:00.00#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.20:36:00.00#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.20:36:00.00#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.20:36:00.00$vck44/vb=7,4 2006.173.20:36:00.00#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.20:36:00.00#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.20:36:00.00#ibcon#ireg 11 cls_cnt 2 2006.173.20:36:00.00#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.20:36:00.06#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.20:36:00.06#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.20:36:00.06#ibcon#enter wrdev, iclass 31, count 2 2006.173.20:36:00.06#ibcon#first serial, iclass 31, count 2 2006.173.20:36:00.06#ibcon#enter sib2, iclass 31, count 2 2006.173.20:36:00.06#ibcon#flushed, iclass 31, count 2 2006.173.20:36:00.06#ibcon#about to write, iclass 31, count 2 2006.173.20:36:00.06#ibcon#wrote, iclass 31, count 2 2006.173.20:36:00.06#ibcon#about to read 3, iclass 31, count 2 2006.173.20:36:00.08#ibcon#read 3, iclass 31, count 2 2006.173.20:36:00.08#ibcon#about to read 4, iclass 31, count 2 2006.173.20:36:00.08#ibcon#read 4, iclass 31, count 2 2006.173.20:36:00.08#ibcon#about to read 5, iclass 31, count 2 2006.173.20:36:00.08#ibcon#read 5, iclass 31, count 2 2006.173.20:36:00.08#ibcon#about to read 6, iclass 31, count 2 2006.173.20:36:00.08#ibcon#read 6, iclass 31, count 2 2006.173.20:36:00.08#ibcon#end of sib2, iclass 31, count 2 2006.173.20:36:00.08#ibcon#*mode == 0, iclass 31, count 2 2006.173.20:36:00.08#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.20:36:00.08#ibcon#[27=AT07-04\r\n] 2006.173.20:36:00.08#ibcon#*before write, iclass 31, count 2 2006.173.20:36:00.08#ibcon#enter sib2, iclass 31, count 2 2006.173.20:36:00.08#ibcon#flushed, iclass 31, count 2 2006.173.20:36:00.08#ibcon#about to write, iclass 31, count 2 2006.173.20:36:00.08#ibcon#wrote, iclass 31, count 2 2006.173.20:36:00.08#ibcon#about to read 3, iclass 31, count 2 2006.173.20:36:00.11#ibcon#read 3, iclass 31, count 2 2006.173.20:36:00.11#ibcon#about to read 4, iclass 31, count 2 2006.173.20:36:00.11#ibcon#read 4, iclass 31, count 2 2006.173.20:36:00.11#ibcon#about to read 5, iclass 31, count 2 2006.173.20:36:00.11#ibcon#read 5, iclass 31, count 2 2006.173.20:36:00.11#ibcon#about to read 6, iclass 31, count 2 2006.173.20:36:00.11#ibcon#read 6, iclass 31, count 2 2006.173.20:36:00.11#ibcon#end of sib2, iclass 31, count 2 2006.173.20:36:00.11#ibcon#*after write, iclass 31, count 2 2006.173.20:36:00.11#ibcon#*before return 0, iclass 31, count 2 2006.173.20:36:00.11#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.20:36:00.11#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.20:36:00.11#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.20:36:00.11#ibcon#ireg 7 cls_cnt 0 2006.173.20:36:00.11#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.20:36:00.23#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.20:36:00.23#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.20:36:00.23#ibcon#enter wrdev, iclass 31, count 0 2006.173.20:36:00.23#ibcon#first serial, iclass 31, count 0 2006.173.20:36:00.23#ibcon#enter sib2, iclass 31, count 0 2006.173.20:36:00.23#ibcon#flushed, iclass 31, count 0 2006.173.20:36:00.23#ibcon#about to write, iclass 31, count 0 2006.173.20:36:00.23#ibcon#wrote, iclass 31, count 0 2006.173.20:36:00.23#ibcon#about to read 3, iclass 31, count 0 2006.173.20:36:00.25#ibcon#read 3, iclass 31, count 0 2006.173.20:36:00.25#ibcon#about to read 4, iclass 31, count 0 2006.173.20:36:00.25#ibcon#read 4, iclass 31, count 0 2006.173.20:36:00.25#ibcon#about to read 5, iclass 31, count 0 2006.173.20:36:00.25#ibcon#read 5, iclass 31, count 0 2006.173.20:36:00.25#ibcon#about to read 6, iclass 31, count 0 2006.173.20:36:00.25#ibcon#read 6, iclass 31, count 0 2006.173.20:36:00.25#ibcon#end of sib2, iclass 31, count 0 2006.173.20:36:00.25#ibcon#*mode == 0, iclass 31, count 0 2006.173.20:36:00.25#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.20:36:00.25#ibcon#[27=USB\r\n] 2006.173.20:36:00.25#ibcon#*before write, iclass 31, count 0 2006.173.20:36:00.25#ibcon#enter sib2, iclass 31, count 0 2006.173.20:36:00.25#ibcon#flushed, iclass 31, count 0 2006.173.20:36:00.25#ibcon#about to write, iclass 31, count 0 2006.173.20:36:00.25#ibcon#wrote, iclass 31, count 0 2006.173.20:36:00.25#ibcon#about to read 3, iclass 31, count 0 2006.173.20:36:00.28#ibcon#read 3, iclass 31, count 0 2006.173.20:36:00.28#ibcon#about to read 4, iclass 31, count 0 2006.173.20:36:00.28#ibcon#read 4, iclass 31, count 0 2006.173.20:36:00.28#ibcon#about to read 5, iclass 31, count 0 2006.173.20:36:00.28#ibcon#read 5, iclass 31, count 0 2006.173.20:36:00.28#ibcon#about to read 6, iclass 31, count 0 2006.173.20:36:00.28#ibcon#read 6, iclass 31, count 0 2006.173.20:36:00.28#ibcon#end of sib2, iclass 31, count 0 2006.173.20:36:00.28#ibcon#*after write, iclass 31, count 0 2006.173.20:36:00.28#ibcon#*before return 0, iclass 31, count 0 2006.173.20:36:00.28#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.20:36:00.28#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.20:36:00.28#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.20:36:00.28#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.20:36:00.28$vck44/vblo=8,744.99 2006.173.20:36:00.28#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.20:36:00.28#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.20:36:00.28#ibcon#ireg 17 cls_cnt 0 2006.173.20:36:00.28#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.20:36:00.28#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.20:36:00.28#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.20:36:00.28#ibcon#enter wrdev, iclass 33, count 0 2006.173.20:36:00.28#ibcon#first serial, iclass 33, count 0 2006.173.20:36:00.28#ibcon#enter sib2, iclass 33, count 0 2006.173.20:36:00.28#ibcon#flushed, iclass 33, count 0 2006.173.20:36:00.28#ibcon#about to write, iclass 33, count 0 2006.173.20:36:00.28#ibcon#wrote, iclass 33, count 0 2006.173.20:36:00.28#ibcon#about to read 3, iclass 33, count 0 2006.173.20:36:00.30#ibcon#read 3, iclass 33, count 0 2006.173.20:36:00.30#ibcon#about to read 4, iclass 33, count 0 2006.173.20:36:00.30#ibcon#read 4, iclass 33, count 0 2006.173.20:36:00.30#ibcon#about to read 5, iclass 33, count 0 2006.173.20:36:00.30#ibcon#read 5, iclass 33, count 0 2006.173.20:36:00.30#ibcon#about to read 6, iclass 33, count 0 2006.173.20:36:00.30#ibcon#read 6, iclass 33, count 0 2006.173.20:36:00.30#ibcon#end of sib2, iclass 33, count 0 2006.173.20:36:00.30#ibcon#*mode == 0, iclass 33, count 0 2006.173.20:36:00.30#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.20:36:00.30#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.20:36:00.30#ibcon#*before write, iclass 33, count 0 2006.173.20:36:00.30#ibcon#enter sib2, iclass 33, count 0 2006.173.20:36:00.30#ibcon#flushed, iclass 33, count 0 2006.173.20:36:00.30#ibcon#about to write, iclass 33, count 0 2006.173.20:36:00.30#ibcon#wrote, iclass 33, count 0 2006.173.20:36:00.30#ibcon#about to read 3, iclass 33, count 0 2006.173.20:36:00.34#ibcon#read 3, iclass 33, count 0 2006.173.20:36:00.34#ibcon#about to read 4, iclass 33, count 0 2006.173.20:36:00.34#ibcon#read 4, iclass 33, count 0 2006.173.20:36:00.34#ibcon#about to read 5, iclass 33, count 0 2006.173.20:36:00.34#ibcon#read 5, iclass 33, count 0 2006.173.20:36:00.34#ibcon#about to read 6, iclass 33, count 0 2006.173.20:36:00.34#ibcon#read 6, iclass 33, count 0 2006.173.20:36:00.34#ibcon#end of sib2, iclass 33, count 0 2006.173.20:36:00.34#ibcon#*after write, iclass 33, count 0 2006.173.20:36:00.34#ibcon#*before return 0, iclass 33, count 0 2006.173.20:36:00.34#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.20:36:00.34#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.20:36:00.34#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.20:36:00.34#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.20:36:00.34$vck44/vb=8,4 2006.173.20:36:00.34#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.20:36:00.34#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.20:36:00.34#ibcon#ireg 11 cls_cnt 2 2006.173.20:36:00.34#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.20:36:00.40#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.20:36:00.40#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.20:36:00.40#ibcon#enter wrdev, iclass 35, count 2 2006.173.20:36:00.40#ibcon#first serial, iclass 35, count 2 2006.173.20:36:00.40#ibcon#enter sib2, iclass 35, count 2 2006.173.20:36:00.40#ibcon#flushed, iclass 35, count 2 2006.173.20:36:00.40#ibcon#about to write, iclass 35, count 2 2006.173.20:36:00.40#ibcon#wrote, iclass 35, count 2 2006.173.20:36:00.40#ibcon#about to read 3, iclass 35, count 2 2006.173.20:36:00.42#ibcon#read 3, iclass 35, count 2 2006.173.20:36:00.42#ibcon#about to read 4, iclass 35, count 2 2006.173.20:36:00.42#ibcon#read 4, iclass 35, count 2 2006.173.20:36:00.42#ibcon#about to read 5, iclass 35, count 2 2006.173.20:36:00.42#ibcon#read 5, iclass 35, count 2 2006.173.20:36:00.42#ibcon#about to read 6, iclass 35, count 2 2006.173.20:36:00.42#ibcon#read 6, iclass 35, count 2 2006.173.20:36:00.42#ibcon#end of sib2, iclass 35, count 2 2006.173.20:36:00.42#ibcon#*mode == 0, iclass 35, count 2 2006.173.20:36:00.42#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.20:36:00.42#ibcon#[27=AT08-04\r\n] 2006.173.20:36:00.42#ibcon#*before write, iclass 35, count 2 2006.173.20:36:00.42#ibcon#enter sib2, iclass 35, count 2 2006.173.20:36:00.42#ibcon#flushed, iclass 35, count 2 2006.173.20:36:00.42#ibcon#about to write, iclass 35, count 2 2006.173.20:36:00.42#ibcon#wrote, iclass 35, count 2 2006.173.20:36:00.42#ibcon#about to read 3, iclass 35, count 2 2006.173.20:36:00.45#ibcon#read 3, iclass 35, count 2 2006.173.20:36:00.45#ibcon#about to read 4, iclass 35, count 2 2006.173.20:36:00.45#ibcon#read 4, iclass 35, count 2 2006.173.20:36:00.45#ibcon#about to read 5, iclass 35, count 2 2006.173.20:36:00.45#ibcon#read 5, iclass 35, count 2 2006.173.20:36:00.45#ibcon#about to read 6, iclass 35, count 2 2006.173.20:36:00.45#ibcon#read 6, iclass 35, count 2 2006.173.20:36:00.45#ibcon#end of sib2, iclass 35, count 2 2006.173.20:36:00.45#ibcon#*after write, iclass 35, count 2 2006.173.20:36:00.45#ibcon#*before return 0, iclass 35, count 2 2006.173.20:36:00.45#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.20:36:00.45#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.20:36:00.45#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.20:36:00.45#ibcon#ireg 7 cls_cnt 0 2006.173.20:36:00.45#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.20:36:00.57#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.20:36:00.57#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.20:36:00.57#ibcon#enter wrdev, iclass 35, count 0 2006.173.20:36:00.57#ibcon#first serial, iclass 35, count 0 2006.173.20:36:00.57#ibcon#enter sib2, iclass 35, count 0 2006.173.20:36:00.57#ibcon#flushed, iclass 35, count 0 2006.173.20:36:00.57#ibcon#about to write, iclass 35, count 0 2006.173.20:36:00.57#ibcon#wrote, iclass 35, count 0 2006.173.20:36:00.57#ibcon#about to read 3, iclass 35, count 0 2006.173.20:36:00.59#ibcon#read 3, iclass 35, count 0 2006.173.20:36:00.59#ibcon#about to read 4, iclass 35, count 0 2006.173.20:36:00.59#ibcon#read 4, iclass 35, count 0 2006.173.20:36:00.59#ibcon#about to read 5, iclass 35, count 0 2006.173.20:36:00.59#ibcon#read 5, iclass 35, count 0 2006.173.20:36:00.59#ibcon#about to read 6, iclass 35, count 0 2006.173.20:36:00.59#ibcon#read 6, iclass 35, count 0 2006.173.20:36:00.59#ibcon#end of sib2, iclass 35, count 0 2006.173.20:36:00.59#ibcon#*mode == 0, iclass 35, count 0 2006.173.20:36:00.59#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.20:36:00.59#ibcon#[27=USB\r\n] 2006.173.20:36:00.59#ibcon#*before write, iclass 35, count 0 2006.173.20:36:00.59#ibcon#enter sib2, iclass 35, count 0 2006.173.20:36:00.59#ibcon#flushed, iclass 35, count 0 2006.173.20:36:00.59#ibcon#about to write, iclass 35, count 0 2006.173.20:36:00.59#ibcon#wrote, iclass 35, count 0 2006.173.20:36:00.59#ibcon#about to read 3, iclass 35, count 0 2006.173.20:36:00.62#ibcon#read 3, iclass 35, count 0 2006.173.20:36:00.62#ibcon#about to read 4, iclass 35, count 0 2006.173.20:36:00.62#ibcon#read 4, iclass 35, count 0 2006.173.20:36:00.62#ibcon#about to read 5, iclass 35, count 0 2006.173.20:36:00.62#ibcon#read 5, iclass 35, count 0 2006.173.20:36:00.62#ibcon#about to read 6, iclass 35, count 0 2006.173.20:36:00.62#ibcon#read 6, iclass 35, count 0 2006.173.20:36:00.62#ibcon#end of sib2, iclass 35, count 0 2006.173.20:36:00.62#ibcon#*after write, iclass 35, count 0 2006.173.20:36:00.62#ibcon#*before return 0, iclass 35, count 0 2006.173.20:36:00.62#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.20:36:00.62#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.20:36:00.62#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.20:36:00.62#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.20:36:00.62$vck44/vabw=wide 2006.173.20:36:00.62#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.20:36:00.62#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.20:36:00.62#ibcon#ireg 8 cls_cnt 0 2006.173.20:36:00.62#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.20:36:00.62#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.20:36:00.62#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.20:36:00.62#ibcon#enter wrdev, iclass 37, count 0 2006.173.20:36:00.62#ibcon#first serial, iclass 37, count 0 2006.173.20:36:00.62#ibcon#enter sib2, iclass 37, count 0 2006.173.20:36:00.62#ibcon#flushed, iclass 37, count 0 2006.173.20:36:00.62#ibcon#about to write, iclass 37, count 0 2006.173.20:36:00.62#ibcon#wrote, iclass 37, count 0 2006.173.20:36:00.62#ibcon#about to read 3, iclass 37, count 0 2006.173.20:36:00.64#ibcon#read 3, iclass 37, count 0 2006.173.20:36:00.64#ibcon#about to read 4, iclass 37, count 0 2006.173.20:36:00.64#ibcon#read 4, iclass 37, count 0 2006.173.20:36:00.64#ibcon#about to read 5, iclass 37, count 0 2006.173.20:36:00.64#ibcon#read 5, iclass 37, count 0 2006.173.20:36:00.64#ibcon#about to read 6, iclass 37, count 0 2006.173.20:36:00.64#ibcon#read 6, iclass 37, count 0 2006.173.20:36:00.64#ibcon#end of sib2, iclass 37, count 0 2006.173.20:36:00.64#ibcon#*mode == 0, iclass 37, count 0 2006.173.20:36:00.64#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.20:36:00.64#ibcon#[25=BW32\r\n] 2006.173.20:36:00.64#ibcon#*before write, iclass 37, count 0 2006.173.20:36:00.64#ibcon#enter sib2, iclass 37, count 0 2006.173.20:36:00.64#ibcon#flushed, iclass 37, count 0 2006.173.20:36:00.64#ibcon#about to write, iclass 37, count 0 2006.173.20:36:00.64#ibcon#wrote, iclass 37, count 0 2006.173.20:36:00.64#ibcon#about to read 3, iclass 37, count 0 2006.173.20:36:00.67#ibcon#read 3, iclass 37, count 0 2006.173.20:36:00.67#ibcon#about to read 4, iclass 37, count 0 2006.173.20:36:00.67#ibcon#read 4, iclass 37, count 0 2006.173.20:36:00.67#ibcon#about to read 5, iclass 37, count 0 2006.173.20:36:00.67#ibcon#read 5, iclass 37, count 0 2006.173.20:36:00.67#ibcon#about to read 6, iclass 37, count 0 2006.173.20:36:00.67#ibcon#read 6, iclass 37, count 0 2006.173.20:36:00.67#ibcon#end of sib2, iclass 37, count 0 2006.173.20:36:00.67#ibcon#*after write, iclass 37, count 0 2006.173.20:36:00.67#ibcon#*before return 0, iclass 37, count 0 2006.173.20:36:00.67#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.20:36:00.67#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.20:36:00.67#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.20:36:00.67#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.20:36:00.67$vck44/vbbw=wide 2006.173.20:36:00.67#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.20:36:00.67#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.20:36:00.67#ibcon#ireg 8 cls_cnt 0 2006.173.20:36:00.67#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.20:36:00.74#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.20:36:00.74#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.20:36:00.74#ibcon#enter wrdev, iclass 39, count 0 2006.173.20:36:00.74#ibcon#first serial, iclass 39, count 0 2006.173.20:36:00.74#ibcon#enter sib2, iclass 39, count 0 2006.173.20:36:00.74#ibcon#flushed, iclass 39, count 0 2006.173.20:36:00.74#ibcon#about to write, iclass 39, count 0 2006.173.20:36:00.74#ibcon#wrote, iclass 39, count 0 2006.173.20:36:00.74#ibcon#about to read 3, iclass 39, count 0 2006.173.20:36:00.76#ibcon#read 3, iclass 39, count 0 2006.173.20:36:00.76#ibcon#about to read 4, iclass 39, count 0 2006.173.20:36:00.76#ibcon#read 4, iclass 39, count 0 2006.173.20:36:00.76#ibcon#about to read 5, iclass 39, count 0 2006.173.20:36:00.76#ibcon#read 5, iclass 39, count 0 2006.173.20:36:00.76#ibcon#about to read 6, iclass 39, count 0 2006.173.20:36:00.76#ibcon#read 6, iclass 39, count 0 2006.173.20:36:00.76#ibcon#end of sib2, iclass 39, count 0 2006.173.20:36:00.76#ibcon#*mode == 0, iclass 39, count 0 2006.173.20:36:00.76#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.20:36:00.76#ibcon#[27=BW32\r\n] 2006.173.20:36:00.76#ibcon#*before write, iclass 39, count 0 2006.173.20:36:00.76#ibcon#enter sib2, iclass 39, count 0 2006.173.20:36:00.76#ibcon#flushed, iclass 39, count 0 2006.173.20:36:00.76#ibcon#about to write, iclass 39, count 0 2006.173.20:36:00.76#ibcon#wrote, iclass 39, count 0 2006.173.20:36:00.76#ibcon#about to read 3, iclass 39, count 0 2006.173.20:36:00.79#ibcon#read 3, iclass 39, count 0 2006.173.20:36:00.79#ibcon#about to read 4, iclass 39, count 0 2006.173.20:36:00.79#ibcon#read 4, iclass 39, count 0 2006.173.20:36:00.79#ibcon#about to read 5, iclass 39, count 0 2006.173.20:36:00.79#ibcon#read 5, iclass 39, count 0 2006.173.20:36:00.79#ibcon#about to read 6, iclass 39, count 0 2006.173.20:36:00.79#ibcon#read 6, iclass 39, count 0 2006.173.20:36:00.79#ibcon#end of sib2, iclass 39, count 0 2006.173.20:36:00.79#ibcon#*after write, iclass 39, count 0 2006.173.20:36:00.79#ibcon#*before return 0, iclass 39, count 0 2006.173.20:36:00.79#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.20:36:00.79#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.20:36:00.79#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.20:36:00.79#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.20:36:00.79$setupk4/ifdk4 2006.173.20:36:00.79$ifdk4/lo= 2006.173.20:36:00.79$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.20:36:00.79$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.20:36:00.79$ifdk4/patch= 2006.173.20:36:00.79$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.20:36:00.79$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.20:36:00.80$setupk4/!*+20s 2006.173.20:36:03.82#abcon#<5=/06 0.8 1.3 20.141001002.9\r\n> 2006.173.20:36:03.84#abcon#{5=INTERFACE CLEAR} 2006.173.20:36:03.90#abcon#[5=S1D000X0/0*\r\n] 2006.173.20:36:06.14#trakl#Source acquired 2006.173.20:36:07.13#flagr#flagr/antenna,acquired 2006.173.20:36:11.04$setupk4/"tpicd 2006.173.20:36:11.04$setupk4/echo=off 2006.173.20:36:11.04$setupk4/xlog=off 2006.173.20:36:11.04:!2006.173.20:36:06 2006.173.20:36:11.04:preob 2006.173.20:36:12.13/onsource/TRACKING 2006.173.20:36:12.13:!2006.173.20:36:16 2006.173.20:36:16.00:"tape 2006.173.20:36:16.00:"st=record 2006.173.20:36:16.00:data_valid=on 2006.173.20:36:16.00:midob 2006.173.20:36:16.13/onsource/TRACKING 2006.173.20:36:16.13/wx/20.15,1002.9,100 2006.173.20:36:16.29/cable/+6.5162E-03 2006.173.20:36:17.38/va/01,07,usb,yes,35,37 2006.173.20:36:17.38/va/02,06,usb,yes,34,35 2006.173.20:36:17.38/va/03,05,usb,yes,44,46 2006.173.20:36:17.38/va/04,06,usb,yes,35,37 2006.173.20:36:17.38/va/05,04,usb,yes,28,28 2006.173.20:36:17.38/va/06,03,usb,yes,39,39 2006.173.20:36:17.38/va/07,04,usb,yes,31,32 2006.173.20:36:17.38/va/08,04,usb,yes,27,32 2006.173.20:36:17.61/valo/01,524.99,yes,locked 2006.173.20:36:17.61/valo/02,534.99,yes,locked 2006.173.20:36:17.61/valo/03,564.99,yes,locked 2006.173.20:36:17.61/valo/04,624.99,yes,locked 2006.173.20:36:17.61/valo/05,734.99,yes,locked 2006.173.20:36:17.61/valo/06,814.99,yes,locked 2006.173.20:36:17.61/valo/07,864.99,yes,locked 2006.173.20:36:17.61/valo/08,884.99,yes,locked 2006.173.20:36:18.70/vb/01,04,usb,yes,29,27 2006.173.20:36:18.70/vb/02,04,usb,yes,31,31 2006.173.20:36:18.70/vb/03,04,usb,yes,28,31 2006.173.20:36:18.70/vb/04,04,usb,yes,32,31 2006.173.20:36:18.70/vb/05,04,usb,yes,25,27 2006.173.20:36:18.70/vb/06,04,usb,yes,29,26 2006.173.20:36:18.70/vb/07,04,usb,yes,29,29 2006.173.20:36:18.70/vb/08,04,usb,yes,27,30 2006.173.20:36:18.94/vblo/01,629.99,yes,locked 2006.173.20:36:18.94/vblo/02,634.99,yes,locked 2006.173.20:36:18.94/vblo/03,649.99,yes,locked 2006.173.20:36:18.94/vblo/04,679.99,yes,locked 2006.173.20:36:18.94/vblo/05,709.99,yes,locked 2006.173.20:36:18.94/vblo/06,719.99,yes,locked 2006.173.20:36:18.94/vblo/07,734.99,yes,locked 2006.173.20:36:18.94/vblo/08,744.99,yes,locked 2006.173.20:36:19.09/vabw/8 2006.173.20:36:19.24/vbbw/8 2006.173.20:36:19.33/xfe/off,on,14.7 2006.173.20:36:19.71/ifatt/23,28,28,28 2006.173.20:36:20.07/fmout-gps/S +3.89E-07 2006.173.20:36:20.11:!2006.173.20:39:56 2006.173.20:39:56.01:data_valid=off 2006.173.20:39:56.01:"et 2006.173.20:39:56.01:!+3s 2006.173.20:39:59.02:"tape 2006.173.20:39:59.02:postob 2006.173.20:39:59.24/cable/+6.5160E-03 2006.173.20:39:59.24/wx/20.34,1003.0,100 2006.173.20:39:59.30/fmout-gps/S +3.88E-07 2006.173.20:39:59.30:scan_name=173-2049,jd0606,50 2006.173.20:39:59.30:source=0552+398,055530.81,394849.2,2000.0,cw 2006.173.20:40:01.14#flagr#flagr/antenna,new-source 2006.173.20:40:01.14:checkk5 2006.173.20:40:01.54/chk_autoobs//k5ts1/ autoobs is running! 2006.173.20:40:01.95/chk_autoobs//k5ts2/ autoobs is running! 2006.173.20:40:02.36/chk_autoobs//k5ts3/ autoobs is running! 2006.173.20:40:02.77/chk_autoobs//k5ts4/ autoobs is running! 2006.173.20:40:03.16/chk_obsdata//k5ts1/T1732036??a.dat file size is correct (nominal:880MB, actual:880MB). 2006.173.20:40:03.57/chk_obsdata//k5ts2/T1732036??b.dat file size is correct (nominal:880MB, actual:880MB). 2006.173.20:40:03.98/chk_obsdata//k5ts3/T1732036??c.dat file size is correct (nominal:880MB, actual:880MB). 2006.173.20:40:04.37/chk_obsdata//k5ts4/T1732036??d.dat file size is correct (nominal:880MB, actual:880MB). 2006.173.20:40:05.06/k5log//k5ts1_log_newline 2006.173.20:40:05.76/k5log//k5ts2_log_newline 2006.173.20:40:06.50/k5log//k5ts3_log_newline 2006.173.20:40:07.19/k5log//k5ts4_log_newline 2006.173.20:40:07.21/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.20:40:07.21:setupk4=1 2006.173.20:40:07.21$setupk4/echo=on 2006.173.20:40:07.21$setupk4/pcalon 2006.173.20:40:07.21$pcalon/"no phase cal control is implemented here 2006.173.20:40:07.21$setupk4/"tpicd=stop 2006.173.20:40:07.21$setupk4/"rec=synch_on 2006.173.20:40:07.21$setupk4/"rec_mode=128 2006.173.20:40:07.21$setupk4/!* 2006.173.20:40:07.21$setupk4/recpk4 2006.173.20:40:07.21$recpk4/recpatch= 2006.173.20:40:07.22$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.20:40:07.22$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.20:40:07.22$setupk4/vck44 2006.173.20:40:07.22$vck44/valo=1,524.99 2006.173.20:40:07.22#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.20:40:07.22#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.20:40:07.22#ibcon#ireg 17 cls_cnt 0 2006.173.20:40:07.22#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.20:40:07.22#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.20:40:07.22#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.20:40:07.22#ibcon#enter wrdev, iclass 32, count 0 2006.173.20:40:07.22#ibcon#first serial, iclass 32, count 0 2006.173.20:40:07.22#ibcon#enter sib2, iclass 32, count 0 2006.173.20:40:07.22#ibcon#flushed, iclass 32, count 0 2006.173.20:40:07.22#ibcon#about to write, iclass 32, count 0 2006.173.20:40:07.22#ibcon#wrote, iclass 32, count 0 2006.173.20:40:07.22#ibcon#about to read 3, iclass 32, count 0 2006.173.20:40:07.24#ibcon#read 3, iclass 32, count 0 2006.173.20:40:07.24#ibcon#about to read 4, iclass 32, count 0 2006.173.20:40:07.24#ibcon#read 4, iclass 32, count 0 2006.173.20:40:07.24#ibcon#about to read 5, iclass 32, count 0 2006.173.20:40:07.24#ibcon#read 5, iclass 32, count 0 2006.173.20:40:07.24#ibcon#about to read 6, iclass 32, count 0 2006.173.20:40:07.24#ibcon#read 6, iclass 32, count 0 2006.173.20:40:07.24#ibcon#end of sib2, iclass 32, count 0 2006.173.20:40:07.24#ibcon#*mode == 0, iclass 32, count 0 2006.173.20:40:07.24#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.20:40:07.24#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.20:40:07.24#ibcon#*before write, iclass 32, count 0 2006.173.20:40:07.24#ibcon#enter sib2, iclass 32, count 0 2006.173.20:40:07.24#ibcon#flushed, iclass 32, count 0 2006.173.20:40:07.24#ibcon#about to write, iclass 32, count 0 2006.173.20:40:07.24#ibcon#wrote, iclass 32, count 0 2006.173.20:40:07.24#ibcon#about to read 3, iclass 32, count 0 2006.173.20:40:07.29#ibcon#read 3, iclass 32, count 0 2006.173.20:40:07.29#ibcon#about to read 4, iclass 32, count 0 2006.173.20:40:07.29#ibcon#read 4, iclass 32, count 0 2006.173.20:40:07.29#ibcon#about to read 5, iclass 32, count 0 2006.173.20:40:07.29#ibcon#read 5, iclass 32, count 0 2006.173.20:40:07.29#ibcon#about to read 6, iclass 32, count 0 2006.173.20:40:07.29#ibcon#read 6, iclass 32, count 0 2006.173.20:40:07.29#ibcon#end of sib2, iclass 32, count 0 2006.173.20:40:07.29#ibcon#*after write, iclass 32, count 0 2006.173.20:40:07.29#ibcon#*before return 0, iclass 32, count 0 2006.173.20:40:07.29#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.20:40:07.29#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.20:40:07.29#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.20:40:07.29#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.20:40:07.29$vck44/va=1,7 2006.173.20:40:07.29#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.20:40:07.29#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.20:40:07.29#ibcon#ireg 11 cls_cnt 2 2006.173.20:40:07.29#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.20:40:07.29#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.20:40:07.29#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.20:40:07.29#ibcon#enter wrdev, iclass 34, count 2 2006.173.20:40:07.29#ibcon#first serial, iclass 34, count 2 2006.173.20:40:07.29#ibcon#enter sib2, iclass 34, count 2 2006.173.20:40:07.29#ibcon#flushed, iclass 34, count 2 2006.173.20:40:07.29#ibcon#about to write, iclass 34, count 2 2006.173.20:40:07.29#ibcon#wrote, iclass 34, count 2 2006.173.20:40:07.29#ibcon#about to read 3, iclass 34, count 2 2006.173.20:40:07.31#ibcon#read 3, iclass 34, count 2 2006.173.20:40:07.31#ibcon#about to read 4, iclass 34, count 2 2006.173.20:40:07.31#ibcon#read 4, iclass 34, count 2 2006.173.20:40:07.31#ibcon#about to read 5, iclass 34, count 2 2006.173.20:40:07.31#ibcon#read 5, iclass 34, count 2 2006.173.20:40:07.31#ibcon#about to read 6, iclass 34, count 2 2006.173.20:40:07.31#ibcon#read 6, iclass 34, count 2 2006.173.20:40:07.31#ibcon#end of sib2, iclass 34, count 2 2006.173.20:40:07.31#ibcon#*mode == 0, iclass 34, count 2 2006.173.20:40:07.31#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.20:40:07.31#ibcon#[25=AT01-07\r\n] 2006.173.20:40:07.31#ibcon#*before write, iclass 34, count 2 2006.173.20:40:07.31#ibcon#enter sib2, iclass 34, count 2 2006.173.20:40:07.31#ibcon#flushed, iclass 34, count 2 2006.173.20:40:07.31#ibcon#about to write, iclass 34, count 2 2006.173.20:40:07.31#ibcon#wrote, iclass 34, count 2 2006.173.20:40:07.31#ibcon#about to read 3, iclass 34, count 2 2006.173.20:40:07.34#ibcon#read 3, iclass 34, count 2 2006.173.20:40:07.34#ibcon#about to read 4, iclass 34, count 2 2006.173.20:40:07.34#ibcon#read 4, iclass 34, count 2 2006.173.20:40:07.34#ibcon#about to read 5, iclass 34, count 2 2006.173.20:40:07.34#ibcon#read 5, iclass 34, count 2 2006.173.20:40:07.34#ibcon#about to read 6, iclass 34, count 2 2006.173.20:40:07.34#ibcon#read 6, iclass 34, count 2 2006.173.20:40:07.34#ibcon#end of sib2, iclass 34, count 2 2006.173.20:40:07.34#ibcon#*after write, iclass 34, count 2 2006.173.20:40:07.34#ibcon#*before return 0, iclass 34, count 2 2006.173.20:40:07.34#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.20:40:07.34#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.20:40:07.34#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.20:40:07.34#ibcon#ireg 7 cls_cnt 0 2006.173.20:40:07.34#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.20:40:07.46#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.20:40:07.46#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.20:40:07.46#ibcon#enter wrdev, iclass 34, count 0 2006.173.20:40:07.46#ibcon#first serial, iclass 34, count 0 2006.173.20:40:07.46#ibcon#enter sib2, iclass 34, count 0 2006.173.20:40:07.46#ibcon#flushed, iclass 34, count 0 2006.173.20:40:07.46#ibcon#about to write, iclass 34, count 0 2006.173.20:40:07.46#ibcon#wrote, iclass 34, count 0 2006.173.20:40:07.46#ibcon#about to read 3, iclass 34, count 0 2006.173.20:40:07.48#ibcon#read 3, iclass 34, count 0 2006.173.20:40:07.48#ibcon#about to read 4, iclass 34, count 0 2006.173.20:40:07.48#ibcon#read 4, iclass 34, count 0 2006.173.20:40:07.48#ibcon#about to read 5, iclass 34, count 0 2006.173.20:40:07.48#ibcon#read 5, iclass 34, count 0 2006.173.20:40:07.48#ibcon#about to read 6, iclass 34, count 0 2006.173.20:40:07.48#ibcon#read 6, iclass 34, count 0 2006.173.20:40:07.48#ibcon#end of sib2, iclass 34, count 0 2006.173.20:40:07.48#ibcon#*mode == 0, iclass 34, count 0 2006.173.20:40:07.48#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.20:40:07.48#ibcon#[25=USB\r\n] 2006.173.20:40:07.48#ibcon#*before write, iclass 34, count 0 2006.173.20:40:07.48#ibcon#enter sib2, iclass 34, count 0 2006.173.20:40:07.48#ibcon#flushed, iclass 34, count 0 2006.173.20:40:07.48#ibcon#about to write, iclass 34, count 0 2006.173.20:40:07.48#ibcon#wrote, iclass 34, count 0 2006.173.20:40:07.48#ibcon#about to read 3, iclass 34, count 0 2006.173.20:40:07.51#ibcon#read 3, iclass 34, count 0 2006.173.20:40:07.51#ibcon#about to read 4, iclass 34, count 0 2006.173.20:40:07.51#ibcon#read 4, iclass 34, count 0 2006.173.20:40:07.51#ibcon#about to read 5, iclass 34, count 0 2006.173.20:40:07.51#ibcon#read 5, iclass 34, count 0 2006.173.20:40:07.51#ibcon#about to read 6, iclass 34, count 0 2006.173.20:40:07.51#ibcon#read 6, iclass 34, count 0 2006.173.20:40:07.51#ibcon#end of sib2, iclass 34, count 0 2006.173.20:40:07.51#ibcon#*after write, iclass 34, count 0 2006.173.20:40:07.51#ibcon#*before return 0, iclass 34, count 0 2006.173.20:40:07.51#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.20:40:07.51#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.20:40:07.51#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.20:40:07.51#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.20:40:07.51$vck44/valo=2,534.99 2006.173.20:40:07.51#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.20:40:07.51#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.20:40:07.51#ibcon#ireg 17 cls_cnt 0 2006.173.20:40:07.51#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.20:40:07.51#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.20:40:07.51#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.20:40:07.51#ibcon#enter wrdev, iclass 36, count 0 2006.173.20:40:07.51#ibcon#first serial, iclass 36, count 0 2006.173.20:40:07.51#ibcon#enter sib2, iclass 36, count 0 2006.173.20:40:07.51#ibcon#flushed, iclass 36, count 0 2006.173.20:40:07.51#ibcon#about to write, iclass 36, count 0 2006.173.20:40:07.51#ibcon#wrote, iclass 36, count 0 2006.173.20:40:07.51#ibcon#about to read 3, iclass 36, count 0 2006.173.20:40:07.53#ibcon#read 3, iclass 36, count 0 2006.173.20:40:07.53#ibcon#about to read 4, iclass 36, count 0 2006.173.20:40:07.53#ibcon#read 4, iclass 36, count 0 2006.173.20:40:07.53#ibcon#about to read 5, iclass 36, count 0 2006.173.20:40:07.53#ibcon#read 5, iclass 36, count 0 2006.173.20:40:07.53#ibcon#about to read 6, iclass 36, count 0 2006.173.20:40:07.53#ibcon#read 6, iclass 36, count 0 2006.173.20:40:07.53#ibcon#end of sib2, iclass 36, count 0 2006.173.20:40:07.53#ibcon#*mode == 0, iclass 36, count 0 2006.173.20:40:07.53#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.20:40:07.53#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.20:40:07.53#ibcon#*before write, iclass 36, count 0 2006.173.20:40:07.53#ibcon#enter sib2, iclass 36, count 0 2006.173.20:40:07.53#ibcon#flushed, iclass 36, count 0 2006.173.20:40:07.53#ibcon#about to write, iclass 36, count 0 2006.173.20:40:07.53#ibcon#wrote, iclass 36, count 0 2006.173.20:40:07.53#ibcon#about to read 3, iclass 36, count 0 2006.173.20:40:07.57#ibcon#read 3, iclass 36, count 0 2006.173.20:40:07.57#ibcon#about to read 4, iclass 36, count 0 2006.173.20:40:07.57#ibcon#read 4, iclass 36, count 0 2006.173.20:40:07.57#ibcon#about to read 5, iclass 36, count 0 2006.173.20:40:07.57#ibcon#read 5, iclass 36, count 0 2006.173.20:40:07.57#ibcon#about to read 6, iclass 36, count 0 2006.173.20:40:07.57#ibcon#read 6, iclass 36, count 0 2006.173.20:40:07.57#ibcon#end of sib2, iclass 36, count 0 2006.173.20:40:07.57#ibcon#*after write, iclass 36, count 0 2006.173.20:40:07.57#ibcon#*before return 0, iclass 36, count 0 2006.173.20:40:07.57#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.20:40:07.57#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.20:40:07.57#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.20:40:07.57#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.20:40:07.57$vck44/va=2,6 2006.173.20:40:07.57#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.20:40:07.57#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.20:40:07.57#ibcon#ireg 11 cls_cnt 2 2006.173.20:40:07.57#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.20:40:07.63#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.20:40:07.63#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.20:40:07.63#ibcon#enter wrdev, iclass 38, count 2 2006.173.20:40:07.63#ibcon#first serial, iclass 38, count 2 2006.173.20:40:07.63#ibcon#enter sib2, iclass 38, count 2 2006.173.20:40:07.63#ibcon#flushed, iclass 38, count 2 2006.173.20:40:07.63#ibcon#about to write, iclass 38, count 2 2006.173.20:40:07.63#ibcon#wrote, iclass 38, count 2 2006.173.20:40:07.63#ibcon#about to read 3, iclass 38, count 2 2006.173.20:40:07.65#ibcon#read 3, iclass 38, count 2 2006.173.20:40:07.65#ibcon#about to read 4, iclass 38, count 2 2006.173.20:40:07.65#ibcon#read 4, iclass 38, count 2 2006.173.20:40:07.65#ibcon#about to read 5, iclass 38, count 2 2006.173.20:40:07.65#ibcon#read 5, iclass 38, count 2 2006.173.20:40:07.65#ibcon#about to read 6, iclass 38, count 2 2006.173.20:40:07.65#ibcon#read 6, iclass 38, count 2 2006.173.20:40:07.65#ibcon#end of sib2, iclass 38, count 2 2006.173.20:40:07.65#ibcon#*mode == 0, iclass 38, count 2 2006.173.20:40:07.65#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.20:40:07.65#ibcon#[25=AT02-06\r\n] 2006.173.20:40:07.65#ibcon#*before write, iclass 38, count 2 2006.173.20:40:07.65#ibcon#enter sib2, iclass 38, count 2 2006.173.20:40:07.65#ibcon#flushed, iclass 38, count 2 2006.173.20:40:07.65#ibcon#about to write, iclass 38, count 2 2006.173.20:40:07.65#ibcon#wrote, iclass 38, count 2 2006.173.20:40:07.65#ibcon#about to read 3, iclass 38, count 2 2006.173.20:40:07.68#ibcon#read 3, iclass 38, count 2 2006.173.20:40:07.68#ibcon#about to read 4, iclass 38, count 2 2006.173.20:40:07.68#ibcon#read 4, iclass 38, count 2 2006.173.20:40:07.68#ibcon#about to read 5, iclass 38, count 2 2006.173.20:40:07.68#ibcon#read 5, iclass 38, count 2 2006.173.20:40:07.68#ibcon#about to read 6, iclass 38, count 2 2006.173.20:40:07.68#ibcon#read 6, iclass 38, count 2 2006.173.20:40:07.68#ibcon#end of sib2, iclass 38, count 2 2006.173.20:40:07.68#ibcon#*after write, iclass 38, count 2 2006.173.20:40:07.68#ibcon#*before return 0, iclass 38, count 2 2006.173.20:40:07.68#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.20:40:07.68#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.20:40:07.68#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.20:40:07.68#ibcon#ireg 7 cls_cnt 0 2006.173.20:40:07.68#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.20:40:07.80#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.20:40:07.80#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.20:40:07.80#ibcon#enter wrdev, iclass 38, count 0 2006.173.20:40:07.80#ibcon#first serial, iclass 38, count 0 2006.173.20:40:07.80#ibcon#enter sib2, iclass 38, count 0 2006.173.20:40:07.80#ibcon#flushed, iclass 38, count 0 2006.173.20:40:07.80#ibcon#about to write, iclass 38, count 0 2006.173.20:40:07.80#ibcon#wrote, iclass 38, count 0 2006.173.20:40:07.80#ibcon#about to read 3, iclass 38, count 0 2006.173.20:40:07.82#ibcon#read 3, iclass 38, count 0 2006.173.20:40:07.82#ibcon#about to read 4, iclass 38, count 0 2006.173.20:40:07.82#ibcon#read 4, iclass 38, count 0 2006.173.20:40:07.82#ibcon#about to read 5, iclass 38, count 0 2006.173.20:40:07.82#ibcon#read 5, iclass 38, count 0 2006.173.20:40:07.82#ibcon#about to read 6, iclass 38, count 0 2006.173.20:40:07.82#ibcon#read 6, iclass 38, count 0 2006.173.20:40:07.82#ibcon#end of sib2, iclass 38, count 0 2006.173.20:40:07.82#ibcon#*mode == 0, iclass 38, count 0 2006.173.20:40:07.82#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.20:40:07.82#ibcon#[25=USB\r\n] 2006.173.20:40:07.82#ibcon#*before write, iclass 38, count 0 2006.173.20:40:07.82#ibcon#enter sib2, iclass 38, count 0 2006.173.20:40:07.82#ibcon#flushed, iclass 38, count 0 2006.173.20:40:07.82#ibcon#about to write, iclass 38, count 0 2006.173.20:40:07.82#ibcon#wrote, iclass 38, count 0 2006.173.20:40:07.82#ibcon#about to read 3, iclass 38, count 0 2006.173.20:40:07.85#ibcon#read 3, iclass 38, count 0 2006.173.20:40:07.85#ibcon#about to read 4, iclass 38, count 0 2006.173.20:40:07.85#ibcon#read 4, iclass 38, count 0 2006.173.20:40:07.85#ibcon#about to read 5, iclass 38, count 0 2006.173.20:40:07.85#ibcon#read 5, iclass 38, count 0 2006.173.20:40:07.85#ibcon#about to read 6, iclass 38, count 0 2006.173.20:40:07.85#ibcon#read 6, iclass 38, count 0 2006.173.20:40:07.85#ibcon#end of sib2, iclass 38, count 0 2006.173.20:40:07.85#ibcon#*after write, iclass 38, count 0 2006.173.20:40:07.85#ibcon#*before return 0, iclass 38, count 0 2006.173.20:40:07.85#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.20:40:07.85#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.20:40:07.85#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.20:40:07.85#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.20:40:07.85$vck44/valo=3,564.99 2006.173.20:40:07.85#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.20:40:07.85#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.20:40:07.85#ibcon#ireg 17 cls_cnt 0 2006.173.20:40:07.85#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.20:40:07.85#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.20:40:07.85#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.20:40:07.85#ibcon#enter wrdev, iclass 3, count 0 2006.173.20:40:07.85#ibcon#first serial, iclass 3, count 0 2006.173.20:40:07.85#ibcon#enter sib2, iclass 3, count 0 2006.173.20:40:07.85#ibcon#flushed, iclass 3, count 0 2006.173.20:40:07.85#ibcon#about to write, iclass 3, count 0 2006.173.20:40:07.85#ibcon#wrote, iclass 3, count 0 2006.173.20:40:07.85#ibcon#about to read 3, iclass 3, count 0 2006.173.20:40:07.87#ibcon#read 3, iclass 3, count 0 2006.173.20:40:07.87#ibcon#about to read 4, iclass 3, count 0 2006.173.20:40:07.87#ibcon#read 4, iclass 3, count 0 2006.173.20:40:07.87#ibcon#about to read 5, iclass 3, count 0 2006.173.20:40:07.87#ibcon#read 5, iclass 3, count 0 2006.173.20:40:07.87#ibcon#about to read 6, iclass 3, count 0 2006.173.20:40:07.87#ibcon#read 6, iclass 3, count 0 2006.173.20:40:07.87#ibcon#end of sib2, iclass 3, count 0 2006.173.20:40:07.87#ibcon#*mode == 0, iclass 3, count 0 2006.173.20:40:07.87#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.20:40:07.87#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.20:40:07.87#ibcon#*before write, iclass 3, count 0 2006.173.20:40:07.87#ibcon#enter sib2, iclass 3, count 0 2006.173.20:40:07.87#ibcon#flushed, iclass 3, count 0 2006.173.20:40:07.87#ibcon#about to write, iclass 3, count 0 2006.173.20:40:07.87#ibcon#wrote, iclass 3, count 0 2006.173.20:40:07.87#ibcon#about to read 3, iclass 3, count 0 2006.173.20:40:07.91#ibcon#read 3, iclass 3, count 0 2006.173.20:40:07.91#ibcon#about to read 4, iclass 3, count 0 2006.173.20:40:07.91#ibcon#read 4, iclass 3, count 0 2006.173.20:40:07.91#ibcon#about to read 5, iclass 3, count 0 2006.173.20:40:07.91#ibcon#read 5, iclass 3, count 0 2006.173.20:40:07.91#ibcon#about to read 6, iclass 3, count 0 2006.173.20:40:07.91#ibcon#read 6, iclass 3, count 0 2006.173.20:40:07.91#ibcon#end of sib2, iclass 3, count 0 2006.173.20:40:07.91#ibcon#*after write, iclass 3, count 0 2006.173.20:40:07.91#ibcon#*before return 0, iclass 3, count 0 2006.173.20:40:07.91#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.20:40:07.91#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.20:40:07.91#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.20:40:07.91#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.20:40:07.91$vck44/va=3,5 2006.173.20:40:07.91#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.20:40:07.91#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.20:40:07.91#ibcon#ireg 11 cls_cnt 2 2006.173.20:40:07.91#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.20:40:07.95#abcon#<5=/06 0.8 1.4 20.361001003.0\r\n> 2006.173.20:40:07.97#abcon#{5=INTERFACE CLEAR} 2006.173.20:40:07.97#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.20:40:07.97#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.20:40:07.97#ibcon#enter wrdev, iclass 5, count 2 2006.173.20:40:07.97#ibcon#first serial, iclass 5, count 2 2006.173.20:40:07.97#ibcon#enter sib2, iclass 5, count 2 2006.173.20:40:07.97#ibcon#flushed, iclass 5, count 2 2006.173.20:40:07.97#ibcon#about to write, iclass 5, count 2 2006.173.20:40:07.97#ibcon#wrote, iclass 5, count 2 2006.173.20:40:07.97#ibcon#about to read 3, iclass 5, count 2 2006.173.20:40:07.99#ibcon#read 3, iclass 5, count 2 2006.173.20:40:07.99#ibcon#about to read 4, iclass 5, count 2 2006.173.20:40:07.99#ibcon#read 4, iclass 5, count 2 2006.173.20:40:07.99#ibcon#about to read 5, iclass 5, count 2 2006.173.20:40:07.99#ibcon#read 5, iclass 5, count 2 2006.173.20:40:07.99#ibcon#about to read 6, iclass 5, count 2 2006.173.20:40:07.99#ibcon#read 6, iclass 5, count 2 2006.173.20:40:07.99#ibcon#end of sib2, iclass 5, count 2 2006.173.20:40:07.99#ibcon#*mode == 0, iclass 5, count 2 2006.173.20:40:07.99#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.20:40:07.99#ibcon#[25=AT03-05\r\n] 2006.173.20:40:07.99#ibcon#*before write, iclass 5, count 2 2006.173.20:40:07.99#ibcon#enter sib2, iclass 5, count 2 2006.173.20:40:07.99#ibcon#flushed, iclass 5, count 2 2006.173.20:40:07.99#ibcon#about to write, iclass 5, count 2 2006.173.20:40:07.99#ibcon#wrote, iclass 5, count 2 2006.173.20:40:07.99#ibcon#about to read 3, iclass 5, count 2 2006.173.20:40:08.02#ibcon#read 3, iclass 5, count 2 2006.173.20:40:08.02#ibcon#about to read 4, iclass 5, count 2 2006.173.20:40:08.02#ibcon#read 4, iclass 5, count 2 2006.173.20:40:08.02#ibcon#about to read 5, iclass 5, count 2 2006.173.20:40:08.02#ibcon#read 5, iclass 5, count 2 2006.173.20:40:08.02#ibcon#about to read 6, iclass 5, count 2 2006.173.20:40:08.02#ibcon#read 6, iclass 5, count 2 2006.173.20:40:08.02#ibcon#end of sib2, iclass 5, count 2 2006.173.20:40:08.02#ibcon#*after write, iclass 5, count 2 2006.173.20:40:08.02#ibcon#*before return 0, iclass 5, count 2 2006.173.20:40:08.02#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.20:40:08.02#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.20:40:08.02#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.20:40:08.02#ibcon#ireg 7 cls_cnt 0 2006.173.20:40:08.02#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.20:40:08.03#abcon#[5=S1D000X0/0*\r\n] 2006.173.20:40:08.14#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.20:40:08.14#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.20:40:08.14#ibcon#enter wrdev, iclass 5, count 0 2006.173.20:40:08.14#ibcon#first serial, iclass 5, count 0 2006.173.20:40:08.14#ibcon#enter sib2, iclass 5, count 0 2006.173.20:40:08.14#ibcon#flushed, iclass 5, count 0 2006.173.20:40:08.14#ibcon#about to write, iclass 5, count 0 2006.173.20:40:08.14#ibcon#wrote, iclass 5, count 0 2006.173.20:40:08.14#ibcon#about to read 3, iclass 5, count 0 2006.173.20:40:08.16#ibcon#read 3, iclass 5, count 0 2006.173.20:40:08.16#ibcon#about to read 4, iclass 5, count 0 2006.173.20:40:08.16#ibcon#read 4, iclass 5, count 0 2006.173.20:40:08.16#ibcon#about to read 5, iclass 5, count 0 2006.173.20:40:08.16#ibcon#read 5, iclass 5, count 0 2006.173.20:40:08.16#ibcon#about to read 6, iclass 5, count 0 2006.173.20:40:08.16#ibcon#read 6, iclass 5, count 0 2006.173.20:40:08.16#ibcon#end of sib2, iclass 5, count 0 2006.173.20:40:08.16#ibcon#*mode == 0, iclass 5, count 0 2006.173.20:40:08.16#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.20:40:08.16#ibcon#[25=USB\r\n] 2006.173.20:40:08.16#ibcon#*before write, iclass 5, count 0 2006.173.20:40:08.16#ibcon#enter sib2, iclass 5, count 0 2006.173.20:40:08.16#ibcon#flushed, iclass 5, count 0 2006.173.20:40:08.16#ibcon#about to write, iclass 5, count 0 2006.173.20:40:08.16#ibcon#wrote, iclass 5, count 0 2006.173.20:40:08.16#ibcon#about to read 3, iclass 5, count 0 2006.173.20:40:08.19#ibcon#read 3, iclass 5, count 0 2006.173.20:40:08.19#ibcon#about to read 4, iclass 5, count 0 2006.173.20:40:08.19#ibcon#read 4, iclass 5, count 0 2006.173.20:40:08.19#ibcon#about to read 5, iclass 5, count 0 2006.173.20:40:08.19#ibcon#read 5, iclass 5, count 0 2006.173.20:40:08.19#ibcon#about to read 6, iclass 5, count 0 2006.173.20:40:08.19#ibcon#read 6, iclass 5, count 0 2006.173.20:40:08.19#ibcon#end of sib2, iclass 5, count 0 2006.173.20:40:08.19#ibcon#*after write, iclass 5, count 0 2006.173.20:40:08.19#ibcon#*before return 0, iclass 5, count 0 2006.173.20:40:08.19#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.20:40:08.19#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.20:40:08.19#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.20:40:08.19#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.20:40:08.19$vck44/valo=4,624.99 2006.173.20:40:08.19#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.20:40:08.19#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.20:40:08.19#ibcon#ireg 17 cls_cnt 0 2006.173.20:40:08.19#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.20:40:08.19#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.20:40:08.19#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.20:40:08.19#ibcon#enter wrdev, iclass 12, count 0 2006.173.20:40:08.19#ibcon#first serial, iclass 12, count 0 2006.173.20:40:08.19#ibcon#enter sib2, iclass 12, count 0 2006.173.20:40:08.19#ibcon#flushed, iclass 12, count 0 2006.173.20:40:08.19#ibcon#about to write, iclass 12, count 0 2006.173.20:40:08.19#ibcon#wrote, iclass 12, count 0 2006.173.20:40:08.19#ibcon#about to read 3, iclass 12, count 0 2006.173.20:40:08.21#ibcon#read 3, iclass 12, count 0 2006.173.20:40:08.21#ibcon#about to read 4, iclass 12, count 0 2006.173.20:40:08.21#ibcon#read 4, iclass 12, count 0 2006.173.20:40:08.21#ibcon#about to read 5, iclass 12, count 0 2006.173.20:40:08.21#ibcon#read 5, iclass 12, count 0 2006.173.20:40:08.21#ibcon#about to read 6, iclass 12, count 0 2006.173.20:40:08.21#ibcon#read 6, iclass 12, count 0 2006.173.20:40:08.21#ibcon#end of sib2, iclass 12, count 0 2006.173.20:40:08.21#ibcon#*mode == 0, iclass 12, count 0 2006.173.20:40:08.21#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.20:40:08.21#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.20:40:08.21#ibcon#*before write, iclass 12, count 0 2006.173.20:40:08.21#ibcon#enter sib2, iclass 12, count 0 2006.173.20:40:08.21#ibcon#flushed, iclass 12, count 0 2006.173.20:40:08.21#ibcon#about to write, iclass 12, count 0 2006.173.20:40:08.21#ibcon#wrote, iclass 12, count 0 2006.173.20:40:08.21#ibcon#about to read 3, iclass 12, count 0 2006.173.20:40:08.25#ibcon#read 3, iclass 12, count 0 2006.173.20:40:08.25#ibcon#about to read 4, iclass 12, count 0 2006.173.20:40:08.25#ibcon#read 4, iclass 12, count 0 2006.173.20:40:08.25#ibcon#about to read 5, iclass 12, count 0 2006.173.20:40:08.25#ibcon#read 5, iclass 12, count 0 2006.173.20:40:08.25#ibcon#about to read 6, iclass 12, count 0 2006.173.20:40:08.25#ibcon#read 6, iclass 12, count 0 2006.173.20:40:08.25#ibcon#end of sib2, iclass 12, count 0 2006.173.20:40:08.25#ibcon#*after write, iclass 12, count 0 2006.173.20:40:08.25#ibcon#*before return 0, iclass 12, count 0 2006.173.20:40:08.25#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.20:40:08.25#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.20:40:08.25#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.20:40:08.25#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.20:40:08.25$vck44/va=4,6 2006.173.20:40:08.25#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.20:40:08.25#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.20:40:08.25#ibcon#ireg 11 cls_cnt 2 2006.173.20:40:08.25#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.20:40:08.31#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.20:40:08.31#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.20:40:08.31#ibcon#enter wrdev, iclass 14, count 2 2006.173.20:40:08.31#ibcon#first serial, iclass 14, count 2 2006.173.20:40:08.31#ibcon#enter sib2, iclass 14, count 2 2006.173.20:40:08.31#ibcon#flushed, iclass 14, count 2 2006.173.20:40:08.31#ibcon#about to write, iclass 14, count 2 2006.173.20:40:08.31#ibcon#wrote, iclass 14, count 2 2006.173.20:40:08.31#ibcon#about to read 3, iclass 14, count 2 2006.173.20:40:08.33#ibcon#read 3, iclass 14, count 2 2006.173.20:40:08.33#ibcon#about to read 4, iclass 14, count 2 2006.173.20:40:08.33#ibcon#read 4, iclass 14, count 2 2006.173.20:40:08.33#ibcon#about to read 5, iclass 14, count 2 2006.173.20:40:08.33#ibcon#read 5, iclass 14, count 2 2006.173.20:40:08.33#ibcon#about to read 6, iclass 14, count 2 2006.173.20:40:08.33#ibcon#read 6, iclass 14, count 2 2006.173.20:40:08.33#ibcon#end of sib2, iclass 14, count 2 2006.173.20:40:08.33#ibcon#*mode == 0, iclass 14, count 2 2006.173.20:40:08.33#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.20:40:08.33#ibcon#[25=AT04-06\r\n] 2006.173.20:40:08.33#ibcon#*before write, iclass 14, count 2 2006.173.20:40:08.33#ibcon#enter sib2, iclass 14, count 2 2006.173.20:40:08.33#ibcon#flushed, iclass 14, count 2 2006.173.20:40:08.33#ibcon#about to write, iclass 14, count 2 2006.173.20:40:08.33#ibcon#wrote, iclass 14, count 2 2006.173.20:40:08.33#ibcon#about to read 3, iclass 14, count 2 2006.173.20:40:08.36#ibcon#read 3, iclass 14, count 2 2006.173.20:40:08.36#ibcon#about to read 4, iclass 14, count 2 2006.173.20:40:08.36#ibcon#read 4, iclass 14, count 2 2006.173.20:40:08.36#ibcon#about to read 5, iclass 14, count 2 2006.173.20:40:08.36#ibcon#read 5, iclass 14, count 2 2006.173.20:40:08.36#ibcon#about to read 6, iclass 14, count 2 2006.173.20:40:08.36#ibcon#read 6, iclass 14, count 2 2006.173.20:40:08.36#ibcon#end of sib2, iclass 14, count 2 2006.173.20:40:08.36#ibcon#*after write, iclass 14, count 2 2006.173.20:40:08.36#ibcon#*before return 0, iclass 14, count 2 2006.173.20:40:08.36#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.20:40:08.36#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.20:40:08.36#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.20:40:08.36#ibcon#ireg 7 cls_cnt 0 2006.173.20:40:08.36#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.20:40:08.48#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.20:40:08.48#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.20:40:08.48#ibcon#enter wrdev, iclass 14, count 0 2006.173.20:40:08.48#ibcon#first serial, iclass 14, count 0 2006.173.20:40:08.48#ibcon#enter sib2, iclass 14, count 0 2006.173.20:40:08.48#ibcon#flushed, iclass 14, count 0 2006.173.20:40:08.48#ibcon#about to write, iclass 14, count 0 2006.173.20:40:08.48#ibcon#wrote, iclass 14, count 0 2006.173.20:40:08.48#ibcon#about to read 3, iclass 14, count 0 2006.173.20:40:08.50#ibcon#read 3, iclass 14, count 0 2006.173.20:40:08.50#ibcon#about to read 4, iclass 14, count 0 2006.173.20:40:08.50#ibcon#read 4, iclass 14, count 0 2006.173.20:40:08.50#ibcon#about to read 5, iclass 14, count 0 2006.173.20:40:08.50#ibcon#read 5, iclass 14, count 0 2006.173.20:40:08.50#ibcon#about to read 6, iclass 14, count 0 2006.173.20:40:08.50#ibcon#read 6, iclass 14, count 0 2006.173.20:40:08.50#ibcon#end of sib2, iclass 14, count 0 2006.173.20:40:08.50#ibcon#*mode == 0, iclass 14, count 0 2006.173.20:40:08.50#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.20:40:08.50#ibcon#[25=USB\r\n] 2006.173.20:40:08.50#ibcon#*before write, iclass 14, count 0 2006.173.20:40:08.50#ibcon#enter sib2, iclass 14, count 0 2006.173.20:40:08.50#ibcon#flushed, iclass 14, count 0 2006.173.20:40:08.50#ibcon#about to write, iclass 14, count 0 2006.173.20:40:08.50#ibcon#wrote, iclass 14, count 0 2006.173.20:40:08.50#ibcon#about to read 3, iclass 14, count 0 2006.173.20:40:08.53#ibcon#read 3, iclass 14, count 0 2006.173.20:40:08.53#ibcon#about to read 4, iclass 14, count 0 2006.173.20:40:08.53#ibcon#read 4, iclass 14, count 0 2006.173.20:40:08.53#ibcon#about to read 5, iclass 14, count 0 2006.173.20:40:08.53#ibcon#read 5, iclass 14, count 0 2006.173.20:40:08.53#ibcon#about to read 6, iclass 14, count 0 2006.173.20:40:08.53#ibcon#read 6, iclass 14, count 0 2006.173.20:40:08.53#ibcon#end of sib2, iclass 14, count 0 2006.173.20:40:08.53#ibcon#*after write, iclass 14, count 0 2006.173.20:40:08.53#ibcon#*before return 0, iclass 14, count 0 2006.173.20:40:08.53#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.20:40:08.53#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.20:40:08.53#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.20:40:08.53#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.20:40:08.53$vck44/valo=5,734.99 2006.173.20:40:08.53#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.20:40:08.53#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.20:40:08.53#ibcon#ireg 17 cls_cnt 0 2006.173.20:40:08.53#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.20:40:08.53#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.20:40:08.53#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.20:40:08.53#ibcon#enter wrdev, iclass 16, count 0 2006.173.20:40:08.53#ibcon#first serial, iclass 16, count 0 2006.173.20:40:08.53#ibcon#enter sib2, iclass 16, count 0 2006.173.20:40:08.53#ibcon#flushed, iclass 16, count 0 2006.173.20:40:08.53#ibcon#about to write, iclass 16, count 0 2006.173.20:40:08.53#ibcon#wrote, iclass 16, count 0 2006.173.20:40:08.53#ibcon#about to read 3, iclass 16, count 0 2006.173.20:40:08.55#ibcon#read 3, iclass 16, count 0 2006.173.20:40:08.55#ibcon#about to read 4, iclass 16, count 0 2006.173.20:40:08.55#ibcon#read 4, iclass 16, count 0 2006.173.20:40:08.55#ibcon#about to read 5, iclass 16, count 0 2006.173.20:40:08.55#ibcon#read 5, iclass 16, count 0 2006.173.20:40:08.55#ibcon#about to read 6, iclass 16, count 0 2006.173.20:40:08.55#ibcon#read 6, iclass 16, count 0 2006.173.20:40:08.55#ibcon#end of sib2, iclass 16, count 0 2006.173.20:40:08.55#ibcon#*mode == 0, iclass 16, count 0 2006.173.20:40:08.55#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.20:40:08.55#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.20:40:08.55#ibcon#*before write, iclass 16, count 0 2006.173.20:40:08.55#ibcon#enter sib2, iclass 16, count 0 2006.173.20:40:08.55#ibcon#flushed, iclass 16, count 0 2006.173.20:40:08.55#ibcon#about to write, iclass 16, count 0 2006.173.20:40:08.55#ibcon#wrote, iclass 16, count 0 2006.173.20:40:08.55#ibcon#about to read 3, iclass 16, count 0 2006.173.20:40:08.59#ibcon#read 3, iclass 16, count 0 2006.173.20:40:08.59#ibcon#about to read 4, iclass 16, count 0 2006.173.20:40:08.59#ibcon#read 4, iclass 16, count 0 2006.173.20:40:08.59#ibcon#about to read 5, iclass 16, count 0 2006.173.20:40:08.59#ibcon#read 5, iclass 16, count 0 2006.173.20:40:08.59#ibcon#about to read 6, iclass 16, count 0 2006.173.20:40:08.59#ibcon#read 6, iclass 16, count 0 2006.173.20:40:08.59#ibcon#end of sib2, iclass 16, count 0 2006.173.20:40:08.59#ibcon#*after write, iclass 16, count 0 2006.173.20:40:08.59#ibcon#*before return 0, iclass 16, count 0 2006.173.20:40:08.59#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.20:40:08.59#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.20:40:08.59#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.20:40:08.59#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.20:40:08.59$vck44/va=5,4 2006.173.20:40:08.59#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.20:40:08.59#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.20:40:08.59#ibcon#ireg 11 cls_cnt 2 2006.173.20:40:08.59#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.20:40:08.65#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.20:40:08.65#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.20:40:08.65#ibcon#enter wrdev, iclass 18, count 2 2006.173.20:40:08.65#ibcon#first serial, iclass 18, count 2 2006.173.20:40:08.65#ibcon#enter sib2, iclass 18, count 2 2006.173.20:40:08.65#ibcon#flushed, iclass 18, count 2 2006.173.20:40:08.65#ibcon#about to write, iclass 18, count 2 2006.173.20:40:08.65#ibcon#wrote, iclass 18, count 2 2006.173.20:40:08.65#ibcon#about to read 3, iclass 18, count 2 2006.173.20:40:08.67#ibcon#read 3, iclass 18, count 2 2006.173.20:40:08.67#ibcon#about to read 4, iclass 18, count 2 2006.173.20:40:08.67#ibcon#read 4, iclass 18, count 2 2006.173.20:40:08.67#ibcon#about to read 5, iclass 18, count 2 2006.173.20:40:08.67#ibcon#read 5, iclass 18, count 2 2006.173.20:40:08.67#ibcon#about to read 6, iclass 18, count 2 2006.173.20:40:08.67#ibcon#read 6, iclass 18, count 2 2006.173.20:40:08.67#ibcon#end of sib2, iclass 18, count 2 2006.173.20:40:08.67#ibcon#*mode == 0, iclass 18, count 2 2006.173.20:40:08.67#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.20:40:08.67#ibcon#[25=AT05-04\r\n] 2006.173.20:40:08.67#ibcon#*before write, iclass 18, count 2 2006.173.20:40:08.67#ibcon#enter sib2, iclass 18, count 2 2006.173.20:40:08.67#ibcon#flushed, iclass 18, count 2 2006.173.20:40:08.67#ibcon#about to write, iclass 18, count 2 2006.173.20:40:08.67#ibcon#wrote, iclass 18, count 2 2006.173.20:40:08.67#ibcon#about to read 3, iclass 18, count 2 2006.173.20:40:08.70#ibcon#read 3, iclass 18, count 2 2006.173.20:40:08.70#ibcon#about to read 4, iclass 18, count 2 2006.173.20:40:08.70#ibcon#read 4, iclass 18, count 2 2006.173.20:40:08.70#ibcon#about to read 5, iclass 18, count 2 2006.173.20:40:08.70#ibcon#read 5, iclass 18, count 2 2006.173.20:40:08.70#ibcon#about to read 6, iclass 18, count 2 2006.173.20:40:08.70#ibcon#read 6, iclass 18, count 2 2006.173.20:40:08.70#ibcon#end of sib2, iclass 18, count 2 2006.173.20:40:08.70#ibcon#*after write, iclass 18, count 2 2006.173.20:40:08.70#ibcon#*before return 0, iclass 18, count 2 2006.173.20:40:08.70#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.20:40:08.70#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.20:40:08.70#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.20:40:08.70#ibcon#ireg 7 cls_cnt 0 2006.173.20:40:08.70#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.20:40:08.82#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.20:40:08.82#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.20:40:08.82#ibcon#enter wrdev, iclass 18, count 0 2006.173.20:40:08.82#ibcon#first serial, iclass 18, count 0 2006.173.20:40:08.82#ibcon#enter sib2, iclass 18, count 0 2006.173.20:40:08.82#ibcon#flushed, iclass 18, count 0 2006.173.20:40:08.82#ibcon#about to write, iclass 18, count 0 2006.173.20:40:08.82#ibcon#wrote, iclass 18, count 0 2006.173.20:40:08.82#ibcon#about to read 3, iclass 18, count 0 2006.173.20:40:08.84#ibcon#read 3, iclass 18, count 0 2006.173.20:40:08.84#ibcon#about to read 4, iclass 18, count 0 2006.173.20:40:08.84#ibcon#read 4, iclass 18, count 0 2006.173.20:40:08.84#ibcon#about to read 5, iclass 18, count 0 2006.173.20:40:08.84#ibcon#read 5, iclass 18, count 0 2006.173.20:40:08.84#ibcon#about to read 6, iclass 18, count 0 2006.173.20:40:08.84#ibcon#read 6, iclass 18, count 0 2006.173.20:40:08.84#ibcon#end of sib2, iclass 18, count 0 2006.173.20:40:08.84#ibcon#*mode == 0, iclass 18, count 0 2006.173.20:40:08.84#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.20:40:08.84#ibcon#[25=USB\r\n] 2006.173.20:40:08.84#ibcon#*before write, iclass 18, count 0 2006.173.20:40:08.84#ibcon#enter sib2, iclass 18, count 0 2006.173.20:40:08.84#ibcon#flushed, iclass 18, count 0 2006.173.20:40:08.84#ibcon#about to write, iclass 18, count 0 2006.173.20:40:08.84#ibcon#wrote, iclass 18, count 0 2006.173.20:40:08.84#ibcon#about to read 3, iclass 18, count 0 2006.173.20:40:08.87#ibcon#read 3, iclass 18, count 0 2006.173.20:40:08.87#ibcon#about to read 4, iclass 18, count 0 2006.173.20:40:08.87#ibcon#read 4, iclass 18, count 0 2006.173.20:40:08.87#ibcon#about to read 5, iclass 18, count 0 2006.173.20:40:08.87#ibcon#read 5, iclass 18, count 0 2006.173.20:40:08.87#ibcon#about to read 6, iclass 18, count 0 2006.173.20:40:08.87#ibcon#read 6, iclass 18, count 0 2006.173.20:40:08.87#ibcon#end of sib2, iclass 18, count 0 2006.173.20:40:08.87#ibcon#*after write, iclass 18, count 0 2006.173.20:40:08.87#ibcon#*before return 0, iclass 18, count 0 2006.173.20:40:08.87#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.20:40:08.87#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.20:40:08.87#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.20:40:08.87#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.20:40:08.87$vck44/valo=6,814.99 2006.173.20:40:08.87#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.20:40:08.87#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.20:40:08.87#ibcon#ireg 17 cls_cnt 0 2006.173.20:40:08.87#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.20:40:08.87#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.20:40:08.87#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.20:40:08.87#ibcon#enter wrdev, iclass 20, count 0 2006.173.20:40:08.87#ibcon#first serial, iclass 20, count 0 2006.173.20:40:08.87#ibcon#enter sib2, iclass 20, count 0 2006.173.20:40:08.87#ibcon#flushed, iclass 20, count 0 2006.173.20:40:08.87#ibcon#about to write, iclass 20, count 0 2006.173.20:40:08.87#ibcon#wrote, iclass 20, count 0 2006.173.20:40:08.87#ibcon#about to read 3, iclass 20, count 0 2006.173.20:40:08.89#ibcon#read 3, iclass 20, count 0 2006.173.20:40:08.89#ibcon#about to read 4, iclass 20, count 0 2006.173.20:40:08.89#ibcon#read 4, iclass 20, count 0 2006.173.20:40:08.89#ibcon#about to read 5, iclass 20, count 0 2006.173.20:40:08.89#ibcon#read 5, iclass 20, count 0 2006.173.20:40:08.89#ibcon#about to read 6, iclass 20, count 0 2006.173.20:40:08.89#ibcon#read 6, iclass 20, count 0 2006.173.20:40:08.89#ibcon#end of sib2, iclass 20, count 0 2006.173.20:40:08.89#ibcon#*mode == 0, iclass 20, count 0 2006.173.20:40:08.89#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.20:40:08.89#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.20:40:08.89#ibcon#*before write, iclass 20, count 0 2006.173.20:40:08.89#ibcon#enter sib2, iclass 20, count 0 2006.173.20:40:08.89#ibcon#flushed, iclass 20, count 0 2006.173.20:40:08.89#ibcon#about to write, iclass 20, count 0 2006.173.20:40:08.89#ibcon#wrote, iclass 20, count 0 2006.173.20:40:08.89#ibcon#about to read 3, iclass 20, count 0 2006.173.20:40:08.93#ibcon#read 3, iclass 20, count 0 2006.173.20:40:08.93#ibcon#about to read 4, iclass 20, count 0 2006.173.20:40:08.93#ibcon#read 4, iclass 20, count 0 2006.173.20:40:08.93#ibcon#about to read 5, iclass 20, count 0 2006.173.20:40:08.93#ibcon#read 5, iclass 20, count 0 2006.173.20:40:08.93#ibcon#about to read 6, iclass 20, count 0 2006.173.20:40:08.93#ibcon#read 6, iclass 20, count 0 2006.173.20:40:08.93#ibcon#end of sib2, iclass 20, count 0 2006.173.20:40:08.93#ibcon#*after write, iclass 20, count 0 2006.173.20:40:08.93#ibcon#*before return 0, iclass 20, count 0 2006.173.20:40:08.93#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.20:40:08.93#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.20:40:08.93#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.20:40:08.93#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.20:40:08.93$vck44/va=6,3 2006.173.20:40:08.93#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.20:40:08.93#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.20:40:08.93#ibcon#ireg 11 cls_cnt 2 2006.173.20:40:08.93#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.20:40:08.99#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.20:40:08.99#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.20:40:08.99#ibcon#enter wrdev, iclass 22, count 2 2006.173.20:40:08.99#ibcon#first serial, iclass 22, count 2 2006.173.20:40:08.99#ibcon#enter sib2, iclass 22, count 2 2006.173.20:40:08.99#ibcon#flushed, iclass 22, count 2 2006.173.20:40:08.99#ibcon#about to write, iclass 22, count 2 2006.173.20:40:08.99#ibcon#wrote, iclass 22, count 2 2006.173.20:40:08.99#ibcon#about to read 3, iclass 22, count 2 2006.173.20:40:09.01#ibcon#read 3, iclass 22, count 2 2006.173.20:40:09.01#ibcon#about to read 4, iclass 22, count 2 2006.173.20:40:09.01#ibcon#read 4, iclass 22, count 2 2006.173.20:40:09.01#ibcon#about to read 5, iclass 22, count 2 2006.173.20:40:09.01#ibcon#read 5, iclass 22, count 2 2006.173.20:40:09.01#ibcon#about to read 6, iclass 22, count 2 2006.173.20:40:09.01#ibcon#read 6, iclass 22, count 2 2006.173.20:40:09.01#ibcon#end of sib2, iclass 22, count 2 2006.173.20:40:09.01#ibcon#*mode == 0, iclass 22, count 2 2006.173.20:40:09.01#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.20:40:09.01#ibcon#[25=AT06-03\r\n] 2006.173.20:40:09.01#ibcon#*before write, iclass 22, count 2 2006.173.20:40:09.01#ibcon#enter sib2, iclass 22, count 2 2006.173.20:40:09.01#ibcon#flushed, iclass 22, count 2 2006.173.20:40:09.01#ibcon#about to write, iclass 22, count 2 2006.173.20:40:09.01#ibcon#wrote, iclass 22, count 2 2006.173.20:40:09.01#ibcon#about to read 3, iclass 22, count 2 2006.173.20:40:09.04#ibcon#read 3, iclass 22, count 2 2006.173.20:40:09.04#ibcon#about to read 4, iclass 22, count 2 2006.173.20:40:09.04#ibcon#read 4, iclass 22, count 2 2006.173.20:40:09.04#ibcon#about to read 5, iclass 22, count 2 2006.173.20:40:09.04#ibcon#read 5, iclass 22, count 2 2006.173.20:40:09.04#ibcon#about to read 6, iclass 22, count 2 2006.173.20:40:09.04#ibcon#read 6, iclass 22, count 2 2006.173.20:40:09.04#ibcon#end of sib2, iclass 22, count 2 2006.173.20:40:09.04#ibcon#*after write, iclass 22, count 2 2006.173.20:40:09.04#ibcon#*before return 0, iclass 22, count 2 2006.173.20:40:09.04#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.20:40:09.04#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.20:40:09.04#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.20:40:09.04#ibcon#ireg 7 cls_cnt 0 2006.173.20:40:09.04#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.20:40:09.16#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.20:40:09.16#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.20:40:09.16#ibcon#enter wrdev, iclass 22, count 0 2006.173.20:40:09.16#ibcon#first serial, iclass 22, count 0 2006.173.20:40:09.16#ibcon#enter sib2, iclass 22, count 0 2006.173.20:40:09.16#ibcon#flushed, iclass 22, count 0 2006.173.20:40:09.16#ibcon#about to write, iclass 22, count 0 2006.173.20:40:09.16#ibcon#wrote, iclass 22, count 0 2006.173.20:40:09.16#ibcon#about to read 3, iclass 22, count 0 2006.173.20:40:09.18#ibcon#read 3, iclass 22, count 0 2006.173.20:40:09.18#ibcon#about to read 4, iclass 22, count 0 2006.173.20:40:09.18#ibcon#read 4, iclass 22, count 0 2006.173.20:40:09.18#ibcon#about to read 5, iclass 22, count 0 2006.173.20:40:09.18#ibcon#read 5, iclass 22, count 0 2006.173.20:40:09.18#ibcon#about to read 6, iclass 22, count 0 2006.173.20:40:09.18#ibcon#read 6, iclass 22, count 0 2006.173.20:40:09.18#ibcon#end of sib2, iclass 22, count 0 2006.173.20:40:09.18#ibcon#*mode == 0, iclass 22, count 0 2006.173.20:40:09.18#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.20:40:09.18#ibcon#[25=USB\r\n] 2006.173.20:40:09.18#ibcon#*before write, iclass 22, count 0 2006.173.20:40:09.18#ibcon#enter sib2, iclass 22, count 0 2006.173.20:40:09.18#ibcon#flushed, iclass 22, count 0 2006.173.20:40:09.18#ibcon#about to write, iclass 22, count 0 2006.173.20:40:09.18#ibcon#wrote, iclass 22, count 0 2006.173.20:40:09.18#ibcon#about to read 3, iclass 22, count 0 2006.173.20:40:09.21#ibcon#read 3, iclass 22, count 0 2006.173.20:40:09.21#ibcon#about to read 4, iclass 22, count 0 2006.173.20:40:09.21#ibcon#read 4, iclass 22, count 0 2006.173.20:40:09.21#ibcon#about to read 5, iclass 22, count 0 2006.173.20:40:09.21#ibcon#read 5, iclass 22, count 0 2006.173.20:40:09.21#ibcon#about to read 6, iclass 22, count 0 2006.173.20:40:09.21#ibcon#read 6, iclass 22, count 0 2006.173.20:40:09.21#ibcon#end of sib2, iclass 22, count 0 2006.173.20:40:09.21#ibcon#*after write, iclass 22, count 0 2006.173.20:40:09.21#ibcon#*before return 0, iclass 22, count 0 2006.173.20:40:09.21#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.20:40:09.21#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.20:40:09.21#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.20:40:09.21#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.20:40:09.21$vck44/valo=7,864.99 2006.173.20:40:09.21#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.20:40:09.21#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.20:40:09.21#ibcon#ireg 17 cls_cnt 0 2006.173.20:40:09.21#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.20:40:09.21#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.20:40:09.21#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.20:40:09.21#ibcon#enter wrdev, iclass 24, count 0 2006.173.20:40:09.21#ibcon#first serial, iclass 24, count 0 2006.173.20:40:09.21#ibcon#enter sib2, iclass 24, count 0 2006.173.20:40:09.21#ibcon#flushed, iclass 24, count 0 2006.173.20:40:09.21#ibcon#about to write, iclass 24, count 0 2006.173.20:40:09.21#ibcon#wrote, iclass 24, count 0 2006.173.20:40:09.21#ibcon#about to read 3, iclass 24, count 0 2006.173.20:40:09.23#ibcon#read 3, iclass 24, count 0 2006.173.20:40:09.23#ibcon#about to read 4, iclass 24, count 0 2006.173.20:40:09.23#ibcon#read 4, iclass 24, count 0 2006.173.20:40:09.23#ibcon#about to read 5, iclass 24, count 0 2006.173.20:40:09.23#ibcon#read 5, iclass 24, count 0 2006.173.20:40:09.23#ibcon#about to read 6, iclass 24, count 0 2006.173.20:40:09.23#ibcon#read 6, iclass 24, count 0 2006.173.20:40:09.23#ibcon#end of sib2, iclass 24, count 0 2006.173.20:40:09.23#ibcon#*mode == 0, iclass 24, count 0 2006.173.20:40:09.23#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.20:40:09.23#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.20:40:09.23#ibcon#*before write, iclass 24, count 0 2006.173.20:40:09.23#ibcon#enter sib2, iclass 24, count 0 2006.173.20:40:09.23#ibcon#flushed, iclass 24, count 0 2006.173.20:40:09.23#ibcon#about to write, iclass 24, count 0 2006.173.20:40:09.23#ibcon#wrote, iclass 24, count 0 2006.173.20:40:09.23#ibcon#about to read 3, iclass 24, count 0 2006.173.20:40:09.27#ibcon#read 3, iclass 24, count 0 2006.173.20:40:09.27#ibcon#about to read 4, iclass 24, count 0 2006.173.20:40:09.27#ibcon#read 4, iclass 24, count 0 2006.173.20:40:09.27#ibcon#about to read 5, iclass 24, count 0 2006.173.20:40:09.27#ibcon#read 5, iclass 24, count 0 2006.173.20:40:09.27#ibcon#about to read 6, iclass 24, count 0 2006.173.20:40:09.27#ibcon#read 6, iclass 24, count 0 2006.173.20:40:09.27#ibcon#end of sib2, iclass 24, count 0 2006.173.20:40:09.27#ibcon#*after write, iclass 24, count 0 2006.173.20:40:09.27#ibcon#*before return 0, iclass 24, count 0 2006.173.20:40:09.27#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.20:40:09.27#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.20:40:09.27#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.20:40:09.27#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.20:40:09.27$vck44/va=7,4 2006.173.20:40:09.27#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.20:40:09.27#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.20:40:09.27#ibcon#ireg 11 cls_cnt 2 2006.173.20:40:09.27#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.20:40:09.33#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.20:40:09.33#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.20:40:09.33#ibcon#enter wrdev, iclass 26, count 2 2006.173.20:40:09.33#ibcon#first serial, iclass 26, count 2 2006.173.20:40:09.33#ibcon#enter sib2, iclass 26, count 2 2006.173.20:40:09.33#ibcon#flushed, iclass 26, count 2 2006.173.20:40:09.33#ibcon#about to write, iclass 26, count 2 2006.173.20:40:09.33#ibcon#wrote, iclass 26, count 2 2006.173.20:40:09.33#ibcon#about to read 3, iclass 26, count 2 2006.173.20:40:09.35#ibcon#read 3, iclass 26, count 2 2006.173.20:40:09.35#ibcon#about to read 4, iclass 26, count 2 2006.173.20:40:09.35#ibcon#read 4, iclass 26, count 2 2006.173.20:40:09.35#ibcon#about to read 5, iclass 26, count 2 2006.173.20:40:09.35#ibcon#read 5, iclass 26, count 2 2006.173.20:40:09.35#ibcon#about to read 6, iclass 26, count 2 2006.173.20:40:09.35#ibcon#read 6, iclass 26, count 2 2006.173.20:40:09.35#ibcon#end of sib2, iclass 26, count 2 2006.173.20:40:09.35#ibcon#*mode == 0, iclass 26, count 2 2006.173.20:40:09.35#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.20:40:09.35#ibcon#[25=AT07-04\r\n] 2006.173.20:40:09.35#ibcon#*before write, iclass 26, count 2 2006.173.20:40:09.35#ibcon#enter sib2, iclass 26, count 2 2006.173.20:40:09.35#ibcon#flushed, iclass 26, count 2 2006.173.20:40:09.35#ibcon#about to write, iclass 26, count 2 2006.173.20:40:09.35#ibcon#wrote, iclass 26, count 2 2006.173.20:40:09.35#ibcon#about to read 3, iclass 26, count 2 2006.173.20:40:09.38#ibcon#read 3, iclass 26, count 2 2006.173.20:40:09.38#ibcon#about to read 4, iclass 26, count 2 2006.173.20:40:09.38#ibcon#read 4, iclass 26, count 2 2006.173.20:40:09.38#ibcon#about to read 5, iclass 26, count 2 2006.173.20:40:09.38#ibcon#read 5, iclass 26, count 2 2006.173.20:40:09.38#ibcon#about to read 6, iclass 26, count 2 2006.173.20:40:09.38#ibcon#read 6, iclass 26, count 2 2006.173.20:40:09.38#ibcon#end of sib2, iclass 26, count 2 2006.173.20:40:09.38#ibcon#*after write, iclass 26, count 2 2006.173.20:40:09.38#ibcon#*before return 0, iclass 26, count 2 2006.173.20:40:09.38#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.20:40:09.38#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.20:40:09.38#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.20:40:09.38#ibcon#ireg 7 cls_cnt 0 2006.173.20:40:09.38#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.20:40:09.50#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.20:40:09.50#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.20:40:09.50#ibcon#enter wrdev, iclass 26, count 0 2006.173.20:40:09.50#ibcon#first serial, iclass 26, count 0 2006.173.20:40:09.50#ibcon#enter sib2, iclass 26, count 0 2006.173.20:40:09.50#ibcon#flushed, iclass 26, count 0 2006.173.20:40:09.50#ibcon#about to write, iclass 26, count 0 2006.173.20:40:09.50#ibcon#wrote, iclass 26, count 0 2006.173.20:40:09.50#ibcon#about to read 3, iclass 26, count 0 2006.173.20:40:09.52#ibcon#read 3, iclass 26, count 0 2006.173.20:40:09.52#ibcon#about to read 4, iclass 26, count 0 2006.173.20:40:09.52#ibcon#read 4, iclass 26, count 0 2006.173.20:40:09.52#ibcon#about to read 5, iclass 26, count 0 2006.173.20:40:09.52#ibcon#read 5, iclass 26, count 0 2006.173.20:40:09.52#ibcon#about to read 6, iclass 26, count 0 2006.173.20:40:09.52#ibcon#read 6, iclass 26, count 0 2006.173.20:40:09.52#ibcon#end of sib2, iclass 26, count 0 2006.173.20:40:09.52#ibcon#*mode == 0, iclass 26, count 0 2006.173.20:40:09.52#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.20:40:09.52#ibcon#[25=USB\r\n] 2006.173.20:40:09.52#ibcon#*before write, iclass 26, count 0 2006.173.20:40:09.52#ibcon#enter sib2, iclass 26, count 0 2006.173.20:40:09.52#ibcon#flushed, iclass 26, count 0 2006.173.20:40:09.52#ibcon#about to write, iclass 26, count 0 2006.173.20:40:09.52#ibcon#wrote, iclass 26, count 0 2006.173.20:40:09.52#ibcon#about to read 3, iclass 26, count 0 2006.173.20:40:09.55#ibcon#read 3, iclass 26, count 0 2006.173.20:40:09.55#ibcon#about to read 4, iclass 26, count 0 2006.173.20:40:09.55#ibcon#read 4, iclass 26, count 0 2006.173.20:40:09.55#ibcon#about to read 5, iclass 26, count 0 2006.173.20:40:09.55#ibcon#read 5, iclass 26, count 0 2006.173.20:40:09.55#ibcon#about to read 6, iclass 26, count 0 2006.173.20:40:09.55#ibcon#read 6, iclass 26, count 0 2006.173.20:40:09.55#ibcon#end of sib2, iclass 26, count 0 2006.173.20:40:09.55#ibcon#*after write, iclass 26, count 0 2006.173.20:40:09.55#ibcon#*before return 0, iclass 26, count 0 2006.173.20:40:09.55#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.20:40:09.55#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.20:40:09.55#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.20:40:09.55#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.20:40:09.55$vck44/valo=8,884.99 2006.173.20:40:09.55#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.20:40:09.55#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.20:40:09.55#ibcon#ireg 17 cls_cnt 0 2006.173.20:40:09.55#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.20:40:09.55#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.20:40:09.55#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.20:40:09.55#ibcon#enter wrdev, iclass 28, count 0 2006.173.20:40:09.55#ibcon#first serial, iclass 28, count 0 2006.173.20:40:09.55#ibcon#enter sib2, iclass 28, count 0 2006.173.20:40:09.55#ibcon#flushed, iclass 28, count 0 2006.173.20:40:09.55#ibcon#about to write, iclass 28, count 0 2006.173.20:40:09.55#ibcon#wrote, iclass 28, count 0 2006.173.20:40:09.55#ibcon#about to read 3, iclass 28, count 0 2006.173.20:40:09.57#ibcon#read 3, iclass 28, count 0 2006.173.20:40:09.57#ibcon#about to read 4, iclass 28, count 0 2006.173.20:40:09.57#ibcon#read 4, iclass 28, count 0 2006.173.20:40:09.57#ibcon#about to read 5, iclass 28, count 0 2006.173.20:40:09.57#ibcon#read 5, iclass 28, count 0 2006.173.20:40:09.57#ibcon#about to read 6, iclass 28, count 0 2006.173.20:40:09.57#ibcon#read 6, iclass 28, count 0 2006.173.20:40:09.57#ibcon#end of sib2, iclass 28, count 0 2006.173.20:40:09.57#ibcon#*mode == 0, iclass 28, count 0 2006.173.20:40:09.57#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.20:40:09.57#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.20:40:09.57#ibcon#*before write, iclass 28, count 0 2006.173.20:40:09.57#ibcon#enter sib2, iclass 28, count 0 2006.173.20:40:09.57#ibcon#flushed, iclass 28, count 0 2006.173.20:40:09.57#ibcon#about to write, iclass 28, count 0 2006.173.20:40:09.57#ibcon#wrote, iclass 28, count 0 2006.173.20:40:09.57#ibcon#about to read 3, iclass 28, count 0 2006.173.20:40:09.61#ibcon#read 3, iclass 28, count 0 2006.173.20:40:09.61#ibcon#about to read 4, iclass 28, count 0 2006.173.20:40:09.61#ibcon#read 4, iclass 28, count 0 2006.173.20:40:09.61#ibcon#about to read 5, iclass 28, count 0 2006.173.20:40:09.61#ibcon#read 5, iclass 28, count 0 2006.173.20:40:09.61#ibcon#about to read 6, iclass 28, count 0 2006.173.20:40:09.61#ibcon#read 6, iclass 28, count 0 2006.173.20:40:09.61#ibcon#end of sib2, iclass 28, count 0 2006.173.20:40:09.61#ibcon#*after write, iclass 28, count 0 2006.173.20:40:09.61#ibcon#*before return 0, iclass 28, count 0 2006.173.20:40:09.61#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.20:40:09.61#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.20:40:09.61#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.20:40:09.61#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.20:40:09.61$vck44/va=8,4 2006.173.20:40:09.61#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.20:40:09.61#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.20:40:09.61#ibcon#ireg 11 cls_cnt 2 2006.173.20:40:09.61#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.20:40:09.67#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.20:40:09.67#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.20:40:09.67#ibcon#enter wrdev, iclass 30, count 2 2006.173.20:40:09.67#ibcon#first serial, iclass 30, count 2 2006.173.20:40:09.67#ibcon#enter sib2, iclass 30, count 2 2006.173.20:40:09.67#ibcon#flushed, iclass 30, count 2 2006.173.20:40:09.67#ibcon#about to write, iclass 30, count 2 2006.173.20:40:09.67#ibcon#wrote, iclass 30, count 2 2006.173.20:40:09.67#ibcon#about to read 3, iclass 30, count 2 2006.173.20:40:09.69#ibcon#read 3, iclass 30, count 2 2006.173.20:40:09.69#ibcon#about to read 4, iclass 30, count 2 2006.173.20:40:09.69#ibcon#read 4, iclass 30, count 2 2006.173.20:40:09.69#ibcon#about to read 5, iclass 30, count 2 2006.173.20:40:09.69#ibcon#read 5, iclass 30, count 2 2006.173.20:40:09.69#ibcon#about to read 6, iclass 30, count 2 2006.173.20:40:09.69#ibcon#read 6, iclass 30, count 2 2006.173.20:40:09.69#ibcon#end of sib2, iclass 30, count 2 2006.173.20:40:09.69#ibcon#*mode == 0, iclass 30, count 2 2006.173.20:40:09.69#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.20:40:09.69#ibcon#[25=AT08-04\r\n] 2006.173.20:40:09.69#ibcon#*before write, iclass 30, count 2 2006.173.20:40:09.69#ibcon#enter sib2, iclass 30, count 2 2006.173.20:40:09.69#ibcon#flushed, iclass 30, count 2 2006.173.20:40:09.69#ibcon#about to write, iclass 30, count 2 2006.173.20:40:09.69#ibcon#wrote, iclass 30, count 2 2006.173.20:40:09.69#ibcon#about to read 3, iclass 30, count 2 2006.173.20:40:09.72#ibcon#read 3, iclass 30, count 2 2006.173.20:40:09.72#ibcon#about to read 4, iclass 30, count 2 2006.173.20:40:09.72#ibcon#read 4, iclass 30, count 2 2006.173.20:40:09.72#ibcon#about to read 5, iclass 30, count 2 2006.173.20:40:09.72#ibcon#read 5, iclass 30, count 2 2006.173.20:40:09.72#ibcon#about to read 6, iclass 30, count 2 2006.173.20:40:09.72#ibcon#read 6, iclass 30, count 2 2006.173.20:40:09.72#ibcon#end of sib2, iclass 30, count 2 2006.173.20:40:09.72#ibcon#*after write, iclass 30, count 2 2006.173.20:40:09.72#ibcon#*before return 0, iclass 30, count 2 2006.173.20:40:09.72#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.20:40:09.72#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.20:40:09.72#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.20:40:09.72#ibcon#ireg 7 cls_cnt 0 2006.173.20:40:09.72#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.20:40:09.84#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.20:40:09.84#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.20:40:09.84#ibcon#enter wrdev, iclass 30, count 0 2006.173.20:40:09.84#ibcon#first serial, iclass 30, count 0 2006.173.20:40:09.84#ibcon#enter sib2, iclass 30, count 0 2006.173.20:40:09.84#ibcon#flushed, iclass 30, count 0 2006.173.20:40:09.84#ibcon#about to write, iclass 30, count 0 2006.173.20:40:09.84#ibcon#wrote, iclass 30, count 0 2006.173.20:40:09.84#ibcon#about to read 3, iclass 30, count 0 2006.173.20:40:09.86#ibcon#read 3, iclass 30, count 0 2006.173.20:40:09.86#ibcon#about to read 4, iclass 30, count 0 2006.173.20:40:09.86#ibcon#read 4, iclass 30, count 0 2006.173.20:40:09.86#ibcon#about to read 5, iclass 30, count 0 2006.173.20:40:09.86#ibcon#read 5, iclass 30, count 0 2006.173.20:40:09.86#ibcon#about to read 6, iclass 30, count 0 2006.173.20:40:09.86#ibcon#read 6, iclass 30, count 0 2006.173.20:40:09.86#ibcon#end of sib2, iclass 30, count 0 2006.173.20:40:09.86#ibcon#*mode == 0, iclass 30, count 0 2006.173.20:40:09.86#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.20:40:09.86#ibcon#[25=USB\r\n] 2006.173.20:40:09.86#ibcon#*before write, iclass 30, count 0 2006.173.20:40:09.86#ibcon#enter sib2, iclass 30, count 0 2006.173.20:40:09.86#ibcon#flushed, iclass 30, count 0 2006.173.20:40:09.86#ibcon#about to write, iclass 30, count 0 2006.173.20:40:09.86#ibcon#wrote, iclass 30, count 0 2006.173.20:40:09.86#ibcon#about to read 3, iclass 30, count 0 2006.173.20:40:09.89#ibcon#read 3, iclass 30, count 0 2006.173.20:40:09.89#ibcon#about to read 4, iclass 30, count 0 2006.173.20:40:09.89#ibcon#read 4, iclass 30, count 0 2006.173.20:40:09.89#ibcon#about to read 5, iclass 30, count 0 2006.173.20:40:09.89#ibcon#read 5, iclass 30, count 0 2006.173.20:40:09.89#ibcon#about to read 6, iclass 30, count 0 2006.173.20:40:09.89#ibcon#read 6, iclass 30, count 0 2006.173.20:40:09.89#ibcon#end of sib2, iclass 30, count 0 2006.173.20:40:09.89#ibcon#*after write, iclass 30, count 0 2006.173.20:40:09.89#ibcon#*before return 0, iclass 30, count 0 2006.173.20:40:09.89#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.20:40:09.89#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.20:40:09.89#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.20:40:09.89#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.20:40:09.89$vck44/vblo=1,629.99 2006.173.20:40:09.89#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.20:40:09.89#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.20:40:09.89#ibcon#ireg 17 cls_cnt 0 2006.173.20:40:09.89#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.20:40:09.89#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.20:40:09.89#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.20:40:09.89#ibcon#enter wrdev, iclass 32, count 0 2006.173.20:40:09.89#ibcon#first serial, iclass 32, count 0 2006.173.20:40:09.89#ibcon#enter sib2, iclass 32, count 0 2006.173.20:40:09.89#ibcon#flushed, iclass 32, count 0 2006.173.20:40:09.89#ibcon#about to write, iclass 32, count 0 2006.173.20:40:09.89#ibcon#wrote, iclass 32, count 0 2006.173.20:40:09.89#ibcon#about to read 3, iclass 32, count 0 2006.173.20:40:09.91#ibcon#read 3, iclass 32, count 0 2006.173.20:40:09.91#ibcon#about to read 4, iclass 32, count 0 2006.173.20:40:09.91#ibcon#read 4, iclass 32, count 0 2006.173.20:40:09.91#ibcon#about to read 5, iclass 32, count 0 2006.173.20:40:09.91#ibcon#read 5, iclass 32, count 0 2006.173.20:40:09.91#ibcon#about to read 6, iclass 32, count 0 2006.173.20:40:09.91#ibcon#read 6, iclass 32, count 0 2006.173.20:40:09.91#ibcon#end of sib2, iclass 32, count 0 2006.173.20:40:09.91#ibcon#*mode == 0, iclass 32, count 0 2006.173.20:40:09.91#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.20:40:09.91#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.20:40:09.91#ibcon#*before write, iclass 32, count 0 2006.173.20:40:09.91#ibcon#enter sib2, iclass 32, count 0 2006.173.20:40:09.91#ibcon#flushed, iclass 32, count 0 2006.173.20:40:09.91#ibcon#about to write, iclass 32, count 0 2006.173.20:40:09.91#ibcon#wrote, iclass 32, count 0 2006.173.20:40:09.91#ibcon#about to read 3, iclass 32, count 0 2006.173.20:40:09.95#ibcon#read 3, iclass 32, count 0 2006.173.20:40:09.95#ibcon#about to read 4, iclass 32, count 0 2006.173.20:40:09.95#ibcon#read 4, iclass 32, count 0 2006.173.20:40:09.95#ibcon#about to read 5, iclass 32, count 0 2006.173.20:40:09.95#ibcon#read 5, iclass 32, count 0 2006.173.20:40:09.95#ibcon#about to read 6, iclass 32, count 0 2006.173.20:40:09.95#ibcon#read 6, iclass 32, count 0 2006.173.20:40:09.95#ibcon#end of sib2, iclass 32, count 0 2006.173.20:40:09.95#ibcon#*after write, iclass 32, count 0 2006.173.20:40:09.95#ibcon#*before return 0, iclass 32, count 0 2006.173.20:40:09.95#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.20:40:09.95#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.20:40:09.95#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.20:40:09.95#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.20:40:09.95$vck44/vb=1,4 2006.173.20:40:09.95#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.20:40:09.95#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.20:40:09.95#ibcon#ireg 11 cls_cnt 2 2006.173.20:40:09.95#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.20:40:09.95#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.20:40:09.95#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.20:40:09.95#ibcon#enter wrdev, iclass 34, count 2 2006.173.20:40:09.95#ibcon#first serial, iclass 34, count 2 2006.173.20:40:09.95#ibcon#enter sib2, iclass 34, count 2 2006.173.20:40:09.95#ibcon#flushed, iclass 34, count 2 2006.173.20:40:09.95#ibcon#about to write, iclass 34, count 2 2006.173.20:40:09.95#ibcon#wrote, iclass 34, count 2 2006.173.20:40:09.95#ibcon#about to read 3, iclass 34, count 2 2006.173.20:40:09.97#ibcon#read 3, iclass 34, count 2 2006.173.20:40:09.97#ibcon#about to read 4, iclass 34, count 2 2006.173.20:40:09.97#ibcon#read 4, iclass 34, count 2 2006.173.20:40:09.97#ibcon#about to read 5, iclass 34, count 2 2006.173.20:40:09.97#ibcon#read 5, iclass 34, count 2 2006.173.20:40:09.97#ibcon#about to read 6, iclass 34, count 2 2006.173.20:40:09.97#ibcon#read 6, iclass 34, count 2 2006.173.20:40:09.97#ibcon#end of sib2, iclass 34, count 2 2006.173.20:40:09.97#ibcon#*mode == 0, iclass 34, count 2 2006.173.20:40:09.97#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.20:40:09.97#ibcon#[27=AT01-04\r\n] 2006.173.20:40:09.97#ibcon#*before write, iclass 34, count 2 2006.173.20:40:09.97#ibcon#enter sib2, iclass 34, count 2 2006.173.20:40:09.97#ibcon#flushed, iclass 34, count 2 2006.173.20:40:09.97#ibcon#about to write, iclass 34, count 2 2006.173.20:40:09.97#ibcon#wrote, iclass 34, count 2 2006.173.20:40:09.97#ibcon#about to read 3, iclass 34, count 2 2006.173.20:40:10.00#ibcon#read 3, iclass 34, count 2 2006.173.20:40:10.14#ibcon#about to read 4, iclass 34, count 2 2006.173.20:40:10.14#ibcon#read 4, iclass 34, count 2 2006.173.20:40:10.14#ibcon#about to read 5, iclass 34, count 2 2006.173.20:40:10.14#ibcon#read 5, iclass 34, count 2 2006.173.20:40:10.14#ibcon#about to read 6, iclass 34, count 2 2006.173.20:40:10.14#ibcon#read 6, iclass 34, count 2 2006.173.20:40:10.14#ibcon#end of sib2, iclass 34, count 2 2006.173.20:40:10.14#ibcon#*after write, iclass 34, count 2 2006.173.20:40:10.14#ibcon#*before return 0, iclass 34, count 2 2006.173.20:40:10.14#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.20:40:10.14#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.20:40:10.14#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.20:40:10.14#ibcon#ireg 7 cls_cnt 0 2006.173.20:40:10.14#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.20:40:10.26#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.20:40:10.26#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.20:40:10.26#ibcon#enter wrdev, iclass 34, count 0 2006.173.20:40:10.26#ibcon#first serial, iclass 34, count 0 2006.173.20:40:10.26#ibcon#enter sib2, iclass 34, count 0 2006.173.20:40:10.26#ibcon#flushed, iclass 34, count 0 2006.173.20:40:10.26#ibcon#about to write, iclass 34, count 0 2006.173.20:40:10.26#ibcon#wrote, iclass 34, count 0 2006.173.20:40:10.26#ibcon#about to read 3, iclass 34, count 0 2006.173.20:40:10.28#ibcon#read 3, iclass 34, count 0 2006.173.20:40:10.28#ibcon#about to read 4, iclass 34, count 0 2006.173.20:40:10.28#ibcon#read 4, iclass 34, count 0 2006.173.20:40:10.28#ibcon#about to read 5, iclass 34, count 0 2006.173.20:40:10.28#ibcon#read 5, iclass 34, count 0 2006.173.20:40:10.28#ibcon#about to read 6, iclass 34, count 0 2006.173.20:40:10.28#ibcon#read 6, iclass 34, count 0 2006.173.20:40:10.28#ibcon#end of sib2, iclass 34, count 0 2006.173.20:40:10.28#ibcon#*mode == 0, iclass 34, count 0 2006.173.20:40:10.28#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.20:40:10.28#ibcon#[27=USB\r\n] 2006.173.20:40:10.28#ibcon#*before write, iclass 34, count 0 2006.173.20:40:10.28#ibcon#enter sib2, iclass 34, count 0 2006.173.20:40:10.28#ibcon#flushed, iclass 34, count 0 2006.173.20:40:10.28#ibcon#about to write, iclass 34, count 0 2006.173.20:40:10.28#ibcon#wrote, iclass 34, count 0 2006.173.20:40:10.28#ibcon#about to read 3, iclass 34, count 0 2006.173.20:40:10.31#ibcon#read 3, iclass 34, count 0 2006.173.20:40:10.31#ibcon#about to read 4, iclass 34, count 0 2006.173.20:40:10.31#ibcon#read 4, iclass 34, count 0 2006.173.20:40:10.31#ibcon#about to read 5, iclass 34, count 0 2006.173.20:40:10.31#ibcon#read 5, iclass 34, count 0 2006.173.20:40:10.31#ibcon#about to read 6, iclass 34, count 0 2006.173.20:40:10.31#ibcon#read 6, iclass 34, count 0 2006.173.20:40:10.31#ibcon#end of sib2, iclass 34, count 0 2006.173.20:40:10.31#ibcon#*after write, iclass 34, count 0 2006.173.20:40:10.31#ibcon#*before return 0, iclass 34, count 0 2006.173.20:40:10.31#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.20:40:10.31#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.20:40:10.31#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.20:40:10.31#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.20:40:10.31$vck44/vblo=2,634.99 2006.173.20:40:10.31#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.20:40:10.31#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.20:40:10.31#ibcon#ireg 17 cls_cnt 0 2006.173.20:40:10.31#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.20:40:10.31#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.20:40:10.31#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.20:40:10.31#ibcon#enter wrdev, iclass 36, count 0 2006.173.20:40:10.31#ibcon#first serial, iclass 36, count 0 2006.173.20:40:10.31#ibcon#enter sib2, iclass 36, count 0 2006.173.20:40:10.31#ibcon#flushed, iclass 36, count 0 2006.173.20:40:10.31#ibcon#about to write, iclass 36, count 0 2006.173.20:40:10.31#ibcon#wrote, iclass 36, count 0 2006.173.20:40:10.31#ibcon#about to read 3, iclass 36, count 0 2006.173.20:40:10.33#ibcon#read 3, iclass 36, count 0 2006.173.20:40:10.33#ibcon#about to read 4, iclass 36, count 0 2006.173.20:40:10.33#ibcon#read 4, iclass 36, count 0 2006.173.20:40:10.33#ibcon#about to read 5, iclass 36, count 0 2006.173.20:40:10.33#ibcon#read 5, iclass 36, count 0 2006.173.20:40:10.33#ibcon#about to read 6, iclass 36, count 0 2006.173.20:40:10.33#ibcon#read 6, iclass 36, count 0 2006.173.20:40:10.33#ibcon#end of sib2, iclass 36, count 0 2006.173.20:40:10.33#ibcon#*mode == 0, iclass 36, count 0 2006.173.20:40:10.33#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.20:40:10.33#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.20:40:10.33#ibcon#*before write, iclass 36, count 0 2006.173.20:40:10.33#ibcon#enter sib2, iclass 36, count 0 2006.173.20:40:10.33#ibcon#flushed, iclass 36, count 0 2006.173.20:40:10.33#ibcon#about to write, iclass 36, count 0 2006.173.20:40:10.33#ibcon#wrote, iclass 36, count 0 2006.173.20:40:10.33#ibcon#about to read 3, iclass 36, count 0 2006.173.20:40:10.37#ibcon#read 3, iclass 36, count 0 2006.173.20:40:10.37#ibcon#about to read 4, iclass 36, count 0 2006.173.20:40:10.37#ibcon#read 4, iclass 36, count 0 2006.173.20:40:10.37#ibcon#about to read 5, iclass 36, count 0 2006.173.20:40:10.37#ibcon#read 5, iclass 36, count 0 2006.173.20:40:10.37#ibcon#about to read 6, iclass 36, count 0 2006.173.20:40:10.37#ibcon#read 6, iclass 36, count 0 2006.173.20:40:10.37#ibcon#end of sib2, iclass 36, count 0 2006.173.20:40:10.37#ibcon#*after write, iclass 36, count 0 2006.173.20:40:10.37#ibcon#*before return 0, iclass 36, count 0 2006.173.20:40:10.37#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.20:40:10.37#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.20:40:10.37#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.20:40:10.37#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.20:40:10.37$vck44/vb=2,4 2006.173.20:40:10.37#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.20:40:10.37#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.20:40:10.37#ibcon#ireg 11 cls_cnt 2 2006.173.20:40:10.37#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.20:40:10.43#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.20:40:10.43#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.20:40:10.43#ibcon#enter wrdev, iclass 38, count 2 2006.173.20:40:10.43#ibcon#first serial, iclass 38, count 2 2006.173.20:40:10.43#ibcon#enter sib2, iclass 38, count 2 2006.173.20:40:10.43#ibcon#flushed, iclass 38, count 2 2006.173.20:40:10.43#ibcon#about to write, iclass 38, count 2 2006.173.20:40:10.43#ibcon#wrote, iclass 38, count 2 2006.173.20:40:10.43#ibcon#about to read 3, iclass 38, count 2 2006.173.20:40:10.45#ibcon#read 3, iclass 38, count 2 2006.173.20:40:10.45#ibcon#about to read 4, iclass 38, count 2 2006.173.20:40:10.45#ibcon#read 4, iclass 38, count 2 2006.173.20:40:10.45#ibcon#about to read 5, iclass 38, count 2 2006.173.20:40:10.45#ibcon#read 5, iclass 38, count 2 2006.173.20:40:10.45#ibcon#about to read 6, iclass 38, count 2 2006.173.20:40:10.45#ibcon#read 6, iclass 38, count 2 2006.173.20:40:10.45#ibcon#end of sib2, iclass 38, count 2 2006.173.20:40:10.45#ibcon#*mode == 0, iclass 38, count 2 2006.173.20:40:10.45#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.20:40:10.45#ibcon#[27=AT02-04\r\n] 2006.173.20:40:10.45#ibcon#*before write, iclass 38, count 2 2006.173.20:40:10.45#ibcon#enter sib2, iclass 38, count 2 2006.173.20:40:10.45#ibcon#flushed, iclass 38, count 2 2006.173.20:40:10.45#ibcon#about to write, iclass 38, count 2 2006.173.20:40:10.45#ibcon#wrote, iclass 38, count 2 2006.173.20:40:10.45#ibcon#about to read 3, iclass 38, count 2 2006.173.20:40:10.48#ibcon#read 3, iclass 38, count 2 2006.173.20:40:10.48#ibcon#about to read 4, iclass 38, count 2 2006.173.20:40:10.48#ibcon#read 4, iclass 38, count 2 2006.173.20:40:10.48#ibcon#about to read 5, iclass 38, count 2 2006.173.20:40:10.48#ibcon#read 5, iclass 38, count 2 2006.173.20:40:10.48#ibcon#about to read 6, iclass 38, count 2 2006.173.20:40:10.48#ibcon#read 6, iclass 38, count 2 2006.173.20:40:10.48#ibcon#end of sib2, iclass 38, count 2 2006.173.20:40:10.48#ibcon#*after write, iclass 38, count 2 2006.173.20:40:10.48#ibcon#*before return 0, iclass 38, count 2 2006.173.20:40:10.48#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.20:40:10.48#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.20:40:10.48#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.20:40:10.48#ibcon#ireg 7 cls_cnt 0 2006.173.20:40:10.48#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.20:40:10.60#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.20:40:10.60#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.20:40:10.60#ibcon#enter wrdev, iclass 38, count 0 2006.173.20:40:10.60#ibcon#first serial, iclass 38, count 0 2006.173.20:40:10.60#ibcon#enter sib2, iclass 38, count 0 2006.173.20:40:10.60#ibcon#flushed, iclass 38, count 0 2006.173.20:40:10.60#ibcon#about to write, iclass 38, count 0 2006.173.20:40:10.60#ibcon#wrote, iclass 38, count 0 2006.173.20:40:10.60#ibcon#about to read 3, iclass 38, count 0 2006.173.20:40:10.62#ibcon#read 3, iclass 38, count 0 2006.173.20:40:10.62#ibcon#about to read 4, iclass 38, count 0 2006.173.20:40:10.62#ibcon#read 4, iclass 38, count 0 2006.173.20:40:10.62#ibcon#about to read 5, iclass 38, count 0 2006.173.20:40:10.62#ibcon#read 5, iclass 38, count 0 2006.173.20:40:10.62#ibcon#about to read 6, iclass 38, count 0 2006.173.20:40:10.62#ibcon#read 6, iclass 38, count 0 2006.173.20:40:10.62#ibcon#end of sib2, iclass 38, count 0 2006.173.20:40:10.62#ibcon#*mode == 0, iclass 38, count 0 2006.173.20:40:10.62#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.20:40:10.62#ibcon#[27=USB\r\n] 2006.173.20:40:10.62#ibcon#*before write, iclass 38, count 0 2006.173.20:40:10.62#ibcon#enter sib2, iclass 38, count 0 2006.173.20:40:10.62#ibcon#flushed, iclass 38, count 0 2006.173.20:40:10.62#ibcon#about to write, iclass 38, count 0 2006.173.20:40:10.62#ibcon#wrote, iclass 38, count 0 2006.173.20:40:10.62#ibcon#about to read 3, iclass 38, count 0 2006.173.20:40:10.65#ibcon#read 3, iclass 38, count 0 2006.173.20:40:10.65#ibcon#about to read 4, iclass 38, count 0 2006.173.20:40:10.65#ibcon#read 4, iclass 38, count 0 2006.173.20:40:10.65#ibcon#about to read 5, iclass 38, count 0 2006.173.20:40:10.65#ibcon#read 5, iclass 38, count 0 2006.173.20:40:10.65#ibcon#about to read 6, iclass 38, count 0 2006.173.20:40:10.65#ibcon#read 6, iclass 38, count 0 2006.173.20:40:10.65#ibcon#end of sib2, iclass 38, count 0 2006.173.20:40:10.65#ibcon#*after write, iclass 38, count 0 2006.173.20:40:10.65#ibcon#*before return 0, iclass 38, count 0 2006.173.20:40:10.65#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.20:40:10.65#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.20:40:10.65#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.20:40:10.65#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.20:40:10.65$vck44/vblo=3,649.99 2006.173.20:40:10.65#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.20:40:10.65#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.20:40:10.65#ibcon#ireg 17 cls_cnt 0 2006.173.20:40:10.65#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.20:40:10.65#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.20:40:10.65#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.20:40:10.65#ibcon#enter wrdev, iclass 40, count 0 2006.173.20:40:10.65#ibcon#first serial, iclass 40, count 0 2006.173.20:40:10.65#ibcon#enter sib2, iclass 40, count 0 2006.173.20:40:10.65#ibcon#flushed, iclass 40, count 0 2006.173.20:40:10.65#ibcon#about to write, iclass 40, count 0 2006.173.20:40:10.65#ibcon#wrote, iclass 40, count 0 2006.173.20:40:10.65#ibcon#about to read 3, iclass 40, count 0 2006.173.20:40:10.67#ibcon#read 3, iclass 40, count 0 2006.173.20:40:10.67#ibcon#about to read 4, iclass 40, count 0 2006.173.20:40:10.67#ibcon#read 4, iclass 40, count 0 2006.173.20:40:10.67#ibcon#about to read 5, iclass 40, count 0 2006.173.20:40:10.67#ibcon#read 5, iclass 40, count 0 2006.173.20:40:10.67#ibcon#about to read 6, iclass 40, count 0 2006.173.20:40:10.67#ibcon#read 6, iclass 40, count 0 2006.173.20:40:10.67#ibcon#end of sib2, iclass 40, count 0 2006.173.20:40:10.67#ibcon#*mode == 0, iclass 40, count 0 2006.173.20:40:10.67#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.20:40:10.67#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.20:40:10.67#ibcon#*before write, iclass 40, count 0 2006.173.20:40:10.67#ibcon#enter sib2, iclass 40, count 0 2006.173.20:40:10.67#ibcon#flushed, iclass 40, count 0 2006.173.20:40:10.67#ibcon#about to write, iclass 40, count 0 2006.173.20:40:10.67#ibcon#wrote, iclass 40, count 0 2006.173.20:40:10.67#ibcon#about to read 3, iclass 40, count 0 2006.173.20:40:10.71#ibcon#read 3, iclass 40, count 0 2006.173.20:40:10.71#ibcon#about to read 4, iclass 40, count 0 2006.173.20:40:10.71#ibcon#read 4, iclass 40, count 0 2006.173.20:40:10.71#ibcon#about to read 5, iclass 40, count 0 2006.173.20:40:10.71#ibcon#read 5, iclass 40, count 0 2006.173.20:40:10.71#ibcon#about to read 6, iclass 40, count 0 2006.173.20:40:10.71#ibcon#read 6, iclass 40, count 0 2006.173.20:40:10.71#ibcon#end of sib2, iclass 40, count 0 2006.173.20:40:10.71#ibcon#*after write, iclass 40, count 0 2006.173.20:40:10.71#ibcon#*before return 0, iclass 40, count 0 2006.173.20:40:10.71#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.20:40:10.71#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.20:40:10.71#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.20:40:10.71#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.20:40:10.71$vck44/vb=3,4 2006.173.20:40:10.71#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.20:40:10.71#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.20:40:10.71#ibcon#ireg 11 cls_cnt 2 2006.173.20:40:10.71#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.20:40:10.77#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.20:40:10.77#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.20:40:10.77#ibcon#enter wrdev, iclass 4, count 2 2006.173.20:40:10.77#ibcon#first serial, iclass 4, count 2 2006.173.20:40:10.77#ibcon#enter sib2, iclass 4, count 2 2006.173.20:40:10.77#ibcon#flushed, iclass 4, count 2 2006.173.20:40:10.77#ibcon#about to write, iclass 4, count 2 2006.173.20:40:10.77#ibcon#wrote, iclass 4, count 2 2006.173.20:40:10.77#ibcon#about to read 3, iclass 4, count 2 2006.173.20:40:10.79#ibcon#read 3, iclass 4, count 2 2006.173.20:40:10.79#ibcon#about to read 4, iclass 4, count 2 2006.173.20:40:10.79#ibcon#read 4, iclass 4, count 2 2006.173.20:40:10.79#ibcon#about to read 5, iclass 4, count 2 2006.173.20:40:10.79#ibcon#read 5, iclass 4, count 2 2006.173.20:40:10.79#ibcon#about to read 6, iclass 4, count 2 2006.173.20:40:10.79#ibcon#read 6, iclass 4, count 2 2006.173.20:40:10.79#ibcon#end of sib2, iclass 4, count 2 2006.173.20:40:10.79#ibcon#*mode == 0, iclass 4, count 2 2006.173.20:40:10.79#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.20:40:10.79#ibcon#[27=AT03-04\r\n] 2006.173.20:40:10.79#ibcon#*before write, iclass 4, count 2 2006.173.20:40:10.79#ibcon#enter sib2, iclass 4, count 2 2006.173.20:40:10.79#ibcon#flushed, iclass 4, count 2 2006.173.20:40:10.79#ibcon#about to write, iclass 4, count 2 2006.173.20:40:10.79#ibcon#wrote, iclass 4, count 2 2006.173.20:40:10.79#ibcon#about to read 3, iclass 4, count 2 2006.173.20:40:10.82#ibcon#read 3, iclass 4, count 2 2006.173.20:40:10.82#ibcon#about to read 4, iclass 4, count 2 2006.173.20:40:10.82#ibcon#read 4, iclass 4, count 2 2006.173.20:40:10.82#ibcon#about to read 5, iclass 4, count 2 2006.173.20:40:10.82#ibcon#read 5, iclass 4, count 2 2006.173.20:40:10.82#ibcon#about to read 6, iclass 4, count 2 2006.173.20:40:10.82#ibcon#read 6, iclass 4, count 2 2006.173.20:40:10.82#ibcon#end of sib2, iclass 4, count 2 2006.173.20:40:10.82#ibcon#*after write, iclass 4, count 2 2006.173.20:40:10.82#ibcon#*before return 0, iclass 4, count 2 2006.173.20:40:10.82#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.20:40:10.82#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.20:40:10.82#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.20:40:10.82#ibcon#ireg 7 cls_cnt 0 2006.173.20:40:10.82#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.20:40:10.94#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.20:40:10.94#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.20:40:10.94#ibcon#enter wrdev, iclass 4, count 0 2006.173.20:40:10.94#ibcon#first serial, iclass 4, count 0 2006.173.20:40:10.94#ibcon#enter sib2, iclass 4, count 0 2006.173.20:40:10.94#ibcon#flushed, iclass 4, count 0 2006.173.20:40:10.94#ibcon#about to write, iclass 4, count 0 2006.173.20:40:10.94#ibcon#wrote, iclass 4, count 0 2006.173.20:40:10.94#ibcon#about to read 3, iclass 4, count 0 2006.173.20:40:10.96#ibcon#read 3, iclass 4, count 0 2006.173.20:40:10.96#ibcon#about to read 4, iclass 4, count 0 2006.173.20:40:10.96#ibcon#read 4, iclass 4, count 0 2006.173.20:40:10.96#ibcon#about to read 5, iclass 4, count 0 2006.173.20:40:10.96#ibcon#read 5, iclass 4, count 0 2006.173.20:40:10.96#ibcon#about to read 6, iclass 4, count 0 2006.173.20:40:10.96#ibcon#read 6, iclass 4, count 0 2006.173.20:40:10.96#ibcon#end of sib2, iclass 4, count 0 2006.173.20:40:10.96#ibcon#*mode == 0, iclass 4, count 0 2006.173.20:40:10.96#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.20:40:10.96#ibcon#[27=USB\r\n] 2006.173.20:40:10.96#ibcon#*before write, iclass 4, count 0 2006.173.20:40:10.96#ibcon#enter sib2, iclass 4, count 0 2006.173.20:40:10.96#ibcon#flushed, iclass 4, count 0 2006.173.20:40:10.96#ibcon#about to write, iclass 4, count 0 2006.173.20:40:10.96#ibcon#wrote, iclass 4, count 0 2006.173.20:40:10.96#ibcon#about to read 3, iclass 4, count 0 2006.173.20:40:10.99#ibcon#read 3, iclass 4, count 0 2006.173.20:40:10.99#ibcon#about to read 4, iclass 4, count 0 2006.173.20:40:10.99#ibcon#read 4, iclass 4, count 0 2006.173.20:40:10.99#ibcon#about to read 5, iclass 4, count 0 2006.173.20:40:10.99#ibcon#read 5, iclass 4, count 0 2006.173.20:40:10.99#ibcon#about to read 6, iclass 4, count 0 2006.173.20:40:10.99#ibcon#read 6, iclass 4, count 0 2006.173.20:40:10.99#ibcon#end of sib2, iclass 4, count 0 2006.173.20:40:10.99#ibcon#*after write, iclass 4, count 0 2006.173.20:40:10.99#ibcon#*before return 0, iclass 4, count 0 2006.173.20:40:10.99#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.20:40:10.99#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.20:40:10.99#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.20:40:10.99#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.20:40:10.99$vck44/vblo=4,679.99 2006.173.20:40:10.99#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.20:40:10.99#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.20:40:10.99#ibcon#ireg 17 cls_cnt 0 2006.173.20:40:10.99#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.20:40:10.99#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.20:40:10.99#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.20:40:10.99#ibcon#enter wrdev, iclass 6, count 0 2006.173.20:40:10.99#ibcon#first serial, iclass 6, count 0 2006.173.20:40:10.99#ibcon#enter sib2, iclass 6, count 0 2006.173.20:40:10.99#ibcon#flushed, iclass 6, count 0 2006.173.20:40:10.99#ibcon#about to write, iclass 6, count 0 2006.173.20:40:10.99#ibcon#wrote, iclass 6, count 0 2006.173.20:40:10.99#ibcon#about to read 3, iclass 6, count 0 2006.173.20:40:11.01#ibcon#read 3, iclass 6, count 0 2006.173.20:40:11.01#ibcon#about to read 4, iclass 6, count 0 2006.173.20:40:11.01#ibcon#read 4, iclass 6, count 0 2006.173.20:40:11.01#ibcon#about to read 5, iclass 6, count 0 2006.173.20:40:11.01#ibcon#read 5, iclass 6, count 0 2006.173.20:40:11.01#ibcon#about to read 6, iclass 6, count 0 2006.173.20:40:11.01#ibcon#read 6, iclass 6, count 0 2006.173.20:40:11.01#ibcon#end of sib2, iclass 6, count 0 2006.173.20:40:11.01#ibcon#*mode == 0, iclass 6, count 0 2006.173.20:40:11.01#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.20:40:11.01#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.20:40:11.01#ibcon#*before write, iclass 6, count 0 2006.173.20:40:11.01#ibcon#enter sib2, iclass 6, count 0 2006.173.20:40:11.01#ibcon#flushed, iclass 6, count 0 2006.173.20:40:11.01#ibcon#about to write, iclass 6, count 0 2006.173.20:40:11.01#ibcon#wrote, iclass 6, count 0 2006.173.20:40:11.01#ibcon#about to read 3, iclass 6, count 0 2006.173.20:40:11.05#ibcon#read 3, iclass 6, count 0 2006.173.20:40:11.05#ibcon#about to read 4, iclass 6, count 0 2006.173.20:40:11.05#ibcon#read 4, iclass 6, count 0 2006.173.20:40:11.05#ibcon#about to read 5, iclass 6, count 0 2006.173.20:40:11.05#ibcon#read 5, iclass 6, count 0 2006.173.20:40:11.05#ibcon#about to read 6, iclass 6, count 0 2006.173.20:40:11.05#ibcon#read 6, iclass 6, count 0 2006.173.20:40:11.05#ibcon#end of sib2, iclass 6, count 0 2006.173.20:40:11.05#ibcon#*after write, iclass 6, count 0 2006.173.20:40:11.05#ibcon#*before return 0, iclass 6, count 0 2006.173.20:40:11.05#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.20:40:11.05#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.20:40:11.05#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.20:40:11.05#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.20:40:11.05$vck44/vb=4,4 2006.173.20:40:11.05#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.20:40:11.05#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.20:40:11.05#ibcon#ireg 11 cls_cnt 2 2006.173.20:40:11.05#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.20:40:11.11#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.20:40:11.11#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.20:40:11.11#ibcon#enter wrdev, iclass 10, count 2 2006.173.20:40:11.11#ibcon#first serial, iclass 10, count 2 2006.173.20:40:11.11#ibcon#enter sib2, iclass 10, count 2 2006.173.20:40:11.11#ibcon#flushed, iclass 10, count 2 2006.173.20:40:11.11#ibcon#about to write, iclass 10, count 2 2006.173.20:40:11.11#ibcon#wrote, iclass 10, count 2 2006.173.20:40:11.11#ibcon#about to read 3, iclass 10, count 2 2006.173.20:40:11.13#ibcon#read 3, iclass 10, count 2 2006.173.20:40:11.13#ibcon#about to read 4, iclass 10, count 2 2006.173.20:40:11.13#ibcon#read 4, iclass 10, count 2 2006.173.20:40:11.13#ibcon#about to read 5, iclass 10, count 2 2006.173.20:40:11.13#ibcon#read 5, iclass 10, count 2 2006.173.20:40:11.13#ibcon#about to read 6, iclass 10, count 2 2006.173.20:40:11.13#ibcon#read 6, iclass 10, count 2 2006.173.20:40:11.13#ibcon#end of sib2, iclass 10, count 2 2006.173.20:40:11.13#ibcon#*mode == 0, iclass 10, count 2 2006.173.20:40:11.13#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.20:40:11.13#ibcon#[27=AT04-04\r\n] 2006.173.20:40:11.13#ibcon#*before write, iclass 10, count 2 2006.173.20:40:11.13#ibcon#enter sib2, iclass 10, count 2 2006.173.20:40:11.13#ibcon#flushed, iclass 10, count 2 2006.173.20:40:11.13#ibcon#about to write, iclass 10, count 2 2006.173.20:40:11.13#ibcon#wrote, iclass 10, count 2 2006.173.20:40:11.13#ibcon#about to read 3, iclass 10, count 2 2006.173.20:40:11.16#ibcon#read 3, iclass 10, count 2 2006.173.20:40:11.16#ibcon#about to read 4, iclass 10, count 2 2006.173.20:40:11.16#ibcon#read 4, iclass 10, count 2 2006.173.20:40:11.16#ibcon#about to read 5, iclass 10, count 2 2006.173.20:40:11.16#ibcon#read 5, iclass 10, count 2 2006.173.20:40:11.16#ibcon#about to read 6, iclass 10, count 2 2006.173.20:40:11.16#ibcon#read 6, iclass 10, count 2 2006.173.20:40:11.16#ibcon#end of sib2, iclass 10, count 2 2006.173.20:40:11.16#ibcon#*after write, iclass 10, count 2 2006.173.20:40:11.16#ibcon#*before return 0, iclass 10, count 2 2006.173.20:40:11.16#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.20:40:11.16#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.20:40:11.16#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.20:40:11.16#ibcon#ireg 7 cls_cnt 0 2006.173.20:40:11.16#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.20:40:11.28#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.20:40:11.28#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.20:40:11.28#ibcon#enter wrdev, iclass 10, count 0 2006.173.20:40:11.28#ibcon#first serial, iclass 10, count 0 2006.173.20:40:11.28#ibcon#enter sib2, iclass 10, count 0 2006.173.20:40:11.28#ibcon#flushed, iclass 10, count 0 2006.173.20:40:11.28#ibcon#about to write, iclass 10, count 0 2006.173.20:40:11.28#ibcon#wrote, iclass 10, count 0 2006.173.20:40:11.28#ibcon#about to read 3, iclass 10, count 0 2006.173.20:40:11.30#ibcon#read 3, iclass 10, count 0 2006.173.20:40:11.30#ibcon#about to read 4, iclass 10, count 0 2006.173.20:40:11.30#ibcon#read 4, iclass 10, count 0 2006.173.20:40:11.30#ibcon#about to read 5, iclass 10, count 0 2006.173.20:40:11.30#ibcon#read 5, iclass 10, count 0 2006.173.20:40:11.30#ibcon#about to read 6, iclass 10, count 0 2006.173.20:40:11.30#ibcon#read 6, iclass 10, count 0 2006.173.20:40:11.30#ibcon#end of sib2, iclass 10, count 0 2006.173.20:40:11.30#ibcon#*mode == 0, iclass 10, count 0 2006.173.20:40:11.30#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.20:40:11.30#ibcon#[27=USB\r\n] 2006.173.20:40:11.30#ibcon#*before write, iclass 10, count 0 2006.173.20:40:11.30#ibcon#enter sib2, iclass 10, count 0 2006.173.20:40:11.30#ibcon#flushed, iclass 10, count 0 2006.173.20:40:11.30#ibcon#about to write, iclass 10, count 0 2006.173.20:40:11.30#ibcon#wrote, iclass 10, count 0 2006.173.20:40:11.30#ibcon#about to read 3, iclass 10, count 0 2006.173.20:40:11.33#ibcon#read 3, iclass 10, count 0 2006.173.20:40:11.33#ibcon#about to read 4, iclass 10, count 0 2006.173.20:40:11.33#ibcon#read 4, iclass 10, count 0 2006.173.20:40:11.33#ibcon#about to read 5, iclass 10, count 0 2006.173.20:40:11.33#ibcon#read 5, iclass 10, count 0 2006.173.20:40:11.33#ibcon#about to read 6, iclass 10, count 0 2006.173.20:40:11.33#ibcon#read 6, iclass 10, count 0 2006.173.20:40:11.33#ibcon#end of sib2, iclass 10, count 0 2006.173.20:40:11.33#ibcon#*after write, iclass 10, count 0 2006.173.20:40:11.33#ibcon#*before return 0, iclass 10, count 0 2006.173.20:40:11.33#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.20:40:11.33#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.20:40:11.33#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.20:40:11.33#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.20:40:11.33$vck44/vblo=5,709.99 2006.173.20:40:11.33#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.20:40:11.33#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.20:40:11.33#ibcon#ireg 17 cls_cnt 0 2006.173.20:40:11.33#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.20:40:11.33#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.20:40:11.33#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.20:40:11.33#ibcon#enter wrdev, iclass 12, count 0 2006.173.20:40:11.33#ibcon#first serial, iclass 12, count 0 2006.173.20:40:11.33#ibcon#enter sib2, iclass 12, count 0 2006.173.20:40:11.33#ibcon#flushed, iclass 12, count 0 2006.173.20:40:11.33#ibcon#about to write, iclass 12, count 0 2006.173.20:40:11.33#ibcon#wrote, iclass 12, count 0 2006.173.20:40:11.33#ibcon#about to read 3, iclass 12, count 0 2006.173.20:40:11.35#ibcon#read 3, iclass 12, count 0 2006.173.20:40:11.35#ibcon#about to read 4, iclass 12, count 0 2006.173.20:40:11.35#ibcon#read 4, iclass 12, count 0 2006.173.20:40:11.35#ibcon#about to read 5, iclass 12, count 0 2006.173.20:40:11.35#ibcon#read 5, iclass 12, count 0 2006.173.20:40:11.35#ibcon#about to read 6, iclass 12, count 0 2006.173.20:40:11.35#ibcon#read 6, iclass 12, count 0 2006.173.20:40:11.35#ibcon#end of sib2, iclass 12, count 0 2006.173.20:40:11.35#ibcon#*mode == 0, iclass 12, count 0 2006.173.20:40:11.35#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.20:40:11.35#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.20:40:11.35#ibcon#*before write, iclass 12, count 0 2006.173.20:40:11.35#ibcon#enter sib2, iclass 12, count 0 2006.173.20:40:11.35#ibcon#flushed, iclass 12, count 0 2006.173.20:40:11.35#ibcon#about to write, iclass 12, count 0 2006.173.20:40:11.35#ibcon#wrote, iclass 12, count 0 2006.173.20:40:11.35#ibcon#about to read 3, iclass 12, count 0 2006.173.20:40:11.39#ibcon#read 3, iclass 12, count 0 2006.173.20:40:11.39#ibcon#about to read 4, iclass 12, count 0 2006.173.20:40:11.39#ibcon#read 4, iclass 12, count 0 2006.173.20:40:11.39#ibcon#about to read 5, iclass 12, count 0 2006.173.20:40:11.39#ibcon#read 5, iclass 12, count 0 2006.173.20:40:11.39#ibcon#about to read 6, iclass 12, count 0 2006.173.20:40:11.39#ibcon#read 6, iclass 12, count 0 2006.173.20:40:11.39#ibcon#end of sib2, iclass 12, count 0 2006.173.20:40:11.39#ibcon#*after write, iclass 12, count 0 2006.173.20:40:11.39#ibcon#*before return 0, iclass 12, count 0 2006.173.20:40:11.39#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.20:40:11.39#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.20:40:11.39#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.20:40:11.39#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.20:40:11.39$vck44/vb=5,4 2006.173.20:40:11.39#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.20:40:11.39#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.20:40:11.39#ibcon#ireg 11 cls_cnt 2 2006.173.20:40:11.39#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.20:40:11.45#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.20:40:11.45#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.20:40:11.45#ibcon#enter wrdev, iclass 14, count 2 2006.173.20:40:11.45#ibcon#first serial, iclass 14, count 2 2006.173.20:40:11.45#ibcon#enter sib2, iclass 14, count 2 2006.173.20:40:11.45#ibcon#flushed, iclass 14, count 2 2006.173.20:40:11.45#ibcon#about to write, iclass 14, count 2 2006.173.20:40:11.45#ibcon#wrote, iclass 14, count 2 2006.173.20:40:11.45#ibcon#about to read 3, iclass 14, count 2 2006.173.20:40:11.47#ibcon#read 3, iclass 14, count 2 2006.173.20:40:11.47#ibcon#about to read 4, iclass 14, count 2 2006.173.20:40:11.47#ibcon#read 4, iclass 14, count 2 2006.173.20:40:11.47#ibcon#about to read 5, iclass 14, count 2 2006.173.20:40:11.47#ibcon#read 5, iclass 14, count 2 2006.173.20:40:11.47#ibcon#about to read 6, iclass 14, count 2 2006.173.20:40:11.47#ibcon#read 6, iclass 14, count 2 2006.173.20:40:11.47#ibcon#end of sib2, iclass 14, count 2 2006.173.20:40:11.47#ibcon#*mode == 0, iclass 14, count 2 2006.173.20:40:11.47#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.20:40:11.47#ibcon#[27=AT05-04\r\n] 2006.173.20:40:11.47#ibcon#*before write, iclass 14, count 2 2006.173.20:40:11.47#ibcon#enter sib2, iclass 14, count 2 2006.173.20:40:11.47#ibcon#flushed, iclass 14, count 2 2006.173.20:40:11.47#ibcon#about to write, iclass 14, count 2 2006.173.20:40:11.47#ibcon#wrote, iclass 14, count 2 2006.173.20:40:11.47#ibcon#about to read 3, iclass 14, count 2 2006.173.20:40:11.50#ibcon#read 3, iclass 14, count 2 2006.173.20:40:11.50#ibcon#about to read 4, iclass 14, count 2 2006.173.20:40:11.57#ibcon#read 4, iclass 14, count 2 2006.173.20:40:11.57#ibcon#about to read 5, iclass 14, count 2 2006.173.20:40:11.57#ibcon#read 5, iclass 14, count 2 2006.173.20:40:11.57#ibcon#about to read 6, iclass 14, count 2 2006.173.20:40:11.57#ibcon#read 6, iclass 14, count 2 2006.173.20:40:11.57#ibcon#end of sib2, iclass 14, count 2 2006.173.20:40:11.57#ibcon#*after write, iclass 14, count 2 2006.173.20:40:11.57#ibcon#*before return 0, iclass 14, count 2 2006.173.20:40:11.58#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.20:40:11.58#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.20:40:11.58#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.20:40:11.58#ibcon#ireg 7 cls_cnt 0 2006.173.20:40:11.58#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.20:40:11.69#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.20:40:11.69#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.20:40:11.69#ibcon#enter wrdev, iclass 14, count 0 2006.173.20:40:11.69#ibcon#first serial, iclass 14, count 0 2006.173.20:40:11.69#ibcon#enter sib2, iclass 14, count 0 2006.173.20:40:11.69#ibcon#flushed, iclass 14, count 0 2006.173.20:40:11.69#ibcon#about to write, iclass 14, count 0 2006.173.20:40:11.69#ibcon#wrote, iclass 14, count 0 2006.173.20:40:11.69#ibcon#about to read 3, iclass 14, count 0 2006.173.20:40:11.71#ibcon#read 3, iclass 14, count 0 2006.173.20:40:11.71#ibcon#about to read 4, iclass 14, count 0 2006.173.20:40:11.71#ibcon#read 4, iclass 14, count 0 2006.173.20:40:11.71#ibcon#about to read 5, iclass 14, count 0 2006.173.20:40:11.71#ibcon#read 5, iclass 14, count 0 2006.173.20:40:11.71#ibcon#about to read 6, iclass 14, count 0 2006.173.20:40:11.71#ibcon#read 6, iclass 14, count 0 2006.173.20:40:11.71#ibcon#end of sib2, iclass 14, count 0 2006.173.20:40:11.71#ibcon#*mode == 0, iclass 14, count 0 2006.173.20:40:11.71#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.20:40:11.71#ibcon#[27=USB\r\n] 2006.173.20:40:11.71#ibcon#*before write, iclass 14, count 0 2006.173.20:40:11.71#ibcon#enter sib2, iclass 14, count 0 2006.173.20:40:11.71#ibcon#flushed, iclass 14, count 0 2006.173.20:40:11.71#ibcon#about to write, iclass 14, count 0 2006.173.20:40:11.71#ibcon#wrote, iclass 14, count 0 2006.173.20:40:11.71#ibcon#about to read 3, iclass 14, count 0 2006.173.20:40:11.74#ibcon#read 3, iclass 14, count 0 2006.173.20:40:11.74#ibcon#about to read 4, iclass 14, count 0 2006.173.20:40:11.74#ibcon#read 4, iclass 14, count 0 2006.173.20:40:11.74#ibcon#about to read 5, iclass 14, count 0 2006.173.20:40:11.74#ibcon#read 5, iclass 14, count 0 2006.173.20:40:11.74#ibcon#about to read 6, iclass 14, count 0 2006.173.20:40:11.74#ibcon#read 6, iclass 14, count 0 2006.173.20:40:11.74#ibcon#end of sib2, iclass 14, count 0 2006.173.20:40:11.74#ibcon#*after write, iclass 14, count 0 2006.173.20:40:11.74#ibcon#*before return 0, iclass 14, count 0 2006.173.20:40:11.74#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.20:40:11.74#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.20:40:11.74#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.20:40:11.74#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.20:40:11.74$vck44/vblo=6,719.99 2006.173.20:40:11.74#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.20:40:11.74#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.20:40:11.74#ibcon#ireg 17 cls_cnt 0 2006.173.20:40:11.74#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.20:40:11.74#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.20:40:11.74#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.20:40:11.74#ibcon#enter wrdev, iclass 16, count 0 2006.173.20:40:11.74#ibcon#first serial, iclass 16, count 0 2006.173.20:40:11.74#ibcon#enter sib2, iclass 16, count 0 2006.173.20:40:11.74#ibcon#flushed, iclass 16, count 0 2006.173.20:40:11.74#ibcon#about to write, iclass 16, count 0 2006.173.20:40:11.74#ibcon#wrote, iclass 16, count 0 2006.173.20:40:11.74#ibcon#about to read 3, iclass 16, count 0 2006.173.20:40:11.76#ibcon#read 3, iclass 16, count 0 2006.173.20:40:11.76#ibcon#about to read 4, iclass 16, count 0 2006.173.20:40:11.76#ibcon#read 4, iclass 16, count 0 2006.173.20:40:11.76#ibcon#about to read 5, iclass 16, count 0 2006.173.20:40:11.76#ibcon#read 5, iclass 16, count 0 2006.173.20:40:11.76#ibcon#about to read 6, iclass 16, count 0 2006.173.20:40:11.76#ibcon#read 6, iclass 16, count 0 2006.173.20:40:11.76#ibcon#end of sib2, iclass 16, count 0 2006.173.20:40:11.76#ibcon#*mode == 0, iclass 16, count 0 2006.173.20:40:11.76#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.20:40:11.76#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.20:40:11.76#ibcon#*before write, iclass 16, count 0 2006.173.20:40:11.76#ibcon#enter sib2, iclass 16, count 0 2006.173.20:40:11.76#ibcon#flushed, iclass 16, count 0 2006.173.20:40:11.76#ibcon#about to write, iclass 16, count 0 2006.173.20:40:11.76#ibcon#wrote, iclass 16, count 0 2006.173.20:40:11.76#ibcon#about to read 3, iclass 16, count 0 2006.173.20:40:11.80#ibcon#read 3, iclass 16, count 0 2006.173.20:40:11.80#ibcon#about to read 4, iclass 16, count 0 2006.173.20:40:11.80#ibcon#read 4, iclass 16, count 0 2006.173.20:40:11.80#ibcon#about to read 5, iclass 16, count 0 2006.173.20:40:11.80#ibcon#read 5, iclass 16, count 0 2006.173.20:40:11.80#ibcon#about to read 6, iclass 16, count 0 2006.173.20:40:11.80#ibcon#read 6, iclass 16, count 0 2006.173.20:40:11.80#ibcon#end of sib2, iclass 16, count 0 2006.173.20:40:11.80#ibcon#*after write, iclass 16, count 0 2006.173.20:40:11.80#ibcon#*before return 0, iclass 16, count 0 2006.173.20:40:11.80#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.20:40:11.80#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.20:40:11.80#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.20:40:11.80#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.20:40:11.80$vck44/vb=6,4 2006.173.20:40:11.80#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.20:40:11.80#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.20:40:11.80#ibcon#ireg 11 cls_cnt 2 2006.173.20:40:11.80#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.20:40:11.86#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.20:40:11.86#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.20:40:11.86#ibcon#enter wrdev, iclass 18, count 2 2006.173.20:40:11.86#ibcon#first serial, iclass 18, count 2 2006.173.20:40:11.86#ibcon#enter sib2, iclass 18, count 2 2006.173.20:40:11.86#ibcon#flushed, iclass 18, count 2 2006.173.20:40:11.86#ibcon#about to write, iclass 18, count 2 2006.173.20:40:11.86#ibcon#wrote, iclass 18, count 2 2006.173.20:40:11.86#ibcon#about to read 3, iclass 18, count 2 2006.173.20:40:11.88#ibcon#read 3, iclass 18, count 2 2006.173.20:40:11.88#ibcon#about to read 4, iclass 18, count 2 2006.173.20:40:11.88#ibcon#read 4, iclass 18, count 2 2006.173.20:40:11.88#ibcon#about to read 5, iclass 18, count 2 2006.173.20:40:11.88#ibcon#read 5, iclass 18, count 2 2006.173.20:40:11.88#ibcon#about to read 6, iclass 18, count 2 2006.173.20:40:11.88#ibcon#read 6, iclass 18, count 2 2006.173.20:40:11.88#ibcon#end of sib2, iclass 18, count 2 2006.173.20:40:11.88#ibcon#*mode == 0, iclass 18, count 2 2006.173.20:40:11.88#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.20:40:11.88#ibcon#[27=AT06-04\r\n] 2006.173.20:40:11.88#ibcon#*before write, iclass 18, count 2 2006.173.20:40:11.88#ibcon#enter sib2, iclass 18, count 2 2006.173.20:40:11.88#ibcon#flushed, iclass 18, count 2 2006.173.20:40:11.88#ibcon#about to write, iclass 18, count 2 2006.173.20:40:11.88#ibcon#wrote, iclass 18, count 2 2006.173.20:40:11.88#ibcon#about to read 3, iclass 18, count 2 2006.173.20:40:11.91#ibcon#read 3, iclass 18, count 2 2006.173.20:40:11.91#ibcon#about to read 4, iclass 18, count 2 2006.173.20:40:11.91#ibcon#read 4, iclass 18, count 2 2006.173.20:40:11.91#ibcon#about to read 5, iclass 18, count 2 2006.173.20:40:11.91#ibcon#read 5, iclass 18, count 2 2006.173.20:40:11.91#ibcon#about to read 6, iclass 18, count 2 2006.173.20:40:11.91#ibcon#read 6, iclass 18, count 2 2006.173.20:40:11.91#ibcon#end of sib2, iclass 18, count 2 2006.173.20:40:11.91#ibcon#*after write, iclass 18, count 2 2006.173.20:40:11.91#ibcon#*before return 0, iclass 18, count 2 2006.173.20:40:11.91#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.20:40:11.91#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.20:40:11.91#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.20:40:11.91#ibcon#ireg 7 cls_cnt 0 2006.173.20:40:11.91#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.20:40:12.03#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.20:40:12.03#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.20:40:12.03#ibcon#enter wrdev, iclass 18, count 0 2006.173.20:40:12.03#ibcon#first serial, iclass 18, count 0 2006.173.20:40:12.03#ibcon#enter sib2, iclass 18, count 0 2006.173.20:40:12.03#ibcon#flushed, iclass 18, count 0 2006.173.20:40:12.03#ibcon#about to write, iclass 18, count 0 2006.173.20:40:12.03#ibcon#wrote, iclass 18, count 0 2006.173.20:40:12.03#ibcon#about to read 3, iclass 18, count 0 2006.173.20:40:12.05#ibcon#read 3, iclass 18, count 0 2006.173.20:40:12.05#ibcon#about to read 4, iclass 18, count 0 2006.173.20:40:12.05#ibcon#read 4, iclass 18, count 0 2006.173.20:40:12.05#ibcon#about to read 5, iclass 18, count 0 2006.173.20:40:12.05#ibcon#read 5, iclass 18, count 0 2006.173.20:40:12.05#ibcon#about to read 6, iclass 18, count 0 2006.173.20:40:12.05#ibcon#read 6, iclass 18, count 0 2006.173.20:40:12.05#ibcon#end of sib2, iclass 18, count 0 2006.173.20:40:12.05#ibcon#*mode == 0, iclass 18, count 0 2006.173.20:40:12.05#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.20:40:12.05#ibcon#[27=USB\r\n] 2006.173.20:40:12.05#ibcon#*before write, iclass 18, count 0 2006.173.20:40:12.05#ibcon#enter sib2, iclass 18, count 0 2006.173.20:40:12.05#ibcon#flushed, iclass 18, count 0 2006.173.20:40:12.05#ibcon#about to write, iclass 18, count 0 2006.173.20:40:12.05#ibcon#wrote, iclass 18, count 0 2006.173.20:40:12.05#ibcon#about to read 3, iclass 18, count 0 2006.173.20:40:12.08#ibcon#read 3, iclass 18, count 0 2006.173.20:40:12.08#ibcon#about to read 4, iclass 18, count 0 2006.173.20:40:12.08#ibcon#read 4, iclass 18, count 0 2006.173.20:40:12.08#ibcon#about to read 5, iclass 18, count 0 2006.173.20:40:12.08#ibcon#read 5, iclass 18, count 0 2006.173.20:40:12.08#ibcon#about to read 6, iclass 18, count 0 2006.173.20:40:12.08#ibcon#read 6, iclass 18, count 0 2006.173.20:40:12.08#ibcon#end of sib2, iclass 18, count 0 2006.173.20:40:12.08#ibcon#*after write, iclass 18, count 0 2006.173.20:40:12.08#ibcon#*before return 0, iclass 18, count 0 2006.173.20:40:12.08#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.20:40:12.08#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.20:40:12.08#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.20:40:12.08#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.20:40:12.08$vck44/vblo=7,734.99 2006.173.20:40:12.08#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.20:40:12.08#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.20:40:12.08#ibcon#ireg 17 cls_cnt 0 2006.173.20:40:12.08#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.20:40:12.08#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.20:40:12.08#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.20:40:12.08#ibcon#enter wrdev, iclass 20, count 0 2006.173.20:40:12.08#ibcon#first serial, iclass 20, count 0 2006.173.20:40:12.08#ibcon#enter sib2, iclass 20, count 0 2006.173.20:40:12.08#ibcon#flushed, iclass 20, count 0 2006.173.20:40:12.08#ibcon#about to write, iclass 20, count 0 2006.173.20:40:12.08#ibcon#wrote, iclass 20, count 0 2006.173.20:40:12.08#ibcon#about to read 3, iclass 20, count 0 2006.173.20:40:12.10#ibcon#read 3, iclass 20, count 0 2006.173.20:40:12.10#ibcon#about to read 4, iclass 20, count 0 2006.173.20:40:12.10#ibcon#read 4, iclass 20, count 0 2006.173.20:40:12.10#ibcon#about to read 5, iclass 20, count 0 2006.173.20:40:12.10#ibcon#read 5, iclass 20, count 0 2006.173.20:40:12.10#ibcon#about to read 6, iclass 20, count 0 2006.173.20:40:12.10#ibcon#read 6, iclass 20, count 0 2006.173.20:40:12.10#ibcon#end of sib2, iclass 20, count 0 2006.173.20:40:12.10#ibcon#*mode == 0, iclass 20, count 0 2006.173.20:40:12.10#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.20:40:12.10#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.20:40:12.10#ibcon#*before write, iclass 20, count 0 2006.173.20:40:12.10#ibcon#enter sib2, iclass 20, count 0 2006.173.20:40:12.10#ibcon#flushed, iclass 20, count 0 2006.173.20:40:12.10#ibcon#about to write, iclass 20, count 0 2006.173.20:40:12.10#ibcon#wrote, iclass 20, count 0 2006.173.20:40:12.10#ibcon#about to read 3, iclass 20, count 0 2006.173.20:40:12.14#ibcon#read 3, iclass 20, count 0 2006.173.20:40:12.14#ibcon#about to read 4, iclass 20, count 0 2006.173.20:40:12.14#ibcon#read 4, iclass 20, count 0 2006.173.20:40:12.14#ibcon#about to read 5, iclass 20, count 0 2006.173.20:40:12.14#ibcon#read 5, iclass 20, count 0 2006.173.20:40:12.14#ibcon#about to read 6, iclass 20, count 0 2006.173.20:40:12.14#ibcon#read 6, iclass 20, count 0 2006.173.20:40:12.14#ibcon#end of sib2, iclass 20, count 0 2006.173.20:40:12.14#ibcon#*after write, iclass 20, count 0 2006.173.20:40:12.14#ibcon#*before return 0, iclass 20, count 0 2006.173.20:40:12.14#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.20:40:12.14#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.20:40:12.14#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.20:40:12.14#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.20:40:12.14$vck44/vb=7,4 2006.173.20:40:12.14#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.20:40:12.14#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.20:40:12.14#ibcon#ireg 11 cls_cnt 2 2006.173.20:40:12.14#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.20:40:12.20#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.20:40:12.20#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.20:40:12.20#ibcon#enter wrdev, iclass 22, count 2 2006.173.20:40:12.20#ibcon#first serial, iclass 22, count 2 2006.173.20:40:12.20#ibcon#enter sib2, iclass 22, count 2 2006.173.20:40:12.20#ibcon#flushed, iclass 22, count 2 2006.173.20:40:12.20#ibcon#about to write, iclass 22, count 2 2006.173.20:40:12.20#ibcon#wrote, iclass 22, count 2 2006.173.20:40:12.20#ibcon#about to read 3, iclass 22, count 2 2006.173.20:40:12.22#ibcon#read 3, iclass 22, count 2 2006.173.20:40:12.22#ibcon#about to read 4, iclass 22, count 2 2006.173.20:40:12.22#ibcon#read 4, iclass 22, count 2 2006.173.20:40:12.22#ibcon#about to read 5, iclass 22, count 2 2006.173.20:40:12.22#ibcon#read 5, iclass 22, count 2 2006.173.20:40:12.22#ibcon#about to read 6, iclass 22, count 2 2006.173.20:40:12.22#ibcon#read 6, iclass 22, count 2 2006.173.20:40:12.22#ibcon#end of sib2, iclass 22, count 2 2006.173.20:40:12.22#ibcon#*mode == 0, iclass 22, count 2 2006.173.20:40:12.22#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.20:40:12.22#ibcon#[27=AT07-04\r\n] 2006.173.20:40:12.22#ibcon#*before write, iclass 22, count 2 2006.173.20:40:12.22#ibcon#enter sib2, iclass 22, count 2 2006.173.20:40:12.22#ibcon#flushed, iclass 22, count 2 2006.173.20:40:12.22#ibcon#about to write, iclass 22, count 2 2006.173.20:40:12.22#ibcon#wrote, iclass 22, count 2 2006.173.20:40:12.22#ibcon#about to read 3, iclass 22, count 2 2006.173.20:40:12.25#ibcon#read 3, iclass 22, count 2 2006.173.20:40:12.25#ibcon#about to read 4, iclass 22, count 2 2006.173.20:40:12.25#ibcon#read 4, iclass 22, count 2 2006.173.20:40:12.25#ibcon#about to read 5, iclass 22, count 2 2006.173.20:40:12.25#ibcon#read 5, iclass 22, count 2 2006.173.20:40:12.25#ibcon#about to read 6, iclass 22, count 2 2006.173.20:40:12.25#ibcon#read 6, iclass 22, count 2 2006.173.20:40:12.25#ibcon#end of sib2, iclass 22, count 2 2006.173.20:40:12.25#ibcon#*after write, iclass 22, count 2 2006.173.20:40:12.25#ibcon#*before return 0, iclass 22, count 2 2006.173.20:40:12.25#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.20:40:12.25#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.20:40:12.25#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.20:40:12.25#ibcon#ireg 7 cls_cnt 0 2006.173.20:40:12.25#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.20:40:12.37#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.20:40:12.37#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.20:40:12.37#ibcon#enter wrdev, iclass 22, count 0 2006.173.20:40:12.37#ibcon#first serial, iclass 22, count 0 2006.173.20:40:12.37#ibcon#enter sib2, iclass 22, count 0 2006.173.20:40:12.37#ibcon#flushed, iclass 22, count 0 2006.173.20:40:12.37#ibcon#about to write, iclass 22, count 0 2006.173.20:40:12.37#ibcon#wrote, iclass 22, count 0 2006.173.20:40:12.37#ibcon#about to read 3, iclass 22, count 0 2006.173.20:40:12.39#ibcon#read 3, iclass 22, count 0 2006.173.20:40:12.39#ibcon#about to read 4, iclass 22, count 0 2006.173.20:40:12.39#ibcon#read 4, iclass 22, count 0 2006.173.20:40:12.39#ibcon#about to read 5, iclass 22, count 0 2006.173.20:40:12.39#ibcon#read 5, iclass 22, count 0 2006.173.20:40:12.39#ibcon#about to read 6, iclass 22, count 0 2006.173.20:40:12.39#ibcon#read 6, iclass 22, count 0 2006.173.20:40:12.39#ibcon#end of sib2, iclass 22, count 0 2006.173.20:40:12.39#ibcon#*mode == 0, iclass 22, count 0 2006.173.20:40:12.39#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.20:40:12.39#ibcon#[27=USB\r\n] 2006.173.20:40:12.39#ibcon#*before write, iclass 22, count 0 2006.173.20:40:12.39#ibcon#enter sib2, iclass 22, count 0 2006.173.20:40:12.39#ibcon#flushed, iclass 22, count 0 2006.173.20:40:12.39#ibcon#about to write, iclass 22, count 0 2006.173.20:40:12.39#ibcon#wrote, iclass 22, count 0 2006.173.20:40:12.39#ibcon#about to read 3, iclass 22, count 0 2006.173.20:40:12.42#ibcon#read 3, iclass 22, count 0 2006.173.20:40:12.42#ibcon#about to read 4, iclass 22, count 0 2006.173.20:40:12.42#ibcon#read 4, iclass 22, count 0 2006.173.20:40:12.42#ibcon#about to read 5, iclass 22, count 0 2006.173.20:40:12.42#ibcon#read 5, iclass 22, count 0 2006.173.20:40:12.42#ibcon#about to read 6, iclass 22, count 0 2006.173.20:40:12.42#ibcon#read 6, iclass 22, count 0 2006.173.20:40:12.42#ibcon#end of sib2, iclass 22, count 0 2006.173.20:40:12.42#ibcon#*after write, iclass 22, count 0 2006.173.20:40:12.42#ibcon#*before return 0, iclass 22, count 0 2006.173.20:40:12.42#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.20:40:12.42#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.20:40:12.42#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.20:40:12.42#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.20:40:12.42$vck44/vblo=8,744.99 2006.173.20:40:12.42#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.20:40:12.42#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.20:40:12.42#ibcon#ireg 17 cls_cnt 0 2006.173.20:40:12.42#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.20:40:12.42#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.20:40:12.42#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.20:40:12.42#ibcon#enter wrdev, iclass 24, count 0 2006.173.20:40:12.42#ibcon#first serial, iclass 24, count 0 2006.173.20:40:12.42#ibcon#enter sib2, iclass 24, count 0 2006.173.20:40:12.42#ibcon#flushed, iclass 24, count 0 2006.173.20:40:12.42#ibcon#about to write, iclass 24, count 0 2006.173.20:40:12.42#ibcon#wrote, iclass 24, count 0 2006.173.20:40:12.42#ibcon#about to read 3, iclass 24, count 0 2006.173.20:40:12.44#ibcon#read 3, iclass 24, count 0 2006.173.20:40:12.44#ibcon#about to read 4, iclass 24, count 0 2006.173.20:40:12.44#ibcon#read 4, iclass 24, count 0 2006.173.20:40:12.44#ibcon#about to read 5, iclass 24, count 0 2006.173.20:40:12.44#ibcon#read 5, iclass 24, count 0 2006.173.20:40:12.44#ibcon#about to read 6, iclass 24, count 0 2006.173.20:40:12.44#ibcon#read 6, iclass 24, count 0 2006.173.20:40:12.44#ibcon#end of sib2, iclass 24, count 0 2006.173.20:40:12.44#ibcon#*mode == 0, iclass 24, count 0 2006.173.20:40:12.44#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.20:40:12.44#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.20:40:12.44#ibcon#*before write, iclass 24, count 0 2006.173.20:40:12.44#ibcon#enter sib2, iclass 24, count 0 2006.173.20:40:12.44#ibcon#flushed, iclass 24, count 0 2006.173.20:40:12.44#ibcon#about to write, iclass 24, count 0 2006.173.20:40:12.44#ibcon#wrote, iclass 24, count 0 2006.173.20:40:12.44#ibcon#about to read 3, iclass 24, count 0 2006.173.20:40:12.48#ibcon#read 3, iclass 24, count 0 2006.173.20:40:12.48#ibcon#about to read 4, iclass 24, count 0 2006.173.20:40:12.48#ibcon#read 4, iclass 24, count 0 2006.173.20:40:12.48#ibcon#about to read 5, iclass 24, count 0 2006.173.20:40:12.48#ibcon#read 5, iclass 24, count 0 2006.173.20:40:12.48#ibcon#about to read 6, iclass 24, count 0 2006.173.20:40:12.48#ibcon#read 6, iclass 24, count 0 2006.173.20:40:12.48#ibcon#end of sib2, iclass 24, count 0 2006.173.20:40:12.48#ibcon#*after write, iclass 24, count 0 2006.173.20:40:12.48#ibcon#*before return 0, iclass 24, count 0 2006.173.20:40:12.48#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.20:40:12.48#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.20:40:12.48#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.20:40:12.48#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.20:40:12.48$vck44/vb=8,4 2006.173.20:40:12.48#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.20:40:12.48#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.20:40:12.48#ibcon#ireg 11 cls_cnt 2 2006.173.20:40:12.48#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.20:40:12.54#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.20:40:12.54#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.20:40:12.54#ibcon#enter wrdev, iclass 26, count 2 2006.173.20:40:12.54#ibcon#first serial, iclass 26, count 2 2006.173.20:40:12.54#ibcon#enter sib2, iclass 26, count 2 2006.173.20:40:12.54#ibcon#flushed, iclass 26, count 2 2006.173.20:40:12.54#ibcon#about to write, iclass 26, count 2 2006.173.20:40:12.54#ibcon#wrote, iclass 26, count 2 2006.173.20:40:12.54#ibcon#about to read 3, iclass 26, count 2 2006.173.20:40:12.56#ibcon#read 3, iclass 26, count 2 2006.173.20:40:12.56#ibcon#about to read 4, iclass 26, count 2 2006.173.20:40:12.56#ibcon#read 4, iclass 26, count 2 2006.173.20:40:12.56#ibcon#about to read 5, iclass 26, count 2 2006.173.20:40:12.56#ibcon#read 5, iclass 26, count 2 2006.173.20:40:12.56#ibcon#about to read 6, iclass 26, count 2 2006.173.20:40:12.56#ibcon#read 6, iclass 26, count 2 2006.173.20:40:12.56#ibcon#end of sib2, iclass 26, count 2 2006.173.20:40:12.56#ibcon#*mode == 0, iclass 26, count 2 2006.173.20:40:12.56#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.20:40:12.56#ibcon#[27=AT08-04\r\n] 2006.173.20:40:12.56#ibcon#*before write, iclass 26, count 2 2006.173.20:40:12.56#ibcon#enter sib2, iclass 26, count 2 2006.173.20:40:12.56#ibcon#flushed, iclass 26, count 2 2006.173.20:40:12.56#ibcon#about to write, iclass 26, count 2 2006.173.20:40:12.56#ibcon#wrote, iclass 26, count 2 2006.173.20:40:12.56#ibcon#about to read 3, iclass 26, count 2 2006.173.20:40:12.59#ibcon#read 3, iclass 26, count 2 2006.173.20:40:12.59#ibcon#about to read 4, iclass 26, count 2 2006.173.20:40:12.59#ibcon#read 4, iclass 26, count 2 2006.173.20:40:12.59#ibcon#about to read 5, iclass 26, count 2 2006.173.20:40:12.59#ibcon#read 5, iclass 26, count 2 2006.173.20:40:12.59#ibcon#about to read 6, iclass 26, count 2 2006.173.20:40:12.59#ibcon#read 6, iclass 26, count 2 2006.173.20:40:12.59#ibcon#end of sib2, iclass 26, count 2 2006.173.20:40:12.59#ibcon#*after write, iclass 26, count 2 2006.173.20:40:12.59#ibcon#*before return 0, iclass 26, count 2 2006.173.20:40:12.59#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.20:40:12.59#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.20:40:12.59#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.20:40:12.59#ibcon#ireg 7 cls_cnt 0 2006.173.20:40:12.59#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.20:40:12.71#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.20:40:12.71#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.20:40:12.71#ibcon#enter wrdev, iclass 26, count 0 2006.173.20:40:12.71#ibcon#first serial, iclass 26, count 0 2006.173.20:40:12.71#ibcon#enter sib2, iclass 26, count 0 2006.173.20:40:12.71#ibcon#flushed, iclass 26, count 0 2006.173.20:40:12.71#ibcon#about to write, iclass 26, count 0 2006.173.20:40:12.71#ibcon#wrote, iclass 26, count 0 2006.173.20:40:12.71#ibcon#about to read 3, iclass 26, count 0 2006.173.20:40:12.73#ibcon#read 3, iclass 26, count 0 2006.173.20:40:12.73#ibcon#about to read 4, iclass 26, count 0 2006.173.20:40:12.73#ibcon#read 4, iclass 26, count 0 2006.173.20:40:12.73#ibcon#about to read 5, iclass 26, count 0 2006.173.20:40:12.73#ibcon#read 5, iclass 26, count 0 2006.173.20:40:12.73#ibcon#about to read 6, iclass 26, count 0 2006.173.20:40:12.73#ibcon#read 6, iclass 26, count 0 2006.173.20:40:12.73#ibcon#end of sib2, iclass 26, count 0 2006.173.20:40:12.73#ibcon#*mode == 0, iclass 26, count 0 2006.173.20:40:12.73#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.20:40:12.73#ibcon#[27=USB\r\n] 2006.173.20:40:12.73#ibcon#*before write, iclass 26, count 0 2006.173.20:40:12.73#ibcon#enter sib2, iclass 26, count 0 2006.173.20:40:12.73#ibcon#flushed, iclass 26, count 0 2006.173.20:40:12.73#ibcon#about to write, iclass 26, count 0 2006.173.20:40:12.73#ibcon#wrote, iclass 26, count 0 2006.173.20:40:12.73#ibcon#about to read 3, iclass 26, count 0 2006.173.20:40:12.76#ibcon#read 3, iclass 26, count 0 2006.173.20:40:12.76#ibcon#about to read 4, iclass 26, count 0 2006.173.20:40:12.76#ibcon#read 4, iclass 26, count 0 2006.173.20:40:12.76#ibcon#about to read 5, iclass 26, count 0 2006.173.20:40:12.76#ibcon#read 5, iclass 26, count 0 2006.173.20:40:12.76#ibcon#about to read 6, iclass 26, count 0 2006.173.20:40:12.76#ibcon#read 6, iclass 26, count 0 2006.173.20:40:12.76#ibcon#end of sib2, iclass 26, count 0 2006.173.20:40:12.76#ibcon#*after write, iclass 26, count 0 2006.173.20:40:12.76#ibcon#*before return 0, iclass 26, count 0 2006.173.20:40:12.76#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.20:40:12.76#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.20:40:12.76#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.20:40:12.76#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.20:40:12.76$vck44/vabw=wide 2006.173.20:40:12.76#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.20:40:12.76#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.20:40:12.76#ibcon#ireg 8 cls_cnt 0 2006.173.20:40:12.76#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.20:40:12.76#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.20:40:12.76#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.20:40:12.76#ibcon#enter wrdev, iclass 28, count 0 2006.173.20:40:12.76#ibcon#first serial, iclass 28, count 0 2006.173.20:40:12.76#ibcon#enter sib2, iclass 28, count 0 2006.173.20:40:12.76#ibcon#flushed, iclass 28, count 0 2006.173.20:40:12.76#ibcon#about to write, iclass 28, count 0 2006.173.20:40:12.76#ibcon#wrote, iclass 28, count 0 2006.173.20:40:12.76#ibcon#about to read 3, iclass 28, count 0 2006.173.20:40:12.78#ibcon#read 3, iclass 28, count 0 2006.173.20:40:12.78#ibcon#about to read 4, iclass 28, count 0 2006.173.20:40:12.78#ibcon#read 4, iclass 28, count 0 2006.173.20:40:12.78#ibcon#about to read 5, iclass 28, count 0 2006.173.20:40:12.78#ibcon#read 5, iclass 28, count 0 2006.173.20:40:12.78#ibcon#about to read 6, iclass 28, count 0 2006.173.20:40:12.78#ibcon#read 6, iclass 28, count 0 2006.173.20:40:12.78#ibcon#end of sib2, iclass 28, count 0 2006.173.20:40:12.78#ibcon#*mode == 0, iclass 28, count 0 2006.173.20:40:12.78#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.20:40:12.78#ibcon#[25=BW32\r\n] 2006.173.20:40:12.78#ibcon#*before write, iclass 28, count 0 2006.173.20:40:12.78#ibcon#enter sib2, iclass 28, count 0 2006.173.20:40:12.78#ibcon#flushed, iclass 28, count 0 2006.173.20:40:12.78#ibcon#about to write, iclass 28, count 0 2006.173.20:40:12.78#ibcon#wrote, iclass 28, count 0 2006.173.20:40:12.78#ibcon#about to read 3, iclass 28, count 0 2006.173.20:40:12.81#ibcon#read 3, iclass 28, count 0 2006.173.20:40:12.81#ibcon#about to read 4, iclass 28, count 0 2006.173.20:40:12.81#ibcon#read 4, iclass 28, count 0 2006.173.20:40:12.81#ibcon#about to read 5, iclass 28, count 0 2006.173.20:40:12.81#ibcon#read 5, iclass 28, count 0 2006.173.20:40:12.81#ibcon#about to read 6, iclass 28, count 0 2006.173.20:40:12.81#ibcon#read 6, iclass 28, count 0 2006.173.20:40:12.81#ibcon#end of sib2, iclass 28, count 0 2006.173.20:40:12.81#ibcon#*after write, iclass 28, count 0 2006.173.20:40:12.81#ibcon#*before return 0, iclass 28, count 0 2006.173.20:40:12.81#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.20:40:12.81#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.20:40:12.81#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.20:40:12.81#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.20:40:12.81$vck44/vbbw=wide 2006.173.20:40:12.81#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.20:40:12.81#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.20:40:12.81#ibcon#ireg 8 cls_cnt 0 2006.173.20:40:12.81#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.20:40:12.88#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.20:40:12.88#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.20:40:12.88#ibcon#enter wrdev, iclass 30, count 0 2006.173.20:40:12.88#ibcon#first serial, iclass 30, count 0 2006.173.20:40:12.88#ibcon#enter sib2, iclass 30, count 0 2006.173.20:40:12.88#ibcon#flushed, iclass 30, count 0 2006.173.20:40:12.88#ibcon#about to write, iclass 30, count 0 2006.173.20:40:12.88#ibcon#wrote, iclass 30, count 0 2006.173.20:40:12.88#ibcon#about to read 3, iclass 30, count 0 2006.173.20:40:12.90#ibcon#read 3, iclass 30, count 0 2006.173.20:40:12.90#ibcon#about to read 4, iclass 30, count 0 2006.173.20:40:12.90#ibcon#read 4, iclass 30, count 0 2006.173.20:40:12.90#ibcon#about to read 5, iclass 30, count 0 2006.173.20:40:12.90#ibcon#read 5, iclass 30, count 0 2006.173.20:40:12.90#ibcon#about to read 6, iclass 30, count 0 2006.173.20:40:12.90#ibcon#read 6, iclass 30, count 0 2006.173.20:40:12.90#ibcon#end of sib2, iclass 30, count 0 2006.173.20:40:12.90#ibcon#*mode == 0, iclass 30, count 0 2006.173.20:40:12.90#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.20:40:12.90#ibcon#[27=BW32\r\n] 2006.173.20:40:12.90#ibcon#*before write, iclass 30, count 0 2006.173.20:40:12.90#ibcon#enter sib2, iclass 30, count 0 2006.173.20:40:12.90#ibcon#flushed, iclass 30, count 0 2006.173.20:40:12.90#ibcon#about to write, iclass 30, count 0 2006.173.20:40:13.09#ibcon#wrote, iclass 30, count 0 2006.173.20:40:13.09#ibcon#about to read 3, iclass 30, count 0 2006.173.20:40:13.12#ibcon#read 3, iclass 30, count 0 2006.173.20:40:13.12#ibcon#about to read 4, iclass 30, count 0 2006.173.20:40:13.12#ibcon#read 4, iclass 30, count 0 2006.173.20:40:13.12#ibcon#about to read 5, iclass 30, count 0 2006.173.20:40:13.12#ibcon#read 5, iclass 30, count 0 2006.173.20:40:13.12#ibcon#about to read 6, iclass 30, count 0 2006.173.20:40:13.12#ibcon#read 6, iclass 30, count 0 2006.173.20:40:13.12#ibcon#end of sib2, iclass 30, count 0 2006.173.20:40:13.12#ibcon#*after write, iclass 30, count 0 2006.173.20:40:13.12#ibcon#*before return 0, iclass 30, count 0 2006.173.20:40:13.12#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.20:40:13.12#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.20:40:13.12#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.20:40:13.12#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.20:40:13.12$setupk4/ifdk4 2006.173.20:40:13.12$ifdk4/lo= 2006.173.20:40:13.12$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.20:40:13.12$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.20:40:13.12$ifdk4/patch= 2006.173.20:40:13.12$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.20:40:13.12$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.20:40:13.12$setupk4/!*+20s 2006.173.20:40:18.12#abcon#<5=/06 0.8 1.4 20.381001003.0\r\n> 2006.173.20:40:18.14#abcon#{5=INTERFACE CLEAR} 2006.173.20:40:18.20#abcon#[5=S1D000X0/0*\r\n] 2006.173.20:40:27.22$setupk4/"tpicd 2006.173.20:40:27.22$setupk4/echo=off 2006.173.20:40:27.22$setupk4/xlog=off 2006.173.20:40:27.22:!2006.173.20:49:46 2006.173.20:40:28.14#trakl#Source acquired 2006.173.20:40:29.14#flagr#flagr/antenna,acquired 2006.173.20:49:46.00:preob 2006.173.20:49:46.14/onsource/TRACKING 2006.173.20:49:46.14:!2006.173.20:49:56 2006.173.20:49:56.00:"tape 2006.173.20:49:56.00:"st=record 2006.173.20:49:56.00:data_valid=on 2006.173.20:49:56.00:midob 2006.173.20:49:56.14/onsource/TRACKING 2006.173.20:49:56.14/wx/20.77,1003.2,100 2006.173.20:49:56.24/cable/+6.5153E-03 2006.173.20:49:57.33/va/01,07,usb,yes,36,39 2006.173.20:49:57.33/va/02,06,usb,yes,36,37 2006.173.20:49:57.33/va/03,05,usb,yes,46,48 2006.173.20:49:57.33/va/04,06,usb,yes,37,39 2006.173.20:49:57.33/va/05,04,usb,yes,29,29 2006.173.20:49:57.33/va/06,03,usb,yes,40,40 2006.173.20:49:57.33/va/07,04,usb,yes,33,34 2006.173.20:49:57.33/va/08,04,usb,yes,28,33 2006.173.20:49:57.56/valo/01,524.99,yes,locked 2006.173.20:49:57.56/valo/02,534.99,yes,locked 2006.173.20:49:57.56/valo/03,564.99,yes,locked 2006.173.20:49:57.56/valo/04,624.99,yes,locked 2006.173.20:49:57.56/valo/05,734.99,yes,locked 2006.173.20:49:57.56/valo/06,814.99,yes,locked 2006.173.20:49:57.56/valo/07,864.99,yes,locked 2006.173.20:49:57.56/valo/08,884.99,yes,locked 2006.173.20:49:58.65/vb/01,04,usb,yes,29,27 2006.173.20:49:58.65/vb/02,04,usb,yes,32,32 2006.173.20:49:58.65/vb/03,04,usb,yes,29,32 2006.173.20:49:58.65/vb/04,04,usb,yes,33,32 2006.173.20:49:58.65/vb/05,04,usb,yes,26,28 2006.173.20:49:58.65/vb/06,04,usb,yes,30,26 2006.173.20:49:58.65/vb/07,04,usb,yes,30,30 2006.173.20:49:58.65/vb/08,04,usb,yes,28,31 2006.173.20:49:58.88/vblo/01,629.99,yes,locked 2006.173.20:49:58.88/vblo/02,634.99,yes,locked 2006.173.20:49:58.88/vblo/03,649.99,yes,locked 2006.173.20:49:58.88/vblo/04,679.99,yes,locked 2006.173.20:49:58.88/vblo/05,709.99,yes,locked 2006.173.20:49:58.88/vblo/06,719.99,yes,locked 2006.173.20:49:58.88/vblo/07,734.99,yes,locked 2006.173.20:49:58.88/vblo/08,744.99,yes,locked 2006.173.20:49:59.03/vabw/8 2006.173.20:49:59.18/vbbw/8 2006.173.20:49:59.27/xfe/off,on,15.2 2006.173.20:49:59.65/ifatt/23,28,28,28 2006.173.20:50:00.08/fmout-gps/S +3.85E-07 2006.173.20:50:00.12:!2006.173.20:50:46 2006.173.20:50:46.01:data_valid=off 2006.173.20:50:46.01:"et 2006.173.20:50:46.01:!+3s 2006.173.20:50:49.02:"tape 2006.173.20:50:49.02:postob 2006.173.20:50:49.08/cable/+6.5151E-03 2006.173.20:50:49.08/wx/20.77,1003.2,100 2006.173.20:50:50.08/fmout-gps/S +3.84E-07 2006.173.20:50:50.08:scan_name=173-2054,jd0606,270 2006.173.20:50:50.08:source=cta26,033930.94,-014635.8,2000.0,cw 2006.173.20:50:51.14#flagr#flagr/antenna,new-source 2006.173.20:50:51.14:checkk5 2006.173.20:50:51.56/chk_autoobs//k5ts1/ autoobs is running! 2006.173.20:50:51.97/chk_autoobs//k5ts2/ autoobs is running! 2006.173.20:50:52.37/chk_autoobs//k5ts3/ autoobs is running! 2006.173.20:50:52.77/chk_autoobs//k5ts4/ autoobs is running! 2006.173.20:50:53.17/chk_obsdata//k5ts1/T1732049??a.dat file size is correct (nominal:200MB, actual:196MB). 2006.173.20:50:53.58/chk_obsdata//k5ts2/T1732049??b.dat file size is correct (nominal:200MB, actual:196MB). 2006.173.20:50:53.98/chk_obsdata//k5ts3/T1732049??c.dat file size is correct (nominal:200MB, actual:196MB). 2006.173.20:50:54.38/chk_obsdata//k5ts4/T1732049??d.dat file size is correct (nominal:200MB, actual:196MB). 2006.173.20:50:55.10/k5log//k5ts1_log_newline 2006.173.20:50:55.80/k5log//k5ts2_log_newline 2006.173.20:50:56.51/k5log//k5ts3_log_newline 2006.173.20:50:57.22/k5log//k5ts4_log_newline 2006.173.20:50:57.24/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.20:50:57.24:setupk4=1 2006.173.20:50:57.24$setupk4/echo=on 2006.173.20:50:57.24$setupk4/pcalon 2006.173.20:50:57.24$pcalon/"no phase cal control is implemented here 2006.173.20:50:57.24$setupk4/"tpicd=stop 2006.173.20:50:57.24$setupk4/"rec=synch_on 2006.173.20:50:57.24$setupk4/"rec_mode=128 2006.173.20:50:57.24$setupk4/!* 2006.173.20:50:57.24$setupk4/recpk4 2006.173.20:50:57.24$recpk4/recpatch= 2006.173.20:50:57.24$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.20:50:57.24$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.20:50:57.24$setupk4/vck44 2006.173.20:50:57.24$vck44/valo=1,524.99 2006.173.20:50:57.24#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.20:50:57.24#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.20:50:57.24#ibcon#ireg 17 cls_cnt 0 2006.173.20:50:57.24#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.20:50:57.24#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.20:50:57.24#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.20:50:57.24#ibcon#enter wrdev, iclass 35, count 0 2006.173.20:50:57.24#ibcon#first serial, iclass 35, count 0 2006.173.20:50:57.24#ibcon#enter sib2, iclass 35, count 0 2006.173.20:50:57.24#ibcon#flushed, iclass 35, count 0 2006.173.20:50:57.24#ibcon#about to write, iclass 35, count 0 2006.173.20:50:57.24#ibcon#wrote, iclass 35, count 0 2006.173.20:50:57.24#ibcon#about to read 3, iclass 35, count 0 2006.173.20:50:57.26#ibcon#read 3, iclass 35, count 0 2006.173.20:50:57.26#ibcon#about to read 4, iclass 35, count 0 2006.173.20:50:57.26#ibcon#read 4, iclass 35, count 0 2006.173.20:50:57.26#ibcon#about to read 5, iclass 35, count 0 2006.173.20:50:57.26#ibcon#read 5, iclass 35, count 0 2006.173.20:50:57.26#ibcon#about to read 6, iclass 35, count 0 2006.173.20:50:57.26#ibcon#read 6, iclass 35, count 0 2006.173.20:50:57.26#ibcon#end of sib2, iclass 35, count 0 2006.173.20:50:57.26#ibcon#*mode == 0, iclass 35, count 0 2006.173.20:50:57.26#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.20:50:57.26#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.20:50:57.26#ibcon#*before write, iclass 35, count 0 2006.173.20:50:57.26#ibcon#enter sib2, iclass 35, count 0 2006.173.20:50:57.26#ibcon#flushed, iclass 35, count 0 2006.173.20:50:57.26#ibcon#about to write, iclass 35, count 0 2006.173.20:50:57.26#ibcon#wrote, iclass 35, count 0 2006.173.20:50:57.26#ibcon#about to read 3, iclass 35, count 0 2006.173.20:50:57.31#ibcon#read 3, iclass 35, count 0 2006.173.20:50:57.31#ibcon#about to read 4, iclass 35, count 0 2006.173.20:50:57.31#ibcon#read 4, iclass 35, count 0 2006.173.20:50:57.31#ibcon#about to read 5, iclass 35, count 0 2006.173.20:50:57.31#ibcon#read 5, iclass 35, count 0 2006.173.20:50:57.31#ibcon#about to read 6, iclass 35, count 0 2006.173.20:50:57.31#ibcon#read 6, iclass 35, count 0 2006.173.20:50:57.31#ibcon#end of sib2, iclass 35, count 0 2006.173.20:50:57.31#ibcon#*after write, iclass 35, count 0 2006.173.20:50:57.31#ibcon#*before return 0, iclass 35, count 0 2006.173.20:50:57.31#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.20:50:57.31#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.20:50:57.31#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.20:50:57.31#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.20:50:57.31$vck44/va=1,7 2006.173.20:50:57.31#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.173.20:50:57.31#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.173.20:50:57.31#ibcon#ireg 11 cls_cnt 2 2006.173.20:50:57.31#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.20:50:57.31#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.20:50:57.31#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.20:50:57.31#ibcon#enter wrdev, iclass 37, count 2 2006.173.20:50:57.31#ibcon#first serial, iclass 37, count 2 2006.173.20:50:57.31#ibcon#enter sib2, iclass 37, count 2 2006.173.20:50:57.31#ibcon#flushed, iclass 37, count 2 2006.173.20:50:57.31#ibcon#about to write, iclass 37, count 2 2006.173.20:50:57.31#ibcon#wrote, iclass 37, count 2 2006.173.20:50:57.31#ibcon#about to read 3, iclass 37, count 2 2006.173.20:50:57.33#ibcon#read 3, iclass 37, count 2 2006.173.20:50:57.33#ibcon#about to read 4, iclass 37, count 2 2006.173.20:50:57.33#ibcon#read 4, iclass 37, count 2 2006.173.20:50:57.33#ibcon#about to read 5, iclass 37, count 2 2006.173.20:50:57.33#ibcon#read 5, iclass 37, count 2 2006.173.20:50:57.33#ibcon#about to read 6, iclass 37, count 2 2006.173.20:50:57.33#ibcon#read 6, iclass 37, count 2 2006.173.20:50:57.33#ibcon#end of sib2, iclass 37, count 2 2006.173.20:50:57.33#ibcon#*mode == 0, iclass 37, count 2 2006.173.20:50:57.33#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.173.20:50:57.33#ibcon#[25=AT01-07\r\n] 2006.173.20:50:57.33#ibcon#*before write, iclass 37, count 2 2006.173.20:50:57.33#ibcon#enter sib2, iclass 37, count 2 2006.173.20:50:57.33#ibcon#flushed, iclass 37, count 2 2006.173.20:50:57.33#ibcon#about to write, iclass 37, count 2 2006.173.20:50:57.33#ibcon#wrote, iclass 37, count 2 2006.173.20:50:57.33#ibcon#about to read 3, iclass 37, count 2 2006.173.20:50:57.36#ibcon#read 3, iclass 37, count 2 2006.173.20:50:57.36#ibcon#about to read 4, iclass 37, count 2 2006.173.20:50:57.36#ibcon#read 4, iclass 37, count 2 2006.173.20:50:57.36#ibcon#about to read 5, iclass 37, count 2 2006.173.20:50:57.36#ibcon#read 5, iclass 37, count 2 2006.173.20:50:57.36#ibcon#about to read 6, iclass 37, count 2 2006.173.20:50:57.36#ibcon#read 6, iclass 37, count 2 2006.173.20:50:57.36#ibcon#end of sib2, iclass 37, count 2 2006.173.20:50:57.36#ibcon#*after write, iclass 37, count 2 2006.173.20:50:57.36#ibcon#*before return 0, iclass 37, count 2 2006.173.20:50:57.36#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.20:50:57.36#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.173.20:50:57.36#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.173.20:50:57.36#ibcon#ireg 7 cls_cnt 0 2006.173.20:50:57.36#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.20:50:57.48#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.20:50:57.48#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.20:50:57.48#ibcon#enter wrdev, iclass 37, count 0 2006.173.20:50:57.48#ibcon#first serial, iclass 37, count 0 2006.173.20:50:57.48#ibcon#enter sib2, iclass 37, count 0 2006.173.20:50:57.48#ibcon#flushed, iclass 37, count 0 2006.173.20:50:57.48#ibcon#about to write, iclass 37, count 0 2006.173.20:50:57.48#ibcon#wrote, iclass 37, count 0 2006.173.20:50:57.48#ibcon#about to read 3, iclass 37, count 0 2006.173.20:50:57.50#ibcon#read 3, iclass 37, count 0 2006.173.20:50:57.50#ibcon#about to read 4, iclass 37, count 0 2006.173.20:50:57.50#ibcon#read 4, iclass 37, count 0 2006.173.20:50:57.50#ibcon#about to read 5, iclass 37, count 0 2006.173.20:50:57.50#ibcon#read 5, iclass 37, count 0 2006.173.20:50:57.50#ibcon#about to read 6, iclass 37, count 0 2006.173.20:50:57.50#ibcon#read 6, iclass 37, count 0 2006.173.20:50:57.50#ibcon#end of sib2, iclass 37, count 0 2006.173.20:50:57.50#ibcon#*mode == 0, iclass 37, count 0 2006.173.20:50:57.50#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.20:50:57.50#ibcon#[25=USB\r\n] 2006.173.20:50:57.50#ibcon#*before write, iclass 37, count 0 2006.173.20:50:57.50#ibcon#enter sib2, iclass 37, count 0 2006.173.20:50:57.50#ibcon#flushed, iclass 37, count 0 2006.173.20:50:57.50#ibcon#about to write, iclass 37, count 0 2006.173.20:50:57.50#ibcon#wrote, iclass 37, count 0 2006.173.20:50:57.50#ibcon#about to read 3, iclass 37, count 0 2006.173.20:50:57.53#ibcon#read 3, iclass 37, count 0 2006.173.20:50:57.53#ibcon#about to read 4, iclass 37, count 0 2006.173.20:50:57.53#ibcon#read 4, iclass 37, count 0 2006.173.20:50:57.53#ibcon#about to read 5, iclass 37, count 0 2006.173.20:50:57.53#ibcon#read 5, iclass 37, count 0 2006.173.20:50:57.53#ibcon#about to read 6, iclass 37, count 0 2006.173.20:50:57.53#ibcon#read 6, iclass 37, count 0 2006.173.20:50:57.53#ibcon#end of sib2, iclass 37, count 0 2006.173.20:50:57.53#ibcon#*after write, iclass 37, count 0 2006.173.20:50:57.53#ibcon#*before return 0, iclass 37, count 0 2006.173.20:50:57.53#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.20:50:57.53#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.173.20:50:57.53#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.20:50:57.53#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.20:50:57.53$vck44/valo=2,534.99 2006.173.20:50:57.53#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.20:50:57.53#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.20:50:57.53#ibcon#ireg 17 cls_cnt 0 2006.173.20:50:57.53#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.20:50:57.53#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.20:50:57.53#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.20:50:57.53#ibcon#enter wrdev, iclass 39, count 0 2006.173.20:50:57.53#ibcon#first serial, iclass 39, count 0 2006.173.20:50:57.53#ibcon#enter sib2, iclass 39, count 0 2006.173.20:50:57.53#ibcon#flushed, iclass 39, count 0 2006.173.20:50:57.53#ibcon#about to write, iclass 39, count 0 2006.173.20:50:57.53#ibcon#wrote, iclass 39, count 0 2006.173.20:50:57.53#ibcon#about to read 3, iclass 39, count 0 2006.173.20:50:57.55#ibcon#read 3, iclass 39, count 0 2006.173.20:50:57.55#ibcon#about to read 4, iclass 39, count 0 2006.173.20:50:57.55#ibcon#read 4, iclass 39, count 0 2006.173.20:50:57.55#ibcon#about to read 5, iclass 39, count 0 2006.173.20:50:57.55#ibcon#read 5, iclass 39, count 0 2006.173.20:50:57.55#ibcon#about to read 6, iclass 39, count 0 2006.173.20:50:57.55#ibcon#read 6, iclass 39, count 0 2006.173.20:50:57.55#ibcon#end of sib2, iclass 39, count 0 2006.173.20:50:57.55#ibcon#*mode == 0, iclass 39, count 0 2006.173.20:50:57.55#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.20:50:57.55#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.20:50:57.55#ibcon#*before write, iclass 39, count 0 2006.173.20:50:57.55#ibcon#enter sib2, iclass 39, count 0 2006.173.20:50:57.55#ibcon#flushed, iclass 39, count 0 2006.173.20:50:57.55#ibcon#about to write, iclass 39, count 0 2006.173.20:50:57.55#ibcon#wrote, iclass 39, count 0 2006.173.20:50:57.55#ibcon#about to read 3, iclass 39, count 0 2006.173.20:50:57.59#ibcon#read 3, iclass 39, count 0 2006.173.20:50:57.59#ibcon#about to read 4, iclass 39, count 0 2006.173.20:50:57.59#ibcon#read 4, iclass 39, count 0 2006.173.20:50:57.59#ibcon#about to read 5, iclass 39, count 0 2006.173.20:50:57.59#ibcon#read 5, iclass 39, count 0 2006.173.20:50:57.59#ibcon#about to read 6, iclass 39, count 0 2006.173.20:50:57.59#ibcon#read 6, iclass 39, count 0 2006.173.20:50:57.59#ibcon#end of sib2, iclass 39, count 0 2006.173.20:50:57.59#ibcon#*after write, iclass 39, count 0 2006.173.20:50:57.59#ibcon#*before return 0, iclass 39, count 0 2006.173.20:50:57.59#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.20:50:57.59#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.20:50:57.59#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.20:50:57.59#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.20:50:57.59$vck44/va=2,6 2006.173.20:50:57.59#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.20:50:57.59#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.20:50:57.59#ibcon#ireg 11 cls_cnt 2 2006.173.20:50:57.59#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.20:50:57.65#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.20:50:57.65#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.20:50:57.65#ibcon#enter wrdev, iclass 3, count 2 2006.173.20:50:57.65#ibcon#first serial, iclass 3, count 2 2006.173.20:50:57.65#ibcon#enter sib2, iclass 3, count 2 2006.173.20:50:57.65#ibcon#flushed, iclass 3, count 2 2006.173.20:50:57.65#ibcon#about to write, iclass 3, count 2 2006.173.20:50:57.65#ibcon#wrote, iclass 3, count 2 2006.173.20:50:57.65#ibcon#about to read 3, iclass 3, count 2 2006.173.20:50:57.67#ibcon#read 3, iclass 3, count 2 2006.173.20:50:57.67#ibcon#about to read 4, iclass 3, count 2 2006.173.20:50:57.67#ibcon#read 4, iclass 3, count 2 2006.173.20:50:57.67#ibcon#about to read 5, iclass 3, count 2 2006.173.20:50:57.67#ibcon#read 5, iclass 3, count 2 2006.173.20:50:57.67#ibcon#about to read 6, iclass 3, count 2 2006.173.20:50:57.67#ibcon#read 6, iclass 3, count 2 2006.173.20:50:57.67#ibcon#end of sib2, iclass 3, count 2 2006.173.20:50:57.67#ibcon#*mode == 0, iclass 3, count 2 2006.173.20:50:57.67#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.20:50:57.67#ibcon#[25=AT02-06\r\n] 2006.173.20:50:57.67#ibcon#*before write, iclass 3, count 2 2006.173.20:50:57.67#ibcon#enter sib2, iclass 3, count 2 2006.173.20:50:57.67#ibcon#flushed, iclass 3, count 2 2006.173.20:50:57.67#ibcon#about to write, iclass 3, count 2 2006.173.20:50:57.67#ibcon#wrote, iclass 3, count 2 2006.173.20:50:57.67#ibcon#about to read 3, iclass 3, count 2 2006.173.20:50:57.70#ibcon#read 3, iclass 3, count 2 2006.173.20:50:57.70#ibcon#about to read 4, iclass 3, count 2 2006.173.20:50:57.70#ibcon#read 4, iclass 3, count 2 2006.173.20:50:57.70#ibcon#about to read 5, iclass 3, count 2 2006.173.20:50:57.70#ibcon#read 5, iclass 3, count 2 2006.173.20:50:57.70#ibcon#about to read 6, iclass 3, count 2 2006.173.20:50:57.70#ibcon#read 6, iclass 3, count 2 2006.173.20:50:57.70#ibcon#end of sib2, iclass 3, count 2 2006.173.20:50:57.70#ibcon#*after write, iclass 3, count 2 2006.173.20:50:57.70#ibcon#*before return 0, iclass 3, count 2 2006.173.20:50:57.70#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.20:50:57.70#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.20:50:57.70#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.20:50:57.70#ibcon#ireg 7 cls_cnt 0 2006.173.20:50:57.70#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.20:50:57.82#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.20:50:57.82#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.20:50:57.82#ibcon#enter wrdev, iclass 3, count 0 2006.173.20:50:57.82#ibcon#first serial, iclass 3, count 0 2006.173.20:50:57.82#ibcon#enter sib2, iclass 3, count 0 2006.173.20:50:57.82#ibcon#flushed, iclass 3, count 0 2006.173.20:50:57.82#ibcon#about to write, iclass 3, count 0 2006.173.20:50:57.82#ibcon#wrote, iclass 3, count 0 2006.173.20:50:57.82#ibcon#about to read 3, iclass 3, count 0 2006.173.20:50:57.84#ibcon#read 3, iclass 3, count 0 2006.173.20:50:57.84#ibcon#about to read 4, iclass 3, count 0 2006.173.20:50:57.84#ibcon#read 4, iclass 3, count 0 2006.173.20:50:57.84#ibcon#about to read 5, iclass 3, count 0 2006.173.20:50:57.84#ibcon#read 5, iclass 3, count 0 2006.173.20:50:57.84#ibcon#about to read 6, iclass 3, count 0 2006.173.20:50:57.84#ibcon#read 6, iclass 3, count 0 2006.173.20:50:57.84#ibcon#end of sib2, iclass 3, count 0 2006.173.20:50:57.84#ibcon#*mode == 0, iclass 3, count 0 2006.173.20:50:57.84#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.20:50:57.84#ibcon#[25=USB\r\n] 2006.173.20:50:57.84#ibcon#*before write, iclass 3, count 0 2006.173.20:50:57.84#ibcon#enter sib2, iclass 3, count 0 2006.173.20:50:57.84#ibcon#flushed, iclass 3, count 0 2006.173.20:50:57.84#ibcon#about to write, iclass 3, count 0 2006.173.20:50:57.84#ibcon#wrote, iclass 3, count 0 2006.173.20:50:57.84#ibcon#about to read 3, iclass 3, count 0 2006.173.20:50:57.87#ibcon#read 3, iclass 3, count 0 2006.173.20:50:57.87#ibcon#about to read 4, iclass 3, count 0 2006.173.20:50:57.87#ibcon#read 4, iclass 3, count 0 2006.173.20:50:57.87#ibcon#about to read 5, iclass 3, count 0 2006.173.20:50:57.87#ibcon#read 5, iclass 3, count 0 2006.173.20:50:57.87#ibcon#about to read 6, iclass 3, count 0 2006.173.20:50:57.87#ibcon#read 6, iclass 3, count 0 2006.173.20:50:57.87#ibcon#end of sib2, iclass 3, count 0 2006.173.20:50:57.87#ibcon#*after write, iclass 3, count 0 2006.173.20:50:57.87#ibcon#*before return 0, iclass 3, count 0 2006.173.20:50:57.87#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.20:50:57.87#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.20:50:57.87#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.20:50:57.87#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.20:50:57.87$vck44/valo=3,564.99 2006.173.20:50:57.87#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.20:50:57.87#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.20:50:57.87#ibcon#ireg 17 cls_cnt 0 2006.173.20:50:57.87#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.20:50:57.87#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.20:50:57.87#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.20:50:57.87#ibcon#enter wrdev, iclass 5, count 0 2006.173.20:50:57.87#ibcon#first serial, iclass 5, count 0 2006.173.20:50:57.87#ibcon#enter sib2, iclass 5, count 0 2006.173.20:50:57.87#ibcon#flushed, iclass 5, count 0 2006.173.20:50:57.87#ibcon#about to write, iclass 5, count 0 2006.173.20:50:57.87#ibcon#wrote, iclass 5, count 0 2006.173.20:50:57.87#ibcon#about to read 3, iclass 5, count 0 2006.173.20:50:57.89#ibcon#read 3, iclass 5, count 0 2006.173.20:50:57.89#ibcon#about to read 4, iclass 5, count 0 2006.173.20:50:57.89#ibcon#read 4, iclass 5, count 0 2006.173.20:50:57.89#ibcon#about to read 5, iclass 5, count 0 2006.173.20:50:57.89#ibcon#read 5, iclass 5, count 0 2006.173.20:50:57.89#ibcon#about to read 6, iclass 5, count 0 2006.173.20:50:57.89#ibcon#read 6, iclass 5, count 0 2006.173.20:50:57.89#ibcon#end of sib2, iclass 5, count 0 2006.173.20:50:57.89#ibcon#*mode == 0, iclass 5, count 0 2006.173.20:50:57.89#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.20:50:57.89#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.20:50:57.89#ibcon#*before write, iclass 5, count 0 2006.173.20:50:57.89#ibcon#enter sib2, iclass 5, count 0 2006.173.20:50:57.89#ibcon#flushed, iclass 5, count 0 2006.173.20:50:57.89#ibcon#about to write, iclass 5, count 0 2006.173.20:50:57.89#ibcon#wrote, iclass 5, count 0 2006.173.20:50:57.89#ibcon#about to read 3, iclass 5, count 0 2006.173.20:50:57.93#ibcon#read 3, iclass 5, count 0 2006.173.20:50:57.93#ibcon#about to read 4, iclass 5, count 0 2006.173.20:50:57.93#ibcon#read 4, iclass 5, count 0 2006.173.20:50:57.93#ibcon#about to read 5, iclass 5, count 0 2006.173.20:50:57.93#ibcon#read 5, iclass 5, count 0 2006.173.20:50:57.93#ibcon#about to read 6, iclass 5, count 0 2006.173.20:50:57.93#ibcon#read 6, iclass 5, count 0 2006.173.20:50:57.93#ibcon#end of sib2, iclass 5, count 0 2006.173.20:50:57.93#ibcon#*after write, iclass 5, count 0 2006.173.20:50:57.93#ibcon#*before return 0, iclass 5, count 0 2006.173.20:50:57.93#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.20:50:57.93#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.20:50:57.93#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.20:50:57.93#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.20:50:57.93$vck44/va=3,5 2006.173.20:50:57.93#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.173.20:50:57.93#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.173.20:50:57.93#ibcon#ireg 11 cls_cnt 2 2006.173.20:50:57.93#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.20:50:57.99#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.20:50:57.99#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.20:50:57.99#ibcon#enter wrdev, iclass 7, count 2 2006.173.20:50:57.99#ibcon#first serial, iclass 7, count 2 2006.173.20:50:57.99#ibcon#enter sib2, iclass 7, count 2 2006.173.20:50:57.99#ibcon#flushed, iclass 7, count 2 2006.173.20:50:57.99#ibcon#about to write, iclass 7, count 2 2006.173.20:50:57.99#ibcon#wrote, iclass 7, count 2 2006.173.20:50:57.99#ibcon#about to read 3, iclass 7, count 2 2006.173.20:50:58.01#ibcon#read 3, iclass 7, count 2 2006.173.20:50:58.01#ibcon#about to read 4, iclass 7, count 2 2006.173.20:50:58.01#ibcon#read 4, iclass 7, count 2 2006.173.20:50:58.01#ibcon#about to read 5, iclass 7, count 2 2006.173.20:50:58.01#ibcon#read 5, iclass 7, count 2 2006.173.20:50:58.01#ibcon#about to read 6, iclass 7, count 2 2006.173.20:50:58.01#ibcon#read 6, iclass 7, count 2 2006.173.20:50:58.01#ibcon#end of sib2, iclass 7, count 2 2006.173.20:50:58.01#ibcon#*mode == 0, iclass 7, count 2 2006.173.20:50:58.01#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.173.20:50:58.01#ibcon#[25=AT03-05\r\n] 2006.173.20:50:58.01#ibcon#*before write, iclass 7, count 2 2006.173.20:50:58.01#ibcon#enter sib2, iclass 7, count 2 2006.173.20:50:58.01#ibcon#flushed, iclass 7, count 2 2006.173.20:50:58.01#ibcon#about to write, iclass 7, count 2 2006.173.20:50:58.01#ibcon#wrote, iclass 7, count 2 2006.173.20:50:58.01#ibcon#about to read 3, iclass 7, count 2 2006.173.20:50:58.04#ibcon#read 3, iclass 7, count 2 2006.173.20:50:58.04#ibcon#about to read 4, iclass 7, count 2 2006.173.20:50:58.04#ibcon#read 4, iclass 7, count 2 2006.173.20:50:58.04#ibcon#about to read 5, iclass 7, count 2 2006.173.20:50:58.04#ibcon#read 5, iclass 7, count 2 2006.173.20:50:58.04#ibcon#about to read 6, iclass 7, count 2 2006.173.20:50:58.04#ibcon#read 6, iclass 7, count 2 2006.173.20:50:58.04#ibcon#end of sib2, iclass 7, count 2 2006.173.20:50:58.04#ibcon#*after write, iclass 7, count 2 2006.173.20:50:58.04#ibcon#*before return 0, iclass 7, count 2 2006.173.20:50:58.04#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.20:50:58.04#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.173.20:50:58.04#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.173.20:50:58.04#ibcon#ireg 7 cls_cnt 0 2006.173.20:50:58.04#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.20:50:58.16#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.20:50:58.16#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.20:50:58.16#ibcon#enter wrdev, iclass 7, count 0 2006.173.20:50:58.16#ibcon#first serial, iclass 7, count 0 2006.173.20:50:58.16#ibcon#enter sib2, iclass 7, count 0 2006.173.20:50:58.16#ibcon#flushed, iclass 7, count 0 2006.173.20:50:58.16#ibcon#about to write, iclass 7, count 0 2006.173.20:50:58.16#ibcon#wrote, iclass 7, count 0 2006.173.20:50:58.16#ibcon#about to read 3, iclass 7, count 0 2006.173.20:50:58.18#ibcon#read 3, iclass 7, count 0 2006.173.20:50:58.18#ibcon#about to read 4, iclass 7, count 0 2006.173.20:50:58.18#ibcon#read 4, iclass 7, count 0 2006.173.20:50:58.18#ibcon#about to read 5, iclass 7, count 0 2006.173.20:50:58.18#ibcon#read 5, iclass 7, count 0 2006.173.20:50:58.18#ibcon#about to read 6, iclass 7, count 0 2006.173.20:50:58.18#ibcon#read 6, iclass 7, count 0 2006.173.20:50:58.18#ibcon#end of sib2, iclass 7, count 0 2006.173.20:50:58.18#ibcon#*mode == 0, iclass 7, count 0 2006.173.20:50:58.18#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.20:50:58.18#ibcon#[25=USB\r\n] 2006.173.20:50:58.18#ibcon#*before write, iclass 7, count 0 2006.173.20:50:58.18#ibcon#enter sib2, iclass 7, count 0 2006.173.20:50:58.18#ibcon#flushed, iclass 7, count 0 2006.173.20:50:58.18#ibcon#about to write, iclass 7, count 0 2006.173.20:50:58.18#ibcon#wrote, iclass 7, count 0 2006.173.20:50:58.18#ibcon#about to read 3, iclass 7, count 0 2006.173.20:50:58.21#ibcon#read 3, iclass 7, count 0 2006.173.20:50:58.21#ibcon#about to read 4, iclass 7, count 0 2006.173.20:50:58.21#ibcon#read 4, iclass 7, count 0 2006.173.20:50:58.21#ibcon#about to read 5, iclass 7, count 0 2006.173.20:50:58.21#ibcon#read 5, iclass 7, count 0 2006.173.20:50:58.21#ibcon#about to read 6, iclass 7, count 0 2006.173.20:50:58.21#ibcon#read 6, iclass 7, count 0 2006.173.20:50:58.21#ibcon#end of sib2, iclass 7, count 0 2006.173.20:50:58.21#ibcon#*after write, iclass 7, count 0 2006.173.20:50:58.21#ibcon#*before return 0, iclass 7, count 0 2006.173.20:50:58.21#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.20:50:58.21#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.173.20:50:58.21#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.20:50:58.21#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.20:50:58.21$vck44/valo=4,624.99 2006.173.20:50:58.21#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.20:50:58.21#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.20:50:58.21#ibcon#ireg 17 cls_cnt 0 2006.173.20:50:58.21#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.20:50:58.21#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.20:50:58.21#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.20:50:58.21#ibcon#enter wrdev, iclass 11, count 0 2006.173.20:50:58.21#ibcon#first serial, iclass 11, count 0 2006.173.20:50:58.21#ibcon#enter sib2, iclass 11, count 0 2006.173.20:50:58.21#ibcon#flushed, iclass 11, count 0 2006.173.20:50:58.21#ibcon#about to write, iclass 11, count 0 2006.173.20:50:58.21#ibcon#wrote, iclass 11, count 0 2006.173.20:50:58.21#ibcon#about to read 3, iclass 11, count 0 2006.173.20:50:58.23#ibcon#read 3, iclass 11, count 0 2006.173.20:50:58.23#ibcon#about to read 4, iclass 11, count 0 2006.173.20:50:58.23#ibcon#read 4, iclass 11, count 0 2006.173.20:50:58.23#ibcon#about to read 5, iclass 11, count 0 2006.173.20:50:58.23#ibcon#read 5, iclass 11, count 0 2006.173.20:50:58.23#ibcon#about to read 6, iclass 11, count 0 2006.173.20:50:58.23#ibcon#read 6, iclass 11, count 0 2006.173.20:50:58.23#ibcon#end of sib2, iclass 11, count 0 2006.173.20:50:58.23#ibcon#*mode == 0, iclass 11, count 0 2006.173.20:50:58.23#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.20:50:58.23#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.20:50:58.23#ibcon#*before write, iclass 11, count 0 2006.173.20:50:58.23#ibcon#enter sib2, iclass 11, count 0 2006.173.20:50:58.23#ibcon#flushed, iclass 11, count 0 2006.173.20:50:58.23#ibcon#about to write, iclass 11, count 0 2006.173.20:50:58.23#ibcon#wrote, iclass 11, count 0 2006.173.20:50:58.23#ibcon#about to read 3, iclass 11, count 0 2006.173.20:50:58.27#ibcon#read 3, iclass 11, count 0 2006.173.20:50:58.27#ibcon#about to read 4, iclass 11, count 0 2006.173.20:50:58.27#ibcon#read 4, iclass 11, count 0 2006.173.20:50:58.27#ibcon#about to read 5, iclass 11, count 0 2006.173.20:50:58.27#ibcon#read 5, iclass 11, count 0 2006.173.20:50:58.27#ibcon#about to read 6, iclass 11, count 0 2006.173.20:50:58.27#ibcon#read 6, iclass 11, count 0 2006.173.20:50:58.27#ibcon#end of sib2, iclass 11, count 0 2006.173.20:50:58.27#ibcon#*after write, iclass 11, count 0 2006.173.20:50:58.27#ibcon#*before return 0, iclass 11, count 0 2006.173.20:50:58.27#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.20:50:58.27#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.20:50:58.27#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.20:50:58.27#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.20:50:58.27$vck44/va=4,6 2006.173.20:50:58.27#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.173.20:50:58.27#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.173.20:50:58.27#ibcon#ireg 11 cls_cnt 2 2006.173.20:50:58.27#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.20:50:58.33#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.20:50:58.33#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.20:50:58.33#ibcon#enter wrdev, iclass 13, count 2 2006.173.20:50:58.33#ibcon#first serial, iclass 13, count 2 2006.173.20:50:58.33#ibcon#enter sib2, iclass 13, count 2 2006.173.20:50:58.33#ibcon#flushed, iclass 13, count 2 2006.173.20:50:58.33#ibcon#about to write, iclass 13, count 2 2006.173.20:50:58.33#ibcon#wrote, iclass 13, count 2 2006.173.20:50:58.33#ibcon#about to read 3, iclass 13, count 2 2006.173.20:50:58.35#ibcon#read 3, iclass 13, count 2 2006.173.20:50:58.35#ibcon#about to read 4, iclass 13, count 2 2006.173.20:50:58.35#ibcon#read 4, iclass 13, count 2 2006.173.20:50:58.35#ibcon#about to read 5, iclass 13, count 2 2006.173.20:50:58.35#ibcon#read 5, iclass 13, count 2 2006.173.20:50:58.35#ibcon#about to read 6, iclass 13, count 2 2006.173.20:50:58.35#ibcon#read 6, iclass 13, count 2 2006.173.20:50:58.35#ibcon#end of sib2, iclass 13, count 2 2006.173.20:50:58.35#ibcon#*mode == 0, iclass 13, count 2 2006.173.20:50:58.35#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.173.20:50:58.35#ibcon#[25=AT04-06\r\n] 2006.173.20:50:58.35#ibcon#*before write, iclass 13, count 2 2006.173.20:50:58.35#ibcon#enter sib2, iclass 13, count 2 2006.173.20:50:58.35#ibcon#flushed, iclass 13, count 2 2006.173.20:50:58.35#ibcon#about to write, iclass 13, count 2 2006.173.20:50:58.35#ibcon#wrote, iclass 13, count 2 2006.173.20:50:58.35#ibcon#about to read 3, iclass 13, count 2 2006.173.20:50:58.38#ibcon#read 3, iclass 13, count 2 2006.173.20:50:58.38#ibcon#about to read 4, iclass 13, count 2 2006.173.20:50:58.38#ibcon#read 4, iclass 13, count 2 2006.173.20:50:58.38#ibcon#about to read 5, iclass 13, count 2 2006.173.20:50:58.38#ibcon#read 5, iclass 13, count 2 2006.173.20:50:58.38#ibcon#about to read 6, iclass 13, count 2 2006.173.20:50:58.38#ibcon#read 6, iclass 13, count 2 2006.173.20:50:58.38#ibcon#end of sib2, iclass 13, count 2 2006.173.20:50:58.38#ibcon#*after write, iclass 13, count 2 2006.173.20:50:58.38#ibcon#*before return 0, iclass 13, count 2 2006.173.20:50:58.38#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.20:50:58.38#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.173.20:50:58.38#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.173.20:50:58.38#ibcon#ireg 7 cls_cnt 0 2006.173.20:50:58.38#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.20:50:58.50#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.20:50:58.50#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.20:50:58.50#ibcon#enter wrdev, iclass 13, count 0 2006.173.20:50:58.50#ibcon#first serial, iclass 13, count 0 2006.173.20:50:58.50#ibcon#enter sib2, iclass 13, count 0 2006.173.20:50:58.50#ibcon#flushed, iclass 13, count 0 2006.173.20:50:58.50#ibcon#about to write, iclass 13, count 0 2006.173.20:50:58.50#ibcon#wrote, iclass 13, count 0 2006.173.20:50:58.50#ibcon#about to read 3, iclass 13, count 0 2006.173.20:50:58.52#ibcon#read 3, iclass 13, count 0 2006.173.20:50:58.52#ibcon#about to read 4, iclass 13, count 0 2006.173.20:50:58.52#ibcon#read 4, iclass 13, count 0 2006.173.20:50:58.52#ibcon#about to read 5, iclass 13, count 0 2006.173.20:50:58.52#ibcon#read 5, iclass 13, count 0 2006.173.20:50:58.52#ibcon#about to read 6, iclass 13, count 0 2006.173.20:50:58.52#ibcon#read 6, iclass 13, count 0 2006.173.20:50:58.52#ibcon#end of sib2, iclass 13, count 0 2006.173.20:50:58.52#ibcon#*mode == 0, iclass 13, count 0 2006.173.20:50:58.52#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.20:50:58.52#ibcon#[25=USB\r\n] 2006.173.20:50:58.52#ibcon#*before write, iclass 13, count 0 2006.173.20:50:58.52#ibcon#enter sib2, iclass 13, count 0 2006.173.20:50:58.52#ibcon#flushed, iclass 13, count 0 2006.173.20:50:58.52#ibcon#about to write, iclass 13, count 0 2006.173.20:50:58.52#ibcon#wrote, iclass 13, count 0 2006.173.20:50:58.52#ibcon#about to read 3, iclass 13, count 0 2006.173.20:50:58.55#ibcon#read 3, iclass 13, count 0 2006.173.20:50:58.55#ibcon#about to read 4, iclass 13, count 0 2006.173.20:50:58.55#ibcon#read 4, iclass 13, count 0 2006.173.20:50:58.55#ibcon#about to read 5, iclass 13, count 0 2006.173.20:50:58.55#ibcon#read 5, iclass 13, count 0 2006.173.20:50:58.55#ibcon#about to read 6, iclass 13, count 0 2006.173.20:50:58.55#ibcon#read 6, iclass 13, count 0 2006.173.20:50:58.55#ibcon#end of sib2, iclass 13, count 0 2006.173.20:50:58.55#ibcon#*after write, iclass 13, count 0 2006.173.20:50:58.55#ibcon#*before return 0, iclass 13, count 0 2006.173.20:50:58.55#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.20:50:58.55#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.173.20:50:58.55#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.20:50:58.55#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.20:50:58.55$vck44/valo=5,734.99 2006.173.20:50:58.55#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.20:50:58.55#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.20:50:58.55#ibcon#ireg 17 cls_cnt 0 2006.173.20:50:58.55#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.20:50:58.55#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.20:50:58.55#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.20:50:58.55#ibcon#enter wrdev, iclass 15, count 0 2006.173.20:50:58.55#ibcon#first serial, iclass 15, count 0 2006.173.20:50:58.55#ibcon#enter sib2, iclass 15, count 0 2006.173.20:50:58.55#ibcon#flushed, iclass 15, count 0 2006.173.20:50:58.55#ibcon#about to write, iclass 15, count 0 2006.173.20:50:58.55#ibcon#wrote, iclass 15, count 0 2006.173.20:50:58.55#ibcon#about to read 3, iclass 15, count 0 2006.173.20:50:58.57#ibcon#read 3, iclass 15, count 0 2006.173.20:50:58.57#ibcon#about to read 4, iclass 15, count 0 2006.173.20:50:58.57#ibcon#read 4, iclass 15, count 0 2006.173.20:50:58.57#ibcon#about to read 5, iclass 15, count 0 2006.173.20:50:58.57#ibcon#read 5, iclass 15, count 0 2006.173.20:50:58.57#ibcon#about to read 6, iclass 15, count 0 2006.173.20:50:58.57#ibcon#read 6, iclass 15, count 0 2006.173.20:50:58.57#ibcon#end of sib2, iclass 15, count 0 2006.173.20:50:58.57#ibcon#*mode == 0, iclass 15, count 0 2006.173.20:50:58.57#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.20:50:58.57#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.20:50:58.57#ibcon#*before write, iclass 15, count 0 2006.173.20:50:58.57#ibcon#enter sib2, iclass 15, count 0 2006.173.20:50:58.57#ibcon#flushed, iclass 15, count 0 2006.173.20:50:58.57#ibcon#about to write, iclass 15, count 0 2006.173.20:50:58.57#ibcon#wrote, iclass 15, count 0 2006.173.20:50:58.57#ibcon#about to read 3, iclass 15, count 0 2006.173.20:50:58.61#ibcon#read 3, iclass 15, count 0 2006.173.20:50:58.61#ibcon#about to read 4, iclass 15, count 0 2006.173.20:50:58.61#ibcon#read 4, iclass 15, count 0 2006.173.20:50:58.61#ibcon#about to read 5, iclass 15, count 0 2006.173.20:50:58.61#ibcon#read 5, iclass 15, count 0 2006.173.20:50:58.61#ibcon#about to read 6, iclass 15, count 0 2006.173.20:50:58.61#ibcon#read 6, iclass 15, count 0 2006.173.20:50:58.61#ibcon#end of sib2, iclass 15, count 0 2006.173.20:50:58.61#ibcon#*after write, iclass 15, count 0 2006.173.20:50:58.61#ibcon#*before return 0, iclass 15, count 0 2006.173.20:50:58.61#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.20:50:58.61#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.20:50:58.61#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.20:50:58.61#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.20:50:58.61$vck44/va=5,4 2006.173.20:50:58.61#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.20:50:58.61#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.20:50:58.61#ibcon#ireg 11 cls_cnt 2 2006.173.20:50:58.61#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.20:50:58.67#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.20:50:58.67#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.20:50:58.67#ibcon#enter wrdev, iclass 17, count 2 2006.173.20:50:58.67#ibcon#first serial, iclass 17, count 2 2006.173.20:50:58.67#ibcon#enter sib2, iclass 17, count 2 2006.173.20:50:58.67#ibcon#flushed, iclass 17, count 2 2006.173.20:50:58.67#ibcon#about to write, iclass 17, count 2 2006.173.20:50:58.67#ibcon#wrote, iclass 17, count 2 2006.173.20:50:58.67#ibcon#about to read 3, iclass 17, count 2 2006.173.20:50:58.69#ibcon#read 3, iclass 17, count 2 2006.173.20:50:58.69#ibcon#about to read 4, iclass 17, count 2 2006.173.20:50:58.69#ibcon#read 4, iclass 17, count 2 2006.173.20:50:58.69#ibcon#about to read 5, iclass 17, count 2 2006.173.20:50:58.69#ibcon#read 5, iclass 17, count 2 2006.173.20:50:58.69#ibcon#about to read 6, iclass 17, count 2 2006.173.20:50:58.69#ibcon#read 6, iclass 17, count 2 2006.173.20:50:58.69#ibcon#end of sib2, iclass 17, count 2 2006.173.20:50:58.69#ibcon#*mode == 0, iclass 17, count 2 2006.173.20:50:58.69#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.20:50:58.69#ibcon#[25=AT05-04\r\n] 2006.173.20:50:58.69#ibcon#*before write, iclass 17, count 2 2006.173.20:50:58.69#ibcon#enter sib2, iclass 17, count 2 2006.173.20:50:58.69#ibcon#flushed, iclass 17, count 2 2006.173.20:50:58.69#ibcon#about to write, iclass 17, count 2 2006.173.20:50:58.69#ibcon#wrote, iclass 17, count 2 2006.173.20:50:58.69#ibcon#about to read 3, iclass 17, count 2 2006.173.20:50:58.72#ibcon#read 3, iclass 17, count 2 2006.173.20:50:58.72#ibcon#about to read 4, iclass 17, count 2 2006.173.20:50:58.72#ibcon#read 4, iclass 17, count 2 2006.173.20:50:58.72#ibcon#about to read 5, iclass 17, count 2 2006.173.20:50:58.72#ibcon#read 5, iclass 17, count 2 2006.173.20:50:58.72#ibcon#about to read 6, iclass 17, count 2 2006.173.20:50:58.72#ibcon#read 6, iclass 17, count 2 2006.173.20:50:58.72#ibcon#end of sib2, iclass 17, count 2 2006.173.20:50:58.72#ibcon#*after write, iclass 17, count 2 2006.173.20:50:58.72#ibcon#*before return 0, iclass 17, count 2 2006.173.20:50:58.72#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.20:50:58.72#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.20:50:58.72#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.20:50:58.72#ibcon#ireg 7 cls_cnt 0 2006.173.20:50:58.72#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.20:50:58.84#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.20:50:58.84#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.20:50:58.84#ibcon#enter wrdev, iclass 17, count 0 2006.173.20:50:58.84#ibcon#first serial, iclass 17, count 0 2006.173.20:50:58.84#ibcon#enter sib2, iclass 17, count 0 2006.173.20:50:58.84#ibcon#flushed, iclass 17, count 0 2006.173.20:50:58.84#ibcon#about to write, iclass 17, count 0 2006.173.20:50:58.84#ibcon#wrote, iclass 17, count 0 2006.173.20:50:58.84#ibcon#about to read 3, iclass 17, count 0 2006.173.20:50:58.86#ibcon#read 3, iclass 17, count 0 2006.173.20:50:58.86#ibcon#about to read 4, iclass 17, count 0 2006.173.20:50:58.86#ibcon#read 4, iclass 17, count 0 2006.173.20:50:58.86#ibcon#about to read 5, iclass 17, count 0 2006.173.20:50:58.86#ibcon#read 5, iclass 17, count 0 2006.173.20:50:58.86#ibcon#about to read 6, iclass 17, count 0 2006.173.20:50:58.86#ibcon#read 6, iclass 17, count 0 2006.173.20:50:58.86#ibcon#end of sib2, iclass 17, count 0 2006.173.20:50:58.86#ibcon#*mode == 0, iclass 17, count 0 2006.173.20:50:58.86#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.20:50:58.86#ibcon#[25=USB\r\n] 2006.173.20:50:58.86#ibcon#*before write, iclass 17, count 0 2006.173.20:50:58.86#ibcon#enter sib2, iclass 17, count 0 2006.173.20:50:58.86#ibcon#flushed, iclass 17, count 0 2006.173.20:50:58.86#ibcon#about to write, iclass 17, count 0 2006.173.20:50:58.86#ibcon#wrote, iclass 17, count 0 2006.173.20:50:58.86#ibcon#about to read 3, iclass 17, count 0 2006.173.20:50:58.89#ibcon#read 3, iclass 17, count 0 2006.173.20:50:58.89#ibcon#about to read 4, iclass 17, count 0 2006.173.20:50:58.89#ibcon#read 4, iclass 17, count 0 2006.173.20:50:58.89#ibcon#about to read 5, iclass 17, count 0 2006.173.20:50:58.89#ibcon#read 5, iclass 17, count 0 2006.173.20:50:58.89#ibcon#about to read 6, iclass 17, count 0 2006.173.20:50:58.89#ibcon#read 6, iclass 17, count 0 2006.173.20:50:58.89#ibcon#end of sib2, iclass 17, count 0 2006.173.20:50:58.89#ibcon#*after write, iclass 17, count 0 2006.173.20:50:58.89#ibcon#*before return 0, iclass 17, count 0 2006.173.20:50:58.89#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.20:50:58.89#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.20:50:58.89#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.20:50:58.89#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.20:50:58.89$vck44/valo=6,814.99 2006.173.20:50:58.89#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.20:50:58.89#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.20:50:58.89#ibcon#ireg 17 cls_cnt 0 2006.173.20:50:58.89#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.20:50:58.89#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.20:50:58.89#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.20:50:58.89#ibcon#enter wrdev, iclass 19, count 0 2006.173.20:50:58.89#ibcon#first serial, iclass 19, count 0 2006.173.20:50:58.89#ibcon#enter sib2, iclass 19, count 0 2006.173.20:50:58.89#ibcon#flushed, iclass 19, count 0 2006.173.20:50:58.89#ibcon#about to write, iclass 19, count 0 2006.173.20:50:58.89#ibcon#wrote, iclass 19, count 0 2006.173.20:50:58.89#ibcon#about to read 3, iclass 19, count 0 2006.173.20:50:58.91#ibcon#read 3, iclass 19, count 0 2006.173.20:50:58.91#ibcon#about to read 4, iclass 19, count 0 2006.173.20:50:58.91#ibcon#read 4, iclass 19, count 0 2006.173.20:50:58.91#ibcon#about to read 5, iclass 19, count 0 2006.173.20:50:58.91#ibcon#read 5, iclass 19, count 0 2006.173.20:50:58.91#ibcon#about to read 6, iclass 19, count 0 2006.173.20:50:58.91#ibcon#read 6, iclass 19, count 0 2006.173.20:50:58.91#ibcon#end of sib2, iclass 19, count 0 2006.173.20:50:58.91#ibcon#*mode == 0, iclass 19, count 0 2006.173.20:50:58.91#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.20:50:58.91#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.20:50:58.91#ibcon#*before write, iclass 19, count 0 2006.173.20:50:58.91#ibcon#enter sib2, iclass 19, count 0 2006.173.20:50:58.91#ibcon#flushed, iclass 19, count 0 2006.173.20:50:58.91#ibcon#about to write, iclass 19, count 0 2006.173.20:50:58.91#ibcon#wrote, iclass 19, count 0 2006.173.20:50:58.91#ibcon#about to read 3, iclass 19, count 0 2006.173.20:50:58.95#ibcon#read 3, iclass 19, count 0 2006.173.20:50:58.95#ibcon#about to read 4, iclass 19, count 0 2006.173.20:50:58.95#ibcon#read 4, iclass 19, count 0 2006.173.20:50:58.95#ibcon#about to read 5, iclass 19, count 0 2006.173.20:50:58.95#ibcon#read 5, iclass 19, count 0 2006.173.20:50:58.95#ibcon#about to read 6, iclass 19, count 0 2006.173.20:50:58.95#ibcon#read 6, iclass 19, count 0 2006.173.20:50:58.95#ibcon#end of sib2, iclass 19, count 0 2006.173.20:50:58.95#ibcon#*after write, iclass 19, count 0 2006.173.20:50:58.95#ibcon#*before return 0, iclass 19, count 0 2006.173.20:50:58.95#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.20:50:58.95#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.20:50:58.95#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.20:50:58.95#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.20:50:58.95$vck44/va=6,3 2006.173.20:50:58.95#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.20:50:58.95#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.20:50:58.95#ibcon#ireg 11 cls_cnt 2 2006.173.20:50:58.95#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.20:50:58.97#abcon#<5=/08 0.4 1.4 20.771001003.2\r\n> 2006.173.20:50:58.99#abcon#{5=INTERFACE CLEAR} 2006.173.20:50:59.01#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.20:50:59.01#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.20:50:59.01#ibcon#enter wrdev, iclass 22, count 2 2006.173.20:50:59.01#ibcon#first serial, iclass 22, count 2 2006.173.20:50:59.01#ibcon#enter sib2, iclass 22, count 2 2006.173.20:50:59.01#ibcon#flushed, iclass 22, count 2 2006.173.20:50:59.01#ibcon#about to write, iclass 22, count 2 2006.173.20:50:59.01#ibcon#wrote, iclass 22, count 2 2006.173.20:50:59.01#ibcon#about to read 3, iclass 22, count 2 2006.173.20:50:59.03#ibcon#read 3, iclass 22, count 2 2006.173.20:50:59.03#ibcon#about to read 4, iclass 22, count 2 2006.173.20:50:59.03#ibcon#read 4, iclass 22, count 2 2006.173.20:50:59.03#ibcon#about to read 5, iclass 22, count 2 2006.173.20:50:59.03#ibcon#read 5, iclass 22, count 2 2006.173.20:50:59.03#ibcon#about to read 6, iclass 22, count 2 2006.173.20:50:59.03#ibcon#read 6, iclass 22, count 2 2006.173.20:50:59.03#ibcon#end of sib2, iclass 22, count 2 2006.173.20:50:59.03#ibcon#*mode == 0, iclass 22, count 2 2006.173.20:50:59.03#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.20:50:59.03#ibcon#[25=AT06-03\r\n] 2006.173.20:50:59.03#ibcon#*before write, iclass 22, count 2 2006.173.20:50:59.03#ibcon#enter sib2, iclass 22, count 2 2006.173.20:50:59.03#ibcon#flushed, iclass 22, count 2 2006.173.20:50:59.03#ibcon#about to write, iclass 22, count 2 2006.173.20:50:59.03#ibcon#wrote, iclass 22, count 2 2006.173.20:50:59.03#ibcon#about to read 3, iclass 22, count 2 2006.173.20:50:59.05#abcon#[5=S1D000X0/0*\r\n] 2006.173.20:50:59.06#ibcon#read 3, iclass 22, count 2 2006.173.20:50:59.06#ibcon#about to read 4, iclass 22, count 2 2006.173.20:50:59.06#ibcon#read 4, iclass 22, count 2 2006.173.20:50:59.06#ibcon#about to read 5, iclass 22, count 2 2006.173.20:50:59.06#ibcon#read 5, iclass 22, count 2 2006.173.20:50:59.06#ibcon#about to read 6, iclass 22, count 2 2006.173.20:50:59.06#ibcon#read 6, iclass 22, count 2 2006.173.20:50:59.06#ibcon#end of sib2, iclass 22, count 2 2006.173.20:50:59.06#ibcon#*after write, iclass 22, count 2 2006.173.20:50:59.06#ibcon#*before return 0, iclass 22, count 2 2006.173.20:50:59.06#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.20:50:59.06#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.20:50:59.06#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.20:50:59.06#ibcon#ireg 7 cls_cnt 0 2006.173.20:50:59.06#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.20:50:59.18#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.20:50:59.18#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.20:50:59.18#ibcon#enter wrdev, iclass 22, count 0 2006.173.20:50:59.18#ibcon#first serial, iclass 22, count 0 2006.173.20:50:59.18#ibcon#enter sib2, iclass 22, count 0 2006.173.20:50:59.18#ibcon#flushed, iclass 22, count 0 2006.173.20:50:59.18#ibcon#about to write, iclass 22, count 0 2006.173.20:50:59.18#ibcon#wrote, iclass 22, count 0 2006.173.20:50:59.18#ibcon#about to read 3, iclass 22, count 0 2006.173.20:50:59.20#ibcon#read 3, iclass 22, count 0 2006.173.20:50:59.20#ibcon#about to read 4, iclass 22, count 0 2006.173.20:50:59.20#ibcon#read 4, iclass 22, count 0 2006.173.20:50:59.20#ibcon#about to read 5, iclass 22, count 0 2006.173.20:50:59.20#ibcon#read 5, iclass 22, count 0 2006.173.20:50:59.20#ibcon#about to read 6, iclass 22, count 0 2006.173.20:50:59.20#ibcon#read 6, iclass 22, count 0 2006.173.20:50:59.20#ibcon#end of sib2, iclass 22, count 0 2006.173.20:50:59.20#ibcon#*mode == 0, iclass 22, count 0 2006.173.20:50:59.20#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.20:50:59.20#ibcon#[25=USB\r\n] 2006.173.20:50:59.20#ibcon#*before write, iclass 22, count 0 2006.173.20:50:59.20#ibcon#enter sib2, iclass 22, count 0 2006.173.20:50:59.20#ibcon#flushed, iclass 22, count 0 2006.173.20:50:59.20#ibcon#about to write, iclass 22, count 0 2006.173.20:50:59.20#ibcon#wrote, iclass 22, count 0 2006.173.20:50:59.20#ibcon#about to read 3, iclass 22, count 0 2006.173.20:50:59.23#ibcon#read 3, iclass 22, count 0 2006.173.20:50:59.23#ibcon#about to read 4, iclass 22, count 0 2006.173.20:50:59.23#ibcon#read 4, iclass 22, count 0 2006.173.20:50:59.23#ibcon#about to read 5, iclass 22, count 0 2006.173.20:50:59.23#ibcon#read 5, iclass 22, count 0 2006.173.20:50:59.23#ibcon#about to read 6, iclass 22, count 0 2006.173.20:50:59.23#ibcon#read 6, iclass 22, count 0 2006.173.20:50:59.23#ibcon#end of sib2, iclass 22, count 0 2006.173.20:50:59.23#ibcon#*after write, iclass 22, count 0 2006.173.20:50:59.23#ibcon#*before return 0, iclass 22, count 0 2006.173.20:50:59.23#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.20:50:59.23#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.20:50:59.23#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.20:50:59.23#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.20:50:59.23$vck44/valo=7,864.99 2006.173.20:50:59.23#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.20:50:59.23#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.20:50:59.23#ibcon#ireg 17 cls_cnt 0 2006.173.20:50:59.23#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.20:50:59.23#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.20:50:59.23#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.20:50:59.23#ibcon#enter wrdev, iclass 27, count 0 2006.173.20:50:59.23#ibcon#first serial, iclass 27, count 0 2006.173.20:50:59.23#ibcon#enter sib2, iclass 27, count 0 2006.173.20:50:59.23#ibcon#flushed, iclass 27, count 0 2006.173.20:50:59.23#ibcon#about to write, iclass 27, count 0 2006.173.20:50:59.23#ibcon#wrote, iclass 27, count 0 2006.173.20:50:59.23#ibcon#about to read 3, iclass 27, count 0 2006.173.20:50:59.25#ibcon#read 3, iclass 27, count 0 2006.173.20:50:59.25#ibcon#about to read 4, iclass 27, count 0 2006.173.20:50:59.25#ibcon#read 4, iclass 27, count 0 2006.173.20:50:59.25#ibcon#about to read 5, iclass 27, count 0 2006.173.20:50:59.25#ibcon#read 5, iclass 27, count 0 2006.173.20:50:59.25#ibcon#about to read 6, iclass 27, count 0 2006.173.20:50:59.25#ibcon#read 6, iclass 27, count 0 2006.173.20:50:59.25#ibcon#end of sib2, iclass 27, count 0 2006.173.20:50:59.25#ibcon#*mode == 0, iclass 27, count 0 2006.173.20:50:59.25#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.20:50:59.25#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.20:50:59.25#ibcon#*before write, iclass 27, count 0 2006.173.20:50:59.25#ibcon#enter sib2, iclass 27, count 0 2006.173.20:50:59.25#ibcon#flushed, iclass 27, count 0 2006.173.20:50:59.25#ibcon#about to write, iclass 27, count 0 2006.173.20:50:59.25#ibcon#wrote, iclass 27, count 0 2006.173.20:50:59.25#ibcon#about to read 3, iclass 27, count 0 2006.173.20:50:59.29#ibcon#read 3, iclass 27, count 0 2006.173.20:50:59.29#ibcon#about to read 4, iclass 27, count 0 2006.173.20:50:59.29#ibcon#read 4, iclass 27, count 0 2006.173.20:50:59.29#ibcon#about to read 5, iclass 27, count 0 2006.173.20:50:59.29#ibcon#read 5, iclass 27, count 0 2006.173.20:50:59.29#ibcon#about to read 6, iclass 27, count 0 2006.173.20:50:59.29#ibcon#read 6, iclass 27, count 0 2006.173.20:50:59.29#ibcon#end of sib2, iclass 27, count 0 2006.173.20:50:59.29#ibcon#*after write, iclass 27, count 0 2006.173.20:50:59.29#ibcon#*before return 0, iclass 27, count 0 2006.173.20:50:59.29#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.20:50:59.29#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.20:50:59.29#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.20:50:59.29#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.20:50:59.29$vck44/va=7,4 2006.173.20:50:59.29#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.20:50:59.29#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.20:50:59.29#ibcon#ireg 11 cls_cnt 2 2006.173.20:50:59.29#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.20:50:59.35#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.20:50:59.35#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.20:50:59.35#ibcon#enter wrdev, iclass 29, count 2 2006.173.20:50:59.35#ibcon#first serial, iclass 29, count 2 2006.173.20:50:59.35#ibcon#enter sib2, iclass 29, count 2 2006.173.20:50:59.35#ibcon#flushed, iclass 29, count 2 2006.173.20:50:59.35#ibcon#about to write, iclass 29, count 2 2006.173.20:50:59.35#ibcon#wrote, iclass 29, count 2 2006.173.20:50:59.35#ibcon#about to read 3, iclass 29, count 2 2006.173.20:50:59.37#ibcon#read 3, iclass 29, count 2 2006.173.20:50:59.37#ibcon#about to read 4, iclass 29, count 2 2006.173.20:50:59.37#ibcon#read 4, iclass 29, count 2 2006.173.20:50:59.37#ibcon#about to read 5, iclass 29, count 2 2006.173.20:50:59.37#ibcon#read 5, iclass 29, count 2 2006.173.20:50:59.37#ibcon#about to read 6, iclass 29, count 2 2006.173.20:50:59.37#ibcon#read 6, iclass 29, count 2 2006.173.20:50:59.37#ibcon#end of sib2, iclass 29, count 2 2006.173.20:50:59.37#ibcon#*mode == 0, iclass 29, count 2 2006.173.20:50:59.37#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.20:50:59.37#ibcon#[25=AT07-04\r\n] 2006.173.20:50:59.37#ibcon#*before write, iclass 29, count 2 2006.173.20:50:59.37#ibcon#enter sib2, iclass 29, count 2 2006.173.20:50:59.37#ibcon#flushed, iclass 29, count 2 2006.173.20:50:59.37#ibcon#about to write, iclass 29, count 2 2006.173.20:50:59.37#ibcon#wrote, iclass 29, count 2 2006.173.20:50:59.37#ibcon#about to read 3, iclass 29, count 2 2006.173.20:50:59.40#ibcon#read 3, iclass 29, count 2 2006.173.20:50:59.40#ibcon#about to read 4, iclass 29, count 2 2006.173.20:50:59.40#ibcon#read 4, iclass 29, count 2 2006.173.20:50:59.40#ibcon#about to read 5, iclass 29, count 2 2006.173.20:50:59.40#ibcon#read 5, iclass 29, count 2 2006.173.20:50:59.40#ibcon#about to read 6, iclass 29, count 2 2006.173.20:50:59.40#ibcon#read 6, iclass 29, count 2 2006.173.20:50:59.40#ibcon#end of sib2, iclass 29, count 2 2006.173.20:50:59.40#ibcon#*after write, iclass 29, count 2 2006.173.20:50:59.40#ibcon#*before return 0, iclass 29, count 2 2006.173.20:50:59.40#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.20:50:59.40#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.20:50:59.40#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.20:50:59.40#ibcon#ireg 7 cls_cnt 0 2006.173.20:50:59.40#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.20:50:59.52#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.20:50:59.52#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.20:50:59.52#ibcon#enter wrdev, iclass 29, count 0 2006.173.20:50:59.52#ibcon#first serial, iclass 29, count 0 2006.173.20:50:59.52#ibcon#enter sib2, iclass 29, count 0 2006.173.20:50:59.52#ibcon#flushed, iclass 29, count 0 2006.173.20:50:59.52#ibcon#about to write, iclass 29, count 0 2006.173.20:50:59.52#ibcon#wrote, iclass 29, count 0 2006.173.20:50:59.52#ibcon#about to read 3, iclass 29, count 0 2006.173.20:50:59.54#ibcon#read 3, iclass 29, count 0 2006.173.20:50:59.54#ibcon#about to read 4, iclass 29, count 0 2006.173.20:50:59.54#ibcon#read 4, iclass 29, count 0 2006.173.20:50:59.54#ibcon#about to read 5, iclass 29, count 0 2006.173.20:50:59.54#ibcon#read 5, iclass 29, count 0 2006.173.20:50:59.54#ibcon#about to read 6, iclass 29, count 0 2006.173.20:50:59.54#ibcon#read 6, iclass 29, count 0 2006.173.20:50:59.54#ibcon#end of sib2, iclass 29, count 0 2006.173.20:50:59.54#ibcon#*mode == 0, iclass 29, count 0 2006.173.20:50:59.54#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.20:50:59.54#ibcon#[25=USB\r\n] 2006.173.20:50:59.54#ibcon#*before write, iclass 29, count 0 2006.173.20:50:59.54#ibcon#enter sib2, iclass 29, count 0 2006.173.20:50:59.54#ibcon#flushed, iclass 29, count 0 2006.173.20:50:59.54#ibcon#about to write, iclass 29, count 0 2006.173.20:50:59.54#ibcon#wrote, iclass 29, count 0 2006.173.20:50:59.54#ibcon#about to read 3, iclass 29, count 0 2006.173.20:50:59.57#ibcon#read 3, iclass 29, count 0 2006.173.20:50:59.57#ibcon#about to read 4, iclass 29, count 0 2006.173.20:50:59.57#ibcon#read 4, iclass 29, count 0 2006.173.20:50:59.57#ibcon#about to read 5, iclass 29, count 0 2006.173.20:50:59.57#ibcon#read 5, iclass 29, count 0 2006.173.20:50:59.57#ibcon#about to read 6, iclass 29, count 0 2006.173.20:50:59.57#ibcon#read 6, iclass 29, count 0 2006.173.20:50:59.57#ibcon#end of sib2, iclass 29, count 0 2006.173.20:50:59.57#ibcon#*after write, iclass 29, count 0 2006.173.20:50:59.57#ibcon#*before return 0, iclass 29, count 0 2006.173.20:50:59.57#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.20:50:59.57#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.20:50:59.57#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.20:50:59.57#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.20:50:59.57$vck44/valo=8,884.99 2006.173.20:50:59.57#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.20:50:59.57#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.20:50:59.57#ibcon#ireg 17 cls_cnt 0 2006.173.20:50:59.57#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.20:50:59.57#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.20:50:59.57#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.20:50:59.57#ibcon#enter wrdev, iclass 31, count 0 2006.173.20:50:59.57#ibcon#first serial, iclass 31, count 0 2006.173.20:50:59.57#ibcon#enter sib2, iclass 31, count 0 2006.173.20:50:59.57#ibcon#flushed, iclass 31, count 0 2006.173.20:50:59.57#ibcon#about to write, iclass 31, count 0 2006.173.20:50:59.57#ibcon#wrote, iclass 31, count 0 2006.173.20:50:59.57#ibcon#about to read 3, iclass 31, count 0 2006.173.20:50:59.59#ibcon#read 3, iclass 31, count 0 2006.173.20:50:59.59#ibcon#about to read 4, iclass 31, count 0 2006.173.20:50:59.59#ibcon#read 4, iclass 31, count 0 2006.173.20:50:59.59#ibcon#about to read 5, iclass 31, count 0 2006.173.20:50:59.59#ibcon#read 5, iclass 31, count 0 2006.173.20:50:59.59#ibcon#about to read 6, iclass 31, count 0 2006.173.20:50:59.59#ibcon#read 6, iclass 31, count 0 2006.173.20:50:59.59#ibcon#end of sib2, iclass 31, count 0 2006.173.20:50:59.59#ibcon#*mode == 0, iclass 31, count 0 2006.173.20:50:59.59#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.20:50:59.59#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.20:50:59.59#ibcon#*before write, iclass 31, count 0 2006.173.20:50:59.59#ibcon#enter sib2, iclass 31, count 0 2006.173.20:50:59.59#ibcon#flushed, iclass 31, count 0 2006.173.20:50:59.59#ibcon#about to write, iclass 31, count 0 2006.173.20:50:59.59#ibcon#wrote, iclass 31, count 0 2006.173.20:50:59.59#ibcon#about to read 3, iclass 31, count 0 2006.173.20:50:59.63#ibcon#read 3, iclass 31, count 0 2006.173.20:50:59.63#ibcon#about to read 4, iclass 31, count 0 2006.173.20:50:59.63#ibcon#read 4, iclass 31, count 0 2006.173.20:50:59.63#ibcon#about to read 5, iclass 31, count 0 2006.173.20:50:59.63#ibcon#read 5, iclass 31, count 0 2006.173.20:50:59.63#ibcon#about to read 6, iclass 31, count 0 2006.173.20:50:59.63#ibcon#read 6, iclass 31, count 0 2006.173.20:50:59.63#ibcon#end of sib2, iclass 31, count 0 2006.173.20:50:59.63#ibcon#*after write, iclass 31, count 0 2006.173.20:50:59.63#ibcon#*before return 0, iclass 31, count 0 2006.173.20:50:59.63#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.20:50:59.63#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.20:50:59.63#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.20:50:59.63#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.20:50:59.63$vck44/va=8,4 2006.173.20:50:59.63#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.173.20:50:59.63#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.173.20:50:59.63#ibcon#ireg 11 cls_cnt 2 2006.173.20:50:59.63#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.20:50:59.69#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.20:50:59.69#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.20:50:59.69#ibcon#enter wrdev, iclass 33, count 2 2006.173.20:50:59.69#ibcon#first serial, iclass 33, count 2 2006.173.20:50:59.69#ibcon#enter sib2, iclass 33, count 2 2006.173.20:50:59.69#ibcon#flushed, iclass 33, count 2 2006.173.20:50:59.69#ibcon#about to write, iclass 33, count 2 2006.173.20:50:59.69#ibcon#wrote, iclass 33, count 2 2006.173.20:50:59.69#ibcon#about to read 3, iclass 33, count 2 2006.173.20:50:59.71#ibcon#read 3, iclass 33, count 2 2006.173.20:50:59.71#ibcon#about to read 4, iclass 33, count 2 2006.173.20:50:59.71#ibcon#read 4, iclass 33, count 2 2006.173.20:50:59.71#ibcon#about to read 5, iclass 33, count 2 2006.173.20:50:59.71#ibcon#read 5, iclass 33, count 2 2006.173.20:50:59.71#ibcon#about to read 6, iclass 33, count 2 2006.173.20:50:59.71#ibcon#read 6, iclass 33, count 2 2006.173.20:50:59.71#ibcon#end of sib2, iclass 33, count 2 2006.173.20:50:59.71#ibcon#*mode == 0, iclass 33, count 2 2006.173.20:50:59.71#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.173.20:50:59.71#ibcon#[25=AT08-04\r\n] 2006.173.20:50:59.71#ibcon#*before write, iclass 33, count 2 2006.173.20:50:59.71#ibcon#enter sib2, iclass 33, count 2 2006.173.20:50:59.71#ibcon#flushed, iclass 33, count 2 2006.173.20:50:59.71#ibcon#about to write, iclass 33, count 2 2006.173.20:50:59.71#ibcon#wrote, iclass 33, count 2 2006.173.20:50:59.71#ibcon#about to read 3, iclass 33, count 2 2006.173.20:50:59.74#ibcon#read 3, iclass 33, count 2 2006.173.20:50:59.74#ibcon#about to read 4, iclass 33, count 2 2006.173.20:50:59.74#ibcon#read 4, iclass 33, count 2 2006.173.20:50:59.74#ibcon#about to read 5, iclass 33, count 2 2006.173.20:50:59.74#ibcon#read 5, iclass 33, count 2 2006.173.20:50:59.74#ibcon#about to read 6, iclass 33, count 2 2006.173.20:50:59.74#ibcon#read 6, iclass 33, count 2 2006.173.20:50:59.74#ibcon#end of sib2, iclass 33, count 2 2006.173.20:50:59.74#ibcon#*after write, iclass 33, count 2 2006.173.20:50:59.74#ibcon#*before return 0, iclass 33, count 2 2006.173.20:50:59.74#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.20:50:59.74#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.173.20:50:59.74#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.173.20:50:59.74#ibcon#ireg 7 cls_cnt 0 2006.173.20:50:59.74#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.20:50:59.86#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.20:50:59.86#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.20:50:59.86#ibcon#enter wrdev, iclass 33, count 0 2006.173.20:50:59.86#ibcon#first serial, iclass 33, count 0 2006.173.20:50:59.86#ibcon#enter sib2, iclass 33, count 0 2006.173.20:50:59.86#ibcon#flushed, iclass 33, count 0 2006.173.20:50:59.86#ibcon#about to write, iclass 33, count 0 2006.173.20:50:59.86#ibcon#wrote, iclass 33, count 0 2006.173.20:50:59.86#ibcon#about to read 3, iclass 33, count 0 2006.173.20:50:59.88#ibcon#read 3, iclass 33, count 0 2006.173.20:50:59.88#ibcon#about to read 4, iclass 33, count 0 2006.173.20:50:59.88#ibcon#read 4, iclass 33, count 0 2006.173.20:50:59.88#ibcon#about to read 5, iclass 33, count 0 2006.173.20:50:59.88#ibcon#read 5, iclass 33, count 0 2006.173.20:50:59.88#ibcon#about to read 6, iclass 33, count 0 2006.173.20:50:59.88#ibcon#read 6, iclass 33, count 0 2006.173.20:50:59.88#ibcon#end of sib2, iclass 33, count 0 2006.173.20:50:59.88#ibcon#*mode == 0, iclass 33, count 0 2006.173.20:50:59.88#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.20:50:59.88#ibcon#[25=USB\r\n] 2006.173.20:50:59.88#ibcon#*before write, iclass 33, count 0 2006.173.20:50:59.88#ibcon#enter sib2, iclass 33, count 0 2006.173.20:50:59.88#ibcon#flushed, iclass 33, count 0 2006.173.20:50:59.88#ibcon#about to write, iclass 33, count 0 2006.173.20:50:59.88#ibcon#wrote, iclass 33, count 0 2006.173.20:50:59.88#ibcon#about to read 3, iclass 33, count 0 2006.173.20:50:59.91#ibcon#read 3, iclass 33, count 0 2006.173.20:50:59.91#ibcon#about to read 4, iclass 33, count 0 2006.173.20:50:59.91#ibcon#read 4, iclass 33, count 0 2006.173.20:50:59.91#ibcon#about to read 5, iclass 33, count 0 2006.173.20:50:59.91#ibcon#read 5, iclass 33, count 0 2006.173.20:50:59.91#ibcon#about to read 6, iclass 33, count 0 2006.173.20:50:59.91#ibcon#read 6, iclass 33, count 0 2006.173.20:50:59.91#ibcon#end of sib2, iclass 33, count 0 2006.173.20:50:59.91#ibcon#*after write, iclass 33, count 0 2006.173.20:50:59.91#ibcon#*before return 0, iclass 33, count 0 2006.173.20:50:59.91#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.20:50:59.91#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.173.20:50:59.91#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.20:50:59.91#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.20:50:59.91$vck44/vblo=1,629.99 2006.173.20:50:59.91#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.20:50:59.91#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.20:50:59.91#ibcon#ireg 17 cls_cnt 0 2006.173.20:50:59.91#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.20:50:59.91#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.20:50:59.91#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.20:50:59.91#ibcon#enter wrdev, iclass 35, count 0 2006.173.20:50:59.91#ibcon#first serial, iclass 35, count 0 2006.173.20:50:59.91#ibcon#enter sib2, iclass 35, count 0 2006.173.20:50:59.91#ibcon#flushed, iclass 35, count 0 2006.173.20:50:59.91#ibcon#about to write, iclass 35, count 0 2006.173.20:50:59.91#ibcon#wrote, iclass 35, count 0 2006.173.20:50:59.91#ibcon#about to read 3, iclass 35, count 0 2006.173.20:50:59.93#ibcon#read 3, iclass 35, count 0 2006.173.20:50:59.93#ibcon#about to read 4, iclass 35, count 0 2006.173.20:50:59.93#ibcon#read 4, iclass 35, count 0 2006.173.20:50:59.93#ibcon#about to read 5, iclass 35, count 0 2006.173.20:50:59.93#ibcon#read 5, iclass 35, count 0 2006.173.20:50:59.93#ibcon#about to read 6, iclass 35, count 0 2006.173.20:50:59.93#ibcon#read 6, iclass 35, count 0 2006.173.20:50:59.93#ibcon#end of sib2, iclass 35, count 0 2006.173.20:50:59.93#ibcon#*mode == 0, iclass 35, count 0 2006.173.20:50:59.93#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.20:50:59.93#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.20:50:59.93#ibcon#*before write, iclass 35, count 0 2006.173.20:50:59.93#ibcon#enter sib2, iclass 35, count 0 2006.173.20:50:59.93#ibcon#flushed, iclass 35, count 0 2006.173.20:50:59.93#ibcon#about to write, iclass 35, count 0 2006.173.20:50:59.93#ibcon#wrote, iclass 35, count 0 2006.173.20:50:59.93#ibcon#about to read 3, iclass 35, count 0 2006.173.20:50:59.97#ibcon#read 3, iclass 35, count 0 2006.173.20:50:59.97#ibcon#about to read 4, iclass 35, count 0 2006.173.20:50:59.97#ibcon#read 4, iclass 35, count 0 2006.173.20:50:59.97#ibcon#about to read 5, iclass 35, count 0 2006.173.20:50:59.97#ibcon#read 5, iclass 35, count 0 2006.173.20:50:59.97#ibcon#about to read 6, iclass 35, count 0 2006.173.20:50:59.97#ibcon#read 6, iclass 35, count 0 2006.173.20:50:59.97#ibcon#end of sib2, iclass 35, count 0 2006.173.20:50:59.97#ibcon#*after write, iclass 35, count 0 2006.173.20:50:59.97#ibcon#*before return 0, iclass 35, count 0 2006.173.20:50:59.97#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.20:50:59.97#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.20:50:59.97#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.20:50:59.97#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.20:50:59.97$vck44/vb=1,4 2006.173.20:50:59.97#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.173.20:50:59.97#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.173.20:50:59.97#ibcon#ireg 11 cls_cnt 2 2006.173.20:50:59.97#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.20:50:59.97#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.20:50:59.97#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.20:50:59.97#ibcon#enter wrdev, iclass 37, count 2 2006.173.20:50:59.97#ibcon#first serial, iclass 37, count 2 2006.173.20:50:59.97#ibcon#enter sib2, iclass 37, count 2 2006.173.20:50:59.97#ibcon#flushed, iclass 37, count 2 2006.173.20:50:59.97#ibcon#about to write, iclass 37, count 2 2006.173.20:50:59.97#ibcon#wrote, iclass 37, count 2 2006.173.20:50:59.97#ibcon#about to read 3, iclass 37, count 2 2006.173.20:50:59.99#ibcon#read 3, iclass 37, count 2 2006.173.20:50:59.99#ibcon#about to read 4, iclass 37, count 2 2006.173.20:50:59.99#ibcon#read 4, iclass 37, count 2 2006.173.20:50:59.99#ibcon#about to read 5, iclass 37, count 2 2006.173.20:50:59.99#ibcon#read 5, iclass 37, count 2 2006.173.20:50:59.99#ibcon#about to read 6, iclass 37, count 2 2006.173.20:50:59.99#ibcon#read 6, iclass 37, count 2 2006.173.20:50:59.99#ibcon#end of sib2, iclass 37, count 2 2006.173.20:50:59.99#ibcon#*mode == 0, iclass 37, count 2 2006.173.20:50:59.99#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.173.20:50:59.99#ibcon#[27=AT01-04\r\n] 2006.173.20:50:59.99#ibcon#*before write, iclass 37, count 2 2006.173.20:50:59.99#ibcon#enter sib2, iclass 37, count 2 2006.173.20:50:59.99#ibcon#flushed, iclass 37, count 2 2006.173.20:50:59.99#ibcon#about to write, iclass 37, count 2 2006.173.20:50:59.99#ibcon#wrote, iclass 37, count 2 2006.173.20:50:59.99#ibcon#about to read 3, iclass 37, count 2 2006.173.20:51:00.02#ibcon#read 3, iclass 37, count 2 2006.173.20:51:00.02#ibcon#about to read 4, iclass 37, count 2 2006.173.20:51:00.02#ibcon#read 4, iclass 37, count 2 2006.173.20:51:00.02#ibcon#about to read 5, iclass 37, count 2 2006.173.20:51:00.02#ibcon#read 5, iclass 37, count 2 2006.173.20:51:00.02#ibcon#about to read 6, iclass 37, count 2 2006.173.20:51:00.02#ibcon#read 6, iclass 37, count 2 2006.173.20:51:00.02#ibcon#end of sib2, iclass 37, count 2 2006.173.20:51:00.02#ibcon#*after write, iclass 37, count 2 2006.173.20:51:00.02#ibcon#*before return 0, iclass 37, count 2 2006.173.20:51:00.02#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.20:51:00.02#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.173.20:51:00.02#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.173.20:51:00.02#ibcon#ireg 7 cls_cnt 0 2006.173.20:51:00.02#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.20:51:00.14#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.20:51:00.14#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.20:51:00.14#ibcon#enter wrdev, iclass 37, count 0 2006.173.20:51:00.14#ibcon#first serial, iclass 37, count 0 2006.173.20:51:00.14#ibcon#enter sib2, iclass 37, count 0 2006.173.20:51:00.14#ibcon#flushed, iclass 37, count 0 2006.173.20:51:00.14#ibcon#about to write, iclass 37, count 0 2006.173.20:51:00.14#ibcon#wrote, iclass 37, count 0 2006.173.20:51:00.14#ibcon#about to read 3, iclass 37, count 0 2006.173.20:51:00.16#ibcon#read 3, iclass 37, count 0 2006.173.20:51:00.16#ibcon#about to read 4, iclass 37, count 0 2006.173.20:51:00.16#ibcon#read 4, iclass 37, count 0 2006.173.20:51:00.16#ibcon#about to read 5, iclass 37, count 0 2006.173.20:51:00.16#ibcon#read 5, iclass 37, count 0 2006.173.20:51:00.16#ibcon#about to read 6, iclass 37, count 0 2006.173.20:51:00.16#ibcon#read 6, iclass 37, count 0 2006.173.20:51:00.16#ibcon#end of sib2, iclass 37, count 0 2006.173.20:51:00.16#ibcon#*mode == 0, iclass 37, count 0 2006.173.20:51:00.16#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.20:51:00.16#ibcon#[27=USB\r\n] 2006.173.20:51:00.16#ibcon#*before write, iclass 37, count 0 2006.173.20:51:00.16#ibcon#enter sib2, iclass 37, count 0 2006.173.20:51:00.16#ibcon#flushed, iclass 37, count 0 2006.173.20:51:00.16#ibcon#about to write, iclass 37, count 0 2006.173.20:51:00.16#ibcon#wrote, iclass 37, count 0 2006.173.20:51:00.16#ibcon#about to read 3, iclass 37, count 0 2006.173.20:51:00.19#ibcon#read 3, iclass 37, count 0 2006.173.20:51:00.19#ibcon#about to read 4, iclass 37, count 0 2006.173.20:51:00.19#ibcon#read 4, iclass 37, count 0 2006.173.20:51:00.19#ibcon#about to read 5, iclass 37, count 0 2006.173.20:51:00.19#ibcon#read 5, iclass 37, count 0 2006.173.20:51:00.19#ibcon#about to read 6, iclass 37, count 0 2006.173.20:51:00.19#ibcon#read 6, iclass 37, count 0 2006.173.20:51:00.19#ibcon#end of sib2, iclass 37, count 0 2006.173.20:51:00.19#ibcon#*after write, iclass 37, count 0 2006.173.20:51:00.19#ibcon#*before return 0, iclass 37, count 0 2006.173.20:51:00.19#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.20:51:00.19#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.173.20:51:00.19#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.20:51:00.19#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.20:51:00.19$vck44/vblo=2,634.99 2006.173.20:51:00.19#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.20:51:00.19#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.20:51:00.19#ibcon#ireg 17 cls_cnt 0 2006.173.20:51:00.19#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.20:51:00.19#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.20:51:00.19#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.20:51:00.19#ibcon#enter wrdev, iclass 39, count 0 2006.173.20:51:00.19#ibcon#first serial, iclass 39, count 0 2006.173.20:51:00.19#ibcon#enter sib2, iclass 39, count 0 2006.173.20:51:00.19#ibcon#flushed, iclass 39, count 0 2006.173.20:51:00.19#ibcon#about to write, iclass 39, count 0 2006.173.20:51:00.19#ibcon#wrote, iclass 39, count 0 2006.173.20:51:00.19#ibcon#about to read 3, iclass 39, count 0 2006.173.20:51:00.21#ibcon#read 3, iclass 39, count 0 2006.173.20:51:00.21#ibcon#about to read 4, iclass 39, count 0 2006.173.20:51:00.21#ibcon#read 4, iclass 39, count 0 2006.173.20:51:00.21#ibcon#about to read 5, iclass 39, count 0 2006.173.20:51:00.21#ibcon#read 5, iclass 39, count 0 2006.173.20:51:00.21#ibcon#about to read 6, iclass 39, count 0 2006.173.20:51:00.21#ibcon#read 6, iclass 39, count 0 2006.173.20:51:00.21#ibcon#end of sib2, iclass 39, count 0 2006.173.20:51:00.21#ibcon#*mode == 0, iclass 39, count 0 2006.173.20:51:00.21#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.20:51:00.21#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.20:51:00.21#ibcon#*before write, iclass 39, count 0 2006.173.20:51:00.21#ibcon#enter sib2, iclass 39, count 0 2006.173.20:51:00.21#ibcon#flushed, iclass 39, count 0 2006.173.20:51:00.21#ibcon#about to write, iclass 39, count 0 2006.173.20:51:00.21#ibcon#wrote, iclass 39, count 0 2006.173.20:51:00.21#ibcon#about to read 3, iclass 39, count 0 2006.173.20:51:00.25#ibcon#read 3, iclass 39, count 0 2006.173.20:51:00.25#ibcon#about to read 4, iclass 39, count 0 2006.173.20:51:00.25#ibcon#read 4, iclass 39, count 0 2006.173.20:51:00.25#ibcon#about to read 5, iclass 39, count 0 2006.173.20:51:00.25#ibcon#read 5, iclass 39, count 0 2006.173.20:51:00.25#ibcon#about to read 6, iclass 39, count 0 2006.173.20:51:00.25#ibcon#read 6, iclass 39, count 0 2006.173.20:51:00.25#ibcon#end of sib2, iclass 39, count 0 2006.173.20:51:00.25#ibcon#*after write, iclass 39, count 0 2006.173.20:51:00.25#ibcon#*before return 0, iclass 39, count 0 2006.173.20:51:00.25#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.20:51:00.25#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.20:51:00.25#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.20:51:00.25#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.20:51:00.25$vck44/vb=2,4 2006.173.20:51:00.25#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.20:51:00.25#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.20:51:00.25#ibcon#ireg 11 cls_cnt 2 2006.173.20:51:00.25#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.20:51:00.31#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.20:51:00.31#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.20:51:00.31#ibcon#enter wrdev, iclass 3, count 2 2006.173.20:51:00.31#ibcon#first serial, iclass 3, count 2 2006.173.20:51:00.31#ibcon#enter sib2, iclass 3, count 2 2006.173.20:51:00.31#ibcon#flushed, iclass 3, count 2 2006.173.20:51:00.31#ibcon#about to write, iclass 3, count 2 2006.173.20:51:00.31#ibcon#wrote, iclass 3, count 2 2006.173.20:51:00.31#ibcon#about to read 3, iclass 3, count 2 2006.173.20:51:00.33#ibcon#read 3, iclass 3, count 2 2006.173.20:51:00.33#ibcon#about to read 4, iclass 3, count 2 2006.173.20:51:00.33#ibcon#read 4, iclass 3, count 2 2006.173.20:51:00.33#ibcon#about to read 5, iclass 3, count 2 2006.173.20:51:00.33#ibcon#read 5, iclass 3, count 2 2006.173.20:51:00.33#ibcon#about to read 6, iclass 3, count 2 2006.173.20:51:00.33#ibcon#read 6, iclass 3, count 2 2006.173.20:51:00.33#ibcon#end of sib2, iclass 3, count 2 2006.173.20:51:00.33#ibcon#*mode == 0, iclass 3, count 2 2006.173.20:51:00.33#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.20:51:00.33#ibcon#[27=AT02-04\r\n] 2006.173.20:51:00.33#ibcon#*before write, iclass 3, count 2 2006.173.20:51:00.33#ibcon#enter sib2, iclass 3, count 2 2006.173.20:51:00.33#ibcon#flushed, iclass 3, count 2 2006.173.20:51:00.33#ibcon#about to write, iclass 3, count 2 2006.173.20:51:00.33#ibcon#wrote, iclass 3, count 2 2006.173.20:51:00.33#ibcon#about to read 3, iclass 3, count 2 2006.173.20:51:00.36#ibcon#read 3, iclass 3, count 2 2006.173.20:51:00.36#ibcon#about to read 4, iclass 3, count 2 2006.173.20:51:00.36#ibcon#read 4, iclass 3, count 2 2006.173.20:51:00.36#ibcon#about to read 5, iclass 3, count 2 2006.173.20:51:00.36#ibcon#read 5, iclass 3, count 2 2006.173.20:51:00.36#ibcon#about to read 6, iclass 3, count 2 2006.173.20:51:00.36#ibcon#read 6, iclass 3, count 2 2006.173.20:51:00.36#ibcon#end of sib2, iclass 3, count 2 2006.173.20:51:00.36#ibcon#*after write, iclass 3, count 2 2006.173.20:51:00.36#ibcon#*before return 0, iclass 3, count 2 2006.173.20:51:00.36#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.20:51:00.36#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.20:51:00.36#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.20:51:00.36#ibcon#ireg 7 cls_cnt 0 2006.173.20:51:00.36#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.20:51:00.48#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.20:51:00.48#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.20:51:00.48#ibcon#enter wrdev, iclass 3, count 0 2006.173.20:51:00.48#ibcon#first serial, iclass 3, count 0 2006.173.20:51:00.48#ibcon#enter sib2, iclass 3, count 0 2006.173.20:51:00.48#ibcon#flushed, iclass 3, count 0 2006.173.20:51:00.48#ibcon#about to write, iclass 3, count 0 2006.173.20:51:00.48#ibcon#wrote, iclass 3, count 0 2006.173.20:51:00.48#ibcon#about to read 3, iclass 3, count 0 2006.173.20:51:00.50#ibcon#read 3, iclass 3, count 0 2006.173.20:51:00.50#ibcon#about to read 4, iclass 3, count 0 2006.173.20:51:00.50#ibcon#read 4, iclass 3, count 0 2006.173.20:51:00.50#ibcon#about to read 5, iclass 3, count 0 2006.173.20:51:00.50#ibcon#read 5, iclass 3, count 0 2006.173.20:51:00.50#ibcon#about to read 6, iclass 3, count 0 2006.173.20:51:00.50#ibcon#read 6, iclass 3, count 0 2006.173.20:51:00.50#ibcon#end of sib2, iclass 3, count 0 2006.173.20:51:00.50#ibcon#*mode == 0, iclass 3, count 0 2006.173.20:51:00.50#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.20:51:00.50#ibcon#[27=USB\r\n] 2006.173.20:51:00.50#ibcon#*before write, iclass 3, count 0 2006.173.20:51:00.50#ibcon#enter sib2, iclass 3, count 0 2006.173.20:51:00.50#ibcon#flushed, iclass 3, count 0 2006.173.20:51:00.50#ibcon#about to write, iclass 3, count 0 2006.173.20:51:00.50#ibcon#wrote, iclass 3, count 0 2006.173.20:51:00.50#ibcon#about to read 3, iclass 3, count 0 2006.173.20:51:00.53#ibcon#read 3, iclass 3, count 0 2006.173.20:51:00.53#ibcon#about to read 4, iclass 3, count 0 2006.173.20:51:00.53#ibcon#read 4, iclass 3, count 0 2006.173.20:51:00.53#ibcon#about to read 5, iclass 3, count 0 2006.173.20:51:00.53#ibcon#read 5, iclass 3, count 0 2006.173.20:51:00.53#ibcon#about to read 6, iclass 3, count 0 2006.173.20:51:00.53#ibcon#read 6, iclass 3, count 0 2006.173.20:51:00.53#ibcon#end of sib2, iclass 3, count 0 2006.173.20:51:00.53#ibcon#*after write, iclass 3, count 0 2006.173.20:51:00.53#ibcon#*before return 0, iclass 3, count 0 2006.173.20:51:00.53#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.20:51:00.53#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.20:51:00.53#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.20:51:00.53#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.20:51:00.53$vck44/vblo=3,649.99 2006.173.20:51:00.53#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.20:51:00.53#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.20:51:00.53#ibcon#ireg 17 cls_cnt 0 2006.173.20:51:00.53#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.20:51:00.53#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.20:51:00.53#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.20:51:00.53#ibcon#enter wrdev, iclass 5, count 0 2006.173.20:51:00.53#ibcon#first serial, iclass 5, count 0 2006.173.20:51:00.53#ibcon#enter sib2, iclass 5, count 0 2006.173.20:51:00.53#ibcon#flushed, iclass 5, count 0 2006.173.20:51:00.53#ibcon#about to write, iclass 5, count 0 2006.173.20:51:00.53#ibcon#wrote, iclass 5, count 0 2006.173.20:51:00.53#ibcon#about to read 3, iclass 5, count 0 2006.173.20:51:00.55#ibcon#read 3, iclass 5, count 0 2006.173.20:51:00.55#ibcon#about to read 4, iclass 5, count 0 2006.173.20:51:00.55#ibcon#read 4, iclass 5, count 0 2006.173.20:51:00.55#ibcon#about to read 5, iclass 5, count 0 2006.173.20:51:00.55#ibcon#read 5, iclass 5, count 0 2006.173.20:51:00.55#ibcon#about to read 6, iclass 5, count 0 2006.173.20:51:00.55#ibcon#read 6, iclass 5, count 0 2006.173.20:51:00.55#ibcon#end of sib2, iclass 5, count 0 2006.173.20:51:00.55#ibcon#*mode == 0, iclass 5, count 0 2006.173.20:51:00.55#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.20:51:00.55#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.20:51:00.55#ibcon#*before write, iclass 5, count 0 2006.173.20:51:00.55#ibcon#enter sib2, iclass 5, count 0 2006.173.20:51:00.55#ibcon#flushed, iclass 5, count 0 2006.173.20:51:00.55#ibcon#about to write, iclass 5, count 0 2006.173.20:51:00.55#ibcon#wrote, iclass 5, count 0 2006.173.20:51:00.55#ibcon#about to read 3, iclass 5, count 0 2006.173.20:51:00.59#ibcon#read 3, iclass 5, count 0 2006.173.20:51:00.59#ibcon#about to read 4, iclass 5, count 0 2006.173.20:51:00.59#ibcon#read 4, iclass 5, count 0 2006.173.20:51:00.59#ibcon#about to read 5, iclass 5, count 0 2006.173.20:51:00.59#ibcon#read 5, iclass 5, count 0 2006.173.20:51:00.59#ibcon#about to read 6, iclass 5, count 0 2006.173.20:51:00.59#ibcon#read 6, iclass 5, count 0 2006.173.20:51:00.59#ibcon#end of sib2, iclass 5, count 0 2006.173.20:51:00.59#ibcon#*after write, iclass 5, count 0 2006.173.20:51:00.59#ibcon#*before return 0, iclass 5, count 0 2006.173.20:51:00.59#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.20:51:00.59#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.20:51:00.59#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.20:51:00.59#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.20:51:00.59$vck44/vb=3,4 2006.173.20:51:00.59#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.173.20:51:00.59#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.173.20:51:00.59#ibcon#ireg 11 cls_cnt 2 2006.173.20:51:00.59#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.20:51:00.65#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.20:51:00.65#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.20:51:00.65#ibcon#enter wrdev, iclass 7, count 2 2006.173.20:51:00.65#ibcon#first serial, iclass 7, count 2 2006.173.20:51:00.65#ibcon#enter sib2, iclass 7, count 2 2006.173.20:51:00.65#ibcon#flushed, iclass 7, count 2 2006.173.20:51:00.65#ibcon#about to write, iclass 7, count 2 2006.173.20:51:00.65#ibcon#wrote, iclass 7, count 2 2006.173.20:51:00.65#ibcon#about to read 3, iclass 7, count 2 2006.173.20:51:00.67#ibcon#read 3, iclass 7, count 2 2006.173.20:51:00.67#ibcon#about to read 4, iclass 7, count 2 2006.173.20:51:00.67#ibcon#read 4, iclass 7, count 2 2006.173.20:51:00.67#ibcon#about to read 5, iclass 7, count 2 2006.173.20:51:00.67#ibcon#read 5, iclass 7, count 2 2006.173.20:51:00.67#ibcon#about to read 6, iclass 7, count 2 2006.173.20:51:00.67#ibcon#read 6, iclass 7, count 2 2006.173.20:51:00.67#ibcon#end of sib2, iclass 7, count 2 2006.173.20:51:00.67#ibcon#*mode == 0, iclass 7, count 2 2006.173.20:51:00.67#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.173.20:51:00.67#ibcon#[27=AT03-04\r\n] 2006.173.20:51:00.67#ibcon#*before write, iclass 7, count 2 2006.173.20:51:00.67#ibcon#enter sib2, iclass 7, count 2 2006.173.20:51:00.67#ibcon#flushed, iclass 7, count 2 2006.173.20:51:00.67#ibcon#about to write, iclass 7, count 2 2006.173.20:51:00.67#ibcon#wrote, iclass 7, count 2 2006.173.20:51:00.67#ibcon#about to read 3, iclass 7, count 2 2006.173.20:51:00.70#ibcon#read 3, iclass 7, count 2 2006.173.20:51:00.70#ibcon#about to read 4, iclass 7, count 2 2006.173.20:51:00.70#ibcon#read 4, iclass 7, count 2 2006.173.20:51:00.70#ibcon#about to read 5, iclass 7, count 2 2006.173.20:51:00.70#ibcon#read 5, iclass 7, count 2 2006.173.20:51:00.70#ibcon#about to read 6, iclass 7, count 2 2006.173.20:51:00.70#ibcon#read 6, iclass 7, count 2 2006.173.20:51:00.70#ibcon#end of sib2, iclass 7, count 2 2006.173.20:51:00.70#ibcon#*after write, iclass 7, count 2 2006.173.20:51:00.70#ibcon#*before return 0, iclass 7, count 2 2006.173.20:51:00.70#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.20:51:00.70#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.173.20:51:00.70#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.173.20:51:00.70#ibcon#ireg 7 cls_cnt 0 2006.173.20:51:00.70#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.20:51:00.82#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.20:51:00.82#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.20:51:00.82#ibcon#enter wrdev, iclass 7, count 0 2006.173.20:51:00.82#ibcon#first serial, iclass 7, count 0 2006.173.20:51:00.82#ibcon#enter sib2, iclass 7, count 0 2006.173.20:51:00.82#ibcon#flushed, iclass 7, count 0 2006.173.20:51:00.82#ibcon#about to write, iclass 7, count 0 2006.173.20:51:00.82#ibcon#wrote, iclass 7, count 0 2006.173.20:51:00.82#ibcon#about to read 3, iclass 7, count 0 2006.173.20:51:00.84#ibcon#read 3, iclass 7, count 0 2006.173.20:51:00.84#ibcon#about to read 4, iclass 7, count 0 2006.173.20:51:00.84#ibcon#read 4, iclass 7, count 0 2006.173.20:51:00.84#ibcon#about to read 5, iclass 7, count 0 2006.173.20:51:00.84#ibcon#read 5, iclass 7, count 0 2006.173.20:51:00.84#ibcon#about to read 6, iclass 7, count 0 2006.173.20:51:00.84#ibcon#read 6, iclass 7, count 0 2006.173.20:51:00.84#ibcon#end of sib2, iclass 7, count 0 2006.173.20:51:00.84#ibcon#*mode == 0, iclass 7, count 0 2006.173.20:51:00.84#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.20:51:00.84#ibcon#[27=USB\r\n] 2006.173.20:51:00.84#ibcon#*before write, iclass 7, count 0 2006.173.20:51:00.84#ibcon#enter sib2, iclass 7, count 0 2006.173.20:51:00.84#ibcon#flushed, iclass 7, count 0 2006.173.20:51:00.84#ibcon#about to write, iclass 7, count 0 2006.173.20:51:00.84#ibcon#wrote, iclass 7, count 0 2006.173.20:51:00.84#ibcon#about to read 3, iclass 7, count 0 2006.173.20:51:00.87#ibcon#read 3, iclass 7, count 0 2006.173.20:51:00.87#ibcon#about to read 4, iclass 7, count 0 2006.173.20:51:00.87#ibcon#read 4, iclass 7, count 0 2006.173.20:51:00.87#ibcon#about to read 5, iclass 7, count 0 2006.173.20:51:00.87#ibcon#read 5, iclass 7, count 0 2006.173.20:51:00.87#ibcon#about to read 6, iclass 7, count 0 2006.173.20:51:00.87#ibcon#read 6, iclass 7, count 0 2006.173.20:51:00.87#ibcon#end of sib2, iclass 7, count 0 2006.173.20:51:00.87#ibcon#*after write, iclass 7, count 0 2006.173.20:51:00.87#ibcon#*before return 0, iclass 7, count 0 2006.173.20:51:00.87#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.20:51:00.87#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.173.20:51:00.87#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.20:51:00.87#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.20:51:00.87$vck44/vblo=4,679.99 2006.173.20:51:00.87#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.20:51:00.87#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.20:51:00.87#ibcon#ireg 17 cls_cnt 0 2006.173.20:51:00.87#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.20:51:00.87#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.20:51:00.87#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.20:51:00.87#ibcon#enter wrdev, iclass 11, count 0 2006.173.20:51:00.87#ibcon#first serial, iclass 11, count 0 2006.173.20:51:00.87#ibcon#enter sib2, iclass 11, count 0 2006.173.20:51:00.87#ibcon#flushed, iclass 11, count 0 2006.173.20:51:00.87#ibcon#about to write, iclass 11, count 0 2006.173.20:51:00.87#ibcon#wrote, iclass 11, count 0 2006.173.20:51:00.87#ibcon#about to read 3, iclass 11, count 0 2006.173.20:51:00.89#ibcon#read 3, iclass 11, count 0 2006.173.20:51:00.89#ibcon#about to read 4, iclass 11, count 0 2006.173.20:51:00.89#ibcon#read 4, iclass 11, count 0 2006.173.20:51:00.89#ibcon#about to read 5, iclass 11, count 0 2006.173.20:51:00.89#ibcon#read 5, iclass 11, count 0 2006.173.20:51:00.89#ibcon#about to read 6, iclass 11, count 0 2006.173.20:51:00.89#ibcon#read 6, iclass 11, count 0 2006.173.20:51:00.89#ibcon#end of sib2, iclass 11, count 0 2006.173.20:51:00.89#ibcon#*mode == 0, iclass 11, count 0 2006.173.20:51:00.89#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.20:51:00.89#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.20:51:00.89#ibcon#*before write, iclass 11, count 0 2006.173.20:51:00.89#ibcon#enter sib2, iclass 11, count 0 2006.173.20:51:00.89#ibcon#flushed, iclass 11, count 0 2006.173.20:51:00.89#ibcon#about to write, iclass 11, count 0 2006.173.20:51:00.89#ibcon#wrote, iclass 11, count 0 2006.173.20:51:00.89#ibcon#about to read 3, iclass 11, count 0 2006.173.20:51:00.93#ibcon#read 3, iclass 11, count 0 2006.173.20:51:00.93#ibcon#about to read 4, iclass 11, count 0 2006.173.20:51:00.93#ibcon#read 4, iclass 11, count 0 2006.173.20:51:00.93#ibcon#about to read 5, iclass 11, count 0 2006.173.20:51:00.93#ibcon#read 5, iclass 11, count 0 2006.173.20:51:00.93#ibcon#about to read 6, iclass 11, count 0 2006.173.20:51:00.93#ibcon#read 6, iclass 11, count 0 2006.173.20:51:00.93#ibcon#end of sib2, iclass 11, count 0 2006.173.20:51:00.93#ibcon#*after write, iclass 11, count 0 2006.173.20:51:00.93#ibcon#*before return 0, iclass 11, count 0 2006.173.20:51:00.93#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.20:51:00.93#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.20:51:00.93#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.20:51:00.93#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.20:51:00.93$vck44/vb=4,4 2006.173.20:51:00.93#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.173.20:51:00.93#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.173.20:51:00.93#ibcon#ireg 11 cls_cnt 2 2006.173.20:51:00.93#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.20:51:00.99#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.20:51:00.99#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.20:51:00.99#ibcon#enter wrdev, iclass 13, count 2 2006.173.20:51:00.99#ibcon#first serial, iclass 13, count 2 2006.173.20:51:00.99#ibcon#enter sib2, iclass 13, count 2 2006.173.20:51:00.99#ibcon#flushed, iclass 13, count 2 2006.173.20:51:00.99#ibcon#about to write, iclass 13, count 2 2006.173.20:51:00.99#ibcon#wrote, iclass 13, count 2 2006.173.20:51:00.99#ibcon#about to read 3, iclass 13, count 2 2006.173.20:51:01.01#ibcon#read 3, iclass 13, count 2 2006.173.20:51:01.01#ibcon#about to read 4, iclass 13, count 2 2006.173.20:51:01.01#ibcon#read 4, iclass 13, count 2 2006.173.20:51:01.01#ibcon#about to read 5, iclass 13, count 2 2006.173.20:51:01.01#ibcon#read 5, iclass 13, count 2 2006.173.20:51:01.01#ibcon#about to read 6, iclass 13, count 2 2006.173.20:51:01.01#ibcon#read 6, iclass 13, count 2 2006.173.20:51:01.01#ibcon#end of sib2, iclass 13, count 2 2006.173.20:51:01.01#ibcon#*mode == 0, iclass 13, count 2 2006.173.20:51:01.01#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.173.20:51:01.01#ibcon#[27=AT04-04\r\n] 2006.173.20:51:01.01#ibcon#*before write, iclass 13, count 2 2006.173.20:51:01.01#ibcon#enter sib2, iclass 13, count 2 2006.173.20:51:01.01#ibcon#flushed, iclass 13, count 2 2006.173.20:51:01.01#ibcon#about to write, iclass 13, count 2 2006.173.20:51:01.01#ibcon#wrote, iclass 13, count 2 2006.173.20:51:01.01#ibcon#about to read 3, iclass 13, count 2 2006.173.20:51:01.04#ibcon#read 3, iclass 13, count 2 2006.173.20:51:01.04#ibcon#about to read 4, iclass 13, count 2 2006.173.20:51:01.04#ibcon#read 4, iclass 13, count 2 2006.173.20:51:01.04#ibcon#about to read 5, iclass 13, count 2 2006.173.20:51:01.04#ibcon#read 5, iclass 13, count 2 2006.173.20:51:01.04#ibcon#about to read 6, iclass 13, count 2 2006.173.20:51:01.04#ibcon#read 6, iclass 13, count 2 2006.173.20:51:01.04#ibcon#end of sib2, iclass 13, count 2 2006.173.20:51:01.04#ibcon#*after write, iclass 13, count 2 2006.173.20:51:01.04#ibcon#*before return 0, iclass 13, count 2 2006.173.20:51:01.04#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.20:51:01.04#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.173.20:51:01.04#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.173.20:51:01.04#ibcon#ireg 7 cls_cnt 0 2006.173.20:51:01.04#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.20:51:01.16#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.20:51:01.16#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.20:51:01.16#ibcon#enter wrdev, iclass 13, count 0 2006.173.20:51:01.16#ibcon#first serial, iclass 13, count 0 2006.173.20:51:01.16#ibcon#enter sib2, iclass 13, count 0 2006.173.20:51:01.16#ibcon#flushed, iclass 13, count 0 2006.173.20:51:01.16#ibcon#about to write, iclass 13, count 0 2006.173.20:51:01.16#ibcon#wrote, iclass 13, count 0 2006.173.20:51:01.16#ibcon#about to read 3, iclass 13, count 0 2006.173.20:51:01.18#ibcon#read 3, iclass 13, count 0 2006.173.20:51:01.18#ibcon#about to read 4, iclass 13, count 0 2006.173.20:51:01.18#ibcon#read 4, iclass 13, count 0 2006.173.20:51:01.18#ibcon#about to read 5, iclass 13, count 0 2006.173.20:51:01.18#ibcon#read 5, iclass 13, count 0 2006.173.20:51:01.18#ibcon#about to read 6, iclass 13, count 0 2006.173.20:51:01.18#ibcon#read 6, iclass 13, count 0 2006.173.20:51:01.18#ibcon#end of sib2, iclass 13, count 0 2006.173.20:51:01.18#ibcon#*mode == 0, iclass 13, count 0 2006.173.20:51:01.18#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.20:51:01.18#ibcon#[27=USB\r\n] 2006.173.20:51:01.18#ibcon#*before write, iclass 13, count 0 2006.173.20:51:01.18#ibcon#enter sib2, iclass 13, count 0 2006.173.20:51:01.18#ibcon#flushed, iclass 13, count 0 2006.173.20:51:01.18#ibcon#about to write, iclass 13, count 0 2006.173.20:51:01.18#ibcon#wrote, iclass 13, count 0 2006.173.20:51:01.18#ibcon#about to read 3, iclass 13, count 0 2006.173.20:51:01.21#ibcon#read 3, iclass 13, count 0 2006.173.20:51:01.21#ibcon#about to read 4, iclass 13, count 0 2006.173.20:51:01.21#ibcon#read 4, iclass 13, count 0 2006.173.20:51:01.21#ibcon#about to read 5, iclass 13, count 0 2006.173.20:51:01.21#ibcon#read 5, iclass 13, count 0 2006.173.20:51:01.21#ibcon#about to read 6, iclass 13, count 0 2006.173.20:51:01.21#ibcon#read 6, iclass 13, count 0 2006.173.20:51:01.21#ibcon#end of sib2, iclass 13, count 0 2006.173.20:51:01.21#ibcon#*after write, iclass 13, count 0 2006.173.20:51:01.21#ibcon#*before return 0, iclass 13, count 0 2006.173.20:51:01.21#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.20:51:01.21#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.173.20:51:01.21#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.20:51:01.21#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.20:51:01.21$vck44/vblo=5,709.99 2006.173.20:51:01.21#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.20:51:01.21#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.20:51:01.21#ibcon#ireg 17 cls_cnt 0 2006.173.20:51:01.21#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.20:51:01.21#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.20:51:01.21#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.20:51:01.21#ibcon#enter wrdev, iclass 15, count 0 2006.173.20:51:01.21#ibcon#first serial, iclass 15, count 0 2006.173.20:51:01.21#ibcon#enter sib2, iclass 15, count 0 2006.173.20:51:01.21#ibcon#flushed, iclass 15, count 0 2006.173.20:51:01.21#ibcon#about to write, iclass 15, count 0 2006.173.20:51:01.21#ibcon#wrote, iclass 15, count 0 2006.173.20:51:01.21#ibcon#about to read 3, iclass 15, count 0 2006.173.20:51:01.23#ibcon#read 3, iclass 15, count 0 2006.173.20:51:01.23#ibcon#about to read 4, iclass 15, count 0 2006.173.20:51:01.23#ibcon#read 4, iclass 15, count 0 2006.173.20:51:01.23#ibcon#about to read 5, iclass 15, count 0 2006.173.20:51:01.23#ibcon#read 5, iclass 15, count 0 2006.173.20:51:01.23#ibcon#about to read 6, iclass 15, count 0 2006.173.20:51:01.23#ibcon#read 6, iclass 15, count 0 2006.173.20:51:01.23#ibcon#end of sib2, iclass 15, count 0 2006.173.20:51:01.23#ibcon#*mode == 0, iclass 15, count 0 2006.173.20:51:01.23#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.20:51:01.23#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.20:51:01.23#ibcon#*before write, iclass 15, count 0 2006.173.20:51:01.23#ibcon#enter sib2, iclass 15, count 0 2006.173.20:51:01.23#ibcon#flushed, iclass 15, count 0 2006.173.20:51:01.23#ibcon#about to write, iclass 15, count 0 2006.173.20:51:01.23#ibcon#wrote, iclass 15, count 0 2006.173.20:51:01.23#ibcon#about to read 3, iclass 15, count 0 2006.173.20:51:01.27#ibcon#read 3, iclass 15, count 0 2006.173.20:51:01.27#ibcon#about to read 4, iclass 15, count 0 2006.173.20:51:01.27#ibcon#read 4, iclass 15, count 0 2006.173.20:51:01.27#ibcon#about to read 5, iclass 15, count 0 2006.173.20:51:01.27#ibcon#read 5, iclass 15, count 0 2006.173.20:51:01.27#ibcon#about to read 6, iclass 15, count 0 2006.173.20:51:01.27#ibcon#read 6, iclass 15, count 0 2006.173.20:51:01.27#ibcon#end of sib2, iclass 15, count 0 2006.173.20:51:01.27#ibcon#*after write, iclass 15, count 0 2006.173.20:51:01.27#ibcon#*before return 0, iclass 15, count 0 2006.173.20:51:01.27#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.20:51:01.27#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.20:51:01.27#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.20:51:01.27#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.20:51:01.27$vck44/vb=5,4 2006.173.20:51:01.27#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.20:51:01.27#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.20:51:01.27#ibcon#ireg 11 cls_cnt 2 2006.173.20:51:01.27#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.20:51:01.33#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.20:51:01.33#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.20:51:01.33#ibcon#enter wrdev, iclass 17, count 2 2006.173.20:51:01.33#ibcon#first serial, iclass 17, count 2 2006.173.20:51:01.33#ibcon#enter sib2, iclass 17, count 2 2006.173.20:51:01.33#ibcon#flushed, iclass 17, count 2 2006.173.20:51:01.33#ibcon#about to write, iclass 17, count 2 2006.173.20:51:01.33#ibcon#wrote, iclass 17, count 2 2006.173.20:51:01.33#ibcon#about to read 3, iclass 17, count 2 2006.173.20:51:01.35#ibcon#read 3, iclass 17, count 2 2006.173.20:51:01.35#ibcon#about to read 4, iclass 17, count 2 2006.173.20:51:01.35#ibcon#read 4, iclass 17, count 2 2006.173.20:51:01.35#ibcon#about to read 5, iclass 17, count 2 2006.173.20:51:01.35#ibcon#read 5, iclass 17, count 2 2006.173.20:51:01.35#ibcon#about to read 6, iclass 17, count 2 2006.173.20:51:01.35#ibcon#read 6, iclass 17, count 2 2006.173.20:51:01.35#ibcon#end of sib2, iclass 17, count 2 2006.173.20:51:01.35#ibcon#*mode == 0, iclass 17, count 2 2006.173.20:51:01.35#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.20:51:01.35#ibcon#[27=AT05-04\r\n] 2006.173.20:51:01.35#ibcon#*before write, iclass 17, count 2 2006.173.20:51:01.35#ibcon#enter sib2, iclass 17, count 2 2006.173.20:51:01.35#ibcon#flushed, iclass 17, count 2 2006.173.20:51:01.35#ibcon#about to write, iclass 17, count 2 2006.173.20:51:01.35#ibcon#wrote, iclass 17, count 2 2006.173.20:51:01.35#ibcon#about to read 3, iclass 17, count 2 2006.173.20:51:01.38#ibcon#read 3, iclass 17, count 2 2006.173.20:51:01.38#ibcon#about to read 4, iclass 17, count 2 2006.173.20:51:01.38#ibcon#read 4, iclass 17, count 2 2006.173.20:51:01.38#ibcon#about to read 5, iclass 17, count 2 2006.173.20:51:01.38#ibcon#read 5, iclass 17, count 2 2006.173.20:51:01.38#ibcon#about to read 6, iclass 17, count 2 2006.173.20:51:01.38#ibcon#read 6, iclass 17, count 2 2006.173.20:51:01.38#ibcon#end of sib2, iclass 17, count 2 2006.173.20:51:01.38#ibcon#*after write, iclass 17, count 2 2006.173.20:51:01.38#ibcon#*before return 0, iclass 17, count 2 2006.173.20:51:01.38#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.20:51:01.38#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.20:51:01.38#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.20:51:01.38#ibcon#ireg 7 cls_cnt 0 2006.173.20:51:01.38#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.20:51:01.50#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.20:51:01.50#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.20:51:01.50#ibcon#enter wrdev, iclass 17, count 0 2006.173.20:51:01.50#ibcon#first serial, iclass 17, count 0 2006.173.20:51:01.50#ibcon#enter sib2, iclass 17, count 0 2006.173.20:51:01.50#ibcon#flushed, iclass 17, count 0 2006.173.20:51:01.50#ibcon#about to write, iclass 17, count 0 2006.173.20:51:01.50#ibcon#wrote, iclass 17, count 0 2006.173.20:51:01.50#ibcon#about to read 3, iclass 17, count 0 2006.173.20:51:01.52#ibcon#read 3, iclass 17, count 0 2006.173.20:51:01.52#ibcon#about to read 4, iclass 17, count 0 2006.173.20:51:01.52#ibcon#read 4, iclass 17, count 0 2006.173.20:51:01.52#ibcon#about to read 5, iclass 17, count 0 2006.173.20:51:01.52#ibcon#read 5, iclass 17, count 0 2006.173.20:51:01.52#ibcon#about to read 6, iclass 17, count 0 2006.173.20:51:01.52#ibcon#read 6, iclass 17, count 0 2006.173.20:51:01.52#ibcon#end of sib2, iclass 17, count 0 2006.173.20:51:01.52#ibcon#*mode == 0, iclass 17, count 0 2006.173.20:51:01.52#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.20:51:01.52#ibcon#[27=USB\r\n] 2006.173.20:51:01.52#ibcon#*before write, iclass 17, count 0 2006.173.20:51:01.52#ibcon#enter sib2, iclass 17, count 0 2006.173.20:51:01.52#ibcon#flushed, iclass 17, count 0 2006.173.20:51:01.52#ibcon#about to write, iclass 17, count 0 2006.173.20:51:01.52#ibcon#wrote, iclass 17, count 0 2006.173.20:51:01.52#ibcon#about to read 3, iclass 17, count 0 2006.173.20:51:01.55#ibcon#read 3, iclass 17, count 0 2006.173.20:51:01.55#ibcon#about to read 4, iclass 17, count 0 2006.173.20:51:01.55#ibcon#read 4, iclass 17, count 0 2006.173.20:51:01.55#ibcon#about to read 5, iclass 17, count 0 2006.173.20:51:01.55#ibcon#read 5, iclass 17, count 0 2006.173.20:51:01.55#ibcon#about to read 6, iclass 17, count 0 2006.173.20:51:01.55#ibcon#read 6, iclass 17, count 0 2006.173.20:51:01.55#ibcon#end of sib2, iclass 17, count 0 2006.173.20:51:01.55#ibcon#*after write, iclass 17, count 0 2006.173.20:51:01.55#ibcon#*before return 0, iclass 17, count 0 2006.173.20:51:01.55#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.20:51:01.55#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.20:51:01.55#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.20:51:01.55#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.20:51:01.55$vck44/vblo=6,719.99 2006.173.20:51:01.55#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.20:51:01.55#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.20:51:01.55#ibcon#ireg 17 cls_cnt 0 2006.173.20:51:01.55#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.20:51:01.55#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.20:51:01.55#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.20:51:01.55#ibcon#enter wrdev, iclass 19, count 0 2006.173.20:51:01.55#ibcon#first serial, iclass 19, count 0 2006.173.20:51:01.55#ibcon#enter sib2, iclass 19, count 0 2006.173.20:51:01.55#ibcon#flushed, iclass 19, count 0 2006.173.20:51:01.55#ibcon#about to write, iclass 19, count 0 2006.173.20:51:01.55#ibcon#wrote, iclass 19, count 0 2006.173.20:51:01.55#ibcon#about to read 3, iclass 19, count 0 2006.173.20:51:01.57#ibcon#read 3, iclass 19, count 0 2006.173.20:51:01.57#ibcon#about to read 4, iclass 19, count 0 2006.173.20:51:01.57#ibcon#read 4, iclass 19, count 0 2006.173.20:51:01.57#ibcon#about to read 5, iclass 19, count 0 2006.173.20:51:01.57#ibcon#read 5, iclass 19, count 0 2006.173.20:51:01.57#ibcon#about to read 6, iclass 19, count 0 2006.173.20:51:01.57#ibcon#read 6, iclass 19, count 0 2006.173.20:51:01.57#ibcon#end of sib2, iclass 19, count 0 2006.173.20:51:01.57#ibcon#*mode == 0, iclass 19, count 0 2006.173.20:51:01.57#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.20:51:01.57#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.20:51:01.57#ibcon#*before write, iclass 19, count 0 2006.173.20:51:01.57#ibcon#enter sib2, iclass 19, count 0 2006.173.20:51:01.57#ibcon#flushed, iclass 19, count 0 2006.173.20:51:01.57#ibcon#about to write, iclass 19, count 0 2006.173.20:51:01.57#ibcon#wrote, iclass 19, count 0 2006.173.20:51:01.57#ibcon#about to read 3, iclass 19, count 0 2006.173.20:51:01.61#ibcon#read 3, iclass 19, count 0 2006.173.20:51:01.61#ibcon#about to read 4, iclass 19, count 0 2006.173.20:51:01.61#ibcon#read 4, iclass 19, count 0 2006.173.20:51:01.61#ibcon#about to read 5, iclass 19, count 0 2006.173.20:51:01.61#ibcon#read 5, iclass 19, count 0 2006.173.20:51:01.61#ibcon#about to read 6, iclass 19, count 0 2006.173.20:51:01.61#ibcon#read 6, iclass 19, count 0 2006.173.20:51:01.61#ibcon#end of sib2, iclass 19, count 0 2006.173.20:51:01.61#ibcon#*after write, iclass 19, count 0 2006.173.20:51:01.61#ibcon#*before return 0, iclass 19, count 0 2006.173.20:51:01.61#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.20:51:01.61#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.20:51:01.61#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.20:51:01.61#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.20:51:01.61$vck44/vb=6,4 2006.173.20:51:01.61#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.20:51:01.61#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.20:51:01.61#ibcon#ireg 11 cls_cnt 2 2006.173.20:51:01.61#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.20:51:01.67#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.20:51:01.67#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.20:51:01.67#ibcon#enter wrdev, iclass 21, count 2 2006.173.20:51:01.67#ibcon#first serial, iclass 21, count 2 2006.173.20:51:01.67#ibcon#enter sib2, iclass 21, count 2 2006.173.20:51:01.67#ibcon#flushed, iclass 21, count 2 2006.173.20:51:01.67#ibcon#about to write, iclass 21, count 2 2006.173.20:51:01.67#ibcon#wrote, iclass 21, count 2 2006.173.20:51:01.67#ibcon#about to read 3, iclass 21, count 2 2006.173.20:51:01.69#ibcon#read 3, iclass 21, count 2 2006.173.20:51:01.69#ibcon#about to read 4, iclass 21, count 2 2006.173.20:51:01.69#ibcon#read 4, iclass 21, count 2 2006.173.20:51:01.69#ibcon#about to read 5, iclass 21, count 2 2006.173.20:51:01.69#ibcon#read 5, iclass 21, count 2 2006.173.20:51:01.69#ibcon#about to read 6, iclass 21, count 2 2006.173.20:51:01.69#ibcon#read 6, iclass 21, count 2 2006.173.20:51:01.69#ibcon#end of sib2, iclass 21, count 2 2006.173.20:51:01.69#ibcon#*mode == 0, iclass 21, count 2 2006.173.20:51:01.69#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.20:51:01.69#ibcon#[27=AT06-04\r\n] 2006.173.20:51:01.69#ibcon#*before write, iclass 21, count 2 2006.173.20:51:01.69#ibcon#enter sib2, iclass 21, count 2 2006.173.20:51:01.69#ibcon#flushed, iclass 21, count 2 2006.173.20:51:01.69#ibcon#about to write, iclass 21, count 2 2006.173.20:51:01.69#ibcon#wrote, iclass 21, count 2 2006.173.20:51:01.69#ibcon#about to read 3, iclass 21, count 2 2006.173.20:51:01.72#ibcon#read 3, iclass 21, count 2 2006.173.20:51:01.72#ibcon#about to read 4, iclass 21, count 2 2006.173.20:51:01.72#ibcon#read 4, iclass 21, count 2 2006.173.20:51:01.72#ibcon#about to read 5, iclass 21, count 2 2006.173.20:51:01.72#ibcon#read 5, iclass 21, count 2 2006.173.20:51:01.72#ibcon#about to read 6, iclass 21, count 2 2006.173.20:51:01.72#ibcon#read 6, iclass 21, count 2 2006.173.20:51:01.72#ibcon#end of sib2, iclass 21, count 2 2006.173.20:51:01.72#ibcon#*after write, iclass 21, count 2 2006.173.20:51:01.72#ibcon#*before return 0, iclass 21, count 2 2006.173.20:51:01.72#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.20:51:01.72#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.20:51:01.72#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.20:51:01.72#ibcon#ireg 7 cls_cnt 0 2006.173.20:51:01.72#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.20:51:01.84#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.20:51:01.84#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.20:51:01.84#ibcon#enter wrdev, iclass 21, count 0 2006.173.20:51:01.84#ibcon#first serial, iclass 21, count 0 2006.173.20:51:01.84#ibcon#enter sib2, iclass 21, count 0 2006.173.20:51:01.84#ibcon#flushed, iclass 21, count 0 2006.173.20:51:01.84#ibcon#about to write, iclass 21, count 0 2006.173.20:51:01.84#ibcon#wrote, iclass 21, count 0 2006.173.20:51:01.84#ibcon#about to read 3, iclass 21, count 0 2006.173.20:51:01.86#ibcon#read 3, iclass 21, count 0 2006.173.20:51:01.86#ibcon#about to read 4, iclass 21, count 0 2006.173.20:51:01.86#ibcon#read 4, iclass 21, count 0 2006.173.20:51:01.86#ibcon#about to read 5, iclass 21, count 0 2006.173.20:51:01.86#ibcon#read 5, iclass 21, count 0 2006.173.20:51:01.86#ibcon#about to read 6, iclass 21, count 0 2006.173.20:51:01.86#ibcon#read 6, iclass 21, count 0 2006.173.20:51:01.86#ibcon#end of sib2, iclass 21, count 0 2006.173.20:51:01.86#ibcon#*mode == 0, iclass 21, count 0 2006.173.20:51:01.86#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.20:51:01.86#ibcon#[27=USB\r\n] 2006.173.20:51:01.86#ibcon#*before write, iclass 21, count 0 2006.173.20:51:01.86#ibcon#enter sib2, iclass 21, count 0 2006.173.20:51:01.86#ibcon#flushed, iclass 21, count 0 2006.173.20:51:01.86#ibcon#about to write, iclass 21, count 0 2006.173.20:51:01.86#ibcon#wrote, iclass 21, count 0 2006.173.20:51:01.86#ibcon#about to read 3, iclass 21, count 0 2006.173.20:51:01.89#ibcon#read 3, iclass 21, count 0 2006.173.20:51:01.89#ibcon#about to read 4, iclass 21, count 0 2006.173.20:51:01.89#ibcon#read 4, iclass 21, count 0 2006.173.20:51:01.89#ibcon#about to read 5, iclass 21, count 0 2006.173.20:51:01.89#ibcon#read 5, iclass 21, count 0 2006.173.20:51:01.89#ibcon#about to read 6, iclass 21, count 0 2006.173.20:51:01.89#ibcon#read 6, iclass 21, count 0 2006.173.20:51:01.89#ibcon#end of sib2, iclass 21, count 0 2006.173.20:51:01.89#ibcon#*after write, iclass 21, count 0 2006.173.20:51:01.89#ibcon#*before return 0, iclass 21, count 0 2006.173.20:51:01.89#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.20:51:01.89#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.20:51:01.89#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.20:51:01.89#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.20:51:01.89$vck44/vblo=7,734.99 2006.173.20:51:01.89#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.20:51:01.89#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.20:51:01.89#ibcon#ireg 17 cls_cnt 0 2006.173.20:51:01.89#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.20:51:01.89#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.20:51:01.89#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.20:51:01.89#ibcon#enter wrdev, iclass 23, count 0 2006.173.20:51:01.89#ibcon#first serial, iclass 23, count 0 2006.173.20:51:01.89#ibcon#enter sib2, iclass 23, count 0 2006.173.20:51:01.89#ibcon#flushed, iclass 23, count 0 2006.173.20:51:01.89#ibcon#about to write, iclass 23, count 0 2006.173.20:51:01.89#ibcon#wrote, iclass 23, count 0 2006.173.20:51:01.89#ibcon#about to read 3, iclass 23, count 0 2006.173.20:51:01.91#ibcon#read 3, iclass 23, count 0 2006.173.20:51:01.91#ibcon#about to read 4, iclass 23, count 0 2006.173.20:51:01.91#ibcon#read 4, iclass 23, count 0 2006.173.20:51:01.91#ibcon#about to read 5, iclass 23, count 0 2006.173.20:51:01.91#ibcon#read 5, iclass 23, count 0 2006.173.20:51:01.91#ibcon#about to read 6, iclass 23, count 0 2006.173.20:51:01.91#ibcon#read 6, iclass 23, count 0 2006.173.20:51:01.91#ibcon#end of sib2, iclass 23, count 0 2006.173.20:51:01.91#ibcon#*mode == 0, iclass 23, count 0 2006.173.20:51:01.91#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.20:51:01.91#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.20:51:01.91#ibcon#*before write, iclass 23, count 0 2006.173.20:51:01.91#ibcon#enter sib2, iclass 23, count 0 2006.173.20:51:01.91#ibcon#flushed, iclass 23, count 0 2006.173.20:51:01.91#ibcon#about to write, iclass 23, count 0 2006.173.20:51:01.91#ibcon#wrote, iclass 23, count 0 2006.173.20:51:01.91#ibcon#about to read 3, iclass 23, count 0 2006.173.20:51:01.95#ibcon#read 3, iclass 23, count 0 2006.173.20:51:01.95#ibcon#about to read 4, iclass 23, count 0 2006.173.20:51:01.95#ibcon#read 4, iclass 23, count 0 2006.173.20:51:01.95#ibcon#about to read 5, iclass 23, count 0 2006.173.20:51:01.95#ibcon#read 5, iclass 23, count 0 2006.173.20:51:01.95#ibcon#about to read 6, iclass 23, count 0 2006.173.20:51:01.95#ibcon#read 6, iclass 23, count 0 2006.173.20:51:01.95#ibcon#end of sib2, iclass 23, count 0 2006.173.20:51:01.95#ibcon#*after write, iclass 23, count 0 2006.173.20:51:01.95#ibcon#*before return 0, iclass 23, count 0 2006.173.20:51:01.95#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.20:51:01.95#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.20:51:01.95#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.20:51:01.95#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.20:51:01.95$vck44/vb=7,4 2006.173.20:51:01.95#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.20:51:01.95#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.20:51:01.95#ibcon#ireg 11 cls_cnt 2 2006.173.20:51:01.95#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.20:51:02.01#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.20:51:02.01#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.20:51:02.01#ibcon#enter wrdev, iclass 25, count 2 2006.173.20:51:02.01#ibcon#first serial, iclass 25, count 2 2006.173.20:51:02.01#ibcon#enter sib2, iclass 25, count 2 2006.173.20:51:02.01#ibcon#flushed, iclass 25, count 2 2006.173.20:51:02.01#ibcon#about to write, iclass 25, count 2 2006.173.20:51:02.01#ibcon#wrote, iclass 25, count 2 2006.173.20:51:02.01#ibcon#about to read 3, iclass 25, count 2 2006.173.20:51:02.03#ibcon#read 3, iclass 25, count 2 2006.173.20:51:02.03#ibcon#about to read 4, iclass 25, count 2 2006.173.20:51:02.03#ibcon#read 4, iclass 25, count 2 2006.173.20:51:02.03#ibcon#about to read 5, iclass 25, count 2 2006.173.20:51:02.03#ibcon#read 5, iclass 25, count 2 2006.173.20:51:02.03#ibcon#about to read 6, iclass 25, count 2 2006.173.20:51:02.03#ibcon#read 6, iclass 25, count 2 2006.173.20:51:02.03#ibcon#end of sib2, iclass 25, count 2 2006.173.20:51:02.03#ibcon#*mode == 0, iclass 25, count 2 2006.173.20:51:02.03#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.20:51:02.03#ibcon#[27=AT07-04\r\n] 2006.173.20:51:02.03#ibcon#*before write, iclass 25, count 2 2006.173.20:51:02.03#ibcon#enter sib2, iclass 25, count 2 2006.173.20:51:02.03#ibcon#flushed, iclass 25, count 2 2006.173.20:51:02.03#ibcon#about to write, iclass 25, count 2 2006.173.20:51:02.03#ibcon#wrote, iclass 25, count 2 2006.173.20:51:02.03#ibcon#about to read 3, iclass 25, count 2 2006.173.20:51:02.06#ibcon#read 3, iclass 25, count 2 2006.173.20:51:02.06#ibcon#about to read 4, iclass 25, count 2 2006.173.20:51:02.06#ibcon#read 4, iclass 25, count 2 2006.173.20:51:02.06#ibcon#about to read 5, iclass 25, count 2 2006.173.20:51:02.06#ibcon#read 5, iclass 25, count 2 2006.173.20:51:02.06#ibcon#about to read 6, iclass 25, count 2 2006.173.20:51:02.06#ibcon#read 6, iclass 25, count 2 2006.173.20:51:02.06#ibcon#end of sib2, iclass 25, count 2 2006.173.20:51:02.06#ibcon#*after write, iclass 25, count 2 2006.173.20:51:02.06#ibcon#*before return 0, iclass 25, count 2 2006.173.20:51:02.06#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.20:51:02.06#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.20:51:02.06#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.20:51:02.06#ibcon#ireg 7 cls_cnt 0 2006.173.20:51:02.06#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.20:51:02.18#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.20:51:02.18#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.20:51:02.18#ibcon#enter wrdev, iclass 25, count 0 2006.173.20:51:02.18#ibcon#first serial, iclass 25, count 0 2006.173.20:51:02.18#ibcon#enter sib2, iclass 25, count 0 2006.173.20:51:02.18#ibcon#flushed, iclass 25, count 0 2006.173.20:51:02.18#ibcon#about to write, iclass 25, count 0 2006.173.20:51:02.18#ibcon#wrote, iclass 25, count 0 2006.173.20:51:02.18#ibcon#about to read 3, iclass 25, count 0 2006.173.20:51:02.20#ibcon#read 3, iclass 25, count 0 2006.173.20:51:02.20#ibcon#about to read 4, iclass 25, count 0 2006.173.20:51:02.20#ibcon#read 4, iclass 25, count 0 2006.173.20:51:02.20#ibcon#about to read 5, iclass 25, count 0 2006.173.20:51:02.20#ibcon#read 5, iclass 25, count 0 2006.173.20:51:02.20#ibcon#about to read 6, iclass 25, count 0 2006.173.20:51:02.20#ibcon#read 6, iclass 25, count 0 2006.173.20:51:02.20#ibcon#end of sib2, iclass 25, count 0 2006.173.20:51:02.20#ibcon#*mode == 0, iclass 25, count 0 2006.173.20:51:02.20#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.20:51:02.20#ibcon#[27=USB\r\n] 2006.173.20:51:02.20#ibcon#*before write, iclass 25, count 0 2006.173.20:51:02.20#ibcon#enter sib2, iclass 25, count 0 2006.173.20:51:02.20#ibcon#flushed, iclass 25, count 0 2006.173.20:51:02.20#ibcon#about to write, iclass 25, count 0 2006.173.20:51:02.20#ibcon#wrote, iclass 25, count 0 2006.173.20:51:02.20#ibcon#about to read 3, iclass 25, count 0 2006.173.20:51:02.23#ibcon#read 3, iclass 25, count 0 2006.173.20:51:02.23#ibcon#about to read 4, iclass 25, count 0 2006.173.20:51:02.23#ibcon#read 4, iclass 25, count 0 2006.173.20:51:02.23#ibcon#about to read 5, iclass 25, count 0 2006.173.20:51:02.23#ibcon#read 5, iclass 25, count 0 2006.173.20:51:02.23#ibcon#about to read 6, iclass 25, count 0 2006.173.20:51:02.23#ibcon#read 6, iclass 25, count 0 2006.173.20:51:02.23#ibcon#end of sib2, iclass 25, count 0 2006.173.20:51:02.23#ibcon#*after write, iclass 25, count 0 2006.173.20:51:02.23#ibcon#*before return 0, iclass 25, count 0 2006.173.20:51:02.23#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.20:51:02.23#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.20:51:02.23#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.20:51:02.23#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.20:51:02.23$vck44/vblo=8,744.99 2006.173.20:51:02.23#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.20:51:02.23#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.20:51:02.23#ibcon#ireg 17 cls_cnt 0 2006.173.20:51:02.23#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.20:51:02.23#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.20:51:02.23#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.20:51:02.23#ibcon#enter wrdev, iclass 27, count 0 2006.173.20:51:02.23#ibcon#first serial, iclass 27, count 0 2006.173.20:51:02.23#ibcon#enter sib2, iclass 27, count 0 2006.173.20:51:02.23#ibcon#flushed, iclass 27, count 0 2006.173.20:51:02.23#ibcon#about to write, iclass 27, count 0 2006.173.20:51:02.23#ibcon#wrote, iclass 27, count 0 2006.173.20:51:02.23#ibcon#about to read 3, iclass 27, count 0 2006.173.20:51:02.25#ibcon#read 3, iclass 27, count 0 2006.173.20:51:02.25#ibcon#about to read 4, iclass 27, count 0 2006.173.20:51:02.25#ibcon#read 4, iclass 27, count 0 2006.173.20:51:02.25#ibcon#about to read 5, iclass 27, count 0 2006.173.20:51:02.25#ibcon#read 5, iclass 27, count 0 2006.173.20:51:02.25#ibcon#about to read 6, iclass 27, count 0 2006.173.20:51:02.25#ibcon#read 6, iclass 27, count 0 2006.173.20:51:02.25#ibcon#end of sib2, iclass 27, count 0 2006.173.20:51:02.25#ibcon#*mode == 0, iclass 27, count 0 2006.173.20:51:02.25#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.20:51:02.25#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.20:51:02.25#ibcon#*before write, iclass 27, count 0 2006.173.20:51:02.25#ibcon#enter sib2, iclass 27, count 0 2006.173.20:51:02.25#ibcon#flushed, iclass 27, count 0 2006.173.20:51:02.25#ibcon#about to write, iclass 27, count 0 2006.173.20:51:02.25#ibcon#wrote, iclass 27, count 0 2006.173.20:51:02.25#ibcon#about to read 3, iclass 27, count 0 2006.173.20:51:02.29#ibcon#read 3, iclass 27, count 0 2006.173.20:51:02.29#ibcon#about to read 4, iclass 27, count 0 2006.173.20:51:02.29#ibcon#read 4, iclass 27, count 0 2006.173.20:51:02.29#ibcon#about to read 5, iclass 27, count 0 2006.173.20:51:02.29#ibcon#read 5, iclass 27, count 0 2006.173.20:51:02.29#ibcon#about to read 6, iclass 27, count 0 2006.173.20:51:02.29#ibcon#read 6, iclass 27, count 0 2006.173.20:51:02.29#ibcon#end of sib2, iclass 27, count 0 2006.173.20:51:02.29#ibcon#*after write, iclass 27, count 0 2006.173.20:51:02.29#ibcon#*before return 0, iclass 27, count 0 2006.173.20:51:02.29#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.20:51:02.29#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.20:51:02.29#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.20:51:02.29#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.20:51:02.29$vck44/vb=8,4 2006.173.20:51:02.29#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.20:51:02.29#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.20:51:02.29#ibcon#ireg 11 cls_cnt 2 2006.173.20:51:02.29#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.20:51:02.35#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.20:51:02.35#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.20:51:02.35#ibcon#enter wrdev, iclass 29, count 2 2006.173.20:51:02.35#ibcon#first serial, iclass 29, count 2 2006.173.20:51:02.35#ibcon#enter sib2, iclass 29, count 2 2006.173.20:51:02.35#ibcon#flushed, iclass 29, count 2 2006.173.20:51:02.35#ibcon#about to write, iclass 29, count 2 2006.173.20:51:02.35#ibcon#wrote, iclass 29, count 2 2006.173.20:51:02.35#ibcon#about to read 3, iclass 29, count 2 2006.173.20:51:02.37#ibcon#read 3, iclass 29, count 2 2006.173.20:51:02.37#ibcon#about to read 4, iclass 29, count 2 2006.173.20:51:02.37#ibcon#read 4, iclass 29, count 2 2006.173.20:51:02.37#ibcon#about to read 5, iclass 29, count 2 2006.173.20:51:02.37#ibcon#read 5, iclass 29, count 2 2006.173.20:51:02.37#ibcon#about to read 6, iclass 29, count 2 2006.173.20:51:02.37#ibcon#read 6, iclass 29, count 2 2006.173.20:51:02.37#ibcon#end of sib2, iclass 29, count 2 2006.173.20:51:02.37#ibcon#*mode == 0, iclass 29, count 2 2006.173.20:51:02.37#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.20:51:02.37#ibcon#[27=AT08-04\r\n] 2006.173.20:51:02.37#ibcon#*before write, iclass 29, count 2 2006.173.20:51:02.37#ibcon#enter sib2, iclass 29, count 2 2006.173.20:51:02.37#ibcon#flushed, iclass 29, count 2 2006.173.20:51:02.37#ibcon#about to write, iclass 29, count 2 2006.173.20:51:02.37#ibcon#wrote, iclass 29, count 2 2006.173.20:51:02.37#ibcon#about to read 3, iclass 29, count 2 2006.173.20:51:02.40#ibcon#read 3, iclass 29, count 2 2006.173.20:51:02.40#ibcon#about to read 4, iclass 29, count 2 2006.173.20:51:02.40#ibcon#read 4, iclass 29, count 2 2006.173.20:51:02.40#ibcon#about to read 5, iclass 29, count 2 2006.173.20:51:02.40#ibcon#read 5, iclass 29, count 2 2006.173.20:51:02.40#ibcon#about to read 6, iclass 29, count 2 2006.173.20:51:02.40#ibcon#read 6, iclass 29, count 2 2006.173.20:51:02.40#ibcon#end of sib2, iclass 29, count 2 2006.173.20:51:02.40#ibcon#*after write, iclass 29, count 2 2006.173.20:51:02.40#ibcon#*before return 0, iclass 29, count 2 2006.173.20:51:02.40#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.20:51:02.40#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.20:51:02.40#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.20:51:02.40#ibcon#ireg 7 cls_cnt 0 2006.173.20:51:02.40#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.20:51:02.52#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.20:51:02.52#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.20:51:02.52#ibcon#enter wrdev, iclass 29, count 0 2006.173.20:51:02.52#ibcon#first serial, iclass 29, count 0 2006.173.20:51:02.52#ibcon#enter sib2, iclass 29, count 0 2006.173.20:51:02.52#ibcon#flushed, iclass 29, count 0 2006.173.20:51:02.52#ibcon#about to write, iclass 29, count 0 2006.173.20:51:02.52#ibcon#wrote, iclass 29, count 0 2006.173.20:51:02.52#ibcon#about to read 3, iclass 29, count 0 2006.173.20:51:02.54#ibcon#read 3, iclass 29, count 0 2006.173.20:51:02.54#ibcon#about to read 4, iclass 29, count 0 2006.173.20:51:02.54#ibcon#read 4, iclass 29, count 0 2006.173.20:51:02.54#ibcon#about to read 5, iclass 29, count 0 2006.173.20:51:02.54#ibcon#read 5, iclass 29, count 0 2006.173.20:51:02.54#ibcon#about to read 6, iclass 29, count 0 2006.173.20:51:02.54#ibcon#read 6, iclass 29, count 0 2006.173.20:51:02.54#ibcon#end of sib2, iclass 29, count 0 2006.173.20:51:02.54#ibcon#*mode == 0, iclass 29, count 0 2006.173.20:51:02.54#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.20:51:02.54#ibcon#[27=USB\r\n] 2006.173.20:51:02.54#ibcon#*before write, iclass 29, count 0 2006.173.20:51:02.54#ibcon#enter sib2, iclass 29, count 0 2006.173.20:51:02.54#ibcon#flushed, iclass 29, count 0 2006.173.20:51:02.54#ibcon#about to write, iclass 29, count 0 2006.173.20:51:02.54#ibcon#wrote, iclass 29, count 0 2006.173.20:51:02.54#ibcon#about to read 3, iclass 29, count 0 2006.173.20:51:02.57#ibcon#read 3, iclass 29, count 0 2006.173.20:51:02.57#ibcon#about to read 4, iclass 29, count 0 2006.173.20:51:02.57#ibcon#read 4, iclass 29, count 0 2006.173.20:51:02.57#ibcon#about to read 5, iclass 29, count 0 2006.173.20:51:02.57#ibcon#read 5, iclass 29, count 0 2006.173.20:51:02.57#ibcon#about to read 6, iclass 29, count 0 2006.173.20:51:02.57#ibcon#read 6, iclass 29, count 0 2006.173.20:51:02.57#ibcon#end of sib2, iclass 29, count 0 2006.173.20:51:02.57#ibcon#*after write, iclass 29, count 0 2006.173.20:51:02.57#ibcon#*before return 0, iclass 29, count 0 2006.173.20:51:02.57#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.20:51:02.57#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.20:51:02.57#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.20:51:02.57#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.20:51:02.57$vck44/vabw=wide 2006.173.20:51:02.57#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.20:51:02.57#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.20:51:02.57#ibcon#ireg 8 cls_cnt 0 2006.173.20:51:02.57#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.20:51:02.57#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.20:51:02.57#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.20:51:02.57#ibcon#enter wrdev, iclass 31, count 0 2006.173.20:51:02.57#ibcon#first serial, iclass 31, count 0 2006.173.20:51:02.57#ibcon#enter sib2, iclass 31, count 0 2006.173.20:51:02.57#ibcon#flushed, iclass 31, count 0 2006.173.20:51:02.57#ibcon#about to write, iclass 31, count 0 2006.173.20:51:02.57#ibcon#wrote, iclass 31, count 0 2006.173.20:51:02.57#ibcon#about to read 3, iclass 31, count 0 2006.173.20:51:02.59#ibcon#read 3, iclass 31, count 0 2006.173.20:51:02.59#ibcon#about to read 4, iclass 31, count 0 2006.173.20:51:02.59#ibcon#read 4, iclass 31, count 0 2006.173.20:51:02.59#ibcon#about to read 5, iclass 31, count 0 2006.173.20:51:02.59#ibcon#read 5, iclass 31, count 0 2006.173.20:51:02.59#ibcon#about to read 6, iclass 31, count 0 2006.173.20:51:02.59#ibcon#read 6, iclass 31, count 0 2006.173.20:51:02.59#ibcon#end of sib2, iclass 31, count 0 2006.173.20:51:02.59#ibcon#*mode == 0, iclass 31, count 0 2006.173.20:51:02.59#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.20:51:02.59#ibcon#[25=BW32\r\n] 2006.173.20:51:02.59#ibcon#*before write, iclass 31, count 0 2006.173.20:51:02.59#ibcon#enter sib2, iclass 31, count 0 2006.173.20:51:02.59#ibcon#flushed, iclass 31, count 0 2006.173.20:51:02.59#ibcon#about to write, iclass 31, count 0 2006.173.20:51:02.59#ibcon#wrote, iclass 31, count 0 2006.173.20:51:02.59#ibcon#about to read 3, iclass 31, count 0 2006.173.20:51:02.62#ibcon#read 3, iclass 31, count 0 2006.173.20:51:02.62#ibcon#about to read 4, iclass 31, count 0 2006.173.20:51:02.62#ibcon#read 4, iclass 31, count 0 2006.173.20:51:02.62#ibcon#about to read 5, iclass 31, count 0 2006.173.20:51:02.62#ibcon#read 5, iclass 31, count 0 2006.173.20:51:02.62#ibcon#about to read 6, iclass 31, count 0 2006.173.20:51:02.62#ibcon#read 6, iclass 31, count 0 2006.173.20:51:02.62#ibcon#end of sib2, iclass 31, count 0 2006.173.20:51:02.62#ibcon#*after write, iclass 31, count 0 2006.173.20:51:02.62#ibcon#*before return 0, iclass 31, count 0 2006.173.20:51:02.62#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.20:51:02.62#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.20:51:02.62#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.20:51:02.62#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.20:51:02.62$vck44/vbbw=wide 2006.173.20:51:02.62#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.20:51:02.62#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.20:51:02.62#ibcon#ireg 8 cls_cnt 0 2006.173.20:51:02.62#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.20:51:02.69#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.20:51:02.69#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.20:51:02.69#ibcon#enter wrdev, iclass 33, count 0 2006.173.20:51:02.69#ibcon#first serial, iclass 33, count 0 2006.173.20:51:02.69#ibcon#enter sib2, iclass 33, count 0 2006.173.20:51:02.69#ibcon#flushed, iclass 33, count 0 2006.173.20:51:02.69#ibcon#about to write, iclass 33, count 0 2006.173.20:51:02.69#ibcon#wrote, iclass 33, count 0 2006.173.20:51:02.69#ibcon#about to read 3, iclass 33, count 0 2006.173.20:51:02.71#ibcon#read 3, iclass 33, count 0 2006.173.20:51:02.71#ibcon#about to read 4, iclass 33, count 0 2006.173.20:51:02.71#ibcon#read 4, iclass 33, count 0 2006.173.20:51:02.71#ibcon#about to read 5, iclass 33, count 0 2006.173.20:51:02.71#ibcon#read 5, iclass 33, count 0 2006.173.20:51:02.71#ibcon#about to read 6, iclass 33, count 0 2006.173.20:51:02.71#ibcon#read 6, iclass 33, count 0 2006.173.20:51:02.71#ibcon#end of sib2, iclass 33, count 0 2006.173.20:51:02.71#ibcon#*mode == 0, iclass 33, count 0 2006.173.20:51:02.71#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.20:51:02.71#ibcon#[27=BW32\r\n] 2006.173.20:51:02.71#ibcon#*before write, iclass 33, count 0 2006.173.20:51:02.71#ibcon#enter sib2, iclass 33, count 0 2006.173.20:51:02.71#ibcon#flushed, iclass 33, count 0 2006.173.20:51:02.71#ibcon#about to write, iclass 33, count 0 2006.173.20:51:02.71#ibcon#wrote, iclass 33, count 0 2006.173.20:51:02.71#ibcon#about to read 3, iclass 33, count 0 2006.173.20:51:02.74#ibcon#read 3, iclass 33, count 0 2006.173.20:51:02.74#ibcon#about to read 4, iclass 33, count 0 2006.173.20:51:02.74#ibcon#read 4, iclass 33, count 0 2006.173.20:51:02.74#ibcon#about to read 5, iclass 33, count 0 2006.173.20:51:02.74#ibcon#read 5, iclass 33, count 0 2006.173.20:51:02.74#ibcon#about to read 6, iclass 33, count 0 2006.173.20:51:02.74#ibcon#read 6, iclass 33, count 0 2006.173.20:51:02.74#ibcon#end of sib2, iclass 33, count 0 2006.173.20:51:02.74#ibcon#*after write, iclass 33, count 0 2006.173.20:51:02.74#ibcon#*before return 0, iclass 33, count 0 2006.173.20:51:02.74#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.20:51:02.74#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.20:51:02.74#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.20:51:02.74#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.20:51:02.74$setupk4/ifdk4 2006.173.20:51:02.74$ifdk4/lo= 2006.173.20:51:02.74$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.20:51:02.74$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.20:51:02.74$ifdk4/patch= 2006.173.20:51:02.74$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.20:51:02.74$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.20:51:02.74$setupk4/!*+20s 2006.173.20:51:09.14#abcon#<5=/08 0.4 1.4 20.771001003.2\r\n> 2006.173.20:51:09.16#abcon#{5=INTERFACE CLEAR} 2006.173.20:51:09.22#abcon#[5=S1D000X0/0*\r\n] 2006.173.20:51:17.25$setupk4/"tpicd 2006.173.20:51:17.25$setupk4/echo=off 2006.173.20:51:17.25$setupk4/xlog=off 2006.173.20:51:17.25:!2006.173.20:54:02 2006.173.20:51:19.14#trakl#Source acquired 2006.173.20:51:20.14#flagr#flagr/antenna,acquired 2006.173.20:54:02.00:preob 2006.173.20:54:03.13/onsource/TRACKING 2006.173.20:54:03.13:!2006.173.20:54:12 2006.173.20:54:12.00:"tape 2006.173.20:54:12.00:"st=record 2006.173.20:54:12.00:data_valid=on 2006.173.20:54:12.00:midob 2006.173.20:54:12.13/onsource/TRACKING 2006.173.20:54:12.13/wx/20.78,1003.1,100 2006.173.20:54:12.20/cable/+6.5158E-03 2006.173.20:54:13.29/va/01,07,usb,yes,35,38 2006.173.20:54:13.29/va/02,06,usb,yes,35,36 2006.173.20:54:13.29/va/03,05,usb,yes,45,47 2006.173.20:54:13.29/va/04,06,usb,yes,36,38 2006.173.20:54:13.29/va/05,04,usb,yes,28,29 2006.173.20:54:13.29/va/06,03,usb,yes,40,39 2006.173.20:54:13.29/va/07,04,usb,yes,32,33 2006.173.20:54:13.29/va/08,04,usb,yes,27,33 2006.173.20:54:13.52/valo/01,524.99,yes,locked 2006.173.20:54:13.52/valo/02,534.99,yes,locked 2006.173.20:54:13.52/valo/03,564.99,yes,locked 2006.173.20:54:13.52/valo/04,624.99,yes,locked 2006.173.20:54:13.52/valo/05,734.99,yes,locked 2006.173.20:54:13.52/valo/06,814.99,yes,locked 2006.173.20:54:13.52/valo/07,864.99,yes,locked 2006.173.20:54:13.52/valo/08,884.99,yes,locked 2006.173.20:54:14.61/vb/01,04,usb,yes,29,27 2006.173.20:54:14.61/vb/02,04,usb,yes,31,31 2006.173.20:54:14.61/vb/03,04,usb,yes,28,31 2006.173.20:54:14.61/vb/04,04,usb,yes,33,32 2006.173.20:54:14.61/vb/05,04,usb,yes,25,28 2006.173.20:54:14.61/vb/06,04,usb,yes,30,26 2006.173.20:54:14.61/vb/07,04,usb,yes,29,29 2006.173.20:54:14.61/vb/08,04,usb,yes,27,30 2006.173.20:54:14.85/vblo/01,629.99,yes,locked 2006.173.20:54:14.85/vblo/02,634.99,yes,locked 2006.173.20:54:14.85/vblo/03,649.99,yes,locked 2006.173.20:54:14.85/vblo/04,679.99,yes,locked 2006.173.20:54:14.85/vblo/05,709.99,yes,locked 2006.173.20:54:14.85/vblo/06,719.99,yes,locked 2006.173.20:54:14.85/vblo/07,734.99,yes,locked 2006.173.20:54:14.85/vblo/08,744.99,yes,locked 2006.173.20:54:15.00/vabw/8 2006.173.20:54:15.15/vbbw/8 2006.173.20:54:15.32/xfe/off,on,15.2 2006.173.20:54:15.71/ifatt/23,28,28,28 2006.173.20:54:16.08/fmout-gps/S +3.84E-07 2006.173.20:54:16.12:!2006.173.20:58:42 2006.173.20:58:42.01:data_valid=off 2006.173.20:58:42.01:"et 2006.173.20:58:42.02:!+3s 2006.173.20:58:45.03:"tape 2006.173.20:58:45.03:postob 2006.173.20:58:45.13/cable/+6.5160E-03 2006.173.20:58:45.13/wx/20.87,1003.0,100 2006.173.20:58:45.19/fmout-gps/S +3.82E-07 2006.173.20:58:45.19:scan_name=173-2108,jd0606,180 2006.173.20:58:45.20:source=3c446,222547.26,-045701.4,2000.0,cw 2006.173.20:58:46.14#flagr#flagr/antenna,new-source 2006.173.20:58:46.14:checkk5 2006.173.20:58:46.56/chk_autoobs//k5ts1/ autoobs is running! 2006.173.20:58:46.96/chk_autoobs//k5ts2/ autoobs is running! 2006.173.20:58:47.35/chk_autoobs//k5ts3/ autoobs is running! 2006.173.20:58:47.75/chk_autoobs//k5ts4/ autoobs is running! 2006.173.20:58:48.13/chk_obsdata//k5ts1/T1732054??a.dat file size is correct (nominal:1080MB, actual:1076MB). 2006.173.20:58:48.53/chk_obsdata//k5ts2/T1732054??b.dat file size is correct (nominal:1080MB, actual:1076MB). 2006.173.20:58:48.93/chk_obsdata//k5ts3/T1732054??c.dat file size is correct (nominal:1080MB, actual:1076MB). 2006.173.20:58:49.33/chk_obsdata//k5ts4/T1732054??d.dat file size is correct (nominal:1080MB, actual:1076MB). 2006.173.20:58:50.04/k5log//k5ts1_log_newline 2006.173.20:58:50.74/k5log//k5ts2_log_newline 2006.173.20:58:51.44/k5log//k5ts3_log_newline 2006.173.20:58:52.14/k5log//k5ts4_log_newline 2006.173.20:58:52.16/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.20:58:52.16:setupk4=1 2006.173.20:58:52.17$setupk4/echo=on 2006.173.20:58:52.17$setupk4/pcalon 2006.173.20:58:52.17$pcalon/"no phase cal control is implemented here 2006.173.20:58:52.17$setupk4/"tpicd=stop 2006.173.20:58:52.17$setupk4/"rec=synch_on 2006.173.20:58:52.17$setupk4/"rec_mode=128 2006.173.20:58:52.17$setupk4/!* 2006.173.20:58:52.17$setupk4/recpk4 2006.173.20:58:52.17$recpk4/recpatch= 2006.173.20:58:52.17$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.20:58:52.17$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.20:58:52.17$setupk4/vck44 2006.173.20:58:52.17$vck44/valo=1,524.99 2006.173.20:58:52.17#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.20:58:52.17#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.20:58:52.17#ibcon#ireg 17 cls_cnt 0 2006.173.20:58:52.17#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.20:58:52.17#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.20:58:52.17#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.20:58:52.17#ibcon#enter wrdev, iclass 4, count 0 2006.173.20:58:52.17#ibcon#first serial, iclass 4, count 0 2006.173.20:58:52.17#ibcon#enter sib2, iclass 4, count 0 2006.173.20:58:52.17#ibcon#flushed, iclass 4, count 0 2006.173.20:58:52.17#ibcon#about to write, iclass 4, count 0 2006.173.20:58:52.17#ibcon#wrote, iclass 4, count 0 2006.173.20:58:52.17#ibcon#about to read 3, iclass 4, count 0 2006.173.20:58:52.19#ibcon#read 3, iclass 4, count 0 2006.173.20:58:52.19#ibcon#about to read 4, iclass 4, count 0 2006.173.20:58:52.19#ibcon#read 4, iclass 4, count 0 2006.173.20:58:52.19#ibcon#about to read 5, iclass 4, count 0 2006.173.20:58:52.19#ibcon#read 5, iclass 4, count 0 2006.173.20:58:52.19#ibcon#about to read 6, iclass 4, count 0 2006.173.20:58:52.19#ibcon#read 6, iclass 4, count 0 2006.173.20:58:52.19#ibcon#end of sib2, iclass 4, count 0 2006.173.20:58:52.19#ibcon#*mode == 0, iclass 4, count 0 2006.173.20:58:52.19#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.20:58:52.19#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.20:58:52.19#ibcon#*before write, iclass 4, count 0 2006.173.20:58:52.19#ibcon#enter sib2, iclass 4, count 0 2006.173.20:58:52.19#ibcon#flushed, iclass 4, count 0 2006.173.20:58:52.19#ibcon#about to write, iclass 4, count 0 2006.173.20:58:52.19#ibcon#wrote, iclass 4, count 0 2006.173.20:58:52.19#ibcon#about to read 3, iclass 4, count 0 2006.173.20:58:52.24#ibcon#read 3, iclass 4, count 0 2006.173.20:58:52.24#ibcon#about to read 4, iclass 4, count 0 2006.173.20:58:52.24#ibcon#read 4, iclass 4, count 0 2006.173.20:58:52.24#ibcon#about to read 5, iclass 4, count 0 2006.173.20:58:52.24#ibcon#read 5, iclass 4, count 0 2006.173.20:58:52.24#ibcon#about to read 6, iclass 4, count 0 2006.173.20:58:52.24#ibcon#read 6, iclass 4, count 0 2006.173.20:58:52.24#ibcon#end of sib2, iclass 4, count 0 2006.173.20:58:52.24#ibcon#*after write, iclass 4, count 0 2006.173.20:58:52.24#ibcon#*before return 0, iclass 4, count 0 2006.173.20:58:52.24#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.20:58:52.24#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.20:58:52.24#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.20:58:52.24#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.20:58:52.24$vck44/va=1,7 2006.173.20:58:52.24#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.20:58:52.24#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.20:58:52.24#ibcon#ireg 11 cls_cnt 2 2006.173.20:58:52.24#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.20:58:52.24#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.20:58:52.24#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.20:58:52.24#ibcon#enter wrdev, iclass 6, count 2 2006.173.20:58:52.24#ibcon#first serial, iclass 6, count 2 2006.173.20:58:52.24#ibcon#enter sib2, iclass 6, count 2 2006.173.20:58:52.24#ibcon#flushed, iclass 6, count 2 2006.173.20:58:52.24#ibcon#about to write, iclass 6, count 2 2006.173.20:58:52.24#ibcon#wrote, iclass 6, count 2 2006.173.20:58:52.24#ibcon#about to read 3, iclass 6, count 2 2006.173.20:58:52.26#ibcon#read 3, iclass 6, count 2 2006.173.20:58:52.26#ibcon#about to read 4, iclass 6, count 2 2006.173.20:58:52.26#ibcon#read 4, iclass 6, count 2 2006.173.20:58:52.26#ibcon#about to read 5, iclass 6, count 2 2006.173.20:58:52.26#ibcon#read 5, iclass 6, count 2 2006.173.20:58:52.26#ibcon#about to read 6, iclass 6, count 2 2006.173.20:58:52.26#ibcon#read 6, iclass 6, count 2 2006.173.20:58:52.26#ibcon#end of sib2, iclass 6, count 2 2006.173.20:58:52.26#ibcon#*mode == 0, iclass 6, count 2 2006.173.20:58:52.26#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.20:58:52.26#ibcon#[25=AT01-07\r\n] 2006.173.20:58:52.26#ibcon#*before write, iclass 6, count 2 2006.173.20:58:52.26#ibcon#enter sib2, iclass 6, count 2 2006.173.20:58:52.26#ibcon#flushed, iclass 6, count 2 2006.173.20:58:52.26#ibcon#about to write, iclass 6, count 2 2006.173.20:58:52.26#ibcon#wrote, iclass 6, count 2 2006.173.20:58:52.26#ibcon#about to read 3, iclass 6, count 2 2006.173.20:58:52.29#ibcon#read 3, iclass 6, count 2 2006.173.20:58:52.29#ibcon#about to read 4, iclass 6, count 2 2006.173.20:58:52.29#ibcon#read 4, iclass 6, count 2 2006.173.20:58:52.29#ibcon#about to read 5, iclass 6, count 2 2006.173.20:58:52.29#ibcon#read 5, iclass 6, count 2 2006.173.20:58:52.29#ibcon#about to read 6, iclass 6, count 2 2006.173.20:58:52.29#ibcon#read 6, iclass 6, count 2 2006.173.20:58:52.29#ibcon#end of sib2, iclass 6, count 2 2006.173.20:58:52.29#ibcon#*after write, iclass 6, count 2 2006.173.20:58:52.29#ibcon#*before return 0, iclass 6, count 2 2006.173.20:58:52.29#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.20:58:52.29#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.20:58:52.29#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.20:58:52.29#ibcon#ireg 7 cls_cnt 0 2006.173.20:58:52.29#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.20:58:52.41#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.20:58:52.41#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.20:58:52.41#ibcon#enter wrdev, iclass 6, count 0 2006.173.20:58:52.41#ibcon#first serial, iclass 6, count 0 2006.173.20:58:52.41#ibcon#enter sib2, iclass 6, count 0 2006.173.20:58:52.41#ibcon#flushed, iclass 6, count 0 2006.173.20:58:52.41#ibcon#about to write, iclass 6, count 0 2006.173.20:58:52.41#ibcon#wrote, iclass 6, count 0 2006.173.20:58:52.41#ibcon#about to read 3, iclass 6, count 0 2006.173.20:58:52.43#ibcon#read 3, iclass 6, count 0 2006.173.20:58:52.43#ibcon#about to read 4, iclass 6, count 0 2006.173.20:58:52.43#ibcon#read 4, iclass 6, count 0 2006.173.20:58:52.43#ibcon#about to read 5, iclass 6, count 0 2006.173.20:58:52.43#ibcon#read 5, iclass 6, count 0 2006.173.20:58:52.43#ibcon#about to read 6, iclass 6, count 0 2006.173.20:58:52.43#ibcon#read 6, iclass 6, count 0 2006.173.20:58:52.43#ibcon#end of sib2, iclass 6, count 0 2006.173.20:58:52.43#ibcon#*mode == 0, iclass 6, count 0 2006.173.20:58:52.43#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.20:58:52.43#ibcon#[25=USB\r\n] 2006.173.20:58:52.43#ibcon#*before write, iclass 6, count 0 2006.173.20:58:52.43#ibcon#enter sib2, iclass 6, count 0 2006.173.20:58:52.43#ibcon#flushed, iclass 6, count 0 2006.173.20:58:52.43#ibcon#about to write, iclass 6, count 0 2006.173.20:58:52.43#ibcon#wrote, iclass 6, count 0 2006.173.20:58:52.43#ibcon#about to read 3, iclass 6, count 0 2006.173.20:58:52.46#ibcon#read 3, iclass 6, count 0 2006.173.20:58:52.46#ibcon#about to read 4, iclass 6, count 0 2006.173.20:58:52.46#ibcon#read 4, iclass 6, count 0 2006.173.20:58:52.46#ibcon#about to read 5, iclass 6, count 0 2006.173.20:58:52.46#ibcon#read 5, iclass 6, count 0 2006.173.20:58:52.46#ibcon#about to read 6, iclass 6, count 0 2006.173.20:58:52.46#ibcon#read 6, iclass 6, count 0 2006.173.20:58:52.46#ibcon#end of sib2, iclass 6, count 0 2006.173.20:58:52.46#ibcon#*after write, iclass 6, count 0 2006.173.20:58:52.46#ibcon#*before return 0, iclass 6, count 0 2006.173.20:58:52.46#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.20:58:52.46#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.20:58:52.46#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.20:58:52.46#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.20:58:52.46$vck44/valo=2,534.99 2006.173.20:58:52.46#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.20:58:52.46#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.20:58:52.46#ibcon#ireg 17 cls_cnt 0 2006.173.20:58:52.46#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.20:58:52.46#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.20:58:52.46#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.20:58:52.46#ibcon#enter wrdev, iclass 10, count 0 2006.173.20:58:52.46#ibcon#first serial, iclass 10, count 0 2006.173.20:58:52.46#ibcon#enter sib2, iclass 10, count 0 2006.173.20:58:52.46#ibcon#flushed, iclass 10, count 0 2006.173.20:58:52.46#ibcon#about to write, iclass 10, count 0 2006.173.20:58:52.46#ibcon#wrote, iclass 10, count 0 2006.173.20:58:52.46#ibcon#about to read 3, iclass 10, count 0 2006.173.20:58:52.48#ibcon#read 3, iclass 10, count 0 2006.173.20:58:52.48#ibcon#about to read 4, iclass 10, count 0 2006.173.20:58:52.48#ibcon#read 4, iclass 10, count 0 2006.173.20:58:52.48#ibcon#about to read 5, iclass 10, count 0 2006.173.20:58:52.48#ibcon#read 5, iclass 10, count 0 2006.173.20:58:52.48#ibcon#about to read 6, iclass 10, count 0 2006.173.20:58:52.48#ibcon#read 6, iclass 10, count 0 2006.173.20:58:52.48#ibcon#end of sib2, iclass 10, count 0 2006.173.20:58:52.48#ibcon#*mode == 0, iclass 10, count 0 2006.173.20:58:52.48#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.20:58:52.48#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.20:58:52.48#ibcon#*before write, iclass 10, count 0 2006.173.20:58:52.48#ibcon#enter sib2, iclass 10, count 0 2006.173.20:58:52.48#ibcon#flushed, iclass 10, count 0 2006.173.20:58:52.48#ibcon#about to write, iclass 10, count 0 2006.173.20:58:52.48#ibcon#wrote, iclass 10, count 0 2006.173.20:58:52.48#ibcon#about to read 3, iclass 10, count 0 2006.173.20:58:52.52#ibcon#read 3, iclass 10, count 0 2006.173.20:58:52.52#ibcon#about to read 4, iclass 10, count 0 2006.173.20:58:52.52#ibcon#read 4, iclass 10, count 0 2006.173.20:58:52.52#ibcon#about to read 5, iclass 10, count 0 2006.173.20:58:52.52#ibcon#read 5, iclass 10, count 0 2006.173.20:58:52.52#ibcon#about to read 6, iclass 10, count 0 2006.173.20:58:52.52#ibcon#read 6, iclass 10, count 0 2006.173.20:58:52.52#ibcon#end of sib2, iclass 10, count 0 2006.173.20:58:52.52#ibcon#*after write, iclass 10, count 0 2006.173.20:58:52.52#ibcon#*before return 0, iclass 10, count 0 2006.173.20:58:52.52#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.20:58:52.52#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.20:58:52.52#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.20:58:52.52#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.20:58:52.52$vck44/va=2,6 2006.173.20:58:52.52#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.20:58:52.52#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.20:58:52.52#ibcon#ireg 11 cls_cnt 2 2006.173.20:58:52.52#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.20:58:52.58#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.20:58:52.58#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.20:58:52.58#ibcon#enter wrdev, iclass 12, count 2 2006.173.20:58:52.58#ibcon#first serial, iclass 12, count 2 2006.173.20:58:52.58#ibcon#enter sib2, iclass 12, count 2 2006.173.20:58:52.58#ibcon#flushed, iclass 12, count 2 2006.173.20:58:52.58#ibcon#about to write, iclass 12, count 2 2006.173.20:58:52.58#ibcon#wrote, iclass 12, count 2 2006.173.20:58:52.58#ibcon#about to read 3, iclass 12, count 2 2006.173.20:58:52.60#ibcon#read 3, iclass 12, count 2 2006.173.20:58:52.60#ibcon#about to read 4, iclass 12, count 2 2006.173.20:58:52.60#ibcon#read 4, iclass 12, count 2 2006.173.20:58:52.60#ibcon#about to read 5, iclass 12, count 2 2006.173.20:58:52.60#ibcon#read 5, iclass 12, count 2 2006.173.20:58:52.60#ibcon#about to read 6, iclass 12, count 2 2006.173.20:58:52.60#ibcon#read 6, iclass 12, count 2 2006.173.20:58:52.60#ibcon#end of sib2, iclass 12, count 2 2006.173.20:58:52.60#ibcon#*mode == 0, iclass 12, count 2 2006.173.20:58:52.60#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.20:58:52.60#ibcon#[25=AT02-06\r\n] 2006.173.20:58:52.60#ibcon#*before write, iclass 12, count 2 2006.173.20:58:52.60#ibcon#enter sib2, iclass 12, count 2 2006.173.20:58:52.60#ibcon#flushed, iclass 12, count 2 2006.173.20:58:52.60#ibcon#about to write, iclass 12, count 2 2006.173.20:58:52.60#ibcon#wrote, iclass 12, count 2 2006.173.20:58:52.60#ibcon#about to read 3, iclass 12, count 2 2006.173.20:58:52.63#ibcon#read 3, iclass 12, count 2 2006.173.20:58:52.63#ibcon#about to read 4, iclass 12, count 2 2006.173.20:58:52.63#ibcon#read 4, iclass 12, count 2 2006.173.20:58:52.63#ibcon#about to read 5, iclass 12, count 2 2006.173.20:58:52.63#ibcon#read 5, iclass 12, count 2 2006.173.20:58:52.63#ibcon#about to read 6, iclass 12, count 2 2006.173.20:58:52.63#ibcon#read 6, iclass 12, count 2 2006.173.20:58:52.63#ibcon#end of sib2, iclass 12, count 2 2006.173.20:58:52.63#ibcon#*after write, iclass 12, count 2 2006.173.20:58:52.63#ibcon#*before return 0, iclass 12, count 2 2006.173.20:58:52.63#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.20:58:52.63#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.20:58:52.63#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.20:58:52.63#ibcon#ireg 7 cls_cnt 0 2006.173.20:58:52.63#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.20:58:52.75#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.20:58:52.75#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.20:58:52.75#ibcon#enter wrdev, iclass 12, count 0 2006.173.20:58:52.75#ibcon#first serial, iclass 12, count 0 2006.173.20:58:52.75#ibcon#enter sib2, iclass 12, count 0 2006.173.20:58:52.75#ibcon#flushed, iclass 12, count 0 2006.173.20:58:52.75#ibcon#about to write, iclass 12, count 0 2006.173.20:58:52.75#ibcon#wrote, iclass 12, count 0 2006.173.20:58:52.75#ibcon#about to read 3, iclass 12, count 0 2006.173.20:58:52.77#ibcon#read 3, iclass 12, count 0 2006.173.20:58:52.77#ibcon#about to read 4, iclass 12, count 0 2006.173.20:58:52.77#ibcon#read 4, iclass 12, count 0 2006.173.20:58:52.77#ibcon#about to read 5, iclass 12, count 0 2006.173.20:58:52.77#ibcon#read 5, iclass 12, count 0 2006.173.20:58:52.77#ibcon#about to read 6, iclass 12, count 0 2006.173.20:58:52.77#ibcon#read 6, iclass 12, count 0 2006.173.20:58:52.77#ibcon#end of sib2, iclass 12, count 0 2006.173.20:58:52.77#ibcon#*mode == 0, iclass 12, count 0 2006.173.20:58:52.77#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.20:58:52.77#ibcon#[25=USB\r\n] 2006.173.20:58:52.77#ibcon#*before write, iclass 12, count 0 2006.173.20:58:52.77#ibcon#enter sib2, iclass 12, count 0 2006.173.20:58:52.77#ibcon#flushed, iclass 12, count 0 2006.173.20:58:52.77#ibcon#about to write, iclass 12, count 0 2006.173.20:58:52.77#ibcon#wrote, iclass 12, count 0 2006.173.20:58:52.77#ibcon#about to read 3, iclass 12, count 0 2006.173.20:58:52.80#ibcon#read 3, iclass 12, count 0 2006.173.20:58:52.80#ibcon#about to read 4, iclass 12, count 0 2006.173.20:58:52.80#ibcon#read 4, iclass 12, count 0 2006.173.20:58:52.80#ibcon#about to read 5, iclass 12, count 0 2006.173.20:58:52.80#ibcon#read 5, iclass 12, count 0 2006.173.20:58:52.80#ibcon#about to read 6, iclass 12, count 0 2006.173.20:58:52.80#ibcon#read 6, iclass 12, count 0 2006.173.20:58:52.80#ibcon#end of sib2, iclass 12, count 0 2006.173.20:58:52.80#ibcon#*after write, iclass 12, count 0 2006.173.20:58:52.80#ibcon#*before return 0, iclass 12, count 0 2006.173.20:58:52.80#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.20:58:52.80#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.20:58:52.80#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.20:58:52.80#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.20:58:52.80$vck44/valo=3,564.99 2006.173.20:58:52.80#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.20:58:52.80#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.20:58:52.80#ibcon#ireg 17 cls_cnt 0 2006.173.20:58:52.80#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.20:58:52.80#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.20:58:52.80#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.20:58:52.80#ibcon#enter wrdev, iclass 14, count 0 2006.173.20:58:52.80#ibcon#first serial, iclass 14, count 0 2006.173.20:58:52.80#ibcon#enter sib2, iclass 14, count 0 2006.173.20:58:52.80#ibcon#flushed, iclass 14, count 0 2006.173.20:58:52.80#ibcon#about to write, iclass 14, count 0 2006.173.20:58:52.80#ibcon#wrote, iclass 14, count 0 2006.173.20:58:52.80#ibcon#about to read 3, iclass 14, count 0 2006.173.20:58:52.82#ibcon#read 3, iclass 14, count 0 2006.173.20:58:52.82#ibcon#about to read 4, iclass 14, count 0 2006.173.20:58:52.82#ibcon#read 4, iclass 14, count 0 2006.173.20:58:52.82#ibcon#about to read 5, iclass 14, count 0 2006.173.20:58:52.82#ibcon#read 5, iclass 14, count 0 2006.173.20:58:52.82#ibcon#about to read 6, iclass 14, count 0 2006.173.20:58:52.82#ibcon#read 6, iclass 14, count 0 2006.173.20:58:52.82#ibcon#end of sib2, iclass 14, count 0 2006.173.20:58:52.82#ibcon#*mode == 0, iclass 14, count 0 2006.173.20:58:52.82#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.20:58:52.82#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.20:58:52.82#ibcon#*before write, iclass 14, count 0 2006.173.20:58:52.82#ibcon#enter sib2, iclass 14, count 0 2006.173.20:58:52.82#ibcon#flushed, iclass 14, count 0 2006.173.20:58:52.82#ibcon#about to write, iclass 14, count 0 2006.173.20:58:52.82#ibcon#wrote, iclass 14, count 0 2006.173.20:58:52.82#ibcon#about to read 3, iclass 14, count 0 2006.173.20:58:52.86#ibcon#read 3, iclass 14, count 0 2006.173.20:58:52.86#ibcon#about to read 4, iclass 14, count 0 2006.173.20:58:52.86#ibcon#read 4, iclass 14, count 0 2006.173.20:58:52.86#ibcon#about to read 5, iclass 14, count 0 2006.173.20:58:52.86#ibcon#read 5, iclass 14, count 0 2006.173.20:58:52.86#ibcon#about to read 6, iclass 14, count 0 2006.173.20:58:52.86#ibcon#read 6, iclass 14, count 0 2006.173.20:58:52.86#ibcon#end of sib2, iclass 14, count 0 2006.173.20:58:52.86#ibcon#*after write, iclass 14, count 0 2006.173.20:58:52.86#ibcon#*before return 0, iclass 14, count 0 2006.173.20:58:52.86#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.20:58:52.86#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.20:58:52.86#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.20:58:52.86#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.20:58:52.86$vck44/va=3,5 2006.173.20:58:52.86#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.20:58:52.86#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.20:58:52.86#ibcon#ireg 11 cls_cnt 2 2006.173.20:58:52.86#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.20:58:52.92#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.20:58:52.92#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.20:58:52.92#ibcon#enter wrdev, iclass 16, count 2 2006.173.20:58:52.92#ibcon#first serial, iclass 16, count 2 2006.173.20:58:52.92#ibcon#enter sib2, iclass 16, count 2 2006.173.20:58:52.92#ibcon#flushed, iclass 16, count 2 2006.173.20:58:52.92#ibcon#about to write, iclass 16, count 2 2006.173.20:58:52.92#ibcon#wrote, iclass 16, count 2 2006.173.20:58:52.92#ibcon#about to read 3, iclass 16, count 2 2006.173.20:58:52.94#ibcon#read 3, iclass 16, count 2 2006.173.20:58:52.94#ibcon#about to read 4, iclass 16, count 2 2006.173.20:58:52.94#ibcon#read 4, iclass 16, count 2 2006.173.20:58:52.94#ibcon#about to read 5, iclass 16, count 2 2006.173.20:58:52.94#ibcon#read 5, iclass 16, count 2 2006.173.20:58:52.94#ibcon#about to read 6, iclass 16, count 2 2006.173.20:58:52.94#ibcon#read 6, iclass 16, count 2 2006.173.20:58:52.94#ibcon#end of sib2, iclass 16, count 2 2006.173.20:58:52.94#ibcon#*mode == 0, iclass 16, count 2 2006.173.20:58:52.94#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.20:58:52.94#ibcon#[25=AT03-05\r\n] 2006.173.20:58:52.94#ibcon#*before write, iclass 16, count 2 2006.173.20:58:52.94#ibcon#enter sib2, iclass 16, count 2 2006.173.20:58:52.94#ibcon#flushed, iclass 16, count 2 2006.173.20:58:52.94#ibcon#about to write, iclass 16, count 2 2006.173.20:58:52.94#ibcon#wrote, iclass 16, count 2 2006.173.20:58:52.94#ibcon#about to read 3, iclass 16, count 2 2006.173.20:58:52.97#ibcon#read 3, iclass 16, count 2 2006.173.20:58:52.97#ibcon#about to read 4, iclass 16, count 2 2006.173.20:58:52.97#ibcon#read 4, iclass 16, count 2 2006.173.20:58:52.97#ibcon#about to read 5, iclass 16, count 2 2006.173.20:58:52.97#ibcon#read 5, iclass 16, count 2 2006.173.20:58:52.97#ibcon#about to read 6, iclass 16, count 2 2006.173.20:58:52.97#ibcon#read 6, iclass 16, count 2 2006.173.20:58:52.97#ibcon#end of sib2, iclass 16, count 2 2006.173.20:58:52.97#ibcon#*after write, iclass 16, count 2 2006.173.20:58:52.97#ibcon#*before return 0, iclass 16, count 2 2006.173.20:58:52.97#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.20:58:52.97#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.20:58:52.97#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.20:58:52.97#ibcon#ireg 7 cls_cnt 0 2006.173.20:58:52.97#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.20:58:53.09#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.20:58:53.09#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.20:58:53.09#ibcon#enter wrdev, iclass 16, count 0 2006.173.20:58:53.09#ibcon#first serial, iclass 16, count 0 2006.173.20:58:53.09#ibcon#enter sib2, iclass 16, count 0 2006.173.20:58:53.09#ibcon#flushed, iclass 16, count 0 2006.173.20:58:53.09#ibcon#about to write, iclass 16, count 0 2006.173.20:58:53.09#ibcon#wrote, iclass 16, count 0 2006.173.20:58:53.09#ibcon#about to read 3, iclass 16, count 0 2006.173.20:58:53.11#ibcon#read 3, iclass 16, count 0 2006.173.20:58:53.11#ibcon#about to read 4, iclass 16, count 0 2006.173.20:58:53.11#ibcon#read 4, iclass 16, count 0 2006.173.20:58:53.11#ibcon#about to read 5, iclass 16, count 0 2006.173.20:58:53.11#ibcon#read 5, iclass 16, count 0 2006.173.20:58:53.11#ibcon#about to read 6, iclass 16, count 0 2006.173.20:58:53.11#ibcon#read 6, iclass 16, count 0 2006.173.20:58:53.11#ibcon#end of sib2, iclass 16, count 0 2006.173.20:58:53.11#ibcon#*mode == 0, iclass 16, count 0 2006.173.20:58:53.11#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.20:58:53.11#ibcon#[25=USB\r\n] 2006.173.20:58:53.11#ibcon#*before write, iclass 16, count 0 2006.173.20:58:53.11#ibcon#enter sib2, iclass 16, count 0 2006.173.20:58:53.11#ibcon#flushed, iclass 16, count 0 2006.173.20:58:53.11#ibcon#about to write, iclass 16, count 0 2006.173.20:58:53.11#ibcon#wrote, iclass 16, count 0 2006.173.20:58:53.11#ibcon#about to read 3, iclass 16, count 0 2006.173.20:58:53.14#ibcon#read 3, iclass 16, count 0 2006.173.20:58:53.14#ibcon#about to read 4, iclass 16, count 0 2006.173.20:58:53.14#ibcon#read 4, iclass 16, count 0 2006.173.20:58:53.14#ibcon#about to read 5, iclass 16, count 0 2006.173.20:58:53.14#ibcon#read 5, iclass 16, count 0 2006.173.20:58:53.14#ibcon#about to read 6, iclass 16, count 0 2006.173.20:58:53.14#ibcon#read 6, iclass 16, count 0 2006.173.20:58:53.14#ibcon#end of sib2, iclass 16, count 0 2006.173.20:58:53.14#ibcon#*after write, iclass 16, count 0 2006.173.20:58:53.14#ibcon#*before return 0, iclass 16, count 0 2006.173.20:58:53.14#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.20:58:53.14#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.20:58:53.14#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.20:58:53.14#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.20:58:53.14$vck44/valo=4,624.99 2006.173.20:58:53.14#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.20:58:53.14#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.20:58:53.14#ibcon#ireg 17 cls_cnt 0 2006.173.20:58:53.14#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.20:58:53.14#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.20:58:53.14#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.20:58:53.14#ibcon#enter wrdev, iclass 18, count 0 2006.173.20:58:53.14#ibcon#first serial, iclass 18, count 0 2006.173.20:58:53.14#ibcon#enter sib2, iclass 18, count 0 2006.173.20:58:53.14#ibcon#flushed, iclass 18, count 0 2006.173.20:58:53.14#ibcon#about to write, iclass 18, count 0 2006.173.20:58:53.14#ibcon#wrote, iclass 18, count 0 2006.173.20:58:53.14#ibcon#about to read 3, iclass 18, count 0 2006.173.20:58:53.16#ibcon#read 3, iclass 18, count 0 2006.173.20:58:53.16#ibcon#about to read 4, iclass 18, count 0 2006.173.20:58:53.16#ibcon#read 4, iclass 18, count 0 2006.173.20:58:53.16#ibcon#about to read 5, iclass 18, count 0 2006.173.20:58:53.16#ibcon#read 5, iclass 18, count 0 2006.173.20:58:53.16#ibcon#about to read 6, iclass 18, count 0 2006.173.20:58:53.16#ibcon#read 6, iclass 18, count 0 2006.173.20:58:53.16#ibcon#end of sib2, iclass 18, count 0 2006.173.20:58:53.16#ibcon#*mode == 0, iclass 18, count 0 2006.173.20:58:53.16#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.20:58:53.16#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.20:58:53.16#ibcon#*before write, iclass 18, count 0 2006.173.20:58:53.16#ibcon#enter sib2, iclass 18, count 0 2006.173.20:58:53.16#ibcon#flushed, iclass 18, count 0 2006.173.20:58:53.16#ibcon#about to write, iclass 18, count 0 2006.173.20:58:53.16#ibcon#wrote, iclass 18, count 0 2006.173.20:58:53.16#ibcon#about to read 3, iclass 18, count 0 2006.173.20:58:53.20#ibcon#read 3, iclass 18, count 0 2006.173.20:58:53.20#ibcon#about to read 4, iclass 18, count 0 2006.173.20:58:53.20#ibcon#read 4, iclass 18, count 0 2006.173.20:58:53.20#ibcon#about to read 5, iclass 18, count 0 2006.173.20:58:53.20#ibcon#read 5, iclass 18, count 0 2006.173.20:58:53.20#ibcon#about to read 6, iclass 18, count 0 2006.173.20:58:53.20#ibcon#read 6, iclass 18, count 0 2006.173.20:58:53.20#ibcon#end of sib2, iclass 18, count 0 2006.173.20:58:53.20#ibcon#*after write, iclass 18, count 0 2006.173.20:58:53.20#ibcon#*before return 0, iclass 18, count 0 2006.173.20:58:53.20#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.20:58:53.20#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.20:58:53.20#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.20:58:53.20#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.20:58:53.20$vck44/va=4,6 2006.173.20:58:53.20#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.20:58:53.20#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.20:58:53.20#ibcon#ireg 11 cls_cnt 2 2006.173.20:58:53.20#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.20:58:53.26#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.20:58:53.26#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.20:58:53.26#ibcon#enter wrdev, iclass 20, count 2 2006.173.20:58:53.26#ibcon#first serial, iclass 20, count 2 2006.173.20:58:53.26#ibcon#enter sib2, iclass 20, count 2 2006.173.20:58:53.26#ibcon#flushed, iclass 20, count 2 2006.173.20:58:53.26#ibcon#about to write, iclass 20, count 2 2006.173.20:58:53.26#ibcon#wrote, iclass 20, count 2 2006.173.20:58:53.26#ibcon#about to read 3, iclass 20, count 2 2006.173.20:58:53.28#ibcon#read 3, iclass 20, count 2 2006.173.20:58:53.28#ibcon#about to read 4, iclass 20, count 2 2006.173.20:58:53.28#ibcon#read 4, iclass 20, count 2 2006.173.20:58:53.28#ibcon#about to read 5, iclass 20, count 2 2006.173.20:58:53.28#ibcon#read 5, iclass 20, count 2 2006.173.20:58:53.28#ibcon#about to read 6, iclass 20, count 2 2006.173.20:58:53.28#ibcon#read 6, iclass 20, count 2 2006.173.20:58:53.28#ibcon#end of sib2, iclass 20, count 2 2006.173.20:58:53.28#ibcon#*mode == 0, iclass 20, count 2 2006.173.20:58:53.28#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.20:58:53.28#ibcon#[25=AT04-06\r\n] 2006.173.20:58:53.28#ibcon#*before write, iclass 20, count 2 2006.173.20:58:53.28#ibcon#enter sib2, iclass 20, count 2 2006.173.20:58:53.28#ibcon#flushed, iclass 20, count 2 2006.173.20:58:53.28#ibcon#about to write, iclass 20, count 2 2006.173.20:58:53.28#ibcon#wrote, iclass 20, count 2 2006.173.20:58:53.28#ibcon#about to read 3, iclass 20, count 2 2006.173.20:58:53.31#ibcon#read 3, iclass 20, count 2 2006.173.20:58:53.31#ibcon#about to read 4, iclass 20, count 2 2006.173.20:58:53.31#ibcon#read 4, iclass 20, count 2 2006.173.20:58:53.31#ibcon#about to read 5, iclass 20, count 2 2006.173.20:58:53.31#ibcon#read 5, iclass 20, count 2 2006.173.20:58:53.31#ibcon#about to read 6, iclass 20, count 2 2006.173.20:58:53.31#ibcon#read 6, iclass 20, count 2 2006.173.20:58:53.31#ibcon#end of sib2, iclass 20, count 2 2006.173.20:58:53.31#ibcon#*after write, iclass 20, count 2 2006.173.20:58:53.31#ibcon#*before return 0, iclass 20, count 2 2006.173.20:58:53.31#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.20:58:53.31#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.20:58:53.31#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.20:58:53.31#ibcon#ireg 7 cls_cnt 0 2006.173.20:58:53.31#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.20:58:53.43#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.20:58:53.43#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.20:58:53.43#ibcon#enter wrdev, iclass 20, count 0 2006.173.20:58:53.43#ibcon#first serial, iclass 20, count 0 2006.173.20:58:53.43#ibcon#enter sib2, iclass 20, count 0 2006.173.20:58:53.43#ibcon#flushed, iclass 20, count 0 2006.173.20:58:53.43#ibcon#about to write, iclass 20, count 0 2006.173.20:58:53.43#ibcon#wrote, iclass 20, count 0 2006.173.20:58:53.43#ibcon#about to read 3, iclass 20, count 0 2006.173.20:58:53.45#ibcon#read 3, iclass 20, count 0 2006.173.20:58:53.45#ibcon#about to read 4, iclass 20, count 0 2006.173.20:58:53.45#ibcon#read 4, iclass 20, count 0 2006.173.20:58:53.45#ibcon#about to read 5, iclass 20, count 0 2006.173.20:58:53.45#ibcon#read 5, iclass 20, count 0 2006.173.20:58:53.45#ibcon#about to read 6, iclass 20, count 0 2006.173.20:58:53.45#ibcon#read 6, iclass 20, count 0 2006.173.20:58:53.45#ibcon#end of sib2, iclass 20, count 0 2006.173.20:58:53.45#ibcon#*mode == 0, iclass 20, count 0 2006.173.20:58:53.45#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.20:58:53.45#ibcon#[25=USB\r\n] 2006.173.20:58:53.45#ibcon#*before write, iclass 20, count 0 2006.173.20:58:53.45#ibcon#enter sib2, iclass 20, count 0 2006.173.20:58:53.45#ibcon#flushed, iclass 20, count 0 2006.173.20:58:53.45#ibcon#about to write, iclass 20, count 0 2006.173.20:58:53.45#ibcon#wrote, iclass 20, count 0 2006.173.20:58:53.45#ibcon#about to read 3, iclass 20, count 0 2006.173.20:58:53.48#ibcon#read 3, iclass 20, count 0 2006.173.20:58:53.48#ibcon#about to read 4, iclass 20, count 0 2006.173.20:58:53.48#ibcon#read 4, iclass 20, count 0 2006.173.20:58:53.48#ibcon#about to read 5, iclass 20, count 0 2006.173.20:58:53.48#ibcon#read 5, iclass 20, count 0 2006.173.20:58:53.48#ibcon#about to read 6, iclass 20, count 0 2006.173.20:58:53.48#ibcon#read 6, iclass 20, count 0 2006.173.20:58:53.48#ibcon#end of sib2, iclass 20, count 0 2006.173.20:58:53.48#ibcon#*after write, iclass 20, count 0 2006.173.20:58:53.48#ibcon#*before return 0, iclass 20, count 0 2006.173.20:58:53.48#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.20:58:53.48#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.20:58:53.48#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.20:58:53.48#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.20:58:53.48$vck44/valo=5,734.99 2006.173.20:58:53.48#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.20:58:53.48#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.20:58:53.48#ibcon#ireg 17 cls_cnt 0 2006.173.20:58:53.48#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.20:58:53.48#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.20:58:53.48#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.20:58:53.48#ibcon#enter wrdev, iclass 22, count 0 2006.173.20:58:53.48#ibcon#first serial, iclass 22, count 0 2006.173.20:58:53.48#ibcon#enter sib2, iclass 22, count 0 2006.173.20:58:53.48#ibcon#flushed, iclass 22, count 0 2006.173.20:58:53.48#ibcon#about to write, iclass 22, count 0 2006.173.20:58:53.48#ibcon#wrote, iclass 22, count 0 2006.173.20:58:53.48#ibcon#about to read 3, iclass 22, count 0 2006.173.20:58:53.50#ibcon#read 3, iclass 22, count 0 2006.173.20:58:53.50#ibcon#about to read 4, iclass 22, count 0 2006.173.20:58:53.50#ibcon#read 4, iclass 22, count 0 2006.173.20:58:53.50#ibcon#about to read 5, iclass 22, count 0 2006.173.20:58:53.50#ibcon#read 5, iclass 22, count 0 2006.173.20:58:53.50#ibcon#about to read 6, iclass 22, count 0 2006.173.20:58:53.50#ibcon#read 6, iclass 22, count 0 2006.173.20:58:53.50#ibcon#end of sib2, iclass 22, count 0 2006.173.20:58:53.50#ibcon#*mode == 0, iclass 22, count 0 2006.173.20:58:53.50#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.20:58:53.50#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.20:58:53.50#ibcon#*before write, iclass 22, count 0 2006.173.20:58:53.50#ibcon#enter sib2, iclass 22, count 0 2006.173.20:58:53.50#ibcon#flushed, iclass 22, count 0 2006.173.20:58:53.50#ibcon#about to write, iclass 22, count 0 2006.173.20:58:53.50#ibcon#wrote, iclass 22, count 0 2006.173.20:58:53.50#ibcon#about to read 3, iclass 22, count 0 2006.173.20:58:53.54#ibcon#read 3, iclass 22, count 0 2006.173.20:58:53.54#ibcon#about to read 4, iclass 22, count 0 2006.173.20:58:53.54#ibcon#read 4, iclass 22, count 0 2006.173.20:58:53.54#ibcon#about to read 5, iclass 22, count 0 2006.173.20:58:53.54#ibcon#read 5, iclass 22, count 0 2006.173.20:58:53.54#ibcon#about to read 6, iclass 22, count 0 2006.173.20:58:53.54#ibcon#read 6, iclass 22, count 0 2006.173.20:58:53.54#ibcon#end of sib2, iclass 22, count 0 2006.173.20:58:53.54#ibcon#*after write, iclass 22, count 0 2006.173.20:58:53.54#ibcon#*before return 0, iclass 22, count 0 2006.173.20:58:53.54#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.20:58:53.54#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.20:58:53.54#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.20:58:53.54#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.20:58:53.54$vck44/va=5,4 2006.173.20:58:53.54#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.20:58:53.54#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.20:58:53.54#ibcon#ireg 11 cls_cnt 2 2006.173.20:58:53.54#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.20:58:53.60#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.20:58:53.60#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.20:58:53.60#ibcon#enter wrdev, iclass 24, count 2 2006.173.20:58:53.60#ibcon#first serial, iclass 24, count 2 2006.173.20:58:53.60#ibcon#enter sib2, iclass 24, count 2 2006.173.20:58:53.60#ibcon#flushed, iclass 24, count 2 2006.173.20:58:53.60#ibcon#about to write, iclass 24, count 2 2006.173.20:58:53.60#ibcon#wrote, iclass 24, count 2 2006.173.20:58:53.60#ibcon#about to read 3, iclass 24, count 2 2006.173.20:58:53.62#ibcon#read 3, iclass 24, count 2 2006.173.20:58:53.62#ibcon#about to read 4, iclass 24, count 2 2006.173.20:58:53.62#ibcon#read 4, iclass 24, count 2 2006.173.20:58:53.62#ibcon#about to read 5, iclass 24, count 2 2006.173.20:58:53.62#ibcon#read 5, iclass 24, count 2 2006.173.20:58:53.62#ibcon#about to read 6, iclass 24, count 2 2006.173.20:58:53.62#ibcon#read 6, iclass 24, count 2 2006.173.20:58:53.62#ibcon#end of sib2, iclass 24, count 2 2006.173.20:58:53.62#ibcon#*mode == 0, iclass 24, count 2 2006.173.20:58:53.62#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.20:58:53.62#ibcon#[25=AT05-04\r\n] 2006.173.20:58:53.62#ibcon#*before write, iclass 24, count 2 2006.173.20:58:53.62#ibcon#enter sib2, iclass 24, count 2 2006.173.20:58:53.62#ibcon#flushed, iclass 24, count 2 2006.173.20:58:53.62#ibcon#about to write, iclass 24, count 2 2006.173.20:58:53.62#ibcon#wrote, iclass 24, count 2 2006.173.20:58:53.62#ibcon#about to read 3, iclass 24, count 2 2006.173.20:58:53.65#ibcon#read 3, iclass 24, count 2 2006.173.20:58:53.65#ibcon#about to read 4, iclass 24, count 2 2006.173.20:58:53.65#ibcon#read 4, iclass 24, count 2 2006.173.20:58:53.65#ibcon#about to read 5, iclass 24, count 2 2006.173.20:58:53.65#ibcon#read 5, iclass 24, count 2 2006.173.20:58:53.65#ibcon#about to read 6, iclass 24, count 2 2006.173.20:58:53.65#ibcon#read 6, iclass 24, count 2 2006.173.20:58:53.65#ibcon#end of sib2, iclass 24, count 2 2006.173.20:58:53.65#ibcon#*after write, iclass 24, count 2 2006.173.20:58:53.65#ibcon#*before return 0, iclass 24, count 2 2006.173.20:58:53.65#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.20:58:53.65#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.20:58:53.65#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.20:58:53.65#ibcon#ireg 7 cls_cnt 0 2006.173.20:58:53.65#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.20:58:53.77#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.20:58:53.77#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.20:58:53.77#ibcon#enter wrdev, iclass 24, count 0 2006.173.20:58:53.77#ibcon#first serial, iclass 24, count 0 2006.173.20:58:53.77#ibcon#enter sib2, iclass 24, count 0 2006.173.20:58:53.77#ibcon#flushed, iclass 24, count 0 2006.173.20:58:53.77#ibcon#about to write, iclass 24, count 0 2006.173.20:58:53.77#ibcon#wrote, iclass 24, count 0 2006.173.20:58:53.77#ibcon#about to read 3, iclass 24, count 0 2006.173.20:58:53.79#ibcon#read 3, iclass 24, count 0 2006.173.20:58:53.79#ibcon#about to read 4, iclass 24, count 0 2006.173.20:58:53.79#ibcon#read 4, iclass 24, count 0 2006.173.20:58:53.79#ibcon#about to read 5, iclass 24, count 0 2006.173.20:58:53.79#ibcon#read 5, iclass 24, count 0 2006.173.20:58:53.79#ibcon#about to read 6, iclass 24, count 0 2006.173.20:58:53.79#ibcon#read 6, iclass 24, count 0 2006.173.20:58:53.79#ibcon#end of sib2, iclass 24, count 0 2006.173.20:58:53.79#ibcon#*mode == 0, iclass 24, count 0 2006.173.20:58:53.79#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.20:58:53.79#ibcon#[25=USB\r\n] 2006.173.20:58:53.79#ibcon#*before write, iclass 24, count 0 2006.173.20:58:53.79#ibcon#enter sib2, iclass 24, count 0 2006.173.20:58:53.79#ibcon#flushed, iclass 24, count 0 2006.173.20:58:53.79#ibcon#about to write, iclass 24, count 0 2006.173.20:58:53.79#ibcon#wrote, iclass 24, count 0 2006.173.20:58:53.79#ibcon#about to read 3, iclass 24, count 0 2006.173.20:58:53.82#ibcon#read 3, iclass 24, count 0 2006.173.20:58:53.82#ibcon#about to read 4, iclass 24, count 0 2006.173.20:58:53.82#ibcon#read 4, iclass 24, count 0 2006.173.20:58:53.82#ibcon#about to read 5, iclass 24, count 0 2006.173.20:58:53.82#ibcon#read 5, iclass 24, count 0 2006.173.20:58:53.82#ibcon#about to read 6, iclass 24, count 0 2006.173.20:58:53.82#ibcon#read 6, iclass 24, count 0 2006.173.20:58:53.82#ibcon#end of sib2, iclass 24, count 0 2006.173.20:58:53.82#ibcon#*after write, iclass 24, count 0 2006.173.20:58:53.82#ibcon#*before return 0, iclass 24, count 0 2006.173.20:58:53.82#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.20:58:53.82#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.20:58:53.82#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.20:58:53.82#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.20:58:53.82$vck44/valo=6,814.99 2006.173.20:58:53.82#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.20:58:53.82#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.20:58:53.82#ibcon#ireg 17 cls_cnt 0 2006.173.20:58:53.82#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.20:58:53.82#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.20:58:53.82#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.20:58:53.82#ibcon#enter wrdev, iclass 26, count 0 2006.173.20:58:53.82#ibcon#first serial, iclass 26, count 0 2006.173.20:58:53.82#ibcon#enter sib2, iclass 26, count 0 2006.173.20:58:53.82#ibcon#flushed, iclass 26, count 0 2006.173.20:58:53.82#ibcon#about to write, iclass 26, count 0 2006.173.20:58:53.82#ibcon#wrote, iclass 26, count 0 2006.173.20:58:53.82#ibcon#about to read 3, iclass 26, count 0 2006.173.20:58:53.84#ibcon#read 3, iclass 26, count 0 2006.173.20:58:53.84#ibcon#about to read 4, iclass 26, count 0 2006.173.20:58:53.84#ibcon#read 4, iclass 26, count 0 2006.173.20:58:53.84#ibcon#about to read 5, iclass 26, count 0 2006.173.20:58:53.84#ibcon#read 5, iclass 26, count 0 2006.173.20:58:53.84#ibcon#about to read 6, iclass 26, count 0 2006.173.20:58:53.84#ibcon#read 6, iclass 26, count 0 2006.173.20:58:53.84#ibcon#end of sib2, iclass 26, count 0 2006.173.20:58:53.84#ibcon#*mode == 0, iclass 26, count 0 2006.173.20:58:53.84#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.20:58:53.84#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.20:58:53.84#ibcon#*before write, iclass 26, count 0 2006.173.20:58:53.84#ibcon#enter sib2, iclass 26, count 0 2006.173.20:58:53.84#ibcon#flushed, iclass 26, count 0 2006.173.20:58:53.84#ibcon#about to write, iclass 26, count 0 2006.173.20:58:53.84#ibcon#wrote, iclass 26, count 0 2006.173.20:58:53.84#ibcon#about to read 3, iclass 26, count 0 2006.173.20:58:53.88#ibcon#read 3, iclass 26, count 0 2006.173.20:58:53.88#ibcon#about to read 4, iclass 26, count 0 2006.173.20:58:53.88#ibcon#read 4, iclass 26, count 0 2006.173.20:58:53.88#ibcon#about to read 5, iclass 26, count 0 2006.173.20:58:53.88#ibcon#read 5, iclass 26, count 0 2006.173.20:58:53.88#ibcon#about to read 6, iclass 26, count 0 2006.173.20:58:53.88#ibcon#read 6, iclass 26, count 0 2006.173.20:58:53.88#ibcon#end of sib2, iclass 26, count 0 2006.173.20:58:53.88#ibcon#*after write, iclass 26, count 0 2006.173.20:58:53.88#ibcon#*before return 0, iclass 26, count 0 2006.173.20:58:53.88#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.20:58:53.88#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.20:58:53.88#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.20:58:53.88#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.20:58:53.88$vck44/va=6,3 2006.173.20:58:53.88#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.20:58:53.88#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.20:58:53.88#ibcon#ireg 11 cls_cnt 2 2006.173.20:58:53.88#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.20:58:53.94#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.20:58:53.94#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.20:58:53.94#ibcon#enter wrdev, iclass 28, count 2 2006.173.20:58:53.94#ibcon#first serial, iclass 28, count 2 2006.173.20:58:53.94#ibcon#enter sib2, iclass 28, count 2 2006.173.20:58:53.94#ibcon#flushed, iclass 28, count 2 2006.173.20:58:53.94#ibcon#about to write, iclass 28, count 2 2006.173.20:58:53.94#ibcon#wrote, iclass 28, count 2 2006.173.20:58:53.94#ibcon#about to read 3, iclass 28, count 2 2006.173.20:58:53.96#ibcon#read 3, iclass 28, count 2 2006.173.20:58:53.96#ibcon#about to read 4, iclass 28, count 2 2006.173.20:58:53.96#ibcon#read 4, iclass 28, count 2 2006.173.20:58:53.96#ibcon#about to read 5, iclass 28, count 2 2006.173.20:58:53.96#ibcon#read 5, iclass 28, count 2 2006.173.20:58:53.96#ibcon#about to read 6, iclass 28, count 2 2006.173.20:58:53.96#ibcon#read 6, iclass 28, count 2 2006.173.20:58:53.96#ibcon#end of sib2, iclass 28, count 2 2006.173.20:58:53.96#ibcon#*mode == 0, iclass 28, count 2 2006.173.20:58:53.96#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.20:58:53.96#ibcon#[25=AT06-03\r\n] 2006.173.20:58:53.96#ibcon#*before write, iclass 28, count 2 2006.173.20:58:53.96#ibcon#enter sib2, iclass 28, count 2 2006.173.20:58:53.96#ibcon#flushed, iclass 28, count 2 2006.173.20:58:53.96#ibcon#about to write, iclass 28, count 2 2006.173.20:58:53.96#ibcon#wrote, iclass 28, count 2 2006.173.20:58:53.96#ibcon#about to read 3, iclass 28, count 2 2006.173.20:58:53.99#ibcon#read 3, iclass 28, count 2 2006.173.20:58:53.99#ibcon#about to read 4, iclass 28, count 2 2006.173.20:58:53.99#ibcon#read 4, iclass 28, count 2 2006.173.20:58:53.99#ibcon#about to read 5, iclass 28, count 2 2006.173.20:58:53.99#ibcon#read 5, iclass 28, count 2 2006.173.20:58:53.99#ibcon#about to read 6, iclass 28, count 2 2006.173.20:58:53.99#ibcon#read 6, iclass 28, count 2 2006.173.20:58:53.99#ibcon#end of sib2, iclass 28, count 2 2006.173.20:58:53.99#ibcon#*after write, iclass 28, count 2 2006.173.20:58:53.99#ibcon#*before return 0, iclass 28, count 2 2006.173.20:58:53.99#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.20:58:53.99#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.20:58:53.99#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.20:58:53.99#ibcon#ireg 7 cls_cnt 0 2006.173.20:58:53.99#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.20:58:54.11#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.20:58:54.11#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.20:58:54.11#ibcon#enter wrdev, iclass 28, count 0 2006.173.20:58:54.11#ibcon#first serial, iclass 28, count 0 2006.173.20:58:54.11#ibcon#enter sib2, iclass 28, count 0 2006.173.20:58:54.11#ibcon#flushed, iclass 28, count 0 2006.173.20:58:54.11#ibcon#about to write, iclass 28, count 0 2006.173.20:58:54.11#ibcon#wrote, iclass 28, count 0 2006.173.20:58:54.11#ibcon#about to read 3, iclass 28, count 0 2006.173.20:58:54.13#ibcon#read 3, iclass 28, count 0 2006.173.20:58:54.13#ibcon#about to read 4, iclass 28, count 0 2006.173.20:58:54.13#ibcon#read 4, iclass 28, count 0 2006.173.20:58:54.13#ibcon#about to read 5, iclass 28, count 0 2006.173.20:58:54.13#ibcon#read 5, iclass 28, count 0 2006.173.20:58:54.13#ibcon#about to read 6, iclass 28, count 0 2006.173.20:58:54.13#ibcon#read 6, iclass 28, count 0 2006.173.20:58:54.13#ibcon#end of sib2, iclass 28, count 0 2006.173.20:58:54.13#ibcon#*mode == 0, iclass 28, count 0 2006.173.20:58:54.13#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.20:58:54.13#ibcon#[25=USB\r\n] 2006.173.20:58:54.13#ibcon#*before write, iclass 28, count 0 2006.173.20:58:54.13#ibcon#enter sib2, iclass 28, count 0 2006.173.20:58:54.13#ibcon#flushed, iclass 28, count 0 2006.173.20:58:54.13#ibcon#about to write, iclass 28, count 0 2006.173.20:58:54.13#ibcon#wrote, iclass 28, count 0 2006.173.20:58:54.13#ibcon#about to read 3, iclass 28, count 0 2006.173.20:58:54.16#ibcon#read 3, iclass 28, count 0 2006.173.20:58:54.16#ibcon#about to read 4, iclass 28, count 0 2006.173.20:58:54.16#ibcon#read 4, iclass 28, count 0 2006.173.20:58:54.16#ibcon#about to read 5, iclass 28, count 0 2006.173.20:58:54.16#ibcon#read 5, iclass 28, count 0 2006.173.20:58:54.16#ibcon#about to read 6, iclass 28, count 0 2006.173.20:58:54.16#ibcon#read 6, iclass 28, count 0 2006.173.20:58:54.16#ibcon#end of sib2, iclass 28, count 0 2006.173.20:58:54.16#ibcon#*after write, iclass 28, count 0 2006.173.20:58:54.16#ibcon#*before return 0, iclass 28, count 0 2006.173.20:58:54.16#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.20:58:54.16#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.20:58:54.16#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.20:58:54.16#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.20:58:54.16$vck44/valo=7,864.99 2006.173.20:58:54.16#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.20:58:54.16#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.20:58:54.16#ibcon#ireg 17 cls_cnt 0 2006.173.20:58:54.16#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.20:58:54.16#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.20:58:54.16#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.20:58:54.16#ibcon#enter wrdev, iclass 30, count 0 2006.173.20:58:54.16#ibcon#first serial, iclass 30, count 0 2006.173.20:58:54.16#ibcon#enter sib2, iclass 30, count 0 2006.173.20:58:54.16#ibcon#flushed, iclass 30, count 0 2006.173.20:58:54.16#ibcon#about to write, iclass 30, count 0 2006.173.20:58:54.16#ibcon#wrote, iclass 30, count 0 2006.173.20:58:54.16#ibcon#about to read 3, iclass 30, count 0 2006.173.20:58:54.18#ibcon#read 3, iclass 30, count 0 2006.173.20:58:54.18#ibcon#about to read 4, iclass 30, count 0 2006.173.20:58:54.18#ibcon#read 4, iclass 30, count 0 2006.173.20:58:54.18#ibcon#about to read 5, iclass 30, count 0 2006.173.20:58:54.18#ibcon#read 5, iclass 30, count 0 2006.173.20:58:54.18#ibcon#about to read 6, iclass 30, count 0 2006.173.20:58:54.18#ibcon#read 6, iclass 30, count 0 2006.173.20:58:54.18#ibcon#end of sib2, iclass 30, count 0 2006.173.20:58:54.18#ibcon#*mode == 0, iclass 30, count 0 2006.173.20:58:54.18#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.20:58:54.18#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.20:58:54.18#ibcon#*before write, iclass 30, count 0 2006.173.20:58:54.18#ibcon#enter sib2, iclass 30, count 0 2006.173.20:58:54.18#ibcon#flushed, iclass 30, count 0 2006.173.20:58:54.18#ibcon#about to write, iclass 30, count 0 2006.173.20:58:54.18#ibcon#wrote, iclass 30, count 0 2006.173.20:58:54.18#ibcon#about to read 3, iclass 30, count 0 2006.173.20:58:54.22#ibcon#read 3, iclass 30, count 0 2006.173.20:58:54.22#ibcon#about to read 4, iclass 30, count 0 2006.173.20:58:54.22#ibcon#read 4, iclass 30, count 0 2006.173.20:58:54.22#ibcon#about to read 5, iclass 30, count 0 2006.173.20:58:54.22#ibcon#read 5, iclass 30, count 0 2006.173.20:58:54.22#ibcon#about to read 6, iclass 30, count 0 2006.173.20:58:54.22#ibcon#read 6, iclass 30, count 0 2006.173.20:58:54.22#ibcon#end of sib2, iclass 30, count 0 2006.173.20:58:54.22#ibcon#*after write, iclass 30, count 0 2006.173.20:58:54.22#ibcon#*before return 0, iclass 30, count 0 2006.173.20:58:54.22#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.20:58:54.22#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.20:58:54.22#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.20:58:54.22#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.20:58:54.22$vck44/va=7,4 2006.173.20:58:54.22#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.173.20:58:54.22#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.173.20:58:54.22#ibcon#ireg 11 cls_cnt 2 2006.173.20:58:54.22#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.20:58:54.28#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.20:58:54.28#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.20:58:54.28#ibcon#enter wrdev, iclass 32, count 2 2006.173.20:58:54.28#ibcon#first serial, iclass 32, count 2 2006.173.20:58:54.28#ibcon#enter sib2, iclass 32, count 2 2006.173.20:58:54.28#ibcon#flushed, iclass 32, count 2 2006.173.20:58:54.28#ibcon#about to write, iclass 32, count 2 2006.173.20:58:54.28#ibcon#wrote, iclass 32, count 2 2006.173.20:58:54.28#ibcon#about to read 3, iclass 32, count 2 2006.173.20:58:54.30#ibcon#read 3, iclass 32, count 2 2006.173.20:58:54.30#ibcon#about to read 4, iclass 32, count 2 2006.173.20:58:54.30#ibcon#read 4, iclass 32, count 2 2006.173.20:58:54.30#ibcon#about to read 5, iclass 32, count 2 2006.173.20:58:54.30#ibcon#read 5, iclass 32, count 2 2006.173.20:58:54.30#ibcon#about to read 6, iclass 32, count 2 2006.173.20:58:54.30#ibcon#read 6, iclass 32, count 2 2006.173.20:58:54.30#ibcon#end of sib2, iclass 32, count 2 2006.173.20:58:54.30#ibcon#*mode == 0, iclass 32, count 2 2006.173.20:58:54.30#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.173.20:58:54.30#ibcon#[25=AT07-04\r\n] 2006.173.20:58:54.30#ibcon#*before write, iclass 32, count 2 2006.173.20:58:54.30#ibcon#enter sib2, iclass 32, count 2 2006.173.20:58:54.30#ibcon#flushed, iclass 32, count 2 2006.173.20:58:54.30#ibcon#about to write, iclass 32, count 2 2006.173.20:58:54.30#ibcon#wrote, iclass 32, count 2 2006.173.20:58:54.30#ibcon#about to read 3, iclass 32, count 2 2006.173.20:58:54.33#ibcon#read 3, iclass 32, count 2 2006.173.20:58:54.33#ibcon#about to read 4, iclass 32, count 2 2006.173.20:58:54.33#ibcon#read 4, iclass 32, count 2 2006.173.20:58:54.33#ibcon#about to read 5, iclass 32, count 2 2006.173.20:58:54.33#ibcon#read 5, iclass 32, count 2 2006.173.20:58:54.33#ibcon#about to read 6, iclass 32, count 2 2006.173.20:58:54.33#ibcon#read 6, iclass 32, count 2 2006.173.20:58:54.33#ibcon#end of sib2, iclass 32, count 2 2006.173.20:58:54.33#ibcon#*after write, iclass 32, count 2 2006.173.20:58:54.33#ibcon#*before return 0, iclass 32, count 2 2006.173.20:58:54.33#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.20:58:54.33#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.173.20:58:54.33#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.173.20:58:54.33#ibcon#ireg 7 cls_cnt 0 2006.173.20:58:54.33#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.20:58:54.45#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.20:58:54.45#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.20:58:54.45#ibcon#enter wrdev, iclass 32, count 0 2006.173.20:58:54.45#ibcon#first serial, iclass 32, count 0 2006.173.20:58:54.45#ibcon#enter sib2, iclass 32, count 0 2006.173.20:58:54.45#ibcon#flushed, iclass 32, count 0 2006.173.20:58:54.45#ibcon#about to write, iclass 32, count 0 2006.173.20:58:54.45#ibcon#wrote, iclass 32, count 0 2006.173.20:58:54.45#ibcon#about to read 3, iclass 32, count 0 2006.173.20:58:54.47#ibcon#read 3, iclass 32, count 0 2006.173.20:58:54.47#ibcon#about to read 4, iclass 32, count 0 2006.173.20:58:54.47#ibcon#read 4, iclass 32, count 0 2006.173.20:58:54.47#ibcon#about to read 5, iclass 32, count 0 2006.173.20:58:54.47#ibcon#read 5, iclass 32, count 0 2006.173.20:58:54.47#ibcon#about to read 6, iclass 32, count 0 2006.173.20:58:54.47#ibcon#read 6, iclass 32, count 0 2006.173.20:58:54.47#ibcon#end of sib2, iclass 32, count 0 2006.173.20:58:54.47#ibcon#*mode == 0, iclass 32, count 0 2006.173.20:58:54.47#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.20:58:54.47#ibcon#[25=USB\r\n] 2006.173.20:58:54.47#ibcon#*before write, iclass 32, count 0 2006.173.20:58:54.47#ibcon#enter sib2, iclass 32, count 0 2006.173.20:58:54.47#ibcon#flushed, iclass 32, count 0 2006.173.20:58:54.47#ibcon#about to write, iclass 32, count 0 2006.173.20:58:54.47#ibcon#wrote, iclass 32, count 0 2006.173.20:58:54.47#ibcon#about to read 3, iclass 32, count 0 2006.173.20:58:54.50#ibcon#read 3, iclass 32, count 0 2006.173.20:58:54.50#ibcon#about to read 4, iclass 32, count 0 2006.173.20:58:54.50#ibcon#read 4, iclass 32, count 0 2006.173.20:58:54.50#ibcon#about to read 5, iclass 32, count 0 2006.173.20:58:54.50#ibcon#read 5, iclass 32, count 0 2006.173.20:58:54.50#ibcon#about to read 6, iclass 32, count 0 2006.173.20:58:54.50#ibcon#read 6, iclass 32, count 0 2006.173.20:58:54.50#ibcon#end of sib2, iclass 32, count 0 2006.173.20:58:54.50#ibcon#*after write, iclass 32, count 0 2006.173.20:58:54.50#ibcon#*before return 0, iclass 32, count 0 2006.173.20:58:54.50#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.20:58:54.50#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.173.20:58:54.50#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.20:58:54.50#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.20:58:54.50$vck44/valo=8,884.99 2006.173.20:58:54.50#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.20:58:54.50#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.20:58:54.50#ibcon#ireg 17 cls_cnt 0 2006.173.20:58:54.50#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.20:58:54.50#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.20:58:54.50#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.20:58:54.50#ibcon#enter wrdev, iclass 34, count 0 2006.173.20:58:54.50#ibcon#first serial, iclass 34, count 0 2006.173.20:58:54.50#ibcon#enter sib2, iclass 34, count 0 2006.173.20:58:54.50#ibcon#flushed, iclass 34, count 0 2006.173.20:58:54.50#ibcon#about to write, iclass 34, count 0 2006.173.20:58:54.50#ibcon#wrote, iclass 34, count 0 2006.173.20:58:54.50#ibcon#about to read 3, iclass 34, count 0 2006.173.20:58:54.52#ibcon#read 3, iclass 34, count 0 2006.173.20:58:54.52#ibcon#about to read 4, iclass 34, count 0 2006.173.20:58:54.52#ibcon#read 4, iclass 34, count 0 2006.173.20:58:54.52#ibcon#about to read 5, iclass 34, count 0 2006.173.20:58:54.52#ibcon#read 5, iclass 34, count 0 2006.173.20:58:54.52#ibcon#about to read 6, iclass 34, count 0 2006.173.20:58:54.52#ibcon#read 6, iclass 34, count 0 2006.173.20:58:54.52#ibcon#end of sib2, iclass 34, count 0 2006.173.20:58:54.52#ibcon#*mode == 0, iclass 34, count 0 2006.173.20:58:54.52#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.20:58:54.52#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.20:58:54.52#ibcon#*before write, iclass 34, count 0 2006.173.20:58:54.52#ibcon#enter sib2, iclass 34, count 0 2006.173.20:58:54.52#ibcon#flushed, iclass 34, count 0 2006.173.20:58:54.52#ibcon#about to write, iclass 34, count 0 2006.173.20:58:54.52#ibcon#wrote, iclass 34, count 0 2006.173.20:58:54.52#ibcon#about to read 3, iclass 34, count 0 2006.173.20:58:54.56#ibcon#read 3, iclass 34, count 0 2006.173.20:58:54.56#ibcon#about to read 4, iclass 34, count 0 2006.173.20:58:54.56#ibcon#read 4, iclass 34, count 0 2006.173.20:58:54.56#ibcon#about to read 5, iclass 34, count 0 2006.173.20:58:54.56#ibcon#read 5, iclass 34, count 0 2006.173.20:58:54.56#ibcon#about to read 6, iclass 34, count 0 2006.173.20:58:54.56#ibcon#read 6, iclass 34, count 0 2006.173.20:58:54.56#ibcon#end of sib2, iclass 34, count 0 2006.173.20:58:54.56#ibcon#*after write, iclass 34, count 0 2006.173.20:58:54.56#ibcon#*before return 0, iclass 34, count 0 2006.173.20:58:54.56#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.20:58:54.56#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.20:58:54.56#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.20:58:54.56#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.20:58:54.56$vck44/va=8,4 2006.173.20:58:54.56#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.20:58:54.56#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.20:58:54.56#ibcon#ireg 11 cls_cnt 2 2006.173.20:58:54.56#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.20:58:54.62#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.20:58:54.62#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.20:58:54.62#ibcon#enter wrdev, iclass 36, count 2 2006.173.20:58:54.62#ibcon#first serial, iclass 36, count 2 2006.173.20:58:54.62#ibcon#enter sib2, iclass 36, count 2 2006.173.20:58:54.62#ibcon#flushed, iclass 36, count 2 2006.173.20:58:54.62#ibcon#about to write, iclass 36, count 2 2006.173.20:58:54.62#ibcon#wrote, iclass 36, count 2 2006.173.20:58:54.62#ibcon#about to read 3, iclass 36, count 2 2006.173.20:58:54.64#ibcon#read 3, iclass 36, count 2 2006.173.20:58:54.64#ibcon#about to read 4, iclass 36, count 2 2006.173.20:58:54.64#ibcon#read 4, iclass 36, count 2 2006.173.20:58:54.64#ibcon#about to read 5, iclass 36, count 2 2006.173.20:58:54.64#ibcon#read 5, iclass 36, count 2 2006.173.20:58:54.64#ibcon#about to read 6, iclass 36, count 2 2006.173.20:58:54.64#ibcon#read 6, iclass 36, count 2 2006.173.20:58:54.64#ibcon#end of sib2, iclass 36, count 2 2006.173.20:58:54.64#ibcon#*mode == 0, iclass 36, count 2 2006.173.20:58:54.64#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.20:58:54.64#ibcon#[25=AT08-04\r\n] 2006.173.20:58:54.64#ibcon#*before write, iclass 36, count 2 2006.173.20:58:54.64#ibcon#enter sib2, iclass 36, count 2 2006.173.20:58:54.64#ibcon#flushed, iclass 36, count 2 2006.173.20:58:54.64#ibcon#about to write, iclass 36, count 2 2006.173.20:58:54.64#ibcon#wrote, iclass 36, count 2 2006.173.20:58:54.64#ibcon#about to read 3, iclass 36, count 2 2006.173.20:58:54.67#ibcon#read 3, iclass 36, count 2 2006.173.20:58:54.67#ibcon#about to read 4, iclass 36, count 2 2006.173.20:58:54.67#ibcon#read 4, iclass 36, count 2 2006.173.20:58:54.67#ibcon#about to read 5, iclass 36, count 2 2006.173.20:58:54.67#ibcon#read 5, iclass 36, count 2 2006.173.20:58:54.67#ibcon#about to read 6, iclass 36, count 2 2006.173.20:58:54.67#ibcon#read 6, iclass 36, count 2 2006.173.20:58:54.67#ibcon#end of sib2, iclass 36, count 2 2006.173.20:58:54.67#ibcon#*after write, iclass 36, count 2 2006.173.20:58:54.67#ibcon#*before return 0, iclass 36, count 2 2006.173.20:58:54.67#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.20:58:54.67#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.20:58:54.67#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.20:58:54.67#ibcon#ireg 7 cls_cnt 0 2006.173.20:58:54.67#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.20:58:54.79#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.20:58:54.79#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.20:58:54.79#ibcon#enter wrdev, iclass 36, count 0 2006.173.20:58:54.79#ibcon#first serial, iclass 36, count 0 2006.173.20:58:54.79#ibcon#enter sib2, iclass 36, count 0 2006.173.20:58:54.79#ibcon#flushed, iclass 36, count 0 2006.173.20:58:54.79#ibcon#about to write, iclass 36, count 0 2006.173.20:58:54.79#ibcon#wrote, iclass 36, count 0 2006.173.20:58:54.79#ibcon#about to read 3, iclass 36, count 0 2006.173.20:58:54.81#ibcon#read 3, iclass 36, count 0 2006.173.20:58:54.81#ibcon#about to read 4, iclass 36, count 0 2006.173.20:58:54.81#ibcon#read 4, iclass 36, count 0 2006.173.20:58:54.81#ibcon#about to read 5, iclass 36, count 0 2006.173.20:58:54.81#ibcon#read 5, iclass 36, count 0 2006.173.20:58:54.81#ibcon#about to read 6, iclass 36, count 0 2006.173.20:58:54.81#ibcon#read 6, iclass 36, count 0 2006.173.20:58:54.81#ibcon#end of sib2, iclass 36, count 0 2006.173.20:58:54.81#ibcon#*mode == 0, iclass 36, count 0 2006.173.20:58:54.81#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.20:58:54.81#ibcon#[25=USB\r\n] 2006.173.20:58:54.81#ibcon#*before write, iclass 36, count 0 2006.173.20:58:54.81#ibcon#enter sib2, iclass 36, count 0 2006.173.20:58:54.81#ibcon#flushed, iclass 36, count 0 2006.173.20:58:54.81#ibcon#about to write, iclass 36, count 0 2006.173.20:58:54.81#ibcon#wrote, iclass 36, count 0 2006.173.20:58:54.81#ibcon#about to read 3, iclass 36, count 0 2006.173.20:58:54.84#ibcon#read 3, iclass 36, count 0 2006.173.20:58:54.84#ibcon#about to read 4, iclass 36, count 0 2006.173.20:58:54.84#ibcon#read 4, iclass 36, count 0 2006.173.20:58:54.84#ibcon#about to read 5, iclass 36, count 0 2006.173.20:58:54.84#ibcon#read 5, iclass 36, count 0 2006.173.20:58:54.84#ibcon#about to read 6, iclass 36, count 0 2006.173.20:58:54.84#ibcon#read 6, iclass 36, count 0 2006.173.20:58:54.84#ibcon#end of sib2, iclass 36, count 0 2006.173.20:58:54.84#ibcon#*after write, iclass 36, count 0 2006.173.20:58:54.84#ibcon#*before return 0, iclass 36, count 0 2006.173.20:58:54.84#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.20:58:54.84#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.20:58:54.84#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.20:58:54.84#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.20:58:54.84$vck44/vblo=1,629.99 2006.173.20:58:54.84#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.20:58:54.84#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.20:58:54.84#ibcon#ireg 17 cls_cnt 0 2006.173.20:58:54.84#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.20:58:54.84#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.20:58:54.84#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.20:58:54.84#ibcon#enter wrdev, iclass 38, count 0 2006.173.20:58:54.84#ibcon#first serial, iclass 38, count 0 2006.173.20:58:54.84#ibcon#enter sib2, iclass 38, count 0 2006.173.20:58:54.84#ibcon#flushed, iclass 38, count 0 2006.173.20:58:54.84#ibcon#about to write, iclass 38, count 0 2006.173.20:58:54.84#ibcon#wrote, iclass 38, count 0 2006.173.20:58:54.84#ibcon#about to read 3, iclass 38, count 0 2006.173.20:58:54.86#ibcon#read 3, iclass 38, count 0 2006.173.20:58:54.86#ibcon#about to read 4, iclass 38, count 0 2006.173.20:58:54.86#ibcon#read 4, iclass 38, count 0 2006.173.20:58:54.86#ibcon#about to read 5, iclass 38, count 0 2006.173.20:58:54.86#ibcon#read 5, iclass 38, count 0 2006.173.20:58:54.86#ibcon#about to read 6, iclass 38, count 0 2006.173.20:58:54.86#ibcon#read 6, iclass 38, count 0 2006.173.20:58:54.86#ibcon#end of sib2, iclass 38, count 0 2006.173.20:58:54.86#ibcon#*mode == 0, iclass 38, count 0 2006.173.20:58:54.86#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.20:58:54.86#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.20:58:54.86#ibcon#*before write, iclass 38, count 0 2006.173.20:58:54.86#ibcon#enter sib2, iclass 38, count 0 2006.173.20:58:54.86#ibcon#flushed, iclass 38, count 0 2006.173.20:58:54.86#ibcon#about to write, iclass 38, count 0 2006.173.20:58:54.86#ibcon#wrote, iclass 38, count 0 2006.173.20:58:54.86#ibcon#about to read 3, iclass 38, count 0 2006.173.20:58:54.90#ibcon#read 3, iclass 38, count 0 2006.173.20:58:54.90#ibcon#about to read 4, iclass 38, count 0 2006.173.20:58:54.90#ibcon#read 4, iclass 38, count 0 2006.173.20:58:54.90#ibcon#about to read 5, iclass 38, count 0 2006.173.20:58:54.90#ibcon#read 5, iclass 38, count 0 2006.173.20:58:54.90#ibcon#about to read 6, iclass 38, count 0 2006.173.20:58:54.90#ibcon#read 6, iclass 38, count 0 2006.173.20:58:54.90#ibcon#end of sib2, iclass 38, count 0 2006.173.20:58:54.90#ibcon#*after write, iclass 38, count 0 2006.173.20:58:54.90#ibcon#*before return 0, iclass 38, count 0 2006.173.20:58:54.90#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.20:58:54.90#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.20:58:54.90#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.20:58:54.90#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.20:58:54.90$vck44/vb=1,4 2006.173.20:58:54.90#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.20:58:54.90#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.20:58:54.90#ibcon#ireg 11 cls_cnt 2 2006.173.20:58:54.90#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.20:58:54.90#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.20:58:54.90#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.20:58:54.90#ibcon#enter wrdev, iclass 40, count 2 2006.173.20:58:54.90#ibcon#first serial, iclass 40, count 2 2006.173.20:58:54.90#ibcon#enter sib2, iclass 40, count 2 2006.173.20:58:54.90#ibcon#flushed, iclass 40, count 2 2006.173.20:58:54.90#ibcon#about to write, iclass 40, count 2 2006.173.20:58:54.90#ibcon#wrote, iclass 40, count 2 2006.173.20:58:54.90#ibcon#about to read 3, iclass 40, count 2 2006.173.20:58:54.92#ibcon#read 3, iclass 40, count 2 2006.173.20:58:54.92#ibcon#about to read 4, iclass 40, count 2 2006.173.20:58:54.92#ibcon#read 4, iclass 40, count 2 2006.173.20:58:54.92#ibcon#about to read 5, iclass 40, count 2 2006.173.20:58:54.92#ibcon#read 5, iclass 40, count 2 2006.173.20:58:54.92#ibcon#about to read 6, iclass 40, count 2 2006.173.20:58:54.92#ibcon#read 6, iclass 40, count 2 2006.173.20:58:54.92#ibcon#end of sib2, iclass 40, count 2 2006.173.20:58:54.92#ibcon#*mode == 0, iclass 40, count 2 2006.173.20:58:54.92#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.20:58:54.92#ibcon#[27=AT01-04\r\n] 2006.173.20:58:54.92#ibcon#*before write, iclass 40, count 2 2006.173.20:58:54.92#ibcon#enter sib2, iclass 40, count 2 2006.173.20:58:54.92#ibcon#flushed, iclass 40, count 2 2006.173.20:58:54.92#ibcon#about to write, iclass 40, count 2 2006.173.20:58:54.92#ibcon#wrote, iclass 40, count 2 2006.173.20:58:54.92#ibcon#about to read 3, iclass 40, count 2 2006.173.20:58:54.95#ibcon#read 3, iclass 40, count 2 2006.173.20:58:54.95#ibcon#about to read 4, iclass 40, count 2 2006.173.20:58:54.95#ibcon#read 4, iclass 40, count 2 2006.173.20:58:54.95#ibcon#about to read 5, iclass 40, count 2 2006.173.20:58:54.95#ibcon#read 5, iclass 40, count 2 2006.173.20:58:54.95#ibcon#about to read 6, iclass 40, count 2 2006.173.20:58:54.95#ibcon#read 6, iclass 40, count 2 2006.173.20:58:54.95#ibcon#end of sib2, iclass 40, count 2 2006.173.20:58:54.95#ibcon#*after write, iclass 40, count 2 2006.173.20:58:54.95#ibcon#*before return 0, iclass 40, count 2 2006.173.20:58:54.95#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.20:58:54.95#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.20:58:54.95#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.20:58:54.95#ibcon#ireg 7 cls_cnt 0 2006.173.20:58:54.95#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.20:58:55.07#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.20:58:55.07#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.20:58:55.07#ibcon#enter wrdev, iclass 40, count 0 2006.173.20:58:55.07#ibcon#first serial, iclass 40, count 0 2006.173.20:58:55.07#ibcon#enter sib2, iclass 40, count 0 2006.173.20:58:55.07#ibcon#flushed, iclass 40, count 0 2006.173.20:58:55.07#ibcon#about to write, iclass 40, count 0 2006.173.20:58:55.07#ibcon#wrote, iclass 40, count 0 2006.173.20:58:55.07#ibcon#about to read 3, iclass 40, count 0 2006.173.20:58:55.09#ibcon#read 3, iclass 40, count 0 2006.173.20:58:55.09#ibcon#about to read 4, iclass 40, count 0 2006.173.20:58:55.09#ibcon#read 4, iclass 40, count 0 2006.173.20:58:55.09#ibcon#about to read 5, iclass 40, count 0 2006.173.20:58:55.09#ibcon#read 5, iclass 40, count 0 2006.173.20:58:55.09#ibcon#about to read 6, iclass 40, count 0 2006.173.20:58:55.09#ibcon#read 6, iclass 40, count 0 2006.173.20:58:55.09#ibcon#end of sib2, iclass 40, count 0 2006.173.20:58:55.09#ibcon#*mode == 0, iclass 40, count 0 2006.173.20:58:55.09#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.20:58:55.09#ibcon#[27=USB\r\n] 2006.173.20:58:55.09#ibcon#*before write, iclass 40, count 0 2006.173.20:58:55.09#ibcon#enter sib2, iclass 40, count 0 2006.173.20:58:55.09#ibcon#flushed, iclass 40, count 0 2006.173.20:58:55.09#ibcon#about to write, iclass 40, count 0 2006.173.20:58:55.09#ibcon#wrote, iclass 40, count 0 2006.173.20:58:55.09#ibcon#about to read 3, iclass 40, count 0 2006.173.20:58:55.12#ibcon#read 3, iclass 40, count 0 2006.173.20:58:55.12#ibcon#about to read 4, iclass 40, count 0 2006.173.20:58:55.12#ibcon#read 4, iclass 40, count 0 2006.173.20:58:55.12#ibcon#about to read 5, iclass 40, count 0 2006.173.20:58:55.12#ibcon#read 5, iclass 40, count 0 2006.173.20:58:55.12#ibcon#about to read 6, iclass 40, count 0 2006.173.20:58:55.12#ibcon#read 6, iclass 40, count 0 2006.173.20:58:55.12#ibcon#end of sib2, iclass 40, count 0 2006.173.20:58:55.12#ibcon#*after write, iclass 40, count 0 2006.173.20:58:55.12#ibcon#*before return 0, iclass 40, count 0 2006.173.20:58:55.12#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.20:58:55.12#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.20:58:55.12#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.20:58:55.12#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.20:58:55.12$vck44/vblo=2,634.99 2006.173.20:58:55.12#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.20:58:55.12#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.20:58:55.12#ibcon#ireg 17 cls_cnt 0 2006.173.20:58:55.12#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.20:58:55.12#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.20:58:55.12#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.20:58:55.12#ibcon#enter wrdev, iclass 4, count 0 2006.173.20:58:55.12#ibcon#first serial, iclass 4, count 0 2006.173.20:58:55.12#ibcon#enter sib2, iclass 4, count 0 2006.173.20:58:55.12#ibcon#flushed, iclass 4, count 0 2006.173.20:58:55.12#ibcon#about to write, iclass 4, count 0 2006.173.20:58:55.12#ibcon#wrote, iclass 4, count 0 2006.173.20:58:55.12#ibcon#about to read 3, iclass 4, count 0 2006.173.20:58:55.14#ibcon#read 3, iclass 4, count 0 2006.173.20:58:55.14#ibcon#about to read 4, iclass 4, count 0 2006.173.20:58:55.14#ibcon#read 4, iclass 4, count 0 2006.173.20:58:55.14#ibcon#about to read 5, iclass 4, count 0 2006.173.20:58:55.14#ibcon#read 5, iclass 4, count 0 2006.173.20:58:55.14#ibcon#about to read 6, iclass 4, count 0 2006.173.20:58:55.14#ibcon#read 6, iclass 4, count 0 2006.173.20:58:55.14#ibcon#end of sib2, iclass 4, count 0 2006.173.20:58:55.14#ibcon#*mode == 0, iclass 4, count 0 2006.173.20:58:55.14#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.20:58:55.14#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.20:58:55.14#ibcon#*before write, iclass 4, count 0 2006.173.20:58:55.14#ibcon#enter sib2, iclass 4, count 0 2006.173.20:58:55.14#ibcon#flushed, iclass 4, count 0 2006.173.20:58:55.14#ibcon#about to write, iclass 4, count 0 2006.173.20:58:55.14#ibcon#wrote, iclass 4, count 0 2006.173.20:58:55.14#ibcon#about to read 3, iclass 4, count 0 2006.173.20:58:55.18#ibcon#read 3, iclass 4, count 0 2006.173.20:58:55.18#ibcon#about to read 4, iclass 4, count 0 2006.173.20:58:55.18#ibcon#read 4, iclass 4, count 0 2006.173.20:58:55.18#ibcon#about to read 5, iclass 4, count 0 2006.173.20:58:55.18#ibcon#read 5, iclass 4, count 0 2006.173.20:58:55.18#ibcon#about to read 6, iclass 4, count 0 2006.173.20:58:55.18#ibcon#read 6, iclass 4, count 0 2006.173.20:58:55.18#ibcon#end of sib2, iclass 4, count 0 2006.173.20:58:55.18#ibcon#*after write, iclass 4, count 0 2006.173.20:58:55.18#ibcon#*before return 0, iclass 4, count 0 2006.173.20:58:55.18#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.20:58:55.18#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.20:58:55.18#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.20:58:55.18#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.20:58:55.18$vck44/vb=2,4 2006.173.20:58:55.18#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.20:58:55.18#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.20:58:55.18#ibcon#ireg 11 cls_cnt 2 2006.173.20:58:55.18#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.20:58:55.24#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.20:58:55.24#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.20:58:55.24#ibcon#enter wrdev, iclass 6, count 2 2006.173.20:58:55.24#ibcon#first serial, iclass 6, count 2 2006.173.20:58:55.24#ibcon#enter sib2, iclass 6, count 2 2006.173.20:58:55.24#ibcon#flushed, iclass 6, count 2 2006.173.20:58:55.24#ibcon#about to write, iclass 6, count 2 2006.173.20:58:55.24#ibcon#wrote, iclass 6, count 2 2006.173.20:58:55.24#ibcon#about to read 3, iclass 6, count 2 2006.173.20:58:55.26#ibcon#read 3, iclass 6, count 2 2006.173.20:58:55.26#ibcon#about to read 4, iclass 6, count 2 2006.173.20:58:55.26#ibcon#read 4, iclass 6, count 2 2006.173.20:58:55.26#ibcon#about to read 5, iclass 6, count 2 2006.173.20:58:55.26#ibcon#read 5, iclass 6, count 2 2006.173.20:58:55.26#ibcon#about to read 6, iclass 6, count 2 2006.173.20:58:55.26#ibcon#read 6, iclass 6, count 2 2006.173.20:58:55.26#ibcon#end of sib2, iclass 6, count 2 2006.173.20:58:55.26#ibcon#*mode == 0, iclass 6, count 2 2006.173.20:58:55.26#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.20:58:55.26#ibcon#[27=AT02-04\r\n] 2006.173.20:58:55.26#ibcon#*before write, iclass 6, count 2 2006.173.20:58:55.26#ibcon#enter sib2, iclass 6, count 2 2006.173.20:58:55.26#ibcon#flushed, iclass 6, count 2 2006.173.20:58:55.26#ibcon#about to write, iclass 6, count 2 2006.173.20:58:55.26#ibcon#wrote, iclass 6, count 2 2006.173.20:58:55.26#ibcon#about to read 3, iclass 6, count 2 2006.173.20:58:55.29#ibcon#read 3, iclass 6, count 2 2006.173.20:58:55.29#ibcon#about to read 4, iclass 6, count 2 2006.173.20:58:55.29#ibcon#read 4, iclass 6, count 2 2006.173.20:58:55.29#ibcon#about to read 5, iclass 6, count 2 2006.173.20:58:55.29#ibcon#read 5, iclass 6, count 2 2006.173.20:58:55.29#ibcon#about to read 6, iclass 6, count 2 2006.173.20:58:55.29#ibcon#read 6, iclass 6, count 2 2006.173.20:58:55.29#ibcon#end of sib2, iclass 6, count 2 2006.173.20:58:55.29#ibcon#*after write, iclass 6, count 2 2006.173.20:58:55.29#ibcon#*before return 0, iclass 6, count 2 2006.173.20:58:55.29#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.20:58:55.29#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.20:58:55.29#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.20:58:55.29#ibcon#ireg 7 cls_cnt 0 2006.173.20:58:55.29#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.20:58:55.41#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.20:58:55.41#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.20:58:55.41#ibcon#enter wrdev, iclass 6, count 0 2006.173.20:58:55.41#ibcon#first serial, iclass 6, count 0 2006.173.20:58:55.41#ibcon#enter sib2, iclass 6, count 0 2006.173.20:58:55.41#ibcon#flushed, iclass 6, count 0 2006.173.20:58:55.41#ibcon#about to write, iclass 6, count 0 2006.173.20:58:55.41#ibcon#wrote, iclass 6, count 0 2006.173.20:58:55.41#ibcon#about to read 3, iclass 6, count 0 2006.173.20:58:55.43#ibcon#read 3, iclass 6, count 0 2006.173.20:58:55.43#ibcon#about to read 4, iclass 6, count 0 2006.173.20:58:55.43#ibcon#read 4, iclass 6, count 0 2006.173.20:58:55.43#ibcon#about to read 5, iclass 6, count 0 2006.173.20:58:55.43#ibcon#read 5, iclass 6, count 0 2006.173.20:58:55.43#ibcon#about to read 6, iclass 6, count 0 2006.173.20:58:55.43#ibcon#read 6, iclass 6, count 0 2006.173.20:58:55.43#ibcon#end of sib2, iclass 6, count 0 2006.173.20:58:55.43#ibcon#*mode == 0, iclass 6, count 0 2006.173.20:58:55.43#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.20:58:55.43#ibcon#[27=USB\r\n] 2006.173.20:58:55.43#ibcon#*before write, iclass 6, count 0 2006.173.20:58:55.43#ibcon#enter sib2, iclass 6, count 0 2006.173.20:58:55.43#ibcon#flushed, iclass 6, count 0 2006.173.20:58:55.43#ibcon#about to write, iclass 6, count 0 2006.173.20:58:55.43#ibcon#wrote, iclass 6, count 0 2006.173.20:58:55.43#ibcon#about to read 3, iclass 6, count 0 2006.173.20:58:55.46#ibcon#read 3, iclass 6, count 0 2006.173.20:58:55.46#ibcon#about to read 4, iclass 6, count 0 2006.173.20:58:55.46#ibcon#read 4, iclass 6, count 0 2006.173.20:58:55.46#ibcon#about to read 5, iclass 6, count 0 2006.173.20:58:55.46#ibcon#read 5, iclass 6, count 0 2006.173.20:58:55.46#ibcon#about to read 6, iclass 6, count 0 2006.173.20:58:55.46#ibcon#read 6, iclass 6, count 0 2006.173.20:58:55.46#ibcon#end of sib2, iclass 6, count 0 2006.173.20:58:55.46#ibcon#*after write, iclass 6, count 0 2006.173.20:58:55.46#ibcon#*before return 0, iclass 6, count 0 2006.173.20:58:55.46#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.20:58:55.46#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.20:58:55.46#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.20:58:55.46#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.20:58:55.46$vck44/vblo=3,649.99 2006.173.20:58:55.46#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.20:58:55.46#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.20:58:55.46#ibcon#ireg 17 cls_cnt 0 2006.173.20:58:55.46#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.20:58:55.46#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.20:58:55.46#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.20:58:55.46#ibcon#enter wrdev, iclass 10, count 0 2006.173.20:58:55.46#ibcon#first serial, iclass 10, count 0 2006.173.20:58:55.46#ibcon#enter sib2, iclass 10, count 0 2006.173.20:58:55.46#ibcon#flushed, iclass 10, count 0 2006.173.20:58:55.46#ibcon#about to write, iclass 10, count 0 2006.173.20:58:55.46#ibcon#wrote, iclass 10, count 0 2006.173.20:58:55.46#ibcon#about to read 3, iclass 10, count 0 2006.173.20:58:55.48#ibcon#read 3, iclass 10, count 0 2006.173.20:58:55.48#ibcon#about to read 4, iclass 10, count 0 2006.173.20:58:55.48#ibcon#read 4, iclass 10, count 0 2006.173.20:58:55.48#ibcon#about to read 5, iclass 10, count 0 2006.173.20:58:55.48#ibcon#read 5, iclass 10, count 0 2006.173.20:58:55.48#ibcon#about to read 6, iclass 10, count 0 2006.173.20:58:55.48#ibcon#read 6, iclass 10, count 0 2006.173.20:58:55.48#ibcon#end of sib2, iclass 10, count 0 2006.173.20:58:55.48#ibcon#*mode == 0, iclass 10, count 0 2006.173.20:58:55.48#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.20:58:55.48#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.20:58:55.48#ibcon#*before write, iclass 10, count 0 2006.173.20:58:55.48#ibcon#enter sib2, iclass 10, count 0 2006.173.20:58:55.48#ibcon#flushed, iclass 10, count 0 2006.173.20:58:55.48#ibcon#about to write, iclass 10, count 0 2006.173.20:58:55.48#ibcon#wrote, iclass 10, count 0 2006.173.20:58:55.48#ibcon#about to read 3, iclass 10, count 0 2006.173.20:58:55.52#ibcon#read 3, iclass 10, count 0 2006.173.20:58:55.52#ibcon#about to read 4, iclass 10, count 0 2006.173.20:58:55.52#ibcon#read 4, iclass 10, count 0 2006.173.20:58:55.52#ibcon#about to read 5, iclass 10, count 0 2006.173.20:58:55.52#ibcon#read 5, iclass 10, count 0 2006.173.20:58:55.52#ibcon#about to read 6, iclass 10, count 0 2006.173.20:58:55.52#ibcon#read 6, iclass 10, count 0 2006.173.20:58:55.52#ibcon#end of sib2, iclass 10, count 0 2006.173.20:58:55.52#ibcon#*after write, iclass 10, count 0 2006.173.20:58:55.52#ibcon#*before return 0, iclass 10, count 0 2006.173.20:58:55.52#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.20:58:55.52#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.20:58:55.52#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.20:58:55.52#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.20:58:55.52$vck44/vb=3,4 2006.173.20:58:55.52#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.20:58:55.52#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.20:58:55.52#ibcon#ireg 11 cls_cnt 2 2006.173.20:58:55.52#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.20:58:55.58#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.20:58:55.58#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.20:58:55.58#ibcon#enter wrdev, iclass 12, count 2 2006.173.20:58:55.58#ibcon#first serial, iclass 12, count 2 2006.173.20:58:55.58#ibcon#enter sib2, iclass 12, count 2 2006.173.20:58:55.58#ibcon#flushed, iclass 12, count 2 2006.173.20:58:55.58#ibcon#about to write, iclass 12, count 2 2006.173.20:58:55.58#ibcon#wrote, iclass 12, count 2 2006.173.20:58:55.58#ibcon#about to read 3, iclass 12, count 2 2006.173.20:58:55.60#ibcon#read 3, iclass 12, count 2 2006.173.20:58:55.60#ibcon#about to read 4, iclass 12, count 2 2006.173.20:58:55.60#ibcon#read 4, iclass 12, count 2 2006.173.20:58:55.60#ibcon#about to read 5, iclass 12, count 2 2006.173.20:58:55.60#ibcon#read 5, iclass 12, count 2 2006.173.20:58:55.60#ibcon#about to read 6, iclass 12, count 2 2006.173.20:58:55.60#ibcon#read 6, iclass 12, count 2 2006.173.20:58:55.60#ibcon#end of sib2, iclass 12, count 2 2006.173.20:58:55.60#ibcon#*mode == 0, iclass 12, count 2 2006.173.20:58:55.60#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.20:58:55.60#ibcon#[27=AT03-04\r\n] 2006.173.20:58:55.60#ibcon#*before write, iclass 12, count 2 2006.173.20:58:55.60#ibcon#enter sib2, iclass 12, count 2 2006.173.20:58:55.60#ibcon#flushed, iclass 12, count 2 2006.173.20:58:55.60#ibcon#about to write, iclass 12, count 2 2006.173.20:58:55.60#ibcon#wrote, iclass 12, count 2 2006.173.20:58:55.60#ibcon#about to read 3, iclass 12, count 2 2006.173.20:58:55.63#ibcon#read 3, iclass 12, count 2 2006.173.20:58:55.63#ibcon#about to read 4, iclass 12, count 2 2006.173.20:58:55.63#ibcon#read 4, iclass 12, count 2 2006.173.20:58:55.63#ibcon#about to read 5, iclass 12, count 2 2006.173.20:58:55.63#ibcon#read 5, iclass 12, count 2 2006.173.20:58:55.63#ibcon#about to read 6, iclass 12, count 2 2006.173.20:58:55.63#ibcon#read 6, iclass 12, count 2 2006.173.20:58:55.63#ibcon#end of sib2, iclass 12, count 2 2006.173.20:58:55.63#ibcon#*after write, iclass 12, count 2 2006.173.20:58:55.63#ibcon#*before return 0, iclass 12, count 2 2006.173.20:58:55.63#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.20:58:55.63#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.20:58:55.63#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.20:58:55.63#ibcon#ireg 7 cls_cnt 0 2006.173.20:58:55.63#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.20:58:55.75#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.20:58:55.75#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.20:58:55.75#ibcon#enter wrdev, iclass 12, count 0 2006.173.20:58:55.75#ibcon#first serial, iclass 12, count 0 2006.173.20:58:55.75#ibcon#enter sib2, iclass 12, count 0 2006.173.20:58:55.75#ibcon#flushed, iclass 12, count 0 2006.173.20:58:55.75#ibcon#about to write, iclass 12, count 0 2006.173.20:58:55.75#ibcon#wrote, iclass 12, count 0 2006.173.20:58:55.75#ibcon#about to read 3, iclass 12, count 0 2006.173.20:58:55.77#ibcon#read 3, iclass 12, count 0 2006.173.20:58:55.77#ibcon#about to read 4, iclass 12, count 0 2006.173.20:58:55.77#ibcon#read 4, iclass 12, count 0 2006.173.20:58:55.77#ibcon#about to read 5, iclass 12, count 0 2006.173.20:58:55.77#ibcon#read 5, iclass 12, count 0 2006.173.20:58:55.77#ibcon#about to read 6, iclass 12, count 0 2006.173.20:58:55.77#ibcon#read 6, iclass 12, count 0 2006.173.20:58:55.77#ibcon#end of sib2, iclass 12, count 0 2006.173.20:58:55.77#ibcon#*mode == 0, iclass 12, count 0 2006.173.20:58:55.77#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.20:58:55.77#ibcon#[27=USB\r\n] 2006.173.20:58:55.77#ibcon#*before write, iclass 12, count 0 2006.173.20:58:55.77#ibcon#enter sib2, iclass 12, count 0 2006.173.20:58:55.77#ibcon#flushed, iclass 12, count 0 2006.173.20:58:55.77#ibcon#about to write, iclass 12, count 0 2006.173.20:58:55.77#ibcon#wrote, iclass 12, count 0 2006.173.20:58:55.77#ibcon#about to read 3, iclass 12, count 0 2006.173.20:58:55.80#ibcon#read 3, iclass 12, count 0 2006.173.20:58:55.80#ibcon#about to read 4, iclass 12, count 0 2006.173.20:58:55.80#ibcon#read 4, iclass 12, count 0 2006.173.20:58:55.80#ibcon#about to read 5, iclass 12, count 0 2006.173.20:58:55.80#ibcon#read 5, iclass 12, count 0 2006.173.20:58:55.80#ibcon#about to read 6, iclass 12, count 0 2006.173.20:58:55.80#ibcon#read 6, iclass 12, count 0 2006.173.20:58:55.80#ibcon#end of sib2, iclass 12, count 0 2006.173.20:58:55.80#ibcon#*after write, iclass 12, count 0 2006.173.20:58:55.80#ibcon#*before return 0, iclass 12, count 0 2006.173.20:58:55.80#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.20:58:55.80#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.20:58:55.80#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.20:58:55.80#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.20:58:55.80$vck44/vblo=4,679.99 2006.173.20:58:55.80#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.20:58:55.80#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.20:58:55.80#ibcon#ireg 17 cls_cnt 0 2006.173.20:58:55.80#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.20:58:55.80#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.20:58:55.80#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.20:58:55.80#ibcon#enter wrdev, iclass 14, count 0 2006.173.20:58:55.80#ibcon#first serial, iclass 14, count 0 2006.173.20:58:55.80#ibcon#enter sib2, iclass 14, count 0 2006.173.20:58:55.80#ibcon#flushed, iclass 14, count 0 2006.173.20:58:55.80#ibcon#about to write, iclass 14, count 0 2006.173.20:58:55.80#ibcon#wrote, iclass 14, count 0 2006.173.20:58:55.80#ibcon#about to read 3, iclass 14, count 0 2006.173.20:58:55.82#ibcon#read 3, iclass 14, count 0 2006.173.20:58:55.82#ibcon#about to read 4, iclass 14, count 0 2006.173.20:58:55.82#ibcon#read 4, iclass 14, count 0 2006.173.20:58:55.82#ibcon#about to read 5, iclass 14, count 0 2006.173.20:58:55.82#ibcon#read 5, iclass 14, count 0 2006.173.20:58:55.82#ibcon#about to read 6, iclass 14, count 0 2006.173.20:58:55.82#ibcon#read 6, iclass 14, count 0 2006.173.20:58:55.82#ibcon#end of sib2, iclass 14, count 0 2006.173.20:58:55.82#ibcon#*mode == 0, iclass 14, count 0 2006.173.20:58:55.82#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.20:58:55.82#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.20:58:55.82#ibcon#*before write, iclass 14, count 0 2006.173.20:58:55.82#ibcon#enter sib2, iclass 14, count 0 2006.173.20:58:55.82#ibcon#flushed, iclass 14, count 0 2006.173.20:58:55.82#ibcon#about to write, iclass 14, count 0 2006.173.20:58:55.82#ibcon#wrote, iclass 14, count 0 2006.173.20:58:55.82#ibcon#about to read 3, iclass 14, count 0 2006.173.20:58:55.86#ibcon#read 3, iclass 14, count 0 2006.173.20:58:55.86#ibcon#about to read 4, iclass 14, count 0 2006.173.20:58:55.86#ibcon#read 4, iclass 14, count 0 2006.173.20:58:55.86#ibcon#about to read 5, iclass 14, count 0 2006.173.20:58:55.86#ibcon#read 5, iclass 14, count 0 2006.173.20:58:55.86#ibcon#about to read 6, iclass 14, count 0 2006.173.20:58:55.86#ibcon#read 6, iclass 14, count 0 2006.173.20:58:55.86#ibcon#end of sib2, iclass 14, count 0 2006.173.20:58:55.86#ibcon#*after write, iclass 14, count 0 2006.173.20:58:55.86#ibcon#*before return 0, iclass 14, count 0 2006.173.20:58:55.86#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.20:58:55.86#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.20:58:55.86#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.20:58:55.86#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.20:58:55.86$vck44/vb=4,4 2006.173.20:58:55.86#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.20:58:55.86#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.20:58:55.86#ibcon#ireg 11 cls_cnt 2 2006.173.20:58:55.86#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.20:58:55.92#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.20:58:55.92#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.20:58:55.92#ibcon#enter wrdev, iclass 16, count 2 2006.173.20:58:55.92#ibcon#first serial, iclass 16, count 2 2006.173.20:58:55.92#ibcon#enter sib2, iclass 16, count 2 2006.173.20:58:55.92#ibcon#flushed, iclass 16, count 2 2006.173.20:58:55.92#ibcon#about to write, iclass 16, count 2 2006.173.20:58:55.92#ibcon#wrote, iclass 16, count 2 2006.173.20:58:55.92#ibcon#about to read 3, iclass 16, count 2 2006.173.20:58:55.94#ibcon#read 3, iclass 16, count 2 2006.173.20:58:55.94#ibcon#about to read 4, iclass 16, count 2 2006.173.20:58:55.94#ibcon#read 4, iclass 16, count 2 2006.173.20:58:55.94#ibcon#about to read 5, iclass 16, count 2 2006.173.20:58:55.94#ibcon#read 5, iclass 16, count 2 2006.173.20:58:55.94#ibcon#about to read 6, iclass 16, count 2 2006.173.20:58:55.94#ibcon#read 6, iclass 16, count 2 2006.173.20:58:55.94#ibcon#end of sib2, iclass 16, count 2 2006.173.20:58:55.94#ibcon#*mode == 0, iclass 16, count 2 2006.173.20:58:55.94#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.20:58:55.94#ibcon#[27=AT04-04\r\n] 2006.173.20:58:55.94#ibcon#*before write, iclass 16, count 2 2006.173.20:58:55.94#ibcon#enter sib2, iclass 16, count 2 2006.173.20:58:55.94#ibcon#flushed, iclass 16, count 2 2006.173.20:58:55.94#ibcon#about to write, iclass 16, count 2 2006.173.20:58:55.94#ibcon#wrote, iclass 16, count 2 2006.173.20:58:55.94#ibcon#about to read 3, iclass 16, count 2 2006.173.20:58:55.97#ibcon#read 3, iclass 16, count 2 2006.173.20:58:55.97#ibcon#about to read 4, iclass 16, count 2 2006.173.20:58:55.97#ibcon#read 4, iclass 16, count 2 2006.173.20:58:55.97#ibcon#about to read 5, iclass 16, count 2 2006.173.20:58:55.97#ibcon#read 5, iclass 16, count 2 2006.173.20:58:55.97#ibcon#about to read 6, iclass 16, count 2 2006.173.20:58:55.97#ibcon#read 6, iclass 16, count 2 2006.173.20:58:55.97#ibcon#end of sib2, iclass 16, count 2 2006.173.20:58:55.97#ibcon#*after write, iclass 16, count 2 2006.173.20:58:55.97#ibcon#*before return 0, iclass 16, count 2 2006.173.20:58:55.97#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.20:58:55.97#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.20:58:55.97#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.20:58:55.97#ibcon#ireg 7 cls_cnt 0 2006.173.20:58:55.97#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.20:58:56.09#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.20:58:56.09#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.20:58:56.09#ibcon#enter wrdev, iclass 16, count 0 2006.173.20:58:56.09#ibcon#first serial, iclass 16, count 0 2006.173.20:58:56.09#ibcon#enter sib2, iclass 16, count 0 2006.173.20:58:56.09#ibcon#flushed, iclass 16, count 0 2006.173.20:58:56.09#ibcon#about to write, iclass 16, count 0 2006.173.20:58:56.09#ibcon#wrote, iclass 16, count 0 2006.173.20:58:56.09#ibcon#about to read 3, iclass 16, count 0 2006.173.20:58:56.11#ibcon#read 3, iclass 16, count 0 2006.173.20:58:56.11#ibcon#about to read 4, iclass 16, count 0 2006.173.20:58:56.11#ibcon#read 4, iclass 16, count 0 2006.173.20:58:56.11#ibcon#about to read 5, iclass 16, count 0 2006.173.20:58:56.11#ibcon#read 5, iclass 16, count 0 2006.173.20:58:56.11#ibcon#about to read 6, iclass 16, count 0 2006.173.20:58:56.11#ibcon#read 6, iclass 16, count 0 2006.173.20:58:56.11#ibcon#end of sib2, iclass 16, count 0 2006.173.20:58:56.11#ibcon#*mode == 0, iclass 16, count 0 2006.173.20:58:56.11#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.20:58:56.11#ibcon#[27=USB\r\n] 2006.173.20:58:56.11#ibcon#*before write, iclass 16, count 0 2006.173.20:58:56.11#ibcon#enter sib2, iclass 16, count 0 2006.173.20:58:56.11#ibcon#flushed, iclass 16, count 0 2006.173.20:58:56.11#ibcon#about to write, iclass 16, count 0 2006.173.20:58:56.11#ibcon#wrote, iclass 16, count 0 2006.173.20:58:56.11#ibcon#about to read 3, iclass 16, count 0 2006.173.20:58:56.14#ibcon#read 3, iclass 16, count 0 2006.173.20:58:56.14#ibcon#about to read 4, iclass 16, count 0 2006.173.20:58:56.14#ibcon#read 4, iclass 16, count 0 2006.173.20:58:56.14#ibcon#about to read 5, iclass 16, count 0 2006.173.20:58:56.14#ibcon#read 5, iclass 16, count 0 2006.173.20:58:56.14#ibcon#about to read 6, iclass 16, count 0 2006.173.20:58:56.14#ibcon#read 6, iclass 16, count 0 2006.173.20:58:56.14#ibcon#end of sib2, iclass 16, count 0 2006.173.20:58:56.14#ibcon#*after write, iclass 16, count 0 2006.173.20:58:56.14#ibcon#*before return 0, iclass 16, count 0 2006.173.20:58:56.14#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.20:58:56.14#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.20:58:56.14#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.20:58:56.14#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.20:58:56.14$vck44/vblo=5,709.99 2006.173.20:58:56.14#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.20:58:56.14#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.20:58:56.14#ibcon#ireg 17 cls_cnt 0 2006.173.20:58:56.14#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.20:58:56.14#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.20:58:56.14#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.20:58:56.14#ibcon#enter wrdev, iclass 18, count 0 2006.173.20:58:56.14#ibcon#first serial, iclass 18, count 0 2006.173.20:58:56.14#ibcon#enter sib2, iclass 18, count 0 2006.173.20:58:56.14#ibcon#flushed, iclass 18, count 0 2006.173.20:58:56.14#ibcon#about to write, iclass 18, count 0 2006.173.20:58:56.14#ibcon#wrote, iclass 18, count 0 2006.173.20:58:56.14#ibcon#about to read 3, iclass 18, count 0 2006.173.20:58:56.16#ibcon#read 3, iclass 18, count 0 2006.173.20:58:56.16#ibcon#about to read 4, iclass 18, count 0 2006.173.20:58:56.16#ibcon#read 4, iclass 18, count 0 2006.173.20:58:56.16#ibcon#about to read 5, iclass 18, count 0 2006.173.20:58:56.16#ibcon#read 5, iclass 18, count 0 2006.173.20:58:56.16#ibcon#about to read 6, iclass 18, count 0 2006.173.20:58:56.16#ibcon#read 6, iclass 18, count 0 2006.173.20:58:56.16#ibcon#end of sib2, iclass 18, count 0 2006.173.20:58:56.16#ibcon#*mode == 0, iclass 18, count 0 2006.173.20:58:56.16#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.20:58:56.16#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.20:58:56.16#ibcon#*before write, iclass 18, count 0 2006.173.20:58:56.16#ibcon#enter sib2, iclass 18, count 0 2006.173.20:58:56.16#ibcon#flushed, iclass 18, count 0 2006.173.20:58:56.16#ibcon#about to write, iclass 18, count 0 2006.173.20:58:56.16#ibcon#wrote, iclass 18, count 0 2006.173.20:58:56.16#ibcon#about to read 3, iclass 18, count 0 2006.173.20:58:56.20#ibcon#read 3, iclass 18, count 0 2006.173.20:58:56.20#ibcon#about to read 4, iclass 18, count 0 2006.173.20:58:56.20#ibcon#read 4, iclass 18, count 0 2006.173.20:58:56.20#ibcon#about to read 5, iclass 18, count 0 2006.173.20:58:56.20#ibcon#read 5, iclass 18, count 0 2006.173.20:58:56.20#ibcon#about to read 6, iclass 18, count 0 2006.173.20:58:56.20#ibcon#read 6, iclass 18, count 0 2006.173.20:58:56.20#ibcon#end of sib2, iclass 18, count 0 2006.173.20:58:56.20#ibcon#*after write, iclass 18, count 0 2006.173.20:58:56.20#ibcon#*before return 0, iclass 18, count 0 2006.173.20:58:56.20#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.20:58:56.20#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.20:58:56.20#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.20:58:56.20#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.20:58:56.20$vck44/vb=5,4 2006.173.20:58:56.20#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.20:58:56.20#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.20:58:56.20#ibcon#ireg 11 cls_cnt 2 2006.173.20:58:56.20#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.20:58:56.26#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.20:58:56.26#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.20:58:56.26#ibcon#enter wrdev, iclass 20, count 2 2006.173.20:58:56.26#ibcon#first serial, iclass 20, count 2 2006.173.20:58:56.26#ibcon#enter sib2, iclass 20, count 2 2006.173.20:58:56.26#ibcon#flushed, iclass 20, count 2 2006.173.20:58:56.26#ibcon#about to write, iclass 20, count 2 2006.173.20:58:56.26#ibcon#wrote, iclass 20, count 2 2006.173.20:58:56.26#ibcon#about to read 3, iclass 20, count 2 2006.173.20:58:56.28#ibcon#read 3, iclass 20, count 2 2006.173.20:58:56.28#ibcon#about to read 4, iclass 20, count 2 2006.173.20:58:56.28#ibcon#read 4, iclass 20, count 2 2006.173.20:58:56.28#ibcon#about to read 5, iclass 20, count 2 2006.173.20:58:56.28#ibcon#read 5, iclass 20, count 2 2006.173.20:58:56.28#ibcon#about to read 6, iclass 20, count 2 2006.173.20:58:56.28#ibcon#read 6, iclass 20, count 2 2006.173.20:58:56.28#ibcon#end of sib2, iclass 20, count 2 2006.173.20:58:56.28#ibcon#*mode == 0, iclass 20, count 2 2006.173.20:58:56.28#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.20:58:56.28#ibcon#[27=AT05-04\r\n] 2006.173.20:58:56.28#ibcon#*before write, iclass 20, count 2 2006.173.20:58:56.28#ibcon#enter sib2, iclass 20, count 2 2006.173.20:58:56.28#ibcon#flushed, iclass 20, count 2 2006.173.20:58:56.28#ibcon#about to write, iclass 20, count 2 2006.173.20:58:56.28#ibcon#wrote, iclass 20, count 2 2006.173.20:58:56.28#ibcon#about to read 3, iclass 20, count 2 2006.173.20:58:56.31#ibcon#read 3, iclass 20, count 2 2006.173.20:58:56.31#ibcon#about to read 4, iclass 20, count 2 2006.173.20:58:56.31#ibcon#read 4, iclass 20, count 2 2006.173.20:58:56.31#ibcon#about to read 5, iclass 20, count 2 2006.173.20:58:56.31#ibcon#read 5, iclass 20, count 2 2006.173.20:58:56.31#ibcon#about to read 6, iclass 20, count 2 2006.173.20:58:56.31#ibcon#read 6, iclass 20, count 2 2006.173.20:58:56.31#ibcon#end of sib2, iclass 20, count 2 2006.173.20:58:56.31#ibcon#*after write, iclass 20, count 2 2006.173.20:58:56.31#ibcon#*before return 0, iclass 20, count 2 2006.173.20:58:56.31#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.20:58:56.31#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.20:58:56.31#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.20:58:56.31#ibcon#ireg 7 cls_cnt 0 2006.173.20:58:56.31#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.20:58:56.43#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.20:58:56.43#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.20:58:56.43#ibcon#enter wrdev, iclass 20, count 0 2006.173.20:58:56.43#ibcon#first serial, iclass 20, count 0 2006.173.20:58:56.43#ibcon#enter sib2, iclass 20, count 0 2006.173.20:58:56.43#ibcon#flushed, iclass 20, count 0 2006.173.20:58:56.43#ibcon#about to write, iclass 20, count 0 2006.173.20:58:56.43#ibcon#wrote, iclass 20, count 0 2006.173.20:58:56.43#ibcon#about to read 3, iclass 20, count 0 2006.173.20:58:56.45#ibcon#read 3, iclass 20, count 0 2006.173.20:58:56.45#ibcon#about to read 4, iclass 20, count 0 2006.173.20:58:56.45#ibcon#read 4, iclass 20, count 0 2006.173.20:58:56.45#ibcon#about to read 5, iclass 20, count 0 2006.173.20:58:56.45#ibcon#read 5, iclass 20, count 0 2006.173.20:58:56.45#ibcon#about to read 6, iclass 20, count 0 2006.173.20:58:56.45#ibcon#read 6, iclass 20, count 0 2006.173.20:58:56.45#ibcon#end of sib2, iclass 20, count 0 2006.173.20:58:56.45#ibcon#*mode == 0, iclass 20, count 0 2006.173.20:58:56.45#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.20:58:56.45#ibcon#[27=USB\r\n] 2006.173.20:58:56.45#ibcon#*before write, iclass 20, count 0 2006.173.20:58:56.45#ibcon#enter sib2, iclass 20, count 0 2006.173.20:58:56.45#ibcon#flushed, iclass 20, count 0 2006.173.20:58:56.45#ibcon#about to write, iclass 20, count 0 2006.173.20:58:56.45#ibcon#wrote, iclass 20, count 0 2006.173.20:58:56.45#ibcon#about to read 3, iclass 20, count 0 2006.173.20:58:56.48#ibcon#read 3, iclass 20, count 0 2006.173.20:58:56.48#ibcon#about to read 4, iclass 20, count 0 2006.173.20:58:56.48#ibcon#read 4, iclass 20, count 0 2006.173.20:58:56.48#ibcon#about to read 5, iclass 20, count 0 2006.173.20:58:56.48#ibcon#read 5, iclass 20, count 0 2006.173.20:58:56.48#ibcon#about to read 6, iclass 20, count 0 2006.173.20:58:56.48#ibcon#read 6, iclass 20, count 0 2006.173.20:58:56.48#ibcon#end of sib2, iclass 20, count 0 2006.173.20:58:56.48#ibcon#*after write, iclass 20, count 0 2006.173.20:58:56.48#ibcon#*before return 0, iclass 20, count 0 2006.173.20:58:56.48#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.20:58:56.48#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.20:58:56.48#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.20:58:56.48#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.20:58:56.48$vck44/vblo=6,719.99 2006.173.20:58:56.48#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.20:58:56.48#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.20:58:56.48#ibcon#ireg 17 cls_cnt 0 2006.173.20:58:56.48#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.20:58:56.48#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.20:58:56.48#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.20:58:56.48#ibcon#enter wrdev, iclass 22, count 0 2006.173.20:58:56.48#ibcon#first serial, iclass 22, count 0 2006.173.20:58:56.48#ibcon#enter sib2, iclass 22, count 0 2006.173.20:58:56.48#ibcon#flushed, iclass 22, count 0 2006.173.20:58:56.48#ibcon#about to write, iclass 22, count 0 2006.173.20:58:56.48#ibcon#wrote, iclass 22, count 0 2006.173.20:58:56.48#ibcon#about to read 3, iclass 22, count 0 2006.173.20:58:56.50#ibcon#read 3, iclass 22, count 0 2006.173.20:58:56.50#ibcon#about to read 4, iclass 22, count 0 2006.173.20:58:56.50#ibcon#read 4, iclass 22, count 0 2006.173.20:58:56.50#ibcon#about to read 5, iclass 22, count 0 2006.173.20:58:56.50#ibcon#read 5, iclass 22, count 0 2006.173.20:58:56.50#ibcon#about to read 6, iclass 22, count 0 2006.173.20:58:56.50#ibcon#read 6, iclass 22, count 0 2006.173.20:58:56.50#ibcon#end of sib2, iclass 22, count 0 2006.173.20:58:56.50#ibcon#*mode == 0, iclass 22, count 0 2006.173.20:58:56.50#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.20:58:56.50#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.20:58:56.50#ibcon#*before write, iclass 22, count 0 2006.173.20:58:56.50#ibcon#enter sib2, iclass 22, count 0 2006.173.20:58:56.50#ibcon#flushed, iclass 22, count 0 2006.173.20:58:56.50#ibcon#about to write, iclass 22, count 0 2006.173.20:58:56.50#ibcon#wrote, iclass 22, count 0 2006.173.20:58:56.50#ibcon#about to read 3, iclass 22, count 0 2006.173.20:58:56.54#ibcon#read 3, iclass 22, count 0 2006.173.20:58:56.54#ibcon#about to read 4, iclass 22, count 0 2006.173.20:58:56.54#ibcon#read 4, iclass 22, count 0 2006.173.20:58:56.54#ibcon#about to read 5, iclass 22, count 0 2006.173.20:58:56.54#ibcon#read 5, iclass 22, count 0 2006.173.20:58:56.54#ibcon#about to read 6, iclass 22, count 0 2006.173.20:58:56.54#ibcon#read 6, iclass 22, count 0 2006.173.20:58:56.54#ibcon#end of sib2, iclass 22, count 0 2006.173.20:58:56.54#ibcon#*after write, iclass 22, count 0 2006.173.20:58:56.54#ibcon#*before return 0, iclass 22, count 0 2006.173.20:58:56.54#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.20:58:56.54#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.20:58:56.54#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.20:58:56.54#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.20:58:56.54$vck44/vb=6,4 2006.173.20:58:56.54#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.20:58:56.54#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.20:58:56.54#ibcon#ireg 11 cls_cnt 2 2006.173.20:58:56.54#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.20:58:56.60#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.20:58:56.60#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.20:58:56.60#ibcon#enter wrdev, iclass 24, count 2 2006.173.20:58:56.60#ibcon#first serial, iclass 24, count 2 2006.173.20:58:56.60#ibcon#enter sib2, iclass 24, count 2 2006.173.20:58:56.60#ibcon#flushed, iclass 24, count 2 2006.173.20:58:56.60#ibcon#about to write, iclass 24, count 2 2006.173.20:58:56.60#ibcon#wrote, iclass 24, count 2 2006.173.20:58:56.60#ibcon#about to read 3, iclass 24, count 2 2006.173.20:58:56.62#ibcon#read 3, iclass 24, count 2 2006.173.20:58:56.62#ibcon#about to read 4, iclass 24, count 2 2006.173.20:58:56.62#ibcon#read 4, iclass 24, count 2 2006.173.20:58:56.62#ibcon#about to read 5, iclass 24, count 2 2006.173.20:58:56.62#ibcon#read 5, iclass 24, count 2 2006.173.20:58:56.62#ibcon#about to read 6, iclass 24, count 2 2006.173.20:58:56.62#ibcon#read 6, iclass 24, count 2 2006.173.20:58:56.62#ibcon#end of sib2, iclass 24, count 2 2006.173.20:58:56.62#ibcon#*mode == 0, iclass 24, count 2 2006.173.20:58:56.62#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.20:58:56.62#ibcon#[27=AT06-04\r\n] 2006.173.20:58:56.62#ibcon#*before write, iclass 24, count 2 2006.173.20:58:56.62#ibcon#enter sib2, iclass 24, count 2 2006.173.20:58:56.62#ibcon#flushed, iclass 24, count 2 2006.173.20:58:56.62#ibcon#about to write, iclass 24, count 2 2006.173.20:58:56.62#ibcon#wrote, iclass 24, count 2 2006.173.20:58:56.62#ibcon#about to read 3, iclass 24, count 2 2006.173.20:58:56.65#ibcon#read 3, iclass 24, count 2 2006.173.20:58:56.65#ibcon#about to read 4, iclass 24, count 2 2006.173.20:58:56.65#ibcon#read 4, iclass 24, count 2 2006.173.20:58:56.65#ibcon#about to read 5, iclass 24, count 2 2006.173.20:58:56.65#ibcon#read 5, iclass 24, count 2 2006.173.20:58:56.65#ibcon#about to read 6, iclass 24, count 2 2006.173.20:58:56.65#ibcon#read 6, iclass 24, count 2 2006.173.20:58:56.65#ibcon#end of sib2, iclass 24, count 2 2006.173.20:58:56.65#ibcon#*after write, iclass 24, count 2 2006.173.20:58:56.65#ibcon#*before return 0, iclass 24, count 2 2006.173.20:58:56.65#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.20:58:56.65#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.20:58:56.65#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.20:58:56.65#ibcon#ireg 7 cls_cnt 0 2006.173.20:58:56.65#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.20:58:56.77#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.20:58:56.77#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.20:58:56.77#ibcon#enter wrdev, iclass 24, count 0 2006.173.20:58:56.77#ibcon#first serial, iclass 24, count 0 2006.173.20:58:56.77#ibcon#enter sib2, iclass 24, count 0 2006.173.20:58:56.77#ibcon#flushed, iclass 24, count 0 2006.173.20:58:56.77#ibcon#about to write, iclass 24, count 0 2006.173.20:58:56.77#ibcon#wrote, iclass 24, count 0 2006.173.20:58:56.77#ibcon#about to read 3, iclass 24, count 0 2006.173.20:58:56.79#ibcon#read 3, iclass 24, count 0 2006.173.20:58:56.79#ibcon#about to read 4, iclass 24, count 0 2006.173.20:58:56.79#ibcon#read 4, iclass 24, count 0 2006.173.20:58:56.79#ibcon#about to read 5, iclass 24, count 0 2006.173.20:58:56.79#ibcon#read 5, iclass 24, count 0 2006.173.20:58:56.79#ibcon#about to read 6, iclass 24, count 0 2006.173.20:58:56.79#ibcon#read 6, iclass 24, count 0 2006.173.20:58:56.79#ibcon#end of sib2, iclass 24, count 0 2006.173.20:58:56.79#ibcon#*mode == 0, iclass 24, count 0 2006.173.20:58:56.79#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.20:58:56.79#ibcon#[27=USB\r\n] 2006.173.20:58:56.79#ibcon#*before write, iclass 24, count 0 2006.173.20:58:56.79#ibcon#enter sib2, iclass 24, count 0 2006.173.20:58:56.79#ibcon#flushed, iclass 24, count 0 2006.173.20:58:56.79#ibcon#about to write, iclass 24, count 0 2006.173.20:58:56.79#ibcon#wrote, iclass 24, count 0 2006.173.20:58:56.79#ibcon#about to read 3, iclass 24, count 0 2006.173.20:58:56.82#ibcon#read 3, iclass 24, count 0 2006.173.20:58:56.82#ibcon#about to read 4, iclass 24, count 0 2006.173.20:58:56.82#ibcon#read 4, iclass 24, count 0 2006.173.20:58:56.82#ibcon#about to read 5, iclass 24, count 0 2006.173.20:58:56.82#ibcon#read 5, iclass 24, count 0 2006.173.20:58:56.82#ibcon#about to read 6, iclass 24, count 0 2006.173.20:58:56.82#ibcon#read 6, iclass 24, count 0 2006.173.20:58:56.82#ibcon#end of sib2, iclass 24, count 0 2006.173.20:58:56.82#ibcon#*after write, iclass 24, count 0 2006.173.20:58:56.82#ibcon#*before return 0, iclass 24, count 0 2006.173.20:58:56.82#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.20:58:56.82#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.20:58:56.82#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.20:58:56.82#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.20:58:56.82$vck44/vblo=7,734.99 2006.173.20:58:56.82#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.20:58:56.82#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.20:58:56.82#ibcon#ireg 17 cls_cnt 0 2006.173.20:58:56.82#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.20:58:56.82#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.20:58:56.82#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.20:58:56.82#ibcon#enter wrdev, iclass 26, count 0 2006.173.20:58:56.82#ibcon#first serial, iclass 26, count 0 2006.173.20:58:56.82#ibcon#enter sib2, iclass 26, count 0 2006.173.20:58:56.82#ibcon#flushed, iclass 26, count 0 2006.173.20:58:56.82#ibcon#about to write, iclass 26, count 0 2006.173.20:58:56.82#ibcon#wrote, iclass 26, count 0 2006.173.20:58:56.82#ibcon#about to read 3, iclass 26, count 0 2006.173.20:58:56.84#ibcon#read 3, iclass 26, count 0 2006.173.20:58:56.84#ibcon#about to read 4, iclass 26, count 0 2006.173.20:58:56.84#ibcon#read 4, iclass 26, count 0 2006.173.20:58:56.84#ibcon#about to read 5, iclass 26, count 0 2006.173.20:58:56.84#ibcon#read 5, iclass 26, count 0 2006.173.20:58:56.84#ibcon#about to read 6, iclass 26, count 0 2006.173.20:58:56.84#ibcon#read 6, iclass 26, count 0 2006.173.20:58:56.84#ibcon#end of sib2, iclass 26, count 0 2006.173.20:58:56.84#ibcon#*mode == 0, iclass 26, count 0 2006.173.20:58:56.84#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.20:58:56.84#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.20:58:56.84#ibcon#*before write, iclass 26, count 0 2006.173.20:58:56.84#ibcon#enter sib2, iclass 26, count 0 2006.173.20:58:56.84#ibcon#flushed, iclass 26, count 0 2006.173.20:58:56.84#ibcon#about to write, iclass 26, count 0 2006.173.20:58:56.84#ibcon#wrote, iclass 26, count 0 2006.173.20:58:56.84#ibcon#about to read 3, iclass 26, count 0 2006.173.20:58:56.88#ibcon#read 3, iclass 26, count 0 2006.173.20:58:56.88#ibcon#about to read 4, iclass 26, count 0 2006.173.20:58:56.88#ibcon#read 4, iclass 26, count 0 2006.173.20:58:56.88#ibcon#about to read 5, iclass 26, count 0 2006.173.20:58:56.88#ibcon#read 5, iclass 26, count 0 2006.173.20:58:56.88#ibcon#about to read 6, iclass 26, count 0 2006.173.20:58:56.88#ibcon#read 6, iclass 26, count 0 2006.173.20:58:56.88#ibcon#end of sib2, iclass 26, count 0 2006.173.20:58:56.88#ibcon#*after write, iclass 26, count 0 2006.173.20:58:56.88#ibcon#*before return 0, iclass 26, count 0 2006.173.20:58:56.88#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.20:58:56.88#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.20:58:56.88#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.20:58:56.88#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.20:58:56.88$vck44/vb=7,4 2006.173.20:58:56.88#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.20:58:56.88#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.20:58:56.88#ibcon#ireg 11 cls_cnt 2 2006.173.20:58:56.88#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.20:58:56.94#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.20:58:56.94#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.20:58:56.94#ibcon#enter wrdev, iclass 28, count 2 2006.173.20:58:56.94#ibcon#first serial, iclass 28, count 2 2006.173.20:58:56.94#ibcon#enter sib2, iclass 28, count 2 2006.173.20:58:56.94#ibcon#flushed, iclass 28, count 2 2006.173.20:58:56.94#ibcon#about to write, iclass 28, count 2 2006.173.20:58:56.94#ibcon#wrote, iclass 28, count 2 2006.173.20:58:56.94#ibcon#about to read 3, iclass 28, count 2 2006.173.20:58:56.96#ibcon#read 3, iclass 28, count 2 2006.173.20:58:56.96#ibcon#about to read 4, iclass 28, count 2 2006.173.20:58:56.96#ibcon#read 4, iclass 28, count 2 2006.173.20:58:56.96#ibcon#about to read 5, iclass 28, count 2 2006.173.20:58:56.96#ibcon#read 5, iclass 28, count 2 2006.173.20:58:56.96#ibcon#about to read 6, iclass 28, count 2 2006.173.20:58:56.96#ibcon#read 6, iclass 28, count 2 2006.173.20:58:56.96#ibcon#end of sib2, iclass 28, count 2 2006.173.20:58:56.96#ibcon#*mode == 0, iclass 28, count 2 2006.173.20:58:56.96#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.20:58:56.96#ibcon#[27=AT07-04\r\n] 2006.173.20:58:56.96#ibcon#*before write, iclass 28, count 2 2006.173.20:58:56.96#ibcon#enter sib2, iclass 28, count 2 2006.173.20:58:56.96#ibcon#flushed, iclass 28, count 2 2006.173.20:58:56.96#ibcon#about to write, iclass 28, count 2 2006.173.20:58:56.96#ibcon#wrote, iclass 28, count 2 2006.173.20:58:56.96#ibcon#about to read 3, iclass 28, count 2 2006.173.20:58:56.96#abcon#<5=/10 0.3 1.0 20.881001003.1\r\n> 2006.173.20:58:56.98#abcon#{5=INTERFACE CLEAR} 2006.173.20:58:56.99#ibcon#read 3, iclass 28, count 2 2006.173.20:58:56.99#ibcon#about to read 4, iclass 28, count 2 2006.173.20:58:56.99#ibcon#read 4, iclass 28, count 2 2006.173.20:58:56.99#ibcon#about to read 5, iclass 28, count 2 2006.173.20:58:56.99#ibcon#read 5, iclass 28, count 2 2006.173.20:58:56.99#ibcon#about to read 6, iclass 28, count 2 2006.173.20:58:56.99#ibcon#read 6, iclass 28, count 2 2006.173.20:58:56.99#ibcon#end of sib2, iclass 28, count 2 2006.173.20:58:56.99#ibcon#*after write, iclass 28, count 2 2006.173.20:58:56.99#ibcon#*before return 0, iclass 28, count 2 2006.173.20:58:56.99#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.20:58:56.99#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.20:58:56.99#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.20:58:56.99#ibcon#ireg 7 cls_cnt 0 2006.173.20:58:56.99#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.20:58:57.04#abcon#[5=S1D000X0/0*\r\n] 2006.173.20:58:57.11#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.20:58:57.11#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.20:58:57.11#ibcon#enter wrdev, iclass 28, count 0 2006.173.20:58:57.11#ibcon#first serial, iclass 28, count 0 2006.173.20:58:57.11#ibcon#enter sib2, iclass 28, count 0 2006.173.20:58:57.11#ibcon#flushed, iclass 28, count 0 2006.173.20:58:57.11#ibcon#about to write, iclass 28, count 0 2006.173.20:58:57.11#ibcon#wrote, iclass 28, count 0 2006.173.20:58:57.11#ibcon#about to read 3, iclass 28, count 0 2006.173.20:58:57.13#ibcon#read 3, iclass 28, count 0 2006.173.20:58:57.13#ibcon#about to read 4, iclass 28, count 0 2006.173.20:58:57.13#ibcon#read 4, iclass 28, count 0 2006.173.20:58:57.13#ibcon#about to read 5, iclass 28, count 0 2006.173.20:58:57.13#ibcon#read 5, iclass 28, count 0 2006.173.20:58:57.13#ibcon#about to read 6, iclass 28, count 0 2006.173.20:58:57.13#ibcon#read 6, iclass 28, count 0 2006.173.20:58:57.13#ibcon#end of sib2, iclass 28, count 0 2006.173.20:58:57.13#ibcon#*mode == 0, iclass 28, count 0 2006.173.20:58:57.13#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.20:58:57.13#ibcon#[27=USB\r\n] 2006.173.20:58:57.13#ibcon#*before write, iclass 28, count 0 2006.173.20:58:57.13#ibcon#enter sib2, iclass 28, count 0 2006.173.20:58:57.13#ibcon#flushed, iclass 28, count 0 2006.173.20:58:57.13#ibcon#about to write, iclass 28, count 0 2006.173.20:58:57.13#ibcon#wrote, iclass 28, count 0 2006.173.20:58:57.13#ibcon#about to read 3, iclass 28, count 0 2006.173.20:58:57.16#ibcon#read 3, iclass 28, count 0 2006.173.20:58:57.16#ibcon#about to read 4, iclass 28, count 0 2006.173.20:58:57.16#ibcon#read 4, iclass 28, count 0 2006.173.20:58:57.16#ibcon#about to read 5, iclass 28, count 0 2006.173.20:58:57.16#ibcon#read 5, iclass 28, count 0 2006.173.20:58:57.16#ibcon#about to read 6, iclass 28, count 0 2006.173.20:58:57.16#ibcon#read 6, iclass 28, count 0 2006.173.20:58:57.16#ibcon#end of sib2, iclass 28, count 0 2006.173.20:58:57.16#ibcon#*after write, iclass 28, count 0 2006.173.20:58:57.16#ibcon#*before return 0, iclass 28, count 0 2006.173.20:58:57.16#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.20:58:57.16#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.20:58:57.16#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.20:58:57.16#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.20:58:57.16$vck44/vblo=8,744.99 2006.173.20:58:57.16#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.20:58:57.16#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.20:58:57.16#ibcon#ireg 17 cls_cnt 0 2006.173.20:58:57.16#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.20:58:57.16#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.20:58:57.16#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.20:58:57.16#ibcon#enter wrdev, iclass 34, count 0 2006.173.20:58:57.16#ibcon#first serial, iclass 34, count 0 2006.173.20:58:57.16#ibcon#enter sib2, iclass 34, count 0 2006.173.20:58:57.16#ibcon#flushed, iclass 34, count 0 2006.173.20:58:57.16#ibcon#about to write, iclass 34, count 0 2006.173.20:58:57.16#ibcon#wrote, iclass 34, count 0 2006.173.20:58:57.16#ibcon#about to read 3, iclass 34, count 0 2006.173.20:58:57.18#ibcon#read 3, iclass 34, count 0 2006.173.20:58:57.18#ibcon#about to read 4, iclass 34, count 0 2006.173.20:58:57.18#ibcon#read 4, iclass 34, count 0 2006.173.20:58:57.18#ibcon#about to read 5, iclass 34, count 0 2006.173.20:58:57.18#ibcon#read 5, iclass 34, count 0 2006.173.20:58:57.18#ibcon#about to read 6, iclass 34, count 0 2006.173.20:58:57.18#ibcon#read 6, iclass 34, count 0 2006.173.20:58:57.18#ibcon#end of sib2, iclass 34, count 0 2006.173.20:58:57.18#ibcon#*mode == 0, iclass 34, count 0 2006.173.20:58:57.18#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.20:58:57.18#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.20:58:57.18#ibcon#*before write, iclass 34, count 0 2006.173.20:58:57.18#ibcon#enter sib2, iclass 34, count 0 2006.173.20:58:57.18#ibcon#flushed, iclass 34, count 0 2006.173.20:58:57.18#ibcon#about to write, iclass 34, count 0 2006.173.20:58:57.18#ibcon#wrote, iclass 34, count 0 2006.173.20:58:57.18#ibcon#about to read 3, iclass 34, count 0 2006.173.20:58:57.22#ibcon#read 3, iclass 34, count 0 2006.173.20:58:57.22#ibcon#about to read 4, iclass 34, count 0 2006.173.20:58:57.22#ibcon#read 4, iclass 34, count 0 2006.173.20:58:57.22#ibcon#about to read 5, iclass 34, count 0 2006.173.20:58:57.22#ibcon#read 5, iclass 34, count 0 2006.173.20:58:57.22#ibcon#about to read 6, iclass 34, count 0 2006.173.20:58:57.22#ibcon#read 6, iclass 34, count 0 2006.173.20:58:57.22#ibcon#end of sib2, iclass 34, count 0 2006.173.20:58:57.22#ibcon#*after write, iclass 34, count 0 2006.173.20:58:57.22#ibcon#*before return 0, iclass 34, count 0 2006.173.20:58:57.22#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.20:58:57.22#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.20:58:57.22#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.20:58:57.22#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.20:58:57.22$vck44/vb=8,4 2006.173.20:58:57.22#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.20:58:57.22#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.20:58:57.22#ibcon#ireg 11 cls_cnt 2 2006.173.20:58:57.22#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.20:58:57.28#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.20:58:57.28#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.20:58:57.28#ibcon#enter wrdev, iclass 36, count 2 2006.173.20:58:57.28#ibcon#first serial, iclass 36, count 2 2006.173.20:58:57.28#ibcon#enter sib2, iclass 36, count 2 2006.173.20:58:57.28#ibcon#flushed, iclass 36, count 2 2006.173.20:58:57.28#ibcon#about to write, iclass 36, count 2 2006.173.20:58:57.28#ibcon#wrote, iclass 36, count 2 2006.173.20:58:57.28#ibcon#about to read 3, iclass 36, count 2 2006.173.20:58:57.30#ibcon#read 3, iclass 36, count 2 2006.173.20:58:57.30#ibcon#about to read 4, iclass 36, count 2 2006.173.20:58:57.30#ibcon#read 4, iclass 36, count 2 2006.173.20:58:57.30#ibcon#about to read 5, iclass 36, count 2 2006.173.20:58:57.30#ibcon#read 5, iclass 36, count 2 2006.173.20:58:57.30#ibcon#about to read 6, iclass 36, count 2 2006.173.20:58:57.30#ibcon#read 6, iclass 36, count 2 2006.173.20:58:57.30#ibcon#end of sib2, iclass 36, count 2 2006.173.20:58:57.30#ibcon#*mode == 0, iclass 36, count 2 2006.173.20:58:57.30#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.20:58:57.30#ibcon#[27=AT08-04\r\n] 2006.173.20:58:57.30#ibcon#*before write, iclass 36, count 2 2006.173.20:58:57.30#ibcon#enter sib2, iclass 36, count 2 2006.173.20:58:57.30#ibcon#flushed, iclass 36, count 2 2006.173.20:58:57.30#ibcon#about to write, iclass 36, count 2 2006.173.20:58:57.30#ibcon#wrote, iclass 36, count 2 2006.173.20:58:57.30#ibcon#about to read 3, iclass 36, count 2 2006.173.20:58:57.33#ibcon#read 3, iclass 36, count 2 2006.173.20:58:57.33#ibcon#about to read 4, iclass 36, count 2 2006.173.20:58:57.33#ibcon#read 4, iclass 36, count 2 2006.173.20:58:57.33#ibcon#about to read 5, iclass 36, count 2 2006.173.20:58:57.33#ibcon#read 5, iclass 36, count 2 2006.173.20:58:57.33#ibcon#about to read 6, iclass 36, count 2 2006.173.20:58:57.33#ibcon#read 6, iclass 36, count 2 2006.173.20:58:57.33#ibcon#end of sib2, iclass 36, count 2 2006.173.20:58:57.33#ibcon#*after write, iclass 36, count 2 2006.173.20:58:57.33#ibcon#*before return 0, iclass 36, count 2 2006.173.20:58:57.33#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.20:58:57.33#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.20:58:57.33#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.20:58:57.33#ibcon#ireg 7 cls_cnt 0 2006.173.20:58:57.33#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.20:58:57.45#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.20:58:57.45#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.20:58:57.45#ibcon#enter wrdev, iclass 36, count 0 2006.173.20:58:57.45#ibcon#first serial, iclass 36, count 0 2006.173.20:58:57.45#ibcon#enter sib2, iclass 36, count 0 2006.173.20:58:57.45#ibcon#flushed, iclass 36, count 0 2006.173.20:58:57.45#ibcon#about to write, iclass 36, count 0 2006.173.20:58:57.45#ibcon#wrote, iclass 36, count 0 2006.173.20:58:57.45#ibcon#about to read 3, iclass 36, count 0 2006.173.20:58:57.47#ibcon#read 3, iclass 36, count 0 2006.173.20:58:57.47#ibcon#about to read 4, iclass 36, count 0 2006.173.20:58:57.47#ibcon#read 4, iclass 36, count 0 2006.173.20:58:57.47#ibcon#about to read 5, iclass 36, count 0 2006.173.20:58:57.47#ibcon#read 5, iclass 36, count 0 2006.173.20:58:57.47#ibcon#about to read 6, iclass 36, count 0 2006.173.20:58:57.47#ibcon#read 6, iclass 36, count 0 2006.173.20:58:57.47#ibcon#end of sib2, iclass 36, count 0 2006.173.20:58:57.47#ibcon#*mode == 0, iclass 36, count 0 2006.173.20:58:57.47#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.20:58:57.47#ibcon#[27=USB\r\n] 2006.173.20:58:57.47#ibcon#*before write, iclass 36, count 0 2006.173.20:58:57.47#ibcon#enter sib2, iclass 36, count 0 2006.173.20:58:57.47#ibcon#flushed, iclass 36, count 0 2006.173.20:58:57.47#ibcon#about to write, iclass 36, count 0 2006.173.20:58:57.47#ibcon#wrote, iclass 36, count 0 2006.173.20:58:57.47#ibcon#about to read 3, iclass 36, count 0 2006.173.20:58:57.50#ibcon#read 3, iclass 36, count 0 2006.173.20:58:57.50#ibcon#about to read 4, iclass 36, count 0 2006.173.20:58:57.50#ibcon#read 4, iclass 36, count 0 2006.173.20:58:57.50#ibcon#about to read 5, iclass 36, count 0 2006.173.20:58:57.50#ibcon#read 5, iclass 36, count 0 2006.173.20:58:57.50#ibcon#about to read 6, iclass 36, count 0 2006.173.20:58:57.50#ibcon#read 6, iclass 36, count 0 2006.173.20:58:57.50#ibcon#end of sib2, iclass 36, count 0 2006.173.20:58:57.50#ibcon#*after write, iclass 36, count 0 2006.173.20:58:57.50#ibcon#*before return 0, iclass 36, count 0 2006.173.20:58:57.50#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.20:58:57.50#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.20:58:57.50#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.20:58:57.50#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.20:58:57.50$vck44/vabw=wide 2006.173.20:58:57.50#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.20:58:57.50#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.20:58:57.50#ibcon#ireg 8 cls_cnt 0 2006.173.20:58:57.50#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.20:58:57.50#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.20:58:57.50#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.20:58:57.50#ibcon#enter wrdev, iclass 38, count 0 2006.173.20:58:57.50#ibcon#first serial, iclass 38, count 0 2006.173.20:58:57.50#ibcon#enter sib2, iclass 38, count 0 2006.173.20:58:57.50#ibcon#flushed, iclass 38, count 0 2006.173.20:58:57.50#ibcon#about to write, iclass 38, count 0 2006.173.20:58:57.50#ibcon#wrote, iclass 38, count 0 2006.173.20:58:57.50#ibcon#about to read 3, iclass 38, count 0 2006.173.20:58:57.52#ibcon#read 3, iclass 38, count 0 2006.173.20:58:57.52#ibcon#about to read 4, iclass 38, count 0 2006.173.20:58:57.52#ibcon#read 4, iclass 38, count 0 2006.173.20:58:57.52#ibcon#about to read 5, iclass 38, count 0 2006.173.20:58:57.52#ibcon#read 5, iclass 38, count 0 2006.173.20:58:57.52#ibcon#about to read 6, iclass 38, count 0 2006.173.20:58:57.52#ibcon#read 6, iclass 38, count 0 2006.173.20:58:57.52#ibcon#end of sib2, iclass 38, count 0 2006.173.20:58:57.52#ibcon#*mode == 0, iclass 38, count 0 2006.173.20:58:57.52#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.20:58:57.52#ibcon#[25=BW32\r\n] 2006.173.20:58:57.52#ibcon#*before write, iclass 38, count 0 2006.173.20:58:57.52#ibcon#enter sib2, iclass 38, count 0 2006.173.20:58:57.52#ibcon#flushed, iclass 38, count 0 2006.173.20:58:57.52#ibcon#about to write, iclass 38, count 0 2006.173.20:58:57.52#ibcon#wrote, iclass 38, count 0 2006.173.20:58:57.52#ibcon#about to read 3, iclass 38, count 0 2006.173.20:58:57.55#ibcon#read 3, iclass 38, count 0 2006.173.20:58:57.55#ibcon#about to read 4, iclass 38, count 0 2006.173.20:58:57.55#ibcon#read 4, iclass 38, count 0 2006.173.20:58:57.55#ibcon#about to read 5, iclass 38, count 0 2006.173.20:58:57.55#ibcon#read 5, iclass 38, count 0 2006.173.20:58:57.55#ibcon#about to read 6, iclass 38, count 0 2006.173.20:58:57.55#ibcon#read 6, iclass 38, count 0 2006.173.20:58:57.55#ibcon#end of sib2, iclass 38, count 0 2006.173.20:58:57.55#ibcon#*after write, iclass 38, count 0 2006.173.20:58:57.55#ibcon#*before return 0, iclass 38, count 0 2006.173.20:58:57.55#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.20:58:57.55#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.20:58:57.55#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.20:58:57.55#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.20:58:57.55$vck44/vbbw=wide 2006.173.20:58:57.55#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.20:58:57.55#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.20:58:57.55#ibcon#ireg 8 cls_cnt 0 2006.173.20:58:57.55#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.20:58:57.62#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.20:58:57.62#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.20:58:57.62#ibcon#enter wrdev, iclass 40, count 0 2006.173.20:58:57.62#ibcon#first serial, iclass 40, count 0 2006.173.20:58:57.62#ibcon#enter sib2, iclass 40, count 0 2006.173.20:58:57.62#ibcon#flushed, iclass 40, count 0 2006.173.20:58:57.62#ibcon#about to write, iclass 40, count 0 2006.173.20:58:57.62#ibcon#wrote, iclass 40, count 0 2006.173.20:58:57.62#ibcon#about to read 3, iclass 40, count 0 2006.173.20:58:57.64#ibcon#read 3, iclass 40, count 0 2006.173.20:58:57.64#ibcon#about to read 4, iclass 40, count 0 2006.173.20:58:57.64#ibcon#read 4, iclass 40, count 0 2006.173.20:58:57.64#ibcon#about to read 5, iclass 40, count 0 2006.173.20:58:57.64#ibcon#read 5, iclass 40, count 0 2006.173.20:58:57.64#ibcon#about to read 6, iclass 40, count 0 2006.173.20:58:57.64#ibcon#read 6, iclass 40, count 0 2006.173.20:58:57.64#ibcon#end of sib2, iclass 40, count 0 2006.173.20:58:57.64#ibcon#*mode == 0, iclass 40, count 0 2006.173.20:58:57.64#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.20:58:57.64#ibcon#[27=BW32\r\n] 2006.173.20:58:57.64#ibcon#*before write, iclass 40, count 0 2006.173.20:58:57.64#ibcon#enter sib2, iclass 40, count 0 2006.173.20:58:57.64#ibcon#flushed, iclass 40, count 0 2006.173.20:58:57.64#ibcon#about to write, iclass 40, count 0 2006.173.20:58:57.64#ibcon#wrote, iclass 40, count 0 2006.173.20:58:57.64#ibcon#about to read 3, iclass 40, count 0 2006.173.20:58:57.67#ibcon#read 3, iclass 40, count 0 2006.173.20:58:57.67#ibcon#about to read 4, iclass 40, count 0 2006.173.20:58:57.67#ibcon#read 4, iclass 40, count 0 2006.173.20:58:57.67#ibcon#about to read 5, iclass 40, count 0 2006.173.20:58:57.67#ibcon#read 5, iclass 40, count 0 2006.173.20:58:57.67#ibcon#about to read 6, iclass 40, count 0 2006.173.20:58:57.67#ibcon#read 6, iclass 40, count 0 2006.173.20:58:57.67#ibcon#end of sib2, iclass 40, count 0 2006.173.20:58:57.67#ibcon#*after write, iclass 40, count 0 2006.173.20:58:57.67#ibcon#*before return 0, iclass 40, count 0 2006.173.20:58:57.67#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.20:58:57.67#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.20:58:57.67#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.20:58:57.67#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.20:58:57.67$setupk4/ifdk4 2006.173.20:58:57.67$ifdk4/lo= 2006.173.20:58:57.67$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.20:58:57.67$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.20:58:57.67$ifdk4/patch= 2006.173.20:58:57.67$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.20:58:57.67$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.20:58:57.67$setupk4/!*+20s 2006.173.20:59:07.13#abcon#<5=/10 0.3 0.9 20.881001003.1\r\n> 2006.173.20:59:07.15#abcon#{5=INTERFACE CLEAR} 2006.173.20:59:07.21#abcon#[5=S1D000X0/0*\r\n] 2006.173.20:59:12.18$setupk4/"tpicd 2006.173.20:59:12.18$setupk4/echo=off 2006.173.20:59:12.18$setupk4/xlog=off 2006.173.20:59:12.18:!2006.173.21:07:55 2006.173.20:59:27.14#trakl#Source acquired 2006.173.20:59:27.14#flagr#flagr/antenna,acquired 2006.173.21:07:55.02:preob 2006.173.21:07:56.15/onsource/TRACKING 2006.173.21:07:56.15:!2006.173.21:08:05 2006.173.21:08:05.01:"tape 2006.173.21:08:05.02:"st=record 2006.173.21:08:05.02:data_valid=on 2006.173.21:08:05.02:midob 2006.173.21:08:06.15/onsource/TRACKING 2006.173.21:08:06.15/wx/21.01,1003.2,100 2006.173.21:08:06.35/cable/+6.5162E-03 2006.173.21:08:07.44/va/01,07,usb,yes,35,38 2006.173.21:08:07.44/va/02,06,usb,yes,35,36 2006.173.21:08:07.44/va/03,05,usb,yes,44,46 2006.173.21:08:07.44/va/04,06,usb,yes,36,37 2006.173.21:08:07.44/va/05,04,usb,yes,28,28 2006.173.21:08:07.44/va/06,03,usb,yes,39,39 2006.173.21:08:07.44/va/07,04,usb,yes,32,33 2006.173.21:08:07.44/va/08,04,usb,yes,27,32 2006.173.21:08:07.67/valo/01,524.99,yes,locked 2006.173.21:08:07.67/valo/02,534.99,yes,locked 2006.173.21:08:07.67/valo/03,564.99,yes,locked 2006.173.21:08:07.67/valo/04,624.99,yes,locked 2006.173.21:08:07.67/valo/05,734.99,yes,locked 2006.173.21:08:07.67/valo/06,814.99,yes,locked 2006.173.21:08:07.67/valo/07,864.99,yes,locked 2006.173.21:08:07.68/valo/08,884.99,yes,locked 2006.173.21:08:08.76/vb/01,04,usb,yes,29,27 2006.173.21:08:08.76/vb/02,04,usb,yes,32,32 2006.173.21:08:08.76/vb/03,04,usb,yes,29,32 2006.173.21:08:08.76/vb/04,04,usb,yes,33,32 2006.173.21:08:08.76/vb/05,04,usb,yes,25,28 2006.173.21:08:08.76/vb/06,04,usb,yes,30,26 2006.173.21:08:08.76/vb/07,04,usb,yes,30,29 2006.173.21:08:08.76/vb/08,04,usb,yes,27,31 2006.173.21:08:09.00/vblo/01,629.99,yes,locked 2006.173.21:08:09.00/vblo/02,634.99,yes,locked 2006.173.21:08:09.00/vblo/03,649.99,yes,locked 2006.173.21:08:09.00/vblo/04,679.99,yes,locked 2006.173.21:08:09.00/vblo/05,709.99,yes,locked 2006.173.21:08:09.00/vblo/06,719.99,yes,locked 2006.173.21:08:09.00/vblo/07,734.99,yes,locked 2006.173.21:08:09.01/vblo/08,744.99,yes,locked 2006.173.21:08:09.15/vabw/8 2006.173.21:08:09.30/vbbw/8 2006.173.21:08:09.39/xfe/off,on,14.2 2006.173.21:08:09.77/ifatt/23,28,28,28 2006.173.21:08:10.07/fmout-gps/S +3.84E-07 2006.173.21:08:10.12:!2006.173.21:11:05 2006.173.21:11:05.01:data_valid=off 2006.173.21:11:05.02:"et 2006.173.21:11:05.02:!+3s 2006.173.21:11:08.05:"tape 2006.173.21:11:08.06:postob 2006.173.21:11:08.20/cable/+6.5166E-03 2006.173.21:11:08.21/wx/21.04,1003.2,100 2006.173.21:11:08.26/fmout-gps/S +3.85E-07 2006.173.21:11:08.27:scan_name=173-2113,jd0606,40 2006.173.21:11:08.27:source=3c454.3,225357.75,160853.6,2000.0,cw 2006.173.21:11:09.13#flagr#flagr/antenna,new-source 2006.173.21:11:09.14:checkk5 2006.173.21:11:09.55/chk_autoobs//k5ts1/ autoobs is running! 2006.173.21:11:09.95/chk_autoobs//k5ts2/ autoobs is running! 2006.173.21:11:10.36/chk_autoobs//k5ts3/ autoobs is running! 2006.173.21:11:10.77/chk_autoobs//k5ts4/ autoobs is running! 2006.173.21:11:11.15/chk_obsdata//k5ts1/T1732108??a.dat file size is correct (nominal:720MB, actual:716MB). 2006.173.21:11:11.55/chk_obsdata//k5ts2/T1732108??b.dat file size is correct (nominal:720MB, actual:716MB). 2006.173.21:11:11.96/chk_obsdata//k5ts3/T1732108??c.dat file size is correct (nominal:720MB, actual:716MB). 2006.173.21:11:12.36/chk_obsdata//k5ts4/T1732108??d.dat file size is correct (nominal:720MB, actual:716MB). 2006.173.21:11:13.07/k5log//k5ts1_log_newline 2006.173.21:11:13.79/k5log//k5ts2_log_newline 2006.173.21:11:14.51/k5log//k5ts3_log_newline 2006.173.21:11:15.21/k5log//k5ts4_log_newline 2006.173.21:11:15.24/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.21:11:15.24:setupk4=1 2006.173.21:11:15.24$setupk4/echo=on 2006.173.21:11:15.24$setupk4/pcalon 2006.173.21:11:15.24$pcalon/"no phase cal control is implemented here 2006.173.21:11:15.24$setupk4/"tpicd=stop 2006.173.21:11:15.24$setupk4/"rec=synch_on 2006.173.21:11:15.24$setupk4/"rec_mode=128 2006.173.21:11:15.24$setupk4/!* 2006.173.21:11:15.24$setupk4/recpk4 2006.173.21:11:15.24$recpk4/recpatch= 2006.173.21:11:15.24$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.21:11:15.24$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.21:11:15.24$setupk4/vck44 2006.173.21:11:15.24$vck44/valo=1,524.99 2006.173.21:11:15.24#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.21:11:15.24#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.21:11:15.24#ibcon#ireg 17 cls_cnt 0 2006.173.21:11:15.24#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.21:11:15.24#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.21:11:15.24#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.21:11:15.24#ibcon#enter wrdev, iclass 7, count 0 2006.173.21:11:15.24#ibcon#first serial, iclass 7, count 0 2006.173.21:11:15.24#ibcon#enter sib2, iclass 7, count 0 2006.173.21:11:15.24#ibcon#flushed, iclass 7, count 0 2006.173.21:11:15.24#ibcon#about to write, iclass 7, count 0 2006.173.21:11:15.24#ibcon#wrote, iclass 7, count 0 2006.173.21:11:15.24#ibcon#about to read 3, iclass 7, count 0 2006.173.21:11:15.25#ibcon#read 3, iclass 7, count 0 2006.173.21:11:15.25#ibcon#about to read 4, iclass 7, count 0 2006.173.21:11:15.25#ibcon#read 4, iclass 7, count 0 2006.173.21:11:15.25#ibcon#about to read 5, iclass 7, count 0 2006.173.21:11:15.25#ibcon#read 5, iclass 7, count 0 2006.173.21:11:15.25#ibcon#about to read 6, iclass 7, count 0 2006.173.21:11:15.25#ibcon#read 6, iclass 7, count 0 2006.173.21:11:15.25#ibcon#end of sib2, iclass 7, count 0 2006.173.21:11:15.25#ibcon#*mode == 0, iclass 7, count 0 2006.173.21:11:15.25#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.21:11:15.25#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.21:11:15.25#ibcon#*before write, iclass 7, count 0 2006.173.21:11:15.25#ibcon#enter sib2, iclass 7, count 0 2006.173.21:11:15.25#ibcon#flushed, iclass 7, count 0 2006.173.21:11:15.25#ibcon#about to write, iclass 7, count 0 2006.173.21:11:15.25#ibcon#wrote, iclass 7, count 0 2006.173.21:11:15.25#ibcon#about to read 3, iclass 7, count 0 2006.173.21:11:15.30#ibcon#read 3, iclass 7, count 0 2006.173.21:11:15.30#ibcon#about to read 4, iclass 7, count 0 2006.173.21:11:15.30#ibcon#read 4, iclass 7, count 0 2006.173.21:11:15.30#ibcon#about to read 5, iclass 7, count 0 2006.173.21:11:15.30#ibcon#read 5, iclass 7, count 0 2006.173.21:11:15.30#ibcon#about to read 6, iclass 7, count 0 2006.173.21:11:15.30#ibcon#read 6, iclass 7, count 0 2006.173.21:11:15.30#ibcon#end of sib2, iclass 7, count 0 2006.173.21:11:15.30#ibcon#*after write, iclass 7, count 0 2006.173.21:11:15.30#ibcon#*before return 0, iclass 7, count 0 2006.173.21:11:15.30#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.21:11:15.30#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.21:11:15.30#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.21:11:15.30#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.21:11:15.30$vck44/va=1,7 2006.173.21:11:15.30#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.21:11:15.30#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.21:11:15.30#ibcon#ireg 11 cls_cnt 2 2006.173.21:11:15.30#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.21:11:15.30#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.21:11:15.30#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.21:11:15.30#ibcon#enter wrdev, iclass 11, count 2 2006.173.21:11:15.30#ibcon#first serial, iclass 11, count 2 2006.173.21:11:15.30#ibcon#enter sib2, iclass 11, count 2 2006.173.21:11:15.30#ibcon#flushed, iclass 11, count 2 2006.173.21:11:15.30#ibcon#about to write, iclass 11, count 2 2006.173.21:11:15.30#ibcon#wrote, iclass 11, count 2 2006.173.21:11:15.30#ibcon#about to read 3, iclass 11, count 2 2006.173.21:11:15.32#ibcon#read 3, iclass 11, count 2 2006.173.21:11:15.32#ibcon#about to read 4, iclass 11, count 2 2006.173.21:11:15.32#ibcon#read 4, iclass 11, count 2 2006.173.21:11:15.32#ibcon#about to read 5, iclass 11, count 2 2006.173.21:11:15.32#ibcon#read 5, iclass 11, count 2 2006.173.21:11:15.32#ibcon#about to read 6, iclass 11, count 2 2006.173.21:11:15.32#ibcon#read 6, iclass 11, count 2 2006.173.21:11:15.32#ibcon#end of sib2, iclass 11, count 2 2006.173.21:11:15.32#ibcon#*mode == 0, iclass 11, count 2 2006.173.21:11:15.32#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.21:11:15.32#ibcon#[25=AT01-07\r\n] 2006.173.21:11:15.32#ibcon#*before write, iclass 11, count 2 2006.173.21:11:15.32#ibcon#enter sib2, iclass 11, count 2 2006.173.21:11:15.32#ibcon#flushed, iclass 11, count 2 2006.173.21:11:15.32#ibcon#about to write, iclass 11, count 2 2006.173.21:11:15.32#ibcon#wrote, iclass 11, count 2 2006.173.21:11:15.32#ibcon#about to read 3, iclass 11, count 2 2006.173.21:11:15.35#ibcon#read 3, iclass 11, count 2 2006.173.21:11:15.35#ibcon#about to read 4, iclass 11, count 2 2006.173.21:11:15.35#ibcon#read 4, iclass 11, count 2 2006.173.21:11:15.35#ibcon#about to read 5, iclass 11, count 2 2006.173.21:11:15.35#ibcon#read 5, iclass 11, count 2 2006.173.21:11:15.35#ibcon#about to read 6, iclass 11, count 2 2006.173.21:11:15.35#ibcon#read 6, iclass 11, count 2 2006.173.21:11:15.35#ibcon#end of sib2, iclass 11, count 2 2006.173.21:11:15.35#ibcon#*after write, iclass 11, count 2 2006.173.21:11:15.35#ibcon#*before return 0, iclass 11, count 2 2006.173.21:11:15.35#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.21:11:15.35#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.21:11:15.35#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.21:11:15.35#ibcon#ireg 7 cls_cnt 0 2006.173.21:11:15.35#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.21:11:15.47#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.21:11:15.47#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.21:11:15.47#ibcon#enter wrdev, iclass 11, count 0 2006.173.21:11:15.47#ibcon#first serial, iclass 11, count 0 2006.173.21:11:15.47#ibcon#enter sib2, iclass 11, count 0 2006.173.21:11:15.47#ibcon#flushed, iclass 11, count 0 2006.173.21:11:15.47#ibcon#about to write, iclass 11, count 0 2006.173.21:11:15.47#ibcon#wrote, iclass 11, count 0 2006.173.21:11:15.47#ibcon#about to read 3, iclass 11, count 0 2006.173.21:11:15.49#ibcon#read 3, iclass 11, count 0 2006.173.21:11:15.49#ibcon#about to read 4, iclass 11, count 0 2006.173.21:11:15.49#ibcon#read 4, iclass 11, count 0 2006.173.21:11:15.49#ibcon#about to read 5, iclass 11, count 0 2006.173.21:11:15.49#ibcon#read 5, iclass 11, count 0 2006.173.21:11:15.49#ibcon#about to read 6, iclass 11, count 0 2006.173.21:11:15.49#ibcon#read 6, iclass 11, count 0 2006.173.21:11:15.49#ibcon#end of sib2, iclass 11, count 0 2006.173.21:11:15.49#ibcon#*mode == 0, iclass 11, count 0 2006.173.21:11:15.49#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.21:11:15.49#ibcon#[25=USB\r\n] 2006.173.21:11:15.49#ibcon#*before write, iclass 11, count 0 2006.173.21:11:15.49#ibcon#enter sib2, iclass 11, count 0 2006.173.21:11:15.49#ibcon#flushed, iclass 11, count 0 2006.173.21:11:15.49#ibcon#about to write, iclass 11, count 0 2006.173.21:11:15.49#ibcon#wrote, iclass 11, count 0 2006.173.21:11:15.49#ibcon#about to read 3, iclass 11, count 0 2006.173.21:11:15.52#ibcon#read 3, iclass 11, count 0 2006.173.21:11:15.52#ibcon#about to read 4, iclass 11, count 0 2006.173.21:11:15.52#ibcon#read 4, iclass 11, count 0 2006.173.21:11:15.52#ibcon#about to read 5, iclass 11, count 0 2006.173.21:11:15.52#ibcon#read 5, iclass 11, count 0 2006.173.21:11:15.52#ibcon#about to read 6, iclass 11, count 0 2006.173.21:11:15.52#ibcon#read 6, iclass 11, count 0 2006.173.21:11:15.52#ibcon#end of sib2, iclass 11, count 0 2006.173.21:11:15.52#ibcon#*after write, iclass 11, count 0 2006.173.21:11:15.52#ibcon#*before return 0, iclass 11, count 0 2006.173.21:11:15.52#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.21:11:15.52#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.21:11:15.52#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.21:11:15.52#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.21:11:15.52$vck44/valo=2,534.99 2006.173.21:11:15.52#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.21:11:15.52#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.21:11:15.52#ibcon#ireg 17 cls_cnt 0 2006.173.21:11:15.52#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.21:11:15.52#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.21:11:15.52#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.21:11:15.52#ibcon#enter wrdev, iclass 13, count 0 2006.173.21:11:15.52#ibcon#first serial, iclass 13, count 0 2006.173.21:11:15.52#ibcon#enter sib2, iclass 13, count 0 2006.173.21:11:15.52#ibcon#flushed, iclass 13, count 0 2006.173.21:11:15.52#ibcon#about to write, iclass 13, count 0 2006.173.21:11:15.52#ibcon#wrote, iclass 13, count 0 2006.173.21:11:15.52#ibcon#about to read 3, iclass 13, count 0 2006.173.21:11:15.54#ibcon#read 3, iclass 13, count 0 2006.173.21:11:15.54#ibcon#about to read 4, iclass 13, count 0 2006.173.21:11:15.54#ibcon#read 4, iclass 13, count 0 2006.173.21:11:15.54#ibcon#about to read 5, iclass 13, count 0 2006.173.21:11:15.54#ibcon#read 5, iclass 13, count 0 2006.173.21:11:15.54#ibcon#about to read 6, iclass 13, count 0 2006.173.21:11:15.54#ibcon#read 6, iclass 13, count 0 2006.173.21:11:15.54#ibcon#end of sib2, iclass 13, count 0 2006.173.21:11:15.54#ibcon#*mode == 0, iclass 13, count 0 2006.173.21:11:15.54#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.21:11:15.54#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.21:11:15.54#ibcon#*before write, iclass 13, count 0 2006.173.21:11:15.54#ibcon#enter sib2, iclass 13, count 0 2006.173.21:11:15.54#ibcon#flushed, iclass 13, count 0 2006.173.21:11:15.54#ibcon#about to write, iclass 13, count 0 2006.173.21:11:15.54#ibcon#wrote, iclass 13, count 0 2006.173.21:11:15.54#ibcon#about to read 3, iclass 13, count 0 2006.173.21:11:15.58#ibcon#read 3, iclass 13, count 0 2006.173.21:11:15.58#ibcon#about to read 4, iclass 13, count 0 2006.173.21:11:15.58#ibcon#read 4, iclass 13, count 0 2006.173.21:11:15.58#ibcon#about to read 5, iclass 13, count 0 2006.173.21:11:15.58#ibcon#read 5, iclass 13, count 0 2006.173.21:11:15.58#ibcon#about to read 6, iclass 13, count 0 2006.173.21:11:15.58#ibcon#read 6, iclass 13, count 0 2006.173.21:11:15.58#ibcon#end of sib2, iclass 13, count 0 2006.173.21:11:15.58#ibcon#*after write, iclass 13, count 0 2006.173.21:11:15.58#ibcon#*before return 0, iclass 13, count 0 2006.173.21:11:15.58#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.21:11:15.58#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.21:11:15.58#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.21:11:15.58#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.21:11:15.58$vck44/va=2,6 2006.173.21:11:15.58#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.21:11:15.58#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.21:11:15.58#ibcon#ireg 11 cls_cnt 2 2006.173.21:11:15.58#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.21:11:15.64#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.21:11:15.64#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.21:11:15.64#ibcon#enter wrdev, iclass 15, count 2 2006.173.21:11:15.64#ibcon#first serial, iclass 15, count 2 2006.173.21:11:15.64#ibcon#enter sib2, iclass 15, count 2 2006.173.21:11:15.64#ibcon#flushed, iclass 15, count 2 2006.173.21:11:15.64#ibcon#about to write, iclass 15, count 2 2006.173.21:11:15.64#ibcon#wrote, iclass 15, count 2 2006.173.21:11:15.64#ibcon#about to read 3, iclass 15, count 2 2006.173.21:11:15.66#ibcon#read 3, iclass 15, count 2 2006.173.21:11:15.66#ibcon#about to read 4, iclass 15, count 2 2006.173.21:11:15.66#ibcon#read 4, iclass 15, count 2 2006.173.21:11:15.66#ibcon#about to read 5, iclass 15, count 2 2006.173.21:11:15.66#ibcon#read 5, iclass 15, count 2 2006.173.21:11:15.66#ibcon#about to read 6, iclass 15, count 2 2006.173.21:11:15.66#ibcon#read 6, iclass 15, count 2 2006.173.21:11:15.66#ibcon#end of sib2, iclass 15, count 2 2006.173.21:11:15.66#ibcon#*mode == 0, iclass 15, count 2 2006.173.21:11:15.66#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.21:11:15.66#ibcon#[25=AT02-06\r\n] 2006.173.21:11:15.66#ibcon#*before write, iclass 15, count 2 2006.173.21:11:15.66#ibcon#enter sib2, iclass 15, count 2 2006.173.21:11:15.66#ibcon#flushed, iclass 15, count 2 2006.173.21:11:15.66#ibcon#about to write, iclass 15, count 2 2006.173.21:11:15.66#ibcon#wrote, iclass 15, count 2 2006.173.21:11:15.66#ibcon#about to read 3, iclass 15, count 2 2006.173.21:11:15.69#ibcon#read 3, iclass 15, count 2 2006.173.21:11:15.69#ibcon#about to read 4, iclass 15, count 2 2006.173.21:11:15.69#ibcon#read 4, iclass 15, count 2 2006.173.21:11:15.69#ibcon#about to read 5, iclass 15, count 2 2006.173.21:11:15.69#ibcon#read 5, iclass 15, count 2 2006.173.21:11:15.69#ibcon#about to read 6, iclass 15, count 2 2006.173.21:11:15.69#ibcon#read 6, iclass 15, count 2 2006.173.21:11:15.69#ibcon#end of sib2, iclass 15, count 2 2006.173.21:11:15.69#ibcon#*after write, iclass 15, count 2 2006.173.21:11:15.69#ibcon#*before return 0, iclass 15, count 2 2006.173.21:11:15.69#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.21:11:15.69#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.21:11:15.69#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.21:11:15.69#ibcon#ireg 7 cls_cnt 0 2006.173.21:11:15.69#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.21:11:15.81#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.21:11:15.81#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.21:11:15.81#ibcon#enter wrdev, iclass 15, count 0 2006.173.21:11:15.81#ibcon#first serial, iclass 15, count 0 2006.173.21:11:15.81#ibcon#enter sib2, iclass 15, count 0 2006.173.21:11:15.81#ibcon#flushed, iclass 15, count 0 2006.173.21:11:15.81#ibcon#about to write, iclass 15, count 0 2006.173.21:11:15.81#ibcon#wrote, iclass 15, count 0 2006.173.21:11:15.81#ibcon#about to read 3, iclass 15, count 0 2006.173.21:11:15.83#ibcon#read 3, iclass 15, count 0 2006.173.21:11:15.83#ibcon#about to read 4, iclass 15, count 0 2006.173.21:11:15.83#ibcon#read 4, iclass 15, count 0 2006.173.21:11:15.83#ibcon#about to read 5, iclass 15, count 0 2006.173.21:11:15.83#ibcon#read 5, iclass 15, count 0 2006.173.21:11:15.83#ibcon#about to read 6, iclass 15, count 0 2006.173.21:11:15.83#ibcon#read 6, iclass 15, count 0 2006.173.21:11:15.83#ibcon#end of sib2, iclass 15, count 0 2006.173.21:11:15.83#ibcon#*mode == 0, iclass 15, count 0 2006.173.21:11:15.83#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.21:11:15.83#ibcon#[25=USB\r\n] 2006.173.21:11:15.83#ibcon#*before write, iclass 15, count 0 2006.173.21:11:15.83#ibcon#enter sib2, iclass 15, count 0 2006.173.21:11:15.83#ibcon#flushed, iclass 15, count 0 2006.173.21:11:15.83#ibcon#about to write, iclass 15, count 0 2006.173.21:11:15.83#ibcon#wrote, iclass 15, count 0 2006.173.21:11:15.83#ibcon#about to read 3, iclass 15, count 0 2006.173.21:11:15.86#ibcon#read 3, iclass 15, count 0 2006.173.21:11:15.86#ibcon#about to read 4, iclass 15, count 0 2006.173.21:11:15.86#ibcon#read 4, iclass 15, count 0 2006.173.21:11:15.86#ibcon#about to read 5, iclass 15, count 0 2006.173.21:11:15.86#ibcon#read 5, iclass 15, count 0 2006.173.21:11:15.86#ibcon#about to read 6, iclass 15, count 0 2006.173.21:11:15.86#ibcon#read 6, iclass 15, count 0 2006.173.21:11:15.86#ibcon#end of sib2, iclass 15, count 0 2006.173.21:11:15.86#ibcon#*after write, iclass 15, count 0 2006.173.21:11:15.86#ibcon#*before return 0, iclass 15, count 0 2006.173.21:11:15.86#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.21:11:15.86#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.21:11:15.86#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.21:11:15.86#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.21:11:15.86$vck44/valo=3,564.99 2006.173.21:11:15.86#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.21:11:15.86#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.21:11:15.86#ibcon#ireg 17 cls_cnt 0 2006.173.21:11:15.86#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.21:11:15.86#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.21:11:15.86#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.21:11:15.86#ibcon#enter wrdev, iclass 17, count 0 2006.173.21:11:15.86#ibcon#first serial, iclass 17, count 0 2006.173.21:11:15.86#ibcon#enter sib2, iclass 17, count 0 2006.173.21:11:15.86#ibcon#flushed, iclass 17, count 0 2006.173.21:11:15.86#ibcon#about to write, iclass 17, count 0 2006.173.21:11:15.86#ibcon#wrote, iclass 17, count 0 2006.173.21:11:15.86#ibcon#about to read 3, iclass 17, count 0 2006.173.21:11:15.88#ibcon#read 3, iclass 17, count 0 2006.173.21:11:15.88#ibcon#about to read 4, iclass 17, count 0 2006.173.21:11:15.88#ibcon#read 4, iclass 17, count 0 2006.173.21:11:15.88#ibcon#about to read 5, iclass 17, count 0 2006.173.21:11:15.88#ibcon#read 5, iclass 17, count 0 2006.173.21:11:15.88#ibcon#about to read 6, iclass 17, count 0 2006.173.21:11:15.88#ibcon#read 6, iclass 17, count 0 2006.173.21:11:15.88#ibcon#end of sib2, iclass 17, count 0 2006.173.21:11:15.88#ibcon#*mode == 0, iclass 17, count 0 2006.173.21:11:15.88#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.21:11:15.88#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.21:11:15.88#ibcon#*before write, iclass 17, count 0 2006.173.21:11:15.88#ibcon#enter sib2, iclass 17, count 0 2006.173.21:11:15.88#ibcon#flushed, iclass 17, count 0 2006.173.21:11:15.88#ibcon#about to write, iclass 17, count 0 2006.173.21:11:15.88#ibcon#wrote, iclass 17, count 0 2006.173.21:11:15.88#ibcon#about to read 3, iclass 17, count 0 2006.173.21:11:15.92#ibcon#read 3, iclass 17, count 0 2006.173.21:11:15.92#ibcon#about to read 4, iclass 17, count 0 2006.173.21:11:15.92#ibcon#read 4, iclass 17, count 0 2006.173.21:11:15.92#ibcon#about to read 5, iclass 17, count 0 2006.173.21:11:15.92#ibcon#read 5, iclass 17, count 0 2006.173.21:11:15.92#ibcon#about to read 6, iclass 17, count 0 2006.173.21:11:15.92#ibcon#read 6, iclass 17, count 0 2006.173.21:11:15.92#ibcon#end of sib2, iclass 17, count 0 2006.173.21:11:15.92#ibcon#*after write, iclass 17, count 0 2006.173.21:11:15.92#ibcon#*before return 0, iclass 17, count 0 2006.173.21:11:15.92#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.21:11:15.92#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.21:11:15.92#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.21:11:15.92#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.21:11:15.92$vck44/va=3,5 2006.173.21:11:15.92#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.21:11:15.92#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.21:11:15.92#ibcon#ireg 11 cls_cnt 2 2006.173.21:11:15.92#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.21:11:15.98#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.21:11:15.98#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.21:11:15.98#ibcon#enter wrdev, iclass 19, count 2 2006.173.21:11:15.98#ibcon#first serial, iclass 19, count 2 2006.173.21:11:15.98#ibcon#enter sib2, iclass 19, count 2 2006.173.21:11:15.98#ibcon#flushed, iclass 19, count 2 2006.173.21:11:15.98#ibcon#about to write, iclass 19, count 2 2006.173.21:11:15.98#ibcon#wrote, iclass 19, count 2 2006.173.21:11:15.98#ibcon#about to read 3, iclass 19, count 2 2006.173.21:11:16.00#ibcon#read 3, iclass 19, count 2 2006.173.21:11:16.00#ibcon#about to read 4, iclass 19, count 2 2006.173.21:11:16.00#ibcon#read 4, iclass 19, count 2 2006.173.21:11:16.00#ibcon#about to read 5, iclass 19, count 2 2006.173.21:11:16.00#ibcon#read 5, iclass 19, count 2 2006.173.21:11:16.00#ibcon#about to read 6, iclass 19, count 2 2006.173.21:11:16.00#ibcon#read 6, iclass 19, count 2 2006.173.21:11:16.00#ibcon#end of sib2, iclass 19, count 2 2006.173.21:11:16.00#ibcon#*mode == 0, iclass 19, count 2 2006.173.21:11:16.00#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.21:11:16.00#ibcon#[25=AT03-05\r\n] 2006.173.21:11:16.00#ibcon#*before write, iclass 19, count 2 2006.173.21:11:16.00#ibcon#enter sib2, iclass 19, count 2 2006.173.21:11:16.00#ibcon#flushed, iclass 19, count 2 2006.173.21:11:16.00#ibcon#about to write, iclass 19, count 2 2006.173.21:11:16.00#ibcon#wrote, iclass 19, count 2 2006.173.21:11:16.00#ibcon#about to read 3, iclass 19, count 2 2006.173.21:11:16.03#ibcon#read 3, iclass 19, count 2 2006.173.21:11:16.03#ibcon#about to read 4, iclass 19, count 2 2006.173.21:11:16.03#ibcon#read 4, iclass 19, count 2 2006.173.21:11:16.03#ibcon#about to read 5, iclass 19, count 2 2006.173.21:11:16.03#ibcon#read 5, iclass 19, count 2 2006.173.21:11:16.03#ibcon#about to read 6, iclass 19, count 2 2006.173.21:11:16.03#ibcon#read 6, iclass 19, count 2 2006.173.21:11:16.03#ibcon#end of sib2, iclass 19, count 2 2006.173.21:11:16.03#ibcon#*after write, iclass 19, count 2 2006.173.21:11:16.03#ibcon#*before return 0, iclass 19, count 2 2006.173.21:11:16.03#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.21:11:16.03#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.21:11:16.03#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.21:11:16.03#ibcon#ireg 7 cls_cnt 0 2006.173.21:11:16.03#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.21:11:16.15#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.21:11:16.15#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.21:11:16.15#ibcon#enter wrdev, iclass 19, count 0 2006.173.21:11:16.15#ibcon#first serial, iclass 19, count 0 2006.173.21:11:16.15#ibcon#enter sib2, iclass 19, count 0 2006.173.21:11:16.15#ibcon#flushed, iclass 19, count 0 2006.173.21:11:16.15#ibcon#about to write, iclass 19, count 0 2006.173.21:11:16.15#ibcon#wrote, iclass 19, count 0 2006.173.21:11:16.15#ibcon#about to read 3, iclass 19, count 0 2006.173.21:11:16.17#ibcon#read 3, iclass 19, count 0 2006.173.21:11:16.17#ibcon#about to read 4, iclass 19, count 0 2006.173.21:11:16.17#ibcon#read 4, iclass 19, count 0 2006.173.21:11:16.17#ibcon#about to read 5, iclass 19, count 0 2006.173.21:11:16.17#ibcon#read 5, iclass 19, count 0 2006.173.21:11:16.17#ibcon#about to read 6, iclass 19, count 0 2006.173.21:11:16.17#ibcon#read 6, iclass 19, count 0 2006.173.21:11:16.17#ibcon#end of sib2, iclass 19, count 0 2006.173.21:11:16.17#ibcon#*mode == 0, iclass 19, count 0 2006.173.21:11:16.17#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.21:11:16.17#ibcon#[25=USB\r\n] 2006.173.21:11:16.17#ibcon#*before write, iclass 19, count 0 2006.173.21:11:16.17#ibcon#enter sib2, iclass 19, count 0 2006.173.21:11:16.17#ibcon#flushed, iclass 19, count 0 2006.173.21:11:16.17#ibcon#about to write, iclass 19, count 0 2006.173.21:11:16.17#ibcon#wrote, iclass 19, count 0 2006.173.21:11:16.17#ibcon#about to read 3, iclass 19, count 0 2006.173.21:11:16.20#ibcon#read 3, iclass 19, count 0 2006.173.21:11:16.20#ibcon#about to read 4, iclass 19, count 0 2006.173.21:11:16.20#ibcon#read 4, iclass 19, count 0 2006.173.21:11:16.20#ibcon#about to read 5, iclass 19, count 0 2006.173.21:11:16.20#ibcon#read 5, iclass 19, count 0 2006.173.21:11:16.20#ibcon#about to read 6, iclass 19, count 0 2006.173.21:11:16.20#ibcon#read 6, iclass 19, count 0 2006.173.21:11:16.20#ibcon#end of sib2, iclass 19, count 0 2006.173.21:11:16.20#ibcon#*after write, iclass 19, count 0 2006.173.21:11:16.20#ibcon#*before return 0, iclass 19, count 0 2006.173.21:11:16.20#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.21:11:16.20#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.21:11:16.20#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.21:11:16.20#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.21:11:16.20$vck44/valo=4,624.99 2006.173.21:11:16.20#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.21:11:16.20#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.21:11:16.20#ibcon#ireg 17 cls_cnt 0 2006.173.21:11:16.20#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.21:11:16.20#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.21:11:16.20#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.21:11:16.20#ibcon#enter wrdev, iclass 21, count 0 2006.173.21:11:16.20#ibcon#first serial, iclass 21, count 0 2006.173.21:11:16.20#ibcon#enter sib2, iclass 21, count 0 2006.173.21:11:16.20#ibcon#flushed, iclass 21, count 0 2006.173.21:11:16.20#ibcon#about to write, iclass 21, count 0 2006.173.21:11:16.20#ibcon#wrote, iclass 21, count 0 2006.173.21:11:16.20#ibcon#about to read 3, iclass 21, count 0 2006.173.21:11:16.22#ibcon#read 3, iclass 21, count 0 2006.173.21:11:16.22#ibcon#about to read 4, iclass 21, count 0 2006.173.21:11:16.22#ibcon#read 4, iclass 21, count 0 2006.173.21:11:16.22#ibcon#about to read 5, iclass 21, count 0 2006.173.21:11:16.22#ibcon#read 5, iclass 21, count 0 2006.173.21:11:16.22#ibcon#about to read 6, iclass 21, count 0 2006.173.21:11:16.22#ibcon#read 6, iclass 21, count 0 2006.173.21:11:16.22#ibcon#end of sib2, iclass 21, count 0 2006.173.21:11:16.22#ibcon#*mode == 0, iclass 21, count 0 2006.173.21:11:16.22#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.21:11:16.22#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.21:11:16.22#ibcon#*before write, iclass 21, count 0 2006.173.21:11:16.22#ibcon#enter sib2, iclass 21, count 0 2006.173.21:11:16.22#ibcon#flushed, iclass 21, count 0 2006.173.21:11:16.22#ibcon#about to write, iclass 21, count 0 2006.173.21:11:16.22#ibcon#wrote, iclass 21, count 0 2006.173.21:11:16.22#ibcon#about to read 3, iclass 21, count 0 2006.173.21:11:16.26#ibcon#read 3, iclass 21, count 0 2006.173.21:11:16.26#ibcon#about to read 4, iclass 21, count 0 2006.173.21:11:16.26#ibcon#read 4, iclass 21, count 0 2006.173.21:11:16.26#ibcon#about to read 5, iclass 21, count 0 2006.173.21:11:16.26#ibcon#read 5, iclass 21, count 0 2006.173.21:11:16.26#ibcon#about to read 6, iclass 21, count 0 2006.173.21:11:16.26#ibcon#read 6, iclass 21, count 0 2006.173.21:11:16.26#ibcon#end of sib2, iclass 21, count 0 2006.173.21:11:16.26#ibcon#*after write, iclass 21, count 0 2006.173.21:11:16.26#ibcon#*before return 0, iclass 21, count 0 2006.173.21:11:16.26#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.21:11:16.26#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.21:11:16.26#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.21:11:16.26#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.21:11:16.26$vck44/va=4,6 2006.173.21:11:16.26#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.21:11:16.26#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.21:11:16.26#ibcon#ireg 11 cls_cnt 2 2006.173.21:11:16.26#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.21:11:16.32#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.21:11:16.32#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.21:11:16.32#ibcon#enter wrdev, iclass 23, count 2 2006.173.21:11:16.32#ibcon#first serial, iclass 23, count 2 2006.173.21:11:16.32#ibcon#enter sib2, iclass 23, count 2 2006.173.21:11:16.32#ibcon#flushed, iclass 23, count 2 2006.173.21:11:16.32#ibcon#about to write, iclass 23, count 2 2006.173.21:11:16.32#ibcon#wrote, iclass 23, count 2 2006.173.21:11:16.32#ibcon#about to read 3, iclass 23, count 2 2006.173.21:11:16.34#ibcon#read 3, iclass 23, count 2 2006.173.21:11:16.34#ibcon#about to read 4, iclass 23, count 2 2006.173.21:11:16.34#ibcon#read 4, iclass 23, count 2 2006.173.21:11:16.34#ibcon#about to read 5, iclass 23, count 2 2006.173.21:11:16.34#ibcon#read 5, iclass 23, count 2 2006.173.21:11:16.34#ibcon#about to read 6, iclass 23, count 2 2006.173.21:11:16.34#ibcon#read 6, iclass 23, count 2 2006.173.21:11:16.34#ibcon#end of sib2, iclass 23, count 2 2006.173.21:11:16.34#ibcon#*mode == 0, iclass 23, count 2 2006.173.21:11:16.34#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.21:11:16.34#ibcon#[25=AT04-06\r\n] 2006.173.21:11:16.34#ibcon#*before write, iclass 23, count 2 2006.173.21:11:16.34#ibcon#enter sib2, iclass 23, count 2 2006.173.21:11:16.34#ibcon#flushed, iclass 23, count 2 2006.173.21:11:16.34#ibcon#about to write, iclass 23, count 2 2006.173.21:11:16.34#ibcon#wrote, iclass 23, count 2 2006.173.21:11:16.34#ibcon#about to read 3, iclass 23, count 2 2006.173.21:11:16.37#ibcon#read 3, iclass 23, count 2 2006.173.21:11:16.37#ibcon#about to read 4, iclass 23, count 2 2006.173.21:11:16.37#ibcon#read 4, iclass 23, count 2 2006.173.21:11:16.37#ibcon#about to read 5, iclass 23, count 2 2006.173.21:11:16.37#ibcon#read 5, iclass 23, count 2 2006.173.21:11:16.37#ibcon#about to read 6, iclass 23, count 2 2006.173.21:11:16.37#ibcon#read 6, iclass 23, count 2 2006.173.21:11:16.37#ibcon#end of sib2, iclass 23, count 2 2006.173.21:11:16.37#ibcon#*after write, iclass 23, count 2 2006.173.21:11:16.37#ibcon#*before return 0, iclass 23, count 2 2006.173.21:11:16.37#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.21:11:16.37#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.21:11:16.37#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.21:11:16.37#ibcon#ireg 7 cls_cnt 0 2006.173.21:11:16.37#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.21:11:16.49#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.21:11:16.49#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.21:11:16.49#ibcon#enter wrdev, iclass 23, count 0 2006.173.21:11:16.49#ibcon#first serial, iclass 23, count 0 2006.173.21:11:16.49#ibcon#enter sib2, iclass 23, count 0 2006.173.21:11:16.49#ibcon#flushed, iclass 23, count 0 2006.173.21:11:16.49#ibcon#about to write, iclass 23, count 0 2006.173.21:11:16.49#ibcon#wrote, iclass 23, count 0 2006.173.21:11:16.49#ibcon#about to read 3, iclass 23, count 0 2006.173.21:11:16.51#ibcon#read 3, iclass 23, count 0 2006.173.21:11:16.51#ibcon#about to read 4, iclass 23, count 0 2006.173.21:11:16.51#ibcon#read 4, iclass 23, count 0 2006.173.21:11:16.51#ibcon#about to read 5, iclass 23, count 0 2006.173.21:11:16.51#ibcon#read 5, iclass 23, count 0 2006.173.21:11:16.51#ibcon#about to read 6, iclass 23, count 0 2006.173.21:11:16.51#ibcon#read 6, iclass 23, count 0 2006.173.21:11:16.51#ibcon#end of sib2, iclass 23, count 0 2006.173.21:11:16.51#ibcon#*mode == 0, iclass 23, count 0 2006.173.21:11:16.51#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.21:11:16.51#ibcon#[25=USB\r\n] 2006.173.21:11:16.51#ibcon#*before write, iclass 23, count 0 2006.173.21:11:16.51#ibcon#enter sib2, iclass 23, count 0 2006.173.21:11:16.51#ibcon#flushed, iclass 23, count 0 2006.173.21:11:16.51#ibcon#about to write, iclass 23, count 0 2006.173.21:11:16.51#ibcon#wrote, iclass 23, count 0 2006.173.21:11:16.51#ibcon#about to read 3, iclass 23, count 0 2006.173.21:11:16.54#ibcon#read 3, iclass 23, count 0 2006.173.21:11:16.54#ibcon#about to read 4, iclass 23, count 0 2006.173.21:11:16.54#ibcon#read 4, iclass 23, count 0 2006.173.21:11:16.54#ibcon#about to read 5, iclass 23, count 0 2006.173.21:11:16.54#ibcon#read 5, iclass 23, count 0 2006.173.21:11:16.54#ibcon#about to read 6, iclass 23, count 0 2006.173.21:11:16.54#ibcon#read 6, iclass 23, count 0 2006.173.21:11:16.54#ibcon#end of sib2, iclass 23, count 0 2006.173.21:11:16.54#ibcon#*after write, iclass 23, count 0 2006.173.21:11:16.54#ibcon#*before return 0, iclass 23, count 0 2006.173.21:11:16.54#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.21:11:16.54#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.21:11:16.54#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.21:11:16.54#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.21:11:16.54$vck44/valo=5,734.99 2006.173.21:11:16.54#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.21:11:16.54#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.21:11:16.54#ibcon#ireg 17 cls_cnt 0 2006.173.21:11:16.54#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.21:11:16.54#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.21:11:16.54#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.21:11:16.54#ibcon#enter wrdev, iclass 25, count 0 2006.173.21:11:16.54#ibcon#first serial, iclass 25, count 0 2006.173.21:11:16.54#ibcon#enter sib2, iclass 25, count 0 2006.173.21:11:16.54#ibcon#flushed, iclass 25, count 0 2006.173.21:11:16.54#ibcon#about to write, iclass 25, count 0 2006.173.21:11:16.54#ibcon#wrote, iclass 25, count 0 2006.173.21:11:16.54#ibcon#about to read 3, iclass 25, count 0 2006.173.21:11:16.56#ibcon#read 3, iclass 25, count 0 2006.173.21:11:16.56#ibcon#about to read 4, iclass 25, count 0 2006.173.21:11:16.56#ibcon#read 4, iclass 25, count 0 2006.173.21:11:16.56#ibcon#about to read 5, iclass 25, count 0 2006.173.21:11:16.56#ibcon#read 5, iclass 25, count 0 2006.173.21:11:16.56#ibcon#about to read 6, iclass 25, count 0 2006.173.21:11:16.56#ibcon#read 6, iclass 25, count 0 2006.173.21:11:16.56#ibcon#end of sib2, iclass 25, count 0 2006.173.21:11:16.56#ibcon#*mode == 0, iclass 25, count 0 2006.173.21:11:16.56#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.21:11:16.56#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.21:11:16.56#ibcon#*before write, iclass 25, count 0 2006.173.21:11:16.56#ibcon#enter sib2, iclass 25, count 0 2006.173.21:11:16.56#ibcon#flushed, iclass 25, count 0 2006.173.21:11:16.56#ibcon#about to write, iclass 25, count 0 2006.173.21:11:16.56#ibcon#wrote, iclass 25, count 0 2006.173.21:11:16.56#ibcon#about to read 3, iclass 25, count 0 2006.173.21:11:16.60#ibcon#read 3, iclass 25, count 0 2006.173.21:11:16.60#ibcon#about to read 4, iclass 25, count 0 2006.173.21:11:16.60#ibcon#read 4, iclass 25, count 0 2006.173.21:11:16.60#ibcon#about to read 5, iclass 25, count 0 2006.173.21:11:16.60#ibcon#read 5, iclass 25, count 0 2006.173.21:11:16.60#ibcon#about to read 6, iclass 25, count 0 2006.173.21:11:16.60#ibcon#read 6, iclass 25, count 0 2006.173.21:11:16.60#ibcon#end of sib2, iclass 25, count 0 2006.173.21:11:16.60#ibcon#*after write, iclass 25, count 0 2006.173.21:11:16.60#ibcon#*before return 0, iclass 25, count 0 2006.173.21:11:16.60#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.21:11:16.60#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.21:11:16.60#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.21:11:16.60#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.21:11:16.60$vck44/va=5,4 2006.173.21:11:16.60#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.21:11:16.60#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.21:11:16.60#ibcon#ireg 11 cls_cnt 2 2006.173.21:11:16.60#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.21:11:16.66#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.21:11:16.66#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.21:11:16.66#ibcon#enter wrdev, iclass 27, count 2 2006.173.21:11:16.66#ibcon#first serial, iclass 27, count 2 2006.173.21:11:16.66#ibcon#enter sib2, iclass 27, count 2 2006.173.21:11:16.66#ibcon#flushed, iclass 27, count 2 2006.173.21:11:16.66#ibcon#about to write, iclass 27, count 2 2006.173.21:11:16.66#ibcon#wrote, iclass 27, count 2 2006.173.21:11:16.66#ibcon#about to read 3, iclass 27, count 2 2006.173.21:11:16.68#ibcon#read 3, iclass 27, count 2 2006.173.21:11:16.68#ibcon#about to read 4, iclass 27, count 2 2006.173.21:11:16.68#ibcon#read 4, iclass 27, count 2 2006.173.21:11:16.68#ibcon#about to read 5, iclass 27, count 2 2006.173.21:11:16.68#ibcon#read 5, iclass 27, count 2 2006.173.21:11:16.68#ibcon#about to read 6, iclass 27, count 2 2006.173.21:11:16.68#ibcon#read 6, iclass 27, count 2 2006.173.21:11:16.68#ibcon#end of sib2, iclass 27, count 2 2006.173.21:11:16.68#ibcon#*mode == 0, iclass 27, count 2 2006.173.21:11:16.68#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.21:11:16.68#ibcon#[25=AT05-04\r\n] 2006.173.21:11:16.68#ibcon#*before write, iclass 27, count 2 2006.173.21:11:16.68#ibcon#enter sib2, iclass 27, count 2 2006.173.21:11:16.68#ibcon#flushed, iclass 27, count 2 2006.173.21:11:16.68#ibcon#about to write, iclass 27, count 2 2006.173.21:11:16.68#ibcon#wrote, iclass 27, count 2 2006.173.21:11:16.68#ibcon#about to read 3, iclass 27, count 2 2006.173.21:11:16.71#ibcon#read 3, iclass 27, count 2 2006.173.21:11:16.71#ibcon#about to read 4, iclass 27, count 2 2006.173.21:11:16.71#ibcon#read 4, iclass 27, count 2 2006.173.21:11:16.71#ibcon#about to read 5, iclass 27, count 2 2006.173.21:11:16.71#ibcon#read 5, iclass 27, count 2 2006.173.21:11:16.71#ibcon#about to read 6, iclass 27, count 2 2006.173.21:11:16.71#ibcon#read 6, iclass 27, count 2 2006.173.21:11:16.71#ibcon#end of sib2, iclass 27, count 2 2006.173.21:11:16.71#ibcon#*after write, iclass 27, count 2 2006.173.21:11:16.71#ibcon#*before return 0, iclass 27, count 2 2006.173.21:11:16.71#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.21:11:16.71#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.21:11:16.71#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.21:11:16.71#ibcon#ireg 7 cls_cnt 0 2006.173.21:11:16.71#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.21:11:16.83#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.21:11:16.83#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.21:11:16.83#ibcon#enter wrdev, iclass 27, count 0 2006.173.21:11:16.83#ibcon#first serial, iclass 27, count 0 2006.173.21:11:16.83#ibcon#enter sib2, iclass 27, count 0 2006.173.21:11:16.83#ibcon#flushed, iclass 27, count 0 2006.173.21:11:16.83#ibcon#about to write, iclass 27, count 0 2006.173.21:11:16.83#ibcon#wrote, iclass 27, count 0 2006.173.21:11:16.83#ibcon#about to read 3, iclass 27, count 0 2006.173.21:11:16.85#ibcon#read 3, iclass 27, count 0 2006.173.21:11:16.85#ibcon#about to read 4, iclass 27, count 0 2006.173.21:11:16.85#ibcon#read 4, iclass 27, count 0 2006.173.21:11:16.85#ibcon#about to read 5, iclass 27, count 0 2006.173.21:11:16.85#ibcon#read 5, iclass 27, count 0 2006.173.21:11:16.85#ibcon#about to read 6, iclass 27, count 0 2006.173.21:11:16.85#ibcon#read 6, iclass 27, count 0 2006.173.21:11:16.85#ibcon#end of sib2, iclass 27, count 0 2006.173.21:11:16.85#ibcon#*mode == 0, iclass 27, count 0 2006.173.21:11:16.85#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.21:11:16.85#ibcon#[25=USB\r\n] 2006.173.21:11:16.85#ibcon#*before write, iclass 27, count 0 2006.173.21:11:16.85#ibcon#enter sib2, iclass 27, count 0 2006.173.21:11:16.85#ibcon#flushed, iclass 27, count 0 2006.173.21:11:16.85#ibcon#about to write, iclass 27, count 0 2006.173.21:11:16.85#ibcon#wrote, iclass 27, count 0 2006.173.21:11:16.85#ibcon#about to read 3, iclass 27, count 0 2006.173.21:11:16.88#ibcon#read 3, iclass 27, count 0 2006.173.21:11:16.88#ibcon#about to read 4, iclass 27, count 0 2006.173.21:11:16.88#ibcon#read 4, iclass 27, count 0 2006.173.21:11:16.88#ibcon#about to read 5, iclass 27, count 0 2006.173.21:11:16.88#ibcon#read 5, iclass 27, count 0 2006.173.21:11:16.88#ibcon#about to read 6, iclass 27, count 0 2006.173.21:11:16.88#ibcon#read 6, iclass 27, count 0 2006.173.21:11:16.88#ibcon#end of sib2, iclass 27, count 0 2006.173.21:11:16.88#ibcon#*after write, iclass 27, count 0 2006.173.21:11:16.88#ibcon#*before return 0, iclass 27, count 0 2006.173.21:11:16.88#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.21:11:16.88#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.21:11:16.88#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.21:11:16.88#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.21:11:16.88$vck44/valo=6,814.99 2006.173.21:11:16.88#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.21:11:16.88#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.21:11:16.88#ibcon#ireg 17 cls_cnt 0 2006.173.21:11:16.88#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.21:11:16.88#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.21:11:16.88#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.21:11:16.88#ibcon#enter wrdev, iclass 29, count 0 2006.173.21:11:16.88#ibcon#first serial, iclass 29, count 0 2006.173.21:11:16.88#ibcon#enter sib2, iclass 29, count 0 2006.173.21:11:16.88#ibcon#flushed, iclass 29, count 0 2006.173.21:11:16.88#ibcon#about to write, iclass 29, count 0 2006.173.21:11:16.88#ibcon#wrote, iclass 29, count 0 2006.173.21:11:16.88#ibcon#about to read 3, iclass 29, count 0 2006.173.21:11:16.90#ibcon#read 3, iclass 29, count 0 2006.173.21:11:16.90#ibcon#about to read 4, iclass 29, count 0 2006.173.21:11:16.90#ibcon#read 4, iclass 29, count 0 2006.173.21:11:16.90#ibcon#about to read 5, iclass 29, count 0 2006.173.21:11:16.90#ibcon#read 5, iclass 29, count 0 2006.173.21:11:16.90#ibcon#about to read 6, iclass 29, count 0 2006.173.21:11:16.90#ibcon#read 6, iclass 29, count 0 2006.173.21:11:16.90#ibcon#end of sib2, iclass 29, count 0 2006.173.21:11:16.90#ibcon#*mode == 0, iclass 29, count 0 2006.173.21:11:16.90#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.21:11:16.90#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.21:11:16.90#ibcon#*before write, iclass 29, count 0 2006.173.21:11:16.90#ibcon#enter sib2, iclass 29, count 0 2006.173.21:11:16.90#ibcon#flushed, iclass 29, count 0 2006.173.21:11:16.90#ibcon#about to write, iclass 29, count 0 2006.173.21:11:16.90#ibcon#wrote, iclass 29, count 0 2006.173.21:11:16.90#ibcon#about to read 3, iclass 29, count 0 2006.173.21:11:16.94#ibcon#read 3, iclass 29, count 0 2006.173.21:11:16.94#ibcon#about to read 4, iclass 29, count 0 2006.173.21:11:16.94#ibcon#read 4, iclass 29, count 0 2006.173.21:11:16.94#ibcon#about to read 5, iclass 29, count 0 2006.173.21:11:16.94#ibcon#read 5, iclass 29, count 0 2006.173.21:11:16.94#ibcon#about to read 6, iclass 29, count 0 2006.173.21:11:16.94#ibcon#read 6, iclass 29, count 0 2006.173.21:11:16.94#ibcon#end of sib2, iclass 29, count 0 2006.173.21:11:16.94#ibcon#*after write, iclass 29, count 0 2006.173.21:11:16.94#ibcon#*before return 0, iclass 29, count 0 2006.173.21:11:16.94#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.21:11:16.94#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.21:11:16.94#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.21:11:16.94#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.21:11:16.94$vck44/va=6,3 2006.173.21:11:16.94#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.21:11:16.94#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.21:11:16.94#ibcon#ireg 11 cls_cnt 2 2006.173.21:11:16.94#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.21:11:17.00#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.21:11:17.00#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.21:11:17.00#ibcon#enter wrdev, iclass 31, count 2 2006.173.21:11:17.00#ibcon#first serial, iclass 31, count 2 2006.173.21:11:17.00#ibcon#enter sib2, iclass 31, count 2 2006.173.21:11:17.00#ibcon#flushed, iclass 31, count 2 2006.173.21:11:17.00#ibcon#about to write, iclass 31, count 2 2006.173.21:11:17.00#ibcon#wrote, iclass 31, count 2 2006.173.21:11:17.00#ibcon#about to read 3, iclass 31, count 2 2006.173.21:11:17.02#ibcon#read 3, iclass 31, count 2 2006.173.21:11:17.02#ibcon#about to read 4, iclass 31, count 2 2006.173.21:11:17.02#ibcon#read 4, iclass 31, count 2 2006.173.21:11:17.02#ibcon#about to read 5, iclass 31, count 2 2006.173.21:11:17.02#ibcon#read 5, iclass 31, count 2 2006.173.21:11:17.02#ibcon#about to read 6, iclass 31, count 2 2006.173.21:11:17.02#ibcon#read 6, iclass 31, count 2 2006.173.21:11:17.02#ibcon#end of sib2, iclass 31, count 2 2006.173.21:11:17.02#ibcon#*mode == 0, iclass 31, count 2 2006.173.21:11:17.02#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.21:11:17.02#ibcon#[25=AT06-03\r\n] 2006.173.21:11:17.02#ibcon#*before write, iclass 31, count 2 2006.173.21:11:17.02#ibcon#enter sib2, iclass 31, count 2 2006.173.21:11:17.02#ibcon#flushed, iclass 31, count 2 2006.173.21:11:17.02#ibcon#about to write, iclass 31, count 2 2006.173.21:11:17.02#ibcon#wrote, iclass 31, count 2 2006.173.21:11:17.02#ibcon#about to read 3, iclass 31, count 2 2006.173.21:11:17.05#ibcon#read 3, iclass 31, count 2 2006.173.21:11:17.05#ibcon#about to read 4, iclass 31, count 2 2006.173.21:11:17.05#ibcon#read 4, iclass 31, count 2 2006.173.21:11:17.05#ibcon#about to read 5, iclass 31, count 2 2006.173.21:11:17.05#ibcon#read 5, iclass 31, count 2 2006.173.21:11:17.05#ibcon#about to read 6, iclass 31, count 2 2006.173.21:11:17.05#ibcon#read 6, iclass 31, count 2 2006.173.21:11:17.05#ibcon#end of sib2, iclass 31, count 2 2006.173.21:11:17.05#ibcon#*after write, iclass 31, count 2 2006.173.21:11:17.05#ibcon#*before return 0, iclass 31, count 2 2006.173.21:11:17.05#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.21:11:17.05#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.21:11:17.05#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.21:11:17.05#ibcon#ireg 7 cls_cnt 0 2006.173.21:11:17.05#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.21:11:17.17#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.21:11:17.17#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.21:11:17.17#ibcon#enter wrdev, iclass 31, count 0 2006.173.21:11:17.17#ibcon#first serial, iclass 31, count 0 2006.173.21:11:17.17#ibcon#enter sib2, iclass 31, count 0 2006.173.21:11:17.17#ibcon#flushed, iclass 31, count 0 2006.173.21:11:17.17#ibcon#about to write, iclass 31, count 0 2006.173.21:11:17.17#ibcon#wrote, iclass 31, count 0 2006.173.21:11:17.17#ibcon#about to read 3, iclass 31, count 0 2006.173.21:11:17.19#ibcon#read 3, iclass 31, count 0 2006.173.21:11:17.19#ibcon#about to read 4, iclass 31, count 0 2006.173.21:11:17.19#ibcon#read 4, iclass 31, count 0 2006.173.21:11:17.19#ibcon#about to read 5, iclass 31, count 0 2006.173.21:11:17.19#ibcon#read 5, iclass 31, count 0 2006.173.21:11:17.19#ibcon#about to read 6, iclass 31, count 0 2006.173.21:11:17.19#ibcon#read 6, iclass 31, count 0 2006.173.21:11:17.19#ibcon#end of sib2, iclass 31, count 0 2006.173.21:11:17.19#ibcon#*mode == 0, iclass 31, count 0 2006.173.21:11:17.19#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.21:11:17.19#ibcon#[25=USB\r\n] 2006.173.21:11:17.19#ibcon#*before write, iclass 31, count 0 2006.173.21:11:17.19#ibcon#enter sib2, iclass 31, count 0 2006.173.21:11:17.19#ibcon#flushed, iclass 31, count 0 2006.173.21:11:17.19#ibcon#about to write, iclass 31, count 0 2006.173.21:11:17.19#ibcon#wrote, iclass 31, count 0 2006.173.21:11:17.19#ibcon#about to read 3, iclass 31, count 0 2006.173.21:11:17.22#ibcon#read 3, iclass 31, count 0 2006.173.21:11:17.22#ibcon#about to read 4, iclass 31, count 0 2006.173.21:11:17.22#ibcon#read 4, iclass 31, count 0 2006.173.21:11:17.22#ibcon#about to read 5, iclass 31, count 0 2006.173.21:11:17.22#ibcon#read 5, iclass 31, count 0 2006.173.21:11:17.22#ibcon#about to read 6, iclass 31, count 0 2006.173.21:11:17.22#ibcon#read 6, iclass 31, count 0 2006.173.21:11:17.22#ibcon#end of sib2, iclass 31, count 0 2006.173.21:11:17.22#ibcon#*after write, iclass 31, count 0 2006.173.21:11:17.22#ibcon#*before return 0, iclass 31, count 0 2006.173.21:11:17.22#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.21:11:17.22#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.21:11:17.22#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.21:11:17.22#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.21:11:17.22$vck44/valo=7,864.99 2006.173.21:11:17.22#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.21:11:17.22#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.21:11:17.22#ibcon#ireg 17 cls_cnt 0 2006.173.21:11:17.22#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.21:11:17.22#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.21:11:17.22#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.21:11:17.22#ibcon#enter wrdev, iclass 33, count 0 2006.173.21:11:17.22#ibcon#first serial, iclass 33, count 0 2006.173.21:11:17.22#ibcon#enter sib2, iclass 33, count 0 2006.173.21:11:17.22#ibcon#flushed, iclass 33, count 0 2006.173.21:11:17.22#ibcon#about to write, iclass 33, count 0 2006.173.21:11:17.22#ibcon#wrote, iclass 33, count 0 2006.173.21:11:17.22#ibcon#about to read 3, iclass 33, count 0 2006.173.21:11:17.24#ibcon#read 3, iclass 33, count 0 2006.173.21:11:17.24#ibcon#about to read 4, iclass 33, count 0 2006.173.21:11:17.24#ibcon#read 4, iclass 33, count 0 2006.173.21:11:17.24#ibcon#about to read 5, iclass 33, count 0 2006.173.21:11:17.24#ibcon#read 5, iclass 33, count 0 2006.173.21:11:17.24#ibcon#about to read 6, iclass 33, count 0 2006.173.21:11:17.24#ibcon#read 6, iclass 33, count 0 2006.173.21:11:17.24#ibcon#end of sib2, iclass 33, count 0 2006.173.21:11:17.24#ibcon#*mode == 0, iclass 33, count 0 2006.173.21:11:17.24#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.21:11:17.24#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.21:11:17.24#ibcon#*before write, iclass 33, count 0 2006.173.21:11:17.24#ibcon#enter sib2, iclass 33, count 0 2006.173.21:11:17.24#ibcon#flushed, iclass 33, count 0 2006.173.21:11:17.24#ibcon#about to write, iclass 33, count 0 2006.173.21:11:17.24#ibcon#wrote, iclass 33, count 0 2006.173.21:11:17.24#ibcon#about to read 3, iclass 33, count 0 2006.173.21:11:17.28#ibcon#read 3, iclass 33, count 0 2006.173.21:11:17.28#ibcon#about to read 4, iclass 33, count 0 2006.173.21:11:17.28#ibcon#read 4, iclass 33, count 0 2006.173.21:11:17.28#ibcon#about to read 5, iclass 33, count 0 2006.173.21:11:17.28#ibcon#read 5, iclass 33, count 0 2006.173.21:11:17.28#ibcon#about to read 6, iclass 33, count 0 2006.173.21:11:17.28#ibcon#read 6, iclass 33, count 0 2006.173.21:11:17.28#ibcon#end of sib2, iclass 33, count 0 2006.173.21:11:17.28#ibcon#*after write, iclass 33, count 0 2006.173.21:11:17.28#ibcon#*before return 0, iclass 33, count 0 2006.173.21:11:17.28#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.21:11:17.28#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.21:11:17.28#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.21:11:17.28#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.21:11:17.28$vck44/va=7,4 2006.173.21:11:17.28#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.21:11:17.28#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.21:11:17.28#ibcon#ireg 11 cls_cnt 2 2006.173.21:11:17.28#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.21:11:17.34#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.21:11:17.34#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.21:11:17.34#ibcon#enter wrdev, iclass 35, count 2 2006.173.21:11:17.34#ibcon#first serial, iclass 35, count 2 2006.173.21:11:17.34#ibcon#enter sib2, iclass 35, count 2 2006.173.21:11:17.34#ibcon#flushed, iclass 35, count 2 2006.173.21:11:17.34#ibcon#about to write, iclass 35, count 2 2006.173.21:11:17.34#ibcon#wrote, iclass 35, count 2 2006.173.21:11:17.34#ibcon#about to read 3, iclass 35, count 2 2006.173.21:11:17.36#ibcon#read 3, iclass 35, count 2 2006.173.21:11:17.36#ibcon#about to read 4, iclass 35, count 2 2006.173.21:11:17.36#ibcon#read 4, iclass 35, count 2 2006.173.21:11:17.36#ibcon#about to read 5, iclass 35, count 2 2006.173.21:11:17.36#ibcon#read 5, iclass 35, count 2 2006.173.21:11:17.36#ibcon#about to read 6, iclass 35, count 2 2006.173.21:11:17.36#ibcon#read 6, iclass 35, count 2 2006.173.21:11:17.36#ibcon#end of sib2, iclass 35, count 2 2006.173.21:11:17.36#ibcon#*mode == 0, iclass 35, count 2 2006.173.21:11:17.36#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.21:11:17.36#ibcon#[25=AT07-04\r\n] 2006.173.21:11:17.36#ibcon#*before write, iclass 35, count 2 2006.173.21:11:17.36#ibcon#enter sib2, iclass 35, count 2 2006.173.21:11:17.36#ibcon#flushed, iclass 35, count 2 2006.173.21:11:17.36#ibcon#about to write, iclass 35, count 2 2006.173.21:11:17.36#ibcon#wrote, iclass 35, count 2 2006.173.21:11:17.36#ibcon#about to read 3, iclass 35, count 2 2006.173.21:11:17.39#ibcon#read 3, iclass 35, count 2 2006.173.21:11:17.39#ibcon#about to read 4, iclass 35, count 2 2006.173.21:11:17.39#ibcon#read 4, iclass 35, count 2 2006.173.21:11:17.39#ibcon#about to read 5, iclass 35, count 2 2006.173.21:11:17.39#ibcon#read 5, iclass 35, count 2 2006.173.21:11:17.39#ibcon#about to read 6, iclass 35, count 2 2006.173.21:11:17.39#ibcon#read 6, iclass 35, count 2 2006.173.21:11:17.39#ibcon#end of sib2, iclass 35, count 2 2006.173.21:11:17.39#ibcon#*after write, iclass 35, count 2 2006.173.21:11:17.39#ibcon#*before return 0, iclass 35, count 2 2006.173.21:11:17.39#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.21:11:17.39#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.21:11:17.39#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.21:11:17.39#ibcon#ireg 7 cls_cnt 0 2006.173.21:11:17.39#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.21:11:17.51#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.21:11:17.51#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.21:11:17.51#ibcon#enter wrdev, iclass 35, count 0 2006.173.21:11:17.51#ibcon#first serial, iclass 35, count 0 2006.173.21:11:17.51#ibcon#enter sib2, iclass 35, count 0 2006.173.21:11:17.51#ibcon#flushed, iclass 35, count 0 2006.173.21:11:17.51#ibcon#about to write, iclass 35, count 0 2006.173.21:11:17.51#ibcon#wrote, iclass 35, count 0 2006.173.21:11:17.51#ibcon#about to read 3, iclass 35, count 0 2006.173.21:11:17.53#ibcon#read 3, iclass 35, count 0 2006.173.21:11:17.53#ibcon#about to read 4, iclass 35, count 0 2006.173.21:11:17.53#ibcon#read 4, iclass 35, count 0 2006.173.21:11:17.53#ibcon#about to read 5, iclass 35, count 0 2006.173.21:11:17.53#ibcon#read 5, iclass 35, count 0 2006.173.21:11:17.53#ibcon#about to read 6, iclass 35, count 0 2006.173.21:11:17.53#ibcon#read 6, iclass 35, count 0 2006.173.21:11:17.53#ibcon#end of sib2, iclass 35, count 0 2006.173.21:11:17.53#ibcon#*mode == 0, iclass 35, count 0 2006.173.21:11:17.53#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.21:11:17.53#ibcon#[25=USB\r\n] 2006.173.21:11:17.53#ibcon#*before write, iclass 35, count 0 2006.173.21:11:17.53#ibcon#enter sib2, iclass 35, count 0 2006.173.21:11:17.53#ibcon#flushed, iclass 35, count 0 2006.173.21:11:17.53#ibcon#about to write, iclass 35, count 0 2006.173.21:11:17.53#ibcon#wrote, iclass 35, count 0 2006.173.21:11:17.53#ibcon#about to read 3, iclass 35, count 0 2006.173.21:11:17.56#ibcon#read 3, iclass 35, count 0 2006.173.21:11:17.56#ibcon#about to read 4, iclass 35, count 0 2006.173.21:11:17.56#ibcon#read 4, iclass 35, count 0 2006.173.21:11:17.56#ibcon#about to read 5, iclass 35, count 0 2006.173.21:11:17.56#ibcon#read 5, iclass 35, count 0 2006.173.21:11:17.56#ibcon#about to read 6, iclass 35, count 0 2006.173.21:11:17.56#ibcon#read 6, iclass 35, count 0 2006.173.21:11:17.56#ibcon#end of sib2, iclass 35, count 0 2006.173.21:11:17.56#ibcon#*after write, iclass 35, count 0 2006.173.21:11:17.56#ibcon#*before return 0, iclass 35, count 0 2006.173.21:11:17.56#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.21:11:17.56#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.21:11:17.56#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.21:11:17.56#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.21:11:17.56$vck44/valo=8,884.99 2006.173.21:11:17.56#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.21:11:17.56#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.21:11:17.56#ibcon#ireg 17 cls_cnt 0 2006.173.21:11:17.56#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.21:11:17.56#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.21:11:17.56#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.21:11:17.56#ibcon#enter wrdev, iclass 37, count 0 2006.173.21:11:17.56#ibcon#first serial, iclass 37, count 0 2006.173.21:11:17.56#ibcon#enter sib2, iclass 37, count 0 2006.173.21:11:17.56#ibcon#flushed, iclass 37, count 0 2006.173.21:11:17.56#ibcon#about to write, iclass 37, count 0 2006.173.21:11:17.56#ibcon#wrote, iclass 37, count 0 2006.173.21:11:17.56#ibcon#about to read 3, iclass 37, count 0 2006.173.21:11:17.58#ibcon#read 3, iclass 37, count 0 2006.173.21:11:17.58#ibcon#about to read 4, iclass 37, count 0 2006.173.21:11:17.58#ibcon#read 4, iclass 37, count 0 2006.173.21:11:17.58#ibcon#about to read 5, iclass 37, count 0 2006.173.21:11:17.58#ibcon#read 5, iclass 37, count 0 2006.173.21:11:17.58#ibcon#about to read 6, iclass 37, count 0 2006.173.21:11:17.58#ibcon#read 6, iclass 37, count 0 2006.173.21:11:17.58#ibcon#end of sib2, iclass 37, count 0 2006.173.21:11:17.58#ibcon#*mode == 0, iclass 37, count 0 2006.173.21:11:17.58#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.21:11:17.58#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.21:11:17.58#ibcon#*before write, iclass 37, count 0 2006.173.21:11:17.58#ibcon#enter sib2, iclass 37, count 0 2006.173.21:11:17.58#ibcon#flushed, iclass 37, count 0 2006.173.21:11:17.58#ibcon#about to write, iclass 37, count 0 2006.173.21:11:17.58#ibcon#wrote, iclass 37, count 0 2006.173.21:11:17.58#ibcon#about to read 3, iclass 37, count 0 2006.173.21:11:17.62#ibcon#read 3, iclass 37, count 0 2006.173.21:11:17.62#ibcon#about to read 4, iclass 37, count 0 2006.173.21:11:17.62#ibcon#read 4, iclass 37, count 0 2006.173.21:11:17.62#ibcon#about to read 5, iclass 37, count 0 2006.173.21:11:17.62#ibcon#read 5, iclass 37, count 0 2006.173.21:11:17.62#ibcon#about to read 6, iclass 37, count 0 2006.173.21:11:17.62#ibcon#read 6, iclass 37, count 0 2006.173.21:11:17.62#ibcon#end of sib2, iclass 37, count 0 2006.173.21:11:17.62#ibcon#*after write, iclass 37, count 0 2006.173.21:11:17.62#ibcon#*before return 0, iclass 37, count 0 2006.173.21:11:17.62#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.21:11:17.62#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.21:11:17.62#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.21:11:17.62#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.21:11:17.62$vck44/va=8,4 2006.173.21:11:17.62#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.21:11:17.62#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.21:11:17.62#ibcon#ireg 11 cls_cnt 2 2006.173.21:11:17.62#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.21:11:17.68#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.21:11:17.68#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.21:11:17.68#ibcon#enter wrdev, iclass 39, count 2 2006.173.21:11:17.68#ibcon#first serial, iclass 39, count 2 2006.173.21:11:17.68#ibcon#enter sib2, iclass 39, count 2 2006.173.21:11:17.68#ibcon#flushed, iclass 39, count 2 2006.173.21:11:17.68#ibcon#about to write, iclass 39, count 2 2006.173.21:11:17.68#ibcon#wrote, iclass 39, count 2 2006.173.21:11:17.68#ibcon#about to read 3, iclass 39, count 2 2006.173.21:11:17.70#ibcon#read 3, iclass 39, count 2 2006.173.21:11:17.70#ibcon#about to read 4, iclass 39, count 2 2006.173.21:11:17.70#ibcon#read 4, iclass 39, count 2 2006.173.21:11:17.70#ibcon#about to read 5, iclass 39, count 2 2006.173.21:11:17.70#ibcon#read 5, iclass 39, count 2 2006.173.21:11:17.70#ibcon#about to read 6, iclass 39, count 2 2006.173.21:11:17.70#ibcon#read 6, iclass 39, count 2 2006.173.21:11:17.70#ibcon#end of sib2, iclass 39, count 2 2006.173.21:11:17.70#ibcon#*mode == 0, iclass 39, count 2 2006.173.21:11:17.70#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.21:11:17.70#ibcon#[25=AT08-04\r\n] 2006.173.21:11:17.70#ibcon#*before write, iclass 39, count 2 2006.173.21:11:17.70#ibcon#enter sib2, iclass 39, count 2 2006.173.21:11:17.70#ibcon#flushed, iclass 39, count 2 2006.173.21:11:17.70#ibcon#about to write, iclass 39, count 2 2006.173.21:11:17.70#ibcon#wrote, iclass 39, count 2 2006.173.21:11:17.70#ibcon#about to read 3, iclass 39, count 2 2006.173.21:11:17.73#ibcon#read 3, iclass 39, count 2 2006.173.21:11:17.73#ibcon#about to read 4, iclass 39, count 2 2006.173.21:11:17.73#ibcon#read 4, iclass 39, count 2 2006.173.21:11:17.73#ibcon#about to read 5, iclass 39, count 2 2006.173.21:11:17.73#ibcon#read 5, iclass 39, count 2 2006.173.21:11:17.73#ibcon#about to read 6, iclass 39, count 2 2006.173.21:11:17.73#ibcon#read 6, iclass 39, count 2 2006.173.21:11:17.73#ibcon#end of sib2, iclass 39, count 2 2006.173.21:11:17.73#ibcon#*after write, iclass 39, count 2 2006.173.21:11:17.73#ibcon#*before return 0, iclass 39, count 2 2006.173.21:11:17.73#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.21:11:17.73#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.21:11:17.73#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.21:11:17.73#ibcon#ireg 7 cls_cnt 0 2006.173.21:11:17.73#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.21:11:17.85#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.21:11:17.85#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.21:11:17.85#ibcon#enter wrdev, iclass 39, count 0 2006.173.21:11:17.85#ibcon#first serial, iclass 39, count 0 2006.173.21:11:17.85#ibcon#enter sib2, iclass 39, count 0 2006.173.21:11:17.85#ibcon#flushed, iclass 39, count 0 2006.173.21:11:17.85#ibcon#about to write, iclass 39, count 0 2006.173.21:11:17.85#ibcon#wrote, iclass 39, count 0 2006.173.21:11:17.85#ibcon#about to read 3, iclass 39, count 0 2006.173.21:11:17.87#ibcon#read 3, iclass 39, count 0 2006.173.21:11:17.87#ibcon#about to read 4, iclass 39, count 0 2006.173.21:11:17.87#ibcon#read 4, iclass 39, count 0 2006.173.21:11:17.87#ibcon#about to read 5, iclass 39, count 0 2006.173.21:11:17.87#ibcon#read 5, iclass 39, count 0 2006.173.21:11:17.87#ibcon#about to read 6, iclass 39, count 0 2006.173.21:11:17.87#ibcon#read 6, iclass 39, count 0 2006.173.21:11:17.87#ibcon#end of sib2, iclass 39, count 0 2006.173.21:11:17.87#ibcon#*mode == 0, iclass 39, count 0 2006.173.21:11:17.87#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.21:11:17.87#ibcon#[25=USB\r\n] 2006.173.21:11:17.87#ibcon#*before write, iclass 39, count 0 2006.173.21:11:17.87#ibcon#enter sib2, iclass 39, count 0 2006.173.21:11:17.87#ibcon#flushed, iclass 39, count 0 2006.173.21:11:17.87#ibcon#about to write, iclass 39, count 0 2006.173.21:11:17.87#ibcon#wrote, iclass 39, count 0 2006.173.21:11:17.87#ibcon#about to read 3, iclass 39, count 0 2006.173.21:11:17.90#ibcon#read 3, iclass 39, count 0 2006.173.21:11:17.90#ibcon#about to read 4, iclass 39, count 0 2006.173.21:11:17.90#ibcon#read 4, iclass 39, count 0 2006.173.21:11:17.90#ibcon#about to read 5, iclass 39, count 0 2006.173.21:11:17.90#ibcon#read 5, iclass 39, count 0 2006.173.21:11:17.90#ibcon#about to read 6, iclass 39, count 0 2006.173.21:11:17.90#ibcon#read 6, iclass 39, count 0 2006.173.21:11:17.90#ibcon#end of sib2, iclass 39, count 0 2006.173.21:11:17.90#ibcon#*after write, iclass 39, count 0 2006.173.21:11:17.90#ibcon#*before return 0, iclass 39, count 0 2006.173.21:11:17.90#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.21:11:17.90#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.21:11:17.90#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.21:11:17.90#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.21:11:17.90$vck44/vblo=1,629.99 2006.173.21:11:17.90#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.21:11:17.90#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.21:11:17.90#ibcon#ireg 17 cls_cnt 0 2006.173.21:11:17.90#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.21:11:17.90#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.21:11:17.90#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.21:11:17.90#ibcon#enter wrdev, iclass 3, count 0 2006.173.21:11:17.90#ibcon#first serial, iclass 3, count 0 2006.173.21:11:17.90#ibcon#enter sib2, iclass 3, count 0 2006.173.21:11:17.90#ibcon#flushed, iclass 3, count 0 2006.173.21:11:17.90#ibcon#about to write, iclass 3, count 0 2006.173.21:11:17.90#ibcon#wrote, iclass 3, count 0 2006.173.21:11:17.90#ibcon#about to read 3, iclass 3, count 0 2006.173.21:11:17.92#ibcon#read 3, iclass 3, count 0 2006.173.21:11:17.92#ibcon#about to read 4, iclass 3, count 0 2006.173.21:11:17.92#ibcon#read 4, iclass 3, count 0 2006.173.21:11:17.92#ibcon#about to read 5, iclass 3, count 0 2006.173.21:11:17.92#ibcon#read 5, iclass 3, count 0 2006.173.21:11:17.92#ibcon#about to read 6, iclass 3, count 0 2006.173.21:11:17.92#ibcon#read 6, iclass 3, count 0 2006.173.21:11:17.92#ibcon#end of sib2, iclass 3, count 0 2006.173.21:11:17.92#ibcon#*mode == 0, iclass 3, count 0 2006.173.21:11:17.92#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.21:11:17.92#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.21:11:17.92#ibcon#*before write, iclass 3, count 0 2006.173.21:11:17.92#ibcon#enter sib2, iclass 3, count 0 2006.173.21:11:17.92#ibcon#flushed, iclass 3, count 0 2006.173.21:11:17.92#ibcon#about to write, iclass 3, count 0 2006.173.21:11:17.92#ibcon#wrote, iclass 3, count 0 2006.173.21:11:17.92#ibcon#about to read 3, iclass 3, count 0 2006.173.21:11:17.96#ibcon#read 3, iclass 3, count 0 2006.173.21:11:17.96#ibcon#about to read 4, iclass 3, count 0 2006.173.21:11:17.96#ibcon#read 4, iclass 3, count 0 2006.173.21:11:17.96#ibcon#about to read 5, iclass 3, count 0 2006.173.21:11:17.96#ibcon#read 5, iclass 3, count 0 2006.173.21:11:17.96#ibcon#about to read 6, iclass 3, count 0 2006.173.21:11:17.96#ibcon#read 6, iclass 3, count 0 2006.173.21:11:17.96#ibcon#end of sib2, iclass 3, count 0 2006.173.21:11:17.96#ibcon#*after write, iclass 3, count 0 2006.173.21:11:17.96#ibcon#*before return 0, iclass 3, count 0 2006.173.21:11:17.96#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.21:11:17.96#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.21:11:17.96#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.21:11:17.96#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.21:11:17.96$vck44/vb=1,4 2006.173.21:11:17.96#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.21:11:17.96#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.21:11:17.96#ibcon#ireg 11 cls_cnt 2 2006.173.21:11:17.96#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.21:11:17.96#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.21:11:17.96#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.21:11:17.96#ibcon#enter wrdev, iclass 5, count 2 2006.173.21:11:17.96#ibcon#first serial, iclass 5, count 2 2006.173.21:11:17.96#ibcon#enter sib2, iclass 5, count 2 2006.173.21:11:17.96#ibcon#flushed, iclass 5, count 2 2006.173.21:11:17.96#ibcon#about to write, iclass 5, count 2 2006.173.21:11:17.96#ibcon#wrote, iclass 5, count 2 2006.173.21:11:17.96#ibcon#about to read 3, iclass 5, count 2 2006.173.21:11:17.98#ibcon#read 3, iclass 5, count 2 2006.173.21:11:17.98#ibcon#about to read 4, iclass 5, count 2 2006.173.21:11:17.98#ibcon#read 4, iclass 5, count 2 2006.173.21:11:17.98#ibcon#about to read 5, iclass 5, count 2 2006.173.21:11:17.98#ibcon#read 5, iclass 5, count 2 2006.173.21:11:17.98#ibcon#about to read 6, iclass 5, count 2 2006.173.21:11:17.98#ibcon#read 6, iclass 5, count 2 2006.173.21:11:17.98#ibcon#end of sib2, iclass 5, count 2 2006.173.21:11:17.98#ibcon#*mode == 0, iclass 5, count 2 2006.173.21:11:17.98#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.21:11:17.98#ibcon#[27=AT01-04\r\n] 2006.173.21:11:17.98#ibcon#*before write, iclass 5, count 2 2006.173.21:11:17.98#ibcon#enter sib2, iclass 5, count 2 2006.173.21:11:17.98#ibcon#flushed, iclass 5, count 2 2006.173.21:11:17.98#ibcon#about to write, iclass 5, count 2 2006.173.21:11:17.98#ibcon#wrote, iclass 5, count 2 2006.173.21:11:17.98#ibcon#about to read 3, iclass 5, count 2 2006.173.21:11:18.01#ibcon#read 3, iclass 5, count 2 2006.173.21:11:18.01#ibcon#about to read 4, iclass 5, count 2 2006.173.21:11:18.01#ibcon#read 4, iclass 5, count 2 2006.173.21:11:18.01#ibcon#about to read 5, iclass 5, count 2 2006.173.21:11:18.01#ibcon#read 5, iclass 5, count 2 2006.173.21:11:18.01#ibcon#about to read 6, iclass 5, count 2 2006.173.21:11:18.01#ibcon#read 6, iclass 5, count 2 2006.173.21:11:18.01#ibcon#end of sib2, iclass 5, count 2 2006.173.21:11:18.01#ibcon#*after write, iclass 5, count 2 2006.173.21:11:18.01#ibcon#*before return 0, iclass 5, count 2 2006.173.21:11:18.01#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.21:11:18.01#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.21:11:18.01#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.21:11:18.01#ibcon#ireg 7 cls_cnt 0 2006.173.21:11:18.01#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.21:11:18.13#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.21:11:18.13#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.21:11:18.13#ibcon#enter wrdev, iclass 5, count 0 2006.173.21:11:18.13#ibcon#first serial, iclass 5, count 0 2006.173.21:11:18.13#ibcon#enter sib2, iclass 5, count 0 2006.173.21:11:18.13#ibcon#flushed, iclass 5, count 0 2006.173.21:11:18.13#ibcon#about to write, iclass 5, count 0 2006.173.21:11:18.13#ibcon#wrote, iclass 5, count 0 2006.173.21:11:18.13#ibcon#about to read 3, iclass 5, count 0 2006.173.21:11:18.15#ibcon#read 3, iclass 5, count 0 2006.173.21:11:18.15#ibcon#about to read 4, iclass 5, count 0 2006.173.21:11:18.15#ibcon#read 4, iclass 5, count 0 2006.173.21:11:18.15#ibcon#about to read 5, iclass 5, count 0 2006.173.21:11:18.15#ibcon#read 5, iclass 5, count 0 2006.173.21:11:18.15#ibcon#about to read 6, iclass 5, count 0 2006.173.21:11:18.15#ibcon#read 6, iclass 5, count 0 2006.173.21:11:18.15#ibcon#end of sib2, iclass 5, count 0 2006.173.21:11:18.15#ibcon#*mode == 0, iclass 5, count 0 2006.173.21:11:18.15#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.21:11:18.15#ibcon#[27=USB\r\n] 2006.173.21:11:18.15#ibcon#*before write, iclass 5, count 0 2006.173.21:11:18.15#ibcon#enter sib2, iclass 5, count 0 2006.173.21:11:18.15#ibcon#flushed, iclass 5, count 0 2006.173.21:11:18.15#ibcon#about to write, iclass 5, count 0 2006.173.21:11:18.15#ibcon#wrote, iclass 5, count 0 2006.173.21:11:18.15#ibcon#about to read 3, iclass 5, count 0 2006.173.21:11:18.18#ibcon#read 3, iclass 5, count 0 2006.173.21:11:18.18#ibcon#about to read 4, iclass 5, count 0 2006.173.21:11:18.18#ibcon#read 4, iclass 5, count 0 2006.173.21:11:18.18#ibcon#about to read 5, iclass 5, count 0 2006.173.21:11:18.18#ibcon#read 5, iclass 5, count 0 2006.173.21:11:18.18#ibcon#about to read 6, iclass 5, count 0 2006.173.21:11:18.18#ibcon#read 6, iclass 5, count 0 2006.173.21:11:18.18#ibcon#end of sib2, iclass 5, count 0 2006.173.21:11:18.18#ibcon#*after write, iclass 5, count 0 2006.173.21:11:18.18#ibcon#*before return 0, iclass 5, count 0 2006.173.21:11:18.18#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.21:11:18.18#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.21:11:18.18#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.21:11:18.18#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.21:11:18.18$vck44/vblo=2,634.99 2006.173.21:11:18.18#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.21:11:18.18#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.21:11:18.18#ibcon#ireg 17 cls_cnt 0 2006.173.21:11:18.18#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.21:11:18.18#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.21:11:18.18#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.21:11:18.18#ibcon#enter wrdev, iclass 7, count 0 2006.173.21:11:18.18#ibcon#first serial, iclass 7, count 0 2006.173.21:11:18.18#ibcon#enter sib2, iclass 7, count 0 2006.173.21:11:18.18#ibcon#flushed, iclass 7, count 0 2006.173.21:11:18.18#ibcon#about to write, iclass 7, count 0 2006.173.21:11:18.18#ibcon#wrote, iclass 7, count 0 2006.173.21:11:18.18#ibcon#about to read 3, iclass 7, count 0 2006.173.21:11:18.20#ibcon#read 3, iclass 7, count 0 2006.173.21:11:18.20#ibcon#about to read 4, iclass 7, count 0 2006.173.21:11:18.20#ibcon#read 4, iclass 7, count 0 2006.173.21:11:18.20#ibcon#about to read 5, iclass 7, count 0 2006.173.21:11:18.20#ibcon#read 5, iclass 7, count 0 2006.173.21:11:18.20#ibcon#about to read 6, iclass 7, count 0 2006.173.21:11:18.20#ibcon#read 6, iclass 7, count 0 2006.173.21:11:18.20#ibcon#end of sib2, iclass 7, count 0 2006.173.21:11:18.20#ibcon#*mode == 0, iclass 7, count 0 2006.173.21:11:18.20#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.21:11:18.20#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.21:11:18.20#ibcon#*before write, iclass 7, count 0 2006.173.21:11:18.20#ibcon#enter sib2, iclass 7, count 0 2006.173.21:11:18.20#ibcon#flushed, iclass 7, count 0 2006.173.21:11:18.20#ibcon#about to write, iclass 7, count 0 2006.173.21:11:18.20#ibcon#wrote, iclass 7, count 0 2006.173.21:11:18.20#ibcon#about to read 3, iclass 7, count 0 2006.173.21:11:18.24#ibcon#read 3, iclass 7, count 0 2006.173.21:11:18.24#ibcon#about to read 4, iclass 7, count 0 2006.173.21:11:18.24#ibcon#read 4, iclass 7, count 0 2006.173.21:11:18.24#ibcon#about to read 5, iclass 7, count 0 2006.173.21:11:18.24#ibcon#read 5, iclass 7, count 0 2006.173.21:11:18.24#ibcon#about to read 6, iclass 7, count 0 2006.173.21:11:18.24#ibcon#read 6, iclass 7, count 0 2006.173.21:11:18.24#ibcon#end of sib2, iclass 7, count 0 2006.173.21:11:18.24#ibcon#*after write, iclass 7, count 0 2006.173.21:11:18.24#ibcon#*before return 0, iclass 7, count 0 2006.173.21:11:18.24#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.21:11:18.24#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.21:11:18.24#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.21:11:18.24#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.21:11:18.24$vck44/vb=2,4 2006.173.21:11:18.24#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.21:11:18.24#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.21:11:18.24#ibcon#ireg 11 cls_cnt 2 2006.173.21:11:18.24#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.21:11:18.30#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.21:11:18.30#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.21:11:18.30#ibcon#enter wrdev, iclass 11, count 2 2006.173.21:11:18.30#ibcon#first serial, iclass 11, count 2 2006.173.21:11:18.30#ibcon#enter sib2, iclass 11, count 2 2006.173.21:11:18.30#ibcon#flushed, iclass 11, count 2 2006.173.21:11:18.30#ibcon#about to write, iclass 11, count 2 2006.173.21:11:18.30#ibcon#wrote, iclass 11, count 2 2006.173.21:11:18.30#ibcon#about to read 3, iclass 11, count 2 2006.173.21:11:18.32#ibcon#read 3, iclass 11, count 2 2006.173.21:11:18.32#ibcon#about to read 4, iclass 11, count 2 2006.173.21:11:18.32#ibcon#read 4, iclass 11, count 2 2006.173.21:11:18.32#ibcon#about to read 5, iclass 11, count 2 2006.173.21:11:18.32#ibcon#read 5, iclass 11, count 2 2006.173.21:11:18.32#ibcon#about to read 6, iclass 11, count 2 2006.173.21:11:18.32#ibcon#read 6, iclass 11, count 2 2006.173.21:11:18.32#ibcon#end of sib2, iclass 11, count 2 2006.173.21:11:18.32#ibcon#*mode == 0, iclass 11, count 2 2006.173.21:11:18.32#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.21:11:18.32#ibcon#[27=AT02-04\r\n] 2006.173.21:11:18.32#ibcon#*before write, iclass 11, count 2 2006.173.21:11:18.32#ibcon#enter sib2, iclass 11, count 2 2006.173.21:11:18.32#ibcon#flushed, iclass 11, count 2 2006.173.21:11:18.32#ibcon#about to write, iclass 11, count 2 2006.173.21:11:18.32#ibcon#wrote, iclass 11, count 2 2006.173.21:11:18.32#ibcon#about to read 3, iclass 11, count 2 2006.173.21:11:18.35#ibcon#read 3, iclass 11, count 2 2006.173.21:11:18.35#ibcon#about to read 4, iclass 11, count 2 2006.173.21:11:18.35#ibcon#read 4, iclass 11, count 2 2006.173.21:11:18.35#ibcon#about to read 5, iclass 11, count 2 2006.173.21:11:18.35#ibcon#read 5, iclass 11, count 2 2006.173.21:11:18.35#ibcon#about to read 6, iclass 11, count 2 2006.173.21:11:18.35#ibcon#read 6, iclass 11, count 2 2006.173.21:11:18.35#ibcon#end of sib2, iclass 11, count 2 2006.173.21:11:18.35#ibcon#*after write, iclass 11, count 2 2006.173.21:11:18.35#ibcon#*before return 0, iclass 11, count 2 2006.173.21:11:18.35#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.21:11:18.35#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.21:11:18.35#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.21:11:18.35#ibcon#ireg 7 cls_cnt 0 2006.173.21:11:18.35#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.21:11:18.47#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.21:11:18.47#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.21:11:18.47#ibcon#enter wrdev, iclass 11, count 0 2006.173.21:11:18.47#ibcon#first serial, iclass 11, count 0 2006.173.21:11:18.47#ibcon#enter sib2, iclass 11, count 0 2006.173.21:11:18.47#ibcon#flushed, iclass 11, count 0 2006.173.21:11:18.47#ibcon#about to write, iclass 11, count 0 2006.173.21:11:18.47#ibcon#wrote, iclass 11, count 0 2006.173.21:11:18.47#ibcon#about to read 3, iclass 11, count 0 2006.173.21:11:18.49#ibcon#read 3, iclass 11, count 0 2006.173.21:11:18.49#ibcon#about to read 4, iclass 11, count 0 2006.173.21:11:18.49#ibcon#read 4, iclass 11, count 0 2006.173.21:11:18.49#ibcon#about to read 5, iclass 11, count 0 2006.173.21:11:18.49#ibcon#read 5, iclass 11, count 0 2006.173.21:11:18.49#ibcon#about to read 6, iclass 11, count 0 2006.173.21:11:18.49#ibcon#read 6, iclass 11, count 0 2006.173.21:11:18.49#ibcon#end of sib2, iclass 11, count 0 2006.173.21:11:18.49#ibcon#*mode == 0, iclass 11, count 0 2006.173.21:11:18.49#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.21:11:18.49#ibcon#[27=USB\r\n] 2006.173.21:11:18.49#ibcon#*before write, iclass 11, count 0 2006.173.21:11:18.49#ibcon#enter sib2, iclass 11, count 0 2006.173.21:11:18.49#ibcon#flushed, iclass 11, count 0 2006.173.21:11:18.49#ibcon#about to write, iclass 11, count 0 2006.173.21:11:18.49#ibcon#wrote, iclass 11, count 0 2006.173.21:11:18.49#ibcon#about to read 3, iclass 11, count 0 2006.173.21:11:18.52#ibcon#read 3, iclass 11, count 0 2006.173.21:11:18.52#ibcon#about to read 4, iclass 11, count 0 2006.173.21:11:18.52#ibcon#read 4, iclass 11, count 0 2006.173.21:11:18.52#ibcon#about to read 5, iclass 11, count 0 2006.173.21:11:18.52#ibcon#read 5, iclass 11, count 0 2006.173.21:11:18.52#ibcon#about to read 6, iclass 11, count 0 2006.173.21:11:18.52#ibcon#read 6, iclass 11, count 0 2006.173.21:11:18.52#ibcon#end of sib2, iclass 11, count 0 2006.173.21:11:18.52#ibcon#*after write, iclass 11, count 0 2006.173.21:11:18.52#ibcon#*before return 0, iclass 11, count 0 2006.173.21:11:18.52#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.21:11:18.52#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.21:11:18.52#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.21:11:18.52#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.21:11:18.52$vck44/vblo=3,649.99 2006.173.21:11:18.52#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.21:11:18.52#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.21:11:18.52#ibcon#ireg 17 cls_cnt 0 2006.173.21:11:18.52#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.21:11:18.52#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.21:11:18.52#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.21:11:18.52#ibcon#enter wrdev, iclass 13, count 0 2006.173.21:11:18.52#ibcon#first serial, iclass 13, count 0 2006.173.21:11:18.52#ibcon#enter sib2, iclass 13, count 0 2006.173.21:11:18.52#ibcon#flushed, iclass 13, count 0 2006.173.21:11:18.52#ibcon#about to write, iclass 13, count 0 2006.173.21:11:18.52#ibcon#wrote, iclass 13, count 0 2006.173.21:11:18.52#ibcon#about to read 3, iclass 13, count 0 2006.173.21:11:18.54#ibcon#read 3, iclass 13, count 0 2006.173.21:11:18.54#ibcon#about to read 4, iclass 13, count 0 2006.173.21:11:18.54#ibcon#read 4, iclass 13, count 0 2006.173.21:11:18.54#ibcon#about to read 5, iclass 13, count 0 2006.173.21:11:18.54#ibcon#read 5, iclass 13, count 0 2006.173.21:11:18.54#ibcon#about to read 6, iclass 13, count 0 2006.173.21:11:18.54#ibcon#read 6, iclass 13, count 0 2006.173.21:11:18.54#ibcon#end of sib2, iclass 13, count 0 2006.173.21:11:18.54#ibcon#*mode == 0, iclass 13, count 0 2006.173.21:11:18.54#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.21:11:18.54#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.21:11:18.54#ibcon#*before write, iclass 13, count 0 2006.173.21:11:18.54#ibcon#enter sib2, iclass 13, count 0 2006.173.21:11:18.54#ibcon#flushed, iclass 13, count 0 2006.173.21:11:18.54#ibcon#about to write, iclass 13, count 0 2006.173.21:11:18.54#ibcon#wrote, iclass 13, count 0 2006.173.21:11:18.54#ibcon#about to read 3, iclass 13, count 0 2006.173.21:11:18.58#ibcon#read 3, iclass 13, count 0 2006.173.21:11:18.58#ibcon#about to read 4, iclass 13, count 0 2006.173.21:11:18.58#ibcon#read 4, iclass 13, count 0 2006.173.21:11:18.58#ibcon#about to read 5, iclass 13, count 0 2006.173.21:11:18.58#ibcon#read 5, iclass 13, count 0 2006.173.21:11:18.58#ibcon#about to read 6, iclass 13, count 0 2006.173.21:11:18.58#ibcon#read 6, iclass 13, count 0 2006.173.21:11:18.58#ibcon#end of sib2, iclass 13, count 0 2006.173.21:11:18.58#ibcon#*after write, iclass 13, count 0 2006.173.21:11:18.58#ibcon#*before return 0, iclass 13, count 0 2006.173.21:11:18.58#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.21:11:18.58#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.21:11:18.58#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.21:11:18.58#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.21:11:18.58$vck44/vb=3,4 2006.173.21:11:18.58#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.21:11:18.58#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.21:11:18.58#ibcon#ireg 11 cls_cnt 2 2006.173.21:11:18.58#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.21:11:18.64#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.21:11:18.64#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.21:11:18.64#ibcon#enter wrdev, iclass 15, count 2 2006.173.21:11:18.64#ibcon#first serial, iclass 15, count 2 2006.173.21:11:18.64#ibcon#enter sib2, iclass 15, count 2 2006.173.21:11:18.64#ibcon#flushed, iclass 15, count 2 2006.173.21:11:18.64#ibcon#about to write, iclass 15, count 2 2006.173.21:11:18.64#ibcon#wrote, iclass 15, count 2 2006.173.21:11:18.64#ibcon#about to read 3, iclass 15, count 2 2006.173.21:11:18.66#ibcon#read 3, iclass 15, count 2 2006.173.21:11:18.66#ibcon#about to read 4, iclass 15, count 2 2006.173.21:11:18.66#ibcon#read 4, iclass 15, count 2 2006.173.21:11:18.66#ibcon#about to read 5, iclass 15, count 2 2006.173.21:11:18.66#ibcon#read 5, iclass 15, count 2 2006.173.21:11:18.66#ibcon#about to read 6, iclass 15, count 2 2006.173.21:11:18.66#ibcon#read 6, iclass 15, count 2 2006.173.21:11:18.66#ibcon#end of sib2, iclass 15, count 2 2006.173.21:11:18.66#ibcon#*mode == 0, iclass 15, count 2 2006.173.21:11:18.66#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.21:11:18.66#ibcon#[27=AT03-04\r\n] 2006.173.21:11:18.66#ibcon#*before write, iclass 15, count 2 2006.173.21:11:18.66#ibcon#enter sib2, iclass 15, count 2 2006.173.21:11:18.66#ibcon#flushed, iclass 15, count 2 2006.173.21:11:18.66#ibcon#about to write, iclass 15, count 2 2006.173.21:11:18.66#ibcon#wrote, iclass 15, count 2 2006.173.21:11:18.66#ibcon#about to read 3, iclass 15, count 2 2006.173.21:11:18.69#ibcon#read 3, iclass 15, count 2 2006.173.21:11:18.69#ibcon#about to read 4, iclass 15, count 2 2006.173.21:11:18.69#ibcon#read 4, iclass 15, count 2 2006.173.21:11:18.69#ibcon#about to read 5, iclass 15, count 2 2006.173.21:11:18.69#ibcon#read 5, iclass 15, count 2 2006.173.21:11:18.69#ibcon#about to read 6, iclass 15, count 2 2006.173.21:11:18.69#ibcon#read 6, iclass 15, count 2 2006.173.21:11:18.69#ibcon#end of sib2, iclass 15, count 2 2006.173.21:11:18.69#ibcon#*after write, iclass 15, count 2 2006.173.21:11:18.69#ibcon#*before return 0, iclass 15, count 2 2006.173.21:11:18.69#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.21:11:18.69#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.21:11:18.69#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.21:11:18.69#ibcon#ireg 7 cls_cnt 0 2006.173.21:11:18.69#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.21:11:18.81#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.21:11:18.81#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.21:11:18.81#ibcon#enter wrdev, iclass 15, count 0 2006.173.21:11:18.81#ibcon#first serial, iclass 15, count 0 2006.173.21:11:18.81#ibcon#enter sib2, iclass 15, count 0 2006.173.21:11:18.81#ibcon#flushed, iclass 15, count 0 2006.173.21:11:18.81#ibcon#about to write, iclass 15, count 0 2006.173.21:11:18.81#ibcon#wrote, iclass 15, count 0 2006.173.21:11:18.81#ibcon#about to read 3, iclass 15, count 0 2006.173.21:11:18.83#ibcon#read 3, iclass 15, count 0 2006.173.21:11:18.83#ibcon#about to read 4, iclass 15, count 0 2006.173.21:11:18.83#ibcon#read 4, iclass 15, count 0 2006.173.21:11:18.83#ibcon#about to read 5, iclass 15, count 0 2006.173.21:11:18.83#ibcon#read 5, iclass 15, count 0 2006.173.21:11:18.83#ibcon#about to read 6, iclass 15, count 0 2006.173.21:11:18.83#ibcon#read 6, iclass 15, count 0 2006.173.21:11:18.83#ibcon#end of sib2, iclass 15, count 0 2006.173.21:11:18.83#ibcon#*mode == 0, iclass 15, count 0 2006.173.21:11:18.83#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.21:11:18.83#ibcon#[27=USB\r\n] 2006.173.21:11:18.83#ibcon#*before write, iclass 15, count 0 2006.173.21:11:18.83#ibcon#enter sib2, iclass 15, count 0 2006.173.21:11:18.83#ibcon#flushed, iclass 15, count 0 2006.173.21:11:18.83#ibcon#about to write, iclass 15, count 0 2006.173.21:11:18.83#ibcon#wrote, iclass 15, count 0 2006.173.21:11:18.83#ibcon#about to read 3, iclass 15, count 0 2006.173.21:11:18.86#ibcon#read 3, iclass 15, count 0 2006.173.21:11:18.86#ibcon#about to read 4, iclass 15, count 0 2006.173.21:11:18.86#ibcon#read 4, iclass 15, count 0 2006.173.21:11:18.86#ibcon#about to read 5, iclass 15, count 0 2006.173.21:11:18.86#ibcon#read 5, iclass 15, count 0 2006.173.21:11:18.86#ibcon#about to read 6, iclass 15, count 0 2006.173.21:11:18.86#ibcon#read 6, iclass 15, count 0 2006.173.21:11:18.86#ibcon#end of sib2, iclass 15, count 0 2006.173.21:11:18.86#ibcon#*after write, iclass 15, count 0 2006.173.21:11:18.86#ibcon#*before return 0, iclass 15, count 0 2006.173.21:11:18.86#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.21:11:18.86#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.21:11:18.86#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.21:11:18.86#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.21:11:18.86$vck44/vblo=4,679.99 2006.173.21:11:18.86#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.21:11:18.86#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.21:11:18.86#ibcon#ireg 17 cls_cnt 0 2006.173.21:11:18.86#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.21:11:18.86#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.21:11:18.86#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.21:11:18.86#ibcon#enter wrdev, iclass 17, count 0 2006.173.21:11:18.86#ibcon#first serial, iclass 17, count 0 2006.173.21:11:18.86#ibcon#enter sib2, iclass 17, count 0 2006.173.21:11:18.86#ibcon#flushed, iclass 17, count 0 2006.173.21:11:18.86#ibcon#about to write, iclass 17, count 0 2006.173.21:11:18.86#ibcon#wrote, iclass 17, count 0 2006.173.21:11:18.86#ibcon#about to read 3, iclass 17, count 0 2006.173.21:11:18.88#ibcon#read 3, iclass 17, count 0 2006.173.21:11:18.88#ibcon#about to read 4, iclass 17, count 0 2006.173.21:11:18.88#ibcon#read 4, iclass 17, count 0 2006.173.21:11:18.88#ibcon#about to read 5, iclass 17, count 0 2006.173.21:11:18.88#ibcon#read 5, iclass 17, count 0 2006.173.21:11:18.88#ibcon#about to read 6, iclass 17, count 0 2006.173.21:11:18.88#ibcon#read 6, iclass 17, count 0 2006.173.21:11:18.88#ibcon#end of sib2, iclass 17, count 0 2006.173.21:11:18.88#ibcon#*mode == 0, iclass 17, count 0 2006.173.21:11:18.88#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.21:11:18.88#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.21:11:18.88#ibcon#*before write, iclass 17, count 0 2006.173.21:11:18.88#ibcon#enter sib2, iclass 17, count 0 2006.173.21:11:18.88#ibcon#flushed, iclass 17, count 0 2006.173.21:11:18.88#ibcon#about to write, iclass 17, count 0 2006.173.21:11:18.88#ibcon#wrote, iclass 17, count 0 2006.173.21:11:18.88#ibcon#about to read 3, iclass 17, count 0 2006.173.21:11:18.92#ibcon#read 3, iclass 17, count 0 2006.173.21:11:18.92#ibcon#about to read 4, iclass 17, count 0 2006.173.21:11:18.92#ibcon#read 4, iclass 17, count 0 2006.173.21:11:18.92#ibcon#about to read 5, iclass 17, count 0 2006.173.21:11:18.92#ibcon#read 5, iclass 17, count 0 2006.173.21:11:18.92#ibcon#about to read 6, iclass 17, count 0 2006.173.21:11:18.92#ibcon#read 6, iclass 17, count 0 2006.173.21:11:18.92#ibcon#end of sib2, iclass 17, count 0 2006.173.21:11:18.92#ibcon#*after write, iclass 17, count 0 2006.173.21:11:18.92#ibcon#*before return 0, iclass 17, count 0 2006.173.21:11:18.92#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.21:11:18.92#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.21:11:18.92#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.21:11:18.92#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.21:11:18.92$vck44/vb=4,4 2006.173.21:11:18.92#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.21:11:18.92#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.21:11:18.92#ibcon#ireg 11 cls_cnt 2 2006.173.21:11:18.92#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.21:11:18.98#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.21:11:18.98#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.21:11:18.98#ibcon#enter wrdev, iclass 19, count 2 2006.173.21:11:18.98#ibcon#first serial, iclass 19, count 2 2006.173.21:11:18.98#ibcon#enter sib2, iclass 19, count 2 2006.173.21:11:18.98#ibcon#flushed, iclass 19, count 2 2006.173.21:11:18.98#ibcon#about to write, iclass 19, count 2 2006.173.21:11:18.98#ibcon#wrote, iclass 19, count 2 2006.173.21:11:18.98#ibcon#about to read 3, iclass 19, count 2 2006.173.21:11:19.00#ibcon#read 3, iclass 19, count 2 2006.173.21:11:19.00#ibcon#about to read 4, iclass 19, count 2 2006.173.21:11:19.00#ibcon#read 4, iclass 19, count 2 2006.173.21:11:19.00#ibcon#about to read 5, iclass 19, count 2 2006.173.21:11:19.00#ibcon#read 5, iclass 19, count 2 2006.173.21:11:19.00#ibcon#about to read 6, iclass 19, count 2 2006.173.21:11:19.00#ibcon#read 6, iclass 19, count 2 2006.173.21:11:19.00#ibcon#end of sib2, iclass 19, count 2 2006.173.21:11:19.00#ibcon#*mode == 0, iclass 19, count 2 2006.173.21:11:19.00#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.21:11:19.00#ibcon#[27=AT04-04\r\n] 2006.173.21:11:19.00#ibcon#*before write, iclass 19, count 2 2006.173.21:11:19.00#ibcon#enter sib2, iclass 19, count 2 2006.173.21:11:19.00#ibcon#flushed, iclass 19, count 2 2006.173.21:11:19.00#ibcon#about to write, iclass 19, count 2 2006.173.21:11:19.00#ibcon#wrote, iclass 19, count 2 2006.173.21:11:19.00#ibcon#about to read 3, iclass 19, count 2 2006.173.21:11:19.03#ibcon#read 3, iclass 19, count 2 2006.173.21:11:19.03#ibcon#about to read 4, iclass 19, count 2 2006.173.21:11:19.03#ibcon#read 4, iclass 19, count 2 2006.173.21:11:19.03#ibcon#about to read 5, iclass 19, count 2 2006.173.21:11:19.03#ibcon#read 5, iclass 19, count 2 2006.173.21:11:19.03#ibcon#about to read 6, iclass 19, count 2 2006.173.21:11:19.03#ibcon#read 6, iclass 19, count 2 2006.173.21:11:19.03#ibcon#end of sib2, iclass 19, count 2 2006.173.21:11:19.03#ibcon#*after write, iclass 19, count 2 2006.173.21:11:19.03#ibcon#*before return 0, iclass 19, count 2 2006.173.21:11:19.03#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.21:11:19.03#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.21:11:19.03#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.21:11:19.03#ibcon#ireg 7 cls_cnt 0 2006.173.21:11:19.03#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.21:11:19.15#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.21:11:19.15#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.21:11:19.15#ibcon#enter wrdev, iclass 19, count 0 2006.173.21:11:19.15#ibcon#first serial, iclass 19, count 0 2006.173.21:11:19.15#ibcon#enter sib2, iclass 19, count 0 2006.173.21:11:19.15#ibcon#flushed, iclass 19, count 0 2006.173.21:11:19.15#ibcon#about to write, iclass 19, count 0 2006.173.21:11:19.15#ibcon#wrote, iclass 19, count 0 2006.173.21:11:19.15#ibcon#about to read 3, iclass 19, count 0 2006.173.21:11:19.17#ibcon#read 3, iclass 19, count 0 2006.173.21:11:19.17#ibcon#about to read 4, iclass 19, count 0 2006.173.21:11:19.17#ibcon#read 4, iclass 19, count 0 2006.173.21:11:19.17#ibcon#about to read 5, iclass 19, count 0 2006.173.21:11:19.17#ibcon#read 5, iclass 19, count 0 2006.173.21:11:19.17#ibcon#about to read 6, iclass 19, count 0 2006.173.21:11:19.17#ibcon#read 6, iclass 19, count 0 2006.173.21:11:19.17#ibcon#end of sib2, iclass 19, count 0 2006.173.21:11:19.17#ibcon#*mode == 0, iclass 19, count 0 2006.173.21:11:19.17#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.21:11:19.17#ibcon#[27=USB\r\n] 2006.173.21:11:19.17#ibcon#*before write, iclass 19, count 0 2006.173.21:11:19.17#ibcon#enter sib2, iclass 19, count 0 2006.173.21:11:19.17#ibcon#flushed, iclass 19, count 0 2006.173.21:11:19.17#ibcon#about to write, iclass 19, count 0 2006.173.21:11:19.17#ibcon#wrote, iclass 19, count 0 2006.173.21:11:19.17#ibcon#about to read 3, iclass 19, count 0 2006.173.21:11:19.20#ibcon#read 3, iclass 19, count 0 2006.173.21:11:19.20#ibcon#about to read 4, iclass 19, count 0 2006.173.21:11:19.20#ibcon#read 4, iclass 19, count 0 2006.173.21:11:19.20#ibcon#about to read 5, iclass 19, count 0 2006.173.21:11:19.20#ibcon#read 5, iclass 19, count 0 2006.173.21:11:19.20#ibcon#about to read 6, iclass 19, count 0 2006.173.21:11:19.20#ibcon#read 6, iclass 19, count 0 2006.173.21:11:19.20#ibcon#end of sib2, iclass 19, count 0 2006.173.21:11:19.20#ibcon#*after write, iclass 19, count 0 2006.173.21:11:19.20#ibcon#*before return 0, iclass 19, count 0 2006.173.21:11:19.20#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.21:11:19.20#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.21:11:19.20#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.21:11:19.20#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.21:11:19.20$vck44/vblo=5,709.99 2006.173.21:11:19.20#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.21:11:19.20#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.21:11:19.20#ibcon#ireg 17 cls_cnt 0 2006.173.21:11:19.20#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.21:11:19.20#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.21:11:19.20#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.21:11:19.20#ibcon#enter wrdev, iclass 21, count 0 2006.173.21:11:19.20#ibcon#first serial, iclass 21, count 0 2006.173.21:11:19.20#ibcon#enter sib2, iclass 21, count 0 2006.173.21:11:19.20#ibcon#flushed, iclass 21, count 0 2006.173.21:11:19.20#ibcon#about to write, iclass 21, count 0 2006.173.21:11:19.20#ibcon#wrote, iclass 21, count 0 2006.173.21:11:19.20#ibcon#about to read 3, iclass 21, count 0 2006.173.21:11:19.22#ibcon#read 3, iclass 21, count 0 2006.173.21:11:19.22#ibcon#about to read 4, iclass 21, count 0 2006.173.21:11:19.22#ibcon#read 4, iclass 21, count 0 2006.173.21:11:19.22#ibcon#about to read 5, iclass 21, count 0 2006.173.21:11:19.22#ibcon#read 5, iclass 21, count 0 2006.173.21:11:19.22#ibcon#about to read 6, iclass 21, count 0 2006.173.21:11:19.22#ibcon#read 6, iclass 21, count 0 2006.173.21:11:19.22#ibcon#end of sib2, iclass 21, count 0 2006.173.21:11:19.22#ibcon#*mode == 0, iclass 21, count 0 2006.173.21:11:19.22#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.21:11:19.22#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.21:11:19.22#ibcon#*before write, iclass 21, count 0 2006.173.21:11:19.22#ibcon#enter sib2, iclass 21, count 0 2006.173.21:11:19.22#ibcon#flushed, iclass 21, count 0 2006.173.21:11:19.22#ibcon#about to write, iclass 21, count 0 2006.173.21:11:19.22#ibcon#wrote, iclass 21, count 0 2006.173.21:11:19.22#ibcon#about to read 3, iclass 21, count 0 2006.173.21:11:19.26#ibcon#read 3, iclass 21, count 0 2006.173.21:11:19.26#ibcon#about to read 4, iclass 21, count 0 2006.173.21:11:19.26#ibcon#read 4, iclass 21, count 0 2006.173.21:11:19.26#ibcon#about to read 5, iclass 21, count 0 2006.173.21:11:19.26#ibcon#read 5, iclass 21, count 0 2006.173.21:11:19.26#ibcon#about to read 6, iclass 21, count 0 2006.173.21:11:19.26#ibcon#read 6, iclass 21, count 0 2006.173.21:11:19.26#ibcon#end of sib2, iclass 21, count 0 2006.173.21:11:19.26#ibcon#*after write, iclass 21, count 0 2006.173.21:11:19.26#ibcon#*before return 0, iclass 21, count 0 2006.173.21:11:19.26#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.21:11:19.26#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.21:11:19.26#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.21:11:19.26#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.21:11:19.26$vck44/vb=5,4 2006.173.21:11:19.26#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.21:11:19.26#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.21:11:19.26#ibcon#ireg 11 cls_cnt 2 2006.173.21:11:19.26#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.21:11:19.32#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.21:11:19.32#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.21:11:19.32#ibcon#enter wrdev, iclass 23, count 2 2006.173.21:11:19.32#ibcon#first serial, iclass 23, count 2 2006.173.21:11:19.32#ibcon#enter sib2, iclass 23, count 2 2006.173.21:11:19.32#ibcon#flushed, iclass 23, count 2 2006.173.21:11:19.32#ibcon#about to write, iclass 23, count 2 2006.173.21:11:19.32#ibcon#wrote, iclass 23, count 2 2006.173.21:11:19.32#ibcon#about to read 3, iclass 23, count 2 2006.173.21:11:19.34#ibcon#read 3, iclass 23, count 2 2006.173.21:11:19.34#ibcon#about to read 4, iclass 23, count 2 2006.173.21:11:19.34#ibcon#read 4, iclass 23, count 2 2006.173.21:11:19.34#ibcon#about to read 5, iclass 23, count 2 2006.173.21:11:19.34#ibcon#read 5, iclass 23, count 2 2006.173.21:11:19.34#ibcon#about to read 6, iclass 23, count 2 2006.173.21:11:19.34#ibcon#read 6, iclass 23, count 2 2006.173.21:11:19.34#ibcon#end of sib2, iclass 23, count 2 2006.173.21:11:19.34#ibcon#*mode == 0, iclass 23, count 2 2006.173.21:11:19.34#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.21:11:19.34#ibcon#[27=AT05-04\r\n] 2006.173.21:11:19.34#ibcon#*before write, iclass 23, count 2 2006.173.21:11:19.34#ibcon#enter sib2, iclass 23, count 2 2006.173.21:11:19.34#ibcon#flushed, iclass 23, count 2 2006.173.21:11:19.34#ibcon#about to write, iclass 23, count 2 2006.173.21:11:19.34#ibcon#wrote, iclass 23, count 2 2006.173.21:11:19.34#ibcon#about to read 3, iclass 23, count 2 2006.173.21:11:19.37#ibcon#read 3, iclass 23, count 2 2006.173.21:11:19.37#ibcon#about to read 4, iclass 23, count 2 2006.173.21:11:19.37#ibcon#read 4, iclass 23, count 2 2006.173.21:11:19.37#ibcon#about to read 5, iclass 23, count 2 2006.173.21:11:19.37#ibcon#read 5, iclass 23, count 2 2006.173.21:11:19.37#ibcon#about to read 6, iclass 23, count 2 2006.173.21:11:19.37#ibcon#read 6, iclass 23, count 2 2006.173.21:11:19.37#ibcon#end of sib2, iclass 23, count 2 2006.173.21:11:19.37#ibcon#*after write, iclass 23, count 2 2006.173.21:11:19.37#ibcon#*before return 0, iclass 23, count 2 2006.173.21:11:19.37#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.21:11:19.37#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.21:11:19.37#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.21:11:19.37#ibcon#ireg 7 cls_cnt 0 2006.173.21:11:19.37#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.21:11:19.49#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.21:11:19.49#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.21:11:19.49#ibcon#enter wrdev, iclass 23, count 0 2006.173.21:11:19.49#ibcon#first serial, iclass 23, count 0 2006.173.21:11:19.49#ibcon#enter sib2, iclass 23, count 0 2006.173.21:11:19.49#ibcon#flushed, iclass 23, count 0 2006.173.21:11:19.49#ibcon#about to write, iclass 23, count 0 2006.173.21:11:19.49#ibcon#wrote, iclass 23, count 0 2006.173.21:11:19.49#ibcon#about to read 3, iclass 23, count 0 2006.173.21:11:19.51#ibcon#read 3, iclass 23, count 0 2006.173.21:11:19.51#ibcon#about to read 4, iclass 23, count 0 2006.173.21:11:19.51#ibcon#read 4, iclass 23, count 0 2006.173.21:11:19.51#ibcon#about to read 5, iclass 23, count 0 2006.173.21:11:19.51#ibcon#read 5, iclass 23, count 0 2006.173.21:11:19.51#ibcon#about to read 6, iclass 23, count 0 2006.173.21:11:19.51#ibcon#read 6, iclass 23, count 0 2006.173.21:11:19.51#ibcon#end of sib2, iclass 23, count 0 2006.173.21:11:19.51#ibcon#*mode == 0, iclass 23, count 0 2006.173.21:11:19.51#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.21:11:19.51#ibcon#[27=USB\r\n] 2006.173.21:11:19.51#ibcon#*before write, iclass 23, count 0 2006.173.21:11:19.51#ibcon#enter sib2, iclass 23, count 0 2006.173.21:11:19.51#ibcon#flushed, iclass 23, count 0 2006.173.21:11:19.51#ibcon#about to write, iclass 23, count 0 2006.173.21:11:19.51#ibcon#wrote, iclass 23, count 0 2006.173.21:11:19.51#ibcon#about to read 3, iclass 23, count 0 2006.173.21:11:19.54#ibcon#read 3, iclass 23, count 0 2006.173.21:11:19.54#ibcon#about to read 4, iclass 23, count 0 2006.173.21:11:19.54#ibcon#read 4, iclass 23, count 0 2006.173.21:11:19.54#ibcon#about to read 5, iclass 23, count 0 2006.173.21:11:19.54#ibcon#read 5, iclass 23, count 0 2006.173.21:11:19.54#ibcon#about to read 6, iclass 23, count 0 2006.173.21:11:19.54#ibcon#read 6, iclass 23, count 0 2006.173.21:11:19.54#ibcon#end of sib2, iclass 23, count 0 2006.173.21:11:19.54#ibcon#*after write, iclass 23, count 0 2006.173.21:11:19.54#ibcon#*before return 0, iclass 23, count 0 2006.173.21:11:19.54#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.21:11:19.54#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.21:11:19.54#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.21:11:19.54#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.21:11:19.54$vck44/vblo=6,719.99 2006.173.21:11:19.54#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.21:11:19.54#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.21:11:19.54#ibcon#ireg 17 cls_cnt 0 2006.173.21:11:19.54#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.21:11:19.54#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.21:11:19.54#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.21:11:19.54#ibcon#enter wrdev, iclass 25, count 0 2006.173.21:11:19.54#ibcon#first serial, iclass 25, count 0 2006.173.21:11:19.54#ibcon#enter sib2, iclass 25, count 0 2006.173.21:11:19.54#ibcon#flushed, iclass 25, count 0 2006.173.21:11:19.54#ibcon#about to write, iclass 25, count 0 2006.173.21:11:19.54#ibcon#wrote, iclass 25, count 0 2006.173.21:11:19.54#ibcon#about to read 3, iclass 25, count 0 2006.173.21:11:19.56#ibcon#read 3, iclass 25, count 0 2006.173.21:11:19.56#ibcon#about to read 4, iclass 25, count 0 2006.173.21:11:19.56#ibcon#read 4, iclass 25, count 0 2006.173.21:11:19.56#ibcon#about to read 5, iclass 25, count 0 2006.173.21:11:19.56#ibcon#read 5, iclass 25, count 0 2006.173.21:11:19.56#ibcon#about to read 6, iclass 25, count 0 2006.173.21:11:19.56#ibcon#read 6, iclass 25, count 0 2006.173.21:11:19.56#ibcon#end of sib2, iclass 25, count 0 2006.173.21:11:19.56#ibcon#*mode == 0, iclass 25, count 0 2006.173.21:11:19.56#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.21:11:19.56#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.21:11:19.56#ibcon#*before write, iclass 25, count 0 2006.173.21:11:19.56#ibcon#enter sib2, iclass 25, count 0 2006.173.21:11:19.56#ibcon#flushed, iclass 25, count 0 2006.173.21:11:19.56#ibcon#about to write, iclass 25, count 0 2006.173.21:11:19.56#ibcon#wrote, iclass 25, count 0 2006.173.21:11:19.56#ibcon#about to read 3, iclass 25, count 0 2006.173.21:11:19.60#ibcon#read 3, iclass 25, count 0 2006.173.21:11:19.60#ibcon#about to read 4, iclass 25, count 0 2006.173.21:11:19.60#ibcon#read 4, iclass 25, count 0 2006.173.21:11:19.60#ibcon#about to read 5, iclass 25, count 0 2006.173.21:11:19.60#ibcon#read 5, iclass 25, count 0 2006.173.21:11:19.60#ibcon#about to read 6, iclass 25, count 0 2006.173.21:11:19.60#ibcon#read 6, iclass 25, count 0 2006.173.21:11:19.60#ibcon#end of sib2, iclass 25, count 0 2006.173.21:11:19.60#ibcon#*after write, iclass 25, count 0 2006.173.21:11:19.60#ibcon#*before return 0, iclass 25, count 0 2006.173.21:11:19.60#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.21:11:19.60#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.21:11:19.60#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.21:11:19.60#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.21:11:19.60$vck44/vb=6,4 2006.173.21:11:19.60#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.21:11:19.60#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.21:11:19.60#ibcon#ireg 11 cls_cnt 2 2006.173.21:11:19.60#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.21:11:19.66#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.21:11:19.66#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.21:11:19.66#ibcon#enter wrdev, iclass 27, count 2 2006.173.21:11:19.66#ibcon#first serial, iclass 27, count 2 2006.173.21:11:19.66#ibcon#enter sib2, iclass 27, count 2 2006.173.21:11:19.66#ibcon#flushed, iclass 27, count 2 2006.173.21:11:19.66#ibcon#about to write, iclass 27, count 2 2006.173.21:11:19.66#ibcon#wrote, iclass 27, count 2 2006.173.21:11:19.66#ibcon#about to read 3, iclass 27, count 2 2006.173.21:11:19.68#ibcon#read 3, iclass 27, count 2 2006.173.21:11:19.68#ibcon#about to read 4, iclass 27, count 2 2006.173.21:11:19.68#ibcon#read 4, iclass 27, count 2 2006.173.21:11:19.68#ibcon#about to read 5, iclass 27, count 2 2006.173.21:11:19.68#ibcon#read 5, iclass 27, count 2 2006.173.21:11:19.68#ibcon#about to read 6, iclass 27, count 2 2006.173.21:11:19.68#ibcon#read 6, iclass 27, count 2 2006.173.21:11:19.68#ibcon#end of sib2, iclass 27, count 2 2006.173.21:11:19.68#ibcon#*mode == 0, iclass 27, count 2 2006.173.21:11:19.68#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.21:11:19.68#ibcon#[27=AT06-04\r\n] 2006.173.21:11:19.68#ibcon#*before write, iclass 27, count 2 2006.173.21:11:19.68#ibcon#enter sib2, iclass 27, count 2 2006.173.21:11:19.68#ibcon#flushed, iclass 27, count 2 2006.173.21:11:19.68#ibcon#about to write, iclass 27, count 2 2006.173.21:11:19.68#ibcon#wrote, iclass 27, count 2 2006.173.21:11:19.68#ibcon#about to read 3, iclass 27, count 2 2006.173.21:11:19.71#ibcon#read 3, iclass 27, count 2 2006.173.21:11:19.71#ibcon#about to read 4, iclass 27, count 2 2006.173.21:11:19.71#ibcon#read 4, iclass 27, count 2 2006.173.21:11:19.71#ibcon#about to read 5, iclass 27, count 2 2006.173.21:11:19.71#ibcon#read 5, iclass 27, count 2 2006.173.21:11:19.71#ibcon#about to read 6, iclass 27, count 2 2006.173.21:11:19.71#ibcon#read 6, iclass 27, count 2 2006.173.21:11:19.71#ibcon#end of sib2, iclass 27, count 2 2006.173.21:11:19.71#ibcon#*after write, iclass 27, count 2 2006.173.21:11:19.71#ibcon#*before return 0, iclass 27, count 2 2006.173.21:11:19.71#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.21:11:19.71#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.21:11:19.71#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.21:11:19.71#ibcon#ireg 7 cls_cnt 0 2006.173.21:11:19.71#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.21:11:19.81#abcon#<5=/11 0.9 1.8 21.041001003.3\r\n> 2006.173.21:11:19.83#abcon#{5=INTERFACE CLEAR} 2006.173.21:11:19.83#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.21:11:19.83#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.21:11:19.83#ibcon#enter wrdev, iclass 27, count 0 2006.173.21:11:19.83#ibcon#first serial, iclass 27, count 0 2006.173.21:11:19.83#ibcon#enter sib2, iclass 27, count 0 2006.173.21:11:19.83#ibcon#flushed, iclass 27, count 0 2006.173.21:11:19.83#ibcon#about to write, iclass 27, count 0 2006.173.21:11:19.83#ibcon#wrote, iclass 27, count 0 2006.173.21:11:19.83#ibcon#about to read 3, iclass 27, count 0 2006.173.21:11:19.85#ibcon#read 3, iclass 27, count 0 2006.173.21:11:19.85#ibcon#about to read 4, iclass 27, count 0 2006.173.21:11:19.85#ibcon#read 4, iclass 27, count 0 2006.173.21:11:19.85#ibcon#about to read 5, iclass 27, count 0 2006.173.21:11:19.85#ibcon#read 5, iclass 27, count 0 2006.173.21:11:19.85#ibcon#about to read 6, iclass 27, count 0 2006.173.21:11:19.85#ibcon#read 6, iclass 27, count 0 2006.173.21:11:19.85#ibcon#end of sib2, iclass 27, count 0 2006.173.21:11:19.85#ibcon#*mode == 0, iclass 27, count 0 2006.173.21:11:19.85#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.21:11:19.85#ibcon#[27=USB\r\n] 2006.173.21:11:19.85#ibcon#*before write, iclass 27, count 0 2006.173.21:11:19.85#ibcon#enter sib2, iclass 27, count 0 2006.173.21:11:19.85#ibcon#flushed, iclass 27, count 0 2006.173.21:11:19.85#ibcon#about to write, iclass 27, count 0 2006.173.21:11:19.85#ibcon#wrote, iclass 27, count 0 2006.173.21:11:19.85#ibcon#about to read 3, iclass 27, count 0 2006.173.21:11:19.88#ibcon#read 3, iclass 27, count 0 2006.173.21:11:19.88#ibcon#about to read 4, iclass 27, count 0 2006.173.21:11:19.88#ibcon#read 4, iclass 27, count 0 2006.173.21:11:19.88#ibcon#about to read 5, iclass 27, count 0 2006.173.21:11:19.88#ibcon#read 5, iclass 27, count 0 2006.173.21:11:19.88#ibcon#about to read 6, iclass 27, count 0 2006.173.21:11:19.88#ibcon#read 6, iclass 27, count 0 2006.173.21:11:19.88#ibcon#end of sib2, iclass 27, count 0 2006.173.21:11:19.88#ibcon#*after write, iclass 27, count 0 2006.173.21:11:19.88#ibcon#*before return 0, iclass 27, count 0 2006.173.21:11:19.88#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.21:11:19.88#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.21:11:19.88#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.21:11:19.88#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.21:11:19.88$vck44/vblo=7,734.99 2006.173.21:11:19.88#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.21:11:19.88#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.21:11:19.88#ibcon#ireg 17 cls_cnt 0 2006.173.21:11:19.88#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.21:11:19.88#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.21:11:19.88#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.21:11:19.88#ibcon#enter wrdev, iclass 33, count 0 2006.173.21:11:19.88#ibcon#first serial, iclass 33, count 0 2006.173.21:11:19.88#ibcon#enter sib2, iclass 33, count 0 2006.173.21:11:19.88#ibcon#flushed, iclass 33, count 0 2006.173.21:11:19.88#ibcon#about to write, iclass 33, count 0 2006.173.21:11:19.88#ibcon#wrote, iclass 33, count 0 2006.173.21:11:19.88#ibcon#about to read 3, iclass 33, count 0 2006.173.21:11:19.89#abcon#[5=S1D000X0/0*\r\n] 2006.173.21:11:19.90#ibcon#read 3, iclass 33, count 0 2006.173.21:11:19.90#ibcon#about to read 4, iclass 33, count 0 2006.173.21:11:19.90#ibcon#read 4, iclass 33, count 0 2006.173.21:11:19.90#ibcon#about to read 5, iclass 33, count 0 2006.173.21:11:19.90#ibcon#read 5, iclass 33, count 0 2006.173.21:11:19.90#ibcon#about to read 6, iclass 33, count 0 2006.173.21:11:19.90#ibcon#read 6, iclass 33, count 0 2006.173.21:11:19.90#ibcon#end of sib2, iclass 33, count 0 2006.173.21:11:19.90#ibcon#*mode == 0, iclass 33, count 0 2006.173.21:11:19.90#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.21:11:19.90#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.21:11:19.90#ibcon#*before write, iclass 33, count 0 2006.173.21:11:19.90#ibcon#enter sib2, iclass 33, count 0 2006.173.21:11:19.90#ibcon#flushed, iclass 33, count 0 2006.173.21:11:19.90#ibcon#about to write, iclass 33, count 0 2006.173.21:11:19.90#ibcon#wrote, iclass 33, count 0 2006.173.21:11:19.90#ibcon#about to read 3, iclass 33, count 0 2006.173.21:11:19.94#ibcon#read 3, iclass 33, count 0 2006.173.21:11:19.94#ibcon#about to read 4, iclass 33, count 0 2006.173.21:11:19.94#ibcon#read 4, iclass 33, count 0 2006.173.21:11:19.94#ibcon#about to read 5, iclass 33, count 0 2006.173.21:11:19.94#ibcon#read 5, iclass 33, count 0 2006.173.21:11:19.94#ibcon#about to read 6, iclass 33, count 0 2006.173.21:11:19.94#ibcon#read 6, iclass 33, count 0 2006.173.21:11:19.94#ibcon#end of sib2, iclass 33, count 0 2006.173.21:11:19.94#ibcon#*after write, iclass 33, count 0 2006.173.21:11:19.94#ibcon#*before return 0, iclass 33, count 0 2006.173.21:11:19.94#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.21:11:19.94#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.21:11:19.94#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.21:11:19.94#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.21:11:19.94$vck44/vb=7,4 2006.173.21:11:19.94#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.21:11:19.94#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.21:11:19.94#ibcon#ireg 11 cls_cnt 2 2006.173.21:11:19.94#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.21:11:20.00#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.21:11:20.00#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.21:11:20.00#ibcon#enter wrdev, iclass 35, count 2 2006.173.21:11:20.00#ibcon#first serial, iclass 35, count 2 2006.173.21:11:20.00#ibcon#enter sib2, iclass 35, count 2 2006.173.21:11:20.00#ibcon#flushed, iclass 35, count 2 2006.173.21:11:20.00#ibcon#about to write, iclass 35, count 2 2006.173.21:11:20.00#ibcon#wrote, iclass 35, count 2 2006.173.21:11:20.00#ibcon#about to read 3, iclass 35, count 2 2006.173.21:11:20.02#ibcon#read 3, iclass 35, count 2 2006.173.21:11:20.02#ibcon#about to read 4, iclass 35, count 2 2006.173.21:11:20.02#ibcon#read 4, iclass 35, count 2 2006.173.21:11:20.02#ibcon#about to read 5, iclass 35, count 2 2006.173.21:11:20.02#ibcon#read 5, iclass 35, count 2 2006.173.21:11:20.02#ibcon#about to read 6, iclass 35, count 2 2006.173.21:11:20.02#ibcon#read 6, iclass 35, count 2 2006.173.21:11:20.02#ibcon#end of sib2, iclass 35, count 2 2006.173.21:11:20.02#ibcon#*mode == 0, iclass 35, count 2 2006.173.21:11:20.02#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.21:11:20.02#ibcon#[27=AT07-04\r\n] 2006.173.21:11:20.02#ibcon#*before write, iclass 35, count 2 2006.173.21:11:20.02#ibcon#enter sib2, iclass 35, count 2 2006.173.21:11:20.02#ibcon#flushed, iclass 35, count 2 2006.173.21:11:20.02#ibcon#about to write, iclass 35, count 2 2006.173.21:11:20.02#ibcon#wrote, iclass 35, count 2 2006.173.21:11:20.02#ibcon#about to read 3, iclass 35, count 2 2006.173.21:11:20.05#ibcon#read 3, iclass 35, count 2 2006.173.21:11:20.05#ibcon#about to read 4, iclass 35, count 2 2006.173.21:11:20.05#ibcon#read 4, iclass 35, count 2 2006.173.21:11:20.05#ibcon#about to read 5, iclass 35, count 2 2006.173.21:11:20.05#ibcon#read 5, iclass 35, count 2 2006.173.21:11:20.05#ibcon#about to read 6, iclass 35, count 2 2006.173.21:11:20.05#ibcon#read 6, iclass 35, count 2 2006.173.21:11:20.05#ibcon#end of sib2, iclass 35, count 2 2006.173.21:11:20.05#ibcon#*after write, iclass 35, count 2 2006.173.21:11:20.05#ibcon#*before return 0, iclass 35, count 2 2006.173.21:11:20.05#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.21:11:20.05#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.21:11:20.05#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.21:11:20.05#ibcon#ireg 7 cls_cnt 0 2006.173.21:11:20.05#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.21:11:20.17#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.21:11:20.17#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.21:11:20.17#ibcon#enter wrdev, iclass 35, count 0 2006.173.21:11:20.17#ibcon#first serial, iclass 35, count 0 2006.173.21:11:20.17#ibcon#enter sib2, iclass 35, count 0 2006.173.21:11:20.17#ibcon#flushed, iclass 35, count 0 2006.173.21:11:20.17#ibcon#about to write, iclass 35, count 0 2006.173.21:11:20.17#ibcon#wrote, iclass 35, count 0 2006.173.21:11:20.17#ibcon#about to read 3, iclass 35, count 0 2006.173.21:11:20.19#ibcon#read 3, iclass 35, count 0 2006.173.21:11:20.19#ibcon#about to read 4, iclass 35, count 0 2006.173.21:11:20.19#ibcon#read 4, iclass 35, count 0 2006.173.21:11:20.19#ibcon#about to read 5, iclass 35, count 0 2006.173.21:11:20.19#ibcon#read 5, iclass 35, count 0 2006.173.21:11:20.19#ibcon#about to read 6, iclass 35, count 0 2006.173.21:11:20.19#ibcon#read 6, iclass 35, count 0 2006.173.21:11:20.19#ibcon#end of sib2, iclass 35, count 0 2006.173.21:11:20.19#ibcon#*mode == 0, iclass 35, count 0 2006.173.21:11:20.19#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.21:11:20.19#ibcon#[27=USB\r\n] 2006.173.21:11:20.19#ibcon#*before write, iclass 35, count 0 2006.173.21:11:20.19#ibcon#enter sib2, iclass 35, count 0 2006.173.21:11:20.19#ibcon#flushed, iclass 35, count 0 2006.173.21:11:20.19#ibcon#about to write, iclass 35, count 0 2006.173.21:11:20.19#ibcon#wrote, iclass 35, count 0 2006.173.21:11:20.19#ibcon#about to read 3, iclass 35, count 0 2006.173.21:11:20.22#ibcon#read 3, iclass 35, count 0 2006.173.21:11:20.22#ibcon#about to read 4, iclass 35, count 0 2006.173.21:11:20.22#ibcon#read 4, iclass 35, count 0 2006.173.21:11:20.22#ibcon#about to read 5, iclass 35, count 0 2006.173.21:11:20.22#ibcon#read 5, iclass 35, count 0 2006.173.21:11:20.22#ibcon#about to read 6, iclass 35, count 0 2006.173.21:11:20.22#ibcon#read 6, iclass 35, count 0 2006.173.21:11:20.22#ibcon#end of sib2, iclass 35, count 0 2006.173.21:11:20.22#ibcon#*after write, iclass 35, count 0 2006.173.21:11:20.22#ibcon#*before return 0, iclass 35, count 0 2006.173.21:11:20.22#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.21:11:20.22#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.21:11:20.22#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.21:11:20.22#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.21:11:20.22$vck44/vblo=8,744.99 2006.173.21:11:20.22#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.21:11:20.22#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.21:11:20.22#ibcon#ireg 17 cls_cnt 0 2006.173.21:11:20.22#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.21:11:20.22#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.21:11:20.22#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.21:11:20.22#ibcon#enter wrdev, iclass 37, count 0 2006.173.21:11:20.22#ibcon#first serial, iclass 37, count 0 2006.173.21:11:20.22#ibcon#enter sib2, iclass 37, count 0 2006.173.21:11:20.22#ibcon#flushed, iclass 37, count 0 2006.173.21:11:20.22#ibcon#about to write, iclass 37, count 0 2006.173.21:11:20.22#ibcon#wrote, iclass 37, count 0 2006.173.21:11:20.22#ibcon#about to read 3, iclass 37, count 0 2006.173.21:11:20.24#ibcon#read 3, iclass 37, count 0 2006.173.21:11:20.24#ibcon#about to read 4, iclass 37, count 0 2006.173.21:11:20.24#ibcon#read 4, iclass 37, count 0 2006.173.21:11:20.24#ibcon#about to read 5, iclass 37, count 0 2006.173.21:11:20.24#ibcon#read 5, iclass 37, count 0 2006.173.21:11:20.24#ibcon#about to read 6, iclass 37, count 0 2006.173.21:11:20.24#ibcon#read 6, iclass 37, count 0 2006.173.21:11:20.24#ibcon#end of sib2, iclass 37, count 0 2006.173.21:11:20.24#ibcon#*mode == 0, iclass 37, count 0 2006.173.21:11:20.24#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.21:11:20.24#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.21:11:20.24#ibcon#*before write, iclass 37, count 0 2006.173.21:11:20.24#ibcon#enter sib2, iclass 37, count 0 2006.173.21:11:20.24#ibcon#flushed, iclass 37, count 0 2006.173.21:11:20.24#ibcon#about to write, iclass 37, count 0 2006.173.21:11:20.24#ibcon#wrote, iclass 37, count 0 2006.173.21:11:20.24#ibcon#about to read 3, iclass 37, count 0 2006.173.21:11:20.28#ibcon#read 3, iclass 37, count 0 2006.173.21:11:20.28#ibcon#about to read 4, iclass 37, count 0 2006.173.21:11:20.28#ibcon#read 4, iclass 37, count 0 2006.173.21:11:20.28#ibcon#about to read 5, iclass 37, count 0 2006.173.21:11:20.28#ibcon#read 5, iclass 37, count 0 2006.173.21:11:20.28#ibcon#about to read 6, iclass 37, count 0 2006.173.21:11:20.28#ibcon#read 6, iclass 37, count 0 2006.173.21:11:20.28#ibcon#end of sib2, iclass 37, count 0 2006.173.21:11:20.28#ibcon#*after write, iclass 37, count 0 2006.173.21:11:20.28#ibcon#*before return 0, iclass 37, count 0 2006.173.21:11:20.28#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.21:11:20.28#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.21:11:20.28#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.21:11:20.28#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.21:11:20.28$vck44/vb=8,4 2006.173.21:11:20.28#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.21:11:20.28#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.21:11:20.28#ibcon#ireg 11 cls_cnt 2 2006.173.21:11:20.28#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.21:11:20.34#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.21:11:20.34#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.21:11:20.34#ibcon#enter wrdev, iclass 39, count 2 2006.173.21:11:20.34#ibcon#first serial, iclass 39, count 2 2006.173.21:11:20.34#ibcon#enter sib2, iclass 39, count 2 2006.173.21:11:20.34#ibcon#flushed, iclass 39, count 2 2006.173.21:11:20.34#ibcon#about to write, iclass 39, count 2 2006.173.21:11:20.34#ibcon#wrote, iclass 39, count 2 2006.173.21:11:20.34#ibcon#about to read 3, iclass 39, count 2 2006.173.21:11:20.36#ibcon#read 3, iclass 39, count 2 2006.173.21:11:20.36#ibcon#about to read 4, iclass 39, count 2 2006.173.21:11:20.36#ibcon#read 4, iclass 39, count 2 2006.173.21:11:20.36#ibcon#about to read 5, iclass 39, count 2 2006.173.21:11:20.36#ibcon#read 5, iclass 39, count 2 2006.173.21:11:20.36#ibcon#about to read 6, iclass 39, count 2 2006.173.21:11:20.36#ibcon#read 6, iclass 39, count 2 2006.173.21:11:20.36#ibcon#end of sib2, iclass 39, count 2 2006.173.21:11:20.36#ibcon#*mode == 0, iclass 39, count 2 2006.173.21:11:20.36#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.21:11:20.36#ibcon#[27=AT08-04\r\n] 2006.173.21:11:20.36#ibcon#*before write, iclass 39, count 2 2006.173.21:11:20.36#ibcon#enter sib2, iclass 39, count 2 2006.173.21:11:20.36#ibcon#flushed, iclass 39, count 2 2006.173.21:11:20.36#ibcon#about to write, iclass 39, count 2 2006.173.21:11:20.36#ibcon#wrote, iclass 39, count 2 2006.173.21:11:20.36#ibcon#about to read 3, iclass 39, count 2 2006.173.21:11:20.39#ibcon#read 3, iclass 39, count 2 2006.173.21:11:20.39#ibcon#about to read 4, iclass 39, count 2 2006.173.21:11:20.39#ibcon#read 4, iclass 39, count 2 2006.173.21:11:20.39#ibcon#about to read 5, iclass 39, count 2 2006.173.21:11:20.39#ibcon#read 5, iclass 39, count 2 2006.173.21:11:20.39#ibcon#about to read 6, iclass 39, count 2 2006.173.21:11:20.39#ibcon#read 6, iclass 39, count 2 2006.173.21:11:20.39#ibcon#end of sib2, iclass 39, count 2 2006.173.21:11:20.39#ibcon#*after write, iclass 39, count 2 2006.173.21:11:20.39#ibcon#*before return 0, iclass 39, count 2 2006.173.21:11:20.39#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.21:11:20.39#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.21:11:20.39#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.21:11:20.39#ibcon#ireg 7 cls_cnt 0 2006.173.21:11:20.39#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.21:11:20.51#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.21:11:20.51#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.21:11:20.51#ibcon#enter wrdev, iclass 39, count 0 2006.173.21:11:20.51#ibcon#first serial, iclass 39, count 0 2006.173.21:11:20.51#ibcon#enter sib2, iclass 39, count 0 2006.173.21:11:20.51#ibcon#flushed, iclass 39, count 0 2006.173.21:11:20.51#ibcon#about to write, iclass 39, count 0 2006.173.21:11:20.51#ibcon#wrote, iclass 39, count 0 2006.173.21:11:20.51#ibcon#about to read 3, iclass 39, count 0 2006.173.21:11:20.53#ibcon#read 3, iclass 39, count 0 2006.173.21:11:20.53#ibcon#about to read 4, iclass 39, count 0 2006.173.21:11:20.53#ibcon#read 4, iclass 39, count 0 2006.173.21:11:20.53#ibcon#about to read 5, iclass 39, count 0 2006.173.21:11:20.53#ibcon#read 5, iclass 39, count 0 2006.173.21:11:20.53#ibcon#about to read 6, iclass 39, count 0 2006.173.21:11:20.53#ibcon#read 6, iclass 39, count 0 2006.173.21:11:20.53#ibcon#end of sib2, iclass 39, count 0 2006.173.21:11:20.53#ibcon#*mode == 0, iclass 39, count 0 2006.173.21:11:20.53#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.21:11:20.53#ibcon#[27=USB\r\n] 2006.173.21:11:20.53#ibcon#*before write, iclass 39, count 0 2006.173.21:11:20.53#ibcon#enter sib2, iclass 39, count 0 2006.173.21:11:20.53#ibcon#flushed, iclass 39, count 0 2006.173.21:11:20.53#ibcon#about to write, iclass 39, count 0 2006.173.21:11:20.53#ibcon#wrote, iclass 39, count 0 2006.173.21:11:20.53#ibcon#about to read 3, iclass 39, count 0 2006.173.21:11:20.56#ibcon#read 3, iclass 39, count 0 2006.173.21:11:20.56#ibcon#about to read 4, iclass 39, count 0 2006.173.21:11:20.56#ibcon#read 4, iclass 39, count 0 2006.173.21:11:20.56#ibcon#about to read 5, iclass 39, count 0 2006.173.21:11:20.56#ibcon#read 5, iclass 39, count 0 2006.173.21:11:20.56#ibcon#about to read 6, iclass 39, count 0 2006.173.21:11:20.56#ibcon#read 6, iclass 39, count 0 2006.173.21:11:20.56#ibcon#end of sib2, iclass 39, count 0 2006.173.21:11:20.56#ibcon#*after write, iclass 39, count 0 2006.173.21:11:20.56#ibcon#*before return 0, iclass 39, count 0 2006.173.21:11:20.56#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.21:11:20.56#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.21:11:20.56#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.21:11:20.56#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.21:11:20.56$vck44/vabw=wide 2006.173.21:11:20.56#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.21:11:20.56#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.21:11:20.56#ibcon#ireg 8 cls_cnt 0 2006.173.21:11:20.56#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.21:11:20.56#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.21:11:20.56#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.21:11:20.56#ibcon#enter wrdev, iclass 3, count 0 2006.173.21:11:20.56#ibcon#first serial, iclass 3, count 0 2006.173.21:11:20.56#ibcon#enter sib2, iclass 3, count 0 2006.173.21:11:20.56#ibcon#flushed, iclass 3, count 0 2006.173.21:11:20.56#ibcon#about to write, iclass 3, count 0 2006.173.21:11:20.56#ibcon#wrote, iclass 3, count 0 2006.173.21:11:20.56#ibcon#about to read 3, iclass 3, count 0 2006.173.21:11:20.58#ibcon#read 3, iclass 3, count 0 2006.173.21:11:20.58#ibcon#about to read 4, iclass 3, count 0 2006.173.21:11:20.58#ibcon#read 4, iclass 3, count 0 2006.173.21:11:20.58#ibcon#about to read 5, iclass 3, count 0 2006.173.21:11:20.58#ibcon#read 5, iclass 3, count 0 2006.173.21:11:20.58#ibcon#about to read 6, iclass 3, count 0 2006.173.21:11:20.58#ibcon#read 6, iclass 3, count 0 2006.173.21:11:20.58#ibcon#end of sib2, iclass 3, count 0 2006.173.21:11:20.58#ibcon#*mode == 0, iclass 3, count 0 2006.173.21:11:20.58#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.21:11:20.58#ibcon#[25=BW32\r\n] 2006.173.21:11:20.58#ibcon#*before write, iclass 3, count 0 2006.173.21:11:20.58#ibcon#enter sib2, iclass 3, count 0 2006.173.21:11:20.58#ibcon#flushed, iclass 3, count 0 2006.173.21:11:20.58#ibcon#about to write, iclass 3, count 0 2006.173.21:11:20.58#ibcon#wrote, iclass 3, count 0 2006.173.21:11:20.58#ibcon#about to read 3, iclass 3, count 0 2006.173.21:11:20.61#ibcon#read 3, iclass 3, count 0 2006.173.21:11:20.61#ibcon#about to read 4, iclass 3, count 0 2006.173.21:11:20.61#ibcon#read 4, iclass 3, count 0 2006.173.21:11:20.61#ibcon#about to read 5, iclass 3, count 0 2006.173.21:11:20.61#ibcon#read 5, iclass 3, count 0 2006.173.21:11:20.61#ibcon#about to read 6, iclass 3, count 0 2006.173.21:11:20.61#ibcon#read 6, iclass 3, count 0 2006.173.21:11:20.61#ibcon#end of sib2, iclass 3, count 0 2006.173.21:11:20.61#ibcon#*after write, iclass 3, count 0 2006.173.21:11:20.61#ibcon#*before return 0, iclass 3, count 0 2006.173.21:11:20.61#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.21:11:20.61#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.21:11:20.61#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.21:11:20.61#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.21:11:20.61$vck44/vbbw=wide 2006.173.21:11:20.61#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.21:11:20.61#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.21:11:20.61#ibcon#ireg 8 cls_cnt 0 2006.173.21:11:20.61#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.21:11:20.68#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.21:11:20.68#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.21:11:20.68#ibcon#enter wrdev, iclass 5, count 0 2006.173.21:11:20.68#ibcon#first serial, iclass 5, count 0 2006.173.21:11:20.68#ibcon#enter sib2, iclass 5, count 0 2006.173.21:11:20.68#ibcon#flushed, iclass 5, count 0 2006.173.21:11:20.68#ibcon#about to write, iclass 5, count 0 2006.173.21:11:20.68#ibcon#wrote, iclass 5, count 0 2006.173.21:11:20.68#ibcon#about to read 3, iclass 5, count 0 2006.173.21:11:20.70#ibcon#read 3, iclass 5, count 0 2006.173.21:11:20.70#ibcon#about to read 4, iclass 5, count 0 2006.173.21:11:20.70#ibcon#read 4, iclass 5, count 0 2006.173.21:11:20.70#ibcon#about to read 5, iclass 5, count 0 2006.173.21:11:20.70#ibcon#read 5, iclass 5, count 0 2006.173.21:11:20.70#ibcon#about to read 6, iclass 5, count 0 2006.173.21:11:20.70#ibcon#read 6, iclass 5, count 0 2006.173.21:11:20.70#ibcon#end of sib2, iclass 5, count 0 2006.173.21:11:20.70#ibcon#*mode == 0, iclass 5, count 0 2006.173.21:11:20.70#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.21:11:20.70#ibcon#[27=BW32\r\n] 2006.173.21:11:20.70#ibcon#*before write, iclass 5, count 0 2006.173.21:11:20.70#ibcon#enter sib2, iclass 5, count 0 2006.173.21:11:20.70#ibcon#flushed, iclass 5, count 0 2006.173.21:11:20.70#ibcon#about to write, iclass 5, count 0 2006.173.21:11:20.70#ibcon#wrote, iclass 5, count 0 2006.173.21:11:20.70#ibcon#about to read 3, iclass 5, count 0 2006.173.21:11:20.73#ibcon#read 3, iclass 5, count 0 2006.173.21:11:20.73#ibcon#about to read 4, iclass 5, count 0 2006.173.21:11:20.73#ibcon#read 4, iclass 5, count 0 2006.173.21:11:20.73#ibcon#about to read 5, iclass 5, count 0 2006.173.21:11:20.73#ibcon#read 5, iclass 5, count 0 2006.173.21:11:20.73#ibcon#about to read 6, iclass 5, count 0 2006.173.21:11:20.73#ibcon#read 6, iclass 5, count 0 2006.173.21:11:20.73#ibcon#end of sib2, iclass 5, count 0 2006.173.21:11:20.73#ibcon#*after write, iclass 5, count 0 2006.173.21:11:20.73#ibcon#*before return 0, iclass 5, count 0 2006.173.21:11:20.73#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.21:11:20.73#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.21:11:20.73#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.21:11:20.73#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.21:11:20.73$setupk4/ifdk4 2006.173.21:11:20.73$ifdk4/lo= 2006.173.21:11:20.73$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.21:11:20.74$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.21:11:20.74$ifdk4/patch= 2006.173.21:11:20.74$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.21:11:20.74$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.21:11:20.74$setupk4/!*+20s 2006.173.21:11:26.13#trakl#Source acquired 2006.173.21:11:28.13#flagr#flagr/antenna,acquired 2006.173.21:11:29.98#abcon#<5=/11 0.9 1.8 21.041001003.2\r\n> 2006.173.21:11:30.00#abcon#{5=INTERFACE CLEAR} 2006.173.21:11:30.06#abcon#[5=S1D000X0/0*\r\n] 2006.173.21:11:35.26$setupk4/"tpicd 2006.173.21:11:35.26$setupk4/echo=off 2006.173.21:11:35.26$setupk4/xlog=off 2006.173.21:11:35.26:!2006.173.21:13:21 2006.173.21:13:21.00:preob 2006.173.21:13:21.14/onsource/TRACKING 2006.173.21:13:21.14:!2006.173.21:13:31 2006.173.21:13:31.00:"tape 2006.173.21:13:31.00:"st=record 2006.173.21:13:31.00:data_valid=on 2006.173.21:13:31.00:midob 2006.173.21:13:31.14/onsource/TRACKING 2006.173.21:13:31.14/wx/21.07,1003.3,100 2006.173.21:13:31.36/cable/+6.5160E-03 2006.173.21:13:32.45/va/01,07,usb,yes,35,37 2006.173.21:13:32.45/va/02,06,usb,yes,35,36 2006.173.21:13:32.45/va/03,05,usb,yes,44,46 2006.173.21:13:32.45/va/04,06,usb,yes,35,37 2006.173.21:13:32.45/va/05,04,usb,yes,28,28 2006.173.21:13:32.45/va/06,03,usb,yes,39,39 2006.173.21:13:32.45/va/07,04,usb,yes,31,33 2006.173.21:13:32.45/va/08,04,usb,yes,27,32 2006.173.21:13:32.68/valo/01,524.99,yes,locked 2006.173.21:13:32.68/valo/02,534.99,yes,locked 2006.173.21:13:32.68/valo/03,564.99,yes,locked 2006.173.21:13:32.68/valo/04,624.99,yes,locked 2006.173.21:13:32.68/valo/05,734.99,yes,locked 2006.173.21:13:32.68/valo/06,814.99,yes,locked 2006.173.21:13:32.68/valo/07,864.99,yes,locked 2006.173.21:13:32.68/valo/08,884.99,yes,locked 2006.173.21:13:33.77/vb/01,04,usb,yes,29,27 2006.173.21:13:33.77/vb/02,04,usb,yes,32,31 2006.173.21:13:33.77/vb/03,04,usb,yes,29,31 2006.173.21:13:33.77/vb/04,04,usb,yes,33,32 2006.173.21:13:33.77/vb/05,04,usb,yes,25,28 2006.173.21:13:33.77/vb/06,04,usb,yes,30,26 2006.173.21:13:33.77/vb/07,04,usb,yes,30,29 2006.173.21:13:33.77/vb/08,04,usb,yes,27,31 2006.173.21:13:34.00/vblo/01,629.99,yes,locked 2006.173.21:13:34.00/vblo/02,634.99,yes,locked 2006.173.21:13:34.00/vblo/03,649.99,yes,locked 2006.173.21:13:34.00/vblo/04,679.99,yes,locked 2006.173.21:13:34.00/vblo/05,709.99,yes,locked 2006.173.21:13:34.00/vblo/06,719.99,yes,locked 2006.173.21:13:34.00/vblo/07,734.99,yes,locked 2006.173.21:13:34.00/vblo/08,744.99,yes,locked 2006.173.21:13:34.15/vabw/8 2006.173.21:13:34.30/vbbw/8 2006.173.21:13:34.39/xfe/off,on,15.2 2006.173.21:13:34.77/ifatt/23,28,28,28 2006.173.21:13:35.07/fmout-gps/S +3.86E-07 2006.173.21:13:35.12:!2006.173.21:14:11 2006.173.21:14:11.01:data_valid=off 2006.173.21:14:11.01:"et 2006.173.21:14:11.01:!+3s 2006.173.21:14:14.02:"tape 2006.173.21:14:14.02:postob 2006.173.21:14:14.21/cable/+6.5170E-03 2006.173.21:14:14.21/wx/21.09,1003.3,100 2006.173.21:14:14.27/fmout-gps/S +3.86E-07 2006.173.21:14:14.27:scan_name=173-2114,jd0606,120 2006.173.21:14:14.27:source=2201+315,220314.98,314538.3,2000.0,cw 2006.173.21:14:16.14#flagr#flagr/antenna,new-source 2006.173.21:14:16.14:checkk5 2006.173.21:14:16.50/chk_autoobs//k5ts1/ autoobs is running! 2006.173.21:14:16.89/chk_autoobs//k5ts2/ autoobs is running! 2006.173.21:14:17.30/chk_autoobs//k5ts3/ autoobs is running! 2006.173.21:14:17.70/chk_autoobs//k5ts4/ autoobs is running! 2006.173.21:14:18.09/chk_obsdata//k5ts1/T1732113??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.21:14:18.50/chk_obsdata//k5ts2/T1732113??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.21:14:18.90/chk_obsdata//k5ts3/T1732113??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.21:14:19.31/chk_obsdata//k5ts4/T1732113??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.21:14:20.03/k5log//k5ts1_log_newline 2006.173.21:14:20.75/k5log//k5ts2_log_newline 2006.173.21:14:21.45/k5log//k5ts3_log_newline 2006.173.21:14:22.15/k5log//k5ts4_log_newline 2006.173.21:14:22.18/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.21:14:22.18:setupk4=1 2006.173.21:14:22.18$setupk4/echo=on 2006.173.21:14:22.18$setupk4/pcalon 2006.173.21:14:22.18$pcalon/"no phase cal control is implemented here 2006.173.21:14:22.18$setupk4/"tpicd=stop 2006.173.21:14:22.18$setupk4/"rec=synch_on 2006.173.21:14:22.18$setupk4/"rec_mode=128 2006.173.21:14:22.18$setupk4/!* 2006.173.21:14:22.18$setupk4/recpk4 2006.173.21:14:22.18$recpk4/recpatch= 2006.173.21:14:22.18$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.21:14:22.18$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.21:14:22.18$setupk4/vck44 2006.173.21:14:22.18$vck44/valo=1,524.99 2006.173.21:14:22.18#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.21:14:22.18#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.21:14:22.18#ibcon#ireg 17 cls_cnt 0 2006.173.21:14:22.18#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.21:14:22.18#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.21:14:22.18#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.21:14:22.18#ibcon#enter wrdev, iclass 6, count 0 2006.173.21:14:22.18#ibcon#first serial, iclass 6, count 0 2006.173.21:14:22.18#ibcon#enter sib2, iclass 6, count 0 2006.173.21:14:22.18#ibcon#flushed, iclass 6, count 0 2006.173.21:14:22.18#ibcon#about to write, iclass 6, count 0 2006.173.21:14:22.18#ibcon#wrote, iclass 6, count 0 2006.173.21:14:22.18#ibcon#about to read 3, iclass 6, count 0 2006.173.21:14:22.19#ibcon#read 3, iclass 6, count 0 2006.173.21:14:22.19#ibcon#about to read 4, iclass 6, count 0 2006.173.21:14:22.19#ibcon#read 4, iclass 6, count 0 2006.173.21:14:22.19#ibcon#about to read 5, iclass 6, count 0 2006.173.21:14:22.19#ibcon#read 5, iclass 6, count 0 2006.173.21:14:22.19#ibcon#about to read 6, iclass 6, count 0 2006.173.21:14:22.19#ibcon#read 6, iclass 6, count 0 2006.173.21:14:22.19#ibcon#end of sib2, iclass 6, count 0 2006.173.21:14:22.19#ibcon#*mode == 0, iclass 6, count 0 2006.173.21:14:22.19#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.21:14:22.19#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.21:14:22.19#ibcon#*before write, iclass 6, count 0 2006.173.21:14:22.19#ibcon#enter sib2, iclass 6, count 0 2006.173.21:14:22.19#ibcon#flushed, iclass 6, count 0 2006.173.21:14:22.19#ibcon#about to write, iclass 6, count 0 2006.173.21:14:22.19#ibcon#wrote, iclass 6, count 0 2006.173.21:14:22.19#ibcon#about to read 3, iclass 6, count 0 2006.173.21:14:22.24#ibcon#read 3, iclass 6, count 0 2006.173.21:14:22.24#ibcon#about to read 4, iclass 6, count 0 2006.173.21:14:22.24#ibcon#read 4, iclass 6, count 0 2006.173.21:14:22.24#ibcon#about to read 5, iclass 6, count 0 2006.173.21:14:22.24#ibcon#read 5, iclass 6, count 0 2006.173.21:14:22.24#ibcon#about to read 6, iclass 6, count 0 2006.173.21:14:22.24#ibcon#read 6, iclass 6, count 0 2006.173.21:14:22.24#ibcon#end of sib2, iclass 6, count 0 2006.173.21:14:22.24#ibcon#*after write, iclass 6, count 0 2006.173.21:14:22.24#ibcon#*before return 0, iclass 6, count 0 2006.173.21:14:22.24#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.21:14:22.24#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.21:14:22.24#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.21:14:22.24#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.21:14:22.24$vck44/va=1,7 2006.173.21:14:22.24#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.21:14:22.24#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.21:14:22.24#ibcon#ireg 11 cls_cnt 2 2006.173.21:14:22.24#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.21:14:22.24#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.21:14:22.24#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.21:14:22.24#ibcon#enter wrdev, iclass 10, count 2 2006.173.21:14:22.24#ibcon#first serial, iclass 10, count 2 2006.173.21:14:22.24#ibcon#enter sib2, iclass 10, count 2 2006.173.21:14:22.24#ibcon#flushed, iclass 10, count 2 2006.173.21:14:22.24#ibcon#about to write, iclass 10, count 2 2006.173.21:14:22.24#ibcon#wrote, iclass 10, count 2 2006.173.21:14:22.24#ibcon#about to read 3, iclass 10, count 2 2006.173.21:14:22.26#ibcon#read 3, iclass 10, count 2 2006.173.21:14:22.26#ibcon#about to read 4, iclass 10, count 2 2006.173.21:14:22.26#ibcon#read 4, iclass 10, count 2 2006.173.21:14:22.26#ibcon#about to read 5, iclass 10, count 2 2006.173.21:14:22.26#ibcon#read 5, iclass 10, count 2 2006.173.21:14:22.26#ibcon#about to read 6, iclass 10, count 2 2006.173.21:14:22.26#ibcon#read 6, iclass 10, count 2 2006.173.21:14:22.26#ibcon#end of sib2, iclass 10, count 2 2006.173.21:14:22.26#ibcon#*mode == 0, iclass 10, count 2 2006.173.21:14:22.26#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.21:14:22.26#ibcon#[25=AT01-07\r\n] 2006.173.21:14:22.26#ibcon#*before write, iclass 10, count 2 2006.173.21:14:22.26#ibcon#enter sib2, iclass 10, count 2 2006.173.21:14:22.26#ibcon#flushed, iclass 10, count 2 2006.173.21:14:22.26#ibcon#about to write, iclass 10, count 2 2006.173.21:14:22.26#ibcon#wrote, iclass 10, count 2 2006.173.21:14:22.26#ibcon#about to read 3, iclass 10, count 2 2006.173.21:14:22.29#ibcon#read 3, iclass 10, count 2 2006.173.21:14:22.29#ibcon#about to read 4, iclass 10, count 2 2006.173.21:14:22.29#ibcon#read 4, iclass 10, count 2 2006.173.21:14:22.29#ibcon#about to read 5, iclass 10, count 2 2006.173.21:14:22.29#ibcon#read 5, iclass 10, count 2 2006.173.21:14:22.29#ibcon#about to read 6, iclass 10, count 2 2006.173.21:14:22.29#ibcon#read 6, iclass 10, count 2 2006.173.21:14:22.29#ibcon#end of sib2, iclass 10, count 2 2006.173.21:14:22.29#ibcon#*after write, iclass 10, count 2 2006.173.21:14:22.29#ibcon#*before return 0, iclass 10, count 2 2006.173.21:14:22.29#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.21:14:22.29#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.21:14:22.29#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.21:14:22.29#ibcon#ireg 7 cls_cnt 0 2006.173.21:14:22.29#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.21:14:22.41#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.21:14:22.41#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.21:14:22.41#ibcon#enter wrdev, iclass 10, count 0 2006.173.21:14:22.41#ibcon#first serial, iclass 10, count 0 2006.173.21:14:22.41#ibcon#enter sib2, iclass 10, count 0 2006.173.21:14:22.41#ibcon#flushed, iclass 10, count 0 2006.173.21:14:22.41#ibcon#about to write, iclass 10, count 0 2006.173.21:14:22.41#ibcon#wrote, iclass 10, count 0 2006.173.21:14:22.41#ibcon#about to read 3, iclass 10, count 0 2006.173.21:14:22.43#ibcon#read 3, iclass 10, count 0 2006.173.21:14:22.43#ibcon#about to read 4, iclass 10, count 0 2006.173.21:14:22.43#ibcon#read 4, iclass 10, count 0 2006.173.21:14:22.43#ibcon#about to read 5, iclass 10, count 0 2006.173.21:14:22.43#ibcon#read 5, iclass 10, count 0 2006.173.21:14:22.43#ibcon#about to read 6, iclass 10, count 0 2006.173.21:14:22.43#ibcon#read 6, iclass 10, count 0 2006.173.21:14:22.43#ibcon#end of sib2, iclass 10, count 0 2006.173.21:14:22.43#ibcon#*mode == 0, iclass 10, count 0 2006.173.21:14:22.43#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.21:14:22.43#ibcon#[25=USB\r\n] 2006.173.21:14:22.43#ibcon#*before write, iclass 10, count 0 2006.173.21:14:22.43#ibcon#enter sib2, iclass 10, count 0 2006.173.21:14:22.43#ibcon#flushed, iclass 10, count 0 2006.173.21:14:22.43#ibcon#about to write, iclass 10, count 0 2006.173.21:14:22.43#ibcon#wrote, iclass 10, count 0 2006.173.21:14:22.43#ibcon#about to read 3, iclass 10, count 0 2006.173.21:14:22.46#ibcon#read 3, iclass 10, count 0 2006.173.21:14:22.46#ibcon#about to read 4, iclass 10, count 0 2006.173.21:14:22.46#ibcon#read 4, iclass 10, count 0 2006.173.21:14:22.46#ibcon#about to read 5, iclass 10, count 0 2006.173.21:14:22.46#ibcon#read 5, iclass 10, count 0 2006.173.21:14:22.46#ibcon#about to read 6, iclass 10, count 0 2006.173.21:14:22.46#ibcon#read 6, iclass 10, count 0 2006.173.21:14:22.46#ibcon#end of sib2, iclass 10, count 0 2006.173.21:14:22.46#ibcon#*after write, iclass 10, count 0 2006.173.21:14:22.46#ibcon#*before return 0, iclass 10, count 0 2006.173.21:14:22.46#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.21:14:22.46#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.21:14:22.46#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.21:14:22.46#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.21:14:22.46$vck44/valo=2,534.99 2006.173.21:14:22.46#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.21:14:22.46#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.21:14:22.46#ibcon#ireg 17 cls_cnt 0 2006.173.21:14:22.46#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.21:14:22.46#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.21:14:22.46#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.21:14:22.46#ibcon#enter wrdev, iclass 12, count 0 2006.173.21:14:22.46#ibcon#first serial, iclass 12, count 0 2006.173.21:14:22.46#ibcon#enter sib2, iclass 12, count 0 2006.173.21:14:22.46#ibcon#flushed, iclass 12, count 0 2006.173.21:14:22.46#ibcon#about to write, iclass 12, count 0 2006.173.21:14:22.46#ibcon#wrote, iclass 12, count 0 2006.173.21:14:22.46#ibcon#about to read 3, iclass 12, count 0 2006.173.21:14:22.48#ibcon#read 3, iclass 12, count 0 2006.173.21:14:22.48#ibcon#about to read 4, iclass 12, count 0 2006.173.21:14:22.48#ibcon#read 4, iclass 12, count 0 2006.173.21:14:22.48#ibcon#about to read 5, iclass 12, count 0 2006.173.21:14:22.48#ibcon#read 5, iclass 12, count 0 2006.173.21:14:22.48#ibcon#about to read 6, iclass 12, count 0 2006.173.21:14:22.48#ibcon#read 6, iclass 12, count 0 2006.173.21:14:22.48#ibcon#end of sib2, iclass 12, count 0 2006.173.21:14:22.48#ibcon#*mode == 0, iclass 12, count 0 2006.173.21:14:22.48#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.21:14:22.48#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.21:14:22.48#ibcon#*before write, iclass 12, count 0 2006.173.21:14:22.48#ibcon#enter sib2, iclass 12, count 0 2006.173.21:14:22.48#ibcon#flushed, iclass 12, count 0 2006.173.21:14:22.48#ibcon#about to write, iclass 12, count 0 2006.173.21:14:22.48#ibcon#wrote, iclass 12, count 0 2006.173.21:14:22.48#ibcon#about to read 3, iclass 12, count 0 2006.173.21:14:22.52#ibcon#read 3, iclass 12, count 0 2006.173.21:14:22.52#ibcon#about to read 4, iclass 12, count 0 2006.173.21:14:22.52#ibcon#read 4, iclass 12, count 0 2006.173.21:14:22.52#ibcon#about to read 5, iclass 12, count 0 2006.173.21:14:22.52#ibcon#read 5, iclass 12, count 0 2006.173.21:14:22.52#ibcon#about to read 6, iclass 12, count 0 2006.173.21:14:22.52#ibcon#read 6, iclass 12, count 0 2006.173.21:14:22.52#ibcon#end of sib2, iclass 12, count 0 2006.173.21:14:22.52#ibcon#*after write, iclass 12, count 0 2006.173.21:14:22.52#ibcon#*before return 0, iclass 12, count 0 2006.173.21:14:22.52#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.21:14:22.52#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.21:14:22.52#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.21:14:22.52#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.21:14:22.52$vck44/va=2,6 2006.173.21:14:22.52#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.21:14:22.52#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.21:14:22.52#ibcon#ireg 11 cls_cnt 2 2006.173.21:14:22.52#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.21:14:22.58#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.21:14:22.58#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.21:14:22.58#ibcon#enter wrdev, iclass 14, count 2 2006.173.21:14:22.58#ibcon#first serial, iclass 14, count 2 2006.173.21:14:22.58#ibcon#enter sib2, iclass 14, count 2 2006.173.21:14:22.58#ibcon#flushed, iclass 14, count 2 2006.173.21:14:22.58#ibcon#about to write, iclass 14, count 2 2006.173.21:14:22.58#ibcon#wrote, iclass 14, count 2 2006.173.21:14:22.58#ibcon#about to read 3, iclass 14, count 2 2006.173.21:14:22.60#ibcon#read 3, iclass 14, count 2 2006.173.21:14:22.60#ibcon#about to read 4, iclass 14, count 2 2006.173.21:14:22.60#ibcon#read 4, iclass 14, count 2 2006.173.21:14:22.60#ibcon#about to read 5, iclass 14, count 2 2006.173.21:14:22.60#ibcon#read 5, iclass 14, count 2 2006.173.21:14:22.60#ibcon#about to read 6, iclass 14, count 2 2006.173.21:14:22.60#ibcon#read 6, iclass 14, count 2 2006.173.21:14:22.60#ibcon#end of sib2, iclass 14, count 2 2006.173.21:14:22.60#ibcon#*mode == 0, iclass 14, count 2 2006.173.21:14:22.60#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.21:14:22.60#ibcon#[25=AT02-06\r\n] 2006.173.21:14:22.60#ibcon#*before write, iclass 14, count 2 2006.173.21:14:22.60#ibcon#enter sib2, iclass 14, count 2 2006.173.21:14:22.60#ibcon#flushed, iclass 14, count 2 2006.173.21:14:22.60#ibcon#about to write, iclass 14, count 2 2006.173.21:14:22.60#ibcon#wrote, iclass 14, count 2 2006.173.21:14:22.60#ibcon#about to read 3, iclass 14, count 2 2006.173.21:14:22.63#ibcon#read 3, iclass 14, count 2 2006.173.21:14:22.63#ibcon#about to read 4, iclass 14, count 2 2006.173.21:14:22.63#ibcon#read 4, iclass 14, count 2 2006.173.21:14:22.63#ibcon#about to read 5, iclass 14, count 2 2006.173.21:14:22.63#ibcon#read 5, iclass 14, count 2 2006.173.21:14:22.63#ibcon#about to read 6, iclass 14, count 2 2006.173.21:14:22.63#ibcon#read 6, iclass 14, count 2 2006.173.21:14:22.63#ibcon#end of sib2, iclass 14, count 2 2006.173.21:14:22.63#ibcon#*after write, iclass 14, count 2 2006.173.21:14:22.63#ibcon#*before return 0, iclass 14, count 2 2006.173.21:14:22.63#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.21:14:22.63#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.21:14:22.63#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.21:14:22.63#ibcon#ireg 7 cls_cnt 0 2006.173.21:14:22.63#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.21:14:22.75#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.21:14:22.75#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.21:14:22.75#ibcon#enter wrdev, iclass 14, count 0 2006.173.21:14:22.75#ibcon#first serial, iclass 14, count 0 2006.173.21:14:22.75#ibcon#enter sib2, iclass 14, count 0 2006.173.21:14:22.75#ibcon#flushed, iclass 14, count 0 2006.173.21:14:22.75#ibcon#about to write, iclass 14, count 0 2006.173.21:14:22.75#ibcon#wrote, iclass 14, count 0 2006.173.21:14:22.75#ibcon#about to read 3, iclass 14, count 0 2006.173.21:14:22.77#ibcon#read 3, iclass 14, count 0 2006.173.21:14:22.77#ibcon#about to read 4, iclass 14, count 0 2006.173.21:14:22.77#ibcon#read 4, iclass 14, count 0 2006.173.21:14:22.77#ibcon#about to read 5, iclass 14, count 0 2006.173.21:14:22.77#ibcon#read 5, iclass 14, count 0 2006.173.21:14:22.77#ibcon#about to read 6, iclass 14, count 0 2006.173.21:14:22.77#ibcon#read 6, iclass 14, count 0 2006.173.21:14:22.77#ibcon#end of sib2, iclass 14, count 0 2006.173.21:14:22.77#ibcon#*mode == 0, iclass 14, count 0 2006.173.21:14:22.77#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.21:14:22.77#ibcon#[25=USB\r\n] 2006.173.21:14:22.77#ibcon#*before write, iclass 14, count 0 2006.173.21:14:22.77#ibcon#enter sib2, iclass 14, count 0 2006.173.21:14:22.77#ibcon#flushed, iclass 14, count 0 2006.173.21:14:22.77#ibcon#about to write, iclass 14, count 0 2006.173.21:14:22.77#ibcon#wrote, iclass 14, count 0 2006.173.21:14:22.77#ibcon#about to read 3, iclass 14, count 0 2006.173.21:14:22.80#ibcon#read 3, iclass 14, count 0 2006.173.21:14:22.80#ibcon#about to read 4, iclass 14, count 0 2006.173.21:14:22.80#ibcon#read 4, iclass 14, count 0 2006.173.21:14:22.80#ibcon#about to read 5, iclass 14, count 0 2006.173.21:14:22.80#ibcon#read 5, iclass 14, count 0 2006.173.21:14:22.80#ibcon#about to read 6, iclass 14, count 0 2006.173.21:14:22.80#ibcon#read 6, iclass 14, count 0 2006.173.21:14:22.80#ibcon#end of sib2, iclass 14, count 0 2006.173.21:14:22.80#ibcon#*after write, iclass 14, count 0 2006.173.21:14:22.80#ibcon#*before return 0, iclass 14, count 0 2006.173.21:14:22.80#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.21:14:22.80#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.21:14:22.80#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.21:14:22.80#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.21:14:22.80$vck44/valo=3,564.99 2006.173.21:14:22.80#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.21:14:22.80#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.21:14:22.80#ibcon#ireg 17 cls_cnt 0 2006.173.21:14:22.80#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.21:14:22.80#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.21:14:22.80#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.21:14:22.80#ibcon#enter wrdev, iclass 16, count 0 2006.173.21:14:22.80#ibcon#first serial, iclass 16, count 0 2006.173.21:14:22.80#ibcon#enter sib2, iclass 16, count 0 2006.173.21:14:22.80#ibcon#flushed, iclass 16, count 0 2006.173.21:14:22.80#ibcon#about to write, iclass 16, count 0 2006.173.21:14:22.80#ibcon#wrote, iclass 16, count 0 2006.173.21:14:22.80#ibcon#about to read 3, iclass 16, count 0 2006.173.21:14:22.82#ibcon#read 3, iclass 16, count 0 2006.173.21:14:22.82#ibcon#about to read 4, iclass 16, count 0 2006.173.21:14:22.82#ibcon#read 4, iclass 16, count 0 2006.173.21:14:22.82#ibcon#about to read 5, iclass 16, count 0 2006.173.21:14:22.82#ibcon#read 5, iclass 16, count 0 2006.173.21:14:22.82#ibcon#about to read 6, iclass 16, count 0 2006.173.21:14:22.82#ibcon#read 6, iclass 16, count 0 2006.173.21:14:22.82#ibcon#end of sib2, iclass 16, count 0 2006.173.21:14:22.82#ibcon#*mode == 0, iclass 16, count 0 2006.173.21:14:22.82#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.21:14:22.82#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.21:14:22.82#ibcon#*before write, iclass 16, count 0 2006.173.21:14:22.82#ibcon#enter sib2, iclass 16, count 0 2006.173.21:14:22.82#ibcon#flushed, iclass 16, count 0 2006.173.21:14:22.82#ibcon#about to write, iclass 16, count 0 2006.173.21:14:22.82#ibcon#wrote, iclass 16, count 0 2006.173.21:14:22.82#ibcon#about to read 3, iclass 16, count 0 2006.173.21:14:22.86#ibcon#read 3, iclass 16, count 0 2006.173.21:14:22.86#ibcon#about to read 4, iclass 16, count 0 2006.173.21:14:22.86#ibcon#read 4, iclass 16, count 0 2006.173.21:14:22.86#ibcon#about to read 5, iclass 16, count 0 2006.173.21:14:22.86#ibcon#read 5, iclass 16, count 0 2006.173.21:14:22.86#ibcon#about to read 6, iclass 16, count 0 2006.173.21:14:22.86#ibcon#read 6, iclass 16, count 0 2006.173.21:14:22.86#ibcon#end of sib2, iclass 16, count 0 2006.173.21:14:22.86#ibcon#*after write, iclass 16, count 0 2006.173.21:14:22.86#ibcon#*before return 0, iclass 16, count 0 2006.173.21:14:22.86#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.21:14:22.86#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.21:14:22.86#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.21:14:22.86#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.21:14:22.86$vck44/va=3,5 2006.173.21:14:22.86#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.21:14:22.86#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.21:14:22.86#ibcon#ireg 11 cls_cnt 2 2006.173.21:14:22.86#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.21:14:22.87#abcon#<5=/11 0.7 1.8 21.091001003.3\r\n> 2006.173.21:14:22.89#abcon#{5=INTERFACE CLEAR} 2006.173.21:14:22.92#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.21:14:22.92#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.21:14:22.92#ibcon#enter wrdev, iclass 19, count 2 2006.173.21:14:22.92#ibcon#first serial, iclass 19, count 2 2006.173.21:14:22.92#ibcon#enter sib2, iclass 19, count 2 2006.173.21:14:22.92#ibcon#flushed, iclass 19, count 2 2006.173.21:14:22.92#ibcon#about to write, iclass 19, count 2 2006.173.21:14:22.92#ibcon#wrote, iclass 19, count 2 2006.173.21:14:22.92#ibcon#about to read 3, iclass 19, count 2 2006.173.21:14:22.94#ibcon#read 3, iclass 19, count 2 2006.173.21:14:22.94#ibcon#about to read 4, iclass 19, count 2 2006.173.21:14:22.94#ibcon#read 4, iclass 19, count 2 2006.173.21:14:22.94#ibcon#about to read 5, iclass 19, count 2 2006.173.21:14:22.94#ibcon#read 5, iclass 19, count 2 2006.173.21:14:22.94#ibcon#about to read 6, iclass 19, count 2 2006.173.21:14:22.94#ibcon#read 6, iclass 19, count 2 2006.173.21:14:22.94#ibcon#end of sib2, iclass 19, count 2 2006.173.21:14:22.94#ibcon#*mode == 0, iclass 19, count 2 2006.173.21:14:22.94#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.21:14:22.94#ibcon#[25=AT03-05\r\n] 2006.173.21:14:22.94#ibcon#*before write, iclass 19, count 2 2006.173.21:14:22.94#ibcon#enter sib2, iclass 19, count 2 2006.173.21:14:22.94#ibcon#flushed, iclass 19, count 2 2006.173.21:14:22.94#ibcon#about to write, iclass 19, count 2 2006.173.21:14:22.94#ibcon#wrote, iclass 19, count 2 2006.173.21:14:22.94#ibcon#about to read 3, iclass 19, count 2 2006.173.21:14:22.95#abcon#[5=S1D000X0/0*\r\n] 2006.173.21:14:22.97#ibcon#read 3, iclass 19, count 2 2006.173.21:14:22.97#ibcon#about to read 4, iclass 19, count 2 2006.173.21:14:22.97#ibcon#read 4, iclass 19, count 2 2006.173.21:14:22.97#ibcon#about to read 5, iclass 19, count 2 2006.173.21:14:22.97#ibcon#read 5, iclass 19, count 2 2006.173.21:14:22.97#ibcon#about to read 6, iclass 19, count 2 2006.173.21:14:22.97#ibcon#read 6, iclass 19, count 2 2006.173.21:14:22.97#ibcon#end of sib2, iclass 19, count 2 2006.173.21:14:22.97#ibcon#*after write, iclass 19, count 2 2006.173.21:14:22.97#ibcon#*before return 0, iclass 19, count 2 2006.173.21:14:22.97#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.21:14:22.97#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.21:14:22.97#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.21:14:22.97#ibcon#ireg 7 cls_cnt 0 2006.173.21:14:22.97#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.21:14:23.09#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.21:14:23.09#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.21:14:23.09#ibcon#enter wrdev, iclass 19, count 0 2006.173.21:14:23.09#ibcon#first serial, iclass 19, count 0 2006.173.21:14:23.09#ibcon#enter sib2, iclass 19, count 0 2006.173.21:14:23.09#ibcon#flushed, iclass 19, count 0 2006.173.21:14:23.09#ibcon#about to write, iclass 19, count 0 2006.173.21:14:23.09#ibcon#wrote, iclass 19, count 0 2006.173.21:14:23.09#ibcon#about to read 3, iclass 19, count 0 2006.173.21:14:23.11#ibcon#read 3, iclass 19, count 0 2006.173.21:14:23.11#ibcon#about to read 4, iclass 19, count 0 2006.173.21:14:23.11#ibcon#read 4, iclass 19, count 0 2006.173.21:14:23.11#ibcon#about to read 5, iclass 19, count 0 2006.173.21:14:23.11#ibcon#read 5, iclass 19, count 0 2006.173.21:14:23.11#ibcon#about to read 6, iclass 19, count 0 2006.173.21:14:23.11#ibcon#read 6, iclass 19, count 0 2006.173.21:14:23.11#ibcon#end of sib2, iclass 19, count 0 2006.173.21:14:23.11#ibcon#*mode == 0, iclass 19, count 0 2006.173.21:14:23.11#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.21:14:23.11#ibcon#[25=USB\r\n] 2006.173.21:14:23.11#ibcon#*before write, iclass 19, count 0 2006.173.21:14:23.11#ibcon#enter sib2, iclass 19, count 0 2006.173.21:14:23.11#ibcon#flushed, iclass 19, count 0 2006.173.21:14:23.11#ibcon#about to write, iclass 19, count 0 2006.173.21:14:23.11#ibcon#wrote, iclass 19, count 0 2006.173.21:14:23.11#ibcon#about to read 3, iclass 19, count 0 2006.173.21:14:23.14#ibcon#read 3, iclass 19, count 0 2006.173.21:14:23.14#ibcon#about to read 4, iclass 19, count 0 2006.173.21:14:23.14#ibcon#read 4, iclass 19, count 0 2006.173.21:14:23.14#ibcon#about to read 5, iclass 19, count 0 2006.173.21:14:23.14#ibcon#read 5, iclass 19, count 0 2006.173.21:14:23.14#ibcon#about to read 6, iclass 19, count 0 2006.173.21:14:23.14#ibcon#read 6, iclass 19, count 0 2006.173.21:14:23.14#ibcon#end of sib2, iclass 19, count 0 2006.173.21:14:23.14#ibcon#*after write, iclass 19, count 0 2006.173.21:14:23.14#ibcon#*before return 0, iclass 19, count 0 2006.173.21:14:23.14#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.21:14:23.14#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.21:14:23.14#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.21:14:23.14#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.21:14:23.14$vck44/valo=4,624.99 2006.173.21:14:23.14#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.21:14:23.14#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.21:14:23.14#ibcon#ireg 17 cls_cnt 0 2006.173.21:14:23.14#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.21:14:23.14#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.21:14:23.14#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.21:14:23.14#ibcon#enter wrdev, iclass 24, count 0 2006.173.21:14:23.14#ibcon#first serial, iclass 24, count 0 2006.173.21:14:23.14#ibcon#enter sib2, iclass 24, count 0 2006.173.21:14:23.14#ibcon#flushed, iclass 24, count 0 2006.173.21:14:23.14#ibcon#about to write, iclass 24, count 0 2006.173.21:14:23.14#ibcon#wrote, iclass 24, count 0 2006.173.21:14:23.14#ibcon#about to read 3, iclass 24, count 0 2006.173.21:14:23.16#ibcon#read 3, iclass 24, count 0 2006.173.21:14:23.16#ibcon#about to read 4, iclass 24, count 0 2006.173.21:14:23.16#ibcon#read 4, iclass 24, count 0 2006.173.21:14:23.16#ibcon#about to read 5, iclass 24, count 0 2006.173.21:14:23.16#ibcon#read 5, iclass 24, count 0 2006.173.21:14:23.16#ibcon#about to read 6, iclass 24, count 0 2006.173.21:14:23.16#ibcon#read 6, iclass 24, count 0 2006.173.21:14:23.16#ibcon#end of sib2, iclass 24, count 0 2006.173.21:14:23.16#ibcon#*mode == 0, iclass 24, count 0 2006.173.21:14:23.16#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.21:14:23.16#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.21:14:23.16#ibcon#*before write, iclass 24, count 0 2006.173.21:14:23.16#ibcon#enter sib2, iclass 24, count 0 2006.173.21:14:23.16#ibcon#flushed, iclass 24, count 0 2006.173.21:14:23.16#ibcon#about to write, iclass 24, count 0 2006.173.21:14:23.16#ibcon#wrote, iclass 24, count 0 2006.173.21:14:23.16#ibcon#about to read 3, iclass 24, count 0 2006.173.21:14:23.20#ibcon#read 3, iclass 24, count 0 2006.173.21:14:23.20#ibcon#about to read 4, iclass 24, count 0 2006.173.21:14:23.20#ibcon#read 4, iclass 24, count 0 2006.173.21:14:23.20#ibcon#about to read 5, iclass 24, count 0 2006.173.21:14:23.20#ibcon#read 5, iclass 24, count 0 2006.173.21:14:23.20#ibcon#about to read 6, iclass 24, count 0 2006.173.21:14:23.20#ibcon#read 6, iclass 24, count 0 2006.173.21:14:23.20#ibcon#end of sib2, iclass 24, count 0 2006.173.21:14:23.20#ibcon#*after write, iclass 24, count 0 2006.173.21:14:23.20#ibcon#*before return 0, iclass 24, count 0 2006.173.21:14:23.20#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.21:14:23.20#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.21:14:23.20#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.21:14:23.20#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.21:14:23.20$vck44/va=4,6 2006.173.21:14:23.20#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.21:14:23.20#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.21:14:23.20#ibcon#ireg 11 cls_cnt 2 2006.173.21:14:23.20#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.21:14:23.26#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.21:14:23.26#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.21:14:23.26#ibcon#enter wrdev, iclass 26, count 2 2006.173.21:14:23.26#ibcon#first serial, iclass 26, count 2 2006.173.21:14:23.26#ibcon#enter sib2, iclass 26, count 2 2006.173.21:14:23.26#ibcon#flushed, iclass 26, count 2 2006.173.21:14:23.26#ibcon#about to write, iclass 26, count 2 2006.173.21:14:23.26#ibcon#wrote, iclass 26, count 2 2006.173.21:14:23.26#ibcon#about to read 3, iclass 26, count 2 2006.173.21:14:23.28#ibcon#read 3, iclass 26, count 2 2006.173.21:14:23.28#ibcon#about to read 4, iclass 26, count 2 2006.173.21:14:23.28#ibcon#read 4, iclass 26, count 2 2006.173.21:14:23.28#ibcon#about to read 5, iclass 26, count 2 2006.173.21:14:23.28#ibcon#read 5, iclass 26, count 2 2006.173.21:14:23.28#ibcon#about to read 6, iclass 26, count 2 2006.173.21:14:23.28#ibcon#read 6, iclass 26, count 2 2006.173.21:14:23.28#ibcon#end of sib2, iclass 26, count 2 2006.173.21:14:23.28#ibcon#*mode == 0, iclass 26, count 2 2006.173.21:14:23.28#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.21:14:23.28#ibcon#[25=AT04-06\r\n] 2006.173.21:14:23.28#ibcon#*before write, iclass 26, count 2 2006.173.21:14:23.28#ibcon#enter sib2, iclass 26, count 2 2006.173.21:14:23.28#ibcon#flushed, iclass 26, count 2 2006.173.21:14:23.28#ibcon#about to write, iclass 26, count 2 2006.173.21:14:23.28#ibcon#wrote, iclass 26, count 2 2006.173.21:14:23.28#ibcon#about to read 3, iclass 26, count 2 2006.173.21:14:23.31#ibcon#read 3, iclass 26, count 2 2006.173.21:14:23.31#ibcon#about to read 4, iclass 26, count 2 2006.173.21:14:23.31#ibcon#read 4, iclass 26, count 2 2006.173.21:14:23.31#ibcon#about to read 5, iclass 26, count 2 2006.173.21:14:23.31#ibcon#read 5, iclass 26, count 2 2006.173.21:14:23.31#ibcon#about to read 6, iclass 26, count 2 2006.173.21:14:23.31#ibcon#read 6, iclass 26, count 2 2006.173.21:14:23.31#ibcon#end of sib2, iclass 26, count 2 2006.173.21:14:23.31#ibcon#*after write, iclass 26, count 2 2006.173.21:14:23.31#ibcon#*before return 0, iclass 26, count 2 2006.173.21:14:23.31#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.21:14:23.31#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.21:14:23.31#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.21:14:23.31#ibcon#ireg 7 cls_cnt 0 2006.173.21:14:23.31#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.21:14:23.43#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.21:14:23.43#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.21:14:23.43#ibcon#enter wrdev, iclass 26, count 0 2006.173.21:14:23.43#ibcon#first serial, iclass 26, count 0 2006.173.21:14:23.43#ibcon#enter sib2, iclass 26, count 0 2006.173.21:14:23.43#ibcon#flushed, iclass 26, count 0 2006.173.21:14:23.43#ibcon#about to write, iclass 26, count 0 2006.173.21:14:23.43#ibcon#wrote, iclass 26, count 0 2006.173.21:14:23.43#ibcon#about to read 3, iclass 26, count 0 2006.173.21:14:23.45#ibcon#read 3, iclass 26, count 0 2006.173.21:14:23.45#ibcon#about to read 4, iclass 26, count 0 2006.173.21:14:23.45#ibcon#read 4, iclass 26, count 0 2006.173.21:14:23.45#ibcon#about to read 5, iclass 26, count 0 2006.173.21:14:23.45#ibcon#read 5, iclass 26, count 0 2006.173.21:14:23.45#ibcon#about to read 6, iclass 26, count 0 2006.173.21:14:23.45#ibcon#read 6, iclass 26, count 0 2006.173.21:14:23.45#ibcon#end of sib2, iclass 26, count 0 2006.173.21:14:23.45#ibcon#*mode == 0, iclass 26, count 0 2006.173.21:14:23.45#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.21:14:23.45#ibcon#[25=USB\r\n] 2006.173.21:14:23.45#ibcon#*before write, iclass 26, count 0 2006.173.21:14:23.45#ibcon#enter sib2, iclass 26, count 0 2006.173.21:14:23.45#ibcon#flushed, iclass 26, count 0 2006.173.21:14:23.45#ibcon#about to write, iclass 26, count 0 2006.173.21:14:23.45#ibcon#wrote, iclass 26, count 0 2006.173.21:14:23.45#ibcon#about to read 3, iclass 26, count 0 2006.173.21:14:23.48#ibcon#read 3, iclass 26, count 0 2006.173.21:14:23.48#ibcon#about to read 4, iclass 26, count 0 2006.173.21:14:23.48#ibcon#read 4, iclass 26, count 0 2006.173.21:14:23.48#ibcon#about to read 5, iclass 26, count 0 2006.173.21:14:23.48#ibcon#read 5, iclass 26, count 0 2006.173.21:14:23.48#ibcon#about to read 6, iclass 26, count 0 2006.173.21:14:23.48#ibcon#read 6, iclass 26, count 0 2006.173.21:14:23.48#ibcon#end of sib2, iclass 26, count 0 2006.173.21:14:23.48#ibcon#*after write, iclass 26, count 0 2006.173.21:14:23.48#ibcon#*before return 0, iclass 26, count 0 2006.173.21:14:23.48#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.21:14:23.48#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.21:14:23.48#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.21:14:23.48#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.21:14:23.48$vck44/valo=5,734.99 2006.173.21:14:23.48#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.21:14:23.48#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.21:14:23.48#ibcon#ireg 17 cls_cnt 0 2006.173.21:14:23.48#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.21:14:23.48#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.21:14:23.48#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.21:14:23.48#ibcon#enter wrdev, iclass 28, count 0 2006.173.21:14:23.48#ibcon#first serial, iclass 28, count 0 2006.173.21:14:23.48#ibcon#enter sib2, iclass 28, count 0 2006.173.21:14:23.48#ibcon#flushed, iclass 28, count 0 2006.173.21:14:23.48#ibcon#about to write, iclass 28, count 0 2006.173.21:14:23.48#ibcon#wrote, iclass 28, count 0 2006.173.21:14:23.48#ibcon#about to read 3, iclass 28, count 0 2006.173.21:14:23.50#ibcon#read 3, iclass 28, count 0 2006.173.21:14:23.50#ibcon#about to read 4, iclass 28, count 0 2006.173.21:14:23.50#ibcon#read 4, iclass 28, count 0 2006.173.21:14:23.50#ibcon#about to read 5, iclass 28, count 0 2006.173.21:14:23.50#ibcon#read 5, iclass 28, count 0 2006.173.21:14:23.50#ibcon#about to read 6, iclass 28, count 0 2006.173.21:14:23.50#ibcon#read 6, iclass 28, count 0 2006.173.21:14:23.50#ibcon#end of sib2, iclass 28, count 0 2006.173.21:14:23.50#ibcon#*mode == 0, iclass 28, count 0 2006.173.21:14:23.50#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.21:14:23.50#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.21:14:23.50#ibcon#*before write, iclass 28, count 0 2006.173.21:14:23.50#ibcon#enter sib2, iclass 28, count 0 2006.173.21:14:23.50#ibcon#flushed, iclass 28, count 0 2006.173.21:14:23.50#ibcon#about to write, iclass 28, count 0 2006.173.21:14:23.50#ibcon#wrote, iclass 28, count 0 2006.173.21:14:23.50#ibcon#about to read 3, iclass 28, count 0 2006.173.21:14:23.54#ibcon#read 3, iclass 28, count 0 2006.173.21:14:23.54#ibcon#about to read 4, iclass 28, count 0 2006.173.21:14:23.54#ibcon#read 4, iclass 28, count 0 2006.173.21:14:23.54#ibcon#about to read 5, iclass 28, count 0 2006.173.21:14:23.54#ibcon#read 5, iclass 28, count 0 2006.173.21:14:23.54#ibcon#about to read 6, iclass 28, count 0 2006.173.21:14:23.54#ibcon#read 6, iclass 28, count 0 2006.173.21:14:23.54#ibcon#end of sib2, iclass 28, count 0 2006.173.21:14:23.54#ibcon#*after write, iclass 28, count 0 2006.173.21:14:23.54#ibcon#*before return 0, iclass 28, count 0 2006.173.21:14:23.54#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.21:14:23.54#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.21:14:23.54#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.21:14:23.54#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.21:14:23.54$vck44/va=5,4 2006.173.21:14:23.54#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.21:14:23.54#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.21:14:23.54#ibcon#ireg 11 cls_cnt 2 2006.173.21:14:23.54#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.21:14:23.60#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.21:14:23.60#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.21:14:23.60#ibcon#enter wrdev, iclass 30, count 2 2006.173.21:14:23.60#ibcon#first serial, iclass 30, count 2 2006.173.21:14:23.60#ibcon#enter sib2, iclass 30, count 2 2006.173.21:14:23.60#ibcon#flushed, iclass 30, count 2 2006.173.21:14:23.60#ibcon#about to write, iclass 30, count 2 2006.173.21:14:23.60#ibcon#wrote, iclass 30, count 2 2006.173.21:14:23.60#ibcon#about to read 3, iclass 30, count 2 2006.173.21:14:23.62#ibcon#read 3, iclass 30, count 2 2006.173.21:14:23.62#ibcon#about to read 4, iclass 30, count 2 2006.173.21:14:23.62#ibcon#read 4, iclass 30, count 2 2006.173.21:14:23.62#ibcon#about to read 5, iclass 30, count 2 2006.173.21:14:23.62#ibcon#read 5, iclass 30, count 2 2006.173.21:14:23.62#ibcon#about to read 6, iclass 30, count 2 2006.173.21:14:23.62#ibcon#read 6, iclass 30, count 2 2006.173.21:14:23.62#ibcon#end of sib2, iclass 30, count 2 2006.173.21:14:23.62#ibcon#*mode == 0, iclass 30, count 2 2006.173.21:14:23.62#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.21:14:23.62#ibcon#[25=AT05-04\r\n] 2006.173.21:14:23.62#ibcon#*before write, iclass 30, count 2 2006.173.21:14:23.62#ibcon#enter sib2, iclass 30, count 2 2006.173.21:14:23.62#ibcon#flushed, iclass 30, count 2 2006.173.21:14:23.62#ibcon#about to write, iclass 30, count 2 2006.173.21:14:23.62#ibcon#wrote, iclass 30, count 2 2006.173.21:14:23.62#ibcon#about to read 3, iclass 30, count 2 2006.173.21:14:23.65#ibcon#read 3, iclass 30, count 2 2006.173.21:14:23.65#ibcon#about to read 4, iclass 30, count 2 2006.173.21:14:23.65#ibcon#read 4, iclass 30, count 2 2006.173.21:14:23.65#ibcon#about to read 5, iclass 30, count 2 2006.173.21:14:23.65#ibcon#read 5, iclass 30, count 2 2006.173.21:14:23.65#ibcon#about to read 6, iclass 30, count 2 2006.173.21:14:23.65#ibcon#read 6, iclass 30, count 2 2006.173.21:14:23.65#ibcon#end of sib2, iclass 30, count 2 2006.173.21:14:23.65#ibcon#*after write, iclass 30, count 2 2006.173.21:14:23.65#ibcon#*before return 0, iclass 30, count 2 2006.173.21:14:23.65#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.21:14:23.65#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.21:14:23.65#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.21:14:23.65#ibcon#ireg 7 cls_cnt 0 2006.173.21:14:23.65#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.21:14:23.77#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.21:14:23.77#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.21:14:23.77#ibcon#enter wrdev, iclass 30, count 0 2006.173.21:14:23.77#ibcon#first serial, iclass 30, count 0 2006.173.21:14:23.77#ibcon#enter sib2, iclass 30, count 0 2006.173.21:14:23.77#ibcon#flushed, iclass 30, count 0 2006.173.21:14:23.77#ibcon#about to write, iclass 30, count 0 2006.173.21:14:23.77#ibcon#wrote, iclass 30, count 0 2006.173.21:14:23.77#ibcon#about to read 3, iclass 30, count 0 2006.173.21:14:23.79#ibcon#read 3, iclass 30, count 0 2006.173.21:14:23.79#ibcon#about to read 4, iclass 30, count 0 2006.173.21:14:23.79#ibcon#read 4, iclass 30, count 0 2006.173.21:14:23.79#ibcon#about to read 5, iclass 30, count 0 2006.173.21:14:23.79#ibcon#read 5, iclass 30, count 0 2006.173.21:14:23.79#ibcon#about to read 6, iclass 30, count 0 2006.173.21:14:23.79#ibcon#read 6, iclass 30, count 0 2006.173.21:14:23.79#ibcon#end of sib2, iclass 30, count 0 2006.173.21:14:23.79#ibcon#*mode == 0, iclass 30, count 0 2006.173.21:14:23.79#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.21:14:23.79#ibcon#[25=USB\r\n] 2006.173.21:14:23.79#ibcon#*before write, iclass 30, count 0 2006.173.21:14:23.79#ibcon#enter sib2, iclass 30, count 0 2006.173.21:14:23.79#ibcon#flushed, iclass 30, count 0 2006.173.21:14:23.79#ibcon#about to write, iclass 30, count 0 2006.173.21:14:23.79#ibcon#wrote, iclass 30, count 0 2006.173.21:14:23.79#ibcon#about to read 3, iclass 30, count 0 2006.173.21:14:23.82#ibcon#read 3, iclass 30, count 0 2006.173.21:14:23.82#ibcon#about to read 4, iclass 30, count 0 2006.173.21:14:23.82#ibcon#read 4, iclass 30, count 0 2006.173.21:14:23.82#ibcon#about to read 5, iclass 30, count 0 2006.173.21:14:23.82#ibcon#read 5, iclass 30, count 0 2006.173.21:14:23.82#ibcon#about to read 6, iclass 30, count 0 2006.173.21:14:23.82#ibcon#read 6, iclass 30, count 0 2006.173.21:14:23.82#ibcon#end of sib2, iclass 30, count 0 2006.173.21:14:23.82#ibcon#*after write, iclass 30, count 0 2006.173.21:14:23.82#ibcon#*before return 0, iclass 30, count 0 2006.173.21:14:23.82#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.21:14:23.82#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.21:14:23.82#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.21:14:23.82#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.21:14:23.82$vck44/valo=6,814.99 2006.173.21:14:23.82#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.21:14:23.82#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.21:14:23.82#ibcon#ireg 17 cls_cnt 0 2006.173.21:14:23.82#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.21:14:23.82#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.21:14:23.82#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.21:14:23.82#ibcon#enter wrdev, iclass 32, count 0 2006.173.21:14:23.82#ibcon#first serial, iclass 32, count 0 2006.173.21:14:23.82#ibcon#enter sib2, iclass 32, count 0 2006.173.21:14:23.82#ibcon#flushed, iclass 32, count 0 2006.173.21:14:23.82#ibcon#about to write, iclass 32, count 0 2006.173.21:14:23.82#ibcon#wrote, iclass 32, count 0 2006.173.21:14:23.82#ibcon#about to read 3, iclass 32, count 0 2006.173.21:14:23.84#ibcon#read 3, iclass 32, count 0 2006.173.21:14:23.84#ibcon#about to read 4, iclass 32, count 0 2006.173.21:14:23.84#ibcon#read 4, iclass 32, count 0 2006.173.21:14:23.84#ibcon#about to read 5, iclass 32, count 0 2006.173.21:14:23.84#ibcon#read 5, iclass 32, count 0 2006.173.21:14:23.84#ibcon#about to read 6, iclass 32, count 0 2006.173.21:14:23.84#ibcon#read 6, iclass 32, count 0 2006.173.21:14:23.84#ibcon#end of sib2, iclass 32, count 0 2006.173.21:14:23.84#ibcon#*mode == 0, iclass 32, count 0 2006.173.21:14:23.84#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.21:14:23.84#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.21:14:23.84#ibcon#*before write, iclass 32, count 0 2006.173.21:14:23.84#ibcon#enter sib2, iclass 32, count 0 2006.173.21:14:23.84#ibcon#flushed, iclass 32, count 0 2006.173.21:14:23.84#ibcon#about to write, iclass 32, count 0 2006.173.21:14:23.84#ibcon#wrote, iclass 32, count 0 2006.173.21:14:23.84#ibcon#about to read 3, iclass 32, count 0 2006.173.21:14:23.88#ibcon#read 3, iclass 32, count 0 2006.173.21:14:23.88#ibcon#about to read 4, iclass 32, count 0 2006.173.21:14:23.88#ibcon#read 4, iclass 32, count 0 2006.173.21:14:23.88#ibcon#about to read 5, iclass 32, count 0 2006.173.21:14:23.88#ibcon#read 5, iclass 32, count 0 2006.173.21:14:23.88#ibcon#about to read 6, iclass 32, count 0 2006.173.21:14:23.88#ibcon#read 6, iclass 32, count 0 2006.173.21:14:23.88#ibcon#end of sib2, iclass 32, count 0 2006.173.21:14:23.88#ibcon#*after write, iclass 32, count 0 2006.173.21:14:23.88#ibcon#*before return 0, iclass 32, count 0 2006.173.21:14:23.88#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.21:14:23.88#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.21:14:23.88#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.21:14:23.88#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.21:14:23.88$vck44/va=6,3 2006.173.21:14:23.88#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.21:14:23.88#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.21:14:23.88#ibcon#ireg 11 cls_cnt 2 2006.173.21:14:23.88#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.21:14:23.94#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.21:14:23.94#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.21:14:23.94#ibcon#enter wrdev, iclass 34, count 2 2006.173.21:14:23.94#ibcon#first serial, iclass 34, count 2 2006.173.21:14:23.94#ibcon#enter sib2, iclass 34, count 2 2006.173.21:14:23.94#ibcon#flushed, iclass 34, count 2 2006.173.21:14:23.94#ibcon#about to write, iclass 34, count 2 2006.173.21:14:23.94#ibcon#wrote, iclass 34, count 2 2006.173.21:14:23.94#ibcon#about to read 3, iclass 34, count 2 2006.173.21:14:23.96#ibcon#read 3, iclass 34, count 2 2006.173.21:14:23.96#ibcon#about to read 4, iclass 34, count 2 2006.173.21:14:23.96#ibcon#read 4, iclass 34, count 2 2006.173.21:14:23.96#ibcon#about to read 5, iclass 34, count 2 2006.173.21:14:23.96#ibcon#read 5, iclass 34, count 2 2006.173.21:14:23.96#ibcon#about to read 6, iclass 34, count 2 2006.173.21:14:23.96#ibcon#read 6, iclass 34, count 2 2006.173.21:14:23.96#ibcon#end of sib2, iclass 34, count 2 2006.173.21:14:23.96#ibcon#*mode == 0, iclass 34, count 2 2006.173.21:14:23.96#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.21:14:23.96#ibcon#[25=AT06-03\r\n] 2006.173.21:14:23.96#ibcon#*before write, iclass 34, count 2 2006.173.21:14:23.96#ibcon#enter sib2, iclass 34, count 2 2006.173.21:14:23.96#ibcon#flushed, iclass 34, count 2 2006.173.21:14:23.96#ibcon#about to write, iclass 34, count 2 2006.173.21:14:23.96#ibcon#wrote, iclass 34, count 2 2006.173.21:14:23.96#ibcon#about to read 3, iclass 34, count 2 2006.173.21:14:23.99#ibcon#read 3, iclass 34, count 2 2006.173.21:14:23.99#ibcon#about to read 4, iclass 34, count 2 2006.173.21:14:23.99#ibcon#read 4, iclass 34, count 2 2006.173.21:14:23.99#ibcon#about to read 5, iclass 34, count 2 2006.173.21:14:23.99#ibcon#read 5, iclass 34, count 2 2006.173.21:14:23.99#ibcon#about to read 6, iclass 34, count 2 2006.173.21:14:23.99#ibcon#read 6, iclass 34, count 2 2006.173.21:14:23.99#ibcon#end of sib2, iclass 34, count 2 2006.173.21:14:23.99#ibcon#*after write, iclass 34, count 2 2006.173.21:14:23.99#ibcon#*before return 0, iclass 34, count 2 2006.173.21:14:23.99#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.21:14:23.99#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.21:14:23.99#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.21:14:23.99#ibcon#ireg 7 cls_cnt 0 2006.173.21:14:23.99#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.21:14:24.11#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.21:14:24.11#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.21:14:24.11#ibcon#enter wrdev, iclass 34, count 0 2006.173.21:14:24.11#ibcon#first serial, iclass 34, count 0 2006.173.21:14:24.11#ibcon#enter sib2, iclass 34, count 0 2006.173.21:14:24.11#ibcon#flushed, iclass 34, count 0 2006.173.21:14:24.11#ibcon#about to write, iclass 34, count 0 2006.173.21:14:24.11#ibcon#wrote, iclass 34, count 0 2006.173.21:14:24.11#ibcon#about to read 3, iclass 34, count 0 2006.173.21:14:24.13#ibcon#read 3, iclass 34, count 0 2006.173.21:14:24.13#ibcon#about to read 4, iclass 34, count 0 2006.173.21:14:24.13#ibcon#read 4, iclass 34, count 0 2006.173.21:14:24.13#ibcon#about to read 5, iclass 34, count 0 2006.173.21:14:24.13#ibcon#read 5, iclass 34, count 0 2006.173.21:14:24.13#ibcon#about to read 6, iclass 34, count 0 2006.173.21:14:24.13#ibcon#read 6, iclass 34, count 0 2006.173.21:14:24.13#ibcon#end of sib2, iclass 34, count 0 2006.173.21:14:24.13#ibcon#*mode == 0, iclass 34, count 0 2006.173.21:14:24.13#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.21:14:24.13#ibcon#[25=USB\r\n] 2006.173.21:14:24.13#ibcon#*before write, iclass 34, count 0 2006.173.21:14:24.13#ibcon#enter sib2, iclass 34, count 0 2006.173.21:14:24.13#ibcon#flushed, iclass 34, count 0 2006.173.21:14:24.13#ibcon#about to write, iclass 34, count 0 2006.173.21:14:24.13#ibcon#wrote, iclass 34, count 0 2006.173.21:14:24.13#ibcon#about to read 3, iclass 34, count 0 2006.173.21:14:24.16#ibcon#read 3, iclass 34, count 0 2006.173.21:14:24.16#ibcon#about to read 4, iclass 34, count 0 2006.173.21:14:24.16#ibcon#read 4, iclass 34, count 0 2006.173.21:14:24.16#ibcon#about to read 5, iclass 34, count 0 2006.173.21:14:24.16#ibcon#read 5, iclass 34, count 0 2006.173.21:14:24.16#ibcon#about to read 6, iclass 34, count 0 2006.173.21:14:24.16#ibcon#read 6, iclass 34, count 0 2006.173.21:14:24.16#ibcon#end of sib2, iclass 34, count 0 2006.173.21:14:24.16#ibcon#*after write, iclass 34, count 0 2006.173.21:14:24.16#ibcon#*before return 0, iclass 34, count 0 2006.173.21:14:24.16#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.21:14:24.16#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.21:14:24.16#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.21:14:24.16#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.21:14:24.16$vck44/valo=7,864.99 2006.173.21:14:24.16#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.21:14:24.16#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.21:14:24.16#ibcon#ireg 17 cls_cnt 0 2006.173.21:14:24.16#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.21:14:24.16#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.21:14:24.16#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.21:14:24.16#ibcon#enter wrdev, iclass 36, count 0 2006.173.21:14:24.16#ibcon#first serial, iclass 36, count 0 2006.173.21:14:24.16#ibcon#enter sib2, iclass 36, count 0 2006.173.21:14:24.16#ibcon#flushed, iclass 36, count 0 2006.173.21:14:24.16#ibcon#about to write, iclass 36, count 0 2006.173.21:14:24.16#ibcon#wrote, iclass 36, count 0 2006.173.21:14:24.16#ibcon#about to read 3, iclass 36, count 0 2006.173.21:14:24.18#ibcon#read 3, iclass 36, count 0 2006.173.21:14:24.18#ibcon#about to read 4, iclass 36, count 0 2006.173.21:14:24.18#ibcon#read 4, iclass 36, count 0 2006.173.21:14:24.18#ibcon#about to read 5, iclass 36, count 0 2006.173.21:14:24.18#ibcon#read 5, iclass 36, count 0 2006.173.21:14:24.18#ibcon#about to read 6, iclass 36, count 0 2006.173.21:14:24.18#ibcon#read 6, iclass 36, count 0 2006.173.21:14:24.18#ibcon#end of sib2, iclass 36, count 0 2006.173.21:14:24.18#ibcon#*mode == 0, iclass 36, count 0 2006.173.21:14:24.18#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.21:14:24.18#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.21:14:24.18#ibcon#*before write, iclass 36, count 0 2006.173.21:14:24.18#ibcon#enter sib2, iclass 36, count 0 2006.173.21:14:24.18#ibcon#flushed, iclass 36, count 0 2006.173.21:14:24.18#ibcon#about to write, iclass 36, count 0 2006.173.21:14:24.18#ibcon#wrote, iclass 36, count 0 2006.173.21:14:24.18#ibcon#about to read 3, iclass 36, count 0 2006.173.21:14:24.22#ibcon#read 3, iclass 36, count 0 2006.173.21:14:24.22#ibcon#about to read 4, iclass 36, count 0 2006.173.21:14:24.22#ibcon#read 4, iclass 36, count 0 2006.173.21:14:24.22#ibcon#about to read 5, iclass 36, count 0 2006.173.21:14:24.22#ibcon#read 5, iclass 36, count 0 2006.173.21:14:24.22#ibcon#about to read 6, iclass 36, count 0 2006.173.21:14:24.22#ibcon#read 6, iclass 36, count 0 2006.173.21:14:24.22#ibcon#end of sib2, iclass 36, count 0 2006.173.21:14:24.22#ibcon#*after write, iclass 36, count 0 2006.173.21:14:24.22#ibcon#*before return 0, iclass 36, count 0 2006.173.21:14:24.22#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.21:14:24.22#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.21:14:24.22#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.21:14:24.22#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.21:14:24.22$vck44/va=7,4 2006.173.21:14:24.22#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.21:14:24.22#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.21:14:24.22#ibcon#ireg 11 cls_cnt 2 2006.173.21:14:24.22#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.21:14:24.28#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.21:14:24.28#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.21:14:24.28#ibcon#enter wrdev, iclass 38, count 2 2006.173.21:14:24.28#ibcon#first serial, iclass 38, count 2 2006.173.21:14:24.28#ibcon#enter sib2, iclass 38, count 2 2006.173.21:14:24.28#ibcon#flushed, iclass 38, count 2 2006.173.21:14:24.28#ibcon#about to write, iclass 38, count 2 2006.173.21:14:24.28#ibcon#wrote, iclass 38, count 2 2006.173.21:14:24.28#ibcon#about to read 3, iclass 38, count 2 2006.173.21:14:24.30#ibcon#read 3, iclass 38, count 2 2006.173.21:14:24.30#ibcon#about to read 4, iclass 38, count 2 2006.173.21:14:24.30#ibcon#read 4, iclass 38, count 2 2006.173.21:14:24.30#ibcon#about to read 5, iclass 38, count 2 2006.173.21:14:24.30#ibcon#read 5, iclass 38, count 2 2006.173.21:14:24.30#ibcon#about to read 6, iclass 38, count 2 2006.173.21:14:24.30#ibcon#read 6, iclass 38, count 2 2006.173.21:14:24.30#ibcon#end of sib2, iclass 38, count 2 2006.173.21:14:24.30#ibcon#*mode == 0, iclass 38, count 2 2006.173.21:14:24.30#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.21:14:24.30#ibcon#[25=AT07-04\r\n] 2006.173.21:14:24.30#ibcon#*before write, iclass 38, count 2 2006.173.21:14:24.30#ibcon#enter sib2, iclass 38, count 2 2006.173.21:14:24.30#ibcon#flushed, iclass 38, count 2 2006.173.21:14:24.30#ibcon#about to write, iclass 38, count 2 2006.173.21:14:24.30#ibcon#wrote, iclass 38, count 2 2006.173.21:14:24.30#ibcon#about to read 3, iclass 38, count 2 2006.173.21:14:24.33#ibcon#read 3, iclass 38, count 2 2006.173.21:14:24.33#ibcon#about to read 4, iclass 38, count 2 2006.173.21:14:24.33#ibcon#read 4, iclass 38, count 2 2006.173.21:14:24.33#ibcon#about to read 5, iclass 38, count 2 2006.173.21:14:24.33#ibcon#read 5, iclass 38, count 2 2006.173.21:14:24.33#ibcon#about to read 6, iclass 38, count 2 2006.173.21:14:24.33#ibcon#read 6, iclass 38, count 2 2006.173.21:14:24.33#ibcon#end of sib2, iclass 38, count 2 2006.173.21:14:24.33#ibcon#*after write, iclass 38, count 2 2006.173.21:14:24.33#ibcon#*before return 0, iclass 38, count 2 2006.173.21:14:24.33#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.21:14:24.33#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.21:14:24.33#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.21:14:24.33#ibcon#ireg 7 cls_cnt 0 2006.173.21:14:24.33#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.21:14:24.45#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.21:14:24.45#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.21:14:24.45#ibcon#enter wrdev, iclass 38, count 0 2006.173.21:14:24.45#ibcon#first serial, iclass 38, count 0 2006.173.21:14:24.45#ibcon#enter sib2, iclass 38, count 0 2006.173.21:14:24.45#ibcon#flushed, iclass 38, count 0 2006.173.21:14:24.45#ibcon#about to write, iclass 38, count 0 2006.173.21:14:24.45#ibcon#wrote, iclass 38, count 0 2006.173.21:14:24.45#ibcon#about to read 3, iclass 38, count 0 2006.173.21:14:24.47#ibcon#read 3, iclass 38, count 0 2006.173.21:14:24.47#ibcon#about to read 4, iclass 38, count 0 2006.173.21:14:24.47#ibcon#read 4, iclass 38, count 0 2006.173.21:14:24.47#ibcon#about to read 5, iclass 38, count 0 2006.173.21:14:24.47#ibcon#read 5, iclass 38, count 0 2006.173.21:14:24.47#ibcon#about to read 6, iclass 38, count 0 2006.173.21:14:24.47#ibcon#read 6, iclass 38, count 0 2006.173.21:14:24.47#ibcon#end of sib2, iclass 38, count 0 2006.173.21:14:24.47#ibcon#*mode == 0, iclass 38, count 0 2006.173.21:14:24.47#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.21:14:24.47#ibcon#[25=USB\r\n] 2006.173.21:14:24.47#ibcon#*before write, iclass 38, count 0 2006.173.21:14:24.47#ibcon#enter sib2, iclass 38, count 0 2006.173.21:14:24.47#ibcon#flushed, iclass 38, count 0 2006.173.21:14:24.47#ibcon#about to write, iclass 38, count 0 2006.173.21:14:24.47#ibcon#wrote, iclass 38, count 0 2006.173.21:14:24.47#ibcon#about to read 3, iclass 38, count 0 2006.173.21:14:24.50#ibcon#read 3, iclass 38, count 0 2006.173.21:14:24.50#ibcon#about to read 4, iclass 38, count 0 2006.173.21:14:24.50#ibcon#read 4, iclass 38, count 0 2006.173.21:14:24.50#ibcon#about to read 5, iclass 38, count 0 2006.173.21:14:24.50#ibcon#read 5, iclass 38, count 0 2006.173.21:14:24.50#ibcon#about to read 6, iclass 38, count 0 2006.173.21:14:24.50#ibcon#read 6, iclass 38, count 0 2006.173.21:14:24.50#ibcon#end of sib2, iclass 38, count 0 2006.173.21:14:24.50#ibcon#*after write, iclass 38, count 0 2006.173.21:14:24.50#ibcon#*before return 0, iclass 38, count 0 2006.173.21:14:24.50#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.21:14:24.50#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.21:14:24.50#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.21:14:24.50#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.21:14:24.50$vck44/valo=8,884.99 2006.173.21:14:24.50#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.21:14:24.50#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.21:14:24.50#ibcon#ireg 17 cls_cnt 0 2006.173.21:14:24.50#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.21:14:24.50#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.21:14:24.50#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.21:14:24.50#ibcon#enter wrdev, iclass 40, count 0 2006.173.21:14:24.50#ibcon#first serial, iclass 40, count 0 2006.173.21:14:24.50#ibcon#enter sib2, iclass 40, count 0 2006.173.21:14:24.50#ibcon#flushed, iclass 40, count 0 2006.173.21:14:24.50#ibcon#about to write, iclass 40, count 0 2006.173.21:14:24.50#ibcon#wrote, iclass 40, count 0 2006.173.21:14:24.50#ibcon#about to read 3, iclass 40, count 0 2006.173.21:14:24.52#ibcon#read 3, iclass 40, count 0 2006.173.21:14:24.52#ibcon#about to read 4, iclass 40, count 0 2006.173.21:14:24.52#ibcon#read 4, iclass 40, count 0 2006.173.21:14:24.52#ibcon#about to read 5, iclass 40, count 0 2006.173.21:14:24.52#ibcon#read 5, iclass 40, count 0 2006.173.21:14:24.52#ibcon#about to read 6, iclass 40, count 0 2006.173.21:14:24.52#ibcon#read 6, iclass 40, count 0 2006.173.21:14:24.52#ibcon#end of sib2, iclass 40, count 0 2006.173.21:14:24.52#ibcon#*mode == 0, iclass 40, count 0 2006.173.21:14:24.52#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.21:14:24.52#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.21:14:24.52#ibcon#*before write, iclass 40, count 0 2006.173.21:14:24.52#ibcon#enter sib2, iclass 40, count 0 2006.173.21:14:24.52#ibcon#flushed, iclass 40, count 0 2006.173.21:14:24.52#ibcon#about to write, iclass 40, count 0 2006.173.21:14:24.52#ibcon#wrote, iclass 40, count 0 2006.173.21:14:24.52#ibcon#about to read 3, iclass 40, count 0 2006.173.21:14:24.56#ibcon#read 3, iclass 40, count 0 2006.173.21:14:24.56#ibcon#about to read 4, iclass 40, count 0 2006.173.21:14:24.56#ibcon#read 4, iclass 40, count 0 2006.173.21:14:24.56#ibcon#about to read 5, iclass 40, count 0 2006.173.21:14:24.56#ibcon#read 5, iclass 40, count 0 2006.173.21:14:24.56#ibcon#about to read 6, iclass 40, count 0 2006.173.21:14:24.56#ibcon#read 6, iclass 40, count 0 2006.173.21:14:24.56#ibcon#end of sib2, iclass 40, count 0 2006.173.21:14:24.56#ibcon#*after write, iclass 40, count 0 2006.173.21:14:24.56#ibcon#*before return 0, iclass 40, count 0 2006.173.21:14:24.56#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.21:14:24.56#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.21:14:24.56#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.21:14:24.56#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.21:14:24.56$vck44/va=8,4 2006.173.21:14:24.56#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.21:14:24.56#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.21:14:24.56#ibcon#ireg 11 cls_cnt 2 2006.173.21:14:24.56#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.21:14:24.62#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.21:14:24.62#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.21:14:24.62#ibcon#enter wrdev, iclass 4, count 2 2006.173.21:14:24.62#ibcon#first serial, iclass 4, count 2 2006.173.21:14:24.62#ibcon#enter sib2, iclass 4, count 2 2006.173.21:14:24.62#ibcon#flushed, iclass 4, count 2 2006.173.21:14:24.62#ibcon#about to write, iclass 4, count 2 2006.173.21:14:24.62#ibcon#wrote, iclass 4, count 2 2006.173.21:14:24.62#ibcon#about to read 3, iclass 4, count 2 2006.173.21:14:24.64#ibcon#read 3, iclass 4, count 2 2006.173.21:14:24.64#ibcon#about to read 4, iclass 4, count 2 2006.173.21:14:24.64#ibcon#read 4, iclass 4, count 2 2006.173.21:14:24.64#ibcon#about to read 5, iclass 4, count 2 2006.173.21:14:24.64#ibcon#read 5, iclass 4, count 2 2006.173.21:14:24.64#ibcon#about to read 6, iclass 4, count 2 2006.173.21:14:24.64#ibcon#read 6, iclass 4, count 2 2006.173.21:14:24.64#ibcon#end of sib2, iclass 4, count 2 2006.173.21:14:24.64#ibcon#*mode == 0, iclass 4, count 2 2006.173.21:14:24.64#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.21:14:24.64#ibcon#[25=AT08-04\r\n] 2006.173.21:14:24.64#ibcon#*before write, iclass 4, count 2 2006.173.21:14:24.64#ibcon#enter sib2, iclass 4, count 2 2006.173.21:14:24.64#ibcon#flushed, iclass 4, count 2 2006.173.21:14:24.64#ibcon#about to write, iclass 4, count 2 2006.173.21:14:24.64#ibcon#wrote, iclass 4, count 2 2006.173.21:14:24.64#ibcon#about to read 3, iclass 4, count 2 2006.173.21:14:24.67#ibcon#read 3, iclass 4, count 2 2006.173.21:14:24.67#ibcon#about to read 4, iclass 4, count 2 2006.173.21:14:24.67#ibcon#read 4, iclass 4, count 2 2006.173.21:14:24.67#ibcon#about to read 5, iclass 4, count 2 2006.173.21:14:24.67#ibcon#read 5, iclass 4, count 2 2006.173.21:14:24.67#ibcon#about to read 6, iclass 4, count 2 2006.173.21:14:24.67#ibcon#read 6, iclass 4, count 2 2006.173.21:14:24.67#ibcon#end of sib2, iclass 4, count 2 2006.173.21:14:24.67#ibcon#*after write, iclass 4, count 2 2006.173.21:14:24.67#ibcon#*before return 0, iclass 4, count 2 2006.173.21:14:24.67#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.21:14:24.67#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.21:14:24.67#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.21:14:24.67#ibcon#ireg 7 cls_cnt 0 2006.173.21:14:24.67#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.21:14:24.79#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.21:14:24.79#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.21:14:24.79#ibcon#enter wrdev, iclass 4, count 0 2006.173.21:14:24.79#ibcon#first serial, iclass 4, count 0 2006.173.21:14:24.79#ibcon#enter sib2, iclass 4, count 0 2006.173.21:14:24.79#ibcon#flushed, iclass 4, count 0 2006.173.21:14:24.79#ibcon#about to write, iclass 4, count 0 2006.173.21:14:24.79#ibcon#wrote, iclass 4, count 0 2006.173.21:14:24.79#ibcon#about to read 3, iclass 4, count 0 2006.173.21:14:24.81#ibcon#read 3, iclass 4, count 0 2006.173.21:14:24.81#ibcon#about to read 4, iclass 4, count 0 2006.173.21:14:24.81#ibcon#read 4, iclass 4, count 0 2006.173.21:14:24.81#ibcon#about to read 5, iclass 4, count 0 2006.173.21:14:24.81#ibcon#read 5, iclass 4, count 0 2006.173.21:14:24.81#ibcon#about to read 6, iclass 4, count 0 2006.173.21:14:24.81#ibcon#read 6, iclass 4, count 0 2006.173.21:14:24.81#ibcon#end of sib2, iclass 4, count 0 2006.173.21:14:24.81#ibcon#*mode == 0, iclass 4, count 0 2006.173.21:14:24.81#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.21:14:24.81#ibcon#[25=USB\r\n] 2006.173.21:14:24.81#ibcon#*before write, iclass 4, count 0 2006.173.21:14:24.81#ibcon#enter sib2, iclass 4, count 0 2006.173.21:14:24.81#ibcon#flushed, iclass 4, count 0 2006.173.21:14:24.81#ibcon#about to write, iclass 4, count 0 2006.173.21:14:24.81#ibcon#wrote, iclass 4, count 0 2006.173.21:14:24.81#ibcon#about to read 3, iclass 4, count 0 2006.173.21:14:24.84#ibcon#read 3, iclass 4, count 0 2006.173.21:14:24.84#ibcon#about to read 4, iclass 4, count 0 2006.173.21:14:24.84#ibcon#read 4, iclass 4, count 0 2006.173.21:14:24.84#ibcon#about to read 5, iclass 4, count 0 2006.173.21:14:24.84#ibcon#read 5, iclass 4, count 0 2006.173.21:14:24.84#ibcon#about to read 6, iclass 4, count 0 2006.173.21:14:24.84#ibcon#read 6, iclass 4, count 0 2006.173.21:14:24.84#ibcon#end of sib2, iclass 4, count 0 2006.173.21:14:24.84#ibcon#*after write, iclass 4, count 0 2006.173.21:14:24.84#ibcon#*before return 0, iclass 4, count 0 2006.173.21:14:24.84#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.21:14:24.84#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.21:14:24.84#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.21:14:24.84#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.21:14:24.84$vck44/vblo=1,629.99 2006.173.21:14:24.84#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.21:14:24.84#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.21:14:24.84#ibcon#ireg 17 cls_cnt 0 2006.173.21:14:24.84#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.21:14:24.84#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.21:14:24.84#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.21:14:24.84#ibcon#enter wrdev, iclass 6, count 0 2006.173.21:14:24.84#ibcon#first serial, iclass 6, count 0 2006.173.21:14:24.84#ibcon#enter sib2, iclass 6, count 0 2006.173.21:14:24.84#ibcon#flushed, iclass 6, count 0 2006.173.21:14:24.84#ibcon#about to write, iclass 6, count 0 2006.173.21:14:24.84#ibcon#wrote, iclass 6, count 0 2006.173.21:14:24.84#ibcon#about to read 3, iclass 6, count 0 2006.173.21:14:24.86#ibcon#read 3, iclass 6, count 0 2006.173.21:14:24.86#ibcon#about to read 4, iclass 6, count 0 2006.173.21:14:24.86#ibcon#read 4, iclass 6, count 0 2006.173.21:14:24.86#ibcon#about to read 5, iclass 6, count 0 2006.173.21:14:24.86#ibcon#read 5, iclass 6, count 0 2006.173.21:14:24.86#ibcon#about to read 6, iclass 6, count 0 2006.173.21:14:24.86#ibcon#read 6, iclass 6, count 0 2006.173.21:14:24.86#ibcon#end of sib2, iclass 6, count 0 2006.173.21:14:24.86#ibcon#*mode == 0, iclass 6, count 0 2006.173.21:14:24.86#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.21:14:24.86#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.21:14:24.86#ibcon#*before write, iclass 6, count 0 2006.173.21:14:24.86#ibcon#enter sib2, iclass 6, count 0 2006.173.21:14:24.86#ibcon#flushed, iclass 6, count 0 2006.173.21:14:24.86#ibcon#about to write, iclass 6, count 0 2006.173.21:14:24.86#ibcon#wrote, iclass 6, count 0 2006.173.21:14:24.86#ibcon#about to read 3, iclass 6, count 0 2006.173.21:14:24.90#ibcon#read 3, iclass 6, count 0 2006.173.21:14:24.90#ibcon#about to read 4, iclass 6, count 0 2006.173.21:14:24.90#ibcon#read 4, iclass 6, count 0 2006.173.21:14:24.90#ibcon#about to read 5, iclass 6, count 0 2006.173.21:14:24.90#ibcon#read 5, iclass 6, count 0 2006.173.21:14:24.90#ibcon#about to read 6, iclass 6, count 0 2006.173.21:14:24.90#ibcon#read 6, iclass 6, count 0 2006.173.21:14:24.90#ibcon#end of sib2, iclass 6, count 0 2006.173.21:14:24.90#ibcon#*after write, iclass 6, count 0 2006.173.21:14:24.90#ibcon#*before return 0, iclass 6, count 0 2006.173.21:14:24.90#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.21:14:24.90#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.21:14:24.90#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.21:14:24.90#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.21:14:24.90$vck44/vb=1,4 2006.173.21:14:24.90#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.21:14:24.90#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.21:14:24.90#ibcon#ireg 11 cls_cnt 2 2006.173.21:14:24.90#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.21:14:24.90#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.21:14:24.90#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.21:14:24.90#ibcon#enter wrdev, iclass 10, count 2 2006.173.21:14:24.90#ibcon#first serial, iclass 10, count 2 2006.173.21:14:24.90#ibcon#enter sib2, iclass 10, count 2 2006.173.21:14:24.90#ibcon#flushed, iclass 10, count 2 2006.173.21:14:24.90#ibcon#about to write, iclass 10, count 2 2006.173.21:14:24.90#ibcon#wrote, iclass 10, count 2 2006.173.21:14:24.90#ibcon#about to read 3, iclass 10, count 2 2006.173.21:14:24.92#ibcon#read 3, iclass 10, count 2 2006.173.21:14:24.92#ibcon#about to read 4, iclass 10, count 2 2006.173.21:14:24.92#ibcon#read 4, iclass 10, count 2 2006.173.21:14:24.92#ibcon#about to read 5, iclass 10, count 2 2006.173.21:14:24.92#ibcon#read 5, iclass 10, count 2 2006.173.21:14:24.92#ibcon#about to read 6, iclass 10, count 2 2006.173.21:14:24.92#ibcon#read 6, iclass 10, count 2 2006.173.21:14:24.92#ibcon#end of sib2, iclass 10, count 2 2006.173.21:14:24.92#ibcon#*mode == 0, iclass 10, count 2 2006.173.21:14:24.92#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.21:14:24.92#ibcon#[27=AT01-04\r\n] 2006.173.21:14:24.92#ibcon#*before write, iclass 10, count 2 2006.173.21:14:24.92#ibcon#enter sib2, iclass 10, count 2 2006.173.21:14:24.92#ibcon#flushed, iclass 10, count 2 2006.173.21:14:24.92#ibcon#about to write, iclass 10, count 2 2006.173.21:14:24.92#ibcon#wrote, iclass 10, count 2 2006.173.21:14:24.92#ibcon#about to read 3, iclass 10, count 2 2006.173.21:14:24.95#ibcon#read 3, iclass 10, count 2 2006.173.21:14:24.95#ibcon#about to read 4, iclass 10, count 2 2006.173.21:14:24.95#ibcon#read 4, iclass 10, count 2 2006.173.21:14:24.95#ibcon#about to read 5, iclass 10, count 2 2006.173.21:14:24.95#ibcon#read 5, iclass 10, count 2 2006.173.21:14:24.95#ibcon#about to read 6, iclass 10, count 2 2006.173.21:14:24.95#ibcon#read 6, iclass 10, count 2 2006.173.21:14:24.95#ibcon#end of sib2, iclass 10, count 2 2006.173.21:14:24.95#ibcon#*after write, iclass 10, count 2 2006.173.21:14:24.95#ibcon#*before return 0, iclass 10, count 2 2006.173.21:14:24.95#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.21:14:24.95#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.21:14:24.95#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.21:14:24.95#ibcon#ireg 7 cls_cnt 0 2006.173.21:14:24.95#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.21:14:25.07#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.21:14:25.07#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.21:14:25.07#ibcon#enter wrdev, iclass 10, count 0 2006.173.21:14:25.07#ibcon#first serial, iclass 10, count 0 2006.173.21:14:25.07#ibcon#enter sib2, iclass 10, count 0 2006.173.21:14:25.07#ibcon#flushed, iclass 10, count 0 2006.173.21:14:25.07#ibcon#about to write, iclass 10, count 0 2006.173.21:14:25.07#ibcon#wrote, iclass 10, count 0 2006.173.21:14:25.07#ibcon#about to read 3, iclass 10, count 0 2006.173.21:14:25.09#ibcon#read 3, iclass 10, count 0 2006.173.21:14:25.09#ibcon#about to read 4, iclass 10, count 0 2006.173.21:14:25.09#ibcon#read 4, iclass 10, count 0 2006.173.21:14:25.09#ibcon#about to read 5, iclass 10, count 0 2006.173.21:14:25.09#ibcon#read 5, iclass 10, count 0 2006.173.21:14:25.09#ibcon#about to read 6, iclass 10, count 0 2006.173.21:14:25.09#ibcon#read 6, iclass 10, count 0 2006.173.21:14:25.09#ibcon#end of sib2, iclass 10, count 0 2006.173.21:14:25.09#ibcon#*mode == 0, iclass 10, count 0 2006.173.21:14:25.09#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.21:14:25.09#ibcon#[27=USB\r\n] 2006.173.21:14:25.09#ibcon#*before write, iclass 10, count 0 2006.173.21:14:25.09#ibcon#enter sib2, iclass 10, count 0 2006.173.21:14:25.09#ibcon#flushed, iclass 10, count 0 2006.173.21:14:25.09#ibcon#about to write, iclass 10, count 0 2006.173.21:14:25.09#ibcon#wrote, iclass 10, count 0 2006.173.21:14:25.09#ibcon#about to read 3, iclass 10, count 0 2006.173.21:14:25.12#ibcon#read 3, iclass 10, count 0 2006.173.21:14:25.12#ibcon#about to read 4, iclass 10, count 0 2006.173.21:14:25.12#ibcon#read 4, iclass 10, count 0 2006.173.21:14:25.12#ibcon#about to read 5, iclass 10, count 0 2006.173.21:14:25.12#ibcon#read 5, iclass 10, count 0 2006.173.21:14:25.12#ibcon#about to read 6, iclass 10, count 0 2006.173.21:14:25.12#ibcon#read 6, iclass 10, count 0 2006.173.21:14:25.12#ibcon#end of sib2, iclass 10, count 0 2006.173.21:14:25.12#ibcon#*after write, iclass 10, count 0 2006.173.21:14:25.12#ibcon#*before return 0, iclass 10, count 0 2006.173.21:14:25.12#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.21:14:25.12#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.21:14:25.12#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.21:14:25.12#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.21:14:25.12$vck44/vblo=2,634.99 2006.173.21:14:25.12#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.21:14:25.12#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.21:14:25.12#ibcon#ireg 17 cls_cnt 0 2006.173.21:14:25.12#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.21:14:25.12#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.21:14:25.12#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.21:14:25.12#ibcon#enter wrdev, iclass 12, count 0 2006.173.21:14:25.12#ibcon#first serial, iclass 12, count 0 2006.173.21:14:25.12#ibcon#enter sib2, iclass 12, count 0 2006.173.21:14:25.12#ibcon#flushed, iclass 12, count 0 2006.173.21:14:25.12#ibcon#about to write, iclass 12, count 0 2006.173.21:14:25.12#ibcon#wrote, iclass 12, count 0 2006.173.21:14:25.12#ibcon#about to read 3, iclass 12, count 0 2006.173.21:14:25.14#ibcon#read 3, iclass 12, count 0 2006.173.21:14:25.14#ibcon#about to read 4, iclass 12, count 0 2006.173.21:14:25.14#ibcon#read 4, iclass 12, count 0 2006.173.21:14:25.14#ibcon#about to read 5, iclass 12, count 0 2006.173.21:14:25.14#ibcon#read 5, iclass 12, count 0 2006.173.21:14:25.14#ibcon#about to read 6, iclass 12, count 0 2006.173.21:14:25.14#ibcon#read 6, iclass 12, count 0 2006.173.21:14:25.14#ibcon#end of sib2, iclass 12, count 0 2006.173.21:14:25.14#ibcon#*mode == 0, iclass 12, count 0 2006.173.21:14:25.14#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.21:14:25.14#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.21:14:25.14#ibcon#*before write, iclass 12, count 0 2006.173.21:14:25.14#ibcon#enter sib2, iclass 12, count 0 2006.173.21:14:25.14#ibcon#flushed, iclass 12, count 0 2006.173.21:14:25.14#ibcon#about to write, iclass 12, count 0 2006.173.21:14:25.14#ibcon#wrote, iclass 12, count 0 2006.173.21:14:25.14#ibcon#about to read 3, iclass 12, count 0 2006.173.21:14:25.18#ibcon#read 3, iclass 12, count 0 2006.173.21:14:25.18#ibcon#about to read 4, iclass 12, count 0 2006.173.21:14:25.18#ibcon#read 4, iclass 12, count 0 2006.173.21:14:25.18#ibcon#about to read 5, iclass 12, count 0 2006.173.21:14:25.18#ibcon#read 5, iclass 12, count 0 2006.173.21:14:25.18#ibcon#about to read 6, iclass 12, count 0 2006.173.21:14:25.18#ibcon#read 6, iclass 12, count 0 2006.173.21:14:25.18#ibcon#end of sib2, iclass 12, count 0 2006.173.21:14:25.18#ibcon#*after write, iclass 12, count 0 2006.173.21:14:25.18#ibcon#*before return 0, iclass 12, count 0 2006.173.21:14:25.18#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.21:14:25.18#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.21:14:25.18#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.21:14:25.18#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.21:14:25.18$vck44/vb=2,4 2006.173.21:14:25.18#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.21:14:25.18#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.21:14:25.18#ibcon#ireg 11 cls_cnt 2 2006.173.21:14:25.18#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.21:14:25.24#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.21:14:25.24#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.21:14:25.24#ibcon#enter wrdev, iclass 14, count 2 2006.173.21:14:25.24#ibcon#first serial, iclass 14, count 2 2006.173.21:14:25.24#ibcon#enter sib2, iclass 14, count 2 2006.173.21:14:25.24#ibcon#flushed, iclass 14, count 2 2006.173.21:14:25.24#ibcon#about to write, iclass 14, count 2 2006.173.21:14:25.24#ibcon#wrote, iclass 14, count 2 2006.173.21:14:25.24#ibcon#about to read 3, iclass 14, count 2 2006.173.21:14:25.26#ibcon#read 3, iclass 14, count 2 2006.173.21:14:25.26#ibcon#about to read 4, iclass 14, count 2 2006.173.21:14:25.26#ibcon#read 4, iclass 14, count 2 2006.173.21:14:25.26#ibcon#about to read 5, iclass 14, count 2 2006.173.21:14:25.26#ibcon#read 5, iclass 14, count 2 2006.173.21:14:25.26#ibcon#about to read 6, iclass 14, count 2 2006.173.21:14:25.26#ibcon#read 6, iclass 14, count 2 2006.173.21:14:25.26#ibcon#end of sib2, iclass 14, count 2 2006.173.21:14:25.26#ibcon#*mode == 0, iclass 14, count 2 2006.173.21:14:25.26#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.21:14:25.26#ibcon#[27=AT02-04\r\n] 2006.173.21:14:25.26#ibcon#*before write, iclass 14, count 2 2006.173.21:14:25.26#ibcon#enter sib2, iclass 14, count 2 2006.173.21:14:25.26#ibcon#flushed, iclass 14, count 2 2006.173.21:14:25.26#ibcon#about to write, iclass 14, count 2 2006.173.21:14:25.26#ibcon#wrote, iclass 14, count 2 2006.173.21:14:25.26#ibcon#about to read 3, iclass 14, count 2 2006.173.21:14:25.29#ibcon#read 3, iclass 14, count 2 2006.173.21:14:25.29#ibcon#about to read 4, iclass 14, count 2 2006.173.21:14:25.29#ibcon#read 4, iclass 14, count 2 2006.173.21:14:25.29#ibcon#about to read 5, iclass 14, count 2 2006.173.21:14:25.29#ibcon#read 5, iclass 14, count 2 2006.173.21:14:25.29#ibcon#about to read 6, iclass 14, count 2 2006.173.21:14:25.29#ibcon#read 6, iclass 14, count 2 2006.173.21:14:25.29#ibcon#end of sib2, iclass 14, count 2 2006.173.21:14:25.29#ibcon#*after write, iclass 14, count 2 2006.173.21:14:25.29#ibcon#*before return 0, iclass 14, count 2 2006.173.21:14:25.29#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.21:14:25.29#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.21:14:25.29#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.21:14:25.29#ibcon#ireg 7 cls_cnt 0 2006.173.21:14:25.29#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.21:14:25.41#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.21:14:25.41#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.21:14:25.41#ibcon#enter wrdev, iclass 14, count 0 2006.173.21:14:25.41#ibcon#first serial, iclass 14, count 0 2006.173.21:14:25.41#ibcon#enter sib2, iclass 14, count 0 2006.173.21:14:25.41#ibcon#flushed, iclass 14, count 0 2006.173.21:14:25.41#ibcon#about to write, iclass 14, count 0 2006.173.21:14:25.41#ibcon#wrote, iclass 14, count 0 2006.173.21:14:25.41#ibcon#about to read 3, iclass 14, count 0 2006.173.21:14:25.43#ibcon#read 3, iclass 14, count 0 2006.173.21:14:25.43#ibcon#about to read 4, iclass 14, count 0 2006.173.21:14:25.43#ibcon#read 4, iclass 14, count 0 2006.173.21:14:25.43#ibcon#about to read 5, iclass 14, count 0 2006.173.21:14:25.43#ibcon#read 5, iclass 14, count 0 2006.173.21:14:25.43#ibcon#about to read 6, iclass 14, count 0 2006.173.21:14:25.43#ibcon#read 6, iclass 14, count 0 2006.173.21:14:25.43#ibcon#end of sib2, iclass 14, count 0 2006.173.21:14:25.43#ibcon#*mode == 0, iclass 14, count 0 2006.173.21:14:25.43#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.21:14:25.43#ibcon#[27=USB\r\n] 2006.173.21:14:25.43#ibcon#*before write, iclass 14, count 0 2006.173.21:14:25.43#ibcon#enter sib2, iclass 14, count 0 2006.173.21:14:25.43#ibcon#flushed, iclass 14, count 0 2006.173.21:14:25.43#ibcon#about to write, iclass 14, count 0 2006.173.21:14:25.43#ibcon#wrote, iclass 14, count 0 2006.173.21:14:25.43#ibcon#about to read 3, iclass 14, count 0 2006.173.21:14:25.46#ibcon#read 3, iclass 14, count 0 2006.173.21:14:25.46#ibcon#about to read 4, iclass 14, count 0 2006.173.21:14:25.46#ibcon#read 4, iclass 14, count 0 2006.173.21:14:25.46#ibcon#about to read 5, iclass 14, count 0 2006.173.21:14:25.46#ibcon#read 5, iclass 14, count 0 2006.173.21:14:25.46#ibcon#about to read 6, iclass 14, count 0 2006.173.21:14:25.46#ibcon#read 6, iclass 14, count 0 2006.173.21:14:25.46#ibcon#end of sib2, iclass 14, count 0 2006.173.21:14:25.46#ibcon#*after write, iclass 14, count 0 2006.173.21:14:25.46#ibcon#*before return 0, iclass 14, count 0 2006.173.21:14:25.46#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.21:14:25.46#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.21:14:25.46#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.21:14:25.46#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.21:14:25.46$vck44/vblo=3,649.99 2006.173.21:14:25.46#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.21:14:25.46#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.21:14:25.46#ibcon#ireg 17 cls_cnt 0 2006.173.21:14:25.46#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.21:14:25.46#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.21:14:25.46#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.21:14:25.46#ibcon#enter wrdev, iclass 16, count 0 2006.173.21:14:25.46#ibcon#first serial, iclass 16, count 0 2006.173.21:14:25.46#ibcon#enter sib2, iclass 16, count 0 2006.173.21:14:25.46#ibcon#flushed, iclass 16, count 0 2006.173.21:14:25.46#ibcon#about to write, iclass 16, count 0 2006.173.21:14:25.46#ibcon#wrote, iclass 16, count 0 2006.173.21:14:25.46#ibcon#about to read 3, iclass 16, count 0 2006.173.21:14:25.48#ibcon#read 3, iclass 16, count 0 2006.173.21:14:25.48#ibcon#about to read 4, iclass 16, count 0 2006.173.21:14:25.48#ibcon#read 4, iclass 16, count 0 2006.173.21:14:25.48#ibcon#about to read 5, iclass 16, count 0 2006.173.21:14:25.48#ibcon#read 5, iclass 16, count 0 2006.173.21:14:25.48#ibcon#about to read 6, iclass 16, count 0 2006.173.21:14:25.48#ibcon#read 6, iclass 16, count 0 2006.173.21:14:25.48#ibcon#end of sib2, iclass 16, count 0 2006.173.21:14:25.48#ibcon#*mode == 0, iclass 16, count 0 2006.173.21:14:25.48#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.21:14:25.48#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.21:14:25.48#ibcon#*before write, iclass 16, count 0 2006.173.21:14:25.48#ibcon#enter sib2, iclass 16, count 0 2006.173.21:14:25.48#ibcon#flushed, iclass 16, count 0 2006.173.21:14:25.48#ibcon#about to write, iclass 16, count 0 2006.173.21:14:25.48#ibcon#wrote, iclass 16, count 0 2006.173.21:14:25.48#ibcon#about to read 3, iclass 16, count 0 2006.173.21:14:25.52#ibcon#read 3, iclass 16, count 0 2006.173.21:14:25.52#ibcon#about to read 4, iclass 16, count 0 2006.173.21:14:25.52#ibcon#read 4, iclass 16, count 0 2006.173.21:14:25.52#ibcon#about to read 5, iclass 16, count 0 2006.173.21:14:25.52#ibcon#read 5, iclass 16, count 0 2006.173.21:14:25.52#ibcon#about to read 6, iclass 16, count 0 2006.173.21:14:25.52#ibcon#read 6, iclass 16, count 0 2006.173.21:14:25.52#ibcon#end of sib2, iclass 16, count 0 2006.173.21:14:25.52#ibcon#*after write, iclass 16, count 0 2006.173.21:14:25.52#ibcon#*before return 0, iclass 16, count 0 2006.173.21:14:25.52#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.21:14:25.52#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.21:14:25.52#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.21:14:25.52#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.21:14:25.52$vck44/vb=3,4 2006.173.21:14:25.52#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.21:14:25.52#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.21:14:25.52#ibcon#ireg 11 cls_cnt 2 2006.173.21:14:25.52#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.21:14:25.58#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.21:14:25.58#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.21:14:25.58#ibcon#enter wrdev, iclass 18, count 2 2006.173.21:14:25.58#ibcon#first serial, iclass 18, count 2 2006.173.21:14:25.58#ibcon#enter sib2, iclass 18, count 2 2006.173.21:14:25.58#ibcon#flushed, iclass 18, count 2 2006.173.21:14:25.58#ibcon#about to write, iclass 18, count 2 2006.173.21:14:25.58#ibcon#wrote, iclass 18, count 2 2006.173.21:14:25.58#ibcon#about to read 3, iclass 18, count 2 2006.173.21:14:25.60#ibcon#read 3, iclass 18, count 2 2006.173.21:14:25.60#ibcon#about to read 4, iclass 18, count 2 2006.173.21:14:25.60#ibcon#read 4, iclass 18, count 2 2006.173.21:14:25.60#ibcon#about to read 5, iclass 18, count 2 2006.173.21:14:25.60#ibcon#read 5, iclass 18, count 2 2006.173.21:14:25.60#ibcon#about to read 6, iclass 18, count 2 2006.173.21:14:25.60#ibcon#read 6, iclass 18, count 2 2006.173.21:14:25.60#ibcon#end of sib2, iclass 18, count 2 2006.173.21:14:25.60#ibcon#*mode == 0, iclass 18, count 2 2006.173.21:14:25.60#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.21:14:25.60#ibcon#[27=AT03-04\r\n] 2006.173.21:14:25.60#ibcon#*before write, iclass 18, count 2 2006.173.21:14:25.60#ibcon#enter sib2, iclass 18, count 2 2006.173.21:14:25.60#ibcon#flushed, iclass 18, count 2 2006.173.21:14:25.60#ibcon#about to write, iclass 18, count 2 2006.173.21:14:25.60#ibcon#wrote, iclass 18, count 2 2006.173.21:14:25.60#ibcon#about to read 3, iclass 18, count 2 2006.173.21:14:25.63#ibcon#read 3, iclass 18, count 2 2006.173.21:14:25.63#ibcon#about to read 4, iclass 18, count 2 2006.173.21:14:25.63#ibcon#read 4, iclass 18, count 2 2006.173.21:14:25.63#ibcon#about to read 5, iclass 18, count 2 2006.173.21:14:25.63#ibcon#read 5, iclass 18, count 2 2006.173.21:14:25.63#ibcon#about to read 6, iclass 18, count 2 2006.173.21:14:25.63#ibcon#read 6, iclass 18, count 2 2006.173.21:14:25.63#ibcon#end of sib2, iclass 18, count 2 2006.173.21:14:25.63#ibcon#*after write, iclass 18, count 2 2006.173.21:14:25.63#ibcon#*before return 0, iclass 18, count 2 2006.173.21:14:25.63#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.21:14:25.63#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.21:14:25.63#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.21:14:25.63#ibcon#ireg 7 cls_cnt 0 2006.173.21:14:25.63#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.21:14:25.75#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.21:14:25.75#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.21:14:25.75#ibcon#enter wrdev, iclass 18, count 0 2006.173.21:14:25.75#ibcon#first serial, iclass 18, count 0 2006.173.21:14:25.75#ibcon#enter sib2, iclass 18, count 0 2006.173.21:14:25.75#ibcon#flushed, iclass 18, count 0 2006.173.21:14:25.75#ibcon#about to write, iclass 18, count 0 2006.173.21:14:25.75#ibcon#wrote, iclass 18, count 0 2006.173.21:14:25.75#ibcon#about to read 3, iclass 18, count 0 2006.173.21:14:25.77#ibcon#read 3, iclass 18, count 0 2006.173.21:14:25.77#ibcon#about to read 4, iclass 18, count 0 2006.173.21:14:25.77#ibcon#read 4, iclass 18, count 0 2006.173.21:14:25.77#ibcon#about to read 5, iclass 18, count 0 2006.173.21:14:25.77#ibcon#read 5, iclass 18, count 0 2006.173.21:14:25.77#ibcon#about to read 6, iclass 18, count 0 2006.173.21:14:25.77#ibcon#read 6, iclass 18, count 0 2006.173.21:14:25.77#ibcon#end of sib2, iclass 18, count 0 2006.173.21:14:25.77#ibcon#*mode == 0, iclass 18, count 0 2006.173.21:14:25.77#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.21:14:25.77#ibcon#[27=USB\r\n] 2006.173.21:14:25.77#ibcon#*before write, iclass 18, count 0 2006.173.21:14:25.77#ibcon#enter sib2, iclass 18, count 0 2006.173.21:14:25.77#ibcon#flushed, iclass 18, count 0 2006.173.21:14:25.77#ibcon#about to write, iclass 18, count 0 2006.173.21:14:25.77#ibcon#wrote, iclass 18, count 0 2006.173.21:14:25.77#ibcon#about to read 3, iclass 18, count 0 2006.173.21:14:25.80#ibcon#read 3, iclass 18, count 0 2006.173.21:14:25.80#ibcon#about to read 4, iclass 18, count 0 2006.173.21:14:25.80#ibcon#read 4, iclass 18, count 0 2006.173.21:14:25.80#ibcon#about to read 5, iclass 18, count 0 2006.173.21:14:25.80#ibcon#read 5, iclass 18, count 0 2006.173.21:14:25.80#ibcon#about to read 6, iclass 18, count 0 2006.173.21:14:25.80#ibcon#read 6, iclass 18, count 0 2006.173.21:14:25.80#ibcon#end of sib2, iclass 18, count 0 2006.173.21:14:25.80#ibcon#*after write, iclass 18, count 0 2006.173.21:14:25.80#ibcon#*before return 0, iclass 18, count 0 2006.173.21:14:25.80#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.21:14:25.80#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.21:14:25.80#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.21:14:25.80#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.21:14:25.80$vck44/vblo=4,679.99 2006.173.21:14:25.80#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.21:14:25.80#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.21:14:25.80#ibcon#ireg 17 cls_cnt 0 2006.173.21:14:25.80#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.21:14:25.80#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.21:14:25.80#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.21:14:25.80#ibcon#enter wrdev, iclass 20, count 0 2006.173.21:14:25.80#ibcon#first serial, iclass 20, count 0 2006.173.21:14:25.80#ibcon#enter sib2, iclass 20, count 0 2006.173.21:14:25.80#ibcon#flushed, iclass 20, count 0 2006.173.21:14:25.80#ibcon#about to write, iclass 20, count 0 2006.173.21:14:25.80#ibcon#wrote, iclass 20, count 0 2006.173.21:14:25.80#ibcon#about to read 3, iclass 20, count 0 2006.173.21:14:25.82#ibcon#read 3, iclass 20, count 0 2006.173.21:14:25.82#ibcon#about to read 4, iclass 20, count 0 2006.173.21:14:25.82#ibcon#read 4, iclass 20, count 0 2006.173.21:14:25.82#ibcon#about to read 5, iclass 20, count 0 2006.173.21:14:25.82#ibcon#read 5, iclass 20, count 0 2006.173.21:14:25.82#ibcon#about to read 6, iclass 20, count 0 2006.173.21:14:25.82#ibcon#read 6, iclass 20, count 0 2006.173.21:14:25.82#ibcon#end of sib2, iclass 20, count 0 2006.173.21:14:25.82#ibcon#*mode == 0, iclass 20, count 0 2006.173.21:14:25.82#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.21:14:25.82#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.21:14:25.82#ibcon#*before write, iclass 20, count 0 2006.173.21:14:25.82#ibcon#enter sib2, iclass 20, count 0 2006.173.21:14:25.82#ibcon#flushed, iclass 20, count 0 2006.173.21:14:25.82#ibcon#about to write, iclass 20, count 0 2006.173.21:14:25.82#ibcon#wrote, iclass 20, count 0 2006.173.21:14:25.82#ibcon#about to read 3, iclass 20, count 0 2006.173.21:14:25.86#ibcon#read 3, iclass 20, count 0 2006.173.21:14:25.86#ibcon#about to read 4, iclass 20, count 0 2006.173.21:14:25.86#ibcon#read 4, iclass 20, count 0 2006.173.21:14:25.86#ibcon#about to read 5, iclass 20, count 0 2006.173.21:14:25.86#ibcon#read 5, iclass 20, count 0 2006.173.21:14:25.86#ibcon#about to read 6, iclass 20, count 0 2006.173.21:14:25.86#ibcon#read 6, iclass 20, count 0 2006.173.21:14:25.86#ibcon#end of sib2, iclass 20, count 0 2006.173.21:14:25.86#ibcon#*after write, iclass 20, count 0 2006.173.21:14:25.86#ibcon#*before return 0, iclass 20, count 0 2006.173.21:14:25.86#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.21:14:25.86#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.21:14:25.86#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.21:14:25.86#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.21:14:25.86$vck44/vb=4,4 2006.173.21:14:25.86#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.21:14:25.86#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.21:14:25.86#ibcon#ireg 11 cls_cnt 2 2006.173.21:14:25.86#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.21:14:25.92#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.21:14:25.92#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.21:14:25.92#ibcon#enter wrdev, iclass 22, count 2 2006.173.21:14:25.92#ibcon#first serial, iclass 22, count 2 2006.173.21:14:25.92#ibcon#enter sib2, iclass 22, count 2 2006.173.21:14:25.92#ibcon#flushed, iclass 22, count 2 2006.173.21:14:25.92#ibcon#about to write, iclass 22, count 2 2006.173.21:14:25.92#ibcon#wrote, iclass 22, count 2 2006.173.21:14:25.92#ibcon#about to read 3, iclass 22, count 2 2006.173.21:14:25.94#ibcon#read 3, iclass 22, count 2 2006.173.21:14:25.94#ibcon#about to read 4, iclass 22, count 2 2006.173.21:14:25.94#ibcon#read 4, iclass 22, count 2 2006.173.21:14:25.94#ibcon#about to read 5, iclass 22, count 2 2006.173.21:14:25.94#ibcon#read 5, iclass 22, count 2 2006.173.21:14:25.94#ibcon#about to read 6, iclass 22, count 2 2006.173.21:14:25.94#ibcon#read 6, iclass 22, count 2 2006.173.21:14:25.94#ibcon#end of sib2, iclass 22, count 2 2006.173.21:14:25.94#ibcon#*mode == 0, iclass 22, count 2 2006.173.21:14:25.94#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.21:14:25.94#ibcon#[27=AT04-04\r\n] 2006.173.21:14:25.94#ibcon#*before write, iclass 22, count 2 2006.173.21:14:25.94#ibcon#enter sib2, iclass 22, count 2 2006.173.21:14:25.94#ibcon#flushed, iclass 22, count 2 2006.173.21:14:25.94#ibcon#about to write, iclass 22, count 2 2006.173.21:14:25.94#ibcon#wrote, iclass 22, count 2 2006.173.21:14:25.94#ibcon#about to read 3, iclass 22, count 2 2006.173.21:14:25.97#ibcon#read 3, iclass 22, count 2 2006.173.21:14:25.97#ibcon#about to read 4, iclass 22, count 2 2006.173.21:14:25.97#ibcon#read 4, iclass 22, count 2 2006.173.21:14:25.97#ibcon#about to read 5, iclass 22, count 2 2006.173.21:14:25.97#ibcon#read 5, iclass 22, count 2 2006.173.21:14:25.97#ibcon#about to read 6, iclass 22, count 2 2006.173.21:14:25.97#ibcon#read 6, iclass 22, count 2 2006.173.21:14:25.97#ibcon#end of sib2, iclass 22, count 2 2006.173.21:14:25.97#ibcon#*after write, iclass 22, count 2 2006.173.21:14:25.97#ibcon#*before return 0, iclass 22, count 2 2006.173.21:14:25.97#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.21:14:25.97#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.21:14:25.97#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.21:14:25.97#ibcon#ireg 7 cls_cnt 0 2006.173.21:14:25.97#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.21:14:26.09#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.21:14:26.09#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.21:14:26.09#ibcon#enter wrdev, iclass 22, count 0 2006.173.21:14:26.09#ibcon#first serial, iclass 22, count 0 2006.173.21:14:26.09#ibcon#enter sib2, iclass 22, count 0 2006.173.21:14:26.09#ibcon#flushed, iclass 22, count 0 2006.173.21:14:26.09#ibcon#about to write, iclass 22, count 0 2006.173.21:14:26.09#ibcon#wrote, iclass 22, count 0 2006.173.21:14:26.09#ibcon#about to read 3, iclass 22, count 0 2006.173.21:14:26.11#ibcon#read 3, iclass 22, count 0 2006.173.21:14:26.11#ibcon#about to read 4, iclass 22, count 0 2006.173.21:14:26.11#ibcon#read 4, iclass 22, count 0 2006.173.21:14:26.11#ibcon#about to read 5, iclass 22, count 0 2006.173.21:14:26.11#ibcon#read 5, iclass 22, count 0 2006.173.21:14:26.11#ibcon#about to read 6, iclass 22, count 0 2006.173.21:14:26.11#ibcon#read 6, iclass 22, count 0 2006.173.21:14:26.11#ibcon#end of sib2, iclass 22, count 0 2006.173.21:14:26.11#ibcon#*mode == 0, iclass 22, count 0 2006.173.21:14:26.11#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.21:14:26.11#ibcon#[27=USB\r\n] 2006.173.21:14:26.11#ibcon#*before write, iclass 22, count 0 2006.173.21:14:26.11#ibcon#enter sib2, iclass 22, count 0 2006.173.21:14:26.11#ibcon#flushed, iclass 22, count 0 2006.173.21:14:26.11#ibcon#about to write, iclass 22, count 0 2006.173.21:14:26.11#ibcon#wrote, iclass 22, count 0 2006.173.21:14:26.11#ibcon#about to read 3, iclass 22, count 0 2006.173.21:14:26.14#ibcon#read 3, iclass 22, count 0 2006.173.21:14:26.14#ibcon#about to read 4, iclass 22, count 0 2006.173.21:14:26.14#ibcon#read 4, iclass 22, count 0 2006.173.21:14:26.14#ibcon#about to read 5, iclass 22, count 0 2006.173.21:14:26.14#ibcon#read 5, iclass 22, count 0 2006.173.21:14:26.14#ibcon#about to read 6, iclass 22, count 0 2006.173.21:14:26.14#ibcon#read 6, iclass 22, count 0 2006.173.21:14:26.14#ibcon#end of sib2, iclass 22, count 0 2006.173.21:14:26.14#ibcon#*after write, iclass 22, count 0 2006.173.21:14:26.14#ibcon#*before return 0, iclass 22, count 0 2006.173.21:14:26.14#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.21:14:26.14#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.21:14:26.14#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.21:14:26.14#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.21:14:26.14$vck44/vblo=5,709.99 2006.173.21:14:26.14#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.21:14:26.14#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.21:14:26.14#ibcon#ireg 17 cls_cnt 0 2006.173.21:14:26.14#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.21:14:26.14#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.21:14:26.14#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.21:14:26.14#ibcon#enter wrdev, iclass 24, count 0 2006.173.21:14:26.14#ibcon#first serial, iclass 24, count 0 2006.173.21:14:26.14#ibcon#enter sib2, iclass 24, count 0 2006.173.21:14:26.14#ibcon#flushed, iclass 24, count 0 2006.173.21:14:26.14#ibcon#about to write, iclass 24, count 0 2006.173.21:14:26.14#ibcon#wrote, iclass 24, count 0 2006.173.21:14:26.14#ibcon#about to read 3, iclass 24, count 0 2006.173.21:14:26.16#ibcon#read 3, iclass 24, count 0 2006.173.21:14:26.16#ibcon#about to read 4, iclass 24, count 0 2006.173.21:14:26.16#ibcon#read 4, iclass 24, count 0 2006.173.21:14:26.16#ibcon#about to read 5, iclass 24, count 0 2006.173.21:14:26.16#ibcon#read 5, iclass 24, count 0 2006.173.21:14:26.16#ibcon#about to read 6, iclass 24, count 0 2006.173.21:14:26.16#ibcon#read 6, iclass 24, count 0 2006.173.21:14:26.16#ibcon#end of sib2, iclass 24, count 0 2006.173.21:14:26.16#ibcon#*mode == 0, iclass 24, count 0 2006.173.21:14:26.16#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.21:14:26.16#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.21:14:26.16#ibcon#*before write, iclass 24, count 0 2006.173.21:14:26.16#ibcon#enter sib2, iclass 24, count 0 2006.173.21:14:26.16#ibcon#flushed, iclass 24, count 0 2006.173.21:14:26.16#ibcon#about to write, iclass 24, count 0 2006.173.21:14:26.16#ibcon#wrote, iclass 24, count 0 2006.173.21:14:26.16#ibcon#about to read 3, iclass 24, count 0 2006.173.21:14:26.20#ibcon#read 3, iclass 24, count 0 2006.173.21:14:26.20#ibcon#about to read 4, iclass 24, count 0 2006.173.21:14:26.20#ibcon#read 4, iclass 24, count 0 2006.173.21:14:26.20#ibcon#about to read 5, iclass 24, count 0 2006.173.21:14:26.20#ibcon#read 5, iclass 24, count 0 2006.173.21:14:26.20#ibcon#about to read 6, iclass 24, count 0 2006.173.21:14:26.20#ibcon#read 6, iclass 24, count 0 2006.173.21:14:26.20#ibcon#end of sib2, iclass 24, count 0 2006.173.21:14:26.20#ibcon#*after write, iclass 24, count 0 2006.173.21:14:26.20#ibcon#*before return 0, iclass 24, count 0 2006.173.21:14:26.20#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.21:14:26.20#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.21:14:26.20#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.21:14:26.20#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.21:14:26.20$vck44/vb=5,4 2006.173.21:14:26.20#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.21:14:26.20#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.21:14:26.20#ibcon#ireg 11 cls_cnt 2 2006.173.21:14:26.20#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.21:14:26.26#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.21:14:26.26#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.21:14:26.26#ibcon#enter wrdev, iclass 26, count 2 2006.173.21:14:26.26#ibcon#first serial, iclass 26, count 2 2006.173.21:14:26.26#ibcon#enter sib2, iclass 26, count 2 2006.173.21:14:26.26#ibcon#flushed, iclass 26, count 2 2006.173.21:14:26.26#ibcon#about to write, iclass 26, count 2 2006.173.21:14:26.26#ibcon#wrote, iclass 26, count 2 2006.173.21:14:26.26#ibcon#about to read 3, iclass 26, count 2 2006.173.21:14:26.28#ibcon#read 3, iclass 26, count 2 2006.173.21:14:26.28#ibcon#about to read 4, iclass 26, count 2 2006.173.21:14:26.28#ibcon#read 4, iclass 26, count 2 2006.173.21:14:26.28#ibcon#about to read 5, iclass 26, count 2 2006.173.21:14:26.28#ibcon#read 5, iclass 26, count 2 2006.173.21:14:26.28#ibcon#about to read 6, iclass 26, count 2 2006.173.21:14:26.28#ibcon#read 6, iclass 26, count 2 2006.173.21:14:26.28#ibcon#end of sib2, iclass 26, count 2 2006.173.21:14:26.28#ibcon#*mode == 0, iclass 26, count 2 2006.173.21:14:26.28#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.21:14:26.28#ibcon#[27=AT05-04\r\n] 2006.173.21:14:26.28#ibcon#*before write, iclass 26, count 2 2006.173.21:14:26.28#ibcon#enter sib2, iclass 26, count 2 2006.173.21:14:26.28#ibcon#flushed, iclass 26, count 2 2006.173.21:14:26.28#ibcon#about to write, iclass 26, count 2 2006.173.21:14:26.28#ibcon#wrote, iclass 26, count 2 2006.173.21:14:26.28#ibcon#about to read 3, iclass 26, count 2 2006.173.21:14:26.31#ibcon#read 3, iclass 26, count 2 2006.173.21:14:26.31#ibcon#about to read 4, iclass 26, count 2 2006.173.21:14:26.31#ibcon#read 4, iclass 26, count 2 2006.173.21:14:26.31#ibcon#about to read 5, iclass 26, count 2 2006.173.21:14:26.31#ibcon#read 5, iclass 26, count 2 2006.173.21:14:26.31#ibcon#about to read 6, iclass 26, count 2 2006.173.21:14:26.31#ibcon#read 6, iclass 26, count 2 2006.173.21:14:26.31#ibcon#end of sib2, iclass 26, count 2 2006.173.21:14:26.31#ibcon#*after write, iclass 26, count 2 2006.173.21:14:26.31#ibcon#*before return 0, iclass 26, count 2 2006.173.21:14:26.31#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.21:14:26.31#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.21:14:26.31#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.21:14:26.31#ibcon#ireg 7 cls_cnt 0 2006.173.21:14:26.31#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.21:14:26.43#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.21:14:26.43#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.21:14:26.43#ibcon#enter wrdev, iclass 26, count 0 2006.173.21:14:26.43#ibcon#first serial, iclass 26, count 0 2006.173.21:14:26.43#ibcon#enter sib2, iclass 26, count 0 2006.173.21:14:26.43#ibcon#flushed, iclass 26, count 0 2006.173.21:14:26.43#ibcon#about to write, iclass 26, count 0 2006.173.21:14:26.43#ibcon#wrote, iclass 26, count 0 2006.173.21:14:26.43#ibcon#about to read 3, iclass 26, count 0 2006.173.21:14:26.45#ibcon#read 3, iclass 26, count 0 2006.173.21:14:26.45#ibcon#about to read 4, iclass 26, count 0 2006.173.21:14:26.45#ibcon#read 4, iclass 26, count 0 2006.173.21:14:26.45#ibcon#about to read 5, iclass 26, count 0 2006.173.21:14:26.45#ibcon#read 5, iclass 26, count 0 2006.173.21:14:26.45#ibcon#about to read 6, iclass 26, count 0 2006.173.21:14:26.45#ibcon#read 6, iclass 26, count 0 2006.173.21:14:26.45#ibcon#end of sib2, iclass 26, count 0 2006.173.21:14:26.45#ibcon#*mode == 0, iclass 26, count 0 2006.173.21:14:26.45#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.21:14:26.45#ibcon#[27=USB\r\n] 2006.173.21:14:26.45#ibcon#*before write, iclass 26, count 0 2006.173.21:14:26.45#ibcon#enter sib2, iclass 26, count 0 2006.173.21:14:26.45#ibcon#flushed, iclass 26, count 0 2006.173.21:14:26.45#ibcon#about to write, iclass 26, count 0 2006.173.21:14:26.45#ibcon#wrote, iclass 26, count 0 2006.173.21:14:26.45#ibcon#about to read 3, iclass 26, count 0 2006.173.21:14:26.48#ibcon#read 3, iclass 26, count 0 2006.173.21:14:26.48#ibcon#about to read 4, iclass 26, count 0 2006.173.21:14:26.48#ibcon#read 4, iclass 26, count 0 2006.173.21:14:26.48#ibcon#about to read 5, iclass 26, count 0 2006.173.21:14:26.48#ibcon#read 5, iclass 26, count 0 2006.173.21:14:26.48#ibcon#about to read 6, iclass 26, count 0 2006.173.21:14:26.48#ibcon#read 6, iclass 26, count 0 2006.173.21:14:26.48#ibcon#end of sib2, iclass 26, count 0 2006.173.21:14:26.48#ibcon#*after write, iclass 26, count 0 2006.173.21:14:26.48#ibcon#*before return 0, iclass 26, count 0 2006.173.21:14:26.48#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.21:14:26.48#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.21:14:26.48#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.21:14:26.48#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.21:14:26.48$vck44/vblo=6,719.99 2006.173.21:14:26.48#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.21:14:26.48#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.21:14:26.48#ibcon#ireg 17 cls_cnt 0 2006.173.21:14:26.48#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.21:14:26.48#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.21:14:26.48#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.21:14:26.48#ibcon#enter wrdev, iclass 28, count 0 2006.173.21:14:26.48#ibcon#first serial, iclass 28, count 0 2006.173.21:14:26.48#ibcon#enter sib2, iclass 28, count 0 2006.173.21:14:26.48#ibcon#flushed, iclass 28, count 0 2006.173.21:14:26.48#ibcon#about to write, iclass 28, count 0 2006.173.21:14:26.48#ibcon#wrote, iclass 28, count 0 2006.173.21:14:26.48#ibcon#about to read 3, iclass 28, count 0 2006.173.21:14:26.50#ibcon#read 3, iclass 28, count 0 2006.173.21:14:26.50#ibcon#about to read 4, iclass 28, count 0 2006.173.21:14:26.50#ibcon#read 4, iclass 28, count 0 2006.173.21:14:26.50#ibcon#about to read 5, iclass 28, count 0 2006.173.21:14:26.50#ibcon#read 5, iclass 28, count 0 2006.173.21:14:26.50#ibcon#about to read 6, iclass 28, count 0 2006.173.21:14:26.50#ibcon#read 6, iclass 28, count 0 2006.173.21:14:26.50#ibcon#end of sib2, iclass 28, count 0 2006.173.21:14:26.50#ibcon#*mode == 0, iclass 28, count 0 2006.173.21:14:26.50#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.21:14:26.50#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.21:14:26.50#ibcon#*before write, iclass 28, count 0 2006.173.21:14:26.50#ibcon#enter sib2, iclass 28, count 0 2006.173.21:14:26.50#ibcon#flushed, iclass 28, count 0 2006.173.21:14:26.50#ibcon#about to write, iclass 28, count 0 2006.173.21:14:26.50#ibcon#wrote, iclass 28, count 0 2006.173.21:14:26.50#ibcon#about to read 3, iclass 28, count 0 2006.173.21:14:26.54#ibcon#read 3, iclass 28, count 0 2006.173.21:14:26.54#ibcon#about to read 4, iclass 28, count 0 2006.173.21:14:26.54#ibcon#read 4, iclass 28, count 0 2006.173.21:14:26.54#ibcon#about to read 5, iclass 28, count 0 2006.173.21:14:26.54#ibcon#read 5, iclass 28, count 0 2006.173.21:14:26.54#ibcon#about to read 6, iclass 28, count 0 2006.173.21:14:26.54#ibcon#read 6, iclass 28, count 0 2006.173.21:14:26.54#ibcon#end of sib2, iclass 28, count 0 2006.173.21:14:26.54#ibcon#*after write, iclass 28, count 0 2006.173.21:14:26.54#ibcon#*before return 0, iclass 28, count 0 2006.173.21:14:26.54#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.21:14:26.54#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.21:14:26.54#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.21:14:26.54#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.21:14:26.54$vck44/vb=6,4 2006.173.21:14:26.54#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.21:14:26.54#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.21:14:26.54#ibcon#ireg 11 cls_cnt 2 2006.173.21:14:26.54#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.21:14:26.60#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.21:14:26.60#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.21:14:26.60#ibcon#enter wrdev, iclass 30, count 2 2006.173.21:14:26.60#ibcon#first serial, iclass 30, count 2 2006.173.21:14:26.60#ibcon#enter sib2, iclass 30, count 2 2006.173.21:14:26.60#ibcon#flushed, iclass 30, count 2 2006.173.21:14:26.60#ibcon#about to write, iclass 30, count 2 2006.173.21:14:26.60#ibcon#wrote, iclass 30, count 2 2006.173.21:14:26.60#ibcon#about to read 3, iclass 30, count 2 2006.173.21:14:26.62#ibcon#read 3, iclass 30, count 2 2006.173.21:14:26.62#ibcon#about to read 4, iclass 30, count 2 2006.173.21:14:26.62#ibcon#read 4, iclass 30, count 2 2006.173.21:14:26.62#ibcon#about to read 5, iclass 30, count 2 2006.173.21:14:26.62#ibcon#read 5, iclass 30, count 2 2006.173.21:14:26.62#ibcon#about to read 6, iclass 30, count 2 2006.173.21:14:26.62#ibcon#read 6, iclass 30, count 2 2006.173.21:14:26.62#ibcon#end of sib2, iclass 30, count 2 2006.173.21:14:26.62#ibcon#*mode == 0, iclass 30, count 2 2006.173.21:14:26.62#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.21:14:26.62#ibcon#[27=AT06-04\r\n] 2006.173.21:14:26.62#ibcon#*before write, iclass 30, count 2 2006.173.21:14:26.62#ibcon#enter sib2, iclass 30, count 2 2006.173.21:14:26.62#ibcon#flushed, iclass 30, count 2 2006.173.21:14:26.62#ibcon#about to write, iclass 30, count 2 2006.173.21:14:26.62#ibcon#wrote, iclass 30, count 2 2006.173.21:14:26.62#ibcon#about to read 3, iclass 30, count 2 2006.173.21:14:26.65#ibcon#read 3, iclass 30, count 2 2006.173.21:14:26.65#ibcon#about to read 4, iclass 30, count 2 2006.173.21:14:26.65#ibcon#read 4, iclass 30, count 2 2006.173.21:14:26.65#ibcon#about to read 5, iclass 30, count 2 2006.173.21:14:26.65#ibcon#read 5, iclass 30, count 2 2006.173.21:14:26.65#ibcon#about to read 6, iclass 30, count 2 2006.173.21:14:26.65#ibcon#read 6, iclass 30, count 2 2006.173.21:14:26.65#ibcon#end of sib2, iclass 30, count 2 2006.173.21:14:26.65#ibcon#*after write, iclass 30, count 2 2006.173.21:14:26.65#ibcon#*before return 0, iclass 30, count 2 2006.173.21:14:26.65#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.21:14:26.65#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.21:14:26.65#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.21:14:26.65#ibcon#ireg 7 cls_cnt 0 2006.173.21:14:26.65#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.21:14:26.77#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.21:14:26.77#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.21:14:26.77#ibcon#enter wrdev, iclass 30, count 0 2006.173.21:14:26.77#ibcon#first serial, iclass 30, count 0 2006.173.21:14:26.77#ibcon#enter sib2, iclass 30, count 0 2006.173.21:14:26.77#ibcon#flushed, iclass 30, count 0 2006.173.21:14:26.77#ibcon#about to write, iclass 30, count 0 2006.173.21:14:26.77#ibcon#wrote, iclass 30, count 0 2006.173.21:14:26.77#ibcon#about to read 3, iclass 30, count 0 2006.173.21:14:26.79#ibcon#read 3, iclass 30, count 0 2006.173.21:14:26.79#ibcon#about to read 4, iclass 30, count 0 2006.173.21:14:26.79#ibcon#read 4, iclass 30, count 0 2006.173.21:14:26.79#ibcon#about to read 5, iclass 30, count 0 2006.173.21:14:26.79#ibcon#read 5, iclass 30, count 0 2006.173.21:14:26.79#ibcon#about to read 6, iclass 30, count 0 2006.173.21:14:26.79#ibcon#read 6, iclass 30, count 0 2006.173.21:14:26.79#ibcon#end of sib2, iclass 30, count 0 2006.173.21:14:26.79#ibcon#*mode == 0, iclass 30, count 0 2006.173.21:14:26.79#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.21:14:26.79#ibcon#[27=USB\r\n] 2006.173.21:14:26.79#ibcon#*before write, iclass 30, count 0 2006.173.21:14:26.79#ibcon#enter sib2, iclass 30, count 0 2006.173.21:14:26.79#ibcon#flushed, iclass 30, count 0 2006.173.21:14:26.79#ibcon#about to write, iclass 30, count 0 2006.173.21:14:26.79#ibcon#wrote, iclass 30, count 0 2006.173.21:14:26.79#ibcon#about to read 3, iclass 30, count 0 2006.173.21:14:26.82#ibcon#read 3, iclass 30, count 0 2006.173.21:14:26.82#ibcon#about to read 4, iclass 30, count 0 2006.173.21:14:26.82#ibcon#read 4, iclass 30, count 0 2006.173.21:14:26.82#ibcon#about to read 5, iclass 30, count 0 2006.173.21:14:26.82#ibcon#read 5, iclass 30, count 0 2006.173.21:14:26.82#ibcon#about to read 6, iclass 30, count 0 2006.173.21:14:26.82#ibcon#read 6, iclass 30, count 0 2006.173.21:14:26.82#ibcon#end of sib2, iclass 30, count 0 2006.173.21:14:26.82#ibcon#*after write, iclass 30, count 0 2006.173.21:14:26.82#ibcon#*before return 0, iclass 30, count 0 2006.173.21:14:26.82#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.21:14:26.82#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.21:14:26.82#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.21:14:26.82#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.21:14:26.82$vck44/vblo=7,734.99 2006.173.21:14:26.82#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.21:14:26.82#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.21:14:26.82#ibcon#ireg 17 cls_cnt 0 2006.173.21:14:26.82#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.21:14:26.82#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.21:14:26.82#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.21:14:26.82#ibcon#enter wrdev, iclass 32, count 0 2006.173.21:14:26.82#ibcon#first serial, iclass 32, count 0 2006.173.21:14:26.82#ibcon#enter sib2, iclass 32, count 0 2006.173.21:14:26.82#ibcon#flushed, iclass 32, count 0 2006.173.21:14:26.82#ibcon#about to write, iclass 32, count 0 2006.173.21:14:26.82#ibcon#wrote, iclass 32, count 0 2006.173.21:14:26.82#ibcon#about to read 3, iclass 32, count 0 2006.173.21:14:26.84#ibcon#read 3, iclass 32, count 0 2006.173.21:14:26.84#ibcon#about to read 4, iclass 32, count 0 2006.173.21:14:26.84#ibcon#read 4, iclass 32, count 0 2006.173.21:14:26.84#ibcon#about to read 5, iclass 32, count 0 2006.173.21:14:26.84#ibcon#read 5, iclass 32, count 0 2006.173.21:14:26.84#ibcon#about to read 6, iclass 32, count 0 2006.173.21:14:26.84#ibcon#read 6, iclass 32, count 0 2006.173.21:14:26.84#ibcon#end of sib2, iclass 32, count 0 2006.173.21:14:26.84#ibcon#*mode == 0, iclass 32, count 0 2006.173.21:14:26.84#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.21:14:26.84#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.21:14:26.84#ibcon#*before write, iclass 32, count 0 2006.173.21:14:26.84#ibcon#enter sib2, iclass 32, count 0 2006.173.21:14:26.84#ibcon#flushed, iclass 32, count 0 2006.173.21:14:26.84#ibcon#about to write, iclass 32, count 0 2006.173.21:14:26.84#ibcon#wrote, iclass 32, count 0 2006.173.21:14:26.84#ibcon#about to read 3, iclass 32, count 0 2006.173.21:14:26.88#ibcon#read 3, iclass 32, count 0 2006.173.21:14:26.88#ibcon#about to read 4, iclass 32, count 0 2006.173.21:14:26.88#ibcon#read 4, iclass 32, count 0 2006.173.21:14:26.88#ibcon#about to read 5, iclass 32, count 0 2006.173.21:14:26.88#ibcon#read 5, iclass 32, count 0 2006.173.21:14:26.88#ibcon#about to read 6, iclass 32, count 0 2006.173.21:14:26.88#ibcon#read 6, iclass 32, count 0 2006.173.21:14:26.88#ibcon#end of sib2, iclass 32, count 0 2006.173.21:14:26.88#ibcon#*after write, iclass 32, count 0 2006.173.21:14:26.88#ibcon#*before return 0, iclass 32, count 0 2006.173.21:14:26.88#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.21:14:26.88#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.21:14:26.88#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.21:14:26.88#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.21:14:26.88$vck44/vb=7,4 2006.173.21:14:26.88#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.21:14:26.88#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.21:14:26.88#ibcon#ireg 11 cls_cnt 2 2006.173.21:14:26.88#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.21:14:26.94#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.21:14:26.94#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.21:14:26.94#ibcon#enter wrdev, iclass 34, count 2 2006.173.21:14:26.94#ibcon#first serial, iclass 34, count 2 2006.173.21:14:26.94#ibcon#enter sib2, iclass 34, count 2 2006.173.21:14:26.94#ibcon#flushed, iclass 34, count 2 2006.173.21:14:26.94#ibcon#about to write, iclass 34, count 2 2006.173.21:14:26.94#ibcon#wrote, iclass 34, count 2 2006.173.21:14:26.94#ibcon#about to read 3, iclass 34, count 2 2006.173.21:14:26.96#ibcon#read 3, iclass 34, count 2 2006.173.21:14:26.96#ibcon#about to read 4, iclass 34, count 2 2006.173.21:14:26.96#ibcon#read 4, iclass 34, count 2 2006.173.21:14:26.96#ibcon#about to read 5, iclass 34, count 2 2006.173.21:14:26.96#ibcon#read 5, iclass 34, count 2 2006.173.21:14:26.96#ibcon#about to read 6, iclass 34, count 2 2006.173.21:14:26.96#ibcon#read 6, iclass 34, count 2 2006.173.21:14:26.96#ibcon#end of sib2, iclass 34, count 2 2006.173.21:14:26.96#ibcon#*mode == 0, iclass 34, count 2 2006.173.21:14:26.96#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.21:14:26.96#ibcon#[27=AT07-04\r\n] 2006.173.21:14:26.96#ibcon#*before write, iclass 34, count 2 2006.173.21:14:26.96#ibcon#enter sib2, iclass 34, count 2 2006.173.21:14:26.96#ibcon#flushed, iclass 34, count 2 2006.173.21:14:26.96#ibcon#about to write, iclass 34, count 2 2006.173.21:14:26.96#ibcon#wrote, iclass 34, count 2 2006.173.21:14:26.96#ibcon#about to read 3, iclass 34, count 2 2006.173.21:14:26.99#ibcon#read 3, iclass 34, count 2 2006.173.21:14:26.99#ibcon#about to read 4, iclass 34, count 2 2006.173.21:14:26.99#ibcon#read 4, iclass 34, count 2 2006.173.21:14:26.99#ibcon#about to read 5, iclass 34, count 2 2006.173.21:14:26.99#ibcon#read 5, iclass 34, count 2 2006.173.21:14:26.99#ibcon#about to read 6, iclass 34, count 2 2006.173.21:14:26.99#ibcon#read 6, iclass 34, count 2 2006.173.21:14:26.99#ibcon#end of sib2, iclass 34, count 2 2006.173.21:14:26.99#ibcon#*after write, iclass 34, count 2 2006.173.21:14:26.99#ibcon#*before return 0, iclass 34, count 2 2006.173.21:14:26.99#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.21:14:26.99#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.21:14:26.99#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.21:14:26.99#ibcon#ireg 7 cls_cnt 0 2006.173.21:14:26.99#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.21:14:27.11#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.21:14:27.11#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.21:14:27.11#ibcon#enter wrdev, iclass 34, count 0 2006.173.21:14:27.11#ibcon#first serial, iclass 34, count 0 2006.173.21:14:27.11#ibcon#enter sib2, iclass 34, count 0 2006.173.21:14:27.11#ibcon#flushed, iclass 34, count 0 2006.173.21:14:27.11#ibcon#about to write, iclass 34, count 0 2006.173.21:14:27.11#ibcon#wrote, iclass 34, count 0 2006.173.21:14:27.11#ibcon#about to read 3, iclass 34, count 0 2006.173.21:14:27.13#ibcon#read 3, iclass 34, count 0 2006.173.21:14:27.13#ibcon#about to read 4, iclass 34, count 0 2006.173.21:14:27.13#ibcon#read 4, iclass 34, count 0 2006.173.21:14:27.13#ibcon#about to read 5, iclass 34, count 0 2006.173.21:14:27.13#ibcon#read 5, iclass 34, count 0 2006.173.21:14:27.13#ibcon#about to read 6, iclass 34, count 0 2006.173.21:14:27.13#ibcon#read 6, iclass 34, count 0 2006.173.21:14:27.13#ibcon#end of sib2, iclass 34, count 0 2006.173.21:14:27.13#ibcon#*mode == 0, iclass 34, count 0 2006.173.21:14:27.13#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.21:14:27.13#ibcon#[27=USB\r\n] 2006.173.21:14:27.13#ibcon#*before write, iclass 34, count 0 2006.173.21:14:27.13#ibcon#enter sib2, iclass 34, count 0 2006.173.21:14:27.13#ibcon#flushed, iclass 34, count 0 2006.173.21:14:27.13#ibcon#about to write, iclass 34, count 0 2006.173.21:14:27.13#ibcon#wrote, iclass 34, count 0 2006.173.21:14:27.13#ibcon#about to read 3, iclass 34, count 0 2006.173.21:14:27.16#ibcon#read 3, iclass 34, count 0 2006.173.21:14:27.16#ibcon#about to read 4, iclass 34, count 0 2006.173.21:14:27.16#ibcon#read 4, iclass 34, count 0 2006.173.21:14:27.16#ibcon#about to read 5, iclass 34, count 0 2006.173.21:14:27.16#ibcon#read 5, iclass 34, count 0 2006.173.21:14:27.16#ibcon#about to read 6, iclass 34, count 0 2006.173.21:14:27.16#ibcon#read 6, iclass 34, count 0 2006.173.21:14:27.16#ibcon#end of sib2, iclass 34, count 0 2006.173.21:14:27.16#ibcon#*after write, iclass 34, count 0 2006.173.21:14:27.16#ibcon#*before return 0, iclass 34, count 0 2006.173.21:14:27.16#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.21:14:27.16#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.21:14:27.16#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.21:14:27.16#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.21:14:27.16$vck44/vblo=8,744.99 2006.173.21:14:27.16#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.21:14:27.16#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.21:14:27.16#ibcon#ireg 17 cls_cnt 0 2006.173.21:14:27.16#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.21:14:27.16#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.21:14:27.16#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.21:14:27.16#ibcon#enter wrdev, iclass 36, count 0 2006.173.21:14:27.16#ibcon#first serial, iclass 36, count 0 2006.173.21:14:27.16#ibcon#enter sib2, iclass 36, count 0 2006.173.21:14:27.16#ibcon#flushed, iclass 36, count 0 2006.173.21:14:27.16#ibcon#about to write, iclass 36, count 0 2006.173.21:14:27.16#ibcon#wrote, iclass 36, count 0 2006.173.21:14:27.16#ibcon#about to read 3, iclass 36, count 0 2006.173.21:14:27.18#ibcon#read 3, iclass 36, count 0 2006.173.21:14:27.18#ibcon#about to read 4, iclass 36, count 0 2006.173.21:14:27.18#ibcon#read 4, iclass 36, count 0 2006.173.21:14:27.18#ibcon#about to read 5, iclass 36, count 0 2006.173.21:14:27.18#ibcon#read 5, iclass 36, count 0 2006.173.21:14:27.18#ibcon#about to read 6, iclass 36, count 0 2006.173.21:14:27.18#ibcon#read 6, iclass 36, count 0 2006.173.21:14:27.18#ibcon#end of sib2, iclass 36, count 0 2006.173.21:14:27.18#ibcon#*mode == 0, iclass 36, count 0 2006.173.21:14:27.18#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.21:14:27.18#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.21:14:27.18#ibcon#*before write, iclass 36, count 0 2006.173.21:14:27.18#ibcon#enter sib2, iclass 36, count 0 2006.173.21:14:27.18#ibcon#flushed, iclass 36, count 0 2006.173.21:14:27.18#ibcon#about to write, iclass 36, count 0 2006.173.21:14:27.18#ibcon#wrote, iclass 36, count 0 2006.173.21:14:27.18#ibcon#about to read 3, iclass 36, count 0 2006.173.21:14:27.22#ibcon#read 3, iclass 36, count 0 2006.173.21:14:27.22#ibcon#about to read 4, iclass 36, count 0 2006.173.21:14:27.22#ibcon#read 4, iclass 36, count 0 2006.173.21:14:27.22#ibcon#about to read 5, iclass 36, count 0 2006.173.21:14:27.22#ibcon#read 5, iclass 36, count 0 2006.173.21:14:27.22#ibcon#about to read 6, iclass 36, count 0 2006.173.21:14:27.22#ibcon#read 6, iclass 36, count 0 2006.173.21:14:27.22#ibcon#end of sib2, iclass 36, count 0 2006.173.21:14:27.22#ibcon#*after write, iclass 36, count 0 2006.173.21:14:27.22#ibcon#*before return 0, iclass 36, count 0 2006.173.21:14:27.22#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.21:14:27.22#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.21:14:27.22#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.21:14:27.22#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.21:14:27.22$vck44/vb=8,4 2006.173.21:14:27.22#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.21:14:27.22#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.21:14:27.22#ibcon#ireg 11 cls_cnt 2 2006.173.21:14:27.22#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.21:14:27.28#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.21:14:27.28#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.21:14:27.28#ibcon#enter wrdev, iclass 38, count 2 2006.173.21:14:27.28#ibcon#first serial, iclass 38, count 2 2006.173.21:14:27.28#ibcon#enter sib2, iclass 38, count 2 2006.173.21:14:27.28#ibcon#flushed, iclass 38, count 2 2006.173.21:14:27.28#ibcon#about to write, iclass 38, count 2 2006.173.21:14:27.28#ibcon#wrote, iclass 38, count 2 2006.173.21:14:27.28#ibcon#about to read 3, iclass 38, count 2 2006.173.21:14:27.30#ibcon#read 3, iclass 38, count 2 2006.173.21:14:27.30#ibcon#about to read 4, iclass 38, count 2 2006.173.21:14:27.30#ibcon#read 4, iclass 38, count 2 2006.173.21:14:27.30#ibcon#about to read 5, iclass 38, count 2 2006.173.21:14:27.30#ibcon#read 5, iclass 38, count 2 2006.173.21:14:27.30#ibcon#about to read 6, iclass 38, count 2 2006.173.21:14:27.30#ibcon#read 6, iclass 38, count 2 2006.173.21:14:27.30#ibcon#end of sib2, iclass 38, count 2 2006.173.21:14:27.30#ibcon#*mode == 0, iclass 38, count 2 2006.173.21:14:27.30#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.21:14:27.30#ibcon#[27=AT08-04\r\n] 2006.173.21:14:27.30#ibcon#*before write, iclass 38, count 2 2006.173.21:14:27.30#ibcon#enter sib2, iclass 38, count 2 2006.173.21:14:27.30#ibcon#flushed, iclass 38, count 2 2006.173.21:14:27.30#ibcon#about to write, iclass 38, count 2 2006.173.21:14:27.30#ibcon#wrote, iclass 38, count 2 2006.173.21:14:27.30#ibcon#about to read 3, iclass 38, count 2 2006.173.21:14:27.33#ibcon#read 3, iclass 38, count 2 2006.173.21:14:27.33#ibcon#about to read 4, iclass 38, count 2 2006.173.21:14:27.33#ibcon#read 4, iclass 38, count 2 2006.173.21:14:27.33#ibcon#about to read 5, iclass 38, count 2 2006.173.21:14:27.33#ibcon#read 5, iclass 38, count 2 2006.173.21:14:27.33#ibcon#about to read 6, iclass 38, count 2 2006.173.21:14:27.33#ibcon#read 6, iclass 38, count 2 2006.173.21:14:27.33#ibcon#end of sib2, iclass 38, count 2 2006.173.21:14:27.33#ibcon#*after write, iclass 38, count 2 2006.173.21:14:27.33#ibcon#*before return 0, iclass 38, count 2 2006.173.21:14:27.33#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.21:14:27.33#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.21:14:27.33#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.21:14:27.33#ibcon#ireg 7 cls_cnt 0 2006.173.21:14:27.33#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.21:14:27.45#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.21:14:27.45#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.21:14:27.45#ibcon#enter wrdev, iclass 38, count 0 2006.173.21:14:27.45#ibcon#first serial, iclass 38, count 0 2006.173.21:14:27.45#ibcon#enter sib2, iclass 38, count 0 2006.173.21:14:27.45#ibcon#flushed, iclass 38, count 0 2006.173.21:14:27.45#ibcon#about to write, iclass 38, count 0 2006.173.21:14:27.45#ibcon#wrote, iclass 38, count 0 2006.173.21:14:27.45#ibcon#about to read 3, iclass 38, count 0 2006.173.21:14:27.47#ibcon#read 3, iclass 38, count 0 2006.173.21:14:27.47#ibcon#about to read 4, iclass 38, count 0 2006.173.21:14:27.47#ibcon#read 4, iclass 38, count 0 2006.173.21:14:27.47#ibcon#about to read 5, iclass 38, count 0 2006.173.21:14:27.47#ibcon#read 5, iclass 38, count 0 2006.173.21:14:27.47#ibcon#about to read 6, iclass 38, count 0 2006.173.21:14:27.47#ibcon#read 6, iclass 38, count 0 2006.173.21:14:27.47#ibcon#end of sib2, iclass 38, count 0 2006.173.21:14:27.47#ibcon#*mode == 0, iclass 38, count 0 2006.173.21:14:27.47#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.21:14:27.47#ibcon#[27=USB\r\n] 2006.173.21:14:27.47#ibcon#*before write, iclass 38, count 0 2006.173.21:14:27.47#ibcon#enter sib2, iclass 38, count 0 2006.173.21:14:27.47#ibcon#flushed, iclass 38, count 0 2006.173.21:14:27.47#ibcon#about to write, iclass 38, count 0 2006.173.21:14:27.47#ibcon#wrote, iclass 38, count 0 2006.173.21:14:27.47#ibcon#about to read 3, iclass 38, count 0 2006.173.21:14:27.50#ibcon#read 3, iclass 38, count 0 2006.173.21:14:27.50#ibcon#about to read 4, iclass 38, count 0 2006.173.21:14:27.50#ibcon#read 4, iclass 38, count 0 2006.173.21:14:27.50#ibcon#about to read 5, iclass 38, count 0 2006.173.21:14:27.50#ibcon#read 5, iclass 38, count 0 2006.173.21:14:27.50#ibcon#about to read 6, iclass 38, count 0 2006.173.21:14:27.50#ibcon#read 6, iclass 38, count 0 2006.173.21:14:27.50#ibcon#end of sib2, iclass 38, count 0 2006.173.21:14:27.50#ibcon#*after write, iclass 38, count 0 2006.173.21:14:27.50#ibcon#*before return 0, iclass 38, count 0 2006.173.21:14:27.50#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.21:14:27.50#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.21:14:27.50#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.21:14:27.50#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.21:14:27.50$vck44/vabw=wide 2006.173.21:14:27.50#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.21:14:27.50#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.21:14:27.50#ibcon#ireg 8 cls_cnt 0 2006.173.21:14:27.50#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.21:14:27.50#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.21:14:27.50#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.21:14:27.50#ibcon#enter wrdev, iclass 40, count 0 2006.173.21:14:27.50#ibcon#first serial, iclass 40, count 0 2006.173.21:14:27.50#ibcon#enter sib2, iclass 40, count 0 2006.173.21:14:27.50#ibcon#flushed, iclass 40, count 0 2006.173.21:14:27.50#ibcon#about to write, iclass 40, count 0 2006.173.21:14:27.50#ibcon#wrote, iclass 40, count 0 2006.173.21:14:27.50#ibcon#about to read 3, iclass 40, count 0 2006.173.21:14:27.52#ibcon#read 3, iclass 40, count 0 2006.173.21:14:27.52#ibcon#about to read 4, iclass 40, count 0 2006.173.21:14:27.52#ibcon#read 4, iclass 40, count 0 2006.173.21:14:27.52#ibcon#about to read 5, iclass 40, count 0 2006.173.21:14:27.52#ibcon#read 5, iclass 40, count 0 2006.173.21:14:27.52#ibcon#about to read 6, iclass 40, count 0 2006.173.21:14:27.52#ibcon#read 6, iclass 40, count 0 2006.173.21:14:27.52#ibcon#end of sib2, iclass 40, count 0 2006.173.21:14:27.52#ibcon#*mode == 0, iclass 40, count 0 2006.173.21:14:27.52#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.21:14:27.52#ibcon#[25=BW32\r\n] 2006.173.21:14:27.52#ibcon#*before write, iclass 40, count 0 2006.173.21:14:27.52#ibcon#enter sib2, iclass 40, count 0 2006.173.21:14:27.52#ibcon#flushed, iclass 40, count 0 2006.173.21:14:27.52#ibcon#about to write, iclass 40, count 0 2006.173.21:14:27.52#ibcon#wrote, iclass 40, count 0 2006.173.21:14:27.52#ibcon#about to read 3, iclass 40, count 0 2006.173.21:14:27.55#ibcon#read 3, iclass 40, count 0 2006.173.21:14:27.55#ibcon#about to read 4, iclass 40, count 0 2006.173.21:14:27.55#ibcon#read 4, iclass 40, count 0 2006.173.21:14:27.55#ibcon#about to read 5, iclass 40, count 0 2006.173.21:14:27.55#ibcon#read 5, iclass 40, count 0 2006.173.21:14:27.55#ibcon#about to read 6, iclass 40, count 0 2006.173.21:14:27.55#ibcon#read 6, iclass 40, count 0 2006.173.21:14:27.55#ibcon#end of sib2, iclass 40, count 0 2006.173.21:14:27.55#ibcon#*after write, iclass 40, count 0 2006.173.21:14:27.55#ibcon#*before return 0, iclass 40, count 0 2006.173.21:14:27.55#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.21:14:27.55#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.21:14:27.55#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.21:14:27.55#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.21:14:27.55$vck44/vbbw=wide 2006.173.21:14:27.55#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.21:14:27.55#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.21:14:27.55#ibcon#ireg 8 cls_cnt 0 2006.173.21:14:27.55#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.21:14:27.62#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.21:14:27.62#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.21:14:27.62#ibcon#enter wrdev, iclass 4, count 0 2006.173.21:14:27.62#ibcon#first serial, iclass 4, count 0 2006.173.21:14:27.62#ibcon#enter sib2, iclass 4, count 0 2006.173.21:14:27.62#ibcon#flushed, iclass 4, count 0 2006.173.21:14:27.62#ibcon#about to write, iclass 4, count 0 2006.173.21:14:27.62#ibcon#wrote, iclass 4, count 0 2006.173.21:14:27.62#ibcon#about to read 3, iclass 4, count 0 2006.173.21:14:27.64#ibcon#read 3, iclass 4, count 0 2006.173.21:14:27.64#ibcon#about to read 4, iclass 4, count 0 2006.173.21:14:27.64#ibcon#read 4, iclass 4, count 0 2006.173.21:14:27.64#ibcon#about to read 5, iclass 4, count 0 2006.173.21:14:27.64#ibcon#read 5, iclass 4, count 0 2006.173.21:14:27.64#ibcon#about to read 6, iclass 4, count 0 2006.173.21:14:27.64#ibcon#read 6, iclass 4, count 0 2006.173.21:14:27.64#ibcon#end of sib2, iclass 4, count 0 2006.173.21:14:27.64#ibcon#*mode == 0, iclass 4, count 0 2006.173.21:14:27.64#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.21:14:27.64#ibcon#[27=BW32\r\n] 2006.173.21:14:27.64#ibcon#*before write, iclass 4, count 0 2006.173.21:14:27.64#ibcon#enter sib2, iclass 4, count 0 2006.173.21:14:27.64#ibcon#flushed, iclass 4, count 0 2006.173.21:14:27.64#ibcon#about to write, iclass 4, count 0 2006.173.21:14:27.64#ibcon#wrote, iclass 4, count 0 2006.173.21:14:27.64#ibcon#about to read 3, iclass 4, count 0 2006.173.21:14:27.67#ibcon#read 3, iclass 4, count 0 2006.173.21:14:27.67#ibcon#about to read 4, iclass 4, count 0 2006.173.21:14:27.67#ibcon#read 4, iclass 4, count 0 2006.173.21:14:27.67#ibcon#about to read 5, iclass 4, count 0 2006.173.21:14:27.67#ibcon#read 5, iclass 4, count 0 2006.173.21:14:27.67#ibcon#about to read 6, iclass 4, count 0 2006.173.21:14:27.67#ibcon#read 6, iclass 4, count 0 2006.173.21:14:27.67#ibcon#end of sib2, iclass 4, count 0 2006.173.21:14:27.67#ibcon#*after write, iclass 4, count 0 2006.173.21:14:27.67#ibcon#*before return 0, iclass 4, count 0 2006.173.21:14:27.67#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.21:14:27.67#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.21:14:27.67#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.21:14:27.67#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.21:14:27.67$setupk4/ifdk4 2006.173.21:14:27.67$ifdk4/lo= 2006.173.21:14:27.67$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.21:14:27.67$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.21:14:27.67$ifdk4/patch= 2006.173.21:14:27.67$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.21:14:27.67$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.21:14:27.67$setupk4/!*+20s 2006.173.21:14:33.04#abcon#<5=/11 0.7 1.8 21.091001003.3\r\n> 2006.173.21:14:33.06#abcon#{5=INTERFACE CLEAR} 2006.173.21:14:33.12#abcon#[5=S1D000X0/0*\r\n] 2006.173.21:14:37.14#trakl#Source acquired 2006.173.21:14:38.14#flagr#flagr/antenna,acquired 2006.173.21:14:42.20$setupk4/"tpicd 2006.173.21:14:42.20$setupk4/echo=off 2006.173.21:14:42.20$setupk4/xlog=off 2006.173.21:14:42.20:!2006.173.21:14:46 2006.173.21:14:46.00:preob 2006.173.21:14:46.14/onsource/TRACKING 2006.173.21:14:46.14:!2006.173.21:14:56 2006.173.21:14:56.00:"tape 2006.173.21:14:56.00:"st=record 2006.173.21:14:56.00:data_valid=on 2006.173.21:14:56.00:midob 2006.173.21:14:56.14/onsource/TRACKING 2006.173.21:14:56.14/wx/21.10,1003.3,100 2006.173.21:14:56.25/cable/+6.5181E-03 2006.173.21:14:57.34/va/01,07,usb,yes,34,37 2006.173.21:14:57.34/va/02,06,usb,yes,34,35 2006.173.21:14:57.34/va/03,05,usb,yes,43,45 2006.173.21:14:57.34/va/04,06,usb,yes,35,37 2006.173.21:14:57.34/va/05,04,usb,yes,27,28 2006.173.21:14:57.34/va/06,03,usb,yes,38,38 2006.173.21:14:57.34/va/07,04,usb,yes,31,32 2006.173.21:14:57.34/va/08,04,usb,yes,26,32 2006.173.21:14:57.57/valo/01,524.99,yes,locked 2006.173.21:14:57.57/valo/02,534.99,yes,locked 2006.173.21:14:57.57/valo/03,564.99,yes,locked 2006.173.21:14:57.57/valo/04,624.99,yes,locked 2006.173.21:14:57.57/valo/05,734.99,yes,locked 2006.173.21:14:57.57/valo/06,814.99,yes,locked 2006.173.21:14:57.57/valo/07,864.99,yes,locked 2006.173.21:14:57.57/valo/08,884.99,yes,locked 2006.173.21:14:58.66/vb/01,04,usb,yes,29,27 2006.173.21:14:58.66/vb/02,04,usb,yes,31,31 2006.173.21:14:58.66/vb/03,04,usb,yes,28,31 2006.173.21:14:58.66/vb/04,04,usb,yes,32,31 2006.173.21:14:58.66/vb/05,04,usb,yes,25,27 2006.173.21:14:58.66/vb/06,04,usb,yes,29,26 2006.173.21:14:58.66/vb/07,04,usb,yes,29,29 2006.173.21:14:58.66/vb/08,04,usb,yes,27,30 2006.173.21:14:58.89/vblo/01,629.99,yes,locked 2006.173.21:14:58.89/vblo/02,634.99,yes,locked 2006.173.21:14:58.89/vblo/03,649.99,yes,locked 2006.173.21:14:58.89/vblo/04,679.99,yes,locked 2006.173.21:14:58.89/vblo/05,709.99,yes,locked 2006.173.21:14:58.89/vblo/06,719.99,yes,locked 2006.173.21:14:58.89/vblo/07,734.99,yes,locked 2006.173.21:14:58.89/vblo/08,744.99,yes,locked 2006.173.21:14:59.04/vabw/8 2006.173.21:14:59.19/vbbw/8 2006.173.21:14:59.40/xfe/off,on,15.2 2006.173.21:14:59.78/ifatt/23,28,28,28 2006.173.21:15:00.07/fmout-gps/S +3.86E-07 2006.173.21:15:00.12:!2006.173.21:16:56 2006.173.21:16:56.01:data_valid=off 2006.173.21:16:56.01:"et 2006.173.21:16:56.01:!+3s 2006.173.21:16:59.02:"tape 2006.173.21:16:59.02:postob 2006.173.21:16:59.09/cable/+6.5166E-03 2006.173.21:16:59.09/wx/21.09,1003.2,100 2006.173.21:16:59.15/fmout-gps/S +3.88E-07 2006.173.21:16:59.15:scan_name=173-2122,jd0606,80 2006.173.21:16:59.15:source=2136+141,213901.31,142336.0,2000.0,cw 2006.173.21:17:00.14#flagr#flagr/antenna,new-source 2006.173.21:17:00.14:checkk5 2006.173.21:17:00.50/chk_autoobs//k5ts1/ autoobs is running! 2006.173.21:17:00.90/chk_autoobs//k5ts2/ autoobs is running! 2006.173.21:17:01.32/chk_autoobs//k5ts3/ autoobs is running! 2006.173.21:17:01.72/chk_autoobs//k5ts4/ autoobs is running! 2006.173.21:17:02.11/chk_obsdata//k5ts1/T1732114??a.dat file size is correct (nominal:480MB, actual:476MB). 2006.173.21:17:02.50/chk_obsdata//k5ts2/T1732114??b.dat file size is correct (nominal:480MB, actual:476MB). 2006.173.21:17:02.93/chk_obsdata//k5ts3/T1732114??c.dat file size is correct (nominal:480MB, actual:476MB). 2006.173.21:17:03.35/chk_obsdata//k5ts4/T1732114??d.dat file size is correct (nominal:480MB, actual:476MB). 2006.173.21:17:04.08/k5log//k5ts1_log_newline 2006.173.21:17:04.80/k5log//k5ts2_log_newline 2006.173.21:17:05.52/k5log//k5ts3_log_newline 2006.173.21:17:06.23/k5log//k5ts4_log_newline 2006.173.21:17:06.25/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.21:17:06.25:setupk4=1 2006.173.21:17:06.25$setupk4/echo=on 2006.173.21:17:06.25$setupk4/pcalon 2006.173.21:17:06.26$pcalon/"no phase cal control is implemented here 2006.173.21:17:06.26$setupk4/"tpicd=stop 2006.173.21:17:06.26$setupk4/"rec=synch_on 2006.173.21:17:06.26$setupk4/"rec_mode=128 2006.173.21:17:06.26$setupk4/!* 2006.173.21:17:06.26$setupk4/recpk4 2006.173.21:17:06.26$recpk4/recpatch= 2006.173.21:17:06.26$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.21:17:06.26$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.21:17:06.26$setupk4/vck44 2006.173.21:17:06.26$vck44/valo=1,524.99 2006.173.21:17:06.26#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.21:17:06.26#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.21:17:06.26#ibcon#ireg 17 cls_cnt 0 2006.173.21:17:06.26#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.21:17:06.26#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.21:17:06.26#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.21:17:06.26#ibcon#enter wrdev, iclass 39, count 0 2006.173.21:17:06.26#ibcon#first serial, iclass 39, count 0 2006.173.21:17:06.26#ibcon#enter sib2, iclass 39, count 0 2006.173.21:17:06.26#ibcon#flushed, iclass 39, count 0 2006.173.21:17:06.26#ibcon#about to write, iclass 39, count 0 2006.173.21:17:06.26#ibcon#wrote, iclass 39, count 0 2006.173.21:17:06.26#ibcon#about to read 3, iclass 39, count 0 2006.173.21:17:06.27#ibcon#read 3, iclass 39, count 0 2006.173.21:17:06.27#ibcon#about to read 4, iclass 39, count 0 2006.173.21:17:06.27#ibcon#read 4, iclass 39, count 0 2006.173.21:17:06.27#ibcon#about to read 5, iclass 39, count 0 2006.173.21:17:06.27#ibcon#read 5, iclass 39, count 0 2006.173.21:17:06.27#ibcon#about to read 6, iclass 39, count 0 2006.173.21:17:06.27#ibcon#read 6, iclass 39, count 0 2006.173.21:17:06.27#ibcon#end of sib2, iclass 39, count 0 2006.173.21:17:06.27#ibcon#*mode == 0, iclass 39, count 0 2006.173.21:17:06.27#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.21:17:06.27#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.21:17:06.27#ibcon#*before write, iclass 39, count 0 2006.173.21:17:06.27#ibcon#enter sib2, iclass 39, count 0 2006.173.21:17:06.27#ibcon#flushed, iclass 39, count 0 2006.173.21:17:06.27#ibcon#about to write, iclass 39, count 0 2006.173.21:17:06.27#ibcon#wrote, iclass 39, count 0 2006.173.21:17:06.27#ibcon#about to read 3, iclass 39, count 0 2006.173.21:17:06.32#ibcon#read 3, iclass 39, count 0 2006.173.21:17:06.32#ibcon#about to read 4, iclass 39, count 0 2006.173.21:17:06.32#ibcon#read 4, iclass 39, count 0 2006.173.21:17:06.32#ibcon#about to read 5, iclass 39, count 0 2006.173.21:17:06.32#ibcon#read 5, iclass 39, count 0 2006.173.21:17:06.32#ibcon#about to read 6, iclass 39, count 0 2006.173.21:17:06.32#ibcon#read 6, iclass 39, count 0 2006.173.21:17:06.32#ibcon#end of sib2, iclass 39, count 0 2006.173.21:17:06.32#ibcon#*after write, iclass 39, count 0 2006.173.21:17:06.32#ibcon#*before return 0, iclass 39, count 0 2006.173.21:17:06.32#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.21:17:06.32#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.21:17:06.32#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.21:17:06.32#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.21:17:06.32$vck44/va=1,7 2006.173.21:17:06.32#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.21:17:06.32#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.21:17:06.32#ibcon#ireg 11 cls_cnt 2 2006.173.21:17:06.32#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.21:17:06.32#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.21:17:06.32#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.21:17:06.32#ibcon#enter wrdev, iclass 3, count 2 2006.173.21:17:06.32#ibcon#first serial, iclass 3, count 2 2006.173.21:17:06.32#ibcon#enter sib2, iclass 3, count 2 2006.173.21:17:06.32#ibcon#flushed, iclass 3, count 2 2006.173.21:17:06.32#ibcon#about to write, iclass 3, count 2 2006.173.21:17:06.32#ibcon#wrote, iclass 3, count 2 2006.173.21:17:06.32#ibcon#about to read 3, iclass 3, count 2 2006.173.21:17:06.34#ibcon#read 3, iclass 3, count 2 2006.173.21:17:06.34#ibcon#about to read 4, iclass 3, count 2 2006.173.21:17:06.34#ibcon#read 4, iclass 3, count 2 2006.173.21:17:06.34#ibcon#about to read 5, iclass 3, count 2 2006.173.21:17:06.34#ibcon#read 5, iclass 3, count 2 2006.173.21:17:06.34#ibcon#about to read 6, iclass 3, count 2 2006.173.21:17:06.34#ibcon#read 6, iclass 3, count 2 2006.173.21:17:06.34#ibcon#end of sib2, iclass 3, count 2 2006.173.21:17:06.34#ibcon#*mode == 0, iclass 3, count 2 2006.173.21:17:06.34#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.21:17:06.34#ibcon#[25=AT01-07\r\n] 2006.173.21:17:06.34#ibcon#*before write, iclass 3, count 2 2006.173.21:17:06.34#ibcon#enter sib2, iclass 3, count 2 2006.173.21:17:06.34#ibcon#flushed, iclass 3, count 2 2006.173.21:17:06.34#ibcon#about to write, iclass 3, count 2 2006.173.21:17:06.34#ibcon#wrote, iclass 3, count 2 2006.173.21:17:06.34#ibcon#about to read 3, iclass 3, count 2 2006.173.21:17:06.37#ibcon#read 3, iclass 3, count 2 2006.173.21:17:06.37#ibcon#about to read 4, iclass 3, count 2 2006.173.21:17:06.37#ibcon#read 4, iclass 3, count 2 2006.173.21:17:06.37#ibcon#about to read 5, iclass 3, count 2 2006.173.21:17:06.37#ibcon#read 5, iclass 3, count 2 2006.173.21:17:06.37#ibcon#about to read 6, iclass 3, count 2 2006.173.21:17:06.37#ibcon#read 6, iclass 3, count 2 2006.173.21:17:06.37#ibcon#end of sib2, iclass 3, count 2 2006.173.21:17:06.37#ibcon#*after write, iclass 3, count 2 2006.173.21:17:06.37#ibcon#*before return 0, iclass 3, count 2 2006.173.21:17:06.37#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.21:17:06.37#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.21:17:06.37#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.21:17:06.37#ibcon#ireg 7 cls_cnt 0 2006.173.21:17:06.37#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.21:17:06.49#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.21:17:06.49#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.21:17:06.49#ibcon#enter wrdev, iclass 3, count 0 2006.173.21:17:06.49#ibcon#first serial, iclass 3, count 0 2006.173.21:17:06.49#ibcon#enter sib2, iclass 3, count 0 2006.173.21:17:06.49#ibcon#flushed, iclass 3, count 0 2006.173.21:17:06.49#ibcon#about to write, iclass 3, count 0 2006.173.21:17:06.49#ibcon#wrote, iclass 3, count 0 2006.173.21:17:06.49#ibcon#about to read 3, iclass 3, count 0 2006.173.21:17:06.51#ibcon#read 3, iclass 3, count 0 2006.173.21:17:06.51#ibcon#about to read 4, iclass 3, count 0 2006.173.21:17:06.51#ibcon#read 4, iclass 3, count 0 2006.173.21:17:06.51#ibcon#about to read 5, iclass 3, count 0 2006.173.21:17:06.51#ibcon#read 5, iclass 3, count 0 2006.173.21:17:06.51#ibcon#about to read 6, iclass 3, count 0 2006.173.21:17:06.51#ibcon#read 6, iclass 3, count 0 2006.173.21:17:06.51#ibcon#end of sib2, iclass 3, count 0 2006.173.21:17:06.51#ibcon#*mode == 0, iclass 3, count 0 2006.173.21:17:06.51#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.21:17:06.51#ibcon#[25=USB\r\n] 2006.173.21:17:06.51#ibcon#*before write, iclass 3, count 0 2006.173.21:17:06.51#ibcon#enter sib2, iclass 3, count 0 2006.173.21:17:06.51#ibcon#flushed, iclass 3, count 0 2006.173.21:17:06.51#ibcon#about to write, iclass 3, count 0 2006.173.21:17:06.51#ibcon#wrote, iclass 3, count 0 2006.173.21:17:06.51#ibcon#about to read 3, iclass 3, count 0 2006.173.21:17:06.54#ibcon#read 3, iclass 3, count 0 2006.173.21:17:06.54#ibcon#about to read 4, iclass 3, count 0 2006.173.21:17:06.54#ibcon#read 4, iclass 3, count 0 2006.173.21:17:06.54#ibcon#about to read 5, iclass 3, count 0 2006.173.21:17:06.54#ibcon#read 5, iclass 3, count 0 2006.173.21:17:06.54#ibcon#about to read 6, iclass 3, count 0 2006.173.21:17:06.54#ibcon#read 6, iclass 3, count 0 2006.173.21:17:06.54#ibcon#end of sib2, iclass 3, count 0 2006.173.21:17:06.54#ibcon#*after write, iclass 3, count 0 2006.173.21:17:06.54#ibcon#*before return 0, iclass 3, count 0 2006.173.21:17:06.54#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.21:17:06.54#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.21:17:06.54#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.21:17:06.54#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.21:17:06.54$vck44/valo=2,534.99 2006.173.21:17:06.54#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.21:17:06.54#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.21:17:06.54#ibcon#ireg 17 cls_cnt 0 2006.173.21:17:06.54#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.21:17:06.54#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.21:17:06.54#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.21:17:06.54#ibcon#enter wrdev, iclass 5, count 0 2006.173.21:17:06.54#ibcon#first serial, iclass 5, count 0 2006.173.21:17:06.54#ibcon#enter sib2, iclass 5, count 0 2006.173.21:17:06.54#ibcon#flushed, iclass 5, count 0 2006.173.21:17:06.54#ibcon#about to write, iclass 5, count 0 2006.173.21:17:06.54#ibcon#wrote, iclass 5, count 0 2006.173.21:17:06.54#ibcon#about to read 3, iclass 5, count 0 2006.173.21:17:06.56#ibcon#read 3, iclass 5, count 0 2006.173.21:17:06.56#ibcon#about to read 4, iclass 5, count 0 2006.173.21:17:06.56#ibcon#read 4, iclass 5, count 0 2006.173.21:17:06.56#ibcon#about to read 5, iclass 5, count 0 2006.173.21:17:06.56#ibcon#read 5, iclass 5, count 0 2006.173.21:17:06.56#ibcon#about to read 6, iclass 5, count 0 2006.173.21:17:06.56#ibcon#read 6, iclass 5, count 0 2006.173.21:17:06.56#ibcon#end of sib2, iclass 5, count 0 2006.173.21:17:06.56#ibcon#*mode == 0, iclass 5, count 0 2006.173.21:17:06.56#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.21:17:06.56#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.21:17:06.56#ibcon#*before write, iclass 5, count 0 2006.173.21:17:06.56#ibcon#enter sib2, iclass 5, count 0 2006.173.21:17:06.56#ibcon#flushed, iclass 5, count 0 2006.173.21:17:06.56#ibcon#about to write, iclass 5, count 0 2006.173.21:17:06.56#ibcon#wrote, iclass 5, count 0 2006.173.21:17:06.56#ibcon#about to read 3, iclass 5, count 0 2006.173.21:17:06.60#ibcon#read 3, iclass 5, count 0 2006.173.21:17:06.60#ibcon#about to read 4, iclass 5, count 0 2006.173.21:17:06.60#ibcon#read 4, iclass 5, count 0 2006.173.21:17:06.60#ibcon#about to read 5, iclass 5, count 0 2006.173.21:17:06.60#ibcon#read 5, iclass 5, count 0 2006.173.21:17:06.60#ibcon#about to read 6, iclass 5, count 0 2006.173.21:17:06.60#ibcon#read 6, iclass 5, count 0 2006.173.21:17:06.60#ibcon#end of sib2, iclass 5, count 0 2006.173.21:17:06.60#ibcon#*after write, iclass 5, count 0 2006.173.21:17:06.60#ibcon#*before return 0, iclass 5, count 0 2006.173.21:17:06.60#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.21:17:06.60#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.21:17:06.60#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.21:17:06.60#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.21:17:06.60$vck44/va=2,6 2006.173.21:17:06.60#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.173.21:17:06.60#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.173.21:17:06.60#ibcon#ireg 11 cls_cnt 2 2006.173.21:17:06.60#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.21:17:06.66#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.21:17:06.66#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.21:17:06.66#ibcon#enter wrdev, iclass 7, count 2 2006.173.21:17:06.66#ibcon#first serial, iclass 7, count 2 2006.173.21:17:06.66#ibcon#enter sib2, iclass 7, count 2 2006.173.21:17:06.66#ibcon#flushed, iclass 7, count 2 2006.173.21:17:06.66#ibcon#about to write, iclass 7, count 2 2006.173.21:17:06.66#ibcon#wrote, iclass 7, count 2 2006.173.21:17:06.66#ibcon#about to read 3, iclass 7, count 2 2006.173.21:17:06.68#ibcon#read 3, iclass 7, count 2 2006.173.21:17:06.68#ibcon#about to read 4, iclass 7, count 2 2006.173.21:17:06.68#ibcon#read 4, iclass 7, count 2 2006.173.21:17:06.68#ibcon#about to read 5, iclass 7, count 2 2006.173.21:17:06.68#ibcon#read 5, iclass 7, count 2 2006.173.21:17:06.68#ibcon#about to read 6, iclass 7, count 2 2006.173.21:17:06.68#ibcon#read 6, iclass 7, count 2 2006.173.21:17:06.68#ibcon#end of sib2, iclass 7, count 2 2006.173.21:17:06.68#ibcon#*mode == 0, iclass 7, count 2 2006.173.21:17:06.68#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.173.21:17:06.68#ibcon#[25=AT02-06\r\n] 2006.173.21:17:06.68#ibcon#*before write, iclass 7, count 2 2006.173.21:17:06.68#ibcon#enter sib2, iclass 7, count 2 2006.173.21:17:06.68#ibcon#flushed, iclass 7, count 2 2006.173.21:17:06.68#ibcon#about to write, iclass 7, count 2 2006.173.21:17:06.68#ibcon#wrote, iclass 7, count 2 2006.173.21:17:06.68#ibcon#about to read 3, iclass 7, count 2 2006.173.21:17:06.71#ibcon#read 3, iclass 7, count 2 2006.173.21:17:06.71#ibcon#about to read 4, iclass 7, count 2 2006.173.21:17:06.71#ibcon#read 4, iclass 7, count 2 2006.173.21:17:06.71#ibcon#about to read 5, iclass 7, count 2 2006.173.21:17:06.71#ibcon#read 5, iclass 7, count 2 2006.173.21:17:06.71#ibcon#about to read 6, iclass 7, count 2 2006.173.21:17:06.71#ibcon#read 6, iclass 7, count 2 2006.173.21:17:06.71#ibcon#end of sib2, iclass 7, count 2 2006.173.21:17:06.71#ibcon#*after write, iclass 7, count 2 2006.173.21:17:06.71#ibcon#*before return 0, iclass 7, count 2 2006.173.21:17:06.71#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.21:17:06.71#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.173.21:17:06.71#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.173.21:17:06.71#ibcon#ireg 7 cls_cnt 0 2006.173.21:17:06.71#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.21:17:06.83#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.21:17:06.83#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.21:17:06.83#ibcon#enter wrdev, iclass 7, count 0 2006.173.21:17:06.83#ibcon#first serial, iclass 7, count 0 2006.173.21:17:06.83#ibcon#enter sib2, iclass 7, count 0 2006.173.21:17:06.83#ibcon#flushed, iclass 7, count 0 2006.173.21:17:06.83#ibcon#about to write, iclass 7, count 0 2006.173.21:17:06.83#ibcon#wrote, iclass 7, count 0 2006.173.21:17:06.83#ibcon#about to read 3, iclass 7, count 0 2006.173.21:17:06.85#ibcon#read 3, iclass 7, count 0 2006.173.21:17:06.85#ibcon#about to read 4, iclass 7, count 0 2006.173.21:17:06.85#ibcon#read 4, iclass 7, count 0 2006.173.21:17:06.85#ibcon#about to read 5, iclass 7, count 0 2006.173.21:17:06.85#ibcon#read 5, iclass 7, count 0 2006.173.21:17:06.85#ibcon#about to read 6, iclass 7, count 0 2006.173.21:17:06.85#ibcon#read 6, iclass 7, count 0 2006.173.21:17:06.85#ibcon#end of sib2, iclass 7, count 0 2006.173.21:17:06.85#ibcon#*mode == 0, iclass 7, count 0 2006.173.21:17:06.85#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.21:17:06.85#ibcon#[25=USB\r\n] 2006.173.21:17:06.85#ibcon#*before write, iclass 7, count 0 2006.173.21:17:06.85#ibcon#enter sib2, iclass 7, count 0 2006.173.21:17:06.85#ibcon#flushed, iclass 7, count 0 2006.173.21:17:06.85#ibcon#about to write, iclass 7, count 0 2006.173.21:17:06.85#ibcon#wrote, iclass 7, count 0 2006.173.21:17:06.85#ibcon#about to read 3, iclass 7, count 0 2006.173.21:17:06.88#ibcon#read 3, iclass 7, count 0 2006.173.21:17:06.88#ibcon#about to read 4, iclass 7, count 0 2006.173.21:17:06.88#ibcon#read 4, iclass 7, count 0 2006.173.21:17:06.88#ibcon#about to read 5, iclass 7, count 0 2006.173.21:17:06.88#ibcon#read 5, iclass 7, count 0 2006.173.21:17:06.88#ibcon#about to read 6, iclass 7, count 0 2006.173.21:17:06.88#ibcon#read 6, iclass 7, count 0 2006.173.21:17:06.88#ibcon#end of sib2, iclass 7, count 0 2006.173.21:17:06.88#ibcon#*after write, iclass 7, count 0 2006.173.21:17:06.88#ibcon#*before return 0, iclass 7, count 0 2006.173.21:17:06.88#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.21:17:06.88#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.173.21:17:06.88#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.21:17:06.88#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.21:17:06.88$vck44/valo=3,564.99 2006.173.21:17:06.88#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.21:17:06.88#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.21:17:06.88#ibcon#ireg 17 cls_cnt 0 2006.173.21:17:06.88#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.21:17:06.88#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.21:17:06.88#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.21:17:06.88#ibcon#enter wrdev, iclass 11, count 0 2006.173.21:17:06.88#ibcon#first serial, iclass 11, count 0 2006.173.21:17:06.88#ibcon#enter sib2, iclass 11, count 0 2006.173.21:17:06.88#ibcon#flushed, iclass 11, count 0 2006.173.21:17:06.88#ibcon#about to write, iclass 11, count 0 2006.173.21:17:06.88#ibcon#wrote, iclass 11, count 0 2006.173.21:17:06.88#ibcon#about to read 3, iclass 11, count 0 2006.173.21:17:06.90#ibcon#read 3, iclass 11, count 0 2006.173.21:17:06.90#ibcon#about to read 4, iclass 11, count 0 2006.173.21:17:06.90#ibcon#read 4, iclass 11, count 0 2006.173.21:17:06.90#ibcon#about to read 5, iclass 11, count 0 2006.173.21:17:06.90#ibcon#read 5, iclass 11, count 0 2006.173.21:17:06.90#ibcon#about to read 6, iclass 11, count 0 2006.173.21:17:06.90#ibcon#read 6, iclass 11, count 0 2006.173.21:17:06.90#ibcon#end of sib2, iclass 11, count 0 2006.173.21:17:06.90#ibcon#*mode == 0, iclass 11, count 0 2006.173.21:17:06.90#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.21:17:06.90#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.21:17:06.90#ibcon#*before write, iclass 11, count 0 2006.173.21:17:06.90#ibcon#enter sib2, iclass 11, count 0 2006.173.21:17:06.90#ibcon#flushed, iclass 11, count 0 2006.173.21:17:06.90#ibcon#about to write, iclass 11, count 0 2006.173.21:17:06.90#ibcon#wrote, iclass 11, count 0 2006.173.21:17:06.90#ibcon#about to read 3, iclass 11, count 0 2006.173.21:17:06.94#ibcon#read 3, iclass 11, count 0 2006.173.21:17:06.94#ibcon#about to read 4, iclass 11, count 0 2006.173.21:17:06.94#ibcon#read 4, iclass 11, count 0 2006.173.21:17:06.94#ibcon#about to read 5, iclass 11, count 0 2006.173.21:17:06.94#ibcon#read 5, iclass 11, count 0 2006.173.21:17:06.94#ibcon#about to read 6, iclass 11, count 0 2006.173.21:17:06.94#ibcon#read 6, iclass 11, count 0 2006.173.21:17:06.94#ibcon#end of sib2, iclass 11, count 0 2006.173.21:17:06.94#ibcon#*after write, iclass 11, count 0 2006.173.21:17:06.94#ibcon#*before return 0, iclass 11, count 0 2006.173.21:17:06.94#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.21:17:06.94#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.21:17:06.94#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.21:17:06.94#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.21:17:06.94$vck44/va=3,5 2006.173.21:17:06.94#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.173.21:17:06.94#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.173.21:17:06.94#ibcon#ireg 11 cls_cnt 2 2006.173.21:17:06.94#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.21:17:07.00#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.21:17:07.00#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.21:17:07.00#ibcon#enter wrdev, iclass 13, count 2 2006.173.21:17:07.00#ibcon#first serial, iclass 13, count 2 2006.173.21:17:07.00#ibcon#enter sib2, iclass 13, count 2 2006.173.21:17:07.00#ibcon#flushed, iclass 13, count 2 2006.173.21:17:07.00#ibcon#about to write, iclass 13, count 2 2006.173.21:17:07.00#ibcon#wrote, iclass 13, count 2 2006.173.21:17:07.00#ibcon#about to read 3, iclass 13, count 2 2006.173.21:17:07.02#ibcon#read 3, iclass 13, count 2 2006.173.21:17:07.02#ibcon#about to read 4, iclass 13, count 2 2006.173.21:17:07.02#ibcon#read 4, iclass 13, count 2 2006.173.21:17:07.02#ibcon#about to read 5, iclass 13, count 2 2006.173.21:17:07.02#ibcon#read 5, iclass 13, count 2 2006.173.21:17:07.02#ibcon#about to read 6, iclass 13, count 2 2006.173.21:17:07.02#ibcon#read 6, iclass 13, count 2 2006.173.21:17:07.02#ibcon#end of sib2, iclass 13, count 2 2006.173.21:17:07.02#ibcon#*mode == 0, iclass 13, count 2 2006.173.21:17:07.02#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.173.21:17:07.02#ibcon#[25=AT03-05\r\n] 2006.173.21:17:07.02#ibcon#*before write, iclass 13, count 2 2006.173.21:17:07.02#ibcon#enter sib2, iclass 13, count 2 2006.173.21:17:07.02#ibcon#flushed, iclass 13, count 2 2006.173.21:17:07.02#ibcon#about to write, iclass 13, count 2 2006.173.21:17:07.02#ibcon#wrote, iclass 13, count 2 2006.173.21:17:07.02#ibcon#about to read 3, iclass 13, count 2 2006.173.21:17:07.05#ibcon#read 3, iclass 13, count 2 2006.173.21:17:07.05#ibcon#about to read 4, iclass 13, count 2 2006.173.21:17:07.05#ibcon#read 4, iclass 13, count 2 2006.173.21:17:07.05#ibcon#about to read 5, iclass 13, count 2 2006.173.21:17:07.05#ibcon#read 5, iclass 13, count 2 2006.173.21:17:07.05#ibcon#about to read 6, iclass 13, count 2 2006.173.21:17:07.05#ibcon#read 6, iclass 13, count 2 2006.173.21:17:07.05#ibcon#end of sib2, iclass 13, count 2 2006.173.21:17:07.05#ibcon#*after write, iclass 13, count 2 2006.173.21:17:07.05#ibcon#*before return 0, iclass 13, count 2 2006.173.21:17:07.05#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.21:17:07.05#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.173.21:17:07.05#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.173.21:17:07.05#ibcon#ireg 7 cls_cnt 0 2006.173.21:17:07.05#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.21:17:07.17#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.21:17:07.17#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.21:17:07.17#ibcon#enter wrdev, iclass 13, count 0 2006.173.21:17:07.17#ibcon#first serial, iclass 13, count 0 2006.173.21:17:07.17#ibcon#enter sib2, iclass 13, count 0 2006.173.21:17:07.17#ibcon#flushed, iclass 13, count 0 2006.173.21:17:07.17#ibcon#about to write, iclass 13, count 0 2006.173.21:17:07.17#ibcon#wrote, iclass 13, count 0 2006.173.21:17:07.17#ibcon#about to read 3, iclass 13, count 0 2006.173.21:17:07.19#ibcon#read 3, iclass 13, count 0 2006.173.21:17:07.19#ibcon#about to read 4, iclass 13, count 0 2006.173.21:17:07.19#ibcon#read 4, iclass 13, count 0 2006.173.21:17:07.19#ibcon#about to read 5, iclass 13, count 0 2006.173.21:17:07.19#ibcon#read 5, iclass 13, count 0 2006.173.21:17:07.19#ibcon#about to read 6, iclass 13, count 0 2006.173.21:17:07.19#ibcon#read 6, iclass 13, count 0 2006.173.21:17:07.19#ibcon#end of sib2, iclass 13, count 0 2006.173.21:17:07.19#ibcon#*mode == 0, iclass 13, count 0 2006.173.21:17:07.19#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.21:17:07.19#ibcon#[25=USB\r\n] 2006.173.21:17:07.19#ibcon#*before write, iclass 13, count 0 2006.173.21:17:07.19#ibcon#enter sib2, iclass 13, count 0 2006.173.21:17:07.19#ibcon#flushed, iclass 13, count 0 2006.173.21:17:07.19#ibcon#about to write, iclass 13, count 0 2006.173.21:17:07.19#ibcon#wrote, iclass 13, count 0 2006.173.21:17:07.19#ibcon#about to read 3, iclass 13, count 0 2006.173.21:17:07.22#ibcon#read 3, iclass 13, count 0 2006.173.21:17:07.22#ibcon#about to read 4, iclass 13, count 0 2006.173.21:17:07.22#ibcon#read 4, iclass 13, count 0 2006.173.21:17:07.22#ibcon#about to read 5, iclass 13, count 0 2006.173.21:17:07.22#ibcon#read 5, iclass 13, count 0 2006.173.21:17:07.22#ibcon#about to read 6, iclass 13, count 0 2006.173.21:17:07.22#ibcon#read 6, iclass 13, count 0 2006.173.21:17:07.22#ibcon#end of sib2, iclass 13, count 0 2006.173.21:17:07.22#ibcon#*after write, iclass 13, count 0 2006.173.21:17:07.22#ibcon#*before return 0, iclass 13, count 0 2006.173.21:17:07.22#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.21:17:07.22#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.173.21:17:07.22#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.21:17:07.22#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.21:17:07.22$vck44/valo=4,624.99 2006.173.21:17:07.22#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.21:17:07.22#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.21:17:07.22#ibcon#ireg 17 cls_cnt 0 2006.173.21:17:07.22#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.21:17:07.22#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.21:17:07.22#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.21:17:07.22#ibcon#enter wrdev, iclass 15, count 0 2006.173.21:17:07.22#ibcon#first serial, iclass 15, count 0 2006.173.21:17:07.22#ibcon#enter sib2, iclass 15, count 0 2006.173.21:17:07.22#ibcon#flushed, iclass 15, count 0 2006.173.21:17:07.22#ibcon#about to write, iclass 15, count 0 2006.173.21:17:07.22#ibcon#wrote, iclass 15, count 0 2006.173.21:17:07.22#ibcon#about to read 3, iclass 15, count 0 2006.173.21:17:07.24#ibcon#read 3, iclass 15, count 0 2006.173.21:17:07.24#ibcon#about to read 4, iclass 15, count 0 2006.173.21:17:07.24#ibcon#read 4, iclass 15, count 0 2006.173.21:17:07.24#ibcon#about to read 5, iclass 15, count 0 2006.173.21:17:07.24#ibcon#read 5, iclass 15, count 0 2006.173.21:17:07.24#ibcon#about to read 6, iclass 15, count 0 2006.173.21:17:07.24#ibcon#read 6, iclass 15, count 0 2006.173.21:17:07.24#ibcon#end of sib2, iclass 15, count 0 2006.173.21:17:07.24#ibcon#*mode == 0, iclass 15, count 0 2006.173.21:17:07.24#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.21:17:07.24#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.21:17:07.24#ibcon#*before write, iclass 15, count 0 2006.173.21:17:07.24#ibcon#enter sib2, iclass 15, count 0 2006.173.21:17:07.24#ibcon#flushed, iclass 15, count 0 2006.173.21:17:07.24#ibcon#about to write, iclass 15, count 0 2006.173.21:17:07.24#ibcon#wrote, iclass 15, count 0 2006.173.21:17:07.24#ibcon#about to read 3, iclass 15, count 0 2006.173.21:17:07.28#ibcon#read 3, iclass 15, count 0 2006.173.21:17:07.28#ibcon#about to read 4, iclass 15, count 0 2006.173.21:17:07.28#ibcon#read 4, iclass 15, count 0 2006.173.21:17:07.28#ibcon#about to read 5, iclass 15, count 0 2006.173.21:17:07.28#ibcon#read 5, iclass 15, count 0 2006.173.21:17:07.28#ibcon#about to read 6, iclass 15, count 0 2006.173.21:17:07.28#ibcon#read 6, iclass 15, count 0 2006.173.21:17:07.28#ibcon#end of sib2, iclass 15, count 0 2006.173.21:17:07.28#ibcon#*after write, iclass 15, count 0 2006.173.21:17:07.28#ibcon#*before return 0, iclass 15, count 0 2006.173.21:17:07.28#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.21:17:07.28#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.21:17:07.28#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.21:17:07.28#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.21:17:07.28$vck44/va=4,6 2006.173.21:17:07.28#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.21:17:07.28#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.21:17:07.28#ibcon#ireg 11 cls_cnt 2 2006.173.21:17:07.28#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.21:17:07.34#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.21:17:07.34#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.21:17:07.34#ibcon#enter wrdev, iclass 17, count 2 2006.173.21:17:07.34#ibcon#first serial, iclass 17, count 2 2006.173.21:17:07.34#ibcon#enter sib2, iclass 17, count 2 2006.173.21:17:07.34#ibcon#flushed, iclass 17, count 2 2006.173.21:17:07.34#ibcon#about to write, iclass 17, count 2 2006.173.21:17:07.34#ibcon#wrote, iclass 17, count 2 2006.173.21:17:07.34#ibcon#about to read 3, iclass 17, count 2 2006.173.21:17:07.36#ibcon#read 3, iclass 17, count 2 2006.173.21:17:07.36#ibcon#about to read 4, iclass 17, count 2 2006.173.21:17:07.36#ibcon#read 4, iclass 17, count 2 2006.173.21:17:07.36#ibcon#about to read 5, iclass 17, count 2 2006.173.21:17:07.36#ibcon#read 5, iclass 17, count 2 2006.173.21:17:07.36#ibcon#about to read 6, iclass 17, count 2 2006.173.21:17:07.36#ibcon#read 6, iclass 17, count 2 2006.173.21:17:07.36#ibcon#end of sib2, iclass 17, count 2 2006.173.21:17:07.36#ibcon#*mode == 0, iclass 17, count 2 2006.173.21:17:07.36#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.21:17:07.36#ibcon#[25=AT04-06\r\n] 2006.173.21:17:07.36#ibcon#*before write, iclass 17, count 2 2006.173.21:17:07.36#ibcon#enter sib2, iclass 17, count 2 2006.173.21:17:07.36#ibcon#flushed, iclass 17, count 2 2006.173.21:17:07.36#ibcon#about to write, iclass 17, count 2 2006.173.21:17:07.36#ibcon#wrote, iclass 17, count 2 2006.173.21:17:07.36#ibcon#about to read 3, iclass 17, count 2 2006.173.21:17:07.39#ibcon#read 3, iclass 17, count 2 2006.173.21:17:07.39#ibcon#about to read 4, iclass 17, count 2 2006.173.21:17:07.39#ibcon#read 4, iclass 17, count 2 2006.173.21:17:07.39#ibcon#about to read 5, iclass 17, count 2 2006.173.21:17:07.39#ibcon#read 5, iclass 17, count 2 2006.173.21:17:07.39#ibcon#about to read 6, iclass 17, count 2 2006.173.21:17:07.39#ibcon#read 6, iclass 17, count 2 2006.173.21:17:07.39#ibcon#end of sib2, iclass 17, count 2 2006.173.21:17:07.39#ibcon#*after write, iclass 17, count 2 2006.173.21:17:07.39#ibcon#*before return 0, iclass 17, count 2 2006.173.21:17:07.39#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.21:17:07.39#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.21:17:07.39#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.21:17:07.39#ibcon#ireg 7 cls_cnt 0 2006.173.21:17:07.39#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.21:17:07.51#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.21:17:07.51#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.21:17:07.51#ibcon#enter wrdev, iclass 17, count 0 2006.173.21:17:07.51#ibcon#first serial, iclass 17, count 0 2006.173.21:17:07.51#ibcon#enter sib2, iclass 17, count 0 2006.173.21:17:07.51#ibcon#flushed, iclass 17, count 0 2006.173.21:17:07.51#ibcon#about to write, iclass 17, count 0 2006.173.21:17:07.51#ibcon#wrote, iclass 17, count 0 2006.173.21:17:07.51#ibcon#about to read 3, iclass 17, count 0 2006.173.21:17:07.53#ibcon#read 3, iclass 17, count 0 2006.173.21:17:07.53#ibcon#about to read 4, iclass 17, count 0 2006.173.21:17:07.53#ibcon#read 4, iclass 17, count 0 2006.173.21:17:07.53#ibcon#about to read 5, iclass 17, count 0 2006.173.21:17:07.53#ibcon#read 5, iclass 17, count 0 2006.173.21:17:07.53#ibcon#about to read 6, iclass 17, count 0 2006.173.21:17:07.53#ibcon#read 6, iclass 17, count 0 2006.173.21:17:07.53#ibcon#end of sib2, iclass 17, count 0 2006.173.21:17:07.53#ibcon#*mode == 0, iclass 17, count 0 2006.173.21:17:07.53#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.21:17:07.53#ibcon#[25=USB\r\n] 2006.173.21:17:07.53#ibcon#*before write, iclass 17, count 0 2006.173.21:17:07.53#ibcon#enter sib2, iclass 17, count 0 2006.173.21:17:07.53#ibcon#flushed, iclass 17, count 0 2006.173.21:17:07.53#ibcon#about to write, iclass 17, count 0 2006.173.21:17:07.53#ibcon#wrote, iclass 17, count 0 2006.173.21:17:07.53#ibcon#about to read 3, iclass 17, count 0 2006.173.21:17:07.56#ibcon#read 3, iclass 17, count 0 2006.173.21:17:07.56#ibcon#about to read 4, iclass 17, count 0 2006.173.21:17:07.56#ibcon#read 4, iclass 17, count 0 2006.173.21:17:07.56#ibcon#about to read 5, iclass 17, count 0 2006.173.21:17:07.56#ibcon#read 5, iclass 17, count 0 2006.173.21:17:07.56#ibcon#about to read 6, iclass 17, count 0 2006.173.21:17:07.56#ibcon#read 6, iclass 17, count 0 2006.173.21:17:07.56#ibcon#end of sib2, iclass 17, count 0 2006.173.21:17:07.56#ibcon#*after write, iclass 17, count 0 2006.173.21:17:07.56#ibcon#*before return 0, iclass 17, count 0 2006.173.21:17:07.56#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.21:17:07.56#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.21:17:07.56#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.21:17:07.56#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.21:17:07.56$vck44/valo=5,734.99 2006.173.21:17:07.56#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.21:17:07.56#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.21:17:07.56#ibcon#ireg 17 cls_cnt 0 2006.173.21:17:07.56#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.21:17:07.56#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.21:17:07.56#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.21:17:07.56#ibcon#enter wrdev, iclass 19, count 0 2006.173.21:17:07.56#ibcon#first serial, iclass 19, count 0 2006.173.21:17:07.56#ibcon#enter sib2, iclass 19, count 0 2006.173.21:17:07.56#ibcon#flushed, iclass 19, count 0 2006.173.21:17:07.56#ibcon#about to write, iclass 19, count 0 2006.173.21:17:07.56#ibcon#wrote, iclass 19, count 0 2006.173.21:17:07.56#ibcon#about to read 3, iclass 19, count 0 2006.173.21:17:07.58#ibcon#read 3, iclass 19, count 0 2006.173.21:17:07.58#ibcon#about to read 4, iclass 19, count 0 2006.173.21:17:07.58#ibcon#read 4, iclass 19, count 0 2006.173.21:17:07.58#ibcon#about to read 5, iclass 19, count 0 2006.173.21:17:07.58#ibcon#read 5, iclass 19, count 0 2006.173.21:17:07.58#ibcon#about to read 6, iclass 19, count 0 2006.173.21:17:07.58#ibcon#read 6, iclass 19, count 0 2006.173.21:17:07.58#ibcon#end of sib2, iclass 19, count 0 2006.173.21:17:07.58#ibcon#*mode == 0, iclass 19, count 0 2006.173.21:17:07.58#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.21:17:07.58#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.21:17:07.58#ibcon#*before write, iclass 19, count 0 2006.173.21:17:07.58#ibcon#enter sib2, iclass 19, count 0 2006.173.21:17:07.58#ibcon#flushed, iclass 19, count 0 2006.173.21:17:07.58#ibcon#about to write, iclass 19, count 0 2006.173.21:17:07.58#ibcon#wrote, iclass 19, count 0 2006.173.21:17:07.58#ibcon#about to read 3, iclass 19, count 0 2006.173.21:17:07.62#ibcon#read 3, iclass 19, count 0 2006.173.21:17:07.62#ibcon#about to read 4, iclass 19, count 0 2006.173.21:17:07.62#ibcon#read 4, iclass 19, count 0 2006.173.21:17:07.62#ibcon#about to read 5, iclass 19, count 0 2006.173.21:17:07.62#ibcon#read 5, iclass 19, count 0 2006.173.21:17:07.62#ibcon#about to read 6, iclass 19, count 0 2006.173.21:17:07.62#ibcon#read 6, iclass 19, count 0 2006.173.21:17:07.62#ibcon#end of sib2, iclass 19, count 0 2006.173.21:17:07.62#ibcon#*after write, iclass 19, count 0 2006.173.21:17:07.62#ibcon#*before return 0, iclass 19, count 0 2006.173.21:17:07.62#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.21:17:07.62#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.21:17:07.62#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.21:17:07.62#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.21:17:07.62$vck44/va=5,4 2006.173.21:17:07.62#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.21:17:07.62#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.21:17:07.62#ibcon#ireg 11 cls_cnt 2 2006.173.21:17:07.62#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.21:17:07.68#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.21:17:07.68#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.21:17:07.68#ibcon#enter wrdev, iclass 21, count 2 2006.173.21:17:07.68#ibcon#first serial, iclass 21, count 2 2006.173.21:17:07.68#ibcon#enter sib2, iclass 21, count 2 2006.173.21:17:07.68#ibcon#flushed, iclass 21, count 2 2006.173.21:17:07.68#ibcon#about to write, iclass 21, count 2 2006.173.21:17:07.68#ibcon#wrote, iclass 21, count 2 2006.173.21:17:07.68#ibcon#about to read 3, iclass 21, count 2 2006.173.21:17:07.70#ibcon#read 3, iclass 21, count 2 2006.173.21:17:07.70#ibcon#about to read 4, iclass 21, count 2 2006.173.21:17:07.70#ibcon#read 4, iclass 21, count 2 2006.173.21:17:07.70#ibcon#about to read 5, iclass 21, count 2 2006.173.21:17:07.70#ibcon#read 5, iclass 21, count 2 2006.173.21:17:07.70#ibcon#about to read 6, iclass 21, count 2 2006.173.21:17:07.70#ibcon#read 6, iclass 21, count 2 2006.173.21:17:07.70#ibcon#end of sib2, iclass 21, count 2 2006.173.21:17:07.70#ibcon#*mode == 0, iclass 21, count 2 2006.173.21:17:07.70#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.21:17:07.70#ibcon#[25=AT05-04\r\n] 2006.173.21:17:07.70#ibcon#*before write, iclass 21, count 2 2006.173.21:17:07.70#ibcon#enter sib2, iclass 21, count 2 2006.173.21:17:07.70#ibcon#flushed, iclass 21, count 2 2006.173.21:17:07.70#ibcon#about to write, iclass 21, count 2 2006.173.21:17:07.70#ibcon#wrote, iclass 21, count 2 2006.173.21:17:07.70#ibcon#about to read 3, iclass 21, count 2 2006.173.21:17:07.73#ibcon#read 3, iclass 21, count 2 2006.173.21:17:07.73#ibcon#about to read 4, iclass 21, count 2 2006.173.21:17:07.73#ibcon#read 4, iclass 21, count 2 2006.173.21:17:07.73#ibcon#about to read 5, iclass 21, count 2 2006.173.21:17:07.73#ibcon#read 5, iclass 21, count 2 2006.173.21:17:07.73#ibcon#about to read 6, iclass 21, count 2 2006.173.21:17:07.73#ibcon#read 6, iclass 21, count 2 2006.173.21:17:07.73#ibcon#end of sib2, iclass 21, count 2 2006.173.21:17:07.73#ibcon#*after write, iclass 21, count 2 2006.173.21:17:07.73#ibcon#*before return 0, iclass 21, count 2 2006.173.21:17:07.73#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.21:17:07.73#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.21:17:07.73#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.21:17:07.73#ibcon#ireg 7 cls_cnt 0 2006.173.21:17:07.73#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.21:17:07.85#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.21:17:07.85#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.21:17:07.85#ibcon#enter wrdev, iclass 21, count 0 2006.173.21:17:07.85#ibcon#first serial, iclass 21, count 0 2006.173.21:17:07.85#ibcon#enter sib2, iclass 21, count 0 2006.173.21:17:07.85#ibcon#flushed, iclass 21, count 0 2006.173.21:17:07.85#ibcon#about to write, iclass 21, count 0 2006.173.21:17:07.85#ibcon#wrote, iclass 21, count 0 2006.173.21:17:07.85#ibcon#about to read 3, iclass 21, count 0 2006.173.21:17:07.87#ibcon#read 3, iclass 21, count 0 2006.173.21:17:07.87#ibcon#about to read 4, iclass 21, count 0 2006.173.21:17:07.87#ibcon#read 4, iclass 21, count 0 2006.173.21:17:07.87#ibcon#about to read 5, iclass 21, count 0 2006.173.21:17:07.87#ibcon#read 5, iclass 21, count 0 2006.173.21:17:07.87#ibcon#about to read 6, iclass 21, count 0 2006.173.21:17:07.87#ibcon#read 6, iclass 21, count 0 2006.173.21:17:07.87#ibcon#end of sib2, iclass 21, count 0 2006.173.21:17:07.87#ibcon#*mode == 0, iclass 21, count 0 2006.173.21:17:07.87#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.21:17:07.87#ibcon#[25=USB\r\n] 2006.173.21:17:07.87#ibcon#*before write, iclass 21, count 0 2006.173.21:17:07.87#ibcon#enter sib2, iclass 21, count 0 2006.173.21:17:07.87#ibcon#flushed, iclass 21, count 0 2006.173.21:17:07.87#ibcon#about to write, iclass 21, count 0 2006.173.21:17:07.87#ibcon#wrote, iclass 21, count 0 2006.173.21:17:07.87#ibcon#about to read 3, iclass 21, count 0 2006.173.21:17:07.90#ibcon#read 3, iclass 21, count 0 2006.173.21:17:07.90#ibcon#about to read 4, iclass 21, count 0 2006.173.21:17:07.90#ibcon#read 4, iclass 21, count 0 2006.173.21:17:07.90#ibcon#about to read 5, iclass 21, count 0 2006.173.21:17:07.90#ibcon#read 5, iclass 21, count 0 2006.173.21:17:07.90#ibcon#about to read 6, iclass 21, count 0 2006.173.21:17:07.90#ibcon#read 6, iclass 21, count 0 2006.173.21:17:07.90#ibcon#end of sib2, iclass 21, count 0 2006.173.21:17:07.90#ibcon#*after write, iclass 21, count 0 2006.173.21:17:07.90#ibcon#*before return 0, iclass 21, count 0 2006.173.21:17:07.90#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.21:17:07.90#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.21:17:07.90#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.21:17:07.90#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.21:17:07.90$vck44/valo=6,814.99 2006.173.21:17:07.90#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.21:17:07.90#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.21:17:07.90#ibcon#ireg 17 cls_cnt 0 2006.173.21:17:07.90#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.21:17:07.90#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.21:17:07.90#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.21:17:07.90#ibcon#enter wrdev, iclass 23, count 0 2006.173.21:17:07.90#ibcon#first serial, iclass 23, count 0 2006.173.21:17:07.90#ibcon#enter sib2, iclass 23, count 0 2006.173.21:17:07.90#ibcon#flushed, iclass 23, count 0 2006.173.21:17:07.90#ibcon#about to write, iclass 23, count 0 2006.173.21:17:07.90#ibcon#wrote, iclass 23, count 0 2006.173.21:17:07.90#ibcon#about to read 3, iclass 23, count 0 2006.173.21:17:07.92#ibcon#read 3, iclass 23, count 0 2006.173.21:17:07.92#ibcon#about to read 4, iclass 23, count 0 2006.173.21:17:07.92#ibcon#read 4, iclass 23, count 0 2006.173.21:17:07.92#ibcon#about to read 5, iclass 23, count 0 2006.173.21:17:07.92#ibcon#read 5, iclass 23, count 0 2006.173.21:17:07.92#ibcon#about to read 6, iclass 23, count 0 2006.173.21:17:07.92#ibcon#read 6, iclass 23, count 0 2006.173.21:17:07.92#ibcon#end of sib2, iclass 23, count 0 2006.173.21:17:07.92#ibcon#*mode == 0, iclass 23, count 0 2006.173.21:17:07.92#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.21:17:07.92#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.21:17:07.92#ibcon#*before write, iclass 23, count 0 2006.173.21:17:07.92#ibcon#enter sib2, iclass 23, count 0 2006.173.21:17:07.92#ibcon#flushed, iclass 23, count 0 2006.173.21:17:07.92#ibcon#about to write, iclass 23, count 0 2006.173.21:17:07.92#ibcon#wrote, iclass 23, count 0 2006.173.21:17:07.92#ibcon#about to read 3, iclass 23, count 0 2006.173.21:17:07.96#ibcon#read 3, iclass 23, count 0 2006.173.21:17:07.96#ibcon#about to read 4, iclass 23, count 0 2006.173.21:17:07.96#ibcon#read 4, iclass 23, count 0 2006.173.21:17:07.96#ibcon#about to read 5, iclass 23, count 0 2006.173.21:17:07.96#ibcon#read 5, iclass 23, count 0 2006.173.21:17:07.96#ibcon#about to read 6, iclass 23, count 0 2006.173.21:17:07.96#ibcon#read 6, iclass 23, count 0 2006.173.21:17:07.96#ibcon#end of sib2, iclass 23, count 0 2006.173.21:17:07.96#ibcon#*after write, iclass 23, count 0 2006.173.21:17:07.96#ibcon#*before return 0, iclass 23, count 0 2006.173.21:17:07.96#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.21:17:07.96#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.21:17:07.96#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.21:17:07.96#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.21:17:07.96$vck44/va=6,3 2006.173.21:17:07.96#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.21:17:07.96#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.21:17:07.96#ibcon#ireg 11 cls_cnt 2 2006.173.21:17:07.96#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.21:17:08.02#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.21:17:08.02#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.21:17:08.02#ibcon#enter wrdev, iclass 25, count 2 2006.173.21:17:08.02#ibcon#first serial, iclass 25, count 2 2006.173.21:17:08.02#ibcon#enter sib2, iclass 25, count 2 2006.173.21:17:08.02#ibcon#flushed, iclass 25, count 2 2006.173.21:17:08.02#ibcon#about to write, iclass 25, count 2 2006.173.21:17:08.02#ibcon#wrote, iclass 25, count 2 2006.173.21:17:08.02#ibcon#about to read 3, iclass 25, count 2 2006.173.21:17:08.04#ibcon#read 3, iclass 25, count 2 2006.173.21:17:08.04#ibcon#about to read 4, iclass 25, count 2 2006.173.21:17:08.04#ibcon#read 4, iclass 25, count 2 2006.173.21:17:08.04#ibcon#about to read 5, iclass 25, count 2 2006.173.21:17:08.04#ibcon#read 5, iclass 25, count 2 2006.173.21:17:08.04#ibcon#about to read 6, iclass 25, count 2 2006.173.21:17:08.04#ibcon#read 6, iclass 25, count 2 2006.173.21:17:08.04#ibcon#end of sib2, iclass 25, count 2 2006.173.21:17:08.04#ibcon#*mode == 0, iclass 25, count 2 2006.173.21:17:08.04#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.21:17:08.04#ibcon#[25=AT06-03\r\n] 2006.173.21:17:08.04#ibcon#*before write, iclass 25, count 2 2006.173.21:17:08.04#ibcon#enter sib2, iclass 25, count 2 2006.173.21:17:08.04#ibcon#flushed, iclass 25, count 2 2006.173.21:17:08.04#ibcon#about to write, iclass 25, count 2 2006.173.21:17:08.04#ibcon#wrote, iclass 25, count 2 2006.173.21:17:08.04#ibcon#about to read 3, iclass 25, count 2 2006.173.21:17:08.07#ibcon#read 3, iclass 25, count 2 2006.173.21:17:08.07#ibcon#about to read 4, iclass 25, count 2 2006.173.21:17:08.07#ibcon#read 4, iclass 25, count 2 2006.173.21:17:08.07#ibcon#about to read 5, iclass 25, count 2 2006.173.21:17:08.07#ibcon#read 5, iclass 25, count 2 2006.173.21:17:08.07#ibcon#about to read 6, iclass 25, count 2 2006.173.21:17:08.07#ibcon#read 6, iclass 25, count 2 2006.173.21:17:08.07#ibcon#end of sib2, iclass 25, count 2 2006.173.21:17:08.07#ibcon#*after write, iclass 25, count 2 2006.173.21:17:08.07#ibcon#*before return 0, iclass 25, count 2 2006.173.21:17:08.07#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.21:17:08.07#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.21:17:08.07#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.21:17:08.07#ibcon#ireg 7 cls_cnt 0 2006.173.21:17:08.07#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.21:17:08.19#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.21:17:08.19#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.21:17:08.19#ibcon#enter wrdev, iclass 25, count 0 2006.173.21:17:08.19#ibcon#first serial, iclass 25, count 0 2006.173.21:17:08.19#ibcon#enter sib2, iclass 25, count 0 2006.173.21:17:08.19#ibcon#flushed, iclass 25, count 0 2006.173.21:17:08.19#ibcon#about to write, iclass 25, count 0 2006.173.21:17:08.19#ibcon#wrote, iclass 25, count 0 2006.173.21:17:08.19#ibcon#about to read 3, iclass 25, count 0 2006.173.21:17:08.21#ibcon#read 3, iclass 25, count 0 2006.173.21:17:08.21#ibcon#about to read 4, iclass 25, count 0 2006.173.21:17:08.21#ibcon#read 4, iclass 25, count 0 2006.173.21:17:08.21#ibcon#about to read 5, iclass 25, count 0 2006.173.21:17:08.21#ibcon#read 5, iclass 25, count 0 2006.173.21:17:08.21#ibcon#about to read 6, iclass 25, count 0 2006.173.21:17:08.21#ibcon#read 6, iclass 25, count 0 2006.173.21:17:08.21#ibcon#end of sib2, iclass 25, count 0 2006.173.21:17:08.21#ibcon#*mode == 0, iclass 25, count 0 2006.173.21:17:08.21#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.21:17:08.21#ibcon#[25=USB\r\n] 2006.173.21:17:08.21#ibcon#*before write, iclass 25, count 0 2006.173.21:17:08.21#ibcon#enter sib2, iclass 25, count 0 2006.173.21:17:08.21#ibcon#flushed, iclass 25, count 0 2006.173.21:17:08.21#ibcon#about to write, iclass 25, count 0 2006.173.21:17:08.21#ibcon#wrote, iclass 25, count 0 2006.173.21:17:08.21#ibcon#about to read 3, iclass 25, count 0 2006.173.21:17:08.24#ibcon#read 3, iclass 25, count 0 2006.173.21:17:08.24#ibcon#about to read 4, iclass 25, count 0 2006.173.21:17:08.24#ibcon#read 4, iclass 25, count 0 2006.173.21:17:08.24#ibcon#about to read 5, iclass 25, count 0 2006.173.21:17:08.24#ibcon#read 5, iclass 25, count 0 2006.173.21:17:08.24#ibcon#about to read 6, iclass 25, count 0 2006.173.21:17:08.24#ibcon#read 6, iclass 25, count 0 2006.173.21:17:08.24#ibcon#end of sib2, iclass 25, count 0 2006.173.21:17:08.24#ibcon#*after write, iclass 25, count 0 2006.173.21:17:08.24#ibcon#*before return 0, iclass 25, count 0 2006.173.21:17:08.24#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.21:17:08.24#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.21:17:08.24#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.21:17:08.24#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.21:17:08.24$vck44/valo=7,864.99 2006.173.21:17:08.24#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.21:17:08.24#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.21:17:08.24#ibcon#ireg 17 cls_cnt 0 2006.173.21:17:08.24#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.21:17:08.24#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.21:17:08.24#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.21:17:08.24#ibcon#enter wrdev, iclass 27, count 0 2006.173.21:17:08.24#ibcon#first serial, iclass 27, count 0 2006.173.21:17:08.24#ibcon#enter sib2, iclass 27, count 0 2006.173.21:17:08.24#ibcon#flushed, iclass 27, count 0 2006.173.21:17:08.24#ibcon#about to write, iclass 27, count 0 2006.173.21:17:08.24#ibcon#wrote, iclass 27, count 0 2006.173.21:17:08.24#ibcon#about to read 3, iclass 27, count 0 2006.173.21:17:08.26#ibcon#read 3, iclass 27, count 0 2006.173.21:17:08.26#ibcon#about to read 4, iclass 27, count 0 2006.173.21:17:08.26#ibcon#read 4, iclass 27, count 0 2006.173.21:17:08.26#ibcon#about to read 5, iclass 27, count 0 2006.173.21:17:08.26#ibcon#read 5, iclass 27, count 0 2006.173.21:17:08.26#ibcon#about to read 6, iclass 27, count 0 2006.173.21:17:08.26#ibcon#read 6, iclass 27, count 0 2006.173.21:17:08.26#ibcon#end of sib2, iclass 27, count 0 2006.173.21:17:08.26#ibcon#*mode == 0, iclass 27, count 0 2006.173.21:17:08.26#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.21:17:08.26#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.21:17:08.26#ibcon#*before write, iclass 27, count 0 2006.173.21:17:08.26#ibcon#enter sib2, iclass 27, count 0 2006.173.21:17:08.26#ibcon#flushed, iclass 27, count 0 2006.173.21:17:08.26#ibcon#about to write, iclass 27, count 0 2006.173.21:17:08.26#ibcon#wrote, iclass 27, count 0 2006.173.21:17:08.26#ibcon#about to read 3, iclass 27, count 0 2006.173.21:17:08.30#ibcon#read 3, iclass 27, count 0 2006.173.21:17:08.30#ibcon#about to read 4, iclass 27, count 0 2006.173.21:17:08.30#ibcon#read 4, iclass 27, count 0 2006.173.21:17:08.30#ibcon#about to read 5, iclass 27, count 0 2006.173.21:17:08.30#ibcon#read 5, iclass 27, count 0 2006.173.21:17:08.30#ibcon#about to read 6, iclass 27, count 0 2006.173.21:17:08.30#ibcon#read 6, iclass 27, count 0 2006.173.21:17:08.30#ibcon#end of sib2, iclass 27, count 0 2006.173.21:17:08.30#ibcon#*after write, iclass 27, count 0 2006.173.21:17:08.30#ibcon#*before return 0, iclass 27, count 0 2006.173.21:17:08.30#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.21:17:08.30#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.21:17:08.30#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.21:17:08.30#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.21:17:08.30$vck44/va=7,4 2006.173.21:17:08.30#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.21:17:08.30#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.21:17:08.30#ibcon#ireg 11 cls_cnt 2 2006.173.21:17:08.30#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.21:17:08.36#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.21:17:08.36#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.21:17:08.36#ibcon#enter wrdev, iclass 29, count 2 2006.173.21:17:08.36#ibcon#first serial, iclass 29, count 2 2006.173.21:17:08.36#ibcon#enter sib2, iclass 29, count 2 2006.173.21:17:08.36#ibcon#flushed, iclass 29, count 2 2006.173.21:17:08.36#ibcon#about to write, iclass 29, count 2 2006.173.21:17:08.36#ibcon#wrote, iclass 29, count 2 2006.173.21:17:08.36#ibcon#about to read 3, iclass 29, count 2 2006.173.21:17:08.38#ibcon#read 3, iclass 29, count 2 2006.173.21:17:08.38#ibcon#about to read 4, iclass 29, count 2 2006.173.21:17:08.38#ibcon#read 4, iclass 29, count 2 2006.173.21:17:08.38#ibcon#about to read 5, iclass 29, count 2 2006.173.21:17:08.38#ibcon#read 5, iclass 29, count 2 2006.173.21:17:08.38#ibcon#about to read 6, iclass 29, count 2 2006.173.21:17:08.38#ibcon#read 6, iclass 29, count 2 2006.173.21:17:08.38#ibcon#end of sib2, iclass 29, count 2 2006.173.21:17:08.38#ibcon#*mode == 0, iclass 29, count 2 2006.173.21:17:08.38#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.21:17:08.38#ibcon#[25=AT07-04\r\n] 2006.173.21:17:08.38#ibcon#*before write, iclass 29, count 2 2006.173.21:17:08.38#ibcon#enter sib2, iclass 29, count 2 2006.173.21:17:08.38#ibcon#flushed, iclass 29, count 2 2006.173.21:17:08.38#ibcon#about to write, iclass 29, count 2 2006.173.21:17:08.38#ibcon#wrote, iclass 29, count 2 2006.173.21:17:08.38#ibcon#about to read 3, iclass 29, count 2 2006.173.21:17:08.41#ibcon#read 3, iclass 29, count 2 2006.173.21:17:08.41#ibcon#about to read 4, iclass 29, count 2 2006.173.21:17:08.41#ibcon#read 4, iclass 29, count 2 2006.173.21:17:08.41#ibcon#about to read 5, iclass 29, count 2 2006.173.21:17:08.41#ibcon#read 5, iclass 29, count 2 2006.173.21:17:08.41#ibcon#about to read 6, iclass 29, count 2 2006.173.21:17:08.41#ibcon#read 6, iclass 29, count 2 2006.173.21:17:08.41#ibcon#end of sib2, iclass 29, count 2 2006.173.21:17:08.41#ibcon#*after write, iclass 29, count 2 2006.173.21:17:08.41#ibcon#*before return 0, iclass 29, count 2 2006.173.21:17:08.41#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.21:17:08.41#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.21:17:08.41#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.21:17:08.41#ibcon#ireg 7 cls_cnt 0 2006.173.21:17:08.41#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.21:17:08.53#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.21:17:08.53#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.21:17:08.53#ibcon#enter wrdev, iclass 29, count 0 2006.173.21:17:08.53#ibcon#first serial, iclass 29, count 0 2006.173.21:17:08.53#ibcon#enter sib2, iclass 29, count 0 2006.173.21:17:08.53#ibcon#flushed, iclass 29, count 0 2006.173.21:17:08.53#ibcon#about to write, iclass 29, count 0 2006.173.21:17:08.53#ibcon#wrote, iclass 29, count 0 2006.173.21:17:08.53#ibcon#about to read 3, iclass 29, count 0 2006.173.21:17:08.55#ibcon#read 3, iclass 29, count 0 2006.173.21:17:08.55#ibcon#about to read 4, iclass 29, count 0 2006.173.21:17:08.55#ibcon#read 4, iclass 29, count 0 2006.173.21:17:08.55#ibcon#about to read 5, iclass 29, count 0 2006.173.21:17:08.55#ibcon#read 5, iclass 29, count 0 2006.173.21:17:08.55#ibcon#about to read 6, iclass 29, count 0 2006.173.21:17:08.55#ibcon#read 6, iclass 29, count 0 2006.173.21:17:08.55#ibcon#end of sib2, iclass 29, count 0 2006.173.21:17:08.55#ibcon#*mode == 0, iclass 29, count 0 2006.173.21:17:08.55#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.21:17:08.55#ibcon#[25=USB\r\n] 2006.173.21:17:08.55#ibcon#*before write, iclass 29, count 0 2006.173.21:17:08.55#ibcon#enter sib2, iclass 29, count 0 2006.173.21:17:08.55#ibcon#flushed, iclass 29, count 0 2006.173.21:17:08.55#ibcon#about to write, iclass 29, count 0 2006.173.21:17:08.55#ibcon#wrote, iclass 29, count 0 2006.173.21:17:08.55#ibcon#about to read 3, iclass 29, count 0 2006.173.21:17:08.58#ibcon#read 3, iclass 29, count 0 2006.173.21:17:08.58#ibcon#about to read 4, iclass 29, count 0 2006.173.21:17:08.58#ibcon#read 4, iclass 29, count 0 2006.173.21:17:08.58#ibcon#about to read 5, iclass 29, count 0 2006.173.21:17:08.58#ibcon#read 5, iclass 29, count 0 2006.173.21:17:08.58#ibcon#about to read 6, iclass 29, count 0 2006.173.21:17:08.58#ibcon#read 6, iclass 29, count 0 2006.173.21:17:08.58#ibcon#end of sib2, iclass 29, count 0 2006.173.21:17:08.58#ibcon#*after write, iclass 29, count 0 2006.173.21:17:08.58#ibcon#*before return 0, iclass 29, count 0 2006.173.21:17:08.58#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.21:17:08.58#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.21:17:08.58#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.21:17:08.58#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.21:17:08.58$vck44/valo=8,884.99 2006.173.21:17:08.58#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.21:17:08.58#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.21:17:08.58#ibcon#ireg 17 cls_cnt 0 2006.173.21:17:08.58#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.21:17:08.58#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.21:17:08.58#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.21:17:08.58#ibcon#enter wrdev, iclass 31, count 0 2006.173.21:17:08.58#ibcon#first serial, iclass 31, count 0 2006.173.21:17:08.58#ibcon#enter sib2, iclass 31, count 0 2006.173.21:17:08.58#ibcon#flushed, iclass 31, count 0 2006.173.21:17:08.58#ibcon#about to write, iclass 31, count 0 2006.173.21:17:08.58#ibcon#wrote, iclass 31, count 0 2006.173.21:17:08.58#ibcon#about to read 3, iclass 31, count 0 2006.173.21:17:08.60#ibcon#read 3, iclass 31, count 0 2006.173.21:17:08.60#ibcon#about to read 4, iclass 31, count 0 2006.173.21:17:08.60#ibcon#read 4, iclass 31, count 0 2006.173.21:17:08.60#ibcon#about to read 5, iclass 31, count 0 2006.173.21:17:08.60#ibcon#read 5, iclass 31, count 0 2006.173.21:17:08.60#ibcon#about to read 6, iclass 31, count 0 2006.173.21:17:08.60#ibcon#read 6, iclass 31, count 0 2006.173.21:17:08.60#ibcon#end of sib2, iclass 31, count 0 2006.173.21:17:08.60#ibcon#*mode == 0, iclass 31, count 0 2006.173.21:17:08.60#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.21:17:08.60#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.21:17:08.60#ibcon#*before write, iclass 31, count 0 2006.173.21:17:08.60#ibcon#enter sib2, iclass 31, count 0 2006.173.21:17:08.60#ibcon#flushed, iclass 31, count 0 2006.173.21:17:08.60#ibcon#about to write, iclass 31, count 0 2006.173.21:17:08.60#ibcon#wrote, iclass 31, count 0 2006.173.21:17:08.60#ibcon#about to read 3, iclass 31, count 0 2006.173.21:17:08.64#ibcon#read 3, iclass 31, count 0 2006.173.21:17:08.64#ibcon#about to read 4, iclass 31, count 0 2006.173.21:17:08.64#ibcon#read 4, iclass 31, count 0 2006.173.21:17:08.64#ibcon#about to read 5, iclass 31, count 0 2006.173.21:17:08.64#ibcon#read 5, iclass 31, count 0 2006.173.21:17:08.64#ibcon#about to read 6, iclass 31, count 0 2006.173.21:17:08.64#ibcon#read 6, iclass 31, count 0 2006.173.21:17:08.64#ibcon#end of sib2, iclass 31, count 0 2006.173.21:17:08.64#ibcon#*after write, iclass 31, count 0 2006.173.21:17:08.64#ibcon#*before return 0, iclass 31, count 0 2006.173.21:17:08.64#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.21:17:08.64#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.21:17:08.64#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.21:17:08.64#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.21:17:08.64$vck44/va=8,4 2006.173.21:17:08.64#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.173.21:17:08.64#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.173.21:17:08.64#ibcon#ireg 11 cls_cnt 2 2006.173.21:17:08.64#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.21:17:08.70#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.21:17:08.70#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.21:17:08.70#ibcon#enter wrdev, iclass 33, count 2 2006.173.21:17:08.70#ibcon#first serial, iclass 33, count 2 2006.173.21:17:08.70#ibcon#enter sib2, iclass 33, count 2 2006.173.21:17:08.70#ibcon#flushed, iclass 33, count 2 2006.173.21:17:08.70#ibcon#about to write, iclass 33, count 2 2006.173.21:17:08.70#ibcon#wrote, iclass 33, count 2 2006.173.21:17:08.70#ibcon#about to read 3, iclass 33, count 2 2006.173.21:17:08.72#ibcon#read 3, iclass 33, count 2 2006.173.21:17:08.72#ibcon#about to read 4, iclass 33, count 2 2006.173.21:17:08.72#ibcon#read 4, iclass 33, count 2 2006.173.21:17:08.72#ibcon#about to read 5, iclass 33, count 2 2006.173.21:17:08.72#ibcon#read 5, iclass 33, count 2 2006.173.21:17:08.72#ibcon#about to read 6, iclass 33, count 2 2006.173.21:17:08.72#ibcon#read 6, iclass 33, count 2 2006.173.21:17:08.72#ibcon#end of sib2, iclass 33, count 2 2006.173.21:17:08.72#ibcon#*mode == 0, iclass 33, count 2 2006.173.21:17:08.72#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.173.21:17:08.72#ibcon#[25=AT08-04\r\n] 2006.173.21:17:08.72#ibcon#*before write, iclass 33, count 2 2006.173.21:17:08.72#ibcon#enter sib2, iclass 33, count 2 2006.173.21:17:08.72#ibcon#flushed, iclass 33, count 2 2006.173.21:17:08.72#ibcon#about to write, iclass 33, count 2 2006.173.21:17:08.72#ibcon#wrote, iclass 33, count 2 2006.173.21:17:08.72#ibcon#about to read 3, iclass 33, count 2 2006.173.21:17:08.75#ibcon#read 3, iclass 33, count 2 2006.173.21:17:08.75#ibcon#about to read 4, iclass 33, count 2 2006.173.21:17:08.75#ibcon#read 4, iclass 33, count 2 2006.173.21:17:08.75#ibcon#about to read 5, iclass 33, count 2 2006.173.21:17:08.75#ibcon#read 5, iclass 33, count 2 2006.173.21:17:08.75#ibcon#about to read 6, iclass 33, count 2 2006.173.21:17:08.75#ibcon#read 6, iclass 33, count 2 2006.173.21:17:08.75#ibcon#end of sib2, iclass 33, count 2 2006.173.21:17:08.75#ibcon#*after write, iclass 33, count 2 2006.173.21:17:08.75#ibcon#*before return 0, iclass 33, count 2 2006.173.21:17:08.75#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.21:17:08.75#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.173.21:17:08.75#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.173.21:17:08.75#ibcon#ireg 7 cls_cnt 0 2006.173.21:17:08.75#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.21:17:08.87#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.21:17:08.87#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.21:17:08.87#ibcon#enter wrdev, iclass 33, count 0 2006.173.21:17:08.87#ibcon#first serial, iclass 33, count 0 2006.173.21:17:08.87#ibcon#enter sib2, iclass 33, count 0 2006.173.21:17:08.87#ibcon#flushed, iclass 33, count 0 2006.173.21:17:08.87#ibcon#about to write, iclass 33, count 0 2006.173.21:17:08.87#ibcon#wrote, iclass 33, count 0 2006.173.21:17:08.87#ibcon#about to read 3, iclass 33, count 0 2006.173.21:17:08.89#ibcon#read 3, iclass 33, count 0 2006.173.21:17:08.89#ibcon#about to read 4, iclass 33, count 0 2006.173.21:17:08.89#ibcon#read 4, iclass 33, count 0 2006.173.21:17:08.89#ibcon#about to read 5, iclass 33, count 0 2006.173.21:17:08.89#ibcon#read 5, iclass 33, count 0 2006.173.21:17:08.89#ibcon#about to read 6, iclass 33, count 0 2006.173.21:17:08.89#ibcon#read 6, iclass 33, count 0 2006.173.21:17:08.89#ibcon#end of sib2, iclass 33, count 0 2006.173.21:17:08.89#ibcon#*mode == 0, iclass 33, count 0 2006.173.21:17:08.89#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.21:17:08.89#ibcon#[25=USB\r\n] 2006.173.21:17:08.89#ibcon#*before write, iclass 33, count 0 2006.173.21:17:08.89#ibcon#enter sib2, iclass 33, count 0 2006.173.21:17:08.89#ibcon#flushed, iclass 33, count 0 2006.173.21:17:08.89#ibcon#about to write, iclass 33, count 0 2006.173.21:17:08.89#ibcon#wrote, iclass 33, count 0 2006.173.21:17:08.89#ibcon#about to read 3, iclass 33, count 0 2006.173.21:17:08.92#ibcon#read 3, iclass 33, count 0 2006.173.21:17:08.92#ibcon#about to read 4, iclass 33, count 0 2006.173.21:17:08.92#ibcon#read 4, iclass 33, count 0 2006.173.21:17:08.92#ibcon#about to read 5, iclass 33, count 0 2006.173.21:17:08.92#ibcon#read 5, iclass 33, count 0 2006.173.21:17:08.92#ibcon#about to read 6, iclass 33, count 0 2006.173.21:17:08.92#ibcon#read 6, iclass 33, count 0 2006.173.21:17:08.92#ibcon#end of sib2, iclass 33, count 0 2006.173.21:17:08.92#ibcon#*after write, iclass 33, count 0 2006.173.21:17:08.92#ibcon#*before return 0, iclass 33, count 0 2006.173.21:17:08.92#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.21:17:08.92#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.173.21:17:08.92#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.21:17:08.92#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.21:17:08.92$vck44/vblo=1,629.99 2006.173.21:17:08.92#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.21:17:08.92#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.21:17:08.92#ibcon#ireg 17 cls_cnt 0 2006.173.21:17:08.92#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.21:17:08.92#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.21:17:08.92#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.21:17:08.92#ibcon#enter wrdev, iclass 35, count 0 2006.173.21:17:08.92#ibcon#first serial, iclass 35, count 0 2006.173.21:17:08.92#ibcon#enter sib2, iclass 35, count 0 2006.173.21:17:08.92#ibcon#flushed, iclass 35, count 0 2006.173.21:17:08.92#ibcon#about to write, iclass 35, count 0 2006.173.21:17:08.92#ibcon#wrote, iclass 35, count 0 2006.173.21:17:08.92#ibcon#about to read 3, iclass 35, count 0 2006.173.21:17:08.94#ibcon#read 3, iclass 35, count 0 2006.173.21:17:08.94#ibcon#about to read 4, iclass 35, count 0 2006.173.21:17:08.94#ibcon#read 4, iclass 35, count 0 2006.173.21:17:08.94#ibcon#about to read 5, iclass 35, count 0 2006.173.21:17:08.94#ibcon#read 5, iclass 35, count 0 2006.173.21:17:08.94#ibcon#about to read 6, iclass 35, count 0 2006.173.21:17:08.94#ibcon#read 6, iclass 35, count 0 2006.173.21:17:08.94#ibcon#end of sib2, iclass 35, count 0 2006.173.21:17:08.94#ibcon#*mode == 0, iclass 35, count 0 2006.173.21:17:08.94#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.21:17:08.94#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.21:17:08.94#ibcon#*before write, iclass 35, count 0 2006.173.21:17:08.94#ibcon#enter sib2, iclass 35, count 0 2006.173.21:17:08.94#ibcon#flushed, iclass 35, count 0 2006.173.21:17:08.94#ibcon#about to write, iclass 35, count 0 2006.173.21:17:08.94#ibcon#wrote, iclass 35, count 0 2006.173.21:17:08.94#ibcon#about to read 3, iclass 35, count 0 2006.173.21:17:08.98#ibcon#read 3, iclass 35, count 0 2006.173.21:17:08.98#ibcon#about to read 4, iclass 35, count 0 2006.173.21:17:08.98#ibcon#read 4, iclass 35, count 0 2006.173.21:17:08.98#ibcon#about to read 5, iclass 35, count 0 2006.173.21:17:08.98#ibcon#read 5, iclass 35, count 0 2006.173.21:17:08.98#ibcon#about to read 6, iclass 35, count 0 2006.173.21:17:08.98#ibcon#read 6, iclass 35, count 0 2006.173.21:17:08.98#ibcon#end of sib2, iclass 35, count 0 2006.173.21:17:08.98#ibcon#*after write, iclass 35, count 0 2006.173.21:17:08.98#ibcon#*before return 0, iclass 35, count 0 2006.173.21:17:08.98#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.21:17:08.98#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.21:17:08.98#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.21:17:08.98#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.21:17:08.98$vck44/vb=1,4 2006.173.21:17:08.98#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.173.21:17:08.98#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.173.21:17:08.98#ibcon#ireg 11 cls_cnt 2 2006.173.21:17:08.98#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.21:17:08.98#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.21:17:08.98#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.21:17:08.98#ibcon#enter wrdev, iclass 37, count 2 2006.173.21:17:08.98#ibcon#first serial, iclass 37, count 2 2006.173.21:17:08.98#ibcon#enter sib2, iclass 37, count 2 2006.173.21:17:08.98#ibcon#flushed, iclass 37, count 2 2006.173.21:17:08.98#ibcon#about to write, iclass 37, count 2 2006.173.21:17:08.98#ibcon#wrote, iclass 37, count 2 2006.173.21:17:08.98#ibcon#about to read 3, iclass 37, count 2 2006.173.21:17:09.00#ibcon#read 3, iclass 37, count 2 2006.173.21:17:09.00#ibcon#about to read 4, iclass 37, count 2 2006.173.21:17:09.00#ibcon#read 4, iclass 37, count 2 2006.173.21:17:09.00#ibcon#about to read 5, iclass 37, count 2 2006.173.21:17:09.00#ibcon#read 5, iclass 37, count 2 2006.173.21:17:09.00#ibcon#about to read 6, iclass 37, count 2 2006.173.21:17:09.00#ibcon#read 6, iclass 37, count 2 2006.173.21:17:09.00#ibcon#end of sib2, iclass 37, count 2 2006.173.21:17:09.00#ibcon#*mode == 0, iclass 37, count 2 2006.173.21:17:09.00#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.173.21:17:09.00#ibcon#[27=AT01-04\r\n] 2006.173.21:17:09.00#ibcon#*before write, iclass 37, count 2 2006.173.21:17:09.00#ibcon#enter sib2, iclass 37, count 2 2006.173.21:17:09.00#ibcon#flushed, iclass 37, count 2 2006.173.21:17:09.00#ibcon#about to write, iclass 37, count 2 2006.173.21:17:09.00#ibcon#wrote, iclass 37, count 2 2006.173.21:17:09.00#ibcon#about to read 3, iclass 37, count 2 2006.173.21:17:09.03#ibcon#read 3, iclass 37, count 2 2006.173.21:17:09.03#ibcon#about to read 4, iclass 37, count 2 2006.173.21:17:09.03#ibcon#read 4, iclass 37, count 2 2006.173.21:17:09.03#ibcon#about to read 5, iclass 37, count 2 2006.173.21:17:09.03#ibcon#read 5, iclass 37, count 2 2006.173.21:17:09.03#ibcon#about to read 6, iclass 37, count 2 2006.173.21:17:09.03#ibcon#read 6, iclass 37, count 2 2006.173.21:17:09.03#ibcon#end of sib2, iclass 37, count 2 2006.173.21:17:09.03#ibcon#*after write, iclass 37, count 2 2006.173.21:17:09.03#ibcon#*before return 0, iclass 37, count 2 2006.173.21:17:09.03#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.21:17:09.03#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.173.21:17:09.03#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.173.21:17:09.03#ibcon#ireg 7 cls_cnt 0 2006.173.21:17:09.03#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.21:17:09.15#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.21:17:09.15#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.21:17:09.15#ibcon#enter wrdev, iclass 37, count 0 2006.173.21:17:09.15#ibcon#first serial, iclass 37, count 0 2006.173.21:17:09.15#ibcon#enter sib2, iclass 37, count 0 2006.173.21:17:09.15#ibcon#flushed, iclass 37, count 0 2006.173.21:17:09.15#ibcon#about to write, iclass 37, count 0 2006.173.21:17:09.15#ibcon#wrote, iclass 37, count 0 2006.173.21:17:09.15#ibcon#about to read 3, iclass 37, count 0 2006.173.21:17:09.17#ibcon#read 3, iclass 37, count 0 2006.173.21:17:09.17#ibcon#about to read 4, iclass 37, count 0 2006.173.21:17:09.17#ibcon#read 4, iclass 37, count 0 2006.173.21:17:09.17#ibcon#about to read 5, iclass 37, count 0 2006.173.21:17:09.17#ibcon#read 5, iclass 37, count 0 2006.173.21:17:09.17#ibcon#about to read 6, iclass 37, count 0 2006.173.21:17:09.17#ibcon#read 6, iclass 37, count 0 2006.173.21:17:09.17#ibcon#end of sib2, iclass 37, count 0 2006.173.21:17:09.17#ibcon#*mode == 0, iclass 37, count 0 2006.173.21:17:09.17#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.21:17:09.17#ibcon#[27=USB\r\n] 2006.173.21:17:09.17#ibcon#*before write, iclass 37, count 0 2006.173.21:17:09.17#ibcon#enter sib2, iclass 37, count 0 2006.173.21:17:09.17#ibcon#flushed, iclass 37, count 0 2006.173.21:17:09.17#ibcon#about to write, iclass 37, count 0 2006.173.21:17:09.17#ibcon#wrote, iclass 37, count 0 2006.173.21:17:09.17#ibcon#about to read 3, iclass 37, count 0 2006.173.21:17:09.20#ibcon#read 3, iclass 37, count 0 2006.173.21:17:09.20#ibcon#about to read 4, iclass 37, count 0 2006.173.21:17:09.20#ibcon#read 4, iclass 37, count 0 2006.173.21:17:09.20#ibcon#about to read 5, iclass 37, count 0 2006.173.21:17:09.20#ibcon#read 5, iclass 37, count 0 2006.173.21:17:09.20#ibcon#about to read 6, iclass 37, count 0 2006.173.21:17:09.20#ibcon#read 6, iclass 37, count 0 2006.173.21:17:09.20#ibcon#end of sib2, iclass 37, count 0 2006.173.21:17:09.20#ibcon#*after write, iclass 37, count 0 2006.173.21:17:09.20#ibcon#*before return 0, iclass 37, count 0 2006.173.21:17:09.20#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.21:17:09.20#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.173.21:17:09.20#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.21:17:09.20#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.21:17:09.20$vck44/vblo=2,634.99 2006.173.21:17:09.20#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.21:17:09.20#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.21:17:09.20#ibcon#ireg 17 cls_cnt 0 2006.173.21:17:09.20#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.21:17:09.20#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.21:17:09.20#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.21:17:09.20#ibcon#enter wrdev, iclass 39, count 0 2006.173.21:17:09.20#ibcon#first serial, iclass 39, count 0 2006.173.21:17:09.20#ibcon#enter sib2, iclass 39, count 0 2006.173.21:17:09.20#ibcon#flushed, iclass 39, count 0 2006.173.21:17:09.20#ibcon#about to write, iclass 39, count 0 2006.173.21:17:09.20#ibcon#wrote, iclass 39, count 0 2006.173.21:17:09.20#ibcon#about to read 3, iclass 39, count 0 2006.173.21:17:09.22#ibcon#read 3, iclass 39, count 0 2006.173.21:17:09.22#ibcon#about to read 4, iclass 39, count 0 2006.173.21:17:09.22#ibcon#read 4, iclass 39, count 0 2006.173.21:17:09.22#ibcon#about to read 5, iclass 39, count 0 2006.173.21:17:09.22#ibcon#read 5, iclass 39, count 0 2006.173.21:17:09.22#ibcon#about to read 6, iclass 39, count 0 2006.173.21:17:09.22#ibcon#read 6, iclass 39, count 0 2006.173.21:17:09.22#ibcon#end of sib2, iclass 39, count 0 2006.173.21:17:09.22#ibcon#*mode == 0, iclass 39, count 0 2006.173.21:17:09.22#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.21:17:09.22#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.21:17:09.22#ibcon#*before write, iclass 39, count 0 2006.173.21:17:09.22#ibcon#enter sib2, iclass 39, count 0 2006.173.21:17:09.22#ibcon#flushed, iclass 39, count 0 2006.173.21:17:09.22#ibcon#about to write, iclass 39, count 0 2006.173.21:17:09.22#ibcon#wrote, iclass 39, count 0 2006.173.21:17:09.22#ibcon#about to read 3, iclass 39, count 0 2006.173.21:17:09.26#ibcon#read 3, iclass 39, count 0 2006.173.21:17:09.26#ibcon#about to read 4, iclass 39, count 0 2006.173.21:17:09.26#ibcon#read 4, iclass 39, count 0 2006.173.21:17:09.26#ibcon#about to read 5, iclass 39, count 0 2006.173.21:17:09.26#ibcon#read 5, iclass 39, count 0 2006.173.21:17:09.26#ibcon#about to read 6, iclass 39, count 0 2006.173.21:17:09.26#ibcon#read 6, iclass 39, count 0 2006.173.21:17:09.26#ibcon#end of sib2, iclass 39, count 0 2006.173.21:17:09.26#ibcon#*after write, iclass 39, count 0 2006.173.21:17:09.26#ibcon#*before return 0, iclass 39, count 0 2006.173.21:17:09.26#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.21:17:09.26#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.21:17:09.26#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.21:17:09.26#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.21:17:09.26$vck44/vb=2,4 2006.173.21:17:09.26#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.21:17:09.26#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.21:17:09.26#ibcon#ireg 11 cls_cnt 2 2006.173.21:17:09.26#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.21:17:09.32#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.21:17:09.32#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.21:17:09.32#ibcon#enter wrdev, iclass 3, count 2 2006.173.21:17:09.32#ibcon#first serial, iclass 3, count 2 2006.173.21:17:09.32#ibcon#enter sib2, iclass 3, count 2 2006.173.21:17:09.32#ibcon#flushed, iclass 3, count 2 2006.173.21:17:09.32#ibcon#about to write, iclass 3, count 2 2006.173.21:17:09.32#ibcon#wrote, iclass 3, count 2 2006.173.21:17:09.32#ibcon#about to read 3, iclass 3, count 2 2006.173.21:17:09.34#ibcon#read 3, iclass 3, count 2 2006.173.21:17:09.34#ibcon#about to read 4, iclass 3, count 2 2006.173.21:17:09.34#ibcon#read 4, iclass 3, count 2 2006.173.21:17:09.34#ibcon#about to read 5, iclass 3, count 2 2006.173.21:17:09.34#ibcon#read 5, iclass 3, count 2 2006.173.21:17:09.34#ibcon#about to read 6, iclass 3, count 2 2006.173.21:17:09.34#ibcon#read 6, iclass 3, count 2 2006.173.21:17:09.34#ibcon#end of sib2, iclass 3, count 2 2006.173.21:17:09.34#ibcon#*mode == 0, iclass 3, count 2 2006.173.21:17:09.34#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.21:17:09.34#ibcon#[27=AT02-04\r\n] 2006.173.21:17:09.34#ibcon#*before write, iclass 3, count 2 2006.173.21:17:09.34#ibcon#enter sib2, iclass 3, count 2 2006.173.21:17:09.34#ibcon#flushed, iclass 3, count 2 2006.173.21:17:09.34#ibcon#about to write, iclass 3, count 2 2006.173.21:17:09.34#ibcon#wrote, iclass 3, count 2 2006.173.21:17:09.34#ibcon#about to read 3, iclass 3, count 2 2006.173.21:17:09.37#ibcon#read 3, iclass 3, count 2 2006.173.21:17:09.37#ibcon#about to read 4, iclass 3, count 2 2006.173.21:17:09.37#ibcon#read 4, iclass 3, count 2 2006.173.21:17:09.37#ibcon#about to read 5, iclass 3, count 2 2006.173.21:17:09.37#ibcon#read 5, iclass 3, count 2 2006.173.21:17:09.37#ibcon#about to read 6, iclass 3, count 2 2006.173.21:17:09.37#ibcon#read 6, iclass 3, count 2 2006.173.21:17:09.37#ibcon#end of sib2, iclass 3, count 2 2006.173.21:17:09.37#ibcon#*after write, iclass 3, count 2 2006.173.21:17:09.37#ibcon#*before return 0, iclass 3, count 2 2006.173.21:17:09.37#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.21:17:09.37#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.21:17:09.37#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.21:17:09.37#ibcon#ireg 7 cls_cnt 0 2006.173.21:17:09.37#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.21:17:09.49#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.21:17:09.49#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.21:17:09.49#ibcon#enter wrdev, iclass 3, count 0 2006.173.21:17:09.49#ibcon#first serial, iclass 3, count 0 2006.173.21:17:09.49#ibcon#enter sib2, iclass 3, count 0 2006.173.21:17:09.49#ibcon#flushed, iclass 3, count 0 2006.173.21:17:09.49#ibcon#about to write, iclass 3, count 0 2006.173.21:17:09.49#ibcon#wrote, iclass 3, count 0 2006.173.21:17:09.49#ibcon#about to read 3, iclass 3, count 0 2006.173.21:17:09.51#ibcon#read 3, iclass 3, count 0 2006.173.21:17:09.51#ibcon#about to read 4, iclass 3, count 0 2006.173.21:17:09.51#ibcon#read 4, iclass 3, count 0 2006.173.21:17:09.51#ibcon#about to read 5, iclass 3, count 0 2006.173.21:17:09.51#ibcon#read 5, iclass 3, count 0 2006.173.21:17:09.51#ibcon#about to read 6, iclass 3, count 0 2006.173.21:17:09.51#ibcon#read 6, iclass 3, count 0 2006.173.21:17:09.51#ibcon#end of sib2, iclass 3, count 0 2006.173.21:17:09.51#ibcon#*mode == 0, iclass 3, count 0 2006.173.21:17:09.51#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.21:17:09.51#ibcon#[27=USB\r\n] 2006.173.21:17:09.51#ibcon#*before write, iclass 3, count 0 2006.173.21:17:09.51#ibcon#enter sib2, iclass 3, count 0 2006.173.21:17:09.51#ibcon#flushed, iclass 3, count 0 2006.173.21:17:09.51#ibcon#about to write, iclass 3, count 0 2006.173.21:17:09.51#ibcon#wrote, iclass 3, count 0 2006.173.21:17:09.51#ibcon#about to read 3, iclass 3, count 0 2006.173.21:17:09.54#ibcon#read 3, iclass 3, count 0 2006.173.21:17:09.54#ibcon#about to read 4, iclass 3, count 0 2006.173.21:17:09.54#ibcon#read 4, iclass 3, count 0 2006.173.21:17:09.54#ibcon#about to read 5, iclass 3, count 0 2006.173.21:17:09.54#ibcon#read 5, iclass 3, count 0 2006.173.21:17:09.54#ibcon#about to read 6, iclass 3, count 0 2006.173.21:17:09.54#ibcon#read 6, iclass 3, count 0 2006.173.21:17:09.54#ibcon#end of sib2, iclass 3, count 0 2006.173.21:17:09.54#ibcon#*after write, iclass 3, count 0 2006.173.21:17:09.54#ibcon#*before return 0, iclass 3, count 0 2006.173.21:17:09.54#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.21:17:09.54#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.21:17:09.54#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.21:17:09.54#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.21:17:09.54$vck44/vblo=3,649.99 2006.173.21:17:09.54#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.21:17:09.54#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.21:17:09.54#ibcon#ireg 17 cls_cnt 0 2006.173.21:17:09.54#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.21:17:09.54#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.21:17:09.54#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.21:17:09.54#ibcon#enter wrdev, iclass 5, count 0 2006.173.21:17:09.54#ibcon#first serial, iclass 5, count 0 2006.173.21:17:09.54#ibcon#enter sib2, iclass 5, count 0 2006.173.21:17:09.54#ibcon#flushed, iclass 5, count 0 2006.173.21:17:09.54#ibcon#about to write, iclass 5, count 0 2006.173.21:17:09.54#ibcon#wrote, iclass 5, count 0 2006.173.21:17:09.54#ibcon#about to read 3, iclass 5, count 0 2006.173.21:17:09.56#ibcon#read 3, iclass 5, count 0 2006.173.21:17:09.56#ibcon#about to read 4, iclass 5, count 0 2006.173.21:17:09.56#ibcon#read 4, iclass 5, count 0 2006.173.21:17:09.56#ibcon#about to read 5, iclass 5, count 0 2006.173.21:17:09.56#ibcon#read 5, iclass 5, count 0 2006.173.21:17:09.56#ibcon#about to read 6, iclass 5, count 0 2006.173.21:17:09.56#ibcon#read 6, iclass 5, count 0 2006.173.21:17:09.56#ibcon#end of sib2, iclass 5, count 0 2006.173.21:17:09.56#ibcon#*mode == 0, iclass 5, count 0 2006.173.21:17:09.56#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.21:17:09.56#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.21:17:09.56#ibcon#*before write, iclass 5, count 0 2006.173.21:17:09.56#ibcon#enter sib2, iclass 5, count 0 2006.173.21:17:09.56#ibcon#flushed, iclass 5, count 0 2006.173.21:17:09.56#ibcon#about to write, iclass 5, count 0 2006.173.21:17:09.56#ibcon#wrote, iclass 5, count 0 2006.173.21:17:09.56#ibcon#about to read 3, iclass 5, count 0 2006.173.21:17:09.60#ibcon#read 3, iclass 5, count 0 2006.173.21:17:09.60#ibcon#about to read 4, iclass 5, count 0 2006.173.21:17:09.60#ibcon#read 4, iclass 5, count 0 2006.173.21:17:09.60#ibcon#about to read 5, iclass 5, count 0 2006.173.21:17:09.60#ibcon#read 5, iclass 5, count 0 2006.173.21:17:09.60#ibcon#about to read 6, iclass 5, count 0 2006.173.21:17:09.60#ibcon#read 6, iclass 5, count 0 2006.173.21:17:09.60#ibcon#end of sib2, iclass 5, count 0 2006.173.21:17:09.60#ibcon#*after write, iclass 5, count 0 2006.173.21:17:09.60#ibcon#*before return 0, iclass 5, count 0 2006.173.21:17:09.60#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.21:17:09.60#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.21:17:09.60#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.21:17:09.60#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.21:17:09.60$vck44/vb=3,4 2006.173.21:17:09.60#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.173.21:17:09.60#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.173.21:17:09.60#ibcon#ireg 11 cls_cnt 2 2006.173.21:17:09.60#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.21:17:09.66#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.21:17:09.66#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.21:17:09.66#ibcon#enter wrdev, iclass 7, count 2 2006.173.21:17:09.66#ibcon#first serial, iclass 7, count 2 2006.173.21:17:09.66#ibcon#enter sib2, iclass 7, count 2 2006.173.21:17:09.66#ibcon#flushed, iclass 7, count 2 2006.173.21:17:09.66#ibcon#about to write, iclass 7, count 2 2006.173.21:17:09.66#ibcon#wrote, iclass 7, count 2 2006.173.21:17:09.66#ibcon#about to read 3, iclass 7, count 2 2006.173.21:17:09.68#ibcon#read 3, iclass 7, count 2 2006.173.21:17:09.68#ibcon#about to read 4, iclass 7, count 2 2006.173.21:17:09.68#ibcon#read 4, iclass 7, count 2 2006.173.21:17:09.68#ibcon#about to read 5, iclass 7, count 2 2006.173.21:17:09.68#ibcon#read 5, iclass 7, count 2 2006.173.21:17:09.68#ibcon#about to read 6, iclass 7, count 2 2006.173.21:17:09.68#ibcon#read 6, iclass 7, count 2 2006.173.21:17:09.68#ibcon#end of sib2, iclass 7, count 2 2006.173.21:17:09.68#ibcon#*mode == 0, iclass 7, count 2 2006.173.21:17:09.68#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.173.21:17:09.68#ibcon#[27=AT03-04\r\n] 2006.173.21:17:09.68#ibcon#*before write, iclass 7, count 2 2006.173.21:17:09.68#ibcon#enter sib2, iclass 7, count 2 2006.173.21:17:09.68#ibcon#flushed, iclass 7, count 2 2006.173.21:17:09.68#ibcon#about to write, iclass 7, count 2 2006.173.21:17:09.68#ibcon#wrote, iclass 7, count 2 2006.173.21:17:09.68#ibcon#about to read 3, iclass 7, count 2 2006.173.21:17:09.71#ibcon#read 3, iclass 7, count 2 2006.173.21:17:09.71#ibcon#about to read 4, iclass 7, count 2 2006.173.21:17:09.71#ibcon#read 4, iclass 7, count 2 2006.173.21:17:09.71#ibcon#about to read 5, iclass 7, count 2 2006.173.21:17:09.71#ibcon#read 5, iclass 7, count 2 2006.173.21:17:09.71#ibcon#about to read 6, iclass 7, count 2 2006.173.21:17:09.71#ibcon#read 6, iclass 7, count 2 2006.173.21:17:09.71#ibcon#end of sib2, iclass 7, count 2 2006.173.21:17:09.71#ibcon#*after write, iclass 7, count 2 2006.173.21:17:09.71#ibcon#*before return 0, iclass 7, count 2 2006.173.21:17:09.71#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.21:17:09.71#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.173.21:17:09.71#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.173.21:17:09.71#ibcon#ireg 7 cls_cnt 0 2006.173.21:17:09.71#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.21:17:09.83#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.21:17:09.83#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.21:17:09.83#ibcon#enter wrdev, iclass 7, count 0 2006.173.21:17:09.83#ibcon#first serial, iclass 7, count 0 2006.173.21:17:09.83#ibcon#enter sib2, iclass 7, count 0 2006.173.21:17:09.83#ibcon#flushed, iclass 7, count 0 2006.173.21:17:09.83#ibcon#about to write, iclass 7, count 0 2006.173.21:17:09.83#ibcon#wrote, iclass 7, count 0 2006.173.21:17:09.83#ibcon#about to read 3, iclass 7, count 0 2006.173.21:17:09.85#ibcon#read 3, iclass 7, count 0 2006.173.21:17:09.85#ibcon#about to read 4, iclass 7, count 0 2006.173.21:17:09.85#ibcon#read 4, iclass 7, count 0 2006.173.21:17:09.85#ibcon#about to read 5, iclass 7, count 0 2006.173.21:17:09.85#ibcon#read 5, iclass 7, count 0 2006.173.21:17:09.85#ibcon#about to read 6, iclass 7, count 0 2006.173.21:17:09.85#ibcon#read 6, iclass 7, count 0 2006.173.21:17:09.85#ibcon#end of sib2, iclass 7, count 0 2006.173.21:17:09.85#ibcon#*mode == 0, iclass 7, count 0 2006.173.21:17:09.85#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.21:17:09.85#ibcon#[27=USB\r\n] 2006.173.21:17:09.85#ibcon#*before write, iclass 7, count 0 2006.173.21:17:09.85#ibcon#enter sib2, iclass 7, count 0 2006.173.21:17:09.85#ibcon#flushed, iclass 7, count 0 2006.173.21:17:09.85#ibcon#about to write, iclass 7, count 0 2006.173.21:17:09.85#ibcon#wrote, iclass 7, count 0 2006.173.21:17:09.85#ibcon#about to read 3, iclass 7, count 0 2006.173.21:17:09.88#ibcon#read 3, iclass 7, count 0 2006.173.21:17:09.88#ibcon#about to read 4, iclass 7, count 0 2006.173.21:17:09.88#ibcon#read 4, iclass 7, count 0 2006.173.21:17:09.88#ibcon#about to read 5, iclass 7, count 0 2006.173.21:17:09.88#ibcon#read 5, iclass 7, count 0 2006.173.21:17:09.88#ibcon#about to read 6, iclass 7, count 0 2006.173.21:17:09.88#ibcon#read 6, iclass 7, count 0 2006.173.21:17:09.88#ibcon#end of sib2, iclass 7, count 0 2006.173.21:17:09.88#ibcon#*after write, iclass 7, count 0 2006.173.21:17:09.88#ibcon#*before return 0, iclass 7, count 0 2006.173.21:17:09.88#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.21:17:09.88#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.173.21:17:09.88#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.21:17:09.88#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.21:17:09.88$vck44/vblo=4,679.99 2006.173.21:17:09.88#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.21:17:09.88#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.21:17:09.88#ibcon#ireg 17 cls_cnt 0 2006.173.21:17:09.88#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.21:17:09.88#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.21:17:09.88#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.21:17:09.88#ibcon#enter wrdev, iclass 11, count 0 2006.173.21:17:09.88#ibcon#first serial, iclass 11, count 0 2006.173.21:17:09.88#ibcon#enter sib2, iclass 11, count 0 2006.173.21:17:09.88#ibcon#flushed, iclass 11, count 0 2006.173.21:17:09.88#ibcon#about to write, iclass 11, count 0 2006.173.21:17:09.88#ibcon#wrote, iclass 11, count 0 2006.173.21:17:09.88#ibcon#about to read 3, iclass 11, count 0 2006.173.21:17:09.90#ibcon#read 3, iclass 11, count 0 2006.173.21:17:09.90#ibcon#about to read 4, iclass 11, count 0 2006.173.21:17:09.90#ibcon#read 4, iclass 11, count 0 2006.173.21:17:09.90#ibcon#about to read 5, iclass 11, count 0 2006.173.21:17:09.90#ibcon#read 5, iclass 11, count 0 2006.173.21:17:09.90#ibcon#about to read 6, iclass 11, count 0 2006.173.21:17:09.90#ibcon#read 6, iclass 11, count 0 2006.173.21:17:09.90#ibcon#end of sib2, iclass 11, count 0 2006.173.21:17:09.90#ibcon#*mode == 0, iclass 11, count 0 2006.173.21:17:09.90#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.21:17:09.90#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.21:17:09.90#ibcon#*before write, iclass 11, count 0 2006.173.21:17:09.90#ibcon#enter sib2, iclass 11, count 0 2006.173.21:17:09.90#ibcon#flushed, iclass 11, count 0 2006.173.21:17:09.90#ibcon#about to write, iclass 11, count 0 2006.173.21:17:09.90#ibcon#wrote, iclass 11, count 0 2006.173.21:17:09.90#ibcon#about to read 3, iclass 11, count 0 2006.173.21:17:09.94#ibcon#read 3, iclass 11, count 0 2006.173.21:17:09.94#ibcon#about to read 4, iclass 11, count 0 2006.173.21:17:09.94#ibcon#read 4, iclass 11, count 0 2006.173.21:17:09.94#ibcon#about to read 5, iclass 11, count 0 2006.173.21:17:09.94#ibcon#read 5, iclass 11, count 0 2006.173.21:17:09.94#ibcon#about to read 6, iclass 11, count 0 2006.173.21:17:09.94#ibcon#read 6, iclass 11, count 0 2006.173.21:17:09.94#ibcon#end of sib2, iclass 11, count 0 2006.173.21:17:09.94#ibcon#*after write, iclass 11, count 0 2006.173.21:17:09.94#ibcon#*before return 0, iclass 11, count 0 2006.173.21:17:09.94#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.21:17:09.94#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.21:17:09.94#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.21:17:09.94#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.21:17:09.94$vck44/vb=4,4 2006.173.21:17:09.94#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.173.21:17:09.94#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.173.21:17:09.94#ibcon#ireg 11 cls_cnt 2 2006.173.21:17:09.94#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.21:17:10.00#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.21:17:10.00#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.21:17:10.00#ibcon#enter wrdev, iclass 13, count 2 2006.173.21:17:10.00#ibcon#first serial, iclass 13, count 2 2006.173.21:17:10.00#ibcon#enter sib2, iclass 13, count 2 2006.173.21:17:10.00#ibcon#flushed, iclass 13, count 2 2006.173.21:17:10.00#ibcon#about to write, iclass 13, count 2 2006.173.21:17:10.00#ibcon#wrote, iclass 13, count 2 2006.173.21:17:10.00#ibcon#about to read 3, iclass 13, count 2 2006.173.21:17:10.02#ibcon#read 3, iclass 13, count 2 2006.173.21:17:10.02#ibcon#about to read 4, iclass 13, count 2 2006.173.21:17:10.02#ibcon#read 4, iclass 13, count 2 2006.173.21:17:10.02#ibcon#about to read 5, iclass 13, count 2 2006.173.21:17:10.02#ibcon#read 5, iclass 13, count 2 2006.173.21:17:10.02#ibcon#about to read 6, iclass 13, count 2 2006.173.21:17:10.02#ibcon#read 6, iclass 13, count 2 2006.173.21:17:10.02#ibcon#end of sib2, iclass 13, count 2 2006.173.21:17:10.02#ibcon#*mode == 0, iclass 13, count 2 2006.173.21:17:10.02#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.173.21:17:10.02#ibcon#[27=AT04-04\r\n] 2006.173.21:17:10.02#ibcon#*before write, iclass 13, count 2 2006.173.21:17:10.02#ibcon#enter sib2, iclass 13, count 2 2006.173.21:17:10.02#ibcon#flushed, iclass 13, count 2 2006.173.21:17:10.02#ibcon#about to write, iclass 13, count 2 2006.173.21:17:10.02#ibcon#wrote, iclass 13, count 2 2006.173.21:17:10.02#ibcon#about to read 3, iclass 13, count 2 2006.173.21:17:10.05#ibcon#read 3, iclass 13, count 2 2006.173.21:17:10.05#ibcon#about to read 4, iclass 13, count 2 2006.173.21:17:10.05#ibcon#read 4, iclass 13, count 2 2006.173.21:17:10.05#ibcon#about to read 5, iclass 13, count 2 2006.173.21:17:10.05#ibcon#read 5, iclass 13, count 2 2006.173.21:17:10.05#ibcon#about to read 6, iclass 13, count 2 2006.173.21:17:10.05#ibcon#read 6, iclass 13, count 2 2006.173.21:17:10.05#ibcon#end of sib2, iclass 13, count 2 2006.173.21:17:10.05#ibcon#*after write, iclass 13, count 2 2006.173.21:17:10.05#ibcon#*before return 0, iclass 13, count 2 2006.173.21:17:10.05#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.21:17:10.05#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.173.21:17:10.05#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.173.21:17:10.05#ibcon#ireg 7 cls_cnt 0 2006.173.21:17:10.05#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.21:17:10.17#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.21:17:10.17#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.21:17:10.17#ibcon#enter wrdev, iclass 13, count 0 2006.173.21:17:10.17#ibcon#first serial, iclass 13, count 0 2006.173.21:17:10.17#ibcon#enter sib2, iclass 13, count 0 2006.173.21:17:10.17#ibcon#flushed, iclass 13, count 0 2006.173.21:17:10.17#ibcon#about to write, iclass 13, count 0 2006.173.21:17:10.17#ibcon#wrote, iclass 13, count 0 2006.173.21:17:10.17#ibcon#about to read 3, iclass 13, count 0 2006.173.21:17:10.19#ibcon#read 3, iclass 13, count 0 2006.173.21:17:10.19#ibcon#about to read 4, iclass 13, count 0 2006.173.21:17:10.19#ibcon#read 4, iclass 13, count 0 2006.173.21:17:10.19#ibcon#about to read 5, iclass 13, count 0 2006.173.21:17:10.19#ibcon#read 5, iclass 13, count 0 2006.173.21:17:10.19#ibcon#about to read 6, iclass 13, count 0 2006.173.21:17:10.19#ibcon#read 6, iclass 13, count 0 2006.173.21:17:10.19#ibcon#end of sib2, iclass 13, count 0 2006.173.21:17:10.19#ibcon#*mode == 0, iclass 13, count 0 2006.173.21:17:10.19#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.21:17:10.19#ibcon#[27=USB\r\n] 2006.173.21:17:10.19#ibcon#*before write, iclass 13, count 0 2006.173.21:17:10.19#ibcon#enter sib2, iclass 13, count 0 2006.173.21:17:10.19#ibcon#flushed, iclass 13, count 0 2006.173.21:17:10.19#ibcon#about to write, iclass 13, count 0 2006.173.21:17:10.19#ibcon#wrote, iclass 13, count 0 2006.173.21:17:10.19#ibcon#about to read 3, iclass 13, count 0 2006.173.21:17:10.22#ibcon#read 3, iclass 13, count 0 2006.173.21:17:10.22#ibcon#about to read 4, iclass 13, count 0 2006.173.21:17:10.22#ibcon#read 4, iclass 13, count 0 2006.173.21:17:10.22#ibcon#about to read 5, iclass 13, count 0 2006.173.21:17:10.22#ibcon#read 5, iclass 13, count 0 2006.173.21:17:10.22#ibcon#about to read 6, iclass 13, count 0 2006.173.21:17:10.22#ibcon#read 6, iclass 13, count 0 2006.173.21:17:10.22#ibcon#end of sib2, iclass 13, count 0 2006.173.21:17:10.22#ibcon#*after write, iclass 13, count 0 2006.173.21:17:10.22#ibcon#*before return 0, iclass 13, count 0 2006.173.21:17:10.22#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.21:17:10.22#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.173.21:17:10.22#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.21:17:10.22#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.21:17:10.22$vck44/vblo=5,709.99 2006.173.21:17:10.22#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.21:17:10.22#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.21:17:10.22#ibcon#ireg 17 cls_cnt 0 2006.173.21:17:10.22#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.21:17:10.22#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.21:17:10.22#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.21:17:10.22#ibcon#enter wrdev, iclass 15, count 0 2006.173.21:17:10.22#ibcon#first serial, iclass 15, count 0 2006.173.21:17:10.22#ibcon#enter sib2, iclass 15, count 0 2006.173.21:17:10.22#ibcon#flushed, iclass 15, count 0 2006.173.21:17:10.22#ibcon#about to write, iclass 15, count 0 2006.173.21:17:10.22#ibcon#wrote, iclass 15, count 0 2006.173.21:17:10.22#ibcon#about to read 3, iclass 15, count 0 2006.173.21:17:10.24#ibcon#read 3, iclass 15, count 0 2006.173.21:17:10.24#ibcon#about to read 4, iclass 15, count 0 2006.173.21:17:10.24#ibcon#read 4, iclass 15, count 0 2006.173.21:17:10.24#ibcon#about to read 5, iclass 15, count 0 2006.173.21:17:10.24#ibcon#read 5, iclass 15, count 0 2006.173.21:17:10.24#ibcon#about to read 6, iclass 15, count 0 2006.173.21:17:10.24#ibcon#read 6, iclass 15, count 0 2006.173.21:17:10.24#ibcon#end of sib2, iclass 15, count 0 2006.173.21:17:10.24#ibcon#*mode == 0, iclass 15, count 0 2006.173.21:17:10.24#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.21:17:10.24#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.21:17:10.24#ibcon#*before write, iclass 15, count 0 2006.173.21:17:10.24#ibcon#enter sib2, iclass 15, count 0 2006.173.21:17:10.24#ibcon#flushed, iclass 15, count 0 2006.173.21:17:10.24#ibcon#about to write, iclass 15, count 0 2006.173.21:17:10.24#ibcon#wrote, iclass 15, count 0 2006.173.21:17:10.24#ibcon#about to read 3, iclass 15, count 0 2006.173.21:17:10.28#ibcon#read 3, iclass 15, count 0 2006.173.21:17:10.28#ibcon#about to read 4, iclass 15, count 0 2006.173.21:17:10.28#ibcon#read 4, iclass 15, count 0 2006.173.21:17:10.28#ibcon#about to read 5, iclass 15, count 0 2006.173.21:17:10.28#ibcon#read 5, iclass 15, count 0 2006.173.21:17:10.28#ibcon#about to read 6, iclass 15, count 0 2006.173.21:17:10.28#ibcon#read 6, iclass 15, count 0 2006.173.21:17:10.28#ibcon#end of sib2, iclass 15, count 0 2006.173.21:17:10.28#ibcon#*after write, iclass 15, count 0 2006.173.21:17:10.28#ibcon#*before return 0, iclass 15, count 0 2006.173.21:17:10.28#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.21:17:10.28#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.21:17:10.28#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.21:17:10.28#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.21:17:10.28$vck44/vb=5,4 2006.173.21:17:10.28#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.21:17:10.28#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.21:17:10.28#ibcon#ireg 11 cls_cnt 2 2006.173.21:17:10.28#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.21:17:10.34#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.21:17:10.34#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.21:17:10.34#ibcon#enter wrdev, iclass 17, count 2 2006.173.21:17:10.34#ibcon#first serial, iclass 17, count 2 2006.173.21:17:10.34#ibcon#enter sib2, iclass 17, count 2 2006.173.21:17:10.34#ibcon#flushed, iclass 17, count 2 2006.173.21:17:10.34#ibcon#about to write, iclass 17, count 2 2006.173.21:17:10.34#ibcon#wrote, iclass 17, count 2 2006.173.21:17:10.34#ibcon#about to read 3, iclass 17, count 2 2006.173.21:17:10.36#ibcon#read 3, iclass 17, count 2 2006.173.21:17:10.36#ibcon#about to read 4, iclass 17, count 2 2006.173.21:17:10.36#ibcon#read 4, iclass 17, count 2 2006.173.21:17:10.36#ibcon#about to read 5, iclass 17, count 2 2006.173.21:17:10.36#ibcon#read 5, iclass 17, count 2 2006.173.21:17:10.36#ibcon#about to read 6, iclass 17, count 2 2006.173.21:17:10.36#ibcon#read 6, iclass 17, count 2 2006.173.21:17:10.36#ibcon#end of sib2, iclass 17, count 2 2006.173.21:17:10.36#ibcon#*mode == 0, iclass 17, count 2 2006.173.21:17:10.36#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.21:17:10.36#ibcon#[27=AT05-04\r\n] 2006.173.21:17:10.36#ibcon#*before write, iclass 17, count 2 2006.173.21:17:10.36#ibcon#enter sib2, iclass 17, count 2 2006.173.21:17:10.36#ibcon#flushed, iclass 17, count 2 2006.173.21:17:10.36#ibcon#about to write, iclass 17, count 2 2006.173.21:17:10.36#ibcon#wrote, iclass 17, count 2 2006.173.21:17:10.36#ibcon#about to read 3, iclass 17, count 2 2006.173.21:17:10.39#ibcon#read 3, iclass 17, count 2 2006.173.21:17:10.39#ibcon#about to read 4, iclass 17, count 2 2006.173.21:17:10.39#ibcon#read 4, iclass 17, count 2 2006.173.21:17:10.39#ibcon#about to read 5, iclass 17, count 2 2006.173.21:17:10.39#ibcon#read 5, iclass 17, count 2 2006.173.21:17:10.39#ibcon#about to read 6, iclass 17, count 2 2006.173.21:17:10.39#ibcon#read 6, iclass 17, count 2 2006.173.21:17:10.39#ibcon#end of sib2, iclass 17, count 2 2006.173.21:17:10.39#ibcon#*after write, iclass 17, count 2 2006.173.21:17:10.39#ibcon#*before return 0, iclass 17, count 2 2006.173.21:17:10.39#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.21:17:10.39#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.21:17:10.39#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.21:17:10.39#ibcon#ireg 7 cls_cnt 0 2006.173.21:17:10.39#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.21:17:10.51#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.21:17:10.51#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.21:17:10.51#ibcon#enter wrdev, iclass 17, count 0 2006.173.21:17:10.51#ibcon#first serial, iclass 17, count 0 2006.173.21:17:10.51#ibcon#enter sib2, iclass 17, count 0 2006.173.21:17:10.51#ibcon#flushed, iclass 17, count 0 2006.173.21:17:10.51#ibcon#about to write, iclass 17, count 0 2006.173.21:17:10.51#ibcon#wrote, iclass 17, count 0 2006.173.21:17:10.51#ibcon#about to read 3, iclass 17, count 0 2006.173.21:17:10.53#ibcon#read 3, iclass 17, count 0 2006.173.21:17:10.53#ibcon#about to read 4, iclass 17, count 0 2006.173.21:17:10.53#ibcon#read 4, iclass 17, count 0 2006.173.21:17:10.53#ibcon#about to read 5, iclass 17, count 0 2006.173.21:17:10.53#ibcon#read 5, iclass 17, count 0 2006.173.21:17:10.53#ibcon#about to read 6, iclass 17, count 0 2006.173.21:17:10.53#ibcon#read 6, iclass 17, count 0 2006.173.21:17:10.53#ibcon#end of sib2, iclass 17, count 0 2006.173.21:17:10.53#ibcon#*mode == 0, iclass 17, count 0 2006.173.21:17:10.53#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.21:17:10.53#ibcon#[27=USB\r\n] 2006.173.21:17:10.53#ibcon#*before write, iclass 17, count 0 2006.173.21:17:10.53#ibcon#enter sib2, iclass 17, count 0 2006.173.21:17:10.53#ibcon#flushed, iclass 17, count 0 2006.173.21:17:10.53#ibcon#about to write, iclass 17, count 0 2006.173.21:17:10.53#ibcon#wrote, iclass 17, count 0 2006.173.21:17:10.53#ibcon#about to read 3, iclass 17, count 0 2006.173.21:17:10.56#ibcon#read 3, iclass 17, count 0 2006.173.21:17:10.56#ibcon#about to read 4, iclass 17, count 0 2006.173.21:17:10.56#ibcon#read 4, iclass 17, count 0 2006.173.21:17:10.56#ibcon#about to read 5, iclass 17, count 0 2006.173.21:17:10.56#ibcon#read 5, iclass 17, count 0 2006.173.21:17:10.56#ibcon#about to read 6, iclass 17, count 0 2006.173.21:17:10.56#ibcon#read 6, iclass 17, count 0 2006.173.21:17:10.56#ibcon#end of sib2, iclass 17, count 0 2006.173.21:17:10.56#ibcon#*after write, iclass 17, count 0 2006.173.21:17:10.56#ibcon#*before return 0, iclass 17, count 0 2006.173.21:17:10.56#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.21:17:10.56#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.21:17:10.56#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.21:17:10.56#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.21:17:10.56$vck44/vblo=6,719.99 2006.173.21:17:10.56#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.21:17:10.56#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.21:17:10.56#ibcon#ireg 17 cls_cnt 0 2006.173.21:17:10.56#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.21:17:10.56#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.21:17:10.56#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.21:17:10.56#ibcon#enter wrdev, iclass 19, count 0 2006.173.21:17:10.56#ibcon#first serial, iclass 19, count 0 2006.173.21:17:10.56#ibcon#enter sib2, iclass 19, count 0 2006.173.21:17:10.56#ibcon#flushed, iclass 19, count 0 2006.173.21:17:10.56#ibcon#about to write, iclass 19, count 0 2006.173.21:17:10.56#ibcon#wrote, iclass 19, count 0 2006.173.21:17:10.56#ibcon#about to read 3, iclass 19, count 0 2006.173.21:17:10.58#ibcon#read 3, iclass 19, count 0 2006.173.21:17:10.58#ibcon#about to read 4, iclass 19, count 0 2006.173.21:17:10.58#ibcon#read 4, iclass 19, count 0 2006.173.21:17:10.58#ibcon#about to read 5, iclass 19, count 0 2006.173.21:17:10.58#ibcon#read 5, iclass 19, count 0 2006.173.21:17:10.58#ibcon#about to read 6, iclass 19, count 0 2006.173.21:17:10.58#ibcon#read 6, iclass 19, count 0 2006.173.21:17:10.58#ibcon#end of sib2, iclass 19, count 0 2006.173.21:17:10.58#ibcon#*mode == 0, iclass 19, count 0 2006.173.21:17:10.58#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.21:17:10.58#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.21:17:10.58#ibcon#*before write, iclass 19, count 0 2006.173.21:17:10.58#ibcon#enter sib2, iclass 19, count 0 2006.173.21:17:10.58#ibcon#flushed, iclass 19, count 0 2006.173.21:17:10.58#ibcon#about to write, iclass 19, count 0 2006.173.21:17:10.58#ibcon#wrote, iclass 19, count 0 2006.173.21:17:10.58#ibcon#about to read 3, iclass 19, count 0 2006.173.21:17:10.62#ibcon#read 3, iclass 19, count 0 2006.173.21:17:10.62#ibcon#about to read 4, iclass 19, count 0 2006.173.21:17:10.62#ibcon#read 4, iclass 19, count 0 2006.173.21:17:10.62#ibcon#about to read 5, iclass 19, count 0 2006.173.21:17:10.62#ibcon#read 5, iclass 19, count 0 2006.173.21:17:10.62#ibcon#about to read 6, iclass 19, count 0 2006.173.21:17:10.62#ibcon#read 6, iclass 19, count 0 2006.173.21:17:10.62#ibcon#end of sib2, iclass 19, count 0 2006.173.21:17:10.62#ibcon#*after write, iclass 19, count 0 2006.173.21:17:10.62#ibcon#*before return 0, iclass 19, count 0 2006.173.21:17:10.62#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.21:17:10.62#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.21:17:10.62#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.21:17:10.62#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.21:17:10.62$vck44/vb=6,4 2006.173.21:17:10.62#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.21:17:10.62#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.21:17:10.62#ibcon#ireg 11 cls_cnt 2 2006.173.21:17:10.62#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.21:17:10.68#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.21:17:10.68#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.21:17:10.68#ibcon#enter wrdev, iclass 21, count 2 2006.173.21:17:10.68#ibcon#first serial, iclass 21, count 2 2006.173.21:17:10.68#ibcon#enter sib2, iclass 21, count 2 2006.173.21:17:10.68#ibcon#flushed, iclass 21, count 2 2006.173.21:17:10.68#ibcon#about to write, iclass 21, count 2 2006.173.21:17:10.68#ibcon#wrote, iclass 21, count 2 2006.173.21:17:10.68#ibcon#about to read 3, iclass 21, count 2 2006.173.21:17:10.70#ibcon#read 3, iclass 21, count 2 2006.173.21:17:10.70#ibcon#about to read 4, iclass 21, count 2 2006.173.21:17:10.70#ibcon#read 4, iclass 21, count 2 2006.173.21:17:10.70#ibcon#about to read 5, iclass 21, count 2 2006.173.21:17:10.70#ibcon#read 5, iclass 21, count 2 2006.173.21:17:10.70#ibcon#about to read 6, iclass 21, count 2 2006.173.21:17:10.70#ibcon#read 6, iclass 21, count 2 2006.173.21:17:10.70#ibcon#end of sib2, iclass 21, count 2 2006.173.21:17:10.70#ibcon#*mode == 0, iclass 21, count 2 2006.173.21:17:10.70#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.21:17:10.70#ibcon#[27=AT06-04\r\n] 2006.173.21:17:10.70#ibcon#*before write, iclass 21, count 2 2006.173.21:17:10.70#ibcon#enter sib2, iclass 21, count 2 2006.173.21:17:10.70#ibcon#flushed, iclass 21, count 2 2006.173.21:17:10.70#ibcon#about to write, iclass 21, count 2 2006.173.21:17:10.70#ibcon#wrote, iclass 21, count 2 2006.173.21:17:10.70#ibcon#about to read 3, iclass 21, count 2 2006.173.21:17:10.73#ibcon#read 3, iclass 21, count 2 2006.173.21:17:10.73#ibcon#about to read 4, iclass 21, count 2 2006.173.21:17:10.73#ibcon#read 4, iclass 21, count 2 2006.173.21:17:10.73#ibcon#about to read 5, iclass 21, count 2 2006.173.21:17:10.73#ibcon#read 5, iclass 21, count 2 2006.173.21:17:10.73#ibcon#about to read 6, iclass 21, count 2 2006.173.21:17:10.73#ibcon#read 6, iclass 21, count 2 2006.173.21:17:10.73#ibcon#end of sib2, iclass 21, count 2 2006.173.21:17:10.73#ibcon#*after write, iclass 21, count 2 2006.173.21:17:10.73#ibcon#*before return 0, iclass 21, count 2 2006.173.21:17:10.73#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.21:17:10.73#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.21:17:10.73#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.21:17:10.73#ibcon#ireg 7 cls_cnt 0 2006.173.21:17:10.73#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.21:17:10.85#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.21:17:10.85#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.21:17:10.85#ibcon#enter wrdev, iclass 21, count 0 2006.173.21:17:10.85#ibcon#first serial, iclass 21, count 0 2006.173.21:17:10.85#ibcon#enter sib2, iclass 21, count 0 2006.173.21:17:10.85#ibcon#flushed, iclass 21, count 0 2006.173.21:17:10.85#ibcon#about to write, iclass 21, count 0 2006.173.21:17:10.85#ibcon#wrote, iclass 21, count 0 2006.173.21:17:10.85#ibcon#about to read 3, iclass 21, count 0 2006.173.21:17:10.87#ibcon#read 3, iclass 21, count 0 2006.173.21:17:10.87#ibcon#about to read 4, iclass 21, count 0 2006.173.21:17:10.87#ibcon#read 4, iclass 21, count 0 2006.173.21:17:10.87#ibcon#about to read 5, iclass 21, count 0 2006.173.21:17:10.87#ibcon#read 5, iclass 21, count 0 2006.173.21:17:10.87#ibcon#about to read 6, iclass 21, count 0 2006.173.21:17:10.87#ibcon#read 6, iclass 21, count 0 2006.173.21:17:10.87#ibcon#end of sib2, iclass 21, count 0 2006.173.21:17:10.87#ibcon#*mode == 0, iclass 21, count 0 2006.173.21:17:10.87#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.21:17:10.87#ibcon#[27=USB\r\n] 2006.173.21:17:10.87#ibcon#*before write, iclass 21, count 0 2006.173.21:17:10.87#ibcon#enter sib2, iclass 21, count 0 2006.173.21:17:10.87#ibcon#flushed, iclass 21, count 0 2006.173.21:17:10.87#ibcon#about to write, iclass 21, count 0 2006.173.21:17:10.87#ibcon#wrote, iclass 21, count 0 2006.173.21:17:10.87#ibcon#about to read 3, iclass 21, count 0 2006.173.21:17:10.90#ibcon#read 3, iclass 21, count 0 2006.173.21:17:10.90#ibcon#about to read 4, iclass 21, count 0 2006.173.21:17:10.90#ibcon#read 4, iclass 21, count 0 2006.173.21:17:10.90#ibcon#about to read 5, iclass 21, count 0 2006.173.21:17:10.90#ibcon#read 5, iclass 21, count 0 2006.173.21:17:10.90#ibcon#about to read 6, iclass 21, count 0 2006.173.21:17:10.90#ibcon#read 6, iclass 21, count 0 2006.173.21:17:10.90#ibcon#end of sib2, iclass 21, count 0 2006.173.21:17:10.90#ibcon#*after write, iclass 21, count 0 2006.173.21:17:10.90#ibcon#*before return 0, iclass 21, count 0 2006.173.21:17:10.90#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.21:17:10.90#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.21:17:10.90#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.21:17:10.90#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.21:17:10.90$vck44/vblo=7,734.99 2006.173.21:17:10.90#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.21:17:10.90#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.21:17:10.90#ibcon#ireg 17 cls_cnt 0 2006.173.21:17:10.90#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.21:17:10.90#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.21:17:10.90#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.21:17:10.90#ibcon#enter wrdev, iclass 23, count 0 2006.173.21:17:10.90#ibcon#first serial, iclass 23, count 0 2006.173.21:17:10.90#ibcon#enter sib2, iclass 23, count 0 2006.173.21:17:10.90#ibcon#flushed, iclass 23, count 0 2006.173.21:17:10.90#ibcon#about to write, iclass 23, count 0 2006.173.21:17:10.90#ibcon#wrote, iclass 23, count 0 2006.173.21:17:10.90#ibcon#about to read 3, iclass 23, count 0 2006.173.21:17:10.92#ibcon#read 3, iclass 23, count 0 2006.173.21:17:10.92#ibcon#about to read 4, iclass 23, count 0 2006.173.21:17:10.92#ibcon#read 4, iclass 23, count 0 2006.173.21:17:10.92#ibcon#about to read 5, iclass 23, count 0 2006.173.21:17:10.92#ibcon#read 5, iclass 23, count 0 2006.173.21:17:10.92#ibcon#about to read 6, iclass 23, count 0 2006.173.21:17:10.92#ibcon#read 6, iclass 23, count 0 2006.173.21:17:10.92#ibcon#end of sib2, iclass 23, count 0 2006.173.21:17:10.92#ibcon#*mode == 0, iclass 23, count 0 2006.173.21:17:10.92#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.21:17:10.92#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.21:17:10.92#ibcon#*before write, iclass 23, count 0 2006.173.21:17:10.92#ibcon#enter sib2, iclass 23, count 0 2006.173.21:17:10.92#ibcon#flushed, iclass 23, count 0 2006.173.21:17:10.92#ibcon#about to write, iclass 23, count 0 2006.173.21:17:10.92#ibcon#wrote, iclass 23, count 0 2006.173.21:17:10.92#ibcon#about to read 3, iclass 23, count 0 2006.173.21:17:10.96#ibcon#read 3, iclass 23, count 0 2006.173.21:17:10.96#ibcon#about to read 4, iclass 23, count 0 2006.173.21:17:10.96#ibcon#read 4, iclass 23, count 0 2006.173.21:17:10.96#ibcon#about to read 5, iclass 23, count 0 2006.173.21:17:10.96#ibcon#read 5, iclass 23, count 0 2006.173.21:17:10.96#ibcon#about to read 6, iclass 23, count 0 2006.173.21:17:10.96#ibcon#read 6, iclass 23, count 0 2006.173.21:17:10.96#ibcon#end of sib2, iclass 23, count 0 2006.173.21:17:10.96#ibcon#*after write, iclass 23, count 0 2006.173.21:17:10.96#ibcon#*before return 0, iclass 23, count 0 2006.173.21:17:10.96#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.21:17:10.96#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.21:17:10.96#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.21:17:10.96#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.21:17:10.96$vck44/vb=7,4 2006.173.21:17:10.96#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.21:17:10.96#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.21:17:10.96#ibcon#ireg 11 cls_cnt 2 2006.173.21:17:10.96#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.21:17:11.02#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.21:17:11.02#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.21:17:11.02#ibcon#enter wrdev, iclass 25, count 2 2006.173.21:17:11.02#ibcon#first serial, iclass 25, count 2 2006.173.21:17:11.02#ibcon#enter sib2, iclass 25, count 2 2006.173.21:17:11.02#ibcon#flushed, iclass 25, count 2 2006.173.21:17:11.02#ibcon#about to write, iclass 25, count 2 2006.173.21:17:11.02#ibcon#wrote, iclass 25, count 2 2006.173.21:17:11.02#ibcon#about to read 3, iclass 25, count 2 2006.173.21:17:11.04#ibcon#read 3, iclass 25, count 2 2006.173.21:17:11.04#ibcon#about to read 4, iclass 25, count 2 2006.173.21:17:11.04#ibcon#read 4, iclass 25, count 2 2006.173.21:17:11.04#ibcon#about to read 5, iclass 25, count 2 2006.173.21:17:11.04#ibcon#read 5, iclass 25, count 2 2006.173.21:17:11.04#ibcon#about to read 6, iclass 25, count 2 2006.173.21:17:11.04#ibcon#read 6, iclass 25, count 2 2006.173.21:17:11.04#ibcon#end of sib2, iclass 25, count 2 2006.173.21:17:11.04#ibcon#*mode == 0, iclass 25, count 2 2006.173.21:17:11.04#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.21:17:11.04#ibcon#[27=AT07-04\r\n] 2006.173.21:17:11.04#ibcon#*before write, iclass 25, count 2 2006.173.21:17:11.04#ibcon#enter sib2, iclass 25, count 2 2006.173.21:17:11.04#ibcon#flushed, iclass 25, count 2 2006.173.21:17:11.04#ibcon#about to write, iclass 25, count 2 2006.173.21:17:11.04#ibcon#wrote, iclass 25, count 2 2006.173.21:17:11.04#ibcon#about to read 3, iclass 25, count 2 2006.173.21:17:11.07#ibcon#read 3, iclass 25, count 2 2006.173.21:17:11.07#ibcon#about to read 4, iclass 25, count 2 2006.173.21:17:11.07#ibcon#read 4, iclass 25, count 2 2006.173.21:17:11.07#ibcon#about to read 5, iclass 25, count 2 2006.173.21:17:11.07#ibcon#read 5, iclass 25, count 2 2006.173.21:17:11.07#ibcon#about to read 6, iclass 25, count 2 2006.173.21:17:11.07#ibcon#read 6, iclass 25, count 2 2006.173.21:17:11.07#ibcon#end of sib2, iclass 25, count 2 2006.173.21:17:11.07#ibcon#*after write, iclass 25, count 2 2006.173.21:17:11.07#ibcon#*before return 0, iclass 25, count 2 2006.173.21:17:11.07#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.21:17:11.07#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.21:17:11.07#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.21:17:11.07#ibcon#ireg 7 cls_cnt 0 2006.173.21:17:11.07#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.21:17:11.19#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.21:17:11.19#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.21:17:11.19#ibcon#enter wrdev, iclass 25, count 0 2006.173.21:17:11.19#ibcon#first serial, iclass 25, count 0 2006.173.21:17:11.19#ibcon#enter sib2, iclass 25, count 0 2006.173.21:17:11.19#ibcon#flushed, iclass 25, count 0 2006.173.21:17:11.19#ibcon#about to write, iclass 25, count 0 2006.173.21:17:11.19#ibcon#wrote, iclass 25, count 0 2006.173.21:17:11.19#ibcon#about to read 3, iclass 25, count 0 2006.173.21:17:11.21#ibcon#read 3, iclass 25, count 0 2006.173.21:17:11.21#ibcon#about to read 4, iclass 25, count 0 2006.173.21:17:11.21#ibcon#read 4, iclass 25, count 0 2006.173.21:17:11.21#ibcon#about to read 5, iclass 25, count 0 2006.173.21:17:11.21#ibcon#read 5, iclass 25, count 0 2006.173.21:17:11.21#ibcon#about to read 6, iclass 25, count 0 2006.173.21:17:11.21#ibcon#read 6, iclass 25, count 0 2006.173.21:17:11.21#ibcon#end of sib2, iclass 25, count 0 2006.173.21:17:11.21#ibcon#*mode == 0, iclass 25, count 0 2006.173.21:17:11.21#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.21:17:11.21#ibcon#[27=USB\r\n] 2006.173.21:17:11.21#ibcon#*before write, iclass 25, count 0 2006.173.21:17:11.21#ibcon#enter sib2, iclass 25, count 0 2006.173.21:17:11.21#ibcon#flushed, iclass 25, count 0 2006.173.21:17:11.21#ibcon#about to write, iclass 25, count 0 2006.173.21:17:11.21#ibcon#wrote, iclass 25, count 0 2006.173.21:17:11.21#ibcon#about to read 3, iclass 25, count 0 2006.173.21:17:11.24#ibcon#read 3, iclass 25, count 0 2006.173.21:17:11.24#ibcon#about to read 4, iclass 25, count 0 2006.173.21:17:11.24#ibcon#read 4, iclass 25, count 0 2006.173.21:17:11.24#ibcon#about to read 5, iclass 25, count 0 2006.173.21:17:11.24#ibcon#read 5, iclass 25, count 0 2006.173.21:17:11.24#ibcon#about to read 6, iclass 25, count 0 2006.173.21:17:11.24#ibcon#read 6, iclass 25, count 0 2006.173.21:17:11.24#ibcon#end of sib2, iclass 25, count 0 2006.173.21:17:11.24#ibcon#*after write, iclass 25, count 0 2006.173.21:17:11.24#ibcon#*before return 0, iclass 25, count 0 2006.173.21:17:11.24#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.21:17:11.24#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.21:17:11.24#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.21:17:11.24#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.21:17:11.24$vck44/vblo=8,744.99 2006.173.21:17:11.24#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.21:17:11.24#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.21:17:11.24#ibcon#ireg 17 cls_cnt 0 2006.173.21:17:11.24#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.21:17:11.24#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.21:17:11.24#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.21:17:11.24#ibcon#enter wrdev, iclass 27, count 0 2006.173.21:17:11.24#ibcon#first serial, iclass 27, count 0 2006.173.21:17:11.24#ibcon#enter sib2, iclass 27, count 0 2006.173.21:17:11.24#ibcon#flushed, iclass 27, count 0 2006.173.21:17:11.24#ibcon#about to write, iclass 27, count 0 2006.173.21:17:11.24#ibcon#wrote, iclass 27, count 0 2006.173.21:17:11.24#ibcon#about to read 3, iclass 27, count 0 2006.173.21:17:11.26#ibcon#read 3, iclass 27, count 0 2006.173.21:17:11.26#ibcon#about to read 4, iclass 27, count 0 2006.173.21:17:11.26#ibcon#read 4, iclass 27, count 0 2006.173.21:17:11.26#ibcon#about to read 5, iclass 27, count 0 2006.173.21:17:11.26#ibcon#read 5, iclass 27, count 0 2006.173.21:17:11.26#ibcon#about to read 6, iclass 27, count 0 2006.173.21:17:11.26#ibcon#read 6, iclass 27, count 0 2006.173.21:17:11.26#ibcon#end of sib2, iclass 27, count 0 2006.173.21:17:11.26#ibcon#*mode == 0, iclass 27, count 0 2006.173.21:17:11.26#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.21:17:11.26#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.21:17:11.26#ibcon#*before write, iclass 27, count 0 2006.173.21:17:11.26#ibcon#enter sib2, iclass 27, count 0 2006.173.21:17:11.26#ibcon#flushed, iclass 27, count 0 2006.173.21:17:11.26#ibcon#about to write, iclass 27, count 0 2006.173.21:17:11.26#ibcon#wrote, iclass 27, count 0 2006.173.21:17:11.26#ibcon#about to read 3, iclass 27, count 0 2006.173.21:17:11.30#ibcon#read 3, iclass 27, count 0 2006.173.21:17:11.30#ibcon#about to read 4, iclass 27, count 0 2006.173.21:17:11.30#ibcon#read 4, iclass 27, count 0 2006.173.21:17:11.30#ibcon#about to read 5, iclass 27, count 0 2006.173.21:17:11.30#ibcon#read 5, iclass 27, count 0 2006.173.21:17:11.30#ibcon#about to read 6, iclass 27, count 0 2006.173.21:17:11.30#ibcon#read 6, iclass 27, count 0 2006.173.21:17:11.30#ibcon#end of sib2, iclass 27, count 0 2006.173.21:17:11.30#ibcon#*after write, iclass 27, count 0 2006.173.21:17:11.30#ibcon#*before return 0, iclass 27, count 0 2006.173.21:17:11.30#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.21:17:11.30#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.21:17:11.30#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.21:17:11.30#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.21:17:11.30$vck44/vb=8,4 2006.173.21:17:11.30#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.21:17:11.30#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.21:17:11.30#ibcon#ireg 11 cls_cnt 2 2006.173.21:17:11.30#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.21:17:11.36#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.21:17:11.36#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.21:17:11.36#ibcon#enter wrdev, iclass 29, count 2 2006.173.21:17:11.36#ibcon#first serial, iclass 29, count 2 2006.173.21:17:11.36#ibcon#enter sib2, iclass 29, count 2 2006.173.21:17:11.36#ibcon#flushed, iclass 29, count 2 2006.173.21:17:11.36#ibcon#about to write, iclass 29, count 2 2006.173.21:17:11.36#ibcon#wrote, iclass 29, count 2 2006.173.21:17:11.36#ibcon#about to read 3, iclass 29, count 2 2006.173.21:17:11.38#ibcon#read 3, iclass 29, count 2 2006.173.21:17:11.38#ibcon#about to read 4, iclass 29, count 2 2006.173.21:17:11.38#ibcon#read 4, iclass 29, count 2 2006.173.21:17:11.38#ibcon#about to read 5, iclass 29, count 2 2006.173.21:17:11.38#ibcon#read 5, iclass 29, count 2 2006.173.21:17:11.38#ibcon#about to read 6, iclass 29, count 2 2006.173.21:17:11.38#ibcon#read 6, iclass 29, count 2 2006.173.21:17:11.38#ibcon#end of sib2, iclass 29, count 2 2006.173.21:17:11.38#ibcon#*mode == 0, iclass 29, count 2 2006.173.21:17:11.38#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.21:17:11.38#ibcon#[27=AT08-04\r\n] 2006.173.21:17:11.38#ibcon#*before write, iclass 29, count 2 2006.173.21:17:11.38#ibcon#enter sib2, iclass 29, count 2 2006.173.21:17:11.38#ibcon#flushed, iclass 29, count 2 2006.173.21:17:11.38#ibcon#about to write, iclass 29, count 2 2006.173.21:17:11.38#ibcon#wrote, iclass 29, count 2 2006.173.21:17:11.38#ibcon#about to read 3, iclass 29, count 2 2006.173.21:17:11.41#ibcon#read 3, iclass 29, count 2 2006.173.21:17:11.41#ibcon#about to read 4, iclass 29, count 2 2006.173.21:17:11.41#ibcon#read 4, iclass 29, count 2 2006.173.21:17:11.41#ibcon#about to read 5, iclass 29, count 2 2006.173.21:17:11.41#ibcon#read 5, iclass 29, count 2 2006.173.21:17:11.41#ibcon#about to read 6, iclass 29, count 2 2006.173.21:17:11.41#ibcon#read 6, iclass 29, count 2 2006.173.21:17:11.41#ibcon#end of sib2, iclass 29, count 2 2006.173.21:17:11.41#ibcon#*after write, iclass 29, count 2 2006.173.21:17:11.41#ibcon#*before return 0, iclass 29, count 2 2006.173.21:17:11.41#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.21:17:11.41#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.21:17:11.41#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.21:17:11.41#ibcon#ireg 7 cls_cnt 0 2006.173.21:17:11.41#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.21:17:11.53#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.21:17:11.53#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.21:17:11.53#ibcon#enter wrdev, iclass 29, count 0 2006.173.21:17:11.53#ibcon#first serial, iclass 29, count 0 2006.173.21:17:11.53#ibcon#enter sib2, iclass 29, count 0 2006.173.21:17:11.53#ibcon#flushed, iclass 29, count 0 2006.173.21:17:11.53#ibcon#about to write, iclass 29, count 0 2006.173.21:17:11.53#ibcon#wrote, iclass 29, count 0 2006.173.21:17:11.53#ibcon#about to read 3, iclass 29, count 0 2006.173.21:17:11.55#ibcon#read 3, iclass 29, count 0 2006.173.21:17:11.55#ibcon#about to read 4, iclass 29, count 0 2006.173.21:17:11.55#ibcon#read 4, iclass 29, count 0 2006.173.21:17:11.55#ibcon#about to read 5, iclass 29, count 0 2006.173.21:17:11.55#ibcon#read 5, iclass 29, count 0 2006.173.21:17:11.55#ibcon#about to read 6, iclass 29, count 0 2006.173.21:17:11.55#ibcon#read 6, iclass 29, count 0 2006.173.21:17:11.55#ibcon#end of sib2, iclass 29, count 0 2006.173.21:17:11.55#ibcon#*mode == 0, iclass 29, count 0 2006.173.21:17:11.55#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.21:17:11.55#ibcon#[27=USB\r\n] 2006.173.21:17:11.55#ibcon#*before write, iclass 29, count 0 2006.173.21:17:11.55#ibcon#enter sib2, iclass 29, count 0 2006.173.21:17:11.55#ibcon#flushed, iclass 29, count 0 2006.173.21:17:11.55#ibcon#about to write, iclass 29, count 0 2006.173.21:17:11.55#ibcon#wrote, iclass 29, count 0 2006.173.21:17:11.55#ibcon#about to read 3, iclass 29, count 0 2006.173.21:17:11.58#ibcon#read 3, iclass 29, count 0 2006.173.21:17:11.58#ibcon#about to read 4, iclass 29, count 0 2006.173.21:17:11.58#ibcon#read 4, iclass 29, count 0 2006.173.21:17:11.58#ibcon#about to read 5, iclass 29, count 0 2006.173.21:17:11.58#ibcon#read 5, iclass 29, count 0 2006.173.21:17:11.58#ibcon#about to read 6, iclass 29, count 0 2006.173.21:17:11.58#ibcon#read 6, iclass 29, count 0 2006.173.21:17:11.58#ibcon#end of sib2, iclass 29, count 0 2006.173.21:17:11.58#ibcon#*after write, iclass 29, count 0 2006.173.21:17:11.58#ibcon#*before return 0, iclass 29, count 0 2006.173.21:17:11.58#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.21:17:11.58#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.21:17:11.58#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.21:17:11.58#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.21:17:11.58$vck44/vabw=wide 2006.173.21:17:11.58#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.21:17:11.58#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.21:17:11.58#ibcon#ireg 8 cls_cnt 0 2006.173.21:17:11.58#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.21:17:11.58#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.21:17:11.58#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.21:17:11.58#ibcon#enter wrdev, iclass 31, count 0 2006.173.21:17:11.58#ibcon#first serial, iclass 31, count 0 2006.173.21:17:11.58#ibcon#enter sib2, iclass 31, count 0 2006.173.21:17:11.58#ibcon#flushed, iclass 31, count 0 2006.173.21:17:11.58#ibcon#about to write, iclass 31, count 0 2006.173.21:17:11.58#ibcon#wrote, iclass 31, count 0 2006.173.21:17:11.58#ibcon#about to read 3, iclass 31, count 0 2006.173.21:17:11.60#ibcon#read 3, iclass 31, count 0 2006.173.21:17:11.60#ibcon#about to read 4, iclass 31, count 0 2006.173.21:17:11.60#ibcon#read 4, iclass 31, count 0 2006.173.21:17:11.60#ibcon#about to read 5, iclass 31, count 0 2006.173.21:17:11.60#ibcon#read 5, iclass 31, count 0 2006.173.21:17:11.60#ibcon#about to read 6, iclass 31, count 0 2006.173.21:17:11.60#ibcon#read 6, iclass 31, count 0 2006.173.21:17:11.60#ibcon#end of sib2, iclass 31, count 0 2006.173.21:17:11.60#ibcon#*mode == 0, iclass 31, count 0 2006.173.21:17:11.60#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.21:17:11.60#ibcon#[25=BW32\r\n] 2006.173.21:17:11.60#ibcon#*before write, iclass 31, count 0 2006.173.21:17:11.60#ibcon#enter sib2, iclass 31, count 0 2006.173.21:17:11.60#ibcon#flushed, iclass 31, count 0 2006.173.21:17:11.60#ibcon#about to write, iclass 31, count 0 2006.173.21:17:11.60#ibcon#wrote, iclass 31, count 0 2006.173.21:17:11.60#ibcon#about to read 3, iclass 31, count 0 2006.173.21:17:11.63#ibcon#read 3, iclass 31, count 0 2006.173.21:17:11.63#ibcon#about to read 4, iclass 31, count 0 2006.173.21:17:11.63#ibcon#read 4, iclass 31, count 0 2006.173.21:17:11.63#ibcon#about to read 5, iclass 31, count 0 2006.173.21:17:11.63#ibcon#read 5, iclass 31, count 0 2006.173.21:17:11.63#ibcon#about to read 6, iclass 31, count 0 2006.173.21:17:11.63#ibcon#read 6, iclass 31, count 0 2006.173.21:17:11.63#ibcon#end of sib2, iclass 31, count 0 2006.173.21:17:11.63#ibcon#*after write, iclass 31, count 0 2006.173.21:17:11.63#ibcon#*before return 0, iclass 31, count 0 2006.173.21:17:11.63#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.21:17:11.63#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.21:17:11.63#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.21:17:11.63#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.21:17:11.63$vck44/vbbw=wide 2006.173.21:17:11.63#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.21:17:11.63#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.21:17:11.63#ibcon#ireg 8 cls_cnt 0 2006.173.21:17:11.63#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.21:17:11.70#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.21:17:11.70#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.21:17:11.70#ibcon#enter wrdev, iclass 33, count 0 2006.173.21:17:11.70#ibcon#first serial, iclass 33, count 0 2006.173.21:17:11.70#ibcon#enter sib2, iclass 33, count 0 2006.173.21:17:11.70#ibcon#flushed, iclass 33, count 0 2006.173.21:17:11.70#ibcon#about to write, iclass 33, count 0 2006.173.21:17:11.70#ibcon#wrote, iclass 33, count 0 2006.173.21:17:11.70#ibcon#about to read 3, iclass 33, count 0 2006.173.21:17:11.72#ibcon#read 3, iclass 33, count 0 2006.173.21:17:11.72#ibcon#about to read 4, iclass 33, count 0 2006.173.21:17:11.72#ibcon#read 4, iclass 33, count 0 2006.173.21:17:11.72#ibcon#about to read 5, iclass 33, count 0 2006.173.21:17:11.72#ibcon#read 5, iclass 33, count 0 2006.173.21:17:11.72#ibcon#about to read 6, iclass 33, count 0 2006.173.21:17:11.72#ibcon#read 6, iclass 33, count 0 2006.173.21:17:11.72#ibcon#end of sib2, iclass 33, count 0 2006.173.21:17:11.72#ibcon#*mode == 0, iclass 33, count 0 2006.173.21:17:11.72#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.21:17:11.72#ibcon#[27=BW32\r\n] 2006.173.21:17:11.72#ibcon#*before write, iclass 33, count 0 2006.173.21:17:11.72#ibcon#enter sib2, iclass 33, count 0 2006.173.21:17:11.72#ibcon#flushed, iclass 33, count 0 2006.173.21:17:11.72#ibcon#about to write, iclass 33, count 0 2006.173.21:17:11.72#ibcon#wrote, iclass 33, count 0 2006.173.21:17:11.72#ibcon#about to read 3, iclass 33, count 0 2006.173.21:17:11.75#ibcon#read 3, iclass 33, count 0 2006.173.21:17:11.75#ibcon#about to read 4, iclass 33, count 0 2006.173.21:17:11.75#ibcon#read 4, iclass 33, count 0 2006.173.21:17:11.75#ibcon#about to read 5, iclass 33, count 0 2006.173.21:17:11.75#ibcon#read 5, iclass 33, count 0 2006.173.21:17:11.75#ibcon#about to read 6, iclass 33, count 0 2006.173.21:17:11.75#ibcon#read 6, iclass 33, count 0 2006.173.21:17:11.75#ibcon#end of sib2, iclass 33, count 0 2006.173.21:17:11.75#ibcon#*after write, iclass 33, count 0 2006.173.21:17:11.75#ibcon#*before return 0, iclass 33, count 0 2006.173.21:17:11.75#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.21:17:11.75#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.21:17:11.75#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.21:17:11.75#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.21:17:11.75$setupk4/ifdk4 2006.173.21:17:11.75$ifdk4/lo= 2006.173.21:17:11.75$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.21:17:11.75$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.21:17:11.75$ifdk4/patch= 2006.173.21:17:11.75$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.21:17:11.75$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.21:17:11.75$setupk4/!*+20s 2006.173.21:17:15.76#abcon#<5=/12 0.6 1.6 21.091001003.2\r\n> 2006.173.21:17:15.78#abcon#{5=INTERFACE CLEAR} 2006.173.21:17:15.84#abcon#[5=S1D000X0/0*\r\n] 2006.173.21:17:21.14#trakl#Source acquired 2006.173.21:17:23.14#flagr#flagr/antenna,acquired 2006.173.21:17:25.93#abcon#<5=/12 0.6 1.6 21.091001003.2\r\n> 2006.173.21:17:25.95#abcon#{5=INTERFACE CLEAR} 2006.173.21:17:26.01#abcon#[5=S1D000X0/0*\r\n] 2006.173.21:17:26.27$setupk4/"tpicd 2006.173.21:17:26.27$setupk4/echo=off 2006.173.21:17:26.27$setupk4/xlog=off 2006.173.21:17:26.27:!2006.173.21:22:22 2006.173.21:22:22.00:preob 2006.173.21:22:22.14/onsource/TRACKING 2006.173.21:22:22.14:!2006.173.21:22:32 2006.173.21:22:32.00:"tape 2006.173.21:22:32.00:"st=record 2006.173.21:22:32.00:data_valid=on 2006.173.21:22:32.00:midob 2006.173.21:22:32.14/onsource/TRACKING 2006.173.21:22:32.14/wx/20.99,1003.0,100 2006.173.21:22:32.21/cable/+6.5173E-03 2006.173.21:22:33.30/va/01,07,usb,yes,35,37 2006.173.21:22:33.30/va/02,06,usb,yes,34,35 2006.173.21:22:33.30/va/03,05,usb,yes,44,46 2006.173.21:22:33.30/va/04,06,usb,yes,35,37 2006.173.21:22:33.30/va/05,04,usb,yes,28,28 2006.173.21:22:33.30/va/06,03,usb,yes,39,38 2006.173.21:22:33.30/va/07,04,usb,yes,31,32 2006.173.21:22:33.30/va/08,04,usb,yes,27,32 2006.173.21:22:33.53/valo/01,524.99,yes,locked 2006.173.21:22:33.53/valo/02,534.99,yes,locked 2006.173.21:22:33.53/valo/03,564.99,yes,locked 2006.173.21:22:33.53/valo/04,624.99,yes,locked 2006.173.21:22:33.53/valo/05,734.99,yes,locked 2006.173.21:22:33.53/valo/06,814.99,yes,locked 2006.173.21:22:33.53/valo/07,864.99,yes,locked 2006.173.21:22:33.53/valo/08,884.99,yes,locked 2006.173.21:22:34.62/vb/01,04,usb,yes,29,27 2006.173.21:22:34.62/vb/02,04,usb,yes,31,32 2006.173.21:22:34.62/vb/03,04,usb,yes,28,31 2006.173.21:22:34.62/vb/04,04,usb,yes,32,31 2006.173.21:22:34.62/vb/05,04,usb,yes,25,27 2006.173.21:22:34.62/vb/06,04,usb,yes,29,26 2006.173.21:22:34.62/vb/07,04,usb,yes,29,29 2006.173.21:22:34.62/vb/08,04,usb,yes,27,30 2006.173.21:22:34.86/vblo/01,629.99,yes,locked 2006.173.21:22:34.86/vblo/02,634.99,yes,locked 2006.173.21:22:34.86/vblo/03,649.99,yes,locked 2006.173.21:22:34.86/vblo/04,679.99,yes,locked 2006.173.21:22:34.86/vblo/05,709.99,yes,locked 2006.173.21:22:34.86/vblo/06,719.99,yes,locked 2006.173.21:22:34.86/vblo/07,734.99,yes,locked 2006.173.21:22:34.86/vblo/08,744.99,yes,locked 2006.173.21:22:35.01/vabw/8 2006.173.21:22:35.16/vbbw/8 2006.173.21:22:35.25/xfe/off,on,14.7 2006.173.21:22:35.64/ifatt/23,28,28,28 2006.173.21:22:36.07/fmout-gps/S +3.89E-07 2006.173.21:22:36.11:!2006.173.21:23:52 2006.173.21:23:52.00:data_valid=off 2006.173.21:23:52.00:"et 2006.173.21:23:52.00:!+3s 2006.173.21:23:55.01:"tape 2006.173.21:23:55.01:postob 2006.173.21:23:55.16/cable/+6.5171E-03 2006.173.21:23:55.16/wx/20.97,1003.0,100 2006.173.21:23:56.07/fmout-gps/S +3.88E-07 2006.173.21:23:56.07:scan_name=173-2128,jd0606,50 2006.173.21:23:56.07:source=0552+398,055530.81,394849.2,2000.0,cw 2006.173.21:23:57.14#flagr#flagr/antenna,new-source 2006.173.21:23:57.14:checkk5 2006.173.21:23:57.55/chk_autoobs//k5ts1/ autoobs is running! 2006.173.21:23:57.95/chk_autoobs//k5ts2/ autoobs is running! 2006.173.21:23:58.35/chk_autoobs//k5ts3/ autoobs is running! 2006.173.21:23:58.73/chk_autoobs//k5ts4/ autoobs is running! 2006.173.21:23:59.12/chk_obsdata//k5ts1/T1732122??a.dat file size is correct (nominal:320MB, actual:316MB). 2006.173.21:23:59.53/chk_obsdata//k5ts2/T1732122??b.dat file size is correct (nominal:320MB, actual:316MB). 2006.173.21:23:59.92/chk_obsdata//k5ts3/T1732122??c.dat file size is correct (nominal:320MB, actual:316MB). 2006.173.21:24:00.35/chk_obsdata//k5ts4/T1732122??d.dat file size is correct (nominal:320MB, actual:316MB). 2006.173.21:24:01.06/k5log//k5ts1_log_newline 2006.173.21:24:01.76/k5log//k5ts2_log_newline 2006.173.21:24:02.47/k5log//k5ts3_log_newline 2006.173.21:24:03.17/k5log//k5ts4_log_newline 2006.173.21:24:03.20/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.21:24:03.20:setupk4=1 2006.173.21:24:03.20$setupk4/echo=on 2006.173.21:24:03.20$setupk4/pcalon 2006.173.21:24:03.20$pcalon/"no phase cal control is implemented here 2006.173.21:24:03.20$setupk4/"tpicd=stop 2006.173.21:24:03.20$setupk4/"rec=synch_on 2006.173.21:24:03.20$setupk4/"rec_mode=128 2006.173.21:24:03.20$setupk4/!* 2006.173.21:24:03.20$setupk4/recpk4 2006.173.21:24:03.20$recpk4/recpatch= 2006.173.21:24:03.21$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.21:24:03.21$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.21:24:03.21$setupk4/vck44 2006.173.21:24:03.21$vck44/valo=1,524.99 2006.173.21:24:03.21#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.21:24:03.21#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.21:24:03.21#ibcon#ireg 17 cls_cnt 0 2006.173.21:24:03.21#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.21:24:03.21#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.21:24:03.21#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.21:24:03.21#ibcon#enter wrdev, iclass 22, count 0 2006.173.21:24:03.21#ibcon#first serial, iclass 22, count 0 2006.173.21:24:03.21#ibcon#enter sib2, iclass 22, count 0 2006.173.21:24:03.21#ibcon#flushed, iclass 22, count 0 2006.173.21:24:03.21#ibcon#about to write, iclass 22, count 0 2006.173.21:24:03.21#ibcon#wrote, iclass 22, count 0 2006.173.21:24:03.21#ibcon#about to read 3, iclass 22, count 0 2006.173.21:24:03.23#ibcon#read 3, iclass 22, count 0 2006.173.21:24:03.23#ibcon#about to read 4, iclass 22, count 0 2006.173.21:24:03.23#ibcon#read 4, iclass 22, count 0 2006.173.21:24:03.23#ibcon#about to read 5, iclass 22, count 0 2006.173.21:24:03.23#ibcon#read 5, iclass 22, count 0 2006.173.21:24:03.23#ibcon#about to read 6, iclass 22, count 0 2006.173.21:24:03.23#ibcon#read 6, iclass 22, count 0 2006.173.21:24:03.23#ibcon#end of sib2, iclass 22, count 0 2006.173.21:24:03.23#ibcon#*mode == 0, iclass 22, count 0 2006.173.21:24:03.23#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.21:24:03.23#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.21:24:03.23#ibcon#*before write, iclass 22, count 0 2006.173.21:24:03.23#ibcon#enter sib2, iclass 22, count 0 2006.173.21:24:03.23#ibcon#flushed, iclass 22, count 0 2006.173.21:24:03.23#ibcon#about to write, iclass 22, count 0 2006.173.21:24:03.23#ibcon#wrote, iclass 22, count 0 2006.173.21:24:03.23#ibcon#about to read 3, iclass 22, count 0 2006.173.21:24:03.28#ibcon#read 3, iclass 22, count 0 2006.173.21:24:03.28#ibcon#about to read 4, iclass 22, count 0 2006.173.21:24:03.28#ibcon#read 4, iclass 22, count 0 2006.173.21:24:03.28#ibcon#about to read 5, iclass 22, count 0 2006.173.21:24:03.28#ibcon#read 5, iclass 22, count 0 2006.173.21:24:03.28#ibcon#about to read 6, iclass 22, count 0 2006.173.21:24:03.28#ibcon#read 6, iclass 22, count 0 2006.173.21:24:03.28#ibcon#end of sib2, iclass 22, count 0 2006.173.21:24:03.28#ibcon#*after write, iclass 22, count 0 2006.173.21:24:03.28#ibcon#*before return 0, iclass 22, count 0 2006.173.21:24:03.28#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.21:24:03.28#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.21:24:03.28#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.21:24:03.28#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.21:24:03.28$vck44/va=1,7 2006.173.21:24:03.28#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.21:24:03.28#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.21:24:03.28#ibcon#ireg 11 cls_cnt 2 2006.173.21:24:03.28#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.21:24:03.28#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.21:24:03.28#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.21:24:03.28#ibcon#enter wrdev, iclass 24, count 2 2006.173.21:24:03.28#ibcon#first serial, iclass 24, count 2 2006.173.21:24:03.28#ibcon#enter sib2, iclass 24, count 2 2006.173.21:24:03.28#ibcon#flushed, iclass 24, count 2 2006.173.21:24:03.28#ibcon#about to write, iclass 24, count 2 2006.173.21:24:03.28#ibcon#wrote, iclass 24, count 2 2006.173.21:24:03.28#ibcon#about to read 3, iclass 24, count 2 2006.173.21:24:03.30#ibcon#read 3, iclass 24, count 2 2006.173.21:24:03.30#ibcon#about to read 4, iclass 24, count 2 2006.173.21:24:03.30#ibcon#read 4, iclass 24, count 2 2006.173.21:24:03.30#ibcon#about to read 5, iclass 24, count 2 2006.173.21:24:03.30#ibcon#read 5, iclass 24, count 2 2006.173.21:24:03.30#ibcon#about to read 6, iclass 24, count 2 2006.173.21:24:03.30#ibcon#read 6, iclass 24, count 2 2006.173.21:24:03.30#ibcon#end of sib2, iclass 24, count 2 2006.173.21:24:03.30#ibcon#*mode == 0, iclass 24, count 2 2006.173.21:24:03.30#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.21:24:03.30#ibcon#[25=AT01-07\r\n] 2006.173.21:24:03.30#ibcon#*before write, iclass 24, count 2 2006.173.21:24:03.30#ibcon#enter sib2, iclass 24, count 2 2006.173.21:24:03.30#ibcon#flushed, iclass 24, count 2 2006.173.21:24:03.30#ibcon#about to write, iclass 24, count 2 2006.173.21:24:03.30#ibcon#wrote, iclass 24, count 2 2006.173.21:24:03.30#ibcon#about to read 3, iclass 24, count 2 2006.173.21:24:03.33#ibcon#read 3, iclass 24, count 2 2006.173.21:24:03.33#ibcon#about to read 4, iclass 24, count 2 2006.173.21:24:03.33#ibcon#read 4, iclass 24, count 2 2006.173.21:24:03.33#ibcon#about to read 5, iclass 24, count 2 2006.173.21:24:03.33#ibcon#read 5, iclass 24, count 2 2006.173.21:24:03.33#ibcon#about to read 6, iclass 24, count 2 2006.173.21:24:03.33#ibcon#read 6, iclass 24, count 2 2006.173.21:24:03.33#ibcon#end of sib2, iclass 24, count 2 2006.173.21:24:03.33#ibcon#*after write, iclass 24, count 2 2006.173.21:24:03.33#ibcon#*before return 0, iclass 24, count 2 2006.173.21:24:03.33#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.21:24:03.33#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.21:24:03.33#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.21:24:03.33#ibcon#ireg 7 cls_cnt 0 2006.173.21:24:03.33#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.21:24:03.45#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.21:24:03.45#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.21:24:03.45#ibcon#enter wrdev, iclass 24, count 0 2006.173.21:24:03.45#ibcon#first serial, iclass 24, count 0 2006.173.21:24:03.45#ibcon#enter sib2, iclass 24, count 0 2006.173.21:24:03.45#ibcon#flushed, iclass 24, count 0 2006.173.21:24:03.45#ibcon#about to write, iclass 24, count 0 2006.173.21:24:03.45#ibcon#wrote, iclass 24, count 0 2006.173.21:24:03.45#ibcon#about to read 3, iclass 24, count 0 2006.173.21:24:03.47#ibcon#read 3, iclass 24, count 0 2006.173.21:24:03.47#ibcon#about to read 4, iclass 24, count 0 2006.173.21:24:03.47#ibcon#read 4, iclass 24, count 0 2006.173.21:24:03.47#ibcon#about to read 5, iclass 24, count 0 2006.173.21:24:03.47#ibcon#read 5, iclass 24, count 0 2006.173.21:24:03.47#ibcon#about to read 6, iclass 24, count 0 2006.173.21:24:03.47#ibcon#read 6, iclass 24, count 0 2006.173.21:24:03.47#ibcon#end of sib2, iclass 24, count 0 2006.173.21:24:03.47#ibcon#*mode == 0, iclass 24, count 0 2006.173.21:24:03.47#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.21:24:03.47#ibcon#[25=USB\r\n] 2006.173.21:24:03.47#ibcon#*before write, iclass 24, count 0 2006.173.21:24:03.47#ibcon#enter sib2, iclass 24, count 0 2006.173.21:24:03.47#ibcon#flushed, iclass 24, count 0 2006.173.21:24:03.47#ibcon#about to write, iclass 24, count 0 2006.173.21:24:03.47#ibcon#wrote, iclass 24, count 0 2006.173.21:24:03.47#ibcon#about to read 3, iclass 24, count 0 2006.173.21:24:03.50#ibcon#read 3, iclass 24, count 0 2006.173.21:24:03.50#ibcon#about to read 4, iclass 24, count 0 2006.173.21:24:03.50#ibcon#read 4, iclass 24, count 0 2006.173.21:24:03.50#ibcon#about to read 5, iclass 24, count 0 2006.173.21:24:03.50#ibcon#read 5, iclass 24, count 0 2006.173.21:24:03.50#ibcon#about to read 6, iclass 24, count 0 2006.173.21:24:03.50#ibcon#read 6, iclass 24, count 0 2006.173.21:24:03.50#ibcon#end of sib2, iclass 24, count 0 2006.173.21:24:03.50#ibcon#*after write, iclass 24, count 0 2006.173.21:24:03.50#ibcon#*before return 0, iclass 24, count 0 2006.173.21:24:03.50#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.21:24:03.50#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.21:24:03.50#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.21:24:03.50#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.21:24:03.50$vck44/valo=2,534.99 2006.173.21:24:03.50#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.21:24:03.50#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.21:24:03.50#ibcon#ireg 17 cls_cnt 0 2006.173.21:24:03.50#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.21:24:03.50#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.21:24:03.50#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.21:24:03.50#ibcon#enter wrdev, iclass 26, count 0 2006.173.21:24:03.50#ibcon#first serial, iclass 26, count 0 2006.173.21:24:03.50#ibcon#enter sib2, iclass 26, count 0 2006.173.21:24:03.50#ibcon#flushed, iclass 26, count 0 2006.173.21:24:03.50#ibcon#about to write, iclass 26, count 0 2006.173.21:24:03.50#ibcon#wrote, iclass 26, count 0 2006.173.21:24:03.50#ibcon#about to read 3, iclass 26, count 0 2006.173.21:24:03.52#ibcon#read 3, iclass 26, count 0 2006.173.21:24:03.52#ibcon#about to read 4, iclass 26, count 0 2006.173.21:24:03.52#ibcon#read 4, iclass 26, count 0 2006.173.21:24:03.52#ibcon#about to read 5, iclass 26, count 0 2006.173.21:24:03.52#ibcon#read 5, iclass 26, count 0 2006.173.21:24:03.52#ibcon#about to read 6, iclass 26, count 0 2006.173.21:24:03.52#ibcon#read 6, iclass 26, count 0 2006.173.21:24:03.52#ibcon#end of sib2, iclass 26, count 0 2006.173.21:24:03.52#ibcon#*mode == 0, iclass 26, count 0 2006.173.21:24:03.52#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.21:24:03.52#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.21:24:03.52#ibcon#*before write, iclass 26, count 0 2006.173.21:24:03.52#ibcon#enter sib2, iclass 26, count 0 2006.173.21:24:03.52#ibcon#flushed, iclass 26, count 0 2006.173.21:24:03.52#ibcon#about to write, iclass 26, count 0 2006.173.21:24:03.52#ibcon#wrote, iclass 26, count 0 2006.173.21:24:03.52#ibcon#about to read 3, iclass 26, count 0 2006.173.21:24:03.56#ibcon#read 3, iclass 26, count 0 2006.173.21:24:03.56#ibcon#about to read 4, iclass 26, count 0 2006.173.21:24:03.56#ibcon#read 4, iclass 26, count 0 2006.173.21:24:03.56#ibcon#about to read 5, iclass 26, count 0 2006.173.21:24:03.56#ibcon#read 5, iclass 26, count 0 2006.173.21:24:03.56#ibcon#about to read 6, iclass 26, count 0 2006.173.21:24:03.56#ibcon#read 6, iclass 26, count 0 2006.173.21:24:03.56#ibcon#end of sib2, iclass 26, count 0 2006.173.21:24:03.56#ibcon#*after write, iclass 26, count 0 2006.173.21:24:03.56#ibcon#*before return 0, iclass 26, count 0 2006.173.21:24:03.56#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.21:24:03.56#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.21:24:03.56#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.21:24:03.56#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.21:24:03.56$vck44/va=2,6 2006.173.21:24:03.56#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.21:24:03.56#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.21:24:03.56#ibcon#ireg 11 cls_cnt 2 2006.173.21:24:03.56#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.21:24:03.62#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.21:24:03.62#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.21:24:03.62#ibcon#enter wrdev, iclass 28, count 2 2006.173.21:24:03.62#ibcon#first serial, iclass 28, count 2 2006.173.21:24:03.62#ibcon#enter sib2, iclass 28, count 2 2006.173.21:24:03.62#ibcon#flushed, iclass 28, count 2 2006.173.21:24:03.62#ibcon#about to write, iclass 28, count 2 2006.173.21:24:03.62#ibcon#wrote, iclass 28, count 2 2006.173.21:24:03.62#ibcon#about to read 3, iclass 28, count 2 2006.173.21:24:03.64#ibcon#read 3, iclass 28, count 2 2006.173.21:24:03.64#ibcon#about to read 4, iclass 28, count 2 2006.173.21:24:03.64#ibcon#read 4, iclass 28, count 2 2006.173.21:24:03.64#ibcon#about to read 5, iclass 28, count 2 2006.173.21:24:03.64#ibcon#read 5, iclass 28, count 2 2006.173.21:24:03.64#ibcon#about to read 6, iclass 28, count 2 2006.173.21:24:03.64#ibcon#read 6, iclass 28, count 2 2006.173.21:24:03.64#ibcon#end of sib2, iclass 28, count 2 2006.173.21:24:03.64#ibcon#*mode == 0, iclass 28, count 2 2006.173.21:24:03.64#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.21:24:03.64#ibcon#[25=AT02-06\r\n] 2006.173.21:24:03.64#ibcon#*before write, iclass 28, count 2 2006.173.21:24:03.64#ibcon#enter sib2, iclass 28, count 2 2006.173.21:24:03.64#ibcon#flushed, iclass 28, count 2 2006.173.21:24:03.64#ibcon#about to write, iclass 28, count 2 2006.173.21:24:03.64#ibcon#wrote, iclass 28, count 2 2006.173.21:24:03.64#ibcon#about to read 3, iclass 28, count 2 2006.173.21:24:03.67#ibcon#read 3, iclass 28, count 2 2006.173.21:24:03.67#ibcon#about to read 4, iclass 28, count 2 2006.173.21:24:03.67#ibcon#read 4, iclass 28, count 2 2006.173.21:24:03.67#ibcon#about to read 5, iclass 28, count 2 2006.173.21:24:03.67#ibcon#read 5, iclass 28, count 2 2006.173.21:24:03.67#ibcon#about to read 6, iclass 28, count 2 2006.173.21:24:03.67#ibcon#read 6, iclass 28, count 2 2006.173.21:24:03.67#ibcon#end of sib2, iclass 28, count 2 2006.173.21:24:03.67#ibcon#*after write, iclass 28, count 2 2006.173.21:24:03.67#ibcon#*before return 0, iclass 28, count 2 2006.173.21:24:03.67#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.21:24:03.67#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.21:24:03.67#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.21:24:03.67#ibcon#ireg 7 cls_cnt 0 2006.173.21:24:03.67#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.21:24:03.79#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.21:24:03.79#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.21:24:03.79#ibcon#enter wrdev, iclass 28, count 0 2006.173.21:24:03.79#ibcon#first serial, iclass 28, count 0 2006.173.21:24:03.79#ibcon#enter sib2, iclass 28, count 0 2006.173.21:24:03.79#ibcon#flushed, iclass 28, count 0 2006.173.21:24:03.79#ibcon#about to write, iclass 28, count 0 2006.173.21:24:03.79#ibcon#wrote, iclass 28, count 0 2006.173.21:24:03.79#ibcon#about to read 3, iclass 28, count 0 2006.173.21:24:03.81#ibcon#read 3, iclass 28, count 0 2006.173.21:24:03.81#ibcon#about to read 4, iclass 28, count 0 2006.173.21:24:03.81#ibcon#read 4, iclass 28, count 0 2006.173.21:24:03.81#ibcon#about to read 5, iclass 28, count 0 2006.173.21:24:03.81#ibcon#read 5, iclass 28, count 0 2006.173.21:24:03.81#ibcon#about to read 6, iclass 28, count 0 2006.173.21:24:03.81#ibcon#read 6, iclass 28, count 0 2006.173.21:24:03.81#ibcon#end of sib2, iclass 28, count 0 2006.173.21:24:03.81#ibcon#*mode == 0, iclass 28, count 0 2006.173.21:24:03.81#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.21:24:03.81#ibcon#[25=USB\r\n] 2006.173.21:24:03.81#ibcon#*before write, iclass 28, count 0 2006.173.21:24:03.81#ibcon#enter sib2, iclass 28, count 0 2006.173.21:24:03.81#ibcon#flushed, iclass 28, count 0 2006.173.21:24:03.81#ibcon#about to write, iclass 28, count 0 2006.173.21:24:03.81#ibcon#wrote, iclass 28, count 0 2006.173.21:24:03.81#ibcon#about to read 3, iclass 28, count 0 2006.173.21:24:03.84#ibcon#read 3, iclass 28, count 0 2006.173.21:24:03.84#ibcon#about to read 4, iclass 28, count 0 2006.173.21:24:03.84#ibcon#read 4, iclass 28, count 0 2006.173.21:24:03.84#ibcon#about to read 5, iclass 28, count 0 2006.173.21:24:03.84#ibcon#read 5, iclass 28, count 0 2006.173.21:24:03.84#ibcon#about to read 6, iclass 28, count 0 2006.173.21:24:03.84#ibcon#read 6, iclass 28, count 0 2006.173.21:24:03.84#ibcon#end of sib2, iclass 28, count 0 2006.173.21:24:03.84#ibcon#*after write, iclass 28, count 0 2006.173.21:24:03.84#ibcon#*before return 0, iclass 28, count 0 2006.173.21:24:03.84#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.21:24:03.84#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.21:24:03.84#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.21:24:03.84#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.21:24:03.84$vck44/valo=3,564.99 2006.173.21:24:03.84#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.21:24:03.84#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.21:24:03.84#ibcon#ireg 17 cls_cnt 0 2006.173.21:24:03.84#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.21:24:03.84#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.21:24:03.84#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.21:24:03.84#ibcon#enter wrdev, iclass 30, count 0 2006.173.21:24:03.84#ibcon#first serial, iclass 30, count 0 2006.173.21:24:03.84#ibcon#enter sib2, iclass 30, count 0 2006.173.21:24:03.84#ibcon#flushed, iclass 30, count 0 2006.173.21:24:03.84#ibcon#about to write, iclass 30, count 0 2006.173.21:24:03.84#ibcon#wrote, iclass 30, count 0 2006.173.21:24:03.84#ibcon#about to read 3, iclass 30, count 0 2006.173.21:24:03.86#ibcon#read 3, iclass 30, count 0 2006.173.21:24:03.86#ibcon#about to read 4, iclass 30, count 0 2006.173.21:24:03.86#ibcon#read 4, iclass 30, count 0 2006.173.21:24:03.86#ibcon#about to read 5, iclass 30, count 0 2006.173.21:24:03.86#ibcon#read 5, iclass 30, count 0 2006.173.21:24:03.86#ibcon#about to read 6, iclass 30, count 0 2006.173.21:24:03.86#ibcon#read 6, iclass 30, count 0 2006.173.21:24:03.86#ibcon#end of sib2, iclass 30, count 0 2006.173.21:24:03.86#ibcon#*mode == 0, iclass 30, count 0 2006.173.21:24:03.86#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.21:24:03.86#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.21:24:03.86#ibcon#*before write, iclass 30, count 0 2006.173.21:24:03.86#ibcon#enter sib2, iclass 30, count 0 2006.173.21:24:03.86#ibcon#flushed, iclass 30, count 0 2006.173.21:24:03.86#ibcon#about to write, iclass 30, count 0 2006.173.21:24:03.86#ibcon#wrote, iclass 30, count 0 2006.173.21:24:03.86#ibcon#about to read 3, iclass 30, count 0 2006.173.21:24:03.90#ibcon#read 3, iclass 30, count 0 2006.173.21:24:03.90#ibcon#about to read 4, iclass 30, count 0 2006.173.21:24:03.90#ibcon#read 4, iclass 30, count 0 2006.173.21:24:03.90#ibcon#about to read 5, iclass 30, count 0 2006.173.21:24:03.90#ibcon#read 5, iclass 30, count 0 2006.173.21:24:03.90#ibcon#about to read 6, iclass 30, count 0 2006.173.21:24:03.90#ibcon#read 6, iclass 30, count 0 2006.173.21:24:03.90#ibcon#end of sib2, iclass 30, count 0 2006.173.21:24:03.90#ibcon#*after write, iclass 30, count 0 2006.173.21:24:03.90#ibcon#*before return 0, iclass 30, count 0 2006.173.21:24:03.90#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.21:24:03.90#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.21:24:03.90#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.21:24:03.90#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.21:24:03.90$vck44/va=3,5 2006.173.21:24:03.90#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.173.21:24:03.90#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.173.21:24:03.90#ibcon#ireg 11 cls_cnt 2 2006.173.21:24:03.90#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.21:24:03.96#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.21:24:03.96#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.21:24:03.96#ibcon#enter wrdev, iclass 32, count 2 2006.173.21:24:03.96#ibcon#first serial, iclass 32, count 2 2006.173.21:24:03.96#ibcon#enter sib2, iclass 32, count 2 2006.173.21:24:03.96#ibcon#flushed, iclass 32, count 2 2006.173.21:24:03.96#ibcon#about to write, iclass 32, count 2 2006.173.21:24:03.96#ibcon#wrote, iclass 32, count 2 2006.173.21:24:03.96#ibcon#about to read 3, iclass 32, count 2 2006.173.21:24:03.98#ibcon#read 3, iclass 32, count 2 2006.173.21:24:03.98#ibcon#about to read 4, iclass 32, count 2 2006.173.21:24:03.98#ibcon#read 4, iclass 32, count 2 2006.173.21:24:03.98#ibcon#about to read 5, iclass 32, count 2 2006.173.21:24:03.98#ibcon#read 5, iclass 32, count 2 2006.173.21:24:03.98#ibcon#about to read 6, iclass 32, count 2 2006.173.21:24:03.98#ibcon#read 6, iclass 32, count 2 2006.173.21:24:03.98#ibcon#end of sib2, iclass 32, count 2 2006.173.21:24:03.98#ibcon#*mode == 0, iclass 32, count 2 2006.173.21:24:03.98#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.173.21:24:03.98#ibcon#[25=AT03-05\r\n] 2006.173.21:24:03.98#ibcon#*before write, iclass 32, count 2 2006.173.21:24:03.98#ibcon#enter sib2, iclass 32, count 2 2006.173.21:24:03.98#ibcon#flushed, iclass 32, count 2 2006.173.21:24:03.98#ibcon#about to write, iclass 32, count 2 2006.173.21:24:03.98#ibcon#wrote, iclass 32, count 2 2006.173.21:24:03.98#ibcon#about to read 3, iclass 32, count 2 2006.173.21:24:04.01#ibcon#read 3, iclass 32, count 2 2006.173.21:24:04.01#ibcon#about to read 4, iclass 32, count 2 2006.173.21:24:04.01#ibcon#read 4, iclass 32, count 2 2006.173.21:24:04.01#ibcon#about to read 5, iclass 32, count 2 2006.173.21:24:04.01#ibcon#read 5, iclass 32, count 2 2006.173.21:24:04.01#ibcon#about to read 6, iclass 32, count 2 2006.173.21:24:04.01#ibcon#read 6, iclass 32, count 2 2006.173.21:24:04.01#ibcon#end of sib2, iclass 32, count 2 2006.173.21:24:04.01#ibcon#*after write, iclass 32, count 2 2006.173.21:24:04.01#ibcon#*before return 0, iclass 32, count 2 2006.173.21:24:04.01#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.21:24:04.01#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.173.21:24:04.01#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.173.21:24:04.01#ibcon#ireg 7 cls_cnt 0 2006.173.21:24:04.01#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.21:24:04.13#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.21:24:04.13#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.21:24:04.13#ibcon#enter wrdev, iclass 32, count 0 2006.173.21:24:04.13#ibcon#first serial, iclass 32, count 0 2006.173.21:24:04.13#ibcon#enter sib2, iclass 32, count 0 2006.173.21:24:04.13#ibcon#flushed, iclass 32, count 0 2006.173.21:24:04.13#ibcon#about to write, iclass 32, count 0 2006.173.21:24:04.13#ibcon#wrote, iclass 32, count 0 2006.173.21:24:04.13#ibcon#about to read 3, iclass 32, count 0 2006.173.21:24:04.15#ibcon#read 3, iclass 32, count 0 2006.173.21:24:04.15#ibcon#about to read 4, iclass 32, count 0 2006.173.21:24:04.15#ibcon#read 4, iclass 32, count 0 2006.173.21:24:04.15#ibcon#about to read 5, iclass 32, count 0 2006.173.21:24:04.15#ibcon#read 5, iclass 32, count 0 2006.173.21:24:04.15#ibcon#about to read 6, iclass 32, count 0 2006.173.21:24:04.15#ibcon#read 6, iclass 32, count 0 2006.173.21:24:04.15#ibcon#end of sib2, iclass 32, count 0 2006.173.21:24:04.15#ibcon#*mode == 0, iclass 32, count 0 2006.173.21:24:04.15#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.21:24:04.15#ibcon#[25=USB\r\n] 2006.173.21:24:04.15#ibcon#*before write, iclass 32, count 0 2006.173.21:24:04.15#ibcon#enter sib2, iclass 32, count 0 2006.173.21:24:04.15#ibcon#flushed, iclass 32, count 0 2006.173.21:24:04.15#ibcon#about to write, iclass 32, count 0 2006.173.21:24:04.15#ibcon#wrote, iclass 32, count 0 2006.173.21:24:04.15#ibcon#about to read 3, iclass 32, count 0 2006.173.21:24:04.18#ibcon#read 3, iclass 32, count 0 2006.173.21:24:04.18#ibcon#about to read 4, iclass 32, count 0 2006.173.21:24:04.18#ibcon#read 4, iclass 32, count 0 2006.173.21:24:04.18#ibcon#about to read 5, iclass 32, count 0 2006.173.21:24:04.18#ibcon#read 5, iclass 32, count 0 2006.173.21:24:04.18#ibcon#about to read 6, iclass 32, count 0 2006.173.21:24:04.18#ibcon#read 6, iclass 32, count 0 2006.173.21:24:04.18#ibcon#end of sib2, iclass 32, count 0 2006.173.21:24:04.18#ibcon#*after write, iclass 32, count 0 2006.173.21:24:04.18#ibcon#*before return 0, iclass 32, count 0 2006.173.21:24:04.18#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.21:24:04.18#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.173.21:24:04.18#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.21:24:04.18#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.21:24:04.18$vck44/valo=4,624.99 2006.173.21:24:04.18#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.21:24:04.18#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.21:24:04.18#ibcon#ireg 17 cls_cnt 0 2006.173.21:24:04.18#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.21:24:04.18#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.21:24:04.18#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.21:24:04.18#ibcon#enter wrdev, iclass 34, count 0 2006.173.21:24:04.18#ibcon#first serial, iclass 34, count 0 2006.173.21:24:04.18#ibcon#enter sib2, iclass 34, count 0 2006.173.21:24:04.18#ibcon#flushed, iclass 34, count 0 2006.173.21:24:04.18#ibcon#about to write, iclass 34, count 0 2006.173.21:24:04.18#ibcon#wrote, iclass 34, count 0 2006.173.21:24:04.18#ibcon#about to read 3, iclass 34, count 0 2006.173.21:24:04.20#ibcon#read 3, iclass 34, count 0 2006.173.21:24:04.20#ibcon#about to read 4, iclass 34, count 0 2006.173.21:24:04.20#ibcon#read 4, iclass 34, count 0 2006.173.21:24:04.20#ibcon#about to read 5, iclass 34, count 0 2006.173.21:24:04.20#ibcon#read 5, iclass 34, count 0 2006.173.21:24:04.20#ibcon#about to read 6, iclass 34, count 0 2006.173.21:24:04.20#ibcon#read 6, iclass 34, count 0 2006.173.21:24:04.20#ibcon#end of sib2, iclass 34, count 0 2006.173.21:24:04.20#ibcon#*mode == 0, iclass 34, count 0 2006.173.21:24:04.20#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.21:24:04.20#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.21:24:04.20#ibcon#*before write, iclass 34, count 0 2006.173.21:24:04.20#ibcon#enter sib2, iclass 34, count 0 2006.173.21:24:04.20#ibcon#flushed, iclass 34, count 0 2006.173.21:24:04.20#ibcon#about to write, iclass 34, count 0 2006.173.21:24:04.20#ibcon#wrote, iclass 34, count 0 2006.173.21:24:04.20#ibcon#about to read 3, iclass 34, count 0 2006.173.21:24:04.24#ibcon#read 3, iclass 34, count 0 2006.173.21:24:04.24#ibcon#about to read 4, iclass 34, count 0 2006.173.21:24:04.24#ibcon#read 4, iclass 34, count 0 2006.173.21:24:04.24#ibcon#about to read 5, iclass 34, count 0 2006.173.21:24:04.24#ibcon#read 5, iclass 34, count 0 2006.173.21:24:04.24#ibcon#about to read 6, iclass 34, count 0 2006.173.21:24:04.24#ibcon#read 6, iclass 34, count 0 2006.173.21:24:04.24#ibcon#end of sib2, iclass 34, count 0 2006.173.21:24:04.24#ibcon#*after write, iclass 34, count 0 2006.173.21:24:04.24#ibcon#*before return 0, iclass 34, count 0 2006.173.21:24:04.24#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.21:24:04.24#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.21:24:04.24#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.21:24:04.24#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.21:24:04.24$vck44/va=4,6 2006.173.21:24:04.24#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.21:24:04.24#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.21:24:04.24#ibcon#ireg 11 cls_cnt 2 2006.173.21:24:04.24#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.21:24:04.30#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.21:24:04.30#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.21:24:04.30#ibcon#enter wrdev, iclass 36, count 2 2006.173.21:24:04.30#ibcon#first serial, iclass 36, count 2 2006.173.21:24:04.30#ibcon#enter sib2, iclass 36, count 2 2006.173.21:24:04.30#ibcon#flushed, iclass 36, count 2 2006.173.21:24:04.30#ibcon#about to write, iclass 36, count 2 2006.173.21:24:04.30#ibcon#wrote, iclass 36, count 2 2006.173.21:24:04.30#ibcon#about to read 3, iclass 36, count 2 2006.173.21:24:04.32#ibcon#read 3, iclass 36, count 2 2006.173.21:24:04.32#ibcon#about to read 4, iclass 36, count 2 2006.173.21:24:04.32#ibcon#read 4, iclass 36, count 2 2006.173.21:24:04.32#ibcon#about to read 5, iclass 36, count 2 2006.173.21:24:04.32#ibcon#read 5, iclass 36, count 2 2006.173.21:24:04.32#ibcon#about to read 6, iclass 36, count 2 2006.173.21:24:04.32#ibcon#read 6, iclass 36, count 2 2006.173.21:24:04.32#ibcon#end of sib2, iclass 36, count 2 2006.173.21:24:04.32#ibcon#*mode == 0, iclass 36, count 2 2006.173.21:24:04.32#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.21:24:04.32#ibcon#[25=AT04-06\r\n] 2006.173.21:24:04.32#ibcon#*before write, iclass 36, count 2 2006.173.21:24:04.32#ibcon#enter sib2, iclass 36, count 2 2006.173.21:24:04.32#ibcon#flushed, iclass 36, count 2 2006.173.21:24:04.32#ibcon#about to write, iclass 36, count 2 2006.173.21:24:04.32#ibcon#wrote, iclass 36, count 2 2006.173.21:24:04.32#ibcon#about to read 3, iclass 36, count 2 2006.173.21:24:04.35#ibcon#read 3, iclass 36, count 2 2006.173.21:24:04.35#ibcon#about to read 4, iclass 36, count 2 2006.173.21:24:04.35#ibcon#read 4, iclass 36, count 2 2006.173.21:24:04.35#ibcon#about to read 5, iclass 36, count 2 2006.173.21:24:04.35#ibcon#read 5, iclass 36, count 2 2006.173.21:24:04.35#ibcon#about to read 6, iclass 36, count 2 2006.173.21:24:04.35#ibcon#read 6, iclass 36, count 2 2006.173.21:24:04.35#ibcon#end of sib2, iclass 36, count 2 2006.173.21:24:04.35#ibcon#*after write, iclass 36, count 2 2006.173.21:24:04.35#ibcon#*before return 0, iclass 36, count 2 2006.173.21:24:04.35#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.21:24:04.35#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.21:24:04.35#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.21:24:04.35#ibcon#ireg 7 cls_cnt 0 2006.173.21:24:04.35#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.21:24:04.47#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.21:24:04.47#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.21:24:04.47#ibcon#enter wrdev, iclass 36, count 0 2006.173.21:24:04.47#ibcon#first serial, iclass 36, count 0 2006.173.21:24:04.47#ibcon#enter sib2, iclass 36, count 0 2006.173.21:24:04.47#ibcon#flushed, iclass 36, count 0 2006.173.21:24:04.47#ibcon#about to write, iclass 36, count 0 2006.173.21:24:04.47#ibcon#wrote, iclass 36, count 0 2006.173.21:24:04.47#ibcon#about to read 3, iclass 36, count 0 2006.173.21:24:04.49#ibcon#read 3, iclass 36, count 0 2006.173.21:24:04.49#ibcon#about to read 4, iclass 36, count 0 2006.173.21:24:04.49#ibcon#read 4, iclass 36, count 0 2006.173.21:24:04.49#ibcon#about to read 5, iclass 36, count 0 2006.173.21:24:04.49#ibcon#read 5, iclass 36, count 0 2006.173.21:24:04.49#ibcon#about to read 6, iclass 36, count 0 2006.173.21:24:04.49#ibcon#read 6, iclass 36, count 0 2006.173.21:24:04.49#ibcon#end of sib2, iclass 36, count 0 2006.173.21:24:04.49#ibcon#*mode == 0, iclass 36, count 0 2006.173.21:24:04.49#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.21:24:04.49#ibcon#[25=USB\r\n] 2006.173.21:24:04.49#ibcon#*before write, iclass 36, count 0 2006.173.21:24:04.49#ibcon#enter sib2, iclass 36, count 0 2006.173.21:24:04.49#ibcon#flushed, iclass 36, count 0 2006.173.21:24:04.49#ibcon#about to write, iclass 36, count 0 2006.173.21:24:04.49#ibcon#wrote, iclass 36, count 0 2006.173.21:24:04.49#ibcon#about to read 3, iclass 36, count 0 2006.173.21:24:04.52#ibcon#read 3, iclass 36, count 0 2006.173.21:24:04.52#ibcon#about to read 4, iclass 36, count 0 2006.173.21:24:04.52#ibcon#read 4, iclass 36, count 0 2006.173.21:24:04.52#ibcon#about to read 5, iclass 36, count 0 2006.173.21:24:04.52#ibcon#read 5, iclass 36, count 0 2006.173.21:24:04.52#ibcon#about to read 6, iclass 36, count 0 2006.173.21:24:04.52#ibcon#read 6, iclass 36, count 0 2006.173.21:24:04.52#ibcon#end of sib2, iclass 36, count 0 2006.173.21:24:04.52#ibcon#*after write, iclass 36, count 0 2006.173.21:24:04.52#ibcon#*before return 0, iclass 36, count 0 2006.173.21:24:04.52#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.21:24:04.52#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.21:24:04.52#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.21:24:04.52#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.21:24:04.52$vck44/valo=5,734.99 2006.173.21:24:04.52#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.21:24:04.52#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.21:24:04.52#ibcon#ireg 17 cls_cnt 0 2006.173.21:24:04.52#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.21:24:04.52#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.21:24:04.52#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.21:24:04.52#ibcon#enter wrdev, iclass 38, count 0 2006.173.21:24:04.52#ibcon#first serial, iclass 38, count 0 2006.173.21:24:04.52#ibcon#enter sib2, iclass 38, count 0 2006.173.21:24:04.52#ibcon#flushed, iclass 38, count 0 2006.173.21:24:04.52#ibcon#about to write, iclass 38, count 0 2006.173.21:24:04.52#ibcon#wrote, iclass 38, count 0 2006.173.21:24:04.52#ibcon#about to read 3, iclass 38, count 0 2006.173.21:24:04.54#ibcon#read 3, iclass 38, count 0 2006.173.21:24:04.54#ibcon#about to read 4, iclass 38, count 0 2006.173.21:24:04.54#ibcon#read 4, iclass 38, count 0 2006.173.21:24:04.54#ibcon#about to read 5, iclass 38, count 0 2006.173.21:24:04.54#ibcon#read 5, iclass 38, count 0 2006.173.21:24:04.54#ibcon#about to read 6, iclass 38, count 0 2006.173.21:24:04.54#ibcon#read 6, iclass 38, count 0 2006.173.21:24:04.54#ibcon#end of sib2, iclass 38, count 0 2006.173.21:24:04.54#ibcon#*mode == 0, iclass 38, count 0 2006.173.21:24:04.54#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.21:24:04.54#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.21:24:04.54#ibcon#*before write, iclass 38, count 0 2006.173.21:24:04.54#ibcon#enter sib2, iclass 38, count 0 2006.173.21:24:04.54#ibcon#flushed, iclass 38, count 0 2006.173.21:24:04.54#ibcon#about to write, iclass 38, count 0 2006.173.21:24:04.54#ibcon#wrote, iclass 38, count 0 2006.173.21:24:04.54#ibcon#about to read 3, iclass 38, count 0 2006.173.21:24:04.58#ibcon#read 3, iclass 38, count 0 2006.173.21:24:04.58#ibcon#about to read 4, iclass 38, count 0 2006.173.21:24:04.58#ibcon#read 4, iclass 38, count 0 2006.173.21:24:04.58#ibcon#about to read 5, iclass 38, count 0 2006.173.21:24:04.58#ibcon#read 5, iclass 38, count 0 2006.173.21:24:04.58#ibcon#about to read 6, iclass 38, count 0 2006.173.21:24:04.58#ibcon#read 6, iclass 38, count 0 2006.173.21:24:04.58#ibcon#end of sib2, iclass 38, count 0 2006.173.21:24:04.58#ibcon#*after write, iclass 38, count 0 2006.173.21:24:04.58#ibcon#*before return 0, iclass 38, count 0 2006.173.21:24:04.58#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.21:24:04.58#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.21:24:04.58#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.21:24:04.58#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.21:24:04.58$vck44/va=5,4 2006.173.21:24:04.58#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.21:24:04.58#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.21:24:04.58#ibcon#ireg 11 cls_cnt 2 2006.173.21:24:04.58#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.21:24:04.64#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.21:24:04.64#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.21:24:04.64#ibcon#enter wrdev, iclass 40, count 2 2006.173.21:24:04.64#ibcon#first serial, iclass 40, count 2 2006.173.21:24:04.64#ibcon#enter sib2, iclass 40, count 2 2006.173.21:24:04.64#ibcon#flushed, iclass 40, count 2 2006.173.21:24:04.64#ibcon#about to write, iclass 40, count 2 2006.173.21:24:04.64#ibcon#wrote, iclass 40, count 2 2006.173.21:24:04.64#ibcon#about to read 3, iclass 40, count 2 2006.173.21:24:04.66#ibcon#read 3, iclass 40, count 2 2006.173.21:24:04.66#ibcon#about to read 4, iclass 40, count 2 2006.173.21:24:04.66#ibcon#read 4, iclass 40, count 2 2006.173.21:24:04.66#ibcon#about to read 5, iclass 40, count 2 2006.173.21:24:04.66#ibcon#read 5, iclass 40, count 2 2006.173.21:24:04.66#ibcon#about to read 6, iclass 40, count 2 2006.173.21:24:04.66#ibcon#read 6, iclass 40, count 2 2006.173.21:24:04.66#ibcon#end of sib2, iclass 40, count 2 2006.173.21:24:04.66#ibcon#*mode == 0, iclass 40, count 2 2006.173.21:24:04.66#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.21:24:04.66#ibcon#[25=AT05-04\r\n] 2006.173.21:24:04.66#ibcon#*before write, iclass 40, count 2 2006.173.21:24:04.66#ibcon#enter sib2, iclass 40, count 2 2006.173.21:24:04.66#ibcon#flushed, iclass 40, count 2 2006.173.21:24:04.66#ibcon#about to write, iclass 40, count 2 2006.173.21:24:04.66#ibcon#wrote, iclass 40, count 2 2006.173.21:24:04.66#ibcon#about to read 3, iclass 40, count 2 2006.173.21:24:04.69#ibcon#read 3, iclass 40, count 2 2006.173.21:24:04.69#ibcon#about to read 4, iclass 40, count 2 2006.173.21:24:04.69#ibcon#read 4, iclass 40, count 2 2006.173.21:24:04.69#ibcon#about to read 5, iclass 40, count 2 2006.173.21:24:04.69#ibcon#read 5, iclass 40, count 2 2006.173.21:24:04.69#ibcon#about to read 6, iclass 40, count 2 2006.173.21:24:04.69#ibcon#read 6, iclass 40, count 2 2006.173.21:24:04.69#ibcon#end of sib2, iclass 40, count 2 2006.173.21:24:04.69#ibcon#*after write, iclass 40, count 2 2006.173.21:24:04.69#ibcon#*before return 0, iclass 40, count 2 2006.173.21:24:04.69#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.21:24:04.69#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.21:24:04.69#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.21:24:04.69#ibcon#ireg 7 cls_cnt 0 2006.173.21:24:04.69#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.21:24:04.81#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.21:24:04.81#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.21:24:04.81#ibcon#enter wrdev, iclass 40, count 0 2006.173.21:24:04.81#ibcon#first serial, iclass 40, count 0 2006.173.21:24:04.81#ibcon#enter sib2, iclass 40, count 0 2006.173.21:24:04.81#ibcon#flushed, iclass 40, count 0 2006.173.21:24:04.81#ibcon#about to write, iclass 40, count 0 2006.173.21:24:04.81#ibcon#wrote, iclass 40, count 0 2006.173.21:24:04.81#ibcon#about to read 3, iclass 40, count 0 2006.173.21:24:04.83#ibcon#read 3, iclass 40, count 0 2006.173.21:24:04.83#ibcon#about to read 4, iclass 40, count 0 2006.173.21:24:04.83#ibcon#read 4, iclass 40, count 0 2006.173.21:24:04.83#ibcon#about to read 5, iclass 40, count 0 2006.173.21:24:04.83#ibcon#read 5, iclass 40, count 0 2006.173.21:24:04.83#ibcon#about to read 6, iclass 40, count 0 2006.173.21:24:04.83#ibcon#read 6, iclass 40, count 0 2006.173.21:24:04.83#ibcon#end of sib2, iclass 40, count 0 2006.173.21:24:04.83#ibcon#*mode == 0, iclass 40, count 0 2006.173.21:24:04.83#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.21:24:04.83#ibcon#[25=USB\r\n] 2006.173.21:24:04.83#ibcon#*before write, iclass 40, count 0 2006.173.21:24:04.83#ibcon#enter sib2, iclass 40, count 0 2006.173.21:24:04.83#ibcon#flushed, iclass 40, count 0 2006.173.21:24:04.83#ibcon#about to write, iclass 40, count 0 2006.173.21:24:04.83#ibcon#wrote, iclass 40, count 0 2006.173.21:24:04.83#ibcon#about to read 3, iclass 40, count 0 2006.173.21:24:04.86#ibcon#read 3, iclass 40, count 0 2006.173.21:24:04.86#ibcon#about to read 4, iclass 40, count 0 2006.173.21:24:04.86#ibcon#read 4, iclass 40, count 0 2006.173.21:24:04.86#ibcon#about to read 5, iclass 40, count 0 2006.173.21:24:04.86#ibcon#read 5, iclass 40, count 0 2006.173.21:24:04.86#ibcon#about to read 6, iclass 40, count 0 2006.173.21:24:04.86#ibcon#read 6, iclass 40, count 0 2006.173.21:24:04.86#ibcon#end of sib2, iclass 40, count 0 2006.173.21:24:04.86#ibcon#*after write, iclass 40, count 0 2006.173.21:24:04.86#ibcon#*before return 0, iclass 40, count 0 2006.173.21:24:04.86#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.21:24:04.86#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.21:24:04.86#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.21:24:04.86#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.21:24:04.86$vck44/valo=6,814.99 2006.173.21:24:04.86#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.21:24:04.86#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.21:24:04.86#ibcon#ireg 17 cls_cnt 0 2006.173.21:24:04.86#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.21:24:04.86#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.21:24:04.86#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.21:24:04.86#ibcon#enter wrdev, iclass 4, count 0 2006.173.21:24:04.86#ibcon#first serial, iclass 4, count 0 2006.173.21:24:04.86#ibcon#enter sib2, iclass 4, count 0 2006.173.21:24:04.86#ibcon#flushed, iclass 4, count 0 2006.173.21:24:04.86#ibcon#about to write, iclass 4, count 0 2006.173.21:24:04.86#ibcon#wrote, iclass 4, count 0 2006.173.21:24:04.86#ibcon#about to read 3, iclass 4, count 0 2006.173.21:24:04.88#ibcon#read 3, iclass 4, count 0 2006.173.21:24:04.88#ibcon#about to read 4, iclass 4, count 0 2006.173.21:24:04.88#ibcon#read 4, iclass 4, count 0 2006.173.21:24:04.88#ibcon#about to read 5, iclass 4, count 0 2006.173.21:24:04.88#ibcon#read 5, iclass 4, count 0 2006.173.21:24:04.88#ibcon#about to read 6, iclass 4, count 0 2006.173.21:24:04.88#ibcon#read 6, iclass 4, count 0 2006.173.21:24:04.88#ibcon#end of sib2, iclass 4, count 0 2006.173.21:24:04.88#ibcon#*mode == 0, iclass 4, count 0 2006.173.21:24:04.88#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.21:24:04.88#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.21:24:04.88#ibcon#*before write, iclass 4, count 0 2006.173.21:24:04.88#ibcon#enter sib2, iclass 4, count 0 2006.173.21:24:04.88#ibcon#flushed, iclass 4, count 0 2006.173.21:24:04.88#ibcon#about to write, iclass 4, count 0 2006.173.21:24:04.88#ibcon#wrote, iclass 4, count 0 2006.173.21:24:04.88#ibcon#about to read 3, iclass 4, count 0 2006.173.21:24:04.92#ibcon#read 3, iclass 4, count 0 2006.173.21:24:04.92#ibcon#about to read 4, iclass 4, count 0 2006.173.21:24:04.92#ibcon#read 4, iclass 4, count 0 2006.173.21:24:04.92#ibcon#about to read 5, iclass 4, count 0 2006.173.21:24:04.92#ibcon#read 5, iclass 4, count 0 2006.173.21:24:04.92#ibcon#about to read 6, iclass 4, count 0 2006.173.21:24:04.92#ibcon#read 6, iclass 4, count 0 2006.173.21:24:04.92#ibcon#end of sib2, iclass 4, count 0 2006.173.21:24:04.92#ibcon#*after write, iclass 4, count 0 2006.173.21:24:04.92#ibcon#*before return 0, iclass 4, count 0 2006.173.21:24:04.92#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.21:24:04.92#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.21:24:04.92#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.21:24:04.92#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.21:24:04.92$vck44/va=6,3 2006.173.21:24:04.92#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.21:24:04.92#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.21:24:04.92#ibcon#ireg 11 cls_cnt 2 2006.173.21:24:04.92#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.21:24:04.98#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.21:24:04.98#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.21:24:04.98#ibcon#enter wrdev, iclass 6, count 2 2006.173.21:24:04.98#ibcon#first serial, iclass 6, count 2 2006.173.21:24:04.98#ibcon#enter sib2, iclass 6, count 2 2006.173.21:24:04.98#ibcon#flushed, iclass 6, count 2 2006.173.21:24:04.98#ibcon#about to write, iclass 6, count 2 2006.173.21:24:04.98#ibcon#wrote, iclass 6, count 2 2006.173.21:24:04.98#ibcon#about to read 3, iclass 6, count 2 2006.173.21:24:05.00#ibcon#read 3, iclass 6, count 2 2006.173.21:24:05.00#ibcon#about to read 4, iclass 6, count 2 2006.173.21:24:05.00#ibcon#read 4, iclass 6, count 2 2006.173.21:24:05.00#ibcon#about to read 5, iclass 6, count 2 2006.173.21:24:05.00#ibcon#read 5, iclass 6, count 2 2006.173.21:24:05.00#ibcon#about to read 6, iclass 6, count 2 2006.173.21:24:05.00#ibcon#read 6, iclass 6, count 2 2006.173.21:24:05.00#ibcon#end of sib2, iclass 6, count 2 2006.173.21:24:05.00#ibcon#*mode == 0, iclass 6, count 2 2006.173.21:24:05.00#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.21:24:05.00#ibcon#[25=AT06-03\r\n] 2006.173.21:24:05.00#ibcon#*before write, iclass 6, count 2 2006.173.21:24:05.00#ibcon#enter sib2, iclass 6, count 2 2006.173.21:24:05.00#ibcon#flushed, iclass 6, count 2 2006.173.21:24:05.00#ibcon#about to write, iclass 6, count 2 2006.173.21:24:05.00#ibcon#wrote, iclass 6, count 2 2006.173.21:24:05.00#ibcon#about to read 3, iclass 6, count 2 2006.173.21:24:05.03#ibcon#read 3, iclass 6, count 2 2006.173.21:24:05.03#ibcon#about to read 4, iclass 6, count 2 2006.173.21:24:05.03#ibcon#read 4, iclass 6, count 2 2006.173.21:24:05.03#ibcon#about to read 5, iclass 6, count 2 2006.173.21:24:05.03#ibcon#read 5, iclass 6, count 2 2006.173.21:24:05.03#ibcon#about to read 6, iclass 6, count 2 2006.173.21:24:05.03#ibcon#read 6, iclass 6, count 2 2006.173.21:24:05.03#ibcon#end of sib2, iclass 6, count 2 2006.173.21:24:05.03#ibcon#*after write, iclass 6, count 2 2006.173.21:24:05.03#ibcon#*before return 0, iclass 6, count 2 2006.173.21:24:05.03#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.21:24:05.03#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.21:24:05.03#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.21:24:05.03#ibcon#ireg 7 cls_cnt 0 2006.173.21:24:05.03#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.21:24:05.15#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.21:24:05.15#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.21:24:05.15#ibcon#enter wrdev, iclass 6, count 0 2006.173.21:24:05.15#ibcon#first serial, iclass 6, count 0 2006.173.21:24:05.15#ibcon#enter sib2, iclass 6, count 0 2006.173.21:24:05.15#ibcon#flushed, iclass 6, count 0 2006.173.21:24:05.15#ibcon#about to write, iclass 6, count 0 2006.173.21:24:05.15#ibcon#wrote, iclass 6, count 0 2006.173.21:24:05.15#ibcon#about to read 3, iclass 6, count 0 2006.173.21:24:05.17#ibcon#read 3, iclass 6, count 0 2006.173.21:24:05.17#ibcon#about to read 4, iclass 6, count 0 2006.173.21:24:05.17#ibcon#read 4, iclass 6, count 0 2006.173.21:24:05.17#ibcon#about to read 5, iclass 6, count 0 2006.173.21:24:05.17#ibcon#read 5, iclass 6, count 0 2006.173.21:24:05.17#ibcon#about to read 6, iclass 6, count 0 2006.173.21:24:05.17#ibcon#read 6, iclass 6, count 0 2006.173.21:24:05.17#ibcon#end of sib2, iclass 6, count 0 2006.173.21:24:05.17#ibcon#*mode == 0, iclass 6, count 0 2006.173.21:24:05.17#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.21:24:05.17#ibcon#[25=USB\r\n] 2006.173.21:24:05.17#ibcon#*before write, iclass 6, count 0 2006.173.21:24:05.17#ibcon#enter sib2, iclass 6, count 0 2006.173.21:24:05.17#ibcon#flushed, iclass 6, count 0 2006.173.21:24:05.17#ibcon#about to write, iclass 6, count 0 2006.173.21:24:05.17#ibcon#wrote, iclass 6, count 0 2006.173.21:24:05.17#ibcon#about to read 3, iclass 6, count 0 2006.173.21:24:05.20#ibcon#read 3, iclass 6, count 0 2006.173.21:24:05.20#ibcon#about to read 4, iclass 6, count 0 2006.173.21:24:05.20#ibcon#read 4, iclass 6, count 0 2006.173.21:24:05.20#ibcon#about to read 5, iclass 6, count 0 2006.173.21:24:05.20#ibcon#read 5, iclass 6, count 0 2006.173.21:24:05.20#ibcon#about to read 6, iclass 6, count 0 2006.173.21:24:05.20#ibcon#read 6, iclass 6, count 0 2006.173.21:24:05.20#ibcon#end of sib2, iclass 6, count 0 2006.173.21:24:05.20#ibcon#*after write, iclass 6, count 0 2006.173.21:24:05.20#ibcon#*before return 0, iclass 6, count 0 2006.173.21:24:05.20#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.21:24:05.20#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.21:24:05.20#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.21:24:05.20#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.21:24:05.20$vck44/valo=7,864.99 2006.173.21:24:05.20#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.21:24:05.20#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.21:24:05.20#ibcon#ireg 17 cls_cnt 0 2006.173.21:24:05.20#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.21:24:05.20#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.21:24:05.20#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.21:24:05.20#ibcon#enter wrdev, iclass 10, count 0 2006.173.21:24:05.20#ibcon#first serial, iclass 10, count 0 2006.173.21:24:05.20#ibcon#enter sib2, iclass 10, count 0 2006.173.21:24:05.20#ibcon#flushed, iclass 10, count 0 2006.173.21:24:05.20#ibcon#about to write, iclass 10, count 0 2006.173.21:24:05.20#ibcon#wrote, iclass 10, count 0 2006.173.21:24:05.20#ibcon#about to read 3, iclass 10, count 0 2006.173.21:24:05.22#ibcon#read 3, iclass 10, count 0 2006.173.21:24:05.22#ibcon#about to read 4, iclass 10, count 0 2006.173.21:24:05.22#ibcon#read 4, iclass 10, count 0 2006.173.21:24:05.22#ibcon#about to read 5, iclass 10, count 0 2006.173.21:24:05.22#ibcon#read 5, iclass 10, count 0 2006.173.21:24:05.22#ibcon#about to read 6, iclass 10, count 0 2006.173.21:24:05.22#ibcon#read 6, iclass 10, count 0 2006.173.21:24:05.22#ibcon#end of sib2, iclass 10, count 0 2006.173.21:24:05.22#ibcon#*mode == 0, iclass 10, count 0 2006.173.21:24:05.22#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.21:24:05.22#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.21:24:05.22#ibcon#*before write, iclass 10, count 0 2006.173.21:24:05.22#ibcon#enter sib2, iclass 10, count 0 2006.173.21:24:05.22#ibcon#flushed, iclass 10, count 0 2006.173.21:24:05.22#ibcon#about to write, iclass 10, count 0 2006.173.21:24:05.22#ibcon#wrote, iclass 10, count 0 2006.173.21:24:05.22#ibcon#about to read 3, iclass 10, count 0 2006.173.21:24:05.26#ibcon#read 3, iclass 10, count 0 2006.173.21:24:05.26#ibcon#about to read 4, iclass 10, count 0 2006.173.21:24:05.26#ibcon#read 4, iclass 10, count 0 2006.173.21:24:05.26#ibcon#about to read 5, iclass 10, count 0 2006.173.21:24:05.26#ibcon#read 5, iclass 10, count 0 2006.173.21:24:05.26#ibcon#about to read 6, iclass 10, count 0 2006.173.21:24:05.26#ibcon#read 6, iclass 10, count 0 2006.173.21:24:05.26#ibcon#end of sib2, iclass 10, count 0 2006.173.21:24:05.26#ibcon#*after write, iclass 10, count 0 2006.173.21:24:05.26#ibcon#*before return 0, iclass 10, count 0 2006.173.21:24:05.26#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.21:24:05.26#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.21:24:05.26#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.21:24:05.26#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.21:24:05.26$vck44/va=7,4 2006.173.21:24:05.26#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.21:24:05.26#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.21:24:05.26#ibcon#ireg 11 cls_cnt 2 2006.173.21:24:05.26#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.21:24:05.32#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.21:24:05.32#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.21:24:05.32#ibcon#enter wrdev, iclass 12, count 2 2006.173.21:24:05.32#ibcon#first serial, iclass 12, count 2 2006.173.21:24:05.32#ibcon#enter sib2, iclass 12, count 2 2006.173.21:24:05.32#ibcon#flushed, iclass 12, count 2 2006.173.21:24:05.32#ibcon#about to write, iclass 12, count 2 2006.173.21:24:05.32#ibcon#wrote, iclass 12, count 2 2006.173.21:24:05.32#ibcon#about to read 3, iclass 12, count 2 2006.173.21:24:05.34#ibcon#read 3, iclass 12, count 2 2006.173.21:24:05.34#ibcon#about to read 4, iclass 12, count 2 2006.173.21:24:05.34#ibcon#read 4, iclass 12, count 2 2006.173.21:24:05.34#ibcon#about to read 5, iclass 12, count 2 2006.173.21:24:05.34#ibcon#read 5, iclass 12, count 2 2006.173.21:24:05.34#ibcon#about to read 6, iclass 12, count 2 2006.173.21:24:05.34#ibcon#read 6, iclass 12, count 2 2006.173.21:24:05.34#ibcon#end of sib2, iclass 12, count 2 2006.173.21:24:05.34#ibcon#*mode == 0, iclass 12, count 2 2006.173.21:24:05.34#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.21:24:05.34#ibcon#[25=AT07-04\r\n] 2006.173.21:24:05.34#ibcon#*before write, iclass 12, count 2 2006.173.21:24:05.34#ibcon#enter sib2, iclass 12, count 2 2006.173.21:24:05.34#ibcon#flushed, iclass 12, count 2 2006.173.21:24:05.34#ibcon#about to write, iclass 12, count 2 2006.173.21:24:05.34#ibcon#wrote, iclass 12, count 2 2006.173.21:24:05.34#ibcon#about to read 3, iclass 12, count 2 2006.173.21:24:05.37#ibcon#read 3, iclass 12, count 2 2006.173.21:24:05.37#ibcon#about to read 4, iclass 12, count 2 2006.173.21:24:05.37#ibcon#read 4, iclass 12, count 2 2006.173.21:24:05.37#ibcon#about to read 5, iclass 12, count 2 2006.173.21:24:05.37#ibcon#read 5, iclass 12, count 2 2006.173.21:24:05.37#ibcon#about to read 6, iclass 12, count 2 2006.173.21:24:05.37#ibcon#read 6, iclass 12, count 2 2006.173.21:24:05.37#ibcon#end of sib2, iclass 12, count 2 2006.173.21:24:05.37#ibcon#*after write, iclass 12, count 2 2006.173.21:24:05.37#ibcon#*before return 0, iclass 12, count 2 2006.173.21:24:05.37#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.21:24:05.37#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.21:24:05.37#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.21:24:05.37#ibcon#ireg 7 cls_cnt 0 2006.173.21:24:05.37#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.21:24:05.49#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.21:24:05.49#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.21:24:05.49#ibcon#enter wrdev, iclass 12, count 0 2006.173.21:24:05.49#ibcon#first serial, iclass 12, count 0 2006.173.21:24:05.49#ibcon#enter sib2, iclass 12, count 0 2006.173.21:24:05.49#ibcon#flushed, iclass 12, count 0 2006.173.21:24:05.49#ibcon#about to write, iclass 12, count 0 2006.173.21:24:05.49#ibcon#wrote, iclass 12, count 0 2006.173.21:24:05.49#ibcon#about to read 3, iclass 12, count 0 2006.173.21:24:05.51#ibcon#read 3, iclass 12, count 0 2006.173.21:24:05.51#ibcon#about to read 4, iclass 12, count 0 2006.173.21:24:05.51#ibcon#read 4, iclass 12, count 0 2006.173.21:24:05.51#ibcon#about to read 5, iclass 12, count 0 2006.173.21:24:05.51#ibcon#read 5, iclass 12, count 0 2006.173.21:24:05.51#ibcon#about to read 6, iclass 12, count 0 2006.173.21:24:05.51#ibcon#read 6, iclass 12, count 0 2006.173.21:24:05.51#ibcon#end of sib2, iclass 12, count 0 2006.173.21:24:05.51#ibcon#*mode == 0, iclass 12, count 0 2006.173.21:24:05.51#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.21:24:05.51#ibcon#[25=USB\r\n] 2006.173.21:24:05.51#ibcon#*before write, iclass 12, count 0 2006.173.21:24:05.51#ibcon#enter sib2, iclass 12, count 0 2006.173.21:24:05.51#ibcon#flushed, iclass 12, count 0 2006.173.21:24:05.51#ibcon#about to write, iclass 12, count 0 2006.173.21:24:05.51#ibcon#wrote, iclass 12, count 0 2006.173.21:24:05.51#ibcon#about to read 3, iclass 12, count 0 2006.173.21:24:05.54#ibcon#read 3, iclass 12, count 0 2006.173.21:24:05.54#ibcon#about to read 4, iclass 12, count 0 2006.173.21:24:05.54#ibcon#read 4, iclass 12, count 0 2006.173.21:24:05.54#ibcon#about to read 5, iclass 12, count 0 2006.173.21:24:05.54#ibcon#read 5, iclass 12, count 0 2006.173.21:24:05.54#ibcon#about to read 6, iclass 12, count 0 2006.173.21:24:05.54#ibcon#read 6, iclass 12, count 0 2006.173.21:24:05.54#ibcon#end of sib2, iclass 12, count 0 2006.173.21:24:05.54#ibcon#*after write, iclass 12, count 0 2006.173.21:24:05.54#ibcon#*before return 0, iclass 12, count 0 2006.173.21:24:05.54#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.21:24:05.54#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.21:24:05.54#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.21:24:05.54#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.21:24:05.54$vck44/valo=8,884.99 2006.173.21:24:05.54#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.21:24:05.54#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.21:24:05.54#ibcon#ireg 17 cls_cnt 0 2006.173.21:24:05.54#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.21:24:05.54#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.21:24:05.54#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.21:24:05.54#ibcon#enter wrdev, iclass 14, count 0 2006.173.21:24:05.54#ibcon#first serial, iclass 14, count 0 2006.173.21:24:05.54#ibcon#enter sib2, iclass 14, count 0 2006.173.21:24:05.54#ibcon#flushed, iclass 14, count 0 2006.173.21:24:05.54#ibcon#about to write, iclass 14, count 0 2006.173.21:24:05.54#ibcon#wrote, iclass 14, count 0 2006.173.21:24:05.54#ibcon#about to read 3, iclass 14, count 0 2006.173.21:24:05.56#ibcon#read 3, iclass 14, count 0 2006.173.21:24:05.56#ibcon#about to read 4, iclass 14, count 0 2006.173.21:24:05.56#ibcon#read 4, iclass 14, count 0 2006.173.21:24:05.56#ibcon#about to read 5, iclass 14, count 0 2006.173.21:24:05.56#ibcon#read 5, iclass 14, count 0 2006.173.21:24:05.56#ibcon#about to read 6, iclass 14, count 0 2006.173.21:24:05.56#ibcon#read 6, iclass 14, count 0 2006.173.21:24:05.56#ibcon#end of sib2, iclass 14, count 0 2006.173.21:24:05.56#ibcon#*mode == 0, iclass 14, count 0 2006.173.21:24:05.56#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.21:24:05.56#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.21:24:05.56#ibcon#*before write, iclass 14, count 0 2006.173.21:24:05.56#ibcon#enter sib2, iclass 14, count 0 2006.173.21:24:05.56#ibcon#flushed, iclass 14, count 0 2006.173.21:24:05.56#ibcon#about to write, iclass 14, count 0 2006.173.21:24:05.56#ibcon#wrote, iclass 14, count 0 2006.173.21:24:05.56#ibcon#about to read 3, iclass 14, count 0 2006.173.21:24:05.60#ibcon#read 3, iclass 14, count 0 2006.173.21:24:05.60#ibcon#about to read 4, iclass 14, count 0 2006.173.21:24:05.60#ibcon#read 4, iclass 14, count 0 2006.173.21:24:05.60#ibcon#about to read 5, iclass 14, count 0 2006.173.21:24:05.60#ibcon#read 5, iclass 14, count 0 2006.173.21:24:05.60#ibcon#about to read 6, iclass 14, count 0 2006.173.21:24:05.60#ibcon#read 6, iclass 14, count 0 2006.173.21:24:05.60#ibcon#end of sib2, iclass 14, count 0 2006.173.21:24:05.60#ibcon#*after write, iclass 14, count 0 2006.173.21:24:05.60#ibcon#*before return 0, iclass 14, count 0 2006.173.21:24:05.60#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.21:24:05.60#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.21:24:05.60#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.21:24:05.60#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.21:24:05.60$vck44/va=8,4 2006.173.21:24:05.60#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.21:24:05.60#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.21:24:05.60#ibcon#ireg 11 cls_cnt 2 2006.173.21:24:05.60#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.21:24:05.66#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.21:24:05.66#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.21:24:05.66#ibcon#enter wrdev, iclass 16, count 2 2006.173.21:24:05.66#ibcon#first serial, iclass 16, count 2 2006.173.21:24:05.66#ibcon#enter sib2, iclass 16, count 2 2006.173.21:24:05.66#ibcon#flushed, iclass 16, count 2 2006.173.21:24:05.66#ibcon#about to write, iclass 16, count 2 2006.173.21:24:05.66#ibcon#wrote, iclass 16, count 2 2006.173.21:24:05.66#ibcon#about to read 3, iclass 16, count 2 2006.173.21:24:05.68#ibcon#read 3, iclass 16, count 2 2006.173.21:24:05.68#ibcon#about to read 4, iclass 16, count 2 2006.173.21:24:05.68#ibcon#read 4, iclass 16, count 2 2006.173.21:24:05.68#ibcon#about to read 5, iclass 16, count 2 2006.173.21:24:05.68#ibcon#read 5, iclass 16, count 2 2006.173.21:24:05.68#ibcon#about to read 6, iclass 16, count 2 2006.173.21:24:05.68#ibcon#read 6, iclass 16, count 2 2006.173.21:24:05.68#ibcon#end of sib2, iclass 16, count 2 2006.173.21:24:05.68#ibcon#*mode == 0, iclass 16, count 2 2006.173.21:24:05.68#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.21:24:05.68#ibcon#[25=AT08-04\r\n] 2006.173.21:24:05.68#ibcon#*before write, iclass 16, count 2 2006.173.21:24:05.68#ibcon#enter sib2, iclass 16, count 2 2006.173.21:24:05.68#ibcon#flushed, iclass 16, count 2 2006.173.21:24:05.68#ibcon#about to write, iclass 16, count 2 2006.173.21:24:05.68#ibcon#wrote, iclass 16, count 2 2006.173.21:24:05.68#ibcon#about to read 3, iclass 16, count 2 2006.173.21:24:05.71#ibcon#read 3, iclass 16, count 2 2006.173.21:24:05.71#ibcon#about to read 4, iclass 16, count 2 2006.173.21:24:05.71#ibcon#read 4, iclass 16, count 2 2006.173.21:24:05.71#ibcon#about to read 5, iclass 16, count 2 2006.173.21:24:05.71#ibcon#read 5, iclass 16, count 2 2006.173.21:24:05.71#ibcon#about to read 6, iclass 16, count 2 2006.173.21:24:05.71#ibcon#read 6, iclass 16, count 2 2006.173.21:24:05.71#ibcon#end of sib2, iclass 16, count 2 2006.173.21:24:05.71#ibcon#*after write, iclass 16, count 2 2006.173.21:24:05.71#ibcon#*before return 0, iclass 16, count 2 2006.173.21:24:05.71#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.21:24:05.71#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.21:24:05.71#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.21:24:05.71#ibcon#ireg 7 cls_cnt 0 2006.173.21:24:05.71#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.21:24:05.83#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.21:24:05.83#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.21:24:05.83#ibcon#enter wrdev, iclass 16, count 0 2006.173.21:24:05.83#ibcon#first serial, iclass 16, count 0 2006.173.21:24:05.83#ibcon#enter sib2, iclass 16, count 0 2006.173.21:24:05.83#ibcon#flushed, iclass 16, count 0 2006.173.21:24:05.83#ibcon#about to write, iclass 16, count 0 2006.173.21:24:05.83#ibcon#wrote, iclass 16, count 0 2006.173.21:24:05.83#ibcon#about to read 3, iclass 16, count 0 2006.173.21:24:05.85#ibcon#read 3, iclass 16, count 0 2006.173.21:24:05.85#ibcon#about to read 4, iclass 16, count 0 2006.173.21:24:05.85#ibcon#read 4, iclass 16, count 0 2006.173.21:24:05.85#ibcon#about to read 5, iclass 16, count 0 2006.173.21:24:05.85#ibcon#read 5, iclass 16, count 0 2006.173.21:24:05.85#ibcon#about to read 6, iclass 16, count 0 2006.173.21:24:05.85#ibcon#read 6, iclass 16, count 0 2006.173.21:24:05.85#ibcon#end of sib2, iclass 16, count 0 2006.173.21:24:05.85#ibcon#*mode == 0, iclass 16, count 0 2006.173.21:24:05.85#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.21:24:05.85#ibcon#[25=USB\r\n] 2006.173.21:24:05.85#ibcon#*before write, iclass 16, count 0 2006.173.21:24:05.85#ibcon#enter sib2, iclass 16, count 0 2006.173.21:24:05.85#ibcon#flushed, iclass 16, count 0 2006.173.21:24:05.85#ibcon#about to write, iclass 16, count 0 2006.173.21:24:05.85#ibcon#wrote, iclass 16, count 0 2006.173.21:24:05.85#ibcon#about to read 3, iclass 16, count 0 2006.173.21:24:05.88#ibcon#read 3, iclass 16, count 0 2006.173.21:24:05.88#ibcon#about to read 4, iclass 16, count 0 2006.173.21:24:05.88#ibcon#read 4, iclass 16, count 0 2006.173.21:24:05.88#ibcon#about to read 5, iclass 16, count 0 2006.173.21:24:05.88#ibcon#read 5, iclass 16, count 0 2006.173.21:24:05.88#ibcon#about to read 6, iclass 16, count 0 2006.173.21:24:05.88#ibcon#read 6, iclass 16, count 0 2006.173.21:24:05.88#ibcon#end of sib2, iclass 16, count 0 2006.173.21:24:05.88#ibcon#*after write, iclass 16, count 0 2006.173.21:24:05.88#ibcon#*before return 0, iclass 16, count 0 2006.173.21:24:05.88#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.21:24:05.88#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.21:24:05.88#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.21:24:05.88#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.21:24:05.88$vck44/vblo=1,629.99 2006.173.21:24:05.88#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.21:24:05.88#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.21:24:05.88#ibcon#ireg 17 cls_cnt 0 2006.173.21:24:05.88#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.21:24:05.88#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.21:24:05.88#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.21:24:05.88#ibcon#enter wrdev, iclass 18, count 0 2006.173.21:24:05.88#ibcon#first serial, iclass 18, count 0 2006.173.21:24:05.88#ibcon#enter sib2, iclass 18, count 0 2006.173.21:24:05.88#ibcon#flushed, iclass 18, count 0 2006.173.21:24:05.88#ibcon#about to write, iclass 18, count 0 2006.173.21:24:05.88#ibcon#wrote, iclass 18, count 0 2006.173.21:24:05.88#ibcon#about to read 3, iclass 18, count 0 2006.173.21:24:05.90#ibcon#read 3, iclass 18, count 0 2006.173.21:24:05.90#ibcon#about to read 4, iclass 18, count 0 2006.173.21:24:05.90#ibcon#read 4, iclass 18, count 0 2006.173.21:24:05.90#ibcon#about to read 5, iclass 18, count 0 2006.173.21:24:05.90#ibcon#read 5, iclass 18, count 0 2006.173.21:24:05.90#ibcon#about to read 6, iclass 18, count 0 2006.173.21:24:05.90#ibcon#read 6, iclass 18, count 0 2006.173.21:24:05.90#ibcon#end of sib2, iclass 18, count 0 2006.173.21:24:05.90#ibcon#*mode == 0, iclass 18, count 0 2006.173.21:24:05.90#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.21:24:05.90#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.21:24:05.90#ibcon#*before write, iclass 18, count 0 2006.173.21:24:05.90#ibcon#enter sib2, iclass 18, count 0 2006.173.21:24:05.90#ibcon#flushed, iclass 18, count 0 2006.173.21:24:05.90#ibcon#about to write, iclass 18, count 0 2006.173.21:24:05.90#ibcon#wrote, iclass 18, count 0 2006.173.21:24:05.90#ibcon#about to read 3, iclass 18, count 0 2006.173.21:24:05.94#ibcon#read 3, iclass 18, count 0 2006.173.21:24:05.94#ibcon#about to read 4, iclass 18, count 0 2006.173.21:24:05.94#ibcon#read 4, iclass 18, count 0 2006.173.21:24:05.94#ibcon#about to read 5, iclass 18, count 0 2006.173.21:24:05.94#ibcon#read 5, iclass 18, count 0 2006.173.21:24:05.94#ibcon#about to read 6, iclass 18, count 0 2006.173.21:24:05.94#ibcon#read 6, iclass 18, count 0 2006.173.21:24:05.94#ibcon#end of sib2, iclass 18, count 0 2006.173.21:24:05.94#ibcon#*after write, iclass 18, count 0 2006.173.21:24:05.94#ibcon#*before return 0, iclass 18, count 0 2006.173.21:24:05.94#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.21:24:05.94#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.21:24:05.94#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.21:24:05.94#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.21:24:05.94$vck44/vb=1,4 2006.173.21:24:05.94#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.21:24:05.94#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.21:24:05.94#ibcon#ireg 11 cls_cnt 2 2006.173.21:24:05.94#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.21:24:05.94#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.21:24:05.94#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.21:24:05.94#ibcon#enter wrdev, iclass 20, count 2 2006.173.21:24:05.94#ibcon#first serial, iclass 20, count 2 2006.173.21:24:05.94#ibcon#enter sib2, iclass 20, count 2 2006.173.21:24:05.94#ibcon#flushed, iclass 20, count 2 2006.173.21:24:05.94#ibcon#about to write, iclass 20, count 2 2006.173.21:24:05.94#ibcon#wrote, iclass 20, count 2 2006.173.21:24:05.94#ibcon#about to read 3, iclass 20, count 2 2006.173.21:24:05.96#ibcon#read 3, iclass 20, count 2 2006.173.21:24:05.96#ibcon#about to read 4, iclass 20, count 2 2006.173.21:24:05.96#ibcon#read 4, iclass 20, count 2 2006.173.21:24:05.96#ibcon#about to read 5, iclass 20, count 2 2006.173.21:24:05.96#ibcon#read 5, iclass 20, count 2 2006.173.21:24:05.96#ibcon#about to read 6, iclass 20, count 2 2006.173.21:24:05.96#ibcon#read 6, iclass 20, count 2 2006.173.21:24:05.96#ibcon#end of sib2, iclass 20, count 2 2006.173.21:24:05.96#ibcon#*mode == 0, iclass 20, count 2 2006.173.21:24:05.96#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.21:24:05.96#ibcon#[27=AT01-04\r\n] 2006.173.21:24:05.96#ibcon#*before write, iclass 20, count 2 2006.173.21:24:05.96#ibcon#enter sib2, iclass 20, count 2 2006.173.21:24:05.96#ibcon#flushed, iclass 20, count 2 2006.173.21:24:05.96#ibcon#about to write, iclass 20, count 2 2006.173.21:24:05.96#ibcon#wrote, iclass 20, count 2 2006.173.21:24:05.96#ibcon#about to read 3, iclass 20, count 2 2006.173.21:24:05.99#ibcon#read 3, iclass 20, count 2 2006.173.21:24:05.99#ibcon#about to read 4, iclass 20, count 2 2006.173.21:24:05.99#ibcon#read 4, iclass 20, count 2 2006.173.21:24:05.99#ibcon#about to read 5, iclass 20, count 2 2006.173.21:24:05.99#ibcon#read 5, iclass 20, count 2 2006.173.21:24:05.99#ibcon#about to read 6, iclass 20, count 2 2006.173.21:24:05.99#ibcon#read 6, iclass 20, count 2 2006.173.21:24:05.99#ibcon#end of sib2, iclass 20, count 2 2006.173.21:24:05.99#ibcon#*after write, iclass 20, count 2 2006.173.21:24:05.99#ibcon#*before return 0, iclass 20, count 2 2006.173.21:24:05.99#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.21:24:05.99#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.21:24:05.99#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.21:24:05.99#ibcon#ireg 7 cls_cnt 0 2006.173.21:24:05.99#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.21:24:06.11#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.21:24:06.11#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.21:24:06.11#ibcon#enter wrdev, iclass 20, count 0 2006.173.21:24:06.11#ibcon#first serial, iclass 20, count 0 2006.173.21:24:06.11#ibcon#enter sib2, iclass 20, count 0 2006.173.21:24:06.11#ibcon#flushed, iclass 20, count 0 2006.173.21:24:06.11#ibcon#about to write, iclass 20, count 0 2006.173.21:24:06.11#ibcon#wrote, iclass 20, count 0 2006.173.21:24:06.11#ibcon#about to read 3, iclass 20, count 0 2006.173.21:24:06.13#ibcon#read 3, iclass 20, count 0 2006.173.21:24:06.13#ibcon#about to read 4, iclass 20, count 0 2006.173.21:24:06.13#ibcon#read 4, iclass 20, count 0 2006.173.21:24:06.13#ibcon#about to read 5, iclass 20, count 0 2006.173.21:24:06.13#ibcon#read 5, iclass 20, count 0 2006.173.21:24:06.13#ibcon#about to read 6, iclass 20, count 0 2006.173.21:24:06.13#ibcon#read 6, iclass 20, count 0 2006.173.21:24:06.13#ibcon#end of sib2, iclass 20, count 0 2006.173.21:24:06.13#ibcon#*mode == 0, iclass 20, count 0 2006.173.21:24:06.13#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.21:24:06.13#ibcon#[27=USB\r\n] 2006.173.21:24:06.13#ibcon#*before write, iclass 20, count 0 2006.173.21:24:06.13#ibcon#enter sib2, iclass 20, count 0 2006.173.21:24:06.13#ibcon#flushed, iclass 20, count 0 2006.173.21:24:06.13#ibcon#about to write, iclass 20, count 0 2006.173.21:24:06.13#ibcon#wrote, iclass 20, count 0 2006.173.21:24:06.13#ibcon#about to read 3, iclass 20, count 0 2006.173.21:24:06.16#ibcon#read 3, iclass 20, count 0 2006.173.21:24:06.16#ibcon#about to read 4, iclass 20, count 0 2006.173.21:24:06.16#ibcon#read 4, iclass 20, count 0 2006.173.21:24:06.16#ibcon#about to read 5, iclass 20, count 0 2006.173.21:24:06.16#ibcon#read 5, iclass 20, count 0 2006.173.21:24:06.16#ibcon#about to read 6, iclass 20, count 0 2006.173.21:24:06.16#ibcon#read 6, iclass 20, count 0 2006.173.21:24:06.16#ibcon#end of sib2, iclass 20, count 0 2006.173.21:24:06.16#ibcon#*after write, iclass 20, count 0 2006.173.21:24:06.16#ibcon#*before return 0, iclass 20, count 0 2006.173.21:24:06.16#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.21:24:06.16#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.21:24:06.16#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.21:24:06.16#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.21:24:06.16$vck44/vblo=2,634.99 2006.173.21:24:06.16#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.21:24:06.16#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.21:24:06.16#ibcon#ireg 17 cls_cnt 0 2006.173.21:24:06.16#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.21:24:06.16#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.21:24:06.16#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.21:24:06.16#ibcon#enter wrdev, iclass 22, count 0 2006.173.21:24:06.16#ibcon#first serial, iclass 22, count 0 2006.173.21:24:06.16#ibcon#enter sib2, iclass 22, count 0 2006.173.21:24:06.16#ibcon#flushed, iclass 22, count 0 2006.173.21:24:06.16#ibcon#about to write, iclass 22, count 0 2006.173.21:24:06.16#ibcon#wrote, iclass 22, count 0 2006.173.21:24:06.16#ibcon#about to read 3, iclass 22, count 0 2006.173.21:24:06.18#ibcon#read 3, iclass 22, count 0 2006.173.21:24:06.18#ibcon#about to read 4, iclass 22, count 0 2006.173.21:24:06.18#ibcon#read 4, iclass 22, count 0 2006.173.21:24:06.18#ibcon#about to read 5, iclass 22, count 0 2006.173.21:24:06.18#ibcon#read 5, iclass 22, count 0 2006.173.21:24:06.18#ibcon#about to read 6, iclass 22, count 0 2006.173.21:24:06.18#ibcon#read 6, iclass 22, count 0 2006.173.21:24:06.18#ibcon#end of sib2, iclass 22, count 0 2006.173.21:24:06.18#ibcon#*mode == 0, iclass 22, count 0 2006.173.21:24:06.18#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.21:24:06.18#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.21:24:06.18#ibcon#*before write, iclass 22, count 0 2006.173.21:24:06.18#ibcon#enter sib2, iclass 22, count 0 2006.173.21:24:06.18#ibcon#flushed, iclass 22, count 0 2006.173.21:24:06.18#ibcon#about to write, iclass 22, count 0 2006.173.21:24:06.18#ibcon#wrote, iclass 22, count 0 2006.173.21:24:06.18#ibcon#about to read 3, iclass 22, count 0 2006.173.21:24:06.22#ibcon#read 3, iclass 22, count 0 2006.173.21:24:06.22#ibcon#about to read 4, iclass 22, count 0 2006.173.21:24:06.22#ibcon#read 4, iclass 22, count 0 2006.173.21:24:06.22#ibcon#about to read 5, iclass 22, count 0 2006.173.21:24:06.22#ibcon#read 5, iclass 22, count 0 2006.173.21:24:06.22#ibcon#about to read 6, iclass 22, count 0 2006.173.21:24:06.22#ibcon#read 6, iclass 22, count 0 2006.173.21:24:06.22#ibcon#end of sib2, iclass 22, count 0 2006.173.21:24:06.22#ibcon#*after write, iclass 22, count 0 2006.173.21:24:06.22#ibcon#*before return 0, iclass 22, count 0 2006.173.21:24:06.22#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.21:24:06.22#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.21:24:06.22#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.21:24:06.22#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.21:24:06.22$vck44/vb=2,4 2006.173.21:24:06.22#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.21:24:06.22#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.21:24:06.22#ibcon#ireg 11 cls_cnt 2 2006.173.21:24:06.22#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.21:24:06.28#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.21:24:06.28#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.21:24:06.28#ibcon#enter wrdev, iclass 24, count 2 2006.173.21:24:06.28#ibcon#first serial, iclass 24, count 2 2006.173.21:24:06.28#ibcon#enter sib2, iclass 24, count 2 2006.173.21:24:06.28#ibcon#flushed, iclass 24, count 2 2006.173.21:24:06.28#ibcon#about to write, iclass 24, count 2 2006.173.21:24:06.28#ibcon#wrote, iclass 24, count 2 2006.173.21:24:06.28#ibcon#about to read 3, iclass 24, count 2 2006.173.21:24:06.30#ibcon#read 3, iclass 24, count 2 2006.173.21:24:06.30#ibcon#about to read 4, iclass 24, count 2 2006.173.21:24:06.30#ibcon#read 4, iclass 24, count 2 2006.173.21:24:06.30#ibcon#about to read 5, iclass 24, count 2 2006.173.21:24:06.30#ibcon#read 5, iclass 24, count 2 2006.173.21:24:06.30#ibcon#about to read 6, iclass 24, count 2 2006.173.21:24:06.30#ibcon#read 6, iclass 24, count 2 2006.173.21:24:06.30#ibcon#end of sib2, iclass 24, count 2 2006.173.21:24:06.30#ibcon#*mode == 0, iclass 24, count 2 2006.173.21:24:06.30#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.21:24:06.30#ibcon#[27=AT02-04\r\n] 2006.173.21:24:06.30#ibcon#*before write, iclass 24, count 2 2006.173.21:24:06.30#ibcon#enter sib2, iclass 24, count 2 2006.173.21:24:06.30#ibcon#flushed, iclass 24, count 2 2006.173.21:24:06.30#ibcon#about to write, iclass 24, count 2 2006.173.21:24:06.30#ibcon#wrote, iclass 24, count 2 2006.173.21:24:06.30#ibcon#about to read 3, iclass 24, count 2 2006.173.21:24:06.33#ibcon#read 3, iclass 24, count 2 2006.173.21:24:06.33#ibcon#about to read 4, iclass 24, count 2 2006.173.21:24:06.33#ibcon#read 4, iclass 24, count 2 2006.173.21:24:06.33#ibcon#about to read 5, iclass 24, count 2 2006.173.21:24:06.33#ibcon#read 5, iclass 24, count 2 2006.173.21:24:06.33#ibcon#about to read 6, iclass 24, count 2 2006.173.21:24:06.33#ibcon#read 6, iclass 24, count 2 2006.173.21:24:06.33#ibcon#end of sib2, iclass 24, count 2 2006.173.21:24:06.33#ibcon#*after write, iclass 24, count 2 2006.173.21:24:06.33#ibcon#*before return 0, iclass 24, count 2 2006.173.21:24:06.33#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.21:24:06.33#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.21:24:06.33#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.21:24:06.33#ibcon#ireg 7 cls_cnt 0 2006.173.21:24:06.33#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.21:24:06.45#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.21:24:06.45#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.21:24:06.45#ibcon#enter wrdev, iclass 24, count 0 2006.173.21:24:06.45#ibcon#first serial, iclass 24, count 0 2006.173.21:24:06.45#ibcon#enter sib2, iclass 24, count 0 2006.173.21:24:06.45#ibcon#flushed, iclass 24, count 0 2006.173.21:24:06.45#ibcon#about to write, iclass 24, count 0 2006.173.21:24:06.45#ibcon#wrote, iclass 24, count 0 2006.173.21:24:06.45#ibcon#about to read 3, iclass 24, count 0 2006.173.21:24:06.47#ibcon#read 3, iclass 24, count 0 2006.173.21:24:06.47#ibcon#about to read 4, iclass 24, count 0 2006.173.21:24:06.47#ibcon#read 4, iclass 24, count 0 2006.173.21:24:06.47#ibcon#about to read 5, iclass 24, count 0 2006.173.21:24:06.47#ibcon#read 5, iclass 24, count 0 2006.173.21:24:06.47#ibcon#about to read 6, iclass 24, count 0 2006.173.21:24:06.47#ibcon#read 6, iclass 24, count 0 2006.173.21:24:06.47#ibcon#end of sib2, iclass 24, count 0 2006.173.21:24:06.47#ibcon#*mode == 0, iclass 24, count 0 2006.173.21:24:06.47#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.21:24:06.47#ibcon#[27=USB\r\n] 2006.173.21:24:06.47#ibcon#*before write, iclass 24, count 0 2006.173.21:24:06.47#ibcon#enter sib2, iclass 24, count 0 2006.173.21:24:06.47#ibcon#flushed, iclass 24, count 0 2006.173.21:24:06.47#ibcon#about to write, iclass 24, count 0 2006.173.21:24:06.47#ibcon#wrote, iclass 24, count 0 2006.173.21:24:06.47#ibcon#about to read 3, iclass 24, count 0 2006.173.21:24:06.50#ibcon#read 3, iclass 24, count 0 2006.173.21:24:06.50#ibcon#about to read 4, iclass 24, count 0 2006.173.21:24:06.50#ibcon#read 4, iclass 24, count 0 2006.173.21:24:06.50#ibcon#about to read 5, iclass 24, count 0 2006.173.21:24:06.50#ibcon#read 5, iclass 24, count 0 2006.173.21:24:06.50#ibcon#about to read 6, iclass 24, count 0 2006.173.21:24:06.50#ibcon#read 6, iclass 24, count 0 2006.173.21:24:06.50#ibcon#end of sib2, iclass 24, count 0 2006.173.21:24:06.50#ibcon#*after write, iclass 24, count 0 2006.173.21:24:06.50#ibcon#*before return 0, iclass 24, count 0 2006.173.21:24:06.50#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.21:24:06.50#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.21:24:06.50#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.21:24:06.50#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.21:24:06.50$vck44/vblo=3,649.99 2006.173.21:24:06.50#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.21:24:06.50#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.21:24:06.50#ibcon#ireg 17 cls_cnt 0 2006.173.21:24:06.50#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.21:24:06.50#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.21:24:06.50#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.21:24:06.50#ibcon#enter wrdev, iclass 26, count 0 2006.173.21:24:06.50#ibcon#first serial, iclass 26, count 0 2006.173.21:24:06.50#ibcon#enter sib2, iclass 26, count 0 2006.173.21:24:06.50#ibcon#flushed, iclass 26, count 0 2006.173.21:24:06.50#ibcon#about to write, iclass 26, count 0 2006.173.21:24:06.50#ibcon#wrote, iclass 26, count 0 2006.173.21:24:06.50#ibcon#about to read 3, iclass 26, count 0 2006.173.21:24:06.52#ibcon#read 3, iclass 26, count 0 2006.173.21:24:06.52#ibcon#about to read 4, iclass 26, count 0 2006.173.21:24:06.52#ibcon#read 4, iclass 26, count 0 2006.173.21:24:06.52#ibcon#about to read 5, iclass 26, count 0 2006.173.21:24:06.52#ibcon#read 5, iclass 26, count 0 2006.173.21:24:06.52#ibcon#about to read 6, iclass 26, count 0 2006.173.21:24:06.52#ibcon#read 6, iclass 26, count 0 2006.173.21:24:06.52#ibcon#end of sib2, iclass 26, count 0 2006.173.21:24:06.52#ibcon#*mode == 0, iclass 26, count 0 2006.173.21:24:06.52#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.21:24:06.52#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.21:24:06.52#ibcon#*before write, iclass 26, count 0 2006.173.21:24:06.52#ibcon#enter sib2, iclass 26, count 0 2006.173.21:24:06.52#ibcon#flushed, iclass 26, count 0 2006.173.21:24:06.52#ibcon#about to write, iclass 26, count 0 2006.173.21:24:06.52#ibcon#wrote, iclass 26, count 0 2006.173.21:24:06.52#ibcon#about to read 3, iclass 26, count 0 2006.173.21:24:06.56#ibcon#read 3, iclass 26, count 0 2006.173.21:24:06.56#ibcon#about to read 4, iclass 26, count 0 2006.173.21:24:06.56#ibcon#read 4, iclass 26, count 0 2006.173.21:24:06.56#ibcon#about to read 5, iclass 26, count 0 2006.173.21:24:06.56#ibcon#read 5, iclass 26, count 0 2006.173.21:24:06.56#ibcon#about to read 6, iclass 26, count 0 2006.173.21:24:06.56#ibcon#read 6, iclass 26, count 0 2006.173.21:24:06.56#ibcon#end of sib2, iclass 26, count 0 2006.173.21:24:06.56#ibcon#*after write, iclass 26, count 0 2006.173.21:24:06.56#ibcon#*before return 0, iclass 26, count 0 2006.173.21:24:06.56#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.21:24:06.56#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.21:24:06.56#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.21:24:06.56#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.21:24:06.56$vck44/vb=3,4 2006.173.21:24:06.56#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.21:24:06.56#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.21:24:06.56#ibcon#ireg 11 cls_cnt 2 2006.173.21:24:06.56#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.21:24:06.62#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.21:24:06.62#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.21:24:06.62#ibcon#enter wrdev, iclass 28, count 2 2006.173.21:24:06.62#ibcon#first serial, iclass 28, count 2 2006.173.21:24:06.62#ibcon#enter sib2, iclass 28, count 2 2006.173.21:24:06.62#ibcon#flushed, iclass 28, count 2 2006.173.21:24:06.62#ibcon#about to write, iclass 28, count 2 2006.173.21:24:06.62#ibcon#wrote, iclass 28, count 2 2006.173.21:24:06.62#ibcon#about to read 3, iclass 28, count 2 2006.173.21:24:06.64#ibcon#read 3, iclass 28, count 2 2006.173.21:24:06.64#ibcon#about to read 4, iclass 28, count 2 2006.173.21:24:06.64#ibcon#read 4, iclass 28, count 2 2006.173.21:24:06.64#ibcon#about to read 5, iclass 28, count 2 2006.173.21:24:06.64#ibcon#read 5, iclass 28, count 2 2006.173.21:24:06.64#ibcon#about to read 6, iclass 28, count 2 2006.173.21:24:06.64#ibcon#read 6, iclass 28, count 2 2006.173.21:24:06.64#ibcon#end of sib2, iclass 28, count 2 2006.173.21:24:06.64#ibcon#*mode == 0, iclass 28, count 2 2006.173.21:24:06.64#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.21:24:06.64#ibcon#[27=AT03-04\r\n] 2006.173.21:24:06.64#ibcon#*before write, iclass 28, count 2 2006.173.21:24:06.64#ibcon#enter sib2, iclass 28, count 2 2006.173.21:24:06.64#ibcon#flushed, iclass 28, count 2 2006.173.21:24:06.64#ibcon#about to write, iclass 28, count 2 2006.173.21:24:06.64#ibcon#wrote, iclass 28, count 2 2006.173.21:24:06.64#ibcon#about to read 3, iclass 28, count 2 2006.173.21:24:06.67#ibcon#read 3, iclass 28, count 2 2006.173.21:24:06.67#ibcon#about to read 4, iclass 28, count 2 2006.173.21:24:06.67#ibcon#read 4, iclass 28, count 2 2006.173.21:24:06.67#ibcon#about to read 5, iclass 28, count 2 2006.173.21:24:06.67#ibcon#read 5, iclass 28, count 2 2006.173.21:24:06.67#ibcon#about to read 6, iclass 28, count 2 2006.173.21:24:06.67#ibcon#read 6, iclass 28, count 2 2006.173.21:24:06.67#ibcon#end of sib2, iclass 28, count 2 2006.173.21:24:06.67#ibcon#*after write, iclass 28, count 2 2006.173.21:24:06.67#ibcon#*before return 0, iclass 28, count 2 2006.173.21:24:06.67#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.21:24:06.67#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.21:24:06.67#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.21:24:06.67#ibcon#ireg 7 cls_cnt 0 2006.173.21:24:06.67#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.21:24:06.79#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.21:24:06.79#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.21:24:06.79#ibcon#enter wrdev, iclass 28, count 0 2006.173.21:24:06.79#ibcon#first serial, iclass 28, count 0 2006.173.21:24:06.79#ibcon#enter sib2, iclass 28, count 0 2006.173.21:24:06.79#ibcon#flushed, iclass 28, count 0 2006.173.21:24:06.79#ibcon#about to write, iclass 28, count 0 2006.173.21:24:06.79#ibcon#wrote, iclass 28, count 0 2006.173.21:24:06.79#ibcon#about to read 3, iclass 28, count 0 2006.173.21:24:06.81#ibcon#read 3, iclass 28, count 0 2006.173.21:24:06.81#ibcon#about to read 4, iclass 28, count 0 2006.173.21:24:06.81#ibcon#read 4, iclass 28, count 0 2006.173.21:24:06.81#ibcon#about to read 5, iclass 28, count 0 2006.173.21:24:06.81#ibcon#read 5, iclass 28, count 0 2006.173.21:24:06.81#ibcon#about to read 6, iclass 28, count 0 2006.173.21:24:06.81#ibcon#read 6, iclass 28, count 0 2006.173.21:24:06.81#ibcon#end of sib2, iclass 28, count 0 2006.173.21:24:06.81#ibcon#*mode == 0, iclass 28, count 0 2006.173.21:24:06.81#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.21:24:06.81#ibcon#[27=USB\r\n] 2006.173.21:24:06.81#ibcon#*before write, iclass 28, count 0 2006.173.21:24:06.81#ibcon#enter sib2, iclass 28, count 0 2006.173.21:24:06.81#ibcon#flushed, iclass 28, count 0 2006.173.21:24:06.81#ibcon#about to write, iclass 28, count 0 2006.173.21:24:06.81#ibcon#wrote, iclass 28, count 0 2006.173.21:24:06.81#ibcon#about to read 3, iclass 28, count 0 2006.173.21:24:06.84#ibcon#read 3, iclass 28, count 0 2006.173.21:24:06.84#ibcon#about to read 4, iclass 28, count 0 2006.173.21:24:06.84#ibcon#read 4, iclass 28, count 0 2006.173.21:24:06.84#ibcon#about to read 5, iclass 28, count 0 2006.173.21:24:06.84#ibcon#read 5, iclass 28, count 0 2006.173.21:24:06.84#ibcon#about to read 6, iclass 28, count 0 2006.173.21:24:06.84#ibcon#read 6, iclass 28, count 0 2006.173.21:24:06.84#ibcon#end of sib2, iclass 28, count 0 2006.173.21:24:06.84#ibcon#*after write, iclass 28, count 0 2006.173.21:24:06.84#ibcon#*before return 0, iclass 28, count 0 2006.173.21:24:06.84#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.21:24:06.84#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.21:24:06.84#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.21:24:06.84#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.21:24:06.84$vck44/vblo=4,679.99 2006.173.21:24:06.84#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.21:24:06.84#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.21:24:06.84#ibcon#ireg 17 cls_cnt 0 2006.173.21:24:06.84#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.21:24:06.84#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.21:24:06.84#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.21:24:06.84#ibcon#enter wrdev, iclass 30, count 0 2006.173.21:24:06.84#ibcon#first serial, iclass 30, count 0 2006.173.21:24:06.84#ibcon#enter sib2, iclass 30, count 0 2006.173.21:24:06.84#ibcon#flushed, iclass 30, count 0 2006.173.21:24:06.84#ibcon#about to write, iclass 30, count 0 2006.173.21:24:06.84#ibcon#wrote, iclass 30, count 0 2006.173.21:24:06.84#ibcon#about to read 3, iclass 30, count 0 2006.173.21:24:06.86#ibcon#read 3, iclass 30, count 0 2006.173.21:24:06.86#ibcon#about to read 4, iclass 30, count 0 2006.173.21:24:06.86#ibcon#read 4, iclass 30, count 0 2006.173.21:24:06.86#ibcon#about to read 5, iclass 30, count 0 2006.173.21:24:06.86#ibcon#read 5, iclass 30, count 0 2006.173.21:24:06.86#ibcon#about to read 6, iclass 30, count 0 2006.173.21:24:06.86#ibcon#read 6, iclass 30, count 0 2006.173.21:24:06.86#ibcon#end of sib2, iclass 30, count 0 2006.173.21:24:06.86#ibcon#*mode == 0, iclass 30, count 0 2006.173.21:24:06.86#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.21:24:06.86#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.21:24:06.86#ibcon#*before write, iclass 30, count 0 2006.173.21:24:06.86#ibcon#enter sib2, iclass 30, count 0 2006.173.21:24:06.86#ibcon#flushed, iclass 30, count 0 2006.173.21:24:06.86#ibcon#about to write, iclass 30, count 0 2006.173.21:24:06.86#ibcon#wrote, iclass 30, count 0 2006.173.21:24:06.86#ibcon#about to read 3, iclass 30, count 0 2006.173.21:24:06.90#ibcon#read 3, iclass 30, count 0 2006.173.21:24:06.90#ibcon#about to read 4, iclass 30, count 0 2006.173.21:24:06.90#ibcon#read 4, iclass 30, count 0 2006.173.21:24:06.90#ibcon#about to read 5, iclass 30, count 0 2006.173.21:24:06.90#ibcon#read 5, iclass 30, count 0 2006.173.21:24:06.90#ibcon#about to read 6, iclass 30, count 0 2006.173.21:24:06.90#ibcon#read 6, iclass 30, count 0 2006.173.21:24:06.90#ibcon#end of sib2, iclass 30, count 0 2006.173.21:24:06.90#ibcon#*after write, iclass 30, count 0 2006.173.21:24:06.90#ibcon#*before return 0, iclass 30, count 0 2006.173.21:24:06.90#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.21:24:06.90#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.21:24:06.90#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.21:24:06.90#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.21:24:06.90$vck44/vb=4,4 2006.173.21:24:06.90#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.173.21:24:06.90#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.173.21:24:06.90#ibcon#ireg 11 cls_cnt 2 2006.173.21:24:06.90#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.21:24:06.96#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.21:24:06.96#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.21:24:06.96#ibcon#enter wrdev, iclass 32, count 2 2006.173.21:24:06.96#ibcon#first serial, iclass 32, count 2 2006.173.21:24:06.96#ibcon#enter sib2, iclass 32, count 2 2006.173.21:24:06.96#ibcon#flushed, iclass 32, count 2 2006.173.21:24:06.96#ibcon#about to write, iclass 32, count 2 2006.173.21:24:06.96#ibcon#wrote, iclass 32, count 2 2006.173.21:24:06.96#ibcon#about to read 3, iclass 32, count 2 2006.173.21:24:06.98#ibcon#read 3, iclass 32, count 2 2006.173.21:24:06.98#ibcon#about to read 4, iclass 32, count 2 2006.173.21:24:06.98#ibcon#read 4, iclass 32, count 2 2006.173.21:24:06.98#ibcon#about to read 5, iclass 32, count 2 2006.173.21:24:06.98#ibcon#read 5, iclass 32, count 2 2006.173.21:24:06.98#ibcon#about to read 6, iclass 32, count 2 2006.173.21:24:06.98#ibcon#read 6, iclass 32, count 2 2006.173.21:24:06.98#ibcon#end of sib2, iclass 32, count 2 2006.173.21:24:06.98#ibcon#*mode == 0, iclass 32, count 2 2006.173.21:24:06.98#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.173.21:24:06.98#ibcon#[27=AT04-04\r\n] 2006.173.21:24:06.98#ibcon#*before write, iclass 32, count 2 2006.173.21:24:06.98#ibcon#enter sib2, iclass 32, count 2 2006.173.21:24:06.98#ibcon#flushed, iclass 32, count 2 2006.173.21:24:06.98#ibcon#about to write, iclass 32, count 2 2006.173.21:24:06.98#ibcon#wrote, iclass 32, count 2 2006.173.21:24:06.98#ibcon#about to read 3, iclass 32, count 2 2006.173.21:24:07.01#ibcon#read 3, iclass 32, count 2 2006.173.21:24:07.01#ibcon#about to read 4, iclass 32, count 2 2006.173.21:24:07.01#ibcon#read 4, iclass 32, count 2 2006.173.21:24:07.01#ibcon#about to read 5, iclass 32, count 2 2006.173.21:24:07.01#ibcon#read 5, iclass 32, count 2 2006.173.21:24:07.01#ibcon#about to read 6, iclass 32, count 2 2006.173.21:24:07.01#ibcon#read 6, iclass 32, count 2 2006.173.21:24:07.01#ibcon#end of sib2, iclass 32, count 2 2006.173.21:24:07.01#ibcon#*after write, iclass 32, count 2 2006.173.21:24:07.01#ibcon#*before return 0, iclass 32, count 2 2006.173.21:24:07.01#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.21:24:07.01#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.173.21:24:07.01#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.173.21:24:07.01#ibcon#ireg 7 cls_cnt 0 2006.173.21:24:07.01#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.21:24:07.13#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.21:24:07.13#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.21:24:07.13#ibcon#enter wrdev, iclass 32, count 0 2006.173.21:24:07.13#ibcon#first serial, iclass 32, count 0 2006.173.21:24:07.13#ibcon#enter sib2, iclass 32, count 0 2006.173.21:24:07.13#ibcon#flushed, iclass 32, count 0 2006.173.21:24:07.13#ibcon#about to write, iclass 32, count 0 2006.173.21:24:07.13#ibcon#wrote, iclass 32, count 0 2006.173.21:24:07.13#ibcon#about to read 3, iclass 32, count 0 2006.173.21:24:07.15#ibcon#read 3, iclass 32, count 0 2006.173.21:24:07.15#ibcon#about to read 4, iclass 32, count 0 2006.173.21:24:07.15#ibcon#read 4, iclass 32, count 0 2006.173.21:24:07.15#ibcon#about to read 5, iclass 32, count 0 2006.173.21:24:07.15#ibcon#read 5, iclass 32, count 0 2006.173.21:24:07.15#ibcon#about to read 6, iclass 32, count 0 2006.173.21:24:07.15#ibcon#read 6, iclass 32, count 0 2006.173.21:24:07.15#ibcon#end of sib2, iclass 32, count 0 2006.173.21:24:07.15#ibcon#*mode == 0, iclass 32, count 0 2006.173.21:24:07.15#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.21:24:07.15#ibcon#[27=USB\r\n] 2006.173.21:24:07.15#ibcon#*before write, iclass 32, count 0 2006.173.21:24:07.15#ibcon#enter sib2, iclass 32, count 0 2006.173.21:24:07.15#ibcon#flushed, iclass 32, count 0 2006.173.21:24:07.15#ibcon#about to write, iclass 32, count 0 2006.173.21:24:07.15#ibcon#wrote, iclass 32, count 0 2006.173.21:24:07.15#ibcon#about to read 3, iclass 32, count 0 2006.173.21:24:07.18#ibcon#read 3, iclass 32, count 0 2006.173.21:24:07.18#ibcon#about to read 4, iclass 32, count 0 2006.173.21:24:07.18#ibcon#read 4, iclass 32, count 0 2006.173.21:24:07.18#ibcon#about to read 5, iclass 32, count 0 2006.173.21:24:07.18#ibcon#read 5, iclass 32, count 0 2006.173.21:24:07.18#ibcon#about to read 6, iclass 32, count 0 2006.173.21:24:07.18#ibcon#read 6, iclass 32, count 0 2006.173.21:24:07.18#ibcon#end of sib2, iclass 32, count 0 2006.173.21:24:07.18#ibcon#*after write, iclass 32, count 0 2006.173.21:24:07.18#ibcon#*before return 0, iclass 32, count 0 2006.173.21:24:07.18#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.21:24:07.18#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.173.21:24:07.18#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.21:24:07.18#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.21:24:07.18$vck44/vblo=5,709.99 2006.173.21:24:07.18#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.21:24:07.18#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.21:24:07.18#ibcon#ireg 17 cls_cnt 0 2006.173.21:24:07.18#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.21:24:07.18#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.21:24:07.18#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.21:24:07.18#ibcon#enter wrdev, iclass 34, count 0 2006.173.21:24:07.18#ibcon#first serial, iclass 34, count 0 2006.173.21:24:07.18#ibcon#enter sib2, iclass 34, count 0 2006.173.21:24:07.18#ibcon#flushed, iclass 34, count 0 2006.173.21:24:07.18#ibcon#about to write, iclass 34, count 0 2006.173.21:24:07.18#ibcon#wrote, iclass 34, count 0 2006.173.21:24:07.18#ibcon#about to read 3, iclass 34, count 0 2006.173.21:24:07.20#ibcon#read 3, iclass 34, count 0 2006.173.21:24:07.20#ibcon#about to read 4, iclass 34, count 0 2006.173.21:24:07.20#ibcon#read 4, iclass 34, count 0 2006.173.21:24:07.20#ibcon#about to read 5, iclass 34, count 0 2006.173.21:24:07.20#ibcon#read 5, iclass 34, count 0 2006.173.21:24:07.20#ibcon#about to read 6, iclass 34, count 0 2006.173.21:24:07.20#ibcon#read 6, iclass 34, count 0 2006.173.21:24:07.20#ibcon#end of sib2, iclass 34, count 0 2006.173.21:24:07.20#ibcon#*mode == 0, iclass 34, count 0 2006.173.21:24:07.20#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.21:24:07.20#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.21:24:07.20#ibcon#*before write, iclass 34, count 0 2006.173.21:24:07.20#ibcon#enter sib2, iclass 34, count 0 2006.173.21:24:07.20#ibcon#flushed, iclass 34, count 0 2006.173.21:24:07.20#ibcon#about to write, iclass 34, count 0 2006.173.21:24:07.20#ibcon#wrote, iclass 34, count 0 2006.173.21:24:07.20#ibcon#about to read 3, iclass 34, count 0 2006.173.21:24:07.24#ibcon#read 3, iclass 34, count 0 2006.173.21:24:07.24#ibcon#about to read 4, iclass 34, count 0 2006.173.21:24:07.24#ibcon#read 4, iclass 34, count 0 2006.173.21:24:07.24#ibcon#about to read 5, iclass 34, count 0 2006.173.21:24:07.24#ibcon#read 5, iclass 34, count 0 2006.173.21:24:07.24#ibcon#about to read 6, iclass 34, count 0 2006.173.21:24:07.24#ibcon#read 6, iclass 34, count 0 2006.173.21:24:07.24#ibcon#end of sib2, iclass 34, count 0 2006.173.21:24:07.24#ibcon#*after write, iclass 34, count 0 2006.173.21:24:07.24#ibcon#*before return 0, iclass 34, count 0 2006.173.21:24:07.24#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.21:24:07.24#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.21:24:07.24#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.21:24:07.24#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.21:24:07.24$vck44/vb=5,4 2006.173.21:24:07.24#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.21:24:07.24#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.21:24:07.24#ibcon#ireg 11 cls_cnt 2 2006.173.21:24:07.24#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.21:24:07.30#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.21:24:07.30#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.21:24:07.30#ibcon#enter wrdev, iclass 36, count 2 2006.173.21:24:07.30#ibcon#first serial, iclass 36, count 2 2006.173.21:24:07.30#ibcon#enter sib2, iclass 36, count 2 2006.173.21:24:07.30#ibcon#flushed, iclass 36, count 2 2006.173.21:24:07.30#ibcon#about to write, iclass 36, count 2 2006.173.21:24:07.30#ibcon#wrote, iclass 36, count 2 2006.173.21:24:07.30#ibcon#about to read 3, iclass 36, count 2 2006.173.21:24:07.32#ibcon#read 3, iclass 36, count 2 2006.173.21:24:07.32#ibcon#about to read 4, iclass 36, count 2 2006.173.21:24:07.32#ibcon#read 4, iclass 36, count 2 2006.173.21:24:07.32#ibcon#about to read 5, iclass 36, count 2 2006.173.21:24:07.32#ibcon#read 5, iclass 36, count 2 2006.173.21:24:07.32#ibcon#about to read 6, iclass 36, count 2 2006.173.21:24:07.32#ibcon#read 6, iclass 36, count 2 2006.173.21:24:07.32#ibcon#end of sib2, iclass 36, count 2 2006.173.21:24:07.32#ibcon#*mode == 0, iclass 36, count 2 2006.173.21:24:07.32#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.21:24:07.32#ibcon#[27=AT05-04\r\n] 2006.173.21:24:07.32#ibcon#*before write, iclass 36, count 2 2006.173.21:24:07.32#ibcon#enter sib2, iclass 36, count 2 2006.173.21:24:07.32#ibcon#flushed, iclass 36, count 2 2006.173.21:24:07.32#ibcon#about to write, iclass 36, count 2 2006.173.21:24:07.32#ibcon#wrote, iclass 36, count 2 2006.173.21:24:07.32#ibcon#about to read 3, iclass 36, count 2 2006.173.21:24:07.35#ibcon#read 3, iclass 36, count 2 2006.173.21:24:07.35#ibcon#about to read 4, iclass 36, count 2 2006.173.21:24:07.35#ibcon#read 4, iclass 36, count 2 2006.173.21:24:07.35#ibcon#about to read 5, iclass 36, count 2 2006.173.21:24:07.35#ibcon#read 5, iclass 36, count 2 2006.173.21:24:07.35#ibcon#about to read 6, iclass 36, count 2 2006.173.21:24:07.35#ibcon#read 6, iclass 36, count 2 2006.173.21:24:07.35#ibcon#end of sib2, iclass 36, count 2 2006.173.21:24:07.35#ibcon#*after write, iclass 36, count 2 2006.173.21:24:07.35#ibcon#*before return 0, iclass 36, count 2 2006.173.21:24:07.35#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.21:24:07.35#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.21:24:07.35#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.21:24:07.35#ibcon#ireg 7 cls_cnt 0 2006.173.21:24:07.35#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.21:24:07.47#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.21:24:07.47#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.21:24:07.47#ibcon#enter wrdev, iclass 36, count 0 2006.173.21:24:07.47#ibcon#first serial, iclass 36, count 0 2006.173.21:24:07.47#ibcon#enter sib2, iclass 36, count 0 2006.173.21:24:07.47#ibcon#flushed, iclass 36, count 0 2006.173.21:24:07.47#ibcon#about to write, iclass 36, count 0 2006.173.21:24:07.47#ibcon#wrote, iclass 36, count 0 2006.173.21:24:07.47#ibcon#about to read 3, iclass 36, count 0 2006.173.21:24:07.49#ibcon#read 3, iclass 36, count 0 2006.173.21:24:07.49#ibcon#about to read 4, iclass 36, count 0 2006.173.21:24:07.49#ibcon#read 4, iclass 36, count 0 2006.173.21:24:07.49#ibcon#about to read 5, iclass 36, count 0 2006.173.21:24:07.49#ibcon#read 5, iclass 36, count 0 2006.173.21:24:07.49#ibcon#about to read 6, iclass 36, count 0 2006.173.21:24:07.49#ibcon#read 6, iclass 36, count 0 2006.173.21:24:07.49#ibcon#end of sib2, iclass 36, count 0 2006.173.21:24:07.49#ibcon#*mode == 0, iclass 36, count 0 2006.173.21:24:07.49#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.21:24:07.49#ibcon#[27=USB\r\n] 2006.173.21:24:07.49#ibcon#*before write, iclass 36, count 0 2006.173.21:24:07.49#ibcon#enter sib2, iclass 36, count 0 2006.173.21:24:07.49#ibcon#flushed, iclass 36, count 0 2006.173.21:24:07.49#ibcon#about to write, iclass 36, count 0 2006.173.21:24:07.49#ibcon#wrote, iclass 36, count 0 2006.173.21:24:07.49#ibcon#about to read 3, iclass 36, count 0 2006.173.21:24:07.52#ibcon#read 3, iclass 36, count 0 2006.173.21:24:07.52#ibcon#about to read 4, iclass 36, count 0 2006.173.21:24:07.52#ibcon#read 4, iclass 36, count 0 2006.173.21:24:07.52#ibcon#about to read 5, iclass 36, count 0 2006.173.21:24:07.52#ibcon#read 5, iclass 36, count 0 2006.173.21:24:07.52#ibcon#about to read 6, iclass 36, count 0 2006.173.21:24:07.52#ibcon#read 6, iclass 36, count 0 2006.173.21:24:07.52#ibcon#end of sib2, iclass 36, count 0 2006.173.21:24:07.52#ibcon#*after write, iclass 36, count 0 2006.173.21:24:07.52#ibcon#*before return 0, iclass 36, count 0 2006.173.21:24:07.52#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.21:24:07.52#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.21:24:07.52#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.21:24:07.52#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.21:24:07.52$vck44/vblo=6,719.99 2006.173.21:24:07.52#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.21:24:07.52#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.21:24:07.52#ibcon#ireg 17 cls_cnt 0 2006.173.21:24:07.52#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.21:24:07.52#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.21:24:07.52#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.21:24:07.52#ibcon#enter wrdev, iclass 38, count 0 2006.173.21:24:07.52#ibcon#first serial, iclass 38, count 0 2006.173.21:24:07.52#ibcon#enter sib2, iclass 38, count 0 2006.173.21:24:07.52#ibcon#flushed, iclass 38, count 0 2006.173.21:24:07.52#ibcon#about to write, iclass 38, count 0 2006.173.21:24:07.52#ibcon#wrote, iclass 38, count 0 2006.173.21:24:07.52#ibcon#about to read 3, iclass 38, count 0 2006.173.21:24:07.54#ibcon#read 3, iclass 38, count 0 2006.173.21:24:07.54#ibcon#about to read 4, iclass 38, count 0 2006.173.21:24:07.54#ibcon#read 4, iclass 38, count 0 2006.173.21:24:07.54#ibcon#about to read 5, iclass 38, count 0 2006.173.21:24:07.54#ibcon#read 5, iclass 38, count 0 2006.173.21:24:07.54#ibcon#about to read 6, iclass 38, count 0 2006.173.21:24:07.54#ibcon#read 6, iclass 38, count 0 2006.173.21:24:07.54#ibcon#end of sib2, iclass 38, count 0 2006.173.21:24:07.54#ibcon#*mode == 0, iclass 38, count 0 2006.173.21:24:07.54#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.21:24:07.54#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.21:24:07.54#ibcon#*before write, iclass 38, count 0 2006.173.21:24:07.54#ibcon#enter sib2, iclass 38, count 0 2006.173.21:24:07.54#ibcon#flushed, iclass 38, count 0 2006.173.21:24:07.54#ibcon#about to write, iclass 38, count 0 2006.173.21:24:07.54#ibcon#wrote, iclass 38, count 0 2006.173.21:24:07.54#ibcon#about to read 3, iclass 38, count 0 2006.173.21:24:07.58#ibcon#read 3, iclass 38, count 0 2006.173.21:24:07.58#ibcon#about to read 4, iclass 38, count 0 2006.173.21:24:07.58#ibcon#read 4, iclass 38, count 0 2006.173.21:24:07.58#ibcon#about to read 5, iclass 38, count 0 2006.173.21:24:07.58#ibcon#read 5, iclass 38, count 0 2006.173.21:24:07.58#ibcon#about to read 6, iclass 38, count 0 2006.173.21:24:07.58#ibcon#read 6, iclass 38, count 0 2006.173.21:24:07.58#ibcon#end of sib2, iclass 38, count 0 2006.173.21:24:07.58#ibcon#*after write, iclass 38, count 0 2006.173.21:24:07.58#ibcon#*before return 0, iclass 38, count 0 2006.173.21:24:07.58#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.21:24:07.58#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.21:24:07.58#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.21:24:07.58#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.21:24:07.58$vck44/vb=6,4 2006.173.21:24:07.58#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.21:24:07.58#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.21:24:07.58#ibcon#ireg 11 cls_cnt 2 2006.173.21:24:07.58#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.21:24:07.64#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.21:24:07.64#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.21:24:07.64#ibcon#enter wrdev, iclass 40, count 2 2006.173.21:24:07.64#ibcon#first serial, iclass 40, count 2 2006.173.21:24:07.64#ibcon#enter sib2, iclass 40, count 2 2006.173.21:24:07.64#ibcon#flushed, iclass 40, count 2 2006.173.21:24:07.64#ibcon#about to write, iclass 40, count 2 2006.173.21:24:07.64#ibcon#wrote, iclass 40, count 2 2006.173.21:24:07.64#ibcon#about to read 3, iclass 40, count 2 2006.173.21:24:07.66#ibcon#read 3, iclass 40, count 2 2006.173.21:24:07.66#ibcon#about to read 4, iclass 40, count 2 2006.173.21:24:07.66#ibcon#read 4, iclass 40, count 2 2006.173.21:24:07.66#ibcon#about to read 5, iclass 40, count 2 2006.173.21:24:07.66#ibcon#read 5, iclass 40, count 2 2006.173.21:24:07.66#ibcon#about to read 6, iclass 40, count 2 2006.173.21:24:07.66#ibcon#read 6, iclass 40, count 2 2006.173.21:24:07.66#ibcon#end of sib2, iclass 40, count 2 2006.173.21:24:07.66#ibcon#*mode == 0, iclass 40, count 2 2006.173.21:24:07.66#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.21:24:07.66#ibcon#[27=AT06-04\r\n] 2006.173.21:24:07.66#ibcon#*before write, iclass 40, count 2 2006.173.21:24:07.66#ibcon#enter sib2, iclass 40, count 2 2006.173.21:24:07.66#ibcon#flushed, iclass 40, count 2 2006.173.21:24:07.66#ibcon#about to write, iclass 40, count 2 2006.173.21:24:07.66#ibcon#wrote, iclass 40, count 2 2006.173.21:24:07.66#ibcon#about to read 3, iclass 40, count 2 2006.173.21:24:07.69#ibcon#read 3, iclass 40, count 2 2006.173.21:24:07.69#ibcon#about to read 4, iclass 40, count 2 2006.173.21:24:07.69#ibcon#read 4, iclass 40, count 2 2006.173.21:24:07.69#ibcon#about to read 5, iclass 40, count 2 2006.173.21:24:07.69#ibcon#read 5, iclass 40, count 2 2006.173.21:24:07.69#ibcon#about to read 6, iclass 40, count 2 2006.173.21:24:07.69#ibcon#read 6, iclass 40, count 2 2006.173.21:24:07.69#ibcon#end of sib2, iclass 40, count 2 2006.173.21:24:07.69#ibcon#*after write, iclass 40, count 2 2006.173.21:24:07.69#ibcon#*before return 0, iclass 40, count 2 2006.173.21:24:07.69#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.21:24:07.69#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.21:24:07.69#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.21:24:07.69#ibcon#ireg 7 cls_cnt 0 2006.173.21:24:07.69#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.21:24:07.81#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.21:24:07.81#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.21:24:07.81#ibcon#enter wrdev, iclass 40, count 0 2006.173.21:24:07.81#ibcon#first serial, iclass 40, count 0 2006.173.21:24:07.81#ibcon#enter sib2, iclass 40, count 0 2006.173.21:24:07.81#ibcon#flushed, iclass 40, count 0 2006.173.21:24:07.81#ibcon#about to write, iclass 40, count 0 2006.173.21:24:07.81#ibcon#wrote, iclass 40, count 0 2006.173.21:24:07.81#ibcon#about to read 3, iclass 40, count 0 2006.173.21:24:07.83#ibcon#read 3, iclass 40, count 0 2006.173.21:24:07.83#ibcon#about to read 4, iclass 40, count 0 2006.173.21:24:07.83#ibcon#read 4, iclass 40, count 0 2006.173.21:24:07.83#ibcon#about to read 5, iclass 40, count 0 2006.173.21:24:07.83#ibcon#read 5, iclass 40, count 0 2006.173.21:24:07.83#ibcon#about to read 6, iclass 40, count 0 2006.173.21:24:07.83#ibcon#read 6, iclass 40, count 0 2006.173.21:24:07.83#ibcon#end of sib2, iclass 40, count 0 2006.173.21:24:07.83#ibcon#*mode == 0, iclass 40, count 0 2006.173.21:24:07.83#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.21:24:07.83#ibcon#[27=USB\r\n] 2006.173.21:24:07.83#ibcon#*before write, iclass 40, count 0 2006.173.21:24:07.83#ibcon#enter sib2, iclass 40, count 0 2006.173.21:24:07.83#ibcon#flushed, iclass 40, count 0 2006.173.21:24:07.83#ibcon#about to write, iclass 40, count 0 2006.173.21:24:07.83#ibcon#wrote, iclass 40, count 0 2006.173.21:24:07.83#ibcon#about to read 3, iclass 40, count 0 2006.173.21:24:07.86#ibcon#read 3, iclass 40, count 0 2006.173.21:24:07.86#ibcon#about to read 4, iclass 40, count 0 2006.173.21:24:07.86#ibcon#read 4, iclass 40, count 0 2006.173.21:24:07.86#ibcon#about to read 5, iclass 40, count 0 2006.173.21:24:07.86#ibcon#read 5, iclass 40, count 0 2006.173.21:24:07.86#ibcon#about to read 6, iclass 40, count 0 2006.173.21:24:07.86#ibcon#read 6, iclass 40, count 0 2006.173.21:24:07.86#ibcon#end of sib2, iclass 40, count 0 2006.173.21:24:07.86#ibcon#*after write, iclass 40, count 0 2006.173.21:24:07.86#ibcon#*before return 0, iclass 40, count 0 2006.173.21:24:07.86#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.21:24:07.86#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.21:24:07.86#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.21:24:07.86#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.21:24:07.86$vck44/vblo=7,734.99 2006.173.21:24:07.86#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.21:24:07.86#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.21:24:07.86#ibcon#ireg 17 cls_cnt 0 2006.173.21:24:07.86#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.21:24:07.86#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.21:24:07.86#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.21:24:07.86#ibcon#enter wrdev, iclass 4, count 0 2006.173.21:24:07.86#ibcon#first serial, iclass 4, count 0 2006.173.21:24:07.86#ibcon#enter sib2, iclass 4, count 0 2006.173.21:24:07.86#ibcon#flushed, iclass 4, count 0 2006.173.21:24:07.86#ibcon#about to write, iclass 4, count 0 2006.173.21:24:07.86#ibcon#wrote, iclass 4, count 0 2006.173.21:24:07.86#ibcon#about to read 3, iclass 4, count 0 2006.173.21:24:07.88#ibcon#read 3, iclass 4, count 0 2006.173.21:24:07.88#ibcon#about to read 4, iclass 4, count 0 2006.173.21:24:07.88#ibcon#read 4, iclass 4, count 0 2006.173.21:24:07.88#ibcon#about to read 5, iclass 4, count 0 2006.173.21:24:07.88#ibcon#read 5, iclass 4, count 0 2006.173.21:24:07.88#ibcon#about to read 6, iclass 4, count 0 2006.173.21:24:07.88#ibcon#read 6, iclass 4, count 0 2006.173.21:24:07.88#ibcon#end of sib2, iclass 4, count 0 2006.173.21:24:07.88#ibcon#*mode == 0, iclass 4, count 0 2006.173.21:24:07.88#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.21:24:07.88#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.21:24:07.88#ibcon#*before write, iclass 4, count 0 2006.173.21:24:07.88#ibcon#enter sib2, iclass 4, count 0 2006.173.21:24:07.88#ibcon#flushed, iclass 4, count 0 2006.173.21:24:07.88#ibcon#about to write, iclass 4, count 0 2006.173.21:24:07.88#ibcon#wrote, iclass 4, count 0 2006.173.21:24:07.88#ibcon#about to read 3, iclass 4, count 0 2006.173.21:24:07.92#ibcon#read 3, iclass 4, count 0 2006.173.21:24:07.92#ibcon#about to read 4, iclass 4, count 0 2006.173.21:24:07.92#ibcon#read 4, iclass 4, count 0 2006.173.21:24:07.92#ibcon#about to read 5, iclass 4, count 0 2006.173.21:24:07.92#ibcon#read 5, iclass 4, count 0 2006.173.21:24:07.92#ibcon#about to read 6, iclass 4, count 0 2006.173.21:24:07.92#ibcon#read 6, iclass 4, count 0 2006.173.21:24:07.92#ibcon#end of sib2, iclass 4, count 0 2006.173.21:24:07.92#ibcon#*after write, iclass 4, count 0 2006.173.21:24:07.92#ibcon#*before return 0, iclass 4, count 0 2006.173.21:24:07.92#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.21:24:07.92#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.21:24:07.92#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.21:24:07.92#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.21:24:07.92$vck44/vb=7,4 2006.173.21:24:07.92#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.21:24:07.92#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.21:24:07.92#ibcon#ireg 11 cls_cnt 2 2006.173.21:24:07.92#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.21:24:07.98#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.21:24:07.98#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.21:24:07.98#ibcon#enter wrdev, iclass 6, count 2 2006.173.21:24:07.98#ibcon#first serial, iclass 6, count 2 2006.173.21:24:07.98#ibcon#enter sib2, iclass 6, count 2 2006.173.21:24:07.98#ibcon#flushed, iclass 6, count 2 2006.173.21:24:07.98#ibcon#about to write, iclass 6, count 2 2006.173.21:24:07.98#ibcon#wrote, iclass 6, count 2 2006.173.21:24:07.98#ibcon#about to read 3, iclass 6, count 2 2006.173.21:24:08.00#ibcon#read 3, iclass 6, count 2 2006.173.21:24:08.00#ibcon#about to read 4, iclass 6, count 2 2006.173.21:24:08.00#ibcon#read 4, iclass 6, count 2 2006.173.21:24:08.00#ibcon#about to read 5, iclass 6, count 2 2006.173.21:24:08.00#ibcon#read 5, iclass 6, count 2 2006.173.21:24:08.00#ibcon#about to read 6, iclass 6, count 2 2006.173.21:24:08.00#ibcon#read 6, iclass 6, count 2 2006.173.21:24:08.00#ibcon#end of sib2, iclass 6, count 2 2006.173.21:24:08.00#ibcon#*mode == 0, iclass 6, count 2 2006.173.21:24:08.00#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.21:24:08.00#ibcon#[27=AT07-04\r\n] 2006.173.21:24:08.00#ibcon#*before write, iclass 6, count 2 2006.173.21:24:08.00#ibcon#enter sib2, iclass 6, count 2 2006.173.21:24:08.00#ibcon#flushed, iclass 6, count 2 2006.173.21:24:08.00#ibcon#about to write, iclass 6, count 2 2006.173.21:24:08.00#ibcon#wrote, iclass 6, count 2 2006.173.21:24:08.00#ibcon#about to read 3, iclass 6, count 2 2006.173.21:24:08.03#ibcon#read 3, iclass 6, count 2 2006.173.21:24:08.03#ibcon#about to read 4, iclass 6, count 2 2006.173.21:24:08.03#ibcon#read 4, iclass 6, count 2 2006.173.21:24:08.03#ibcon#about to read 5, iclass 6, count 2 2006.173.21:24:08.03#ibcon#read 5, iclass 6, count 2 2006.173.21:24:08.03#ibcon#about to read 6, iclass 6, count 2 2006.173.21:24:08.03#ibcon#read 6, iclass 6, count 2 2006.173.21:24:08.03#ibcon#end of sib2, iclass 6, count 2 2006.173.21:24:08.03#ibcon#*after write, iclass 6, count 2 2006.173.21:24:08.03#ibcon#*before return 0, iclass 6, count 2 2006.173.21:24:08.03#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.21:24:08.03#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.21:24:08.03#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.21:24:08.03#ibcon#ireg 7 cls_cnt 0 2006.173.21:24:08.03#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.21:24:08.15#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.21:24:08.15#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.21:24:08.15#ibcon#enter wrdev, iclass 6, count 0 2006.173.21:24:08.15#ibcon#first serial, iclass 6, count 0 2006.173.21:24:08.15#ibcon#enter sib2, iclass 6, count 0 2006.173.21:24:08.15#ibcon#flushed, iclass 6, count 0 2006.173.21:24:08.15#ibcon#about to write, iclass 6, count 0 2006.173.21:24:08.15#ibcon#wrote, iclass 6, count 0 2006.173.21:24:08.15#ibcon#about to read 3, iclass 6, count 0 2006.173.21:24:08.17#ibcon#read 3, iclass 6, count 0 2006.173.21:24:08.17#ibcon#about to read 4, iclass 6, count 0 2006.173.21:24:08.17#ibcon#read 4, iclass 6, count 0 2006.173.21:24:08.17#ibcon#about to read 5, iclass 6, count 0 2006.173.21:24:08.17#ibcon#read 5, iclass 6, count 0 2006.173.21:24:08.17#ibcon#about to read 6, iclass 6, count 0 2006.173.21:24:08.17#ibcon#read 6, iclass 6, count 0 2006.173.21:24:08.17#ibcon#end of sib2, iclass 6, count 0 2006.173.21:24:08.17#ibcon#*mode == 0, iclass 6, count 0 2006.173.21:24:08.17#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.21:24:08.17#ibcon#[27=USB\r\n] 2006.173.21:24:08.17#ibcon#*before write, iclass 6, count 0 2006.173.21:24:08.17#ibcon#enter sib2, iclass 6, count 0 2006.173.21:24:08.17#ibcon#flushed, iclass 6, count 0 2006.173.21:24:08.17#ibcon#about to write, iclass 6, count 0 2006.173.21:24:08.17#ibcon#wrote, iclass 6, count 0 2006.173.21:24:08.17#ibcon#about to read 3, iclass 6, count 0 2006.173.21:24:08.20#ibcon#read 3, iclass 6, count 0 2006.173.21:24:08.20#ibcon#about to read 4, iclass 6, count 0 2006.173.21:24:08.20#ibcon#read 4, iclass 6, count 0 2006.173.21:24:08.20#ibcon#about to read 5, iclass 6, count 0 2006.173.21:24:08.20#ibcon#read 5, iclass 6, count 0 2006.173.21:24:08.20#ibcon#about to read 6, iclass 6, count 0 2006.173.21:24:08.20#ibcon#read 6, iclass 6, count 0 2006.173.21:24:08.20#ibcon#end of sib2, iclass 6, count 0 2006.173.21:24:08.20#ibcon#*after write, iclass 6, count 0 2006.173.21:24:08.20#ibcon#*before return 0, iclass 6, count 0 2006.173.21:24:08.20#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.21:24:08.20#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.21:24:08.20#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.21:24:08.20#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.21:24:08.20$vck44/vblo=8,744.99 2006.173.21:24:08.20#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.21:24:08.20#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.21:24:08.20#ibcon#ireg 17 cls_cnt 0 2006.173.21:24:08.20#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.21:24:08.20#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.21:24:08.20#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.21:24:08.20#ibcon#enter wrdev, iclass 10, count 0 2006.173.21:24:08.20#ibcon#first serial, iclass 10, count 0 2006.173.21:24:08.20#ibcon#enter sib2, iclass 10, count 0 2006.173.21:24:08.20#ibcon#flushed, iclass 10, count 0 2006.173.21:24:08.20#ibcon#about to write, iclass 10, count 0 2006.173.21:24:08.20#ibcon#wrote, iclass 10, count 0 2006.173.21:24:08.20#ibcon#about to read 3, iclass 10, count 0 2006.173.21:24:08.22#ibcon#read 3, iclass 10, count 0 2006.173.21:24:08.22#ibcon#about to read 4, iclass 10, count 0 2006.173.21:24:08.22#ibcon#read 4, iclass 10, count 0 2006.173.21:24:08.22#ibcon#about to read 5, iclass 10, count 0 2006.173.21:24:08.22#ibcon#read 5, iclass 10, count 0 2006.173.21:24:08.22#ibcon#about to read 6, iclass 10, count 0 2006.173.21:24:08.22#ibcon#read 6, iclass 10, count 0 2006.173.21:24:08.22#ibcon#end of sib2, iclass 10, count 0 2006.173.21:24:08.22#ibcon#*mode == 0, iclass 10, count 0 2006.173.21:24:08.22#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.21:24:08.22#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.21:24:08.22#ibcon#*before write, iclass 10, count 0 2006.173.21:24:08.22#ibcon#enter sib2, iclass 10, count 0 2006.173.21:24:08.22#ibcon#flushed, iclass 10, count 0 2006.173.21:24:08.22#ibcon#about to write, iclass 10, count 0 2006.173.21:24:08.22#ibcon#wrote, iclass 10, count 0 2006.173.21:24:08.22#ibcon#about to read 3, iclass 10, count 0 2006.173.21:24:08.26#ibcon#read 3, iclass 10, count 0 2006.173.21:24:08.26#ibcon#about to read 4, iclass 10, count 0 2006.173.21:24:08.26#ibcon#read 4, iclass 10, count 0 2006.173.21:24:08.26#ibcon#about to read 5, iclass 10, count 0 2006.173.21:24:08.26#ibcon#read 5, iclass 10, count 0 2006.173.21:24:08.26#ibcon#about to read 6, iclass 10, count 0 2006.173.21:24:08.26#ibcon#read 6, iclass 10, count 0 2006.173.21:24:08.26#ibcon#end of sib2, iclass 10, count 0 2006.173.21:24:08.26#ibcon#*after write, iclass 10, count 0 2006.173.21:24:08.26#ibcon#*before return 0, iclass 10, count 0 2006.173.21:24:08.26#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.21:24:08.26#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.21:24:08.26#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.21:24:08.26#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.21:24:08.26$vck44/vb=8,4 2006.173.21:24:08.26#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.21:24:08.26#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.21:24:08.26#ibcon#ireg 11 cls_cnt 2 2006.173.21:24:08.26#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.21:24:08.32#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.21:24:08.32#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.21:24:08.32#ibcon#enter wrdev, iclass 12, count 2 2006.173.21:24:08.32#ibcon#first serial, iclass 12, count 2 2006.173.21:24:08.32#ibcon#enter sib2, iclass 12, count 2 2006.173.21:24:08.32#ibcon#flushed, iclass 12, count 2 2006.173.21:24:08.32#ibcon#about to write, iclass 12, count 2 2006.173.21:24:08.32#ibcon#wrote, iclass 12, count 2 2006.173.21:24:08.32#ibcon#about to read 3, iclass 12, count 2 2006.173.21:24:08.34#ibcon#read 3, iclass 12, count 2 2006.173.21:24:08.34#ibcon#about to read 4, iclass 12, count 2 2006.173.21:24:08.34#ibcon#read 4, iclass 12, count 2 2006.173.21:24:08.34#ibcon#about to read 5, iclass 12, count 2 2006.173.21:24:08.34#ibcon#read 5, iclass 12, count 2 2006.173.21:24:08.34#ibcon#about to read 6, iclass 12, count 2 2006.173.21:24:08.34#ibcon#read 6, iclass 12, count 2 2006.173.21:24:08.34#ibcon#end of sib2, iclass 12, count 2 2006.173.21:24:08.34#ibcon#*mode == 0, iclass 12, count 2 2006.173.21:24:08.34#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.21:24:08.34#ibcon#[27=AT08-04\r\n] 2006.173.21:24:08.34#ibcon#*before write, iclass 12, count 2 2006.173.21:24:08.34#ibcon#enter sib2, iclass 12, count 2 2006.173.21:24:08.34#ibcon#flushed, iclass 12, count 2 2006.173.21:24:08.34#ibcon#about to write, iclass 12, count 2 2006.173.21:24:08.34#ibcon#wrote, iclass 12, count 2 2006.173.21:24:08.34#ibcon#about to read 3, iclass 12, count 2 2006.173.21:24:08.37#ibcon#read 3, iclass 12, count 2 2006.173.21:24:08.37#ibcon#about to read 4, iclass 12, count 2 2006.173.21:24:08.37#ibcon#read 4, iclass 12, count 2 2006.173.21:24:08.37#ibcon#about to read 5, iclass 12, count 2 2006.173.21:24:08.37#ibcon#read 5, iclass 12, count 2 2006.173.21:24:08.37#ibcon#about to read 6, iclass 12, count 2 2006.173.21:24:08.37#ibcon#read 6, iclass 12, count 2 2006.173.21:24:08.37#ibcon#end of sib2, iclass 12, count 2 2006.173.21:24:08.37#ibcon#*after write, iclass 12, count 2 2006.173.21:24:08.37#ibcon#*before return 0, iclass 12, count 2 2006.173.21:24:08.37#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.21:24:08.37#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.21:24:08.37#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.21:24:08.37#ibcon#ireg 7 cls_cnt 0 2006.173.21:24:08.37#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.21:24:08.49#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.21:24:08.49#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.21:24:08.49#ibcon#enter wrdev, iclass 12, count 0 2006.173.21:24:08.49#ibcon#first serial, iclass 12, count 0 2006.173.21:24:08.49#ibcon#enter sib2, iclass 12, count 0 2006.173.21:24:08.49#ibcon#flushed, iclass 12, count 0 2006.173.21:24:08.49#ibcon#about to write, iclass 12, count 0 2006.173.21:24:08.49#ibcon#wrote, iclass 12, count 0 2006.173.21:24:08.49#ibcon#about to read 3, iclass 12, count 0 2006.173.21:24:08.51#ibcon#read 3, iclass 12, count 0 2006.173.21:24:08.51#ibcon#about to read 4, iclass 12, count 0 2006.173.21:24:08.51#ibcon#read 4, iclass 12, count 0 2006.173.21:24:08.51#ibcon#about to read 5, iclass 12, count 0 2006.173.21:24:08.51#ibcon#read 5, iclass 12, count 0 2006.173.21:24:08.51#ibcon#about to read 6, iclass 12, count 0 2006.173.21:24:08.51#ibcon#read 6, iclass 12, count 0 2006.173.21:24:08.51#ibcon#end of sib2, iclass 12, count 0 2006.173.21:24:08.51#ibcon#*mode == 0, iclass 12, count 0 2006.173.21:24:08.51#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.21:24:08.51#ibcon#[27=USB\r\n] 2006.173.21:24:08.51#ibcon#*before write, iclass 12, count 0 2006.173.21:24:08.51#ibcon#enter sib2, iclass 12, count 0 2006.173.21:24:08.51#ibcon#flushed, iclass 12, count 0 2006.173.21:24:08.51#ibcon#about to write, iclass 12, count 0 2006.173.21:24:08.51#ibcon#wrote, iclass 12, count 0 2006.173.21:24:08.51#ibcon#about to read 3, iclass 12, count 0 2006.173.21:24:08.54#ibcon#read 3, iclass 12, count 0 2006.173.21:24:08.54#ibcon#about to read 4, iclass 12, count 0 2006.173.21:24:08.54#ibcon#read 4, iclass 12, count 0 2006.173.21:24:08.54#ibcon#about to read 5, iclass 12, count 0 2006.173.21:24:08.54#ibcon#read 5, iclass 12, count 0 2006.173.21:24:08.54#ibcon#about to read 6, iclass 12, count 0 2006.173.21:24:08.54#ibcon#read 6, iclass 12, count 0 2006.173.21:24:08.54#ibcon#end of sib2, iclass 12, count 0 2006.173.21:24:08.54#ibcon#*after write, iclass 12, count 0 2006.173.21:24:08.54#ibcon#*before return 0, iclass 12, count 0 2006.173.21:24:08.54#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.21:24:08.54#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.21:24:08.54#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.21:24:08.54#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.21:24:08.54$vck44/vabw=wide 2006.173.21:24:08.54#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.21:24:08.54#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.21:24:08.54#ibcon#ireg 8 cls_cnt 0 2006.173.21:24:08.54#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.21:24:08.54#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.21:24:08.54#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.21:24:08.54#ibcon#enter wrdev, iclass 14, count 0 2006.173.21:24:08.54#ibcon#first serial, iclass 14, count 0 2006.173.21:24:08.54#ibcon#enter sib2, iclass 14, count 0 2006.173.21:24:08.54#ibcon#flushed, iclass 14, count 0 2006.173.21:24:08.54#ibcon#about to write, iclass 14, count 0 2006.173.21:24:08.54#ibcon#wrote, iclass 14, count 0 2006.173.21:24:08.54#ibcon#about to read 3, iclass 14, count 0 2006.173.21:24:08.56#ibcon#read 3, iclass 14, count 0 2006.173.21:24:08.56#ibcon#about to read 4, iclass 14, count 0 2006.173.21:24:08.56#ibcon#read 4, iclass 14, count 0 2006.173.21:24:08.56#ibcon#about to read 5, iclass 14, count 0 2006.173.21:24:08.56#ibcon#read 5, iclass 14, count 0 2006.173.21:24:08.56#ibcon#about to read 6, iclass 14, count 0 2006.173.21:24:08.56#ibcon#read 6, iclass 14, count 0 2006.173.21:24:08.56#ibcon#end of sib2, iclass 14, count 0 2006.173.21:24:08.56#ibcon#*mode == 0, iclass 14, count 0 2006.173.21:24:08.56#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.21:24:08.56#ibcon#[25=BW32\r\n] 2006.173.21:24:08.56#ibcon#*before write, iclass 14, count 0 2006.173.21:24:08.56#ibcon#enter sib2, iclass 14, count 0 2006.173.21:24:08.56#ibcon#flushed, iclass 14, count 0 2006.173.21:24:08.56#ibcon#about to write, iclass 14, count 0 2006.173.21:24:08.56#ibcon#wrote, iclass 14, count 0 2006.173.21:24:08.56#ibcon#about to read 3, iclass 14, count 0 2006.173.21:24:08.59#ibcon#read 3, iclass 14, count 0 2006.173.21:24:08.59#ibcon#about to read 4, iclass 14, count 0 2006.173.21:24:08.59#ibcon#read 4, iclass 14, count 0 2006.173.21:24:08.59#ibcon#about to read 5, iclass 14, count 0 2006.173.21:24:08.59#ibcon#read 5, iclass 14, count 0 2006.173.21:24:08.59#ibcon#about to read 6, iclass 14, count 0 2006.173.21:24:08.59#ibcon#read 6, iclass 14, count 0 2006.173.21:24:08.59#ibcon#end of sib2, iclass 14, count 0 2006.173.21:24:08.59#ibcon#*after write, iclass 14, count 0 2006.173.21:24:08.59#ibcon#*before return 0, iclass 14, count 0 2006.173.21:24:08.59#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.21:24:08.59#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.21:24:08.59#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.21:24:08.59#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.21:24:08.59$vck44/vbbw=wide 2006.173.21:24:08.59#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.21:24:08.59#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.21:24:08.59#ibcon#ireg 8 cls_cnt 0 2006.173.21:24:08.59#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.21:24:08.66#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.21:24:08.66#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.21:24:08.66#ibcon#enter wrdev, iclass 16, count 0 2006.173.21:24:08.66#ibcon#first serial, iclass 16, count 0 2006.173.21:24:08.66#ibcon#enter sib2, iclass 16, count 0 2006.173.21:24:08.66#ibcon#flushed, iclass 16, count 0 2006.173.21:24:08.66#ibcon#about to write, iclass 16, count 0 2006.173.21:24:08.66#ibcon#wrote, iclass 16, count 0 2006.173.21:24:08.66#ibcon#about to read 3, iclass 16, count 0 2006.173.21:24:08.68#ibcon#read 3, iclass 16, count 0 2006.173.21:24:08.68#ibcon#about to read 4, iclass 16, count 0 2006.173.21:24:08.68#ibcon#read 4, iclass 16, count 0 2006.173.21:24:08.68#ibcon#about to read 5, iclass 16, count 0 2006.173.21:24:08.68#ibcon#read 5, iclass 16, count 0 2006.173.21:24:08.68#ibcon#about to read 6, iclass 16, count 0 2006.173.21:24:08.68#ibcon#read 6, iclass 16, count 0 2006.173.21:24:08.68#ibcon#end of sib2, iclass 16, count 0 2006.173.21:24:08.68#ibcon#*mode == 0, iclass 16, count 0 2006.173.21:24:08.68#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.21:24:08.68#ibcon#[27=BW32\r\n] 2006.173.21:24:08.68#ibcon#*before write, iclass 16, count 0 2006.173.21:24:08.68#ibcon#enter sib2, iclass 16, count 0 2006.173.21:24:08.68#ibcon#flushed, iclass 16, count 0 2006.173.21:24:08.68#ibcon#about to write, iclass 16, count 0 2006.173.21:24:08.68#ibcon#wrote, iclass 16, count 0 2006.173.21:24:08.68#ibcon#about to read 3, iclass 16, count 0 2006.173.21:24:08.71#ibcon#read 3, iclass 16, count 0 2006.173.21:24:08.71#ibcon#about to read 4, iclass 16, count 0 2006.173.21:24:08.71#ibcon#read 4, iclass 16, count 0 2006.173.21:24:08.71#ibcon#about to read 5, iclass 16, count 0 2006.173.21:24:08.71#ibcon#read 5, iclass 16, count 0 2006.173.21:24:08.71#ibcon#about to read 6, iclass 16, count 0 2006.173.21:24:08.71#ibcon#read 6, iclass 16, count 0 2006.173.21:24:08.71#ibcon#end of sib2, iclass 16, count 0 2006.173.21:24:08.71#ibcon#*after write, iclass 16, count 0 2006.173.21:24:08.71#ibcon#*before return 0, iclass 16, count 0 2006.173.21:24:08.71#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.21:24:08.71#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.21:24:08.71#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.21:24:08.71#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.21:24:08.71$setupk4/ifdk4 2006.173.21:24:08.71$ifdk4/lo= 2006.173.21:24:08.71$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.21:24:08.71$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.21:24:08.71$ifdk4/patch= 2006.173.21:24:08.71$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.21:24:08.71$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.21:24:08.71$setupk4/!*+20s 2006.173.21:24:12.89#abcon#<5=/11 0.5 1.2 20.971001003.0\r\n> 2006.173.21:24:12.91#abcon#{5=INTERFACE CLEAR} 2006.173.21:24:12.97#abcon#[5=S1D000X0/0*\r\n] 2006.173.21:24:23.06#abcon#<5=/11 0.5 1.2 20.971001003.0\r\n> 2006.173.21:24:23.08#abcon#{5=INTERFACE CLEAR} 2006.173.21:24:23.14#abcon#[5=S1D000X0/0*\r\n] 2006.173.21:24:23.21$setupk4/"tpicd 2006.173.21:24:23.21$setupk4/echo=off 2006.173.21:24:23.21$setupk4/xlog=off 2006.173.21:24:23.21:!2006.173.21:28:22 2006.173.21:25:06.14#trakl#Source acquired 2006.173.21:25:08.14#flagr#flagr/antenna,acquired 2006.173.21:28:22.00:preob 2006.173.21:28:22.13/onsource/TRACKING 2006.173.21:28:22.13:!2006.173.21:28:32 2006.173.21:28:32.00:"tape 2006.173.21:28:32.00:"st=record 2006.173.21:28:32.00:data_valid=on 2006.173.21:28:32.00:midob 2006.173.21:28:32.14/onsource/TRACKING 2006.173.21:28:32.14/wx/21.00,1003.1,100 2006.173.21:28:32.29/cable/+6.5159E-03 2006.173.21:28:33.38/va/01,07,usb,yes,36,38 2006.173.21:28:33.38/va/02,06,usb,yes,35,36 2006.173.21:28:33.38/va/03,05,usb,yes,45,47 2006.173.21:28:33.38/va/04,06,usb,yes,36,38 2006.173.21:28:33.38/va/05,04,usb,yes,28,29 2006.173.21:28:33.38/va/06,03,usb,yes,40,39 2006.173.21:28:33.38/va/07,04,usb,yes,32,33 2006.173.21:28:33.38/va/08,04,usb,yes,27,33 2006.173.21:28:33.61/valo/01,524.99,yes,locked 2006.173.21:28:33.61/valo/02,534.99,yes,locked 2006.173.21:28:33.61/valo/03,564.99,yes,locked 2006.173.21:28:33.61/valo/04,624.99,yes,locked 2006.173.21:28:33.61/valo/05,734.99,yes,locked 2006.173.21:28:33.61/valo/06,814.99,yes,locked 2006.173.21:28:33.61/valo/07,864.99,yes,locked 2006.173.21:28:33.61/valo/08,884.99,yes,locked 2006.173.21:28:34.70/vb/01,04,usb,yes,29,27 2006.173.21:28:34.70/vb/02,04,usb,yes,32,31 2006.173.21:28:34.70/vb/03,04,usb,yes,29,32 2006.173.21:28:34.70/vb/04,04,usb,yes,33,32 2006.173.21:28:34.70/vb/05,04,usb,yes,26,28 2006.173.21:28:34.70/vb/06,04,usb,yes,30,26 2006.173.21:28:34.70/vb/07,04,usb,yes,30,30 2006.173.21:28:34.70/vb/08,04,usb,yes,27,31 2006.173.21:28:34.94/vblo/01,629.99,yes,locked 2006.173.21:28:34.94/vblo/02,634.99,yes,locked 2006.173.21:28:34.94/vblo/03,649.99,yes,locked 2006.173.21:28:34.94/vblo/04,679.99,yes,locked 2006.173.21:28:34.94/vblo/05,709.99,yes,locked 2006.173.21:28:34.94/vblo/06,719.99,yes,locked 2006.173.21:28:34.94/vblo/07,734.99,yes,locked 2006.173.21:28:34.94/vblo/08,744.99,yes,locked 2006.173.21:28:35.09/vabw/8 2006.173.21:28:35.24/vbbw/8 2006.173.21:28:35.33/xfe/off,on,14.7 2006.173.21:28:35.70/ifatt/23,28,28,28 2006.173.21:28:36.08/fmout-gps/S +3.88E-07 2006.173.21:28:36.12:!2006.173.21:29:22 2006.173.21:29:22.01:data_valid=off 2006.173.21:29:22.01:"et 2006.173.21:29:22.02:!+3s 2006.173.21:29:25.03:"tape 2006.173.21:29:25.03:postob 2006.173.21:29:25.16/cable/+6.5164E-03 2006.173.21:29:25.16/wx/21.03,1003.1,100 2006.173.21:29:25.22/fmout-gps/S +3.89E-07 2006.173.21:29:25.22:scan_name=173-2132,jd0606,210 2006.173.21:29:25.23:source=0059+581,010245.76,582411.1,2000.0,neutral 2006.173.21:29:26.14#flagr#flagr/antenna,new-source 2006.173.21:29:26.14:checkk5 2006.173.21:29:26.55/chk_autoobs//k5ts1/ autoobs is running! 2006.173.21:29:26.94/chk_autoobs//k5ts2/ autoobs is running! 2006.173.21:29:27.37/chk_autoobs//k5ts3/ autoobs is running! 2006.173.21:29:27.76/chk_autoobs//k5ts4/ autoobs is running! 2006.173.21:29:28.15/chk_obsdata//k5ts1/T1732128??a.dat file size is correct (nominal:200MB, actual:196MB). 2006.173.21:29:28.54/chk_obsdata//k5ts2/T1732128??b.dat file size is correct (nominal:200MB, actual:196MB). 2006.173.21:29:28.94/chk_obsdata//k5ts3/T1732128??c.dat file size is correct (nominal:200MB, actual:196MB). 2006.173.21:29:29.34/chk_obsdata//k5ts4/T1732128??d.dat file size is correct (nominal:200MB, actual:196MB). 2006.173.21:29:30.06/k5log//k5ts1_log_newline 2006.173.21:29:30.78/k5log//k5ts2_log_newline 2006.173.21:29:31.51/k5log//k5ts3_log_newline 2006.173.21:29:32.21/k5log//k5ts4_log_newline 2006.173.21:29:32.24/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.21:29:32.24:setupk4=1 2006.173.21:29:32.24$setupk4/echo=on 2006.173.21:29:32.24$setupk4/pcalon 2006.173.21:29:32.24$pcalon/"no phase cal control is implemented here 2006.173.21:29:32.24$setupk4/"tpicd=stop 2006.173.21:29:32.24$setupk4/"rec=synch_on 2006.173.21:29:32.24$setupk4/"rec_mode=128 2006.173.21:29:32.24$setupk4/!* 2006.173.21:29:32.24$setupk4/recpk4 2006.173.21:29:32.24$recpk4/recpatch= 2006.173.21:29:32.25$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.21:29:32.25$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.21:29:32.25$setupk4/vck44 2006.173.21:29:32.25$vck44/valo=1,524.99 2006.173.21:29:32.25#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.21:29:32.25#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.21:29:32.25#ibcon#ireg 17 cls_cnt 0 2006.173.21:29:32.25#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.21:29:32.25#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.21:29:32.25#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.21:29:32.25#ibcon#enter wrdev, iclass 3, count 0 2006.173.21:29:32.25#ibcon#first serial, iclass 3, count 0 2006.173.21:29:32.25#ibcon#enter sib2, iclass 3, count 0 2006.173.21:29:32.25#ibcon#flushed, iclass 3, count 0 2006.173.21:29:32.25#ibcon#about to write, iclass 3, count 0 2006.173.21:29:32.25#ibcon#wrote, iclass 3, count 0 2006.173.21:29:32.25#ibcon#about to read 3, iclass 3, count 0 2006.173.21:29:32.26#ibcon#read 3, iclass 3, count 0 2006.173.21:29:32.26#ibcon#about to read 4, iclass 3, count 0 2006.173.21:29:32.26#ibcon#read 4, iclass 3, count 0 2006.173.21:29:32.26#ibcon#about to read 5, iclass 3, count 0 2006.173.21:29:32.26#ibcon#read 5, iclass 3, count 0 2006.173.21:29:32.26#ibcon#about to read 6, iclass 3, count 0 2006.173.21:29:32.26#ibcon#read 6, iclass 3, count 0 2006.173.21:29:32.26#ibcon#end of sib2, iclass 3, count 0 2006.173.21:29:32.26#ibcon#*mode == 0, iclass 3, count 0 2006.173.21:29:32.26#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.21:29:32.26#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.21:29:32.26#ibcon#*before write, iclass 3, count 0 2006.173.21:29:32.26#ibcon#enter sib2, iclass 3, count 0 2006.173.21:29:32.26#ibcon#flushed, iclass 3, count 0 2006.173.21:29:32.26#ibcon#about to write, iclass 3, count 0 2006.173.21:29:32.26#ibcon#wrote, iclass 3, count 0 2006.173.21:29:32.26#ibcon#about to read 3, iclass 3, count 0 2006.173.21:29:32.31#ibcon#read 3, iclass 3, count 0 2006.173.21:29:32.31#ibcon#about to read 4, iclass 3, count 0 2006.173.21:29:32.31#ibcon#read 4, iclass 3, count 0 2006.173.21:29:32.31#ibcon#about to read 5, iclass 3, count 0 2006.173.21:29:32.31#ibcon#read 5, iclass 3, count 0 2006.173.21:29:32.31#ibcon#about to read 6, iclass 3, count 0 2006.173.21:29:32.31#ibcon#read 6, iclass 3, count 0 2006.173.21:29:32.31#ibcon#end of sib2, iclass 3, count 0 2006.173.21:29:32.31#ibcon#*after write, iclass 3, count 0 2006.173.21:29:32.31#ibcon#*before return 0, iclass 3, count 0 2006.173.21:29:32.31#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.21:29:32.31#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.21:29:32.31#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.21:29:32.31#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.21:29:32.31$vck44/va=1,7 2006.173.21:29:32.31#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.21:29:32.31#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.21:29:32.31#ibcon#ireg 11 cls_cnt 2 2006.173.21:29:32.31#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.21:29:32.31#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.21:29:32.31#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.21:29:32.31#ibcon#enter wrdev, iclass 5, count 2 2006.173.21:29:32.31#ibcon#first serial, iclass 5, count 2 2006.173.21:29:32.31#ibcon#enter sib2, iclass 5, count 2 2006.173.21:29:32.31#ibcon#flushed, iclass 5, count 2 2006.173.21:29:32.31#ibcon#about to write, iclass 5, count 2 2006.173.21:29:32.31#ibcon#wrote, iclass 5, count 2 2006.173.21:29:32.31#ibcon#about to read 3, iclass 5, count 2 2006.173.21:29:32.33#ibcon#read 3, iclass 5, count 2 2006.173.21:29:32.33#ibcon#about to read 4, iclass 5, count 2 2006.173.21:29:32.33#ibcon#read 4, iclass 5, count 2 2006.173.21:29:32.33#ibcon#about to read 5, iclass 5, count 2 2006.173.21:29:32.33#ibcon#read 5, iclass 5, count 2 2006.173.21:29:32.33#ibcon#about to read 6, iclass 5, count 2 2006.173.21:29:32.33#ibcon#read 6, iclass 5, count 2 2006.173.21:29:32.33#ibcon#end of sib2, iclass 5, count 2 2006.173.21:29:32.33#ibcon#*mode == 0, iclass 5, count 2 2006.173.21:29:32.33#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.21:29:32.33#ibcon#[25=AT01-07\r\n] 2006.173.21:29:32.33#ibcon#*before write, iclass 5, count 2 2006.173.21:29:32.33#ibcon#enter sib2, iclass 5, count 2 2006.173.21:29:32.33#ibcon#flushed, iclass 5, count 2 2006.173.21:29:32.33#ibcon#about to write, iclass 5, count 2 2006.173.21:29:32.33#ibcon#wrote, iclass 5, count 2 2006.173.21:29:32.33#ibcon#about to read 3, iclass 5, count 2 2006.173.21:29:32.36#ibcon#read 3, iclass 5, count 2 2006.173.21:29:32.36#ibcon#about to read 4, iclass 5, count 2 2006.173.21:29:32.36#ibcon#read 4, iclass 5, count 2 2006.173.21:29:32.36#ibcon#about to read 5, iclass 5, count 2 2006.173.21:29:32.36#ibcon#read 5, iclass 5, count 2 2006.173.21:29:32.36#ibcon#about to read 6, iclass 5, count 2 2006.173.21:29:32.36#ibcon#read 6, iclass 5, count 2 2006.173.21:29:32.36#ibcon#end of sib2, iclass 5, count 2 2006.173.21:29:32.36#ibcon#*after write, iclass 5, count 2 2006.173.21:29:32.36#ibcon#*before return 0, iclass 5, count 2 2006.173.21:29:32.36#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.21:29:32.36#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.21:29:32.36#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.21:29:32.36#ibcon#ireg 7 cls_cnt 0 2006.173.21:29:32.36#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.21:29:32.48#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.21:29:32.48#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.21:29:32.48#ibcon#enter wrdev, iclass 5, count 0 2006.173.21:29:32.48#ibcon#first serial, iclass 5, count 0 2006.173.21:29:32.48#ibcon#enter sib2, iclass 5, count 0 2006.173.21:29:32.48#ibcon#flushed, iclass 5, count 0 2006.173.21:29:32.48#ibcon#about to write, iclass 5, count 0 2006.173.21:29:32.48#ibcon#wrote, iclass 5, count 0 2006.173.21:29:32.48#ibcon#about to read 3, iclass 5, count 0 2006.173.21:29:32.50#ibcon#read 3, iclass 5, count 0 2006.173.21:29:32.50#ibcon#about to read 4, iclass 5, count 0 2006.173.21:29:32.50#ibcon#read 4, iclass 5, count 0 2006.173.21:29:32.50#ibcon#about to read 5, iclass 5, count 0 2006.173.21:29:32.50#ibcon#read 5, iclass 5, count 0 2006.173.21:29:32.50#ibcon#about to read 6, iclass 5, count 0 2006.173.21:29:32.50#ibcon#read 6, iclass 5, count 0 2006.173.21:29:32.50#ibcon#end of sib2, iclass 5, count 0 2006.173.21:29:32.50#ibcon#*mode == 0, iclass 5, count 0 2006.173.21:29:32.50#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.21:29:32.50#ibcon#[25=USB\r\n] 2006.173.21:29:32.50#ibcon#*before write, iclass 5, count 0 2006.173.21:29:32.50#ibcon#enter sib2, iclass 5, count 0 2006.173.21:29:32.50#ibcon#flushed, iclass 5, count 0 2006.173.21:29:32.50#ibcon#about to write, iclass 5, count 0 2006.173.21:29:32.50#ibcon#wrote, iclass 5, count 0 2006.173.21:29:32.50#ibcon#about to read 3, iclass 5, count 0 2006.173.21:29:32.53#ibcon#read 3, iclass 5, count 0 2006.173.21:29:32.53#ibcon#about to read 4, iclass 5, count 0 2006.173.21:29:32.53#ibcon#read 4, iclass 5, count 0 2006.173.21:29:32.53#ibcon#about to read 5, iclass 5, count 0 2006.173.21:29:32.53#ibcon#read 5, iclass 5, count 0 2006.173.21:29:32.53#ibcon#about to read 6, iclass 5, count 0 2006.173.21:29:32.53#ibcon#read 6, iclass 5, count 0 2006.173.21:29:32.53#ibcon#end of sib2, iclass 5, count 0 2006.173.21:29:32.53#ibcon#*after write, iclass 5, count 0 2006.173.21:29:32.53#ibcon#*before return 0, iclass 5, count 0 2006.173.21:29:32.53#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.21:29:32.53#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.21:29:32.53#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.21:29:32.53#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.21:29:32.53$vck44/valo=2,534.99 2006.173.21:29:32.53#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.21:29:32.53#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.21:29:32.53#ibcon#ireg 17 cls_cnt 0 2006.173.21:29:32.53#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.21:29:32.53#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.21:29:32.53#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.21:29:32.53#ibcon#enter wrdev, iclass 7, count 0 2006.173.21:29:32.53#ibcon#first serial, iclass 7, count 0 2006.173.21:29:32.53#ibcon#enter sib2, iclass 7, count 0 2006.173.21:29:32.53#ibcon#flushed, iclass 7, count 0 2006.173.21:29:32.53#ibcon#about to write, iclass 7, count 0 2006.173.21:29:32.53#ibcon#wrote, iclass 7, count 0 2006.173.21:29:32.53#ibcon#about to read 3, iclass 7, count 0 2006.173.21:29:32.55#ibcon#read 3, iclass 7, count 0 2006.173.21:29:32.55#ibcon#about to read 4, iclass 7, count 0 2006.173.21:29:32.55#ibcon#read 4, iclass 7, count 0 2006.173.21:29:32.55#ibcon#about to read 5, iclass 7, count 0 2006.173.21:29:32.55#ibcon#read 5, iclass 7, count 0 2006.173.21:29:32.55#ibcon#about to read 6, iclass 7, count 0 2006.173.21:29:32.55#ibcon#read 6, iclass 7, count 0 2006.173.21:29:32.55#ibcon#end of sib2, iclass 7, count 0 2006.173.21:29:32.55#ibcon#*mode == 0, iclass 7, count 0 2006.173.21:29:32.55#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.21:29:32.55#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.21:29:32.55#ibcon#*before write, iclass 7, count 0 2006.173.21:29:32.55#ibcon#enter sib2, iclass 7, count 0 2006.173.21:29:32.55#ibcon#flushed, iclass 7, count 0 2006.173.21:29:32.55#ibcon#about to write, iclass 7, count 0 2006.173.21:29:32.55#ibcon#wrote, iclass 7, count 0 2006.173.21:29:32.55#ibcon#about to read 3, iclass 7, count 0 2006.173.21:29:32.59#ibcon#read 3, iclass 7, count 0 2006.173.21:29:32.59#ibcon#about to read 4, iclass 7, count 0 2006.173.21:29:32.59#ibcon#read 4, iclass 7, count 0 2006.173.21:29:32.59#ibcon#about to read 5, iclass 7, count 0 2006.173.21:29:32.59#ibcon#read 5, iclass 7, count 0 2006.173.21:29:32.59#ibcon#about to read 6, iclass 7, count 0 2006.173.21:29:32.59#ibcon#read 6, iclass 7, count 0 2006.173.21:29:32.59#ibcon#end of sib2, iclass 7, count 0 2006.173.21:29:32.59#ibcon#*after write, iclass 7, count 0 2006.173.21:29:32.59#ibcon#*before return 0, iclass 7, count 0 2006.173.21:29:32.59#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.21:29:32.59#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.21:29:32.59#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.21:29:32.59#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.21:29:32.59$vck44/va=2,6 2006.173.21:29:32.59#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.21:29:32.59#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.21:29:32.59#ibcon#ireg 11 cls_cnt 2 2006.173.21:29:32.59#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.21:29:32.65#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.21:29:32.65#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.21:29:32.65#ibcon#enter wrdev, iclass 11, count 2 2006.173.21:29:32.65#ibcon#first serial, iclass 11, count 2 2006.173.21:29:32.65#ibcon#enter sib2, iclass 11, count 2 2006.173.21:29:32.65#ibcon#flushed, iclass 11, count 2 2006.173.21:29:32.65#ibcon#about to write, iclass 11, count 2 2006.173.21:29:32.65#ibcon#wrote, iclass 11, count 2 2006.173.21:29:32.65#ibcon#about to read 3, iclass 11, count 2 2006.173.21:29:32.67#ibcon#read 3, iclass 11, count 2 2006.173.21:29:32.67#ibcon#about to read 4, iclass 11, count 2 2006.173.21:29:32.67#ibcon#read 4, iclass 11, count 2 2006.173.21:29:32.67#ibcon#about to read 5, iclass 11, count 2 2006.173.21:29:32.67#ibcon#read 5, iclass 11, count 2 2006.173.21:29:32.67#ibcon#about to read 6, iclass 11, count 2 2006.173.21:29:32.67#ibcon#read 6, iclass 11, count 2 2006.173.21:29:32.67#ibcon#end of sib2, iclass 11, count 2 2006.173.21:29:32.67#ibcon#*mode == 0, iclass 11, count 2 2006.173.21:29:32.67#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.21:29:32.67#ibcon#[25=AT02-06\r\n] 2006.173.21:29:32.67#ibcon#*before write, iclass 11, count 2 2006.173.21:29:32.67#ibcon#enter sib2, iclass 11, count 2 2006.173.21:29:32.67#ibcon#flushed, iclass 11, count 2 2006.173.21:29:32.67#ibcon#about to write, iclass 11, count 2 2006.173.21:29:32.67#ibcon#wrote, iclass 11, count 2 2006.173.21:29:32.67#ibcon#about to read 3, iclass 11, count 2 2006.173.21:29:32.70#ibcon#read 3, iclass 11, count 2 2006.173.21:29:32.70#ibcon#about to read 4, iclass 11, count 2 2006.173.21:29:32.70#ibcon#read 4, iclass 11, count 2 2006.173.21:29:32.70#ibcon#about to read 5, iclass 11, count 2 2006.173.21:29:32.70#ibcon#read 5, iclass 11, count 2 2006.173.21:29:32.70#ibcon#about to read 6, iclass 11, count 2 2006.173.21:29:32.70#ibcon#read 6, iclass 11, count 2 2006.173.21:29:32.70#ibcon#end of sib2, iclass 11, count 2 2006.173.21:29:32.70#ibcon#*after write, iclass 11, count 2 2006.173.21:29:32.70#ibcon#*before return 0, iclass 11, count 2 2006.173.21:29:32.70#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.21:29:32.70#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.21:29:32.70#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.21:29:32.70#ibcon#ireg 7 cls_cnt 0 2006.173.21:29:32.70#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.21:29:32.82#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.21:29:32.82#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.21:29:32.82#ibcon#enter wrdev, iclass 11, count 0 2006.173.21:29:32.82#ibcon#first serial, iclass 11, count 0 2006.173.21:29:32.82#ibcon#enter sib2, iclass 11, count 0 2006.173.21:29:32.82#ibcon#flushed, iclass 11, count 0 2006.173.21:29:32.82#ibcon#about to write, iclass 11, count 0 2006.173.21:29:32.82#ibcon#wrote, iclass 11, count 0 2006.173.21:29:32.82#ibcon#about to read 3, iclass 11, count 0 2006.173.21:29:32.84#ibcon#read 3, iclass 11, count 0 2006.173.21:29:32.84#ibcon#about to read 4, iclass 11, count 0 2006.173.21:29:32.84#ibcon#read 4, iclass 11, count 0 2006.173.21:29:32.84#ibcon#about to read 5, iclass 11, count 0 2006.173.21:29:32.84#ibcon#read 5, iclass 11, count 0 2006.173.21:29:32.84#ibcon#about to read 6, iclass 11, count 0 2006.173.21:29:32.84#ibcon#read 6, iclass 11, count 0 2006.173.21:29:32.84#ibcon#end of sib2, iclass 11, count 0 2006.173.21:29:32.84#ibcon#*mode == 0, iclass 11, count 0 2006.173.21:29:32.84#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.21:29:32.84#ibcon#[25=USB\r\n] 2006.173.21:29:32.84#ibcon#*before write, iclass 11, count 0 2006.173.21:29:32.84#ibcon#enter sib2, iclass 11, count 0 2006.173.21:29:32.84#ibcon#flushed, iclass 11, count 0 2006.173.21:29:32.84#ibcon#about to write, iclass 11, count 0 2006.173.21:29:32.84#ibcon#wrote, iclass 11, count 0 2006.173.21:29:32.84#ibcon#about to read 3, iclass 11, count 0 2006.173.21:29:32.87#ibcon#read 3, iclass 11, count 0 2006.173.21:29:32.87#ibcon#about to read 4, iclass 11, count 0 2006.173.21:29:32.87#ibcon#read 4, iclass 11, count 0 2006.173.21:29:32.87#ibcon#about to read 5, iclass 11, count 0 2006.173.21:29:32.87#ibcon#read 5, iclass 11, count 0 2006.173.21:29:32.87#ibcon#about to read 6, iclass 11, count 0 2006.173.21:29:32.87#ibcon#read 6, iclass 11, count 0 2006.173.21:29:32.87#ibcon#end of sib2, iclass 11, count 0 2006.173.21:29:32.87#ibcon#*after write, iclass 11, count 0 2006.173.21:29:32.87#ibcon#*before return 0, iclass 11, count 0 2006.173.21:29:32.87#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.21:29:32.87#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.21:29:32.87#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.21:29:32.87#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.21:29:32.87$vck44/valo=3,564.99 2006.173.21:29:32.87#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.21:29:32.87#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.21:29:32.87#ibcon#ireg 17 cls_cnt 0 2006.173.21:29:32.87#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.21:29:32.87#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.21:29:32.87#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.21:29:32.87#ibcon#enter wrdev, iclass 13, count 0 2006.173.21:29:32.87#ibcon#first serial, iclass 13, count 0 2006.173.21:29:32.87#ibcon#enter sib2, iclass 13, count 0 2006.173.21:29:32.87#ibcon#flushed, iclass 13, count 0 2006.173.21:29:32.87#ibcon#about to write, iclass 13, count 0 2006.173.21:29:32.87#ibcon#wrote, iclass 13, count 0 2006.173.21:29:32.87#ibcon#about to read 3, iclass 13, count 0 2006.173.21:29:32.89#ibcon#read 3, iclass 13, count 0 2006.173.21:29:32.89#ibcon#about to read 4, iclass 13, count 0 2006.173.21:29:32.89#ibcon#read 4, iclass 13, count 0 2006.173.21:29:32.89#ibcon#about to read 5, iclass 13, count 0 2006.173.21:29:32.89#ibcon#read 5, iclass 13, count 0 2006.173.21:29:32.89#ibcon#about to read 6, iclass 13, count 0 2006.173.21:29:32.89#ibcon#read 6, iclass 13, count 0 2006.173.21:29:32.89#ibcon#end of sib2, iclass 13, count 0 2006.173.21:29:32.89#ibcon#*mode == 0, iclass 13, count 0 2006.173.21:29:32.89#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.21:29:32.89#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.21:29:32.89#ibcon#*before write, iclass 13, count 0 2006.173.21:29:32.89#ibcon#enter sib2, iclass 13, count 0 2006.173.21:29:32.89#ibcon#flushed, iclass 13, count 0 2006.173.21:29:32.89#ibcon#about to write, iclass 13, count 0 2006.173.21:29:32.89#ibcon#wrote, iclass 13, count 0 2006.173.21:29:32.89#ibcon#about to read 3, iclass 13, count 0 2006.173.21:29:32.93#ibcon#read 3, iclass 13, count 0 2006.173.21:29:32.93#ibcon#about to read 4, iclass 13, count 0 2006.173.21:29:32.93#ibcon#read 4, iclass 13, count 0 2006.173.21:29:32.93#ibcon#about to read 5, iclass 13, count 0 2006.173.21:29:32.93#ibcon#read 5, iclass 13, count 0 2006.173.21:29:32.93#ibcon#about to read 6, iclass 13, count 0 2006.173.21:29:32.93#ibcon#read 6, iclass 13, count 0 2006.173.21:29:32.93#ibcon#end of sib2, iclass 13, count 0 2006.173.21:29:32.93#ibcon#*after write, iclass 13, count 0 2006.173.21:29:32.93#ibcon#*before return 0, iclass 13, count 0 2006.173.21:29:32.93#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.21:29:32.93#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.21:29:32.93#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.21:29:32.93#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.21:29:32.93$vck44/va=3,5 2006.173.21:29:32.93#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.21:29:32.93#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.21:29:32.93#ibcon#ireg 11 cls_cnt 2 2006.173.21:29:32.93#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.21:29:32.99#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.21:29:32.99#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.21:29:32.99#ibcon#enter wrdev, iclass 15, count 2 2006.173.21:29:32.99#ibcon#first serial, iclass 15, count 2 2006.173.21:29:32.99#ibcon#enter sib2, iclass 15, count 2 2006.173.21:29:32.99#ibcon#flushed, iclass 15, count 2 2006.173.21:29:32.99#ibcon#about to write, iclass 15, count 2 2006.173.21:29:32.99#ibcon#wrote, iclass 15, count 2 2006.173.21:29:32.99#ibcon#about to read 3, iclass 15, count 2 2006.173.21:29:33.01#ibcon#read 3, iclass 15, count 2 2006.173.21:29:33.01#ibcon#about to read 4, iclass 15, count 2 2006.173.21:29:33.01#ibcon#read 4, iclass 15, count 2 2006.173.21:29:33.01#ibcon#about to read 5, iclass 15, count 2 2006.173.21:29:33.01#ibcon#read 5, iclass 15, count 2 2006.173.21:29:33.01#ibcon#about to read 6, iclass 15, count 2 2006.173.21:29:33.01#ibcon#read 6, iclass 15, count 2 2006.173.21:29:33.01#ibcon#end of sib2, iclass 15, count 2 2006.173.21:29:33.01#ibcon#*mode == 0, iclass 15, count 2 2006.173.21:29:33.01#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.21:29:33.01#ibcon#[25=AT03-05\r\n] 2006.173.21:29:33.01#ibcon#*before write, iclass 15, count 2 2006.173.21:29:33.01#ibcon#enter sib2, iclass 15, count 2 2006.173.21:29:33.01#ibcon#flushed, iclass 15, count 2 2006.173.21:29:33.01#ibcon#about to write, iclass 15, count 2 2006.173.21:29:33.01#ibcon#wrote, iclass 15, count 2 2006.173.21:29:33.01#ibcon#about to read 3, iclass 15, count 2 2006.173.21:29:33.04#ibcon#read 3, iclass 15, count 2 2006.173.21:29:33.04#ibcon#about to read 4, iclass 15, count 2 2006.173.21:29:33.04#ibcon#read 4, iclass 15, count 2 2006.173.21:29:33.04#ibcon#about to read 5, iclass 15, count 2 2006.173.21:29:33.04#ibcon#read 5, iclass 15, count 2 2006.173.21:29:33.04#ibcon#about to read 6, iclass 15, count 2 2006.173.21:29:33.04#ibcon#read 6, iclass 15, count 2 2006.173.21:29:33.04#ibcon#end of sib2, iclass 15, count 2 2006.173.21:29:33.04#ibcon#*after write, iclass 15, count 2 2006.173.21:29:33.04#ibcon#*before return 0, iclass 15, count 2 2006.173.21:29:33.04#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.21:29:33.04#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.21:29:33.04#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.21:29:33.04#ibcon#ireg 7 cls_cnt 0 2006.173.21:29:33.04#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.21:29:33.16#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.21:29:33.16#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.21:29:33.16#ibcon#enter wrdev, iclass 15, count 0 2006.173.21:29:33.16#ibcon#first serial, iclass 15, count 0 2006.173.21:29:33.16#ibcon#enter sib2, iclass 15, count 0 2006.173.21:29:33.16#ibcon#flushed, iclass 15, count 0 2006.173.21:29:33.16#ibcon#about to write, iclass 15, count 0 2006.173.21:29:33.16#ibcon#wrote, iclass 15, count 0 2006.173.21:29:33.16#ibcon#about to read 3, iclass 15, count 0 2006.173.21:29:33.18#ibcon#read 3, iclass 15, count 0 2006.173.21:29:33.18#ibcon#about to read 4, iclass 15, count 0 2006.173.21:29:33.18#ibcon#read 4, iclass 15, count 0 2006.173.21:29:33.18#ibcon#about to read 5, iclass 15, count 0 2006.173.21:29:33.18#ibcon#read 5, iclass 15, count 0 2006.173.21:29:33.18#ibcon#about to read 6, iclass 15, count 0 2006.173.21:29:33.18#ibcon#read 6, iclass 15, count 0 2006.173.21:29:33.18#ibcon#end of sib2, iclass 15, count 0 2006.173.21:29:33.18#ibcon#*mode == 0, iclass 15, count 0 2006.173.21:29:33.18#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.21:29:33.18#ibcon#[25=USB\r\n] 2006.173.21:29:33.18#ibcon#*before write, iclass 15, count 0 2006.173.21:29:33.18#ibcon#enter sib2, iclass 15, count 0 2006.173.21:29:33.18#ibcon#flushed, iclass 15, count 0 2006.173.21:29:33.18#ibcon#about to write, iclass 15, count 0 2006.173.21:29:33.18#ibcon#wrote, iclass 15, count 0 2006.173.21:29:33.18#ibcon#about to read 3, iclass 15, count 0 2006.173.21:29:33.21#ibcon#read 3, iclass 15, count 0 2006.173.21:29:33.21#ibcon#about to read 4, iclass 15, count 0 2006.173.21:29:33.21#ibcon#read 4, iclass 15, count 0 2006.173.21:29:33.21#ibcon#about to read 5, iclass 15, count 0 2006.173.21:29:33.21#ibcon#read 5, iclass 15, count 0 2006.173.21:29:33.21#ibcon#about to read 6, iclass 15, count 0 2006.173.21:29:33.21#ibcon#read 6, iclass 15, count 0 2006.173.21:29:33.21#ibcon#end of sib2, iclass 15, count 0 2006.173.21:29:33.21#ibcon#*after write, iclass 15, count 0 2006.173.21:29:33.21#ibcon#*before return 0, iclass 15, count 0 2006.173.21:29:33.21#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.21:29:33.21#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.21:29:33.21#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.21:29:33.21#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.21:29:33.21$vck44/valo=4,624.99 2006.173.21:29:33.21#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.21:29:33.21#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.21:29:33.21#ibcon#ireg 17 cls_cnt 0 2006.173.21:29:33.21#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.21:29:33.21#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.21:29:33.21#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.21:29:33.21#ibcon#enter wrdev, iclass 17, count 0 2006.173.21:29:33.21#ibcon#first serial, iclass 17, count 0 2006.173.21:29:33.21#ibcon#enter sib2, iclass 17, count 0 2006.173.21:29:33.21#ibcon#flushed, iclass 17, count 0 2006.173.21:29:33.21#ibcon#about to write, iclass 17, count 0 2006.173.21:29:33.21#ibcon#wrote, iclass 17, count 0 2006.173.21:29:33.21#ibcon#about to read 3, iclass 17, count 0 2006.173.21:29:33.23#ibcon#read 3, iclass 17, count 0 2006.173.21:29:33.23#ibcon#about to read 4, iclass 17, count 0 2006.173.21:29:33.23#ibcon#read 4, iclass 17, count 0 2006.173.21:29:33.23#ibcon#about to read 5, iclass 17, count 0 2006.173.21:29:33.23#ibcon#read 5, iclass 17, count 0 2006.173.21:29:33.23#ibcon#about to read 6, iclass 17, count 0 2006.173.21:29:33.23#ibcon#read 6, iclass 17, count 0 2006.173.21:29:33.23#ibcon#end of sib2, iclass 17, count 0 2006.173.21:29:33.23#ibcon#*mode == 0, iclass 17, count 0 2006.173.21:29:33.23#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.21:29:33.23#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.21:29:33.23#ibcon#*before write, iclass 17, count 0 2006.173.21:29:33.23#ibcon#enter sib2, iclass 17, count 0 2006.173.21:29:33.23#ibcon#flushed, iclass 17, count 0 2006.173.21:29:33.23#ibcon#about to write, iclass 17, count 0 2006.173.21:29:33.23#ibcon#wrote, iclass 17, count 0 2006.173.21:29:33.23#ibcon#about to read 3, iclass 17, count 0 2006.173.21:29:33.27#ibcon#read 3, iclass 17, count 0 2006.173.21:29:33.27#ibcon#about to read 4, iclass 17, count 0 2006.173.21:29:33.27#ibcon#read 4, iclass 17, count 0 2006.173.21:29:33.27#ibcon#about to read 5, iclass 17, count 0 2006.173.21:29:33.27#ibcon#read 5, iclass 17, count 0 2006.173.21:29:33.27#ibcon#about to read 6, iclass 17, count 0 2006.173.21:29:33.27#ibcon#read 6, iclass 17, count 0 2006.173.21:29:33.27#ibcon#end of sib2, iclass 17, count 0 2006.173.21:29:33.27#ibcon#*after write, iclass 17, count 0 2006.173.21:29:33.27#ibcon#*before return 0, iclass 17, count 0 2006.173.21:29:33.27#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.21:29:33.27#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.21:29:33.27#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.21:29:33.27#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.21:29:33.27$vck44/va=4,6 2006.173.21:29:33.27#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.21:29:33.27#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.21:29:33.27#ibcon#ireg 11 cls_cnt 2 2006.173.21:29:33.27#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.21:29:33.33#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.21:29:33.33#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.21:29:33.33#ibcon#enter wrdev, iclass 19, count 2 2006.173.21:29:33.33#ibcon#first serial, iclass 19, count 2 2006.173.21:29:33.33#ibcon#enter sib2, iclass 19, count 2 2006.173.21:29:33.33#ibcon#flushed, iclass 19, count 2 2006.173.21:29:33.33#ibcon#about to write, iclass 19, count 2 2006.173.21:29:33.33#ibcon#wrote, iclass 19, count 2 2006.173.21:29:33.33#ibcon#about to read 3, iclass 19, count 2 2006.173.21:29:33.35#ibcon#read 3, iclass 19, count 2 2006.173.21:29:33.35#ibcon#about to read 4, iclass 19, count 2 2006.173.21:29:33.35#ibcon#read 4, iclass 19, count 2 2006.173.21:29:33.35#ibcon#about to read 5, iclass 19, count 2 2006.173.21:29:33.35#ibcon#read 5, iclass 19, count 2 2006.173.21:29:33.35#ibcon#about to read 6, iclass 19, count 2 2006.173.21:29:33.35#ibcon#read 6, iclass 19, count 2 2006.173.21:29:33.35#ibcon#end of sib2, iclass 19, count 2 2006.173.21:29:33.35#ibcon#*mode == 0, iclass 19, count 2 2006.173.21:29:33.35#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.21:29:33.35#ibcon#[25=AT04-06\r\n] 2006.173.21:29:33.35#ibcon#*before write, iclass 19, count 2 2006.173.21:29:33.35#ibcon#enter sib2, iclass 19, count 2 2006.173.21:29:33.35#ibcon#flushed, iclass 19, count 2 2006.173.21:29:33.35#ibcon#about to write, iclass 19, count 2 2006.173.21:29:33.35#ibcon#wrote, iclass 19, count 2 2006.173.21:29:33.35#ibcon#about to read 3, iclass 19, count 2 2006.173.21:29:33.38#ibcon#read 3, iclass 19, count 2 2006.173.21:29:33.38#ibcon#about to read 4, iclass 19, count 2 2006.173.21:29:33.38#ibcon#read 4, iclass 19, count 2 2006.173.21:29:33.38#ibcon#about to read 5, iclass 19, count 2 2006.173.21:29:33.38#ibcon#read 5, iclass 19, count 2 2006.173.21:29:33.38#ibcon#about to read 6, iclass 19, count 2 2006.173.21:29:33.38#ibcon#read 6, iclass 19, count 2 2006.173.21:29:33.38#ibcon#end of sib2, iclass 19, count 2 2006.173.21:29:33.38#ibcon#*after write, iclass 19, count 2 2006.173.21:29:33.38#ibcon#*before return 0, iclass 19, count 2 2006.173.21:29:33.38#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.21:29:33.38#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.21:29:33.38#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.21:29:33.38#ibcon#ireg 7 cls_cnt 0 2006.173.21:29:33.38#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.21:29:33.50#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.21:29:33.50#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.21:29:33.50#ibcon#enter wrdev, iclass 19, count 0 2006.173.21:29:33.50#ibcon#first serial, iclass 19, count 0 2006.173.21:29:33.50#ibcon#enter sib2, iclass 19, count 0 2006.173.21:29:33.50#ibcon#flushed, iclass 19, count 0 2006.173.21:29:33.50#ibcon#about to write, iclass 19, count 0 2006.173.21:29:33.50#ibcon#wrote, iclass 19, count 0 2006.173.21:29:33.50#ibcon#about to read 3, iclass 19, count 0 2006.173.21:29:33.52#ibcon#read 3, iclass 19, count 0 2006.173.21:29:33.52#ibcon#about to read 4, iclass 19, count 0 2006.173.21:29:33.52#ibcon#read 4, iclass 19, count 0 2006.173.21:29:33.52#ibcon#about to read 5, iclass 19, count 0 2006.173.21:29:33.52#ibcon#read 5, iclass 19, count 0 2006.173.21:29:33.52#ibcon#about to read 6, iclass 19, count 0 2006.173.21:29:33.52#ibcon#read 6, iclass 19, count 0 2006.173.21:29:33.52#ibcon#end of sib2, iclass 19, count 0 2006.173.21:29:33.52#ibcon#*mode == 0, iclass 19, count 0 2006.173.21:29:33.52#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.21:29:33.52#ibcon#[25=USB\r\n] 2006.173.21:29:33.52#ibcon#*before write, iclass 19, count 0 2006.173.21:29:33.52#ibcon#enter sib2, iclass 19, count 0 2006.173.21:29:33.52#ibcon#flushed, iclass 19, count 0 2006.173.21:29:33.52#ibcon#about to write, iclass 19, count 0 2006.173.21:29:33.52#ibcon#wrote, iclass 19, count 0 2006.173.21:29:33.52#ibcon#about to read 3, iclass 19, count 0 2006.173.21:29:33.55#ibcon#read 3, iclass 19, count 0 2006.173.21:29:33.55#ibcon#about to read 4, iclass 19, count 0 2006.173.21:29:33.55#ibcon#read 4, iclass 19, count 0 2006.173.21:29:33.55#ibcon#about to read 5, iclass 19, count 0 2006.173.21:29:33.55#ibcon#read 5, iclass 19, count 0 2006.173.21:29:33.55#ibcon#about to read 6, iclass 19, count 0 2006.173.21:29:33.55#ibcon#read 6, iclass 19, count 0 2006.173.21:29:33.55#ibcon#end of sib2, iclass 19, count 0 2006.173.21:29:33.55#ibcon#*after write, iclass 19, count 0 2006.173.21:29:33.55#ibcon#*before return 0, iclass 19, count 0 2006.173.21:29:33.55#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.21:29:33.55#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.21:29:33.55#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.21:29:33.55#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.21:29:33.55$vck44/valo=5,734.99 2006.173.21:29:33.55#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.21:29:33.55#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.21:29:33.55#ibcon#ireg 17 cls_cnt 0 2006.173.21:29:33.55#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.21:29:33.55#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.21:29:33.55#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.21:29:33.55#ibcon#enter wrdev, iclass 21, count 0 2006.173.21:29:33.55#ibcon#first serial, iclass 21, count 0 2006.173.21:29:33.55#ibcon#enter sib2, iclass 21, count 0 2006.173.21:29:33.55#ibcon#flushed, iclass 21, count 0 2006.173.21:29:33.55#ibcon#about to write, iclass 21, count 0 2006.173.21:29:33.55#ibcon#wrote, iclass 21, count 0 2006.173.21:29:33.55#ibcon#about to read 3, iclass 21, count 0 2006.173.21:29:33.57#ibcon#read 3, iclass 21, count 0 2006.173.21:29:33.57#ibcon#about to read 4, iclass 21, count 0 2006.173.21:29:33.57#ibcon#read 4, iclass 21, count 0 2006.173.21:29:33.57#ibcon#about to read 5, iclass 21, count 0 2006.173.21:29:33.57#ibcon#read 5, iclass 21, count 0 2006.173.21:29:33.57#ibcon#about to read 6, iclass 21, count 0 2006.173.21:29:33.57#ibcon#read 6, iclass 21, count 0 2006.173.21:29:33.57#ibcon#end of sib2, iclass 21, count 0 2006.173.21:29:33.57#ibcon#*mode == 0, iclass 21, count 0 2006.173.21:29:33.57#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.21:29:33.57#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.21:29:33.57#ibcon#*before write, iclass 21, count 0 2006.173.21:29:33.57#ibcon#enter sib2, iclass 21, count 0 2006.173.21:29:33.57#ibcon#flushed, iclass 21, count 0 2006.173.21:29:33.57#ibcon#about to write, iclass 21, count 0 2006.173.21:29:33.57#ibcon#wrote, iclass 21, count 0 2006.173.21:29:33.57#ibcon#about to read 3, iclass 21, count 0 2006.173.21:29:33.61#ibcon#read 3, iclass 21, count 0 2006.173.21:29:33.61#ibcon#about to read 4, iclass 21, count 0 2006.173.21:29:33.61#ibcon#read 4, iclass 21, count 0 2006.173.21:29:33.61#ibcon#about to read 5, iclass 21, count 0 2006.173.21:29:33.61#ibcon#read 5, iclass 21, count 0 2006.173.21:29:33.61#ibcon#about to read 6, iclass 21, count 0 2006.173.21:29:33.61#ibcon#read 6, iclass 21, count 0 2006.173.21:29:33.61#ibcon#end of sib2, iclass 21, count 0 2006.173.21:29:33.61#ibcon#*after write, iclass 21, count 0 2006.173.21:29:33.61#ibcon#*before return 0, iclass 21, count 0 2006.173.21:29:33.61#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.21:29:33.61#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.21:29:33.61#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.21:29:33.61#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.21:29:33.61$vck44/va=5,4 2006.173.21:29:33.61#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.21:29:33.61#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.21:29:33.61#ibcon#ireg 11 cls_cnt 2 2006.173.21:29:33.61#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.21:29:33.67#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.21:29:33.67#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.21:29:33.67#ibcon#enter wrdev, iclass 23, count 2 2006.173.21:29:33.67#ibcon#first serial, iclass 23, count 2 2006.173.21:29:33.67#ibcon#enter sib2, iclass 23, count 2 2006.173.21:29:33.67#ibcon#flushed, iclass 23, count 2 2006.173.21:29:33.67#ibcon#about to write, iclass 23, count 2 2006.173.21:29:33.67#ibcon#wrote, iclass 23, count 2 2006.173.21:29:33.67#ibcon#about to read 3, iclass 23, count 2 2006.173.21:29:33.69#ibcon#read 3, iclass 23, count 2 2006.173.21:29:33.69#ibcon#about to read 4, iclass 23, count 2 2006.173.21:29:33.69#ibcon#read 4, iclass 23, count 2 2006.173.21:29:33.69#ibcon#about to read 5, iclass 23, count 2 2006.173.21:29:33.69#ibcon#read 5, iclass 23, count 2 2006.173.21:29:33.69#ibcon#about to read 6, iclass 23, count 2 2006.173.21:29:33.69#ibcon#read 6, iclass 23, count 2 2006.173.21:29:33.69#ibcon#end of sib2, iclass 23, count 2 2006.173.21:29:33.69#ibcon#*mode == 0, iclass 23, count 2 2006.173.21:29:33.69#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.21:29:33.69#ibcon#[25=AT05-04\r\n] 2006.173.21:29:33.69#ibcon#*before write, iclass 23, count 2 2006.173.21:29:33.69#ibcon#enter sib2, iclass 23, count 2 2006.173.21:29:33.69#ibcon#flushed, iclass 23, count 2 2006.173.21:29:33.69#ibcon#about to write, iclass 23, count 2 2006.173.21:29:33.69#ibcon#wrote, iclass 23, count 2 2006.173.21:29:33.69#ibcon#about to read 3, iclass 23, count 2 2006.173.21:29:33.72#ibcon#read 3, iclass 23, count 2 2006.173.21:29:33.72#ibcon#about to read 4, iclass 23, count 2 2006.173.21:29:33.72#ibcon#read 4, iclass 23, count 2 2006.173.21:29:33.72#ibcon#about to read 5, iclass 23, count 2 2006.173.21:29:33.72#ibcon#read 5, iclass 23, count 2 2006.173.21:29:33.72#ibcon#about to read 6, iclass 23, count 2 2006.173.21:29:33.72#ibcon#read 6, iclass 23, count 2 2006.173.21:29:33.72#ibcon#end of sib2, iclass 23, count 2 2006.173.21:29:33.72#ibcon#*after write, iclass 23, count 2 2006.173.21:29:33.72#ibcon#*before return 0, iclass 23, count 2 2006.173.21:29:33.72#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.21:29:33.72#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.21:29:33.72#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.21:29:33.72#ibcon#ireg 7 cls_cnt 0 2006.173.21:29:33.72#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.21:29:33.84#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.21:29:33.84#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.21:29:33.84#ibcon#enter wrdev, iclass 23, count 0 2006.173.21:29:33.84#ibcon#first serial, iclass 23, count 0 2006.173.21:29:33.84#ibcon#enter sib2, iclass 23, count 0 2006.173.21:29:33.84#ibcon#flushed, iclass 23, count 0 2006.173.21:29:33.84#ibcon#about to write, iclass 23, count 0 2006.173.21:29:33.84#ibcon#wrote, iclass 23, count 0 2006.173.21:29:33.84#ibcon#about to read 3, iclass 23, count 0 2006.173.21:29:33.86#ibcon#read 3, iclass 23, count 0 2006.173.21:29:33.86#ibcon#about to read 4, iclass 23, count 0 2006.173.21:29:33.86#ibcon#read 4, iclass 23, count 0 2006.173.21:29:33.86#ibcon#about to read 5, iclass 23, count 0 2006.173.21:29:33.86#ibcon#read 5, iclass 23, count 0 2006.173.21:29:33.86#ibcon#about to read 6, iclass 23, count 0 2006.173.21:29:33.86#ibcon#read 6, iclass 23, count 0 2006.173.21:29:33.86#ibcon#end of sib2, iclass 23, count 0 2006.173.21:29:33.86#ibcon#*mode == 0, iclass 23, count 0 2006.173.21:29:33.86#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.21:29:33.86#ibcon#[25=USB\r\n] 2006.173.21:29:33.86#ibcon#*before write, iclass 23, count 0 2006.173.21:29:33.86#ibcon#enter sib2, iclass 23, count 0 2006.173.21:29:33.86#ibcon#flushed, iclass 23, count 0 2006.173.21:29:33.86#ibcon#about to write, iclass 23, count 0 2006.173.21:29:33.86#ibcon#wrote, iclass 23, count 0 2006.173.21:29:33.86#ibcon#about to read 3, iclass 23, count 0 2006.173.21:29:33.89#ibcon#read 3, iclass 23, count 0 2006.173.21:29:33.89#ibcon#about to read 4, iclass 23, count 0 2006.173.21:29:33.89#ibcon#read 4, iclass 23, count 0 2006.173.21:29:33.89#ibcon#about to read 5, iclass 23, count 0 2006.173.21:29:33.89#ibcon#read 5, iclass 23, count 0 2006.173.21:29:33.89#ibcon#about to read 6, iclass 23, count 0 2006.173.21:29:33.89#ibcon#read 6, iclass 23, count 0 2006.173.21:29:33.89#ibcon#end of sib2, iclass 23, count 0 2006.173.21:29:33.89#ibcon#*after write, iclass 23, count 0 2006.173.21:29:33.89#ibcon#*before return 0, iclass 23, count 0 2006.173.21:29:33.89#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.21:29:33.89#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.21:29:33.89#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.21:29:33.89#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.21:29:33.89$vck44/valo=6,814.99 2006.173.21:29:33.89#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.21:29:33.89#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.21:29:33.89#ibcon#ireg 17 cls_cnt 0 2006.173.21:29:33.89#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.21:29:33.89#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.21:29:33.89#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.21:29:33.89#ibcon#enter wrdev, iclass 25, count 0 2006.173.21:29:33.89#ibcon#first serial, iclass 25, count 0 2006.173.21:29:33.89#ibcon#enter sib2, iclass 25, count 0 2006.173.21:29:33.89#ibcon#flushed, iclass 25, count 0 2006.173.21:29:33.89#ibcon#about to write, iclass 25, count 0 2006.173.21:29:33.89#ibcon#wrote, iclass 25, count 0 2006.173.21:29:33.89#ibcon#about to read 3, iclass 25, count 0 2006.173.21:29:33.91#ibcon#read 3, iclass 25, count 0 2006.173.21:29:33.91#ibcon#about to read 4, iclass 25, count 0 2006.173.21:29:33.91#ibcon#read 4, iclass 25, count 0 2006.173.21:29:33.91#ibcon#about to read 5, iclass 25, count 0 2006.173.21:29:33.91#ibcon#read 5, iclass 25, count 0 2006.173.21:29:33.91#ibcon#about to read 6, iclass 25, count 0 2006.173.21:29:33.91#ibcon#read 6, iclass 25, count 0 2006.173.21:29:33.91#ibcon#end of sib2, iclass 25, count 0 2006.173.21:29:33.91#ibcon#*mode == 0, iclass 25, count 0 2006.173.21:29:33.91#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.21:29:33.91#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.21:29:33.91#ibcon#*before write, iclass 25, count 0 2006.173.21:29:33.91#ibcon#enter sib2, iclass 25, count 0 2006.173.21:29:33.91#ibcon#flushed, iclass 25, count 0 2006.173.21:29:33.91#ibcon#about to write, iclass 25, count 0 2006.173.21:29:33.91#ibcon#wrote, iclass 25, count 0 2006.173.21:29:33.91#ibcon#about to read 3, iclass 25, count 0 2006.173.21:29:33.95#ibcon#read 3, iclass 25, count 0 2006.173.21:29:33.95#ibcon#about to read 4, iclass 25, count 0 2006.173.21:29:33.95#ibcon#read 4, iclass 25, count 0 2006.173.21:29:33.95#ibcon#about to read 5, iclass 25, count 0 2006.173.21:29:33.95#ibcon#read 5, iclass 25, count 0 2006.173.21:29:33.95#ibcon#about to read 6, iclass 25, count 0 2006.173.21:29:33.95#ibcon#read 6, iclass 25, count 0 2006.173.21:29:33.95#ibcon#end of sib2, iclass 25, count 0 2006.173.21:29:33.95#ibcon#*after write, iclass 25, count 0 2006.173.21:29:33.95#ibcon#*before return 0, iclass 25, count 0 2006.173.21:29:33.95#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.21:29:33.95#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.21:29:33.95#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.21:29:33.95#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.21:29:33.95$vck44/va=6,3 2006.173.21:29:33.95#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.21:29:33.95#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.21:29:33.95#ibcon#ireg 11 cls_cnt 2 2006.173.21:29:33.95#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.21:29:34.01#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.21:29:34.01#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.21:29:34.01#ibcon#enter wrdev, iclass 27, count 2 2006.173.21:29:34.01#ibcon#first serial, iclass 27, count 2 2006.173.21:29:34.01#ibcon#enter sib2, iclass 27, count 2 2006.173.21:29:34.01#ibcon#flushed, iclass 27, count 2 2006.173.21:29:34.01#ibcon#about to write, iclass 27, count 2 2006.173.21:29:34.01#ibcon#wrote, iclass 27, count 2 2006.173.21:29:34.01#ibcon#about to read 3, iclass 27, count 2 2006.173.21:29:34.03#ibcon#read 3, iclass 27, count 2 2006.173.21:29:34.03#ibcon#about to read 4, iclass 27, count 2 2006.173.21:29:34.03#ibcon#read 4, iclass 27, count 2 2006.173.21:29:34.03#ibcon#about to read 5, iclass 27, count 2 2006.173.21:29:34.03#ibcon#read 5, iclass 27, count 2 2006.173.21:29:34.03#ibcon#about to read 6, iclass 27, count 2 2006.173.21:29:34.03#ibcon#read 6, iclass 27, count 2 2006.173.21:29:34.03#ibcon#end of sib2, iclass 27, count 2 2006.173.21:29:34.03#ibcon#*mode == 0, iclass 27, count 2 2006.173.21:29:34.03#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.21:29:34.03#ibcon#[25=AT06-03\r\n] 2006.173.21:29:34.03#ibcon#*before write, iclass 27, count 2 2006.173.21:29:34.03#ibcon#enter sib2, iclass 27, count 2 2006.173.21:29:34.03#ibcon#flushed, iclass 27, count 2 2006.173.21:29:34.03#ibcon#about to write, iclass 27, count 2 2006.173.21:29:34.03#ibcon#wrote, iclass 27, count 2 2006.173.21:29:34.03#ibcon#about to read 3, iclass 27, count 2 2006.173.21:29:34.06#ibcon#read 3, iclass 27, count 2 2006.173.21:29:34.06#ibcon#about to read 4, iclass 27, count 2 2006.173.21:29:34.06#ibcon#read 4, iclass 27, count 2 2006.173.21:29:34.06#ibcon#about to read 5, iclass 27, count 2 2006.173.21:29:34.06#ibcon#read 5, iclass 27, count 2 2006.173.21:29:34.06#ibcon#about to read 6, iclass 27, count 2 2006.173.21:29:34.06#ibcon#read 6, iclass 27, count 2 2006.173.21:29:34.06#ibcon#end of sib2, iclass 27, count 2 2006.173.21:29:34.06#ibcon#*after write, iclass 27, count 2 2006.173.21:29:34.06#ibcon#*before return 0, iclass 27, count 2 2006.173.21:29:34.06#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.21:29:34.06#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.21:29:34.06#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.21:29:34.06#ibcon#ireg 7 cls_cnt 0 2006.173.21:29:34.06#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.21:29:34.18#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.21:29:34.18#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.21:29:34.18#ibcon#enter wrdev, iclass 27, count 0 2006.173.21:29:34.18#ibcon#first serial, iclass 27, count 0 2006.173.21:29:34.18#ibcon#enter sib2, iclass 27, count 0 2006.173.21:29:34.18#ibcon#flushed, iclass 27, count 0 2006.173.21:29:34.18#ibcon#about to write, iclass 27, count 0 2006.173.21:29:34.18#ibcon#wrote, iclass 27, count 0 2006.173.21:29:34.18#ibcon#about to read 3, iclass 27, count 0 2006.173.21:29:34.20#ibcon#read 3, iclass 27, count 0 2006.173.21:29:34.20#ibcon#about to read 4, iclass 27, count 0 2006.173.21:29:34.20#ibcon#read 4, iclass 27, count 0 2006.173.21:29:34.20#ibcon#about to read 5, iclass 27, count 0 2006.173.21:29:34.20#ibcon#read 5, iclass 27, count 0 2006.173.21:29:34.20#ibcon#about to read 6, iclass 27, count 0 2006.173.21:29:34.20#ibcon#read 6, iclass 27, count 0 2006.173.21:29:34.20#ibcon#end of sib2, iclass 27, count 0 2006.173.21:29:34.20#ibcon#*mode == 0, iclass 27, count 0 2006.173.21:29:34.20#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.21:29:34.20#ibcon#[25=USB\r\n] 2006.173.21:29:34.20#ibcon#*before write, iclass 27, count 0 2006.173.21:29:34.20#ibcon#enter sib2, iclass 27, count 0 2006.173.21:29:34.20#ibcon#flushed, iclass 27, count 0 2006.173.21:29:34.20#ibcon#about to write, iclass 27, count 0 2006.173.21:29:34.20#ibcon#wrote, iclass 27, count 0 2006.173.21:29:34.20#ibcon#about to read 3, iclass 27, count 0 2006.173.21:29:34.23#ibcon#read 3, iclass 27, count 0 2006.173.21:29:34.23#ibcon#about to read 4, iclass 27, count 0 2006.173.21:29:34.23#ibcon#read 4, iclass 27, count 0 2006.173.21:29:34.23#ibcon#about to read 5, iclass 27, count 0 2006.173.21:29:34.23#ibcon#read 5, iclass 27, count 0 2006.173.21:29:34.23#ibcon#about to read 6, iclass 27, count 0 2006.173.21:29:34.23#ibcon#read 6, iclass 27, count 0 2006.173.21:29:34.23#ibcon#end of sib2, iclass 27, count 0 2006.173.21:29:34.23#ibcon#*after write, iclass 27, count 0 2006.173.21:29:34.23#ibcon#*before return 0, iclass 27, count 0 2006.173.21:29:34.23#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.21:29:34.23#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.21:29:34.23#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.21:29:34.23#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.21:29:34.23$vck44/valo=7,864.99 2006.173.21:29:34.23#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.21:29:34.23#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.21:29:34.23#ibcon#ireg 17 cls_cnt 0 2006.173.21:29:34.23#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.21:29:34.23#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.21:29:34.23#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.21:29:34.23#ibcon#enter wrdev, iclass 29, count 0 2006.173.21:29:34.23#ibcon#first serial, iclass 29, count 0 2006.173.21:29:34.23#ibcon#enter sib2, iclass 29, count 0 2006.173.21:29:34.23#ibcon#flushed, iclass 29, count 0 2006.173.21:29:34.23#ibcon#about to write, iclass 29, count 0 2006.173.21:29:34.23#ibcon#wrote, iclass 29, count 0 2006.173.21:29:34.23#ibcon#about to read 3, iclass 29, count 0 2006.173.21:29:34.25#ibcon#read 3, iclass 29, count 0 2006.173.21:29:34.25#ibcon#about to read 4, iclass 29, count 0 2006.173.21:29:34.25#ibcon#read 4, iclass 29, count 0 2006.173.21:29:34.25#ibcon#about to read 5, iclass 29, count 0 2006.173.21:29:34.25#ibcon#read 5, iclass 29, count 0 2006.173.21:29:34.25#ibcon#about to read 6, iclass 29, count 0 2006.173.21:29:34.25#ibcon#read 6, iclass 29, count 0 2006.173.21:29:34.25#ibcon#end of sib2, iclass 29, count 0 2006.173.21:29:34.25#ibcon#*mode == 0, iclass 29, count 0 2006.173.21:29:34.25#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.21:29:34.25#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.21:29:34.25#ibcon#*before write, iclass 29, count 0 2006.173.21:29:34.25#ibcon#enter sib2, iclass 29, count 0 2006.173.21:29:34.25#ibcon#flushed, iclass 29, count 0 2006.173.21:29:34.25#ibcon#about to write, iclass 29, count 0 2006.173.21:29:34.25#ibcon#wrote, iclass 29, count 0 2006.173.21:29:34.25#ibcon#about to read 3, iclass 29, count 0 2006.173.21:29:34.29#ibcon#read 3, iclass 29, count 0 2006.173.21:29:34.29#ibcon#about to read 4, iclass 29, count 0 2006.173.21:29:34.29#ibcon#read 4, iclass 29, count 0 2006.173.21:29:34.29#ibcon#about to read 5, iclass 29, count 0 2006.173.21:29:34.29#ibcon#read 5, iclass 29, count 0 2006.173.21:29:34.29#ibcon#about to read 6, iclass 29, count 0 2006.173.21:29:34.29#ibcon#read 6, iclass 29, count 0 2006.173.21:29:34.29#ibcon#end of sib2, iclass 29, count 0 2006.173.21:29:34.29#ibcon#*after write, iclass 29, count 0 2006.173.21:29:34.29#ibcon#*before return 0, iclass 29, count 0 2006.173.21:29:34.29#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.21:29:34.29#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.21:29:34.29#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.21:29:34.29#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.21:29:34.29$vck44/va=7,4 2006.173.21:29:34.29#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.21:29:34.29#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.21:29:34.29#ibcon#ireg 11 cls_cnt 2 2006.173.21:29:34.29#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.21:29:34.35#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.21:29:34.35#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.21:29:34.35#ibcon#enter wrdev, iclass 31, count 2 2006.173.21:29:34.35#ibcon#first serial, iclass 31, count 2 2006.173.21:29:34.35#ibcon#enter sib2, iclass 31, count 2 2006.173.21:29:34.35#ibcon#flushed, iclass 31, count 2 2006.173.21:29:34.35#ibcon#about to write, iclass 31, count 2 2006.173.21:29:34.35#ibcon#wrote, iclass 31, count 2 2006.173.21:29:34.35#ibcon#about to read 3, iclass 31, count 2 2006.173.21:29:34.37#ibcon#read 3, iclass 31, count 2 2006.173.21:29:34.37#ibcon#about to read 4, iclass 31, count 2 2006.173.21:29:34.37#ibcon#read 4, iclass 31, count 2 2006.173.21:29:34.37#ibcon#about to read 5, iclass 31, count 2 2006.173.21:29:34.37#ibcon#read 5, iclass 31, count 2 2006.173.21:29:34.37#ibcon#about to read 6, iclass 31, count 2 2006.173.21:29:34.37#ibcon#read 6, iclass 31, count 2 2006.173.21:29:34.37#ibcon#end of sib2, iclass 31, count 2 2006.173.21:29:34.37#ibcon#*mode == 0, iclass 31, count 2 2006.173.21:29:34.37#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.21:29:34.37#ibcon#[25=AT07-04\r\n] 2006.173.21:29:34.37#ibcon#*before write, iclass 31, count 2 2006.173.21:29:34.37#ibcon#enter sib2, iclass 31, count 2 2006.173.21:29:34.37#ibcon#flushed, iclass 31, count 2 2006.173.21:29:34.37#ibcon#about to write, iclass 31, count 2 2006.173.21:29:34.37#ibcon#wrote, iclass 31, count 2 2006.173.21:29:34.37#ibcon#about to read 3, iclass 31, count 2 2006.173.21:29:34.40#ibcon#read 3, iclass 31, count 2 2006.173.21:29:34.40#ibcon#about to read 4, iclass 31, count 2 2006.173.21:29:34.40#ibcon#read 4, iclass 31, count 2 2006.173.21:29:34.40#ibcon#about to read 5, iclass 31, count 2 2006.173.21:29:34.40#ibcon#read 5, iclass 31, count 2 2006.173.21:29:34.40#ibcon#about to read 6, iclass 31, count 2 2006.173.21:29:34.40#ibcon#read 6, iclass 31, count 2 2006.173.21:29:34.40#ibcon#end of sib2, iclass 31, count 2 2006.173.21:29:34.40#ibcon#*after write, iclass 31, count 2 2006.173.21:29:34.40#ibcon#*before return 0, iclass 31, count 2 2006.173.21:29:34.40#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.21:29:34.40#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.21:29:34.40#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.21:29:34.40#ibcon#ireg 7 cls_cnt 0 2006.173.21:29:34.40#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.21:29:34.52#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.21:29:34.52#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.21:29:34.52#ibcon#enter wrdev, iclass 31, count 0 2006.173.21:29:34.52#ibcon#first serial, iclass 31, count 0 2006.173.21:29:34.52#ibcon#enter sib2, iclass 31, count 0 2006.173.21:29:34.52#ibcon#flushed, iclass 31, count 0 2006.173.21:29:34.52#ibcon#about to write, iclass 31, count 0 2006.173.21:29:34.52#ibcon#wrote, iclass 31, count 0 2006.173.21:29:34.52#ibcon#about to read 3, iclass 31, count 0 2006.173.21:29:34.54#ibcon#read 3, iclass 31, count 0 2006.173.21:29:34.54#ibcon#about to read 4, iclass 31, count 0 2006.173.21:29:34.54#ibcon#read 4, iclass 31, count 0 2006.173.21:29:34.54#ibcon#about to read 5, iclass 31, count 0 2006.173.21:29:34.54#ibcon#read 5, iclass 31, count 0 2006.173.21:29:34.54#ibcon#about to read 6, iclass 31, count 0 2006.173.21:29:34.54#ibcon#read 6, iclass 31, count 0 2006.173.21:29:34.54#ibcon#end of sib2, iclass 31, count 0 2006.173.21:29:34.54#ibcon#*mode == 0, iclass 31, count 0 2006.173.21:29:34.54#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.21:29:34.54#ibcon#[25=USB\r\n] 2006.173.21:29:34.54#ibcon#*before write, iclass 31, count 0 2006.173.21:29:34.54#ibcon#enter sib2, iclass 31, count 0 2006.173.21:29:34.54#ibcon#flushed, iclass 31, count 0 2006.173.21:29:34.54#ibcon#about to write, iclass 31, count 0 2006.173.21:29:34.54#ibcon#wrote, iclass 31, count 0 2006.173.21:29:34.54#ibcon#about to read 3, iclass 31, count 0 2006.173.21:29:34.57#ibcon#read 3, iclass 31, count 0 2006.173.21:29:34.57#ibcon#about to read 4, iclass 31, count 0 2006.173.21:29:34.57#ibcon#read 4, iclass 31, count 0 2006.173.21:29:34.57#ibcon#about to read 5, iclass 31, count 0 2006.173.21:29:34.57#ibcon#read 5, iclass 31, count 0 2006.173.21:29:34.57#ibcon#about to read 6, iclass 31, count 0 2006.173.21:29:34.57#ibcon#read 6, iclass 31, count 0 2006.173.21:29:34.57#ibcon#end of sib2, iclass 31, count 0 2006.173.21:29:34.57#ibcon#*after write, iclass 31, count 0 2006.173.21:29:34.57#ibcon#*before return 0, iclass 31, count 0 2006.173.21:29:34.57#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.21:29:34.57#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.21:29:34.57#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.21:29:34.57#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.21:29:34.57$vck44/valo=8,884.99 2006.173.21:29:34.57#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.21:29:34.57#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.21:29:34.57#ibcon#ireg 17 cls_cnt 0 2006.173.21:29:34.57#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.21:29:34.57#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.21:29:34.57#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.21:29:34.57#ibcon#enter wrdev, iclass 33, count 0 2006.173.21:29:34.57#ibcon#first serial, iclass 33, count 0 2006.173.21:29:34.57#ibcon#enter sib2, iclass 33, count 0 2006.173.21:29:34.57#ibcon#flushed, iclass 33, count 0 2006.173.21:29:34.57#ibcon#about to write, iclass 33, count 0 2006.173.21:29:34.57#ibcon#wrote, iclass 33, count 0 2006.173.21:29:34.57#ibcon#about to read 3, iclass 33, count 0 2006.173.21:29:34.59#ibcon#read 3, iclass 33, count 0 2006.173.21:29:34.59#ibcon#about to read 4, iclass 33, count 0 2006.173.21:29:34.59#ibcon#read 4, iclass 33, count 0 2006.173.21:29:34.59#ibcon#about to read 5, iclass 33, count 0 2006.173.21:29:34.59#ibcon#read 5, iclass 33, count 0 2006.173.21:29:34.59#ibcon#about to read 6, iclass 33, count 0 2006.173.21:29:34.59#ibcon#read 6, iclass 33, count 0 2006.173.21:29:34.59#ibcon#end of sib2, iclass 33, count 0 2006.173.21:29:34.59#ibcon#*mode == 0, iclass 33, count 0 2006.173.21:29:34.59#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.21:29:34.59#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.21:29:34.59#ibcon#*before write, iclass 33, count 0 2006.173.21:29:34.59#ibcon#enter sib2, iclass 33, count 0 2006.173.21:29:34.59#ibcon#flushed, iclass 33, count 0 2006.173.21:29:34.59#ibcon#about to write, iclass 33, count 0 2006.173.21:29:34.59#ibcon#wrote, iclass 33, count 0 2006.173.21:29:34.59#ibcon#about to read 3, iclass 33, count 0 2006.173.21:29:34.63#ibcon#read 3, iclass 33, count 0 2006.173.21:29:34.63#ibcon#about to read 4, iclass 33, count 0 2006.173.21:29:34.63#ibcon#read 4, iclass 33, count 0 2006.173.21:29:34.63#ibcon#about to read 5, iclass 33, count 0 2006.173.21:29:34.63#ibcon#read 5, iclass 33, count 0 2006.173.21:29:34.63#ibcon#about to read 6, iclass 33, count 0 2006.173.21:29:34.63#ibcon#read 6, iclass 33, count 0 2006.173.21:29:34.63#ibcon#end of sib2, iclass 33, count 0 2006.173.21:29:34.63#ibcon#*after write, iclass 33, count 0 2006.173.21:29:34.63#ibcon#*before return 0, iclass 33, count 0 2006.173.21:29:34.63#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.21:29:34.63#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.21:29:34.63#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.21:29:34.63#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.21:29:34.63$vck44/va=8,4 2006.173.21:29:34.63#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.21:29:34.63#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.21:29:34.63#ibcon#ireg 11 cls_cnt 2 2006.173.21:29:34.63#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.21:29:34.69#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.21:29:34.69#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.21:29:34.69#ibcon#enter wrdev, iclass 35, count 2 2006.173.21:29:34.69#ibcon#first serial, iclass 35, count 2 2006.173.21:29:34.69#ibcon#enter sib2, iclass 35, count 2 2006.173.21:29:34.69#ibcon#flushed, iclass 35, count 2 2006.173.21:29:34.69#ibcon#about to write, iclass 35, count 2 2006.173.21:29:34.69#ibcon#wrote, iclass 35, count 2 2006.173.21:29:34.69#ibcon#about to read 3, iclass 35, count 2 2006.173.21:29:34.71#ibcon#read 3, iclass 35, count 2 2006.173.21:29:34.71#ibcon#about to read 4, iclass 35, count 2 2006.173.21:29:34.71#ibcon#read 4, iclass 35, count 2 2006.173.21:29:34.71#ibcon#about to read 5, iclass 35, count 2 2006.173.21:29:34.71#ibcon#read 5, iclass 35, count 2 2006.173.21:29:34.71#ibcon#about to read 6, iclass 35, count 2 2006.173.21:29:34.71#ibcon#read 6, iclass 35, count 2 2006.173.21:29:34.71#ibcon#end of sib2, iclass 35, count 2 2006.173.21:29:34.71#ibcon#*mode == 0, iclass 35, count 2 2006.173.21:29:34.71#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.21:29:34.71#ibcon#[25=AT08-04\r\n] 2006.173.21:29:34.71#ibcon#*before write, iclass 35, count 2 2006.173.21:29:34.71#ibcon#enter sib2, iclass 35, count 2 2006.173.21:29:34.71#ibcon#flushed, iclass 35, count 2 2006.173.21:29:34.71#ibcon#about to write, iclass 35, count 2 2006.173.21:29:34.71#ibcon#wrote, iclass 35, count 2 2006.173.21:29:34.71#ibcon#about to read 3, iclass 35, count 2 2006.173.21:29:34.74#ibcon#read 3, iclass 35, count 2 2006.173.21:29:34.74#ibcon#about to read 4, iclass 35, count 2 2006.173.21:29:34.74#ibcon#read 4, iclass 35, count 2 2006.173.21:29:34.74#ibcon#about to read 5, iclass 35, count 2 2006.173.21:29:34.74#ibcon#read 5, iclass 35, count 2 2006.173.21:29:34.74#ibcon#about to read 6, iclass 35, count 2 2006.173.21:29:34.74#ibcon#read 6, iclass 35, count 2 2006.173.21:29:34.74#ibcon#end of sib2, iclass 35, count 2 2006.173.21:29:34.74#ibcon#*after write, iclass 35, count 2 2006.173.21:29:34.74#ibcon#*before return 0, iclass 35, count 2 2006.173.21:29:34.74#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.21:29:34.74#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.21:29:34.74#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.21:29:34.74#ibcon#ireg 7 cls_cnt 0 2006.173.21:29:34.74#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.21:29:34.86#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.21:29:34.86#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.21:29:34.86#ibcon#enter wrdev, iclass 35, count 0 2006.173.21:29:34.86#ibcon#first serial, iclass 35, count 0 2006.173.21:29:34.86#ibcon#enter sib2, iclass 35, count 0 2006.173.21:29:34.86#ibcon#flushed, iclass 35, count 0 2006.173.21:29:34.86#ibcon#about to write, iclass 35, count 0 2006.173.21:29:34.86#ibcon#wrote, iclass 35, count 0 2006.173.21:29:34.86#ibcon#about to read 3, iclass 35, count 0 2006.173.21:29:34.88#ibcon#read 3, iclass 35, count 0 2006.173.21:29:34.88#ibcon#about to read 4, iclass 35, count 0 2006.173.21:29:34.88#ibcon#read 4, iclass 35, count 0 2006.173.21:29:34.88#ibcon#about to read 5, iclass 35, count 0 2006.173.21:29:34.88#ibcon#read 5, iclass 35, count 0 2006.173.21:29:34.88#ibcon#about to read 6, iclass 35, count 0 2006.173.21:29:34.88#ibcon#read 6, iclass 35, count 0 2006.173.21:29:34.88#ibcon#end of sib2, iclass 35, count 0 2006.173.21:29:34.88#ibcon#*mode == 0, iclass 35, count 0 2006.173.21:29:34.88#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.21:29:34.88#ibcon#[25=USB\r\n] 2006.173.21:29:34.88#ibcon#*before write, iclass 35, count 0 2006.173.21:29:34.88#ibcon#enter sib2, iclass 35, count 0 2006.173.21:29:34.88#ibcon#flushed, iclass 35, count 0 2006.173.21:29:34.88#ibcon#about to write, iclass 35, count 0 2006.173.21:29:34.88#ibcon#wrote, iclass 35, count 0 2006.173.21:29:34.88#ibcon#about to read 3, iclass 35, count 0 2006.173.21:29:34.91#ibcon#read 3, iclass 35, count 0 2006.173.21:29:34.91#ibcon#about to read 4, iclass 35, count 0 2006.173.21:29:34.91#ibcon#read 4, iclass 35, count 0 2006.173.21:29:34.91#ibcon#about to read 5, iclass 35, count 0 2006.173.21:29:34.91#ibcon#read 5, iclass 35, count 0 2006.173.21:29:34.91#ibcon#about to read 6, iclass 35, count 0 2006.173.21:29:34.91#ibcon#read 6, iclass 35, count 0 2006.173.21:29:34.91#ibcon#end of sib2, iclass 35, count 0 2006.173.21:29:34.91#ibcon#*after write, iclass 35, count 0 2006.173.21:29:34.91#ibcon#*before return 0, iclass 35, count 0 2006.173.21:29:34.91#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.21:29:34.91#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.21:29:34.91#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.21:29:34.91#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.21:29:34.91$vck44/vblo=1,629.99 2006.173.21:29:34.91#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.21:29:34.91#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.21:29:34.91#ibcon#ireg 17 cls_cnt 0 2006.173.21:29:34.91#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.21:29:34.91#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.21:29:34.91#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.21:29:34.91#ibcon#enter wrdev, iclass 37, count 0 2006.173.21:29:34.91#ibcon#first serial, iclass 37, count 0 2006.173.21:29:34.91#ibcon#enter sib2, iclass 37, count 0 2006.173.21:29:34.91#ibcon#flushed, iclass 37, count 0 2006.173.21:29:34.91#ibcon#about to write, iclass 37, count 0 2006.173.21:29:34.91#ibcon#wrote, iclass 37, count 0 2006.173.21:29:34.91#ibcon#about to read 3, iclass 37, count 0 2006.173.21:29:34.93#ibcon#read 3, iclass 37, count 0 2006.173.21:29:34.93#ibcon#about to read 4, iclass 37, count 0 2006.173.21:29:34.93#ibcon#read 4, iclass 37, count 0 2006.173.21:29:34.93#ibcon#about to read 5, iclass 37, count 0 2006.173.21:29:34.93#ibcon#read 5, iclass 37, count 0 2006.173.21:29:34.93#ibcon#about to read 6, iclass 37, count 0 2006.173.21:29:34.93#ibcon#read 6, iclass 37, count 0 2006.173.21:29:34.93#ibcon#end of sib2, iclass 37, count 0 2006.173.21:29:34.93#ibcon#*mode == 0, iclass 37, count 0 2006.173.21:29:34.93#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.21:29:34.93#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.21:29:34.93#ibcon#*before write, iclass 37, count 0 2006.173.21:29:34.93#ibcon#enter sib2, iclass 37, count 0 2006.173.21:29:34.93#ibcon#flushed, iclass 37, count 0 2006.173.21:29:34.93#ibcon#about to write, iclass 37, count 0 2006.173.21:29:34.93#ibcon#wrote, iclass 37, count 0 2006.173.21:29:34.93#ibcon#about to read 3, iclass 37, count 0 2006.173.21:29:34.97#ibcon#read 3, iclass 37, count 0 2006.173.21:29:34.97#ibcon#about to read 4, iclass 37, count 0 2006.173.21:29:34.97#ibcon#read 4, iclass 37, count 0 2006.173.21:29:34.97#ibcon#about to read 5, iclass 37, count 0 2006.173.21:29:34.97#ibcon#read 5, iclass 37, count 0 2006.173.21:29:34.97#ibcon#about to read 6, iclass 37, count 0 2006.173.21:29:34.97#ibcon#read 6, iclass 37, count 0 2006.173.21:29:34.97#ibcon#end of sib2, iclass 37, count 0 2006.173.21:29:34.97#ibcon#*after write, iclass 37, count 0 2006.173.21:29:34.97#ibcon#*before return 0, iclass 37, count 0 2006.173.21:29:34.97#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.21:29:34.97#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.21:29:34.97#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.21:29:34.97#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.21:29:34.97$vck44/vb=1,4 2006.173.21:29:34.97#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.21:29:34.97#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.21:29:34.97#ibcon#ireg 11 cls_cnt 2 2006.173.21:29:34.97#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.21:29:34.97#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.21:29:34.97#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.21:29:34.97#ibcon#enter wrdev, iclass 39, count 2 2006.173.21:29:34.97#ibcon#first serial, iclass 39, count 2 2006.173.21:29:34.97#ibcon#enter sib2, iclass 39, count 2 2006.173.21:29:34.97#ibcon#flushed, iclass 39, count 2 2006.173.21:29:34.97#ibcon#about to write, iclass 39, count 2 2006.173.21:29:34.97#ibcon#wrote, iclass 39, count 2 2006.173.21:29:34.97#ibcon#about to read 3, iclass 39, count 2 2006.173.21:29:34.99#ibcon#read 3, iclass 39, count 2 2006.173.21:29:34.99#ibcon#about to read 4, iclass 39, count 2 2006.173.21:29:34.99#ibcon#read 4, iclass 39, count 2 2006.173.21:29:34.99#ibcon#about to read 5, iclass 39, count 2 2006.173.21:29:34.99#ibcon#read 5, iclass 39, count 2 2006.173.21:29:34.99#ibcon#about to read 6, iclass 39, count 2 2006.173.21:29:34.99#ibcon#read 6, iclass 39, count 2 2006.173.21:29:34.99#ibcon#end of sib2, iclass 39, count 2 2006.173.21:29:34.99#ibcon#*mode == 0, iclass 39, count 2 2006.173.21:29:34.99#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.21:29:34.99#ibcon#[27=AT01-04\r\n] 2006.173.21:29:34.99#ibcon#*before write, iclass 39, count 2 2006.173.21:29:34.99#ibcon#enter sib2, iclass 39, count 2 2006.173.21:29:34.99#ibcon#flushed, iclass 39, count 2 2006.173.21:29:34.99#ibcon#about to write, iclass 39, count 2 2006.173.21:29:34.99#ibcon#wrote, iclass 39, count 2 2006.173.21:29:34.99#ibcon#about to read 3, iclass 39, count 2 2006.173.21:29:35.02#ibcon#read 3, iclass 39, count 2 2006.173.21:29:35.02#ibcon#about to read 4, iclass 39, count 2 2006.173.21:29:35.02#ibcon#read 4, iclass 39, count 2 2006.173.21:29:35.02#ibcon#about to read 5, iclass 39, count 2 2006.173.21:29:35.02#ibcon#read 5, iclass 39, count 2 2006.173.21:29:35.02#ibcon#about to read 6, iclass 39, count 2 2006.173.21:29:35.02#ibcon#read 6, iclass 39, count 2 2006.173.21:29:35.02#ibcon#end of sib2, iclass 39, count 2 2006.173.21:29:35.02#ibcon#*after write, iclass 39, count 2 2006.173.21:29:35.02#ibcon#*before return 0, iclass 39, count 2 2006.173.21:29:35.02#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.21:29:35.02#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.21:29:35.02#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.21:29:35.02#ibcon#ireg 7 cls_cnt 0 2006.173.21:29:35.02#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.21:29:35.14#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.21:29:35.14#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.21:29:35.14#ibcon#enter wrdev, iclass 39, count 0 2006.173.21:29:35.14#ibcon#first serial, iclass 39, count 0 2006.173.21:29:35.14#ibcon#enter sib2, iclass 39, count 0 2006.173.21:29:35.14#ibcon#flushed, iclass 39, count 0 2006.173.21:29:35.14#ibcon#about to write, iclass 39, count 0 2006.173.21:29:35.14#ibcon#wrote, iclass 39, count 0 2006.173.21:29:35.14#ibcon#about to read 3, iclass 39, count 0 2006.173.21:29:35.16#ibcon#read 3, iclass 39, count 0 2006.173.21:29:35.16#ibcon#about to read 4, iclass 39, count 0 2006.173.21:29:35.16#ibcon#read 4, iclass 39, count 0 2006.173.21:29:35.16#ibcon#about to read 5, iclass 39, count 0 2006.173.21:29:35.16#ibcon#read 5, iclass 39, count 0 2006.173.21:29:35.16#ibcon#about to read 6, iclass 39, count 0 2006.173.21:29:35.16#ibcon#read 6, iclass 39, count 0 2006.173.21:29:35.16#ibcon#end of sib2, iclass 39, count 0 2006.173.21:29:35.16#ibcon#*mode == 0, iclass 39, count 0 2006.173.21:29:35.16#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.21:29:35.16#ibcon#[27=USB\r\n] 2006.173.21:29:35.16#ibcon#*before write, iclass 39, count 0 2006.173.21:29:35.16#ibcon#enter sib2, iclass 39, count 0 2006.173.21:29:35.16#ibcon#flushed, iclass 39, count 0 2006.173.21:29:35.16#ibcon#about to write, iclass 39, count 0 2006.173.21:29:35.16#ibcon#wrote, iclass 39, count 0 2006.173.21:29:35.16#ibcon#about to read 3, iclass 39, count 0 2006.173.21:29:35.19#ibcon#read 3, iclass 39, count 0 2006.173.21:29:35.19#ibcon#about to read 4, iclass 39, count 0 2006.173.21:29:35.19#ibcon#read 4, iclass 39, count 0 2006.173.21:29:35.19#ibcon#about to read 5, iclass 39, count 0 2006.173.21:29:35.19#ibcon#read 5, iclass 39, count 0 2006.173.21:29:35.19#ibcon#about to read 6, iclass 39, count 0 2006.173.21:29:35.19#ibcon#read 6, iclass 39, count 0 2006.173.21:29:35.19#ibcon#end of sib2, iclass 39, count 0 2006.173.21:29:35.19#ibcon#*after write, iclass 39, count 0 2006.173.21:29:35.19#ibcon#*before return 0, iclass 39, count 0 2006.173.21:29:35.19#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.21:29:35.19#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.21:29:35.19#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.21:29:35.19#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.21:29:35.19$vck44/vblo=2,634.99 2006.173.21:29:35.19#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.21:29:35.19#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.21:29:35.19#ibcon#ireg 17 cls_cnt 0 2006.173.21:29:35.19#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.21:29:35.19#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.21:29:35.19#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.21:29:35.19#ibcon#enter wrdev, iclass 3, count 0 2006.173.21:29:35.19#ibcon#first serial, iclass 3, count 0 2006.173.21:29:35.19#ibcon#enter sib2, iclass 3, count 0 2006.173.21:29:35.19#ibcon#flushed, iclass 3, count 0 2006.173.21:29:35.19#ibcon#about to write, iclass 3, count 0 2006.173.21:29:35.19#ibcon#wrote, iclass 3, count 0 2006.173.21:29:35.19#ibcon#about to read 3, iclass 3, count 0 2006.173.21:29:35.21#ibcon#read 3, iclass 3, count 0 2006.173.21:29:35.21#ibcon#about to read 4, iclass 3, count 0 2006.173.21:29:35.21#ibcon#read 4, iclass 3, count 0 2006.173.21:29:35.21#ibcon#about to read 5, iclass 3, count 0 2006.173.21:29:35.21#ibcon#read 5, iclass 3, count 0 2006.173.21:29:35.21#ibcon#about to read 6, iclass 3, count 0 2006.173.21:29:35.21#ibcon#read 6, iclass 3, count 0 2006.173.21:29:35.21#ibcon#end of sib2, iclass 3, count 0 2006.173.21:29:35.21#ibcon#*mode == 0, iclass 3, count 0 2006.173.21:29:35.21#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.21:29:35.21#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.21:29:35.21#ibcon#*before write, iclass 3, count 0 2006.173.21:29:35.21#ibcon#enter sib2, iclass 3, count 0 2006.173.21:29:35.21#ibcon#flushed, iclass 3, count 0 2006.173.21:29:35.21#ibcon#about to write, iclass 3, count 0 2006.173.21:29:35.21#ibcon#wrote, iclass 3, count 0 2006.173.21:29:35.21#ibcon#about to read 3, iclass 3, count 0 2006.173.21:29:35.25#ibcon#read 3, iclass 3, count 0 2006.173.21:29:35.25#ibcon#about to read 4, iclass 3, count 0 2006.173.21:29:35.25#ibcon#read 4, iclass 3, count 0 2006.173.21:29:35.25#ibcon#about to read 5, iclass 3, count 0 2006.173.21:29:35.25#ibcon#read 5, iclass 3, count 0 2006.173.21:29:35.25#ibcon#about to read 6, iclass 3, count 0 2006.173.21:29:35.25#ibcon#read 6, iclass 3, count 0 2006.173.21:29:35.25#ibcon#end of sib2, iclass 3, count 0 2006.173.21:29:35.25#ibcon#*after write, iclass 3, count 0 2006.173.21:29:35.25#ibcon#*before return 0, iclass 3, count 0 2006.173.21:29:35.25#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.21:29:35.25#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.21:29:35.25#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.21:29:35.25#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.21:29:35.25$vck44/vb=2,4 2006.173.21:29:35.25#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.21:29:35.25#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.21:29:35.25#ibcon#ireg 11 cls_cnt 2 2006.173.21:29:35.25#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.21:29:35.31#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.21:29:35.31#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.21:29:35.31#ibcon#enter wrdev, iclass 5, count 2 2006.173.21:29:35.31#ibcon#first serial, iclass 5, count 2 2006.173.21:29:35.31#ibcon#enter sib2, iclass 5, count 2 2006.173.21:29:35.31#ibcon#flushed, iclass 5, count 2 2006.173.21:29:35.31#ibcon#about to write, iclass 5, count 2 2006.173.21:29:35.31#ibcon#wrote, iclass 5, count 2 2006.173.21:29:35.31#ibcon#about to read 3, iclass 5, count 2 2006.173.21:29:35.33#ibcon#read 3, iclass 5, count 2 2006.173.21:29:35.33#ibcon#about to read 4, iclass 5, count 2 2006.173.21:29:35.33#ibcon#read 4, iclass 5, count 2 2006.173.21:29:35.33#ibcon#about to read 5, iclass 5, count 2 2006.173.21:29:35.33#ibcon#read 5, iclass 5, count 2 2006.173.21:29:35.33#ibcon#about to read 6, iclass 5, count 2 2006.173.21:29:35.33#ibcon#read 6, iclass 5, count 2 2006.173.21:29:35.33#ibcon#end of sib2, iclass 5, count 2 2006.173.21:29:35.33#ibcon#*mode == 0, iclass 5, count 2 2006.173.21:29:35.33#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.21:29:35.33#ibcon#[27=AT02-04\r\n] 2006.173.21:29:35.33#ibcon#*before write, iclass 5, count 2 2006.173.21:29:35.33#ibcon#enter sib2, iclass 5, count 2 2006.173.21:29:35.33#ibcon#flushed, iclass 5, count 2 2006.173.21:29:35.33#ibcon#about to write, iclass 5, count 2 2006.173.21:29:35.33#ibcon#wrote, iclass 5, count 2 2006.173.21:29:35.33#ibcon#about to read 3, iclass 5, count 2 2006.173.21:29:35.36#ibcon#read 3, iclass 5, count 2 2006.173.21:29:35.36#ibcon#about to read 4, iclass 5, count 2 2006.173.21:29:35.36#ibcon#read 4, iclass 5, count 2 2006.173.21:29:35.36#ibcon#about to read 5, iclass 5, count 2 2006.173.21:29:35.36#ibcon#read 5, iclass 5, count 2 2006.173.21:29:35.36#ibcon#about to read 6, iclass 5, count 2 2006.173.21:29:35.36#ibcon#read 6, iclass 5, count 2 2006.173.21:29:35.36#ibcon#end of sib2, iclass 5, count 2 2006.173.21:29:35.36#ibcon#*after write, iclass 5, count 2 2006.173.21:29:35.36#ibcon#*before return 0, iclass 5, count 2 2006.173.21:29:35.36#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.21:29:35.36#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.21:29:35.36#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.21:29:35.36#ibcon#ireg 7 cls_cnt 0 2006.173.21:29:35.36#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.21:29:35.48#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.21:29:35.48#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.21:29:35.48#ibcon#enter wrdev, iclass 5, count 0 2006.173.21:29:35.48#ibcon#first serial, iclass 5, count 0 2006.173.21:29:35.48#ibcon#enter sib2, iclass 5, count 0 2006.173.21:29:35.48#ibcon#flushed, iclass 5, count 0 2006.173.21:29:35.48#ibcon#about to write, iclass 5, count 0 2006.173.21:29:35.48#ibcon#wrote, iclass 5, count 0 2006.173.21:29:35.48#ibcon#about to read 3, iclass 5, count 0 2006.173.21:29:35.50#ibcon#read 3, iclass 5, count 0 2006.173.21:29:35.50#ibcon#about to read 4, iclass 5, count 0 2006.173.21:29:35.50#ibcon#read 4, iclass 5, count 0 2006.173.21:29:35.50#ibcon#about to read 5, iclass 5, count 0 2006.173.21:29:35.50#ibcon#read 5, iclass 5, count 0 2006.173.21:29:35.50#ibcon#about to read 6, iclass 5, count 0 2006.173.21:29:35.50#ibcon#read 6, iclass 5, count 0 2006.173.21:29:35.50#ibcon#end of sib2, iclass 5, count 0 2006.173.21:29:35.50#ibcon#*mode == 0, iclass 5, count 0 2006.173.21:29:35.50#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.21:29:35.50#ibcon#[27=USB\r\n] 2006.173.21:29:35.50#ibcon#*before write, iclass 5, count 0 2006.173.21:29:35.50#ibcon#enter sib2, iclass 5, count 0 2006.173.21:29:35.50#ibcon#flushed, iclass 5, count 0 2006.173.21:29:35.50#ibcon#about to write, iclass 5, count 0 2006.173.21:29:35.50#ibcon#wrote, iclass 5, count 0 2006.173.21:29:35.50#ibcon#about to read 3, iclass 5, count 0 2006.173.21:29:35.53#ibcon#read 3, iclass 5, count 0 2006.173.21:29:35.53#ibcon#about to read 4, iclass 5, count 0 2006.173.21:29:35.53#ibcon#read 4, iclass 5, count 0 2006.173.21:29:35.53#ibcon#about to read 5, iclass 5, count 0 2006.173.21:29:35.53#ibcon#read 5, iclass 5, count 0 2006.173.21:29:35.53#ibcon#about to read 6, iclass 5, count 0 2006.173.21:29:35.53#ibcon#read 6, iclass 5, count 0 2006.173.21:29:35.53#ibcon#end of sib2, iclass 5, count 0 2006.173.21:29:35.53#ibcon#*after write, iclass 5, count 0 2006.173.21:29:35.53#ibcon#*before return 0, iclass 5, count 0 2006.173.21:29:35.53#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.21:29:35.53#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.21:29:35.53#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.21:29:35.53#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.21:29:35.53$vck44/vblo=3,649.99 2006.173.21:29:35.53#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.21:29:35.53#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.21:29:35.53#ibcon#ireg 17 cls_cnt 0 2006.173.21:29:35.53#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.21:29:35.53#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.21:29:35.53#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.21:29:35.53#ibcon#enter wrdev, iclass 7, count 0 2006.173.21:29:35.53#ibcon#first serial, iclass 7, count 0 2006.173.21:29:35.53#ibcon#enter sib2, iclass 7, count 0 2006.173.21:29:35.53#ibcon#flushed, iclass 7, count 0 2006.173.21:29:35.53#ibcon#about to write, iclass 7, count 0 2006.173.21:29:35.53#ibcon#wrote, iclass 7, count 0 2006.173.21:29:35.53#ibcon#about to read 3, iclass 7, count 0 2006.173.21:29:35.55#ibcon#read 3, iclass 7, count 0 2006.173.21:29:35.55#ibcon#about to read 4, iclass 7, count 0 2006.173.21:29:35.55#ibcon#read 4, iclass 7, count 0 2006.173.21:29:35.55#ibcon#about to read 5, iclass 7, count 0 2006.173.21:29:35.55#ibcon#read 5, iclass 7, count 0 2006.173.21:29:35.55#ibcon#about to read 6, iclass 7, count 0 2006.173.21:29:35.55#ibcon#read 6, iclass 7, count 0 2006.173.21:29:35.55#ibcon#end of sib2, iclass 7, count 0 2006.173.21:29:35.55#ibcon#*mode == 0, iclass 7, count 0 2006.173.21:29:35.55#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.21:29:35.55#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.21:29:35.55#ibcon#*before write, iclass 7, count 0 2006.173.21:29:35.55#ibcon#enter sib2, iclass 7, count 0 2006.173.21:29:35.55#ibcon#flushed, iclass 7, count 0 2006.173.21:29:35.55#ibcon#about to write, iclass 7, count 0 2006.173.21:29:35.55#ibcon#wrote, iclass 7, count 0 2006.173.21:29:35.55#ibcon#about to read 3, iclass 7, count 0 2006.173.21:29:35.59#ibcon#read 3, iclass 7, count 0 2006.173.21:29:35.59#ibcon#about to read 4, iclass 7, count 0 2006.173.21:29:35.59#ibcon#read 4, iclass 7, count 0 2006.173.21:29:35.59#ibcon#about to read 5, iclass 7, count 0 2006.173.21:29:35.59#ibcon#read 5, iclass 7, count 0 2006.173.21:29:35.59#ibcon#about to read 6, iclass 7, count 0 2006.173.21:29:35.59#ibcon#read 6, iclass 7, count 0 2006.173.21:29:35.59#ibcon#end of sib2, iclass 7, count 0 2006.173.21:29:35.59#ibcon#*after write, iclass 7, count 0 2006.173.21:29:35.59#ibcon#*before return 0, iclass 7, count 0 2006.173.21:29:35.59#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.21:29:35.59#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.21:29:35.59#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.21:29:35.59#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.21:29:35.59$vck44/vb=3,4 2006.173.21:29:35.59#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.21:29:35.59#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.21:29:35.59#ibcon#ireg 11 cls_cnt 2 2006.173.21:29:35.59#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.21:29:35.65#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.21:29:35.65#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.21:29:35.65#ibcon#enter wrdev, iclass 11, count 2 2006.173.21:29:35.65#ibcon#first serial, iclass 11, count 2 2006.173.21:29:35.65#ibcon#enter sib2, iclass 11, count 2 2006.173.21:29:35.65#ibcon#flushed, iclass 11, count 2 2006.173.21:29:35.65#ibcon#about to write, iclass 11, count 2 2006.173.21:29:35.65#ibcon#wrote, iclass 11, count 2 2006.173.21:29:35.65#ibcon#about to read 3, iclass 11, count 2 2006.173.21:29:35.67#ibcon#read 3, iclass 11, count 2 2006.173.21:29:35.67#ibcon#about to read 4, iclass 11, count 2 2006.173.21:29:35.67#ibcon#read 4, iclass 11, count 2 2006.173.21:29:35.67#ibcon#about to read 5, iclass 11, count 2 2006.173.21:29:35.67#ibcon#read 5, iclass 11, count 2 2006.173.21:29:35.67#ibcon#about to read 6, iclass 11, count 2 2006.173.21:29:35.67#ibcon#read 6, iclass 11, count 2 2006.173.21:29:35.67#ibcon#end of sib2, iclass 11, count 2 2006.173.21:29:35.67#ibcon#*mode == 0, iclass 11, count 2 2006.173.21:29:35.67#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.21:29:35.67#ibcon#[27=AT03-04\r\n] 2006.173.21:29:35.67#ibcon#*before write, iclass 11, count 2 2006.173.21:29:35.67#ibcon#enter sib2, iclass 11, count 2 2006.173.21:29:35.67#ibcon#flushed, iclass 11, count 2 2006.173.21:29:35.67#ibcon#about to write, iclass 11, count 2 2006.173.21:29:35.67#ibcon#wrote, iclass 11, count 2 2006.173.21:29:35.67#ibcon#about to read 3, iclass 11, count 2 2006.173.21:29:35.70#ibcon#read 3, iclass 11, count 2 2006.173.21:29:35.70#ibcon#about to read 4, iclass 11, count 2 2006.173.21:29:35.70#ibcon#read 4, iclass 11, count 2 2006.173.21:29:35.70#ibcon#about to read 5, iclass 11, count 2 2006.173.21:29:35.70#ibcon#read 5, iclass 11, count 2 2006.173.21:29:35.70#ibcon#about to read 6, iclass 11, count 2 2006.173.21:29:35.70#ibcon#read 6, iclass 11, count 2 2006.173.21:29:35.70#ibcon#end of sib2, iclass 11, count 2 2006.173.21:29:35.70#ibcon#*after write, iclass 11, count 2 2006.173.21:29:35.70#ibcon#*before return 0, iclass 11, count 2 2006.173.21:29:35.70#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.21:29:35.70#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.21:29:35.70#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.21:29:35.70#ibcon#ireg 7 cls_cnt 0 2006.173.21:29:35.70#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.21:29:35.82#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.21:29:35.82#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.21:29:35.82#ibcon#enter wrdev, iclass 11, count 0 2006.173.21:29:35.82#ibcon#first serial, iclass 11, count 0 2006.173.21:29:35.82#ibcon#enter sib2, iclass 11, count 0 2006.173.21:29:35.82#ibcon#flushed, iclass 11, count 0 2006.173.21:29:35.82#ibcon#about to write, iclass 11, count 0 2006.173.21:29:35.82#ibcon#wrote, iclass 11, count 0 2006.173.21:29:35.82#ibcon#about to read 3, iclass 11, count 0 2006.173.21:29:35.84#ibcon#read 3, iclass 11, count 0 2006.173.21:29:35.84#ibcon#about to read 4, iclass 11, count 0 2006.173.21:29:35.84#ibcon#read 4, iclass 11, count 0 2006.173.21:29:35.84#ibcon#about to read 5, iclass 11, count 0 2006.173.21:29:35.84#ibcon#read 5, iclass 11, count 0 2006.173.21:29:35.84#ibcon#about to read 6, iclass 11, count 0 2006.173.21:29:35.84#ibcon#read 6, iclass 11, count 0 2006.173.21:29:35.84#ibcon#end of sib2, iclass 11, count 0 2006.173.21:29:35.84#ibcon#*mode == 0, iclass 11, count 0 2006.173.21:29:35.84#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.21:29:35.84#ibcon#[27=USB\r\n] 2006.173.21:29:35.84#ibcon#*before write, iclass 11, count 0 2006.173.21:29:35.84#ibcon#enter sib2, iclass 11, count 0 2006.173.21:29:35.84#ibcon#flushed, iclass 11, count 0 2006.173.21:29:35.84#ibcon#about to write, iclass 11, count 0 2006.173.21:29:35.84#ibcon#wrote, iclass 11, count 0 2006.173.21:29:35.84#ibcon#about to read 3, iclass 11, count 0 2006.173.21:29:35.87#ibcon#read 3, iclass 11, count 0 2006.173.21:29:35.87#ibcon#about to read 4, iclass 11, count 0 2006.173.21:29:35.87#ibcon#read 4, iclass 11, count 0 2006.173.21:29:35.87#ibcon#about to read 5, iclass 11, count 0 2006.173.21:29:35.87#ibcon#read 5, iclass 11, count 0 2006.173.21:29:35.87#ibcon#about to read 6, iclass 11, count 0 2006.173.21:29:35.87#ibcon#read 6, iclass 11, count 0 2006.173.21:29:35.87#ibcon#end of sib2, iclass 11, count 0 2006.173.21:29:35.87#ibcon#*after write, iclass 11, count 0 2006.173.21:29:35.87#ibcon#*before return 0, iclass 11, count 0 2006.173.21:29:35.87#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.21:29:35.87#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.21:29:35.87#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.21:29:35.87#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.21:29:35.87$vck44/vblo=4,679.99 2006.173.21:29:35.87#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.21:29:35.87#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.21:29:35.87#ibcon#ireg 17 cls_cnt 0 2006.173.21:29:35.87#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.21:29:35.87#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.21:29:35.87#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.21:29:35.87#ibcon#enter wrdev, iclass 13, count 0 2006.173.21:29:35.87#ibcon#first serial, iclass 13, count 0 2006.173.21:29:35.87#ibcon#enter sib2, iclass 13, count 0 2006.173.21:29:35.87#ibcon#flushed, iclass 13, count 0 2006.173.21:29:35.87#ibcon#about to write, iclass 13, count 0 2006.173.21:29:35.87#ibcon#wrote, iclass 13, count 0 2006.173.21:29:35.87#ibcon#about to read 3, iclass 13, count 0 2006.173.21:29:35.89#ibcon#read 3, iclass 13, count 0 2006.173.21:29:35.89#ibcon#about to read 4, iclass 13, count 0 2006.173.21:29:35.89#ibcon#read 4, iclass 13, count 0 2006.173.21:29:35.89#ibcon#about to read 5, iclass 13, count 0 2006.173.21:29:35.89#ibcon#read 5, iclass 13, count 0 2006.173.21:29:35.89#ibcon#about to read 6, iclass 13, count 0 2006.173.21:29:35.89#ibcon#read 6, iclass 13, count 0 2006.173.21:29:35.89#ibcon#end of sib2, iclass 13, count 0 2006.173.21:29:35.89#ibcon#*mode == 0, iclass 13, count 0 2006.173.21:29:35.89#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.21:29:35.89#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.21:29:35.89#ibcon#*before write, iclass 13, count 0 2006.173.21:29:35.89#ibcon#enter sib2, iclass 13, count 0 2006.173.21:29:35.89#ibcon#flushed, iclass 13, count 0 2006.173.21:29:35.89#ibcon#about to write, iclass 13, count 0 2006.173.21:29:35.89#ibcon#wrote, iclass 13, count 0 2006.173.21:29:35.89#ibcon#about to read 3, iclass 13, count 0 2006.173.21:29:35.93#ibcon#read 3, iclass 13, count 0 2006.173.21:29:35.93#ibcon#about to read 4, iclass 13, count 0 2006.173.21:29:35.93#ibcon#read 4, iclass 13, count 0 2006.173.21:29:35.93#ibcon#about to read 5, iclass 13, count 0 2006.173.21:29:35.93#ibcon#read 5, iclass 13, count 0 2006.173.21:29:35.93#ibcon#about to read 6, iclass 13, count 0 2006.173.21:29:35.93#ibcon#read 6, iclass 13, count 0 2006.173.21:29:35.93#ibcon#end of sib2, iclass 13, count 0 2006.173.21:29:35.93#ibcon#*after write, iclass 13, count 0 2006.173.21:29:35.93#ibcon#*before return 0, iclass 13, count 0 2006.173.21:29:35.93#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.21:29:35.93#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.21:29:35.93#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.21:29:35.93#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.21:29:35.93$vck44/vb=4,4 2006.173.21:29:35.93#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.21:29:35.93#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.21:29:35.93#ibcon#ireg 11 cls_cnt 2 2006.173.21:29:35.93#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.21:29:35.99#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.21:29:35.99#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.21:29:35.99#ibcon#enter wrdev, iclass 15, count 2 2006.173.21:29:35.99#ibcon#first serial, iclass 15, count 2 2006.173.21:29:35.99#ibcon#enter sib2, iclass 15, count 2 2006.173.21:29:35.99#ibcon#flushed, iclass 15, count 2 2006.173.21:29:35.99#ibcon#about to write, iclass 15, count 2 2006.173.21:29:35.99#ibcon#wrote, iclass 15, count 2 2006.173.21:29:35.99#ibcon#about to read 3, iclass 15, count 2 2006.173.21:29:36.01#ibcon#read 3, iclass 15, count 2 2006.173.21:29:36.01#ibcon#about to read 4, iclass 15, count 2 2006.173.21:29:36.01#ibcon#read 4, iclass 15, count 2 2006.173.21:29:36.01#ibcon#about to read 5, iclass 15, count 2 2006.173.21:29:36.01#ibcon#read 5, iclass 15, count 2 2006.173.21:29:36.01#ibcon#about to read 6, iclass 15, count 2 2006.173.21:29:36.01#ibcon#read 6, iclass 15, count 2 2006.173.21:29:36.01#ibcon#end of sib2, iclass 15, count 2 2006.173.21:29:36.01#ibcon#*mode == 0, iclass 15, count 2 2006.173.21:29:36.01#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.21:29:36.01#ibcon#[27=AT04-04\r\n] 2006.173.21:29:36.01#ibcon#*before write, iclass 15, count 2 2006.173.21:29:36.01#ibcon#enter sib2, iclass 15, count 2 2006.173.21:29:36.01#ibcon#flushed, iclass 15, count 2 2006.173.21:29:36.01#ibcon#about to write, iclass 15, count 2 2006.173.21:29:36.01#ibcon#wrote, iclass 15, count 2 2006.173.21:29:36.01#ibcon#about to read 3, iclass 15, count 2 2006.173.21:29:36.04#ibcon#read 3, iclass 15, count 2 2006.173.21:29:36.04#ibcon#about to read 4, iclass 15, count 2 2006.173.21:29:36.04#ibcon#read 4, iclass 15, count 2 2006.173.21:29:36.04#ibcon#about to read 5, iclass 15, count 2 2006.173.21:29:36.04#ibcon#read 5, iclass 15, count 2 2006.173.21:29:36.04#ibcon#about to read 6, iclass 15, count 2 2006.173.21:29:36.04#ibcon#read 6, iclass 15, count 2 2006.173.21:29:36.04#ibcon#end of sib2, iclass 15, count 2 2006.173.21:29:36.04#ibcon#*after write, iclass 15, count 2 2006.173.21:29:36.04#ibcon#*before return 0, iclass 15, count 2 2006.173.21:29:36.04#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.21:29:36.04#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.21:29:36.04#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.21:29:36.04#ibcon#ireg 7 cls_cnt 0 2006.173.21:29:36.04#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.21:29:36.16#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.21:29:36.16#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.21:29:36.16#ibcon#enter wrdev, iclass 15, count 0 2006.173.21:29:36.16#ibcon#first serial, iclass 15, count 0 2006.173.21:29:36.16#ibcon#enter sib2, iclass 15, count 0 2006.173.21:29:36.16#ibcon#flushed, iclass 15, count 0 2006.173.21:29:36.16#ibcon#about to write, iclass 15, count 0 2006.173.21:29:36.16#ibcon#wrote, iclass 15, count 0 2006.173.21:29:36.16#ibcon#about to read 3, iclass 15, count 0 2006.173.21:29:36.18#ibcon#read 3, iclass 15, count 0 2006.173.21:29:36.18#ibcon#about to read 4, iclass 15, count 0 2006.173.21:29:36.18#ibcon#read 4, iclass 15, count 0 2006.173.21:29:36.18#ibcon#about to read 5, iclass 15, count 0 2006.173.21:29:36.18#ibcon#read 5, iclass 15, count 0 2006.173.21:29:36.18#ibcon#about to read 6, iclass 15, count 0 2006.173.21:29:36.18#ibcon#read 6, iclass 15, count 0 2006.173.21:29:36.18#ibcon#end of sib2, iclass 15, count 0 2006.173.21:29:36.18#ibcon#*mode == 0, iclass 15, count 0 2006.173.21:29:36.18#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.21:29:36.18#ibcon#[27=USB\r\n] 2006.173.21:29:36.18#ibcon#*before write, iclass 15, count 0 2006.173.21:29:36.18#ibcon#enter sib2, iclass 15, count 0 2006.173.21:29:36.18#ibcon#flushed, iclass 15, count 0 2006.173.21:29:36.18#ibcon#about to write, iclass 15, count 0 2006.173.21:29:36.18#ibcon#wrote, iclass 15, count 0 2006.173.21:29:36.18#ibcon#about to read 3, iclass 15, count 0 2006.173.21:29:36.21#ibcon#read 3, iclass 15, count 0 2006.173.21:29:36.21#ibcon#about to read 4, iclass 15, count 0 2006.173.21:29:36.21#ibcon#read 4, iclass 15, count 0 2006.173.21:29:36.21#ibcon#about to read 5, iclass 15, count 0 2006.173.21:29:36.21#ibcon#read 5, iclass 15, count 0 2006.173.21:29:36.21#ibcon#about to read 6, iclass 15, count 0 2006.173.21:29:36.21#ibcon#read 6, iclass 15, count 0 2006.173.21:29:36.21#ibcon#end of sib2, iclass 15, count 0 2006.173.21:29:36.21#ibcon#*after write, iclass 15, count 0 2006.173.21:29:36.21#ibcon#*before return 0, iclass 15, count 0 2006.173.21:29:36.21#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.21:29:36.21#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.21:29:36.21#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.21:29:36.21#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.21:29:36.21$vck44/vblo=5,709.99 2006.173.21:29:36.21#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.21:29:36.21#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.21:29:36.21#ibcon#ireg 17 cls_cnt 0 2006.173.21:29:36.21#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.21:29:36.21#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.21:29:36.21#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.21:29:36.21#ibcon#enter wrdev, iclass 17, count 0 2006.173.21:29:36.21#ibcon#first serial, iclass 17, count 0 2006.173.21:29:36.21#ibcon#enter sib2, iclass 17, count 0 2006.173.21:29:36.21#ibcon#flushed, iclass 17, count 0 2006.173.21:29:36.21#ibcon#about to write, iclass 17, count 0 2006.173.21:29:36.21#ibcon#wrote, iclass 17, count 0 2006.173.21:29:36.21#ibcon#about to read 3, iclass 17, count 0 2006.173.21:29:36.23#ibcon#read 3, iclass 17, count 0 2006.173.21:29:36.23#ibcon#about to read 4, iclass 17, count 0 2006.173.21:29:36.23#ibcon#read 4, iclass 17, count 0 2006.173.21:29:36.23#ibcon#about to read 5, iclass 17, count 0 2006.173.21:29:36.23#ibcon#read 5, iclass 17, count 0 2006.173.21:29:36.23#ibcon#about to read 6, iclass 17, count 0 2006.173.21:29:36.23#ibcon#read 6, iclass 17, count 0 2006.173.21:29:36.23#ibcon#end of sib2, iclass 17, count 0 2006.173.21:29:36.23#ibcon#*mode == 0, iclass 17, count 0 2006.173.21:29:36.23#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.21:29:36.23#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.21:29:36.23#ibcon#*before write, iclass 17, count 0 2006.173.21:29:36.23#ibcon#enter sib2, iclass 17, count 0 2006.173.21:29:36.23#ibcon#flushed, iclass 17, count 0 2006.173.21:29:36.23#ibcon#about to write, iclass 17, count 0 2006.173.21:29:36.23#ibcon#wrote, iclass 17, count 0 2006.173.21:29:36.23#ibcon#about to read 3, iclass 17, count 0 2006.173.21:29:36.27#ibcon#read 3, iclass 17, count 0 2006.173.21:29:36.27#ibcon#about to read 4, iclass 17, count 0 2006.173.21:29:36.27#ibcon#read 4, iclass 17, count 0 2006.173.21:29:36.27#ibcon#about to read 5, iclass 17, count 0 2006.173.21:29:36.27#ibcon#read 5, iclass 17, count 0 2006.173.21:29:36.27#ibcon#about to read 6, iclass 17, count 0 2006.173.21:29:36.27#ibcon#read 6, iclass 17, count 0 2006.173.21:29:36.27#ibcon#end of sib2, iclass 17, count 0 2006.173.21:29:36.27#ibcon#*after write, iclass 17, count 0 2006.173.21:29:36.27#ibcon#*before return 0, iclass 17, count 0 2006.173.21:29:36.27#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.21:29:36.27#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.21:29:36.27#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.21:29:36.27#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.21:29:36.27$vck44/vb=5,4 2006.173.21:29:36.27#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.21:29:36.27#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.21:29:36.27#ibcon#ireg 11 cls_cnt 2 2006.173.21:29:36.27#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.21:29:36.33#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.21:29:36.33#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.21:29:36.33#ibcon#enter wrdev, iclass 19, count 2 2006.173.21:29:36.33#ibcon#first serial, iclass 19, count 2 2006.173.21:29:36.33#ibcon#enter sib2, iclass 19, count 2 2006.173.21:29:36.33#ibcon#flushed, iclass 19, count 2 2006.173.21:29:36.33#ibcon#about to write, iclass 19, count 2 2006.173.21:29:36.33#ibcon#wrote, iclass 19, count 2 2006.173.21:29:36.33#ibcon#about to read 3, iclass 19, count 2 2006.173.21:29:36.35#ibcon#read 3, iclass 19, count 2 2006.173.21:29:36.35#ibcon#about to read 4, iclass 19, count 2 2006.173.21:29:36.35#ibcon#read 4, iclass 19, count 2 2006.173.21:29:36.35#ibcon#about to read 5, iclass 19, count 2 2006.173.21:29:36.35#ibcon#read 5, iclass 19, count 2 2006.173.21:29:36.35#ibcon#about to read 6, iclass 19, count 2 2006.173.21:29:36.35#ibcon#read 6, iclass 19, count 2 2006.173.21:29:36.35#ibcon#end of sib2, iclass 19, count 2 2006.173.21:29:36.35#ibcon#*mode == 0, iclass 19, count 2 2006.173.21:29:36.35#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.21:29:36.35#ibcon#[27=AT05-04\r\n] 2006.173.21:29:36.35#ibcon#*before write, iclass 19, count 2 2006.173.21:29:36.35#ibcon#enter sib2, iclass 19, count 2 2006.173.21:29:36.35#ibcon#flushed, iclass 19, count 2 2006.173.21:29:36.35#ibcon#about to write, iclass 19, count 2 2006.173.21:29:36.35#ibcon#wrote, iclass 19, count 2 2006.173.21:29:36.35#ibcon#about to read 3, iclass 19, count 2 2006.173.21:29:36.38#ibcon#read 3, iclass 19, count 2 2006.173.21:29:36.38#ibcon#about to read 4, iclass 19, count 2 2006.173.21:29:36.38#ibcon#read 4, iclass 19, count 2 2006.173.21:29:36.38#ibcon#about to read 5, iclass 19, count 2 2006.173.21:29:36.38#ibcon#read 5, iclass 19, count 2 2006.173.21:29:36.38#ibcon#about to read 6, iclass 19, count 2 2006.173.21:29:36.38#ibcon#read 6, iclass 19, count 2 2006.173.21:29:36.38#ibcon#end of sib2, iclass 19, count 2 2006.173.21:29:36.38#ibcon#*after write, iclass 19, count 2 2006.173.21:29:36.38#ibcon#*before return 0, iclass 19, count 2 2006.173.21:29:36.38#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.21:29:36.38#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.21:29:36.38#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.21:29:36.38#ibcon#ireg 7 cls_cnt 0 2006.173.21:29:36.38#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.21:29:36.50#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.21:29:36.50#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.21:29:36.50#ibcon#enter wrdev, iclass 19, count 0 2006.173.21:29:36.50#ibcon#first serial, iclass 19, count 0 2006.173.21:29:36.50#ibcon#enter sib2, iclass 19, count 0 2006.173.21:29:36.50#ibcon#flushed, iclass 19, count 0 2006.173.21:29:36.50#ibcon#about to write, iclass 19, count 0 2006.173.21:29:36.50#ibcon#wrote, iclass 19, count 0 2006.173.21:29:36.50#ibcon#about to read 3, iclass 19, count 0 2006.173.21:29:36.52#ibcon#read 3, iclass 19, count 0 2006.173.21:29:36.52#ibcon#about to read 4, iclass 19, count 0 2006.173.21:29:36.52#ibcon#read 4, iclass 19, count 0 2006.173.21:29:36.52#ibcon#about to read 5, iclass 19, count 0 2006.173.21:29:36.52#ibcon#read 5, iclass 19, count 0 2006.173.21:29:36.52#ibcon#about to read 6, iclass 19, count 0 2006.173.21:29:36.52#ibcon#read 6, iclass 19, count 0 2006.173.21:29:36.52#ibcon#end of sib2, iclass 19, count 0 2006.173.21:29:36.52#ibcon#*mode == 0, iclass 19, count 0 2006.173.21:29:36.52#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.21:29:36.52#ibcon#[27=USB\r\n] 2006.173.21:29:36.52#ibcon#*before write, iclass 19, count 0 2006.173.21:29:36.52#ibcon#enter sib2, iclass 19, count 0 2006.173.21:29:36.52#ibcon#flushed, iclass 19, count 0 2006.173.21:29:36.52#ibcon#about to write, iclass 19, count 0 2006.173.21:29:36.52#ibcon#wrote, iclass 19, count 0 2006.173.21:29:36.52#ibcon#about to read 3, iclass 19, count 0 2006.173.21:29:36.55#ibcon#read 3, iclass 19, count 0 2006.173.21:29:36.55#ibcon#about to read 4, iclass 19, count 0 2006.173.21:29:36.55#ibcon#read 4, iclass 19, count 0 2006.173.21:29:36.55#ibcon#about to read 5, iclass 19, count 0 2006.173.21:29:36.55#ibcon#read 5, iclass 19, count 0 2006.173.21:29:36.55#ibcon#about to read 6, iclass 19, count 0 2006.173.21:29:36.55#ibcon#read 6, iclass 19, count 0 2006.173.21:29:36.55#ibcon#end of sib2, iclass 19, count 0 2006.173.21:29:36.55#ibcon#*after write, iclass 19, count 0 2006.173.21:29:36.55#ibcon#*before return 0, iclass 19, count 0 2006.173.21:29:36.55#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.21:29:36.55#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.21:29:36.55#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.21:29:36.55#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.21:29:36.55$vck44/vblo=6,719.99 2006.173.21:29:36.55#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.21:29:36.55#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.21:29:36.55#ibcon#ireg 17 cls_cnt 0 2006.173.21:29:36.55#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.21:29:36.55#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.21:29:36.55#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.21:29:36.55#ibcon#enter wrdev, iclass 21, count 0 2006.173.21:29:36.55#ibcon#first serial, iclass 21, count 0 2006.173.21:29:36.55#ibcon#enter sib2, iclass 21, count 0 2006.173.21:29:36.55#ibcon#flushed, iclass 21, count 0 2006.173.21:29:36.55#ibcon#about to write, iclass 21, count 0 2006.173.21:29:36.55#ibcon#wrote, iclass 21, count 0 2006.173.21:29:36.55#ibcon#about to read 3, iclass 21, count 0 2006.173.21:29:36.57#ibcon#read 3, iclass 21, count 0 2006.173.21:29:36.57#ibcon#about to read 4, iclass 21, count 0 2006.173.21:29:36.57#ibcon#read 4, iclass 21, count 0 2006.173.21:29:36.57#ibcon#about to read 5, iclass 21, count 0 2006.173.21:29:36.57#ibcon#read 5, iclass 21, count 0 2006.173.21:29:36.57#ibcon#about to read 6, iclass 21, count 0 2006.173.21:29:36.57#ibcon#read 6, iclass 21, count 0 2006.173.21:29:36.57#ibcon#end of sib2, iclass 21, count 0 2006.173.21:29:36.57#ibcon#*mode == 0, iclass 21, count 0 2006.173.21:29:36.57#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.21:29:36.57#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.21:29:36.57#ibcon#*before write, iclass 21, count 0 2006.173.21:29:36.57#ibcon#enter sib2, iclass 21, count 0 2006.173.21:29:36.57#ibcon#flushed, iclass 21, count 0 2006.173.21:29:36.57#ibcon#about to write, iclass 21, count 0 2006.173.21:29:36.57#ibcon#wrote, iclass 21, count 0 2006.173.21:29:36.57#ibcon#about to read 3, iclass 21, count 0 2006.173.21:29:36.61#ibcon#read 3, iclass 21, count 0 2006.173.21:29:36.61#ibcon#about to read 4, iclass 21, count 0 2006.173.21:29:36.61#ibcon#read 4, iclass 21, count 0 2006.173.21:29:36.61#ibcon#about to read 5, iclass 21, count 0 2006.173.21:29:36.61#ibcon#read 5, iclass 21, count 0 2006.173.21:29:36.61#ibcon#about to read 6, iclass 21, count 0 2006.173.21:29:36.61#ibcon#read 6, iclass 21, count 0 2006.173.21:29:36.61#ibcon#end of sib2, iclass 21, count 0 2006.173.21:29:36.61#ibcon#*after write, iclass 21, count 0 2006.173.21:29:36.61#ibcon#*before return 0, iclass 21, count 0 2006.173.21:29:36.61#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.21:29:36.61#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.21:29:36.61#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.21:29:36.61#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.21:29:36.61$vck44/vb=6,4 2006.173.21:29:36.61#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.21:29:36.61#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.21:29:36.61#ibcon#ireg 11 cls_cnt 2 2006.173.21:29:36.61#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.21:29:36.67#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.21:29:36.67#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.21:29:36.67#ibcon#enter wrdev, iclass 23, count 2 2006.173.21:29:36.67#ibcon#first serial, iclass 23, count 2 2006.173.21:29:36.67#ibcon#enter sib2, iclass 23, count 2 2006.173.21:29:36.67#ibcon#flushed, iclass 23, count 2 2006.173.21:29:36.67#ibcon#about to write, iclass 23, count 2 2006.173.21:29:36.67#ibcon#wrote, iclass 23, count 2 2006.173.21:29:36.67#ibcon#about to read 3, iclass 23, count 2 2006.173.21:29:36.69#ibcon#read 3, iclass 23, count 2 2006.173.21:29:36.69#ibcon#about to read 4, iclass 23, count 2 2006.173.21:29:36.69#ibcon#read 4, iclass 23, count 2 2006.173.21:29:36.69#ibcon#about to read 5, iclass 23, count 2 2006.173.21:29:36.69#ibcon#read 5, iclass 23, count 2 2006.173.21:29:36.69#ibcon#about to read 6, iclass 23, count 2 2006.173.21:29:36.69#ibcon#read 6, iclass 23, count 2 2006.173.21:29:36.69#ibcon#end of sib2, iclass 23, count 2 2006.173.21:29:36.69#ibcon#*mode == 0, iclass 23, count 2 2006.173.21:29:36.69#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.21:29:36.69#ibcon#[27=AT06-04\r\n] 2006.173.21:29:36.69#ibcon#*before write, iclass 23, count 2 2006.173.21:29:36.69#ibcon#enter sib2, iclass 23, count 2 2006.173.21:29:36.69#ibcon#flushed, iclass 23, count 2 2006.173.21:29:36.69#ibcon#about to write, iclass 23, count 2 2006.173.21:29:36.69#ibcon#wrote, iclass 23, count 2 2006.173.21:29:36.69#ibcon#about to read 3, iclass 23, count 2 2006.173.21:29:36.72#ibcon#read 3, iclass 23, count 2 2006.173.21:29:36.72#ibcon#about to read 4, iclass 23, count 2 2006.173.21:29:36.72#ibcon#read 4, iclass 23, count 2 2006.173.21:29:36.72#ibcon#about to read 5, iclass 23, count 2 2006.173.21:29:36.72#ibcon#read 5, iclass 23, count 2 2006.173.21:29:36.72#ibcon#about to read 6, iclass 23, count 2 2006.173.21:29:36.72#ibcon#read 6, iclass 23, count 2 2006.173.21:29:36.72#ibcon#end of sib2, iclass 23, count 2 2006.173.21:29:36.72#ibcon#*after write, iclass 23, count 2 2006.173.21:29:36.72#ibcon#*before return 0, iclass 23, count 2 2006.173.21:29:36.72#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.21:29:36.72#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.21:29:36.72#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.21:29:36.72#ibcon#ireg 7 cls_cnt 0 2006.173.21:29:36.72#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.21:29:36.84#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.21:29:36.84#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.21:29:36.84#ibcon#enter wrdev, iclass 23, count 0 2006.173.21:29:36.84#ibcon#first serial, iclass 23, count 0 2006.173.21:29:36.84#ibcon#enter sib2, iclass 23, count 0 2006.173.21:29:36.84#ibcon#flushed, iclass 23, count 0 2006.173.21:29:36.84#ibcon#about to write, iclass 23, count 0 2006.173.21:29:36.84#ibcon#wrote, iclass 23, count 0 2006.173.21:29:36.84#ibcon#about to read 3, iclass 23, count 0 2006.173.21:29:36.86#ibcon#read 3, iclass 23, count 0 2006.173.21:29:36.86#ibcon#about to read 4, iclass 23, count 0 2006.173.21:29:36.86#ibcon#read 4, iclass 23, count 0 2006.173.21:29:36.86#ibcon#about to read 5, iclass 23, count 0 2006.173.21:29:36.86#ibcon#read 5, iclass 23, count 0 2006.173.21:29:36.86#ibcon#about to read 6, iclass 23, count 0 2006.173.21:29:36.86#ibcon#read 6, iclass 23, count 0 2006.173.21:29:36.86#ibcon#end of sib2, iclass 23, count 0 2006.173.21:29:36.86#ibcon#*mode == 0, iclass 23, count 0 2006.173.21:29:36.86#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.21:29:36.86#ibcon#[27=USB\r\n] 2006.173.21:29:36.86#ibcon#*before write, iclass 23, count 0 2006.173.21:29:36.86#ibcon#enter sib2, iclass 23, count 0 2006.173.21:29:36.86#ibcon#flushed, iclass 23, count 0 2006.173.21:29:36.86#ibcon#about to write, iclass 23, count 0 2006.173.21:29:36.86#ibcon#wrote, iclass 23, count 0 2006.173.21:29:36.86#ibcon#about to read 3, iclass 23, count 0 2006.173.21:29:36.89#ibcon#read 3, iclass 23, count 0 2006.173.21:29:36.89#ibcon#about to read 4, iclass 23, count 0 2006.173.21:29:36.89#ibcon#read 4, iclass 23, count 0 2006.173.21:29:36.89#ibcon#about to read 5, iclass 23, count 0 2006.173.21:29:36.89#ibcon#read 5, iclass 23, count 0 2006.173.21:29:36.89#ibcon#about to read 6, iclass 23, count 0 2006.173.21:29:36.89#ibcon#read 6, iclass 23, count 0 2006.173.21:29:36.89#ibcon#end of sib2, iclass 23, count 0 2006.173.21:29:36.89#ibcon#*after write, iclass 23, count 0 2006.173.21:29:36.89#ibcon#*before return 0, iclass 23, count 0 2006.173.21:29:36.89#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.21:29:36.89#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.21:29:36.89#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.21:29:36.89#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.21:29:36.89$vck44/vblo=7,734.99 2006.173.21:29:36.89#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.21:29:36.89#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.21:29:36.89#ibcon#ireg 17 cls_cnt 0 2006.173.21:29:36.89#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.21:29:36.89#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.21:29:36.89#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.21:29:36.89#ibcon#enter wrdev, iclass 25, count 0 2006.173.21:29:36.89#ibcon#first serial, iclass 25, count 0 2006.173.21:29:36.89#ibcon#enter sib2, iclass 25, count 0 2006.173.21:29:36.89#ibcon#flushed, iclass 25, count 0 2006.173.21:29:36.89#ibcon#about to write, iclass 25, count 0 2006.173.21:29:36.89#ibcon#wrote, iclass 25, count 0 2006.173.21:29:36.89#ibcon#about to read 3, iclass 25, count 0 2006.173.21:29:36.91#ibcon#read 3, iclass 25, count 0 2006.173.21:29:36.91#ibcon#about to read 4, iclass 25, count 0 2006.173.21:29:36.91#ibcon#read 4, iclass 25, count 0 2006.173.21:29:36.91#ibcon#about to read 5, iclass 25, count 0 2006.173.21:29:36.91#ibcon#read 5, iclass 25, count 0 2006.173.21:29:36.91#ibcon#about to read 6, iclass 25, count 0 2006.173.21:29:36.91#ibcon#read 6, iclass 25, count 0 2006.173.21:29:36.91#ibcon#end of sib2, iclass 25, count 0 2006.173.21:29:36.91#ibcon#*mode == 0, iclass 25, count 0 2006.173.21:29:36.91#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.21:29:36.91#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.21:29:36.91#ibcon#*before write, iclass 25, count 0 2006.173.21:29:36.91#ibcon#enter sib2, iclass 25, count 0 2006.173.21:29:36.91#ibcon#flushed, iclass 25, count 0 2006.173.21:29:36.91#ibcon#about to write, iclass 25, count 0 2006.173.21:29:36.91#ibcon#wrote, iclass 25, count 0 2006.173.21:29:36.91#ibcon#about to read 3, iclass 25, count 0 2006.173.21:29:36.95#ibcon#read 3, iclass 25, count 0 2006.173.21:29:36.95#ibcon#about to read 4, iclass 25, count 0 2006.173.21:29:36.95#ibcon#read 4, iclass 25, count 0 2006.173.21:29:36.95#ibcon#about to read 5, iclass 25, count 0 2006.173.21:29:36.95#ibcon#read 5, iclass 25, count 0 2006.173.21:29:36.95#ibcon#about to read 6, iclass 25, count 0 2006.173.21:29:36.95#ibcon#read 6, iclass 25, count 0 2006.173.21:29:36.95#ibcon#end of sib2, iclass 25, count 0 2006.173.21:29:36.95#ibcon#*after write, iclass 25, count 0 2006.173.21:29:36.95#ibcon#*before return 0, iclass 25, count 0 2006.173.21:29:36.95#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.21:29:36.95#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.21:29:36.95#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.21:29:36.95#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.21:29:36.95$vck44/vb=7,4 2006.173.21:29:36.95#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.21:29:36.95#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.21:29:36.95#ibcon#ireg 11 cls_cnt 2 2006.173.21:29:36.95#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.21:29:37.01#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.21:29:37.01#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.21:29:37.01#ibcon#enter wrdev, iclass 27, count 2 2006.173.21:29:37.01#ibcon#first serial, iclass 27, count 2 2006.173.21:29:37.01#ibcon#enter sib2, iclass 27, count 2 2006.173.21:29:37.01#ibcon#flushed, iclass 27, count 2 2006.173.21:29:37.01#ibcon#about to write, iclass 27, count 2 2006.173.21:29:37.01#ibcon#wrote, iclass 27, count 2 2006.173.21:29:37.01#ibcon#about to read 3, iclass 27, count 2 2006.173.21:29:37.03#ibcon#read 3, iclass 27, count 2 2006.173.21:29:37.03#ibcon#about to read 4, iclass 27, count 2 2006.173.21:29:37.03#ibcon#read 4, iclass 27, count 2 2006.173.21:29:37.03#ibcon#about to read 5, iclass 27, count 2 2006.173.21:29:37.03#ibcon#read 5, iclass 27, count 2 2006.173.21:29:37.03#ibcon#about to read 6, iclass 27, count 2 2006.173.21:29:37.03#ibcon#read 6, iclass 27, count 2 2006.173.21:29:37.03#ibcon#end of sib2, iclass 27, count 2 2006.173.21:29:37.03#ibcon#*mode == 0, iclass 27, count 2 2006.173.21:29:37.03#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.21:29:37.03#ibcon#[27=AT07-04\r\n] 2006.173.21:29:37.03#ibcon#*before write, iclass 27, count 2 2006.173.21:29:37.03#ibcon#enter sib2, iclass 27, count 2 2006.173.21:29:37.03#ibcon#flushed, iclass 27, count 2 2006.173.21:29:37.03#ibcon#about to write, iclass 27, count 2 2006.173.21:29:37.03#ibcon#wrote, iclass 27, count 2 2006.173.21:29:37.03#ibcon#about to read 3, iclass 27, count 2 2006.173.21:29:37.06#ibcon#read 3, iclass 27, count 2 2006.173.21:29:37.06#ibcon#about to read 4, iclass 27, count 2 2006.173.21:29:37.06#ibcon#read 4, iclass 27, count 2 2006.173.21:29:37.06#ibcon#about to read 5, iclass 27, count 2 2006.173.21:29:37.06#ibcon#read 5, iclass 27, count 2 2006.173.21:29:37.06#ibcon#about to read 6, iclass 27, count 2 2006.173.21:29:37.06#ibcon#read 6, iclass 27, count 2 2006.173.21:29:37.06#ibcon#end of sib2, iclass 27, count 2 2006.173.21:29:37.06#ibcon#*after write, iclass 27, count 2 2006.173.21:29:37.06#ibcon#*before return 0, iclass 27, count 2 2006.173.21:29:37.06#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.21:29:37.06#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.21:29:37.06#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.21:29:37.06#ibcon#ireg 7 cls_cnt 0 2006.173.21:29:37.06#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.21:29:37.18#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.21:29:37.18#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.21:29:37.18#ibcon#enter wrdev, iclass 27, count 0 2006.173.21:29:37.18#ibcon#first serial, iclass 27, count 0 2006.173.21:29:37.18#ibcon#enter sib2, iclass 27, count 0 2006.173.21:29:37.18#ibcon#flushed, iclass 27, count 0 2006.173.21:29:37.18#ibcon#about to write, iclass 27, count 0 2006.173.21:29:37.18#ibcon#wrote, iclass 27, count 0 2006.173.21:29:37.18#ibcon#about to read 3, iclass 27, count 0 2006.173.21:29:37.20#ibcon#read 3, iclass 27, count 0 2006.173.21:29:37.20#ibcon#about to read 4, iclass 27, count 0 2006.173.21:29:37.20#ibcon#read 4, iclass 27, count 0 2006.173.21:29:37.20#ibcon#about to read 5, iclass 27, count 0 2006.173.21:29:37.20#ibcon#read 5, iclass 27, count 0 2006.173.21:29:37.20#ibcon#about to read 6, iclass 27, count 0 2006.173.21:29:37.20#ibcon#read 6, iclass 27, count 0 2006.173.21:29:37.20#ibcon#end of sib2, iclass 27, count 0 2006.173.21:29:37.20#ibcon#*mode == 0, iclass 27, count 0 2006.173.21:29:37.20#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.21:29:37.20#ibcon#[27=USB\r\n] 2006.173.21:29:37.20#ibcon#*before write, iclass 27, count 0 2006.173.21:29:37.20#ibcon#enter sib2, iclass 27, count 0 2006.173.21:29:37.20#ibcon#flushed, iclass 27, count 0 2006.173.21:29:37.20#ibcon#about to write, iclass 27, count 0 2006.173.21:29:37.20#ibcon#wrote, iclass 27, count 0 2006.173.21:29:37.20#ibcon#about to read 3, iclass 27, count 0 2006.173.21:29:37.23#ibcon#read 3, iclass 27, count 0 2006.173.21:29:37.23#ibcon#about to read 4, iclass 27, count 0 2006.173.21:29:37.23#ibcon#read 4, iclass 27, count 0 2006.173.21:29:37.23#ibcon#about to read 5, iclass 27, count 0 2006.173.21:29:37.23#ibcon#read 5, iclass 27, count 0 2006.173.21:29:37.23#ibcon#about to read 6, iclass 27, count 0 2006.173.21:29:37.23#ibcon#read 6, iclass 27, count 0 2006.173.21:29:37.23#ibcon#end of sib2, iclass 27, count 0 2006.173.21:29:37.23#ibcon#*after write, iclass 27, count 0 2006.173.21:29:37.23#ibcon#*before return 0, iclass 27, count 0 2006.173.21:29:37.23#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.21:29:37.23#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.21:29:37.23#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.21:29:37.23#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.21:29:37.23$vck44/vblo=8,744.99 2006.173.21:29:37.23#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.21:29:37.23#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.21:29:37.23#ibcon#ireg 17 cls_cnt 0 2006.173.21:29:37.23#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.21:29:37.23#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.21:29:37.23#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.21:29:37.23#ibcon#enter wrdev, iclass 29, count 0 2006.173.21:29:37.23#ibcon#first serial, iclass 29, count 0 2006.173.21:29:37.23#ibcon#enter sib2, iclass 29, count 0 2006.173.21:29:37.23#ibcon#flushed, iclass 29, count 0 2006.173.21:29:37.23#ibcon#about to write, iclass 29, count 0 2006.173.21:29:37.23#ibcon#wrote, iclass 29, count 0 2006.173.21:29:37.23#ibcon#about to read 3, iclass 29, count 0 2006.173.21:29:37.25#ibcon#read 3, iclass 29, count 0 2006.173.21:29:37.25#ibcon#about to read 4, iclass 29, count 0 2006.173.21:29:37.25#ibcon#read 4, iclass 29, count 0 2006.173.21:29:37.25#ibcon#about to read 5, iclass 29, count 0 2006.173.21:29:37.25#ibcon#read 5, iclass 29, count 0 2006.173.21:29:37.25#ibcon#about to read 6, iclass 29, count 0 2006.173.21:29:37.25#ibcon#read 6, iclass 29, count 0 2006.173.21:29:37.25#ibcon#end of sib2, iclass 29, count 0 2006.173.21:29:37.25#ibcon#*mode == 0, iclass 29, count 0 2006.173.21:29:37.25#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.21:29:37.25#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.21:29:37.25#ibcon#*before write, iclass 29, count 0 2006.173.21:29:37.25#ibcon#enter sib2, iclass 29, count 0 2006.173.21:29:37.25#ibcon#flushed, iclass 29, count 0 2006.173.21:29:37.25#ibcon#about to write, iclass 29, count 0 2006.173.21:29:37.25#ibcon#wrote, iclass 29, count 0 2006.173.21:29:37.25#ibcon#about to read 3, iclass 29, count 0 2006.173.21:29:37.29#ibcon#read 3, iclass 29, count 0 2006.173.21:29:37.29#ibcon#about to read 4, iclass 29, count 0 2006.173.21:29:37.29#ibcon#read 4, iclass 29, count 0 2006.173.21:29:37.29#ibcon#about to read 5, iclass 29, count 0 2006.173.21:29:37.29#ibcon#read 5, iclass 29, count 0 2006.173.21:29:37.29#ibcon#about to read 6, iclass 29, count 0 2006.173.21:29:37.29#ibcon#read 6, iclass 29, count 0 2006.173.21:29:37.29#ibcon#end of sib2, iclass 29, count 0 2006.173.21:29:37.29#ibcon#*after write, iclass 29, count 0 2006.173.21:29:37.29#ibcon#*before return 0, iclass 29, count 0 2006.173.21:29:37.29#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.21:29:37.29#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.21:29:37.29#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.21:29:37.29#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.21:29:37.29$vck44/vb=8,4 2006.173.21:29:37.29#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.21:29:37.29#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.21:29:37.29#ibcon#ireg 11 cls_cnt 2 2006.173.21:29:37.29#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.21:29:37.35#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.21:29:37.35#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.21:29:37.35#ibcon#enter wrdev, iclass 31, count 2 2006.173.21:29:37.35#ibcon#first serial, iclass 31, count 2 2006.173.21:29:37.35#ibcon#enter sib2, iclass 31, count 2 2006.173.21:29:37.35#ibcon#flushed, iclass 31, count 2 2006.173.21:29:37.35#ibcon#about to write, iclass 31, count 2 2006.173.21:29:37.35#ibcon#wrote, iclass 31, count 2 2006.173.21:29:37.35#ibcon#about to read 3, iclass 31, count 2 2006.173.21:29:37.37#ibcon#read 3, iclass 31, count 2 2006.173.21:29:37.37#ibcon#about to read 4, iclass 31, count 2 2006.173.21:29:37.37#ibcon#read 4, iclass 31, count 2 2006.173.21:29:37.37#ibcon#about to read 5, iclass 31, count 2 2006.173.21:29:37.37#ibcon#read 5, iclass 31, count 2 2006.173.21:29:37.37#ibcon#about to read 6, iclass 31, count 2 2006.173.21:29:37.37#ibcon#read 6, iclass 31, count 2 2006.173.21:29:37.37#ibcon#end of sib2, iclass 31, count 2 2006.173.21:29:37.37#ibcon#*mode == 0, iclass 31, count 2 2006.173.21:29:37.37#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.21:29:37.37#ibcon#[27=AT08-04\r\n] 2006.173.21:29:37.37#ibcon#*before write, iclass 31, count 2 2006.173.21:29:37.37#ibcon#enter sib2, iclass 31, count 2 2006.173.21:29:37.37#ibcon#flushed, iclass 31, count 2 2006.173.21:29:37.37#ibcon#about to write, iclass 31, count 2 2006.173.21:29:37.37#ibcon#wrote, iclass 31, count 2 2006.173.21:29:37.37#ibcon#about to read 3, iclass 31, count 2 2006.173.21:29:37.40#ibcon#read 3, iclass 31, count 2 2006.173.21:29:37.40#ibcon#about to read 4, iclass 31, count 2 2006.173.21:29:37.40#ibcon#read 4, iclass 31, count 2 2006.173.21:29:37.40#ibcon#about to read 5, iclass 31, count 2 2006.173.21:29:37.40#ibcon#read 5, iclass 31, count 2 2006.173.21:29:37.40#ibcon#about to read 6, iclass 31, count 2 2006.173.21:29:37.40#ibcon#read 6, iclass 31, count 2 2006.173.21:29:37.40#ibcon#end of sib2, iclass 31, count 2 2006.173.21:29:37.40#ibcon#*after write, iclass 31, count 2 2006.173.21:29:37.40#ibcon#*before return 0, iclass 31, count 2 2006.173.21:29:37.40#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.21:29:37.40#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.21:29:37.40#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.21:29:37.40#ibcon#ireg 7 cls_cnt 0 2006.173.21:29:37.40#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.21:29:37.52#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.21:29:37.52#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.21:29:37.52#ibcon#enter wrdev, iclass 31, count 0 2006.173.21:29:37.52#ibcon#first serial, iclass 31, count 0 2006.173.21:29:37.52#ibcon#enter sib2, iclass 31, count 0 2006.173.21:29:37.52#ibcon#flushed, iclass 31, count 0 2006.173.21:29:37.52#ibcon#about to write, iclass 31, count 0 2006.173.21:29:37.52#ibcon#wrote, iclass 31, count 0 2006.173.21:29:37.52#ibcon#about to read 3, iclass 31, count 0 2006.173.21:29:37.54#ibcon#read 3, iclass 31, count 0 2006.173.21:29:37.54#ibcon#about to read 4, iclass 31, count 0 2006.173.21:29:37.54#ibcon#read 4, iclass 31, count 0 2006.173.21:29:37.54#ibcon#about to read 5, iclass 31, count 0 2006.173.21:29:37.54#ibcon#read 5, iclass 31, count 0 2006.173.21:29:37.54#ibcon#about to read 6, iclass 31, count 0 2006.173.21:29:37.54#ibcon#read 6, iclass 31, count 0 2006.173.21:29:37.54#ibcon#end of sib2, iclass 31, count 0 2006.173.21:29:37.54#ibcon#*mode == 0, iclass 31, count 0 2006.173.21:29:37.54#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.21:29:37.54#ibcon#[27=USB\r\n] 2006.173.21:29:37.54#ibcon#*before write, iclass 31, count 0 2006.173.21:29:37.54#ibcon#enter sib2, iclass 31, count 0 2006.173.21:29:37.54#ibcon#flushed, iclass 31, count 0 2006.173.21:29:37.54#ibcon#about to write, iclass 31, count 0 2006.173.21:29:37.54#ibcon#wrote, iclass 31, count 0 2006.173.21:29:37.54#ibcon#about to read 3, iclass 31, count 0 2006.173.21:29:37.57#ibcon#read 3, iclass 31, count 0 2006.173.21:29:37.57#ibcon#about to read 4, iclass 31, count 0 2006.173.21:29:37.57#ibcon#read 4, iclass 31, count 0 2006.173.21:29:37.57#ibcon#about to read 5, iclass 31, count 0 2006.173.21:29:37.57#ibcon#read 5, iclass 31, count 0 2006.173.21:29:37.57#ibcon#about to read 6, iclass 31, count 0 2006.173.21:29:37.57#ibcon#read 6, iclass 31, count 0 2006.173.21:29:37.57#ibcon#end of sib2, iclass 31, count 0 2006.173.21:29:37.57#ibcon#*after write, iclass 31, count 0 2006.173.21:29:37.57#ibcon#*before return 0, iclass 31, count 0 2006.173.21:29:37.57#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.21:29:37.57#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.21:29:37.57#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.21:29:37.57#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.21:29:37.57$vck44/vabw=wide 2006.173.21:29:37.57#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.21:29:37.57#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.21:29:37.57#ibcon#ireg 8 cls_cnt 0 2006.173.21:29:37.57#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.21:29:37.57#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.21:29:37.57#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.21:29:37.57#ibcon#enter wrdev, iclass 33, count 0 2006.173.21:29:37.57#ibcon#first serial, iclass 33, count 0 2006.173.21:29:37.57#ibcon#enter sib2, iclass 33, count 0 2006.173.21:29:37.57#ibcon#flushed, iclass 33, count 0 2006.173.21:29:37.57#ibcon#about to write, iclass 33, count 0 2006.173.21:29:37.57#ibcon#wrote, iclass 33, count 0 2006.173.21:29:37.57#ibcon#about to read 3, iclass 33, count 0 2006.173.21:29:37.59#ibcon#read 3, iclass 33, count 0 2006.173.21:29:37.59#ibcon#about to read 4, iclass 33, count 0 2006.173.21:29:37.59#ibcon#read 4, iclass 33, count 0 2006.173.21:29:37.59#ibcon#about to read 5, iclass 33, count 0 2006.173.21:29:37.59#ibcon#read 5, iclass 33, count 0 2006.173.21:29:37.59#ibcon#about to read 6, iclass 33, count 0 2006.173.21:29:37.59#ibcon#read 6, iclass 33, count 0 2006.173.21:29:37.59#ibcon#end of sib2, iclass 33, count 0 2006.173.21:29:37.59#ibcon#*mode == 0, iclass 33, count 0 2006.173.21:29:37.59#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.21:29:37.59#ibcon#[25=BW32\r\n] 2006.173.21:29:37.59#ibcon#*before write, iclass 33, count 0 2006.173.21:29:37.59#ibcon#enter sib2, iclass 33, count 0 2006.173.21:29:37.59#ibcon#flushed, iclass 33, count 0 2006.173.21:29:37.59#ibcon#about to write, iclass 33, count 0 2006.173.21:29:37.59#ibcon#wrote, iclass 33, count 0 2006.173.21:29:37.59#ibcon#about to read 3, iclass 33, count 0 2006.173.21:29:37.62#ibcon#read 3, iclass 33, count 0 2006.173.21:29:37.62#ibcon#about to read 4, iclass 33, count 0 2006.173.21:29:37.62#ibcon#read 4, iclass 33, count 0 2006.173.21:29:37.62#ibcon#about to read 5, iclass 33, count 0 2006.173.21:29:37.62#ibcon#read 5, iclass 33, count 0 2006.173.21:29:37.62#ibcon#about to read 6, iclass 33, count 0 2006.173.21:29:37.62#ibcon#read 6, iclass 33, count 0 2006.173.21:29:37.62#ibcon#end of sib2, iclass 33, count 0 2006.173.21:29:37.62#ibcon#*after write, iclass 33, count 0 2006.173.21:29:37.62#ibcon#*before return 0, iclass 33, count 0 2006.173.21:29:37.62#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.21:29:37.62#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.21:29:37.62#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.21:29:37.62#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.21:29:37.62$vck44/vbbw=wide 2006.173.21:29:37.62#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.21:29:37.62#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.21:29:37.62#ibcon#ireg 8 cls_cnt 0 2006.173.21:29:37.62#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.21:29:37.69#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.21:29:37.69#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.21:29:37.69#ibcon#enter wrdev, iclass 35, count 0 2006.173.21:29:37.69#ibcon#first serial, iclass 35, count 0 2006.173.21:29:37.69#ibcon#enter sib2, iclass 35, count 0 2006.173.21:29:37.69#ibcon#flushed, iclass 35, count 0 2006.173.21:29:37.69#ibcon#about to write, iclass 35, count 0 2006.173.21:29:37.69#ibcon#wrote, iclass 35, count 0 2006.173.21:29:37.69#ibcon#about to read 3, iclass 35, count 0 2006.173.21:29:37.71#ibcon#read 3, iclass 35, count 0 2006.173.21:29:37.71#ibcon#about to read 4, iclass 35, count 0 2006.173.21:29:37.71#ibcon#read 4, iclass 35, count 0 2006.173.21:29:37.71#ibcon#about to read 5, iclass 35, count 0 2006.173.21:29:37.71#ibcon#read 5, iclass 35, count 0 2006.173.21:29:37.71#ibcon#about to read 6, iclass 35, count 0 2006.173.21:29:37.71#ibcon#read 6, iclass 35, count 0 2006.173.21:29:37.71#ibcon#end of sib2, iclass 35, count 0 2006.173.21:29:37.71#ibcon#*mode == 0, iclass 35, count 0 2006.173.21:29:37.71#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.21:29:37.71#ibcon#[27=BW32\r\n] 2006.173.21:29:37.71#ibcon#*before write, iclass 35, count 0 2006.173.21:29:37.71#ibcon#enter sib2, iclass 35, count 0 2006.173.21:29:37.71#ibcon#flushed, iclass 35, count 0 2006.173.21:29:37.71#ibcon#about to write, iclass 35, count 0 2006.173.21:29:37.71#ibcon#wrote, iclass 35, count 0 2006.173.21:29:37.71#ibcon#about to read 3, iclass 35, count 0 2006.173.21:29:37.74#ibcon#read 3, iclass 35, count 0 2006.173.21:29:37.74#ibcon#about to read 4, iclass 35, count 0 2006.173.21:29:37.74#ibcon#read 4, iclass 35, count 0 2006.173.21:29:37.74#ibcon#about to read 5, iclass 35, count 0 2006.173.21:29:37.74#ibcon#read 5, iclass 35, count 0 2006.173.21:29:37.74#ibcon#about to read 6, iclass 35, count 0 2006.173.21:29:37.74#ibcon#read 6, iclass 35, count 0 2006.173.21:29:37.74#ibcon#end of sib2, iclass 35, count 0 2006.173.21:29:37.74#ibcon#*after write, iclass 35, count 0 2006.173.21:29:37.74#ibcon#*before return 0, iclass 35, count 0 2006.173.21:29:37.74#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.21:29:37.74#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.21:29:37.74#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.21:29:37.74#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.21:29:37.74$setupk4/ifdk4 2006.173.21:29:37.74$ifdk4/lo= 2006.173.21:29:37.74$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.21:29:37.74$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.21:29:37.74$ifdk4/patch= 2006.173.21:29:37.74$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.21:29:37.74$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.21:29:37.74$setupk4/!*+20s 2006.173.21:29:38.45#abcon#<5=/10 0.5 1.1 21.031001003.1\r\n> 2006.173.21:29:38.47#abcon#{5=INTERFACE CLEAR} 2006.173.21:29:38.53#abcon#[5=S1D000X0/0*\r\n] 2006.173.21:29:48.62#abcon#<5=/10 0.5 1.1 21.041001003.1\r\n> 2006.173.21:29:48.64#abcon#{5=INTERFACE CLEAR} 2006.173.21:29:48.70#abcon#[5=S1D000X0/0*\r\n] 2006.173.21:29:52.25$setupk4/"tpicd 2006.173.21:29:52.25$setupk4/echo=off 2006.173.21:29:52.25$setupk4/xlog=off 2006.173.21:29:52.25:!2006.173.21:31:58 2006.173.21:29:53.14#trakl#Source acquired 2006.173.21:29:54.14#flagr#flagr/antenna,acquired 2006.173.21:31:58.00:preob 2006.173.21:31:58.14/onsource/TRACKING 2006.173.21:31:58.14:!2006.173.21:32:08 2006.173.21:32:08.00:"tape 2006.173.21:32:08.00:"st=record 2006.173.21:32:08.00:data_valid=on 2006.173.21:32:08.00:midob 2006.173.21:32:09.14/onsource/TRACKING 2006.173.21:32:09.14/wx/21.07,1003.2,100 2006.173.21:32:09.29/cable/+6.5152E-03 2006.173.21:32:10.38/va/01,07,usb,yes,34,37 2006.173.21:32:10.38/va/02,06,usb,yes,34,35 2006.173.21:32:10.38/va/03,05,usb,yes,43,45 2006.173.21:32:10.38/va/04,06,usb,yes,35,36 2006.173.21:32:10.38/va/05,04,usb,yes,27,27 2006.173.21:32:10.38/va/06,03,usb,yes,38,38 2006.173.21:32:10.38/va/07,04,usb,yes,31,32 2006.173.21:32:10.38/va/08,04,usb,yes,26,31 2006.173.21:32:10.61/valo/01,524.99,yes,locked 2006.173.21:32:10.61/valo/02,534.99,yes,locked 2006.173.21:32:10.61/valo/03,564.99,yes,locked 2006.173.21:32:10.61/valo/04,624.99,yes,locked 2006.173.21:32:10.61/valo/05,734.99,yes,locked 2006.173.21:32:10.61/valo/06,814.99,yes,locked 2006.173.21:32:10.61/valo/07,864.99,yes,locked 2006.173.21:32:10.61/valo/08,884.99,yes,locked 2006.173.21:32:11.70/vb/01,04,usb,yes,29,27 2006.173.21:32:11.70/vb/02,04,usb,yes,31,31 2006.173.21:32:11.70/vb/03,04,usb,yes,28,31 2006.173.21:32:11.70/vb/04,04,usb,yes,32,31 2006.173.21:32:11.70/vb/05,04,usb,yes,25,27 2006.173.21:32:11.70/vb/06,04,usb,yes,29,26 2006.173.21:32:11.70/vb/07,04,usb,yes,29,29 2006.173.21:32:11.70/vb/08,04,usb,yes,27,30 2006.173.21:32:11.93/vblo/01,629.99,yes,locked 2006.173.21:32:11.93/vblo/02,634.99,yes,locked 2006.173.21:32:11.93/vblo/03,649.99,yes,locked 2006.173.21:32:11.93/vblo/04,679.99,yes,locked 2006.173.21:32:11.93/vblo/05,709.99,yes,locked 2006.173.21:32:11.93/vblo/06,719.99,yes,locked 2006.173.21:32:11.93/vblo/07,734.99,yes,locked 2006.173.21:32:11.93/vblo/08,744.99,yes,locked 2006.173.21:32:12.08/vabw/8 2006.173.21:32:12.23/vbbw/8 2006.173.21:32:12.32/xfe/off,on,14.7 2006.173.21:32:12.71/ifatt/23,28,28,28 2006.173.21:32:13.08/fmout-gps/S +3.90E-07 2006.173.21:32:13.12:!2006.173.21:35:38 2006.173.21:35:38.00:data_valid=off 2006.173.21:35:38.00:"et 2006.173.21:35:38.00:!+3s 2006.173.21:35:41.01:"tape 2006.173.21:35:41.01:postob 2006.173.21:35:41.16/cable/+6.5163E-03 2006.173.21:35:41.16/wx/21.22,1003.3,100 2006.173.21:35:42.07/fmout-gps/S +3.92E-07 2006.173.21:35:42.07:scan_name=173-2138,jd0606,560 2006.173.21:35:42.07:source=0133+476,013658.59,475129.1,2000.0,cw 2006.173.21:35:42.13#flagr#flagr/antenna,new-source 2006.173.21:35:43.13:checkk5 2006.173.21:35:43.47/chk_autoobs//k5ts1/ autoobs is running! 2006.173.21:35:43.86/chk_autoobs//k5ts2/ autoobs is running! 2006.173.21:35:44.27/chk_autoobs//k5ts3/ autoobs is running! 2006.173.21:35:44.68/chk_autoobs//k5ts4/ autoobs is running! 2006.173.21:35:45.07/chk_obsdata//k5ts1/T1732132??a.dat file size is correct (nominal:840MB, actual:836MB). 2006.173.21:35:45.47/chk_obsdata//k5ts2/T1732132??b.dat file size is correct (nominal:840MB, actual:836MB). 2006.173.21:35:45.86/chk_obsdata//k5ts3/T1732132??c.dat file size is correct (nominal:840MB, actual:836MB). 2006.173.21:35:46.27/chk_obsdata//k5ts4/T1732132??d.dat file size is correct (nominal:840MB, actual:836MB). 2006.173.21:35:47.01/k5log//k5ts1_log_newline 2006.173.21:35:47.71/k5log//k5ts2_log_newline 2006.173.21:35:48.43/k5log//k5ts3_log_newline 2006.173.21:35:49.14/k5log//k5ts4_log_newline 2006.173.21:35:49.16/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.21:35:49.16:setupk4=1 2006.173.21:35:49.16$setupk4/echo=on 2006.173.21:35:49.16$setupk4/pcalon 2006.173.21:35:49.16$pcalon/"no phase cal control is implemented here 2006.173.21:35:49.16$setupk4/"tpicd=stop 2006.173.21:35:49.16$setupk4/"rec=synch_on 2006.173.21:35:49.16$setupk4/"rec_mode=128 2006.173.21:35:49.16$setupk4/!* 2006.173.21:35:49.16$setupk4/recpk4 2006.173.21:35:49.16$recpk4/recpatch= 2006.173.21:35:49.16$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.21:35:49.16$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.21:35:49.16$setupk4/vck44 2006.173.21:35:49.16$vck44/valo=1,524.99 2006.173.21:35:49.16#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.21:35:49.16#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.21:35:49.16#ibcon#ireg 17 cls_cnt 0 2006.173.21:35:49.16#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.21:35:49.16#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.21:35:49.16#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.21:35:49.16#ibcon#enter wrdev, iclass 6, count 0 2006.173.21:35:49.16#ibcon#first serial, iclass 6, count 0 2006.173.21:35:49.16#ibcon#enter sib2, iclass 6, count 0 2006.173.21:35:49.16#ibcon#flushed, iclass 6, count 0 2006.173.21:35:49.16#ibcon#about to write, iclass 6, count 0 2006.173.21:35:49.16#ibcon#wrote, iclass 6, count 0 2006.173.21:35:49.16#ibcon#about to read 3, iclass 6, count 0 2006.173.21:35:49.18#ibcon#read 3, iclass 6, count 0 2006.173.21:35:49.18#ibcon#about to read 4, iclass 6, count 0 2006.173.21:35:49.18#ibcon#read 4, iclass 6, count 0 2006.173.21:35:49.18#ibcon#about to read 5, iclass 6, count 0 2006.173.21:35:49.18#ibcon#read 5, iclass 6, count 0 2006.173.21:35:49.18#ibcon#about to read 6, iclass 6, count 0 2006.173.21:35:49.18#ibcon#read 6, iclass 6, count 0 2006.173.21:35:49.18#ibcon#end of sib2, iclass 6, count 0 2006.173.21:35:49.18#ibcon#*mode == 0, iclass 6, count 0 2006.173.21:35:49.18#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.21:35:49.18#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.21:35:49.18#ibcon#*before write, iclass 6, count 0 2006.173.21:35:49.18#ibcon#enter sib2, iclass 6, count 0 2006.173.21:35:49.18#ibcon#flushed, iclass 6, count 0 2006.173.21:35:49.18#ibcon#about to write, iclass 6, count 0 2006.173.21:35:49.18#ibcon#wrote, iclass 6, count 0 2006.173.21:35:49.18#ibcon#about to read 3, iclass 6, count 0 2006.173.21:35:49.23#ibcon#read 3, iclass 6, count 0 2006.173.21:35:49.23#ibcon#about to read 4, iclass 6, count 0 2006.173.21:35:49.23#ibcon#read 4, iclass 6, count 0 2006.173.21:35:49.23#ibcon#about to read 5, iclass 6, count 0 2006.173.21:35:49.23#ibcon#read 5, iclass 6, count 0 2006.173.21:35:49.23#ibcon#about to read 6, iclass 6, count 0 2006.173.21:35:49.23#ibcon#read 6, iclass 6, count 0 2006.173.21:35:49.23#ibcon#end of sib2, iclass 6, count 0 2006.173.21:35:49.23#ibcon#*after write, iclass 6, count 0 2006.173.21:35:49.23#ibcon#*before return 0, iclass 6, count 0 2006.173.21:35:49.23#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.21:35:49.23#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.21:35:49.23#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.21:35:49.23#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.21:35:49.23$vck44/va=1,7 2006.173.21:35:49.23#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.21:35:49.23#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.21:35:49.23#ibcon#ireg 11 cls_cnt 2 2006.173.21:35:49.23#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.21:35:49.23#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.21:35:49.23#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.21:35:49.23#ibcon#enter wrdev, iclass 10, count 2 2006.173.21:35:49.23#ibcon#first serial, iclass 10, count 2 2006.173.21:35:49.23#ibcon#enter sib2, iclass 10, count 2 2006.173.21:35:49.23#ibcon#flushed, iclass 10, count 2 2006.173.21:35:49.23#ibcon#about to write, iclass 10, count 2 2006.173.21:35:49.23#ibcon#wrote, iclass 10, count 2 2006.173.21:35:49.23#ibcon#about to read 3, iclass 10, count 2 2006.173.21:35:49.25#ibcon#read 3, iclass 10, count 2 2006.173.21:35:49.25#ibcon#about to read 4, iclass 10, count 2 2006.173.21:35:49.25#ibcon#read 4, iclass 10, count 2 2006.173.21:35:49.25#ibcon#about to read 5, iclass 10, count 2 2006.173.21:35:49.25#ibcon#read 5, iclass 10, count 2 2006.173.21:35:49.25#ibcon#about to read 6, iclass 10, count 2 2006.173.21:35:49.25#ibcon#read 6, iclass 10, count 2 2006.173.21:35:49.25#ibcon#end of sib2, iclass 10, count 2 2006.173.21:35:49.25#ibcon#*mode == 0, iclass 10, count 2 2006.173.21:35:49.25#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.21:35:49.25#ibcon#[25=AT01-07\r\n] 2006.173.21:35:49.25#ibcon#*before write, iclass 10, count 2 2006.173.21:35:49.25#ibcon#enter sib2, iclass 10, count 2 2006.173.21:35:49.25#ibcon#flushed, iclass 10, count 2 2006.173.21:35:49.25#ibcon#about to write, iclass 10, count 2 2006.173.21:35:49.25#ibcon#wrote, iclass 10, count 2 2006.173.21:35:49.25#ibcon#about to read 3, iclass 10, count 2 2006.173.21:35:49.28#ibcon#read 3, iclass 10, count 2 2006.173.21:35:49.28#ibcon#about to read 4, iclass 10, count 2 2006.173.21:35:49.28#ibcon#read 4, iclass 10, count 2 2006.173.21:35:49.28#ibcon#about to read 5, iclass 10, count 2 2006.173.21:35:49.28#ibcon#read 5, iclass 10, count 2 2006.173.21:35:49.28#ibcon#about to read 6, iclass 10, count 2 2006.173.21:35:49.28#ibcon#read 6, iclass 10, count 2 2006.173.21:35:49.28#ibcon#end of sib2, iclass 10, count 2 2006.173.21:35:49.28#ibcon#*after write, iclass 10, count 2 2006.173.21:35:49.28#ibcon#*before return 0, iclass 10, count 2 2006.173.21:35:49.28#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.21:35:49.28#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.21:35:49.28#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.21:35:49.28#ibcon#ireg 7 cls_cnt 0 2006.173.21:35:49.28#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.21:35:49.40#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.21:35:49.40#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.21:35:49.40#ibcon#enter wrdev, iclass 10, count 0 2006.173.21:35:49.40#ibcon#first serial, iclass 10, count 0 2006.173.21:35:49.40#ibcon#enter sib2, iclass 10, count 0 2006.173.21:35:49.40#ibcon#flushed, iclass 10, count 0 2006.173.21:35:49.40#ibcon#about to write, iclass 10, count 0 2006.173.21:35:49.40#ibcon#wrote, iclass 10, count 0 2006.173.21:35:49.40#ibcon#about to read 3, iclass 10, count 0 2006.173.21:35:49.42#ibcon#read 3, iclass 10, count 0 2006.173.21:35:49.42#ibcon#about to read 4, iclass 10, count 0 2006.173.21:35:49.42#ibcon#read 4, iclass 10, count 0 2006.173.21:35:49.42#ibcon#about to read 5, iclass 10, count 0 2006.173.21:35:49.42#ibcon#read 5, iclass 10, count 0 2006.173.21:35:49.42#ibcon#about to read 6, iclass 10, count 0 2006.173.21:35:49.42#ibcon#read 6, iclass 10, count 0 2006.173.21:35:49.42#ibcon#end of sib2, iclass 10, count 0 2006.173.21:35:49.42#ibcon#*mode == 0, iclass 10, count 0 2006.173.21:35:49.42#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.21:35:49.42#ibcon#[25=USB\r\n] 2006.173.21:35:49.42#ibcon#*before write, iclass 10, count 0 2006.173.21:35:49.42#ibcon#enter sib2, iclass 10, count 0 2006.173.21:35:49.42#ibcon#flushed, iclass 10, count 0 2006.173.21:35:49.42#ibcon#about to write, iclass 10, count 0 2006.173.21:35:49.42#ibcon#wrote, iclass 10, count 0 2006.173.21:35:49.42#ibcon#about to read 3, iclass 10, count 0 2006.173.21:35:49.45#ibcon#read 3, iclass 10, count 0 2006.173.21:35:49.45#ibcon#about to read 4, iclass 10, count 0 2006.173.21:35:49.45#ibcon#read 4, iclass 10, count 0 2006.173.21:35:49.45#ibcon#about to read 5, iclass 10, count 0 2006.173.21:35:49.45#ibcon#read 5, iclass 10, count 0 2006.173.21:35:49.45#ibcon#about to read 6, iclass 10, count 0 2006.173.21:35:49.45#ibcon#read 6, iclass 10, count 0 2006.173.21:35:49.45#ibcon#end of sib2, iclass 10, count 0 2006.173.21:35:49.45#ibcon#*after write, iclass 10, count 0 2006.173.21:35:49.45#ibcon#*before return 0, iclass 10, count 0 2006.173.21:35:49.45#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.21:35:49.45#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.21:35:49.45#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.21:35:49.45#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.21:35:49.45$vck44/valo=2,534.99 2006.173.21:35:49.45#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.21:35:49.45#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.21:35:49.45#ibcon#ireg 17 cls_cnt 0 2006.173.21:35:49.45#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.21:35:49.45#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.21:35:49.45#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.21:35:49.45#ibcon#enter wrdev, iclass 12, count 0 2006.173.21:35:49.45#ibcon#first serial, iclass 12, count 0 2006.173.21:35:49.45#ibcon#enter sib2, iclass 12, count 0 2006.173.21:35:49.45#ibcon#flushed, iclass 12, count 0 2006.173.21:35:49.45#ibcon#about to write, iclass 12, count 0 2006.173.21:35:49.45#ibcon#wrote, iclass 12, count 0 2006.173.21:35:49.45#ibcon#about to read 3, iclass 12, count 0 2006.173.21:35:49.47#ibcon#read 3, iclass 12, count 0 2006.173.21:35:49.47#ibcon#about to read 4, iclass 12, count 0 2006.173.21:35:49.47#ibcon#read 4, iclass 12, count 0 2006.173.21:35:49.47#ibcon#about to read 5, iclass 12, count 0 2006.173.21:35:49.47#ibcon#read 5, iclass 12, count 0 2006.173.21:35:49.47#ibcon#about to read 6, iclass 12, count 0 2006.173.21:35:49.47#ibcon#read 6, iclass 12, count 0 2006.173.21:35:49.47#ibcon#end of sib2, iclass 12, count 0 2006.173.21:35:49.47#ibcon#*mode == 0, iclass 12, count 0 2006.173.21:35:49.47#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.21:35:49.47#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.21:35:49.47#ibcon#*before write, iclass 12, count 0 2006.173.21:35:49.47#ibcon#enter sib2, iclass 12, count 0 2006.173.21:35:49.47#ibcon#flushed, iclass 12, count 0 2006.173.21:35:49.47#ibcon#about to write, iclass 12, count 0 2006.173.21:35:49.47#ibcon#wrote, iclass 12, count 0 2006.173.21:35:49.47#ibcon#about to read 3, iclass 12, count 0 2006.173.21:35:49.51#ibcon#read 3, iclass 12, count 0 2006.173.21:35:49.51#ibcon#about to read 4, iclass 12, count 0 2006.173.21:35:49.51#ibcon#read 4, iclass 12, count 0 2006.173.21:35:49.51#ibcon#about to read 5, iclass 12, count 0 2006.173.21:35:49.51#ibcon#read 5, iclass 12, count 0 2006.173.21:35:49.51#ibcon#about to read 6, iclass 12, count 0 2006.173.21:35:49.51#ibcon#read 6, iclass 12, count 0 2006.173.21:35:49.51#ibcon#end of sib2, iclass 12, count 0 2006.173.21:35:49.51#ibcon#*after write, iclass 12, count 0 2006.173.21:35:49.51#ibcon#*before return 0, iclass 12, count 0 2006.173.21:35:49.51#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.21:35:49.51#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.21:35:49.51#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.21:35:49.51#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.21:35:49.51$vck44/va=2,6 2006.173.21:35:49.51#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.21:35:49.51#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.21:35:49.51#ibcon#ireg 11 cls_cnt 2 2006.173.21:35:49.51#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.21:35:49.57#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.21:35:49.57#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.21:35:49.57#ibcon#enter wrdev, iclass 14, count 2 2006.173.21:35:49.57#ibcon#first serial, iclass 14, count 2 2006.173.21:35:49.57#ibcon#enter sib2, iclass 14, count 2 2006.173.21:35:49.57#ibcon#flushed, iclass 14, count 2 2006.173.21:35:49.57#ibcon#about to write, iclass 14, count 2 2006.173.21:35:49.57#ibcon#wrote, iclass 14, count 2 2006.173.21:35:49.57#ibcon#about to read 3, iclass 14, count 2 2006.173.21:35:49.59#ibcon#read 3, iclass 14, count 2 2006.173.21:35:49.59#ibcon#about to read 4, iclass 14, count 2 2006.173.21:35:49.59#ibcon#read 4, iclass 14, count 2 2006.173.21:35:49.59#ibcon#about to read 5, iclass 14, count 2 2006.173.21:35:49.59#ibcon#read 5, iclass 14, count 2 2006.173.21:35:49.59#ibcon#about to read 6, iclass 14, count 2 2006.173.21:35:49.59#ibcon#read 6, iclass 14, count 2 2006.173.21:35:49.59#ibcon#end of sib2, iclass 14, count 2 2006.173.21:35:49.59#ibcon#*mode == 0, iclass 14, count 2 2006.173.21:35:49.59#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.21:35:49.59#ibcon#[25=AT02-06\r\n] 2006.173.21:35:49.59#ibcon#*before write, iclass 14, count 2 2006.173.21:35:49.59#ibcon#enter sib2, iclass 14, count 2 2006.173.21:35:49.59#ibcon#flushed, iclass 14, count 2 2006.173.21:35:49.59#ibcon#about to write, iclass 14, count 2 2006.173.21:35:49.59#ibcon#wrote, iclass 14, count 2 2006.173.21:35:49.59#ibcon#about to read 3, iclass 14, count 2 2006.173.21:35:49.62#ibcon#read 3, iclass 14, count 2 2006.173.21:35:49.62#ibcon#about to read 4, iclass 14, count 2 2006.173.21:35:49.62#ibcon#read 4, iclass 14, count 2 2006.173.21:35:49.62#ibcon#about to read 5, iclass 14, count 2 2006.173.21:35:49.62#ibcon#read 5, iclass 14, count 2 2006.173.21:35:49.62#ibcon#about to read 6, iclass 14, count 2 2006.173.21:35:49.62#ibcon#read 6, iclass 14, count 2 2006.173.21:35:49.62#ibcon#end of sib2, iclass 14, count 2 2006.173.21:35:49.62#ibcon#*after write, iclass 14, count 2 2006.173.21:35:49.62#ibcon#*before return 0, iclass 14, count 2 2006.173.21:35:49.62#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.21:35:49.62#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.21:35:49.62#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.21:35:49.62#ibcon#ireg 7 cls_cnt 0 2006.173.21:35:49.62#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.21:35:49.74#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.21:35:49.74#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.21:35:49.74#ibcon#enter wrdev, iclass 14, count 0 2006.173.21:35:49.74#ibcon#first serial, iclass 14, count 0 2006.173.21:35:49.74#ibcon#enter sib2, iclass 14, count 0 2006.173.21:35:49.74#ibcon#flushed, iclass 14, count 0 2006.173.21:35:49.74#ibcon#about to write, iclass 14, count 0 2006.173.21:35:49.74#ibcon#wrote, iclass 14, count 0 2006.173.21:35:49.74#ibcon#about to read 3, iclass 14, count 0 2006.173.21:35:49.76#ibcon#read 3, iclass 14, count 0 2006.173.21:35:49.76#ibcon#about to read 4, iclass 14, count 0 2006.173.21:35:49.76#ibcon#read 4, iclass 14, count 0 2006.173.21:35:49.76#ibcon#about to read 5, iclass 14, count 0 2006.173.21:35:49.76#ibcon#read 5, iclass 14, count 0 2006.173.21:35:49.76#ibcon#about to read 6, iclass 14, count 0 2006.173.21:35:49.76#ibcon#read 6, iclass 14, count 0 2006.173.21:35:49.76#ibcon#end of sib2, iclass 14, count 0 2006.173.21:35:49.76#ibcon#*mode == 0, iclass 14, count 0 2006.173.21:35:49.76#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.21:35:49.76#ibcon#[25=USB\r\n] 2006.173.21:35:49.76#ibcon#*before write, iclass 14, count 0 2006.173.21:35:49.76#ibcon#enter sib2, iclass 14, count 0 2006.173.21:35:49.76#ibcon#flushed, iclass 14, count 0 2006.173.21:35:49.76#ibcon#about to write, iclass 14, count 0 2006.173.21:35:49.76#ibcon#wrote, iclass 14, count 0 2006.173.21:35:49.76#ibcon#about to read 3, iclass 14, count 0 2006.173.21:35:49.79#ibcon#read 3, iclass 14, count 0 2006.173.21:35:49.79#ibcon#about to read 4, iclass 14, count 0 2006.173.21:35:49.79#ibcon#read 4, iclass 14, count 0 2006.173.21:35:49.79#ibcon#about to read 5, iclass 14, count 0 2006.173.21:35:49.79#ibcon#read 5, iclass 14, count 0 2006.173.21:35:49.79#ibcon#about to read 6, iclass 14, count 0 2006.173.21:35:49.79#ibcon#read 6, iclass 14, count 0 2006.173.21:35:49.79#ibcon#end of sib2, iclass 14, count 0 2006.173.21:35:49.79#ibcon#*after write, iclass 14, count 0 2006.173.21:35:49.79#ibcon#*before return 0, iclass 14, count 0 2006.173.21:35:49.79#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.21:35:49.79#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.21:35:49.79#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.21:35:49.79#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.21:35:49.79$vck44/valo=3,564.99 2006.173.21:35:49.79#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.21:35:49.79#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.21:35:49.79#ibcon#ireg 17 cls_cnt 0 2006.173.21:35:49.79#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.21:35:49.79#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.21:35:49.79#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.21:35:49.79#ibcon#enter wrdev, iclass 16, count 0 2006.173.21:35:49.79#ibcon#first serial, iclass 16, count 0 2006.173.21:35:49.79#ibcon#enter sib2, iclass 16, count 0 2006.173.21:35:49.79#ibcon#flushed, iclass 16, count 0 2006.173.21:35:49.79#ibcon#about to write, iclass 16, count 0 2006.173.21:35:49.79#ibcon#wrote, iclass 16, count 0 2006.173.21:35:49.79#ibcon#about to read 3, iclass 16, count 0 2006.173.21:35:49.81#ibcon#read 3, iclass 16, count 0 2006.173.21:35:49.81#ibcon#about to read 4, iclass 16, count 0 2006.173.21:35:49.81#ibcon#read 4, iclass 16, count 0 2006.173.21:35:49.81#ibcon#about to read 5, iclass 16, count 0 2006.173.21:35:49.81#ibcon#read 5, iclass 16, count 0 2006.173.21:35:49.81#ibcon#about to read 6, iclass 16, count 0 2006.173.21:35:49.81#ibcon#read 6, iclass 16, count 0 2006.173.21:35:49.81#ibcon#end of sib2, iclass 16, count 0 2006.173.21:35:49.81#ibcon#*mode == 0, iclass 16, count 0 2006.173.21:35:49.81#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.21:35:49.81#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.21:35:49.81#ibcon#*before write, iclass 16, count 0 2006.173.21:35:49.81#ibcon#enter sib2, iclass 16, count 0 2006.173.21:35:49.81#ibcon#flushed, iclass 16, count 0 2006.173.21:35:49.81#ibcon#about to write, iclass 16, count 0 2006.173.21:35:49.81#ibcon#wrote, iclass 16, count 0 2006.173.21:35:49.81#ibcon#about to read 3, iclass 16, count 0 2006.173.21:35:49.85#ibcon#read 3, iclass 16, count 0 2006.173.21:35:49.85#ibcon#about to read 4, iclass 16, count 0 2006.173.21:35:49.85#ibcon#read 4, iclass 16, count 0 2006.173.21:35:49.85#ibcon#about to read 5, iclass 16, count 0 2006.173.21:35:49.85#ibcon#read 5, iclass 16, count 0 2006.173.21:35:49.85#ibcon#about to read 6, iclass 16, count 0 2006.173.21:35:49.85#ibcon#read 6, iclass 16, count 0 2006.173.21:35:49.85#ibcon#end of sib2, iclass 16, count 0 2006.173.21:35:49.85#ibcon#*after write, iclass 16, count 0 2006.173.21:35:49.85#ibcon#*before return 0, iclass 16, count 0 2006.173.21:35:49.85#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.21:35:49.85#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.21:35:49.85#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.21:35:49.85#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.21:35:49.85$vck44/va=3,5 2006.173.21:35:49.85#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.21:35:49.85#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.21:35:49.85#ibcon#ireg 11 cls_cnt 2 2006.173.21:35:49.85#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.21:35:49.91#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.21:35:49.91#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.21:35:49.91#ibcon#enter wrdev, iclass 18, count 2 2006.173.21:35:49.91#ibcon#first serial, iclass 18, count 2 2006.173.21:35:49.91#ibcon#enter sib2, iclass 18, count 2 2006.173.21:35:49.91#ibcon#flushed, iclass 18, count 2 2006.173.21:35:49.91#ibcon#about to write, iclass 18, count 2 2006.173.21:35:49.91#ibcon#wrote, iclass 18, count 2 2006.173.21:35:49.91#ibcon#about to read 3, iclass 18, count 2 2006.173.21:35:49.93#ibcon#read 3, iclass 18, count 2 2006.173.21:35:49.93#ibcon#about to read 4, iclass 18, count 2 2006.173.21:35:49.93#ibcon#read 4, iclass 18, count 2 2006.173.21:35:49.93#ibcon#about to read 5, iclass 18, count 2 2006.173.21:35:49.93#ibcon#read 5, iclass 18, count 2 2006.173.21:35:49.93#ibcon#about to read 6, iclass 18, count 2 2006.173.21:35:49.93#ibcon#read 6, iclass 18, count 2 2006.173.21:35:49.93#ibcon#end of sib2, iclass 18, count 2 2006.173.21:35:49.93#ibcon#*mode == 0, iclass 18, count 2 2006.173.21:35:49.93#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.21:35:49.93#ibcon#[25=AT03-05\r\n] 2006.173.21:35:49.93#ibcon#*before write, iclass 18, count 2 2006.173.21:35:49.93#ibcon#enter sib2, iclass 18, count 2 2006.173.21:35:49.93#ibcon#flushed, iclass 18, count 2 2006.173.21:35:49.93#ibcon#about to write, iclass 18, count 2 2006.173.21:35:49.93#ibcon#wrote, iclass 18, count 2 2006.173.21:35:49.93#ibcon#about to read 3, iclass 18, count 2 2006.173.21:35:49.96#ibcon#read 3, iclass 18, count 2 2006.173.21:35:49.96#ibcon#about to read 4, iclass 18, count 2 2006.173.21:35:49.96#ibcon#read 4, iclass 18, count 2 2006.173.21:35:49.96#ibcon#about to read 5, iclass 18, count 2 2006.173.21:35:49.96#ibcon#read 5, iclass 18, count 2 2006.173.21:35:49.96#ibcon#about to read 6, iclass 18, count 2 2006.173.21:35:49.96#ibcon#read 6, iclass 18, count 2 2006.173.21:35:49.96#ibcon#end of sib2, iclass 18, count 2 2006.173.21:35:49.96#ibcon#*after write, iclass 18, count 2 2006.173.21:35:49.96#ibcon#*before return 0, iclass 18, count 2 2006.173.21:35:49.96#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.21:35:49.96#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.21:35:49.96#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.21:35:49.96#ibcon#ireg 7 cls_cnt 0 2006.173.21:35:49.96#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.21:35:50.08#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.21:35:50.08#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.21:35:50.08#ibcon#enter wrdev, iclass 18, count 0 2006.173.21:35:50.08#ibcon#first serial, iclass 18, count 0 2006.173.21:35:50.08#ibcon#enter sib2, iclass 18, count 0 2006.173.21:35:50.08#ibcon#flushed, iclass 18, count 0 2006.173.21:35:50.08#ibcon#about to write, iclass 18, count 0 2006.173.21:35:50.08#ibcon#wrote, iclass 18, count 0 2006.173.21:35:50.08#ibcon#about to read 3, iclass 18, count 0 2006.173.21:35:50.10#ibcon#read 3, iclass 18, count 0 2006.173.21:35:50.10#ibcon#about to read 4, iclass 18, count 0 2006.173.21:35:50.10#ibcon#read 4, iclass 18, count 0 2006.173.21:35:50.10#ibcon#about to read 5, iclass 18, count 0 2006.173.21:35:50.10#ibcon#read 5, iclass 18, count 0 2006.173.21:35:50.10#ibcon#about to read 6, iclass 18, count 0 2006.173.21:35:50.10#ibcon#read 6, iclass 18, count 0 2006.173.21:35:50.10#ibcon#end of sib2, iclass 18, count 0 2006.173.21:35:50.10#ibcon#*mode == 0, iclass 18, count 0 2006.173.21:35:50.10#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.21:35:50.10#ibcon#[25=USB\r\n] 2006.173.21:35:50.10#ibcon#*before write, iclass 18, count 0 2006.173.21:35:50.10#ibcon#enter sib2, iclass 18, count 0 2006.173.21:35:50.10#ibcon#flushed, iclass 18, count 0 2006.173.21:35:50.10#ibcon#about to write, iclass 18, count 0 2006.173.21:35:50.10#ibcon#wrote, iclass 18, count 0 2006.173.21:35:50.10#ibcon#about to read 3, iclass 18, count 0 2006.173.21:35:50.13#ibcon#read 3, iclass 18, count 0 2006.173.21:35:50.13#ibcon#about to read 4, iclass 18, count 0 2006.173.21:35:50.13#ibcon#read 4, iclass 18, count 0 2006.173.21:35:50.13#ibcon#about to read 5, iclass 18, count 0 2006.173.21:35:50.13#ibcon#read 5, iclass 18, count 0 2006.173.21:35:50.13#ibcon#about to read 6, iclass 18, count 0 2006.173.21:35:50.13#ibcon#read 6, iclass 18, count 0 2006.173.21:35:50.13#ibcon#end of sib2, iclass 18, count 0 2006.173.21:35:50.13#ibcon#*after write, iclass 18, count 0 2006.173.21:35:50.13#ibcon#*before return 0, iclass 18, count 0 2006.173.21:35:50.13#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.21:35:50.13#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.21:35:50.13#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.21:35:50.13#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.21:35:50.13$vck44/valo=4,624.99 2006.173.21:35:50.13#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.21:35:50.13#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.21:35:50.13#ibcon#ireg 17 cls_cnt 0 2006.173.21:35:50.13#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.21:35:50.13#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.21:35:50.13#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.21:35:50.13#ibcon#enter wrdev, iclass 20, count 0 2006.173.21:35:50.13#ibcon#first serial, iclass 20, count 0 2006.173.21:35:50.13#ibcon#enter sib2, iclass 20, count 0 2006.173.21:35:50.13#ibcon#flushed, iclass 20, count 0 2006.173.21:35:50.13#ibcon#about to write, iclass 20, count 0 2006.173.21:35:50.13#ibcon#wrote, iclass 20, count 0 2006.173.21:35:50.13#ibcon#about to read 3, iclass 20, count 0 2006.173.21:35:50.15#ibcon#read 3, iclass 20, count 0 2006.173.21:35:50.15#ibcon#about to read 4, iclass 20, count 0 2006.173.21:35:50.15#ibcon#read 4, iclass 20, count 0 2006.173.21:35:50.15#ibcon#about to read 5, iclass 20, count 0 2006.173.21:35:50.15#ibcon#read 5, iclass 20, count 0 2006.173.21:35:50.15#ibcon#about to read 6, iclass 20, count 0 2006.173.21:35:50.15#ibcon#read 6, iclass 20, count 0 2006.173.21:35:50.15#ibcon#end of sib2, iclass 20, count 0 2006.173.21:35:50.15#ibcon#*mode == 0, iclass 20, count 0 2006.173.21:35:50.15#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.21:35:50.15#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.21:35:50.15#ibcon#*before write, iclass 20, count 0 2006.173.21:35:50.15#ibcon#enter sib2, iclass 20, count 0 2006.173.21:35:50.15#ibcon#flushed, iclass 20, count 0 2006.173.21:35:50.15#ibcon#about to write, iclass 20, count 0 2006.173.21:35:50.15#ibcon#wrote, iclass 20, count 0 2006.173.21:35:50.15#ibcon#about to read 3, iclass 20, count 0 2006.173.21:35:50.19#ibcon#read 3, iclass 20, count 0 2006.173.21:35:50.19#ibcon#about to read 4, iclass 20, count 0 2006.173.21:35:50.19#ibcon#read 4, iclass 20, count 0 2006.173.21:35:50.19#ibcon#about to read 5, iclass 20, count 0 2006.173.21:35:50.19#ibcon#read 5, iclass 20, count 0 2006.173.21:35:50.19#ibcon#about to read 6, iclass 20, count 0 2006.173.21:35:50.19#ibcon#read 6, iclass 20, count 0 2006.173.21:35:50.19#ibcon#end of sib2, iclass 20, count 0 2006.173.21:35:50.19#ibcon#*after write, iclass 20, count 0 2006.173.21:35:50.19#ibcon#*before return 0, iclass 20, count 0 2006.173.21:35:50.19#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.21:35:50.19#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.21:35:50.19#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.21:35:50.19#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.21:35:50.19$vck44/va=4,6 2006.173.21:35:50.19#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.21:35:50.19#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.21:35:50.19#ibcon#ireg 11 cls_cnt 2 2006.173.21:35:50.19#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.21:35:50.25#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.21:35:50.25#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.21:35:50.25#ibcon#enter wrdev, iclass 22, count 2 2006.173.21:35:50.25#ibcon#first serial, iclass 22, count 2 2006.173.21:35:50.25#ibcon#enter sib2, iclass 22, count 2 2006.173.21:35:50.25#ibcon#flushed, iclass 22, count 2 2006.173.21:35:50.25#ibcon#about to write, iclass 22, count 2 2006.173.21:35:50.25#ibcon#wrote, iclass 22, count 2 2006.173.21:35:50.25#ibcon#about to read 3, iclass 22, count 2 2006.173.21:35:50.27#ibcon#read 3, iclass 22, count 2 2006.173.21:35:50.27#ibcon#about to read 4, iclass 22, count 2 2006.173.21:35:50.27#ibcon#read 4, iclass 22, count 2 2006.173.21:35:50.27#ibcon#about to read 5, iclass 22, count 2 2006.173.21:35:50.27#ibcon#read 5, iclass 22, count 2 2006.173.21:35:50.27#ibcon#about to read 6, iclass 22, count 2 2006.173.21:35:50.27#ibcon#read 6, iclass 22, count 2 2006.173.21:35:50.27#ibcon#end of sib2, iclass 22, count 2 2006.173.21:35:50.27#ibcon#*mode == 0, iclass 22, count 2 2006.173.21:35:50.27#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.21:35:50.27#ibcon#[25=AT04-06\r\n] 2006.173.21:35:50.27#ibcon#*before write, iclass 22, count 2 2006.173.21:35:50.27#ibcon#enter sib2, iclass 22, count 2 2006.173.21:35:50.27#ibcon#flushed, iclass 22, count 2 2006.173.21:35:50.27#ibcon#about to write, iclass 22, count 2 2006.173.21:35:50.27#ibcon#wrote, iclass 22, count 2 2006.173.21:35:50.27#ibcon#about to read 3, iclass 22, count 2 2006.173.21:35:50.30#ibcon#read 3, iclass 22, count 2 2006.173.21:35:50.30#ibcon#about to read 4, iclass 22, count 2 2006.173.21:35:50.30#ibcon#read 4, iclass 22, count 2 2006.173.21:35:50.30#ibcon#about to read 5, iclass 22, count 2 2006.173.21:35:50.30#ibcon#read 5, iclass 22, count 2 2006.173.21:35:50.30#ibcon#about to read 6, iclass 22, count 2 2006.173.21:35:50.30#ibcon#read 6, iclass 22, count 2 2006.173.21:35:50.30#ibcon#end of sib2, iclass 22, count 2 2006.173.21:35:50.30#ibcon#*after write, iclass 22, count 2 2006.173.21:35:50.30#ibcon#*before return 0, iclass 22, count 2 2006.173.21:35:50.30#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.21:35:50.30#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.21:35:50.30#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.21:35:50.30#ibcon#ireg 7 cls_cnt 0 2006.173.21:35:50.30#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.21:35:50.42#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.21:35:50.42#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.21:35:50.42#ibcon#enter wrdev, iclass 22, count 0 2006.173.21:35:50.42#ibcon#first serial, iclass 22, count 0 2006.173.21:35:50.42#ibcon#enter sib2, iclass 22, count 0 2006.173.21:35:50.42#ibcon#flushed, iclass 22, count 0 2006.173.21:35:50.42#ibcon#about to write, iclass 22, count 0 2006.173.21:35:50.42#ibcon#wrote, iclass 22, count 0 2006.173.21:35:50.42#ibcon#about to read 3, iclass 22, count 0 2006.173.21:35:50.44#ibcon#read 3, iclass 22, count 0 2006.173.21:35:50.44#ibcon#about to read 4, iclass 22, count 0 2006.173.21:35:50.44#ibcon#read 4, iclass 22, count 0 2006.173.21:35:50.44#ibcon#about to read 5, iclass 22, count 0 2006.173.21:35:50.44#ibcon#read 5, iclass 22, count 0 2006.173.21:35:50.44#ibcon#about to read 6, iclass 22, count 0 2006.173.21:35:50.44#ibcon#read 6, iclass 22, count 0 2006.173.21:35:50.44#ibcon#end of sib2, iclass 22, count 0 2006.173.21:35:50.44#ibcon#*mode == 0, iclass 22, count 0 2006.173.21:35:50.44#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.21:35:50.44#ibcon#[25=USB\r\n] 2006.173.21:35:50.44#ibcon#*before write, iclass 22, count 0 2006.173.21:35:50.44#ibcon#enter sib2, iclass 22, count 0 2006.173.21:35:50.44#ibcon#flushed, iclass 22, count 0 2006.173.21:35:50.44#ibcon#about to write, iclass 22, count 0 2006.173.21:35:50.44#ibcon#wrote, iclass 22, count 0 2006.173.21:35:50.44#ibcon#about to read 3, iclass 22, count 0 2006.173.21:35:50.47#ibcon#read 3, iclass 22, count 0 2006.173.21:35:50.47#ibcon#about to read 4, iclass 22, count 0 2006.173.21:35:50.47#ibcon#read 4, iclass 22, count 0 2006.173.21:35:50.47#ibcon#about to read 5, iclass 22, count 0 2006.173.21:35:50.47#ibcon#read 5, iclass 22, count 0 2006.173.21:35:50.47#ibcon#about to read 6, iclass 22, count 0 2006.173.21:35:50.47#ibcon#read 6, iclass 22, count 0 2006.173.21:35:50.47#ibcon#end of sib2, iclass 22, count 0 2006.173.21:35:50.47#ibcon#*after write, iclass 22, count 0 2006.173.21:35:50.47#ibcon#*before return 0, iclass 22, count 0 2006.173.21:35:50.47#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.21:35:50.47#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.21:35:50.47#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.21:35:50.47#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.21:35:50.47$vck44/valo=5,734.99 2006.173.21:35:50.47#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.21:35:50.47#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.21:35:50.47#ibcon#ireg 17 cls_cnt 0 2006.173.21:35:50.47#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.21:35:50.47#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.21:35:50.47#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.21:35:50.47#ibcon#enter wrdev, iclass 24, count 0 2006.173.21:35:50.47#ibcon#first serial, iclass 24, count 0 2006.173.21:35:50.47#ibcon#enter sib2, iclass 24, count 0 2006.173.21:35:50.47#ibcon#flushed, iclass 24, count 0 2006.173.21:35:50.47#ibcon#about to write, iclass 24, count 0 2006.173.21:35:50.47#ibcon#wrote, iclass 24, count 0 2006.173.21:35:50.47#ibcon#about to read 3, iclass 24, count 0 2006.173.21:35:50.49#ibcon#read 3, iclass 24, count 0 2006.173.21:35:50.49#ibcon#about to read 4, iclass 24, count 0 2006.173.21:35:50.49#ibcon#read 4, iclass 24, count 0 2006.173.21:35:50.49#ibcon#about to read 5, iclass 24, count 0 2006.173.21:35:50.49#ibcon#read 5, iclass 24, count 0 2006.173.21:35:50.49#ibcon#about to read 6, iclass 24, count 0 2006.173.21:35:50.49#ibcon#read 6, iclass 24, count 0 2006.173.21:35:50.49#ibcon#end of sib2, iclass 24, count 0 2006.173.21:35:50.49#ibcon#*mode == 0, iclass 24, count 0 2006.173.21:35:50.49#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.21:35:50.49#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.21:35:50.49#ibcon#*before write, iclass 24, count 0 2006.173.21:35:50.49#ibcon#enter sib2, iclass 24, count 0 2006.173.21:35:50.49#ibcon#flushed, iclass 24, count 0 2006.173.21:35:50.49#ibcon#about to write, iclass 24, count 0 2006.173.21:35:50.49#ibcon#wrote, iclass 24, count 0 2006.173.21:35:50.49#ibcon#about to read 3, iclass 24, count 0 2006.173.21:35:50.53#ibcon#read 3, iclass 24, count 0 2006.173.21:35:50.53#ibcon#about to read 4, iclass 24, count 0 2006.173.21:35:50.53#ibcon#read 4, iclass 24, count 0 2006.173.21:35:50.53#ibcon#about to read 5, iclass 24, count 0 2006.173.21:35:50.53#ibcon#read 5, iclass 24, count 0 2006.173.21:35:50.53#ibcon#about to read 6, iclass 24, count 0 2006.173.21:35:50.53#ibcon#read 6, iclass 24, count 0 2006.173.21:35:50.53#ibcon#end of sib2, iclass 24, count 0 2006.173.21:35:50.53#ibcon#*after write, iclass 24, count 0 2006.173.21:35:50.53#ibcon#*before return 0, iclass 24, count 0 2006.173.21:35:50.53#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.21:35:50.53#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.21:35:50.53#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.21:35:50.53#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.21:35:50.53$vck44/va=5,4 2006.173.21:35:50.53#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.21:35:50.53#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.21:35:50.53#ibcon#ireg 11 cls_cnt 2 2006.173.21:35:50.53#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.21:35:50.59#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.21:35:50.59#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.21:35:50.59#ibcon#enter wrdev, iclass 26, count 2 2006.173.21:35:50.59#ibcon#first serial, iclass 26, count 2 2006.173.21:35:50.59#ibcon#enter sib2, iclass 26, count 2 2006.173.21:35:50.59#ibcon#flushed, iclass 26, count 2 2006.173.21:35:50.59#ibcon#about to write, iclass 26, count 2 2006.173.21:35:50.59#ibcon#wrote, iclass 26, count 2 2006.173.21:35:50.59#ibcon#about to read 3, iclass 26, count 2 2006.173.21:35:50.61#ibcon#read 3, iclass 26, count 2 2006.173.21:35:50.61#ibcon#about to read 4, iclass 26, count 2 2006.173.21:35:50.61#ibcon#read 4, iclass 26, count 2 2006.173.21:35:50.61#ibcon#about to read 5, iclass 26, count 2 2006.173.21:35:50.61#ibcon#read 5, iclass 26, count 2 2006.173.21:35:50.61#ibcon#about to read 6, iclass 26, count 2 2006.173.21:35:50.61#ibcon#read 6, iclass 26, count 2 2006.173.21:35:50.61#ibcon#end of sib2, iclass 26, count 2 2006.173.21:35:50.61#ibcon#*mode == 0, iclass 26, count 2 2006.173.21:35:50.61#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.21:35:50.61#ibcon#[25=AT05-04\r\n] 2006.173.21:35:50.61#ibcon#*before write, iclass 26, count 2 2006.173.21:35:50.61#ibcon#enter sib2, iclass 26, count 2 2006.173.21:35:50.61#ibcon#flushed, iclass 26, count 2 2006.173.21:35:50.61#ibcon#about to write, iclass 26, count 2 2006.173.21:35:50.61#ibcon#wrote, iclass 26, count 2 2006.173.21:35:50.61#ibcon#about to read 3, iclass 26, count 2 2006.173.21:35:50.64#ibcon#read 3, iclass 26, count 2 2006.173.21:35:50.64#ibcon#about to read 4, iclass 26, count 2 2006.173.21:35:50.64#ibcon#read 4, iclass 26, count 2 2006.173.21:35:50.64#ibcon#about to read 5, iclass 26, count 2 2006.173.21:35:50.64#ibcon#read 5, iclass 26, count 2 2006.173.21:35:50.64#ibcon#about to read 6, iclass 26, count 2 2006.173.21:35:50.64#ibcon#read 6, iclass 26, count 2 2006.173.21:35:50.64#ibcon#end of sib2, iclass 26, count 2 2006.173.21:35:50.64#ibcon#*after write, iclass 26, count 2 2006.173.21:35:50.64#ibcon#*before return 0, iclass 26, count 2 2006.173.21:35:50.64#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.21:35:50.64#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.21:35:50.64#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.21:35:50.64#ibcon#ireg 7 cls_cnt 0 2006.173.21:35:50.64#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.21:35:50.76#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.21:35:50.76#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.21:35:50.76#ibcon#enter wrdev, iclass 26, count 0 2006.173.21:35:50.76#ibcon#first serial, iclass 26, count 0 2006.173.21:35:50.76#ibcon#enter sib2, iclass 26, count 0 2006.173.21:35:50.76#ibcon#flushed, iclass 26, count 0 2006.173.21:35:50.76#ibcon#about to write, iclass 26, count 0 2006.173.21:35:50.76#ibcon#wrote, iclass 26, count 0 2006.173.21:35:50.76#ibcon#about to read 3, iclass 26, count 0 2006.173.21:35:50.78#ibcon#read 3, iclass 26, count 0 2006.173.21:35:50.78#ibcon#about to read 4, iclass 26, count 0 2006.173.21:35:50.78#ibcon#read 4, iclass 26, count 0 2006.173.21:35:50.78#ibcon#about to read 5, iclass 26, count 0 2006.173.21:35:50.78#ibcon#read 5, iclass 26, count 0 2006.173.21:35:50.78#ibcon#about to read 6, iclass 26, count 0 2006.173.21:35:50.78#ibcon#read 6, iclass 26, count 0 2006.173.21:35:50.78#ibcon#end of sib2, iclass 26, count 0 2006.173.21:35:50.78#ibcon#*mode == 0, iclass 26, count 0 2006.173.21:35:50.78#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.21:35:50.78#ibcon#[25=USB\r\n] 2006.173.21:35:50.78#ibcon#*before write, iclass 26, count 0 2006.173.21:35:50.78#ibcon#enter sib2, iclass 26, count 0 2006.173.21:35:50.78#ibcon#flushed, iclass 26, count 0 2006.173.21:35:50.78#ibcon#about to write, iclass 26, count 0 2006.173.21:35:50.78#ibcon#wrote, iclass 26, count 0 2006.173.21:35:50.78#ibcon#about to read 3, iclass 26, count 0 2006.173.21:35:50.81#ibcon#read 3, iclass 26, count 0 2006.173.21:35:50.81#ibcon#about to read 4, iclass 26, count 0 2006.173.21:35:50.81#ibcon#read 4, iclass 26, count 0 2006.173.21:35:50.81#ibcon#about to read 5, iclass 26, count 0 2006.173.21:35:50.81#ibcon#read 5, iclass 26, count 0 2006.173.21:35:50.81#ibcon#about to read 6, iclass 26, count 0 2006.173.21:35:50.81#ibcon#read 6, iclass 26, count 0 2006.173.21:35:50.81#ibcon#end of sib2, iclass 26, count 0 2006.173.21:35:50.81#ibcon#*after write, iclass 26, count 0 2006.173.21:35:50.81#ibcon#*before return 0, iclass 26, count 0 2006.173.21:35:50.81#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.21:35:50.81#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.21:35:50.81#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.21:35:50.81#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.21:35:50.81$vck44/valo=6,814.99 2006.173.21:35:50.81#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.21:35:50.81#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.21:35:50.81#ibcon#ireg 17 cls_cnt 0 2006.173.21:35:50.81#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.21:35:50.81#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.21:35:50.81#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.21:35:50.81#ibcon#enter wrdev, iclass 28, count 0 2006.173.21:35:50.81#ibcon#first serial, iclass 28, count 0 2006.173.21:35:50.81#ibcon#enter sib2, iclass 28, count 0 2006.173.21:35:50.81#ibcon#flushed, iclass 28, count 0 2006.173.21:35:50.81#ibcon#about to write, iclass 28, count 0 2006.173.21:35:50.81#ibcon#wrote, iclass 28, count 0 2006.173.21:35:50.81#ibcon#about to read 3, iclass 28, count 0 2006.173.21:35:50.83#ibcon#read 3, iclass 28, count 0 2006.173.21:35:50.83#ibcon#about to read 4, iclass 28, count 0 2006.173.21:35:50.83#ibcon#read 4, iclass 28, count 0 2006.173.21:35:50.83#ibcon#about to read 5, iclass 28, count 0 2006.173.21:35:50.83#ibcon#read 5, iclass 28, count 0 2006.173.21:35:50.83#ibcon#about to read 6, iclass 28, count 0 2006.173.21:35:50.83#ibcon#read 6, iclass 28, count 0 2006.173.21:35:50.83#ibcon#end of sib2, iclass 28, count 0 2006.173.21:35:50.83#ibcon#*mode == 0, iclass 28, count 0 2006.173.21:35:50.83#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.21:35:50.83#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.21:35:50.83#ibcon#*before write, iclass 28, count 0 2006.173.21:35:50.83#ibcon#enter sib2, iclass 28, count 0 2006.173.21:35:50.83#ibcon#flushed, iclass 28, count 0 2006.173.21:35:50.83#ibcon#about to write, iclass 28, count 0 2006.173.21:35:50.83#ibcon#wrote, iclass 28, count 0 2006.173.21:35:50.83#ibcon#about to read 3, iclass 28, count 0 2006.173.21:35:50.87#ibcon#read 3, iclass 28, count 0 2006.173.21:35:50.87#ibcon#about to read 4, iclass 28, count 0 2006.173.21:35:50.87#ibcon#read 4, iclass 28, count 0 2006.173.21:35:50.87#ibcon#about to read 5, iclass 28, count 0 2006.173.21:35:50.87#ibcon#read 5, iclass 28, count 0 2006.173.21:35:50.87#ibcon#about to read 6, iclass 28, count 0 2006.173.21:35:50.87#ibcon#read 6, iclass 28, count 0 2006.173.21:35:50.87#ibcon#end of sib2, iclass 28, count 0 2006.173.21:35:50.87#ibcon#*after write, iclass 28, count 0 2006.173.21:35:50.87#ibcon#*before return 0, iclass 28, count 0 2006.173.21:35:50.87#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.21:35:50.87#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.21:35:50.87#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.21:35:50.87#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.21:35:50.87$vck44/va=6,3 2006.173.21:35:50.87#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.21:35:50.87#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.21:35:50.87#ibcon#ireg 11 cls_cnt 2 2006.173.21:35:50.87#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.21:35:50.93#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.21:35:50.93#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.21:35:50.93#ibcon#enter wrdev, iclass 30, count 2 2006.173.21:35:50.93#ibcon#first serial, iclass 30, count 2 2006.173.21:35:50.93#ibcon#enter sib2, iclass 30, count 2 2006.173.21:35:50.93#ibcon#flushed, iclass 30, count 2 2006.173.21:35:50.93#ibcon#about to write, iclass 30, count 2 2006.173.21:35:50.93#ibcon#wrote, iclass 30, count 2 2006.173.21:35:50.93#ibcon#about to read 3, iclass 30, count 2 2006.173.21:35:50.95#ibcon#read 3, iclass 30, count 2 2006.173.21:35:50.95#ibcon#about to read 4, iclass 30, count 2 2006.173.21:35:50.95#ibcon#read 4, iclass 30, count 2 2006.173.21:35:50.95#ibcon#about to read 5, iclass 30, count 2 2006.173.21:35:50.95#ibcon#read 5, iclass 30, count 2 2006.173.21:35:50.95#ibcon#about to read 6, iclass 30, count 2 2006.173.21:35:50.95#ibcon#read 6, iclass 30, count 2 2006.173.21:35:50.95#ibcon#end of sib2, iclass 30, count 2 2006.173.21:35:50.95#ibcon#*mode == 0, iclass 30, count 2 2006.173.21:35:50.95#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.21:35:50.95#ibcon#[25=AT06-03\r\n] 2006.173.21:35:50.95#ibcon#*before write, iclass 30, count 2 2006.173.21:35:50.95#ibcon#enter sib2, iclass 30, count 2 2006.173.21:35:50.95#ibcon#flushed, iclass 30, count 2 2006.173.21:35:50.95#ibcon#about to write, iclass 30, count 2 2006.173.21:35:50.95#ibcon#wrote, iclass 30, count 2 2006.173.21:35:50.95#ibcon#about to read 3, iclass 30, count 2 2006.173.21:35:50.98#ibcon#read 3, iclass 30, count 2 2006.173.21:35:50.98#ibcon#about to read 4, iclass 30, count 2 2006.173.21:35:50.98#ibcon#read 4, iclass 30, count 2 2006.173.21:35:50.98#ibcon#about to read 5, iclass 30, count 2 2006.173.21:35:50.98#ibcon#read 5, iclass 30, count 2 2006.173.21:35:50.98#ibcon#about to read 6, iclass 30, count 2 2006.173.21:35:50.98#ibcon#read 6, iclass 30, count 2 2006.173.21:35:50.98#ibcon#end of sib2, iclass 30, count 2 2006.173.21:35:50.98#ibcon#*after write, iclass 30, count 2 2006.173.21:35:50.98#ibcon#*before return 0, iclass 30, count 2 2006.173.21:35:50.98#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.21:35:50.98#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.21:35:50.98#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.21:35:50.98#ibcon#ireg 7 cls_cnt 0 2006.173.21:35:50.98#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.21:35:51.10#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.21:35:51.10#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.21:35:51.10#ibcon#enter wrdev, iclass 30, count 0 2006.173.21:35:51.10#ibcon#first serial, iclass 30, count 0 2006.173.21:35:51.10#ibcon#enter sib2, iclass 30, count 0 2006.173.21:35:51.10#ibcon#flushed, iclass 30, count 0 2006.173.21:35:51.10#ibcon#about to write, iclass 30, count 0 2006.173.21:35:51.10#ibcon#wrote, iclass 30, count 0 2006.173.21:35:51.10#ibcon#about to read 3, iclass 30, count 0 2006.173.21:35:51.12#ibcon#read 3, iclass 30, count 0 2006.173.21:35:51.12#ibcon#about to read 4, iclass 30, count 0 2006.173.21:35:51.12#ibcon#read 4, iclass 30, count 0 2006.173.21:35:51.12#ibcon#about to read 5, iclass 30, count 0 2006.173.21:35:51.12#ibcon#read 5, iclass 30, count 0 2006.173.21:35:51.12#ibcon#about to read 6, iclass 30, count 0 2006.173.21:35:51.12#ibcon#read 6, iclass 30, count 0 2006.173.21:35:51.12#ibcon#end of sib2, iclass 30, count 0 2006.173.21:35:51.12#ibcon#*mode == 0, iclass 30, count 0 2006.173.21:35:51.12#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.21:35:51.12#ibcon#[25=USB\r\n] 2006.173.21:35:51.12#ibcon#*before write, iclass 30, count 0 2006.173.21:35:51.12#ibcon#enter sib2, iclass 30, count 0 2006.173.21:35:51.12#ibcon#flushed, iclass 30, count 0 2006.173.21:35:51.12#ibcon#about to write, iclass 30, count 0 2006.173.21:35:51.12#ibcon#wrote, iclass 30, count 0 2006.173.21:35:51.12#ibcon#about to read 3, iclass 30, count 0 2006.173.21:35:51.15#ibcon#read 3, iclass 30, count 0 2006.173.21:35:51.15#ibcon#about to read 4, iclass 30, count 0 2006.173.21:35:51.15#ibcon#read 4, iclass 30, count 0 2006.173.21:35:51.15#ibcon#about to read 5, iclass 30, count 0 2006.173.21:35:51.15#ibcon#read 5, iclass 30, count 0 2006.173.21:35:51.15#ibcon#about to read 6, iclass 30, count 0 2006.173.21:35:51.15#ibcon#read 6, iclass 30, count 0 2006.173.21:35:51.15#ibcon#end of sib2, iclass 30, count 0 2006.173.21:35:51.15#ibcon#*after write, iclass 30, count 0 2006.173.21:35:51.15#ibcon#*before return 0, iclass 30, count 0 2006.173.21:35:51.15#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.21:35:51.15#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.21:35:51.15#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.21:35:51.15#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.21:35:51.15$vck44/valo=7,864.99 2006.173.21:35:51.15#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.21:35:51.15#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.21:35:51.15#ibcon#ireg 17 cls_cnt 0 2006.173.21:35:51.15#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.21:35:51.15#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.21:35:51.15#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.21:35:51.15#ibcon#enter wrdev, iclass 32, count 0 2006.173.21:35:51.15#ibcon#first serial, iclass 32, count 0 2006.173.21:35:51.15#ibcon#enter sib2, iclass 32, count 0 2006.173.21:35:51.15#ibcon#flushed, iclass 32, count 0 2006.173.21:35:51.15#ibcon#about to write, iclass 32, count 0 2006.173.21:35:51.15#ibcon#wrote, iclass 32, count 0 2006.173.21:35:51.15#ibcon#about to read 3, iclass 32, count 0 2006.173.21:35:51.17#ibcon#read 3, iclass 32, count 0 2006.173.21:35:51.17#ibcon#about to read 4, iclass 32, count 0 2006.173.21:35:51.17#ibcon#read 4, iclass 32, count 0 2006.173.21:35:51.17#ibcon#about to read 5, iclass 32, count 0 2006.173.21:35:51.17#ibcon#read 5, iclass 32, count 0 2006.173.21:35:51.17#ibcon#about to read 6, iclass 32, count 0 2006.173.21:35:51.17#ibcon#read 6, iclass 32, count 0 2006.173.21:35:51.17#ibcon#end of sib2, iclass 32, count 0 2006.173.21:35:51.17#ibcon#*mode == 0, iclass 32, count 0 2006.173.21:35:51.17#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.21:35:51.17#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.21:35:51.17#ibcon#*before write, iclass 32, count 0 2006.173.21:35:51.17#ibcon#enter sib2, iclass 32, count 0 2006.173.21:35:51.17#ibcon#flushed, iclass 32, count 0 2006.173.21:35:51.17#ibcon#about to write, iclass 32, count 0 2006.173.21:35:51.17#ibcon#wrote, iclass 32, count 0 2006.173.21:35:51.17#ibcon#about to read 3, iclass 32, count 0 2006.173.21:35:51.21#ibcon#read 3, iclass 32, count 0 2006.173.21:35:51.21#ibcon#about to read 4, iclass 32, count 0 2006.173.21:35:51.21#ibcon#read 4, iclass 32, count 0 2006.173.21:35:51.21#ibcon#about to read 5, iclass 32, count 0 2006.173.21:35:51.21#ibcon#read 5, iclass 32, count 0 2006.173.21:35:51.21#ibcon#about to read 6, iclass 32, count 0 2006.173.21:35:51.21#ibcon#read 6, iclass 32, count 0 2006.173.21:35:51.21#ibcon#end of sib2, iclass 32, count 0 2006.173.21:35:51.21#ibcon#*after write, iclass 32, count 0 2006.173.21:35:51.21#ibcon#*before return 0, iclass 32, count 0 2006.173.21:35:51.21#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.21:35:51.21#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.21:35:51.21#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.21:35:51.21#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.21:35:51.21$vck44/va=7,4 2006.173.21:35:51.21#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.21:35:51.21#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.21:35:51.21#ibcon#ireg 11 cls_cnt 2 2006.173.21:35:51.21#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.21:35:51.27#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.21:35:51.27#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.21:35:51.27#ibcon#enter wrdev, iclass 34, count 2 2006.173.21:35:51.27#ibcon#first serial, iclass 34, count 2 2006.173.21:35:51.27#ibcon#enter sib2, iclass 34, count 2 2006.173.21:35:51.27#ibcon#flushed, iclass 34, count 2 2006.173.21:35:51.27#ibcon#about to write, iclass 34, count 2 2006.173.21:35:51.27#ibcon#wrote, iclass 34, count 2 2006.173.21:35:51.27#ibcon#about to read 3, iclass 34, count 2 2006.173.21:35:51.29#ibcon#read 3, iclass 34, count 2 2006.173.21:35:51.29#ibcon#about to read 4, iclass 34, count 2 2006.173.21:35:51.29#ibcon#read 4, iclass 34, count 2 2006.173.21:35:51.29#ibcon#about to read 5, iclass 34, count 2 2006.173.21:35:51.29#ibcon#read 5, iclass 34, count 2 2006.173.21:35:51.29#ibcon#about to read 6, iclass 34, count 2 2006.173.21:35:51.29#ibcon#read 6, iclass 34, count 2 2006.173.21:35:51.29#ibcon#end of sib2, iclass 34, count 2 2006.173.21:35:51.29#ibcon#*mode == 0, iclass 34, count 2 2006.173.21:35:51.29#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.21:35:51.29#ibcon#[25=AT07-04\r\n] 2006.173.21:35:51.29#ibcon#*before write, iclass 34, count 2 2006.173.21:35:51.29#ibcon#enter sib2, iclass 34, count 2 2006.173.21:35:51.29#ibcon#flushed, iclass 34, count 2 2006.173.21:35:51.29#ibcon#about to write, iclass 34, count 2 2006.173.21:35:51.29#ibcon#wrote, iclass 34, count 2 2006.173.21:35:51.29#ibcon#about to read 3, iclass 34, count 2 2006.173.21:35:51.32#ibcon#read 3, iclass 34, count 2 2006.173.21:35:51.32#ibcon#about to read 4, iclass 34, count 2 2006.173.21:35:51.32#ibcon#read 4, iclass 34, count 2 2006.173.21:35:51.32#ibcon#about to read 5, iclass 34, count 2 2006.173.21:35:51.32#ibcon#read 5, iclass 34, count 2 2006.173.21:35:51.32#ibcon#about to read 6, iclass 34, count 2 2006.173.21:35:51.32#ibcon#read 6, iclass 34, count 2 2006.173.21:35:51.32#ibcon#end of sib2, iclass 34, count 2 2006.173.21:35:51.32#ibcon#*after write, iclass 34, count 2 2006.173.21:35:51.32#ibcon#*before return 0, iclass 34, count 2 2006.173.21:35:51.32#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.21:35:51.32#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.21:35:51.32#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.21:35:51.32#ibcon#ireg 7 cls_cnt 0 2006.173.21:35:51.32#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.21:35:51.44#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.21:35:51.44#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.21:35:51.44#ibcon#enter wrdev, iclass 34, count 0 2006.173.21:35:51.44#ibcon#first serial, iclass 34, count 0 2006.173.21:35:51.44#ibcon#enter sib2, iclass 34, count 0 2006.173.21:35:51.44#ibcon#flushed, iclass 34, count 0 2006.173.21:35:51.44#ibcon#about to write, iclass 34, count 0 2006.173.21:35:51.44#ibcon#wrote, iclass 34, count 0 2006.173.21:35:51.44#ibcon#about to read 3, iclass 34, count 0 2006.173.21:35:51.46#ibcon#read 3, iclass 34, count 0 2006.173.21:35:51.46#ibcon#about to read 4, iclass 34, count 0 2006.173.21:35:51.46#ibcon#read 4, iclass 34, count 0 2006.173.21:35:51.46#ibcon#about to read 5, iclass 34, count 0 2006.173.21:35:51.46#ibcon#read 5, iclass 34, count 0 2006.173.21:35:51.46#ibcon#about to read 6, iclass 34, count 0 2006.173.21:35:51.46#ibcon#read 6, iclass 34, count 0 2006.173.21:35:51.46#ibcon#end of sib2, iclass 34, count 0 2006.173.21:35:51.46#ibcon#*mode == 0, iclass 34, count 0 2006.173.21:35:51.46#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.21:35:51.46#ibcon#[25=USB\r\n] 2006.173.21:35:51.46#ibcon#*before write, iclass 34, count 0 2006.173.21:35:51.46#ibcon#enter sib2, iclass 34, count 0 2006.173.21:35:51.46#ibcon#flushed, iclass 34, count 0 2006.173.21:35:51.46#ibcon#about to write, iclass 34, count 0 2006.173.21:35:51.46#ibcon#wrote, iclass 34, count 0 2006.173.21:35:51.46#ibcon#about to read 3, iclass 34, count 0 2006.173.21:35:51.49#ibcon#read 3, iclass 34, count 0 2006.173.21:35:51.49#ibcon#about to read 4, iclass 34, count 0 2006.173.21:35:51.49#ibcon#read 4, iclass 34, count 0 2006.173.21:35:51.49#ibcon#about to read 5, iclass 34, count 0 2006.173.21:35:51.49#ibcon#read 5, iclass 34, count 0 2006.173.21:35:51.49#ibcon#about to read 6, iclass 34, count 0 2006.173.21:35:51.49#ibcon#read 6, iclass 34, count 0 2006.173.21:35:51.49#ibcon#end of sib2, iclass 34, count 0 2006.173.21:35:51.49#ibcon#*after write, iclass 34, count 0 2006.173.21:35:51.49#ibcon#*before return 0, iclass 34, count 0 2006.173.21:35:51.49#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.21:35:51.49#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.21:35:51.49#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.21:35:51.49#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.21:35:51.49$vck44/valo=8,884.99 2006.173.21:35:51.49#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.21:35:51.49#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.21:35:51.49#ibcon#ireg 17 cls_cnt 0 2006.173.21:35:51.49#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.21:35:51.49#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.21:35:51.49#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.21:35:51.49#ibcon#enter wrdev, iclass 36, count 0 2006.173.21:35:51.49#ibcon#first serial, iclass 36, count 0 2006.173.21:35:51.49#ibcon#enter sib2, iclass 36, count 0 2006.173.21:35:51.49#ibcon#flushed, iclass 36, count 0 2006.173.21:35:51.49#ibcon#about to write, iclass 36, count 0 2006.173.21:35:51.49#ibcon#wrote, iclass 36, count 0 2006.173.21:35:51.49#ibcon#about to read 3, iclass 36, count 0 2006.173.21:35:51.51#ibcon#read 3, iclass 36, count 0 2006.173.21:35:51.51#ibcon#about to read 4, iclass 36, count 0 2006.173.21:35:51.51#ibcon#read 4, iclass 36, count 0 2006.173.21:35:51.51#ibcon#about to read 5, iclass 36, count 0 2006.173.21:35:51.51#ibcon#read 5, iclass 36, count 0 2006.173.21:35:51.51#ibcon#about to read 6, iclass 36, count 0 2006.173.21:35:51.51#ibcon#read 6, iclass 36, count 0 2006.173.21:35:51.51#ibcon#end of sib2, iclass 36, count 0 2006.173.21:35:51.51#ibcon#*mode == 0, iclass 36, count 0 2006.173.21:35:51.51#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.21:35:51.51#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.21:35:51.51#ibcon#*before write, iclass 36, count 0 2006.173.21:35:51.51#ibcon#enter sib2, iclass 36, count 0 2006.173.21:35:51.51#ibcon#flushed, iclass 36, count 0 2006.173.21:35:51.51#ibcon#about to write, iclass 36, count 0 2006.173.21:35:51.51#ibcon#wrote, iclass 36, count 0 2006.173.21:35:51.51#ibcon#about to read 3, iclass 36, count 0 2006.173.21:35:51.55#ibcon#read 3, iclass 36, count 0 2006.173.21:35:51.55#ibcon#about to read 4, iclass 36, count 0 2006.173.21:35:51.55#ibcon#read 4, iclass 36, count 0 2006.173.21:35:51.55#ibcon#about to read 5, iclass 36, count 0 2006.173.21:35:51.55#ibcon#read 5, iclass 36, count 0 2006.173.21:35:51.55#ibcon#about to read 6, iclass 36, count 0 2006.173.21:35:51.55#ibcon#read 6, iclass 36, count 0 2006.173.21:35:51.55#ibcon#end of sib2, iclass 36, count 0 2006.173.21:35:51.55#ibcon#*after write, iclass 36, count 0 2006.173.21:35:51.55#ibcon#*before return 0, iclass 36, count 0 2006.173.21:35:51.55#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.21:35:51.55#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.21:35:51.55#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.21:35:51.55#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.21:35:51.55$vck44/va=8,4 2006.173.21:35:51.55#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.21:35:51.55#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.21:35:51.55#ibcon#ireg 11 cls_cnt 2 2006.173.21:35:51.55#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.21:35:51.61#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.21:35:51.61#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.21:35:51.61#ibcon#enter wrdev, iclass 38, count 2 2006.173.21:35:51.61#ibcon#first serial, iclass 38, count 2 2006.173.21:35:51.61#ibcon#enter sib2, iclass 38, count 2 2006.173.21:35:51.61#ibcon#flushed, iclass 38, count 2 2006.173.21:35:51.61#ibcon#about to write, iclass 38, count 2 2006.173.21:35:51.61#ibcon#wrote, iclass 38, count 2 2006.173.21:35:51.61#ibcon#about to read 3, iclass 38, count 2 2006.173.21:35:51.63#ibcon#read 3, iclass 38, count 2 2006.173.21:35:51.63#ibcon#about to read 4, iclass 38, count 2 2006.173.21:35:51.63#ibcon#read 4, iclass 38, count 2 2006.173.21:35:51.63#ibcon#about to read 5, iclass 38, count 2 2006.173.21:35:51.63#ibcon#read 5, iclass 38, count 2 2006.173.21:35:51.63#ibcon#about to read 6, iclass 38, count 2 2006.173.21:35:51.63#ibcon#read 6, iclass 38, count 2 2006.173.21:35:51.63#ibcon#end of sib2, iclass 38, count 2 2006.173.21:35:51.63#ibcon#*mode == 0, iclass 38, count 2 2006.173.21:35:51.63#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.21:35:51.63#ibcon#[25=AT08-04\r\n] 2006.173.21:35:51.63#ibcon#*before write, iclass 38, count 2 2006.173.21:35:51.63#ibcon#enter sib2, iclass 38, count 2 2006.173.21:35:51.63#ibcon#flushed, iclass 38, count 2 2006.173.21:35:51.63#ibcon#about to write, iclass 38, count 2 2006.173.21:35:51.63#ibcon#wrote, iclass 38, count 2 2006.173.21:35:51.63#ibcon#about to read 3, iclass 38, count 2 2006.173.21:35:51.66#ibcon#read 3, iclass 38, count 2 2006.173.21:35:51.66#ibcon#about to read 4, iclass 38, count 2 2006.173.21:35:51.66#ibcon#read 4, iclass 38, count 2 2006.173.21:35:51.66#ibcon#about to read 5, iclass 38, count 2 2006.173.21:35:51.66#ibcon#read 5, iclass 38, count 2 2006.173.21:35:51.66#ibcon#about to read 6, iclass 38, count 2 2006.173.21:35:51.66#ibcon#read 6, iclass 38, count 2 2006.173.21:35:51.66#ibcon#end of sib2, iclass 38, count 2 2006.173.21:35:51.66#ibcon#*after write, iclass 38, count 2 2006.173.21:35:51.66#ibcon#*before return 0, iclass 38, count 2 2006.173.21:35:51.66#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.21:35:51.66#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.21:35:51.66#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.21:35:51.66#ibcon#ireg 7 cls_cnt 0 2006.173.21:35:51.66#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.21:35:51.78#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.21:35:51.78#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.21:35:51.78#ibcon#enter wrdev, iclass 38, count 0 2006.173.21:35:51.78#ibcon#first serial, iclass 38, count 0 2006.173.21:35:51.78#ibcon#enter sib2, iclass 38, count 0 2006.173.21:35:51.78#ibcon#flushed, iclass 38, count 0 2006.173.21:35:51.78#ibcon#about to write, iclass 38, count 0 2006.173.21:35:51.78#ibcon#wrote, iclass 38, count 0 2006.173.21:35:51.78#ibcon#about to read 3, iclass 38, count 0 2006.173.21:35:51.80#ibcon#read 3, iclass 38, count 0 2006.173.21:35:51.80#ibcon#about to read 4, iclass 38, count 0 2006.173.21:35:51.80#ibcon#read 4, iclass 38, count 0 2006.173.21:35:51.80#ibcon#about to read 5, iclass 38, count 0 2006.173.21:35:51.80#ibcon#read 5, iclass 38, count 0 2006.173.21:35:51.80#ibcon#about to read 6, iclass 38, count 0 2006.173.21:35:51.80#ibcon#read 6, iclass 38, count 0 2006.173.21:35:51.80#ibcon#end of sib2, iclass 38, count 0 2006.173.21:35:51.80#ibcon#*mode == 0, iclass 38, count 0 2006.173.21:35:51.80#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.21:35:51.80#ibcon#[25=USB\r\n] 2006.173.21:35:51.80#ibcon#*before write, iclass 38, count 0 2006.173.21:35:51.80#ibcon#enter sib2, iclass 38, count 0 2006.173.21:35:51.80#ibcon#flushed, iclass 38, count 0 2006.173.21:35:51.80#ibcon#about to write, iclass 38, count 0 2006.173.21:35:51.80#ibcon#wrote, iclass 38, count 0 2006.173.21:35:51.80#ibcon#about to read 3, iclass 38, count 0 2006.173.21:35:51.83#ibcon#read 3, iclass 38, count 0 2006.173.21:35:51.83#ibcon#about to read 4, iclass 38, count 0 2006.173.21:35:51.83#ibcon#read 4, iclass 38, count 0 2006.173.21:35:51.83#ibcon#about to read 5, iclass 38, count 0 2006.173.21:35:51.83#ibcon#read 5, iclass 38, count 0 2006.173.21:35:51.83#ibcon#about to read 6, iclass 38, count 0 2006.173.21:35:51.83#ibcon#read 6, iclass 38, count 0 2006.173.21:35:51.83#ibcon#end of sib2, iclass 38, count 0 2006.173.21:35:51.83#ibcon#*after write, iclass 38, count 0 2006.173.21:35:51.83#ibcon#*before return 0, iclass 38, count 0 2006.173.21:35:51.83#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.21:35:51.83#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.21:35:51.83#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.21:35:51.83#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.21:35:51.83$vck44/vblo=1,629.99 2006.173.21:35:51.83#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.21:35:51.83#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.21:35:51.83#ibcon#ireg 17 cls_cnt 0 2006.173.21:35:51.83#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.21:35:51.83#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.21:35:51.83#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.21:35:51.83#ibcon#enter wrdev, iclass 40, count 0 2006.173.21:35:51.83#ibcon#first serial, iclass 40, count 0 2006.173.21:35:51.83#ibcon#enter sib2, iclass 40, count 0 2006.173.21:35:51.83#ibcon#flushed, iclass 40, count 0 2006.173.21:35:51.83#ibcon#about to write, iclass 40, count 0 2006.173.21:35:51.83#ibcon#wrote, iclass 40, count 0 2006.173.21:35:51.83#ibcon#about to read 3, iclass 40, count 0 2006.173.21:35:51.85#ibcon#read 3, iclass 40, count 0 2006.173.21:35:51.85#ibcon#about to read 4, iclass 40, count 0 2006.173.21:35:51.85#ibcon#read 4, iclass 40, count 0 2006.173.21:35:51.85#ibcon#about to read 5, iclass 40, count 0 2006.173.21:35:51.85#ibcon#read 5, iclass 40, count 0 2006.173.21:35:51.85#ibcon#about to read 6, iclass 40, count 0 2006.173.21:35:51.85#ibcon#read 6, iclass 40, count 0 2006.173.21:35:51.85#ibcon#end of sib2, iclass 40, count 0 2006.173.21:35:51.85#ibcon#*mode == 0, iclass 40, count 0 2006.173.21:35:51.85#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.21:35:51.85#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.21:35:51.85#ibcon#*before write, iclass 40, count 0 2006.173.21:35:51.85#ibcon#enter sib2, iclass 40, count 0 2006.173.21:35:51.85#ibcon#flushed, iclass 40, count 0 2006.173.21:35:51.85#ibcon#about to write, iclass 40, count 0 2006.173.21:35:51.85#ibcon#wrote, iclass 40, count 0 2006.173.21:35:51.85#ibcon#about to read 3, iclass 40, count 0 2006.173.21:35:51.89#ibcon#read 3, iclass 40, count 0 2006.173.21:35:51.89#ibcon#about to read 4, iclass 40, count 0 2006.173.21:35:51.89#ibcon#read 4, iclass 40, count 0 2006.173.21:35:51.89#ibcon#about to read 5, iclass 40, count 0 2006.173.21:35:51.89#ibcon#read 5, iclass 40, count 0 2006.173.21:35:51.89#ibcon#about to read 6, iclass 40, count 0 2006.173.21:35:51.89#ibcon#read 6, iclass 40, count 0 2006.173.21:35:51.89#ibcon#end of sib2, iclass 40, count 0 2006.173.21:35:51.89#ibcon#*after write, iclass 40, count 0 2006.173.21:35:51.89#ibcon#*before return 0, iclass 40, count 0 2006.173.21:35:51.89#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.21:35:51.89#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.21:35:51.89#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.21:35:51.89#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.21:35:51.89$vck44/vb=1,4 2006.173.21:35:51.89#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.21:35:51.89#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.21:35:51.89#ibcon#ireg 11 cls_cnt 2 2006.173.21:35:51.89#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.21:35:51.89#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.21:35:51.89#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.21:35:51.89#ibcon#enter wrdev, iclass 4, count 2 2006.173.21:35:51.89#ibcon#first serial, iclass 4, count 2 2006.173.21:35:51.89#ibcon#enter sib2, iclass 4, count 2 2006.173.21:35:51.89#ibcon#flushed, iclass 4, count 2 2006.173.21:35:51.89#ibcon#about to write, iclass 4, count 2 2006.173.21:35:51.89#ibcon#wrote, iclass 4, count 2 2006.173.21:35:51.89#ibcon#about to read 3, iclass 4, count 2 2006.173.21:35:51.91#ibcon#read 3, iclass 4, count 2 2006.173.21:35:51.91#ibcon#about to read 4, iclass 4, count 2 2006.173.21:35:51.91#ibcon#read 4, iclass 4, count 2 2006.173.21:35:51.91#ibcon#about to read 5, iclass 4, count 2 2006.173.21:35:51.91#ibcon#read 5, iclass 4, count 2 2006.173.21:35:51.91#ibcon#about to read 6, iclass 4, count 2 2006.173.21:35:51.91#ibcon#read 6, iclass 4, count 2 2006.173.21:35:51.91#ibcon#end of sib2, iclass 4, count 2 2006.173.21:35:51.91#ibcon#*mode == 0, iclass 4, count 2 2006.173.21:35:51.91#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.21:35:51.91#ibcon#[27=AT01-04\r\n] 2006.173.21:35:51.91#ibcon#*before write, iclass 4, count 2 2006.173.21:35:51.91#ibcon#enter sib2, iclass 4, count 2 2006.173.21:35:51.91#ibcon#flushed, iclass 4, count 2 2006.173.21:35:51.91#ibcon#about to write, iclass 4, count 2 2006.173.21:35:51.91#ibcon#wrote, iclass 4, count 2 2006.173.21:35:51.91#ibcon#about to read 3, iclass 4, count 2 2006.173.21:35:51.94#ibcon#read 3, iclass 4, count 2 2006.173.21:35:51.94#ibcon#about to read 4, iclass 4, count 2 2006.173.21:35:51.94#ibcon#read 4, iclass 4, count 2 2006.173.21:35:51.94#ibcon#about to read 5, iclass 4, count 2 2006.173.21:35:51.94#ibcon#read 5, iclass 4, count 2 2006.173.21:35:51.94#ibcon#about to read 6, iclass 4, count 2 2006.173.21:35:51.94#ibcon#read 6, iclass 4, count 2 2006.173.21:35:51.94#ibcon#end of sib2, iclass 4, count 2 2006.173.21:35:51.94#ibcon#*after write, iclass 4, count 2 2006.173.21:35:51.94#ibcon#*before return 0, iclass 4, count 2 2006.173.21:35:51.94#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.21:35:51.94#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.21:35:51.94#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.21:35:51.94#ibcon#ireg 7 cls_cnt 0 2006.173.21:35:51.94#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.21:35:52.06#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.21:35:52.06#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.21:35:52.06#ibcon#enter wrdev, iclass 4, count 0 2006.173.21:35:52.06#ibcon#first serial, iclass 4, count 0 2006.173.21:35:52.06#ibcon#enter sib2, iclass 4, count 0 2006.173.21:35:52.06#ibcon#flushed, iclass 4, count 0 2006.173.21:35:52.06#ibcon#about to write, iclass 4, count 0 2006.173.21:35:52.06#ibcon#wrote, iclass 4, count 0 2006.173.21:35:52.06#ibcon#about to read 3, iclass 4, count 0 2006.173.21:35:52.08#ibcon#read 3, iclass 4, count 0 2006.173.21:35:52.08#ibcon#about to read 4, iclass 4, count 0 2006.173.21:35:52.08#ibcon#read 4, iclass 4, count 0 2006.173.21:35:52.08#ibcon#about to read 5, iclass 4, count 0 2006.173.21:35:52.08#ibcon#read 5, iclass 4, count 0 2006.173.21:35:52.08#ibcon#about to read 6, iclass 4, count 0 2006.173.21:35:52.08#ibcon#read 6, iclass 4, count 0 2006.173.21:35:52.08#ibcon#end of sib2, iclass 4, count 0 2006.173.21:35:52.08#ibcon#*mode == 0, iclass 4, count 0 2006.173.21:35:52.08#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.21:35:52.08#ibcon#[27=USB\r\n] 2006.173.21:35:52.08#ibcon#*before write, iclass 4, count 0 2006.173.21:35:52.08#ibcon#enter sib2, iclass 4, count 0 2006.173.21:35:52.08#ibcon#flushed, iclass 4, count 0 2006.173.21:35:52.08#ibcon#about to write, iclass 4, count 0 2006.173.21:35:52.08#ibcon#wrote, iclass 4, count 0 2006.173.21:35:52.08#ibcon#about to read 3, iclass 4, count 0 2006.173.21:35:52.11#ibcon#read 3, iclass 4, count 0 2006.173.21:35:52.11#ibcon#about to read 4, iclass 4, count 0 2006.173.21:35:52.11#ibcon#read 4, iclass 4, count 0 2006.173.21:35:52.11#ibcon#about to read 5, iclass 4, count 0 2006.173.21:35:52.11#ibcon#read 5, iclass 4, count 0 2006.173.21:35:52.11#ibcon#about to read 6, iclass 4, count 0 2006.173.21:35:52.11#ibcon#read 6, iclass 4, count 0 2006.173.21:35:52.11#ibcon#end of sib2, iclass 4, count 0 2006.173.21:35:52.11#ibcon#*after write, iclass 4, count 0 2006.173.21:35:52.11#ibcon#*before return 0, iclass 4, count 0 2006.173.21:35:52.11#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.21:35:52.11#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.21:35:52.11#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.21:35:52.11#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.21:35:52.11$vck44/vblo=2,634.99 2006.173.21:35:52.11#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.21:35:52.11#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.21:35:52.11#ibcon#ireg 17 cls_cnt 0 2006.173.21:35:52.11#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.21:35:52.11#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.21:35:52.11#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.21:35:52.11#ibcon#enter wrdev, iclass 6, count 0 2006.173.21:35:52.11#ibcon#first serial, iclass 6, count 0 2006.173.21:35:52.11#ibcon#enter sib2, iclass 6, count 0 2006.173.21:35:52.11#ibcon#flushed, iclass 6, count 0 2006.173.21:35:52.11#ibcon#about to write, iclass 6, count 0 2006.173.21:35:52.11#ibcon#wrote, iclass 6, count 0 2006.173.21:35:52.11#ibcon#about to read 3, iclass 6, count 0 2006.173.21:35:52.13#ibcon#read 3, iclass 6, count 0 2006.173.21:35:52.13#ibcon#about to read 4, iclass 6, count 0 2006.173.21:35:52.13#ibcon#read 4, iclass 6, count 0 2006.173.21:35:52.13#ibcon#about to read 5, iclass 6, count 0 2006.173.21:35:52.13#ibcon#read 5, iclass 6, count 0 2006.173.21:35:52.13#ibcon#about to read 6, iclass 6, count 0 2006.173.21:35:52.13#ibcon#read 6, iclass 6, count 0 2006.173.21:35:52.13#ibcon#end of sib2, iclass 6, count 0 2006.173.21:35:52.13#ibcon#*mode == 0, iclass 6, count 0 2006.173.21:35:52.13#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.21:35:52.13#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.21:35:52.13#ibcon#*before write, iclass 6, count 0 2006.173.21:35:52.13#ibcon#enter sib2, iclass 6, count 0 2006.173.21:35:52.13#ibcon#flushed, iclass 6, count 0 2006.173.21:35:52.13#ibcon#about to write, iclass 6, count 0 2006.173.21:35:52.13#ibcon#wrote, iclass 6, count 0 2006.173.21:35:52.13#ibcon#about to read 3, iclass 6, count 0 2006.173.21:35:52.17#ibcon#read 3, iclass 6, count 0 2006.173.21:35:52.17#ibcon#about to read 4, iclass 6, count 0 2006.173.21:35:52.17#ibcon#read 4, iclass 6, count 0 2006.173.21:35:52.17#ibcon#about to read 5, iclass 6, count 0 2006.173.21:35:52.17#ibcon#read 5, iclass 6, count 0 2006.173.21:35:52.17#ibcon#about to read 6, iclass 6, count 0 2006.173.21:35:52.17#ibcon#read 6, iclass 6, count 0 2006.173.21:35:52.17#ibcon#end of sib2, iclass 6, count 0 2006.173.21:35:52.17#ibcon#*after write, iclass 6, count 0 2006.173.21:35:52.17#ibcon#*before return 0, iclass 6, count 0 2006.173.21:35:52.17#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.21:35:52.17#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.21:35:52.17#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.21:35:52.17#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.21:35:52.17$vck44/vb=2,4 2006.173.21:35:52.17#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.21:35:52.17#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.21:35:52.17#ibcon#ireg 11 cls_cnt 2 2006.173.21:35:52.17#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.21:35:52.23#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.21:35:52.23#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.21:35:52.23#ibcon#enter wrdev, iclass 10, count 2 2006.173.21:35:52.23#ibcon#first serial, iclass 10, count 2 2006.173.21:35:52.23#ibcon#enter sib2, iclass 10, count 2 2006.173.21:35:52.23#ibcon#flushed, iclass 10, count 2 2006.173.21:35:52.23#ibcon#about to write, iclass 10, count 2 2006.173.21:35:52.23#ibcon#wrote, iclass 10, count 2 2006.173.21:35:52.23#ibcon#about to read 3, iclass 10, count 2 2006.173.21:35:52.25#ibcon#read 3, iclass 10, count 2 2006.173.21:35:52.25#ibcon#about to read 4, iclass 10, count 2 2006.173.21:35:52.25#ibcon#read 4, iclass 10, count 2 2006.173.21:35:52.25#ibcon#about to read 5, iclass 10, count 2 2006.173.21:35:52.25#ibcon#read 5, iclass 10, count 2 2006.173.21:35:52.25#ibcon#about to read 6, iclass 10, count 2 2006.173.21:35:52.25#ibcon#read 6, iclass 10, count 2 2006.173.21:35:52.25#ibcon#end of sib2, iclass 10, count 2 2006.173.21:35:52.25#ibcon#*mode == 0, iclass 10, count 2 2006.173.21:35:52.25#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.21:35:52.25#ibcon#[27=AT02-04\r\n] 2006.173.21:35:52.25#ibcon#*before write, iclass 10, count 2 2006.173.21:35:52.25#ibcon#enter sib2, iclass 10, count 2 2006.173.21:35:52.25#ibcon#flushed, iclass 10, count 2 2006.173.21:35:52.25#ibcon#about to write, iclass 10, count 2 2006.173.21:35:52.25#ibcon#wrote, iclass 10, count 2 2006.173.21:35:52.25#ibcon#about to read 3, iclass 10, count 2 2006.173.21:35:52.28#ibcon#read 3, iclass 10, count 2 2006.173.21:35:52.28#ibcon#about to read 4, iclass 10, count 2 2006.173.21:35:52.28#ibcon#read 4, iclass 10, count 2 2006.173.21:35:52.28#ibcon#about to read 5, iclass 10, count 2 2006.173.21:35:52.28#ibcon#read 5, iclass 10, count 2 2006.173.21:35:52.28#ibcon#about to read 6, iclass 10, count 2 2006.173.21:35:52.28#ibcon#read 6, iclass 10, count 2 2006.173.21:35:52.28#ibcon#end of sib2, iclass 10, count 2 2006.173.21:35:52.28#ibcon#*after write, iclass 10, count 2 2006.173.21:35:52.28#ibcon#*before return 0, iclass 10, count 2 2006.173.21:35:52.28#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.21:35:52.28#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.21:35:52.28#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.21:35:52.28#ibcon#ireg 7 cls_cnt 0 2006.173.21:35:52.28#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.21:35:52.40#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.21:35:52.40#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.21:35:52.40#ibcon#enter wrdev, iclass 10, count 0 2006.173.21:35:52.40#ibcon#first serial, iclass 10, count 0 2006.173.21:35:52.40#ibcon#enter sib2, iclass 10, count 0 2006.173.21:35:52.40#ibcon#flushed, iclass 10, count 0 2006.173.21:35:52.40#ibcon#about to write, iclass 10, count 0 2006.173.21:35:52.40#ibcon#wrote, iclass 10, count 0 2006.173.21:35:52.40#ibcon#about to read 3, iclass 10, count 0 2006.173.21:35:52.42#ibcon#read 3, iclass 10, count 0 2006.173.21:35:52.42#ibcon#about to read 4, iclass 10, count 0 2006.173.21:35:52.42#ibcon#read 4, iclass 10, count 0 2006.173.21:35:52.42#ibcon#about to read 5, iclass 10, count 0 2006.173.21:35:52.42#ibcon#read 5, iclass 10, count 0 2006.173.21:35:52.42#ibcon#about to read 6, iclass 10, count 0 2006.173.21:35:52.42#ibcon#read 6, iclass 10, count 0 2006.173.21:35:52.42#ibcon#end of sib2, iclass 10, count 0 2006.173.21:35:52.42#ibcon#*mode == 0, iclass 10, count 0 2006.173.21:35:52.42#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.21:35:52.42#ibcon#[27=USB\r\n] 2006.173.21:35:52.42#ibcon#*before write, iclass 10, count 0 2006.173.21:35:52.42#ibcon#enter sib2, iclass 10, count 0 2006.173.21:35:52.42#ibcon#flushed, iclass 10, count 0 2006.173.21:35:52.42#ibcon#about to write, iclass 10, count 0 2006.173.21:35:52.42#ibcon#wrote, iclass 10, count 0 2006.173.21:35:52.42#ibcon#about to read 3, iclass 10, count 0 2006.173.21:35:52.45#ibcon#read 3, iclass 10, count 0 2006.173.21:35:52.45#ibcon#about to read 4, iclass 10, count 0 2006.173.21:35:52.45#ibcon#read 4, iclass 10, count 0 2006.173.21:35:52.45#ibcon#about to read 5, iclass 10, count 0 2006.173.21:35:52.45#ibcon#read 5, iclass 10, count 0 2006.173.21:35:52.45#ibcon#about to read 6, iclass 10, count 0 2006.173.21:35:52.45#ibcon#read 6, iclass 10, count 0 2006.173.21:35:52.45#ibcon#end of sib2, iclass 10, count 0 2006.173.21:35:52.45#ibcon#*after write, iclass 10, count 0 2006.173.21:35:52.45#ibcon#*before return 0, iclass 10, count 0 2006.173.21:35:52.45#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.21:35:52.45#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.21:35:52.45#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.21:35:52.45#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.21:35:52.45$vck44/vblo=3,649.99 2006.173.21:35:52.45#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.21:35:52.45#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.21:35:52.45#ibcon#ireg 17 cls_cnt 0 2006.173.21:35:52.45#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.21:35:52.45#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.21:35:52.45#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.21:35:52.45#ibcon#enter wrdev, iclass 12, count 0 2006.173.21:35:52.45#ibcon#first serial, iclass 12, count 0 2006.173.21:35:52.45#ibcon#enter sib2, iclass 12, count 0 2006.173.21:35:52.45#ibcon#flushed, iclass 12, count 0 2006.173.21:35:52.45#ibcon#about to write, iclass 12, count 0 2006.173.21:35:52.45#ibcon#wrote, iclass 12, count 0 2006.173.21:35:52.45#ibcon#about to read 3, iclass 12, count 0 2006.173.21:35:52.47#ibcon#read 3, iclass 12, count 0 2006.173.21:35:52.47#ibcon#about to read 4, iclass 12, count 0 2006.173.21:35:52.47#ibcon#read 4, iclass 12, count 0 2006.173.21:35:52.47#ibcon#about to read 5, iclass 12, count 0 2006.173.21:35:52.47#ibcon#read 5, iclass 12, count 0 2006.173.21:35:52.47#ibcon#about to read 6, iclass 12, count 0 2006.173.21:35:52.47#ibcon#read 6, iclass 12, count 0 2006.173.21:35:52.47#ibcon#end of sib2, iclass 12, count 0 2006.173.21:35:52.47#ibcon#*mode == 0, iclass 12, count 0 2006.173.21:35:52.47#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.21:35:52.47#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.21:35:52.47#ibcon#*before write, iclass 12, count 0 2006.173.21:35:52.47#ibcon#enter sib2, iclass 12, count 0 2006.173.21:35:52.47#ibcon#flushed, iclass 12, count 0 2006.173.21:35:52.47#ibcon#about to write, iclass 12, count 0 2006.173.21:35:52.47#ibcon#wrote, iclass 12, count 0 2006.173.21:35:52.47#ibcon#about to read 3, iclass 12, count 0 2006.173.21:35:52.51#ibcon#read 3, iclass 12, count 0 2006.173.21:35:52.51#ibcon#about to read 4, iclass 12, count 0 2006.173.21:35:52.51#ibcon#read 4, iclass 12, count 0 2006.173.21:35:52.51#ibcon#about to read 5, iclass 12, count 0 2006.173.21:35:52.51#ibcon#read 5, iclass 12, count 0 2006.173.21:35:52.51#ibcon#about to read 6, iclass 12, count 0 2006.173.21:35:52.51#ibcon#read 6, iclass 12, count 0 2006.173.21:35:52.51#ibcon#end of sib2, iclass 12, count 0 2006.173.21:35:52.51#ibcon#*after write, iclass 12, count 0 2006.173.21:35:52.51#ibcon#*before return 0, iclass 12, count 0 2006.173.21:35:52.51#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.21:35:52.51#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.21:35:52.51#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.21:35:52.51#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.21:35:52.51$vck44/vb=3,4 2006.173.21:35:52.51#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.21:35:52.51#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.21:35:52.51#ibcon#ireg 11 cls_cnt 2 2006.173.21:35:52.51#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.21:35:52.57#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.21:35:52.57#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.21:35:52.57#ibcon#enter wrdev, iclass 14, count 2 2006.173.21:35:52.57#ibcon#first serial, iclass 14, count 2 2006.173.21:35:52.57#ibcon#enter sib2, iclass 14, count 2 2006.173.21:35:52.57#ibcon#flushed, iclass 14, count 2 2006.173.21:35:52.57#ibcon#about to write, iclass 14, count 2 2006.173.21:35:52.57#ibcon#wrote, iclass 14, count 2 2006.173.21:35:52.57#ibcon#about to read 3, iclass 14, count 2 2006.173.21:35:52.59#ibcon#read 3, iclass 14, count 2 2006.173.21:35:52.59#ibcon#about to read 4, iclass 14, count 2 2006.173.21:35:52.59#ibcon#read 4, iclass 14, count 2 2006.173.21:35:52.59#ibcon#about to read 5, iclass 14, count 2 2006.173.21:35:52.59#ibcon#read 5, iclass 14, count 2 2006.173.21:35:52.59#ibcon#about to read 6, iclass 14, count 2 2006.173.21:35:52.59#ibcon#read 6, iclass 14, count 2 2006.173.21:35:52.59#ibcon#end of sib2, iclass 14, count 2 2006.173.21:35:52.59#ibcon#*mode == 0, iclass 14, count 2 2006.173.21:35:52.59#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.21:35:52.59#ibcon#[27=AT03-04\r\n] 2006.173.21:35:52.59#ibcon#*before write, iclass 14, count 2 2006.173.21:35:52.59#ibcon#enter sib2, iclass 14, count 2 2006.173.21:35:52.59#ibcon#flushed, iclass 14, count 2 2006.173.21:35:52.59#ibcon#about to write, iclass 14, count 2 2006.173.21:35:52.59#ibcon#wrote, iclass 14, count 2 2006.173.21:35:52.59#ibcon#about to read 3, iclass 14, count 2 2006.173.21:35:52.62#ibcon#read 3, iclass 14, count 2 2006.173.21:35:52.62#ibcon#about to read 4, iclass 14, count 2 2006.173.21:35:52.62#ibcon#read 4, iclass 14, count 2 2006.173.21:35:52.62#ibcon#about to read 5, iclass 14, count 2 2006.173.21:35:52.62#ibcon#read 5, iclass 14, count 2 2006.173.21:35:52.62#ibcon#about to read 6, iclass 14, count 2 2006.173.21:35:52.62#ibcon#read 6, iclass 14, count 2 2006.173.21:35:52.62#ibcon#end of sib2, iclass 14, count 2 2006.173.21:35:52.62#ibcon#*after write, iclass 14, count 2 2006.173.21:35:52.62#ibcon#*before return 0, iclass 14, count 2 2006.173.21:35:52.62#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.21:35:52.62#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.21:35:52.62#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.21:35:52.62#ibcon#ireg 7 cls_cnt 0 2006.173.21:35:52.62#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.21:35:52.74#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.21:35:52.74#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.21:35:52.74#ibcon#enter wrdev, iclass 14, count 0 2006.173.21:35:52.74#ibcon#first serial, iclass 14, count 0 2006.173.21:35:52.74#ibcon#enter sib2, iclass 14, count 0 2006.173.21:35:52.74#ibcon#flushed, iclass 14, count 0 2006.173.21:35:52.74#ibcon#about to write, iclass 14, count 0 2006.173.21:35:52.74#ibcon#wrote, iclass 14, count 0 2006.173.21:35:52.74#ibcon#about to read 3, iclass 14, count 0 2006.173.21:35:52.76#ibcon#read 3, iclass 14, count 0 2006.173.21:35:52.76#ibcon#about to read 4, iclass 14, count 0 2006.173.21:35:52.76#ibcon#read 4, iclass 14, count 0 2006.173.21:35:52.76#ibcon#about to read 5, iclass 14, count 0 2006.173.21:35:52.76#ibcon#read 5, iclass 14, count 0 2006.173.21:35:52.76#ibcon#about to read 6, iclass 14, count 0 2006.173.21:35:52.76#ibcon#read 6, iclass 14, count 0 2006.173.21:35:52.76#ibcon#end of sib2, iclass 14, count 0 2006.173.21:35:52.76#ibcon#*mode == 0, iclass 14, count 0 2006.173.21:35:52.76#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.21:35:52.76#ibcon#[27=USB\r\n] 2006.173.21:35:52.76#ibcon#*before write, iclass 14, count 0 2006.173.21:35:52.76#ibcon#enter sib2, iclass 14, count 0 2006.173.21:35:52.76#ibcon#flushed, iclass 14, count 0 2006.173.21:35:52.76#ibcon#about to write, iclass 14, count 0 2006.173.21:35:52.76#ibcon#wrote, iclass 14, count 0 2006.173.21:35:52.76#ibcon#about to read 3, iclass 14, count 0 2006.173.21:35:52.79#ibcon#read 3, iclass 14, count 0 2006.173.21:35:52.79#ibcon#about to read 4, iclass 14, count 0 2006.173.21:35:52.79#ibcon#read 4, iclass 14, count 0 2006.173.21:35:52.79#ibcon#about to read 5, iclass 14, count 0 2006.173.21:35:52.79#ibcon#read 5, iclass 14, count 0 2006.173.21:35:52.79#ibcon#about to read 6, iclass 14, count 0 2006.173.21:35:52.79#ibcon#read 6, iclass 14, count 0 2006.173.21:35:52.79#ibcon#end of sib2, iclass 14, count 0 2006.173.21:35:52.79#ibcon#*after write, iclass 14, count 0 2006.173.21:35:52.79#ibcon#*before return 0, iclass 14, count 0 2006.173.21:35:52.79#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.21:35:52.79#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.21:35:52.79#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.21:35:52.79#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.21:35:52.79$vck44/vblo=4,679.99 2006.173.21:35:52.79#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.21:35:52.79#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.21:35:52.79#ibcon#ireg 17 cls_cnt 0 2006.173.21:35:52.79#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.21:35:52.79#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.21:35:52.79#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.21:35:52.79#ibcon#enter wrdev, iclass 16, count 0 2006.173.21:35:52.79#ibcon#first serial, iclass 16, count 0 2006.173.21:35:52.79#ibcon#enter sib2, iclass 16, count 0 2006.173.21:35:52.79#ibcon#flushed, iclass 16, count 0 2006.173.21:35:52.79#ibcon#about to write, iclass 16, count 0 2006.173.21:35:52.79#ibcon#wrote, iclass 16, count 0 2006.173.21:35:52.79#ibcon#about to read 3, iclass 16, count 0 2006.173.21:35:52.81#ibcon#read 3, iclass 16, count 0 2006.173.21:35:52.81#ibcon#about to read 4, iclass 16, count 0 2006.173.21:35:52.81#ibcon#read 4, iclass 16, count 0 2006.173.21:35:52.81#ibcon#about to read 5, iclass 16, count 0 2006.173.21:35:52.81#ibcon#read 5, iclass 16, count 0 2006.173.21:35:52.81#ibcon#about to read 6, iclass 16, count 0 2006.173.21:35:52.81#ibcon#read 6, iclass 16, count 0 2006.173.21:35:52.81#ibcon#end of sib2, iclass 16, count 0 2006.173.21:35:52.81#ibcon#*mode == 0, iclass 16, count 0 2006.173.21:35:52.81#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.21:35:52.81#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.21:35:52.81#ibcon#*before write, iclass 16, count 0 2006.173.21:35:52.81#ibcon#enter sib2, iclass 16, count 0 2006.173.21:35:52.81#ibcon#flushed, iclass 16, count 0 2006.173.21:35:52.81#ibcon#about to write, iclass 16, count 0 2006.173.21:35:52.81#ibcon#wrote, iclass 16, count 0 2006.173.21:35:52.81#ibcon#about to read 3, iclass 16, count 0 2006.173.21:35:52.85#ibcon#read 3, iclass 16, count 0 2006.173.21:35:52.85#ibcon#about to read 4, iclass 16, count 0 2006.173.21:35:52.85#ibcon#read 4, iclass 16, count 0 2006.173.21:35:52.85#ibcon#about to read 5, iclass 16, count 0 2006.173.21:35:52.85#ibcon#read 5, iclass 16, count 0 2006.173.21:35:52.85#ibcon#about to read 6, iclass 16, count 0 2006.173.21:35:52.85#ibcon#read 6, iclass 16, count 0 2006.173.21:35:52.85#ibcon#end of sib2, iclass 16, count 0 2006.173.21:35:52.85#ibcon#*after write, iclass 16, count 0 2006.173.21:35:52.85#ibcon#*before return 0, iclass 16, count 0 2006.173.21:35:52.85#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.21:35:52.85#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.21:35:52.85#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.21:35:52.85#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.21:35:52.85$vck44/vb=4,4 2006.173.21:35:52.85#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.21:35:52.85#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.21:35:52.85#ibcon#ireg 11 cls_cnt 2 2006.173.21:35:52.85#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.21:35:52.91#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.21:35:52.91#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.21:35:52.91#ibcon#enter wrdev, iclass 18, count 2 2006.173.21:35:52.91#ibcon#first serial, iclass 18, count 2 2006.173.21:35:52.91#ibcon#enter sib2, iclass 18, count 2 2006.173.21:35:52.91#ibcon#flushed, iclass 18, count 2 2006.173.21:35:52.91#ibcon#about to write, iclass 18, count 2 2006.173.21:35:52.91#ibcon#wrote, iclass 18, count 2 2006.173.21:35:52.91#ibcon#about to read 3, iclass 18, count 2 2006.173.21:35:52.93#ibcon#read 3, iclass 18, count 2 2006.173.21:35:52.93#ibcon#about to read 4, iclass 18, count 2 2006.173.21:35:52.93#ibcon#read 4, iclass 18, count 2 2006.173.21:35:52.93#ibcon#about to read 5, iclass 18, count 2 2006.173.21:35:52.93#ibcon#read 5, iclass 18, count 2 2006.173.21:35:52.93#ibcon#about to read 6, iclass 18, count 2 2006.173.21:35:52.93#ibcon#read 6, iclass 18, count 2 2006.173.21:35:52.93#ibcon#end of sib2, iclass 18, count 2 2006.173.21:35:52.93#ibcon#*mode == 0, iclass 18, count 2 2006.173.21:35:52.93#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.21:35:52.93#ibcon#[27=AT04-04\r\n] 2006.173.21:35:52.93#ibcon#*before write, iclass 18, count 2 2006.173.21:35:52.93#ibcon#enter sib2, iclass 18, count 2 2006.173.21:35:52.93#ibcon#flushed, iclass 18, count 2 2006.173.21:35:52.93#ibcon#about to write, iclass 18, count 2 2006.173.21:35:52.93#ibcon#wrote, iclass 18, count 2 2006.173.21:35:52.93#ibcon#about to read 3, iclass 18, count 2 2006.173.21:35:52.96#ibcon#read 3, iclass 18, count 2 2006.173.21:35:52.96#ibcon#about to read 4, iclass 18, count 2 2006.173.21:35:52.96#ibcon#read 4, iclass 18, count 2 2006.173.21:35:52.96#ibcon#about to read 5, iclass 18, count 2 2006.173.21:35:52.96#ibcon#read 5, iclass 18, count 2 2006.173.21:35:52.96#ibcon#about to read 6, iclass 18, count 2 2006.173.21:35:52.96#ibcon#read 6, iclass 18, count 2 2006.173.21:35:52.96#ibcon#end of sib2, iclass 18, count 2 2006.173.21:35:52.96#ibcon#*after write, iclass 18, count 2 2006.173.21:35:52.96#ibcon#*before return 0, iclass 18, count 2 2006.173.21:35:52.96#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.21:35:52.96#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.21:35:52.96#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.21:35:52.96#ibcon#ireg 7 cls_cnt 0 2006.173.21:35:52.96#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.21:35:53.08#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.21:35:53.08#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.21:35:53.08#ibcon#enter wrdev, iclass 18, count 0 2006.173.21:35:53.08#ibcon#first serial, iclass 18, count 0 2006.173.21:35:53.08#ibcon#enter sib2, iclass 18, count 0 2006.173.21:35:53.08#ibcon#flushed, iclass 18, count 0 2006.173.21:35:53.08#ibcon#about to write, iclass 18, count 0 2006.173.21:35:53.08#ibcon#wrote, iclass 18, count 0 2006.173.21:35:53.08#ibcon#about to read 3, iclass 18, count 0 2006.173.21:35:53.10#ibcon#read 3, iclass 18, count 0 2006.173.21:35:53.10#ibcon#about to read 4, iclass 18, count 0 2006.173.21:35:53.10#ibcon#read 4, iclass 18, count 0 2006.173.21:35:53.10#ibcon#about to read 5, iclass 18, count 0 2006.173.21:35:53.10#ibcon#read 5, iclass 18, count 0 2006.173.21:35:53.10#ibcon#about to read 6, iclass 18, count 0 2006.173.21:35:53.10#ibcon#read 6, iclass 18, count 0 2006.173.21:35:53.10#ibcon#end of sib2, iclass 18, count 0 2006.173.21:35:53.10#ibcon#*mode == 0, iclass 18, count 0 2006.173.21:35:53.10#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.21:35:53.10#ibcon#[27=USB\r\n] 2006.173.21:35:53.10#ibcon#*before write, iclass 18, count 0 2006.173.21:35:53.10#ibcon#enter sib2, iclass 18, count 0 2006.173.21:35:53.10#ibcon#flushed, iclass 18, count 0 2006.173.21:35:53.10#ibcon#about to write, iclass 18, count 0 2006.173.21:35:53.10#ibcon#wrote, iclass 18, count 0 2006.173.21:35:53.10#ibcon#about to read 3, iclass 18, count 0 2006.173.21:35:53.13#ibcon#read 3, iclass 18, count 0 2006.173.21:35:53.13#ibcon#about to read 4, iclass 18, count 0 2006.173.21:35:53.13#ibcon#read 4, iclass 18, count 0 2006.173.21:35:53.13#ibcon#about to read 5, iclass 18, count 0 2006.173.21:35:53.13#ibcon#read 5, iclass 18, count 0 2006.173.21:35:53.13#ibcon#about to read 6, iclass 18, count 0 2006.173.21:35:53.13#ibcon#read 6, iclass 18, count 0 2006.173.21:35:53.13#ibcon#end of sib2, iclass 18, count 0 2006.173.21:35:53.13#ibcon#*after write, iclass 18, count 0 2006.173.21:35:53.13#ibcon#*before return 0, iclass 18, count 0 2006.173.21:35:53.13#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.21:35:53.13#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.21:35:53.13#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.21:35:53.13#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.21:35:53.13$vck44/vblo=5,709.99 2006.173.21:35:53.13#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.21:35:53.13#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.21:35:53.13#ibcon#ireg 17 cls_cnt 0 2006.173.21:35:53.13#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.21:35:53.13#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.21:35:53.13#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.21:35:53.13#ibcon#enter wrdev, iclass 20, count 0 2006.173.21:35:53.13#ibcon#first serial, iclass 20, count 0 2006.173.21:35:53.13#ibcon#enter sib2, iclass 20, count 0 2006.173.21:35:53.13#ibcon#flushed, iclass 20, count 0 2006.173.21:35:53.13#ibcon#about to write, iclass 20, count 0 2006.173.21:35:53.13#ibcon#wrote, iclass 20, count 0 2006.173.21:35:53.13#ibcon#about to read 3, iclass 20, count 0 2006.173.21:35:53.15#ibcon#read 3, iclass 20, count 0 2006.173.21:35:53.15#ibcon#about to read 4, iclass 20, count 0 2006.173.21:35:53.15#ibcon#read 4, iclass 20, count 0 2006.173.21:35:53.15#ibcon#about to read 5, iclass 20, count 0 2006.173.21:35:53.15#ibcon#read 5, iclass 20, count 0 2006.173.21:35:53.15#ibcon#about to read 6, iclass 20, count 0 2006.173.21:35:53.15#ibcon#read 6, iclass 20, count 0 2006.173.21:35:53.15#ibcon#end of sib2, iclass 20, count 0 2006.173.21:35:53.15#ibcon#*mode == 0, iclass 20, count 0 2006.173.21:35:53.15#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.21:35:53.15#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.21:35:53.15#ibcon#*before write, iclass 20, count 0 2006.173.21:35:53.15#ibcon#enter sib2, iclass 20, count 0 2006.173.21:35:53.15#ibcon#flushed, iclass 20, count 0 2006.173.21:35:53.15#ibcon#about to write, iclass 20, count 0 2006.173.21:35:53.15#ibcon#wrote, iclass 20, count 0 2006.173.21:35:53.15#ibcon#about to read 3, iclass 20, count 0 2006.173.21:35:53.19#ibcon#read 3, iclass 20, count 0 2006.173.21:35:53.19#ibcon#about to read 4, iclass 20, count 0 2006.173.21:35:53.19#ibcon#read 4, iclass 20, count 0 2006.173.21:35:53.19#ibcon#about to read 5, iclass 20, count 0 2006.173.21:35:53.19#ibcon#read 5, iclass 20, count 0 2006.173.21:35:53.19#ibcon#about to read 6, iclass 20, count 0 2006.173.21:35:53.19#ibcon#read 6, iclass 20, count 0 2006.173.21:35:53.19#ibcon#end of sib2, iclass 20, count 0 2006.173.21:35:53.19#ibcon#*after write, iclass 20, count 0 2006.173.21:35:53.19#ibcon#*before return 0, iclass 20, count 0 2006.173.21:35:53.19#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.21:35:53.19#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.21:35:53.19#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.21:35:53.19#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.21:35:53.19$vck44/vb=5,4 2006.173.21:35:53.19#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.21:35:53.19#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.21:35:53.19#ibcon#ireg 11 cls_cnt 2 2006.173.21:35:53.19#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.21:35:53.25#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.21:35:53.25#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.21:35:53.25#ibcon#enter wrdev, iclass 22, count 2 2006.173.21:35:53.25#ibcon#first serial, iclass 22, count 2 2006.173.21:35:53.25#ibcon#enter sib2, iclass 22, count 2 2006.173.21:35:53.25#ibcon#flushed, iclass 22, count 2 2006.173.21:35:53.25#ibcon#about to write, iclass 22, count 2 2006.173.21:35:53.25#ibcon#wrote, iclass 22, count 2 2006.173.21:35:53.25#ibcon#about to read 3, iclass 22, count 2 2006.173.21:35:53.27#ibcon#read 3, iclass 22, count 2 2006.173.21:35:53.27#ibcon#about to read 4, iclass 22, count 2 2006.173.21:35:53.27#ibcon#read 4, iclass 22, count 2 2006.173.21:35:53.27#ibcon#about to read 5, iclass 22, count 2 2006.173.21:35:53.27#ibcon#read 5, iclass 22, count 2 2006.173.21:35:53.27#ibcon#about to read 6, iclass 22, count 2 2006.173.21:35:53.27#ibcon#read 6, iclass 22, count 2 2006.173.21:35:53.27#ibcon#end of sib2, iclass 22, count 2 2006.173.21:35:53.27#ibcon#*mode == 0, iclass 22, count 2 2006.173.21:35:53.27#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.21:35:53.27#ibcon#[27=AT05-04\r\n] 2006.173.21:35:53.27#ibcon#*before write, iclass 22, count 2 2006.173.21:35:53.27#ibcon#enter sib2, iclass 22, count 2 2006.173.21:35:53.27#ibcon#flushed, iclass 22, count 2 2006.173.21:35:53.27#ibcon#about to write, iclass 22, count 2 2006.173.21:35:53.27#ibcon#wrote, iclass 22, count 2 2006.173.21:35:53.27#ibcon#about to read 3, iclass 22, count 2 2006.173.21:35:53.30#ibcon#read 3, iclass 22, count 2 2006.173.21:35:53.30#ibcon#about to read 4, iclass 22, count 2 2006.173.21:35:53.30#ibcon#read 4, iclass 22, count 2 2006.173.21:35:53.30#ibcon#about to read 5, iclass 22, count 2 2006.173.21:35:53.30#ibcon#read 5, iclass 22, count 2 2006.173.21:35:53.30#ibcon#about to read 6, iclass 22, count 2 2006.173.21:35:53.30#ibcon#read 6, iclass 22, count 2 2006.173.21:35:53.30#ibcon#end of sib2, iclass 22, count 2 2006.173.21:35:53.30#ibcon#*after write, iclass 22, count 2 2006.173.21:35:53.30#ibcon#*before return 0, iclass 22, count 2 2006.173.21:35:53.30#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.21:35:53.30#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.21:35:53.30#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.21:35:53.30#ibcon#ireg 7 cls_cnt 0 2006.173.21:35:53.30#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.21:35:53.42#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.21:35:53.42#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.21:35:53.42#ibcon#enter wrdev, iclass 22, count 0 2006.173.21:35:53.42#ibcon#first serial, iclass 22, count 0 2006.173.21:35:53.42#ibcon#enter sib2, iclass 22, count 0 2006.173.21:35:53.42#ibcon#flushed, iclass 22, count 0 2006.173.21:35:53.42#ibcon#about to write, iclass 22, count 0 2006.173.21:35:53.42#ibcon#wrote, iclass 22, count 0 2006.173.21:35:53.42#ibcon#about to read 3, iclass 22, count 0 2006.173.21:35:53.44#ibcon#read 3, iclass 22, count 0 2006.173.21:35:53.44#ibcon#about to read 4, iclass 22, count 0 2006.173.21:35:53.44#ibcon#read 4, iclass 22, count 0 2006.173.21:35:53.44#ibcon#about to read 5, iclass 22, count 0 2006.173.21:35:53.44#ibcon#read 5, iclass 22, count 0 2006.173.21:35:53.44#ibcon#about to read 6, iclass 22, count 0 2006.173.21:35:53.44#ibcon#read 6, iclass 22, count 0 2006.173.21:35:53.44#ibcon#end of sib2, iclass 22, count 0 2006.173.21:35:53.44#ibcon#*mode == 0, iclass 22, count 0 2006.173.21:35:53.44#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.21:35:53.44#ibcon#[27=USB\r\n] 2006.173.21:35:53.44#ibcon#*before write, iclass 22, count 0 2006.173.21:35:53.44#ibcon#enter sib2, iclass 22, count 0 2006.173.21:35:53.44#ibcon#flushed, iclass 22, count 0 2006.173.21:35:53.44#ibcon#about to write, iclass 22, count 0 2006.173.21:35:53.44#ibcon#wrote, iclass 22, count 0 2006.173.21:35:53.44#ibcon#about to read 3, iclass 22, count 0 2006.173.21:35:53.47#ibcon#read 3, iclass 22, count 0 2006.173.21:35:53.47#ibcon#about to read 4, iclass 22, count 0 2006.173.21:35:53.47#ibcon#read 4, iclass 22, count 0 2006.173.21:35:53.47#ibcon#about to read 5, iclass 22, count 0 2006.173.21:35:53.47#ibcon#read 5, iclass 22, count 0 2006.173.21:35:53.47#ibcon#about to read 6, iclass 22, count 0 2006.173.21:35:53.47#ibcon#read 6, iclass 22, count 0 2006.173.21:35:53.47#ibcon#end of sib2, iclass 22, count 0 2006.173.21:35:53.47#ibcon#*after write, iclass 22, count 0 2006.173.21:35:53.47#ibcon#*before return 0, iclass 22, count 0 2006.173.21:35:53.47#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.21:35:53.47#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.21:35:53.47#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.21:35:53.47#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.21:35:53.47$vck44/vblo=6,719.99 2006.173.21:35:53.47#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.21:35:53.47#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.21:35:53.47#ibcon#ireg 17 cls_cnt 0 2006.173.21:35:53.47#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.21:35:53.47#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.21:35:53.47#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.21:35:53.47#ibcon#enter wrdev, iclass 24, count 0 2006.173.21:35:53.47#ibcon#first serial, iclass 24, count 0 2006.173.21:35:53.47#ibcon#enter sib2, iclass 24, count 0 2006.173.21:35:53.47#ibcon#flushed, iclass 24, count 0 2006.173.21:35:53.47#ibcon#about to write, iclass 24, count 0 2006.173.21:35:53.47#ibcon#wrote, iclass 24, count 0 2006.173.21:35:53.47#ibcon#about to read 3, iclass 24, count 0 2006.173.21:35:53.49#ibcon#read 3, iclass 24, count 0 2006.173.21:35:53.49#ibcon#about to read 4, iclass 24, count 0 2006.173.21:35:53.49#ibcon#read 4, iclass 24, count 0 2006.173.21:35:53.49#ibcon#about to read 5, iclass 24, count 0 2006.173.21:35:53.49#ibcon#read 5, iclass 24, count 0 2006.173.21:35:53.49#ibcon#about to read 6, iclass 24, count 0 2006.173.21:35:53.49#ibcon#read 6, iclass 24, count 0 2006.173.21:35:53.49#ibcon#end of sib2, iclass 24, count 0 2006.173.21:35:53.49#ibcon#*mode == 0, iclass 24, count 0 2006.173.21:35:53.49#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.21:35:53.49#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.21:35:53.49#ibcon#*before write, iclass 24, count 0 2006.173.21:35:53.49#ibcon#enter sib2, iclass 24, count 0 2006.173.21:35:53.49#ibcon#flushed, iclass 24, count 0 2006.173.21:35:53.49#ibcon#about to write, iclass 24, count 0 2006.173.21:35:53.49#ibcon#wrote, iclass 24, count 0 2006.173.21:35:53.49#ibcon#about to read 3, iclass 24, count 0 2006.173.21:35:53.53#ibcon#read 3, iclass 24, count 0 2006.173.21:35:53.53#ibcon#about to read 4, iclass 24, count 0 2006.173.21:35:53.53#ibcon#read 4, iclass 24, count 0 2006.173.21:35:53.53#ibcon#about to read 5, iclass 24, count 0 2006.173.21:35:53.53#ibcon#read 5, iclass 24, count 0 2006.173.21:35:53.53#ibcon#about to read 6, iclass 24, count 0 2006.173.21:35:53.53#ibcon#read 6, iclass 24, count 0 2006.173.21:35:53.53#ibcon#end of sib2, iclass 24, count 0 2006.173.21:35:53.53#ibcon#*after write, iclass 24, count 0 2006.173.21:35:53.53#ibcon#*before return 0, iclass 24, count 0 2006.173.21:35:53.53#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.21:35:53.53#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.21:35:53.53#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.21:35:53.53#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.21:35:53.53$vck44/vb=6,4 2006.173.21:35:53.53#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.21:35:53.53#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.21:35:53.53#ibcon#ireg 11 cls_cnt 2 2006.173.21:35:53.53#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.21:35:53.59#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.21:35:53.59#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.21:35:53.59#ibcon#enter wrdev, iclass 26, count 2 2006.173.21:35:53.59#ibcon#first serial, iclass 26, count 2 2006.173.21:35:53.59#ibcon#enter sib2, iclass 26, count 2 2006.173.21:35:53.59#ibcon#flushed, iclass 26, count 2 2006.173.21:35:53.59#ibcon#about to write, iclass 26, count 2 2006.173.21:35:53.59#ibcon#wrote, iclass 26, count 2 2006.173.21:35:53.59#ibcon#about to read 3, iclass 26, count 2 2006.173.21:35:53.61#ibcon#read 3, iclass 26, count 2 2006.173.21:35:53.61#ibcon#about to read 4, iclass 26, count 2 2006.173.21:35:53.61#ibcon#read 4, iclass 26, count 2 2006.173.21:35:53.61#ibcon#about to read 5, iclass 26, count 2 2006.173.21:35:53.61#ibcon#read 5, iclass 26, count 2 2006.173.21:35:53.61#ibcon#about to read 6, iclass 26, count 2 2006.173.21:35:53.61#ibcon#read 6, iclass 26, count 2 2006.173.21:35:53.61#ibcon#end of sib2, iclass 26, count 2 2006.173.21:35:53.61#ibcon#*mode == 0, iclass 26, count 2 2006.173.21:35:53.61#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.21:35:53.61#ibcon#[27=AT06-04\r\n] 2006.173.21:35:53.61#ibcon#*before write, iclass 26, count 2 2006.173.21:35:53.61#ibcon#enter sib2, iclass 26, count 2 2006.173.21:35:53.61#ibcon#flushed, iclass 26, count 2 2006.173.21:35:53.61#ibcon#about to write, iclass 26, count 2 2006.173.21:35:53.61#ibcon#wrote, iclass 26, count 2 2006.173.21:35:53.61#ibcon#about to read 3, iclass 26, count 2 2006.173.21:35:53.64#ibcon#read 3, iclass 26, count 2 2006.173.21:35:53.64#ibcon#about to read 4, iclass 26, count 2 2006.173.21:35:53.64#ibcon#read 4, iclass 26, count 2 2006.173.21:35:53.64#ibcon#about to read 5, iclass 26, count 2 2006.173.21:35:53.64#ibcon#read 5, iclass 26, count 2 2006.173.21:35:53.64#ibcon#about to read 6, iclass 26, count 2 2006.173.21:35:53.64#ibcon#read 6, iclass 26, count 2 2006.173.21:35:53.64#ibcon#end of sib2, iclass 26, count 2 2006.173.21:35:53.64#ibcon#*after write, iclass 26, count 2 2006.173.21:35:53.64#ibcon#*before return 0, iclass 26, count 2 2006.173.21:35:53.64#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.21:35:53.64#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.21:35:53.64#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.21:35:53.64#ibcon#ireg 7 cls_cnt 0 2006.173.21:35:53.64#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.21:35:53.76#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.21:35:53.76#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.21:35:53.76#ibcon#enter wrdev, iclass 26, count 0 2006.173.21:35:53.76#ibcon#first serial, iclass 26, count 0 2006.173.21:35:53.76#ibcon#enter sib2, iclass 26, count 0 2006.173.21:35:53.76#ibcon#flushed, iclass 26, count 0 2006.173.21:35:53.76#ibcon#about to write, iclass 26, count 0 2006.173.21:35:53.76#ibcon#wrote, iclass 26, count 0 2006.173.21:35:53.76#ibcon#about to read 3, iclass 26, count 0 2006.173.21:35:53.78#ibcon#read 3, iclass 26, count 0 2006.173.21:35:53.78#ibcon#about to read 4, iclass 26, count 0 2006.173.21:35:53.78#ibcon#read 4, iclass 26, count 0 2006.173.21:35:53.78#ibcon#about to read 5, iclass 26, count 0 2006.173.21:35:53.78#ibcon#read 5, iclass 26, count 0 2006.173.21:35:53.78#ibcon#about to read 6, iclass 26, count 0 2006.173.21:35:53.78#ibcon#read 6, iclass 26, count 0 2006.173.21:35:53.78#ibcon#end of sib2, iclass 26, count 0 2006.173.21:35:53.78#ibcon#*mode == 0, iclass 26, count 0 2006.173.21:35:53.78#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.21:35:53.78#ibcon#[27=USB\r\n] 2006.173.21:35:53.78#ibcon#*before write, iclass 26, count 0 2006.173.21:35:53.78#ibcon#enter sib2, iclass 26, count 0 2006.173.21:35:53.78#ibcon#flushed, iclass 26, count 0 2006.173.21:35:53.78#ibcon#about to write, iclass 26, count 0 2006.173.21:35:53.78#ibcon#wrote, iclass 26, count 0 2006.173.21:35:53.78#ibcon#about to read 3, iclass 26, count 0 2006.173.21:35:53.81#ibcon#read 3, iclass 26, count 0 2006.173.21:35:53.81#ibcon#about to read 4, iclass 26, count 0 2006.173.21:35:53.81#ibcon#read 4, iclass 26, count 0 2006.173.21:35:53.81#ibcon#about to read 5, iclass 26, count 0 2006.173.21:35:53.81#ibcon#read 5, iclass 26, count 0 2006.173.21:35:53.81#ibcon#about to read 6, iclass 26, count 0 2006.173.21:35:53.81#ibcon#read 6, iclass 26, count 0 2006.173.21:35:53.81#ibcon#end of sib2, iclass 26, count 0 2006.173.21:35:53.81#ibcon#*after write, iclass 26, count 0 2006.173.21:35:53.81#ibcon#*before return 0, iclass 26, count 0 2006.173.21:35:53.81#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.21:35:53.81#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.21:35:53.81#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.21:35:53.81#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.21:35:53.81$vck44/vblo=7,734.99 2006.173.21:35:53.81#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.21:35:53.81#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.21:35:53.81#ibcon#ireg 17 cls_cnt 0 2006.173.21:35:53.81#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.21:35:53.81#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.21:35:53.81#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.21:35:53.81#ibcon#enter wrdev, iclass 28, count 0 2006.173.21:35:53.81#ibcon#first serial, iclass 28, count 0 2006.173.21:35:53.81#ibcon#enter sib2, iclass 28, count 0 2006.173.21:35:53.81#ibcon#flushed, iclass 28, count 0 2006.173.21:35:53.81#ibcon#about to write, iclass 28, count 0 2006.173.21:35:53.81#ibcon#wrote, iclass 28, count 0 2006.173.21:35:53.81#ibcon#about to read 3, iclass 28, count 0 2006.173.21:35:53.83#ibcon#read 3, iclass 28, count 0 2006.173.21:35:53.83#ibcon#about to read 4, iclass 28, count 0 2006.173.21:35:53.83#ibcon#read 4, iclass 28, count 0 2006.173.21:35:53.83#ibcon#about to read 5, iclass 28, count 0 2006.173.21:35:53.83#ibcon#read 5, iclass 28, count 0 2006.173.21:35:53.83#ibcon#about to read 6, iclass 28, count 0 2006.173.21:35:53.83#ibcon#read 6, iclass 28, count 0 2006.173.21:35:53.83#ibcon#end of sib2, iclass 28, count 0 2006.173.21:35:53.83#ibcon#*mode == 0, iclass 28, count 0 2006.173.21:35:53.83#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.21:35:53.83#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.21:35:53.83#ibcon#*before write, iclass 28, count 0 2006.173.21:35:53.83#ibcon#enter sib2, iclass 28, count 0 2006.173.21:35:53.83#ibcon#flushed, iclass 28, count 0 2006.173.21:35:53.83#ibcon#about to write, iclass 28, count 0 2006.173.21:35:53.83#ibcon#wrote, iclass 28, count 0 2006.173.21:35:53.83#ibcon#about to read 3, iclass 28, count 0 2006.173.21:35:53.87#ibcon#read 3, iclass 28, count 0 2006.173.21:35:53.87#ibcon#about to read 4, iclass 28, count 0 2006.173.21:35:53.87#ibcon#read 4, iclass 28, count 0 2006.173.21:35:53.87#ibcon#about to read 5, iclass 28, count 0 2006.173.21:35:53.87#ibcon#read 5, iclass 28, count 0 2006.173.21:35:53.87#ibcon#about to read 6, iclass 28, count 0 2006.173.21:35:53.87#ibcon#read 6, iclass 28, count 0 2006.173.21:35:53.87#ibcon#end of sib2, iclass 28, count 0 2006.173.21:35:53.87#ibcon#*after write, iclass 28, count 0 2006.173.21:35:53.87#ibcon#*before return 0, iclass 28, count 0 2006.173.21:35:53.87#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.21:35:53.87#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.21:35:53.87#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.21:35:53.87#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.21:35:53.87$vck44/vb=7,4 2006.173.21:35:53.87#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.21:35:53.87#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.21:35:53.87#ibcon#ireg 11 cls_cnt 2 2006.173.21:35:53.87#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.21:35:53.93#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.21:35:53.93#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.21:35:53.93#ibcon#enter wrdev, iclass 30, count 2 2006.173.21:35:53.93#ibcon#first serial, iclass 30, count 2 2006.173.21:35:53.93#ibcon#enter sib2, iclass 30, count 2 2006.173.21:35:53.93#ibcon#flushed, iclass 30, count 2 2006.173.21:35:53.93#ibcon#about to write, iclass 30, count 2 2006.173.21:35:53.93#ibcon#wrote, iclass 30, count 2 2006.173.21:35:53.93#ibcon#about to read 3, iclass 30, count 2 2006.173.21:35:53.95#ibcon#read 3, iclass 30, count 2 2006.173.21:35:53.95#ibcon#about to read 4, iclass 30, count 2 2006.173.21:35:53.95#ibcon#read 4, iclass 30, count 2 2006.173.21:35:53.95#ibcon#about to read 5, iclass 30, count 2 2006.173.21:35:53.95#ibcon#read 5, iclass 30, count 2 2006.173.21:35:53.95#ibcon#about to read 6, iclass 30, count 2 2006.173.21:35:53.95#ibcon#read 6, iclass 30, count 2 2006.173.21:35:53.95#ibcon#end of sib2, iclass 30, count 2 2006.173.21:35:53.95#ibcon#*mode == 0, iclass 30, count 2 2006.173.21:35:53.95#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.21:35:53.95#ibcon#[27=AT07-04\r\n] 2006.173.21:35:53.95#ibcon#*before write, iclass 30, count 2 2006.173.21:35:53.95#ibcon#enter sib2, iclass 30, count 2 2006.173.21:35:53.95#ibcon#flushed, iclass 30, count 2 2006.173.21:35:53.95#ibcon#about to write, iclass 30, count 2 2006.173.21:35:53.95#ibcon#wrote, iclass 30, count 2 2006.173.21:35:53.95#ibcon#about to read 3, iclass 30, count 2 2006.173.21:35:53.98#ibcon#read 3, iclass 30, count 2 2006.173.21:35:53.98#ibcon#about to read 4, iclass 30, count 2 2006.173.21:35:53.98#ibcon#read 4, iclass 30, count 2 2006.173.21:35:53.98#ibcon#about to read 5, iclass 30, count 2 2006.173.21:35:53.98#ibcon#read 5, iclass 30, count 2 2006.173.21:35:53.98#ibcon#about to read 6, iclass 30, count 2 2006.173.21:35:53.98#ibcon#read 6, iclass 30, count 2 2006.173.21:35:53.98#ibcon#end of sib2, iclass 30, count 2 2006.173.21:35:53.98#ibcon#*after write, iclass 30, count 2 2006.173.21:35:53.98#ibcon#*before return 0, iclass 30, count 2 2006.173.21:35:53.98#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.21:35:53.98#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.21:35:53.98#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.21:35:53.98#ibcon#ireg 7 cls_cnt 0 2006.173.21:35:53.98#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.21:35:54.10#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.21:35:54.10#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.21:35:54.10#ibcon#enter wrdev, iclass 30, count 0 2006.173.21:35:54.10#ibcon#first serial, iclass 30, count 0 2006.173.21:35:54.10#ibcon#enter sib2, iclass 30, count 0 2006.173.21:35:54.10#ibcon#flushed, iclass 30, count 0 2006.173.21:35:54.10#ibcon#about to write, iclass 30, count 0 2006.173.21:35:54.10#ibcon#wrote, iclass 30, count 0 2006.173.21:35:54.10#ibcon#about to read 3, iclass 30, count 0 2006.173.21:35:54.12#ibcon#read 3, iclass 30, count 0 2006.173.21:35:54.12#ibcon#about to read 4, iclass 30, count 0 2006.173.21:35:54.12#ibcon#read 4, iclass 30, count 0 2006.173.21:35:54.12#ibcon#about to read 5, iclass 30, count 0 2006.173.21:35:54.12#ibcon#read 5, iclass 30, count 0 2006.173.21:35:54.12#ibcon#about to read 6, iclass 30, count 0 2006.173.21:35:54.12#ibcon#read 6, iclass 30, count 0 2006.173.21:35:54.12#ibcon#end of sib2, iclass 30, count 0 2006.173.21:35:54.12#ibcon#*mode == 0, iclass 30, count 0 2006.173.21:35:54.12#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.21:35:54.12#ibcon#[27=USB\r\n] 2006.173.21:35:54.12#ibcon#*before write, iclass 30, count 0 2006.173.21:35:54.12#ibcon#enter sib2, iclass 30, count 0 2006.173.21:35:54.12#ibcon#flushed, iclass 30, count 0 2006.173.21:35:54.12#ibcon#about to write, iclass 30, count 0 2006.173.21:35:54.12#ibcon#wrote, iclass 30, count 0 2006.173.21:35:54.12#ibcon#about to read 3, iclass 30, count 0 2006.173.21:35:54.15#ibcon#read 3, iclass 30, count 0 2006.173.21:35:54.15#ibcon#about to read 4, iclass 30, count 0 2006.173.21:35:54.15#ibcon#read 4, iclass 30, count 0 2006.173.21:35:54.15#ibcon#about to read 5, iclass 30, count 0 2006.173.21:35:54.15#ibcon#read 5, iclass 30, count 0 2006.173.21:35:54.15#ibcon#about to read 6, iclass 30, count 0 2006.173.21:35:54.15#ibcon#read 6, iclass 30, count 0 2006.173.21:35:54.15#ibcon#end of sib2, iclass 30, count 0 2006.173.21:35:54.15#ibcon#*after write, iclass 30, count 0 2006.173.21:35:54.15#ibcon#*before return 0, iclass 30, count 0 2006.173.21:35:54.15#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.21:35:54.15#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.21:35:54.15#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.21:35:54.15#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.21:35:54.15$vck44/vblo=8,744.99 2006.173.21:35:54.15#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.21:35:54.15#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.21:35:54.15#ibcon#ireg 17 cls_cnt 0 2006.173.21:35:54.15#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.21:35:54.15#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.21:35:54.15#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.21:35:54.15#ibcon#enter wrdev, iclass 32, count 0 2006.173.21:35:54.15#ibcon#first serial, iclass 32, count 0 2006.173.21:35:54.15#ibcon#enter sib2, iclass 32, count 0 2006.173.21:35:54.15#ibcon#flushed, iclass 32, count 0 2006.173.21:35:54.15#ibcon#about to write, iclass 32, count 0 2006.173.21:35:54.15#ibcon#wrote, iclass 32, count 0 2006.173.21:35:54.15#ibcon#about to read 3, iclass 32, count 0 2006.173.21:35:54.17#ibcon#read 3, iclass 32, count 0 2006.173.21:35:54.17#ibcon#about to read 4, iclass 32, count 0 2006.173.21:35:54.17#ibcon#read 4, iclass 32, count 0 2006.173.21:35:54.17#ibcon#about to read 5, iclass 32, count 0 2006.173.21:35:54.17#ibcon#read 5, iclass 32, count 0 2006.173.21:35:54.17#ibcon#about to read 6, iclass 32, count 0 2006.173.21:35:54.17#ibcon#read 6, iclass 32, count 0 2006.173.21:35:54.17#ibcon#end of sib2, iclass 32, count 0 2006.173.21:35:54.17#ibcon#*mode == 0, iclass 32, count 0 2006.173.21:35:54.17#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.21:35:54.17#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.21:35:54.17#ibcon#*before write, iclass 32, count 0 2006.173.21:35:54.17#ibcon#enter sib2, iclass 32, count 0 2006.173.21:35:54.17#ibcon#flushed, iclass 32, count 0 2006.173.21:35:54.17#ibcon#about to write, iclass 32, count 0 2006.173.21:35:54.17#ibcon#wrote, iclass 32, count 0 2006.173.21:35:54.17#ibcon#about to read 3, iclass 32, count 0 2006.173.21:35:54.21#ibcon#read 3, iclass 32, count 0 2006.173.21:35:54.21#ibcon#about to read 4, iclass 32, count 0 2006.173.21:35:54.21#ibcon#read 4, iclass 32, count 0 2006.173.21:35:54.21#ibcon#about to read 5, iclass 32, count 0 2006.173.21:35:54.21#ibcon#read 5, iclass 32, count 0 2006.173.21:35:54.21#ibcon#about to read 6, iclass 32, count 0 2006.173.21:35:54.21#ibcon#read 6, iclass 32, count 0 2006.173.21:35:54.21#ibcon#end of sib2, iclass 32, count 0 2006.173.21:35:54.21#ibcon#*after write, iclass 32, count 0 2006.173.21:35:54.21#ibcon#*before return 0, iclass 32, count 0 2006.173.21:35:54.21#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.21:35:54.21#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.21:35:54.21#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.21:35:54.21#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.21:35:54.21$vck44/vb=8,4 2006.173.21:35:54.21#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.21:35:54.21#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.21:35:54.21#ibcon#ireg 11 cls_cnt 2 2006.173.21:35:54.21#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.21:35:54.27#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.21:35:54.27#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.21:35:54.27#ibcon#enter wrdev, iclass 34, count 2 2006.173.21:35:54.27#ibcon#first serial, iclass 34, count 2 2006.173.21:35:54.27#ibcon#enter sib2, iclass 34, count 2 2006.173.21:35:54.27#ibcon#flushed, iclass 34, count 2 2006.173.21:35:54.27#ibcon#about to write, iclass 34, count 2 2006.173.21:35:54.27#ibcon#wrote, iclass 34, count 2 2006.173.21:35:54.27#ibcon#about to read 3, iclass 34, count 2 2006.173.21:35:54.29#ibcon#read 3, iclass 34, count 2 2006.173.21:35:54.29#ibcon#about to read 4, iclass 34, count 2 2006.173.21:35:54.29#ibcon#read 4, iclass 34, count 2 2006.173.21:35:54.29#ibcon#about to read 5, iclass 34, count 2 2006.173.21:35:54.29#ibcon#read 5, iclass 34, count 2 2006.173.21:35:54.29#ibcon#about to read 6, iclass 34, count 2 2006.173.21:35:54.29#ibcon#read 6, iclass 34, count 2 2006.173.21:35:54.29#ibcon#end of sib2, iclass 34, count 2 2006.173.21:35:54.29#ibcon#*mode == 0, iclass 34, count 2 2006.173.21:35:54.29#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.21:35:54.29#ibcon#[27=AT08-04\r\n] 2006.173.21:35:54.29#ibcon#*before write, iclass 34, count 2 2006.173.21:35:54.29#ibcon#enter sib2, iclass 34, count 2 2006.173.21:35:54.29#ibcon#flushed, iclass 34, count 2 2006.173.21:35:54.29#ibcon#about to write, iclass 34, count 2 2006.173.21:35:54.29#ibcon#wrote, iclass 34, count 2 2006.173.21:35:54.29#ibcon#about to read 3, iclass 34, count 2 2006.173.21:35:54.32#ibcon#read 3, iclass 34, count 2 2006.173.21:35:54.32#ibcon#about to read 4, iclass 34, count 2 2006.173.21:35:54.32#ibcon#read 4, iclass 34, count 2 2006.173.21:35:54.32#ibcon#about to read 5, iclass 34, count 2 2006.173.21:35:54.32#ibcon#read 5, iclass 34, count 2 2006.173.21:35:54.32#ibcon#about to read 6, iclass 34, count 2 2006.173.21:35:54.32#ibcon#read 6, iclass 34, count 2 2006.173.21:35:54.32#ibcon#end of sib2, iclass 34, count 2 2006.173.21:35:54.32#ibcon#*after write, iclass 34, count 2 2006.173.21:35:54.32#ibcon#*before return 0, iclass 34, count 2 2006.173.21:35:54.32#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.21:35:54.32#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.21:35:54.32#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.21:35:54.32#ibcon#ireg 7 cls_cnt 0 2006.173.21:35:54.32#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.21:35:54.44#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.21:35:54.44#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.21:35:54.44#ibcon#enter wrdev, iclass 34, count 0 2006.173.21:35:54.44#ibcon#first serial, iclass 34, count 0 2006.173.21:35:54.44#ibcon#enter sib2, iclass 34, count 0 2006.173.21:35:54.44#ibcon#flushed, iclass 34, count 0 2006.173.21:35:54.44#ibcon#about to write, iclass 34, count 0 2006.173.21:35:54.44#ibcon#wrote, iclass 34, count 0 2006.173.21:35:54.44#ibcon#about to read 3, iclass 34, count 0 2006.173.21:35:54.46#ibcon#read 3, iclass 34, count 0 2006.173.21:35:54.46#ibcon#about to read 4, iclass 34, count 0 2006.173.21:35:54.46#ibcon#read 4, iclass 34, count 0 2006.173.21:35:54.46#ibcon#about to read 5, iclass 34, count 0 2006.173.21:35:54.46#ibcon#read 5, iclass 34, count 0 2006.173.21:35:54.46#ibcon#about to read 6, iclass 34, count 0 2006.173.21:35:54.46#ibcon#read 6, iclass 34, count 0 2006.173.21:35:54.46#ibcon#end of sib2, iclass 34, count 0 2006.173.21:35:54.46#ibcon#*mode == 0, iclass 34, count 0 2006.173.21:35:54.46#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.21:35:54.46#ibcon#[27=USB\r\n] 2006.173.21:35:54.46#ibcon#*before write, iclass 34, count 0 2006.173.21:35:54.46#ibcon#enter sib2, iclass 34, count 0 2006.173.21:35:54.46#ibcon#flushed, iclass 34, count 0 2006.173.21:35:54.46#ibcon#about to write, iclass 34, count 0 2006.173.21:35:54.46#ibcon#wrote, iclass 34, count 0 2006.173.21:35:54.46#ibcon#about to read 3, iclass 34, count 0 2006.173.21:35:54.49#ibcon#read 3, iclass 34, count 0 2006.173.21:35:54.49#ibcon#about to read 4, iclass 34, count 0 2006.173.21:35:54.49#ibcon#read 4, iclass 34, count 0 2006.173.21:35:54.49#ibcon#about to read 5, iclass 34, count 0 2006.173.21:35:54.49#ibcon#read 5, iclass 34, count 0 2006.173.21:35:54.49#ibcon#about to read 6, iclass 34, count 0 2006.173.21:35:54.49#ibcon#read 6, iclass 34, count 0 2006.173.21:35:54.49#ibcon#end of sib2, iclass 34, count 0 2006.173.21:35:54.49#ibcon#*after write, iclass 34, count 0 2006.173.21:35:54.49#ibcon#*before return 0, iclass 34, count 0 2006.173.21:35:54.49#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.21:35:54.49#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.21:35:54.49#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.21:35:54.49#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.21:35:54.49$vck44/vabw=wide 2006.173.21:35:54.49#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.21:35:54.49#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.21:35:54.49#ibcon#ireg 8 cls_cnt 0 2006.173.21:35:54.49#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.21:35:54.49#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.21:35:54.49#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.21:35:54.49#ibcon#enter wrdev, iclass 36, count 0 2006.173.21:35:54.49#ibcon#first serial, iclass 36, count 0 2006.173.21:35:54.49#ibcon#enter sib2, iclass 36, count 0 2006.173.21:35:54.49#ibcon#flushed, iclass 36, count 0 2006.173.21:35:54.49#ibcon#about to write, iclass 36, count 0 2006.173.21:35:54.49#ibcon#wrote, iclass 36, count 0 2006.173.21:35:54.49#ibcon#about to read 3, iclass 36, count 0 2006.173.21:35:54.51#ibcon#read 3, iclass 36, count 0 2006.173.21:35:54.51#ibcon#about to read 4, iclass 36, count 0 2006.173.21:35:54.51#ibcon#read 4, iclass 36, count 0 2006.173.21:35:54.51#ibcon#about to read 5, iclass 36, count 0 2006.173.21:35:54.51#ibcon#read 5, iclass 36, count 0 2006.173.21:35:54.51#ibcon#about to read 6, iclass 36, count 0 2006.173.21:35:54.51#ibcon#read 6, iclass 36, count 0 2006.173.21:35:54.51#ibcon#end of sib2, iclass 36, count 0 2006.173.21:35:54.51#ibcon#*mode == 0, iclass 36, count 0 2006.173.21:35:54.51#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.21:35:54.51#ibcon#[25=BW32\r\n] 2006.173.21:35:54.51#ibcon#*before write, iclass 36, count 0 2006.173.21:35:54.51#ibcon#enter sib2, iclass 36, count 0 2006.173.21:35:54.51#ibcon#flushed, iclass 36, count 0 2006.173.21:35:54.51#ibcon#about to write, iclass 36, count 0 2006.173.21:35:54.51#ibcon#wrote, iclass 36, count 0 2006.173.21:35:54.51#ibcon#about to read 3, iclass 36, count 0 2006.173.21:35:54.54#ibcon#read 3, iclass 36, count 0 2006.173.21:35:54.54#ibcon#about to read 4, iclass 36, count 0 2006.173.21:35:54.54#ibcon#read 4, iclass 36, count 0 2006.173.21:35:54.54#ibcon#about to read 5, iclass 36, count 0 2006.173.21:35:54.54#ibcon#read 5, iclass 36, count 0 2006.173.21:35:54.54#ibcon#about to read 6, iclass 36, count 0 2006.173.21:35:54.54#ibcon#read 6, iclass 36, count 0 2006.173.21:35:54.54#ibcon#end of sib2, iclass 36, count 0 2006.173.21:35:54.54#ibcon#*after write, iclass 36, count 0 2006.173.21:35:54.54#ibcon#*before return 0, iclass 36, count 0 2006.173.21:35:54.54#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.21:35:54.54#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.21:35:54.54#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.21:35:54.54#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.21:35:54.54$vck44/vbbw=wide 2006.173.21:35:54.54#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.21:35:54.54#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.21:35:54.54#ibcon#ireg 8 cls_cnt 0 2006.173.21:35:54.54#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.21:35:54.61#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.21:35:54.61#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.21:35:54.61#ibcon#enter wrdev, iclass 38, count 0 2006.173.21:35:54.61#ibcon#first serial, iclass 38, count 0 2006.173.21:35:54.61#ibcon#enter sib2, iclass 38, count 0 2006.173.21:35:54.61#ibcon#flushed, iclass 38, count 0 2006.173.21:35:54.61#ibcon#about to write, iclass 38, count 0 2006.173.21:35:54.61#ibcon#wrote, iclass 38, count 0 2006.173.21:35:54.61#ibcon#about to read 3, iclass 38, count 0 2006.173.21:35:54.63#ibcon#read 3, iclass 38, count 0 2006.173.21:35:54.63#ibcon#about to read 4, iclass 38, count 0 2006.173.21:35:54.63#ibcon#read 4, iclass 38, count 0 2006.173.21:35:54.63#ibcon#about to read 5, iclass 38, count 0 2006.173.21:35:54.63#ibcon#read 5, iclass 38, count 0 2006.173.21:35:54.63#ibcon#about to read 6, iclass 38, count 0 2006.173.21:35:54.63#ibcon#read 6, iclass 38, count 0 2006.173.21:35:54.63#ibcon#end of sib2, iclass 38, count 0 2006.173.21:35:54.63#ibcon#*mode == 0, iclass 38, count 0 2006.173.21:35:54.63#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.21:35:54.63#ibcon#[27=BW32\r\n] 2006.173.21:35:54.63#ibcon#*before write, iclass 38, count 0 2006.173.21:35:54.63#ibcon#enter sib2, iclass 38, count 0 2006.173.21:35:54.63#ibcon#flushed, iclass 38, count 0 2006.173.21:35:54.63#ibcon#about to write, iclass 38, count 0 2006.173.21:35:54.63#ibcon#wrote, iclass 38, count 0 2006.173.21:35:54.63#ibcon#about to read 3, iclass 38, count 0 2006.173.21:35:54.66#ibcon#read 3, iclass 38, count 0 2006.173.21:35:54.66#ibcon#about to read 4, iclass 38, count 0 2006.173.21:35:54.66#ibcon#read 4, iclass 38, count 0 2006.173.21:35:54.66#ibcon#about to read 5, iclass 38, count 0 2006.173.21:35:54.66#ibcon#read 5, iclass 38, count 0 2006.173.21:35:54.66#ibcon#about to read 6, iclass 38, count 0 2006.173.21:35:54.66#ibcon#read 6, iclass 38, count 0 2006.173.21:35:54.66#ibcon#end of sib2, iclass 38, count 0 2006.173.21:35:54.66#ibcon#*after write, iclass 38, count 0 2006.173.21:35:54.66#ibcon#*before return 0, iclass 38, count 0 2006.173.21:35:54.66#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.21:35:54.66#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.21:35:54.66#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.21:35:54.66#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.21:35:54.66$setupk4/ifdk4 2006.173.21:35:54.66$ifdk4/lo= 2006.173.21:35:54.66$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.21:35:54.66$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.21:35:54.66$ifdk4/patch= 2006.173.21:35:54.66$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.21:35:54.66$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.21:35:54.66$setupk4/!*+20s 2006.173.21:35:54.92#abcon#<5=/12 0.5 0.9 21.221001003.2\r\n> 2006.173.21:35:54.94#abcon#{5=INTERFACE CLEAR} 2006.173.21:35:55.00#abcon#[5=S1D000X0/0*\r\n] 2006.173.21:36:01.13#trakl#Source acquired 2006.173.21:36:03.13#flagr#flagr/antenna,acquired 2006.173.21:36:05.09#abcon#<5=/12 0.5 1.0 21.221001003.2\r\n> 2006.173.21:36:05.11#abcon#{5=INTERFACE CLEAR} 2006.173.21:36:05.17#abcon#[5=S1D000X0/0*\r\n] 2006.173.21:36:09.17$setupk4/"tpicd 2006.173.21:36:09.17$setupk4/echo=off 2006.173.21:36:09.17$setupk4/xlog=off 2006.173.21:36:09.17:!2006.173.21:38:44 2006.173.21:38:44.00:preob 2006.173.21:38:44.14/onsource/TRACKING 2006.173.21:38:44.14:!2006.173.21:38:54 2006.173.21:38:54.00:"tape 2006.173.21:38:54.00:"st=record 2006.173.21:38:54.00:data_valid=on 2006.173.21:38:54.00:midob 2006.173.21:38:54.14/onsource/TRACKING 2006.173.21:38:54.14/wx/21.28,1003.2,100 2006.173.21:38:54.32/cable/+6.5145E-03 2006.173.21:38:55.41/va/01,07,usb,yes,34,37 2006.173.21:38:55.41/va/02,06,usb,yes,34,35 2006.173.21:38:55.41/va/03,05,usb,yes,43,45 2006.173.21:38:55.41/va/04,06,usb,yes,35,36 2006.173.21:38:55.41/va/05,04,usb,yes,27,27 2006.173.21:38:55.41/va/06,03,usb,yes,38,38 2006.173.21:38:55.41/va/07,04,usb,yes,31,32 2006.173.21:38:55.41/va/08,04,usb,yes,26,31 2006.173.21:38:55.64/valo/01,524.99,yes,locked 2006.173.21:38:55.64/valo/02,534.99,yes,locked 2006.173.21:38:55.64/valo/03,564.99,yes,locked 2006.173.21:38:55.64/valo/04,624.99,yes,locked 2006.173.21:38:55.64/valo/05,734.99,yes,locked 2006.173.21:38:55.64/valo/06,814.99,yes,locked 2006.173.21:38:55.64/valo/07,864.99,yes,locked 2006.173.21:38:55.64/valo/08,884.99,yes,locked 2006.173.21:38:56.73/vb/01,04,usb,yes,28,26 2006.173.21:38:56.73/vb/02,04,usb,yes,30,30 2006.173.21:38:56.73/vb/03,04,usb,yes,28,30 2006.173.21:38:56.73/vb/04,04,usb,yes,32,31 2006.173.21:38:56.73/vb/05,04,usb,yes,25,27 2006.173.21:38:56.73/vb/06,04,usb,yes,29,26 2006.173.21:38:56.73/vb/07,04,usb,yes,29,29 2006.173.21:38:56.73/vb/08,04,usb,yes,26,30 2006.173.21:38:56.96/vblo/01,629.99,yes,locked 2006.173.21:38:56.96/vblo/02,634.99,yes,locked 2006.173.21:38:56.96/vblo/03,649.99,yes,locked 2006.173.21:38:56.96/vblo/04,679.99,yes,locked 2006.173.21:38:56.96/vblo/05,709.99,yes,locked 2006.173.21:38:56.96/vblo/06,719.99,yes,locked 2006.173.21:38:56.96/vblo/07,734.99,yes,locked 2006.173.21:38:56.96/vblo/08,744.99,yes,locked 2006.173.21:38:57.11/vabw/8 2006.173.21:38:57.26/vbbw/8 2006.173.21:38:57.35/xfe/off,on,16.0 2006.173.21:38:57.73/ifatt/23,28,28,28 2006.173.21:38:58.08/fmout-gps/S +3.94E-07 2006.173.21:38:58.12:!2006.173.21:48:14 2006.173.21:48:14.01:data_valid=off 2006.173.21:48:14.02:"et 2006.173.21:48:14.02:!+3s 2006.173.21:48:17.04:"tape 2006.173.21:48:17.04:postob 2006.173.21:48:17.20/cable/+6.5156E-03 2006.173.21:48:17.21/wx/21.37,1003.3,99 2006.173.21:48:17.26/fmout-gps/S +3.92E-07 2006.173.21:48:17.27:scan_name=173-2152,jd0606,250 2006.173.21:48:17.27:source=1044+719,104827.62,714335.9,2000.0,cw 2006.173.21:48:18.15#flagr#flagr/antenna,new-source 2006.173.21:48:18.15:checkk5 2006.173.21:48:18.50/chk_autoobs//k5ts1/ autoobs is running! 2006.173.21:48:18.92/chk_autoobs//k5ts2/ autoobs is running! 2006.173.21:48:19.34/chk_autoobs//k5ts3/ autoobs is running! 2006.173.21:48:19.73/chk_autoobs//k5ts4/ autoobs is running! 2006.173.21:48:20.43/chk_obsdata//k5ts1/T1732138??a.dat file size is correct (nominal:2240MB, actual:2236MB). 2006.173.21:48:21.16/chk_obsdata//k5ts2/T1732138??b.dat file size is correct (nominal:2240MB, actual:2236MB). 2006.173.21:48:21.87/chk_obsdata//k5ts3/T1732138??c.dat file size is correct (nominal:2240MB, actual:2236MB). 2006.173.21:48:22.56/chk_obsdata//k5ts4/T1732138??d.dat file size is correct (nominal:2240MB, actual:2236MB). 2006.173.21:48:23.31/k5log//k5ts1_log_newline 2006.173.21:48:24.01/k5log//k5ts2_log_newline 2006.173.21:48:24.72/k5log//k5ts3_log_newline 2006.173.21:48:25.43/k5log//k5ts4_log_newline 2006.173.21:48:25.45/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.21:48:25.45:setupk4=1 2006.173.21:48:25.45$setupk4/echo=on 2006.173.21:48:25.45$setupk4/pcalon 2006.173.21:48:25.45$pcalon/"no phase cal control is implemented here 2006.173.21:48:25.45$setupk4/"tpicd=stop 2006.173.21:48:25.45$setupk4/"rec=synch_on 2006.173.21:48:25.45$setupk4/"rec_mode=128 2006.173.21:48:25.45$setupk4/!* 2006.173.21:48:25.45$setupk4/recpk4 2006.173.21:48:25.45$recpk4/recpatch= 2006.173.21:48:25.46$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.21:48:25.46$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.21:48:25.46$setupk4/vck44 2006.173.21:48:25.46$vck44/valo=1,524.99 2006.173.21:48:25.46#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.21:48:25.46#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.21:48:25.46#ibcon#ireg 17 cls_cnt 0 2006.173.21:48:25.46#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.21:48:25.46#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.21:48:25.46#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.21:48:25.46#ibcon#enter wrdev, iclass 15, count 0 2006.173.21:48:25.46#ibcon#first serial, iclass 15, count 0 2006.173.21:48:25.46#ibcon#enter sib2, iclass 15, count 0 2006.173.21:48:25.46#ibcon#flushed, iclass 15, count 0 2006.173.21:48:25.46#ibcon#about to write, iclass 15, count 0 2006.173.21:48:25.46#ibcon#wrote, iclass 15, count 0 2006.173.21:48:25.46#ibcon#about to read 3, iclass 15, count 0 2006.173.21:48:25.47#ibcon#read 3, iclass 15, count 0 2006.173.21:48:25.47#ibcon#about to read 4, iclass 15, count 0 2006.173.21:48:25.47#ibcon#read 4, iclass 15, count 0 2006.173.21:48:25.47#ibcon#about to read 5, iclass 15, count 0 2006.173.21:48:25.47#ibcon#read 5, iclass 15, count 0 2006.173.21:48:25.47#ibcon#about to read 6, iclass 15, count 0 2006.173.21:48:25.47#ibcon#read 6, iclass 15, count 0 2006.173.21:48:25.47#ibcon#end of sib2, iclass 15, count 0 2006.173.21:48:25.47#ibcon#*mode == 0, iclass 15, count 0 2006.173.21:48:25.47#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.21:48:25.47#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.21:48:25.47#ibcon#*before write, iclass 15, count 0 2006.173.21:48:25.47#ibcon#enter sib2, iclass 15, count 0 2006.173.21:48:25.47#ibcon#flushed, iclass 15, count 0 2006.173.21:48:25.47#ibcon#about to write, iclass 15, count 0 2006.173.21:48:25.47#ibcon#wrote, iclass 15, count 0 2006.173.21:48:25.47#ibcon#about to read 3, iclass 15, count 0 2006.173.21:48:25.52#ibcon#read 3, iclass 15, count 0 2006.173.21:48:25.52#ibcon#about to read 4, iclass 15, count 0 2006.173.21:48:25.52#ibcon#read 4, iclass 15, count 0 2006.173.21:48:25.52#ibcon#about to read 5, iclass 15, count 0 2006.173.21:48:25.52#ibcon#read 5, iclass 15, count 0 2006.173.21:48:25.52#ibcon#about to read 6, iclass 15, count 0 2006.173.21:48:25.52#ibcon#read 6, iclass 15, count 0 2006.173.21:48:25.52#ibcon#end of sib2, iclass 15, count 0 2006.173.21:48:25.52#ibcon#*after write, iclass 15, count 0 2006.173.21:48:25.52#ibcon#*before return 0, iclass 15, count 0 2006.173.21:48:25.52#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.21:48:25.52#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.21:48:25.52#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.21:48:25.52#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.21:48:25.52$vck44/va=1,7 2006.173.21:48:25.52#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.21:48:25.52#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.21:48:25.52#ibcon#ireg 11 cls_cnt 2 2006.173.21:48:25.52#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.21:48:25.52#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.21:48:25.52#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.21:48:25.52#ibcon#enter wrdev, iclass 17, count 2 2006.173.21:48:25.52#ibcon#first serial, iclass 17, count 2 2006.173.21:48:25.52#ibcon#enter sib2, iclass 17, count 2 2006.173.21:48:25.52#ibcon#flushed, iclass 17, count 2 2006.173.21:48:25.53#ibcon#about to write, iclass 17, count 2 2006.173.21:48:25.53#ibcon#wrote, iclass 17, count 2 2006.173.21:48:25.53#ibcon#about to read 3, iclass 17, count 2 2006.173.21:48:25.54#ibcon#read 3, iclass 17, count 2 2006.173.21:48:25.54#ibcon#about to read 4, iclass 17, count 2 2006.173.21:48:25.54#ibcon#read 4, iclass 17, count 2 2006.173.21:48:25.54#ibcon#about to read 5, iclass 17, count 2 2006.173.21:48:25.54#ibcon#read 5, iclass 17, count 2 2006.173.21:48:25.54#ibcon#about to read 6, iclass 17, count 2 2006.173.21:48:25.54#ibcon#read 6, iclass 17, count 2 2006.173.21:48:25.54#ibcon#end of sib2, iclass 17, count 2 2006.173.21:48:25.54#ibcon#*mode == 0, iclass 17, count 2 2006.173.21:48:25.54#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.21:48:25.54#ibcon#[25=AT01-07\r\n] 2006.173.21:48:25.54#ibcon#*before write, iclass 17, count 2 2006.173.21:48:25.54#ibcon#enter sib2, iclass 17, count 2 2006.173.21:48:25.54#ibcon#flushed, iclass 17, count 2 2006.173.21:48:25.54#ibcon#about to write, iclass 17, count 2 2006.173.21:48:25.54#ibcon#wrote, iclass 17, count 2 2006.173.21:48:25.54#ibcon#about to read 3, iclass 17, count 2 2006.173.21:48:25.57#ibcon#read 3, iclass 17, count 2 2006.173.21:48:25.57#ibcon#about to read 4, iclass 17, count 2 2006.173.21:48:25.57#ibcon#read 4, iclass 17, count 2 2006.173.21:48:25.57#ibcon#about to read 5, iclass 17, count 2 2006.173.21:48:25.57#ibcon#read 5, iclass 17, count 2 2006.173.21:48:25.57#ibcon#about to read 6, iclass 17, count 2 2006.173.21:48:25.57#ibcon#read 6, iclass 17, count 2 2006.173.21:48:25.57#ibcon#end of sib2, iclass 17, count 2 2006.173.21:48:25.57#ibcon#*after write, iclass 17, count 2 2006.173.21:48:25.57#ibcon#*before return 0, iclass 17, count 2 2006.173.21:48:25.57#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.21:48:25.57#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.21:48:25.57#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.21:48:25.57#ibcon#ireg 7 cls_cnt 0 2006.173.21:48:25.57#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.21:48:25.69#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.21:48:25.69#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.21:48:25.69#ibcon#enter wrdev, iclass 17, count 0 2006.173.21:48:25.69#ibcon#first serial, iclass 17, count 0 2006.173.21:48:25.69#ibcon#enter sib2, iclass 17, count 0 2006.173.21:48:25.69#ibcon#flushed, iclass 17, count 0 2006.173.21:48:25.69#ibcon#about to write, iclass 17, count 0 2006.173.21:48:25.69#ibcon#wrote, iclass 17, count 0 2006.173.21:48:25.69#ibcon#about to read 3, iclass 17, count 0 2006.173.21:48:25.71#ibcon#read 3, iclass 17, count 0 2006.173.21:48:25.71#ibcon#about to read 4, iclass 17, count 0 2006.173.21:48:25.71#ibcon#read 4, iclass 17, count 0 2006.173.21:48:25.71#ibcon#about to read 5, iclass 17, count 0 2006.173.21:48:25.71#ibcon#read 5, iclass 17, count 0 2006.173.21:48:25.71#ibcon#about to read 6, iclass 17, count 0 2006.173.21:48:25.71#ibcon#read 6, iclass 17, count 0 2006.173.21:48:25.71#ibcon#end of sib2, iclass 17, count 0 2006.173.21:48:25.71#ibcon#*mode == 0, iclass 17, count 0 2006.173.21:48:25.71#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.21:48:25.71#ibcon#[25=USB\r\n] 2006.173.21:48:25.71#ibcon#*before write, iclass 17, count 0 2006.173.21:48:25.71#ibcon#enter sib2, iclass 17, count 0 2006.173.21:48:25.71#ibcon#flushed, iclass 17, count 0 2006.173.21:48:25.71#ibcon#about to write, iclass 17, count 0 2006.173.21:48:25.71#ibcon#wrote, iclass 17, count 0 2006.173.21:48:25.71#ibcon#about to read 3, iclass 17, count 0 2006.173.21:48:25.74#ibcon#read 3, iclass 17, count 0 2006.173.21:48:25.74#ibcon#about to read 4, iclass 17, count 0 2006.173.21:48:25.74#ibcon#read 4, iclass 17, count 0 2006.173.21:48:25.74#ibcon#about to read 5, iclass 17, count 0 2006.173.21:48:25.74#ibcon#read 5, iclass 17, count 0 2006.173.21:48:25.74#ibcon#about to read 6, iclass 17, count 0 2006.173.21:48:25.74#ibcon#read 6, iclass 17, count 0 2006.173.21:48:25.74#ibcon#end of sib2, iclass 17, count 0 2006.173.21:48:25.74#ibcon#*after write, iclass 17, count 0 2006.173.21:48:25.74#ibcon#*before return 0, iclass 17, count 0 2006.173.21:48:25.74#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.21:48:25.74#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.21:48:25.74#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.21:48:25.74#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.21:48:25.74$vck44/valo=2,534.99 2006.173.21:48:25.74#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.21:48:25.74#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.21:48:25.74#ibcon#ireg 17 cls_cnt 0 2006.173.21:48:25.74#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.21:48:25.75#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.21:48:25.75#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.21:48:25.75#ibcon#enter wrdev, iclass 19, count 0 2006.173.21:48:25.75#ibcon#first serial, iclass 19, count 0 2006.173.21:48:25.75#ibcon#enter sib2, iclass 19, count 0 2006.173.21:48:25.75#ibcon#flushed, iclass 19, count 0 2006.173.21:48:25.75#ibcon#about to write, iclass 19, count 0 2006.173.21:48:25.75#ibcon#wrote, iclass 19, count 0 2006.173.21:48:25.75#ibcon#about to read 3, iclass 19, count 0 2006.173.21:48:25.76#ibcon#read 3, iclass 19, count 0 2006.173.21:48:25.76#ibcon#about to read 4, iclass 19, count 0 2006.173.21:48:25.76#ibcon#read 4, iclass 19, count 0 2006.173.21:48:25.76#ibcon#about to read 5, iclass 19, count 0 2006.173.21:48:25.76#ibcon#read 5, iclass 19, count 0 2006.173.21:48:25.76#ibcon#about to read 6, iclass 19, count 0 2006.173.21:48:25.76#ibcon#read 6, iclass 19, count 0 2006.173.21:48:25.76#ibcon#end of sib2, iclass 19, count 0 2006.173.21:48:25.76#ibcon#*mode == 0, iclass 19, count 0 2006.173.21:48:25.76#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.21:48:25.76#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.21:48:25.76#ibcon#*before write, iclass 19, count 0 2006.173.21:48:25.76#ibcon#enter sib2, iclass 19, count 0 2006.173.21:48:25.76#ibcon#flushed, iclass 19, count 0 2006.173.21:48:25.76#ibcon#about to write, iclass 19, count 0 2006.173.21:48:25.76#ibcon#wrote, iclass 19, count 0 2006.173.21:48:25.76#ibcon#about to read 3, iclass 19, count 0 2006.173.21:48:25.80#ibcon#read 3, iclass 19, count 0 2006.173.21:48:25.80#ibcon#about to read 4, iclass 19, count 0 2006.173.21:48:25.80#ibcon#read 4, iclass 19, count 0 2006.173.21:48:25.80#ibcon#about to read 5, iclass 19, count 0 2006.173.21:48:25.80#ibcon#read 5, iclass 19, count 0 2006.173.21:48:25.80#ibcon#about to read 6, iclass 19, count 0 2006.173.21:48:25.80#ibcon#read 6, iclass 19, count 0 2006.173.21:48:25.80#ibcon#end of sib2, iclass 19, count 0 2006.173.21:48:25.80#ibcon#*after write, iclass 19, count 0 2006.173.21:48:25.80#ibcon#*before return 0, iclass 19, count 0 2006.173.21:48:25.80#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.21:48:25.80#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.21:48:25.80#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.21:48:25.80#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.21:48:25.80$vck44/va=2,6 2006.173.21:48:25.80#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.21:48:25.80#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.21:48:25.80#ibcon#ireg 11 cls_cnt 2 2006.173.21:48:25.80#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.21:48:25.86#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.21:48:25.86#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.21:48:25.86#ibcon#enter wrdev, iclass 21, count 2 2006.173.21:48:25.86#ibcon#first serial, iclass 21, count 2 2006.173.21:48:25.86#ibcon#enter sib2, iclass 21, count 2 2006.173.21:48:25.86#ibcon#flushed, iclass 21, count 2 2006.173.21:48:25.86#ibcon#about to write, iclass 21, count 2 2006.173.21:48:25.86#ibcon#wrote, iclass 21, count 2 2006.173.21:48:25.86#ibcon#about to read 3, iclass 21, count 2 2006.173.21:48:25.88#ibcon#read 3, iclass 21, count 2 2006.173.21:48:25.88#ibcon#about to read 4, iclass 21, count 2 2006.173.21:48:25.88#ibcon#read 4, iclass 21, count 2 2006.173.21:48:25.88#ibcon#about to read 5, iclass 21, count 2 2006.173.21:48:25.88#ibcon#read 5, iclass 21, count 2 2006.173.21:48:25.88#ibcon#about to read 6, iclass 21, count 2 2006.173.21:48:25.88#ibcon#read 6, iclass 21, count 2 2006.173.21:48:25.88#ibcon#end of sib2, iclass 21, count 2 2006.173.21:48:25.88#ibcon#*mode == 0, iclass 21, count 2 2006.173.21:48:25.88#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.21:48:25.88#ibcon#[25=AT02-06\r\n] 2006.173.21:48:25.88#ibcon#*before write, iclass 21, count 2 2006.173.21:48:25.88#ibcon#enter sib2, iclass 21, count 2 2006.173.21:48:25.88#ibcon#flushed, iclass 21, count 2 2006.173.21:48:25.88#ibcon#about to write, iclass 21, count 2 2006.173.21:48:25.88#ibcon#wrote, iclass 21, count 2 2006.173.21:48:25.88#ibcon#about to read 3, iclass 21, count 2 2006.173.21:48:25.91#ibcon#read 3, iclass 21, count 2 2006.173.21:48:25.91#ibcon#about to read 4, iclass 21, count 2 2006.173.21:48:25.91#ibcon#read 4, iclass 21, count 2 2006.173.21:48:25.91#ibcon#about to read 5, iclass 21, count 2 2006.173.21:48:25.91#ibcon#read 5, iclass 21, count 2 2006.173.21:48:25.91#ibcon#about to read 6, iclass 21, count 2 2006.173.21:48:25.91#ibcon#read 6, iclass 21, count 2 2006.173.21:48:25.91#ibcon#end of sib2, iclass 21, count 2 2006.173.21:48:25.91#ibcon#*after write, iclass 21, count 2 2006.173.21:48:25.91#ibcon#*before return 0, iclass 21, count 2 2006.173.21:48:25.91#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.21:48:25.91#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.21:48:25.91#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.21:48:25.91#ibcon#ireg 7 cls_cnt 0 2006.173.21:48:25.91#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.21:48:26.03#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.21:48:26.03#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.21:48:26.03#ibcon#enter wrdev, iclass 21, count 0 2006.173.21:48:26.03#ibcon#first serial, iclass 21, count 0 2006.173.21:48:26.03#ibcon#enter sib2, iclass 21, count 0 2006.173.21:48:26.03#ibcon#flushed, iclass 21, count 0 2006.173.21:48:26.03#ibcon#about to write, iclass 21, count 0 2006.173.21:48:26.03#ibcon#wrote, iclass 21, count 0 2006.173.21:48:26.03#ibcon#about to read 3, iclass 21, count 0 2006.173.21:48:26.05#ibcon#read 3, iclass 21, count 0 2006.173.21:48:26.05#ibcon#about to read 4, iclass 21, count 0 2006.173.21:48:26.05#ibcon#read 4, iclass 21, count 0 2006.173.21:48:26.05#ibcon#about to read 5, iclass 21, count 0 2006.173.21:48:26.05#ibcon#read 5, iclass 21, count 0 2006.173.21:48:26.05#ibcon#about to read 6, iclass 21, count 0 2006.173.21:48:26.05#ibcon#read 6, iclass 21, count 0 2006.173.21:48:26.05#ibcon#end of sib2, iclass 21, count 0 2006.173.21:48:26.05#ibcon#*mode == 0, iclass 21, count 0 2006.173.21:48:26.05#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.21:48:26.05#ibcon#[25=USB\r\n] 2006.173.21:48:26.05#ibcon#*before write, iclass 21, count 0 2006.173.21:48:26.05#ibcon#enter sib2, iclass 21, count 0 2006.173.21:48:26.05#ibcon#flushed, iclass 21, count 0 2006.173.21:48:26.05#ibcon#about to write, iclass 21, count 0 2006.173.21:48:26.05#ibcon#wrote, iclass 21, count 0 2006.173.21:48:26.05#ibcon#about to read 3, iclass 21, count 0 2006.173.21:48:26.08#ibcon#read 3, iclass 21, count 0 2006.173.21:48:26.08#ibcon#about to read 4, iclass 21, count 0 2006.173.21:48:26.08#ibcon#read 4, iclass 21, count 0 2006.173.21:48:26.08#ibcon#about to read 5, iclass 21, count 0 2006.173.21:48:26.08#ibcon#read 5, iclass 21, count 0 2006.173.21:48:26.08#ibcon#about to read 6, iclass 21, count 0 2006.173.21:48:26.08#ibcon#read 6, iclass 21, count 0 2006.173.21:48:26.08#ibcon#end of sib2, iclass 21, count 0 2006.173.21:48:26.08#ibcon#*after write, iclass 21, count 0 2006.173.21:48:26.08#ibcon#*before return 0, iclass 21, count 0 2006.173.21:48:26.08#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.21:48:26.08#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.21:48:26.08#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.21:48:26.08#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.21:48:26.08$vck44/valo=3,564.99 2006.173.21:48:26.08#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.21:48:26.08#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.21:48:26.08#ibcon#ireg 17 cls_cnt 0 2006.173.21:48:26.08#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.21:48:26.08#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.21:48:26.08#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.21:48:26.08#ibcon#enter wrdev, iclass 23, count 0 2006.173.21:48:26.08#ibcon#first serial, iclass 23, count 0 2006.173.21:48:26.08#ibcon#enter sib2, iclass 23, count 0 2006.173.21:48:26.09#ibcon#flushed, iclass 23, count 0 2006.173.21:48:26.09#ibcon#about to write, iclass 23, count 0 2006.173.21:48:26.09#ibcon#wrote, iclass 23, count 0 2006.173.21:48:26.09#ibcon#about to read 3, iclass 23, count 0 2006.173.21:48:26.10#ibcon#read 3, iclass 23, count 0 2006.173.21:48:26.10#ibcon#about to read 4, iclass 23, count 0 2006.173.21:48:26.10#ibcon#read 4, iclass 23, count 0 2006.173.21:48:26.10#ibcon#about to read 5, iclass 23, count 0 2006.173.21:48:26.10#ibcon#read 5, iclass 23, count 0 2006.173.21:48:26.10#ibcon#about to read 6, iclass 23, count 0 2006.173.21:48:26.10#ibcon#read 6, iclass 23, count 0 2006.173.21:48:26.10#ibcon#end of sib2, iclass 23, count 0 2006.173.21:48:26.10#ibcon#*mode == 0, iclass 23, count 0 2006.173.21:48:26.10#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.21:48:26.10#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.21:48:26.10#ibcon#*before write, iclass 23, count 0 2006.173.21:48:26.10#ibcon#enter sib2, iclass 23, count 0 2006.173.21:48:26.10#ibcon#flushed, iclass 23, count 0 2006.173.21:48:26.10#ibcon#about to write, iclass 23, count 0 2006.173.21:48:26.10#ibcon#wrote, iclass 23, count 0 2006.173.21:48:26.10#ibcon#about to read 3, iclass 23, count 0 2006.173.21:48:26.14#ibcon#read 3, iclass 23, count 0 2006.173.21:48:26.14#ibcon#about to read 4, iclass 23, count 0 2006.173.21:48:26.14#ibcon#read 4, iclass 23, count 0 2006.173.21:48:26.14#ibcon#about to read 5, iclass 23, count 0 2006.173.21:48:26.14#ibcon#read 5, iclass 23, count 0 2006.173.21:48:26.15#ibcon#about to read 6, iclass 23, count 0 2006.173.21:48:26.15#ibcon#read 6, iclass 23, count 0 2006.173.21:48:26.15#ibcon#end of sib2, iclass 23, count 0 2006.173.21:48:26.15#ibcon#*after write, iclass 23, count 0 2006.173.21:48:26.15#ibcon#*before return 0, iclass 23, count 0 2006.173.21:48:26.15#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.21:48:26.15#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.21:48:26.15#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.21:48:26.15#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.21:48:26.15$vck44/va=3,5 2006.173.21:48:26.15#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.21:48:26.15#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.21:48:26.15#ibcon#ireg 11 cls_cnt 2 2006.173.21:48:26.15#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.21:48:26.19#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.21:48:26.19#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.21:48:26.19#ibcon#enter wrdev, iclass 25, count 2 2006.173.21:48:26.19#ibcon#first serial, iclass 25, count 2 2006.173.21:48:26.19#ibcon#enter sib2, iclass 25, count 2 2006.173.21:48:26.19#ibcon#flushed, iclass 25, count 2 2006.173.21:48:26.19#ibcon#about to write, iclass 25, count 2 2006.173.21:48:26.19#ibcon#wrote, iclass 25, count 2 2006.173.21:48:26.19#ibcon#about to read 3, iclass 25, count 2 2006.173.21:48:26.21#ibcon#read 3, iclass 25, count 2 2006.173.21:48:26.21#ibcon#about to read 4, iclass 25, count 2 2006.173.21:48:26.21#ibcon#read 4, iclass 25, count 2 2006.173.21:48:26.21#ibcon#about to read 5, iclass 25, count 2 2006.173.21:48:26.21#ibcon#read 5, iclass 25, count 2 2006.173.21:48:26.21#ibcon#about to read 6, iclass 25, count 2 2006.173.21:48:26.21#ibcon#read 6, iclass 25, count 2 2006.173.21:48:26.21#ibcon#end of sib2, iclass 25, count 2 2006.173.21:48:26.21#ibcon#*mode == 0, iclass 25, count 2 2006.173.21:48:26.21#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.21:48:26.21#ibcon#[25=AT03-05\r\n] 2006.173.21:48:26.21#ibcon#*before write, iclass 25, count 2 2006.173.21:48:26.21#ibcon#enter sib2, iclass 25, count 2 2006.173.21:48:26.21#ibcon#flushed, iclass 25, count 2 2006.173.21:48:26.21#ibcon#about to write, iclass 25, count 2 2006.173.21:48:26.21#ibcon#wrote, iclass 25, count 2 2006.173.21:48:26.21#ibcon#about to read 3, iclass 25, count 2 2006.173.21:48:26.24#ibcon#read 3, iclass 25, count 2 2006.173.21:48:26.24#ibcon#about to read 4, iclass 25, count 2 2006.173.21:48:26.24#ibcon#read 4, iclass 25, count 2 2006.173.21:48:26.24#ibcon#about to read 5, iclass 25, count 2 2006.173.21:48:26.24#ibcon#read 5, iclass 25, count 2 2006.173.21:48:26.24#ibcon#about to read 6, iclass 25, count 2 2006.173.21:48:26.24#ibcon#read 6, iclass 25, count 2 2006.173.21:48:26.24#ibcon#end of sib2, iclass 25, count 2 2006.173.21:48:26.24#ibcon#*after write, iclass 25, count 2 2006.173.21:48:26.24#ibcon#*before return 0, iclass 25, count 2 2006.173.21:48:26.24#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.21:48:26.24#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.21:48:26.24#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.21:48:26.24#ibcon#ireg 7 cls_cnt 0 2006.173.21:48:26.24#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.21:48:26.36#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.21:48:26.36#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.21:48:26.36#ibcon#enter wrdev, iclass 25, count 0 2006.173.21:48:26.36#ibcon#first serial, iclass 25, count 0 2006.173.21:48:26.36#ibcon#enter sib2, iclass 25, count 0 2006.173.21:48:26.36#ibcon#flushed, iclass 25, count 0 2006.173.21:48:26.36#ibcon#about to write, iclass 25, count 0 2006.173.21:48:26.36#ibcon#wrote, iclass 25, count 0 2006.173.21:48:26.36#ibcon#about to read 3, iclass 25, count 0 2006.173.21:48:26.38#ibcon#read 3, iclass 25, count 0 2006.173.21:48:26.38#ibcon#about to read 4, iclass 25, count 0 2006.173.21:48:26.38#ibcon#read 4, iclass 25, count 0 2006.173.21:48:26.38#ibcon#about to read 5, iclass 25, count 0 2006.173.21:48:26.38#ibcon#read 5, iclass 25, count 0 2006.173.21:48:26.38#ibcon#about to read 6, iclass 25, count 0 2006.173.21:48:26.38#ibcon#read 6, iclass 25, count 0 2006.173.21:48:26.38#ibcon#end of sib2, iclass 25, count 0 2006.173.21:48:26.38#ibcon#*mode == 0, iclass 25, count 0 2006.173.21:48:26.38#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.21:48:26.38#ibcon#[25=USB\r\n] 2006.173.21:48:26.38#ibcon#*before write, iclass 25, count 0 2006.173.21:48:26.38#ibcon#enter sib2, iclass 25, count 0 2006.173.21:48:26.38#ibcon#flushed, iclass 25, count 0 2006.173.21:48:26.38#ibcon#about to write, iclass 25, count 0 2006.173.21:48:26.38#ibcon#wrote, iclass 25, count 0 2006.173.21:48:26.38#ibcon#about to read 3, iclass 25, count 0 2006.173.21:48:26.41#ibcon#read 3, iclass 25, count 0 2006.173.21:48:26.41#ibcon#about to read 4, iclass 25, count 0 2006.173.21:48:26.41#ibcon#read 4, iclass 25, count 0 2006.173.21:48:26.41#ibcon#about to read 5, iclass 25, count 0 2006.173.21:48:26.41#ibcon#read 5, iclass 25, count 0 2006.173.21:48:26.41#ibcon#about to read 6, iclass 25, count 0 2006.173.21:48:26.41#ibcon#read 6, iclass 25, count 0 2006.173.21:48:26.41#ibcon#end of sib2, iclass 25, count 0 2006.173.21:48:26.41#ibcon#*after write, iclass 25, count 0 2006.173.21:48:26.41#ibcon#*before return 0, iclass 25, count 0 2006.173.21:48:26.41#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.21:48:26.41#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.21:48:26.41#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.21:48:26.41#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.21:48:26.41$vck44/valo=4,624.99 2006.173.21:48:26.41#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.21:48:26.41#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.21:48:26.41#ibcon#ireg 17 cls_cnt 0 2006.173.21:48:26.42#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.21:48:26.42#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.21:48:26.42#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.21:48:26.42#ibcon#enter wrdev, iclass 27, count 0 2006.173.21:48:26.42#ibcon#first serial, iclass 27, count 0 2006.173.21:48:26.42#ibcon#enter sib2, iclass 27, count 0 2006.173.21:48:26.42#ibcon#flushed, iclass 27, count 0 2006.173.21:48:26.42#ibcon#about to write, iclass 27, count 0 2006.173.21:48:26.42#ibcon#wrote, iclass 27, count 0 2006.173.21:48:26.42#ibcon#about to read 3, iclass 27, count 0 2006.173.21:48:26.43#ibcon#read 3, iclass 27, count 0 2006.173.21:48:26.43#ibcon#about to read 4, iclass 27, count 0 2006.173.21:48:26.43#ibcon#read 4, iclass 27, count 0 2006.173.21:48:26.43#ibcon#about to read 5, iclass 27, count 0 2006.173.21:48:26.43#ibcon#read 5, iclass 27, count 0 2006.173.21:48:26.43#ibcon#about to read 6, iclass 27, count 0 2006.173.21:48:26.43#ibcon#read 6, iclass 27, count 0 2006.173.21:48:26.43#ibcon#end of sib2, iclass 27, count 0 2006.173.21:48:26.43#ibcon#*mode == 0, iclass 27, count 0 2006.173.21:48:26.43#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.21:48:26.43#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.21:48:26.43#ibcon#*before write, iclass 27, count 0 2006.173.21:48:26.43#ibcon#enter sib2, iclass 27, count 0 2006.173.21:48:26.43#ibcon#flushed, iclass 27, count 0 2006.173.21:48:26.43#ibcon#about to write, iclass 27, count 0 2006.173.21:48:26.43#ibcon#wrote, iclass 27, count 0 2006.173.21:48:26.43#ibcon#about to read 3, iclass 27, count 0 2006.173.21:48:26.47#ibcon#read 3, iclass 27, count 0 2006.173.21:48:26.47#ibcon#about to read 4, iclass 27, count 0 2006.173.21:48:26.47#ibcon#read 4, iclass 27, count 0 2006.173.21:48:26.47#ibcon#about to read 5, iclass 27, count 0 2006.173.21:48:26.47#ibcon#read 5, iclass 27, count 0 2006.173.21:48:26.47#ibcon#about to read 6, iclass 27, count 0 2006.173.21:48:26.47#ibcon#read 6, iclass 27, count 0 2006.173.21:48:26.47#ibcon#end of sib2, iclass 27, count 0 2006.173.21:48:26.47#ibcon#*after write, iclass 27, count 0 2006.173.21:48:26.47#ibcon#*before return 0, iclass 27, count 0 2006.173.21:48:26.47#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.21:48:26.47#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.21:48:26.47#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.21:48:26.47#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.21:48:26.47$vck44/va=4,6 2006.173.21:48:26.47#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.21:48:26.47#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.21:48:26.47#ibcon#ireg 11 cls_cnt 2 2006.173.21:48:26.47#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.21:48:26.53#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.21:48:26.53#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.21:48:26.53#ibcon#enter wrdev, iclass 29, count 2 2006.173.21:48:26.53#ibcon#first serial, iclass 29, count 2 2006.173.21:48:26.53#ibcon#enter sib2, iclass 29, count 2 2006.173.21:48:26.53#ibcon#flushed, iclass 29, count 2 2006.173.21:48:26.53#ibcon#about to write, iclass 29, count 2 2006.173.21:48:26.53#ibcon#wrote, iclass 29, count 2 2006.173.21:48:26.53#ibcon#about to read 3, iclass 29, count 2 2006.173.21:48:26.55#ibcon#read 3, iclass 29, count 2 2006.173.21:48:26.55#ibcon#about to read 4, iclass 29, count 2 2006.173.21:48:26.55#ibcon#read 4, iclass 29, count 2 2006.173.21:48:26.55#ibcon#about to read 5, iclass 29, count 2 2006.173.21:48:26.55#ibcon#read 5, iclass 29, count 2 2006.173.21:48:26.55#ibcon#about to read 6, iclass 29, count 2 2006.173.21:48:26.55#ibcon#read 6, iclass 29, count 2 2006.173.21:48:26.55#ibcon#end of sib2, iclass 29, count 2 2006.173.21:48:26.55#ibcon#*mode == 0, iclass 29, count 2 2006.173.21:48:26.55#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.21:48:26.55#ibcon#[25=AT04-06\r\n] 2006.173.21:48:26.55#ibcon#*before write, iclass 29, count 2 2006.173.21:48:26.55#ibcon#enter sib2, iclass 29, count 2 2006.173.21:48:26.55#ibcon#flushed, iclass 29, count 2 2006.173.21:48:26.55#ibcon#about to write, iclass 29, count 2 2006.173.21:48:26.55#ibcon#wrote, iclass 29, count 2 2006.173.21:48:26.55#ibcon#about to read 3, iclass 29, count 2 2006.173.21:48:26.58#ibcon#read 3, iclass 29, count 2 2006.173.21:48:26.58#ibcon#about to read 4, iclass 29, count 2 2006.173.21:48:26.58#ibcon#read 4, iclass 29, count 2 2006.173.21:48:26.58#ibcon#about to read 5, iclass 29, count 2 2006.173.21:48:26.58#ibcon#read 5, iclass 29, count 2 2006.173.21:48:26.58#ibcon#about to read 6, iclass 29, count 2 2006.173.21:48:26.58#ibcon#read 6, iclass 29, count 2 2006.173.21:48:26.58#ibcon#end of sib2, iclass 29, count 2 2006.173.21:48:26.58#ibcon#*after write, iclass 29, count 2 2006.173.21:48:26.58#ibcon#*before return 0, iclass 29, count 2 2006.173.21:48:26.58#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.21:48:26.58#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.21:48:26.58#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.21:48:26.58#ibcon#ireg 7 cls_cnt 0 2006.173.21:48:26.58#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.21:48:26.70#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.21:48:26.70#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.21:48:26.70#ibcon#enter wrdev, iclass 29, count 0 2006.173.21:48:26.70#ibcon#first serial, iclass 29, count 0 2006.173.21:48:26.70#ibcon#enter sib2, iclass 29, count 0 2006.173.21:48:26.70#ibcon#flushed, iclass 29, count 0 2006.173.21:48:26.70#ibcon#about to write, iclass 29, count 0 2006.173.21:48:26.70#ibcon#wrote, iclass 29, count 0 2006.173.21:48:26.70#ibcon#about to read 3, iclass 29, count 0 2006.173.21:48:26.72#ibcon#read 3, iclass 29, count 0 2006.173.21:48:26.72#ibcon#about to read 4, iclass 29, count 0 2006.173.21:48:26.72#ibcon#read 4, iclass 29, count 0 2006.173.21:48:26.72#ibcon#about to read 5, iclass 29, count 0 2006.173.21:48:26.72#ibcon#read 5, iclass 29, count 0 2006.173.21:48:26.72#ibcon#about to read 6, iclass 29, count 0 2006.173.21:48:26.72#ibcon#read 6, iclass 29, count 0 2006.173.21:48:26.72#ibcon#end of sib2, iclass 29, count 0 2006.173.21:48:26.72#ibcon#*mode == 0, iclass 29, count 0 2006.173.21:48:26.72#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.21:48:26.72#ibcon#[25=USB\r\n] 2006.173.21:48:26.72#ibcon#*before write, iclass 29, count 0 2006.173.21:48:26.72#ibcon#enter sib2, iclass 29, count 0 2006.173.21:48:26.72#ibcon#flushed, iclass 29, count 0 2006.173.21:48:26.72#ibcon#about to write, iclass 29, count 0 2006.173.21:48:26.72#ibcon#wrote, iclass 29, count 0 2006.173.21:48:26.72#ibcon#about to read 3, iclass 29, count 0 2006.173.21:48:26.75#ibcon#read 3, iclass 29, count 0 2006.173.21:48:26.75#ibcon#about to read 4, iclass 29, count 0 2006.173.21:48:26.75#ibcon#read 4, iclass 29, count 0 2006.173.21:48:26.75#ibcon#about to read 5, iclass 29, count 0 2006.173.21:48:26.75#ibcon#read 5, iclass 29, count 0 2006.173.21:48:26.75#ibcon#about to read 6, iclass 29, count 0 2006.173.21:48:26.75#ibcon#read 6, iclass 29, count 0 2006.173.21:48:26.75#ibcon#end of sib2, iclass 29, count 0 2006.173.21:48:26.75#ibcon#*after write, iclass 29, count 0 2006.173.21:48:26.75#ibcon#*before return 0, iclass 29, count 0 2006.173.21:48:26.75#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.21:48:26.75#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.21:48:26.75#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.21:48:26.75#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.21:48:26.75$vck44/valo=5,734.99 2006.173.21:48:26.75#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.21:48:26.75#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.21:48:26.75#ibcon#ireg 17 cls_cnt 0 2006.173.21:48:26.75#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.21:48:26.76#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.21:48:26.76#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.21:48:26.76#ibcon#enter wrdev, iclass 31, count 0 2006.173.21:48:26.76#ibcon#first serial, iclass 31, count 0 2006.173.21:48:26.76#ibcon#enter sib2, iclass 31, count 0 2006.173.21:48:26.76#ibcon#flushed, iclass 31, count 0 2006.173.21:48:26.76#ibcon#about to write, iclass 31, count 0 2006.173.21:48:26.76#ibcon#wrote, iclass 31, count 0 2006.173.21:48:26.76#ibcon#about to read 3, iclass 31, count 0 2006.173.21:48:26.77#ibcon#read 3, iclass 31, count 0 2006.173.21:48:26.77#ibcon#about to read 4, iclass 31, count 0 2006.173.21:48:26.77#ibcon#read 4, iclass 31, count 0 2006.173.21:48:26.77#ibcon#about to read 5, iclass 31, count 0 2006.173.21:48:26.77#ibcon#read 5, iclass 31, count 0 2006.173.21:48:26.77#ibcon#about to read 6, iclass 31, count 0 2006.173.21:48:26.77#ibcon#read 6, iclass 31, count 0 2006.173.21:48:26.77#ibcon#end of sib2, iclass 31, count 0 2006.173.21:48:26.77#ibcon#*mode == 0, iclass 31, count 0 2006.173.21:48:26.77#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.21:48:26.77#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.21:48:26.77#ibcon#*before write, iclass 31, count 0 2006.173.21:48:26.77#ibcon#enter sib2, iclass 31, count 0 2006.173.21:48:26.77#ibcon#flushed, iclass 31, count 0 2006.173.21:48:26.77#ibcon#about to write, iclass 31, count 0 2006.173.21:48:26.77#ibcon#wrote, iclass 31, count 0 2006.173.21:48:26.77#ibcon#about to read 3, iclass 31, count 0 2006.173.21:48:26.81#ibcon#read 3, iclass 31, count 0 2006.173.21:48:26.81#ibcon#about to read 4, iclass 31, count 0 2006.173.21:48:26.81#ibcon#read 4, iclass 31, count 0 2006.173.21:48:26.81#ibcon#about to read 5, iclass 31, count 0 2006.173.21:48:26.81#ibcon#read 5, iclass 31, count 0 2006.173.21:48:26.81#ibcon#about to read 6, iclass 31, count 0 2006.173.21:48:26.81#ibcon#read 6, iclass 31, count 0 2006.173.21:48:26.81#ibcon#end of sib2, iclass 31, count 0 2006.173.21:48:26.81#ibcon#*after write, iclass 31, count 0 2006.173.21:48:26.81#ibcon#*before return 0, iclass 31, count 0 2006.173.21:48:26.81#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.21:48:26.81#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.21:48:26.81#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.21:48:26.81#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.21:48:26.81$vck44/va=5,4 2006.173.21:48:26.81#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.173.21:48:26.81#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.173.21:48:26.81#ibcon#ireg 11 cls_cnt 2 2006.173.21:48:26.81#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.21:48:26.87#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.21:48:26.87#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.21:48:26.87#ibcon#enter wrdev, iclass 33, count 2 2006.173.21:48:26.87#ibcon#first serial, iclass 33, count 2 2006.173.21:48:26.87#ibcon#enter sib2, iclass 33, count 2 2006.173.21:48:26.87#ibcon#flushed, iclass 33, count 2 2006.173.21:48:26.87#ibcon#about to write, iclass 33, count 2 2006.173.21:48:26.87#ibcon#wrote, iclass 33, count 2 2006.173.21:48:26.87#ibcon#about to read 3, iclass 33, count 2 2006.173.21:48:26.89#ibcon#read 3, iclass 33, count 2 2006.173.21:48:26.89#ibcon#about to read 4, iclass 33, count 2 2006.173.21:48:26.89#ibcon#read 4, iclass 33, count 2 2006.173.21:48:26.89#ibcon#about to read 5, iclass 33, count 2 2006.173.21:48:26.89#ibcon#read 5, iclass 33, count 2 2006.173.21:48:26.89#ibcon#about to read 6, iclass 33, count 2 2006.173.21:48:26.89#ibcon#read 6, iclass 33, count 2 2006.173.21:48:26.89#ibcon#end of sib2, iclass 33, count 2 2006.173.21:48:26.89#ibcon#*mode == 0, iclass 33, count 2 2006.173.21:48:26.89#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.173.21:48:26.89#ibcon#[25=AT05-04\r\n] 2006.173.21:48:26.89#ibcon#*before write, iclass 33, count 2 2006.173.21:48:26.89#ibcon#enter sib2, iclass 33, count 2 2006.173.21:48:26.89#ibcon#flushed, iclass 33, count 2 2006.173.21:48:26.89#ibcon#about to write, iclass 33, count 2 2006.173.21:48:26.89#ibcon#wrote, iclass 33, count 2 2006.173.21:48:26.89#ibcon#about to read 3, iclass 33, count 2 2006.173.21:48:26.92#ibcon#read 3, iclass 33, count 2 2006.173.21:48:26.92#ibcon#about to read 4, iclass 33, count 2 2006.173.21:48:26.92#ibcon#read 4, iclass 33, count 2 2006.173.21:48:26.92#ibcon#about to read 5, iclass 33, count 2 2006.173.21:48:26.92#ibcon#read 5, iclass 33, count 2 2006.173.21:48:26.92#ibcon#about to read 6, iclass 33, count 2 2006.173.21:48:26.92#ibcon#read 6, iclass 33, count 2 2006.173.21:48:26.92#ibcon#end of sib2, iclass 33, count 2 2006.173.21:48:26.92#ibcon#*after write, iclass 33, count 2 2006.173.21:48:26.92#ibcon#*before return 0, iclass 33, count 2 2006.173.21:48:26.92#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.21:48:26.92#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.173.21:48:26.92#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.173.21:48:26.92#ibcon#ireg 7 cls_cnt 0 2006.173.21:48:26.92#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.21:48:27.04#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.21:48:27.04#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.21:48:27.04#ibcon#enter wrdev, iclass 33, count 0 2006.173.21:48:27.04#ibcon#first serial, iclass 33, count 0 2006.173.21:48:27.04#ibcon#enter sib2, iclass 33, count 0 2006.173.21:48:27.04#ibcon#flushed, iclass 33, count 0 2006.173.21:48:27.04#ibcon#about to write, iclass 33, count 0 2006.173.21:48:27.04#ibcon#wrote, iclass 33, count 0 2006.173.21:48:27.04#ibcon#about to read 3, iclass 33, count 0 2006.173.21:48:27.06#ibcon#read 3, iclass 33, count 0 2006.173.21:48:27.06#ibcon#about to read 4, iclass 33, count 0 2006.173.21:48:27.06#ibcon#read 4, iclass 33, count 0 2006.173.21:48:27.06#ibcon#about to read 5, iclass 33, count 0 2006.173.21:48:27.06#ibcon#read 5, iclass 33, count 0 2006.173.21:48:27.06#ibcon#about to read 6, iclass 33, count 0 2006.173.21:48:27.06#ibcon#read 6, iclass 33, count 0 2006.173.21:48:27.06#ibcon#end of sib2, iclass 33, count 0 2006.173.21:48:27.06#ibcon#*mode == 0, iclass 33, count 0 2006.173.21:48:27.06#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.21:48:27.06#ibcon#[25=USB\r\n] 2006.173.21:48:27.06#ibcon#*before write, iclass 33, count 0 2006.173.21:48:27.06#ibcon#enter sib2, iclass 33, count 0 2006.173.21:48:27.06#ibcon#flushed, iclass 33, count 0 2006.173.21:48:27.06#ibcon#about to write, iclass 33, count 0 2006.173.21:48:27.06#ibcon#wrote, iclass 33, count 0 2006.173.21:48:27.06#ibcon#about to read 3, iclass 33, count 0 2006.173.21:48:27.09#ibcon#read 3, iclass 33, count 0 2006.173.21:48:27.09#ibcon#about to read 4, iclass 33, count 0 2006.173.21:48:27.09#ibcon#read 4, iclass 33, count 0 2006.173.21:48:27.09#ibcon#about to read 5, iclass 33, count 0 2006.173.21:48:27.09#ibcon#read 5, iclass 33, count 0 2006.173.21:48:27.09#ibcon#about to read 6, iclass 33, count 0 2006.173.21:48:27.09#ibcon#read 6, iclass 33, count 0 2006.173.21:48:27.09#ibcon#end of sib2, iclass 33, count 0 2006.173.21:48:27.09#ibcon#*after write, iclass 33, count 0 2006.173.21:48:27.09#ibcon#*before return 0, iclass 33, count 0 2006.173.21:48:27.09#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.21:48:27.09#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.173.21:48:27.09#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.21:48:27.09#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.21:48:27.09$vck44/valo=6,814.99 2006.173.21:48:27.09#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.21:48:27.09#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.21:48:27.09#ibcon#ireg 17 cls_cnt 0 2006.173.21:48:27.09#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.21:48:27.09#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.21:48:27.09#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.21:48:27.09#ibcon#enter wrdev, iclass 35, count 0 2006.173.21:48:27.09#ibcon#first serial, iclass 35, count 0 2006.173.21:48:27.10#ibcon#enter sib2, iclass 35, count 0 2006.173.21:48:27.10#ibcon#flushed, iclass 35, count 0 2006.173.21:48:27.10#ibcon#about to write, iclass 35, count 0 2006.173.21:48:27.10#ibcon#wrote, iclass 35, count 0 2006.173.21:48:27.10#ibcon#about to read 3, iclass 35, count 0 2006.173.21:48:27.11#ibcon#read 3, iclass 35, count 0 2006.173.21:48:27.11#ibcon#about to read 4, iclass 35, count 0 2006.173.21:48:27.11#ibcon#read 4, iclass 35, count 0 2006.173.21:48:27.11#ibcon#about to read 5, iclass 35, count 0 2006.173.21:48:27.11#ibcon#read 5, iclass 35, count 0 2006.173.21:48:27.11#ibcon#about to read 6, iclass 35, count 0 2006.173.21:48:27.11#ibcon#read 6, iclass 35, count 0 2006.173.21:48:27.11#ibcon#end of sib2, iclass 35, count 0 2006.173.21:48:27.11#ibcon#*mode == 0, iclass 35, count 0 2006.173.21:48:27.11#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.21:48:27.11#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.21:48:27.11#ibcon#*before write, iclass 35, count 0 2006.173.21:48:27.11#ibcon#enter sib2, iclass 35, count 0 2006.173.21:48:27.11#ibcon#flushed, iclass 35, count 0 2006.173.21:48:27.11#ibcon#about to write, iclass 35, count 0 2006.173.21:48:27.11#ibcon#wrote, iclass 35, count 0 2006.173.21:48:27.11#ibcon#about to read 3, iclass 35, count 0 2006.173.21:48:27.15#ibcon#read 3, iclass 35, count 0 2006.173.21:48:27.15#ibcon#about to read 4, iclass 35, count 0 2006.173.21:48:27.15#ibcon#read 4, iclass 35, count 0 2006.173.21:48:27.15#ibcon#about to read 5, iclass 35, count 0 2006.173.21:48:27.15#ibcon#read 5, iclass 35, count 0 2006.173.21:48:27.15#ibcon#about to read 6, iclass 35, count 0 2006.173.21:48:27.15#ibcon#read 6, iclass 35, count 0 2006.173.21:48:27.15#ibcon#end of sib2, iclass 35, count 0 2006.173.21:48:27.15#ibcon#*after write, iclass 35, count 0 2006.173.21:48:27.15#ibcon#*before return 0, iclass 35, count 0 2006.173.21:48:27.15#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.21:48:27.15#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.21:48:27.15#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.21:48:27.15#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.21:48:27.15$vck44/va=6,3 2006.173.21:48:27.15#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.173.21:48:27.15#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.173.21:48:27.15#ibcon#ireg 11 cls_cnt 2 2006.173.21:48:27.15#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.21:48:27.21#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.21:48:27.21#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.21:48:27.21#ibcon#enter wrdev, iclass 37, count 2 2006.173.21:48:27.21#ibcon#first serial, iclass 37, count 2 2006.173.21:48:27.21#ibcon#enter sib2, iclass 37, count 2 2006.173.21:48:27.21#ibcon#flushed, iclass 37, count 2 2006.173.21:48:27.21#ibcon#about to write, iclass 37, count 2 2006.173.21:48:27.21#ibcon#wrote, iclass 37, count 2 2006.173.21:48:27.21#ibcon#about to read 3, iclass 37, count 2 2006.173.21:48:27.23#ibcon#read 3, iclass 37, count 2 2006.173.21:48:27.23#ibcon#about to read 4, iclass 37, count 2 2006.173.21:48:27.23#ibcon#read 4, iclass 37, count 2 2006.173.21:48:27.23#ibcon#about to read 5, iclass 37, count 2 2006.173.21:48:27.23#ibcon#read 5, iclass 37, count 2 2006.173.21:48:27.23#ibcon#about to read 6, iclass 37, count 2 2006.173.21:48:27.23#ibcon#read 6, iclass 37, count 2 2006.173.21:48:27.23#ibcon#end of sib2, iclass 37, count 2 2006.173.21:48:27.23#ibcon#*mode == 0, iclass 37, count 2 2006.173.21:48:27.23#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.173.21:48:27.23#ibcon#[25=AT06-03\r\n] 2006.173.21:48:27.23#ibcon#*before write, iclass 37, count 2 2006.173.21:48:27.23#ibcon#enter sib2, iclass 37, count 2 2006.173.21:48:27.23#ibcon#flushed, iclass 37, count 2 2006.173.21:48:27.23#ibcon#about to write, iclass 37, count 2 2006.173.21:48:27.23#ibcon#wrote, iclass 37, count 2 2006.173.21:48:27.23#ibcon#about to read 3, iclass 37, count 2 2006.173.21:48:27.26#ibcon#read 3, iclass 37, count 2 2006.173.21:48:27.26#ibcon#about to read 4, iclass 37, count 2 2006.173.21:48:27.26#ibcon#read 4, iclass 37, count 2 2006.173.21:48:27.26#ibcon#about to read 5, iclass 37, count 2 2006.173.21:48:27.26#ibcon#read 5, iclass 37, count 2 2006.173.21:48:27.26#ibcon#about to read 6, iclass 37, count 2 2006.173.21:48:27.26#ibcon#read 6, iclass 37, count 2 2006.173.21:48:27.26#ibcon#end of sib2, iclass 37, count 2 2006.173.21:48:27.26#ibcon#*after write, iclass 37, count 2 2006.173.21:48:27.26#ibcon#*before return 0, iclass 37, count 2 2006.173.21:48:27.26#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.21:48:27.26#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.173.21:48:27.26#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.173.21:48:27.26#ibcon#ireg 7 cls_cnt 0 2006.173.21:48:27.26#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.21:48:27.38#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.21:48:27.38#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.21:48:27.38#ibcon#enter wrdev, iclass 37, count 0 2006.173.21:48:27.38#ibcon#first serial, iclass 37, count 0 2006.173.21:48:27.38#ibcon#enter sib2, iclass 37, count 0 2006.173.21:48:27.38#ibcon#flushed, iclass 37, count 0 2006.173.21:48:27.38#ibcon#about to write, iclass 37, count 0 2006.173.21:48:27.38#ibcon#wrote, iclass 37, count 0 2006.173.21:48:27.38#ibcon#about to read 3, iclass 37, count 0 2006.173.21:48:27.40#ibcon#read 3, iclass 37, count 0 2006.173.21:48:27.40#ibcon#about to read 4, iclass 37, count 0 2006.173.21:48:27.40#ibcon#read 4, iclass 37, count 0 2006.173.21:48:27.40#ibcon#about to read 5, iclass 37, count 0 2006.173.21:48:27.40#ibcon#read 5, iclass 37, count 0 2006.173.21:48:27.40#ibcon#about to read 6, iclass 37, count 0 2006.173.21:48:27.40#ibcon#read 6, iclass 37, count 0 2006.173.21:48:27.40#ibcon#end of sib2, iclass 37, count 0 2006.173.21:48:27.40#ibcon#*mode == 0, iclass 37, count 0 2006.173.21:48:27.40#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.21:48:27.40#ibcon#[25=USB\r\n] 2006.173.21:48:27.40#ibcon#*before write, iclass 37, count 0 2006.173.21:48:27.40#ibcon#enter sib2, iclass 37, count 0 2006.173.21:48:27.40#ibcon#flushed, iclass 37, count 0 2006.173.21:48:27.40#ibcon#about to write, iclass 37, count 0 2006.173.21:48:27.40#ibcon#wrote, iclass 37, count 0 2006.173.21:48:27.40#ibcon#about to read 3, iclass 37, count 0 2006.173.21:48:27.43#ibcon#read 3, iclass 37, count 0 2006.173.21:48:27.43#ibcon#about to read 4, iclass 37, count 0 2006.173.21:48:27.43#ibcon#read 4, iclass 37, count 0 2006.173.21:48:27.43#ibcon#about to read 5, iclass 37, count 0 2006.173.21:48:27.43#ibcon#read 5, iclass 37, count 0 2006.173.21:48:27.43#ibcon#about to read 6, iclass 37, count 0 2006.173.21:48:27.43#ibcon#read 6, iclass 37, count 0 2006.173.21:48:27.43#ibcon#end of sib2, iclass 37, count 0 2006.173.21:48:27.43#ibcon#*after write, iclass 37, count 0 2006.173.21:48:27.43#ibcon#*before return 0, iclass 37, count 0 2006.173.21:48:27.43#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.21:48:27.43#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.173.21:48:27.43#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.21:48:27.43#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.21:48:27.43$vck44/valo=7,864.99 2006.173.21:48:27.43#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.21:48:27.43#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.21:48:27.43#ibcon#ireg 17 cls_cnt 0 2006.173.21:48:27.43#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.21:48:27.43#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.21:48:27.43#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.21:48:27.43#ibcon#enter wrdev, iclass 39, count 0 2006.173.21:48:27.43#ibcon#first serial, iclass 39, count 0 2006.173.21:48:27.43#ibcon#enter sib2, iclass 39, count 0 2006.173.21:48:27.43#ibcon#flushed, iclass 39, count 0 2006.173.21:48:27.44#ibcon#about to write, iclass 39, count 0 2006.173.21:48:27.44#ibcon#wrote, iclass 39, count 0 2006.173.21:48:27.44#ibcon#about to read 3, iclass 39, count 0 2006.173.21:48:27.45#ibcon#read 3, iclass 39, count 0 2006.173.21:48:27.45#ibcon#about to read 4, iclass 39, count 0 2006.173.21:48:27.45#ibcon#read 4, iclass 39, count 0 2006.173.21:48:27.45#ibcon#about to read 5, iclass 39, count 0 2006.173.21:48:27.45#ibcon#read 5, iclass 39, count 0 2006.173.21:48:27.45#ibcon#about to read 6, iclass 39, count 0 2006.173.21:48:27.45#ibcon#read 6, iclass 39, count 0 2006.173.21:48:27.45#ibcon#end of sib2, iclass 39, count 0 2006.173.21:48:27.45#ibcon#*mode == 0, iclass 39, count 0 2006.173.21:48:27.45#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.21:48:27.45#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.21:48:27.45#ibcon#*before write, iclass 39, count 0 2006.173.21:48:27.45#ibcon#enter sib2, iclass 39, count 0 2006.173.21:48:27.45#ibcon#flushed, iclass 39, count 0 2006.173.21:48:27.45#ibcon#about to write, iclass 39, count 0 2006.173.21:48:27.45#ibcon#wrote, iclass 39, count 0 2006.173.21:48:27.45#ibcon#about to read 3, iclass 39, count 0 2006.173.21:48:27.49#ibcon#read 3, iclass 39, count 0 2006.173.21:48:27.49#ibcon#about to read 4, iclass 39, count 0 2006.173.21:48:27.49#ibcon#read 4, iclass 39, count 0 2006.173.21:48:27.49#ibcon#about to read 5, iclass 39, count 0 2006.173.21:48:27.49#ibcon#read 5, iclass 39, count 0 2006.173.21:48:27.49#ibcon#about to read 6, iclass 39, count 0 2006.173.21:48:27.49#ibcon#read 6, iclass 39, count 0 2006.173.21:48:27.49#ibcon#end of sib2, iclass 39, count 0 2006.173.21:48:27.49#ibcon#*after write, iclass 39, count 0 2006.173.21:48:27.49#ibcon#*before return 0, iclass 39, count 0 2006.173.21:48:27.49#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.21:48:27.49#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.21:48:27.49#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.21:48:27.49#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.21:48:27.49$vck44/va=7,4 2006.173.21:48:27.49#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.21:48:27.49#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.21:48:27.49#ibcon#ireg 11 cls_cnt 2 2006.173.21:48:27.49#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.21:48:27.55#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.21:48:27.55#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.21:48:27.55#ibcon#enter wrdev, iclass 3, count 2 2006.173.21:48:27.55#ibcon#first serial, iclass 3, count 2 2006.173.21:48:27.55#ibcon#enter sib2, iclass 3, count 2 2006.173.21:48:27.55#ibcon#flushed, iclass 3, count 2 2006.173.21:48:27.55#ibcon#about to write, iclass 3, count 2 2006.173.21:48:27.55#ibcon#wrote, iclass 3, count 2 2006.173.21:48:27.55#ibcon#about to read 3, iclass 3, count 2 2006.173.21:48:27.57#ibcon#read 3, iclass 3, count 2 2006.173.21:48:27.57#ibcon#about to read 4, iclass 3, count 2 2006.173.21:48:27.57#ibcon#read 4, iclass 3, count 2 2006.173.21:48:27.57#ibcon#about to read 5, iclass 3, count 2 2006.173.21:48:27.57#ibcon#read 5, iclass 3, count 2 2006.173.21:48:27.57#ibcon#about to read 6, iclass 3, count 2 2006.173.21:48:27.57#ibcon#read 6, iclass 3, count 2 2006.173.21:48:27.57#ibcon#end of sib2, iclass 3, count 2 2006.173.21:48:27.57#ibcon#*mode == 0, iclass 3, count 2 2006.173.21:48:27.57#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.21:48:27.57#ibcon#[25=AT07-04\r\n] 2006.173.21:48:27.57#ibcon#*before write, iclass 3, count 2 2006.173.21:48:27.57#ibcon#enter sib2, iclass 3, count 2 2006.173.21:48:27.57#ibcon#flushed, iclass 3, count 2 2006.173.21:48:27.57#ibcon#about to write, iclass 3, count 2 2006.173.21:48:27.57#ibcon#wrote, iclass 3, count 2 2006.173.21:48:27.57#ibcon#about to read 3, iclass 3, count 2 2006.173.21:48:27.58#abcon#<5=/00 0.1 0.6 21.38 991003.3\r\n> 2006.173.21:48:27.60#abcon#{5=INTERFACE CLEAR} 2006.173.21:48:27.60#ibcon#read 3, iclass 3, count 2 2006.173.21:48:27.60#ibcon#about to read 4, iclass 3, count 2 2006.173.21:48:27.60#ibcon#read 4, iclass 3, count 2 2006.173.21:48:27.60#ibcon#about to read 5, iclass 3, count 2 2006.173.21:48:27.60#ibcon#read 5, iclass 3, count 2 2006.173.21:48:27.60#ibcon#about to read 6, iclass 3, count 2 2006.173.21:48:27.60#ibcon#read 6, iclass 3, count 2 2006.173.21:48:27.60#ibcon#end of sib2, iclass 3, count 2 2006.173.21:48:27.60#ibcon#*after write, iclass 3, count 2 2006.173.21:48:27.60#ibcon#*before return 0, iclass 3, count 2 2006.173.21:48:27.60#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.21:48:27.60#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.21:48:27.60#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.21:48:27.60#ibcon#ireg 7 cls_cnt 0 2006.173.21:48:27.60#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.21:48:27.66#abcon#[5=S1D000X0/0*\r\n] 2006.173.21:48:27.72#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.21:48:27.72#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.21:48:27.72#ibcon#enter wrdev, iclass 3, count 0 2006.173.21:48:27.72#ibcon#first serial, iclass 3, count 0 2006.173.21:48:27.72#ibcon#enter sib2, iclass 3, count 0 2006.173.21:48:27.72#ibcon#flushed, iclass 3, count 0 2006.173.21:48:27.72#ibcon#about to write, iclass 3, count 0 2006.173.21:48:27.72#ibcon#wrote, iclass 3, count 0 2006.173.21:48:27.72#ibcon#about to read 3, iclass 3, count 0 2006.173.21:48:27.74#ibcon#read 3, iclass 3, count 0 2006.173.21:48:27.74#ibcon#about to read 4, iclass 3, count 0 2006.173.21:48:27.74#ibcon#read 4, iclass 3, count 0 2006.173.21:48:27.74#ibcon#about to read 5, iclass 3, count 0 2006.173.21:48:27.74#ibcon#read 5, iclass 3, count 0 2006.173.21:48:27.74#ibcon#about to read 6, iclass 3, count 0 2006.173.21:48:27.74#ibcon#read 6, iclass 3, count 0 2006.173.21:48:27.74#ibcon#end of sib2, iclass 3, count 0 2006.173.21:48:27.74#ibcon#*mode == 0, iclass 3, count 0 2006.173.21:48:27.74#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.21:48:27.74#ibcon#[25=USB\r\n] 2006.173.21:48:27.74#ibcon#*before write, iclass 3, count 0 2006.173.21:48:27.74#ibcon#enter sib2, iclass 3, count 0 2006.173.21:48:27.74#ibcon#flushed, iclass 3, count 0 2006.173.21:48:27.74#ibcon#about to write, iclass 3, count 0 2006.173.21:48:27.74#ibcon#wrote, iclass 3, count 0 2006.173.21:48:27.74#ibcon#about to read 3, iclass 3, count 0 2006.173.21:48:27.77#ibcon#read 3, iclass 3, count 0 2006.173.21:48:27.77#ibcon#about to read 4, iclass 3, count 0 2006.173.21:48:27.77#ibcon#read 4, iclass 3, count 0 2006.173.21:48:27.77#ibcon#about to read 5, iclass 3, count 0 2006.173.21:48:27.77#ibcon#read 5, iclass 3, count 0 2006.173.21:48:27.77#ibcon#about to read 6, iclass 3, count 0 2006.173.21:48:27.77#ibcon#read 6, iclass 3, count 0 2006.173.21:48:27.77#ibcon#end of sib2, iclass 3, count 0 2006.173.21:48:27.77#ibcon#*after write, iclass 3, count 0 2006.173.21:48:27.77#ibcon#*before return 0, iclass 3, count 0 2006.173.21:48:27.77#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.21:48:27.77#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.21:48:27.77#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.21:48:27.77#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.21:48:27.77$vck44/valo=8,884.99 2006.173.21:48:27.77#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.21:48:27.77#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.21:48:27.77#ibcon#ireg 17 cls_cnt 0 2006.173.21:48:27.77#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.21:48:27.77#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.21:48:27.77#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.21:48:27.77#ibcon#enter wrdev, iclass 11, count 0 2006.173.21:48:27.77#ibcon#first serial, iclass 11, count 0 2006.173.21:48:27.77#ibcon#enter sib2, iclass 11, count 0 2006.173.21:48:27.77#ibcon#flushed, iclass 11, count 0 2006.173.21:48:27.78#ibcon#about to write, iclass 11, count 0 2006.173.21:48:27.78#ibcon#wrote, iclass 11, count 0 2006.173.21:48:27.78#ibcon#about to read 3, iclass 11, count 0 2006.173.21:48:27.79#ibcon#read 3, iclass 11, count 0 2006.173.21:48:27.79#ibcon#about to read 4, iclass 11, count 0 2006.173.21:48:27.79#ibcon#read 4, iclass 11, count 0 2006.173.21:48:27.79#ibcon#about to read 5, iclass 11, count 0 2006.173.21:48:27.79#ibcon#read 5, iclass 11, count 0 2006.173.21:48:27.79#ibcon#about to read 6, iclass 11, count 0 2006.173.21:48:27.79#ibcon#read 6, iclass 11, count 0 2006.173.21:48:27.79#ibcon#end of sib2, iclass 11, count 0 2006.173.21:48:27.79#ibcon#*mode == 0, iclass 11, count 0 2006.173.21:48:27.79#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.21:48:27.79#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.21:48:27.79#ibcon#*before write, iclass 11, count 0 2006.173.21:48:27.79#ibcon#enter sib2, iclass 11, count 0 2006.173.21:48:27.79#ibcon#flushed, iclass 11, count 0 2006.173.21:48:27.79#ibcon#about to write, iclass 11, count 0 2006.173.21:48:27.79#ibcon#wrote, iclass 11, count 0 2006.173.21:48:27.79#ibcon#about to read 3, iclass 11, count 0 2006.173.21:48:27.83#ibcon#read 3, iclass 11, count 0 2006.173.21:48:27.83#ibcon#about to read 4, iclass 11, count 0 2006.173.21:48:27.83#ibcon#read 4, iclass 11, count 0 2006.173.21:48:27.83#ibcon#about to read 5, iclass 11, count 0 2006.173.21:48:27.83#ibcon#read 5, iclass 11, count 0 2006.173.21:48:27.83#ibcon#about to read 6, iclass 11, count 0 2006.173.21:48:27.83#ibcon#read 6, iclass 11, count 0 2006.173.21:48:27.83#ibcon#end of sib2, iclass 11, count 0 2006.173.21:48:27.83#ibcon#*after write, iclass 11, count 0 2006.173.21:48:27.83#ibcon#*before return 0, iclass 11, count 0 2006.173.21:48:27.83#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.21:48:27.83#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.21:48:27.83#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.21:48:27.83#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.21:48:27.83$vck44/va=8,4 2006.173.21:48:27.83#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.173.21:48:27.83#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.173.21:48:27.83#ibcon#ireg 11 cls_cnt 2 2006.173.21:48:27.83#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.21:48:27.89#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.21:48:27.89#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.21:48:27.89#ibcon#enter wrdev, iclass 13, count 2 2006.173.21:48:27.89#ibcon#first serial, iclass 13, count 2 2006.173.21:48:27.89#ibcon#enter sib2, iclass 13, count 2 2006.173.21:48:27.89#ibcon#flushed, iclass 13, count 2 2006.173.21:48:27.89#ibcon#about to write, iclass 13, count 2 2006.173.21:48:27.89#ibcon#wrote, iclass 13, count 2 2006.173.21:48:27.89#ibcon#about to read 3, iclass 13, count 2 2006.173.21:48:27.91#ibcon#read 3, iclass 13, count 2 2006.173.21:48:27.91#ibcon#about to read 4, iclass 13, count 2 2006.173.21:48:27.91#ibcon#read 4, iclass 13, count 2 2006.173.21:48:27.91#ibcon#about to read 5, iclass 13, count 2 2006.173.21:48:27.91#ibcon#read 5, iclass 13, count 2 2006.173.21:48:27.91#ibcon#about to read 6, iclass 13, count 2 2006.173.21:48:27.91#ibcon#read 6, iclass 13, count 2 2006.173.21:48:27.91#ibcon#end of sib2, iclass 13, count 2 2006.173.21:48:27.91#ibcon#*mode == 0, iclass 13, count 2 2006.173.21:48:27.91#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.173.21:48:27.91#ibcon#[25=AT08-04\r\n] 2006.173.21:48:27.91#ibcon#*before write, iclass 13, count 2 2006.173.21:48:27.91#ibcon#enter sib2, iclass 13, count 2 2006.173.21:48:27.91#ibcon#flushed, iclass 13, count 2 2006.173.21:48:27.91#ibcon#about to write, iclass 13, count 2 2006.173.21:48:27.91#ibcon#wrote, iclass 13, count 2 2006.173.21:48:27.91#ibcon#about to read 3, iclass 13, count 2 2006.173.21:48:27.94#ibcon#read 3, iclass 13, count 2 2006.173.21:48:27.94#ibcon#about to read 4, iclass 13, count 2 2006.173.21:48:27.94#ibcon#read 4, iclass 13, count 2 2006.173.21:48:27.94#ibcon#about to read 5, iclass 13, count 2 2006.173.21:48:27.94#ibcon#read 5, iclass 13, count 2 2006.173.21:48:27.94#ibcon#about to read 6, iclass 13, count 2 2006.173.21:48:27.94#ibcon#read 6, iclass 13, count 2 2006.173.21:48:27.94#ibcon#end of sib2, iclass 13, count 2 2006.173.21:48:27.94#ibcon#*after write, iclass 13, count 2 2006.173.21:48:27.94#ibcon#*before return 0, iclass 13, count 2 2006.173.21:48:27.94#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.21:48:27.94#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.173.21:48:27.94#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.173.21:48:27.94#ibcon#ireg 7 cls_cnt 0 2006.173.21:48:27.94#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.21:48:28.06#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.21:48:28.06#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.21:48:28.06#ibcon#enter wrdev, iclass 13, count 0 2006.173.21:48:28.06#ibcon#first serial, iclass 13, count 0 2006.173.21:48:28.06#ibcon#enter sib2, iclass 13, count 0 2006.173.21:48:28.06#ibcon#flushed, iclass 13, count 0 2006.173.21:48:28.06#ibcon#about to write, iclass 13, count 0 2006.173.21:48:28.06#ibcon#wrote, iclass 13, count 0 2006.173.21:48:28.06#ibcon#about to read 3, iclass 13, count 0 2006.173.21:48:28.08#ibcon#read 3, iclass 13, count 0 2006.173.21:48:28.08#ibcon#about to read 4, iclass 13, count 0 2006.173.21:48:28.08#ibcon#read 4, iclass 13, count 0 2006.173.21:48:28.08#ibcon#about to read 5, iclass 13, count 0 2006.173.21:48:28.08#ibcon#read 5, iclass 13, count 0 2006.173.21:48:28.08#ibcon#about to read 6, iclass 13, count 0 2006.173.21:48:28.08#ibcon#read 6, iclass 13, count 0 2006.173.21:48:28.08#ibcon#end of sib2, iclass 13, count 0 2006.173.21:48:28.08#ibcon#*mode == 0, iclass 13, count 0 2006.173.21:48:28.08#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.21:48:28.08#ibcon#[25=USB\r\n] 2006.173.21:48:28.08#ibcon#*before write, iclass 13, count 0 2006.173.21:48:28.08#ibcon#enter sib2, iclass 13, count 0 2006.173.21:48:28.08#ibcon#flushed, iclass 13, count 0 2006.173.21:48:28.08#ibcon#about to write, iclass 13, count 0 2006.173.21:48:28.08#ibcon#wrote, iclass 13, count 0 2006.173.21:48:28.08#ibcon#about to read 3, iclass 13, count 0 2006.173.21:48:28.11#ibcon#read 3, iclass 13, count 0 2006.173.21:48:28.11#ibcon#about to read 4, iclass 13, count 0 2006.173.21:48:28.11#ibcon#read 4, iclass 13, count 0 2006.173.21:48:28.11#ibcon#about to read 5, iclass 13, count 0 2006.173.21:48:28.11#ibcon#read 5, iclass 13, count 0 2006.173.21:48:28.11#ibcon#about to read 6, iclass 13, count 0 2006.173.21:48:28.11#ibcon#read 6, iclass 13, count 0 2006.173.21:48:28.11#ibcon#end of sib2, iclass 13, count 0 2006.173.21:48:28.11#ibcon#*after write, iclass 13, count 0 2006.173.21:48:28.11#ibcon#*before return 0, iclass 13, count 0 2006.173.21:48:28.11#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.21:48:28.11#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.173.21:48:28.11#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.21:48:28.11#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.21:48:28.11$vck44/vblo=1,629.99 2006.173.21:48:28.11#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.21:48:28.11#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.21:48:28.11#ibcon#ireg 17 cls_cnt 0 2006.173.21:48:28.11#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.21:48:28.11#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.21:48:28.11#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.21:48:28.11#ibcon#enter wrdev, iclass 15, count 0 2006.173.21:48:28.11#ibcon#first serial, iclass 15, count 0 2006.173.21:48:28.11#ibcon#enter sib2, iclass 15, count 0 2006.173.21:48:28.11#ibcon#flushed, iclass 15, count 0 2006.173.21:48:28.12#ibcon#about to write, iclass 15, count 0 2006.173.21:48:28.12#ibcon#wrote, iclass 15, count 0 2006.173.21:48:28.12#ibcon#about to read 3, iclass 15, count 0 2006.173.21:48:28.13#ibcon#read 3, iclass 15, count 0 2006.173.21:48:28.13#ibcon#about to read 4, iclass 15, count 0 2006.173.21:48:28.13#ibcon#read 4, iclass 15, count 0 2006.173.21:48:28.13#ibcon#about to read 5, iclass 15, count 0 2006.173.21:48:28.13#ibcon#read 5, iclass 15, count 0 2006.173.21:48:28.13#ibcon#about to read 6, iclass 15, count 0 2006.173.21:48:28.13#ibcon#read 6, iclass 15, count 0 2006.173.21:48:28.13#ibcon#end of sib2, iclass 15, count 0 2006.173.21:48:28.13#ibcon#*mode == 0, iclass 15, count 0 2006.173.21:48:28.13#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.21:48:28.13#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.21:48:28.13#ibcon#*before write, iclass 15, count 0 2006.173.21:48:28.13#ibcon#enter sib2, iclass 15, count 0 2006.173.21:48:28.13#ibcon#flushed, iclass 15, count 0 2006.173.21:48:28.13#ibcon#about to write, iclass 15, count 0 2006.173.21:48:28.13#ibcon#wrote, iclass 15, count 0 2006.173.21:48:28.13#ibcon#about to read 3, iclass 15, count 0 2006.173.21:48:28.17#ibcon#read 3, iclass 15, count 0 2006.173.21:48:28.17#ibcon#about to read 4, iclass 15, count 0 2006.173.21:48:28.17#ibcon#read 4, iclass 15, count 0 2006.173.21:48:28.17#ibcon#about to read 5, iclass 15, count 0 2006.173.21:48:28.17#ibcon#read 5, iclass 15, count 0 2006.173.21:48:28.17#ibcon#about to read 6, iclass 15, count 0 2006.173.21:48:28.17#ibcon#read 6, iclass 15, count 0 2006.173.21:48:28.17#ibcon#end of sib2, iclass 15, count 0 2006.173.21:48:28.17#ibcon#*after write, iclass 15, count 0 2006.173.21:48:28.17#ibcon#*before return 0, iclass 15, count 0 2006.173.21:48:28.17#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.21:48:28.17#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.21:48:28.17#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.21:48:28.17#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.21:48:28.17$vck44/vb=1,4 2006.173.21:48:28.17#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.21:48:28.17#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.21:48:28.17#ibcon#ireg 11 cls_cnt 2 2006.173.21:48:28.17#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.21:48:28.17#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.21:48:28.17#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.21:48:28.17#ibcon#enter wrdev, iclass 17, count 2 2006.173.21:48:28.17#ibcon#first serial, iclass 17, count 2 2006.173.21:48:28.17#ibcon#enter sib2, iclass 17, count 2 2006.173.21:48:28.17#ibcon#flushed, iclass 17, count 2 2006.173.21:48:28.17#ibcon#about to write, iclass 17, count 2 2006.173.21:48:28.18#ibcon#wrote, iclass 17, count 2 2006.173.21:48:28.18#ibcon#about to read 3, iclass 17, count 2 2006.173.21:48:28.19#ibcon#read 3, iclass 17, count 2 2006.173.21:48:28.19#ibcon#about to read 4, iclass 17, count 2 2006.173.21:48:28.19#ibcon#read 4, iclass 17, count 2 2006.173.21:48:28.19#ibcon#about to read 5, iclass 17, count 2 2006.173.21:48:28.19#ibcon#read 5, iclass 17, count 2 2006.173.21:48:28.19#ibcon#about to read 6, iclass 17, count 2 2006.173.21:48:28.19#ibcon#read 6, iclass 17, count 2 2006.173.21:48:28.19#ibcon#end of sib2, iclass 17, count 2 2006.173.21:48:28.19#ibcon#*mode == 0, iclass 17, count 2 2006.173.21:48:28.19#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.21:48:28.19#ibcon#[27=AT01-04\r\n] 2006.173.21:48:28.19#ibcon#*before write, iclass 17, count 2 2006.173.21:48:28.19#ibcon#enter sib2, iclass 17, count 2 2006.173.21:48:28.19#ibcon#flushed, iclass 17, count 2 2006.173.21:48:28.19#ibcon#about to write, iclass 17, count 2 2006.173.21:48:28.19#ibcon#wrote, iclass 17, count 2 2006.173.21:48:28.19#ibcon#about to read 3, iclass 17, count 2 2006.173.21:48:28.22#ibcon#read 3, iclass 17, count 2 2006.173.21:48:28.22#ibcon#about to read 4, iclass 17, count 2 2006.173.21:48:28.22#ibcon#read 4, iclass 17, count 2 2006.173.21:48:28.22#ibcon#about to read 5, iclass 17, count 2 2006.173.21:48:28.22#ibcon#read 5, iclass 17, count 2 2006.173.21:48:28.22#ibcon#about to read 6, iclass 17, count 2 2006.173.21:48:28.22#ibcon#read 6, iclass 17, count 2 2006.173.21:48:28.22#ibcon#end of sib2, iclass 17, count 2 2006.173.21:48:28.22#ibcon#*after write, iclass 17, count 2 2006.173.21:48:28.22#ibcon#*before return 0, iclass 17, count 2 2006.173.21:48:28.22#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.21:48:28.22#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.21:48:28.22#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.21:48:28.22#ibcon#ireg 7 cls_cnt 0 2006.173.21:48:28.22#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.21:48:28.34#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.21:48:28.34#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.21:48:28.34#ibcon#enter wrdev, iclass 17, count 0 2006.173.21:48:28.34#ibcon#first serial, iclass 17, count 0 2006.173.21:48:28.34#ibcon#enter sib2, iclass 17, count 0 2006.173.21:48:28.34#ibcon#flushed, iclass 17, count 0 2006.173.21:48:28.34#ibcon#about to write, iclass 17, count 0 2006.173.21:48:28.34#ibcon#wrote, iclass 17, count 0 2006.173.21:48:28.34#ibcon#about to read 3, iclass 17, count 0 2006.173.21:48:28.36#ibcon#read 3, iclass 17, count 0 2006.173.21:48:28.36#ibcon#about to read 4, iclass 17, count 0 2006.173.21:48:28.36#ibcon#read 4, iclass 17, count 0 2006.173.21:48:28.36#ibcon#about to read 5, iclass 17, count 0 2006.173.21:48:28.36#ibcon#read 5, iclass 17, count 0 2006.173.21:48:28.36#ibcon#about to read 6, iclass 17, count 0 2006.173.21:48:28.36#ibcon#read 6, iclass 17, count 0 2006.173.21:48:28.36#ibcon#end of sib2, iclass 17, count 0 2006.173.21:48:28.36#ibcon#*mode == 0, iclass 17, count 0 2006.173.21:48:28.36#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.21:48:28.36#ibcon#[27=USB\r\n] 2006.173.21:48:28.36#ibcon#*before write, iclass 17, count 0 2006.173.21:48:28.36#ibcon#enter sib2, iclass 17, count 0 2006.173.21:48:28.36#ibcon#flushed, iclass 17, count 0 2006.173.21:48:28.36#ibcon#about to write, iclass 17, count 0 2006.173.21:48:28.36#ibcon#wrote, iclass 17, count 0 2006.173.21:48:28.36#ibcon#about to read 3, iclass 17, count 0 2006.173.21:48:28.39#ibcon#read 3, iclass 17, count 0 2006.173.21:48:28.39#ibcon#about to read 4, iclass 17, count 0 2006.173.21:48:28.39#ibcon#read 4, iclass 17, count 0 2006.173.21:48:28.39#ibcon#about to read 5, iclass 17, count 0 2006.173.21:48:28.39#ibcon#read 5, iclass 17, count 0 2006.173.21:48:28.39#ibcon#about to read 6, iclass 17, count 0 2006.173.21:48:28.39#ibcon#read 6, iclass 17, count 0 2006.173.21:48:28.39#ibcon#end of sib2, iclass 17, count 0 2006.173.21:48:28.39#ibcon#*after write, iclass 17, count 0 2006.173.21:48:28.39#ibcon#*before return 0, iclass 17, count 0 2006.173.21:48:28.39#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.21:48:28.39#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.21:48:28.39#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.21:48:28.39#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.21:48:28.39$vck44/vblo=2,634.99 2006.173.21:48:28.39#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.21:48:28.39#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.21:48:28.39#ibcon#ireg 17 cls_cnt 0 2006.173.21:48:28.39#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.21:48:28.39#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.21:48:28.39#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.21:48:28.39#ibcon#enter wrdev, iclass 19, count 0 2006.173.21:48:28.39#ibcon#first serial, iclass 19, count 0 2006.173.21:48:28.39#ibcon#enter sib2, iclass 19, count 0 2006.173.21:48:28.39#ibcon#flushed, iclass 19, count 0 2006.173.21:48:28.39#ibcon#about to write, iclass 19, count 0 2006.173.21:48:28.40#ibcon#wrote, iclass 19, count 0 2006.173.21:48:28.40#ibcon#about to read 3, iclass 19, count 0 2006.173.21:48:28.41#ibcon#read 3, iclass 19, count 0 2006.173.21:48:28.41#ibcon#about to read 4, iclass 19, count 0 2006.173.21:48:28.41#ibcon#read 4, iclass 19, count 0 2006.173.21:48:28.41#ibcon#about to read 5, iclass 19, count 0 2006.173.21:48:28.41#ibcon#read 5, iclass 19, count 0 2006.173.21:48:28.41#ibcon#about to read 6, iclass 19, count 0 2006.173.21:48:28.41#ibcon#read 6, iclass 19, count 0 2006.173.21:48:28.41#ibcon#end of sib2, iclass 19, count 0 2006.173.21:48:28.41#ibcon#*mode == 0, iclass 19, count 0 2006.173.21:48:28.41#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.21:48:28.41#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.21:48:28.41#ibcon#*before write, iclass 19, count 0 2006.173.21:48:28.41#ibcon#enter sib2, iclass 19, count 0 2006.173.21:48:28.41#ibcon#flushed, iclass 19, count 0 2006.173.21:48:28.41#ibcon#about to write, iclass 19, count 0 2006.173.21:48:28.41#ibcon#wrote, iclass 19, count 0 2006.173.21:48:28.41#ibcon#about to read 3, iclass 19, count 0 2006.173.21:48:28.45#ibcon#read 3, iclass 19, count 0 2006.173.21:48:28.45#ibcon#about to read 4, iclass 19, count 0 2006.173.21:48:28.45#ibcon#read 4, iclass 19, count 0 2006.173.21:48:28.45#ibcon#about to read 5, iclass 19, count 0 2006.173.21:48:28.45#ibcon#read 5, iclass 19, count 0 2006.173.21:48:28.45#ibcon#about to read 6, iclass 19, count 0 2006.173.21:48:28.45#ibcon#read 6, iclass 19, count 0 2006.173.21:48:28.45#ibcon#end of sib2, iclass 19, count 0 2006.173.21:48:28.45#ibcon#*after write, iclass 19, count 0 2006.173.21:48:28.45#ibcon#*before return 0, iclass 19, count 0 2006.173.21:48:28.45#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.21:48:28.45#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.21:48:28.45#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.21:48:28.45#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.21:48:28.45$vck44/vb=2,4 2006.173.21:48:28.45#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.21:48:28.45#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.21:48:28.45#ibcon#ireg 11 cls_cnt 2 2006.173.21:48:28.45#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.21:48:28.51#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.21:48:28.51#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.21:48:28.51#ibcon#enter wrdev, iclass 21, count 2 2006.173.21:48:28.51#ibcon#first serial, iclass 21, count 2 2006.173.21:48:28.51#ibcon#enter sib2, iclass 21, count 2 2006.173.21:48:28.51#ibcon#flushed, iclass 21, count 2 2006.173.21:48:28.51#ibcon#about to write, iclass 21, count 2 2006.173.21:48:28.51#ibcon#wrote, iclass 21, count 2 2006.173.21:48:28.51#ibcon#about to read 3, iclass 21, count 2 2006.173.21:48:28.53#ibcon#read 3, iclass 21, count 2 2006.173.21:48:28.53#ibcon#about to read 4, iclass 21, count 2 2006.173.21:48:28.53#ibcon#read 4, iclass 21, count 2 2006.173.21:48:28.53#ibcon#about to read 5, iclass 21, count 2 2006.173.21:48:28.53#ibcon#read 5, iclass 21, count 2 2006.173.21:48:28.53#ibcon#about to read 6, iclass 21, count 2 2006.173.21:48:28.53#ibcon#read 6, iclass 21, count 2 2006.173.21:48:28.53#ibcon#end of sib2, iclass 21, count 2 2006.173.21:48:28.53#ibcon#*mode == 0, iclass 21, count 2 2006.173.21:48:28.53#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.21:48:28.53#ibcon#[27=AT02-04\r\n] 2006.173.21:48:28.53#ibcon#*before write, iclass 21, count 2 2006.173.21:48:28.53#ibcon#enter sib2, iclass 21, count 2 2006.173.21:48:28.53#ibcon#flushed, iclass 21, count 2 2006.173.21:48:28.53#ibcon#about to write, iclass 21, count 2 2006.173.21:48:28.53#ibcon#wrote, iclass 21, count 2 2006.173.21:48:28.53#ibcon#about to read 3, iclass 21, count 2 2006.173.21:48:28.56#ibcon#read 3, iclass 21, count 2 2006.173.21:48:28.56#ibcon#about to read 4, iclass 21, count 2 2006.173.21:48:28.56#ibcon#read 4, iclass 21, count 2 2006.173.21:48:28.56#ibcon#about to read 5, iclass 21, count 2 2006.173.21:48:28.56#ibcon#read 5, iclass 21, count 2 2006.173.21:48:28.56#ibcon#about to read 6, iclass 21, count 2 2006.173.21:48:28.56#ibcon#read 6, iclass 21, count 2 2006.173.21:48:28.56#ibcon#end of sib2, iclass 21, count 2 2006.173.21:48:28.56#ibcon#*after write, iclass 21, count 2 2006.173.21:48:28.56#ibcon#*before return 0, iclass 21, count 2 2006.173.21:48:28.56#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.21:48:28.56#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.21:48:28.56#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.21:48:28.56#ibcon#ireg 7 cls_cnt 0 2006.173.21:48:28.56#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.21:48:28.68#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.21:48:28.68#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.21:48:28.68#ibcon#enter wrdev, iclass 21, count 0 2006.173.21:48:28.68#ibcon#first serial, iclass 21, count 0 2006.173.21:48:28.68#ibcon#enter sib2, iclass 21, count 0 2006.173.21:48:28.68#ibcon#flushed, iclass 21, count 0 2006.173.21:48:28.68#ibcon#about to write, iclass 21, count 0 2006.173.21:48:28.68#ibcon#wrote, iclass 21, count 0 2006.173.21:48:28.68#ibcon#about to read 3, iclass 21, count 0 2006.173.21:48:28.70#ibcon#read 3, iclass 21, count 0 2006.173.21:48:28.70#ibcon#about to read 4, iclass 21, count 0 2006.173.21:48:28.70#ibcon#read 4, iclass 21, count 0 2006.173.21:48:28.70#ibcon#about to read 5, iclass 21, count 0 2006.173.21:48:28.70#ibcon#read 5, iclass 21, count 0 2006.173.21:48:28.70#ibcon#about to read 6, iclass 21, count 0 2006.173.21:48:28.70#ibcon#read 6, iclass 21, count 0 2006.173.21:48:28.70#ibcon#end of sib2, iclass 21, count 0 2006.173.21:48:28.70#ibcon#*mode == 0, iclass 21, count 0 2006.173.21:48:28.70#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.21:48:28.70#ibcon#[27=USB\r\n] 2006.173.21:48:28.70#ibcon#*before write, iclass 21, count 0 2006.173.21:48:28.70#ibcon#enter sib2, iclass 21, count 0 2006.173.21:48:28.70#ibcon#flushed, iclass 21, count 0 2006.173.21:48:28.70#ibcon#about to write, iclass 21, count 0 2006.173.21:48:28.70#ibcon#wrote, iclass 21, count 0 2006.173.21:48:28.70#ibcon#about to read 3, iclass 21, count 0 2006.173.21:48:28.73#ibcon#read 3, iclass 21, count 0 2006.173.21:48:28.73#ibcon#about to read 4, iclass 21, count 0 2006.173.21:48:28.73#ibcon#read 4, iclass 21, count 0 2006.173.21:48:28.73#ibcon#about to read 5, iclass 21, count 0 2006.173.21:48:28.73#ibcon#read 5, iclass 21, count 0 2006.173.21:48:28.73#ibcon#about to read 6, iclass 21, count 0 2006.173.21:48:28.73#ibcon#read 6, iclass 21, count 0 2006.173.21:48:28.73#ibcon#end of sib2, iclass 21, count 0 2006.173.21:48:28.73#ibcon#*after write, iclass 21, count 0 2006.173.21:48:28.73#ibcon#*before return 0, iclass 21, count 0 2006.173.21:48:28.73#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.21:48:28.73#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.21:48:28.73#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.21:48:28.73#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.21:48:28.73$vck44/vblo=3,649.99 2006.173.21:48:28.73#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.21:48:28.73#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.21:48:28.73#ibcon#ireg 17 cls_cnt 0 2006.173.21:48:28.73#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.21:48:28.73#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.21:48:28.73#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.21:48:28.73#ibcon#enter wrdev, iclass 23, count 0 2006.173.21:48:28.73#ibcon#first serial, iclass 23, count 0 2006.173.21:48:28.73#ibcon#enter sib2, iclass 23, count 0 2006.173.21:48:28.73#ibcon#flushed, iclass 23, count 0 2006.173.21:48:28.74#ibcon#about to write, iclass 23, count 0 2006.173.21:48:28.74#ibcon#wrote, iclass 23, count 0 2006.173.21:48:28.74#ibcon#about to read 3, iclass 23, count 0 2006.173.21:48:28.75#ibcon#read 3, iclass 23, count 0 2006.173.21:48:28.75#ibcon#about to read 4, iclass 23, count 0 2006.173.21:48:28.75#ibcon#read 4, iclass 23, count 0 2006.173.21:48:28.75#ibcon#about to read 5, iclass 23, count 0 2006.173.21:48:28.75#ibcon#read 5, iclass 23, count 0 2006.173.21:48:28.75#ibcon#about to read 6, iclass 23, count 0 2006.173.21:48:28.75#ibcon#read 6, iclass 23, count 0 2006.173.21:48:28.75#ibcon#end of sib2, iclass 23, count 0 2006.173.21:48:28.75#ibcon#*mode == 0, iclass 23, count 0 2006.173.21:48:28.75#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.21:48:28.75#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.21:48:28.75#ibcon#*before write, iclass 23, count 0 2006.173.21:48:28.75#ibcon#enter sib2, iclass 23, count 0 2006.173.21:48:28.75#ibcon#flushed, iclass 23, count 0 2006.173.21:48:28.75#ibcon#about to write, iclass 23, count 0 2006.173.21:48:28.75#ibcon#wrote, iclass 23, count 0 2006.173.21:48:28.75#ibcon#about to read 3, iclass 23, count 0 2006.173.21:48:28.79#ibcon#read 3, iclass 23, count 0 2006.173.21:48:28.79#ibcon#about to read 4, iclass 23, count 0 2006.173.21:48:28.79#ibcon#read 4, iclass 23, count 0 2006.173.21:48:28.79#ibcon#about to read 5, iclass 23, count 0 2006.173.21:48:28.79#ibcon#read 5, iclass 23, count 0 2006.173.21:48:28.79#ibcon#about to read 6, iclass 23, count 0 2006.173.21:48:28.79#ibcon#read 6, iclass 23, count 0 2006.173.21:48:28.79#ibcon#end of sib2, iclass 23, count 0 2006.173.21:48:28.79#ibcon#*after write, iclass 23, count 0 2006.173.21:48:28.79#ibcon#*before return 0, iclass 23, count 0 2006.173.21:48:28.79#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.21:48:28.79#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.21:48:28.79#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.21:48:28.79#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.21:48:28.79$vck44/vb=3,4 2006.173.21:48:28.79#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.21:48:28.79#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.21:48:28.79#ibcon#ireg 11 cls_cnt 2 2006.173.21:48:28.79#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.21:48:28.85#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.21:48:28.85#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.21:48:28.85#ibcon#enter wrdev, iclass 25, count 2 2006.173.21:48:28.85#ibcon#first serial, iclass 25, count 2 2006.173.21:48:28.85#ibcon#enter sib2, iclass 25, count 2 2006.173.21:48:28.85#ibcon#flushed, iclass 25, count 2 2006.173.21:48:28.85#ibcon#about to write, iclass 25, count 2 2006.173.21:48:28.85#ibcon#wrote, iclass 25, count 2 2006.173.21:48:28.85#ibcon#about to read 3, iclass 25, count 2 2006.173.21:48:28.87#ibcon#read 3, iclass 25, count 2 2006.173.21:48:28.87#ibcon#about to read 4, iclass 25, count 2 2006.173.21:48:28.87#ibcon#read 4, iclass 25, count 2 2006.173.21:48:28.87#ibcon#about to read 5, iclass 25, count 2 2006.173.21:48:28.87#ibcon#read 5, iclass 25, count 2 2006.173.21:48:28.87#ibcon#about to read 6, iclass 25, count 2 2006.173.21:48:28.87#ibcon#read 6, iclass 25, count 2 2006.173.21:48:28.87#ibcon#end of sib2, iclass 25, count 2 2006.173.21:48:28.87#ibcon#*mode == 0, iclass 25, count 2 2006.173.21:48:28.87#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.21:48:28.87#ibcon#[27=AT03-04\r\n] 2006.173.21:48:28.87#ibcon#*before write, iclass 25, count 2 2006.173.21:48:28.87#ibcon#enter sib2, iclass 25, count 2 2006.173.21:48:28.87#ibcon#flushed, iclass 25, count 2 2006.173.21:48:28.87#ibcon#about to write, iclass 25, count 2 2006.173.21:48:28.87#ibcon#wrote, iclass 25, count 2 2006.173.21:48:28.87#ibcon#about to read 3, iclass 25, count 2 2006.173.21:48:28.90#ibcon#read 3, iclass 25, count 2 2006.173.21:48:28.90#ibcon#about to read 4, iclass 25, count 2 2006.173.21:48:28.90#ibcon#read 4, iclass 25, count 2 2006.173.21:48:28.90#ibcon#about to read 5, iclass 25, count 2 2006.173.21:48:28.90#ibcon#read 5, iclass 25, count 2 2006.173.21:48:28.90#ibcon#about to read 6, iclass 25, count 2 2006.173.21:48:28.90#ibcon#read 6, iclass 25, count 2 2006.173.21:48:28.90#ibcon#end of sib2, iclass 25, count 2 2006.173.21:48:28.90#ibcon#*after write, iclass 25, count 2 2006.173.21:48:28.90#ibcon#*before return 0, iclass 25, count 2 2006.173.21:48:28.90#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.21:48:28.90#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.21:48:28.90#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.21:48:28.90#ibcon#ireg 7 cls_cnt 0 2006.173.21:48:28.90#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.21:48:29.02#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.21:48:29.02#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.21:48:29.02#ibcon#enter wrdev, iclass 25, count 0 2006.173.21:48:29.02#ibcon#first serial, iclass 25, count 0 2006.173.21:48:29.02#ibcon#enter sib2, iclass 25, count 0 2006.173.21:48:29.02#ibcon#flushed, iclass 25, count 0 2006.173.21:48:29.02#ibcon#about to write, iclass 25, count 0 2006.173.21:48:29.02#ibcon#wrote, iclass 25, count 0 2006.173.21:48:29.02#ibcon#about to read 3, iclass 25, count 0 2006.173.21:48:29.04#ibcon#read 3, iclass 25, count 0 2006.173.21:48:29.04#ibcon#about to read 4, iclass 25, count 0 2006.173.21:48:29.04#ibcon#read 4, iclass 25, count 0 2006.173.21:48:29.04#ibcon#about to read 5, iclass 25, count 0 2006.173.21:48:29.04#ibcon#read 5, iclass 25, count 0 2006.173.21:48:29.04#ibcon#about to read 6, iclass 25, count 0 2006.173.21:48:29.04#ibcon#read 6, iclass 25, count 0 2006.173.21:48:29.04#ibcon#end of sib2, iclass 25, count 0 2006.173.21:48:29.04#ibcon#*mode == 0, iclass 25, count 0 2006.173.21:48:29.04#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.21:48:29.04#ibcon#[27=USB\r\n] 2006.173.21:48:29.04#ibcon#*before write, iclass 25, count 0 2006.173.21:48:29.04#ibcon#enter sib2, iclass 25, count 0 2006.173.21:48:29.04#ibcon#flushed, iclass 25, count 0 2006.173.21:48:29.04#ibcon#about to write, iclass 25, count 0 2006.173.21:48:29.04#ibcon#wrote, iclass 25, count 0 2006.173.21:48:29.04#ibcon#about to read 3, iclass 25, count 0 2006.173.21:48:29.07#ibcon#read 3, iclass 25, count 0 2006.173.21:48:29.07#ibcon#about to read 4, iclass 25, count 0 2006.173.21:48:29.07#ibcon#read 4, iclass 25, count 0 2006.173.21:48:29.07#ibcon#about to read 5, iclass 25, count 0 2006.173.21:48:29.07#ibcon#read 5, iclass 25, count 0 2006.173.21:48:29.07#ibcon#about to read 6, iclass 25, count 0 2006.173.21:48:29.07#ibcon#read 6, iclass 25, count 0 2006.173.21:48:29.07#ibcon#end of sib2, iclass 25, count 0 2006.173.21:48:29.07#ibcon#*after write, iclass 25, count 0 2006.173.21:48:29.07#ibcon#*before return 0, iclass 25, count 0 2006.173.21:48:29.07#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.21:48:29.07#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.21:48:29.07#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.21:48:29.07#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.21:48:29.07$vck44/vblo=4,679.99 2006.173.21:48:29.07#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.21:48:29.07#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.21:48:29.07#ibcon#ireg 17 cls_cnt 0 2006.173.21:48:29.07#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.21:48:29.07#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.21:48:29.07#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.21:48:29.07#ibcon#enter wrdev, iclass 27, count 0 2006.173.21:48:29.07#ibcon#first serial, iclass 27, count 0 2006.173.21:48:29.07#ibcon#enter sib2, iclass 27, count 0 2006.173.21:48:29.07#ibcon#flushed, iclass 27, count 0 2006.173.21:48:29.07#ibcon#about to write, iclass 27, count 0 2006.173.21:48:29.08#ibcon#wrote, iclass 27, count 0 2006.173.21:48:29.08#ibcon#about to read 3, iclass 27, count 0 2006.173.21:48:29.09#ibcon#read 3, iclass 27, count 0 2006.173.21:48:29.09#ibcon#about to read 4, iclass 27, count 0 2006.173.21:48:29.09#ibcon#read 4, iclass 27, count 0 2006.173.21:48:29.09#ibcon#about to read 5, iclass 27, count 0 2006.173.21:48:29.09#ibcon#read 5, iclass 27, count 0 2006.173.21:48:29.09#ibcon#about to read 6, iclass 27, count 0 2006.173.21:48:29.09#ibcon#read 6, iclass 27, count 0 2006.173.21:48:29.09#ibcon#end of sib2, iclass 27, count 0 2006.173.21:48:29.09#ibcon#*mode == 0, iclass 27, count 0 2006.173.21:48:29.09#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.21:48:29.09#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.21:48:29.09#ibcon#*before write, iclass 27, count 0 2006.173.21:48:29.09#ibcon#enter sib2, iclass 27, count 0 2006.173.21:48:29.09#ibcon#flushed, iclass 27, count 0 2006.173.21:48:29.09#ibcon#about to write, iclass 27, count 0 2006.173.21:48:29.09#ibcon#wrote, iclass 27, count 0 2006.173.21:48:29.09#ibcon#about to read 3, iclass 27, count 0 2006.173.21:48:29.13#ibcon#read 3, iclass 27, count 0 2006.173.21:48:29.13#ibcon#about to read 4, iclass 27, count 0 2006.173.21:48:29.13#ibcon#read 4, iclass 27, count 0 2006.173.21:48:29.13#ibcon#about to read 5, iclass 27, count 0 2006.173.21:48:29.13#ibcon#read 5, iclass 27, count 0 2006.173.21:48:29.13#ibcon#about to read 6, iclass 27, count 0 2006.173.21:48:29.13#ibcon#read 6, iclass 27, count 0 2006.173.21:48:29.13#ibcon#end of sib2, iclass 27, count 0 2006.173.21:48:29.13#ibcon#*after write, iclass 27, count 0 2006.173.21:48:29.13#ibcon#*before return 0, iclass 27, count 0 2006.173.21:48:29.13#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.21:48:29.13#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.21:48:29.13#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.21:48:29.13#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.21:48:29.13$vck44/vb=4,4 2006.173.21:48:29.13#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.21:48:29.13#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.21:48:29.13#ibcon#ireg 11 cls_cnt 2 2006.173.21:48:29.13#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.21:48:29.19#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.21:48:29.19#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.21:48:29.19#ibcon#enter wrdev, iclass 29, count 2 2006.173.21:48:29.19#ibcon#first serial, iclass 29, count 2 2006.173.21:48:29.19#ibcon#enter sib2, iclass 29, count 2 2006.173.21:48:29.19#ibcon#flushed, iclass 29, count 2 2006.173.21:48:29.19#ibcon#about to write, iclass 29, count 2 2006.173.21:48:29.19#ibcon#wrote, iclass 29, count 2 2006.173.21:48:29.19#ibcon#about to read 3, iclass 29, count 2 2006.173.21:48:29.21#ibcon#read 3, iclass 29, count 2 2006.173.21:48:29.21#ibcon#about to read 4, iclass 29, count 2 2006.173.21:48:29.21#ibcon#read 4, iclass 29, count 2 2006.173.21:48:29.21#ibcon#about to read 5, iclass 29, count 2 2006.173.21:48:29.21#ibcon#read 5, iclass 29, count 2 2006.173.21:48:29.21#ibcon#about to read 6, iclass 29, count 2 2006.173.21:48:29.21#ibcon#read 6, iclass 29, count 2 2006.173.21:48:29.21#ibcon#end of sib2, iclass 29, count 2 2006.173.21:48:29.21#ibcon#*mode == 0, iclass 29, count 2 2006.173.21:48:29.21#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.21:48:29.21#ibcon#[27=AT04-04\r\n] 2006.173.21:48:29.21#ibcon#*before write, iclass 29, count 2 2006.173.21:48:29.21#ibcon#enter sib2, iclass 29, count 2 2006.173.21:48:29.21#ibcon#flushed, iclass 29, count 2 2006.173.21:48:29.21#ibcon#about to write, iclass 29, count 2 2006.173.21:48:29.21#ibcon#wrote, iclass 29, count 2 2006.173.21:48:29.21#ibcon#about to read 3, iclass 29, count 2 2006.173.21:48:29.24#ibcon#read 3, iclass 29, count 2 2006.173.21:48:29.24#ibcon#about to read 4, iclass 29, count 2 2006.173.21:48:29.24#ibcon#read 4, iclass 29, count 2 2006.173.21:48:29.24#ibcon#about to read 5, iclass 29, count 2 2006.173.21:48:29.24#ibcon#read 5, iclass 29, count 2 2006.173.21:48:29.24#ibcon#about to read 6, iclass 29, count 2 2006.173.21:48:29.24#ibcon#read 6, iclass 29, count 2 2006.173.21:48:29.24#ibcon#end of sib2, iclass 29, count 2 2006.173.21:48:29.24#ibcon#*after write, iclass 29, count 2 2006.173.21:48:29.24#ibcon#*before return 0, iclass 29, count 2 2006.173.21:48:29.24#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.21:48:29.24#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.21:48:29.24#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.21:48:29.24#ibcon#ireg 7 cls_cnt 0 2006.173.21:48:29.24#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.21:48:29.36#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.21:48:29.36#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.21:48:29.36#ibcon#enter wrdev, iclass 29, count 0 2006.173.21:48:29.36#ibcon#first serial, iclass 29, count 0 2006.173.21:48:29.36#ibcon#enter sib2, iclass 29, count 0 2006.173.21:48:29.36#ibcon#flushed, iclass 29, count 0 2006.173.21:48:29.36#ibcon#about to write, iclass 29, count 0 2006.173.21:48:29.36#ibcon#wrote, iclass 29, count 0 2006.173.21:48:29.36#ibcon#about to read 3, iclass 29, count 0 2006.173.21:48:29.38#ibcon#read 3, iclass 29, count 0 2006.173.21:48:29.38#ibcon#about to read 4, iclass 29, count 0 2006.173.21:48:29.38#ibcon#read 4, iclass 29, count 0 2006.173.21:48:29.38#ibcon#about to read 5, iclass 29, count 0 2006.173.21:48:29.38#ibcon#read 5, iclass 29, count 0 2006.173.21:48:29.38#ibcon#about to read 6, iclass 29, count 0 2006.173.21:48:29.38#ibcon#read 6, iclass 29, count 0 2006.173.21:48:29.38#ibcon#end of sib2, iclass 29, count 0 2006.173.21:48:29.38#ibcon#*mode == 0, iclass 29, count 0 2006.173.21:48:29.38#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.21:48:29.38#ibcon#[27=USB\r\n] 2006.173.21:48:29.38#ibcon#*before write, iclass 29, count 0 2006.173.21:48:29.38#ibcon#enter sib2, iclass 29, count 0 2006.173.21:48:29.38#ibcon#flushed, iclass 29, count 0 2006.173.21:48:29.38#ibcon#about to write, iclass 29, count 0 2006.173.21:48:29.38#ibcon#wrote, iclass 29, count 0 2006.173.21:48:29.38#ibcon#about to read 3, iclass 29, count 0 2006.173.21:48:29.41#ibcon#read 3, iclass 29, count 0 2006.173.21:48:29.41#ibcon#about to read 4, iclass 29, count 0 2006.173.21:48:29.41#ibcon#read 4, iclass 29, count 0 2006.173.21:48:29.41#ibcon#about to read 5, iclass 29, count 0 2006.173.21:48:29.41#ibcon#read 5, iclass 29, count 0 2006.173.21:48:29.41#ibcon#about to read 6, iclass 29, count 0 2006.173.21:48:29.41#ibcon#read 6, iclass 29, count 0 2006.173.21:48:29.41#ibcon#end of sib2, iclass 29, count 0 2006.173.21:48:29.41#ibcon#*after write, iclass 29, count 0 2006.173.21:48:29.41#ibcon#*before return 0, iclass 29, count 0 2006.173.21:48:29.41#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.21:48:29.41#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.21:48:29.41#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.21:48:29.41#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.21:48:29.41$vck44/vblo=5,709.99 2006.173.21:48:29.41#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.21:48:29.41#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.21:48:29.41#ibcon#ireg 17 cls_cnt 0 2006.173.21:48:29.41#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.21:48:29.41#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.21:48:29.41#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.21:48:29.41#ibcon#enter wrdev, iclass 31, count 0 2006.173.21:48:29.41#ibcon#first serial, iclass 31, count 0 2006.173.21:48:29.41#ibcon#enter sib2, iclass 31, count 0 2006.173.21:48:29.41#ibcon#flushed, iclass 31, count 0 2006.173.21:48:29.41#ibcon#about to write, iclass 31, count 0 2006.173.21:48:29.42#ibcon#wrote, iclass 31, count 0 2006.173.21:48:29.42#ibcon#about to read 3, iclass 31, count 0 2006.173.21:48:29.43#ibcon#read 3, iclass 31, count 0 2006.173.21:48:29.43#ibcon#about to read 4, iclass 31, count 0 2006.173.21:48:29.43#ibcon#read 4, iclass 31, count 0 2006.173.21:48:29.43#ibcon#about to read 5, iclass 31, count 0 2006.173.21:48:29.43#ibcon#read 5, iclass 31, count 0 2006.173.21:48:29.43#ibcon#about to read 6, iclass 31, count 0 2006.173.21:48:29.43#ibcon#read 6, iclass 31, count 0 2006.173.21:48:29.43#ibcon#end of sib2, iclass 31, count 0 2006.173.21:48:29.43#ibcon#*mode == 0, iclass 31, count 0 2006.173.21:48:29.43#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.21:48:29.43#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.21:48:29.43#ibcon#*before write, iclass 31, count 0 2006.173.21:48:29.43#ibcon#enter sib2, iclass 31, count 0 2006.173.21:48:29.43#ibcon#flushed, iclass 31, count 0 2006.173.21:48:29.43#ibcon#about to write, iclass 31, count 0 2006.173.21:48:29.43#ibcon#wrote, iclass 31, count 0 2006.173.21:48:29.43#ibcon#about to read 3, iclass 31, count 0 2006.173.21:48:29.47#ibcon#read 3, iclass 31, count 0 2006.173.21:48:29.47#ibcon#about to read 4, iclass 31, count 0 2006.173.21:48:29.47#ibcon#read 4, iclass 31, count 0 2006.173.21:48:29.47#ibcon#about to read 5, iclass 31, count 0 2006.173.21:48:29.47#ibcon#read 5, iclass 31, count 0 2006.173.21:48:29.47#ibcon#about to read 6, iclass 31, count 0 2006.173.21:48:29.47#ibcon#read 6, iclass 31, count 0 2006.173.21:48:29.47#ibcon#end of sib2, iclass 31, count 0 2006.173.21:48:29.47#ibcon#*after write, iclass 31, count 0 2006.173.21:48:29.47#ibcon#*before return 0, iclass 31, count 0 2006.173.21:48:29.47#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.21:48:29.47#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.21:48:29.47#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.21:48:29.47#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.21:48:29.47$vck44/vb=5,4 2006.173.21:48:29.47#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.173.21:48:29.47#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.173.21:48:29.47#ibcon#ireg 11 cls_cnt 2 2006.173.21:48:29.47#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.21:48:29.53#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.21:48:29.53#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.21:48:29.53#ibcon#enter wrdev, iclass 33, count 2 2006.173.21:48:29.53#ibcon#first serial, iclass 33, count 2 2006.173.21:48:29.53#ibcon#enter sib2, iclass 33, count 2 2006.173.21:48:29.53#ibcon#flushed, iclass 33, count 2 2006.173.21:48:29.53#ibcon#about to write, iclass 33, count 2 2006.173.21:48:29.53#ibcon#wrote, iclass 33, count 2 2006.173.21:48:29.53#ibcon#about to read 3, iclass 33, count 2 2006.173.21:48:29.55#ibcon#read 3, iclass 33, count 2 2006.173.21:48:29.55#ibcon#about to read 4, iclass 33, count 2 2006.173.21:48:29.55#ibcon#read 4, iclass 33, count 2 2006.173.21:48:29.55#ibcon#about to read 5, iclass 33, count 2 2006.173.21:48:29.55#ibcon#read 5, iclass 33, count 2 2006.173.21:48:29.55#ibcon#about to read 6, iclass 33, count 2 2006.173.21:48:29.55#ibcon#read 6, iclass 33, count 2 2006.173.21:48:29.55#ibcon#end of sib2, iclass 33, count 2 2006.173.21:48:29.55#ibcon#*mode == 0, iclass 33, count 2 2006.173.21:48:29.55#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.173.21:48:29.55#ibcon#[27=AT05-04\r\n] 2006.173.21:48:29.55#ibcon#*before write, iclass 33, count 2 2006.173.21:48:29.55#ibcon#enter sib2, iclass 33, count 2 2006.173.21:48:29.55#ibcon#flushed, iclass 33, count 2 2006.173.21:48:29.55#ibcon#about to write, iclass 33, count 2 2006.173.21:48:29.55#ibcon#wrote, iclass 33, count 2 2006.173.21:48:29.55#ibcon#about to read 3, iclass 33, count 2 2006.173.21:48:29.58#ibcon#read 3, iclass 33, count 2 2006.173.21:48:29.58#ibcon#about to read 4, iclass 33, count 2 2006.173.21:48:29.58#ibcon#read 4, iclass 33, count 2 2006.173.21:48:29.58#ibcon#about to read 5, iclass 33, count 2 2006.173.21:48:29.58#ibcon#read 5, iclass 33, count 2 2006.173.21:48:29.58#ibcon#about to read 6, iclass 33, count 2 2006.173.21:48:29.58#ibcon#read 6, iclass 33, count 2 2006.173.21:48:29.58#ibcon#end of sib2, iclass 33, count 2 2006.173.21:48:29.58#ibcon#*after write, iclass 33, count 2 2006.173.21:48:29.58#ibcon#*before return 0, iclass 33, count 2 2006.173.21:48:29.58#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.21:48:29.58#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.173.21:48:29.58#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.173.21:48:29.58#ibcon#ireg 7 cls_cnt 0 2006.173.21:48:29.58#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.21:48:29.70#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.21:48:29.70#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.21:48:29.70#ibcon#enter wrdev, iclass 33, count 0 2006.173.21:48:29.70#ibcon#first serial, iclass 33, count 0 2006.173.21:48:29.70#ibcon#enter sib2, iclass 33, count 0 2006.173.21:48:29.70#ibcon#flushed, iclass 33, count 0 2006.173.21:48:29.70#ibcon#about to write, iclass 33, count 0 2006.173.21:48:29.70#ibcon#wrote, iclass 33, count 0 2006.173.21:48:29.70#ibcon#about to read 3, iclass 33, count 0 2006.173.21:48:29.72#ibcon#read 3, iclass 33, count 0 2006.173.21:48:29.72#ibcon#about to read 4, iclass 33, count 0 2006.173.21:48:29.72#ibcon#read 4, iclass 33, count 0 2006.173.21:48:29.72#ibcon#about to read 5, iclass 33, count 0 2006.173.21:48:29.72#ibcon#read 5, iclass 33, count 0 2006.173.21:48:29.72#ibcon#about to read 6, iclass 33, count 0 2006.173.21:48:29.72#ibcon#read 6, iclass 33, count 0 2006.173.21:48:29.72#ibcon#end of sib2, iclass 33, count 0 2006.173.21:48:29.72#ibcon#*mode == 0, iclass 33, count 0 2006.173.21:48:29.72#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.21:48:29.72#ibcon#[27=USB\r\n] 2006.173.21:48:29.72#ibcon#*before write, iclass 33, count 0 2006.173.21:48:29.72#ibcon#enter sib2, iclass 33, count 0 2006.173.21:48:29.72#ibcon#flushed, iclass 33, count 0 2006.173.21:48:29.72#ibcon#about to write, iclass 33, count 0 2006.173.21:48:29.72#ibcon#wrote, iclass 33, count 0 2006.173.21:48:29.72#ibcon#about to read 3, iclass 33, count 0 2006.173.21:48:29.75#ibcon#read 3, iclass 33, count 0 2006.173.21:48:29.75#ibcon#about to read 4, iclass 33, count 0 2006.173.21:48:29.75#ibcon#read 4, iclass 33, count 0 2006.173.21:48:29.75#ibcon#about to read 5, iclass 33, count 0 2006.173.21:48:29.75#ibcon#read 5, iclass 33, count 0 2006.173.21:48:29.75#ibcon#about to read 6, iclass 33, count 0 2006.173.21:48:29.75#ibcon#read 6, iclass 33, count 0 2006.173.21:48:29.75#ibcon#end of sib2, iclass 33, count 0 2006.173.21:48:29.75#ibcon#*after write, iclass 33, count 0 2006.173.21:48:29.75#ibcon#*before return 0, iclass 33, count 0 2006.173.21:48:29.75#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.21:48:29.75#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.173.21:48:29.75#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.21:48:29.75#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.21:48:29.75$vck44/vblo=6,719.99 2006.173.21:48:29.75#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.21:48:29.75#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.21:48:29.75#ibcon#ireg 17 cls_cnt 0 2006.173.21:48:29.75#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.21:48:29.75#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.21:48:29.75#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.21:48:29.75#ibcon#enter wrdev, iclass 35, count 0 2006.173.21:48:29.76#ibcon#first serial, iclass 35, count 0 2006.173.21:48:29.76#ibcon#enter sib2, iclass 35, count 0 2006.173.21:48:29.76#ibcon#flushed, iclass 35, count 0 2006.173.21:48:29.76#ibcon#about to write, iclass 35, count 0 2006.173.21:48:29.76#ibcon#wrote, iclass 35, count 0 2006.173.21:48:29.76#ibcon#about to read 3, iclass 35, count 0 2006.173.21:48:29.77#ibcon#read 3, iclass 35, count 0 2006.173.21:48:29.77#ibcon#about to read 4, iclass 35, count 0 2006.173.21:48:29.77#ibcon#read 4, iclass 35, count 0 2006.173.21:48:29.77#ibcon#about to read 5, iclass 35, count 0 2006.173.21:48:29.77#ibcon#read 5, iclass 35, count 0 2006.173.21:48:29.77#ibcon#about to read 6, iclass 35, count 0 2006.173.21:48:29.77#ibcon#read 6, iclass 35, count 0 2006.173.21:48:29.77#ibcon#end of sib2, iclass 35, count 0 2006.173.21:48:29.77#ibcon#*mode == 0, iclass 35, count 0 2006.173.21:48:29.77#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.21:48:29.77#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.21:48:29.77#ibcon#*before write, iclass 35, count 0 2006.173.21:48:29.77#ibcon#enter sib2, iclass 35, count 0 2006.173.21:48:29.77#ibcon#flushed, iclass 35, count 0 2006.173.21:48:29.77#ibcon#about to write, iclass 35, count 0 2006.173.21:48:29.77#ibcon#wrote, iclass 35, count 0 2006.173.21:48:29.77#ibcon#about to read 3, iclass 35, count 0 2006.173.21:48:29.81#ibcon#read 3, iclass 35, count 0 2006.173.21:48:29.81#ibcon#about to read 4, iclass 35, count 0 2006.173.21:48:29.81#ibcon#read 4, iclass 35, count 0 2006.173.21:48:29.81#ibcon#about to read 5, iclass 35, count 0 2006.173.21:48:29.81#ibcon#read 5, iclass 35, count 0 2006.173.21:48:29.81#ibcon#about to read 6, iclass 35, count 0 2006.173.21:48:29.81#ibcon#read 6, iclass 35, count 0 2006.173.21:48:29.81#ibcon#end of sib2, iclass 35, count 0 2006.173.21:48:29.81#ibcon#*after write, iclass 35, count 0 2006.173.21:48:29.81#ibcon#*before return 0, iclass 35, count 0 2006.173.21:48:29.81#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.21:48:29.81#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.21:48:29.81#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.21:48:29.81#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.21:48:29.81$vck44/vb=6,4 2006.173.21:48:29.81#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.173.21:48:29.81#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.173.21:48:29.81#ibcon#ireg 11 cls_cnt 2 2006.173.21:48:29.81#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.21:48:29.87#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.21:48:29.87#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.21:48:29.87#ibcon#enter wrdev, iclass 37, count 2 2006.173.21:48:29.87#ibcon#first serial, iclass 37, count 2 2006.173.21:48:29.87#ibcon#enter sib2, iclass 37, count 2 2006.173.21:48:29.87#ibcon#flushed, iclass 37, count 2 2006.173.21:48:29.87#ibcon#about to write, iclass 37, count 2 2006.173.21:48:29.87#ibcon#wrote, iclass 37, count 2 2006.173.21:48:29.87#ibcon#about to read 3, iclass 37, count 2 2006.173.21:48:29.89#ibcon#read 3, iclass 37, count 2 2006.173.21:48:29.89#ibcon#about to read 4, iclass 37, count 2 2006.173.21:48:29.89#ibcon#read 4, iclass 37, count 2 2006.173.21:48:29.89#ibcon#about to read 5, iclass 37, count 2 2006.173.21:48:29.89#ibcon#read 5, iclass 37, count 2 2006.173.21:48:29.89#ibcon#about to read 6, iclass 37, count 2 2006.173.21:48:29.89#ibcon#read 6, iclass 37, count 2 2006.173.21:48:29.89#ibcon#end of sib2, iclass 37, count 2 2006.173.21:48:29.89#ibcon#*mode == 0, iclass 37, count 2 2006.173.21:48:29.89#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.173.21:48:29.89#ibcon#[27=AT06-04\r\n] 2006.173.21:48:29.89#ibcon#*before write, iclass 37, count 2 2006.173.21:48:29.89#ibcon#enter sib2, iclass 37, count 2 2006.173.21:48:29.89#ibcon#flushed, iclass 37, count 2 2006.173.21:48:29.89#ibcon#about to write, iclass 37, count 2 2006.173.21:48:29.89#ibcon#wrote, iclass 37, count 2 2006.173.21:48:29.89#ibcon#about to read 3, iclass 37, count 2 2006.173.21:48:29.92#ibcon#read 3, iclass 37, count 2 2006.173.21:48:29.92#ibcon#about to read 4, iclass 37, count 2 2006.173.21:48:29.92#ibcon#read 4, iclass 37, count 2 2006.173.21:48:29.92#ibcon#about to read 5, iclass 37, count 2 2006.173.21:48:29.92#ibcon#read 5, iclass 37, count 2 2006.173.21:48:29.92#ibcon#about to read 6, iclass 37, count 2 2006.173.21:48:29.92#ibcon#read 6, iclass 37, count 2 2006.173.21:48:29.92#ibcon#end of sib2, iclass 37, count 2 2006.173.21:48:29.92#ibcon#*after write, iclass 37, count 2 2006.173.21:48:29.92#ibcon#*before return 0, iclass 37, count 2 2006.173.21:48:29.92#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.21:48:29.92#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.173.21:48:29.92#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.173.21:48:29.92#ibcon#ireg 7 cls_cnt 0 2006.173.21:48:29.92#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.21:48:30.04#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.21:48:30.04#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.21:48:30.04#ibcon#enter wrdev, iclass 37, count 0 2006.173.21:48:30.04#ibcon#first serial, iclass 37, count 0 2006.173.21:48:30.04#ibcon#enter sib2, iclass 37, count 0 2006.173.21:48:30.04#ibcon#flushed, iclass 37, count 0 2006.173.21:48:30.04#ibcon#about to write, iclass 37, count 0 2006.173.21:48:30.04#ibcon#wrote, iclass 37, count 0 2006.173.21:48:30.04#ibcon#about to read 3, iclass 37, count 0 2006.173.21:48:30.06#ibcon#read 3, iclass 37, count 0 2006.173.21:48:30.06#ibcon#about to read 4, iclass 37, count 0 2006.173.21:48:30.06#ibcon#read 4, iclass 37, count 0 2006.173.21:48:30.06#ibcon#about to read 5, iclass 37, count 0 2006.173.21:48:30.06#ibcon#read 5, iclass 37, count 0 2006.173.21:48:30.06#ibcon#about to read 6, iclass 37, count 0 2006.173.21:48:30.06#ibcon#read 6, iclass 37, count 0 2006.173.21:48:30.06#ibcon#end of sib2, iclass 37, count 0 2006.173.21:48:30.06#ibcon#*mode == 0, iclass 37, count 0 2006.173.21:48:30.06#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.21:48:30.06#ibcon#[27=USB\r\n] 2006.173.21:48:30.06#ibcon#*before write, iclass 37, count 0 2006.173.21:48:30.06#ibcon#enter sib2, iclass 37, count 0 2006.173.21:48:30.06#ibcon#flushed, iclass 37, count 0 2006.173.21:48:30.06#ibcon#about to write, iclass 37, count 0 2006.173.21:48:30.06#ibcon#wrote, iclass 37, count 0 2006.173.21:48:30.06#ibcon#about to read 3, iclass 37, count 0 2006.173.21:48:30.09#ibcon#read 3, iclass 37, count 0 2006.173.21:48:30.09#ibcon#about to read 4, iclass 37, count 0 2006.173.21:48:30.09#ibcon#read 4, iclass 37, count 0 2006.173.21:48:30.09#ibcon#about to read 5, iclass 37, count 0 2006.173.21:48:30.09#ibcon#read 5, iclass 37, count 0 2006.173.21:48:30.09#ibcon#about to read 6, iclass 37, count 0 2006.173.21:48:30.09#ibcon#read 6, iclass 37, count 0 2006.173.21:48:30.09#ibcon#end of sib2, iclass 37, count 0 2006.173.21:48:30.09#ibcon#*after write, iclass 37, count 0 2006.173.21:48:30.09#ibcon#*before return 0, iclass 37, count 0 2006.173.21:48:30.09#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.21:48:30.09#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.173.21:48:30.09#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.21:48:30.09#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.21:48:30.09$vck44/vblo=7,734.99 2006.173.21:48:30.09#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.21:48:30.09#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.21:48:30.09#ibcon#ireg 17 cls_cnt 0 2006.173.21:48:30.09#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.21:48:30.09#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.21:48:30.09#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.21:48:30.09#ibcon#enter wrdev, iclass 39, count 0 2006.173.21:48:30.09#ibcon#first serial, iclass 39, count 0 2006.173.21:48:30.09#ibcon#enter sib2, iclass 39, count 0 2006.173.21:48:30.09#ibcon#flushed, iclass 39, count 0 2006.173.21:48:30.09#ibcon#about to write, iclass 39, count 0 2006.173.21:48:30.10#ibcon#wrote, iclass 39, count 0 2006.173.21:48:30.10#ibcon#about to read 3, iclass 39, count 0 2006.173.21:48:30.11#ibcon#read 3, iclass 39, count 0 2006.173.21:48:30.11#ibcon#about to read 4, iclass 39, count 0 2006.173.21:48:30.11#ibcon#read 4, iclass 39, count 0 2006.173.21:48:30.11#ibcon#about to read 5, iclass 39, count 0 2006.173.21:48:30.11#ibcon#read 5, iclass 39, count 0 2006.173.21:48:30.11#ibcon#about to read 6, iclass 39, count 0 2006.173.21:48:30.11#ibcon#read 6, iclass 39, count 0 2006.173.21:48:30.11#ibcon#end of sib2, iclass 39, count 0 2006.173.21:48:30.11#ibcon#*mode == 0, iclass 39, count 0 2006.173.21:48:30.11#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.21:48:30.11#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.21:48:30.11#ibcon#*before write, iclass 39, count 0 2006.173.21:48:30.11#ibcon#enter sib2, iclass 39, count 0 2006.173.21:48:30.11#ibcon#flushed, iclass 39, count 0 2006.173.21:48:30.11#ibcon#about to write, iclass 39, count 0 2006.173.21:48:30.11#ibcon#wrote, iclass 39, count 0 2006.173.21:48:30.11#ibcon#about to read 3, iclass 39, count 0 2006.173.21:48:30.15#ibcon#read 3, iclass 39, count 0 2006.173.21:48:30.15#ibcon#about to read 4, iclass 39, count 0 2006.173.21:48:30.15#ibcon#read 4, iclass 39, count 0 2006.173.21:48:30.15#ibcon#about to read 5, iclass 39, count 0 2006.173.21:48:30.15#ibcon#read 5, iclass 39, count 0 2006.173.21:48:30.15#ibcon#about to read 6, iclass 39, count 0 2006.173.21:48:30.15#ibcon#read 6, iclass 39, count 0 2006.173.21:48:30.15#ibcon#end of sib2, iclass 39, count 0 2006.173.21:48:30.15#ibcon#*after write, iclass 39, count 0 2006.173.21:48:30.15#ibcon#*before return 0, iclass 39, count 0 2006.173.21:48:30.15#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.21:48:30.15#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.21:48:30.15#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.21:48:30.15#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.21:48:30.15$vck44/vb=7,4 2006.173.21:48:30.15#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.21:48:30.15#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.21:48:30.15#ibcon#ireg 11 cls_cnt 2 2006.173.21:48:30.15#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.21:48:30.21#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.21:48:30.21#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.21:48:30.21#ibcon#enter wrdev, iclass 3, count 2 2006.173.21:48:30.21#ibcon#first serial, iclass 3, count 2 2006.173.21:48:30.21#ibcon#enter sib2, iclass 3, count 2 2006.173.21:48:30.21#ibcon#flushed, iclass 3, count 2 2006.173.21:48:30.21#ibcon#about to write, iclass 3, count 2 2006.173.21:48:30.21#ibcon#wrote, iclass 3, count 2 2006.173.21:48:30.21#ibcon#about to read 3, iclass 3, count 2 2006.173.21:48:30.23#ibcon#read 3, iclass 3, count 2 2006.173.21:48:30.23#ibcon#about to read 4, iclass 3, count 2 2006.173.21:48:30.23#ibcon#read 4, iclass 3, count 2 2006.173.21:48:30.23#ibcon#about to read 5, iclass 3, count 2 2006.173.21:48:30.23#ibcon#read 5, iclass 3, count 2 2006.173.21:48:30.23#ibcon#about to read 6, iclass 3, count 2 2006.173.21:48:30.23#ibcon#read 6, iclass 3, count 2 2006.173.21:48:30.23#ibcon#end of sib2, iclass 3, count 2 2006.173.21:48:30.23#ibcon#*mode == 0, iclass 3, count 2 2006.173.21:48:30.23#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.21:48:30.23#ibcon#[27=AT07-04\r\n] 2006.173.21:48:30.23#ibcon#*before write, iclass 3, count 2 2006.173.21:48:30.23#ibcon#enter sib2, iclass 3, count 2 2006.173.21:48:30.23#ibcon#flushed, iclass 3, count 2 2006.173.21:48:30.23#ibcon#about to write, iclass 3, count 2 2006.173.21:48:30.23#ibcon#wrote, iclass 3, count 2 2006.173.21:48:30.23#ibcon#about to read 3, iclass 3, count 2 2006.173.21:48:30.26#ibcon#read 3, iclass 3, count 2 2006.173.21:48:30.26#ibcon#about to read 4, iclass 3, count 2 2006.173.21:48:30.26#ibcon#read 4, iclass 3, count 2 2006.173.21:48:30.26#ibcon#about to read 5, iclass 3, count 2 2006.173.21:48:30.26#ibcon#read 5, iclass 3, count 2 2006.173.21:48:30.26#ibcon#about to read 6, iclass 3, count 2 2006.173.21:48:30.26#ibcon#read 6, iclass 3, count 2 2006.173.21:48:30.26#ibcon#end of sib2, iclass 3, count 2 2006.173.21:48:30.26#ibcon#*after write, iclass 3, count 2 2006.173.21:48:30.26#ibcon#*before return 0, iclass 3, count 2 2006.173.21:48:30.26#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.21:48:30.26#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.21:48:30.26#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.21:48:30.26#ibcon#ireg 7 cls_cnt 0 2006.173.21:48:30.26#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.21:48:30.38#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.21:48:30.38#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.21:48:30.38#ibcon#enter wrdev, iclass 3, count 0 2006.173.21:48:30.38#ibcon#first serial, iclass 3, count 0 2006.173.21:48:30.38#ibcon#enter sib2, iclass 3, count 0 2006.173.21:48:30.38#ibcon#flushed, iclass 3, count 0 2006.173.21:48:30.38#ibcon#about to write, iclass 3, count 0 2006.173.21:48:30.38#ibcon#wrote, iclass 3, count 0 2006.173.21:48:30.38#ibcon#about to read 3, iclass 3, count 0 2006.173.21:48:30.40#ibcon#read 3, iclass 3, count 0 2006.173.21:48:30.40#ibcon#about to read 4, iclass 3, count 0 2006.173.21:48:30.40#ibcon#read 4, iclass 3, count 0 2006.173.21:48:30.40#ibcon#about to read 5, iclass 3, count 0 2006.173.21:48:30.40#ibcon#read 5, iclass 3, count 0 2006.173.21:48:30.40#ibcon#about to read 6, iclass 3, count 0 2006.173.21:48:30.40#ibcon#read 6, iclass 3, count 0 2006.173.21:48:30.40#ibcon#end of sib2, iclass 3, count 0 2006.173.21:48:30.40#ibcon#*mode == 0, iclass 3, count 0 2006.173.21:48:30.40#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.21:48:30.40#ibcon#[27=USB\r\n] 2006.173.21:48:30.40#ibcon#*before write, iclass 3, count 0 2006.173.21:48:30.40#ibcon#enter sib2, iclass 3, count 0 2006.173.21:48:30.40#ibcon#flushed, iclass 3, count 0 2006.173.21:48:30.40#ibcon#about to write, iclass 3, count 0 2006.173.21:48:30.40#ibcon#wrote, iclass 3, count 0 2006.173.21:48:30.40#ibcon#about to read 3, iclass 3, count 0 2006.173.21:48:30.43#ibcon#read 3, iclass 3, count 0 2006.173.21:48:30.43#ibcon#about to read 4, iclass 3, count 0 2006.173.21:48:30.43#ibcon#read 4, iclass 3, count 0 2006.173.21:48:30.43#ibcon#about to read 5, iclass 3, count 0 2006.173.21:48:30.43#ibcon#read 5, iclass 3, count 0 2006.173.21:48:30.43#ibcon#about to read 6, iclass 3, count 0 2006.173.21:48:30.43#ibcon#read 6, iclass 3, count 0 2006.173.21:48:30.43#ibcon#end of sib2, iclass 3, count 0 2006.173.21:48:30.43#ibcon#*after write, iclass 3, count 0 2006.173.21:48:30.43#ibcon#*before return 0, iclass 3, count 0 2006.173.21:48:30.43#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.21:48:30.43#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.21:48:30.43#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.21:48:30.43#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.21:48:30.43$vck44/vblo=8,744.99 2006.173.21:48:30.43#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.21:48:30.43#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.21:48:30.43#ibcon#ireg 17 cls_cnt 0 2006.173.21:48:30.43#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.21:48:30.43#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.21:48:30.43#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.21:48:30.43#ibcon#enter wrdev, iclass 5, count 0 2006.173.21:48:30.43#ibcon#first serial, iclass 5, count 0 2006.173.21:48:30.43#ibcon#enter sib2, iclass 5, count 0 2006.173.21:48:30.43#ibcon#flushed, iclass 5, count 0 2006.173.21:48:30.43#ibcon#about to write, iclass 5, count 0 2006.173.21:48:30.43#ibcon#wrote, iclass 5, count 0 2006.173.21:48:30.44#ibcon#about to read 3, iclass 5, count 0 2006.173.21:48:30.45#ibcon#read 3, iclass 5, count 0 2006.173.21:48:30.45#ibcon#about to read 4, iclass 5, count 0 2006.173.21:48:30.45#ibcon#read 4, iclass 5, count 0 2006.173.21:48:30.45#ibcon#about to read 5, iclass 5, count 0 2006.173.21:48:30.45#ibcon#read 5, iclass 5, count 0 2006.173.21:48:30.45#ibcon#about to read 6, iclass 5, count 0 2006.173.21:48:30.45#ibcon#read 6, iclass 5, count 0 2006.173.21:48:30.45#ibcon#end of sib2, iclass 5, count 0 2006.173.21:48:30.45#ibcon#*mode == 0, iclass 5, count 0 2006.173.21:48:30.45#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.21:48:30.45#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.21:48:30.45#ibcon#*before write, iclass 5, count 0 2006.173.21:48:30.45#ibcon#enter sib2, iclass 5, count 0 2006.173.21:48:30.45#ibcon#flushed, iclass 5, count 0 2006.173.21:48:30.45#ibcon#about to write, iclass 5, count 0 2006.173.21:48:30.45#ibcon#wrote, iclass 5, count 0 2006.173.21:48:30.45#ibcon#about to read 3, iclass 5, count 0 2006.173.21:48:30.49#ibcon#read 3, iclass 5, count 0 2006.173.21:48:30.49#ibcon#about to read 4, iclass 5, count 0 2006.173.21:48:30.49#ibcon#read 4, iclass 5, count 0 2006.173.21:48:30.49#ibcon#about to read 5, iclass 5, count 0 2006.173.21:48:30.49#ibcon#read 5, iclass 5, count 0 2006.173.21:48:30.49#ibcon#about to read 6, iclass 5, count 0 2006.173.21:48:30.49#ibcon#read 6, iclass 5, count 0 2006.173.21:48:30.49#ibcon#end of sib2, iclass 5, count 0 2006.173.21:48:30.49#ibcon#*after write, iclass 5, count 0 2006.173.21:48:30.49#ibcon#*before return 0, iclass 5, count 0 2006.173.21:48:30.49#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.21:48:30.49#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.21:48:30.49#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.21:48:30.49#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.21:48:30.49$vck44/vb=8,4 2006.173.21:48:30.49#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.173.21:48:30.49#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.173.21:48:30.49#ibcon#ireg 11 cls_cnt 2 2006.173.21:48:30.49#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.21:48:30.55#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.21:48:30.55#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.21:48:30.55#ibcon#enter wrdev, iclass 7, count 2 2006.173.21:48:30.55#ibcon#first serial, iclass 7, count 2 2006.173.21:48:30.55#ibcon#enter sib2, iclass 7, count 2 2006.173.21:48:30.55#ibcon#flushed, iclass 7, count 2 2006.173.21:48:30.55#ibcon#about to write, iclass 7, count 2 2006.173.21:48:30.55#ibcon#wrote, iclass 7, count 2 2006.173.21:48:30.55#ibcon#about to read 3, iclass 7, count 2 2006.173.21:48:30.57#ibcon#read 3, iclass 7, count 2 2006.173.21:48:30.57#ibcon#about to read 4, iclass 7, count 2 2006.173.21:48:30.57#ibcon#read 4, iclass 7, count 2 2006.173.21:48:30.57#ibcon#about to read 5, iclass 7, count 2 2006.173.21:48:30.57#ibcon#read 5, iclass 7, count 2 2006.173.21:48:30.57#ibcon#about to read 6, iclass 7, count 2 2006.173.21:48:30.57#ibcon#read 6, iclass 7, count 2 2006.173.21:48:30.57#ibcon#end of sib2, iclass 7, count 2 2006.173.21:48:30.57#ibcon#*mode == 0, iclass 7, count 2 2006.173.21:48:30.57#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.173.21:48:30.57#ibcon#[27=AT08-04\r\n] 2006.173.21:48:30.57#ibcon#*before write, iclass 7, count 2 2006.173.21:48:30.57#ibcon#enter sib2, iclass 7, count 2 2006.173.21:48:30.57#ibcon#flushed, iclass 7, count 2 2006.173.21:48:30.57#ibcon#about to write, iclass 7, count 2 2006.173.21:48:30.57#ibcon#wrote, iclass 7, count 2 2006.173.21:48:30.57#ibcon#about to read 3, iclass 7, count 2 2006.173.21:48:30.60#ibcon#read 3, iclass 7, count 2 2006.173.21:48:30.60#ibcon#about to read 4, iclass 7, count 2 2006.173.21:48:30.60#ibcon#read 4, iclass 7, count 2 2006.173.21:48:30.60#ibcon#about to read 5, iclass 7, count 2 2006.173.21:48:30.60#ibcon#read 5, iclass 7, count 2 2006.173.21:48:30.60#ibcon#about to read 6, iclass 7, count 2 2006.173.21:48:30.60#ibcon#read 6, iclass 7, count 2 2006.173.21:48:30.60#ibcon#end of sib2, iclass 7, count 2 2006.173.21:48:30.60#ibcon#*after write, iclass 7, count 2 2006.173.21:48:30.60#ibcon#*before return 0, iclass 7, count 2 2006.173.21:48:30.60#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.21:48:30.60#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.173.21:48:30.60#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.173.21:48:30.60#ibcon#ireg 7 cls_cnt 0 2006.173.21:48:30.60#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.21:48:30.72#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.21:48:30.72#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.21:48:30.72#ibcon#enter wrdev, iclass 7, count 0 2006.173.21:48:30.72#ibcon#first serial, iclass 7, count 0 2006.173.21:48:30.72#ibcon#enter sib2, iclass 7, count 0 2006.173.21:48:30.72#ibcon#flushed, iclass 7, count 0 2006.173.21:48:30.72#ibcon#about to write, iclass 7, count 0 2006.173.21:48:30.72#ibcon#wrote, iclass 7, count 0 2006.173.21:48:30.72#ibcon#about to read 3, iclass 7, count 0 2006.173.21:48:30.74#ibcon#read 3, iclass 7, count 0 2006.173.21:48:30.74#ibcon#about to read 4, iclass 7, count 0 2006.173.21:48:30.74#ibcon#read 4, iclass 7, count 0 2006.173.21:48:30.74#ibcon#about to read 5, iclass 7, count 0 2006.173.21:48:30.74#ibcon#read 5, iclass 7, count 0 2006.173.21:48:30.74#ibcon#about to read 6, iclass 7, count 0 2006.173.21:48:30.74#ibcon#read 6, iclass 7, count 0 2006.173.21:48:30.74#ibcon#end of sib2, iclass 7, count 0 2006.173.21:48:30.74#ibcon#*mode == 0, iclass 7, count 0 2006.173.21:48:30.74#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.21:48:30.74#ibcon#[27=USB\r\n] 2006.173.21:48:30.74#ibcon#*before write, iclass 7, count 0 2006.173.21:48:30.74#ibcon#enter sib2, iclass 7, count 0 2006.173.21:48:30.74#ibcon#flushed, iclass 7, count 0 2006.173.21:48:30.74#ibcon#about to write, iclass 7, count 0 2006.173.21:48:30.74#ibcon#wrote, iclass 7, count 0 2006.173.21:48:30.74#ibcon#about to read 3, iclass 7, count 0 2006.173.21:48:30.77#ibcon#read 3, iclass 7, count 0 2006.173.21:48:30.77#ibcon#about to read 4, iclass 7, count 0 2006.173.21:48:30.77#ibcon#read 4, iclass 7, count 0 2006.173.21:48:30.77#ibcon#about to read 5, iclass 7, count 0 2006.173.21:48:30.77#ibcon#read 5, iclass 7, count 0 2006.173.21:48:30.77#ibcon#about to read 6, iclass 7, count 0 2006.173.21:48:30.77#ibcon#read 6, iclass 7, count 0 2006.173.21:48:30.77#ibcon#end of sib2, iclass 7, count 0 2006.173.21:48:30.77#ibcon#*after write, iclass 7, count 0 2006.173.21:48:30.77#ibcon#*before return 0, iclass 7, count 0 2006.173.21:48:30.77#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.21:48:30.77#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.173.21:48:30.77#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.21:48:30.77#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.21:48:30.77$vck44/vabw=wide 2006.173.21:48:30.77#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.21:48:30.77#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.21:48:30.77#ibcon#ireg 8 cls_cnt 0 2006.173.21:48:30.77#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.21:48:30.77#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.21:48:30.77#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.21:48:30.77#ibcon#enter wrdev, iclass 11, count 0 2006.173.21:48:30.77#ibcon#first serial, iclass 11, count 0 2006.173.21:48:30.77#ibcon#enter sib2, iclass 11, count 0 2006.173.21:48:30.77#ibcon#flushed, iclass 11, count 0 2006.173.21:48:30.77#ibcon#about to write, iclass 11, count 0 2006.173.21:48:30.77#ibcon#wrote, iclass 11, count 0 2006.173.21:48:30.78#ibcon#about to read 3, iclass 11, count 0 2006.173.21:48:30.79#ibcon#read 3, iclass 11, count 0 2006.173.21:48:30.79#ibcon#about to read 4, iclass 11, count 0 2006.173.21:48:30.79#ibcon#read 4, iclass 11, count 0 2006.173.21:48:30.79#ibcon#about to read 5, iclass 11, count 0 2006.173.21:48:30.79#ibcon#read 5, iclass 11, count 0 2006.173.21:48:30.79#ibcon#about to read 6, iclass 11, count 0 2006.173.21:48:30.79#ibcon#read 6, iclass 11, count 0 2006.173.21:48:30.79#ibcon#end of sib2, iclass 11, count 0 2006.173.21:48:30.79#ibcon#*mode == 0, iclass 11, count 0 2006.173.21:48:30.79#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.21:48:30.79#ibcon#[25=BW32\r\n] 2006.173.21:48:30.79#ibcon#*before write, iclass 11, count 0 2006.173.21:48:30.79#ibcon#enter sib2, iclass 11, count 0 2006.173.21:48:30.79#ibcon#flushed, iclass 11, count 0 2006.173.21:48:30.79#ibcon#about to write, iclass 11, count 0 2006.173.21:48:30.79#ibcon#wrote, iclass 11, count 0 2006.173.21:48:30.79#ibcon#about to read 3, iclass 11, count 0 2006.173.21:48:30.82#ibcon#read 3, iclass 11, count 0 2006.173.21:48:30.82#ibcon#about to read 4, iclass 11, count 0 2006.173.21:48:30.82#ibcon#read 4, iclass 11, count 0 2006.173.21:48:30.82#ibcon#about to read 5, iclass 11, count 0 2006.173.21:48:30.82#ibcon#read 5, iclass 11, count 0 2006.173.21:48:30.82#ibcon#about to read 6, iclass 11, count 0 2006.173.21:48:30.82#ibcon#read 6, iclass 11, count 0 2006.173.21:48:30.82#ibcon#end of sib2, iclass 11, count 0 2006.173.21:48:30.82#ibcon#*after write, iclass 11, count 0 2006.173.21:48:30.82#ibcon#*before return 0, iclass 11, count 0 2006.173.21:48:30.82#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.21:48:30.82#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.21:48:30.82#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.21:48:30.82#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.21:48:30.82$vck44/vbbw=wide 2006.173.21:48:30.82#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.21:48:30.82#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.21:48:30.82#ibcon#ireg 8 cls_cnt 0 2006.173.21:48:30.82#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.21:48:30.89#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.21:48:30.89#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.21:48:30.89#ibcon#enter wrdev, iclass 13, count 0 2006.173.21:48:30.89#ibcon#first serial, iclass 13, count 0 2006.173.21:48:30.89#ibcon#enter sib2, iclass 13, count 0 2006.173.21:48:30.89#ibcon#flushed, iclass 13, count 0 2006.173.21:48:30.89#ibcon#about to write, iclass 13, count 0 2006.173.21:48:30.89#ibcon#wrote, iclass 13, count 0 2006.173.21:48:30.89#ibcon#about to read 3, iclass 13, count 0 2006.173.21:48:30.91#ibcon#read 3, iclass 13, count 0 2006.173.21:48:30.91#ibcon#about to read 4, iclass 13, count 0 2006.173.21:48:30.91#ibcon#read 4, iclass 13, count 0 2006.173.21:48:30.91#ibcon#about to read 5, iclass 13, count 0 2006.173.21:48:30.91#ibcon#read 5, iclass 13, count 0 2006.173.21:48:30.91#ibcon#about to read 6, iclass 13, count 0 2006.173.21:48:30.91#ibcon#read 6, iclass 13, count 0 2006.173.21:48:30.91#ibcon#end of sib2, iclass 13, count 0 2006.173.21:48:30.91#ibcon#*mode == 0, iclass 13, count 0 2006.173.21:48:30.91#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.21:48:30.91#ibcon#[27=BW32\r\n] 2006.173.21:48:30.91#ibcon#*before write, iclass 13, count 0 2006.173.21:48:30.91#ibcon#enter sib2, iclass 13, count 0 2006.173.21:48:30.91#ibcon#flushed, iclass 13, count 0 2006.173.21:48:30.91#ibcon#about to write, iclass 13, count 0 2006.173.21:48:30.91#ibcon#wrote, iclass 13, count 0 2006.173.21:48:30.91#ibcon#about to read 3, iclass 13, count 0 2006.173.21:48:30.94#ibcon#read 3, iclass 13, count 0 2006.173.21:48:30.94#ibcon#about to read 4, iclass 13, count 0 2006.173.21:48:30.94#ibcon#read 4, iclass 13, count 0 2006.173.21:48:30.94#ibcon#about to read 5, iclass 13, count 0 2006.173.21:48:30.94#ibcon#read 5, iclass 13, count 0 2006.173.21:48:30.94#ibcon#about to read 6, iclass 13, count 0 2006.173.21:48:30.94#ibcon#read 6, iclass 13, count 0 2006.173.21:48:30.94#ibcon#end of sib2, iclass 13, count 0 2006.173.21:48:30.94#ibcon#*after write, iclass 13, count 0 2006.173.21:48:30.94#ibcon#*before return 0, iclass 13, count 0 2006.173.21:48:30.94#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.21:48:30.94#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.21:48:30.94#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.21:48:30.94#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.21:48:30.94$setupk4/ifdk4 2006.173.21:48:30.95$ifdk4/lo= 2006.173.21:48:30.95$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.21:48:30.95$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.21:48:30.95$ifdk4/patch= 2006.173.21:48:30.95$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.21:48:30.95$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.21:48:30.95$setupk4/!*+20s 2006.173.21:48:37.94#abcon#<5=/00 0.2 0.6 21.39 991003.3\r\n> 2006.173.21:48:37.96#abcon#{5=INTERFACE CLEAR} 2006.173.21:48:38.02#abcon#[5=S1D000X0/0*\r\n] 2006.173.21:48:45.47$setupk4/"tpicd 2006.173.21:48:45.47$setupk4/echo=off 2006.173.21:48:45.47$setupk4/xlog=off 2006.173.21:48:45.47:!2006.173.21:52:24 2006.173.21:48:48.14#trakl#Source acquired 2006.173.21:48:49.14#flagr#flagr/antenna,acquired 2006.173.21:52:24.00:preob 2006.173.21:52:24.13/onsource/TRACKING 2006.173.21:52:24.13:!2006.173.21:52:34 2006.173.21:52:34.00:"tape 2006.173.21:52:34.00:"st=record 2006.173.21:52:34.00:data_valid=on 2006.173.21:52:34.00:midob 2006.173.21:52:34.13/onsource/TRACKING 2006.173.21:52:34.13/wx/21.54,1003.3,99 2006.173.21:52:34.28/cable/+6.5157E-03 2006.173.21:52:35.37/va/01,07,usb,yes,36,39 2006.173.21:52:35.37/va/02,06,usb,yes,36,37 2006.173.21:52:35.37/va/03,05,usb,yes,46,48 2006.173.21:52:35.37/va/04,06,usb,yes,37,39 2006.173.21:52:35.37/va/05,04,usb,yes,29,30 2006.173.21:52:35.37/va/06,03,usb,yes,41,40 2006.173.21:52:35.37/va/07,04,usb,yes,33,34 2006.173.21:52:35.37/va/08,04,usb,yes,28,34 2006.173.21:52:35.60/valo/01,524.99,yes,locked 2006.173.21:52:35.60/valo/02,534.99,yes,locked 2006.173.21:52:35.60/valo/03,564.99,yes,locked 2006.173.21:52:35.60/valo/04,624.99,yes,locked 2006.173.21:52:35.60/valo/05,734.99,yes,locked 2006.173.21:52:35.60/valo/06,814.99,yes,locked 2006.173.21:52:35.60/valo/07,864.99,yes,locked 2006.173.21:52:35.60/valo/08,884.99,yes,locked 2006.173.21:52:36.69/vb/01,04,usb,yes,30,28 2006.173.21:52:36.69/vb/02,04,usb,yes,32,32 2006.173.21:52:36.69/vb/03,04,usb,yes,29,32 2006.173.21:52:36.69/vb/04,04,usb,yes,34,33 2006.173.21:52:36.69/vb/05,04,usb,yes,26,29 2006.173.21:52:36.69/vb/06,04,usb,yes,31,27 2006.173.21:52:36.69/vb/07,04,usb,yes,30,30 2006.173.21:52:36.69/vb/08,04,usb,yes,28,31 2006.173.21:52:36.93/vblo/01,629.99,yes,locked 2006.173.21:52:36.93/vblo/02,634.99,yes,locked 2006.173.21:52:36.93/vblo/03,649.99,yes,locked 2006.173.21:52:36.93/vblo/04,679.99,yes,locked 2006.173.21:52:36.93/vblo/05,709.99,yes,locked 2006.173.21:52:36.93/vblo/06,719.99,yes,locked 2006.173.21:52:36.93/vblo/07,734.99,yes,locked 2006.173.21:52:36.93/vblo/08,744.99,yes,locked 2006.173.21:52:37.08/vabw/8 2006.173.21:52:37.23/vbbw/8 2006.173.21:52:37.34/xfe/off,on,15.2 2006.173.21:52:37.72/ifatt/23,28,28,28 2006.173.21:52:38.07/fmout-gps/S +3.91E-07 2006.173.21:52:38.12:!2006.173.21:56:44 2006.173.21:56:44.01:data_valid=off 2006.173.21:56:44.02:"et 2006.173.21:56:44.02:!+3s 2006.173.21:56:47.03:"tape 2006.173.21:56:47.03:postob 2006.173.21:56:47.13/cable/+6.5136E-03 2006.173.21:56:47.13/wx/21.67,1003.3,98 2006.173.21:56:47.19/fmout-gps/S +3.89E-07 2006.173.21:56:47.19:scan_name=173-2201,jd0606,120 2006.173.21:56:47.19:source=2201+315,220314.98,314538.3,2000.0,ccw 2006.173.21:56:49.14#flagr#flagr/antenna,new-source 2006.173.21:56:49.14:checkk5 2006.173.21:56:49.54/chk_autoobs//k5ts1/ autoobs is running! 2006.173.21:56:49.93/chk_autoobs//k5ts2/ autoobs is running! 2006.173.21:56:50.34/chk_autoobs//k5ts3/ autoobs is running! 2006.173.21:56:50.74/chk_autoobs//k5ts4/ autoobs is running! 2006.173.21:56:51.13/chk_obsdata//k5ts1/T1732152??a.dat file size is correct (nominal:1000MB, actual:996MB). 2006.173.21:56:51.53/chk_obsdata//k5ts2/T1732152??b.dat file size is correct (nominal:1000MB, actual:996MB). 2006.173.21:56:51.94/chk_obsdata//k5ts3/T1732152??c.dat file size is correct (nominal:1000MB, actual:996MB). 2006.173.21:56:52.35/chk_obsdata//k5ts4/T1732152??d.dat file size is correct (nominal:1000MB, actual:996MB). 2006.173.21:56:53.05/k5log//k5ts1_log_newline 2006.173.21:56:53.70/k5log//k5ts2_log_newline 2006.173.21:56:54.45/k5log//k5ts3_log_newline 2006.173.21:56:55.16/k5log//k5ts4_log_newline 2006.173.21:56:55.18/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.21:56:55.18:setupk4=1 2006.173.21:56:55.18$setupk4/echo=on 2006.173.21:56:55.18$setupk4/pcalon 2006.173.21:56:55.19$pcalon/"no phase cal control is implemented here 2006.173.21:56:55.19$setupk4/"tpicd=stop 2006.173.21:56:55.19$setupk4/"rec=synch_on 2006.173.21:56:55.19$setupk4/"rec_mode=128 2006.173.21:56:55.19$setupk4/!* 2006.173.21:56:55.19$setupk4/recpk4 2006.173.21:56:55.19$recpk4/recpatch= 2006.173.21:56:55.19$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.21:56:55.19$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.21:56:55.19$setupk4/vck44 2006.173.21:56:55.19$vck44/valo=1,524.99 2006.173.21:56:55.19#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.21:56:55.19#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.21:56:55.19#ibcon#ireg 17 cls_cnt 0 2006.173.21:56:55.19#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.21:56:55.19#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.21:56:55.19#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.21:56:55.19#ibcon#enter wrdev, iclass 34, count 0 2006.173.21:56:55.19#ibcon#first serial, iclass 34, count 0 2006.173.21:56:55.19#ibcon#enter sib2, iclass 34, count 0 2006.173.21:56:55.19#ibcon#flushed, iclass 34, count 0 2006.173.21:56:55.19#ibcon#about to write, iclass 34, count 0 2006.173.21:56:55.19#ibcon#wrote, iclass 34, count 0 2006.173.21:56:55.19#ibcon#about to read 3, iclass 34, count 0 2006.173.21:56:55.20#ibcon#read 3, iclass 34, count 0 2006.173.21:56:55.20#ibcon#about to read 4, iclass 34, count 0 2006.173.21:56:55.20#ibcon#read 4, iclass 34, count 0 2006.173.21:56:55.20#ibcon#about to read 5, iclass 34, count 0 2006.173.21:56:55.20#ibcon#read 5, iclass 34, count 0 2006.173.21:56:55.20#ibcon#about to read 6, iclass 34, count 0 2006.173.21:56:55.20#ibcon#read 6, iclass 34, count 0 2006.173.21:56:55.20#ibcon#end of sib2, iclass 34, count 0 2006.173.21:56:55.20#ibcon#*mode == 0, iclass 34, count 0 2006.173.21:56:55.20#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.21:56:55.20#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.21:56:55.20#ibcon#*before write, iclass 34, count 0 2006.173.21:56:55.20#ibcon#enter sib2, iclass 34, count 0 2006.173.21:56:55.20#ibcon#flushed, iclass 34, count 0 2006.173.21:56:55.20#ibcon#about to write, iclass 34, count 0 2006.173.21:56:55.20#ibcon#wrote, iclass 34, count 0 2006.173.21:56:55.20#ibcon#about to read 3, iclass 34, count 0 2006.173.21:56:55.25#ibcon#read 3, iclass 34, count 0 2006.173.21:56:55.25#ibcon#about to read 4, iclass 34, count 0 2006.173.21:56:55.25#ibcon#read 4, iclass 34, count 0 2006.173.21:56:55.25#ibcon#about to read 5, iclass 34, count 0 2006.173.21:56:55.25#ibcon#read 5, iclass 34, count 0 2006.173.21:56:55.25#ibcon#about to read 6, iclass 34, count 0 2006.173.21:56:55.25#ibcon#read 6, iclass 34, count 0 2006.173.21:56:55.25#ibcon#end of sib2, iclass 34, count 0 2006.173.21:56:55.25#ibcon#*after write, iclass 34, count 0 2006.173.21:56:55.25#ibcon#*before return 0, iclass 34, count 0 2006.173.21:56:55.25#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.21:56:55.25#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.21:56:55.25#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.21:56:55.25#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.21:56:55.25$vck44/va=1,7 2006.173.21:56:55.25#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.21:56:55.25#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.21:56:55.25#ibcon#ireg 11 cls_cnt 2 2006.173.21:56:55.25#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.21:56:55.25#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.21:56:55.25#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.21:56:55.25#ibcon#enter wrdev, iclass 36, count 2 2006.173.21:56:55.25#ibcon#first serial, iclass 36, count 2 2006.173.21:56:55.25#ibcon#enter sib2, iclass 36, count 2 2006.173.21:56:55.25#ibcon#flushed, iclass 36, count 2 2006.173.21:56:55.25#ibcon#about to write, iclass 36, count 2 2006.173.21:56:55.25#ibcon#wrote, iclass 36, count 2 2006.173.21:56:55.25#ibcon#about to read 3, iclass 36, count 2 2006.173.21:56:55.27#ibcon#read 3, iclass 36, count 2 2006.173.21:56:55.27#ibcon#about to read 4, iclass 36, count 2 2006.173.21:56:55.27#ibcon#read 4, iclass 36, count 2 2006.173.21:56:55.27#ibcon#about to read 5, iclass 36, count 2 2006.173.21:56:55.27#ibcon#read 5, iclass 36, count 2 2006.173.21:56:55.27#ibcon#about to read 6, iclass 36, count 2 2006.173.21:56:55.27#ibcon#read 6, iclass 36, count 2 2006.173.21:56:55.27#ibcon#end of sib2, iclass 36, count 2 2006.173.21:56:55.27#ibcon#*mode == 0, iclass 36, count 2 2006.173.21:56:55.27#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.21:56:55.27#ibcon#[25=AT01-07\r\n] 2006.173.21:56:55.27#ibcon#*before write, iclass 36, count 2 2006.173.21:56:55.27#ibcon#enter sib2, iclass 36, count 2 2006.173.21:56:55.27#ibcon#flushed, iclass 36, count 2 2006.173.21:56:55.27#ibcon#about to write, iclass 36, count 2 2006.173.21:56:55.27#ibcon#wrote, iclass 36, count 2 2006.173.21:56:55.27#ibcon#about to read 3, iclass 36, count 2 2006.173.21:56:55.30#ibcon#read 3, iclass 36, count 2 2006.173.21:56:55.30#ibcon#about to read 4, iclass 36, count 2 2006.173.21:56:55.30#ibcon#read 4, iclass 36, count 2 2006.173.21:56:55.30#ibcon#about to read 5, iclass 36, count 2 2006.173.21:56:55.30#ibcon#read 5, iclass 36, count 2 2006.173.21:56:55.30#ibcon#about to read 6, iclass 36, count 2 2006.173.21:56:55.30#ibcon#read 6, iclass 36, count 2 2006.173.21:56:55.30#ibcon#end of sib2, iclass 36, count 2 2006.173.21:56:55.30#ibcon#*after write, iclass 36, count 2 2006.173.21:56:55.30#ibcon#*before return 0, iclass 36, count 2 2006.173.21:56:55.30#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.21:56:55.30#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.21:56:55.30#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.21:56:55.30#ibcon#ireg 7 cls_cnt 0 2006.173.21:56:55.30#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.21:56:55.42#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.21:56:55.42#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.21:56:55.42#ibcon#enter wrdev, iclass 36, count 0 2006.173.21:56:55.42#ibcon#first serial, iclass 36, count 0 2006.173.21:56:55.42#ibcon#enter sib2, iclass 36, count 0 2006.173.21:56:55.42#ibcon#flushed, iclass 36, count 0 2006.173.21:56:55.42#ibcon#about to write, iclass 36, count 0 2006.173.21:56:55.42#ibcon#wrote, iclass 36, count 0 2006.173.21:56:55.42#ibcon#about to read 3, iclass 36, count 0 2006.173.21:56:55.44#ibcon#read 3, iclass 36, count 0 2006.173.21:56:55.44#ibcon#about to read 4, iclass 36, count 0 2006.173.21:56:55.44#ibcon#read 4, iclass 36, count 0 2006.173.21:56:55.44#ibcon#about to read 5, iclass 36, count 0 2006.173.21:56:55.44#ibcon#read 5, iclass 36, count 0 2006.173.21:56:55.44#ibcon#about to read 6, iclass 36, count 0 2006.173.21:56:55.44#ibcon#read 6, iclass 36, count 0 2006.173.21:56:55.44#ibcon#end of sib2, iclass 36, count 0 2006.173.21:56:55.44#ibcon#*mode == 0, iclass 36, count 0 2006.173.21:56:55.44#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.21:56:55.44#ibcon#[25=USB\r\n] 2006.173.21:56:55.44#ibcon#*before write, iclass 36, count 0 2006.173.21:56:55.44#ibcon#enter sib2, iclass 36, count 0 2006.173.21:56:55.44#ibcon#flushed, iclass 36, count 0 2006.173.21:56:55.44#ibcon#about to write, iclass 36, count 0 2006.173.21:56:55.44#ibcon#wrote, iclass 36, count 0 2006.173.21:56:55.44#ibcon#about to read 3, iclass 36, count 0 2006.173.21:56:55.47#ibcon#read 3, iclass 36, count 0 2006.173.21:56:55.47#ibcon#about to read 4, iclass 36, count 0 2006.173.21:56:55.47#ibcon#read 4, iclass 36, count 0 2006.173.21:56:55.47#ibcon#about to read 5, iclass 36, count 0 2006.173.21:56:55.47#ibcon#read 5, iclass 36, count 0 2006.173.21:56:55.47#ibcon#about to read 6, iclass 36, count 0 2006.173.21:56:55.47#ibcon#read 6, iclass 36, count 0 2006.173.21:56:55.47#ibcon#end of sib2, iclass 36, count 0 2006.173.21:56:55.47#ibcon#*after write, iclass 36, count 0 2006.173.21:56:55.47#ibcon#*before return 0, iclass 36, count 0 2006.173.21:56:55.47#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.21:56:55.47#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.21:56:55.47#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.21:56:55.47#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.21:56:55.47$vck44/valo=2,534.99 2006.173.21:56:55.47#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.21:56:55.47#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.21:56:55.47#ibcon#ireg 17 cls_cnt 0 2006.173.21:56:55.47#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.21:56:55.47#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.21:56:55.47#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.21:56:55.47#ibcon#enter wrdev, iclass 38, count 0 2006.173.21:56:55.47#ibcon#first serial, iclass 38, count 0 2006.173.21:56:55.47#ibcon#enter sib2, iclass 38, count 0 2006.173.21:56:55.47#ibcon#flushed, iclass 38, count 0 2006.173.21:56:55.47#ibcon#about to write, iclass 38, count 0 2006.173.21:56:55.47#ibcon#wrote, iclass 38, count 0 2006.173.21:56:55.47#ibcon#about to read 3, iclass 38, count 0 2006.173.21:56:55.49#ibcon#read 3, iclass 38, count 0 2006.173.21:56:55.49#ibcon#about to read 4, iclass 38, count 0 2006.173.21:56:55.49#ibcon#read 4, iclass 38, count 0 2006.173.21:56:55.49#ibcon#about to read 5, iclass 38, count 0 2006.173.21:56:55.49#ibcon#read 5, iclass 38, count 0 2006.173.21:56:55.49#ibcon#about to read 6, iclass 38, count 0 2006.173.21:56:55.49#ibcon#read 6, iclass 38, count 0 2006.173.21:56:55.49#ibcon#end of sib2, iclass 38, count 0 2006.173.21:56:55.49#ibcon#*mode == 0, iclass 38, count 0 2006.173.21:56:55.49#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.21:56:55.49#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.21:56:55.49#ibcon#*before write, iclass 38, count 0 2006.173.21:56:55.49#ibcon#enter sib2, iclass 38, count 0 2006.173.21:56:55.49#ibcon#flushed, iclass 38, count 0 2006.173.21:56:55.49#ibcon#about to write, iclass 38, count 0 2006.173.21:56:55.49#ibcon#wrote, iclass 38, count 0 2006.173.21:56:55.49#ibcon#about to read 3, iclass 38, count 0 2006.173.21:56:55.53#ibcon#read 3, iclass 38, count 0 2006.173.21:56:55.53#ibcon#about to read 4, iclass 38, count 0 2006.173.21:56:55.53#ibcon#read 4, iclass 38, count 0 2006.173.21:56:55.53#ibcon#about to read 5, iclass 38, count 0 2006.173.21:56:55.53#ibcon#read 5, iclass 38, count 0 2006.173.21:56:55.53#ibcon#about to read 6, iclass 38, count 0 2006.173.21:56:55.53#ibcon#read 6, iclass 38, count 0 2006.173.21:56:55.53#ibcon#end of sib2, iclass 38, count 0 2006.173.21:56:55.53#ibcon#*after write, iclass 38, count 0 2006.173.21:56:55.53#ibcon#*before return 0, iclass 38, count 0 2006.173.21:56:55.53#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.21:56:55.53#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.21:56:55.53#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.21:56:55.53#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.21:56:55.53$vck44/va=2,6 2006.173.21:56:55.53#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.21:56:55.53#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.21:56:55.53#ibcon#ireg 11 cls_cnt 2 2006.173.21:56:55.53#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.21:56:55.59#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.21:56:55.59#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.21:56:55.59#ibcon#enter wrdev, iclass 40, count 2 2006.173.21:56:55.59#ibcon#first serial, iclass 40, count 2 2006.173.21:56:55.59#ibcon#enter sib2, iclass 40, count 2 2006.173.21:56:55.59#ibcon#flushed, iclass 40, count 2 2006.173.21:56:55.59#ibcon#about to write, iclass 40, count 2 2006.173.21:56:55.59#ibcon#wrote, iclass 40, count 2 2006.173.21:56:55.59#ibcon#about to read 3, iclass 40, count 2 2006.173.21:56:55.61#ibcon#read 3, iclass 40, count 2 2006.173.21:56:55.61#ibcon#about to read 4, iclass 40, count 2 2006.173.21:56:55.61#ibcon#read 4, iclass 40, count 2 2006.173.21:56:55.61#ibcon#about to read 5, iclass 40, count 2 2006.173.21:56:55.61#ibcon#read 5, iclass 40, count 2 2006.173.21:56:55.61#ibcon#about to read 6, iclass 40, count 2 2006.173.21:56:55.61#ibcon#read 6, iclass 40, count 2 2006.173.21:56:55.61#ibcon#end of sib2, iclass 40, count 2 2006.173.21:56:55.61#ibcon#*mode == 0, iclass 40, count 2 2006.173.21:56:55.61#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.21:56:55.61#ibcon#[25=AT02-06\r\n] 2006.173.21:56:55.61#ibcon#*before write, iclass 40, count 2 2006.173.21:56:55.61#ibcon#enter sib2, iclass 40, count 2 2006.173.21:56:55.61#ibcon#flushed, iclass 40, count 2 2006.173.21:56:55.61#ibcon#about to write, iclass 40, count 2 2006.173.21:56:55.61#ibcon#wrote, iclass 40, count 2 2006.173.21:56:55.61#ibcon#about to read 3, iclass 40, count 2 2006.173.21:56:55.64#ibcon#read 3, iclass 40, count 2 2006.173.21:56:55.64#ibcon#about to read 4, iclass 40, count 2 2006.173.21:56:55.64#ibcon#read 4, iclass 40, count 2 2006.173.21:56:55.64#ibcon#about to read 5, iclass 40, count 2 2006.173.21:56:55.64#ibcon#read 5, iclass 40, count 2 2006.173.21:56:55.64#ibcon#about to read 6, iclass 40, count 2 2006.173.21:56:55.64#ibcon#read 6, iclass 40, count 2 2006.173.21:56:55.64#ibcon#end of sib2, iclass 40, count 2 2006.173.21:56:55.64#ibcon#*after write, iclass 40, count 2 2006.173.21:56:55.64#ibcon#*before return 0, iclass 40, count 2 2006.173.21:56:55.64#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.21:56:55.64#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.21:56:55.64#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.21:56:55.64#ibcon#ireg 7 cls_cnt 0 2006.173.21:56:55.64#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.21:56:55.76#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.21:56:55.76#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.21:56:55.76#ibcon#enter wrdev, iclass 40, count 0 2006.173.21:56:55.76#ibcon#first serial, iclass 40, count 0 2006.173.21:56:55.76#ibcon#enter sib2, iclass 40, count 0 2006.173.21:56:55.76#ibcon#flushed, iclass 40, count 0 2006.173.21:56:55.76#ibcon#about to write, iclass 40, count 0 2006.173.21:56:55.76#ibcon#wrote, iclass 40, count 0 2006.173.21:56:55.76#ibcon#about to read 3, iclass 40, count 0 2006.173.21:56:55.78#ibcon#read 3, iclass 40, count 0 2006.173.21:56:55.78#ibcon#about to read 4, iclass 40, count 0 2006.173.21:56:55.78#ibcon#read 4, iclass 40, count 0 2006.173.21:56:55.78#ibcon#about to read 5, iclass 40, count 0 2006.173.21:56:55.78#ibcon#read 5, iclass 40, count 0 2006.173.21:56:55.78#ibcon#about to read 6, iclass 40, count 0 2006.173.21:56:55.78#ibcon#read 6, iclass 40, count 0 2006.173.21:56:55.78#ibcon#end of sib2, iclass 40, count 0 2006.173.21:56:55.78#ibcon#*mode == 0, iclass 40, count 0 2006.173.21:56:55.78#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.21:56:55.78#ibcon#[25=USB\r\n] 2006.173.21:56:55.78#ibcon#*before write, iclass 40, count 0 2006.173.21:56:55.78#ibcon#enter sib2, iclass 40, count 0 2006.173.21:56:55.78#ibcon#flushed, iclass 40, count 0 2006.173.21:56:55.78#ibcon#about to write, iclass 40, count 0 2006.173.21:56:55.78#ibcon#wrote, iclass 40, count 0 2006.173.21:56:55.78#ibcon#about to read 3, iclass 40, count 0 2006.173.21:56:55.81#ibcon#read 3, iclass 40, count 0 2006.173.21:56:55.81#ibcon#about to read 4, iclass 40, count 0 2006.173.21:56:55.81#ibcon#read 4, iclass 40, count 0 2006.173.21:56:55.81#ibcon#about to read 5, iclass 40, count 0 2006.173.21:56:55.81#ibcon#read 5, iclass 40, count 0 2006.173.21:56:55.81#ibcon#about to read 6, iclass 40, count 0 2006.173.21:56:55.81#ibcon#read 6, iclass 40, count 0 2006.173.21:56:55.81#ibcon#end of sib2, iclass 40, count 0 2006.173.21:56:55.81#ibcon#*after write, iclass 40, count 0 2006.173.21:56:55.81#ibcon#*before return 0, iclass 40, count 0 2006.173.21:56:55.81#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.21:56:55.81#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.21:56:55.81#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.21:56:55.81#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.21:56:55.81$vck44/valo=3,564.99 2006.173.21:56:55.81#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.21:56:55.81#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.21:56:55.81#ibcon#ireg 17 cls_cnt 0 2006.173.21:56:55.81#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.21:56:55.81#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.21:56:55.81#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.21:56:55.81#ibcon#enter wrdev, iclass 4, count 0 2006.173.21:56:55.81#ibcon#first serial, iclass 4, count 0 2006.173.21:56:55.81#ibcon#enter sib2, iclass 4, count 0 2006.173.21:56:55.81#ibcon#flushed, iclass 4, count 0 2006.173.21:56:55.81#ibcon#about to write, iclass 4, count 0 2006.173.21:56:55.81#ibcon#wrote, iclass 4, count 0 2006.173.21:56:55.81#ibcon#about to read 3, iclass 4, count 0 2006.173.21:56:55.83#ibcon#read 3, iclass 4, count 0 2006.173.21:56:55.83#ibcon#about to read 4, iclass 4, count 0 2006.173.21:56:55.83#ibcon#read 4, iclass 4, count 0 2006.173.21:56:55.83#ibcon#about to read 5, iclass 4, count 0 2006.173.21:56:55.83#ibcon#read 5, iclass 4, count 0 2006.173.21:56:55.83#ibcon#about to read 6, iclass 4, count 0 2006.173.21:56:55.83#ibcon#read 6, iclass 4, count 0 2006.173.21:56:55.83#ibcon#end of sib2, iclass 4, count 0 2006.173.21:56:55.83#ibcon#*mode == 0, iclass 4, count 0 2006.173.21:56:55.83#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.21:56:55.83#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.21:56:55.83#ibcon#*before write, iclass 4, count 0 2006.173.21:56:55.83#ibcon#enter sib2, iclass 4, count 0 2006.173.21:56:55.83#ibcon#flushed, iclass 4, count 0 2006.173.21:56:55.83#ibcon#about to write, iclass 4, count 0 2006.173.21:56:55.83#ibcon#wrote, iclass 4, count 0 2006.173.21:56:55.83#ibcon#about to read 3, iclass 4, count 0 2006.173.21:56:55.87#ibcon#read 3, iclass 4, count 0 2006.173.21:56:55.87#ibcon#about to read 4, iclass 4, count 0 2006.173.21:56:55.87#ibcon#read 4, iclass 4, count 0 2006.173.21:56:55.87#ibcon#about to read 5, iclass 4, count 0 2006.173.21:56:55.87#ibcon#read 5, iclass 4, count 0 2006.173.21:56:55.87#ibcon#about to read 6, iclass 4, count 0 2006.173.21:56:55.87#ibcon#read 6, iclass 4, count 0 2006.173.21:56:55.87#ibcon#end of sib2, iclass 4, count 0 2006.173.21:56:55.87#ibcon#*after write, iclass 4, count 0 2006.173.21:56:55.87#ibcon#*before return 0, iclass 4, count 0 2006.173.21:56:55.87#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.21:56:55.87#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.21:56:55.87#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.21:56:55.87#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.21:56:55.87$vck44/va=3,5 2006.173.21:56:55.87#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.21:56:55.87#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.21:56:55.87#ibcon#ireg 11 cls_cnt 2 2006.173.21:56:55.87#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.21:56:55.93#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.21:56:55.93#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.21:56:55.93#ibcon#enter wrdev, iclass 6, count 2 2006.173.21:56:55.93#ibcon#first serial, iclass 6, count 2 2006.173.21:56:55.93#ibcon#enter sib2, iclass 6, count 2 2006.173.21:56:55.93#ibcon#flushed, iclass 6, count 2 2006.173.21:56:55.93#ibcon#about to write, iclass 6, count 2 2006.173.21:56:55.93#ibcon#wrote, iclass 6, count 2 2006.173.21:56:55.93#ibcon#about to read 3, iclass 6, count 2 2006.173.21:56:55.95#ibcon#read 3, iclass 6, count 2 2006.173.21:56:55.95#ibcon#about to read 4, iclass 6, count 2 2006.173.21:56:55.95#ibcon#read 4, iclass 6, count 2 2006.173.21:56:55.95#ibcon#about to read 5, iclass 6, count 2 2006.173.21:56:55.95#ibcon#read 5, iclass 6, count 2 2006.173.21:56:55.95#ibcon#about to read 6, iclass 6, count 2 2006.173.21:56:55.95#ibcon#read 6, iclass 6, count 2 2006.173.21:56:55.95#ibcon#end of sib2, iclass 6, count 2 2006.173.21:56:55.95#ibcon#*mode == 0, iclass 6, count 2 2006.173.21:56:55.95#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.21:56:55.95#ibcon#[25=AT03-05\r\n] 2006.173.21:56:55.95#ibcon#*before write, iclass 6, count 2 2006.173.21:56:55.95#ibcon#enter sib2, iclass 6, count 2 2006.173.21:56:55.95#ibcon#flushed, iclass 6, count 2 2006.173.21:56:55.95#ibcon#about to write, iclass 6, count 2 2006.173.21:56:55.95#ibcon#wrote, iclass 6, count 2 2006.173.21:56:55.95#ibcon#about to read 3, iclass 6, count 2 2006.173.21:56:55.98#ibcon#read 3, iclass 6, count 2 2006.173.21:56:55.98#ibcon#about to read 4, iclass 6, count 2 2006.173.21:56:55.98#ibcon#read 4, iclass 6, count 2 2006.173.21:56:55.98#ibcon#about to read 5, iclass 6, count 2 2006.173.21:56:55.98#ibcon#read 5, iclass 6, count 2 2006.173.21:56:55.98#ibcon#about to read 6, iclass 6, count 2 2006.173.21:56:55.98#ibcon#read 6, iclass 6, count 2 2006.173.21:56:55.98#ibcon#end of sib2, iclass 6, count 2 2006.173.21:56:55.98#ibcon#*after write, iclass 6, count 2 2006.173.21:56:55.98#ibcon#*before return 0, iclass 6, count 2 2006.173.21:56:55.98#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.21:56:55.98#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.21:56:55.98#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.21:56:55.98#ibcon#ireg 7 cls_cnt 0 2006.173.21:56:55.98#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.21:56:56.10#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.21:56:56.10#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.21:56:56.10#ibcon#enter wrdev, iclass 6, count 0 2006.173.21:56:56.10#ibcon#first serial, iclass 6, count 0 2006.173.21:56:56.10#ibcon#enter sib2, iclass 6, count 0 2006.173.21:56:56.10#ibcon#flushed, iclass 6, count 0 2006.173.21:56:56.10#ibcon#about to write, iclass 6, count 0 2006.173.21:56:56.10#ibcon#wrote, iclass 6, count 0 2006.173.21:56:56.10#ibcon#about to read 3, iclass 6, count 0 2006.173.21:56:56.12#ibcon#read 3, iclass 6, count 0 2006.173.21:56:56.12#ibcon#about to read 4, iclass 6, count 0 2006.173.21:56:56.12#ibcon#read 4, iclass 6, count 0 2006.173.21:56:56.12#ibcon#about to read 5, iclass 6, count 0 2006.173.21:56:56.12#ibcon#read 5, iclass 6, count 0 2006.173.21:56:56.12#ibcon#about to read 6, iclass 6, count 0 2006.173.21:56:56.12#ibcon#read 6, iclass 6, count 0 2006.173.21:56:56.12#ibcon#end of sib2, iclass 6, count 0 2006.173.21:56:56.12#ibcon#*mode == 0, iclass 6, count 0 2006.173.21:56:56.12#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.21:56:56.12#ibcon#[25=USB\r\n] 2006.173.21:56:56.12#ibcon#*before write, iclass 6, count 0 2006.173.21:56:56.12#ibcon#enter sib2, iclass 6, count 0 2006.173.21:56:56.12#ibcon#flushed, iclass 6, count 0 2006.173.21:56:56.12#ibcon#about to write, iclass 6, count 0 2006.173.21:56:56.12#ibcon#wrote, iclass 6, count 0 2006.173.21:56:56.12#ibcon#about to read 3, iclass 6, count 0 2006.173.21:56:56.15#ibcon#read 3, iclass 6, count 0 2006.173.21:56:56.15#ibcon#about to read 4, iclass 6, count 0 2006.173.21:56:56.15#ibcon#read 4, iclass 6, count 0 2006.173.21:56:56.15#ibcon#about to read 5, iclass 6, count 0 2006.173.21:56:56.15#ibcon#read 5, iclass 6, count 0 2006.173.21:56:56.15#ibcon#about to read 6, iclass 6, count 0 2006.173.21:56:56.15#ibcon#read 6, iclass 6, count 0 2006.173.21:56:56.15#ibcon#end of sib2, iclass 6, count 0 2006.173.21:56:56.15#ibcon#*after write, iclass 6, count 0 2006.173.21:56:56.15#ibcon#*before return 0, iclass 6, count 0 2006.173.21:56:56.15#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.21:56:56.15#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.21:56:56.15#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.21:56:56.15#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.21:56:56.15$vck44/valo=4,624.99 2006.173.21:56:56.15#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.21:56:56.15#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.21:56:56.15#ibcon#ireg 17 cls_cnt 0 2006.173.21:56:56.15#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.21:56:56.15#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.21:56:56.15#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.21:56:56.15#ibcon#enter wrdev, iclass 10, count 0 2006.173.21:56:56.15#ibcon#first serial, iclass 10, count 0 2006.173.21:56:56.15#ibcon#enter sib2, iclass 10, count 0 2006.173.21:56:56.15#ibcon#flushed, iclass 10, count 0 2006.173.21:56:56.15#ibcon#about to write, iclass 10, count 0 2006.173.21:56:56.15#ibcon#wrote, iclass 10, count 0 2006.173.21:56:56.15#ibcon#about to read 3, iclass 10, count 0 2006.173.21:56:56.17#ibcon#read 3, iclass 10, count 0 2006.173.21:56:56.17#ibcon#about to read 4, iclass 10, count 0 2006.173.21:56:56.17#ibcon#read 4, iclass 10, count 0 2006.173.21:56:56.17#ibcon#about to read 5, iclass 10, count 0 2006.173.21:56:56.17#ibcon#read 5, iclass 10, count 0 2006.173.21:56:56.17#ibcon#about to read 6, iclass 10, count 0 2006.173.21:56:56.17#ibcon#read 6, iclass 10, count 0 2006.173.21:56:56.17#ibcon#end of sib2, iclass 10, count 0 2006.173.21:56:56.17#ibcon#*mode == 0, iclass 10, count 0 2006.173.21:56:56.17#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.21:56:56.17#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.21:56:56.17#ibcon#*before write, iclass 10, count 0 2006.173.21:56:56.17#ibcon#enter sib2, iclass 10, count 0 2006.173.21:56:56.17#ibcon#flushed, iclass 10, count 0 2006.173.21:56:56.17#ibcon#about to write, iclass 10, count 0 2006.173.21:56:56.17#ibcon#wrote, iclass 10, count 0 2006.173.21:56:56.17#ibcon#about to read 3, iclass 10, count 0 2006.173.21:56:56.21#ibcon#read 3, iclass 10, count 0 2006.173.21:56:56.21#ibcon#about to read 4, iclass 10, count 0 2006.173.21:56:56.21#ibcon#read 4, iclass 10, count 0 2006.173.21:56:56.21#ibcon#about to read 5, iclass 10, count 0 2006.173.21:56:56.21#ibcon#read 5, iclass 10, count 0 2006.173.21:56:56.21#ibcon#about to read 6, iclass 10, count 0 2006.173.21:56:56.21#ibcon#read 6, iclass 10, count 0 2006.173.21:56:56.21#ibcon#end of sib2, iclass 10, count 0 2006.173.21:56:56.21#ibcon#*after write, iclass 10, count 0 2006.173.21:56:56.21#ibcon#*before return 0, iclass 10, count 0 2006.173.21:56:56.21#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.21:56:56.21#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.21:56:56.21#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.21:56:56.21#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.21:56:56.21$vck44/va=4,6 2006.173.21:56:56.21#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.21:56:56.21#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.21:56:56.21#ibcon#ireg 11 cls_cnt 2 2006.173.21:56:56.21#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.21:56:56.27#abcon#<5=/00 0.2 1.0 21.67 981003.3\r\n> 2006.173.21:56:56.27#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.21:56:56.27#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.21:56:56.27#ibcon#enter wrdev, iclass 12, count 2 2006.173.21:56:56.27#ibcon#first serial, iclass 12, count 2 2006.173.21:56:56.27#ibcon#enter sib2, iclass 12, count 2 2006.173.21:56:56.27#ibcon#flushed, iclass 12, count 2 2006.173.21:56:56.27#ibcon#about to write, iclass 12, count 2 2006.173.21:56:56.27#ibcon#wrote, iclass 12, count 2 2006.173.21:56:56.27#ibcon#about to read 3, iclass 12, count 2 2006.173.21:56:56.29#ibcon#read 3, iclass 12, count 2 2006.173.21:56:56.29#ibcon#about to read 4, iclass 12, count 2 2006.173.21:56:56.29#ibcon#read 4, iclass 12, count 2 2006.173.21:56:56.29#ibcon#about to read 5, iclass 12, count 2 2006.173.21:56:56.29#ibcon#read 5, iclass 12, count 2 2006.173.21:56:56.29#ibcon#about to read 6, iclass 12, count 2 2006.173.21:56:56.29#ibcon#read 6, iclass 12, count 2 2006.173.21:56:56.29#ibcon#end of sib2, iclass 12, count 2 2006.173.21:56:56.29#ibcon#*mode == 0, iclass 12, count 2 2006.173.21:56:56.29#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.21:56:56.29#ibcon#[25=AT04-06\r\n] 2006.173.21:56:56.29#ibcon#*before write, iclass 12, count 2 2006.173.21:56:56.29#ibcon#enter sib2, iclass 12, count 2 2006.173.21:56:56.29#ibcon#flushed, iclass 12, count 2 2006.173.21:56:56.29#ibcon#about to write, iclass 12, count 2 2006.173.21:56:56.29#ibcon#wrote, iclass 12, count 2 2006.173.21:56:56.29#ibcon#about to read 3, iclass 12, count 2 2006.173.21:56:56.29#abcon#{5=INTERFACE CLEAR} 2006.173.21:56:56.32#ibcon#read 3, iclass 12, count 2 2006.173.21:56:56.32#ibcon#about to read 4, iclass 12, count 2 2006.173.21:56:56.32#ibcon#read 4, iclass 12, count 2 2006.173.21:56:56.32#ibcon#about to read 5, iclass 12, count 2 2006.173.21:56:56.32#ibcon#read 5, iclass 12, count 2 2006.173.21:56:56.32#ibcon#about to read 6, iclass 12, count 2 2006.173.21:56:56.32#ibcon#read 6, iclass 12, count 2 2006.173.21:56:56.32#ibcon#end of sib2, iclass 12, count 2 2006.173.21:56:56.32#ibcon#*after write, iclass 12, count 2 2006.173.21:56:56.32#ibcon#*before return 0, iclass 12, count 2 2006.173.21:56:56.32#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.21:56:56.32#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.21:56:56.32#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.21:56:56.32#ibcon#ireg 7 cls_cnt 0 2006.173.21:56:56.32#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.21:56:56.35#abcon#[5=S1D000X0/0*\r\n] 2006.173.21:56:56.44#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.21:56:56.44#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.21:56:56.44#ibcon#enter wrdev, iclass 12, count 0 2006.173.21:56:56.44#ibcon#first serial, iclass 12, count 0 2006.173.21:56:56.44#ibcon#enter sib2, iclass 12, count 0 2006.173.21:56:56.44#ibcon#flushed, iclass 12, count 0 2006.173.21:56:56.44#ibcon#about to write, iclass 12, count 0 2006.173.21:56:56.44#ibcon#wrote, iclass 12, count 0 2006.173.21:56:56.44#ibcon#about to read 3, iclass 12, count 0 2006.173.21:56:56.46#ibcon#read 3, iclass 12, count 0 2006.173.21:56:56.46#ibcon#about to read 4, iclass 12, count 0 2006.173.21:56:56.46#ibcon#read 4, iclass 12, count 0 2006.173.21:56:56.46#ibcon#about to read 5, iclass 12, count 0 2006.173.21:56:56.46#ibcon#read 5, iclass 12, count 0 2006.173.21:56:56.46#ibcon#about to read 6, iclass 12, count 0 2006.173.21:56:56.46#ibcon#read 6, iclass 12, count 0 2006.173.21:56:56.46#ibcon#end of sib2, iclass 12, count 0 2006.173.21:56:56.46#ibcon#*mode == 0, iclass 12, count 0 2006.173.21:56:56.46#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.21:56:56.46#ibcon#[25=USB\r\n] 2006.173.21:56:56.46#ibcon#*before write, iclass 12, count 0 2006.173.21:56:56.46#ibcon#enter sib2, iclass 12, count 0 2006.173.21:56:56.46#ibcon#flushed, iclass 12, count 0 2006.173.21:56:56.46#ibcon#about to write, iclass 12, count 0 2006.173.21:56:56.46#ibcon#wrote, iclass 12, count 0 2006.173.21:56:56.46#ibcon#about to read 3, iclass 12, count 0 2006.173.21:56:56.49#ibcon#read 3, iclass 12, count 0 2006.173.21:56:56.49#ibcon#about to read 4, iclass 12, count 0 2006.173.21:56:56.49#ibcon#read 4, iclass 12, count 0 2006.173.21:56:56.49#ibcon#about to read 5, iclass 12, count 0 2006.173.21:56:56.49#ibcon#read 5, iclass 12, count 0 2006.173.21:56:56.49#ibcon#about to read 6, iclass 12, count 0 2006.173.21:56:56.49#ibcon#read 6, iclass 12, count 0 2006.173.21:56:56.49#ibcon#end of sib2, iclass 12, count 0 2006.173.21:56:56.49#ibcon#*after write, iclass 12, count 0 2006.173.21:56:56.49#ibcon#*before return 0, iclass 12, count 0 2006.173.21:56:56.49#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.21:56:56.49#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.21:56:56.49#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.21:56:56.49#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.21:56:56.49$vck44/valo=5,734.99 2006.173.21:56:56.49#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.21:56:56.49#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.21:56:56.49#ibcon#ireg 17 cls_cnt 0 2006.173.21:56:56.49#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.21:56:56.49#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.21:56:56.49#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.21:56:56.49#ibcon#enter wrdev, iclass 18, count 0 2006.173.21:56:56.49#ibcon#first serial, iclass 18, count 0 2006.173.21:56:56.49#ibcon#enter sib2, iclass 18, count 0 2006.173.21:56:56.49#ibcon#flushed, iclass 18, count 0 2006.173.21:56:56.49#ibcon#about to write, iclass 18, count 0 2006.173.21:56:56.49#ibcon#wrote, iclass 18, count 0 2006.173.21:56:56.49#ibcon#about to read 3, iclass 18, count 0 2006.173.21:56:56.51#ibcon#read 3, iclass 18, count 0 2006.173.21:56:56.51#ibcon#about to read 4, iclass 18, count 0 2006.173.21:56:56.51#ibcon#read 4, iclass 18, count 0 2006.173.21:56:56.51#ibcon#about to read 5, iclass 18, count 0 2006.173.21:56:56.51#ibcon#read 5, iclass 18, count 0 2006.173.21:56:56.51#ibcon#about to read 6, iclass 18, count 0 2006.173.21:56:56.51#ibcon#read 6, iclass 18, count 0 2006.173.21:56:56.51#ibcon#end of sib2, iclass 18, count 0 2006.173.21:56:56.51#ibcon#*mode == 0, iclass 18, count 0 2006.173.21:56:56.51#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.21:56:56.51#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.21:56:56.51#ibcon#*before write, iclass 18, count 0 2006.173.21:56:56.51#ibcon#enter sib2, iclass 18, count 0 2006.173.21:56:56.51#ibcon#flushed, iclass 18, count 0 2006.173.21:56:56.51#ibcon#about to write, iclass 18, count 0 2006.173.21:56:56.51#ibcon#wrote, iclass 18, count 0 2006.173.21:56:56.51#ibcon#about to read 3, iclass 18, count 0 2006.173.21:56:56.55#ibcon#read 3, iclass 18, count 0 2006.173.21:56:56.55#ibcon#about to read 4, iclass 18, count 0 2006.173.21:56:56.55#ibcon#read 4, iclass 18, count 0 2006.173.21:56:56.55#ibcon#about to read 5, iclass 18, count 0 2006.173.21:56:56.55#ibcon#read 5, iclass 18, count 0 2006.173.21:56:56.55#ibcon#about to read 6, iclass 18, count 0 2006.173.21:56:56.55#ibcon#read 6, iclass 18, count 0 2006.173.21:56:56.55#ibcon#end of sib2, iclass 18, count 0 2006.173.21:56:56.55#ibcon#*after write, iclass 18, count 0 2006.173.21:56:56.55#ibcon#*before return 0, iclass 18, count 0 2006.173.21:56:56.55#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.21:56:56.55#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.21:56:56.55#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.21:56:56.55#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.21:56:56.55$vck44/va=5,4 2006.173.21:56:56.55#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.21:56:56.55#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.21:56:56.55#ibcon#ireg 11 cls_cnt 2 2006.173.21:56:56.55#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.21:56:56.61#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.21:56:56.61#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.21:56:56.61#ibcon#enter wrdev, iclass 20, count 2 2006.173.21:56:56.61#ibcon#first serial, iclass 20, count 2 2006.173.21:56:56.61#ibcon#enter sib2, iclass 20, count 2 2006.173.21:56:56.61#ibcon#flushed, iclass 20, count 2 2006.173.21:56:56.61#ibcon#about to write, iclass 20, count 2 2006.173.21:56:56.61#ibcon#wrote, iclass 20, count 2 2006.173.21:56:56.61#ibcon#about to read 3, iclass 20, count 2 2006.173.21:56:56.63#ibcon#read 3, iclass 20, count 2 2006.173.21:56:56.63#ibcon#about to read 4, iclass 20, count 2 2006.173.21:56:56.63#ibcon#read 4, iclass 20, count 2 2006.173.21:56:56.63#ibcon#about to read 5, iclass 20, count 2 2006.173.21:56:56.63#ibcon#read 5, iclass 20, count 2 2006.173.21:56:56.63#ibcon#about to read 6, iclass 20, count 2 2006.173.21:56:56.63#ibcon#read 6, iclass 20, count 2 2006.173.21:56:56.63#ibcon#end of sib2, iclass 20, count 2 2006.173.21:56:56.63#ibcon#*mode == 0, iclass 20, count 2 2006.173.21:56:56.63#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.21:56:56.63#ibcon#[25=AT05-04\r\n] 2006.173.21:56:56.63#ibcon#*before write, iclass 20, count 2 2006.173.21:56:56.63#ibcon#enter sib2, iclass 20, count 2 2006.173.21:56:56.63#ibcon#flushed, iclass 20, count 2 2006.173.21:56:56.63#ibcon#about to write, iclass 20, count 2 2006.173.21:56:56.63#ibcon#wrote, iclass 20, count 2 2006.173.21:56:56.63#ibcon#about to read 3, iclass 20, count 2 2006.173.21:56:56.66#ibcon#read 3, iclass 20, count 2 2006.173.21:56:56.66#ibcon#about to read 4, iclass 20, count 2 2006.173.21:56:56.66#ibcon#read 4, iclass 20, count 2 2006.173.21:56:56.66#ibcon#about to read 5, iclass 20, count 2 2006.173.21:56:56.66#ibcon#read 5, iclass 20, count 2 2006.173.21:56:56.66#ibcon#about to read 6, iclass 20, count 2 2006.173.21:56:56.66#ibcon#read 6, iclass 20, count 2 2006.173.21:56:56.66#ibcon#end of sib2, iclass 20, count 2 2006.173.21:56:56.66#ibcon#*after write, iclass 20, count 2 2006.173.21:56:56.66#ibcon#*before return 0, iclass 20, count 2 2006.173.21:56:56.66#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.21:56:56.66#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.21:56:56.66#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.21:56:56.66#ibcon#ireg 7 cls_cnt 0 2006.173.21:56:56.66#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.21:56:56.78#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.21:56:56.78#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.21:56:56.78#ibcon#enter wrdev, iclass 20, count 0 2006.173.21:56:56.78#ibcon#first serial, iclass 20, count 0 2006.173.21:56:56.78#ibcon#enter sib2, iclass 20, count 0 2006.173.21:56:56.78#ibcon#flushed, iclass 20, count 0 2006.173.21:56:56.78#ibcon#about to write, iclass 20, count 0 2006.173.21:56:56.78#ibcon#wrote, iclass 20, count 0 2006.173.21:56:56.78#ibcon#about to read 3, iclass 20, count 0 2006.173.21:56:56.80#ibcon#read 3, iclass 20, count 0 2006.173.21:56:56.80#ibcon#about to read 4, iclass 20, count 0 2006.173.21:56:56.80#ibcon#read 4, iclass 20, count 0 2006.173.21:56:56.80#ibcon#about to read 5, iclass 20, count 0 2006.173.21:56:56.80#ibcon#read 5, iclass 20, count 0 2006.173.21:56:56.80#ibcon#about to read 6, iclass 20, count 0 2006.173.21:56:56.80#ibcon#read 6, iclass 20, count 0 2006.173.21:56:56.80#ibcon#end of sib2, iclass 20, count 0 2006.173.21:56:56.80#ibcon#*mode == 0, iclass 20, count 0 2006.173.21:56:56.80#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.21:56:56.80#ibcon#[25=USB\r\n] 2006.173.21:56:56.80#ibcon#*before write, iclass 20, count 0 2006.173.21:56:56.80#ibcon#enter sib2, iclass 20, count 0 2006.173.21:56:56.80#ibcon#flushed, iclass 20, count 0 2006.173.21:56:56.80#ibcon#about to write, iclass 20, count 0 2006.173.21:56:56.80#ibcon#wrote, iclass 20, count 0 2006.173.21:56:56.80#ibcon#about to read 3, iclass 20, count 0 2006.173.21:56:56.83#ibcon#read 3, iclass 20, count 0 2006.173.21:56:56.83#ibcon#about to read 4, iclass 20, count 0 2006.173.21:56:56.83#ibcon#read 4, iclass 20, count 0 2006.173.21:56:56.83#ibcon#about to read 5, iclass 20, count 0 2006.173.21:56:56.83#ibcon#read 5, iclass 20, count 0 2006.173.21:56:56.83#ibcon#about to read 6, iclass 20, count 0 2006.173.21:56:56.83#ibcon#read 6, iclass 20, count 0 2006.173.21:56:56.83#ibcon#end of sib2, iclass 20, count 0 2006.173.21:56:56.83#ibcon#*after write, iclass 20, count 0 2006.173.21:56:56.83#ibcon#*before return 0, iclass 20, count 0 2006.173.21:56:56.83#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.21:56:56.83#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.21:56:56.83#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.21:56:56.83#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.21:56:56.83$vck44/valo=6,814.99 2006.173.21:56:56.83#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.21:56:56.83#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.21:56:56.83#ibcon#ireg 17 cls_cnt 0 2006.173.21:56:56.83#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.21:56:56.83#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.21:56:56.83#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.21:56:56.83#ibcon#enter wrdev, iclass 22, count 0 2006.173.21:56:56.83#ibcon#first serial, iclass 22, count 0 2006.173.21:56:56.83#ibcon#enter sib2, iclass 22, count 0 2006.173.21:56:56.83#ibcon#flushed, iclass 22, count 0 2006.173.21:56:56.83#ibcon#about to write, iclass 22, count 0 2006.173.21:56:56.83#ibcon#wrote, iclass 22, count 0 2006.173.21:56:56.83#ibcon#about to read 3, iclass 22, count 0 2006.173.21:56:56.85#ibcon#read 3, iclass 22, count 0 2006.173.21:56:56.85#ibcon#about to read 4, iclass 22, count 0 2006.173.21:56:56.85#ibcon#read 4, iclass 22, count 0 2006.173.21:56:56.85#ibcon#about to read 5, iclass 22, count 0 2006.173.21:56:56.85#ibcon#read 5, iclass 22, count 0 2006.173.21:56:56.85#ibcon#about to read 6, iclass 22, count 0 2006.173.21:56:56.85#ibcon#read 6, iclass 22, count 0 2006.173.21:56:56.85#ibcon#end of sib2, iclass 22, count 0 2006.173.21:56:56.85#ibcon#*mode == 0, iclass 22, count 0 2006.173.21:56:56.85#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.21:56:56.85#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.21:56:56.85#ibcon#*before write, iclass 22, count 0 2006.173.21:56:56.85#ibcon#enter sib2, iclass 22, count 0 2006.173.21:56:56.85#ibcon#flushed, iclass 22, count 0 2006.173.21:56:56.85#ibcon#about to write, iclass 22, count 0 2006.173.21:56:56.85#ibcon#wrote, iclass 22, count 0 2006.173.21:56:56.85#ibcon#about to read 3, iclass 22, count 0 2006.173.21:56:56.89#ibcon#read 3, iclass 22, count 0 2006.173.21:56:56.89#ibcon#about to read 4, iclass 22, count 0 2006.173.21:56:56.89#ibcon#read 4, iclass 22, count 0 2006.173.21:56:56.89#ibcon#about to read 5, iclass 22, count 0 2006.173.21:56:56.89#ibcon#read 5, iclass 22, count 0 2006.173.21:56:56.89#ibcon#about to read 6, iclass 22, count 0 2006.173.21:56:56.89#ibcon#read 6, iclass 22, count 0 2006.173.21:56:56.89#ibcon#end of sib2, iclass 22, count 0 2006.173.21:56:56.89#ibcon#*after write, iclass 22, count 0 2006.173.21:56:56.89#ibcon#*before return 0, iclass 22, count 0 2006.173.21:56:56.89#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.21:56:56.89#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.21:56:56.89#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.21:56:56.89#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.21:56:56.89$vck44/va=6,3 2006.173.21:56:56.89#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.21:56:56.89#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.21:56:56.89#ibcon#ireg 11 cls_cnt 2 2006.173.21:56:56.89#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.21:56:56.95#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.21:56:56.95#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.21:56:56.95#ibcon#enter wrdev, iclass 24, count 2 2006.173.21:56:56.95#ibcon#first serial, iclass 24, count 2 2006.173.21:56:56.95#ibcon#enter sib2, iclass 24, count 2 2006.173.21:56:56.95#ibcon#flushed, iclass 24, count 2 2006.173.21:56:56.95#ibcon#about to write, iclass 24, count 2 2006.173.21:56:56.95#ibcon#wrote, iclass 24, count 2 2006.173.21:56:56.95#ibcon#about to read 3, iclass 24, count 2 2006.173.21:56:56.97#ibcon#read 3, iclass 24, count 2 2006.173.21:56:56.97#ibcon#about to read 4, iclass 24, count 2 2006.173.21:56:56.97#ibcon#read 4, iclass 24, count 2 2006.173.21:56:56.97#ibcon#about to read 5, iclass 24, count 2 2006.173.21:56:56.97#ibcon#read 5, iclass 24, count 2 2006.173.21:56:56.97#ibcon#about to read 6, iclass 24, count 2 2006.173.21:56:56.97#ibcon#read 6, iclass 24, count 2 2006.173.21:56:56.97#ibcon#end of sib2, iclass 24, count 2 2006.173.21:56:56.97#ibcon#*mode == 0, iclass 24, count 2 2006.173.21:56:56.97#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.21:56:56.97#ibcon#[25=AT06-03\r\n] 2006.173.21:56:56.97#ibcon#*before write, iclass 24, count 2 2006.173.21:56:56.97#ibcon#enter sib2, iclass 24, count 2 2006.173.21:56:56.97#ibcon#flushed, iclass 24, count 2 2006.173.21:56:56.97#ibcon#about to write, iclass 24, count 2 2006.173.21:56:56.97#ibcon#wrote, iclass 24, count 2 2006.173.21:56:56.97#ibcon#about to read 3, iclass 24, count 2 2006.173.21:56:57.00#ibcon#read 3, iclass 24, count 2 2006.173.21:56:57.00#ibcon#about to read 4, iclass 24, count 2 2006.173.21:56:57.00#ibcon#read 4, iclass 24, count 2 2006.173.21:56:57.00#ibcon#about to read 5, iclass 24, count 2 2006.173.21:56:57.00#ibcon#read 5, iclass 24, count 2 2006.173.21:56:57.00#ibcon#about to read 6, iclass 24, count 2 2006.173.21:56:57.00#ibcon#read 6, iclass 24, count 2 2006.173.21:56:57.00#ibcon#end of sib2, iclass 24, count 2 2006.173.21:56:57.00#ibcon#*after write, iclass 24, count 2 2006.173.21:56:57.00#ibcon#*before return 0, iclass 24, count 2 2006.173.21:56:57.00#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.21:56:57.00#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.21:56:57.00#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.21:56:57.00#ibcon#ireg 7 cls_cnt 0 2006.173.21:56:57.00#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.21:56:57.12#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.21:56:57.12#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.21:56:57.12#ibcon#enter wrdev, iclass 24, count 0 2006.173.21:56:57.12#ibcon#first serial, iclass 24, count 0 2006.173.21:56:57.12#ibcon#enter sib2, iclass 24, count 0 2006.173.21:56:57.12#ibcon#flushed, iclass 24, count 0 2006.173.21:56:57.12#ibcon#about to write, iclass 24, count 0 2006.173.21:56:57.12#ibcon#wrote, iclass 24, count 0 2006.173.21:56:57.12#ibcon#about to read 3, iclass 24, count 0 2006.173.21:56:57.14#ibcon#read 3, iclass 24, count 0 2006.173.21:56:57.14#ibcon#about to read 4, iclass 24, count 0 2006.173.21:56:57.14#ibcon#read 4, iclass 24, count 0 2006.173.21:56:57.14#ibcon#about to read 5, iclass 24, count 0 2006.173.21:56:57.14#ibcon#read 5, iclass 24, count 0 2006.173.21:56:57.14#ibcon#about to read 6, iclass 24, count 0 2006.173.21:56:57.14#ibcon#read 6, iclass 24, count 0 2006.173.21:56:57.14#ibcon#end of sib2, iclass 24, count 0 2006.173.21:56:57.14#ibcon#*mode == 0, iclass 24, count 0 2006.173.21:56:57.14#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.21:56:57.14#ibcon#[25=USB\r\n] 2006.173.21:56:57.14#ibcon#*before write, iclass 24, count 0 2006.173.21:56:57.14#ibcon#enter sib2, iclass 24, count 0 2006.173.21:56:57.14#ibcon#flushed, iclass 24, count 0 2006.173.21:56:57.14#ibcon#about to write, iclass 24, count 0 2006.173.21:56:57.14#ibcon#wrote, iclass 24, count 0 2006.173.21:56:57.14#ibcon#about to read 3, iclass 24, count 0 2006.173.21:56:57.17#ibcon#read 3, iclass 24, count 0 2006.173.21:56:57.17#ibcon#about to read 4, iclass 24, count 0 2006.173.21:56:57.17#ibcon#read 4, iclass 24, count 0 2006.173.21:56:57.17#ibcon#about to read 5, iclass 24, count 0 2006.173.21:56:57.17#ibcon#read 5, iclass 24, count 0 2006.173.21:56:57.17#ibcon#about to read 6, iclass 24, count 0 2006.173.21:56:57.17#ibcon#read 6, iclass 24, count 0 2006.173.21:56:57.17#ibcon#end of sib2, iclass 24, count 0 2006.173.21:56:57.17#ibcon#*after write, iclass 24, count 0 2006.173.21:56:57.17#ibcon#*before return 0, iclass 24, count 0 2006.173.21:56:57.17#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.21:56:57.17#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.21:56:57.17#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.21:56:57.17#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.21:56:57.17$vck44/valo=7,864.99 2006.173.21:56:57.17#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.21:56:57.17#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.21:56:57.17#ibcon#ireg 17 cls_cnt 0 2006.173.21:56:57.17#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.21:56:57.17#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.21:56:57.17#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.21:56:57.17#ibcon#enter wrdev, iclass 26, count 0 2006.173.21:56:57.17#ibcon#first serial, iclass 26, count 0 2006.173.21:56:57.17#ibcon#enter sib2, iclass 26, count 0 2006.173.21:56:57.17#ibcon#flushed, iclass 26, count 0 2006.173.21:56:57.17#ibcon#about to write, iclass 26, count 0 2006.173.21:56:57.17#ibcon#wrote, iclass 26, count 0 2006.173.21:56:57.17#ibcon#about to read 3, iclass 26, count 0 2006.173.21:56:57.19#ibcon#read 3, iclass 26, count 0 2006.173.21:56:57.19#ibcon#about to read 4, iclass 26, count 0 2006.173.21:56:57.19#ibcon#read 4, iclass 26, count 0 2006.173.21:56:57.19#ibcon#about to read 5, iclass 26, count 0 2006.173.21:56:57.19#ibcon#read 5, iclass 26, count 0 2006.173.21:56:57.19#ibcon#about to read 6, iclass 26, count 0 2006.173.21:56:57.19#ibcon#read 6, iclass 26, count 0 2006.173.21:56:57.19#ibcon#end of sib2, iclass 26, count 0 2006.173.21:56:57.19#ibcon#*mode == 0, iclass 26, count 0 2006.173.21:56:57.19#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.21:56:57.19#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.21:56:57.19#ibcon#*before write, iclass 26, count 0 2006.173.21:56:57.19#ibcon#enter sib2, iclass 26, count 0 2006.173.21:56:57.19#ibcon#flushed, iclass 26, count 0 2006.173.21:56:57.19#ibcon#about to write, iclass 26, count 0 2006.173.21:56:57.19#ibcon#wrote, iclass 26, count 0 2006.173.21:56:57.19#ibcon#about to read 3, iclass 26, count 0 2006.173.21:56:57.23#ibcon#read 3, iclass 26, count 0 2006.173.21:56:57.23#ibcon#about to read 4, iclass 26, count 0 2006.173.21:56:57.23#ibcon#read 4, iclass 26, count 0 2006.173.21:56:57.23#ibcon#about to read 5, iclass 26, count 0 2006.173.21:56:57.23#ibcon#read 5, iclass 26, count 0 2006.173.21:56:57.23#ibcon#about to read 6, iclass 26, count 0 2006.173.21:56:57.23#ibcon#read 6, iclass 26, count 0 2006.173.21:56:57.23#ibcon#end of sib2, iclass 26, count 0 2006.173.21:56:57.23#ibcon#*after write, iclass 26, count 0 2006.173.21:56:57.23#ibcon#*before return 0, iclass 26, count 0 2006.173.21:56:57.23#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.21:56:57.23#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.21:56:57.23#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.21:56:57.23#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.21:56:57.23$vck44/va=7,4 2006.173.21:56:57.23#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.21:56:57.23#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.21:56:57.23#ibcon#ireg 11 cls_cnt 2 2006.173.21:56:57.23#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.21:56:57.29#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.21:56:57.29#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.21:56:57.29#ibcon#enter wrdev, iclass 28, count 2 2006.173.21:56:57.29#ibcon#first serial, iclass 28, count 2 2006.173.21:56:57.29#ibcon#enter sib2, iclass 28, count 2 2006.173.21:56:57.29#ibcon#flushed, iclass 28, count 2 2006.173.21:56:57.29#ibcon#about to write, iclass 28, count 2 2006.173.21:56:57.29#ibcon#wrote, iclass 28, count 2 2006.173.21:56:57.29#ibcon#about to read 3, iclass 28, count 2 2006.173.21:56:57.31#ibcon#read 3, iclass 28, count 2 2006.173.21:56:57.31#ibcon#about to read 4, iclass 28, count 2 2006.173.21:56:57.31#ibcon#read 4, iclass 28, count 2 2006.173.21:56:57.31#ibcon#about to read 5, iclass 28, count 2 2006.173.21:56:57.31#ibcon#read 5, iclass 28, count 2 2006.173.21:56:57.31#ibcon#about to read 6, iclass 28, count 2 2006.173.21:56:57.31#ibcon#read 6, iclass 28, count 2 2006.173.21:56:57.31#ibcon#end of sib2, iclass 28, count 2 2006.173.21:56:57.31#ibcon#*mode == 0, iclass 28, count 2 2006.173.21:56:57.31#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.21:56:57.31#ibcon#[25=AT07-04\r\n] 2006.173.21:56:57.31#ibcon#*before write, iclass 28, count 2 2006.173.21:56:57.31#ibcon#enter sib2, iclass 28, count 2 2006.173.21:56:57.31#ibcon#flushed, iclass 28, count 2 2006.173.21:56:57.31#ibcon#about to write, iclass 28, count 2 2006.173.21:56:57.31#ibcon#wrote, iclass 28, count 2 2006.173.21:56:57.31#ibcon#about to read 3, iclass 28, count 2 2006.173.21:56:57.34#ibcon#read 3, iclass 28, count 2 2006.173.21:56:57.34#ibcon#about to read 4, iclass 28, count 2 2006.173.21:56:57.34#ibcon#read 4, iclass 28, count 2 2006.173.21:56:57.34#ibcon#about to read 5, iclass 28, count 2 2006.173.21:56:57.34#ibcon#read 5, iclass 28, count 2 2006.173.21:56:57.34#ibcon#about to read 6, iclass 28, count 2 2006.173.21:56:57.34#ibcon#read 6, iclass 28, count 2 2006.173.21:56:57.34#ibcon#end of sib2, iclass 28, count 2 2006.173.21:56:57.34#ibcon#*after write, iclass 28, count 2 2006.173.21:56:57.34#ibcon#*before return 0, iclass 28, count 2 2006.173.21:56:57.34#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.21:56:57.34#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.21:56:57.34#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.21:56:57.34#ibcon#ireg 7 cls_cnt 0 2006.173.21:56:57.34#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.21:56:57.46#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.21:56:57.46#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.21:56:57.46#ibcon#enter wrdev, iclass 28, count 0 2006.173.21:56:57.46#ibcon#first serial, iclass 28, count 0 2006.173.21:56:57.46#ibcon#enter sib2, iclass 28, count 0 2006.173.21:56:57.46#ibcon#flushed, iclass 28, count 0 2006.173.21:56:57.46#ibcon#about to write, iclass 28, count 0 2006.173.21:56:57.46#ibcon#wrote, iclass 28, count 0 2006.173.21:56:57.46#ibcon#about to read 3, iclass 28, count 0 2006.173.21:56:57.48#ibcon#read 3, iclass 28, count 0 2006.173.21:56:57.48#ibcon#about to read 4, iclass 28, count 0 2006.173.21:56:57.48#ibcon#read 4, iclass 28, count 0 2006.173.21:56:57.48#ibcon#about to read 5, iclass 28, count 0 2006.173.21:56:57.48#ibcon#read 5, iclass 28, count 0 2006.173.21:56:57.48#ibcon#about to read 6, iclass 28, count 0 2006.173.21:56:57.48#ibcon#read 6, iclass 28, count 0 2006.173.21:56:57.48#ibcon#end of sib2, iclass 28, count 0 2006.173.21:56:57.48#ibcon#*mode == 0, iclass 28, count 0 2006.173.21:56:57.48#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.21:56:57.48#ibcon#[25=USB\r\n] 2006.173.21:56:57.48#ibcon#*before write, iclass 28, count 0 2006.173.21:56:57.48#ibcon#enter sib2, iclass 28, count 0 2006.173.21:56:57.48#ibcon#flushed, iclass 28, count 0 2006.173.21:56:57.48#ibcon#about to write, iclass 28, count 0 2006.173.21:56:57.48#ibcon#wrote, iclass 28, count 0 2006.173.21:56:57.48#ibcon#about to read 3, iclass 28, count 0 2006.173.21:56:57.51#ibcon#read 3, iclass 28, count 0 2006.173.21:56:57.51#ibcon#about to read 4, iclass 28, count 0 2006.173.21:56:57.51#ibcon#read 4, iclass 28, count 0 2006.173.21:56:57.51#ibcon#about to read 5, iclass 28, count 0 2006.173.21:56:57.51#ibcon#read 5, iclass 28, count 0 2006.173.21:56:57.51#ibcon#about to read 6, iclass 28, count 0 2006.173.21:56:57.51#ibcon#read 6, iclass 28, count 0 2006.173.21:56:57.51#ibcon#end of sib2, iclass 28, count 0 2006.173.21:56:57.51#ibcon#*after write, iclass 28, count 0 2006.173.21:56:57.51#ibcon#*before return 0, iclass 28, count 0 2006.173.21:56:57.51#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.21:56:57.51#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.21:56:57.51#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.21:56:57.51#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.21:56:57.51$vck44/valo=8,884.99 2006.173.21:56:57.51#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.21:56:57.51#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.21:56:57.51#ibcon#ireg 17 cls_cnt 0 2006.173.21:56:57.51#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.21:56:57.51#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.21:56:57.51#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.21:56:57.51#ibcon#enter wrdev, iclass 30, count 0 2006.173.21:56:57.51#ibcon#first serial, iclass 30, count 0 2006.173.21:56:57.51#ibcon#enter sib2, iclass 30, count 0 2006.173.21:56:57.51#ibcon#flushed, iclass 30, count 0 2006.173.21:56:57.51#ibcon#about to write, iclass 30, count 0 2006.173.21:56:57.51#ibcon#wrote, iclass 30, count 0 2006.173.21:56:57.51#ibcon#about to read 3, iclass 30, count 0 2006.173.21:56:57.53#ibcon#read 3, iclass 30, count 0 2006.173.21:56:57.53#ibcon#about to read 4, iclass 30, count 0 2006.173.21:56:57.53#ibcon#read 4, iclass 30, count 0 2006.173.21:56:57.53#ibcon#about to read 5, iclass 30, count 0 2006.173.21:56:57.53#ibcon#read 5, iclass 30, count 0 2006.173.21:56:57.53#ibcon#about to read 6, iclass 30, count 0 2006.173.21:56:57.53#ibcon#read 6, iclass 30, count 0 2006.173.21:56:57.53#ibcon#end of sib2, iclass 30, count 0 2006.173.21:56:57.53#ibcon#*mode == 0, iclass 30, count 0 2006.173.21:56:57.53#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.21:56:57.53#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.21:56:57.53#ibcon#*before write, iclass 30, count 0 2006.173.21:56:57.53#ibcon#enter sib2, iclass 30, count 0 2006.173.21:56:57.53#ibcon#flushed, iclass 30, count 0 2006.173.21:56:57.53#ibcon#about to write, iclass 30, count 0 2006.173.21:56:57.53#ibcon#wrote, iclass 30, count 0 2006.173.21:56:57.53#ibcon#about to read 3, iclass 30, count 0 2006.173.21:56:57.57#ibcon#read 3, iclass 30, count 0 2006.173.21:56:57.57#ibcon#about to read 4, iclass 30, count 0 2006.173.21:56:57.57#ibcon#read 4, iclass 30, count 0 2006.173.21:56:57.57#ibcon#about to read 5, iclass 30, count 0 2006.173.21:56:57.57#ibcon#read 5, iclass 30, count 0 2006.173.21:56:57.57#ibcon#about to read 6, iclass 30, count 0 2006.173.21:56:57.57#ibcon#read 6, iclass 30, count 0 2006.173.21:56:57.57#ibcon#end of sib2, iclass 30, count 0 2006.173.21:56:57.57#ibcon#*after write, iclass 30, count 0 2006.173.21:56:57.57#ibcon#*before return 0, iclass 30, count 0 2006.173.21:56:57.57#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.21:56:57.57#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.21:56:57.57#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.21:56:57.57#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.21:56:57.57$vck44/va=8,4 2006.173.21:56:57.57#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.173.21:56:57.57#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.173.21:56:57.57#ibcon#ireg 11 cls_cnt 2 2006.173.21:56:57.57#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.21:56:57.63#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.21:56:57.63#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.21:56:57.63#ibcon#enter wrdev, iclass 32, count 2 2006.173.21:56:57.63#ibcon#first serial, iclass 32, count 2 2006.173.21:56:57.63#ibcon#enter sib2, iclass 32, count 2 2006.173.21:56:57.63#ibcon#flushed, iclass 32, count 2 2006.173.21:56:57.63#ibcon#about to write, iclass 32, count 2 2006.173.21:56:57.63#ibcon#wrote, iclass 32, count 2 2006.173.21:56:57.63#ibcon#about to read 3, iclass 32, count 2 2006.173.21:56:57.65#ibcon#read 3, iclass 32, count 2 2006.173.21:56:57.65#ibcon#about to read 4, iclass 32, count 2 2006.173.21:56:57.65#ibcon#read 4, iclass 32, count 2 2006.173.21:56:57.65#ibcon#about to read 5, iclass 32, count 2 2006.173.21:56:57.65#ibcon#read 5, iclass 32, count 2 2006.173.21:56:57.65#ibcon#about to read 6, iclass 32, count 2 2006.173.21:56:57.65#ibcon#read 6, iclass 32, count 2 2006.173.21:56:57.65#ibcon#end of sib2, iclass 32, count 2 2006.173.21:56:57.65#ibcon#*mode == 0, iclass 32, count 2 2006.173.21:56:57.65#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.173.21:56:57.65#ibcon#[25=AT08-04\r\n] 2006.173.21:56:57.65#ibcon#*before write, iclass 32, count 2 2006.173.21:56:57.65#ibcon#enter sib2, iclass 32, count 2 2006.173.21:56:57.65#ibcon#flushed, iclass 32, count 2 2006.173.21:56:57.65#ibcon#about to write, iclass 32, count 2 2006.173.21:56:57.65#ibcon#wrote, iclass 32, count 2 2006.173.21:56:57.65#ibcon#about to read 3, iclass 32, count 2 2006.173.21:56:57.68#ibcon#read 3, iclass 32, count 2 2006.173.21:56:57.68#ibcon#about to read 4, iclass 32, count 2 2006.173.21:56:57.68#ibcon#read 4, iclass 32, count 2 2006.173.21:56:57.68#ibcon#about to read 5, iclass 32, count 2 2006.173.21:56:57.68#ibcon#read 5, iclass 32, count 2 2006.173.21:56:57.68#ibcon#about to read 6, iclass 32, count 2 2006.173.21:56:57.68#ibcon#read 6, iclass 32, count 2 2006.173.21:56:57.68#ibcon#end of sib2, iclass 32, count 2 2006.173.21:56:57.68#ibcon#*after write, iclass 32, count 2 2006.173.21:56:57.68#ibcon#*before return 0, iclass 32, count 2 2006.173.21:56:57.68#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.21:56:57.68#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.173.21:56:57.68#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.173.21:56:57.68#ibcon#ireg 7 cls_cnt 0 2006.173.21:56:57.68#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.21:56:57.80#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.21:56:57.80#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.21:56:57.80#ibcon#enter wrdev, iclass 32, count 0 2006.173.21:56:57.80#ibcon#first serial, iclass 32, count 0 2006.173.21:56:57.80#ibcon#enter sib2, iclass 32, count 0 2006.173.21:56:57.80#ibcon#flushed, iclass 32, count 0 2006.173.21:56:57.80#ibcon#about to write, iclass 32, count 0 2006.173.21:56:57.80#ibcon#wrote, iclass 32, count 0 2006.173.21:56:57.80#ibcon#about to read 3, iclass 32, count 0 2006.173.21:56:57.82#ibcon#read 3, iclass 32, count 0 2006.173.21:56:57.82#ibcon#about to read 4, iclass 32, count 0 2006.173.21:56:57.82#ibcon#read 4, iclass 32, count 0 2006.173.21:56:57.82#ibcon#about to read 5, iclass 32, count 0 2006.173.21:56:57.82#ibcon#read 5, iclass 32, count 0 2006.173.21:56:57.82#ibcon#about to read 6, iclass 32, count 0 2006.173.21:56:57.82#ibcon#read 6, iclass 32, count 0 2006.173.21:56:57.82#ibcon#end of sib2, iclass 32, count 0 2006.173.21:56:57.82#ibcon#*mode == 0, iclass 32, count 0 2006.173.21:56:57.82#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.21:56:57.82#ibcon#[25=USB\r\n] 2006.173.21:56:57.82#ibcon#*before write, iclass 32, count 0 2006.173.21:56:57.82#ibcon#enter sib2, iclass 32, count 0 2006.173.21:56:57.82#ibcon#flushed, iclass 32, count 0 2006.173.21:56:57.82#ibcon#about to write, iclass 32, count 0 2006.173.21:56:57.82#ibcon#wrote, iclass 32, count 0 2006.173.21:56:57.82#ibcon#about to read 3, iclass 32, count 0 2006.173.21:56:57.85#ibcon#read 3, iclass 32, count 0 2006.173.21:56:57.85#ibcon#about to read 4, iclass 32, count 0 2006.173.21:56:57.85#ibcon#read 4, iclass 32, count 0 2006.173.21:56:57.85#ibcon#about to read 5, iclass 32, count 0 2006.173.21:56:57.85#ibcon#read 5, iclass 32, count 0 2006.173.21:56:57.85#ibcon#about to read 6, iclass 32, count 0 2006.173.21:56:57.85#ibcon#read 6, iclass 32, count 0 2006.173.21:56:57.85#ibcon#end of sib2, iclass 32, count 0 2006.173.21:56:57.85#ibcon#*after write, iclass 32, count 0 2006.173.21:56:57.85#ibcon#*before return 0, iclass 32, count 0 2006.173.21:56:57.85#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.21:56:57.85#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.173.21:56:57.85#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.21:56:57.85#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.21:56:57.85$vck44/vblo=1,629.99 2006.173.21:56:57.85#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.21:56:57.85#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.21:56:57.85#ibcon#ireg 17 cls_cnt 0 2006.173.21:56:57.85#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.21:56:57.85#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.21:56:57.85#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.21:56:57.85#ibcon#enter wrdev, iclass 34, count 0 2006.173.21:56:57.85#ibcon#first serial, iclass 34, count 0 2006.173.21:56:57.85#ibcon#enter sib2, iclass 34, count 0 2006.173.21:56:57.85#ibcon#flushed, iclass 34, count 0 2006.173.21:56:57.85#ibcon#about to write, iclass 34, count 0 2006.173.21:56:57.85#ibcon#wrote, iclass 34, count 0 2006.173.21:56:57.85#ibcon#about to read 3, iclass 34, count 0 2006.173.21:56:57.87#ibcon#read 3, iclass 34, count 0 2006.173.21:56:57.87#ibcon#about to read 4, iclass 34, count 0 2006.173.21:56:57.87#ibcon#read 4, iclass 34, count 0 2006.173.21:56:57.87#ibcon#about to read 5, iclass 34, count 0 2006.173.21:56:57.87#ibcon#read 5, iclass 34, count 0 2006.173.21:56:57.87#ibcon#about to read 6, iclass 34, count 0 2006.173.21:56:57.87#ibcon#read 6, iclass 34, count 0 2006.173.21:56:57.87#ibcon#end of sib2, iclass 34, count 0 2006.173.21:56:57.87#ibcon#*mode == 0, iclass 34, count 0 2006.173.21:56:57.87#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.21:56:57.87#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.21:56:57.87#ibcon#*before write, iclass 34, count 0 2006.173.21:56:57.87#ibcon#enter sib2, iclass 34, count 0 2006.173.21:56:57.87#ibcon#flushed, iclass 34, count 0 2006.173.21:56:57.87#ibcon#about to write, iclass 34, count 0 2006.173.21:56:57.87#ibcon#wrote, iclass 34, count 0 2006.173.21:56:57.87#ibcon#about to read 3, iclass 34, count 0 2006.173.21:56:57.91#ibcon#read 3, iclass 34, count 0 2006.173.21:56:57.91#ibcon#about to read 4, iclass 34, count 0 2006.173.21:56:57.91#ibcon#read 4, iclass 34, count 0 2006.173.21:56:57.91#ibcon#about to read 5, iclass 34, count 0 2006.173.21:56:57.91#ibcon#read 5, iclass 34, count 0 2006.173.21:56:57.91#ibcon#about to read 6, iclass 34, count 0 2006.173.21:56:57.91#ibcon#read 6, iclass 34, count 0 2006.173.21:56:57.91#ibcon#end of sib2, iclass 34, count 0 2006.173.21:56:57.91#ibcon#*after write, iclass 34, count 0 2006.173.21:56:57.91#ibcon#*before return 0, iclass 34, count 0 2006.173.21:56:57.91#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.21:56:57.91#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.21:56:57.91#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.21:56:57.91#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.21:56:57.91$vck44/vb=1,4 2006.173.21:56:57.91#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.21:56:57.91#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.21:56:57.91#ibcon#ireg 11 cls_cnt 2 2006.173.21:56:57.91#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.21:56:57.91#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.21:56:57.91#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.21:56:57.91#ibcon#enter wrdev, iclass 36, count 2 2006.173.21:56:57.91#ibcon#first serial, iclass 36, count 2 2006.173.21:56:57.91#ibcon#enter sib2, iclass 36, count 2 2006.173.21:56:57.91#ibcon#flushed, iclass 36, count 2 2006.173.21:56:57.91#ibcon#about to write, iclass 36, count 2 2006.173.21:56:57.91#ibcon#wrote, iclass 36, count 2 2006.173.21:56:57.91#ibcon#about to read 3, iclass 36, count 2 2006.173.21:56:57.93#ibcon#read 3, iclass 36, count 2 2006.173.21:56:57.93#ibcon#about to read 4, iclass 36, count 2 2006.173.21:56:57.93#ibcon#read 4, iclass 36, count 2 2006.173.21:56:57.93#ibcon#about to read 5, iclass 36, count 2 2006.173.21:56:57.93#ibcon#read 5, iclass 36, count 2 2006.173.21:56:57.93#ibcon#about to read 6, iclass 36, count 2 2006.173.21:56:57.93#ibcon#read 6, iclass 36, count 2 2006.173.21:56:57.93#ibcon#end of sib2, iclass 36, count 2 2006.173.21:56:57.93#ibcon#*mode == 0, iclass 36, count 2 2006.173.21:56:57.93#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.21:56:57.93#ibcon#[27=AT01-04\r\n] 2006.173.21:56:57.93#ibcon#*before write, iclass 36, count 2 2006.173.21:56:57.93#ibcon#enter sib2, iclass 36, count 2 2006.173.21:56:57.93#ibcon#flushed, iclass 36, count 2 2006.173.21:56:57.93#ibcon#about to write, iclass 36, count 2 2006.173.21:56:57.93#ibcon#wrote, iclass 36, count 2 2006.173.21:56:57.93#ibcon#about to read 3, iclass 36, count 2 2006.173.21:56:57.96#ibcon#read 3, iclass 36, count 2 2006.173.21:56:57.96#ibcon#about to read 4, iclass 36, count 2 2006.173.21:56:57.96#ibcon#read 4, iclass 36, count 2 2006.173.21:56:57.96#ibcon#about to read 5, iclass 36, count 2 2006.173.21:56:57.96#ibcon#read 5, iclass 36, count 2 2006.173.21:56:57.96#ibcon#about to read 6, iclass 36, count 2 2006.173.21:56:57.96#ibcon#read 6, iclass 36, count 2 2006.173.21:56:57.96#ibcon#end of sib2, iclass 36, count 2 2006.173.21:56:57.96#ibcon#*after write, iclass 36, count 2 2006.173.21:56:57.96#ibcon#*before return 0, iclass 36, count 2 2006.173.21:56:57.96#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.21:56:57.96#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.21:56:57.96#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.21:56:57.96#ibcon#ireg 7 cls_cnt 0 2006.173.21:56:57.96#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.21:56:58.08#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.21:56:58.08#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.21:56:58.08#ibcon#enter wrdev, iclass 36, count 0 2006.173.21:56:58.08#ibcon#first serial, iclass 36, count 0 2006.173.21:56:58.08#ibcon#enter sib2, iclass 36, count 0 2006.173.21:56:58.08#ibcon#flushed, iclass 36, count 0 2006.173.21:56:58.08#ibcon#about to write, iclass 36, count 0 2006.173.21:56:58.08#ibcon#wrote, iclass 36, count 0 2006.173.21:56:58.08#ibcon#about to read 3, iclass 36, count 0 2006.173.21:56:58.10#ibcon#read 3, iclass 36, count 0 2006.173.21:56:58.10#ibcon#about to read 4, iclass 36, count 0 2006.173.21:56:58.10#ibcon#read 4, iclass 36, count 0 2006.173.21:56:58.10#ibcon#about to read 5, iclass 36, count 0 2006.173.21:56:58.10#ibcon#read 5, iclass 36, count 0 2006.173.21:56:58.10#ibcon#about to read 6, iclass 36, count 0 2006.173.21:56:58.10#ibcon#read 6, iclass 36, count 0 2006.173.21:56:58.10#ibcon#end of sib2, iclass 36, count 0 2006.173.21:56:58.10#ibcon#*mode == 0, iclass 36, count 0 2006.173.21:56:58.10#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.21:56:58.10#ibcon#[27=USB\r\n] 2006.173.21:56:58.10#ibcon#*before write, iclass 36, count 0 2006.173.21:56:58.10#ibcon#enter sib2, iclass 36, count 0 2006.173.21:56:58.10#ibcon#flushed, iclass 36, count 0 2006.173.21:56:58.10#ibcon#about to write, iclass 36, count 0 2006.173.21:56:58.10#ibcon#wrote, iclass 36, count 0 2006.173.21:56:58.10#ibcon#about to read 3, iclass 36, count 0 2006.173.21:56:58.13#ibcon#read 3, iclass 36, count 0 2006.173.21:56:58.13#ibcon#about to read 4, iclass 36, count 0 2006.173.21:56:58.13#ibcon#read 4, iclass 36, count 0 2006.173.21:56:58.13#ibcon#about to read 5, iclass 36, count 0 2006.173.21:56:58.13#ibcon#read 5, iclass 36, count 0 2006.173.21:56:58.13#ibcon#about to read 6, iclass 36, count 0 2006.173.21:56:58.13#ibcon#read 6, iclass 36, count 0 2006.173.21:56:58.13#ibcon#end of sib2, iclass 36, count 0 2006.173.21:56:58.13#ibcon#*after write, iclass 36, count 0 2006.173.21:56:58.13#ibcon#*before return 0, iclass 36, count 0 2006.173.21:56:58.13#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.21:56:58.13#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.21:56:58.13#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.21:56:58.13#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.21:56:58.13$vck44/vblo=2,634.99 2006.173.21:56:58.13#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.21:56:58.13#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.21:56:58.13#ibcon#ireg 17 cls_cnt 0 2006.173.21:56:58.13#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.21:56:58.13#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.21:56:58.13#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.21:56:58.13#ibcon#enter wrdev, iclass 38, count 0 2006.173.21:56:58.13#ibcon#first serial, iclass 38, count 0 2006.173.21:56:58.13#ibcon#enter sib2, iclass 38, count 0 2006.173.21:56:58.13#ibcon#flushed, iclass 38, count 0 2006.173.21:56:58.13#ibcon#about to write, iclass 38, count 0 2006.173.21:56:58.13#ibcon#wrote, iclass 38, count 0 2006.173.21:56:58.13#ibcon#about to read 3, iclass 38, count 0 2006.173.21:56:58.15#ibcon#read 3, iclass 38, count 0 2006.173.21:56:58.15#ibcon#about to read 4, iclass 38, count 0 2006.173.21:56:58.15#ibcon#read 4, iclass 38, count 0 2006.173.21:56:58.15#ibcon#about to read 5, iclass 38, count 0 2006.173.21:56:58.15#ibcon#read 5, iclass 38, count 0 2006.173.21:56:58.15#ibcon#about to read 6, iclass 38, count 0 2006.173.21:56:58.15#ibcon#read 6, iclass 38, count 0 2006.173.21:56:58.15#ibcon#end of sib2, iclass 38, count 0 2006.173.21:56:58.15#ibcon#*mode == 0, iclass 38, count 0 2006.173.21:56:58.15#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.21:56:58.15#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.21:56:58.15#ibcon#*before write, iclass 38, count 0 2006.173.21:56:58.15#ibcon#enter sib2, iclass 38, count 0 2006.173.21:56:58.15#ibcon#flushed, iclass 38, count 0 2006.173.21:56:58.15#ibcon#about to write, iclass 38, count 0 2006.173.21:56:58.15#ibcon#wrote, iclass 38, count 0 2006.173.21:56:58.15#ibcon#about to read 3, iclass 38, count 0 2006.173.21:56:58.19#ibcon#read 3, iclass 38, count 0 2006.173.21:56:58.19#ibcon#about to read 4, iclass 38, count 0 2006.173.21:56:58.19#ibcon#read 4, iclass 38, count 0 2006.173.21:56:58.19#ibcon#about to read 5, iclass 38, count 0 2006.173.21:56:58.19#ibcon#read 5, iclass 38, count 0 2006.173.21:56:58.19#ibcon#about to read 6, iclass 38, count 0 2006.173.21:56:58.19#ibcon#read 6, iclass 38, count 0 2006.173.21:56:58.19#ibcon#end of sib2, iclass 38, count 0 2006.173.21:56:58.19#ibcon#*after write, iclass 38, count 0 2006.173.21:56:58.19#ibcon#*before return 0, iclass 38, count 0 2006.173.21:56:58.19#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.21:56:58.19#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.21:56:58.19#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.21:56:58.19#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.21:56:58.19$vck44/vb=2,4 2006.173.21:56:58.19#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.21:56:58.19#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.21:56:58.19#ibcon#ireg 11 cls_cnt 2 2006.173.21:56:58.19#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.21:56:58.25#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.21:56:58.25#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.21:56:58.25#ibcon#enter wrdev, iclass 40, count 2 2006.173.21:56:58.25#ibcon#first serial, iclass 40, count 2 2006.173.21:56:58.25#ibcon#enter sib2, iclass 40, count 2 2006.173.21:56:58.25#ibcon#flushed, iclass 40, count 2 2006.173.21:56:58.25#ibcon#about to write, iclass 40, count 2 2006.173.21:56:58.25#ibcon#wrote, iclass 40, count 2 2006.173.21:56:58.25#ibcon#about to read 3, iclass 40, count 2 2006.173.21:56:58.27#ibcon#read 3, iclass 40, count 2 2006.173.21:56:58.27#ibcon#about to read 4, iclass 40, count 2 2006.173.21:56:58.27#ibcon#read 4, iclass 40, count 2 2006.173.21:56:58.27#ibcon#about to read 5, iclass 40, count 2 2006.173.21:56:58.27#ibcon#read 5, iclass 40, count 2 2006.173.21:56:58.27#ibcon#about to read 6, iclass 40, count 2 2006.173.21:56:58.27#ibcon#read 6, iclass 40, count 2 2006.173.21:56:58.27#ibcon#end of sib2, iclass 40, count 2 2006.173.21:56:58.27#ibcon#*mode == 0, iclass 40, count 2 2006.173.21:56:58.27#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.21:56:58.27#ibcon#[27=AT02-04\r\n] 2006.173.21:56:58.27#ibcon#*before write, iclass 40, count 2 2006.173.21:56:58.27#ibcon#enter sib2, iclass 40, count 2 2006.173.21:56:58.27#ibcon#flushed, iclass 40, count 2 2006.173.21:56:58.27#ibcon#about to write, iclass 40, count 2 2006.173.21:56:58.27#ibcon#wrote, iclass 40, count 2 2006.173.21:56:58.27#ibcon#about to read 3, iclass 40, count 2 2006.173.21:56:58.30#ibcon#read 3, iclass 40, count 2 2006.173.21:56:58.34#ibcon#about to read 4, iclass 40, count 2 2006.173.21:56:58.34#ibcon#read 4, iclass 40, count 2 2006.173.21:56:58.34#ibcon#about to read 5, iclass 40, count 2 2006.173.21:56:58.34#ibcon#read 5, iclass 40, count 2 2006.173.21:56:58.34#ibcon#about to read 6, iclass 40, count 2 2006.173.21:56:58.34#ibcon#read 6, iclass 40, count 2 2006.173.21:56:58.34#ibcon#end of sib2, iclass 40, count 2 2006.173.21:56:58.34#ibcon#*after write, iclass 40, count 2 2006.173.21:56:58.34#ibcon#*before return 0, iclass 40, count 2 2006.173.21:56:58.35#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.21:56:58.35#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.21:56:58.35#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.21:56:58.35#ibcon#ireg 7 cls_cnt 0 2006.173.21:56:58.35#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.21:56:58.46#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.21:56:58.46#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.21:56:58.46#ibcon#enter wrdev, iclass 40, count 0 2006.173.21:56:58.46#ibcon#first serial, iclass 40, count 0 2006.173.21:56:58.46#ibcon#enter sib2, iclass 40, count 0 2006.173.21:56:58.46#ibcon#flushed, iclass 40, count 0 2006.173.21:56:58.46#ibcon#about to write, iclass 40, count 0 2006.173.21:56:58.46#ibcon#wrote, iclass 40, count 0 2006.173.21:56:58.46#ibcon#about to read 3, iclass 40, count 0 2006.173.21:56:58.48#ibcon#read 3, iclass 40, count 0 2006.173.21:56:58.48#ibcon#about to read 4, iclass 40, count 0 2006.173.21:56:58.48#ibcon#read 4, iclass 40, count 0 2006.173.21:56:58.48#ibcon#about to read 5, iclass 40, count 0 2006.173.21:56:58.48#ibcon#read 5, iclass 40, count 0 2006.173.21:56:58.48#ibcon#about to read 6, iclass 40, count 0 2006.173.21:56:58.48#ibcon#read 6, iclass 40, count 0 2006.173.21:56:58.48#ibcon#end of sib2, iclass 40, count 0 2006.173.21:56:58.48#ibcon#*mode == 0, iclass 40, count 0 2006.173.21:56:58.48#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.21:56:58.48#ibcon#[27=USB\r\n] 2006.173.21:56:58.48#ibcon#*before write, iclass 40, count 0 2006.173.21:56:58.48#ibcon#enter sib2, iclass 40, count 0 2006.173.21:56:58.48#ibcon#flushed, iclass 40, count 0 2006.173.21:56:58.48#ibcon#about to write, iclass 40, count 0 2006.173.21:56:58.48#ibcon#wrote, iclass 40, count 0 2006.173.21:56:58.48#ibcon#about to read 3, iclass 40, count 0 2006.173.21:56:58.51#ibcon#read 3, iclass 40, count 0 2006.173.21:56:58.51#ibcon#about to read 4, iclass 40, count 0 2006.173.21:56:58.51#ibcon#read 4, iclass 40, count 0 2006.173.21:56:58.51#ibcon#about to read 5, iclass 40, count 0 2006.173.21:56:58.51#ibcon#read 5, iclass 40, count 0 2006.173.21:56:58.51#ibcon#about to read 6, iclass 40, count 0 2006.173.21:56:58.51#ibcon#read 6, iclass 40, count 0 2006.173.21:56:58.51#ibcon#end of sib2, iclass 40, count 0 2006.173.21:56:58.51#ibcon#*after write, iclass 40, count 0 2006.173.21:56:58.51#ibcon#*before return 0, iclass 40, count 0 2006.173.21:56:58.51#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.21:56:58.51#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.21:56:58.51#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.21:56:58.51#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.21:56:58.51$vck44/vblo=3,649.99 2006.173.21:56:58.51#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.21:56:58.51#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.21:56:58.51#ibcon#ireg 17 cls_cnt 0 2006.173.21:56:58.51#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.21:56:58.51#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.21:56:58.51#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.21:56:58.51#ibcon#enter wrdev, iclass 4, count 0 2006.173.21:56:58.51#ibcon#first serial, iclass 4, count 0 2006.173.21:56:58.51#ibcon#enter sib2, iclass 4, count 0 2006.173.21:56:58.51#ibcon#flushed, iclass 4, count 0 2006.173.21:56:58.51#ibcon#about to write, iclass 4, count 0 2006.173.21:56:58.51#ibcon#wrote, iclass 4, count 0 2006.173.21:56:58.51#ibcon#about to read 3, iclass 4, count 0 2006.173.21:56:58.53#ibcon#read 3, iclass 4, count 0 2006.173.21:56:58.53#ibcon#about to read 4, iclass 4, count 0 2006.173.21:56:58.53#ibcon#read 4, iclass 4, count 0 2006.173.21:56:58.53#ibcon#about to read 5, iclass 4, count 0 2006.173.21:56:58.53#ibcon#read 5, iclass 4, count 0 2006.173.21:56:58.53#ibcon#about to read 6, iclass 4, count 0 2006.173.21:56:58.53#ibcon#read 6, iclass 4, count 0 2006.173.21:56:58.53#ibcon#end of sib2, iclass 4, count 0 2006.173.21:56:58.53#ibcon#*mode == 0, iclass 4, count 0 2006.173.21:56:58.53#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.21:56:58.53#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.21:56:58.53#ibcon#*before write, iclass 4, count 0 2006.173.21:56:58.53#ibcon#enter sib2, iclass 4, count 0 2006.173.21:56:58.53#ibcon#flushed, iclass 4, count 0 2006.173.21:56:58.53#ibcon#about to write, iclass 4, count 0 2006.173.21:56:58.53#ibcon#wrote, iclass 4, count 0 2006.173.21:56:58.53#ibcon#about to read 3, iclass 4, count 0 2006.173.21:56:58.57#ibcon#read 3, iclass 4, count 0 2006.173.21:56:58.57#ibcon#about to read 4, iclass 4, count 0 2006.173.21:56:58.57#ibcon#read 4, iclass 4, count 0 2006.173.21:56:58.57#ibcon#about to read 5, iclass 4, count 0 2006.173.21:56:58.57#ibcon#read 5, iclass 4, count 0 2006.173.21:56:58.57#ibcon#about to read 6, iclass 4, count 0 2006.173.21:56:58.57#ibcon#read 6, iclass 4, count 0 2006.173.21:56:58.57#ibcon#end of sib2, iclass 4, count 0 2006.173.21:56:58.57#ibcon#*after write, iclass 4, count 0 2006.173.21:56:58.57#ibcon#*before return 0, iclass 4, count 0 2006.173.21:56:58.57#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.21:56:58.57#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.21:56:58.57#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.21:56:58.57#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.21:56:58.57$vck44/vb=3,4 2006.173.21:56:58.57#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.21:56:58.57#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.21:56:58.57#ibcon#ireg 11 cls_cnt 2 2006.173.21:56:58.57#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.21:56:58.63#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.21:56:58.63#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.21:56:58.63#ibcon#enter wrdev, iclass 6, count 2 2006.173.21:56:58.63#ibcon#first serial, iclass 6, count 2 2006.173.21:56:58.63#ibcon#enter sib2, iclass 6, count 2 2006.173.21:56:58.63#ibcon#flushed, iclass 6, count 2 2006.173.21:56:58.63#ibcon#about to write, iclass 6, count 2 2006.173.21:56:58.63#ibcon#wrote, iclass 6, count 2 2006.173.21:56:58.63#ibcon#about to read 3, iclass 6, count 2 2006.173.21:56:58.65#ibcon#read 3, iclass 6, count 2 2006.173.21:56:58.65#ibcon#about to read 4, iclass 6, count 2 2006.173.21:56:58.65#ibcon#read 4, iclass 6, count 2 2006.173.21:56:58.65#ibcon#about to read 5, iclass 6, count 2 2006.173.21:56:58.65#ibcon#read 5, iclass 6, count 2 2006.173.21:56:58.65#ibcon#about to read 6, iclass 6, count 2 2006.173.21:56:58.65#ibcon#read 6, iclass 6, count 2 2006.173.21:56:58.65#ibcon#end of sib2, iclass 6, count 2 2006.173.21:56:58.65#ibcon#*mode == 0, iclass 6, count 2 2006.173.21:56:58.65#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.21:56:58.65#ibcon#[27=AT03-04\r\n] 2006.173.21:56:58.65#ibcon#*before write, iclass 6, count 2 2006.173.21:56:58.65#ibcon#enter sib2, iclass 6, count 2 2006.173.21:56:58.65#ibcon#flushed, iclass 6, count 2 2006.173.21:56:58.65#ibcon#about to write, iclass 6, count 2 2006.173.21:56:58.65#ibcon#wrote, iclass 6, count 2 2006.173.21:56:58.65#ibcon#about to read 3, iclass 6, count 2 2006.173.21:56:58.68#ibcon#read 3, iclass 6, count 2 2006.173.21:56:58.68#ibcon#about to read 4, iclass 6, count 2 2006.173.21:56:58.68#ibcon#read 4, iclass 6, count 2 2006.173.21:56:58.68#ibcon#about to read 5, iclass 6, count 2 2006.173.21:56:58.68#ibcon#read 5, iclass 6, count 2 2006.173.21:56:58.68#ibcon#about to read 6, iclass 6, count 2 2006.173.21:56:58.68#ibcon#read 6, iclass 6, count 2 2006.173.21:56:58.68#ibcon#end of sib2, iclass 6, count 2 2006.173.21:56:58.68#ibcon#*after write, iclass 6, count 2 2006.173.21:56:58.68#ibcon#*before return 0, iclass 6, count 2 2006.173.21:56:58.68#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.21:56:58.68#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.21:56:58.68#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.21:56:58.68#ibcon#ireg 7 cls_cnt 0 2006.173.21:56:58.68#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.21:56:58.80#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.21:56:58.80#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.21:56:58.80#ibcon#enter wrdev, iclass 6, count 0 2006.173.21:56:58.80#ibcon#first serial, iclass 6, count 0 2006.173.21:56:58.80#ibcon#enter sib2, iclass 6, count 0 2006.173.21:56:58.80#ibcon#flushed, iclass 6, count 0 2006.173.21:56:58.80#ibcon#about to write, iclass 6, count 0 2006.173.21:56:58.80#ibcon#wrote, iclass 6, count 0 2006.173.21:56:58.80#ibcon#about to read 3, iclass 6, count 0 2006.173.21:56:58.82#ibcon#read 3, iclass 6, count 0 2006.173.21:56:58.82#ibcon#about to read 4, iclass 6, count 0 2006.173.21:56:58.82#ibcon#read 4, iclass 6, count 0 2006.173.21:56:58.82#ibcon#about to read 5, iclass 6, count 0 2006.173.21:56:58.82#ibcon#read 5, iclass 6, count 0 2006.173.21:56:58.82#ibcon#about to read 6, iclass 6, count 0 2006.173.21:56:58.82#ibcon#read 6, iclass 6, count 0 2006.173.21:56:58.82#ibcon#end of sib2, iclass 6, count 0 2006.173.21:56:58.82#ibcon#*mode == 0, iclass 6, count 0 2006.173.21:56:58.82#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.21:56:58.82#ibcon#[27=USB\r\n] 2006.173.21:56:58.82#ibcon#*before write, iclass 6, count 0 2006.173.21:56:58.82#ibcon#enter sib2, iclass 6, count 0 2006.173.21:56:58.82#ibcon#flushed, iclass 6, count 0 2006.173.21:56:58.82#ibcon#about to write, iclass 6, count 0 2006.173.21:56:58.82#ibcon#wrote, iclass 6, count 0 2006.173.21:56:58.82#ibcon#about to read 3, iclass 6, count 0 2006.173.21:56:58.85#ibcon#read 3, iclass 6, count 0 2006.173.21:56:58.85#ibcon#about to read 4, iclass 6, count 0 2006.173.21:56:58.85#ibcon#read 4, iclass 6, count 0 2006.173.21:56:58.85#ibcon#about to read 5, iclass 6, count 0 2006.173.21:56:58.85#ibcon#read 5, iclass 6, count 0 2006.173.21:56:58.85#ibcon#about to read 6, iclass 6, count 0 2006.173.21:56:58.85#ibcon#read 6, iclass 6, count 0 2006.173.21:56:58.85#ibcon#end of sib2, iclass 6, count 0 2006.173.21:56:58.85#ibcon#*after write, iclass 6, count 0 2006.173.21:56:58.85#ibcon#*before return 0, iclass 6, count 0 2006.173.21:56:58.85#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.21:56:58.85#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.21:56:58.85#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.21:56:58.85#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.21:56:58.85$vck44/vblo=4,679.99 2006.173.21:56:58.85#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.21:56:58.85#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.21:56:58.85#ibcon#ireg 17 cls_cnt 0 2006.173.21:56:58.85#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.21:56:58.85#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.21:56:58.85#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.21:56:58.85#ibcon#enter wrdev, iclass 10, count 0 2006.173.21:56:58.85#ibcon#first serial, iclass 10, count 0 2006.173.21:56:58.85#ibcon#enter sib2, iclass 10, count 0 2006.173.21:56:58.85#ibcon#flushed, iclass 10, count 0 2006.173.21:56:58.85#ibcon#about to write, iclass 10, count 0 2006.173.21:56:58.85#ibcon#wrote, iclass 10, count 0 2006.173.21:56:58.85#ibcon#about to read 3, iclass 10, count 0 2006.173.21:56:58.87#ibcon#read 3, iclass 10, count 0 2006.173.21:56:58.87#ibcon#about to read 4, iclass 10, count 0 2006.173.21:56:58.87#ibcon#read 4, iclass 10, count 0 2006.173.21:56:58.87#ibcon#about to read 5, iclass 10, count 0 2006.173.21:56:58.87#ibcon#read 5, iclass 10, count 0 2006.173.21:56:58.87#ibcon#about to read 6, iclass 10, count 0 2006.173.21:56:58.87#ibcon#read 6, iclass 10, count 0 2006.173.21:56:58.87#ibcon#end of sib2, iclass 10, count 0 2006.173.21:56:58.87#ibcon#*mode == 0, iclass 10, count 0 2006.173.21:56:58.87#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.21:56:58.87#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.21:56:58.87#ibcon#*before write, iclass 10, count 0 2006.173.21:56:58.87#ibcon#enter sib2, iclass 10, count 0 2006.173.21:56:58.87#ibcon#flushed, iclass 10, count 0 2006.173.21:56:58.87#ibcon#about to write, iclass 10, count 0 2006.173.21:56:58.87#ibcon#wrote, iclass 10, count 0 2006.173.21:56:58.87#ibcon#about to read 3, iclass 10, count 0 2006.173.21:56:58.91#ibcon#read 3, iclass 10, count 0 2006.173.21:56:58.91#ibcon#about to read 4, iclass 10, count 0 2006.173.21:56:58.91#ibcon#read 4, iclass 10, count 0 2006.173.21:56:58.91#ibcon#about to read 5, iclass 10, count 0 2006.173.21:56:58.91#ibcon#read 5, iclass 10, count 0 2006.173.21:56:58.91#ibcon#about to read 6, iclass 10, count 0 2006.173.21:56:58.91#ibcon#read 6, iclass 10, count 0 2006.173.21:56:58.91#ibcon#end of sib2, iclass 10, count 0 2006.173.21:56:58.91#ibcon#*after write, iclass 10, count 0 2006.173.21:56:58.91#ibcon#*before return 0, iclass 10, count 0 2006.173.21:56:58.91#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.21:56:58.91#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.21:56:58.91#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.21:56:58.91#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.21:56:58.91$vck44/vb=4,4 2006.173.21:56:58.91#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.21:56:58.91#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.21:56:58.91#ibcon#ireg 11 cls_cnt 2 2006.173.21:56:58.91#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.21:56:58.97#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.21:56:58.97#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.21:56:58.97#ibcon#enter wrdev, iclass 12, count 2 2006.173.21:56:58.97#ibcon#first serial, iclass 12, count 2 2006.173.21:56:58.97#ibcon#enter sib2, iclass 12, count 2 2006.173.21:56:58.97#ibcon#flushed, iclass 12, count 2 2006.173.21:56:58.97#ibcon#about to write, iclass 12, count 2 2006.173.21:56:58.97#ibcon#wrote, iclass 12, count 2 2006.173.21:56:58.97#ibcon#about to read 3, iclass 12, count 2 2006.173.21:56:58.99#ibcon#read 3, iclass 12, count 2 2006.173.21:56:58.99#ibcon#about to read 4, iclass 12, count 2 2006.173.21:56:58.99#ibcon#read 4, iclass 12, count 2 2006.173.21:56:58.99#ibcon#about to read 5, iclass 12, count 2 2006.173.21:56:58.99#ibcon#read 5, iclass 12, count 2 2006.173.21:56:58.99#ibcon#about to read 6, iclass 12, count 2 2006.173.21:56:58.99#ibcon#read 6, iclass 12, count 2 2006.173.21:56:58.99#ibcon#end of sib2, iclass 12, count 2 2006.173.21:56:58.99#ibcon#*mode == 0, iclass 12, count 2 2006.173.21:56:58.99#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.21:56:58.99#ibcon#[27=AT04-04\r\n] 2006.173.21:56:58.99#ibcon#*before write, iclass 12, count 2 2006.173.21:56:58.99#ibcon#enter sib2, iclass 12, count 2 2006.173.21:56:58.99#ibcon#flushed, iclass 12, count 2 2006.173.21:56:58.99#ibcon#about to write, iclass 12, count 2 2006.173.21:56:58.99#ibcon#wrote, iclass 12, count 2 2006.173.21:56:58.99#ibcon#about to read 3, iclass 12, count 2 2006.173.21:56:59.02#ibcon#read 3, iclass 12, count 2 2006.173.21:56:59.02#ibcon#about to read 4, iclass 12, count 2 2006.173.21:56:59.02#ibcon#read 4, iclass 12, count 2 2006.173.21:56:59.02#ibcon#about to read 5, iclass 12, count 2 2006.173.21:56:59.02#ibcon#read 5, iclass 12, count 2 2006.173.21:56:59.02#ibcon#about to read 6, iclass 12, count 2 2006.173.21:56:59.02#ibcon#read 6, iclass 12, count 2 2006.173.21:56:59.02#ibcon#end of sib2, iclass 12, count 2 2006.173.21:56:59.02#ibcon#*after write, iclass 12, count 2 2006.173.21:56:59.02#ibcon#*before return 0, iclass 12, count 2 2006.173.21:56:59.02#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.21:56:59.02#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.21:56:59.02#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.21:56:59.02#ibcon#ireg 7 cls_cnt 0 2006.173.21:56:59.02#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.21:56:59.14#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.21:56:59.14#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.21:56:59.14#ibcon#enter wrdev, iclass 12, count 0 2006.173.21:56:59.14#ibcon#first serial, iclass 12, count 0 2006.173.21:56:59.14#ibcon#enter sib2, iclass 12, count 0 2006.173.21:56:59.14#ibcon#flushed, iclass 12, count 0 2006.173.21:56:59.14#ibcon#about to write, iclass 12, count 0 2006.173.21:56:59.14#ibcon#wrote, iclass 12, count 0 2006.173.21:56:59.14#ibcon#about to read 3, iclass 12, count 0 2006.173.21:56:59.16#ibcon#read 3, iclass 12, count 0 2006.173.21:56:59.16#ibcon#about to read 4, iclass 12, count 0 2006.173.21:56:59.16#ibcon#read 4, iclass 12, count 0 2006.173.21:56:59.16#ibcon#about to read 5, iclass 12, count 0 2006.173.21:56:59.16#ibcon#read 5, iclass 12, count 0 2006.173.21:56:59.16#ibcon#about to read 6, iclass 12, count 0 2006.173.21:56:59.16#ibcon#read 6, iclass 12, count 0 2006.173.21:56:59.16#ibcon#end of sib2, iclass 12, count 0 2006.173.21:56:59.16#ibcon#*mode == 0, iclass 12, count 0 2006.173.21:56:59.16#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.21:56:59.16#ibcon#[27=USB\r\n] 2006.173.21:56:59.16#ibcon#*before write, iclass 12, count 0 2006.173.21:56:59.16#ibcon#enter sib2, iclass 12, count 0 2006.173.21:56:59.16#ibcon#flushed, iclass 12, count 0 2006.173.21:56:59.16#ibcon#about to write, iclass 12, count 0 2006.173.21:56:59.16#ibcon#wrote, iclass 12, count 0 2006.173.21:56:59.16#ibcon#about to read 3, iclass 12, count 0 2006.173.21:56:59.19#ibcon#read 3, iclass 12, count 0 2006.173.21:56:59.19#ibcon#about to read 4, iclass 12, count 0 2006.173.21:56:59.19#ibcon#read 4, iclass 12, count 0 2006.173.21:56:59.19#ibcon#about to read 5, iclass 12, count 0 2006.173.21:56:59.19#ibcon#read 5, iclass 12, count 0 2006.173.21:56:59.19#ibcon#about to read 6, iclass 12, count 0 2006.173.21:56:59.19#ibcon#read 6, iclass 12, count 0 2006.173.21:56:59.19#ibcon#end of sib2, iclass 12, count 0 2006.173.21:56:59.19#ibcon#*after write, iclass 12, count 0 2006.173.21:56:59.19#ibcon#*before return 0, iclass 12, count 0 2006.173.21:56:59.19#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.21:56:59.19#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.21:56:59.19#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.21:56:59.19#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.21:56:59.19$vck44/vblo=5,709.99 2006.173.21:56:59.19#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.21:56:59.19#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.21:56:59.19#ibcon#ireg 17 cls_cnt 0 2006.173.21:56:59.19#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.21:56:59.19#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.21:56:59.19#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.21:56:59.19#ibcon#enter wrdev, iclass 14, count 0 2006.173.21:56:59.19#ibcon#first serial, iclass 14, count 0 2006.173.21:56:59.19#ibcon#enter sib2, iclass 14, count 0 2006.173.21:56:59.19#ibcon#flushed, iclass 14, count 0 2006.173.21:56:59.19#ibcon#about to write, iclass 14, count 0 2006.173.21:56:59.19#ibcon#wrote, iclass 14, count 0 2006.173.21:56:59.19#ibcon#about to read 3, iclass 14, count 0 2006.173.21:56:59.21#ibcon#read 3, iclass 14, count 0 2006.173.21:56:59.21#ibcon#about to read 4, iclass 14, count 0 2006.173.21:56:59.21#ibcon#read 4, iclass 14, count 0 2006.173.21:56:59.21#ibcon#about to read 5, iclass 14, count 0 2006.173.21:56:59.21#ibcon#read 5, iclass 14, count 0 2006.173.21:56:59.21#ibcon#about to read 6, iclass 14, count 0 2006.173.21:56:59.21#ibcon#read 6, iclass 14, count 0 2006.173.21:56:59.21#ibcon#end of sib2, iclass 14, count 0 2006.173.21:56:59.21#ibcon#*mode == 0, iclass 14, count 0 2006.173.21:56:59.21#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.21:56:59.21#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.21:56:59.21#ibcon#*before write, iclass 14, count 0 2006.173.21:56:59.21#ibcon#enter sib2, iclass 14, count 0 2006.173.21:56:59.21#ibcon#flushed, iclass 14, count 0 2006.173.21:56:59.21#ibcon#about to write, iclass 14, count 0 2006.173.21:56:59.21#ibcon#wrote, iclass 14, count 0 2006.173.21:56:59.21#ibcon#about to read 3, iclass 14, count 0 2006.173.21:56:59.25#ibcon#read 3, iclass 14, count 0 2006.173.21:56:59.25#ibcon#about to read 4, iclass 14, count 0 2006.173.21:56:59.25#ibcon#read 4, iclass 14, count 0 2006.173.21:56:59.25#ibcon#about to read 5, iclass 14, count 0 2006.173.21:56:59.25#ibcon#read 5, iclass 14, count 0 2006.173.21:56:59.25#ibcon#about to read 6, iclass 14, count 0 2006.173.21:56:59.25#ibcon#read 6, iclass 14, count 0 2006.173.21:56:59.25#ibcon#end of sib2, iclass 14, count 0 2006.173.21:56:59.25#ibcon#*after write, iclass 14, count 0 2006.173.21:56:59.25#ibcon#*before return 0, iclass 14, count 0 2006.173.21:56:59.25#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.21:56:59.25#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.21:56:59.25#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.21:56:59.25#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.21:56:59.25$vck44/vb=5,4 2006.173.21:56:59.25#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.21:56:59.25#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.21:56:59.25#ibcon#ireg 11 cls_cnt 2 2006.173.21:56:59.25#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.21:56:59.31#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.21:56:59.31#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.21:56:59.31#ibcon#enter wrdev, iclass 16, count 2 2006.173.21:56:59.31#ibcon#first serial, iclass 16, count 2 2006.173.21:56:59.31#ibcon#enter sib2, iclass 16, count 2 2006.173.21:56:59.31#ibcon#flushed, iclass 16, count 2 2006.173.21:56:59.31#ibcon#about to write, iclass 16, count 2 2006.173.21:56:59.31#ibcon#wrote, iclass 16, count 2 2006.173.21:56:59.31#ibcon#about to read 3, iclass 16, count 2 2006.173.21:56:59.33#ibcon#read 3, iclass 16, count 2 2006.173.21:56:59.33#ibcon#about to read 4, iclass 16, count 2 2006.173.21:56:59.33#ibcon#read 4, iclass 16, count 2 2006.173.21:56:59.33#ibcon#about to read 5, iclass 16, count 2 2006.173.21:56:59.33#ibcon#read 5, iclass 16, count 2 2006.173.21:56:59.33#ibcon#about to read 6, iclass 16, count 2 2006.173.21:56:59.33#ibcon#read 6, iclass 16, count 2 2006.173.21:56:59.33#ibcon#end of sib2, iclass 16, count 2 2006.173.21:56:59.33#ibcon#*mode == 0, iclass 16, count 2 2006.173.21:56:59.33#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.21:56:59.33#ibcon#[27=AT05-04\r\n] 2006.173.21:56:59.33#ibcon#*before write, iclass 16, count 2 2006.173.21:56:59.33#ibcon#enter sib2, iclass 16, count 2 2006.173.21:56:59.33#ibcon#flushed, iclass 16, count 2 2006.173.21:56:59.33#ibcon#about to write, iclass 16, count 2 2006.173.21:56:59.33#ibcon#wrote, iclass 16, count 2 2006.173.21:56:59.33#ibcon#about to read 3, iclass 16, count 2 2006.173.21:56:59.36#ibcon#read 3, iclass 16, count 2 2006.173.21:56:59.36#ibcon#about to read 4, iclass 16, count 2 2006.173.21:56:59.36#ibcon#read 4, iclass 16, count 2 2006.173.21:56:59.36#ibcon#about to read 5, iclass 16, count 2 2006.173.21:56:59.36#ibcon#read 5, iclass 16, count 2 2006.173.21:56:59.36#ibcon#about to read 6, iclass 16, count 2 2006.173.21:56:59.36#ibcon#read 6, iclass 16, count 2 2006.173.21:56:59.36#ibcon#end of sib2, iclass 16, count 2 2006.173.21:56:59.36#ibcon#*after write, iclass 16, count 2 2006.173.21:56:59.36#ibcon#*before return 0, iclass 16, count 2 2006.173.21:56:59.36#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.21:56:59.36#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.21:56:59.36#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.21:56:59.36#ibcon#ireg 7 cls_cnt 0 2006.173.21:56:59.36#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.21:56:59.48#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.21:56:59.48#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.21:56:59.48#ibcon#enter wrdev, iclass 16, count 0 2006.173.21:56:59.48#ibcon#first serial, iclass 16, count 0 2006.173.21:56:59.48#ibcon#enter sib2, iclass 16, count 0 2006.173.21:56:59.48#ibcon#flushed, iclass 16, count 0 2006.173.21:56:59.48#ibcon#about to write, iclass 16, count 0 2006.173.21:56:59.48#ibcon#wrote, iclass 16, count 0 2006.173.21:56:59.48#ibcon#about to read 3, iclass 16, count 0 2006.173.21:56:59.50#ibcon#read 3, iclass 16, count 0 2006.173.21:56:59.50#ibcon#about to read 4, iclass 16, count 0 2006.173.21:56:59.50#ibcon#read 4, iclass 16, count 0 2006.173.21:56:59.50#ibcon#about to read 5, iclass 16, count 0 2006.173.21:56:59.50#ibcon#read 5, iclass 16, count 0 2006.173.21:56:59.50#ibcon#about to read 6, iclass 16, count 0 2006.173.21:56:59.50#ibcon#read 6, iclass 16, count 0 2006.173.21:56:59.50#ibcon#end of sib2, iclass 16, count 0 2006.173.21:56:59.50#ibcon#*mode == 0, iclass 16, count 0 2006.173.21:56:59.50#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.21:56:59.50#ibcon#[27=USB\r\n] 2006.173.21:56:59.50#ibcon#*before write, iclass 16, count 0 2006.173.21:56:59.50#ibcon#enter sib2, iclass 16, count 0 2006.173.21:56:59.50#ibcon#flushed, iclass 16, count 0 2006.173.21:56:59.50#ibcon#about to write, iclass 16, count 0 2006.173.21:56:59.50#ibcon#wrote, iclass 16, count 0 2006.173.21:56:59.50#ibcon#about to read 3, iclass 16, count 0 2006.173.21:56:59.53#ibcon#read 3, iclass 16, count 0 2006.173.21:56:59.53#ibcon#about to read 4, iclass 16, count 0 2006.173.21:56:59.53#ibcon#read 4, iclass 16, count 0 2006.173.21:56:59.53#ibcon#about to read 5, iclass 16, count 0 2006.173.21:56:59.53#ibcon#read 5, iclass 16, count 0 2006.173.21:56:59.53#ibcon#about to read 6, iclass 16, count 0 2006.173.21:56:59.53#ibcon#read 6, iclass 16, count 0 2006.173.21:56:59.53#ibcon#end of sib2, iclass 16, count 0 2006.173.21:56:59.53#ibcon#*after write, iclass 16, count 0 2006.173.21:56:59.53#ibcon#*before return 0, iclass 16, count 0 2006.173.21:56:59.53#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.21:56:59.53#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.21:56:59.53#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.21:56:59.53#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.21:56:59.53$vck44/vblo=6,719.99 2006.173.21:56:59.53#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.21:56:59.53#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.21:56:59.53#ibcon#ireg 17 cls_cnt 0 2006.173.21:56:59.53#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.21:56:59.53#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.21:56:59.53#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.21:56:59.53#ibcon#enter wrdev, iclass 18, count 0 2006.173.21:56:59.53#ibcon#first serial, iclass 18, count 0 2006.173.21:56:59.53#ibcon#enter sib2, iclass 18, count 0 2006.173.21:56:59.53#ibcon#flushed, iclass 18, count 0 2006.173.21:56:59.53#ibcon#about to write, iclass 18, count 0 2006.173.21:56:59.53#ibcon#wrote, iclass 18, count 0 2006.173.21:56:59.53#ibcon#about to read 3, iclass 18, count 0 2006.173.21:56:59.55#ibcon#read 3, iclass 18, count 0 2006.173.21:56:59.55#ibcon#about to read 4, iclass 18, count 0 2006.173.21:56:59.55#ibcon#read 4, iclass 18, count 0 2006.173.21:56:59.55#ibcon#about to read 5, iclass 18, count 0 2006.173.21:56:59.55#ibcon#read 5, iclass 18, count 0 2006.173.21:56:59.55#ibcon#about to read 6, iclass 18, count 0 2006.173.21:56:59.55#ibcon#read 6, iclass 18, count 0 2006.173.21:56:59.55#ibcon#end of sib2, iclass 18, count 0 2006.173.21:56:59.55#ibcon#*mode == 0, iclass 18, count 0 2006.173.21:56:59.55#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.21:56:59.55#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.21:56:59.55#ibcon#*before write, iclass 18, count 0 2006.173.21:56:59.55#ibcon#enter sib2, iclass 18, count 0 2006.173.21:56:59.55#ibcon#flushed, iclass 18, count 0 2006.173.21:56:59.55#ibcon#about to write, iclass 18, count 0 2006.173.21:56:59.55#ibcon#wrote, iclass 18, count 0 2006.173.21:56:59.55#ibcon#about to read 3, iclass 18, count 0 2006.173.21:56:59.59#ibcon#read 3, iclass 18, count 0 2006.173.21:56:59.59#ibcon#about to read 4, iclass 18, count 0 2006.173.21:56:59.59#ibcon#read 4, iclass 18, count 0 2006.173.21:56:59.59#ibcon#about to read 5, iclass 18, count 0 2006.173.21:56:59.59#ibcon#read 5, iclass 18, count 0 2006.173.21:56:59.59#ibcon#about to read 6, iclass 18, count 0 2006.173.21:56:59.59#ibcon#read 6, iclass 18, count 0 2006.173.21:56:59.59#ibcon#end of sib2, iclass 18, count 0 2006.173.21:56:59.59#ibcon#*after write, iclass 18, count 0 2006.173.21:56:59.59#ibcon#*before return 0, iclass 18, count 0 2006.173.21:56:59.59#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.21:56:59.59#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.21:56:59.59#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.21:56:59.59#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.21:56:59.59$vck44/vb=6,4 2006.173.21:56:59.59#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.21:56:59.59#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.21:56:59.59#ibcon#ireg 11 cls_cnt 2 2006.173.21:56:59.59#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.21:56:59.65#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.21:56:59.65#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.21:56:59.65#ibcon#enter wrdev, iclass 20, count 2 2006.173.21:56:59.65#ibcon#first serial, iclass 20, count 2 2006.173.21:56:59.65#ibcon#enter sib2, iclass 20, count 2 2006.173.21:56:59.65#ibcon#flushed, iclass 20, count 2 2006.173.21:56:59.65#ibcon#about to write, iclass 20, count 2 2006.173.21:56:59.65#ibcon#wrote, iclass 20, count 2 2006.173.21:56:59.65#ibcon#about to read 3, iclass 20, count 2 2006.173.21:56:59.67#ibcon#read 3, iclass 20, count 2 2006.173.21:56:59.67#ibcon#about to read 4, iclass 20, count 2 2006.173.21:56:59.67#ibcon#read 4, iclass 20, count 2 2006.173.21:56:59.67#ibcon#about to read 5, iclass 20, count 2 2006.173.21:56:59.67#ibcon#read 5, iclass 20, count 2 2006.173.21:56:59.67#ibcon#about to read 6, iclass 20, count 2 2006.173.21:56:59.67#ibcon#read 6, iclass 20, count 2 2006.173.21:56:59.67#ibcon#end of sib2, iclass 20, count 2 2006.173.21:56:59.67#ibcon#*mode == 0, iclass 20, count 2 2006.173.21:56:59.67#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.21:56:59.67#ibcon#[27=AT06-04\r\n] 2006.173.21:56:59.67#ibcon#*before write, iclass 20, count 2 2006.173.21:56:59.67#ibcon#enter sib2, iclass 20, count 2 2006.173.21:56:59.67#ibcon#flushed, iclass 20, count 2 2006.173.21:56:59.67#ibcon#about to write, iclass 20, count 2 2006.173.21:56:59.67#ibcon#wrote, iclass 20, count 2 2006.173.21:56:59.67#ibcon#about to read 3, iclass 20, count 2 2006.173.21:56:59.70#ibcon#read 3, iclass 20, count 2 2006.173.21:56:59.70#ibcon#about to read 4, iclass 20, count 2 2006.173.21:56:59.70#ibcon#read 4, iclass 20, count 2 2006.173.21:56:59.70#ibcon#about to read 5, iclass 20, count 2 2006.173.21:56:59.70#ibcon#read 5, iclass 20, count 2 2006.173.21:56:59.70#ibcon#about to read 6, iclass 20, count 2 2006.173.21:56:59.70#ibcon#read 6, iclass 20, count 2 2006.173.21:56:59.70#ibcon#end of sib2, iclass 20, count 2 2006.173.21:56:59.70#ibcon#*after write, iclass 20, count 2 2006.173.21:56:59.70#ibcon#*before return 0, iclass 20, count 2 2006.173.21:56:59.70#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.21:56:59.70#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.21:56:59.70#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.21:56:59.70#ibcon#ireg 7 cls_cnt 0 2006.173.21:56:59.70#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.21:56:59.82#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.21:56:59.82#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.21:56:59.82#ibcon#enter wrdev, iclass 20, count 0 2006.173.21:56:59.82#ibcon#first serial, iclass 20, count 0 2006.173.21:56:59.82#ibcon#enter sib2, iclass 20, count 0 2006.173.21:56:59.82#ibcon#flushed, iclass 20, count 0 2006.173.21:56:59.82#ibcon#about to write, iclass 20, count 0 2006.173.21:56:59.82#ibcon#wrote, iclass 20, count 0 2006.173.21:56:59.82#ibcon#about to read 3, iclass 20, count 0 2006.173.21:56:59.84#ibcon#read 3, iclass 20, count 0 2006.173.21:56:59.84#ibcon#about to read 4, iclass 20, count 0 2006.173.21:56:59.84#ibcon#read 4, iclass 20, count 0 2006.173.21:56:59.84#ibcon#about to read 5, iclass 20, count 0 2006.173.21:56:59.84#ibcon#read 5, iclass 20, count 0 2006.173.21:56:59.84#ibcon#about to read 6, iclass 20, count 0 2006.173.21:56:59.84#ibcon#read 6, iclass 20, count 0 2006.173.21:56:59.84#ibcon#end of sib2, iclass 20, count 0 2006.173.21:56:59.84#ibcon#*mode == 0, iclass 20, count 0 2006.173.21:56:59.84#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.21:56:59.84#ibcon#[27=USB\r\n] 2006.173.21:56:59.84#ibcon#*before write, iclass 20, count 0 2006.173.21:56:59.84#ibcon#enter sib2, iclass 20, count 0 2006.173.21:56:59.84#ibcon#flushed, iclass 20, count 0 2006.173.21:56:59.84#ibcon#about to write, iclass 20, count 0 2006.173.21:56:59.84#ibcon#wrote, iclass 20, count 0 2006.173.21:56:59.84#ibcon#about to read 3, iclass 20, count 0 2006.173.21:56:59.87#ibcon#read 3, iclass 20, count 0 2006.173.21:56:59.87#ibcon#about to read 4, iclass 20, count 0 2006.173.21:56:59.87#ibcon#read 4, iclass 20, count 0 2006.173.21:56:59.87#ibcon#about to read 5, iclass 20, count 0 2006.173.21:56:59.87#ibcon#read 5, iclass 20, count 0 2006.173.21:56:59.87#ibcon#about to read 6, iclass 20, count 0 2006.173.21:56:59.87#ibcon#read 6, iclass 20, count 0 2006.173.21:56:59.87#ibcon#end of sib2, iclass 20, count 0 2006.173.21:56:59.87#ibcon#*after write, iclass 20, count 0 2006.173.21:56:59.87#ibcon#*before return 0, iclass 20, count 0 2006.173.21:56:59.87#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.21:56:59.87#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.21:56:59.87#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.21:56:59.87#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.21:56:59.87$vck44/vblo=7,734.99 2006.173.21:56:59.87#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.21:56:59.87#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.21:56:59.87#ibcon#ireg 17 cls_cnt 0 2006.173.21:56:59.87#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.21:56:59.87#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.21:56:59.87#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.21:56:59.87#ibcon#enter wrdev, iclass 22, count 0 2006.173.21:56:59.87#ibcon#first serial, iclass 22, count 0 2006.173.21:56:59.87#ibcon#enter sib2, iclass 22, count 0 2006.173.21:56:59.87#ibcon#flushed, iclass 22, count 0 2006.173.21:56:59.87#ibcon#about to write, iclass 22, count 0 2006.173.21:56:59.87#ibcon#wrote, iclass 22, count 0 2006.173.21:56:59.87#ibcon#about to read 3, iclass 22, count 0 2006.173.21:56:59.89#ibcon#read 3, iclass 22, count 0 2006.173.21:56:59.89#ibcon#about to read 4, iclass 22, count 0 2006.173.21:56:59.89#ibcon#read 4, iclass 22, count 0 2006.173.21:56:59.89#ibcon#about to read 5, iclass 22, count 0 2006.173.21:56:59.89#ibcon#read 5, iclass 22, count 0 2006.173.21:56:59.89#ibcon#about to read 6, iclass 22, count 0 2006.173.21:56:59.89#ibcon#read 6, iclass 22, count 0 2006.173.21:56:59.89#ibcon#end of sib2, iclass 22, count 0 2006.173.21:56:59.89#ibcon#*mode == 0, iclass 22, count 0 2006.173.21:56:59.89#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.21:56:59.89#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.21:56:59.89#ibcon#*before write, iclass 22, count 0 2006.173.21:56:59.89#ibcon#enter sib2, iclass 22, count 0 2006.173.21:56:59.89#ibcon#flushed, iclass 22, count 0 2006.173.21:56:59.89#ibcon#about to write, iclass 22, count 0 2006.173.21:56:59.89#ibcon#wrote, iclass 22, count 0 2006.173.21:56:59.89#ibcon#about to read 3, iclass 22, count 0 2006.173.21:56:59.93#ibcon#read 3, iclass 22, count 0 2006.173.21:56:59.93#ibcon#about to read 4, iclass 22, count 0 2006.173.21:56:59.93#ibcon#read 4, iclass 22, count 0 2006.173.21:56:59.93#ibcon#about to read 5, iclass 22, count 0 2006.173.21:56:59.93#ibcon#read 5, iclass 22, count 0 2006.173.21:56:59.93#ibcon#about to read 6, iclass 22, count 0 2006.173.21:56:59.93#ibcon#read 6, iclass 22, count 0 2006.173.21:56:59.93#ibcon#end of sib2, iclass 22, count 0 2006.173.21:56:59.93#ibcon#*after write, iclass 22, count 0 2006.173.21:56:59.93#ibcon#*before return 0, iclass 22, count 0 2006.173.21:56:59.93#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.21:56:59.93#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.21:56:59.93#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.21:56:59.93#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.21:56:59.93$vck44/vb=7,4 2006.173.21:56:59.93#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.21:56:59.93#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.21:56:59.93#ibcon#ireg 11 cls_cnt 2 2006.173.21:56:59.93#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.21:56:59.99#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.21:56:59.99#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.21:56:59.99#ibcon#enter wrdev, iclass 24, count 2 2006.173.21:56:59.99#ibcon#first serial, iclass 24, count 2 2006.173.21:56:59.99#ibcon#enter sib2, iclass 24, count 2 2006.173.21:56:59.99#ibcon#flushed, iclass 24, count 2 2006.173.21:56:59.99#ibcon#about to write, iclass 24, count 2 2006.173.21:56:59.99#ibcon#wrote, iclass 24, count 2 2006.173.21:56:59.99#ibcon#about to read 3, iclass 24, count 2 2006.173.21:57:00.01#ibcon#read 3, iclass 24, count 2 2006.173.21:57:00.01#ibcon#about to read 4, iclass 24, count 2 2006.173.21:57:00.01#ibcon#read 4, iclass 24, count 2 2006.173.21:57:00.01#ibcon#about to read 5, iclass 24, count 2 2006.173.21:57:00.01#ibcon#read 5, iclass 24, count 2 2006.173.21:57:00.01#ibcon#about to read 6, iclass 24, count 2 2006.173.21:57:00.01#ibcon#read 6, iclass 24, count 2 2006.173.21:57:00.01#ibcon#end of sib2, iclass 24, count 2 2006.173.21:57:00.01#ibcon#*mode == 0, iclass 24, count 2 2006.173.21:57:00.01#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.21:57:00.01#ibcon#[27=AT07-04\r\n] 2006.173.21:57:00.01#ibcon#*before write, iclass 24, count 2 2006.173.21:57:00.01#ibcon#enter sib2, iclass 24, count 2 2006.173.21:57:00.01#ibcon#flushed, iclass 24, count 2 2006.173.21:57:00.01#ibcon#about to write, iclass 24, count 2 2006.173.21:57:00.01#ibcon#wrote, iclass 24, count 2 2006.173.21:57:00.01#ibcon#about to read 3, iclass 24, count 2 2006.173.21:57:00.04#ibcon#read 3, iclass 24, count 2 2006.173.21:57:00.04#ibcon#about to read 4, iclass 24, count 2 2006.173.21:57:00.04#ibcon#read 4, iclass 24, count 2 2006.173.21:57:00.04#ibcon#about to read 5, iclass 24, count 2 2006.173.21:57:00.04#ibcon#read 5, iclass 24, count 2 2006.173.21:57:00.04#ibcon#about to read 6, iclass 24, count 2 2006.173.21:57:00.04#ibcon#read 6, iclass 24, count 2 2006.173.21:57:00.04#ibcon#end of sib2, iclass 24, count 2 2006.173.21:57:00.04#ibcon#*after write, iclass 24, count 2 2006.173.21:57:00.04#ibcon#*before return 0, iclass 24, count 2 2006.173.21:57:00.04#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.21:57:00.04#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.21:57:00.04#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.21:57:00.04#ibcon#ireg 7 cls_cnt 0 2006.173.21:57:00.04#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.21:57:00.16#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.21:57:00.16#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.21:57:00.16#ibcon#enter wrdev, iclass 24, count 0 2006.173.21:57:00.16#ibcon#first serial, iclass 24, count 0 2006.173.21:57:00.16#ibcon#enter sib2, iclass 24, count 0 2006.173.21:57:00.16#ibcon#flushed, iclass 24, count 0 2006.173.21:57:00.16#ibcon#about to write, iclass 24, count 0 2006.173.21:57:00.16#ibcon#wrote, iclass 24, count 0 2006.173.21:57:00.16#ibcon#about to read 3, iclass 24, count 0 2006.173.21:57:00.18#ibcon#read 3, iclass 24, count 0 2006.173.21:57:00.18#ibcon#about to read 4, iclass 24, count 0 2006.173.21:57:00.18#ibcon#read 4, iclass 24, count 0 2006.173.21:57:00.18#ibcon#about to read 5, iclass 24, count 0 2006.173.21:57:00.18#ibcon#read 5, iclass 24, count 0 2006.173.21:57:00.18#ibcon#about to read 6, iclass 24, count 0 2006.173.21:57:00.18#ibcon#read 6, iclass 24, count 0 2006.173.21:57:00.18#ibcon#end of sib2, iclass 24, count 0 2006.173.21:57:00.18#ibcon#*mode == 0, iclass 24, count 0 2006.173.21:57:00.18#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.21:57:00.18#ibcon#[27=USB\r\n] 2006.173.21:57:00.18#ibcon#*before write, iclass 24, count 0 2006.173.21:57:00.18#ibcon#enter sib2, iclass 24, count 0 2006.173.21:57:00.18#ibcon#flushed, iclass 24, count 0 2006.173.21:57:00.18#ibcon#about to write, iclass 24, count 0 2006.173.21:57:00.18#ibcon#wrote, iclass 24, count 0 2006.173.21:57:00.18#ibcon#about to read 3, iclass 24, count 0 2006.173.21:57:00.21#ibcon#read 3, iclass 24, count 0 2006.173.21:57:00.21#ibcon#about to read 4, iclass 24, count 0 2006.173.21:57:00.21#ibcon#read 4, iclass 24, count 0 2006.173.21:57:00.21#ibcon#about to read 5, iclass 24, count 0 2006.173.21:57:00.21#ibcon#read 5, iclass 24, count 0 2006.173.21:57:00.21#ibcon#about to read 6, iclass 24, count 0 2006.173.21:57:00.21#ibcon#read 6, iclass 24, count 0 2006.173.21:57:00.21#ibcon#end of sib2, iclass 24, count 0 2006.173.21:57:00.21#ibcon#*after write, iclass 24, count 0 2006.173.21:57:00.21#ibcon#*before return 0, iclass 24, count 0 2006.173.21:57:00.21#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.21:57:00.21#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.21:57:00.21#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.21:57:00.21#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.21:57:00.21$vck44/vblo=8,744.99 2006.173.21:57:00.21#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.21:57:00.21#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.21:57:00.21#ibcon#ireg 17 cls_cnt 0 2006.173.21:57:00.21#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.21:57:00.21#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.21:57:00.21#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.21:57:00.21#ibcon#enter wrdev, iclass 26, count 0 2006.173.21:57:00.21#ibcon#first serial, iclass 26, count 0 2006.173.21:57:00.21#ibcon#enter sib2, iclass 26, count 0 2006.173.21:57:00.21#ibcon#flushed, iclass 26, count 0 2006.173.21:57:00.21#ibcon#about to write, iclass 26, count 0 2006.173.21:57:00.21#ibcon#wrote, iclass 26, count 0 2006.173.21:57:00.21#ibcon#about to read 3, iclass 26, count 0 2006.173.21:57:00.23#ibcon#read 3, iclass 26, count 0 2006.173.21:57:00.23#ibcon#about to read 4, iclass 26, count 0 2006.173.21:57:00.23#ibcon#read 4, iclass 26, count 0 2006.173.21:57:00.23#ibcon#about to read 5, iclass 26, count 0 2006.173.21:57:00.23#ibcon#read 5, iclass 26, count 0 2006.173.21:57:00.23#ibcon#about to read 6, iclass 26, count 0 2006.173.21:57:00.23#ibcon#read 6, iclass 26, count 0 2006.173.21:57:00.23#ibcon#end of sib2, iclass 26, count 0 2006.173.21:57:00.23#ibcon#*mode == 0, iclass 26, count 0 2006.173.21:57:00.23#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.21:57:00.23#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.21:57:00.23#ibcon#*before write, iclass 26, count 0 2006.173.21:57:00.23#ibcon#enter sib2, iclass 26, count 0 2006.173.21:57:00.23#ibcon#flushed, iclass 26, count 0 2006.173.21:57:00.23#ibcon#about to write, iclass 26, count 0 2006.173.21:57:00.23#ibcon#wrote, iclass 26, count 0 2006.173.21:57:00.23#ibcon#about to read 3, iclass 26, count 0 2006.173.21:57:00.27#ibcon#read 3, iclass 26, count 0 2006.173.21:57:00.27#ibcon#about to read 4, iclass 26, count 0 2006.173.21:57:00.27#ibcon#read 4, iclass 26, count 0 2006.173.21:57:00.27#ibcon#about to read 5, iclass 26, count 0 2006.173.21:57:00.27#ibcon#read 5, iclass 26, count 0 2006.173.21:57:00.27#ibcon#about to read 6, iclass 26, count 0 2006.173.21:57:00.27#ibcon#read 6, iclass 26, count 0 2006.173.21:57:00.27#ibcon#end of sib2, iclass 26, count 0 2006.173.21:57:00.27#ibcon#*after write, iclass 26, count 0 2006.173.21:57:00.27#ibcon#*before return 0, iclass 26, count 0 2006.173.21:57:00.27#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.21:57:00.27#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.21:57:00.27#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.21:57:00.27#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.21:57:00.27$vck44/vb=8,4 2006.173.21:57:00.27#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.21:57:00.27#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.21:57:00.27#ibcon#ireg 11 cls_cnt 2 2006.173.21:57:00.27#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.21:57:00.33#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.21:57:00.33#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.21:57:00.33#ibcon#enter wrdev, iclass 28, count 2 2006.173.21:57:00.33#ibcon#first serial, iclass 28, count 2 2006.173.21:57:00.33#ibcon#enter sib2, iclass 28, count 2 2006.173.21:57:00.33#ibcon#flushed, iclass 28, count 2 2006.173.21:57:00.33#ibcon#about to write, iclass 28, count 2 2006.173.21:57:00.33#ibcon#wrote, iclass 28, count 2 2006.173.21:57:00.33#ibcon#about to read 3, iclass 28, count 2 2006.173.21:57:00.35#ibcon#read 3, iclass 28, count 2 2006.173.21:57:00.35#ibcon#about to read 4, iclass 28, count 2 2006.173.21:57:00.35#ibcon#read 4, iclass 28, count 2 2006.173.21:57:00.35#ibcon#about to read 5, iclass 28, count 2 2006.173.21:57:00.35#ibcon#read 5, iclass 28, count 2 2006.173.21:57:00.35#ibcon#about to read 6, iclass 28, count 2 2006.173.21:57:00.35#ibcon#read 6, iclass 28, count 2 2006.173.21:57:00.35#ibcon#end of sib2, iclass 28, count 2 2006.173.21:57:00.35#ibcon#*mode == 0, iclass 28, count 2 2006.173.21:57:00.35#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.21:57:00.35#ibcon#[27=AT08-04\r\n] 2006.173.21:57:00.35#ibcon#*before write, iclass 28, count 2 2006.173.21:57:00.35#ibcon#enter sib2, iclass 28, count 2 2006.173.21:57:00.35#ibcon#flushed, iclass 28, count 2 2006.173.21:57:00.35#ibcon#about to write, iclass 28, count 2 2006.173.21:57:00.35#ibcon#wrote, iclass 28, count 2 2006.173.21:57:00.35#ibcon#about to read 3, iclass 28, count 2 2006.173.21:57:00.38#ibcon#read 3, iclass 28, count 2 2006.173.21:57:00.38#ibcon#about to read 4, iclass 28, count 2 2006.173.21:57:00.38#ibcon#read 4, iclass 28, count 2 2006.173.21:57:00.38#ibcon#about to read 5, iclass 28, count 2 2006.173.21:57:00.38#ibcon#read 5, iclass 28, count 2 2006.173.21:57:00.38#ibcon#about to read 6, iclass 28, count 2 2006.173.21:57:00.38#ibcon#read 6, iclass 28, count 2 2006.173.21:57:00.38#ibcon#end of sib2, iclass 28, count 2 2006.173.21:57:00.38#ibcon#*after write, iclass 28, count 2 2006.173.21:57:00.38#ibcon#*before return 0, iclass 28, count 2 2006.173.21:57:00.38#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.21:57:00.38#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.21:57:00.38#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.21:57:00.38#ibcon#ireg 7 cls_cnt 0 2006.173.21:57:00.38#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.21:57:00.50#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.21:57:00.50#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.21:57:00.50#ibcon#enter wrdev, iclass 28, count 0 2006.173.21:57:00.50#ibcon#first serial, iclass 28, count 0 2006.173.21:57:00.50#ibcon#enter sib2, iclass 28, count 0 2006.173.21:57:00.50#ibcon#flushed, iclass 28, count 0 2006.173.21:57:00.50#ibcon#about to write, iclass 28, count 0 2006.173.21:57:00.50#ibcon#wrote, iclass 28, count 0 2006.173.21:57:00.50#ibcon#about to read 3, iclass 28, count 0 2006.173.21:57:00.52#ibcon#read 3, iclass 28, count 0 2006.173.21:57:00.52#ibcon#about to read 4, iclass 28, count 0 2006.173.21:57:00.52#ibcon#read 4, iclass 28, count 0 2006.173.21:57:00.52#ibcon#about to read 5, iclass 28, count 0 2006.173.21:57:00.52#ibcon#read 5, iclass 28, count 0 2006.173.21:57:00.52#ibcon#about to read 6, iclass 28, count 0 2006.173.21:57:00.52#ibcon#read 6, iclass 28, count 0 2006.173.21:57:00.52#ibcon#end of sib2, iclass 28, count 0 2006.173.21:57:00.52#ibcon#*mode == 0, iclass 28, count 0 2006.173.21:57:00.52#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.21:57:00.52#ibcon#[27=USB\r\n] 2006.173.21:57:00.52#ibcon#*before write, iclass 28, count 0 2006.173.21:57:00.52#ibcon#enter sib2, iclass 28, count 0 2006.173.21:57:00.52#ibcon#flushed, iclass 28, count 0 2006.173.21:57:00.52#ibcon#about to write, iclass 28, count 0 2006.173.21:57:00.52#ibcon#wrote, iclass 28, count 0 2006.173.21:57:00.52#ibcon#about to read 3, iclass 28, count 0 2006.173.21:57:00.55#ibcon#read 3, iclass 28, count 0 2006.173.21:57:00.55#ibcon#about to read 4, iclass 28, count 0 2006.173.21:57:00.55#ibcon#read 4, iclass 28, count 0 2006.173.21:57:00.55#ibcon#about to read 5, iclass 28, count 0 2006.173.21:57:00.55#ibcon#read 5, iclass 28, count 0 2006.173.21:57:00.55#ibcon#about to read 6, iclass 28, count 0 2006.173.21:57:00.55#ibcon#read 6, iclass 28, count 0 2006.173.21:57:00.55#ibcon#end of sib2, iclass 28, count 0 2006.173.21:57:00.55#ibcon#*after write, iclass 28, count 0 2006.173.21:57:00.55#ibcon#*before return 0, iclass 28, count 0 2006.173.21:57:00.55#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.21:57:00.55#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.21:57:00.55#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.21:57:00.55#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.21:57:00.55$vck44/vabw=wide 2006.173.21:57:00.55#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.21:57:00.55#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.21:57:00.55#ibcon#ireg 8 cls_cnt 0 2006.173.21:57:00.55#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.21:57:00.55#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.21:57:00.55#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.21:57:00.55#ibcon#enter wrdev, iclass 30, count 0 2006.173.21:57:00.55#ibcon#first serial, iclass 30, count 0 2006.173.21:57:00.55#ibcon#enter sib2, iclass 30, count 0 2006.173.21:57:00.55#ibcon#flushed, iclass 30, count 0 2006.173.21:57:00.55#ibcon#about to write, iclass 30, count 0 2006.173.21:57:00.55#ibcon#wrote, iclass 30, count 0 2006.173.21:57:00.55#ibcon#about to read 3, iclass 30, count 0 2006.173.21:57:00.57#ibcon#read 3, iclass 30, count 0 2006.173.21:57:00.57#ibcon#about to read 4, iclass 30, count 0 2006.173.21:57:00.57#ibcon#read 4, iclass 30, count 0 2006.173.21:57:00.57#ibcon#about to read 5, iclass 30, count 0 2006.173.21:57:00.57#ibcon#read 5, iclass 30, count 0 2006.173.21:57:00.57#ibcon#about to read 6, iclass 30, count 0 2006.173.21:57:00.57#ibcon#read 6, iclass 30, count 0 2006.173.21:57:00.57#ibcon#end of sib2, iclass 30, count 0 2006.173.21:57:00.57#ibcon#*mode == 0, iclass 30, count 0 2006.173.21:57:00.57#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.21:57:00.57#ibcon#[25=BW32\r\n] 2006.173.21:57:00.57#ibcon#*before write, iclass 30, count 0 2006.173.21:57:00.57#ibcon#enter sib2, iclass 30, count 0 2006.173.21:57:00.57#ibcon#flushed, iclass 30, count 0 2006.173.21:57:00.57#ibcon#about to write, iclass 30, count 0 2006.173.21:57:00.57#ibcon#wrote, iclass 30, count 0 2006.173.21:57:00.57#ibcon#about to read 3, iclass 30, count 0 2006.173.21:57:00.60#ibcon#read 3, iclass 30, count 0 2006.173.21:57:00.60#ibcon#about to read 4, iclass 30, count 0 2006.173.21:57:00.60#ibcon#read 4, iclass 30, count 0 2006.173.21:57:00.60#ibcon#about to read 5, iclass 30, count 0 2006.173.21:57:00.60#ibcon#read 5, iclass 30, count 0 2006.173.21:57:00.60#ibcon#about to read 6, iclass 30, count 0 2006.173.21:57:00.60#ibcon#read 6, iclass 30, count 0 2006.173.21:57:00.60#ibcon#end of sib2, iclass 30, count 0 2006.173.21:57:00.60#ibcon#*after write, iclass 30, count 0 2006.173.21:57:00.60#ibcon#*before return 0, iclass 30, count 0 2006.173.21:57:00.60#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.21:57:00.60#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.21:57:00.60#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.21:57:00.60#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.21:57:00.60$vck44/vbbw=wide 2006.173.21:57:00.60#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.21:57:00.60#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.21:57:00.60#ibcon#ireg 8 cls_cnt 0 2006.173.21:57:00.60#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.21:57:00.67#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.21:57:00.67#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.21:57:00.67#ibcon#enter wrdev, iclass 32, count 0 2006.173.21:57:00.67#ibcon#first serial, iclass 32, count 0 2006.173.21:57:00.67#ibcon#enter sib2, iclass 32, count 0 2006.173.21:57:00.67#ibcon#flushed, iclass 32, count 0 2006.173.21:57:00.67#ibcon#about to write, iclass 32, count 0 2006.173.21:57:00.67#ibcon#wrote, iclass 32, count 0 2006.173.21:57:00.67#ibcon#about to read 3, iclass 32, count 0 2006.173.21:57:00.69#ibcon#read 3, iclass 32, count 0 2006.173.21:57:00.69#ibcon#about to read 4, iclass 32, count 0 2006.173.21:57:00.69#ibcon#read 4, iclass 32, count 0 2006.173.21:57:00.69#ibcon#about to read 5, iclass 32, count 0 2006.173.21:57:00.69#ibcon#read 5, iclass 32, count 0 2006.173.21:57:00.69#ibcon#about to read 6, iclass 32, count 0 2006.173.21:57:00.69#ibcon#read 6, iclass 32, count 0 2006.173.21:57:00.69#ibcon#end of sib2, iclass 32, count 0 2006.173.21:57:00.69#ibcon#*mode == 0, iclass 32, count 0 2006.173.21:57:00.69#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.21:57:00.69#ibcon#[27=BW32\r\n] 2006.173.21:57:00.69#ibcon#*before write, iclass 32, count 0 2006.173.21:57:00.69#ibcon#enter sib2, iclass 32, count 0 2006.173.21:57:00.69#ibcon#flushed, iclass 32, count 0 2006.173.21:57:00.69#ibcon#about to write, iclass 32, count 0 2006.173.21:57:00.69#ibcon#wrote, iclass 32, count 0 2006.173.21:57:00.69#ibcon#about to read 3, iclass 32, count 0 2006.173.21:57:00.72#ibcon#read 3, iclass 32, count 0 2006.173.21:57:00.72#ibcon#about to read 4, iclass 32, count 0 2006.173.21:57:00.72#ibcon#read 4, iclass 32, count 0 2006.173.21:57:00.72#ibcon#about to read 5, iclass 32, count 0 2006.173.21:57:00.72#ibcon#read 5, iclass 32, count 0 2006.173.21:57:00.72#ibcon#about to read 6, iclass 32, count 0 2006.173.21:57:00.72#ibcon#read 6, iclass 32, count 0 2006.173.21:57:00.72#ibcon#end of sib2, iclass 32, count 0 2006.173.21:57:00.72#ibcon#*after write, iclass 32, count 0 2006.173.21:57:00.72#ibcon#*before return 0, iclass 32, count 0 2006.173.21:57:00.72#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.21:57:00.72#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.21:57:00.72#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.21:57:00.72#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.21:57:00.72$setupk4/ifdk4 2006.173.21:57:00.72$ifdk4/lo= 2006.173.21:57:00.72$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.21:57:00.72$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.21:57:00.72$ifdk4/patch= 2006.173.21:57:00.72$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.21:57:00.72$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.21:57:00.72$setupk4/!*+20s 2006.173.21:57:06.44#abcon#<5=/14 0.3 1.0 21.67 981003.3\r\n> 2006.173.21:57:06.46#abcon#{5=INTERFACE CLEAR} 2006.173.21:57:06.52#abcon#[5=S1D000X0/0*\r\n] 2006.173.21:57:15.20$setupk4/"tpicd 2006.173.21:57:15.20$setupk4/echo=off 2006.173.21:57:15.20$setupk4/xlog=off 2006.173.21:57:15.20:!2006.173.22:01:14 2006.173.21:57:27.14#trakl#Source acquired 2006.173.21:57:29.14#flagr#flagr/antenna,acquired 2006.173.22:01:14.00:preob 2006.173.22:01:15.13/onsource/TRACKING 2006.173.22:01:15.13:!2006.173.22:01:24 2006.173.22:01:24.00:"tape 2006.173.22:01:24.00:"st=record 2006.173.22:01:24.00:data_valid=on 2006.173.22:01:24.00:midob 2006.173.22:01:24.13/onsource/TRACKING 2006.173.22:01:24.13/wx/21.77,1003.4,97 2006.173.22:01:24.28/cable/+6.5165E-03 2006.173.22:01:25.37/va/01,07,usb,yes,34,37 2006.173.22:01:25.37/va/02,06,usb,yes,34,35 2006.173.22:01:25.37/va/03,05,usb,yes,43,45 2006.173.22:01:25.37/va/04,06,usb,yes,35,37 2006.173.22:01:25.37/va/05,04,usb,yes,27,28 2006.173.22:01:25.37/va/06,03,usb,yes,38,38 2006.173.22:01:25.37/va/07,04,usb,yes,31,32 2006.173.22:01:25.37/va/08,04,usb,yes,26,32 2006.173.22:01:25.60/valo/01,524.99,yes,locked 2006.173.22:01:25.60/valo/02,534.99,yes,locked 2006.173.22:01:25.60/valo/03,564.99,yes,locked 2006.173.22:01:25.60/valo/04,624.99,yes,locked 2006.173.22:01:25.60/valo/05,734.99,yes,locked 2006.173.22:01:25.60/valo/06,814.99,yes,locked 2006.173.22:01:25.60/valo/07,864.99,yes,locked 2006.173.22:01:25.60/valo/08,884.99,yes,locked 2006.173.22:01:26.69/vb/01,04,usb,yes,29,27 2006.173.22:01:26.69/vb/02,04,usb,yes,31,31 2006.173.22:01:26.69/vb/03,04,usb,yes,28,31 2006.173.22:01:26.69/vb/04,04,usb,yes,32,31 2006.173.22:01:26.69/vb/05,04,usb,yes,25,27 2006.173.22:01:26.69/vb/06,04,usb,yes,29,26 2006.173.22:01:26.69/vb/07,04,usb,yes,29,29 2006.173.22:01:26.69/vb/08,04,usb,yes,27,30 2006.173.22:01:26.92/vblo/01,629.99,yes,locked 2006.173.22:01:26.92/vblo/02,634.99,yes,locked 2006.173.22:01:26.92/vblo/03,649.99,yes,locked 2006.173.22:01:26.92/vblo/04,679.99,yes,locked 2006.173.22:01:26.92/vblo/05,709.99,yes,locked 2006.173.22:01:26.92/vblo/06,719.99,yes,locked 2006.173.22:01:26.92/vblo/07,734.99,yes,locked 2006.173.22:01:26.92/vblo/08,744.99,yes,locked 2006.173.22:01:27.07/vabw/8 2006.173.22:01:27.22/vbbw/8 2006.173.22:01:27.34/xfe/off,on,15.0 2006.173.22:01:27.73/ifatt/23,28,28,28 2006.173.22:01:28.08/fmout-gps/S +3.88E-07 2006.173.22:01:28.12:!2006.173.22:03:24 2006.173.22:03:24.00:data_valid=off 2006.173.22:03:24.00:"et 2006.173.22:03:24.00:!+3s 2006.173.22:03:27.01:"tape 2006.173.22:03:27.01:postob 2006.173.22:03:27.08/cable/+6.5152E-03 2006.173.22:03:27.08/wx/21.78,1003.4,97 2006.173.22:03:28.08/fmout-gps/S +3.89E-07 2006.173.22:03:28.08:scan_name=173-2209,jd0606,80 2006.173.22:03:28.08:source=2136+141,213901.31,142336.0,2000.0,ccw 2006.173.22:03:28.14#flagr#flagr/antenna,new-source 2006.173.22:03:29.14:checkk5 2006.173.22:03:29.50/chk_autoobs//k5ts1/ autoobs is running! 2006.173.22:03:29.88/chk_autoobs//k5ts2/ autoobs is running! 2006.173.22:03:30.29/chk_autoobs//k5ts3/ autoobs is running! 2006.173.22:03:30.69/chk_autoobs//k5ts4/ autoobs is running! 2006.173.22:03:31.09/chk_obsdata//k5ts1/T1732201??a.dat file size is correct (nominal:480MB, actual:476MB). 2006.173.22:03:31.49/chk_obsdata//k5ts2/T1732201??b.dat file size is correct (nominal:480MB, actual:476MB). 2006.173.22:03:31.88/chk_obsdata//k5ts3/T1732201??c.dat file size is correct (nominal:480MB, actual:476MB). 2006.173.22:03:32.31/chk_obsdata//k5ts4/T1732201??d.dat file size is correct (nominal:480MB, actual:476MB). 2006.173.22:03:33.03/k5log//k5ts1_log_newline 2006.173.22:03:33.74/k5log//k5ts2_log_newline 2006.173.22:03:34.45/k5log//k5ts3_log_newline 2006.173.22:03:35.15/k5log//k5ts4_log_newline 2006.173.22:03:35.18/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.22:03:35.18:setupk4=1 2006.173.22:03:35.18$setupk4/echo=on 2006.173.22:03:35.18$setupk4/pcalon 2006.173.22:03:35.18$pcalon/"no phase cal control is implemented here 2006.173.22:03:35.18$setupk4/"tpicd=stop 2006.173.22:03:35.18$setupk4/"rec=synch_on 2006.173.22:03:35.18$setupk4/"rec_mode=128 2006.173.22:03:35.18$setupk4/!* 2006.173.22:03:35.18$setupk4/recpk4 2006.173.22:03:35.18$recpk4/recpatch= 2006.173.22:03:35.18$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.22:03:35.18$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.22:03:35.18$setupk4/vck44 2006.173.22:03:35.18$vck44/valo=1,524.99 2006.173.22:03:35.18#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.22:03:35.18#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.22:03:35.18#ibcon#ireg 17 cls_cnt 0 2006.173.22:03:35.18#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.22:03:35.18#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.22:03:35.18#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.22:03:35.18#ibcon#enter wrdev, iclass 13, count 0 2006.173.22:03:35.18#ibcon#first serial, iclass 13, count 0 2006.173.22:03:35.18#ibcon#enter sib2, iclass 13, count 0 2006.173.22:03:35.18#ibcon#flushed, iclass 13, count 0 2006.173.22:03:35.18#ibcon#about to write, iclass 13, count 0 2006.173.22:03:35.18#ibcon#wrote, iclass 13, count 0 2006.173.22:03:35.18#ibcon#about to read 3, iclass 13, count 0 2006.173.22:03:35.20#ibcon#read 3, iclass 13, count 0 2006.173.22:03:35.20#ibcon#about to read 4, iclass 13, count 0 2006.173.22:03:35.20#ibcon#read 4, iclass 13, count 0 2006.173.22:03:35.20#ibcon#about to read 5, iclass 13, count 0 2006.173.22:03:35.20#ibcon#read 5, iclass 13, count 0 2006.173.22:03:35.20#ibcon#about to read 6, iclass 13, count 0 2006.173.22:03:35.20#ibcon#read 6, iclass 13, count 0 2006.173.22:03:35.20#ibcon#end of sib2, iclass 13, count 0 2006.173.22:03:35.20#ibcon#*mode == 0, iclass 13, count 0 2006.173.22:03:35.20#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.22:03:35.20#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.22:03:35.20#ibcon#*before write, iclass 13, count 0 2006.173.22:03:35.20#ibcon#enter sib2, iclass 13, count 0 2006.173.22:03:35.20#ibcon#flushed, iclass 13, count 0 2006.173.22:03:35.20#ibcon#about to write, iclass 13, count 0 2006.173.22:03:35.20#ibcon#wrote, iclass 13, count 0 2006.173.22:03:35.20#ibcon#about to read 3, iclass 13, count 0 2006.173.22:03:35.25#ibcon#read 3, iclass 13, count 0 2006.173.22:03:35.25#ibcon#about to read 4, iclass 13, count 0 2006.173.22:03:35.25#ibcon#read 4, iclass 13, count 0 2006.173.22:03:35.25#ibcon#about to read 5, iclass 13, count 0 2006.173.22:03:35.25#ibcon#read 5, iclass 13, count 0 2006.173.22:03:35.25#ibcon#about to read 6, iclass 13, count 0 2006.173.22:03:35.25#ibcon#read 6, iclass 13, count 0 2006.173.22:03:35.25#ibcon#end of sib2, iclass 13, count 0 2006.173.22:03:35.25#ibcon#*after write, iclass 13, count 0 2006.173.22:03:35.25#ibcon#*before return 0, iclass 13, count 0 2006.173.22:03:35.25#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.22:03:35.25#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.22:03:35.25#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.22:03:35.25#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.22:03:35.25$vck44/va=1,7 2006.173.22:03:35.25#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.22:03:35.25#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.22:03:35.25#ibcon#ireg 11 cls_cnt 2 2006.173.22:03:35.25#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.22:03:35.25#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.22:03:35.25#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.22:03:35.25#ibcon#enter wrdev, iclass 15, count 2 2006.173.22:03:35.25#ibcon#first serial, iclass 15, count 2 2006.173.22:03:35.25#ibcon#enter sib2, iclass 15, count 2 2006.173.22:03:35.25#ibcon#flushed, iclass 15, count 2 2006.173.22:03:35.25#ibcon#about to write, iclass 15, count 2 2006.173.22:03:35.25#ibcon#wrote, iclass 15, count 2 2006.173.22:03:35.25#ibcon#about to read 3, iclass 15, count 2 2006.173.22:03:35.27#ibcon#read 3, iclass 15, count 2 2006.173.22:03:35.27#ibcon#about to read 4, iclass 15, count 2 2006.173.22:03:35.27#ibcon#read 4, iclass 15, count 2 2006.173.22:03:35.27#ibcon#about to read 5, iclass 15, count 2 2006.173.22:03:35.27#ibcon#read 5, iclass 15, count 2 2006.173.22:03:35.27#ibcon#about to read 6, iclass 15, count 2 2006.173.22:03:35.27#ibcon#read 6, iclass 15, count 2 2006.173.22:03:35.27#ibcon#end of sib2, iclass 15, count 2 2006.173.22:03:35.27#ibcon#*mode == 0, iclass 15, count 2 2006.173.22:03:35.27#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.22:03:35.27#ibcon#[25=AT01-07\r\n] 2006.173.22:03:35.27#ibcon#*before write, iclass 15, count 2 2006.173.22:03:35.27#ibcon#enter sib2, iclass 15, count 2 2006.173.22:03:35.27#ibcon#flushed, iclass 15, count 2 2006.173.22:03:35.27#ibcon#about to write, iclass 15, count 2 2006.173.22:03:35.27#ibcon#wrote, iclass 15, count 2 2006.173.22:03:35.27#ibcon#about to read 3, iclass 15, count 2 2006.173.22:03:35.30#ibcon#read 3, iclass 15, count 2 2006.173.22:03:35.30#ibcon#about to read 4, iclass 15, count 2 2006.173.22:03:35.30#ibcon#read 4, iclass 15, count 2 2006.173.22:03:35.30#ibcon#about to read 5, iclass 15, count 2 2006.173.22:03:35.30#ibcon#read 5, iclass 15, count 2 2006.173.22:03:35.30#ibcon#about to read 6, iclass 15, count 2 2006.173.22:03:35.30#ibcon#read 6, iclass 15, count 2 2006.173.22:03:35.30#ibcon#end of sib2, iclass 15, count 2 2006.173.22:03:35.30#ibcon#*after write, iclass 15, count 2 2006.173.22:03:35.30#ibcon#*before return 0, iclass 15, count 2 2006.173.22:03:35.30#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.22:03:35.30#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.22:03:35.30#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.22:03:35.30#ibcon#ireg 7 cls_cnt 0 2006.173.22:03:35.30#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.22:03:35.42#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.22:03:35.42#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.22:03:35.42#ibcon#enter wrdev, iclass 15, count 0 2006.173.22:03:35.42#ibcon#first serial, iclass 15, count 0 2006.173.22:03:35.42#ibcon#enter sib2, iclass 15, count 0 2006.173.22:03:35.42#ibcon#flushed, iclass 15, count 0 2006.173.22:03:35.42#ibcon#about to write, iclass 15, count 0 2006.173.22:03:35.42#ibcon#wrote, iclass 15, count 0 2006.173.22:03:35.42#ibcon#about to read 3, iclass 15, count 0 2006.173.22:03:35.44#ibcon#read 3, iclass 15, count 0 2006.173.22:03:35.44#ibcon#about to read 4, iclass 15, count 0 2006.173.22:03:35.44#ibcon#read 4, iclass 15, count 0 2006.173.22:03:35.44#ibcon#about to read 5, iclass 15, count 0 2006.173.22:03:35.44#ibcon#read 5, iclass 15, count 0 2006.173.22:03:35.44#ibcon#about to read 6, iclass 15, count 0 2006.173.22:03:35.44#ibcon#read 6, iclass 15, count 0 2006.173.22:03:35.44#ibcon#end of sib2, iclass 15, count 0 2006.173.22:03:35.44#ibcon#*mode == 0, iclass 15, count 0 2006.173.22:03:35.44#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.22:03:35.44#ibcon#[25=USB\r\n] 2006.173.22:03:35.44#ibcon#*before write, iclass 15, count 0 2006.173.22:03:35.44#ibcon#enter sib2, iclass 15, count 0 2006.173.22:03:35.44#ibcon#flushed, iclass 15, count 0 2006.173.22:03:35.44#ibcon#about to write, iclass 15, count 0 2006.173.22:03:35.44#ibcon#wrote, iclass 15, count 0 2006.173.22:03:35.44#ibcon#about to read 3, iclass 15, count 0 2006.173.22:03:35.47#ibcon#read 3, iclass 15, count 0 2006.173.22:03:35.47#ibcon#about to read 4, iclass 15, count 0 2006.173.22:03:35.47#ibcon#read 4, iclass 15, count 0 2006.173.22:03:35.47#ibcon#about to read 5, iclass 15, count 0 2006.173.22:03:35.47#ibcon#read 5, iclass 15, count 0 2006.173.22:03:35.47#ibcon#about to read 6, iclass 15, count 0 2006.173.22:03:35.47#ibcon#read 6, iclass 15, count 0 2006.173.22:03:35.47#ibcon#end of sib2, iclass 15, count 0 2006.173.22:03:35.47#ibcon#*after write, iclass 15, count 0 2006.173.22:03:35.47#ibcon#*before return 0, iclass 15, count 0 2006.173.22:03:35.47#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.22:03:35.47#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.22:03:35.47#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.22:03:35.47#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.22:03:35.47$vck44/valo=2,534.99 2006.173.22:03:35.47#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.22:03:35.47#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.22:03:35.47#ibcon#ireg 17 cls_cnt 0 2006.173.22:03:35.47#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.22:03:35.47#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.22:03:35.47#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.22:03:35.47#ibcon#enter wrdev, iclass 17, count 0 2006.173.22:03:35.47#ibcon#first serial, iclass 17, count 0 2006.173.22:03:35.47#ibcon#enter sib2, iclass 17, count 0 2006.173.22:03:35.47#ibcon#flushed, iclass 17, count 0 2006.173.22:03:35.47#ibcon#about to write, iclass 17, count 0 2006.173.22:03:35.47#ibcon#wrote, iclass 17, count 0 2006.173.22:03:35.47#ibcon#about to read 3, iclass 17, count 0 2006.173.22:03:35.49#ibcon#read 3, iclass 17, count 0 2006.173.22:03:35.49#ibcon#about to read 4, iclass 17, count 0 2006.173.22:03:35.49#ibcon#read 4, iclass 17, count 0 2006.173.22:03:35.49#ibcon#about to read 5, iclass 17, count 0 2006.173.22:03:35.49#ibcon#read 5, iclass 17, count 0 2006.173.22:03:35.49#ibcon#about to read 6, iclass 17, count 0 2006.173.22:03:35.49#ibcon#read 6, iclass 17, count 0 2006.173.22:03:35.49#ibcon#end of sib2, iclass 17, count 0 2006.173.22:03:35.49#ibcon#*mode == 0, iclass 17, count 0 2006.173.22:03:35.49#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.22:03:35.49#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.22:03:35.49#ibcon#*before write, iclass 17, count 0 2006.173.22:03:35.49#ibcon#enter sib2, iclass 17, count 0 2006.173.22:03:35.49#ibcon#flushed, iclass 17, count 0 2006.173.22:03:35.49#ibcon#about to write, iclass 17, count 0 2006.173.22:03:35.49#ibcon#wrote, iclass 17, count 0 2006.173.22:03:35.49#ibcon#about to read 3, iclass 17, count 0 2006.173.22:03:35.53#ibcon#read 3, iclass 17, count 0 2006.173.22:03:35.53#ibcon#about to read 4, iclass 17, count 0 2006.173.22:03:35.53#ibcon#read 4, iclass 17, count 0 2006.173.22:03:35.53#ibcon#about to read 5, iclass 17, count 0 2006.173.22:03:35.53#ibcon#read 5, iclass 17, count 0 2006.173.22:03:35.53#ibcon#about to read 6, iclass 17, count 0 2006.173.22:03:35.53#ibcon#read 6, iclass 17, count 0 2006.173.22:03:35.53#ibcon#end of sib2, iclass 17, count 0 2006.173.22:03:35.53#ibcon#*after write, iclass 17, count 0 2006.173.22:03:35.53#ibcon#*before return 0, iclass 17, count 0 2006.173.22:03:35.53#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.22:03:35.53#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.22:03:35.53#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.22:03:35.53#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.22:03:35.53$vck44/va=2,6 2006.173.22:03:35.53#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.22:03:35.53#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.22:03:35.53#ibcon#ireg 11 cls_cnt 2 2006.173.22:03:35.53#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.22:03:35.59#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.22:03:35.59#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.22:03:35.59#ibcon#enter wrdev, iclass 19, count 2 2006.173.22:03:35.59#ibcon#first serial, iclass 19, count 2 2006.173.22:03:35.59#ibcon#enter sib2, iclass 19, count 2 2006.173.22:03:35.59#ibcon#flushed, iclass 19, count 2 2006.173.22:03:35.59#ibcon#about to write, iclass 19, count 2 2006.173.22:03:35.59#ibcon#wrote, iclass 19, count 2 2006.173.22:03:35.59#ibcon#about to read 3, iclass 19, count 2 2006.173.22:03:35.61#ibcon#read 3, iclass 19, count 2 2006.173.22:03:35.61#ibcon#about to read 4, iclass 19, count 2 2006.173.22:03:35.61#ibcon#read 4, iclass 19, count 2 2006.173.22:03:35.61#ibcon#about to read 5, iclass 19, count 2 2006.173.22:03:35.61#ibcon#read 5, iclass 19, count 2 2006.173.22:03:35.61#ibcon#about to read 6, iclass 19, count 2 2006.173.22:03:35.61#ibcon#read 6, iclass 19, count 2 2006.173.22:03:35.61#ibcon#end of sib2, iclass 19, count 2 2006.173.22:03:35.61#ibcon#*mode == 0, iclass 19, count 2 2006.173.22:03:35.61#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.22:03:35.61#ibcon#[25=AT02-06\r\n] 2006.173.22:03:35.61#ibcon#*before write, iclass 19, count 2 2006.173.22:03:35.61#ibcon#enter sib2, iclass 19, count 2 2006.173.22:03:35.61#ibcon#flushed, iclass 19, count 2 2006.173.22:03:35.61#ibcon#about to write, iclass 19, count 2 2006.173.22:03:35.61#ibcon#wrote, iclass 19, count 2 2006.173.22:03:35.61#ibcon#about to read 3, iclass 19, count 2 2006.173.22:03:35.64#ibcon#read 3, iclass 19, count 2 2006.173.22:03:35.64#ibcon#about to read 4, iclass 19, count 2 2006.173.22:03:35.64#ibcon#read 4, iclass 19, count 2 2006.173.22:03:35.64#ibcon#about to read 5, iclass 19, count 2 2006.173.22:03:35.64#ibcon#read 5, iclass 19, count 2 2006.173.22:03:35.64#ibcon#about to read 6, iclass 19, count 2 2006.173.22:03:35.64#ibcon#read 6, iclass 19, count 2 2006.173.22:03:35.64#ibcon#end of sib2, iclass 19, count 2 2006.173.22:03:35.64#ibcon#*after write, iclass 19, count 2 2006.173.22:03:35.64#ibcon#*before return 0, iclass 19, count 2 2006.173.22:03:35.64#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.22:03:35.64#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.22:03:35.64#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.22:03:35.64#ibcon#ireg 7 cls_cnt 0 2006.173.22:03:35.64#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.22:03:35.76#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.22:03:35.76#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.22:03:35.76#ibcon#enter wrdev, iclass 19, count 0 2006.173.22:03:35.76#ibcon#first serial, iclass 19, count 0 2006.173.22:03:35.76#ibcon#enter sib2, iclass 19, count 0 2006.173.22:03:35.76#ibcon#flushed, iclass 19, count 0 2006.173.22:03:35.76#ibcon#about to write, iclass 19, count 0 2006.173.22:03:35.76#ibcon#wrote, iclass 19, count 0 2006.173.22:03:35.76#ibcon#about to read 3, iclass 19, count 0 2006.173.22:03:35.78#ibcon#read 3, iclass 19, count 0 2006.173.22:03:35.78#ibcon#about to read 4, iclass 19, count 0 2006.173.22:03:35.78#ibcon#read 4, iclass 19, count 0 2006.173.22:03:35.78#ibcon#about to read 5, iclass 19, count 0 2006.173.22:03:35.78#ibcon#read 5, iclass 19, count 0 2006.173.22:03:35.78#ibcon#about to read 6, iclass 19, count 0 2006.173.22:03:35.78#ibcon#read 6, iclass 19, count 0 2006.173.22:03:35.78#ibcon#end of sib2, iclass 19, count 0 2006.173.22:03:35.78#ibcon#*mode == 0, iclass 19, count 0 2006.173.22:03:35.78#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.22:03:35.78#ibcon#[25=USB\r\n] 2006.173.22:03:35.78#ibcon#*before write, iclass 19, count 0 2006.173.22:03:35.78#ibcon#enter sib2, iclass 19, count 0 2006.173.22:03:35.78#ibcon#flushed, iclass 19, count 0 2006.173.22:03:35.78#ibcon#about to write, iclass 19, count 0 2006.173.22:03:35.78#ibcon#wrote, iclass 19, count 0 2006.173.22:03:35.78#ibcon#about to read 3, iclass 19, count 0 2006.173.22:03:35.81#ibcon#read 3, iclass 19, count 0 2006.173.22:03:35.81#ibcon#about to read 4, iclass 19, count 0 2006.173.22:03:35.81#ibcon#read 4, iclass 19, count 0 2006.173.22:03:35.81#ibcon#about to read 5, iclass 19, count 0 2006.173.22:03:35.81#ibcon#read 5, iclass 19, count 0 2006.173.22:03:35.81#ibcon#about to read 6, iclass 19, count 0 2006.173.22:03:35.81#ibcon#read 6, iclass 19, count 0 2006.173.22:03:35.81#ibcon#end of sib2, iclass 19, count 0 2006.173.22:03:35.81#ibcon#*after write, iclass 19, count 0 2006.173.22:03:35.81#ibcon#*before return 0, iclass 19, count 0 2006.173.22:03:35.81#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.22:03:35.81#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.22:03:35.81#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.22:03:35.81#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.22:03:35.81$vck44/valo=3,564.99 2006.173.22:03:35.81#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.22:03:35.81#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.22:03:35.81#ibcon#ireg 17 cls_cnt 0 2006.173.22:03:35.81#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.22:03:35.81#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.22:03:35.81#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.22:03:35.81#ibcon#enter wrdev, iclass 21, count 0 2006.173.22:03:35.81#ibcon#first serial, iclass 21, count 0 2006.173.22:03:35.81#ibcon#enter sib2, iclass 21, count 0 2006.173.22:03:35.81#ibcon#flushed, iclass 21, count 0 2006.173.22:03:35.81#ibcon#about to write, iclass 21, count 0 2006.173.22:03:35.81#ibcon#wrote, iclass 21, count 0 2006.173.22:03:35.81#ibcon#about to read 3, iclass 21, count 0 2006.173.22:03:35.83#ibcon#read 3, iclass 21, count 0 2006.173.22:03:35.83#ibcon#about to read 4, iclass 21, count 0 2006.173.22:03:35.83#ibcon#read 4, iclass 21, count 0 2006.173.22:03:35.83#ibcon#about to read 5, iclass 21, count 0 2006.173.22:03:35.83#ibcon#read 5, iclass 21, count 0 2006.173.22:03:35.83#ibcon#about to read 6, iclass 21, count 0 2006.173.22:03:35.83#ibcon#read 6, iclass 21, count 0 2006.173.22:03:35.83#ibcon#end of sib2, iclass 21, count 0 2006.173.22:03:35.83#ibcon#*mode == 0, iclass 21, count 0 2006.173.22:03:35.83#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.22:03:35.83#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.22:03:35.83#ibcon#*before write, iclass 21, count 0 2006.173.22:03:35.83#ibcon#enter sib2, iclass 21, count 0 2006.173.22:03:35.83#ibcon#flushed, iclass 21, count 0 2006.173.22:03:35.83#ibcon#about to write, iclass 21, count 0 2006.173.22:03:35.83#ibcon#wrote, iclass 21, count 0 2006.173.22:03:35.83#ibcon#about to read 3, iclass 21, count 0 2006.173.22:03:35.87#ibcon#read 3, iclass 21, count 0 2006.173.22:03:35.87#ibcon#about to read 4, iclass 21, count 0 2006.173.22:03:35.87#ibcon#read 4, iclass 21, count 0 2006.173.22:03:35.87#ibcon#about to read 5, iclass 21, count 0 2006.173.22:03:35.87#ibcon#read 5, iclass 21, count 0 2006.173.22:03:35.87#ibcon#about to read 6, iclass 21, count 0 2006.173.22:03:35.87#ibcon#read 6, iclass 21, count 0 2006.173.22:03:35.87#ibcon#end of sib2, iclass 21, count 0 2006.173.22:03:35.87#ibcon#*after write, iclass 21, count 0 2006.173.22:03:35.87#ibcon#*before return 0, iclass 21, count 0 2006.173.22:03:35.87#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.22:03:35.87#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.22:03:35.87#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.22:03:35.87#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.22:03:35.87$vck44/va=3,5 2006.173.22:03:35.87#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.22:03:35.87#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.22:03:35.87#ibcon#ireg 11 cls_cnt 2 2006.173.22:03:35.87#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.22:03:35.93#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.22:03:35.93#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.22:03:35.93#ibcon#enter wrdev, iclass 23, count 2 2006.173.22:03:35.93#ibcon#first serial, iclass 23, count 2 2006.173.22:03:35.93#ibcon#enter sib2, iclass 23, count 2 2006.173.22:03:35.93#ibcon#flushed, iclass 23, count 2 2006.173.22:03:35.93#ibcon#about to write, iclass 23, count 2 2006.173.22:03:35.93#ibcon#wrote, iclass 23, count 2 2006.173.22:03:35.93#ibcon#about to read 3, iclass 23, count 2 2006.173.22:03:35.95#ibcon#read 3, iclass 23, count 2 2006.173.22:03:35.95#ibcon#about to read 4, iclass 23, count 2 2006.173.22:03:35.95#ibcon#read 4, iclass 23, count 2 2006.173.22:03:35.95#ibcon#about to read 5, iclass 23, count 2 2006.173.22:03:35.95#ibcon#read 5, iclass 23, count 2 2006.173.22:03:35.95#ibcon#about to read 6, iclass 23, count 2 2006.173.22:03:35.95#ibcon#read 6, iclass 23, count 2 2006.173.22:03:35.95#ibcon#end of sib2, iclass 23, count 2 2006.173.22:03:35.95#ibcon#*mode == 0, iclass 23, count 2 2006.173.22:03:35.95#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.22:03:35.95#ibcon#[25=AT03-05\r\n] 2006.173.22:03:35.95#ibcon#*before write, iclass 23, count 2 2006.173.22:03:35.95#ibcon#enter sib2, iclass 23, count 2 2006.173.22:03:35.95#ibcon#flushed, iclass 23, count 2 2006.173.22:03:35.95#ibcon#about to write, iclass 23, count 2 2006.173.22:03:35.95#ibcon#wrote, iclass 23, count 2 2006.173.22:03:35.95#ibcon#about to read 3, iclass 23, count 2 2006.173.22:03:35.98#ibcon#read 3, iclass 23, count 2 2006.173.22:03:35.98#ibcon#about to read 4, iclass 23, count 2 2006.173.22:03:35.98#ibcon#read 4, iclass 23, count 2 2006.173.22:03:35.98#ibcon#about to read 5, iclass 23, count 2 2006.173.22:03:35.98#ibcon#read 5, iclass 23, count 2 2006.173.22:03:35.98#ibcon#about to read 6, iclass 23, count 2 2006.173.22:03:35.98#ibcon#read 6, iclass 23, count 2 2006.173.22:03:35.98#ibcon#end of sib2, iclass 23, count 2 2006.173.22:03:35.98#ibcon#*after write, iclass 23, count 2 2006.173.22:03:35.98#ibcon#*before return 0, iclass 23, count 2 2006.173.22:03:35.98#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.22:03:35.98#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.22:03:35.98#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.22:03:35.98#ibcon#ireg 7 cls_cnt 0 2006.173.22:03:35.98#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.22:03:36.10#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.22:03:36.10#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.22:03:36.10#ibcon#enter wrdev, iclass 23, count 0 2006.173.22:03:36.10#ibcon#first serial, iclass 23, count 0 2006.173.22:03:36.10#ibcon#enter sib2, iclass 23, count 0 2006.173.22:03:36.10#ibcon#flushed, iclass 23, count 0 2006.173.22:03:36.10#ibcon#about to write, iclass 23, count 0 2006.173.22:03:36.10#ibcon#wrote, iclass 23, count 0 2006.173.22:03:36.10#ibcon#about to read 3, iclass 23, count 0 2006.173.22:03:36.12#ibcon#read 3, iclass 23, count 0 2006.173.22:03:36.12#ibcon#about to read 4, iclass 23, count 0 2006.173.22:03:36.12#ibcon#read 4, iclass 23, count 0 2006.173.22:03:36.12#ibcon#about to read 5, iclass 23, count 0 2006.173.22:03:36.12#ibcon#read 5, iclass 23, count 0 2006.173.22:03:36.12#ibcon#about to read 6, iclass 23, count 0 2006.173.22:03:36.12#ibcon#read 6, iclass 23, count 0 2006.173.22:03:36.12#ibcon#end of sib2, iclass 23, count 0 2006.173.22:03:36.12#ibcon#*mode == 0, iclass 23, count 0 2006.173.22:03:36.12#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.22:03:36.12#ibcon#[25=USB\r\n] 2006.173.22:03:36.12#ibcon#*before write, iclass 23, count 0 2006.173.22:03:36.12#ibcon#enter sib2, iclass 23, count 0 2006.173.22:03:36.12#ibcon#flushed, iclass 23, count 0 2006.173.22:03:36.12#ibcon#about to write, iclass 23, count 0 2006.173.22:03:36.12#ibcon#wrote, iclass 23, count 0 2006.173.22:03:36.12#ibcon#about to read 3, iclass 23, count 0 2006.173.22:03:36.15#ibcon#read 3, iclass 23, count 0 2006.173.22:03:36.15#ibcon#about to read 4, iclass 23, count 0 2006.173.22:03:36.15#ibcon#read 4, iclass 23, count 0 2006.173.22:03:36.15#ibcon#about to read 5, iclass 23, count 0 2006.173.22:03:36.15#ibcon#read 5, iclass 23, count 0 2006.173.22:03:36.15#ibcon#about to read 6, iclass 23, count 0 2006.173.22:03:36.15#ibcon#read 6, iclass 23, count 0 2006.173.22:03:36.15#ibcon#end of sib2, iclass 23, count 0 2006.173.22:03:36.15#ibcon#*after write, iclass 23, count 0 2006.173.22:03:36.15#ibcon#*before return 0, iclass 23, count 0 2006.173.22:03:36.15#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.22:03:36.15#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.22:03:36.15#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.22:03:36.15#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.22:03:36.15$vck44/valo=4,624.99 2006.173.22:03:36.15#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.22:03:36.15#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.22:03:36.15#ibcon#ireg 17 cls_cnt 0 2006.173.22:03:36.15#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.22:03:36.15#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.22:03:36.15#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.22:03:36.15#ibcon#enter wrdev, iclass 25, count 0 2006.173.22:03:36.15#ibcon#first serial, iclass 25, count 0 2006.173.22:03:36.15#ibcon#enter sib2, iclass 25, count 0 2006.173.22:03:36.15#ibcon#flushed, iclass 25, count 0 2006.173.22:03:36.15#ibcon#about to write, iclass 25, count 0 2006.173.22:03:36.15#ibcon#wrote, iclass 25, count 0 2006.173.22:03:36.15#ibcon#about to read 3, iclass 25, count 0 2006.173.22:03:36.17#ibcon#read 3, iclass 25, count 0 2006.173.22:03:36.17#ibcon#about to read 4, iclass 25, count 0 2006.173.22:03:36.17#ibcon#read 4, iclass 25, count 0 2006.173.22:03:36.17#ibcon#about to read 5, iclass 25, count 0 2006.173.22:03:36.17#ibcon#read 5, iclass 25, count 0 2006.173.22:03:36.17#ibcon#about to read 6, iclass 25, count 0 2006.173.22:03:36.17#ibcon#read 6, iclass 25, count 0 2006.173.22:03:36.17#ibcon#end of sib2, iclass 25, count 0 2006.173.22:03:36.17#ibcon#*mode == 0, iclass 25, count 0 2006.173.22:03:36.17#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.22:03:36.17#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.22:03:36.17#ibcon#*before write, iclass 25, count 0 2006.173.22:03:36.17#ibcon#enter sib2, iclass 25, count 0 2006.173.22:03:36.17#ibcon#flushed, iclass 25, count 0 2006.173.22:03:36.17#ibcon#about to write, iclass 25, count 0 2006.173.22:03:36.17#ibcon#wrote, iclass 25, count 0 2006.173.22:03:36.17#ibcon#about to read 3, iclass 25, count 0 2006.173.22:03:36.21#ibcon#read 3, iclass 25, count 0 2006.173.22:03:36.21#ibcon#about to read 4, iclass 25, count 0 2006.173.22:03:36.21#ibcon#read 4, iclass 25, count 0 2006.173.22:03:36.21#ibcon#about to read 5, iclass 25, count 0 2006.173.22:03:36.21#ibcon#read 5, iclass 25, count 0 2006.173.22:03:36.21#ibcon#about to read 6, iclass 25, count 0 2006.173.22:03:36.21#ibcon#read 6, iclass 25, count 0 2006.173.22:03:36.21#ibcon#end of sib2, iclass 25, count 0 2006.173.22:03:36.21#ibcon#*after write, iclass 25, count 0 2006.173.22:03:36.21#ibcon#*before return 0, iclass 25, count 0 2006.173.22:03:36.21#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.22:03:36.21#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.22:03:36.21#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.22:03:36.21#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.22:03:36.21$vck44/va=4,6 2006.173.22:03:36.21#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.22:03:36.21#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.22:03:36.21#ibcon#ireg 11 cls_cnt 2 2006.173.22:03:36.21#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.22:03:36.27#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.22:03:36.27#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.22:03:36.27#ibcon#enter wrdev, iclass 27, count 2 2006.173.22:03:36.27#ibcon#first serial, iclass 27, count 2 2006.173.22:03:36.27#ibcon#enter sib2, iclass 27, count 2 2006.173.22:03:36.27#ibcon#flushed, iclass 27, count 2 2006.173.22:03:36.27#ibcon#about to write, iclass 27, count 2 2006.173.22:03:36.27#ibcon#wrote, iclass 27, count 2 2006.173.22:03:36.27#ibcon#about to read 3, iclass 27, count 2 2006.173.22:03:36.29#ibcon#read 3, iclass 27, count 2 2006.173.22:03:36.29#ibcon#about to read 4, iclass 27, count 2 2006.173.22:03:36.29#ibcon#read 4, iclass 27, count 2 2006.173.22:03:36.29#ibcon#about to read 5, iclass 27, count 2 2006.173.22:03:36.29#ibcon#read 5, iclass 27, count 2 2006.173.22:03:36.29#ibcon#about to read 6, iclass 27, count 2 2006.173.22:03:36.29#ibcon#read 6, iclass 27, count 2 2006.173.22:03:36.29#ibcon#end of sib2, iclass 27, count 2 2006.173.22:03:36.29#ibcon#*mode == 0, iclass 27, count 2 2006.173.22:03:36.29#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.22:03:36.29#ibcon#[25=AT04-06\r\n] 2006.173.22:03:36.29#ibcon#*before write, iclass 27, count 2 2006.173.22:03:36.29#ibcon#enter sib2, iclass 27, count 2 2006.173.22:03:36.29#ibcon#flushed, iclass 27, count 2 2006.173.22:03:36.29#ibcon#about to write, iclass 27, count 2 2006.173.22:03:36.29#ibcon#wrote, iclass 27, count 2 2006.173.22:03:36.29#ibcon#about to read 3, iclass 27, count 2 2006.173.22:03:36.32#ibcon#read 3, iclass 27, count 2 2006.173.22:03:36.32#ibcon#about to read 4, iclass 27, count 2 2006.173.22:03:36.32#ibcon#read 4, iclass 27, count 2 2006.173.22:03:36.32#ibcon#about to read 5, iclass 27, count 2 2006.173.22:03:36.32#ibcon#read 5, iclass 27, count 2 2006.173.22:03:36.32#ibcon#about to read 6, iclass 27, count 2 2006.173.22:03:36.32#ibcon#read 6, iclass 27, count 2 2006.173.22:03:36.32#ibcon#end of sib2, iclass 27, count 2 2006.173.22:03:36.32#ibcon#*after write, iclass 27, count 2 2006.173.22:03:36.32#ibcon#*before return 0, iclass 27, count 2 2006.173.22:03:36.32#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.22:03:36.32#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.22:03:36.32#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.22:03:36.32#ibcon#ireg 7 cls_cnt 0 2006.173.22:03:36.32#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.22:03:36.44#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.22:03:36.44#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.22:03:36.44#ibcon#enter wrdev, iclass 27, count 0 2006.173.22:03:36.44#ibcon#first serial, iclass 27, count 0 2006.173.22:03:36.44#ibcon#enter sib2, iclass 27, count 0 2006.173.22:03:36.44#ibcon#flushed, iclass 27, count 0 2006.173.22:03:36.44#ibcon#about to write, iclass 27, count 0 2006.173.22:03:36.44#ibcon#wrote, iclass 27, count 0 2006.173.22:03:36.44#ibcon#about to read 3, iclass 27, count 0 2006.173.22:03:36.46#ibcon#read 3, iclass 27, count 0 2006.173.22:03:36.46#ibcon#about to read 4, iclass 27, count 0 2006.173.22:03:36.46#ibcon#read 4, iclass 27, count 0 2006.173.22:03:36.46#ibcon#about to read 5, iclass 27, count 0 2006.173.22:03:36.46#ibcon#read 5, iclass 27, count 0 2006.173.22:03:36.46#ibcon#about to read 6, iclass 27, count 0 2006.173.22:03:36.46#ibcon#read 6, iclass 27, count 0 2006.173.22:03:36.46#ibcon#end of sib2, iclass 27, count 0 2006.173.22:03:36.46#ibcon#*mode == 0, iclass 27, count 0 2006.173.22:03:36.46#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.22:03:36.46#ibcon#[25=USB\r\n] 2006.173.22:03:36.46#ibcon#*before write, iclass 27, count 0 2006.173.22:03:36.46#ibcon#enter sib2, iclass 27, count 0 2006.173.22:03:36.46#ibcon#flushed, iclass 27, count 0 2006.173.22:03:36.46#ibcon#about to write, iclass 27, count 0 2006.173.22:03:36.46#ibcon#wrote, iclass 27, count 0 2006.173.22:03:36.46#ibcon#about to read 3, iclass 27, count 0 2006.173.22:03:36.49#ibcon#read 3, iclass 27, count 0 2006.173.22:03:36.49#ibcon#about to read 4, iclass 27, count 0 2006.173.22:03:36.49#ibcon#read 4, iclass 27, count 0 2006.173.22:03:36.49#ibcon#about to read 5, iclass 27, count 0 2006.173.22:03:36.49#ibcon#read 5, iclass 27, count 0 2006.173.22:03:36.49#ibcon#about to read 6, iclass 27, count 0 2006.173.22:03:36.49#ibcon#read 6, iclass 27, count 0 2006.173.22:03:36.49#ibcon#end of sib2, iclass 27, count 0 2006.173.22:03:36.49#ibcon#*after write, iclass 27, count 0 2006.173.22:03:36.49#ibcon#*before return 0, iclass 27, count 0 2006.173.22:03:36.49#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.22:03:36.49#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.22:03:36.49#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.22:03:36.49#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.22:03:36.49$vck44/valo=5,734.99 2006.173.22:03:36.49#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.22:03:36.49#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.22:03:36.49#ibcon#ireg 17 cls_cnt 0 2006.173.22:03:36.49#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.22:03:36.49#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.22:03:36.49#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.22:03:36.49#ibcon#enter wrdev, iclass 29, count 0 2006.173.22:03:36.49#ibcon#first serial, iclass 29, count 0 2006.173.22:03:36.49#ibcon#enter sib2, iclass 29, count 0 2006.173.22:03:36.49#ibcon#flushed, iclass 29, count 0 2006.173.22:03:36.49#ibcon#about to write, iclass 29, count 0 2006.173.22:03:36.49#ibcon#wrote, iclass 29, count 0 2006.173.22:03:36.49#ibcon#about to read 3, iclass 29, count 0 2006.173.22:03:36.51#ibcon#read 3, iclass 29, count 0 2006.173.22:03:36.51#ibcon#about to read 4, iclass 29, count 0 2006.173.22:03:36.51#ibcon#read 4, iclass 29, count 0 2006.173.22:03:36.51#ibcon#about to read 5, iclass 29, count 0 2006.173.22:03:36.51#ibcon#read 5, iclass 29, count 0 2006.173.22:03:36.51#ibcon#about to read 6, iclass 29, count 0 2006.173.22:03:36.51#ibcon#read 6, iclass 29, count 0 2006.173.22:03:36.51#ibcon#end of sib2, iclass 29, count 0 2006.173.22:03:36.51#ibcon#*mode == 0, iclass 29, count 0 2006.173.22:03:36.51#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.22:03:36.51#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.22:03:36.51#ibcon#*before write, iclass 29, count 0 2006.173.22:03:36.51#ibcon#enter sib2, iclass 29, count 0 2006.173.22:03:36.51#ibcon#flushed, iclass 29, count 0 2006.173.22:03:36.51#ibcon#about to write, iclass 29, count 0 2006.173.22:03:36.51#ibcon#wrote, iclass 29, count 0 2006.173.22:03:36.51#ibcon#about to read 3, iclass 29, count 0 2006.173.22:03:36.55#ibcon#read 3, iclass 29, count 0 2006.173.22:03:36.55#ibcon#about to read 4, iclass 29, count 0 2006.173.22:03:36.55#ibcon#read 4, iclass 29, count 0 2006.173.22:03:36.55#ibcon#about to read 5, iclass 29, count 0 2006.173.22:03:36.55#ibcon#read 5, iclass 29, count 0 2006.173.22:03:36.55#ibcon#about to read 6, iclass 29, count 0 2006.173.22:03:36.55#ibcon#read 6, iclass 29, count 0 2006.173.22:03:36.55#ibcon#end of sib2, iclass 29, count 0 2006.173.22:03:36.55#ibcon#*after write, iclass 29, count 0 2006.173.22:03:36.55#ibcon#*before return 0, iclass 29, count 0 2006.173.22:03:36.55#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.22:03:36.55#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.22:03:36.55#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.22:03:36.55#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.22:03:36.55$vck44/va=5,4 2006.173.22:03:36.55#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.22:03:36.55#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.22:03:36.55#ibcon#ireg 11 cls_cnt 2 2006.173.22:03:36.55#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.22:03:36.61#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.22:03:36.61#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.22:03:36.61#ibcon#enter wrdev, iclass 31, count 2 2006.173.22:03:36.61#ibcon#first serial, iclass 31, count 2 2006.173.22:03:36.61#ibcon#enter sib2, iclass 31, count 2 2006.173.22:03:36.61#ibcon#flushed, iclass 31, count 2 2006.173.22:03:36.61#ibcon#about to write, iclass 31, count 2 2006.173.22:03:36.61#ibcon#wrote, iclass 31, count 2 2006.173.22:03:36.61#ibcon#about to read 3, iclass 31, count 2 2006.173.22:03:36.63#ibcon#read 3, iclass 31, count 2 2006.173.22:03:36.63#ibcon#about to read 4, iclass 31, count 2 2006.173.22:03:36.63#ibcon#read 4, iclass 31, count 2 2006.173.22:03:36.63#ibcon#about to read 5, iclass 31, count 2 2006.173.22:03:36.63#ibcon#read 5, iclass 31, count 2 2006.173.22:03:36.63#ibcon#about to read 6, iclass 31, count 2 2006.173.22:03:36.63#ibcon#read 6, iclass 31, count 2 2006.173.22:03:36.63#ibcon#end of sib2, iclass 31, count 2 2006.173.22:03:36.63#ibcon#*mode == 0, iclass 31, count 2 2006.173.22:03:36.63#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.22:03:36.63#ibcon#[25=AT05-04\r\n] 2006.173.22:03:36.63#ibcon#*before write, iclass 31, count 2 2006.173.22:03:36.63#ibcon#enter sib2, iclass 31, count 2 2006.173.22:03:36.63#ibcon#flushed, iclass 31, count 2 2006.173.22:03:36.63#ibcon#about to write, iclass 31, count 2 2006.173.22:03:36.63#ibcon#wrote, iclass 31, count 2 2006.173.22:03:36.63#ibcon#about to read 3, iclass 31, count 2 2006.173.22:03:36.66#ibcon#read 3, iclass 31, count 2 2006.173.22:03:36.66#ibcon#about to read 4, iclass 31, count 2 2006.173.22:03:36.66#ibcon#read 4, iclass 31, count 2 2006.173.22:03:36.66#ibcon#about to read 5, iclass 31, count 2 2006.173.22:03:36.66#ibcon#read 5, iclass 31, count 2 2006.173.22:03:36.66#ibcon#about to read 6, iclass 31, count 2 2006.173.22:03:36.66#ibcon#read 6, iclass 31, count 2 2006.173.22:03:36.66#ibcon#end of sib2, iclass 31, count 2 2006.173.22:03:36.66#ibcon#*after write, iclass 31, count 2 2006.173.22:03:36.66#ibcon#*before return 0, iclass 31, count 2 2006.173.22:03:36.66#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.22:03:36.66#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.22:03:36.66#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.22:03:36.66#ibcon#ireg 7 cls_cnt 0 2006.173.22:03:36.66#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.22:03:36.78#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.22:03:36.78#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.22:03:36.78#ibcon#enter wrdev, iclass 31, count 0 2006.173.22:03:36.78#ibcon#first serial, iclass 31, count 0 2006.173.22:03:36.78#ibcon#enter sib2, iclass 31, count 0 2006.173.22:03:36.78#ibcon#flushed, iclass 31, count 0 2006.173.22:03:36.78#ibcon#about to write, iclass 31, count 0 2006.173.22:03:36.78#ibcon#wrote, iclass 31, count 0 2006.173.22:03:36.78#ibcon#about to read 3, iclass 31, count 0 2006.173.22:03:36.80#ibcon#read 3, iclass 31, count 0 2006.173.22:03:36.80#ibcon#about to read 4, iclass 31, count 0 2006.173.22:03:36.80#ibcon#read 4, iclass 31, count 0 2006.173.22:03:36.80#ibcon#about to read 5, iclass 31, count 0 2006.173.22:03:36.80#ibcon#read 5, iclass 31, count 0 2006.173.22:03:36.80#ibcon#about to read 6, iclass 31, count 0 2006.173.22:03:36.80#ibcon#read 6, iclass 31, count 0 2006.173.22:03:36.80#ibcon#end of sib2, iclass 31, count 0 2006.173.22:03:36.80#ibcon#*mode == 0, iclass 31, count 0 2006.173.22:03:36.80#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.22:03:36.80#ibcon#[25=USB\r\n] 2006.173.22:03:36.80#ibcon#*before write, iclass 31, count 0 2006.173.22:03:36.80#ibcon#enter sib2, iclass 31, count 0 2006.173.22:03:36.80#ibcon#flushed, iclass 31, count 0 2006.173.22:03:36.80#ibcon#about to write, iclass 31, count 0 2006.173.22:03:36.80#ibcon#wrote, iclass 31, count 0 2006.173.22:03:36.80#ibcon#about to read 3, iclass 31, count 0 2006.173.22:03:36.83#ibcon#read 3, iclass 31, count 0 2006.173.22:03:36.83#ibcon#about to read 4, iclass 31, count 0 2006.173.22:03:36.83#ibcon#read 4, iclass 31, count 0 2006.173.22:03:36.83#ibcon#about to read 5, iclass 31, count 0 2006.173.22:03:36.83#ibcon#read 5, iclass 31, count 0 2006.173.22:03:36.83#ibcon#about to read 6, iclass 31, count 0 2006.173.22:03:36.83#ibcon#read 6, iclass 31, count 0 2006.173.22:03:36.83#ibcon#end of sib2, iclass 31, count 0 2006.173.22:03:36.83#ibcon#*after write, iclass 31, count 0 2006.173.22:03:36.83#ibcon#*before return 0, iclass 31, count 0 2006.173.22:03:36.83#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.22:03:36.83#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.22:03:36.83#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.22:03:36.83#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.22:03:36.83$vck44/valo=6,814.99 2006.173.22:03:36.83#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.22:03:36.83#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.22:03:36.83#ibcon#ireg 17 cls_cnt 0 2006.173.22:03:36.83#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.22:03:36.83#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.22:03:36.83#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.22:03:36.83#ibcon#enter wrdev, iclass 33, count 0 2006.173.22:03:36.83#ibcon#first serial, iclass 33, count 0 2006.173.22:03:36.83#ibcon#enter sib2, iclass 33, count 0 2006.173.22:03:36.83#ibcon#flushed, iclass 33, count 0 2006.173.22:03:36.83#ibcon#about to write, iclass 33, count 0 2006.173.22:03:36.83#ibcon#wrote, iclass 33, count 0 2006.173.22:03:36.83#ibcon#about to read 3, iclass 33, count 0 2006.173.22:03:36.85#ibcon#read 3, iclass 33, count 0 2006.173.22:03:36.85#ibcon#about to read 4, iclass 33, count 0 2006.173.22:03:36.85#ibcon#read 4, iclass 33, count 0 2006.173.22:03:36.85#ibcon#about to read 5, iclass 33, count 0 2006.173.22:03:36.85#ibcon#read 5, iclass 33, count 0 2006.173.22:03:36.85#ibcon#about to read 6, iclass 33, count 0 2006.173.22:03:36.85#ibcon#read 6, iclass 33, count 0 2006.173.22:03:36.85#ibcon#end of sib2, iclass 33, count 0 2006.173.22:03:36.85#ibcon#*mode == 0, iclass 33, count 0 2006.173.22:03:36.85#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.22:03:36.85#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.22:03:36.85#ibcon#*before write, iclass 33, count 0 2006.173.22:03:36.85#ibcon#enter sib2, iclass 33, count 0 2006.173.22:03:36.85#ibcon#flushed, iclass 33, count 0 2006.173.22:03:36.85#ibcon#about to write, iclass 33, count 0 2006.173.22:03:36.85#ibcon#wrote, iclass 33, count 0 2006.173.22:03:36.85#ibcon#about to read 3, iclass 33, count 0 2006.173.22:03:36.89#ibcon#read 3, iclass 33, count 0 2006.173.22:03:36.89#ibcon#about to read 4, iclass 33, count 0 2006.173.22:03:36.89#ibcon#read 4, iclass 33, count 0 2006.173.22:03:36.89#ibcon#about to read 5, iclass 33, count 0 2006.173.22:03:36.89#ibcon#read 5, iclass 33, count 0 2006.173.22:03:36.89#ibcon#about to read 6, iclass 33, count 0 2006.173.22:03:36.89#ibcon#read 6, iclass 33, count 0 2006.173.22:03:36.89#ibcon#end of sib2, iclass 33, count 0 2006.173.22:03:36.89#ibcon#*after write, iclass 33, count 0 2006.173.22:03:36.89#ibcon#*before return 0, iclass 33, count 0 2006.173.22:03:36.89#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.22:03:36.89#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.22:03:36.89#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.22:03:36.89#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.22:03:36.89$vck44/va=6,3 2006.173.22:03:36.89#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.22:03:36.89#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.22:03:36.89#ibcon#ireg 11 cls_cnt 2 2006.173.22:03:36.89#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.22:03:36.95#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.22:03:36.95#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.22:03:36.95#ibcon#enter wrdev, iclass 35, count 2 2006.173.22:03:36.95#ibcon#first serial, iclass 35, count 2 2006.173.22:03:36.95#ibcon#enter sib2, iclass 35, count 2 2006.173.22:03:36.95#ibcon#flushed, iclass 35, count 2 2006.173.22:03:36.95#ibcon#about to write, iclass 35, count 2 2006.173.22:03:36.95#ibcon#wrote, iclass 35, count 2 2006.173.22:03:36.95#ibcon#about to read 3, iclass 35, count 2 2006.173.22:03:36.97#ibcon#read 3, iclass 35, count 2 2006.173.22:03:36.97#ibcon#about to read 4, iclass 35, count 2 2006.173.22:03:36.97#ibcon#read 4, iclass 35, count 2 2006.173.22:03:36.97#ibcon#about to read 5, iclass 35, count 2 2006.173.22:03:36.97#ibcon#read 5, iclass 35, count 2 2006.173.22:03:36.97#ibcon#about to read 6, iclass 35, count 2 2006.173.22:03:36.97#ibcon#read 6, iclass 35, count 2 2006.173.22:03:36.97#ibcon#end of sib2, iclass 35, count 2 2006.173.22:03:36.97#ibcon#*mode == 0, iclass 35, count 2 2006.173.22:03:36.97#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.22:03:36.97#ibcon#[25=AT06-03\r\n] 2006.173.22:03:36.97#ibcon#*before write, iclass 35, count 2 2006.173.22:03:36.97#ibcon#enter sib2, iclass 35, count 2 2006.173.22:03:36.97#ibcon#flushed, iclass 35, count 2 2006.173.22:03:36.97#ibcon#about to write, iclass 35, count 2 2006.173.22:03:36.97#ibcon#wrote, iclass 35, count 2 2006.173.22:03:36.97#ibcon#about to read 3, iclass 35, count 2 2006.173.22:03:37.00#ibcon#read 3, iclass 35, count 2 2006.173.22:03:37.00#ibcon#about to read 4, iclass 35, count 2 2006.173.22:03:37.00#ibcon#read 4, iclass 35, count 2 2006.173.22:03:37.00#ibcon#about to read 5, iclass 35, count 2 2006.173.22:03:37.00#ibcon#read 5, iclass 35, count 2 2006.173.22:03:37.00#ibcon#about to read 6, iclass 35, count 2 2006.173.22:03:37.00#ibcon#read 6, iclass 35, count 2 2006.173.22:03:37.00#ibcon#end of sib2, iclass 35, count 2 2006.173.22:03:37.00#ibcon#*after write, iclass 35, count 2 2006.173.22:03:37.00#ibcon#*before return 0, iclass 35, count 2 2006.173.22:03:37.00#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.22:03:37.00#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.22:03:37.00#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.22:03:37.00#ibcon#ireg 7 cls_cnt 0 2006.173.22:03:37.00#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.22:03:37.12#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.22:03:37.12#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.22:03:37.12#ibcon#enter wrdev, iclass 35, count 0 2006.173.22:03:37.12#ibcon#first serial, iclass 35, count 0 2006.173.22:03:37.12#ibcon#enter sib2, iclass 35, count 0 2006.173.22:03:37.12#ibcon#flushed, iclass 35, count 0 2006.173.22:03:37.12#ibcon#about to write, iclass 35, count 0 2006.173.22:03:37.12#ibcon#wrote, iclass 35, count 0 2006.173.22:03:37.12#ibcon#about to read 3, iclass 35, count 0 2006.173.22:03:37.14#ibcon#read 3, iclass 35, count 0 2006.173.22:03:37.14#ibcon#about to read 4, iclass 35, count 0 2006.173.22:03:37.14#ibcon#read 4, iclass 35, count 0 2006.173.22:03:37.14#ibcon#about to read 5, iclass 35, count 0 2006.173.22:03:37.14#ibcon#read 5, iclass 35, count 0 2006.173.22:03:37.14#ibcon#about to read 6, iclass 35, count 0 2006.173.22:03:37.14#ibcon#read 6, iclass 35, count 0 2006.173.22:03:37.14#ibcon#end of sib2, iclass 35, count 0 2006.173.22:03:37.14#ibcon#*mode == 0, iclass 35, count 0 2006.173.22:03:37.14#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.22:03:37.14#ibcon#[25=USB\r\n] 2006.173.22:03:37.14#ibcon#*before write, iclass 35, count 0 2006.173.22:03:37.14#ibcon#enter sib2, iclass 35, count 0 2006.173.22:03:37.14#ibcon#flushed, iclass 35, count 0 2006.173.22:03:37.14#ibcon#about to write, iclass 35, count 0 2006.173.22:03:37.14#ibcon#wrote, iclass 35, count 0 2006.173.22:03:37.14#ibcon#about to read 3, iclass 35, count 0 2006.173.22:03:37.17#ibcon#read 3, iclass 35, count 0 2006.173.22:03:37.17#ibcon#about to read 4, iclass 35, count 0 2006.173.22:03:37.17#ibcon#read 4, iclass 35, count 0 2006.173.22:03:37.17#ibcon#about to read 5, iclass 35, count 0 2006.173.22:03:37.17#ibcon#read 5, iclass 35, count 0 2006.173.22:03:37.17#ibcon#about to read 6, iclass 35, count 0 2006.173.22:03:37.17#ibcon#read 6, iclass 35, count 0 2006.173.22:03:37.17#ibcon#end of sib2, iclass 35, count 0 2006.173.22:03:37.17#ibcon#*after write, iclass 35, count 0 2006.173.22:03:37.17#ibcon#*before return 0, iclass 35, count 0 2006.173.22:03:37.17#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.22:03:37.17#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.22:03:37.17#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.22:03:37.17#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.22:03:37.17$vck44/valo=7,864.99 2006.173.22:03:37.17#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.22:03:37.17#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.22:03:37.17#ibcon#ireg 17 cls_cnt 0 2006.173.22:03:37.17#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.22:03:37.17#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.22:03:37.17#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.22:03:37.17#ibcon#enter wrdev, iclass 37, count 0 2006.173.22:03:37.17#ibcon#first serial, iclass 37, count 0 2006.173.22:03:37.17#ibcon#enter sib2, iclass 37, count 0 2006.173.22:03:37.17#ibcon#flushed, iclass 37, count 0 2006.173.22:03:37.17#ibcon#about to write, iclass 37, count 0 2006.173.22:03:37.17#ibcon#wrote, iclass 37, count 0 2006.173.22:03:37.17#ibcon#about to read 3, iclass 37, count 0 2006.173.22:03:37.19#ibcon#read 3, iclass 37, count 0 2006.173.22:03:37.19#ibcon#about to read 4, iclass 37, count 0 2006.173.22:03:37.19#ibcon#read 4, iclass 37, count 0 2006.173.22:03:37.19#ibcon#about to read 5, iclass 37, count 0 2006.173.22:03:37.19#ibcon#read 5, iclass 37, count 0 2006.173.22:03:37.19#ibcon#about to read 6, iclass 37, count 0 2006.173.22:03:37.19#ibcon#read 6, iclass 37, count 0 2006.173.22:03:37.19#ibcon#end of sib2, iclass 37, count 0 2006.173.22:03:37.19#ibcon#*mode == 0, iclass 37, count 0 2006.173.22:03:37.19#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.22:03:37.19#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.22:03:37.19#ibcon#*before write, iclass 37, count 0 2006.173.22:03:37.19#ibcon#enter sib2, iclass 37, count 0 2006.173.22:03:37.19#ibcon#flushed, iclass 37, count 0 2006.173.22:03:37.19#ibcon#about to write, iclass 37, count 0 2006.173.22:03:37.19#ibcon#wrote, iclass 37, count 0 2006.173.22:03:37.19#ibcon#about to read 3, iclass 37, count 0 2006.173.22:03:37.23#ibcon#read 3, iclass 37, count 0 2006.173.22:03:37.23#ibcon#about to read 4, iclass 37, count 0 2006.173.22:03:37.23#ibcon#read 4, iclass 37, count 0 2006.173.22:03:37.23#ibcon#about to read 5, iclass 37, count 0 2006.173.22:03:37.23#ibcon#read 5, iclass 37, count 0 2006.173.22:03:37.23#ibcon#about to read 6, iclass 37, count 0 2006.173.22:03:37.23#ibcon#read 6, iclass 37, count 0 2006.173.22:03:37.23#ibcon#end of sib2, iclass 37, count 0 2006.173.22:03:37.23#ibcon#*after write, iclass 37, count 0 2006.173.22:03:37.23#ibcon#*before return 0, iclass 37, count 0 2006.173.22:03:37.23#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.22:03:37.23#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.22:03:37.23#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.22:03:37.23#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.22:03:37.23$vck44/va=7,4 2006.173.22:03:37.23#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.22:03:37.23#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.22:03:37.23#ibcon#ireg 11 cls_cnt 2 2006.173.22:03:37.23#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.22:03:37.29#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.22:03:37.29#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.22:03:37.29#ibcon#enter wrdev, iclass 39, count 2 2006.173.22:03:37.29#ibcon#first serial, iclass 39, count 2 2006.173.22:03:37.29#ibcon#enter sib2, iclass 39, count 2 2006.173.22:03:37.29#ibcon#flushed, iclass 39, count 2 2006.173.22:03:37.29#ibcon#about to write, iclass 39, count 2 2006.173.22:03:37.29#ibcon#wrote, iclass 39, count 2 2006.173.22:03:37.29#ibcon#about to read 3, iclass 39, count 2 2006.173.22:03:37.31#ibcon#read 3, iclass 39, count 2 2006.173.22:03:37.31#ibcon#about to read 4, iclass 39, count 2 2006.173.22:03:37.31#ibcon#read 4, iclass 39, count 2 2006.173.22:03:37.31#ibcon#about to read 5, iclass 39, count 2 2006.173.22:03:37.31#ibcon#read 5, iclass 39, count 2 2006.173.22:03:37.31#ibcon#about to read 6, iclass 39, count 2 2006.173.22:03:37.31#ibcon#read 6, iclass 39, count 2 2006.173.22:03:37.31#ibcon#end of sib2, iclass 39, count 2 2006.173.22:03:37.31#ibcon#*mode == 0, iclass 39, count 2 2006.173.22:03:37.31#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.22:03:37.31#ibcon#[25=AT07-04\r\n] 2006.173.22:03:37.31#ibcon#*before write, iclass 39, count 2 2006.173.22:03:37.31#ibcon#enter sib2, iclass 39, count 2 2006.173.22:03:37.31#ibcon#flushed, iclass 39, count 2 2006.173.22:03:37.31#ibcon#about to write, iclass 39, count 2 2006.173.22:03:37.31#ibcon#wrote, iclass 39, count 2 2006.173.22:03:37.31#ibcon#about to read 3, iclass 39, count 2 2006.173.22:03:37.34#ibcon#read 3, iclass 39, count 2 2006.173.22:03:37.34#ibcon#about to read 4, iclass 39, count 2 2006.173.22:03:37.34#ibcon#read 4, iclass 39, count 2 2006.173.22:03:37.34#ibcon#about to read 5, iclass 39, count 2 2006.173.22:03:37.34#ibcon#read 5, iclass 39, count 2 2006.173.22:03:37.34#ibcon#about to read 6, iclass 39, count 2 2006.173.22:03:37.34#ibcon#read 6, iclass 39, count 2 2006.173.22:03:37.34#ibcon#end of sib2, iclass 39, count 2 2006.173.22:03:37.34#ibcon#*after write, iclass 39, count 2 2006.173.22:03:37.34#ibcon#*before return 0, iclass 39, count 2 2006.173.22:03:37.34#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.22:03:37.34#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.22:03:37.34#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.22:03:37.34#ibcon#ireg 7 cls_cnt 0 2006.173.22:03:37.34#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.22:03:37.46#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.22:03:37.46#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.22:03:37.46#ibcon#enter wrdev, iclass 39, count 0 2006.173.22:03:37.46#ibcon#first serial, iclass 39, count 0 2006.173.22:03:37.46#ibcon#enter sib2, iclass 39, count 0 2006.173.22:03:37.46#ibcon#flushed, iclass 39, count 0 2006.173.22:03:37.46#ibcon#about to write, iclass 39, count 0 2006.173.22:03:37.46#ibcon#wrote, iclass 39, count 0 2006.173.22:03:37.46#ibcon#about to read 3, iclass 39, count 0 2006.173.22:03:37.48#ibcon#read 3, iclass 39, count 0 2006.173.22:03:37.48#ibcon#about to read 4, iclass 39, count 0 2006.173.22:03:37.48#ibcon#read 4, iclass 39, count 0 2006.173.22:03:37.48#ibcon#about to read 5, iclass 39, count 0 2006.173.22:03:37.48#ibcon#read 5, iclass 39, count 0 2006.173.22:03:37.48#ibcon#about to read 6, iclass 39, count 0 2006.173.22:03:37.48#ibcon#read 6, iclass 39, count 0 2006.173.22:03:37.48#ibcon#end of sib2, iclass 39, count 0 2006.173.22:03:37.48#ibcon#*mode == 0, iclass 39, count 0 2006.173.22:03:37.48#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.22:03:37.48#ibcon#[25=USB\r\n] 2006.173.22:03:37.48#ibcon#*before write, iclass 39, count 0 2006.173.22:03:37.48#ibcon#enter sib2, iclass 39, count 0 2006.173.22:03:37.48#ibcon#flushed, iclass 39, count 0 2006.173.22:03:37.48#ibcon#about to write, iclass 39, count 0 2006.173.22:03:37.48#ibcon#wrote, iclass 39, count 0 2006.173.22:03:37.48#ibcon#about to read 3, iclass 39, count 0 2006.173.22:03:37.51#ibcon#read 3, iclass 39, count 0 2006.173.22:03:37.51#ibcon#about to read 4, iclass 39, count 0 2006.173.22:03:37.51#ibcon#read 4, iclass 39, count 0 2006.173.22:03:37.51#ibcon#about to read 5, iclass 39, count 0 2006.173.22:03:37.51#ibcon#read 5, iclass 39, count 0 2006.173.22:03:37.51#ibcon#about to read 6, iclass 39, count 0 2006.173.22:03:37.51#ibcon#read 6, iclass 39, count 0 2006.173.22:03:37.51#ibcon#end of sib2, iclass 39, count 0 2006.173.22:03:37.51#ibcon#*after write, iclass 39, count 0 2006.173.22:03:37.51#ibcon#*before return 0, iclass 39, count 0 2006.173.22:03:37.51#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.22:03:37.51#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.22:03:37.51#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.22:03:37.51#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.22:03:37.51$vck44/valo=8,884.99 2006.173.22:03:37.51#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.22:03:37.51#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.22:03:37.51#ibcon#ireg 17 cls_cnt 0 2006.173.22:03:37.51#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.22:03:37.51#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.22:03:37.51#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.22:03:37.51#ibcon#enter wrdev, iclass 3, count 0 2006.173.22:03:37.51#ibcon#first serial, iclass 3, count 0 2006.173.22:03:37.51#ibcon#enter sib2, iclass 3, count 0 2006.173.22:03:37.51#ibcon#flushed, iclass 3, count 0 2006.173.22:03:37.51#ibcon#about to write, iclass 3, count 0 2006.173.22:03:37.51#ibcon#wrote, iclass 3, count 0 2006.173.22:03:37.51#ibcon#about to read 3, iclass 3, count 0 2006.173.22:03:37.53#ibcon#read 3, iclass 3, count 0 2006.173.22:03:37.53#ibcon#about to read 4, iclass 3, count 0 2006.173.22:03:37.53#ibcon#read 4, iclass 3, count 0 2006.173.22:03:37.53#ibcon#about to read 5, iclass 3, count 0 2006.173.22:03:37.53#ibcon#read 5, iclass 3, count 0 2006.173.22:03:37.53#ibcon#about to read 6, iclass 3, count 0 2006.173.22:03:37.53#ibcon#read 6, iclass 3, count 0 2006.173.22:03:37.53#ibcon#end of sib2, iclass 3, count 0 2006.173.22:03:37.53#ibcon#*mode == 0, iclass 3, count 0 2006.173.22:03:37.53#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.22:03:37.53#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.22:03:37.53#ibcon#*before write, iclass 3, count 0 2006.173.22:03:37.53#ibcon#enter sib2, iclass 3, count 0 2006.173.22:03:37.53#ibcon#flushed, iclass 3, count 0 2006.173.22:03:37.53#ibcon#about to write, iclass 3, count 0 2006.173.22:03:37.53#ibcon#wrote, iclass 3, count 0 2006.173.22:03:37.53#ibcon#about to read 3, iclass 3, count 0 2006.173.22:03:37.57#ibcon#read 3, iclass 3, count 0 2006.173.22:03:37.57#ibcon#about to read 4, iclass 3, count 0 2006.173.22:03:37.57#ibcon#read 4, iclass 3, count 0 2006.173.22:03:37.57#ibcon#about to read 5, iclass 3, count 0 2006.173.22:03:37.57#ibcon#read 5, iclass 3, count 0 2006.173.22:03:37.57#ibcon#about to read 6, iclass 3, count 0 2006.173.22:03:37.57#ibcon#read 6, iclass 3, count 0 2006.173.22:03:37.57#ibcon#end of sib2, iclass 3, count 0 2006.173.22:03:37.57#ibcon#*after write, iclass 3, count 0 2006.173.22:03:37.57#ibcon#*before return 0, iclass 3, count 0 2006.173.22:03:37.57#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.22:03:37.57#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.22:03:37.57#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.22:03:37.57#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.22:03:37.57$vck44/va=8,4 2006.173.22:03:37.57#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.22:03:37.57#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.22:03:37.57#ibcon#ireg 11 cls_cnt 2 2006.173.22:03:37.57#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.22:03:37.63#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.22:03:37.63#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.22:03:37.63#ibcon#enter wrdev, iclass 5, count 2 2006.173.22:03:37.63#ibcon#first serial, iclass 5, count 2 2006.173.22:03:37.63#ibcon#enter sib2, iclass 5, count 2 2006.173.22:03:37.63#ibcon#flushed, iclass 5, count 2 2006.173.22:03:37.63#ibcon#about to write, iclass 5, count 2 2006.173.22:03:37.63#ibcon#wrote, iclass 5, count 2 2006.173.22:03:37.63#ibcon#about to read 3, iclass 5, count 2 2006.173.22:03:37.65#ibcon#read 3, iclass 5, count 2 2006.173.22:03:37.65#ibcon#about to read 4, iclass 5, count 2 2006.173.22:03:37.65#ibcon#read 4, iclass 5, count 2 2006.173.22:03:37.65#ibcon#about to read 5, iclass 5, count 2 2006.173.22:03:37.65#ibcon#read 5, iclass 5, count 2 2006.173.22:03:37.65#ibcon#about to read 6, iclass 5, count 2 2006.173.22:03:37.65#ibcon#read 6, iclass 5, count 2 2006.173.22:03:37.65#ibcon#end of sib2, iclass 5, count 2 2006.173.22:03:37.65#ibcon#*mode == 0, iclass 5, count 2 2006.173.22:03:37.65#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.22:03:37.65#ibcon#[25=AT08-04\r\n] 2006.173.22:03:37.65#ibcon#*before write, iclass 5, count 2 2006.173.22:03:37.65#ibcon#enter sib2, iclass 5, count 2 2006.173.22:03:37.65#ibcon#flushed, iclass 5, count 2 2006.173.22:03:37.65#ibcon#about to write, iclass 5, count 2 2006.173.22:03:37.65#ibcon#wrote, iclass 5, count 2 2006.173.22:03:37.65#ibcon#about to read 3, iclass 5, count 2 2006.173.22:03:37.68#ibcon#read 3, iclass 5, count 2 2006.173.22:03:37.68#ibcon#about to read 4, iclass 5, count 2 2006.173.22:03:37.68#ibcon#read 4, iclass 5, count 2 2006.173.22:03:37.68#ibcon#about to read 5, iclass 5, count 2 2006.173.22:03:37.68#ibcon#read 5, iclass 5, count 2 2006.173.22:03:37.68#ibcon#about to read 6, iclass 5, count 2 2006.173.22:03:37.68#ibcon#read 6, iclass 5, count 2 2006.173.22:03:37.68#ibcon#end of sib2, iclass 5, count 2 2006.173.22:03:37.68#ibcon#*after write, iclass 5, count 2 2006.173.22:03:37.68#ibcon#*before return 0, iclass 5, count 2 2006.173.22:03:37.68#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.22:03:37.68#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.22:03:37.68#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.22:03:37.68#ibcon#ireg 7 cls_cnt 0 2006.173.22:03:37.68#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.22:03:37.80#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.22:03:37.80#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.22:03:37.80#ibcon#enter wrdev, iclass 5, count 0 2006.173.22:03:37.80#ibcon#first serial, iclass 5, count 0 2006.173.22:03:37.80#ibcon#enter sib2, iclass 5, count 0 2006.173.22:03:37.80#ibcon#flushed, iclass 5, count 0 2006.173.22:03:37.80#ibcon#about to write, iclass 5, count 0 2006.173.22:03:37.80#ibcon#wrote, iclass 5, count 0 2006.173.22:03:37.80#ibcon#about to read 3, iclass 5, count 0 2006.173.22:03:37.82#ibcon#read 3, iclass 5, count 0 2006.173.22:03:37.82#ibcon#about to read 4, iclass 5, count 0 2006.173.22:03:37.82#ibcon#read 4, iclass 5, count 0 2006.173.22:03:37.82#ibcon#about to read 5, iclass 5, count 0 2006.173.22:03:37.82#ibcon#read 5, iclass 5, count 0 2006.173.22:03:37.82#ibcon#about to read 6, iclass 5, count 0 2006.173.22:03:37.82#ibcon#read 6, iclass 5, count 0 2006.173.22:03:37.82#ibcon#end of sib2, iclass 5, count 0 2006.173.22:03:37.82#ibcon#*mode == 0, iclass 5, count 0 2006.173.22:03:37.82#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.22:03:37.82#ibcon#[25=USB\r\n] 2006.173.22:03:37.82#ibcon#*before write, iclass 5, count 0 2006.173.22:03:37.82#ibcon#enter sib2, iclass 5, count 0 2006.173.22:03:37.82#ibcon#flushed, iclass 5, count 0 2006.173.22:03:37.82#ibcon#about to write, iclass 5, count 0 2006.173.22:03:37.82#ibcon#wrote, iclass 5, count 0 2006.173.22:03:37.82#ibcon#about to read 3, iclass 5, count 0 2006.173.22:03:37.85#ibcon#read 3, iclass 5, count 0 2006.173.22:03:37.85#ibcon#about to read 4, iclass 5, count 0 2006.173.22:03:37.85#ibcon#read 4, iclass 5, count 0 2006.173.22:03:37.85#ibcon#about to read 5, iclass 5, count 0 2006.173.22:03:37.85#ibcon#read 5, iclass 5, count 0 2006.173.22:03:37.85#ibcon#about to read 6, iclass 5, count 0 2006.173.22:03:37.85#ibcon#read 6, iclass 5, count 0 2006.173.22:03:37.85#ibcon#end of sib2, iclass 5, count 0 2006.173.22:03:37.85#ibcon#*after write, iclass 5, count 0 2006.173.22:03:37.85#ibcon#*before return 0, iclass 5, count 0 2006.173.22:03:37.85#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.22:03:37.85#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.22:03:37.85#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.22:03:37.85#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.22:03:37.85$vck44/vblo=1,629.99 2006.173.22:03:37.85#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.22:03:37.85#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.22:03:37.85#ibcon#ireg 17 cls_cnt 0 2006.173.22:03:37.85#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.22:03:37.85#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.22:03:37.85#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.22:03:37.85#ibcon#enter wrdev, iclass 7, count 0 2006.173.22:03:37.85#ibcon#first serial, iclass 7, count 0 2006.173.22:03:37.85#ibcon#enter sib2, iclass 7, count 0 2006.173.22:03:37.85#ibcon#flushed, iclass 7, count 0 2006.173.22:03:37.85#ibcon#about to write, iclass 7, count 0 2006.173.22:03:37.85#ibcon#wrote, iclass 7, count 0 2006.173.22:03:37.85#ibcon#about to read 3, iclass 7, count 0 2006.173.22:03:37.87#ibcon#read 3, iclass 7, count 0 2006.173.22:03:37.87#ibcon#about to read 4, iclass 7, count 0 2006.173.22:03:37.87#ibcon#read 4, iclass 7, count 0 2006.173.22:03:37.87#ibcon#about to read 5, iclass 7, count 0 2006.173.22:03:37.87#ibcon#read 5, iclass 7, count 0 2006.173.22:03:37.87#ibcon#about to read 6, iclass 7, count 0 2006.173.22:03:37.87#ibcon#read 6, iclass 7, count 0 2006.173.22:03:37.87#ibcon#end of sib2, iclass 7, count 0 2006.173.22:03:37.87#ibcon#*mode == 0, iclass 7, count 0 2006.173.22:03:37.87#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.22:03:37.87#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.22:03:37.87#ibcon#*before write, iclass 7, count 0 2006.173.22:03:37.87#ibcon#enter sib2, iclass 7, count 0 2006.173.22:03:37.87#ibcon#flushed, iclass 7, count 0 2006.173.22:03:37.87#ibcon#about to write, iclass 7, count 0 2006.173.22:03:37.87#ibcon#wrote, iclass 7, count 0 2006.173.22:03:37.87#ibcon#about to read 3, iclass 7, count 0 2006.173.22:03:37.91#ibcon#read 3, iclass 7, count 0 2006.173.22:03:37.91#ibcon#about to read 4, iclass 7, count 0 2006.173.22:03:37.91#ibcon#read 4, iclass 7, count 0 2006.173.22:03:37.91#ibcon#about to read 5, iclass 7, count 0 2006.173.22:03:37.91#ibcon#read 5, iclass 7, count 0 2006.173.22:03:37.91#ibcon#about to read 6, iclass 7, count 0 2006.173.22:03:37.91#ibcon#read 6, iclass 7, count 0 2006.173.22:03:37.91#ibcon#end of sib2, iclass 7, count 0 2006.173.22:03:37.91#ibcon#*after write, iclass 7, count 0 2006.173.22:03:37.91#ibcon#*before return 0, iclass 7, count 0 2006.173.22:03:37.91#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.22:03:37.91#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.22:03:37.91#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.22:03:37.91#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.22:03:37.91$vck44/vb=1,4 2006.173.22:03:37.91#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.22:03:37.91#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.22:03:37.91#ibcon#ireg 11 cls_cnt 2 2006.173.22:03:37.91#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.22:03:37.91#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.22:03:37.91#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.22:03:37.91#ibcon#enter wrdev, iclass 11, count 2 2006.173.22:03:37.91#ibcon#first serial, iclass 11, count 2 2006.173.22:03:37.91#ibcon#enter sib2, iclass 11, count 2 2006.173.22:03:37.91#ibcon#flushed, iclass 11, count 2 2006.173.22:03:37.91#ibcon#about to write, iclass 11, count 2 2006.173.22:03:37.91#ibcon#wrote, iclass 11, count 2 2006.173.22:03:37.91#ibcon#about to read 3, iclass 11, count 2 2006.173.22:03:37.93#ibcon#read 3, iclass 11, count 2 2006.173.22:03:37.93#ibcon#about to read 4, iclass 11, count 2 2006.173.22:03:37.93#ibcon#read 4, iclass 11, count 2 2006.173.22:03:37.93#ibcon#about to read 5, iclass 11, count 2 2006.173.22:03:37.93#ibcon#read 5, iclass 11, count 2 2006.173.22:03:37.93#ibcon#about to read 6, iclass 11, count 2 2006.173.22:03:37.93#ibcon#read 6, iclass 11, count 2 2006.173.22:03:37.93#ibcon#end of sib2, iclass 11, count 2 2006.173.22:03:37.93#ibcon#*mode == 0, iclass 11, count 2 2006.173.22:03:37.93#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.22:03:37.93#ibcon#[27=AT01-04\r\n] 2006.173.22:03:37.93#ibcon#*before write, iclass 11, count 2 2006.173.22:03:37.93#ibcon#enter sib2, iclass 11, count 2 2006.173.22:03:37.93#ibcon#flushed, iclass 11, count 2 2006.173.22:03:37.93#ibcon#about to write, iclass 11, count 2 2006.173.22:03:37.93#ibcon#wrote, iclass 11, count 2 2006.173.22:03:37.93#ibcon#about to read 3, iclass 11, count 2 2006.173.22:03:37.96#ibcon#read 3, iclass 11, count 2 2006.173.22:03:37.96#ibcon#about to read 4, iclass 11, count 2 2006.173.22:03:37.96#ibcon#read 4, iclass 11, count 2 2006.173.22:03:37.96#ibcon#about to read 5, iclass 11, count 2 2006.173.22:03:37.96#ibcon#read 5, iclass 11, count 2 2006.173.22:03:37.96#ibcon#about to read 6, iclass 11, count 2 2006.173.22:03:37.96#ibcon#read 6, iclass 11, count 2 2006.173.22:03:37.96#ibcon#end of sib2, iclass 11, count 2 2006.173.22:03:37.96#ibcon#*after write, iclass 11, count 2 2006.173.22:03:37.96#ibcon#*before return 0, iclass 11, count 2 2006.173.22:03:37.96#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.22:03:37.96#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.22:03:37.96#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.22:03:37.96#ibcon#ireg 7 cls_cnt 0 2006.173.22:03:37.96#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.22:03:38.08#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.22:03:38.08#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.22:03:38.08#ibcon#enter wrdev, iclass 11, count 0 2006.173.22:03:38.08#ibcon#first serial, iclass 11, count 0 2006.173.22:03:38.08#ibcon#enter sib2, iclass 11, count 0 2006.173.22:03:38.08#ibcon#flushed, iclass 11, count 0 2006.173.22:03:38.08#ibcon#about to write, iclass 11, count 0 2006.173.22:03:38.08#ibcon#wrote, iclass 11, count 0 2006.173.22:03:38.08#ibcon#about to read 3, iclass 11, count 0 2006.173.22:03:38.10#ibcon#read 3, iclass 11, count 0 2006.173.22:03:38.10#ibcon#about to read 4, iclass 11, count 0 2006.173.22:03:38.10#ibcon#read 4, iclass 11, count 0 2006.173.22:03:38.10#ibcon#about to read 5, iclass 11, count 0 2006.173.22:03:38.10#ibcon#read 5, iclass 11, count 0 2006.173.22:03:38.10#ibcon#about to read 6, iclass 11, count 0 2006.173.22:03:38.10#ibcon#read 6, iclass 11, count 0 2006.173.22:03:38.10#ibcon#end of sib2, iclass 11, count 0 2006.173.22:03:38.10#ibcon#*mode == 0, iclass 11, count 0 2006.173.22:03:38.10#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.22:03:38.10#ibcon#[27=USB\r\n] 2006.173.22:03:38.10#ibcon#*before write, iclass 11, count 0 2006.173.22:03:38.10#ibcon#enter sib2, iclass 11, count 0 2006.173.22:03:38.10#ibcon#flushed, iclass 11, count 0 2006.173.22:03:38.10#ibcon#about to write, iclass 11, count 0 2006.173.22:03:38.10#ibcon#wrote, iclass 11, count 0 2006.173.22:03:38.10#ibcon#about to read 3, iclass 11, count 0 2006.173.22:03:38.13#ibcon#read 3, iclass 11, count 0 2006.173.22:03:38.13#ibcon#about to read 4, iclass 11, count 0 2006.173.22:03:38.13#ibcon#read 4, iclass 11, count 0 2006.173.22:03:38.13#ibcon#about to read 5, iclass 11, count 0 2006.173.22:03:38.13#ibcon#read 5, iclass 11, count 0 2006.173.22:03:38.13#ibcon#about to read 6, iclass 11, count 0 2006.173.22:03:38.13#ibcon#read 6, iclass 11, count 0 2006.173.22:03:38.13#ibcon#end of sib2, iclass 11, count 0 2006.173.22:03:38.13#ibcon#*after write, iclass 11, count 0 2006.173.22:03:38.13#ibcon#*before return 0, iclass 11, count 0 2006.173.22:03:38.13#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.22:03:38.13#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.22:03:38.13#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.22:03:38.13#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.22:03:38.13$vck44/vblo=2,634.99 2006.173.22:03:38.13#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.22:03:38.13#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.22:03:38.13#ibcon#ireg 17 cls_cnt 0 2006.173.22:03:38.13#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.22:03:38.13#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.22:03:38.13#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.22:03:38.13#ibcon#enter wrdev, iclass 13, count 0 2006.173.22:03:38.13#ibcon#first serial, iclass 13, count 0 2006.173.22:03:38.13#ibcon#enter sib2, iclass 13, count 0 2006.173.22:03:38.13#ibcon#flushed, iclass 13, count 0 2006.173.22:03:38.13#ibcon#about to write, iclass 13, count 0 2006.173.22:03:38.13#ibcon#wrote, iclass 13, count 0 2006.173.22:03:38.13#ibcon#about to read 3, iclass 13, count 0 2006.173.22:03:38.15#ibcon#read 3, iclass 13, count 0 2006.173.22:03:38.15#ibcon#about to read 4, iclass 13, count 0 2006.173.22:03:38.15#ibcon#read 4, iclass 13, count 0 2006.173.22:03:38.15#ibcon#about to read 5, iclass 13, count 0 2006.173.22:03:38.15#ibcon#read 5, iclass 13, count 0 2006.173.22:03:38.15#ibcon#about to read 6, iclass 13, count 0 2006.173.22:03:38.15#ibcon#read 6, iclass 13, count 0 2006.173.22:03:38.15#ibcon#end of sib2, iclass 13, count 0 2006.173.22:03:38.15#ibcon#*mode == 0, iclass 13, count 0 2006.173.22:03:38.15#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.22:03:38.15#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.22:03:38.15#ibcon#*before write, iclass 13, count 0 2006.173.22:03:38.15#ibcon#enter sib2, iclass 13, count 0 2006.173.22:03:38.15#ibcon#flushed, iclass 13, count 0 2006.173.22:03:38.15#ibcon#about to write, iclass 13, count 0 2006.173.22:03:38.15#ibcon#wrote, iclass 13, count 0 2006.173.22:03:38.15#ibcon#about to read 3, iclass 13, count 0 2006.173.22:03:38.19#ibcon#read 3, iclass 13, count 0 2006.173.22:03:38.19#ibcon#about to read 4, iclass 13, count 0 2006.173.22:03:38.19#ibcon#read 4, iclass 13, count 0 2006.173.22:03:38.19#ibcon#about to read 5, iclass 13, count 0 2006.173.22:03:38.19#ibcon#read 5, iclass 13, count 0 2006.173.22:03:38.19#ibcon#about to read 6, iclass 13, count 0 2006.173.22:03:38.19#ibcon#read 6, iclass 13, count 0 2006.173.22:03:38.19#ibcon#end of sib2, iclass 13, count 0 2006.173.22:03:38.19#ibcon#*after write, iclass 13, count 0 2006.173.22:03:38.19#ibcon#*before return 0, iclass 13, count 0 2006.173.22:03:38.19#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.22:03:38.19#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.22:03:38.19#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.22:03:38.19#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.22:03:38.19$vck44/vb=2,4 2006.173.22:03:38.19#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.22:03:38.19#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.22:03:38.19#ibcon#ireg 11 cls_cnt 2 2006.173.22:03:38.19#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.22:03:38.25#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.22:03:38.25#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.22:03:38.25#ibcon#enter wrdev, iclass 15, count 2 2006.173.22:03:38.25#ibcon#first serial, iclass 15, count 2 2006.173.22:03:38.25#ibcon#enter sib2, iclass 15, count 2 2006.173.22:03:38.25#ibcon#flushed, iclass 15, count 2 2006.173.22:03:38.25#ibcon#about to write, iclass 15, count 2 2006.173.22:03:38.25#ibcon#wrote, iclass 15, count 2 2006.173.22:03:38.25#ibcon#about to read 3, iclass 15, count 2 2006.173.22:03:38.27#ibcon#read 3, iclass 15, count 2 2006.173.22:03:38.27#ibcon#about to read 4, iclass 15, count 2 2006.173.22:03:38.27#ibcon#read 4, iclass 15, count 2 2006.173.22:03:38.27#ibcon#about to read 5, iclass 15, count 2 2006.173.22:03:38.27#ibcon#read 5, iclass 15, count 2 2006.173.22:03:38.27#ibcon#about to read 6, iclass 15, count 2 2006.173.22:03:38.27#ibcon#read 6, iclass 15, count 2 2006.173.22:03:38.27#ibcon#end of sib2, iclass 15, count 2 2006.173.22:03:38.27#ibcon#*mode == 0, iclass 15, count 2 2006.173.22:03:38.27#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.22:03:38.27#ibcon#[27=AT02-04\r\n] 2006.173.22:03:38.27#ibcon#*before write, iclass 15, count 2 2006.173.22:03:38.27#ibcon#enter sib2, iclass 15, count 2 2006.173.22:03:38.27#ibcon#flushed, iclass 15, count 2 2006.173.22:03:38.27#ibcon#about to write, iclass 15, count 2 2006.173.22:03:38.27#ibcon#wrote, iclass 15, count 2 2006.173.22:03:38.27#ibcon#about to read 3, iclass 15, count 2 2006.173.22:03:38.30#ibcon#read 3, iclass 15, count 2 2006.173.22:03:38.30#ibcon#about to read 4, iclass 15, count 2 2006.173.22:03:38.30#ibcon#read 4, iclass 15, count 2 2006.173.22:03:38.30#ibcon#about to read 5, iclass 15, count 2 2006.173.22:03:38.30#ibcon#read 5, iclass 15, count 2 2006.173.22:03:38.30#ibcon#about to read 6, iclass 15, count 2 2006.173.22:03:38.30#ibcon#read 6, iclass 15, count 2 2006.173.22:03:38.30#ibcon#end of sib2, iclass 15, count 2 2006.173.22:03:38.30#ibcon#*after write, iclass 15, count 2 2006.173.22:03:38.30#ibcon#*before return 0, iclass 15, count 2 2006.173.22:03:38.30#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.22:03:38.30#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.22:03:38.30#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.22:03:38.30#ibcon#ireg 7 cls_cnt 0 2006.173.22:03:38.30#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.22:03:38.42#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.22:03:38.42#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.22:03:38.42#ibcon#enter wrdev, iclass 15, count 0 2006.173.22:03:38.42#ibcon#first serial, iclass 15, count 0 2006.173.22:03:38.42#ibcon#enter sib2, iclass 15, count 0 2006.173.22:03:38.42#ibcon#flushed, iclass 15, count 0 2006.173.22:03:38.42#ibcon#about to write, iclass 15, count 0 2006.173.22:03:38.42#ibcon#wrote, iclass 15, count 0 2006.173.22:03:38.42#ibcon#about to read 3, iclass 15, count 0 2006.173.22:03:38.44#ibcon#read 3, iclass 15, count 0 2006.173.22:03:38.44#ibcon#about to read 4, iclass 15, count 0 2006.173.22:03:38.44#ibcon#read 4, iclass 15, count 0 2006.173.22:03:38.44#ibcon#about to read 5, iclass 15, count 0 2006.173.22:03:38.44#ibcon#read 5, iclass 15, count 0 2006.173.22:03:38.44#ibcon#about to read 6, iclass 15, count 0 2006.173.22:03:38.44#ibcon#read 6, iclass 15, count 0 2006.173.22:03:38.44#ibcon#end of sib2, iclass 15, count 0 2006.173.22:03:38.44#ibcon#*mode == 0, iclass 15, count 0 2006.173.22:03:38.44#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.22:03:38.44#ibcon#[27=USB\r\n] 2006.173.22:03:38.44#ibcon#*before write, iclass 15, count 0 2006.173.22:03:38.44#ibcon#enter sib2, iclass 15, count 0 2006.173.22:03:38.44#ibcon#flushed, iclass 15, count 0 2006.173.22:03:38.44#ibcon#about to write, iclass 15, count 0 2006.173.22:03:38.44#ibcon#wrote, iclass 15, count 0 2006.173.22:03:38.44#ibcon#about to read 3, iclass 15, count 0 2006.173.22:03:38.47#ibcon#read 3, iclass 15, count 0 2006.173.22:03:38.47#ibcon#about to read 4, iclass 15, count 0 2006.173.22:03:38.47#ibcon#read 4, iclass 15, count 0 2006.173.22:03:38.47#ibcon#about to read 5, iclass 15, count 0 2006.173.22:03:38.47#ibcon#read 5, iclass 15, count 0 2006.173.22:03:38.47#ibcon#about to read 6, iclass 15, count 0 2006.173.22:03:38.47#ibcon#read 6, iclass 15, count 0 2006.173.22:03:38.47#ibcon#end of sib2, iclass 15, count 0 2006.173.22:03:38.47#ibcon#*after write, iclass 15, count 0 2006.173.22:03:38.47#ibcon#*before return 0, iclass 15, count 0 2006.173.22:03:38.47#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.22:03:38.47#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.22:03:38.47#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.22:03:38.47#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.22:03:38.47$vck44/vblo=3,649.99 2006.173.22:03:38.47#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.22:03:38.47#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.22:03:38.47#ibcon#ireg 17 cls_cnt 0 2006.173.22:03:38.47#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.22:03:38.47#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.22:03:38.47#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.22:03:38.47#ibcon#enter wrdev, iclass 17, count 0 2006.173.22:03:38.47#ibcon#first serial, iclass 17, count 0 2006.173.22:03:38.47#ibcon#enter sib2, iclass 17, count 0 2006.173.22:03:38.47#ibcon#flushed, iclass 17, count 0 2006.173.22:03:38.47#ibcon#about to write, iclass 17, count 0 2006.173.22:03:38.47#ibcon#wrote, iclass 17, count 0 2006.173.22:03:38.47#ibcon#about to read 3, iclass 17, count 0 2006.173.22:03:38.49#ibcon#read 3, iclass 17, count 0 2006.173.22:03:38.49#ibcon#about to read 4, iclass 17, count 0 2006.173.22:03:38.49#ibcon#read 4, iclass 17, count 0 2006.173.22:03:38.49#ibcon#about to read 5, iclass 17, count 0 2006.173.22:03:38.49#ibcon#read 5, iclass 17, count 0 2006.173.22:03:38.49#ibcon#about to read 6, iclass 17, count 0 2006.173.22:03:38.49#ibcon#read 6, iclass 17, count 0 2006.173.22:03:38.49#ibcon#end of sib2, iclass 17, count 0 2006.173.22:03:38.49#ibcon#*mode == 0, iclass 17, count 0 2006.173.22:03:38.49#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.22:03:38.49#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.22:03:38.49#ibcon#*before write, iclass 17, count 0 2006.173.22:03:38.49#ibcon#enter sib2, iclass 17, count 0 2006.173.22:03:38.49#ibcon#flushed, iclass 17, count 0 2006.173.22:03:38.49#ibcon#about to write, iclass 17, count 0 2006.173.22:03:38.49#ibcon#wrote, iclass 17, count 0 2006.173.22:03:38.49#ibcon#about to read 3, iclass 17, count 0 2006.173.22:03:38.53#ibcon#read 3, iclass 17, count 0 2006.173.22:03:38.53#ibcon#about to read 4, iclass 17, count 0 2006.173.22:03:38.53#ibcon#read 4, iclass 17, count 0 2006.173.22:03:38.53#ibcon#about to read 5, iclass 17, count 0 2006.173.22:03:38.53#ibcon#read 5, iclass 17, count 0 2006.173.22:03:38.53#ibcon#about to read 6, iclass 17, count 0 2006.173.22:03:38.53#ibcon#read 6, iclass 17, count 0 2006.173.22:03:38.53#ibcon#end of sib2, iclass 17, count 0 2006.173.22:03:38.53#ibcon#*after write, iclass 17, count 0 2006.173.22:03:38.53#ibcon#*before return 0, iclass 17, count 0 2006.173.22:03:38.53#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.22:03:38.53#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.22:03:38.53#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.22:03:38.53#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.22:03:38.53$vck44/vb=3,4 2006.173.22:03:38.53#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.22:03:38.53#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.22:03:38.53#ibcon#ireg 11 cls_cnt 2 2006.173.22:03:38.53#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.22:03:38.59#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.22:03:38.59#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.22:03:38.59#ibcon#enter wrdev, iclass 19, count 2 2006.173.22:03:38.59#ibcon#first serial, iclass 19, count 2 2006.173.22:03:38.59#ibcon#enter sib2, iclass 19, count 2 2006.173.22:03:38.59#ibcon#flushed, iclass 19, count 2 2006.173.22:03:38.59#ibcon#about to write, iclass 19, count 2 2006.173.22:03:38.59#ibcon#wrote, iclass 19, count 2 2006.173.22:03:38.59#ibcon#about to read 3, iclass 19, count 2 2006.173.22:03:38.61#ibcon#read 3, iclass 19, count 2 2006.173.22:03:38.61#ibcon#about to read 4, iclass 19, count 2 2006.173.22:03:38.61#ibcon#read 4, iclass 19, count 2 2006.173.22:03:38.61#ibcon#about to read 5, iclass 19, count 2 2006.173.22:03:38.61#ibcon#read 5, iclass 19, count 2 2006.173.22:03:38.61#ibcon#about to read 6, iclass 19, count 2 2006.173.22:03:38.61#ibcon#read 6, iclass 19, count 2 2006.173.22:03:38.61#ibcon#end of sib2, iclass 19, count 2 2006.173.22:03:38.61#ibcon#*mode == 0, iclass 19, count 2 2006.173.22:03:38.61#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.22:03:38.61#ibcon#[27=AT03-04\r\n] 2006.173.22:03:38.61#ibcon#*before write, iclass 19, count 2 2006.173.22:03:38.61#ibcon#enter sib2, iclass 19, count 2 2006.173.22:03:38.61#ibcon#flushed, iclass 19, count 2 2006.173.22:03:38.61#ibcon#about to write, iclass 19, count 2 2006.173.22:03:38.61#ibcon#wrote, iclass 19, count 2 2006.173.22:03:38.61#ibcon#about to read 3, iclass 19, count 2 2006.173.22:03:38.64#ibcon#read 3, iclass 19, count 2 2006.173.22:03:38.64#ibcon#about to read 4, iclass 19, count 2 2006.173.22:03:38.64#ibcon#read 4, iclass 19, count 2 2006.173.22:03:38.64#ibcon#about to read 5, iclass 19, count 2 2006.173.22:03:38.64#ibcon#read 5, iclass 19, count 2 2006.173.22:03:38.64#ibcon#about to read 6, iclass 19, count 2 2006.173.22:03:38.64#ibcon#read 6, iclass 19, count 2 2006.173.22:03:38.64#ibcon#end of sib2, iclass 19, count 2 2006.173.22:03:38.64#ibcon#*after write, iclass 19, count 2 2006.173.22:03:38.64#ibcon#*before return 0, iclass 19, count 2 2006.173.22:03:38.64#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.22:03:38.64#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.22:03:38.64#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.22:03:38.64#ibcon#ireg 7 cls_cnt 0 2006.173.22:03:38.64#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.22:03:38.76#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.22:03:38.76#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.22:03:38.76#ibcon#enter wrdev, iclass 19, count 0 2006.173.22:03:38.76#ibcon#first serial, iclass 19, count 0 2006.173.22:03:38.76#ibcon#enter sib2, iclass 19, count 0 2006.173.22:03:38.76#ibcon#flushed, iclass 19, count 0 2006.173.22:03:38.76#ibcon#about to write, iclass 19, count 0 2006.173.22:03:38.76#ibcon#wrote, iclass 19, count 0 2006.173.22:03:38.76#ibcon#about to read 3, iclass 19, count 0 2006.173.22:03:38.78#ibcon#read 3, iclass 19, count 0 2006.173.22:03:38.78#ibcon#about to read 4, iclass 19, count 0 2006.173.22:03:38.78#ibcon#read 4, iclass 19, count 0 2006.173.22:03:38.78#ibcon#about to read 5, iclass 19, count 0 2006.173.22:03:38.78#ibcon#read 5, iclass 19, count 0 2006.173.22:03:38.78#ibcon#about to read 6, iclass 19, count 0 2006.173.22:03:38.78#ibcon#read 6, iclass 19, count 0 2006.173.22:03:38.78#ibcon#end of sib2, iclass 19, count 0 2006.173.22:03:38.78#ibcon#*mode == 0, iclass 19, count 0 2006.173.22:03:38.78#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.22:03:38.78#ibcon#[27=USB\r\n] 2006.173.22:03:38.78#ibcon#*before write, iclass 19, count 0 2006.173.22:03:38.78#ibcon#enter sib2, iclass 19, count 0 2006.173.22:03:38.78#ibcon#flushed, iclass 19, count 0 2006.173.22:03:38.78#ibcon#about to write, iclass 19, count 0 2006.173.22:03:38.78#ibcon#wrote, iclass 19, count 0 2006.173.22:03:38.78#ibcon#about to read 3, iclass 19, count 0 2006.173.22:03:38.81#ibcon#read 3, iclass 19, count 0 2006.173.22:03:38.81#ibcon#about to read 4, iclass 19, count 0 2006.173.22:03:38.81#ibcon#read 4, iclass 19, count 0 2006.173.22:03:38.81#ibcon#about to read 5, iclass 19, count 0 2006.173.22:03:38.81#ibcon#read 5, iclass 19, count 0 2006.173.22:03:38.81#ibcon#about to read 6, iclass 19, count 0 2006.173.22:03:38.81#ibcon#read 6, iclass 19, count 0 2006.173.22:03:38.81#ibcon#end of sib2, iclass 19, count 0 2006.173.22:03:38.81#ibcon#*after write, iclass 19, count 0 2006.173.22:03:38.81#ibcon#*before return 0, iclass 19, count 0 2006.173.22:03:38.81#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.22:03:38.81#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.22:03:38.81#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.22:03:38.81#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.22:03:38.81$vck44/vblo=4,679.99 2006.173.22:03:38.81#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.22:03:38.81#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.22:03:38.81#ibcon#ireg 17 cls_cnt 0 2006.173.22:03:38.81#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.22:03:38.81#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.22:03:38.81#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.22:03:38.81#ibcon#enter wrdev, iclass 21, count 0 2006.173.22:03:38.81#ibcon#first serial, iclass 21, count 0 2006.173.22:03:38.81#ibcon#enter sib2, iclass 21, count 0 2006.173.22:03:38.81#ibcon#flushed, iclass 21, count 0 2006.173.22:03:38.81#ibcon#about to write, iclass 21, count 0 2006.173.22:03:38.81#ibcon#wrote, iclass 21, count 0 2006.173.22:03:38.81#ibcon#about to read 3, iclass 21, count 0 2006.173.22:03:38.83#ibcon#read 3, iclass 21, count 0 2006.173.22:03:38.83#ibcon#about to read 4, iclass 21, count 0 2006.173.22:03:38.83#ibcon#read 4, iclass 21, count 0 2006.173.22:03:38.83#ibcon#about to read 5, iclass 21, count 0 2006.173.22:03:38.83#ibcon#read 5, iclass 21, count 0 2006.173.22:03:38.83#ibcon#about to read 6, iclass 21, count 0 2006.173.22:03:38.83#ibcon#read 6, iclass 21, count 0 2006.173.22:03:38.83#ibcon#end of sib2, iclass 21, count 0 2006.173.22:03:38.83#ibcon#*mode == 0, iclass 21, count 0 2006.173.22:03:38.83#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.22:03:38.83#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.22:03:38.83#ibcon#*before write, iclass 21, count 0 2006.173.22:03:38.83#ibcon#enter sib2, iclass 21, count 0 2006.173.22:03:38.83#ibcon#flushed, iclass 21, count 0 2006.173.22:03:38.83#ibcon#about to write, iclass 21, count 0 2006.173.22:03:38.83#ibcon#wrote, iclass 21, count 0 2006.173.22:03:38.83#ibcon#about to read 3, iclass 21, count 0 2006.173.22:03:38.87#ibcon#read 3, iclass 21, count 0 2006.173.22:03:38.87#ibcon#about to read 4, iclass 21, count 0 2006.173.22:03:38.87#ibcon#read 4, iclass 21, count 0 2006.173.22:03:38.87#ibcon#about to read 5, iclass 21, count 0 2006.173.22:03:38.87#ibcon#read 5, iclass 21, count 0 2006.173.22:03:38.87#ibcon#about to read 6, iclass 21, count 0 2006.173.22:03:38.87#ibcon#read 6, iclass 21, count 0 2006.173.22:03:38.87#ibcon#end of sib2, iclass 21, count 0 2006.173.22:03:38.87#ibcon#*after write, iclass 21, count 0 2006.173.22:03:38.87#ibcon#*before return 0, iclass 21, count 0 2006.173.22:03:38.87#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.22:03:38.87#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.22:03:38.87#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.22:03:38.87#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.22:03:38.87$vck44/vb=4,4 2006.173.22:03:38.87#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.22:03:38.87#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.22:03:38.87#ibcon#ireg 11 cls_cnt 2 2006.173.22:03:38.87#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.22:03:38.93#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.22:03:38.93#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.22:03:38.93#ibcon#enter wrdev, iclass 23, count 2 2006.173.22:03:38.93#ibcon#first serial, iclass 23, count 2 2006.173.22:03:38.93#ibcon#enter sib2, iclass 23, count 2 2006.173.22:03:38.93#ibcon#flushed, iclass 23, count 2 2006.173.22:03:38.93#ibcon#about to write, iclass 23, count 2 2006.173.22:03:38.93#ibcon#wrote, iclass 23, count 2 2006.173.22:03:38.93#ibcon#about to read 3, iclass 23, count 2 2006.173.22:03:38.95#ibcon#read 3, iclass 23, count 2 2006.173.22:03:38.95#ibcon#about to read 4, iclass 23, count 2 2006.173.22:03:38.95#ibcon#read 4, iclass 23, count 2 2006.173.22:03:38.95#ibcon#about to read 5, iclass 23, count 2 2006.173.22:03:38.95#ibcon#read 5, iclass 23, count 2 2006.173.22:03:38.95#ibcon#about to read 6, iclass 23, count 2 2006.173.22:03:38.95#ibcon#read 6, iclass 23, count 2 2006.173.22:03:38.95#ibcon#end of sib2, iclass 23, count 2 2006.173.22:03:38.95#ibcon#*mode == 0, iclass 23, count 2 2006.173.22:03:38.95#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.22:03:38.95#ibcon#[27=AT04-04\r\n] 2006.173.22:03:38.95#ibcon#*before write, iclass 23, count 2 2006.173.22:03:38.95#ibcon#enter sib2, iclass 23, count 2 2006.173.22:03:38.95#ibcon#flushed, iclass 23, count 2 2006.173.22:03:38.95#ibcon#about to write, iclass 23, count 2 2006.173.22:03:38.95#ibcon#wrote, iclass 23, count 2 2006.173.22:03:38.95#ibcon#about to read 3, iclass 23, count 2 2006.173.22:03:38.98#ibcon#read 3, iclass 23, count 2 2006.173.22:03:38.98#ibcon#about to read 4, iclass 23, count 2 2006.173.22:03:38.98#ibcon#read 4, iclass 23, count 2 2006.173.22:03:38.98#ibcon#about to read 5, iclass 23, count 2 2006.173.22:03:38.98#ibcon#read 5, iclass 23, count 2 2006.173.22:03:38.98#ibcon#about to read 6, iclass 23, count 2 2006.173.22:03:38.98#ibcon#read 6, iclass 23, count 2 2006.173.22:03:38.98#ibcon#end of sib2, iclass 23, count 2 2006.173.22:03:38.98#ibcon#*after write, iclass 23, count 2 2006.173.22:03:38.98#ibcon#*before return 0, iclass 23, count 2 2006.173.22:03:38.98#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.22:03:38.98#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.22:03:38.98#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.22:03:38.98#ibcon#ireg 7 cls_cnt 0 2006.173.22:03:38.98#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.22:03:39.10#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.22:03:39.10#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.22:03:39.10#ibcon#enter wrdev, iclass 23, count 0 2006.173.22:03:39.10#ibcon#first serial, iclass 23, count 0 2006.173.22:03:39.10#ibcon#enter sib2, iclass 23, count 0 2006.173.22:03:39.10#ibcon#flushed, iclass 23, count 0 2006.173.22:03:39.10#ibcon#about to write, iclass 23, count 0 2006.173.22:03:39.10#ibcon#wrote, iclass 23, count 0 2006.173.22:03:39.10#ibcon#about to read 3, iclass 23, count 0 2006.173.22:03:39.12#ibcon#read 3, iclass 23, count 0 2006.173.22:03:39.12#ibcon#about to read 4, iclass 23, count 0 2006.173.22:03:39.12#ibcon#read 4, iclass 23, count 0 2006.173.22:03:39.12#ibcon#about to read 5, iclass 23, count 0 2006.173.22:03:39.12#ibcon#read 5, iclass 23, count 0 2006.173.22:03:39.12#ibcon#about to read 6, iclass 23, count 0 2006.173.22:03:39.12#ibcon#read 6, iclass 23, count 0 2006.173.22:03:39.12#ibcon#end of sib2, iclass 23, count 0 2006.173.22:03:39.12#ibcon#*mode == 0, iclass 23, count 0 2006.173.22:03:39.12#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.22:03:39.12#ibcon#[27=USB\r\n] 2006.173.22:03:39.12#ibcon#*before write, iclass 23, count 0 2006.173.22:03:39.12#ibcon#enter sib2, iclass 23, count 0 2006.173.22:03:39.12#ibcon#flushed, iclass 23, count 0 2006.173.22:03:39.12#ibcon#about to write, iclass 23, count 0 2006.173.22:03:39.12#ibcon#wrote, iclass 23, count 0 2006.173.22:03:39.12#ibcon#about to read 3, iclass 23, count 0 2006.173.22:03:39.15#ibcon#read 3, iclass 23, count 0 2006.173.22:03:39.15#ibcon#about to read 4, iclass 23, count 0 2006.173.22:03:39.15#ibcon#read 4, iclass 23, count 0 2006.173.22:03:39.15#ibcon#about to read 5, iclass 23, count 0 2006.173.22:03:39.15#ibcon#read 5, iclass 23, count 0 2006.173.22:03:39.15#ibcon#about to read 6, iclass 23, count 0 2006.173.22:03:39.15#ibcon#read 6, iclass 23, count 0 2006.173.22:03:39.15#ibcon#end of sib2, iclass 23, count 0 2006.173.22:03:39.15#ibcon#*after write, iclass 23, count 0 2006.173.22:03:39.15#ibcon#*before return 0, iclass 23, count 0 2006.173.22:03:39.15#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.22:03:39.15#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.22:03:39.15#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.22:03:39.15#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.22:03:39.15$vck44/vblo=5,709.99 2006.173.22:03:39.15#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.22:03:39.15#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.22:03:39.15#ibcon#ireg 17 cls_cnt 0 2006.173.22:03:39.15#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.22:03:39.15#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.22:03:39.15#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.22:03:39.15#ibcon#enter wrdev, iclass 25, count 0 2006.173.22:03:39.15#ibcon#first serial, iclass 25, count 0 2006.173.22:03:39.15#ibcon#enter sib2, iclass 25, count 0 2006.173.22:03:39.15#ibcon#flushed, iclass 25, count 0 2006.173.22:03:39.15#ibcon#about to write, iclass 25, count 0 2006.173.22:03:39.15#ibcon#wrote, iclass 25, count 0 2006.173.22:03:39.15#ibcon#about to read 3, iclass 25, count 0 2006.173.22:03:39.17#ibcon#read 3, iclass 25, count 0 2006.173.22:03:39.17#ibcon#about to read 4, iclass 25, count 0 2006.173.22:03:39.17#ibcon#read 4, iclass 25, count 0 2006.173.22:03:39.17#ibcon#about to read 5, iclass 25, count 0 2006.173.22:03:39.17#ibcon#read 5, iclass 25, count 0 2006.173.22:03:39.17#ibcon#about to read 6, iclass 25, count 0 2006.173.22:03:39.17#ibcon#read 6, iclass 25, count 0 2006.173.22:03:39.17#ibcon#end of sib2, iclass 25, count 0 2006.173.22:03:39.17#ibcon#*mode == 0, iclass 25, count 0 2006.173.22:03:39.17#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.22:03:39.17#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.22:03:39.17#ibcon#*before write, iclass 25, count 0 2006.173.22:03:39.17#ibcon#enter sib2, iclass 25, count 0 2006.173.22:03:39.17#ibcon#flushed, iclass 25, count 0 2006.173.22:03:39.17#ibcon#about to write, iclass 25, count 0 2006.173.22:03:39.17#ibcon#wrote, iclass 25, count 0 2006.173.22:03:39.17#ibcon#about to read 3, iclass 25, count 0 2006.173.22:03:39.21#ibcon#read 3, iclass 25, count 0 2006.173.22:03:39.21#ibcon#about to read 4, iclass 25, count 0 2006.173.22:03:39.21#ibcon#read 4, iclass 25, count 0 2006.173.22:03:39.21#ibcon#about to read 5, iclass 25, count 0 2006.173.22:03:39.21#ibcon#read 5, iclass 25, count 0 2006.173.22:03:39.21#ibcon#about to read 6, iclass 25, count 0 2006.173.22:03:39.21#ibcon#read 6, iclass 25, count 0 2006.173.22:03:39.21#ibcon#end of sib2, iclass 25, count 0 2006.173.22:03:39.21#ibcon#*after write, iclass 25, count 0 2006.173.22:03:39.21#ibcon#*before return 0, iclass 25, count 0 2006.173.22:03:39.21#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.22:03:39.21#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.22:03:39.21#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.22:03:39.21#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.22:03:39.21$vck44/vb=5,4 2006.173.22:03:39.21#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.22:03:39.21#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.22:03:39.21#ibcon#ireg 11 cls_cnt 2 2006.173.22:03:39.21#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.22:03:39.27#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.22:03:39.27#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.22:03:39.27#ibcon#enter wrdev, iclass 27, count 2 2006.173.22:03:39.27#ibcon#first serial, iclass 27, count 2 2006.173.22:03:39.27#ibcon#enter sib2, iclass 27, count 2 2006.173.22:03:39.27#ibcon#flushed, iclass 27, count 2 2006.173.22:03:39.27#ibcon#about to write, iclass 27, count 2 2006.173.22:03:39.27#ibcon#wrote, iclass 27, count 2 2006.173.22:03:39.27#ibcon#about to read 3, iclass 27, count 2 2006.173.22:03:39.29#ibcon#read 3, iclass 27, count 2 2006.173.22:03:39.29#ibcon#about to read 4, iclass 27, count 2 2006.173.22:03:39.29#ibcon#read 4, iclass 27, count 2 2006.173.22:03:39.29#ibcon#about to read 5, iclass 27, count 2 2006.173.22:03:39.29#ibcon#read 5, iclass 27, count 2 2006.173.22:03:39.29#ibcon#about to read 6, iclass 27, count 2 2006.173.22:03:39.29#ibcon#read 6, iclass 27, count 2 2006.173.22:03:39.29#ibcon#end of sib2, iclass 27, count 2 2006.173.22:03:39.29#ibcon#*mode == 0, iclass 27, count 2 2006.173.22:03:39.29#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.22:03:39.29#ibcon#[27=AT05-04\r\n] 2006.173.22:03:39.29#ibcon#*before write, iclass 27, count 2 2006.173.22:03:39.29#ibcon#enter sib2, iclass 27, count 2 2006.173.22:03:39.29#ibcon#flushed, iclass 27, count 2 2006.173.22:03:39.29#ibcon#about to write, iclass 27, count 2 2006.173.22:03:39.29#ibcon#wrote, iclass 27, count 2 2006.173.22:03:39.29#ibcon#about to read 3, iclass 27, count 2 2006.173.22:03:39.32#ibcon#read 3, iclass 27, count 2 2006.173.22:03:39.32#ibcon#about to read 4, iclass 27, count 2 2006.173.22:03:39.32#ibcon#read 4, iclass 27, count 2 2006.173.22:03:39.32#ibcon#about to read 5, iclass 27, count 2 2006.173.22:03:39.32#ibcon#read 5, iclass 27, count 2 2006.173.22:03:39.32#ibcon#about to read 6, iclass 27, count 2 2006.173.22:03:39.32#ibcon#read 6, iclass 27, count 2 2006.173.22:03:39.32#ibcon#end of sib2, iclass 27, count 2 2006.173.22:03:39.32#ibcon#*after write, iclass 27, count 2 2006.173.22:03:39.32#ibcon#*before return 0, iclass 27, count 2 2006.173.22:03:39.32#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.22:03:39.32#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.22:03:39.32#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.22:03:39.32#ibcon#ireg 7 cls_cnt 0 2006.173.22:03:39.32#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.22:03:39.44#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.22:03:39.44#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.22:03:39.44#ibcon#enter wrdev, iclass 27, count 0 2006.173.22:03:39.44#ibcon#first serial, iclass 27, count 0 2006.173.22:03:39.44#ibcon#enter sib2, iclass 27, count 0 2006.173.22:03:39.44#ibcon#flushed, iclass 27, count 0 2006.173.22:03:39.44#ibcon#about to write, iclass 27, count 0 2006.173.22:03:39.44#ibcon#wrote, iclass 27, count 0 2006.173.22:03:39.44#ibcon#about to read 3, iclass 27, count 0 2006.173.22:03:39.46#ibcon#read 3, iclass 27, count 0 2006.173.22:03:39.46#ibcon#about to read 4, iclass 27, count 0 2006.173.22:03:39.46#ibcon#read 4, iclass 27, count 0 2006.173.22:03:39.46#ibcon#about to read 5, iclass 27, count 0 2006.173.22:03:39.46#ibcon#read 5, iclass 27, count 0 2006.173.22:03:39.46#ibcon#about to read 6, iclass 27, count 0 2006.173.22:03:39.46#ibcon#read 6, iclass 27, count 0 2006.173.22:03:39.46#ibcon#end of sib2, iclass 27, count 0 2006.173.22:03:39.46#ibcon#*mode == 0, iclass 27, count 0 2006.173.22:03:39.46#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.22:03:39.46#ibcon#[27=USB\r\n] 2006.173.22:03:39.46#ibcon#*before write, iclass 27, count 0 2006.173.22:03:39.46#ibcon#enter sib2, iclass 27, count 0 2006.173.22:03:39.46#ibcon#flushed, iclass 27, count 0 2006.173.22:03:39.46#ibcon#about to write, iclass 27, count 0 2006.173.22:03:39.46#ibcon#wrote, iclass 27, count 0 2006.173.22:03:39.46#ibcon#about to read 3, iclass 27, count 0 2006.173.22:03:39.49#ibcon#read 3, iclass 27, count 0 2006.173.22:03:39.49#ibcon#about to read 4, iclass 27, count 0 2006.173.22:03:39.49#ibcon#read 4, iclass 27, count 0 2006.173.22:03:39.49#ibcon#about to read 5, iclass 27, count 0 2006.173.22:03:39.49#ibcon#read 5, iclass 27, count 0 2006.173.22:03:39.49#ibcon#about to read 6, iclass 27, count 0 2006.173.22:03:39.49#ibcon#read 6, iclass 27, count 0 2006.173.22:03:39.49#ibcon#end of sib2, iclass 27, count 0 2006.173.22:03:39.49#ibcon#*after write, iclass 27, count 0 2006.173.22:03:39.49#ibcon#*before return 0, iclass 27, count 0 2006.173.22:03:39.49#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.22:03:39.49#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.22:03:39.49#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.22:03:39.49#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.22:03:39.49$vck44/vblo=6,719.99 2006.173.22:03:39.49#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.22:03:39.49#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.22:03:39.49#ibcon#ireg 17 cls_cnt 0 2006.173.22:03:39.49#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.22:03:39.49#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.22:03:39.49#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.22:03:39.49#ibcon#enter wrdev, iclass 29, count 0 2006.173.22:03:39.49#ibcon#first serial, iclass 29, count 0 2006.173.22:03:39.49#ibcon#enter sib2, iclass 29, count 0 2006.173.22:03:39.49#ibcon#flushed, iclass 29, count 0 2006.173.22:03:39.49#ibcon#about to write, iclass 29, count 0 2006.173.22:03:39.49#ibcon#wrote, iclass 29, count 0 2006.173.22:03:39.49#ibcon#about to read 3, iclass 29, count 0 2006.173.22:03:39.51#ibcon#read 3, iclass 29, count 0 2006.173.22:03:39.51#ibcon#about to read 4, iclass 29, count 0 2006.173.22:03:39.51#ibcon#read 4, iclass 29, count 0 2006.173.22:03:39.51#ibcon#about to read 5, iclass 29, count 0 2006.173.22:03:39.51#ibcon#read 5, iclass 29, count 0 2006.173.22:03:39.51#ibcon#about to read 6, iclass 29, count 0 2006.173.22:03:39.51#ibcon#read 6, iclass 29, count 0 2006.173.22:03:39.51#ibcon#end of sib2, iclass 29, count 0 2006.173.22:03:39.51#ibcon#*mode == 0, iclass 29, count 0 2006.173.22:03:39.51#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.22:03:39.51#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.22:03:39.51#ibcon#*before write, iclass 29, count 0 2006.173.22:03:39.51#ibcon#enter sib2, iclass 29, count 0 2006.173.22:03:39.51#ibcon#flushed, iclass 29, count 0 2006.173.22:03:39.51#ibcon#about to write, iclass 29, count 0 2006.173.22:03:39.51#ibcon#wrote, iclass 29, count 0 2006.173.22:03:39.51#ibcon#about to read 3, iclass 29, count 0 2006.173.22:03:39.55#ibcon#read 3, iclass 29, count 0 2006.173.22:03:39.55#ibcon#about to read 4, iclass 29, count 0 2006.173.22:03:39.55#ibcon#read 4, iclass 29, count 0 2006.173.22:03:39.55#ibcon#about to read 5, iclass 29, count 0 2006.173.22:03:39.55#ibcon#read 5, iclass 29, count 0 2006.173.22:03:39.55#ibcon#about to read 6, iclass 29, count 0 2006.173.22:03:39.55#ibcon#read 6, iclass 29, count 0 2006.173.22:03:39.55#ibcon#end of sib2, iclass 29, count 0 2006.173.22:03:39.55#ibcon#*after write, iclass 29, count 0 2006.173.22:03:39.55#ibcon#*before return 0, iclass 29, count 0 2006.173.22:03:39.55#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.22:03:39.55#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.22:03:39.55#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.22:03:39.55#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.22:03:39.55$vck44/vb=6,4 2006.173.22:03:39.55#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.22:03:39.55#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.22:03:39.55#ibcon#ireg 11 cls_cnt 2 2006.173.22:03:39.55#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.22:03:39.61#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.22:03:39.61#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.22:03:39.61#ibcon#enter wrdev, iclass 31, count 2 2006.173.22:03:39.61#ibcon#first serial, iclass 31, count 2 2006.173.22:03:39.61#ibcon#enter sib2, iclass 31, count 2 2006.173.22:03:39.61#ibcon#flushed, iclass 31, count 2 2006.173.22:03:39.61#ibcon#about to write, iclass 31, count 2 2006.173.22:03:39.61#ibcon#wrote, iclass 31, count 2 2006.173.22:03:39.61#ibcon#about to read 3, iclass 31, count 2 2006.173.22:03:39.63#ibcon#read 3, iclass 31, count 2 2006.173.22:03:39.63#ibcon#about to read 4, iclass 31, count 2 2006.173.22:03:39.63#ibcon#read 4, iclass 31, count 2 2006.173.22:03:39.63#ibcon#about to read 5, iclass 31, count 2 2006.173.22:03:39.63#ibcon#read 5, iclass 31, count 2 2006.173.22:03:39.63#ibcon#about to read 6, iclass 31, count 2 2006.173.22:03:39.63#ibcon#read 6, iclass 31, count 2 2006.173.22:03:39.63#ibcon#end of sib2, iclass 31, count 2 2006.173.22:03:39.63#ibcon#*mode == 0, iclass 31, count 2 2006.173.22:03:39.63#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.22:03:39.63#ibcon#[27=AT06-04\r\n] 2006.173.22:03:39.63#ibcon#*before write, iclass 31, count 2 2006.173.22:03:39.63#ibcon#enter sib2, iclass 31, count 2 2006.173.22:03:39.63#ibcon#flushed, iclass 31, count 2 2006.173.22:03:39.63#ibcon#about to write, iclass 31, count 2 2006.173.22:03:39.63#ibcon#wrote, iclass 31, count 2 2006.173.22:03:39.63#ibcon#about to read 3, iclass 31, count 2 2006.173.22:03:39.66#ibcon#read 3, iclass 31, count 2 2006.173.22:03:39.66#ibcon#about to read 4, iclass 31, count 2 2006.173.22:03:39.66#ibcon#read 4, iclass 31, count 2 2006.173.22:03:39.66#ibcon#about to read 5, iclass 31, count 2 2006.173.22:03:39.66#ibcon#read 5, iclass 31, count 2 2006.173.22:03:39.66#ibcon#about to read 6, iclass 31, count 2 2006.173.22:03:39.66#ibcon#read 6, iclass 31, count 2 2006.173.22:03:39.66#ibcon#end of sib2, iclass 31, count 2 2006.173.22:03:39.66#ibcon#*after write, iclass 31, count 2 2006.173.22:03:39.66#ibcon#*before return 0, iclass 31, count 2 2006.173.22:03:39.66#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.22:03:39.66#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.22:03:39.66#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.22:03:39.66#ibcon#ireg 7 cls_cnt 0 2006.173.22:03:39.66#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.22:03:39.78#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.22:03:39.78#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.22:03:39.78#ibcon#enter wrdev, iclass 31, count 0 2006.173.22:03:39.78#ibcon#first serial, iclass 31, count 0 2006.173.22:03:39.78#ibcon#enter sib2, iclass 31, count 0 2006.173.22:03:39.78#ibcon#flushed, iclass 31, count 0 2006.173.22:03:39.78#ibcon#about to write, iclass 31, count 0 2006.173.22:03:39.78#ibcon#wrote, iclass 31, count 0 2006.173.22:03:39.78#ibcon#about to read 3, iclass 31, count 0 2006.173.22:03:39.80#ibcon#read 3, iclass 31, count 0 2006.173.22:03:39.80#ibcon#about to read 4, iclass 31, count 0 2006.173.22:03:39.80#ibcon#read 4, iclass 31, count 0 2006.173.22:03:39.80#ibcon#about to read 5, iclass 31, count 0 2006.173.22:03:39.80#ibcon#read 5, iclass 31, count 0 2006.173.22:03:39.80#ibcon#about to read 6, iclass 31, count 0 2006.173.22:03:39.80#ibcon#read 6, iclass 31, count 0 2006.173.22:03:39.80#ibcon#end of sib2, iclass 31, count 0 2006.173.22:03:39.80#ibcon#*mode == 0, iclass 31, count 0 2006.173.22:03:39.80#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.22:03:39.80#ibcon#[27=USB\r\n] 2006.173.22:03:39.80#ibcon#*before write, iclass 31, count 0 2006.173.22:03:39.80#ibcon#enter sib2, iclass 31, count 0 2006.173.22:03:39.80#ibcon#flushed, iclass 31, count 0 2006.173.22:03:39.80#ibcon#about to write, iclass 31, count 0 2006.173.22:03:39.80#ibcon#wrote, iclass 31, count 0 2006.173.22:03:39.80#ibcon#about to read 3, iclass 31, count 0 2006.173.22:03:39.83#ibcon#read 3, iclass 31, count 0 2006.173.22:03:39.83#ibcon#about to read 4, iclass 31, count 0 2006.173.22:03:39.83#ibcon#read 4, iclass 31, count 0 2006.173.22:03:39.83#ibcon#about to read 5, iclass 31, count 0 2006.173.22:03:39.83#ibcon#read 5, iclass 31, count 0 2006.173.22:03:39.83#ibcon#about to read 6, iclass 31, count 0 2006.173.22:03:39.83#ibcon#read 6, iclass 31, count 0 2006.173.22:03:39.83#ibcon#end of sib2, iclass 31, count 0 2006.173.22:03:39.83#ibcon#*after write, iclass 31, count 0 2006.173.22:03:39.83#ibcon#*before return 0, iclass 31, count 0 2006.173.22:03:39.83#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.22:03:39.83#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.22:03:39.83#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.22:03:39.83#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.22:03:39.83$vck44/vblo=7,734.99 2006.173.22:03:39.83#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.22:03:39.83#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.22:03:39.83#ibcon#ireg 17 cls_cnt 0 2006.173.22:03:39.83#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.22:03:39.83#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.22:03:39.83#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.22:03:39.83#ibcon#enter wrdev, iclass 33, count 0 2006.173.22:03:39.83#ibcon#first serial, iclass 33, count 0 2006.173.22:03:39.83#ibcon#enter sib2, iclass 33, count 0 2006.173.22:03:39.83#ibcon#flushed, iclass 33, count 0 2006.173.22:03:39.83#ibcon#about to write, iclass 33, count 0 2006.173.22:03:39.83#ibcon#wrote, iclass 33, count 0 2006.173.22:03:39.83#ibcon#about to read 3, iclass 33, count 0 2006.173.22:03:39.85#ibcon#read 3, iclass 33, count 0 2006.173.22:03:39.85#ibcon#about to read 4, iclass 33, count 0 2006.173.22:03:39.85#ibcon#read 4, iclass 33, count 0 2006.173.22:03:39.85#ibcon#about to read 5, iclass 33, count 0 2006.173.22:03:39.85#ibcon#read 5, iclass 33, count 0 2006.173.22:03:39.85#ibcon#about to read 6, iclass 33, count 0 2006.173.22:03:39.85#ibcon#read 6, iclass 33, count 0 2006.173.22:03:39.85#ibcon#end of sib2, iclass 33, count 0 2006.173.22:03:39.85#ibcon#*mode == 0, iclass 33, count 0 2006.173.22:03:39.85#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.22:03:39.85#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.22:03:39.85#ibcon#*before write, iclass 33, count 0 2006.173.22:03:39.85#ibcon#enter sib2, iclass 33, count 0 2006.173.22:03:39.85#ibcon#flushed, iclass 33, count 0 2006.173.22:03:39.85#ibcon#about to write, iclass 33, count 0 2006.173.22:03:39.85#ibcon#wrote, iclass 33, count 0 2006.173.22:03:39.85#ibcon#about to read 3, iclass 33, count 0 2006.173.22:03:39.89#ibcon#read 3, iclass 33, count 0 2006.173.22:03:39.89#ibcon#about to read 4, iclass 33, count 0 2006.173.22:03:39.89#ibcon#read 4, iclass 33, count 0 2006.173.22:03:39.89#ibcon#about to read 5, iclass 33, count 0 2006.173.22:03:39.89#ibcon#read 5, iclass 33, count 0 2006.173.22:03:39.89#ibcon#about to read 6, iclass 33, count 0 2006.173.22:03:39.89#ibcon#read 6, iclass 33, count 0 2006.173.22:03:39.89#ibcon#end of sib2, iclass 33, count 0 2006.173.22:03:39.89#ibcon#*after write, iclass 33, count 0 2006.173.22:03:39.89#ibcon#*before return 0, iclass 33, count 0 2006.173.22:03:39.89#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.22:03:39.89#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.22:03:39.89#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.22:03:39.89#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.22:03:39.89$vck44/vb=7,4 2006.173.22:03:39.89#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.22:03:39.89#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.22:03:39.89#ibcon#ireg 11 cls_cnt 2 2006.173.22:03:39.89#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.22:03:39.95#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.22:03:39.95#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.22:03:39.95#ibcon#enter wrdev, iclass 35, count 2 2006.173.22:03:39.95#ibcon#first serial, iclass 35, count 2 2006.173.22:03:39.95#ibcon#enter sib2, iclass 35, count 2 2006.173.22:03:39.95#ibcon#flushed, iclass 35, count 2 2006.173.22:03:39.95#ibcon#about to write, iclass 35, count 2 2006.173.22:03:39.95#ibcon#wrote, iclass 35, count 2 2006.173.22:03:39.95#ibcon#about to read 3, iclass 35, count 2 2006.173.22:03:39.97#ibcon#read 3, iclass 35, count 2 2006.173.22:03:39.97#ibcon#about to read 4, iclass 35, count 2 2006.173.22:03:39.97#ibcon#read 4, iclass 35, count 2 2006.173.22:03:39.97#ibcon#about to read 5, iclass 35, count 2 2006.173.22:03:39.97#ibcon#read 5, iclass 35, count 2 2006.173.22:03:39.97#ibcon#about to read 6, iclass 35, count 2 2006.173.22:03:39.97#ibcon#read 6, iclass 35, count 2 2006.173.22:03:39.97#ibcon#end of sib2, iclass 35, count 2 2006.173.22:03:39.97#ibcon#*mode == 0, iclass 35, count 2 2006.173.22:03:39.97#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.22:03:39.97#ibcon#[27=AT07-04\r\n] 2006.173.22:03:39.97#ibcon#*before write, iclass 35, count 2 2006.173.22:03:39.97#ibcon#enter sib2, iclass 35, count 2 2006.173.22:03:39.97#ibcon#flushed, iclass 35, count 2 2006.173.22:03:39.97#ibcon#about to write, iclass 35, count 2 2006.173.22:03:39.97#ibcon#wrote, iclass 35, count 2 2006.173.22:03:39.97#ibcon#about to read 3, iclass 35, count 2 2006.173.22:03:40.00#ibcon#read 3, iclass 35, count 2 2006.173.22:03:40.00#ibcon#about to read 4, iclass 35, count 2 2006.173.22:03:40.00#ibcon#read 4, iclass 35, count 2 2006.173.22:03:40.00#ibcon#about to read 5, iclass 35, count 2 2006.173.22:03:40.00#ibcon#read 5, iclass 35, count 2 2006.173.22:03:40.00#ibcon#about to read 6, iclass 35, count 2 2006.173.22:03:40.00#ibcon#read 6, iclass 35, count 2 2006.173.22:03:40.00#ibcon#end of sib2, iclass 35, count 2 2006.173.22:03:40.00#ibcon#*after write, iclass 35, count 2 2006.173.22:03:40.00#ibcon#*before return 0, iclass 35, count 2 2006.173.22:03:40.00#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.22:03:40.00#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.22:03:40.00#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.22:03:40.00#ibcon#ireg 7 cls_cnt 0 2006.173.22:03:40.00#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.22:03:40.12#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.22:03:40.12#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.22:03:40.12#ibcon#enter wrdev, iclass 35, count 0 2006.173.22:03:40.12#ibcon#first serial, iclass 35, count 0 2006.173.22:03:40.12#ibcon#enter sib2, iclass 35, count 0 2006.173.22:03:40.12#ibcon#flushed, iclass 35, count 0 2006.173.22:03:40.12#ibcon#about to write, iclass 35, count 0 2006.173.22:03:40.12#ibcon#wrote, iclass 35, count 0 2006.173.22:03:40.12#ibcon#about to read 3, iclass 35, count 0 2006.173.22:03:40.14#ibcon#read 3, iclass 35, count 0 2006.173.22:03:40.14#ibcon#about to read 4, iclass 35, count 0 2006.173.22:03:40.14#ibcon#read 4, iclass 35, count 0 2006.173.22:03:40.14#ibcon#about to read 5, iclass 35, count 0 2006.173.22:03:40.14#ibcon#read 5, iclass 35, count 0 2006.173.22:03:40.14#ibcon#about to read 6, iclass 35, count 0 2006.173.22:03:40.14#ibcon#read 6, iclass 35, count 0 2006.173.22:03:40.14#ibcon#end of sib2, iclass 35, count 0 2006.173.22:03:40.14#ibcon#*mode == 0, iclass 35, count 0 2006.173.22:03:40.14#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.22:03:40.14#ibcon#[27=USB\r\n] 2006.173.22:03:40.14#ibcon#*before write, iclass 35, count 0 2006.173.22:03:40.14#ibcon#enter sib2, iclass 35, count 0 2006.173.22:03:40.14#ibcon#flushed, iclass 35, count 0 2006.173.22:03:40.14#ibcon#about to write, iclass 35, count 0 2006.173.22:03:40.14#ibcon#wrote, iclass 35, count 0 2006.173.22:03:40.14#ibcon#about to read 3, iclass 35, count 0 2006.173.22:03:40.17#ibcon#read 3, iclass 35, count 0 2006.173.22:03:40.17#ibcon#about to read 4, iclass 35, count 0 2006.173.22:03:40.17#ibcon#read 4, iclass 35, count 0 2006.173.22:03:40.17#ibcon#about to read 5, iclass 35, count 0 2006.173.22:03:40.17#ibcon#read 5, iclass 35, count 0 2006.173.22:03:40.17#ibcon#about to read 6, iclass 35, count 0 2006.173.22:03:40.17#ibcon#read 6, iclass 35, count 0 2006.173.22:03:40.17#ibcon#end of sib2, iclass 35, count 0 2006.173.22:03:40.17#ibcon#*after write, iclass 35, count 0 2006.173.22:03:40.17#ibcon#*before return 0, iclass 35, count 0 2006.173.22:03:40.17#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.22:03:40.17#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.22:03:40.17#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.22:03:40.17#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.22:03:40.17$vck44/vblo=8,744.99 2006.173.22:03:40.17#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.22:03:40.17#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.22:03:40.17#ibcon#ireg 17 cls_cnt 0 2006.173.22:03:40.17#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.22:03:40.17#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.22:03:40.17#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.22:03:40.17#ibcon#enter wrdev, iclass 37, count 0 2006.173.22:03:40.17#ibcon#first serial, iclass 37, count 0 2006.173.22:03:40.17#ibcon#enter sib2, iclass 37, count 0 2006.173.22:03:40.17#ibcon#flushed, iclass 37, count 0 2006.173.22:03:40.17#ibcon#about to write, iclass 37, count 0 2006.173.22:03:40.17#ibcon#wrote, iclass 37, count 0 2006.173.22:03:40.17#ibcon#about to read 3, iclass 37, count 0 2006.173.22:03:40.19#ibcon#read 3, iclass 37, count 0 2006.173.22:03:40.19#ibcon#about to read 4, iclass 37, count 0 2006.173.22:03:40.19#ibcon#read 4, iclass 37, count 0 2006.173.22:03:40.19#ibcon#about to read 5, iclass 37, count 0 2006.173.22:03:40.19#ibcon#read 5, iclass 37, count 0 2006.173.22:03:40.19#ibcon#about to read 6, iclass 37, count 0 2006.173.22:03:40.19#ibcon#read 6, iclass 37, count 0 2006.173.22:03:40.19#ibcon#end of sib2, iclass 37, count 0 2006.173.22:03:40.19#ibcon#*mode == 0, iclass 37, count 0 2006.173.22:03:40.19#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.22:03:40.19#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.22:03:40.19#ibcon#*before write, iclass 37, count 0 2006.173.22:03:40.19#ibcon#enter sib2, iclass 37, count 0 2006.173.22:03:40.19#ibcon#flushed, iclass 37, count 0 2006.173.22:03:40.19#ibcon#about to write, iclass 37, count 0 2006.173.22:03:40.19#ibcon#wrote, iclass 37, count 0 2006.173.22:03:40.19#ibcon#about to read 3, iclass 37, count 0 2006.173.22:03:40.23#ibcon#read 3, iclass 37, count 0 2006.173.22:03:40.23#ibcon#about to read 4, iclass 37, count 0 2006.173.22:03:40.23#ibcon#read 4, iclass 37, count 0 2006.173.22:03:40.23#ibcon#about to read 5, iclass 37, count 0 2006.173.22:03:40.23#ibcon#read 5, iclass 37, count 0 2006.173.22:03:40.23#ibcon#about to read 6, iclass 37, count 0 2006.173.22:03:40.23#ibcon#read 6, iclass 37, count 0 2006.173.22:03:40.23#ibcon#end of sib2, iclass 37, count 0 2006.173.22:03:40.23#ibcon#*after write, iclass 37, count 0 2006.173.22:03:40.23#ibcon#*before return 0, iclass 37, count 0 2006.173.22:03:40.23#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.22:03:40.23#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.22:03:40.23#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.22:03:40.23#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.22:03:40.23$vck44/vb=8,4 2006.173.22:03:40.23#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.22:03:40.23#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.22:03:40.23#ibcon#ireg 11 cls_cnt 2 2006.173.22:03:40.23#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.22:03:40.29#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.22:03:40.29#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.22:03:40.29#ibcon#enter wrdev, iclass 39, count 2 2006.173.22:03:40.29#ibcon#first serial, iclass 39, count 2 2006.173.22:03:40.29#ibcon#enter sib2, iclass 39, count 2 2006.173.22:03:40.29#ibcon#flushed, iclass 39, count 2 2006.173.22:03:40.29#ibcon#about to write, iclass 39, count 2 2006.173.22:03:40.29#ibcon#wrote, iclass 39, count 2 2006.173.22:03:40.29#ibcon#about to read 3, iclass 39, count 2 2006.173.22:03:40.31#ibcon#read 3, iclass 39, count 2 2006.173.22:03:40.31#ibcon#about to read 4, iclass 39, count 2 2006.173.22:03:40.31#ibcon#read 4, iclass 39, count 2 2006.173.22:03:40.31#ibcon#about to read 5, iclass 39, count 2 2006.173.22:03:40.31#ibcon#read 5, iclass 39, count 2 2006.173.22:03:40.31#ibcon#about to read 6, iclass 39, count 2 2006.173.22:03:40.31#ibcon#read 6, iclass 39, count 2 2006.173.22:03:40.31#ibcon#end of sib2, iclass 39, count 2 2006.173.22:03:40.31#ibcon#*mode == 0, iclass 39, count 2 2006.173.22:03:40.31#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.22:03:40.31#ibcon#[27=AT08-04\r\n] 2006.173.22:03:40.31#ibcon#*before write, iclass 39, count 2 2006.173.22:03:40.31#ibcon#enter sib2, iclass 39, count 2 2006.173.22:03:40.31#ibcon#flushed, iclass 39, count 2 2006.173.22:03:40.31#ibcon#about to write, iclass 39, count 2 2006.173.22:03:40.31#ibcon#wrote, iclass 39, count 2 2006.173.22:03:40.31#ibcon#about to read 3, iclass 39, count 2 2006.173.22:03:40.34#ibcon#read 3, iclass 39, count 2 2006.173.22:03:40.34#ibcon#about to read 4, iclass 39, count 2 2006.173.22:03:40.34#ibcon#read 4, iclass 39, count 2 2006.173.22:03:40.34#ibcon#about to read 5, iclass 39, count 2 2006.173.22:03:40.34#ibcon#read 5, iclass 39, count 2 2006.173.22:03:40.34#ibcon#about to read 6, iclass 39, count 2 2006.173.22:03:40.34#ibcon#read 6, iclass 39, count 2 2006.173.22:03:40.34#ibcon#end of sib2, iclass 39, count 2 2006.173.22:03:40.34#ibcon#*after write, iclass 39, count 2 2006.173.22:03:40.34#ibcon#*before return 0, iclass 39, count 2 2006.173.22:03:40.34#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.22:03:40.34#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.22:03:40.34#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.22:03:40.34#ibcon#ireg 7 cls_cnt 0 2006.173.22:03:40.34#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.22:03:40.46#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.22:03:40.46#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.22:03:40.46#ibcon#enter wrdev, iclass 39, count 0 2006.173.22:03:40.46#ibcon#first serial, iclass 39, count 0 2006.173.22:03:40.46#ibcon#enter sib2, iclass 39, count 0 2006.173.22:03:40.46#ibcon#flushed, iclass 39, count 0 2006.173.22:03:40.46#ibcon#about to write, iclass 39, count 0 2006.173.22:03:40.46#ibcon#wrote, iclass 39, count 0 2006.173.22:03:40.46#ibcon#about to read 3, iclass 39, count 0 2006.173.22:03:40.48#ibcon#read 3, iclass 39, count 0 2006.173.22:03:40.48#ibcon#about to read 4, iclass 39, count 0 2006.173.22:03:40.48#ibcon#read 4, iclass 39, count 0 2006.173.22:03:40.48#ibcon#about to read 5, iclass 39, count 0 2006.173.22:03:40.48#ibcon#read 5, iclass 39, count 0 2006.173.22:03:40.48#ibcon#about to read 6, iclass 39, count 0 2006.173.22:03:40.48#ibcon#read 6, iclass 39, count 0 2006.173.22:03:40.48#ibcon#end of sib2, iclass 39, count 0 2006.173.22:03:40.48#ibcon#*mode == 0, iclass 39, count 0 2006.173.22:03:40.48#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.22:03:40.48#ibcon#[27=USB\r\n] 2006.173.22:03:40.48#ibcon#*before write, iclass 39, count 0 2006.173.22:03:40.48#ibcon#enter sib2, iclass 39, count 0 2006.173.22:03:40.48#ibcon#flushed, iclass 39, count 0 2006.173.22:03:40.48#ibcon#about to write, iclass 39, count 0 2006.173.22:03:40.48#ibcon#wrote, iclass 39, count 0 2006.173.22:03:40.48#ibcon#about to read 3, iclass 39, count 0 2006.173.22:03:40.51#ibcon#read 3, iclass 39, count 0 2006.173.22:03:40.51#ibcon#about to read 4, iclass 39, count 0 2006.173.22:03:40.51#ibcon#read 4, iclass 39, count 0 2006.173.22:03:40.51#ibcon#about to read 5, iclass 39, count 0 2006.173.22:03:40.51#ibcon#read 5, iclass 39, count 0 2006.173.22:03:40.51#ibcon#about to read 6, iclass 39, count 0 2006.173.22:03:40.51#ibcon#read 6, iclass 39, count 0 2006.173.22:03:40.51#ibcon#end of sib2, iclass 39, count 0 2006.173.22:03:40.51#ibcon#*after write, iclass 39, count 0 2006.173.22:03:40.51#ibcon#*before return 0, iclass 39, count 0 2006.173.22:03:40.51#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.22:03:40.51#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.22:03:40.51#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.22:03:40.51#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.22:03:40.51$vck44/vabw=wide 2006.173.22:03:40.51#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.22:03:40.51#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.22:03:40.51#ibcon#ireg 8 cls_cnt 0 2006.173.22:03:40.51#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.22:03:40.51#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.22:03:40.51#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.22:03:40.51#ibcon#enter wrdev, iclass 3, count 0 2006.173.22:03:40.51#ibcon#first serial, iclass 3, count 0 2006.173.22:03:40.51#ibcon#enter sib2, iclass 3, count 0 2006.173.22:03:40.51#ibcon#flushed, iclass 3, count 0 2006.173.22:03:40.51#ibcon#about to write, iclass 3, count 0 2006.173.22:03:40.51#ibcon#wrote, iclass 3, count 0 2006.173.22:03:40.51#ibcon#about to read 3, iclass 3, count 0 2006.173.22:03:40.53#ibcon#read 3, iclass 3, count 0 2006.173.22:03:40.53#ibcon#about to read 4, iclass 3, count 0 2006.173.22:03:40.53#ibcon#read 4, iclass 3, count 0 2006.173.22:03:40.53#ibcon#about to read 5, iclass 3, count 0 2006.173.22:03:40.53#ibcon#read 5, iclass 3, count 0 2006.173.22:03:40.53#ibcon#about to read 6, iclass 3, count 0 2006.173.22:03:40.53#ibcon#read 6, iclass 3, count 0 2006.173.22:03:40.53#ibcon#end of sib2, iclass 3, count 0 2006.173.22:03:40.53#ibcon#*mode == 0, iclass 3, count 0 2006.173.22:03:40.53#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.22:03:40.53#ibcon#[25=BW32\r\n] 2006.173.22:03:40.53#ibcon#*before write, iclass 3, count 0 2006.173.22:03:40.53#ibcon#enter sib2, iclass 3, count 0 2006.173.22:03:40.53#ibcon#flushed, iclass 3, count 0 2006.173.22:03:40.53#ibcon#about to write, iclass 3, count 0 2006.173.22:03:40.53#ibcon#wrote, iclass 3, count 0 2006.173.22:03:40.53#ibcon#about to read 3, iclass 3, count 0 2006.173.22:03:40.56#ibcon#read 3, iclass 3, count 0 2006.173.22:03:40.56#ibcon#about to read 4, iclass 3, count 0 2006.173.22:03:40.56#ibcon#read 4, iclass 3, count 0 2006.173.22:03:40.56#ibcon#about to read 5, iclass 3, count 0 2006.173.22:03:40.56#ibcon#read 5, iclass 3, count 0 2006.173.22:03:40.56#ibcon#about to read 6, iclass 3, count 0 2006.173.22:03:40.56#ibcon#read 6, iclass 3, count 0 2006.173.22:03:40.56#ibcon#end of sib2, iclass 3, count 0 2006.173.22:03:40.56#ibcon#*after write, iclass 3, count 0 2006.173.22:03:40.56#ibcon#*before return 0, iclass 3, count 0 2006.173.22:03:40.56#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.22:03:40.56#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.22:03:40.56#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.22:03:40.56#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.22:03:40.56$vck44/vbbw=wide 2006.173.22:03:40.56#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.22:03:40.56#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.22:03:40.56#ibcon#ireg 8 cls_cnt 0 2006.173.22:03:40.56#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.22:03:40.63#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.22:03:40.63#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.22:03:40.63#ibcon#enter wrdev, iclass 5, count 0 2006.173.22:03:40.63#ibcon#first serial, iclass 5, count 0 2006.173.22:03:40.63#ibcon#enter sib2, iclass 5, count 0 2006.173.22:03:40.63#ibcon#flushed, iclass 5, count 0 2006.173.22:03:40.63#ibcon#about to write, iclass 5, count 0 2006.173.22:03:40.63#ibcon#wrote, iclass 5, count 0 2006.173.22:03:40.63#ibcon#about to read 3, iclass 5, count 0 2006.173.22:03:40.65#ibcon#read 3, iclass 5, count 0 2006.173.22:03:40.65#ibcon#about to read 4, iclass 5, count 0 2006.173.22:03:40.65#ibcon#read 4, iclass 5, count 0 2006.173.22:03:40.65#ibcon#about to read 5, iclass 5, count 0 2006.173.22:03:40.65#ibcon#read 5, iclass 5, count 0 2006.173.22:03:40.65#ibcon#about to read 6, iclass 5, count 0 2006.173.22:03:40.65#ibcon#read 6, iclass 5, count 0 2006.173.22:03:40.65#ibcon#end of sib2, iclass 5, count 0 2006.173.22:03:40.65#ibcon#*mode == 0, iclass 5, count 0 2006.173.22:03:40.65#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.22:03:40.65#ibcon#[27=BW32\r\n] 2006.173.22:03:40.65#ibcon#*before write, iclass 5, count 0 2006.173.22:03:40.65#ibcon#enter sib2, iclass 5, count 0 2006.173.22:03:40.65#ibcon#flushed, iclass 5, count 0 2006.173.22:03:40.65#ibcon#about to write, iclass 5, count 0 2006.173.22:03:40.65#ibcon#wrote, iclass 5, count 0 2006.173.22:03:40.65#ibcon#about to read 3, iclass 5, count 0 2006.173.22:03:40.68#ibcon#read 3, iclass 5, count 0 2006.173.22:03:40.68#ibcon#about to read 4, iclass 5, count 0 2006.173.22:03:40.68#ibcon#read 4, iclass 5, count 0 2006.173.22:03:40.68#ibcon#about to read 5, iclass 5, count 0 2006.173.22:03:40.68#ibcon#read 5, iclass 5, count 0 2006.173.22:03:40.68#ibcon#about to read 6, iclass 5, count 0 2006.173.22:03:40.68#ibcon#read 6, iclass 5, count 0 2006.173.22:03:40.68#ibcon#end of sib2, iclass 5, count 0 2006.173.22:03:40.68#ibcon#*after write, iclass 5, count 0 2006.173.22:03:40.68#ibcon#*before return 0, iclass 5, count 0 2006.173.22:03:40.68#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.22:03:40.68#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.22:03:40.68#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.22:03:40.68#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.22:03:40.68$setupk4/ifdk4 2006.173.22:03:40.68$ifdk4/lo= 2006.173.22:03:40.68$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.22:03:40.68$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.22:03:40.68$ifdk4/patch= 2006.173.22:03:40.68$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.22:03:40.68$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.22:03:40.68$setupk4/!*+20s 2006.173.22:03:43.22#abcon#<5=/12 0.5 1.3 21.78 961003.4\r\n> 2006.173.22:03:43.24#abcon#{5=INTERFACE CLEAR} 2006.173.22:03:43.30#abcon#[5=S1D000X0/0*\r\n] 2006.173.22:03:47.14#trakl#Source acquired 2006.173.22:03:49.14#flagr#flagr/antenna,acquired 2006.173.22:03:53.39#abcon#<5=/12 0.5 1.3 21.78 961003.4\r\n> 2006.173.22:03:53.41#abcon#{5=INTERFACE CLEAR} 2006.173.22:03:53.47#abcon#[5=S1D000X0/0*\r\n] 2006.173.22:03:55.19$setupk4/"tpicd 2006.173.22:03:55.19$setupk4/echo=off 2006.173.22:03:55.19$setupk4/xlog=off 2006.173.22:03:55.19:!2006.173.22:09:10 2006.173.22:09:10.00:preob 2006.173.22:09:11.13/onsource/TRACKING 2006.173.22:09:11.13:!2006.173.22:09:20 2006.173.22:09:20.00:"tape 2006.173.22:09:20.00:"st=record 2006.173.22:09:20.00:data_valid=on 2006.173.22:09:20.00:midob 2006.173.22:09:20.13/onsource/TRACKING 2006.173.22:09:20.13/wx/21.79,1003.4,97 2006.173.22:09:20.33/cable/+6.5153E-03 2006.173.22:09:21.42/va/01,07,usb,yes,35,38 2006.173.22:09:21.42/va/02,06,usb,yes,35,36 2006.173.22:09:21.42/va/03,05,usb,yes,44,46 2006.173.22:09:21.42/va/04,06,usb,yes,36,37 2006.173.22:09:21.42/va/05,04,usb,yes,28,28 2006.173.22:09:21.42/va/06,03,usb,yes,39,39 2006.173.22:09:21.42/va/07,04,usb,yes,32,33 2006.173.22:09:21.42/va/08,04,usb,yes,27,32 2006.173.22:09:21.65/valo/01,524.99,yes,locked 2006.173.22:09:21.65/valo/02,534.99,yes,locked 2006.173.22:09:21.65/valo/03,564.99,yes,locked 2006.173.22:09:21.65/valo/04,624.99,yes,locked 2006.173.22:09:21.65/valo/05,734.99,yes,locked 2006.173.22:09:21.65/valo/06,814.99,yes,locked 2006.173.22:09:21.65/valo/07,864.99,yes,locked 2006.173.22:09:21.65/valo/08,884.99,yes,locked 2006.173.22:09:22.74/vb/01,04,usb,yes,29,27 2006.173.22:09:22.74/vb/02,04,usb,yes,31,31 2006.173.22:09:22.74/vb/03,04,usb,yes,28,31 2006.173.22:09:22.74/vb/04,04,usb,yes,33,32 2006.173.22:09:22.74/vb/05,04,usb,yes,25,28 2006.173.22:09:22.74/vb/06,04,usb,yes,30,26 2006.173.22:09:22.74/vb/07,04,usb,yes,30,29 2006.173.22:09:22.74/vb/08,04,usb,yes,27,30 2006.173.22:09:22.97/vblo/01,629.99,yes,locked 2006.173.22:09:22.97/vblo/02,634.99,yes,locked 2006.173.22:09:22.97/vblo/03,649.99,yes,locked 2006.173.22:09:22.97/vblo/04,679.99,yes,locked 2006.173.22:09:22.97/vblo/05,709.99,yes,locked 2006.173.22:09:22.97/vblo/06,719.99,yes,locked 2006.173.22:09:22.97/vblo/07,734.99,yes,locked 2006.173.22:09:22.97/vblo/08,744.99,yes,locked 2006.173.22:09:23.12/vabw/8 2006.173.22:09:23.27/vbbw/8 2006.173.22:09:23.36/xfe/off,on,14.5 2006.173.22:09:23.73/ifatt/23,28,28,28 2006.173.22:09:24.07/fmout-gps/S +3.86E-07 2006.173.22:09:24.11:!2006.173.22:10:40 2006.173.22:10:40.00:data_valid=off 2006.173.22:10:40.00:"et 2006.173.22:10:40.00:!+3s 2006.173.22:10:43.01:"tape 2006.173.22:10:43.01:postob 2006.173.22:10:43.14/cable/+6.5148E-03 2006.173.22:10:43.14/wx/21.80,1003.4,96 2006.173.22:10:44.07/fmout-gps/S +3.85E-07 2006.173.22:10:44.07:scan_name=173-2214,jd0606,80 2006.173.22:10:44.07:source=2121+053,212344.52,053522.1,2000.0,ccw 2006.173.22:10:45.14#flagr#flagr/antenna,new-source 2006.173.22:10:45.14:checkk5 2006.173.22:10:45.50/chk_autoobs//k5ts1/ autoobs is running! 2006.173.22:10:45.89/chk_autoobs//k5ts2/ autoobs is running! 2006.173.22:10:46.29/chk_autoobs//k5ts3/ autoobs is running! 2006.173.22:10:46.70/chk_autoobs//k5ts4/ autoobs is running! 2006.173.22:10:47.09/chk_obsdata//k5ts1/T1732209??a.dat file size is correct (nominal:320MB, actual:316MB). 2006.173.22:10:47.49/chk_obsdata//k5ts2/T1732209??b.dat file size is correct (nominal:320MB, actual:316MB). 2006.173.22:10:47.89/chk_obsdata//k5ts3/T1732209??c.dat file size is correct (nominal:320MB, actual:316MB). 2006.173.22:10:48.32/chk_obsdata//k5ts4/T1732209??d.dat file size is correct (nominal:320MB, actual:316MB). 2006.173.22:10:49.03/k5log//k5ts1_log_newline 2006.173.22:10:49.73/k5log//k5ts2_log_newline 2006.173.22:10:50.44/k5log//k5ts3_log_newline 2006.173.22:10:51.14/k5log//k5ts4_log_newline 2006.173.22:10:51.17/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.22:10:51.17:setupk4=1 2006.173.22:10:51.17$setupk4/echo=on 2006.173.22:10:51.17$setupk4/pcalon 2006.173.22:10:51.17$pcalon/"no phase cal control is implemented here 2006.173.22:10:51.17$setupk4/"tpicd=stop 2006.173.22:10:51.17$setupk4/"rec=synch_on 2006.173.22:10:51.17$setupk4/"rec_mode=128 2006.173.22:10:51.17$setupk4/!* 2006.173.22:10:51.17$setupk4/recpk4 2006.173.22:10:51.17$recpk4/recpatch= 2006.173.22:10:51.17$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.22:10:51.17$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.22:10:51.17$setupk4/vck44 2006.173.22:10:51.17$vck44/valo=1,524.99 2006.173.22:10:51.17#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.22:10:51.17#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.22:10:51.17#ibcon#ireg 17 cls_cnt 0 2006.173.22:10:51.17#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.22:10:51.17#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.22:10:51.17#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.22:10:51.17#ibcon#enter wrdev, iclass 40, count 0 2006.173.22:10:51.17#ibcon#first serial, iclass 40, count 0 2006.173.22:10:51.17#ibcon#enter sib2, iclass 40, count 0 2006.173.22:10:51.17#ibcon#flushed, iclass 40, count 0 2006.173.22:10:51.17#ibcon#about to write, iclass 40, count 0 2006.173.22:10:51.17#ibcon#wrote, iclass 40, count 0 2006.173.22:10:51.17#ibcon#about to read 3, iclass 40, count 0 2006.173.22:10:51.19#ibcon#read 3, iclass 40, count 0 2006.173.22:10:51.19#ibcon#about to read 4, iclass 40, count 0 2006.173.22:10:51.19#ibcon#read 4, iclass 40, count 0 2006.173.22:10:51.19#ibcon#about to read 5, iclass 40, count 0 2006.173.22:10:51.19#ibcon#read 5, iclass 40, count 0 2006.173.22:10:51.19#ibcon#about to read 6, iclass 40, count 0 2006.173.22:10:51.19#ibcon#read 6, iclass 40, count 0 2006.173.22:10:51.19#ibcon#end of sib2, iclass 40, count 0 2006.173.22:10:51.19#ibcon#*mode == 0, iclass 40, count 0 2006.173.22:10:51.19#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.22:10:51.19#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.22:10:51.19#ibcon#*before write, iclass 40, count 0 2006.173.22:10:51.19#ibcon#enter sib2, iclass 40, count 0 2006.173.22:10:51.19#ibcon#flushed, iclass 40, count 0 2006.173.22:10:51.19#ibcon#about to write, iclass 40, count 0 2006.173.22:10:51.19#ibcon#wrote, iclass 40, count 0 2006.173.22:10:51.19#ibcon#about to read 3, iclass 40, count 0 2006.173.22:10:51.24#ibcon#read 3, iclass 40, count 0 2006.173.22:10:51.24#ibcon#about to read 4, iclass 40, count 0 2006.173.22:10:51.24#ibcon#read 4, iclass 40, count 0 2006.173.22:10:51.24#ibcon#about to read 5, iclass 40, count 0 2006.173.22:10:51.24#ibcon#read 5, iclass 40, count 0 2006.173.22:10:51.24#ibcon#about to read 6, iclass 40, count 0 2006.173.22:10:51.24#ibcon#read 6, iclass 40, count 0 2006.173.22:10:51.24#ibcon#end of sib2, iclass 40, count 0 2006.173.22:10:51.24#ibcon#*after write, iclass 40, count 0 2006.173.22:10:51.24#ibcon#*before return 0, iclass 40, count 0 2006.173.22:10:51.24#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.22:10:51.24#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.22:10:51.24#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.22:10:51.24#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.22:10:51.24$vck44/va=1,7 2006.173.22:10:51.24#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.22:10:51.24#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.22:10:51.24#ibcon#ireg 11 cls_cnt 2 2006.173.22:10:51.24#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.22:10:51.24#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.22:10:51.24#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.22:10:51.24#ibcon#enter wrdev, iclass 4, count 2 2006.173.22:10:51.24#ibcon#first serial, iclass 4, count 2 2006.173.22:10:51.24#ibcon#enter sib2, iclass 4, count 2 2006.173.22:10:51.24#ibcon#flushed, iclass 4, count 2 2006.173.22:10:51.24#ibcon#about to write, iclass 4, count 2 2006.173.22:10:51.24#ibcon#wrote, iclass 4, count 2 2006.173.22:10:51.24#ibcon#about to read 3, iclass 4, count 2 2006.173.22:10:51.26#ibcon#read 3, iclass 4, count 2 2006.173.22:10:51.26#ibcon#about to read 4, iclass 4, count 2 2006.173.22:10:51.26#ibcon#read 4, iclass 4, count 2 2006.173.22:10:51.26#ibcon#about to read 5, iclass 4, count 2 2006.173.22:10:51.26#ibcon#read 5, iclass 4, count 2 2006.173.22:10:51.26#ibcon#about to read 6, iclass 4, count 2 2006.173.22:10:51.26#ibcon#read 6, iclass 4, count 2 2006.173.22:10:51.26#ibcon#end of sib2, iclass 4, count 2 2006.173.22:10:51.26#ibcon#*mode == 0, iclass 4, count 2 2006.173.22:10:51.26#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.22:10:51.26#ibcon#[25=AT01-07\r\n] 2006.173.22:10:51.26#ibcon#*before write, iclass 4, count 2 2006.173.22:10:51.26#ibcon#enter sib2, iclass 4, count 2 2006.173.22:10:51.26#ibcon#flushed, iclass 4, count 2 2006.173.22:10:51.26#ibcon#about to write, iclass 4, count 2 2006.173.22:10:51.26#ibcon#wrote, iclass 4, count 2 2006.173.22:10:51.26#ibcon#about to read 3, iclass 4, count 2 2006.173.22:10:51.29#ibcon#read 3, iclass 4, count 2 2006.173.22:10:51.29#ibcon#about to read 4, iclass 4, count 2 2006.173.22:10:51.29#ibcon#read 4, iclass 4, count 2 2006.173.22:10:51.29#ibcon#about to read 5, iclass 4, count 2 2006.173.22:10:51.29#ibcon#read 5, iclass 4, count 2 2006.173.22:10:51.29#ibcon#about to read 6, iclass 4, count 2 2006.173.22:10:51.29#ibcon#read 6, iclass 4, count 2 2006.173.22:10:51.29#ibcon#end of sib2, iclass 4, count 2 2006.173.22:10:51.29#ibcon#*after write, iclass 4, count 2 2006.173.22:10:51.29#ibcon#*before return 0, iclass 4, count 2 2006.173.22:10:51.29#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.22:10:51.29#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.22:10:51.29#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.22:10:51.29#ibcon#ireg 7 cls_cnt 0 2006.173.22:10:51.29#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.22:10:51.41#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.22:10:51.41#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.22:10:51.41#ibcon#enter wrdev, iclass 4, count 0 2006.173.22:10:51.41#ibcon#first serial, iclass 4, count 0 2006.173.22:10:51.41#ibcon#enter sib2, iclass 4, count 0 2006.173.22:10:51.41#ibcon#flushed, iclass 4, count 0 2006.173.22:10:51.41#ibcon#about to write, iclass 4, count 0 2006.173.22:10:51.41#ibcon#wrote, iclass 4, count 0 2006.173.22:10:51.41#ibcon#about to read 3, iclass 4, count 0 2006.173.22:10:51.43#ibcon#read 3, iclass 4, count 0 2006.173.22:10:51.43#ibcon#about to read 4, iclass 4, count 0 2006.173.22:10:51.43#ibcon#read 4, iclass 4, count 0 2006.173.22:10:51.43#ibcon#about to read 5, iclass 4, count 0 2006.173.22:10:51.43#ibcon#read 5, iclass 4, count 0 2006.173.22:10:51.43#ibcon#about to read 6, iclass 4, count 0 2006.173.22:10:51.43#ibcon#read 6, iclass 4, count 0 2006.173.22:10:51.43#ibcon#end of sib2, iclass 4, count 0 2006.173.22:10:51.43#ibcon#*mode == 0, iclass 4, count 0 2006.173.22:10:51.43#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.22:10:51.43#ibcon#[25=USB\r\n] 2006.173.22:10:51.43#ibcon#*before write, iclass 4, count 0 2006.173.22:10:51.43#ibcon#enter sib2, iclass 4, count 0 2006.173.22:10:51.43#ibcon#flushed, iclass 4, count 0 2006.173.22:10:51.43#ibcon#about to write, iclass 4, count 0 2006.173.22:10:51.43#ibcon#wrote, iclass 4, count 0 2006.173.22:10:51.43#ibcon#about to read 3, iclass 4, count 0 2006.173.22:10:51.46#ibcon#read 3, iclass 4, count 0 2006.173.22:10:51.46#ibcon#about to read 4, iclass 4, count 0 2006.173.22:10:51.46#ibcon#read 4, iclass 4, count 0 2006.173.22:10:51.46#ibcon#about to read 5, iclass 4, count 0 2006.173.22:10:51.46#ibcon#read 5, iclass 4, count 0 2006.173.22:10:51.46#ibcon#about to read 6, iclass 4, count 0 2006.173.22:10:51.46#ibcon#read 6, iclass 4, count 0 2006.173.22:10:51.46#ibcon#end of sib2, iclass 4, count 0 2006.173.22:10:51.46#ibcon#*after write, iclass 4, count 0 2006.173.22:10:51.46#ibcon#*before return 0, iclass 4, count 0 2006.173.22:10:51.46#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.22:10:51.46#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.22:10:51.46#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.22:10:51.46#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.22:10:51.46$vck44/valo=2,534.99 2006.173.22:10:51.46#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.22:10:51.46#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.22:10:51.46#ibcon#ireg 17 cls_cnt 0 2006.173.22:10:51.46#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.22:10:51.46#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.22:10:51.46#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.22:10:51.46#ibcon#enter wrdev, iclass 6, count 0 2006.173.22:10:51.46#ibcon#first serial, iclass 6, count 0 2006.173.22:10:51.46#ibcon#enter sib2, iclass 6, count 0 2006.173.22:10:51.46#ibcon#flushed, iclass 6, count 0 2006.173.22:10:51.46#ibcon#about to write, iclass 6, count 0 2006.173.22:10:51.46#ibcon#wrote, iclass 6, count 0 2006.173.22:10:51.46#ibcon#about to read 3, iclass 6, count 0 2006.173.22:10:51.48#ibcon#read 3, iclass 6, count 0 2006.173.22:10:51.48#ibcon#about to read 4, iclass 6, count 0 2006.173.22:10:51.48#ibcon#read 4, iclass 6, count 0 2006.173.22:10:51.48#ibcon#about to read 5, iclass 6, count 0 2006.173.22:10:51.48#ibcon#read 5, iclass 6, count 0 2006.173.22:10:51.48#ibcon#about to read 6, iclass 6, count 0 2006.173.22:10:51.48#ibcon#read 6, iclass 6, count 0 2006.173.22:10:51.48#ibcon#end of sib2, iclass 6, count 0 2006.173.22:10:51.48#ibcon#*mode == 0, iclass 6, count 0 2006.173.22:10:51.48#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.22:10:51.48#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.22:10:51.48#ibcon#*before write, iclass 6, count 0 2006.173.22:10:51.48#ibcon#enter sib2, iclass 6, count 0 2006.173.22:10:51.48#ibcon#flushed, iclass 6, count 0 2006.173.22:10:51.48#ibcon#about to write, iclass 6, count 0 2006.173.22:10:51.48#ibcon#wrote, iclass 6, count 0 2006.173.22:10:51.48#ibcon#about to read 3, iclass 6, count 0 2006.173.22:10:51.52#ibcon#read 3, iclass 6, count 0 2006.173.22:10:51.52#ibcon#about to read 4, iclass 6, count 0 2006.173.22:10:51.52#ibcon#read 4, iclass 6, count 0 2006.173.22:10:51.52#ibcon#about to read 5, iclass 6, count 0 2006.173.22:10:51.52#ibcon#read 5, iclass 6, count 0 2006.173.22:10:51.52#ibcon#about to read 6, iclass 6, count 0 2006.173.22:10:51.52#ibcon#read 6, iclass 6, count 0 2006.173.22:10:51.52#ibcon#end of sib2, iclass 6, count 0 2006.173.22:10:51.52#ibcon#*after write, iclass 6, count 0 2006.173.22:10:51.52#ibcon#*before return 0, iclass 6, count 0 2006.173.22:10:51.52#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.22:10:51.52#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.22:10:51.52#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.22:10:51.52#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.22:10:51.52$vck44/va=2,6 2006.173.22:10:51.52#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.22:10:51.52#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.22:10:51.52#ibcon#ireg 11 cls_cnt 2 2006.173.22:10:51.52#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.22:10:51.58#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.22:10:51.58#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.22:10:51.58#ibcon#enter wrdev, iclass 10, count 2 2006.173.22:10:51.58#ibcon#first serial, iclass 10, count 2 2006.173.22:10:51.58#ibcon#enter sib2, iclass 10, count 2 2006.173.22:10:51.58#ibcon#flushed, iclass 10, count 2 2006.173.22:10:51.58#ibcon#about to write, iclass 10, count 2 2006.173.22:10:51.58#ibcon#wrote, iclass 10, count 2 2006.173.22:10:51.58#ibcon#about to read 3, iclass 10, count 2 2006.173.22:10:51.60#ibcon#read 3, iclass 10, count 2 2006.173.22:10:51.60#ibcon#about to read 4, iclass 10, count 2 2006.173.22:10:51.60#ibcon#read 4, iclass 10, count 2 2006.173.22:10:51.60#ibcon#about to read 5, iclass 10, count 2 2006.173.22:10:51.60#ibcon#read 5, iclass 10, count 2 2006.173.22:10:51.60#ibcon#about to read 6, iclass 10, count 2 2006.173.22:10:51.60#ibcon#read 6, iclass 10, count 2 2006.173.22:10:51.60#ibcon#end of sib2, iclass 10, count 2 2006.173.22:10:51.60#ibcon#*mode == 0, iclass 10, count 2 2006.173.22:10:51.60#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.22:10:51.60#ibcon#[25=AT02-06\r\n] 2006.173.22:10:51.60#ibcon#*before write, iclass 10, count 2 2006.173.22:10:51.60#ibcon#enter sib2, iclass 10, count 2 2006.173.22:10:51.60#ibcon#flushed, iclass 10, count 2 2006.173.22:10:51.60#ibcon#about to write, iclass 10, count 2 2006.173.22:10:51.60#ibcon#wrote, iclass 10, count 2 2006.173.22:10:51.60#ibcon#about to read 3, iclass 10, count 2 2006.173.22:10:51.63#ibcon#read 3, iclass 10, count 2 2006.173.22:10:51.63#ibcon#about to read 4, iclass 10, count 2 2006.173.22:10:51.63#ibcon#read 4, iclass 10, count 2 2006.173.22:10:51.63#ibcon#about to read 5, iclass 10, count 2 2006.173.22:10:51.63#ibcon#read 5, iclass 10, count 2 2006.173.22:10:51.63#ibcon#about to read 6, iclass 10, count 2 2006.173.22:10:51.63#ibcon#read 6, iclass 10, count 2 2006.173.22:10:51.63#ibcon#end of sib2, iclass 10, count 2 2006.173.22:10:51.63#ibcon#*after write, iclass 10, count 2 2006.173.22:10:51.63#ibcon#*before return 0, iclass 10, count 2 2006.173.22:10:51.63#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.22:10:51.63#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.22:10:51.63#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.22:10:51.63#ibcon#ireg 7 cls_cnt 0 2006.173.22:10:51.63#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.22:10:51.75#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.22:10:51.75#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.22:10:51.75#ibcon#enter wrdev, iclass 10, count 0 2006.173.22:10:51.75#ibcon#first serial, iclass 10, count 0 2006.173.22:10:51.75#ibcon#enter sib2, iclass 10, count 0 2006.173.22:10:51.75#ibcon#flushed, iclass 10, count 0 2006.173.22:10:51.75#ibcon#about to write, iclass 10, count 0 2006.173.22:10:51.75#ibcon#wrote, iclass 10, count 0 2006.173.22:10:51.75#ibcon#about to read 3, iclass 10, count 0 2006.173.22:10:51.77#ibcon#read 3, iclass 10, count 0 2006.173.22:10:51.77#ibcon#about to read 4, iclass 10, count 0 2006.173.22:10:51.77#ibcon#read 4, iclass 10, count 0 2006.173.22:10:51.77#ibcon#about to read 5, iclass 10, count 0 2006.173.22:10:51.77#ibcon#read 5, iclass 10, count 0 2006.173.22:10:51.77#ibcon#about to read 6, iclass 10, count 0 2006.173.22:10:51.77#ibcon#read 6, iclass 10, count 0 2006.173.22:10:51.77#ibcon#end of sib2, iclass 10, count 0 2006.173.22:10:51.77#ibcon#*mode == 0, iclass 10, count 0 2006.173.22:10:51.77#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.22:10:51.77#ibcon#[25=USB\r\n] 2006.173.22:10:51.77#ibcon#*before write, iclass 10, count 0 2006.173.22:10:51.77#ibcon#enter sib2, iclass 10, count 0 2006.173.22:10:51.77#ibcon#flushed, iclass 10, count 0 2006.173.22:10:51.77#ibcon#about to write, iclass 10, count 0 2006.173.22:10:51.77#ibcon#wrote, iclass 10, count 0 2006.173.22:10:51.77#ibcon#about to read 3, iclass 10, count 0 2006.173.22:10:51.80#ibcon#read 3, iclass 10, count 0 2006.173.22:10:51.80#ibcon#about to read 4, iclass 10, count 0 2006.173.22:10:51.80#ibcon#read 4, iclass 10, count 0 2006.173.22:10:51.80#ibcon#about to read 5, iclass 10, count 0 2006.173.22:10:51.80#ibcon#read 5, iclass 10, count 0 2006.173.22:10:51.80#ibcon#about to read 6, iclass 10, count 0 2006.173.22:10:51.80#ibcon#read 6, iclass 10, count 0 2006.173.22:10:51.80#ibcon#end of sib2, iclass 10, count 0 2006.173.22:10:51.80#ibcon#*after write, iclass 10, count 0 2006.173.22:10:51.80#ibcon#*before return 0, iclass 10, count 0 2006.173.22:10:51.80#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.22:10:51.80#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.22:10:51.80#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.22:10:51.80#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.22:10:51.80$vck44/valo=3,564.99 2006.173.22:10:51.80#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.22:10:51.80#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.22:10:51.80#ibcon#ireg 17 cls_cnt 0 2006.173.22:10:51.80#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.22:10:51.80#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.22:10:51.80#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.22:10:51.80#ibcon#enter wrdev, iclass 12, count 0 2006.173.22:10:51.80#ibcon#first serial, iclass 12, count 0 2006.173.22:10:51.80#ibcon#enter sib2, iclass 12, count 0 2006.173.22:10:51.80#ibcon#flushed, iclass 12, count 0 2006.173.22:10:51.80#ibcon#about to write, iclass 12, count 0 2006.173.22:10:51.80#ibcon#wrote, iclass 12, count 0 2006.173.22:10:51.80#ibcon#about to read 3, iclass 12, count 0 2006.173.22:10:51.82#ibcon#read 3, iclass 12, count 0 2006.173.22:10:51.82#ibcon#about to read 4, iclass 12, count 0 2006.173.22:10:51.82#ibcon#read 4, iclass 12, count 0 2006.173.22:10:51.82#ibcon#about to read 5, iclass 12, count 0 2006.173.22:10:51.82#ibcon#read 5, iclass 12, count 0 2006.173.22:10:51.82#ibcon#about to read 6, iclass 12, count 0 2006.173.22:10:51.82#ibcon#read 6, iclass 12, count 0 2006.173.22:10:51.82#ibcon#end of sib2, iclass 12, count 0 2006.173.22:10:51.82#ibcon#*mode == 0, iclass 12, count 0 2006.173.22:10:51.82#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.22:10:51.82#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.22:10:51.82#ibcon#*before write, iclass 12, count 0 2006.173.22:10:51.82#ibcon#enter sib2, iclass 12, count 0 2006.173.22:10:51.82#ibcon#flushed, iclass 12, count 0 2006.173.22:10:51.82#ibcon#about to write, iclass 12, count 0 2006.173.22:10:51.82#ibcon#wrote, iclass 12, count 0 2006.173.22:10:51.82#ibcon#about to read 3, iclass 12, count 0 2006.173.22:10:51.86#ibcon#read 3, iclass 12, count 0 2006.173.22:10:51.86#ibcon#about to read 4, iclass 12, count 0 2006.173.22:10:51.86#ibcon#read 4, iclass 12, count 0 2006.173.22:10:51.86#ibcon#about to read 5, iclass 12, count 0 2006.173.22:10:51.86#ibcon#read 5, iclass 12, count 0 2006.173.22:10:51.86#ibcon#about to read 6, iclass 12, count 0 2006.173.22:10:51.86#ibcon#read 6, iclass 12, count 0 2006.173.22:10:51.86#ibcon#end of sib2, iclass 12, count 0 2006.173.22:10:51.86#ibcon#*after write, iclass 12, count 0 2006.173.22:10:51.86#ibcon#*before return 0, iclass 12, count 0 2006.173.22:10:51.86#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.22:10:51.86#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.22:10:51.86#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.22:10:51.86#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.22:10:51.86$vck44/va=3,5 2006.173.22:10:51.86#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.22:10:51.86#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.22:10:51.86#ibcon#ireg 11 cls_cnt 2 2006.173.22:10:51.86#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.22:10:51.92#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.22:10:51.92#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.22:10:51.92#ibcon#enter wrdev, iclass 14, count 2 2006.173.22:10:51.92#ibcon#first serial, iclass 14, count 2 2006.173.22:10:51.92#ibcon#enter sib2, iclass 14, count 2 2006.173.22:10:51.92#ibcon#flushed, iclass 14, count 2 2006.173.22:10:51.92#ibcon#about to write, iclass 14, count 2 2006.173.22:10:51.92#ibcon#wrote, iclass 14, count 2 2006.173.22:10:51.92#ibcon#about to read 3, iclass 14, count 2 2006.173.22:10:51.94#ibcon#read 3, iclass 14, count 2 2006.173.22:10:51.94#ibcon#about to read 4, iclass 14, count 2 2006.173.22:10:51.94#ibcon#read 4, iclass 14, count 2 2006.173.22:10:51.94#ibcon#about to read 5, iclass 14, count 2 2006.173.22:10:51.94#ibcon#read 5, iclass 14, count 2 2006.173.22:10:51.94#ibcon#about to read 6, iclass 14, count 2 2006.173.22:10:51.94#ibcon#read 6, iclass 14, count 2 2006.173.22:10:51.94#ibcon#end of sib2, iclass 14, count 2 2006.173.22:10:51.94#ibcon#*mode == 0, iclass 14, count 2 2006.173.22:10:51.94#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.22:10:51.94#ibcon#[25=AT03-05\r\n] 2006.173.22:10:51.94#ibcon#*before write, iclass 14, count 2 2006.173.22:10:51.94#ibcon#enter sib2, iclass 14, count 2 2006.173.22:10:51.94#ibcon#flushed, iclass 14, count 2 2006.173.22:10:51.94#ibcon#about to write, iclass 14, count 2 2006.173.22:10:51.94#ibcon#wrote, iclass 14, count 2 2006.173.22:10:51.94#ibcon#about to read 3, iclass 14, count 2 2006.173.22:10:51.97#ibcon#read 3, iclass 14, count 2 2006.173.22:10:51.97#ibcon#about to read 4, iclass 14, count 2 2006.173.22:10:51.97#ibcon#read 4, iclass 14, count 2 2006.173.22:10:51.97#ibcon#about to read 5, iclass 14, count 2 2006.173.22:10:51.97#ibcon#read 5, iclass 14, count 2 2006.173.22:10:51.97#ibcon#about to read 6, iclass 14, count 2 2006.173.22:10:51.97#ibcon#read 6, iclass 14, count 2 2006.173.22:10:51.97#ibcon#end of sib2, iclass 14, count 2 2006.173.22:10:51.97#ibcon#*after write, iclass 14, count 2 2006.173.22:10:51.97#ibcon#*before return 0, iclass 14, count 2 2006.173.22:10:51.97#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.22:10:51.97#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.22:10:51.97#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.22:10:51.97#ibcon#ireg 7 cls_cnt 0 2006.173.22:10:51.97#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.22:10:52.09#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.22:10:52.09#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.22:10:52.09#ibcon#enter wrdev, iclass 14, count 0 2006.173.22:10:52.09#ibcon#first serial, iclass 14, count 0 2006.173.22:10:52.09#ibcon#enter sib2, iclass 14, count 0 2006.173.22:10:52.09#ibcon#flushed, iclass 14, count 0 2006.173.22:10:52.09#ibcon#about to write, iclass 14, count 0 2006.173.22:10:52.09#ibcon#wrote, iclass 14, count 0 2006.173.22:10:52.09#ibcon#about to read 3, iclass 14, count 0 2006.173.22:10:52.11#ibcon#read 3, iclass 14, count 0 2006.173.22:10:52.11#ibcon#about to read 4, iclass 14, count 0 2006.173.22:10:52.11#ibcon#read 4, iclass 14, count 0 2006.173.22:10:52.11#ibcon#about to read 5, iclass 14, count 0 2006.173.22:10:52.11#ibcon#read 5, iclass 14, count 0 2006.173.22:10:52.11#ibcon#about to read 6, iclass 14, count 0 2006.173.22:10:52.11#ibcon#read 6, iclass 14, count 0 2006.173.22:10:52.11#ibcon#end of sib2, iclass 14, count 0 2006.173.22:10:52.11#ibcon#*mode == 0, iclass 14, count 0 2006.173.22:10:52.11#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.22:10:52.11#ibcon#[25=USB\r\n] 2006.173.22:10:52.11#ibcon#*before write, iclass 14, count 0 2006.173.22:10:52.11#ibcon#enter sib2, iclass 14, count 0 2006.173.22:10:52.11#ibcon#flushed, iclass 14, count 0 2006.173.22:10:52.11#ibcon#about to write, iclass 14, count 0 2006.173.22:10:52.11#ibcon#wrote, iclass 14, count 0 2006.173.22:10:52.11#ibcon#about to read 3, iclass 14, count 0 2006.173.22:10:52.14#ibcon#read 3, iclass 14, count 0 2006.173.22:10:52.14#ibcon#about to read 4, iclass 14, count 0 2006.173.22:10:52.14#ibcon#read 4, iclass 14, count 0 2006.173.22:10:52.14#ibcon#about to read 5, iclass 14, count 0 2006.173.22:10:52.14#ibcon#read 5, iclass 14, count 0 2006.173.22:10:52.14#ibcon#about to read 6, iclass 14, count 0 2006.173.22:10:52.14#ibcon#read 6, iclass 14, count 0 2006.173.22:10:52.14#ibcon#end of sib2, iclass 14, count 0 2006.173.22:10:52.14#ibcon#*after write, iclass 14, count 0 2006.173.22:10:52.14#ibcon#*before return 0, iclass 14, count 0 2006.173.22:10:52.14#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.22:10:52.14#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.22:10:52.14#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.22:10:52.14#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.22:10:52.14$vck44/valo=4,624.99 2006.173.22:10:52.14#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.22:10:52.14#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.22:10:52.14#ibcon#ireg 17 cls_cnt 0 2006.173.22:10:52.14#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.22:10:52.14#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.22:10:52.14#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.22:10:52.14#ibcon#enter wrdev, iclass 16, count 0 2006.173.22:10:52.14#ibcon#first serial, iclass 16, count 0 2006.173.22:10:52.14#ibcon#enter sib2, iclass 16, count 0 2006.173.22:10:52.14#ibcon#flushed, iclass 16, count 0 2006.173.22:10:52.14#ibcon#about to write, iclass 16, count 0 2006.173.22:10:52.14#ibcon#wrote, iclass 16, count 0 2006.173.22:10:52.14#ibcon#about to read 3, iclass 16, count 0 2006.173.22:10:52.16#ibcon#read 3, iclass 16, count 0 2006.173.22:10:52.16#ibcon#about to read 4, iclass 16, count 0 2006.173.22:10:52.16#ibcon#read 4, iclass 16, count 0 2006.173.22:10:52.16#ibcon#about to read 5, iclass 16, count 0 2006.173.22:10:52.16#ibcon#read 5, iclass 16, count 0 2006.173.22:10:52.16#ibcon#about to read 6, iclass 16, count 0 2006.173.22:10:52.16#ibcon#read 6, iclass 16, count 0 2006.173.22:10:52.16#ibcon#end of sib2, iclass 16, count 0 2006.173.22:10:52.16#ibcon#*mode == 0, iclass 16, count 0 2006.173.22:10:52.16#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.22:10:52.16#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.22:10:52.16#ibcon#*before write, iclass 16, count 0 2006.173.22:10:52.16#ibcon#enter sib2, iclass 16, count 0 2006.173.22:10:52.16#ibcon#flushed, iclass 16, count 0 2006.173.22:10:52.16#ibcon#about to write, iclass 16, count 0 2006.173.22:10:52.16#ibcon#wrote, iclass 16, count 0 2006.173.22:10:52.16#ibcon#about to read 3, iclass 16, count 0 2006.173.22:10:52.20#ibcon#read 3, iclass 16, count 0 2006.173.22:10:52.20#ibcon#about to read 4, iclass 16, count 0 2006.173.22:10:52.20#ibcon#read 4, iclass 16, count 0 2006.173.22:10:52.20#ibcon#about to read 5, iclass 16, count 0 2006.173.22:10:52.20#ibcon#read 5, iclass 16, count 0 2006.173.22:10:52.20#ibcon#about to read 6, iclass 16, count 0 2006.173.22:10:52.20#ibcon#read 6, iclass 16, count 0 2006.173.22:10:52.20#ibcon#end of sib2, iclass 16, count 0 2006.173.22:10:52.20#ibcon#*after write, iclass 16, count 0 2006.173.22:10:52.20#ibcon#*before return 0, iclass 16, count 0 2006.173.22:10:52.20#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.22:10:52.20#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.22:10:52.20#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.22:10:52.20#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.22:10:52.20$vck44/va=4,6 2006.173.22:10:52.20#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.22:10:52.20#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.22:10:52.20#ibcon#ireg 11 cls_cnt 2 2006.173.22:10:52.20#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.22:10:52.26#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.22:10:52.26#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.22:10:52.26#ibcon#enter wrdev, iclass 18, count 2 2006.173.22:10:52.26#ibcon#first serial, iclass 18, count 2 2006.173.22:10:52.26#ibcon#enter sib2, iclass 18, count 2 2006.173.22:10:52.26#ibcon#flushed, iclass 18, count 2 2006.173.22:10:52.26#ibcon#about to write, iclass 18, count 2 2006.173.22:10:52.26#ibcon#wrote, iclass 18, count 2 2006.173.22:10:52.26#ibcon#about to read 3, iclass 18, count 2 2006.173.22:10:52.28#ibcon#read 3, iclass 18, count 2 2006.173.22:10:52.28#ibcon#about to read 4, iclass 18, count 2 2006.173.22:10:52.28#ibcon#read 4, iclass 18, count 2 2006.173.22:10:52.28#ibcon#about to read 5, iclass 18, count 2 2006.173.22:10:52.28#ibcon#read 5, iclass 18, count 2 2006.173.22:10:52.28#ibcon#about to read 6, iclass 18, count 2 2006.173.22:10:52.28#ibcon#read 6, iclass 18, count 2 2006.173.22:10:52.28#ibcon#end of sib2, iclass 18, count 2 2006.173.22:10:52.28#ibcon#*mode == 0, iclass 18, count 2 2006.173.22:10:52.28#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.22:10:52.28#ibcon#[25=AT04-06\r\n] 2006.173.22:10:52.28#ibcon#*before write, iclass 18, count 2 2006.173.22:10:52.28#ibcon#enter sib2, iclass 18, count 2 2006.173.22:10:52.28#ibcon#flushed, iclass 18, count 2 2006.173.22:10:52.28#ibcon#about to write, iclass 18, count 2 2006.173.22:10:52.28#ibcon#wrote, iclass 18, count 2 2006.173.22:10:52.28#ibcon#about to read 3, iclass 18, count 2 2006.173.22:10:52.31#ibcon#read 3, iclass 18, count 2 2006.173.22:10:52.31#ibcon#about to read 4, iclass 18, count 2 2006.173.22:10:52.31#ibcon#read 4, iclass 18, count 2 2006.173.22:10:52.31#ibcon#about to read 5, iclass 18, count 2 2006.173.22:10:52.31#ibcon#read 5, iclass 18, count 2 2006.173.22:10:52.31#ibcon#about to read 6, iclass 18, count 2 2006.173.22:10:52.31#ibcon#read 6, iclass 18, count 2 2006.173.22:10:52.31#ibcon#end of sib2, iclass 18, count 2 2006.173.22:10:52.31#ibcon#*after write, iclass 18, count 2 2006.173.22:10:52.31#ibcon#*before return 0, iclass 18, count 2 2006.173.22:10:52.31#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.22:10:52.31#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.22:10:52.31#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.22:10:52.31#ibcon#ireg 7 cls_cnt 0 2006.173.22:10:52.31#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.22:10:52.43#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.22:10:52.43#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.22:10:52.43#ibcon#enter wrdev, iclass 18, count 0 2006.173.22:10:52.43#ibcon#first serial, iclass 18, count 0 2006.173.22:10:52.43#ibcon#enter sib2, iclass 18, count 0 2006.173.22:10:52.43#ibcon#flushed, iclass 18, count 0 2006.173.22:10:52.43#ibcon#about to write, iclass 18, count 0 2006.173.22:10:52.43#ibcon#wrote, iclass 18, count 0 2006.173.22:10:52.43#ibcon#about to read 3, iclass 18, count 0 2006.173.22:10:52.45#ibcon#read 3, iclass 18, count 0 2006.173.22:10:52.45#ibcon#about to read 4, iclass 18, count 0 2006.173.22:10:52.45#ibcon#read 4, iclass 18, count 0 2006.173.22:10:52.45#ibcon#about to read 5, iclass 18, count 0 2006.173.22:10:52.45#ibcon#read 5, iclass 18, count 0 2006.173.22:10:52.45#ibcon#about to read 6, iclass 18, count 0 2006.173.22:10:52.45#ibcon#read 6, iclass 18, count 0 2006.173.22:10:52.45#ibcon#end of sib2, iclass 18, count 0 2006.173.22:10:52.45#ibcon#*mode == 0, iclass 18, count 0 2006.173.22:10:52.45#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.22:10:52.45#ibcon#[25=USB\r\n] 2006.173.22:10:52.45#ibcon#*before write, iclass 18, count 0 2006.173.22:10:52.45#ibcon#enter sib2, iclass 18, count 0 2006.173.22:10:52.45#ibcon#flushed, iclass 18, count 0 2006.173.22:10:52.45#ibcon#about to write, iclass 18, count 0 2006.173.22:10:52.45#ibcon#wrote, iclass 18, count 0 2006.173.22:10:52.45#ibcon#about to read 3, iclass 18, count 0 2006.173.22:10:52.48#ibcon#read 3, iclass 18, count 0 2006.173.22:10:52.48#ibcon#about to read 4, iclass 18, count 0 2006.173.22:10:52.48#ibcon#read 4, iclass 18, count 0 2006.173.22:10:52.48#ibcon#about to read 5, iclass 18, count 0 2006.173.22:10:52.48#ibcon#read 5, iclass 18, count 0 2006.173.22:10:52.48#ibcon#about to read 6, iclass 18, count 0 2006.173.22:10:52.48#ibcon#read 6, iclass 18, count 0 2006.173.22:10:52.48#ibcon#end of sib2, iclass 18, count 0 2006.173.22:10:52.48#ibcon#*after write, iclass 18, count 0 2006.173.22:10:52.48#ibcon#*before return 0, iclass 18, count 0 2006.173.22:10:52.48#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.22:10:52.48#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.22:10:52.48#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.22:10:52.48#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.22:10:52.48$vck44/valo=5,734.99 2006.173.22:10:52.48#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.22:10:52.48#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.22:10:52.48#ibcon#ireg 17 cls_cnt 0 2006.173.22:10:52.48#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.22:10:52.48#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.22:10:52.48#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.22:10:52.48#ibcon#enter wrdev, iclass 20, count 0 2006.173.22:10:52.48#ibcon#first serial, iclass 20, count 0 2006.173.22:10:52.48#ibcon#enter sib2, iclass 20, count 0 2006.173.22:10:52.48#ibcon#flushed, iclass 20, count 0 2006.173.22:10:52.48#ibcon#about to write, iclass 20, count 0 2006.173.22:10:52.48#ibcon#wrote, iclass 20, count 0 2006.173.22:10:52.48#ibcon#about to read 3, iclass 20, count 0 2006.173.22:10:52.50#ibcon#read 3, iclass 20, count 0 2006.173.22:10:52.50#ibcon#about to read 4, iclass 20, count 0 2006.173.22:10:52.50#ibcon#read 4, iclass 20, count 0 2006.173.22:10:52.50#ibcon#about to read 5, iclass 20, count 0 2006.173.22:10:52.50#ibcon#read 5, iclass 20, count 0 2006.173.22:10:52.50#ibcon#about to read 6, iclass 20, count 0 2006.173.22:10:52.50#ibcon#read 6, iclass 20, count 0 2006.173.22:10:52.50#ibcon#end of sib2, iclass 20, count 0 2006.173.22:10:52.50#ibcon#*mode == 0, iclass 20, count 0 2006.173.22:10:52.50#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.22:10:52.50#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.22:10:52.50#ibcon#*before write, iclass 20, count 0 2006.173.22:10:52.50#ibcon#enter sib2, iclass 20, count 0 2006.173.22:10:52.50#ibcon#flushed, iclass 20, count 0 2006.173.22:10:52.50#ibcon#about to write, iclass 20, count 0 2006.173.22:10:52.50#ibcon#wrote, iclass 20, count 0 2006.173.22:10:52.50#ibcon#about to read 3, iclass 20, count 0 2006.173.22:10:52.54#ibcon#read 3, iclass 20, count 0 2006.173.22:10:52.54#ibcon#about to read 4, iclass 20, count 0 2006.173.22:10:52.54#ibcon#read 4, iclass 20, count 0 2006.173.22:10:52.54#ibcon#about to read 5, iclass 20, count 0 2006.173.22:10:52.54#ibcon#read 5, iclass 20, count 0 2006.173.22:10:52.54#ibcon#about to read 6, iclass 20, count 0 2006.173.22:10:52.54#ibcon#read 6, iclass 20, count 0 2006.173.22:10:52.54#ibcon#end of sib2, iclass 20, count 0 2006.173.22:10:52.54#ibcon#*after write, iclass 20, count 0 2006.173.22:10:52.54#ibcon#*before return 0, iclass 20, count 0 2006.173.22:10:52.54#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.22:10:52.54#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.22:10:52.54#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.22:10:52.54#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.22:10:52.54$vck44/va=5,4 2006.173.22:10:52.54#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.22:10:52.54#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.22:10:52.54#ibcon#ireg 11 cls_cnt 2 2006.173.22:10:52.54#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.22:10:52.60#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.22:10:52.60#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.22:10:52.60#ibcon#enter wrdev, iclass 22, count 2 2006.173.22:10:52.60#ibcon#first serial, iclass 22, count 2 2006.173.22:10:52.60#ibcon#enter sib2, iclass 22, count 2 2006.173.22:10:52.60#ibcon#flushed, iclass 22, count 2 2006.173.22:10:52.60#ibcon#about to write, iclass 22, count 2 2006.173.22:10:52.60#ibcon#wrote, iclass 22, count 2 2006.173.22:10:52.60#ibcon#about to read 3, iclass 22, count 2 2006.173.22:10:52.62#ibcon#read 3, iclass 22, count 2 2006.173.22:10:52.62#ibcon#about to read 4, iclass 22, count 2 2006.173.22:10:52.62#ibcon#read 4, iclass 22, count 2 2006.173.22:10:52.62#ibcon#about to read 5, iclass 22, count 2 2006.173.22:10:52.62#ibcon#read 5, iclass 22, count 2 2006.173.22:10:52.62#ibcon#about to read 6, iclass 22, count 2 2006.173.22:10:52.62#ibcon#read 6, iclass 22, count 2 2006.173.22:10:52.62#ibcon#end of sib2, iclass 22, count 2 2006.173.22:10:52.62#ibcon#*mode == 0, iclass 22, count 2 2006.173.22:10:52.62#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.22:10:52.62#ibcon#[25=AT05-04\r\n] 2006.173.22:10:52.62#ibcon#*before write, iclass 22, count 2 2006.173.22:10:52.62#ibcon#enter sib2, iclass 22, count 2 2006.173.22:10:52.62#ibcon#flushed, iclass 22, count 2 2006.173.22:10:52.62#ibcon#about to write, iclass 22, count 2 2006.173.22:10:52.62#ibcon#wrote, iclass 22, count 2 2006.173.22:10:52.62#ibcon#about to read 3, iclass 22, count 2 2006.173.22:10:52.65#ibcon#read 3, iclass 22, count 2 2006.173.22:10:52.65#ibcon#about to read 4, iclass 22, count 2 2006.173.22:10:52.65#ibcon#read 4, iclass 22, count 2 2006.173.22:10:52.65#ibcon#about to read 5, iclass 22, count 2 2006.173.22:10:52.65#ibcon#read 5, iclass 22, count 2 2006.173.22:10:52.65#ibcon#about to read 6, iclass 22, count 2 2006.173.22:10:52.65#ibcon#read 6, iclass 22, count 2 2006.173.22:10:52.65#ibcon#end of sib2, iclass 22, count 2 2006.173.22:10:52.65#ibcon#*after write, iclass 22, count 2 2006.173.22:10:52.65#ibcon#*before return 0, iclass 22, count 2 2006.173.22:10:52.65#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.22:10:52.65#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.22:10:52.65#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.22:10:52.65#ibcon#ireg 7 cls_cnt 0 2006.173.22:10:52.65#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.22:10:52.77#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.22:10:52.77#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.22:10:52.77#ibcon#enter wrdev, iclass 22, count 0 2006.173.22:10:52.77#ibcon#first serial, iclass 22, count 0 2006.173.22:10:52.77#ibcon#enter sib2, iclass 22, count 0 2006.173.22:10:52.77#ibcon#flushed, iclass 22, count 0 2006.173.22:10:52.77#ibcon#about to write, iclass 22, count 0 2006.173.22:10:52.77#ibcon#wrote, iclass 22, count 0 2006.173.22:10:52.77#ibcon#about to read 3, iclass 22, count 0 2006.173.22:10:52.79#ibcon#read 3, iclass 22, count 0 2006.173.22:10:52.79#ibcon#about to read 4, iclass 22, count 0 2006.173.22:10:52.79#ibcon#read 4, iclass 22, count 0 2006.173.22:10:52.79#ibcon#about to read 5, iclass 22, count 0 2006.173.22:10:52.79#ibcon#read 5, iclass 22, count 0 2006.173.22:10:52.79#ibcon#about to read 6, iclass 22, count 0 2006.173.22:10:52.79#ibcon#read 6, iclass 22, count 0 2006.173.22:10:52.79#ibcon#end of sib2, iclass 22, count 0 2006.173.22:10:52.79#ibcon#*mode == 0, iclass 22, count 0 2006.173.22:10:52.79#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.22:10:52.79#ibcon#[25=USB\r\n] 2006.173.22:10:52.79#ibcon#*before write, iclass 22, count 0 2006.173.22:10:52.79#ibcon#enter sib2, iclass 22, count 0 2006.173.22:10:52.79#ibcon#flushed, iclass 22, count 0 2006.173.22:10:52.79#ibcon#about to write, iclass 22, count 0 2006.173.22:10:52.79#ibcon#wrote, iclass 22, count 0 2006.173.22:10:52.79#ibcon#about to read 3, iclass 22, count 0 2006.173.22:10:52.82#ibcon#read 3, iclass 22, count 0 2006.173.22:10:52.82#ibcon#about to read 4, iclass 22, count 0 2006.173.22:10:52.82#ibcon#read 4, iclass 22, count 0 2006.173.22:10:52.82#ibcon#about to read 5, iclass 22, count 0 2006.173.22:10:52.82#ibcon#read 5, iclass 22, count 0 2006.173.22:10:52.82#ibcon#about to read 6, iclass 22, count 0 2006.173.22:10:52.82#ibcon#read 6, iclass 22, count 0 2006.173.22:10:52.82#ibcon#end of sib2, iclass 22, count 0 2006.173.22:10:52.82#ibcon#*after write, iclass 22, count 0 2006.173.22:10:52.82#ibcon#*before return 0, iclass 22, count 0 2006.173.22:10:52.82#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.22:10:52.82#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.22:10:52.82#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.22:10:52.82#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.22:10:52.82$vck44/valo=6,814.99 2006.173.22:10:52.82#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.22:10:52.82#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.22:10:52.82#ibcon#ireg 17 cls_cnt 0 2006.173.22:10:52.82#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.22:10:52.82#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.22:10:52.82#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.22:10:52.82#ibcon#enter wrdev, iclass 24, count 0 2006.173.22:10:52.82#ibcon#first serial, iclass 24, count 0 2006.173.22:10:52.82#ibcon#enter sib2, iclass 24, count 0 2006.173.22:10:52.82#ibcon#flushed, iclass 24, count 0 2006.173.22:10:52.82#ibcon#about to write, iclass 24, count 0 2006.173.22:10:52.82#ibcon#wrote, iclass 24, count 0 2006.173.22:10:52.82#ibcon#about to read 3, iclass 24, count 0 2006.173.22:10:52.84#ibcon#read 3, iclass 24, count 0 2006.173.22:10:52.84#ibcon#about to read 4, iclass 24, count 0 2006.173.22:10:52.84#ibcon#read 4, iclass 24, count 0 2006.173.22:10:52.84#ibcon#about to read 5, iclass 24, count 0 2006.173.22:10:52.84#ibcon#read 5, iclass 24, count 0 2006.173.22:10:52.84#ibcon#about to read 6, iclass 24, count 0 2006.173.22:10:52.84#ibcon#read 6, iclass 24, count 0 2006.173.22:10:52.84#ibcon#end of sib2, iclass 24, count 0 2006.173.22:10:52.84#ibcon#*mode == 0, iclass 24, count 0 2006.173.22:10:52.84#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.22:10:52.84#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.22:10:52.84#ibcon#*before write, iclass 24, count 0 2006.173.22:10:52.84#ibcon#enter sib2, iclass 24, count 0 2006.173.22:10:52.84#ibcon#flushed, iclass 24, count 0 2006.173.22:10:52.84#ibcon#about to write, iclass 24, count 0 2006.173.22:10:52.84#ibcon#wrote, iclass 24, count 0 2006.173.22:10:52.84#ibcon#about to read 3, iclass 24, count 0 2006.173.22:10:52.88#ibcon#read 3, iclass 24, count 0 2006.173.22:10:52.88#ibcon#about to read 4, iclass 24, count 0 2006.173.22:10:52.88#ibcon#read 4, iclass 24, count 0 2006.173.22:10:52.88#ibcon#about to read 5, iclass 24, count 0 2006.173.22:10:52.88#ibcon#read 5, iclass 24, count 0 2006.173.22:10:52.88#ibcon#about to read 6, iclass 24, count 0 2006.173.22:10:52.88#ibcon#read 6, iclass 24, count 0 2006.173.22:10:52.88#ibcon#end of sib2, iclass 24, count 0 2006.173.22:10:52.88#ibcon#*after write, iclass 24, count 0 2006.173.22:10:52.88#ibcon#*before return 0, iclass 24, count 0 2006.173.22:10:52.88#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.22:10:52.88#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.22:10:52.88#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.22:10:52.88#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.22:10:52.88$vck44/va=6,3 2006.173.22:10:52.88#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.22:10:52.88#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.22:10:52.88#ibcon#ireg 11 cls_cnt 2 2006.173.22:10:52.88#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.22:10:52.94#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.22:10:52.94#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.22:10:52.94#ibcon#enter wrdev, iclass 26, count 2 2006.173.22:10:52.94#ibcon#first serial, iclass 26, count 2 2006.173.22:10:52.94#ibcon#enter sib2, iclass 26, count 2 2006.173.22:10:52.94#ibcon#flushed, iclass 26, count 2 2006.173.22:10:52.94#ibcon#about to write, iclass 26, count 2 2006.173.22:10:52.94#ibcon#wrote, iclass 26, count 2 2006.173.22:10:52.94#ibcon#about to read 3, iclass 26, count 2 2006.173.22:10:52.96#ibcon#read 3, iclass 26, count 2 2006.173.22:10:52.96#ibcon#about to read 4, iclass 26, count 2 2006.173.22:10:52.96#ibcon#read 4, iclass 26, count 2 2006.173.22:10:52.96#ibcon#about to read 5, iclass 26, count 2 2006.173.22:10:52.96#ibcon#read 5, iclass 26, count 2 2006.173.22:10:52.96#ibcon#about to read 6, iclass 26, count 2 2006.173.22:10:52.96#ibcon#read 6, iclass 26, count 2 2006.173.22:10:52.96#ibcon#end of sib2, iclass 26, count 2 2006.173.22:10:52.96#ibcon#*mode == 0, iclass 26, count 2 2006.173.22:10:52.96#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.22:10:52.96#ibcon#[25=AT06-03\r\n] 2006.173.22:10:52.96#ibcon#*before write, iclass 26, count 2 2006.173.22:10:52.96#ibcon#enter sib2, iclass 26, count 2 2006.173.22:10:52.96#ibcon#flushed, iclass 26, count 2 2006.173.22:10:52.96#ibcon#about to write, iclass 26, count 2 2006.173.22:10:52.96#ibcon#wrote, iclass 26, count 2 2006.173.22:10:52.96#ibcon#about to read 3, iclass 26, count 2 2006.173.22:10:52.99#ibcon#read 3, iclass 26, count 2 2006.173.22:10:52.99#ibcon#about to read 4, iclass 26, count 2 2006.173.22:10:52.99#ibcon#read 4, iclass 26, count 2 2006.173.22:10:52.99#ibcon#about to read 5, iclass 26, count 2 2006.173.22:10:52.99#ibcon#read 5, iclass 26, count 2 2006.173.22:10:52.99#ibcon#about to read 6, iclass 26, count 2 2006.173.22:10:52.99#ibcon#read 6, iclass 26, count 2 2006.173.22:10:52.99#ibcon#end of sib2, iclass 26, count 2 2006.173.22:10:52.99#ibcon#*after write, iclass 26, count 2 2006.173.22:10:52.99#ibcon#*before return 0, iclass 26, count 2 2006.173.22:10:52.99#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.22:10:52.99#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.22:10:52.99#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.22:10:52.99#ibcon#ireg 7 cls_cnt 0 2006.173.22:10:52.99#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.22:10:53.11#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.22:10:53.11#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.22:10:53.11#ibcon#enter wrdev, iclass 26, count 0 2006.173.22:10:53.11#ibcon#first serial, iclass 26, count 0 2006.173.22:10:53.11#ibcon#enter sib2, iclass 26, count 0 2006.173.22:10:53.11#ibcon#flushed, iclass 26, count 0 2006.173.22:10:53.11#ibcon#about to write, iclass 26, count 0 2006.173.22:10:53.11#ibcon#wrote, iclass 26, count 0 2006.173.22:10:53.11#ibcon#about to read 3, iclass 26, count 0 2006.173.22:10:53.13#ibcon#read 3, iclass 26, count 0 2006.173.22:10:53.13#ibcon#about to read 4, iclass 26, count 0 2006.173.22:10:53.13#ibcon#read 4, iclass 26, count 0 2006.173.22:10:53.13#ibcon#about to read 5, iclass 26, count 0 2006.173.22:10:53.13#ibcon#read 5, iclass 26, count 0 2006.173.22:10:53.13#ibcon#about to read 6, iclass 26, count 0 2006.173.22:10:53.13#ibcon#read 6, iclass 26, count 0 2006.173.22:10:53.13#ibcon#end of sib2, iclass 26, count 0 2006.173.22:10:53.13#ibcon#*mode == 0, iclass 26, count 0 2006.173.22:10:53.13#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.22:10:53.13#ibcon#[25=USB\r\n] 2006.173.22:10:53.13#ibcon#*before write, iclass 26, count 0 2006.173.22:10:53.13#ibcon#enter sib2, iclass 26, count 0 2006.173.22:10:53.13#ibcon#flushed, iclass 26, count 0 2006.173.22:10:53.13#ibcon#about to write, iclass 26, count 0 2006.173.22:10:53.13#ibcon#wrote, iclass 26, count 0 2006.173.22:10:53.13#ibcon#about to read 3, iclass 26, count 0 2006.173.22:10:53.16#ibcon#read 3, iclass 26, count 0 2006.173.22:10:53.16#ibcon#about to read 4, iclass 26, count 0 2006.173.22:10:53.16#ibcon#read 4, iclass 26, count 0 2006.173.22:10:53.16#ibcon#about to read 5, iclass 26, count 0 2006.173.22:10:53.16#ibcon#read 5, iclass 26, count 0 2006.173.22:10:53.16#ibcon#about to read 6, iclass 26, count 0 2006.173.22:10:53.16#ibcon#read 6, iclass 26, count 0 2006.173.22:10:53.16#ibcon#end of sib2, iclass 26, count 0 2006.173.22:10:53.16#ibcon#*after write, iclass 26, count 0 2006.173.22:10:53.16#ibcon#*before return 0, iclass 26, count 0 2006.173.22:10:53.16#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.22:10:53.16#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.22:10:53.16#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.22:10:53.16#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.22:10:53.16$vck44/valo=7,864.99 2006.173.22:10:53.16#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.22:10:53.16#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.22:10:53.16#ibcon#ireg 17 cls_cnt 0 2006.173.22:10:53.16#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.22:10:53.16#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.22:10:53.16#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.22:10:53.16#ibcon#enter wrdev, iclass 28, count 0 2006.173.22:10:53.16#ibcon#first serial, iclass 28, count 0 2006.173.22:10:53.16#ibcon#enter sib2, iclass 28, count 0 2006.173.22:10:53.16#ibcon#flushed, iclass 28, count 0 2006.173.22:10:53.16#ibcon#about to write, iclass 28, count 0 2006.173.22:10:53.16#ibcon#wrote, iclass 28, count 0 2006.173.22:10:53.16#ibcon#about to read 3, iclass 28, count 0 2006.173.22:10:53.18#ibcon#read 3, iclass 28, count 0 2006.173.22:10:53.18#ibcon#about to read 4, iclass 28, count 0 2006.173.22:10:53.18#ibcon#read 4, iclass 28, count 0 2006.173.22:10:53.18#ibcon#about to read 5, iclass 28, count 0 2006.173.22:10:53.18#ibcon#read 5, iclass 28, count 0 2006.173.22:10:53.18#ibcon#about to read 6, iclass 28, count 0 2006.173.22:10:53.18#ibcon#read 6, iclass 28, count 0 2006.173.22:10:53.18#ibcon#end of sib2, iclass 28, count 0 2006.173.22:10:53.18#ibcon#*mode == 0, iclass 28, count 0 2006.173.22:10:53.18#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.22:10:53.18#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.22:10:53.18#ibcon#*before write, iclass 28, count 0 2006.173.22:10:53.18#ibcon#enter sib2, iclass 28, count 0 2006.173.22:10:53.18#ibcon#flushed, iclass 28, count 0 2006.173.22:10:53.18#ibcon#about to write, iclass 28, count 0 2006.173.22:10:53.18#ibcon#wrote, iclass 28, count 0 2006.173.22:10:53.18#ibcon#about to read 3, iclass 28, count 0 2006.173.22:10:53.22#ibcon#read 3, iclass 28, count 0 2006.173.22:10:53.22#ibcon#about to read 4, iclass 28, count 0 2006.173.22:10:53.22#ibcon#read 4, iclass 28, count 0 2006.173.22:10:53.22#ibcon#about to read 5, iclass 28, count 0 2006.173.22:10:53.22#ibcon#read 5, iclass 28, count 0 2006.173.22:10:53.22#ibcon#about to read 6, iclass 28, count 0 2006.173.22:10:53.22#ibcon#read 6, iclass 28, count 0 2006.173.22:10:53.22#ibcon#end of sib2, iclass 28, count 0 2006.173.22:10:53.22#ibcon#*after write, iclass 28, count 0 2006.173.22:10:53.22#ibcon#*before return 0, iclass 28, count 0 2006.173.22:10:53.22#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.22:10:53.22#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.22:10:53.22#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.22:10:53.22#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.22:10:53.22$vck44/va=7,4 2006.173.22:10:53.22#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.22:10:53.22#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.22:10:53.22#ibcon#ireg 11 cls_cnt 2 2006.173.22:10:53.22#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.22:10:53.28#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.22:10:53.28#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.22:10:53.28#ibcon#enter wrdev, iclass 30, count 2 2006.173.22:10:53.28#ibcon#first serial, iclass 30, count 2 2006.173.22:10:53.28#ibcon#enter sib2, iclass 30, count 2 2006.173.22:10:53.28#ibcon#flushed, iclass 30, count 2 2006.173.22:10:53.28#ibcon#about to write, iclass 30, count 2 2006.173.22:10:53.28#ibcon#wrote, iclass 30, count 2 2006.173.22:10:53.28#ibcon#about to read 3, iclass 30, count 2 2006.173.22:10:53.30#ibcon#read 3, iclass 30, count 2 2006.173.22:10:53.30#ibcon#about to read 4, iclass 30, count 2 2006.173.22:10:53.30#ibcon#read 4, iclass 30, count 2 2006.173.22:10:53.30#ibcon#about to read 5, iclass 30, count 2 2006.173.22:10:53.30#ibcon#read 5, iclass 30, count 2 2006.173.22:10:53.30#ibcon#about to read 6, iclass 30, count 2 2006.173.22:10:53.30#ibcon#read 6, iclass 30, count 2 2006.173.22:10:53.30#ibcon#end of sib2, iclass 30, count 2 2006.173.22:10:53.30#ibcon#*mode == 0, iclass 30, count 2 2006.173.22:10:53.30#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.22:10:53.30#ibcon#[25=AT07-04\r\n] 2006.173.22:10:53.30#ibcon#*before write, iclass 30, count 2 2006.173.22:10:53.30#ibcon#enter sib2, iclass 30, count 2 2006.173.22:10:53.30#ibcon#flushed, iclass 30, count 2 2006.173.22:10:53.30#ibcon#about to write, iclass 30, count 2 2006.173.22:10:53.30#ibcon#wrote, iclass 30, count 2 2006.173.22:10:53.30#ibcon#about to read 3, iclass 30, count 2 2006.173.22:10:53.33#ibcon#read 3, iclass 30, count 2 2006.173.22:10:53.33#ibcon#about to read 4, iclass 30, count 2 2006.173.22:10:53.33#ibcon#read 4, iclass 30, count 2 2006.173.22:10:53.33#ibcon#about to read 5, iclass 30, count 2 2006.173.22:10:53.33#ibcon#read 5, iclass 30, count 2 2006.173.22:10:53.33#ibcon#about to read 6, iclass 30, count 2 2006.173.22:10:53.33#ibcon#read 6, iclass 30, count 2 2006.173.22:10:53.33#ibcon#end of sib2, iclass 30, count 2 2006.173.22:10:53.33#ibcon#*after write, iclass 30, count 2 2006.173.22:10:53.33#ibcon#*before return 0, iclass 30, count 2 2006.173.22:10:53.33#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.22:10:53.33#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.22:10:53.33#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.22:10:53.33#ibcon#ireg 7 cls_cnt 0 2006.173.22:10:53.33#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.22:10:53.45#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.22:10:53.45#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.22:10:53.45#ibcon#enter wrdev, iclass 30, count 0 2006.173.22:10:53.45#ibcon#first serial, iclass 30, count 0 2006.173.22:10:53.45#ibcon#enter sib2, iclass 30, count 0 2006.173.22:10:53.45#ibcon#flushed, iclass 30, count 0 2006.173.22:10:53.45#ibcon#about to write, iclass 30, count 0 2006.173.22:10:53.45#ibcon#wrote, iclass 30, count 0 2006.173.22:10:53.45#ibcon#about to read 3, iclass 30, count 0 2006.173.22:10:53.47#ibcon#read 3, iclass 30, count 0 2006.173.22:10:53.47#ibcon#about to read 4, iclass 30, count 0 2006.173.22:10:53.47#ibcon#read 4, iclass 30, count 0 2006.173.22:10:53.47#ibcon#about to read 5, iclass 30, count 0 2006.173.22:10:53.47#ibcon#read 5, iclass 30, count 0 2006.173.22:10:53.47#ibcon#about to read 6, iclass 30, count 0 2006.173.22:10:53.47#ibcon#read 6, iclass 30, count 0 2006.173.22:10:53.47#ibcon#end of sib2, iclass 30, count 0 2006.173.22:10:53.47#ibcon#*mode == 0, iclass 30, count 0 2006.173.22:10:53.47#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.22:10:53.47#ibcon#[25=USB\r\n] 2006.173.22:10:53.47#ibcon#*before write, iclass 30, count 0 2006.173.22:10:53.47#ibcon#enter sib2, iclass 30, count 0 2006.173.22:10:53.47#ibcon#flushed, iclass 30, count 0 2006.173.22:10:53.47#ibcon#about to write, iclass 30, count 0 2006.173.22:10:53.47#ibcon#wrote, iclass 30, count 0 2006.173.22:10:53.47#ibcon#about to read 3, iclass 30, count 0 2006.173.22:10:53.50#ibcon#read 3, iclass 30, count 0 2006.173.22:10:53.50#ibcon#about to read 4, iclass 30, count 0 2006.173.22:10:53.50#ibcon#read 4, iclass 30, count 0 2006.173.22:10:53.50#ibcon#about to read 5, iclass 30, count 0 2006.173.22:10:53.50#ibcon#read 5, iclass 30, count 0 2006.173.22:10:53.50#ibcon#about to read 6, iclass 30, count 0 2006.173.22:10:53.50#ibcon#read 6, iclass 30, count 0 2006.173.22:10:53.50#ibcon#end of sib2, iclass 30, count 0 2006.173.22:10:53.50#ibcon#*after write, iclass 30, count 0 2006.173.22:10:53.50#ibcon#*before return 0, iclass 30, count 0 2006.173.22:10:53.50#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.22:10:53.50#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.22:10:53.50#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.22:10:53.50#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.22:10:53.50$vck44/valo=8,884.99 2006.173.22:10:53.50#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.22:10:53.50#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.22:10:53.50#ibcon#ireg 17 cls_cnt 0 2006.173.22:10:53.50#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.22:10:53.50#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.22:10:53.50#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.22:10:53.50#ibcon#enter wrdev, iclass 32, count 0 2006.173.22:10:53.50#ibcon#first serial, iclass 32, count 0 2006.173.22:10:53.50#ibcon#enter sib2, iclass 32, count 0 2006.173.22:10:53.50#ibcon#flushed, iclass 32, count 0 2006.173.22:10:53.50#ibcon#about to write, iclass 32, count 0 2006.173.22:10:53.50#ibcon#wrote, iclass 32, count 0 2006.173.22:10:53.50#ibcon#about to read 3, iclass 32, count 0 2006.173.22:10:53.52#ibcon#read 3, iclass 32, count 0 2006.173.22:10:53.52#ibcon#about to read 4, iclass 32, count 0 2006.173.22:10:53.52#ibcon#read 4, iclass 32, count 0 2006.173.22:10:53.52#ibcon#about to read 5, iclass 32, count 0 2006.173.22:10:53.52#ibcon#read 5, iclass 32, count 0 2006.173.22:10:53.52#ibcon#about to read 6, iclass 32, count 0 2006.173.22:10:53.52#ibcon#read 6, iclass 32, count 0 2006.173.22:10:53.52#ibcon#end of sib2, iclass 32, count 0 2006.173.22:10:53.52#ibcon#*mode == 0, iclass 32, count 0 2006.173.22:10:53.52#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.22:10:53.52#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.22:10:53.52#ibcon#*before write, iclass 32, count 0 2006.173.22:10:53.52#ibcon#enter sib2, iclass 32, count 0 2006.173.22:10:53.52#ibcon#flushed, iclass 32, count 0 2006.173.22:10:53.52#ibcon#about to write, iclass 32, count 0 2006.173.22:10:53.52#ibcon#wrote, iclass 32, count 0 2006.173.22:10:53.52#ibcon#about to read 3, iclass 32, count 0 2006.173.22:10:53.56#ibcon#read 3, iclass 32, count 0 2006.173.22:10:53.56#ibcon#about to read 4, iclass 32, count 0 2006.173.22:10:53.56#ibcon#read 4, iclass 32, count 0 2006.173.22:10:53.56#ibcon#about to read 5, iclass 32, count 0 2006.173.22:10:53.56#ibcon#read 5, iclass 32, count 0 2006.173.22:10:53.56#ibcon#about to read 6, iclass 32, count 0 2006.173.22:10:53.56#ibcon#read 6, iclass 32, count 0 2006.173.22:10:53.56#ibcon#end of sib2, iclass 32, count 0 2006.173.22:10:53.56#ibcon#*after write, iclass 32, count 0 2006.173.22:10:53.56#ibcon#*before return 0, iclass 32, count 0 2006.173.22:10:53.56#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.22:10:53.56#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.22:10:53.56#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.22:10:53.56#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.22:10:53.56$vck44/va=8,4 2006.173.22:10:53.56#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.22:10:53.56#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.22:10:53.56#ibcon#ireg 11 cls_cnt 2 2006.173.22:10:53.56#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.22:10:53.62#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.22:10:53.62#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.22:10:53.62#ibcon#enter wrdev, iclass 34, count 2 2006.173.22:10:53.62#ibcon#first serial, iclass 34, count 2 2006.173.22:10:53.62#ibcon#enter sib2, iclass 34, count 2 2006.173.22:10:53.62#ibcon#flushed, iclass 34, count 2 2006.173.22:10:53.62#ibcon#about to write, iclass 34, count 2 2006.173.22:10:53.62#ibcon#wrote, iclass 34, count 2 2006.173.22:10:53.62#ibcon#about to read 3, iclass 34, count 2 2006.173.22:10:53.64#ibcon#read 3, iclass 34, count 2 2006.173.22:10:53.64#ibcon#about to read 4, iclass 34, count 2 2006.173.22:10:53.64#ibcon#read 4, iclass 34, count 2 2006.173.22:10:53.64#ibcon#about to read 5, iclass 34, count 2 2006.173.22:10:53.64#ibcon#read 5, iclass 34, count 2 2006.173.22:10:53.64#ibcon#about to read 6, iclass 34, count 2 2006.173.22:10:53.64#ibcon#read 6, iclass 34, count 2 2006.173.22:10:53.64#ibcon#end of sib2, iclass 34, count 2 2006.173.22:10:53.64#ibcon#*mode == 0, iclass 34, count 2 2006.173.22:10:53.64#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.22:10:53.64#ibcon#[25=AT08-04\r\n] 2006.173.22:10:53.64#ibcon#*before write, iclass 34, count 2 2006.173.22:10:53.64#ibcon#enter sib2, iclass 34, count 2 2006.173.22:10:53.64#ibcon#flushed, iclass 34, count 2 2006.173.22:10:53.64#ibcon#about to write, iclass 34, count 2 2006.173.22:10:53.64#ibcon#wrote, iclass 34, count 2 2006.173.22:10:53.64#ibcon#about to read 3, iclass 34, count 2 2006.173.22:10:53.67#ibcon#read 3, iclass 34, count 2 2006.173.22:10:53.67#ibcon#about to read 4, iclass 34, count 2 2006.173.22:10:53.67#ibcon#read 4, iclass 34, count 2 2006.173.22:10:53.67#ibcon#about to read 5, iclass 34, count 2 2006.173.22:10:53.67#ibcon#read 5, iclass 34, count 2 2006.173.22:10:53.67#ibcon#about to read 6, iclass 34, count 2 2006.173.22:10:53.67#ibcon#read 6, iclass 34, count 2 2006.173.22:10:53.67#ibcon#end of sib2, iclass 34, count 2 2006.173.22:10:53.67#ibcon#*after write, iclass 34, count 2 2006.173.22:10:53.67#ibcon#*before return 0, iclass 34, count 2 2006.173.22:10:53.67#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.22:10:53.67#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.22:10:53.67#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.22:10:53.67#ibcon#ireg 7 cls_cnt 0 2006.173.22:10:53.67#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.22:10:53.79#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.22:10:53.79#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.22:10:53.79#ibcon#enter wrdev, iclass 34, count 0 2006.173.22:10:53.79#ibcon#first serial, iclass 34, count 0 2006.173.22:10:53.79#ibcon#enter sib2, iclass 34, count 0 2006.173.22:10:53.79#ibcon#flushed, iclass 34, count 0 2006.173.22:10:53.79#ibcon#about to write, iclass 34, count 0 2006.173.22:10:53.79#ibcon#wrote, iclass 34, count 0 2006.173.22:10:53.79#ibcon#about to read 3, iclass 34, count 0 2006.173.22:10:53.81#ibcon#read 3, iclass 34, count 0 2006.173.22:10:53.81#ibcon#about to read 4, iclass 34, count 0 2006.173.22:10:53.81#ibcon#read 4, iclass 34, count 0 2006.173.22:10:53.81#ibcon#about to read 5, iclass 34, count 0 2006.173.22:10:53.81#ibcon#read 5, iclass 34, count 0 2006.173.22:10:53.81#ibcon#about to read 6, iclass 34, count 0 2006.173.22:10:53.81#ibcon#read 6, iclass 34, count 0 2006.173.22:10:53.81#ibcon#end of sib2, iclass 34, count 0 2006.173.22:10:53.81#ibcon#*mode == 0, iclass 34, count 0 2006.173.22:10:53.81#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.22:10:53.81#ibcon#[25=USB\r\n] 2006.173.22:10:53.81#ibcon#*before write, iclass 34, count 0 2006.173.22:10:53.81#ibcon#enter sib2, iclass 34, count 0 2006.173.22:10:53.81#ibcon#flushed, iclass 34, count 0 2006.173.22:10:53.81#ibcon#about to write, iclass 34, count 0 2006.173.22:10:53.81#ibcon#wrote, iclass 34, count 0 2006.173.22:10:53.81#ibcon#about to read 3, iclass 34, count 0 2006.173.22:10:53.84#ibcon#read 3, iclass 34, count 0 2006.173.22:10:53.84#ibcon#about to read 4, iclass 34, count 0 2006.173.22:10:53.84#ibcon#read 4, iclass 34, count 0 2006.173.22:10:53.84#ibcon#about to read 5, iclass 34, count 0 2006.173.22:10:53.84#ibcon#read 5, iclass 34, count 0 2006.173.22:10:53.84#ibcon#about to read 6, iclass 34, count 0 2006.173.22:10:53.84#ibcon#read 6, iclass 34, count 0 2006.173.22:10:53.84#ibcon#end of sib2, iclass 34, count 0 2006.173.22:10:53.84#ibcon#*after write, iclass 34, count 0 2006.173.22:10:53.84#ibcon#*before return 0, iclass 34, count 0 2006.173.22:10:53.84#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.22:10:53.84#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.22:10:53.84#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.22:10:53.84#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.22:10:53.84$vck44/vblo=1,629.99 2006.173.22:10:53.84#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.22:10:53.84#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.22:10:53.84#ibcon#ireg 17 cls_cnt 0 2006.173.22:10:53.84#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.22:10:53.84#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.22:10:53.84#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.22:10:53.84#ibcon#enter wrdev, iclass 36, count 0 2006.173.22:10:53.84#ibcon#first serial, iclass 36, count 0 2006.173.22:10:53.84#ibcon#enter sib2, iclass 36, count 0 2006.173.22:10:53.84#ibcon#flushed, iclass 36, count 0 2006.173.22:10:53.84#ibcon#about to write, iclass 36, count 0 2006.173.22:10:53.84#ibcon#wrote, iclass 36, count 0 2006.173.22:10:53.84#ibcon#about to read 3, iclass 36, count 0 2006.173.22:10:53.86#ibcon#read 3, iclass 36, count 0 2006.173.22:10:53.86#ibcon#about to read 4, iclass 36, count 0 2006.173.22:10:53.86#ibcon#read 4, iclass 36, count 0 2006.173.22:10:53.86#ibcon#about to read 5, iclass 36, count 0 2006.173.22:10:53.86#ibcon#read 5, iclass 36, count 0 2006.173.22:10:53.86#ibcon#about to read 6, iclass 36, count 0 2006.173.22:10:53.86#ibcon#read 6, iclass 36, count 0 2006.173.22:10:53.86#ibcon#end of sib2, iclass 36, count 0 2006.173.22:10:53.86#ibcon#*mode == 0, iclass 36, count 0 2006.173.22:10:53.86#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.22:10:53.86#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.22:10:53.86#ibcon#*before write, iclass 36, count 0 2006.173.22:10:53.86#ibcon#enter sib2, iclass 36, count 0 2006.173.22:10:53.86#ibcon#flushed, iclass 36, count 0 2006.173.22:10:53.86#ibcon#about to write, iclass 36, count 0 2006.173.22:10:53.86#ibcon#wrote, iclass 36, count 0 2006.173.22:10:53.86#ibcon#about to read 3, iclass 36, count 0 2006.173.22:10:53.90#ibcon#read 3, iclass 36, count 0 2006.173.22:10:53.90#ibcon#about to read 4, iclass 36, count 0 2006.173.22:10:53.90#ibcon#read 4, iclass 36, count 0 2006.173.22:10:53.90#ibcon#about to read 5, iclass 36, count 0 2006.173.22:10:53.90#ibcon#read 5, iclass 36, count 0 2006.173.22:10:53.90#ibcon#about to read 6, iclass 36, count 0 2006.173.22:10:53.90#ibcon#read 6, iclass 36, count 0 2006.173.22:10:53.90#ibcon#end of sib2, iclass 36, count 0 2006.173.22:10:53.90#ibcon#*after write, iclass 36, count 0 2006.173.22:10:53.90#ibcon#*before return 0, iclass 36, count 0 2006.173.22:10:53.90#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.22:10:53.90#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.22:10:53.90#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.22:10:53.90#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.22:10:53.90$vck44/vb=1,4 2006.173.22:10:53.90#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.22:10:53.90#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.22:10:53.90#ibcon#ireg 11 cls_cnt 2 2006.173.22:10:53.90#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.22:10:53.90#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.22:10:53.90#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.22:10:53.90#ibcon#enter wrdev, iclass 38, count 2 2006.173.22:10:53.90#ibcon#first serial, iclass 38, count 2 2006.173.22:10:53.90#ibcon#enter sib2, iclass 38, count 2 2006.173.22:10:53.90#ibcon#flushed, iclass 38, count 2 2006.173.22:10:53.90#ibcon#about to write, iclass 38, count 2 2006.173.22:10:53.90#ibcon#wrote, iclass 38, count 2 2006.173.22:10:53.90#ibcon#about to read 3, iclass 38, count 2 2006.173.22:10:53.92#ibcon#read 3, iclass 38, count 2 2006.173.22:10:53.92#ibcon#about to read 4, iclass 38, count 2 2006.173.22:10:53.92#ibcon#read 4, iclass 38, count 2 2006.173.22:10:53.92#ibcon#about to read 5, iclass 38, count 2 2006.173.22:10:53.92#ibcon#read 5, iclass 38, count 2 2006.173.22:10:53.92#ibcon#about to read 6, iclass 38, count 2 2006.173.22:10:53.92#ibcon#read 6, iclass 38, count 2 2006.173.22:10:53.92#ibcon#end of sib2, iclass 38, count 2 2006.173.22:10:53.92#ibcon#*mode == 0, iclass 38, count 2 2006.173.22:10:53.92#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.22:10:53.92#ibcon#[27=AT01-04\r\n] 2006.173.22:10:53.92#ibcon#*before write, iclass 38, count 2 2006.173.22:10:53.92#ibcon#enter sib2, iclass 38, count 2 2006.173.22:10:53.92#ibcon#flushed, iclass 38, count 2 2006.173.22:10:53.92#ibcon#about to write, iclass 38, count 2 2006.173.22:10:53.92#ibcon#wrote, iclass 38, count 2 2006.173.22:10:53.92#ibcon#about to read 3, iclass 38, count 2 2006.173.22:10:53.95#ibcon#read 3, iclass 38, count 2 2006.173.22:10:53.95#ibcon#about to read 4, iclass 38, count 2 2006.173.22:10:53.95#ibcon#read 4, iclass 38, count 2 2006.173.22:10:53.95#ibcon#about to read 5, iclass 38, count 2 2006.173.22:10:53.95#ibcon#read 5, iclass 38, count 2 2006.173.22:10:53.95#ibcon#about to read 6, iclass 38, count 2 2006.173.22:10:53.95#ibcon#read 6, iclass 38, count 2 2006.173.22:10:53.95#ibcon#end of sib2, iclass 38, count 2 2006.173.22:10:53.95#ibcon#*after write, iclass 38, count 2 2006.173.22:10:53.95#ibcon#*before return 0, iclass 38, count 2 2006.173.22:10:53.95#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.22:10:53.95#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.22:10:53.95#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.22:10:53.95#ibcon#ireg 7 cls_cnt 0 2006.173.22:10:53.95#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.22:10:54.07#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.22:10:54.07#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.22:10:54.07#ibcon#enter wrdev, iclass 38, count 0 2006.173.22:10:54.07#ibcon#first serial, iclass 38, count 0 2006.173.22:10:54.07#ibcon#enter sib2, iclass 38, count 0 2006.173.22:10:54.07#ibcon#flushed, iclass 38, count 0 2006.173.22:10:54.07#ibcon#about to write, iclass 38, count 0 2006.173.22:10:54.07#ibcon#wrote, iclass 38, count 0 2006.173.22:10:54.07#ibcon#about to read 3, iclass 38, count 0 2006.173.22:10:54.09#ibcon#read 3, iclass 38, count 0 2006.173.22:10:54.09#ibcon#about to read 4, iclass 38, count 0 2006.173.22:10:54.09#ibcon#read 4, iclass 38, count 0 2006.173.22:10:54.09#ibcon#about to read 5, iclass 38, count 0 2006.173.22:10:54.09#ibcon#read 5, iclass 38, count 0 2006.173.22:10:54.09#ibcon#about to read 6, iclass 38, count 0 2006.173.22:10:54.09#ibcon#read 6, iclass 38, count 0 2006.173.22:10:54.09#ibcon#end of sib2, iclass 38, count 0 2006.173.22:10:54.09#ibcon#*mode == 0, iclass 38, count 0 2006.173.22:10:54.09#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.22:10:54.09#ibcon#[27=USB\r\n] 2006.173.22:10:54.09#ibcon#*before write, iclass 38, count 0 2006.173.22:10:54.09#ibcon#enter sib2, iclass 38, count 0 2006.173.22:10:54.09#ibcon#flushed, iclass 38, count 0 2006.173.22:10:54.09#ibcon#about to write, iclass 38, count 0 2006.173.22:10:54.09#ibcon#wrote, iclass 38, count 0 2006.173.22:10:54.09#ibcon#about to read 3, iclass 38, count 0 2006.173.22:10:54.12#ibcon#read 3, iclass 38, count 0 2006.173.22:10:54.12#ibcon#about to read 4, iclass 38, count 0 2006.173.22:10:54.12#ibcon#read 4, iclass 38, count 0 2006.173.22:10:54.12#ibcon#about to read 5, iclass 38, count 0 2006.173.22:10:54.12#ibcon#read 5, iclass 38, count 0 2006.173.22:10:54.12#ibcon#about to read 6, iclass 38, count 0 2006.173.22:10:54.12#ibcon#read 6, iclass 38, count 0 2006.173.22:10:54.12#ibcon#end of sib2, iclass 38, count 0 2006.173.22:10:54.12#ibcon#*after write, iclass 38, count 0 2006.173.22:10:54.12#ibcon#*before return 0, iclass 38, count 0 2006.173.22:10:54.12#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.22:10:54.12#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.22:10:54.12#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.22:10:54.12#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.22:10:54.12$vck44/vblo=2,634.99 2006.173.22:10:54.12#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.22:10:54.12#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.22:10:54.12#ibcon#ireg 17 cls_cnt 0 2006.173.22:10:54.12#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.22:10:54.12#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.22:10:54.12#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.22:10:54.12#ibcon#enter wrdev, iclass 40, count 0 2006.173.22:10:54.12#ibcon#first serial, iclass 40, count 0 2006.173.22:10:54.12#ibcon#enter sib2, iclass 40, count 0 2006.173.22:10:54.12#ibcon#flushed, iclass 40, count 0 2006.173.22:10:54.12#ibcon#about to write, iclass 40, count 0 2006.173.22:10:54.12#ibcon#wrote, iclass 40, count 0 2006.173.22:10:54.12#ibcon#about to read 3, iclass 40, count 0 2006.173.22:10:54.14#ibcon#read 3, iclass 40, count 0 2006.173.22:10:54.14#ibcon#about to read 4, iclass 40, count 0 2006.173.22:10:54.14#ibcon#read 4, iclass 40, count 0 2006.173.22:10:54.14#ibcon#about to read 5, iclass 40, count 0 2006.173.22:10:54.14#ibcon#read 5, iclass 40, count 0 2006.173.22:10:54.14#ibcon#about to read 6, iclass 40, count 0 2006.173.22:10:54.14#ibcon#read 6, iclass 40, count 0 2006.173.22:10:54.14#ibcon#end of sib2, iclass 40, count 0 2006.173.22:10:54.14#ibcon#*mode == 0, iclass 40, count 0 2006.173.22:10:54.14#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.22:10:54.14#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.22:10:54.14#ibcon#*before write, iclass 40, count 0 2006.173.22:10:54.14#ibcon#enter sib2, iclass 40, count 0 2006.173.22:10:54.14#ibcon#flushed, iclass 40, count 0 2006.173.22:10:54.14#ibcon#about to write, iclass 40, count 0 2006.173.22:10:54.14#ibcon#wrote, iclass 40, count 0 2006.173.22:10:54.14#ibcon#about to read 3, iclass 40, count 0 2006.173.22:10:54.18#ibcon#read 3, iclass 40, count 0 2006.173.22:10:54.18#ibcon#about to read 4, iclass 40, count 0 2006.173.22:10:54.18#ibcon#read 4, iclass 40, count 0 2006.173.22:10:54.18#ibcon#about to read 5, iclass 40, count 0 2006.173.22:10:54.18#ibcon#read 5, iclass 40, count 0 2006.173.22:10:54.18#ibcon#about to read 6, iclass 40, count 0 2006.173.22:10:54.18#ibcon#read 6, iclass 40, count 0 2006.173.22:10:54.18#ibcon#end of sib2, iclass 40, count 0 2006.173.22:10:54.18#ibcon#*after write, iclass 40, count 0 2006.173.22:10:54.18#ibcon#*before return 0, iclass 40, count 0 2006.173.22:10:54.18#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.22:10:54.18#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.22:10:54.18#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.22:10:54.18#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.22:10:54.18$vck44/vb=2,4 2006.173.22:10:54.18#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.22:10:54.18#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.22:10:54.18#ibcon#ireg 11 cls_cnt 2 2006.173.22:10:54.18#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.22:10:54.24#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.22:10:54.24#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.22:10:54.24#ibcon#enter wrdev, iclass 4, count 2 2006.173.22:10:54.24#ibcon#first serial, iclass 4, count 2 2006.173.22:10:54.24#ibcon#enter sib2, iclass 4, count 2 2006.173.22:10:54.24#ibcon#flushed, iclass 4, count 2 2006.173.22:10:54.24#ibcon#about to write, iclass 4, count 2 2006.173.22:10:54.24#ibcon#wrote, iclass 4, count 2 2006.173.22:10:54.24#ibcon#about to read 3, iclass 4, count 2 2006.173.22:10:54.26#ibcon#read 3, iclass 4, count 2 2006.173.22:10:54.26#ibcon#about to read 4, iclass 4, count 2 2006.173.22:10:54.26#ibcon#read 4, iclass 4, count 2 2006.173.22:10:54.26#ibcon#about to read 5, iclass 4, count 2 2006.173.22:10:54.26#ibcon#read 5, iclass 4, count 2 2006.173.22:10:54.26#ibcon#about to read 6, iclass 4, count 2 2006.173.22:10:54.26#ibcon#read 6, iclass 4, count 2 2006.173.22:10:54.26#ibcon#end of sib2, iclass 4, count 2 2006.173.22:10:54.26#ibcon#*mode == 0, iclass 4, count 2 2006.173.22:10:54.26#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.22:10:54.26#ibcon#[27=AT02-04\r\n] 2006.173.22:10:54.26#ibcon#*before write, iclass 4, count 2 2006.173.22:10:54.26#ibcon#enter sib2, iclass 4, count 2 2006.173.22:10:54.26#ibcon#flushed, iclass 4, count 2 2006.173.22:10:54.26#ibcon#about to write, iclass 4, count 2 2006.173.22:10:54.26#ibcon#wrote, iclass 4, count 2 2006.173.22:10:54.26#ibcon#about to read 3, iclass 4, count 2 2006.173.22:10:54.29#ibcon#read 3, iclass 4, count 2 2006.173.22:10:54.29#ibcon#about to read 4, iclass 4, count 2 2006.173.22:10:54.29#ibcon#read 4, iclass 4, count 2 2006.173.22:10:54.29#ibcon#about to read 5, iclass 4, count 2 2006.173.22:10:54.29#ibcon#read 5, iclass 4, count 2 2006.173.22:10:54.29#ibcon#about to read 6, iclass 4, count 2 2006.173.22:10:54.29#ibcon#read 6, iclass 4, count 2 2006.173.22:10:54.29#ibcon#end of sib2, iclass 4, count 2 2006.173.22:10:54.29#ibcon#*after write, iclass 4, count 2 2006.173.22:10:54.29#ibcon#*before return 0, iclass 4, count 2 2006.173.22:10:54.29#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.22:10:54.29#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.22:10:54.29#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.22:10:54.29#ibcon#ireg 7 cls_cnt 0 2006.173.22:10:54.29#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.22:10:54.41#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.22:10:54.41#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.22:10:54.41#ibcon#enter wrdev, iclass 4, count 0 2006.173.22:10:54.41#ibcon#first serial, iclass 4, count 0 2006.173.22:10:54.41#ibcon#enter sib2, iclass 4, count 0 2006.173.22:10:54.41#ibcon#flushed, iclass 4, count 0 2006.173.22:10:54.41#ibcon#about to write, iclass 4, count 0 2006.173.22:10:54.41#ibcon#wrote, iclass 4, count 0 2006.173.22:10:54.41#ibcon#about to read 3, iclass 4, count 0 2006.173.22:10:54.43#ibcon#read 3, iclass 4, count 0 2006.173.22:10:54.43#ibcon#about to read 4, iclass 4, count 0 2006.173.22:10:54.43#ibcon#read 4, iclass 4, count 0 2006.173.22:10:54.43#ibcon#about to read 5, iclass 4, count 0 2006.173.22:10:54.43#ibcon#read 5, iclass 4, count 0 2006.173.22:10:54.43#ibcon#about to read 6, iclass 4, count 0 2006.173.22:10:54.43#ibcon#read 6, iclass 4, count 0 2006.173.22:10:54.43#ibcon#end of sib2, iclass 4, count 0 2006.173.22:10:54.43#ibcon#*mode == 0, iclass 4, count 0 2006.173.22:10:54.43#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.22:10:54.43#ibcon#[27=USB\r\n] 2006.173.22:10:54.43#ibcon#*before write, iclass 4, count 0 2006.173.22:10:54.43#ibcon#enter sib2, iclass 4, count 0 2006.173.22:10:54.43#ibcon#flushed, iclass 4, count 0 2006.173.22:10:54.43#ibcon#about to write, iclass 4, count 0 2006.173.22:10:54.43#ibcon#wrote, iclass 4, count 0 2006.173.22:10:54.43#ibcon#about to read 3, iclass 4, count 0 2006.173.22:10:54.46#ibcon#read 3, iclass 4, count 0 2006.173.22:10:54.46#ibcon#about to read 4, iclass 4, count 0 2006.173.22:10:54.46#ibcon#read 4, iclass 4, count 0 2006.173.22:10:54.46#ibcon#about to read 5, iclass 4, count 0 2006.173.22:10:54.46#ibcon#read 5, iclass 4, count 0 2006.173.22:10:54.46#ibcon#about to read 6, iclass 4, count 0 2006.173.22:10:54.46#ibcon#read 6, iclass 4, count 0 2006.173.22:10:54.46#ibcon#end of sib2, iclass 4, count 0 2006.173.22:10:54.46#ibcon#*after write, iclass 4, count 0 2006.173.22:10:54.46#ibcon#*before return 0, iclass 4, count 0 2006.173.22:10:54.46#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.22:10:54.46#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.22:10:54.46#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.22:10:54.46#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.22:10:54.46$vck44/vblo=3,649.99 2006.173.22:10:54.46#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.22:10:54.46#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.22:10:54.46#ibcon#ireg 17 cls_cnt 0 2006.173.22:10:54.46#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.22:10:54.46#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.22:10:54.46#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.22:10:54.46#ibcon#enter wrdev, iclass 6, count 0 2006.173.22:10:54.46#ibcon#first serial, iclass 6, count 0 2006.173.22:10:54.46#ibcon#enter sib2, iclass 6, count 0 2006.173.22:10:54.46#ibcon#flushed, iclass 6, count 0 2006.173.22:10:54.46#ibcon#about to write, iclass 6, count 0 2006.173.22:10:54.46#ibcon#wrote, iclass 6, count 0 2006.173.22:10:54.46#ibcon#about to read 3, iclass 6, count 0 2006.173.22:10:54.48#ibcon#read 3, iclass 6, count 0 2006.173.22:10:54.48#ibcon#about to read 4, iclass 6, count 0 2006.173.22:10:54.48#ibcon#read 4, iclass 6, count 0 2006.173.22:10:54.48#ibcon#about to read 5, iclass 6, count 0 2006.173.22:10:54.48#ibcon#read 5, iclass 6, count 0 2006.173.22:10:54.48#ibcon#about to read 6, iclass 6, count 0 2006.173.22:10:54.48#ibcon#read 6, iclass 6, count 0 2006.173.22:10:54.48#ibcon#end of sib2, iclass 6, count 0 2006.173.22:10:54.48#ibcon#*mode == 0, iclass 6, count 0 2006.173.22:10:54.48#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.22:10:54.48#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.22:10:54.48#ibcon#*before write, iclass 6, count 0 2006.173.22:10:54.48#ibcon#enter sib2, iclass 6, count 0 2006.173.22:10:54.48#ibcon#flushed, iclass 6, count 0 2006.173.22:10:54.48#ibcon#about to write, iclass 6, count 0 2006.173.22:10:54.48#ibcon#wrote, iclass 6, count 0 2006.173.22:10:54.48#ibcon#about to read 3, iclass 6, count 0 2006.173.22:10:54.52#ibcon#read 3, iclass 6, count 0 2006.173.22:10:54.52#ibcon#about to read 4, iclass 6, count 0 2006.173.22:10:54.52#ibcon#read 4, iclass 6, count 0 2006.173.22:10:54.52#ibcon#about to read 5, iclass 6, count 0 2006.173.22:10:54.52#ibcon#read 5, iclass 6, count 0 2006.173.22:10:54.52#ibcon#about to read 6, iclass 6, count 0 2006.173.22:10:54.52#ibcon#read 6, iclass 6, count 0 2006.173.22:10:54.52#ibcon#end of sib2, iclass 6, count 0 2006.173.22:10:54.52#ibcon#*after write, iclass 6, count 0 2006.173.22:10:54.52#ibcon#*before return 0, iclass 6, count 0 2006.173.22:10:54.52#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.22:10:54.52#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.22:10:54.52#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.22:10:54.52#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.22:10:54.52$vck44/vb=3,4 2006.173.22:10:54.52#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.22:10:54.52#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.22:10:54.52#ibcon#ireg 11 cls_cnt 2 2006.173.22:10:54.52#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.22:10:54.58#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.22:10:54.58#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.22:10:54.58#ibcon#enter wrdev, iclass 10, count 2 2006.173.22:10:54.58#ibcon#first serial, iclass 10, count 2 2006.173.22:10:54.58#ibcon#enter sib2, iclass 10, count 2 2006.173.22:10:54.58#ibcon#flushed, iclass 10, count 2 2006.173.22:10:54.58#ibcon#about to write, iclass 10, count 2 2006.173.22:10:54.58#ibcon#wrote, iclass 10, count 2 2006.173.22:10:54.58#ibcon#about to read 3, iclass 10, count 2 2006.173.22:10:54.60#ibcon#read 3, iclass 10, count 2 2006.173.22:10:54.60#ibcon#about to read 4, iclass 10, count 2 2006.173.22:10:54.60#ibcon#read 4, iclass 10, count 2 2006.173.22:10:54.60#ibcon#about to read 5, iclass 10, count 2 2006.173.22:10:54.60#ibcon#read 5, iclass 10, count 2 2006.173.22:10:54.60#ibcon#about to read 6, iclass 10, count 2 2006.173.22:10:54.60#ibcon#read 6, iclass 10, count 2 2006.173.22:10:54.60#ibcon#end of sib2, iclass 10, count 2 2006.173.22:10:54.60#ibcon#*mode == 0, iclass 10, count 2 2006.173.22:10:54.60#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.22:10:54.60#ibcon#[27=AT03-04\r\n] 2006.173.22:10:54.60#ibcon#*before write, iclass 10, count 2 2006.173.22:10:54.60#ibcon#enter sib2, iclass 10, count 2 2006.173.22:10:54.60#ibcon#flushed, iclass 10, count 2 2006.173.22:10:54.60#ibcon#about to write, iclass 10, count 2 2006.173.22:10:54.60#ibcon#wrote, iclass 10, count 2 2006.173.22:10:54.60#ibcon#about to read 3, iclass 10, count 2 2006.173.22:10:54.63#ibcon#read 3, iclass 10, count 2 2006.173.22:10:54.63#ibcon#about to read 4, iclass 10, count 2 2006.173.22:10:54.63#ibcon#read 4, iclass 10, count 2 2006.173.22:10:54.63#ibcon#about to read 5, iclass 10, count 2 2006.173.22:10:54.63#ibcon#read 5, iclass 10, count 2 2006.173.22:10:54.63#ibcon#about to read 6, iclass 10, count 2 2006.173.22:10:54.63#ibcon#read 6, iclass 10, count 2 2006.173.22:10:54.63#ibcon#end of sib2, iclass 10, count 2 2006.173.22:10:54.63#ibcon#*after write, iclass 10, count 2 2006.173.22:10:54.63#ibcon#*before return 0, iclass 10, count 2 2006.173.22:10:54.63#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.22:10:54.63#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.22:10:54.63#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.22:10:54.63#ibcon#ireg 7 cls_cnt 0 2006.173.22:10:54.63#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.22:10:54.75#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.22:10:54.75#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.22:10:54.75#ibcon#enter wrdev, iclass 10, count 0 2006.173.22:10:54.75#ibcon#first serial, iclass 10, count 0 2006.173.22:10:54.75#ibcon#enter sib2, iclass 10, count 0 2006.173.22:10:54.75#ibcon#flushed, iclass 10, count 0 2006.173.22:10:54.75#ibcon#about to write, iclass 10, count 0 2006.173.22:10:54.75#ibcon#wrote, iclass 10, count 0 2006.173.22:10:54.75#ibcon#about to read 3, iclass 10, count 0 2006.173.22:10:54.77#ibcon#read 3, iclass 10, count 0 2006.173.22:10:54.77#ibcon#about to read 4, iclass 10, count 0 2006.173.22:10:54.77#ibcon#read 4, iclass 10, count 0 2006.173.22:10:54.77#ibcon#about to read 5, iclass 10, count 0 2006.173.22:10:54.77#ibcon#read 5, iclass 10, count 0 2006.173.22:10:54.77#ibcon#about to read 6, iclass 10, count 0 2006.173.22:10:54.77#ibcon#read 6, iclass 10, count 0 2006.173.22:10:54.77#ibcon#end of sib2, iclass 10, count 0 2006.173.22:10:54.77#ibcon#*mode == 0, iclass 10, count 0 2006.173.22:10:54.77#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.22:10:54.77#ibcon#[27=USB\r\n] 2006.173.22:10:54.77#ibcon#*before write, iclass 10, count 0 2006.173.22:10:54.77#ibcon#enter sib2, iclass 10, count 0 2006.173.22:10:54.77#ibcon#flushed, iclass 10, count 0 2006.173.22:10:54.77#ibcon#about to write, iclass 10, count 0 2006.173.22:10:54.77#ibcon#wrote, iclass 10, count 0 2006.173.22:10:54.77#ibcon#about to read 3, iclass 10, count 0 2006.173.22:10:54.80#ibcon#read 3, iclass 10, count 0 2006.173.22:10:54.80#ibcon#about to read 4, iclass 10, count 0 2006.173.22:10:54.80#ibcon#read 4, iclass 10, count 0 2006.173.22:10:54.80#ibcon#about to read 5, iclass 10, count 0 2006.173.22:10:54.80#ibcon#read 5, iclass 10, count 0 2006.173.22:10:54.80#ibcon#about to read 6, iclass 10, count 0 2006.173.22:10:54.80#ibcon#read 6, iclass 10, count 0 2006.173.22:10:54.80#ibcon#end of sib2, iclass 10, count 0 2006.173.22:10:54.80#ibcon#*after write, iclass 10, count 0 2006.173.22:10:54.80#ibcon#*before return 0, iclass 10, count 0 2006.173.22:10:54.80#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.22:10:54.80#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.22:10:54.80#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.22:10:54.80#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.22:10:54.80$vck44/vblo=4,679.99 2006.173.22:10:54.80#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.22:10:54.80#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.22:10:54.80#ibcon#ireg 17 cls_cnt 0 2006.173.22:10:54.80#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.22:10:54.80#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.22:10:54.80#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.22:10:54.80#ibcon#enter wrdev, iclass 12, count 0 2006.173.22:10:54.80#ibcon#first serial, iclass 12, count 0 2006.173.22:10:54.80#ibcon#enter sib2, iclass 12, count 0 2006.173.22:10:54.80#ibcon#flushed, iclass 12, count 0 2006.173.22:10:54.80#ibcon#about to write, iclass 12, count 0 2006.173.22:10:54.80#ibcon#wrote, iclass 12, count 0 2006.173.22:10:54.80#ibcon#about to read 3, iclass 12, count 0 2006.173.22:10:54.82#ibcon#read 3, iclass 12, count 0 2006.173.22:10:54.82#ibcon#about to read 4, iclass 12, count 0 2006.173.22:10:54.82#ibcon#read 4, iclass 12, count 0 2006.173.22:10:54.82#ibcon#about to read 5, iclass 12, count 0 2006.173.22:10:54.82#ibcon#read 5, iclass 12, count 0 2006.173.22:10:54.82#ibcon#about to read 6, iclass 12, count 0 2006.173.22:10:54.82#ibcon#read 6, iclass 12, count 0 2006.173.22:10:54.82#ibcon#end of sib2, iclass 12, count 0 2006.173.22:10:54.82#ibcon#*mode == 0, iclass 12, count 0 2006.173.22:10:54.82#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.22:10:54.82#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.22:10:54.82#ibcon#*before write, iclass 12, count 0 2006.173.22:10:54.82#ibcon#enter sib2, iclass 12, count 0 2006.173.22:10:54.82#ibcon#flushed, iclass 12, count 0 2006.173.22:10:54.82#ibcon#about to write, iclass 12, count 0 2006.173.22:10:54.82#ibcon#wrote, iclass 12, count 0 2006.173.22:10:54.82#ibcon#about to read 3, iclass 12, count 0 2006.173.22:10:54.86#ibcon#read 3, iclass 12, count 0 2006.173.22:10:54.86#ibcon#about to read 4, iclass 12, count 0 2006.173.22:10:54.86#ibcon#read 4, iclass 12, count 0 2006.173.22:10:54.86#ibcon#about to read 5, iclass 12, count 0 2006.173.22:10:54.86#ibcon#read 5, iclass 12, count 0 2006.173.22:10:54.86#ibcon#about to read 6, iclass 12, count 0 2006.173.22:10:54.86#ibcon#read 6, iclass 12, count 0 2006.173.22:10:54.86#ibcon#end of sib2, iclass 12, count 0 2006.173.22:10:54.86#ibcon#*after write, iclass 12, count 0 2006.173.22:10:54.86#ibcon#*before return 0, iclass 12, count 0 2006.173.22:10:54.86#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.22:10:54.86#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.22:10:54.86#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.22:10:54.86#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.22:10:54.86$vck44/vb=4,4 2006.173.22:10:54.86#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.22:10:54.86#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.22:10:54.86#ibcon#ireg 11 cls_cnt 2 2006.173.22:10:54.86#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.22:10:54.92#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.22:10:54.92#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.22:10:54.92#ibcon#enter wrdev, iclass 14, count 2 2006.173.22:10:54.92#ibcon#first serial, iclass 14, count 2 2006.173.22:10:54.92#ibcon#enter sib2, iclass 14, count 2 2006.173.22:10:54.92#ibcon#flushed, iclass 14, count 2 2006.173.22:10:54.92#ibcon#about to write, iclass 14, count 2 2006.173.22:10:54.92#ibcon#wrote, iclass 14, count 2 2006.173.22:10:54.92#ibcon#about to read 3, iclass 14, count 2 2006.173.22:10:54.94#ibcon#read 3, iclass 14, count 2 2006.173.22:10:54.94#ibcon#about to read 4, iclass 14, count 2 2006.173.22:10:54.94#ibcon#read 4, iclass 14, count 2 2006.173.22:10:54.94#ibcon#about to read 5, iclass 14, count 2 2006.173.22:10:54.94#ibcon#read 5, iclass 14, count 2 2006.173.22:10:54.94#ibcon#about to read 6, iclass 14, count 2 2006.173.22:10:54.94#ibcon#read 6, iclass 14, count 2 2006.173.22:10:54.94#ibcon#end of sib2, iclass 14, count 2 2006.173.22:10:54.94#ibcon#*mode == 0, iclass 14, count 2 2006.173.22:10:54.94#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.22:10:54.94#ibcon#[27=AT04-04\r\n] 2006.173.22:10:54.94#ibcon#*before write, iclass 14, count 2 2006.173.22:10:54.94#ibcon#enter sib2, iclass 14, count 2 2006.173.22:10:54.94#ibcon#flushed, iclass 14, count 2 2006.173.22:10:54.94#ibcon#about to write, iclass 14, count 2 2006.173.22:10:54.94#ibcon#wrote, iclass 14, count 2 2006.173.22:10:54.94#ibcon#about to read 3, iclass 14, count 2 2006.173.22:10:54.97#ibcon#read 3, iclass 14, count 2 2006.173.22:10:54.97#ibcon#about to read 4, iclass 14, count 2 2006.173.22:10:54.97#ibcon#read 4, iclass 14, count 2 2006.173.22:10:54.97#ibcon#about to read 5, iclass 14, count 2 2006.173.22:10:54.97#ibcon#read 5, iclass 14, count 2 2006.173.22:10:54.97#ibcon#about to read 6, iclass 14, count 2 2006.173.22:10:54.97#ibcon#read 6, iclass 14, count 2 2006.173.22:10:54.97#ibcon#end of sib2, iclass 14, count 2 2006.173.22:10:54.97#ibcon#*after write, iclass 14, count 2 2006.173.22:10:54.97#ibcon#*before return 0, iclass 14, count 2 2006.173.22:10:54.97#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.22:10:54.97#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.22:10:54.97#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.22:10:54.97#ibcon#ireg 7 cls_cnt 0 2006.173.22:10:54.97#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.22:10:55.09#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.22:10:55.09#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.22:10:55.09#ibcon#enter wrdev, iclass 14, count 0 2006.173.22:10:55.09#ibcon#first serial, iclass 14, count 0 2006.173.22:10:55.09#ibcon#enter sib2, iclass 14, count 0 2006.173.22:10:55.09#ibcon#flushed, iclass 14, count 0 2006.173.22:10:55.09#ibcon#about to write, iclass 14, count 0 2006.173.22:10:55.09#ibcon#wrote, iclass 14, count 0 2006.173.22:10:55.09#ibcon#about to read 3, iclass 14, count 0 2006.173.22:10:55.11#ibcon#read 3, iclass 14, count 0 2006.173.22:10:55.11#ibcon#about to read 4, iclass 14, count 0 2006.173.22:10:55.11#ibcon#read 4, iclass 14, count 0 2006.173.22:10:55.11#ibcon#about to read 5, iclass 14, count 0 2006.173.22:10:55.11#ibcon#read 5, iclass 14, count 0 2006.173.22:10:55.11#ibcon#about to read 6, iclass 14, count 0 2006.173.22:10:55.11#ibcon#read 6, iclass 14, count 0 2006.173.22:10:55.11#ibcon#end of sib2, iclass 14, count 0 2006.173.22:10:55.11#ibcon#*mode == 0, iclass 14, count 0 2006.173.22:10:55.11#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.22:10:55.11#ibcon#[27=USB\r\n] 2006.173.22:10:55.11#ibcon#*before write, iclass 14, count 0 2006.173.22:10:55.11#ibcon#enter sib2, iclass 14, count 0 2006.173.22:10:55.11#ibcon#flushed, iclass 14, count 0 2006.173.22:10:55.11#ibcon#about to write, iclass 14, count 0 2006.173.22:10:55.11#ibcon#wrote, iclass 14, count 0 2006.173.22:10:55.11#ibcon#about to read 3, iclass 14, count 0 2006.173.22:10:55.14#ibcon#read 3, iclass 14, count 0 2006.173.22:10:55.14#ibcon#about to read 4, iclass 14, count 0 2006.173.22:10:55.14#ibcon#read 4, iclass 14, count 0 2006.173.22:10:55.14#ibcon#about to read 5, iclass 14, count 0 2006.173.22:10:55.14#ibcon#read 5, iclass 14, count 0 2006.173.22:10:55.14#ibcon#about to read 6, iclass 14, count 0 2006.173.22:10:55.14#ibcon#read 6, iclass 14, count 0 2006.173.22:10:55.14#ibcon#end of sib2, iclass 14, count 0 2006.173.22:10:55.14#ibcon#*after write, iclass 14, count 0 2006.173.22:10:55.14#ibcon#*before return 0, iclass 14, count 0 2006.173.22:10:55.14#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.22:10:55.14#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.22:10:55.14#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.22:10:55.14#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.22:10:55.14$vck44/vblo=5,709.99 2006.173.22:10:55.14#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.22:10:55.14#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.22:10:55.14#ibcon#ireg 17 cls_cnt 0 2006.173.22:10:55.14#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.22:10:55.14#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.22:10:55.14#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.22:10:55.14#ibcon#enter wrdev, iclass 16, count 0 2006.173.22:10:55.14#ibcon#first serial, iclass 16, count 0 2006.173.22:10:55.14#ibcon#enter sib2, iclass 16, count 0 2006.173.22:10:55.14#ibcon#flushed, iclass 16, count 0 2006.173.22:10:55.14#ibcon#about to write, iclass 16, count 0 2006.173.22:10:55.14#ibcon#wrote, iclass 16, count 0 2006.173.22:10:55.14#ibcon#about to read 3, iclass 16, count 0 2006.173.22:10:55.16#ibcon#read 3, iclass 16, count 0 2006.173.22:10:55.16#ibcon#about to read 4, iclass 16, count 0 2006.173.22:10:55.16#ibcon#read 4, iclass 16, count 0 2006.173.22:10:55.16#ibcon#about to read 5, iclass 16, count 0 2006.173.22:10:55.16#ibcon#read 5, iclass 16, count 0 2006.173.22:10:55.16#ibcon#about to read 6, iclass 16, count 0 2006.173.22:10:55.16#ibcon#read 6, iclass 16, count 0 2006.173.22:10:55.16#ibcon#end of sib2, iclass 16, count 0 2006.173.22:10:55.16#ibcon#*mode == 0, iclass 16, count 0 2006.173.22:10:55.16#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.22:10:55.16#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.22:10:55.16#ibcon#*before write, iclass 16, count 0 2006.173.22:10:55.16#ibcon#enter sib2, iclass 16, count 0 2006.173.22:10:55.16#ibcon#flushed, iclass 16, count 0 2006.173.22:10:55.16#ibcon#about to write, iclass 16, count 0 2006.173.22:10:55.16#ibcon#wrote, iclass 16, count 0 2006.173.22:10:55.16#ibcon#about to read 3, iclass 16, count 0 2006.173.22:10:55.20#ibcon#read 3, iclass 16, count 0 2006.173.22:10:55.20#ibcon#about to read 4, iclass 16, count 0 2006.173.22:10:55.20#ibcon#read 4, iclass 16, count 0 2006.173.22:10:55.20#ibcon#about to read 5, iclass 16, count 0 2006.173.22:10:55.20#ibcon#read 5, iclass 16, count 0 2006.173.22:10:55.20#ibcon#about to read 6, iclass 16, count 0 2006.173.22:10:55.20#ibcon#read 6, iclass 16, count 0 2006.173.22:10:55.20#ibcon#end of sib2, iclass 16, count 0 2006.173.22:10:55.20#ibcon#*after write, iclass 16, count 0 2006.173.22:10:55.20#ibcon#*before return 0, iclass 16, count 0 2006.173.22:10:55.20#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.22:10:55.20#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.22:10:55.20#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.22:10:55.20#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.22:10:55.20$vck44/vb=5,4 2006.173.22:10:55.20#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.22:10:55.20#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.22:10:55.20#ibcon#ireg 11 cls_cnt 2 2006.173.22:10:55.20#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.22:10:55.26#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.22:10:55.26#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.22:10:55.26#ibcon#enter wrdev, iclass 18, count 2 2006.173.22:10:55.26#ibcon#first serial, iclass 18, count 2 2006.173.22:10:55.26#ibcon#enter sib2, iclass 18, count 2 2006.173.22:10:55.26#ibcon#flushed, iclass 18, count 2 2006.173.22:10:55.26#ibcon#about to write, iclass 18, count 2 2006.173.22:10:55.26#ibcon#wrote, iclass 18, count 2 2006.173.22:10:55.26#ibcon#about to read 3, iclass 18, count 2 2006.173.22:10:55.28#ibcon#read 3, iclass 18, count 2 2006.173.22:10:55.28#ibcon#about to read 4, iclass 18, count 2 2006.173.22:10:55.28#ibcon#read 4, iclass 18, count 2 2006.173.22:10:55.28#ibcon#about to read 5, iclass 18, count 2 2006.173.22:10:55.28#ibcon#read 5, iclass 18, count 2 2006.173.22:10:55.28#ibcon#about to read 6, iclass 18, count 2 2006.173.22:10:55.28#ibcon#read 6, iclass 18, count 2 2006.173.22:10:55.28#ibcon#end of sib2, iclass 18, count 2 2006.173.22:10:55.28#ibcon#*mode == 0, iclass 18, count 2 2006.173.22:10:55.28#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.22:10:55.28#ibcon#[27=AT05-04\r\n] 2006.173.22:10:55.28#ibcon#*before write, iclass 18, count 2 2006.173.22:10:55.28#ibcon#enter sib2, iclass 18, count 2 2006.173.22:10:55.28#ibcon#flushed, iclass 18, count 2 2006.173.22:10:55.28#ibcon#about to write, iclass 18, count 2 2006.173.22:10:55.28#ibcon#wrote, iclass 18, count 2 2006.173.22:10:55.28#ibcon#about to read 3, iclass 18, count 2 2006.173.22:10:55.31#ibcon#read 3, iclass 18, count 2 2006.173.22:10:55.31#ibcon#about to read 4, iclass 18, count 2 2006.173.22:10:55.31#ibcon#read 4, iclass 18, count 2 2006.173.22:10:55.31#ibcon#about to read 5, iclass 18, count 2 2006.173.22:10:55.31#ibcon#read 5, iclass 18, count 2 2006.173.22:10:55.31#ibcon#about to read 6, iclass 18, count 2 2006.173.22:10:55.31#ibcon#read 6, iclass 18, count 2 2006.173.22:10:55.31#ibcon#end of sib2, iclass 18, count 2 2006.173.22:10:55.31#ibcon#*after write, iclass 18, count 2 2006.173.22:10:55.31#ibcon#*before return 0, iclass 18, count 2 2006.173.22:10:55.31#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.22:10:55.31#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.22:10:55.31#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.22:10:55.31#ibcon#ireg 7 cls_cnt 0 2006.173.22:10:55.31#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.22:10:55.43#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.22:10:55.43#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.22:10:55.43#ibcon#enter wrdev, iclass 18, count 0 2006.173.22:10:55.43#ibcon#first serial, iclass 18, count 0 2006.173.22:10:55.43#ibcon#enter sib2, iclass 18, count 0 2006.173.22:10:55.43#ibcon#flushed, iclass 18, count 0 2006.173.22:10:55.43#ibcon#about to write, iclass 18, count 0 2006.173.22:10:55.43#ibcon#wrote, iclass 18, count 0 2006.173.22:10:55.43#ibcon#about to read 3, iclass 18, count 0 2006.173.22:10:55.45#ibcon#read 3, iclass 18, count 0 2006.173.22:10:55.45#ibcon#about to read 4, iclass 18, count 0 2006.173.22:10:55.45#ibcon#read 4, iclass 18, count 0 2006.173.22:10:55.45#ibcon#about to read 5, iclass 18, count 0 2006.173.22:10:55.45#ibcon#read 5, iclass 18, count 0 2006.173.22:10:55.45#ibcon#about to read 6, iclass 18, count 0 2006.173.22:10:55.45#ibcon#read 6, iclass 18, count 0 2006.173.22:10:55.45#ibcon#end of sib2, iclass 18, count 0 2006.173.22:10:55.45#ibcon#*mode == 0, iclass 18, count 0 2006.173.22:10:55.45#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.22:10:55.45#ibcon#[27=USB\r\n] 2006.173.22:10:55.45#ibcon#*before write, iclass 18, count 0 2006.173.22:10:55.45#ibcon#enter sib2, iclass 18, count 0 2006.173.22:10:55.45#ibcon#flushed, iclass 18, count 0 2006.173.22:10:55.45#ibcon#about to write, iclass 18, count 0 2006.173.22:10:55.45#ibcon#wrote, iclass 18, count 0 2006.173.22:10:55.45#ibcon#about to read 3, iclass 18, count 0 2006.173.22:10:55.48#ibcon#read 3, iclass 18, count 0 2006.173.22:10:55.48#ibcon#about to read 4, iclass 18, count 0 2006.173.22:10:55.48#ibcon#read 4, iclass 18, count 0 2006.173.22:10:55.48#ibcon#about to read 5, iclass 18, count 0 2006.173.22:10:55.48#ibcon#read 5, iclass 18, count 0 2006.173.22:10:55.48#ibcon#about to read 6, iclass 18, count 0 2006.173.22:10:55.48#ibcon#read 6, iclass 18, count 0 2006.173.22:10:55.48#ibcon#end of sib2, iclass 18, count 0 2006.173.22:10:55.48#ibcon#*after write, iclass 18, count 0 2006.173.22:10:55.48#ibcon#*before return 0, iclass 18, count 0 2006.173.22:10:55.48#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.22:10:55.48#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.22:10:55.48#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.22:10:55.48#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.22:10:55.48$vck44/vblo=6,719.99 2006.173.22:10:55.48#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.22:10:55.48#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.22:10:55.48#ibcon#ireg 17 cls_cnt 0 2006.173.22:10:55.48#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.22:10:55.48#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.22:10:55.48#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.22:10:55.48#ibcon#enter wrdev, iclass 20, count 0 2006.173.22:10:55.48#ibcon#first serial, iclass 20, count 0 2006.173.22:10:55.48#ibcon#enter sib2, iclass 20, count 0 2006.173.22:10:55.48#ibcon#flushed, iclass 20, count 0 2006.173.22:10:55.48#ibcon#about to write, iclass 20, count 0 2006.173.22:10:55.48#ibcon#wrote, iclass 20, count 0 2006.173.22:10:55.48#ibcon#about to read 3, iclass 20, count 0 2006.173.22:10:55.50#ibcon#read 3, iclass 20, count 0 2006.173.22:10:55.50#ibcon#about to read 4, iclass 20, count 0 2006.173.22:10:55.50#ibcon#read 4, iclass 20, count 0 2006.173.22:10:55.50#ibcon#about to read 5, iclass 20, count 0 2006.173.22:10:55.50#ibcon#read 5, iclass 20, count 0 2006.173.22:10:55.50#ibcon#about to read 6, iclass 20, count 0 2006.173.22:10:55.50#ibcon#read 6, iclass 20, count 0 2006.173.22:10:55.50#ibcon#end of sib2, iclass 20, count 0 2006.173.22:10:55.50#ibcon#*mode == 0, iclass 20, count 0 2006.173.22:10:55.50#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.22:10:55.50#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.22:10:55.50#ibcon#*before write, iclass 20, count 0 2006.173.22:10:55.50#ibcon#enter sib2, iclass 20, count 0 2006.173.22:10:55.50#ibcon#flushed, iclass 20, count 0 2006.173.22:10:55.50#ibcon#about to write, iclass 20, count 0 2006.173.22:10:55.50#ibcon#wrote, iclass 20, count 0 2006.173.22:10:55.50#ibcon#about to read 3, iclass 20, count 0 2006.173.22:10:55.54#ibcon#read 3, iclass 20, count 0 2006.173.22:10:55.54#ibcon#about to read 4, iclass 20, count 0 2006.173.22:10:55.54#ibcon#read 4, iclass 20, count 0 2006.173.22:10:55.54#ibcon#about to read 5, iclass 20, count 0 2006.173.22:10:55.54#ibcon#read 5, iclass 20, count 0 2006.173.22:10:55.54#ibcon#about to read 6, iclass 20, count 0 2006.173.22:10:55.54#ibcon#read 6, iclass 20, count 0 2006.173.22:10:55.54#ibcon#end of sib2, iclass 20, count 0 2006.173.22:10:55.54#ibcon#*after write, iclass 20, count 0 2006.173.22:10:55.54#ibcon#*before return 0, iclass 20, count 0 2006.173.22:10:55.54#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.22:10:55.54#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.22:10:55.54#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.22:10:55.54#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.22:10:55.54$vck44/vb=6,4 2006.173.22:10:55.54#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.22:10:55.54#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.22:10:55.54#ibcon#ireg 11 cls_cnt 2 2006.173.22:10:55.54#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.22:10:55.60#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.22:10:55.60#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.22:10:55.60#ibcon#enter wrdev, iclass 22, count 2 2006.173.22:10:55.60#ibcon#first serial, iclass 22, count 2 2006.173.22:10:55.60#ibcon#enter sib2, iclass 22, count 2 2006.173.22:10:55.60#ibcon#flushed, iclass 22, count 2 2006.173.22:10:55.60#ibcon#about to write, iclass 22, count 2 2006.173.22:10:55.60#ibcon#wrote, iclass 22, count 2 2006.173.22:10:55.60#ibcon#about to read 3, iclass 22, count 2 2006.173.22:10:55.62#ibcon#read 3, iclass 22, count 2 2006.173.22:10:55.62#ibcon#about to read 4, iclass 22, count 2 2006.173.22:10:55.62#ibcon#read 4, iclass 22, count 2 2006.173.22:10:55.62#ibcon#about to read 5, iclass 22, count 2 2006.173.22:10:55.62#ibcon#read 5, iclass 22, count 2 2006.173.22:10:55.62#ibcon#about to read 6, iclass 22, count 2 2006.173.22:10:55.62#ibcon#read 6, iclass 22, count 2 2006.173.22:10:55.62#ibcon#end of sib2, iclass 22, count 2 2006.173.22:10:55.62#ibcon#*mode == 0, iclass 22, count 2 2006.173.22:10:55.62#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.22:10:55.62#ibcon#[27=AT06-04\r\n] 2006.173.22:10:55.62#ibcon#*before write, iclass 22, count 2 2006.173.22:10:55.62#ibcon#enter sib2, iclass 22, count 2 2006.173.22:10:55.62#ibcon#flushed, iclass 22, count 2 2006.173.22:10:55.62#ibcon#about to write, iclass 22, count 2 2006.173.22:10:55.62#ibcon#wrote, iclass 22, count 2 2006.173.22:10:55.62#ibcon#about to read 3, iclass 22, count 2 2006.173.22:10:55.65#ibcon#read 3, iclass 22, count 2 2006.173.22:10:55.65#ibcon#about to read 4, iclass 22, count 2 2006.173.22:10:55.65#ibcon#read 4, iclass 22, count 2 2006.173.22:10:55.65#ibcon#about to read 5, iclass 22, count 2 2006.173.22:10:55.65#ibcon#read 5, iclass 22, count 2 2006.173.22:10:55.65#ibcon#about to read 6, iclass 22, count 2 2006.173.22:10:55.65#ibcon#read 6, iclass 22, count 2 2006.173.22:10:55.65#ibcon#end of sib2, iclass 22, count 2 2006.173.22:10:55.65#ibcon#*after write, iclass 22, count 2 2006.173.22:10:55.65#ibcon#*before return 0, iclass 22, count 2 2006.173.22:10:55.65#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.22:10:55.65#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.22:10:55.65#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.22:10:55.65#ibcon#ireg 7 cls_cnt 0 2006.173.22:10:55.65#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.22:10:55.77#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.22:10:55.77#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.22:10:55.77#ibcon#enter wrdev, iclass 22, count 0 2006.173.22:10:55.77#ibcon#first serial, iclass 22, count 0 2006.173.22:10:55.77#ibcon#enter sib2, iclass 22, count 0 2006.173.22:10:55.77#ibcon#flushed, iclass 22, count 0 2006.173.22:10:55.77#ibcon#about to write, iclass 22, count 0 2006.173.22:10:55.77#ibcon#wrote, iclass 22, count 0 2006.173.22:10:55.77#ibcon#about to read 3, iclass 22, count 0 2006.173.22:10:55.79#ibcon#read 3, iclass 22, count 0 2006.173.22:10:55.79#ibcon#about to read 4, iclass 22, count 0 2006.173.22:10:55.79#ibcon#read 4, iclass 22, count 0 2006.173.22:10:55.79#ibcon#about to read 5, iclass 22, count 0 2006.173.22:10:55.79#ibcon#read 5, iclass 22, count 0 2006.173.22:10:55.79#ibcon#about to read 6, iclass 22, count 0 2006.173.22:10:55.79#ibcon#read 6, iclass 22, count 0 2006.173.22:10:55.79#ibcon#end of sib2, iclass 22, count 0 2006.173.22:10:55.79#ibcon#*mode == 0, iclass 22, count 0 2006.173.22:10:55.79#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.22:10:55.79#ibcon#[27=USB\r\n] 2006.173.22:10:55.79#ibcon#*before write, iclass 22, count 0 2006.173.22:10:55.79#ibcon#enter sib2, iclass 22, count 0 2006.173.22:10:55.79#ibcon#flushed, iclass 22, count 0 2006.173.22:10:55.79#ibcon#about to write, iclass 22, count 0 2006.173.22:10:55.79#ibcon#wrote, iclass 22, count 0 2006.173.22:10:55.79#ibcon#about to read 3, iclass 22, count 0 2006.173.22:10:55.82#ibcon#read 3, iclass 22, count 0 2006.173.22:10:55.82#ibcon#about to read 4, iclass 22, count 0 2006.173.22:10:55.82#ibcon#read 4, iclass 22, count 0 2006.173.22:10:55.82#ibcon#about to read 5, iclass 22, count 0 2006.173.22:10:55.82#ibcon#read 5, iclass 22, count 0 2006.173.22:10:55.82#ibcon#about to read 6, iclass 22, count 0 2006.173.22:10:55.82#ibcon#read 6, iclass 22, count 0 2006.173.22:10:55.82#ibcon#end of sib2, iclass 22, count 0 2006.173.22:10:55.82#ibcon#*after write, iclass 22, count 0 2006.173.22:10:55.82#ibcon#*before return 0, iclass 22, count 0 2006.173.22:10:55.82#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.22:10:55.82#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.22:10:55.82#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.22:10:55.82#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.22:10:55.82$vck44/vblo=7,734.99 2006.173.22:10:55.82#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.22:10:55.82#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.22:10:55.82#ibcon#ireg 17 cls_cnt 0 2006.173.22:10:55.82#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.22:10:55.82#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.22:10:55.82#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.22:10:55.82#ibcon#enter wrdev, iclass 24, count 0 2006.173.22:10:55.82#ibcon#first serial, iclass 24, count 0 2006.173.22:10:55.82#ibcon#enter sib2, iclass 24, count 0 2006.173.22:10:55.82#ibcon#flushed, iclass 24, count 0 2006.173.22:10:55.82#ibcon#about to write, iclass 24, count 0 2006.173.22:10:55.82#ibcon#wrote, iclass 24, count 0 2006.173.22:10:55.82#ibcon#about to read 3, iclass 24, count 0 2006.173.22:10:55.84#ibcon#read 3, iclass 24, count 0 2006.173.22:10:55.84#ibcon#about to read 4, iclass 24, count 0 2006.173.22:10:55.84#ibcon#read 4, iclass 24, count 0 2006.173.22:10:55.84#ibcon#about to read 5, iclass 24, count 0 2006.173.22:10:55.84#ibcon#read 5, iclass 24, count 0 2006.173.22:10:55.84#ibcon#about to read 6, iclass 24, count 0 2006.173.22:10:55.84#ibcon#read 6, iclass 24, count 0 2006.173.22:10:55.84#ibcon#end of sib2, iclass 24, count 0 2006.173.22:10:55.84#ibcon#*mode == 0, iclass 24, count 0 2006.173.22:10:55.84#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.22:10:55.84#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.22:10:55.84#ibcon#*before write, iclass 24, count 0 2006.173.22:10:55.84#ibcon#enter sib2, iclass 24, count 0 2006.173.22:10:55.84#ibcon#flushed, iclass 24, count 0 2006.173.22:10:55.84#ibcon#about to write, iclass 24, count 0 2006.173.22:10:55.84#ibcon#wrote, iclass 24, count 0 2006.173.22:10:55.84#ibcon#about to read 3, iclass 24, count 0 2006.173.22:10:55.88#ibcon#read 3, iclass 24, count 0 2006.173.22:10:55.88#ibcon#about to read 4, iclass 24, count 0 2006.173.22:10:55.88#ibcon#read 4, iclass 24, count 0 2006.173.22:10:55.88#ibcon#about to read 5, iclass 24, count 0 2006.173.22:10:55.88#ibcon#read 5, iclass 24, count 0 2006.173.22:10:55.88#ibcon#about to read 6, iclass 24, count 0 2006.173.22:10:55.88#ibcon#read 6, iclass 24, count 0 2006.173.22:10:55.88#ibcon#end of sib2, iclass 24, count 0 2006.173.22:10:55.88#ibcon#*after write, iclass 24, count 0 2006.173.22:10:55.88#ibcon#*before return 0, iclass 24, count 0 2006.173.22:10:55.88#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.22:10:55.88#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.22:10:55.88#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.22:10:55.88#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.22:10:55.88$vck44/vb=7,4 2006.173.22:10:55.88#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.22:10:55.88#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.22:10:55.88#ibcon#ireg 11 cls_cnt 2 2006.173.22:10:55.88#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.22:10:55.94#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.22:10:55.94#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.22:10:55.94#ibcon#enter wrdev, iclass 26, count 2 2006.173.22:10:55.94#ibcon#first serial, iclass 26, count 2 2006.173.22:10:55.94#ibcon#enter sib2, iclass 26, count 2 2006.173.22:10:55.94#ibcon#flushed, iclass 26, count 2 2006.173.22:10:55.94#ibcon#about to write, iclass 26, count 2 2006.173.22:10:55.94#ibcon#wrote, iclass 26, count 2 2006.173.22:10:55.94#ibcon#about to read 3, iclass 26, count 2 2006.173.22:10:55.96#ibcon#read 3, iclass 26, count 2 2006.173.22:10:55.96#ibcon#about to read 4, iclass 26, count 2 2006.173.22:10:55.96#ibcon#read 4, iclass 26, count 2 2006.173.22:10:55.96#ibcon#about to read 5, iclass 26, count 2 2006.173.22:10:55.96#ibcon#read 5, iclass 26, count 2 2006.173.22:10:55.96#ibcon#about to read 6, iclass 26, count 2 2006.173.22:10:55.96#ibcon#read 6, iclass 26, count 2 2006.173.22:10:55.96#ibcon#end of sib2, iclass 26, count 2 2006.173.22:10:55.96#ibcon#*mode == 0, iclass 26, count 2 2006.173.22:10:55.96#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.22:10:55.96#ibcon#[27=AT07-04\r\n] 2006.173.22:10:55.96#ibcon#*before write, iclass 26, count 2 2006.173.22:10:55.96#ibcon#enter sib2, iclass 26, count 2 2006.173.22:10:55.96#ibcon#flushed, iclass 26, count 2 2006.173.22:10:55.96#ibcon#about to write, iclass 26, count 2 2006.173.22:10:55.96#ibcon#wrote, iclass 26, count 2 2006.173.22:10:55.96#ibcon#about to read 3, iclass 26, count 2 2006.173.22:10:55.99#ibcon#read 3, iclass 26, count 2 2006.173.22:10:55.99#ibcon#about to read 4, iclass 26, count 2 2006.173.22:10:55.99#ibcon#read 4, iclass 26, count 2 2006.173.22:10:55.99#ibcon#about to read 5, iclass 26, count 2 2006.173.22:10:55.99#ibcon#read 5, iclass 26, count 2 2006.173.22:10:55.99#ibcon#about to read 6, iclass 26, count 2 2006.173.22:10:55.99#ibcon#read 6, iclass 26, count 2 2006.173.22:10:55.99#ibcon#end of sib2, iclass 26, count 2 2006.173.22:10:55.99#ibcon#*after write, iclass 26, count 2 2006.173.22:10:55.99#ibcon#*before return 0, iclass 26, count 2 2006.173.22:10:55.99#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.22:10:55.99#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.22:10:55.99#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.22:10:55.99#ibcon#ireg 7 cls_cnt 0 2006.173.22:10:55.99#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.22:10:56.11#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.22:10:56.11#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.22:10:56.11#ibcon#enter wrdev, iclass 26, count 0 2006.173.22:10:56.11#ibcon#first serial, iclass 26, count 0 2006.173.22:10:56.11#ibcon#enter sib2, iclass 26, count 0 2006.173.22:10:56.11#ibcon#flushed, iclass 26, count 0 2006.173.22:10:56.11#ibcon#about to write, iclass 26, count 0 2006.173.22:10:56.11#ibcon#wrote, iclass 26, count 0 2006.173.22:10:56.11#ibcon#about to read 3, iclass 26, count 0 2006.173.22:10:56.13#ibcon#read 3, iclass 26, count 0 2006.173.22:10:56.13#ibcon#about to read 4, iclass 26, count 0 2006.173.22:10:56.13#ibcon#read 4, iclass 26, count 0 2006.173.22:10:56.13#ibcon#about to read 5, iclass 26, count 0 2006.173.22:10:56.13#ibcon#read 5, iclass 26, count 0 2006.173.22:10:56.13#ibcon#about to read 6, iclass 26, count 0 2006.173.22:10:56.13#ibcon#read 6, iclass 26, count 0 2006.173.22:10:56.13#ibcon#end of sib2, iclass 26, count 0 2006.173.22:10:56.13#ibcon#*mode == 0, iclass 26, count 0 2006.173.22:10:56.13#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.22:10:56.13#ibcon#[27=USB\r\n] 2006.173.22:10:56.13#ibcon#*before write, iclass 26, count 0 2006.173.22:10:56.13#ibcon#enter sib2, iclass 26, count 0 2006.173.22:10:56.13#ibcon#flushed, iclass 26, count 0 2006.173.22:10:56.13#ibcon#about to write, iclass 26, count 0 2006.173.22:10:56.13#ibcon#wrote, iclass 26, count 0 2006.173.22:10:56.13#ibcon#about to read 3, iclass 26, count 0 2006.173.22:10:56.16#ibcon#read 3, iclass 26, count 0 2006.173.22:10:56.16#ibcon#about to read 4, iclass 26, count 0 2006.173.22:10:56.16#ibcon#read 4, iclass 26, count 0 2006.173.22:10:56.16#ibcon#about to read 5, iclass 26, count 0 2006.173.22:10:56.16#ibcon#read 5, iclass 26, count 0 2006.173.22:10:56.16#ibcon#about to read 6, iclass 26, count 0 2006.173.22:10:56.16#ibcon#read 6, iclass 26, count 0 2006.173.22:10:56.16#ibcon#end of sib2, iclass 26, count 0 2006.173.22:10:56.16#ibcon#*after write, iclass 26, count 0 2006.173.22:10:56.16#ibcon#*before return 0, iclass 26, count 0 2006.173.22:10:56.16#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.22:10:56.16#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.22:10:56.16#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.22:10:56.16#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.22:10:56.16$vck44/vblo=8,744.99 2006.173.22:10:56.16#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.22:10:56.16#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.22:10:56.16#ibcon#ireg 17 cls_cnt 0 2006.173.22:10:56.16#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.22:10:56.16#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.22:10:56.16#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.22:10:56.16#ibcon#enter wrdev, iclass 28, count 0 2006.173.22:10:56.16#ibcon#first serial, iclass 28, count 0 2006.173.22:10:56.16#ibcon#enter sib2, iclass 28, count 0 2006.173.22:10:56.16#ibcon#flushed, iclass 28, count 0 2006.173.22:10:56.16#ibcon#about to write, iclass 28, count 0 2006.173.22:10:56.16#ibcon#wrote, iclass 28, count 0 2006.173.22:10:56.16#ibcon#about to read 3, iclass 28, count 0 2006.173.22:10:56.18#ibcon#read 3, iclass 28, count 0 2006.173.22:10:56.18#ibcon#about to read 4, iclass 28, count 0 2006.173.22:10:56.18#ibcon#read 4, iclass 28, count 0 2006.173.22:10:56.18#ibcon#about to read 5, iclass 28, count 0 2006.173.22:10:56.18#ibcon#read 5, iclass 28, count 0 2006.173.22:10:56.18#ibcon#about to read 6, iclass 28, count 0 2006.173.22:10:56.18#ibcon#read 6, iclass 28, count 0 2006.173.22:10:56.18#ibcon#end of sib2, iclass 28, count 0 2006.173.22:10:56.18#ibcon#*mode == 0, iclass 28, count 0 2006.173.22:10:56.18#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.22:10:56.18#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.22:10:56.18#ibcon#*before write, iclass 28, count 0 2006.173.22:10:56.18#ibcon#enter sib2, iclass 28, count 0 2006.173.22:10:56.18#ibcon#flushed, iclass 28, count 0 2006.173.22:10:56.18#ibcon#about to write, iclass 28, count 0 2006.173.22:10:56.18#ibcon#wrote, iclass 28, count 0 2006.173.22:10:56.18#ibcon#about to read 3, iclass 28, count 0 2006.173.22:10:56.22#ibcon#read 3, iclass 28, count 0 2006.173.22:10:56.22#ibcon#about to read 4, iclass 28, count 0 2006.173.22:10:56.22#ibcon#read 4, iclass 28, count 0 2006.173.22:10:56.22#ibcon#about to read 5, iclass 28, count 0 2006.173.22:10:56.22#ibcon#read 5, iclass 28, count 0 2006.173.22:10:56.22#ibcon#about to read 6, iclass 28, count 0 2006.173.22:10:56.22#ibcon#read 6, iclass 28, count 0 2006.173.22:10:56.22#ibcon#end of sib2, iclass 28, count 0 2006.173.22:10:56.22#ibcon#*after write, iclass 28, count 0 2006.173.22:10:56.22#ibcon#*before return 0, iclass 28, count 0 2006.173.22:10:56.22#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.22:10:56.22#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.22:10:56.22#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.22:10:56.22#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.22:10:56.22$vck44/vb=8,4 2006.173.22:10:56.22#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.22:10:56.22#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.22:10:56.22#ibcon#ireg 11 cls_cnt 2 2006.173.22:10:56.22#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.22:10:56.28#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.22:10:56.28#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.22:10:56.28#ibcon#enter wrdev, iclass 30, count 2 2006.173.22:10:56.28#ibcon#first serial, iclass 30, count 2 2006.173.22:10:56.28#ibcon#enter sib2, iclass 30, count 2 2006.173.22:10:56.28#ibcon#flushed, iclass 30, count 2 2006.173.22:10:56.28#ibcon#about to write, iclass 30, count 2 2006.173.22:10:56.28#ibcon#wrote, iclass 30, count 2 2006.173.22:10:56.28#ibcon#about to read 3, iclass 30, count 2 2006.173.22:10:56.30#ibcon#read 3, iclass 30, count 2 2006.173.22:10:56.30#ibcon#about to read 4, iclass 30, count 2 2006.173.22:10:56.30#ibcon#read 4, iclass 30, count 2 2006.173.22:10:56.30#ibcon#about to read 5, iclass 30, count 2 2006.173.22:10:56.30#ibcon#read 5, iclass 30, count 2 2006.173.22:10:56.30#ibcon#about to read 6, iclass 30, count 2 2006.173.22:10:56.30#ibcon#read 6, iclass 30, count 2 2006.173.22:10:56.30#ibcon#end of sib2, iclass 30, count 2 2006.173.22:10:56.30#ibcon#*mode == 0, iclass 30, count 2 2006.173.22:10:56.30#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.22:10:56.30#ibcon#[27=AT08-04\r\n] 2006.173.22:10:56.30#ibcon#*before write, iclass 30, count 2 2006.173.22:10:56.30#ibcon#enter sib2, iclass 30, count 2 2006.173.22:10:56.30#ibcon#flushed, iclass 30, count 2 2006.173.22:10:56.30#ibcon#about to write, iclass 30, count 2 2006.173.22:10:56.30#ibcon#wrote, iclass 30, count 2 2006.173.22:10:56.30#ibcon#about to read 3, iclass 30, count 2 2006.173.22:10:56.33#ibcon#read 3, iclass 30, count 2 2006.173.22:10:56.33#ibcon#about to read 4, iclass 30, count 2 2006.173.22:10:56.33#ibcon#read 4, iclass 30, count 2 2006.173.22:10:56.33#ibcon#about to read 5, iclass 30, count 2 2006.173.22:10:56.33#ibcon#read 5, iclass 30, count 2 2006.173.22:10:56.33#ibcon#about to read 6, iclass 30, count 2 2006.173.22:10:56.33#ibcon#read 6, iclass 30, count 2 2006.173.22:10:56.33#ibcon#end of sib2, iclass 30, count 2 2006.173.22:10:56.33#ibcon#*after write, iclass 30, count 2 2006.173.22:10:56.33#ibcon#*before return 0, iclass 30, count 2 2006.173.22:10:56.33#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.22:10:56.33#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.22:10:56.33#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.22:10:56.33#ibcon#ireg 7 cls_cnt 0 2006.173.22:10:56.33#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.22:10:56.45#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.22:10:56.45#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.22:10:56.45#ibcon#enter wrdev, iclass 30, count 0 2006.173.22:10:56.45#ibcon#first serial, iclass 30, count 0 2006.173.22:10:56.45#ibcon#enter sib2, iclass 30, count 0 2006.173.22:10:56.45#ibcon#flushed, iclass 30, count 0 2006.173.22:10:56.45#ibcon#about to write, iclass 30, count 0 2006.173.22:10:56.45#ibcon#wrote, iclass 30, count 0 2006.173.22:10:56.45#ibcon#about to read 3, iclass 30, count 0 2006.173.22:10:56.47#ibcon#read 3, iclass 30, count 0 2006.173.22:10:56.47#ibcon#about to read 4, iclass 30, count 0 2006.173.22:10:56.47#ibcon#read 4, iclass 30, count 0 2006.173.22:10:56.47#ibcon#about to read 5, iclass 30, count 0 2006.173.22:10:56.47#ibcon#read 5, iclass 30, count 0 2006.173.22:10:56.47#ibcon#about to read 6, iclass 30, count 0 2006.173.22:10:56.47#ibcon#read 6, iclass 30, count 0 2006.173.22:10:56.47#ibcon#end of sib2, iclass 30, count 0 2006.173.22:10:56.47#ibcon#*mode == 0, iclass 30, count 0 2006.173.22:10:56.47#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.22:10:56.47#ibcon#[27=USB\r\n] 2006.173.22:10:56.47#ibcon#*before write, iclass 30, count 0 2006.173.22:10:56.47#ibcon#enter sib2, iclass 30, count 0 2006.173.22:10:56.47#ibcon#flushed, iclass 30, count 0 2006.173.22:10:56.47#ibcon#about to write, iclass 30, count 0 2006.173.22:10:56.47#ibcon#wrote, iclass 30, count 0 2006.173.22:10:56.47#ibcon#about to read 3, iclass 30, count 0 2006.173.22:10:56.50#ibcon#read 3, iclass 30, count 0 2006.173.22:10:56.50#ibcon#about to read 4, iclass 30, count 0 2006.173.22:10:56.50#ibcon#read 4, iclass 30, count 0 2006.173.22:10:56.50#ibcon#about to read 5, iclass 30, count 0 2006.173.22:10:56.50#ibcon#read 5, iclass 30, count 0 2006.173.22:10:56.50#ibcon#about to read 6, iclass 30, count 0 2006.173.22:10:56.50#ibcon#read 6, iclass 30, count 0 2006.173.22:10:56.50#ibcon#end of sib2, iclass 30, count 0 2006.173.22:10:56.50#ibcon#*after write, iclass 30, count 0 2006.173.22:10:56.50#ibcon#*before return 0, iclass 30, count 0 2006.173.22:10:56.50#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.22:10:56.50#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.22:10:56.50#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.22:10:56.50#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.22:10:56.50$vck44/vabw=wide 2006.173.22:10:56.50#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.22:10:56.50#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.22:10:56.50#ibcon#ireg 8 cls_cnt 0 2006.173.22:10:56.50#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.22:10:56.50#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.22:10:56.50#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.22:10:56.50#ibcon#enter wrdev, iclass 32, count 0 2006.173.22:10:56.50#ibcon#first serial, iclass 32, count 0 2006.173.22:10:56.50#ibcon#enter sib2, iclass 32, count 0 2006.173.22:10:56.50#ibcon#flushed, iclass 32, count 0 2006.173.22:10:56.50#ibcon#about to write, iclass 32, count 0 2006.173.22:10:56.50#ibcon#wrote, iclass 32, count 0 2006.173.22:10:56.50#ibcon#about to read 3, iclass 32, count 0 2006.173.22:10:56.52#ibcon#read 3, iclass 32, count 0 2006.173.22:10:56.52#ibcon#about to read 4, iclass 32, count 0 2006.173.22:10:56.52#ibcon#read 4, iclass 32, count 0 2006.173.22:10:56.52#ibcon#about to read 5, iclass 32, count 0 2006.173.22:10:56.52#ibcon#read 5, iclass 32, count 0 2006.173.22:10:56.52#ibcon#about to read 6, iclass 32, count 0 2006.173.22:10:56.52#ibcon#read 6, iclass 32, count 0 2006.173.22:10:56.52#ibcon#end of sib2, iclass 32, count 0 2006.173.22:10:56.52#ibcon#*mode == 0, iclass 32, count 0 2006.173.22:10:56.52#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.22:10:56.52#ibcon#[25=BW32\r\n] 2006.173.22:10:56.52#ibcon#*before write, iclass 32, count 0 2006.173.22:10:56.52#ibcon#enter sib2, iclass 32, count 0 2006.173.22:10:56.52#ibcon#flushed, iclass 32, count 0 2006.173.22:10:56.52#ibcon#about to write, iclass 32, count 0 2006.173.22:10:56.52#ibcon#wrote, iclass 32, count 0 2006.173.22:10:56.52#ibcon#about to read 3, iclass 32, count 0 2006.173.22:10:56.55#ibcon#read 3, iclass 32, count 0 2006.173.22:10:56.55#ibcon#about to read 4, iclass 32, count 0 2006.173.22:10:56.55#ibcon#read 4, iclass 32, count 0 2006.173.22:10:56.55#ibcon#about to read 5, iclass 32, count 0 2006.173.22:10:56.55#ibcon#read 5, iclass 32, count 0 2006.173.22:10:56.55#ibcon#about to read 6, iclass 32, count 0 2006.173.22:10:56.55#ibcon#read 6, iclass 32, count 0 2006.173.22:10:56.55#ibcon#end of sib2, iclass 32, count 0 2006.173.22:10:56.55#ibcon#*after write, iclass 32, count 0 2006.173.22:10:56.55#ibcon#*before return 0, iclass 32, count 0 2006.173.22:10:56.55#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.22:10:56.55#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.22:10:56.55#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.22:10:56.55#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.22:10:56.55$vck44/vbbw=wide 2006.173.22:10:56.55#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.22:10:56.55#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.22:10:56.55#ibcon#ireg 8 cls_cnt 0 2006.173.22:10:56.55#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.22:10:56.62#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.22:10:56.62#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.22:10:56.62#ibcon#enter wrdev, iclass 34, count 0 2006.173.22:10:56.62#ibcon#first serial, iclass 34, count 0 2006.173.22:10:56.62#ibcon#enter sib2, iclass 34, count 0 2006.173.22:10:56.62#ibcon#flushed, iclass 34, count 0 2006.173.22:10:56.62#ibcon#about to write, iclass 34, count 0 2006.173.22:10:56.62#ibcon#wrote, iclass 34, count 0 2006.173.22:10:56.62#ibcon#about to read 3, iclass 34, count 0 2006.173.22:10:56.64#ibcon#read 3, iclass 34, count 0 2006.173.22:10:56.64#ibcon#about to read 4, iclass 34, count 0 2006.173.22:10:56.64#ibcon#read 4, iclass 34, count 0 2006.173.22:10:56.64#ibcon#about to read 5, iclass 34, count 0 2006.173.22:10:56.64#ibcon#read 5, iclass 34, count 0 2006.173.22:10:56.64#ibcon#about to read 6, iclass 34, count 0 2006.173.22:10:56.64#ibcon#read 6, iclass 34, count 0 2006.173.22:10:56.64#ibcon#end of sib2, iclass 34, count 0 2006.173.22:10:56.64#ibcon#*mode == 0, iclass 34, count 0 2006.173.22:10:56.64#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.22:10:56.64#ibcon#[27=BW32\r\n] 2006.173.22:10:56.64#ibcon#*before write, iclass 34, count 0 2006.173.22:10:56.64#ibcon#enter sib2, iclass 34, count 0 2006.173.22:10:56.64#ibcon#flushed, iclass 34, count 0 2006.173.22:10:56.64#ibcon#about to write, iclass 34, count 0 2006.173.22:10:56.64#ibcon#wrote, iclass 34, count 0 2006.173.22:10:56.64#ibcon#about to read 3, iclass 34, count 0 2006.173.22:10:56.67#ibcon#read 3, iclass 34, count 0 2006.173.22:10:56.67#ibcon#about to read 4, iclass 34, count 0 2006.173.22:10:56.67#ibcon#read 4, iclass 34, count 0 2006.173.22:10:56.67#ibcon#about to read 5, iclass 34, count 0 2006.173.22:10:56.67#ibcon#read 5, iclass 34, count 0 2006.173.22:10:56.67#ibcon#about to read 6, iclass 34, count 0 2006.173.22:10:56.67#ibcon#read 6, iclass 34, count 0 2006.173.22:10:56.67#ibcon#end of sib2, iclass 34, count 0 2006.173.22:10:56.67#ibcon#*after write, iclass 34, count 0 2006.173.22:10:56.67#ibcon#*before return 0, iclass 34, count 0 2006.173.22:10:56.67#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.22:10:56.67#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.22:10:56.67#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.22:10:56.67#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.22:10:56.67$setupk4/ifdk4 2006.173.22:10:56.67$ifdk4/lo= 2006.173.22:10:56.67$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.22:10:56.67$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.22:10:56.67$ifdk4/patch= 2006.173.22:10:56.67$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.22:10:56.67$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.22:10:56.67$setupk4/!*+20s 2006.173.22:11:00.14#trakl#Source acquired 2006.173.22:11:00.84#abcon#<5=/12 0.5 1.4 21.80 961003.4\r\n> 2006.173.22:11:00.86#abcon#{5=INTERFACE CLEAR} 2006.173.22:11:00.92#abcon#[5=S1D000X0/0*\r\n] 2006.173.22:11:02.14#flagr#flagr/antenna,acquired 2006.173.22:11:11.01#abcon#<5=/12 0.5 1.4 21.80 971003.4\r\n> 2006.173.22:11:11.03#abcon#{5=INTERFACE CLEAR} 2006.173.22:11:11.09#abcon#[5=S1D000X0/0*\r\n] 2006.173.22:11:11.18$setupk4/"tpicd 2006.173.22:11:11.18$setupk4/echo=off 2006.173.22:11:11.18$setupk4/xlog=off 2006.173.22:11:11.18:!2006.173.22:14:16 2006.173.22:14:16.00:preob 2006.173.22:14:16.14/onsource/TRACKING 2006.173.22:14:16.14:!2006.173.22:14:26 2006.173.22:14:26.00:"tape 2006.173.22:14:26.00:"st=record 2006.173.22:14:26.00:data_valid=on 2006.173.22:14:26.00:midob 2006.173.22:14:26.14/onsource/TRACKING 2006.173.22:14:26.14/wx/21.89,1003.4,97 2006.173.22:14:26.30/cable/+6.5177E-03 2006.173.22:14:27.39/va/01,07,usb,yes,36,39 2006.173.22:14:27.39/va/02,06,usb,yes,36,37 2006.173.22:14:27.39/va/03,05,usb,yes,45,47 2006.173.22:14:27.39/va/04,06,usb,yes,36,38 2006.173.22:14:27.39/va/05,04,usb,yes,28,29 2006.173.22:14:27.39/va/06,03,usb,yes,40,40 2006.173.22:14:27.39/va/07,04,usb,yes,32,34 2006.173.22:14:27.39/va/08,04,usb,yes,28,33 2006.173.22:14:27.62/valo/01,524.99,yes,locked 2006.173.22:14:27.62/valo/02,534.99,yes,locked 2006.173.22:14:27.62/valo/03,564.99,yes,locked 2006.173.22:14:27.62/valo/04,624.99,yes,locked 2006.173.22:14:27.62/valo/05,734.99,yes,locked 2006.173.22:14:27.62/valo/06,814.99,yes,locked 2006.173.22:14:27.62/valo/07,864.99,yes,locked 2006.173.22:14:27.62/valo/08,884.99,yes,locked 2006.173.22:14:28.71/vb/01,04,usb,yes,30,28 2006.173.22:14:28.71/vb/02,04,usb,yes,32,32 2006.173.22:14:28.71/vb/03,04,usb,yes,29,32 2006.173.22:14:28.71/vb/04,04,usb,yes,33,32 2006.173.22:14:28.71/vb/05,04,usb,yes,26,28 2006.173.22:14:28.71/vb/06,04,usb,yes,30,27 2006.173.22:14:28.71/vb/07,04,usb,yes,30,30 2006.173.22:14:28.71/vb/08,04,usb,yes,28,31 2006.173.22:14:28.94/vblo/01,629.99,yes,locked 2006.173.22:14:28.94/vblo/02,634.99,yes,locked 2006.173.22:14:28.94/vblo/03,649.99,yes,locked 2006.173.22:14:28.94/vblo/04,679.99,yes,locked 2006.173.22:14:28.94/vblo/05,709.99,yes,locked 2006.173.22:14:28.94/vblo/06,719.99,yes,locked 2006.173.22:14:28.94/vblo/07,734.99,yes,locked 2006.173.22:14:28.94/vblo/08,744.99,yes,locked 2006.173.22:14:29.09/vabw/8 2006.173.22:14:29.24/vbbw/8 2006.173.22:14:29.33/xfe/off,on,15.2 2006.173.22:14:29.70/ifatt/23,28,28,28 2006.173.22:14:30.08/fmout-gps/S +3.83E-07 2006.173.22:14:30.12:!2006.173.22:15:46 2006.173.22:15:46.00:data_valid=off 2006.173.22:15:46.00:"et 2006.173.22:15:46.00:!+3s 2006.173.22:15:49.01:"tape 2006.173.22:15:49.01:postob 2006.173.22:15:49.14/cable/+6.5150E-03 2006.173.22:15:49.14/wx/21.93,1003.4,97 2006.173.22:15:50.08/fmout-gps/S +3.84E-07 2006.173.22:15:50.08:scan_name=173-2218,jd0606,190 2006.173.22:15:50.08:source=3c446,222547.26,-045701.4,2000.0,ccw 2006.173.22:15:51.14#flagr#flagr/antenna,new-source 2006.173.22:15:51.14:checkk5 2006.173.22:15:51.53/chk_autoobs//k5ts1/ autoobs is running! 2006.173.22:15:51.92/chk_autoobs//k5ts2/ autoobs is running! 2006.173.22:15:52.34/chk_autoobs//k5ts3/ autoobs is running! 2006.173.22:15:52.74/chk_autoobs//k5ts4/ autoobs is running! 2006.173.22:15:53.12/chk_obsdata//k5ts1/T1732214??a.dat file size is correct (nominal:320MB, actual:316MB). 2006.173.22:15:53.55/chk_obsdata//k5ts2/T1732214??b.dat file size is correct (nominal:320MB, actual:316MB). 2006.173.22:15:53.96/chk_obsdata//k5ts3/T1732214??c.dat file size is correct (nominal:320MB, actual:316MB). 2006.173.22:15:54.36/chk_obsdata//k5ts4/T1732214??d.dat file size is correct (nominal:320MB, actual:316MB). 2006.173.22:15:55.08/k5log//k5ts1_log_newline 2006.173.22:15:55.81/k5log//k5ts2_log_newline 2006.173.22:15:56.52/k5log//k5ts3_log_newline 2006.173.22:15:57.22/k5log//k5ts4_log_newline 2006.173.22:15:57.25/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.22:15:57.25:setupk4=1 2006.173.22:15:57.25$setupk4/echo=on 2006.173.22:15:57.25$setupk4/pcalon 2006.173.22:15:57.25$pcalon/"no phase cal control is implemented here 2006.173.22:15:57.25$setupk4/"tpicd=stop 2006.173.22:15:57.25$setupk4/"rec=synch_on 2006.173.22:15:57.25$setupk4/"rec_mode=128 2006.173.22:15:57.25$setupk4/!* 2006.173.22:15:57.25$setupk4/recpk4 2006.173.22:15:57.25$recpk4/recpatch= 2006.173.22:15:57.26$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.22:15:57.26$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.22:15:57.26$setupk4/vck44 2006.173.22:15:57.26$vck44/valo=1,524.99 2006.173.22:15:57.26#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.22:15:57.26#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.22:15:57.26#ibcon#ireg 17 cls_cnt 0 2006.173.22:15:57.26#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.22:15:57.26#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.22:15:57.26#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.22:15:57.26#ibcon#enter wrdev, iclass 15, count 0 2006.173.22:15:57.26#ibcon#first serial, iclass 15, count 0 2006.173.22:15:57.26#ibcon#enter sib2, iclass 15, count 0 2006.173.22:15:57.26#ibcon#flushed, iclass 15, count 0 2006.173.22:15:57.26#ibcon#about to write, iclass 15, count 0 2006.173.22:15:57.26#ibcon#wrote, iclass 15, count 0 2006.173.22:15:57.26#ibcon#about to read 3, iclass 15, count 0 2006.173.22:15:57.27#ibcon#read 3, iclass 15, count 0 2006.173.22:15:57.27#ibcon#about to read 4, iclass 15, count 0 2006.173.22:15:57.27#ibcon#read 4, iclass 15, count 0 2006.173.22:15:57.27#ibcon#about to read 5, iclass 15, count 0 2006.173.22:15:57.27#ibcon#read 5, iclass 15, count 0 2006.173.22:15:57.27#ibcon#about to read 6, iclass 15, count 0 2006.173.22:15:57.27#ibcon#read 6, iclass 15, count 0 2006.173.22:15:57.27#ibcon#end of sib2, iclass 15, count 0 2006.173.22:15:57.27#ibcon#*mode == 0, iclass 15, count 0 2006.173.22:15:57.27#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.22:15:57.27#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.22:15:57.27#ibcon#*before write, iclass 15, count 0 2006.173.22:15:57.27#ibcon#enter sib2, iclass 15, count 0 2006.173.22:15:57.27#ibcon#flushed, iclass 15, count 0 2006.173.22:15:57.27#ibcon#about to write, iclass 15, count 0 2006.173.22:15:57.27#ibcon#wrote, iclass 15, count 0 2006.173.22:15:57.27#ibcon#about to read 3, iclass 15, count 0 2006.173.22:15:57.32#ibcon#read 3, iclass 15, count 0 2006.173.22:15:57.32#ibcon#about to read 4, iclass 15, count 0 2006.173.22:15:57.32#ibcon#read 4, iclass 15, count 0 2006.173.22:15:57.32#ibcon#about to read 5, iclass 15, count 0 2006.173.22:15:57.32#ibcon#read 5, iclass 15, count 0 2006.173.22:15:57.32#ibcon#about to read 6, iclass 15, count 0 2006.173.22:15:57.32#ibcon#read 6, iclass 15, count 0 2006.173.22:15:57.32#ibcon#end of sib2, iclass 15, count 0 2006.173.22:15:57.32#ibcon#*after write, iclass 15, count 0 2006.173.22:15:57.32#ibcon#*before return 0, iclass 15, count 0 2006.173.22:15:57.32#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.22:15:57.32#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.22:15:57.32#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.22:15:57.32#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.22:15:57.32$vck44/va=1,7 2006.173.22:15:57.32#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.22:15:57.32#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.22:15:57.32#ibcon#ireg 11 cls_cnt 2 2006.173.22:15:57.32#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.22:15:57.32#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.22:15:57.32#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.22:15:57.32#ibcon#enter wrdev, iclass 17, count 2 2006.173.22:15:57.32#ibcon#first serial, iclass 17, count 2 2006.173.22:15:57.32#ibcon#enter sib2, iclass 17, count 2 2006.173.22:15:57.32#ibcon#flushed, iclass 17, count 2 2006.173.22:15:57.32#ibcon#about to write, iclass 17, count 2 2006.173.22:15:57.32#ibcon#wrote, iclass 17, count 2 2006.173.22:15:57.32#ibcon#about to read 3, iclass 17, count 2 2006.173.22:15:57.34#ibcon#read 3, iclass 17, count 2 2006.173.22:15:57.34#ibcon#about to read 4, iclass 17, count 2 2006.173.22:15:57.34#ibcon#read 4, iclass 17, count 2 2006.173.22:15:57.34#ibcon#about to read 5, iclass 17, count 2 2006.173.22:15:57.34#ibcon#read 5, iclass 17, count 2 2006.173.22:15:57.34#ibcon#about to read 6, iclass 17, count 2 2006.173.22:15:57.34#ibcon#read 6, iclass 17, count 2 2006.173.22:15:57.34#ibcon#end of sib2, iclass 17, count 2 2006.173.22:15:57.34#ibcon#*mode == 0, iclass 17, count 2 2006.173.22:15:57.34#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.22:15:57.34#ibcon#[25=AT01-07\r\n] 2006.173.22:15:57.34#ibcon#*before write, iclass 17, count 2 2006.173.22:15:57.34#ibcon#enter sib2, iclass 17, count 2 2006.173.22:15:57.34#ibcon#flushed, iclass 17, count 2 2006.173.22:15:57.34#ibcon#about to write, iclass 17, count 2 2006.173.22:15:57.34#ibcon#wrote, iclass 17, count 2 2006.173.22:15:57.34#ibcon#about to read 3, iclass 17, count 2 2006.173.22:15:57.37#ibcon#read 3, iclass 17, count 2 2006.173.22:15:57.37#ibcon#about to read 4, iclass 17, count 2 2006.173.22:15:57.37#ibcon#read 4, iclass 17, count 2 2006.173.22:15:57.37#ibcon#about to read 5, iclass 17, count 2 2006.173.22:15:57.37#ibcon#read 5, iclass 17, count 2 2006.173.22:15:57.37#ibcon#about to read 6, iclass 17, count 2 2006.173.22:15:57.37#ibcon#read 6, iclass 17, count 2 2006.173.22:15:57.37#ibcon#end of sib2, iclass 17, count 2 2006.173.22:15:57.37#ibcon#*after write, iclass 17, count 2 2006.173.22:15:57.37#ibcon#*before return 0, iclass 17, count 2 2006.173.22:15:57.37#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.22:15:57.37#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.22:15:57.37#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.22:15:57.37#ibcon#ireg 7 cls_cnt 0 2006.173.22:15:57.37#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.22:15:57.49#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.22:15:57.49#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.22:15:57.49#ibcon#enter wrdev, iclass 17, count 0 2006.173.22:15:57.49#ibcon#first serial, iclass 17, count 0 2006.173.22:15:57.49#ibcon#enter sib2, iclass 17, count 0 2006.173.22:15:57.49#ibcon#flushed, iclass 17, count 0 2006.173.22:15:57.49#ibcon#about to write, iclass 17, count 0 2006.173.22:15:57.49#ibcon#wrote, iclass 17, count 0 2006.173.22:15:57.49#ibcon#about to read 3, iclass 17, count 0 2006.173.22:15:57.51#ibcon#read 3, iclass 17, count 0 2006.173.22:15:57.51#ibcon#about to read 4, iclass 17, count 0 2006.173.22:15:57.51#ibcon#read 4, iclass 17, count 0 2006.173.22:15:57.51#ibcon#about to read 5, iclass 17, count 0 2006.173.22:15:57.51#ibcon#read 5, iclass 17, count 0 2006.173.22:15:57.51#ibcon#about to read 6, iclass 17, count 0 2006.173.22:15:57.51#ibcon#read 6, iclass 17, count 0 2006.173.22:15:57.51#ibcon#end of sib2, iclass 17, count 0 2006.173.22:15:57.51#ibcon#*mode == 0, iclass 17, count 0 2006.173.22:15:57.51#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.22:15:57.51#ibcon#[25=USB\r\n] 2006.173.22:15:57.51#ibcon#*before write, iclass 17, count 0 2006.173.22:15:57.51#ibcon#enter sib2, iclass 17, count 0 2006.173.22:15:57.51#ibcon#flushed, iclass 17, count 0 2006.173.22:15:57.51#ibcon#about to write, iclass 17, count 0 2006.173.22:15:57.51#ibcon#wrote, iclass 17, count 0 2006.173.22:15:57.51#ibcon#about to read 3, iclass 17, count 0 2006.173.22:15:57.54#ibcon#read 3, iclass 17, count 0 2006.173.22:15:57.54#ibcon#about to read 4, iclass 17, count 0 2006.173.22:15:57.54#ibcon#read 4, iclass 17, count 0 2006.173.22:15:57.54#ibcon#about to read 5, iclass 17, count 0 2006.173.22:15:57.54#ibcon#read 5, iclass 17, count 0 2006.173.22:15:57.54#ibcon#about to read 6, iclass 17, count 0 2006.173.22:15:57.54#ibcon#read 6, iclass 17, count 0 2006.173.22:15:57.54#ibcon#end of sib2, iclass 17, count 0 2006.173.22:15:57.54#ibcon#*after write, iclass 17, count 0 2006.173.22:15:57.54#ibcon#*before return 0, iclass 17, count 0 2006.173.22:15:57.54#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.22:15:57.54#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.22:15:57.54#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.22:15:57.54#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.22:15:57.54$vck44/valo=2,534.99 2006.173.22:15:57.54#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.22:15:57.54#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.22:15:57.54#ibcon#ireg 17 cls_cnt 0 2006.173.22:15:57.54#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.22:15:57.54#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.22:15:57.54#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.22:15:57.54#ibcon#enter wrdev, iclass 19, count 0 2006.173.22:15:57.54#ibcon#first serial, iclass 19, count 0 2006.173.22:15:57.54#ibcon#enter sib2, iclass 19, count 0 2006.173.22:15:57.54#ibcon#flushed, iclass 19, count 0 2006.173.22:15:57.54#ibcon#about to write, iclass 19, count 0 2006.173.22:15:57.54#ibcon#wrote, iclass 19, count 0 2006.173.22:15:57.54#ibcon#about to read 3, iclass 19, count 0 2006.173.22:15:57.56#ibcon#read 3, iclass 19, count 0 2006.173.22:15:57.56#ibcon#about to read 4, iclass 19, count 0 2006.173.22:15:57.56#ibcon#read 4, iclass 19, count 0 2006.173.22:15:57.56#ibcon#about to read 5, iclass 19, count 0 2006.173.22:15:57.56#ibcon#read 5, iclass 19, count 0 2006.173.22:15:57.56#ibcon#about to read 6, iclass 19, count 0 2006.173.22:15:57.56#ibcon#read 6, iclass 19, count 0 2006.173.22:15:57.56#ibcon#end of sib2, iclass 19, count 0 2006.173.22:15:57.56#ibcon#*mode == 0, iclass 19, count 0 2006.173.22:15:57.56#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.22:15:57.56#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.22:15:57.56#ibcon#*before write, iclass 19, count 0 2006.173.22:15:57.56#ibcon#enter sib2, iclass 19, count 0 2006.173.22:15:57.56#ibcon#flushed, iclass 19, count 0 2006.173.22:15:57.56#ibcon#about to write, iclass 19, count 0 2006.173.22:15:57.56#ibcon#wrote, iclass 19, count 0 2006.173.22:15:57.56#ibcon#about to read 3, iclass 19, count 0 2006.173.22:15:57.60#ibcon#read 3, iclass 19, count 0 2006.173.22:15:57.60#ibcon#about to read 4, iclass 19, count 0 2006.173.22:15:57.60#ibcon#read 4, iclass 19, count 0 2006.173.22:15:57.60#ibcon#about to read 5, iclass 19, count 0 2006.173.22:15:57.60#ibcon#read 5, iclass 19, count 0 2006.173.22:15:57.60#ibcon#about to read 6, iclass 19, count 0 2006.173.22:15:57.60#ibcon#read 6, iclass 19, count 0 2006.173.22:15:57.60#ibcon#end of sib2, iclass 19, count 0 2006.173.22:15:57.60#ibcon#*after write, iclass 19, count 0 2006.173.22:15:57.60#ibcon#*before return 0, iclass 19, count 0 2006.173.22:15:57.60#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.22:15:57.60#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.22:15:57.60#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.22:15:57.60#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.22:15:57.60$vck44/va=2,6 2006.173.22:15:57.60#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.22:15:57.60#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.22:15:57.60#ibcon#ireg 11 cls_cnt 2 2006.173.22:15:57.60#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.22:15:57.66#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.22:15:57.66#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.22:15:57.66#ibcon#enter wrdev, iclass 21, count 2 2006.173.22:15:57.66#ibcon#first serial, iclass 21, count 2 2006.173.22:15:57.66#ibcon#enter sib2, iclass 21, count 2 2006.173.22:15:57.66#ibcon#flushed, iclass 21, count 2 2006.173.22:15:57.66#ibcon#about to write, iclass 21, count 2 2006.173.22:15:57.66#ibcon#wrote, iclass 21, count 2 2006.173.22:15:57.66#ibcon#about to read 3, iclass 21, count 2 2006.173.22:15:57.68#ibcon#read 3, iclass 21, count 2 2006.173.22:15:57.68#ibcon#about to read 4, iclass 21, count 2 2006.173.22:15:57.68#ibcon#read 4, iclass 21, count 2 2006.173.22:15:57.68#ibcon#about to read 5, iclass 21, count 2 2006.173.22:15:57.68#ibcon#read 5, iclass 21, count 2 2006.173.22:15:57.68#ibcon#about to read 6, iclass 21, count 2 2006.173.22:15:57.68#ibcon#read 6, iclass 21, count 2 2006.173.22:15:57.68#ibcon#end of sib2, iclass 21, count 2 2006.173.22:15:57.68#ibcon#*mode == 0, iclass 21, count 2 2006.173.22:15:57.68#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.22:15:57.68#ibcon#[25=AT02-06\r\n] 2006.173.22:15:57.68#ibcon#*before write, iclass 21, count 2 2006.173.22:15:57.68#ibcon#enter sib2, iclass 21, count 2 2006.173.22:15:57.68#ibcon#flushed, iclass 21, count 2 2006.173.22:15:57.68#ibcon#about to write, iclass 21, count 2 2006.173.22:15:57.68#ibcon#wrote, iclass 21, count 2 2006.173.22:15:57.68#ibcon#about to read 3, iclass 21, count 2 2006.173.22:15:57.71#ibcon#read 3, iclass 21, count 2 2006.173.22:15:57.71#ibcon#about to read 4, iclass 21, count 2 2006.173.22:15:57.71#ibcon#read 4, iclass 21, count 2 2006.173.22:15:57.71#ibcon#about to read 5, iclass 21, count 2 2006.173.22:15:57.71#ibcon#read 5, iclass 21, count 2 2006.173.22:15:57.71#ibcon#about to read 6, iclass 21, count 2 2006.173.22:15:57.71#ibcon#read 6, iclass 21, count 2 2006.173.22:15:57.71#ibcon#end of sib2, iclass 21, count 2 2006.173.22:15:57.71#ibcon#*after write, iclass 21, count 2 2006.173.22:15:57.71#ibcon#*before return 0, iclass 21, count 2 2006.173.22:15:57.71#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.22:15:57.71#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.22:15:57.71#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.22:15:57.71#ibcon#ireg 7 cls_cnt 0 2006.173.22:15:57.71#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.22:15:57.83#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.22:15:57.83#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.22:15:57.83#ibcon#enter wrdev, iclass 21, count 0 2006.173.22:15:57.83#ibcon#first serial, iclass 21, count 0 2006.173.22:15:57.83#ibcon#enter sib2, iclass 21, count 0 2006.173.22:15:57.83#ibcon#flushed, iclass 21, count 0 2006.173.22:15:57.83#ibcon#about to write, iclass 21, count 0 2006.173.22:15:57.83#ibcon#wrote, iclass 21, count 0 2006.173.22:15:57.83#ibcon#about to read 3, iclass 21, count 0 2006.173.22:15:57.85#ibcon#read 3, iclass 21, count 0 2006.173.22:15:57.85#ibcon#about to read 4, iclass 21, count 0 2006.173.22:15:57.85#ibcon#read 4, iclass 21, count 0 2006.173.22:15:57.85#ibcon#about to read 5, iclass 21, count 0 2006.173.22:15:57.85#ibcon#read 5, iclass 21, count 0 2006.173.22:15:57.85#ibcon#about to read 6, iclass 21, count 0 2006.173.22:15:57.85#ibcon#read 6, iclass 21, count 0 2006.173.22:15:57.85#ibcon#end of sib2, iclass 21, count 0 2006.173.22:15:57.85#ibcon#*mode == 0, iclass 21, count 0 2006.173.22:15:57.85#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.22:15:57.85#ibcon#[25=USB\r\n] 2006.173.22:15:57.85#ibcon#*before write, iclass 21, count 0 2006.173.22:15:57.85#ibcon#enter sib2, iclass 21, count 0 2006.173.22:15:57.85#ibcon#flushed, iclass 21, count 0 2006.173.22:15:57.85#ibcon#about to write, iclass 21, count 0 2006.173.22:15:57.85#ibcon#wrote, iclass 21, count 0 2006.173.22:15:57.85#ibcon#about to read 3, iclass 21, count 0 2006.173.22:15:57.88#ibcon#read 3, iclass 21, count 0 2006.173.22:15:57.88#ibcon#about to read 4, iclass 21, count 0 2006.173.22:15:57.88#ibcon#read 4, iclass 21, count 0 2006.173.22:15:57.88#ibcon#about to read 5, iclass 21, count 0 2006.173.22:15:57.88#ibcon#read 5, iclass 21, count 0 2006.173.22:15:57.88#ibcon#about to read 6, iclass 21, count 0 2006.173.22:15:57.88#ibcon#read 6, iclass 21, count 0 2006.173.22:15:57.88#ibcon#end of sib2, iclass 21, count 0 2006.173.22:15:57.88#ibcon#*after write, iclass 21, count 0 2006.173.22:15:57.88#ibcon#*before return 0, iclass 21, count 0 2006.173.22:15:57.88#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.22:15:57.88#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.22:15:57.88#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.22:15:57.88#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.22:15:57.88$vck44/valo=3,564.99 2006.173.22:15:57.88#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.22:15:57.88#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.22:15:57.88#ibcon#ireg 17 cls_cnt 0 2006.173.22:15:57.88#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.22:15:57.88#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.22:15:57.88#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.22:15:57.88#ibcon#enter wrdev, iclass 23, count 0 2006.173.22:15:57.88#ibcon#first serial, iclass 23, count 0 2006.173.22:15:57.88#ibcon#enter sib2, iclass 23, count 0 2006.173.22:15:57.88#ibcon#flushed, iclass 23, count 0 2006.173.22:15:57.88#ibcon#about to write, iclass 23, count 0 2006.173.22:15:57.88#ibcon#wrote, iclass 23, count 0 2006.173.22:15:57.88#ibcon#about to read 3, iclass 23, count 0 2006.173.22:15:57.90#ibcon#read 3, iclass 23, count 0 2006.173.22:15:57.90#ibcon#about to read 4, iclass 23, count 0 2006.173.22:15:57.90#ibcon#read 4, iclass 23, count 0 2006.173.22:15:57.90#ibcon#about to read 5, iclass 23, count 0 2006.173.22:15:57.90#ibcon#read 5, iclass 23, count 0 2006.173.22:15:57.90#ibcon#about to read 6, iclass 23, count 0 2006.173.22:15:57.90#ibcon#read 6, iclass 23, count 0 2006.173.22:15:57.90#ibcon#end of sib2, iclass 23, count 0 2006.173.22:15:57.90#ibcon#*mode == 0, iclass 23, count 0 2006.173.22:15:57.90#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.22:15:57.90#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.22:15:57.90#ibcon#*before write, iclass 23, count 0 2006.173.22:15:57.90#ibcon#enter sib2, iclass 23, count 0 2006.173.22:15:57.90#ibcon#flushed, iclass 23, count 0 2006.173.22:15:57.90#ibcon#about to write, iclass 23, count 0 2006.173.22:15:57.90#ibcon#wrote, iclass 23, count 0 2006.173.22:15:57.90#ibcon#about to read 3, iclass 23, count 0 2006.173.22:15:57.94#ibcon#read 3, iclass 23, count 0 2006.173.22:15:57.94#ibcon#about to read 4, iclass 23, count 0 2006.173.22:15:57.94#ibcon#read 4, iclass 23, count 0 2006.173.22:15:57.94#ibcon#about to read 5, iclass 23, count 0 2006.173.22:15:57.94#ibcon#read 5, iclass 23, count 0 2006.173.22:15:57.94#ibcon#about to read 6, iclass 23, count 0 2006.173.22:15:57.94#ibcon#read 6, iclass 23, count 0 2006.173.22:15:57.94#ibcon#end of sib2, iclass 23, count 0 2006.173.22:15:57.94#ibcon#*after write, iclass 23, count 0 2006.173.22:15:57.94#ibcon#*before return 0, iclass 23, count 0 2006.173.22:15:57.94#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.22:15:57.94#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.22:15:57.94#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.22:15:57.94#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.22:15:57.94$vck44/va=3,5 2006.173.22:15:57.94#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.22:15:57.94#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.22:15:57.94#ibcon#ireg 11 cls_cnt 2 2006.173.22:15:57.94#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.22:15:58.00#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.22:15:58.00#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.22:15:58.00#ibcon#enter wrdev, iclass 25, count 2 2006.173.22:15:58.00#ibcon#first serial, iclass 25, count 2 2006.173.22:15:58.00#ibcon#enter sib2, iclass 25, count 2 2006.173.22:15:58.00#ibcon#flushed, iclass 25, count 2 2006.173.22:15:58.00#ibcon#about to write, iclass 25, count 2 2006.173.22:15:58.00#ibcon#wrote, iclass 25, count 2 2006.173.22:15:58.00#ibcon#about to read 3, iclass 25, count 2 2006.173.22:15:58.02#ibcon#read 3, iclass 25, count 2 2006.173.22:15:58.02#ibcon#about to read 4, iclass 25, count 2 2006.173.22:15:58.02#ibcon#read 4, iclass 25, count 2 2006.173.22:15:58.02#ibcon#about to read 5, iclass 25, count 2 2006.173.22:15:58.02#ibcon#read 5, iclass 25, count 2 2006.173.22:15:58.02#ibcon#about to read 6, iclass 25, count 2 2006.173.22:15:58.02#ibcon#read 6, iclass 25, count 2 2006.173.22:15:58.02#ibcon#end of sib2, iclass 25, count 2 2006.173.22:15:58.02#ibcon#*mode == 0, iclass 25, count 2 2006.173.22:15:58.02#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.22:15:58.02#ibcon#[25=AT03-05\r\n] 2006.173.22:15:58.02#ibcon#*before write, iclass 25, count 2 2006.173.22:15:58.02#ibcon#enter sib2, iclass 25, count 2 2006.173.22:15:58.02#ibcon#flushed, iclass 25, count 2 2006.173.22:15:58.02#ibcon#about to write, iclass 25, count 2 2006.173.22:15:58.02#ibcon#wrote, iclass 25, count 2 2006.173.22:15:58.02#ibcon#about to read 3, iclass 25, count 2 2006.173.22:15:58.05#ibcon#read 3, iclass 25, count 2 2006.173.22:15:58.05#ibcon#about to read 4, iclass 25, count 2 2006.173.22:15:58.05#ibcon#read 4, iclass 25, count 2 2006.173.22:15:58.05#ibcon#about to read 5, iclass 25, count 2 2006.173.22:15:58.05#ibcon#read 5, iclass 25, count 2 2006.173.22:15:58.05#ibcon#about to read 6, iclass 25, count 2 2006.173.22:15:58.05#ibcon#read 6, iclass 25, count 2 2006.173.22:15:58.05#ibcon#end of sib2, iclass 25, count 2 2006.173.22:15:58.05#ibcon#*after write, iclass 25, count 2 2006.173.22:15:58.05#ibcon#*before return 0, iclass 25, count 2 2006.173.22:15:58.05#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.22:15:58.05#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.22:15:58.05#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.22:15:58.05#ibcon#ireg 7 cls_cnt 0 2006.173.22:15:58.05#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.22:15:58.17#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.22:15:58.17#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.22:15:58.17#ibcon#enter wrdev, iclass 25, count 0 2006.173.22:15:58.17#ibcon#first serial, iclass 25, count 0 2006.173.22:15:58.17#ibcon#enter sib2, iclass 25, count 0 2006.173.22:15:58.17#ibcon#flushed, iclass 25, count 0 2006.173.22:15:58.17#ibcon#about to write, iclass 25, count 0 2006.173.22:15:58.17#ibcon#wrote, iclass 25, count 0 2006.173.22:15:58.17#ibcon#about to read 3, iclass 25, count 0 2006.173.22:15:58.19#ibcon#read 3, iclass 25, count 0 2006.173.22:15:58.19#ibcon#about to read 4, iclass 25, count 0 2006.173.22:15:58.19#ibcon#read 4, iclass 25, count 0 2006.173.22:15:58.19#ibcon#about to read 5, iclass 25, count 0 2006.173.22:15:58.19#ibcon#read 5, iclass 25, count 0 2006.173.22:15:58.19#ibcon#about to read 6, iclass 25, count 0 2006.173.22:15:58.19#ibcon#read 6, iclass 25, count 0 2006.173.22:15:58.19#ibcon#end of sib2, iclass 25, count 0 2006.173.22:15:58.19#ibcon#*mode == 0, iclass 25, count 0 2006.173.22:15:58.19#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.22:15:58.19#ibcon#[25=USB\r\n] 2006.173.22:15:58.19#ibcon#*before write, iclass 25, count 0 2006.173.22:15:58.19#ibcon#enter sib2, iclass 25, count 0 2006.173.22:15:58.19#ibcon#flushed, iclass 25, count 0 2006.173.22:15:58.19#ibcon#about to write, iclass 25, count 0 2006.173.22:15:58.19#ibcon#wrote, iclass 25, count 0 2006.173.22:15:58.19#ibcon#about to read 3, iclass 25, count 0 2006.173.22:15:58.22#ibcon#read 3, iclass 25, count 0 2006.173.22:15:58.22#ibcon#about to read 4, iclass 25, count 0 2006.173.22:15:58.22#ibcon#read 4, iclass 25, count 0 2006.173.22:15:58.22#ibcon#about to read 5, iclass 25, count 0 2006.173.22:15:58.22#ibcon#read 5, iclass 25, count 0 2006.173.22:15:58.22#ibcon#about to read 6, iclass 25, count 0 2006.173.22:15:58.22#ibcon#read 6, iclass 25, count 0 2006.173.22:15:58.22#ibcon#end of sib2, iclass 25, count 0 2006.173.22:15:58.22#ibcon#*after write, iclass 25, count 0 2006.173.22:15:58.22#ibcon#*before return 0, iclass 25, count 0 2006.173.22:15:58.22#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.22:15:58.22#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.22:15:58.22#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.22:15:58.22#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.22:15:58.22$vck44/valo=4,624.99 2006.173.22:15:58.22#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.22:15:58.22#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.22:15:58.22#ibcon#ireg 17 cls_cnt 0 2006.173.22:15:58.22#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.22:15:58.22#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.22:15:58.22#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.22:15:58.22#ibcon#enter wrdev, iclass 27, count 0 2006.173.22:15:58.22#ibcon#first serial, iclass 27, count 0 2006.173.22:15:58.22#ibcon#enter sib2, iclass 27, count 0 2006.173.22:15:58.22#ibcon#flushed, iclass 27, count 0 2006.173.22:15:58.22#ibcon#about to write, iclass 27, count 0 2006.173.22:15:58.22#ibcon#wrote, iclass 27, count 0 2006.173.22:15:58.22#ibcon#about to read 3, iclass 27, count 0 2006.173.22:15:58.24#ibcon#read 3, iclass 27, count 0 2006.173.22:15:58.24#ibcon#about to read 4, iclass 27, count 0 2006.173.22:15:58.24#ibcon#read 4, iclass 27, count 0 2006.173.22:15:58.24#ibcon#about to read 5, iclass 27, count 0 2006.173.22:15:58.24#ibcon#read 5, iclass 27, count 0 2006.173.22:15:58.24#ibcon#about to read 6, iclass 27, count 0 2006.173.22:15:58.24#ibcon#read 6, iclass 27, count 0 2006.173.22:15:58.24#ibcon#end of sib2, iclass 27, count 0 2006.173.22:15:58.24#ibcon#*mode == 0, iclass 27, count 0 2006.173.22:15:58.24#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.22:15:58.24#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.22:15:58.24#ibcon#*before write, iclass 27, count 0 2006.173.22:15:58.24#ibcon#enter sib2, iclass 27, count 0 2006.173.22:15:58.24#ibcon#flushed, iclass 27, count 0 2006.173.22:15:58.24#ibcon#about to write, iclass 27, count 0 2006.173.22:15:58.24#ibcon#wrote, iclass 27, count 0 2006.173.22:15:58.24#ibcon#about to read 3, iclass 27, count 0 2006.173.22:15:58.28#ibcon#read 3, iclass 27, count 0 2006.173.22:15:58.28#ibcon#about to read 4, iclass 27, count 0 2006.173.22:15:58.28#ibcon#read 4, iclass 27, count 0 2006.173.22:15:58.28#ibcon#about to read 5, iclass 27, count 0 2006.173.22:15:58.28#ibcon#read 5, iclass 27, count 0 2006.173.22:15:58.28#ibcon#about to read 6, iclass 27, count 0 2006.173.22:15:58.28#ibcon#read 6, iclass 27, count 0 2006.173.22:15:58.28#ibcon#end of sib2, iclass 27, count 0 2006.173.22:15:58.28#ibcon#*after write, iclass 27, count 0 2006.173.22:15:58.28#ibcon#*before return 0, iclass 27, count 0 2006.173.22:15:58.28#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.22:15:58.28#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.22:15:58.28#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.22:15:58.28#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.22:15:58.28$vck44/va=4,6 2006.173.22:15:58.28#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.22:15:58.28#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.22:15:58.28#ibcon#ireg 11 cls_cnt 2 2006.173.22:15:58.28#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.22:15:58.34#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.22:15:58.34#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.22:15:58.34#ibcon#enter wrdev, iclass 29, count 2 2006.173.22:15:58.34#ibcon#first serial, iclass 29, count 2 2006.173.22:15:58.34#ibcon#enter sib2, iclass 29, count 2 2006.173.22:15:58.34#ibcon#flushed, iclass 29, count 2 2006.173.22:15:58.34#ibcon#about to write, iclass 29, count 2 2006.173.22:15:58.34#ibcon#wrote, iclass 29, count 2 2006.173.22:15:58.34#ibcon#about to read 3, iclass 29, count 2 2006.173.22:15:58.36#ibcon#read 3, iclass 29, count 2 2006.173.22:15:58.36#ibcon#about to read 4, iclass 29, count 2 2006.173.22:15:58.36#ibcon#read 4, iclass 29, count 2 2006.173.22:15:58.36#ibcon#about to read 5, iclass 29, count 2 2006.173.22:15:58.36#ibcon#read 5, iclass 29, count 2 2006.173.22:15:58.36#ibcon#about to read 6, iclass 29, count 2 2006.173.22:15:58.36#ibcon#read 6, iclass 29, count 2 2006.173.22:15:58.36#ibcon#end of sib2, iclass 29, count 2 2006.173.22:15:58.36#ibcon#*mode == 0, iclass 29, count 2 2006.173.22:15:58.36#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.22:15:58.36#ibcon#[25=AT04-06\r\n] 2006.173.22:15:58.36#ibcon#*before write, iclass 29, count 2 2006.173.22:15:58.36#ibcon#enter sib2, iclass 29, count 2 2006.173.22:15:58.36#ibcon#flushed, iclass 29, count 2 2006.173.22:15:58.36#ibcon#about to write, iclass 29, count 2 2006.173.22:15:58.36#ibcon#wrote, iclass 29, count 2 2006.173.22:15:58.36#ibcon#about to read 3, iclass 29, count 2 2006.173.22:15:58.39#ibcon#read 3, iclass 29, count 2 2006.173.22:15:58.39#ibcon#about to read 4, iclass 29, count 2 2006.173.22:15:58.39#ibcon#read 4, iclass 29, count 2 2006.173.22:15:58.39#ibcon#about to read 5, iclass 29, count 2 2006.173.22:15:58.39#ibcon#read 5, iclass 29, count 2 2006.173.22:15:58.39#ibcon#about to read 6, iclass 29, count 2 2006.173.22:15:58.39#ibcon#read 6, iclass 29, count 2 2006.173.22:15:58.39#ibcon#end of sib2, iclass 29, count 2 2006.173.22:15:58.39#ibcon#*after write, iclass 29, count 2 2006.173.22:15:58.39#ibcon#*before return 0, iclass 29, count 2 2006.173.22:15:58.39#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.22:15:58.39#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.22:15:58.39#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.22:15:58.39#ibcon#ireg 7 cls_cnt 0 2006.173.22:15:58.39#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.22:15:58.51#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.22:15:58.51#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.22:15:58.51#ibcon#enter wrdev, iclass 29, count 0 2006.173.22:15:58.51#ibcon#first serial, iclass 29, count 0 2006.173.22:15:58.51#ibcon#enter sib2, iclass 29, count 0 2006.173.22:15:58.51#ibcon#flushed, iclass 29, count 0 2006.173.22:15:58.51#ibcon#about to write, iclass 29, count 0 2006.173.22:15:58.51#ibcon#wrote, iclass 29, count 0 2006.173.22:15:58.51#ibcon#about to read 3, iclass 29, count 0 2006.173.22:15:58.53#ibcon#read 3, iclass 29, count 0 2006.173.22:15:58.53#ibcon#about to read 4, iclass 29, count 0 2006.173.22:15:58.53#ibcon#read 4, iclass 29, count 0 2006.173.22:15:58.53#ibcon#about to read 5, iclass 29, count 0 2006.173.22:15:58.53#ibcon#read 5, iclass 29, count 0 2006.173.22:15:58.53#ibcon#about to read 6, iclass 29, count 0 2006.173.22:15:58.53#ibcon#read 6, iclass 29, count 0 2006.173.22:15:58.53#ibcon#end of sib2, iclass 29, count 0 2006.173.22:15:58.53#ibcon#*mode == 0, iclass 29, count 0 2006.173.22:15:58.53#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.22:15:58.53#ibcon#[25=USB\r\n] 2006.173.22:15:58.53#ibcon#*before write, iclass 29, count 0 2006.173.22:15:58.53#ibcon#enter sib2, iclass 29, count 0 2006.173.22:15:58.53#ibcon#flushed, iclass 29, count 0 2006.173.22:15:58.53#ibcon#about to write, iclass 29, count 0 2006.173.22:15:58.53#ibcon#wrote, iclass 29, count 0 2006.173.22:15:58.53#ibcon#about to read 3, iclass 29, count 0 2006.173.22:15:58.56#ibcon#read 3, iclass 29, count 0 2006.173.22:15:58.56#ibcon#about to read 4, iclass 29, count 0 2006.173.22:15:58.56#ibcon#read 4, iclass 29, count 0 2006.173.22:15:58.56#ibcon#about to read 5, iclass 29, count 0 2006.173.22:15:58.56#ibcon#read 5, iclass 29, count 0 2006.173.22:15:58.56#ibcon#about to read 6, iclass 29, count 0 2006.173.22:15:58.56#ibcon#read 6, iclass 29, count 0 2006.173.22:15:58.56#ibcon#end of sib2, iclass 29, count 0 2006.173.22:15:58.56#ibcon#*after write, iclass 29, count 0 2006.173.22:15:58.56#ibcon#*before return 0, iclass 29, count 0 2006.173.22:15:58.56#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.22:15:58.56#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.22:15:58.56#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.22:15:58.56#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.22:15:58.56$vck44/valo=5,734.99 2006.173.22:15:58.56#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.22:15:58.56#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.22:15:58.56#ibcon#ireg 17 cls_cnt 0 2006.173.22:15:58.56#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.22:15:58.56#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.22:15:58.56#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.22:15:58.56#ibcon#enter wrdev, iclass 31, count 0 2006.173.22:15:58.56#ibcon#first serial, iclass 31, count 0 2006.173.22:15:58.56#ibcon#enter sib2, iclass 31, count 0 2006.173.22:15:58.56#ibcon#flushed, iclass 31, count 0 2006.173.22:15:58.56#ibcon#about to write, iclass 31, count 0 2006.173.22:15:58.56#ibcon#wrote, iclass 31, count 0 2006.173.22:15:58.56#ibcon#about to read 3, iclass 31, count 0 2006.173.22:15:58.58#ibcon#read 3, iclass 31, count 0 2006.173.22:15:58.58#ibcon#about to read 4, iclass 31, count 0 2006.173.22:15:58.58#ibcon#read 4, iclass 31, count 0 2006.173.22:15:58.58#ibcon#about to read 5, iclass 31, count 0 2006.173.22:15:58.58#ibcon#read 5, iclass 31, count 0 2006.173.22:15:58.58#ibcon#about to read 6, iclass 31, count 0 2006.173.22:15:58.58#ibcon#read 6, iclass 31, count 0 2006.173.22:15:58.58#ibcon#end of sib2, iclass 31, count 0 2006.173.22:15:58.58#ibcon#*mode == 0, iclass 31, count 0 2006.173.22:15:58.58#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.22:15:58.58#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.22:15:58.58#ibcon#*before write, iclass 31, count 0 2006.173.22:15:58.58#ibcon#enter sib2, iclass 31, count 0 2006.173.22:15:58.58#ibcon#flushed, iclass 31, count 0 2006.173.22:15:58.58#ibcon#about to write, iclass 31, count 0 2006.173.22:15:58.58#ibcon#wrote, iclass 31, count 0 2006.173.22:15:58.58#ibcon#about to read 3, iclass 31, count 0 2006.173.22:15:58.62#ibcon#read 3, iclass 31, count 0 2006.173.22:15:58.62#ibcon#about to read 4, iclass 31, count 0 2006.173.22:15:58.62#ibcon#read 4, iclass 31, count 0 2006.173.22:15:58.62#ibcon#about to read 5, iclass 31, count 0 2006.173.22:15:58.62#ibcon#read 5, iclass 31, count 0 2006.173.22:15:58.62#ibcon#about to read 6, iclass 31, count 0 2006.173.22:15:58.62#ibcon#read 6, iclass 31, count 0 2006.173.22:15:58.62#ibcon#end of sib2, iclass 31, count 0 2006.173.22:15:58.62#ibcon#*after write, iclass 31, count 0 2006.173.22:15:58.62#ibcon#*before return 0, iclass 31, count 0 2006.173.22:15:58.62#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.22:15:58.62#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.22:15:58.62#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.22:15:58.62#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.22:15:58.62$vck44/va=5,4 2006.173.22:15:58.62#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.173.22:15:58.62#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.173.22:15:58.62#ibcon#ireg 11 cls_cnt 2 2006.173.22:15:58.62#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.22:15:58.68#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.22:15:58.68#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.22:15:58.68#ibcon#enter wrdev, iclass 33, count 2 2006.173.22:15:58.68#ibcon#first serial, iclass 33, count 2 2006.173.22:15:58.68#ibcon#enter sib2, iclass 33, count 2 2006.173.22:15:58.68#ibcon#flushed, iclass 33, count 2 2006.173.22:15:58.68#ibcon#about to write, iclass 33, count 2 2006.173.22:15:58.68#ibcon#wrote, iclass 33, count 2 2006.173.22:15:58.68#ibcon#about to read 3, iclass 33, count 2 2006.173.22:15:58.70#ibcon#read 3, iclass 33, count 2 2006.173.22:15:58.70#ibcon#about to read 4, iclass 33, count 2 2006.173.22:15:58.70#ibcon#read 4, iclass 33, count 2 2006.173.22:15:58.70#ibcon#about to read 5, iclass 33, count 2 2006.173.22:15:58.70#ibcon#read 5, iclass 33, count 2 2006.173.22:15:58.70#ibcon#about to read 6, iclass 33, count 2 2006.173.22:15:58.70#ibcon#read 6, iclass 33, count 2 2006.173.22:15:58.70#ibcon#end of sib2, iclass 33, count 2 2006.173.22:15:58.70#ibcon#*mode == 0, iclass 33, count 2 2006.173.22:15:58.70#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.173.22:15:58.70#ibcon#[25=AT05-04\r\n] 2006.173.22:15:58.70#ibcon#*before write, iclass 33, count 2 2006.173.22:15:58.70#ibcon#enter sib2, iclass 33, count 2 2006.173.22:15:58.70#ibcon#flushed, iclass 33, count 2 2006.173.22:15:58.70#ibcon#about to write, iclass 33, count 2 2006.173.22:15:58.70#ibcon#wrote, iclass 33, count 2 2006.173.22:15:58.70#ibcon#about to read 3, iclass 33, count 2 2006.173.22:15:58.73#ibcon#read 3, iclass 33, count 2 2006.173.22:15:58.73#ibcon#about to read 4, iclass 33, count 2 2006.173.22:15:58.73#ibcon#read 4, iclass 33, count 2 2006.173.22:15:58.73#ibcon#about to read 5, iclass 33, count 2 2006.173.22:15:58.73#ibcon#read 5, iclass 33, count 2 2006.173.22:15:58.73#ibcon#about to read 6, iclass 33, count 2 2006.173.22:15:58.73#ibcon#read 6, iclass 33, count 2 2006.173.22:15:58.73#ibcon#end of sib2, iclass 33, count 2 2006.173.22:15:58.73#ibcon#*after write, iclass 33, count 2 2006.173.22:15:58.73#ibcon#*before return 0, iclass 33, count 2 2006.173.22:15:58.73#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.22:15:58.73#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.173.22:15:58.73#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.173.22:15:58.73#ibcon#ireg 7 cls_cnt 0 2006.173.22:15:58.73#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.22:15:58.85#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.22:15:58.85#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.22:15:58.85#ibcon#enter wrdev, iclass 33, count 0 2006.173.22:15:58.85#ibcon#first serial, iclass 33, count 0 2006.173.22:15:58.85#ibcon#enter sib2, iclass 33, count 0 2006.173.22:15:58.85#ibcon#flushed, iclass 33, count 0 2006.173.22:15:58.85#ibcon#about to write, iclass 33, count 0 2006.173.22:15:58.85#ibcon#wrote, iclass 33, count 0 2006.173.22:15:58.85#ibcon#about to read 3, iclass 33, count 0 2006.173.22:15:58.87#ibcon#read 3, iclass 33, count 0 2006.173.22:15:58.87#ibcon#about to read 4, iclass 33, count 0 2006.173.22:15:58.87#ibcon#read 4, iclass 33, count 0 2006.173.22:15:58.87#ibcon#about to read 5, iclass 33, count 0 2006.173.22:15:58.87#ibcon#read 5, iclass 33, count 0 2006.173.22:15:58.87#ibcon#about to read 6, iclass 33, count 0 2006.173.22:15:58.87#ibcon#read 6, iclass 33, count 0 2006.173.22:15:58.87#ibcon#end of sib2, iclass 33, count 0 2006.173.22:15:58.87#ibcon#*mode == 0, iclass 33, count 0 2006.173.22:15:58.87#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.22:15:58.87#ibcon#[25=USB\r\n] 2006.173.22:15:58.87#ibcon#*before write, iclass 33, count 0 2006.173.22:15:58.87#ibcon#enter sib2, iclass 33, count 0 2006.173.22:15:58.87#ibcon#flushed, iclass 33, count 0 2006.173.22:15:58.87#ibcon#about to write, iclass 33, count 0 2006.173.22:15:58.87#ibcon#wrote, iclass 33, count 0 2006.173.22:15:58.87#ibcon#about to read 3, iclass 33, count 0 2006.173.22:15:58.90#ibcon#read 3, iclass 33, count 0 2006.173.22:15:58.90#ibcon#about to read 4, iclass 33, count 0 2006.173.22:15:58.90#ibcon#read 4, iclass 33, count 0 2006.173.22:15:58.90#ibcon#about to read 5, iclass 33, count 0 2006.173.22:15:58.90#ibcon#read 5, iclass 33, count 0 2006.173.22:15:58.90#ibcon#about to read 6, iclass 33, count 0 2006.173.22:15:58.90#ibcon#read 6, iclass 33, count 0 2006.173.22:15:58.90#ibcon#end of sib2, iclass 33, count 0 2006.173.22:15:58.90#ibcon#*after write, iclass 33, count 0 2006.173.22:15:58.90#ibcon#*before return 0, iclass 33, count 0 2006.173.22:15:58.90#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.22:15:58.90#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.173.22:15:58.90#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.22:15:58.90#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.22:15:58.90$vck44/valo=6,814.99 2006.173.22:15:58.90#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.22:15:58.90#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.22:15:58.90#ibcon#ireg 17 cls_cnt 0 2006.173.22:15:58.90#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.22:15:58.90#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.22:15:58.90#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.22:15:58.90#ibcon#enter wrdev, iclass 35, count 0 2006.173.22:15:58.90#ibcon#first serial, iclass 35, count 0 2006.173.22:15:58.90#ibcon#enter sib2, iclass 35, count 0 2006.173.22:15:58.90#ibcon#flushed, iclass 35, count 0 2006.173.22:15:58.90#ibcon#about to write, iclass 35, count 0 2006.173.22:15:58.90#ibcon#wrote, iclass 35, count 0 2006.173.22:15:58.90#ibcon#about to read 3, iclass 35, count 0 2006.173.22:15:58.92#ibcon#read 3, iclass 35, count 0 2006.173.22:15:58.92#ibcon#about to read 4, iclass 35, count 0 2006.173.22:15:58.92#ibcon#read 4, iclass 35, count 0 2006.173.22:15:58.92#ibcon#about to read 5, iclass 35, count 0 2006.173.22:15:58.92#ibcon#read 5, iclass 35, count 0 2006.173.22:15:58.92#ibcon#about to read 6, iclass 35, count 0 2006.173.22:15:58.92#ibcon#read 6, iclass 35, count 0 2006.173.22:15:58.92#ibcon#end of sib2, iclass 35, count 0 2006.173.22:15:58.92#ibcon#*mode == 0, iclass 35, count 0 2006.173.22:15:58.92#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.22:15:58.92#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.22:15:58.92#ibcon#*before write, iclass 35, count 0 2006.173.22:15:58.92#ibcon#enter sib2, iclass 35, count 0 2006.173.22:15:58.92#ibcon#flushed, iclass 35, count 0 2006.173.22:15:58.92#ibcon#about to write, iclass 35, count 0 2006.173.22:15:58.92#ibcon#wrote, iclass 35, count 0 2006.173.22:15:58.92#ibcon#about to read 3, iclass 35, count 0 2006.173.22:15:58.96#ibcon#read 3, iclass 35, count 0 2006.173.22:15:58.96#ibcon#about to read 4, iclass 35, count 0 2006.173.22:15:58.96#ibcon#read 4, iclass 35, count 0 2006.173.22:15:58.96#ibcon#about to read 5, iclass 35, count 0 2006.173.22:15:58.96#ibcon#read 5, iclass 35, count 0 2006.173.22:15:58.96#ibcon#about to read 6, iclass 35, count 0 2006.173.22:15:58.96#ibcon#read 6, iclass 35, count 0 2006.173.22:15:58.96#ibcon#end of sib2, iclass 35, count 0 2006.173.22:15:58.96#ibcon#*after write, iclass 35, count 0 2006.173.22:15:58.96#ibcon#*before return 0, iclass 35, count 0 2006.173.22:15:58.96#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.22:15:58.96#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.22:15:58.96#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.22:15:58.96#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.22:15:58.96$vck44/va=6,3 2006.173.22:15:58.96#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.173.22:15:58.96#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.173.22:15:58.96#ibcon#ireg 11 cls_cnt 2 2006.173.22:15:58.96#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.22:15:59.02#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.22:15:59.02#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.22:15:59.02#ibcon#enter wrdev, iclass 37, count 2 2006.173.22:15:59.02#ibcon#first serial, iclass 37, count 2 2006.173.22:15:59.02#ibcon#enter sib2, iclass 37, count 2 2006.173.22:15:59.02#ibcon#flushed, iclass 37, count 2 2006.173.22:15:59.02#ibcon#about to write, iclass 37, count 2 2006.173.22:15:59.02#ibcon#wrote, iclass 37, count 2 2006.173.22:15:59.02#ibcon#about to read 3, iclass 37, count 2 2006.173.22:15:59.04#ibcon#read 3, iclass 37, count 2 2006.173.22:15:59.04#ibcon#about to read 4, iclass 37, count 2 2006.173.22:15:59.04#ibcon#read 4, iclass 37, count 2 2006.173.22:15:59.04#ibcon#about to read 5, iclass 37, count 2 2006.173.22:15:59.04#ibcon#read 5, iclass 37, count 2 2006.173.22:15:59.04#ibcon#about to read 6, iclass 37, count 2 2006.173.22:15:59.04#ibcon#read 6, iclass 37, count 2 2006.173.22:15:59.04#ibcon#end of sib2, iclass 37, count 2 2006.173.22:15:59.04#ibcon#*mode == 0, iclass 37, count 2 2006.173.22:15:59.04#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.173.22:15:59.04#ibcon#[25=AT06-03\r\n] 2006.173.22:15:59.04#ibcon#*before write, iclass 37, count 2 2006.173.22:15:59.04#ibcon#enter sib2, iclass 37, count 2 2006.173.22:15:59.04#ibcon#flushed, iclass 37, count 2 2006.173.22:15:59.04#ibcon#about to write, iclass 37, count 2 2006.173.22:15:59.04#ibcon#wrote, iclass 37, count 2 2006.173.22:15:59.04#ibcon#about to read 3, iclass 37, count 2 2006.173.22:15:59.07#ibcon#read 3, iclass 37, count 2 2006.173.22:15:59.07#ibcon#about to read 4, iclass 37, count 2 2006.173.22:15:59.07#ibcon#read 4, iclass 37, count 2 2006.173.22:15:59.07#ibcon#about to read 5, iclass 37, count 2 2006.173.22:15:59.07#ibcon#read 5, iclass 37, count 2 2006.173.22:15:59.07#ibcon#about to read 6, iclass 37, count 2 2006.173.22:15:59.07#ibcon#read 6, iclass 37, count 2 2006.173.22:15:59.07#ibcon#end of sib2, iclass 37, count 2 2006.173.22:15:59.07#ibcon#*after write, iclass 37, count 2 2006.173.22:15:59.07#ibcon#*before return 0, iclass 37, count 2 2006.173.22:15:59.07#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.22:15:59.07#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.173.22:15:59.07#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.173.22:15:59.07#ibcon#ireg 7 cls_cnt 0 2006.173.22:15:59.07#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.22:15:59.19#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.22:15:59.19#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.22:15:59.19#ibcon#enter wrdev, iclass 37, count 0 2006.173.22:15:59.19#ibcon#first serial, iclass 37, count 0 2006.173.22:15:59.19#ibcon#enter sib2, iclass 37, count 0 2006.173.22:15:59.19#ibcon#flushed, iclass 37, count 0 2006.173.22:15:59.19#ibcon#about to write, iclass 37, count 0 2006.173.22:15:59.19#ibcon#wrote, iclass 37, count 0 2006.173.22:15:59.19#ibcon#about to read 3, iclass 37, count 0 2006.173.22:15:59.21#ibcon#read 3, iclass 37, count 0 2006.173.22:15:59.21#ibcon#about to read 4, iclass 37, count 0 2006.173.22:15:59.21#ibcon#read 4, iclass 37, count 0 2006.173.22:15:59.21#ibcon#about to read 5, iclass 37, count 0 2006.173.22:15:59.21#ibcon#read 5, iclass 37, count 0 2006.173.22:15:59.21#ibcon#about to read 6, iclass 37, count 0 2006.173.22:15:59.21#ibcon#read 6, iclass 37, count 0 2006.173.22:15:59.21#ibcon#end of sib2, iclass 37, count 0 2006.173.22:15:59.21#ibcon#*mode == 0, iclass 37, count 0 2006.173.22:15:59.21#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.22:15:59.21#ibcon#[25=USB\r\n] 2006.173.22:15:59.21#ibcon#*before write, iclass 37, count 0 2006.173.22:15:59.21#ibcon#enter sib2, iclass 37, count 0 2006.173.22:15:59.21#ibcon#flushed, iclass 37, count 0 2006.173.22:15:59.21#ibcon#about to write, iclass 37, count 0 2006.173.22:15:59.21#ibcon#wrote, iclass 37, count 0 2006.173.22:15:59.21#ibcon#about to read 3, iclass 37, count 0 2006.173.22:15:59.24#ibcon#read 3, iclass 37, count 0 2006.173.22:15:59.24#ibcon#about to read 4, iclass 37, count 0 2006.173.22:15:59.24#ibcon#read 4, iclass 37, count 0 2006.173.22:15:59.24#ibcon#about to read 5, iclass 37, count 0 2006.173.22:15:59.24#ibcon#read 5, iclass 37, count 0 2006.173.22:15:59.24#ibcon#about to read 6, iclass 37, count 0 2006.173.22:15:59.24#ibcon#read 6, iclass 37, count 0 2006.173.22:15:59.24#ibcon#end of sib2, iclass 37, count 0 2006.173.22:15:59.24#ibcon#*after write, iclass 37, count 0 2006.173.22:15:59.24#ibcon#*before return 0, iclass 37, count 0 2006.173.22:15:59.24#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.22:15:59.24#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.173.22:15:59.24#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.22:15:59.24#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.22:15:59.24$vck44/valo=7,864.99 2006.173.22:15:59.24#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.22:15:59.24#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.22:15:59.24#ibcon#ireg 17 cls_cnt 0 2006.173.22:15:59.24#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.22:15:59.24#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.22:15:59.24#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.22:15:59.24#ibcon#enter wrdev, iclass 39, count 0 2006.173.22:15:59.24#ibcon#first serial, iclass 39, count 0 2006.173.22:15:59.24#ibcon#enter sib2, iclass 39, count 0 2006.173.22:15:59.24#ibcon#flushed, iclass 39, count 0 2006.173.22:15:59.24#ibcon#about to write, iclass 39, count 0 2006.173.22:15:59.24#ibcon#wrote, iclass 39, count 0 2006.173.22:15:59.24#ibcon#about to read 3, iclass 39, count 0 2006.173.22:15:59.26#ibcon#read 3, iclass 39, count 0 2006.173.22:15:59.26#ibcon#about to read 4, iclass 39, count 0 2006.173.22:15:59.26#ibcon#read 4, iclass 39, count 0 2006.173.22:15:59.26#ibcon#about to read 5, iclass 39, count 0 2006.173.22:15:59.26#ibcon#read 5, iclass 39, count 0 2006.173.22:15:59.26#ibcon#about to read 6, iclass 39, count 0 2006.173.22:15:59.26#ibcon#read 6, iclass 39, count 0 2006.173.22:15:59.26#ibcon#end of sib2, iclass 39, count 0 2006.173.22:15:59.26#ibcon#*mode == 0, iclass 39, count 0 2006.173.22:15:59.26#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.22:15:59.26#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.22:15:59.26#ibcon#*before write, iclass 39, count 0 2006.173.22:15:59.26#ibcon#enter sib2, iclass 39, count 0 2006.173.22:15:59.26#ibcon#flushed, iclass 39, count 0 2006.173.22:15:59.26#ibcon#about to write, iclass 39, count 0 2006.173.22:15:59.26#ibcon#wrote, iclass 39, count 0 2006.173.22:15:59.26#ibcon#about to read 3, iclass 39, count 0 2006.173.22:15:59.30#ibcon#read 3, iclass 39, count 0 2006.173.22:15:59.30#ibcon#about to read 4, iclass 39, count 0 2006.173.22:15:59.30#ibcon#read 4, iclass 39, count 0 2006.173.22:15:59.30#ibcon#about to read 5, iclass 39, count 0 2006.173.22:15:59.30#ibcon#read 5, iclass 39, count 0 2006.173.22:15:59.30#ibcon#about to read 6, iclass 39, count 0 2006.173.22:15:59.30#ibcon#read 6, iclass 39, count 0 2006.173.22:15:59.30#ibcon#end of sib2, iclass 39, count 0 2006.173.22:15:59.30#ibcon#*after write, iclass 39, count 0 2006.173.22:15:59.30#ibcon#*before return 0, iclass 39, count 0 2006.173.22:15:59.30#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.22:15:59.30#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.22:15:59.30#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.22:15:59.30#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.22:15:59.30$vck44/va=7,4 2006.173.22:15:59.30#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.22:15:59.30#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.22:15:59.30#ibcon#ireg 11 cls_cnt 2 2006.173.22:15:59.30#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.22:15:59.36#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.22:15:59.36#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.22:15:59.36#ibcon#enter wrdev, iclass 3, count 2 2006.173.22:15:59.36#ibcon#first serial, iclass 3, count 2 2006.173.22:15:59.36#ibcon#enter sib2, iclass 3, count 2 2006.173.22:15:59.36#ibcon#flushed, iclass 3, count 2 2006.173.22:15:59.36#ibcon#about to write, iclass 3, count 2 2006.173.22:15:59.36#ibcon#wrote, iclass 3, count 2 2006.173.22:15:59.36#ibcon#about to read 3, iclass 3, count 2 2006.173.22:15:59.38#ibcon#read 3, iclass 3, count 2 2006.173.22:15:59.38#ibcon#about to read 4, iclass 3, count 2 2006.173.22:15:59.38#ibcon#read 4, iclass 3, count 2 2006.173.22:15:59.38#ibcon#about to read 5, iclass 3, count 2 2006.173.22:15:59.38#ibcon#read 5, iclass 3, count 2 2006.173.22:15:59.38#ibcon#about to read 6, iclass 3, count 2 2006.173.22:15:59.38#ibcon#read 6, iclass 3, count 2 2006.173.22:15:59.38#ibcon#end of sib2, iclass 3, count 2 2006.173.22:15:59.38#ibcon#*mode == 0, iclass 3, count 2 2006.173.22:15:59.38#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.22:15:59.38#ibcon#[25=AT07-04\r\n] 2006.173.22:15:59.38#ibcon#*before write, iclass 3, count 2 2006.173.22:15:59.38#ibcon#enter sib2, iclass 3, count 2 2006.173.22:15:59.38#ibcon#flushed, iclass 3, count 2 2006.173.22:15:59.38#ibcon#about to write, iclass 3, count 2 2006.173.22:15:59.38#ibcon#wrote, iclass 3, count 2 2006.173.22:15:59.38#ibcon#about to read 3, iclass 3, count 2 2006.173.22:15:59.41#ibcon#read 3, iclass 3, count 2 2006.173.22:15:59.41#ibcon#about to read 4, iclass 3, count 2 2006.173.22:15:59.41#ibcon#read 4, iclass 3, count 2 2006.173.22:15:59.41#ibcon#about to read 5, iclass 3, count 2 2006.173.22:15:59.41#ibcon#read 5, iclass 3, count 2 2006.173.22:15:59.41#ibcon#about to read 6, iclass 3, count 2 2006.173.22:15:59.41#ibcon#read 6, iclass 3, count 2 2006.173.22:15:59.41#ibcon#end of sib2, iclass 3, count 2 2006.173.22:15:59.41#ibcon#*after write, iclass 3, count 2 2006.173.22:15:59.41#ibcon#*before return 0, iclass 3, count 2 2006.173.22:15:59.41#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.22:15:59.41#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.22:15:59.41#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.22:15:59.41#ibcon#ireg 7 cls_cnt 0 2006.173.22:15:59.41#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.22:15:59.53#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.22:15:59.53#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.22:15:59.53#ibcon#enter wrdev, iclass 3, count 0 2006.173.22:15:59.53#ibcon#first serial, iclass 3, count 0 2006.173.22:15:59.53#ibcon#enter sib2, iclass 3, count 0 2006.173.22:15:59.53#ibcon#flushed, iclass 3, count 0 2006.173.22:15:59.53#ibcon#about to write, iclass 3, count 0 2006.173.22:15:59.53#ibcon#wrote, iclass 3, count 0 2006.173.22:15:59.53#ibcon#about to read 3, iclass 3, count 0 2006.173.22:15:59.55#ibcon#read 3, iclass 3, count 0 2006.173.22:15:59.55#ibcon#about to read 4, iclass 3, count 0 2006.173.22:15:59.55#ibcon#read 4, iclass 3, count 0 2006.173.22:15:59.55#ibcon#about to read 5, iclass 3, count 0 2006.173.22:15:59.55#ibcon#read 5, iclass 3, count 0 2006.173.22:15:59.55#ibcon#about to read 6, iclass 3, count 0 2006.173.22:15:59.55#ibcon#read 6, iclass 3, count 0 2006.173.22:15:59.55#ibcon#end of sib2, iclass 3, count 0 2006.173.22:15:59.55#ibcon#*mode == 0, iclass 3, count 0 2006.173.22:15:59.55#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.22:15:59.55#ibcon#[25=USB\r\n] 2006.173.22:15:59.55#ibcon#*before write, iclass 3, count 0 2006.173.22:15:59.55#ibcon#enter sib2, iclass 3, count 0 2006.173.22:15:59.55#ibcon#flushed, iclass 3, count 0 2006.173.22:15:59.55#ibcon#about to write, iclass 3, count 0 2006.173.22:15:59.55#ibcon#wrote, iclass 3, count 0 2006.173.22:15:59.55#ibcon#about to read 3, iclass 3, count 0 2006.173.22:15:59.58#ibcon#read 3, iclass 3, count 0 2006.173.22:15:59.58#ibcon#about to read 4, iclass 3, count 0 2006.173.22:15:59.58#ibcon#read 4, iclass 3, count 0 2006.173.22:15:59.58#ibcon#about to read 5, iclass 3, count 0 2006.173.22:15:59.58#ibcon#read 5, iclass 3, count 0 2006.173.22:15:59.58#ibcon#about to read 6, iclass 3, count 0 2006.173.22:15:59.58#ibcon#read 6, iclass 3, count 0 2006.173.22:15:59.58#ibcon#end of sib2, iclass 3, count 0 2006.173.22:15:59.58#ibcon#*after write, iclass 3, count 0 2006.173.22:15:59.58#ibcon#*before return 0, iclass 3, count 0 2006.173.22:15:59.58#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.22:15:59.58#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.22:15:59.58#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.22:15:59.58#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.22:15:59.58$vck44/valo=8,884.99 2006.173.22:15:59.58#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.22:15:59.58#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.22:15:59.58#ibcon#ireg 17 cls_cnt 0 2006.173.22:15:59.58#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.22:15:59.58#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.22:15:59.58#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.22:15:59.58#ibcon#enter wrdev, iclass 5, count 0 2006.173.22:15:59.58#ibcon#first serial, iclass 5, count 0 2006.173.22:15:59.58#ibcon#enter sib2, iclass 5, count 0 2006.173.22:15:59.58#ibcon#flushed, iclass 5, count 0 2006.173.22:15:59.58#ibcon#about to write, iclass 5, count 0 2006.173.22:15:59.58#ibcon#wrote, iclass 5, count 0 2006.173.22:15:59.58#ibcon#about to read 3, iclass 5, count 0 2006.173.22:15:59.60#ibcon#read 3, iclass 5, count 0 2006.173.22:15:59.60#ibcon#about to read 4, iclass 5, count 0 2006.173.22:15:59.60#ibcon#read 4, iclass 5, count 0 2006.173.22:15:59.60#ibcon#about to read 5, iclass 5, count 0 2006.173.22:15:59.60#ibcon#read 5, iclass 5, count 0 2006.173.22:15:59.60#ibcon#about to read 6, iclass 5, count 0 2006.173.22:15:59.60#ibcon#read 6, iclass 5, count 0 2006.173.22:15:59.60#ibcon#end of sib2, iclass 5, count 0 2006.173.22:15:59.60#ibcon#*mode == 0, iclass 5, count 0 2006.173.22:15:59.60#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.22:15:59.60#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.22:15:59.60#ibcon#*before write, iclass 5, count 0 2006.173.22:15:59.60#ibcon#enter sib2, iclass 5, count 0 2006.173.22:15:59.60#ibcon#flushed, iclass 5, count 0 2006.173.22:15:59.60#ibcon#about to write, iclass 5, count 0 2006.173.22:15:59.60#ibcon#wrote, iclass 5, count 0 2006.173.22:15:59.60#ibcon#about to read 3, iclass 5, count 0 2006.173.22:15:59.64#ibcon#read 3, iclass 5, count 0 2006.173.22:15:59.64#ibcon#about to read 4, iclass 5, count 0 2006.173.22:15:59.64#ibcon#read 4, iclass 5, count 0 2006.173.22:15:59.64#ibcon#about to read 5, iclass 5, count 0 2006.173.22:15:59.64#ibcon#read 5, iclass 5, count 0 2006.173.22:15:59.64#ibcon#about to read 6, iclass 5, count 0 2006.173.22:15:59.64#ibcon#read 6, iclass 5, count 0 2006.173.22:15:59.64#ibcon#end of sib2, iclass 5, count 0 2006.173.22:15:59.64#ibcon#*after write, iclass 5, count 0 2006.173.22:15:59.64#ibcon#*before return 0, iclass 5, count 0 2006.173.22:15:59.64#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.22:15:59.64#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.22:15:59.64#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.22:15:59.64#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.22:15:59.64$vck44/va=8,4 2006.173.22:15:59.64#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.173.22:15:59.64#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.173.22:15:59.64#ibcon#ireg 11 cls_cnt 2 2006.173.22:15:59.64#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.22:15:59.70#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.22:15:59.70#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.22:15:59.70#ibcon#enter wrdev, iclass 7, count 2 2006.173.22:15:59.70#ibcon#first serial, iclass 7, count 2 2006.173.22:15:59.70#ibcon#enter sib2, iclass 7, count 2 2006.173.22:15:59.70#ibcon#flushed, iclass 7, count 2 2006.173.22:15:59.70#ibcon#about to write, iclass 7, count 2 2006.173.22:15:59.70#ibcon#wrote, iclass 7, count 2 2006.173.22:15:59.70#ibcon#about to read 3, iclass 7, count 2 2006.173.22:15:59.72#ibcon#read 3, iclass 7, count 2 2006.173.22:15:59.72#ibcon#about to read 4, iclass 7, count 2 2006.173.22:15:59.72#ibcon#read 4, iclass 7, count 2 2006.173.22:15:59.72#ibcon#about to read 5, iclass 7, count 2 2006.173.22:15:59.72#ibcon#read 5, iclass 7, count 2 2006.173.22:15:59.72#ibcon#about to read 6, iclass 7, count 2 2006.173.22:15:59.72#ibcon#read 6, iclass 7, count 2 2006.173.22:15:59.72#ibcon#end of sib2, iclass 7, count 2 2006.173.22:15:59.72#ibcon#*mode == 0, iclass 7, count 2 2006.173.22:15:59.72#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.173.22:15:59.72#ibcon#[25=AT08-04\r\n] 2006.173.22:15:59.72#ibcon#*before write, iclass 7, count 2 2006.173.22:15:59.72#ibcon#enter sib2, iclass 7, count 2 2006.173.22:15:59.72#ibcon#flushed, iclass 7, count 2 2006.173.22:15:59.72#ibcon#about to write, iclass 7, count 2 2006.173.22:15:59.72#ibcon#wrote, iclass 7, count 2 2006.173.22:15:59.72#ibcon#about to read 3, iclass 7, count 2 2006.173.22:15:59.75#ibcon#read 3, iclass 7, count 2 2006.173.22:15:59.75#ibcon#about to read 4, iclass 7, count 2 2006.173.22:15:59.75#ibcon#read 4, iclass 7, count 2 2006.173.22:15:59.75#ibcon#about to read 5, iclass 7, count 2 2006.173.22:15:59.75#ibcon#read 5, iclass 7, count 2 2006.173.22:15:59.75#ibcon#about to read 6, iclass 7, count 2 2006.173.22:15:59.75#ibcon#read 6, iclass 7, count 2 2006.173.22:15:59.75#ibcon#end of sib2, iclass 7, count 2 2006.173.22:15:59.75#ibcon#*after write, iclass 7, count 2 2006.173.22:15:59.75#ibcon#*before return 0, iclass 7, count 2 2006.173.22:15:59.75#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.22:15:59.75#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.173.22:15:59.75#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.173.22:15:59.75#ibcon#ireg 7 cls_cnt 0 2006.173.22:15:59.75#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.22:15:59.87#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.22:15:59.87#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.22:15:59.87#ibcon#enter wrdev, iclass 7, count 0 2006.173.22:15:59.87#ibcon#first serial, iclass 7, count 0 2006.173.22:15:59.87#ibcon#enter sib2, iclass 7, count 0 2006.173.22:15:59.87#ibcon#flushed, iclass 7, count 0 2006.173.22:15:59.87#ibcon#about to write, iclass 7, count 0 2006.173.22:15:59.87#ibcon#wrote, iclass 7, count 0 2006.173.22:15:59.87#ibcon#about to read 3, iclass 7, count 0 2006.173.22:15:59.89#ibcon#read 3, iclass 7, count 0 2006.173.22:15:59.89#ibcon#about to read 4, iclass 7, count 0 2006.173.22:15:59.89#ibcon#read 4, iclass 7, count 0 2006.173.22:15:59.89#ibcon#about to read 5, iclass 7, count 0 2006.173.22:15:59.89#ibcon#read 5, iclass 7, count 0 2006.173.22:15:59.89#ibcon#about to read 6, iclass 7, count 0 2006.173.22:15:59.89#ibcon#read 6, iclass 7, count 0 2006.173.22:15:59.89#ibcon#end of sib2, iclass 7, count 0 2006.173.22:15:59.89#ibcon#*mode == 0, iclass 7, count 0 2006.173.22:15:59.89#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.22:15:59.89#ibcon#[25=USB\r\n] 2006.173.22:15:59.89#ibcon#*before write, iclass 7, count 0 2006.173.22:15:59.89#ibcon#enter sib2, iclass 7, count 0 2006.173.22:15:59.89#ibcon#flushed, iclass 7, count 0 2006.173.22:15:59.89#ibcon#about to write, iclass 7, count 0 2006.173.22:15:59.89#ibcon#wrote, iclass 7, count 0 2006.173.22:15:59.89#ibcon#about to read 3, iclass 7, count 0 2006.173.22:15:59.92#ibcon#read 3, iclass 7, count 0 2006.173.22:15:59.92#ibcon#about to read 4, iclass 7, count 0 2006.173.22:15:59.92#ibcon#read 4, iclass 7, count 0 2006.173.22:15:59.92#ibcon#about to read 5, iclass 7, count 0 2006.173.22:15:59.92#ibcon#read 5, iclass 7, count 0 2006.173.22:15:59.92#ibcon#about to read 6, iclass 7, count 0 2006.173.22:15:59.92#ibcon#read 6, iclass 7, count 0 2006.173.22:15:59.92#ibcon#end of sib2, iclass 7, count 0 2006.173.22:15:59.92#ibcon#*after write, iclass 7, count 0 2006.173.22:15:59.92#ibcon#*before return 0, iclass 7, count 0 2006.173.22:15:59.92#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.22:15:59.92#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.173.22:15:59.92#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.22:15:59.92#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.22:15:59.92$vck44/vblo=1,629.99 2006.173.22:15:59.92#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.22:15:59.92#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.22:15:59.92#ibcon#ireg 17 cls_cnt 0 2006.173.22:15:59.92#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.22:15:59.92#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.22:15:59.92#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.22:15:59.92#ibcon#enter wrdev, iclass 11, count 0 2006.173.22:15:59.92#ibcon#first serial, iclass 11, count 0 2006.173.22:15:59.92#ibcon#enter sib2, iclass 11, count 0 2006.173.22:15:59.92#ibcon#flushed, iclass 11, count 0 2006.173.22:15:59.92#ibcon#about to write, iclass 11, count 0 2006.173.22:15:59.92#ibcon#wrote, iclass 11, count 0 2006.173.22:15:59.92#ibcon#about to read 3, iclass 11, count 0 2006.173.22:15:59.94#ibcon#read 3, iclass 11, count 0 2006.173.22:15:59.94#ibcon#about to read 4, iclass 11, count 0 2006.173.22:15:59.94#ibcon#read 4, iclass 11, count 0 2006.173.22:15:59.94#ibcon#about to read 5, iclass 11, count 0 2006.173.22:15:59.94#ibcon#read 5, iclass 11, count 0 2006.173.22:15:59.94#ibcon#about to read 6, iclass 11, count 0 2006.173.22:15:59.94#ibcon#read 6, iclass 11, count 0 2006.173.22:15:59.94#ibcon#end of sib2, iclass 11, count 0 2006.173.22:15:59.94#ibcon#*mode == 0, iclass 11, count 0 2006.173.22:15:59.94#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.22:15:59.94#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.22:15:59.94#ibcon#*before write, iclass 11, count 0 2006.173.22:15:59.94#ibcon#enter sib2, iclass 11, count 0 2006.173.22:15:59.94#ibcon#flushed, iclass 11, count 0 2006.173.22:15:59.94#ibcon#about to write, iclass 11, count 0 2006.173.22:15:59.94#ibcon#wrote, iclass 11, count 0 2006.173.22:15:59.94#ibcon#about to read 3, iclass 11, count 0 2006.173.22:15:59.98#ibcon#read 3, iclass 11, count 0 2006.173.22:15:59.98#ibcon#about to read 4, iclass 11, count 0 2006.173.22:15:59.98#ibcon#read 4, iclass 11, count 0 2006.173.22:15:59.98#ibcon#about to read 5, iclass 11, count 0 2006.173.22:15:59.98#ibcon#read 5, iclass 11, count 0 2006.173.22:15:59.98#ibcon#about to read 6, iclass 11, count 0 2006.173.22:15:59.98#ibcon#read 6, iclass 11, count 0 2006.173.22:15:59.98#ibcon#end of sib2, iclass 11, count 0 2006.173.22:15:59.98#ibcon#*after write, iclass 11, count 0 2006.173.22:15:59.98#ibcon#*before return 0, iclass 11, count 0 2006.173.22:15:59.98#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.22:15:59.98#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.22:15:59.98#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.22:15:59.98#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.22:15:59.98$vck44/vb=1,4 2006.173.22:15:59.98#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.173.22:15:59.98#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.173.22:15:59.98#ibcon#ireg 11 cls_cnt 2 2006.173.22:15:59.98#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.22:15:59.98#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.22:15:59.98#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.22:15:59.98#ibcon#enter wrdev, iclass 13, count 2 2006.173.22:15:59.98#ibcon#first serial, iclass 13, count 2 2006.173.22:15:59.98#ibcon#enter sib2, iclass 13, count 2 2006.173.22:15:59.98#ibcon#flushed, iclass 13, count 2 2006.173.22:15:59.98#ibcon#about to write, iclass 13, count 2 2006.173.22:15:59.98#ibcon#wrote, iclass 13, count 2 2006.173.22:15:59.98#ibcon#about to read 3, iclass 13, count 2 2006.173.22:16:00.00#ibcon#read 3, iclass 13, count 2 2006.173.22:16:00.00#ibcon#about to read 4, iclass 13, count 2 2006.173.22:16:00.00#ibcon#read 4, iclass 13, count 2 2006.173.22:16:00.00#ibcon#about to read 5, iclass 13, count 2 2006.173.22:16:00.00#ibcon#read 5, iclass 13, count 2 2006.173.22:16:00.00#ibcon#about to read 6, iclass 13, count 2 2006.173.22:16:00.00#ibcon#read 6, iclass 13, count 2 2006.173.22:16:00.00#ibcon#end of sib2, iclass 13, count 2 2006.173.22:16:00.00#ibcon#*mode == 0, iclass 13, count 2 2006.173.22:16:00.00#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.173.22:16:00.00#ibcon#[27=AT01-04\r\n] 2006.173.22:16:00.00#ibcon#*before write, iclass 13, count 2 2006.173.22:16:00.00#ibcon#enter sib2, iclass 13, count 2 2006.173.22:16:00.00#ibcon#flushed, iclass 13, count 2 2006.173.22:16:00.00#ibcon#about to write, iclass 13, count 2 2006.173.22:16:00.00#ibcon#wrote, iclass 13, count 2 2006.173.22:16:00.00#ibcon#about to read 3, iclass 13, count 2 2006.173.22:16:00.03#ibcon#read 3, iclass 13, count 2 2006.173.22:16:00.03#ibcon#about to read 4, iclass 13, count 2 2006.173.22:16:00.03#ibcon#read 4, iclass 13, count 2 2006.173.22:16:00.03#ibcon#about to read 5, iclass 13, count 2 2006.173.22:16:00.03#ibcon#read 5, iclass 13, count 2 2006.173.22:16:00.03#ibcon#about to read 6, iclass 13, count 2 2006.173.22:16:00.03#ibcon#read 6, iclass 13, count 2 2006.173.22:16:00.03#ibcon#end of sib2, iclass 13, count 2 2006.173.22:16:00.03#ibcon#*after write, iclass 13, count 2 2006.173.22:16:00.03#ibcon#*before return 0, iclass 13, count 2 2006.173.22:16:00.03#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.22:16:00.03#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.173.22:16:00.03#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.173.22:16:00.03#ibcon#ireg 7 cls_cnt 0 2006.173.22:16:00.03#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.22:16:00.15#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.22:16:00.15#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.22:16:00.15#ibcon#enter wrdev, iclass 13, count 0 2006.173.22:16:00.15#ibcon#first serial, iclass 13, count 0 2006.173.22:16:00.15#ibcon#enter sib2, iclass 13, count 0 2006.173.22:16:00.15#ibcon#flushed, iclass 13, count 0 2006.173.22:16:00.15#ibcon#about to write, iclass 13, count 0 2006.173.22:16:00.15#ibcon#wrote, iclass 13, count 0 2006.173.22:16:00.15#ibcon#about to read 3, iclass 13, count 0 2006.173.22:16:00.17#ibcon#read 3, iclass 13, count 0 2006.173.22:16:00.17#ibcon#about to read 4, iclass 13, count 0 2006.173.22:16:00.17#ibcon#read 4, iclass 13, count 0 2006.173.22:16:00.17#ibcon#about to read 5, iclass 13, count 0 2006.173.22:16:00.17#ibcon#read 5, iclass 13, count 0 2006.173.22:16:00.17#ibcon#about to read 6, iclass 13, count 0 2006.173.22:16:00.17#ibcon#read 6, iclass 13, count 0 2006.173.22:16:00.17#ibcon#end of sib2, iclass 13, count 0 2006.173.22:16:00.17#ibcon#*mode == 0, iclass 13, count 0 2006.173.22:16:00.17#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.22:16:00.17#ibcon#[27=USB\r\n] 2006.173.22:16:00.17#ibcon#*before write, iclass 13, count 0 2006.173.22:16:00.17#ibcon#enter sib2, iclass 13, count 0 2006.173.22:16:00.17#ibcon#flushed, iclass 13, count 0 2006.173.22:16:00.17#ibcon#about to write, iclass 13, count 0 2006.173.22:16:00.17#ibcon#wrote, iclass 13, count 0 2006.173.22:16:00.17#ibcon#about to read 3, iclass 13, count 0 2006.173.22:16:00.20#ibcon#read 3, iclass 13, count 0 2006.173.22:16:00.20#ibcon#about to read 4, iclass 13, count 0 2006.173.22:16:00.20#ibcon#read 4, iclass 13, count 0 2006.173.22:16:00.20#ibcon#about to read 5, iclass 13, count 0 2006.173.22:16:00.20#ibcon#read 5, iclass 13, count 0 2006.173.22:16:00.20#ibcon#about to read 6, iclass 13, count 0 2006.173.22:16:00.20#ibcon#read 6, iclass 13, count 0 2006.173.22:16:00.20#ibcon#end of sib2, iclass 13, count 0 2006.173.22:16:00.20#ibcon#*after write, iclass 13, count 0 2006.173.22:16:00.20#ibcon#*before return 0, iclass 13, count 0 2006.173.22:16:00.20#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.22:16:00.20#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.173.22:16:00.20#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.22:16:00.20#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.22:16:00.20$vck44/vblo=2,634.99 2006.173.22:16:00.20#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.22:16:00.20#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.22:16:00.20#ibcon#ireg 17 cls_cnt 0 2006.173.22:16:00.20#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.22:16:00.20#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.22:16:00.20#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.22:16:00.20#ibcon#enter wrdev, iclass 15, count 0 2006.173.22:16:00.20#ibcon#first serial, iclass 15, count 0 2006.173.22:16:00.20#ibcon#enter sib2, iclass 15, count 0 2006.173.22:16:00.20#ibcon#flushed, iclass 15, count 0 2006.173.22:16:00.20#ibcon#about to write, iclass 15, count 0 2006.173.22:16:00.20#ibcon#wrote, iclass 15, count 0 2006.173.22:16:00.20#ibcon#about to read 3, iclass 15, count 0 2006.173.22:16:00.22#ibcon#read 3, iclass 15, count 0 2006.173.22:16:00.22#ibcon#about to read 4, iclass 15, count 0 2006.173.22:16:00.22#ibcon#read 4, iclass 15, count 0 2006.173.22:16:00.22#ibcon#about to read 5, iclass 15, count 0 2006.173.22:16:00.22#ibcon#read 5, iclass 15, count 0 2006.173.22:16:00.22#ibcon#about to read 6, iclass 15, count 0 2006.173.22:16:00.22#ibcon#read 6, iclass 15, count 0 2006.173.22:16:00.22#ibcon#end of sib2, iclass 15, count 0 2006.173.22:16:00.22#ibcon#*mode == 0, iclass 15, count 0 2006.173.22:16:00.22#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.22:16:00.22#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.22:16:00.22#ibcon#*before write, iclass 15, count 0 2006.173.22:16:00.22#ibcon#enter sib2, iclass 15, count 0 2006.173.22:16:00.22#ibcon#flushed, iclass 15, count 0 2006.173.22:16:00.22#ibcon#about to write, iclass 15, count 0 2006.173.22:16:00.22#ibcon#wrote, iclass 15, count 0 2006.173.22:16:00.22#ibcon#about to read 3, iclass 15, count 0 2006.173.22:16:00.26#ibcon#read 3, iclass 15, count 0 2006.173.22:16:00.26#ibcon#about to read 4, iclass 15, count 0 2006.173.22:16:00.26#ibcon#read 4, iclass 15, count 0 2006.173.22:16:00.26#ibcon#about to read 5, iclass 15, count 0 2006.173.22:16:00.26#ibcon#read 5, iclass 15, count 0 2006.173.22:16:00.26#ibcon#about to read 6, iclass 15, count 0 2006.173.22:16:00.26#ibcon#read 6, iclass 15, count 0 2006.173.22:16:00.26#ibcon#end of sib2, iclass 15, count 0 2006.173.22:16:00.26#ibcon#*after write, iclass 15, count 0 2006.173.22:16:00.26#ibcon#*before return 0, iclass 15, count 0 2006.173.22:16:00.26#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.22:16:00.26#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.22:16:00.26#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.22:16:00.26#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.22:16:00.26$vck44/vb=2,4 2006.173.22:16:00.26#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.22:16:00.26#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.22:16:00.26#ibcon#ireg 11 cls_cnt 2 2006.173.22:16:00.26#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.22:16:00.32#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.22:16:00.32#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.22:16:00.32#ibcon#enter wrdev, iclass 17, count 2 2006.173.22:16:00.32#ibcon#first serial, iclass 17, count 2 2006.173.22:16:00.32#ibcon#enter sib2, iclass 17, count 2 2006.173.22:16:00.32#ibcon#flushed, iclass 17, count 2 2006.173.22:16:00.32#ibcon#about to write, iclass 17, count 2 2006.173.22:16:00.32#ibcon#wrote, iclass 17, count 2 2006.173.22:16:00.32#ibcon#about to read 3, iclass 17, count 2 2006.173.22:16:00.34#ibcon#read 3, iclass 17, count 2 2006.173.22:16:00.34#ibcon#about to read 4, iclass 17, count 2 2006.173.22:16:00.34#ibcon#read 4, iclass 17, count 2 2006.173.22:16:00.34#ibcon#about to read 5, iclass 17, count 2 2006.173.22:16:00.34#ibcon#read 5, iclass 17, count 2 2006.173.22:16:00.34#ibcon#about to read 6, iclass 17, count 2 2006.173.22:16:00.34#ibcon#read 6, iclass 17, count 2 2006.173.22:16:00.34#ibcon#end of sib2, iclass 17, count 2 2006.173.22:16:00.34#ibcon#*mode == 0, iclass 17, count 2 2006.173.22:16:00.34#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.22:16:00.34#ibcon#[27=AT02-04\r\n] 2006.173.22:16:00.34#ibcon#*before write, iclass 17, count 2 2006.173.22:16:00.34#ibcon#enter sib2, iclass 17, count 2 2006.173.22:16:00.34#ibcon#flushed, iclass 17, count 2 2006.173.22:16:00.34#ibcon#about to write, iclass 17, count 2 2006.173.22:16:00.34#ibcon#wrote, iclass 17, count 2 2006.173.22:16:00.34#ibcon#about to read 3, iclass 17, count 2 2006.173.22:16:00.37#ibcon#read 3, iclass 17, count 2 2006.173.22:16:00.37#ibcon#about to read 4, iclass 17, count 2 2006.173.22:16:00.37#ibcon#read 4, iclass 17, count 2 2006.173.22:16:00.37#ibcon#about to read 5, iclass 17, count 2 2006.173.22:16:00.37#ibcon#read 5, iclass 17, count 2 2006.173.22:16:00.37#ibcon#about to read 6, iclass 17, count 2 2006.173.22:16:00.37#ibcon#read 6, iclass 17, count 2 2006.173.22:16:00.37#ibcon#end of sib2, iclass 17, count 2 2006.173.22:16:00.37#ibcon#*after write, iclass 17, count 2 2006.173.22:16:00.37#ibcon#*before return 0, iclass 17, count 2 2006.173.22:16:00.37#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.22:16:00.37#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.22:16:00.37#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.22:16:00.37#ibcon#ireg 7 cls_cnt 0 2006.173.22:16:00.37#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.22:16:00.49#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.22:16:00.49#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.22:16:00.49#ibcon#enter wrdev, iclass 17, count 0 2006.173.22:16:00.49#ibcon#first serial, iclass 17, count 0 2006.173.22:16:00.49#ibcon#enter sib2, iclass 17, count 0 2006.173.22:16:00.49#ibcon#flushed, iclass 17, count 0 2006.173.22:16:00.49#ibcon#about to write, iclass 17, count 0 2006.173.22:16:00.49#ibcon#wrote, iclass 17, count 0 2006.173.22:16:00.49#ibcon#about to read 3, iclass 17, count 0 2006.173.22:16:00.51#ibcon#read 3, iclass 17, count 0 2006.173.22:16:00.51#ibcon#about to read 4, iclass 17, count 0 2006.173.22:16:00.51#ibcon#read 4, iclass 17, count 0 2006.173.22:16:00.51#ibcon#about to read 5, iclass 17, count 0 2006.173.22:16:00.51#ibcon#read 5, iclass 17, count 0 2006.173.22:16:00.51#ibcon#about to read 6, iclass 17, count 0 2006.173.22:16:00.51#ibcon#read 6, iclass 17, count 0 2006.173.22:16:00.51#ibcon#end of sib2, iclass 17, count 0 2006.173.22:16:00.51#ibcon#*mode == 0, iclass 17, count 0 2006.173.22:16:00.51#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.22:16:00.51#ibcon#[27=USB\r\n] 2006.173.22:16:00.51#ibcon#*before write, iclass 17, count 0 2006.173.22:16:00.51#ibcon#enter sib2, iclass 17, count 0 2006.173.22:16:00.51#ibcon#flushed, iclass 17, count 0 2006.173.22:16:00.51#ibcon#about to write, iclass 17, count 0 2006.173.22:16:00.51#ibcon#wrote, iclass 17, count 0 2006.173.22:16:00.51#ibcon#about to read 3, iclass 17, count 0 2006.173.22:16:00.54#ibcon#read 3, iclass 17, count 0 2006.173.22:16:00.54#ibcon#about to read 4, iclass 17, count 0 2006.173.22:16:00.54#ibcon#read 4, iclass 17, count 0 2006.173.22:16:00.54#ibcon#about to read 5, iclass 17, count 0 2006.173.22:16:00.54#ibcon#read 5, iclass 17, count 0 2006.173.22:16:00.54#ibcon#about to read 6, iclass 17, count 0 2006.173.22:16:00.54#ibcon#read 6, iclass 17, count 0 2006.173.22:16:00.54#ibcon#end of sib2, iclass 17, count 0 2006.173.22:16:00.54#ibcon#*after write, iclass 17, count 0 2006.173.22:16:00.54#ibcon#*before return 0, iclass 17, count 0 2006.173.22:16:00.54#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.22:16:00.54#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.22:16:00.54#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.22:16:00.54#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.22:16:00.54$vck44/vblo=3,649.99 2006.173.22:16:00.54#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.22:16:00.54#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.22:16:00.54#ibcon#ireg 17 cls_cnt 0 2006.173.22:16:00.54#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.22:16:00.54#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.22:16:00.54#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.22:16:00.54#ibcon#enter wrdev, iclass 19, count 0 2006.173.22:16:00.54#ibcon#first serial, iclass 19, count 0 2006.173.22:16:00.54#ibcon#enter sib2, iclass 19, count 0 2006.173.22:16:00.54#ibcon#flushed, iclass 19, count 0 2006.173.22:16:00.54#ibcon#about to write, iclass 19, count 0 2006.173.22:16:00.54#ibcon#wrote, iclass 19, count 0 2006.173.22:16:00.54#ibcon#about to read 3, iclass 19, count 0 2006.173.22:16:00.56#ibcon#read 3, iclass 19, count 0 2006.173.22:16:00.56#ibcon#about to read 4, iclass 19, count 0 2006.173.22:16:00.56#ibcon#read 4, iclass 19, count 0 2006.173.22:16:00.56#ibcon#about to read 5, iclass 19, count 0 2006.173.22:16:00.56#ibcon#read 5, iclass 19, count 0 2006.173.22:16:00.56#ibcon#about to read 6, iclass 19, count 0 2006.173.22:16:00.56#ibcon#read 6, iclass 19, count 0 2006.173.22:16:00.56#ibcon#end of sib2, iclass 19, count 0 2006.173.22:16:00.56#ibcon#*mode == 0, iclass 19, count 0 2006.173.22:16:00.56#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.22:16:00.56#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.22:16:00.56#ibcon#*before write, iclass 19, count 0 2006.173.22:16:00.56#ibcon#enter sib2, iclass 19, count 0 2006.173.22:16:00.56#ibcon#flushed, iclass 19, count 0 2006.173.22:16:00.56#ibcon#about to write, iclass 19, count 0 2006.173.22:16:00.56#ibcon#wrote, iclass 19, count 0 2006.173.22:16:00.56#ibcon#about to read 3, iclass 19, count 0 2006.173.22:16:00.60#ibcon#read 3, iclass 19, count 0 2006.173.22:16:00.60#ibcon#about to read 4, iclass 19, count 0 2006.173.22:16:00.60#ibcon#read 4, iclass 19, count 0 2006.173.22:16:00.60#ibcon#about to read 5, iclass 19, count 0 2006.173.22:16:00.60#ibcon#read 5, iclass 19, count 0 2006.173.22:16:00.60#ibcon#about to read 6, iclass 19, count 0 2006.173.22:16:00.60#ibcon#read 6, iclass 19, count 0 2006.173.22:16:00.60#ibcon#end of sib2, iclass 19, count 0 2006.173.22:16:00.60#ibcon#*after write, iclass 19, count 0 2006.173.22:16:00.60#ibcon#*before return 0, iclass 19, count 0 2006.173.22:16:00.60#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.22:16:00.60#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.22:16:00.60#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.22:16:00.60#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.22:16:00.60$vck44/vb=3,4 2006.173.22:16:00.60#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.22:16:00.60#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.22:16:00.60#ibcon#ireg 11 cls_cnt 2 2006.173.22:16:00.60#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.22:16:00.66#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.22:16:00.66#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.22:16:00.66#ibcon#enter wrdev, iclass 21, count 2 2006.173.22:16:00.66#ibcon#first serial, iclass 21, count 2 2006.173.22:16:00.66#ibcon#enter sib2, iclass 21, count 2 2006.173.22:16:00.66#ibcon#flushed, iclass 21, count 2 2006.173.22:16:00.66#ibcon#about to write, iclass 21, count 2 2006.173.22:16:00.66#ibcon#wrote, iclass 21, count 2 2006.173.22:16:00.66#ibcon#about to read 3, iclass 21, count 2 2006.173.22:16:00.68#ibcon#read 3, iclass 21, count 2 2006.173.22:16:00.68#ibcon#about to read 4, iclass 21, count 2 2006.173.22:16:00.68#ibcon#read 4, iclass 21, count 2 2006.173.22:16:00.68#ibcon#about to read 5, iclass 21, count 2 2006.173.22:16:00.68#ibcon#read 5, iclass 21, count 2 2006.173.22:16:00.68#ibcon#about to read 6, iclass 21, count 2 2006.173.22:16:00.68#ibcon#read 6, iclass 21, count 2 2006.173.22:16:00.68#ibcon#end of sib2, iclass 21, count 2 2006.173.22:16:00.68#ibcon#*mode == 0, iclass 21, count 2 2006.173.22:16:00.68#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.22:16:00.68#ibcon#[27=AT03-04\r\n] 2006.173.22:16:00.68#ibcon#*before write, iclass 21, count 2 2006.173.22:16:00.68#ibcon#enter sib2, iclass 21, count 2 2006.173.22:16:00.68#ibcon#flushed, iclass 21, count 2 2006.173.22:16:00.68#ibcon#about to write, iclass 21, count 2 2006.173.22:16:00.68#ibcon#wrote, iclass 21, count 2 2006.173.22:16:00.68#ibcon#about to read 3, iclass 21, count 2 2006.173.22:16:00.71#ibcon#read 3, iclass 21, count 2 2006.173.22:16:00.71#ibcon#about to read 4, iclass 21, count 2 2006.173.22:16:00.71#ibcon#read 4, iclass 21, count 2 2006.173.22:16:00.71#ibcon#about to read 5, iclass 21, count 2 2006.173.22:16:00.71#ibcon#read 5, iclass 21, count 2 2006.173.22:16:00.71#ibcon#about to read 6, iclass 21, count 2 2006.173.22:16:00.71#ibcon#read 6, iclass 21, count 2 2006.173.22:16:00.71#ibcon#end of sib2, iclass 21, count 2 2006.173.22:16:00.71#ibcon#*after write, iclass 21, count 2 2006.173.22:16:00.71#ibcon#*before return 0, iclass 21, count 2 2006.173.22:16:00.71#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.22:16:00.71#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.22:16:00.71#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.22:16:00.71#ibcon#ireg 7 cls_cnt 0 2006.173.22:16:00.71#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.22:16:00.83#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.22:16:00.83#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.22:16:00.83#ibcon#enter wrdev, iclass 21, count 0 2006.173.22:16:00.83#ibcon#first serial, iclass 21, count 0 2006.173.22:16:00.83#ibcon#enter sib2, iclass 21, count 0 2006.173.22:16:00.83#ibcon#flushed, iclass 21, count 0 2006.173.22:16:00.83#ibcon#about to write, iclass 21, count 0 2006.173.22:16:00.83#ibcon#wrote, iclass 21, count 0 2006.173.22:16:00.83#ibcon#about to read 3, iclass 21, count 0 2006.173.22:16:00.85#ibcon#read 3, iclass 21, count 0 2006.173.22:16:00.85#ibcon#about to read 4, iclass 21, count 0 2006.173.22:16:00.85#ibcon#read 4, iclass 21, count 0 2006.173.22:16:00.85#ibcon#about to read 5, iclass 21, count 0 2006.173.22:16:00.85#ibcon#read 5, iclass 21, count 0 2006.173.22:16:00.85#ibcon#about to read 6, iclass 21, count 0 2006.173.22:16:00.85#ibcon#read 6, iclass 21, count 0 2006.173.22:16:00.85#ibcon#end of sib2, iclass 21, count 0 2006.173.22:16:00.85#ibcon#*mode == 0, iclass 21, count 0 2006.173.22:16:00.85#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.22:16:00.85#ibcon#[27=USB\r\n] 2006.173.22:16:00.85#ibcon#*before write, iclass 21, count 0 2006.173.22:16:00.85#ibcon#enter sib2, iclass 21, count 0 2006.173.22:16:00.85#ibcon#flushed, iclass 21, count 0 2006.173.22:16:00.85#ibcon#about to write, iclass 21, count 0 2006.173.22:16:00.85#ibcon#wrote, iclass 21, count 0 2006.173.22:16:00.85#ibcon#about to read 3, iclass 21, count 0 2006.173.22:16:00.88#ibcon#read 3, iclass 21, count 0 2006.173.22:16:00.88#ibcon#about to read 4, iclass 21, count 0 2006.173.22:16:00.88#ibcon#read 4, iclass 21, count 0 2006.173.22:16:00.88#ibcon#about to read 5, iclass 21, count 0 2006.173.22:16:00.88#ibcon#read 5, iclass 21, count 0 2006.173.22:16:00.88#ibcon#about to read 6, iclass 21, count 0 2006.173.22:16:00.88#ibcon#read 6, iclass 21, count 0 2006.173.22:16:00.88#ibcon#end of sib2, iclass 21, count 0 2006.173.22:16:00.88#ibcon#*after write, iclass 21, count 0 2006.173.22:16:00.88#ibcon#*before return 0, iclass 21, count 0 2006.173.22:16:00.88#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.22:16:00.88#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.22:16:00.88#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.22:16:00.88#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.22:16:00.88$vck44/vblo=4,679.99 2006.173.22:16:00.88#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.22:16:00.88#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.22:16:00.88#ibcon#ireg 17 cls_cnt 0 2006.173.22:16:00.88#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.22:16:00.88#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.22:16:00.88#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.22:16:00.88#ibcon#enter wrdev, iclass 23, count 0 2006.173.22:16:00.88#ibcon#first serial, iclass 23, count 0 2006.173.22:16:00.88#ibcon#enter sib2, iclass 23, count 0 2006.173.22:16:00.88#ibcon#flushed, iclass 23, count 0 2006.173.22:16:00.88#ibcon#about to write, iclass 23, count 0 2006.173.22:16:00.88#ibcon#wrote, iclass 23, count 0 2006.173.22:16:00.88#ibcon#about to read 3, iclass 23, count 0 2006.173.22:16:00.90#ibcon#read 3, iclass 23, count 0 2006.173.22:16:00.90#ibcon#about to read 4, iclass 23, count 0 2006.173.22:16:00.90#ibcon#read 4, iclass 23, count 0 2006.173.22:16:00.90#ibcon#about to read 5, iclass 23, count 0 2006.173.22:16:00.90#ibcon#read 5, iclass 23, count 0 2006.173.22:16:00.90#ibcon#about to read 6, iclass 23, count 0 2006.173.22:16:00.90#ibcon#read 6, iclass 23, count 0 2006.173.22:16:00.90#ibcon#end of sib2, iclass 23, count 0 2006.173.22:16:00.90#ibcon#*mode == 0, iclass 23, count 0 2006.173.22:16:00.90#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.22:16:00.90#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.22:16:00.90#ibcon#*before write, iclass 23, count 0 2006.173.22:16:00.90#ibcon#enter sib2, iclass 23, count 0 2006.173.22:16:00.90#ibcon#flushed, iclass 23, count 0 2006.173.22:16:00.90#ibcon#about to write, iclass 23, count 0 2006.173.22:16:00.90#ibcon#wrote, iclass 23, count 0 2006.173.22:16:00.90#ibcon#about to read 3, iclass 23, count 0 2006.173.22:16:00.94#ibcon#read 3, iclass 23, count 0 2006.173.22:16:00.94#ibcon#about to read 4, iclass 23, count 0 2006.173.22:16:00.94#ibcon#read 4, iclass 23, count 0 2006.173.22:16:00.94#ibcon#about to read 5, iclass 23, count 0 2006.173.22:16:00.94#ibcon#read 5, iclass 23, count 0 2006.173.22:16:00.94#ibcon#about to read 6, iclass 23, count 0 2006.173.22:16:00.94#ibcon#read 6, iclass 23, count 0 2006.173.22:16:00.94#ibcon#end of sib2, iclass 23, count 0 2006.173.22:16:00.94#ibcon#*after write, iclass 23, count 0 2006.173.22:16:00.94#ibcon#*before return 0, iclass 23, count 0 2006.173.22:16:00.94#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.22:16:00.94#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.22:16:00.94#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.22:16:00.94#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.22:16:00.94$vck44/vb=4,4 2006.173.22:16:00.94#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.22:16:00.94#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.22:16:00.94#ibcon#ireg 11 cls_cnt 2 2006.173.22:16:00.94#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.22:16:01.00#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.22:16:01.00#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.22:16:01.00#ibcon#enter wrdev, iclass 25, count 2 2006.173.22:16:01.00#ibcon#first serial, iclass 25, count 2 2006.173.22:16:01.00#ibcon#enter sib2, iclass 25, count 2 2006.173.22:16:01.00#ibcon#flushed, iclass 25, count 2 2006.173.22:16:01.00#ibcon#about to write, iclass 25, count 2 2006.173.22:16:01.00#ibcon#wrote, iclass 25, count 2 2006.173.22:16:01.00#ibcon#about to read 3, iclass 25, count 2 2006.173.22:16:01.02#ibcon#read 3, iclass 25, count 2 2006.173.22:16:01.02#ibcon#about to read 4, iclass 25, count 2 2006.173.22:16:01.02#ibcon#read 4, iclass 25, count 2 2006.173.22:16:01.02#ibcon#about to read 5, iclass 25, count 2 2006.173.22:16:01.02#ibcon#read 5, iclass 25, count 2 2006.173.22:16:01.02#ibcon#about to read 6, iclass 25, count 2 2006.173.22:16:01.02#ibcon#read 6, iclass 25, count 2 2006.173.22:16:01.02#ibcon#end of sib2, iclass 25, count 2 2006.173.22:16:01.02#ibcon#*mode == 0, iclass 25, count 2 2006.173.22:16:01.02#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.22:16:01.02#ibcon#[27=AT04-04\r\n] 2006.173.22:16:01.02#ibcon#*before write, iclass 25, count 2 2006.173.22:16:01.02#ibcon#enter sib2, iclass 25, count 2 2006.173.22:16:01.02#ibcon#flushed, iclass 25, count 2 2006.173.22:16:01.02#ibcon#about to write, iclass 25, count 2 2006.173.22:16:01.02#ibcon#wrote, iclass 25, count 2 2006.173.22:16:01.02#ibcon#about to read 3, iclass 25, count 2 2006.173.22:16:01.05#ibcon#read 3, iclass 25, count 2 2006.173.22:16:01.05#ibcon#about to read 4, iclass 25, count 2 2006.173.22:16:01.05#ibcon#read 4, iclass 25, count 2 2006.173.22:16:01.05#ibcon#about to read 5, iclass 25, count 2 2006.173.22:16:01.05#ibcon#read 5, iclass 25, count 2 2006.173.22:16:01.05#ibcon#about to read 6, iclass 25, count 2 2006.173.22:16:01.05#ibcon#read 6, iclass 25, count 2 2006.173.22:16:01.05#ibcon#end of sib2, iclass 25, count 2 2006.173.22:16:01.05#ibcon#*after write, iclass 25, count 2 2006.173.22:16:01.05#ibcon#*before return 0, iclass 25, count 2 2006.173.22:16:01.05#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.22:16:01.05#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.22:16:01.05#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.22:16:01.05#ibcon#ireg 7 cls_cnt 0 2006.173.22:16:01.05#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.22:16:01.17#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.22:16:01.17#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.22:16:01.17#ibcon#enter wrdev, iclass 25, count 0 2006.173.22:16:01.17#ibcon#first serial, iclass 25, count 0 2006.173.22:16:01.17#ibcon#enter sib2, iclass 25, count 0 2006.173.22:16:01.17#ibcon#flushed, iclass 25, count 0 2006.173.22:16:01.17#ibcon#about to write, iclass 25, count 0 2006.173.22:16:01.17#ibcon#wrote, iclass 25, count 0 2006.173.22:16:01.17#ibcon#about to read 3, iclass 25, count 0 2006.173.22:16:01.19#ibcon#read 3, iclass 25, count 0 2006.173.22:16:01.19#ibcon#about to read 4, iclass 25, count 0 2006.173.22:16:01.19#ibcon#read 4, iclass 25, count 0 2006.173.22:16:01.19#ibcon#about to read 5, iclass 25, count 0 2006.173.22:16:01.19#ibcon#read 5, iclass 25, count 0 2006.173.22:16:01.19#ibcon#about to read 6, iclass 25, count 0 2006.173.22:16:01.19#ibcon#read 6, iclass 25, count 0 2006.173.22:16:01.19#ibcon#end of sib2, iclass 25, count 0 2006.173.22:16:01.19#ibcon#*mode == 0, iclass 25, count 0 2006.173.22:16:01.19#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.22:16:01.19#ibcon#[27=USB\r\n] 2006.173.22:16:01.19#ibcon#*before write, iclass 25, count 0 2006.173.22:16:01.19#ibcon#enter sib2, iclass 25, count 0 2006.173.22:16:01.19#ibcon#flushed, iclass 25, count 0 2006.173.22:16:01.19#ibcon#about to write, iclass 25, count 0 2006.173.22:16:01.19#ibcon#wrote, iclass 25, count 0 2006.173.22:16:01.19#ibcon#about to read 3, iclass 25, count 0 2006.173.22:16:01.22#ibcon#read 3, iclass 25, count 0 2006.173.22:16:01.22#ibcon#about to read 4, iclass 25, count 0 2006.173.22:16:01.22#ibcon#read 4, iclass 25, count 0 2006.173.22:16:01.22#ibcon#about to read 5, iclass 25, count 0 2006.173.22:16:01.22#ibcon#read 5, iclass 25, count 0 2006.173.22:16:01.22#ibcon#about to read 6, iclass 25, count 0 2006.173.22:16:01.22#ibcon#read 6, iclass 25, count 0 2006.173.22:16:01.22#ibcon#end of sib2, iclass 25, count 0 2006.173.22:16:01.22#ibcon#*after write, iclass 25, count 0 2006.173.22:16:01.22#ibcon#*before return 0, iclass 25, count 0 2006.173.22:16:01.22#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.22:16:01.22#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.22:16:01.22#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.22:16:01.22#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.22:16:01.22$vck44/vblo=5,709.99 2006.173.22:16:01.22#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.22:16:01.22#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.22:16:01.22#ibcon#ireg 17 cls_cnt 0 2006.173.22:16:01.22#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.22:16:01.22#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.22:16:01.22#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.22:16:01.22#ibcon#enter wrdev, iclass 27, count 0 2006.173.22:16:01.22#ibcon#first serial, iclass 27, count 0 2006.173.22:16:01.22#ibcon#enter sib2, iclass 27, count 0 2006.173.22:16:01.22#ibcon#flushed, iclass 27, count 0 2006.173.22:16:01.22#ibcon#about to write, iclass 27, count 0 2006.173.22:16:01.22#ibcon#wrote, iclass 27, count 0 2006.173.22:16:01.22#ibcon#about to read 3, iclass 27, count 0 2006.173.22:16:01.24#ibcon#read 3, iclass 27, count 0 2006.173.22:16:01.24#ibcon#about to read 4, iclass 27, count 0 2006.173.22:16:01.24#ibcon#read 4, iclass 27, count 0 2006.173.22:16:01.24#ibcon#about to read 5, iclass 27, count 0 2006.173.22:16:01.24#ibcon#read 5, iclass 27, count 0 2006.173.22:16:01.24#ibcon#about to read 6, iclass 27, count 0 2006.173.22:16:01.24#ibcon#read 6, iclass 27, count 0 2006.173.22:16:01.24#ibcon#end of sib2, iclass 27, count 0 2006.173.22:16:01.24#ibcon#*mode == 0, iclass 27, count 0 2006.173.22:16:01.24#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.22:16:01.24#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.22:16:01.24#ibcon#*before write, iclass 27, count 0 2006.173.22:16:01.24#ibcon#enter sib2, iclass 27, count 0 2006.173.22:16:01.24#ibcon#flushed, iclass 27, count 0 2006.173.22:16:01.24#ibcon#about to write, iclass 27, count 0 2006.173.22:16:01.24#ibcon#wrote, iclass 27, count 0 2006.173.22:16:01.24#ibcon#about to read 3, iclass 27, count 0 2006.173.22:16:01.28#ibcon#read 3, iclass 27, count 0 2006.173.22:16:01.28#ibcon#about to read 4, iclass 27, count 0 2006.173.22:16:01.28#ibcon#read 4, iclass 27, count 0 2006.173.22:16:01.28#ibcon#about to read 5, iclass 27, count 0 2006.173.22:16:01.28#ibcon#read 5, iclass 27, count 0 2006.173.22:16:01.28#ibcon#about to read 6, iclass 27, count 0 2006.173.22:16:01.28#ibcon#read 6, iclass 27, count 0 2006.173.22:16:01.28#ibcon#end of sib2, iclass 27, count 0 2006.173.22:16:01.28#ibcon#*after write, iclass 27, count 0 2006.173.22:16:01.28#ibcon#*before return 0, iclass 27, count 0 2006.173.22:16:01.28#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.22:16:01.28#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.22:16:01.28#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.22:16:01.28#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.22:16:01.28$vck44/vb=5,4 2006.173.22:16:01.28#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.22:16:01.28#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.22:16:01.28#ibcon#ireg 11 cls_cnt 2 2006.173.22:16:01.28#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.22:16:01.34#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.22:16:01.34#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.22:16:01.34#ibcon#enter wrdev, iclass 29, count 2 2006.173.22:16:01.34#ibcon#first serial, iclass 29, count 2 2006.173.22:16:01.34#ibcon#enter sib2, iclass 29, count 2 2006.173.22:16:01.34#ibcon#flushed, iclass 29, count 2 2006.173.22:16:01.34#ibcon#about to write, iclass 29, count 2 2006.173.22:16:01.34#ibcon#wrote, iclass 29, count 2 2006.173.22:16:01.34#ibcon#about to read 3, iclass 29, count 2 2006.173.22:16:01.36#ibcon#read 3, iclass 29, count 2 2006.173.22:16:01.36#ibcon#about to read 4, iclass 29, count 2 2006.173.22:16:01.36#ibcon#read 4, iclass 29, count 2 2006.173.22:16:01.36#ibcon#about to read 5, iclass 29, count 2 2006.173.22:16:01.36#ibcon#read 5, iclass 29, count 2 2006.173.22:16:01.36#ibcon#about to read 6, iclass 29, count 2 2006.173.22:16:01.36#ibcon#read 6, iclass 29, count 2 2006.173.22:16:01.36#ibcon#end of sib2, iclass 29, count 2 2006.173.22:16:01.36#ibcon#*mode == 0, iclass 29, count 2 2006.173.22:16:01.36#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.22:16:01.36#ibcon#[27=AT05-04\r\n] 2006.173.22:16:01.36#ibcon#*before write, iclass 29, count 2 2006.173.22:16:01.36#ibcon#enter sib2, iclass 29, count 2 2006.173.22:16:01.36#ibcon#flushed, iclass 29, count 2 2006.173.22:16:01.36#ibcon#about to write, iclass 29, count 2 2006.173.22:16:01.36#ibcon#wrote, iclass 29, count 2 2006.173.22:16:01.36#ibcon#about to read 3, iclass 29, count 2 2006.173.22:16:01.39#ibcon#read 3, iclass 29, count 2 2006.173.22:16:01.39#ibcon#about to read 4, iclass 29, count 2 2006.173.22:16:01.39#ibcon#read 4, iclass 29, count 2 2006.173.22:16:01.39#ibcon#about to read 5, iclass 29, count 2 2006.173.22:16:01.39#ibcon#read 5, iclass 29, count 2 2006.173.22:16:01.39#ibcon#about to read 6, iclass 29, count 2 2006.173.22:16:01.39#ibcon#read 6, iclass 29, count 2 2006.173.22:16:01.39#ibcon#end of sib2, iclass 29, count 2 2006.173.22:16:01.39#ibcon#*after write, iclass 29, count 2 2006.173.22:16:01.39#ibcon#*before return 0, iclass 29, count 2 2006.173.22:16:01.39#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.22:16:01.39#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.22:16:01.39#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.22:16:01.39#ibcon#ireg 7 cls_cnt 0 2006.173.22:16:01.39#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.22:16:01.51#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.22:16:01.51#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.22:16:01.51#ibcon#enter wrdev, iclass 29, count 0 2006.173.22:16:01.51#ibcon#first serial, iclass 29, count 0 2006.173.22:16:01.51#ibcon#enter sib2, iclass 29, count 0 2006.173.22:16:01.51#ibcon#flushed, iclass 29, count 0 2006.173.22:16:01.51#ibcon#about to write, iclass 29, count 0 2006.173.22:16:01.51#ibcon#wrote, iclass 29, count 0 2006.173.22:16:01.51#ibcon#about to read 3, iclass 29, count 0 2006.173.22:16:01.53#ibcon#read 3, iclass 29, count 0 2006.173.22:16:01.53#ibcon#about to read 4, iclass 29, count 0 2006.173.22:16:01.53#ibcon#read 4, iclass 29, count 0 2006.173.22:16:01.53#ibcon#about to read 5, iclass 29, count 0 2006.173.22:16:01.53#ibcon#read 5, iclass 29, count 0 2006.173.22:16:01.53#ibcon#about to read 6, iclass 29, count 0 2006.173.22:16:01.53#ibcon#read 6, iclass 29, count 0 2006.173.22:16:01.53#ibcon#end of sib2, iclass 29, count 0 2006.173.22:16:01.53#ibcon#*mode == 0, iclass 29, count 0 2006.173.22:16:01.53#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.22:16:01.53#ibcon#[27=USB\r\n] 2006.173.22:16:01.53#ibcon#*before write, iclass 29, count 0 2006.173.22:16:01.53#ibcon#enter sib2, iclass 29, count 0 2006.173.22:16:01.53#ibcon#flushed, iclass 29, count 0 2006.173.22:16:01.53#ibcon#about to write, iclass 29, count 0 2006.173.22:16:01.53#ibcon#wrote, iclass 29, count 0 2006.173.22:16:01.53#ibcon#about to read 3, iclass 29, count 0 2006.173.22:16:01.56#ibcon#read 3, iclass 29, count 0 2006.173.22:16:01.56#ibcon#about to read 4, iclass 29, count 0 2006.173.22:16:01.56#ibcon#read 4, iclass 29, count 0 2006.173.22:16:01.56#ibcon#about to read 5, iclass 29, count 0 2006.173.22:16:01.56#ibcon#read 5, iclass 29, count 0 2006.173.22:16:01.56#ibcon#about to read 6, iclass 29, count 0 2006.173.22:16:01.56#ibcon#read 6, iclass 29, count 0 2006.173.22:16:01.56#ibcon#end of sib2, iclass 29, count 0 2006.173.22:16:01.56#ibcon#*after write, iclass 29, count 0 2006.173.22:16:01.56#ibcon#*before return 0, iclass 29, count 0 2006.173.22:16:01.56#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.22:16:01.56#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.22:16:01.56#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.22:16:01.56#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.22:16:01.56$vck44/vblo=6,719.99 2006.173.22:16:01.56#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.22:16:01.56#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.22:16:01.56#ibcon#ireg 17 cls_cnt 0 2006.173.22:16:01.56#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.22:16:01.56#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.22:16:01.56#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.22:16:01.56#ibcon#enter wrdev, iclass 31, count 0 2006.173.22:16:01.56#ibcon#first serial, iclass 31, count 0 2006.173.22:16:01.56#ibcon#enter sib2, iclass 31, count 0 2006.173.22:16:01.56#ibcon#flushed, iclass 31, count 0 2006.173.22:16:01.56#ibcon#about to write, iclass 31, count 0 2006.173.22:16:01.56#ibcon#wrote, iclass 31, count 0 2006.173.22:16:01.56#ibcon#about to read 3, iclass 31, count 0 2006.173.22:16:01.58#ibcon#read 3, iclass 31, count 0 2006.173.22:16:01.58#ibcon#about to read 4, iclass 31, count 0 2006.173.22:16:01.58#ibcon#read 4, iclass 31, count 0 2006.173.22:16:01.58#ibcon#about to read 5, iclass 31, count 0 2006.173.22:16:01.58#ibcon#read 5, iclass 31, count 0 2006.173.22:16:01.58#ibcon#about to read 6, iclass 31, count 0 2006.173.22:16:01.58#ibcon#read 6, iclass 31, count 0 2006.173.22:16:01.58#ibcon#end of sib2, iclass 31, count 0 2006.173.22:16:01.58#ibcon#*mode == 0, iclass 31, count 0 2006.173.22:16:01.58#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.22:16:01.58#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.22:16:01.58#ibcon#*before write, iclass 31, count 0 2006.173.22:16:01.58#ibcon#enter sib2, iclass 31, count 0 2006.173.22:16:01.58#ibcon#flushed, iclass 31, count 0 2006.173.22:16:01.58#ibcon#about to write, iclass 31, count 0 2006.173.22:16:01.58#ibcon#wrote, iclass 31, count 0 2006.173.22:16:01.58#ibcon#about to read 3, iclass 31, count 0 2006.173.22:16:01.62#ibcon#read 3, iclass 31, count 0 2006.173.22:16:01.62#ibcon#about to read 4, iclass 31, count 0 2006.173.22:16:01.62#ibcon#read 4, iclass 31, count 0 2006.173.22:16:01.62#ibcon#about to read 5, iclass 31, count 0 2006.173.22:16:01.62#ibcon#read 5, iclass 31, count 0 2006.173.22:16:01.62#ibcon#about to read 6, iclass 31, count 0 2006.173.22:16:01.62#ibcon#read 6, iclass 31, count 0 2006.173.22:16:01.62#ibcon#end of sib2, iclass 31, count 0 2006.173.22:16:01.62#ibcon#*after write, iclass 31, count 0 2006.173.22:16:01.62#ibcon#*before return 0, iclass 31, count 0 2006.173.22:16:01.62#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.22:16:01.62#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.22:16:01.62#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.22:16:01.62#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.22:16:01.62$vck44/vb=6,4 2006.173.22:16:01.62#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.173.22:16:01.62#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.173.22:16:01.62#ibcon#ireg 11 cls_cnt 2 2006.173.22:16:01.62#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.22:16:01.68#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.22:16:01.68#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.22:16:01.68#ibcon#enter wrdev, iclass 33, count 2 2006.173.22:16:01.68#ibcon#first serial, iclass 33, count 2 2006.173.22:16:01.68#ibcon#enter sib2, iclass 33, count 2 2006.173.22:16:01.68#ibcon#flushed, iclass 33, count 2 2006.173.22:16:01.68#ibcon#about to write, iclass 33, count 2 2006.173.22:16:01.68#ibcon#wrote, iclass 33, count 2 2006.173.22:16:01.68#ibcon#about to read 3, iclass 33, count 2 2006.173.22:16:01.70#ibcon#read 3, iclass 33, count 2 2006.173.22:16:01.70#ibcon#about to read 4, iclass 33, count 2 2006.173.22:16:01.70#ibcon#read 4, iclass 33, count 2 2006.173.22:16:01.70#ibcon#about to read 5, iclass 33, count 2 2006.173.22:16:01.70#ibcon#read 5, iclass 33, count 2 2006.173.22:16:01.70#ibcon#about to read 6, iclass 33, count 2 2006.173.22:16:01.70#ibcon#read 6, iclass 33, count 2 2006.173.22:16:01.70#ibcon#end of sib2, iclass 33, count 2 2006.173.22:16:01.70#ibcon#*mode == 0, iclass 33, count 2 2006.173.22:16:01.70#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.173.22:16:01.70#ibcon#[27=AT06-04\r\n] 2006.173.22:16:01.70#ibcon#*before write, iclass 33, count 2 2006.173.22:16:01.70#ibcon#enter sib2, iclass 33, count 2 2006.173.22:16:01.70#ibcon#flushed, iclass 33, count 2 2006.173.22:16:01.70#ibcon#about to write, iclass 33, count 2 2006.173.22:16:01.70#ibcon#wrote, iclass 33, count 2 2006.173.22:16:01.70#ibcon#about to read 3, iclass 33, count 2 2006.173.22:16:01.73#ibcon#read 3, iclass 33, count 2 2006.173.22:16:01.73#ibcon#about to read 4, iclass 33, count 2 2006.173.22:16:01.73#ibcon#read 4, iclass 33, count 2 2006.173.22:16:01.73#ibcon#about to read 5, iclass 33, count 2 2006.173.22:16:01.73#ibcon#read 5, iclass 33, count 2 2006.173.22:16:01.73#ibcon#about to read 6, iclass 33, count 2 2006.173.22:16:01.73#ibcon#read 6, iclass 33, count 2 2006.173.22:16:01.73#ibcon#end of sib2, iclass 33, count 2 2006.173.22:16:01.73#ibcon#*after write, iclass 33, count 2 2006.173.22:16:01.73#ibcon#*before return 0, iclass 33, count 2 2006.173.22:16:01.73#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.22:16:01.73#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.173.22:16:01.73#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.173.22:16:01.73#ibcon#ireg 7 cls_cnt 0 2006.173.22:16:01.73#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.22:16:01.85#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.22:16:01.85#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.22:16:01.85#ibcon#enter wrdev, iclass 33, count 0 2006.173.22:16:01.85#ibcon#first serial, iclass 33, count 0 2006.173.22:16:01.85#ibcon#enter sib2, iclass 33, count 0 2006.173.22:16:01.85#ibcon#flushed, iclass 33, count 0 2006.173.22:16:01.85#ibcon#about to write, iclass 33, count 0 2006.173.22:16:01.85#ibcon#wrote, iclass 33, count 0 2006.173.22:16:01.85#ibcon#about to read 3, iclass 33, count 0 2006.173.22:16:01.87#ibcon#read 3, iclass 33, count 0 2006.173.22:16:01.87#ibcon#about to read 4, iclass 33, count 0 2006.173.22:16:01.87#ibcon#read 4, iclass 33, count 0 2006.173.22:16:01.87#ibcon#about to read 5, iclass 33, count 0 2006.173.22:16:01.87#ibcon#read 5, iclass 33, count 0 2006.173.22:16:01.87#ibcon#about to read 6, iclass 33, count 0 2006.173.22:16:01.87#ibcon#read 6, iclass 33, count 0 2006.173.22:16:01.87#ibcon#end of sib2, iclass 33, count 0 2006.173.22:16:01.87#ibcon#*mode == 0, iclass 33, count 0 2006.173.22:16:01.87#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.22:16:01.87#ibcon#[27=USB\r\n] 2006.173.22:16:01.87#ibcon#*before write, iclass 33, count 0 2006.173.22:16:01.87#ibcon#enter sib2, iclass 33, count 0 2006.173.22:16:01.87#ibcon#flushed, iclass 33, count 0 2006.173.22:16:01.87#ibcon#about to write, iclass 33, count 0 2006.173.22:16:01.87#ibcon#wrote, iclass 33, count 0 2006.173.22:16:01.87#ibcon#about to read 3, iclass 33, count 0 2006.173.22:16:01.90#ibcon#read 3, iclass 33, count 0 2006.173.22:16:01.90#ibcon#about to read 4, iclass 33, count 0 2006.173.22:16:01.90#ibcon#read 4, iclass 33, count 0 2006.173.22:16:01.90#ibcon#about to read 5, iclass 33, count 0 2006.173.22:16:01.90#ibcon#read 5, iclass 33, count 0 2006.173.22:16:01.90#ibcon#about to read 6, iclass 33, count 0 2006.173.22:16:01.90#ibcon#read 6, iclass 33, count 0 2006.173.22:16:01.90#ibcon#end of sib2, iclass 33, count 0 2006.173.22:16:01.90#ibcon#*after write, iclass 33, count 0 2006.173.22:16:01.90#ibcon#*before return 0, iclass 33, count 0 2006.173.22:16:01.90#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.22:16:01.90#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.173.22:16:01.90#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.22:16:01.90#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.22:16:01.90$vck44/vblo=7,734.99 2006.173.22:16:01.90#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.22:16:01.90#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.22:16:01.90#ibcon#ireg 17 cls_cnt 0 2006.173.22:16:01.90#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.22:16:01.90#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.22:16:01.90#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.22:16:01.90#ibcon#enter wrdev, iclass 35, count 0 2006.173.22:16:01.90#ibcon#first serial, iclass 35, count 0 2006.173.22:16:01.90#ibcon#enter sib2, iclass 35, count 0 2006.173.22:16:01.90#ibcon#flushed, iclass 35, count 0 2006.173.22:16:01.90#ibcon#about to write, iclass 35, count 0 2006.173.22:16:01.90#ibcon#wrote, iclass 35, count 0 2006.173.22:16:01.90#ibcon#about to read 3, iclass 35, count 0 2006.173.22:16:01.92#ibcon#read 3, iclass 35, count 0 2006.173.22:16:01.92#ibcon#about to read 4, iclass 35, count 0 2006.173.22:16:01.92#ibcon#read 4, iclass 35, count 0 2006.173.22:16:01.92#ibcon#about to read 5, iclass 35, count 0 2006.173.22:16:01.92#ibcon#read 5, iclass 35, count 0 2006.173.22:16:01.92#ibcon#about to read 6, iclass 35, count 0 2006.173.22:16:01.92#ibcon#read 6, iclass 35, count 0 2006.173.22:16:01.92#ibcon#end of sib2, iclass 35, count 0 2006.173.22:16:01.92#ibcon#*mode == 0, iclass 35, count 0 2006.173.22:16:01.92#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.22:16:01.92#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.22:16:01.92#ibcon#*before write, iclass 35, count 0 2006.173.22:16:01.92#ibcon#enter sib2, iclass 35, count 0 2006.173.22:16:01.92#ibcon#flushed, iclass 35, count 0 2006.173.22:16:01.92#ibcon#about to write, iclass 35, count 0 2006.173.22:16:01.92#ibcon#wrote, iclass 35, count 0 2006.173.22:16:01.92#ibcon#about to read 3, iclass 35, count 0 2006.173.22:16:01.96#ibcon#read 3, iclass 35, count 0 2006.173.22:16:01.96#ibcon#about to read 4, iclass 35, count 0 2006.173.22:16:01.96#ibcon#read 4, iclass 35, count 0 2006.173.22:16:01.96#ibcon#about to read 5, iclass 35, count 0 2006.173.22:16:01.96#ibcon#read 5, iclass 35, count 0 2006.173.22:16:01.96#ibcon#about to read 6, iclass 35, count 0 2006.173.22:16:01.96#ibcon#read 6, iclass 35, count 0 2006.173.22:16:01.96#ibcon#end of sib2, iclass 35, count 0 2006.173.22:16:01.96#ibcon#*after write, iclass 35, count 0 2006.173.22:16:01.96#ibcon#*before return 0, iclass 35, count 0 2006.173.22:16:01.96#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.22:16:01.96#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.22:16:01.96#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.22:16:01.96#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.22:16:01.96$vck44/vb=7,4 2006.173.22:16:01.96#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.173.22:16:01.96#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.173.22:16:01.96#ibcon#ireg 11 cls_cnt 2 2006.173.22:16:01.96#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.22:16:02.02#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.22:16:02.02#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.22:16:02.02#ibcon#enter wrdev, iclass 37, count 2 2006.173.22:16:02.02#ibcon#first serial, iclass 37, count 2 2006.173.22:16:02.02#ibcon#enter sib2, iclass 37, count 2 2006.173.22:16:02.02#ibcon#flushed, iclass 37, count 2 2006.173.22:16:02.02#ibcon#about to write, iclass 37, count 2 2006.173.22:16:02.02#ibcon#wrote, iclass 37, count 2 2006.173.22:16:02.02#ibcon#about to read 3, iclass 37, count 2 2006.173.22:16:02.04#ibcon#read 3, iclass 37, count 2 2006.173.22:16:02.04#ibcon#about to read 4, iclass 37, count 2 2006.173.22:16:02.04#ibcon#read 4, iclass 37, count 2 2006.173.22:16:02.04#ibcon#about to read 5, iclass 37, count 2 2006.173.22:16:02.04#ibcon#read 5, iclass 37, count 2 2006.173.22:16:02.04#ibcon#about to read 6, iclass 37, count 2 2006.173.22:16:02.04#ibcon#read 6, iclass 37, count 2 2006.173.22:16:02.04#ibcon#end of sib2, iclass 37, count 2 2006.173.22:16:02.04#ibcon#*mode == 0, iclass 37, count 2 2006.173.22:16:02.04#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.173.22:16:02.04#ibcon#[27=AT07-04\r\n] 2006.173.22:16:02.04#ibcon#*before write, iclass 37, count 2 2006.173.22:16:02.04#ibcon#enter sib2, iclass 37, count 2 2006.173.22:16:02.04#ibcon#flushed, iclass 37, count 2 2006.173.22:16:02.04#ibcon#about to write, iclass 37, count 2 2006.173.22:16:02.04#ibcon#wrote, iclass 37, count 2 2006.173.22:16:02.04#ibcon#about to read 3, iclass 37, count 2 2006.173.22:16:02.07#ibcon#read 3, iclass 37, count 2 2006.173.22:16:02.07#ibcon#about to read 4, iclass 37, count 2 2006.173.22:16:02.07#ibcon#read 4, iclass 37, count 2 2006.173.22:16:02.07#ibcon#about to read 5, iclass 37, count 2 2006.173.22:16:02.07#ibcon#read 5, iclass 37, count 2 2006.173.22:16:02.07#ibcon#about to read 6, iclass 37, count 2 2006.173.22:16:02.07#ibcon#read 6, iclass 37, count 2 2006.173.22:16:02.07#ibcon#end of sib2, iclass 37, count 2 2006.173.22:16:02.07#ibcon#*after write, iclass 37, count 2 2006.173.22:16:02.07#ibcon#*before return 0, iclass 37, count 2 2006.173.22:16:02.07#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.22:16:02.07#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.173.22:16:02.07#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.173.22:16:02.07#ibcon#ireg 7 cls_cnt 0 2006.173.22:16:02.07#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.22:16:02.19#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.22:16:02.19#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.22:16:02.19#ibcon#enter wrdev, iclass 37, count 0 2006.173.22:16:02.19#ibcon#first serial, iclass 37, count 0 2006.173.22:16:02.19#ibcon#enter sib2, iclass 37, count 0 2006.173.22:16:02.19#ibcon#flushed, iclass 37, count 0 2006.173.22:16:02.19#ibcon#about to write, iclass 37, count 0 2006.173.22:16:02.19#ibcon#wrote, iclass 37, count 0 2006.173.22:16:02.19#ibcon#about to read 3, iclass 37, count 0 2006.173.22:16:02.21#ibcon#read 3, iclass 37, count 0 2006.173.22:16:02.21#ibcon#about to read 4, iclass 37, count 0 2006.173.22:16:02.21#ibcon#read 4, iclass 37, count 0 2006.173.22:16:02.21#ibcon#about to read 5, iclass 37, count 0 2006.173.22:16:02.21#ibcon#read 5, iclass 37, count 0 2006.173.22:16:02.21#ibcon#about to read 6, iclass 37, count 0 2006.173.22:16:02.21#ibcon#read 6, iclass 37, count 0 2006.173.22:16:02.21#ibcon#end of sib2, iclass 37, count 0 2006.173.22:16:02.21#ibcon#*mode == 0, iclass 37, count 0 2006.173.22:16:02.21#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.22:16:02.21#ibcon#[27=USB\r\n] 2006.173.22:16:02.21#ibcon#*before write, iclass 37, count 0 2006.173.22:16:02.21#ibcon#enter sib2, iclass 37, count 0 2006.173.22:16:02.21#ibcon#flushed, iclass 37, count 0 2006.173.22:16:02.21#ibcon#about to write, iclass 37, count 0 2006.173.22:16:02.21#ibcon#wrote, iclass 37, count 0 2006.173.22:16:02.21#ibcon#about to read 3, iclass 37, count 0 2006.173.22:16:02.24#ibcon#read 3, iclass 37, count 0 2006.173.22:16:02.24#ibcon#about to read 4, iclass 37, count 0 2006.173.22:16:02.24#ibcon#read 4, iclass 37, count 0 2006.173.22:16:02.24#ibcon#about to read 5, iclass 37, count 0 2006.173.22:16:02.24#ibcon#read 5, iclass 37, count 0 2006.173.22:16:02.24#ibcon#about to read 6, iclass 37, count 0 2006.173.22:16:02.24#ibcon#read 6, iclass 37, count 0 2006.173.22:16:02.24#ibcon#end of sib2, iclass 37, count 0 2006.173.22:16:02.24#ibcon#*after write, iclass 37, count 0 2006.173.22:16:02.24#ibcon#*before return 0, iclass 37, count 0 2006.173.22:16:02.24#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.22:16:02.24#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.173.22:16:02.24#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.22:16:02.24#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.22:16:02.24$vck44/vblo=8,744.99 2006.173.22:16:02.24#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.22:16:02.24#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.22:16:02.24#ibcon#ireg 17 cls_cnt 0 2006.173.22:16:02.24#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.22:16:02.24#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.22:16:02.24#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.22:16:02.24#ibcon#enter wrdev, iclass 39, count 0 2006.173.22:16:02.24#ibcon#first serial, iclass 39, count 0 2006.173.22:16:02.24#ibcon#enter sib2, iclass 39, count 0 2006.173.22:16:02.24#ibcon#flushed, iclass 39, count 0 2006.173.22:16:02.24#ibcon#about to write, iclass 39, count 0 2006.173.22:16:02.24#ibcon#wrote, iclass 39, count 0 2006.173.22:16:02.24#ibcon#about to read 3, iclass 39, count 0 2006.173.22:16:02.26#ibcon#read 3, iclass 39, count 0 2006.173.22:16:02.26#ibcon#about to read 4, iclass 39, count 0 2006.173.22:16:02.26#ibcon#read 4, iclass 39, count 0 2006.173.22:16:02.26#ibcon#about to read 5, iclass 39, count 0 2006.173.22:16:02.26#ibcon#read 5, iclass 39, count 0 2006.173.22:16:02.26#ibcon#about to read 6, iclass 39, count 0 2006.173.22:16:02.26#ibcon#read 6, iclass 39, count 0 2006.173.22:16:02.26#ibcon#end of sib2, iclass 39, count 0 2006.173.22:16:02.26#ibcon#*mode == 0, iclass 39, count 0 2006.173.22:16:02.26#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.22:16:02.26#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.22:16:02.26#ibcon#*before write, iclass 39, count 0 2006.173.22:16:02.26#ibcon#enter sib2, iclass 39, count 0 2006.173.22:16:02.26#ibcon#flushed, iclass 39, count 0 2006.173.22:16:02.26#ibcon#about to write, iclass 39, count 0 2006.173.22:16:02.26#ibcon#wrote, iclass 39, count 0 2006.173.22:16:02.26#ibcon#about to read 3, iclass 39, count 0 2006.173.22:16:02.30#ibcon#read 3, iclass 39, count 0 2006.173.22:16:02.30#ibcon#about to read 4, iclass 39, count 0 2006.173.22:16:02.30#ibcon#read 4, iclass 39, count 0 2006.173.22:16:02.30#ibcon#about to read 5, iclass 39, count 0 2006.173.22:16:02.30#ibcon#read 5, iclass 39, count 0 2006.173.22:16:02.30#ibcon#about to read 6, iclass 39, count 0 2006.173.22:16:02.30#ibcon#read 6, iclass 39, count 0 2006.173.22:16:02.30#ibcon#end of sib2, iclass 39, count 0 2006.173.22:16:02.30#ibcon#*after write, iclass 39, count 0 2006.173.22:16:02.30#ibcon#*before return 0, iclass 39, count 0 2006.173.22:16:02.30#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.22:16:02.30#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.22:16:02.30#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.22:16:02.30#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.22:16:02.30$vck44/vb=8,4 2006.173.22:16:02.30#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.22:16:02.30#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.22:16:02.30#ibcon#ireg 11 cls_cnt 2 2006.173.22:16:02.30#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.22:16:02.36#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.22:16:02.36#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.22:16:02.36#ibcon#enter wrdev, iclass 3, count 2 2006.173.22:16:02.36#ibcon#first serial, iclass 3, count 2 2006.173.22:16:02.36#ibcon#enter sib2, iclass 3, count 2 2006.173.22:16:02.36#ibcon#flushed, iclass 3, count 2 2006.173.22:16:02.36#ibcon#about to write, iclass 3, count 2 2006.173.22:16:02.36#ibcon#wrote, iclass 3, count 2 2006.173.22:16:02.36#ibcon#about to read 3, iclass 3, count 2 2006.173.22:16:02.38#ibcon#read 3, iclass 3, count 2 2006.173.22:16:02.38#ibcon#about to read 4, iclass 3, count 2 2006.173.22:16:02.38#ibcon#read 4, iclass 3, count 2 2006.173.22:16:02.38#ibcon#about to read 5, iclass 3, count 2 2006.173.22:16:02.38#ibcon#read 5, iclass 3, count 2 2006.173.22:16:02.38#ibcon#about to read 6, iclass 3, count 2 2006.173.22:16:02.38#ibcon#read 6, iclass 3, count 2 2006.173.22:16:02.38#ibcon#end of sib2, iclass 3, count 2 2006.173.22:16:02.38#ibcon#*mode == 0, iclass 3, count 2 2006.173.22:16:02.38#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.22:16:02.38#ibcon#[27=AT08-04\r\n] 2006.173.22:16:02.38#ibcon#*before write, iclass 3, count 2 2006.173.22:16:02.38#ibcon#enter sib2, iclass 3, count 2 2006.173.22:16:02.38#ibcon#flushed, iclass 3, count 2 2006.173.22:16:02.38#ibcon#about to write, iclass 3, count 2 2006.173.22:16:02.38#ibcon#wrote, iclass 3, count 2 2006.173.22:16:02.38#ibcon#about to read 3, iclass 3, count 2 2006.173.22:16:02.41#ibcon#read 3, iclass 3, count 2 2006.173.22:16:02.41#ibcon#about to read 4, iclass 3, count 2 2006.173.22:16:02.41#ibcon#read 4, iclass 3, count 2 2006.173.22:16:02.41#ibcon#about to read 5, iclass 3, count 2 2006.173.22:16:02.41#ibcon#read 5, iclass 3, count 2 2006.173.22:16:02.41#ibcon#about to read 6, iclass 3, count 2 2006.173.22:16:02.41#ibcon#read 6, iclass 3, count 2 2006.173.22:16:02.41#ibcon#end of sib2, iclass 3, count 2 2006.173.22:16:02.41#ibcon#*after write, iclass 3, count 2 2006.173.22:16:02.41#ibcon#*before return 0, iclass 3, count 2 2006.173.22:16:02.41#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.22:16:02.41#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.22:16:02.41#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.22:16:02.41#ibcon#ireg 7 cls_cnt 0 2006.173.22:16:02.41#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.22:16:02.53#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.22:16:02.53#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.22:16:02.53#ibcon#enter wrdev, iclass 3, count 0 2006.173.22:16:02.53#ibcon#first serial, iclass 3, count 0 2006.173.22:16:02.53#ibcon#enter sib2, iclass 3, count 0 2006.173.22:16:02.53#ibcon#flushed, iclass 3, count 0 2006.173.22:16:02.53#ibcon#about to write, iclass 3, count 0 2006.173.22:16:02.53#ibcon#wrote, iclass 3, count 0 2006.173.22:16:02.53#ibcon#about to read 3, iclass 3, count 0 2006.173.22:16:02.55#ibcon#read 3, iclass 3, count 0 2006.173.22:16:02.55#ibcon#about to read 4, iclass 3, count 0 2006.173.22:16:02.55#ibcon#read 4, iclass 3, count 0 2006.173.22:16:02.55#ibcon#about to read 5, iclass 3, count 0 2006.173.22:16:02.55#ibcon#read 5, iclass 3, count 0 2006.173.22:16:02.55#ibcon#about to read 6, iclass 3, count 0 2006.173.22:16:02.55#ibcon#read 6, iclass 3, count 0 2006.173.22:16:02.55#ibcon#end of sib2, iclass 3, count 0 2006.173.22:16:02.55#ibcon#*mode == 0, iclass 3, count 0 2006.173.22:16:02.55#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.22:16:02.55#ibcon#[27=USB\r\n] 2006.173.22:16:02.55#ibcon#*before write, iclass 3, count 0 2006.173.22:16:02.55#ibcon#enter sib2, iclass 3, count 0 2006.173.22:16:02.55#ibcon#flushed, iclass 3, count 0 2006.173.22:16:02.55#ibcon#about to write, iclass 3, count 0 2006.173.22:16:02.55#ibcon#wrote, iclass 3, count 0 2006.173.22:16:02.55#ibcon#about to read 3, iclass 3, count 0 2006.173.22:16:02.58#ibcon#read 3, iclass 3, count 0 2006.173.22:16:02.58#ibcon#about to read 4, iclass 3, count 0 2006.173.22:16:02.58#ibcon#read 4, iclass 3, count 0 2006.173.22:16:02.58#ibcon#about to read 5, iclass 3, count 0 2006.173.22:16:02.58#ibcon#read 5, iclass 3, count 0 2006.173.22:16:02.58#ibcon#about to read 6, iclass 3, count 0 2006.173.22:16:02.58#ibcon#read 6, iclass 3, count 0 2006.173.22:16:02.58#ibcon#end of sib2, iclass 3, count 0 2006.173.22:16:02.58#ibcon#*after write, iclass 3, count 0 2006.173.22:16:02.58#ibcon#*before return 0, iclass 3, count 0 2006.173.22:16:02.58#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.22:16:02.58#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.22:16:02.58#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.22:16:02.58#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.22:16:02.58$vck44/vabw=wide 2006.173.22:16:02.58#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.22:16:02.58#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.22:16:02.58#ibcon#ireg 8 cls_cnt 0 2006.173.22:16:02.58#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.22:16:02.58#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.22:16:02.58#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.22:16:02.58#ibcon#enter wrdev, iclass 5, count 0 2006.173.22:16:02.58#ibcon#first serial, iclass 5, count 0 2006.173.22:16:02.58#ibcon#enter sib2, iclass 5, count 0 2006.173.22:16:02.58#ibcon#flushed, iclass 5, count 0 2006.173.22:16:02.58#ibcon#about to write, iclass 5, count 0 2006.173.22:16:02.58#ibcon#wrote, iclass 5, count 0 2006.173.22:16:02.58#ibcon#about to read 3, iclass 5, count 0 2006.173.22:16:02.60#ibcon#read 3, iclass 5, count 0 2006.173.22:16:02.60#ibcon#about to read 4, iclass 5, count 0 2006.173.22:16:02.60#ibcon#read 4, iclass 5, count 0 2006.173.22:16:02.60#ibcon#about to read 5, iclass 5, count 0 2006.173.22:16:02.60#ibcon#read 5, iclass 5, count 0 2006.173.22:16:02.60#ibcon#about to read 6, iclass 5, count 0 2006.173.22:16:02.60#ibcon#read 6, iclass 5, count 0 2006.173.22:16:02.60#ibcon#end of sib2, iclass 5, count 0 2006.173.22:16:02.60#ibcon#*mode == 0, iclass 5, count 0 2006.173.22:16:02.60#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.22:16:02.60#ibcon#[25=BW32\r\n] 2006.173.22:16:02.60#ibcon#*before write, iclass 5, count 0 2006.173.22:16:02.60#ibcon#enter sib2, iclass 5, count 0 2006.173.22:16:02.60#ibcon#flushed, iclass 5, count 0 2006.173.22:16:02.60#ibcon#about to write, iclass 5, count 0 2006.173.22:16:02.60#ibcon#wrote, iclass 5, count 0 2006.173.22:16:02.60#ibcon#about to read 3, iclass 5, count 0 2006.173.22:16:02.63#ibcon#read 3, iclass 5, count 0 2006.173.22:16:02.63#ibcon#about to read 4, iclass 5, count 0 2006.173.22:16:02.63#ibcon#read 4, iclass 5, count 0 2006.173.22:16:02.63#ibcon#about to read 5, iclass 5, count 0 2006.173.22:16:02.63#ibcon#read 5, iclass 5, count 0 2006.173.22:16:02.63#ibcon#about to read 6, iclass 5, count 0 2006.173.22:16:02.63#ibcon#read 6, iclass 5, count 0 2006.173.22:16:02.63#ibcon#end of sib2, iclass 5, count 0 2006.173.22:16:02.63#ibcon#*after write, iclass 5, count 0 2006.173.22:16:02.63#ibcon#*before return 0, iclass 5, count 0 2006.173.22:16:02.63#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.22:16:02.63#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.22:16:02.63#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.22:16:02.63#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.22:16:02.63$vck44/vbbw=wide 2006.173.22:16:02.63#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.22:16:02.63#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.22:16:02.63#ibcon#ireg 8 cls_cnt 0 2006.173.22:16:02.63#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.22:16:02.70#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.22:16:02.70#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.22:16:02.70#ibcon#enter wrdev, iclass 7, count 0 2006.173.22:16:02.70#ibcon#first serial, iclass 7, count 0 2006.173.22:16:02.70#ibcon#enter sib2, iclass 7, count 0 2006.173.22:16:02.70#ibcon#flushed, iclass 7, count 0 2006.173.22:16:02.70#ibcon#about to write, iclass 7, count 0 2006.173.22:16:02.70#ibcon#wrote, iclass 7, count 0 2006.173.22:16:02.70#ibcon#about to read 3, iclass 7, count 0 2006.173.22:16:02.72#ibcon#read 3, iclass 7, count 0 2006.173.22:16:02.72#ibcon#about to read 4, iclass 7, count 0 2006.173.22:16:02.72#ibcon#read 4, iclass 7, count 0 2006.173.22:16:02.72#ibcon#about to read 5, iclass 7, count 0 2006.173.22:16:02.72#ibcon#read 5, iclass 7, count 0 2006.173.22:16:02.72#ibcon#about to read 6, iclass 7, count 0 2006.173.22:16:02.72#ibcon#read 6, iclass 7, count 0 2006.173.22:16:02.72#ibcon#end of sib2, iclass 7, count 0 2006.173.22:16:02.72#ibcon#*mode == 0, iclass 7, count 0 2006.173.22:16:02.72#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.22:16:02.72#ibcon#[27=BW32\r\n] 2006.173.22:16:02.72#ibcon#*before write, iclass 7, count 0 2006.173.22:16:02.72#ibcon#enter sib2, iclass 7, count 0 2006.173.22:16:02.72#ibcon#flushed, iclass 7, count 0 2006.173.22:16:02.72#ibcon#about to write, iclass 7, count 0 2006.173.22:16:02.72#ibcon#wrote, iclass 7, count 0 2006.173.22:16:02.72#ibcon#about to read 3, iclass 7, count 0 2006.173.22:16:02.75#ibcon#read 3, iclass 7, count 0 2006.173.22:16:02.75#ibcon#about to read 4, iclass 7, count 0 2006.173.22:16:02.75#ibcon#read 4, iclass 7, count 0 2006.173.22:16:02.75#ibcon#about to read 5, iclass 7, count 0 2006.173.22:16:02.75#ibcon#read 5, iclass 7, count 0 2006.173.22:16:02.75#ibcon#about to read 6, iclass 7, count 0 2006.173.22:16:02.75#ibcon#read 6, iclass 7, count 0 2006.173.22:16:02.75#ibcon#end of sib2, iclass 7, count 0 2006.173.22:16:02.75#ibcon#*after write, iclass 7, count 0 2006.173.22:16:02.75#ibcon#*before return 0, iclass 7, count 0 2006.173.22:16:02.75#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.22:16:02.75#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.22:16:02.75#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.22:16:02.75#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.22:16:02.75$setupk4/ifdk4 2006.173.22:16:02.75$ifdk4/lo= 2006.173.22:16:02.75$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.22:16:02.75$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.22:16:02.75$ifdk4/patch= 2006.173.22:16:02.75$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.22:16:02.75$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.22:16:02.75$setupk4/!*+20s 2006.173.22:16:06.03#abcon#<5=/10 0.8 2.0 21.94 971003.4\r\n> 2006.173.22:16:06.05#abcon#{5=INTERFACE CLEAR} 2006.173.22:16:06.11#abcon#[5=S1D000X0/0*\r\n] 2006.173.22:16:07.14#trakl#Source acquired 2006.173.22:16:08.14#flagr#flagr/antenna,acquired 2006.173.22:16:16.20#abcon#<5=/10 0.8 2.0 21.94 971003.4\r\n> 2006.173.22:16:16.22#abcon#{5=INTERFACE CLEAR} 2006.173.22:16:16.28#abcon#[5=S1D000X0/0*\r\n] 2006.173.22:16:17.26$setupk4/"tpicd 2006.173.22:16:17.26$setupk4/echo=off 2006.173.22:16:17.26$setupk4/xlog=off 2006.173.22:16:17.26:!2006.173.22:18:02 2006.173.22:18:02.00:preob 2006.173.22:18:03.13/onsource/TRACKING 2006.173.22:18:03.13:!2006.173.22:18:12 2006.173.22:18:12.00:"tape 2006.173.22:18:12.00:"st=record 2006.173.22:18:12.00:data_valid=on 2006.173.22:18:12.00:midob 2006.173.22:18:12.13/onsource/TRACKING 2006.173.22:18:12.13/wx/22.03,1003.4,97 2006.173.22:18:12.29/cable/+6.5154E-03 2006.173.22:18:13.38/va/01,07,usb,yes,36,38 2006.173.22:18:13.38/va/02,06,usb,yes,36,36 2006.173.22:18:13.38/va/03,05,usb,yes,45,47 2006.173.22:18:13.38/va/04,06,usb,yes,36,38 2006.173.22:18:13.38/va/05,04,usb,yes,28,29 2006.173.22:18:13.38/va/06,03,usb,yes,40,40 2006.173.22:18:13.38/va/07,04,usb,yes,32,34 2006.173.22:18:13.38/va/08,04,usb,yes,28,33 2006.173.22:18:13.61/valo/01,524.99,yes,locked 2006.173.22:18:13.61/valo/02,534.99,yes,locked 2006.173.22:18:13.61/valo/03,564.99,yes,locked 2006.173.22:18:13.61/valo/04,624.99,yes,locked 2006.173.22:18:13.61/valo/05,734.99,yes,locked 2006.173.22:18:13.61/valo/06,814.99,yes,locked 2006.173.22:18:13.61/valo/07,864.99,yes,locked 2006.173.22:18:13.61/valo/08,884.99,yes,locked 2006.173.22:18:14.70/vb/01,04,usb,yes,30,28 2006.173.22:18:14.70/vb/02,04,usb,yes,32,32 2006.173.22:18:14.70/vb/03,04,usb,yes,29,32 2006.173.22:18:14.70/vb/04,04,usb,yes,33,32 2006.173.22:18:14.70/vb/05,04,usb,yes,26,28 2006.173.22:18:14.70/vb/06,04,usb,yes,30,27 2006.173.22:18:14.70/vb/07,04,usb,yes,30,30 2006.173.22:18:14.70/vb/08,04,usb,yes,28,31 2006.173.22:18:14.93/vblo/01,629.99,yes,locked 2006.173.22:18:14.93/vblo/02,634.99,yes,locked 2006.173.22:18:14.93/vblo/03,649.99,yes,locked 2006.173.22:18:14.93/vblo/04,679.99,yes,locked 2006.173.22:18:14.93/vblo/05,709.99,yes,locked 2006.173.22:18:14.93/vblo/06,719.99,yes,locked 2006.173.22:18:14.93/vblo/07,734.99,yes,locked 2006.173.22:18:14.93/vblo/08,744.99,yes,locked 2006.173.22:18:15.08/vabw/8 2006.173.22:18:15.23/vbbw/8 2006.173.22:18:15.32/xfe/off,on,15.2 2006.173.22:18:15.70/ifatt/23,28,28,28 2006.173.22:18:16.08/fmout-gps/S +3.81E-07 2006.173.22:18:16.12:!2006.173.22:21:22 2006.173.22:21:22.00:data_valid=off 2006.173.22:21:22.00:"et 2006.173.22:21:22.00:!+3s 2006.173.22:21:25.02:"tape 2006.173.22:21:25.02:postob 2006.173.22:21:25.22/cable/+6.5137E-03 2006.173.22:21:25.22/wx/22.18,1003.4,96 2006.173.22:21:26.08/fmout-gps/S +3.77E-07 2006.173.22:21:26.08:scan_name=173-2224,jd0606,50 2006.173.22:21:26.08:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.173.22:21:27.14#flagr#flagr/antenna,new-source 2006.173.22:21:27.14:checkk5 2006.173.22:21:27.55/chk_autoobs//k5ts1/ autoobs is running! 2006.173.22:21:27.95/chk_autoobs//k5ts2/ autoobs is running! 2006.173.22:21:28.35/chk_autoobs//k5ts3/ autoobs is running! 2006.173.22:21:28.75/chk_autoobs//k5ts4/ autoobs is running! 2006.173.22:21:29.14/chk_obsdata//k5ts1/T1732218??a.dat file size is correct (nominal:760MB, actual:760MB). 2006.173.22:21:29.56/chk_obsdata//k5ts2/T1732218??b.dat file size is correct (nominal:760MB, actual:760MB). 2006.173.22:21:29.97/chk_obsdata//k5ts3/T1732218??c.dat file size is correct (nominal:760MB, actual:760MB). 2006.173.22:21:30.37/chk_obsdata//k5ts4/T1732218??d.dat file size is correct (nominal:760MB, actual:760MB). 2006.173.22:21:31.10/k5log//k5ts1_log_newline 2006.173.22:21:31.82/k5log//k5ts2_log_newline 2006.173.22:21:32.53/k5log//k5ts3_log_newline 2006.173.22:21:33.23/k5log//k5ts4_log_newline 2006.173.22:21:33.26/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.22:21:33.26:setupk4=1 2006.173.22:21:33.26$setupk4/echo=on 2006.173.22:21:33.26$setupk4/pcalon 2006.173.22:21:33.26$pcalon/"no phase cal control is implemented here 2006.173.22:21:33.26$setupk4/"tpicd=stop 2006.173.22:21:33.26$setupk4/"rec=synch_on 2006.173.22:21:33.26$setupk4/"rec_mode=128 2006.173.22:21:33.26$setupk4/!* 2006.173.22:21:33.26$setupk4/recpk4 2006.173.22:21:33.26$recpk4/recpatch= 2006.173.22:21:33.26$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.22:21:33.26$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.22:21:33.26$setupk4/vck44 2006.173.22:21:33.26$vck44/valo=1,524.99 2006.173.22:21:33.26#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.22:21:33.26#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.22:21:33.26#ibcon#ireg 17 cls_cnt 0 2006.173.22:21:33.26#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.22:21:33.26#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.22:21:33.26#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.22:21:33.26#ibcon#enter wrdev, iclass 38, count 0 2006.173.22:21:33.26#ibcon#first serial, iclass 38, count 0 2006.173.22:21:33.26#ibcon#enter sib2, iclass 38, count 0 2006.173.22:21:33.26#ibcon#flushed, iclass 38, count 0 2006.173.22:21:33.26#ibcon#about to write, iclass 38, count 0 2006.173.22:21:33.26#ibcon#wrote, iclass 38, count 0 2006.173.22:21:33.26#ibcon#about to read 3, iclass 38, count 0 2006.173.22:21:33.28#ibcon#read 3, iclass 38, count 0 2006.173.22:21:33.28#ibcon#about to read 4, iclass 38, count 0 2006.173.22:21:33.28#ibcon#read 4, iclass 38, count 0 2006.173.22:21:33.28#ibcon#about to read 5, iclass 38, count 0 2006.173.22:21:33.28#ibcon#read 5, iclass 38, count 0 2006.173.22:21:33.28#ibcon#about to read 6, iclass 38, count 0 2006.173.22:21:33.28#ibcon#read 6, iclass 38, count 0 2006.173.22:21:33.28#ibcon#end of sib2, iclass 38, count 0 2006.173.22:21:33.28#ibcon#*mode == 0, iclass 38, count 0 2006.173.22:21:33.28#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.22:21:33.28#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.22:21:33.28#ibcon#*before write, iclass 38, count 0 2006.173.22:21:33.28#ibcon#enter sib2, iclass 38, count 0 2006.173.22:21:33.28#ibcon#flushed, iclass 38, count 0 2006.173.22:21:33.28#ibcon#about to write, iclass 38, count 0 2006.173.22:21:33.28#ibcon#wrote, iclass 38, count 0 2006.173.22:21:33.28#ibcon#about to read 3, iclass 38, count 0 2006.173.22:21:33.33#ibcon#read 3, iclass 38, count 0 2006.173.22:21:33.33#ibcon#about to read 4, iclass 38, count 0 2006.173.22:21:33.33#ibcon#read 4, iclass 38, count 0 2006.173.22:21:33.33#ibcon#about to read 5, iclass 38, count 0 2006.173.22:21:33.33#ibcon#read 5, iclass 38, count 0 2006.173.22:21:33.33#ibcon#about to read 6, iclass 38, count 0 2006.173.22:21:33.33#ibcon#read 6, iclass 38, count 0 2006.173.22:21:33.33#ibcon#end of sib2, iclass 38, count 0 2006.173.22:21:33.33#ibcon#*after write, iclass 38, count 0 2006.173.22:21:33.33#ibcon#*before return 0, iclass 38, count 0 2006.173.22:21:33.33#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.22:21:33.33#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.22:21:33.33#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.22:21:33.33#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.22:21:33.33$vck44/va=1,7 2006.173.22:21:33.33#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.22:21:33.33#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.22:21:33.33#ibcon#ireg 11 cls_cnt 2 2006.173.22:21:33.33#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.22:21:33.33#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.22:21:33.33#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.22:21:33.33#ibcon#enter wrdev, iclass 40, count 2 2006.173.22:21:33.33#ibcon#first serial, iclass 40, count 2 2006.173.22:21:33.33#ibcon#enter sib2, iclass 40, count 2 2006.173.22:21:33.33#ibcon#flushed, iclass 40, count 2 2006.173.22:21:33.33#ibcon#about to write, iclass 40, count 2 2006.173.22:21:33.33#ibcon#wrote, iclass 40, count 2 2006.173.22:21:33.33#ibcon#about to read 3, iclass 40, count 2 2006.173.22:21:33.35#ibcon#read 3, iclass 40, count 2 2006.173.22:21:33.35#ibcon#about to read 4, iclass 40, count 2 2006.173.22:21:33.35#ibcon#read 4, iclass 40, count 2 2006.173.22:21:33.35#ibcon#about to read 5, iclass 40, count 2 2006.173.22:21:33.35#ibcon#read 5, iclass 40, count 2 2006.173.22:21:33.35#ibcon#about to read 6, iclass 40, count 2 2006.173.22:21:33.35#ibcon#read 6, iclass 40, count 2 2006.173.22:21:33.35#ibcon#end of sib2, iclass 40, count 2 2006.173.22:21:33.35#ibcon#*mode == 0, iclass 40, count 2 2006.173.22:21:33.35#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.22:21:33.35#ibcon#[25=AT01-07\r\n] 2006.173.22:21:33.35#ibcon#*before write, iclass 40, count 2 2006.173.22:21:33.35#ibcon#enter sib2, iclass 40, count 2 2006.173.22:21:33.35#ibcon#flushed, iclass 40, count 2 2006.173.22:21:33.35#ibcon#about to write, iclass 40, count 2 2006.173.22:21:33.35#ibcon#wrote, iclass 40, count 2 2006.173.22:21:33.35#ibcon#about to read 3, iclass 40, count 2 2006.173.22:21:33.38#ibcon#read 3, iclass 40, count 2 2006.173.22:21:33.38#ibcon#about to read 4, iclass 40, count 2 2006.173.22:21:33.38#ibcon#read 4, iclass 40, count 2 2006.173.22:21:33.38#ibcon#about to read 5, iclass 40, count 2 2006.173.22:21:33.38#ibcon#read 5, iclass 40, count 2 2006.173.22:21:33.38#ibcon#about to read 6, iclass 40, count 2 2006.173.22:21:33.38#ibcon#read 6, iclass 40, count 2 2006.173.22:21:33.38#ibcon#end of sib2, iclass 40, count 2 2006.173.22:21:33.38#ibcon#*after write, iclass 40, count 2 2006.173.22:21:33.38#ibcon#*before return 0, iclass 40, count 2 2006.173.22:21:33.38#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.22:21:33.38#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.22:21:33.38#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.22:21:33.38#ibcon#ireg 7 cls_cnt 0 2006.173.22:21:33.38#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.22:21:33.50#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.22:21:33.50#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.22:21:33.50#ibcon#enter wrdev, iclass 40, count 0 2006.173.22:21:33.50#ibcon#first serial, iclass 40, count 0 2006.173.22:21:33.50#ibcon#enter sib2, iclass 40, count 0 2006.173.22:21:33.50#ibcon#flushed, iclass 40, count 0 2006.173.22:21:33.50#ibcon#about to write, iclass 40, count 0 2006.173.22:21:33.50#ibcon#wrote, iclass 40, count 0 2006.173.22:21:33.50#ibcon#about to read 3, iclass 40, count 0 2006.173.22:21:33.52#ibcon#read 3, iclass 40, count 0 2006.173.22:21:33.52#ibcon#about to read 4, iclass 40, count 0 2006.173.22:21:33.52#ibcon#read 4, iclass 40, count 0 2006.173.22:21:33.52#ibcon#about to read 5, iclass 40, count 0 2006.173.22:21:33.52#ibcon#read 5, iclass 40, count 0 2006.173.22:21:33.52#ibcon#about to read 6, iclass 40, count 0 2006.173.22:21:33.52#ibcon#read 6, iclass 40, count 0 2006.173.22:21:33.52#ibcon#end of sib2, iclass 40, count 0 2006.173.22:21:33.52#ibcon#*mode == 0, iclass 40, count 0 2006.173.22:21:33.52#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.22:21:33.52#ibcon#[25=USB\r\n] 2006.173.22:21:33.52#ibcon#*before write, iclass 40, count 0 2006.173.22:21:33.52#ibcon#enter sib2, iclass 40, count 0 2006.173.22:21:33.52#ibcon#flushed, iclass 40, count 0 2006.173.22:21:33.52#ibcon#about to write, iclass 40, count 0 2006.173.22:21:33.52#ibcon#wrote, iclass 40, count 0 2006.173.22:21:33.52#ibcon#about to read 3, iclass 40, count 0 2006.173.22:21:33.55#ibcon#read 3, iclass 40, count 0 2006.173.22:21:33.55#ibcon#about to read 4, iclass 40, count 0 2006.173.22:21:33.55#ibcon#read 4, iclass 40, count 0 2006.173.22:21:33.55#ibcon#about to read 5, iclass 40, count 0 2006.173.22:21:33.55#ibcon#read 5, iclass 40, count 0 2006.173.22:21:33.55#ibcon#about to read 6, iclass 40, count 0 2006.173.22:21:33.55#ibcon#read 6, iclass 40, count 0 2006.173.22:21:33.55#ibcon#end of sib2, iclass 40, count 0 2006.173.22:21:33.55#ibcon#*after write, iclass 40, count 0 2006.173.22:21:33.55#ibcon#*before return 0, iclass 40, count 0 2006.173.22:21:33.55#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.22:21:33.55#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.22:21:33.55#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.22:21:33.55#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.22:21:33.55$vck44/valo=2,534.99 2006.173.22:21:33.55#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.22:21:33.55#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.22:21:33.55#ibcon#ireg 17 cls_cnt 0 2006.173.22:21:33.55#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.22:21:33.55#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.22:21:33.55#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.22:21:33.55#ibcon#enter wrdev, iclass 4, count 0 2006.173.22:21:33.55#ibcon#first serial, iclass 4, count 0 2006.173.22:21:33.55#ibcon#enter sib2, iclass 4, count 0 2006.173.22:21:33.55#ibcon#flushed, iclass 4, count 0 2006.173.22:21:33.55#ibcon#about to write, iclass 4, count 0 2006.173.22:21:33.55#ibcon#wrote, iclass 4, count 0 2006.173.22:21:33.55#ibcon#about to read 3, iclass 4, count 0 2006.173.22:21:33.57#ibcon#read 3, iclass 4, count 0 2006.173.22:21:33.57#ibcon#about to read 4, iclass 4, count 0 2006.173.22:21:33.57#ibcon#read 4, iclass 4, count 0 2006.173.22:21:33.57#ibcon#about to read 5, iclass 4, count 0 2006.173.22:21:33.57#ibcon#read 5, iclass 4, count 0 2006.173.22:21:33.57#ibcon#about to read 6, iclass 4, count 0 2006.173.22:21:33.57#ibcon#read 6, iclass 4, count 0 2006.173.22:21:33.57#ibcon#end of sib2, iclass 4, count 0 2006.173.22:21:33.57#ibcon#*mode == 0, iclass 4, count 0 2006.173.22:21:33.57#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.22:21:33.57#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.22:21:33.57#ibcon#*before write, iclass 4, count 0 2006.173.22:21:33.57#ibcon#enter sib2, iclass 4, count 0 2006.173.22:21:33.57#ibcon#flushed, iclass 4, count 0 2006.173.22:21:33.57#ibcon#about to write, iclass 4, count 0 2006.173.22:21:33.57#ibcon#wrote, iclass 4, count 0 2006.173.22:21:33.57#ibcon#about to read 3, iclass 4, count 0 2006.173.22:21:33.61#ibcon#read 3, iclass 4, count 0 2006.173.22:21:33.61#ibcon#about to read 4, iclass 4, count 0 2006.173.22:21:33.61#ibcon#read 4, iclass 4, count 0 2006.173.22:21:33.61#ibcon#about to read 5, iclass 4, count 0 2006.173.22:21:33.61#ibcon#read 5, iclass 4, count 0 2006.173.22:21:33.61#ibcon#about to read 6, iclass 4, count 0 2006.173.22:21:33.61#ibcon#read 6, iclass 4, count 0 2006.173.22:21:33.61#ibcon#end of sib2, iclass 4, count 0 2006.173.22:21:33.61#ibcon#*after write, iclass 4, count 0 2006.173.22:21:33.61#ibcon#*before return 0, iclass 4, count 0 2006.173.22:21:33.61#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.22:21:33.61#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.22:21:33.61#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.22:21:33.61#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.22:21:33.61$vck44/va=2,6 2006.173.22:21:33.61#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.22:21:33.61#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.22:21:33.61#ibcon#ireg 11 cls_cnt 2 2006.173.22:21:33.61#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.22:21:33.67#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.22:21:33.67#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.22:21:33.67#ibcon#enter wrdev, iclass 6, count 2 2006.173.22:21:33.67#ibcon#first serial, iclass 6, count 2 2006.173.22:21:33.67#ibcon#enter sib2, iclass 6, count 2 2006.173.22:21:33.67#ibcon#flushed, iclass 6, count 2 2006.173.22:21:33.67#ibcon#about to write, iclass 6, count 2 2006.173.22:21:33.67#ibcon#wrote, iclass 6, count 2 2006.173.22:21:33.67#ibcon#about to read 3, iclass 6, count 2 2006.173.22:21:33.69#ibcon#read 3, iclass 6, count 2 2006.173.22:21:33.69#ibcon#about to read 4, iclass 6, count 2 2006.173.22:21:33.69#ibcon#read 4, iclass 6, count 2 2006.173.22:21:33.69#ibcon#about to read 5, iclass 6, count 2 2006.173.22:21:33.69#ibcon#read 5, iclass 6, count 2 2006.173.22:21:33.69#ibcon#about to read 6, iclass 6, count 2 2006.173.22:21:33.69#ibcon#read 6, iclass 6, count 2 2006.173.22:21:33.69#ibcon#end of sib2, iclass 6, count 2 2006.173.22:21:33.69#ibcon#*mode == 0, iclass 6, count 2 2006.173.22:21:33.69#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.22:21:33.69#ibcon#[25=AT02-06\r\n] 2006.173.22:21:33.69#ibcon#*before write, iclass 6, count 2 2006.173.22:21:33.69#ibcon#enter sib2, iclass 6, count 2 2006.173.22:21:33.69#ibcon#flushed, iclass 6, count 2 2006.173.22:21:33.69#ibcon#about to write, iclass 6, count 2 2006.173.22:21:33.69#ibcon#wrote, iclass 6, count 2 2006.173.22:21:33.69#ibcon#about to read 3, iclass 6, count 2 2006.173.22:21:33.72#ibcon#read 3, iclass 6, count 2 2006.173.22:21:33.72#ibcon#about to read 4, iclass 6, count 2 2006.173.22:21:33.72#ibcon#read 4, iclass 6, count 2 2006.173.22:21:33.72#ibcon#about to read 5, iclass 6, count 2 2006.173.22:21:33.72#ibcon#read 5, iclass 6, count 2 2006.173.22:21:33.72#ibcon#about to read 6, iclass 6, count 2 2006.173.22:21:33.72#ibcon#read 6, iclass 6, count 2 2006.173.22:21:33.72#ibcon#end of sib2, iclass 6, count 2 2006.173.22:21:33.72#ibcon#*after write, iclass 6, count 2 2006.173.22:21:33.72#ibcon#*before return 0, iclass 6, count 2 2006.173.22:21:33.72#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.22:21:33.72#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.22:21:33.72#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.22:21:33.72#ibcon#ireg 7 cls_cnt 0 2006.173.22:21:33.72#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.22:21:33.84#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.22:21:33.84#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.22:21:33.84#ibcon#enter wrdev, iclass 6, count 0 2006.173.22:21:33.84#ibcon#first serial, iclass 6, count 0 2006.173.22:21:33.84#ibcon#enter sib2, iclass 6, count 0 2006.173.22:21:33.84#ibcon#flushed, iclass 6, count 0 2006.173.22:21:33.84#ibcon#about to write, iclass 6, count 0 2006.173.22:21:33.84#ibcon#wrote, iclass 6, count 0 2006.173.22:21:33.84#ibcon#about to read 3, iclass 6, count 0 2006.173.22:21:33.86#ibcon#read 3, iclass 6, count 0 2006.173.22:21:33.86#ibcon#about to read 4, iclass 6, count 0 2006.173.22:21:33.86#ibcon#read 4, iclass 6, count 0 2006.173.22:21:33.86#ibcon#about to read 5, iclass 6, count 0 2006.173.22:21:33.86#ibcon#read 5, iclass 6, count 0 2006.173.22:21:33.86#ibcon#about to read 6, iclass 6, count 0 2006.173.22:21:33.86#ibcon#read 6, iclass 6, count 0 2006.173.22:21:33.86#ibcon#end of sib2, iclass 6, count 0 2006.173.22:21:33.86#ibcon#*mode == 0, iclass 6, count 0 2006.173.22:21:33.86#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.22:21:33.86#ibcon#[25=USB\r\n] 2006.173.22:21:33.86#ibcon#*before write, iclass 6, count 0 2006.173.22:21:33.86#ibcon#enter sib2, iclass 6, count 0 2006.173.22:21:33.86#ibcon#flushed, iclass 6, count 0 2006.173.22:21:33.86#ibcon#about to write, iclass 6, count 0 2006.173.22:21:33.86#ibcon#wrote, iclass 6, count 0 2006.173.22:21:33.86#ibcon#about to read 3, iclass 6, count 0 2006.173.22:21:33.89#ibcon#read 3, iclass 6, count 0 2006.173.22:21:33.89#ibcon#about to read 4, iclass 6, count 0 2006.173.22:21:33.89#ibcon#read 4, iclass 6, count 0 2006.173.22:21:33.89#ibcon#about to read 5, iclass 6, count 0 2006.173.22:21:33.89#ibcon#read 5, iclass 6, count 0 2006.173.22:21:33.89#ibcon#about to read 6, iclass 6, count 0 2006.173.22:21:33.89#ibcon#read 6, iclass 6, count 0 2006.173.22:21:33.89#ibcon#end of sib2, iclass 6, count 0 2006.173.22:21:33.89#ibcon#*after write, iclass 6, count 0 2006.173.22:21:33.89#ibcon#*before return 0, iclass 6, count 0 2006.173.22:21:33.89#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.22:21:33.89#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.22:21:33.89#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.22:21:33.89#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.22:21:33.89$vck44/valo=3,564.99 2006.173.22:21:33.89#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.22:21:33.89#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.22:21:33.89#ibcon#ireg 17 cls_cnt 0 2006.173.22:21:33.89#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.22:21:33.89#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.22:21:33.89#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.22:21:33.89#ibcon#enter wrdev, iclass 10, count 0 2006.173.22:21:33.89#ibcon#first serial, iclass 10, count 0 2006.173.22:21:33.89#ibcon#enter sib2, iclass 10, count 0 2006.173.22:21:33.89#ibcon#flushed, iclass 10, count 0 2006.173.22:21:33.89#ibcon#about to write, iclass 10, count 0 2006.173.22:21:33.89#ibcon#wrote, iclass 10, count 0 2006.173.22:21:33.89#ibcon#about to read 3, iclass 10, count 0 2006.173.22:21:33.91#ibcon#read 3, iclass 10, count 0 2006.173.22:21:33.91#ibcon#about to read 4, iclass 10, count 0 2006.173.22:21:33.91#ibcon#read 4, iclass 10, count 0 2006.173.22:21:33.91#ibcon#about to read 5, iclass 10, count 0 2006.173.22:21:33.91#ibcon#read 5, iclass 10, count 0 2006.173.22:21:33.91#ibcon#about to read 6, iclass 10, count 0 2006.173.22:21:33.91#ibcon#read 6, iclass 10, count 0 2006.173.22:21:33.91#ibcon#end of sib2, iclass 10, count 0 2006.173.22:21:33.91#ibcon#*mode == 0, iclass 10, count 0 2006.173.22:21:33.91#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.22:21:33.91#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.22:21:33.91#ibcon#*before write, iclass 10, count 0 2006.173.22:21:33.91#ibcon#enter sib2, iclass 10, count 0 2006.173.22:21:33.91#ibcon#flushed, iclass 10, count 0 2006.173.22:21:33.91#ibcon#about to write, iclass 10, count 0 2006.173.22:21:33.91#ibcon#wrote, iclass 10, count 0 2006.173.22:21:33.91#ibcon#about to read 3, iclass 10, count 0 2006.173.22:21:33.95#ibcon#read 3, iclass 10, count 0 2006.173.22:21:33.95#ibcon#about to read 4, iclass 10, count 0 2006.173.22:21:33.95#ibcon#read 4, iclass 10, count 0 2006.173.22:21:33.95#ibcon#about to read 5, iclass 10, count 0 2006.173.22:21:33.95#ibcon#read 5, iclass 10, count 0 2006.173.22:21:33.95#ibcon#about to read 6, iclass 10, count 0 2006.173.22:21:33.95#ibcon#read 6, iclass 10, count 0 2006.173.22:21:33.95#ibcon#end of sib2, iclass 10, count 0 2006.173.22:21:33.95#ibcon#*after write, iclass 10, count 0 2006.173.22:21:33.95#ibcon#*before return 0, iclass 10, count 0 2006.173.22:21:33.95#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.22:21:33.95#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.22:21:33.95#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.22:21:33.95#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.22:21:33.95$vck44/va=3,5 2006.173.22:21:33.95#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.22:21:33.95#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.22:21:33.95#ibcon#ireg 11 cls_cnt 2 2006.173.22:21:33.95#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.22:21:34.01#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.22:21:34.01#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.22:21:34.01#ibcon#enter wrdev, iclass 12, count 2 2006.173.22:21:34.01#ibcon#first serial, iclass 12, count 2 2006.173.22:21:34.01#ibcon#enter sib2, iclass 12, count 2 2006.173.22:21:34.01#ibcon#flushed, iclass 12, count 2 2006.173.22:21:34.01#ibcon#about to write, iclass 12, count 2 2006.173.22:21:34.01#ibcon#wrote, iclass 12, count 2 2006.173.22:21:34.01#ibcon#about to read 3, iclass 12, count 2 2006.173.22:21:34.03#ibcon#read 3, iclass 12, count 2 2006.173.22:21:34.03#ibcon#about to read 4, iclass 12, count 2 2006.173.22:21:34.03#ibcon#read 4, iclass 12, count 2 2006.173.22:21:34.03#ibcon#about to read 5, iclass 12, count 2 2006.173.22:21:34.03#ibcon#read 5, iclass 12, count 2 2006.173.22:21:34.03#ibcon#about to read 6, iclass 12, count 2 2006.173.22:21:34.03#ibcon#read 6, iclass 12, count 2 2006.173.22:21:34.03#ibcon#end of sib2, iclass 12, count 2 2006.173.22:21:34.03#ibcon#*mode == 0, iclass 12, count 2 2006.173.22:21:34.03#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.22:21:34.03#ibcon#[25=AT03-05\r\n] 2006.173.22:21:34.03#ibcon#*before write, iclass 12, count 2 2006.173.22:21:34.03#ibcon#enter sib2, iclass 12, count 2 2006.173.22:21:34.03#ibcon#flushed, iclass 12, count 2 2006.173.22:21:34.03#ibcon#about to write, iclass 12, count 2 2006.173.22:21:34.03#ibcon#wrote, iclass 12, count 2 2006.173.22:21:34.03#ibcon#about to read 3, iclass 12, count 2 2006.173.22:21:34.06#ibcon#read 3, iclass 12, count 2 2006.173.22:21:34.06#ibcon#about to read 4, iclass 12, count 2 2006.173.22:21:34.06#ibcon#read 4, iclass 12, count 2 2006.173.22:21:34.06#ibcon#about to read 5, iclass 12, count 2 2006.173.22:21:34.06#ibcon#read 5, iclass 12, count 2 2006.173.22:21:34.06#ibcon#about to read 6, iclass 12, count 2 2006.173.22:21:34.06#ibcon#read 6, iclass 12, count 2 2006.173.22:21:34.06#ibcon#end of sib2, iclass 12, count 2 2006.173.22:21:34.06#ibcon#*after write, iclass 12, count 2 2006.173.22:21:34.06#ibcon#*before return 0, iclass 12, count 2 2006.173.22:21:34.06#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.22:21:34.06#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.22:21:34.06#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.22:21:34.06#ibcon#ireg 7 cls_cnt 0 2006.173.22:21:34.06#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.22:21:34.18#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.22:21:34.18#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.22:21:34.18#ibcon#enter wrdev, iclass 12, count 0 2006.173.22:21:34.18#ibcon#first serial, iclass 12, count 0 2006.173.22:21:34.18#ibcon#enter sib2, iclass 12, count 0 2006.173.22:21:34.18#ibcon#flushed, iclass 12, count 0 2006.173.22:21:34.18#ibcon#about to write, iclass 12, count 0 2006.173.22:21:34.18#ibcon#wrote, iclass 12, count 0 2006.173.22:21:34.18#ibcon#about to read 3, iclass 12, count 0 2006.173.22:21:34.20#ibcon#read 3, iclass 12, count 0 2006.173.22:21:34.20#ibcon#about to read 4, iclass 12, count 0 2006.173.22:21:34.20#ibcon#read 4, iclass 12, count 0 2006.173.22:21:34.20#ibcon#about to read 5, iclass 12, count 0 2006.173.22:21:34.20#ibcon#read 5, iclass 12, count 0 2006.173.22:21:34.20#ibcon#about to read 6, iclass 12, count 0 2006.173.22:21:34.20#ibcon#read 6, iclass 12, count 0 2006.173.22:21:34.20#ibcon#end of sib2, iclass 12, count 0 2006.173.22:21:34.20#ibcon#*mode == 0, iclass 12, count 0 2006.173.22:21:34.20#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.22:21:34.20#ibcon#[25=USB\r\n] 2006.173.22:21:34.20#ibcon#*before write, iclass 12, count 0 2006.173.22:21:34.20#ibcon#enter sib2, iclass 12, count 0 2006.173.22:21:34.20#ibcon#flushed, iclass 12, count 0 2006.173.22:21:34.20#ibcon#about to write, iclass 12, count 0 2006.173.22:21:34.20#ibcon#wrote, iclass 12, count 0 2006.173.22:21:34.20#ibcon#about to read 3, iclass 12, count 0 2006.173.22:21:34.23#ibcon#read 3, iclass 12, count 0 2006.173.22:21:34.23#ibcon#about to read 4, iclass 12, count 0 2006.173.22:21:34.23#ibcon#read 4, iclass 12, count 0 2006.173.22:21:34.23#ibcon#about to read 5, iclass 12, count 0 2006.173.22:21:34.23#ibcon#read 5, iclass 12, count 0 2006.173.22:21:34.23#ibcon#about to read 6, iclass 12, count 0 2006.173.22:21:34.23#ibcon#read 6, iclass 12, count 0 2006.173.22:21:34.23#ibcon#end of sib2, iclass 12, count 0 2006.173.22:21:34.23#ibcon#*after write, iclass 12, count 0 2006.173.22:21:34.23#ibcon#*before return 0, iclass 12, count 0 2006.173.22:21:34.23#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.22:21:34.23#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.22:21:34.23#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.22:21:34.23#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.22:21:34.23$vck44/valo=4,624.99 2006.173.22:21:34.23#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.22:21:34.23#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.22:21:34.23#ibcon#ireg 17 cls_cnt 0 2006.173.22:21:34.23#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.22:21:34.23#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.22:21:34.23#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.22:21:34.23#ibcon#enter wrdev, iclass 14, count 0 2006.173.22:21:34.23#ibcon#first serial, iclass 14, count 0 2006.173.22:21:34.23#ibcon#enter sib2, iclass 14, count 0 2006.173.22:21:34.23#ibcon#flushed, iclass 14, count 0 2006.173.22:21:34.23#ibcon#about to write, iclass 14, count 0 2006.173.22:21:34.23#ibcon#wrote, iclass 14, count 0 2006.173.22:21:34.23#ibcon#about to read 3, iclass 14, count 0 2006.173.22:21:34.25#ibcon#read 3, iclass 14, count 0 2006.173.22:21:34.25#ibcon#about to read 4, iclass 14, count 0 2006.173.22:21:34.25#ibcon#read 4, iclass 14, count 0 2006.173.22:21:34.25#ibcon#about to read 5, iclass 14, count 0 2006.173.22:21:34.25#ibcon#read 5, iclass 14, count 0 2006.173.22:21:34.25#ibcon#about to read 6, iclass 14, count 0 2006.173.22:21:34.25#ibcon#read 6, iclass 14, count 0 2006.173.22:21:34.25#ibcon#end of sib2, iclass 14, count 0 2006.173.22:21:34.25#ibcon#*mode == 0, iclass 14, count 0 2006.173.22:21:34.25#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.22:21:34.25#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.22:21:34.25#ibcon#*before write, iclass 14, count 0 2006.173.22:21:34.25#ibcon#enter sib2, iclass 14, count 0 2006.173.22:21:34.25#ibcon#flushed, iclass 14, count 0 2006.173.22:21:34.25#ibcon#about to write, iclass 14, count 0 2006.173.22:21:34.25#ibcon#wrote, iclass 14, count 0 2006.173.22:21:34.25#ibcon#about to read 3, iclass 14, count 0 2006.173.22:21:34.29#ibcon#read 3, iclass 14, count 0 2006.173.22:21:34.29#ibcon#about to read 4, iclass 14, count 0 2006.173.22:21:34.29#ibcon#read 4, iclass 14, count 0 2006.173.22:21:34.29#ibcon#about to read 5, iclass 14, count 0 2006.173.22:21:34.29#ibcon#read 5, iclass 14, count 0 2006.173.22:21:34.29#ibcon#about to read 6, iclass 14, count 0 2006.173.22:21:34.29#ibcon#read 6, iclass 14, count 0 2006.173.22:21:34.29#ibcon#end of sib2, iclass 14, count 0 2006.173.22:21:34.29#ibcon#*after write, iclass 14, count 0 2006.173.22:21:34.29#ibcon#*before return 0, iclass 14, count 0 2006.173.22:21:34.29#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.22:21:34.29#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.22:21:34.29#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.22:21:34.29#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.22:21:34.29$vck44/va=4,6 2006.173.22:21:34.29#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.22:21:34.29#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.22:21:34.29#ibcon#ireg 11 cls_cnt 2 2006.173.22:21:34.29#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.22:21:34.35#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.22:21:34.35#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.22:21:34.35#ibcon#enter wrdev, iclass 16, count 2 2006.173.22:21:34.35#ibcon#first serial, iclass 16, count 2 2006.173.22:21:34.35#ibcon#enter sib2, iclass 16, count 2 2006.173.22:21:34.35#ibcon#flushed, iclass 16, count 2 2006.173.22:21:34.35#ibcon#about to write, iclass 16, count 2 2006.173.22:21:34.35#ibcon#wrote, iclass 16, count 2 2006.173.22:21:34.35#ibcon#about to read 3, iclass 16, count 2 2006.173.22:21:34.37#ibcon#read 3, iclass 16, count 2 2006.173.22:21:34.37#ibcon#about to read 4, iclass 16, count 2 2006.173.22:21:34.37#ibcon#read 4, iclass 16, count 2 2006.173.22:21:34.37#ibcon#about to read 5, iclass 16, count 2 2006.173.22:21:34.37#ibcon#read 5, iclass 16, count 2 2006.173.22:21:34.37#ibcon#about to read 6, iclass 16, count 2 2006.173.22:21:34.37#ibcon#read 6, iclass 16, count 2 2006.173.22:21:34.37#ibcon#end of sib2, iclass 16, count 2 2006.173.22:21:34.37#ibcon#*mode == 0, iclass 16, count 2 2006.173.22:21:34.37#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.22:21:34.37#ibcon#[25=AT04-06\r\n] 2006.173.22:21:34.37#ibcon#*before write, iclass 16, count 2 2006.173.22:21:34.37#ibcon#enter sib2, iclass 16, count 2 2006.173.22:21:34.37#ibcon#flushed, iclass 16, count 2 2006.173.22:21:34.37#ibcon#about to write, iclass 16, count 2 2006.173.22:21:34.37#ibcon#wrote, iclass 16, count 2 2006.173.22:21:34.37#ibcon#about to read 3, iclass 16, count 2 2006.173.22:21:34.40#ibcon#read 3, iclass 16, count 2 2006.173.22:21:34.40#ibcon#about to read 4, iclass 16, count 2 2006.173.22:21:34.40#ibcon#read 4, iclass 16, count 2 2006.173.22:21:34.40#ibcon#about to read 5, iclass 16, count 2 2006.173.22:21:34.40#ibcon#read 5, iclass 16, count 2 2006.173.22:21:34.40#ibcon#about to read 6, iclass 16, count 2 2006.173.22:21:34.40#ibcon#read 6, iclass 16, count 2 2006.173.22:21:34.40#ibcon#end of sib2, iclass 16, count 2 2006.173.22:21:34.40#ibcon#*after write, iclass 16, count 2 2006.173.22:21:34.40#ibcon#*before return 0, iclass 16, count 2 2006.173.22:21:34.40#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.22:21:34.40#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.22:21:34.40#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.22:21:34.40#ibcon#ireg 7 cls_cnt 0 2006.173.22:21:34.40#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.22:21:34.52#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.22:21:34.52#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.22:21:34.52#ibcon#enter wrdev, iclass 16, count 0 2006.173.22:21:34.52#ibcon#first serial, iclass 16, count 0 2006.173.22:21:34.52#ibcon#enter sib2, iclass 16, count 0 2006.173.22:21:34.52#ibcon#flushed, iclass 16, count 0 2006.173.22:21:34.52#ibcon#about to write, iclass 16, count 0 2006.173.22:21:34.52#ibcon#wrote, iclass 16, count 0 2006.173.22:21:34.52#ibcon#about to read 3, iclass 16, count 0 2006.173.22:21:34.54#ibcon#read 3, iclass 16, count 0 2006.173.22:21:34.54#ibcon#about to read 4, iclass 16, count 0 2006.173.22:21:34.54#ibcon#read 4, iclass 16, count 0 2006.173.22:21:34.54#ibcon#about to read 5, iclass 16, count 0 2006.173.22:21:34.54#ibcon#read 5, iclass 16, count 0 2006.173.22:21:34.54#ibcon#about to read 6, iclass 16, count 0 2006.173.22:21:34.54#ibcon#read 6, iclass 16, count 0 2006.173.22:21:34.54#ibcon#end of sib2, iclass 16, count 0 2006.173.22:21:34.54#ibcon#*mode == 0, iclass 16, count 0 2006.173.22:21:34.54#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.22:21:34.54#ibcon#[25=USB\r\n] 2006.173.22:21:34.54#ibcon#*before write, iclass 16, count 0 2006.173.22:21:34.54#ibcon#enter sib2, iclass 16, count 0 2006.173.22:21:34.54#ibcon#flushed, iclass 16, count 0 2006.173.22:21:34.54#ibcon#about to write, iclass 16, count 0 2006.173.22:21:34.54#ibcon#wrote, iclass 16, count 0 2006.173.22:21:34.54#ibcon#about to read 3, iclass 16, count 0 2006.173.22:21:34.57#ibcon#read 3, iclass 16, count 0 2006.173.22:21:34.57#ibcon#about to read 4, iclass 16, count 0 2006.173.22:21:34.57#ibcon#read 4, iclass 16, count 0 2006.173.22:21:34.57#ibcon#about to read 5, iclass 16, count 0 2006.173.22:21:34.57#ibcon#read 5, iclass 16, count 0 2006.173.22:21:34.57#ibcon#about to read 6, iclass 16, count 0 2006.173.22:21:34.57#ibcon#read 6, iclass 16, count 0 2006.173.22:21:34.57#ibcon#end of sib2, iclass 16, count 0 2006.173.22:21:34.57#ibcon#*after write, iclass 16, count 0 2006.173.22:21:34.57#ibcon#*before return 0, iclass 16, count 0 2006.173.22:21:34.57#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.22:21:34.57#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.22:21:34.57#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.22:21:34.57#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.22:21:34.57$vck44/valo=5,734.99 2006.173.22:21:34.57#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.22:21:34.57#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.22:21:34.57#ibcon#ireg 17 cls_cnt 0 2006.173.22:21:34.57#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.22:21:34.57#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.22:21:34.57#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.22:21:34.57#ibcon#enter wrdev, iclass 18, count 0 2006.173.22:21:34.57#ibcon#first serial, iclass 18, count 0 2006.173.22:21:34.57#ibcon#enter sib2, iclass 18, count 0 2006.173.22:21:34.57#ibcon#flushed, iclass 18, count 0 2006.173.22:21:34.57#ibcon#about to write, iclass 18, count 0 2006.173.22:21:34.57#ibcon#wrote, iclass 18, count 0 2006.173.22:21:34.57#ibcon#about to read 3, iclass 18, count 0 2006.173.22:21:34.59#ibcon#read 3, iclass 18, count 0 2006.173.22:21:34.59#ibcon#about to read 4, iclass 18, count 0 2006.173.22:21:34.59#ibcon#read 4, iclass 18, count 0 2006.173.22:21:34.59#ibcon#about to read 5, iclass 18, count 0 2006.173.22:21:34.59#ibcon#read 5, iclass 18, count 0 2006.173.22:21:34.59#ibcon#about to read 6, iclass 18, count 0 2006.173.22:21:34.59#ibcon#read 6, iclass 18, count 0 2006.173.22:21:34.59#ibcon#end of sib2, iclass 18, count 0 2006.173.22:21:34.59#ibcon#*mode == 0, iclass 18, count 0 2006.173.22:21:34.59#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.22:21:34.59#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.22:21:34.59#ibcon#*before write, iclass 18, count 0 2006.173.22:21:34.59#ibcon#enter sib2, iclass 18, count 0 2006.173.22:21:34.59#ibcon#flushed, iclass 18, count 0 2006.173.22:21:34.59#ibcon#about to write, iclass 18, count 0 2006.173.22:21:34.59#ibcon#wrote, iclass 18, count 0 2006.173.22:21:34.59#ibcon#about to read 3, iclass 18, count 0 2006.173.22:21:34.63#ibcon#read 3, iclass 18, count 0 2006.173.22:21:34.63#ibcon#about to read 4, iclass 18, count 0 2006.173.22:21:34.63#ibcon#read 4, iclass 18, count 0 2006.173.22:21:34.63#ibcon#about to read 5, iclass 18, count 0 2006.173.22:21:34.63#ibcon#read 5, iclass 18, count 0 2006.173.22:21:34.63#ibcon#about to read 6, iclass 18, count 0 2006.173.22:21:34.63#ibcon#read 6, iclass 18, count 0 2006.173.22:21:34.63#ibcon#end of sib2, iclass 18, count 0 2006.173.22:21:34.63#ibcon#*after write, iclass 18, count 0 2006.173.22:21:34.63#ibcon#*before return 0, iclass 18, count 0 2006.173.22:21:34.63#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.22:21:34.63#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.22:21:34.63#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.22:21:34.63#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.22:21:34.63$vck44/va=5,4 2006.173.22:21:34.63#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.22:21:34.63#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.22:21:34.63#ibcon#ireg 11 cls_cnt 2 2006.173.22:21:34.63#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.22:21:34.69#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.22:21:34.69#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.22:21:34.69#ibcon#enter wrdev, iclass 20, count 2 2006.173.22:21:34.69#ibcon#first serial, iclass 20, count 2 2006.173.22:21:34.69#ibcon#enter sib2, iclass 20, count 2 2006.173.22:21:34.69#ibcon#flushed, iclass 20, count 2 2006.173.22:21:34.69#ibcon#about to write, iclass 20, count 2 2006.173.22:21:34.69#ibcon#wrote, iclass 20, count 2 2006.173.22:21:34.69#ibcon#about to read 3, iclass 20, count 2 2006.173.22:21:34.71#ibcon#read 3, iclass 20, count 2 2006.173.22:21:34.71#ibcon#about to read 4, iclass 20, count 2 2006.173.22:21:34.71#ibcon#read 4, iclass 20, count 2 2006.173.22:21:34.71#ibcon#about to read 5, iclass 20, count 2 2006.173.22:21:34.71#ibcon#read 5, iclass 20, count 2 2006.173.22:21:34.71#ibcon#about to read 6, iclass 20, count 2 2006.173.22:21:34.71#ibcon#read 6, iclass 20, count 2 2006.173.22:21:34.71#ibcon#end of sib2, iclass 20, count 2 2006.173.22:21:34.71#ibcon#*mode == 0, iclass 20, count 2 2006.173.22:21:34.71#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.22:21:34.71#ibcon#[25=AT05-04\r\n] 2006.173.22:21:34.71#ibcon#*before write, iclass 20, count 2 2006.173.22:21:34.71#ibcon#enter sib2, iclass 20, count 2 2006.173.22:21:34.71#ibcon#flushed, iclass 20, count 2 2006.173.22:21:34.71#ibcon#about to write, iclass 20, count 2 2006.173.22:21:34.71#ibcon#wrote, iclass 20, count 2 2006.173.22:21:34.71#ibcon#about to read 3, iclass 20, count 2 2006.173.22:21:34.74#ibcon#read 3, iclass 20, count 2 2006.173.22:21:34.74#ibcon#about to read 4, iclass 20, count 2 2006.173.22:21:34.74#ibcon#read 4, iclass 20, count 2 2006.173.22:21:34.74#ibcon#about to read 5, iclass 20, count 2 2006.173.22:21:34.74#ibcon#read 5, iclass 20, count 2 2006.173.22:21:34.74#ibcon#about to read 6, iclass 20, count 2 2006.173.22:21:34.74#ibcon#read 6, iclass 20, count 2 2006.173.22:21:34.74#ibcon#end of sib2, iclass 20, count 2 2006.173.22:21:34.74#ibcon#*after write, iclass 20, count 2 2006.173.22:21:34.74#ibcon#*before return 0, iclass 20, count 2 2006.173.22:21:34.74#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.22:21:34.74#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.22:21:34.74#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.22:21:34.74#ibcon#ireg 7 cls_cnt 0 2006.173.22:21:34.74#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.22:21:34.86#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.22:21:34.86#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.22:21:34.86#ibcon#enter wrdev, iclass 20, count 0 2006.173.22:21:34.86#ibcon#first serial, iclass 20, count 0 2006.173.22:21:34.86#ibcon#enter sib2, iclass 20, count 0 2006.173.22:21:34.86#ibcon#flushed, iclass 20, count 0 2006.173.22:21:34.86#ibcon#about to write, iclass 20, count 0 2006.173.22:21:34.86#ibcon#wrote, iclass 20, count 0 2006.173.22:21:34.86#ibcon#about to read 3, iclass 20, count 0 2006.173.22:21:34.88#ibcon#read 3, iclass 20, count 0 2006.173.22:21:34.88#ibcon#about to read 4, iclass 20, count 0 2006.173.22:21:34.88#ibcon#read 4, iclass 20, count 0 2006.173.22:21:34.88#ibcon#about to read 5, iclass 20, count 0 2006.173.22:21:34.88#ibcon#read 5, iclass 20, count 0 2006.173.22:21:34.88#ibcon#about to read 6, iclass 20, count 0 2006.173.22:21:34.88#ibcon#read 6, iclass 20, count 0 2006.173.22:21:34.88#ibcon#end of sib2, iclass 20, count 0 2006.173.22:21:34.88#ibcon#*mode == 0, iclass 20, count 0 2006.173.22:21:34.88#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.22:21:34.88#ibcon#[25=USB\r\n] 2006.173.22:21:34.88#ibcon#*before write, iclass 20, count 0 2006.173.22:21:34.88#ibcon#enter sib2, iclass 20, count 0 2006.173.22:21:34.88#ibcon#flushed, iclass 20, count 0 2006.173.22:21:34.88#ibcon#about to write, iclass 20, count 0 2006.173.22:21:34.88#ibcon#wrote, iclass 20, count 0 2006.173.22:21:34.88#ibcon#about to read 3, iclass 20, count 0 2006.173.22:21:34.91#ibcon#read 3, iclass 20, count 0 2006.173.22:21:34.91#ibcon#about to read 4, iclass 20, count 0 2006.173.22:21:34.91#ibcon#read 4, iclass 20, count 0 2006.173.22:21:34.91#ibcon#about to read 5, iclass 20, count 0 2006.173.22:21:34.91#ibcon#read 5, iclass 20, count 0 2006.173.22:21:34.91#ibcon#about to read 6, iclass 20, count 0 2006.173.22:21:34.91#ibcon#read 6, iclass 20, count 0 2006.173.22:21:34.91#ibcon#end of sib2, iclass 20, count 0 2006.173.22:21:34.91#ibcon#*after write, iclass 20, count 0 2006.173.22:21:34.91#ibcon#*before return 0, iclass 20, count 0 2006.173.22:21:34.91#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.22:21:34.91#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.22:21:34.91#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.22:21:34.91#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.22:21:34.91$vck44/valo=6,814.99 2006.173.22:21:34.91#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.22:21:34.91#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.22:21:34.91#ibcon#ireg 17 cls_cnt 0 2006.173.22:21:34.91#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.22:21:34.91#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.22:21:34.91#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.22:21:34.91#ibcon#enter wrdev, iclass 22, count 0 2006.173.22:21:34.91#ibcon#first serial, iclass 22, count 0 2006.173.22:21:34.91#ibcon#enter sib2, iclass 22, count 0 2006.173.22:21:34.91#ibcon#flushed, iclass 22, count 0 2006.173.22:21:34.91#ibcon#about to write, iclass 22, count 0 2006.173.22:21:34.91#ibcon#wrote, iclass 22, count 0 2006.173.22:21:34.91#ibcon#about to read 3, iclass 22, count 0 2006.173.22:21:34.93#ibcon#read 3, iclass 22, count 0 2006.173.22:21:34.93#ibcon#about to read 4, iclass 22, count 0 2006.173.22:21:34.93#ibcon#read 4, iclass 22, count 0 2006.173.22:21:34.93#ibcon#about to read 5, iclass 22, count 0 2006.173.22:21:34.93#ibcon#read 5, iclass 22, count 0 2006.173.22:21:34.93#ibcon#about to read 6, iclass 22, count 0 2006.173.22:21:34.93#ibcon#read 6, iclass 22, count 0 2006.173.22:21:34.93#ibcon#end of sib2, iclass 22, count 0 2006.173.22:21:34.93#ibcon#*mode == 0, iclass 22, count 0 2006.173.22:21:34.93#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.22:21:34.93#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.22:21:34.93#ibcon#*before write, iclass 22, count 0 2006.173.22:21:34.93#ibcon#enter sib2, iclass 22, count 0 2006.173.22:21:34.93#ibcon#flushed, iclass 22, count 0 2006.173.22:21:34.93#ibcon#about to write, iclass 22, count 0 2006.173.22:21:34.93#ibcon#wrote, iclass 22, count 0 2006.173.22:21:34.93#ibcon#about to read 3, iclass 22, count 0 2006.173.22:21:34.97#ibcon#read 3, iclass 22, count 0 2006.173.22:21:34.97#ibcon#about to read 4, iclass 22, count 0 2006.173.22:21:34.97#ibcon#read 4, iclass 22, count 0 2006.173.22:21:34.97#ibcon#about to read 5, iclass 22, count 0 2006.173.22:21:34.97#ibcon#read 5, iclass 22, count 0 2006.173.22:21:34.97#ibcon#about to read 6, iclass 22, count 0 2006.173.22:21:34.97#ibcon#read 6, iclass 22, count 0 2006.173.22:21:34.97#ibcon#end of sib2, iclass 22, count 0 2006.173.22:21:34.97#ibcon#*after write, iclass 22, count 0 2006.173.22:21:34.97#ibcon#*before return 0, iclass 22, count 0 2006.173.22:21:34.97#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.22:21:34.97#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.22:21:34.97#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.22:21:34.97#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.22:21:34.97$vck44/va=6,3 2006.173.22:21:34.97#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.22:21:34.97#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.22:21:34.97#ibcon#ireg 11 cls_cnt 2 2006.173.22:21:34.97#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.22:21:35.03#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.22:21:35.03#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.22:21:35.03#ibcon#enter wrdev, iclass 24, count 2 2006.173.22:21:35.03#ibcon#first serial, iclass 24, count 2 2006.173.22:21:35.03#ibcon#enter sib2, iclass 24, count 2 2006.173.22:21:35.03#ibcon#flushed, iclass 24, count 2 2006.173.22:21:35.03#ibcon#about to write, iclass 24, count 2 2006.173.22:21:35.03#ibcon#wrote, iclass 24, count 2 2006.173.22:21:35.03#ibcon#about to read 3, iclass 24, count 2 2006.173.22:21:35.05#ibcon#read 3, iclass 24, count 2 2006.173.22:21:35.05#ibcon#about to read 4, iclass 24, count 2 2006.173.22:21:35.05#ibcon#read 4, iclass 24, count 2 2006.173.22:21:35.05#ibcon#about to read 5, iclass 24, count 2 2006.173.22:21:35.05#ibcon#read 5, iclass 24, count 2 2006.173.22:21:35.05#ibcon#about to read 6, iclass 24, count 2 2006.173.22:21:35.05#ibcon#read 6, iclass 24, count 2 2006.173.22:21:35.05#ibcon#end of sib2, iclass 24, count 2 2006.173.22:21:35.05#ibcon#*mode == 0, iclass 24, count 2 2006.173.22:21:35.05#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.22:21:35.05#ibcon#[25=AT06-03\r\n] 2006.173.22:21:35.05#ibcon#*before write, iclass 24, count 2 2006.173.22:21:35.05#ibcon#enter sib2, iclass 24, count 2 2006.173.22:21:35.05#ibcon#flushed, iclass 24, count 2 2006.173.22:21:35.05#ibcon#about to write, iclass 24, count 2 2006.173.22:21:35.05#ibcon#wrote, iclass 24, count 2 2006.173.22:21:35.05#ibcon#about to read 3, iclass 24, count 2 2006.173.22:21:35.08#ibcon#read 3, iclass 24, count 2 2006.173.22:21:35.08#ibcon#about to read 4, iclass 24, count 2 2006.173.22:21:35.08#ibcon#read 4, iclass 24, count 2 2006.173.22:21:35.08#ibcon#about to read 5, iclass 24, count 2 2006.173.22:21:35.08#ibcon#read 5, iclass 24, count 2 2006.173.22:21:35.08#ibcon#about to read 6, iclass 24, count 2 2006.173.22:21:35.08#ibcon#read 6, iclass 24, count 2 2006.173.22:21:35.08#ibcon#end of sib2, iclass 24, count 2 2006.173.22:21:35.08#ibcon#*after write, iclass 24, count 2 2006.173.22:21:35.08#ibcon#*before return 0, iclass 24, count 2 2006.173.22:21:35.08#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.22:21:35.08#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.22:21:35.08#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.22:21:35.08#ibcon#ireg 7 cls_cnt 0 2006.173.22:21:35.08#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.22:21:35.20#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.22:21:35.20#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.22:21:35.20#ibcon#enter wrdev, iclass 24, count 0 2006.173.22:21:35.20#ibcon#first serial, iclass 24, count 0 2006.173.22:21:35.20#ibcon#enter sib2, iclass 24, count 0 2006.173.22:21:35.20#ibcon#flushed, iclass 24, count 0 2006.173.22:21:35.20#ibcon#about to write, iclass 24, count 0 2006.173.22:21:35.20#ibcon#wrote, iclass 24, count 0 2006.173.22:21:35.20#ibcon#about to read 3, iclass 24, count 0 2006.173.22:21:35.22#ibcon#read 3, iclass 24, count 0 2006.173.22:21:35.22#ibcon#about to read 4, iclass 24, count 0 2006.173.22:21:35.22#ibcon#read 4, iclass 24, count 0 2006.173.22:21:35.22#ibcon#about to read 5, iclass 24, count 0 2006.173.22:21:35.22#ibcon#read 5, iclass 24, count 0 2006.173.22:21:35.22#ibcon#about to read 6, iclass 24, count 0 2006.173.22:21:35.22#ibcon#read 6, iclass 24, count 0 2006.173.22:21:35.22#ibcon#end of sib2, iclass 24, count 0 2006.173.22:21:35.22#ibcon#*mode == 0, iclass 24, count 0 2006.173.22:21:35.22#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.22:21:35.22#ibcon#[25=USB\r\n] 2006.173.22:21:35.22#ibcon#*before write, iclass 24, count 0 2006.173.22:21:35.22#ibcon#enter sib2, iclass 24, count 0 2006.173.22:21:35.22#ibcon#flushed, iclass 24, count 0 2006.173.22:21:35.22#ibcon#about to write, iclass 24, count 0 2006.173.22:21:35.22#ibcon#wrote, iclass 24, count 0 2006.173.22:21:35.22#ibcon#about to read 3, iclass 24, count 0 2006.173.22:21:35.25#ibcon#read 3, iclass 24, count 0 2006.173.22:21:35.25#ibcon#about to read 4, iclass 24, count 0 2006.173.22:21:35.25#ibcon#read 4, iclass 24, count 0 2006.173.22:21:35.25#ibcon#about to read 5, iclass 24, count 0 2006.173.22:21:35.25#ibcon#read 5, iclass 24, count 0 2006.173.22:21:35.25#ibcon#about to read 6, iclass 24, count 0 2006.173.22:21:35.25#ibcon#read 6, iclass 24, count 0 2006.173.22:21:35.25#ibcon#end of sib2, iclass 24, count 0 2006.173.22:21:35.25#ibcon#*after write, iclass 24, count 0 2006.173.22:21:35.25#ibcon#*before return 0, iclass 24, count 0 2006.173.22:21:35.25#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.22:21:35.25#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.22:21:35.25#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.22:21:35.25#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.22:21:35.25$vck44/valo=7,864.99 2006.173.22:21:35.25#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.22:21:35.25#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.22:21:35.25#ibcon#ireg 17 cls_cnt 0 2006.173.22:21:35.25#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.22:21:35.25#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.22:21:35.25#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.22:21:35.25#ibcon#enter wrdev, iclass 26, count 0 2006.173.22:21:35.25#ibcon#first serial, iclass 26, count 0 2006.173.22:21:35.25#ibcon#enter sib2, iclass 26, count 0 2006.173.22:21:35.25#ibcon#flushed, iclass 26, count 0 2006.173.22:21:35.25#ibcon#about to write, iclass 26, count 0 2006.173.22:21:35.25#ibcon#wrote, iclass 26, count 0 2006.173.22:21:35.25#ibcon#about to read 3, iclass 26, count 0 2006.173.22:21:35.27#ibcon#read 3, iclass 26, count 0 2006.173.22:21:35.27#ibcon#about to read 4, iclass 26, count 0 2006.173.22:21:35.27#ibcon#read 4, iclass 26, count 0 2006.173.22:21:35.27#ibcon#about to read 5, iclass 26, count 0 2006.173.22:21:35.27#ibcon#read 5, iclass 26, count 0 2006.173.22:21:35.27#ibcon#about to read 6, iclass 26, count 0 2006.173.22:21:35.27#ibcon#read 6, iclass 26, count 0 2006.173.22:21:35.27#ibcon#end of sib2, iclass 26, count 0 2006.173.22:21:35.27#ibcon#*mode == 0, iclass 26, count 0 2006.173.22:21:35.27#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.22:21:35.27#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.22:21:35.27#ibcon#*before write, iclass 26, count 0 2006.173.22:21:35.27#ibcon#enter sib2, iclass 26, count 0 2006.173.22:21:35.27#ibcon#flushed, iclass 26, count 0 2006.173.22:21:35.27#ibcon#about to write, iclass 26, count 0 2006.173.22:21:35.27#ibcon#wrote, iclass 26, count 0 2006.173.22:21:35.27#ibcon#about to read 3, iclass 26, count 0 2006.173.22:21:35.31#ibcon#read 3, iclass 26, count 0 2006.173.22:21:35.31#ibcon#about to read 4, iclass 26, count 0 2006.173.22:21:35.31#ibcon#read 4, iclass 26, count 0 2006.173.22:21:35.31#ibcon#about to read 5, iclass 26, count 0 2006.173.22:21:35.31#ibcon#read 5, iclass 26, count 0 2006.173.22:21:35.31#ibcon#about to read 6, iclass 26, count 0 2006.173.22:21:35.31#ibcon#read 6, iclass 26, count 0 2006.173.22:21:35.31#ibcon#end of sib2, iclass 26, count 0 2006.173.22:21:35.31#ibcon#*after write, iclass 26, count 0 2006.173.22:21:35.31#ibcon#*before return 0, iclass 26, count 0 2006.173.22:21:35.31#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.22:21:35.31#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.22:21:35.31#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.22:21:35.31#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.22:21:35.31$vck44/va=7,4 2006.173.22:21:35.31#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.22:21:35.31#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.22:21:35.31#ibcon#ireg 11 cls_cnt 2 2006.173.22:21:35.31#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.22:21:35.37#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.22:21:35.37#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.22:21:35.37#ibcon#enter wrdev, iclass 28, count 2 2006.173.22:21:35.37#ibcon#first serial, iclass 28, count 2 2006.173.22:21:35.37#ibcon#enter sib2, iclass 28, count 2 2006.173.22:21:35.37#ibcon#flushed, iclass 28, count 2 2006.173.22:21:35.37#ibcon#about to write, iclass 28, count 2 2006.173.22:21:35.37#ibcon#wrote, iclass 28, count 2 2006.173.22:21:35.37#ibcon#about to read 3, iclass 28, count 2 2006.173.22:21:35.39#ibcon#read 3, iclass 28, count 2 2006.173.22:21:35.39#ibcon#about to read 4, iclass 28, count 2 2006.173.22:21:35.39#ibcon#read 4, iclass 28, count 2 2006.173.22:21:35.39#ibcon#about to read 5, iclass 28, count 2 2006.173.22:21:35.39#ibcon#read 5, iclass 28, count 2 2006.173.22:21:35.39#ibcon#about to read 6, iclass 28, count 2 2006.173.22:21:35.39#ibcon#read 6, iclass 28, count 2 2006.173.22:21:35.39#ibcon#end of sib2, iclass 28, count 2 2006.173.22:21:35.39#ibcon#*mode == 0, iclass 28, count 2 2006.173.22:21:35.39#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.22:21:35.39#ibcon#[25=AT07-04\r\n] 2006.173.22:21:35.39#ibcon#*before write, iclass 28, count 2 2006.173.22:21:35.39#ibcon#enter sib2, iclass 28, count 2 2006.173.22:21:35.39#ibcon#flushed, iclass 28, count 2 2006.173.22:21:35.39#ibcon#about to write, iclass 28, count 2 2006.173.22:21:35.39#ibcon#wrote, iclass 28, count 2 2006.173.22:21:35.39#ibcon#about to read 3, iclass 28, count 2 2006.173.22:21:35.42#ibcon#read 3, iclass 28, count 2 2006.173.22:21:35.42#ibcon#about to read 4, iclass 28, count 2 2006.173.22:21:35.42#ibcon#read 4, iclass 28, count 2 2006.173.22:21:35.42#ibcon#about to read 5, iclass 28, count 2 2006.173.22:21:35.42#ibcon#read 5, iclass 28, count 2 2006.173.22:21:35.42#ibcon#about to read 6, iclass 28, count 2 2006.173.22:21:35.42#ibcon#read 6, iclass 28, count 2 2006.173.22:21:35.42#ibcon#end of sib2, iclass 28, count 2 2006.173.22:21:35.42#ibcon#*after write, iclass 28, count 2 2006.173.22:21:35.42#ibcon#*before return 0, iclass 28, count 2 2006.173.22:21:35.42#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.22:21:35.42#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.22:21:35.42#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.22:21:35.42#ibcon#ireg 7 cls_cnt 0 2006.173.22:21:35.42#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.22:21:35.54#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.22:21:35.54#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.22:21:35.54#ibcon#enter wrdev, iclass 28, count 0 2006.173.22:21:35.54#ibcon#first serial, iclass 28, count 0 2006.173.22:21:35.54#ibcon#enter sib2, iclass 28, count 0 2006.173.22:21:35.54#ibcon#flushed, iclass 28, count 0 2006.173.22:21:35.54#ibcon#about to write, iclass 28, count 0 2006.173.22:21:35.54#ibcon#wrote, iclass 28, count 0 2006.173.22:21:35.54#ibcon#about to read 3, iclass 28, count 0 2006.173.22:21:35.56#ibcon#read 3, iclass 28, count 0 2006.173.22:21:35.56#ibcon#about to read 4, iclass 28, count 0 2006.173.22:21:35.56#ibcon#read 4, iclass 28, count 0 2006.173.22:21:35.56#ibcon#about to read 5, iclass 28, count 0 2006.173.22:21:35.56#ibcon#read 5, iclass 28, count 0 2006.173.22:21:35.56#ibcon#about to read 6, iclass 28, count 0 2006.173.22:21:35.56#ibcon#read 6, iclass 28, count 0 2006.173.22:21:35.56#ibcon#end of sib2, iclass 28, count 0 2006.173.22:21:35.56#ibcon#*mode == 0, iclass 28, count 0 2006.173.22:21:35.56#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.22:21:35.56#ibcon#[25=USB\r\n] 2006.173.22:21:35.56#ibcon#*before write, iclass 28, count 0 2006.173.22:21:35.56#ibcon#enter sib2, iclass 28, count 0 2006.173.22:21:35.56#ibcon#flushed, iclass 28, count 0 2006.173.22:21:35.56#ibcon#about to write, iclass 28, count 0 2006.173.22:21:35.56#ibcon#wrote, iclass 28, count 0 2006.173.22:21:35.56#ibcon#about to read 3, iclass 28, count 0 2006.173.22:21:35.59#ibcon#read 3, iclass 28, count 0 2006.173.22:21:35.59#ibcon#about to read 4, iclass 28, count 0 2006.173.22:21:35.59#ibcon#read 4, iclass 28, count 0 2006.173.22:21:35.59#ibcon#about to read 5, iclass 28, count 0 2006.173.22:21:35.59#ibcon#read 5, iclass 28, count 0 2006.173.22:21:35.59#ibcon#about to read 6, iclass 28, count 0 2006.173.22:21:35.59#ibcon#read 6, iclass 28, count 0 2006.173.22:21:35.59#ibcon#end of sib2, iclass 28, count 0 2006.173.22:21:35.59#ibcon#*after write, iclass 28, count 0 2006.173.22:21:35.59#ibcon#*before return 0, iclass 28, count 0 2006.173.22:21:35.59#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.22:21:35.59#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.22:21:35.59#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.22:21:35.59#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.22:21:35.59$vck44/valo=8,884.99 2006.173.22:21:35.59#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.22:21:35.59#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.22:21:35.59#ibcon#ireg 17 cls_cnt 0 2006.173.22:21:35.59#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.22:21:35.59#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.22:21:35.59#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.22:21:35.59#ibcon#enter wrdev, iclass 30, count 0 2006.173.22:21:35.59#ibcon#first serial, iclass 30, count 0 2006.173.22:21:35.59#ibcon#enter sib2, iclass 30, count 0 2006.173.22:21:35.59#ibcon#flushed, iclass 30, count 0 2006.173.22:21:35.59#ibcon#about to write, iclass 30, count 0 2006.173.22:21:35.59#ibcon#wrote, iclass 30, count 0 2006.173.22:21:35.59#ibcon#about to read 3, iclass 30, count 0 2006.173.22:21:35.61#ibcon#read 3, iclass 30, count 0 2006.173.22:21:35.61#ibcon#about to read 4, iclass 30, count 0 2006.173.22:21:35.61#ibcon#read 4, iclass 30, count 0 2006.173.22:21:35.61#ibcon#about to read 5, iclass 30, count 0 2006.173.22:21:35.61#ibcon#read 5, iclass 30, count 0 2006.173.22:21:35.61#ibcon#about to read 6, iclass 30, count 0 2006.173.22:21:35.61#ibcon#read 6, iclass 30, count 0 2006.173.22:21:35.61#ibcon#end of sib2, iclass 30, count 0 2006.173.22:21:35.61#ibcon#*mode == 0, iclass 30, count 0 2006.173.22:21:35.61#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.22:21:35.61#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.22:21:35.61#ibcon#*before write, iclass 30, count 0 2006.173.22:21:35.61#ibcon#enter sib2, iclass 30, count 0 2006.173.22:21:35.61#ibcon#flushed, iclass 30, count 0 2006.173.22:21:35.61#ibcon#about to write, iclass 30, count 0 2006.173.22:21:35.61#ibcon#wrote, iclass 30, count 0 2006.173.22:21:35.61#ibcon#about to read 3, iclass 30, count 0 2006.173.22:21:35.65#ibcon#read 3, iclass 30, count 0 2006.173.22:21:35.65#ibcon#about to read 4, iclass 30, count 0 2006.173.22:21:35.65#ibcon#read 4, iclass 30, count 0 2006.173.22:21:35.65#ibcon#about to read 5, iclass 30, count 0 2006.173.22:21:35.65#ibcon#read 5, iclass 30, count 0 2006.173.22:21:35.65#ibcon#about to read 6, iclass 30, count 0 2006.173.22:21:35.65#ibcon#read 6, iclass 30, count 0 2006.173.22:21:35.65#ibcon#end of sib2, iclass 30, count 0 2006.173.22:21:35.65#ibcon#*after write, iclass 30, count 0 2006.173.22:21:35.65#ibcon#*before return 0, iclass 30, count 0 2006.173.22:21:35.65#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.22:21:35.65#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.22:21:35.65#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.22:21:35.65#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.22:21:35.65$vck44/va=8,4 2006.173.22:21:35.65#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.173.22:21:35.65#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.173.22:21:35.65#ibcon#ireg 11 cls_cnt 2 2006.173.22:21:35.65#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.22:21:35.71#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.22:21:35.71#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.22:21:35.71#ibcon#enter wrdev, iclass 32, count 2 2006.173.22:21:35.71#ibcon#first serial, iclass 32, count 2 2006.173.22:21:35.71#ibcon#enter sib2, iclass 32, count 2 2006.173.22:21:35.71#ibcon#flushed, iclass 32, count 2 2006.173.22:21:35.71#ibcon#about to write, iclass 32, count 2 2006.173.22:21:35.71#ibcon#wrote, iclass 32, count 2 2006.173.22:21:35.71#ibcon#about to read 3, iclass 32, count 2 2006.173.22:21:35.73#ibcon#read 3, iclass 32, count 2 2006.173.22:21:35.73#ibcon#about to read 4, iclass 32, count 2 2006.173.22:21:35.73#ibcon#read 4, iclass 32, count 2 2006.173.22:21:35.73#ibcon#about to read 5, iclass 32, count 2 2006.173.22:21:35.73#ibcon#read 5, iclass 32, count 2 2006.173.22:21:35.73#ibcon#about to read 6, iclass 32, count 2 2006.173.22:21:35.73#ibcon#read 6, iclass 32, count 2 2006.173.22:21:35.73#ibcon#end of sib2, iclass 32, count 2 2006.173.22:21:35.73#ibcon#*mode == 0, iclass 32, count 2 2006.173.22:21:35.73#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.173.22:21:35.73#ibcon#[25=AT08-04\r\n] 2006.173.22:21:35.73#ibcon#*before write, iclass 32, count 2 2006.173.22:21:35.73#ibcon#enter sib2, iclass 32, count 2 2006.173.22:21:35.73#ibcon#flushed, iclass 32, count 2 2006.173.22:21:35.73#ibcon#about to write, iclass 32, count 2 2006.173.22:21:35.73#ibcon#wrote, iclass 32, count 2 2006.173.22:21:35.73#ibcon#about to read 3, iclass 32, count 2 2006.173.22:21:35.76#ibcon#read 3, iclass 32, count 2 2006.173.22:21:35.76#ibcon#about to read 4, iclass 32, count 2 2006.173.22:21:35.76#ibcon#read 4, iclass 32, count 2 2006.173.22:21:35.76#ibcon#about to read 5, iclass 32, count 2 2006.173.22:21:35.76#ibcon#read 5, iclass 32, count 2 2006.173.22:21:35.76#ibcon#about to read 6, iclass 32, count 2 2006.173.22:21:35.76#ibcon#read 6, iclass 32, count 2 2006.173.22:21:35.76#ibcon#end of sib2, iclass 32, count 2 2006.173.22:21:35.76#ibcon#*after write, iclass 32, count 2 2006.173.22:21:35.76#ibcon#*before return 0, iclass 32, count 2 2006.173.22:21:35.76#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.22:21:35.76#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.173.22:21:35.76#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.173.22:21:35.76#ibcon#ireg 7 cls_cnt 0 2006.173.22:21:35.76#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.22:21:35.88#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.22:21:35.88#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.22:21:35.88#ibcon#enter wrdev, iclass 32, count 0 2006.173.22:21:35.88#ibcon#first serial, iclass 32, count 0 2006.173.22:21:35.88#ibcon#enter sib2, iclass 32, count 0 2006.173.22:21:35.88#ibcon#flushed, iclass 32, count 0 2006.173.22:21:35.88#ibcon#about to write, iclass 32, count 0 2006.173.22:21:35.88#ibcon#wrote, iclass 32, count 0 2006.173.22:21:35.88#ibcon#about to read 3, iclass 32, count 0 2006.173.22:21:35.90#ibcon#read 3, iclass 32, count 0 2006.173.22:21:35.90#ibcon#about to read 4, iclass 32, count 0 2006.173.22:21:35.90#ibcon#read 4, iclass 32, count 0 2006.173.22:21:35.90#ibcon#about to read 5, iclass 32, count 0 2006.173.22:21:35.90#ibcon#read 5, iclass 32, count 0 2006.173.22:21:35.90#ibcon#about to read 6, iclass 32, count 0 2006.173.22:21:35.90#ibcon#read 6, iclass 32, count 0 2006.173.22:21:35.90#ibcon#end of sib2, iclass 32, count 0 2006.173.22:21:35.90#ibcon#*mode == 0, iclass 32, count 0 2006.173.22:21:35.90#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.22:21:35.90#ibcon#[25=USB\r\n] 2006.173.22:21:35.90#ibcon#*before write, iclass 32, count 0 2006.173.22:21:35.90#ibcon#enter sib2, iclass 32, count 0 2006.173.22:21:35.90#ibcon#flushed, iclass 32, count 0 2006.173.22:21:35.90#ibcon#about to write, iclass 32, count 0 2006.173.22:21:35.90#ibcon#wrote, iclass 32, count 0 2006.173.22:21:35.90#ibcon#about to read 3, iclass 32, count 0 2006.173.22:21:35.93#ibcon#read 3, iclass 32, count 0 2006.173.22:21:35.93#ibcon#about to read 4, iclass 32, count 0 2006.173.22:21:35.93#ibcon#read 4, iclass 32, count 0 2006.173.22:21:35.93#ibcon#about to read 5, iclass 32, count 0 2006.173.22:21:35.93#ibcon#read 5, iclass 32, count 0 2006.173.22:21:35.93#ibcon#about to read 6, iclass 32, count 0 2006.173.22:21:35.93#ibcon#read 6, iclass 32, count 0 2006.173.22:21:35.93#ibcon#end of sib2, iclass 32, count 0 2006.173.22:21:35.93#ibcon#*after write, iclass 32, count 0 2006.173.22:21:35.93#ibcon#*before return 0, iclass 32, count 0 2006.173.22:21:35.93#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.22:21:35.93#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.173.22:21:35.93#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.22:21:35.93#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.22:21:35.93$vck44/vblo=1,629.99 2006.173.22:21:35.93#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.22:21:35.93#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.22:21:35.93#ibcon#ireg 17 cls_cnt 0 2006.173.22:21:35.93#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.22:21:35.93#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.22:21:35.93#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.22:21:35.93#ibcon#enter wrdev, iclass 34, count 0 2006.173.22:21:35.93#ibcon#first serial, iclass 34, count 0 2006.173.22:21:35.93#ibcon#enter sib2, iclass 34, count 0 2006.173.22:21:35.93#ibcon#flushed, iclass 34, count 0 2006.173.22:21:35.93#ibcon#about to write, iclass 34, count 0 2006.173.22:21:35.93#ibcon#wrote, iclass 34, count 0 2006.173.22:21:35.93#ibcon#about to read 3, iclass 34, count 0 2006.173.22:21:35.95#ibcon#read 3, iclass 34, count 0 2006.173.22:21:35.95#ibcon#about to read 4, iclass 34, count 0 2006.173.22:21:35.95#ibcon#read 4, iclass 34, count 0 2006.173.22:21:35.95#ibcon#about to read 5, iclass 34, count 0 2006.173.22:21:35.95#ibcon#read 5, iclass 34, count 0 2006.173.22:21:35.95#ibcon#about to read 6, iclass 34, count 0 2006.173.22:21:35.95#ibcon#read 6, iclass 34, count 0 2006.173.22:21:35.95#ibcon#end of sib2, iclass 34, count 0 2006.173.22:21:35.95#ibcon#*mode == 0, iclass 34, count 0 2006.173.22:21:35.95#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.22:21:35.95#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.22:21:35.95#ibcon#*before write, iclass 34, count 0 2006.173.22:21:35.95#ibcon#enter sib2, iclass 34, count 0 2006.173.22:21:35.95#ibcon#flushed, iclass 34, count 0 2006.173.22:21:35.95#ibcon#about to write, iclass 34, count 0 2006.173.22:21:35.95#ibcon#wrote, iclass 34, count 0 2006.173.22:21:35.95#ibcon#about to read 3, iclass 34, count 0 2006.173.22:21:35.99#ibcon#read 3, iclass 34, count 0 2006.173.22:21:35.99#ibcon#about to read 4, iclass 34, count 0 2006.173.22:21:35.99#ibcon#read 4, iclass 34, count 0 2006.173.22:21:35.99#ibcon#about to read 5, iclass 34, count 0 2006.173.22:21:35.99#ibcon#read 5, iclass 34, count 0 2006.173.22:21:35.99#ibcon#about to read 6, iclass 34, count 0 2006.173.22:21:35.99#ibcon#read 6, iclass 34, count 0 2006.173.22:21:35.99#ibcon#end of sib2, iclass 34, count 0 2006.173.22:21:35.99#ibcon#*after write, iclass 34, count 0 2006.173.22:21:35.99#ibcon#*before return 0, iclass 34, count 0 2006.173.22:21:35.99#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.22:21:35.99#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.22:21:35.99#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.22:21:35.99#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.22:21:35.99$vck44/vb=1,4 2006.173.22:21:35.99#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.22:21:35.99#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.22:21:35.99#ibcon#ireg 11 cls_cnt 2 2006.173.22:21:35.99#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.22:21:35.99#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.22:21:35.99#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.22:21:35.99#ibcon#enter wrdev, iclass 36, count 2 2006.173.22:21:35.99#ibcon#first serial, iclass 36, count 2 2006.173.22:21:35.99#ibcon#enter sib2, iclass 36, count 2 2006.173.22:21:35.99#ibcon#flushed, iclass 36, count 2 2006.173.22:21:35.99#ibcon#about to write, iclass 36, count 2 2006.173.22:21:35.99#ibcon#wrote, iclass 36, count 2 2006.173.22:21:35.99#ibcon#about to read 3, iclass 36, count 2 2006.173.22:21:36.01#ibcon#read 3, iclass 36, count 2 2006.173.22:21:36.01#ibcon#about to read 4, iclass 36, count 2 2006.173.22:21:36.01#ibcon#read 4, iclass 36, count 2 2006.173.22:21:36.01#ibcon#about to read 5, iclass 36, count 2 2006.173.22:21:36.01#ibcon#read 5, iclass 36, count 2 2006.173.22:21:36.01#ibcon#about to read 6, iclass 36, count 2 2006.173.22:21:36.01#ibcon#read 6, iclass 36, count 2 2006.173.22:21:36.01#ibcon#end of sib2, iclass 36, count 2 2006.173.22:21:36.01#ibcon#*mode == 0, iclass 36, count 2 2006.173.22:21:36.01#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.22:21:36.01#ibcon#[27=AT01-04\r\n] 2006.173.22:21:36.01#ibcon#*before write, iclass 36, count 2 2006.173.22:21:36.01#ibcon#enter sib2, iclass 36, count 2 2006.173.22:21:36.01#ibcon#flushed, iclass 36, count 2 2006.173.22:21:36.01#ibcon#about to write, iclass 36, count 2 2006.173.22:21:36.01#ibcon#wrote, iclass 36, count 2 2006.173.22:21:36.01#ibcon#about to read 3, iclass 36, count 2 2006.173.22:21:36.04#ibcon#read 3, iclass 36, count 2 2006.173.22:21:36.04#ibcon#about to read 4, iclass 36, count 2 2006.173.22:21:36.04#ibcon#read 4, iclass 36, count 2 2006.173.22:21:36.04#ibcon#about to read 5, iclass 36, count 2 2006.173.22:21:36.04#ibcon#read 5, iclass 36, count 2 2006.173.22:21:36.04#ibcon#about to read 6, iclass 36, count 2 2006.173.22:21:36.04#ibcon#read 6, iclass 36, count 2 2006.173.22:21:36.04#ibcon#end of sib2, iclass 36, count 2 2006.173.22:21:36.04#ibcon#*after write, iclass 36, count 2 2006.173.22:21:36.04#ibcon#*before return 0, iclass 36, count 2 2006.173.22:21:36.04#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.22:21:36.04#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.22:21:36.04#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.22:21:36.04#ibcon#ireg 7 cls_cnt 0 2006.173.22:21:36.04#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.22:21:36.16#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.22:21:36.16#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.22:21:36.16#ibcon#enter wrdev, iclass 36, count 0 2006.173.22:21:36.16#ibcon#first serial, iclass 36, count 0 2006.173.22:21:36.16#ibcon#enter sib2, iclass 36, count 0 2006.173.22:21:36.16#ibcon#flushed, iclass 36, count 0 2006.173.22:21:36.16#ibcon#about to write, iclass 36, count 0 2006.173.22:21:36.16#ibcon#wrote, iclass 36, count 0 2006.173.22:21:36.16#ibcon#about to read 3, iclass 36, count 0 2006.173.22:21:36.18#ibcon#read 3, iclass 36, count 0 2006.173.22:21:36.18#ibcon#about to read 4, iclass 36, count 0 2006.173.22:21:36.18#ibcon#read 4, iclass 36, count 0 2006.173.22:21:36.18#ibcon#about to read 5, iclass 36, count 0 2006.173.22:21:36.18#ibcon#read 5, iclass 36, count 0 2006.173.22:21:36.18#ibcon#about to read 6, iclass 36, count 0 2006.173.22:21:36.18#ibcon#read 6, iclass 36, count 0 2006.173.22:21:36.18#ibcon#end of sib2, iclass 36, count 0 2006.173.22:21:36.18#ibcon#*mode == 0, iclass 36, count 0 2006.173.22:21:36.18#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.22:21:36.18#ibcon#[27=USB\r\n] 2006.173.22:21:36.18#ibcon#*before write, iclass 36, count 0 2006.173.22:21:36.18#ibcon#enter sib2, iclass 36, count 0 2006.173.22:21:36.18#ibcon#flushed, iclass 36, count 0 2006.173.22:21:36.18#ibcon#about to write, iclass 36, count 0 2006.173.22:21:36.18#ibcon#wrote, iclass 36, count 0 2006.173.22:21:36.18#ibcon#about to read 3, iclass 36, count 0 2006.173.22:21:36.21#ibcon#read 3, iclass 36, count 0 2006.173.22:21:36.21#ibcon#about to read 4, iclass 36, count 0 2006.173.22:21:36.21#ibcon#read 4, iclass 36, count 0 2006.173.22:21:36.21#ibcon#about to read 5, iclass 36, count 0 2006.173.22:21:36.21#ibcon#read 5, iclass 36, count 0 2006.173.22:21:36.21#ibcon#about to read 6, iclass 36, count 0 2006.173.22:21:36.21#ibcon#read 6, iclass 36, count 0 2006.173.22:21:36.21#ibcon#end of sib2, iclass 36, count 0 2006.173.22:21:36.21#ibcon#*after write, iclass 36, count 0 2006.173.22:21:36.21#ibcon#*before return 0, iclass 36, count 0 2006.173.22:21:36.21#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.22:21:36.21#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.22:21:36.21#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.22:21:36.21#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.22:21:36.21$vck44/vblo=2,634.99 2006.173.22:21:36.21#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.22:21:36.21#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.22:21:36.21#ibcon#ireg 17 cls_cnt 0 2006.173.22:21:36.21#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.22:21:36.21#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.22:21:36.21#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.22:21:36.21#ibcon#enter wrdev, iclass 38, count 0 2006.173.22:21:36.21#ibcon#first serial, iclass 38, count 0 2006.173.22:21:36.21#ibcon#enter sib2, iclass 38, count 0 2006.173.22:21:36.21#ibcon#flushed, iclass 38, count 0 2006.173.22:21:36.21#ibcon#about to write, iclass 38, count 0 2006.173.22:21:36.21#ibcon#wrote, iclass 38, count 0 2006.173.22:21:36.21#ibcon#about to read 3, iclass 38, count 0 2006.173.22:21:36.23#ibcon#read 3, iclass 38, count 0 2006.173.22:21:36.23#ibcon#about to read 4, iclass 38, count 0 2006.173.22:21:36.23#ibcon#read 4, iclass 38, count 0 2006.173.22:21:36.23#ibcon#about to read 5, iclass 38, count 0 2006.173.22:21:36.23#ibcon#read 5, iclass 38, count 0 2006.173.22:21:36.23#ibcon#about to read 6, iclass 38, count 0 2006.173.22:21:36.23#ibcon#read 6, iclass 38, count 0 2006.173.22:21:36.23#ibcon#end of sib2, iclass 38, count 0 2006.173.22:21:36.23#ibcon#*mode == 0, iclass 38, count 0 2006.173.22:21:36.23#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.22:21:36.23#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.22:21:36.23#ibcon#*before write, iclass 38, count 0 2006.173.22:21:36.23#ibcon#enter sib2, iclass 38, count 0 2006.173.22:21:36.23#ibcon#flushed, iclass 38, count 0 2006.173.22:21:36.23#ibcon#about to write, iclass 38, count 0 2006.173.22:21:36.23#ibcon#wrote, iclass 38, count 0 2006.173.22:21:36.23#ibcon#about to read 3, iclass 38, count 0 2006.173.22:21:36.27#ibcon#read 3, iclass 38, count 0 2006.173.22:21:36.27#ibcon#about to read 4, iclass 38, count 0 2006.173.22:21:36.27#ibcon#read 4, iclass 38, count 0 2006.173.22:21:36.27#ibcon#about to read 5, iclass 38, count 0 2006.173.22:21:36.27#ibcon#read 5, iclass 38, count 0 2006.173.22:21:36.27#ibcon#about to read 6, iclass 38, count 0 2006.173.22:21:36.27#ibcon#read 6, iclass 38, count 0 2006.173.22:21:36.27#ibcon#end of sib2, iclass 38, count 0 2006.173.22:21:36.27#ibcon#*after write, iclass 38, count 0 2006.173.22:21:36.27#ibcon#*before return 0, iclass 38, count 0 2006.173.22:21:36.27#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.22:21:36.27#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.22:21:36.27#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.22:21:36.27#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.22:21:36.27$vck44/vb=2,4 2006.173.22:21:36.27#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.22:21:36.27#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.22:21:36.27#ibcon#ireg 11 cls_cnt 2 2006.173.22:21:36.27#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.22:21:36.33#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.22:21:36.33#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.22:21:36.33#ibcon#enter wrdev, iclass 40, count 2 2006.173.22:21:36.33#ibcon#first serial, iclass 40, count 2 2006.173.22:21:36.33#ibcon#enter sib2, iclass 40, count 2 2006.173.22:21:36.33#ibcon#flushed, iclass 40, count 2 2006.173.22:21:36.33#ibcon#about to write, iclass 40, count 2 2006.173.22:21:36.33#ibcon#wrote, iclass 40, count 2 2006.173.22:21:36.33#ibcon#about to read 3, iclass 40, count 2 2006.173.22:21:36.35#ibcon#read 3, iclass 40, count 2 2006.173.22:21:36.35#ibcon#about to read 4, iclass 40, count 2 2006.173.22:21:36.35#ibcon#read 4, iclass 40, count 2 2006.173.22:21:36.35#ibcon#about to read 5, iclass 40, count 2 2006.173.22:21:36.35#ibcon#read 5, iclass 40, count 2 2006.173.22:21:36.35#ibcon#about to read 6, iclass 40, count 2 2006.173.22:21:36.35#ibcon#read 6, iclass 40, count 2 2006.173.22:21:36.35#ibcon#end of sib2, iclass 40, count 2 2006.173.22:21:36.35#ibcon#*mode == 0, iclass 40, count 2 2006.173.22:21:36.35#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.22:21:36.35#ibcon#[27=AT02-04\r\n] 2006.173.22:21:36.35#ibcon#*before write, iclass 40, count 2 2006.173.22:21:36.35#ibcon#enter sib2, iclass 40, count 2 2006.173.22:21:36.35#ibcon#flushed, iclass 40, count 2 2006.173.22:21:36.35#ibcon#about to write, iclass 40, count 2 2006.173.22:21:36.35#ibcon#wrote, iclass 40, count 2 2006.173.22:21:36.35#ibcon#about to read 3, iclass 40, count 2 2006.173.22:21:36.38#ibcon#read 3, iclass 40, count 2 2006.173.22:21:36.38#ibcon#about to read 4, iclass 40, count 2 2006.173.22:21:36.38#ibcon#read 4, iclass 40, count 2 2006.173.22:21:36.38#ibcon#about to read 5, iclass 40, count 2 2006.173.22:21:36.38#ibcon#read 5, iclass 40, count 2 2006.173.22:21:36.38#ibcon#about to read 6, iclass 40, count 2 2006.173.22:21:36.38#ibcon#read 6, iclass 40, count 2 2006.173.22:21:36.38#ibcon#end of sib2, iclass 40, count 2 2006.173.22:21:36.38#ibcon#*after write, iclass 40, count 2 2006.173.22:21:36.38#ibcon#*before return 0, iclass 40, count 2 2006.173.22:21:36.38#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.22:21:36.38#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.22:21:36.38#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.22:21:36.38#ibcon#ireg 7 cls_cnt 0 2006.173.22:21:36.38#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.22:21:36.50#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.22:21:36.50#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.22:21:36.50#ibcon#enter wrdev, iclass 40, count 0 2006.173.22:21:36.50#ibcon#first serial, iclass 40, count 0 2006.173.22:21:36.50#ibcon#enter sib2, iclass 40, count 0 2006.173.22:21:36.50#ibcon#flushed, iclass 40, count 0 2006.173.22:21:36.50#ibcon#about to write, iclass 40, count 0 2006.173.22:21:36.50#ibcon#wrote, iclass 40, count 0 2006.173.22:21:36.50#ibcon#about to read 3, iclass 40, count 0 2006.173.22:21:36.52#ibcon#read 3, iclass 40, count 0 2006.173.22:21:36.52#ibcon#about to read 4, iclass 40, count 0 2006.173.22:21:36.52#ibcon#read 4, iclass 40, count 0 2006.173.22:21:36.52#ibcon#about to read 5, iclass 40, count 0 2006.173.22:21:36.52#ibcon#read 5, iclass 40, count 0 2006.173.22:21:36.52#ibcon#about to read 6, iclass 40, count 0 2006.173.22:21:36.52#ibcon#read 6, iclass 40, count 0 2006.173.22:21:36.52#ibcon#end of sib2, iclass 40, count 0 2006.173.22:21:36.52#ibcon#*mode == 0, iclass 40, count 0 2006.173.22:21:36.52#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.22:21:36.52#ibcon#[27=USB\r\n] 2006.173.22:21:36.52#ibcon#*before write, iclass 40, count 0 2006.173.22:21:36.52#ibcon#enter sib2, iclass 40, count 0 2006.173.22:21:36.52#ibcon#flushed, iclass 40, count 0 2006.173.22:21:36.52#ibcon#about to write, iclass 40, count 0 2006.173.22:21:36.52#ibcon#wrote, iclass 40, count 0 2006.173.22:21:36.52#ibcon#about to read 3, iclass 40, count 0 2006.173.22:21:36.55#ibcon#read 3, iclass 40, count 0 2006.173.22:21:36.55#ibcon#about to read 4, iclass 40, count 0 2006.173.22:21:36.55#ibcon#read 4, iclass 40, count 0 2006.173.22:21:36.55#ibcon#about to read 5, iclass 40, count 0 2006.173.22:21:36.55#ibcon#read 5, iclass 40, count 0 2006.173.22:21:36.55#ibcon#about to read 6, iclass 40, count 0 2006.173.22:21:36.55#ibcon#read 6, iclass 40, count 0 2006.173.22:21:36.55#ibcon#end of sib2, iclass 40, count 0 2006.173.22:21:36.55#ibcon#*after write, iclass 40, count 0 2006.173.22:21:36.55#ibcon#*before return 0, iclass 40, count 0 2006.173.22:21:36.55#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.22:21:36.55#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.22:21:36.55#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.22:21:36.55#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.22:21:36.55$vck44/vblo=3,649.99 2006.173.22:21:36.55#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.22:21:36.55#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.22:21:36.55#ibcon#ireg 17 cls_cnt 0 2006.173.22:21:36.55#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.22:21:36.55#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.22:21:36.55#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.22:21:36.55#ibcon#enter wrdev, iclass 4, count 0 2006.173.22:21:36.55#ibcon#first serial, iclass 4, count 0 2006.173.22:21:36.55#ibcon#enter sib2, iclass 4, count 0 2006.173.22:21:36.55#ibcon#flushed, iclass 4, count 0 2006.173.22:21:36.55#ibcon#about to write, iclass 4, count 0 2006.173.22:21:36.55#ibcon#wrote, iclass 4, count 0 2006.173.22:21:36.55#ibcon#about to read 3, iclass 4, count 0 2006.173.22:21:36.57#ibcon#read 3, iclass 4, count 0 2006.173.22:21:36.57#ibcon#about to read 4, iclass 4, count 0 2006.173.22:21:36.57#ibcon#read 4, iclass 4, count 0 2006.173.22:21:36.57#ibcon#about to read 5, iclass 4, count 0 2006.173.22:21:36.57#ibcon#read 5, iclass 4, count 0 2006.173.22:21:36.57#ibcon#about to read 6, iclass 4, count 0 2006.173.22:21:36.57#ibcon#read 6, iclass 4, count 0 2006.173.22:21:36.57#ibcon#end of sib2, iclass 4, count 0 2006.173.22:21:36.57#ibcon#*mode == 0, iclass 4, count 0 2006.173.22:21:36.57#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.22:21:36.57#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.22:21:36.57#ibcon#*before write, iclass 4, count 0 2006.173.22:21:36.57#ibcon#enter sib2, iclass 4, count 0 2006.173.22:21:36.57#ibcon#flushed, iclass 4, count 0 2006.173.22:21:36.57#ibcon#about to write, iclass 4, count 0 2006.173.22:21:36.57#ibcon#wrote, iclass 4, count 0 2006.173.22:21:36.57#ibcon#about to read 3, iclass 4, count 0 2006.173.22:21:36.61#ibcon#read 3, iclass 4, count 0 2006.173.22:21:36.61#ibcon#about to read 4, iclass 4, count 0 2006.173.22:21:36.61#ibcon#read 4, iclass 4, count 0 2006.173.22:21:36.61#ibcon#about to read 5, iclass 4, count 0 2006.173.22:21:36.61#ibcon#read 5, iclass 4, count 0 2006.173.22:21:36.61#ibcon#about to read 6, iclass 4, count 0 2006.173.22:21:36.61#ibcon#read 6, iclass 4, count 0 2006.173.22:21:36.61#ibcon#end of sib2, iclass 4, count 0 2006.173.22:21:36.61#ibcon#*after write, iclass 4, count 0 2006.173.22:21:36.61#ibcon#*before return 0, iclass 4, count 0 2006.173.22:21:36.61#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.22:21:36.61#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.22:21:36.61#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.22:21:36.61#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.22:21:36.61$vck44/vb=3,4 2006.173.22:21:36.61#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.22:21:36.61#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.22:21:36.61#ibcon#ireg 11 cls_cnt 2 2006.173.22:21:36.61#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.22:21:36.67#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.22:21:36.67#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.22:21:36.67#ibcon#enter wrdev, iclass 6, count 2 2006.173.22:21:36.67#ibcon#first serial, iclass 6, count 2 2006.173.22:21:36.67#ibcon#enter sib2, iclass 6, count 2 2006.173.22:21:36.67#ibcon#flushed, iclass 6, count 2 2006.173.22:21:36.67#ibcon#about to write, iclass 6, count 2 2006.173.22:21:36.67#ibcon#wrote, iclass 6, count 2 2006.173.22:21:36.67#ibcon#about to read 3, iclass 6, count 2 2006.173.22:21:36.69#ibcon#read 3, iclass 6, count 2 2006.173.22:21:36.69#ibcon#about to read 4, iclass 6, count 2 2006.173.22:21:36.69#ibcon#read 4, iclass 6, count 2 2006.173.22:21:36.69#ibcon#about to read 5, iclass 6, count 2 2006.173.22:21:36.69#ibcon#read 5, iclass 6, count 2 2006.173.22:21:36.69#ibcon#about to read 6, iclass 6, count 2 2006.173.22:21:36.69#ibcon#read 6, iclass 6, count 2 2006.173.22:21:36.69#ibcon#end of sib2, iclass 6, count 2 2006.173.22:21:36.69#ibcon#*mode == 0, iclass 6, count 2 2006.173.22:21:36.69#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.22:21:36.69#ibcon#[27=AT03-04\r\n] 2006.173.22:21:36.69#ibcon#*before write, iclass 6, count 2 2006.173.22:21:36.69#ibcon#enter sib2, iclass 6, count 2 2006.173.22:21:36.69#ibcon#flushed, iclass 6, count 2 2006.173.22:21:36.69#ibcon#about to write, iclass 6, count 2 2006.173.22:21:36.69#ibcon#wrote, iclass 6, count 2 2006.173.22:21:36.69#ibcon#about to read 3, iclass 6, count 2 2006.173.22:21:36.72#ibcon#read 3, iclass 6, count 2 2006.173.22:21:36.72#ibcon#about to read 4, iclass 6, count 2 2006.173.22:21:36.72#ibcon#read 4, iclass 6, count 2 2006.173.22:21:36.72#ibcon#about to read 5, iclass 6, count 2 2006.173.22:21:36.72#ibcon#read 5, iclass 6, count 2 2006.173.22:21:36.72#ibcon#about to read 6, iclass 6, count 2 2006.173.22:21:36.72#ibcon#read 6, iclass 6, count 2 2006.173.22:21:36.72#ibcon#end of sib2, iclass 6, count 2 2006.173.22:21:36.72#ibcon#*after write, iclass 6, count 2 2006.173.22:21:36.72#ibcon#*before return 0, iclass 6, count 2 2006.173.22:21:36.72#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.22:21:36.72#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.22:21:36.72#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.22:21:36.72#ibcon#ireg 7 cls_cnt 0 2006.173.22:21:36.72#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.22:21:36.84#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.22:21:36.84#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.22:21:36.84#ibcon#enter wrdev, iclass 6, count 0 2006.173.22:21:36.84#ibcon#first serial, iclass 6, count 0 2006.173.22:21:36.84#ibcon#enter sib2, iclass 6, count 0 2006.173.22:21:36.84#ibcon#flushed, iclass 6, count 0 2006.173.22:21:36.84#ibcon#about to write, iclass 6, count 0 2006.173.22:21:36.84#ibcon#wrote, iclass 6, count 0 2006.173.22:21:36.84#ibcon#about to read 3, iclass 6, count 0 2006.173.22:21:36.86#ibcon#read 3, iclass 6, count 0 2006.173.22:21:36.86#ibcon#about to read 4, iclass 6, count 0 2006.173.22:21:36.86#ibcon#read 4, iclass 6, count 0 2006.173.22:21:36.86#ibcon#about to read 5, iclass 6, count 0 2006.173.22:21:36.86#ibcon#read 5, iclass 6, count 0 2006.173.22:21:36.86#ibcon#about to read 6, iclass 6, count 0 2006.173.22:21:36.86#ibcon#read 6, iclass 6, count 0 2006.173.22:21:36.86#ibcon#end of sib2, iclass 6, count 0 2006.173.22:21:36.86#ibcon#*mode == 0, iclass 6, count 0 2006.173.22:21:36.86#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.22:21:36.86#ibcon#[27=USB\r\n] 2006.173.22:21:36.86#ibcon#*before write, iclass 6, count 0 2006.173.22:21:36.86#ibcon#enter sib2, iclass 6, count 0 2006.173.22:21:36.86#ibcon#flushed, iclass 6, count 0 2006.173.22:21:36.86#ibcon#about to write, iclass 6, count 0 2006.173.22:21:36.86#ibcon#wrote, iclass 6, count 0 2006.173.22:21:36.86#ibcon#about to read 3, iclass 6, count 0 2006.173.22:21:36.89#ibcon#read 3, iclass 6, count 0 2006.173.22:21:36.89#ibcon#about to read 4, iclass 6, count 0 2006.173.22:21:36.89#ibcon#read 4, iclass 6, count 0 2006.173.22:21:36.89#ibcon#about to read 5, iclass 6, count 0 2006.173.22:21:36.89#ibcon#read 5, iclass 6, count 0 2006.173.22:21:36.89#ibcon#about to read 6, iclass 6, count 0 2006.173.22:21:36.89#ibcon#read 6, iclass 6, count 0 2006.173.22:21:36.89#ibcon#end of sib2, iclass 6, count 0 2006.173.22:21:36.89#ibcon#*after write, iclass 6, count 0 2006.173.22:21:36.89#ibcon#*before return 0, iclass 6, count 0 2006.173.22:21:36.89#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.22:21:36.89#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.22:21:36.89#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.22:21:36.89#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.22:21:36.89$vck44/vblo=4,679.99 2006.173.22:21:36.89#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.22:21:36.89#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.22:21:36.89#ibcon#ireg 17 cls_cnt 0 2006.173.22:21:36.89#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.22:21:36.89#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.22:21:36.89#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.22:21:36.89#ibcon#enter wrdev, iclass 10, count 0 2006.173.22:21:36.89#ibcon#first serial, iclass 10, count 0 2006.173.22:21:36.89#ibcon#enter sib2, iclass 10, count 0 2006.173.22:21:36.89#ibcon#flushed, iclass 10, count 0 2006.173.22:21:36.89#ibcon#about to write, iclass 10, count 0 2006.173.22:21:36.89#ibcon#wrote, iclass 10, count 0 2006.173.22:21:36.89#ibcon#about to read 3, iclass 10, count 0 2006.173.22:21:36.91#ibcon#read 3, iclass 10, count 0 2006.173.22:21:36.91#ibcon#about to read 4, iclass 10, count 0 2006.173.22:21:36.91#ibcon#read 4, iclass 10, count 0 2006.173.22:21:36.91#ibcon#about to read 5, iclass 10, count 0 2006.173.22:21:36.91#ibcon#read 5, iclass 10, count 0 2006.173.22:21:36.91#ibcon#about to read 6, iclass 10, count 0 2006.173.22:21:36.91#ibcon#read 6, iclass 10, count 0 2006.173.22:21:36.91#ibcon#end of sib2, iclass 10, count 0 2006.173.22:21:36.91#ibcon#*mode == 0, iclass 10, count 0 2006.173.22:21:36.91#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.22:21:36.91#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.22:21:36.91#ibcon#*before write, iclass 10, count 0 2006.173.22:21:36.91#ibcon#enter sib2, iclass 10, count 0 2006.173.22:21:36.91#ibcon#flushed, iclass 10, count 0 2006.173.22:21:36.91#ibcon#about to write, iclass 10, count 0 2006.173.22:21:36.91#ibcon#wrote, iclass 10, count 0 2006.173.22:21:36.91#ibcon#about to read 3, iclass 10, count 0 2006.173.22:21:36.95#ibcon#read 3, iclass 10, count 0 2006.173.22:21:36.95#ibcon#about to read 4, iclass 10, count 0 2006.173.22:21:36.95#ibcon#read 4, iclass 10, count 0 2006.173.22:21:36.95#ibcon#about to read 5, iclass 10, count 0 2006.173.22:21:36.95#ibcon#read 5, iclass 10, count 0 2006.173.22:21:36.95#ibcon#about to read 6, iclass 10, count 0 2006.173.22:21:36.95#ibcon#read 6, iclass 10, count 0 2006.173.22:21:36.95#ibcon#end of sib2, iclass 10, count 0 2006.173.22:21:36.95#ibcon#*after write, iclass 10, count 0 2006.173.22:21:36.95#ibcon#*before return 0, iclass 10, count 0 2006.173.22:21:36.95#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.22:21:36.95#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.22:21:36.95#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.22:21:36.95#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.22:21:36.95$vck44/vb=4,4 2006.173.22:21:36.95#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.22:21:36.95#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.22:21:36.95#ibcon#ireg 11 cls_cnt 2 2006.173.22:21:36.95#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.22:21:37.01#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.22:21:37.01#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.22:21:37.01#ibcon#enter wrdev, iclass 12, count 2 2006.173.22:21:37.01#ibcon#first serial, iclass 12, count 2 2006.173.22:21:37.01#ibcon#enter sib2, iclass 12, count 2 2006.173.22:21:37.01#ibcon#flushed, iclass 12, count 2 2006.173.22:21:37.01#ibcon#about to write, iclass 12, count 2 2006.173.22:21:37.01#ibcon#wrote, iclass 12, count 2 2006.173.22:21:37.01#ibcon#about to read 3, iclass 12, count 2 2006.173.22:21:37.03#ibcon#read 3, iclass 12, count 2 2006.173.22:21:37.03#ibcon#about to read 4, iclass 12, count 2 2006.173.22:21:37.03#ibcon#read 4, iclass 12, count 2 2006.173.22:21:37.03#ibcon#about to read 5, iclass 12, count 2 2006.173.22:21:37.03#ibcon#read 5, iclass 12, count 2 2006.173.22:21:37.03#ibcon#about to read 6, iclass 12, count 2 2006.173.22:21:37.03#ibcon#read 6, iclass 12, count 2 2006.173.22:21:37.03#ibcon#end of sib2, iclass 12, count 2 2006.173.22:21:37.03#ibcon#*mode == 0, iclass 12, count 2 2006.173.22:21:37.03#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.22:21:37.03#ibcon#[27=AT04-04\r\n] 2006.173.22:21:37.03#ibcon#*before write, iclass 12, count 2 2006.173.22:21:37.03#ibcon#enter sib2, iclass 12, count 2 2006.173.22:21:37.03#ibcon#flushed, iclass 12, count 2 2006.173.22:21:37.03#ibcon#about to write, iclass 12, count 2 2006.173.22:21:37.03#ibcon#wrote, iclass 12, count 2 2006.173.22:21:37.03#ibcon#about to read 3, iclass 12, count 2 2006.173.22:21:37.06#ibcon#read 3, iclass 12, count 2 2006.173.22:21:37.06#ibcon#about to read 4, iclass 12, count 2 2006.173.22:21:37.06#ibcon#read 4, iclass 12, count 2 2006.173.22:21:37.06#ibcon#about to read 5, iclass 12, count 2 2006.173.22:21:37.06#ibcon#read 5, iclass 12, count 2 2006.173.22:21:37.06#ibcon#about to read 6, iclass 12, count 2 2006.173.22:21:37.06#ibcon#read 6, iclass 12, count 2 2006.173.22:21:37.06#ibcon#end of sib2, iclass 12, count 2 2006.173.22:21:37.06#ibcon#*after write, iclass 12, count 2 2006.173.22:21:37.06#ibcon#*before return 0, iclass 12, count 2 2006.173.22:21:37.06#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.22:21:37.06#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.22:21:37.06#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.22:21:37.06#ibcon#ireg 7 cls_cnt 0 2006.173.22:21:37.06#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.22:21:37.18#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.22:21:37.18#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.22:21:37.18#ibcon#enter wrdev, iclass 12, count 0 2006.173.22:21:37.18#ibcon#first serial, iclass 12, count 0 2006.173.22:21:37.18#ibcon#enter sib2, iclass 12, count 0 2006.173.22:21:37.18#ibcon#flushed, iclass 12, count 0 2006.173.22:21:37.18#ibcon#about to write, iclass 12, count 0 2006.173.22:21:37.18#ibcon#wrote, iclass 12, count 0 2006.173.22:21:37.18#ibcon#about to read 3, iclass 12, count 0 2006.173.22:21:37.20#ibcon#read 3, iclass 12, count 0 2006.173.22:21:37.20#ibcon#about to read 4, iclass 12, count 0 2006.173.22:21:37.20#ibcon#read 4, iclass 12, count 0 2006.173.22:21:37.20#ibcon#about to read 5, iclass 12, count 0 2006.173.22:21:37.20#ibcon#read 5, iclass 12, count 0 2006.173.22:21:37.20#ibcon#about to read 6, iclass 12, count 0 2006.173.22:21:37.20#ibcon#read 6, iclass 12, count 0 2006.173.22:21:37.20#ibcon#end of sib2, iclass 12, count 0 2006.173.22:21:37.20#ibcon#*mode == 0, iclass 12, count 0 2006.173.22:21:37.20#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.22:21:37.20#ibcon#[27=USB\r\n] 2006.173.22:21:37.20#ibcon#*before write, iclass 12, count 0 2006.173.22:21:37.20#ibcon#enter sib2, iclass 12, count 0 2006.173.22:21:37.20#ibcon#flushed, iclass 12, count 0 2006.173.22:21:37.20#ibcon#about to write, iclass 12, count 0 2006.173.22:21:37.20#ibcon#wrote, iclass 12, count 0 2006.173.22:21:37.20#ibcon#about to read 3, iclass 12, count 0 2006.173.22:21:37.23#ibcon#read 3, iclass 12, count 0 2006.173.22:21:37.23#ibcon#about to read 4, iclass 12, count 0 2006.173.22:21:37.23#ibcon#read 4, iclass 12, count 0 2006.173.22:21:37.23#ibcon#about to read 5, iclass 12, count 0 2006.173.22:21:37.23#ibcon#read 5, iclass 12, count 0 2006.173.22:21:37.23#ibcon#about to read 6, iclass 12, count 0 2006.173.22:21:37.23#ibcon#read 6, iclass 12, count 0 2006.173.22:21:37.23#ibcon#end of sib2, iclass 12, count 0 2006.173.22:21:37.23#ibcon#*after write, iclass 12, count 0 2006.173.22:21:37.23#ibcon#*before return 0, iclass 12, count 0 2006.173.22:21:37.23#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.22:21:37.23#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.22:21:37.23#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.22:21:37.23#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.22:21:37.23$vck44/vblo=5,709.99 2006.173.22:21:37.23#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.22:21:37.23#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.22:21:37.23#ibcon#ireg 17 cls_cnt 0 2006.173.22:21:37.23#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.22:21:37.23#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.22:21:37.23#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.22:21:37.23#ibcon#enter wrdev, iclass 14, count 0 2006.173.22:21:37.23#ibcon#first serial, iclass 14, count 0 2006.173.22:21:37.23#ibcon#enter sib2, iclass 14, count 0 2006.173.22:21:37.23#ibcon#flushed, iclass 14, count 0 2006.173.22:21:37.23#ibcon#about to write, iclass 14, count 0 2006.173.22:21:37.23#ibcon#wrote, iclass 14, count 0 2006.173.22:21:37.23#ibcon#about to read 3, iclass 14, count 0 2006.173.22:21:37.25#ibcon#read 3, iclass 14, count 0 2006.173.22:21:37.25#ibcon#about to read 4, iclass 14, count 0 2006.173.22:21:37.25#ibcon#read 4, iclass 14, count 0 2006.173.22:21:37.25#ibcon#about to read 5, iclass 14, count 0 2006.173.22:21:37.25#ibcon#read 5, iclass 14, count 0 2006.173.22:21:37.25#ibcon#about to read 6, iclass 14, count 0 2006.173.22:21:37.25#ibcon#read 6, iclass 14, count 0 2006.173.22:21:37.25#ibcon#end of sib2, iclass 14, count 0 2006.173.22:21:37.25#ibcon#*mode == 0, iclass 14, count 0 2006.173.22:21:37.25#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.22:21:37.25#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.22:21:37.25#ibcon#*before write, iclass 14, count 0 2006.173.22:21:37.25#ibcon#enter sib2, iclass 14, count 0 2006.173.22:21:37.25#ibcon#flushed, iclass 14, count 0 2006.173.22:21:37.25#ibcon#about to write, iclass 14, count 0 2006.173.22:21:37.25#ibcon#wrote, iclass 14, count 0 2006.173.22:21:37.25#ibcon#about to read 3, iclass 14, count 0 2006.173.22:21:37.29#ibcon#read 3, iclass 14, count 0 2006.173.22:21:37.29#ibcon#about to read 4, iclass 14, count 0 2006.173.22:21:37.29#ibcon#read 4, iclass 14, count 0 2006.173.22:21:37.29#ibcon#about to read 5, iclass 14, count 0 2006.173.22:21:37.29#ibcon#read 5, iclass 14, count 0 2006.173.22:21:37.29#ibcon#about to read 6, iclass 14, count 0 2006.173.22:21:37.29#ibcon#read 6, iclass 14, count 0 2006.173.22:21:37.29#ibcon#end of sib2, iclass 14, count 0 2006.173.22:21:37.29#ibcon#*after write, iclass 14, count 0 2006.173.22:21:37.29#ibcon#*before return 0, iclass 14, count 0 2006.173.22:21:37.29#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.22:21:37.29#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.22:21:37.29#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.22:21:37.29#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.22:21:37.29$vck44/vb=5,4 2006.173.22:21:37.29#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.22:21:37.29#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.22:21:37.29#ibcon#ireg 11 cls_cnt 2 2006.173.22:21:37.29#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.22:21:37.35#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.22:21:37.35#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.22:21:37.35#ibcon#enter wrdev, iclass 16, count 2 2006.173.22:21:37.35#ibcon#first serial, iclass 16, count 2 2006.173.22:21:37.35#ibcon#enter sib2, iclass 16, count 2 2006.173.22:21:37.35#ibcon#flushed, iclass 16, count 2 2006.173.22:21:37.35#ibcon#about to write, iclass 16, count 2 2006.173.22:21:37.35#ibcon#wrote, iclass 16, count 2 2006.173.22:21:37.35#ibcon#about to read 3, iclass 16, count 2 2006.173.22:21:37.37#ibcon#read 3, iclass 16, count 2 2006.173.22:21:37.37#ibcon#about to read 4, iclass 16, count 2 2006.173.22:21:37.37#ibcon#read 4, iclass 16, count 2 2006.173.22:21:37.37#ibcon#about to read 5, iclass 16, count 2 2006.173.22:21:37.37#ibcon#read 5, iclass 16, count 2 2006.173.22:21:37.37#ibcon#about to read 6, iclass 16, count 2 2006.173.22:21:37.37#ibcon#read 6, iclass 16, count 2 2006.173.22:21:37.37#ibcon#end of sib2, iclass 16, count 2 2006.173.22:21:37.37#ibcon#*mode == 0, iclass 16, count 2 2006.173.22:21:37.37#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.22:21:37.37#ibcon#[27=AT05-04\r\n] 2006.173.22:21:37.37#ibcon#*before write, iclass 16, count 2 2006.173.22:21:37.37#ibcon#enter sib2, iclass 16, count 2 2006.173.22:21:37.37#ibcon#flushed, iclass 16, count 2 2006.173.22:21:37.37#ibcon#about to write, iclass 16, count 2 2006.173.22:21:37.37#ibcon#wrote, iclass 16, count 2 2006.173.22:21:37.37#ibcon#about to read 3, iclass 16, count 2 2006.173.22:21:37.40#ibcon#read 3, iclass 16, count 2 2006.173.22:21:37.40#ibcon#about to read 4, iclass 16, count 2 2006.173.22:21:37.40#ibcon#read 4, iclass 16, count 2 2006.173.22:21:37.40#ibcon#about to read 5, iclass 16, count 2 2006.173.22:21:37.40#ibcon#read 5, iclass 16, count 2 2006.173.22:21:37.40#ibcon#about to read 6, iclass 16, count 2 2006.173.22:21:37.40#ibcon#read 6, iclass 16, count 2 2006.173.22:21:37.40#ibcon#end of sib2, iclass 16, count 2 2006.173.22:21:37.40#ibcon#*after write, iclass 16, count 2 2006.173.22:21:37.40#ibcon#*before return 0, iclass 16, count 2 2006.173.22:21:37.40#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.22:21:37.40#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.22:21:37.40#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.22:21:37.40#ibcon#ireg 7 cls_cnt 0 2006.173.22:21:37.40#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.22:21:37.52#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.22:21:37.52#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.22:21:37.52#ibcon#enter wrdev, iclass 16, count 0 2006.173.22:21:37.52#ibcon#first serial, iclass 16, count 0 2006.173.22:21:37.52#ibcon#enter sib2, iclass 16, count 0 2006.173.22:21:37.52#ibcon#flushed, iclass 16, count 0 2006.173.22:21:37.52#ibcon#about to write, iclass 16, count 0 2006.173.22:21:37.52#ibcon#wrote, iclass 16, count 0 2006.173.22:21:37.52#ibcon#about to read 3, iclass 16, count 0 2006.173.22:21:37.54#ibcon#read 3, iclass 16, count 0 2006.173.22:21:37.54#ibcon#about to read 4, iclass 16, count 0 2006.173.22:21:37.54#ibcon#read 4, iclass 16, count 0 2006.173.22:21:37.54#ibcon#about to read 5, iclass 16, count 0 2006.173.22:21:37.54#ibcon#read 5, iclass 16, count 0 2006.173.22:21:37.54#ibcon#about to read 6, iclass 16, count 0 2006.173.22:21:37.54#ibcon#read 6, iclass 16, count 0 2006.173.22:21:37.54#ibcon#end of sib2, iclass 16, count 0 2006.173.22:21:37.54#ibcon#*mode == 0, iclass 16, count 0 2006.173.22:21:37.54#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.22:21:37.54#ibcon#[27=USB\r\n] 2006.173.22:21:37.54#ibcon#*before write, iclass 16, count 0 2006.173.22:21:37.54#ibcon#enter sib2, iclass 16, count 0 2006.173.22:21:37.54#ibcon#flushed, iclass 16, count 0 2006.173.22:21:37.54#ibcon#about to write, iclass 16, count 0 2006.173.22:21:37.54#ibcon#wrote, iclass 16, count 0 2006.173.22:21:37.54#ibcon#about to read 3, iclass 16, count 0 2006.173.22:21:37.57#ibcon#read 3, iclass 16, count 0 2006.173.22:21:37.57#ibcon#about to read 4, iclass 16, count 0 2006.173.22:21:37.57#ibcon#read 4, iclass 16, count 0 2006.173.22:21:37.57#ibcon#about to read 5, iclass 16, count 0 2006.173.22:21:37.57#ibcon#read 5, iclass 16, count 0 2006.173.22:21:37.57#ibcon#about to read 6, iclass 16, count 0 2006.173.22:21:37.57#ibcon#read 6, iclass 16, count 0 2006.173.22:21:37.57#ibcon#end of sib2, iclass 16, count 0 2006.173.22:21:37.57#ibcon#*after write, iclass 16, count 0 2006.173.22:21:37.57#ibcon#*before return 0, iclass 16, count 0 2006.173.22:21:37.57#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.22:21:37.57#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.22:21:37.57#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.22:21:37.57#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.22:21:37.57$vck44/vblo=6,719.99 2006.173.22:21:37.57#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.22:21:37.57#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.22:21:37.57#ibcon#ireg 17 cls_cnt 0 2006.173.22:21:37.57#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.22:21:37.57#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.22:21:37.57#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.22:21:37.57#ibcon#enter wrdev, iclass 18, count 0 2006.173.22:21:37.57#ibcon#first serial, iclass 18, count 0 2006.173.22:21:37.57#ibcon#enter sib2, iclass 18, count 0 2006.173.22:21:37.57#ibcon#flushed, iclass 18, count 0 2006.173.22:21:37.57#ibcon#about to write, iclass 18, count 0 2006.173.22:21:37.57#ibcon#wrote, iclass 18, count 0 2006.173.22:21:37.57#ibcon#about to read 3, iclass 18, count 0 2006.173.22:21:37.59#ibcon#read 3, iclass 18, count 0 2006.173.22:21:37.59#ibcon#about to read 4, iclass 18, count 0 2006.173.22:21:37.59#ibcon#read 4, iclass 18, count 0 2006.173.22:21:37.59#ibcon#about to read 5, iclass 18, count 0 2006.173.22:21:37.59#ibcon#read 5, iclass 18, count 0 2006.173.22:21:37.59#ibcon#about to read 6, iclass 18, count 0 2006.173.22:21:37.59#ibcon#read 6, iclass 18, count 0 2006.173.22:21:37.59#ibcon#end of sib2, iclass 18, count 0 2006.173.22:21:37.59#ibcon#*mode == 0, iclass 18, count 0 2006.173.22:21:37.59#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.22:21:37.59#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.22:21:37.59#ibcon#*before write, iclass 18, count 0 2006.173.22:21:37.59#ibcon#enter sib2, iclass 18, count 0 2006.173.22:21:37.59#ibcon#flushed, iclass 18, count 0 2006.173.22:21:37.59#ibcon#about to write, iclass 18, count 0 2006.173.22:21:37.59#ibcon#wrote, iclass 18, count 0 2006.173.22:21:37.59#ibcon#about to read 3, iclass 18, count 0 2006.173.22:21:37.63#ibcon#read 3, iclass 18, count 0 2006.173.22:21:37.63#ibcon#about to read 4, iclass 18, count 0 2006.173.22:21:37.63#ibcon#read 4, iclass 18, count 0 2006.173.22:21:37.63#ibcon#about to read 5, iclass 18, count 0 2006.173.22:21:37.63#ibcon#read 5, iclass 18, count 0 2006.173.22:21:37.63#ibcon#about to read 6, iclass 18, count 0 2006.173.22:21:37.63#ibcon#read 6, iclass 18, count 0 2006.173.22:21:37.63#ibcon#end of sib2, iclass 18, count 0 2006.173.22:21:37.63#ibcon#*after write, iclass 18, count 0 2006.173.22:21:37.63#ibcon#*before return 0, iclass 18, count 0 2006.173.22:21:37.63#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.22:21:37.63#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.22:21:37.63#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.22:21:37.63#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.22:21:37.63$vck44/vb=6,4 2006.173.22:21:37.63#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.22:21:37.63#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.22:21:37.63#ibcon#ireg 11 cls_cnt 2 2006.173.22:21:37.63#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.22:21:37.69#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.22:21:37.69#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.22:21:37.69#ibcon#enter wrdev, iclass 20, count 2 2006.173.22:21:37.69#ibcon#first serial, iclass 20, count 2 2006.173.22:21:37.69#ibcon#enter sib2, iclass 20, count 2 2006.173.22:21:37.69#ibcon#flushed, iclass 20, count 2 2006.173.22:21:37.69#ibcon#about to write, iclass 20, count 2 2006.173.22:21:37.69#ibcon#wrote, iclass 20, count 2 2006.173.22:21:37.69#ibcon#about to read 3, iclass 20, count 2 2006.173.22:21:37.71#ibcon#read 3, iclass 20, count 2 2006.173.22:21:37.71#ibcon#about to read 4, iclass 20, count 2 2006.173.22:21:37.71#ibcon#read 4, iclass 20, count 2 2006.173.22:21:37.71#ibcon#about to read 5, iclass 20, count 2 2006.173.22:21:37.71#ibcon#read 5, iclass 20, count 2 2006.173.22:21:37.71#ibcon#about to read 6, iclass 20, count 2 2006.173.22:21:37.71#ibcon#read 6, iclass 20, count 2 2006.173.22:21:37.71#ibcon#end of sib2, iclass 20, count 2 2006.173.22:21:37.71#ibcon#*mode == 0, iclass 20, count 2 2006.173.22:21:37.71#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.22:21:37.71#ibcon#[27=AT06-04\r\n] 2006.173.22:21:37.71#ibcon#*before write, iclass 20, count 2 2006.173.22:21:37.71#ibcon#enter sib2, iclass 20, count 2 2006.173.22:21:37.71#ibcon#flushed, iclass 20, count 2 2006.173.22:21:37.71#ibcon#about to write, iclass 20, count 2 2006.173.22:21:37.71#ibcon#wrote, iclass 20, count 2 2006.173.22:21:37.71#ibcon#about to read 3, iclass 20, count 2 2006.173.22:21:37.74#ibcon#read 3, iclass 20, count 2 2006.173.22:21:37.74#ibcon#about to read 4, iclass 20, count 2 2006.173.22:21:37.74#ibcon#read 4, iclass 20, count 2 2006.173.22:21:37.74#ibcon#about to read 5, iclass 20, count 2 2006.173.22:21:37.74#ibcon#read 5, iclass 20, count 2 2006.173.22:21:37.74#ibcon#about to read 6, iclass 20, count 2 2006.173.22:21:37.74#ibcon#read 6, iclass 20, count 2 2006.173.22:21:37.74#ibcon#end of sib2, iclass 20, count 2 2006.173.22:21:37.74#ibcon#*after write, iclass 20, count 2 2006.173.22:21:37.74#ibcon#*before return 0, iclass 20, count 2 2006.173.22:21:37.74#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.22:21:37.74#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.22:21:37.74#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.22:21:37.74#ibcon#ireg 7 cls_cnt 0 2006.173.22:21:37.74#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.22:21:37.86#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.22:21:37.86#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.22:21:37.86#ibcon#enter wrdev, iclass 20, count 0 2006.173.22:21:37.86#ibcon#first serial, iclass 20, count 0 2006.173.22:21:37.86#ibcon#enter sib2, iclass 20, count 0 2006.173.22:21:37.86#ibcon#flushed, iclass 20, count 0 2006.173.22:21:37.86#ibcon#about to write, iclass 20, count 0 2006.173.22:21:37.86#ibcon#wrote, iclass 20, count 0 2006.173.22:21:37.86#ibcon#about to read 3, iclass 20, count 0 2006.173.22:21:37.88#ibcon#read 3, iclass 20, count 0 2006.173.22:21:37.88#ibcon#about to read 4, iclass 20, count 0 2006.173.22:21:37.88#ibcon#read 4, iclass 20, count 0 2006.173.22:21:37.88#ibcon#about to read 5, iclass 20, count 0 2006.173.22:21:37.88#ibcon#read 5, iclass 20, count 0 2006.173.22:21:37.88#ibcon#about to read 6, iclass 20, count 0 2006.173.22:21:37.88#ibcon#read 6, iclass 20, count 0 2006.173.22:21:37.88#ibcon#end of sib2, iclass 20, count 0 2006.173.22:21:37.88#ibcon#*mode == 0, iclass 20, count 0 2006.173.22:21:37.88#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.22:21:37.88#ibcon#[27=USB\r\n] 2006.173.22:21:37.88#ibcon#*before write, iclass 20, count 0 2006.173.22:21:37.88#ibcon#enter sib2, iclass 20, count 0 2006.173.22:21:37.88#ibcon#flushed, iclass 20, count 0 2006.173.22:21:37.88#ibcon#about to write, iclass 20, count 0 2006.173.22:21:37.88#ibcon#wrote, iclass 20, count 0 2006.173.22:21:37.88#ibcon#about to read 3, iclass 20, count 0 2006.173.22:21:37.91#ibcon#read 3, iclass 20, count 0 2006.173.22:21:37.91#ibcon#about to read 4, iclass 20, count 0 2006.173.22:21:37.91#ibcon#read 4, iclass 20, count 0 2006.173.22:21:37.91#ibcon#about to read 5, iclass 20, count 0 2006.173.22:21:37.91#ibcon#read 5, iclass 20, count 0 2006.173.22:21:37.91#ibcon#about to read 6, iclass 20, count 0 2006.173.22:21:37.91#ibcon#read 6, iclass 20, count 0 2006.173.22:21:37.91#ibcon#end of sib2, iclass 20, count 0 2006.173.22:21:37.91#ibcon#*after write, iclass 20, count 0 2006.173.22:21:37.91#ibcon#*before return 0, iclass 20, count 0 2006.173.22:21:37.91#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.22:21:37.91#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.22:21:37.91#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.22:21:37.91#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.22:21:37.91$vck44/vblo=7,734.99 2006.173.22:21:37.91#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.22:21:37.91#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.22:21:37.91#ibcon#ireg 17 cls_cnt 0 2006.173.22:21:37.91#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.22:21:37.91#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.22:21:37.91#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.22:21:37.91#ibcon#enter wrdev, iclass 22, count 0 2006.173.22:21:37.91#ibcon#first serial, iclass 22, count 0 2006.173.22:21:37.91#ibcon#enter sib2, iclass 22, count 0 2006.173.22:21:37.91#ibcon#flushed, iclass 22, count 0 2006.173.22:21:37.91#ibcon#about to write, iclass 22, count 0 2006.173.22:21:37.91#ibcon#wrote, iclass 22, count 0 2006.173.22:21:37.91#ibcon#about to read 3, iclass 22, count 0 2006.173.22:21:37.93#ibcon#read 3, iclass 22, count 0 2006.173.22:21:37.93#ibcon#about to read 4, iclass 22, count 0 2006.173.22:21:37.93#ibcon#read 4, iclass 22, count 0 2006.173.22:21:37.93#ibcon#about to read 5, iclass 22, count 0 2006.173.22:21:37.93#ibcon#read 5, iclass 22, count 0 2006.173.22:21:37.93#ibcon#about to read 6, iclass 22, count 0 2006.173.22:21:37.93#ibcon#read 6, iclass 22, count 0 2006.173.22:21:37.93#ibcon#end of sib2, iclass 22, count 0 2006.173.22:21:37.93#ibcon#*mode == 0, iclass 22, count 0 2006.173.22:21:37.93#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.22:21:37.93#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.22:21:37.93#ibcon#*before write, iclass 22, count 0 2006.173.22:21:37.93#ibcon#enter sib2, iclass 22, count 0 2006.173.22:21:37.93#ibcon#flushed, iclass 22, count 0 2006.173.22:21:37.93#ibcon#about to write, iclass 22, count 0 2006.173.22:21:37.93#ibcon#wrote, iclass 22, count 0 2006.173.22:21:37.93#ibcon#about to read 3, iclass 22, count 0 2006.173.22:21:37.97#ibcon#read 3, iclass 22, count 0 2006.173.22:21:37.97#ibcon#about to read 4, iclass 22, count 0 2006.173.22:21:37.97#ibcon#read 4, iclass 22, count 0 2006.173.22:21:37.97#ibcon#about to read 5, iclass 22, count 0 2006.173.22:21:37.97#ibcon#read 5, iclass 22, count 0 2006.173.22:21:37.97#ibcon#about to read 6, iclass 22, count 0 2006.173.22:21:37.97#ibcon#read 6, iclass 22, count 0 2006.173.22:21:37.97#ibcon#end of sib2, iclass 22, count 0 2006.173.22:21:37.97#ibcon#*after write, iclass 22, count 0 2006.173.22:21:37.97#ibcon#*before return 0, iclass 22, count 0 2006.173.22:21:37.97#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.22:21:37.97#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.22:21:37.97#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.22:21:37.97#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.22:21:37.97$vck44/vb=7,4 2006.173.22:21:37.97#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.22:21:37.97#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.22:21:37.97#ibcon#ireg 11 cls_cnt 2 2006.173.22:21:37.97#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.22:21:38.03#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.22:21:38.03#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.22:21:38.03#ibcon#enter wrdev, iclass 24, count 2 2006.173.22:21:38.03#ibcon#first serial, iclass 24, count 2 2006.173.22:21:38.03#ibcon#enter sib2, iclass 24, count 2 2006.173.22:21:38.03#ibcon#flushed, iclass 24, count 2 2006.173.22:21:38.03#ibcon#about to write, iclass 24, count 2 2006.173.22:21:38.03#ibcon#wrote, iclass 24, count 2 2006.173.22:21:38.03#ibcon#about to read 3, iclass 24, count 2 2006.173.22:21:38.05#ibcon#read 3, iclass 24, count 2 2006.173.22:21:38.05#ibcon#about to read 4, iclass 24, count 2 2006.173.22:21:38.05#ibcon#read 4, iclass 24, count 2 2006.173.22:21:38.05#ibcon#about to read 5, iclass 24, count 2 2006.173.22:21:38.05#ibcon#read 5, iclass 24, count 2 2006.173.22:21:38.05#ibcon#about to read 6, iclass 24, count 2 2006.173.22:21:38.05#ibcon#read 6, iclass 24, count 2 2006.173.22:21:38.05#ibcon#end of sib2, iclass 24, count 2 2006.173.22:21:38.05#ibcon#*mode == 0, iclass 24, count 2 2006.173.22:21:38.05#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.22:21:38.05#ibcon#[27=AT07-04\r\n] 2006.173.22:21:38.05#ibcon#*before write, iclass 24, count 2 2006.173.22:21:38.05#ibcon#enter sib2, iclass 24, count 2 2006.173.22:21:38.05#ibcon#flushed, iclass 24, count 2 2006.173.22:21:38.05#ibcon#about to write, iclass 24, count 2 2006.173.22:21:38.05#ibcon#wrote, iclass 24, count 2 2006.173.22:21:38.05#ibcon#about to read 3, iclass 24, count 2 2006.173.22:21:38.08#ibcon#read 3, iclass 24, count 2 2006.173.22:21:38.08#ibcon#about to read 4, iclass 24, count 2 2006.173.22:21:38.08#ibcon#read 4, iclass 24, count 2 2006.173.22:21:38.08#ibcon#about to read 5, iclass 24, count 2 2006.173.22:21:38.08#ibcon#read 5, iclass 24, count 2 2006.173.22:21:38.08#ibcon#about to read 6, iclass 24, count 2 2006.173.22:21:38.08#ibcon#read 6, iclass 24, count 2 2006.173.22:21:38.08#ibcon#end of sib2, iclass 24, count 2 2006.173.22:21:38.08#ibcon#*after write, iclass 24, count 2 2006.173.22:21:38.08#ibcon#*before return 0, iclass 24, count 2 2006.173.22:21:38.08#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.22:21:38.08#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.22:21:38.08#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.22:21:38.08#ibcon#ireg 7 cls_cnt 0 2006.173.22:21:38.08#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.22:21:38.20#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.22:21:38.20#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.22:21:38.20#ibcon#enter wrdev, iclass 24, count 0 2006.173.22:21:38.20#ibcon#first serial, iclass 24, count 0 2006.173.22:21:38.20#ibcon#enter sib2, iclass 24, count 0 2006.173.22:21:38.20#ibcon#flushed, iclass 24, count 0 2006.173.22:21:38.20#ibcon#about to write, iclass 24, count 0 2006.173.22:21:38.20#ibcon#wrote, iclass 24, count 0 2006.173.22:21:38.20#ibcon#about to read 3, iclass 24, count 0 2006.173.22:21:38.22#ibcon#read 3, iclass 24, count 0 2006.173.22:21:38.22#ibcon#about to read 4, iclass 24, count 0 2006.173.22:21:38.22#ibcon#read 4, iclass 24, count 0 2006.173.22:21:38.22#ibcon#about to read 5, iclass 24, count 0 2006.173.22:21:38.22#ibcon#read 5, iclass 24, count 0 2006.173.22:21:38.22#ibcon#about to read 6, iclass 24, count 0 2006.173.22:21:38.22#ibcon#read 6, iclass 24, count 0 2006.173.22:21:38.22#ibcon#end of sib2, iclass 24, count 0 2006.173.22:21:38.22#ibcon#*mode == 0, iclass 24, count 0 2006.173.22:21:38.22#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.22:21:38.22#ibcon#[27=USB\r\n] 2006.173.22:21:38.22#ibcon#*before write, iclass 24, count 0 2006.173.22:21:38.22#ibcon#enter sib2, iclass 24, count 0 2006.173.22:21:38.22#ibcon#flushed, iclass 24, count 0 2006.173.22:21:38.22#ibcon#about to write, iclass 24, count 0 2006.173.22:21:38.22#ibcon#wrote, iclass 24, count 0 2006.173.22:21:38.22#ibcon#about to read 3, iclass 24, count 0 2006.173.22:21:38.25#ibcon#read 3, iclass 24, count 0 2006.173.22:21:38.25#ibcon#about to read 4, iclass 24, count 0 2006.173.22:21:38.25#ibcon#read 4, iclass 24, count 0 2006.173.22:21:38.25#ibcon#about to read 5, iclass 24, count 0 2006.173.22:21:38.25#ibcon#read 5, iclass 24, count 0 2006.173.22:21:38.25#ibcon#about to read 6, iclass 24, count 0 2006.173.22:21:38.25#ibcon#read 6, iclass 24, count 0 2006.173.22:21:38.25#ibcon#end of sib2, iclass 24, count 0 2006.173.22:21:38.25#ibcon#*after write, iclass 24, count 0 2006.173.22:21:38.25#ibcon#*before return 0, iclass 24, count 0 2006.173.22:21:38.25#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.22:21:38.25#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.22:21:38.25#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.22:21:38.25#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.22:21:38.25$vck44/vblo=8,744.99 2006.173.22:21:38.25#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.22:21:38.25#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.22:21:38.25#ibcon#ireg 17 cls_cnt 0 2006.173.22:21:38.25#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.22:21:38.25#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.22:21:38.25#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.22:21:38.25#ibcon#enter wrdev, iclass 26, count 0 2006.173.22:21:38.25#ibcon#first serial, iclass 26, count 0 2006.173.22:21:38.25#ibcon#enter sib2, iclass 26, count 0 2006.173.22:21:38.25#ibcon#flushed, iclass 26, count 0 2006.173.22:21:38.25#ibcon#about to write, iclass 26, count 0 2006.173.22:21:38.25#ibcon#wrote, iclass 26, count 0 2006.173.22:21:38.25#ibcon#about to read 3, iclass 26, count 0 2006.173.22:21:38.27#ibcon#read 3, iclass 26, count 0 2006.173.22:21:38.27#ibcon#about to read 4, iclass 26, count 0 2006.173.22:21:38.27#ibcon#read 4, iclass 26, count 0 2006.173.22:21:38.27#ibcon#about to read 5, iclass 26, count 0 2006.173.22:21:38.27#ibcon#read 5, iclass 26, count 0 2006.173.22:21:38.27#ibcon#about to read 6, iclass 26, count 0 2006.173.22:21:38.27#ibcon#read 6, iclass 26, count 0 2006.173.22:21:38.27#ibcon#end of sib2, iclass 26, count 0 2006.173.22:21:38.27#ibcon#*mode == 0, iclass 26, count 0 2006.173.22:21:38.27#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.22:21:38.27#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.22:21:38.27#ibcon#*before write, iclass 26, count 0 2006.173.22:21:38.27#ibcon#enter sib2, iclass 26, count 0 2006.173.22:21:38.27#ibcon#flushed, iclass 26, count 0 2006.173.22:21:38.27#ibcon#about to write, iclass 26, count 0 2006.173.22:21:38.27#ibcon#wrote, iclass 26, count 0 2006.173.22:21:38.27#ibcon#about to read 3, iclass 26, count 0 2006.173.22:21:38.31#ibcon#read 3, iclass 26, count 0 2006.173.22:21:38.31#ibcon#about to read 4, iclass 26, count 0 2006.173.22:21:38.31#ibcon#read 4, iclass 26, count 0 2006.173.22:21:38.31#ibcon#about to read 5, iclass 26, count 0 2006.173.22:21:38.31#ibcon#read 5, iclass 26, count 0 2006.173.22:21:38.31#ibcon#about to read 6, iclass 26, count 0 2006.173.22:21:38.31#ibcon#read 6, iclass 26, count 0 2006.173.22:21:38.31#ibcon#end of sib2, iclass 26, count 0 2006.173.22:21:38.31#ibcon#*after write, iclass 26, count 0 2006.173.22:21:38.31#ibcon#*before return 0, iclass 26, count 0 2006.173.22:21:38.31#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.22:21:38.31#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.22:21:38.31#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.22:21:38.31#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.22:21:38.31$vck44/vb=8,4 2006.173.22:21:38.31#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.22:21:38.31#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.22:21:38.31#ibcon#ireg 11 cls_cnt 2 2006.173.22:21:38.31#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.22:21:38.37#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.22:21:38.37#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.22:21:38.37#ibcon#enter wrdev, iclass 28, count 2 2006.173.22:21:38.37#ibcon#first serial, iclass 28, count 2 2006.173.22:21:38.37#ibcon#enter sib2, iclass 28, count 2 2006.173.22:21:38.37#ibcon#flushed, iclass 28, count 2 2006.173.22:21:38.37#ibcon#about to write, iclass 28, count 2 2006.173.22:21:38.37#ibcon#wrote, iclass 28, count 2 2006.173.22:21:38.37#ibcon#about to read 3, iclass 28, count 2 2006.173.22:21:38.39#ibcon#read 3, iclass 28, count 2 2006.173.22:21:38.39#ibcon#about to read 4, iclass 28, count 2 2006.173.22:21:38.39#ibcon#read 4, iclass 28, count 2 2006.173.22:21:38.39#ibcon#about to read 5, iclass 28, count 2 2006.173.22:21:38.39#ibcon#read 5, iclass 28, count 2 2006.173.22:21:38.39#ibcon#about to read 6, iclass 28, count 2 2006.173.22:21:38.39#ibcon#read 6, iclass 28, count 2 2006.173.22:21:38.39#ibcon#end of sib2, iclass 28, count 2 2006.173.22:21:38.39#ibcon#*mode == 0, iclass 28, count 2 2006.173.22:21:38.39#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.22:21:38.39#ibcon#[27=AT08-04\r\n] 2006.173.22:21:38.39#ibcon#*before write, iclass 28, count 2 2006.173.22:21:38.39#ibcon#enter sib2, iclass 28, count 2 2006.173.22:21:38.39#ibcon#flushed, iclass 28, count 2 2006.173.22:21:38.39#ibcon#about to write, iclass 28, count 2 2006.173.22:21:38.39#ibcon#wrote, iclass 28, count 2 2006.173.22:21:38.39#ibcon#about to read 3, iclass 28, count 2 2006.173.22:21:38.42#ibcon#read 3, iclass 28, count 2 2006.173.22:21:38.42#ibcon#about to read 4, iclass 28, count 2 2006.173.22:21:38.42#ibcon#read 4, iclass 28, count 2 2006.173.22:21:38.42#ibcon#about to read 5, iclass 28, count 2 2006.173.22:21:38.42#ibcon#read 5, iclass 28, count 2 2006.173.22:21:38.42#ibcon#about to read 6, iclass 28, count 2 2006.173.22:21:38.42#ibcon#read 6, iclass 28, count 2 2006.173.22:21:38.42#ibcon#end of sib2, iclass 28, count 2 2006.173.22:21:38.42#ibcon#*after write, iclass 28, count 2 2006.173.22:21:38.42#ibcon#*before return 0, iclass 28, count 2 2006.173.22:21:38.42#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.22:21:38.42#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.22:21:38.42#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.22:21:38.42#ibcon#ireg 7 cls_cnt 0 2006.173.22:21:38.42#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.22:21:38.54#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.22:21:38.54#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.22:21:38.54#ibcon#enter wrdev, iclass 28, count 0 2006.173.22:21:38.54#ibcon#first serial, iclass 28, count 0 2006.173.22:21:38.54#ibcon#enter sib2, iclass 28, count 0 2006.173.22:21:38.54#ibcon#flushed, iclass 28, count 0 2006.173.22:21:38.54#ibcon#about to write, iclass 28, count 0 2006.173.22:21:38.54#ibcon#wrote, iclass 28, count 0 2006.173.22:21:38.54#ibcon#about to read 3, iclass 28, count 0 2006.173.22:21:38.56#ibcon#read 3, iclass 28, count 0 2006.173.22:21:38.56#ibcon#about to read 4, iclass 28, count 0 2006.173.22:21:38.56#ibcon#read 4, iclass 28, count 0 2006.173.22:21:38.56#ibcon#about to read 5, iclass 28, count 0 2006.173.22:21:38.56#ibcon#read 5, iclass 28, count 0 2006.173.22:21:38.56#ibcon#about to read 6, iclass 28, count 0 2006.173.22:21:38.56#ibcon#read 6, iclass 28, count 0 2006.173.22:21:38.56#ibcon#end of sib2, iclass 28, count 0 2006.173.22:21:38.56#ibcon#*mode == 0, iclass 28, count 0 2006.173.22:21:38.56#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.22:21:38.56#ibcon#[27=USB\r\n] 2006.173.22:21:38.56#ibcon#*before write, iclass 28, count 0 2006.173.22:21:38.56#ibcon#enter sib2, iclass 28, count 0 2006.173.22:21:38.56#ibcon#flushed, iclass 28, count 0 2006.173.22:21:38.56#ibcon#about to write, iclass 28, count 0 2006.173.22:21:38.56#ibcon#wrote, iclass 28, count 0 2006.173.22:21:38.56#ibcon#about to read 3, iclass 28, count 0 2006.173.22:21:38.59#ibcon#read 3, iclass 28, count 0 2006.173.22:21:38.59#ibcon#about to read 4, iclass 28, count 0 2006.173.22:21:38.59#ibcon#read 4, iclass 28, count 0 2006.173.22:21:38.59#ibcon#about to read 5, iclass 28, count 0 2006.173.22:21:38.59#ibcon#read 5, iclass 28, count 0 2006.173.22:21:38.59#ibcon#about to read 6, iclass 28, count 0 2006.173.22:21:38.59#ibcon#read 6, iclass 28, count 0 2006.173.22:21:38.59#ibcon#end of sib2, iclass 28, count 0 2006.173.22:21:38.59#ibcon#*after write, iclass 28, count 0 2006.173.22:21:38.59#ibcon#*before return 0, iclass 28, count 0 2006.173.22:21:38.59#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.22:21:38.59#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.22:21:38.59#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.22:21:38.59#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.22:21:38.59$vck44/vabw=wide 2006.173.22:21:38.59#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.22:21:38.59#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.22:21:38.59#ibcon#ireg 8 cls_cnt 0 2006.173.22:21:38.59#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.22:21:38.59#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.22:21:38.59#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.22:21:38.59#ibcon#enter wrdev, iclass 30, count 0 2006.173.22:21:38.59#ibcon#first serial, iclass 30, count 0 2006.173.22:21:38.59#ibcon#enter sib2, iclass 30, count 0 2006.173.22:21:38.59#ibcon#flushed, iclass 30, count 0 2006.173.22:21:38.59#ibcon#about to write, iclass 30, count 0 2006.173.22:21:38.59#ibcon#wrote, iclass 30, count 0 2006.173.22:21:38.59#ibcon#about to read 3, iclass 30, count 0 2006.173.22:21:38.61#ibcon#read 3, iclass 30, count 0 2006.173.22:21:38.61#ibcon#about to read 4, iclass 30, count 0 2006.173.22:21:38.61#ibcon#read 4, iclass 30, count 0 2006.173.22:21:38.61#ibcon#about to read 5, iclass 30, count 0 2006.173.22:21:38.61#ibcon#read 5, iclass 30, count 0 2006.173.22:21:38.61#ibcon#about to read 6, iclass 30, count 0 2006.173.22:21:38.61#ibcon#read 6, iclass 30, count 0 2006.173.22:21:38.61#ibcon#end of sib2, iclass 30, count 0 2006.173.22:21:38.61#ibcon#*mode == 0, iclass 30, count 0 2006.173.22:21:38.61#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.22:21:38.61#ibcon#[25=BW32\r\n] 2006.173.22:21:38.61#ibcon#*before write, iclass 30, count 0 2006.173.22:21:38.61#ibcon#enter sib2, iclass 30, count 0 2006.173.22:21:38.61#ibcon#flushed, iclass 30, count 0 2006.173.22:21:38.61#ibcon#about to write, iclass 30, count 0 2006.173.22:21:38.61#ibcon#wrote, iclass 30, count 0 2006.173.22:21:38.61#ibcon#about to read 3, iclass 30, count 0 2006.173.22:21:38.64#ibcon#read 3, iclass 30, count 0 2006.173.22:21:38.64#ibcon#about to read 4, iclass 30, count 0 2006.173.22:21:38.64#ibcon#read 4, iclass 30, count 0 2006.173.22:21:38.64#ibcon#about to read 5, iclass 30, count 0 2006.173.22:21:38.64#ibcon#read 5, iclass 30, count 0 2006.173.22:21:38.64#ibcon#about to read 6, iclass 30, count 0 2006.173.22:21:38.64#ibcon#read 6, iclass 30, count 0 2006.173.22:21:38.64#ibcon#end of sib2, iclass 30, count 0 2006.173.22:21:38.64#ibcon#*after write, iclass 30, count 0 2006.173.22:21:38.64#ibcon#*before return 0, iclass 30, count 0 2006.173.22:21:38.64#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.22:21:38.64#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.22:21:38.64#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.22:21:38.64#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.22:21:38.64$vck44/vbbw=wide 2006.173.22:21:38.64#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.22:21:38.64#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.22:21:38.64#ibcon#ireg 8 cls_cnt 0 2006.173.22:21:38.64#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.22:21:38.71#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.22:21:38.71#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.22:21:38.71#ibcon#enter wrdev, iclass 32, count 0 2006.173.22:21:38.71#ibcon#first serial, iclass 32, count 0 2006.173.22:21:38.71#ibcon#enter sib2, iclass 32, count 0 2006.173.22:21:38.71#ibcon#flushed, iclass 32, count 0 2006.173.22:21:38.71#ibcon#about to write, iclass 32, count 0 2006.173.22:21:38.71#ibcon#wrote, iclass 32, count 0 2006.173.22:21:38.71#ibcon#about to read 3, iclass 32, count 0 2006.173.22:21:38.73#ibcon#read 3, iclass 32, count 0 2006.173.22:21:38.73#ibcon#about to read 4, iclass 32, count 0 2006.173.22:21:38.73#ibcon#read 4, iclass 32, count 0 2006.173.22:21:38.73#ibcon#about to read 5, iclass 32, count 0 2006.173.22:21:38.73#ibcon#read 5, iclass 32, count 0 2006.173.22:21:38.73#ibcon#about to read 6, iclass 32, count 0 2006.173.22:21:38.73#ibcon#read 6, iclass 32, count 0 2006.173.22:21:38.73#ibcon#end of sib2, iclass 32, count 0 2006.173.22:21:38.73#ibcon#*mode == 0, iclass 32, count 0 2006.173.22:21:38.73#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.22:21:38.73#ibcon#[27=BW32\r\n] 2006.173.22:21:38.73#ibcon#*before write, iclass 32, count 0 2006.173.22:21:38.73#ibcon#enter sib2, iclass 32, count 0 2006.173.22:21:38.73#ibcon#flushed, iclass 32, count 0 2006.173.22:21:38.73#ibcon#about to write, iclass 32, count 0 2006.173.22:21:38.73#ibcon#wrote, iclass 32, count 0 2006.173.22:21:38.73#ibcon#about to read 3, iclass 32, count 0 2006.173.22:21:38.76#ibcon#read 3, iclass 32, count 0 2006.173.22:21:38.76#ibcon#about to read 4, iclass 32, count 0 2006.173.22:21:38.76#ibcon#read 4, iclass 32, count 0 2006.173.22:21:38.76#ibcon#about to read 5, iclass 32, count 0 2006.173.22:21:38.76#ibcon#read 5, iclass 32, count 0 2006.173.22:21:38.76#ibcon#about to read 6, iclass 32, count 0 2006.173.22:21:38.76#ibcon#read 6, iclass 32, count 0 2006.173.22:21:38.76#ibcon#end of sib2, iclass 32, count 0 2006.173.22:21:38.76#ibcon#*after write, iclass 32, count 0 2006.173.22:21:38.76#ibcon#*before return 0, iclass 32, count 0 2006.173.22:21:38.76#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.22:21:38.76#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.22:21:38.76#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.22:21:38.76#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.22:21:38.76$setupk4/ifdk4 2006.173.22:21:38.76$ifdk4/lo= 2006.173.22:21:38.76$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.22:21:38.76$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.22:21:38.76$ifdk4/patch= 2006.173.22:21:38.76$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.22:21:38.76$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.22:21:38.76$setupk4/!*+20s 2006.173.22:21:41.68#abcon#<5=/09 0.7 2.0 22.20 961003.4\r\n> 2006.173.22:21:41.70#abcon#{5=INTERFACE CLEAR} 2006.173.22:21:41.76#abcon#[5=S1D000X0/0*\r\n] 2006.173.22:21:51.85#abcon#<5=/09 0.7 2.0 22.21 961003.3\r\n> 2006.173.22:21:51.87#abcon#{5=INTERFACE CLEAR} 2006.173.22:21:51.93#abcon#[5=S1D000X0/0*\r\n] 2006.173.22:21:53.27$setupk4/"tpicd 2006.173.22:21:53.27$setupk4/echo=off 2006.173.22:21:53.27$setupk4/xlog=off 2006.173.22:21:53.27:!2006.173.22:24:10 2006.173.22:22:30.14#trakl#Source acquired 2006.173.22:22:31.14#flagr#flagr/antenna,acquired 2006.173.22:24:10.02:preob 2006.173.22:24:11.14/onsource/TRACKING 2006.173.22:24:11.14:!2006.173.22:24:20 2006.173.22:24:20.01:"tape 2006.173.22:24:20.02:"st=record 2006.173.22:24:20.02:data_valid=on 2006.173.22:24:20.02:midob 2006.173.22:24:21.15/onsource/TRACKING 2006.173.22:24:21.15/wx/22.32,1003.3,94 2006.173.22:24:21.24/cable/+6.5111E-03 2006.173.22:24:22.33/va/01,07,usb,yes,35,37 2006.173.22:24:22.33/va/02,06,usb,yes,35,35 2006.173.22:24:22.33/va/03,05,usb,yes,44,46 2006.173.22:24:22.34/va/04,06,usb,yes,35,37 2006.173.22:24:22.34/va/05,04,usb,yes,28,28 2006.173.22:24:22.34/va/06,03,usb,yes,39,39 2006.173.22:24:22.34/va/07,04,usb,yes,31,33 2006.173.22:24:22.34/va/08,04,usb,yes,27,32 2006.173.22:24:22.57/valo/01,524.99,yes,locked 2006.173.22:24:22.57/valo/02,534.99,yes,locked 2006.173.22:24:22.57/valo/03,564.99,yes,locked 2006.173.22:24:22.57/valo/04,624.99,yes,locked 2006.173.22:24:22.57/valo/05,734.99,yes,locked 2006.173.22:24:22.57/valo/06,814.99,yes,locked 2006.173.22:24:22.57/valo/07,864.99,yes,locked 2006.173.22:24:22.57/valo/08,884.99,yes,locked 2006.173.22:24:23.65/vb/01,04,usb,yes,29,27 2006.173.22:24:23.65/vb/02,04,usb,yes,31,31 2006.173.22:24:23.66/vb/03,04,usb,yes,28,31 2006.173.22:24:23.66/vb/04,04,usb,yes,32,31 2006.173.22:24:23.66/vb/05,04,usb,yes,25,28 2006.173.22:24:23.66/vb/06,04,usb,yes,30,26 2006.173.22:24:23.66/vb/07,04,usb,yes,29,29 2006.173.22:24:23.66/vb/08,04,usb,yes,27,30 2006.173.22:24:23.90/vblo/01,629.99,yes,locked 2006.173.22:24:23.90/vblo/02,634.99,yes,locked 2006.173.22:24:23.90/vblo/03,649.99,yes,locked 2006.173.22:24:23.90/vblo/04,679.99,yes,locked 2006.173.22:24:23.90/vblo/05,709.99,yes,locked 2006.173.22:24:23.90/vblo/06,719.99,yes,locked 2006.173.22:24:23.90/vblo/07,734.99,yes,locked 2006.173.22:24:23.90/vblo/08,744.99,yes,locked 2006.173.22:24:24.04/vabw/8 2006.173.22:24:24.19/vbbw/8 2006.173.22:24:24.29/xfe/off,on,14.7 2006.173.22:24:24.67/ifatt/23,28,28,28 2006.173.22:24:25.07/fmout-gps/S +3.78E-07 2006.173.22:24:25.12:!2006.173.22:25:10 2006.173.22:25:10.02:data_valid=off 2006.173.22:25:10.02:"et 2006.173.22:25:10.02:!+3s 2006.173.22:25:13.04:"tape 2006.173.22:25:13.05:postob 2006.173.22:25:13.20/cable/+6.5131E-03 2006.173.22:25:13.21/wx/22.35,1003.3,95 2006.173.22:25:13.26/fmout-gps/S +3.78E-07 2006.173.22:25:13.27:scan_name=173-2227,jd0606,310 2006.173.22:25:13.27:source=nrao150,035929.75,505750.2,2000.0,ccw 2006.173.22:25:15.14#flagr#flagr/antenna,new-source 2006.173.22:25:15.14:checkk5 2006.173.22:25:15.49/chk_autoobs//k5ts1/ autoobs is running! 2006.173.22:25:15.89/chk_autoobs//k5ts2/ autoobs is running! 2006.173.22:25:16.29/chk_autoobs//k5ts3/ autoobs is running! 2006.173.22:25:16.69/chk_autoobs//k5ts4/ autoobs is running! 2006.173.22:25:17.08/chk_obsdata//k5ts1/T1732224??a.dat file size is correct (nominal:200MB, actual:196MB). 2006.173.22:25:17.47/chk_obsdata//k5ts2/T1732224??b.dat file size is correct (nominal:200MB, actual:196MB). 2006.173.22:25:17.87/chk_obsdata//k5ts3/T1732224??c.dat file size is correct (nominal:200MB, actual:196MB). 2006.173.22:25:18.26/chk_obsdata//k5ts4/T1732224??d.dat file size is correct (nominal:200MB, actual:196MB). 2006.173.22:25:18.98/k5log//k5ts1_log_newline 2006.173.22:25:19.68/k5log//k5ts2_log_newline 2006.173.22:25:20.38/k5log//k5ts3_log_newline 2006.173.22:25:21.08/k5log//k5ts4_log_newline 2006.173.22:25:21.11/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.22:25:21.11:setupk4=1 2006.173.22:25:21.11$setupk4/echo=on 2006.173.22:25:21.11$setupk4/pcalon 2006.173.22:25:21.11$pcalon/"no phase cal control is implemented here 2006.173.22:25:21.11$setupk4/"tpicd=stop 2006.173.22:25:21.11$setupk4/"rec=synch_on 2006.173.22:25:21.11$setupk4/"rec_mode=128 2006.173.22:25:21.11$setupk4/!* 2006.173.22:25:21.11$setupk4/recpk4 2006.173.22:25:21.11$recpk4/recpatch= 2006.173.22:25:21.11$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.22:25:21.11$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.22:25:21.11$setupk4/vck44 2006.173.22:25:21.11$vck44/valo=1,524.99 2006.173.22:25:21.11#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.22:25:21.11#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.22:25:21.11#ibcon#ireg 17 cls_cnt 0 2006.173.22:25:21.11#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.22:25:21.11#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.22:25:21.11#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.22:25:21.11#ibcon#enter wrdev, iclass 17, count 0 2006.173.22:25:21.11#ibcon#first serial, iclass 17, count 0 2006.173.22:25:21.11#ibcon#enter sib2, iclass 17, count 0 2006.173.22:25:21.11#ibcon#flushed, iclass 17, count 0 2006.173.22:25:21.11#ibcon#about to write, iclass 17, count 0 2006.173.22:25:21.11#ibcon#wrote, iclass 17, count 0 2006.173.22:25:21.11#ibcon#about to read 3, iclass 17, count 0 2006.173.22:25:21.12#ibcon#read 3, iclass 17, count 0 2006.173.22:25:21.12#ibcon#about to read 4, iclass 17, count 0 2006.173.22:25:21.12#ibcon#read 4, iclass 17, count 0 2006.173.22:25:21.12#ibcon#about to read 5, iclass 17, count 0 2006.173.22:25:21.12#ibcon#read 5, iclass 17, count 0 2006.173.22:25:21.12#ibcon#about to read 6, iclass 17, count 0 2006.173.22:25:21.12#ibcon#read 6, iclass 17, count 0 2006.173.22:25:21.12#ibcon#end of sib2, iclass 17, count 0 2006.173.22:25:21.12#ibcon#*mode == 0, iclass 17, count 0 2006.173.22:25:21.12#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.22:25:21.12#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.22:25:21.12#ibcon#*before write, iclass 17, count 0 2006.173.22:25:21.12#ibcon#enter sib2, iclass 17, count 0 2006.173.22:25:21.12#ibcon#flushed, iclass 17, count 0 2006.173.22:25:21.12#ibcon#about to write, iclass 17, count 0 2006.173.22:25:21.12#ibcon#wrote, iclass 17, count 0 2006.173.22:25:21.12#ibcon#about to read 3, iclass 17, count 0 2006.173.22:25:21.17#ibcon#read 3, iclass 17, count 0 2006.173.22:25:21.17#ibcon#about to read 4, iclass 17, count 0 2006.173.22:25:21.17#ibcon#read 4, iclass 17, count 0 2006.173.22:25:21.17#ibcon#about to read 5, iclass 17, count 0 2006.173.22:25:21.17#ibcon#read 5, iclass 17, count 0 2006.173.22:25:21.17#ibcon#about to read 6, iclass 17, count 0 2006.173.22:25:21.17#ibcon#read 6, iclass 17, count 0 2006.173.22:25:21.17#ibcon#end of sib2, iclass 17, count 0 2006.173.22:25:21.17#ibcon#*after write, iclass 17, count 0 2006.173.22:25:21.17#ibcon#*before return 0, iclass 17, count 0 2006.173.22:25:21.17#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.22:25:21.17#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.22:25:21.17#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.22:25:21.17#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.22:25:21.18$vck44/va=1,7 2006.173.22:25:21.18#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.22:25:21.18#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.22:25:21.18#ibcon#ireg 11 cls_cnt 2 2006.173.22:25:21.18#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.22:25:21.18#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.22:25:21.18#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.22:25:21.18#ibcon#enter wrdev, iclass 19, count 2 2006.173.22:25:21.18#ibcon#first serial, iclass 19, count 2 2006.173.22:25:21.18#ibcon#enter sib2, iclass 19, count 2 2006.173.22:25:21.18#ibcon#flushed, iclass 19, count 2 2006.173.22:25:21.18#ibcon#about to write, iclass 19, count 2 2006.173.22:25:21.18#ibcon#wrote, iclass 19, count 2 2006.173.22:25:21.18#ibcon#about to read 3, iclass 19, count 2 2006.173.22:25:21.19#ibcon#read 3, iclass 19, count 2 2006.173.22:25:21.19#ibcon#about to read 4, iclass 19, count 2 2006.173.22:25:21.19#ibcon#read 4, iclass 19, count 2 2006.173.22:25:21.19#ibcon#about to read 5, iclass 19, count 2 2006.173.22:25:21.19#ibcon#read 5, iclass 19, count 2 2006.173.22:25:21.19#ibcon#about to read 6, iclass 19, count 2 2006.173.22:25:21.19#ibcon#read 6, iclass 19, count 2 2006.173.22:25:21.19#ibcon#end of sib2, iclass 19, count 2 2006.173.22:25:21.19#ibcon#*mode == 0, iclass 19, count 2 2006.173.22:25:21.19#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.22:25:21.19#ibcon#[25=AT01-07\r\n] 2006.173.22:25:21.19#ibcon#*before write, iclass 19, count 2 2006.173.22:25:21.19#ibcon#enter sib2, iclass 19, count 2 2006.173.22:25:21.19#ibcon#flushed, iclass 19, count 2 2006.173.22:25:21.19#ibcon#about to write, iclass 19, count 2 2006.173.22:25:21.19#ibcon#wrote, iclass 19, count 2 2006.173.22:25:21.19#ibcon#about to read 3, iclass 19, count 2 2006.173.22:25:21.22#ibcon#read 3, iclass 19, count 2 2006.173.22:25:21.22#ibcon#about to read 4, iclass 19, count 2 2006.173.22:25:21.22#ibcon#read 4, iclass 19, count 2 2006.173.22:25:21.22#ibcon#about to read 5, iclass 19, count 2 2006.173.22:25:21.22#ibcon#read 5, iclass 19, count 2 2006.173.22:25:21.22#ibcon#about to read 6, iclass 19, count 2 2006.173.22:25:21.22#ibcon#read 6, iclass 19, count 2 2006.173.22:25:21.22#ibcon#end of sib2, iclass 19, count 2 2006.173.22:25:21.22#ibcon#*after write, iclass 19, count 2 2006.173.22:25:21.22#ibcon#*before return 0, iclass 19, count 2 2006.173.22:25:21.22#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.22:25:21.22#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.22:25:21.22#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.22:25:21.22#ibcon#ireg 7 cls_cnt 0 2006.173.22:25:21.22#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.22:25:21.34#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.22:25:21.34#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.22:25:21.34#ibcon#enter wrdev, iclass 19, count 0 2006.173.22:25:21.34#ibcon#first serial, iclass 19, count 0 2006.173.22:25:21.34#ibcon#enter sib2, iclass 19, count 0 2006.173.22:25:21.34#ibcon#flushed, iclass 19, count 0 2006.173.22:25:21.34#ibcon#about to write, iclass 19, count 0 2006.173.22:25:21.34#ibcon#wrote, iclass 19, count 0 2006.173.22:25:21.34#ibcon#about to read 3, iclass 19, count 0 2006.173.22:25:21.36#ibcon#read 3, iclass 19, count 0 2006.173.22:25:21.36#ibcon#about to read 4, iclass 19, count 0 2006.173.22:25:21.36#ibcon#read 4, iclass 19, count 0 2006.173.22:25:21.36#ibcon#about to read 5, iclass 19, count 0 2006.173.22:25:21.36#ibcon#read 5, iclass 19, count 0 2006.173.22:25:21.36#ibcon#about to read 6, iclass 19, count 0 2006.173.22:25:21.36#ibcon#read 6, iclass 19, count 0 2006.173.22:25:21.36#ibcon#end of sib2, iclass 19, count 0 2006.173.22:25:21.36#ibcon#*mode == 0, iclass 19, count 0 2006.173.22:25:21.36#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.22:25:21.36#ibcon#[25=USB\r\n] 2006.173.22:25:21.36#ibcon#*before write, iclass 19, count 0 2006.173.22:25:21.36#ibcon#enter sib2, iclass 19, count 0 2006.173.22:25:21.36#ibcon#flushed, iclass 19, count 0 2006.173.22:25:21.36#ibcon#about to write, iclass 19, count 0 2006.173.22:25:21.36#ibcon#wrote, iclass 19, count 0 2006.173.22:25:21.36#ibcon#about to read 3, iclass 19, count 0 2006.173.22:25:21.39#ibcon#read 3, iclass 19, count 0 2006.173.22:25:21.39#ibcon#about to read 4, iclass 19, count 0 2006.173.22:25:21.39#ibcon#read 4, iclass 19, count 0 2006.173.22:25:21.39#ibcon#about to read 5, iclass 19, count 0 2006.173.22:25:21.39#ibcon#read 5, iclass 19, count 0 2006.173.22:25:21.39#ibcon#about to read 6, iclass 19, count 0 2006.173.22:25:21.39#ibcon#read 6, iclass 19, count 0 2006.173.22:25:21.39#ibcon#end of sib2, iclass 19, count 0 2006.173.22:25:21.39#ibcon#*after write, iclass 19, count 0 2006.173.22:25:21.39#ibcon#*before return 0, iclass 19, count 0 2006.173.22:25:21.39#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.22:25:21.39#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.22:25:21.39#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.22:25:21.39#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.22:25:21.40$vck44/valo=2,534.99 2006.173.22:25:21.40#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.22:25:21.40#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.22:25:21.40#ibcon#ireg 17 cls_cnt 0 2006.173.22:25:21.40#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.22:25:21.40#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.22:25:21.40#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.22:25:21.40#ibcon#enter wrdev, iclass 21, count 0 2006.173.22:25:21.40#ibcon#first serial, iclass 21, count 0 2006.173.22:25:21.40#ibcon#enter sib2, iclass 21, count 0 2006.173.22:25:21.40#ibcon#flushed, iclass 21, count 0 2006.173.22:25:21.40#ibcon#about to write, iclass 21, count 0 2006.173.22:25:21.40#ibcon#wrote, iclass 21, count 0 2006.173.22:25:21.40#ibcon#about to read 3, iclass 21, count 0 2006.173.22:25:21.41#ibcon#read 3, iclass 21, count 0 2006.173.22:25:21.41#ibcon#about to read 4, iclass 21, count 0 2006.173.22:25:21.41#ibcon#read 4, iclass 21, count 0 2006.173.22:25:21.41#ibcon#about to read 5, iclass 21, count 0 2006.173.22:25:21.41#ibcon#read 5, iclass 21, count 0 2006.173.22:25:21.41#ibcon#about to read 6, iclass 21, count 0 2006.173.22:25:21.41#ibcon#read 6, iclass 21, count 0 2006.173.22:25:21.41#ibcon#end of sib2, iclass 21, count 0 2006.173.22:25:21.41#ibcon#*mode == 0, iclass 21, count 0 2006.173.22:25:21.41#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.22:25:21.41#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.22:25:21.41#ibcon#*before write, iclass 21, count 0 2006.173.22:25:21.41#ibcon#enter sib2, iclass 21, count 0 2006.173.22:25:21.41#ibcon#flushed, iclass 21, count 0 2006.173.22:25:21.41#ibcon#about to write, iclass 21, count 0 2006.173.22:25:21.41#ibcon#wrote, iclass 21, count 0 2006.173.22:25:21.41#ibcon#about to read 3, iclass 21, count 0 2006.173.22:25:21.45#ibcon#read 3, iclass 21, count 0 2006.173.22:25:21.45#ibcon#about to read 4, iclass 21, count 0 2006.173.22:25:21.45#ibcon#read 4, iclass 21, count 0 2006.173.22:25:21.45#ibcon#about to read 5, iclass 21, count 0 2006.173.22:25:21.45#ibcon#read 5, iclass 21, count 0 2006.173.22:25:21.45#ibcon#about to read 6, iclass 21, count 0 2006.173.22:25:21.45#ibcon#read 6, iclass 21, count 0 2006.173.22:25:21.45#ibcon#end of sib2, iclass 21, count 0 2006.173.22:25:21.45#ibcon#*after write, iclass 21, count 0 2006.173.22:25:21.45#ibcon#*before return 0, iclass 21, count 0 2006.173.22:25:21.45#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.22:25:21.45#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.22:25:21.45#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.22:25:21.45#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.22:25:21.46$vck44/va=2,6 2006.173.22:25:21.46#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.22:25:21.46#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.22:25:21.46#ibcon#ireg 11 cls_cnt 2 2006.173.22:25:21.46#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.22:25:21.50#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.22:25:21.50#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.22:25:21.50#ibcon#enter wrdev, iclass 23, count 2 2006.173.22:25:21.50#ibcon#first serial, iclass 23, count 2 2006.173.22:25:21.50#ibcon#enter sib2, iclass 23, count 2 2006.173.22:25:21.50#ibcon#flushed, iclass 23, count 2 2006.173.22:25:21.50#ibcon#about to write, iclass 23, count 2 2006.173.22:25:21.50#ibcon#wrote, iclass 23, count 2 2006.173.22:25:21.50#ibcon#about to read 3, iclass 23, count 2 2006.173.22:25:21.52#ibcon#read 3, iclass 23, count 2 2006.173.22:25:21.52#ibcon#about to read 4, iclass 23, count 2 2006.173.22:25:21.52#ibcon#read 4, iclass 23, count 2 2006.173.22:25:21.52#ibcon#about to read 5, iclass 23, count 2 2006.173.22:25:21.52#ibcon#read 5, iclass 23, count 2 2006.173.22:25:21.52#ibcon#about to read 6, iclass 23, count 2 2006.173.22:25:21.52#ibcon#read 6, iclass 23, count 2 2006.173.22:25:21.52#ibcon#end of sib2, iclass 23, count 2 2006.173.22:25:21.52#ibcon#*mode == 0, iclass 23, count 2 2006.173.22:25:21.52#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.22:25:21.52#ibcon#[25=AT02-06\r\n] 2006.173.22:25:21.52#ibcon#*before write, iclass 23, count 2 2006.173.22:25:21.52#ibcon#enter sib2, iclass 23, count 2 2006.173.22:25:21.52#ibcon#flushed, iclass 23, count 2 2006.173.22:25:21.52#ibcon#about to write, iclass 23, count 2 2006.173.22:25:21.52#ibcon#wrote, iclass 23, count 2 2006.173.22:25:21.52#ibcon#about to read 3, iclass 23, count 2 2006.173.22:25:21.55#ibcon#read 3, iclass 23, count 2 2006.173.22:25:21.55#ibcon#about to read 4, iclass 23, count 2 2006.173.22:25:21.55#ibcon#read 4, iclass 23, count 2 2006.173.22:25:21.55#ibcon#about to read 5, iclass 23, count 2 2006.173.22:25:21.55#ibcon#read 5, iclass 23, count 2 2006.173.22:25:21.55#ibcon#about to read 6, iclass 23, count 2 2006.173.22:25:21.55#ibcon#read 6, iclass 23, count 2 2006.173.22:25:21.55#ibcon#end of sib2, iclass 23, count 2 2006.173.22:25:21.55#ibcon#*after write, iclass 23, count 2 2006.173.22:25:21.55#ibcon#*before return 0, iclass 23, count 2 2006.173.22:25:21.55#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.22:25:21.55#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.22:25:21.55#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.22:25:21.55#ibcon#ireg 7 cls_cnt 0 2006.173.22:25:21.55#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.22:25:21.67#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.22:25:21.67#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.22:25:21.67#ibcon#enter wrdev, iclass 23, count 0 2006.173.22:25:21.67#ibcon#first serial, iclass 23, count 0 2006.173.22:25:21.67#ibcon#enter sib2, iclass 23, count 0 2006.173.22:25:21.67#ibcon#flushed, iclass 23, count 0 2006.173.22:25:21.67#ibcon#about to write, iclass 23, count 0 2006.173.22:25:21.67#ibcon#wrote, iclass 23, count 0 2006.173.22:25:21.67#ibcon#about to read 3, iclass 23, count 0 2006.173.22:25:21.69#ibcon#read 3, iclass 23, count 0 2006.173.22:25:21.69#ibcon#about to read 4, iclass 23, count 0 2006.173.22:25:21.69#ibcon#read 4, iclass 23, count 0 2006.173.22:25:21.69#ibcon#about to read 5, iclass 23, count 0 2006.173.22:25:21.69#ibcon#read 5, iclass 23, count 0 2006.173.22:25:21.69#ibcon#about to read 6, iclass 23, count 0 2006.173.22:25:21.69#ibcon#read 6, iclass 23, count 0 2006.173.22:25:21.69#ibcon#end of sib2, iclass 23, count 0 2006.173.22:25:21.69#ibcon#*mode == 0, iclass 23, count 0 2006.173.22:25:21.69#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.22:25:21.69#ibcon#[25=USB\r\n] 2006.173.22:25:21.69#ibcon#*before write, iclass 23, count 0 2006.173.22:25:21.69#ibcon#enter sib2, iclass 23, count 0 2006.173.22:25:21.69#ibcon#flushed, iclass 23, count 0 2006.173.22:25:21.69#ibcon#about to write, iclass 23, count 0 2006.173.22:25:21.69#ibcon#wrote, iclass 23, count 0 2006.173.22:25:21.69#ibcon#about to read 3, iclass 23, count 0 2006.173.22:25:21.72#ibcon#read 3, iclass 23, count 0 2006.173.22:25:21.72#ibcon#about to read 4, iclass 23, count 0 2006.173.22:25:21.72#ibcon#read 4, iclass 23, count 0 2006.173.22:25:21.72#ibcon#about to read 5, iclass 23, count 0 2006.173.22:25:21.72#ibcon#read 5, iclass 23, count 0 2006.173.22:25:21.72#ibcon#about to read 6, iclass 23, count 0 2006.173.22:25:21.72#ibcon#read 6, iclass 23, count 0 2006.173.22:25:21.72#ibcon#end of sib2, iclass 23, count 0 2006.173.22:25:21.72#ibcon#*after write, iclass 23, count 0 2006.173.22:25:21.72#ibcon#*before return 0, iclass 23, count 0 2006.173.22:25:21.72#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.22:25:21.72#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.22:25:21.72#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.22:25:21.72#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.22:25:21.73$vck44/valo=3,564.99 2006.173.22:25:21.73#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.22:25:21.73#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.22:25:21.73#ibcon#ireg 17 cls_cnt 0 2006.173.22:25:21.73#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.22:25:21.73#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.22:25:21.73#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.22:25:21.73#ibcon#enter wrdev, iclass 25, count 0 2006.173.22:25:21.73#ibcon#first serial, iclass 25, count 0 2006.173.22:25:21.73#ibcon#enter sib2, iclass 25, count 0 2006.173.22:25:21.73#ibcon#flushed, iclass 25, count 0 2006.173.22:25:21.73#ibcon#about to write, iclass 25, count 0 2006.173.22:25:21.73#ibcon#wrote, iclass 25, count 0 2006.173.22:25:21.73#ibcon#about to read 3, iclass 25, count 0 2006.173.22:25:21.74#ibcon#read 3, iclass 25, count 0 2006.173.22:25:21.74#ibcon#about to read 4, iclass 25, count 0 2006.173.22:25:21.74#ibcon#read 4, iclass 25, count 0 2006.173.22:25:21.74#ibcon#about to read 5, iclass 25, count 0 2006.173.22:25:21.74#ibcon#read 5, iclass 25, count 0 2006.173.22:25:21.74#ibcon#about to read 6, iclass 25, count 0 2006.173.22:25:21.74#ibcon#read 6, iclass 25, count 0 2006.173.22:25:21.74#ibcon#end of sib2, iclass 25, count 0 2006.173.22:25:21.74#ibcon#*mode == 0, iclass 25, count 0 2006.173.22:25:21.74#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.22:25:21.74#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.22:25:21.74#ibcon#*before write, iclass 25, count 0 2006.173.22:25:21.74#ibcon#enter sib2, iclass 25, count 0 2006.173.22:25:21.74#ibcon#flushed, iclass 25, count 0 2006.173.22:25:21.74#ibcon#about to write, iclass 25, count 0 2006.173.22:25:21.74#ibcon#wrote, iclass 25, count 0 2006.173.22:25:21.74#ibcon#about to read 3, iclass 25, count 0 2006.173.22:25:21.78#ibcon#read 3, iclass 25, count 0 2006.173.22:25:21.78#ibcon#about to read 4, iclass 25, count 0 2006.173.22:25:21.78#ibcon#read 4, iclass 25, count 0 2006.173.22:25:21.78#ibcon#about to read 5, iclass 25, count 0 2006.173.22:25:21.78#ibcon#read 5, iclass 25, count 0 2006.173.22:25:21.78#ibcon#about to read 6, iclass 25, count 0 2006.173.22:25:21.78#ibcon#read 6, iclass 25, count 0 2006.173.22:25:21.78#ibcon#end of sib2, iclass 25, count 0 2006.173.22:25:21.78#ibcon#*after write, iclass 25, count 0 2006.173.22:25:21.78#ibcon#*before return 0, iclass 25, count 0 2006.173.22:25:21.78#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.22:25:21.78#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.22:25:21.78#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.22:25:21.78#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.22:25:21.79$vck44/va=3,5 2006.173.22:25:21.79#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.22:25:21.79#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.22:25:21.79#ibcon#ireg 11 cls_cnt 2 2006.173.22:25:21.79#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.22:25:21.83#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.22:25:21.83#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.22:25:21.83#ibcon#enter wrdev, iclass 27, count 2 2006.173.22:25:21.83#ibcon#first serial, iclass 27, count 2 2006.173.22:25:21.83#ibcon#enter sib2, iclass 27, count 2 2006.173.22:25:21.83#ibcon#flushed, iclass 27, count 2 2006.173.22:25:21.83#ibcon#about to write, iclass 27, count 2 2006.173.22:25:21.83#ibcon#wrote, iclass 27, count 2 2006.173.22:25:21.83#ibcon#about to read 3, iclass 27, count 2 2006.173.22:25:21.85#ibcon#read 3, iclass 27, count 2 2006.173.22:25:21.85#ibcon#about to read 4, iclass 27, count 2 2006.173.22:25:21.85#ibcon#read 4, iclass 27, count 2 2006.173.22:25:21.85#ibcon#about to read 5, iclass 27, count 2 2006.173.22:25:21.85#ibcon#read 5, iclass 27, count 2 2006.173.22:25:21.85#ibcon#about to read 6, iclass 27, count 2 2006.173.22:25:21.85#ibcon#read 6, iclass 27, count 2 2006.173.22:25:21.85#ibcon#end of sib2, iclass 27, count 2 2006.173.22:25:21.85#ibcon#*mode == 0, iclass 27, count 2 2006.173.22:25:21.85#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.22:25:21.85#ibcon#[25=AT03-05\r\n] 2006.173.22:25:21.85#ibcon#*before write, iclass 27, count 2 2006.173.22:25:21.85#ibcon#enter sib2, iclass 27, count 2 2006.173.22:25:21.85#ibcon#flushed, iclass 27, count 2 2006.173.22:25:21.85#ibcon#about to write, iclass 27, count 2 2006.173.22:25:21.85#ibcon#wrote, iclass 27, count 2 2006.173.22:25:21.85#ibcon#about to read 3, iclass 27, count 2 2006.173.22:25:21.88#ibcon#read 3, iclass 27, count 2 2006.173.22:25:21.88#ibcon#about to read 4, iclass 27, count 2 2006.173.22:25:21.88#ibcon#read 4, iclass 27, count 2 2006.173.22:25:21.88#ibcon#about to read 5, iclass 27, count 2 2006.173.22:25:21.88#ibcon#read 5, iclass 27, count 2 2006.173.22:25:21.88#ibcon#about to read 6, iclass 27, count 2 2006.173.22:25:21.88#ibcon#read 6, iclass 27, count 2 2006.173.22:25:21.88#ibcon#end of sib2, iclass 27, count 2 2006.173.22:25:21.88#ibcon#*after write, iclass 27, count 2 2006.173.22:25:21.88#ibcon#*before return 0, iclass 27, count 2 2006.173.22:25:21.88#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.22:25:21.88#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.22:25:21.88#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.22:25:21.88#ibcon#ireg 7 cls_cnt 0 2006.173.22:25:21.88#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.22:25:22.01#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.22:25:22.01#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.22:25:22.01#ibcon#enter wrdev, iclass 27, count 0 2006.173.22:25:22.01#ibcon#first serial, iclass 27, count 0 2006.173.22:25:22.01#ibcon#enter sib2, iclass 27, count 0 2006.173.22:25:22.01#ibcon#flushed, iclass 27, count 0 2006.173.22:25:22.01#ibcon#about to write, iclass 27, count 0 2006.173.22:25:22.01#ibcon#wrote, iclass 27, count 0 2006.173.22:25:22.01#ibcon#about to read 3, iclass 27, count 0 2006.173.22:25:22.02#ibcon#read 3, iclass 27, count 0 2006.173.22:25:22.02#ibcon#about to read 4, iclass 27, count 0 2006.173.22:25:22.02#ibcon#read 4, iclass 27, count 0 2006.173.22:25:22.02#ibcon#about to read 5, iclass 27, count 0 2006.173.22:25:22.02#ibcon#read 5, iclass 27, count 0 2006.173.22:25:22.02#ibcon#about to read 6, iclass 27, count 0 2006.173.22:25:22.02#ibcon#read 6, iclass 27, count 0 2006.173.22:25:22.02#ibcon#end of sib2, iclass 27, count 0 2006.173.22:25:22.02#ibcon#*mode == 0, iclass 27, count 0 2006.173.22:25:22.02#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.22:25:22.02#ibcon#[25=USB\r\n] 2006.173.22:25:22.02#ibcon#*before write, iclass 27, count 0 2006.173.22:25:22.02#ibcon#enter sib2, iclass 27, count 0 2006.173.22:25:22.02#ibcon#flushed, iclass 27, count 0 2006.173.22:25:22.02#ibcon#about to write, iclass 27, count 0 2006.173.22:25:22.02#ibcon#wrote, iclass 27, count 0 2006.173.22:25:22.02#ibcon#about to read 3, iclass 27, count 0 2006.173.22:25:22.05#ibcon#read 3, iclass 27, count 0 2006.173.22:25:22.05#ibcon#about to read 4, iclass 27, count 0 2006.173.22:25:22.05#ibcon#read 4, iclass 27, count 0 2006.173.22:25:22.05#ibcon#about to read 5, iclass 27, count 0 2006.173.22:25:22.05#ibcon#read 5, iclass 27, count 0 2006.173.22:25:22.05#ibcon#about to read 6, iclass 27, count 0 2006.173.22:25:22.05#ibcon#read 6, iclass 27, count 0 2006.173.22:25:22.05#ibcon#end of sib2, iclass 27, count 0 2006.173.22:25:22.05#ibcon#*after write, iclass 27, count 0 2006.173.22:25:22.05#ibcon#*before return 0, iclass 27, count 0 2006.173.22:25:22.05#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.22:25:22.05#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.22:25:22.05#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.22:25:22.05#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.22:25:22.06$vck44/valo=4,624.99 2006.173.22:25:22.06#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.22:25:22.06#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.22:25:22.06#ibcon#ireg 17 cls_cnt 0 2006.173.22:25:22.06#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.22:25:22.06#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.22:25:22.06#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.22:25:22.06#ibcon#enter wrdev, iclass 29, count 0 2006.173.22:25:22.06#ibcon#first serial, iclass 29, count 0 2006.173.22:25:22.06#ibcon#enter sib2, iclass 29, count 0 2006.173.22:25:22.06#ibcon#flushed, iclass 29, count 0 2006.173.22:25:22.06#ibcon#about to write, iclass 29, count 0 2006.173.22:25:22.06#ibcon#wrote, iclass 29, count 0 2006.173.22:25:22.06#ibcon#about to read 3, iclass 29, count 0 2006.173.22:25:22.07#ibcon#read 3, iclass 29, count 0 2006.173.22:25:22.07#ibcon#about to read 4, iclass 29, count 0 2006.173.22:25:22.07#ibcon#read 4, iclass 29, count 0 2006.173.22:25:22.07#ibcon#about to read 5, iclass 29, count 0 2006.173.22:25:22.07#ibcon#read 5, iclass 29, count 0 2006.173.22:25:22.07#ibcon#about to read 6, iclass 29, count 0 2006.173.22:25:22.07#ibcon#read 6, iclass 29, count 0 2006.173.22:25:22.07#ibcon#end of sib2, iclass 29, count 0 2006.173.22:25:22.07#ibcon#*mode == 0, iclass 29, count 0 2006.173.22:25:22.07#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.22:25:22.07#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.22:25:22.07#ibcon#*before write, iclass 29, count 0 2006.173.22:25:22.07#ibcon#enter sib2, iclass 29, count 0 2006.173.22:25:22.07#ibcon#flushed, iclass 29, count 0 2006.173.22:25:22.07#ibcon#about to write, iclass 29, count 0 2006.173.22:25:22.07#ibcon#wrote, iclass 29, count 0 2006.173.22:25:22.07#ibcon#about to read 3, iclass 29, count 0 2006.173.22:25:22.11#ibcon#read 3, iclass 29, count 0 2006.173.22:25:22.11#ibcon#about to read 4, iclass 29, count 0 2006.173.22:25:22.11#ibcon#read 4, iclass 29, count 0 2006.173.22:25:22.11#ibcon#about to read 5, iclass 29, count 0 2006.173.22:25:22.11#ibcon#read 5, iclass 29, count 0 2006.173.22:25:22.11#ibcon#about to read 6, iclass 29, count 0 2006.173.22:25:22.11#ibcon#read 6, iclass 29, count 0 2006.173.22:25:22.11#ibcon#end of sib2, iclass 29, count 0 2006.173.22:25:22.11#ibcon#*after write, iclass 29, count 0 2006.173.22:25:22.11#ibcon#*before return 0, iclass 29, count 0 2006.173.22:25:22.11#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.22:25:22.11#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.22:25:22.11#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.22:25:22.11#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.22:25:22.12$vck44/va=4,6 2006.173.22:25:22.12#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.22:25:22.12#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.22:25:22.12#ibcon#ireg 11 cls_cnt 2 2006.173.22:25:22.12#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.22:25:22.16#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.22:25:22.16#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.22:25:22.16#ibcon#enter wrdev, iclass 31, count 2 2006.173.22:25:22.16#ibcon#first serial, iclass 31, count 2 2006.173.22:25:22.16#ibcon#enter sib2, iclass 31, count 2 2006.173.22:25:22.16#ibcon#flushed, iclass 31, count 2 2006.173.22:25:22.16#ibcon#about to write, iclass 31, count 2 2006.173.22:25:22.16#ibcon#wrote, iclass 31, count 2 2006.173.22:25:22.16#ibcon#about to read 3, iclass 31, count 2 2006.173.22:25:22.18#ibcon#read 3, iclass 31, count 2 2006.173.22:25:22.18#ibcon#about to read 4, iclass 31, count 2 2006.173.22:25:22.18#ibcon#read 4, iclass 31, count 2 2006.173.22:25:22.18#ibcon#about to read 5, iclass 31, count 2 2006.173.22:25:22.18#ibcon#read 5, iclass 31, count 2 2006.173.22:25:22.18#ibcon#about to read 6, iclass 31, count 2 2006.173.22:25:22.18#ibcon#read 6, iclass 31, count 2 2006.173.22:25:22.18#ibcon#end of sib2, iclass 31, count 2 2006.173.22:25:22.18#ibcon#*mode == 0, iclass 31, count 2 2006.173.22:25:22.18#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.22:25:22.18#ibcon#[25=AT04-06\r\n] 2006.173.22:25:22.18#ibcon#*before write, iclass 31, count 2 2006.173.22:25:22.18#ibcon#enter sib2, iclass 31, count 2 2006.173.22:25:22.18#ibcon#flushed, iclass 31, count 2 2006.173.22:25:22.18#ibcon#about to write, iclass 31, count 2 2006.173.22:25:22.18#ibcon#wrote, iclass 31, count 2 2006.173.22:25:22.18#ibcon#about to read 3, iclass 31, count 2 2006.173.22:25:22.21#ibcon#read 3, iclass 31, count 2 2006.173.22:25:22.21#ibcon#about to read 4, iclass 31, count 2 2006.173.22:25:22.21#ibcon#read 4, iclass 31, count 2 2006.173.22:25:22.21#ibcon#about to read 5, iclass 31, count 2 2006.173.22:25:22.21#ibcon#read 5, iclass 31, count 2 2006.173.22:25:22.21#ibcon#about to read 6, iclass 31, count 2 2006.173.22:25:22.21#ibcon#read 6, iclass 31, count 2 2006.173.22:25:22.21#ibcon#end of sib2, iclass 31, count 2 2006.173.22:25:22.21#ibcon#*after write, iclass 31, count 2 2006.173.22:25:22.21#ibcon#*before return 0, iclass 31, count 2 2006.173.22:25:22.21#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.22:25:22.21#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.22:25:22.21#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.22:25:22.21#ibcon#ireg 7 cls_cnt 0 2006.173.22:25:22.21#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.22:25:22.33#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.22:25:22.33#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.22:25:22.33#ibcon#enter wrdev, iclass 31, count 0 2006.173.22:25:22.33#ibcon#first serial, iclass 31, count 0 2006.173.22:25:22.33#ibcon#enter sib2, iclass 31, count 0 2006.173.22:25:22.33#ibcon#flushed, iclass 31, count 0 2006.173.22:25:22.33#ibcon#about to write, iclass 31, count 0 2006.173.22:25:22.33#ibcon#wrote, iclass 31, count 0 2006.173.22:25:22.33#ibcon#about to read 3, iclass 31, count 0 2006.173.22:25:22.35#ibcon#read 3, iclass 31, count 0 2006.173.22:25:22.35#ibcon#about to read 4, iclass 31, count 0 2006.173.22:25:22.35#ibcon#read 4, iclass 31, count 0 2006.173.22:25:22.35#ibcon#about to read 5, iclass 31, count 0 2006.173.22:25:22.35#ibcon#read 5, iclass 31, count 0 2006.173.22:25:22.35#ibcon#about to read 6, iclass 31, count 0 2006.173.22:25:22.35#ibcon#read 6, iclass 31, count 0 2006.173.22:25:22.35#ibcon#end of sib2, iclass 31, count 0 2006.173.22:25:22.35#ibcon#*mode == 0, iclass 31, count 0 2006.173.22:25:22.35#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.22:25:22.35#ibcon#[25=USB\r\n] 2006.173.22:25:22.35#ibcon#*before write, iclass 31, count 0 2006.173.22:25:22.35#ibcon#enter sib2, iclass 31, count 0 2006.173.22:25:22.35#ibcon#flushed, iclass 31, count 0 2006.173.22:25:22.35#ibcon#about to write, iclass 31, count 0 2006.173.22:25:22.35#ibcon#wrote, iclass 31, count 0 2006.173.22:25:22.35#ibcon#about to read 3, iclass 31, count 0 2006.173.22:25:22.38#ibcon#read 3, iclass 31, count 0 2006.173.22:25:22.38#ibcon#about to read 4, iclass 31, count 0 2006.173.22:25:22.38#ibcon#read 4, iclass 31, count 0 2006.173.22:25:22.38#ibcon#about to read 5, iclass 31, count 0 2006.173.22:25:22.38#ibcon#read 5, iclass 31, count 0 2006.173.22:25:22.38#ibcon#about to read 6, iclass 31, count 0 2006.173.22:25:22.38#ibcon#read 6, iclass 31, count 0 2006.173.22:25:22.38#ibcon#end of sib2, iclass 31, count 0 2006.173.22:25:22.38#ibcon#*after write, iclass 31, count 0 2006.173.22:25:22.38#ibcon#*before return 0, iclass 31, count 0 2006.173.22:25:22.38#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.22:25:22.38#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.22:25:22.38#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.22:25:22.38#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.22:25:22.39$vck44/valo=5,734.99 2006.173.22:25:22.39#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.22:25:22.39#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.22:25:22.39#ibcon#ireg 17 cls_cnt 0 2006.173.22:25:22.39#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.22:25:22.39#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.22:25:22.39#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.22:25:22.39#ibcon#enter wrdev, iclass 33, count 0 2006.173.22:25:22.39#ibcon#first serial, iclass 33, count 0 2006.173.22:25:22.39#ibcon#enter sib2, iclass 33, count 0 2006.173.22:25:22.39#ibcon#flushed, iclass 33, count 0 2006.173.22:25:22.39#ibcon#about to write, iclass 33, count 0 2006.173.22:25:22.39#ibcon#wrote, iclass 33, count 0 2006.173.22:25:22.39#ibcon#about to read 3, iclass 33, count 0 2006.173.22:25:22.40#ibcon#read 3, iclass 33, count 0 2006.173.22:25:22.40#ibcon#about to read 4, iclass 33, count 0 2006.173.22:25:22.40#ibcon#read 4, iclass 33, count 0 2006.173.22:25:22.40#ibcon#about to read 5, iclass 33, count 0 2006.173.22:25:22.40#ibcon#read 5, iclass 33, count 0 2006.173.22:25:22.40#ibcon#about to read 6, iclass 33, count 0 2006.173.22:25:22.40#ibcon#read 6, iclass 33, count 0 2006.173.22:25:22.40#ibcon#end of sib2, iclass 33, count 0 2006.173.22:25:22.40#ibcon#*mode == 0, iclass 33, count 0 2006.173.22:25:22.40#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.22:25:22.40#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.22:25:22.40#ibcon#*before write, iclass 33, count 0 2006.173.22:25:22.40#ibcon#enter sib2, iclass 33, count 0 2006.173.22:25:22.40#ibcon#flushed, iclass 33, count 0 2006.173.22:25:22.40#ibcon#about to write, iclass 33, count 0 2006.173.22:25:22.40#ibcon#wrote, iclass 33, count 0 2006.173.22:25:22.40#ibcon#about to read 3, iclass 33, count 0 2006.173.22:25:22.44#ibcon#read 3, iclass 33, count 0 2006.173.22:25:22.44#ibcon#about to read 4, iclass 33, count 0 2006.173.22:25:22.44#ibcon#read 4, iclass 33, count 0 2006.173.22:25:22.44#ibcon#about to read 5, iclass 33, count 0 2006.173.22:25:22.44#ibcon#read 5, iclass 33, count 0 2006.173.22:25:22.44#ibcon#about to read 6, iclass 33, count 0 2006.173.22:25:22.44#ibcon#read 6, iclass 33, count 0 2006.173.22:25:22.44#ibcon#end of sib2, iclass 33, count 0 2006.173.22:25:22.44#ibcon#*after write, iclass 33, count 0 2006.173.22:25:22.44#ibcon#*before return 0, iclass 33, count 0 2006.173.22:25:22.44#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.22:25:22.44#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.22:25:22.44#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.22:25:22.44#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.22:25:22.45$vck44/va=5,4 2006.173.22:25:22.45#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.22:25:22.45#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.22:25:22.45#ibcon#ireg 11 cls_cnt 2 2006.173.22:25:22.45#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.22:25:22.49#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.22:25:22.49#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.22:25:22.49#ibcon#enter wrdev, iclass 35, count 2 2006.173.22:25:22.49#ibcon#first serial, iclass 35, count 2 2006.173.22:25:22.49#ibcon#enter sib2, iclass 35, count 2 2006.173.22:25:22.49#ibcon#flushed, iclass 35, count 2 2006.173.22:25:22.49#ibcon#about to write, iclass 35, count 2 2006.173.22:25:22.49#ibcon#wrote, iclass 35, count 2 2006.173.22:25:22.49#ibcon#about to read 3, iclass 35, count 2 2006.173.22:25:22.51#ibcon#read 3, iclass 35, count 2 2006.173.22:25:22.51#ibcon#about to read 4, iclass 35, count 2 2006.173.22:25:22.51#ibcon#read 4, iclass 35, count 2 2006.173.22:25:22.51#ibcon#about to read 5, iclass 35, count 2 2006.173.22:25:22.51#ibcon#read 5, iclass 35, count 2 2006.173.22:25:22.51#ibcon#about to read 6, iclass 35, count 2 2006.173.22:25:22.51#ibcon#read 6, iclass 35, count 2 2006.173.22:25:22.51#ibcon#end of sib2, iclass 35, count 2 2006.173.22:25:22.51#ibcon#*mode == 0, iclass 35, count 2 2006.173.22:25:22.51#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.22:25:22.51#ibcon#[25=AT05-04\r\n] 2006.173.22:25:22.51#ibcon#*before write, iclass 35, count 2 2006.173.22:25:22.51#ibcon#enter sib2, iclass 35, count 2 2006.173.22:25:22.51#ibcon#flushed, iclass 35, count 2 2006.173.22:25:22.51#ibcon#about to write, iclass 35, count 2 2006.173.22:25:22.51#ibcon#wrote, iclass 35, count 2 2006.173.22:25:22.51#ibcon#about to read 3, iclass 35, count 2 2006.173.22:25:22.54#ibcon#read 3, iclass 35, count 2 2006.173.22:25:22.54#ibcon#about to read 4, iclass 35, count 2 2006.173.22:25:22.54#ibcon#read 4, iclass 35, count 2 2006.173.22:25:22.54#ibcon#about to read 5, iclass 35, count 2 2006.173.22:25:22.54#ibcon#read 5, iclass 35, count 2 2006.173.22:25:22.54#ibcon#about to read 6, iclass 35, count 2 2006.173.22:25:22.54#ibcon#read 6, iclass 35, count 2 2006.173.22:25:22.54#ibcon#end of sib2, iclass 35, count 2 2006.173.22:25:22.54#ibcon#*after write, iclass 35, count 2 2006.173.22:25:22.54#ibcon#*before return 0, iclass 35, count 2 2006.173.22:25:22.54#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.22:25:22.54#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.22:25:22.54#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.22:25:22.54#ibcon#ireg 7 cls_cnt 0 2006.173.22:25:22.54#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.22:25:22.66#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.22:25:22.66#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.22:25:22.66#ibcon#enter wrdev, iclass 35, count 0 2006.173.22:25:22.66#ibcon#first serial, iclass 35, count 0 2006.173.22:25:22.66#ibcon#enter sib2, iclass 35, count 0 2006.173.22:25:22.66#ibcon#flushed, iclass 35, count 0 2006.173.22:25:22.66#ibcon#about to write, iclass 35, count 0 2006.173.22:25:22.66#ibcon#wrote, iclass 35, count 0 2006.173.22:25:22.66#ibcon#about to read 3, iclass 35, count 0 2006.173.22:25:22.68#ibcon#read 3, iclass 35, count 0 2006.173.22:25:22.68#ibcon#about to read 4, iclass 35, count 0 2006.173.22:25:22.68#ibcon#read 4, iclass 35, count 0 2006.173.22:25:22.68#ibcon#about to read 5, iclass 35, count 0 2006.173.22:25:22.68#ibcon#read 5, iclass 35, count 0 2006.173.22:25:22.68#ibcon#about to read 6, iclass 35, count 0 2006.173.22:25:22.68#ibcon#read 6, iclass 35, count 0 2006.173.22:25:22.68#ibcon#end of sib2, iclass 35, count 0 2006.173.22:25:22.68#ibcon#*mode == 0, iclass 35, count 0 2006.173.22:25:22.68#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.22:25:22.68#ibcon#[25=USB\r\n] 2006.173.22:25:22.68#ibcon#*before write, iclass 35, count 0 2006.173.22:25:22.68#ibcon#enter sib2, iclass 35, count 0 2006.173.22:25:22.68#ibcon#flushed, iclass 35, count 0 2006.173.22:25:22.68#ibcon#about to write, iclass 35, count 0 2006.173.22:25:22.68#ibcon#wrote, iclass 35, count 0 2006.173.22:25:22.68#ibcon#about to read 3, iclass 35, count 0 2006.173.22:25:22.71#ibcon#read 3, iclass 35, count 0 2006.173.22:25:22.71#ibcon#about to read 4, iclass 35, count 0 2006.173.22:25:22.71#ibcon#read 4, iclass 35, count 0 2006.173.22:25:22.71#ibcon#about to read 5, iclass 35, count 0 2006.173.22:25:22.71#ibcon#read 5, iclass 35, count 0 2006.173.22:25:22.71#ibcon#about to read 6, iclass 35, count 0 2006.173.22:25:22.71#ibcon#read 6, iclass 35, count 0 2006.173.22:25:22.71#ibcon#end of sib2, iclass 35, count 0 2006.173.22:25:22.71#ibcon#*after write, iclass 35, count 0 2006.173.22:25:22.71#ibcon#*before return 0, iclass 35, count 0 2006.173.22:25:22.71#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.22:25:22.71#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.22:25:22.71#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.22:25:22.71#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.22:25:22.72$vck44/valo=6,814.99 2006.173.22:25:22.72#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.22:25:22.72#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.22:25:22.72#ibcon#ireg 17 cls_cnt 0 2006.173.22:25:22.72#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.22:25:22.72#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.22:25:22.72#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.22:25:22.72#ibcon#enter wrdev, iclass 37, count 0 2006.173.22:25:22.72#ibcon#first serial, iclass 37, count 0 2006.173.22:25:22.72#ibcon#enter sib2, iclass 37, count 0 2006.173.22:25:22.72#ibcon#flushed, iclass 37, count 0 2006.173.22:25:22.72#ibcon#about to write, iclass 37, count 0 2006.173.22:25:22.72#ibcon#wrote, iclass 37, count 0 2006.173.22:25:22.72#ibcon#about to read 3, iclass 37, count 0 2006.173.22:25:22.73#ibcon#read 3, iclass 37, count 0 2006.173.22:25:22.73#ibcon#about to read 4, iclass 37, count 0 2006.173.22:25:22.73#ibcon#read 4, iclass 37, count 0 2006.173.22:25:22.73#ibcon#about to read 5, iclass 37, count 0 2006.173.22:25:22.73#ibcon#read 5, iclass 37, count 0 2006.173.22:25:22.73#ibcon#about to read 6, iclass 37, count 0 2006.173.22:25:22.73#ibcon#read 6, iclass 37, count 0 2006.173.22:25:22.73#ibcon#end of sib2, iclass 37, count 0 2006.173.22:25:22.73#ibcon#*mode == 0, iclass 37, count 0 2006.173.22:25:22.73#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.22:25:22.73#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.22:25:22.73#ibcon#*before write, iclass 37, count 0 2006.173.22:25:22.73#ibcon#enter sib2, iclass 37, count 0 2006.173.22:25:22.73#ibcon#flushed, iclass 37, count 0 2006.173.22:25:22.73#ibcon#about to write, iclass 37, count 0 2006.173.22:25:22.73#ibcon#wrote, iclass 37, count 0 2006.173.22:25:22.73#ibcon#about to read 3, iclass 37, count 0 2006.173.22:25:22.77#ibcon#read 3, iclass 37, count 0 2006.173.22:25:22.77#ibcon#about to read 4, iclass 37, count 0 2006.173.22:25:22.77#ibcon#read 4, iclass 37, count 0 2006.173.22:25:22.77#ibcon#about to read 5, iclass 37, count 0 2006.173.22:25:22.77#ibcon#read 5, iclass 37, count 0 2006.173.22:25:22.77#ibcon#about to read 6, iclass 37, count 0 2006.173.22:25:22.77#ibcon#read 6, iclass 37, count 0 2006.173.22:25:22.77#ibcon#end of sib2, iclass 37, count 0 2006.173.22:25:22.77#ibcon#*after write, iclass 37, count 0 2006.173.22:25:22.77#ibcon#*before return 0, iclass 37, count 0 2006.173.22:25:22.77#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.22:25:22.77#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.22:25:22.77#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.22:25:22.77#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.22:25:22.78$vck44/va=6,3 2006.173.22:25:22.78#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.22:25:22.78#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.22:25:22.78#ibcon#ireg 11 cls_cnt 2 2006.173.22:25:22.78#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.22:25:22.82#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.22:25:22.82#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.22:25:22.82#ibcon#enter wrdev, iclass 39, count 2 2006.173.22:25:22.82#ibcon#first serial, iclass 39, count 2 2006.173.22:25:22.82#ibcon#enter sib2, iclass 39, count 2 2006.173.22:25:22.82#ibcon#flushed, iclass 39, count 2 2006.173.22:25:22.82#ibcon#about to write, iclass 39, count 2 2006.173.22:25:22.82#ibcon#wrote, iclass 39, count 2 2006.173.22:25:22.82#ibcon#about to read 3, iclass 39, count 2 2006.173.22:25:22.84#ibcon#read 3, iclass 39, count 2 2006.173.22:25:22.84#ibcon#about to read 4, iclass 39, count 2 2006.173.22:25:22.84#ibcon#read 4, iclass 39, count 2 2006.173.22:25:22.84#ibcon#about to read 5, iclass 39, count 2 2006.173.22:25:22.84#ibcon#read 5, iclass 39, count 2 2006.173.22:25:22.84#ibcon#about to read 6, iclass 39, count 2 2006.173.22:25:22.84#ibcon#read 6, iclass 39, count 2 2006.173.22:25:22.84#ibcon#end of sib2, iclass 39, count 2 2006.173.22:25:22.84#ibcon#*mode == 0, iclass 39, count 2 2006.173.22:25:22.84#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.22:25:22.84#ibcon#[25=AT06-03\r\n] 2006.173.22:25:22.84#ibcon#*before write, iclass 39, count 2 2006.173.22:25:22.84#ibcon#enter sib2, iclass 39, count 2 2006.173.22:25:22.84#ibcon#flushed, iclass 39, count 2 2006.173.22:25:22.84#ibcon#about to write, iclass 39, count 2 2006.173.22:25:22.84#ibcon#wrote, iclass 39, count 2 2006.173.22:25:22.84#ibcon#about to read 3, iclass 39, count 2 2006.173.22:25:22.87#ibcon#read 3, iclass 39, count 2 2006.173.22:25:22.87#ibcon#about to read 4, iclass 39, count 2 2006.173.22:25:22.87#ibcon#read 4, iclass 39, count 2 2006.173.22:25:22.87#ibcon#about to read 5, iclass 39, count 2 2006.173.22:25:22.87#ibcon#read 5, iclass 39, count 2 2006.173.22:25:22.87#ibcon#about to read 6, iclass 39, count 2 2006.173.22:25:22.87#ibcon#read 6, iclass 39, count 2 2006.173.22:25:22.87#ibcon#end of sib2, iclass 39, count 2 2006.173.22:25:22.87#ibcon#*after write, iclass 39, count 2 2006.173.22:25:22.87#ibcon#*before return 0, iclass 39, count 2 2006.173.22:25:22.87#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.22:25:22.87#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.22:25:22.87#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.22:25:22.87#ibcon#ireg 7 cls_cnt 0 2006.173.22:25:22.87#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.22:25:22.99#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.22:25:22.99#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.22:25:22.99#ibcon#enter wrdev, iclass 39, count 0 2006.173.22:25:22.99#ibcon#first serial, iclass 39, count 0 2006.173.22:25:22.99#ibcon#enter sib2, iclass 39, count 0 2006.173.22:25:22.99#ibcon#flushed, iclass 39, count 0 2006.173.22:25:22.99#ibcon#about to write, iclass 39, count 0 2006.173.22:25:22.99#ibcon#wrote, iclass 39, count 0 2006.173.22:25:22.99#ibcon#about to read 3, iclass 39, count 0 2006.173.22:25:23.01#ibcon#read 3, iclass 39, count 0 2006.173.22:25:23.01#ibcon#about to read 4, iclass 39, count 0 2006.173.22:25:23.01#ibcon#read 4, iclass 39, count 0 2006.173.22:25:23.01#ibcon#about to read 5, iclass 39, count 0 2006.173.22:25:23.01#ibcon#read 5, iclass 39, count 0 2006.173.22:25:23.01#ibcon#about to read 6, iclass 39, count 0 2006.173.22:25:23.01#ibcon#read 6, iclass 39, count 0 2006.173.22:25:23.01#ibcon#end of sib2, iclass 39, count 0 2006.173.22:25:23.01#ibcon#*mode == 0, iclass 39, count 0 2006.173.22:25:23.01#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.22:25:23.01#ibcon#[25=USB\r\n] 2006.173.22:25:23.01#ibcon#*before write, iclass 39, count 0 2006.173.22:25:23.01#ibcon#enter sib2, iclass 39, count 0 2006.173.22:25:23.01#ibcon#flushed, iclass 39, count 0 2006.173.22:25:23.01#ibcon#about to write, iclass 39, count 0 2006.173.22:25:23.01#ibcon#wrote, iclass 39, count 0 2006.173.22:25:23.01#ibcon#about to read 3, iclass 39, count 0 2006.173.22:25:23.04#ibcon#read 3, iclass 39, count 0 2006.173.22:25:23.04#ibcon#about to read 4, iclass 39, count 0 2006.173.22:25:23.04#ibcon#read 4, iclass 39, count 0 2006.173.22:25:23.04#ibcon#about to read 5, iclass 39, count 0 2006.173.22:25:23.04#ibcon#read 5, iclass 39, count 0 2006.173.22:25:23.04#ibcon#about to read 6, iclass 39, count 0 2006.173.22:25:23.04#ibcon#read 6, iclass 39, count 0 2006.173.22:25:23.04#ibcon#end of sib2, iclass 39, count 0 2006.173.22:25:23.04#ibcon#*after write, iclass 39, count 0 2006.173.22:25:23.04#ibcon#*before return 0, iclass 39, count 0 2006.173.22:25:23.04#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.22:25:23.04#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.22:25:23.04#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.22:25:23.04#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.22:25:23.05$vck44/valo=7,864.99 2006.173.22:25:23.05#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.22:25:23.05#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.22:25:23.05#ibcon#ireg 17 cls_cnt 0 2006.173.22:25:23.05#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.22:25:23.05#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.22:25:23.05#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.22:25:23.05#ibcon#enter wrdev, iclass 3, count 0 2006.173.22:25:23.05#ibcon#first serial, iclass 3, count 0 2006.173.22:25:23.05#ibcon#enter sib2, iclass 3, count 0 2006.173.22:25:23.05#ibcon#flushed, iclass 3, count 0 2006.173.22:25:23.05#ibcon#about to write, iclass 3, count 0 2006.173.22:25:23.05#ibcon#wrote, iclass 3, count 0 2006.173.22:25:23.05#ibcon#about to read 3, iclass 3, count 0 2006.173.22:25:23.06#ibcon#read 3, iclass 3, count 0 2006.173.22:25:23.06#ibcon#about to read 4, iclass 3, count 0 2006.173.22:25:23.06#ibcon#read 4, iclass 3, count 0 2006.173.22:25:23.06#ibcon#about to read 5, iclass 3, count 0 2006.173.22:25:23.06#ibcon#read 5, iclass 3, count 0 2006.173.22:25:23.06#ibcon#about to read 6, iclass 3, count 0 2006.173.22:25:23.06#ibcon#read 6, iclass 3, count 0 2006.173.22:25:23.06#ibcon#end of sib2, iclass 3, count 0 2006.173.22:25:23.06#ibcon#*mode == 0, iclass 3, count 0 2006.173.22:25:23.06#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.22:25:23.06#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.22:25:23.06#ibcon#*before write, iclass 3, count 0 2006.173.22:25:23.06#ibcon#enter sib2, iclass 3, count 0 2006.173.22:25:23.06#ibcon#flushed, iclass 3, count 0 2006.173.22:25:23.06#ibcon#about to write, iclass 3, count 0 2006.173.22:25:23.06#ibcon#wrote, iclass 3, count 0 2006.173.22:25:23.06#ibcon#about to read 3, iclass 3, count 0 2006.173.22:25:23.10#ibcon#read 3, iclass 3, count 0 2006.173.22:25:23.10#ibcon#about to read 4, iclass 3, count 0 2006.173.22:25:23.10#ibcon#read 4, iclass 3, count 0 2006.173.22:25:23.10#ibcon#about to read 5, iclass 3, count 0 2006.173.22:25:23.10#ibcon#read 5, iclass 3, count 0 2006.173.22:25:23.10#ibcon#about to read 6, iclass 3, count 0 2006.173.22:25:23.10#ibcon#read 6, iclass 3, count 0 2006.173.22:25:23.10#ibcon#end of sib2, iclass 3, count 0 2006.173.22:25:23.10#ibcon#*after write, iclass 3, count 0 2006.173.22:25:23.10#ibcon#*before return 0, iclass 3, count 0 2006.173.22:25:23.10#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.22:25:23.10#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.22:25:23.10#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.22:25:23.10#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.22:25:23.11$vck44/va=7,4 2006.173.22:25:23.11#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.22:25:23.11#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.22:25:23.11#ibcon#ireg 11 cls_cnt 2 2006.173.22:25:23.11#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.22:25:23.15#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.22:25:23.15#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.22:25:23.15#ibcon#enter wrdev, iclass 5, count 2 2006.173.22:25:23.15#ibcon#first serial, iclass 5, count 2 2006.173.22:25:23.15#ibcon#enter sib2, iclass 5, count 2 2006.173.22:25:23.15#ibcon#flushed, iclass 5, count 2 2006.173.22:25:23.15#ibcon#about to write, iclass 5, count 2 2006.173.22:25:23.15#ibcon#wrote, iclass 5, count 2 2006.173.22:25:23.15#ibcon#about to read 3, iclass 5, count 2 2006.173.22:25:23.17#ibcon#read 3, iclass 5, count 2 2006.173.22:25:23.17#ibcon#about to read 4, iclass 5, count 2 2006.173.22:25:23.17#ibcon#read 4, iclass 5, count 2 2006.173.22:25:23.17#ibcon#about to read 5, iclass 5, count 2 2006.173.22:25:23.17#ibcon#read 5, iclass 5, count 2 2006.173.22:25:23.17#ibcon#about to read 6, iclass 5, count 2 2006.173.22:25:23.17#ibcon#read 6, iclass 5, count 2 2006.173.22:25:23.17#ibcon#end of sib2, iclass 5, count 2 2006.173.22:25:23.17#ibcon#*mode == 0, iclass 5, count 2 2006.173.22:25:23.17#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.22:25:23.17#ibcon#[25=AT07-04\r\n] 2006.173.22:25:23.17#ibcon#*before write, iclass 5, count 2 2006.173.22:25:23.17#ibcon#enter sib2, iclass 5, count 2 2006.173.22:25:23.17#ibcon#flushed, iclass 5, count 2 2006.173.22:25:23.17#ibcon#about to write, iclass 5, count 2 2006.173.22:25:23.17#ibcon#wrote, iclass 5, count 2 2006.173.22:25:23.17#ibcon#about to read 3, iclass 5, count 2 2006.173.22:25:23.20#ibcon#read 3, iclass 5, count 2 2006.173.22:25:23.20#ibcon#about to read 4, iclass 5, count 2 2006.173.22:25:23.20#ibcon#read 4, iclass 5, count 2 2006.173.22:25:23.20#ibcon#about to read 5, iclass 5, count 2 2006.173.22:25:23.20#ibcon#read 5, iclass 5, count 2 2006.173.22:25:23.20#ibcon#about to read 6, iclass 5, count 2 2006.173.22:25:23.20#ibcon#read 6, iclass 5, count 2 2006.173.22:25:23.20#ibcon#end of sib2, iclass 5, count 2 2006.173.22:25:23.20#ibcon#*after write, iclass 5, count 2 2006.173.22:25:23.20#ibcon#*before return 0, iclass 5, count 2 2006.173.22:25:23.20#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.22:25:23.20#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.22:25:23.20#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.22:25:23.20#ibcon#ireg 7 cls_cnt 0 2006.173.22:25:23.20#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.22:25:23.32#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.22:25:23.32#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.22:25:23.32#ibcon#enter wrdev, iclass 5, count 0 2006.173.22:25:23.32#ibcon#first serial, iclass 5, count 0 2006.173.22:25:23.32#ibcon#enter sib2, iclass 5, count 0 2006.173.22:25:23.32#ibcon#flushed, iclass 5, count 0 2006.173.22:25:23.32#ibcon#about to write, iclass 5, count 0 2006.173.22:25:23.32#ibcon#wrote, iclass 5, count 0 2006.173.22:25:23.32#ibcon#about to read 3, iclass 5, count 0 2006.173.22:25:23.34#ibcon#read 3, iclass 5, count 0 2006.173.22:25:23.34#ibcon#about to read 4, iclass 5, count 0 2006.173.22:25:23.34#ibcon#read 4, iclass 5, count 0 2006.173.22:25:23.34#ibcon#about to read 5, iclass 5, count 0 2006.173.22:25:23.34#ibcon#read 5, iclass 5, count 0 2006.173.22:25:23.34#ibcon#about to read 6, iclass 5, count 0 2006.173.22:25:23.34#ibcon#read 6, iclass 5, count 0 2006.173.22:25:23.34#ibcon#end of sib2, iclass 5, count 0 2006.173.22:25:23.34#ibcon#*mode == 0, iclass 5, count 0 2006.173.22:25:23.34#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.22:25:23.34#ibcon#[25=USB\r\n] 2006.173.22:25:23.34#ibcon#*before write, iclass 5, count 0 2006.173.22:25:23.34#ibcon#enter sib2, iclass 5, count 0 2006.173.22:25:23.34#ibcon#flushed, iclass 5, count 0 2006.173.22:25:23.34#ibcon#about to write, iclass 5, count 0 2006.173.22:25:23.34#ibcon#wrote, iclass 5, count 0 2006.173.22:25:23.34#ibcon#about to read 3, iclass 5, count 0 2006.173.22:25:23.37#ibcon#read 3, iclass 5, count 0 2006.173.22:25:23.37#ibcon#about to read 4, iclass 5, count 0 2006.173.22:25:23.37#ibcon#read 4, iclass 5, count 0 2006.173.22:25:23.37#ibcon#about to read 5, iclass 5, count 0 2006.173.22:25:23.37#ibcon#read 5, iclass 5, count 0 2006.173.22:25:23.37#ibcon#about to read 6, iclass 5, count 0 2006.173.22:25:23.37#ibcon#read 6, iclass 5, count 0 2006.173.22:25:23.37#ibcon#end of sib2, iclass 5, count 0 2006.173.22:25:23.37#ibcon#*after write, iclass 5, count 0 2006.173.22:25:23.37#ibcon#*before return 0, iclass 5, count 0 2006.173.22:25:23.37#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.22:25:23.37#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.22:25:23.37#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.22:25:23.37#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.22:25:23.38$vck44/valo=8,884.99 2006.173.22:25:23.38#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.22:25:23.38#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.22:25:23.38#ibcon#ireg 17 cls_cnt 0 2006.173.22:25:23.38#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.22:25:23.38#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.22:25:23.38#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.22:25:23.38#ibcon#enter wrdev, iclass 7, count 0 2006.173.22:25:23.38#ibcon#first serial, iclass 7, count 0 2006.173.22:25:23.38#ibcon#enter sib2, iclass 7, count 0 2006.173.22:25:23.38#ibcon#flushed, iclass 7, count 0 2006.173.22:25:23.38#ibcon#about to write, iclass 7, count 0 2006.173.22:25:23.38#ibcon#wrote, iclass 7, count 0 2006.173.22:25:23.38#ibcon#about to read 3, iclass 7, count 0 2006.173.22:25:23.39#ibcon#read 3, iclass 7, count 0 2006.173.22:25:23.39#ibcon#about to read 4, iclass 7, count 0 2006.173.22:25:23.39#ibcon#read 4, iclass 7, count 0 2006.173.22:25:23.39#ibcon#about to read 5, iclass 7, count 0 2006.173.22:25:23.39#ibcon#read 5, iclass 7, count 0 2006.173.22:25:23.39#ibcon#about to read 6, iclass 7, count 0 2006.173.22:25:23.39#ibcon#read 6, iclass 7, count 0 2006.173.22:25:23.39#ibcon#end of sib2, iclass 7, count 0 2006.173.22:25:23.39#ibcon#*mode == 0, iclass 7, count 0 2006.173.22:25:23.39#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.22:25:23.39#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.22:25:23.39#ibcon#*before write, iclass 7, count 0 2006.173.22:25:23.39#ibcon#enter sib2, iclass 7, count 0 2006.173.22:25:23.39#ibcon#flushed, iclass 7, count 0 2006.173.22:25:23.39#ibcon#about to write, iclass 7, count 0 2006.173.22:25:23.39#ibcon#wrote, iclass 7, count 0 2006.173.22:25:23.39#ibcon#about to read 3, iclass 7, count 0 2006.173.22:25:23.43#ibcon#read 3, iclass 7, count 0 2006.173.22:25:23.43#ibcon#about to read 4, iclass 7, count 0 2006.173.22:25:23.43#ibcon#read 4, iclass 7, count 0 2006.173.22:25:23.43#ibcon#about to read 5, iclass 7, count 0 2006.173.22:25:23.43#ibcon#read 5, iclass 7, count 0 2006.173.22:25:23.43#ibcon#about to read 6, iclass 7, count 0 2006.173.22:25:23.43#ibcon#read 6, iclass 7, count 0 2006.173.22:25:23.43#ibcon#end of sib2, iclass 7, count 0 2006.173.22:25:23.43#ibcon#*after write, iclass 7, count 0 2006.173.22:25:23.43#ibcon#*before return 0, iclass 7, count 0 2006.173.22:25:23.43#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.22:25:23.43#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.22:25:23.43#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.22:25:23.43#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.22:25:23.44$vck44/va=8,4 2006.173.22:25:23.44#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.22:25:23.44#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.22:25:23.44#ibcon#ireg 11 cls_cnt 2 2006.173.22:25:23.44#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.22:25:23.48#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.22:25:23.48#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.22:25:23.48#ibcon#enter wrdev, iclass 11, count 2 2006.173.22:25:23.48#ibcon#first serial, iclass 11, count 2 2006.173.22:25:23.48#ibcon#enter sib2, iclass 11, count 2 2006.173.22:25:23.48#ibcon#flushed, iclass 11, count 2 2006.173.22:25:23.48#ibcon#about to write, iclass 11, count 2 2006.173.22:25:23.48#ibcon#wrote, iclass 11, count 2 2006.173.22:25:23.48#ibcon#about to read 3, iclass 11, count 2 2006.173.22:25:23.50#ibcon#read 3, iclass 11, count 2 2006.173.22:25:23.50#ibcon#about to read 4, iclass 11, count 2 2006.173.22:25:23.50#ibcon#read 4, iclass 11, count 2 2006.173.22:25:23.50#ibcon#about to read 5, iclass 11, count 2 2006.173.22:25:23.50#ibcon#read 5, iclass 11, count 2 2006.173.22:25:23.50#ibcon#about to read 6, iclass 11, count 2 2006.173.22:25:23.50#ibcon#read 6, iclass 11, count 2 2006.173.22:25:23.50#ibcon#end of sib2, iclass 11, count 2 2006.173.22:25:23.50#ibcon#*mode == 0, iclass 11, count 2 2006.173.22:25:23.50#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.22:25:23.50#ibcon#[25=AT08-04\r\n] 2006.173.22:25:23.50#ibcon#*before write, iclass 11, count 2 2006.173.22:25:23.50#ibcon#enter sib2, iclass 11, count 2 2006.173.22:25:23.50#ibcon#flushed, iclass 11, count 2 2006.173.22:25:23.50#ibcon#about to write, iclass 11, count 2 2006.173.22:25:23.50#ibcon#wrote, iclass 11, count 2 2006.173.22:25:23.50#ibcon#about to read 3, iclass 11, count 2 2006.173.22:25:23.53#ibcon#read 3, iclass 11, count 2 2006.173.22:25:23.53#ibcon#about to read 4, iclass 11, count 2 2006.173.22:25:23.53#ibcon#read 4, iclass 11, count 2 2006.173.22:25:23.53#ibcon#about to read 5, iclass 11, count 2 2006.173.22:25:23.53#ibcon#read 5, iclass 11, count 2 2006.173.22:25:23.53#ibcon#about to read 6, iclass 11, count 2 2006.173.22:25:23.53#ibcon#read 6, iclass 11, count 2 2006.173.22:25:23.53#ibcon#end of sib2, iclass 11, count 2 2006.173.22:25:23.53#ibcon#*after write, iclass 11, count 2 2006.173.22:25:23.53#ibcon#*before return 0, iclass 11, count 2 2006.173.22:25:23.53#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.22:25:23.53#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.22:25:23.53#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.22:25:23.53#ibcon#ireg 7 cls_cnt 0 2006.173.22:25:23.53#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.22:25:23.65#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.22:25:23.65#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.22:25:23.65#ibcon#enter wrdev, iclass 11, count 0 2006.173.22:25:23.65#ibcon#first serial, iclass 11, count 0 2006.173.22:25:23.65#ibcon#enter sib2, iclass 11, count 0 2006.173.22:25:23.65#ibcon#flushed, iclass 11, count 0 2006.173.22:25:23.65#ibcon#about to write, iclass 11, count 0 2006.173.22:25:23.65#ibcon#wrote, iclass 11, count 0 2006.173.22:25:23.65#ibcon#about to read 3, iclass 11, count 0 2006.173.22:25:23.67#ibcon#read 3, iclass 11, count 0 2006.173.22:25:23.67#ibcon#about to read 4, iclass 11, count 0 2006.173.22:25:23.67#ibcon#read 4, iclass 11, count 0 2006.173.22:25:23.67#ibcon#about to read 5, iclass 11, count 0 2006.173.22:25:23.67#ibcon#read 5, iclass 11, count 0 2006.173.22:25:23.67#ibcon#about to read 6, iclass 11, count 0 2006.173.22:25:23.67#ibcon#read 6, iclass 11, count 0 2006.173.22:25:23.67#ibcon#end of sib2, iclass 11, count 0 2006.173.22:25:23.67#ibcon#*mode == 0, iclass 11, count 0 2006.173.22:25:23.67#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.22:25:23.67#ibcon#[25=USB\r\n] 2006.173.22:25:23.67#ibcon#*before write, iclass 11, count 0 2006.173.22:25:23.67#ibcon#enter sib2, iclass 11, count 0 2006.173.22:25:23.67#ibcon#flushed, iclass 11, count 0 2006.173.22:25:23.67#ibcon#about to write, iclass 11, count 0 2006.173.22:25:23.67#ibcon#wrote, iclass 11, count 0 2006.173.22:25:23.67#ibcon#about to read 3, iclass 11, count 0 2006.173.22:25:23.70#ibcon#read 3, iclass 11, count 0 2006.173.22:25:23.70#ibcon#about to read 4, iclass 11, count 0 2006.173.22:25:23.70#ibcon#read 4, iclass 11, count 0 2006.173.22:25:23.70#ibcon#about to read 5, iclass 11, count 0 2006.173.22:25:23.70#ibcon#read 5, iclass 11, count 0 2006.173.22:25:23.70#ibcon#about to read 6, iclass 11, count 0 2006.173.22:25:23.70#ibcon#read 6, iclass 11, count 0 2006.173.22:25:23.70#ibcon#end of sib2, iclass 11, count 0 2006.173.22:25:23.70#ibcon#*after write, iclass 11, count 0 2006.173.22:25:23.70#ibcon#*before return 0, iclass 11, count 0 2006.173.22:25:23.70#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.22:25:23.70#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.22:25:23.70#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.22:25:23.70#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.22:25:23.71$vck44/vblo=1,629.99 2006.173.22:25:23.71#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.22:25:23.71#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.22:25:23.71#ibcon#ireg 17 cls_cnt 0 2006.173.22:25:23.71#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.22:25:23.71#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.22:25:23.71#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.22:25:23.71#ibcon#enter wrdev, iclass 13, count 0 2006.173.22:25:23.71#ibcon#first serial, iclass 13, count 0 2006.173.22:25:23.71#ibcon#enter sib2, iclass 13, count 0 2006.173.22:25:23.71#ibcon#flushed, iclass 13, count 0 2006.173.22:25:23.71#ibcon#about to write, iclass 13, count 0 2006.173.22:25:23.71#ibcon#wrote, iclass 13, count 0 2006.173.22:25:23.71#ibcon#about to read 3, iclass 13, count 0 2006.173.22:25:23.72#ibcon#read 3, iclass 13, count 0 2006.173.22:25:23.72#ibcon#about to read 4, iclass 13, count 0 2006.173.22:25:23.72#ibcon#read 4, iclass 13, count 0 2006.173.22:25:23.72#ibcon#about to read 5, iclass 13, count 0 2006.173.22:25:23.72#ibcon#read 5, iclass 13, count 0 2006.173.22:25:23.72#ibcon#about to read 6, iclass 13, count 0 2006.173.22:25:23.72#ibcon#read 6, iclass 13, count 0 2006.173.22:25:23.72#ibcon#end of sib2, iclass 13, count 0 2006.173.22:25:23.72#ibcon#*mode == 0, iclass 13, count 0 2006.173.22:25:23.72#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.22:25:23.72#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.22:25:23.72#ibcon#*before write, iclass 13, count 0 2006.173.22:25:23.72#ibcon#enter sib2, iclass 13, count 0 2006.173.22:25:23.72#ibcon#flushed, iclass 13, count 0 2006.173.22:25:23.72#ibcon#about to write, iclass 13, count 0 2006.173.22:25:23.72#ibcon#wrote, iclass 13, count 0 2006.173.22:25:23.72#ibcon#about to read 3, iclass 13, count 0 2006.173.22:25:23.76#ibcon#read 3, iclass 13, count 0 2006.173.22:25:23.76#ibcon#about to read 4, iclass 13, count 0 2006.173.22:25:23.76#ibcon#read 4, iclass 13, count 0 2006.173.22:25:23.76#ibcon#about to read 5, iclass 13, count 0 2006.173.22:25:23.76#ibcon#read 5, iclass 13, count 0 2006.173.22:25:23.76#ibcon#about to read 6, iclass 13, count 0 2006.173.22:25:23.76#ibcon#read 6, iclass 13, count 0 2006.173.22:25:23.76#ibcon#end of sib2, iclass 13, count 0 2006.173.22:25:23.76#ibcon#*after write, iclass 13, count 0 2006.173.22:25:23.76#ibcon#*before return 0, iclass 13, count 0 2006.173.22:25:23.76#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.22:25:23.76#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.22:25:23.76#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.22:25:23.76#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.22:25:23.77$vck44/vb=1,4 2006.173.22:25:23.77#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.22:25:23.77#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.22:25:23.77#ibcon#ireg 11 cls_cnt 2 2006.173.22:25:23.77#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.22:25:23.77#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.22:25:23.77#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.22:25:23.77#ibcon#enter wrdev, iclass 15, count 2 2006.173.22:25:23.77#ibcon#first serial, iclass 15, count 2 2006.173.22:25:23.77#ibcon#enter sib2, iclass 15, count 2 2006.173.22:25:23.77#ibcon#flushed, iclass 15, count 2 2006.173.22:25:23.77#ibcon#about to write, iclass 15, count 2 2006.173.22:25:23.77#ibcon#wrote, iclass 15, count 2 2006.173.22:25:23.77#ibcon#about to read 3, iclass 15, count 2 2006.173.22:25:23.78#ibcon#read 3, iclass 15, count 2 2006.173.22:25:23.78#ibcon#about to read 4, iclass 15, count 2 2006.173.22:25:23.78#ibcon#read 4, iclass 15, count 2 2006.173.22:25:23.78#ibcon#about to read 5, iclass 15, count 2 2006.173.22:25:23.78#ibcon#read 5, iclass 15, count 2 2006.173.22:25:23.78#ibcon#about to read 6, iclass 15, count 2 2006.173.22:25:23.78#ibcon#read 6, iclass 15, count 2 2006.173.22:25:23.78#ibcon#end of sib2, iclass 15, count 2 2006.173.22:25:23.78#ibcon#*mode == 0, iclass 15, count 2 2006.173.22:25:23.78#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.22:25:23.78#ibcon#[27=AT01-04\r\n] 2006.173.22:25:23.78#ibcon#*before write, iclass 15, count 2 2006.173.22:25:23.78#ibcon#enter sib2, iclass 15, count 2 2006.173.22:25:23.78#ibcon#flushed, iclass 15, count 2 2006.173.22:25:23.78#ibcon#about to write, iclass 15, count 2 2006.173.22:25:23.78#ibcon#wrote, iclass 15, count 2 2006.173.22:25:23.78#ibcon#about to read 3, iclass 15, count 2 2006.173.22:25:23.81#ibcon#read 3, iclass 15, count 2 2006.173.22:25:23.81#ibcon#about to read 4, iclass 15, count 2 2006.173.22:25:23.81#ibcon#read 4, iclass 15, count 2 2006.173.22:25:23.81#ibcon#about to read 5, iclass 15, count 2 2006.173.22:25:23.81#ibcon#read 5, iclass 15, count 2 2006.173.22:25:23.81#ibcon#about to read 6, iclass 15, count 2 2006.173.22:25:23.81#ibcon#read 6, iclass 15, count 2 2006.173.22:25:23.81#ibcon#end of sib2, iclass 15, count 2 2006.173.22:25:23.81#ibcon#*after write, iclass 15, count 2 2006.173.22:25:23.81#ibcon#*before return 0, iclass 15, count 2 2006.173.22:25:23.81#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.22:25:23.81#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.22:25:23.81#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.22:25:23.81#ibcon#ireg 7 cls_cnt 0 2006.173.22:25:23.81#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.22:25:23.93#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.22:25:23.93#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.22:25:23.93#ibcon#enter wrdev, iclass 15, count 0 2006.173.22:25:23.93#ibcon#first serial, iclass 15, count 0 2006.173.22:25:23.93#ibcon#enter sib2, iclass 15, count 0 2006.173.22:25:23.93#ibcon#flushed, iclass 15, count 0 2006.173.22:25:23.93#ibcon#about to write, iclass 15, count 0 2006.173.22:25:23.93#ibcon#wrote, iclass 15, count 0 2006.173.22:25:23.93#ibcon#about to read 3, iclass 15, count 0 2006.173.22:25:23.95#ibcon#read 3, iclass 15, count 0 2006.173.22:25:23.95#ibcon#about to read 4, iclass 15, count 0 2006.173.22:25:23.95#ibcon#read 4, iclass 15, count 0 2006.173.22:25:23.95#ibcon#about to read 5, iclass 15, count 0 2006.173.22:25:23.95#ibcon#read 5, iclass 15, count 0 2006.173.22:25:23.95#ibcon#about to read 6, iclass 15, count 0 2006.173.22:25:23.95#ibcon#read 6, iclass 15, count 0 2006.173.22:25:23.95#ibcon#end of sib2, iclass 15, count 0 2006.173.22:25:23.95#ibcon#*mode == 0, iclass 15, count 0 2006.173.22:25:23.95#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.22:25:23.95#ibcon#[27=USB\r\n] 2006.173.22:25:23.95#ibcon#*before write, iclass 15, count 0 2006.173.22:25:23.95#ibcon#enter sib2, iclass 15, count 0 2006.173.22:25:23.95#ibcon#flushed, iclass 15, count 0 2006.173.22:25:23.95#ibcon#about to write, iclass 15, count 0 2006.173.22:25:23.95#ibcon#wrote, iclass 15, count 0 2006.173.22:25:23.95#ibcon#about to read 3, iclass 15, count 0 2006.173.22:25:23.98#ibcon#read 3, iclass 15, count 0 2006.173.22:25:23.98#ibcon#about to read 4, iclass 15, count 0 2006.173.22:25:23.98#ibcon#read 4, iclass 15, count 0 2006.173.22:25:23.98#ibcon#about to read 5, iclass 15, count 0 2006.173.22:25:23.98#ibcon#read 5, iclass 15, count 0 2006.173.22:25:23.98#ibcon#about to read 6, iclass 15, count 0 2006.173.22:25:23.98#ibcon#read 6, iclass 15, count 0 2006.173.22:25:23.98#ibcon#end of sib2, iclass 15, count 0 2006.173.22:25:23.98#ibcon#*after write, iclass 15, count 0 2006.173.22:25:23.98#ibcon#*before return 0, iclass 15, count 0 2006.173.22:25:23.98#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.22:25:23.98#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.22:25:23.98#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.22:25:23.98#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.22:25:23.99$vck44/vblo=2,634.99 2006.173.22:25:23.99#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.22:25:23.99#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.22:25:23.99#ibcon#ireg 17 cls_cnt 0 2006.173.22:25:23.99#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.22:25:23.99#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.22:25:23.99#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.22:25:23.99#ibcon#enter wrdev, iclass 17, count 0 2006.173.22:25:23.99#ibcon#first serial, iclass 17, count 0 2006.173.22:25:23.99#ibcon#enter sib2, iclass 17, count 0 2006.173.22:25:23.99#ibcon#flushed, iclass 17, count 0 2006.173.22:25:23.99#ibcon#about to write, iclass 17, count 0 2006.173.22:25:23.99#ibcon#wrote, iclass 17, count 0 2006.173.22:25:23.99#ibcon#about to read 3, iclass 17, count 0 2006.173.22:25:24.00#ibcon#read 3, iclass 17, count 0 2006.173.22:25:24.00#ibcon#about to read 4, iclass 17, count 0 2006.173.22:25:24.00#ibcon#read 4, iclass 17, count 0 2006.173.22:25:24.00#ibcon#about to read 5, iclass 17, count 0 2006.173.22:25:24.00#ibcon#read 5, iclass 17, count 0 2006.173.22:25:24.00#ibcon#about to read 6, iclass 17, count 0 2006.173.22:25:24.00#ibcon#read 6, iclass 17, count 0 2006.173.22:25:24.00#ibcon#end of sib2, iclass 17, count 0 2006.173.22:25:24.00#ibcon#*mode == 0, iclass 17, count 0 2006.173.22:25:24.00#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.22:25:24.00#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.22:25:24.00#ibcon#*before write, iclass 17, count 0 2006.173.22:25:24.00#ibcon#enter sib2, iclass 17, count 0 2006.173.22:25:24.00#ibcon#flushed, iclass 17, count 0 2006.173.22:25:24.00#ibcon#about to write, iclass 17, count 0 2006.173.22:25:24.00#ibcon#wrote, iclass 17, count 0 2006.173.22:25:24.00#ibcon#about to read 3, iclass 17, count 0 2006.173.22:25:24.04#ibcon#read 3, iclass 17, count 0 2006.173.22:25:24.04#ibcon#about to read 4, iclass 17, count 0 2006.173.22:25:24.04#ibcon#read 4, iclass 17, count 0 2006.173.22:25:24.04#ibcon#about to read 5, iclass 17, count 0 2006.173.22:25:24.04#ibcon#read 5, iclass 17, count 0 2006.173.22:25:24.04#ibcon#about to read 6, iclass 17, count 0 2006.173.22:25:24.04#ibcon#read 6, iclass 17, count 0 2006.173.22:25:24.04#ibcon#end of sib2, iclass 17, count 0 2006.173.22:25:24.04#ibcon#*after write, iclass 17, count 0 2006.173.22:25:24.04#ibcon#*before return 0, iclass 17, count 0 2006.173.22:25:24.04#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.22:25:24.04#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.22:25:24.04#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.22:25:24.04#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.22:25:24.05$vck44/vb=2,4 2006.173.22:25:24.05#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.22:25:24.05#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.22:25:24.05#ibcon#ireg 11 cls_cnt 2 2006.173.22:25:24.05#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.22:25:24.09#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.22:25:24.09#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.22:25:24.09#ibcon#enter wrdev, iclass 19, count 2 2006.173.22:25:24.09#ibcon#first serial, iclass 19, count 2 2006.173.22:25:24.09#ibcon#enter sib2, iclass 19, count 2 2006.173.22:25:24.09#ibcon#flushed, iclass 19, count 2 2006.173.22:25:24.09#ibcon#about to write, iclass 19, count 2 2006.173.22:25:24.09#ibcon#wrote, iclass 19, count 2 2006.173.22:25:24.09#ibcon#about to read 3, iclass 19, count 2 2006.173.22:25:24.11#ibcon#read 3, iclass 19, count 2 2006.173.22:25:24.11#ibcon#about to read 4, iclass 19, count 2 2006.173.22:25:24.11#ibcon#read 4, iclass 19, count 2 2006.173.22:25:24.11#ibcon#about to read 5, iclass 19, count 2 2006.173.22:25:24.11#ibcon#read 5, iclass 19, count 2 2006.173.22:25:24.11#ibcon#about to read 6, iclass 19, count 2 2006.173.22:25:24.11#ibcon#read 6, iclass 19, count 2 2006.173.22:25:24.11#ibcon#end of sib2, iclass 19, count 2 2006.173.22:25:24.11#ibcon#*mode == 0, iclass 19, count 2 2006.173.22:25:24.11#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.22:25:24.11#ibcon#[27=AT02-04\r\n] 2006.173.22:25:24.11#ibcon#*before write, iclass 19, count 2 2006.173.22:25:24.11#ibcon#enter sib2, iclass 19, count 2 2006.173.22:25:24.11#ibcon#flushed, iclass 19, count 2 2006.173.22:25:24.11#ibcon#about to write, iclass 19, count 2 2006.173.22:25:24.11#ibcon#wrote, iclass 19, count 2 2006.173.22:25:24.11#ibcon#about to read 3, iclass 19, count 2 2006.173.22:25:24.14#ibcon#read 3, iclass 19, count 2 2006.173.22:25:24.14#ibcon#about to read 4, iclass 19, count 2 2006.173.22:25:24.14#ibcon#read 4, iclass 19, count 2 2006.173.22:25:24.14#ibcon#about to read 5, iclass 19, count 2 2006.173.22:25:24.14#ibcon#read 5, iclass 19, count 2 2006.173.22:25:24.14#ibcon#about to read 6, iclass 19, count 2 2006.173.22:25:24.14#ibcon#read 6, iclass 19, count 2 2006.173.22:25:24.14#ibcon#end of sib2, iclass 19, count 2 2006.173.22:25:24.14#ibcon#*after write, iclass 19, count 2 2006.173.22:25:24.14#ibcon#*before return 0, iclass 19, count 2 2006.173.22:25:24.14#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.22:25:24.14#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.22:25:24.14#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.22:25:24.14#ibcon#ireg 7 cls_cnt 0 2006.173.22:25:24.14#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.22:25:24.26#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.22:25:24.26#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.22:25:24.26#ibcon#enter wrdev, iclass 19, count 0 2006.173.22:25:24.26#ibcon#first serial, iclass 19, count 0 2006.173.22:25:24.26#ibcon#enter sib2, iclass 19, count 0 2006.173.22:25:24.26#ibcon#flushed, iclass 19, count 0 2006.173.22:25:24.26#ibcon#about to write, iclass 19, count 0 2006.173.22:25:24.26#ibcon#wrote, iclass 19, count 0 2006.173.22:25:24.26#ibcon#about to read 3, iclass 19, count 0 2006.173.22:25:24.28#ibcon#read 3, iclass 19, count 0 2006.173.22:25:24.28#ibcon#about to read 4, iclass 19, count 0 2006.173.22:25:24.28#ibcon#read 4, iclass 19, count 0 2006.173.22:25:24.28#ibcon#about to read 5, iclass 19, count 0 2006.173.22:25:24.28#ibcon#read 5, iclass 19, count 0 2006.173.22:25:24.28#ibcon#about to read 6, iclass 19, count 0 2006.173.22:25:24.28#ibcon#read 6, iclass 19, count 0 2006.173.22:25:24.28#ibcon#end of sib2, iclass 19, count 0 2006.173.22:25:24.28#ibcon#*mode == 0, iclass 19, count 0 2006.173.22:25:24.28#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.22:25:24.28#ibcon#[27=USB\r\n] 2006.173.22:25:24.28#ibcon#*before write, iclass 19, count 0 2006.173.22:25:24.28#ibcon#enter sib2, iclass 19, count 0 2006.173.22:25:24.28#ibcon#flushed, iclass 19, count 0 2006.173.22:25:24.28#ibcon#about to write, iclass 19, count 0 2006.173.22:25:24.28#ibcon#wrote, iclass 19, count 0 2006.173.22:25:24.28#ibcon#about to read 3, iclass 19, count 0 2006.173.22:25:24.31#ibcon#read 3, iclass 19, count 0 2006.173.22:25:24.31#ibcon#about to read 4, iclass 19, count 0 2006.173.22:25:24.31#ibcon#read 4, iclass 19, count 0 2006.173.22:25:24.31#ibcon#about to read 5, iclass 19, count 0 2006.173.22:25:24.31#ibcon#read 5, iclass 19, count 0 2006.173.22:25:24.31#ibcon#about to read 6, iclass 19, count 0 2006.173.22:25:24.31#ibcon#read 6, iclass 19, count 0 2006.173.22:25:24.31#ibcon#end of sib2, iclass 19, count 0 2006.173.22:25:24.31#ibcon#*after write, iclass 19, count 0 2006.173.22:25:24.31#ibcon#*before return 0, iclass 19, count 0 2006.173.22:25:24.31#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.22:25:24.31#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.22:25:24.31#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.22:25:24.31#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.22:25:24.32$vck44/vblo=3,649.99 2006.173.22:25:24.32#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.22:25:24.32#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.22:25:24.32#ibcon#ireg 17 cls_cnt 0 2006.173.22:25:24.32#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.22:25:24.32#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.22:25:24.32#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.22:25:24.32#ibcon#enter wrdev, iclass 21, count 0 2006.173.22:25:24.32#ibcon#first serial, iclass 21, count 0 2006.173.22:25:24.32#ibcon#enter sib2, iclass 21, count 0 2006.173.22:25:24.32#ibcon#flushed, iclass 21, count 0 2006.173.22:25:24.32#ibcon#about to write, iclass 21, count 0 2006.173.22:25:24.32#ibcon#wrote, iclass 21, count 0 2006.173.22:25:24.32#ibcon#about to read 3, iclass 21, count 0 2006.173.22:25:24.33#ibcon#read 3, iclass 21, count 0 2006.173.22:25:24.33#ibcon#about to read 4, iclass 21, count 0 2006.173.22:25:24.33#ibcon#read 4, iclass 21, count 0 2006.173.22:25:24.33#ibcon#about to read 5, iclass 21, count 0 2006.173.22:25:24.33#ibcon#read 5, iclass 21, count 0 2006.173.22:25:24.33#ibcon#about to read 6, iclass 21, count 0 2006.173.22:25:24.33#ibcon#read 6, iclass 21, count 0 2006.173.22:25:24.33#ibcon#end of sib2, iclass 21, count 0 2006.173.22:25:24.33#ibcon#*mode == 0, iclass 21, count 0 2006.173.22:25:24.33#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.22:25:24.33#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.22:25:24.33#ibcon#*before write, iclass 21, count 0 2006.173.22:25:24.33#ibcon#enter sib2, iclass 21, count 0 2006.173.22:25:24.33#ibcon#flushed, iclass 21, count 0 2006.173.22:25:24.33#ibcon#about to write, iclass 21, count 0 2006.173.22:25:24.33#ibcon#wrote, iclass 21, count 0 2006.173.22:25:24.33#ibcon#about to read 3, iclass 21, count 0 2006.173.22:25:24.37#ibcon#read 3, iclass 21, count 0 2006.173.22:25:24.37#ibcon#about to read 4, iclass 21, count 0 2006.173.22:25:24.37#ibcon#read 4, iclass 21, count 0 2006.173.22:25:24.37#ibcon#about to read 5, iclass 21, count 0 2006.173.22:25:24.37#ibcon#read 5, iclass 21, count 0 2006.173.22:25:24.37#ibcon#about to read 6, iclass 21, count 0 2006.173.22:25:24.37#ibcon#read 6, iclass 21, count 0 2006.173.22:25:24.37#ibcon#end of sib2, iclass 21, count 0 2006.173.22:25:24.37#ibcon#*after write, iclass 21, count 0 2006.173.22:25:24.37#ibcon#*before return 0, iclass 21, count 0 2006.173.22:25:24.37#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.22:25:24.37#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.22:25:24.37#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.22:25:24.37#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.22:25:24.38$vck44/vb=3,4 2006.173.22:25:24.38#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.22:25:24.38#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.22:25:24.38#ibcon#ireg 11 cls_cnt 2 2006.173.22:25:24.38#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.22:25:24.42#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.22:25:24.42#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.22:25:24.42#ibcon#enter wrdev, iclass 23, count 2 2006.173.22:25:24.42#ibcon#first serial, iclass 23, count 2 2006.173.22:25:24.42#ibcon#enter sib2, iclass 23, count 2 2006.173.22:25:24.42#ibcon#flushed, iclass 23, count 2 2006.173.22:25:24.42#ibcon#about to write, iclass 23, count 2 2006.173.22:25:24.42#ibcon#wrote, iclass 23, count 2 2006.173.22:25:24.42#ibcon#about to read 3, iclass 23, count 2 2006.173.22:25:24.44#ibcon#read 3, iclass 23, count 2 2006.173.22:25:24.44#ibcon#about to read 4, iclass 23, count 2 2006.173.22:25:24.44#ibcon#read 4, iclass 23, count 2 2006.173.22:25:24.44#ibcon#about to read 5, iclass 23, count 2 2006.173.22:25:24.44#ibcon#read 5, iclass 23, count 2 2006.173.22:25:24.44#ibcon#about to read 6, iclass 23, count 2 2006.173.22:25:24.44#ibcon#read 6, iclass 23, count 2 2006.173.22:25:24.44#ibcon#end of sib2, iclass 23, count 2 2006.173.22:25:24.44#ibcon#*mode == 0, iclass 23, count 2 2006.173.22:25:24.44#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.22:25:24.44#ibcon#[27=AT03-04\r\n] 2006.173.22:25:24.44#ibcon#*before write, iclass 23, count 2 2006.173.22:25:24.44#ibcon#enter sib2, iclass 23, count 2 2006.173.22:25:24.44#ibcon#flushed, iclass 23, count 2 2006.173.22:25:24.44#ibcon#about to write, iclass 23, count 2 2006.173.22:25:24.44#ibcon#wrote, iclass 23, count 2 2006.173.22:25:24.44#ibcon#about to read 3, iclass 23, count 2 2006.173.22:25:24.47#ibcon#read 3, iclass 23, count 2 2006.173.22:25:24.47#ibcon#about to read 4, iclass 23, count 2 2006.173.22:25:24.47#ibcon#read 4, iclass 23, count 2 2006.173.22:25:24.47#ibcon#about to read 5, iclass 23, count 2 2006.173.22:25:24.47#ibcon#read 5, iclass 23, count 2 2006.173.22:25:24.47#ibcon#about to read 6, iclass 23, count 2 2006.173.22:25:24.47#ibcon#read 6, iclass 23, count 2 2006.173.22:25:24.47#ibcon#end of sib2, iclass 23, count 2 2006.173.22:25:24.47#ibcon#*after write, iclass 23, count 2 2006.173.22:25:24.50#ibcon#*before return 0, iclass 23, count 2 2006.173.22:25:24.50#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.22:25:24.50#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.22:25:24.50#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.22:25:24.50#ibcon#ireg 7 cls_cnt 0 2006.173.22:25:24.50#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.22:25:24.61#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.22:25:24.61#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.22:25:24.61#ibcon#enter wrdev, iclass 23, count 0 2006.173.22:25:24.61#ibcon#first serial, iclass 23, count 0 2006.173.22:25:24.61#ibcon#enter sib2, iclass 23, count 0 2006.173.22:25:24.61#ibcon#flushed, iclass 23, count 0 2006.173.22:25:24.61#ibcon#about to write, iclass 23, count 0 2006.173.22:25:24.61#ibcon#wrote, iclass 23, count 0 2006.173.22:25:24.61#ibcon#about to read 3, iclass 23, count 0 2006.173.22:25:24.63#ibcon#read 3, iclass 23, count 0 2006.173.22:25:24.63#ibcon#about to read 4, iclass 23, count 0 2006.173.22:25:24.63#ibcon#read 4, iclass 23, count 0 2006.173.22:25:24.63#ibcon#about to read 5, iclass 23, count 0 2006.173.22:25:24.63#ibcon#read 5, iclass 23, count 0 2006.173.22:25:24.63#ibcon#about to read 6, iclass 23, count 0 2006.173.22:25:24.63#ibcon#read 6, iclass 23, count 0 2006.173.22:25:24.63#ibcon#end of sib2, iclass 23, count 0 2006.173.22:25:24.63#ibcon#*mode == 0, iclass 23, count 0 2006.173.22:25:24.63#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.22:25:24.63#ibcon#[27=USB\r\n] 2006.173.22:25:24.63#ibcon#*before write, iclass 23, count 0 2006.173.22:25:24.63#ibcon#enter sib2, iclass 23, count 0 2006.173.22:25:24.63#ibcon#flushed, iclass 23, count 0 2006.173.22:25:24.63#ibcon#about to write, iclass 23, count 0 2006.173.22:25:24.63#ibcon#wrote, iclass 23, count 0 2006.173.22:25:24.63#ibcon#about to read 3, iclass 23, count 0 2006.173.22:25:24.66#ibcon#read 3, iclass 23, count 0 2006.173.22:25:24.66#ibcon#about to read 4, iclass 23, count 0 2006.173.22:25:24.66#ibcon#read 4, iclass 23, count 0 2006.173.22:25:24.66#ibcon#about to read 5, iclass 23, count 0 2006.173.22:25:24.66#ibcon#read 5, iclass 23, count 0 2006.173.22:25:24.66#ibcon#about to read 6, iclass 23, count 0 2006.173.22:25:24.66#ibcon#read 6, iclass 23, count 0 2006.173.22:25:24.66#ibcon#end of sib2, iclass 23, count 0 2006.173.22:25:24.66#ibcon#*after write, iclass 23, count 0 2006.173.22:25:24.66#ibcon#*before return 0, iclass 23, count 0 2006.173.22:25:24.66#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.22:25:24.66#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.22:25:24.66#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.22:25:24.66#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.22:25:24.67$vck44/vblo=4,679.99 2006.173.22:25:24.67#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.22:25:24.67#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.22:25:24.67#ibcon#ireg 17 cls_cnt 0 2006.173.22:25:24.67#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.22:25:24.67#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.22:25:24.67#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.22:25:24.67#ibcon#enter wrdev, iclass 25, count 0 2006.173.22:25:24.67#ibcon#first serial, iclass 25, count 0 2006.173.22:25:24.67#ibcon#enter sib2, iclass 25, count 0 2006.173.22:25:24.67#ibcon#flushed, iclass 25, count 0 2006.173.22:25:24.67#ibcon#about to write, iclass 25, count 0 2006.173.22:25:24.67#ibcon#wrote, iclass 25, count 0 2006.173.22:25:24.67#ibcon#about to read 3, iclass 25, count 0 2006.173.22:25:24.68#ibcon#read 3, iclass 25, count 0 2006.173.22:25:24.68#ibcon#about to read 4, iclass 25, count 0 2006.173.22:25:24.68#ibcon#read 4, iclass 25, count 0 2006.173.22:25:24.68#ibcon#about to read 5, iclass 25, count 0 2006.173.22:25:24.68#ibcon#read 5, iclass 25, count 0 2006.173.22:25:24.68#ibcon#about to read 6, iclass 25, count 0 2006.173.22:25:24.68#ibcon#read 6, iclass 25, count 0 2006.173.22:25:24.68#ibcon#end of sib2, iclass 25, count 0 2006.173.22:25:24.68#ibcon#*mode == 0, iclass 25, count 0 2006.173.22:25:24.68#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.22:25:24.68#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.22:25:24.68#ibcon#*before write, iclass 25, count 0 2006.173.22:25:24.68#ibcon#enter sib2, iclass 25, count 0 2006.173.22:25:24.68#ibcon#flushed, iclass 25, count 0 2006.173.22:25:24.68#ibcon#about to write, iclass 25, count 0 2006.173.22:25:24.68#ibcon#wrote, iclass 25, count 0 2006.173.22:25:24.68#ibcon#about to read 3, iclass 25, count 0 2006.173.22:25:24.72#ibcon#read 3, iclass 25, count 0 2006.173.22:25:24.72#ibcon#about to read 4, iclass 25, count 0 2006.173.22:25:24.72#ibcon#read 4, iclass 25, count 0 2006.173.22:25:24.72#ibcon#about to read 5, iclass 25, count 0 2006.173.22:25:24.72#ibcon#read 5, iclass 25, count 0 2006.173.22:25:24.72#ibcon#about to read 6, iclass 25, count 0 2006.173.22:25:24.72#ibcon#read 6, iclass 25, count 0 2006.173.22:25:24.72#ibcon#end of sib2, iclass 25, count 0 2006.173.22:25:24.72#ibcon#*after write, iclass 25, count 0 2006.173.22:25:24.72#ibcon#*before return 0, iclass 25, count 0 2006.173.22:25:24.72#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.22:25:24.72#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.22:25:24.72#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.22:25:24.72#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.22:25:24.73$vck44/vb=4,4 2006.173.22:25:24.73#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.22:25:24.73#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.22:25:24.73#ibcon#ireg 11 cls_cnt 2 2006.173.22:25:24.73#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.22:25:24.77#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.22:25:24.77#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.22:25:24.77#ibcon#enter wrdev, iclass 27, count 2 2006.173.22:25:24.77#ibcon#first serial, iclass 27, count 2 2006.173.22:25:24.77#ibcon#enter sib2, iclass 27, count 2 2006.173.22:25:24.77#ibcon#flushed, iclass 27, count 2 2006.173.22:25:24.77#ibcon#about to write, iclass 27, count 2 2006.173.22:25:24.77#ibcon#wrote, iclass 27, count 2 2006.173.22:25:24.77#ibcon#about to read 3, iclass 27, count 2 2006.173.22:25:24.79#ibcon#read 3, iclass 27, count 2 2006.173.22:25:24.79#ibcon#about to read 4, iclass 27, count 2 2006.173.22:25:24.79#ibcon#read 4, iclass 27, count 2 2006.173.22:25:24.79#ibcon#about to read 5, iclass 27, count 2 2006.173.22:25:24.79#ibcon#read 5, iclass 27, count 2 2006.173.22:25:24.79#ibcon#about to read 6, iclass 27, count 2 2006.173.22:25:24.79#ibcon#read 6, iclass 27, count 2 2006.173.22:25:24.79#ibcon#end of sib2, iclass 27, count 2 2006.173.22:25:24.79#ibcon#*mode == 0, iclass 27, count 2 2006.173.22:25:24.79#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.22:25:24.79#ibcon#[27=AT04-04\r\n] 2006.173.22:25:24.79#ibcon#*before write, iclass 27, count 2 2006.173.22:25:24.79#ibcon#enter sib2, iclass 27, count 2 2006.173.22:25:24.79#ibcon#flushed, iclass 27, count 2 2006.173.22:25:24.79#ibcon#about to write, iclass 27, count 2 2006.173.22:25:24.79#ibcon#wrote, iclass 27, count 2 2006.173.22:25:24.79#ibcon#about to read 3, iclass 27, count 2 2006.173.22:25:24.82#ibcon#read 3, iclass 27, count 2 2006.173.22:25:24.82#ibcon#about to read 4, iclass 27, count 2 2006.173.22:25:24.82#ibcon#read 4, iclass 27, count 2 2006.173.22:25:24.82#ibcon#about to read 5, iclass 27, count 2 2006.173.22:25:24.82#ibcon#read 5, iclass 27, count 2 2006.173.22:25:24.82#ibcon#about to read 6, iclass 27, count 2 2006.173.22:25:24.82#ibcon#read 6, iclass 27, count 2 2006.173.22:25:24.82#ibcon#end of sib2, iclass 27, count 2 2006.173.22:25:24.82#ibcon#*after write, iclass 27, count 2 2006.173.22:25:24.82#ibcon#*before return 0, iclass 27, count 2 2006.173.22:25:24.82#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.22:25:24.82#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.22:25:24.82#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.22:25:24.82#ibcon#ireg 7 cls_cnt 0 2006.173.22:25:24.82#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.22:25:24.94#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.22:25:24.94#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.22:25:24.94#ibcon#enter wrdev, iclass 27, count 0 2006.173.22:25:24.94#ibcon#first serial, iclass 27, count 0 2006.173.22:25:24.94#ibcon#enter sib2, iclass 27, count 0 2006.173.22:25:24.94#ibcon#flushed, iclass 27, count 0 2006.173.22:25:24.94#ibcon#about to write, iclass 27, count 0 2006.173.22:25:24.94#ibcon#wrote, iclass 27, count 0 2006.173.22:25:24.94#ibcon#about to read 3, iclass 27, count 0 2006.173.22:25:24.96#ibcon#read 3, iclass 27, count 0 2006.173.22:25:24.96#ibcon#about to read 4, iclass 27, count 0 2006.173.22:25:24.96#ibcon#read 4, iclass 27, count 0 2006.173.22:25:24.96#ibcon#about to read 5, iclass 27, count 0 2006.173.22:25:24.96#ibcon#read 5, iclass 27, count 0 2006.173.22:25:24.96#ibcon#about to read 6, iclass 27, count 0 2006.173.22:25:24.96#ibcon#read 6, iclass 27, count 0 2006.173.22:25:24.96#ibcon#end of sib2, iclass 27, count 0 2006.173.22:25:24.96#ibcon#*mode == 0, iclass 27, count 0 2006.173.22:25:24.96#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.22:25:24.96#ibcon#[27=USB\r\n] 2006.173.22:25:24.96#ibcon#*before write, iclass 27, count 0 2006.173.22:25:24.96#ibcon#enter sib2, iclass 27, count 0 2006.173.22:25:24.96#ibcon#flushed, iclass 27, count 0 2006.173.22:25:24.96#ibcon#about to write, iclass 27, count 0 2006.173.22:25:24.96#ibcon#wrote, iclass 27, count 0 2006.173.22:25:24.96#ibcon#about to read 3, iclass 27, count 0 2006.173.22:25:24.99#ibcon#read 3, iclass 27, count 0 2006.173.22:25:24.99#ibcon#about to read 4, iclass 27, count 0 2006.173.22:25:24.99#ibcon#read 4, iclass 27, count 0 2006.173.22:25:24.99#ibcon#about to read 5, iclass 27, count 0 2006.173.22:25:24.99#ibcon#read 5, iclass 27, count 0 2006.173.22:25:24.99#ibcon#about to read 6, iclass 27, count 0 2006.173.22:25:24.99#ibcon#read 6, iclass 27, count 0 2006.173.22:25:24.99#ibcon#end of sib2, iclass 27, count 0 2006.173.22:25:24.99#ibcon#*after write, iclass 27, count 0 2006.173.22:25:24.99#ibcon#*before return 0, iclass 27, count 0 2006.173.22:25:24.99#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.22:25:24.99#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.22:25:24.99#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.22:25:24.99#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.22:25:25.00$vck44/vblo=5,709.99 2006.173.22:25:25.00#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.22:25:25.00#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.22:25:25.00#ibcon#ireg 17 cls_cnt 0 2006.173.22:25:25.00#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.22:25:25.00#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.22:25:25.00#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.22:25:25.00#ibcon#enter wrdev, iclass 29, count 0 2006.173.22:25:25.00#ibcon#first serial, iclass 29, count 0 2006.173.22:25:25.00#ibcon#enter sib2, iclass 29, count 0 2006.173.22:25:25.00#ibcon#flushed, iclass 29, count 0 2006.173.22:25:25.00#ibcon#about to write, iclass 29, count 0 2006.173.22:25:25.00#ibcon#wrote, iclass 29, count 0 2006.173.22:25:25.00#ibcon#about to read 3, iclass 29, count 0 2006.173.22:25:25.01#ibcon#read 3, iclass 29, count 0 2006.173.22:25:25.01#ibcon#about to read 4, iclass 29, count 0 2006.173.22:25:25.01#ibcon#read 4, iclass 29, count 0 2006.173.22:25:25.01#ibcon#about to read 5, iclass 29, count 0 2006.173.22:25:25.01#ibcon#read 5, iclass 29, count 0 2006.173.22:25:25.01#ibcon#about to read 6, iclass 29, count 0 2006.173.22:25:25.01#ibcon#read 6, iclass 29, count 0 2006.173.22:25:25.01#ibcon#end of sib2, iclass 29, count 0 2006.173.22:25:25.01#ibcon#*mode == 0, iclass 29, count 0 2006.173.22:25:25.01#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.22:25:25.01#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.22:25:25.01#ibcon#*before write, iclass 29, count 0 2006.173.22:25:25.01#ibcon#enter sib2, iclass 29, count 0 2006.173.22:25:25.01#ibcon#flushed, iclass 29, count 0 2006.173.22:25:25.01#ibcon#about to write, iclass 29, count 0 2006.173.22:25:25.01#ibcon#wrote, iclass 29, count 0 2006.173.22:25:25.01#ibcon#about to read 3, iclass 29, count 0 2006.173.22:25:25.05#ibcon#read 3, iclass 29, count 0 2006.173.22:25:25.05#ibcon#about to read 4, iclass 29, count 0 2006.173.22:25:25.05#ibcon#read 4, iclass 29, count 0 2006.173.22:25:25.05#ibcon#about to read 5, iclass 29, count 0 2006.173.22:25:25.05#ibcon#read 5, iclass 29, count 0 2006.173.22:25:25.05#ibcon#about to read 6, iclass 29, count 0 2006.173.22:25:25.05#ibcon#read 6, iclass 29, count 0 2006.173.22:25:25.05#ibcon#end of sib2, iclass 29, count 0 2006.173.22:25:25.05#ibcon#*after write, iclass 29, count 0 2006.173.22:25:25.05#ibcon#*before return 0, iclass 29, count 0 2006.173.22:25:25.05#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.22:25:25.05#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.22:25:25.05#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.22:25:25.05#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.22:25:25.06$vck44/vb=5,4 2006.173.22:25:25.06#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.22:25:25.06#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.22:25:25.06#ibcon#ireg 11 cls_cnt 2 2006.173.22:25:25.06#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.22:25:25.10#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.22:25:25.10#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.22:25:25.10#ibcon#enter wrdev, iclass 31, count 2 2006.173.22:25:25.10#ibcon#first serial, iclass 31, count 2 2006.173.22:25:25.10#ibcon#enter sib2, iclass 31, count 2 2006.173.22:25:25.10#ibcon#flushed, iclass 31, count 2 2006.173.22:25:25.10#ibcon#about to write, iclass 31, count 2 2006.173.22:25:25.10#ibcon#wrote, iclass 31, count 2 2006.173.22:25:25.10#ibcon#about to read 3, iclass 31, count 2 2006.173.22:25:25.12#ibcon#read 3, iclass 31, count 2 2006.173.22:25:25.12#ibcon#about to read 4, iclass 31, count 2 2006.173.22:25:25.12#ibcon#read 4, iclass 31, count 2 2006.173.22:25:25.12#ibcon#about to read 5, iclass 31, count 2 2006.173.22:25:25.12#ibcon#read 5, iclass 31, count 2 2006.173.22:25:25.12#ibcon#about to read 6, iclass 31, count 2 2006.173.22:25:25.12#ibcon#read 6, iclass 31, count 2 2006.173.22:25:25.12#ibcon#end of sib2, iclass 31, count 2 2006.173.22:25:25.12#ibcon#*mode == 0, iclass 31, count 2 2006.173.22:25:25.12#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.22:25:25.12#ibcon#[27=AT05-04\r\n] 2006.173.22:25:25.12#ibcon#*before write, iclass 31, count 2 2006.173.22:25:25.12#ibcon#enter sib2, iclass 31, count 2 2006.173.22:25:25.12#ibcon#flushed, iclass 31, count 2 2006.173.22:25:25.12#ibcon#about to write, iclass 31, count 2 2006.173.22:25:25.12#ibcon#wrote, iclass 31, count 2 2006.173.22:25:25.12#ibcon#about to read 3, iclass 31, count 2 2006.173.22:25:25.15#ibcon#read 3, iclass 31, count 2 2006.173.22:25:25.15#ibcon#about to read 4, iclass 31, count 2 2006.173.22:25:25.15#ibcon#read 4, iclass 31, count 2 2006.173.22:25:25.15#ibcon#about to read 5, iclass 31, count 2 2006.173.22:25:25.15#ibcon#read 5, iclass 31, count 2 2006.173.22:25:25.15#ibcon#about to read 6, iclass 31, count 2 2006.173.22:25:25.15#ibcon#read 6, iclass 31, count 2 2006.173.22:25:25.15#ibcon#end of sib2, iclass 31, count 2 2006.173.22:25:25.15#ibcon#*after write, iclass 31, count 2 2006.173.22:25:25.15#ibcon#*before return 0, iclass 31, count 2 2006.173.22:25:25.15#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.22:25:25.15#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.22:25:25.15#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.22:25:25.15#ibcon#ireg 7 cls_cnt 0 2006.173.22:25:25.15#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.22:25:25.27#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.22:25:25.27#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.22:25:25.27#ibcon#enter wrdev, iclass 31, count 0 2006.173.22:25:25.27#ibcon#first serial, iclass 31, count 0 2006.173.22:25:25.27#ibcon#enter sib2, iclass 31, count 0 2006.173.22:25:25.27#ibcon#flushed, iclass 31, count 0 2006.173.22:25:25.27#ibcon#about to write, iclass 31, count 0 2006.173.22:25:25.27#ibcon#wrote, iclass 31, count 0 2006.173.22:25:25.27#ibcon#about to read 3, iclass 31, count 0 2006.173.22:25:25.29#ibcon#read 3, iclass 31, count 0 2006.173.22:25:25.29#ibcon#about to read 4, iclass 31, count 0 2006.173.22:25:25.29#ibcon#read 4, iclass 31, count 0 2006.173.22:25:25.29#ibcon#about to read 5, iclass 31, count 0 2006.173.22:25:25.29#ibcon#read 5, iclass 31, count 0 2006.173.22:25:25.29#ibcon#about to read 6, iclass 31, count 0 2006.173.22:25:25.29#ibcon#read 6, iclass 31, count 0 2006.173.22:25:25.29#ibcon#end of sib2, iclass 31, count 0 2006.173.22:25:25.29#ibcon#*mode == 0, iclass 31, count 0 2006.173.22:25:25.29#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.22:25:25.29#ibcon#[27=USB\r\n] 2006.173.22:25:25.29#ibcon#*before write, iclass 31, count 0 2006.173.22:25:25.29#ibcon#enter sib2, iclass 31, count 0 2006.173.22:25:25.29#ibcon#flushed, iclass 31, count 0 2006.173.22:25:25.29#ibcon#about to write, iclass 31, count 0 2006.173.22:25:25.29#ibcon#wrote, iclass 31, count 0 2006.173.22:25:25.29#ibcon#about to read 3, iclass 31, count 0 2006.173.22:25:25.32#ibcon#read 3, iclass 31, count 0 2006.173.22:25:25.32#ibcon#about to read 4, iclass 31, count 0 2006.173.22:25:25.32#ibcon#read 4, iclass 31, count 0 2006.173.22:25:25.32#ibcon#about to read 5, iclass 31, count 0 2006.173.22:25:25.32#ibcon#read 5, iclass 31, count 0 2006.173.22:25:25.32#ibcon#about to read 6, iclass 31, count 0 2006.173.22:25:25.32#ibcon#read 6, iclass 31, count 0 2006.173.22:25:25.32#ibcon#end of sib2, iclass 31, count 0 2006.173.22:25:25.32#ibcon#*after write, iclass 31, count 0 2006.173.22:25:25.32#ibcon#*before return 0, iclass 31, count 0 2006.173.22:25:25.32#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.22:25:25.32#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.22:25:25.32#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.22:25:25.32#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.22:25:25.33$vck44/vblo=6,719.99 2006.173.22:25:25.33#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.22:25:25.33#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.22:25:25.33#ibcon#ireg 17 cls_cnt 0 2006.173.22:25:25.33#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.22:25:25.33#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.22:25:25.33#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.22:25:25.33#ibcon#enter wrdev, iclass 33, count 0 2006.173.22:25:25.33#ibcon#first serial, iclass 33, count 0 2006.173.22:25:25.33#ibcon#enter sib2, iclass 33, count 0 2006.173.22:25:25.33#ibcon#flushed, iclass 33, count 0 2006.173.22:25:25.33#ibcon#about to write, iclass 33, count 0 2006.173.22:25:25.33#ibcon#wrote, iclass 33, count 0 2006.173.22:25:25.33#ibcon#about to read 3, iclass 33, count 0 2006.173.22:25:25.34#ibcon#read 3, iclass 33, count 0 2006.173.22:25:25.34#ibcon#about to read 4, iclass 33, count 0 2006.173.22:25:25.34#ibcon#read 4, iclass 33, count 0 2006.173.22:25:25.34#ibcon#about to read 5, iclass 33, count 0 2006.173.22:25:25.34#ibcon#read 5, iclass 33, count 0 2006.173.22:25:25.34#ibcon#about to read 6, iclass 33, count 0 2006.173.22:25:25.34#ibcon#read 6, iclass 33, count 0 2006.173.22:25:25.34#ibcon#end of sib2, iclass 33, count 0 2006.173.22:25:25.34#ibcon#*mode == 0, iclass 33, count 0 2006.173.22:25:25.34#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.22:25:25.34#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.22:25:25.34#ibcon#*before write, iclass 33, count 0 2006.173.22:25:25.34#ibcon#enter sib2, iclass 33, count 0 2006.173.22:25:25.34#ibcon#flushed, iclass 33, count 0 2006.173.22:25:25.34#ibcon#about to write, iclass 33, count 0 2006.173.22:25:25.34#ibcon#wrote, iclass 33, count 0 2006.173.22:25:25.34#ibcon#about to read 3, iclass 33, count 0 2006.173.22:25:25.38#ibcon#read 3, iclass 33, count 0 2006.173.22:25:25.38#ibcon#about to read 4, iclass 33, count 0 2006.173.22:25:25.38#ibcon#read 4, iclass 33, count 0 2006.173.22:25:25.38#ibcon#about to read 5, iclass 33, count 0 2006.173.22:25:25.38#ibcon#read 5, iclass 33, count 0 2006.173.22:25:25.38#ibcon#about to read 6, iclass 33, count 0 2006.173.22:25:25.38#ibcon#read 6, iclass 33, count 0 2006.173.22:25:25.38#ibcon#end of sib2, iclass 33, count 0 2006.173.22:25:25.38#ibcon#*after write, iclass 33, count 0 2006.173.22:25:25.38#ibcon#*before return 0, iclass 33, count 0 2006.173.22:25:25.38#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.22:25:25.38#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.22:25:25.38#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.22:25:25.38#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.22:25:25.39$vck44/vb=6,4 2006.173.22:25:25.39#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.22:25:25.39#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.22:25:25.39#ibcon#ireg 11 cls_cnt 2 2006.173.22:25:25.39#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.22:25:25.43#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.22:25:25.43#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.22:25:25.43#ibcon#enter wrdev, iclass 35, count 2 2006.173.22:25:25.43#ibcon#first serial, iclass 35, count 2 2006.173.22:25:25.43#ibcon#enter sib2, iclass 35, count 2 2006.173.22:25:25.43#ibcon#flushed, iclass 35, count 2 2006.173.22:25:25.43#ibcon#about to write, iclass 35, count 2 2006.173.22:25:25.43#ibcon#wrote, iclass 35, count 2 2006.173.22:25:25.43#ibcon#about to read 3, iclass 35, count 2 2006.173.22:25:25.45#ibcon#read 3, iclass 35, count 2 2006.173.22:25:25.45#ibcon#about to read 4, iclass 35, count 2 2006.173.22:25:25.45#ibcon#read 4, iclass 35, count 2 2006.173.22:25:25.45#ibcon#about to read 5, iclass 35, count 2 2006.173.22:25:25.45#ibcon#read 5, iclass 35, count 2 2006.173.22:25:25.45#ibcon#about to read 6, iclass 35, count 2 2006.173.22:25:25.45#ibcon#read 6, iclass 35, count 2 2006.173.22:25:25.45#ibcon#end of sib2, iclass 35, count 2 2006.173.22:25:25.45#ibcon#*mode == 0, iclass 35, count 2 2006.173.22:25:25.45#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.22:25:25.45#ibcon#[27=AT06-04\r\n] 2006.173.22:25:25.45#ibcon#*before write, iclass 35, count 2 2006.173.22:25:25.45#ibcon#enter sib2, iclass 35, count 2 2006.173.22:25:25.45#ibcon#flushed, iclass 35, count 2 2006.173.22:25:25.45#ibcon#about to write, iclass 35, count 2 2006.173.22:25:25.45#ibcon#wrote, iclass 35, count 2 2006.173.22:25:25.45#ibcon#about to read 3, iclass 35, count 2 2006.173.22:25:25.48#ibcon#read 3, iclass 35, count 2 2006.173.22:25:25.48#ibcon#about to read 4, iclass 35, count 2 2006.173.22:25:25.48#ibcon#read 4, iclass 35, count 2 2006.173.22:25:25.48#ibcon#about to read 5, iclass 35, count 2 2006.173.22:25:25.48#ibcon#read 5, iclass 35, count 2 2006.173.22:25:25.48#ibcon#about to read 6, iclass 35, count 2 2006.173.22:25:25.48#ibcon#read 6, iclass 35, count 2 2006.173.22:25:25.48#ibcon#end of sib2, iclass 35, count 2 2006.173.22:25:25.48#ibcon#*after write, iclass 35, count 2 2006.173.22:25:25.48#ibcon#*before return 0, iclass 35, count 2 2006.173.22:25:25.48#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.22:25:25.48#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.22:25:25.48#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.22:25:25.48#ibcon#ireg 7 cls_cnt 0 2006.173.22:25:25.48#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.22:25:25.60#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.22:25:25.60#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.22:25:25.60#ibcon#enter wrdev, iclass 35, count 0 2006.173.22:25:25.60#ibcon#first serial, iclass 35, count 0 2006.173.22:25:25.60#ibcon#enter sib2, iclass 35, count 0 2006.173.22:25:25.60#ibcon#flushed, iclass 35, count 0 2006.173.22:25:25.60#ibcon#about to write, iclass 35, count 0 2006.173.22:25:25.60#ibcon#wrote, iclass 35, count 0 2006.173.22:25:25.60#ibcon#about to read 3, iclass 35, count 0 2006.173.22:25:25.62#ibcon#read 3, iclass 35, count 0 2006.173.22:25:25.62#ibcon#about to read 4, iclass 35, count 0 2006.173.22:25:25.62#ibcon#read 4, iclass 35, count 0 2006.173.22:25:25.62#ibcon#about to read 5, iclass 35, count 0 2006.173.22:25:25.62#ibcon#read 5, iclass 35, count 0 2006.173.22:25:25.62#ibcon#about to read 6, iclass 35, count 0 2006.173.22:25:25.62#ibcon#read 6, iclass 35, count 0 2006.173.22:25:25.62#ibcon#end of sib2, iclass 35, count 0 2006.173.22:25:25.62#ibcon#*mode == 0, iclass 35, count 0 2006.173.22:25:25.62#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.22:25:25.62#ibcon#[27=USB\r\n] 2006.173.22:25:25.62#ibcon#*before write, iclass 35, count 0 2006.173.22:25:25.62#ibcon#enter sib2, iclass 35, count 0 2006.173.22:25:25.62#ibcon#flushed, iclass 35, count 0 2006.173.22:25:25.62#ibcon#about to write, iclass 35, count 0 2006.173.22:25:25.62#ibcon#wrote, iclass 35, count 0 2006.173.22:25:25.62#ibcon#about to read 3, iclass 35, count 0 2006.173.22:25:25.65#ibcon#read 3, iclass 35, count 0 2006.173.22:25:25.65#ibcon#about to read 4, iclass 35, count 0 2006.173.22:25:25.65#ibcon#read 4, iclass 35, count 0 2006.173.22:25:25.65#ibcon#about to read 5, iclass 35, count 0 2006.173.22:25:25.65#ibcon#read 5, iclass 35, count 0 2006.173.22:25:25.65#ibcon#about to read 6, iclass 35, count 0 2006.173.22:25:25.65#ibcon#read 6, iclass 35, count 0 2006.173.22:25:25.65#ibcon#end of sib2, iclass 35, count 0 2006.173.22:25:25.65#ibcon#*after write, iclass 35, count 0 2006.173.22:25:25.65#ibcon#*before return 0, iclass 35, count 0 2006.173.22:25:25.65#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.22:25:25.65#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.22:25:25.65#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.22:25:25.65#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.22:25:25.66$vck44/vblo=7,734.99 2006.173.22:25:25.66#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.22:25:25.66#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.22:25:25.66#ibcon#ireg 17 cls_cnt 0 2006.173.22:25:25.66#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.22:25:25.66#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.22:25:25.66#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.22:25:25.66#ibcon#enter wrdev, iclass 37, count 0 2006.173.22:25:25.66#ibcon#first serial, iclass 37, count 0 2006.173.22:25:25.66#ibcon#enter sib2, iclass 37, count 0 2006.173.22:25:25.66#ibcon#flushed, iclass 37, count 0 2006.173.22:25:25.66#ibcon#about to write, iclass 37, count 0 2006.173.22:25:25.66#ibcon#wrote, iclass 37, count 0 2006.173.22:25:25.66#ibcon#about to read 3, iclass 37, count 0 2006.173.22:25:25.67#ibcon#read 3, iclass 37, count 0 2006.173.22:25:25.67#ibcon#about to read 4, iclass 37, count 0 2006.173.22:25:25.67#ibcon#read 4, iclass 37, count 0 2006.173.22:25:25.67#ibcon#about to read 5, iclass 37, count 0 2006.173.22:25:25.67#ibcon#read 5, iclass 37, count 0 2006.173.22:25:25.67#ibcon#about to read 6, iclass 37, count 0 2006.173.22:25:25.67#ibcon#read 6, iclass 37, count 0 2006.173.22:25:25.67#ibcon#end of sib2, iclass 37, count 0 2006.173.22:25:25.67#ibcon#*mode == 0, iclass 37, count 0 2006.173.22:25:25.67#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.22:25:25.67#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.22:25:25.67#ibcon#*before write, iclass 37, count 0 2006.173.22:25:25.67#ibcon#enter sib2, iclass 37, count 0 2006.173.22:25:25.67#ibcon#flushed, iclass 37, count 0 2006.173.22:25:25.67#ibcon#about to write, iclass 37, count 0 2006.173.22:25:25.67#ibcon#wrote, iclass 37, count 0 2006.173.22:25:25.67#ibcon#about to read 3, iclass 37, count 0 2006.173.22:25:25.71#ibcon#read 3, iclass 37, count 0 2006.173.22:25:25.71#ibcon#about to read 4, iclass 37, count 0 2006.173.22:25:25.71#ibcon#read 4, iclass 37, count 0 2006.173.22:25:25.71#ibcon#about to read 5, iclass 37, count 0 2006.173.22:25:25.71#ibcon#read 5, iclass 37, count 0 2006.173.22:25:25.71#ibcon#about to read 6, iclass 37, count 0 2006.173.22:25:25.71#ibcon#read 6, iclass 37, count 0 2006.173.22:25:25.71#ibcon#end of sib2, iclass 37, count 0 2006.173.22:25:25.71#ibcon#*after write, iclass 37, count 0 2006.173.22:25:25.71#ibcon#*before return 0, iclass 37, count 0 2006.173.22:25:25.71#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.22:25:25.71#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.22:25:25.71#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.22:25:25.71#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.22:25:25.72$vck44/vb=7,4 2006.173.22:25:25.72#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.22:25:25.72#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.22:25:25.72#ibcon#ireg 11 cls_cnt 2 2006.173.22:25:25.72#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.22:25:25.73#abcon#<5=/09 0.4 1.3 22.37 951003.3\r\n> 2006.173.22:25:25.75#abcon#{5=INTERFACE CLEAR} 2006.173.22:25:25.76#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.22:25:25.76#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.22:25:25.76#ibcon#enter wrdev, iclass 40, count 2 2006.173.22:25:25.76#ibcon#first serial, iclass 40, count 2 2006.173.22:25:25.76#ibcon#enter sib2, iclass 40, count 2 2006.173.22:25:25.76#ibcon#flushed, iclass 40, count 2 2006.173.22:25:25.76#ibcon#about to write, iclass 40, count 2 2006.173.22:25:25.76#ibcon#wrote, iclass 40, count 2 2006.173.22:25:25.76#ibcon#about to read 3, iclass 40, count 2 2006.173.22:25:25.78#ibcon#read 3, iclass 40, count 2 2006.173.22:25:25.78#ibcon#about to read 4, iclass 40, count 2 2006.173.22:25:25.78#ibcon#read 4, iclass 40, count 2 2006.173.22:25:25.78#ibcon#about to read 5, iclass 40, count 2 2006.173.22:25:25.78#ibcon#read 5, iclass 40, count 2 2006.173.22:25:25.78#ibcon#about to read 6, iclass 40, count 2 2006.173.22:25:25.78#ibcon#read 6, iclass 40, count 2 2006.173.22:25:25.78#ibcon#end of sib2, iclass 40, count 2 2006.173.22:25:25.78#ibcon#*mode == 0, iclass 40, count 2 2006.173.22:25:25.78#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.22:25:25.78#ibcon#[27=AT07-04\r\n] 2006.173.22:25:25.78#ibcon#*before write, iclass 40, count 2 2006.173.22:25:25.78#ibcon#enter sib2, iclass 40, count 2 2006.173.22:25:25.78#ibcon#flushed, iclass 40, count 2 2006.173.22:25:25.78#ibcon#about to write, iclass 40, count 2 2006.173.22:25:25.78#ibcon#wrote, iclass 40, count 2 2006.173.22:25:25.78#ibcon#about to read 3, iclass 40, count 2 2006.173.22:25:25.81#abcon#[5=S1D000X0/0*\r\n] 2006.173.22:25:25.81#ibcon#read 3, iclass 40, count 2 2006.173.22:25:25.81#ibcon#about to read 4, iclass 40, count 2 2006.173.22:25:25.81#ibcon#read 4, iclass 40, count 2 2006.173.22:25:25.81#ibcon#about to read 5, iclass 40, count 2 2006.173.22:25:25.81#ibcon#read 5, iclass 40, count 2 2006.173.22:25:25.81#ibcon#about to read 6, iclass 40, count 2 2006.173.22:25:25.81#ibcon#read 6, iclass 40, count 2 2006.173.22:25:25.81#ibcon#end of sib2, iclass 40, count 2 2006.173.22:25:25.81#ibcon#*after write, iclass 40, count 2 2006.173.22:25:25.81#ibcon#*before return 0, iclass 40, count 2 2006.173.22:25:25.81#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.22:25:25.82#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.22:25:25.82#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.22:25:25.82#ibcon#ireg 7 cls_cnt 0 2006.173.22:25:25.82#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.22:25:25.92#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.22:25:25.92#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.22:25:25.92#ibcon#enter wrdev, iclass 40, count 0 2006.173.22:25:25.92#ibcon#first serial, iclass 40, count 0 2006.173.22:25:25.92#ibcon#enter sib2, iclass 40, count 0 2006.173.22:25:25.92#ibcon#flushed, iclass 40, count 0 2006.173.22:25:25.92#ibcon#about to write, iclass 40, count 0 2006.173.22:25:25.92#ibcon#wrote, iclass 40, count 0 2006.173.22:25:25.92#ibcon#about to read 3, iclass 40, count 0 2006.173.22:25:25.94#ibcon#read 3, iclass 40, count 0 2006.173.22:25:25.94#ibcon#about to read 4, iclass 40, count 0 2006.173.22:25:25.94#ibcon#read 4, iclass 40, count 0 2006.173.22:25:25.94#ibcon#about to read 5, iclass 40, count 0 2006.173.22:25:25.94#ibcon#read 5, iclass 40, count 0 2006.173.22:25:25.94#ibcon#about to read 6, iclass 40, count 0 2006.173.22:25:25.94#ibcon#read 6, iclass 40, count 0 2006.173.22:25:25.94#ibcon#end of sib2, iclass 40, count 0 2006.173.22:25:25.94#ibcon#*mode == 0, iclass 40, count 0 2006.173.22:25:25.94#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.22:25:25.94#ibcon#[27=USB\r\n] 2006.173.22:25:25.94#ibcon#*before write, iclass 40, count 0 2006.173.22:25:25.94#ibcon#enter sib2, iclass 40, count 0 2006.173.22:25:25.94#ibcon#flushed, iclass 40, count 0 2006.173.22:25:25.94#ibcon#about to write, iclass 40, count 0 2006.173.22:25:25.94#ibcon#wrote, iclass 40, count 0 2006.173.22:25:25.94#ibcon#about to read 3, iclass 40, count 0 2006.173.22:25:25.97#ibcon#read 3, iclass 40, count 0 2006.173.22:25:25.97#ibcon#about to read 4, iclass 40, count 0 2006.173.22:25:25.97#ibcon#read 4, iclass 40, count 0 2006.173.22:25:25.97#ibcon#about to read 5, iclass 40, count 0 2006.173.22:25:25.97#ibcon#read 5, iclass 40, count 0 2006.173.22:25:25.97#ibcon#about to read 6, iclass 40, count 0 2006.173.22:25:25.97#ibcon#read 6, iclass 40, count 0 2006.173.22:25:25.97#ibcon#end of sib2, iclass 40, count 0 2006.173.22:25:25.97#ibcon#*after write, iclass 40, count 0 2006.173.22:25:25.97#ibcon#*before return 0, iclass 40, count 0 2006.173.22:25:25.97#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.22:25:25.97#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.22:25:25.97#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.22:25:25.97#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.22:25:25.98$vck44/vblo=8,744.99 2006.173.22:25:25.98#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.22:25:25.98#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.22:25:25.98#ibcon#ireg 17 cls_cnt 0 2006.173.22:25:25.98#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.22:25:25.98#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.22:25:25.98#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.22:25:25.98#ibcon#enter wrdev, iclass 7, count 0 2006.173.22:25:25.98#ibcon#first serial, iclass 7, count 0 2006.173.22:25:25.98#ibcon#enter sib2, iclass 7, count 0 2006.173.22:25:25.98#ibcon#flushed, iclass 7, count 0 2006.173.22:25:25.98#ibcon#about to write, iclass 7, count 0 2006.173.22:25:25.98#ibcon#wrote, iclass 7, count 0 2006.173.22:25:25.98#ibcon#about to read 3, iclass 7, count 0 2006.173.22:25:25.99#ibcon#read 3, iclass 7, count 0 2006.173.22:25:25.99#ibcon#about to read 4, iclass 7, count 0 2006.173.22:25:25.99#ibcon#read 4, iclass 7, count 0 2006.173.22:25:25.99#ibcon#about to read 5, iclass 7, count 0 2006.173.22:25:25.99#ibcon#read 5, iclass 7, count 0 2006.173.22:25:25.99#ibcon#about to read 6, iclass 7, count 0 2006.173.22:25:25.99#ibcon#read 6, iclass 7, count 0 2006.173.22:25:25.99#ibcon#end of sib2, iclass 7, count 0 2006.173.22:25:25.99#ibcon#*mode == 0, iclass 7, count 0 2006.173.22:25:25.99#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.22:25:25.99#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.22:25:25.99#ibcon#*before write, iclass 7, count 0 2006.173.22:25:25.99#ibcon#enter sib2, iclass 7, count 0 2006.173.22:25:25.99#ibcon#flushed, iclass 7, count 0 2006.173.22:25:25.99#ibcon#about to write, iclass 7, count 0 2006.173.22:25:25.99#ibcon#wrote, iclass 7, count 0 2006.173.22:25:25.99#ibcon#about to read 3, iclass 7, count 0 2006.173.22:25:26.03#ibcon#read 3, iclass 7, count 0 2006.173.22:25:26.03#ibcon#about to read 4, iclass 7, count 0 2006.173.22:25:26.03#ibcon#read 4, iclass 7, count 0 2006.173.22:25:26.03#ibcon#about to read 5, iclass 7, count 0 2006.173.22:25:26.03#ibcon#read 5, iclass 7, count 0 2006.173.22:25:26.03#ibcon#about to read 6, iclass 7, count 0 2006.173.22:25:26.03#ibcon#read 6, iclass 7, count 0 2006.173.22:25:26.03#ibcon#end of sib2, iclass 7, count 0 2006.173.22:25:26.03#ibcon#*after write, iclass 7, count 0 2006.173.22:25:26.03#ibcon#*before return 0, iclass 7, count 0 2006.173.22:25:26.03#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.22:25:26.03#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.22:25:26.03#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.22:25:26.03#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.22:25:26.04$vck44/vb=8,4 2006.173.22:25:26.04#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.22:25:26.04#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.22:25:26.04#ibcon#ireg 11 cls_cnt 2 2006.173.22:25:26.04#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.22:25:26.08#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.22:25:26.08#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.22:25:26.08#ibcon#enter wrdev, iclass 11, count 2 2006.173.22:25:26.08#ibcon#first serial, iclass 11, count 2 2006.173.22:25:26.08#ibcon#enter sib2, iclass 11, count 2 2006.173.22:25:26.08#ibcon#flushed, iclass 11, count 2 2006.173.22:25:26.08#ibcon#about to write, iclass 11, count 2 2006.173.22:25:26.08#ibcon#wrote, iclass 11, count 2 2006.173.22:25:26.08#ibcon#about to read 3, iclass 11, count 2 2006.173.22:25:26.10#ibcon#read 3, iclass 11, count 2 2006.173.22:25:26.10#ibcon#about to read 4, iclass 11, count 2 2006.173.22:25:26.10#ibcon#read 4, iclass 11, count 2 2006.173.22:25:26.10#ibcon#about to read 5, iclass 11, count 2 2006.173.22:25:26.10#ibcon#read 5, iclass 11, count 2 2006.173.22:25:26.10#ibcon#about to read 6, iclass 11, count 2 2006.173.22:25:26.10#ibcon#read 6, iclass 11, count 2 2006.173.22:25:26.10#ibcon#end of sib2, iclass 11, count 2 2006.173.22:25:26.10#ibcon#*mode == 0, iclass 11, count 2 2006.173.22:25:26.10#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.22:25:26.10#ibcon#[27=AT08-04\r\n] 2006.173.22:25:26.10#ibcon#*before write, iclass 11, count 2 2006.173.22:25:26.10#ibcon#enter sib2, iclass 11, count 2 2006.173.22:25:26.10#ibcon#flushed, iclass 11, count 2 2006.173.22:25:26.10#ibcon#about to write, iclass 11, count 2 2006.173.22:25:26.10#ibcon#wrote, iclass 11, count 2 2006.173.22:25:26.11#ibcon#about to read 3, iclass 11, count 2 2006.173.22:25:26.13#ibcon#read 3, iclass 11, count 2 2006.173.22:25:26.13#ibcon#about to read 4, iclass 11, count 2 2006.173.22:25:26.13#ibcon#read 4, iclass 11, count 2 2006.173.22:25:26.13#ibcon#about to read 5, iclass 11, count 2 2006.173.22:25:26.13#ibcon#read 5, iclass 11, count 2 2006.173.22:25:26.13#ibcon#about to read 6, iclass 11, count 2 2006.173.22:25:26.13#ibcon#read 6, iclass 11, count 2 2006.173.22:25:26.13#ibcon#end of sib2, iclass 11, count 2 2006.173.22:25:26.13#ibcon#*after write, iclass 11, count 2 2006.173.22:25:26.13#ibcon#*before return 0, iclass 11, count 2 2006.173.22:25:26.13#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.22:25:26.13#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.22:25:26.13#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.22:25:26.13#ibcon#ireg 7 cls_cnt 0 2006.173.22:25:26.13#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.22:25:26.25#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.22:25:26.25#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.22:25:26.25#ibcon#enter wrdev, iclass 11, count 0 2006.173.22:25:26.25#ibcon#first serial, iclass 11, count 0 2006.173.22:25:26.25#ibcon#enter sib2, iclass 11, count 0 2006.173.22:25:26.25#ibcon#flushed, iclass 11, count 0 2006.173.22:25:26.25#ibcon#about to write, iclass 11, count 0 2006.173.22:25:26.25#ibcon#wrote, iclass 11, count 0 2006.173.22:25:26.25#ibcon#about to read 3, iclass 11, count 0 2006.173.22:25:26.27#ibcon#read 3, iclass 11, count 0 2006.173.22:25:26.27#ibcon#about to read 4, iclass 11, count 0 2006.173.22:25:26.27#ibcon#read 4, iclass 11, count 0 2006.173.22:25:26.27#ibcon#about to read 5, iclass 11, count 0 2006.173.22:25:26.27#ibcon#read 5, iclass 11, count 0 2006.173.22:25:26.27#ibcon#about to read 6, iclass 11, count 0 2006.173.22:25:26.27#ibcon#read 6, iclass 11, count 0 2006.173.22:25:26.27#ibcon#end of sib2, iclass 11, count 0 2006.173.22:25:26.27#ibcon#*mode == 0, iclass 11, count 0 2006.173.22:25:26.27#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.22:25:26.27#ibcon#[27=USB\r\n] 2006.173.22:25:26.27#ibcon#*before write, iclass 11, count 0 2006.173.22:25:26.27#ibcon#enter sib2, iclass 11, count 0 2006.173.22:25:26.27#ibcon#flushed, iclass 11, count 0 2006.173.22:25:26.27#ibcon#about to write, iclass 11, count 0 2006.173.22:25:26.27#ibcon#wrote, iclass 11, count 0 2006.173.22:25:26.27#ibcon#about to read 3, iclass 11, count 0 2006.173.22:25:26.30#ibcon#read 3, iclass 11, count 0 2006.173.22:25:26.30#ibcon#about to read 4, iclass 11, count 0 2006.173.22:25:26.30#ibcon#read 4, iclass 11, count 0 2006.173.22:25:26.30#ibcon#about to read 5, iclass 11, count 0 2006.173.22:25:26.30#ibcon#read 5, iclass 11, count 0 2006.173.22:25:26.30#ibcon#about to read 6, iclass 11, count 0 2006.173.22:25:26.30#ibcon#read 6, iclass 11, count 0 2006.173.22:25:26.30#ibcon#end of sib2, iclass 11, count 0 2006.173.22:25:26.30#ibcon#*after write, iclass 11, count 0 2006.173.22:25:26.30#ibcon#*before return 0, iclass 11, count 0 2006.173.22:25:26.30#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.22:25:26.30#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.22:25:26.30#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.22:25:26.30#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.22:25:26.31$vck44/vabw=wide 2006.173.22:25:26.31#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.22:25:26.31#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.22:25:26.31#ibcon#ireg 8 cls_cnt 0 2006.173.22:25:26.31#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.22:25:26.31#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.22:25:26.31#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.22:25:26.31#ibcon#enter wrdev, iclass 13, count 0 2006.173.22:25:26.31#ibcon#first serial, iclass 13, count 0 2006.173.22:25:26.31#ibcon#enter sib2, iclass 13, count 0 2006.173.22:25:26.31#ibcon#flushed, iclass 13, count 0 2006.173.22:25:26.31#ibcon#about to write, iclass 13, count 0 2006.173.22:25:26.31#ibcon#wrote, iclass 13, count 0 2006.173.22:25:26.31#ibcon#about to read 3, iclass 13, count 0 2006.173.22:25:26.32#ibcon#read 3, iclass 13, count 0 2006.173.22:25:26.32#ibcon#about to read 4, iclass 13, count 0 2006.173.22:25:26.32#ibcon#read 4, iclass 13, count 0 2006.173.22:25:26.32#ibcon#about to read 5, iclass 13, count 0 2006.173.22:25:26.32#ibcon#read 5, iclass 13, count 0 2006.173.22:25:26.32#ibcon#about to read 6, iclass 13, count 0 2006.173.22:25:26.32#ibcon#read 6, iclass 13, count 0 2006.173.22:25:26.32#ibcon#end of sib2, iclass 13, count 0 2006.173.22:25:26.32#ibcon#*mode == 0, iclass 13, count 0 2006.173.22:25:26.32#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.22:25:26.32#ibcon#[25=BW32\r\n] 2006.173.22:25:26.32#ibcon#*before write, iclass 13, count 0 2006.173.22:25:26.32#ibcon#enter sib2, iclass 13, count 0 2006.173.22:25:26.32#ibcon#flushed, iclass 13, count 0 2006.173.22:25:26.32#ibcon#about to write, iclass 13, count 0 2006.173.22:25:26.32#ibcon#wrote, iclass 13, count 0 2006.173.22:25:26.32#ibcon#about to read 3, iclass 13, count 0 2006.173.22:25:26.35#ibcon#read 3, iclass 13, count 0 2006.173.22:25:26.35#ibcon#about to read 4, iclass 13, count 0 2006.173.22:25:26.35#ibcon#read 4, iclass 13, count 0 2006.173.22:25:26.35#ibcon#about to read 5, iclass 13, count 0 2006.173.22:25:26.35#ibcon#read 5, iclass 13, count 0 2006.173.22:25:26.35#ibcon#about to read 6, iclass 13, count 0 2006.173.22:25:26.35#ibcon#read 6, iclass 13, count 0 2006.173.22:25:26.35#ibcon#end of sib2, iclass 13, count 0 2006.173.22:25:26.35#ibcon#*after write, iclass 13, count 0 2006.173.22:25:26.35#ibcon#*before return 0, iclass 13, count 0 2006.173.22:25:26.35#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.22:25:26.35#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.22:25:26.35#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.22:25:26.35#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.22:25:26.36$vck44/vbbw=wide 2006.173.22:25:26.36#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.22:25:26.36#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.22:25:26.36#ibcon#ireg 8 cls_cnt 0 2006.173.22:25:26.36#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.22:25:26.41#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.22:25:26.41#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.22:25:26.41#ibcon#enter wrdev, iclass 15, count 0 2006.173.22:25:26.41#ibcon#first serial, iclass 15, count 0 2006.173.22:25:26.41#ibcon#enter sib2, iclass 15, count 0 2006.173.22:25:26.41#ibcon#flushed, iclass 15, count 0 2006.173.22:25:26.41#ibcon#about to write, iclass 15, count 0 2006.173.22:25:26.41#ibcon#wrote, iclass 15, count 0 2006.173.22:25:26.41#ibcon#about to read 3, iclass 15, count 0 2006.173.22:25:26.43#ibcon#read 3, iclass 15, count 0 2006.173.22:25:26.43#ibcon#about to read 4, iclass 15, count 0 2006.173.22:25:26.43#ibcon#read 4, iclass 15, count 0 2006.173.22:25:26.43#ibcon#about to read 5, iclass 15, count 0 2006.173.22:25:26.43#ibcon#read 5, iclass 15, count 0 2006.173.22:25:26.43#ibcon#about to read 6, iclass 15, count 0 2006.173.22:25:26.43#ibcon#read 6, iclass 15, count 0 2006.173.22:25:26.43#ibcon#end of sib2, iclass 15, count 0 2006.173.22:25:26.43#ibcon#*mode == 0, iclass 15, count 0 2006.173.22:25:26.43#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.22:25:26.43#ibcon#[27=BW32\r\n] 2006.173.22:25:26.43#ibcon#*before write, iclass 15, count 0 2006.173.22:25:26.43#ibcon#enter sib2, iclass 15, count 0 2006.173.22:25:26.43#ibcon#flushed, iclass 15, count 0 2006.173.22:25:26.43#ibcon#about to write, iclass 15, count 0 2006.173.22:25:26.43#ibcon#wrote, iclass 15, count 0 2006.173.22:25:26.43#ibcon#about to read 3, iclass 15, count 0 2006.173.22:25:26.46#ibcon#read 3, iclass 15, count 0 2006.173.22:25:26.46#ibcon#about to read 4, iclass 15, count 0 2006.173.22:25:26.46#ibcon#read 4, iclass 15, count 0 2006.173.22:25:26.46#ibcon#about to read 5, iclass 15, count 0 2006.173.22:25:26.46#ibcon#read 5, iclass 15, count 0 2006.173.22:25:26.46#ibcon#about to read 6, iclass 15, count 0 2006.173.22:25:26.46#ibcon#read 6, iclass 15, count 0 2006.173.22:25:26.46#ibcon#end of sib2, iclass 15, count 0 2006.173.22:25:26.46#ibcon#*after write, iclass 15, count 0 2006.173.22:25:26.46#ibcon#*before return 0, iclass 15, count 0 2006.173.22:25:26.46#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.22:25:26.46#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.22:25:26.46#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.22:25:26.46#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.22:25:26.47$setupk4/ifdk4 2006.173.22:25:26.47$ifdk4/lo= 2006.173.22:25:26.47$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.22:25:26.47$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.22:25:26.47$ifdk4/patch= 2006.173.22:25:26.47$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.22:25:26.47$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.22:25:26.47$setupk4/!*+20s 2006.173.22:25:32.13#trakl#Source acquired 2006.173.22:25:34.14#flagr#flagr/antenna,acquired 2006.173.22:25:35.90#abcon#<5=/09 0.4 1.3 22.37 941003.3\r\n> 2006.173.22:25:35.92#abcon#{5=INTERFACE CLEAR} 2006.173.22:25:35.98#abcon#[5=S1D000X0/0*\r\n] 2006.173.22:25:41.14$setupk4/"tpicd 2006.173.22:25:41.14$setupk4/echo=off 2006.173.22:25:41.14$setupk4/xlog=off 2006.173.22:25:41.14:!2006.173.22:27:26 2006.173.22:27:26.01:preob 2006.173.22:27:27.14/onsource/TRACKING 2006.173.22:27:27.14:!2006.173.22:27:36 2006.173.22:27:36.00:"tape 2006.173.22:27:36.00:"st=record 2006.173.22:27:36.00:data_valid=on 2006.173.22:27:36.00:midob 2006.173.22:27:36.14/onsource/TRACKING 2006.173.22:27:36.15/wx/22.39,1003.3,93 2006.173.22:27:36.21/cable/+6.5153E-03 2006.173.22:27:37.30/va/01,07,usb,yes,34,37 2006.173.22:27:37.30/va/02,06,usb,yes,34,35 2006.173.22:27:37.30/va/03,05,usb,yes,44,46 2006.173.22:27:37.30/va/04,06,usb,yes,35,37 2006.173.22:27:37.30/va/05,04,usb,yes,27,28 2006.173.22:27:37.30/va/06,03,usb,yes,38,38 2006.173.22:27:37.30/va/07,04,usb,yes,31,32 2006.173.22:27:37.30/va/08,04,usb,yes,26,32 2006.173.22:27:37.53/valo/01,524.99,yes,locked 2006.173.22:27:37.53/valo/02,534.99,yes,locked 2006.173.22:27:37.53/valo/03,564.99,yes,locked 2006.173.22:27:37.53/valo/04,624.99,yes,locked 2006.173.22:27:37.53/valo/05,734.99,yes,locked 2006.173.22:27:37.53/valo/06,814.99,yes,locked 2006.173.22:27:37.53/valo/07,864.99,yes,locked 2006.173.22:27:37.53/valo/08,884.99,yes,locked 2006.173.22:27:38.62/vb/01,04,usb,yes,29,27 2006.173.22:27:38.62/vb/02,04,usb,yes,31,31 2006.173.22:27:38.62/vb/03,04,usb,yes,28,31 2006.173.22:27:38.62/vb/04,04,usb,yes,32,31 2006.173.22:27:38.62/vb/05,04,usb,yes,25,27 2006.173.22:27:38.62/vb/06,04,usb,yes,29,26 2006.173.22:27:38.62/vb/07,04,usb,yes,29,29 2006.173.22:27:38.62/vb/08,04,usb,yes,27,30 2006.173.22:27:38.86/vblo/01,629.99,yes,locked 2006.173.22:27:38.86/vblo/02,634.99,yes,locked 2006.173.22:27:38.86/vblo/03,649.99,yes,locked 2006.173.22:27:38.86/vblo/04,679.99,yes,locked 2006.173.22:27:38.86/vblo/05,709.99,yes,locked 2006.173.22:27:38.86/vblo/06,719.99,yes,locked 2006.173.22:27:38.86/vblo/07,734.99,yes,locked 2006.173.22:27:38.86/vblo/08,744.99,yes,locked 2006.173.22:27:39.01/vabw/8 2006.173.22:27:39.16/vbbw/8 2006.173.22:27:39.25/xfe/off,on,14.7 2006.173.22:27:39.64/ifatt/23,28,28,28 2006.173.22:27:40.07/fmout-gps/S +3.78E-07 2006.173.22:27:40.11:!2006.173.22:32:46 2006.173.22:32:46.00:data_valid=off 2006.173.22:32:46.00:"et 2006.173.22:32:46.00:!+3s 2006.173.22:32:49.01:"tape 2006.173.22:32:49.01:postob 2006.173.22:32:49.12/cable/+6.5139E-03 2006.173.22:32:49.12/wx/22.39,1003.3,90 2006.173.22:32:50.08/fmout-gps/S +3.80E-07 2006.173.22:32:50.08:scan_name=173-2237,jd0606,230 2006.173.22:32:50.08:source=cta26,033930.94,-014635.8,2000.0,ccw 2006.173.22:32:51.14#flagr#flagr/antenna,new-source 2006.173.22:32:51.14:checkk5 2006.173.22:32:51.50/chk_autoobs//k5ts1/ autoobs is running! 2006.173.22:32:51.88/chk_autoobs//k5ts2/ autoobs is running! 2006.173.22:32:52.27/chk_autoobs//k5ts3/ autoobs is running! 2006.173.22:32:52.68/chk_autoobs//k5ts4/ autoobs is running! 2006.173.22:32:53.08/chk_obsdata//k5ts1/T1732227??a.dat file size is correct (nominal:1240MB, actual:1236MB). 2006.173.22:32:53.49/chk_obsdata//k5ts2/T1732227??b.dat file size is correct (nominal:1240MB, actual:1236MB). 2006.173.22:32:53.90/chk_obsdata//k5ts3/T1732227??c.dat file size is correct (nominal:1240MB, actual:1236MB). 2006.173.22:32:54.30/chk_obsdata//k5ts4/T1732227??d.dat file size is correct (nominal:1240MB, actual:1236MB). 2006.173.22:32:55.02/k5log//k5ts1_log_newline 2006.173.22:32:55.73/k5log//k5ts2_log_newline 2006.173.22:32:56.43/k5log//k5ts3_log_newline 2006.173.22:32:57.14/k5log//k5ts4_log_newline 2006.173.22:32:57.16/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.22:32:57.16:setupk4=1 2006.173.22:32:57.16$setupk4/echo=on 2006.173.22:32:57.16$setupk4/pcalon 2006.173.22:32:57.16$pcalon/"no phase cal control is implemented here 2006.173.22:32:57.16$setupk4/"tpicd=stop 2006.173.22:32:57.16$setupk4/"rec=synch_on 2006.173.22:32:57.16$setupk4/"rec_mode=128 2006.173.22:32:57.16$setupk4/!* 2006.173.22:32:57.16$setupk4/recpk4 2006.173.22:32:57.16$recpk4/recpatch= 2006.173.22:32:57.17$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.22:32:57.17$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.22:32:57.17$setupk4/vck44 2006.173.22:32:57.17$vck44/valo=1,524.99 2006.173.22:32:57.17#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.22:32:57.17#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.22:32:57.17#ibcon#ireg 17 cls_cnt 0 2006.173.22:32:57.17#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.22:32:57.17#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.22:32:57.17#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.22:32:57.17#ibcon#enter wrdev, iclass 16, count 0 2006.173.22:32:57.17#ibcon#first serial, iclass 16, count 0 2006.173.22:32:57.17#ibcon#enter sib2, iclass 16, count 0 2006.173.22:32:57.17#ibcon#flushed, iclass 16, count 0 2006.173.22:32:57.17#ibcon#about to write, iclass 16, count 0 2006.173.22:32:57.17#ibcon#wrote, iclass 16, count 0 2006.173.22:32:57.17#ibcon#about to read 3, iclass 16, count 0 2006.173.22:32:57.18#ibcon#read 3, iclass 16, count 0 2006.173.22:32:57.18#ibcon#about to read 4, iclass 16, count 0 2006.173.22:32:57.18#ibcon#read 4, iclass 16, count 0 2006.173.22:32:57.18#ibcon#about to read 5, iclass 16, count 0 2006.173.22:32:57.18#ibcon#read 5, iclass 16, count 0 2006.173.22:32:57.18#ibcon#about to read 6, iclass 16, count 0 2006.173.22:32:57.18#ibcon#read 6, iclass 16, count 0 2006.173.22:32:57.18#ibcon#end of sib2, iclass 16, count 0 2006.173.22:32:57.18#ibcon#*mode == 0, iclass 16, count 0 2006.173.22:32:57.18#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.22:32:57.18#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.22:32:57.18#ibcon#*before write, iclass 16, count 0 2006.173.22:32:57.18#ibcon#enter sib2, iclass 16, count 0 2006.173.22:32:57.18#ibcon#flushed, iclass 16, count 0 2006.173.22:32:57.18#ibcon#about to write, iclass 16, count 0 2006.173.22:32:57.18#ibcon#wrote, iclass 16, count 0 2006.173.22:32:57.18#ibcon#about to read 3, iclass 16, count 0 2006.173.22:32:57.23#ibcon#read 3, iclass 16, count 0 2006.173.22:32:57.23#ibcon#about to read 4, iclass 16, count 0 2006.173.22:32:57.23#ibcon#read 4, iclass 16, count 0 2006.173.22:32:57.23#ibcon#about to read 5, iclass 16, count 0 2006.173.22:32:57.23#ibcon#read 5, iclass 16, count 0 2006.173.22:32:57.23#ibcon#about to read 6, iclass 16, count 0 2006.173.22:32:57.23#ibcon#read 6, iclass 16, count 0 2006.173.22:32:57.23#ibcon#end of sib2, iclass 16, count 0 2006.173.22:32:57.23#ibcon#*after write, iclass 16, count 0 2006.173.22:32:57.23#ibcon#*before return 0, iclass 16, count 0 2006.173.22:32:57.23#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.22:32:57.23#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.22:32:57.23#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.22:32:57.23#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.22:32:57.23$vck44/va=1,7 2006.173.22:32:57.23#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.22:32:57.23#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.22:32:57.23#ibcon#ireg 11 cls_cnt 2 2006.173.22:32:57.23#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.22:32:57.23#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.22:32:57.23#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.22:32:57.23#ibcon#enter wrdev, iclass 18, count 2 2006.173.22:32:57.23#ibcon#first serial, iclass 18, count 2 2006.173.22:32:57.23#ibcon#enter sib2, iclass 18, count 2 2006.173.22:32:57.23#ibcon#flushed, iclass 18, count 2 2006.173.22:32:57.23#ibcon#about to write, iclass 18, count 2 2006.173.22:32:57.23#ibcon#wrote, iclass 18, count 2 2006.173.22:32:57.23#ibcon#about to read 3, iclass 18, count 2 2006.173.22:32:57.25#ibcon#read 3, iclass 18, count 2 2006.173.22:32:57.25#ibcon#about to read 4, iclass 18, count 2 2006.173.22:32:57.25#ibcon#read 4, iclass 18, count 2 2006.173.22:32:57.25#ibcon#about to read 5, iclass 18, count 2 2006.173.22:32:57.25#ibcon#read 5, iclass 18, count 2 2006.173.22:32:57.25#ibcon#about to read 6, iclass 18, count 2 2006.173.22:32:57.25#ibcon#read 6, iclass 18, count 2 2006.173.22:32:57.25#ibcon#end of sib2, iclass 18, count 2 2006.173.22:32:57.25#ibcon#*mode == 0, iclass 18, count 2 2006.173.22:32:57.25#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.22:32:57.25#ibcon#[25=AT01-07\r\n] 2006.173.22:32:57.25#ibcon#*before write, iclass 18, count 2 2006.173.22:32:57.25#ibcon#enter sib2, iclass 18, count 2 2006.173.22:32:57.25#ibcon#flushed, iclass 18, count 2 2006.173.22:32:57.25#ibcon#about to write, iclass 18, count 2 2006.173.22:32:57.25#ibcon#wrote, iclass 18, count 2 2006.173.22:32:57.25#ibcon#about to read 3, iclass 18, count 2 2006.173.22:32:57.28#ibcon#read 3, iclass 18, count 2 2006.173.22:32:57.28#ibcon#about to read 4, iclass 18, count 2 2006.173.22:32:57.28#ibcon#read 4, iclass 18, count 2 2006.173.22:32:57.28#ibcon#about to read 5, iclass 18, count 2 2006.173.22:32:57.28#ibcon#read 5, iclass 18, count 2 2006.173.22:32:57.28#ibcon#about to read 6, iclass 18, count 2 2006.173.22:32:57.28#ibcon#read 6, iclass 18, count 2 2006.173.22:32:57.28#ibcon#end of sib2, iclass 18, count 2 2006.173.22:32:57.28#ibcon#*after write, iclass 18, count 2 2006.173.22:32:57.28#ibcon#*before return 0, iclass 18, count 2 2006.173.22:32:57.28#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.22:32:57.28#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.22:32:57.28#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.22:32:57.28#ibcon#ireg 7 cls_cnt 0 2006.173.22:32:57.28#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.22:32:57.40#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.22:32:57.40#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.22:32:57.40#ibcon#enter wrdev, iclass 18, count 0 2006.173.22:32:57.40#ibcon#first serial, iclass 18, count 0 2006.173.22:32:57.40#ibcon#enter sib2, iclass 18, count 0 2006.173.22:32:57.40#ibcon#flushed, iclass 18, count 0 2006.173.22:32:57.40#ibcon#about to write, iclass 18, count 0 2006.173.22:32:57.40#ibcon#wrote, iclass 18, count 0 2006.173.22:32:57.40#ibcon#about to read 3, iclass 18, count 0 2006.173.22:32:57.42#ibcon#read 3, iclass 18, count 0 2006.173.22:32:57.42#ibcon#about to read 4, iclass 18, count 0 2006.173.22:32:57.42#ibcon#read 4, iclass 18, count 0 2006.173.22:32:57.42#ibcon#about to read 5, iclass 18, count 0 2006.173.22:32:57.42#ibcon#read 5, iclass 18, count 0 2006.173.22:32:57.42#ibcon#about to read 6, iclass 18, count 0 2006.173.22:32:57.42#ibcon#read 6, iclass 18, count 0 2006.173.22:32:57.42#ibcon#end of sib2, iclass 18, count 0 2006.173.22:32:57.42#ibcon#*mode == 0, iclass 18, count 0 2006.173.22:32:57.42#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.22:32:57.42#ibcon#[25=USB\r\n] 2006.173.22:32:57.42#ibcon#*before write, iclass 18, count 0 2006.173.22:32:57.42#ibcon#enter sib2, iclass 18, count 0 2006.173.22:32:57.42#ibcon#flushed, iclass 18, count 0 2006.173.22:32:57.42#ibcon#about to write, iclass 18, count 0 2006.173.22:32:57.42#ibcon#wrote, iclass 18, count 0 2006.173.22:32:57.42#ibcon#about to read 3, iclass 18, count 0 2006.173.22:32:57.45#ibcon#read 3, iclass 18, count 0 2006.173.22:32:57.45#ibcon#about to read 4, iclass 18, count 0 2006.173.22:32:57.45#ibcon#read 4, iclass 18, count 0 2006.173.22:32:57.45#ibcon#about to read 5, iclass 18, count 0 2006.173.22:32:57.45#ibcon#read 5, iclass 18, count 0 2006.173.22:32:57.45#ibcon#about to read 6, iclass 18, count 0 2006.173.22:32:57.45#ibcon#read 6, iclass 18, count 0 2006.173.22:32:57.45#ibcon#end of sib2, iclass 18, count 0 2006.173.22:32:57.45#ibcon#*after write, iclass 18, count 0 2006.173.22:32:57.45#ibcon#*before return 0, iclass 18, count 0 2006.173.22:32:57.45#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.22:32:57.45#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.22:32:57.45#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.22:32:57.45#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.22:32:57.45$vck44/valo=2,534.99 2006.173.22:32:57.45#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.22:32:57.45#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.22:32:57.45#ibcon#ireg 17 cls_cnt 0 2006.173.22:32:57.45#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.22:32:57.45#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.22:32:57.45#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.22:32:57.45#ibcon#enter wrdev, iclass 20, count 0 2006.173.22:32:57.45#ibcon#first serial, iclass 20, count 0 2006.173.22:32:57.45#ibcon#enter sib2, iclass 20, count 0 2006.173.22:32:57.45#ibcon#flushed, iclass 20, count 0 2006.173.22:32:57.45#ibcon#about to write, iclass 20, count 0 2006.173.22:32:57.45#ibcon#wrote, iclass 20, count 0 2006.173.22:32:57.45#ibcon#about to read 3, iclass 20, count 0 2006.173.22:32:57.47#ibcon#read 3, iclass 20, count 0 2006.173.22:32:57.47#ibcon#about to read 4, iclass 20, count 0 2006.173.22:32:57.47#ibcon#read 4, iclass 20, count 0 2006.173.22:32:57.47#ibcon#about to read 5, iclass 20, count 0 2006.173.22:32:57.47#ibcon#read 5, iclass 20, count 0 2006.173.22:32:57.47#ibcon#about to read 6, iclass 20, count 0 2006.173.22:32:57.47#ibcon#read 6, iclass 20, count 0 2006.173.22:32:57.47#ibcon#end of sib2, iclass 20, count 0 2006.173.22:32:57.47#ibcon#*mode == 0, iclass 20, count 0 2006.173.22:32:57.47#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.22:32:57.47#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.22:32:57.47#ibcon#*before write, iclass 20, count 0 2006.173.22:32:57.47#ibcon#enter sib2, iclass 20, count 0 2006.173.22:32:57.47#ibcon#flushed, iclass 20, count 0 2006.173.22:32:57.47#ibcon#about to write, iclass 20, count 0 2006.173.22:32:57.47#ibcon#wrote, iclass 20, count 0 2006.173.22:32:57.47#ibcon#about to read 3, iclass 20, count 0 2006.173.22:32:57.51#ibcon#read 3, iclass 20, count 0 2006.173.22:32:57.51#ibcon#about to read 4, iclass 20, count 0 2006.173.22:32:57.51#ibcon#read 4, iclass 20, count 0 2006.173.22:32:57.51#ibcon#about to read 5, iclass 20, count 0 2006.173.22:32:57.51#ibcon#read 5, iclass 20, count 0 2006.173.22:32:57.51#ibcon#about to read 6, iclass 20, count 0 2006.173.22:32:57.51#ibcon#read 6, iclass 20, count 0 2006.173.22:32:57.51#ibcon#end of sib2, iclass 20, count 0 2006.173.22:32:57.51#ibcon#*after write, iclass 20, count 0 2006.173.22:32:57.51#ibcon#*before return 0, iclass 20, count 0 2006.173.22:32:57.51#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.22:32:57.51#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.22:32:57.51#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.22:32:57.51#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.22:32:57.51$vck44/va=2,6 2006.173.22:32:57.51#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.22:32:57.51#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.22:32:57.51#ibcon#ireg 11 cls_cnt 2 2006.173.22:32:57.51#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.22:32:57.57#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.22:32:57.57#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.22:32:57.57#ibcon#enter wrdev, iclass 22, count 2 2006.173.22:32:57.57#ibcon#first serial, iclass 22, count 2 2006.173.22:32:57.57#ibcon#enter sib2, iclass 22, count 2 2006.173.22:32:57.57#ibcon#flushed, iclass 22, count 2 2006.173.22:32:57.57#ibcon#about to write, iclass 22, count 2 2006.173.22:32:57.57#ibcon#wrote, iclass 22, count 2 2006.173.22:32:57.57#ibcon#about to read 3, iclass 22, count 2 2006.173.22:32:57.59#ibcon#read 3, iclass 22, count 2 2006.173.22:32:57.59#ibcon#about to read 4, iclass 22, count 2 2006.173.22:32:57.59#ibcon#read 4, iclass 22, count 2 2006.173.22:32:57.59#ibcon#about to read 5, iclass 22, count 2 2006.173.22:32:57.59#ibcon#read 5, iclass 22, count 2 2006.173.22:32:57.59#ibcon#about to read 6, iclass 22, count 2 2006.173.22:32:57.59#ibcon#read 6, iclass 22, count 2 2006.173.22:32:57.59#ibcon#end of sib2, iclass 22, count 2 2006.173.22:32:57.59#ibcon#*mode == 0, iclass 22, count 2 2006.173.22:32:57.59#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.22:32:57.59#ibcon#[25=AT02-06\r\n] 2006.173.22:32:57.59#ibcon#*before write, iclass 22, count 2 2006.173.22:32:57.59#ibcon#enter sib2, iclass 22, count 2 2006.173.22:32:57.59#ibcon#flushed, iclass 22, count 2 2006.173.22:32:57.59#ibcon#about to write, iclass 22, count 2 2006.173.22:32:57.59#ibcon#wrote, iclass 22, count 2 2006.173.22:32:57.59#ibcon#about to read 3, iclass 22, count 2 2006.173.22:32:57.62#ibcon#read 3, iclass 22, count 2 2006.173.22:32:57.62#ibcon#about to read 4, iclass 22, count 2 2006.173.22:32:57.62#ibcon#read 4, iclass 22, count 2 2006.173.22:32:57.62#ibcon#about to read 5, iclass 22, count 2 2006.173.22:32:57.62#ibcon#read 5, iclass 22, count 2 2006.173.22:32:57.62#ibcon#about to read 6, iclass 22, count 2 2006.173.22:32:57.62#ibcon#read 6, iclass 22, count 2 2006.173.22:32:57.62#ibcon#end of sib2, iclass 22, count 2 2006.173.22:32:57.62#ibcon#*after write, iclass 22, count 2 2006.173.22:32:57.62#ibcon#*before return 0, iclass 22, count 2 2006.173.22:32:57.62#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.22:32:57.62#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.22:32:57.62#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.22:32:57.62#ibcon#ireg 7 cls_cnt 0 2006.173.22:32:57.62#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.22:32:57.74#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.22:32:57.74#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.22:32:57.74#ibcon#enter wrdev, iclass 22, count 0 2006.173.22:32:57.74#ibcon#first serial, iclass 22, count 0 2006.173.22:32:57.74#ibcon#enter sib2, iclass 22, count 0 2006.173.22:32:57.74#ibcon#flushed, iclass 22, count 0 2006.173.22:32:57.74#ibcon#about to write, iclass 22, count 0 2006.173.22:32:57.74#ibcon#wrote, iclass 22, count 0 2006.173.22:32:57.74#ibcon#about to read 3, iclass 22, count 0 2006.173.22:32:57.76#ibcon#read 3, iclass 22, count 0 2006.173.22:32:57.76#ibcon#about to read 4, iclass 22, count 0 2006.173.22:32:57.76#ibcon#read 4, iclass 22, count 0 2006.173.22:32:57.76#ibcon#about to read 5, iclass 22, count 0 2006.173.22:32:57.76#ibcon#read 5, iclass 22, count 0 2006.173.22:32:57.76#ibcon#about to read 6, iclass 22, count 0 2006.173.22:32:57.76#ibcon#read 6, iclass 22, count 0 2006.173.22:32:57.76#ibcon#end of sib2, iclass 22, count 0 2006.173.22:32:57.76#ibcon#*mode == 0, iclass 22, count 0 2006.173.22:32:57.76#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.22:32:57.76#ibcon#[25=USB\r\n] 2006.173.22:32:57.76#ibcon#*before write, iclass 22, count 0 2006.173.22:32:57.76#ibcon#enter sib2, iclass 22, count 0 2006.173.22:32:57.76#ibcon#flushed, iclass 22, count 0 2006.173.22:32:57.76#ibcon#about to write, iclass 22, count 0 2006.173.22:32:57.76#ibcon#wrote, iclass 22, count 0 2006.173.22:32:57.76#ibcon#about to read 3, iclass 22, count 0 2006.173.22:32:57.79#ibcon#read 3, iclass 22, count 0 2006.173.22:32:57.79#ibcon#about to read 4, iclass 22, count 0 2006.173.22:32:57.79#ibcon#read 4, iclass 22, count 0 2006.173.22:32:57.79#ibcon#about to read 5, iclass 22, count 0 2006.173.22:32:57.79#ibcon#read 5, iclass 22, count 0 2006.173.22:32:57.79#ibcon#about to read 6, iclass 22, count 0 2006.173.22:32:57.79#ibcon#read 6, iclass 22, count 0 2006.173.22:32:57.79#ibcon#end of sib2, iclass 22, count 0 2006.173.22:32:57.79#ibcon#*after write, iclass 22, count 0 2006.173.22:32:57.79#ibcon#*before return 0, iclass 22, count 0 2006.173.22:32:57.79#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.22:32:57.79#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.22:32:57.79#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.22:32:57.79#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.22:32:57.79$vck44/valo=3,564.99 2006.173.22:32:57.79#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.22:32:57.79#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.22:32:57.79#ibcon#ireg 17 cls_cnt 0 2006.173.22:32:57.79#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.22:32:57.79#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.22:32:57.79#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.22:32:57.79#ibcon#enter wrdev, iclass 24, count 0 2006.173.22:32:57.79#ibcon#first serial, iclass 24, count 0 2006.173.22:32:57.79#ibcon#enter sib2, iclass 24, count 0 2006.173.22:32:57.79#ibcon#flushed, iclass 24, count 0 2006.173.22:32:57.79#ibcon#about to write, iclass 24, count 0 2006.173.22:32:57.79#ibcon#wrote, iclass 24, count 0 2006.173.22:32:57.79#ibcon#about to read 3, iclass 24, count 0 2006.173.22:32:57.81#ibcon#read 3, iclass 24, count 0 2006.173.22:32:57.81#ibcon#about to read 4, iclass 24, count 0 2006.173.22:32:57.81#ibcon#read 4, iclass 24, count 0 2006.173.22:32:57.81#ibcon#about to read 5, iclass 24, count 0 2006.173.22:32:57.81#ibcon#read 5, iclass 24, count 0 2006.173.22:32:57.81#ibcon#about to read 6, iclass 24, count 0 2006.173.22:32:57.81#ibcon#read 6, iclass 24, count 0 2006.173.22:32:57.81#ibcon#end of sib2, iclass 24, count 0 2006.173.22:32:57.81#ibcon#*mode == 0, iclass 24, count 0 2006.173.22:32:57.81#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.22:32:57.81#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.22:32:57.81#ibcon#*before write, iclass 24, count 0 2006.173.22:32:57.81#ibcon#enter sib2, iclass 24, count 0 2006.173.22:32:57.81#ibcon#flushed, iclass 24, count 0 2006.173.22:32:57.81#ibcon#about to write, iclass 24, count 0 2006.173.22:32:57.81#ibcon#wrote, iclass 24, count 0 2006.173.22:32:57.81#ibcon#about to read 3, iclass 24, count 0 2006.173.22:32:57.85#ibcon#read 3, iclass 24, count 0 2006.173.22:32:57.85#ibcon#about to read 4, iclass 24, count 0 2006.173.22:32:57.85#ibcon#read 4, iclass 24, count 0 2006.173.22:32:57.85#ibcon#about to read 5, iclass 24, count 0 2006.173.22:32:57.85#ibcon#read 5, iclass 24, count 0 2006.173.22:32:57.85#ibcon#about to read 6, iclass 24, count 0 2006.173.22:32:57.85#ibcon#read 6, iclass 24, count 0 2006.173.22:32:57.85#ibcon#end of sib2, iclass 24, count 0 2006.173.22:32:57.85#ibcon#*after write, iclass 24, count 0 2006.173.22:32:57.85#ibcon#*before return 0, iclass 24, count 0 2006.173.22:32:57.85#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.22:32:57.85#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.22:32:57.85#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.22:32:57.85#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.22:32:57.85$vck44/va=3,5 2006.173.22:32:57.85#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.22:32:57.85#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.22:32:57.85#ibcon#ireg 11 cls_cnt 2 2006.173.22:32:57.85#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.22:32:57.91#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.22:32:57.91#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.22:32:57.91#ibcon#enter wrdev, iclass 26, count 2 2006.173.22:32:57.91#ibcon#first serial, iclass 26, count 2 2006.173.22:32:57.91#ibcon#enter sib2, iclass 26, count 2 2006.173.22:32:57.91#ibcon#flushed, iclass 26, count 2 2006.173.22:32:57.91#ibcon#about to write, iclass 26, count 2 2006.173.22:32:57.91#ibcon#wrote, iclass 26, count 2 2006.173.22:32:57.91#ibcon#about to read 3, iclass 26, count 2 2006.173.22:32:57.93#ibcon#read 3, iclass 26, count 2 2006.173.22:32:57.93#ibcon#about to read 4, iclass 26, count 2 2006.173.22:32:57.93#ibcon#read 4, iclass 26, count 2 2006.173.22:32:57.93#ibcon#about to read 5, iclass 26, count 2 2006.173.22:32:57.93#ibcon#read 5, iclass 26, count 2 2006.173.22:32:57.93#ibcon#about to read 6, iclass 26, count 2 2006.173.22:32:57.93#ibcon#read 6, iclass 26, count 2 2006.173.22:32:57.93#ibcon#end of sib2, iclass 26, count 2 2006.173.22:32:57.93#ibcon#*mode == 0, iclass 26, count 2 2006.173.22:32:57.93#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.22:32:57.93#ibcon#[25=AT03-05\r\n] 2006.173.22:32:57.93#ibcon#*before write, iclass 26, count 2 2006.173.22:32:57.93#ibcon#enter sib2, iclass 26, count 2 2006.173.22:32:57.93#ibcon#flushed, iclass 26, count 2 2006.173.22:32:57.93#ibcon#about to write, iclass 26, count 2 2006.173.22:32:57.93#ibcon#wrote, iclass 26, count 2 2006.173.22:32:57.93#ibcon#about to read 3, iclass 26, count 2 2006.173.22:32:57.96#ibcon#read 3, iclass 26, count 2 2006.173.22:32:57.96#ibcon#about to read 4, iclass 26, count 2 2006.173.22:32:57.96#ibcon#read 4, iclass 26, count 2 2006.173.22:32:57.96#ibcon#about to read 5, iclass 26, count 2 2006.173.22:32:57.96#ibcon#read 5, iclass 26, count 2 2006.173.22:32:57.96#ibcon#about to read 6, iclass 26, count 2 2006.173.22:32:57.96#ibcon#read 6, iclass 26, count 2 2006.173.22:32:57.96#ibcon#end of sib2, iclass 26, count 2 2006.173.22:32:57.96#ibcon#*after write, iclass 26, count 2 2006.173.22:32:57.96#ibcon#*before return 0, iclass 26, count 2 2006.173.22:32:57.96#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.22:32:57.96#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.22:32:57.96#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.22:32:57.96#ibcon#ireg 7 cls_cnt 0 2006.173.22:32:57.96#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.22:32:58.08#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.22:32:58.08#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.22:32:58.08#ibcon#enter wrdev, iclass 26, count 0 2006.173.22:32:58.08#ibcon#first serial, iclass 26, count 0 2006.173.22:32:58.08#ibcon#enter sib2, iclass 26, count 0 2006.173.22:32:58.08#ibcon#flushed, iclass 26, count 0 2006.173.22:32:58.08#ibcon#about to write, iclass 26, count 0 2006.173.22:32:58.08#ibcon#wrote, iclass 26, count 0 2006.173.22:32:58.08#ibcon#about to read 3, iclass 26, count 0 2006.173.22:32:58.10#ibcon#read 3, iclass 26, count 0 2006.173.22:32:58.10#ibcon#about to read 4, iclass 26, count 0 2006.173.22:32:58.10#ibcon#read 4, iclass 26, count 0 2006.173.22:32:58.10#ibcon#about to read 5, iclass 26, count 0 2006.173.22:32:58.10#ibcon#read 5, iclass 26, count 0 2006.173.22:32:58.10#ibcon#about to read 6, iclass 26, count 0 2006.173.22:32:58.10#ibcon#read 6, iclass 26, count 0 2006.173.22:32:58.10#ibcon#end of sib2, iclass 26, count 0 2006.173.22:32:58.10#ibcon#*mode == 0, iclass 26, count 0 2006.173.22:32:58.10#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.22:32:58.10#ibcon#[25=USB\r\n] 2006.173.22:32:58.10#ibcon#*before write, iclass 26, count 0 2006.173.22:32:58.10#ibcon#enter sib2, iclass 26, count 0 2006.173.22:32:58.10#ibcon#flushed, iclass 26, count 0 2006.173.22:32:58.10#ibcon#about to write, iclass 26, count 0 2006.173.22:32:58.10#ibcon#wrote, iclass 26, count 0 2006.173.22:32:58.10#ibcon#about to read 3, iclass 26, count 0 2006.173.22:32:58.13#ibcon#read 3, iclass 26, count 0 2006.173.22:32:58.13#ibcon#about to read 4, iclass 26, count 0 2006.173.22:32:58.13#ibcon#read 4, iclass 26, count 0 2006.173.22:32:58.13#ibcon#about to read 5, iclass 26, count 0 2006.173.22:32:58.13#ibcon#read 5, iclass 26, count 0 2006.173.22:32:58.13#ibcon#about to read 6, iclass 26, count 0 2006.173.22:32:58.13#ibcon#read 6, iclass 26, count 0 2006.173.22:32:58.13#ibcon#end of sib2, iclass 26, count 0 2006.173.22:32:58.13#ibcon#*after write, iclass 26, count 0 2006.173.22:32:58.13#ibcon#*before return 0, iclass 26, count 0 2006.173.22:32:58.13#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.22:32:58.13#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.22:32:58.13#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.22:32:58.13#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.22:32:58.13$vck44/valo=4,624.99 2006.173.22:32:58.13#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.22:32:58.13#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.22:32:58.13#ibcon#ireg 17 cls_cnt 0 2006.173.22:32:58.13#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.22:32:58.13#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.22:32:58.13#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.22:32:58.13#ibcon#enter wrdev, iclass 28, count 0 2006.173.22:32:58.13#ibcon#first serial, iclass 28, count 0 2006.173.22:32:58.13#ibcon#enter sib2, iclass 28, count 0 2006.173.22:32:58.13#ibcon#flushed, iclass 28, count 0 2006.173.22:32:58.13#ibcon#about to write, iclass 28, count 0 2006.173.22:32:58.13#ibcon#wrote, iclass 28, count 0 2006.173.22:32:58.13#ibcon#about to read 3, iclass 28, count 0 2006.173.22:32:58.15#ibcon#read 3, iclass 28, count 0 2006.173.22:32:58.15#ibcon#about to read 4, iclass 28, count 0 2006.173.22:32:58.15#ibcon#read 4, iclass 28, count 0 2006.173.22:32:58.15#ibcon#about to read 5, iclass 28, count 0 2006.173.22:32:58.15#ibcon#read 5, iclass 28, count 0 2006.173.22:32:58.15#ibcon#about to read 6, iclass 28, count 0 2006.173.22:32:58.15#ibcon#read 6, iclass 28, count 0 2006.173.22:32:58.15#ibcon#end of sib2, iclass 28, count 0 2006.173.22:32:58.15#ibcon#*mode == 0, iclass 28, count 0 2006.173.22:32:58.15#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.22:32:58.15#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.22:32:58.15#ibcon#*before write, iclass 28, count 0 2006.173.22:32:58.15#ibcon#enter sib2, iclass 28, count 0 2006.173.22:32:58.15#ibcon#flushed, iclass 28, count 0 2006.173.22:32:58.15#ibcon#about to write, iclass 28, count 0 2006.173.22:32:58.15#ibcon#wrote, iclass 28, count 0 2006.173.22:32:58.15#ibcon#about to read 3, iclass 28, count 0 2006.173.22:32:58.19#ibcon#read 3, iclass 28, count 0 2006.173.22:32:58.19#ibcon#about to read 4, iclass 28, count 0 2006.173.22:32:58.19#ibcon#read 4, iclass 28, count 0 2006.173.22:32:58.19#ibcon#about to read 5, iclass 28, count 0 2006.173.22:32:58.19#ibcon#read 5, iclass 28, count 0 2006.173.22:32:58.19#ibcon#about to read 6, iclass 28, count 0 2006.173.22:32:58.19#ibcon#read 6, iclass 28, count 0 2006.173.22:32:58.19#ibcon#end of sib2, iclass 28, count 0 2006.173.22:32:58.19#ibcon#*after write, iclass 28, count 0 2006.173.22:32:58.19#ibcon#*before return 0, iclass 28, count 0 2006.173.22:32:58.19#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.22:32:58.19#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.22:32:58.19#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.22:32:58.19#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.22:32:58.19$vck44/va=4,6 2006.173.22:32:58.19#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.22:32:58.19#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.22:32:58.19#ibcon#ireg 11 cls_cnt 2 2006.173.22:32:58.19#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.22:32:58.25#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.22:32:58.25#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.22:32:58.25#ibcon#enter wrdev, iclass 30, count 2 2006.173.22:32:58.25#ibcon#first serial, iclass 30, count 2 2006.173.22:32:58.25#ibcon#enter sib2, iclass 30, count 2 2006.173.22:32:58.25#ibcon#flushed, iclass 30, count 2 2006.173.22:32:58.25#ibcon#about to write, iclass 30, count 2 2006.173.22:32:58.25#ibcon#wrote, iclass 30, count 2 2006.173.22:32:58.25#ibcon#about to read 3, iclass 30, count 2 2006.173.22:32:58.27#ibcon#read 3, iclass 30, count 2 2006.173.22:32:58.27#ibcon#about to read 4, iclass 30, count 2 2006.173.22:32:58.27#ibcon#read 4, iclass 30, count 2 2006.173.22:32:58.27#ibcon#about to read 5, iclass 30, count 2 2006.173.22:32:58.27#ibcon#read 5, iclass 30, count 2 2006.173.22:32:58.27#ibcon#about to read 6, iclass 30, count 2 2006.173.22:32:58.27#ibcon#read 6, iclass 30, count 2 2006.173.22:32:58.27#ibcon#end of sib2, iclass 30, count 2 2006.173.22:32:58.27#ibcon#*mode == 0, iclass 30, count 2 2006.173.22:32:58.27#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.22:32:58.27#ibcon#[25=AT04-06\r\n] 2006.173.22:32:58.27#ibcon#*before write, iclass 30, count 2 2006.173.22:32:58.27#ibcon#enter sib2, iclass 30, count 2 2006.173.22:32:58.27#ibcon#flushed, iclass 30, count 2 2006.173.22:32:58.27#ibcon#about to write, iclass 30, count 2 2006.173.22:32:58.27#ibcon#wrote, iclass 30, count 2 2006.173.22:32:58.27#ibcon#about to read 3, iclass 30, count 2 2006.173.22:32:58.30#ibcon#read 3, iclass 30, count 2 2006.173.22:32:58.30#ibcon#about to read 4, iclass 30, count 2 2006.173.22:32:58.30#ibcon#read 4, iclass 30, count 2 2006.173.22:32:58.30#ibcon#about to read 5, iclass 30, count 2 2006.173.22:32:58.30#ibcon#read 5, iclass 30, count 2 2006.173.22:32:58.30#ibcon#about to read 6, iclass 30, count 2 2006.173.22:32:58.30#ibcon#read 6, iclass 30, count 2 2006.173.22:32:58.30#ibcon#end of sib2, iclass 30, count 2 2006.173.22:32:58.30#ibcon#*after write, iclass 30, count 2 2006.173.22:32:58.30#ibcon#*before return 0, iclass 30, count 2 2006.173.22:32:58.30#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.22:32:58.30#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.22:32:58.30#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.22:32:58.30#ibcon#ireg 7 cls_cnt 0 2006.173.22:32:58.30#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.22:32:58.42#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.22:32:58.42#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.22:32:58.42#ibcon#enter wrdev, iclass 30, count 0 2006.173.22:32:58.42#ibcon#first serial, iclass 30, count 0 2006.173.22:32:58.42#ibcon#enter sib2, iclass 30, count 0 2006.173.22:32:58.42#ibcon#flushed, iclass 30, count 0 2006.173.22:32:58.42#ibcon#about to write, iclass 30, count 0 2006.173.22:32:58.42#ibcon#wrote, iclass 30, count 0 2006.173.22:32:58.42#ibcon#about to read 3, iclass 30, count 0 2006.173.22:32:58.44#ibcon#read 3, iclass 30, count 0 2006.173.22:32:58.44#ibcon#about to read 4, iclass 30, count 0 2006.173.22:32:58.44#ibcon#read 4, iclass 30, count 0 2006.173.22:32:58.44#ibcon#about to read 5, iclass 30, count 0 2006.173.22:32:58.44#ibcon#read 5, iclass 30, count 0 2006.173.22:32:58.44#ibcon#about to read 6, iclass 30, count 0 2006.173.22:32:58.44#ibcon#read 6, iclass 30, count 0 2006.173.22:32:58.44#ibcon#end of sib2, iclass 30, count 0 2006.173.22:32:58.44#ibcon#*mode == 0, iclass 30, count 0 2006.173.22:32:58.44#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.22:32:58.44#ibcon#[25=USB\r\n] 2006.173.22:32:58.44#ibcon#*before write, iclass 30, count 0 2006.173.22:32:58.44#ibcon#enter sib2, iclass 30, count 0 2006.173.22:32:58.44#ibcon#flushed, iclass 30, count 0 2006.173.22:32:58.44#ibcon#about to write, iclass 30, count 0 2006.173.22:32:58.44#ibcon#wrote, iclass 30, count 0 2006.173.22:32:58.44#ibcon#about to read 3, iclass 30, count 0 2006.173.22:32:58.47#ibcon#read 3, iclass 30, count 0 2006.173.22:32:58.47#ibcon#about to read 4, iclass 30, count 0 2006.173.22:32:58.47#ibcon#read 4, iclass 30, count 0 2006.173.22:32:58.47#ibcon#about to read 5, iclass 30, count 0 2006.173.22:32:58.47#ibcon#read 5, iclass 30, count 0 2006.173.22:32:58.47#ibcon#about to read 6, iclass 30, count 0 2006.173.22:32:58.47#ibcon#read 6, iclass 30, count 0 2006.173.22:32:58.47#ibcon#end of sib2, iclass 30, count 0 2006.173.22:32:58.47#ibcon#*after write, iclass 30, count 0 2006.173.22:32:58.47#ibcon#*before return 0, iclass 30, count 0 2006.173.22:32:58.47#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.22:32:58.47#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.22:32:58.47#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.22:32:58.47#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.22:32:58.47$vck44/valo=5,734.99 2006.173.22:32:58.47#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.22:32:58.47#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.22:32:58.47#ibcon#ireg 17 cls_cnt 0 2006.173.22:32:58.47#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.22:32:58.47#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.22:32:58.47#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.22:32:58.47#ibcon#enter wrdev, iclass 32, count 0 2006.173.22:32:58.47#ibcon#first serial, iclass 32, count 0 2006.173.22:32:58.47#ibcon#enter sib2, iclass 32, count 0 2006.173.22:32:58.47#ibcon#flushed, iclass 32, count 0 2006.173.22:32:58.47#ibcon#about to write, iclass 32, count 0 2006.173.22:32:58.47#ibcon#wrote, iclass 32, count 0 2006.173.22:32:58.47#ibcon#about to read 3, iclass 32, count 0 2006.173.22:32:58.49#ibcon#read 3, iclass 32, count 0 2006.173.22:32:58.49#ibcon#about to read 4, iclass 32, count 0 2006.173.22:32:58.49#ibcon#read 4, iclass 32, count 0 2006.173.22:32:58.49#ibcon#about to read 5, iclass 32, count 0 2006.173.22:32:58.49#ibcon#read 5, iclass 32, count 0 2006.173.22:32:58.49#ibcon#about to read 6, iclass 32, count 0 2006.173.22:32:58.49#ibcon#read 6, iclass 32, count 0 2006.173.22:32:58.49#ibcon#end of sib2, iclass 32, count 0 2006.173.22:32:58.49#ibcon#*mode == 0, iclass 32, count 0 2006.173.22:32:58.49#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.22:32:58.49#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.22:32:58.49#ibcon#*before write, iclass 32, count 0 2006.173.22:32:58.49#ibcon#enter sib2, iclass 32, count 0 2006.173.22:32:58.49#ibcon#flushed, iclass 32, count 0 2006.173.22:32:58.49#ibcon#about to write, iclass 32, count 0 2006.173.22:32:58.49#ibcon#wrote, iclass 32, count 0 2006.173.22:32:58.49#ibcon#about to read 3, iclass 32, count 0 2006.173.22:32:58.53#ibcon#read 3, iclass 32, count 0 2006.173.22:32:58.53#ibcon#about to read 4, iclass 32, count 0 2006.173.22:32:58.53#ibcon#read 4, iclass 32, count 0 2006.173.22:32:58.53#ibcon#about to read 5, iclass 32, count 0 2006.173.22:32:58.53#ibcon#read 5, iclass 32, count 0 2006.173.22:32:58.53#ibcon#about to read 6, iclass 32, count 0 2006.173.22:32:58.53#ibcon#read 6, iclass 32, count 0 2006.173.22:32:58.53#ibcon#end of sib2, iclass 32, count 0 2006.173.22:32:58.53#ibcon#*after write, iclass 32, count 0 2006.173.22:32:58.53#ibcon#*before return 0, iclass 32, count 0 2006.173.22:32:58.53#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.22:32:58.53#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.22:32:58.53#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.22:32:58.53#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.22:32:58.53$vck44/va=5,4 2006.173.22:32:58.53#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.22:32:58.53#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.22:32:58.53#ibcon#ireg 11 cls_cnt 2 2006.173.22:32:58.53#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.22:32:58.59#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.22:32:58.59#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.22:32:58.59#ibcon#enter wrdev, iclass 34, count 2 2006.173.22:32:58.59#ibcon#first serial, iclass 34, count 2 2006.173.22:32:58.59#ibcon#enter sib2, iclass 34, count 2 2006.173.22:32:58.59#ibcon#flushed, iclass 34, count 2 2006.173.22:32:58.59#ibcon#about to write, iclass 34, count 2 2006.173.22:32:58.59#ibcon#wrote, iclass 34, count 2 2006.173.22:32:58.59#ibcon#about to read 3, iclass 34, count 2 2006.173.22:32:58.61#ibcon#read 3, iclass 34, count 2 2006.173.22:32:58.61#ibcon#about to read 4, iclass 34, count 2 2006.173.22:32:58.61#ibcon#read 4, iclass 34, count 2 2006.173.22:32:58.61#ibcon#about to read 5, iclass 34, count 2 2006.173.22:32:58.61#ibcon#read 5, iclass 34, count 2 2006.173.22:32:58.61#ibcon#about to read 6, iclass 34, count 2 2006.173.22:32:58.61#ibcon#read 6, iclass 34, count 2 2006.173.22:32:58.61#ibcon#end of sib2, iclass 34, count 2 2006.173.22:32:58.61#ibcon#*mode == 0, iclass 34, count 2 2006.173.22:32:58.61#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.22:32:58.61#ibcon#[25=AT05-04\r\n] 2006.173.22:32:58.61#ibcon#*before write, iclass 34, count 2 2006.173.22:32:58.61#ibcon#enter sib2, iclass 34, count 2 2006.173.22:32:58.61#ibcon#flushed, iclass 34, count 2 2006.173.22:32:58.61#ibcon#about to write, iclass 34, count 2 2006.173.22:32:58.61#ibcon#wrote, iclass 34, count 2 2006.173.22:32:58.61#ibcon#about to read 3, iclass 34, count 2 2006.173.22:32:58.64#ibcon#read 3, iclass 34, count 2 2006.173.22:32:58.64#ibcon#about to read 4, iclass 34, count 2 2006.173.22:32:58.64#ibcon#read 4, iclass 34, count 2 2006.173.22:32:58.64#ibcon#about to read 5, iclass 34, count 2 2006.173.22:32:58.64#ibcon#read 5, iclass 34, count 2 2006.173.22:32:58.64#ibcon#about to read 6, iclass 34, count 2 2006.173.22:32:58.64#ibcon#read 6, iclass 34, count 2 2006.173.22:32:58.64#ibcon#end of sib2, iclass 34, count 2 2006.173.22:32:58.64#ibcon#*after write, iclass 34, count 2 2006.173.22:32:58.64#ibcon#*before return 0, iclass 34, count 2 2006.173.22:32:58.64#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.22:32:58.64#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.22:32:58.64#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.22:32:58.64#ibcon#ireg 7 cls_cnt 0 2006.173.22:32:58.64#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.22:32:58.76#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.22:32:58.76#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.22:32:58.76#ibcon#enter wrdev, iclass 34, count 0 2006.173.22:32:58.76#ibcon#first serial, iclass 34, count 0 2006.173.22:32:58.76#ibcon#enter sib2, iclass 34, count 0 2006.173.22:32:58.76#ibcon#flushed, iclass 34, count 0 2006.173.22:32:58.76#ibcon#about to write, iclass 34, count 0 2006.173.22:32:58.76#ibcon#wrote, iclass 34, count 0 2006.173.22:32:58.76#ibcon#about to read 3, iclass 34, count 0 2006.173.22:32:58.78#ibcon#read 3, iclass 34, count 0 2006.173.22:32:58.78#ibcon#about to read 4, iclass 34, count 0 2006.173.22:32:58.78#ibcon#read 4, iclass 34, count 0 2006.173.22:32:58.78#ibcon#about to read 5, iclass 34, count 0 2006.173.22:32:58.78#ibcon#read 5, iclass 34, count 0 2006.173.22:32:58.78#ibcon#about to read 6, iclass 34, count 0 2006.173.22:32:58.78#ibcon#read 6, iclass 34, count 0 2006.173.22:32:58.78#ibcon#end of sib2, iclass 34, count 0 2006.173.22:32:58.78#ibcon#*mode == 0, iclass 34, count 0 2006.173.22:32:58.78#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.22:32:58.78#ibcon#[25=USB\r\n] 2006.173.22:32:58.78#ibcon#*before write, iclass 34, count 0 2006.173.22:32:58.78#ibcon#enter sib2, iclass 34, count 0 2006.173.22:32:58.78#ibcon#flushed, iclass 34, count 0 2006.173.22:32:58.78#ibcon#about to write, iclass 34, count 0 2006.173.22:32:58.78#ibcon#wrote, iclass 34, count 0 2006.173.22:32:58.78#ibcon#about to read 3, iclass 34, count 0 2006.173.22:32:58.81#ibcon#read 3, iclass 34, count 0 2006.173.22:32:58.81#ibcon#about to read 4, iclass 34, count 0 2006.173.22:32:58.81#ibcon#read 4, iclass 34, count 0 2006.173.22:32:58.81#ibcon#about to read 5, iclass 34, count 0 2006.173.22:32:58.81#ibcon#read 5, iclass 34, count 0 2006.173.22:32:58.81#ibcon#about to read 6, iclass 34, count 0 2006.173.22:32:58.81#ibcon#read 6, iclass 34, count 0 2006.173.22:32:58.81#ibcon#end of sib2, iclass 34, count 0 2006.173.22:32:58.81#ibcon#*after write, iclass 34, count 0 2006.173.22:32:58.81#ibcon#*before return 0, iclass 34, count 0 2006.173.22:32:58.81#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.22:32:58.81#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.22:32:58.81#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.22:32:58.81#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.22:32:58.81$vck44/valo=6,814.99 2006.173.22:32:58.81#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.22:32:58.81#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.22:32:58.81#ibcon#ireg 17 cls_cnt 0 2006.173.22:32:58.81#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.22:32:58.81#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.22:32:58.81#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.22:32:58.81#ibcon#enter wrdev, iclass 36, count 0 2006.173.22:32:58.81#ibcon#first serial, iclass 36, count 0 2006.173.22:32:58.81#ibcon#enter sib2, iclass 36, count 0 2006.173.22:32:58.81#ibcon#flushed, iclass 36, count 0 2006.173.22:32:58.81#ibcon#about to write, iclass 36, count 0 2006.173.22:32:58.81#ibcon#wrote, iclass 36, count 0 2006.173.22:32:58.81#ibcon#about to read 3, iclass 36, count 0 2006.173.22:32:58.83#ibcon#read 3, iclass 36, count 0 2006.173.22:32:58.83#ibcon#about to read 4, iclass 36, count 0 2006.173.22:32:58.83#ibcon#read 4, iclass 36, count 0 2006.173.22:32:58.83#ibcon#about to read 5, iclass 36, count 0 2006.173.22:32:58.83#ibcon#read 5, iclass 36, count 0 2006.173.22:32:58.83#ibcon#about to read 6, iclass 36, count 0 2006.173.22:32:58.83#ibcon#read 6, iclass 36, count 0 2006.173.22:32:58.83#ibcon#end of sib2, iclass 36, count 0 2006.173.22:32:58.83#ibcon#*mode == 0, iclass 36, count 0 2006.173.22:32:58.83#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.22:32:58.83#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.22:32:58.83#ibcon#*before write, iclass 36, count 0 2006.173.22:32:58.83#ibcon#enter sib2, iclass 36, count 0 2006.173.22:32:58.83#ibcon#flushed, iclass 36, count 0 2006.173.22:32:58.83#ibcon#about to write, iclass 36, count 0 2006.173.22:32:58.83#ibcon#wrote, iclass 36, count 0 2006.173.22:32:58.83#ibcon#about to read 3, iclass 36, count 0 2006.173.22:32:58.87#ibcon#read 3, iclass 36, count 0 2006.173.22:32:58.87#ibcon#about to read 4, iclass 36, count 0 2006.173.22:32:58.87#ibcon#read 4, iclass 36, count 0 2006.173.22:32:58.87#ibcon#about to read 5, iclass 36, count 0 2006.173.22:32:58.87#ibcon#read 5, iclass 36, count 0 2006.173.22:32:58.87#ibcon#about to read 6, iclass 36, count 0 2006.173.22:32:58.87#ibcon#read 6, iclass 36, count 0 2006.173.22:32:58.87#ibcon#end of sib2, iclass 36, count 0 2006.173.22:32:58.87#ibcon#*after write, iclass 36, count 0 2006.173.22:32:58.87#ibcon#*before return 0, iclass 36, count 0 2006.173.22:32:58.87#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.22:32:58.87#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.22:32:58.87#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.22:32:58.87#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.22:32:58.87$vck44/va=6,3 2006.173.22:32:58.87#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.22:32:58.87#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.22:32:58.87#ibcon#ireg 11 cls_cnt 2 2006.173.22:32:58.87#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.22:32:58.93#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.22:32:58.93#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.22:32:58.93#ibcon#enter wrdev, iclass 38, count 2 2006.173.22:32:58.93#ibcon#first serial, iclass 38, count 2 2006.173.22:32:58.93#ibcon#enter sib2, iclass 38, count 2 2006.173.22:32:58.93#ibcon#flushed, iclass 38, count 2 2006.173.22:32:58.93#ibcon#about to write, iclass 38, count 2 2006.173.22:32:58.93#ibcon#wrote, iclass 38, count 2 2006.173.22:32:58.93#ibcon#about to read 3, iclass 38, count 2 2006.173.22:32:58.95#ibcon#read 3, iclass 38, count 2 2006.173.22:32:58.95#ibcon#about to read 4, iclass 38, count 2 2006.173.22:32:58.95#ibcon#read 4, iclass 38, count 2 2006.173.22:32:58.95#ibcon#about to read 5, iclass 38, count 2 2006.173.22:32:58.95#ibcon#read 5, iclass 38, count 2 2006.173.22:32:58.95#ibcon#about to read 6, iclass 38, count 2 2006.173.22:32:58.95#ibcon#read 6, iclass 38, count 2 2006.173.22:32:58.95#ibcon#end of sib2, iclass 38, count 2 2006.173.22:32:58.95#ibcon#*mode == 0, iclass 38, count 2 2006.173.22:32:58.95#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.22:32:58.95#ibcon#[25=AT06-03\r\n] 2006.173.22:32:58.95#ibcon#*before write, iclass 38, count 2 2006.173.22:32:58.95#ibcon#enter sib2, iclass 38, count 2 2006.173.22:32:58.95#ibcon#flushed, iclass 38, count 2 2006.173.22:32:58.95#ibcon#about to write, iclass 38, count 2 2006.173.22:32:58.95#ibcon#wrote, iclass 38, count 2 2006.173.22:32:58.95#ibcon#about to read 3, iclass 38, count 2 2006.173.22:32:58.98#ibcon#read 3, iclass 38, count 2 2006.173.22:32:58.98#ibcon#about to read 4, iclass 38, count 2 2006.173.22:32:58.98#ibcon#read 4, iclass 38, count 2 2006.173.22:32:58.98#ibcon#about to read 5, iclass 38, count 2 2006.173.22:32:58.98#ibcon#read 5, iclass 38, count 2 2006.173.22:32:58.98#ibcon#about to read 6, iclass 38, count 2 2006.173.22:32:58.98#ibcon#read 6, iclass 38, count 2 2006.173.22:32:58.98#ibcon#end of sib2, iclass 38, count 2 2006.173.22:32:58.98#ibcon#*after write, iclass 38, count 2 2006.173.22:32:58.98#ibcon#*before return 0, iclass 38, count 2 2006.173.22:32:58.98#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.22:32:58.98#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.22:32:58.98#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.22:32:58.98#ibcon#ireg 7 cls_cnt 0 2006.173.22:32:58.98#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.22:32:59.10#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.22:32:59.10#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.22:32:59.10#ibcon#enter wrdev, iclass 38, count 0 2006.173.22:32:59.10#ibcon#first serial, iclass 38, count 0 2006.173.22:32:59.10#ibcon#enter sib2, iclass 38, count 0 2006.173.22:32:59.10#ibcon#flushed, iclass 38, count 0 2006.173.22:32:59.10#ibcon#about to write, iclass 38, count 0 2006.173.22:32:59.10#ibcon#wrote, iclass 38, count 0 2006.173.22:32:59.10#ibcon#about to read 3, iclass 38, count 0 2006.173.22:32:59.12#ibcon#read 3, iclass 38, count 0 2006.173.22:32:59.12#ibcon#about to read 4, iclass 38, count 0 2006.173.22:32:59.12#ibcon#read 4, iclass 38, count 0 2006.173.22:32:59.12#ibcon#about to read 5, iclass 38, count 0 2006.173.22:32:59.12#ibcon#read 5, iclass 38, count 0 2006.173.22:32:59.12#ibcon#about to read 6, iclass 38, count 0 2006.173.22:32:59.12#ibcon#read 6, iclass 38, count 0 2006.173.22:32:59.12#ibcon#end of sib2, iclass 38, count 0 2006.173.22:32:59.12#ibcon#*mode == 0, iclass 38, count 0 2006.173.22:32:59.12#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.22:32:59.12#ibcon#[25=USB\r\n] 2006.173.22:32:59.12#ibcon#*before write, iclass 38, count 0 2006.173.22:32:59.12#ibcon#enter sib2, iclass 38, count 0 2006.173.22:32:59.12#ibcon#flushed, iclass 38, count 0 2006.173.22:32:59.12#ibcon#about to write, iclass 38, count 0 2006.173.22:32:59.12#ibcon#wrote, iclass 38, count 0 2006.173.22:32:59.12#ibcon#about to read 3, iclass 38, count 0 2006.173.22:32:59.15#ibcon#read 3, iclass 38, count 0 2006.173.22:32:59.15#ibcon#about to read 4, iclass 38, count 0 2006.173.22:32:59.15#ibcon#read 4, iclass 38, count 0 2006.173.22:32:59.15#ibcon#about to read 5, iclass 38, count 0 2006.173.22:32:59.15#ibcon#read 5, iclass 38, count 0 2006.173.22:32:59.15#ibcon#about to read 6, iclass 38, count 0 2006.173.22:32:59.15#ibcon#read 6, iclass 38, count 0 2006.173.22:32:59.15#ibcon#end of sib2, iclass 38, count 0 2006.173.22:32:59.15#ibcon#*after write, iclass 38, count 0 2006.173.22:32:59.15#ibcon#*before return 0, iclass 38, count 0 2006.173.22:32:59.15#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.22:32:59.15#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.22:32:59.15#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.22:32:59.15#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.22:32:59.15$vck44/valo=7,864.99 2006.173.22:32:59.15#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.22:32:59.15#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.22:32:59.15#ibcon#ireg 17 cls_cnt 0 2006.173.22:32:59.15#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.22:32:59.15#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.22:32:59.15#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.22:32:59.15#ibcon#enter wrdev, iclass 40, count 0 2006.173.22:32:59.15#ibcon#first serial, iclass 40, count 0 2006.173.22:32:59.15#ibcon#enter sib2, iclass 40, count 0 2006.173.22:32:59.15#ibcon#flushed, iclass 40, count 0 2006.173.22:32:59.15#ibcon#about to write, iclass 40, count 0 2006.173.22:32:59.15#ibcon#wrote, iclass 40, count 0 2006.173.22:32:59.15#ibcon#about to read 3, iclass 40, count 0 2006.173.22:32:59.17#ibcon#read 3, iclass 40, count 0 2006.173.22:32:59.17#ibcon#about to read 4, iclass 40, count 0 2006.173.22:32:59.17#ibcon#read 4, iclass 40, count 0 2006.173.22:32:59.17#ibcon#about to read 5, iclass 40, count 0 2006.173.22:32:59.17#ibcon#read 5, iclass 40, count 0 2006.173.22:32:59.17#ibcon#about to read 6, iclass 40, count 0 2006.173.22:32:59.17#ibcon#read 6, iclass 40, count 0 2006.173.22:32:59.17#ibcon#end of sib2, iclass 40, count 0 2006.173.22:32:59.17#ibcon#*mode == 0, iclass 40, count 0 2006.173.22:32:59.17#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.22:32:59.17#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.22:32:59.17#ibcon#*before write, iclass 40, count 0 2006.173.22:32:59.17#ibcon#enter sib2, iclass 40, count 0 2006.173.22:32:59.17#ibcon#flushed, iclass 40, count 0 2006.173.22:32:59.17#ibcon#about to write, iclass 40, count 0 2006.173.22:32:59.17#ibcon#wrote, iclass 40, count 0 2006.173.22:32:59.17#ibcon#about to read 3, iclass 40, count 0 2006.173.22:32:59.21#ibcon#read 3, iclass 40, count 0 2006.173.22:32:59.21#ibcon#about to read 4, iclass 40, count 0 2006.173.22:32:59.21#ibcon#read 4, iclass 40, count 0 2006.173.22:32:59.21#ibcon#about to read 5, iclass 40, count 0 2006.173.22:32:59.21#ibcon#read 5, iclass 40, count 0 2006.173.22:32:59.21#ibcon#about to read 6, iclass 40, count 0 2006.173.22:32:59.21#ibcon#read 6, iclass 40, count 0 2006.173.22:32:59.21#ibcon#end of sib2, iclass 40, count 0 2006.173.22:32:59.21#ibcon#*after write, iclass 40, count 0 2006.173.22:32:59.21#ibcon#*before return 0, iclass 40, count 0 2006.173.22:32:59.21#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.22:32:59.21#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.22:32:59.21#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.22:32:59.21#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.22:32:59.21$vck44/va=7,4 2006.173.22:32:59.21#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.22:32:59.21#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.22:32:59.21#ibcon#ireg 11 cls_cnt 2 2006.173.22:32:59.21#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.22:32:59.27#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.22:32:59.27#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.22:32:59.27#ibcon#enter wrdev, iclass 4, count 2 2006.173.22:32:59.27#ibcon#first serial, iclass 4, count 2 2006.173.22:32:59.27#ibcon#enter sib2, iclass 4, count 2 2006.173.22:32:59.27#ibcon#flushed, iclass 4, count 2 2006.173.22:32:59.27#ibcon#about to write, iclass 4, count 2 2006.173.22:32:59.27#ibcon#wrote, iclass 4, count 2 2006.173.22:32:59.27#ibcon#about to read 3, iclass 4, count 2 2006.173.22:32:59.29#ibcon#read 3, iclass 4, count 2 2006.173.22:32:59.29#ibcon#about to read 4, iclass 4, count 2 2006.173.22:32:59.29#ibcon#read 4, iclass 4, count 2 2006.173.22:32:59.29#ibcon#about to read 5, iclass 4, count 2 2006.173.22:32:59.29#ibcon#read 5, iclass 4, count 2 2006.173.22:32:59.29#ibcon#about to read 6, iclass 4, count 2 2006.173.22:32:59.29#ibcon#read 6, iclass 4, count 2 2006.173.22:32:59.29#ibcon#end of sib2, iclass 4, count 2 2006.173.22:32:59.29#ibcon#*mode == 0, iclass 4, count 2 2006.173.22:32:59.29#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.22:32:59.29#ibcon#[25=AT07-04\r\n] 2006.173.22:32:59.29#ibcon#*before write, iclass 4, count 2 2006.173.22:32:59.29#ibcon#enter sib2, iclass 4, count 2 2006.173.22:32:59.29#ibcon#flushed, iclass 4, count 2 2006.173.22:32:59.29#ibcon#about to write, iclass 4, count 2 2006.173.22:32:59.29#ibcon#wrote, iclass 4, count 2 2006.173.22:32:59.29#ibcon#about to read 3, iclass 4, count 2 2006.173.22:32:59.32#ibcon#read 3, iclass 4, count 2 2006.173.22:32:59.32#ibcon#about to read 4, iclass 4, count 2 2006.173.22:32:59.32#ibcon#read 4, iclass 4, count 2 2006.173.22:32:59.32#ibcon#about to read 5, iclass 4, count 2 2006.173.22:32:59.32#ibcon#read 5, iclass 4, count 2 2006.173.22:32:59.32#ibcon#about to read 6, iclass 4, count 2 2006.173.22:32:59.32#ibcon#read 6, iclass 4, count 2 2006.173.22:32:59.32#ibcon#end of sib2, iclass 4, count 2 2006.173.22:32:59.32#ibcon#*after write, iclass 4, count 2 2006.173.22:32:59.32#ibcon#*before return 0, iclass 4, count 2 2006.173.22:32:59.32#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.22:32:59.32#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.22:32:59.32#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.22:32:59.32#ibcon#ireg 7 cls_cnt 0 2006.173.22:32:59.32#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.22:32:59.44#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.22:32:59.44#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.22:32:59.44#ibcon#enter wrdev, iclass 4, count 0 2006.173.22:32:59.44#ibcon#first serial, iclass 4, count 0 2006.173.22:32:59.44#ibcon#enter sib2, iclass 4, count 0 2006.173.22:32:59.44#ibcon#flushed, iclass 4, count 0 2006.173.22:32:59.44#ibcon#about to write, iclass 4, count 0 2006.173.22:32:59.44#ibcon#wrote, iclass 4, count 0 2006.173.22:32:59.44#ibcon#about to read 3, iclass 4, count 0 2006.173.22:32:59.46#ibcon#read 3, iclass 4, count 0 2006.173.22:32:59.46#ibcon#about to read 4, iclass 4, count 0 2006.173.22:32:59.46#ibcon#read 4, iclass 4, count 0 2006.173.22:32:59.46#ibcon#about to read 5, iclass 4, count 0 2006.173.22:32:59.46#ibcon#read 5, iclass 4, count 0 2006.173.22:32:59.46#ibcon#about to read 6, iclass 4, count 0 2006.173.22:32:59.46#ibcon#read 6, iclass 4, count 0 2006.173.22:32:59.46#ibcon#end of sib2, iclass 4, count 0 2006.173.22:32:59.46#ibcon#*mode == 0, iclass 4, count 0 2006.173.22:32:59.46#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.22:32:59.46#ibcon#[25=USB\r\n] 2006.173.22:32:59.46#ibcon#*before write, iclass 4, count 0 2006.173.22:32:59.46#ibcon#enter sib2, iclass 4, count 0 2006.173.22:32:59.46#ibcon#flushed, iclass 4, count 0 2006.173.22:32:59.46#ibcon#about to write, iclass 4, count 0 2006.173.22:32:59.46#ibcon#wrote, iclass 4, count 0 2006.173.22:32:59.46#ibcon#about to read 3, iclass 4, count 0 2006.173.22:32:59.49#ibcon#read 3, iclass 4, count 0 2006.173.22:32:59.49#ibcon#about to read 4, iclass 4, count 0 2006.173.22:32:59.49#ibcon#read 4, iclass 4, count 0 2006.173.22:32:59.49#ibcon#about to read 5, iclass 4, count 0 2006.173.22:32:59.49#ibcon#read 5, iclass 4, count 0 2006.173.22:32:59.49#ibcon#about to read 6, iclass 4, count 0 2006.173.22:32:59.49#ibcon#read 6, iclass 4, count 0 2006.173.22:32:59.49#ibcon#end of sib2, iclass 4, count 0 2006.173.22:32:59.49#ibcon#*after write, iclass 4, count 0 2006.173.22:32:59.49#ibcon#*before return 0, iclass 4, count 0 2006.173.22:32:59.49#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.22:32:59.49#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.22:32:59.49#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.22:32:59.49#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.22:32:59.49$vck44/valo=8,884.99 2006.173.22:32:59.49#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.22:32:59.49#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.22:32:59.49#ibcon#ireg 17 cls_cnt 0 2006.173.22:32:59.49#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.22:32:59.49#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.22:32:59.49#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.22:32:59.49#ibcon#enter wrdev, iclass 6, count 0 2006.173.22:32:59.49#ibcon#first serial, iclass 6, count 0 2006.173.22:32:59.49#ibcon#enter sib2, iclass 6, count 0 2006.173.22:32:59.49#ibcon#flushed, iclass 6, count 0 2006.173.22:32:59.49#ibcon#about to write, iclass 6, count 0 2006.173.22:32:59.49#ibcon#wrote, iclass 6, count 0 2006.173.22:32:59.49#ibcon#about to read 3, iclass 6, count 0 2006.173.22:32:59.51#ibcon#read 3, iclass 6, count 0 2006.173.22:32:59.51#ibcon#about to read 4, iclass 6, count 0 2006.173.22:32:59.51#ibcon#read 4, iclass 6, count 0 2006.173.22:32:59.51#ibcon#about to read 5, iclass 6, count 0 2006.173.22:32:59.51#ibcon#read 5, iclass 6, count 0 2006.173.22:32:59.51#ibcon#about to read 6, iclass 6, count 0 2006.173.22:32:59.51#ibcon#read 6, iclass 6, count 0 2006.173.22:32:59.51#ibcon#end of sib2, iclass 6, count 0 2006.173.22:32:59.51#ibcon#*mode == 0, iclass 6, count 0 2006.173.22:32:59.51#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.22:32:59.51#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.22:32:59.51#ibcon#*before write, iclass 6, count 0 2006.173.22:32:59.51#ibcon#enter sib2, iclass 6, count 0 2006.173.22:32:59.51#ibcon#flushed, iclass 6, count 0 2006.173.22:32:59.51#ibcon#about to write, iclass 6, count 0 2006.173.22:32:59.51#ibcon#wrote, iclass 6, count 0 2006.173.22:32:59.51#ibcon#about to read 3, iclass 6, count 0 2006.173.22:32:59.55#ibcon#read 3, iclass 6, count 0 2006.173.22:32:59.55#ibcon#about to read 4, iclass 6, count 0 2006.173.22:32:59.55#ibcon#read 4, iclass 6, count 0 2006.173.22:32:59.55#ibcon#about to read 5, iclass 6, count 0 2006.173.22:32:59.55#ibcon#read 5, iclass 6, count 0 2006.173.22:32:59.55#ibcon#about to read 6, iclass 6, count 0 2006.173.22:32:59.55#ibcon#read 6, iclass 6, count 0 2006.173.22:32:59.55#ibcon#end of sib2, iclass 6, count 0 2006.173.22:32:59.55#ibcon#*after write, iclass 6, count 0 2006.173.22:32:59.55#ibcon#*before return 0, iclass 6, count 0 2006.173.22:32:59.55#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.22:32:59.55#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.22:32:59.55#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.22:32:59.55#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.22:32:59.55$vck44/va=8,4 2006.173.22:32:59.55#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.22:32:59.55#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.22:32:59.55#ibcon#ireg 11 cls_cnt 2 2006.173.22:32:59.55#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.22:32:59.61#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.22:32:59.61#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.22:32:59.61#ibcon#enter wrdev, iclass 10, count 2 2006.173.22:32:59.61#ibcon#first serial, iclass 10, count 2 2006.173.22:32:59.61#ibcon#enter sib2, iclass 10, count 2 2006.173.22:32:59.61#ibcon#flushed, iclass 10, count 2 2006.173.22:32:59.61#ibcon#about to write, iclass 10, count 2 2006.173.22:32:59.61#ibcon#wrote, iclass 10, count 2 2006.173.22:32:59.61#ibcon#about to read 3, iclass 10, count 2 2006.173.22:32:59.63#ibcon#read 3, iclass 10, count 2 2006.173.22:32:59.63#ibcon#about to read 4, iclass 10, count 2 2006.173.22:32:59.63#ibcon#read 4, iclass 10, count 2 2006.173.22:32:59.63#ibcon#about to read 5, iclass 10, count 2 2006.173.22:32:59.63#ibcon#read 5, iclass 10, count 2 2006.173.22:32:59.63#ibcon#about to read 6, iclass 10, count 2 2006.173.22:32:59.63#ibcon#read 6, iclass 10, count 2 2006.173.22:32:59.63#ibcon#end of sib2, iclass 10, count 2 2006.173.22:32:59.63#ibcon#*mode == 0, iclass 10, count 2 2006.173.22:32:59.63#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.22:32:59.63#ibcon#[25=AT08-04\r\n] 2006.173.22:32:59.63#ibcon#*before write, iclass 10, count 2 2006.173.22:32:59.63#ibcon#enter sib2, iclass 10, count 2 2006.173.22:32:59.63#ibcon#flushed, iclass 10, count 2 2006.173.22:32:59.63#ibcon#about to write, iclass 10, count 2 2006.173.22:32:59.63#ibcon#wrote, iclass 10, count 2 2006.173.22:32:59.63#ibcon#about to read 3, iclass 10, count 2 2006.173.22:32:59.66#ibcon#read 3, iclass 10, count 2 2006.173.22:32:59.66#ibcon#about to read 4, iclass 10, count 2 2006.173.22:32:59.66#ibcon#read 4, iclass 10, count 2 2006.173.22:32:59.66#ibcon#about to read 5, iclass 10, count 2 2006.173.22:32:59.66#ibcon#read 5, iclass 10, count 2 2006.173.22:32:59.66#ibcon#about to read 6, iclass 10, count 2 2006.173.22:32:59.66#ibcon#read 6, iclass 10, count 2 2006.173.22:32:59.66#ibcon#end of sib2, iclass 10, count 2 2006.173.22:32:59.66#ibcon#*after write, iclass 10, count 2 2006.173.22:32:59.66#ibcon#*before return 0, iclass 10, count 2 2006.173.22:32:59.66#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.22:32:59.66#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.22:32:59.66#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.22:32:59.66#ibcon#ireg 7 cls_cnt 0 2006.173.22:32:59.66#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.22:32:59.78#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.22:32:59.78#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.22:32:59.78#ibcon#enter wrdev, iclass 10, count 0 2006.173.22:32:59.78#ibcon#first serial, iclass 10, count 0 2006.173.22:32:59.78#ibcon#enter sib2, iclass 10, count 0 2006.173.22:32:59.78#ibcon#flushed, iclass 10, count 0 2006.173.22:32:59.78#ibcon#about to write, iclass 10, count 0 2006.173.22:32:59.78#ibcon#wrote, iclass 10, count 0 2006.173.22:32:59.78#ibcon#about to read 3, iclass 10, count 0 2006.173.22:32:59.80#ibcon#read 3, iclass 10, count 0 2006.173.22:32:59.80#ibcon#about to read 4, iclass 10, count 0 2006.173.22:32:59.80#ibcon#read 4, iclass 10, count 0 2006.173.22:32:59.80#ibcon#about to read 5, iclass 10, count 0 2006.173.22:32:59.80#ibcon#read 5, iclass 10, count 0 2006.173.22:32:59.80#ibcon#about to read 6, iclass 10, count 0 2006.173.22:32:59.80#ibcon#read 6, iclass 10, count 0 2006.173.22:32:59.80#ibcon#end of sib2, iclass 10, count 0 2006.173.22:32:59.80#ibcon#*mode == 0, iclass 10, count 0 2006.173.22:32:59.80#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.22:32:59.80#ibcon#[25=USB\r\n] 2006.173.22:32:59.80#ibcon#*before write, iclass 10, count 0 2006.173.22:32:59.80#ibcon#enter sib2, iclass 10, count 0 2006.173.22:32:59.80#ibcon#flushed, iclass 10, count 0 2006.173.22:32:59.80#ibcon#about to write, iclass 10, count 0 2006.173.22:32:59.80#ibcon#wrote, iclass 10, count 0 2006.173.22:32:59.80#ibcon#about to read 3, iclass 10, count 0 2006.173.22:32:59.83#ibcon#read 3, iclass 10, count 0 2006.173.22:32:59.83#ibcon#about to read 4, iclass 10, count 0 2006.173.22:32:59.83#ibcon#read 4, iclass 10, count 0 2006.173.22:32:59.83#ibcon#about to read 5, iclass 10, count 0 2006.173.22:32:59.83#ibcon#read 5, iclass 10, count 0 2006.173.22:32:59.83#ibcon#about to read 6, iclass 10, count 0 2006.173.22:32:59.83#ibcon#read 6, iclass 10, count 0 2006.173.22:32:59.83#ibcon#end of sib2, iclass 10, count 0 2006.173.22:32:59.83#ibcon#*after write, iclass 10, count 0 2006.173.22:32:59.83#ibcon#*before return 0, iclass 10, count 0 2006.173.22:32:59.83#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.22:32:59.83#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.22:32:59.83#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.22:32:59.83#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.22:32:59.83$vck44/vblo=1,629.99 2006.173.22:32:59.83#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.22:32:59.83#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.22:32:59.83#ibcon#ireg 17 cls_cnt 0 2006.173.22:32:59.83#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.22:32:59.83#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.22:32:59.83#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.22:32:59.83#ibcon#enter wrdev, iclass 12, count 0 2006.173.22:32:59.83#ibcon#first serial, iclass 12, count 0 2006.173.22:32:59.83#ibcon#enter sib2, iclass 12, count 0 2006.173.22:32:59.83#ibcon#flushed, iclass 12, count 0 2006.173.22:32:59.83#ibcon#about to write, iclass 12, count 0 2006.173.22:32:59.83#ibcon#wrote, iclass 12, count 0 2006.173.22:32:59.83#ibcon#about to read 3, iclass 12, count 0 2006.173.22:32:59.85#ibcon#read 3, iclass 12, count 0 2006.173.22:32:59.85#ibcon#about to read 4, iclass 12, count 0 2006.173.22:32:59.85#ibcon#read 4, iclass 12, count 0 2006.173.22:32:59.85#ibcon#about to read 5, iclass 12, count 0 2006.173.22:32:59.85#ibcon#read 5, iclass 12, count 0 2006.173.22:32:59.85#ibcon#about to read 6, iclass 12, count 0 2006.173.22:32:59.85#ibcon#read 6, iclass 12, count 0 2006.173.22:32:59.85#ibcon#end of sib2, iclass 12, count 0 2006.173.22:32:59.85#ibcon#*mode == 0, iclass 12, count 0 2006.173.22:32:59.85#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.22:32:59.85#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.22:32:59.85#ibcon#*before write, iclass 12, count 0 2006.173.22:32:59.85#ibcon#enter sib2, iclass 12, count 0 2006.173.22:32:59.85#ibcon#flushed, iclass 12, count 0 2006.173.22:32:59.85#ibcon#about to write, iclass 12, count 0 2006.173.22:32:59.85#ibcon#wrote, iclass 12, count 0 2006.173.22:32:59.85#ibcon#about to read 3, iclass 12, count 0 2006.173.22:32:59.89#ibcon#read 3, iclass 12, count 0 2006.173.22:32:59.89#ibcon#about to read 4, iclass 12, count 0 2006.173.22:32:59.89#ibcon#read 4, iclass 12, count 0 2006.173.22:32:59.89#ibcon#about to read 5, iclass 12, count 0 2006.173.22:32:59.89#ibcon#read 5, iclass 12, count 0 2006.173.22:32:59.89#ibcon#about to read 6, iclass 12, count 0 2006.173.22:32:59.89#ibcon#read 6, iclass 12, count 0 2006.173.22:32:59.89#ibcon#end of sib2, iclass 12, count 0 2006.173.22:32:59.89#ibcon#*after write, iclass 12, count 0 2006.173.22:32:59.89#ibcon#*before return 0, iclass 12, count 0 2006.173.22:32:59.89#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.22:32:59.89#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.22:32:59.89#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.22:32:59.89#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.22:32:59.89$vck44/vb=1,4 2006.173.22:32:59.89#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.22:32:59.89#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.22:32:59.89#ibcon#ireg 11 cls_cnt 2 2006.173.22:32:59.89#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.22:32:59.89#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.22:32:59.89#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.22:32:59.89#ibcon#enter wrdev, iclass 14, count 2 2006.173.22:32:59.89#ibcon#first serial, iclass 14, count 2 2006.173.22:32:59.89#ibcon#enter sib2, iclass 14, count 2 2006.173.22:32:59.89#ibcon#flushed, iclass 14, count 2 2006.173.22:32:59.89#ibcon#about to write, iclass 14, count 2 2006.173.22:32:59.89#ibcon#wrote, iclass 14, count 2 2006.173.22:32:59.89#ibcon#about to read 3, iclass 14, count 2 2006.173.22:32:59.91#ibcon#read 3, iclass 14, count 2 2006.173.22:32:59.91#ibcon#about to read 4, iclass 14, count 2 2006.173.22:32:59.91#ibcon#read 4, iclass 14, count 2 2006.173.22:32:59.91#ibcon#about to read 5, iclass 14, count 2 2006.173.22:32:59.91#ibcon#read 5, iclass 14, count 2 2006.173.22:32:59.91#ibcon#about to read 6, iclass 14, count 2 2006.173.22:32:59.91#ibcon#read 6, iclass 14, count 2 2006.173.22:32:59.91#ibcon#end of sib2, iclass 14, count 2 2006.173.22:32:59.91#ibcon#*mode == 0, iclass 14, count 2 2006.173.22:32:59.91#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.22:32:59.91#ibcon#[27=AT01-04\r\n] 2006.173.22:32:59.91#ibcon#*before write, iclass 14, count 2 2006.173.22:32:59.91#ibcon#enter sib2, iclass 14, count 2 2006.173.22:32:59.91#ibcon#flushed, iclass 14, count 2 2006.173.22:32:59.91#ibcon#about to write, iclass 14, count 2 2006.173.22:32:59.91#ibcon#wrote, iclass 14, count 2 2006.173.22:32:59.91#ibcon#about to read 3, iclass 14, count 2 2006.173.22:32:59.94#ibcon#read 3, iclass 14, count 2 2006.173.22:32:59.94#ibcon#about to read 4, iclass 14, count 2 2006.173.22:32:59.94#ibcon#read 4, iclass 14, count 2 2006.173.22:32:59.94#ibcon#about to read 5, iclass 14, count 2 2006.173.22:32:59.94#ibcon#read 5, iclass 14, count 2 2006.173.22:32:59.94#ibcon#about to read 6, iclass 14, count 2 2006.173.22:32:59.94#ibcon#read 6, iclass 14, count 2 2006.173.22:32:59.94#ibcon#end of sib2, iclass 14, count 2 2006.173.22:32:59.94#ibcon#*after write, iclass 14, count 2 2006.173.22:32:59.94#ibcon#*before return 0, iclass 14, count 2 2006.173.22:32:59.94#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.22:32:59.94#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.22:32:59.94#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.22:32:59.94#ibcon#ireg 7 cls_cnt 0 2006.173.22:32:59.94#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.22:33:00.06#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.22:33:00.06#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.22:33:00.06#ibcon#enter wrdev, iclass 14, count 0 2006.173.22:33:00.06#ibcon#first serial, iclass 14, count 0 2006.173.22:33:00.06#ibcon#enter sib2, iclass 14, count 0 2006.173.22:33:00.06#ibcon#flushed, iclass 14, count 0 2006.173.22:33:00.06#ibcon#about to write, iclass 14, count 0 2006.173.22:33:00.06#ibcon#wrote, iclass 14, count 0 2006.173.22:33:00.06#ibcon#about to read 3, iclass 14, count 0 2006.173.22:33:00.08#ibcon#read 3, iclass 14, count 0 2006.173.22:33:00.08#ibcon#about to read 4, iclass 14, count 0 2006.173.22:33:00.08#ibcon#read 4, iclass 14, count 0 2006.173.22:33:00.08#ibcon#about to read 5, iclass 14, count 0 2006.173.22:33:00.08#ibcon#read 5, iclass 14, count 0 2006.173.22:33:00.08#ibcon#about to read 6, iclass 14, count 0 2006.173.22:33:00.08#ibcon#read 6, iclass 14, count 0 2006.173.22:33:00.08#ibcon#end of sib2, iclass 14, count 0 2006.173.22:33:00.08#ibcon#*mode == 0, iclass 14, count 0 2006.173.22:33:00.08#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.22:33:00.08#ibcon#[27=USB\r\n] 2006.173.22:33:00.08#ibcon#*before write, iclass 14, count 0 2006.173.22:33:00.08#ibcon#enter sib2, iclass 14, count 0 2006.173.22:33:00.08#ibcon#flushed, iclass 14, count 0 2006.173.22:33:00.08#ibcon#about to write, iclass 14, count 0 2006.173.22:33:00.08#ibcon#wrote, iclass 14, count 0 2006.173.22:33:00.08#ibcon#about to read 3, iclass 14, count 0 2006.173.22:33:00.11#ibcon#read 3, iclass 14, count 0 2006.173.22:33:00.11#ibcon#about to read 4, iclass 14, count 0 2006.173.22:33:00.11#ibcon#read 4, iclass 14, count 0 2006.173.22:33:00.11#ibcon#about to read 5, iclass 14, count 0 2006.173.22:33:00.11#ibcon#read 5, iclass 14, count 0 2006.173.22:33:00.11#ibcon#about to read 6, iclass 14, count 0 2006.173.22:33:00.11#ibcon#read 6, iclass 14, count 0 2006.173.22:33:00.11#ibcon#end of sib2, iclass 14, count 0 2006.173.22:33:00.11#ibcon#*after write, iclass 14, count 0 2006.173.22:33:00.11#ibcon#*before return 0, iclass 14, count 0 2006.173.22:33:00.11#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.22:33:00.11#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.22:33:00.11#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.22:33:00.11#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.22:33:00.11$vck44/vblo=2,634.99 2006.173.22:33:00.11#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.22:33:00.11#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.22:33:00.11#ibcon#ireg 17 cls_cnt 0 2006.173.22:33:00.11#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.22:33:00.11#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.22:33:00.11#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.22:33:00.11#ibcon#enter wrdev, iclass 16, count 0 2006.173.22:33:00.11#ibcon#first serial, iclass 16, count 0 2006.173.22:33:00.11#ibcon#enter sib2, iclass 16, count 0 2006.173.22:33:00.11#ibcon#flushed, iclass 16, count 0 2006.173.22:33:00.11#ibcon#about to write, iclass 16, count 0 2006.173.22:33:00.11#ibcon#wrote, iclass 16, count 0 2006.173.22:33:00.11#ibcon#about to read 3, iclass 16, count 0 2006.173.22:33:00.13#ibcon#read 3, iclass 16, count 0 2006.173.22:33:00.13#ibcon#about to read 4, iclass 16, count 0 2006.173.22:33:00.13#ibcon#read 4, iclass 16, count 0 2006.173.22:33:00.13#ibcon#about to read 5, iclass 16, count 0 2006.173.22:33:00.13#ibcon#read 5, iclass 16, count 0 2006.173.22:33:00.13#ibcon#about to read 6, iclass 16, count 0 2006.173.22:33:00.13#ibcon#read 6, iclass 16, count 0 2006.173.22:33:00.13#ibcon#end of sib2, iclass 16, count 0 2006.173.22:33:00.13#ibcon#*mode == 0, iclass 16, count 0 2006.173.22:33:00.13#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.22:33:00.13#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.22:33:00.13#ibcon#*before write, iclass 16, count 0 2006.173.22:33:00.13#ibcon#enter sib2, iclass 16, count 0 2006.173.22:33:00.13#ibcon#flushed, iclass 16, count 0 2006.173.22:33:00.13#ibcon#about to write, iclass 16, count 0 2006.173.22:33:00.13#ibcon#wrote, iclass 16, count 0 2006.173.22:33:00.13#ibcon#about to read 3, iclass 16, count 0 2006.173.22:33:00.17#ibcon#read 3, iclass 16, count 0 2006.173.22:33:00.17#ibcon#about to read 4, iclass 16, count 0 2006.173.22:33:00.17#ibcon#read 4, iclass 16, count 0 2006.173.22:33:00.17#ibcon#about to read 5, iclass 16, count 0 2006.173.22:33:00.17#ibcon#read 5, iclass 16, count 0 2006.173.22:33:00.17#ibcon#about to read 6, iclass 16, count 0 2006.173.22:33:00.17#ibcon#read 6, iclass 16, count 0 2006.173.22:33:00.17#ibcon#end of sib2, iclass 16, count 0 2006.173.22:33:00.17#ibcon#*after write, iclass 16, count 0 2006.173.22:33:00.17#ibcon#*before return 0, iclass 16, count 0 2006.173.22:33:00.17#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.22:33:00.17#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.22:33:00.17#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.22:33:00.17#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.22:33:00.17$vck44/vb=2,4 2006.173.22:33:00.17#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.22:33:00.17#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.22:33:00.17#ibcon#ireg 11 cls_cnt 2 2006.173.22:33:00.17#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.22:33:00.23#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.22:33:00.23#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.22:33:00.23#ibcon#enter wrdev, iclass 18, count 2 2006.173.22:33:00.23#ibcon#first serial, iclass 18, count 2 2006.173.22:33:00.23#ibcon#enter sib2, iclass 18, count 2 2006.173.22:33:00.23#ibcon#flushed, iclass 18, count 2 2006.173.22:33:00.23#ibcon#about to write, iclass 18, count 2 2006.173.22:33:00.23#ibcon#wrote, iclass 18, count 2 2006.173.22:33:00.23#ibcon#about to read 3, iclass 18, count 2 2006.173.22:33:00.25#ibcon#read 3, iclass 18, count 2 2006.173.22:33:00.25#ibcon#about to read 4, iclass 18, count 2 2006.173.22:33:00.25#ibcon#read 4, iclass 18, count 2 2006.173.22:33:00.25#ibcon#about to read 5, iclass 18, count 2 2006.173.22:33:00.25#ibcon#read 5, iclass 18, count 2 2006.173.22:33:00.25#ibcon#about to read 6, iclass 18, count 2 2006.173.22:33:00.25#ibcon#read 6, iclass 18, count 2 2006.173.22:33:00.25#ibcon#end of sib2, iclass 18, count 2 2006.173.22:33:00.25#ibcon#*mode == 0, iclass 18, count 2 2006.173.22:33:00.25#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.22:33:00.25#ibcon#[27=AT02-04\r\n] 2006.173.22:33:00.25#ibcon#*before write, iclass 18, count 2 2006.173.22:33:00.25#ibcon#enter sib2, iclass 18, count 2 2006.173.22:33:00.25#ibcon#flushed, iclass 18, count 2 2006.173.22:33:00.25#ibcon#about to write, iclass 18, count 2 2006.173.22:33:00.25#ibcon#wrote, iclass 18, count 2 2006.173.22:33:00.25#ibcon#about to read 3, iclass 18, count 2 2006.173.22:33:00.28#ibcon#read 3, iclass 18, count 2 2006.173.22:33:00.28#ibcon#about to read 4, iclass 18, count 2 2006.173.22:33:00.28#ibcon#read 4, iclass 18, count 2 2006.173.22:33:00.28#ibcon#about to read 5, iclass 18, count 2 2006.173.22:33:00.28#ibcon#read 5, iclass 18, count 2 2006.173.22:33:00.28#ibcon#about to read 6, iclass 18, count 2 2006.173.22:33:00.28#ibcon#read 6, iclass 18, count 2 2006.173.22:33:00.28#ibcon#end of sib2, iclass 18, count 2 2006.173.22:33:00.28#ibcon#*after write, iclass 18, count 2 2006.173.22:33:00.28#ibcon#*before return 0, iclass 18, count 2 2006.173.22:33:00.28#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.22:33:00.28#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.22:33:00.28#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.22:33:00.28#ibcon#ireg 7 cls_cnt 0 2006.173.22:33:00.28#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.22:33:00.40#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.22:33:00.40#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.22:33:00.40#ibcon#enter wrdev, iclass 18, count 0 2006.173.22:33:00.40#ibcon#first serial, iclass 18, count 0 2006.173.22:33:00.40#ibcon#enter sib2, iclass 18, count 0 2006.173.22:33:00.40#ibcon#flushed, iclass 18, count 0 2006.173.22:33:00.40#ibcon#about to write, iclass 18, count 0 2006.173.22:33:00.40#ibcon#wrote, iclass 18, count 0 2006.173.22:33:00.40#ibcon#about to read 3, iclass 18, count 0 2006.173.22:33:00.42#ibcon#read 3, iclass 18, count 0 2006.173.22:33:00.42#ibcon#about to read 4, iclass 18, count 0 2006.173.22:33:00.42#ibcon#read 4, iclass 18, count 0 2006.173.22:33:00.42#ibcon#about to read 5, iclass 18, count 0 2006.173.22:33:00.42#ibcon#read 5, iclass 18, count 0 2006.173.22:33:00.42#ibcon#about to read 6, iclass 18, count 0 2006.173.22:33:00.42#ibcon#read 6, iclass 18, count 0 2006.173.22:33:00.42#ibcon#end of sib2, iclass 18, count 0 2006.173.22:33:00.42#ibcon#*mode == 0, iclass 18, count 0 2006.173.22:33:00.42#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.22:33:00.42#ibcon#[27=USB\r\n] 2006.173.22:33:00.42#ibcon#*before write, iclass 18, count 0 2006.173.22:33:00.42#ibcon#enter sib2, iclass 18, count 0 2006.173.22:33:00.42#ibcon#flushed, iclass 18, count 0 2006.173.22:33:00.42#ibcon#about to write, iclass 18, count 0 2006.173.22:33:00.42#ibcon#wrote, iclass 18, count 0 2006.173.22:33:00.42#ibcon#about to read 3, iclass 18, count 0 2006.173.22:33:00.45#ibcon#read 3, iclass 18, count 0 2006.173.22:33:00.45#ibcon#about to read 4, iclass 18, count 0 2006.173.22:33:00.45#ibcon#read 4, iclass 18, count 0 2006.173.22:33:00.45#ibcon#about to read 5, iclass 18, count 0 2006.173.22:33:00.45#ibcon#read 5, iclass 18, count 0 2006.173.22:33:00.45#ibcon#about to read 6, iclass 18, count 0 2006.173.22:33:00.45#ibcon#read 6, iclass 18, count 0 2006.173.22:33:00.45#ibcon#end of sib2, iclass 18, count 0 2006.173.22:33:00.45#ibcon#*after write, iclass 18, count 0 2006.173.22:33:00.45#ibcon#*before return 0, iclass 18, count 0 2006.173.22:33:00.45#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.22:33:00.45#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.22:33:00.45#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.22:33:00.45#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.22:33:00.45$vck44/vblo=3,649.99 2006.173.22:33:00.45#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.22:33:00.45#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.22:33:00.45#ibcon#ireg 17 cls_cnt 0 2006.173.22:33:00.45#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.22:33:00.45#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.22:33:00.45#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.22:33:00.45#ibcon#enter wrdev, iclass 20, count 0 2006.173.22:33:00.45#ibcon#first serial, iclass 20, count 0 2006.173.22:33:00.45#ibcon#enter sib2, iclass 20, count 0 2006.173.22:33:00.45#ibcon#flushed, iclass 20, count 0 2006.173.22:33:00.45#ibcon#about to write, iclass 20, count 0 2006.173.22:33:00.45#ibcon#wrote, iclass 20, count 0 2006.173.22:33:00.45#ibcon#about to read 3, iclass 20, count 0 2006.173.22:33:00.47#ibcon#read 3, iclass 20, count 0 2006.173.22:33:00.47#ibcon#about to read 4, iclass 20, count 0 2006.173.22:33:00.47#ibcon#read 4, iclass 20, count 0 2006.173.22:33:00.47#ibcon#about to read 5, iclass 20, count 0 2006.173.22:33:00.47#ibcon#read 5, iclass 20, count 0 2006.173.22:33:00.47#ibcon#about to read 6, iclass 20, count 0 2006.173.22:33:00.47#ibcon#read 6, iclass 20, count 0 2006.173.22:33:00.47#ibcon#end of sib2, iclass 20, count 0 2006.173.22:33:00.47#ibcon#*mode == 0, iclass 20, count 0 2006.173.22:33:00.47#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.22:33:00.47#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.22:33:00.47#ibcon#*before write, iclass 20, count 0 2006.173.22:33:00.47#ibcon#enter sib2, iclass 20, count 0 2006.173.22:33:00.47#ibcon#flushed, iclass 20, count 0 2006.173.22:33:00.47#ibcon#about to write, iclass 20, count 0 2006.173.22:33:00.47#ibcon#wrote, iclass 20, count 0 2006.173.22:33:00.47#ibcon#about to read 3, iclass 20, count 0 2006.173.22:33:00.51#ibcon#read 3, iclass 20, count 0 2006.173.22:33:00.51#ibcon#about to read 4, iclass 20, count 0 2006.173.22:33:00.51#ibcon#read 4, iclass 20, count 0 2006.173.22:33:00.51#ibcon#about to read 5, iclass 20, count 0 2006.173.22:33:00.51#ibcon#read 5, iclass 20, count 0 2006.173.22:33:00.51#ibcon#about to read 6, iclass 20, count 0 2006.173.22:33:00.51#ibcon#read 6, iclass 20, count 0 2006.173.22:33:00.51#ibcon#end of sib2, iclass 20, count 0 2006.173.22:33:00.51#ibcon#*after write, iclass 20, count 0 2006.173.22:33:00.51#ibcon#*before return 0, iclass 20, count 0 2006.173.22:33:00.51#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.22:33:00.51#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.22:33:00.51#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.22:33:00.51#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.22:33:00.51$vck44/vb=3,4 2006.173.22:33:00.51#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.22:33:00.51#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.22:33:00.51#ibcon#ireg 11 cls_cnt 2 2006.173.22:33:00.51#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.22:33:00.57#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.22:33:00.57#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.22:33:00.57#ibcon#enter wrdev, iclass 22, count 2 2006.173.22:33:00.57#ibcon#first serial, iclass 22, count 2 2006.173.22:33:00.57#ibcon#enter sib2, iclass 22, count 2 2006.173.22:33:00.57#ibcon#flushed, iclass 22, count 2 2006.173.22:33:00.57#ibcon#about to write, iclass 22, count 2 2006.173.22:33:00.57#ibcon#wrote, iclass 22, count 2 2006.173.22:33:00.57#ibcon#about to read 3, iclass 22, count 2 2006.173.22:33:00.59#ibcon#read 3, iclass 22, count 2 2006.173.22:33:00.59#ibcon#about to read 4, iclass 22, count 2 2006.173.22:33:00.59#ibcon#read 4, iclass 22, count 2 2006.173.22:33:00.59#ibcon#about to read 5, iclass 22, count 2 2006.173.22:33:00.59#ibcon#read 5, iclass 22, count 2 2006.173.22:33:00.59#ibcon#about to read 6, iclass 22, count 2 2006.173.22:33:00.59#ibcon#read 6, iclass 22, count 2 2006.173.22:33:00.59#ibcon#end of sib2, iclass 22, count 2 2006.173.22:33:00.59#ibcon#*mode == 0, iclass 22, count 2 2006.173.22:33:00.59#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.22:33:00.59#ibcon#[27=AT03-04\r\n] 2006.173.22:33:00.59#ibcon#*before write, iclass 22, count 2 2006.173.22:33:00.59#ibcon#enter sib2, iclass 22, count 2 2006.173.22:33:00.59#ibcon#flushed, iclass 22, count 2 2006.173.22:33:00.59#ibcon#about to write, iclass 22, count 2 2006.173.22:33:00.59#ibcon#wrote, iclass 22, count 2 2006.173.22:33:00.59#ibcon#about to read 3, iclass 22, count 2 2006.173.22:33:00.62#ibcon#read 3, iclass 22, count 2 2006.173.22:33:00.62#ibcon#about to read 4, iclass 22, count 2 2006.173.22:33:00.62#ibcon#read 4, iclass 22, count 2 2006.173.22:33:00.62#ibcon#about to read 5, iclass 22, count 2 2006.173.22:33:00.62#ibcon#read 5, iclass 22, count 2 2006.173.22:33:00.62#ibcon#about to read 6, iclass 22, count 2 2006.173.22:33:00.62#ibcon#read 6, iclass 22, count 2 2006.173.22:33:00.62#ibcon#end of sib2, iclass 22, count 2 2006.173.22:33:00.62#ibcon#*after write, iclass 22, count 2 2006.173.22:33:00.62#ibcon#*before return 0, iclass 22, count 2 2006.173.22:33:00.62#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.22:33:00.62#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.22:33:00.62#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.22:33:00.62#ibcon#ireg 7 cls_cnt 0 2006.173.22:33:00.62#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.22:33:00.74#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.22:33:00.74#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.22:33:00.74#ibcon#enter wrdev, iclass 22, count 0 2006.173.22:33:00.74#ibcon#first serial, iclass 22, count 0 2006.173.22:33:00.74#ibcon#enter sib2, iclass 22, count 0 2006.173.22:33:00.74#ibcon#flushed, iclass 22, count 0 2006.173.22:33:00.74#ibcon#about to write, iclass 22, count 0 2006.173.22:33:00.74#ibcon#wrote, iclass 22, count 0 2006.173.22:33:00.74#ibcon#about to read 3, iclass 22, count 0 2006.173.22:33:00.76#ibcon#read 3, iclass 22, count 0 2006.173.22:33:00.76#ibcon#about to read 4, iclass 22, count 0 2006.173.22:33:00.76#ibcon#read 4, iclass 22, count 0 2006.173.22:33:00.76#ibcon#about to read 5, iclass 22, count 0 2006.173.22:33:00.76#ibcon#read 5, iclass 22, count 0 2006.173.22:33:00.76#ibcon#about to read 6, iclass 22, count 0 2006.173.22:33:00.76#ibcon#read 6, iclass 22, count 0 2006.173.22:33:00.76#ibcon#end of sib2, iclass 22, count 0 2006.173.22:33:00.76#ibcon#*mode == 0, iclass 22, count 0 2006.173.22:33:00.76#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.22:33:00.76#ibcon#[27=USB\r\n] 2006.173.22:33:00.76#ibcon#*before write, iclass 22, count 0 2006.173.22:33:00.76#ibcon#enter sib2, iclass 22, count 0 2006.173.22:33:00.76#ibcon#flushed, iclass 22, count 0 2006.173.22:33:00.76#ibcon#about to write, iclass 22, count 0 2006.173.22:33:00.76#ibcon#wrote, iclass 22, count 0 2006.173.22:33:00.76#ibcon#about to read 3, iclass 22, count 0 2006.173.22:33:00.79#ibcon#read 3, iclass 22, count 0 2006.173.22:33:00.79#ibcon#about to read 4, iclass 22, count 0 2006.173.22:33:00.79#ibcon#read 4, iclass 22, count 0 2006.173.22:33:00.79#ibcon#about to read 5, iclass 22, count 0 2006.173.22:33:00.79#ibcon#read 5, iclass 22, count 0 2006.173.22:33:00.79#ibcon#about to read 6, iclass 22, count 0 2006.173.22:33:00.79#ibcon#read 6, iclass 22, count 0 2006.173.22:33:00.79#ibcon#end of sib2, iclass 22, count 0 2006.173.22:33:00.79#ibcon#*after write, iclass 22, count 0 2006.173.22:33:00.79#ibcon#*before return 0, iclass 22, count 0 2006.173.22:33:00.79#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.22:33:00.79#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.22:33:00.79#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.22:33:00.79#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.22:33:00.79$vck44/vblo=4,679.99 2006.173.22:33:00.79#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.22:33:00.79#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.22:33:00.79#ibcon#ireg 17 cls_cnt 0 2006.173.22:33:00.79#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.22:33:00.79#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.22:33:00.79#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.22:33:00.79#ibcon#enter wrdev, iclass 24, count 0 2006.173.22:33:00.79#ibcon#first serial, iclass 24, count 0 2006.173.22:33:00.79#ibcon#enter sib2, iclass 24, count 0 2006.173.22:33:00.79#ibcon#flushed, iclass 24, count 0 2006.173.22:33:00.79#ibcon#about to write, iclass 24, count 0 2006.173.22:33:00.79#ibcon#wrote, iclass 24, count 0 2006.173.22:33:00.79#ibcon#about to read 3, iclass 24, count 0 2006.173.22:33:00.81#ibcon#read 3, iclass 24, count 0 2006.173.22:33:00.81#ibcon#about to read 4, iclass 24, count 0 2006.173.22:33:00.81#ibcon#read 4, iclass 24, count 0 2006.173.22:33:00.81#ibcon#about to read 5, iclass 24, count 0 2006.173.22:33:00.81#ibcon#read 5, iclass 24, count 0 2006.173.22:33:00.81#ibcon#about to read 6, iclass 24, count 0 2006.173.22:33:00.81#ibcon#read 6, iclass 24, count 0 2006.173.22:33:00.81#ibcon#end of sib2, iclass 24, count 0 2006.173.22:33:00.81#ibcon#*mode == 0, iclass 24, count 0 2006.173.22:33:00.81#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.22:33:00.81#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.22:33:00.81#ibcon#*before write, iclass 24, count 0 2006.173.22:33:00.81#ibcon#enter sib2, iclass 24, count 0 2006.173.22:33:00.81#ibcon#flushed, iclass 24, count 0 2006.173.22:33:00.81#ibcon#about to write, iclass 24, count 0 2006.173.22:33:00.81#ibcon#wrote, iclass 24, count 0 2006.173.22:33:00.81#ibcon#about to read 3, iclass 24, count 0 2006.173.22:33:00.85#ibcon#read 3, iclass 24, count 0 2006.173.22:33:00.85#ibcon#about to read 4, iclass 24, count 0 2006.173.22:33:00.85#ibcon#read 4, iclass 24, count 0 2006.173.22:33:00.85#ibcon#about to read 5, iclass 24, count 0 2006.173.22:33:00.85#ibcon#read 5, iclass 24, count 0 2006.173.22:33:00.85#ibcon#about to read 6, iclass 24, count 0 2006.173.22:33:00.85#ibcon#read 6, iclass 24, count 0 2006.173.22:33:00.85#ibcon#end of sib2, iclass 24, count 0 2006.173.22:33:00.85#ibcon#*after write, iclass 24, count 0 2006.173.22:33:00.85#ibcon#*before return 0, iclass 24, count 0 2006.173.22:33:00.85#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.22:33:00.85#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.22:33:00.85#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.22:33:00.85#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.22:33:00.85$vck44/vb=4,4 2006.173.22:33:00.85#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.22:33:00.85#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.22:33:00.85#ibcon#ireg 11 cls_cnt 2 2006.173.22:33:00.85#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.22:33:00.91#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.22:33:00.91#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.22:33:00.91#ibcon#enter wrdev, iclass 26, count 2 2006.173.22:33:00.91#ibcon#first serial, iclass 26, count 2 2006.173.22:33:00.91#ibcon#enter sib2, iclass 26, count 2 2006.173.22:33:00.91#ibcon#flushed, iclass 26, count 2 2006.173.22:33:00.91#ibcon#about to write, iclass 26, count 2 2006.173.22:33:00.91#ibcon#wrote, iclass 26, count 2 2006.173.22:33:00.91#ibcon#about to read 3, iclass 26, count 2 2006.173.22:33:00.93#ibcon#read 3, iclass 26, count 2 2006.173.22:33:00.93#ibcon#about to read 4, iclass 26, count 2 2006.173.22:33:00.93#ibcon#read 4, iclass 26, count 2 2006.173.22:33:00.93#ibcon#about to read 5, iclass 26, count 2 2006.173.22:33:00.93#ibcon#read 5, iclass 26, count 2 2006.173.22:33:00.93#ibcon#about to read 6, iclass 26, count 2 2006.173.22:33:00.93#ibcon#read 6, iclass 26, count 2 2006.173.22:33:00.93#ibcon#end of sib2, iclass 26, count 2 2006.173.22:33:00.93#ibcon#*mode == 0, iclass 26, count 2 2006.173.22:33:00.93#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.22:33:00.93#ibcon#[27=AT04-04\r\n] 2006.173.22:33:00.93#ibcon#*before write, iclass 26, count 2 2006.173.22:33:00.93#ibcon#enter sib2, iclass 26, count 2 2006.173.22:33:00.93#ibcon#flushed, iclass 26, count 2 2006.173.22:33:00.93#ibcon#about to write, iclass 26, count 2 2006.173.22:33:00.93#ibcon#wrote, iclass 26, count 2 2006.173.22:33:00.93#ibcon#about to read 3, iclass 26, count 2 2006.173.22:33:00.96#ibcon#read 3, iclass 26, count 2 2006.173.22:33:00.96#ibcon#about to read 4, iclass 26, count 2 2006.173.22:33:00.96#ibcon#read 4, iclass 26, count 2 2006.173.22:33:00.96#ibcon#about to read 5, iclass 26, count 2 2006.173.22:33:00.96#ibcon#read 5, iclass 26, count 2 2006.173.22:33:00.96#ibcon#about to read 6, iclass 26, count 2 2006.173.22:33:00.96#ibcon#read 6, iclass 26, count 2 2006.173.22:33:00.96#ibcon#end of sib2, iclass 26, count 2 2006.173.22:33:00.96#ibcon#*after write, iclass 26, count 2 2006.173.22:33:00.96#ibcon#*before return 0, iclass 26, count 2 2006.173.22:33:00.96#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.22:33:00.96#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.22:33:00.96#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.22:33:00.96#ibcon#ireg 7 cls_cnt 0 2006.173.22:33:00.96#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.22:33:01.08#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.22:33:01.08#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.22:33:01.08#ibcon#enter wrdev, iclass 26, count 0 2006.173.22:33:01.08#ibcon#first serial, iclass 26, count 0 2006.173.22:33:01.08#ibcon#enter sib2, iclass 26, count 0 2006.173.22:33:01.08#ibcon#flushed, iclass 26, count 0 2006.173.22:33:01.08#ibcon#about to write, iclass 26, count 0 2006.173.22:33:01.08#ibcon#wrote, iclass 26, count 0 2006.173.22:33:01.08#ibcon#about to read 3, iclass 26, count 0 2006.173.22:33:01.10#ibcon#read 3, iclass 26, count 0 2006.173.22:33:01.10#ibcon#about to read 4, iclass 26, count 0 2006.173.22:33:01.10#ibcon#read 4, iclass 26, count 0 2006.173.22:33:01.10#ibcon#about to read 5, iclass 26, count 0 2006.173.22:33:01.10#ibcon#read 5, iclass 26, count 0 2006.173.22:33:01.10#ibcon#about to read 6, iclass 26, count 0 2006.173.22:33:01.10#ibcon#read 6, iclass 26, count 0 2006.173.22:33:01.10#ibcon#end of sib2, iclass 26, count 0 2006.173.22:33:01.10#ibcon#*mode == 0, iclass 26, count 0 2006.173.22:33:01.10#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.22:33:01.10#ibcon#[27=USB\r\n] 2006.173.22:33:01.10#ibcon#*before write, iclass 26, count 0 2006.173.22:33:01.10#ibcon#enter sib2, iclass 26, count 0 2006.173.22:33:01.10#ibcon#flushed, iclass 26, count 0 2006.173.22:33:01.10#ibcon#about to write, iclass 26, count 0 2006.173.22:33:01.10#ibcon#wrote, iclass 26, count 0 2006.173.22:33:01.10#ibcon#about to read 3, iclass 26, count 0 2006.173.22:33:01.13#ibcon#read 3, iclass 26, count 0 2006.173.22:33:01.13#ibcon#about to read 4, iclass 26, count 0 2006.173.22:33:01.13#ibcon#read 4, iclass 26, count 0 2006.173.22:33:01.13#ibcon#about to read 5, iclass 26, count 0 2006.173.22:33:01.13#ibcon#read 5, iclass 26, count 0 2006.173.22:33:01.13#ibcon#about to read 6, iclass 26, count 0 2006.173.22:33:01.13#ibcon#read 6, iclass 26, count 0 2006.173.22:33:01.13#ibcon#end of sib2, iclass 26, count 0 2006.173.22:33:01.13#ibcon#*after write, iclass 26, count 0 2006.173.22:33:01.13#ibcon#*before return 0, iclass 26, count 0 2006.173.22:33:01.13#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.22:33:01.13#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.22:33:01.13#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.22:33:01.13#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.22:33:01.13$vck44/vblo=5,709.99 2006.173.22:33:01.13#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.22:33:01.13#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.22:33:01.13#ibcon#ireg 17 cls_cnt 0 2006.173.22:33:01.13#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.22:33:01.13#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.22:33:01.13#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.22:33:01.13#ibcon#enter wrdev, iclass 28, count 0 2006.173.22:33:01.13#ibcon#first serial, iclass 28, count 0 2006.173.22:33:01.13#ibcon#enter sib2, iclass 28, count 0 2006.173.22:33:01.13#ibcon#flushed, iclass 28, count 0 2006.173.22:33:01.13#ibcon#about to write, iclass 28, count 0 2006.173.22:33:01.13#ibcon#wrote, iclass 28, count 0 2006.173.22:33:01.13#ibcon#about to read 3, iclass 28, count 0 2006.173.22:33:01.15#ibcon#read 3, iclass 28, count 0 2006.173.22:33:01.15#ibcon#about to read 4, iclass 28, count 0 2006.173.22:33:01.15#ibcon#read 4, iclass 28, count 0 2006.173.22:33:01.15#ibcon#about to read 5, iclass 28, count 0 2006.173.22:33:01.15#ibcon#read 5, iclass 28, count 0 2006.173.22:33:01.15#ibcon#about to read 6, iclass 28, count 0 2006.173.22:33:01.15#ibcon#read 6, iclass 28, count 0 2006.173.22:33:01.15#ibcon#end of sib2, iclass 28, count 0 2006.173.22:33:01.15#ibcon#*mode == 0, iclass 28, count 0 2006.173.22:33:01.15#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.22:33:01.15#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.22:33:01.15#ibcon#*before write, iclass 28, count 0 2006.173.22:33:01.15#ibcon#enter sib2, iclass 28, count 0 2006.173.22:33:01.15#ibcon#flushed, iclass 28, count 0 2006.173.22:33:01.15#ibcon#about to write, iclass 28, count 0 2006.173.22:33:01.15#ibcon#wrote, iclass 28, count 0 2006.173.22:33:01.15#ibcon#about to read 3, iclass 28, count 0 2006.173.22:33:01.19#ibcon#read 3, iclass 28, count 0 2006.173.22:33:01.19#ibcon#about to read 4, iclass 28, count 0 2006.173.22:33:01.19#ibcon#read 4, iclass 28, count 0 2006.173.22:33:01.19#ibcon#about to read 5, iclass 28, count 0 2006.173.22:33:01.19#ibcon#read 5, iclass 28, count 0 2006.173.22:33:01.19#ibcon#about to read 6, iclass 28, count 0 2006.173.22:33:01.19#ibcon#read 6, iclass 28, count 0 2006.173.22:33:01.19#ibcon#end of sib2, iclass 28, count 0 2006.173.22:33:01.19#ibcon#*after write, iclass 28, count 0 2006.173.22:33:01.19#ibcon#*before return 0, iclass 28, count 0 2006.173.22:33:01.19#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.22:33:01.19#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.22:33:01.19#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.22:33:01.19#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.22:33:01.19$vck44/vb=5,4 2006.173.22:33:01.19#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.22:33:01.19#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.22:33:01.19#ibcon#ireg 11 cls_cnt 2 2006.173.22:33:01.19#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.22:33:01.25#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.22:33:01.25#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.22:33:01.25#ibcon#enter wrdev, iclass 30, count 2 2006.173.22:33:01.25#ibcon#first serial, iclass 30, count 2 2006.173.22:33:01.25#ibcon#enter sib2, iclass 30, count 2 2006.173.22:33:01.25#ibcon#flushed, iclass 30, count 2 2006.173.22:33:01.25#ibcon#about to write, iclass 30, count 2 2006.173.22:33:01.25#ibcon#wrote, iclass 30, count 2 2006.173.22:33:01.25#ibcon#about to read 3, iclass 30, count 2 2006.173.22:33:01.27#ibcon#read 3, iclass 30, count 2 2006.173.22:33:01.27#ibcon#about to read 4, iclass 30, count 2 2006.173.22:33:01.27#ibcon#read 4, iclass 30, count 2 2006.173.22:33:01.27#ibcon#about to read 5, iclass 30, count 2 2006.173.22:33:01.27#ibcon#read 5, iclass 30, count 2 2006.173.22:33:01.27#ibcon#about to read 6, iclass 30, count 2 2006.173.22:33:01.27#ibcon#read 6, iclass 30, count 2 2006.173.22:33:01.27#ibcon#end of sib2, iclass 30, count 2 2006.173.22:33:01.27#ibcon#*mode == 0, iclass 30, count 2 2006.173.22:33:01.27#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.22:33:01.27#ibcon#[27=AT05-04\r\n] 2006.173.22:33:01.27#ibcon#*before write, iclass 30, count 2 2006.173.22:33:01.27#ibcon#enter sib2, iclass 30, count 2 2006.173.22:33:01.27#ibcon#flushed, iclass 30, count 2 2006.173.22:33:01.27#ibcon#about to write, iclass 30, count 2 2006.173.22:33:01.27#ibcon#wrote, iclass 30, count 2 2006.173.22:33:01.27#ibcon#about to read 3, iclass 30, count 2 2006.173.22:33:01.30#ibcon#read 3, iclass 30, count 2 2006.173.22:33:01.30#ibcon#about to read 4, iclass 30, count 2 2006.173.22:33:01.30#ibcon#read 4, iclass 30, count 2 2006.173.22:33:01.30#ibcon#about to read 5, iclass 30, count 2 2006.173.22:33:01.30#ibcon#read 5, iclass 30, count 2 2006.173.22:33:01.30#ibcon#about to read 6, iclass 30, count 2 2006.173.22:33:01.30#ibcon#read 6, iclass 30, count 2 2006.173.22:33:01.30#ibcon#end of sib2, iclass 30, count 2 2006.173.22:33:01.30#ibcon#*after write, iclass 30, count 2 2006.173.22:33:01.30#ibcon#*before return 0, iclass 30, count 2 2006.173.22:33:01.30#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.22:33:01.30#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.22:33:01.30#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.22:33:01.30#ibcon#ireg 7 cls_cnt 0 2006.173.22:33:01.30#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.22:33:01.42#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.22:33:01.42#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.22:33:01.42#ibcon#enter wrdev, iclass 30, count 0 2006.173.22:33:01.42#ibcon#first serial, iclass 30, count 0 2006.173.22:33:01.42#ibcon#enter sib2, iclass 30, count 0 2006.173.22:33:01.42#ibcon#flushed, iclass 30, count 0 2006.173.22:33:01.42#ibcon#about to write, iclass 30, count 0 2006.173.22:33:01.42#ibcon#wrote, iclass 30, count 0 2006.173.22:33:01.42#ibcon#about to read 3, iclass 30, count 0 2006.173.22:33:01.44#ibcon#read 3, iclass 30, count 0 2006.173.22:33:01.44#ibcon#about to read 4, iclass 30, count 0 2006.173.22:33:01.44#ibcon#read 4, iclass 30, count 0 2006.173.22:33:01.44#ibcon#about to read 5, iclass 30, count 0 2006.173.22:33:01.44#ibcon#read 5, iclass 30, count 0 2006.173.22:33:01.44#ibcon#about to read 6, iclass 30, count 0 2006.173.22:33:01.44#ibcon#read 6, iclass 30, count 0 2006.173.22:33:01.44#ibcon#end of sib2, iclass 30, count 0 2006.173.22:33:01.44#ibcon#*mode == 0, iclass 30, count 0 2006.173.22:33:01.44#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.22:33:01.44#ibcon#[27=USB\r\n] 2006.173.22:33:01.44#ibcon#*before write, iclass 30, count 0 2006.173.22:33:01.44#ibcon#enter sib2, iclass 30, count 0 2006.173.22:33:01.44#ibcon#flushed, iclass 30, count 0 2006.173.22:33:01.44#ibcon#about to write, iclass 30, count 0 2006.173.22:33:01.44#ibcon#wrote, iclass 30, count 0 2006.173.22:33:01.44#ibcon#about to read 3, iclass 30, count 0 2006.173.22:33:01.47#ibcon#read 3, iclass 30, count 0 2006.173.22:33:01.47#ibcon#about to read 4, iclass 30, count 0 2006.173.22:33:01.47#ibcon#read 4, iclass 30, count 0 2006.173.22:33:01.47#ibcon#about to read 5, iclass 30, count 0 2006.173.22:33:01.47#ibcon#read 5, iclass 30, count 0 2006.173.22:33:01.47#ibcon#about to read 6, iclass 30, count 0 2006.173.22:33:01.47#ibcon#read 6, iclass 30, count 0 2006.173.22:33:01.47#ibcon#end of sib2, iclass 30, count 0 2006.173.22:33:01.47#ibcon#*after write, iclass 30, count 0 2006.173.22:33:01.47#ibcon#*before return 0, iclass 30, count 0 2006.173.22:33:01.47#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.22:33:01.47#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.22:33:01.47#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.22:33:01.47#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.22:33:01.47$vck44/vblo=6,719.99 2006.173.22:33:01.47#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.22:33:01.47#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.22:33:01.47#ibcon#ireg 17 cls_cnt 0 2006.173.22:33:01.47#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.22:33:01.47#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.22:33:01.47#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.22:33:01.47#ibcon#enter wrdev, iclass 32, count 0 2006.173.22:33:01.47#ibcon#first serial, iclass 32, count 0 2006.173.22:33:01.47#ibcon#enter sib2, iclass 32, count 0 2006.173.22:33:01.47#ibcon#flushed, iclass 32, count 0 2006.173.22:33:01.47#ibcon#about to write, iclass 32, count 0 2006.173.22:33:01.47#ibcon#wrote, iclass 32, count 0 2006.173.22:33:01.47#ibcon#about to read 3, iclass 32, count 0 2006.173.22:33:01.49#ibcon#read 3, iclass 32, count 0 2006.173.22:33:01.49#ibcon#about to read 4, iclass 32, count 0 2006.173.22:33:01.49#ibcon#read 4, iclass 32, count 0 2006.173.22:33:01.49#ibcon#about to read 5, iclass 32, count 0 2006.173.22:33:01.49#ibcon#read 5, iclass 32, count 0 2006.173.22:33:01.49#ibcon#about to read 6, iclass 32, count 0 2006.173.22:33:01.49#ibcon#read 6, iclass 32, count 0 2006.173.22:33:01.49#ibcon#end of sib2, iclass 32, count 0 2006.173.22:33:01.49#ibcon#*mode == 0, iclass 32, count 0 2006.173.22:33:01.49#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.22:33:01.49#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.22:33:01.49#ibcon#*before write, iclass 32, count 0 2006.173.22:33:01.49#ibcon#enter sib2, iclass 32, count 0 2006.173.22:33:01.49#ibcon#flushed, iclass 32, count 0 2006.173.22:33:01.49#ibcon#about to write, iclass 32, count 0 2006.173.22:33:01.49#ibcon#wrote, iclass 32, count 0 2006.173.22:33:01.49#ibcon#about to read 3, iclass 32, count 0 2006.173.22:33:01.53#ibcon#read 3, iclass 32, count 0 2006.173.22:33:01.53#ibcon#about to read 4, iclass 32, count 0 2006.173.22:33:01.53#ibcon#read 4, iclass 32, count 0 2006.173.22:33:01.53#ibcon#about to read 5, iclass 32, count 0 2006.173.22:33:01.53#ibcon#read 5, iclass 32, count 0 2006.173.22:33:01.53#ibcon#about to read 6, iclass 32, count 0 2006.173.22:33:01.53#ibcon#read 6, iclass 32, count 0 2006.173.22:33:01.53#ibcon#end of sib2, iclass 32, count 0 2006.173.22:33:01.53#ibcon#*after write, iclass 32, count 0 2006.173.22:33:01.53#ibcon#*before return 0, iclass 32, count 0 2006.173.22:33:01.53#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.22:33:01.53#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.22:33:01.53#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.22:33:01.53#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.22:33:01.53$vck44/vb=6,4 2006.173.22:33:01.53#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.22:33:01.53#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.22:33:01.53#ibcon#ireg 11 cls_cnt 2 2006.173.22:33:01.53#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.22:33:01.59#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.22:33:01.59#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.22:33:01.59#ibcon#enter wrdev, iclass 34, count 2 2006.173.22:33:01.59#ibcon#first serial, iclass 34, count 2 2006.173.22:33:01.59#ibcon#enter sib2, iclass 34, count 2 2006.173.22:33:01.59#ibcon#flushed, iclass 34, count 2 2006.173.22:33:01.59#ibcon#about to write, iclass 34, count 2 2006.173.22:33:01.59#ibcon#wrote, iclass 34, count 2 2006.173.22:33:01.59#ibcon#about to read 3, iclass 34, count 2 2006.173.22:33:01.61#ibcon#read 3, iclass 34, count 2 2006.173.22:33:01.61#ibcon#about to read 4, iclass 34, count 2 2006.173.22:33:01.61#ibcon#read 4, iclass 34, count 2 2006.173.22:33:01.61#ibcon#about to read 5, iclass 34, count 2 2006.173.22:33:01.61#ibcon#read 5, iclass 34, count 2 2006.173.22:33:01.61#ibcon#about to read 6, iclass 34, count 2 2006.173.22:33:01.61#ibcon#read 6, iclass 34, count 2 2006.173.22:33:01.61#ibcon#end of sib2, iclass 34, count 2 2006.173.22:33:01.61#ibcon#*mode == 0, iclass 34, count 2 2006.173.22:33:01.61#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.22:33:01.61#ibcon#[27=AT06-04\r\n] 2006.173.22:33:01.61#ibcon#*before write, iclass 34, count 2 2006.173.22:33:01.61#ibcon#enter sib2, iclass 34, count 2 2006.173.22:33:01.61#ibcon#flushed, iclass 34, count 2 2006.173.22:33:01.61#ibcon#about to write, iclass 34, count 2 2006.173.22:33:01.61#ibcon#wrote, iclass 34, count 2 2006.173.22:33:01.61#ibcon#about to read 3, iclass 34, count 2 2006.173.22:33:01.64#ibcon#read 3, iclass 34, count 2 2006.173.22:33:01.64#ibcon#about to read 4, iclass 34, count 2 2006.173.22:33:01.64#ibcon#read 4, iclass 34, count 2 2006.173.22:33:01.64#ibcon#about to read 5, iclass 34, count 2 2006.173.22:33:01.64#ibcon#read 5, iclass 34, count 2 2006.173.22:33:01.64#ibcon#about to read 6, iclass 34, count 2 2006.173.22:33:01.64#ibcon#read 6, iclass 34, count 2 2006.173.22:33:01.64#ibcon#end of sib2, iclass 34, count 2 2006.173.22:33:01.64#ibcon#*after write, iclass 34, count 2 2006.173.22:33:01.64#ibcon#*before return 0, iclass 34, count 2 2006.173.22:33:01.64#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.22:33:01.64#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.22:33:01.64#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.22:33:01.64#ibcon#ireg 7 cls_cnt 0 2006.173.22:33:01.64#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.22:33:01.76#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.22:33:01.76#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.22:33:01.76#ibcon#enter wrdev, iclass 34, count 0 2006.173.22:33:01.76#ibcon#first serial, iclass 34, count 0 2006.173.22:33:01.76#ibcon#enter sib2, iclass 34, count 0 2006.173.22:33:01.76#ibcon#flushed, iclass 34, count 0 2006.173.22:33:01.76#ibcon#about to write, iclass 34, count 0 2006.173.22:33:01.76#ibcon#wrote, iclass 34, count 0 2006.173.22:33:01.76#ibcon#about to read 3, iclass 34, count 0 2006.173.22:33:01.78#ibcon#read 3, iclass 34, count 0 2006.173.22:33:01.78#ibcon#about to read 4, iclass 34, count 0 2006.173.22:33:01.78#ibcon#read 4, iclass 34, count 0 2006.173.22:33:01.78#ibcon#about to read 5, iclass 34, count 0 2006.173.22:33:01.78#ibcon#read 5, iclass 34, count 0 2006.173.22:33:01.78#ibcon#about to read 6, iclass 34, count 0 2006.173.22:33:01.78#ibcon#read 6, iclass 34, count 0 2006.173.22:33:01.78#ibcon#end of sib2, iclass 34, count 0 2006.173.22:33:01.78#ibcon#*mode == 0, iclass 34, count 0 2006.173.22:33:01.78#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.22:33:01.78#ibcon#[27=USB\r\n] 2006.173.22:33:01.78#ibcon#*before write, iclass 34, count 0 2006.173.22:33:01.78#ibcon#enter sib2, iclass 34, count 0 2006.173.22:33:01.78#ibcon#flushed, iclass 34, count 0 2006.173.22:33:01.78#ibcon#about to write, iclass 34, count 0 2006.173.22:33:01.78#ibcon#wrote, iclass 34, count 0 2006.173.22:33:01.78#ibcon#about to read 3, iclass 34, count 0 2006.173.22:33:01.81#ibcon#read 3, iclass 34, count 0 2006.173.22:33:01.81#ibcon#about to read 4, iclass 34, count 0 2006.173.22:33:01.81#ibcon#read 4, iclass 34, count 0 2006.173.22:33:01.81#ibcon#about to read 5, iclass 34, count 0 2006.173.22:33:01.81#ibcon#read 5, iclass 34, count 0 2006.173.22:33:01.81#ibcon#about to read 6, iclass 34, count 0 2006.173.22:33:01.81#ibcon#read 6, iclass 34, count 0 2006.173.22:33:01.81#ibcon#end of sib2, iclass 34, count 0 2006.173.22:33:01.81#ibcon#*after write, iclass 34, count 0 2006.173.22:33:01.81#ibcon#*before return 0, iclass 34, count 0 2006.173.22:33:01.81#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.22:33:01.81#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.22:33:01.81#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.22:33:01.81#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.22:33:01.81$vck44/vblo=7,734.99 2006.173.22:33:01.81#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.22:33:01.81#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.22:33:01.81#ibcon#ireg 17 cls_cnt 0 2006.173.22:33:01.81#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.22:33:01.81#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.22:33:01.81#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.22:33:01.81#ibcon#enter wrdev, iclass 36, count 0 2006.173.22:33:01.81#ibcon#first serial, iclass 36, count 0 2006.173.22:33:01.81#ibcon#enter sib2, iclass 36, count 0 2006.173.22:33:01.81#ibcon#flushed, iclass 36, count 0 2006.173.22:33:01.81#ibcon#about to write, iclass 36, count 0 2006.173.22:33:01.81#ibcon#wrote, iclass 36, count 0 2006.173.22:33:01.81#ibcon#about to read 3, iclass 36, count 0 2006.173.22:33:01.83#ibcon#read 3, iclass 36, count 0 2006.173.22:33:01.83#ibcon#about to read 4, iclass 36, count 0 2006.173.22:33:01.83#ibcon#read 4, iclass 36, count 0 2006.173.22:33:01.83#ibcon#about to read 5, iclass 36, count 0 2006.173.22:33:01.83#ibcon#read 5, iclass 36, count 0 2006.173.22:33:01.83#ibcon#about to read 6, iclass 36, count 0 2006.173.22:33:01.83#ibcon#read 6, iclass 36, count 0 2006.173.22:33:01.83#ibcon#end of sib2, iclass 36, count 0 2006.173.22:33:01.83#ibcon#*mode == 0, iclass 36, count 0 2006.173.22:33:01.83#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.22:33:01.83#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.22:33:01.83#ibcon#*before write, iclass 36, count 0 2006.173.22:33:01.83#ibcon#enter sib2, iclass 36, count 0 2006.173.22:33:01.83#ibcon#flushed, iclass 36, count 0 2006.173.22:33:01.83#ibcon#about to write, iclass 36, count 0 2006.173.22:33:01.83#ibcon#wrote, iclass 36, count 0 2006.173.22:33:01.83#ibcon#about to read 3, iclass 36, count 0 2006.173.22:33:01.87#ibcon#read 3, iclass 36, count 0 2006.173.22:33:01.87#ibcon#about to read 4, iclass 36, count 0 2006.173.22:33:01.87#ibcon#read 4, iclass 36, count 0 2006.173.22:33:01.87#ibcon#about to read 5, iclass 36, count 0 2006.173.22:33:01.87#ibcon#read 5, iclass 36, count 0 2006.173.22:33:01.87#ibcon#about to read 6, iclass 36, count 0 2006.173.22:33:01.87#ibcon#read 6, iclass 36, count 0 2006.173.22:33:01.87#ibcon#end of sib2, iclass 36, count 0 2006.173.22:33:01.87#ibcon#*after write, iclass 36, count 0 2006.173.22:33:01.87#ibcon#*before return 0, iclass 36, count 0 2006.173.22:33:01.87#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.22:33:01.87#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.22:33:01.87#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.22:33:01.87#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.22:33:01.87$vck44/vb=7,4 2006.173.22:33:01.87#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.22:33:01.87#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.22:33:01.87#ibcon#ireg 11 cls_cnt 2 2006.173.22:33:01.87#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.22:33:01.93#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.22:33:01.93#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.22:33:01.93#ibcon#enter wrdev, iclass 38, count 2 2006.173.22:33:01.93#ibcon#first serial, iclass 38, count 2 2006.173.22:33:01.93#ibcon#enter sib2, iclass 38, count 2 2006.173.22:33:01.93#ibcon#flushed, iclass 38, count 2 2006.173.22:33:01.93#ibcon#about to write, iclass 38, count 2 2006.173.22:33:01.93#ibcon#wrote, iclass 38, count 2 2006.173.22:33:01.93#ibcon#about to read 3, iclass 38, count 2 2006.173.22:33:01.95#ibcon#read 3, iclass 38, count 2 2006.173.22:33:01.95#ibcon#about to read 4, iclass 38, count 2 2006.173.22:33:01.95#ibcon#read 4, iclass 38, count 2 2006.173.22:33:01.95#ibcon#about to read 5, iclass 38, count 2 2006.173.22:33:01.95#ibcon#read 5, iclass 38, count 2 2006.173.22:33:01.95#ibcon#about to read 6, iclass 38, count 2 2006.173.22:33:01.95#ibcon#read 6, iclass 38, count 2 2006.173.22:33:01.95#ibcon#end of sib2, iclass 38, count 2 2006.173.22:33:01.95#ibcon#*mode == 0, iclass 38, count 2 2006.173.22:33:01.95#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.22:33:01.95#ibcon#[27=AT07-04\r\n] 2006.173.22:33:01.95#ibcon#*before write, iclass 38, count 2 2006.173.22:33:01.95#ibcon#enter sib2, iclass 38, count 2 2006.173.22:33:01.95#ibcon#flushed, iclass 38, count 2 2006.173.22:33:01.95#ibcon#about to write, iclass 38, count 2 2006.173.22:33:01.95#ibcon#wrote, iclass 38, count 2 2006.173.22:33:01.95#ibcon#about to read 3, iclass 38, count 2 2006.173.22:33:01.98#ibcon#read 3, iclass 38, count 2 2006.173.22:33:01.98#ibcon#about to read 4, iclass 38, count 2 2006.173.22:33:01.98#ibcon#read 4, iclass 38, count 2 2006.173.22:33:01.98#ibcon#about to read 5, iclass 38, count 2 2006.173.22:33:01.98#ibcon#read 5, iclass 38, count 2 2006.173.22:33:01.98#ibcon#about to read 6, iclass 38, count 2 2006.173.22:33:01.98#ibcon#read 6, iclass 38, count 2 2006.173.22:33:01.98#ibcon#end of sib2, iclass 38, count 2 2006.173.22:33:01.98#ibcon#*after write, iclass 38, count 2 2006.173.22:33:01.98#ibcon#*before return 0, iclass 38, count 2 2006.173.22:33:01.98#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.22:33:01.98#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.22:33:01.98#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.22:33:01.98#ibcon#ireg 7 cls_cnt 0 2006.173.22:33:01.98#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.22:33:02.10#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.22:33:02.10#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.22:33:02.10#ibcon#enter wrdev, iclass 38, count 0 2006.173.22:33:02.10#ibcon#first serial, iclass 38, count 0 2006.173.22:33:02.10#ibcon#enter sib2, iclass 38, count 0 2006.173.22:33:02.10#ibcon#flushed, iclass 38, count 0 2006.173.22:33:02.10#ibcon#about to write, iclass 38, count 0 2006.173.22:33:02.10#ibcon#wrote, iclass 38, count 0 2006.173.22:33:02.10#ibcon#about to read 3, iclass 38, count 0 2006.173.22:33:02.12#ibcon#read 3, iclass 38, count 0 2006.173.22:33:02.12#ibcon#about to read 4, iclass 38, count 0 2006.173.22:33:02.12#ibcon#read 4, iclass 38, count 0 2006.173.22:33:02.12#ibcon#about to read 5, iclass 38, count 0 2006.173.22:33:02.12#ibcon#read 5, iclass 38, count 0 2006.173.22:33:02.12#ibcon#about to read 6, iclass 38, count 0 2006.173.22:33:02.12#ibcon#read 6, iclass 38, count 0 2006.173.22:33:02.12#ibcon#end of sib2, iclass 38, count 0 2006.173.22:33:02.12#ibcon#*mode == 0, iclass 38, count 0 2006.173.22:33:02.12#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.22:33:02.12#ibcon#[27=USB\r\n] 2006.173.22:33:02.12#ibcon#*before write, iclass 38, count 0 2006.173.22:33:02.12#ibcon#enter sib2, iclass 38, count 0 2006.173.22:33:02.12#ibcon#flushed, iclass 38, count 0 2006.173.22:33:02.12#ibcon#about to write, iclass 38, count 0 2006.173.22:33:02.12#ibcon#wrote, iclass 38, count 0 2006.173.22:33:02.12#ibcon#about to read 3, iclass 38, count 0 2006.173.22:33:02.15#ibcon#read 3, iclass 38, count 0 2006.173.22:33:02.15#ibcon#about to read 4, iclass 38, count 0 2006.173.22:33:02.15#ibcon#read 4, iclass 38, count 0 2006.173.22:33:02.15#ibcon#about to read 5, iclass 38, count 0 2006.173.22:33:02.15#ibcon#read 5, iclass 38, count 0 2006.173.22:33:02.15#ibcon#about to read 6, iclass 38, count 0 2006.173.22:33:02.15#ibcon#read 6, iclass 38, count 0 2006.173.22:33:02.15#ibcon#end of sib2, iclass 38, count 0 2006.173.22:33:02.15#ibcon#*after write, iclass 38, count 0 2006.173.22:33:02.15#ibcon#*before return 0, iclass 38, count 0 2006.173.22:33:02.15#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.22:33:02.15#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.22:33:02.15#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.22:33:02.15#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.22:33:02.15$vck44/vblo=8,744.99 2006.173.22:33:02.15#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.22:33:02.15#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.22:33:02.15#ibcon#ireg 17 cls_cnt 0 2006.173.22:33:02.15#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.22:33:02.15#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.22:33:02.15#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.22:33:02.15#ibcon#enter wrdev, iclass 40, count 0 2006.173.22:33:02.15#ibcon#first serial, iclass 40, count 0 2006.173.22:33:02.15#ibcon#enter sib2, iclass 40, count 0 2006.173.22:33:02.15#ibcon#flushed, iclass 40, count 0 2006.173.22:33:02.15#ibcon#about to write, iclass 40, count 0 2006.173.22:33:02.15#ibcon#wrote, iclass 40, count 0 2006.173.22:33:02.15#ibcon#about to read 3, iclass 40, count 0 2006.173.22:33:02.17#ibcon#read 3, iclass 40, count 0 2006.173.22:33:02.17#ibcon#about to read 4, iclass 40, count 0 2006.173.22:33:02.17#ibcon#read 4, iclass 40, count 0 2006.173.22:33:02.17#ibcon#about to read 5, iclass 40, count 0 2006.173.22:33:02.17#ibcon#read 5, iclass 40, count 0 2006.173.22:33:02.17#ibcon#about to read 6, iclass 40, count 0 2006.173.22:33:02.17#ibcon#read 6, iclass 40, count 0 2006.173.22:33:02.17#ibcon#end of sib2, iclass 40, count 0 2006.173.22:33:02.17#ibcon#*mode == 0, iclass 40, count 0 2006.173.22:33:02.17#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.22:33:02.17#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.22:33:02.17#ibcon#*before write, iclass 40, count 0 2006.173.22:33:02.17#ibcon#enter sib2, iclass 40, count 0 2006.173.22:33:02.17#ibcon#flushed, iclass 40, count 0 2006.173.22:33:02.17#ibcon#about to write, iclass 40, count 0 2006.173.22:33:02.17#ibcon#wrote, iclass 40, count 0 2006.173.22:33:02.17#ibcon#about to read 3, iclass 40, count 0 2006.173.22:33:02.21#ibcon#read 3, iclass 40, count 0 2006.173.22:33:02.21#ibcon#about to read 4, iclass 40, count 0 2006.173.22:33:02.21#ibcon#read 4, iclass 40, count 0 2006.173.22:33:02.21#ibcon#about to read 5, iclass 40, count 0 2006.173.22:33:02.21#ibcon#read 5, iclass 40, count 0 2006.173.22:33:02.21#ibcon#about to read 6, iclass 40, count 0 2006.173.22:33:02.21#ibcon#read 6, iclass 40, count 0 2006.173.22:33:02.21#ibcon#end of sib2, iclass 40, count 0 2006.173.22:33:02.21#ibcon#*after write, iclass 40, count 0 2006.173.22:33:02.21#ibcon#*before return 0, iclass 40, count 0 2006.173.22:33:02.21#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.22:33:02.21#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.22:33:02.21#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.22:33:02.21#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.22:33:02.21$vck44/vb=8,4 2006.173.22:33:02.21#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.22:33:02.21#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.22:33:02.21#ibcon#ireg 11 cls_cnt 2 2006.173.22:33:02.21#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.22:33:02.27#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.22:33:02.27#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.22:33:02.27#ibcon#enter wrdev, iclass 4, count 2 2006.173.22:33:02.27#ibcon#first serial, iclass 4, count 2 2006.173.22:33:02.27#ibcon#enter sib2, iclass 4, count 2 2006.173.22:33:02.27#ibcon#flushed, iclass 4, count 2 2006.173.22:33:02.27#ibcon#about to write, iclass 4, count 2 2006.173.22:33:02.27#ibcon#wrote, iclass 4, count 2 2006.173.22:33:02.27#ibcon#about to read 3, iclass 4, count 2 2006.173.22:33:02.29#ibcon#read 3, iclass 4, count 2 2006.173.22:33:02.29#ibcon#about to read 4, iclass 4, count 2 2006.173.22:33:02.29#ibcon#read 4, iclass 4, count 2 2006.173.22:33:02.29#ibcon#about to read 5, iclass 4, count 2 2006.173.22:33:02.29#ibcon#read 5, iclass 4, count 2 2006.173.22:33:02.29#ibcon#about to read 6, iclass 4, count 2 2006.173.22:33:02.29#ibcon#read 6, iclass 4, count 2 2006.173.22:33:02.29#ibcon#end of sib2, iclass 4, count 2 2006.173.22:33:02.29#ibcon#*mode == 0, iclass 4, count 2 2006.173.22:33:02.29#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.22:33:02.29#ibcon#[27=AT08-04\r\n] 2006.173.22:33:02.29#ibcon#*before write, iclass 4, count 2 2006.173.22:33:02.29#ibcon#enter sib2, iclass 4, count 2 2006.173.22:33:02.29#ibcon#flushed, iclass 4, count 2 2006.173.22:33:02.29#ibcon#about to write, iclass 4, count 2 2006.173.22:33:02.29#ibcon#wrote, iclass 4, count 2 2006.173.22:33:02.29#ibcon#about to read 3, iclass 4, count 2 2006.173.22:33:02.32#ibcon#read 3, iclass 4, count 2 2006.173.22:33:02.32#ibcon#about to read 4, iclass 4, count 2 2006.173.22:33:02.32#ibcon#read 4, iclass 4, count 2 2006.173.22:33:02.32#ibcon#about to read 5, iclass 4, count 2 2006.173.22:33:02.32#ibcon#read 5, iclass 4, count 2 2006.173.22:33:02.32#ibcon#about to read 6, iclass 4, count 2 2006.173.22:33:02.32#ibcon#read 6, iclass 4, count 2 2006.173.22:33:02.32#ibcon#end of sib2, iclass 4, count 2 2006.173.22:33:02.32#ibcon#*after write, iclass 4, count 2 2006.173.22:33:02.32#ibcon#*before return 0, iclass 4, count 2 2006.173.22:33:02.32#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.22:33:02.32#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.22:33:02.32#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.22:33:02.32#ibcon#ireg 7 cls_cnt 0 2006.173.22:33:02.32#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.22:33:02.44#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.22:33:02.44#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.22:33:02.44#ibcon#enter wrdev, iclass 4, count 0 2006.173.22:33:02.44#ibcon#first serial, iclass 4, count 0 2006.173.22:33:02.44#ibcon#enter sib2, iclass 4, count 0 2006.173.22:33:02.44#ibcon#flushed, iclass 4, count 0 2006.173.22:33:02.44#ibcon#about to write, iclass 4, count 0 2006.173.22:33:02.44#ibcon#wrote, iclass 4, count 0 2006.173.22:33:02.44#ibcon#about to read 3, iclass 4, count 0 2006.173.22:33:02.46#ibcon#read 3, iclass 4, count 0 2006.173.22:33:02.46#ibcon#about to read 4, iclass 4, count 0 2006.173.22:33:02.46#ibcon#read 4, iclass 4, count 0 2006.173.22:33:02.46#ibcon#about to read 5, iclass 4, count 0 2006.173.22:33:02.46#ibcon#read 5, iclass 4, count 0 2006.173.22:33:02.46#ibcon#about to read 6, iclass 4, count 0 2006.173.22:33:02.46#ibcon#read 6, iclass 4, count 0 2006.173.22:33:02.46#ibcon#end of sib2, iclass 4, count 0 2006.173.22:33:02.46#ibcon#*mode == 0, iclass 4, count 0 2006.173.22:33:02.46#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.22:33:02.46#ibcon#[27=USB\r\n] 2006.173.22:33:02.46#ibcon#*before write, iclass 4, count 0 2006.173.22:33:02.46#ibcon#enter sib2, iclass 4, count 0 2006.173.22:33:02.46#ibcon#flushed, iclass 4, count 0 2006.173.22:33:02.46#ibcon#about to write, iclass 4, count 0 2006.173.22:33:02.46#ibcon#wrote, iclass 4, count 0 2006.173.22:33:02.46#ibcon#about to read 3, iclass 4, count 0 2006.173.22:33:02.49#ibcon#read 3, iclass 4, count 0 2006.173.22:33:02.49#ibcon#about to read 4, iclass 4, count 0 2006.173.22:33:02.49#ibcon#read 4, iclass 4, count 0 2006.173.22:33:02.49#ibcon#about to read 5, iclass 4, count 0 2006.173.22:33:02.49#ibcon#read 5, iclass 4, count 0 2006.173.22:33:02.49#ibcon#about to read 6, iclass 4, count 0 2006.173.22:33:02.49#ibcon#read 6, iclass 4, count 0 2006.173.22:33:02.49#ibcon#end of sib2, iclass 4, count 0 2006.173.22:33:02.49#ibcon#*after write, iclass 4, count 0 2006.173.22:33:02.49#ibcon#*before return 0, iclass 4, count 0 2006.173.22:33:02.49#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.22:33:02.49#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.22:33:02.49#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.22:33:02.49#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.22:33:02.49$vck44/vabw=wide 2006.173.22:33:02.49#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.22:33:02.49#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.22:33:02.49#ibcon#ireg 8 cls_cnt 0 2006.173.22:33:02.49#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.22:33:02.49#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.22:33:02.49#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.22:33:02.49#ibcon#enter wrdev, iclass 6, count 0 2006.173.22:33:02.49#ibcon#first serial, iclass 6, count 0 2006.173.22:33:02.49#ibcon#enter sib2, iclass 6, count 0 2006.173.22:33:02.49#ibcon#flushed, iclass 6, count 0 2006.173.22:33:02.49#ibcon#about to write, iclass 6, count 0 2006.173.22:33:02.49#ibcon#wrote, iclass 6, count 0 2006.173.22:33:02.49#ibcon#about to read 3, iclass 6, count 0 2006.173.22:33:02.51#ibcon#read 3, iclass 6, count 0 2006.173.22:33:02.51#ibcon#about to read 4, iclass 6, count 0 2006.173.22:33:02.51#ibcon#read 4, iclass 6, count 0 2006.173.22:33:02.51#ibcon#about to read 5, iclass 6, count 0 2006.173.22:33:02.51#ibcon#read 5, iclass 6, count 0 2006.173.22:33:02.51#ibcon#about to read 6, iclass 6, count 0 2006.173.22:33:02.51#ibcon#read 6, iclass 6, count 0 2006.173.22:33:02.51#ibcon#end of sib2, iclass 6, count 0 2006.173.22:33:02.51#ibcon#*mode == 0, iclass 6, count 0 2006.173.22:33:02.51#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.22:33:02.51#ibcon#[25=BW32\r\n] 2006.173.22:33:02.51#ibcon#*before write, iclass 6, count 0 2006.173.22:33:02.51#ibcon#enter sib2, iclass 6, count 0 2006.173.22:33:02.51#ibcon#flushed, iclass 6, count 0 2006.173.22:33:02.51#ibcon#about to write, iclass 6, count 0 2006.173.22:33:02.51#ibcon#wrote, iclass 6, count 0 2006.173.22:33:02.51#ibcon#about to read 3, iclass 6, count 0 2006.173.22:33:02.54#ibcon#read 3, iclass 6, count 0 2006.173.22:33:02.54#ibcon#about to read 4, iclass 6, count 0 2006.173.22:33:02.54#ibcon#read 4, iclass 6, count 0 2006.173.22:33:02.54#ibcon#about to read 5, iclass 6, count 0 2006.173.22:33:02.54#ibcon#read 5, iclass 6, count 0 2006.173.22:33:02.54#ibcon#about to read 6, iclass 6, count 0 2006.173.22:33:02.54#ibcon#read 6, iclass 6, count 0 2006.173.22:33:02.54#ibcon#end of sib2, iclass 6, count 0 2006.173.22:33:02.54#ibcon#*after write, iclass 6, count 0 2006.173.22:33:02.54#ibcon#*before return 0, iclass 6, count 0 2006.173.22:33:02.54#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.22:33:02.54#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.22:33:02.54#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.22:33:02.54#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.22:33:02.54$vck44/vbbw=wide 2006.173.22:33:02.54#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.22:33:02.54#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.22:33:02.54#ibcon#ireg 8 cls_cnt 0 2006.173.22:33:02.54#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.22:33:02.61#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.22:33:02.61#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.22:33:02.61#ibcon#enter wrdev, iclass 10, count 0 2006.173.22:33:02.61#ibcon#first serial, iclass 10, count 0 2006.173.22:33:02.61#ibcon#enter sib2, iclass 10, count 0 2006.173.22:33:02.61#ibcon#flushed, iclass 10, count 0 2006.173.22:33:02.61#ibcon#about to write, iclass 10, count 0 2006.173.22:33:02.61#ibcon#wrote, iclass 10, count 0 2006.173.22:33:02.61#ibcon#about to read 3, iclass 10, count 0 2006.173.22:33:02.63#ibcon#read 3, iclass 10, count 0 2006.173.22:33:02.63#ibcon#about to read 4, iclass 10, count 0 2006.173.22:33:02.63#ibcon#read 4, iclass 10, count 0 2006.173.22:33:02.63#ibcon#about to read 5, iclass 10, count 0 2006.173.22:33:02.63#ibcon#read 5, iclass 10, count 0 2006.173.22:33:02.63#ibcon#about to read 6, iclass 10, count 0 2006.173.22:33:02.63#ibcon#read 6, iclass 10, count 0 2006.173.22:33:02.63#ibcon#end of sib2, iclass 10, count 0 2006.173.22:33:02.63#ibcon#*mode == 0, iclass 10, count 0 2006.173.22:33:02.63#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.22:33:02.63#ibcon#[27=BW32\r\n] 2006.173.22:33:02.63#ibcon#*before write, iclass 10, count 0 2006.173.22:33:02.63#ibcon#enter sib2, iclass 10, count 0 2006.173.22:33:02.63#ibcon#flushed, iclass 10, count 0 2006.173.22:33:02.63#ibcon#about to write, iclass 10, count 0 2006.173.22:33:02.63#ibcon#wrote, iclass 10, count 0 2006.173.22:33:02.63#ibcon#about to read 3, iclass 10, count 0 2006.173.22:33:02.66#ibcon#read 3, iclass 10, count 0 2006.173.22:33:02.66#ibcon#about to read 4, iclass 10, count 0 2006.173.22:33:02.66#ibcon#read 4, iclass 10, count 0 2006.173.22:33:02.66#ibcon#about to read 5, iclass 10, count 0 2006.173.22:33:02.66#ibcon#read 5, iclass 10, count 0 2006.173.22:33:02.66#ibcon#about to read 6, iclass 10, count 0 2006.173.22:33:02.66#ibcon#read 6, iclass 10, count 0 2006.173.22:33:02.66#ibcon#end of sib2, iclass 10, count 0 2006.173.22:33:02.66#ibcon#*after write, iclass 10, count 0 2006.173.22:33:02.66#ibcon#*before return 0, iclass 10, count 0 2006.173.22:33:02.66#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.22:33:02.66#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.22:33:02.66#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.22:33:02.66#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.22:33:02.66$setupk4/ifdk4 2006.173.22:33:02.66$ifdk4/lo= 2006.173.22:33:02.66$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.22:33:02.66$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.22:33:02.66$ifdk4/patch= 2006.173.22:33:02.66$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.22:33:02.66$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.22:33:02.66$setupk4/!*+20s 2006.173.22:33:03.55#abcon#<5=/12 0.5 1.3 22.38 901003.3\r\n> 2006.173.22:33:03.57#abcon#{5=INTERFACE CLEAR} 2006.173.22:33:03.63#abcon#[5=S1D000X0/0*\r\n] 2006.173.22:33:13.72#abcon#<5=/12 0.6 1.3 22.38 901003.3\r\n> 2006.173.22:33:13.74#abcon#{5=INTERFACE CLEAR} 2006.173.22:33:13.80#abcon#[5=S1D000X0/0*\r\n] 2006.173.22:33:17.17$setupk4/"tpicd 2006.173.22:33:17.17$setupk4/echo=off 2006.173.22:33:17.17$setupk4/xlog=off 2006.173.22:33:17.17:!2006.173.22:37:12 2006.173.22:33:30.13#trakl#Source acquired 2006.173.22:33:32.14#flagr#flagr/antenna,acquired 2006.173.22:37:12.00:preob 2006.173.22:37:12.14/onsource/TRACKING 2006.173.22:37:12.14:!2006.173.22:37:22 2006.173.22:37:22.00:"tape 2006.173.22:37:22.00:"st=record 2006.173.22:37:22.00:data_valid=on 2006.173.22:37:22.00:midob 2006.173.22:37:23.14/onsource/TRACKING 2006.173.22:37:23.14/wx/22.42,1003.3,93 2006.173.22:37:23.21/cable/+6.5125E-03 2006.173.22:37:24.30/va/01,07,usb,yes,34,37 2006.173.22:37:24.30/va/02,06,usb,yes,34,35 2006.173.22:37:24.30/va/03,05,usb,yes,43,45 2006.173.22:37:24.30/va/04,06,usb,yes,35,37 2006.173.22:37:24.30/va/05,04,usb,yes,27,28 2006.173.22:37:24.30/va/06,03,usb,yes,38,38 2006.173.22:37:24.30/va/07,04,usb,yes,31,32 2006.173.22:37:24.30/va/08,04,usb,yes,26,32 2006.173.22:37:24.53/valo/01,524.99,yes,locked 2006.173.22:37:24.53/valo/02,534.99,yes,locked 2006.173.22:37:24.53/valo/03,564.99,yes,locked 2006.173.22:37:24.53/valo/04,624.99,yes,locked 2006.173.22:37:24.53/valo/05,734.99,yes,locked 2006.173.22:37:24.53/valo/06,814.99,yes,locked 2006.173.22:37:24.53/valo/07,864.99,yes,locked 2006.173.22:37:24.53/valo/08,884.99,yes,locked 2006.173.22:37:25.62/vb/01,04,usb,yes,29,27 2006.173.22:37:25.62/vb/02,04,usb,yes,31,31 2006.173.22:37:25.62/vb/03,04,usb,yes,28,31 2006.173.22:37:25.62/vb/04,04,usb,yes,33,31 2006.173.22:37:25.62/vb/05,04,usb,yes,25,28 2006.173.22:37:25.62/vb/06,04,usb,yes,30,26 2006.173.22:37:25.62/vb/07,04,usb,yes,29,29 2006.173.22:37:25.62/vb/08,04,usb,yes,27,30 2006.173.22:37:25.85/vblo/01,629.99,yes,locked 2006.173.22:37:25.85/vblo/02,634.99,yes,locked 2006.173.22:37:25.85/vblo/03,649.99,yes,locked 2006.173.22:37:25.85/vblo/04,679.99,yes,locked 2006.173.22:37:25.85/vblo/05,709.99,yes,locked 2006.173.22:37:25.85/vblo/06,719.99,yes,locked 2006.173.22:37:25.85/vblo/07,734.99,yes,locked 2006.173.22:37:25.85/vblo/08,744.99,yes,locked 2006.173.22:37:26.00/vabw/8 2006.173.22:37:26.15/vbbw/8 2006.173.22:37:26.30/xfe/off,on,14.2 2006.173.22:37:26.69/ifatt/23,28,28,28 2006.173.22:37:27.07/fmout-gps/S +3.81E-07 2006.173.22:37:27.11:!2006.173.22:41:12 2006.173.22:41:12.01:data_valid=off 2006.173.22:41:12.01:"et 2006.173.22:41:12.01:!+3s 2006.173.22:41:15.02:"tape 2006.173.22:41:15.02:postob 2006.173.22:41:15.21/cable/+6.5136E-03 2006.173.22:41:15.21/wx/22.41,1003.3,89 2006.173.22:41:15.27/fmout-gps/S +3.84E-07 2006.173.22:41:15.27:scan_name=173-2251,jd0606,130 2006.173.22:41:15.27:source=2201+315,220314.98,314538.3,2000.0,ccw 2006.173.22:41:16.14#flagr#flagr/antenna,new-source 2006.173.22:41:16.14:checkk5 2006.173.22:41:16.56/chk_autoobs//k5ts1/ autoobs is running! 2006.173.22:41:16.95/chk_autoobs//k5ts2/ autoobs is running! 2006.173.22:41:17.36/chk_autoobs//k5ts3/ autoobs is running! 2006.173.22:41:17.75/chk_autoobs//k5ts4/ autoobs is running! 2006.173.22:41:18.14/chk_obsdata//k5ts1/T1732237??a.dat file size is correct (nominal:920MB, actual:916MB). 2006.173.22:41:18.54/chk_obsdata//k5ts2/T1732237??b.dat file size is correct (nominal:920MB, actual:916MB). 2006.173.22:41:18.94/chk_obsdata//k5ts3/T1732237??c.dat file size is correct (nominal:920MB, actual:916MB). 2006.173.22:41:19.34/chk_obsdata//k5ts4/T1732237??d.dat file size is correct (nominal:920MB, actual:916MB). 2006.173.22:41:20.05/k5log//k5ts1_log_newline 2006.173.22:41:20.76/k5log//k5ts2_log_newline 2006.173.22:41:21.49/k5log//k5ts3_log_newline 2006.173.22:41:22.20/k5log//k5ts4_log_newline 2006.173.22:41:22.23/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.22:41:22.23:setupk4=1 2006.173.22:41:22.23$setupk4/echo=on 2006.173.22:41:22.23$setupk4/pcalon 2006.173.22:41:22.23$pcalon/"no phase cal control is implemented here 2006.173.22:41:22.23$setupk4/"tpicd=stop 2006.173.22:41:22.23$setupk4/"rec=synch_on 2006.173.22:41:22.23$setupk4/"rec_mode=128 2006.173.22:41:22.23$setupk4/!* 2006.173.22:41:22.23$setupk4/recpk4 2006.173.22:41:22.23$recpk4/recpatch= 2006.173.22:41:22.23$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.22:41:22.23$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.22:41:22.23$setupk4/vck44 2006.173.22:41:22.23$vck44/valo=1,524.99 2006.173.22:41:22.23#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.22:41:22.23#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.22:41:22.23#ibcon#ireg 17 cls_cnt 0 2006.173.22:41:22.23#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.22:41:22.23#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.22:41:22.23#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.22:41:22.23#ibcon#enter wrdev, iclass 35, count 0 2006.173.22:41:22.23#ibcon#first serial, iclass 35, count 0 2006.173.22:41:22.23#ibcon#enter sib2, iclass 35, count 0 2006.173.22:41:22.23#ibcon#flushed, iclass 35, count 0 2006.173.22:41:22.23#ibcon#about to write, iclass 35, count 0 2006.173.22:41:22.23#ibcon#wrote, iclass 35, count 0 2006.173.22:41:22.23#ibcon#about to read 3, iclass 35, count 0 2006.173.22:41:22.25#ibcon#read 3, iclass 35, count 0 2006.173.22:41:22.25#ibcon#about to read 4, iclass 35, count 0 2006.173.22:41:22.25#ibcon#read 4, iclass 35, count 0 2006.173.22:41:22.25#ibcon#about to read 5, iclass 35, count 0 2006.173.22:41:22.25#ibcon#read 5, iclass 35, count 0 2006.173.22:41:22.25#ibcon#about to read 6, iclass 35, count 0 2006.173.22:41:22.25#ibcon#read 6, iclass 35, count 0 2006.173.22:41:22.25#ibcon#end of sib2, iclass 35, count 0 2006.173.22:41:22.25#ibcon#*mode == 0, iclass 35, count 0 2006.173.22:41:22.25#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.22:41:22.25#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.22:41:22.25#ibcon#*before write, iclass 35, count 0 2006.173.22:41:22.25#ibcon#enter sib2, iclass 35, count 0 2006.173.22:41:22.25#ibcon#flushed, iclass 35, count 0 2006.173.22:41:22.25#ibcon#about to write, iclass 35, count 0 2006.173.22:41:22.25#ibcon#wrote, iclass 35, count 0 2006.173.22:41:22.25#ibcon#about to read 3, iclass 35, count 0 2006.173.22:41:22.30#ibcon#read 3, iclass 35, count 0 2006.173.22:41:22.30#ibcon#about to read 4, iclass 35, count 0 2006.173.22:41:22.30#ibcon#read 4, iclass 35, count 0 2006.173.22:41:22.30#ibcon#about to read 5, iclass 35, count 0 2006.173.22:41:22.30#ibcon#read 5, iclass 35, count 0 2006.173.22:41:22.30#ibcon#about to read 6, iclass 35, count 0 2006.173.22:41:22.30#ibcon#read 6, iclass 35, count 0 2006.173.22:41:22.30#ibcon#end of sib2, iclass 35, count 0 2006.173.22:41:22.30#ibcon#*after write, iclass 35, count 0 2006.173.22:41:22.30#ibcon#*before return 0, iclass 35, count 0 2006.173.22:41:22.30#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.22:41:22.30#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.22:41:22.30#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.22:41:22.30#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.22:41:22.30$vck44/va=1,7 2006.173.22:41:22.30#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.173.22:41:22.30#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.173.22:41:22.30#ibcon#ireg 11 cls_cnt 2 2006.173.22:41:22.30#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.22:41:22.30#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.22:41:22.30#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.22:41:22.30#ibcon#enter wrdev, iclass 37, count 2 2006.173.22:41:22.30#ibcon#first serial, iclass 37, count 2 2006.173.22:41:22.30#ibcon#enter sib2, iclass 37, count 2 2006.173.22:41:22.30#ibcon#flushed, iclass 37, count 2 2006.173.22:41:22.30#ibcon#about to write, iclass 37, count 2 2006.173.22:41:22.30#ibcon#wrote, iclass 37, count 2 2006.173.22:41:22.30#ibcon#about to read 3, iclass 37, count 2 2006.173.22:41:22.32#ibcon#read 3, iclass 37, count 2 2006.173.22:41:22.32#ibcon#about to read 4, iclass 37, count 2 2006.173.22:41:22.32#ibcon#read 4, iclass 37, count 2 2006.173.22:41:22.32#ibcon#about to read 5, iclass 37, count 2 2006.173.22:41:22.32#ibcon#read 5, iclass 37, count 2 2006.173.22:41:22.32#ibcon#about to read 6, iclass 37, count 2 2006.173.22:41:22.32#ibcon#read 6, iclass 37, count 2 2006.173.22:41:22.32#ibcon#end of sib2, iclass 37, count 2 2006.173.22:41:22.32#ibcon#*mode == 0, iclass 37, count 2 2006.173.22:41:22.32#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.173.22:41:22.32#ibcon#[25=AT01-07\r\n] 2006.173.22:41:22.32#ibcon#*before write, iclass 37, count 2 2006.173.22:41:22.32#ibcon#enter sib2, iclass 37, count 2 2006.173.22:41:22.32#ibcon#flushed, iclass 37, count 2 2006.173.22:41:22.32#ibcon#about to write, iclass 37, count 2 2006.173.22:41:22.32#ibcon#wrote, iclass 37, count 2 2006.173.22:41:22.32#ibcon#about to read 3, iclass 37, count 2 2006.173.22:41:22.35#ibcon#read 3, iclass 37, count 2 2006.173.22:41:22.35#ibcon#about to read 4, iclass 37, count 2 2006.173.22:41:22.35#ibcon#read 4, iclass 37, count 2 2006.173.22:41:22.35#ibcon#about to read 5, iclass 37, count 2 2006.173.22:41:22.35#ibcon#read 5, iclass 37, count 2 2006.173.22:41:22.35#ibcon#about to read 6, iclass 37, count 2 2006.173.22:41:22.35#ibcon#read 6, iclass 37, count 2 2006.173.22:41:22.35#ibcon#end of sib2, iclass 37, count 2 2006.173.22:41:22.35#ibcon#*after write, iclass 37, count 2 2006.173.22:41:22.35#ibcon#*before return 0, iclass 37, count 2 2006.173.22:41:22.35#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.22:41:22.35#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.173.22:41:22.35#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.173.22:41:22.35#ibcon#ireg 7 cls_cnt 0 2006.173.22:41:22.35#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.22:41:22.47#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.22:41:22.47#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.22:41:22.47#ibcon#enter wrdev, iclass 37, count 0 2006.173.22:41:22.47#ibcon#first serial, iclass 37, count 0 2006.173.22:41:22.47#ibcon#enter sib2, iclass 37, count 0 2006.173.22:41:22.47#ibcon#flushed, iclass 37, count 0 2006.173.22:41:22.47#ibcon#about to write, iclass 37, count 0 2006.173.22:41:22.47#ibcon#wrote, iclass 37, count 0 2006.173.22:41:22.47#ibcon#about to read 3, iclass 37, count 0 2006.173.22:41:22.49#ibcon#read 3, iclass 37, count 0 2006.173.22:41:22.49#ibcon#about to read 4, iclass 37, count 0 2006.173.22:41:22.49#ibcon#read 4, iclass 37, count 0 2006.173.22:41:22.49#ibcon#about to read 5, iclass 37, count 0 2006.173.22:41:22.49#ibcon#read 5, iclass 37, count 0 2006.173.22:41:22.49#ibcon#about to read 6, iclass 37, count 0 2006.173.22:41:22.49#ibcon#read 6, iclass 37, count 0 2006.173.22:41:22.49#ibcon#end of sib2, iclass 37, count 0 2006.173.22:41:22.49#ibcon#*mode == 0, iclass 37, count 0 2006.173.22:41:22.49#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.22:41:22.49#ibcon#[25=USB\r\n] 2006.173.22:41:22.49#ibcon#*before write, iclass 37, count 0 2006.173.22:41:22.49#ibcon#enter sib2, iclass 37, count 0 2006.173.22:41:22.49#ibcon#flushed, iclass 37, count 0 2006.173.22:41:22.49#ibcon#about to write, iclass 37, count 0 2006.173.22:41:22.49#ibcon#wrote, iclass 37, count 0 2006.173.22:41:22.49#ibcon#about to read 3, iclass 37, count 0 2006.173.22:41:22.52#ibcon#read 3, iclass 37, count 0 2006.173.22:41:22.52#ibcon#about to read 4, iclass 37, count 0 2006.173.22:41:22.52#ibcon#read 4, iclass 37, count 0 2006.173.22:41:22.52#ibcon#about to read 5, iclass 37, count 0 2006.173.22:41:22.52#ibcon#read 5, iclass 37, count 0 2006.173.22:41:22.52#ibcon#about to read 6, iclass 37, count 0 2006.173.22:41:22.52#ibcon#read 6, iclass 37, count 0 2006.173.22:41:22.52#ibcon#end of sib2, iclass 37, count 0 2006.173.22:41:22.52#ibcon#*after write, iclass 37, count 0 2006.173.22:41:22.52#ibcon#*before return 0, iclass 37, count 0 2006.173.22:41:22.52#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.22:41:22.52#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.173.22:41:22.52#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.22:41:22.52#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.22:41:22.52$vck44/valo=2,534.99 2006.173.22:41:22.52#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.22:41:22.52#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.22:41:22.52#ibcon#ireg 17 cls_cnt 0 2006.173.22:41:22.52#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.22:41:22.52#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.22:41:22.52#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.22:41:22.52#ibcon#enter wrdev, iclass 39, count 0 2006.173.22:41:22.52#ibcon#first serial, iclass 39, count 0 2006.173.22:41:22.52#ibcon#enter sib2, iclass 39, count 0 2006.173.22:41:22.52#ibcon#flushed, iclass 39, count 0 2006.173.22:41:22.52#ibcon#about to write, iclass 39, count 0 2006.173.22:41:22.52#ibcon#wrote, iclass 39, count 0 2006.173.22:41:22.52#ibcon#about to read 3, iclass 39, count 0 2006.173.22:41:22.54#ibcon#read 3, iclass 39, count 0 2006.173.22:41:22.54#ibcon#about to read 4, iclass 39, count 0 2006.173.22:41:22.54#ibcon#read 4, iclass 39, count 0 2006.173.22:41:22.54#ibcon#about to read 5, iclass 39, count 0 2006.173.22:41:22.54#ibcon#read 5, iclass 39, count 0 2006.173.22:41:22.54#ibcon#about to read 6, iclass 39, count 0 2006.173.22:41:22.54#ibcon#read 6, iclass 39, count 0 2006.173.22:41:22.54#ibcon#end of sib2, iclass 39, count 0 2006.173.22:41:22.54#ibcon#*mode == 0, iclass 39, count 0 2006.173.22:41:22.54#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.22:41:22.54#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.22:41:22.54#ibcon#*before write, iclass 39, count 0 2006.173.22:41:22.54#ibcon#enter sib2, iclass 39, count 0 2006.173.22:41:22.54#ibcon#flushed, iclass 39, count 0 2006.173.22:41:22.54#ibcon#about to write, iclass 39, count 0 2006.173.22:41:22.54#ibcon#wrote, iclass 39, count 0 2006.173.22:41:22.54#ibcon#about to read 3, iclass 39, count 0 2006.173.22:41:22.58#ibcon#read 3, iclass 39, count 0 2006.173.22:41:22.58#ibcon#about to read 4, iclass 39, count 0 2006.173.22:41:22.58#ibcon#read 4, iclass 39, count 0 2006.173.22:41:22.58#ibcon#about to read 5, iclass 39, count 0 2006.173.22:41:22.58#ibcon#read 5, iclass 39, count 0 2006.173.22:41:22.58#ibcon#about to read 6, iclass 39, count 0 2006.173.22:41:22.58#ibcon#read 6, iclass 39, count 0 2006.173.22:41:22.58#ibcon#end of sib2, iclass 39, count 0 2006.173.22:41:22.58#ibcon#*after write, iclass 39, count 0 2006.173.22:41:22.58#ibcon#*before return 0, iclass 39, count 0 2006.173.22:41:22.58#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.22:41:22.58#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.22:41:22.58#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.22:41:22.58#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.22:41:22.58$vck44/va=2,6 2006.173.22:41:22.58#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.22:41:22.58#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.22:41:22.58#ibcon#ireg 11 cls_cnt 2 2006.173.22:41:22.58#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.22:41:22.64#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.22:41:22.64#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.22:41:22.64#ibcon#enter wrdev, iclass 3, count 2 2006.173.22:41:22.64#ibcon#first serial, iclass 3, count 2 2006.173.22:41:22.64#ibcon#enter sib2, iclass 3, count 2 2006.173.22:41:22.64#ibcon#flushed, iclass 3, count 2 2006.173.22:41:22.64#ibcon#about to write, iclass 3, count 2 2006.173.22:41:22.64#ibcon#wrote, iclass 3, count 2 2006.173.22:41:22.64#ibcon#about to read 3, iclass 3, count 2 2006.173.22:41:22.66#ibcon#read 3, iclass 3, count 2 2006.173.22:41:22.66#ibcon#about to read 4, iclass 3, count 2 2006.173.22:41:22.66#ibcon#read 4, iclass 3, count 2 2006.173.22:41:22.66#ibcon#about to read 5, iclass 3, count 2 2006.173.22:41:22.66#ibcon#read 5, iclass 3, count 2 2006.173.22:41:22.66#ibcon#about to read 6, iclass 3, count 2 2006.173.22:41:22.66#ibcon#read 6, iclass 3, count 2 2006.173.22:41:22.66#ibcon#end of sib2, iclass 3, count 2 2006.173.22:41:22.66#ibcon#*mode == 0, iclass 3, count 2 2006.173.22:41:22.66#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.22:41:22.66#ibcon#[25=AT02-06\r\n] 2006.173.22:41:22.66#ibcon#*before write, iclass 3, count 2 2006.173.22:41:22.66#ibcon#enter sib2, iclass 3, count 2 2006.173.22:41:22.66#ibcon#flushed, iclass 3, count 2 2006.173.22:41:22.66#ibcon#about to write, iclass 3, count 2 2006.173.22:41:22.66#ibcon#wrote, iclass 3, count 2 2006.173.22:41:22.66#ibcon#about to read 3, iclass 3, count 2 2006.173.22:41:22.69#ibcon#read 3, iclass 3, count 2 2006.173.22:41:22.69#ibcon#about to read 4, iclass 3, count 2 2006.173.22:41:22.69#ibcon#read 4, iclass 3, count 2 2006.173.22:41:22.69#ibcon#about to read 5, iclass 3, count 2 2006.173.22:41:22.69#ibcon#read 5, iclass 3, count 2 2006.173.22:41:22.69#ibcon#about to read 6, iclass 3, count 2 2006.173.22:41:22.69#ibcon#read 6, iclass 3, count 2 2006.173.22:41:22.69#ibcon#end of sib2, iclass 3, count 2 2006.173.22:41:22.69#ibcon#*after write, iclass 3, count 2 2006.173.22:41:22.69#ibcon#*before return 0, iclass 3, count 2 2006.173.22:41:22.69#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.22:41:22.69#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.22:41:22.69#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.22:41:22.69#ibcon#ireg 7 cls_cnt 0 2006.173.22:41:22.69#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.22:41:22.81#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.22:41:22.81#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.22:41:22.81#ibcon#enter wrdev, iclass 3, count 0 2006.173.22:41:22.81#ibcon#first serial, iclass 3, count 0 2006.173.22:41:22.81#ibcon#enter sib2, iclass 3, count 0 2006.173.22:41:22.81#ibcon#flushed, iclass 3, count 0 2006.173.22:41:22.81#ibcon#about to write, iclass 3, count 0 2006.173.22:41:22.81#ibcon#wrote, iclass 3, count 0 2006.173.22:41:22.81#ibcon#about to read 3, iclass 3, count 0 2006.173.22:41:22.83#ibcon#read 3, iclass 3, count 0 2006.173.22:41:22.83#ibcon#about to read 4, iclass 3, count 0 2006.173.22:41:22.83#ibcon#read 4, iclass 3, count 0 2006.173.22:41:22.83#ibcon#about to read 5, iclass 3, count 0 2006.173.22:41:22.83#ibcon#read 5, iclass 3, count 0 2006.173.22:41:22.83#ibcon#about to read 6, iclass 3, count 0 2006.173.22:41:22.83#ibcon#read 6, iclass 3, count 0 2006.173.22:41:22.83#ibcon#end of sib2, iclass 3, count 0 2006.173.22:41:22.83#ibcon#*mode == 0, iclass 3, count 0 2006.173.22:41:22.83#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.22:41:22.83#ibcon#[25=USB\r\n] 2006.173.22:41:22.83#ibcon#*before write, iclass 3, count 0 2006.173.22:41:22.83#ibcon#enter sib2, iclass 3, count 0 2006.173.22:41:22.83#ibcon#flushed, iclass 3, count 0 2006.173.22:41:22.83#ibcon#about to write, iclass 3, count 0 2006.173.22:41:22.83#ibcon#wrote, iclass 3, count 0 2006.173.22:41:22.83#ibcon#about to read 3, iclass 3, count 0 2006.173.22:41:22.86#ibcon#read 3, iclass 3, count 0 2006.173.22:41:22.86#ibcon#about to read 4, iclass 3, count 0 2006.173.22:41:22.86#ibcon#read 4, iclass 3, count 0 2006.173.22:41:22.86#ibcon#about to read 5, iclass 3, count 0 2006.173.22:41:22.86#ibcon#read 5, iclass 3, count 0 2006.173.22:41:22.86#ibcon#about to read 6, iclass 3, count 0 2006.173.22:41:22.86#ibcon#read 6, iclass 3, count 0 2006.173.22:41:22.86#ibcon#end of sib2, iclass 3, count 0 2006.173.22:41:22.86#ibcon#*after write, iclass 3, count 0 2006.173.22:41:22.86#ibcon#*before return 0, iclass 3, count 0 2006.173.22:41:22.86#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.22:41:22.86#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.22:41:22.86#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.22:41:22.86#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.22:41:22.86$vck44/valo=3,564.99 2006.173.22:41:22.86#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.22:41:22.86#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.22:41:22.86#ibcon#ireg 17 cls_cnt 0 2006.173.22:41:22.86#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.22:41:22.86#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.22:41:22.86#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.22:41:22.86#ibcon#enter wrdev, iclass 5, count 0 2006.173.22:41:22.86#ibcon#first serial, iclass 5, count 0 2006.173.22:41:22.86#ibcon#enter sib2, iclass 5, count 0 2006.173.22:41:22.86#ibcon#flushed, iclass 5, count 0 2006.173.22:41:22.86#ibcon#about to write, iclass 5, count 0 2006.173.22:41:22.86#ibcon#wrote, iclass 5, count 0 2006.173.22:41:22.86#ibcon#about to read 3, iclass 5, count 0 2006.173.22:41:22.88#ibcon#read 3, iclass 5, count 0 2006.173.22:41:22.88#ibcon#about to read 4, iclass 5, count 0 2006.173.22:41:22.88#ibcon#read 4, iclass 5, count 0 2006.173.22:41:22.88#ibcon#about to read 5, iclass 5, count 0 2006.173.22:41:22.88#ibcon#read 5, iclass 5, count 0 2006.173.22:41:22.88#ibcon#about to read 6, iclass 5, count 0 2006.173.22:41:22.88#ibcon#read 6, iclass 5, count 0 2006.173.22:41:22.88#ibcon#end of sib2, iclass 5, count 0 2006.173.22:41:22.88#ibcon#*mode == 0, iclass 5, count 0 2006.173.22:41:22.88#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.22:41:22.88#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.22:41:22.88#ibcon#*before write, iclass 5, count 0 2006.173.22:41:22.88#ibcon#enter sib2, iclass 5, count 0 2006.173.22:41:22.88#ibcon#flushed, iclass 5, count 0 2006.173.22:41:22.88#ibcon#about to write, iclass 5, count 0 2006.173.22:41:22.88#ibcon#wrote, iclass 5, count 0 2006.173.22:41:22.88#ibcon#about to read 3, iclass 5, count 0 2006.173.22:41:22.92#ibcon#read 3, iclass 5, count 0 2006.173.22:41:22.92#ibcon#about to read 4, iclass 5, count 0 2006.173.22:41:22.92#ibcon#read 4, iclass 5, count 0 2006.173.22:41:22.92#ibcon#about to read 5, iclass 5, count 0 2006.173.22:41:22.92#ibcon#read 5, iclass 5, count 0 2006.173.22:41:22.92#ibcon#about to read 6, iclass 5, count 0 2006.173.22:41:22.92#ibcon#read 6, iclass 5, count 0 2006.173.22:41:22.92#ibcon#end of sib2, iclass 5, count 0 2006.173.22:41:22.92#ibcon#*after write, iclass 5, count 0 2006.173.22:41:22.92#ibcon#*before return 0, iclass 5, count 0 2006.173.22:41:22.92#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.22:41:22.92#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.22:41:22.92#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.22:41:22.92#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.22:41:22.92$vck44/va=3,5 2006.173.22:41:22.92#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.173.22:41:22.92#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.173.22:41:22.92#ibcon#ireg 11 cls_cnt 2 2006.173.22:41:22.92#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.22:41:22.98#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.22:41:22.98#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.22:41:22.98#ibcon#enter wrdev, iclass 7, count 2 2006.173.22:41:22.98#ibcon#first serial, iclass 7, count 2 2006.173.22:41:22.98#ibcon#enter sib2, iclass 7, count 2 2006.173.22:41:22.98#ibcon#flushed, iclass 7, count 2 2006.173.22:41:22.98#ibcon#about to write, iclass 7, count 2 2006.173.22:41:22.98#ibcon#wrote, iclass 7, count 2 2006.173.22:41:22.98#ibcon#about to read 3, iclass 7, count 2 2006.173.22:41:23.00#ibcon#read 3, iclass 7, count 2 2006.173.22:41:23.00#ibcon#about to read 4, iclass 7, count 2 2006.173.22:41:23.00#ibcon#read 4, iclass 7, count 2 2006.173.22:41:23.00#ibcon#about to read 5, iclass 7, count 2 2006.173.22:41:23.00#ibcon#read 5, iclass 7, count 2 2006.173.22:41:23.00#ibcon#about to read 6, iclass 7, count 2 2006.173.22:41:23.00#ibcon#read 6, iclass 7, count 2 2006.173.22:41:23.00#ibcon#end of sib2, iclass 7, count 2 2006.173.22:41:23.00#ibcon#*mode == 0, iclass 7, count 2 2006.173.22:41:23.00#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.173.22:41:23.00#ibcon#[25=AT03-05\r\n] 2006.173.22:41:23.00#ibcon#*before write, iclass 7, count 2 2006.173.22:41:23.00#ibcon#enter sib2, iclass 7, count 2 2006.173.22:41:23.00#ibcon#flushed, iclass 7, count 2 2006.173.22:41:23.00#ibcon#about to write, iclass 7, count 2 2006.173.22:41:23.00#ibcon#wrote, iclass 7, count 2 2006.173.22:41:23.00#ibcon#about to read 3, iclass 7, count 2 2006.173.22:41:23.03#ibcon#read 3, iclass 7, count 2 2006.173.22:41:23.03#ibcon#about to read 4, iclass 7, count 2 2006.173.22:41:23.03#ibcon#read 4, iclass 7, count 2 2006.173.22:41:23.03#ibcon#about to read 5, iclass 7, count 2 2006.173.22:41:23.03#ibcon#read 5, iclass 7, count 2 2006.173.22:41:23.03#ibcon#about to read 6, iclass 7, count 2 2006.173.22:41:23.03#ibcon#read 6, iclass 7, count 2 2006.173.22:41:23.03#ibcon#end of sib2, iclass 7, count 2 2006.173.22:41:23.03#ibcon#*after write, iclass 7, count 2 2006.173.22:41:23.03#ibcon#*before return 0, iclass 7, count 2 2006.173.22:41:23.03#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.22:41:23.03#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.173.22:41:23.03#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.173.22:41:23.03#ibcon#ireg 7 cls_cnt 0 2006.173.22:41:23.03#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.22:41:23.15#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.22:41:23.15#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.22:41:23.15#ibcon#enter wrdev, iclass 7, count 0 2006.173.22:41:23.15#ibcon#first serial, iclass 7, count 0 2006.173.22:41:23.15#ibcon#enter sib2, iclass 7, count 0 2006.173.22:41:23.15#ibcon#flushed, iclass 7, count 0 2006.173.22:41:23.15#ibcon#about to write, iclass 7, count 0 2006.173.22:41:23.15#ibcon#wrote, iclass 7, count 0 2006.173.22:41:23.15#ibcon#about to read 3, iclass 7, count 0 2006.173.22:41:23.17#ibcon#read 3, iclass 7, count 0 2006.173.22:41:23.17#ibcon#about to read 4, iclass 7, count 0 2006.173.22:41:23.17#ibcon#read 4, iclass 7, count 0 2006.173.22:41:23.17#ibcon#about to read 5, iclass 7, count 0 2006.173.22:41:23.17#ibcon#read 5, iclass 7, count 0 2006.173.22:41:23.17#ibcon#about to read 6, iclass 7, count 0 2006.173.22:41:23.17#ibcon#read 6, iclass 7, count 0 2006.173.22:41:23.17#ibcon#end of sib2, iclass 7, count 0 2006.173.22:41:23.17#ibcon#*mode == 0, iclass 7, count 0 2006.173.22:41:23.17#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.22:41:23.17#ibcon#[25=USB\r\n] 2006.173.22:41:23.17#ibcon#*before write, iclass 7, count 0 2006.173.22:41:23.17#ibcon#enter sib2, iclass 7, count 0 2006.173.22:41:23.17#ibcon#flushed, iclass 7, count 0 2006.173.22:41:23.17#ibcon#about to write, iclass 7, count 0 2006.173.22:41:23.17#ibcon#wrote, iclass 7, count 0 2006.173.22:41:23.17#ibcon#about to read 3, iclass 7, count 0 2006.173.22:41:23.20#ibcon#read 3, iclass 7, count 0 2006.173.22:41:23.20#ibcon#about to read 4, iclass 7, count 0 2006.173.22:41:23.20#ibcon#read 4, iclass 7, count 0 2006.173.22:41:23.20#ibcon#about to read 5, iclass 7, count 0 2006.173.22:41:23.20#ibcon#read 5, iclass 7, count 0 2006.173.22:41:23.20#ibcon#about to read 6, iclass 7, count 0 2006.173.22:41:23.20#ibcon#read 6, iclass 7, count 0 2006.173.22:41:23.20#ibcon#end of sib2, iclass 7, count 0 2006.173.22:41:23.20#ibcon#*after write, iclass 7, count 0 2006.173.22:41:23.20#ibcon#*before return 0, iclass 7, count 0 2006.173.22:41:23.20#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.22:41:23.20#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.173.22:41:23.20#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.22:41:23.20#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.22:41:23.20$vck44/valo=4,624.99 2006.173.22:41:23.20#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.22:41:23.20#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.22:41:23.20#ibcon#ireg 17 cls_cnt 0 2006.173.22:41:23.20#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.22:41:23.20#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.22:41:23.20#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.22:41:23.20#ibcon#enter wrdev, iclass 11, count 0 2006.173.22:41:23.20#ibcon#first serial, iclass 11, count 0 2006.173.22:41:23.20#ibcon#enter sib2, iclass 11, count 0 2006.173.22:41:23.20#ibcon#flushed, iclass 11, count 0 2006.173.22:41:23.20#ibcon#about to write, iclass 11, count 0 2006.173.22:41:23.20#ibcon#wrote, iclass 11, count 0 2006.173.22:41:23.20#ibcon#about to read 3, iclass 11, count 0 2006.173.22:41:23.22#ibcon#read 3, iclass 11, count 0 2006.173.22:41:23.22#ibcon#about to read 4, iclass 11, count 0 2006.173.22:41:23.22#ibcon#read 4, iclass 11, count 0 2006.173.22:41:23.22#ibcon#about to read 5, iclass 11, count 0 2006.173.22:41:23.22#ibcon#read 5, iclass 11, count 0 2006.173.22:41:23.22#ibcon#about to read 6, iclass 11, count 0 2006.173.22:41:23.22#ibcon#read 6, iclass 11, count 0 2006.173.22:41:23.22#ibcon#end of sib2, iclass 11, count 0 2006.173.22:41:23.22#ibcon#*mode == 0, iclass 11, count 0 2006.173.22:41:23.22#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.22:41:23.22#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.22:41:23.22#ibcon#*before write, iclass 11, count 0 2006.173.22:41:23.22#ibcon#enter sib2, iclass 11, count 0 2006.173.22:41:23.22#ibcon#flushed, iclass 11, count 0 2006.173.22:41:23.22#ibcon#about to write, iclass 11, count 0 2006.173.22:41:23.22#ibcon#wrote, iclass 11, count 0 2006.173.22:41:23.22#ibcon#about to read 3, iclass 11, count 0 2006.173.22:41:23.26#ibcon#read 3, iclass 11, count 0 2006.173.22:41:23.26#ibcon#about to read 4, iclass 11, count 0 2006.173.22:41:23.26#ibcon#read 4, iclass 11, count 0 2006.173.22:41:23.26#ibcon#about to read 5, iclass 11, count 0 2006.173.22:41:23.26#ibcon#read 5, iclass 11, count 0 2006.173.22:41:23.26#ibcon#about to read 6, iclass 11, count 0 2006.173.22:41:23.26#ibcon#read 6, iclass 11, count 0 2006.173.22:41:23.26#ibcon#end of sib2, iclass 11, count 0 2006.173.22:41:23.26#ibcon#*after write, iclass 11, count 0 2006.173.22:41:23.26#ibcon#*before return 0, iclass 11, count 0 2006.173.22:41:23.26#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.22:41:23.26#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.22:41:23.26#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.22:41:23.26#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.22:41:23.26$vck44/va=4,6 2006.173.22:41:23.26#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.173.22:41:23.26#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.173.22:41:23.26#ibcon#ireg 11 cls_cnt 2 2006.173.22:41:23.26#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.22:41:23.32#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.22:41:23.32#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.22:41:23.32#ibcon#enter wrdev, iclass 13, count 2 2006.173.22:41:23.32#ibcon#first serial, iclass 13, count 2 2006.173.22:41:23.32#ibcon#enter sib2, iclass 13, count 2 2006.173.22:41:23.32#ibcon#flushed, iclass 13, count 2 2006.173.22:41:23.32#ibcon#about to write, iclass 13, count 2 2006.173.22:41:23.32#ibcon#wrote, iclass 13, count 2 2006.173.22:41:23.32#ibcon#about to read 3, iclass 13, count 2 2006.173.22:41:23.34#ibcon#read 3, iclass 13, count 2 2006.173.22:41:23.34#ibcon#about to read 4, iclass 13, count 2 2006.173.22:41:23.34#ibcon#read 4, iclass 13, count 2 2006.173.22:41:23.34#ibcon#about to read 5, iclass 13, count 2 2006.173.22:41:23.34#ibcon#read 5, iclass 13, count 2 2006.173.22:41:23.34#ibcon#about to read 6, iclass 13, count 2 2006.173.22:41:23.34#ibcon#read 6, iclass 13, count 2 2006.173.22:41:23.34#ibcon#end of sib2, iclass 13, count 2 2006.173.22:41:23.34#ibcon#*mode == 0, iclass 13, count 2 2006.173.22:41:23.34#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.173.22:41:23.34#ibcon#[25=AT04-06\r\n] 2006.173.22:41:23.34#ibcon#*before write, iclass 13, count 2 2006.173.22:41:23.34#ibcon#enter sib2, iclass 13, count 2 2006.173.22:41:23.34#ibcon#flushed, iclass 13, count 2 2006.173.22:41:23.34#ibcon#about to write, iclass 13, count 2 2006.173.22:41:23.34#ibcon#wrote, iclass 13, count 2 2006.173.22:41:23.34#ibcon#about to read 3, iclass 13, count 2 2006.173.22:41:23.37#ibcon#read 3, iclass 13, count 2 2006.173.22:41:23.37#ibcon#about to read 4, iclass 13, count 2 2006.173.22:41:23.37#ibcon#read 4, iclass 13, count 2 2006.173.22:41:23.37#ibcon#about to read 5, iclass 13, count 2 2006.173.22:41:23.37#ibcon#read 5, iclass 13, count 2 2006.173.22:41:23.37#ibcon#about to read 6, iclass 13, count 2 2006.173.22:41:23.37#ibcon#read 6, iclass 13, count 2 2006.173.22:41:23.37#ibcon#end of sib2, iclass 13, count 2 2006.173.22:41:23.37#ibcon#*after write, iclass 13, count 2 2006.173.22:41:23.37#ibcon#*before return 0, iclass 13, count 2 2006.173.22:41:23.37#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.22:41:23.37#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.173.22:41:23.37#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.173.22:41:23.37#ibcon#ireg 7 cls_cnt 0 2006.173.22:41:23.37#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.22:41:23.49#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.22:41:23.49#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.22:41:23.49#ibcon#enter wrdev, iclass 13, count 0 2006.173.22:41:23.49#ibcon#first serial, iclass 13, count 0 2006.173.22:41:23.49#ibcon#enter sib2, iclass 13, count 0 2006.173.22:41:23.49#ibcon#flushed, iclass 13, count 0 2006.173.22:41:23.49#ibcon#about to write, iclass 13, count 0 2006.173.22:41:23.49#ibcon#wrote, iclass 13, count 0 2006.173.22:41:23.49#ibcon#about to read 3, iclass 13, count 0 2006.173.22:41:23.51#ibcon#read 3, iclass 13, count 0 2006.173.22:41:23.51#ibcon#about to read 4, iclass 13, count 0 2006.173.22:41:23.51#ibcon#read 4, iclass 13, count 0 2006.173.22:41:23.51#ibcon#about to read 5, iclass 13, count 0 2006.173.22:41:23.51#ibcon#read 5, iclass 13, count 0 2006.173.22:41:23.51#ibcon#about to read 6, iclass 13, count 0 2006.173.22:41:23.51#ibcon#read 6, iclass 13, count 0 2006.173.22:41:23.51#ibcon#end of sib2, iclass 13, count 0 2006.173.22:41:23.51#ibcon#*mode == 0, iclass 13, count 0 2006.173.22:41:23.51#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.22:41:23.51#ibcon#[25=USB\r\n] 2006.173.22:41:23.51#ibcon#*before write, iclass 13, count 0 2006.173.22:41:23.51#ibcon#enter sib2, iclass 13, count 0 2006.173.22:41:23.51#ibcon#flushed, iclass 13, count 0 2006.173.22:41:23.51#ibcon#about to write, iclass 13, count 0 2006.173.22:41:23.51#ibcon#wrote, iclass 13, count 0 2006.173.22:41:23.51#ibcon#about to read 3, iclass 13, count 0 2006.173.22:41:23.54#ibcon#read 3, iclass 13, count 0 2006.173.22:41:23.54#ibcon#about to read 4, iclass 13, count 0 2006.173.22:41:23.54#ibcon#read 4, iclass 13, count 0 2006.173.22:41:23.54#ibcon#about to read 5, iclass 13, count 0 2006.173.22:41:23.54#ibcon#read 5, iclass 13, count 0 2006.173.22:41:23.54#ibcon#about to read 6, iclass 13, count 0 2006.173.22:41:23.54#ibcon#read 6, iclass 13, count 0 2006.173.22:41:23.54#ibcon#end of sib2, iclass 13, count 0 2006.173.22:41:23.54#ibcon#*after write, iclass 13, count 0 2006.173.22:41:23.54#ibcon#*before return 0, iclass 13, count 0 2006.173.22:41:23.54#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.22:41:23.54#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.173.22:41:23.54#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.22:41:23.54#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.22:41:23.54$vck44/valo=5,734.99 2006.173.22:41:23.54#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.22:41:23.54#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.22:41:23.54#ibcon#ireg 17 cls_cnt 0 2006.173.22:41:23.54#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.22:41:23.54#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.22:41:23.54#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.22:41:23.54#ibcon#enter wrdev, iclass 15, count 0 2006.173.22:41:23.54#ibcon#first serial, iclass 15, count 0 2006.173.22:41:23.54#ibcon#enter sib2, iclass 15, count 0 2006.173.22:41:23.54#ibcon#flushed, iclass 15, count 0 2006.173.22:41:23.54#ibcon#about to write, iclass 15, count 0 2006.173.22:41:23.54#ibcon#wrote, iclass 15, count 0 2006.173.22:41:23.54#ibcon#about to read 3, iclass 15, count 0 2006.173.22:41:23.56#ibcon#read 3, iclass 15, count 0 2006.173.22:41:23.56#ibcon#about to read 4, iclass 15, count 0 2006.173.22:41:23.56#ibcon#read 4, iclass 15, count 0 2006.173.22:41:23.56#ibcon#about to read 5, iclass 15, count 0 2006.173.22:41:23.56#ibcon#read 5, iclass 15, count 0 2006.173.22:41:23.56#ibcon#about to read 6, iclass 15, count 0 2006.173.22:41:23.56#ibcon#read 6, iclass 15, count 0 2006.173.22:41:23.56#ibcon#end of sib2, iclass 15, count 0 2006.173.22:41:23.56#ibcon#*mode == 0, iclass 15, count 0 2006.173.22:41:23.56#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.22:41:23.56#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.22:41:23.56#ibcon#*before write, iclass 15, count 0 2006.173.22:41:23.56#ibcon#enter sib2, iclass 15, count 0 2006.173.22:41:23.56#ibcon#flushed, iclass 15, count 0 2006.173.22:41:23.56#ibcon#about to write, iclass 15, count 0 2006.173.22:41:23.56#ibcon#wrote, iclass 15, count 0 2006.173.22:41:23.56#ibcon#about to read 3, iclass 15, count 0 2006.173.22:41:23.60#ibcon#read 3, iclass 15, count 0 2006.173.22:41:23.60#ibcon#about to read 4, iclass 15, count 0 2006.173.22:41:23.60#ibcon#read 4, iclass 15, count 0 2006.173.22:41:23.60#ibcon#about to read 5, iclass 15, count 0 2006.173.22:41:23.60#ibcon#read 5, iclass 15, count 0 2006.173.22:41:23.60#ibcon#about to read 6, iclass 15, count 0 2006.173.22:41:23.60#ibcon#read 6, iclass 15, count 0 2006.173.22:41:23.60#ibcon#end of sib2, iclass 15, count 0 2006.173.22:41:23.60#ibcon#*after write, iclass 15, count 0 2006.173.22:41:23.60#ibcon#*before return 0, iclass 15, count 0 2006.173.22:41:23.60#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.22:41:23.60#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.22:41:23.60#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.22:41:23.60#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.22:41:23.60$vck44/va=5,4 2006.173.22:41:23.60#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.22:41:23.60#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.22:41:23.60#ibcon#ireg 11 cls_cnt 2 2006.173.22:41:23.60#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.22:41:23.66#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.22:41:23.66#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.22:41:23.66#ibcon#enter wrdev, iclass 17, count 2 2006.173.22:41:23.66#ibcon#first serial, iclass 17, count 2 2006.173.22:41:23.66#ibcon#enter sib2, iclass 17, count 2 2006.173.22:41:23.66#ibcon#flushed, iclass 17, count 2 2006.173.22:41:23.66#ibcon#about to write, iclass 17, count 2 2006.173.22:41:23.66#ibcon#wrote, iclass 17, count 2 2006.173.22:41:23.66#ibcon#about to read 3, iclass 17, count 2 2006.173.22:41:23.68#ibcon#read 3, iclass 17, count 2 2006.173.22:41:23.68#ibcon#about to read 4, iclass 17, count 2 2006.173.22:41:23.68#ibcon#read 4, iclass 17, count 2 2006.173.22:41:23.68#ibcon#about to read 5, iclass 17, count 2 2006.173.22:41:23.68#ibcon#read 5, iclass 17, count 2 2006.173.22:41:23.68#ibcon#about to read 6, iclass 17, count 2 2006.173.22:41:23.68#ibcon#read 6, iclass 17, count 2 2006.173.22:41:23.68#ibcon#end of sib2, iclass 17, count 2 2006.173.22:41:23.68#ibcon#*mode == 0, iclass 17, count 2 2006.173.22:41:23.68#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.22:41:23.68#ibcon#[25=AT05-04\r\n] 2006.173.22:41:23.68#ibcon#*before write, iclass 17, count 2 2006.173.22:41:23.68#ibcon#enter sib2, iclass 17, count 2 2006.173.22:41:23.68#ibcon#flushed, iclass 17, count 2 2006.173.22:41:23.68#ibcon#about to write, iclass 17, count 2 2006.173.22:41:23.68#ibcon#wrote, iclass 17, count 2 2006.173.22:41:23.68#ibcon#about to read 3, iclass 17, count 2 2006.173.22:41:23.71#ibcon#read 3, iclass 17, count 2 2006.173.22:41:23.71#ibcon#about to read 4, iclass 17, count 2 2006.173.22:41:23.71#ibcon#read 4, iclass 17, count 2 2006.173.22:41:23.71#ibcon#about to read 5, iclass 17, count 2 2006.173.22:41:23.71#ibcon#read 5, iclass 17, count 2 2006.173.22:41:23.71#ibcon#about to read 6, iclass 17, count 2 2006.173.22:41:23.71#ibcon#read 6, iclass 17, count 2 2006.173.22:41:23.71#ibcon#end of sib2, iclass 17, count 2 2006.173.22:41:23.71#ibcon#*after write, iclass 17, count 2 2006.173.22:41:23.71#ibcon#*before return 0, iclass 17, count 2 2006.173.22:41:23.71#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.22:41:23.71#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.22:41:23.71#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.22:41:23.71#ibcon#ireg 7 cls_cnt 0 2006.173.22:41:23.71#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.22:41:23.83#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.22:41:23.83#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.22:41:23.83#ibcon#enter wrdev, iclass 17, count 0 2006.173.22:41:23.83#ibcon#first serial, iclass 17, count 0 2006.173.22:41:23.83#ibcon#enter sib2, iclass 17, count 0 2006.173.22:41:23.83#ibcon#flushed, iclass 17, count 0 2006.173.22:41:23.83#ibcon#about to write, iclass 17, count 0 2006.173.22:41:23.83#ibcon#wrote, iclass 17, count 0 2006.173.22:41:23.83#ibcon#about to read 3, iclass 17, count 0 2006.173.22:41:23.85#ibcon#read 3, iclass 17, count 0 2006.173.22:41:23.85#ibcon#about to read 4, iclass 17, count 0 2006.173.22:41:23.85#ibcon#read 4, iclass 17, count 0 2006.173.22:41:23.85#ibcon#about to read 5, iclass 17, count 0 2006.173.22:41:23.85#ibcon#read 5, iclass 17, count 0 2006.173.22:41:23.85#ibcon#about to read 6, iclass 17, count 0 2006.173.22:41:23.85#ibcon#read 6, iclass 17, count 0 2006.173.22:41:23.85#ibcon#end of sib2, iclass 17, count 0 2006.173.22:41:23.85#ibcon#*mode == 0, iclass 17, count 0 2006.173.22:41:23.85#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.22:41:23.85#ibcon#[25=USB\r\n] 2006.173.22:41:23.85#ibcon#*before write, iclass 17, count 0 2006.173.22:41:23.85#ibcon#enter sib2, iclass 17, count 0 2006.173.22:41:23.85#ibcon#flushed, iclass 17, count 0 2006.173.22:41:23.85#ibcon#about to write, iclass 17, count 0 2006.173.22:41:23.85#ibcon#wrote, iclass 17, count 0 2006.173.22:41:23.85#ibcon#about to read 3, iclass 17, count 0 2006.173.22:41:23.88#ibcon#read 3, iclass 17, count 0 2006.173.22:41:23.88#ibcon#about to read 4, iclass 17, count 0 2006.173.22:41:23.88#ibcon#read 4, iclass 17, count 0 2006.173.22:41:23.88#ibcon#about to read 5, iclass 17, count 0 2006.173.22:41:23.88#ibcon#read 5, iclass 17, count 0 2006.173.22:41:23.88#ibcon#about to read 6, iclass 17, count 0 2006.173.22:41:23.88#ibcon#read 6, iclass 17, count 0 2006.173.22:41:23.88#ibcon#end of sib2, iclass 17, count 0 2006.173.22:41:23.88#ibcon#*after write, iclass 17, count 0 2006.173.22:41:23.88#ibcon#*before return 0, iclass 17, count 0 2006.173.22:41:23.88#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.22:41:23.88#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.22:41:23.88#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.22:41:23.88#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.22:41:23.88$vck44/valo=6,814.99 2006.173.22:41:23.88#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.22:41:23.88#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.22:41:23.88#ibcon#ireg 17 cls_cnt 0 2006.173.22:41:23.88#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.22:41:23.88#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.22:41:23.88#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.22:41:23.88#ibcon#enter wrdev, iclass 19, count 0 2006.173.22:41:23.88#ibcon#first serial, iclass 19, count 0 2006.173.22:41:23.88#ibcon#enter sib2, iclass 19, count 0 2006.173.22:41:23.88#ibcon#flushed, iclass 19, count 0 2006.173.22:41:23.88#ibcon#about to write, iclass 19, count 0 2006.173.22:41:23.88#ibcon#wrote, iclass 19, count 0 2006.173.22:41:23.88#ibcon#about to read 3, iclass 19, count 0 2006.173.22:41:23.90#ibcon#read 3, iclass 19, count 0 2006.173.22:41:23.90#ibcon#about to read 4, iclass 19, count 0 2006.173.22:41:23.90#ibcon#read 4, iclass 19, count 0 2006.173.22:41:23.90#ibcon#about to read 5, iclass 19, count 0 2006.173.22:41:23.90#ibcon#read 5, iclass 19, count 0 2006.173.22:41:23.90#ibcon#about to read 6, iclass 19, count 0 2006.173.22:41:23.90#ibcon#read 6, iclass 19, count 0 2006.173.22:41:23.90#ibcon#end of sib2, iclass 19, count 0 2006.173.22:41:23.90#ibcon#*mode == 0, iclass 19, count 0 2006.173.22:41:23.90#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.22:41:23.90#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.22:41:23.90#ibcon#*before write, iclass 19, count 0 2006.173.22:41:23.90#ibcon#enter sib2, iclass 19, count 0 2006.173.22:41:23.90#ibcon#flushed, iclass 19, count 0 2006.173.22:41:23.90#ibcon#about to write, iclass 19, count 0 2006.173.22:41:23.90#ibcon#wrote, iclass 19, count 0 2006.173.22:41:23.90#ibcon#about to read 3, iclass 19, count 0 2006.173.22:41:23.94#ibcon#read 3, iclass 19, count 0 2006.173.22:41:23.94#ibcon#about to read 4, iclass 19, count 0 2006.173.22:41:23.94#ibcon#read 4, iclass 19, count 0 2006.173.22:41:23.94#ibcon#about to read 5, iclass 19, count 0 2006.173.22:41:23.94#ibcon#read 5, iclass 19, count 0 2006.173.22:41:23.94#ibcon#about to read 6, iclass 19, count 0 2006.173.22:41:23.94#ibcon#read 6, iclass 19, count 0 2006.173.22:41:23.94#ibcon#end of sib2, iclass 19, count 0 2006.173.22:41:23.94#ibcon#*after write, iclass 19, count 0 2006.173.22:41:23.94#ibcon#*before return 0, iclass 19, count 0 2006.173.22:41:23.94#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.22:41:23.94#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.22:41:23.94#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.22:41:23.94#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.22:41:23.94$vck44/va=6,3 2006.173.22:41:23.94#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.22:41:23.94#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.22:41:23.94#ibcon#ireg 11 cls_cnt 2 2006.173.22:41:23.94#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.22:41:24.00#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.22:41:24.00#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.22:41:24.00#ibcon#enter wrdev, iclass 21, count 2 2006.173.22:41:24.00#ibcon#first serial, iclass 21, count 2 2006.173.22:41:24.00#ibcon#enter sib2, iclass 21, count 2 2006.173.22:41:24.00#ibcon#flushed, iclass 21, count 2 2006.173.22:41:24.00#ibcon#about to write, iclass 21, count 2 2006.173.22:41:24.00#ibcon#wrote, iclass 21, count 2 2006.173.22:41:24.00#ibcon#about to read 3, iclass 21, count 2 2006.173.22:41:24.02#ibcon#read 3, iclass 21, count 2 2006.173.22:41:24.02#ibcon#about to read 4, iclass 21, count 2 2006.173.22:41:24.02#ibcon#read 4, iclass 21, count 2 2006.173.22:41:24.02#ibcon#about to read 5, iclass 21, count 2 2006.173.22:41:24.02#ibcon#read 5, iclass 21, count 2 2006.173.22:41:24.02#ibcon#about to read 6, iclass 21, count 2 2006.173.22:41:24.02#ibcon#read 6, iclass 21, count 2 2006.173.22:41:24.02#ibcon#end of sib2, iclass 21, count 2 2006.173.22:41:24.02#ibcon#*mode == 0, iclass 21, count 2 2006.173.22:41:24.02#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.22:41:24.02#ibcon#[25=AT06-03\r\n] 2006.173.22:41:24.02#ibcon#*before write, iclass 21, count 2 2006.173.22:41:24.02#ibcon#enter sib2, iclass 21, count 2 2006.173.22:41:24.02#ibcon#flushed, iclass 21, count 2 2006.173.22:41:24.02#ibcon#about to write, iclass 21, count 2 2006.173.22:41:24.02#ibcon#wrote, iclass 21, count 2 2006.173.22:41:24.02#ibcon#about to read 3, iclass 21, count 2 2006.173.22:41:24.05#ibcon#read 3, iclass 21, count 2 2006.173.22:41:24.05#ibcon#about to read 4, iclass 21, count 2 2006.173.22:41:24.05#ibcon#read 4, iclass 21, count 2 2006.173.22:41:24.05#ibcon#about to read 5, iclass 21, count 2 2006.173.22:41:24.05#ibcon#read 5, iclass 21, count 2 2006.173.22:41:24.05#ibcon#about to read 6, iclass 21, count 2 2006.173.22:41:24.05#ibcon#read 6, iclass 21, count 2 2006.173.22:41:24.05#ibcon#end of sib2, iclass 21, count 2 2006.173.22:41:24.05#ibcon#*after write, iclass 21, count 2 2006.173.22:41:24.05#ibcon#*before return 0, iclass 21, count 2 2006.173.22:41:24.05#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.22:41:24.05#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.22:41:24.05#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.22:41:24.05#ibcon#ireg 7 cls_cnt 0 2006.173.22:41:24.05#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.22:41:24.17#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.22:41:24.17#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.22:41:24.17#ibcon#enter wrdev, iclass 21, count 0 2006.173.22:41:24.17#ibcon#first serial, iclass 21, count 0 2006.173.22:41:24.17#ibcon#enter sib2, iclass 21, count 0 2006.173.22:41:24.17#ibcon#flushed, iclass 21, count 0 2006.173.22:41:24.17#ibcon#about to write, iclass 21, count 0 2006.173.22:41:24.17#ibcon#wrote, iclass 21, count 0 2006.173.22:41:24.17#ibcon#about to read 3, iclass 21, count 0 2006.173.22:41:24.19#ibcon#read 3, iclass 21, count 0 2006.173.22:41:24.19#ibcon#about to read 4, iclass 21, count 0 2006.173.22:41:24.19#ibcon#read 4, iclass 21, count 0 2006.173.22:41:24.19#ibcon#about to read 5, iclass 21, count 0 2006.173.22:41:24.19#ibcon#read 5, iclass 21, count 0 2006.173.22:41:24.19#ibcon#about to read 6, iclass 21, count 0 2006.173.22:41:24.19#ibcon#read 6, iclass 21, count 0 2006.173.22:41:24.19#ibcon#end of sib2, iclass 21, count 0 2006.173.22:41:24.19#ibcon#*mode == 0, iclass 21, count 0 2006.173.22:41:24.19#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.22:41:24.19#ibcon#[25=USB\r\n] 2006.173.22:41:24.19#ibcon#*before write, iclass 21, count 0 2006.173.22:41:24.19#ibcon#enter sib2, iclass 21, count 0 2006.173.22:41:24.19#ibcon#flushed, iclass 21, count 0 2006.173.22:41:24.19#ibcon#about to write, iclass 21, count 0 2006.173.22:41:24.19#ibcon#wrote, iclass 21, count 0 2006.173.22:41:24.19#ibcon#about to read 3, iclass 21, count 0 2006.173.22:41:24.22#ibcon#read 3, iclass 21, count 0 2006.173.22:41:24.22#ibcon#about to read 4, iclass 21, count 0 2006.173.22:41:24.22#ibcon#read 4, iclass 21, count 0 2006.173.22:41:24.22#ibcon#about to read 5, iclass 21, count 0 2006.173.22:41:24.22#ibcon#read 5, iclass 21, count 0 2006.173.22:41:24.22#ibcon#about to read 6, iclass 21, count 0 2006.173.22:41:24.22#ibcon#read 6, iclass 21, count 0 2006.173.22:41:24.22#ibcon#end of sib2, iclass 21, count 0 2006.173.22:41:24.22#ibcon#*after write, iclass 21, count 0 2006.173.22:41:24.22#ibcon#*before return 0, iclass 21, count 0 2006.173.22:41:24.22#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.22:41:24.22#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.22:41:24.22#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.22:41:24.22#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.22:41:24.22$vck44/valo=7,864.99 2006.173.22:41:24.22#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.22:41:24.22#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.22:41:24.22#ibcon#ireg 17 cls_cnt 0 2006.173.22:41:24.22#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.22:41:24.22#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.22:41:24.22#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.22:41:24.22#ibcon#enter wrdev, iclass 23, count 0 2006.173.22:41:24.22#ibcon#first serial, iclass 23, count 0 2006.173.22:41:24.22#ibcon#enter sib2, iclass 23, count 0 2006.173.22:41:24.22#ibcon#flushed, iclass 23, count 0 2006.173.22:41:24.22#ibcon#about to write, iclass 23, count 0 2006.173.22:41:24.22#ibcon#wrote, iclass 23, count 0 2006.173.22:41:24.22#ibcon#about to read 3, iclass 23, count 0 2006.173.22:41:24.24#ibcon#read 3, iclass 23, count 0 2006.173.22:41:24.24#ibcon#about to read 4, iclass 23, count 0 2006.173.22:41:24.24#ibcon#read 4, iclass 23, count 0 2006.173.22:41:24.24#ibcon#about to read 5, iclass 23, count 0 2006.173.22:41:24.24#ibcon#read 5, iclass 23, count 0 2006.173.22:41:24.24#ibcon#about to read 6, iclass 23, count 0 2006.173.22:41:24.24#ibcon#read 6, iclass 23, count 0 2006.173.22:41:24.24#ibcon#end of sib2, iclass 23, count 0 2006.173.22:41:24.24#ibcon#*mode == 0, iclass 23, count 0 2006.173.22:41:24.24#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.22:41:24.24#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.22:41:24.24#ibcon#*before write, iclass 23, count 0 2006.173.22:41:24.24#ibcon#enter sib2, iclass 23, count 0 2006.173.22:41:24.24#ibcon#flushed, iclass 23, count 0 2006.173.22:41:24.24#ibcon#about to write, iclass 23, count 0 2006.173.22:41:24.24#ibcon#wrote, iclass 23, count 0 2006.173.22:41:24.24#ibcon#about to read 3, iclass 23, count 0 2006.173.22:41:24.28#ibcon#read 3, iclass 23, count 0 2006.173.22:41:24.28#ibcon#about to read 4, iclass 23, count 0 2006.173.22:41:24.28#ibcon#read 4, iclass 23, count 0 2006.173.22:41:24.28#ibcon#about to read 5, iclass 23, count 0 2006.173.22:41:24.28#ibcon#read 5, iclass 23, count 0 2006.173.22:41:24.28#ibcon#about to read 6, iclass 23, count 0 2006.173.22:41:24.28#ibcon#read 6, iclass 23, count 0 2006.173.22:41:24.28#ibcon#end of sib2, iclass 23, count 0 2006.173.22:41:24.28#ibcon#*after write, iclass 23, count 0 2006.173.22:41:24.28#ibcon#*before return 0, iclass 23, count 0 2006.173.22:41:24.28#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.22:41:24.28#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.22:41:24.28#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.22:41:24.28#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.22:41:24.28$vck44/va=7,4 2006.173.22:41:24.28#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.22:41:24.28#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.22:41:24.28#ibcon#ireg 11 cls_cnt 2 2006.173.22:41:24.28#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.22:41:24.34#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.22:41:24.34#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.22:41:24.34#ibcon#enter wrdev, iclass 25, count 2 2006.173.22:41:24.34#ibcon#first serial, iclass 25, count 2 2006.173.22:41:24.34#ibcon#enter sib2, iclass 25, count 2 2006.173.22:41:24.34#ibcon#flushed, iclass 25, count 2 2006.173.22:41:24.34#ibcon#about to write, iclass 25, count 2 2006.173.22:41:24.34#ibcon#wrote, iclass 25, count 2 2006.173.22:41:24.34#ibcon#about to read 3, iclass 25, count 2 2006.173.22:41:24.36#ibcon#read 3, iclass 25, count 2 2006.173.22:41:24.36#ibcon#about to read 4, iclass 25, count 2 2006.173.22:41:24.36#ibcon#read 4, iclass 25, count 2 2006.173.22:41:24.36#ibcon#about to read 5, iclass 25, count 2 2006.173.22:41:24.36#ibcon#read 5, iclass 25, count 2 2006.173.22:41:24.36#ibcon#about to read 6, iclass 25, count 2 2006.173.22:41:24.36#ibcon#read 6, iclass 25, count 2 2006.173.22:41:24.36#ibcon#end of sib2, iclass 25, count 2 2006.173.22:41:24.36#ibcon#*mode == 0, iclass 25, count 2 2006.173.22:41:24.36#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.22:41:24.36#ibcon#[25=AT07-04\r\n] 2006.173.22:41:24.36#ibcon#*before write, iclass 25, count 2 2006.173.22:41:24.36#ibcon#enter sib2, iclass 25, count 2 2006.173.22:41:24.36#ibcon#flushed, iclass 25, count 2 2006.173.22:41:24.36#ibcon#about to write, iclass 25, count 2 2006.173.22:41:24.36#ibcon#wrote, iclass 25, count 2 2006.173.22:41:24.36#ibcon#about to read 3, iclass 25, count 2 2006.173.22:41:24.39#ibcon#read 3, iclass 25, count 2 2006.173.22:41:24.39#ibcon#about to read 4, iclass 25, count 2 2006.173.22:41:24.39#ibcon#read 4, iclass 25, count 2 2006.173.22:41:24.39#ibcon#about to read 5, iclass 25, count 2 2006.173.22:41:24.39#ibcon#read 5, iclass 25, count 2 2006.173.22:41:24.39#ibcon#about to read 6, iclass 25, count 2 2006.173.22:41:24.39#ibcon#read 6, iclass 25, count 2 2006.173.22:41:24.39#ibcon#end of sib2, iclass 25, count 2 2006.173.22:41:24.39#ibcon#*after write, iclass 25, count 2 2006.173.22:41:24.39#ibcon#*before return 0, iclass 25, count 2 2006.173.22:41:24.39#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.22:41:24.39#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.22:41:24.39#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.22:41:24.39#ibcon#ireg 7 cls_cnt 0 2006.173.22:41:24.39#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.22:41:24.51#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.22:41:24.51#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.22:41:24.51#ibcon#enter wrdev, iclass 25, count 0 2006.173.22:41:24.51#ibcon#first serial, iclass 25, count 0 2006.173.22:41:24.51#ibcon#enter sib2, iclass 25, count 0 2006.173.22:41:24.51#ibcon#flushed, iclass 25, count 0 2006.173.22:41:24.51#ibcon#about to write, iclass 25, count 0 2006.173.22:41:24.51#ibcon#wrote, iclass 25, count 0 2006.173.22:41:24.51#ibcon#about to read 3, iclass 25, count 0 2006.173.22:41:24.53#ibcon#read 3, iclass 25, count 0 2006.173.22:41:24.53#ibcon#about to read 4, iclass 25, count 0 2006.173.22:41:24.53#ibcon#read 4, iclass 25, count 0 2006.173.22:41:24.53#ibcon#about to read 5, iclass 25, count 0 2006.173.22:41:24.53#ibcon#read 5, iclass 25, count 0 2006.173.22:41:24.53#ibcon#about to read 6, iclass 25, count 0 2006.173.22:41:24.53#ibcon#read 6, iclass 25, count 0 2006.173.22:41:24.53#ibcon#end of sib2, iclass 25, count 0 2006.173.22:41:24.53#ibcon#*mode == 0, iclass 25, count 0 2006.173.22:41:24.53#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.22:41:24.53#ibcon#[25=USB\r\n] 2006.173.22:41:24.53#ibcon#*before write, iclass 25, count 0 2006.173.22:41:24.53#ibcon#enter sib2, iclass 25, count 0 2006.173.22:41:24.53#ibcon#flushed, iclass 25, count 0 2006.173.22:41:24.53#ibcon#about to write, iclass 25, count 0 2006.173.22:41:24.53#ibcon#wrote, iclass 25, count 0 2006.173.22:41:24.53#ibcon#about to read 3, iclass 25, count 0 2006.173.22:41:24.56#ibcon#read 3, iclass 25, count 0 2006.173.22:41:24.56#ibcon#about to read 4, iclass 25, count 0 2006.173.22:41:24.56#ibcon#read 4, iclass 25, count 0 2006.173.22:41:24.56#ibcon#about to read 5, iclass 25, count 0 2006.173.22:41:24.56#ibcon#read 5, iclass 25, count 0 2006.173.22:41:24.56#ibcon#about to read 6, iclass 25, count 0 2006.173.22:41:24.56#ibcon#read 6, iclass 25, count 0 2006.173.22:41:24.56#ibcon#end of sib2, iclass 25, count 0 2006.173.22:41:24.56#ibcon#*after write, iclass 25, count 0 2006.173.22:41:24.56#ibcon#*before return 0, iclass 25, count 0 2006.173.22:41:24.56#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.22:41:24.56#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.22:41:24.56#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.22:41:24.56#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.22:41:24.56$vck44/valo=8,884.99 2006.173.22:41:24.56#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.22:41:24.56#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.22:41:24.56#ibcon#ireg 17 cls_cnt 0 2006.173.22:41:24.56#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.22:41:24.56#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.22:41:24.56#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.22:41:24.56#ibcon#enter wrdev, iclass 27, count 0 2006.173.22:41:24.56#ibcon#first serial, iclass 27, count 0 2006.173.22:41:24.56#ibcon#enter sib2, iclass 27, count 0 2006.173.22:41:24.56#ibcon#flushed, iclass 27, count 0 2006.173.22:41:24.56#ibcon#about to write, iclass 27, count 0 2006.173.22:41:24.56#ibcon#wrote, iclass 27, count 0 2006.173.22:41:24.56#ibcon#about to read 3, iclass 27, count 0 2006.173.22:41:24.58#ibcon#read 3, iclass 27, count 0 2006.173.22:41:24.58#ibcon#about to read 4, iclass 27, count 0 2006.173.22:41:24.58#ibcon#read 4, iclass 27, count 0 2006.173.22:41:24.58#ibcon#about to read 5, iclass 27, count 0 2006.173.22:41:24.58#ibcon#read 5, iclass 27, count 0 2006.173.22:41:24.58#ibcon#about to read 6, iclass 27, count 0 2006.173.22:41:24.58#ibcon#read 6, iclass 27, count 0 2006.173.22:41:24.58#ibcon#end of sib2, iclass 27, count 0 2006.173.22:41:24.58#ibcon#*mode == 0, iclass 27, count 0 2006.173.22:41:24.58#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.22:41:24.58#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.22:41:24.58#ibcon#*before write, iclass 27, count 0 2006.173.22:41:24.58#ibcon#enter sib2, iclass 27, count 0 2006.173.22:41:24.58#ibcon#flushed, iclass 27, count 0 2006.173.22:41:24.58#ibcon#about to write, iclass 27, count 0 2006.173.22:41:24.58#ibcon#wrote, iclass 27, count 0 2006.173.22:41:24.58#ibcon#about to read 3, iclass 27, count 0 2006.173.22:41:24.62#ibcon#read 3, iclass 27, count 0 2006.173.22:41:24.62#ibcon#about to read 4, iclass 27, count 0 2006.173.22:41:24.62#ibcon#read 4, iclass 27, count 0 2006.173.22:41:24.62#ibcon#about to read 5, iclass 27, count 0 2006.173.22:41:24.62#ibcon#read 5, iclass 27, count 0 2006.173.22:41:24.62#ibcon#about to read 6, iclass 27, count 0 2006.173.22:41:24.62#ibcon#read 6, iclass 27, count 0 2006.173.22:41:24.62#ibcon#end of sib2, iclass 27, count 0 2006.173.22:41:24.62#ibcon#*after write, iclass 27, count 0 2006.173.22:41:24.62#ibcon#*before return 0, iclass 27, count 0 2006.173.22:41:24.62#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.22:41:24.62#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.22:41:24.62#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.22:41:24.62#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.22:41:24.62$vck44/va=8,4 2006.173.22:41:24.62#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.22:41:24.62#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.22:41:24.62#ibcon#ireg 11 cls_cnt 2 2006.173.22:41:24.62#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.22:41:24.68#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.22:41:24.68#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.22:41:24.68#ibcon#enter wrdev, iclass 29, count 2 2006.173.22:41:24.68#ibcon#first serial, iclass 29, count 2 2006.173.22:41:24.68#ibcon#enter sib2, iclass 29, count 2 2006.173.22:41:24.68#ibcon#flushed, iclass 29, count 2 2006.173.22:41:24.68#ibcon#about to write, iclass 29, count 2 2006.173.22:41:24.68#ibcon#wrote, iclass 29, count 2 2006.173.22:41:24.68#ibcon#about to read 3, iclass 29, count 2 2006.173.22:41:24.70#ibcon#read 3, iclass 29, count 2 2006.173.22:41:24.70#ibcon#about to read 4, iclass 29, count 2 2006.173.22:41:24.70#ibcon#read 4, iclass 29, count 2 2006.173.22:41:24.70#ibcon#about to read 5, iclass 29, count 2 2006.173.22:41:24.70#ibcon#read 5, iclass 29, count 2 2006.173.22:41:24.70#ibcon#about to read 6, iclass 29, count 2 2006.173.22:41:24.70#ibcon#read 6, iclass 29, count 2 2006.173.22:41:24.70#ibcon#end of sib2, iclass 29, count 2 2006.173.22:41:24.70#ibcon#*mode == 0, iclass 29, count 2 2006.173.22:41:24.70#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.22:41:24.70#ibcon#[25=AT08-04\r\n] 2006.173.22:41:24.70#ibcon#*before write, iclass 29, count 2 2006.173.22:41:24.70#ibcon#enter sib2, iclass 29, count 2 2006.173.22:41:24.70#ibcon#flushed, iclass 29, count 2 2006.173.22:41:24.70#ibcon#about to write, iclass 29, count 2 2006.173.22:41:24.70#ibcon#wrote, iclass 29, count 2 2006.173.22:41:24.70#ibcon#about to read 3, iclass 29, count 2 2006.173.22:41:24.73#ibcon#read 3, iclass 29, count 2 2006.173.22:41:24.73#ibcon#about to read 4, iclass 29, count 2 2006.173.22:41:24.73#ibcon#read 4, iclass 29, count 2 2006.173.22:41:24.73#ibcon#about to read 5, iclass 29, count 2 2006.173.22:41:24.73#ibcon#read 5, iclass 29, count 2 2006.173.22:41:24.73#ibcon#about to read 6, iclass 29, count 2 2006.173.22:41:24.73#ibcon#read 6, iclass 29, count 2 2006.173.22:41:24.73#ibcon#end of sib2, iclass 29, count 2 2006.173.22:41:24.73#ibcon#*after write, iclass 29, count 2 2006.173.22:41:24.73#ibcon#*before return 0, iclass 29, count 2 2006.173.22:41:24.73#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.22:41:24.73#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.22:41:24.73#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.22:41:24.73#ibcon#ireg 7 cls_cnt 0 2006.173.22:41:24.73#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.22:41:24.85#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.22:41:24.85#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.22:41:24.85#ibcon#enter wrdev, iclass 29, count 0 2006.173.22:41:24.85#ibcon#first serial, iclass 29, count 0 2006.173.22:41:24.85#ibcon#enter sib2, iclass 29, count 0 2006.173.22:41:24.85#ibcon#flushed, iclass 29, count 0 2006.173.22:41:24.85#ibcon#about to write, iclass 29, count 0 2006.173.22:41:24.85#ibcon#wrote, iclass 29, count 0 2006.173.22:41:24.85#ibcon#about to read 3, iclass 29, count 0 2006.173.22:41:24.87#ibcon#read 3, iclass 29, count 0 2006.173.22:41:24.87#ibcon#about to read 4, iclass 29, count 0 2006.173.22:41:24.87#ibcon#read 4, iclass 29, count 0 2006.173.22:41:24.87#ibcon#about to read 5, iclass 29, count 0 2006.173.22:41:24.87#ibcon#read 5, iclass 29, count 0 2006.173.22:41:24.87#ibcon#about to read 6, iclass 29, count 0 2006.173.22:41:24.87#ibcon#read 6, iclass 29, count 0 2006.173.22:41:24.87#ibcon#end of sib2, iclass 29, count 0 2006.173.22:41:24.87#ibcon#*mode == 0, iclass 29, count 0 2006.173.22:41:24.87#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.22:41:24.87#ibcon#[25=USB\r\n] 2006.173.22:41:24.87#ibcon#*before write, iclass 29, count 0 2006.173.22:41:24.87#ibcon#enter sib2, iclass 29, count 0 2006.173.22:41:24.87#ibcon#flushed, iclass 29, count 0 2006.173.22:41:24.87#ibcon#about to write, iclass 29, count 0 2006.173.22:41:24.87#ibcon#wrote, iclass 29, count 0 2006.173.22:41:24.87#ibcon#about to read 3, iclass 29, count 0 2006.173.22:41:24.90#ibcon#read 3, iclass 29, count 0 2006.173.22:41:24.90#ibcon#about to read 4, iclass 29, count 0 2006.173.22:41:24.90#ibcon#read 4, iclass 29, count 0 2006.173.22:41:24.90#ibcon#about to read 5, iclass 29, count 0 2006.173.22:41:24.90#ibcon#read 5, iclass 29, count 0 2006.173.22:41:24.90#ibcon#about to read 6, iclass 29, count 0 2006.173.22:41:24.90#ibcon#read 6, iclass 29, count 0 2006.173.22:41:24.90#ibcon#end of sib2, iclass 29, count 0 2006.173.22:41:24.90#ibcon#*after write, iclass 29, count 0 2006.173.22:41:24.90#ibcon#*before return 0, iclass 29, count 0 2006.173.22:41:24.90#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.22:41:24.90#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.22:41:24.90#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.22:41:24.90#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.22:41:24.90$vck44/vblo=1,629.99 2006.173.22:41:24.90#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.22:41:24.90#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.22:41:24.90#ibcon#ireg 17 cls_cnt 0 2006.173.22:41:24.90#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.22:41:24.90#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.22:41:24.90#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.22:41:24.90#ibcon#enter wrdev, iclass 31, count 0 2006.173.22:41:24.90#ibcon#first serial, iclass 31, count 0 2006.173.22:41:24.90#ibcon#enter sib2, iclass 31, count 0 2006.173.22:41:24.90#ibcon#flushed, iclass 31, count 0 2006.173.22:41:24.90#ibcon#about to write, iclass 31, count 0 2006.173.22:41:24.90#ibcon#wrote, iclass 31, count 0 2006.173.22:41:24.90#ibcon#about to read 3, iclass 31, count 0 2006.173.22:41:24.92#ibcon#read 3, iclass 31, count 0 2006.173.22:41:24.92#ibcon#about to read 4, iclass 31, count 0 2006.173.22:41:24.92#ibcon#read 4, iclass 31, count 0 2006.173.22:41:24.92#ibcon#about to read 5, iclass 31, count 0 2006.173.22:41:24.92#ibcon#read 5, iclass 31, count 0 2006.173.22:41:24.92#ibcon#about to read 6, iclass 31, count 0 2006.173.22:41:24.92#ibcon#read 6, iclass 31, count 0 2006.173.22:41:24.92#ibcon#end of sib2, iclass 31, count 0 2006.173.22:41:24.92#ibcon#*mode == 0, iclass 31, count 0 2006.173.22:41:24.92#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.22:41:24.92#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.22:41:24.92#ibcon#*before write, iclass 31, count 0 2006.173.22:41:24.92#ibcon#enter sib2, iclass 31, count 0 2006.173.22:41:24.92#ibcon#flushed, iclass 31, count 0 2006.173.22:41:24.92#ibcon#about to write, iclass 31, count 0 2006.173.22:41:24.92#ibcon#wrote, iclass 31, count 0 2006.173.22:41:24.92#ibcon#about to read 3, iclass 31, count 0 2006.173.22:41:24.96#ibcon#read 3, iclass 31, count 0 2006.173.22:41:24.96#ibcon#about to read 4, iclass 31, count 0 2006.173.22:41:24.96#ibcon#read 4, iclass 31, count 0 2006.173.22:41:24.96#ibcon#about to read 5, iclass 31, count 0 2006.173.22:41:24.96#ibcon#read 5, iclass 31, count 0 2006.173.22:41:24.96#ibcon#about to read 6, iclass 31, count 0 2006.173.22:41:24.96#ibcon#read 6, iclass 31, count 0 2006.173.22:41:24.96#ibcon#end of sib2, iclass 31, count 0 2006.173.22:41:24.96#ibcon#*after write, iclass 31, count 0 2006.173.22:41:24.96#ibcon#*before return 0, iclass 31, count 0 2006.173.22:41:24.96#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.22:41:24.96#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.22:41:24.96#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.22:41:24.96#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.22:41:24.96$vck44/vb=1,4 2006.173.22:41:24.96#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.173.22:41:24.96#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.173.22:41:24.96#ibcon#ireg 11 cls_cnt 2 2006.173.22:41:24.96#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.22:41:24.96#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.22:41:24.96#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.22:41:24.96#ibcon#enter wrdev, iclass 33, count 2 2006.173.22:41:24.96#ibcon#first serial, iclass 33, count 2 2006.173.22:41:24.96#ibcon#enter sib2, iclass 33, count 2 2006.173.22:41:24.96#ibcon#flushed, iclass 33, count 2 2006.173.22:41:24.96#ibcon#about to write, iclass 33, count 2 2006.173.22:41:24.96#ibcon#wrote, iclass 33, count 2 2006.173.22:41:24.96#ibcon#about to read 3, iclass 33, count 2 2006.173.22:41:24.98#ibcon#read 3, iclass 33, count 2 2006.173.22:41:24.98#ibcon#about to read 4, iclass 33, count 2 2006.173.22:41:24.98#ibcon#read 4, iclass 33, count 2 2006.173.22:41:24.98#ibcon#about to read 5, iclass 33, count 2 2006.173.22:41:24.98#ibcon#read 5, iclass 33, count 2 2006.173.22:41:24.98#ibcon#about to read 6, iclass 33, count 2 2006.173.22:41:24.98#ibcon#read 6, iclass 33, count 2 2006.173.22:41:24.98#ibcon#end of sib2, iclass 33, count 2 2006.173.22:41:24.98#ibcon#*mode == 0, iclass 33, count 2 2006.173.22:41:24.98#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.173.22:41:24.98#ibcon#[27=AT01-04\r\n] 2006.173.22:41:24.98#ibcon#*before write, iclass 33, count 2 2006.173.22:41:24.98#ibcon#enter sib2, iclass 33, count 2 2006.173.22:41:24.98#ibcon#flushed, iclass 33, count 2 2006.173.22:41:24.98#ibcon#about to write, iclass 33, count 2 2006.173.22:41:24.98#ibcon#wrote, iclass 33, count 2 2006.173.22:41:24.98#ibcon#about to read 3, iclass 33, count 2 2006.173.22:41:25.01#ibcon#read 3, iclass 33, count 2 2006.173.22:41:25.01#ibcon#about to read 4, iclass 33, count 2 2006.173.22:41:25.01#ibcon#read 4, iclass 33, count 2 2006.173.22:41:25.01#ibcon#about to read 5, iclass 33, count 2 2006.173.22:41:25.01#ibcon#read 5, iclass 33, count 2 2006.173.22:41:25.01#ibcon#about to read 6, iclass 33, count 2 2006.173.22:41:25.01#ibcon#read 6, iclass 33, count 2 2006.173.22:41:25.01#ibcon#end of sib2, iclass 33, count 2 2006.173.22:41:25.01#ibcon#*after write, iclass 33, count 2 2006.173.22:41:25.01#ibcon#*before return 0, iclass 33, count 2 2006.173.22:41:25.01#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.22:41:25.01#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.173.22:41:25.01#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.173.22:41:25.01#ibcon#ireg 7 cls_cnt 0 2006.173.22:41:25.01#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.22:41:25.13#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.22:41:25.13#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.22:41:25.13#ibcon#enter wrdev, iclass 33, count 0 2006.173.22:41:25.13#ibcon#first serial, iclass 33, count 0 2006.173.22:41:25.13#ibcon#enter sib2, iclass 33, count 0 2006.173.22:41:25.13#ibcon#flushed, iclass 33, count 0 2006.173.22:41:25.13#ibcon#about to write, iclass 33, count 0 2006.173.22:41:25.13#ibcon#wrote, iclass 33, count 0 2006.173.22:41:25.13#ibcon#about to read 3, iclass 33, count 0 2006.173.22:41:25.15#ibcon#read 3, iclass 33, count 0 2006.173.22:41:25.15#ibcon#about to read 4, iclass 33, count 0 2006.173.22:41:25.15#ibcon#read 4, iclass 33, count 0 2006.173.22:41:25.15#ibcon#about to read 5, iclass 33, count 0 2006.173.22:41:25.15#ibcon#read 5, iclass 33, count 0 2006.173.22:41:25.15#ibcon#about to read 6, iclass 33, count 0 2006.173.22:41:25.15#ibcon#read 6, iclass 33, count 0 2006.173.22:41:25.15#ibcon#end of sib2, iclass 33, count 0 2006.173.22:41:25.15#ibcon#*mode == 0, iclass 33, count 0 2006.173.22:41:25.15#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.22:41:25.15#ibcon#[27=USB\r\n] 2006.173.22:41:25.15#ibcon#*before write, iclass 33, count 0 2006.173.22:41:25.15#ibcon#enter sib2, iclass 33, count 0 2006.173.22:41:25.15#ibcon#flushed, iclass 33, count 0 2006.173.22:41:25.15#ibcon#about to write, iclass 33, count 0 2006.173.22:41:25.15#ibcon#wrote, iclass 33, count 0 2006.173.22:41:25.15#ibcon#about to read 3, iclass 33, count 0 2006.173.22:41:25.18#ibcon#read 3, iclass 33, count 0 2006.173.22:41:25.18#ibcon#about to read 4, iclass 33, count 0 2006.173.22:41:25.18#ibcon#read 4, iclass 33, count 0 2006.173.22:41:25.18#ibcon#about to read 5, iclass 33, count 0 2006.173.22:41:25.18#ibcon#read 5, iclass 33, count 0 2006.173.22:41:25.18#ibcon#about to read 6, iclass 33, count 0 2006.173.22:41:25.18#ibcon#read 6, iclass 33, count 0 2006.173.22:41:25.18#ibcon#end of sib2, iclass 33, count 0 2006.173.22:41:25.18#ibcon#*after write, iclass 33, count 0 2006.173.22:41:25.18#ibcon#*before return 0, iclass 33, count 0 2006.173.22:41:25.18#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.22:41:25.18#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.173.22:41:25.18#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.22:41:25.18#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.22:41:25.18$vck44/vblo=2,634.99 2006.173.22:41:25.18#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.22:41:25.18#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.22:41:25.18#ibcon#ireg 17 cls_cnt 0 2006.173.22:41:25.18#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.22:41:25.18#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.22:41:25.18#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.22:41:25.18#ibcon#enter wrdev, iclass 35, count 0 2006.173.22:41:25.18#ibcon#first serial, iclass 35, count 0 2006.173.22:41:25.18#ibcon#enter sib2, iclass 35, count 0 2006.173.22:41:25.18#ibcon#flushed, iclass 35, count 0 2006.173.22:41:25.18#ibcon#about to write, iclass 35, count 0 2006.173.22:41:25.18#ibcon#wrote, iclass 35, count 0 2006.173.22:41:25.18#ibcon#about to read 3, iclass 35, count 0 2006.173.22:41:25.20#ibcon#read 3, iclass 35, count 0 2006.173.22:41:25.20#ibcon#about to read 4, iclass 35, count 0 2006.173.22:41:25.20#ibcon#read 4, iclass 35, count 0 2006.173.22:41:25.20#ibcon#about to read 5, iclass 35, count 0 2006.173.22:41:25.20#ibcon#read 5, iclass 35, count 0 2006.173.22:41:25.20#ibcon#about to read 6, iclass 35, count 0 2006.173.22:41:25.20#ibcon#read 6, iclass 35, count 0 2006.173.22:41:25.20#ibcon#end of sib2, iclass 35, count 0 2006.173.22:41:25.20#ibcon#*mode == 0, iclass 35, count 0 2006.173.22:41:25.20#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.22:41:25.20#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.22:41:25.20#ibcon#*before write, iclass 35, count 0 2006.173.22:41:25.20#ibcon#enter sib2, iclass 35, count 0 2006.173.22:41:25.20#ibcon#flushed, iclass 35, count 0 2006.173.22:41:25.20#ibcon#about to write, iclass 35, count 0 2006.173.22:41:25.20#ibcon#wrote, iclass 35, count 0 2006.173.22:41:25.20#ibcon#about to read 3, iclass 35, count 0 2006.173.22:41:25.24#ibcon#read 3, iclass 35, count 0 2006.173.22:41:25.24#ibcon#about to read 4, iclass 35, count 0 2006.173.22:41:25.24#ibcon#read 4, iclass 35, count 0 2006.173.22:41:25.24#ibcon#about to read 5, iclass 35, count 0 2006.173.22:41:25.24#ibcon#read 5, iclass 35, count 0 2006.173.22:41:25.24#ibcon#about to read 6, iclass 35, count 0 2006.173.22:41:25.24#ibcon#read 6, iclass 35, count 0 2006.173.22:41:25.24#ibcon#end of sib2, iclass 35, count 0 2006.173.22:41:25.24#ibcon#*after write, iclass 35, count 0 2006.173.22:41:25.24#ibcon#*before return 0, iclass 35, count 0 2006.173.22:41:25.24#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.22:41:25.24#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.22:41:25.24#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.22:41:25.24#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.22:41:25.24$vck44/vb=2,4 2006.173.22:41:25.24#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.173.22:41:25.24#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.173.22:41:25.24#ibcon#ireg 11 cls_cnt 2 2006.173.22:41:25.24#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.22:41:25.30#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.22:41:25.30#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.22:41:25.30#ibcon#enter wrdev, iclass 37, count 2 2006.173.22:41:25.30#ibcon#first serial, iclass 37, count 2 2006.173.22:41:25.30#ibcon#enter sib2, iclass 37, count 2 2006.173.22:41:25.30#ibcon#flushed, iclass 37, count 2 2006.173.22:41:25.30#ibcon#about to write, iclass 37, count 2 2006.173.22:41:25.30#ibcon#wrote, iclass 37, count 2 2006.173.22:41:25.30#ibcon#about to read 3, iclass 37, count 2 2006.173.22:41:25.32#ibcon#read 3, iclass 37, count 2 2006.173.22:41:25.32#ibcon#about to read 4, iclass 37, count 2 2006.173.22:41:25.32#ibcon#read 4, iclass 37, count 2 2006.173.22:41:25.32#ibcon#about to read 5, iclass 37, count 2 2006.173.22:41:25.32#ibcon#read 5, iclass 37, count 2 2006.173.22:41:25.32#ibcon#about to read 6, iclass 37, count 2 2006.173.22:41:25.32#ibcon#read 6, iclass 37, count 2 2006.173.22:41:25.32#ibcon#end of sib2, iclass 37, count 2 2006.173.22:41:25.32#ibcon#*mode == 0, iclass 37, count 2 2006.173.22:41:25.32#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.173.22:41:25.32#ibcon#[27=AT02-04\r\n] 2006.173.22:41:25.32#ibcon#*before write, iclass 37, count 2 2006.173.22:41:25.32#ibcon#enter sib2, iclass 37, count 2 2006.173.22:41:25.32#ibcon#flushed, iclass 37, count 2 2006.173.22:41:25.32#ibcon#about to write, iclass 37, count 2 2006.173.22:41:25.32#ibcon#wrote, iclass 37, count 2 2006.173.22:41:25.32#ibcon#about to read 3, iclass 37, count 2 2006.173.22:41:25.35#ibcon#read 3, iclass 37, count 2 2006.173.22:41:25.35#ibcon#about to read 4, iclass 37, count 2 2006.173.22:41:25.35#ibcon#read 4, iclass 37, count 2 2006.173.22:41:25.35#ibcon#about to read 5, iclass 37, count 2 2006.173.22:41:25.35#ibcon#read 5, iclass 37, count 2 2006.173.22:41:25.35#ibcon#about to read 6, iclass 37, count 2 2006.173.22:41:25.35#ibcon#read 6, iclass 37, count 2 2006.173.22:41:25.35#ibcon#end of sib2, iclass 37, count 2 2006.173.22:41:25.35#ibcon#*after write, iclass 37, count 2 2006.173.22:41:25.35#ibcon#*before return 0, iclass 37, count 2 2006.173.22:41:25.35#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.22:41:25.35#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.173.22:41:25.35#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.173.22:41:25.35#ibcon#ireg 7 cls_cnt 0 2006.173.22:41:25.35#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.22:41:25.47#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.22:41:25.47#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.22:41:25.47#ibcon#enter wrdev, iclass 37, count 0 2006.173.22:41:25.47#ibcon#first serial, iclass 37, count 0 2006.173.22:41:25.47#ibcon#enter sib2, iclass 37, count 0 2006.173.22:41:25.47#ibcon#flushed, iclass 37, count 0 2006.173.22:41:25.47#ibcon#about to write, iclass 37, count 0 2006.173.22:41:25.47#ibcon#wrote, iclass 37, count 0 2006.173.22:41:25.47#ibcon#about to read 3, iclass 37, count 0 2006.173.22:41:25.49#ibcon#read 3, iclass 37, count 0 2006.173.22:41:25.49#ibcon#about to read 4, iclass 37, count 0 2006.173.22:41:25.49#ibcon#read 4, iclass 37, count 0 2006.173.22:41:25.49#ibcon#about to read 5, iclass 37, count 0 2006.173.22:41:25.49#ibcon#read 5, iclass 37, count 0 2006.173.22:41:25.49#ibcon#about to read 6, iclass 37, count 0 2006.173.22:41:25.49#ibcon#read 6, iclass 37, count 0 2006.173.22:41:25.49#ibcon#end of sib2, iclass 37, count 0 2006.173.22:41:25.49#ibcon#*mode == 0, iclass 37, count 0 2006.173.22:41:25.49#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.22:41:25.49#ibcon#[27=USB\r\n] 2006.173.22:41:25.49#ibcon#*before write, iclass 37, count 0 2006.173.22:41:25.49#ibcon#enter sib2, iclass 37, count 0 2006.173.22:41:25.49#ibcon#flushed, iclass 37, count 0 2006.173.22:41:25.49#ibcon#about to write, iclass 37, count 0 2006.173.22:41:25.49#ibcon#wrote, iclass 37, count 0 2006.173.22:41:25.49#ibcon#about to read 3, iclass 37, count 0 2006.173.22:41:25.52#ibcon#read 3, iclass 37, count 0 2006.173.22:41:25.52#ibcon#about to read 4, iclass 37, count 0 2006.173.22:41:25.52#ibcon#read 4, iclass 37, count 0 2006.173.22:41:25.52#ibcon#about to read 5, iclass 37, count 0 2006.173.22:41:25.52#ibcon#read 5, iclass 37, count 0 2006.173.22:41:25.52#ibcon#about to read 6, iclass 37, count 0 2006.173.22:41:25.52#ibcon#read 6, iclass 37, count 0 2006.173.22:41:25.52#ibcon#end of sib2, iclass 37, count 0 2006.173.22:41:25.52#ibcon#*after write, iclass 37, count 0 2006.173.22:41:25.52#ibcon#*before return 0, iclass 37, count 0 2006.173.22:41:25.52#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.22:41:25.52#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.173.22:41:25.52#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.22:41:25.52#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.22:41:25.52$vck44/vblo=3,649.99 2006.173.22:41:25.52#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.22:41:25.52#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.22:41:25.52#ibcon#ireg 17 cls_cnt 0 2006.173.22:41:25.52#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.22:41:25.52#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.22:41:25.52#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.22:41:25.52#ibcon#enter wrdev, iclass 39, count 0 2006.173.22:41:25.52#ibcon#first serial, iclass 39, count 0 2006.173.22:41:25.52#ibcon#enter sib2, iclass 39, count 0 2006.173.22:41:25.52#ibcon#flushed, iclass 39, count 0 2006.173.22:41:25.52#ibcon#about to write, iclass 39, count 0 2006.173.22:41:25.52#ibcon#wrote, iclass 39, count 0 2006.173.22:41:25.52#ibcon#about to read 3, iclass 39, count 0 2006.173.22:41:25.54#ibcon#read 3, iclass 39, count 0 2006.173.22:41:25.54#ibcon#about to read 4, iclass 39, count 0 2006.173.22:41:25.54#ibcon#read 4, iclass 39, count 0 2006.173.22:41:25.54#ibcon#about to read 5, iclass 39, count 0 2006.173.22:41:25.54#ibcon#read 5, iclass 39, count 0 2006.173.22:41:25.54#ibcon#about to read 6, iclass 39, count 0 2006.173.22:41:25.54#ibcon#read 6, iclass 39, count 0 2006.173.22:41:25.54#ibcon#end of sib2, iclass 39, count 0 2006.173.22:41:25.54#ibcon#*mode == 0, iclass 39, count 0 2006.173.22:41:25.54#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.22:41:25.54#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.22:41:25.54#ibcon#*before write, iclass 39, count 0 2006.173.22:41:25.54#ibcon#enter sib2, iclass 39, count 0 2006.173.22:41:25.54#ibcon#flushed, iclass 39, count 0 2006.173.22:41:25.54#ibcon#about to write, iclass 39, count 0 2006.173.22:41:25.54#ibcon#wrote, iclass 39, count 0 2006.173.22:41:25.54#ibcon#about to read 3, iclass 39, count 0 2006.173.22:41:25.58#ibcon#read 3, iclass 39, count 0 2006.173.22:41:25.58#ibcon#about to read 4, iclass 39, count 0 2006.173.22:41:25.58#ibcon#read 4, iclass 39, count 0 2006.173.22:41:25.58#ibcon#about to read 5, iclass 39, count 0 2006.173.22:41:25.58#ibcon#read 5, iclass 39, count 0 2006.173.22:41:25.58#ibcon#about to read 6, iclass 39, count 0 2006.173.22:41:25.58#ibcon#read 6, iclass 39, count 0 2006.173.22:41:25.58#ibcon#end of sib2, iclass 39, count 0 2006.173.22:41:25.58#ibcon#*after write, iclass 39, count 0 2006.173.22:41:25.58#ibcon#*before return 0, iclass 39, count 0 2006.173.22:41:25.58#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.22:41:25.58#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.22:41:25.58#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.22:41:25.58#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.22:41:25.58$vck44/vb=3,4 2006.173.22:41:25.58#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.22:41:25.58#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.22:41:25.58#ibcon#ireg 11 cls_cnt 2 2006.173.22:41:25.58#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.22:41:25.64#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.22:41:25.64#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.22:41:25.64#ibcon#enter wrdev, iclass 3, count 2 2006.173.22:41:25.64#ibcon#first serial, iclass 3, count 2 2006.173.22:41:25.64#ibcon#enter sib2, iclass 3, count 2 2006.173.22:41:25.64#ibcon#flushed, iclass 3, count 2 2006.173.22:41:25.64#ibcon#about to write, iclass 3, count 2 2006.173.22:41:25.64#ibcon#wrote, iclass 3, count 2 2006.173.22:41:25.64#ibcon#about to read 3, iclass 3, count 2 2006.173.22:41:25.66#ibcon#read 3, iclass 3, count 2 2006.173.22:41:25.66#ibcon#about to read 4, iclass 3, count 2 2006.173.22:41:25.66#ibcon#read 4, iclass 3, count 2 2006.173.22:41:25.66#ibcon#about to read 5, iclass 3, count 2 2006.173.22:41:25.66#ibcon#read 5, iclass 3, count 2 2006.173.22:41:25.66#ibcon#about to read 6, iclass 3, count 2 2006.173.22:41:25.66#ibcon#read 6, iclass 3, count 2 2006.173.22:41:25.66#ibcon#end of sib2, iclass 3, count 2 2006.173.22:41:25.66#ibcon#*mode == 0, iclass 3, count 2 2006.173.22:41:25.66#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.22:41:25.66#ibcon#[27=AT03-04\r\n] 2006.173.22:41:25.66#ibcon#*before write, iclass 3, count 2 2006.173.22:41:25.66#ibcon#enter sib2, iclass 3, count 2 2006.173.22:41:25.66#ibcon#flushed, iclass 3, count 2 2006.173.22:41:25.66#ibcon#about to write, iclass 3, count 2 2006.173.22:41:25.66#ibcon#wrote, iclass 3, count 2 2006.173.22:41:25.66#ibcon#about to read 3, iclass 3, count 2 2006.173.22:41:25.69#ibcon#read 3, iclass 3, count 2 2006.173.22:41:25.69#ibcon#about to read 4, iclass 3, count 2 2006.173.22:41:25.69#ibcon#read 4, iclass 3, count 2 2006.173.22:41:25.69#ibcon#about to read 5, iclass 3, count 2 2006.173.22:41:25.69#ibcon#read 5, iclass 3, count 2 2006.173.22:41:25.69#ibcon#about to read 6, iclass 3, count 2 2006.173.22:41:25.69#ibcon#read 6, iclass 3, count 2 2006.173.22:41:25.69#ibcon#end of sib2, iclass 3, count 2 2006.173.22:41:25.69#ibcon#*after write, iclass 3, count 2 2006.173.22:41:25.69#ibcon#*before return 0, iclass 3, count 2 2006.173.22:41:25.69#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.22:41:25.69#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.22:41:25.69#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.22:41:25.69#ibcon#ireg 7 cls_cnt 0 2006.173.22:41:25.69#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.22:41:25.81#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.22:41:25.81#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.22:41:25.81#ibcon#enter wrdev, iclass 3, count 0 2006.173.22:41:25.81#ibcon#first serial, iclass 3, count 0 2006.173.22:41:25.81#ibcon#enter sib2, iclass 3, count 0 2006.173.22:41:25.81#ibcon#flushed, iclass 3, count 0 2006.173.22:41:25.81#ibcon#about to write, iclass 3, count 0 2006.173.22:41:25.81#ibcon#wrote, iclass 3, count 0 2006.173.22:41:25.81#ibcon#about to read 3, iclass 3, count 0 2006.173.22:41:25.83#ibcon#read 3, iclass 3, count 0 2006.173.22:41:25.83#ibcon#about to read 4, iclass 3, count 0 2006.173.22:41:25.83#ibcon#read 4, iclass 3, count 0 2006.173.22:41:25.83#ibcon#about to read 5, iclass 3, count 0 2006.173.22:41:25.83#ibcon#read 5, iclass 3, count 0 2006.173.22:41:25.83#ibcon#about to read 6, iclass 3, count 0 2006.173.22:41:25.83#ibcon#read 6, iclass 3, count 0 2006.173.22:41:25.83#ibcon#end of sib2, iclass 3, count 0 2006.173.22:41:25.83#ibcon#*mode == 0, iclass 3, count 0 2006.173.22:41:25.83#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.22:41:25.83#ibcon#[27=USB\r\n] 2006.173.22:41:25.83#ibcon#*before write, iclass 3, count 0 2006.173.22:41:25.83#ibcon#enter sib2, iclass 3, count 0 2006.173.22:41:25.83#ibcon#flushed, iclass 3, count 0 2006.173.22:41:25.83#ibcon#about to write, iclass 3, count 0 2006.173.22:41:25.83#ibcon#wrote, iclass 3, count 0 2006.173.22:41:25.83#ibcon#about to read 3, iclass 3, count 0 2006.173.22:41:25.86#ibcon#read 3, iclass 3, count 0 2006.173.22:41:25.86#ibcon#about to read 4, iclass 3, count 0 2006.173.22:41:25.86#ibcon#read 4, iclass 3, count 0 2006.173.22:41:25.86#ibcon#about to read 5, iclass 3, count 0 2006.173.22:41:25.86#ibcon#read 5, iclass 3, count 0 2006.173.22:41:25.86#ibcon#about to read 6, iclass 3, count 0 2006.173.22:41:25.86#ibcon#read 6, iclass 3, count 0 2006.173.22:41:25.86#ibcon#end of sib2, iclass 3, count 0 2006.173.22:41:25.86#ibcon#*after write, iclass 3, count 0 2006.173.22:41:25.86#ibcon#*before return 0, iclass 3, count 0 2006.173.22:41:25.86#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.22:41:25.86#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.22:41:25.86#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.22:41:25.86#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.22:41:25.86$vck44/vblo=4,679.99 2006.173.22:41:25.86#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.22:41:25.86#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.22:41:25.86#ibcon#ireg 17 cls_cnt 0 2006.173.22:41:25.86#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.22:41:25.86#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.22:41:25.86#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.22:41:25.86#ibcon#enter wrdev, iclass 5, count 0 2006.173.22:41:25.86#ibcon#first serial, iclass 5, count 0 2006.173.22:41:25.86#ibcon#enter sib2, iclass 5, count 0 2006.173.22:41:25.86#ibcon#flushed, iclass 5, count 0 2006.173.22:41:25.86#ibcon#about to write, iclass 5, count 0 2006.173.22:41:25.86#ibcon#wrote, iclass 5, count 0 2006.173.22:41:25.86#ibcon#about to read 3, iclass 5, count 0 2006.173.22:41:25.88#ibcon#read 3, iclass 5, count 0 2006.173.22:41:25.88#ibcon#about to read 4, iclass 5, count 0 2006.173.22:41:25.88#ibcon#read 4, iclass 5, count 0 2006.173.22:41:25.88#ibcon#about to read 5, iclass 5, count 0 2006.173.22:41:25.88#ibcon#read 5, iclass 5, count 0 2006.173.22:41:25.88#ibcon#about to read 6, iclass 5, count 0 2006.173.22:41:25.88#ibcon#read 6, iclass 5, count 0 2006.173.22:41:25.88#ibcon#end of sib2, iclass 5, count 0 2006.173.22:41:25.88#ibcon#*mode == 0, iclass 5, count 0 2006.173.22:41:25.88#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.22:41:25.88#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.22:41:25.88#ibcon#*before write, iclass 5, count 0 2006.173.22:41:25.88#ibcon#enter sib2, iclass 5, count 0 2006.173.22:41:25.88#ibcon#flushed, iclass 5, count 0 2006.173.22:41:25.88#ibcon#about to write, iclass 5, count 0 2006.173.22:41:25.88#ibcon#wrote, iclass 5, count 0 2006.173.22:41:25.88#ibcon#about to read 3, iclass 5, count 0 2006.173.22:41:25.92#ibcon#read 3, iclass 5, count 0 2006.173.22:41:25.92#ibcon#about to read 4, iclass 5, count 0 2006.173.22:41:25.92#ibcon#read 4, iclass 5, count 0 2006.173.22:41:25.92#ibcon#about to read 5, iclass 5, count 0 2006.173.22:41:25.92#ibcon#read 5, iclass 5, count 0 2006.173.22:41:25.92#ibcon#about to read 6, iclass 5, count 0 2006.173.22:41:25.92#ibcon#read 6, iclass 5, count 0 2006.173.22:41:25.92#ibcon#end of sib2, iclass 5, count 0 2006.173.22:41:25.92#ibcon#*after write, iclass 5, count 0 2006.173.22:41:25.92#ibcon#*before return 0, iclass 5, count 0 2006.173.22:41:25.92#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.22:41:25.92#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.22:41:25.92#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.22:41:25.92#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.22:41:25.92$vck44/vb=4,4 2006.173.22:41:25.92#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.173.22:41:25.92#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.173.22:41:25.92#ibcon#ireg 11 cls_cnt 2 2006.173.22:41:25.92#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.22:41:25.98#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.22:41:25.98#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.22:41:25.98#ibcon#enter wrdev, iclass 7, count 2 2006.173.22:41:25.98#ibcon#first serial, iclass 7, count 2 2006.173.22:41:25.98#ibcon#enter sib2, iclass 7, count 2 2006.173.22:41:25.98#ibcon#flushed, iclass 7, count 2 2006.173.22:41:25.98#ibcon#about to write, iclass 7, count 2 2006.173.22:41:25.98#ibcon#wrote, iclass 7, count 2 2006.173.22:41:25.98#ibcon#about to read 3, iclass 7, count 2 2006.173.22:41:26.00#ibcon#read 3, iclass 7, count 2 2006.173.22:41:26.00#ibcon#about to read 4, iclass 7, count 2 2006.173.22:41:26.00#ibcon#read 4, iclass 7, count 2 2006.173.22:41:26.00#ibcon#about to read 5, iclass 7, count 2 2006.173.22:41:26.00#ibcon#read 5, iclass 7, count 2 2006.173.22:41:26.00#ibcon#about to read 6, iclass 7, count 2 2006.173.22:41:26.00#ibcon#read 6, iclass 7, count 2 2006.173.22:41:26.00#ibcon#end of sib2, iclass 7, count 2 2006.173.22:41:26.00#ibcon#*mode == 0, iclass 7, count 2 2006.173.22:41:26.00#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.173.22:41:26.00#ibcon#[27=AT04-04\r\n] 2006.173.22:41:26.00#ibcon#*before write, iclass 7, count 2 2006.173.22:41:26.00#ibcon#enter sib2, iclass 7, count 2 2006.173.22:41:26.00#ibcon#flushed, iclass 7, count 2 2006.173.22:41:26.00#ibcon#about to write, iclass 7, count 2 2006.173.22:41:26.00#ibcon#wrote, iclass 7, count 2 2006.173.22:41:26.00#ibcon#about to read 3, iclass 7, count 2 2006.173.22:41:26.03#ibcon#read 3, iclass 7, count 2 2006.173.22:41:26.03#ibcon#about to read 4, iclass 7, count 2 2006.173.22:41:26.03#ibcon#read 4, iclass 7, count 2 2006.173.22:41:26.03#ibcon#about to read 5, iclass 7, count 2 2006.173.22:41:26.03#ibcon#read 5, iclass 7, count 2 2006.173.22:41:26.03#ibcon#about to read 6, iclass 7, count 2 2006.173.22:41:26.03#ibcon#read 6, iclass 7, count 2 2006.173.22:41:26.03#ibcon#end of sib2, iclass 7, count 2 2006.173.22:41:26.03#ibcon#*after write, iclass 7, count 2 2006.173.22:41:26.03#ibcon#*before return 0, iclass 7, count 2 2006.173.22:41:26.03#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.22:41:26.03#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.173.22:41:26.03#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.173.22:41:26.03#ibcon#ireg 7 cls_cnt 0 2006.173.22:41:26.03#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.22:41:26.15#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.22:41:26.15#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.22:41:26.15#ibcon#enter wrdev, iclass 7, count 0 2006.173.22:41:26.15#ibcon#first serial, iclass 7, count 0 2006.173.22:41:26.15#ibcon#enter sib2, iclass 7, count 0 2006.173.22:41:26.15#ibcon#flushed, iclass 7, count 0 2006.173.22:41:26.15#ibcon#about to write, iclass 7, count 0 2006.173.22:41:26.15#ibcon#wrote, iclass 7, count 0 2006.173.22:41:26.15#ibcon#about to read 3, iclass 7, count 0 2006.173.22:41:26.17#ibcon#read 3, iclass 7, count 0 2006.173.22:41:26.17#ibcon#about to read 4, iclass 7, count 0 2006.173.22:41:26.17#ibcon#read 4, iclass 7, count 0 2006.173.22:41:26.17#ibcon#about to read 5, iclass 7, count 0 2006.173.22:41:26.17#ibcon#read 5, iclass 7, count 0 2006.173.22:41:26.17#ibcon#about to read 6, iclass 7, count 0 2006.173.22:41:26.17#ibcon#read 6, iclass 7, count 0 2006.173.22:41:26.17#ibcon#end of sib2, iclass 7, count 0 2006.173.22:41:26.17#ibcon#*mode == 0, iclass 7, count 0 2006.173.22:41:26.17#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.22:41:26.17#ibcon#[27=USB\r\n] 2006.173.22:41:26.17#ibcon#*before write, iclass 7, count 0 2006.173.22:41:26.17#ibcon#enter sib2, iclass 7, count 0 2006.173.22:41:26.17#ibcon#flushed, iclass 7, count 0 2006.173.22:41:26.17#ibcon#about to write, iclass 7, count 0 2006.173.22:41:26.17#ibcon#wrote, iclass 7, count 0 2006.173.22:41:26.17#ibcon#about to read 3, iclass 7, count 0 2006.173.22:41:26.20#ibcon#read 3, iclass 7, count 0 2006.173.22:41:26.20#ibcon#about to read 4, iclass 7, count 0 2006.173.22:41:26.20#ibcon#read 4, iclass 7, count 0 2006.173.22:41:26.20#ibcon#about to read 5, iclass 7, count 0 2006.173.22:41:26.20#ibcon#read 5, iclass 7, count 0 2006.173.22:41:26.20#ibcon#about to read 6, iclass 7, count 0 2006.173.22:41:26.20#ibcon#read 6, iclass 7, count 0 2006.173.22:41:26.20#ibcon#end of sib2, iclass 7, count 0 2006.173.22:41:26.20#ibcon#*after write, iclass 7, count 0 2006.173.22:41:26.20#ibcon#*before return 0, iclass 7, count 0 2006.173.22:41:26.20#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.22:41:26.20#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.173.22:41:26.20#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.22:41:26.20#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.22:41:26.20$vck44/vblo=5,709.99 2006.173.22:41:26.20#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.22:41:26.20#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.22:41:26.20#ibcon#ireg 17 cls_cnt 0 2006.173.22:41:26.20#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.22:41:26.20#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.22:41:26.20#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.22:41:26.20#ibcon#enter wrdev, iclass 11, count 0 2006.173.22:41:26.20#ibcon#first serial, iclass 11, count 0 2006.173.22:41:26.20#ibcon#enter sib2, iclass 11, count 0 2006.173.22:41:26.20#ibcon#flushed, iclass 11, count 0 2006.173.22:41:26.20#ibcon#about to write, iclass 11, count 0 2006.173.22:41:26.20#ibcon#wrote, iclass 11, count 0 2006.173.22:41:26.20#ibcon#about to read 3, iclass 11, count 0 2006.173.22:41:26.22#ibcon#read 3, iclass 11, count 0 2006.173.22:41:26.22#ibcon#about to read 4, iclass 11, count 0 2006.173.22:41:26.22#ibcon#read 4, iclass 11, count 0 2006.173.22:41:26.22#ibcon#about to read 5, iclass 11, count 0 2006.173.22:41:26.22#ibcon#read 5, iclass 11, count 0 2006.173.22:41:26.22#ibcon#about to read 6, iclass 11, count 0 2006.173.22:41:26.22#ibcon#read 6, iclass 11, count 0 2006.173.22:41:26.22#ibcon#end of sib2, iclass 11, count 0 2006.173.22:41:26.22#ibcon#*mode == 0, iclass 11, count 0 2006.173.22:41:26.22#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.22:41:26.22#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.22:41:26.22#ibcon#*before write, iclass 11, count 0 2006.173.22:41:26.22#ibcon#enter sib2, iclass 11, count 0 2006.173.22:41:26.22#ibcon#flushed, iclass 11, count 0 2006.173.22:41:26.22#ibcon#about to write, iclass 11, count 0 2006.173.22:41:26.22#ibcon#wrote, iclass 11, count 0 2006.173.22:41:26.22#ibcon#about to read 3, iclass 11, count 0 2006.173.22:41:26.26#ibcon#read 3, iclass 11, count 0 2006.173.22:41:26.26#ibcon#about to read 4, iclass 11, count 0 2006.173.22:41:26.26#ibcon#read 4, iclass 11, count 0 2006.173.22:41:26.26#ibcon#about to read 5, iclass 11, count 0 2006.173.22:41:26.26#ibcon#read 5, iclass 11, count 0 2006.173.22:41:26.26#ibcon#about to read 6, iclass 11, count 0 2006.173.22:41:26.26#ibcon#read 6, iclass 11, count 0 2006.173.22:41:26.26#ibcon#end of sib2, iclass 11, count 0 2006.173.22:41:26.26#ibcon#*after write, iclass 11, count 0 2006.173.22:41:26.26#ibcon#*before return 0, iclass 11, count 0 2006.173.22:41:26.26#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.22:41:26.26#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.22:41:26.26#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.22:41:26.26#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.22:41:26.26$vck44/vb=5,4 2006.173.22:41:26.26#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.173.22:41:26.26#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.173.22:41:26.26#ibcon#ireg 11 cls_cnt 2 2006.173.22:41:26.26#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.22:41:26.32#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.22:41:26.32#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.22:41:26.32#ibcon#enter wrdev, iclass 13, count 2 2006.173.22:41:26.32#ibcon#first serial, iclass 13, count 2 2006.173.22:41:26.32#ibcon#enter sib2, iclass 13, count 2 2006.173.22:41:26.32#ibcon#flushed, iclass 13, count 2 2006.173.22:41:26.32#ibcon#about to write, iclass 13, count 2 2006.173.22:41:26.32#ibcon#wrote, iclass 13, count 2 2006.173.22:41:26.32#ibcon#about to read 3, iclass 13, count 2 2006.173.22:41:26.34#ibcon#read 3, iclass 13, count 2 2006.173.22:41:26.34#ibcon#about to read 4, iclass 13, count 2 2006.173.22:41:26.34#ibcon#read 4, iclass 13, count 2 2006.173.22:41:26.34#ibcon#about to read 5, iclass 13, count 2 2006.173.22:41:26.34#ibcon#read 5, iclass 13, count 2 2006.173.22:41:26.34#ibcon#about to read 6, iclass 13, count 2 2006.173.22:41:26.34#ibcon#read 6, iclass 13, count 2 2006.173.22:41:26.34#ibcon#end of sib2, iclass 13, count 2 2006.173.22:41:26.34#ibcon#*mode == 0, iclass 13, count 2 2006.173.22:41:26.34#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.173.22:41:26.34#ibcon#[27=AT05-04\r\n] 2006.173.22:41:26.34#ibcon#*before write, iclass 13, count 2 2006.173.22:41:26.34#ibcon#enter sib2, iclass 13, count 2 2006.173.22:41:26.34#ibcon#flushed, iclass 13, count 2 2006.173.22:41:26.34#ibcon#about to write, iclass 13, count 2 2006.173.22:41:26.34#ibcon#wrote, iclass 13, count 2 2006.173.22:41:26.34#ibcon#about to read 3, iclass 13, count 2 2006.173.22:41:26.37#ibcon#read 3, iclass 13, count 2 2006.173.22:41:26.37#ibcon#about to read 4, iclass 13, count 2 2006.173.22:41:26.37#ibcon#read 4, iclass 13, count 2 2006.173.22:41:26.37#ibcon#about to read 5, iclass 13, count 2 2006.173.22:41:26.37#ibcon#read 5, iclass 13, count 2 2006.173.22:41:26.37#ibcon#about to read 6, iclass 13, count 2 2006.173.22:41:26.37#ibcon#read 6, iclass 13, count 2 2006.173.22:41:26.37#ibcon#end of sib2, iclass 13, count 2 2006.173.22:41:26.37#ibcon#*after write, iclass 13, count 2 2006.173.22:41:26.37#ibcon#*before return 0, iclass 13, count 2 2006.173.22:41:26.37#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.22:41:26.37#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.173.22:41:26.37#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.173.22:41:26.37#ibcon#ireg 7 cls_cnt 0 2006.173.22:41:26.37#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.22:41:26.49#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.22:41:26.49#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.22:41:26.49#ibcon#enter wrdev, iclass 13, count 0 2006.173.22:41:26.49#ibcon#first serial, iclass 13, count 0 2006.173.22:41:26.49#ibcon#enter sib2, iclass 13, count 0 2006.173.22:41:26.49#ibcon#flushed, iclass 13, count 0 2006.173.22:41:26.49#ibcon#about to write, iclass 13, count 0 2006.173.22:41:26.49#ibcon#wrote, iclass 13, count 0 2006.173.22:41:26.49#ibcon#about to read 3, iclass 13, count 0 2006.173.22:41:26.51#ibcon#read 3, iclass 13, count 0 2006.173.22:41:26.51#ibcon#about to read 4, iclass 13, count 0 2006.173.22:41:26.51#ibcon#read 4, iclass 13, count 0 2006.173.22:41:26.51#ibcon#about to read 5, iclass 13, count 0 2006.173.22:41:26.51#ibcon#read 5, iclass 13, count 0 2006.173.22:41:26.51#ibcon#about to read 6, iclass 13, count 0 2006.173.22:41:26.51#ibcon#read 6, iclass 13, count 0 2006.173.22:41:26.51#ibcon#end of sib2, iclass 13, count 0 2006.173.22:41:26.51#ibcon#*mode == 0, iclass 13, count 0 2006.173.22:41:26.51#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.22:41:26.51#ibcon#[27=USB\r\n] 2006.173.22:41:26.51#ibcon#*before write, iclass 13, count 0 2006.173.22:41:26.51#ibcon#enter sib2, iclass 13, count 0 2006.173.22:41:26.51#ibcon#flushed, iclass 13, count 0 2006.173.22:41:26.51#ibcon#about to write, iclass 13, count 0 2006.173.22:41:26.51#ibcon#wrote, iclass 13, count 0 2006.173.22:41:26.51#ibcon#about to read 3, iclass 13, count 0 2006.173.22:41:26.54#ibcon#read 3, iclass 13, count 0 2006.173.22:41:26.54#ibcon#about to read 4, iclass 13, count 0 2006.173.22:41:26.54#ibcon#read 4, iclass 13, count 0 2006.173.22:41:26.54#ibcon#about to read 5, iclass 13, count 0 2006.173.22:41:26.54#ibcon#read 5, iclass 13, count 0 2006.173.22:41:26.54#ibcon#about to read 6, iclass 13, count 0 2006.173.22:41:26.54#ibcon#read 6, iclass 13, count 0 2006.173.22:41:26.54#ibcon#end of sib2, iclass 13, count 0 2006.173.22:41:26.54#ibcon#*after write, iclass 13, count 0 2006.173.22:41:26.54#ibcon#*before return 0, iclass 13, count 0 2006.173.22:41:26.54#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.22:41:26.54#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.173.22:41:26.54#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.22:41:26.54#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.22:41:26.54$vck44/vblo=6,719.99 2006.173.22:41:26.54#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.22:41:26.54#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.22:41:26.54#ibcon#ireg 17 cls_cnt 0 2006.173.22:41:26.54#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.22:41:26.54#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.22:41:26.54#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.22:41:26.54#ibcon#enter wrdev, iclass 15, count 0 2006.173.22:41:26.54#ibcon#first serial, iclass 15, count 0 2006.173.22:41:26.54#ibcon#enter sib2, iclass 15, count 0 2006.173.22:41:26.54#ibcon#flushed, iclass 15, count 0 2006.173.22:41:26.54#ibcon#about to write, iclass 15, count 0 2006.173.22:41:26.54#ibcon#wrote, iclass 15, count 0 2006.173.22:41:26.54#ibcon#about to read 3, iclass 15, count 0 2006.173.22:41:26.56#ibcon#read 3, iclass 15, count 0 2006.173.22:41:26.56#ibcon#about to read 4, iclass 15, count 0 2006.173.22:41:26.56#ibcon#read 4, iclass 15, count 0 2006.173.22:41:26.56#ibcon#about to read 5, iclass 15, count 0 2006.173.22:41:26.56#ibcon#read 5, iclass 15, count 0 2006.173.22:41:26.56#ibcon#about to read 6, iclass 15, count 0 2006.173.22:41:26.56#ibcon#read 6, iclass 15, count 0 2006.173.22:41:26.56#ibcon#end of sib2, iclass 15, count 0 2006.173.22:41:26.56#ibcon#*mode == 0, iclass 15, count 0 2006.173.22:41:26.56#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.22:41:26.56#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.22:41:26.56#ibcon#*before write, iclass 15, count 0 2006.173.22:41:26.56#ibcon#enter sib2, iclass 15, count 0 2006.173.22:41:26.56#ibcon#flushed, iclass 15, count 0 2006.173.22:41:26.56#ibcon#about to write, iclass 15, count 0 2006.173.22:41:26.56#ibcon#wrote, iclass 15, count 0 2006.173.22:41:26.56#ibcon#about to read 3, iclass 15, count 0 2006.173.22:41:26.60#ibcon#read 3, iclass 15, count 0 2006.173.22:41:26.60#ibcon#about to read 4, iclass 15, count 0 2006.173.22:41:26.60#ibcon#read 4, iclass 15, count 0 2006.173.22:41:26.60#ibcon#about to read 5, iclass 15, count 0 2006.173.22:41:26.60#ibcon#read 5, iclass 15, count 0 2006.173.22:41:26.60#ibcon#about to read 6, iclass 15, count 0 2006.173.22:41:26.60#ibcon#read 6, iclass 15, count 0 2006.173.22:41:26.60#ibcon#end of sib2, iclass 15, count 0 2006.173.22:41:26.60#ibcon#*after write, iclass 15, count 0 2006.173.22:41:26.60#ibcon#*before return 0, iclass 15, count 0 2006.173.22:41:26.60#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.22:41:26.60#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.22:41:26.60#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.22:41:26.60#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.22:41:26.60$vck44/vb=6,4 2006.173.22:41:26.60#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.22:41:26.60#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.22:41:26.60#ibcon#ireg 11 cls_cnt 2 2006.173.22:41:26.60#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.22:41:26.66#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.22:41:26.66#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.22:41:26.66#ibcon#enter wrdev, iclass 17, count 2 2006.173.22:41:26.66#ibcon#first serial, iclass 17, count 2 2006.173.22:41:26.66#ibcon#enter sib2, iclass 17, count 2 2006.173.22:41:26.66#ibcon#flushed, iclass 17, count 2 2006.173.22:41:26.66#ibcon#about to write, iclass 17, count 2 2006.173.22:41:26.66#ibcon#wrote, iclass 17, count 2 2006.173.22:41:26.66#ibcon#about to read 3, iclass 17, count 2 2006.173.22:41:26.68#ibcon#read 3, iclass 17, count 2 2006.173.22:41:26.68#ibcon#about to read 4, iclass 17, count 2 2006.173.22:41:26.68#ibcon#read 4, iclass 17, count 2 2006.173.22:41:26.68#ibcon#about to read 5, iclass 17, count 2 2006.173.22:41:26.68#ibcon#read 5, iclass 17, count 2 2006.173.22:41:26.68#ibcon#about to read 6, iclass 17, count 2 2006.173.22:41:26.68#ibcon#read 6, iclass 17, count 2 2006.173.22:41:26.68#ibcon#end of sib2, iclass 17, count 2 2006.173.22:41:26.68#ibcon#*mode == 0, iclass 17, count 2 2006.173.22:41:26.68#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.22:41:26.68#ibcon#[27=AT06-04\r\n] 2006.173.22:41:26.68#ibcon#*before write, iclass 17, count 2 2006.173.22:41:26.68#ibcon#enter sib2, iclass 17, count 2 2006.173.22:41:26.68#ibcon#flushed, iclass 17, count 2 2006.173.22:41:26.68#ibcon#about to write, iclass 17, count 2 2006.173.22:41:26.68#ibcon#wrote, iclass 17, count 2 2006.173.22:41:26.68#ibcon#about to read 3, iclass 17, count 2 2006.173.22:41:26.71#ibcon#read 3, iclass 17, count 2 2006.173.22:41:26.71#ibcon#about to read 4, iclass 17, count 2 2006.173.22:41:26.71#ibcon#read 4, iclass 17, count 2 2006.173.22:41:26.71#ibcon#about to read 5, iclass 17, count 2 2006.173.22:41:26.71#ibcon#read 5, iclass 17, count 2 2006.173.22:41:26.71#ibcon#about to read 6, iclass 17, count 2 2006.173.22:41:26.71#ibcon#read 6, iclass 17, count 2 2006.173.22:41:26.71#ibcon#end of sib2, iclass 17, count 2 2006.173.22:41:26.71#ibcon#*after write, iclass 17, count 2 2006.173.22:41:26.71#ibcon#*before return 0, iclass 17, count 2 2006.173.22:41:26.71#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.22:41:26.71#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.22:41:26.71#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.22:41:26.71#ibcon#ireg 7 cls_cnt 0 2006.173.22:41:26.71#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.22:41:26.83#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.22:41:26.83#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.22:41:26.83#ibcon#enter wrdev, iclass 17, count 0 2006.173.22:41:26.83#ibcon#first serial, iclass 17, count 0 2006.173.22:41:26.83#ibcon#enter sib2, iclass 17, count 0 2006.173.22:41:26.83#ibcon#flushed, iclass 17, count 0 2006.173.22:41:26.83#ibcon#about to write, iclass 17, count 0 2006.173.22:41:26.83#ibcon#wrote, iclass 17, count 0 2006.173.22:41:26.83#ibcon#about to read 3, iclass 17, count 0 2006.173.22:41:26.85#ibcon#read 3, iclass 17, count 0 2006.173.22:41:26.85#ibcon#about to read 4, iclass 17, count 0 2006.173.22:41:26.85#ibcon#read 4, iclass 17, count 0 2006.173.22:41:26.85#ibcon#about to read 5, iclass 17, count 0 2006.173.22:41:26.85#ibcon#read 5, iclass 17, count 0 2006.173.22:41:26.85#ibcon#about to read 6, iclass 17, count 0 2006.173.22:41:26.85#ibcon#read 6, iclass 17, count 0 2006.173.22:41:26.85#ibcon#end of sib2, iclass 17, count 0 2006.173.22:41:26.85#ibcon#*mode == 0, iclass 17, count 0 2006.173.22:41:26.85#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.22:41:26.85#ibcon#[27=USB\r\n] 2006.173.22:41:26.85#ibcon#*before write, iclass 17, count 0 2006.173.22:41:26.85#ibcon#enter sib2, iclass 17, count 0 2006.173.22:41:26.85#ibcon#flushed, iclass 17, count 0 2006.173.22:41:26.85#ibcon#about to write, iclass 17, count 0 2006.173.22:41:26.85#ibcon#wrote, iclass 17, count 0 2006.173.22:41:26.85#ibcon#about to read 3, iclass 17, count 0 2006.173.22:41:26.88#ibcon#read 3, iclass 17, count 0 2006.173.22:41:26.88#ibcon#about to read 4, iclass 17, count 0 2006.173.22:41:26.88#ibcon#read 4, iclass 17, count 0 2006.173.22:41:26.88#ibcon#about to read 5, iclass 17, count 0 2006.173.22:41:26.88#ibcon#read 5, iclass 17, count 0 2006.173.22:41:26.88#ibcon#about to read 6, iclass 17, count 0 2006.173.22:41:26.88#ibcon#read 6, iclass 17, count 0 2006.173.22:41:26.88#ibcon#end of sib2, iclass 17, count 0 2006.173.22:41:26.88#ibcon#*after write, iclass 17, count 0 2006.173.22:41:26.88#ibcon#*before return 0, iclass 17, count 0 2006.173.22:41:26.88#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.22:41:26.88#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.22:41:26.88#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.22:41:26.88#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.22:41:26.88$vck44/vblo=7,734.99 2006.173.22:41:26.88#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.22:41:26.88#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.22:41:26.88#ibcon#ireg 17 cls_cnt 0 2006.173.22:41:26.88#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.22:41:26.88#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.22:41:26.88#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.22:41:26.88#ibcon#enter wrdev, iclass 19, count 0 2006.173.22:41:26.88#ibcon#first serial, iclass 19, count 0 2006.173.22:41:26.88#ibcon#enter sib2, iclass 19, count 0 2006.173.22:41:26.88#ibcon#flushed, iclass 19, count 0 2006.173.22:41:26.88#ibcon#about to write, iclass 19, count 0 2006.173.22:41:26.88#ibcon#wrote, iclass 19, count 0 2006.173.22:41:26.88#ibcon#about to read 3, iclass 19, count 0 2006.173.22:41:26.90#ibcon#read 3, iclass 19, count 0 2006.173.22:41:26.90#ibcon#about to read 4, iclass 19, count 0 2006.173.22:41:26.90#ibcon#read 4, iclass 19, count 0 2006.173.22:41:26.90#ibcon#about to read 5, iclass 19, count 0 2006.173.22:41:26.90#ibcon#read 5, iclass 19, count 0 2006.173.22:41:26.90#ibcon#about to read 6, iclass 19, count 0 2006.173.22:41:26.90#ibcon#read 6, iclass 19, count 0 2006.173.22:41:26.90#ibcon#end of sib2, iclass 19, count 0 2006.173.22:41:26.90#ibcon#*mode == 0, iclass 19, count 0 2006.173.22:41:26.90#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.22:41:26.90#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.22:41:26.90#ibcon#*before write, iclass 19, count 0 2006.173.22:41:26.90#ibcon#enter sib2, iclass 19, count 0 2006.173.22:41:26.90#ibcon#flushed, iclass 19, count 0 2006.173.22:41:26.90#ibcon#about to write, iclass 19, count 0 2006.173.22:41:26.90#ibcon#wrote, iclass 19, count 0 2006.173.22:41:26.90#ibcon#about to read 3, iclass 19, count 0 2006.173.22:41:26.94#ibcon#read 3, iclass 19, count 0 2006.173.22:41:26.94#ibcon#about to read 4, iclass 19, count 0 2006.173.22:41:26.94#ibcon#read 4, iclass 19, count 0 2006.173.22:41:26.94#ibcon#about to read 5, iclass 19, count 0 2006.173.22:41:26.94#ibcon#read 5, iclass 19, count 0 2006.173.22:41:26.94#ibcon#about to read 6, iclass 19, count 0 2006.173.22:41:26.94#ibcon#read 6, iclass 19, count 0 2006.173.22:41:26.94#ibcon#end of sib2, iclass 19, count 0 2006.173.22:41:26.94#ibcon#*after write, iclass 19, count 0 2006.173.22:41:26.94#ibcon#*before return 0, iclass 19, count 0 2006.173.22:41:26.94#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.22:41:26.94#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.22:41:26.94#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.22:41:26.94#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.22:41:26.94$vck44/vb=7,4 2006.173.22:41:26.94#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.22:41:26.94#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.22:41:26.94#ibcon#ireg 11 cls_cnt 2 2006.173.22:41:26.94#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.22:41:27.00#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.22:41:27.00#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.22:41:27.00#ibcon#enter wrdev, iclass 21, count 2 2006.173.22:41:27.00#ibcon#first serial, iclass 21, count 2 2006.173.22:41:27.00#ibcon#enter sib2, iclass 21, count 2 2006.173.22:41:27.00#ibcon#flushed, iclass 21, count 2 2006.173.22:41:27.00#ibcon#about to write, iclass 21, count 2 2006.173.22:41:27.00#ibcon#wrote, iclass 21, count 2 2006.173.22:41:27.00#ibcon#about to read 3, iclass 21, count 2 2006.173.22:41:27.02#ibcon#read 3, iclass 21, count 2 2006.173.22:41:27.02#ibcon#about to read 4, iclass 21, count 2 2006.173.22:41:27.02#ibcon#read 4, iclass 21, count 2 2006.173.22:41:27.02#ibcon#about to read 5, iclass 21, count 2 2006.173.22:41:27.02#ibcon#read 5, iclass 21, count 2 2006.173.22:41:27.02#ibcon#about to read 6, iclass 21, count 2 2006.173.22:41:27.02#ibcon#read 6, iclass 21, count 2 2006.173.22:41:27.02#ibcon#end of sib2, iclass 21, count 2 2006.173.22:41:27.02#ibcon#*mode == 0, iclass 21, count 2 2006.173.22:41:27.02#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.22:41:27.02#ibcon#[27=AT07-04\r\n] 2006.173.22:41:27.02#ibcon#*before write, iclass 21, count 2 2006.173.22:41:27.02#ibcon#enter sib2, iclass 21, count 2 2006.173.22:41:27.02#ibcon#flushed, iclass 21, count 2 2006.173.22:41:27.02#ibcon#about to write, iclass 21, count 2 2006.173.22:41:27.02#ibcon#wrote, iclass 21, count 2 2006.173.22:41:27.02#ibcon#about to read 3, iclass 21, count 2 2006.173.22:41:27.05#ibcon#read 3, iclass 21, count 2 2006.173.22:41:27.05#ibcon#about to read 4, iclass 21, count 2 2006.173.22:41:27.05#ibcon#read 4, iclass 21, count 2 2006.173.22:41:27.05#ibcon#about to read 5, iclass 21, count 2 2006.173.22:41:27.05#ibcon#read 5, iclass 21, count 2 2006.173.22:41:27.05#ibcon#about to read 6, iclass 21, count 2 2006.173.22:41:27.05#ibcon#read 6, iclass 21, count 2 2006.173.22:41:27.05#ibcon#end of sib2, iclass 21, count 2 2006.173.22:41:27.05#ibcon#*after write, iclass 21, count 2 2006.173.22:41:27.05#ibcon#*before return 0, iclass 21, count 2 2006.173.22:41:27.05#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.22:41:27.05#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.22:41:27.05#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.22:41:27.05#ibcon#ireg 7 cls_cnt 0 2006.173.22:41:27.05#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.22:41:27.17#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.22:41:27.17#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.22:41:27.17#ibcon#enter wrdev, iclass 21, count 0 2006.173.22:41:27.17#ibcon#first serial, iclass 21, count 0 2006.173.22:41:27.17#ibcon#enter sib2, iclass 21, count 0 2006.173.22:41:27.17#ibcon#flushed, iclass 21, count 0 2006.173.22:41:27.17#ibcon#about to write, iclass 21, count 0 2006.173.22:41:27.17#ibcon#wrote, iclass 21, count 0 2006.173.22:41:27.17#ibcon#about to read 3, iclass 21, count 0 2006.173.22:41:27.19#ibcon#read 3, iclass 21, count 0 2006.173.22:41:27.19#ibcon#about to read 4, iclass 21, count 0 2006.173.22:41:27.19#ibcon#read 4, iclass 21, count 0 2006.173.22:41:27.19#ibcon#about to read 5, iclass 21, count 0 2006.173.22:41:27.19#ibcon#read 5, iclass 21, count 0 2006.173.22:41:27.19#ibcon#about to read 6, iclass 21, count 0 2006.173.22:41:27.19#ibcon#read 6, iclass 21, count 0 2006.173.22:41:27.19#ibcon#end of sib2, iclass 21, count 0 2006.173.22:41:27.19#ibcon#*mode == 0, iclass 21, count 0 2006.173.22:41:27.19#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.22:41:27.19#ibcon#[27=USB\r\n] 2006.173.22:41:27.19#ibcon#*before write, iclass 21, count 0 2006.173.22:41:27.19#ibcon#enter sib2, iclass 21, count 0 2006.173.22:41:27.19#ibcon#flushed, iclass 21, count 0 2006.173.22:41:27.19#ibcon#about to write, iclass 21, count 0 2006.173.22:41:27.19#ibcon#wrote, iclass 21, count 0 2006.173.22:41:27.19#ibcon#about to read 3, iclass 21, count 0 2006.173.22:41:27.22#ibcon#read 3, iclass 21, count 0 2006.173.22:41:27.22#ibcon#about to read 4, iclass 21, count 0 2006.173.22:41:27.22#ibcon#read 4, iclass 21, count 0 2006.173.22:41:27.22#ibcon#about to read 5, iclass 21, count 0 2006.173.22:41:27.22#ibcon#read 5, iclass 21, count 0 2006.173.22:41:27.22#ibcon#about to read 6, iclass 21, count 0 2006.173.22:41:27.22#ibcon#read 6, iclass 21, count 0 2006.173.22:41:27.22#ibcon#end of sib2, iclass 21, count 0 2006.173.22:41:27.22#ibcon#*after write, iclass 21, count 0 2006.173.22:41:27.22#ibcon#*before return 0, iclass 21, count 0 2006.173.22:41:27.22#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.22:41:27.22#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.22:41:27.22#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.22:41:27.22#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.22:41:27.22$vck44/vblo=8,744.99 2006.173.22:41:27.22#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.22:41:27.22#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.22:41:27.22#ibcon#ireg 17 cls_cnt 0 2006.173.22:41:27.22#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.22:41:27.22#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.22:41:27.22#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.22:41:27.22#ibcon#enter wrdev, iclass 23, count 0 2006.173.22:41:27.22#ibcon#first serial, iclass 23, count 0 2006.173.22:41:27.22#ibcon#enter sib2, iclass 23, count 0 2006.173.22:41:27.22#ibcon#flushed, iclass 23, count 0 2006.173.22:41:27.22#ibcon#about to write, iclass 23, count 0 2006.173.22:41:27.22#ibcon#wrote, iclass 23, count 0 2006.173.22:41:27.22#ibcon#about to read 3, iclass 23, count 0 2006.173.22:41:27.24#ibcon#read 3, iclass 23, count 0 2006.173.22:41:27.24#ibcon#about to read 4, iclass 23, count 0 2006.173.22:41:27.24#ibcon#read 4, iclass 23, count 0 2006.173.22:41:27.24#ibcon#about to read 5, iclass 23, count 0 2006.173.22:41:27.24#ibcon#read 5, iclass 23, count 0 2006.173.22:41:27.24#ibcon#about to read 6, iclass 23, count 0 2006.173.22:41:27.24#ibcon#read 6, iclass 23, count 0 2006.173.22:41:27.24#ibcon#end of sib2, iclass 23, count 0 2006.173.22:41:27.24#ibcon#*mode == 0, iclass 23, count 0 2006.173.22:41:27.24#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.22:41:27.24#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.22:41:27.24#ibcon#*before write, iclass 23, count 0 2006.173.22:41:27.24#ibcon#enter sib2, iclass 23, count 0 2006.173.22:41:27.24#ibcon#flushed, iclass 23, count 0 2006.173.22:41:27.24#ibcon#about to write, iclass 23, count 0 2006.173.22:41:27.24#ibcon#wrote, iclass 23, count 0 2006.173.22:41:27.24#ibcon#about to read 3, iclass 23, count 0 2006.173.22:41:27.28#ibcon#read 3, iclass 23, count 0 2006.173.22:41:27.28#ibcon#about to read 4, iclass 23, count 0 2006.173.22:41:27.28#ibcon#read 4, iclass 23, count 0 2006.173.22:41:27.28#ibcon#about to read 5, iclass 23, count 0 2006.173.22:41:27.28#ibcon#read 5, iclass 23, count 0 2006.173.22:41:27.28#ibcon#about to read 6, iclass 23, count 0 2006.173.22:41:27.28#ibcon#read 6, iclass 23, count 0 2006.173.22:41:27.28#ibcon#end of sib2, iclass 23, count 0 2006.173.22:41:27.28#ibcon#*after write, iclass 23, count 0 2006.173.22:41:27.28#ibcon#*before return 0, iclass 23, count 0 2006.173.22:41:27.28#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.22:41:27.28#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.22:41:27.28#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.22:41:27.28#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.22:41:27.28$vck44/vb=8,4 2006.173.22:41:27.28#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.22:41:27.28#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.22:41:27.28#ibcon#ireg 11 cls_cnt 2 2006.173.22:41:27.28#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.22:41:27.34#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.22:41:27.34#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.22:41:27.34#ibcon#enter wrdev, iclass 25, count 2 2006.173.22:41:27.34#ibcon#first serial, iclass 25, count 2 2006.173.22:41:27.34#ibcon#enter sib2, iclass 25, count 2 2006.173.22:41:27.34#ibcon#flushed, iclass 25, count 2 2006.173.22:41:27.34#ibcon#about to write, iclass 25, count 2 2006.173.22:41:27.34#ibcon#wrote, iclass 25, count 2 2006.173.22:41:27.34#ibcon#about to read 3, iclass 25, count 2 2006.173.22:41:27.36#ibcon#read 3, iclass 25, count 2 2006.173.22:41:27.36#ibcon#about to read 4, iclass 25, count 2 2006.173.22:41:27.36#ibcon#read 4, iclass 25, count 2 2006.173.22:41:27.36#ibcon#about to read 5, iclass 25, count 2 2006.173.22:41:27.36#ibcon#read 5, iclass 25, count 2 2006.173.22:41:27.36#ibcon#about to read 6, iclass 25, count 2 2006.173.22:41:27.36#ibcon#read 6, iclass 25, count 2 2006.173.22:41:27.36#ibcon#end of sib2, iclass 25, count 2 2006.173.22:41:27.36#ibcon#*mode == 0, iclass 25, count 2 2006.173.22:41:27.36#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.22:41:27.36#ibcon#[27=AT08-04\r\n] 2006.173.22:41:27.36#ibcon#*before write, iclass 25, count 2 2006.173.22:41:27.36#ibcon#enter sib2, iclass 25, count 2 2006.173.22:41:27.36#ibcon#flushed, iclass 25, count 2 2006.173.22:41:27.36#ibcon#about to write, iclass 25, count 2 2006.173.22:41:27.36#ibcon#wrote, iclass 25, count 2 2006.173.22:41:27.36#ibcon#about to read 3, iclass 25, count 2 2006.173.22:41:27.39#ibcon#read 3, iclass 25, count 2 2006.173.22:41:27.39#ibcon#about to read 4, iclass 25, count 2 2006.173.22:41:27.39#ibcon#read 4, iclass 25, count 2 2006.173.22:41:27.39#ibcon#about to read 5, iclass 25, count 2 2006.173.22:41:27.39#ibcon#read 5, iclass 25, count 2 2006.173.22:41:27.39#ibcon#about to read 6, iclass 25, count 2 2006.173.22:41:27.39#ibcon#read 6, iclass 25, count 2 2006.173.22:41:27.39#ibcon#end of sib2, iclass 25, count 2 2006.173.22:41:27.39#ibcon#*after write, iclass 25, count 2 2006.173.22:41:27.39#ibcon#*before return 0, iclass 25, count 2 2006.173.22:41:27.39#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.22:41:27.39#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.22:41:27.39#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.22:41:27.39#ibcon#ireg 7 cls_cnt 0 2006.173.22:41:27.39#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.22:41:27.51#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.22:41:27.51#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.22:41:27.51#ibcon#enter wrdev, iclass 25, count 0 2006.173.22:41:27.51#ibcon#first serial, iclass 25, count 0 2006.173.22:41:27.51#ibcon#enter sib2, iclass 25, count 0 2006.173.22:41:27.51#ibcon#flushed, iclass 25, count 0 2006.173.22:41:27.51#ibcon#about to write, iclass 25, count 0 2006.173.22:41:27.51#ibcon#wrote, iclass 25, count 0 2006.173.22:41:27.51#ibcon#about to read 3, iclass 25, count 0 2006.173.22:41:27.53#ibcon#read 3, iclass 25, count 0 2006.173.22:41:27.53#ibcon#about to read 4, iclass 25, count 0 2006.173.22:41:27.53#ibcon#read 4, iclass 25, count 0 2006.173.22:41:27.53#ibcon#about to read 5, iclass 25, count 0 2006.173.22:41:27.53#ibcon#read 5, iclass 25, count 0 2006.173.22:41:27.53#ibcon#about to read 6, iclass 25, count 0 2006.173.22:41:27.53#ibcon#read 6, iclass 25, count 0 2006.173.22:41:27.53#ibcon#end of sib2, iclass 25, count 0 2006.173.22:41:27.53#ibcon#*mode == 0, iclass 25, count 0 2006.173.22:41:27.53#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.22:41:27.53#ibcon#[27=USB\r\n] 2006.173.22:41:27.53#ibcon#*before write, iclass 25, count 0 2006.173.22:41:27.53#ibcon#enter sib2, iclass 25, count 0 2006.173.22:41:27.53#ibcon#flushed, iclass 25, count 0 2006.173.22:41:27.53#ibcon#about to write, iclass 25, count 0 2006.173.22:41:27.53#ibcon#wrote, iclass 25, count 0 2006.173.22:41:27.53#ibcon#about to read 3, iclass 25, count 0 2006.173.22:41:27.56#ibcon#read 3, iclass 25, count 0 2006.173.22:41:27.56#ibcon#about to read 4, iclass 25, count 0 2006.173.22:41:27.56#ibcon#read 4, iclass 25, count 0 2006.173.22:41:27.56#ibcon#about to read 5, iclass 25, count 0 2006.173.22:41:27.56#ibcon#read 5, iclass 25, count 0 2006.173.22:41:27.56#ibcon#about to read 6, iclass 25, count 0 2006.173.22:41:27.56#ibcon#read 6, iclass 25, count 0 2006.173.22:41:27.56#ibcon#end of sib2, iclass 25, count 0 2006.173.22:41:27.56#ibcon#*after write, iclass 25, count 0 2006.173.22:41:27.56#ibcon#*before return 0, iclass 25, count 0 2006.173.22:41:27.56#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.22:41:27.56#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.22:41:27.56#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.22:41:27.56#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.22:41:27.56$vck44/vabw=wide 2006.173.22:41:27.56#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.22:41:27.56#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.22:41:27.56#ibcon#ireg 8 cls_cnt 0 2006.173.22:41:27.56#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.22:41:27.56#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.22:41:27.56#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.22:41:27.56#ibcon#enter wrdev, iclass 27, count 0 2006.173.22:41:27.56#ibcon#first serial, iclass 27, count 0 2006.173.22:41:27.56#ibcon#enter sib2, iclass 27, count 0 2006.173.22:41:27.56#ibcon#flushed, iclass 27, count 0 2006.173.22:41:27.56#ibcon#about to write, iclass 27, count 0 2006.173.22:41:27.56#ibcon#wrote, iclass 27, count 0 2006.173.22:41:27.56#ibcon#about to read 3, iclass 27, count 0 2006.173.22:41:27.58#ibcon#read 3, iclass 27, count 0 2006.173.22:41:27.58#ibcon#about to read 4, iclass 27, count 0 2006.173.22:41:27.58#ibcon#read 4, iclass 27, count 0 2006.173.22:41:27.58#ibcon#about to read 5, iclass 27, count 0 2006.173.22:41:27.58#ibcon#read 5, iclass 27, count 0 2006.173.22:41:27.58#ibcon#about to read 6, iclass 27, count 0 2006.173.22:41:27.58#ibcon#read 6, iclass 27, count 0 2006.173.22:41:27.58#ibcon#end of sib2, iclass 27, count 0 2006.173.22:41:27.58#ibcon#*mode == 0, iclass 27, count 0 2006.173.22:41:27.58#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.22:41:27.58#ibcon#[25=BW32\r\n] 2006.173.22:41:27.58#ibcon#*before write, iclass 27, count 0 2006.173.22:41:27.58#ibcon#enter sib2, iclass 27, count 0 2006.173.22:41:27.58#ibcon#flushed, iclass 27, count 0 2006.173.22:41:27.58#ibcon#about to write, iclass 27, count 0 2006.173.22:41:27.58#ibcon#wrote, iclass 27, count 0 2006.173.22:41:27.58#ibcon#about to read 3, iclass 27, count 0 2006.173.22:41:27.61#ibcon#read 3, iclass 27, count 0 2006.173.22:41:27.61#ibcon#about to read 4, iclass 27, count 0 2006.173.22:41:27.61#ibcon#read 4, iclass 27, count 0 2006.173.22:41:27.61#ibcon#about to read 5, iclass 27, count 0 2006.173.22:41:27.61#ibcon#read 5, iclass 27, count 0 2006.173.22:41:27.61#ibcon#about to read 6, iclass 27, count 0 2006.173.22:41:27.61#ibcon#read 6, iclass 27, count 0 2006.173.22:41:27.61#ibcon#end of sib2, iclass 27, count 0 2006.173.22:41:27.61#ibcon#*after write, iclass 27, count 0 2006.173.22:41:27.61#ibcon#*before return 0, iclass 27, count 0 2006.173.22:41:27.61#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.22:41:27.61#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.22:41:27.61#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.22:41:27.61#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.22:41:27.61$vck44/vbbw=wide 2006.173.22:41:27.61#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.22:41:27.61#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.22:41:27.61#ibcon#ireg 8 cls_cnt 0 2006.173.22:41:27.61#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.22:41:27.68#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.22:41:27.68#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.22:41:27.68#ibcon#enter wrdev, iclass 29, count 0 2006.173.22:41:27.68#ibcon#first serial, iclass 29, count 0 2006.173.22:41:27.68#ibcon#enter sib2, iclass 29, count 0 2006.173.22:41:27.68#ibcon#flushed, iclass 29, count 0 2006.173.22:41:27.68#ibcon#about to write, iclass 29, count 0 2006.173.22:41:27.68#ibcon#wrote, iclass 29, count 0 2006.173.22:41:27.68#ibcon#about to read 3, iclass 29, count 0 2006.173.22:41:27.70#ibcon#read 3, iclass 29, count 0 2006.173.22:41:27.70#ibcon#about to read 4, iclass 29, count 0 2006.173.22:41:27.70#ibcon#read 4, iclass 29, count 0 2006.173.22:41:27.70#ibcon#about to read 5, iclass 29, count 0 2006.173.22:41:27.70#ibcon#read 5, iclass 29, count 0 2006.173.22:41:27.70#ibcon#about to read 6, iclass 29, count 0 2006.173.22:41:27.70#ibcon#read 6, iclass 29, count 0 2006.173.22:41:27.70#ibcon#end of sib2, iclass 29, count 0 2006.173.22:41:27.70#ibcon#*mode == 0, iclass 29, count 0 2006.173.22:41:27.70#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.22:41:27.70#ibcon#[27=BW32\r\n] 2006.173.22:41:27.70#ibcon#*before write, iclass 29, count 0 2006.173.22:41:27.70#ibcon#enter sib2, iclass 29, count 0 2006.173.22:41:27.70#ibcon#flushed, iclass 29, count 0 2006.173.22:41:27.70#ibcon#about to write, iclass 29, count 0 2006.173.22:41:27.70#ibcon#wrote, iclass 29, count 0 2006.173.22:41:27.70#ibcon#about to read 3, iclass 29, count 0 2006.173.22:41:27.73#ibcon#read 3, iclass 29, count 0 2006.173.22:41:27.73#ibcon#about to read 4, iclass 29, count 0 2006.173.22:41:27.73#ibcon#read 4, iclass 29, count 0 2006.173.22:41:27.73#ibcon#about to read 5, iclass 29, count 0 2006.173.22:41:27.73#ibcon#read 5, iclass 29, count 0 2006.173.22:41:27.73#ibcon#about to read 6, iclass 29, count 0 2006.173.22:41:27.73#ibcon#read 6, iclass 29, count 0 2006.173.22:41:27.73#ibcon#end of sib2, iclass 29, count 0 2006.173.22:41:27.73#ibcon#*after write, iclass 29, count 0 2006.173.22:41:27.73#ibcon#*before return 0, iclass 29, count 0 2006.173.22:41:27.73#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.22:41:27.73#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.22:41:27.73#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.22:41:27.73#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.22:41:27.73$setupk4/ifdk4 2006.173.22:41:27.73$ifdk4/lo= 2006.173.22:41:27.73$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.22:41:27.73$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.22:41:27.73$ifdk4/patch= 2006.173.22:41:27.73$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.22:41:27.73$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.22:41:27.73$setupk4/!*+20s 2006.173.22:41:32.29#abcon#<5=/09 0.4 1.0 22.40 891003.3\r\n> 2006.173.22:41:32.31#abcon#{5=INTERFACE CLEAR} 2006.173.22:41:32.37#abcon#[5=S1D000X0/0*\r\n] 2006.173.22:41:42.24$setupk4/"tpicd 2006.173.22:41:42.24$setupk4/echo=off 2006.173.22:41:42.24$setupk4/xlog=off 2006.173.22:41:42.24:!2006.173.22:51:17 2006.173.22:42:08.13#trakl#Source acquired 2006.173.22:42:08.13#flagr#flagr/antenna,acquired 2006.173.22:51:17.00:preob 2006.173.22:51:18.13/onsource/TRACKING 2006.173.22:51:18.13:!2006.173.22:51:27 2006.173.22:51:27.00:"tape 2006.173.22:51:27.00:"st=record 2006.173.22:51:27.00:data_valid=on 2006.173.22:51:27.00:midob 2006.173.22:51:27.13/onsource/TRACKING 2006.173.22:51:27.13/wx/22.57,1003.4,92 2006.173.22:51:27.28/cable/+6.5135E-03 2006.173.22:51:28.37/va/01,07,usb,yes,35,37 2006.173.22:51:28.37/va/02,06,usb,yes,34,35 2006.173.22:51:28.37/va/03,05,usb,yes,44,46 2006.173.22:51:28.37/va/04,06,usb,yes,35,37 2006.173.22:51:28.37/va/05,04,usb,yes,28,28 2006.173.22:51:28.37/va/06,03,usb,yes,39,39 2006.173.22:51:28.37/va/07,04,usb,yes,31,32 2006.173.22:51:28.37/va/08,04,usb,yes,27,32 2006.173.22:51:28.60/valo/01,524.99,yes,locked 2006.173.22:51:28.60/valo/02,534.99,yes,locked 2006.173.22:51:28.60/valo/03,564.99,yes,locked 2006.173.22:51:28.60/valo/04,624.99,yes,locked 2006.173.22:51:28.60/valo/05,734.99,yes,locked 2006.173.22:51:28.60/valo/06,814.99,yes,locked 2006.173.22:51:28.60/valo/07,864.99,yes,locked 2006.173.22:51:28.60/valo/08,884.99,yes,locked 2006.173.22:51:29.69/vb/01,04,usb,yes,29,27 2006.173.22:51:29.69/vb/02,04,usb,yes,31,31 2006.173.22:51:29.69/vb/03,04,usb,yes,28,31 2006.173.22:51:29.69/vb/04,04,usb,yes,33,31 2006.173.22:51:29.69/vb/05,04,usb,yes,25,28 2006.173.22:51:29.69/vb/06,04,usb,yes,30,26 2006.173.22:51:29.69/vb/07,04,usb,yes,29,29 2006.173.22:51:29.69/vb/08,04,usb,yes,27,30 2006.173.22:51:29.93/vblo/01,629.99,yes,locked 2006.173.22:51:29.93/vblo/02,634.99,yes,locked 2006.173.22:51:29.93/vblo/03,649.99,yes,locked 2006.173.22:51:29.93/vblo/04,679.99,yes,locked 2006.173.22:51:29.93/vblo/05,709.99,yes,locked 2006.173.22:51:29.93/vblo/06,719.99,yes,locked 2006.173.22:51:29.93/vblo/07,734.99,yes,locked 2006.173.22:51:29.93/vblo/08,744.99,yes,locked 2006.173.22:51:30.08/vabw/8 2006.173.22:51:30.23/vbbw/8 2006.173.22:51:30.32/xfe/off,on,15.2 2006.173.22:51:30.71/ifatt/23,28,28,28 2006.173.22:51:31.07/fmout-gps/S +3.83E-07 2006.173.22:51:31.11:!2006.173.22:53:37 2006.173.22:53:37.01:data_valid=off 2006.173.22:53:37.01:"et 2006.173.22:53:37.02:!+3s 2006.173.22:53:40.03:"tape 2006.173.22:53:40.03:postob 2006.173.22:53:40.16/cable/+6.5136E-03 2006.173.22:53:40.16/wx/22.64,1003.4,91 2006.173.22:53:40.22/fmout-gps/S +3.84E-07 2006.173.22:53:40.22:scan_name=173-2259,jd0606,90 2006.173.22:53:40.23:source=2136+141,213901.31,142336.0,2000.0,ccw 2006.173.22:53:42.14#flagr#flagr/antenna,new-source 2006.173.22:53:42.14:checkk5 2006.173.22:53:42.56/chk_autoobs//k5ts1/ autoobs is running! 2006.173.22:53:42.98/chk_autoobs//k5ts2/ autoobs is running! 2006.173.22:53:43.39/chk_autoobs//k5ts3/ autoobs is running! 2006.173.22:53:43.79/chk_autoobs//k5ts4/ autoobs is running! 2006.173.22:53:44.17/chk_obsdata//k5ts1/T1732251??a.dat file size is correct (nominal:520MB, actual:516MB). 2006.173.22:53:44.57/chk_obsdata//k5ts2/T1732251??b.dat file size is correct (nominal:520MB, actual:516MB). 2006.173.22:53:44.98/chk_obsdata//k5ts3/T1732251??c.dat file size is correct (nominal:520MB, actual:516MB). 2006.173.22:53:45.39/chk_obsdata//k5ts4/T1732251??d.dat file size is correct (nominal:520MB, actual:516MB). 2006.173.22:53:46.11/k5log//k5ts1_log_newline 2006.173.22:53:46.81/k5log//k5ts2_log_newline 2006.173.22:53:47.52/k5log//k5ts3_log_newline 2006.173.22:53:48.22/k5log//k5ts4_log_newline 2006.173.22:53:48.24/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.22:53:48.24:setupk4=1 2006.173.22:53:48.24$setupk4/echo=on 2006.173.22:53:48.24$setupk4/pcalon 2006.173.22:53:48.24$pcalon/"no phase cal control is implemented here 2006.173.22:53:48.24$setupk4/"tpicd=stop 2006.173.22:53:48.24$setupk4/"rec=synch_on 2006.173.22:53:48.24$setupk4/"rec_mode=128 2006.173.22:53:48.24$setupk4/!* 2006.173.22:53:48.24$setupk4/recpk4 2006.173.22:53:48.24$recpk4/recpatch= 2006.173.22:53:48.25$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.22:53:48.25$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.22:53:48.25$setupk4/vck44 2006.173.22:53:48.25$vck44/valo=1,524.99 2006.173.22:53:48.25#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.22:53:48.25#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.22:53:48.25#ibcon#ireg 17 cls_cnt 0 2006.173.22:53:48.25#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.22:53:48.25#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.22:53:48.25#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.22:53:48.25#ibcon#enter wrdev, iclass 38, count 0 2006.173.22:53:48.25#ibcon#first serial, iclass 38, count 0 2006.173.22:53:48.25#ibcon#enter sib2, iclass 38, count 0 2006.173.22:53:48.25#ibcon#flushed, iclass 38, count 0 2006.173.22:53:48.25#ibcon#about to write, iclass 38, count 0 2006.173.22:53:48.25#ibcon#wrote, iclass 38, count 0 2006.173.22:53:48.25#ibcon#about to read 3, iclass 38, count 0 2006.173.22:53:48.27#ibcon#read 3, iclass 38, count 0 2006.173.22:53:48.27#ibcon#about to read 4, iclass 38, count 0 2006.173.22:53:48.27#ibcon#read 4, iclass 38, count 0 2006.173.22:53:48.27#ibcon#about to read 5, iclass 38, count 0 2006.173.22:53:48.27#ibcon#read 5, iclass 38, count 0 2006.173.22:53:48.27#ibcon#about to read 6, iclass 38, count 0 2006.173.22:53:48.27#ibcon#read 6, iclass 38, count 0 2006.173.22:53:48.27#ibcon#end of sib2, iclass 38, count 0 2006.173.22:53:48.27#ibcon#*mode == 0, iclass 38, count 0 2006.173.22:53:48.27#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.22:53:48.27#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.22:53:48.27#ibcon#*before write, iclass 38, count 0 2006.173.22:53:48.27#ibcon#enter sib2, iclass 38, count 0 2006.173.22:53:48.27#ibcon#flushed, iclass 38, count 0 2006.173.22:53:48.27#ibcon#about to write, iclass 38, count 0 2006.173.22:53:48.27#ibcon#wrote, iclass 38, count 0 2006.173.22:53:48.27#ibcon#about to read 3, iclass 38, count 0 2006.173.22:53:48.32#ibcon#read 3, iclass 38, count 0 2006.173.22:53:48.32#ibcon#about to read 4, iclass 38, count 0 2006.173.22:53:48.32#ibcon#read 4, iclass 38, count 0 2006.173.22:53:48.32#ibcon#about to read 5, iclass 38, count 0 2006.173.22:53:48.32#ibcon#read 5, iclass 38, count 0 2006.173.22:53:48.32#ibcon#about to read 6, iclass 38, count 0 2006.173.22:53:48.32#ibcon#read 6, iclass 38, count 0 2006.173.22:53:48.32#ibcon#end of sib2, iclass 38, count 0 2006.173.22:53:48.32#ibcon#*after write, iclass 38, count 0 2006.173.22:53:48.32#ibcon#*before return 0, iclass 38, count 0 2006.173.22:53:48.32#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.22:53:48.32#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.22:53:48.32#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.22:53:48.32#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.22:53:48.32$vck44/va=1,7 2006.173.22:53:48.32#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.22:53:48.32#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.22:53:48.32#ibcon#ireg 11 cls_cnt 2 2006.173.22:53:48.32#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.22:53:48.32#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.22:53:48.32#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.22:53:48.32#ibcon#enter wrdev, iclass 40, count 2 2006.173.22:53:48.32#ibcon#first serial, iclass 40, count 2 2006.173.22:53:48.32#ibcon#enter sib2, iclass 40, count 2 2006.173.22:53:48.32#ibcon#flushed, iclass 40, count 2 2006.173.22:53:48.32#ibcon#about to write, iclass 40, count 2 2006.173.22:53:48.32#ibcon#wrote, iclass 40, count 2 2006.173.22:53:48.32#ibcon#about to read 3, iclass 40, count 2 2006.173.22:53:48.34#ibcon#read 3, iclass 40, count 2 2006.173.22:53:48.34#ibcon#about to read 4, iclass 40, count 2 2006.173.22:53:48.34#ibcon#read 4, iclass 40, count 2 2006.173.22:53:48.34#ibcon#about to read 5, iclass 40, count 2 2006.173.22:53:48.34#ibcon#read 5, iclass 40, count 2 2006.173.22:53:48.34#ibcon#about to read 6, iclass 40, count 2 2006.173.22:53:48.34#ibcon#read 6, iclass 40, count 2 2006.173.22:53:48.34#ibcon#end of sib2, iclass 40, count 2 2006.173.22:53:48.34#ibcon#*mode == 0, iclass 40, count 2 2006.173.22:53:48.34#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.22:53:48.34#ibcon#[25=AT01-07\r\n] 2006.173.22:53:48.34#ibcon#*before write, iclass 40, count 2 2006.173.22:53:48.34#ibcon#enter sib2, iclass 40, count 2 2006.173.22:53:48.34#ibcon#flushed, iclass 40, count 2 2006.173.22:53:48.34#ibcon#about to write, iclass 40, count 2 2006.173.22:53:48.34#ibcon#wrote, iclass 40, count 2 2006.173.22:53:48.34#ibcon#about to read 3, iclass 40, count 2 2006.173.22:53:48.37#ibcon#read 3, iclass 40, count 2 2006.173.22:53:48.37#ibcon#about to read 4, iclass 40, count 2 2006.173.22:53:48.37#ibcon#read 4, iclass 40, count 2 2006.173.22:53:48.37#ibcon#about to read 5, iclass 40, count 2 2006.173.22:53:48.37#ibcon#read 5, iclass 40, count 2 2006.173.22:53:48.37#ibcon#about to read 6, iclass 40, count 2 2006.173.22:53:48.37#ibcon#read 6, iclass 40, count 2 2006.173.22:53:48.37#ibcon#end of sib2, iclass 40, count 2 2006.173.22:53:48.37#ibcon#*after write, iclass 40, count 2 2006.173.22:53:48.37#ibcon#*before return 0, iclass 40, count 2 2006.173.22:53:48.37#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.22:53:48.37#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.22:53:48.37#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.22:53:48.37#ibcon#ireg 7 cls_cnt 0 2006.173.22:53:48.37#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.22:53:48.49#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.22:53:48.49#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.22:53:48.49#ibcon#enter wrdev, iclass 40, count 0 2006.173.22:53:48.49#ibcon#first serial, iclass 40, count 0 2006.173.22:53:48.49#ibcon#enter sib2, iclass 40, count 0 2006.173.22:53:48.49#ibcon#flushed, iclass 40, count 0 2006.173.22:53:48.49#ibcon#about to write, iclass 40, count 0 2006.173.22:53:48.49#ibcon#wrote, iclass 40, count 0 2006.173.22:53:48.49#ibcon#about to read 3, iclass 40, count 0 2006.173.22:53:48.51#ibcon#read 3, iclass 40, count 0 2006.173.22:53:48.51#ibcon#about to read 4, iclass 40, count 0 2006.173.22:53:48.51#ibcon#read 4, iclass 40, count 0 2006.173.22:53:48.51#ibcon#about to read 5, iclass 40, count 0 2006.173.22:53:48.51#ibcon#read 5, iclass 40, count 0 2006.173.22:53:48.51#ibcon#about to read 6, iclass 40, count 0 2006.173.22:53:48.51#ibcon#read 6, iclass 40, count 0 2006.173.22:53:48.51#ibcon#end of sib2, iclass 40, count 0 2006.173.22:53:48.51#ibcon#*mode == 0, iclass 40, count 0 2006.173.22:53:48.51#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.22:53:48.51#ibcon#[25=USB\r\n] 2006.173.22:53:48.51#ibcon#*before write, iclass 40, count 0 2006.173.22:53:48.51#ibcon#enter sib2, iclass 40, count 0 2006.173.22:53:48.51#ibcon#flushed, iclass 40, count 0 2006.173.22:53:48.51#ibcon#about to write, iclass 40, count 0 2006.173.22:53:48.51#ibcon#wrote, iclass 40, count 0 2006.173.22:53:48.51#ibcon#about to read 3, iclass 40, count 0 2006.173.22:53:48.54#ibcon#read 3, iclass 40, count 0 2006.173.22:53:48.54#ibcon#about to read 4, iclass 40, count 0 2006.173.22:53:48.54#ibcon#read 4, iclass 40, count 0 2006.173.22:53:48.54#ibcon#about to read 5, iclass 40, count 0 2006.173.22:53:48.54#ibcon#read 5, iclass 40, count 0 2006.173.22:53:48.54#ibcon#about to read 6, iclass 40, count 0 2006.173.22:53:48.54#ibcon#read 6, iclass 40, count 0 2006.173.22:53:48.54#ibcon#end of sib2, iclass 40, count 0 2006.173.22:53:48.54#ibcon#*after write, iclass 40, count 0 2006.173.22:53:48.54#ibcon#*before return 0, iclass 40, count 0 2006.173.22:53:48.54#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.22:53:48.54#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.22:53:48.54#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.22:53:48.54#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.22:53:48.54$vck44/valo=2,534.99 2006.173.22:53:48.54#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.22:53:48.54#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.22:53:48.54#ibcon#ireg 17 cls_cnt 0 2006.173.22:53:48.54#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.22:53:48.54#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.22:53:48.54#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.22:53:48.54#ibcon#enter wrdev, iclass 4, count 0 2006.173.22:53:48.54#ibcon#first serial, iclass 4, count 0 2006.173.22:53:48.54#ibcon#enter sib2, iclass 4, count 0 2006.173.22:53:48.54#ibcon#flushed, iclass 4, count 0 2006.173.22:53:48.54#ibcon#about to write, iclass 4, count 0 2006.173.22:53:48.54#ibcon#wrote, iclass 4, count 0 2006.173.22:53:48.54#ibcon#about to read 3, iclass 4, count 0 2006.173.22:53:48.56#ibcon#read 3, iclass 4, count 0 2006.173.22:53:48.56#ibcon#about to read 4, iclass 4, count 0 2006.173.22:53:48.56#ibcon#read 4, iclass 4, count 0 2006.173.22:53:48.56#ibcon#about to read 5, iclass 4, count 0 2006.173.22:53:48.56#ibcon#read 5, iclass 4, count 0 2006.173.22:53:48.56#ibcon#about to read 6, iclass 4, count 0 2006.173.22:53:48.56#ibcon#read 6, iclass 4, count 0 2006.173.22:53:48.56#ibcon#end of sib2, iclass 4, count 0 2006.173.22:53:48.56#ibcon#*mode == 0, iclass 4, count 0 2006.173.22:53:48.56#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.22:53:48.56#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.22:53:48.56#ibcon#*before write, iclass 4, count 0 2006.173.22:53:48.56#ibcon#enter sib2, iclass 4, count 0 2006.173.22:53:48.56#ibcon#flushed, iclass 4, count 0 2006.173.22:53:48.56#ibcon#about to write, iclass 4, count 0 2006.173.22:53:48.56#ibcon#wrote, iclass 4, count 0 2006.173.22:53:48.56#ibcon#about to read 3, iclass 4, count 0 2006.173.22:53:48.60#ibcon#read 3, iclass 4, count 0 2006.173.22:53:48.60#ibcon#about to read 4, iclass 4, count 0 2006.173.22:53:48.60#ibcon#read 4, iclass 4, count 0 2006.173.22:53:48.60#ibcon#about to read 5, iclass 4, count 0 2006.173.22:53:48.60#ibcon#read 5, iclass 4, count 0 2006.173.22:53:48.60#ibcon#about to read 6, iclass 4, count 0 2006.173.22:53:48.60#ibcon#read 6, iclass 4, count 0 2006.173.22:53:48.60#ibcon#end of sib2, iclass 4, count 0 2006.173.22:53:48.60#ibcon#*after write, iclass 4, count 0 2006.173.22:53:48.60#ibcon#*before return 0, iclass 4, count 0 2006.173.22:53:48.60#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.22:53:48.60#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.22:53:48.60#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.22:53:48.60#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.22:53:48.60$vck44/va=2,6 2006.173.22:53:48.60#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.22:53:48.60#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.22:53:48.60#ibcon#ireg 11 cls_cnt 2 2006.173.22:53:48.60#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.22:53:48.66#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.22:53:48.66#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.22:53:48.66#ibcon#enter wrdev, iclass 6, count 2 2006.173.22:53:48.66#ibcon#first serial, iclass 6, count 2 2006.173.22:53:48.66#ibcon#enter sib2, iclass 6, count 2 2006.173.22:53:48.66#ibcon#flushed, iclass 6, count 2 2006.173.22:53:48.66#ibcon#about to write, iclass 6, count 2 2006.173.22:53:48.66#ibcon#wrote, iclass 6, count 2 2006.173.22:53:48.66#ibcon#about to read 3, iclass 6, count 2 2006.173.22:53:48.68#ibcon#read 3, iclass 6, count 2 2006.173.22:53:48.68#ibcon#about to read 4, iclass 6, count 2 2006.173.22:53:48.68#ibcon#read 4, iclass 6, count 2 2006.173.22:53:48.68#ibcon#about to read 5, iclass 6, count 2 2006.173.22:53:48.68#ibcon#read 5, iclass 6, count 2 2006.173.22:53:48.68#ibcon#about to read 6, iclass 6, count 2 2006.173.22:53:48.68#ibcon#read 6, iclass 6, count 2 2006.173.22:53:48.68#ibcon#end of sib2, iclass 6, count 2 2006.173.22:53:48.68#ibcon#*mode == 0, iclass 6, count 2 2006.173.22:53:48.68#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.22:53:48.68#ibcon#[25=AT02-06\r\n] 2006.173.22:53:48.68#ibcon#*before write, iclass 6, count 2 2006.173.22:53:48.68#ibcon#enter sib2, iclass 6, count 2 2006.173.22:53:48.68#ibcon#flushed, iclass 6, count 2 2006.173.22:53:48.68#ibcon#about to write, iclass 6, count 2 2006.173.22:53:48.68#ibcon#wrote, iclass 6, count 2 2006.173.22:53:48.68#ibcon#about to read 3, iclass 6, count 2 2006.173.22:53:48.71#ibcon#read 3, iclass 6, count 2 2006.173.22:53:48.71#ibcon#about to read 4, iclass 6, count 2 2006.173.22:53:48.71#ibcon#read 4, iclass 6, count 2 2006.173.22:53:48.71#ibcon#about to read 5, iclass 6, count 2 2006.173.22:53:48.71#ibcon#read 5, iclass 6, count 2 2006.173.22:53:48.71#ibcon#about to read 6, iclass 6, count 2 2006.173.22:53:48.71#ibcon#read 6, iclass 6, count 2 2006.173.22:53:48.71#ibcon#end of sib2, iclass 6, count 2 2006.173.22:53:48.71#ibcon#*after write, iclass 6, count 2 2006.173.22:53:48.71#ibcon#*before return 0, iclass 6, count 2 2006.173.22:53:48.71#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.22:53:48.71#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.22:53:48.71#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.22:53:48.71#ibcon#ireg 7 cls_cnt 0 2006.173.22:53:48.71#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.22:53:48.83#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.22:53:48.83#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.22:53:48.83#ibcon#enter wrdev, iclass 6, count 0 2006.173.22:53:48.83#ibcon#first serial, iclass 6, count 0 2006.173.22:53:48.83#ibcon#enter sib2, iclass 6, count 0 2006.173.22:53:48.83#ibcon#flushed, iclass 6, count 0 2006.173.22:53:48.83#ibcon#about to write, iclass 6, count 0 2006.173.22:53:48.83#ibcon#wrote, iclass 6, count 0 2006.173.22:53:48.83#ibcon#about to read 3, iclass 6, count 0 2006.173.22:53:48.85#ibcon#read 3, iclass 6, count 0 2006.173.22:53:48.85#ibcon#about to read 4, iclass 6, count 0 2006.173.22:53:48.85#ibcon#read 4, iclass 6, count 0 2006.173.22:53:48.85#ibcon#about to read 5, iclass 6, count 0 2006.173.22:53:48.85#ibcon#read 5, iclass 6, count 0 2006.173.22:53:48.85#ibcon#about to read 6, iclass 6, count 0 2006.173.22:53:48.85#ibcon#read 6, iclass 6, count 0 2006.173.22:53:48.85#ibcon#end of sib2, iclass 6, count 0 2006.173.22:53:48.85#ibcon#*mode == 0, iclass 6, count 0 2006.173.22:53:48.85#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.22:53:48.85#ibcon#[25=USB\r\n] 2006.173.22:53:48.85#ibcon#*before write, iclass 6, count 0 2006.173.22:53:48.85#ibcon#enter sib2, iclass 6, count 0 2006.173.22:53:48.85#ibcon#flushed, iclass 6, count 0 2006.173.22:53:48.85#ibcon#about to write, iclass 6, count 0 2006.173.22:53:48.85#ibcon#wrote, iclass 6, count 0 2006.173.22:53:48.85#ibcon#about to read 3, iclass 6, count 0 2006.173.22:53:48.88#ibcon#read 3, iclass 6, count 0 2006.173.22:53:48.88#ibcon#about to read 4, iclass 6, count 0 2006.173.22:53:48.88#ibcon#read 4, iclass 6, count 0 2006.173.22:53:48.88#ibcon#about to read 5, iclass 6, count 0 2006.173.22:53:48.88#ibcon#read 5, iclass 6, count 0 2006.173.22:53:48.88#ibcon#about to read 6, iclass 6, count 0 2006.173.22:53:48.88#ibcon#read 6, iclass 6, count 0 2006.173.22:53:48.88#ibcon#end of sib2, iclass 6, count 0 2006.173.22:53:48.88#ibcon#*after write, iclass 6, count 0 2006.173.22:53:48.88#ibcon#*before return 0, iclass 6, count 0 2006.173.22:53:48.88#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.22:53:48.88#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.22:53:48.88#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.22:53:48.88#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.22:53:48.88$vck44/valo=3,564.99 2006.173.22:53:48.88#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.22:53:48.88#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.22:53:48.88#ibcon#ireg 17 cls_cnt 0 2006.173.22:53:48.88#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.22:53:48.88#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.22:53:48.88#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.22:53:48.88#ibcon#enter wrdev, iclass 10, count 0 2006.173.22:53:48.88#ibcon#first serial, iclass 10, count 0 2006.173.22:53:48.88#ibcon#enter sib2, iclass 10, count 0 2006.173.22:53:48.88#ibcon#flushed, iclass 10, count 0 2006.173.22:53:48.88#ibcon#about to write, iclass 10, count 0 2006.173.22:53:48.88#ibcon#wrote, iclass 10, count 0 2006.173.22:53:48.88#ibcon#about to read 3, iclass 10, count 0 2006.173.22:53:48.90#ibcon#read 3, iclass 10, count 0 2006.173.22:53:48.90#ibcon#about to read 4, iclass 10, count 0 2006.173.22:53:48.90#ibcon#read 4, iclass 10, count 0 2006.173.22:53:48.90#ibcon#about to read 5, iclass 10, count 0 2006.173.22:53:48.90#ibcon#read 5, iclass 10, count 0 2006.173.22:53:48.90#ibcon#about to read 6, iclass 10, count 0 2006.173.22:53:48.90#ibcon#read 6, iclass 10, count 0 2006.173.22:53:48.90#ibcon#end of sib2, iclass 10, count 0 2006.173.22:53:48.90#ibcon#*mode == 0, iclass 10, count 0 2006.173.22:53:48.90#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.22:53:48.90#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.22:53:48.90#ibcon#*before write, iclass 10, count 0 2006.173.22:53:48.90#ibcon#enter sib2, iclass 10, count 0 2006.173.22:53:48.90#ibcon#flushed, iclass 10, count 0 2006.173.22:53:48.90#ibcon#about to write, iclass 10, count 0 2006.173.22:53:48.90#ibcon#wrote, iclass 10, count 0 2006.173.22:53:48.90#ibcon#about to read 3, iclass 10, count 0 2006.173.22:53:48.94#ibcon#read 3, iclass 10, count 0 2006.173.22:53:48.94#ibcon#about to read 4, iclass 10, count 0 2006.173.22:53:48.94#ibcon#read 4, iclass 10, count 0 2006.173.22:53:48.94#ibcon#about to read 5, iclass 10, count 0 2006.173.22:53:48.94#ibcon#read 5, iclass 10, count 0 2006.173.22:53:48.94#ibcon#about to read 6, iclass 10, count 0 2006.173.22:53:48.94#ibcon#read 6, iclass 10, count 0 2006.173.22:53:48.94#ibcon#end of sib2, iclass 10, count 0 2006.173.22:53:48.94#ibcon#*after write, iclass 10, count 0 2006.173.22:53:48.94#ibcon#*before return 0, iclass 10, count 0 2006.173.22:53:48.94#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.22:53:48.94#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.22:53:48.94#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.22:53:48.94#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.22:53:48.94$vck44/va=3,5 2006.173.22:53:48.94#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.22:53:48.94#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.22:53:48.94#ibcon#ireg 11 cls_cnt 2 2006.173.22:53:48.94#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.22:53:49.00#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.22:53:49.00#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.22:53:49.00#ibcon#enter wrdev, iclass 12, count 2 2006.173.22:53:49.00#ibcon#first serial, iclass 12, count 2 2006.173.22:53:49.00#ibcon#enter sib2, iclass 12, count 2 2006.173.22:53:49.00#ibcon#flushed, iclass 12, count 2 2006.173.22:53:49.00#ibcon#about to write, iclass 12, count 2 2006.173.22:53:49.00#ibcon#wrote, iclass 12, count 2 2006.173.22:53:49.00#ibcon#about to read 3, iclass 12, count 2 2006.173.22:53:49.02#ibcon#read 3, iclass 12, count 2 2006.173.22:53:49.02#ibcon#about to read 4, iclass 12, count 2 2006.173.22:53:49.02#ibcon#read 4, iclass 12, count 2 2006.173.22:53:49.02#ibcon#about to read 5, iclass 12, count 2 2006.173.22:53:49.02#ibcon#read 5, iclass 12, count 2 2006.173.22:53:49.02#ibcon#about to read 6, iclass 12, count 2 2006.173.22:53:49.02#ibcon#read 6, iclass 12, count 2 2006.173.22:53:49.02#ibcon#end of sib2, iclass 12, count 2 2006.173.22:53:49.02#ibcon#*mode == 0, iclass 12, count 2 2006.173.22:53:49.02#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.22:53:49.02#ibcon#[25=AT03-05\r\n] 2006.173.22:53:49.02#ibcon#*before write, iclass 12, count 2 2006.173.22:53:49.02#ibcon#enter sib2, iclass 12, count 2 2006.173.22:53:49.02#ibcon#flushed, iclass 12, count 2 2006.173.22:53:49.02#ibcon#about to write, iclass 12, count 2 2006.173.22:53:49.02#ibcon#wrote, iclass 12, count 2 2006.173.22:53:49.02#ibcon#about to read 3, iclass 12, count 2 2006.173.22:53:49.05#ibcon#read 3, iclass 12, count 2 2006.173.22:53:49.05#ibcon#about to read 4, iclass 12, count 2 2006.173.22:53:49.05#ibcon#read 4, iclass 12, count 2 2006.173.22:53:49.05#ibcon#about to read 5, iclass 12, count 2 2006.173.22:53:49.05#ibcon#read 5, iclass 12, count 2 2006.173.22:53:49.05#ibcon#about to read 6, iclass 12, count 2 2006.173.22:53:49.05#ibcon#read 6, iclass 12, count 2 2006.173.22:53:49.05#ibcon#end of sib2, iclass 12, count 2 2006.173.22:53:49.05#ibcon#*after write, iclass 12, count 2 2006.173.22:53:49.05#ibcon#*before return 0, iclass 12, count 2 2006.173.22:53:49.05#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.22:53:49.05#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.22:53:49.05#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.22:53:49.05#ibcon#ireg 7 cls_cnt 0 2006.173.22:53:49.05#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.22:53:49.17#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.22:53:49.17#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.22:53:49.17#ibcon#enter wrdev, iclass 12, count 0 2006.173.22:53:49.17#ibcon#first serial, iclass 12, count 0 2006.173.22:53:49.17#ibcon#enter sib2, iclass 12, count 0 2006.173.22:53:49.17#ibcon#flushed, iclass 12, count 0 2006.173.22:53:49.17#ibcon#about to write, iclass 12, count 0 2006.173.22:53:49.17#ibcon#wrote, iclass 12, count 0 2006.173.22:53:49.17#ibcon#about to read 3, iclass 12, count 0 2006.173.22:53:49.19#ibcon#read 3, iclass 12, count 0 2006.173.22:53:49.19#ibcon#about to read 4, iclass 12, count 0 2006.173.22:53:49.19#ibcon#read 4, iclass 12, count 0 2006.173.22:53:49.19#ibcon#about to read 5, iclass 12, count 0 2006.173.22:53:49.19#ibcon#read 5, iclass 12, count 0 2006.173.22:53:49.19#ibcon#about to read 6, iclass 12, count 0 2006.173.22:53:49.19#ibcon#read 6, iclass 12, count 0 2006.173.22:53:49.19#ibcon#end of sib2, iclass 12, count 0 2006.173.22:53:49.19#ibcon#*mode == 0, iclass 12, count 0 2006.173.22:53:49.19#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.22:53:49.19#ibcon#[25=USB\r\n] 2006.173.22:53:49.19#ibcon#*before write, iclass 12, count 0 2006.173.22:53:49.19#ibcon#enter sib2, iclass 12, count 0 2006.173.22:53:49.19#ibcon#flushed, iclass 12, count 0 2006.173.22:53:49.19#ibcon#about to write, iclass 12, count 0 2006.173.22:53:49.19#ibcon#wrote, iclass 12, count 0 2006.173.22:53:49.19#ibcon#about to read 3, iclass 12, count 0 2006.173.22:53:49.22#ibcon#read 3, iclass 12, count 0 2006.173.22:53:49.22#ibcon#about to read 4, iclass 12, count 0 2006.173.22:53:49.22#ibcon#read 4, iclass 12, count 0 2006.173.22:53:49.22#ibcon#about to read 5, iclass 12, count 0 2006.173.22:53:49.22#ibcon#read 5, iclass 12, count 0 2006.173.22:53:49.22#ibcon#about to read 6, iclass 12, count 0 2006.173.22:53:49.22#ibcon#read 6, iclass 12, count 0 2006.173.22:53:49.22#ibcon#end of sib2, iclass 12, count 0 2006.173.22:53:49.22#ibcon#*after write, iclass 12, count 0 2006.173.22:53:49.22#ibcon#*before return 0, iclass 12, count 0 2006.173.22:53:49.22#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.22:53:49.22#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.22:53:49.22#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.22:53:49.22#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.22:53:49.22$vck44/valo=4,624.99 2006.173.22:53:49.22#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.22:53:49.22#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.22:53:49.22#ibcon#ireg 17 cls_cnt 0 2006.173.22:53:49.22#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.22:53:49.22#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.22:53:49.22#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.22:53:49.22#ibcon#enter wrdev, iclass 14, count 0 2006.173.22:53:49.22#ibcon#first serial, iclass 14, count 0 2006.173.22:53:49.22#ibcon#enter sib2, iclass 14, count 0 2006.173.22:53:49.22#ibcon#flushed, iclass 14, count 0 2006.173.22:53:49.22#ibcon#about to write, iclass 14, count 0 2006.173.22:53:49.22#ibcon#wrote, iclass 14, count 0 2006.173.22:53:49.22#ibcon#about to read 3, iclass 14, count 0 2006.173.22:53:49.24#ibcon#read 3, iclass 14, count 0 2006.173.22:53:49.24#ibcon#about to read 4, iclass 14, count 0 2006.173.22:53:49.24#ibcon#read 4, iclass 14, count 0 2006.173.22:53:49.24#ibcon#about to read 5, iclass 14, count 0 2006.173.22:53:49.24#ibcon#read 5, iclass 14, count 0 2006.173.22:53:49.24#ibcon#about to read 6, iclass 14, count 0 2006.173.22:53:49.24#ibcon#read 6, iclass 14, count 0 2006.173.22:53:49.24#ibcon#end of sib2, iclass 14, count 0 2006.173.22:53:49.24#ibcon#*mode == 0, iclass 14, count 0 2006.173.22:53:49.24#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.22:53:49.24#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.22:53:49.24#ibcon#*before write, iclass 14, count 0 2006.173.22:53:49.24#ibcon#enter sib2, iclass 14, count 0 2006.173.22:53:49.24#ibcon#flushed, iclass 14, count 0 2006.173.22:53:49.24#ibcon#about to write, iclass 14, count 0 2006.173.22:53:49.24#ibcon#wrote, iclass 14, count 0 2006.173.22:53:49.24#ibcon#about to read 3, iclass 14, count 0 2006.173.22:53:49.28#ibcon#read 3, iclass 14, count 0 2006.173.22:53:49.28#ibcon#about to read 4, iclass 14, count 0 2006.173.22:53:49.28#ibcon#read 4, iclass 14, count 0 2006.173.22:53:49.28#ibcon#about to read 5, iclass 14, count 0 2006.173.22:53:49.28#ibcon#read 5, iclass 14, count 0 2006.173.22:53:49.28#ibcon#about to read 6, iclass 14, count 0 2006.173.22:53:49.28#ibcon#read 6, iclass 14, count 0 2006.173.22:53:49.28#ibcon#end of sib2, iclass 14, count 0 2006.173.22:53:49.28#ibcon#*after write, iclass 14, count 0 2006.173.22:53:49.28#ibcon#*before return 0, iclass 14, count 0 2006.173.22:53:49.28#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.22:53:49.28#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.22:53:49.28#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.22:53:49.28#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.22:53:49.28$vck44/va=4,6 2006.173.22:53:49.28#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.22:53:49.28#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.22:53:49.28#ibcon#ireg 11 cls_cnt 2 2006.173.22:53:49.28#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.22:53:49.34#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.22:53:49.34#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.22:53:49.34#ibcon#enter wrdev, iclass 16, count 2 2006.173.22:53:49.34#ibcon#first serial, iclass 16, count 2 2006.173.22:53:49.34#ibcon#enter sib2, iclass 16, count 2 2006.173.22:53:49.34#ibcon#flushed, iclass 16, count 2 2006.173.22:53:49.34#ibcon#about to write, iclass 16, count 2 2006.173.22:53:49.34#ibcon#wrote, iclass 16, count 2 2006.173.22:53:49.34#ibcon#about to read 3, iclass 16, count 2 2006.173.22:53:49.36#ibcon#read 3, iclass 16, count 2 2006.173.22:53:49.36#ibcon#about to read 4, iclass 16, count 2 2006.173.22:53:49.36#ibcon#read 4, iclass 16, count 2 2006.173.22:53:49.36#ibcon#about to read 5, iclass 16, count 2 2006.173.22:53:49.36#ibcon#read 5, iclass 16, count 2 2006.173.22:53:49.36#ibcon#about to read 6, iclass 16, count 2 2006.173.22:53:49.36#ibcon#read 6, iclass 16, count 2 2006.173.22:53:49.36#ibcon#end of sib2, iclass 16, count 2 2006.173.22:53:49.36#ibcon#*mode == 0, iclass 16, count 2 2006.173.22:53:49.36#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.22:53:49.36#ibcon#[25=AT04-06\r\n] 2006.173.22:53:49.36#ibcon#*before write, iclass 16, count 2 2006.173.22:53:49.36#ibcon#enter sib2, iclass 16, count 2 2006.173.22:53:49.36#ibcon#flushed, iclass 16, count 2 2006.173.22:53:49.36#ibcon#about to write, iclass 16, count 2 2006.173.22:53:49.36#ibcon#wrote, iclass 16, count 2 2006.173.22:53:49.36#ibcon#about to read 3, iclass 16, count 2 2006.173.22:53:49.39#ibcon#read 3, iclass 16, count 2 2006.173.22:53:49.39#ibcon#about to read 4, iclass 16, count 2 2006.173.22:53:49.39#ibcon#read 4, iclass 16, count 2 2006.173.22:53:49.39#ibcon#about to read 5, iclass 16, count 2 2006.173.22:53:49.39#ibcon#read 5, iclass 16, count 2 2006.173.22:53:49.39#ibcon#about to read 6, iclass 16, count 2 2006.173.22:53:49.39#ibcon#read 6, iclass 16, count 2 2006.173.22:53:49.39#ibcon#end of sib2, iclass 16, count 2 2006.173.22:53:49.39#ibcon#*after write, iclass 16, count 2 2006.173.22:53:49.39#ibcon#*before return 0, iclass 16, count 2 2006.173.22:53:49.39#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.22:53:49.39#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.22:53:49.39#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.22:53:49.39#ibcon#ireg 7 cls_cnt 0 2006.173.22:53:49.39#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.22:53:49.51#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.22:53:49.51#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.22:53:49.51#ibcon#enter wrdev, iclass 16, count 0 2006.173.22:53:49.51#ibcon#first serial, iclass 16, count 0 2006.173.22:53:49.51#ibcon#enter sib2, iclass 16, count 0 2006.173.22:53:49.51#ibcon#flushed, iclass 16, count 0 2006.173.22:53:49.51#ibcon#about to write, iclass 16, count 0 2006.173.22:53:49.51#ibcon#wrote, iclass 16, count 0 2006.173.22:53:49.51#ibcon#about to read 3, iclass 16, count 0 2006.173.22:53:49.53#ibcon#read 3, iclass 16, count 0 2006.173.22:53:49.53#ibcon#about to read 4, iclass 16, count 0 2006.173.22:53:49.53#ibcon#read 4, iclass 16, count 0 2006.173.22:53:49.53#ibcon#about to read 5, iclass 16, count 0 2006.173.22:53:49.53#ibcon#read 5, iclass 16, count 0 2006.173.22:53:49.53#ibcon#about to read 6, iclass 16, count 0 2006.173.22:53:49.53#ibcon#read 6, iclass 16, count 0 2006.173.22:53:49.53#ibcon#end of sib2, iclass 16, count 0 2006.173.22:53:49.53#ibcon#*mode == 0, iclass 16, count 0 2006.173.22:53:49.53#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.22:53:49.53#ibcon#[25=USB\r\n] 2006.173.22:53:49.53#ibcon#*before write, iclass 16, count 0 2006.173.22:53:49.53#ibcon#enter sib2, iclass 16, count 0 2006.173.22:53:49.53#ibcon#flushed, iclass 16, count 0 2006.173.22:53:49.53#ibcon#about to write, iclass 16, count 0 2006.173.22:53:49.53#ibcon#wrote, iclass 16, count 0 2006.173.22:53:49.53#ibcon#about to read 3, iclass 16, count 0 2006.173.22:53:49.56#ibcon#read 3, iclass 16, count 0 2006.173.22:53:49.56#ibcon#about to read 4, iclass 16, count 0 2006.173.22:53:49.56#ibcon#read 4, iclass 16, count 0 2006.173.22:53:49.56#ibcon#about to read 5, iclass 16, count 0 2006.173.22:53:49.56#ibcon#read 5, iclass 16, count 0 2006.173.22:53:49.56#ibcon#about to read 6, iclass 16, count 0 2006.173.22:53:49.56#ibcon#read 6, iclass 16, count 0 2006.173.22:53:49.56#ibcon#end of sib2, iclass 16, count 0 2006.173.22:53:49.56#ibcon#*after write, iclass 16, count 0 2006.173.22:53:49.56#ibcon#*before return 0, iclass 16, count 0 2006.173.22:53:49.56#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.22:53:49.56#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.22:53:49.56#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.22:53:49.56#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.22:53:49.56$vck44/valo=5,734.99 2006.173.22:53:49.56#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.22:53:49.56#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.22:53:49.56#ibcon#ireg 17 cls_cnt 0 2006.173.22:53:49.56#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.22:53:49.56#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.22:53:49.56#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.22:53:49.56#ibcon#enter wrdev, iclass 18, count 0 2006.173.22:53:49.56#ibcon#first serial, iclass 18, count 0 2006.173.22:53:49.56#ibcon#enter sib2, iclass 18, count 0 2006.173.22:53:49.56#ibcon#flushed, iclass 18, count 0 2006.173.22:53:49.56#ibcon#about to write, iclass 18, count 0 2006.173.22:53:49.56#ibcon#wrote, iclass 18, count 0 2006.173.22:53:49.56#ibcon#about to read 3, iclass 18, count 0 2006.173.22:53:49.58#ibcon#read 3, iclass 18, count 0 2006.173.22:53:49.58#ibcon#about to read 4, iclass 18, count 0 2006.173.22:53:49.58#ibcon#read 4, iclass 18, count 0 2006.173.22:53:49.58#ibcon#about to read 5, iclass 18, count 0 2006.173.22:53:49.58#ibcon#read 5, iclass 18, count 0 2006.173.22:53:49.58#ibcon#about to read 6, iclass 18, count 0 2006.173.22:53:49.58#ibcon#read 6, iclass 18, count 0 2006.173.22:53:49.58#ibcon#end of sib2, iclass 18, count 0 2006.173.22:53:49.58#ibcon#*mode == 0, iclass 18, count 0 2006.173.22:53:49.58#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.22:53:49.58#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.22:53:49.58#ibcon#*before write, iclass 18, count 0 2006.173.22:53:49.58#ibcon#enter sib2, iclass 18, count 0 2006.173.22:53:49.58#ibcon#flushed, iclass 18, count 0 2006.173.22:53:49.58#ibcon#about to write, iclass 18, count 0 2006.173.22:53:49.58#ibcon#wrote, iclass 18, count 0 2006.173.22:53:49.58#ibcon#about to read 3, iclass 18, count 0 2006.173.22:53:49.62#ibcon#read 3, iclass 18, count 0 2006.173.22:53:49.62#ibcon#about to read 4, iclass 18, count 0 2006.173.22:53:49.62#ibcon#read 4, iclass 18, count 0 2006.173.22:53:49.62#ibcon#about to read 5, iclass 18, count 0 2006.173.22:53:49.62#ibcon#read 5, iclass 18, count 0 2006.173.22:53:49.62#ibcon#about to read 6, iclass 18, count 0 2006.173.22:53:49.62#ibcon#read 6, iclass 18, count 0 2006.173.22:53:49.62#ibcon#end of sib2, iclass 18, count 0 2006.173.22:53:49.62#ibcon#*after write, iclass 18, count 0 2006.173.22:53:49.62#ibcon#*before return 0, iclass 18, count 0 2006.173.22:53:49.62#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.22:53:49.62#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.22:53:49.62#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.22:53:49.62#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.22:53:49.62$vck44/va=5,4 2006.173.22:53:49.62#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.22:53:49.62#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.22:53:49.62#ibcon#ireg 11 cls_cnt 2 2006.173.22:53:49.62#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.22:53:49.68#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.22:53:49.68#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.22:53:49.68#ibcon#enter wrdev, iclass 20, count 2 2006.173.22:53:49.68#ibcon#first serial, iclass 20, count 2 2006.173.22:53:49.68#ibcon#enter sib2, iclass 20, count 2 2006.173.22:53:49.68#ibcon#flushed, iclass 20, count 2 2006.173.22:53:49.68#ibcon#about to write, iclass 20, count 2 2006.173.22:53:49.68#ibcon#wrote, iclass 20, count 2 2006.173.22:53:49.68#ibcon#about to read 3, iclass 20, count 2 2006.173.22:53:49.70#ibcon#read 3, iclass 20, count 2 2006.173.22:53:49.70#ibcon#about to read 4, iclass 20, count 2 2006.173.22:53:49.70#ibcon#read 4, iclass 20, count 2 2006.173.22:53:49.70#ibcon#about to read 5, iclass 20, count 2 2006.173.22:53:49.70#ibcon#read 5, iclass 20, count 2 2006.173.22:53:49.70#ibcon#about to read 6, iclass 20, count 2 2006.173.22:53:49.70#ibcon#read 6, iclass 20, count 2 2006.173.22:53:49.70#ibcon#end of sib2, iclass 20, count 2 2006.173.22:53:49.70#ibcon#*mode == 0, iclass 20, count 2 2006.173.22:53:49.70#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.22:53:49.70#ibcon#[25=AT05-04\r\n] 2006.173.22:53:49.70#ibcon#*before write, iclass 20, count 2 2006.173.22:53:49.70#ibcon#enter sib2, iclass 20, count 2 2006.173.22:53:49.70#ibcon#flushed, iclass 20, count 2 2006.173.22:53:49.70#ibcon#about to write, iclass 20, count 2 2006.173.22:53:49.70#ibcon#wrote, iclass 20, count 2 2006.173.22:53:49.70#ibcon#about to read 3, iclass 20, count 2 2006.173.22:53:49.73#ibcon#read 3, iclass 20, count 2 2006.173.22:53:49.73#ibcon#about to read 4, iclass 20, count 2 2006.173.22:53:49.73#ibcon#read 4, iclass 20, count 2 2006.173.22:53:49.73#ibcon#about to read 5, iclass 20, count 2 2006.173.22:53:49.73#ibcon#read 5, iclass 20, count 2 2006.173.22:53:49.73#ibcon#about to read 6, iclass 20, count 2 2006.173.22:53:49.73#ibcon#read 6, iclass 20, count 2 2006.173.22:53:49.73#ibcon#end of sib2, iclass 20, count 2 2006.173.22:53:49.73#ibcon#*after write, iclass 20, count 2 2006.173.22:53:49.73#ibcon#*before return 0, iclass 20, count 2 2006.173.22:53:49.73#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.22:53:49.73#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.22:53:49.73#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.22:53:49.73#ibcon#ireg 7 cls_cnt 0 2006.173.22:53:49.73#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.22:53:49.85#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.22:53:49.85#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.22:53:49.85#ibcon#enter wrdev, iclass 20, count 0 2006.173.22:53:49.85#ibcon#first serial, iclass 20, count 0 2006.173.22:53:49.85#ibcon#enter sib2, iclass 20, count 0 2006.173.22:53:49.85#ibcon#flushed, iclass 20, count 0 2006.173.22:53:49.85#ibcon#about to write, iclass 20, count 0 2006.173.22:53:49.85#ibcon#wrote, iclass 20, count 0 2006.173.22:53:49.85#ibcon#about to read 3, iclass 20, count 0 2006.173.22:53:49.87#ibcon#read 3, iclass 20, count 0 2006.173.22:53:49.87#ibcon#about to read 4, iclass 20, count 0 2006.173.22:53:49.87#ibcon#read 4, iclass 20, count 0 2006.173.22:53:49.87#ibcon#about to read 5, iclass 20, count 0 2006.173.22:53:49.87#ibcon#read 5, iclass 20, count 0 2006.173.22:53:49.87#ibcon#about to read 6, iclass 20, count 0 2006.173.22:53:49.87#ibcon#read 6, iclass 20, count 0 2006.173.22:53:49.87#ibcon#end of sib2, iclass 20, count 0 2006.173.22:53:49.87#ibcon#*mode == 0, iclass 20, count 0 2006.173.22:53:49.87#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.22:53:49.87#ibcon#[25=USB\r\n] 2006.173.22:53:49.87#ibcon#*before write, iclass 20, count 0 2006.173.22:53:49.87#ibcon#enter sib2, iclass 20, count 0 2006.173.22:53:49.87#ibcon#flushed, iclass 20, count 0 2006.173.22:53:49.87#ibcon#about to write, iclass 20, count 0 2006.173.22:53:49.87#ibcon#wrote, iclass 20, count 0 2006.173.22:53:49.87#ibcon#about to read 3, iclass 20, count 0 2006.173.22:53:49.90#ibcon#read 3, iclass 20, count 0 2006.173.22:53:49.90#ibcon#about to read 4, iclass 20, count 0 2006.173.22:53:49.90#ibcon#read 4, iclass 20, count 0 2006.173.22:53:49.90#ibcon#about to read 5, iclass 20, count 0 2006.173.22:53:49.90#ibcon#read 5, iclass 20, count 0 2006.173.22:53:49.90#ibcon#about to read 6, iclass 20, count 0 2006.173.22:53:49.90#ibcon#read 6, iclass 20, count 0 2006.173.22:53:49.90#ibcon#end of sib2, iclass 20, count 0 2006.173.22:53:49.90#ibcon#*after write, iclass 20, count 0 2006.173.22:53:49.90#ibcon#*before return 0, iclass 20, count 0 2006.173.22:53:49.90#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.22:53:49.90#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.22:53:49.90#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.22:53:49.90#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.22:53:49.90$vck44/valo=6,814.99 2006.173.22:53:49.90#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.22:53:49.90#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.22:53:49.90#ibcon#ireg 17 cls_cnt 0 2006.173.22:53:49.90#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.22:53:49.90#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.22:53:49.90#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.22:53:49.90#ibcon#enter wrdev, iclass 22, count 0 2006.173.22:53:49.90#ibcon#first serial, iclass 22, count 0 2006.173.22:53:49.90#ibcon#enter sib2, iclass 22, count 0 2006.173.22:53:49.90#ibcon#flushed, iclass 22, count 0 2006.173.22:53:49.90#ibcon#about to write, iclass 22, count 0 2006.173.22:53:49.90#ibcon#wrote, iclass 22, count 0 2006.173.22:53:49.90#ibcon#about to read 3, iclass 22, count 0 2006.173.22:53:49.92#ibcon#read 3, iclass 22, count 0 2006.173.22:53:49.92#ibcon#about to read 4, iclass 22, count 0 2006.173.22:53:49.92#ibcon#read 4, iclass 22, count 0 2006.173.22:53:49.92#ibcon#about to read 5, iclass 22, count 0 2006.173.22:53:49.92#ibcon#read 5, iclass 22, count 0 2006.173.22:53:49.92#ibcon#about to read 6, iclass 22, count 0 2006.173.22:53:49.92#ibcon#read 6, iclass 22, count 0 2006.173.22:53:49.92#ibcon#end of sib2, iclass 22, count 0 2006.173.22:53:49.92#ibcon#*mode == 0, iclass 22, count 0 2006.173.22:53:49.92#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.22:53:49.92#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.22:53:49.92#ibcon#*before write, iclass 22, count 0 2006.173.22:53:49.92#ibcon#enter sib2, iclass 22, count 0 2006.173.22:53:49.92#ibcon#flushed, iclass 22, count 0 2006.173.22:53:49.92#ibcon#about to write, iclass 22, count 0 2006.173.22:53:49.92#ibcon#wrote, iclass 22, count 0 2006.173.22:53:49.92#ibcon#about to read 3, iclass 22, count 0 2006.173.22:53:49.96#ibcon#read 3, iclass 22, count 0 2006.173.22:53:49.96#ibcon#about to read 4, iclass 22, count 0 2006.173.22:53:49.96#ibcon#read 4, iclass 22, count 0 2006.173.22:53:49.96#ibcon#about to read 5, iclass 22, count 0 2006.173.22:53:49.96#ibcon#read 5, iclass 22, count 0 2006.173.22:53:49.96#ibcon#about to read 6, iclass 22, count 0 2006.173.22:53:49.96#ibcon#read 6, iclass 22, count 0 2006.173.22:53:49.96#ibcon#end of sib2, iclass 22, count 0 2006.173.22:53:49.96#ibcon#*after write, iclass 22, count 0 2006.173.22:53:49.96#ibcon#*before return 0, iclass 22, count 0 2006.173.22:53:49.96#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.22:53:49.96#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.22:53:49.96#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.22:53:49.96#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.22:53:49.96$vck44/va=6,3 2006.173.22:53:49.96#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.22:53:49.96#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.22:53:49.96#ibcon#ireg 11 cls_cnt 2 2006.173.22:53:49.96#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.22:53:50.02#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.22:53:50.02#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.22:53:50.02#ibcon#enter wrdev, iclass 24, count 2 2006.173.22:53:50.02#ibcon#first serial, iclass 24, count 2 2006.173.22:53:50.02#ibcon#enter sib2, iclass 24, count 2 2006.173.22:53:50.02#ibcon#flushed, iclass 24, count 2 2006.173.22:53:50.02#ibcon#about to write, iclass 24, count 2 2006.173.22:53:50.02#ibcon#wrote, iclass 24, count 2 2006.173.22:53:50.02#ibcon#about to read 3, iclass 24, count 2 2006.173.22:53:50.04#ibcon#read 3, iclass 24, count 2 2006.173.22:53:50.04#ibcon#about to read 4, iclass 24, count 2 2006.173.22:53:50.04#ibcon#read 4, iclass 24, count 2 2006.173.22:53:50.04#ibcon#about to read 5, iclass 24, count 2 2006.173.22:53:50.04#ibcon#read 5, iclass 24, count 2 2006.173.22:53:50.04#ibcon#about to read 6, iclass 24, count 2 2006.173.22:53:50.04#ibcon#read 6, iclass 24, count 2 2006.173.22:53:50.04#ibcon#end of sib2, iclass 24, count 2 2006.173.22:53:50.04#ibcon#*mode == 0, iclass 24, count 2 2006.173.22:53:50.04#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.22:53:50.04#ibcon#[25=AT06-03\r\n] 2006.173.22:53:50.04#ibcon#*before write, iclass 24, count 2 2006.173.22:53:50.04#ibcon#enter sib2, iclass 24, count 2 2006.173.22:53:50.04#ibcon#flushed, iclass 24, count 2 2006.173.22:53:50.04#ibcon#about to write, iclass 24, count 2 2006.173.22:53:50.04#ibcon#wrote, iclass 24, count 2 2006.173.22:53:50.04#ibcon#about to read 3, iclass 24, count 2 2006.173.22:53:50.07#ibcon#read 3, iclass 24, count 2 2006.173.22:53:50.07#ibcon#about to read 4, iclass 24, count 2 2006.173.22:53:50.07#ibcon#read 4, iclass 24, count 2 2006.173.22:53:50.07#ibcon#about to read 5, iclass 24, count 2 2006.173.22:53:50.07#ibcon#read 5, iclass 24, count 2 2006.173.22:53:50.07#ibcon#about to read 6, iclass 24, count 2 2006.173.22:53:50.07#ibcon#read 6, iclass 24, count 2 2006.173.22:53:50.07#ibcon#end of sib2, iclass 24, count 2 2006.173.22:53:50.07#ibcon#*after write, iclass 24, count 2 2006.173.22:53:50.07#ibcon#*before return 0, iclass 24, count 2 2006.173.22:53:50.07#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.22:53:50.07#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.22:53:50.07#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.22:53:50.07#ibcon#ireg 7 cls_cnt 0 2006.173.22:53:50.07#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.22:53:50.19#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.22:53:50.19#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.22:53:50.19#ibcon#enter wrdev, iclass 24, count 0 2006.173.22:53:50.19#ibcon#first serial, iclass 24, count 0 2006.173.22:53:50.19#ibcon#enter sib2, iclass 24, count 0 2006.173.22:53:50.19#ibcon#flushed, iclass 24, count 0 2006.173.22:53:50.19#ibcon#about to write, iclass 24, count 0 2006.173.22:53:50.19#ibcon#wrote, iclass 24, count 0 2006.173.22:53:50.19#ibcon#about to read 3, iclass 24, count 0 2006.173.22:53:50.21#ibcon#read 3, iclass 24, count 0 2006.173.22:53:50.21#ibcon#about to read 4, iclass 24, count 0 2006.173.22:53:50.21#ibcon#read 4, iclass 24, count 0 2006.173.22:53:50.21#ibcon#about to read 5, iclass 24, count 0 2006.173.22:53:50.21#ibcon#read 5, iclass 24, count 0 2006.173.22:53:50.21#ibcon#about to read 6, iclass 24, count 0 2006.173.22:53:50.21#ibcon#read 6, iclass 24, count 0 2006.173.22:53:50.21#ibcon#end of sib2, iclass 24, count 0 2006.173.22:53:50.21#ibcon#*mode == 0, iclass 24, count 0 2006.173.22:53:50.21#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.22:53:50.21#ibcon#[25=USB\r\n] 2006.173.22:53:50.21#ibcon#*before write, iclass 24, count 0 2006.173.22:53:50.21#ibcon#enter sib2, iclass 24, count 0 2006.173.22:53:50.21#ibcon#flushed, iclass 24, count 0 2006.173.22:53:50.21#ibcon#about to write, iclass 24, count 0 2006.173.22:53:50.21#ibcon#wrote, iclass 24, count 0 2006.173.22:53:50.21#ibcon#about to read 3, iclass 24, count 0 2006.173.22:53:50.24#ibcon#read 3, iclass 24, count 0 2006.173.22:53:50.24#ibcon#about to read 4, iclass 24, count 0 2006.173.22:53:50.24#ibcon#read 4, iclass 24, count 0 2006.173.22:53:50.24#ibcon#about to read 5, iclass 24, count 0 2006.173.22:53:50.24#ibcon#read 5, iclass 24, count 0 2006.173.22:53:50.24#ibcon#about to read 6, iclass 24, count 0 2006.173.22:53:50.24#ibcon#read 6, iclass 24, count 0 2006.173.22:53:50.24#ibcon#end of sib2, iclass 24, count 0 2006.173.22:53:50.24#ibcon#*after write, iclass 24, count 0 2006.173.22:53:50.24#ibcon#*before return 0, iclass 24, count 0 2006.173.22:53:50.24#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.22:53:50.24#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.22:53:50.24#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.22:53:50.24#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.22:53:50.24$vck44/valo=7,864.99 2006.173.22:53:50.24#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.22:53:50.24#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.22:53:50.24#ibcon#ireg 17 cls_cnt 0 2006.173.22:53:50.24#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.22:53:50.24#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.22:53:50.24#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.22:53:50.24#ibcon#enter wrdev, iclass 26, count 0 2006.173.22:53:50.24#ibcon#first serial, iclass 26, count 0 2006.173.22:53:50.24#ibcon#enter sib2, iclass 26, count 0 2006.173.22:53:50.24#ibcon#flushed, iclass 26, count 0 2006.173.22:53:50.24#ibcon#about to write, iclass 26, count 0 2006.173.22:53:50.24#ibcon#wrote, iclass 26, count 0 2006.173.22:53:50.24#ibcon#about to read 3, iclass 26, count 0 2006.173.22:53:50.26#ibcon#read 3, iclass 26, count 0 2006.173.22:53:50.26#ibcon#about to read 4, iclass 26, count 0 2006.173.22:53:50.26#ibcon#read 4, iclass 26, count 0 2006.173.22:53:50.26#ibcon#about to read 5, iclass 26, count 0 2006.173.22:53:50.26#ibcon#read 5, iclass 26, count 0 2006.173.22:53:50.26#ibcon#about to read 6, iclass 26, count 0 2006.173.22:53:50.26#ibcon#read 6, iclass 26, count 0 2006.173.22:53:50.26#ibcon#end of sib2, iclass 26, count 0 2006.173.22:53:50.26#ibcon#*mode == 0, iclass 26, count 0 2006.173.22:53:50.26#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.22:53:50.26#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.22:53:50.26#ibcon#*before write, iclass 26, count 0 2006.173.22:53:50.26#ibcon#enter sib2, iclass 26, count 0 2006.173.22:53:50.26#ibcon#flushed, iclass 26, count 0 2006.173.22:53:50.26#ibcon#about to write, iclass 26, count 0 2006.173.22:53:50.26#ibcon#wrote, iclass 26, count 0 2006.173.22:53:50.26#ibcon#about to read 3, iclass 26, count 0 2006.173.22:53:50.30#ibcon#read 3, iclass 26, count 0 2006.173.22:53:50.30#ibcon#about to read 4, iclass 26, count 0 2006.173.22:53:50.30#ibcon#read 4, iclass 26, count 0 2006.173.22:53:50.30#ibcon#about to read 5, iclass 26, count 0 2006.173.22:53:50.30#ibcon#read 5, iclass 26, count 0 2006.173.22:53:50.30#ibcon#about to read 6, iclass 26, count 0 2006.173.22:53:50.30#ibcon#read 6, iclass 26, count 0 2006.173.22:53:50.30#ibcon#end of sib2, iclass 26, count 0 2006.173.22:53:50.30#ibcon#*after write, iclass 26, count 0 2006.173.22:53:50.30#ibcon#*before return 0, iclass 26, count 0 2006.173.22:53:50.30#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.22:53:50.30#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.22:53:50.30#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.22:53:50.30#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.22:53:50.30$vck44/va=7,4 2006.173.22:53:50.30#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.22:53:50.30#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.22:53:50.30#ibcon#ireg 11 cls_cnt 2 2006.173.22:53:50.30#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.22:53:50.36#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.22:53:50.36#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.22:53:50.36#ibcon#enter wrdev, iclass 28, count 2 2006.173.22:53:50.36#ibcon#first serial, iclass 28, count 2 2006.173.22:53:50.36#ibcon#enter sib2, iclass 28, count 2 2006.173.22:53:50.36#ibcon#flushed, iclass 28, count 2 2006.173.22:53:50.36#ibcon#about to write, iclass 28, count 2 2006.173.22:53:50.36#ibcon#wrote, iclass 28, count 2 2006.173.22:53:50.36#ibcon#about to read 3, iclass 28, count 2 2006.173.22:53:50.38#ibcon#read 3, iclass 28, count 2 2006.173.22:53:50.38#ibcon#about to read 4, iclass 28, count 2 2006.173.22:53:50.38#ibcon#read 4, iclass 28, count 2 2006.173.22:53:50.38#ibcon#about to read 5, iclass 28, count 2 2006.173.22:53:50.38#ibcon#read 5, iclass 28, count 2 2006.173.22:53:50.38#ibcon#about to read 6, iclass 28, count 2 2006.173.22:53:50.38#ibcon#read 6, iclass 28, count 2 2006.173.22:53:50.38#ibcon#end of sib2, iclass 28, count 2 2006.173.22:53:50.38#ibcon#*mode == 0, iclass 28, count 2 2006.173.22:53:50.38#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.22:53:50.38#ibcon#[25=AT07-04\r\n] 2006.173.22:53:50.38#ibcon#*before write, iclass 28, count 2 2006.173.22:53:50.38#ibcon#enter sib2, iclass 28, count 2 2006.173.22:53:50.38#ibcon#flushed, iclass 28, count 2 2006.173.22:53:50.38#ibcon#about to write, iclass 28, count 2 2006.173.22:53:50.38#ibcon#wrote, iclass 28, count 2 2006.173.22:53:50.38#ibcon#about to read 3, iclass 28, count 2 2006.173.22:53:50.41#ibcon#read 3, iclass 28, count 2 2006.173.22:53:50.41#ibcon#about to read 4, iclass 28, count 2 2006.173.22:53:50.41#ibcon#read 4, iclass 28, count 2 2006.173.22:53:50.41#ibcon#about to read 5, iclass 28, count 2 2006.173.22:53:50.41#ibcon#read 5, iclass 28, count 2 2006.173.22:53:50.41#ibcon#about to read 6, iclass 28, count 2 2006.173.22:53:50.41#ibcon#read 6, iclass 28, count 2 2006.173.22:53:50.41#ibcon#end of sib2, iclass 28, count 2 2006.173.22:53:50.41#ibcon#*after write, iclass 28, count 2 2006.173.22:53:50.41#ibcon#*before return 0, iclass 28, count 2 2006.173.22:53:50.41#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.22:53:50.41#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.22:53:50.41#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.22:53:50.41#ibcon#ireg 7 cls_cnt 0 2006.173.22:53:50.41#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.22:53:50.53#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.22:53:50.53#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.22:53:50.53#ibcon#enter wrdev, iclass 28, count 0 2006.173.22:53:50.53#ibcon#first serial, iclass 28, count 0 2006.173.22:53:50.53#ibcon#enter sib2, iclass 28, count 0 2006.173.22:53:50.53#ibcon#flushed, iclass 28, count 0 2006.173.22:53:50.53#ibcon#about to write, iclass 28, count 0 2006.173.22:53:50.53#ibcon#wrote, iclass 28, count 0 2006.173.22:53:50.53#ibcon#about to read 3, iclass 28, count 0 2006.173.22:53:50.55#ibcon#read 3, iclass 28, count 0 2006.173.22:53:50.55#ibcon#about to read 4, iclass 28, count 0 2006.173.22:53:50.55#ibcon#read 4, iclass 28, count 0 2006.173.22:53:50.55#ibcon#about to read 5, iclass 28, count 0 2006.173.22:53:50.55#ibcon#read 5, iclass 28, count 0 2006.173.22:53:50.55#ibcon#about to read 6, iclass 28, count 0 2006.173.22:53:50.55#ibcon#read 6, iclass 28, count 0 2006.173.22:53:50.55#ibcon#end of sib2, iclass 28, count 0 2006.173.22:53:50.55#ibcon#*mode == 0, iclass 28, count 0 2006.173.22:53:50.55#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.22:53:50.55#ibcon#[25=USB\r\n] 2006.173.22:53:50.55#ibcon#*before write, iclass 28, count 0 2006.173.22:53:50.55#ibcon#enter sib2, iclass 28, count 0 2006.173.22:53:50.55#ibcon#flushed, iclass 28, count 0 2006.173.22:53:50.55#ibcon#about to write, iclass 28, count 0 2006.173.22:53:50.55#ibcon#wrote, iclass 28, count 0 2006.173.22:53:50.55#ibcon#about to read 3, iclass 28, count 0 2006.173.22:53:50.58#ibcon#read 3, iclass 28, count 0 2006.173.22:53:50.58#ibcon#about to read 4, iclass 28, count 0 2006.173.22:53:50.58#ibcon#read 4, iclass 28, count 0 2006.173.22:53:50.58#ibcon#about to read 5, iclass 28, count 0 2006.173.22:53:50.58#ibcon#read 5, iclass 28, count 0 2006.173.22:53:50.58#ibcon#about to read 6, iclass 28, count 0 2006.173.22:53:50.58#ibcon#read 6, iclass 28, count 0 2006.173.22:53:50.58#ibcon#end of sib2, iclass 28, count 0 2006.173.22:53:50.58#ibcon#*after write, iclass 28, count 0 2006.173.22:53:50.58#ibcon#*before return 0, iclass 28, count 0 2006.173.22:53:50.58#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.22:53:50.58#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.22:53:50.58#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.22:53:50.58#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.22:53:50.58$vck44/valo=8,884.99 2006.173.22:53:50.58#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.22:53:50.58#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.22:53:50.58#ibcon#ireg 17 cls_cnt 0 2006.173.22:53:50.58#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.22:53:50.58#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.22:53:50.58#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.22:53:50.58#ibcon#enter wrdev, iclass 30, count 0 2006.173.22:53:50.58#ibcon#first serial, iclass 30, count 0 2006.173.22:53:50.58#ibcon#enter sib2, iclass 30, count 0 2006.173.22:53:50.58#ibcon#flushed, iclass 30, count 0 2006.173.22:53:50.58#ibcon#about to write, iclass 30, count 0 2006.173.22:53:50.58#ibcon#wrote, iclass 30, count 0 2006.173.22:53:50.58#ibcon#about to read 3, iclass 30, count 0 2006.173.22:53:50.60#ibcon#read 3, iclass 30, count 0 2006.173.22:53:50.60#ibcon#about to read 4, iclass 30, count 0 2006.173.22:53:50.60#ibcon#read 4, iclass 30, count 0 2006.173.22:53:50.60#ibcon#about to read 5, iclass 30, count 0 2006.173.22:53:50.60#ibcon#read 5, iclass 30, count 0 2006.173.22:53:50.60#ibcon#about to read 6, iclass 30, count 0 2006.173.22:53:50.60#ibcon#read 6, iclass 30, count 0 2006.173.22:53:50.60#ibcon#end of sib2, iclass 30, count 0 2006.173.22:53:50.60#ibcon#*mode == 0, iclass 30, count 0 2006.173.22:53:50.60#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.22:53:50.60#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.22:53:50.60#ibcon#*before write, iclass 30, count 0 2006.173.22:53:50.60#ibcon#enter sib2, iclass 30, count 0 2006.173.22:53:50.60#ibcon#flushed, iclass 30, count 0 2006.173.22:53:50.60#ibcon#about to write, iclass 30, count 0 2006.173.22:53:50.60#ibcon#wrote, iclass 30, count 0 2006.173.22:53:50.60#ibcon#about to read 3, iclass 30, count 0 2006.173.22:53:50.64#ibcon#read 3, iclass 30, count 0 2006.173.22:53:50.64#ibcon#about to read 4, iclass 30, count 0 2006.173.22:53:50.64#ibcon#read 4, iclass 30, count 0 2006.173.22:53:50.64#ibcon#about to read 5, iclass 30, count 0 2006.173.22:53:50.64#ibcon#read 5, iclass 30, count 0 2006.173.22:53:50.64#ibcon#about to read 6, iclass 30, count 0 2006.173.22:53:50.64#ibcon#read 6, iclass 30, count 0 2006.173.22:53:50.64#ibcon#end of sib2, iclass 30, count 0 2006.173.22:53:50.64#ibcon#*after write, iclass 30, count 0 2006.173.22:53:50.64#ibcon#*before return 0, iclass 30, count 0 2006.173.22:53:50.64#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.22:53:50.64#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.22:53:50.64#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.22:53:50.64#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.22:53:50.64$vck44/va=8,4 2006.173.22:53:50.64#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.173.22:53:50.64#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.173.22:53:50.64#ibcon#ireg 11 cls_cnt 2 2006.173.22:53:50.64#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.22:53:50.70#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.22:53:50.70#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.22:53:50.70#ibcon#enter wrdev, iclass 32, count 2 2006.173.22:53:50.70#ibcon#first serial, iclass 32, count 2 2006.173.22:53:50.70#ibcon#enter sib2, iclass 32, count 2 2006.173.22:53:50.70#ibcon#flushed, iclass 32, count 2 2006.173.22:53:50.70#ibcon#about to write, iclass 32, count 2 2006.173.22:53:50.70#ibcon#wrote, iclass 32, count 2 2006.173.22:53:50.70#ibcon#about to read 3, iclass 32, count 2 2006.173.22:53:50.72#ibcon#read 3, iclass 32, count 2 2006.173.22:53:50.72#ibcon#about to read 4, iclass 32, count 2 2006.173.22:53:50.72#ibcon#read 4, iclass 32, count 2 2006.173.22:53:50.72#ibcon#about to read 5, iclass 32, count 2 2006.173.22:53:50.72#ibcon#read 5, iclass 32, count 2 2006.173.22:53:50.72#ibcon#about to read 6, iclass 32, count 2 2006.173.22:53:50.72#ibcon#read 6, iclass 32, count 2 2006.173.22:53:50.72#ibcon#end of sib2, iclass 32, count 2 2006.173.22:53:50.72#ibcon#*mode == 0, iclass 32, count 2 2006.173.22:53:50.72#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.173.22:53:50.72#ibcon#[25=AT08-04\r\n] 2006.173.22:53:50.72#ibcon#*before write, iclass 32, count 2 2006.173.22:53:50.72#ibcon#enter sib2, iclass 32, count 2 2006.173.22:53:50.72#ibcon#flushed, iclass 32, count 2 2006.173.22:53:50.72#ibcon#about to write, iclass 32, count 2 2006.173.22:53:50.72#ibcon#wrote, iclass 32, count 2 2006.173.22:53:50.72#ibcon#about to read 3, iclass 32, count 2 2006.173.22:53:50.75#ibcon#read 3, iclass 32, count 2 2006.173.22:53:50.75#ibcon#about to read 4, iclass 32, count 2 2006.173.22:53:50.75#ibcon#read 4, iclass 32, count 2 2006.173.22:53:50.75#ibcon#about to read 5, iclass 32, count 2 2006.173.22:53:50.75#ibcon#read 5, iclass 32, count 2 2006.173.22:53:50.75#ibcon#about to read 6, iclass 32, count 2 2006.173.22:53:50.75#ibcon#read 6, iclass 32, count 2 2006.173.22:53:50.75#ibcon#end of sib2, iclass 32, count 2 2006.173.22:53:50.75#ibcon#*after write, iclass 32, count 2 2006.173.22:53:50.75#ibcon#*before return 0, iclass 32, count 2 2006.173.22:53:50.75#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.22:53:50.75#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.173.22:53:50.75#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.173.22:53:50.75#ibcon#ireg 7 cls_cnt 0 2006.173.22:53:50.75#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.22:53:50.87#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.22:53:50.87#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.22:53:50.87#ibcon#enter wrdev, iclass 32, count 0 2006.173.22:53:50.87#ibcon#first serial, iclass 32, count 0 2006.173.22:53:50.87#ibcon#enter sib2, iclass 32, count 0 2006.173.22:53:50.87#ibcon#flushed, iclass 32, count 0 2006.173.22:53:50.87#ibcon#about to write, iclass 32, count 0 2006.173.22:53:50.87#ibcon#wrote, iclass 32, count 0 2006.173.22:53:50.87#ibcon#about to read 3, iclass 32, count 0 2006.173.22:53:50.89#ibcon#read 3, iclass 32, count 0 2006.173.22:53:50.89#ibcon#about to read 4, iclass 32, count 0 2006.173.22:53:50.89#ibcon#read 4, iclass 32, count 0 2006.173.22:53:50.89#ibcon#about to read 5, iclass 32, count 0 2006.173.22:53:50.89#ibcon#read 5, iclass 32, count 0 2006.173.22:53:50.89#ibcon#about to read 6, iclass 32, count 0 2006.173.22:53:50.89#ibcon#read 6, iclass 32, count 0 2006.173.22:53:50.89#ibcon#end of sib2, iclass 32, count 0 2006.173.22:53:50.89#ibcon#*mode == 0, iclass 32, count 0 2006.173.22:53:50.89#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.22:53:50.89#ibcon#[25=USB\r\n] 2006.173.22:53:50.89#ibcon#*before write, iclass 32, count 0 2006.173.22:53:50.89#ibcon#enter sib2, iclass 32, count 0 2006.173.22:53:50.89#ibcon#flushed, iclass 32, count 0 2006.173.22:53:50.89#ibcon#about to write, iclass 32, count 0 2006.173.22:53:50.89#ibcon#wrote, iclass 32, count 0 2006.173.22:53:50.89#ibcon#about to read 3, iclass 32, count 0 2006.173.22:53:50.92#ibcon#read 3, iclass 32, count 0 2006.173.22:53:50.92#ibcon#about to read 4, iclass 32, count 0 2006.173.22:53:50.92#ibcon#read 4, iclass 32, count 0 2006.173.22:53:50.92#ibcon#about to read 5, iclass 32, count 0 2006.173.22:53:50.92#ibcon#read 5, iclass 32, count 0 2006.173.22:53:50.92#ibcon#about to read 6, iclass 32, count 0 2006.173.22:53:50.92#ibcon#read 6, iclass 32, count 0 2006.173.22:53:50.92#ibcon#end of sib2, iclass 32, count 0 2006.173.22:53:50.92#ibcon#*after write, iclass 32, count 0 2006.173.22:53:50.92#ibcon#*before return 0, iclass 32, count 0 2006.173.22:53:50.92#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.22:53:50.92#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.173.22:53:50.92#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.22:53:50.92#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.22:53:50.92$vck44/vblo=1,629.99 2006.173.22:53:50.92#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.22:53:50.92#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.22:53:50.92#ibcon#ireg 17 cls_cnt 0 2006.173.22:53:50.92#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.22:53:50.92#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.22:53:50.92#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.22:53:50.92#ibcon#enter wrdev, iclass 34, count 0 2006.173.22:53:50.92#ibcon#first serial, iclass 34, count 0 2006.173.22:53:50.92#ibcon#enter sib2, iclass 34, count 0 2006.173.22:53:50.92#ibcon#flushed, iclass 34, count 0 2006.173.22:53:50.92#ibcon#about to write, iclass 34, count 0 2006.173.22:53:50.92#ibcon#wrote, iclass 34, count 0 2006.173.22:53:50.92#ibcon#about to read 3, iclass 34, count 0 2006.173.22:53:50.94#ibcon#read 3, iclass 34, count 0 2006.173.22:53:50.94#ibcon#about to read 4, iclass 34, count 0 2006.173.22:53:50.94#ibcon#read 4, iclass 34, count 0 2006.173.22:53:50.94#ibcon#about to read 5, iclass 34, count 0 2006.173.22:53:50.94#ibcon#read 5, iclass 34, count 0 2006.173.22:53:50.94#ibcon#about to read 6, iclass 34, count 0 2006.173.22:53:50.94#ibcon#read 6, iclass 34, count 0 2006.173.22:53:50.94#ibcon#end of sib2, iclass 34, count 0 2006.173.22:53:50.94#ibcon#*mode == 0, iclass 34, count 0 2006.173.22:53:50.94#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.22:53:50.94#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.22:53:50.94#ibcon#*before write, iclass 34, count 0 2006.173.22:53:50.94#ibcon#enter sib2, iclass 34, count 0 2006.173.22:53:50.94#ibcon#flushed, iclass 34, count 0 2006.173.22:53:50.94#ibcon#about to write, iclass 34, count 0 2006.173.22:53:50.94#ibcon#wrote, iclass 34, count 0 2006.173.22:53:50.94#ibcon#about to read 3, iclass 34, count 0 2006.173.22:53:50.98#ibcon#read 3, iclass 34, count 0 2006.173.22:53:50.98#ibcon#about to read 4, iclass 34, count 0 2006.173.22:53:50.98#ibcon#read 4, iclass 34, count 0 2006.173.22:53:50.98#ibcon#about to read 5, iclass 34, count 0 2006.173.22:53:50.98#ibcon#read 5, iclass 34, count 0 2006.173.22:53:50.98#ibcon#about to read 6, iclass 34, count 0 2006.173.22:53:50.98#ibcon#read 6, iclass 34, count 0 2006.173.22:53:50.98#ibcon#end of sib2, iclass 34, count 0 2006.173.22:53:50.98#ibcon#*after write, iclass 34, count 0 2006.173.22:53:50.98#ibcon#*before return 0, iclass 34, count 0 2006.173.22:53:50.98#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.22:53:50.98#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.22:53:50.98#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.22:53:50.98#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.22:53:50.98$vck44/vb=1,4 2006.173.22:53:50.98#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.22:53:50.98#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.22:53:50.98#ibcon#ireg 11 cls_cnt 2 2006.173.22:53:50.98#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.22:53:50.98#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.22:53:50.98#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.22:53:50.98#ibcon#enter wrdev, iclass 36, count 2 2006.173.22:53:50.98#ibcon#first serial, iclass 36, count 2 2006.173.22:53:50.98#ibcon#enter sib2, iclass 36, count 2 2006.173.22:53:50.98#ibcon#flushed, iclass 36, count 2 2006.173.22:53:50.98#ibcon#about to write, iclass 36, count 2 2006.173.22:53:50.98#ibcon#wrote, iclass 36, count 2 2006.173.22:53:50.98#ibcon#about to read 3, iclass 36, count 2 2006.173.22:53:51.00#ibcon#read 3, iclass 36, count 2 2006.173.22:53:51.00#ibcon#about to read 4, iclass 36, count 2 2006.173.22:53:51.00#ibcon#read 4, iclass 36, count 2 2006.173.22:53:51.00#ibcon#about to read 5, iclass 36, count 2 2006.173.22:53:51.00#ibcon#read 5, iclass 36, count 2 2006.173.22:53:51.00#ibcon#about to read 6, iclass 36, count 2 2006.173.22:53:51.00#ibcon#read 6, iclass 36, count 2 2006.173.22:53:51.00#ibcon#end of sib2, iclass 36, count 2 2006.173.22:53:51.00#ibcon#*mode == 0, iclass 36, count 2 2006.173.22:53:51.00#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.22:53:51.00#ibcon#[27=AT01-04\r\n] 2006.173.22:53:51.00#ibcon#*before write, iclass 36, count 2 2006.173.22:53:51.00#ibcon#enter sib2, iclass 36, count 2 2006.173.22:53:51.00#ibcon#flushed, iclass 36, count 2 2006.173.22:53:51.00#ibcon#about to write, iclass 36, count 2 2006.173.22:53:51.00#ibcon#wrote, iclass 36, count 2 2006.173.22:53:51.00#ibcon#about to read 3, iclass 36, count 2 2006.173.22:53:51.03#ibcon#read 3, iclass 36, count 2 2006.173.22:53:51.03#ibcon#about to read 4, iclass 36, count 2 2006.173.22:53:51.03#ibcon#read 4, iclass 36, count 2 2006.173.22:53:51.03#ibcon#about to read 5, iclass 36, count 2 2006.173.22:53:51.03#ibcon#read 5, iclass 36, count 2 2006.173.22:53:51.03#ibcon#about to read 6, iclass 36, count 2 2006.173.22:53:51.03#ibcon#read 6, iclass 36, count 2 2006.173.22:53:51.03#ibcon#end of sib2, iclass 36, count 2 2006.173.22:53:51.03#ibcon#*after write, iclass 36, count 2 2006.173.22:53:51.03#ibcon#*before return 0, iclass 36, count 2 2006.173.22:53:51.03#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.22:53:51.03#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.22:53:51.03#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.22:53:51.03#ibcon#ireg 7 cls_cnt 0 2006.173.22:53:51.03#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.22:53:51.15#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.22:53:51.15#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.22:53:51.15#ibcon#enter wrdev, iclass 36, count 0 2006.173.22:53:51.15#ibcon#first serial, iclass 36, count 0 2006.173.22:53:51.15#ibcon#enter sib2, iclass 36, count 0 2006.173.22:53:51.15#ibcon#flushed, iclass 36, count 0 2006.173.22:53:51.15#ibcon#about to write, iclass 36, count 0 2006.173.22:53:51.15#ibcon#wrote, iclass 36, count 0 2006.173.22:53:51.15#ibcon#about to read 3, iclass 36, count 0 2006.173.22:53:51.17#ibcon#read 3, iclass 36, count 0 2006.173.22:53:51.17#ibcon#about to read 4, iclass 36, count 0 2006.173.22:53:51.17#ibcon#read 4, iclass 36, count 0 2006.173.22:53:51.17#ibcon#about to read 5, iclass 36, count 0 2006.173.22:53:51.17#ibcon#read 5, iclass 36, count 0 2006.173.22:53:51.17#ibcon#about to read 6, iclass 36, count 0 2006.173.22:53:51.17#ibcon#read 6, iclass 36, count 0 2006.173.22:53:51.17#ibcon#end of sib2, iclass 36, count 0 2006.173.22:53:51.17#ibcon#*mode == 0, iclass 36, count 0 2006.173.22:53:51.17#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.22:53:51.17#ibcon#[27=USB\r\n] 2006.173.22:53:51.17#ibcon#*before write, iclass 36, count 0 2006.173.22:53:51.17#ibcon#enter sib2, iclass 36, count 0 2006.173.22:53:51.17#ibcon#flushed, iclass 36, count 0 2006.173.22:53:51.17#ibcon#about to write, iclass 36, count 0 2006.173.22:53:51.17#ibcon#wrote, iclass 36, count 0 2006.173.22:53:51.17#ibcon#about to read 3, iclass 36, count 0 2006.173.22:53:51.20#ibcon#read 3, iclass 36, count 0 2006.173.22:53:51.20#ibcon#about to read 4, iclass 36, count 0 2006.173.22:53:51.20#ibcon#read 4, iclass 36, count 0 2006.173.22:53:51.20#ibcon#about to read 5, iclass 36, count 0 2006.173.22:53:51.20#ibcon#read 5, iclass 36, count 0 2006.173.22:53:51.20#ibcon#about to read 6, iclass 36, count 0 2006.173.22:53:51.20#ibcon#read 6, iclass 36, count 0 2006.173.22:53:51.20#ibcon#end of sib2, iclass 36, count 0 2006.173.22:53:51.20#ibcon#*after write, iclass 36, count 0 2006.173.22:53:51.20#ibcon#*before return 0, iclass 36, count 0 2006.173.22:53:51.20#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.22:53:51.20#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.22:53:51.20#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.22:53:51.20#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.22:53:51.20$vck44/vblo=2,634.99 2006.173.22:53:51.20#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.22:53:51.20#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.22:53:51.20#ibcon#ireg 17 cls_cnt 0 2006.173.22:53:51.20#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.22:53:51.20#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.22:53:51.20#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.22:53:51.20#ibcon#enter wrdev, iclass 38, count 0 2006.173.22:53:51.20#ibcon#first serial, iclass 38, count 0 2006.173.22:53:51.20#ibcon#enter sib2, iclass 38, count 0 2006.173.22:53:51.20#ibcon#flushed, iclass 38, count 0 2006.173.22:53:51.20#ibcon#about to write, iclass 38, count 0 2006.173.22:53:51.20#ibcon#wrote, iclass 38, count 0 2006.173.22:53:51.20#ibcon#about to read 3, iclass 38, count 0 2006.173.22:53:51.22#ibcon#read 3, iclass 38, count 0 2006.173.22:53:51.22#ibcon#about to read 4, iclass 38, count 0 2006.173.22:53:51.22#ibcon#read 4, iclass 38, count 0 2006.173.22:53:51.22#ibcon#about to read 5, iclass 38, count 0 2006.173.22:53:51.22#ibcon#read 5, iclass 38, count 0 2006.173.22:53:51.22#ibcon#about to read 6, iclass 38, count 0 2006.173.22:53:51.22#ibcon#read 6, iclass 38, count 0 2006.173.22:53:51.22#ibcon#end of sib2, iclass 38, count 0 2006.173.22:53:51.22#ibcon#*mode == 0, iclass 38, count 0 2006.173.22:53:51.22#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.22:53:51.22#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.22:53:51.22#ibcon#*before write, iclass 38, count 0 2006.173.22:53:51.22#ibcon#enter sib2, iclass 38, count 0 2006.173.22:53:51.22#ibcon#flushed, iclass 38, count 0 2006.173.22:53:51.22#ibcon#about to write, iclass 38, count 0 2006.173.22:53:51.22#ibcon#wrote, iclass 38, count 0 2006.173.22:53:51.22#ibcon#about to read 3, iclass 38, count 0 2006.173.22:53:51.26#ibcon#read 3, iclass 38, count 0 2006.173.22:53:51.26#ibcon#about to read 4, iclass 38, count 0 2006.173.22:53:51.26#ibcon#read 4, iclass 38, count 0 2006.173.22:53:51.26#ibcon#about to read 5, iclass 38, count 0 2006.173.22:53:51.26#ibcon#read 5, iclass 38, count 0 2006.173.22:53:51.26#ibcon#about to read 6, iclass 38, count 0 2006.173.22:53:51.26#ibcon#read 6, iclass 38, count 0 2006.173.22:53:51.26#ibcon#end of sib2, iclass 38, count 0 2006.173.22:53:51.26#ibcon#*after write, iclass 38, count 0 2006.173.22:53:51.26#ibcon#*before return 0, iclass 38, count 0 2006.173.22:53:51.26#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.22:53:51.26#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.22:53:51.26#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.22:53:51.26#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.22:53:51.26$vck44/vb=2,4 2006.173.22:53:51.26#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.22:53:51.26#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.22:53:51.26#ibcon#ireg 11 cls_cnt 2 2006.173.22:53:51.26#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.22:53:51.32#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.22:53:51.32#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.22:53:51.32#ibcon#enter wrdev, iclass 40, count 2 2006.173.22:53:51.32#ibcon#first serial, iclass 40, count 2 2006.173.22:53:51.32#ibcon#enter sib2, iclass 40, count 2 2006.173.22:53:51.32#ibcon#flushed, iclass 40, count 2 2006.173.22:53:51.32#ibcon#about to write, iclass 40, count 2 2006.173.22:53:51.32#ibcon#wrote, iclass 40, count 2 2006.173.22:53:51.32#ibcon#about to read 3, iclass 40, count 2 2006.173.22:53:51.34#ibcon#read 3, iclass 40, count 2 2006.173.22:53:51.34#ibcon#about to read 4, iclass 40, count 2 2006.173.22:53:51.34#ibcon#read 4, iclass 40, count 2 2006.173.22:53:51.34#ibcon#about to read 5, iclass 40, count 2 2006.173.22:53:51.34#ibcon#read 5, iclass 40, count 2 2006.173.22:53:51.34#ibcon#about to read 6, iclass 40, count 2 2006.173.22:53:51.34#ibcon#read 6, iclass 40, count 2 2006.173.22:53:51.34#ibcon#end of sib2, iclass 40, count 2 2006.173.22:53:51.34#ibcon#*mode == 0, iclass 40, count 2 2006.173.22:53:51.34#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.22:53:51.34#ibcon#[27=AT02-04\r\n] 2006.173.22:53:51.34#ibcon#*before write, iclass 40, count 2 2006.173.22:53:51.34#ibcon#enter sib2, iclass 40, count 2 2006.173.22:53:51.34#ibcon#flushed, iclass 40, count 2 2006.173.22:53:51.34#ibcon#about to write, iclass 40, count 2 2006.173.22:53:51.34#ibcon#wrote, iclass 40, count 2 2006.173.22:53:51.34#ibcon#about to read 3, iclass 40, count 2 2006.173.22:53:51.37#ibcon#read 3, iclass 40, count 2 2006.173.22:53:51.37#ibcon#about to read 4, iclass 40, count 2 2006.173.22:53:51.37#ibcon#read 4, iclass 40, count 2 2006.173.22:53:51.37#ibcon#about to read 5, iclass 40, count 2 2006.173.22:53:51.37#ibcon#read 5, iclass 40, count 2 2006.173.22:53:51.37#ibcon#about to read 6, iclass 40, count 2 2006.173.22:53:51.37#ibcon#read 6, iclass 40, count 2 2006.173.22:53:51.37#ibcon#end of sib2, iclass 40, count 2 2006.173.22:53:51.37#ibcon#*after write, iclass 40, count 2 2006.173.22:53:51.37#ibcon#*before return 0, iclass 40, count 2 2006.173.22:53:51.37#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.22:53:51.37#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.22:53:51.37#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.22:53:51.37#ibcon#ireg 7 cls_cnt 0 2006.173.22:53:51.37#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.22:53:51.49#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.22:53:51.49#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.22:53:51.49#ibcon#enter wrdev, iclass 40, count 0 2006.173.22:53:51.49#ibcon#first serial, iclass 40, count 0 2006.173.22:53:51.49#ibcon#enter sib2, iclass 40, count 0 2006.173.22:53:51.49#ibcon#flushed, iclass 40, count 0 2006.173.22:53:51.49#ibcon#about to write, iclass 40, count 0 2006.173.22:53:51.49#ibcon#wrote, iclass 40, count 0 2006.173.22:53:51.49#ibcon#about to read 3, iclass 40, count 0 2006.173.22:53:51.51#ibcon#read 3, iclass 40, count 0 2006.173.22:53:51.51#ibcon#about to read 4, iclass 40, count 0 2006.173.22:53:51.51#ibcon#read 4, iclass 40, count 0 2006.173.22:53:51.51#ibcon#about to read 5, iclass 40, count 0 2006.173.22:53:51.51#ibcon#read 5, iclass 40, count 0 2006.173.22:53:51.51#ibcon#about to read 6, iclass 40, count 0 2006.173.22:53:51.51#ibcon#read 6, iclass 40, count 0 2006.173.22:53:51.51#ibcon#end of sib2, iclass 40, count 0 2006.173.22:53:51.51#ibcon#*mode == 0, iclass 40, count 0 2006.173.22:53:51.51#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.22:53:51.51#ibcon#[27=USB\r\n] 2006.173.22:53:51.51#ibcon#*before write, iclass 40, count 0 2006.173.22:53:51.51#ibcon#enter sib2, iclass 40, count 0 2006.173.22:53:51.51#ibcon#flushed, iclass 40, count 0 2006.173.22:53:51.51#ibcon#about to write, iclass 40, count 0 2006.173.22:53:51.51#ibcon#wrote, iclass 40, count 0 2006.173.22:53:51.51#ibcon#about to read 3, iclass 40, count 0 2006.173.22:53:51.54#ibcon#read 3, iclass 40, count 0 2006.173.22:53:51.54#ibcon#about to read 4, iclass 40, count 0 2006.173.22:53:51.54#ibcon#read 4, iclass 40, count 0 2006.173.22:53:51.54#ibcon#about to read 5, iclass 40, count 0 2006.173.22:53:51.54#ibcon#read 5, iclass 40, count 0 2006.173.22:53:51.54#ibcon#about to read 6, iclass 40, count 0 2006.173.22:53:51.54#ibcon#read 6, iclass 40, count 0 2006.173.22:53:51.54#ibcon#end of sib2, iclass 40, count 0 2006.173.22:53:51.54#ibcon#*after write, iclass 40, count 0 2006.173.22:53:51.54#ibcon#*before return 0, iclass 40, count 0 2006.173.22:53:51.54#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.22:53:51.54#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.22:53:51.54#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.22:53:51.54#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.22:53:51.54$vck44/vblo=3,649.99 2006.173.22:53:51.54#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.22:53:51.54#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.22:53:51.54#ibcon#ireg 17 cls_cnt 0 2006.173.22:53:51.54#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.22:53:51.54#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.22:53:51.54#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.22:53:51.54#ibcon#enter wrdev, iclass 4, count 0 2006.173.22:53:51.54#ibcon#first serial, iclass 4, count 0 2006.173.22:53:51.54#ibcon#enter sib2, iclass 4, count 0 2006.173.22:53:51.54#ibcon#flushed, iclass 4, count 0 2006.173.22:53:51.54#ibcon#about to write, iclass 4, count 0 2006.173.22:53:51.54#ibcon#wrote, iclass 4, count 0 2006.173.22:53:51.54#ibcon#about to read 3, iclass 4, count 0 2006.173.22:53:51.56#ibcon#read 3, iclass 4, count 0 2006.173.22:53:51.56#ibcon#about to read 4, iclass 4, count 0 2006.173.22:53:51.56#ibcon#read 4, iclass 4, count 0 2006.173.22:53:51.56#ibcon#about to read 5, iclass 4, count 0 2006.173.22:53:51.56#ibcon#read 5, iclass 4, count 0 2006.173.22:53:51.56#ibcon#about to read 6, iclass 4, count 0 2006.173.22:53:51.56#ibcon#read 6, iclass 4, count 0 2006.173.22:53:51.56#ibcon#end of sib2, iclass 4, count 0 2006.173.22:53:51.56#ibcon#*mode == 0, iclass 4, count 0 2006.173.22:53:51.56#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.22:53:51.56#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.22:53:51.56#ibcon#*before write, iclass 4, count 0 2006.173.22:53:51.56#ibcon#enter sib2, iclass 4, count 0 2006.173.22:53:51.56#ibcon#flushed, iclass 4, count 0 2006.173.22:53:51.56#ibcon#about to write, iclass 4, count 0 2006.173.22:53:51.56#ibcon#wrote, iclass 4, count 0 2006.173.22:53:51.56#ibcon#about to read 3, iclass 4, count 0 2006.173.22:53:51.60#ibcon#read 3, iclass 4, count 0 2006.173.22:53:51.60#ibcon#about to read 4, iclass 4, count 0 2006.173.22:53:51.60#ibcon#read 4, iclass 4, count 0 2006.173.22:53:51.60#ibcon#about to read 5, iclass 4, count 0 2006.173.22:53:51.60#ibcon#read 5, iclass 4, count 0 2006.173.22:53:51.60#ibcon#about to read 6, iclass 4, count 0 2006.173.22:53:51.60#ibcon#read 6, iclass 4, count 0 2006.173.22:53:51.60#ibcon#end of sib2, iclass 4, count 0 2006.173.22:53:51.60#ibcon#*after write, iclass 4, count 0 2006.173.22:53:51.60#ibcon#*before return 0, iclass 4, count 0 2006.173.22:53:51.60#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.22:53:51.60#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.22:53:51.60#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.22:53:51.60#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.22:53:51.60$vck44/vb=3,4 2006.173.22:53:51.60#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.22:53:51.60#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.22:53:51.60#ibcon#ireg 11 cls_cnt 2 2006.173.22:53:51.60#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.22:53:51.66#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.22:53:51.66#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.22:53:51.66#ibcon#enter wrdev, iclass 6, count 2 2006.173.22:53:51.66#ibcon#first serial, iclass 6, count 2 2006.173.22:53:51.66#ibcon#enter sib2, iclass 6, count 2 2006.173.22:53:51.66#ibcon#flushed, iclass 6, count 2 2006.173.22:53:51.66#ibcon#about to write, iclass 6, count 2 2006.173.22:53:51.66#ibcon#wrote, iclass 6, count 2 2006.173.22:53:51.66#ibcon#about to read 3, iclass 6, count 2 2006.173.22:53:51.68#ibcon#read 3, iclass 6, count 2 2006.173.22:53:51.68#ibcon#about to read 4, iclass 6, count 2 2006.173.22:53:51.68#ibcon#read 4, iclass 6, count 2 2006.173.22:53:51.68#ibcon#about to read 5, iclass 6, count 2 2006.173.22:53:51.68#ibcon#read 5, iclass 6, count 2 2006.173.22:53:51.68#ibcon#about to read 6, iclass 6, count 2 2006.173.22:53:51.68#ibcon#read 6, iclass 6, count 2 2006.173.22:53:51.68#ibcon#end of sib2, iclass 6, count 2 2006.173.22:53:51.68#ibcon#*mode == 0, iclass 6, count 2 2006.173.22:53:51.68#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.22:53:51.68#ibcon#[27=AT03-04\r\n] 2006.173.22:53:51.68#ibcon#*before write, iclass 6, count 2 2006.173.22:53:51.68#ibcon#enter sib2, iclass 6, count 2 2006.173.22:53:51.68#ibcon#flushed, iclass 6, count 2 2006.173.22:53:51.68#ibcon#about to write, iclass 6, count 2 2006.173.22:53:51.68#ibcon#wrote, iclass 6, count 2 2006.173.22:53:51.68#ibcon#about to read 3, iclass 6, count 2 2006.173.22:53:51.71#ibcon#read 3, iclass 6, count 2 2006.173.22:53:51.71#ibcon#about to read 4, iclass 6, count 2 2006.173.22:53:51.71#ibcon#read 4, iclass 6, count 2 2006.173.22:53:51.71#ibcon#about to read 5, iclass 6, count 2 2006.173.22:53:51.71#ibcon#read 5, iclass 6, count 2 2006.173.22:53:51.71#ibcon#about to read 6, iclass 6, count 2 2006.173.22:53:51.71#ibcon#read 6, iclass 6, count 2 2006.173.22:53:51.71#ibcon#end of sib2, iclass 6, count 2 2006.173.22:53:51.71#ibcon#*after write, iclass 6, count 2 2006.173.22:53:51.71#ibcon#*before return 0, iclass 6, count 2 2006.173.22:53:51.71#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.22:53:51.71#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.22:53:51.71#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.22:53:51.71#ibcon#ireg 7 cls_cnt 0 2006.173.22:53:51.71#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.22:53:51.83#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.22:53:51.83#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.22:53:51.83#ibcon#enter wrdev, iclass 6, count 0 2006.173.22:53:51.83#ibcon#first serial, iclass 6, count 0 2006.173.22:53:51.83#ibcon#enter sib2, iclass 6, count 0 2006.173.22:53:51.83#ibcon#flushed, iclass 6, count 0 2006.173.22:53:51.83#ibcon#about to write, iclass 6, count 0 2006.173.22:53:51.83#ibcon#wrote, iclass 6, count 0 2006.173.22:53:51.83#ibcon#about to read 3, iclass 6, count 0 2006.173.22:53:51.85#ibcon#read 3, iclass 6, count 0 2006.173.22:53:51.85#ibcon#about to read 4, iclass 6, count 0 2006.173.22:53:51.85#ibcon#read 4, iclass 6, count 0 2006.173.22:53:51.85#ibcon#about to read 5, iclass 6, count 0 2006.173.22:53:51.85#ibcon#read 5, iclass 6, count 0 2006.173.22:53:51.85#ibcon#about to read 6, iclass 6, count 0 2006.173.22:53:51.85#ibcon#read 6, iclass 6, count 0 2006.173.22:53:51.85#ibcon#end of sib2, iclass 6, count 0 2006.173.22:53:51.85#ibcon#*mode == 0, iclass 6, count 0 2006.173.22:53:51.85#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.22:53:51.85#ibcon#[27=USB\r\n] 2006.173.22:53:51.85#ibcon#*before write, iclass 6, count 0 2006.173.22:53:51.85#ibcon#enter sib2, iclass 6, count 0 2006.173.22:53:51.85#ibcon#flushed, iclass 6, count 0 2006.173.22:53:51.85#ibcon#about to write, iclass 6, count 0 2006.173.22:53:51.85#ibcon#wrote, iclass 6, count 0 2006.173.22:53:51.85#ibcon#about to read 3, iclass 6, count 0 2006.173.22:53:51.88#ibcon#read 3, iclass 6, count 0 2006.173.22:53:51.88#ibcon#about to read 4, iclass 6, count 0 2006.173.22:53:51.88#ibcon#read 4, iclass 6, count 0 2006.173.22:53:51.88#ibcon#about to read 5, iclass 6, count 0 2006.173.22:53:51.88#ibcon#read 5, iclass 6, count 0 2006.173.22:53:51.88#ibcon#about to read 6, iclass 6, count 0 2006.173.22:53:51.88#ibcon#read 6, iclass 6, count 0 2006.173.22:53:51.88#ibcon#end of sib2, iclass 6, count 0 2006.173.22:53:51.88#ibcon#*after write, iclass 6, count 0 2006.173.22:53:51.88#ibcon#*before return 0, iclass 6, count 0 2006.173.22:53:51.88#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.22:53:51.88#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.22:53:51.88#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.22:53:51.88#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.22:53:51.88$vck44/vblo=4,679.99 2006.173.22:53:51.88#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.22:53:51.88#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.22:53:51.88#ibcon#ireg 17 cls_cnt 0 2006.173.22:53:51.88#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.22:53:51.88#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.22:53:51.88#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.22:53:51.88#ibcon#enter wrdev, iclass 10, count 0 2006.173.22:53:51.88#ibcon#first serial, iclass 10, count 0 2006.173.22:53:51.88#ibcon#enter sib2, iclass 10, count 0 2006.173.22:53:51.88#ibcon#flushed, iclass 10, count 0 2006.173.22:53:51.88#ibcon#about to write, iclass 10, count 0 2006.173.22:53:51.88#ibcon#wrote, iclass 10, count 0 2006.173.22:53:51.88#ibcon#about to read 3, iclass 10, count 0 2006.173.22:53:51.90#ibcon#read 3, iclass 10, count 0 2006.173.22:53:51.90#ibcon#about to read 4, iclass 10, count 0 2006.173.22:53:51.90#ibcon#read 4, iclass 10, count 0 2006.173.22:53:51.90#ibcon#about to read 5, iclass 10, count 0 2006.173.22:53:51.90#ibcon#read 5, iclass 10, count 0 2006.173.22:53:51.90#ibcon#about to read 6, iclass 10, count 0 2006.173.22:53:51.90#ibcon#read 6, iclass 10, count 0 2006.173.22:53:51.90#ibcon#end of sib2, iclass 10, count 0 2006.173.22:53:51.90#ibcon#*mode == 0, iclass 10, count 0 2006.173.22:53:51.90#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.22:53:51.90#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.22:53:51.90#ibcon#*before write, iclass 10, count 0 2006.173.22:53:51.90#ibcon#enter sib2, iclass 10, count 0 2006.173.22:53:51.90#ibcon#flushed, iclass 10, count 0 2006.173.22:53:51.90#ibcon#about to write, iclass 10, count 0 2006.173.22:53:51.90#ibcon#wrote, iclass 10, count 0 2006.173.22:53:51.90#ibcon#about to read 3, iclass 10, count 0 2006.173.22:53:51.94#ibcon#read 3, iclass 10, count 0 2006.173.22:53:51.94#ibcon#about to read 4, iclass 10, count 0 2006.173.22:53:51.94#ibcon#read 4, iclass 10, count 0 2006.173.22:53:51.94#ibcon#about to read 5, iclass 10, count 0 2006.173.22:53:51.94#ibcon#read 5, iclass 10, count 0 2006.173.22:53:51.94#ibcon#about to read 6, iclass 10, count 0 2006.173.22:53:51.94#ibcon#read 6, iclass 10, count 0 2006.173.22:53:51.94#ibcon#end of sib2, iclass 10, count 0 2006.173.22:53:51.94#ibcon#*after write, iclass 10, count 0 2006.173.22:53:51.94#ibcon#*before return 0, iclass 10, count 0 2006.173.22:53:51.94#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.22:53:51.94#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.22:53:51.94#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.22:53:51.94#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.22:53:51.94$vck44/vb=4,4 2006.173.22:53:51.94#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.22:53:51.94#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.22:53:51.94#ibcon#ireg 11 cls_cnt 2 2006.173.22:53:51.94#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.22:53:52.00#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.22:53:52.00#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.22:53:52.00#ibcon#enter wrdev, iclass 12, count 2 2006.173.22:53:52.00#ibcon#first serial, iclass 12, count 2 2006.173.22:53:52.00#ibcon#enter sib2, iclass 12, count 2 2006.173.22:53:52.00#ibcon#flushed, iclass 12, count 2 2006.173.22:53:52.00#ibcon#about to write, iclass 12, count 2 2006.173.22:53:52.00#ibcon#wrote, iclass 12, count 2 2006.173.22:53:52.00#ibcon#about to read 3, iclass 12, count 2 2006.173.22:53:52.02#ibcon#read 3, iclass 12, count 2 2006.173.22:53:52.02#ibcon#about to read 4, iclass 12, count 2 2006.173.22:53:52.02#ibcon#read 4, iclass 12, count 2 2006.173.22:53:52.02#ibcon#about to read 5, iclass 12, count 2 2006.173.22:53:52.02#ibcon#read 5, iclass 12, count 2 2006.173.22:53:52.02#ibcon#about to read 6, iclass 12, count 2 2006.173.22:53:52.02#ibcon#read 6, iclass 12, count 2 2006.173.22:53:52.02#ibcon#end of sib2, iclass 12, count 2 2006.173.22:53:52.02#ibcon#*mode == 0, iclass 12, count 2 2006.173.22:53:52.02#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.22:53:52.02#ibcon#[27=AT04-04\r\n] 2006.173.22:53:52.02#ibcon#*before write, iclass 12, count 2 2006.173.22:53:52.02#ibcon#enter sib2, iclass 12, count 2 2006.173.22:53:52.02#ibcon#flushed, iclass 12, count 2 2006.173.22:53:52.02#ibcon#about to write, iclass 12, count 2 2006.173.22:53:52.02#ibcon#wrote, iclass 12, count 2 2006.173.22:53:52.02#ibcon#about to read 3, iclass 12, count 2 2006.173.22:53:52.05#ibcon#read 3, iclass 12, count 2 2006.173.22:53:52.05#ibcon#about to read 4, iclass 12, count 2 2006.173.22:53:52.05#ibcon#read 4, iclass 12, count 2 2006.173.22:53:52.05#ibcon#about to read 5, iclass 12, count 2 2006.173.22:53:52.05#ibcon#read 5, iclass 12, count 2 2006.173.22:53:52.05#ibcon#about to read 6, iclass 12, count 2 2006.173.22:53:52.05#ibcon#read 6, iclass 12, count 2 2006.173.22:53:52.05#ibcon#end of sib2, iclass 12, count 2 2006.173.22:53:52.05#ibcon#*after write, iclass 12, count 2 2006.173.22:53:52.05#ibcon#*before return 0, iclass 12, count 2 2006.173.22:53:52.05#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.22:53:52.05#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.22:53:52.05#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.22:53:52.05#ibcon#ireg 7 cls_cnt 0 2006.173.22:53:52.05#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.22:53:52.17#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.22:53:52.17#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.22:53:52.17#ibcon#enter wrdev, iclass 12, count 0 2006.173.22:53:52.17#ibcon#first serial, iclass 12, count 0 2006.173.22:53:52.17#ibcon#enter sib2, iclass 12, count 0 2006.173.22:53:52.17#ibcon#flushed, iclass 12, count 0 2006.173.22:53:52.17#ibcon#about to write, iclass 12, count 0 2006.173.22:53:52.17#ibcon#wrote, iclass 12, count 0 2006.173.22:53:52.17#ibcon#about to read 3, iclass 12, count 0 2006.173.22:53:52.19#ibcon#read 3, iclass 12, count 0 2006.173.22:53:52.19#ibcon#about to read 4, iclass 12, count 0 2006.173.22:53:52.19#ibcon#read 4, iclass 12, count 0 2006.173.22:53:52.19#ibcon#about to read 5, iclass 12, count 0 2006.173.22:53:52.19#ibcon#read 5, iclass 12, count 0 2006.173.22:53:52.19#ibcon#about to read 6, iclass 12, count 0 2006.173.22:53:52.19#ibcon#read 6, iclass 12, count 0 2006.173.22:53:52.19#ibcon#end of sib2, iclass 12, count 0 2006.173.22:53:52.19#ibcon#*mode == 0, iclass 12, count 0 2006.173.22:53:52.19#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.22:53:52.19#ibcon#[27=USB\r\n] 2006.173.22:53:52.19#ibcon#*before write, iclass 12, count 0 2006.173.22:53:52.19#ibcon#enter sib2, iclass 12, count 0 2006.173.22:53:52.19#ibcon#flushed, iclass 12, count 0 2006.173.22:53:52.19#ibcon#about to write, iclass 12, count 0 2006.173.22:53:52.19#ibcon#wrote, iclass 12, count 0 2006.173.22:53:52.19#ibcon#about to read 3, iclass 12, count 0 2006.173.22:53:52.22#ibcon#read 3, iclass 12, count 0 2006.173.22:53:52.22#ibcon#about to read 4, iclass 12, count 0 2006.173.22:53:52.22#ibcon#read 4, iclass 12, count 0 2006.173.22:53:52.22#ibcon#about to read 5, iclass 12, count 0 2006.173.22:53:52.22#ibcon#read 5, iclass 12, count 0 2006.173.22:53:52.22#ibcon#about to read 6, iclass 12, count 0 2006.173.22:53:52.22#ibcon#read 6, iclass 12, count 0 2006.173.22:53:52.22#ibcon#end of sib2, iclass 12, count 0 2006.173.22:53:52.22#ibcon#*after write, iclass 12, count 0 2006.173.22:53:52.22#ibcon#*before return 0, iclass 12, count 0 2006.173.22:53:52.22#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.22:53:52.22#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.22:53:52.22#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.22:53:52.22#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.22:53:52.22$vck44/vblo=5,709.99 2006.173.22:53:52.22#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.22:53:52.22#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.22:53:52.22#ibcon#ireg 17 cls_cnt 0 2006.173.22:53:52.22#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.22:53:52.22#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.22:53:52.22#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.22:53:52.22#ibcon#enter wrdev, iclass 14, count 0 2006.173.22:53:52.22#ibcon#first serial, iclass 14, count 0 2006.173.22:53:52.22#ibcon#enter sib2, iclass 14, count 0 2006.173.22:53:52.22#ibcon#flushed, iclass 14, count 0 2006.173.22:53:52.22#ibcon#about to write, iclass 14, count 0 2006.173.22:53:52.22#ibcon#wrote, iclass 14, count 0 2006.173.22:53:52.22#ibcon#about to read 3, iclass 14, count 0 2006.173.22:53:52.24#ibcon#read 3, iclass 14, count 0 2006.173.22:53:52.24#ibcon#about to read 4, iclass 14, count 0 2006.173.22:53:52.24#ibcon#read 4, iclass 14, count 0 2006.173.22:53:52.24#ibcon#about to read 5, iclass 14, count 0 2006.173.22:53:52.24#ibcon#read 5, iclass 14, count 0 2006.173.22:53:52.24#ibcon#about to read 6, iclass 14, count 0 2006.173.22:53:52.24#ibcon#read 6, iclass 14, count 0 2006.173.22:53:52.24#ibcon#end of sib2, iclass 14, count 0 2006.173.22:53:52.24#ibcon#*mode == 0, iclass 14, count 0 2006.173.22:53:52.24#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.22:53:52.24#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.22:53:52.24#ibcon#*before write, iclass 14, count 0 2006.173.22:53:52.24#ibcon#enter sib2, iclass 14, count 0 2006.173.22:53:52.24#ibcon#flushed, iclass 14, count 0 2006.173.22:53:52.24#ibcon#about to write, iclass 14, count 0 2006.173.22:53:52.24#ibcon#wrote, iclass 14, count 0 2006.173.22:53:52.24#ibcon#about to read 3, iclass 14, count 0 2006.173.22:53:52.28#ibcon#read 3, iclass 14, count 0 2006.173.22:53:52.28#ibcon#about to read 4, iclass 14, count 0 2006.173.22:53:52.28#ibcon#read 4, iclass 14, count 0 2006.173.22:53:52.28#ibcon#about to read 5, iclass 14, count 0 2006.173.22:53:52.28#ibcon#read 5, iclass 14, count 0 2006.173.22:53:52.28#ibcon#about to read 6, iclass 14, count 0 2006.173.22:53:52.28#ibcon#read 6, iclass 14, count 0 2006.173.22:53:52.28#ibcon#end of sib2, iclass 14, count 0 2006.173.22:53:52.28#ibcon#*after write, iclass 14, count 0 2006.173.22:53:52.28#ibcon#*before return 0, iclass 14, count 0 2006.173.22:53:52.28#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.22:53:52.28#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.22:53:52.28#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.22:53:52.28#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.22:53:52.28$vck44/vb=5,4 2006.173.22:53:52.28#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.22:53:52.28#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.22:53:52.28#ibcon#ireg 11 cls_cnt 2 2006.173.22:53:52.28#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.22:53:52.34#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.22:53:52.34#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.22:53:52.34#ibcon#enter wrdev, iclass 16, count 2 2006.173.22:53:52.34#ibcon#first serial, iclass 16, count 2 2006.173.22:53:52.34#ibcon#enter sib2, iclass 16, count 2 2006.173.22:53:52.34#ibcon#flushed, iclass 16, count 2 2006.173.22:53:52.34#ibcon#about to write, iclass 16, count 2 2006.173.22:53:52.34#ibcon#wrote, iclass 16, count 2 2006.173.22:53:52.34#ibcon#about to read 3, iclass 16, count 2 2006.173.22:53:52.36#ibcon#read 3, iclass 16, count 2 2006.173.22:53:52.36#ibcon#about to read 4, iclass 16, count 2 2006.173.22:53:52.36#ibcon#read 4, iclass 16, count 2 2006.173.22:53:52.36#ibcon#about to read 5, iclass 16, count 2 2006.173.22:53:52.36#ibcon#read 5, iclass 16, count 2 2006.173.22:53:52.36#ibcon#about to read 6, iclass 16, count 2 2006.173.22:53:52.36#ibcon#read 6, iclass 16, count 2 2006.173.22:53:52.36#ibcon#end of sib2, iclass 16, count 2 2006.173.22:53:52.36#ibcon#*mode == 0, iclass 16, count 2 2006.173.22:53:52.36#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.22:53:52.36#ibcon#[27=AT05-04\r\n] 2006.173.22:53:52.36#ibcon#*before write, iclass 16, count 2 2006.173.22:53:52.36#ibcon#enter sib2, iclass 16, count 2 2006.173.22:53:52.36#ibcon#flushed, iclass 16, count 2 2006.173.22:53:52.36#ibcon#about to write, iclass 16, count 2 2006.173.22:53:52.36#ibcon#wrote, iclass 16, count 2 2006.173.22:53:52.36#ibcon#about to read 3, iclass 16, count 2 2006.173.22:53:52.39#ibcon#read 3, iclass 16, count 2 2006.173.22:53:52.39#ibcon#about to read 4, iclass 16, count 2 2006.173.22:53:52.39#ibcon#read 4, iclass 16, count 2 2006.173.22:53:52.39#ibcon#about to read 5, iclass 16, count 2 2006.173.22:53:52.39#ibcon#read 5, iclass 16, count 2 2006.173.22:53:52.39#ibcon#about to read 6, iclass 16, count 2 2006.173.22:53:52.39#ibcon#read 6, iclass 16, count 2 2006.173.22:53:52.39#ibcon#end of sib2, iclass 16, count 2 2006.173.22:53:52.39#ibcon#*after write, iclass 16, count 2 2006.173.22:53:52.39#ibcon#*before return 0, iclass 16, count 2 2006.173.22:53:52.39#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.22:53:52.39#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.22:53:52.39#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.22:53:52.39#ibcon#ireg 7 cls_cnt 0 2006.173.22:53:52.39#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.22:53:52.51#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.22:53:52.51#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.22:53:52.51#ibcon#enter wrdev, iclass 16, count 0 2006.173.22:53:52.51#ibcon#first serial, iclass 16, count 0 2006.173.22:53:52.51#ibcon#enter sib2, iclass 16, count 0 2006.173.22:53:52.51#ibcon#flushed, iclass 16, count 0 2006.173.22:53:52.51#ibcon#about to write, iclass 16, count 0 2006.173.22:53:52.51#ibcon#wrote, iclass 16, count 0 2006.173.22:53:52.51#ibcon#about to read 3, iclass 16, count 0 2006.173.22:53:52.53#ibcon#read 3, iclass 16, count 0 2006.173.22:53:52.53#ibcon#about to read 4, iclass 16, count 0 2006.173.22:53:52.53#ibcon#read 4, iclass 16, count 0 2006.173.22:53:52.53#ibcon#about to read 5, iclass 16, count 0 2006.173.22:53:52.53#ibcon#read 5, iclass 16, count 0 2006.173.22:53:52.53#ibcon#about to read 6, iclass 16, count 0 2006.173.22:53:52.53#ibcon#read 6, iclass 16, count 0 2006.173.22:53:52.53#ibcon#end of sib2, iclass 16, count 0 2006.173.22:53:52.53#ibcon#*mode == 0, iclass 16, count 0 2006.173.22:53:52.53#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.22:53:52.53#ibcon#[27=USB\r\n] 2006.173.22:53:52.53#ibcon#*before write, iclass 16, count 0 2006.173.22:53:52.53#ibcon#enter sib2, iclass 16, count 0 2006.173.22:53:52.53#ibcon#flushed, iclass 16, count 0 2006.173.22:53:52.53#ibcon#about to write, iclass 16, count 0 2006.173.22:53:52.53#ibcon#wrote, iclass 16, count 0 2006.173.22:53:52.53#ibcon#about to read 3, iclass 16, count 0 2006.173.22:53:52.56#ibcon#read 3, iclass 16, count 0 2006.173.22:53:52.56#ibcon#about to read 4, iclass 16, count 0 2006.173.22:53:52.56#ibcon#read 4, iclass 16, count 0 2006.173.22:53:52.56#ibcon#about to read 5, iclass 16, count 0 2006.173.22:53:52.56#ibcon#read 5, iclass 16, count 0 2006.173.22:53:52.56#ibcon#about to read 6, iclass 16, count 0 2006.173.22:53:52.56#ibcon#read 6, iclass 16, count 0 2006.173.22:53:52.56#ibcon#end of sib2, iclass 16, count 0 2006.173.22:53:52.56#ibcon#*after write, iclass 16, count 0 2006.173.22:53:52.56#ibcon#*before return 0, iclass 16, count 0 2006.173.22:53:52.56#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.22:53:52.56#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.22:53:52.56#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.22:53:52.56#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.22:53:52.56$vck44/vblo=6,719.99 2006.173.22:53:52.56#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.22:53:52.56#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.22:53:52.56#ibcon#ireg 17 cls_cnt 0 2006.173.22:53:52.56#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.22:53:52.56#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.22:53:52.56#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.22:53:52.56#ibcon#enter wrdev, iclass 18, count 0 2006.173.22:53:52.56#ibcon#first serial, iclass 18, count 0 2006.173.22:53:52.56#ibcon#enter sib2, iclass 18, count 0 2006.173.22:53:52.56#ibcon#flushed, iclass 18, count 0 2006.173.22:53:52.56#ibcon#about to write, iclass 18, count 0 2006.173.22:53:52.56#ibcon#wrote, iclass 18, count 0 2006.173.22:53:52.56#ibcon#about to read 3, iclass 18, count 0 2006.173.22:53:52.58#ibcon#read 3, iclass 18, count 0 2006.173.22:53:52.58#ibcon#about to read 4, iclass 18, count 0 2006.173.22:53:52.58#ibcon#read 4, iclass 18, count 0 2006.173.22:53:52.58#ibcon#about to read 5, iclass 18, count 0 2006.173.22:53:52.58#ibcon#read 5, iclass 18, count 0 2006.173.22:53:52.58#ibcon#about to read 6, iclass 18, count 0 2006.173.22:53:52.58#ibcon#read 6, iclass 18, count 0 2006.173.22:53:52.58#ibcon#end of sib2, iclass 18, count 0 2006.173.22:53:52.58#ibcon#*mode == 0, iclass 18, count 0 2006.173.22:53:52.58#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.22:53:52.58#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.22:53:52.58#ibcon#*before write, iclass 18, count 0 2006.173.22:53:52.58#ibcon#enter sib2, iclass 18, count 0 2006.173.22:53:52.58#ibcon#flushed, iclass 18, count 0 2006.173.22:53:52.58#ibcon#about to write, iclass 18, count 0 2006.173.22:53:52.58#ibcon#wrote, iclass 18, count 0 2006.173.22:53:52.58#ibcon#about to read 3, iclass 18, count 0 2006.173.22:53:52.62#ibcon#read 3, iclass 18, count 0 2006.173.22:53:52.62#ibcon#about to read 4, iclass 18, count 0 2006.173.22:53:52.62#ibcon#read 4, iclass 18, count 0 2006.173.22:53:52.62#ibcon#about to read 5, iclass 18, count 0 2006.173.22:53:52.62#ibcon#read 5, iclass 18, count 0 2006.173.22:53:52.62#ibcon#about to read 6, iclass 18, count 0 2006.173.22:53:52.62#ibcon#read 6, iclass 18, count 0 2006.173.22:53:52.62#ibcon#end of sib2, iclass 18, count 0 2006.173.22:53:52.62#ibcon#*after write, iclass 18, count 0 2006.173.22:53:52.62#ibcon#*before return 0, iclass 18, count 0 2006.173.22:53:52.62#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.22:53:52.62#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.22:53:52.62#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.22:53:52.62#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.22:53:52.62$vck44/vb=6,4 2006.173.22:53:52.62#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.22:53:52.62#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.22:53:52.62#ibcon#ireg 11 cls_cnt 2 2006.173.22:53:52.62#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.22:53:52.68#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.22:53:52.68#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.22:53:52.68#ibcon#enter wrdev, iclass 20, count 2 2006.173.22:53:52.68#ibcon#first serial, iclass 20, count 2 2006.173.22:53:52.68#ibcon#enter sib2, iclass 20, count 2 2006.173.22:53:52.68#ibcon#flushed, iclass 20, count 2 2006.173.22:53:52.68#ibcon#about to write, iclass 20, count 2 2006.173.22:53:52.68#ibcon#wrote, iclass 20, count 2 2006.173.22:53:52.68#ibcon#about to read 3, iclass 20, count 2 2006.173.22:53:52.70#ibcon#read 3, iclass 20, count 2 2006.173.22:53:52.70#ibcon#about to read 4, iclass 20, count 2 2006.173.22:53:52.70#ibcon#read 4, iclass 20, count 2 2006.173.22:53:52.70#ibcon#about to read 5, iclass 20, count 2 2006.173.22:53:52.70#ibcon#read 5, iclass 20, count 2 2006.173.22:53:52.70#ibcon#about to read 6, iclass 20, count 2 2006.173.22:53:52.70#ibcon#read 6, iclass 20, count 2 2006.173.22:53:52.70#ibcon#end of sib2, iclass 20, count 2 2006.173.22:53:52.70#ibcon#*mode == 0, iclass 20, count 2 2006.173.22:53:52.70#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.22:53:52.70#ibcon#[27=AT06-04\r\n] 2006.173.22:53:52.70#ibcon#*before write, iclass 20, count 2 2006.173.22:53:52.70#ibcon#enter sib2, iclass 20, count 2 2006.173.22:53:52.70#ibcon#flushed, iclass 20, count 2 2006.173.22:53:52.70#ibcon#about to write, iclass 20, count 2 2006.173.22:53:52.70#ibcon#wrote, iclass 20, count 2 2006.173.22:53:52.70#ibcon#about to read 3, iclass 20, count 2 2006.173.22:53:52.73#ibcon#read 3, iclass 20, count 2 2006.173.22:53:52.73#ibcon#about to read 4, iclass 20, count 2 2006.173.22:53:52.73#ibcon#read 4, iclass 20, count 2 2006.173.22:53:52.73#ibcon#about to read 5, iclass 20, count 2 2006.173.22:53:52.73#ibcon#read 5, iclass 20, count 2 2006.173.22:53:52.73#ibcon#about to read 6, iclass 20, count 2 2006.173.22:53:52.73#ibcon#read 6, iclass 20, count 2 2006.173.22:53:52.73#ibcon#end of sib2, iclass 20, count 2 2006.173.22:53:52.73#ibcon#*after write, iclass 20, count 2 2006.173.22:53:52.73#ibcon#*before return 0, iclass 20, count 2 2006.173.22:53:52.73#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.22:53:52.73#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.22:53:52.73#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.22:53:52.73#ibcon#ireg 7 cls_cnt 0 2006.173.22:53:52.73#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.22:53:52.85#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.22:53:52.85#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.22:53:52.85#ibcon#enter wrdev, iclass 20, count 0 2006.173.22:53:52.85#ibcon#first serial, iclass 20, count 0 2006.173.22:53:52.85#ibcon#enter sib2, iclass 20, count 0 2006.173.22:53:52.85#ibcon#flushed, iclass 20, count 0 2006.173.22:53:52.85#ibcon#about to write, iclass 20, count 0 2006.173.22:53:52.85#ibcon#wrote, iclass 20, count 0 2006.173.22:53:52.85#ibcon#about to read 3, iclass 20, count 0 2006.173.22:53:52.87#ibcon#read 3, iclass 20, count 0 2006.173.22:53:52.87#ibcon#about to read 4, iclass 20, count 0 2006.173.22:53:52.87#ibcon#read 4, iclass 20, count 0 2006.173.22:53:52.87#ibcon#about to read 5, iclass 20, count 0 2006.173.22:53:52.87#ibcon#read 5, iclass 20, count 0 2006.173.22:53:52.87#ibcon#about to read 6, iclass 20, count 0 2006.173.22:53:52.87#ibcon#read 6, iclass 20, count 0 2006.173.22:53:52.87#ibcon#end of sib2, iclass 20, count 0 2006.173.22:53:52.87#ibcon#*mode == 0, iclass 20, count 0 2006.173.22:53:52.87#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.22:53:52.87#ibcon#[27=USB\r\n] 2006.173.22:53:52.87#ibcon#*before write, iclass 20, count 0 2006.173.22:53:52.87#ibcon#enter sib2, iclass 20, count 0 2006.173.22:53:52.87#ibcon#flushed, iclass 20, count 0 2006.173.22:53:52.87#ibcon#about to write, iclass 20, count 0 2006.173.22:53:52.87#ibcon#wrote, iclass 20, count 0 2006.173.22:53:52.87#ibcon#about to read 3, iclass 20, count 0 2006.173.22:53:52.90#ibcon#read 3, iclass 20, count 0 2006.173.22:53:52.90#ibcon#about to read 4, iclass 20, count 0 2006.173.22:53:52.90#ibcon#read 4, iclass 20, count 0 2006.173.22:53:52.90#ibcon#about to read 5, iclass 20, count 0 2006.173.22:53:52.90#ibcon#read 5, iclass 20, count 0 2006.173.22:53:52.90#ibcon#about to read 6, iclass 20, count 0 2006.173.22:53:52.90#ibcon#read 6, iclass 20, count 0 2006.173.22:53:52.90#ibcon#end of sib2, iclass 20, count 0 2006.173.22:53:52.90#ibcon#*after write, iclass 20, count 0 2006.173.22:53:52.90#ibcon#*before return 0, iclass 20, count 0 2006.173.22:53:52.90#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.22:53:52.90#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.22:53:52.90#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.22:53:52.90#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.22:53:52.90$vck44/vblo=7,734.99 2006.173.22:53:52.90#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.22:53:52.90#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.22:53:52.90#ibcon#ireg 17 cls_cnt 0 2006.173.22:53:52.90#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.22:53:52.90#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.22:53:52.90#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.22:53:52.90#ibcon#enter wrdev, iclass 22, count 0 2006.173.22:53:52.90#ibcon#first serial, iclass 22, count 0 2006.173.22:53:52.90#ibcon#enter sib2, iclass 22, count 0 2006.173.22:53:52.90#ibcon#flushed, iclass 22, count 0 2006.173.22:53:52.90#ibcon#about to write, iclass 22, count 0 2006.173.22:53:52.90#ibcon#wrote, iclass 22, count 0 2006.173.22:53:52.90#ibcon#about to read 3, iclass 22, count 0 2006.173.22:53:52.92#ibcon#read 3, iclass 22, count 0 2006.173.22:53:52.92#ibcon#about to read 4, iclass 22, count 0 2006.173.22:53:52.92#ibcon#read 4, iclass 22, count 0 2006.173.22:53:52.92#ibcon#about to read 5, iclass 22, count 0 2006.173.22:53:52.92#ibcon#read 5, iclass 22, count 0 2006.173.22:53:52.92#ibcon#about to read 6, iclass 22, count 0 2006.173.22:53:52.92#ibcon#read 6, iclass 22, count 0 2006.173.22:53:52.92#ibcon#end of sib2, iclass 22, count 0 2006.173.22:53:52.92#ibcon#*mode == 0, iclass 22, count 0 2006.173.22:53:52.92#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.22:53:52.92#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.22:53:52.92#ibcon#*before write, iclass 22, count 0 2006.173.22:53:52.92#ibcon#enter sib2, iclass 22, count 0 2006.173.22:53:52.92#ibcon#flushed, iclass 22, count 0 2006.173.22:53:52.92#ibcon#about to write, iclass 22, count 0 2006.173.22:53:52.92#ibcon#wrote, iclass 22, count 0 2006.173.22:53:52.92#ibcon#about to read 3, iclass 22, count 0 2006.173.22:53:52.96#ibcon#read 3, iclass 22, count 0 2006.173.22:53:52.96#ibcon#about to read 4, iclass 22, count 0 2006.173.22:53:52.96#ibcon#read 4, iclass 22, count 0 2006.173.22:53:52.96#ibcon#about to read 5, iclass 22, count 0 2006.173.22:53:52.96#ibcon#read 5, iclass 22, count 0 2006.173.22:53:52.96#ibcon#about to read 6, iclass 22, count 0 2006.173.22:53:52.96#ibcon#read 6, iclass 22, count 0 2006.173.22:53:52.96#ibcon#end of sib2, iclass 22, count 0 2006.173.22:53:52.96#ibcon#*after write, iclass 22, count 0 2006.173.22:53:52.96#ibcon#*before return 0, iclass 22, count 0 2006.173.22:53:52.96#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.22:53:52.96#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.22:53:52.96#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.22:53:52.96#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.22:53:52.96$vck44/vb=7,4 2006.173.22:53:52.96#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.22:53:52.96#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.22:53:52.96#ibcon#ireg 11 cls_cnt 2 2006.173.22:53:52.96#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.22:53:53.02#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.22:53:53.02#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.22:53:53.02#ibcon#enter wrdev, iclass 24, count 2 2006.173.22:53:53.02#ibcon#first serial, iclass 24, count 2 2006.173.22:53:53.02#ibcon#enter sib2, iclass 24, count 2 2006.173.22:53:53.02#ibcon#flushed, iclass 24, count 2 2006.173.22:53:53.02#ibcon#about to write, iclass 24, count 2 2006.173.22:53:53.02#ibcon#wrote, iclass 24, count 2 2006.173.22:53:53.02#ibcon#about to read 3, iclass 24, count 2 2006.173.22:53:53.04#ibcon#read 3, iclass 24, count 2 2006.173.22:53:53.04#ibcon#about to read 4, iclass 24, count 2 2006.173.22:53:53.04#ibcon#read 4, iclass 24, count 2 2006.173.22:53:53.04#ibcon#about to read 5, iclass 24, count 2 2006.173.22:53:53.04#ibcon#read 5, iclass 24, count 2 2006.173.22:53:53.04#ibcon#about to read 6, iclass 24, count 2 2006.173.22:53:53.04#ibcon#read 6, iclass 24, count 2 2006.173.22:53:53.04#ibcon#end of sib2, iclass 24, count 2 2006.173.22:53:53.04#ibcon#*mode == 0, iclass 24, count 2 2006.173.22:53:53.04#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.22:53:53.04#ibcon#[27=AT07-04\r\n] 2006.173.22:53:53.04#ibcon#*before write, iclass 24, count 2 2006.173.22:53:53.04#ibcon#enter sib2, iclass 24, count 2 2006.173.22:53:53.04#ibcon#flushed, iclass 24, count 2 2006.173.22:53:53.04#ibcon#about to write, iclass 24, count 2 2006.173.22:53:53.04#ibcon#wrote, iclass 24, count 2 2006.173.22:53:53.04#ibcon#about to read 3, iclass 24, count 2 2006.173.22:53:53.07#ibcon#read 3, iclass 24, count 2 2006.173.22:53:53.07#ibcon#about to read 4, iclass 24, count 2 2006.173.22:53:53.07#ibcon#read 4, iclass 24, count 2 2006.173.22:53:53.07#ibcon#about to read 5, iclass 24, count 2 2006.173.22:53:53.07#ibcon#read 5, iclass 24, count 2 2006.173.22:53:53.07#ibcon#about to read 6, iclass 24, count 2 2006.173.22:53:53.07#ibcon#read 6, iclass 24, count 2 2006.173.22:53:53.07#ibcon#end of sib2, iclass 24, count 2 2006.173.22:53:53.07#ibcon#*after write, iclass 24, count 2 2006.173.22:53:53.07#ibcon#*before return 0, iclass 24, count 2 2006.173.22:53:53.07#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.22:53:53.07#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.22:53:53.07#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.22:53:53.07#ibcon#ireg 7 cls_cnt 0 2006.173.22:53:53.07#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.22:53:53.19#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.22:53:53.19#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.22:53:53.19#ibcon#enter wrdev, iclass 24, count 0 2006.173.22:53:53.19#ibcon#first serial, iclass 24, count 0 2006.173.22:53:53.19#ibcon#enter sib2, iclass 24, count 0 2006.173.22:53:53.19#ibcon#flushed, iclass 24, count 0 2006.173.22:53:53.19#ibcon#about to write, iclass 24, count 0 2006.173.22:53:53.19#ibcon#wrote, iclass 24, count 0 2006.173.22:53:53.19#ibcon#about to read 3, iclass 24, count 0 2006.173.22:53:53.21#ibcon#read 3, iclass 24, count 0 2006.173.22:53:53.21#ibcon#about to read 4, iclass 24, count 0 2006.173.22:53:53.21#ibcon#read 4, iclass 24, count 0 2006.173.22:53:53.21#ibcon#about to read 5, iclass 24, count 0 2006.173.22:53:53.21#ibcon#read 5, iclass 24, count 0 2006.173.22:53:53.21#ibcon#about to read 6, iclass 24, count 0 2006.173.22:53:53.21#ibcon#read 6, iclass 24, count 0 2006.173.22:53:53.21#ibcon#end of sib2, iclass 24, count 0 2006.173.22:53:53.21#ibcon#*mode == 0, iclass 24, count 0 2006.173.22:53:53.21#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.22:53:53.21#ibcon#[27=USB\r\n] 2006.173.22:53:53.21#ibcon#*before write, iclass 24, count 0 2006.173.22:53:53.21#ibcon#enter sib2, iclass 24, count 0 2006.173.22:53:53.21#ibcon#flushed, iclass 24, count 0 2006.173.22:53:53.21#ibcon#about to write, iclass 24, count 0 2006.173.22:53:53.21#ibcon#wrote, iclass 24, count 0 2006.173.22:53:53.21#ibcon#about to read 3, iclass 24, count 0 2006.173.22:53:53.24#ibcon#read 3, iclass 24, count 0 2006.173.22:53:53.24#ibcon#about to read 4, iclass 24, count 0 2006.173.22:53:53.24#ibcon#read 4, iclass 24, count 0 2006.173.22:53:53.24#ibcon#about to read 5, iclass 24, count 0 2006.173.22:53:53.24#ibcon#read 5, iclass 24, count 0 2006.173.22:53:53.24#ibcon#about to read 6, iclass 24, count 0 2006.173.22:53:53.24#ibcon#read 6, iclass 24, count 0 2006.173.22:53:53.24#ibcon#end of sib2, iclass 24, count 0 2006.173.22:53:53.24#ibcon#*after write, iclass 24, count 0 2006.173.22:53:53.24#ibcon#*before return 0, iclass 24, count 0 2006.173.22:53:53.24#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.22:53:53.24#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.22:53:53.24#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.22:53:53.24#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.22:53:53.24$vck44/vblo=8,744.99 2006.173.22:53:53.24#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.22:53:53.24#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.22:53:53.24#ibcon#ireg 17 cls_cnt 0 2006.173.22:53:53.24#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.22:53:53.24#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.22:53:53.24#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.22:53:53.24#ibcon#enter wrdev, iclass 26, count 0 2006.173.22:53:53.24#ibcon#first serial, iclass 26, count 0 2006.173.22:53:53.24#ibcon#enter sib2, iclass 26, count 0 2006.173.22:53:53.24#ibcon#flushed, iclass 26, count 0 2006.173.22:53:53.24#ibcon#about to write, iclass 26, count 0 2006.173.22:53:53.24#ibcon#wrote, iclass 26, count 0 2006.173.22:53:53.24#ibcon#about to read 3, iclass 26, count 0 2006.173.22:53:53.26#ibcon#read 3, iclass 26, count 0 2006.173.22:53:53.26#ibcon#about to read 4, iclass 26, count 0 2006.173.22:53:53.26#ibcon#read 4, iclass 26, count 0 2006.173.22:53:53.26#ibcon#about to read 5, iclass 26, count 0 2006.173.22:53:53.26#ibcon#read 5, iclass 26, count 0 2006.173.22:53:53.26#ibcon#about to read 6, iclass 26, count 0 2006.173.22:53:53.26#ibcon#read 6, iclass 26, count 0 2006.173.22:53:53.26#ibcon#end of sib2, iclass 26, count 0 2006.173.22:53:53.26#ibcon#*mode == 0, iclass 26, count 0 2006.173.22:53:53.26#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.22:53:53.26#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.22:53:53.26#ibcon#*before write, iclass 26, count 0 2006.173.22:53:53.26#ibcon#enter sib2, iclass 26, count 0 2006.173.22:53:53.26#ibcon#flushed, iclass 26, count 0 2006.173.22:53:53.26#ibcon#about to write, iclass 26, count 0 2006.173.22:53:53.26#ibcon#wrote, iclass 26, count 0 2006.173.22:53:53.26#ibcon#about to read 3, iclass 26, count 0 2006.173.22:53:53.30#ibcon#read 3, iclass 26, count 0 2006.173.22:53:53.30#ibcon#about to read 4, iclass 26, count 0 2006.173.22:53:53.30#ibcon#read 4, iclass 26, count 0 2006.173.22:53:53.30#ibcon#about to read 5, iclass 26, count 0 2006.173.22:53:53.30#ibcon#read 5, iclass 26, count 0 2006.173.22:53:53.30#ibcon#about to read 6, iclass 26, count 0 2006.173.22:53:53.30#ibcon#read 6, iclass 26, count 0 2006.173.22:53:53.30#ibcon#end of sib2, iclass 26, count 0 2006.173.22:53:53.30#ibcon#*after write, iclass 26, count 0 2006.173.22:53:53.30#ibcon#*before return 0, iclass 26, count 0 2006.173.22:53:53.30#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.22:53:53.30#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.22:53:53.30#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.22:53:53.30#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.22:53:53.30$vck44/vb=8,4 2006.173.22:53:53.30#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.22:53:53.30#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.22:53:53.30#ibcon#ireg 11 cls_cnt 2 2006.173.22:53:53.30#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.22:53:53.36#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.22:53:53.36#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.22:53:53.36#ibcon#enter wrdev, iclass 28, count 2 2006.173.22:53:53.36#ibcon#first serial, iclass 28, count 2 2006.173.22:53:53.36#ibcon#enter sib2, iclass 28, count 2 2006.173.22:53:53.36#ibcon#flushed, iclass 28, count 2 2006.173.22:53:53.36#ibcon#about to write, iclass 28, count 2 2006.173.22:53:53.36#ibcon#wrote, iclass 28, count 2 2006.173.22:53:53.36#ibcon#about to read 3, iclass 28, count 2 2006.173.22:53:53.38#ibcon#read 3, iclass 28, count 2 2006.173.22:53:53.38#ibcon#about to read 4, iclass 28, count 2 2006.173.22:53:53.38#ibcon#read 4, iclass 28, count 2 2006.173.22:53:53.38#ibcon#about to read 5, iclass 28, count 2 2006.173.22:53:53.38#ibcon#read 5, iclass 28, count 2 2006.173.22:53:53.38#ibcon#about to read 6, iclass 28, count 2 2006.173.22:53:53.38#ibcon#read 6, iclass 28, count 2 2006.173.22:53:53.38#ibcon#end of sib2, iclass 28, count 2 2006.173.22:53:53.38#ibcon#*mode == 0, iclass 28, count 2 2006.173.22:53:53.38#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.22:53:53.38#ibcon#[27=AT08-04\r\n] 2006.173.22:53:53.38#ibcon#*before write, iclass 28, count 2 2006.173.22:53:53.38#ibcon#enter sib2, iclass 28, count 2 2006.173.22:53:53.38#ibcon#flushed, iclass 28, count 2 2006.173.22:53:53.38#ibcon#about to write, iclass 28, count 2 2006.173.22:53:53.38#ibcon#wrote, iclass 28, count 2 2006.173.22:53:53.38#ibcon#about to read 3, iclass 28, count 2 2006.173.22:53:53.41#ibcon#read 3, iclass 28, count 2 2006.173.22:53:53.41#ibcon#about to read 4, iclass 28, count 2 2006.173.22:53:53.41#ibcon#read 4, iclass 28, count 2 2006.173.22:53:53.41#ibcon#about to read 5, iclass 28, count 2 2006.173.22:53:53.41#ibcon#read 5, iclass 28, count 2 2006.173.22:53:53.41#ibcon#about to read 6, iclass 28, count 2 2006.173.22:53:53.41#ibcon#read 6, iclass 28, count 2 2006.173.22:53:53.41#ibcon#end of sib2, iclass 28, count 2 2006.173.22:53:53.41#ibcon#*after write, iclass 28, count 2 2006.173.22:53:53.41#ibcon#*before return 0, iclass 28, count 2 2006.173.22:53:53.41#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.22:53:53.41#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.22:53:53.41#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.22:53:53.41#ibcon#ireg 7 cls_cnt 0 2006.173.22:53:53.41#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.22:53:53.53#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.22:53:53.53#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.22:53:53.53#ibcon#enter wrdev, iclass 28, count 0 2006.173.22:53:53.53#ibcon#first serial, iclass 28, count 0 2006.173.22:53:53.53#ibcon#enter sib2, iclass 28, count 0 2006.173.22:53:53.53#ibcon#flushed, iclass 28, count 0 2006.173.22:53:53.53#ibcon#about to write, iclass 28, count 0 2006.173.22:53:53.53#ibcon#wrote, iclass 28, count 0 2006.173.22:53:53.53#ibcon#about to read 3, iclass 28, count 0 2006.173.22:53:53.55#ibcon#read 3, iclass 28, count 0 2006.173.22:53:53.55#ibcon#about to read 4, iclass 28, count 0 2006.173.22:53:53.55#ibcon#read 4, iclass 28, count 0 2006.173.22:53:53.55#ibcon#about to read 5, iclass 28, count 0 2006.173.22:53:53.55#ibcon#read 5, iclass 28, count 0 2006.173.22:53:53.55#ibcon#about to read 6, iclass 28, count 0 2006.173.22:53:53.55#ibcon#read 6, iclass 28, count 0 2006.173.22:53:53.55#ibcon#end of sib2, iclass 28, count 0 2006.173.22:53:53.55#ibcon#*mode == 0, iclass 28, count 0 2006.173.22:53:53.55#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.22:53:53.55#ibcon#[27=USB\r\n] 2006.173.22:53:53.55#ibcon#*before write, iclass 28, count 0 2006.173.22:53:53.55#ibcon#enter sib2, iclass 28, count 0 2006.173.22:53:53.55#ibcon#flushed, iclass 28, count 0 2006.173.22:53:53.55#ibcon#about to write, iclass 28, count 0 2006.173.22:53:53.55#ibcon#wrote, iclass 28, count 0 2006.173.22:53:53.55#ibcon#about to read 3, iclass 28, count 0 2006.173.22:53:53.58#ibcon#read 3, iclass 28, count 0 2006.173.22:53:53.58#ibcon#about to read 4, iclass 28, count 0 2006.173.22:53:53.58#ibcon#read 4, iclass 28, count 0 2006.173.22:53:53.58#ibcon#about to read 5, iclass 28, count 0 2006.173.22:53:53.58#ibcon#read 5, iclass 28, count 0 2006.173.22:53:53.58#ibcon#about to read 6, iclass 28, count 0 2006.173.22:53:53.58#ibcon#read 6, iclass 28, count 0 2006.173.22:53:53.58#ibcon#end of sib2, iclass 28, count 0 2006.173.22:53:53.58#ibcon#*after write, iclass 28, count 0 2006.173.22:53:53.58#ibcon#*before return 0, iclass 28, count 0 2006.173.22:53:53.58#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.22:53:53.58#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.22:53:53.58#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.22:53:53.58#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.22:53:53.58$vck44/vabw=wide 2006.173.22:53:53.58#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.22:53:53.58#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.22:53:53.58#ibcon#ireg 8 cls_cnt 0 2006.173.22:53:53.58#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.22:53:53.58#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.22:53:53.58#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.22:53:53.58#ibcon#enter wrdev, iclass 30, count 0 2006.173.22:53:53.58#ibcon#first serial, iclass 30, count 0 2006.173.22:53:53.58#ibcon#enter sib2, iclass 30, count 0 2006.173.22:53:53.58#ibcon#flushed, iclass 30, count 0 2006.173.22:53:53.58#ibcon#about to write, iclass 30, count 0 2006.173.22:53:53.58#ibcon#wrote, iclass 30, count 0 2006.173.22:53:53.58#ibcon#about to read 3, iclass 30, count 0 2006.173.22:53:53.60#ibcon#read 3, iclass 30, count 0 2006.173.22:53:53.60#ibcon#about to read 4, iclass 30, count 0 2006.173.22:53:53.60#ibcon#read 4, iclass 30, count 0 2006.173.22:53:53.60#ibcon#about to read 5, iclass 30, count 0 2006.173.22:53:53.60#ibcon#read 5, iclass 30, count 0 2006.173.22:53:53.60#ibcon#about to read 6, iclass 30, count 0 2006.173.22:53:53.60#ibcon#read 6, iclass 30, count 0 2006.173.22:53:53.60#ibcon#end of sib2, iclass 30, count 0 2006.173.22:53:53.60#ibcon#*mode == 0, iclass 30, count 0 2006.173.22:53:53.60#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.22:53:53.60#ibcon#[25=BW32\r\n] 2006.173.22:53:53.60#ibcon#*before write, iclass 30, count 0 2006.173.22:53:53.60#ibcon#enter sib2, iclass 30, count 0 2006.173.22:53:53.60#ibcon#flushed, iclass 30, count 0 2006.173.22:53:53.60#ibcon#about to write, iclass 30, count 0 2006.173.22:53:53.60#ibcon#wrote, iclass 30, count 0 2006.173.22:53:53.60#ibcon#about to read 3, iclass 30, count 0 2006.173.22:53:53.63#ibcon#read 3, iclass 30, count 0 2006.173.22:53:53.63#ibcon#about to read 4, iclass 30, count 0 2006.173.22:53:53.63#ibcon#read 4, iclass 30, count 0 2006.173.22:53:53.63#ibcon#about to read 5, iclass 30, count 0 2006.173.22:53:53.63#ibcon#read 5, iclass 30, count 0 2006.173.22:53:53.63#ibcon#about to read 6, iclass 30, count 0 2006.173.22:53:53.63#ibcon#read 6, iclass 30, count 0 2006.173.22:53:53.63#ibcon#end of sib2, iclass 30, count 0 2006.173.22:53:53.63#ibcon#*after write, iclass 30, count 0 2006.173.22:53:53.63#ibcon#*before return 0, iclass 30, count 0 2006.173.22:53:53.63#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.22:53:53.63#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.22:53:53.63#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.22:53:53.63#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.22:53:53.63$vck44/vbbw=wide 2006.173.22:53:53.63#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.22:53:53.63#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.22:53:53.63#ibcon#ireg 8 cls_cnt 0 2006.173.22:53:53.63#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.22:53:53.70#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.22:53:53.70#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.22:53:53.70#ibcon#enter wrdev, iclass 32, count 0 2006.173.22:53:53.70#ibcon#first serial, iclass 32, count 0 2006.173.22:53:53.70#ibcon#enter sib2, iclass 32, count 0 2006.173.22:53:53.70#ibcon#flushed, iclass 32, count 0 2006.173.22:53:53.70#ibcon#about to write, iclass 32, count 0 2006.173.22:53:53.70#ibcon#wrote, iclass 32, count 0 2006.173.22:53:53.70#ibcon#about to read 3, iclass 32, count 0 2006.173.22:53:53.72#ibcon#read 3, iclass 32, count 0 2006.173.22:53:53.72#ibcon#about to read 4, iclass 32, count 0 2006.173.22:53:53.72#ibcon#read 4, iclass 32, count 0 2006.173.22:53:53.72#ibcon#about to read 5, iclass 32, count 0 2006.173.22:53:53.72#ibcon#read 5, iclass 32, count 0 2006.173.22:53:53.72#ibcon#about to read 6, iclass 32, count 0 2006.173.22:53:53.72#ibcon#read 6, iclass 32, count 0 2006.173.22:53:53.72#ibcon#end of sib2, iclass 32, count 0 2006.173.22:53:53.72#ibcon#*mode == 0, iclass 32, count 0 2006.173.22:53:53.72#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.22:53:53.72#ibcon#[27=BW32\r\n] 2006.173.22:53:53.72#ibcon#*before write, iclass 32, count 0 2006.173.22:53:53.72#ibcon#enter sib2, iclass 32, count 0 2006.173.22:53:53.72#ibcon#flushed, iclass 32, count 0 2006.173.22:53:53.72#ibcon#about to write, iclass 32, count 0 2006.173.22:53:53.72#ibcon#wrote, iclass 32, count 0 2006.173.22:53:53.72#ibcon#about to read 3, iclass 32, count 0 2006.173.22:53:53.75#ibcon#read 3, iclass 32, count 0 2006.173.22:53:53.75#ibcon#about to read 4, iclass 32, count 0 2006.173.22:53:53.75#ibcon#read 4, iclass 32, count 0 2006.173.22:53:53.75#ibcon#about to read 5, iclass 32, count 0 2006.173.22:53:53.75#ibcon#read 5, iclass 32, count 0 2006.173.22:53:53.75#ibcon#about to read 6, iclass 32, count 0 2006.173.22:53:53.75#ibcon#read 6, iclass 32, count 0 2006.173.22:53:53.75#ibcon#end of sib2, iclass 32, count 0 2006.173.22:53:53.75#ibcon#*after write, iclass 32, count 0 2006.173.22:53:53.75#ibcon#*before return 0, iclass 32, count 0 2006.173.22:53:53.75#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.22:53:53.75#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.22:53:53.75#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.22:53:53.75#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.22:53:53.75$setupk4/ifdk4 2006.173.22:53:53.75$ifdk4/lo= 2006.173.22:53:53.75$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.22:53:53.75$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.22:53:53.75$ifdk4/patch= 2006.173.22:53:53.75$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.22:53:53.75$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.22:53:53.75$setupk4/!*+20s 2006.173.22:53:54.75#abcon#<5=/11 0.7 2.0 22.64 911003.4\r\n> 2006.173.22:53:54.77#abcon#{5=INTERFACE CLEAR} 2006.173.22:53:54.83#abcon#[5=S1D000X0/0*\r\n] 2006.173.22:53:58.14#trakl#Source acquired 2006.173.22:53:58.14#flagr#flagr/antenna,acquired 2006.173.22:54:04.92#abcon#<5=/11 0.7 2.0 22.64 911003.4\r\n> 2006.173.22:54:04.94#abcon#{5=INTERFACE CLEAR} 2006.173.22:54:05.00#abcon#[5=S1D000X0/0*\r\n] 2006.173.22:54:08.25$setupk4/"tpicd 2006.173.22:54:08.25$setupk4/echo=off 2006.173.22:54:08.25$setupk4/xlog=off 2006.173.22:54:08.25:!2006.173.22:59:43 2006.173.22:59:43.00:preob 2006.173.22:59:44.13/onsource/TRACKING 2006.173.22:59:44.13:!2006.173.22:59:53 2006.173.22:59:53.00:"tape 2006.173.22:59:53.00:"st=record 2006.173.22:59:53.00:data_valid=on 2006.173.22:59:53.00:midob 2006.173.22:59:53.13/onsource/TRACKING 2006.173.22:59:53.13/wx/22.77,1003.3,91 2006.173.22:59:53.29/cable/+6.5124E-03 2006.173.22:59:54.38/va/01,07,usb,yes,36,39 2006.173.22:59:54.38/va/02,06,usb,yes,36,37 2006.173.22:59:54.38/va/03,05,usb,yes,45,47 2006.173.22:59:54.38/va/04,06,usb,yes,36,38 2006.173.22:59:54.38/va/05,04,usb,yes,29,29 2006.173.22:59:54.38/va/06,03,usb,yes,40,40 2006.173.22:59:54.38/va/07,04,usb,yes,32,34 2006.173.22:59:54.38/va/08,04,usb,yes,28,33 2006.173.22:59:54.61/valo/01,524.99,yes,locked 2006.173.22:59:54.61/valo/02,534.99,yes,locked 2006.173.22:59:54.61/valo/03,564.99,yes,locked 2006.173.22:59:54.61/valo/04,624.99,yes,locked 2006.173.22:59:54.61/valo/05,734.99,yes,locked 2006.173.22:59:54.61/valo/06,814.99,yes,locked 2006.173.22:59:54.61/valo/07,864.99,yes,locked 2006.173.22:59:54.61/valo/08,884.99,yes,locked 2006.173.22:59:55.70/vb/01,04,usb,yes,30,27 2006.173.22:59:55.70/vb/02,04,usb,yes,32,32 2006.173.22:59:55.70/vb/03,04,usb,yes,29,32 2006.173.22:59:55.70/vb/04,04,usb,yes,33,32 2006.173.22:59:55.70/vb/05,04,usb,yes,26,28 2006.173.22:59:55.70/vb/06,04,usb,yes,30,26 2006.173.22:59:55.70/vb/07,04,usb,yes,30,30 2006.173.22:59:55.70/vb/08,04,usb,yes,28,31 2006.173.22:59:55.93/vblo/01,629.99,yes,locked 2006.173.22:59:55.93/vblo/02,634.99,yes,locked 2006.173.22:59:55.93/vblo/03,649.99,yes,locked 2006.173.22:59:55.93/vblo/04,679.99,yes,locked 2006.173.22:59:55.93/vblo/05,709.99,yes,locked 2006.173.22:59:55.93/vblo/06,719.99,yes,locked 2006.173.22:59:55.93/vblo/07,734.99,yes,locked 2006.173.22:59:55.93/vblo/08,744.99,yes,locked 2006.173.22:59:56.08/vabw/8 2006.173.22:59:56.23/vbbw/8 2006.173.22:59:56.32/xfe/off,on,14.2 2006.173.22:59:56.70/ifatt/23,28,28,28 2006.173.22:59:57.08/fmout-gps/S +3.87E-07 2006.173.22:59:57.12:!2006.173.23:01:23 2006.173.23:01:23.00:data_valid=off 2006.173.23:01:23.00:"et 2006.173.23:01:23.00:!+3s 2006.173.23:01:26.01:"tape 2006.173.23:01:26.01:postob 2006.173.23:01:26.21/cable/+6.5130E-03 2006.173.23:01:26.21/wx/22.79,1003.3,92 2006.173.23:01:27.08/fmout-gps/S +3.87E-07 2006.173.23:01:27.08:scan_name=173-2305,jd0606,210 2006.173.23:01:27.08:source=3c446,222547.26,-045701.4,2000.0,ccw 2006.173.23:01:27.14#flagr#flagr/antenna,new-source 2006.173.23:01:28.14:checkk5 2006.173.23:01:28.50/chk_autoobs//k5ts1/ autoobs is running! 2006.173.23:01:28.88/chk_autoobs//k5ts2/ autoobs is running! 2006.173.23:01:29.29/chk_autoobs//k5ts3/ autoobs is running! 2006.173.23:01:29.69/chk_autoobs//k5ts4/ autoobs is running! 2006.173.23:01:30.07/chk_obsdata//k5ts1/T1732259??a.dat file size is correct (nominal:360MB, actual:356MB). 2006.173.23:01:30.47/chk_obsdata//k5ts2/T1732259??b.dat file size is correct (nominal:360MB, actual:356MB). 2006.173.23:01:30.87/chk_obsdata//k5ts3/T1732259??c.dat file size is correct (nominal:360MB, actual:356MB). 2006.173.23:01:31.28/chk_obsdata//k5ts4/T1732259??d.dat file size is correct (nominal:360MB, actual:356MB). 2006.173.23:01:32.02/k5log//k5ts1_log_newline 2006.173.23:01:32.77/k5log//k5ts2_log_newline 2006.173.23:01:33.47/k5log//k5ts3_log_newline 2006.173.23:01:34.19/k5log//k5ts4_log_newline 2006.173.23:01:34.22/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.23:01:34.22:setupk4=1 2006.173.23:01:34.22$setupk4/echo=on 2006.173.23:01:34.22$setupk4/pcalon 2006.173.23:01:34.22$pcalon/"no phase cal control is implemented here 2006.173.23:01:34.22$setupk4/"tpicd=stop 2006.173.23:01:34.22$setupk4/"rec=synch_on 2006.173.23:01:34.22$setupk4/"rec_mode=128 2006.173.23:01:34.22$setupk4/!* 2006.173.23:01:34.22$setupk4/recpk4 2006.173.23:01:34.22$recpk4/recpatch= 2006.173.23:01:34.22$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.23:01:34.22$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.23:01:34.22$setupk4/vck44 2006.173.23:01:34.22$vck44/valo=1,524.99 2006.173.23:01:34.22#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.23:01:34.22#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.23:01:34.22#ibcon#ireg 17 cls_cnt 0 2006.173.23:01:34.22#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.23:01:34.22#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.23:01:34.22#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.23:01:34.22#ibcon#enter wrdev, iclass 3, count 0 2006.173.23:01:34.22#ibcon#first serial, iclass 3, count 0 2006.173.23:01:34.22#ibcon#enter sib2, iclass 3, count 0 2006.173.23:01:34.22#ibcon#flushed, iclass 3, count 0 2006.173.23:01:34.22#ibcon#about to write, iclass 3, count 0 2006.173.23:01:34.22#ibcon#wrote, iclass 3, count 0 2006.173.23:01:34.22#ibcon#about to read 3, iclass 3, count 0 2006.173.23:01:34.24#ibcon#read 3, iclass 3, count 0 2006.173.23:01:34.24#ibcon#about to read 4, iclass 3, count 0 2006.173.23:01:34.24#ibcon#read 4, iclass 3, count 0 2006.173.23:01:34.24#ibcon#about to read 5, iclass 3, count 0 2006.173.23:01:34.24#ibcon#read 5, iclass 3, count 0 2006.173.23:01:34.24#ibcon#about to read 6, iclass 3, count 0 2006.173.23:01:34.24#ibcon#read 6, iclass 3, count 0 2006.173.23:01:34.24#ibcon#end of sib2, iclass 3, count 0 2006.173.23:01:34.24#ibcon#*mode == 0, iclass 3, count 0 2006.173.23:01:34.24#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.23:01:34.24#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.23:01:34.24#ibcon#*before write, iclass 3, count 0 2006.173.23:01:34.24#ibcon#enter sib2, iclass 3, count 0 2006.173.23:01:34.24#ibcon#flushed, iclass 3, count 0 2006.173.23:01:34.24#ibcon#about to write, iclass 3, count 0 2006.173.23:01:34.24#ibcon#wrote, iclass 3, count 0 2006.173.23:01:34.24#ibcon#about to read 3, iclass 3, count 0 2006.173.23:01:34.29#ibcon#read 3, iclass 3, count 0 2006.173.23:01:34.29#ibcon#about to read 4, iclass 3, count 0 2006.173.23:01:34.29#ibcon#read 4, iclass 3, count 0 2006.173.23:01:34.29#ibcon#about to read 5, iclass 3, count 0 2006.173.23:01:34.29#ibcon#read 5, iclass 3, count 0 2006.173.23:01:34.29#ibcon#about to read 6, iclass 3, count 0 2006.173.23:01:34.29#ibcon#read 6, iclass 3, count 0 2006.173.23:01:34.29#ibcon#end of sib2, iclass 3, count 0 2006.173.23:01:34.29#ibcon#*after write, iclass 3, count 0 2006.173.23:01:34.29#ibcon#*before return 0, iclass 3, count 0 2006.173.23:01:34.29#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.23:01:34.29#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.23:01:34.29#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.23:01:34.29#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.23:01:34.29$vck44/va=1,7 2006.173.23:01:34.29#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.23:01:34.29#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.23:01:34.29#ibcon#ireg 11 cls_cnt 2 2006.173.23:01:34.29#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.23:01:34.29#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.23:01:34.29#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.23:01:34.29#ibcon#enter wrdev, iclass 5, count 2 2006.173.23:01:34.29#ibcon#first serial, iclass 5, count 2 2006.173.23:01:34.29#ibcon#enter sib2, iclass 5, count 2 2006.173.23:01:34.29#ibcon#flushed, iclass 5, count 2 2006.173.23:01:34.29#ibcon#about to write, iclass 5, count 2 2006.173.23:01:34.29#ibcon#wrote, iclass 5, count 2 2006.173.23:01:34.29#ibcon#about to read 3, iclass 5, count 2 2006.173.23:01:34.31#ibcon#read 3, iclass 5, count 2 2006.173.23:01:34.31#ibcon#about to read 4, iclass 5, count 2 2006.173.23:01:34.31#ibcon#read 4, iclass 5, count 2 2006.173.23:01:34.31#ibcon#about to read 5, iclass 5, count 2 2006.173.23:01:34.31#ibcon#read 5, iclass 5, count 2 2006.173.23:01:34.31#ibcon#about to read 6, iclass 5, count 2 2006.173.23:01:34.31#ibcon#read 6, iclass 5, count 2 2006.173.23:01:34.31#ibcon#end of sib2, iclass 5, count 2 2006.173.23:01:34.31#ibcon#*mode == 0, iclass 5, count 2 2006.173.23:01:34.31#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.23:01:34.31#ibcon#[25=AT01-07\r\n] 2006.173.23:01:34.31#ibcon#*before write, iclass 5, count 2 2006.173.23:01:34.31#ibcon#enter sib2, iclass 5, count 2 2006.173.23:01:34.31#ibcon#flushed, iclass 5, count 2 2006.173.23:01:34.31#ibcon#about to write, iclass 5, count 2 2006.173.23:01:34.31#ibcon#wrote, iclass 5, count 2 2006.173.23:01:34.31#ibcon#about to read 3, iclass 5, count 2 2006.173.23:01:34.33#ibcon#read 3, iclass 5, count 2 2006.173.23:01:34.34#ibcon#about to read 4, iclass 5, count 2 2006.173.23:01:34.34#ibcon#read 4, iclass 5, count 2 2006.173.23:01:34.34#ibcon#about to read 5, iclass 5, count 2 2006.173.23:01:34.34#ibcon#read 5, iclass 5, count 2 2006.173.23:01:34.34#ibcon#about to read 6, iclass 5, count 2 2006.173.23:01:34.34#ibcon#read 6, iclass 5, count 2 2006.173.23:01:34.34#ibcon#end of sib2, iclass 5, count 2 2006.173.23:01:34.34#ibcon#*after write, iclass 5, count 2 2006.173.23:01:34.34#ibcon#*before return 0, iclass 5, count 2 2006.173.23:01:34.34#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.23:01:34.34#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.23:01:34.34#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.23:01:34.34#ibcon#ireg 7 cls_cnt 0 2006.173.23:01:34.34#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.23:01:34.46#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.23:01:34.46#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.23:01:34.46#ibcon#enter wrdev, iclass 5, count 0 2006.173.23:01:34.46#ibcon#first serial, iclass 5, count 0 2006.173.23:01:34.46#ibcon#enter sib2, iclass 5, count 0 2006.173.23:01:34.46#ibcon#flushed, iclass 5, count 0 2006.173.23:01:34.46#ibcon#about to write, iclass 5, count 0 2006.173.23:01:34.46#ibcon#wrote, iclass 5, count 0 2006.173.23:01:34.46#ibcon#about to read 3, iclass 5, count 0 2006.173.23:01:34.48#ibcon#read 3, iclass 5, count 0 2006.173.23:01:34.48#ibcon#about to read 4, iclass 5, count 0 2006.173.23:01:34.48#ibcon#read 4, iclass 5, count 0 2006.173.23:01:34.48#ibcon#about to read 5, iclass 5, count 0 2006.173.23:01:34.48#ibcon#read 5, iclass 5, count 0 2006.173.23:01:34.48#ibcon#about to read 6, iclass 5, count 0 2006.173.23:01:34.48#ibcon#read 6, iclass 5, count 0 2006.173.23:01:34.48#ibcon#end of sib2, iclass 5, count 0 2006.173.23:01:34.48#ibcon#*mode == 0, iclass 5, count 0 2006.173.23:01:34.48#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.23:01:34.48#ibcon#[25=USB\r\n] 2006.173.23:01:34.48#ibcon#*before write, iclass 5, count 0 2006.173.23:01:34.48#ibcon#enter sib2, iclass 5, count 0 2006.173.23:01:34.48#ibcon#flushed, iclass 5, count 0 2006.173.23:01:34.48#ibcon#about to write, iclass 5, count 0 2006.173.23:01:34.48#ibcon#wrote, iclass 5, count 0 2006.173.23:01:34.48#ibcon#about to read 3, iclass 5, count 0 2006.173.23:01:34.51#ibcon#read 3, iclass 5, count 0 2006.173.23:01:34.51#ibcon#about to read 4, iclass 5, count 0 2006.173.23:01:34.51#ibcon#read 4, iclass 5, count 0 2006.173.23:01:34.51#ibcon#about to read 5, iclass 5, count 0 2006.173.23:01:34.51#ibcon#read 5, iclass 5, count 0 2006.173.23:01:34.51#ibcon#about to read 6, iclass 5, count 0 2006.173.23:01:34.51#ibcon#read 6, iclass 5, count 0 2006.173.23:01:34.51#ibcon#end of sib2, iclass 5, count 0 2006.173.23:01:34.51#ibcon#*after write, iclass 5, count 0 2006.173.23:01:34.51#ibcon#*before return 0, iclass 5, count 0 2006.173.23:01:34.51#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.23:01:34.51#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.23:01:34.51#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.23:01:34.51#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.23:01:34.51$vck44/valo=2,534.99 2006.173.23:01:34.51#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.23:01:34.51#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.23:01:34.51#ibcon#ireg 17 cls_cnt 0 2006.173.23:01:34.51#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.23:01:34.51#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.23:01:34.51#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.23:01:34.51#ibcon#enter wrdev, iclass 7, count 0 2006.173.23:01:34.51#ibcon#first serial, iclass 7, count 0 2006.173.23:01:34.51#ibcon#enter sib2, iclass 7, count 0 2006.173.23:01:34.51#ibcon#flushed, iclass 7, count 0 2006.173.23:01:34.51#ibcon#about to write, iclass 7, count 0 2006.173.23:01:34.51#ibcon#wrote, iclass 7, count 0 2006.173.23:01:34.51#ibcon#about to read 3, iclass 7, count 0 2006.173.23:01:34.53#ibcon#read 3, iclass 7, count 0 2006.173.23:01:34.53#ibcon#about to read 4, iclass 7, count 0 2006.173.23:01:34.53#ibcon#read 4, iclass 7, count 0 2006.173.23:01:34.53#ibcon#about to read 5, iclass 7, count 0 2006.173.23:01:34.53#ibcon#read 5, iclass 7, count 0 2006.173.23:01:34.53#ibcon#about to read 6, iclass 7, count 0 2006.173.23:01:34.53#ibcon#read 6, iclass 7, count 0 2006.173.23:01:34.53#ibcon#end of sib2, iclass 7, count 0 2006.173.23:01:34.53#ibcon#*mode == 0, iclass 7, count 0 2006.173.23:01:34.53#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.23:01:34.53#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.23:01:34.53#ibcon#*before write, iclass 7, count 0 2006.173.23:01:34.53#ibcon#enter sib2, iclass 7, count 0 2006.173.23:01:34.53#ibcon#flushed, iclass 7, count 0 2006.173.23:01:34.53#ibcon#about to write, iclass 7, count 0 2006.173.23:01:34.53#ibcon#wrote, iclass 7, count 0 2006.173.23:01:34.53#ibcon#about to read 3, iclass 7, count 0 2006.173.23:01:34.57#ibcon#read 3, iclass 7, count 0 2006.173.23:01:34.57#ibcon#about to read 4, iclass 7, count 0 2006.173.23:01:34.57#ibcon#read 4, iclass 7, count 0 2006.173.23:01:34.57#ibcon#about to read 5, iclass 7, count 0 2006.173.23:01:34.57#ibcon#read 5, iclass 7, count 0 2006.173.23:01:34.57#ibcon#about to read 6, iclass 7, count 0 2006.173.23:01:34.57#ibcon#read 6, iclass 7, count 0 2006.173.23:01:34.57#ibcon#end of sib2, iclass 7, count 0 2006.173.23:01:34.57#ibcon#*after write, iclass 7, count 0 2006.173.23:01:34.57#ibcon#*before return 0, iclass 7, count 0 2006.173.23:01:34.57#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.23:01:34.57#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.23:01:34.57#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.23:01:34.57#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.23:01:34.57$vck44/va=2,6 2006.173.23:01:34.57#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.23:01:34.57#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.23:01:34.57#ibcon#ireg 11 cls_cnt 2 2006.173.23:01:34.57#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.23:01:34.62#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.23:01:34.63#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.23:01:34.63#ibcon#enter wrdev, iclass 11, count 2 2006.173.23:01:34.63#ibcon#first serial, iclass 11, count 2 2006.173.23:01:34.63#ibcon#enter sib2, iclass 11, count 2 2006.173.23:01:34.63#ibcon#flushed, iclass 11, count 2 2006.173.23:01:34.63#ibcon#about to write, iclass 11, count 2 2006.173.23:01:34.63#ibcon#wrote, iclass 11, count 2 2006.173.23:01:34.63#ibcon#about to read 3, iclass 11, count 2 2006.173.23:01:34.64#ibcon#read 3, iclass 11, count 2 2006.173.23:01:34.65#ibcon#about to read 4, iclass 11, count 2 2006.173.23:01:34.65#ibcon#read 4, iclass 11, count 2 2006.173.23:01:34.65#ibcon#about to read 5, iclass 11, count 2 2006.173.23:01:34.65#ibcon#read 5, iclass 11, count 2 2006.173.23:01:34.65#ibcon#about to read 6, iclass 11, count 2 2006.173.23:01:34.65#ibcon#read 6, iclass 11, count 2 2006.173.23:01:34.65#ibcon#end of sib2, iclass 11, count 2 2006.173.23:01:34.65#ibcon#*mode == 0, iclass 11, count 2 2006.173.23:01:34.65#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.23:01:34.65#ibcon#[25=AT02-06\r\n] 2006.173.23:01:34.65#ibcon#*before write, iclass 11, count 2 2006.173.23:01:34.65#ibcon#enter sib2, iclass 11, count 2 2006.173.23:01:34.65#ibcon#flushed, iclass 11, count 2 2006.173.23:01:34.65#ibcon#about to write, iclass 11, count 2 2006.173.23:01:34.65#ibcon#wrote, iclass 11, count 2 2006.173.23:01:34.65#ibcon#about to read 3, iclass 11, count 2 2006.173.23:01:34.68#ibcon#read 3, iclass 11, count 2 2006.173.23:01:34.68#ibcon#about to read 4, iclass 11, count 2 2006.173.23:01:34.68#ibcon#read 4, iclass 11, count 2 2006.173.23:01:34.68#ibcon#about to read 5, iclass 11, count 2 2006.173.23:01:34.68#ibcon#read 5, iclass 11, count 2 2006.173.23:01:34.68#ibcon#about to read 6, iclass 11, count 2 2006.173.23:01:34.68#ibcon#read 6, iclass 11, count 2 2006.173.23:01:34.68#ibcon#end of sib2, iclass 11, count 2 2006.173.23:01:34.68#ibcon#*after write, iclass 11, count 2 2006.173.23:01:34.68#ibcon#*before return 0, iclass 11, count 2 2006.173.23:01:34.68#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.23:01:34.68#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.23:01:34.68#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.23:01:34.68#ibcon#ireg 7 cls_cnt 0 2006.173.23:01:34.68#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.23:01:34.80#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.23:01:34.80#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.23:01:34.80#ibcon#enter wrdev, iclass 11, count 0 2006.173.23:01:34.80#ibcon#first serial, iclass 11, count 0 2006.173.23:01:34.80#ibcon#enter sib2, iclass 11, count 0 2006.173.23:01:34.80#ibcon#flushed, iclass 11, count 0 2006.173.23:01:34.80#ibcon#about to write, iclass 11, count 0 2006.173.23:01:34.80#ibcon#wrote, iclass 11, count 0 2006.173.23:01:34.80#ibcon#about to read 3, iclass 11, count 0 2006.173.23:01:34.81#ibcon#read 3, iclass 11, count 0 2006.173.23:01:34.82#ibcon#about to read 4, iclass 11, count 0 2006.173.23:01:34.82#ibcon#read 4, iclass 11, count 0 2006.173.23:01:34.82#ibcon#about to read 5, iclass 11, count 0 2006.173.23:01:34.82#ibcon#read 5, iclass 11, count 0 2006.173.23:01:34.82#ibcon#about to read 6, iclass 11, count 0 2006.173.23:01:34.82#ibcon#read 6, iclass 11, count 0 2006.173.23:01:34.82#ibcon#end of sib2, iclass 11, count 0 2006.173.23:01:34.82#ibcon#*mode == 0, iclass 11, count 0 2006.173.23:01:34.82#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.23:01:34.82#ibcon#[25=USB\r\n] 2006.173.23:01:34.82#ibcon#*before write, iclass 11, count 0 2006.173.23:01:34.82#ibcon#enter sib2, iclass 11, count 0 2006.173.23:01:34.82#ibcon#flushed, iclass 11, count 0 2006.173.23:01:34.82#ibcon#about to write, iclass 11, count 0 2006.173.23:01:34.82#ibcon#wrote, iclass 11, count 0 2006.173.23:01:34.82#ibcon#about to read 3, iclass 11, count 0 2006.173.23:01:34.84#ibcon#read 3, iclass 11, count 0 2006.173.23:01:34.85#ibcon#about to read 4, iclass 11, count 0 2006.173.23:01:34.85#ibcon#read 4, iclass 11, count 0 2006.173.23:01:34.85#ibcon#about to read 5, iclass 11, count 0 2006.173.23:01:34.85#ibcon#read 5, iclass 11, count 0 2006.173.23:01:34.85#ibcon#about to read 6, iclass 11, count 0 2006.173.23:01:34.85#ibcon#read 6, iclass 11, count 0 2006.173.23:01:34.85#ibcon#end of sib2, iclass 11, count 0 2006.173.23:01:34.85#ibcon#*after write, iclass 11, count 0 2006.173.23:01:34.85#ibcon#*before return 0, iclass 11, count 0 2006.173.23:01:34.85#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.23:01:34.85#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.23:01:34.85#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.23:01:34.85#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.23:01:34.85$vck44/valo=3,564.99 2006.173.23:01:34.85#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.23:01:34.85#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.23:01:34.85#ibcon#ireg 17 cls_cnt 0 2006.173.23:01:34.85#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.23:01:34.85#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.23:01:34.85#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.23:01:34.85#ibcon#enter wrdev, iclass 13, count 0 2006.173.23:01:34.85#ibcon#first serial, iclass 13, count 0 2006.173.23:01:34.85#ibcon#enter sib2, iclass 13, count 0 2006.173.23:01:34.85#ibcon#flushed, iclass 13, count 0 2006.173.23:01:34.85#ibcon#about to write, iclass 13, count 0 2006.173.23:01:34.85#ibcon#wrote, iclass 13, count 0 2006.173.23:01:34.85#ibcon#about to read 3, iclass 13, count 0 2006.173.23:01:34.87#ibcon#read 3, iclass 13, count 0 2006.173.23:01:34.87#ibcon#about to read 4, iclass 13, count 0 2006.173.23:01:34.87#ibcon#read 4, iclass 13, count 0 2006.173.23:01:34.87#ibcon#about to read 5, iclass 13, count 0 2006.173.23:01:34.87#ibcon#read 5, iclass 13, count 0 2006.173.23:01:34.87#ibcon#about to read 6, iclass 13, count 0 2006.173.23:01:34.87#ibcon#read 6, iclass 13, count 0 2006.173.23:01:34.87#ibcon#end of sib2, iclass 13, count 0 2006.173.23:01:34.87#ibcon#*mode == 0, iclass 13, count 0 2006.173.23:01:34.87#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.23:01:34.87#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.23:01:34.87#ibcon#*before write, iclass 13, count 0 2006.173.23:01:34.87#ibcon#enter sib2, iclass 13, count 0 2006.173.23:01:34.87#ibcon#flushed, iclass 13, count 0 2006.173.23:01:34.87#ibcon#about to write, iclass 13, count 0 2006.173.23:01:34.87#ibcon#wrote, iclass 13, count 0 2006.173.23:01:34.87#ibcon#about to read 3, iclass 13, count 0 2006.173.23:01:34.91#ibcon#read 3, iclass 13, count 0 2006.173.23:01:34.91#ibcon#about to read 4, iclass 13, count 0 2006.173.23:01:34.91#ibcon#read 4, iclass 13, count 0 2006.173.23:01:34.91#ibcon#about to read 5, iclass 13, count 0 2006.173.23:01:34.91#ibcon#read 5, iclass 13, count 0 2006.173.23:01:34.91#ibcon#about to read 6, iclass 13, count 0 2006.173.23:01:34.91#ibcon#read 6, iclass 13, count 0 2006.173.23:01:34.91#ibcon#end of sib2, iclass 13, count 0 2006.173.23:01:34.91#ibcon#*after write, iclass 13, count 0 2006.173.23:01:34.91#ibcon#*before return 0, iclass 13, count 0 2006.173.23:01:34.91#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.23:01:34.91#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.23:01:34.91#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.23:01:34.91#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.23:01:34.91$vck44/va=3,5 2006.173.23:01:34.91#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.23:01:34.91#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.23:01:34.91#ibcon#ireg 11 cls_cnt 2 2006.173.23:01:34.91#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.23:01:34.96#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.23:01:34.97#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.23:01:34.97#ibcon#enter wrdev, iclass 15, count 2 2006.173.23:01:34.97#ibcon#first serial, iclass 15, count 2 2006.173.23:01:34.97#ibcon#enter sib2, iclass 15, count 2 2006.173.23:01:34.97#ibcon#flushed, iclass 15, count 2 2006.173.23:01:34.97#ibcon#about to write, iclass 15, count 2 2006.173.23:01:34.97#ibcon#wrote, iclass 15, count 2 2006.173.23:01:34.97#ibcon#about to read 3, iclass 15, count 2 2006.173.23:01:34.98#ibcon#read 3, iclass 15, count 2 2006.173.23:01:34.99#ibcon#about to read 4, iclass 15, count 2 2006.173.23:01:34.99#ibcon#read 4, iclass 15, count 2 2006.173.23:01:34.99#ibcon#about to read 5, iclass 15, count 2 2006.173.23:01:34.99#ibcon#read 5, iclass 15, count 2 2006.173.23:01:34.99#ibcon#about to read 6, iclass 15, count 2 2006.173.23:01:34.99#ibcon#read 6, iclass 15, count 2 2006.173.23:01:34.99#ibcon#end of sib2, iclass 15, count 2 2006.173.23:01:34.99#ibcon#*mode == 0, iclass 15, count 2 2006.173.23:01:34.99#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.23:01:34.99#ibcon#[25=AT03-05\r\n] 2006.173.23:01:34.99#ibcon#*before write, iclass 15, count 2 2006.173.23:01:34.99#ibcon#enter sib2, iclass 15, count 2 2006.173.23:01:34.99#ibcon#flushed, iclass 15, count 2 2006.173.23:01:34.99#ibcon#about to write, iclass 15, count 2 2006.173.23:01:34.99#ibcon#wrote, iclass 15, count 2 2006.173.23:01:34.99#ibcon#about to read 3, iclass 15, count 2 2006.173.23:01:35.02#ibcon#read 3, iclass 15, count 2 2006.173.23:01:35.02#ibcon#about to read 4, iclass 15, count 2 2006.173.23:01:35.02#ibcon#read 4, iclass 15, count 2 2006.173.23:01:35.02#ibcon#about to read 5, iclass 15, count 2 2006.173.23:01:35.02#ibcon#read 5, iclass 15, count 2 2006.173.23:01:35.02#ibcon#about to read 6, iclass 15, count 2 2006.173.23:01:35.02#ibcon#read 6, iclass 15, count 2 2006.173.23:01:35.02#ibcon#end of sib2, iclass 15, count 2 2006.173.23:01:35.02#ibcon#*after write, iclass 15, count 2 2006.173.23:01:35.02#ibcon#*before return 0, iclass 15, count 2 2006.173.23:01:35.02#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.23:01:35.02#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.23:01:35.02#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.23:01:35.02#ibcon#ireg 7 cls_cnt 0 2006.173.23:01:35.02#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.23:01:35.14#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.23:01:35.14#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.23:01:35.14#ibcon#enter wrdev, iclass 15, count 0 2006.173.23:01:35.14#ibcon#first serial, iclass 15, count 0 2006.173.23:01:35.14#ibcon#enter sib2, iclass 15, count 0 2006.173.23:01:35.14#ibcon#flushed, iclass 15, count 0 2006.173.23:01:35.14#ibcon#about to write, iclass 15, count 0 2006.173.23:01:35.14#ibcon#wrote, iclass 15, count 0 2006.173.23:01:35.14#ibcon#about to read 3, iclass 15, count 0 2006.173.23:01:35.16#ibcon#read 3, iclass 15, count 0 2006.173.23:01:35.16#ibcon#about to read 4, iclass 15, count 0 2006.173.23:01:35.16#ibcon#read 4, iclass 15, count 0 2006.173.23:01:35.16#ibcon#about to read 5, iclass 15, count 0 2006.173.23:01:35.16#ibcon#read 5, iclass 15, count 0 2006.173.23:01:35.16#ibcon#about to read 6, iclass 15, count 0 2006.173.23:01:35.16#ibcon#read 6, iclass 15, count 0 2006.173.23:01:35.16#ibcon#end of sib2, iclass 15, count 0 2006.173.23:01:35.16#ibcon#*mode == 0, iclass 15, count 0 2006.173.23:01:35.16#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.23:01:35.16#ibcon#[25=USB\r\n] 2006.173.23:01:35.16#ibcon#*before write, iclass 15, count 0 2006.173.23:01:35.16#ibcon#enter sib2, iclass 15, count 0 2006.173.23:01:35.16#ibcon#flushed, iclass 15, count 0 2006.173.23:01:35.16#ibcon#about to write, iclass 15, count 0 2006.173.23:01:35.16#ibcon#wrote, iclass 15, count 0 2006.173.23:01:35.16#ibcon#about to read 3, iclass 15, count 0 2006.173.23:01:35.18#ibcon#read 3, iclass 15, count 0 2006.173.23:01:35.19#ibcon#about to read 4, iclass 15, count 0 2006.173.23:01:35.19#ibcon#read 4, iclass 15, count 0 2006.173.23:01:35.19#ibcon#about to read 5, iclass 15, count 0 2006.173.23:01:35.19#ibcon#read 5, iclass 15, count 0 2006.173.23:01:35.19#ibcon#about to read 6, iclass 15, count 0 2006.173.23:01:35.19#ibcon#read 6, iclass 15, count 0 2006.173.23:01:35.19#ibcon#end of sib2, iclass 15, count 0 2006.173.23:01:35.19#ibcon#*after write, iclass 15, count 0 2006.173.23:01:35.19#ibcon#*before return 0, iclass 15, count 0 2006.173.23:01:35.19#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.23:01:35.19#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.23:01:35.19#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.23:01:35.19#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.23:01:35.19$vck44/valo=4,624.99 2006.173.23:01:35.19#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.23:01:35.19#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.23:01:35.19#ibcon#ireg 17 cls_cnt 0 2006.173.23:01:35.19#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.23:01:35.19#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.23:01:35.19#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.23:01:35.19#ibcon#enter wrdev, iclass 17, count 0 2006.173.23:01:35.19#ibcon#first serial, iclass 17, count 0 2006.173.23:01:35.19#ibcon#enter sib2, iclass 17, count 0 2006.173.23:01:35.19#ibcon#flushed, iclass 17, count 0 2006.173.23:01:35.19#ibcon#about to write, iclass 17, count 0 2006.173.23:01:35.19#ibcon#wrote, iclass 17, count 0 2006.173.23:01:35.19#ibcon#about to read 3, iclass 17, count 0 2006.173.23:01:35.21#ibcon#read 3, iclass 17, count 0 2006.173.23:01:35.21#ibcon#about to read 4, iclass 17, count 0 2006.173.23:01:35.21#ibcon#read 4, iclass 17, count 0 2006.173.23:01:35.21#ibcon#about to read 5, iclass 17, count 0 2006.173.23:01:35.21#ibcon#read 5, iclass 17, count 0 2006.173.23:01:35.21#ibcon#about to read 6, iclass 17, count 0 2006.173.23:01:35.21#ibcon#read 6, iclass 17, count 0 2006.173.23:01:35.21#ibcon#end of sib2, iclass 17, count 0 2006.173.23:01:35.21#ibcon#*mode == 0, iclass 17, count 0 2006.173.23:01:35.21#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.23:01:35.21#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.23:01:35.21#ibcon#*before write, iclass 17, count 0 2006.173.23:01:35.21#ibcon#enter sib2, iclass 17, count 0 2006.173.23:01:35.21#ibcon#flushed, iclass 17, count 0 2006.173.23:01:35.21#ibcon#about to write, iclass 17, count 0 2006.173.23:01:35.21#ibcon#wrote, iclass 17, count 0 2006.173.23:01:35.21#ibcon#about to read 3, iclass 17, count 0 2006.173.23:01:35.25#ibcon#read 3, iclass 17, count 0 2006.173.23:01:35.25#ibcon#about to read 4, iclass 17, count 0 2006.173.23:01:35.25#ibcon#read 4, iclass 17, count 0 2006.173.23:01:35.25#ibcon#about to read 5, iclass 17, count 0 2006.173.23:01:35.25#ibcon#read 5, iclass 17, count 0 2006.173.23:01:35.25#ibcon#about to read 6, iclass 17, count 0 2006.173.23:01:35.25#ibcon#read 6, iclass 17, count 0 2006.173.23:01:35.25#ibcon#end of sib2, iclass 17, count 0 2006.173.23:01:35.25#ibcon#*after write, iclass 17, count 0 2006.173.23:01:35.25#ibcon#*before return 0, iclass 17, count 0 2006.173.23:01:35.25#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.23:01:35.25#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.23:01:35.25#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.23:01:35.25#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.23:01:35.25$vck44/va=4,6 2006.173.23:01:35.25#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.23:01:35.25#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.23:01:35.25#ibcon#ireg 11 cls_cnt 2 2006.173.23:01:35.25#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.23:01:35.30#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.23:01:35.31#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.23:01:35.31#ibcon#enter wrdev, iclass 19, count 2 2006.173.23:01:35.31#ibcon#first serial, iclass 19, count 2 2006.173.23:01:35.31#ibcon#enter sib2, iclass 19, count 2 2006.173.23:01:35.31#ibcon#flushed, iclass 19, count 2 2006.173.23:01:35.31#ibcon#about to write, iclass 19, count 2 2006.173.23:01:35.31#ibcon#wrote, iclass 19, count 2 2006.173.23:01:35.31#ibcon#about to read 3, iclass 19, count 2 2006.173.23:01:35.33#ibcon#read 3, iclass 19, count 2 2006.173.23:01:35.33#ibcon#about to read 4, iclass 19, count 2 2006.173.23:01:35.33#ibcon#read 4, iclass 19, count 2 2006.173.23:01:35.33#ibcon#about to read 5, iclass 19, count 2 2006.173.23:01:35.33#ibcon#read 5, iclass 19, count 2 2006.173.23:01:35.33#ibcon#about to read 6, iclass 19, count 2 2006.173.23:01:35.33#ibcon#read 6, iclass 19, count 2 2006.173.23:01:35.33#ibcon#end of sib2, iclass 19, count 2 2006.173.23:01:35.33#ibcon#*mode == 0, iclass 19, count 2 2006.173.23:01:35.33#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.23:01:35.33#ibcon#[25=AT04-06\r\n] 2006.173.23:01:35.33#ibcon#*before write, iclass 19, count 2 2006.173.23:01:35.33#ibcon#enter sib2, iclass 19, count 2 2006.173.23:01:35.33#ibcon#flushed, iclass 19, count 2 2006.173.23:01:35.33#ibcon#about to write, iclass 19, count 2 2006.173.23:01:35.33#ibcon#wrote, iclass 19, count 2 2006.173.23:01:35.33#ibcon#about to read 3, iclass 19, count 2 2006.173.23:01:35.36#ibcon#read 3, iclass 19, count 2 2006.173.23:01:35.36#ibcon#about to read 4, iclass 19, count 2 2006.173.23:01:35.36#ibcon#read 4, iclass 19, count 2 2006.173.23:01:35.36#ibcon#about to read 5, iclass 19, count 2 2006.173.23:01:35.36#ibcon#read 5, iclass 19, count 2 2006.173.23:01:35.36#ibcon#about to read 6, iclass 19, count 2 2006.173.23:01:35.36#ibcon#read 6, iclass 19, count 2 2006.173.23:01:35.36#ibcon#end of sib2, iclass 19, count 2 2006.173.23:01:35.36#ibcon#*after write, iclass 19, count 2 2006.173.23:01:35.36#ibcon#*before return 0, iclass 19, count 2 2006.173.23:01:35.36#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.23:01:35.36#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.23:01:35.36#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.23:01:35.36#ibcon#ireg 7 cls_cnt 0 2006.173.23:01:35.36#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.23:01:35.48#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.23:01:35.48#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.23:01:35.48#ibcon#enter wrdev, iclass 19, count 0 2006.173.23:01:35.48#ibcon#first serial, iclass 19, count 0 2006.173.23:01:35.48#ibcon#enter sib2, iclass 19, count 0 2006.173.23:01:35.48#ibcon#flushed, iclass 19, count 0 2006.173.23:01:35.48#ibcon#about to write, iclass 19, count 0 2006.173.23:01:35.48#ibcon#wrote, iclass 19, count 0 2006.173.23:01:35.48#ibcon#about to read 3, iclass 19, count 0 2006.173.23:01:35.50#ibcon#read 3, iclass 19, count 0 2006.173.23:01:35.50#ibcon#about to read 4, iclass 19, count 0 2006.173.23:01:35.50#ibcon#read 4, iclass 19, count 0 2006.173.23:01:35.50#ibcon#about to read 5, iclass 19, count 0 2006.173.23:01:35.50#ibcon#read 5, iclass 19, count 0 2006.173.23:01:35.50#ibcon#about to read 6, iclass 19, count 0 2006.173.23:01:35.50#ibcon#read 6, iclass 19, count 0 2006.173.23:01:35.50#ibcon#end of sib2, iclass 19, count 0 2006.173.23:01:35.50#ibcon#*mode == 0, iclass 19, count 0 2006.173.23:01:35.50#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.23:01:35.50#ibcon#[25=USB\r\n] 2006.173.23:01:35.50#ibcon#*before write, iclass 19, count 0 2006.173.23:01:35.50#ibcon#enter sib2, iclass 19, count 0 2006.173.23:01:35.50#ibcon#flushed, iclass 19, count 0 2006.173.23:01:35.50#ibcon#about to write, iclass 19, count 0 2006.173.23:01:35.50#ibcon#wrote, iclass 19, count 0 2006.173.23:01:35.50#ibcon#about to read 3, iclass 19, count 0 2006.173.23:01:35.53#ibcon#read 3, iclass 19, count 0 2006.173.23:01:35.53#ibcon#about to read 4, iclass 19, count 0 2006.173.23:01:35.53#ibcon#read 4, iclass 19, count 0 2006.173.23:01:35.53#ibcon#about to read 5, iclass 19, count 0 2006.173.23:01:35.53#ibcon#read 5, iclass 19, count 0 2006.173.23:01:35.53#ibcon#about to read 6, iclass 19, count 0 2006.173.23:01:35.53#ibcon#read 6, iclass 19, count 0 2006.173.23:01:35.53#ibcon#end of sib2, iclass 19, count 0 2006.173.23:01:35.53#ibcon#*after write, iclass 19, count 0 2006.173.23:01:35.53#ibcon#*before return 0, iclass 19, count 0 2006.173.23:01:35.53#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.23:01:35.53#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.23:01:35.53#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.23:01:35.53#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.23:01:35.53$vck44/valo=5,734.99 2006.173.23:01:35.53#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.23:01:35.53#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.23:01:35.53#ibcon#ireg 17 cls_cnt 0 2006.173.23:01:35.53#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.23:01:35.53#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.23:01:35.53#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.23:01:35.53#ibcon#enter wrdev, iclass 21, count 0 2006.173.23:01:35.53#ibcon#first serial, iclass 21, count 0 2006.173.23:01:35.53#ibcon#enter sib2, iclass 21, count 0 2006.173.23:01:35.53#ibcon#flushed, iclass 21, count 0 2006.173.23:01:35.53#ibcon#about to write, iclass 21, count 0 2006.173.23:01:35.53#ibcon#wrote, iclass 21, count 0 2006.173.23:01:35.53#ibcon#about to read 3, iclass 21, count 0 2006.173.23:01:35.55#ibcon#read 3, iclass 21, count 0 2006.173.23:01:35.55#ibcon#about to read 4, iclass 21, count 0 2006.173.23:01:35.55#ibcon#read 4, iclass 21, count 0 2006.173.23:01:35.55#ibcon#about to read 5, iclass 21, count 0 2006.173.23:01:35.55#ibcon#read 5, iclass 21, count 0 2006.173.23:01:35.55#ibcon#about to read 6, iclass 21, count 0 2006.173.23:01:35.55#ibcon#read 6, iclass 21, count 0 2006.173.23:01:35.55#ibcon#end of sib2, iclass 21, count 0 2006.173.23:01:35.55#ibcon#*mode == 0, iclass 21, count 0 2006.173.23:01:35.55#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.23:01:35.55#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.23:01:35.55#ibcon#*before write, iclass 21, count 0 2006.173.23:01:35.55#ibcon#enter sib2, iclass 21, count 0 2006.173.23:01:35.55#ibcon#flushed, iclass 21, count 0 2006.173.23:01:35.55#ibcon#about to write, iclass 21, count 0 2006.173.23:01:35.55#ibcon#wrote, iclass 21, count 0 2006.173.23:01:35.55#ibcon#about to read 3, iclass 21, count 0 2006.173.23:01:35.59#ibcon#read 3, iclass 21, count 0 2006.173.23:01:35.59#ibcon#about to read 4, iclass 21, count 0 2006.173.23:01:35.59#ibcon#read 4, iclass 21, count 0 2006.173.23:01:35.59#ibcon#about to read 5, iclass 21, count 0 2006.173.23:01:35.59#ibcon#read 5, iclass 21, count 0 2006.173.23:01:35.59#ibcon#about to read 6, iclass 21, count 0 2006.173.23:01:35.59#ibcon#read 6, iclass 21, count 0 2006.173.23:01:35.59#ibcon#end of sib2, iclass 21, count 0 2006.173.23:01:35.59#ibcon#*after write, iclass 21, count 0 2006.173.23:01:35.59#ibcon#*before return 0, iclass 21, count 0 2006.173.23:01:35.59#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.23:01:35.59#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.23:01:35.59#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.23:01:35.59#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.23:01:35.59$vck44/va=5,4 2006.173.23:01:35.59#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.23:01:35.59#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.23:01:35.59#ibcon#ireg 11 cls_cnt 2 2006.173.23:01:35.59#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.23:01:35.64#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.23:01:35.65#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.23:01:35.65#ibcon#enter wrdev, iclass 23, count 2 2006.173.23:01:35.65#ibcon#first serial, iclass 23, count 2 2006.173.23:01:35.65#ibcon#enter sib2, iclass 23, count 2 2006.173.23:01:35.65#ibcon#flushed, iclass 23, count 2 2006.173.23:01:35.65#ibcon#about to write, iclass 23, count 2 2006.173.23:01:35.65#ibcon#wrote, iclass 23, count 2 2006.173.23:01:35.65#ibcon#about to read 3, iclass 23, count 2 2006.173.23:01:35.67#ibcon#read 3, iclass 23, count 2 2006.173.23:01:35.67#ibcon#about to read 4, iclass 23, count 2 2006.173.23:01:35.67#ibcon#read 4, iclass 23, count 2 2006.173.23:01:35.67#ibcon#about to read 5, iclass 23, count 2 2006.173.23:01:35.67#ibcon#read 5, iclass 23, count 2 2006.173.23:01:35.67#ibcon#about to read 6, iclass 23, count 2 2006.173.23:01:35.67#ibcon#read 6, iclass 23, count 2 2006.173.23:01:35.67#ibcon#end of sib2, iclass 23, count 2 2006.173.23:01:35.67#ibcon#*mode == 0, iclass 23, count 2 2006.173.23:01:35.67#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.23:01:35.67#ibcon#[25=AT05-04\r\n] 2006.173.23:01:35.67#ibcon#*before write, iclass 23, count 2 2006.173.23:01:35.67#ibcon#enter sib2, iclass 23, count 2 2006.173.23:01:35.67#ibcon#flushed, iclass 23, count 2 2006.173.23:01:35.67#ibcon#about to write, iclass 23, count 2 2006.173.23:01:35.67#ibcon#wrote, iclass 23, count 2 2006.173.23:01:35.67#ibcon#about to read 3, iclass 23, count 2 2006.173.23:01:35.70#ibcon#read 3, iclass 23, count 2 2006.173.23:01:35.70#ibcon#about to read 4, iclass 23, count 2 2006.173.23:01:35.70#ibcon#read 4, iclass 23, count 2 2006.173.23:01:35.70#ibcon#about to read 5, iclass 23, count 2 2006.173.23:01:35.70#ibcon#read 5, iclass 23, count 2 2006.173.23:01:35.70#ibcon#about to read 6, iclass 23, count 2 2006.173.23:01:35.70#ibcon#read 6, iclass 23, count 2 2006.173.23:01:35.70#ibcon#end of sib2, iclass 23, count 2 2006.173.23:01:35.70#ibcon#*after write, iclass 23, count 2 2006.173.23:01:35.70#ibcon#*before return 0, iclass 23, count 2 2006.173.23:01:35.70#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.23:01:35.70#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.23:01:35.70#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.23:01:35.70#ibcon#ireg 7 cls_cnt 0 2006.173.23:01:35.70#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.23:01:35.81#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.23:01:35.82#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.23:01:35.82#ibcon#enter wrdev, iclass 23, count 0 2006.173.23:01:35.82#ibcon#first serial, iclass 23, count 0 2006.173.23:01:35.82#ibcon#enter sib2, iclass 23, count 0 2006.173.23:01:35.82#ibcon#flushed, iclass 23, count 0 2006.173.23:01:35.82#ibcon#about to write, iclass 23, count 0 2006.173.23:01:35.82#ibcon#wrote, iclass 23, count 0 2006.173.23:01:35.82#ibcon#about to read 3, iclass 23, count 0 2006.173.23:01:35.83#ibcon#read 3, iclass 23, count 0 2006.173.23:01:35.84#ibcon#about to read 4, iclass 23, count 0 2006.173.23:01:35.84#ibcon#read 4, iclass 23, count 0 2006.173.23:01:35.84#ibcon#about to read 5, iclass 23, count 0 2006.173.23:01:35.84#ibcon#read 5, iclass 23, count 0 2006.173.23:01:35.84#ibcon#about to read 6, iclass 23, count 0 2006.173.23:01:35.84#ibcon#read 6, iclass 23, count 0 2006.173.23:01:35.84#ibcon#end of sib2, iclass 23, count 0 2006.173.23:01:35.84#ibcon#*mode == 0, iclass 23, count 0 2006.173.23:01:35.84#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.23:01:35.84#ibcon#[25=USB\r\n] 2006.173.23:01:35.84#ibcon#*before write, iclass 23, count 0 2006.173.23:01:35.84#ibcon#enter sib2, iclass 23, count 0 2006.173.23:01:35.84#ibcon#flushed, iclass 23, count 0 2006.173.23:01:35.84#ibcon#about to write, iclass 23, count 0 2006.173.23:01:35.84#ibcon#wrote, iclass 23, count 0 2006.173.23:01:35.84#ibcon#about to read 3, iclass 23, count 0 2006.173.23:01:35.87#ibcon#read 3, iclass 23, count 0 2006.173.23:01:35.87#ibcon#about to read 4, iclass 23, count 0 2006.173.23:01:35.87#ibcon#read 4, iclass 23, count 0 2006.173.23:01:35.87#ibcon#about to read 5, iclass 23, count 0 2006.173.23:01:35.87#ibcon#read 5, iclass 23, count 0 2006.173.23:01:35.87#ibcon#about to read 6, iclass 23, count 0 2006.173.23:01:35.87#ibcon#read 6, iclass 23, count 0 2006.173.23:01:35.87#ibcon#end of sib2, iclass 23, count 0 2006.173.23:01:35.87#ibcon#*after write, iclass 23, count 0 2006.173.23:01:35.87#ibcon#*before return 0, iclass 23, count 0 2006.173.23:01:35.87#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.23:01:35.87#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.23:01:35.87#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.23:01:35.87#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.23:01:35.87$vck44/valo=6,814.99 2006.173.23:01:35.87#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.23:01:35.87#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.23:01:35.87#ibcon#ireg 17 cls_cnt 0 2006.173.23:01:35.87#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.23:01:35.87#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.23:01:35.87#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.23:01:35.87#ibcon#enter wrdev, iclass 25, count 0 2006.173.23:01:35.87#ibcon#first serial, iclass 25, count 0 2006.173.23:01:35.87#ibcon#enter sib2, iclass 25, count 0 2006.173.23:01:35.87#ibcon#flushed, iclass 25, count 0 2006.173.23:01:35.87#ibcon#about to write, iclass 25, count 0 2006.173.23:01:35.87#ibcon#wrote, iclass 25, count 0 2006.173.23:01:35.87#ibcon#about to read 3, iclass 25, count 0 2006.173.23:01:35.89#ibcon#read 3, iclass 25, count 0 2006.173.23:01:35.89#ibcon#about to read 4, iclass 25, count 0 2006.173.23:01:35.89#ibcon#read 4, iclass 25, count 0 2006.173.23:01:35.89#ibcon#about to read 5, iclass 25, count 0 2006.173.23:01:35.89#ibcon#read 5, iclass 25, count 0 2006.173.23:01:35.89#ibcon#about to read 6, iclass 25, count 0 2006.173.23:01:35.89#ibcon#read 6, iclass 25, count 0 2006.173.23:01:35.89#ibcon#end of sib2, iclass 25, count 0 2006.173.23:01:35.89#ibcon#*mode == 0, iclass 25, count 0 2006.173.23:01:35.89#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.23:01:35.89#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.23:01:35.89#ibcon#*before write, iclass 25, count 0 2006.173.23:01:35.89#ibcon#enter sib2, iclass 25, count 0 2006.173.23:01:35.89#ibcon#flushed, iclass 25, count 0 2006.173.23:01:35.89#ibcon#about to write, iclass 25, count 0 2006.173.23:01:35.89#ibcon#wrote, iclass 25, count 0 2006.173.23:01:35.89#ibcon#about to read 3, iclass 25, count 0 2006.173.23:01:35.92#ibcon#read 3, iclass 25, count 0 2006.173.23:01:35.93#ibcon#about to read 4, iclass 25, count 0 2006.173.23:01:35.93#ibcon#read 4, iclass 25, count 0 2006.173.23:01:35.93#ibcon#about to read 5, iclass 25, count 0 2006.173.23:01:35.93#ibcon#read 5, iclass 25, count 0 2006.173.23:01:35.93#ibcon#about to read 6, iclass 25, count 0 2006.173.23:01:35.93#ibcon#read 6, iclass 25, count 0 2006.173.23:01:35.93#ibcon#end of sib2, iclass 25, count 0 2006.173.23:01:35.93#ibcon#*after write, iclass 25, count 0 2006.173.23:01:35.93#ibcon#*before return 0, iclass 25, count 0 2006.173.23:01:35.93#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.23:01:35.93#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.23:01:35.93#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.23:01:35.93#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.23:01:35.93$vck44/va=6,3 2006.173.23:01:35.93#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.23:01:35.93#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.23:01:35.93#ibcon#ireg 11 cls_cnt 2 2006.173.23:01:35.93#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.23:01:35.98#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.23:01:35.99#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.23:01:35.99#ibcon#enter wrdev, iclass 27, count 2 2006.173.23:01:35.99#ibcon#first serial, iclass 27, count 2 2006.173.23:01:35.99#ibcon#enter sib2, iclass 27, count 2 2006.173.23:01:35.99#ibcon#flushed, iclass 27, count 2 2006.173.23:01:35.99#ibcon#about to write, iclass 27, count 2 2006.173.23:01:35.99#ibcon#wrote, iclass 27, count 2 2006.173.23:01:35.99#ibcon#about to read 3, iclass 27, count 2 2006.173.23:01:36.01#ibcon#read 3, iclass 27, count 2 2006.173.23:01:36.01#ibcon#about to read 4, iclass 27, count 2 2006.173.23:01:36.01#ibcon#read 4, iclass 27, count 2 2006.173.23:01:36.01#ibcon#about to read 5, iclass 27, count 2 2006.173.23:01:36.01#ibcon#read 5, iclass 27, count 2 2006.173.23:01:36.01#ibcon#about to read 6, iclass 27, count 2 2006.173.23:01:36.01#ibcon#read 6, iclass 27, count 2 2006.173.23:01:36.01#ibcon#end of sib2, iclass 27, count 2 2006.173.23:01:36.01#ibcon#*mode == 0, iclass 27, count 2 2006.173.23:01:36.01#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.23:01:36.01#ibcon#[25=AT06-03\r\n] 2006.173.23:01:36.01#ibcon#*before write, iclass 27, count 2 2006.173.23:01:36.01#ibcon#enter sib2, iclass 27, count 2 2006.173.23:01:36.01#ibcon#flushed, iclass 27, count 2 2006.173.23:01:36.01#ibcon#about to write, iclass 27, count 2 2006.173.23:01:36.01#ibcon#wrote, iclass 27, count 2 2006.173.23:01:36.01#ibcon#about to read 3, iclass 27, count 2 2006.173.23:01:36.03#ibcon#read 3, iclass 27, count 2 2006.173.23:01:36.04#ibcon#about to read 4, iclass 27, count 2 2006.173.23:01:36.04#ibcon#read 4, iclass 27, count 2 2006.173.23:01:36.04#ibcon#about to read 5, iclass 27, count 2 2006.173.23:01:36.04#ibcon#read 5, iclass 27, count 2 2006.173.23:01:36.04#ibcon#about to read 6, iclass 27, count 2 2006.173.23:01:36.04#ibcon#read 6, iclass 27, count 2 2006.173.23:01:36.04#ibcon#end of sib2, iclass 27, count 2 2006.173.23:01:36.04#ibcon#*after write, iclass 27, count 2 2006.173.23:01:36.04#ibcon#*before return 0, iclass 27, count 2 2006.173.23:01:36.04#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.23:01:36.04#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.23:01:36.04#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.23:01:36.04#ibcon#ireg 7 cls_cnt 0 2006.173.23:01:36.04#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.23:01:36.15#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.23:01:36.16#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.23:01:36.16#ibcon#enter wrdev, iclass 27, count 0 2006.173.23:01:36.16#ibcon#first serial, iclass 27, count 0 2006.173.23:01:36.16#ibcon#enter sib2, iclass 27, count 0 2006.173.23:01:36.16#ibcon#flushed, iclass 27, count 0 2006.173.23:01:36.16#ibcon#about to write, iclass 27, count 0 2006.173.23:01:36.16#ibcon#wrote, iclass 27, count 0 2006.173.23:01:36.16#ibcon#about to read 3, iclass 27, count 0 2006.173.23:01:36.17#ibcon#read 3, iclass 27, count 0 2006.173.23:01:36.18#ibcon#about to read 4, iclass 27, count 0 2006.173.23:01:36.18#ibcon#read 4, iclass 27, count 0 2006.173.23:01:36.18#ibcon#about to read 5, iclass 27, count 0 2006.173.23:01:36.18#ibcon#read 5, iclass 27, count 0 2006.173.23:01:36.18#ibcon#about to read 6, iclass 27, count 0 2006.173.23:01:36.18#ibcon#read 6, iclass 27, count 0 2006.173.23:01:36.18#ibcon#end of sib2, iclass 27, count 0 2006.173.23:01:36.18#ibcon#*mode == 0, iclass 27, count 0 2006.173.23:01:36.18#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.23:01:36.18#ibcon#[25=USB\r\n] 2006.173.23:01:36.18#ibcon#*before write, iclass 27, count 0 2006.173.23:01:36.18#ibcon#enter sib2, iclass 27, count 0 2006.173.23:01:36.18#ibcon#flushed, iclass 27, count 0 2006.173.23:01:36.18#ibcon#about to write, iclass 27, count 0 2006.173.23:01:36.18#ibcon#wrote, iclass 27, count 0 2006.173.23:01:36.18#ibcon#about to read 3, iclass 27, count 0 2006.173.23:01:36.20#ibcon#read 3, iclass 27, count 0 2006.173.23:01:36.21#ibcon#about to read 4, iclass 27, count 0 2006.173.23:01:36.21#ibcon#read 4, iclass 27, count 0 2006.173.23:01:36.21#ibcon#about to read 5, iclass 27, count 0 2006.173.23:01:36.21#ibcon#read 5, iclass 27, count 0 2006.173.23:01:36.21#ibcon#about to read 6, iclass 27, count 0 2006.173.23:01:36.21#ibcon#read 6, iclass 27, count 0 2006.173.23:01:36.21#ibcon#end of sib2, iclass 27, count 0 2006.173.23:01:36.21#ibcon#*after write, iclass 27, count 0 2006.173.23:01:36.21#ibcon#*before return 0, iclass 27, count 0 2006.173.23:01:36.21#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.23:01:36.21#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.23:01:36.21#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.23:01:36.21#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.23:01:36.21$vck44/valo=7,864.99 2006.173.23:01:36.21#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.23:01:36.21#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.23:01:36.21#ibcon#ireg 17 cls_cnt 0 2006.173.23:01:36.21#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.23:01:36.21#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.23:01:36.21#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.23:01:36.21#ibcon#enter wrdev, iclass 29, count 0 2006.173.23:01:36.21#ibcon#first serial, iclass 29, count 0 2006.173.23:01:36.21#ibcon#enter sib2, iclass 29, count 0 2006.173.23:01:36.21#ibcon#flushed, iclass 29, count 0 2006.173.23:01:36.21#ibcon#about to write, iclass 29, count 0 2006.173.23:01:36.21#ibcon#wrote, iclass 29, count 0 2006.173.23:01:36.21#ibcon#about to read 3, iclass 29, count 0 2006.173.23:01:36.23#ibcon#read 3, iclass 29, count 0 2006.173.23:01:36.23#ibcon#about to read 4, iclass 29, count 0 2006.173.23:01:36.23#ibcon#read 4, iclass 29, count 0 2006.173.23:01:36.23#ibcon#about to read 5, iclass 29, count 0 2006.173.23:01:36.23#ibcon#read 5, iclass 29, count 0 2006.173.23:01:36.23#ibcon#about to read 6, iclass 29, count 0 2006.173.23:01:36.23#ibcon#read 6, iclass 29, count 0 2006.173.23:01:36.23#ibcon#end of sib2, iclass 29, count 0 2006.173.23:01:36.23#ibcon#*mode == 0, iclass 29, count 0 2006.173.23:01:36.23#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.23:01:36.23#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.23:01:36.23#ibcon#*before write, iclass 29, count 0 2006.173.23:01:36.23#ibcon#enter sib2, iclass 29, count 0 2006.173.23:01:36.23#ibcon#flushed, iclass 29, count 0 2006.173.23:01:36.23#ibcon#about to write, iclass 29, count 0 2006.173.23:01:36.23#ibcon#wrote, iclass 29, count 0 2006.173.23:01:36.23#ibcon#about to read 3, iclass 29, count 0 2006.173.23:01:36.27#ibcon#read 3, iclass 29, count 0 2006.173.23:01:36.27#ibcon#about to read 4, iclass 29, count 0 2006.173.23:01:36.27#ibcon#read 4, iclass 29, count 0 2006.173.23:01:36.27#ibcon#about to read 5, iclass 29, count 0 2006.173.23:01:36.27#ibcon#read 5, iclass 29, count 0 2006.173.23:01:36.27#ibcon#about to read 6, iclass 29, count 0 2006.173.23:01:36.27#ibcon#read 6, iclass 29, count 0 2006.173.23:01:36.27#ibcon#end of sib2, iclass 29, count 0 2006.173.23:01:36.27#ibcon#*after write, iclass 29, count 0 2006.173.23:01:36.27#ibcon#*before return 0, iclass 29, count 0 2006.173.23:01:36.27#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.23:01:36.27#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.23:01:36.27#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.23:01:36.27#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.23:01:36.27$vck44/va=7,4 2006.173.23:01:36.27#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.23:01:36.27#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.23:01:36.27#ibcon#ireg 11 cls_cnt 2 2006.173.23:01:36.27#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.23:01:36.32#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.23:01:36.33#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.23:01:36.33#ibcon#enter wrdev, iclass 31, count 2 2006.173.23:01:36.33#ibcon#first serial, iclass 31, count 2 2006.173.23:01:36.33#ibcon#enter sib2, iclass 31, count 2 2006.173.23:01:36.33#ibcon#flushed, iclass 31, count 2 2006.173.23:01:36.33#ibcon#about to write, iclass 31, count 2 2006.173.23:01:36.33#ibcon#wrote, iclass 31, count 2 2006.173.23:01:36.33#ibcon#about to read 3, iclass 31, count 2 2006.173.23:01:36.34#ibcon#read 3, iclass 31, count 2 2006.173.23:01:36.35#ibcon#about to read 4, iclass 31, count 2 2006.173.23:01:36.35#ibcon#read 4, iclass 31, count 2 2006.173.23:01:36.35#ibcon#about to read 5, iclass 31, count 2 2006.173.23:01:36.35#ibcon#read 5, iclass 31, count 2 2006.173.23:01:36.35#ibcon#about to read 6, iclass 31, count 2 2006.173.23:01:36.35#ibcon#read 6, iclass 31, count 2 2006.173.23:01:36.35#ibcon#end of sib2, iclass 31, count 2 2006.173.23:01:36.35#ibcon#*mode == 0, iclass 31, count 2 2006.173.23:01:36.35#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.23:01:36.35#ibcon#[25=AT07-04\r\n] 2006.173.23:01:36.35#ibcon#*before write, iclass 31, count 2 2006.173.23:01:36.35#ibcon#enter sib2, iclass 31, count 2 2006.173.23:01:36.35#ibcon#flushed, iclass 31, count 2 2006.173.23:01:36.35#ibcon#about to write, iclass 31, count 2 2006.173.23:01:36.35#ibcon#wrote, iclass 31, count 2 2006.173.23:01:36.35#ibcon#about to read 3, iclass 31, count 2 2006.173.23:01:36.37#ibcon#read 3, iclass 31, count 2 2006.173.23:01:36.38#ibcon#about to read 4, iclass 31, count 2 2006.173.23:01:36.38#ibcon#read 4, iclass 31, count 2 2006.173.23:01:36.38#ibcon#about to read 5, iclass 31, count 2 2006.173.23:01:36.38#ibcon#read 5, iclass 31, count 2 2006.173.23:01:36.38#ibcon#about to read 6, iclass 31, count 2 2006.173.23:01:36.38#ibcon#read 6, iclass 31, count 2 2006.173.23:01:36.38#ibcon#end of sib2, iclass 31, count 2 2006.173.23:01:36.38#ibcon#*after write, iclass 31, count 2 2006.173.23:01:36.38#ibcon#*before return 0, iclass 31, count 2 2006.173.23:01:36.38#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.23:01:36.38#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.23:01:36.38#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.23:01:36.38#ibcon#ireg 7 cls_cnt 0 2006.173.23:01:36.38#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.23:01:36.49#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.23:01:36.50#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.23:01:36.50#ibcon#enter wrdev, iclass 31, count 0 2006.173.23:01:36.50#ibcon#first serial, iclass 31, count 0 2006.173.23:01:36.50#ibcon#enter sib2, iclass 31, count 0 2006.173.23:01:36.50#ibcon#flushed, iclass 31, count 0 2006.173.23:01:36.50#ibcon#about to write, iclass 31, count 0 2006.173.23:01:36.50#ibcon#wrote, iclass 31, count 0 2006.173.23:01:36.50#ibcon#about to read 3, iclass 31, count 0 2006.173.23:01:36.51#ibcon#read 3, iclass 31, count 0 2006.173.23:01:36.52#ibcon#about to read 4, iclass 31, count 0 2006.173.23:01:36.52#ibcon#read 4, iclass 31, count 0 2006.173.23:01:36.52#ibcon#about to read 5, iclass 31, count 0 2006.173.23:01:36.52#ibcon#read 5, iclass 31, count 0 2006.173.23:01:36.52#ibcon#about to read 6, iclass 31, count 0 2006.173.23:01:36.52#ibcon#read 6, iclass 31, count 0 2006.173.23:01:36.52#ibcon#end of sib2, iclass 31, count 0 2006.173.23:01:36.52#ibcon#*mode == 0, iclass 31, count 0 2006.173.23:01:36.52#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.23:01:36.52#ibcon#[25=USB\r\n] 2006.173.23:01:36.52#ibcon#*before write, iclass 31, count 0 2006.173.23:01:36.52#ibcon#enter sib2, iclass 31, count 0 2006.173.23:01:36.52#ibcon#flushed, iclass 31, count 0 2006.173.23:01:36.52#ibcon#about to write, iclass 31, count 0 2006.173.23:01:36.52#ibcon#wrote, iclass 31, count 0 2006.173.23:01:36.52#ibcon#about to read 3, iclass 31, count 0 2006.173.23:01:36.55#ibcon#read 3, iclass 31, count 0 2006.173.23:01:36.55#ibcon#about to read 4, iclass 31, count 0 2006.173.23:01:36.55#ibcon#read 4, iclass 31, count 0 2006.173.23:01:36.55#ibcon#about to read 5, iclass 31, count 0 2006.173.23:01:36.55#ibcon#read 5, iclass 31, count 0 2006.173.23:01:36.55#ibcon#about to read 6, iclass 31, count 0 2006.173.23:01:36.55#ibcon#read 6, iclass 31, count 0 2006.173.23:01:36.55#ibcon#end of sib2, iclass 31, count 0 2006.173.23:01:36.55#ibcon#*after write, iclass 31, count 0 2006.173.23:01:36.55#ibcon#*before return 0, iclass 31, count 0 2006.173.23:01:36.55#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.23:01:36.55#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.23:01:36.55#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.23:01:36.55#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.23:01:36.55$vck44/valo=8,884.99 2006.173.23:01:36.55#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.23:01:36.55#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.23:01:36.55#ibcon#ireg 17 cls_cnt 0 2006.173.23:01:36.55#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.23:01:36.55#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.23:01:36.55#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.23:01:36.55#ibcon#enter wrdev, iclass 33, count 0 2006.173.23:01:36.55#ibcon#first serial, iclass 33, count 0 2006.173.23:01:36.55#ibcon#enter sib2, iclass 33, count 0 2006.173.23:01:36.55#ibcon#flushed, iclass 33, count 0 2006.173.23:01:36.55#ibcon#about to write, iclass 33, count 0 2006.173.23:01:36.55#ibcon#wrote, iclass 33, count 0 2006.173.23:01:36.55#ibcon#about to read 3, iclass 33, count 0 2006.173.23:01:36.57#ibcon#read 3, iclass 33, count 0 2006.173.23:01:36.57#ibcon#about to read 4, iclass 33, count 0 2006.173.23:01:36.57#ibcon#read 4, iclass 33, count 0 2006.173.23:01:36.57#ibcon#about to read 5, iclass 33, count 0 2006.173.23:01:36.57#ibcon#read 5, iclass 33, count 0 2006.173.23:01:36.57#ibcon#about to read 6, iclass 33, count 0 2006.173.23:01:36.57#ibcon#read 6, iclass 33, count 0 2006.173.23:01:36.57#ibcon#end of sib2, iclass 33, count 0 2006.173.23:01:36.57#ibcon#*mode == 0, iclass 33, count 0 2006.173.23:01:36.57#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.23:01:36.57#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.23:01:36.57#ibcon#*before write, iclass 33, count 0 2006.173.23:01:36.57#ibcon#enter sib2, iclass 33, count 0 2006.173.23:01:36.57#ibcon#flushed, iclass 33, count 0 2006.173.23:01:36.57#ibcon#about to write, iclass 33, count 0 2006.173.23:01:36.57#ibcon#wrote, iclass 33, count 0 2006.173.23:01:36.57#ibcon#about to read 3, iclass 33, count 0 2006.173.23:01:36.61#ibcon#read 3, iclass 33, count 0 2006.173.23:01:36.61#ibcon#about to read 4, iclass 33, count 0 2006.173.23:01:36.61#ibcon#read 4, iclass 33, count 0 2006.173.23:01:36.61#ibcon#about to read 5, iclass 33, count 0 2006.173.23:01:36.61#ibcon#read 5, iclass 33, count 0 2006.173.23:01:36.61#ibcon#about to read 6, iclass 33, count 0 2006.173.23:01:36.61#ibcon#read 6, iclass 33, count 0 2006.173.23:01:36.61#ibcon#end of sib2, iclass 33, count 0 2006.173.23:01:36.61#ibcon#*after write, iclass 33, count 0 2006.173.23:01:36.61#ibcon#*before return 0, iclass 33, count 0 2006.173.23:01:36.61#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.23:01:36.61#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.23:01:36.61#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.23:01:36.61#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.23:01:36.61$vck44/va=8,4 2006.173.23:01:36.61#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.23:01:36.61#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.23:01:36.61#ibcon#ireg 11 cls_cnt 2 2006.173.23:01:36.61#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.23:01:36.66#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.23:01:36.67#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.23:01:36.67#ibcon#enter wrdev, iclass 35, count 2 2006.173.23:01:36.67#ibcon#first serial, iclass 35, count 2 2006.173.23:01:36.67#ibcon#enter sib2, iclass 35, count 2 2006.173.23:01:36.67#ibcon#flushed, iclass 35, count 2 2006.173.23:01:36.67#ibcon#about to write, iclass 35, count 2 2006.173.23:01:36.67#ibcon#wrote, iclass 35, count 2 2006.173.23:01:36.67#ibcon#about to read 3, iclass 35, count 2 2006.173.23:01:36.69#ibcon#read 3, iclass 35, count 2 2006.173.23:01:36.69#ibcon#about to read 4, iclass 35, count 2 2006.173.23:01:36.69#ibcon#read 4, iclass 35, count 2 2006.173.23:01:36.69#ibcon#about to read 5, iclass 35, count 2 2006.173.23:01:36.69#ibcon#read 5, iclass 35, count 2 2006.173.23:01:36.69#ibcon#about to read 6, iclass 35, count 2 2006.173.23:01:36.69#ibcon#read 6, iclass 35, count 2 2006.173.23:01:36.69#ibcon#end of sib2, iclass 35, count 2 2006.173.23:01:36.69#ibcon#*mode == 0, iclass 35, count 2 2006.173.23:01:36.69#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.23:01:36.69#ibcon#[25=AT08-04\r\n] 2006.173.23:01:36.69#ibcon#*before write, iclass 35, count 2 2006.173.23:01:36.69#ibcon#enter sib2, iclass 35, count 2 2006.173.23:01:36.69#ibcon#flushed, iclass 35, count 2 2006.173.23:01:36.69#ibcon#about to write, iclass 35, count 2 2006.173.23:01:36.69#ibcon#wrote, iclass 35, count 2 2006.173.23:01:36.69#ibcon#about to read 3, iclass 35, count 2 2006.173.23:01:36.72#ibcon#read 3, iclass 35, count 2 2006.173.23:01:36.72#ibcon#about to read 4, iclass 35, count 2 2006.173.23:01:36.72#ibcon#read 4, iclass 35, count 2 2006.173.23:01:36.72#ibcon#about to read 5, iclass 35, count 2 2006.173.23:01:36.72#ibcon#read 5, iclass 35, count 2 2006.173.23:01:36.72#ibcon#about to read 6, iclass 35, count 2 2006.173.23:01:36.72#ibcon#read 6, iclass 35, count 2 2006.173.23:01:36.72#ibcon#end of sib2, iclass 35, count 2 2006.173.23:01:36.72#ibcon#*after write, iclass 35, count 2 2006.173.23:01:36.72#ibcon#*before return 0, iclass 35, count 2 2006.173.23:01:36.72#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.23:01:36.72#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.23:01:36.72#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.23:01:36.72#ibcon#ireg 7 cls_cnt 0 2006.173.23:01:36.72#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.23:01:36.83#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.23:01:36.84#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.23:01:36.84#ibcon#enter wrdev, iclass 35, count 0 2006.173.23:01:36.84#ibcon#first serial, iclass 35, count 0 2006.173.23:01:36.84#ibcon#enter sib2, iclass 35, count 0 2006.173.23:01:36.84#ibcon#flushed, iclass 35, count 0 2006.173.23:01:36.84#ibcon#about to write, iclass 35, count 0 2006.173.23:01:36.84#ibcon#wrote, iclass 35, count 0 2006.173.23:01:36.84#ibcon#about to read 3, iclass 35, count 0 2006.173.23:01:36.85#ibcon#read 3, iclass 35, count 0 2006.173.23:01:36.86#ibcon#about to read 4, iclass 35, count 0 2006.173.23:01:36.86#ibcon#read 4, iclass 35, count 0 2006.173.23:01:36.86#ibcon#about to read 5, iclass 35, count 0 2006.173.23:01:36.86#ibcon#read 5, iclass 35, count 0 2006.173.23:01:36.86#ibcon#about to read 6, iclass 35, count 0 2006.173.23:01:36.86#ibcon#read 6, iclass 35, count 0 2006.173.23:01:36.86#ibcon#end of sib2, iclass 35, count 0 2006.173.23:01:36.86#ibcon#*mode == 0, iclass 35, count 0 2006.173.23:01:36.86#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.23:01:36.86#ibcon#[25=USB\r\n] 2006.173.23:01:36.86#ibcon#*before write, iclass 35, count 0 2006.173.23:01:36.86#ibcon#enter sib2, iclass 35, count 0 2006.173.23:01:36.86#ibcon#flushed, iclass 35, count 0 2006.173.23:01:36.86#ibcon#about to write, iclass 35, count 0 2006.173.23:01:36.86#ibcon#wrote, iclass 35, count 0 2006.173.23:01:36.86#ibcon#about to read 3, iclass 35, count 0 2006.173.23:01:36.88#ibcon#read 3, iclass 35, count 0 2006.173.23:01:36.89#ibcon#about to read 4, iclass 35, count 0 2006.173.23:01:36.89#ibcon#read 4, iclass 35, count 0 2006.173.23:01:36.89#ibcon#about to read 5, iclass 35, count 0 2006.173.23:01:36.89#ibcon#read 5, iclass 35, count 0 2006.173.23:01:36.89#ibcon#about to read 6, iclass 35, count 0 2006.173.23:01:36.89#ibcon#read 6, iclass 35, count 0 2006.173.23:01:36.89#ibcon#end of sib2, iclass 35, count 0 2006.173.23:01:36.89#ibcon#*after write, iclass 35, count 0 2006.173.23:01:36.89#ibcon#*before return 0, iclass 35, count 0 2006.173.23:01:36.89#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.23:01:36.89#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.23:01:36.89#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.23:01:36.89#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.23:01:36.89$vck44/vblo=1,629.99 2006.173.23:01:36.89#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.23:01:36.89#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.23:01:36.89#ibcon#ireg 17 cls_cnt 0 2006.173.23:01:36.89#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.23:01:36.89#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.23:01:36.89#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.23:01:36.89#ibcon#enter wrdev, iclass 37, count 0 2006.173.23:01:36.89#ibcon#first serial, iclass 37, count 0 2006.173.23:01:36.89#ibcon#enter sib2, iclass 37, count 0 2006.173.23:01:36.89#ibcon#flushed, iclass 37, count 0 2006.173.23:01:36.89#ibcon#about to write, iclass 37, count 0 2006.173.23:01:36.89#ibcon#wrote, iclass 37, count 0 2006.173.23:01:36.89#ibcon#about to read 3, iclass 37, count 0 2006.173.23:01:36.90#ibcon#read 3, iclass 37, count 0 2006.173.23:01:36.91#ibcon#about to read 4, iclass 37, count 0 2006.173.23:01:36.91#ibcon#read 4, iclass 37, count 0 2006.173.23:01:36.91#ibcon#about to read 5, iclass 37, count 0 2006.173.23:01:36.91#ibcon#read 5, iclass 37, count 0 2006.173.23:01:36.91#ibcon#about to read 6, iclass 37, count 0 2006.173.23:01:36.91#ibcon#read 6, iclass 37, count 0 2006.173.23:01:36.91#ibcon#end of sib2, iclass 37, count 0 2006.173.23:01:36.91#ibcon#*mode == 0, iclass 37, count 0 2006.173.23:01:36.91#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.23:01:36.91#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.23:01:36.91#ibcon#*before write, iclass 37, count 0 2006.173.23:01:36.91#ibcon#enter sib2, iclass 37, count 0 2006.173.23:01:36.91#ibcon#flushed, iclass 37, count 0 2006.173.23:01:36.91#ibcon#about to write, iclass 37, count 0 2006.173.23:01:36.91#ibcon#wrote, iclass 37, count 0 2006.173.23:01:36.91#ibcon#about to read 3, iclass 37, count 0 2006.173.23:01:36.95#ibcon#read 3, iclass 37, count 0 2006.173.23:01:36.95#ibcon#about to read 4, iclass 37, count 0 2006.173.23:01:36.95#ibcon#read 4, iclass 37, count 0 2006.173.23:01:36.95#ibcon#about to read 5, iclass 37, count 0 2006.173.23:01:36.95#ibcon#read 5, iclass 37, count 0 2006.173.23:01:36.95#ibcon#about to read 6, iclass 37, count 0 2006.173.23:01:36.95#ibcon#read 6, iclass 37, count 0 2006.173.23:01:36.95#ibcon#end of sib2, iclass 37, count 0 2006.173.23:01:36.95#ibcon#*after write, iclass 37, count 0 2006.173.23:01:36.95#ibcon#*before return 0, iclass 37, count 0 2006.173.23:01:36.95#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.23:01:36.95#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.23:01:36.95#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.23:01:36.95#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.23:01:36.95$vck44/vb=1,4 2006.173.23:01:36.95#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.23:01:36.95#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.23:01:36.95#ibcon#ireg 11 cls_cnt 2 2006.173.23:01:36.95#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.23:01:36.95#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.23:01:36.95#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.23:01:36.95#ibcon#enter wrdev, iclass 39, count 2 2006.173.23:01:36.95#ibcon#first serial, iclass 39, count 2 2006.173.23:01:36.95#ibcon#enter sib2, iclass 39, count 2 2006.173.23:01:36.95#ibcon#flushed, iclass 39, count 2 2006.173.23:01:36.95#ibcon#about to write, iclass 39, count 2 2006.173.23:01:36.95#ibcon#wrote, iclass 39, count 2 2006.173.23:01:36.95#ibcon#about to read 3, iclass 39, count 2 2006.173.23:01:36.96#ibcon#read 3, iclass 39, count 2 2006.173.23:01:36.97#ibcon#about to read 4, iclass 39, count 2 2006.173.23:01:36.97#ibcon#read 4, iclass 39, count 2 2006.173.23:01:36.97#ibcon#about to read 5, iclass 39, count 2 2006.173.23:01:36.97#ibcon#read 5, iclass 39, count 2 2006.173.23:01:36.97#ibcon#about to read 6, iclass 39, count 2 2006.173.23:01:36.97#ibcon#read 6, iclass 39, count 2 2006.173.23:01:36.97#ibcon#end of sib2, iclass 39, count 2 2006.173.23:01:36.97#ibcon#*mode == 0, iclass 39, count 2 2006.173.23:01:36.97#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.23:01:36.97#ibcon#[27=AT01-04\r\n] 2006.173.23:01:36.97#ibcon#*before write, iclass 39, count 2 2006.173.23:01:36.97#ibcon#enter sib2, iclass 39, count 2 2006.173.23:01:36.97#ibcon#flushed, iclass 39, count 2 2006.173.23:01:36.97#ibcon#about to write, iclass 39, count 2 2006.173.23:01:36.97#ibcon#wrote, iclass 39, count 2 2006.173.23:01:36.97#ibcon#about to read 3, iclass 39, count 2 2006.173.23:01:37.00#ibcon#read 3, iclass 39, count 2 2006.173.23:01:37.00#ibcon#about to read 4, iclass 39, count 2 2006.173.23:01:37.00#ibcon#read 4, iclass 39, count 2 2006.173.23:01:37.00#ibcon#about to read 5, iclass 39, count 2 2006.173.23:01:37.00#ibcon#read 5, iclass 39, count 2 2006.173.23:01:37.00#ibcon#about to read 6, iclass 39, count 2 2006.173.23:01:37.00#ibcon#read 6, iclass 39, count 2 2006.173.23:01:37.00#ibcon#end of sib2, iclass 39, count 2 2006.173.23:01:37.00#ibcon#*after write, iclass 39, count 2 2006.173.23:01:37.00#ibcon#*before return 0, iclass 39, count 2 2006.173.23:01:37.00#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.23:01:37.00#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.23:01:37.00#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.23:01:37.00#ibcon#ireg 7 cls_cnt 0 2006.173.23:01:37.00#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.23:01:37.11#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.23:01:37.12#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.23:01:37.12#ibcon#enter wrdev, iclass 39, count 0 2006.173.23:01:37.12#ibcon#first serial, iclass 39, count 0 2006.173.23:01:37.12#ibcon#enter sib2, iclass 39, count 0 2006.173.23:01:37.12#ibcon#flushed, iclass 39, count 0 2006.173.23:01:37.12#ibcon#about to write, iclass 39, count 0 2006.173.23:01:37.12#ibcon#wrote, iclass 39, count 0 2006.173.23:01:37.12#ibcon#about to read 3, iclass 39, count 0 2006.173.23:01:37.13#ibcon#read 3, iclass 39, count 0 2006.173.23:01:37.14#ibcon#about to read 4, iclass 39, count 0 2006.173.23:01:37.14#ibcon#read 4, iclass 39, count 0 2006.173.23:01:37.14#ibcon#about to read 5, iclass 39, count 0 2006.173.23:01:37.14#ibcon#read 5, iclass 39, count 0 2006.173.23:01:37.14#ibcon#about to read 6, iclass 39, count 0 2006.173.23:01:37.14#ibcon#read 6, iclass 39, count 0 2006.173.23:01:37.14#ibcon#end of sib2, iclass 39, count 0 2006.173.23:01:37.14#ibcon#*mode == 0, iclass 39, count 0 2006.173.23:01:37.14#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.23:01:37.14#ibcon#[27=USB\r\n] 2006.173.23:01:37.14#ibcon#*before write, iclass 39, count 0 2006.173.23:01:37.14#ibcon#enter sib2, iclass 39, count 0 2006.173.23:01:37.14#ibcon#flushed, iclass 39, count 0 2006.173.23:01:37.14#ibcon#about to write, iclass 39, count 0 2006.173.23:01:37.14#ibcon#wrote, iclass 39, count 0 2006.173.23:01:37.14#ibcon#about to read 3, iclass 39, count 0 2006.173.23:01:37.17#ibcon#read 3, iclass 39, count 0 2006.173.23:01:37.17#ibcon#about to read 4, iclass 39, count 0 2006.173.23:01:37.17#ibcon#read 4, iclass 39, count 0 2006.173.23:01:37.17#ibcon#about to read 5, iclass 39, count 0 2006.173.23:01:37.17#ibcon#read 5, iclass 39, count 0 2006.173.23:01:37.17#ibcon#about to read 6, iclass 39, count 0 2006.173.23:01:37.17#ibcon#read 6, iclass 39, count 0 2006.173.23:01:37.17#ibcon#end of sib2, iclass 39, count 0 2006.173.23:01:37.17#ibcon#*after write, iclass 39, count 0 2006.173.23:01:37.17#ibcon#*before return 0, iclass 39, count 0 2006.173.23:01:37.17#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.23:01:37.17#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.23:01:37.17#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.23:01:37.17#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.23:01:37.17$vck44/vblo=2,634.99 2006.173.23:01:37.17#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.23:01:37.17#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.23:01:37.17#ibcon#ireg 17 cls_cnt 0 2006.173.23:01:37.17#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.23:01:37.17#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.23:01:37.17#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.23:01:37.17#ibcon#enter wrdev, iclass 3, count 0 2006.173.23:01:37.17#ibcon#first serial, iclass 3, count 0 2006.173.23:01:37.17#ibcon#enter sib2, iclass 3, count 0 2006.173.23:01:37.17#ibcon#flushed, iclass 3, count 0 2006.173.23:01:37.17#ibcon#about to write, iclass 3, count 0 2006.173.23:01:37.17#ibcon#wrote, iclass 3, count 0 2006.173.23:01:37.17#ibcon#about to read 3, iclass 3, count 0 2006.173.23:01:37.18#ibcon#read 3, iclass 3, count 0 2006.173.23:01:37.19#ibcon#about to read 4, iclass 3, count 0 2006.173.23:01:37.19#ibcon#read 4, iclass 3, count 0 2006.173.23:01:37.19#ibcon#about to read 5, iclass 3, count 0 2006.173.23:01:37.19#ibcon#read 5, iclass 3, count 0 2006.173.23:01:37.19#ibcon#about to read 6, iclass 3, count 0 2006.173.23:01:37.19#ibcon#read 6, iclass 3, count 0 2006.173.23:01:37.19#ibcon#end of sib2, iclass 3, count 0 2006.173.23:01:37.19#ibcon#*mode == 0, iclass 3, count 0 2006.173.23:01:37.19#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.23:01:37.19#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.23:01:37.19#ibcon#*before write, iclass 3, count 0 2006.173.23:01:37.19#ibcon#enter sib2, iclass 3, count 0 2006.173.23:01:37.19#ibcon#flushed, iclass 3, count 0 2006.173.23:01:37.19#ibcon#about to write, iclass 3, count 0 2006.173.23:01:37.19#ibcon#wrote, iclass 3, count 0 2006.173.23:01:37.19#ibcon#about to read 3, iclass 3, count 0 2006.173.23:01:37.22#ibcon#read 3, iclass 3, count 0 2006.173.23:01:37.23#ibcon#about to read 4, iclass 3, count 0 2006.173.23:01:37.23#ibcon#read 4, iclass 3, count 0 2006.173.23:01:37.23#ibcon#about to read 5, iclass 3, count 0 2006.173.23:01:37.23#ibcon#read 5, iclass 3, count 0 2006.173.23:01:37.23#ibcon#about to read 6, iclass 3, count 0 2006.173.23:01:37.23#ibcon#read 6, iclass 3, count 0 2006.173.23:01:37.23#ibcon#end of sib2, iclass 3, count 0 2006.173.23:01:37.23#ibcon#*after write, iclass 3, count 0 2006.173.23:01:37.23#ibcon#*before return 0, iclass 3, count 0 2006.173.23:01:37.23#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.23:01:37.23#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.23:01:37.23#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.23:01:37.23#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.23:01:37.23$vck44/vb=2,4 2006.173.23:01:37.23#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.23:01:37.23#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.23:01:37.23#ibcon#ireg 11 cls_cnt 2 2006.173.23:01:37.23#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.23:01:37.28#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.23:01:37.29#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.23:01:37.29#ibcon#enter wrdev, iclass 5, count 2 2006.173.23:01:37.29#ibcon#first serial, iclass 5, count 2 2006.173.23:01:37.29#ibcon#enter sib2, iclass 5, count 2 2006.173.23:01:37.29#ibcon#flushed, iclass 5, count 2 2006.173.23:01:37.29#ibcon#about to write, iclass 5, count 2 2006.173.23:01:37.29#ibcon#wrote, iclass 5, count 2 2006.173.23:01:37.29#ibcon#about to read 3, iclass 5, count 2 2006.173.23:01:37.30#ibcon#read 3, iclass 5, count 2 2006.173.23:01:37.31#ibcon#about to read 4, iclass 5, count 2 2006.173.23:01:37.31#ibcon#read 4, iclass 5, count 2 2006.173.23:01:37.31#ibcon#about to read 5, iclass 5, count 2 2006.173.23:01:37.31#ibcon#read 5, iclass 5, count 2 2006.173.23:01:37.31#ibcon#about to read 6, iclass 5, count 2 2006.173.23:01:37.31#ibcon#read 6, iclass 5, count 2 2006.173.23:01:37.31#ibcon#end of sib2, iclass 5, count 2 2006.173.23:01:37.31#ibcon#*mode == 0, iclass 5, count 2 2006.173.23:01:37.31#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.23:01:37.31#ibcon#[27=AT02-04\r\n] 2006.173.23:01:37.31#ibcon#*before write, iclass 5, count 2 2006.173.23:01:37.31#ibcon#enter sib2, iclass 5, count 2 2006.173.23:01:37.31#ibcon#flushed, iclass 5, count 2 2006.173.23:01:37.31#ibcon#about to write, iclass 5, count 2 2006.173.23:01:37.31#ibcon#wrote, iclass 5, count 2 2006.173.23:01:37.31#ibcon#about to read 3, iclass 5, count 2 2006.173.23:01:37.34#ibcon#read 3, iclass 5, count 2 2006.173.23:01:37.34#ibcon#about to read 4, iclass 5, count 2 2006.173.23:01:37.34#ibcon#read 4, iclass 5, count 2 2006.173.23:01:37.34#ibcon#about to read 5, iclass 5, count 2 2006.173.23:01:37.34#ibcon#read 5, iclass 5, count 2 2006.173.23:01:37.34#ibcon#about to read 6, iclass 5, count 2 2006.173.23:01:37.34#ibcon#read 6, iclass 5, count 2 2006.173.23:01:37.34#ibcon#end of sib2, iclass 5, count 2 2006.173.23:01:37.34#ibcon#*after write, iclass 5, count 2 2006.173.23:01:37.34#ibcon#*before return 0, iclass 5, count 2 2006.173.23:01:37.34#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.23:01:37.34#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.23:01:37.34#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.23:01:37.34#ibcon#ireg 7 cls_cnt 0 2006.173.23:01:37.34#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.23:01:37.45#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.23:01:37.46#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.23:01:37.46#ibcon#enter wrdev, iclass 5, count 0 2006.173.23:01:37.46#ibcon#first serial, iclass 5, count 0 2006.173.23:01:37.46#ibcon#enter sib2, iclass 5, count 0 2006.173.23:01:37.46#ibcon#flushed, iclass 5, count 0 2006.173.23:01:37.46#ibcon#about to write, iclass 5, count 0 2006.173.23:01:37.46#ibcon#wrote, iclass 5, count 0 2006.173.23:01:37.46#ibcon#about to read 3, iclass 5, count 0 2006.173.23:01:37.47#ibcon#read 3, iclass 5, count 0 2006.173.23:01:37.48#ibcon#about to read 4, iclass 5, count 0 2006.173.23:01:37.48#ibcon#read 4, iclass 5, count 0 2006.173.23:01:37.48#ibcon#about to read 5, iclass 5, count 0 2006.173.23:01:37.48#ibcon#read 5, iclass 5, count 0 2006.173.23:01:37.48#ibcon#about to read 6, iclass 5, count 0 2006.173.23:01:37.48#ibcon#read 6, iclass 5, count 0 2006.173.23:01:37.48#ibcon#end of sib2, iclass 5, count 0 2006.173.23:01:37.48#ibcon#*mode == 0, iclass 5, count 0 2006.173.23:01:37.48#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.23:01:37.48#ibcon#[27=USB\r\n] 2006.173.23:01:37.48#ibcon#*before write, iclass 5, count 0 2006.173.23:01:37.48#ibcon#enter sib2, iclass 5, count 0 2006.173.23:01:37.48#ibcon#flushed, iclass 5, count 0 2006.173.23:01:37.48#ibcon#about to write, iclass 5, count 0 2006.173.23:01:37.48#ibcon#wrote, iclass 5, count 0 2006.173.23:01:37.48#ibcon#about to read 3, iclass 5, count 0 2006.173.23:01:37.51#ibcon#read 3, iclass 5, count 0 2006.173.23:01:37.51#ibcon#about to read 4, iclass 5, count 0 2006.173.23:01:37.51#ibcon#read 4, iclass 5, count 0 2006.173.23:01:37.51#ibcon#about to read 5, iclass 5, count 0 2006.173.23:01:37.51#ibcon#read 5, iclass 5, count 0 2006.173.23:01:37.51#ibcon#about to read 6, iclass 5, count 0 2006.173.23:01:37.51#ibcon#read 6, iclass 5, count 0 2006.173.23:01:37.51#ibcon#end of sib2, iclass 5, count 0 2006.173.23:01:37.51#ibcon#*after write, iclass 5, count 0 2006.173.23:01:37.51#ibcon#*before return 0, iclass 5, count 0 2006.173.23:01:37.51#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.23:01:37.51#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.23:01:37.51#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.23:01:37.51#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.23:01:37.51$vck44/vblo=3,649.99 2006.173.23:01:37.51#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.23:01:37.51#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.23:01:37.51#ibcon#ireg 17 cls_cnt 0 2006.173.23:01:37.51#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.23:01:37.51#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.23:01:37.51#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.23:01:37.51#ibcon#enter wrdev, iclass 7, count 0 2006.173.23:01:37.51#ibcon#first serial, iclass 7, count 0 2006.173.23:01:37.51#ibcon#enter sib2, iclass 7, count 0 2006.173.23:01:37.51#ibcon#flushed, iclass 7, count 0 2006.173.23:01:37.51#ibcon#about to write, iclass 7, count 0 2006.173.23:01:37.51#ibcon#wrote, iclass 7, count 0 2006.173.23:01:37.51#ibcon#about to read 3, iclass 7, count 0 2006.173.23:01:37.52#ibcon#read 3, iclass 7, count 0 2006.173.23:01:37.52#ibcon#about to read 4, iclass 7, count 0 2006.173.23:01:37.53#ibcon#read 4, iclass 7, count 0 2006.173.23:01:37.53#ibcon#about to read 5, iclass 7, count 0 2006.173.23:01:37.53#ibcon#read 5, iclass 7, count 0 2006.173.23:01:37.53#ibcon#about to read 6, iclass 7, count 0 2006.173.23:01:37.53#ibcon#read 6, iclass 7, count 0 2006.173.23:01:37.53#ibcon#end of sib2, iclass 7, count 0 2006.173.23:01:37.53#ibcon#*mode == 0, iclass 7, count 0 2006.173.23:01:37.53#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.23:01:37.53#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.23:01:37.53#ibcon#*before write, iclass 7, count 0 2006.173.23:01:37.53#ibcon#enter sib2, iclass 7, count 0 2006.173.23:01:37.53#ibcon#flushed, iclass 7, count 0 2006.173.23:01:37.53#ibcon#about to write, iclass 7, count 0 2006.173.23:01:37.53#ibcon#wrote, iclass 7, count 0 2006.173.23:01:37.53#ibcon#about to read 3, iclass 7, count 0 2006.173.23:01:37.57#ibcon#read 3, iclass 7, count 0 2006.173.23:01:37.57#ibcon#about to read 4, iclass 7, count 0 2006.173.23:01:37.57#ibcon#read 4, iclass 7, count 0 2006.173.23:01:37.57#ibcon#about to read 5, iclass 7, count 0 2006.173.23:01:37.57#ibcon#read 5, iclass 7, count 0 2006.173.23:01:37.57#ibcon#about to read 6, iclass 7, count 0 2006.173.23:01:37.57#ibcon#read 6, iclass 7, count 0 2006.173.23:01:37.57#ibcon#end of sib2, iclass 7, count 0 2006.173.23:01:37.57#ibcon#*after write, iclass 7, count 0 2006.173.23:01:37.57#ibcon#*before return 0, iclass 7, count 0 2006.173.23:01:37.57#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.23:01:37.57#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.23:01:37.57#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.23:01:37.57#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.23:01:37.57$vck44/vb=3,4 2006.173.23:01:37.57#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.23:01:37.57#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.23:01:37.57#ibcon#ireg 11 cls_cnt 2 2006.173.23:01:37.57#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.23:01:37.63#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.23:01:37.63#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.23:01:37.63#ibcon#enter wrdev, iclass 11, count 2 2006.173.23:01:37.63#ibcon#first serial, iclass 11, count 2 2006.173.23:01:37.63#ibcon#enter sib2, iclass 11, count 2 2006.173.23:01:37.63#ibcon#flushed, iclass 11, count 2 2006.173.23:01:37.63#ibcon#about to write, iclass 11, count 2 2006.173.23:01:37.63#ibcon#wrote, iclass 11, count 2 2006.173.23:01:37.63#ibcon#about to read 3, iclass 11, count 2 2006.173.23:01:37.65#ibcon#read 3, iclass 11, count 2 2006.173.23:01:37.65#ibcon#about to read 4, iclass 11, count 2 2006.173.23:01:37.65#ibcon#read 4, iclass 11, count 2 2006.173.23:01:37.65#ibcon#about to read 5, iclass 11, count 2 2006.173.23:01:37.65#ibcon#read 5, iclass 11, count 2 2006.173.23:01:37.65#ibcon#about to read 6, iclass 11, count 2 2006.173.23:01:37.65#ibcon#read 6, iclass 11, count 2 2006.173.23:01:37.65#ibcon#end of sib2, iclass 11, count 2 2006.173.23:01:37.65#ibcon#*mode == 0, iclass 11, count 2 2006.173.23:01:37.65#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.23:01:37.65#ibcon#[27=AT03-04\r\n] 2006.173.23:01:37.65#ibcon#*before write, iclass 11, count 2 2006.173.23:01:37.65#ibcon#enter sib2, iclass 11, count 2 2006.173.23:01:37.65#ibcon#flushed, iclass 11, count 2 2006.173.23:01:37.65#ibcon#about to write, iclass 11, count 2 2006.173.23:01:37.65#ibcon#wrote, iclass 11, count 2 2006.173.23:01:37.65#ibcon#about to read 3, iclass 11, count 2 2006.173.23:01:37.68#ibcon#read 3, iclass 11, count 2 2006.173.23:01:37.68#ibcon#about to read 4, iclass 11, count 2 2006.173.23:01:37.68#ibcon#read 4, iclass 11, count 2 2006.173.23:01:37.68#ibcon#about to read 5, iclass 11, count 2 2006.173.23:01:37.68#ibcon#read 5, iclass 11, count 2 2006.173.23:01:37.68#ibcon#about to read 6, iclass 11, count 2 2006.173.23:01:37.68#ibcon#read 6, iclass 11, count 2 2006.173.23:01:37.68#ibcon#end of sib2, iclass 11, count 2 2006.173.23:01:37.68#ibcon#*after write, iclass 11, count 2 2006.173.23:01:37.68#ibcon#*before return 0, iclass 11, count 2 2006.173.23:01:37.68#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.23:01:37.68#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.23:01:37.68#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.23:01:37.68#ibcon#ireg 7 cls_cnt 0 2006.173.23:01:37.68#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.23:01:37.79#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.23:01:37.80#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.23:01:37.80#ibcon#enter wrdev, iclass 11, count 0 2006.173.23:01:37.80#ibcon#first serial, iclass 11, count 0 2006.173.23:01:37.80#ibcon#enter sib2, iclass 11, count 0 2006.173.23:01:37.80#ibcon#flushed, iclass 11, count 0 2006.173.23:01:37.80#ibcon#about to write, iclass 11, count 0 2006.173.23:01:37.80#ibcon#wrote, iclass 11, count 0 2006.173.23:01:37.80#ibcon#about to read 3, iclass 11, count 0 2006.173.23:01:37.82#ibcon#read 3, iclass 11, count 0 2006.173.23:01:37.82#ibcon#about to read 4, iclass 11, count 0 2006.173.23:01:37.82#ibcon#read 4, iclass 11, count 0 2006.173.23:01:37.82#ibcon#about to read 5, iclass 11, count 0 2006.173.23:01:37.82#ibcon#read 5, iclass 11, count 0 2006.173.23:01:37.82#ibcon#about to read 6, iclass 11, count 0 2006.173.23:01:37.82#ibcon#read 6, iclass 11, count 0 2006.173.23:01:37.82#ibcon#end of sib2, iclass 11, count 0 2006.173.23:01:37.82#ibcon#*mode == 0, iclass 11, count 0 2006.173.23:01:37.82#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.23:01:37.82#ibcon#[27=USB\r\n] 2006.173.23:01:37.82#ibcon#*before write, iclass 11, count 0 2006.173.23:01:37.82#ibcon#enter sib2, iclass 11, count 0 2006.173.23:01:37.82#ibcon#flushed, iclass 11, count 0 2006.173.23:01:37.82#ibcon#about to write, iclass 11, count 0 2006.173.23:01:37.82#ibcon#wrote, iclass 11, count 0 2006.173.23:01:37.82#ibcon#about to read 3, iclass 11, count 0 2006.173.23:01:37.84#ibcon#read 3, iclass 11, count 0 2006.173.23:01:37.85#ibcon#about to read 4, iclass 11, count 0 2006.173.23:01:37.85#ibcon#read 4, iclass 11, count 0 2006.173.23:01:37.85#ibcon#about to read 5, iclass 11, count 0 2006.173.23:01:37.85#ibcon#read 5, iclass 11, count 0 2006.173.23:01:37.85#ibcon#about to read 6, iclass 11, count 0 2006.173.23:01:37.85#ibcon#read 6, iclass 11, count 0 2006.173.23:01:37.85#ibcon#end of sib2, iclass 11, count 0 2006.173.23:01:37.85#ibcon#*after write, iclass 11, count 0 2006.173.23:01:37.85#ibcon#*before return 0, iclass 11, count 0 2006.173.23:01:37.85#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.23:01:37.85#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.23:01:37.85#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.23:01:37.85#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.23:01:37.85$vck44/vblo=4,679.99 2006.173.23:01:37.85#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.23:01:37.85#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.23:01:37.85#ibcon#ireg 17 cls_cnt 0 2006.173.23:01:37.85#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.23:01:37.85#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.23:01:37.85#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.23:01:37.85#ibcon#enter wrdev, iclass 13, count 0 2006.173.23:01:37.85#ibcon#first serial, iclass 13, count 0 2006.173.23:01:37.85#ibcon#enter sib2, iclass 13, count 0 2006.173.23:01:37.85#ibcon#flushed, iclass 13, count 0 2006.173.23:01:37.85#ibcon#about to write, iclass 13, count 0 2006.173.23:01:37.85#ibcon#wrote, iclass 13, count 0 2006.173.23:01:37.85#ibcon#about to read 3, iclass 13, count 0 2006.173.23:01:37.87#ibcon#read 3, iclass 13, count 0 2006.173.23:01:37.87#ibcon#about to read 4, iclass 13, count 0 2006.173.23:01:37.87#ibcon#read 4, iclass 13, count 0 2006.173.23:01:37.87#ibcon#about to read 5, iclass 13, count 0 2006.173.23:01:37.87#ibcon#read 5, iclass 13, count 0 2006.173.23:01:37.87#ibcon#about to read 6, iclass 13, count 0 2006.173.23:01:37.87#ibcon#read 6, iclass 13, count 0 2006.173.23:01:37.87#ibcon#end of sib2, iclass 13, count 0 2006.173.23:01:37.87#ibcon#*mode == 0, iclass 13, count 0 2006.173.23:01:37.87#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.23:01:37.87#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.23:01:37.87#ibcon#*before write, iclass 13, count 0 2006.173.23:01:37.87#ibcon#enter sib2, iclass 13, count 0 2006.173.23:01:37.87#ibcon#flushed, iclass 13, count 0 2006.173.23:01:37.87#ibcon#about to write, iclass 13, count 0 2006.173.23:01:37.87#ibcon#wrote, iclass 13, count 0 2006.173.23:01:37.87#ibcon#about to read 3, iclass 13, count 0 2006.173.23:01:37.90#ibcon#read 3, iclass 13, count 0 2006.173.23:01:37.91#ibcon#about to read 4, iclass 13, count 0 2006.173.23:01:37.91#ibcon#read 4, iclass 13, count 0 2006.173.23:01:37.91#ibcon#about to read 5, iclass 13, count 0 2006.173.23:01:37.91#ibcon#read 5, iclass 13, count 0 2006.173.23:01:37.91#ibcon#about to read 6, iclass 13, count 0 2006.173.23:01:37.91#ibcon#read 6, iclass 13, count 0 2006.173.23:01:37.91#ibcon#end of sib2, iclass 13, count 0 2006.173.23:01:37.91#ibcon#*after write, iclass 13, count 0 2006.173.23:01:37.91#ibcon#*before return 0, iclass 13, count 0 2006.173.23:01:37.91#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.23:01:37.91#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.23:01:37.91#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.23:01:37.91#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.23:01:37.91$vck44/vb=4,4 2006.173.23:01:37.91#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.23:01:37.91#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.23:01:37.91#ibcon#ireg 11 cls_cnt 2 2006.173.23:01:37.91#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.23:01:37.96#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.23:01:37.97#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.23:01:37.97#ibcon#enter wrdev, iclass 15, count 2 2006.173.23:01:37.97#ibcon#first serial, iclass 15, count 2 2006.173.23:01:37.97#ibcon#enter sib2, iclass 15, count 2 2006.173.23:01:37.97#ibcon#flushed, iclass 15, count 2 2006.173.23:01:37.97#ibcon#about to write, iclass 15, count 2 2006.173.23:01:37.97#ibcon#wrote, iclass 15, count 2 2006.173.23:01:37.97#ibcon#about to read 3, iclass 15, count 2 2006.173.23:01:37.98#ibcon#read 3, iclass 15, count 2 2006.173.23:01:37.99#ibcon#about to read 4, iclass 15, count 2 2006.173.23:01:37.99#ibcon#read 4, iclass 15, count 2 2006.173.23:01:37.99#ibcon#about to read 5, iclass 15, count 2 2006.173.23:01:37.99#ibcon#read 5, iclass 15, count 2 2006.173.23:01:37.99#ibcon#about to read 6, iclass 15, count 2 2006.173.23:01:37.99#ibcon#read 6, iclass 15, count 2 2006.173.23:01:37.99#ibcon#end of sib2, iclass 15, count 2 2006.173.23:01:37.99#ibcon#*mode == 0, iclass 15, count 2 2006.173.23:01:37.99#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.23:01:37.99#ibcon#[27=AT04-04\r\n] 2006.173.23:01:37.99#ibcon#*before write, iclass 15, count 2 2006.173.23:01:37.99#ibcon#enter sib2, iclass 15, count 2 2006.173.23:01:37.99#ibcon#flushed, iclass 15, count 2 2006.173.23:01:37.99#ibcon#about to write, iclass 15, count 2 2006.173.23:01:37.99#ibcon#wrote, iclass 15, count 2 2006.173.23:01:37.99#ibcon#about to read 3, iclass 15, count 2 2006.173.23:01:38.02#ibcon#read 3, iclass 15, count 2 2006.173.23:01:38.02#ibcon#about to read 4, iclass 15, count 2 2006.173.23:01:38.02#ibcon#read 4, iclass 15, count 2 2006.173.23:01:38.02#ibcon#about to read 5, iclass 15, count 2 2006.173.23:01:38.02#ibcon#read 5, iclass 15, count 2 2006.173.23:01:38.02#ibcon#about to read 6, iclass 15, count 2 2006.173.23:01:38.02#ibcon#read 6, iclass 15, count 2 2006.173.23:01:38.02#ibcon#end of sib2, iclass 15, count 2 2006.173.23:01:38.02#ibcon#*after write, iclass 15, count 2 2006.173.23:01:38.02#ibcon#*before return 0, iclass 15, count 2 2006.173.23:01:38.02#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.23:01:38.02#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.23:01:38.02#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.23:01:38.02#ibcon#ireg 7 cls_cnt 0 2006.173.23:01:38.02#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.23:01:38.14#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.23:01:38.14#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.23:01:38.14#ibcon#enter wrdev, iclass 15, count 0 2006.173.23:01:38.14#ibcon#first serial, iclass 15, count 0 2006.173.23:01:38.14#ibcon#enter sib2, iclass 15, count 0 2006.173.23:01:38.14#ibcon#flushed, iclass 15, count 0 2006.173.23:01:38.14#ibcon#about to write, iclass 15, count 0 2006.173.23:01:38.14#ibcon#wrote, iclass 15, count 0 2006.173.23:01:38.14#ibcon#about to read 3, iclass 15, count 0 2006.173.23:01:38.15#ibcon#read 3, iclass 15, count 0 2006.173.23:01:38.16#ibcon#about to read 4, iclass 15, count 0 2006.173.23:01:38.16#ibcon#read 4, iclass 15, count 0 2006.173.23:01:38.16#ibcon#about to read 5, iclass 15, count 0 2006.173.23:01:38.16#ibcon#read 5, iclass 15, count 0 2006.173.23:01:38.16#ibcon#about to read 6, iclass 15, count 0 2006.173.23:01:38.16#ibcon#read 6, iclass 15, count 0 2006.173.23:01:38.16#ibcon#end of sib2, iclass 15, count 0 2006.173.23:01:38.16#ibcon#*mode == 0, iclass 15, count 0 2006.173.23:01:38.16#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.23:01:38.16#ibcon#[27=USB\r\n] 2006.173.23:01:38.16#ibcon#*before write, iclass 15, count 0 2006.173.23:01:38.16#ibcon#enter sib2, iclass 15, count 0 2006.173.23:01:38.16#ibcon#flushed, iclass 15, count 0 2006.173.23:01:38.16#ibcon#about to write, iclass 15, count 0 2006.173.23:01:38.16#ibcon#wrote, iclass 15, count 0 2006.173.23:01:38.16#ibcon#about to read 3, iclass 15, count 0 2006.173.23:01:38.19#ibcon#read 3, iclass 15, count 0 2006.173.23:01:38.19#ibcon#about to read 4, iclass 15, count 0 2006.173.23:01:38.19#ibcon#read 4, iclass 15, count 0 2006.173.23:01:38.19#ibcon#about to read 5, iclass 15, count 0 2006.173.23:01:38.19#ibcon#read 5, iclass 15, count 0 2006.173.23:01:38.19#ibcon#about to read 6, iclass 15, count 0 2006.173.23:01:38.19#ibcon#read 6, iclass 15, count 0 2006.173.23:01:38.19#ibcon#end of sib2, iclass 15, count 0 2006.173.23:01:38.19#ibcon#*after write, iclass 15, count 0 2006.173.23:01:38.19#ibcon#*before return 0, iclass 15, count 0 2006.173.23:01:38.19#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.23:01:38.19#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.23:01:38.19#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.23:01:38.19#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.23:01:38.19$vck44/vblo=5,709.99 2006.173.23:01:38.19#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.23:01:38.19#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.23:01:38.19#ibcon#ireg 17 cls_cnt 0 2006.173.23:01:38.19#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.23:01:38.19#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.23:01:38.19#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.23:01:38.19#ibcon#enter wrdev, iclass 17, count 0 2006.173.23:01:38.19#ibcon#first serial, iclass 17, count 0 2006.173.23:01:38.19#ibcon#enter sib2, iclass 17, count 0 2006.173.23:01:38.19#ibcon#flushed, iclass 17, count 0 2006.173.23:01:38.19#ibcon#about to write, iclass 17, count 0 2006.173.23:01:38.19#ibcon#wrote, iclass 17, count 0 2006.173.23:01:38.19#ibcon#about to read 3, iclass 17, count 0 2006.173.23:01:38.21#ibcon#read 3, iclass 17, count 0 2006.173.23:01:38.21#ibcon#about to read 4, iclass 17, count 0 2006.173.23:01:38.21#ibcon#read 4, iclass 17, count 0 2006.173.23:01:38.21#ibcon#about to read 5, iclass 17, count 0 2006.173.23:01:38.21#ibcon#read 5, iclass 17, count 0 2006.173.23:01:38.21#ibcon#about to read 6, iclass 17, count 0 2006.173.23:01:38.21#ibcon#read 6, iclass 17, count 0 2006.173.23:01:38.21#ibcon#end of sib2, iclass 17, count 0 2006.173.23:01:38.21#ibcon#*mode == 0, iclass 17, count 0 2006.173.23:01:38.21#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.23:01:38.21#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.23:01:38.21#ibcon#*before write, iclass 17, count 0 2006.173.23:01:38.21#ibcon#enter sib2, iclass 17, count 0 2006.173.23:01:38.21#ibcon#flushed, iclass 17, count 0 2006.173.23:01:38.21#ibcon#about to write, iclass 17, count 0 2006.173.23:01:38.21#ibcon#wrote, iclass 17, count 0 2006.173.23:01:38.21#ibcon#about to read 3, iclass 17, count 0 2006.173.23:01:38.24#ibcon#read 3, iclass 17, count 0 2006.173.23:01:38.25#ibcon#about to read 4, iclass 17, count 0 2006.173.23:01:38.25#ibcon#read 4, iclass 17, count 0 2006.173.23:01:38.25#ibcon#about to read 5, iclass 17, count 0 2006.173.23:01:38.25#ibcon#read 5, iclass 17, count 0 2006.173.23:01:38.25#ibcon#about to read 6, iclass 17, count 0 2006.173.23:01:38.25#ibcon#read 6, iclass 17, count 0 2006.173.23:01:38.25#ibcon#end of sib2, iclass 17, count 0 2006.173.23:01:38.25#ibcon#*after write, iclass 17, count 0 2006.173.23:01:38.25#ibcon#*before return 0, iclass 17, count 0 2006.173.23:01:38.25#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.23:01:38.25#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.23:01:38.25#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.23:01:38.25#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.23:01:38.25$vck44/vb=5,4 2006.173.23:01:38.25#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.23:01:38.25#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.23:01:38.25#ibcon#ireg 11 cls_cnt 2 2006.173.23:01:38.25#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.23:01:38.30#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.23:01:38.31#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.23:01:38.31#ibcon#enter wrdev, iclass 19, count 2 2006.173.23:01:38.31#ibcon#first serial, iclass 19, count 2 2006.173.23:01:38.31#ibcon#enter sib2, iclass 19, count 2 2006.173.23:01:38.31#ibcon#flushed, iclass 19, count 2 2006.173.23:01:38.31#ibcon#about to write, iclass 19, count 2 2006.173.23:01:38.31#ibcon#wrote, iclass 19, count 2 2006.173.23:01:38.31#ibcon#about to read 3, iclass 19, count 2 2006.173.23:01:38.32#ibcon#read 3, iclass 19, count 2 2006.173.23:01:38.33#ibcon#about to read 4, iclass 19, count 2 2006.173.23:01:38.33#ibcon#read 4, iclass 19, count 2 2006.173.23:01:38.33#ibcon#about to read 5, iclass 19, count 2 2006.173.23:01:38.33#ibcon#read 5, iclass 19, count 2 2006.173.23:01:38.33#ibcon#about to read 6, iclass 19, count 2 2006.173.23:01:38.33#ibcon#read 6, iclass 19, count 2 2006.173.23:01:38.33#ibcon#end of sib2, iclass 19, count 2 2006.173.23:01:38.33#ibcon#*mode == 0, iclass 19, count 2 2006.173.23:01:38.33#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.23:01:38.33#ibcon#[27=AT05-04\r\n] 2006.173.23:01:38.33#ibcon#*before write, iclass 19, count 2 2006.173.23:01:38.33#ibcon#enter sib2, iclass 19, count 2 2006.173.23:01:38.33#ibcon#flushed, iclass 19, count 2 2006.173.23:01:38.33#ibcon#about to write, iclass 19, count 2 2006.173.23:01:38.33#ibcon#wrote, iclass 19, count 2 2006.173.23:01:38.33#ibcon#about to read 3, iclass 19, count 2 2006.173.23:01:38.35#ibcon#read 3, iclass 19, count 2 2006.173.23:01:38.36#ibcon#about to read 4, iclass 19, count 2 2006.173.23:01:38.36#ibcon#read 4, iclass 19, count 2 2006.173.23:01:38.36#ibcon#about to read 5, iclass 19, count 2 2006.173.23:01:38.36#ibcon#read 5, iclass 19, count 2 2006.173.23:01:38.36#ibcon#about to read 6, iclass 19, count 2 2006.173.23:01:38.36#ibcon#read 6, iclass 19, count 2 2006.173.23:01:38.36#ibcon#end of sib2, iclass 19, count 2 2006.173.23:01:38.36#ibcon#*after write, iclass 19, count 2 2006.173.23:01:38.36#ibcon#*before return 0, iclass 19, count 2 2006.173.23:01:38.36#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.23:01:38.36#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.23:01:38.36#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.23:01:38.36#ibcon#ireg 7 cls_cnt 0 2006.173.23:01:38.36#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.23:01:38.47#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.23:01:38.48#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.23:01:38.48#ibcon#enter wrdev, iclass 19, count 0 2006.173.23:01:38.48#ibcon#first serial, iclass 19, count 0 2006.173.23:01:38.48#ibcon#enter sib2, iclass 19, count 0 2006.173.23:01:38.48#ibcon#flushed, iclass 19, count 0 2006.173.23:01:38.48#ibcon#about to write, iclass 19, count 0 2006.173.23:01:38.48#ibcon#wrote, iclass 19, count 0 2006.173.23:01:38.48#ibcon#about to read 3, iclass 19, count 0 2006.173.23:01:38.50#ibcon#read 3, iclass 19, count 0 2006.173.23:01:38.50#ibcon#about to read 4, iclass 19, count 0 2006.173.23:01:38.50#ibcon#read 4, iclass 19, count 0 2006.173.23:01:38.50#ibcon#about to read 5, iclass 19, count 0 2006.173.23:01:38.50#ibcon#read 5, iclass 19, count 0 2006.173.23:01:38.50#ibcon#about to read 6, iclass 19, count 0 2006.173.23:01:38.50#ibcon#read 6, iclass 19, count 0 2006.173.23:01:38.50#ibcon#end of sib2, iclass 19, count 0 2006.173.23:01:38.50#ibcon#*mode == 0, iclass 19, count 0 2006.173.23:01:38.50#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.23:01:38.50#ibcon#[27=USB\r\n] 2006.173.23:01:38.50#ibcon#*before write, iclass 19, count 0 2006.173.23:01:38.50#ibcon#enter sib2, iclass 19, count 0 2006.173.23:01:38.50#ibcon#flushed, iclass 19, count 0 2006.173.23:01:38.50#ibcon#about to write, iclass 19, count 0 2006.173.23:01:38.50#ibcon#wrote, iclass 19, count 0 2006.173.23:01:38.50#ibcon#about to read 3, iclass 19, count 0 2006.173.23:01:38.52#ibcon#read 3, iclass 19, count 0 2006.173.23:01:38.53#ibcon#about to read 4, iclass 19, count 0 2006.173.23:01:38.53#ibcon#read 4, iclass 19, count 0 2006.173.23:01:38.53#ibcon#about to read 5, iclass 19, count 0 2006.173.23:01:38.53#ibcon#read 5, iclass 19, count 0 2006.173.23:01:38.53#ibcon#about to read 6, iclass 19, count 0 2006.173.23:01:38.53#ibcon#read 6, iclass 19, count 0 2006.173.23:01:38.53#ibcon#end of sib2, iclass 19, count 0 2006.173.23:01:38.53#ibcon#*after write, iclass 19, count 0 2006.173.23:01:38.53#ibcon#*before return 0, iclass 19, count 0 2006.173.23:01:38.53#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.23:01:38.53#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.23:01:38.53#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.23:01:38.53#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.23:01:38.53$vck44/vblo=6,719.99 2006.173.23:01:38.53#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.23:01:38.53#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.23:01:38.53#ibcon#ireg 17 cls_cnt 0 2006.173.23:01:38.53#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.23:01:38.53#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.23:01:38.53#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.23:01:38.53#ibcon#enter wrdev, iclass 21, count 0 2006.173.23:01:38.53#ibcon#first serial, iclass 21, count 0 2006.173.23:01:38.53#ibcon#enter sib2, iclass 21, count 0 2006.173.23:01:38.53#ibcon#flushed, iclass 21, count 0 2006.173.23:01:38.53#ibcon#about to write, iclass 21, count 0 2006.173.23:01:38.53#ibcon#wrote, iclass 21, count 0 2006.173.23:01:38.53#ibcon#about to read 3, iclass 21, count 0 2006.173.23:01:38.54#ibcon#read 3, iclass 21, count 0 2006.173.23:01:38.55#ibcon#about to read 4, iclass 21, count 0 2006.173.23:01:38.55#ibcon#read 4, iclass 21, count 0 2006.173.23:01:38.55#ibcon#about to read 5, iclass 21, count 0 2006.173.23:01:38.55#ibcon#read 5, iclass 21, count 0 2006.173.23:01:38.55#ibcon#about to read 6, iclass 21, count 0 2006.173.23:01:38.55#ibcon#read 6, iclass 21, count 0 2006.173.23:01:38.55#ibcon#end of sib2, iclass 21, count 0 2006.173.23:01:38.55#ibcon#*mode == 0, iclass 21, count 0 2006.173.23:01:38.55#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.23:01:38.55#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.23:01:38.55#ibcon#*before write, iclass 21, count 0 2006.173.23:01:38.55#ibcon#enter sib2, iclass 21, count 0 2006.173.23:01:38.55#ibcon#flushed, iclass 21, count 0 2006.173.23:01:38.55#ibcon#about to write, iclass 21, count 0 2006.173.23:01:38.55#ibcon#wrote, iclass 21, count 0 2006.173.23:01:38.55#ibcon#about to read 3, iclass 21, count 0 2006.173.23:01:38.59#ibcon#read 3, iclass 21, count 0 2006.173.23:01:38.59#ibcon#about to read 4, iclass 21, count 0 2006.173.23:01:38.59#ibcon#read 4, iclass 21, count 0 2006.173.23:01:38.59#ibcon#about to read 5, iclass 21, count 0 2006.173.23:01:38.59#ibcon#read 5, iclass 21, count 0 2006.173.23:01:38.59#ibcon#about to read 6, iclass 21, count 0 2006.173.23:01:38.59#ibcon#read 6, iclass 21, count 0 2006.173.23:01:38.59#ibcon#end of sib2, iclass 21, count 0 2006.173.23:01:38.59#ibcon#*after write, iclass 21, count 0 2006.173.23:01:38.59#ibcon#*before return 0, iclass 21, count 0 2006.173.23:01:38.59#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.23:01:38.59#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.23:01:38.59#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.23:01:38.59#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.23:01:38.59$vck44/vb=6,4 2006.173.23:01:38.59#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.23:01:38.59#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.23:01:38.59#ibcon#ireg 11 cls_cnt 2 2006.173.23:01:38.59#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.23:01:38.64#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.23:01:38.65#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.23:01:38.65#ibcon#enter wrdev, iclass 23, count 2 2006.173.23:01:38.65#ibcon#first serial, iclass 23, count 2 2006.173.23:01:38.65#ibcon#enter sib2, iclass 23, count 2 2006.173.23:01:38.65#ibcon#flushed, iclass 23, count 2 2006.173.23:01:38.65#ibcon#about to write, iclass 23, count 2 2006.173.23:01:38.65#ibcon#wrote, iclass 23, count 2 2006.173.23:01:38.65#ibcon#about to read 3, iclass 23, count 2 2006.173.23:01:38.66#ibcon#read 3, iclass 23, count 2 2006.173.23:01:38.67#ibcon#about to read 4, iclass 23, count 2 2006.173.23:01:38.67#ibcon#read 4, iclass 23, count 2 2006.173.23:01:38.67#ibcon#about to read 5, iclass 23, count 2 2006.173.23:01:38.67#ibcon#read 5, iclass 23, count 2 2006.173.23:01:38.67#ibcon#about to read 6, iclass 23, count 2 2006.173.23:01:38.67#ibcon#read 6, iclass 23, count 2 2006.173.23:01:38.67#ibcon#end of sib2, iclass 23, count 2 2006.173.23:01:38.67#ibcon#*mode == 0, iclass 23, count 2 2006.173.23:01:38.67#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.23:01:38.67#ibcon#[27=AT06-04\r\n] 2006.173.23:01:38.67#ibcon#*before write, iclass 23, count 2 2006.173.23:01:38.67#ibcon#enter sib2, iclass 23, count 2 2006.173.23:01:38.67#ibcon#flushed, iclass 23, count 2 2006.173.23:01:38.67#ibcon#about to write, iclass 23, count 2 2006.173.23:01:38.67#ibcon#wrote, iclass 23, count 2 2006.173.23:01:38.67#ibcon#about to read 3, iclass 23, count 2 2006.173.23:01:38.69#ibcon#read 3, iclass 23, count 2 2006.173.23:01:38.70#ibcon#about to read 4, iclass 23, count 2 2006.173.23:01:38.70#ibcon#read 4, iclass 23, count 2 2006.173.23:01:38.70#ibcon#about to read 5, iclass 23, count 2 2006.173.23:01:38.70#ibcon#read 5, iclass 23, count 2 2006.173.23:01:38.70#ibcon#about to read 6, iclass 23, count 2 2006.173.23:01:38.70#ibcon#read 6, iclass 23, count 2 2006.173.23:01:38.70#ibcon#end of sib2, iclass 23, count 2 2006.173.23:01:38.70#ibcon#*after write, iclass 23, count 2 2006.173.23:01:38.70#ibcon#*before return 0, iclass 23, count 2 2006.173.23:01:38.70#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.23:01:38.70#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.23:01:38.70#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.23:01:38.70#ibcon#ireg 7 cls_cnt 0 2006.173.23:01:38.70#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.23:01:38.81#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.23:01:38.82#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.23:01:38.82#ibcon#enter wrdev, iclass 23, count 0 2006.173.23:01:38.82#ibcon#first serial, iclass 23, count 0 2006.173.23:01:38.82#ibcon#enter sib2, iclass 23, count 0 2006.173.23:01:38.82#ibcon#flushed, iclass 23, count 0 2006.173.23:01:38.82#ibcon#about to write, iclass 23, count 0 2006.173.23:01:38.82#ibcon#wrote, iclass 23, count 0 2006.173.23:01:38.82#ibcon#about to read 3, iclass 23, count 0 2006.173.23:01:38.83#ibcon#read 3, iclass 23, count 0 2006.173.23:01:38.84#ibcon#about to read 4, iclass 23, count 0 2006.173.23:01:38.84#ibcon#read 4, iclass 23, count 0 2006.173.23:01:38.84#ibcon#about to read 5, iclass 23, count 0 2006.173.23:01:38.84#ibcon#read 5, iclass 23, count 0 2006.173.23:01:38.84#ibcon#about to read 6, iclass 23, count 0 2006.173.23:01:38.84#ibcon#read 6, iclass 23, count 0 2006.173.23:01:38.84#ibcon#end of sib2, iclass 23, count 0 2006.173.23:01:38.84#ibcon#*mode == 0, iclass 23, count 0 2006.173.23:01:38.84#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.23:01:38.84#ibcon#[27=USB\r\n] 2006.173.23:01:38.84#ibcon#*before write, iclass 23, count 0 2006.173.23:01:38.84#ibcon#enter sib2, iclass 23, count 0 2006.173.23:01:38.84#ibcon#flushed, iclass 23, count 0 2006.173.23:01:38.84#ibcon#about to write, iclass 23, count 0 2006.173.23:01:38.84#ibcon#wrote, iclass 23, count 0 2006.173.23:01:38.84#ibcon#about to read 3, iclass 23, count 0 2006.173.23:01:38.87#ibcon#read 3, iclass 23, count 0 2006.173.23:01:38.87#ibcon#about to read 4, iclass 23, count 0 2006.173.23:01:38.87#ibcon#read 4, iclass 23, count 0 2006.173.23:01:38.87#ibcon#about to read 5, iclass 23, count 0 2006.173.23:01:38.87#ibcon#read 5, iclass 23, count 0 2006.173.23:01:38.87#ibcon#about to read 6, iclass 23, count 0 2006.173.23:01:38.87#ibcon#read 6, iclass 23, count 0 2006.173.23:01:38.87#ibcon#end of sib2, iclass 23, count 0 2006.173.23:01:38.87#ibcon#*after write, iclass 23, count 0 2006.173.23:01:38.87#ibcon#*before return 0, iclass 23, count 0 2006.173.23:01:38.87#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.23:01:38.87#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.23:01:38.87#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.23:01:38.87#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.23:01:38.87$vck44/vblo=7,734.99 2006.173.23:01:38.87#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.23:01:38.87#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.23:01:38.87#ibcon#ireg 17 cls_cnt 0 2006.173.23:01:38.87#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.23:01:38.87#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.23:01:38.87#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.23:01:38.87#ibcon#enter wrdev, iclass 25, count 0 2006.173.23:01:38.87#ibcon#first serial, iclass 25, count 0 2006.173.23:01:38.87#ibcon#enter sib2, iclass 25, count 0 2006.173.23:01:38.87#ibcon#flushed, iclass 25, count 0 2006.173.23:01:38.87#ibcon#about to write, iclass 25, count 0 2006.173.23:01:38.87#ibcon#wrote, iclass 25, count 0 2006.173.23:01:38.87#ibcon#about to read 3, iclass 25, count 0 2006.173.23:01:38.89#ibcon#read 3, iclass 25, count 0 2006.173.23:01:38.89#ibcon#about to read 4, iclass 25, count 0 2006.173.23:01:38.89#ibcon#read 4, iclass 25, count 0 2006.173.23:01:38.89#ibcon#about to read 5, iclass 25, count 0 2006.173.23:01:38.89#ibcon#read 5, iclass 25, count 0 2006.173.23:01:38.89#ibcon#about to read 6, iclass 25, count 0 2006.173.23:01:38.89#ibcon#read 6, iclass 25, count 0 2006.173.23:01:38.89#ibcon#end of sib2, iclass 25, count 0 2006.173.23:01:38.89#ibcon#*mode == 0, iclass 25, count 0 2006.173.23:01:38.89#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.23:01:38.89#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.23:01:38.89#ibcon#*before write, iclass 25, count 0 2006.173.23:01:38.89#ibcon#enter sib2, iclass 25, count 0 2006.173.23:01:38.89#ibcon#flushed, iclass 25, count 0 2006.173.23:01:38.89#ibcon#about to write, iclass 25, count 0 2006.173.23:01:38.89#ibcon#wrote, iclass 25, count 0 2006.173.23:01:38.89#ibcon#about to read 3, iclass 25, count 0 2006.173.23:01:38.92#ibcon#read 3, iclass 25, count 0 2006.173.23:01:38.93#ibcon#about to read 4, iclass 25, count 0 2006.173.23:01:38.93#ibcon#read 4, iclass 25, count 0 2006.173.23:01:38.93#ibcon#about to read 5, iclass 25, count 0 2006.173.23:01:38.93#ibcon#read 5, iclass 25, count 0 2006.173.23:01:38.93#ibcon#about to read 6, iclass 25, count 0 2006.173.23:01:38.93#ibcon#read 6, iclass 25, count 0 2006.173.23:01:38.93#ibcon#end of sib2, iclass 25, count 0 2006.173.23:01:38.93#ibcon#*after write, iclass 25, count 0 2006.173.23:01:38.93#ibcon#*before return 0, iclass 25, count 0 2006.173.23:01:38.93#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.23:01:38.93#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.23:01:38.93#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.23:01:38.93#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.23:01:38.93$vck44/vb=7,4 2006.173.23:01:38.93#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.23:01:38.93#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.23:01:38.93#ibcon#ireg 11 cls_cnt 2 2006.173.23:01:38.93#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.23:01:38.98#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.23:01:38.99#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.23:01:38.99#ibcon#enter wrdev, iclass 27, count 2 2006.173.23:01:38.99#ibcon#first serial, iclass 27, count 2 2006.173.23:01:38.99#ibcon#enter sib2, iclass 27, count 2 2006.173.23:01:38.99#ibcon#flushed, iclass 27, count 2 2006.173.23:01:38.99#ibcon#about to write, iclass 27, count 2 2006.173.23:01:38.99#ibcon#wrote, iclass 27, count 2 2006.173.23:01:38.99#ibcon#about to read 3, iclass 27, count 2 2006.173.23:01:39.00#ibcon#read 3, iclass 27, count 2 2006.173.23:01:39.01#ibcon#about to read 4, iclass 27, count 2 2006.173.23:01:39.01#ibcon#read 4, iclass 27, count 2 2006.173.23:01:39.01#ibcon#about to read 5, iclass 27, count 2 2006.173.23:01:39.01#ibcon#read 5, iclass 27, count 2 2006.173.23:01:39.01#ibcon#about to read 6, iclass 27, count 2 2006.173.23:01:39.01#ibcon#read 6, iclass 27, count 2 2006.173.23:01:39.01#ibcon#end of sib2, iclass 27, count 2 2006.173.23:01:39.01#ibcon#*mode == 0, iclass 27, count 2 2006.173.23:01:39.01#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.23:01:39.01#ibcon#[27=AT07-04\r\n] 2006.173.23:01:39.01#ibcon#*before write, iclass 27, count 2 2006.173.23:01:39.01#ibcon#enter sib2, iclass 27, count 2 2006.173.23:01:39.01#ibcon#flushed, iclass 27, count 2 2006.173.23:01:39.01#ibcon#about to write, iclass 27, count 2 2006.173.23:01:39.01#ibcon#wrote, iclass 27, count 2 2006.173.23:01:39.01#ibcon#about to read 3, iclass 27, count 2 2006.173.23:01:39.03#ibcon#read 3, iclass 27, count 2 2006.173.23:01:39.04#ibcon#about to read 4, iclass 27, count 2 2006.173.23:01:39.04#ibcon#read 4, iclass 27, count 2 2006.173.23:01:39.04#ibcon#about to read 5, iclass 27, count 2 2006.173.23:01:39.04#ibcon#read 5, iclass 27, count 2 2006.173.23:01:39.04#ibcon#about to read 6, iclass 27, count 2 2006.173.23:01:39.04#ibcon#read 6, iclass 27, count 2 2006.173.23:01:39.04#ibcon#end of sib2, iclass 27, count 2 2006.173.23:01:39.04#ibcon#*after write, iclass 27, count 2 2006.173.23:01:39.04#ibcon#*before return 0, iclass 27, count 2 2006.173.23:01:39.04#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.23:01:39.04#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.23:01:39.04#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.23:01:39.04#ibcon#ireg 7 cls_cnt 0 2006.173.23:01:39.04#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.23:01:39.16#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.23:01:39.16#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.23:01:39.16#ibcon#enter wrdev, iclass 27, count 0 2006.173.23:01:39.16#ibcon#first serial, iclass 27, count 0 2006.173.23:01:39.16#ibcon#enter sib2, iclass 27, count 0 2006.173.23:01:39.16#ibcon#flushed, iclass 27, count 0 2006.173.23:01:39.16#ibcon#about to write, iclass 27, count 0 2006.173.23:01:39.16#ibcon#wrote, iclass 27, count 0 2006.173.23:01:39.16#ibcon#about to read 3, iclass 27, count 0 2006.173.23:01:39.17#ibcon#read 3, iclass 27, count 0 2006.173.23:01:39.18#ibcon#about to read 4, iclass 27, count 0 2006.173.23:01:39.18#ibcon#read 4, iclass 27, count 0 2006.173.23:01:39.18#ibcon#about to read 5, iclass 27, count 0 2006.173.23:01:39.18#ibcon#read 5, iclass 27, count 0 2006.173.23:01:39.18#ibcon#about to read 6, iclass 27, count 0 2006.173.23:01:39.18#ibcon#read 6, iclass 27, count 0 2006.173.23:01:39.18#ibcon#end of sib2, iclass 27, count 0 2006.173.23:01:39.18#ibcon#*mode == 0, iclass 27, count 0 2006.173.23:01:39.18#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.23:01:39.18#ibcon#[27=USB\r\n] 2006.173.23:01:39.18#ibcon#*before write, iclass 27, count 0 2006.173.23:01:39.18#ibcon#enter sib2, iclass 27, count 0 2006.173.23:01:39.18#ibcon#flushed, iclass 27, count 0 2006.173.23:01:39.18#ibcon#about to write, iclass 27, count 0 2006.173.23:01:39.18#ibcon#wrote, iclass 27, count 0 2006.173.23:01:39.18#ibcon#about to read 3, iclass 27, count 0 2006.173.23:01:39.20#ibcon#read 3, iclass 27, count 0 2006.173.23:01:39.21#ibcon#about to read 4, iclass 27, count 0 2006.173.23:01:39.21#ibcon#read 4, iclass 27, count 0 2006.173.23:01:39.21#ibcon#about to read 5, iclass 27, count 0 2006.173.23:01:39.21#ibcon#read 5, iclass 27, count 0 2006.173.23:01:39.21#ibcon#about to read 6, iclass 27, count 0 2006.173.23:01:39.21#ibcon#read 6, iclass 27, count 0 2006.173.23:01:39.21#ibcon#end of sib2, iclass 27, count 0 2006.173.23:01:39.21#ibcon#*after write, iclass 27, count 0 2006.173.23:01:39.21#ibcon#*before return 0, iclass 27, count 0 2006.173.23:01:39.21#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.23:01:39.21#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.23:01:39.21#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.23:01:39.21#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.23:01:39.21$vck44/vblo=8,744.99 2006.173.23:01:39.21#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.23:01:39.21#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.23:01:39.21#ibcon#ireg 17 cls_cnt 0 2006.173.23:01:39.21#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.23:01:39.21#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.23:01:39.21#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.23:01:39.21#ibcon#enter wrdev, iclass 29, count 0 2006.173.23:01:39.21#ibcon#first serial, iclass 29, count 0 2006.173.23:01:39.21#ibcon#enter sib2, iclass 29, count 0 2006.173.23:01:39.21#ibcon#flushed, iclass 29, count 0 2006.173.23:01:39.21#ibcon#about to write, iclass 29, count 0 2006.173.23:01:39.21#ibcon#wrote, iclass 29, count 0 2006.173.23:01:39.21#ibcon#about to read 3, iclass 29, count 0 2006.173.23:01:39.23#ibcon#read 3, iclass 29, count 0 2006.173.23:01:39.23#ibcon#about to read 4, iclass 29, count 0 2006.173.23:01:39.23#ibcon#read 4, iclass 29, count 0 2006.173.23:01:39.23#ibcon#about to read 5, iclass 29, count 0 2006.173.23:01:39.23#ibcon#read 5, iclass 29, count 0 2006.173.23:01:39.23#ibcon#about to read 6, iclass 29, count 0 2006.173.23:01:39.23#ibcon#read 6, iclass 29, count 0 2006.173.23:01:39.23#ibcon#end of sib2, iclass 29, count 0 2006.173.23:01:39.23#ibcon#*mode == 0, iclass 29, count 0 2006.173.23:01:39.23#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.23:01:39.23#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.23:01:39.23#ibcon#*before write, iclass 29, count 0 2006.173.23:01:39.23#ibcon#enter sib2, iclass 29, count 0 2006.173.23:01:39.23#ibcon#flushed, iclass 29, count 0 2006.173.23:01:39.23#ibcon#about to write, iclass 29, count 0 2006.173.23:01:39.23#ibcon#wrote, iclass 29, count 0 2006.173.23:01:39.23#ibcon#about to read 3, iclass 29, count 0 2006.173.23:01:39.27#ibcon#read 3, iclass 29, count 0 2006.173.23:01:39.27#ibcon#about to read 4, iclass 29, count 0 2006.173.23:01:39.27#ibcon#read 4, iclass 29, count 0 2006.173.23:01:39.27#ibcon#about to read 5, iclass 29, count 0 2006.173.23:01:39.27#ibcon#read 5, iclass 29, count 0 2006.173.23:01:39.27#ibcon#about to read 6, iclass 29, count 0 2006.173.23:01:39.27#ibcon#read 6, iclass 29, count 0 2006.173.23:01:39.27#ibcon#end of sib2, iclass 29, count 0 2006.173.23:01:39.27#ibcon#*after write, iclass 29, count 0 2006.173.23:01:39.27#ibcon#*before return 0, iclass 29, count 0 2006.173.23:01:39.27#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.23:01:39.27#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.23:01:39.27#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.23:01:39.27#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.23:01:39.27$vck44/vb=8,4 2006.173.23:01:39.27#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.23:01:39.27#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.23:01:39.27#ibcon#ireg 11 cls_cnt 2 2006.173.23:01:39.27#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.23:01:39.32#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.23:01:39.33#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.23:01:39.33#ibcon#enter wrdev, iclass 31, count 2 2006.173.23:01:39.33#ibcon#first serial, iclass 31, count 2 2006.173.23:01:39.33#ibcon#enter sib2, iclass 31, count 2 2006.173.23:01:39.33#ibcon#flushed, iclass 31, count 2 2006.173.23:01:39.33#ibcon#about to write, iclass 31, count 2 2006.173.23:01:39.33#ibcon#wrote, iclass 31, count 2 2006.173.23:01:39.33#ibcon#about to read 3, iclass 31, count 2 2006.173.23:01:39.34#ibcon#read 3, iclass 31, count 2 2006.173.23:01:39.35#ibcon#about to read 4, iclass 31, count 2 2006.173.23:01:39.35#ibcon#read 4, iclass 31, count 2 2006.173.23:01:39.35#ibcon#about to read 5, iclass 31, count 2 2006.173.23:01:39.35#ibcon#read 5, iclass 31, count 2 2006.173.23:01:39.35#ibcon#about to read 6, iclass 31, count 2 2006.173.23:01:39.35#ibcon#read 6, iclass 31, count 2 2006.173.23:01:39.35#ibcon#end of sib2, iclass 31, count 2 2006.173.23:01:39.35#ibcon#*mode == 0, iclass 31, count 2 2006.173.23:01:39.35#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.23:01:39.35#ibcon#[27=AT08-04\r\n] 2006.173.23:01:39.35#ibcon#*before write, iclass 31, count 2 2006.173.23:01:39.35#ibcon#enter sib2, iclass 31, count 2 2006.173.23:01:39.35#ibcon#flushed, iclass 31, count 2 2006.173.23:01:39.35#ibcon#about to write, iclass 31, count 2 2006.173.23:01:39.35#ibcon#wrote, iclass 31, count 2 2006.173.23:01:39.35#ibcon#about to read 3, iclass 31, count 2 2006.173.23:01:39.37#ibcon#read 3, iclass 31, count 2 2006.173.23:01:39.38#ibcon#about to read 4, iclass 31, count 2 2006.173.23:01:39.38#ibcon#read 4, iclass 31, count 2 2006.173.23:01:39.38#ibcon#about to read 5, iclass 31, count 2 2006.173.23:01:39.38#ibcon#read 5, iclass 31, count 2 2006.173.23:01:39.38#ibcon#about to read 6, iclass 31, count 2 2006.173.23:01:39.38#ibcon#read 6, iclass 31, count 2 2006.173.23:01:39.38#ibcon#end of sib2, iclass 31, count 2 2006.173.23:01:39.38#ibcon#*after write, iclass 31, count 2 2006.173.23:01:39.38#ibcon#*before return 0, iclass 31, count 2 2006.173.23:01:39.38#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.23:01:39.38#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.23:01:39.38#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.23:01:39.38#ibcon#ireg 7 cls_cnt 0 2006.173.23:01:39.38#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.23:01:39.49#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.23:01:39.50#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.23:01:39.50#ibcon#enter wrdev, iclass 31, count 0 2006.173.23:01:39.50#ibcon#first serial, iclass 31, count 0 2006.173.23:01:39.50#ibcon#enter sib2, iclass 31, count 0 2006.173.23:01:39.50#ibcon#flushed, iclass 31, count 0 2006.173.23:01:39.50#ibcon#about to write, iclass 31, count 0 2006.173.23:01:39.50#ibcon#wrote, iclass 31, count 0 2006.173.23:01:39.50#ibcon#about to read 3, iclass 31, count 0 2006.173.23:01:39.51#ibcon#read 3, iclass 31, count 0 2006.173.23:01:39.52#ibcon#about to read 4, iclass 31, count 0 2006.173.23:01:39.52#ibcon#read 4, iclass 31, count 0 2006.173.23:01:39.52#ibcon#about to read 5, iclass 31, count 0 2006.173.23:01:39.52#ibcon#read 5, iclass 31, count 0 2006.173.23:01:39.52#ibcon#about to read 6, iclass 31, count 0 2006.173.23:01:39.52#ibcon#read 6, iclass 31, count 0 2006.173.23:01:39.52#ibcon#end of sib2, iclass 31, count 0 2006.173.23:01:39.52#ibcon#*mode == 0, iclass 31, count 0 2006.173.23:01:39.52#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.23:01:39.52#ibcon#[27=USB\r\n] 2006.173.23:01:39.52#ibcon#*before write, iclass 31, count 0 2006.173.23:01:39.52#ibcon#enter sib2, iclass 31, count 0 2006.173.23:01:39.52#ibcon#flushed, iclass 31, count 0 2006.173.23:01:39.52#ibcon#about to write, iclass 31, count 0 2006.173.23:01:39.52#ibcon#wrote, iclass 31, count 0 2006.173.23:01:39.52#ibcon#about to read 3, iclass 31, count 0 2006.173.23:01:39.55#ibcon#read 3, iclass 31, count 0 2006.173.23:01:39.55#ibcon#about to read 4, iclass 31, count 0 2006.173.23:01:39.55#ibcon#read 4, iclass 31, count 0 2006.173.23:01:39.55#ibcon#about to read 5, iclass 31, count 0 2006.173.23:01:39.55#ibcon#read 5, iclass 31, count 0 2006.173.23:01:39.55#ibcon#about to read 6, iclass 31, count 0 2006.173.23:01:39.55#ibcon#read 6, iclass 31, count 0 2006.173.23:01:39.55#ibcon#end of sib2, iclass 31, count 0 2006.173.23:01:39.55#ibcon#*after write, iclass 31, count 0 2006.173.23:01:39.55#ibcon#*before return 0, iclass 31, count 0 2006.173.23:01:39.55#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.23:01:39.55#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.23:01:39.55#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.23:01:39.55#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.23:01:39.55$vck44/vabw=wide 2006.173.23:01:39.55#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.23:01:39.55#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.23:01:39.55#ibcon#ireg 8 cls_cnt 0 2006.173.23:01:39.55#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.23:01:39.55#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.23:01:39.55#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.23:01:39.55#ibcon#enter wrdev, iclass 33, count 0 2006.173.23:01:39.55#ibcon#first serial, iclass 33, count 0 2006.173.23:01:39.55#ibcon#enter sib2, iclass 33, count 0 2006.173.23:01:39.55#ibcon#flushed, iclass 33, count 0 2006.173.23:01:39.55#ibcon#about to write, iclass 33, count 0 2006.173.23:01:39.55#ibcon#wrote, iclass 33, count 0 2006.173.23:01:39.55#ibcon#about to read 3, iclass 33, count 0 2006.173.23:01:39.57#ibcon#read 3, iclass 33, count 0 2006.173.23:01:39.57#ibcon#about to read 4, iclass 33, count 0 2006.173.23:01:39.57#ibcon#read 4, iclass 33, count 0 2006.173.23:01:39.57#ibcon#about to read 5, iclass 33, count 0 2006.173.23:01:39.57#ibcon#read 5, iclass 33, count 0 2006.173.23:01:39.57#ibcon#about to read 6, iclass 33, count 0 2006.173.23:01:39.57#ibcon#read 6, iclass 33, count 0 2006.173.23:01:39.57#ibcon#end of sib2, iclass 33, count 0 2006.173.23:01:39.57#ibcon#*mode == 0, iclass 33, count 0 2006.173.23:01:39.57#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.23:01:39.57#ibcon#[25=BW32\r\n] 2006.173.23:01:39.57#ibcon#*before write, iclass 33, count 0 2006.173.23:01:39.57#ibcon#enter sib2, iclass 33, count 0 2006.173.23:01:39.57#ibcon#flushed, iclass 33, count 0 2006.173.23:01:39.57#ibcon#about to write, iclass 33, count 0 2006.173.23:01:39.57#ibcon#wrote, iclass 33, count 0 2006.173.23:01:39.57#ibcon#about to read 3, iclass 33, count 0 2006.173.23:01:39.59#ibcon#read 3, iclass 33, count 0 2006.173.23:01:39.60#ibcon#about to read 4, iclass 33, count 0 2006.173.23:01:39.60#ibcon#read 4, iclass 33, count 0 2006.173.23:01:39.60#ibcon#about to read 5, iclass 33, count 0 2006.173.23:01:39.60#ibcon#read 5, iclass 33, count 0 2006.173.23:01:39.60#ibcon#about to read 6, iclass 33, count 0 2006.173.23:01:39.60#ibcon#read 6, iclass 33, count 0 2006.173.23:01:39.60#ibcon#end of sib2, iclass 33, count 0 2006.173.23:01:39.60#ibcon#*after write, iclass 33, count 0 2006.173.23:01:39.60#ibcon#*before return 0, iclass 33, count 0 2006.173.23:01:39.60#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.23:01:39.60#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.23:01:39.60#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.23:01:39.60#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.23:01:39.60$vck44/vbbw=wide 2006.173.23:01:39.60#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.23:01:39.60#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.23:01:39.60#ibcon#ireg 8 cls_cnt 0 2006.173.23:01:39.60#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.23:01:39.66#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.23:01:39.67#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.23:01:39.67#ibcon#enter wrdev, iclass 35, count 0 2006.173.23:01:39.67#ibcon#first serial, iclass 35, count 0 2006.173.23:01:39.67#ibcon#enter sib2, iclass 35, count 0 2006.173.23:01:39.67#ibcon#flushed, iclass 35, count 0 2006.173.23:01:39.67#ibcon#about to write, iclass 35, count 0 2006.173.23:01:39.67#ibcon#wrote, iclass 35, count 0 2006.173.23:01:39.67#ibcon#about to read 3, iclass 35, count 0 2006.173.23:01:39.68#ibcon#read 3, iclass 35, count 0 2006.173.23:01:39.69#ibcon#about to read 4, iclass 35, count 0 2006.173.23:01:39.69#ibcon#read 4, iclass 35, count 0 2006.173.23:01:39.69#ibcon#about to read 5, iclass 35, count 0 2006.173.23:01:39.69#ibcon#read 5, iclass 35, count 0 2006.173.23:01:39.69#ibcon#about to read 6, iclass 35, count 0 2006.173.23:01:39.69#ibcon#read 6, iclass 35, count 0 2006.173.23:01:39.69#ibcon#end of sib2, iclass 35, count 0 2006.173.23:01:39.69#ibcon#*mode == 0, iclass 35, count 0 2006.173.23:01:39.69#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.23:01:39.69#ibcon#[27=BW32\r\n] 2006.173.23:01:39.69#ibcon#*before write, iclass 35, count 0 2006.173.23:01:39.69#ibcon#enter sib2, iclass 35, count 0 2006.173.23:01:39.69#ibcon#flushed, iclass 35, count 0 2006.173.23:01:39.69#ibcon#about to write, iclass 35, count 0 2006.173.23:01:39.69#ibcon#wrote, iclass 35, count 0 2006.173.23:01:39.69#ibcon#about to read 3, iclass 35, count 0 2006.173.23:01:39.71#ibcon#read 3, iclass 35, count 0 2006.173.23:01:39.71#ibcon#about to read 4, iclass 35, count 0 2006.173.23:01:39.72#ibcon#read 4, iclass 35, count 0 2006.173.23:01:39.72#ibcon#about to read 5, iclass 35, count 0 2006.173.23:01:39.72#ibcon#read 5, iclass 35, count 0 2006.173.23:01:39.72#ibcon#about to read 6, iclass 35, count 0 2006.173.23:01:39.72#ibcon#read 6, iclass 35, count 0 2006.173.23:01:39.72#ibcon#end of sib2, iclass 35, count 0 2006.173.23:01:39.72#ibcon#*after write, iclass 35, count 0 2006.173.23:01:39.72#ibcon#*before return 0, iclass 35, count 0 2006.173.23:01:39.72#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.23:01:39.72#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.23:01:39.72#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.23:01:39.72#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.23:01:39.72$setupk4/ifdk4 2006.173.23:01:39.72$ifdk4/lo= 2006.173.23:01:39.72$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.23:01:39.72$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.23:01:39.72$ifdk4/patch= 2006.173.23:01:39.72$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.23:01:39.72$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.23:01:39.72$setupk4/!*+20s 2006.173.23:01:42.69#abcon#<5=/10 0.9 2.0 22.80 931003.2\r\n> 2006.173.23:01:42.72#abcon#{5=INTERFACE CLEAR} 2006.173.23:01:42.78#abcon#[5=S1D000X0/0*\r\n] 2006.173.23:01:45.14#trakl#Source acquired 2006.173.23:01:45.14#flagr#flagr/antenna,acquired 2006.173.23:01:52.86#abcon#<5=/10 0.9 2.0 22.81 921003.2\r\n> 2006.173.23:01:52.88#abcon#{5=INTERFACE CLEAR} 2006.173.23:01:52.94#abcon#[5=S1D000X0/0*\r\n] 2006.173.23:01:54.25$setupk4/"tpicd 2006.173.23:01:54.25$setupk4/echo=off 2006.173.23:01:54.25$setupk4/xlog=off 2006.173.23:01:54.25:!2006.173.23:05:29 2006.173.23:05:29.01:preob 2006.173.23:05:30.14/onsource/TRACKING 2006.173.23:05:30.14:!2006.173.23:05:39 2006.173.23:05:39.00:"tape 2006.173.23:05:39.00:"st=record 2006.173.23:05:39.00:data_valid=on 2006.173.23:05:39.00:midob 2006.173.23:05:39.14/onsource/TRACKING 2006.173.23:05:39.15/wx/22.91,1003.2,91 2006.173.23:05:39.28/cable/+6.5125E-03 2006.173.23:05:40.37/va/01,07,usb,yes,37,40 2006.173.23:05:40.37/va/02,06,usb,yes,37,37 2006.173.23:05:40.37/va/03,05,usb,yes,47,49 2006.173.23:05:40.37/va/04,06,usb,yes,37,39 2006.173.23:05:40.37/va/05,04,usb,yes,29,30 2006.173.23:05:40.37/va/06,03,usb,yes,41,41 2006.173.23:05:40.37/va/07,04,usb,yes,33,34 2006.173.23:05:40.37/va/08,04,usb,yes,28,34 2006.173.23:05:40.60/valo/01,524.99,yes,locked 2006.173.23:05:40.60/valo/02,534.99,yes,locked 2006.173.23:05:40.60/valo/03,564.99,yes,locked 2006.173.23:05:40.60/valo/04,624.99,yes,locked 2006.173.23:05:40.60/valo/05,734.99,yes,locked 2006.173.23:05:40.60/valo/06,814.99,yes,locked 2006.173.23:05:40.60/valo/07,864.99,yes,locked 2006.173.23:05:40.60/valo/08,884.99,yes,locked 2006.173.23:05:41.69/vb/01,04,usb,yes,30,28 2006.173.23:05:41.69/vb/02,04,usb,yes,33,33 2006.173.23:05:41.69/vb/03,04,usb,yes,30,33 2006.173.23:05:41.69/vb/04,04,usb,yes,34,33 2006.173.23:05:41.69/vb/05,04,usb,yes,26,29 2006.173.23:05:41.69/vb/06,04,usb,yes,31,27 2006.173.23:05:41.69/vb/07,04,usb,yes,31,31 2006.173.23:05:41.69/vb/08,04,usb,yes,28,32 2006.173.23:05:41.92/vblo/01,629.99,yes,locked 2006.173.23:05:41.92/vblo/02,634.99,yes,locked 2006.173.23:05:41.92/vblo/03,649.99,yes,locked 2006.173.23:05:41.92/vblo/04,679.99,yes,locked 2006.173.23:05:41.92/vblo/05,709.99,yes,locked 2006.173.23:05:41.92/vblo/06,719.99,yes,locked 2006.173.23:05:41.92/vblo/07,734.99,yes,locked 2006.173.23:05:41.92/vblo/08,744.99,yes,locked 2006.173.23:05:42.07/vabw/8 2006.173.23:05:42.22/vbbw/8 2006.173.23:05:42.31/xfe/off,on,15.0 2006.173.23:05:42.69/ifatt/23,28,28,28 2006.173.23:05:43.07/fmout-gps/S +3.90E-07 2006.173.23:05:43.12:!2006.173.23:09:09 2006.173.23:09:09.01:data_valid=off 2006.173.23:09:09.01:"et 2006.173.23:09:09.01:!+3s 2006.173.23:09:12.02:"tape 2006.173.23:09:12.02:postob 2006.173.23:09:12.25/cable/+6.5126E-03 2006.173.23:09:12.25/wx/22.96,1003.2,90 2006.173.23:09:12.31/fmout-gps/S +3.93E-07 2006.173.23:09:12.31:scan_name=173-2311,jd0606,210 2006.173.23:09:12.31:source=0059+581,010245.76,582411.1,2000.0,ccw 2006.173.23:09:14.13#flagr#flagr/antenna,new-source 2006.173.23:09:14.13:checkk5 2006.173.23:09:14.56/chk_autoobs//k5ts1/ autoobs is running! 2006.173.23:09:14.96/chk_autoobs//k5ts2/ autoobs is running! 2006.173.23:09:15.37/chk_autoobs//k5ts3/ autoobs is running! 2006.173.23:09:15.77/chk_autoobs//k5ts4/ autoobs is running! 2006.173.23:09:16.17/chk_obsdata//k5ts1/T1732305??a.dat file size is correct (nominal:840MB, actual:836MB). 2006.173.23:09:16.57/chk_obsdata//k5ts2/T1732305??b.dat file size is correct (nominal:840MB, actual:836MB). 2006.173.23:09:16.97/chk_obsdata//k5ts3/T1732305??c.dat file size is correct (nominal:840MB, actual:836MB). 2006.173.23:09:17.37/chk_obsdata//k5ts4/T1732305??d.dat file size is correct (nominal:840MB, actual:836MB). 2006.173.23:09:18.11/k5log//k5ts1_log_newline 2006.173.23:09:18.83/k5log//k5ts2_log_newline 2006.173.23:09:19.55/k5log//k5ts3_log_newline 2006.173.23:09:20.26/k5log//k5ts4_log_newline 2006.173.23:09:20.29/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.23:09:20.29:setupk4=1 2006.173.23:09:20.29$setupk4/echo=on 2006.173.23:09:20.29$setupk4/pcalon 2006.173.23:09:20.29$pcalon/"no phase cal control is implemented here 2006.173.23:09:20.29$setupk4/"tpicd=stop 2006.173.23:09:20.29$setupk4/"rec=synch_on 2006.173.23:09:20.29$setupk4/"rec_mode=128 2006.173.23:09:20.29$setupk4/!* 2006.173.23:09:20.29$setupk4/recpk4 2006.173.23:09:20.29$recpk4/recpatch= 2006.173.23:09:20.29$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.23:09:20.29$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.23:09:20.29$setupk4/vck44 2006.173.23:09:20.29$vck44/valo=1,524.99 2006.173.23:09:20.29#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.23:09:20.29#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.23:09:20.29#ibcon#ireg 17 cls_cnt 0 2006.173.23:09:20.29#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.23:09:20.29#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.23:09:20.29#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.23:09:20.29#ibcon#enter wrdev, iclass 40, count 0 2006.173.23:09:20.29#ibcon#first serial, iclass 40, count 0 2006.173.23:09:20.29#ibcon#enter sib2, iclass 40, count 0 2006.173.23:09:20.29#ibcon#flushed, iclass 40, count 0 2006.173.23:09:20.29#ibcon#about to write, iclass 40, count 0 2006.173.23:09:20.29#ibcon#wrote, iclass 40, count 0 2006.173.23:09:20.29#ibcon#about to read 3, iclass 40, count 0 2006.173.23:09:20.30#ibcon#read 3, iclass 40, count 0 2006.173.23:09:20.30#ibcon#about to read 4, iclass 40, count 0 2006.173.23:09:20.30#ibcon#read 4, iclass 40, count 0 2006.173.23:09:20.30#ibcon#about to read 5, iclass 40, count 0 2006.173.23:09:20.30#ibcon#read 5, iclass 40, count 0 2006.173.23:09:20.30#ibcon#about to read 6, iclass 40, count 0 2006.173.23:09:20.30#ibcon#read 6, iclass 40, count 0 2006.173.23:09:20.30#ibcon#end of sib2, iclass 40, count 0 2006.173.23:09:20.30#ibcon#*mode == 0, iclass 40, count 0 2006.173.23:09:20.30#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.23:09:20.30#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.23:09:20.30#ibcon#*before write, iclass 40, count 0 2006.173.23:09:20.30#ibcon#enter sib2, iclass 40, count 0 2006.173.23:09:20.30#ibcon#flushed, iclass 40, count 0 2006.173.23:09:20.30#ibcon#about to write, iclass 40, count 0 2006.173.23:09:20.30#ibcon#wrote, iclass 40, count 0 2006.173.23:09:20.30#ibcon#about to read 3, iclass 40, count 0 2006.173.23:09:20.35#ibcon#read 3, iclass 40, count 0 2006.173.23:09:20.35#ibcon#about to read 4, iclass 40, count 0 2006.173.23:09:20.35#ibcon#read 4, iclass 40, count 0 2006.173.23:09:20.35#ibcon#about to read 5, iclass 40, count 0 2006.173.23:09:20.35#ibcon#read 5, iclass 40, count 0 2006.173.23:09:20.35#ibcon#about to read 6, iclass 40, count 0 2006.173.23:09:20.35#ibcon#read 6, iclass 40, count 0 2006.173.23:09:20.35#ibcon#end of sib2, iclass 40, count 0 2006.173.23:09:20.35#ibcon#*after write, iclass 40, count 0 2006.173.23:09:20.35#ibcon#*before return 0, iclass 40, count 0 2006.173.23:09:20.35#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.23:09:20.35#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.23:09:20.35#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.23:09:20.35#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.23:09:20.35$vck44/va=1,7 2006.173.23:09:20.35#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.23:09:20.35#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.23:09:20.35#ibcon#ireg 11 cls_cnt 2 2006.173.23:09:20.35#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.23:09:20.35#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.23:09:20.35#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.23:09:20.35#ibcon#enter wrdev, iclass 4, count 2 2006.173.23:09:20.35#ibcon#first serial, iclass 4, count 2 2006.173.23:09:20.35#ibcon#enter sib2, iclass 4, count 2 2006.173.23:09:20.35#ibcon#flushed, iclass 4, count 2 2006.173.23:09:20.35#ibcon#about to write, iclass 4, count 2 2006.173.23:09:20.35#ibcon#wrote, iclass 4, count 2 2006.173.23:09:20.35#ibcon#about to read 3, iclass 4, count 2 2006.173.23:09:20.37#ibcon#read 3, iclass 4, count 2 2006.173.23:09:20.37#ibcon#about to read 4, iclass 4, count 2 2006.173.23:09:20.37#ibcon#read 4, iclass 4, count 2 2006.173.23:09:20.37#ibcon#about to read 5, iclass 4, count 2 2006.173.23:09:20.37#ibcon#read 5, iclass 4, count 2 2006.173.23:09:20.37#ibcon#about to read 6, iclass 4, count 2 2006.173.23:09:20.37#ibcon#read 6, iclass 4, count 2 2006.173.23:09:20.37#ibcon#end of sib2, iclass 4, count 2 2006.173.23:09:20.37#ibcon#*mode == 0, iclass 4, count 2 2006.173.23:09:20.37#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.23:09:20.37#ibcon#[25=AT01-07\r\n] 2006.173.23:09:20.37#ibcon#*before write, iclass 4, count 2 2006.173.23:09:20.37#ibcon#enter sib2, iclass 4, count 2 2006.173.23:09:20.37#ibcon#flushed, iclass 4, count 2 2006.173.23:09:20.37#ibcon#about to write, iclass 4, count 2 2006.173.23:09:20.37#ibcon#wrote, iclass 4, count 2 2006.173.23:09:20.37#ibcon#about to read 3, iclass 4, count 2 2006.173.23:09:20.40#ibcon#read 3, iclass 4, count 2 2006.173.23:09:20.40#ibcon#about to read 4, iclass 4, count 2 2006.173.23:09:20.40#ibcon#read 4, iclass 4, count 2 2006.173.23:09:20.40#ibcon#about to read 5, iclass 4, count 2 2006.173.23:09:20.40#ibcon#read 5, iclass 4, count 2 2006.173.23:09:20.40#ibcon#about to read 6, iclass 4, count 2 2006.173.23:09:20.40#ibcon#read 6, iclass 4, count 2 2006.173.23:09:20.40#ibcon#end of sib2, iclass 4, count 2 2006.173.23:09:20.40#ibcon#*after write, iclass 4, count 2 2006.173.23:09:20.40#ibcon#*before return 0, iclass 4, count 2 2006.173.23:09:20.40#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.23:09:20.40#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.23:09:20.40#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.23:09:20.40#ibcon#ireg 7 cls_cnt 0 2006.173.23:09:20.40#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.23:09:20.49#abcon#<5=/09 0.6 2.0 22.96 901003.2\r\n> 2006.173.23:09:20.51#abcon#{5=INTERFACE CLEAR} 2006.173.23:09:20.52#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.23:09:20.52#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.23:09:20.52#ibcon#enter wrdev, iclass 4, count 0 2006.173.23:09:20.52#ibcon#first serial, iclass 4, count 0 2006.173.23:09:20.52#ibcon#enter sib2, iclass 4, count 0 2006.173.23:09:20.52#ibcon#flushed, iclass 4, count 0 2006.173.23:09:20.52#ibcon#about to write, iclass 4, count 0 2006.173.23:09:20.52#ibcon#wrote, iclass 4, count 0 2006.173.23:09:20.52#ibcon#about to read 3, iclass 4, count 0 2006.173.23:09:20.54#ibcon#read 3, iclass 4, count 0 2006.173.23:09:20.54#ibcon#about to read 4, iclass 4, count 0 2006.173.23:09:20.54#ibcon#read 4, iclass 4, count 0 2006.173.23:09:20.54#ibcon#about to read 5, iclass 4, count 0 2006.173.23:09:20.54#ibcon#read 5, iclass 4, count 0 2006.173.23:09:20.54#ibcon#about to read 6, iclass 4, count 0 2006.173.23:09:20.54#ibcon#read 6, iclass 4, count 0 2006.173.23:09:20.54#ibcon#end of sib2, iclass 4, count 0 2006.173.23:09:20.54#ibcon#*mode == 0, iclass 4, count 0 2006.173.23:09:20.54#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.23:09:20.54#ibcon#[25=USB\r\n] 2006.173.23:09:20.54#ibcon#*before write, iclass 4, count 0 2006.173.23:09:20.54#ibcon#enter sib2, iclass 4, count 0 2006.173.23:09:20.54#ibcon#flushed, iclass 4, count 0 2006.173.23:09:20.54#ibcon#about to write, iclass 4, count 0 2006.173.23:09:20.54#ibcon#wrote, iclass 4, count 0 2006.173.23:09:20.54#ibcon#about to read 3, iclass 4, count 0 2006.173.23:09:20.57#abcon#[5=S1D000X0/0*\r\n] 2006.173.23:09:20.57#ibcon#read 3, iclass 4, count 0 2006.173.23:09:20.57#ibcon#about to read 4, iclass 4, count 0 2006.173.23:09:20.57#ibcon#read 4, iclass 4, count 0 2006.173.23:09:20.57#ibcon#about to read 5, iclass 4, count 0 2006.173.23:09:20.57#ibcon#read 5, iclass 4, count 0 2006.173.23:09:20.57#ibcon#about to read 6, iclass 4, count 0 2006.173.23:09:20.57#ibcon#read 6, iclass 4, count 0 2006.173.23:09:20.57#ibcon#end of sib2, iclass 4, count 0 2006.173.23:09:20.57#ibcon#*after write, iclass 4, count 0 2006.173.23:09:20.57#ibcon#*before return 0, iclass 4, count 0 2006.173.23:09:20.57#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.23:09:20.57#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.23:09:20.57#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.23:09:20.57#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.23:09:20.57$vck44/valo=2,534.99 2006.173.23:09:20.57#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.23:09:20.57#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.23:09:20.57#ibcon#ireg 17 cls_cnt 0 2006.173.23:09:20.57#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.23:09:20.57#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.23:09:20.57#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.23:09:20.57#ibcon#enter wrdev, iclass 12, count 0 2006.173.23:09:20.57#ibcon#first serial, iclass 12, count 0 2006.173.23:09:20.57#ibcon#enter sib2, iclass 12, count 0 2006.173.23:09:20.57#ibcon#flushed, iclass 12, count 0 2006.173.23:09:20.57#ibcon#about to write, iclass 12, count 0 2006.173.23:09:20.57#ibcon#wrote, iclass 12, count 0 2006.173.23:09:20.57#ibcon#about to read 3, iclass 12, count 0 2006.173.23:09:20.59#ibcon#read 3, iclass 12, count 0 2006.173.23:09:20.59#ibcon#about to read 4, iclass 12, count 0 2006.173.23:09:20.59#ibcon#read 4, iclass 12, count 0 2006.173.23:09:20.59#ibcon#about to read 5, iclass 12, count 0 2006.173.23:09:20.59#ibcon#read 5, iclass 12, count 0 2006.173.23:09:20.59#ibcon#about to read 6, iclass 12, count 0 2006.173.23:09:20.59#ibcon#read 6, iclass 12, count 0 2006.173.23:09:20.59#ibcon#end of sib2, iclass 12, count 0 2006.173.23:09:20.59#ibcon#*mode == 0, iclass 12, count 0 2006.173.23:09:20.59#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.23:09:20.59#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.23:09:20.59#ibcon#*before write, iclass 12, count 0 2006.173.23:09:20.59#ibcon#enter sib2, iclass 12, count 0 2006.173.23:09:20.59#ibcon#flushed, iclass 12, count 0 2006.173.23:09:20.59#ibcon#about to write, iclass 12, count 0 2006.173.23:09:20.59#ibcon#wrote, iclass 12, count 0 2006.173.23:09:20.59#ibcon#about to read 3, iclass 12, count 0 2006.173.23:09:20.63#ibcon#read 3, iclass 12, count 0 2006.173.23:09:20.63#ibcon#about to read 4, iclass 12, count 0 2006.173.23:09:20.63#ibcon#read 4, iclass 12, count 0 2006.173.23:09:20.63#ibcon#about to read 5, iclass 12, count 0 2006.173.23:09:20.63#ibcon#read 5, iclass 12, count 0 2006.173.23:09:20.63#ibcon#about to read 6, iclass 12, count 0 2006.173.23:09:20.63#ibcon#read 6, iclass 12, count 0 2006.173.23:09:20.63#ibcon#end of sib2, iclass 12, count 0 2006.173.23:09:20.63#ibcon#*after write, iclass 12, count 0 2006.173.23:09:20.63#ibcon#*before return 0, iclass 12, count 0 2006.173.23:09:20.63#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.23:09:20.63#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.23:09:20.63#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.23:09:20.63#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.23:09:20.63$vck44/va=2,6 2006.173.23:09:20.63#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.23:09:20.63#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.23:09:20.63#ibcon#ireg 11 cls_cnt 2 2006.173.23:09:20.63#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.23:09:20.69#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.23:09:20.69#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.23:09:20.69#ibcon#enter wrdev, iclass 14, count 2 2006.173.23:09:20.69#ibcon#first serial, iclass 14, count 2 2006.173.23:09:20.69#ibcon#enter sib2, iclass 14, count 2 2006.173.23:09:20.69#ibcon#flushed, iclass 14, count 2 2006.173.23:09:20.69#ibcon#about to write, iclass 14, count 2 2006.173.23:09:20.69#ibcon#wrote, iclass 14, count 2 2006.173.23:09:20.69#ibcon#about to read 3, iclass 14, count 2 2006.173.23:09:20.71#ibcon#read 3, iclass 14, count 2 2006.173.23:09:20.71#ibcon#about to read 4, iclass 14, count 2 2006.173.23:09:20.71#ibcon#read 4, iclass 14, count 2 2006.173.23:09:20.71#ibcon#about to read 5, iclass 14, count 2 2006.173.23:09:20.71#ibcon#read 5, iclass 14, count 2 2006.173.23:09:20.71#ibcon#about to read 6, iclass 14, count 2 2006.173.23:09:20.71#ibcon#read 6, iclass 14, count 2 2006.173.23:09:20.71#ibcon#end of sib2, iclass 14, count 2 2006.173.23:09:20.71#ibcon#*mode == 0, iclass 14, count 2 2006.173.23:09:20.71#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.23:09:20.71#ibcon#[25=AT02-06\r\n] 2006.173.23:09:20.71#ibcon#*before write, iclass 14, count 2 2006.173.23:09:20.71#ibcon#enter sib2, iclass 14, count 2 2006.173.23:09:20.71#ibcon#flushed, iclass 14, count 2 2006.173.23:09:20.71#ibcon#about to write, iclass 14, count 2 2006.173.23:09:20.71#ibcon#wrote, iclass 14, count 2 2006.173.23:09:20.71#ibcon#about to read 3, iclass 14, count 2 2006.173.23:09:20.74#ibcon#read 3, iclass 14, count 2 2006.173.23:09:20.74#ibcon#about to read 4, iclass 14, count 2 2006.173.23:09:20.74#ibcon#read 4, iclass 14, count 2 2006.173.23:09:20.74#ibcon#about to read 5, iclass 14, count 2 2006.173.23:09:20.74#ibcon#read 5, iclass 14, count 2 2006.173.23:09:20.74#ibcon#about to read 6, iclass 14, count 2 2006.173.23:09:20.74#ibcon#read 6, iclass 14, count 2 2006.173.23:09:20.74#ibcon#end of sib2, iclass 14, count 2 2006.173.23:09:20.74#ibcon#*after write, iclass 14, count 2 2006.173.23:09:20.74#ibcon#*before return 0, iclass 14, count 2 2006.173.23:09:20.74#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.23:09:20.74#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.23:09:20.74#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.23:09:20.74#ibcon#ireg 7 cls_cnt 0 2006.173.23:09:20.74#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.23:09:20.86#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.23:09:20.86#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.23:09:20.86#ibcon#enter wrdev, iclass 14, count 0 2006.173.23:09:20.86#ibcon#first serial, iclass 14, count 0 2006.173.23:09:20.86#ibcon#enter sib2, iclass 14, count 0 2006.173.23:09:20.86#ibcon#flushed, iclass 14, count 0 2006.173.23:09:20.86#ibcon#about to write, iclass 14, count 0 2006.173.23:09:20.86#ibcon#wrote, iclass 14, count 0 2006.173.23:09:20.86#ibcon#about to read 3, iclass 14, count 0 2006.173.23:09:20.88#ibcon#read 3, iclass 14, count 0 2006.173.23:09:20.88#ibcon#about to read 4, iclass 14, count 0 2006.173.23:09:20.88#ibcon#read 4, iclass 14, count 0 2006.173.23:09:20.88#ibcon#about to read 5, iclass 14, count 0 2006.173.23:09:20.88#ibcon#read 5, iclass 14, count 0 2006.173.23:09:20.88#ibcon#about to read 6, iclass 14, count 0 2006.173.23:09:20.88#ibcon#read 6, iclass 14, count 0 2006.173.23:09:20.88#ibcon#end of sib2, iclass 14, count 0 2006.173.23:09:20.88#ibcon#*mode == 0, iclass 14, count 0 2006.173.23:09:20.88#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.23:09:20.88#ibcon#[25=USB\r\n] 2006.173.23:09:20.88#ibcon#*before write, iclass 14, count 0 2006.173.23:09:20.88#ibcon#enter sib2, iclass 14, count 0 2006.173.23:09:20.88#ibcon#flushed, iclass 14, count 0 2006.173.23:09:20.88#ibcon#about to write, iclass 14, count 0 2006.173.23:09:20.88#ibcon#wrote, iclass 14, count 0 2006.173.23:09:20.88#ibcon#about to read 3, iclass 14, count 0 2006.173.23:09:20.91#ibcon#read 3, iclass 14, count 0 2006.173.23:09:20.91#ibcon#about to read 4, iclass 14, count 0 2006.173.23:09:20.91#ibcon#read 4, iclass 14, count 0 2006.173.23:09:20.91#ibcon#about to read 5, iclass 14, count 0 2006.173.23:09:20.91#ibcon#read 5, iclass 14, count 0 2006.173.23:09:20.91#ibcon#about to read 6, iclass 14, count 0 2006.173.23:09:20.91#ibcon#read 6, iclass 14, count 0 2006.173.23:09:20.91#ibcon#end of sib2, iclass 14, count 0 2006.173.23:09:20.91#ibcon#*after write, iclass 14, count 0 2006.173.23:09:20.91#ibcon#*before return 0, iclass 14, count 0 2006.173.23:09:20.91#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.23:09:20.91#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.23:09:20.91#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.23:09:20.91#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.23:09:20.91$vck44/valo=3,564.99 2006.173.23:09:20.91#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.23:09:20.91#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.23:09:20.91#ibcon#ireg 17 cls_cnt 0 2006.173.23:09:20.91#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.23:09:20.91#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.23:09:20.91#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.23:09:20.91#ibcon#enter wrdev, iclass 16, count 0 2006.173.23:09:20.91#ibcon#first serial, iclass 16, count 0 2006.173.23:09:20.91#ibcon#enter sib2, iclass 16, count 0 2006.173.23:09:20.91#ibcon#flushed, iclass 16, count 0 2006.173.23:09:20.91#ibcon#about to write, iclass 16, count 0 2006.173.23:09:20.91#ibcon#wrote, iclass 16, count 0 2006.173.23:09:20.91#ibcon#about to read 3, iclass 16, count 0 2006.173.23:09:20.93#ibcon#read 3, iclass 16, count 0 2006.173.23:09:20.93#ibcon#about to read 4, iclass 16, count 0 2006.173.23:09:20.93#ibcon#read 4, iclass 16, count 0 2006.173.23:09:20.93#ibcon#about to read 5, iclass 16, count 0 2006.173.23:09:20.93#ibcon#read 5, iclass 16, count 0 2006.173.23:09:20.93#ibcon#about to read 6, iclass 16, count 0 2006.173.23:09:20.93#ibcon#read 6, iclass 16, count 0 2006.173.23:09:20.93#ibcon#end of sib2, iclass 16, count 0 2006.173.23:09:20.93#ibcon#*mode == 0, iclass 16, count 0 2006.173.23:09:20.93#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.23:09:20.93#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.23:09:20.93#ibcon#*before write, iclass 16, count 0 2006.173.23:09:20.93#ibcon#enter sib2, iclass 16, count 0 2006.173.23:09:20.93#ibcon#flushed, iclass 16, count 0 2006.173.23:09:20.93#ibcon#about to write, iclass 16, count 0 2006.173.23:09:20.93#ibcon#wrote, iclass 16, count 0 2006.173.23:09:20.93#ibcon#about to read 3, iclass 16, count 0 2006.173.23:09:20.97#ibcon#read 3, iclass 16, count 0 2006.173.23:09:20.97#ibcon#about to read 4, iclass 16, count 0 2006.173.23:09:20.97#ibcon#read 4, iclass 16, count 0 2006.173.23:09:20.97#ibcon#about to read 5, iclass 16, count 0 2006.173.23:09:20.97#ibcon#read 5, iclass 16, count 0 2006.173.23:09:20.97#ibcon#about to read 6, iclass 16, count 0 2006.173.23:09:20.97#ibcon#read 6, iclass 16, count 0 2006.173.23:09:20.97#ibcon#end of sib2, iclass 16, count 0 2006.173.23:09:20.97#ibcon#*after write, iclass 16, count 0 2006.173.23:09:20.97#ibcon#*before return 0, iclass 16, count 0 2006.173.23:09:20.97#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.23:09:20.97#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.23:09:20.97#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.23:09:20.97#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.23:09:20.97$vck44/va=3,5 2006.173.23:09:20.97#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.23:09:20.97#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.23:09:20.97#ibcon#ireg 11 cls_cnt 2 2006.173.23:09:20.97#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.23:09:21.03#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.23:09:21.03#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.23:09:21.03#ibcon#enter wrdev, iclass 18, count 2 2006.173.23:09:21.03#ibcon#first serial, iclass 18, count 2 2006.173.23:09:21.03#ibcon#enter sib2, iclass 18, count 2 2006.173.23:09:21.03#ibcon#flushed, iclass 18, count 2 2006.173.23:09:21.03#ibcon#about to write, iclass 18, count 2 2006.173.23:09:21.03#ibcon#wrote, iclass 18, count 2 2006.173.23:09:21.03#ibcon#about to read 3, iclass 18, count 2 2006.173.23:09:21.05#ibcon#read 3, iclass 18, count 2 2006.173.23:09:21.05#ibcon#about to read 4, iclass 18, count 2 2006.173.23:09:21.05#ibcon#read 4, iclass 18, count 2 2006.173.23:09:21.05#ibcon#about to read 5, iclass 18, count 2 2006.173.23:09:21.05#ibcon#read 5, iclass 18, count 2 2006.173.23:09:21.05#ibcon#about to read 6, iclass 18, count 2 2006.173.23:09:21.05#ibcon#read 6, iclass 18, count 2 2006.173.23:09:21.05#ibcon#end of sib2, iclass 18, count 2 2006.173.23:09:21.05#ibcon#*mode == 0, iclass 18, count 2 2006.173.23:09:21.05#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.23:09:21.05#ibcon#[25=AT03-05\r\n] 2006.173.23:09:21.05#ibcon#*before write, iclass 18, count 2 2006.173.23:09:21.05#ibcon#enter sib2, iclass 18, count 2 2006.173.23:09:21.05#ibcon#flushed, iclass 18, count 2 2006.173.23:09:21.05#ibcon#about to write, iclass 18, count 2 2006.173.23:09:21.05#ibcon#wrote, iclass 18, count 2 2006.173.23:09:21.05#ibcon#about to read 3, iclass 18, count 2 2006.173.23:09:21.08#ibcon#read 3, iclass 18, count 2 2006.173.23:09:21.08#ibcon#about to read 4, iclass 18, count 2 2006.173.23:09:21.08#ibcon#read 4, iclass 18, count 2 2006.173.23:09:21.08#ibcon#about to read 5, iclass 18, count 2 2006.173.23:09:21.08#ibcon#read 5, iclass 18, count 2 2006.173.23:09:21.08#ibcon#about to read 6, iclass 18, count 2 2006.173.23:09:21.08#ibcon#read 6, iclass 18, count 2 2006.173.23:09:21.08#ibcon#end of sib2, iclass 18, count 2 2006.173.23:09:21.08#ibcon#*after write, iclass 18, count 2 2006.173.23:09:21.08#ibcon#*before return 0, iclass 18, count 2 2006.173.23:09:21.08#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.23:09:21.08#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.23:09:21.08#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.23:09:21.08#ibcon#ireg 7 cls_cnt 0 2006.173.23:09:21.08#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.23:09:21.20#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.23:09:21.20#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.23:09:21.20#ibcon#enter wrdev, iclass 18, count 0 2006.173.23:09:21.20#ibcon#first serial, iclass 18, count 0 2006.173.23:09:21.20#ibcon#enter sib2, iclass 18, count 0 2006.173.23:09:21.20#ibcon#flushed, iclass 18, count 0 2006.173.23:09:21.20#ibcon#about to write, iclass 18, count 0 2006.173.23:09:21.20#ibcon#wrote, iclass 18, count 0 2006.173.23:09:21.20#ibcon#about to read 3, iclass 18, count 0 2006.173.23:09:21.22#ibcon#read 3, iclass 18, count 0 2006.173.23:09:21.22#ibcon#about to read 4, iclass 18, count 0 2006.173.23:09:21.22#ibcon#read 4, iclass 18, count 0 2006.173.23:09:21.22#ibcon#about to read 5, iclass 18, count 0 2006.173.23:09:21.22#ibcon#read 5, iclass 18, count 0 2006.173.23:09:21.22#ibcon#about to read 6, iclass 18, count 0 2006.173.23:09:21.22#ibcon#read 6, iclass 18, count 0 2006.173.23:09:21.22#ibcon#end of sib2, iclass 18, count 0 2006.173.23:09:21.22#ibcon#*mode == 0, iclass 18, count 0 2006.173.23:09:21.22#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.23:09:21.22#ibcon#[25=USB\r\n] 2006.173.23:09:21.22#ibcon#*before write, iclass 18, count 0 2006.173.23:09:21.22#ibcon#enter sib2, iclass 18, count 0 2006.173.23:09:21.22#ibcon#flushed, iclass 18, count 0 2006.173.23:09:21.22#ibcon#about to write, iclass 18, count 0 2006.173.23:09:21.22#ibcon#wrote, iclass 18, count 0 2006.173.23:09:21.22#ibcon#about to read 3, iclass 18, count 0 2006.173.23:09:21.25#ibcon#read 3, iclass 18, count 0 2006.173.23:09:21.25#ibcon#about to read 4, iclass 18, count 0 2006.173.23:09:21.25#ibcon#read 4, iclass 18, count 0 2006.173.23:09:21.25#ibcon#about to read 5, iclass 18, count 0 2006.173.23:09:21.25#ibcon#read 5, iclass 18, count 0 2006.173.23:09:21.25#ibcon#about to read 6, iclass 18, count 0 2006.173.23:09:21.25#ibcon#read 6, iclass 18, count 0 2006.173.23:09:21.25#ibcon#end of sib2, iclass 18, count 0 2006.173.23:09:21.25#ibcon#*after write, iclass 18, count 0 2006.173.23:09:21.25#ibcon#*before return 0, iclass 18, count 0 2006.173.23:09:21.25#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.23:09:21.25#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.23:09:21.25#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.23:09:21.25#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.23:09:21.25$vck44/valo=4,624.99 2006.173.23:09:21.25#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.23:09:21.25#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.23:09:21.25#ibcon#ireg 17 cls_cnt 0 2006.173.23:09:21.25#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.23:09:21.25#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.23:09:21.25#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.23:09:21.25#ibcon#enter wrdev, iclass 20, count 0 2006.173.23:09:21.25#ibcon#first serial, iclass 20, count 0 2006.173.23:09:21.25#ibcon#enter sib2, iclass 20, count 0 2006.173.23:09:21.25#ibcon#flushed, iclass 20, count 0 2006.173.23:09:21.25#ibcon#about to write, iclass 20, count 0 2006.173.23:09:21.25#ibcon#wrote, iclass 20, count 0 2006.173.23:09:21.25#ibcon#about to read 3, iclass 20, count 0 2006.173.23:09:21.27#ibcon#read 3, iclass 20, count 0 2006.173.23:09:21.27#ibcon#about to read 4, iclass 20, count 0 2006.173.23:09:21.27#ibcon#read 4, iclass 20, count 0 2006.173.23:09:21.27#ibcon#about to read 5, iclass 20, count 0 2006.173.23:09:21.27#ibcon#read 5, iclass 20, count 0 2006.173.23:09:21.27#ibcon#about to read 6, iclass 20, count 0 2006.173.23:09:21.27#ibcon#read 6, iclass 20, count 0 2006.173.23:09:21.27#ibcon#end of sib2, iclass 20, count 0 2006.173.23:09:21.27#ibcon#*mode == 0, iclass 20, count 0 2006.173.23:09:21.27#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.23:09:21.27#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.23:09:21.27#ibcon#*before write, iclass 20, count 0 2006.173.23:09:21.27#ibcon#enter sib2, iclass 20, count 0 2006.173.23:09:21.27#ibcon#flushed, iclass 20, count 0 2006.173.23:09:21.27#ibcon#about to write, iclass 20, count 0 2006.173.23:09:21.27#ibcon#wrote, iclass 20, count 0 2006.173.23:09:21.27#ibcon#about to read 3, iclass 20, count 0 2006.173.23:09:21.31#ibcon#read 3, iclass 20, count 0 2006.173.23:09:21.31#ibcon#about to read 4, iclass 20, count 0 2006.173.23:09:21.31#ibcon#read 4, iclass 20, count 0 2006.173.23:09:21.31#ibcon#about to read 5, iclass 20, count 0 2006.173.23:09:21.31#ibcon#read 5, iclass 20, count 0 2006.173.23:09:21.31#ibcon#about to read 6, iclass 20, count 0 2006.173.23:09:21.31#ibcon#read 6, iclass 20, count 0 2006.173.23:09:21.31#ibcon#end of sib2, iclass 20, count 0 2006.173.23:09:21.31#ibcon#*after write, iclass 20, count 0 2006.173.23:09:21.31#ibcon#*before return 0, iclass 20, count 0 2006.173.23:09:21.31#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.23:09:21.31#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.23:09:21.31#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.23:09:21.31#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.23:09:21.31$vck44/va=4,6 2006.173.23:09:21.31#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.23:09:21.31#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.23:09:21.31#ibcon#ireg 11 cls_cnt 2 2006.173.23:09:21.31#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.23:09:21.37#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.23:09:21.37#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.23:09:21.37#ibcon#enter wrdev, iclass 22, count 2 2006.173.23:09:21.37#ibcon#first serial, iclass 22, count 2 2006.173.23:09:21.37#ibcon#enter sib2, iclass 22, count 2 2006.173.23:09:21.37#ibcon#flushed, iclass 22, count 2 2006.173.23:09:21.37#ibcon#about to write, iclass 22, count 2 2006.173.23:09:21.37#ibcon#wrote, iclass 22, count 2 2006.173.23:09:21.37#ibcon#about to read 3, iclass 22, count 2 2006.173.23:09:21.39#ibcon#read 3, iclass 22, count 2 2006.173.23:09:21.39#ibcon#about to read 4, iclass 22, count 2 2006.173.23:09:21.39#ibcon#read 4, iclass 22, count 2 2006.173.23:09:21.39#ibcon#about to read 5, iclass 22, count 2 2006.173.23:09:21.39#ibcon#read 5, iclass 22, count 2 2006.173.23:09:21.39#ibcon#about to read 6, iclass 22, count 2 2006.173.23:09:21.39#ibcon#read 6, iclass 22, count 2 2006.173.23:09:21.39#ibcon#end of sib2, iclass 22, count 2 2006.173.23:09:21.39#ibcon#*mode == 0, iclass 22, count 2 2006.173.23:09:21.39#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.23:09:21.39#ibcon#[25=AT04-06\r\n] 2006.173.23:09:21.39#ibcon#*before write, iclass 22, count 2 2006.173.23:09:21.39#ibcon#enter sib2, iclass 22, count 2 2006.173.23:09:21.39#ibcon#flushed, iclass 22, count 2 2006.173.23:09:21.39#ibcon#about to write, iclass 22, count 2 2006.173.23:09:21.39#ibcon#wrote, iclass 22, count 2 2006.173.23:09:21.39#ibcon#about to read 3, iclass 22, count 2 2006.173.23:09:21.42#ibcon#read 3, iclass 22, count 2 2006.173.23:09:21.42#ibcon#about to read 4, iclass 22, count 2 2006.173.23:09:21.42#ibcon#read 4, iclass 22, count 2 2006.173.23:09:21.42#ibcon#about to read 5, iclass 22, count 2 2006.173.23:09:21.42#ibcon#read 5, iclass 22, count 2 2006.173.23:09:21.42#ibcon#about to read 6, iclass 22, count 2 2006.173.23:09:21.42#ibcon#read 6, iclass 22, count 2 2006.173.23:09:21.42#ibcon#end of sib2, iclass 22, count 2 2006.173.23:09:21.42#ibcon#*after write, iclass 22, count 2 2006.173.23:09:21.42#ibcon#*before return 0, iclass 22, count 2 2006.173.23:09:21.42#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.23:09:21.42#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.23:09:21.42#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.23:09:21.42#ibcon#ireg 7 cls_cnt 0 2006.173.23:09:21.42#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.23:09:21.54#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.23:09:21.54#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.23:09:21.54#ibcon#enter wrdev, iclass 22, count 0 2006.173.23:09:21.54#ibcon#first serial, iclass 22, count 0 2006.173.23:09:21.54#ibcon#enter sib2, iclass 22, count 0 2006.173.23:09:21.54#ibcon#flushed, iclass 22, count 0 2006.173.23:09:21.54#ibcon#about to write, iclass 22, count 0 2006.173.23:09:21.54#ibcon#wrote, iclass 22, count 0 2006.173.23:09:21.54#ibcon#about to read 3, iclass 22, count 0 2006.173.23:09:21.56#ibcon#read 3, iclass 22, count 0 2006.173.23:09:21.56#ibcon#about to read 4, iclass 22, count 0 2006.173.23:09:21.56#ibcon#read 4, iclass 22, count 0 2006.173.23:09:21.56#ibcon#about to read 5, iclass 22, count 0 2006.173.23:09:21.56#ibcon#read 5, iclass 22, count 0 2006.173.23:09:21.56#ibcon#about to read 6, iclass 22, count 0 2006.173.23:09:21.56#ibcon#read 6, iclass 22, count 0 2006.173.23:09:21.56#ibcon#end of sib2, iclass 22, count 0 2006.173.23:09:21.56#ibcon#*mode == 0, iclass 22, count 0 2006.173.23:09:21.56#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.23:09:21.56#ibcon#[25=USB\r\n] 2006.173.23:09:21.56#ibcon#*before write, iclass 22, count 0 2006.173.23:09:21.56#ibcon#enter sib2, iclass 22, count 0 2006.173.23:09:21.56#ibcon#flushed, iclass 22, count 0 2006.173.23:09:21.56#ibcon#about to write, iclass 22, count 0 2006.173.23:09:21.56#ibcon#wrote, iclass 22, count 0 2006.173.23:09:21.56#ibcon#about to read 3, iclass 22, count 0 2006.173.23:09:21.59#ibcon#read 3, iclass 22, count 0 2006.173.23:09:21.59#ibcon#about to read 4, iclass 22, count 0 2006.173.23:09:21.59#ibcon#read 4, iclass 22, count 0 2006.173.23:09:21.59#ibcon#about to read 5, iclass 22, count 0 2006.173.23:09:21.59#ibcon#read 5, iclass 22, count 0 2006.173.23:09:21.59#ibcon#about to read 6, iclass 22, count 0 2006.173.23:09:21.59#ibcon#read 6, iclass 22, count 0 2006.173.23:09:21.59#ibcon#end of sib2, iclass 22, count 0 2006.173.23:09:21.59#ibcon#*after write, iclass 22, count 0 2006.173.23:09:21.59#ibcon#*before return 0, iclass 22, count 0 2006.173.23:09:21.59#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.23:09:21.59#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.23:09:21.59#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.23:09:21.59#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.23:09:21.59$vck44/valo=5,734.99 2006.173.23:09:21.59#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.23:09:21.59#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.23:09:21.59#ibcon#ireg 17 cls_cnt 0 2006.173.23:09:21.59#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.23:09:21.59#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.23:09:21.59#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.23:09:21.59#ibcon#enter wrdev, iclass 24, count 0 2006.173.23:09:21.59#ibcon#first serial, iclass 24, count 0 2006.173.23:09:21.59#ibcon#enter sib2, iclass 24, count 0 2006.173.23:09:21.59#ibcon#flushed, iclass 24, count 0 2006.173.23:09:21.59#ibcon#about to write, iclass 24, count 0 2006.173.23:09:21.59#ibcon#wrote, iclass 24, count 0 2006.173.23:09:21.59#ibcon#about to read 3, iclass 24, count 0 2006.173.23:09:21.61#ibcon#read 3, iclass 24, count 0 2006.173.23:09:21.61#ibcon#about to read 4, iclass 24, count 0 2006.173.23:09:21.61#ibcon#read 4, iclass 24, count 0 2006.173.23:09:21.61#ibcon#about to read 5, iclass 24, count 0 2006.173.23:09:21.61#ibcon#read 5, iclass 24, count 0 2006.173.23:09:21.61#ibcon#about to read 6, iclass 24, count 0 2006.173.23:09:21.61#ibcon#read 6, iclass 24, count 0 2006.173.23:09:21.61#ibcon#end of sib2, iclass 24, count 0 2006.173.23:09:21.61#ibcon#*mode == 0, iclass 24, count 0 2006.173.23:09:21.61#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.23:09:21.61#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.23:09:21.61#ibcon#*before write, iclass 24, count 0 2006.173.23:09:21.61#ibcon#enter sib2, iclass 24, count 0 2006.173.23:09:21.61#ibcon#flushed, iclass 24, count 0 2006.173.23:09:21.61#ibcon#about to write, iclass 24, count 0 2006.173.23:09:21.61#ibcon#wrote, iclass 24, count 0 2006.173.23:09:21.61#ibcon#about to read 3, iclass 24, count 0 2006.173.23:09:21.65#ibcon#read 3, iclass 24, count 0 2006.173.23:09:21.65#ibcon#about to read 4, iclass 24, count 0 2006.173.23:09:21.65#ibcon#read 4, iclass 24, count 0 2006.173.23:09:21.65#ibcon#about to read 5, iclass 24, count 0 2006.173.23:09:21.65#ibcon#read 5, iclass 24, count 0 2006.173.23:09:21.65#ibcon#about to read 6, iclass 24, count 0 2006.173.23:09:21.65#ibcon#read 6, iclass 24, count 0 2006.173.23:09:21.65#ibcon#end of sib2, iclass 24, count 0 2006.173.23:09:21.65#ibcon#*after write, iclass 24, count 0 2006.173.23:09:21.65#ibcon#*before return 0, iclass 24, count 0 2006.173.23:09:21.65#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.23:09:21.65#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.23:09:21.65#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.23:09:21.65#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.23:09:21.65$vck44/va=5,4 2006.173.23:09:21.65#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.23:09:21.65#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.23:09:21.65#ibcon#ireg 11 cls_cnt 2 2006.173.23:09:21.65#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.23:09:21.71#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.23:09:21.71#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.23:09:21.71#ibcon#enter wrdev, iclass 26, count 2 2006.173.23:09:21.71#ibcon#first serial, iclass 26, count 2 2006.173.23:09:21.71#ibcon#enter sib2, iclass 26, count 2 2006.173.23:09:21.71#ibcon#flushed, iclass 26, count 2 2006.173.23:09:21.71#ibcon#about to write, iclass 26, count 2 2006.173.23:09:21.71#ibcon#wrote, iclass 26, count 2 2006.173.23:09:21.71#ibcon#about to read 3, iclass 26, count 2 2006.173.23:09:21.73#ibcon#read 3, iclass 26, count 2 2006.173.23:09:21.73#ibcon#about to read 4, iclass 26, count 2 2006.173.23:09:21.73#ibcon#read 4, iclass 26, count 2 2006.173.23:09:21.73#ibcon#about to read 5, iclass 26, count 2 2006.173.23:09:21.73#ibcon#read 5, iclass 26, count 2 2006.173.23:09:21.73#ibcon#about to read 6, iclass 26, count 2 2006.173.23:09:21.73#ibcon#read 6, iclass 26, count 2 2006.173.23:09:21.73#ibcon#end of sib2, iclass 26, count 2 2006.173.23:09:21.73#ibcon#*mode == 0, iclass 26, count 2 2006.173.23:09:21.73#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.23:09:21.73#ibcon#[25=AT05-04\r\n] 2006.173.23:09:21.73#ibcon#*before write, iclass 26, count 2 2006.173.23:09:21.73#ibcon#enter sib2, iclass 26, count 2 2006.173.23:09:21.73#ibcon#flushed, iclass 26, count 2 2006.173.23:09:21.73#ibcon#about to write, iclass 26, count 2 2006.173.23:09:21.73#ibcon#wrote, iclass 26, count 2 2006.173.23:09:21.73#ibcon#about to read 3, iclass 26, count 2 2006.173.23:09:21.76#ibcon#read 3, iclass 26, count 2 2006.173.23:09:21.76#ibcon#about to read 4, iclass 26, count 2 2006.173.23:09:21.76#ibcon#read 4, iclass 26, count 2 2006.173.23:09:21.76#ibcon#about to read 5, iclass 26, count 2 2006.173.23:09:21.76#ibcon#read 5, iclass 26, count 2 2006.173.23:09:21.76#ibcon#about to read 6, iclass 26, count 2 2006.173.23:09:21.76#ibcon#read 6, iclass 26, count 2 2006.173.23:09:21.76#ibcon#end of sib2, iclass 26, count 2 2006.173.23:09:21.76#ibcon#*after write, iclass 26, count 2 2006.173.23:09:21.76#ibcon#*before return 0, iclass 26, count 2 2006.173.23:09:21.76#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.23:09:21.76#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.23:09:21.76#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.23:09:21.76#ibcon#ireg 7 cls_cnt 0 2006.173.23:09:21.76#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.23:09:21.88#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.23:09:21.88#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.23:09:21.88#ibcon#enter wrdev, iclass 26, count 0 2006.173.23:09:21.88#ibcon#first serial, iclass 26, count 0 2006.173.23:09:21.88#ibcon#enter sib2, iclass 26, count 0 2006.173.23:09:21.88#ibcon#flushed, iclass 26, count 0 2006.173.23:09:21.88#ibcon#about to write, iclass 26, count 0 2006.173.23:09:21.88#ibcon#wrote, iclass 26, count 0 2006.173.23:09:21.88#ibcon#about to read 3, iclass 26, count 0 2006.173.23:09:21.90#ibcon#read 3, iclass 26, count 0 2006.173.23:09:21.90#ibcon#about to read 4, iclass 26, count 0 2006.173.23:09:21.90#ibcon#read 4, iclass 26, count 0 2006.173.23:09:21.90#ibcon#about to read 5, iclass 26, count 0 2006.173.23:09:21.90#ibcon#read 5, iclass 26, count 0 2006.173.23:09:21.90#ibcon#about to read 6, iclass 26, count 0 2006.173.23:09:21.90#ibcon#read 6, iclass 26, count 0 2006.173.23:09:21.90#ibcon#end of sib2, iclass 26, count 0 2006.173.23:09:21.90#ibcon#*mode == 0, iclass 26, count 0 2006.173.23:09:21.90#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.23:09:21.90#ibcon#[25=USB\r\n] 2006.173.23:09:21.90#ibcon#*before write, iclass 26, count 0 2006.173.23:09:21.90#ibcon#enter sib2, iclass 26, count 0 2006.173.23:09:21.90#ibcon#flushed, iclass 26, count 0 2006.173.23:09:21.90#ibcon#about to write, iclass 26, count 0 2006.173.23:09:21.90#ibcon#wrote, iclass 26, count 0 2006.173.23:09:21.90#ibcon#about to read 3, iclass 26, count 0 2006.173.23:09:21.93#ibcon#read 3, iclass 26, count 0 2006.173.23:09:21.93#ibcon#about to read 4, iclass 26, count 0 2006.173.23:09:21.93#ibcon#read 4, iclass 26, count 0 2006.173.23:09:21.93#ibcon#about to read 5, iclass 26, count 0 2006.173.23:09:21.93#ibcon#read 5, iclass 26, count 0 2006.173.23:09:21.93#ibcon#about to read 6, iclass 26, count 0 2006.173.23:09:21.93#ibcon#read 6, iclass 26, count 0 2006.173.23:09:21.93#ibcon#end of sib2, iclass 26, count 0 2006.173.23:09:21.93#ibcon#*after write, iclass 26, count 0 2006.173.23:09:21.93#ibcon#*before return 0, iclass 26, count 0 2006.173.23:09:21.93#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.23:09:21.93#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.23:09:21.93#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.23:09:21.93#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.23:09:21.93$vck44/valo=6,814.99 2006.173.23:09:21.93#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.23:09:21.93#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.23:09:21.93#ibcon#ireg 17 cls_cnt 0 2006.173.23:09:21.93#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.23:09:21.93#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.23:09:21.93#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.23:09:21.93#ibcon#enter wrdev, iclass 28, count 0 2006.173.23:09:21.93#ibcon#first serial, iclass 28, count 0 2006.173.23:09:21.93#ibcon#enter sib2, iclass 28, count 0 2006.173.23:09:21.93#ibcon#flushed, iclass 28, count 0 2006.173.23:09:21.93#ibcon#about to write, iclass 28, count 0 2006.173.23:09:21.93#ibcon#wrote, iclass 28, count 0 2006.173.23:09:21.93#ibcon#about to read 3, iclass 28, count 0 2006.173.23:09:21.95#ibcon#read 3, iclass 28, count 0 2006.173.23:09:21.95#ibcon#about to read 4, iclass 28, count 0 2006.173.23:09:21.95#ibcon#read 4, iclass 28, count 0 2006.173.23:09:21.95#ibcon#about to read 5, iclass 28, count 0 2006.173.23:09:21.95#ibcon#read 5, iclass 28, count 0 2006.173.23:09:21.95#ibcon#about to read 6, iclass 28, count 0 2006.173.23:09:21.95#ibcon#read 6, iclass 28, count 0 2006.173.23:09:21.95#ibcon#end of sib2, iclass 28, count 0 2006.173.23:09:21.95#ibcon#*mode == 0, iclass 28, count 0 2006.173.23:09:21.95#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.23:09:21.95#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.23:09:21.95#ibcon#*before write, iclass 28, count 0 2006.173.23:09:21.95#ibcon#enter sib2, iclass 28, count 0 2006.173.23:09:21.95#ibcon#flushed, iclass 28, count 0 2006.173.23:09:21.95#ibcon#about to write, iclass 28, count 0 2006.173.23:09:21.95#ibcon#wrote, iclass 28, count 0 2006.173.23:09:21.95#ibcon#about to read 3, iclass 28, count 0 2006.173.23:09:21.99#ibcon#read 3, iclass 28, count 0 2006.173.23:09:21.99#ibcon#about to read 4, iclass 28, count 0 2006.173.23:09:21.99#ibcon#read 4, iclass 28, count 0 2006.173.23:09:21.99#ibcon#about to read 5, iclass 28, count 0 2006.173.23:09:21.99#ibcon#read 5, iclass 28, count 0 2006.173.23:09:21.99#ibcon#about to read 6, iclass 28, count 0 2006.173.23:09:21.99#ibcon#read 6, iclass 28, count 0 2006.173.23:09:21.99#ibcon#end of sib2, iclass 28, count 0 2006.173.23:09:21.99#ibcon#*after write, iclass 28, count 0 2006.173.23:09:21.99#ibcon#*before return 0, iclass 28, count 0 2006.173.23:09:21.99#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.23:09:21.99#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.23:09:21.99#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.23:09:21.99#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.23:09:21.99$vck44/va=6,3 2006.173.23:09:21.99#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.23:09:21.99#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.23:09:21.99#ibcon#ireg 11 cls_cnt 2 2006.173.23:09:21.99#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.23:09:22.05#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.23:09:22.05#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.23:09:22.05#ibcon#enter wrdev, iclass 30, count 2 2006.173.23:09:22.05#ibcon#first serial, iclass 30, count 2 2006.173.23:09:22.05#ibcon#enter sib2, iclass 30, count 2 2006.173.23:09:22.05#ibcon#flushed, iclass 30, count 2 2006.173.23:09:22.05#ibcon#about to write, iclass 30, count 2 2006.173.23:09:22.05#ibcon#wrote, iclass 30, count 2 2006.173.23:09:22.05#ibcon#about to read 3, iclass 30, count 2 2006.173.23:09:22.07#ibcon#read 3, iclass 30, count 2 2006.173.23:09:22.07#ibcon#about to read 4, iclass 30, count 2 2006.173.23:09:22.07#ibcon#read 4, iclass 30, count 2 2006.173.23:09:22.07#ibcon#about to read 5, iclass 30, count 2 2006.173.23:09:22.07#ibcon#read 5, iclass 30, count 2 2006.173.23:09:22.07#ibcon#about to read 6, iclass 30, count 2 2006.173.23:09:22.07#ibcon#read 6, iclass 30, count 2 2006.173.23:09:22.07#ibcon#end of sib2, iclass 30, count 2 2006.173.23:09:22.07#ibcon#*mode == 0, iclass 30, count 2 2006.173.23:09:22.07#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.23:09:22.07#ibcon#[25=AT06-03\r\n] 2006.173.23:09:22.07#ibcon#*before write, iclass 30, count 2 2006.173.23:09:22.07#ibcon#enter sib2, iclass 30, count 2 2006.173.23:09:22.07#ibcon#flushed, iclass 30, count 2 2006.173.23:09:22.07#ibcon#about to write, iclass 30, count 2 2006.173.23:09:22.07#ibcon#wrote, iclass 30, count 2 2006.173.23:09:22.07#ibcon#about to read 3, iclass 30, count 2 2006.173.23:09:22.10#ibcon#read 3, iclass 30, count 2 2006.173.23:09:22.10#ibcon#about to read 4, iclass 30, count 2 2006.173.23:09:22.10#ibcon#read 4, iclass 30, count 2 2006.173.23:09:22.10#ibcon#about to read 5, iclass 30, count 2 2006.173.23:09:22.10#ibcon#read 5, iclass 30, count 2 2006.173.23:09:22.10#ibcon#about to read 6, iclass 30, count 2 2006.173.23:09:22.10#ibcon#read 6, iclass 30, count 2 2006.173.23:09:22.10#ibcon#end of sib2, iclass 30, count 2 2006.173.23:09:22.10#ibcon#*after write, iclass 30, count 2 2006.173.23:09:22.10#ibcon#*before return 0, iclass 30, count 2 2006.173.23:09:22.10#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.23:09:22.10#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.23:09:22.10#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.23:09:22.10#ibcon#ireg 7 cls_cnt 0 2006.173.23:09:22.10#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.23:09:22.22#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.23:09:22.22#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.23:09:22.22#ibcon#enter wrdev, iclass 30, count 0 2006.173.23:09:22.22#ibcon#first serial, iclass 30, count 0 2006.173.23:09:22.22#ibcon#enter sib2, iclass 30, count 0 2006.173.23:09:22.22#ibcon#flushed, iclass 30, count 0 2006.173.23:09:22.22#ibcon#about to write, iclass 30, count 0 2006.173.23:09:22.22#ibcon#wrote, iclass 30, count 0 2006.173.23:09:22.22#ibcon#about to read 3, iclass 30, count 0 2006.173.23:09:22.24#ibcon#read 3, iclass 30, count 0 2006.173.23:09:22.24#ibcon#about to read 4, iclass 30, count 0 2006.173.23:09:22.24#ibcon#read 4, iclass 30, count 0 2006.173.23:09:22.24#ibcon#about to read 5, iclass 30, count 0 2006.173.23:09:22.24#ibcon#read 5, iclass 30, count 0 2006.173.23:09:22.24#ibcon#about to read 6, iclass 30, count 0 2006.173.23:09:22.24#ibcon#read 6, iclass 30, count 0 2006.173.23:09:22.24#ibcon#end of sib2, iclass 30, count 0 2006.173.23:09:22.24#ibcon#*mode == 0, iclass 30, count 0 2006.173.23:09:22.24#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.23:09:22.24#ibcon#[25=USB\r\n] 2006.173.23:09:22.24#ibcon#*before write, iclass 30, count 0 2006.173.23:09:22.24#ibcon#enter sib2, iclass 30, count 0 2006.173.23:09:22.24#ibcon#flushed, iclass 30, count 0 2006.173.23:09:22.24#ibcon#about to write, iclass 30, count 0 2006.173.23:09:22.24#ibcon#wrote, iclass 30, count 0 2006.173.23:09:22.24#ibcon#about to read 3, iclass 30, count 0 2006.173.23:09:22.27#ibcon#read 3, iclass 30, count 0 2006.173.23:09:22.27#ibcon#about to read 4, iclass 30, count 0 2006.173.23:09:22.27#ibcon#read 4, iclass 30, count 0 2006.173.23:09:22.27#ibcon#about to read 5, iclass 30, count 0 2006.173.23:09:22.27#ibcon#read 5, iclass 30, count 0 2006.173.23:09:22.27#ibcon#about to read 6, iclass 30, count 0 2006.173.23:09:22.27#ibcon#read 6, iclass 30, count 0 2006.173.23:09:22.27#ibcon#end of sib2, iclass 30, count 0 2006.173.23:09:22.27#ibcon#*after write, iclass 30, count 0 2006.173.23:09:22.27#ibcon#*before return 0, iclass 30, count 0 2006.173.23:09:22.27#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.23:09:22.27#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.23:09:22.27#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.23:09:22.27#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.23:09:22.27$vck44/valo=7,864.99 2006.173.23:09:22.27#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.23:09:22.27#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.23:09:22.27#ibcon#ireg 17 cls_cnt 0 2006.173.23:09:22.27#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.23:09:22.27#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.23:09:22.27#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.23:09:22.27#ibcon#enter wrdev, iclass 32, count 0 2006.173.23:09:22.27#ibcon#first serial, iclass 32, count 0 2006.173.23:09:22.27#ibcon#enter sib2, iclass 32, count 0 2006.173.23:09:22.27#ibcon#flushed, iclass 32, count 0 2006.173.23:09:22.27#ibcon#about to write, iclass 32, count 0 2006.173.23:09:22.27#ibcon#wrote, iclass 32, count 0 2006.173.23:09:22.27#ibcon#about to read 3, iclass 32, count 0 2006.173.23:09:22.29#ibcon#read 3, iclass 32, count 0 2006.173.23:09:22.29#ibcon#about to read 4, iclass 32, count 0 2006.173.23:09:22.29#ibcon#read 4, iclass 32, count 0 2006.173.23:09:22.29#ibcon#about to read 5, iclass 32, count 0 2006.173.23:09:22.29#ibcon#read 5, iclass 32, count 0 2006.173.23:09:22.29#ibcon#about to read 6, iclass 32, count 0 2006.173.23:09:22.29#ibcon#read 6, iclass 32, count 0 2006.173.23:09:22.29#ibcon#end of sib2, iclass 32, count 0 2006.173.23:09:22.29#ibcon#*mode == 0, iclass 32, count 0 2006.173.23:09:22.29#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.23:09:22.29#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.23:09:22.29#ibcon#*before write, iclass 32, count 0 2006.173.23:09:22.29#ibcon#enter sib2, iclass 32, count 0 2006.173.23:09:22.29#ibcon#flushed, iclass 32, count 0 2006.173.23:09:22.29#ibcon#about to write, iclass 32, count 0 2006.173.23:09:22.29#ibcon#wrote, iclass 32, count 0 2006.173.23:09:22.29#ibcon#about to read 3, iclass 32, count 0 2006.173.23:09:22.33#ibcon#read 3, iclass 32, count 0 2006.173.23:09:22.33#ibcon#about to read 4, iclass 32, count 0 2006.173.23:09:22.33#ibcon#read 4, iclass 32, count 0 2006.173.23:09:22.33#ibcon#about to read 5, iclass 32, count 0 2006.173.23:09:22.33#ibcon#read 5, iclass 32, count 0 2006.173.23:09:22.33#ibcon#about to read 6, iclass 32, count 0 2006.173.23:09:22.33#ibcon#read 6, iclass 32, count 0 2006.173.23:09:22.33#ibcon#end of sib2, iclass 32, count 0 2006.173.23:09:22.33#ibcon#*after write, iclass 32, count 0 2006.173.23:09:22.33#ibcon#*before return 0, iclass 32, count 0 2006.173.23:09:22.33#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.23:09:22.33#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.23:09:22.33#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.23:09:22.33#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.23:09:22.33$vck44/va=7,4 2006.173.23:09:22.33#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.23:09:22.33#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.23:09:22.33#ibcon#ireg 11 cls_cnt 2 2006.173.23:09:22.33#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.23:09:22.39#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.23:09:22.39#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.23:09:22.39#ibcon#enter wrdev, iclass 34, count 2 2006.173.23:09:22.39#ibcon#first serial, iclass 34, count 2 2006.173.23:09:22.39#ibcon#enter sib2, iclass 34, count 2 2006.173.23:09:22.39#ibcon#flushed, iclass 34, count 2 2006.173.23:09:22.39#ibcon#about to write, iclass 34, count 2 2006.173.23:09:22.39#ibcon#wrote, iclass 34, count 2 2006.173.23:09:22.39#ibcon#about to read 3, iclass 34, count 2 2006.173.23:09:22.41#ibcon#read 3, iclass 34, count 2 2006.173.23:09:22.41#ibcon#about to read 4, iclass 34, count 2 2006.173.23:09:22.41#ibcon#read 4, iclass 34, count 2 2006.173.23:09:22.41#ibcon#about to read 5, iclass 34, count 2 2006.173.23:09:22.41#ibcon#read 5, iclass 34, count 2 2006.173.23:09:22.41#ibcon#about to read 6, iclass 34, count 2 2006.173.23:09:22.41#ibcon#read 6, iclass 34, count 2 2006.173.23:09:22.41#ibcon#end of sib2, iclass 34, count 2 2006.173.23:09:22.41#ibcon#*mode == 0, iclass 34, count 2 2006.173.23:09:22.41#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.23:09:22.41#ibcon#[25=AT07-04\r\n] 2006.173.23:09:22.41#ibcon#*before write, iclass 34, count 2 2006.173.23:09:22.41#ibcon#enter sib2, iclass 34, count 2 2006.173.23:09:22.41#ibcon#flushed, iclass 34, count 2 2006.173.23:09:22.41#ibcon#about to write, iclass 34, count 2 2006.173.23:09:22.41#ibcon#wrote, iclass 34, count 2 2006.173.23:09:22.41#ibcon#about to read 3, iclass 34, count 2 2006.173.23:09:22.44#ibcon#read 3, iclass 34, count 2 2006.173.23:09:22.44#ibcon#about to read 4, iclass 34, count 2 2006.173.23:09:22.44#ibcon#read 4, iclass 34, count 2 2006.173.23:09:22.44#ibcon#about to read 5, iclass 34, count 2 2006.173.23:09:22.44#ibcon#read 5, iclass 34, count 2 2006.173.23:09:22.44#ibcon#about to read 6, iclass 34, count 2 2006.173.23:09:22.44#ibcon#read 6, iclass 34, count 2 2006.173.23:09:22.44#ibcon#end of sib2, iclass 34, count 2 2006.173.23:09:22.44#ibcon#*after write, iclass 34, count 2 2006.173.23:09:22.44#ibcon#*before return 0, iclass 34, count 2 2006.173.23:09:22.44#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.23:09:22.44#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.23:09:22.44#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.23:09:22.44#ibcon#ireg 7 cls_cnt 0 2006.173.23:09:22.44#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.23:09:22.56#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.23:09:22.56#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.23:09:22.56#ibcon#enter wrdev, iclass 34, count 0 2006.173.23:09:22.56#ibcon#first serial, iclass 34, count 0 2006.173.23:09:22.56#ibcon#enter sib2, iclass 34, count 0 2006.173.23:09:22.56#ibcon#flushed, iclass 34, count 0 2006.173.23:09:22.56#ibcon#about to write, iclass 34, count 0 2006.173.23:09:22.56#ibcon#wrote, iclass 34, count 0 2006.173.23:09:22.56#ibcon#about to read 3, iclass 34, count 0 2006.173.23:09:22.58#ibcon#read 3, iclass 34, count 0 2006.173.23:09:22.58#ibcon#about to read 4, iclass 34, count 0 2006.173.23:09:22.58#ibcon#read 4, iclass 34, count 0 2006.173.23:09:22.58#ibcon#about to read 5, iclass 34, count 0 2006.173.23:09:22.58#ibcon#read 5, iclass 34, count 0 2006.173.23:09:22.58#ibcon#about to read 6, iclass 34, count 0 2006.173.23:09:22.58#ibcon#read 6, iclass 34, count 0 2006.173.23:09:22.58#ibcon#end of sib2, iclass 34, count 0 2006.173.23:09:22.58#ibcon#*mode == 0, iclass 34, count 0 2006.173.23:09:22.58#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.23:09:22.58#ibcon#[25=USB\r\n] 2006.173.23:09:22.58#ibcon#*before write, iclass 34, count 0 2006.173.23:09:22.58#ibcon#enter sib2, iclass 34, count 0 2006.173.23:09:22.58#ibcon#flushed, iclass 34, count 0 2006.173.23:09:22.58#ibcon#about to write, iclass 34, count 0 2006.173.23:09:22.58#ibcon#wrote, iclass 34, count 0 2006.173.23:09:22.58#ibcon#about to read 3, iclass 34, count 0 2006.173.23:09:22.61#ibcon#read 3, iclass 34, count 0 2006.173.23:09:22.61#ibcon#about to read 4, iclass 34, count 0 2006.173.23:09:22.61#ibcon#read 4, iclass 34, count 0 2006.173.23:09:22.61#ibcon#about to read 5, iclass 34, count 0 2006.173.23:09:22.61#ibcon#read 5, iclass 34, count 0 2006.173.23:09:22.61#ibcon#about to read 6, iclass 34, count 0 2006.173.23:09:22.61#ibcon#read 6, iclass 34, count 0 2006.173.23:09:22.61#ibcon#end of sib2, iclass 34, count 0 2006.173.23:09:22.61#ibcon#*after write, iclass 34, count 0 2006.173.23:09:22.61#ibcon#*before return 0, iclass 34, count 0 2006.173.23:09:22.61#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.23:09:22.61#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.23:09:22.61#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.23:09:22.61#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.23:09:22.61$vck44/valo=8,884.99 2006.173.23:09:22.61#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.23:09:22.61#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.23:09:22.61#ibcon#ireg 17 cls_cnt 0 2006.173.23:09:22.61#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.23:09:22.61#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.23:09:22.61#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.23:09:22.61#ibcon#enter wrdev, iclass 36, count 0 2006.173.23:09:22.61#ibcon#first serial, iclass 36, count 0 2006.173.23:09:22.61#ibcon#enter sib2, iclass 36, count 0 2006.173.23:09:22.61#ibcon#flushed, iclass 36, count 0 2006.173.23:09:22.61#ibcon#about to write, iclass 36, count 0 2006.173.23:09:22.61#ibcon#wrote, iclass 36, count 0 2006.173.23:09:22.61#ibcon#about to read 3, iclass 36, count 0 2006.173.23:09:22.63#ibcon#read 3, iclass 36, count 0 2006.173.23:09:22.63#ibcon#about to read 4, iclass 36, count 0 2006.173.23:09:22.63#ibcon#read 4, iclass 36, count 0 2006.173.23:09:22.63#ibcon#about to read 5, iclass 36, count 0 2006.173.23:09:22.63#ibcon#read 5, iclass 36, count 0 2006.173.23:09:22.63#ibcon#about to read 6, iclass 36, count 0 2006.173.23:09:22.63#ibcon#read 6, iclass 36, count 0 2006.173.23:09:22.63#ibcon#end of sib2, iclass 36, count 0 2006.173.23:09:22.63#ibcon#*mode == 0, iclass 36, count 0 2006.173.23:09:22.63#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.23:09:22.63#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.23:09:22.63#ibcon#*before write, iclass 36, count 0 2006.173.23:09:22.63#ibcon#enter sib2, iclass 36, count 0 2006.173.23:09:22.63#ibcon#flushed, iclass 36, count 0 2006.173.23:09:22.63#ibcon#about to write, iclass 36, count 0 2006.173.23:09:22.63#ibcon#wrote, iclass 36, count 0 2006.173.23:09:22.63#ibcon#about to read 3, iclass 36, count 0 2006.173.23:09:22.67#ibcon#read 3, iclass 36, count 0 2006.173.23:09:22.67#ibcon#about to read 4, iclass 36, count 0 2006.173.23:09:22.67#ibcon#read 4, iclass 36, count 0 2006.173.23:09:22.67#ibcon#about to read 5, iclass 36, count 0 2006.173.23:09:22.67#ibcon#read 5, iclass 36, count 0 2006.173.23:09:22.67#ibcon#about to read 6, iclass 36, count 0 2006.173.23:09:22.67#ibcon#read 6, iclass 36, count 0 2006.173.23:09:22.67#ibcon#end of sib2, iclass 36, count 0 2006.173.23:09:22.67#ibcon#*after write, iclass 36, count 0 2006.173.23:09:22.67#ibcon#*before return 0, iclass 36, count 0 2006.173.23:09:22.67#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.23:09:22.67#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.23:09:22.67#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.23:09:22.67#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.23:09:22.67$vck44/va=8,4 2006.173.23:09:22.67#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.23:09:22.67#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.23:09:22.67#ibcon#ireg 11 cls_cnt 2 2006.173.23:09:22.67#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.23:09:22.73#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.23:09:22.73#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.23:09:22.73#ibcon#enter wrdev, iclass 38, count 2 2006.173.23:09:22.73#ibcon#first serial, iclass 38, count 2 2006.173.23:09:22.73#ibcon#enter sib2, iclass 38, count 2 2006.173.23:09:22.73#ibcon#flushed, iclass 38, count 2 2006.173.23:09:22.73#ibcon#about to write, iclass 38, count 2 2006.173.23:09:22.73#ibcon#wrote, iclass 38, count 2 2006.173.23:09:22.73#ibcon#about to read 3, iclass 38, count 2 2006.173.23:09:22.75#ibcon#read 3, iclass 38, count 2 2006.173.23:09:22.75#ibcon#about to read 4, iclass 38, count 2 2006.173.23:09:22.75#ibcon#read 4, iclass 38, count 2 2006.173.23:09:22.75#ibcon#about to read 5, iclass 38, count 2 2006.173.23:09:22.75#ibcon#read 5, iclass 38, count 2 2006.173.23:09:22.75#ibcon#about to read 6, iclass 38, count 2 2006.173.23:09:22.75#ibcon#read 6, iclass 38, count 2 2006.173.23:09:22.75#ibcon#end of sib2, iclass 38, count 2 2006.173.23:09:22.75#ibcon#*mode == 0, iclass 38, count 2 2006.173.23:09:22.75#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.23:09:22.75#ibcon#[25=AT08-04\r\n] 2006.173.23:09:22.75#ibcon#*before write, iclass 38, count 2 2006.173.23:09:22.75#ibcon#enter sib2, iclass 38, count 2 2006.173.23:09:22.75#ibcon#flushed, iclass 38, count 2 2006.173.23:09:22.75#ibcon#about to write, iclass 38, count 2 2006.173.23:09:22.75#ibcon#wrote, iclass 38, count 2 2006.173.23:09:22.75#ibcon#about to read 3, iclass 38, count 2 2006.173.23:09:22.78#ibcon#read 3, iclass 38, count 2 2006.173.23:09:22.78#ibcon#about to read 4, iclass 38, count 2 2006.173.23:09:22.78#ibcon#read 4, iclass 38, count 2 2006.173.23:09:22.78#ibcon#about to read 5, iclass 38, count 2 2006.173.23:09:22.78#ibcon#read 5, iclass 38, count 2 2006.173.23:09:22.78#ibcon#about to read 6, iclass 38, count 2 2006.173.23:09:22.78#ibcon#read 6, iclass 38, count 2 2006.173.23:09:22.78#ibcon#end of sib2, iclass 38, count 2 2006.173.23:09:22.78#ibcon#*after write, iclass 38, count 2 2006.173.23:09:22.78#ibcon#*before return 0, iclass 38, count 2 2006.173.23:09:22.78#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.23:09:22.78#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.23:09:22.78#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.23:09:22.78#ibcon#ireg 7 cls_cnt 0 2006.173.23:09:22.78#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.23:09:22.90#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.23:09:22.90#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.23:09:22.90#ibcon#enter wrdev, iclass 38, count 0 2006.173.23:09:22.90#ibcon#first serial, iclass 38, count 0 2006.173.23:09:22.90#ibcon#enter sib2, iclass 38, count 0 2006.173.23:09:22.90#ibcon#flushed, iclass 38, count 0 2006.173.23:09:22.90#ibcon#about to write, iclass 38, count 0 2006.173.23:09:22.90#ibcon#wrote, iclass 38, count 0 2006.173.23:09:22.90#ibcon#about to read 3, iclass 38, count 0 2006.173.23:09:22.92#ibcon#read 3, iclass 38, count 0 2006.173.23:09:22.92#ibcon#about to read 4, iclass 38, count 0 2006.173.23:09:22.92#ibcon#read 4, iclass 38, count 0 2006.173.23:09:22.92#ibcon#about to read 5, iclass 38, count 0 2006.173.23:09:22.92#ibcon#read 5, iclass 38, count 0 2006.173.23:09:22.92#ibcon#about to read 6, iclass 38, count 0 2006.173.23:09:22.92#ibcon#read 6, iclass 38, count 0 2006.173.23:09:22.92#ibcon#end of sib2, iclass 38, count 0 2006.173.23:09:22.92#ibcon#*mode == 0, iclass 38, count 0 2006.173.23:09:22.92#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.23:09:22.92#ibcon#[25=USB\r\n] 2006.173.23:09:22.92#ibcon#*before write, iclass 38, count 0 2006.173.23:09:22.92#ibcon#enter sib2, iclass 38, count 0 2006.173.23:09:22.92#ibcon#flushed, iclass 38, count 0 2006.173.23:09:22.92#ibcon#about to write, iclass 38, count 0 2006.173.23:09:22.92#ibcon#wrote, iclass 38, count 0 2006.173.23:09:22.92#ibcon#about to read 3, iclass 38, count 0 2006.173.23:09:22.95#ibcon#read 3, iclass 38, count 0 2006.173.23:09:22.95#ibcon#about to read 4, iclass 38, count 0 2006.173.23:09:22.95#ibcon#read 4, iclass 38, count 0 2006.173.23:09:22.95#ibcon#about to read 5, iclass 38, count 0 2006.173.23:09:22.95#ibcon#read 5, iclass 38, count 0 2006.173.23:09:22.95#ibcon#about to read 6, iclass 38, count 0 2006.173.23:09:22.95#ibcon#read 6, iclass 38, count 0 2006.173.23:09:22.95#ibcon#end of sib2, iclass 38, count 0 2006.173.23:09:22.95#ibcon#*after write, iclass 38, count 0 2006.173.23:09:22.95#ibcon#*before return 0, iclass 38, count 0 2006.173.23:09:22.95#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.23:09:22.95#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.23:09:22.95#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.23:09:22.95#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.23:09:22.95$vck44/vblo=1,629.99 2006.173.23:09:22.95#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.23:09:22.95#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.23:09:22.95#ibcon#ireg 17 cls_cnt 0 2006.173.23:09:22.95#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.23:09:22.95#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.23:09:22.95#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.23:09:22.95#ibcon#enter wrdev, iclass 40, count 0 2006.173.23:09:22.95#ibcon#first serial, iclass 40, count 0 2006.173.23:09:22.95#ibcon#enter sib2, iclass 40, count 0 2006.173.23:09:22.95#ibcon#flushed, iclass 40, count 0 2006.173.23:09:22.95#ibcon#about to write, iclass 40, count 0 2006.173.23:09:22.95#ibcon#wrote, iclass 40, count 0 2006.173.23:09:22.95#ibcon#about to read 3, iclass 40, count 0 2006.173.23:09:22.97#ibcon#read 3, iclass 40, count 0 2006.173.23:09:22.97#ibcon#about to read 4, iclass 40, count 0 2006.173.23:09:22.97#ibcon#read 4, iclass 40, count 0 2006.173.23:09:22.97#ibcon#about to read 5, iclass 40, count 0 2006.173.23:09:22.97#ibcon#read 5, iclass 40, count 0 2006.173.23:09:22.97#ibcon#about to read 6, iclass 40, count 0 2006.173.23:09:22.97#ibcon#read 6, iclass 40, count 0 2006.173.23:09:22.97#ibcon#end of sib2, iclass 40, count 0 2006.173.23:09:22.97#ibcon#*mode == 0, iclass 40, count 0 2006.173.23:09:22.97#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.23:09:22.97#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.23:09:22.97#ibcon#*before write, iclass 40, count 0 2006.173.23:09:22.97#ibcon#enter sib2, iclass 40, count 0 2006.173.23:09:22.97#ibcon#flushed, iclass 40, count 0 2006.173.23:09:22.97#ibcon#about to write, iclass 40, count 0 2006.173.23:09:22.97#ibcon#wrote, iclass 40, count 0 2006.173.23:09:22.97#ibcon#about to read 3, iclass 40, count 0 2006.173.23:09:23.01#ibcon#read 3, iclass 40, count 0 2006.173.23:09:23.01#ibcon#about to read 4, iclass 40, count 0 2006.173.23:09:23.01#ibcon#read 4, iclass 40, count 0 2006.173.23:09:23.01#ibcon#about to read 5, iclass 40, count 0 2006.173.23:09:23.01#ibcon#read 5, iclass 40, count 0 2006.173.23:09:23.01#ibcon#about to read 6, iclass 40, count 0 2006.173.23:09:23.01#ibcon#read 6, iclass 40, count 0 2006.173.23:09:23.01#ibcon#end of sib2, iclass 40, count 0 2006.173.23:09:23.01#ibcon#*after write, iclass 40, count 0 2006.173.23:09:23.01#ibcon#*before return 0, iclass 40, count 0 2006.173.23:09:23.01#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.23:09:23.01#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.23:09:23.01#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.23:09:23.01#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.23:09:23.01$vck44/vb=1,4 2006.173.23:09:23.01#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.23:09:23.01#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.23:09:23.01#ibcon#ireg 11 cls_cnt 2 2006.173.23:09:23.01#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.23:09:23.01#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.23:09:23.01#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.23:09:23.01#ibcon#enter wrdev, iclass 4, count 2 2006.173.23:09:23.01#ibcon#first serial, iclass 4, count 2 2006.173.23:09:23.01#ibcon#enter sib2, iclass 4, count 2 2006.173.23:09:23.01#ibcon#flushed, iclass 4, count 2 2006.173.23:09:23.01#ibcon#about to write, iclass 4, count 2 2006.173.23:09:23.01#ibcon#wrote, iclass 4, count 2 2006.173.23:09:23.01#ibcon#about to read 3, iclass 4, count 2 2006.173.23:09:23.03#ibcon#read 3, iclass 4, count 2 2006.173.23:09:23.03#ibcon#about to read 4, iclass 4, count 2 2006.173.23:09:23.03#ibcon#read 4, iclass 4, count 2 2006.173.23:09:23.03#ibcon#about to read 5, iclass 4, count 2 2006.173.23:09:23.03#ibcon#read 5, iclass 4, count 2 2006.173.23:09:23.03#ibcon#about to read 6, iclass 4, count 2 2006.173.23:09:23.03#ibcon#read 6, iclass 4, count 2 2006.173.23:09:23.03#ibcon#end of sib2, iclass 4, count 2 2006.173.23:09:23.03#ibcon#*mode == 0, iclass 4, count 2 2006.173.23:09:23.03#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.23:09:23.03#ibcon#[27=AT01-04\r\n] 2006.173.23:09:23.03#ibcon#*before write, iclass 4, count 2 2006.173.23:09:23.03#ibcon#enter sib2, iclass 4, count 2 2006.173.23:09:23.03#ibcon#flushed, iclass 4, count 2 2006.173.23:09:23.03#ibcon#about to write, iclass 4, count 2 2006.173.23:09:23.03#ibcon#wrote, iclass 4, count 2 2006.173.23:09:23.03#ibcon#about to read 3, iclass 4, count 2 2006.173.23:09:23.06#ibcon#read 3, iclass 4, count 2 2006.173.23:09:23.06#ibcon#about to read 4, iclass 4, count 2 2006.173.23:09:23.06#ibcon#read 4, iclass 4, count 2 2006.173.23:09:23.06#ibcon#about to read 5, iclass 4, count 2 2006.173.23:09:23.06#ibcon#read 5, iclass 4, count 2 2006.173.23:09:23.06#ibcon#about to read 6, iclass 4, count 2 2006.173.23:09:23.06#ibcon#read 6, iclass 4, count 2 2006.173.23:09:23.06#ibcon#end of sib2, iclass 4, count 2 2006.173.23:09:23.06#ibcon#*after write, iclass 4, count 2 2006.173.23:09:23.06#ibcon#*before return 0, iclass 4, count 2 2006.173.23:09:23.06#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.23:09:23.06#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.23:09:23.06#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.23:09:23.06#ibcon#ireg 7 cls_cnt 0 2006.173.23:09:23.06#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.23:09:23.18#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.23:09:23.18#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.23:09:23.18#ibcon#enter wrdev, iclass 4, count 0 2006.173.23:09:23.18#ibcon#first serial, iclass 4, count 0 2006.173.23:09:23.18#ibcon#enter sib2, iclass 4, count 0 2006.173.23:09:23.18#ibcon#flushed, iclass 4, count 0 2006.173.23:09:23.18#ibcon#about to write, iclass 4, count 0 2006.173.23:09:23.18#ibcon#wrote, iclass 4, count 0 2006.173.23:09:23.18#ibcon#about to read 3, iclass 4, count 0 2006.173.23:09:23.20#ibcon#read 3, iclass 4, count 0 2006.173.23:09:23.20#ibcon#about to read 4, iclass 4, count 0 2006.173.23:09:23.20#ibcon#read 4, iclass 4, count 0 2006.173.23:09:23.20#ibcon#about to read 5, iclass 4, count 0 2006.173.23:09:23.20#ibcon#read 5, iclass 4, count 0 2006.173.23:09:23.20#ibcon#about to read 6, iclass 4, count 0 2006.173.23:09:23.20#ibcon#read 6, iclass 4, count 0 2006.173.23:09:23.20#ibcon#end of sib2, iclass 4, count 0 2006.173.23:09:23.20#ibcon#*mode == 0, iclass 4, count 0 2006.173.23:09:23.20#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.23:09:23.20#ibcon#[27=USB\r\n] 2006.173.23:09:23.20#ibcon#*before write, iclass 4, count 0 2006.173.23:09:23.20#ibcon#enter sib2, iclass 4, count 0 2006.173.23:09:23.20#ibcon#flushed, iclass 4, count 0 2006.173.23:09:23.20#ibcon#about to write, iclass 4, count 0 2006.173.23:09:23.20#ibcon#wrote, iclass 4, count 0 2006.173.23:09:23.20#ibcon#about to read 3, iclass 4, count 0 2006.173.23:09:23.23#ibcon#read 3, iclass 4, count 0 2006.173.23:09:23.23#ibcon#about to read 4, iclass 4, count 0 2006.173.23:09:23.23#ibcon#read 4, iclass 4, count 0 2006.173.23:09:23.23#ibcon#about to read 5, iclass 4, count 0 2006.173.23:09:23.23#ibcon#read 5, iclass 4, count 0 2006.173.23:09:23.23#ibcon#about to read 6, iclass 4, count 0 2006.173.23:09:23.23#ibcon#read 6, iclass 4, count 0 2006.173.23:09:23.23#ibcon#end of sib2, iclass 4, count 0 2006.173.23:09:23.23#ibcon#*after write, iclass 4, count 0 2006.173.23:09:23.23#ibcon#*before return 0, iclass 4, count 0 2006.173.23:09:23.23#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.23:09:23.23#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.23:09:23.23#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.23:09:23.23#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.23:09:23.23$vck44/vblo=2,634.99 2006.173.23:09:23.23#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.23:09:23.23#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.23:09:23.23#ibcon#ireg 17 cls_cnt 0 2006.173.23:09:23.23#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.23:09:23.23#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.23:09:23.23#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.23:09:23.23#ibcon#enter wrdev, iclass 6, count 0 2006.173.23:09:23.23#ibcon#first serial, iclass 6, count 0 2006.173.23:09:23.23#ibcon#enter sib2, iclass 6, count 0 2006.173.23:09:23.23#ibcon#flushed, iclass 6, count 0 2006.173.23:09:23.23#ibcon#about to write, iclass 6, count 0 2006.173.23:09:23.23#ibcon#wrote, iclass 6, count 0 2006.173.23:09:23.23#ibcon#about to read 3, iclass 6, count 0 2006.173.23:09:23.25#ibcon#read 3, iclass 6, count 0 2006.173.23:09:23.25#ibcon#about to read 4, iclass 6, count 0 2006.173.23:09:23.25#ibcon#read 4, iclass 6, count 0 2006.173.23:09:23.25#ibcon#about to read 5, iclass 6, count 0 2006.173.23:09:23.25#ibcon#read 5, iclass 6, count 0 2006.173.23:09:23.25#ibcon#about to read 6, iclass 6, count 0 2006.173.23:09:23.25#ibcon#read 6, iclass 6, count 0 2006.173.23:09:23.25#ibcon#end of sib2, iclass 6, count 0 2006.173.23:09:23.25#ibcon#*mode == 0, iclass 6, count 0 2006.173.23:09:23.25#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.23:09:23.25#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.23:09:23.25#ibcon#*before write, iclass 6, count 0 2006.173.23:09:23.25#ibcon#enter sib2, iclass 6, count 0 2006.173.23:09:23.25#ibcon#flushed, iclass 6, count 0 2006.173.23:09:23.25#ibcon#about to write, iclass 6, count 0 2006.173.23:09:23.25#ibcon#wrote, iclass 6, count 0 2006.173.23:09:23.25#ibcon#about to read 3, iclass 6, count 0 2006.173.23:09:23.29#ibcon#read 3, iclass 6, count 0 2006.173.23:09:23.29#ibcon#about to read 4, iclass 6, count 0 2006.173.23:09:23.29#ibcon#read 4, iclass 6, count 0 2006.173.23:09:23.29#ibcon#about to read 5, iclass 6, count 0 2006.173.23:09:23.29#ibcon#read 5, iclass 6, count 0 2006.173.23:09:23.29#ibcon#about to read 6, iclass 6, count 0 2006.173.23:09:23.29#ibcon#read 6, iclass 6, count 0 2006.173.23:09:23.29#ibcon#end of sib2, iclass 6, count 0 2006.173.23:09:23.29#ibcon#*after write, iclass 6, count 0 2006.173.23:09:23.29#ibcon#*before return 0, iclass 6, count 0 2006.173.23:09:23.29#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.23:09:23.29#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.23:09:23.29#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.23:09:23.29#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.23:09:23.29$vck44/vb=2,4 2006.173.23:09:23.29#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.23:09:23.29#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.23:09:23.29#ibcon#ireg 11 cls_cnt 2 2006.173.23:09:23.29#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.23:09:23.35#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.23:09:23.35#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.23:09:23.35#ibcon#enter wrdev, iclass 10, count 2 2006.173.23:09:23.35#ibcon#first serial, iclass 10, count 2 2006.173.23:09:23.35#ibcon#enter sib2, iclass 10, count 2 2006.173.23:09:23.35#ibcon#flushed, iclass 10, count 2 2006.173.23:09:23.35#ibcon#about to write, iclass 10, count 2 2006.173.23:09:23.35#ibcon#wrote, iclass 10, count 2 2006.173.23:09:23.35#ibcon#about to read 3, iclass 10, count 2 2006.173.23:09:23.37#ibcon#read 3, iclass 10, count 2 2006.173.23:09:23.37#ibcon#about to read 4, iclass 10, count 2 2006.173.23:09:23.37#ibcon#read 4, iclass 10, count 2 2006.173.23:09:23.37#ibcon#about to read 5, iclass 10, count 2 2006.173.23:09:23.37#ibcon#read 5, iclass 10, count 2 2006.173.23:09:23.37#ibcon#about to read 6, iclass 10, count 2 2006.173.23:09:23.37#ibcon#read 6, iclass 10, count 2 2006.173.23:09:23.37#ibcon#end of sib2, iclass 10, count 2 2006.173.23:09:23.37#ibcon#*mode == 0, iclass 10, count 2 2006.173.23:09:23.37#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.23:09:23.37#ibcon#[27=AT02-04\r\n] 2006.173.23:09:23.37#ibcon#*before write, iclass 10, count 2 2006.173.23:09:23.37#ibcon#enter sib2, iclass 10, count 2 2006.173.23:09:23.37#ibcon#flushed, iclass 10, count 2 2006.173.23:09:23.37#ibcon#about to write, iclass 10, count 2 2006.173.23:09:23.37#ibcon#wrote, iclass 10, count 2 2006.173.23:09:23.37#ibcon#about to read 3, iclass 10, count 2 2006.173.23:09:23.40#ibcon#read 3, iclass 10, count 2 2006.173.23:09:23.40#ibcon#about to read 4, iclass 10, count 2 2006.173.23:09:23.40#ibcon#read 4, iclass 10, count 2 2006.173.23:09:23.40#ibcon#about to read 5, iclass 10, count 2 2006.173.23:09:23.40#ibcon#read 5, iclass 10, count 2 2006.173.23:09:23.40#ibcon#about to read 6, iclass 10, count 2 2006.173.23:09:23.40#ibcon#read 6, iclass 10, count 2 2006.173.23:09:23.40#ibcon#end of sib2, iclass 10, count 2 2006.173.23:09:23.40#ibcon#*after write, iclass 10, count 2 2006.173.23:09:23.40#ibcon#*before return 0, iclass 10, count 2 2006.173.23:09:23.40#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.23:09:23.40#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.23:09:23.40#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.23:09:23.40#ibcon#ireg 7 cls_cnt 0 2006.173.23:09:23.40#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.23:09:23.52#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.23:09:23.52#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.23:09:23.52#ibcon#enter wrdev, iclass 10, count 0 2006.173.23:09:23.52#ibcon#first serial, iclass 10, count 0 2006.173.23:09:23.52#ibcon#enter sib2, iclass 10, count 0 2006.173.23:09:23.52#ibcon#flushed, iclass 10, count 0 2006.173.23:09:23.52#ibcon#about to write, iclass 10, count 0 2006.173.23:09:23.52#ibcon#wrote, iclass 10, count 0 2006.173.23:09:23.52#ibcon#about to read 3, iclass 10, count 0 2006.173.23:09:23.54#ibcon#read 3, iclass 10, count 0 2006.173.23:09:23.54#ibcon#about to read 4, iclass 10, count 0 2006.173.23:09:23.54#ibcon#read 4, iclass 10, count 0 2006.173.23:09:23.54#ibcon#about to read 5, iclass 10, count 0 2006.173.23:09:23.54#ibcon#read 5, iclass 10, count 0 2006.173.23:09:23.54#ibcon#about to read 6, iclass 10, count 0 2006.173.23:09:23.54#ibcon#read 6, iclass 10, count 0 2006.173.23:09:23.54#ibcon#end of sib2, iclass 10, count 0 2006.173.23:09:23.54#ibcon#*mode == 0, iclass 10, count 0 2006.173.23:09:23.54#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.23:09:23.54#ibcon#[27=USB\r\n] 2006.173.23:09:23.54#ibcon#*before write, iclass 10, count 0 2006.173.23:09:23.54#ibcon#enter sib2, iclass 10, count 0 2006.173.23:09:23.54#ibcon#flushed, iclass 10, count 0 2006.173.23:09:23.54#ibcon#about to write, iclass 10, count 0 2006.173.23:09:23.54#ibcon#wrote, iclass 10, count 0 2006.173.23:09:23.54#ibcon#about to read 3, iclass 10, count 0 2006.173.23:09:23.57#ibcon#read 3, iclass 10, count 0 2006.173.23:09:23.57#ibcon#about to read 4, iclass 10, count 0 2006.173.23:09:23.57#ibcon#read 4, iclass 10, count 0 2006.173.23:09:23.57#ibcon#about to read 5, iclass 10, count 0 2006.173.23:09:23.57#ibcon#read 5, iclass 10, count 0 2006.173.23:09:23.57#ibcon#about to read 6, iclass 10, count 0 2006.173.23:09:23.57#ibcon#read 6, iclass 10, count 0 2006.173.23:09:23.57#ibcon#end of sib2, iclass 10, count 0 2006.173.23:09:23.57#ibcon#*after write, iclass 10, count 0 2006.173.23:09:23.57#ibcon#*before return 0, iclass 10, count 0 2006.173.23:09:23.57#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.23:09:23.57#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.23:09:23.57#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.23:09:23.57#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.23:09:23.57$vck44/vblo=3,649.99 2006.173.23:09:23.57#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.23:09:23.57#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.23:09:23.57#ibcon#ireg 17 cls_cnt 0 2006.173.23:09:23.57#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.23:09:23.57#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.23:09:23.57#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.23:09:23.57#ibcon#enter wrdev, iclass 12, count 0 2006.173.23:09:23.57#ibcon#first serial, iclass 12, count 0 2006.173.23:09:23.57#ibcon#enter sib2, iclass 12, count 0 2006.173.23:09:23.57#ibcon#flushed, iclass 12, count 0 2006.173.23:09:23.57#ibcon#about to write, iclass 12, count 0 2006.173.23:09:23.57#ibcon#wrote, iclass 12, count 0 2006.173.23:09:23.57#ibcon#about to read 3, iclass 12, count 0 2006.173.23:09:23.59#ibcon#read 3, iclass 12, count 0 2006.173.23:09:23.59#ibcon#about to read 4, iclass 12, count 0 2006.173.23:09:23.59#ibcon#read 4, iclass 12, count 0 2006.173.23:09:23.59#ibcon#about to read 5, iclass 12, count 0 2006.173.23:09:23.59#ibcon#read 5, iclass 12, count 0 2006.173.23:09:23.59#ibcon#about to read 6, iclass 12, count 0 2006.173.23:09:23.59#ibcon#read 6, iclass 12, count 0 2006.173.23:09:23.59#ibcon#end of sib2, iclass 12, count 0 2006.173.23:09:23.59#ibcon#*mode == 0, iclass 12, count 0 2006.173.23:09:23.59#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.23:09:23.59#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.23:09:23.59#ibcon#*before write, iclass 12, count 0 2006.173.23:09:23.59#ibcon#enter sib2, iclass 12, count 0 2006.173.23:09:23.59#ibcon#flushed, iclass 12, count 0 2006.173.23:09:23.59#ibcon#about to write, iclass 12, count 0 2006.173.23:09:23.59#ibcon#wrote, iclass 12, count 0 2006.173.23:09:23.59#ibcon#about to read 3, iclass 12, count 0 2006.173.23:09:23.63#ibcon#read 3, iclass 12, count 0 2006.173.23:09:23.63#ibcon#about to read 4, iclass 12, count 0 2006.173.23:09:23.63#ibcon#read 4, iclass 12, count 0 2006.173.23:09:23.63#ibcon#about to read 5, iclass 12, count 0 2006.173.23:09:23.63#ibcon#read 5, iclass 12, count 0 2006.173.23:09:23.63#ibcon#about to read 6, iclass 12, count 0 2006.173.23:09:23.63#ibcon#read 6, iclass 12, count 0 2006.173.23:09:23.63#ibcon#end of sib2, iclass 12, count 0 2006.173.23:09:23.63#ibcon#*after write, iclass 12, count 0 2006.173.23:09:23.63#ibcon#*before return 0, iclass 12, count 0 2006.173.23:09:23.63#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.23:09:23.63#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.23:09:23.63#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.23:09:23.63#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.23:09:23.63$vck44/vb=3,4 2006.173.23:09:23.63#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.23:09:23.63#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.23:09:23.63#ibcon#ireg 11 cls_cnt 2 2006.173.23:09:23.63#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.23:09:23.69#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.23:09:23.69#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.23:09:23.69#ibcon#enter wrdev, iclass 14, count 2 2006.173.23:09:23.69#ibcon#first serial, iclass 14, count 2 2006.173.23:09:23.69#ibcon#enter sib2, iclass 14, count 2 2006.173.23:09:23.69#ibcon#flushed, iclass 14, count 2 2006.173.23:09:23.69#ibcon#about to write, iclass 14, count 2 2006.173.23:09:23.69#ibcon#wrote, iclass 14, count 2 2006.173.23:09:23.69#ibcon#about to read 3, iclass 14, count 2 2006.173.23:09:23.71#ibcon#read 3, iclass 14, count 2 2006.173.23:09:23.71#ibcon#about to read 4, iclass 14, count 2 2006.173.23:09:23.71#ibcon#read 4, iclass 14, count 2 2006.173.23:09:23.71#ibcon#about to read 5, iclass 14, count 2 2006.173.23:09:23.71#ibcon#read 5, iclass 14, count 2 2006.173.23:09:23.71#ibcon#about to read 6, iclass 14, count 2 2006.173.23:09:23.71#ibcon#read 6, iclass 14, count 2 2006.173.23:09:23.71#ibcon#end of sib2, iclass 14, count 2 2006.173.23:09:23.71#ibcon#*mode == 0, iclass 14, count 2 2006.173.23:09:23.71#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.23:09:23.71#ibcon#[27=AT03-04\r\n] 2006.173.23:09:23.71#ibcon#*before write, iclass 14, count 2 2006.173.23:09:23.71#ibcon#enter sib2, iclass 14, count 2 2006.173.23:09:23.71#ibcon#flushed, iclass 14, count 2 2006.173.23:09:23.71#ibcon#about to write, iclass 14, count 2 2006.173.23:09:23.71#ibcon#wrote, iclass 14, count 2 2006.173.23:09:23.71#ibcon#about to read 3, iclass 14, count 2 2006.173.23:09:23.74#ibcon#read 3, iclass 14, count 2 2006.173.23:09:23.74#ibcon#about to read 4, iclass 14, count 2 2006.173.23:09:23.74#ibcon#read 4, iclass 14, count 2 2006.173.23:09:23.74#ibcon#about to read 5, iclass 14, count 2 2006.173.23:09:23.74#ibcon#read 5, iclass 14, count 2 2006.173.23:09:23.74#ibcon#about to read 6, iclass 14, count 2 2006.173.23:09:23.74#ibcon#read 6, iclass 14, count 2 2006.173.23:09:23.74#ibcon#end of sib2, iclass 14, count 2 2006.173.23:09:23.74#ibcon#*after write, iclass 14, count 2 2006.173.23:09:23.74#ibcon#*before return 0, iclass 14, count 2 2006.173.23:09:23.74#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.23:09:23.74#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.23:09:23.74#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.23:09:23.74#ibcon#ireg 7 cls_cnt 0 2006.173.23:09:23.74#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.23:09:23.86#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.23:09:23.86#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.23:09:23.86#ibcon#enter wrdev, iclass 14, count 0 2006.173.23:09:23.86#ibcon#first serial, iclass 14, count 0 2006.173.23:09:23.86#ibcon#enter sib2, iclass 14, count 0 2006.173.23:09:23.86#ibcon#flushed, iclass 14, count 0 2006.173.23:09:23.86#ibcon#about to write, iclass 14, count 0 2006.173.23:09:23.86#ibcon#wrote, iclass 14, count 0 2006.173.23:09:23.86#ibcon#about to read 3, iclass 14, count 0 2006.173.23:09:23.88#ibcon#read 3, iclass 14, count 0 2006.173.23:09:23.88#ibcon#about to read 4, iclass 14, count 0 2006.173.23:09:23.88#ibcon#read 4, iclass 14, count 0 2006.173.23:09:23.88#ibcon#about to read 5, iclass 14, count 0 2006.173.23:09:23.88#ibcon#read 5, iclass 14, count 0 2006.173.23:09:23.88#ibcon#about to read 6, iclass 14, count 0 2006.173.23:09:23.88#ibcon#read 6, iclass 14, count 0 2006.173.23:09:23.88#ibcon#end of sib2, iclass 14, count 0 2006.173.23:09:23.88#ibcon#*mode == 0, iclass 14, count 0 2006.173.23:09:23.88#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.23:09:23.88#ibcon#[27=USB\r\n] 2006.173.23:09:23.88#ibcon#*before write, iclass 14, count 0 2006.173.23:09:23.88#ibcon#enter sib2, iclass 14, count 0 2006.173.23:09:23.88#ibcon#flushed, iclass 14, count 0 2006.173.23:09:23.88#ibcon#about to write, iclass 14, count 0 2006.173.23:09:23.88#ibcon#wrote, iclass 14, count 0 2006.173.23:09:23.88#ibcon#about to read 3, iclass 14, count 0 2006.173.23:09:23.91#ibcon#read 3, iclass 14, count 0 2006.173.23:09:23.91#ibcon#about to read 4, iclass 14, count 0 2006.173.23:09:23.91#ibcon#read 4, iclass 14, count 0 2006.173.23:09:23.91#ibcon#about to read 5, iclass 14, count 0 2006.173.23:09:23.91#ibcon#read 5, iclass 14, count 0 2006.173.23:09:23.91#ibcon#about to read 6, iclass 14, count 0 2006.173.23:09:23.91#ibcon#read 6, iclass 14, count 0 2006.173.23:09:23.91#ibcon#end of sib2, iclass 14, count 0 2006.173.23:09:23.91#ibcon#*after write, iclass 14, count 0 2006.173.23:09:23.91#ibcon#*before return 0, iclass 14, count 0 2006.173.23:09:23.91#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.23:09:23.91#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.23:09:23.91#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.23:09:23.91#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.23:09:23.91$vck44/vblo=4,679.99 2006.173.23:09:23.91#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.23:09:23.91#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.23:09:23.91#ibcon#ireg 17 cls_cnt 0 2006.173.23:09:23.91#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.23:09:23.91#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.23:09:23.91#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.23:09:23.91#ibcon#enter wrdev, iclass 16, count 0 2006.173.23:09:23.91#ibcon#first serial, iclass 16, count 0 2006.173.23:09:23.91#ibcon#enter sib2, iclass 16, count 0 2006.173.23:09:23.91#ibcon#flushed, iclass 16, count 0 2006.173.23:09:23.91#ibcon#about to write, iclass 16, count 0 2006.173.23:09:23.91#ibcon#wrote, iclass 16, count 0 2006.173.23:09:23.91#ibcon#about to read 3, iclass 16, count 0 2006.173.23:09:23.93#ibcon#read 3, iclass 16, count 0 2006.173.23:09:23.93#ibcon#about to read 4, iclass 16, count 0 2006.173.23:09:23.93#ibcon#read 4, iclass 16, count 0 2006.173.23:09:23.93#ibcon#about to read 5, iclass 16, count 0 2006.173.23:09:23.93#ibcon#read 5, iclass 16, count 0 2006.173.23:09:23.93#ibcon#about to read 6, iclass 16, count 0 2006.173.23:09:23.93#ibcon#read 6, iclass 16, count 0 2006.173.23:09:23.93#ibcon#end of sib2, iclass 16, count 0 2006.173.23:09:23.93#ibcon#*mode == 0, iclass 16, count 0 2006.173.23:09:23.93#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.23:09:23.93#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.23:09:23.93#ibcon#*before write, iclass 16, count 0 2006.173.23:09:23.93#ibcon#enter sib2, iclass 16, count 0 2006.173.23:09:23.93#ibcon#flushed, iclass 16, count 0 2006.173.23:09:23.93#ibcon#about to write, iclass 16, count 0 2006.173.23:09:23.93#ibcon#wrote, iclass 16, count 0 2006.173.23:09:23.93#ibcon#about to read 3, iclass 16, count 0 2006.173.23:09:23.97#ibcon#read 3, iclass 16, count 0 2006.173.23:09:23.97#ibcon#about to read 4, iclass 16, count 0 2006.173.23:09:23.97#ibcon#read 4, iclass 16, count 0 2006.173.23:09:23.97#ibcon#about to read 5, iclass 16, count 0 2006.173.23:09:23.97#ibcon#read 5, iclass 16, count 0 2006.173.23:09:23.97#ibcon#about to read 6, iclass 16, count 0 2006.173.23:09:23.97#ibcon#read 6, iclass 16, count 0 2006.173.23:09:23.97#ibcon#end of sib2, iclass 16, count 0 2006.173.23:09:23.97#ibcon#*after write, iclass 16, count 0 2006.173.23:09:23.97#ibcon#*before return 0, iclass 16, count 0 2006.173.23:09:23.97#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.23:09:23.97#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.23:09:23.97#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.23:09:23.97#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.23:09:23.97$vck44/vb=4,4 2006.173.23:09:23.97#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.23:09:23.97#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.23:09:23.97#ibcon#ireg 11 cls_cnt 2 2006.173.23:09:23.97#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.23:09:24.03#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.23:09:24.03#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.23:09:24.03#ibcon#enter wrdev, iclass 18, count 2 2006.173.23:09:24.03#ibcon#first serial, iclass 18, count 2 2006.173.23:09:24.03#ibcon#enter sib2, iclass 18, count 2 2006.173.23:09:24.03#ibcon#flushed, iclass 18, count 2 2006.173.23:09:24.03#ibcon#about to write, iclass 18, count 2 2006.173.23:09:24.03#ibcon#wrote, iclass 18, count 2 2006.173.23:09:24.03#ibcon#about to read 3, iclass 18, count 2 2006.173.23:09:24.05#ibcon#read 3, iclass 18, count 2 2006.173.23:09:24.05#ibcon#about to read 4, iclass 18, count 2 2006.173.23:09:24.05#ibcon#read 4, iclass 18, count 2 2006.173.23:09:24.05#ibcon#about to read 5, iclass 18, count 2 2006.173.23:09:24.05#ibcon#read 5, iclass 18, count 2 2006.173.23:09:24.05#ibcon#about to read 6, iclass 18, count 2 2006.173.23:09:24.05#ibcon#read 6, iclass 18, count 2 2006.173.23:09:24.05#ibcon#end of sib2, iclass 18, count 2 2006.173.23:09:24.05#ibcon#*mode == 0, iclass 18, count 2 2006.173.23:09:24.05#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.23:09:24.05#ibcon#[27=AT04-04\r\n] 2006.173.23:09:24.05#ibcon#*before write, iclass 18, count 2 2006.173.23:09:24.05#ibcon#enter sib2, iclass 18, count 2 2006.173.23:09:24.05#ibcon#flushed, iclass 18, count 2 2006.173.23:09:24.05#ibcon#about to write, iclass 18, count 2 2006.173.23:09:24.05#ibcon#wrote, iclass 18, count 2 2006.173.23:09:24.05#ibcon#about to read 3, iclass 18, count 2 2006.173.23:09:24.08#ibcon#read 3, iclass 18, count 2 2006.173.23:09:24.08#ibcon#about to read 4, iclass 18, count 2 2006.173.23:09:24.08#ibcon#read 4, iclass 18, count 2 2006.173.23:09:24.08#ibcon#about to read 5, iclass 18, count 2 2006.173.23:09:24.08#ibcon#read 5, iclass 18, count 2 2006.173.23:09:24.08#ibcon#about to read 6, iclass 18, count 2 2006.173.23:09:24.08#ibcon#read 6, iclass 18, count 2 2006.173.23:09:24.08#ibcon#end of sib2, iclass 18, count 2 2006.173.23:09:24.08#ibcon#*after write, iclass 18, count 2 2006.173.23:09:24.08#ibcon#*before return 0, iclass 18, count 2 2006.173.23:09:24.08#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.23:09:24.08#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.23:09:24.08#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.23:09:24.08#ibcon#ireg 7 cls_cnt 0 2006.173.23:09:24.08#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.23:09:24.20#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.23:09:24.20#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.23:09:24.20#ibcon#enter wrdev, iclass 18, count 0 2006.173.23:09:24.20#ibcon#first serial, iclass 18, count 0 2006.173.23:09:24.20#ibcon#enter sib2, iclass 18, count 0 2006.173.23:09:24.20#ibcon#flushed, iclass 18, count 0 2006.173.23:09:24.20#ibcon#about to write, iclass 18, count 0 2006.173.23:09:24.20#ibcon#wrote, iclass 18, count 0 2006.173.23:09:24.20#ibcon#about to read 3, iclass 18, count 0 2006.173.23:09:24.22#ibcon#read 3, iclass 18, count 0 2006.173.23:09:24.22#ibcon#about to read 4, iclass 18, count 0 2006.173.23:09:24.22#ibcon#read 4, iclass 18, count 0 2006.173.23:09:24.22#ibcon#about to read 5, iclass 18, count 0 2006.173.23:09:24.22#ibcon#read 5, iclass 18, count 0 2006.173.23:09:24.22#ibcon#about to read 6, iclass 18, count 0 2006.173.23:09:24.22#ibcon#read 6, iclass 18, count 0 2006.173.23:09:24.22#ibcon#end of sib2, iclass 18, count 0 2006.173.23:09:24.22#ibcon#*mode == 0, iclass 18, count 0 2006.173.23:09:24.22#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.23:09:24.22#ibcon#[27=USB\r\n] 2006.173.23:09:24.22#ibcon#*before write, iclass 18, count 0 2006.173.23:09:24.22#ibcon#enter sib2, iclass 18, count 0 2006.173.23:09:24.22#ibcon#flushed, iclass 18, count 0 2006.173.23:09:24.22#ibcon#about to write, iclass 18, count 0 2006.173.23:09:24.22#ibcon#wrote, iclass 18, count 0 2006.173.23:09:24.22#ibcon#about to read 3, iclass 18, count 0 2006.173.23:09:24.25#ibcon#read 3, iclass 18, count 0 2006.173.23:09:24.25#ibcon#about to read 4, iclass 18, count 0 2006.173.23:09:24.25#ibcon#read 4, iclass 18, count 0 2006.173.23:09:24.25#ibcon#about to read 5, iclass 18, count 0 2006.173.23:09:24.25#ibcon#read 5, iclass 18, count 0 2006.173.23:09:24.25#ibcon#about to read 6, iclass 18, count 0 2006.173.23:09:24.25#ibcon#read 6, iclass 18, count 0 2006.173.23:09:24.25#ibcon#end of sib2, iclass 18, count 0 2006.173.23:09:24.25#ibcon#*after write, iclass 18, count 0 2006.173.23:09:24.25#ibcon#*before return 0, iclass 18, count 0 2006.173.23:09:24.25#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.23:09:24.25#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.23:09:24.25#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.23:09:24.25#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.23:09:24.25$vck44/vblo=5,709.99 2006.173.23:09:24.25#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.23:09:24.25#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.23:09:24.25#ibcon#ireg 17 cls_cnt 0 2006.173.23:09:24.25#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.23:09:24.25#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.23:09:24.25#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.23:09:24.25#ibcon#enter wrdev, iclass 20, count 0 2006.173.23:09:24.25#ibcon#first serial, iclass 20, count 0 2006.173.23:09:24.25#ibcon#enter sib2, iclass 20, count 0 2006.173.23:09:24.25#ibcon#flushed, iclass 20, count 0 2006.173.23:09:24.25#ibcon#about to write, iclass 20, count 0 2006.173.23:09:24.25#ibcon#wrote, iclass 20, count 0 2006.173.23:09:24.25#ibcon#about to read 3, iclass 20, count 0 2006.173.23:09:24.27#ibcon#read 3, iclass 20, count 0 2006.173.23:09:24.27#ibcon#about to read 4, iclass 20, count 0 2006.173.23:09:24.27#ibcon#read 4, iclass 20, count 0 2006.173.23:09:24.27#ibcon#about to read 5, iclass 20, count 0 2006.173.23:09:24.27#ibcon#read 5, iclass 20, count 0 2006.173.23:09:24.27#ibcon#about to read 6, iclass 20, count 0 2006.173.23:09:24.27#ibcon#read 6, iclass 20, count 0 2006.173.23:09:24.27#ibcon#end of sib2, iclass 20, count 0 2006.173.23:09:24.27#ibcon#*mode == 0, iclass 20, count 0 2006.173.23:09:24.27#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.23:09:24.27#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.23:09:24.27#ibcon#*before write, iclass 20, count 0 2006.173.23:09:24.27#ibcon#enter sib2, iclass 20, count 0 2006.173.23:09:24.27#ibcon#flushed, iclass 20, count 0 2006.173.23:09:24.27#ibcon#about to write, iclass 20, count 0 2006.173.23:09:24.27#ibcon#wrote, iclass 20, count 0 2006.173.23:09:24.27#ibcon#about to read 3, iclass 20, count 0 2006.173.23:09:24.31#ibcon#read 3, iclass 20, count 0 2006.173.23:09:24.31#ibcon#about to read 4, iclass 20, count 0 2006.173.23:09:24.31#ibcon#read 4, iclass 20, count 0 2006.173.23:09:24.31#ibcon#about to read 5, iclass 20, count 0 2006.173.23:09:24.31#ibcon#read 5, iclass 20, count 0 2006.173.23:09:24.31#ibcon#about to read 6, iclass 20, count 0 2006.173.23:09:24.31#ibcon#read 6, iclass 20, count 0 2006.173.23:09:24.31#ibcon#end of sib2, iclass 20, count 0 2006.173.23:09:24.31#ibcon#*after write, iclass 20, count 0 2006.173.23:09:24.31#ibcon#*before return 0, iclass 20, count 0 2006.173.23:09:24.31#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.23:09:24.31#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.23:09:24.31#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.23:09:24.31#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.23:09:24.31$vck44/vb=5,4 2006.173.23:09:24.31#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.23:09:24.31#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.23:09:24.31#ibcon#ireg 11 cls_cnt 2 2006.173.23:09:24.31#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.23:09:24.37#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.23:09:24.37#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.23:09:24.37#ibcon#enter wrdev, iclass 22, count 2 2006.173.23:09:24.37#ibcon#first serial, iclass 22, count 2 2006.173.23:09:24.37#ibcon#enter sib2, iclass 22, count 2 2006.173.23:09:24.37#ibcon#flushed, iclass 22, count 2 2006.173.23:09:24.37#ibcon#about to write, iclass 22, count 2 2006.173.23:09:24.37#ibcon#wrote, iclass 22, count 2 2006.173.23:09:24.37#ibcon#about to read 3, iclass 22, count 2 2006.173.23:09:24.39#ibcon#read 3, iclass 22, count 2 2006.173.23:09:24.39#ibcon#about to read 4, iclass 22, count 2 2006.173.23:09:24.39#ibcon#read 4, iclass 22, count 2 2006.173.23:09:24.39#ibcon#about to read 5, iclass 22, count 2 2006.173.23:09:24.39#ibcon#read 5, iclass 22, count 2 2006.173.23:09:24.39#ibcon#about to read 6, iclass 22, count 2 2006.173.23:09:24.39#ibcon#read 6, iclass 22, count 2 2006.173.23:09:24.39#ibcon#end of sib2, iclass 22, count 2 2006.173.23:09:24.39#ibcon#*mode == 0, iclass 22, count 2 2006.173.23:09:24.39#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.23:09:24.39#ibcon#[27=AT05-04\r\n] 2006.173.23:09:24.39#ibcon#*before write, iclass 22, count 2 2006.173.23:09:24.39#ibcon#enter sib2, iclass 22, count 2 2006.173.23:09:24.39#ibcon#flushed, iclass 22, count 2 2006.173.23:09:24.39#ibcon#about to write, iclass 22, count 2 2006.173.23:09:24.39#ibcon#wrote, iclass 22, count 2 2006.173.23:09:24.39#ibcon#about to read 3, iclass 22, count 2 2006.173.23:09:24.42#ibcon#read 3, iclass 22, count 2 2006.173.23:09:24.42#ibcon#about to read 4, iclass 22, count 2 2006.173.23:09:24.42#ibcon#read 4, iclass 22, count 2 2006.173.23:09:24.42#ibcon#about to read 5, iclass 22, count 2 2006.173.23:09:24.42#ibcon#read 5, iclass 22, count 2 2006.173.23:09:24.42#ibcon#about to read 6, iclass 22, count 2 2006.173.23:09:24.42#ibcon#read 6, iclass 22, count 2 2006.173.23:09:24.42#ibcon#end of sib2, iclass 22, count 2 2006.173.23:09:24.42#ibcon#*after write, iclass 22, count 2 2006.173.23:09:24.42#ibcon#*before return 0, iclass 22, count 2 2006.173.23:09:24.42#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.23:09:24.42#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.23:09:24.42#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.23:09:24.42#ibcon#ireg 7 cls_cnt 0 2006.173.23:09:24.42#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.23:09:24.54#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.23:09:24.54#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.23:09:24.54#ibcon#enter wrdev, iclass 22, count 0 2006.173.23:09:24.54#ibcon#first serial, iclass 22, count 0 2006.173.23:09:24.54#ibcon#enter sib2, iclass 22, count 0 2006.173.23:09:24.54#ibcon#flushed, iclass 22, count 0 2006.173.23:09:24.54#ibcon#about to write, iclass 22, count 0 2006.173.23:09:24.54#ibcon#wrote, iclass 22, count 0 2006.173.23:09:24.54#ibcon#about to read 3, iclass 22, count 0 2006.173.23:09:24.56#ibcon#read 3, iclass 22, count 0 2006.173.23:09:24.56#ibcon#about to read 4, iclass 22, count 0 2006.173.23:09:24.56#ibcon#read 4, iclass 22, count 0 2006.173.23:09:24.56#ibcon#about to read 5, iclass 22, count 0 2006.173.23:09:24.56#ibcon#read 5, iclass 22, count 0 2006.173.23:09:24.56#ibcon#about to read 6, iclass 22, count 0 2006.173.23:09:24.56#ibcon#read 6, iclass 22, count 0 2006.173.23:09:24.56#ibcon#end of sib2, iclass 22, count 0 2006.173.23:09:24.56#ibcon#*mode == 0, iclass 22, count 0 2006.173.23:09:24.56#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.23:09:24.56#ibcon#[27=USB\r\n] 2006.173.23:09:24.56#ibcon#*before write, iclass 22, count 0 2006.173.23:09:24.56#ibcon#enter sib2, iclass 22, count 0 2006.173.23:09:24.56#ibcon#flushed, iclass 22, count 0 2006.173.23:09:24.56#ibcon#about to write, iclass 22, count 0 2006.173.23:09:24.56#ibcon#wrote, iclass 22, count 0 2006.173.23:09:24.56#ibcon#about to read 3, iclass 22, count 0 2006.173.23:09:24.59#ibcon#read 3, iclass 22, count 0 2006.173.23:09:24.59#ibcon#about to read 4, iclass 22, count 0 2006.173.23:09:24.59#ibcon#read 4, iclass 22, count 0 2006.173.23:09:24.59#ibcon#about to read 5, iclass 22, count 0 2006.173.23:09:24.59#ibcon#read 5, iclass 22, count 0 2006.173.23:09:24.59#ibcon#about to read 6, iclass 22, count 0 2006.173.23:09:24.59#ibcon#read 6, iclass 22, count 0 2006.173.23:09:24.59#ibcon#end of sib2, iclass 22, count 0 2006.173.23:09:24.59#ibcon#*after write, iclass 22, count 0 2006.173.23:09:24.59#ibcon#*before return 0, iclass 22, count 0 2006.173.23:09:24.59#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.23:09:24.59#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.23:09:24.59#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.23:09:24.59#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.23:09:24.59$vck44/vblo=6,719.99 2006.173.23:09:24.59#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.23:09:24.59#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.23:09:24.59#ibcon#ireg 17 cls_cnt 0 2006.173.23:09:24.59#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.23:09:24.59#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.23:09:24.59#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.23:09:24.59#ibcon#enter wrdev, iclass 24, count 0 2006.173.23:09:24.59#ibcon#first serial, iclass 24, count 0 2006.173.23:09:24.59#ibcon#enter sib2, iclass 24, count 0 2006.173.23:09:24.59#ibcon#flushed, iclass 24, count 0 2006.173.23:09:24.59#ibcon#about to write, iclass 24, count 0 2006.173.23:09:24.59#ibcon#wrote, iclass 24, count 0 2006.173.23:09:24.59#ibcon#about to read 3, iclass 24, count 0 2006.173.23:09:24.61#ibcon#read 3, iclass 24, count 0 2006.173.23:09:24.61#ibcon#about to read 4, iclass 24, count 0 2006.173.23:09:24.61#ibcon#read 4, iclass 24, count 0 2006.173.23:09:24.61#ibcon#about to read 5, iclass 24, count 0 2006.173.23:09:24.61#ibcon#read 5, iclass 24, count 0 2006.173.23:09:24.61#ibcon#about to read 6, iclass 24, count 0 2006.173.23:09:24.61#ibcon#read 6, iclass 24, count 0 2006.173.23:09:24.61#ibcon#end of sib2, iclass 24, count 0 2006.173.23:09:24.61#ibcon#*mode == 0, iclass 24, count 0 2006.173.23:09:24.61#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.23:09:24.61#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.23:09:24.61#ibcon#*before write, iclass 24, count 0 2006.173.23:09:24.61#ibcon#enter sib2, iclass 24, count 0 2006.173.23:09:24.61#ibcon#flushed, iclass 24, count 0 2006.173.23:09:24.61#ibcon#about to write, iclass 24, count 0 2006.173.23:09:24.61#ibcon#wrote, iclass 24, count 0 2006.173.23:09:24.61#ibcon#about to read 3, iclass 24, count 0 2006.173.23:09:24.65#ibcon#read 3, iclass 24, count 0 2006.173.23:09:24.65#ibcon#about to read 4, iclass 24, count 0 2006.173.23:09:24.65#ibcon#read 4, iclass 24, count 0 2006.173.23:09:24.65#ibcon#about to read 5, iclass 24, count 0 2006.173.23:09:24.65#ibcon#read 5, iclass 24, count 0 2006.173.23:09:24.65#ibcon#about to read 6, iclass 24, count 0 2006.173.23:09:24.65#ibcon#read 6, iclass 24, count 0 2006.173.23:09:24.65#ibcon#end of sib2, iclass 24, count 0 2006.173.23:09:24.65#ibcon#*after write, iclass 24, count 0 2006.173.23:09:24.65#ibcon#*before return 0, iclass 24, count 0 2006.173.23:09:24.65#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.23:09:24.65#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.23:09:24.65#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.23:09:24.65#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.23:09:24.65$vck44/vb=6,4 2006.173.23:09:24.65#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.23:09:24.65#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.23:09:24.65#ibcon#ireg 11 cls_cnt 2 2006.173.23:09:24.65#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.23:09:24.71#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.23:09:24.71#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.23:09:24.71#ibcon#enter wrdev, iclass 26, count 2 2006.173.23:09:24.71#ibcon#first serial, iclass 26, count 2 2006.173.23:09:24.71#ibcon#enter sib2, iclass 26, count 2 2006.173.23:09:24.71#ibcon#flushed, iclass 26, count 2 2006.173.23:09:24.71#ibcon#about to write, iclass 26, count 2 2006.173.23:09:24.71#ibcon#wrote, iclass 26, count 2 2006.173.23:09:24.71#ibcon#about to read 3, iclass 26, count 2 2006.173.23:09:24.73#ibcon#read 3, iclass 26, count 2 2006.173.23:09:24.73#ibcon#about to read 4, iclass 26, count 2 2006.173.23:09:24.73#ibcon#read 4, iclass 26, count 2 2006.173.23:09:24.73#ibcon#about to read 5, iclass 26, count 2 2006.173.23:09:24.73#ibcon#read 5, iclass 26, count 2 2006.173.23:09:24.73#ibcon#about to read 6, iclass 26, count 2 2006.173.23:09:24.73#ibcon#read 6, iclass 26, count 2 2006.173.23:09:24.73#ibcon#end of sib2, iclass 26, count 2 2006.173.23:09:24.73#ibcon#*mode == 0, iclass 26, count 2 2006.173.23:09:24.73#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.23:09:24.73#ibcon#[27=AT06-04\r\n] 2006.173.23:09:24.73#ibcon#*before write, iclass 26, count 2 2006.173.23:09:24.73#ibcon#enter sib2, iclass 26, count 2 2006.173.23:09:24.73#ibcon#flushed, iclass 26, count 2 2006.173.23:09:24.73#ibcon#about to write, iclass 26, count 2 2006.173.23:09:24.73#ibcon#wrote, iclass 26, count 2 2006.173.23:09:24.73#ibcon#about to read 3, iclass 26, count 2 2006.173.23:09:24.76#ibcon#read 3, iclass 26, count 2 2006.173.23:09:24.76#ibcon#about to read 4, iclass 26, count 2 2006.173.23:09:24.76#ibcon#read 4, iclass 26, count 2 2006.173.23:09:24.76#ibcon#about to read 5, iclass 26, count 2 2006.173.23:09:24.76#ibcon#read 5, iclass 26, count 2 2006.173.23:09:24.76#ibcon#about to read 6, iclass 26, count 2 2006.173.23:09:24.76#ibcon#read 6, iclass 26, count 2 2006.173.23:09:24.76#ibcon#end of sib2, iclass 26, count 2 2006.173.23:09:24.76#ibcon#*after write, iclass 26, count 2 2006.173.23:09:24.76#ibcon#*before return 0, iclass 26, count 2 2006.173.23:09:24.76#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.23:09:24.76#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.23:09:24.76#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.23:09:24.76#ibcon#ireg 7 cls_cnt 0 2006.173.23:09:24.76#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.23:09:24.88#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.23:09:24.88#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.23:09:24.88#ibcon#enter wrdev, iclass 26, count 0 2006.173.23:09:24.88#ibcon#first serial, iclass 26, count 0 2006.173.23:09:24.88#ibcon#enter sib2, iclass 26, count 0 2006.173.23:09:24.88#ibcon#flushed, iclass 26, count 0 2006.173.23:09:24.88#ibcon#about to write, iclass 26, count 0 2006.173.23:09:24.88#ibcon#wrote, iclass 26, count 0 2006.173.23:09:24.88#ibcon#about to read 3, iclass 26, count 0 2006.173.23:09:24.90#ibcon#read 3, iclass 26, count 0 2006.173.23:09:24.90#ibcon#about to read 4, iclass 26, count 0 2006.173.23:09:24.90#ibcon#read 4, iclass 26, count 0 2006.173.23:09:24.90#ibcon#about to read 5, iclass 26, count 0 2006.173.23:09:24.90#ibcon#read 5, iclass 26, count 0 2006.173.23:09:24.90#ibcon#about to read 6, iclass 26, count 0 2006.173.23:09:24.90#ibcon#read 6, iclass 26, count 0 2006.173.23:09:24.90#ibcon#end of sib2, iclass 26, count 0 2006.173.23:09:24.90#ibcon#*mode == 0, iclass 26, count 0 2006.173.23:09:24.90#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.23:09:24.90#ibcon#[27=USB\r\n] 2006.173.23:09:24.90#ibcon#*before write, iclass 26, count 0 2006.173.23:09:24.90#ibcon#enter sib2, iclass 26, count 0 2006.173.23:09:24.90#ibcon#flushed, iclass 26, count 0 2006.173.23:09:24.90#ibcon#about to write, iclass 26, count 0 2006.173.23:09:24.90#ibcon#wrote, iclass 26, count 0 2006.173.23:09:24.90#ibcon#about to read 3, iclass 26, count 0 2006.173.23:09:24.93#ibcon#read 3, iclass 26, count 0 2006.173.23:09:24.93#ibcon#about to read 4, iclass 26, count 0 2006.173.23:09:24.93#ibcon#read 4, iclass 26, count 0 2006.173.23:09:24.93#ibcon#about to read 5, iclass 26, count 0 2006.173.23:09:24.93#ibcon#read 5, iclass 26, count 0 2006.173.23:09:24.93#ibcon#about to read 6, iclass 26, count 0 2006.173.23:09:24.93#ibcon#read 6, iclass 26, count 0 2006.173.23:09:24.93#ibcon#end of sib2, iclass 26, count 0 2006.173.23:09:24.93#ibcon#*after write, iclass 26, count 0 2006.173.23:09:24.93#ibcon#*before return 0, iclass 26, count 0 2006.173.23:09:24.93#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.23:09:24.93#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.23:09:24.93#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.23:09:24.93#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.23:09:24.93$vck44/vblo=7,734.99 2006.173.23:09:24.93#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.23:09:24.93#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.23:09:24.93#ibcon#ireg 17 cls_cnt 0 2006.173.23:09:24.93#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.23:09:24.93#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.23:09:24.93#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.23:09:24.93#ibcon#enter wrdev, iclass 28, count 0 2006.173.23:09:24.93#ibcon#first serial, iclass 28, count 0 2006.173.23:09:24.93#ibcon#enter sib2, iclass 28, count 0 2006.173.23:09:24.93#ibcon#flushed, iclass 28, count 0 2006.173.23:09:24.93#ibcon#about to write, iclass 28, count 0 2006.173.23:09:24.93#ibcon#wrote, iclass 28, count 0 2006.173.23:09:24.93#ibcon#about to read 3, iclass 28, count 0 2006.173.23:09:24.95#ibcon#read 3, iclass 28, count 0 2006.173.23:09:24.95#ibcon#about to read 4, iclass 28, count 0 2006.173.23:09:24.95#ibcon#read 4, iclass 28, count 0 2006.173.23:09:24.95#ibcon#about to read 5, iclass 28, count 0 2006.173.23:09:24.95#ibcon#read 5, iclass 28, count 0 2006.173.23:09:24.95#ibcon#about to read 6, iclass 28, count 0 2006.173.23:09:24.95#ibcon#read 6, iclass 28, count 0 2006.173.23:09:24.95#ibcon#end of sib2, iclass 28, count 0 2006.173.23:09:24.95#ibcon#*mode == 0, iclass 28, count 0 2006.173.23:09:24.95#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.23:09:24.95#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.23:09:24.95#ibcon#*before write, iclass 28, count 0 2006.173.23:09:24.95#ibcon#enter sib2, iclass 28, count 0 2006.173.23:09:24.95#ibcon#flushed, iclass 28, count 0 2006.173.23:09:24.95#ibcon#about to write, iclass 28, count 0 2006.173.23:09:24.95#ibcon#wrote, iclass 28, count 0 2006.173.23:09:24.95#ibcon#about to read 3, iclass 28, count 0 2006.173.23:09:24.99#ibcon#read 3, iclass 28, count 0 2006.173.23:09:24.99#ibcon#about to read 4, iclass 28, count 0 2006.173.23:09:24.99#ibcon#read 4, iclass 28, count 0 2006.173.23:09:24.99#ibcon#about to read 5, iclass 28, count 0 2006.173.23:09:24.99#ibcon#read 5, iclass 28, count 0 2006.173.23:09:24.99#ibcon#about to read 6, iclass 28, count 0 2006.173.23:09:24.99#ibcon#read 6, iclass 28, count 0 2006.173.23:09:24.99#ibcon#end of sib2, iclass 28, count 0 2006.173.23:09:24.99#ibcon#*after write, iclass 28, count 0 2006.173.23:09:24.99#ibcon#*before return 0, iclass 28, count 0 2006.173.23:09:24.99#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.23:09:24.99#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.23:09:24.99#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.23:09:24.99#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.23:09:24.99$vck44/vb=7,4 2006.173.23:09:24.99#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.23:09:24.99#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.23:09:24.99#ibcon#ireg 11 cls_cnt 2 2006.173.23:09:24.99#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.23:09:25.05#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.23:09:25.05#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.23:09:25.05#ibcon#enter wrdev, iclass 30, count 2 2006.173.23:09:25.05#ibcon#first serial, iclass 30, count 2 2006.173.23:09:25.05#ibcon#enter sib2, iclass 30, count 2 2006.173.23:09:25.05#ibcon#flushed, iclass 30, count 2 2006.173.23:09:25.05#ibcon#about to write, iclass 30, count 2 2006.173.23:09:25.05#ibcon#wrote, iclass 30, count 2 2006.173.23:09:25.05#ibcon#about to read 3, iclass 30, count 2 2006.173.23:09:25.07#ibcon#read 3, iclass 30, count 2 2006.173.23:09:25.07#ibcon#about to read 4, iclass 30, count 2 2006.173.23:09:25.07#ibcon#read 4, iclass 30, count 2 2006.173.23:09:25.07#ibcon#about to read 5, iclass 30, count 2 2006.173.23:09:25.07#ibcon#read 5, iclass 30, count 2 2006.173.23:09:25.07#ibcon#about to read 6, iclass 30, count 2 2006.173.23:09:25.07#ibcon#read 6, iclass 30, count 2 2006.173.23:09:25.07#ibcon#end of sib2, iclass 30, count 2 2006.173.23:09:25.07#ibcon#*mode == 0, iclass 30, count 2 2006.173.23:09:25.07#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.23:09:25.07#ibcon#[27=AT07-04\r\n] 2006.173.23:09:25.07#ibcon#*before write, iclass 30, count 2 2006.173.23:09:25.07#ibcon#enter sib2, iclass 30, count 2 2006.173.23:09:25.07#ibcon#flushed, iclass 30, count 2 2006.173.23:09:25.07#ibcon#about to write, iclass 30, count 2 2006.173.23:09:25.07#ibcon#wrote, iclass 30, count 2 2006.173.23:09:25.07#ibcon#about to read 3, iclass 30, count 2 2006.173.23:09:25.10#ibcon#read 3, iclass 30, count 2 2006.173.23:09:25.10#ibcon#about to read 4, iclass 30, count 2 2006.173.23:09:25.10#ibcon#read 4, iclass 30, count 2 2006.173.23:09:25.10#ibcon#about to read 5, iclass 30, count 2 2006.173.23:09:25.10#ibcon#read 5, iclass 30, count 2 2006.173.23:09:25.10#ibcon#about to read 6, iclass 30, count 2 2006.173.23:09:25.10#ibcon#read 6, iclass 30, count 2 2006.173.23:09:25.10#ibcon#end of sib2, iclass 30, count 2 2006.173.23:09:25.10#ibcon#*after write, iclass 30, count 2 2006.173.23:09:25.10#ibcon#*before return 0, iclass 30, count 2 2006.173.23:09:25.10#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.23:09:25.10#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.23:09:25.10#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.23:09:25.10#ibcon#ireg 7 cls_cnt 0 2006.173.23:09:25.10#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.23:09:25.22#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.23:09:25.22#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.23:09:25.22#ibcon#enter wrdev, iclass 30, count 0 2006.173.23:09:25.22#ibcon#first serial, iclass 30, count 0 2006.173.23:09:25.22#ibcon#enter sib2, iclass 30, count 0 2006.173.23:09:25.22#ibcon#flushed, iclass 30, count 0 2006.173.23:09:25.22#ibcon#about to write, iclass 30, count 0 2006.173.23:09:25.22#ibcon#wrote, iclass 30, count 0 2006.173.23:09:25.22#ibcon#about to read 3, iclass 30, count 0 2006.173.23:09:25.24#ibcon#read 3, iclass 30, count 0 2006.173.23:09:25.24#ibcon#about to read 4, iclass 30, count 0 2006.173.23:09:25.24#ibcon#read 4, iclass 30, count 0 2006.173.23:09:25.24#ibcon#about to read 5, iclass 30, count 0 2006.173.23:09:25.24#ibcon#read 5, iclass 30, count 0 2006.173.23:09:25.24#ibcon#about to read 6, iclass 30, count 0 2006.173.23:09:25.24#ibcon#read 6, iclass 30, count 0 2006.173.23:09:25.24#ibcon#end of sib2, iclass 30, count 0 2006.173.23:09:25.24#ibcon#*mode == 0, iclass 30, count 0 2006.173.23:09:25.24#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.23:09:25.24#ibcon#[27=USB\r\n] 2006.173.23:09:25.24#ibcon#*before write, iclass 30, count 0 2006.173.23:09:25.24#ibcon#enter sib2, iclass 30, count 0 2006.173.23:09:25.24#ibcon#flushed, iclass 30, count 0 2006.173.23:09:25.24#ibcon#about to write, iclass 30, count 0 2006.173.23:09:25.24#ibcon#wrote, iclass 30, count 0 2006.173.23:09:25.24#ibcon#about to read 3, iclass 30, count 0 2006.173.23:09:25.27#ibcon#read 3, iclass 30, count 0 2006.173.23:09:25.27#ibcon#about to read 4, iclass 30, count 0 2006.173.23:09:25.27#ibcon#read 4, iclass 30, count 0 2006.173.23:09:25.27#ibcon#about to read 5, iclass 30, count 0 2006.173.23:09:25.27#ibcon#read 5, iclass 30, count 0 2006.173.23:09:25.27#ibcon#about to read 6, iclass 30, count 0 2006.173.23:09:25.27#ibcon#read 6, iclass 30, count 0 2006.173.23:09:25.27#ibcon#end of sib2, iclass 30, count 0 2006.173.23:09:25.27#ibcon#*after write, iclass 30, count 0 2006.173.23:09:25.27#ibcon#*before return 0, iclass 30, count 0 2006.173.23:09:25.27#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.23:09:25.27#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.23:09:25.27#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.23:09:25.27#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.23:09:25.27$vck44/vblo=8,744.99 2006.173.23:09:25.27#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.23:09:25.27#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.23:09:25.27#ibcon#ireg 17 cls_cnt 0 2006.173.23:09:25.27#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.23:09:25.27#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.23:09:25.27#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.23:09:25.27#ibcon#enter wrdev, iclass 32, count 0 2006.173.23:09:25.27#ibcon#first serial, iclass 32, count 0 2006.173.23:09:25.27#ibcon#enter sib2, iclass 32, count 0 2006.173.23:09:25.27#ibcon#flushed, iclass 32, count 0 2006.173.23:09:25.27#ibcon#about to write, iclass 32, count 0 2006.173.23:09:25.27#ibcon#wrote, iclass 32, count 0 2006.173.23:09:25.27#ibcon#about to read 3, iclass 32, count 0 2006.173.23:09:25.29#ibcon#read 3, iclass 32, count 0 2006.173.23:09:25.29#ibcon#about to read 4, iclass 32, count 0 2006.173.23:09:25.29#ibcon#read 4, iclass 32, count 0 2006.173.23:09:25.29#ibcon#about to read 5, iclass 32, count 0 2006.173.23:09:25.29#ibcon#read 5, iclass 32, count 0 2006.173.23:09:25.29#ibcon#about to read 6, iclass 32, count 0 2006.173.23:09:25.29#ibcon#read 6, iclass 32, count 0 2006.173.23:09:25.29#ibcon#end of sib2, iclass 32, count 0 2006.173.23:09:25.29#ibcon#*mode == 0, iclass 32, count 0 2006.173.23:09:25.29#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.23:09:25.29#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.23:09:25.29#ibcon#*before write, iclass 32, count 0 2006.173.23:09:25.29#ibcon#enter sib2, iclass 32, count 0 2006.173.23:09:25.29#ibcon#flushed, iclass 32, count 0 2006.173.23:09:25.29#ibcon#about to write, iclass 32, count 0 2006.173.23:09:25.29#ibcon#wrote, iclass 32, count 0 2006.173.23:09:25.29#ibcon#about to read 3, iclass 32, count 0 2006.173.23:09:25.33#ibcon#read 3, iclass 32, count 0 2006.173.23:09:25.33#ibcon#about to read 4, iclass 32, count 0 2006.173.23:09:25.33#ibcon#read 4, iclass 32, count 0 2006.173.23:09:25.33#ibcon#about to read 5, iclass 32, count 0 2006.173.23:09:25.33#ibcon#read 5, iclass 32, count 0 2006.173.23:09:25.33#ibcon#about to read 6, iclass 32, count 0 2006.173.23:09:25.33#ibcon#read 6, iclass 32, count 0 2006.173.23:09:25.33#ibcon#end of sib2, iclass 32, count 0 2006.173.23:09:25.33#ibcon#*after write, iclass 32, count 0 2006.173.23:09:25.33#ibcon#*before return 0, iclass 32, count 0 2006.173.23:09:25.33#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.23:09:25.33#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.23:09:25.33#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.23:09:25.33#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.23:09:25.33$vck44/vb=8,4 2006.173.23:09:25.33#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.23:09:25.33#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.23:09:25.33#ibcon#ireg 11 cls_cnt 2 2006.173.23:09:25.33#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.23:09:25.39#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.23:09:25.39#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.23:09:25.39#ibcon#enter wrdev, iclass 34, count 2 2006.173.23:09:25.39#ibcon#first serial, iclass 34, count 2 2006.173.23:09:25.39#ibcon#enter sib2, iclass 34, count 2 2006.173.23:09:25.39#ibcon#flushed, iclass 34, count 2 2006.173.23:09:25.39#ibcon#about to write, iclass 34, count 2 2006.173.23:09:25.39#ibcon#wrote, iclass 34, count 2 2006.173.23:09:25.39#ibcon#about to read 3, iclass 34, count 2 2006.173.23:09:25.41#ibcon#read 3, iclass 34, count 2 2006.173.23:09:25.41#ibcon#about to read 4, iclass 34, count 2 2006.173.23:09:25.41#ibcon#read 4, iclass 34, count 2 2006.173.23:09:25.41#ibcon#about to read 5, iclass 34, count 2 2006.173.23:09:25.41#ibcon#read 5, iclass 34, count 2 2006.173.23:09:25.41#ibcon#about to read 6, iclass 34, count 2 2006.173.23:09:25.41#ibcon#read 6, iclass 34, count 2 2006.173.23:09:25.41#ibcon#end of sib2, iclass 34, count 2 2006.173.23:09:25.41#ibcon#*mode == 0, iclass 34, count 2 2006.173.23:09:25.41#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.23:09:25.41#ibcon#[27=AT08-04\r\n] 2006.173.23:09:25.41#ibcon#*before write, iclass 34, count 2 2006.173.23:09:25.41#ibcon#enter sib2, iclass 34, count 2 2006.173.23:09:25.41#ibcon#flushed, iclass 34, count 2 2006.173.23:09:25.41#ibcon#about to write, iclass 34, count 2 2006.173.23:09:25.41#ibcon#wrote, iclass 34, count 2 2006.173.23:09:25.41#ibcon#about to read 3, iclass 34, count 2 2006.173.23:09:25.44#ibcon#read 3, iclass 34, count 2 2006.173.23:09:25.44#ibcon#about to read 4, iclass 34, count 2 2006.173.23:09:25.44#ibcon#read 4, iclass 34, count 2 2006.173.23:09:25.44#ibcon#about to read 5, iclass 34, count 2 2006.173.23:09:25.44#ibcon#read 5, iclass 34, count 2 2006.173.23:09:25.44#ibcon#about to read 6, iclass 34, count 2 2006.173.23:09:25.44#ibcon#read 6, iclass 34, count 2 2006.173.23:09:25.44#ibcon#end of sib2, iclass 34, count 2 2006.173.23:09:25.44#ibcon#*after write, iclass 34, count 2 2006.173.23:09:25.44#ibcon#*before return 0, iclass 34, count 2 2006.173.23:09:25.44#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.23:09:25.44#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.23:09:25.44#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.23:09:25.44#ibcon#ireg 7 cls_cnt 0 2006.173.23:09:25.44#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.23:09:25.56#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.23:09:25.56#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.23:09:25.56#ibcon#enter wrdev, iclass 34, count 0 2006.173.23:09:25.56#ibcon#first serial, iclass 34, count 0 2006.173.23:09:25.56#ibcon#enter sib2, iclass 34, count 0 2006.173.23:09:25.56#ibcon#flushed, iclass 34, count 0 2006.173.23:09:25.56#ibcon#about to write, iclass 34, count 0 2006.173.23:09:25.56#ibcon#wrote, iclass 34, count 0 2006.173.23:09:25.56#ibcon#about to read 3, iclass 34, count 0 2006.173.23:09:25.58#ibcon#read 3, iclass 34, count 0 2006.173.23:09:25.58#ibcon#about to read 4, iclass 34, count 0 2006.173.23:09:25.58#ibcon#read 4, iclass 34, count 0 2006.173.23:09:25.58#ibcon#about to read 5, iclass 34, count 0 2006.173.23:09:25.58#ibcon#read 5, iclass 34, count 0 2006.173.23:09:25.58#ibcon#about to read 6, iclass 34, count 0 2006.173.23:09:25.58#ibcon#read 6, iclass 34, count 0 2006.173.23:09:25.58#ibcon#end of sib2, iclass 34, count 0 2006.173.23:09:25.58#ibcon#*mode == 0, iclass 34, count 0 2006.173.23:09:25.58#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.23:09:25.58#ibcon#[27=USB\r\n] 2006.173.23:09:25.58#ibcon#*before write, iclass 34, count 0 2006.173.23:09:25.58#ibcon#enter sib2, iclass 34, count 0 2006.173.23:09:25.58#ibcon#flushed, iclass 34, count 0 2006.173.23:09:25.58#ibcon#about to write, iclass 34, count 0 2006.173.23:09:25.58#ibcon#wrote, iclass 34, count 0 2006.173.23:09:25.58#ibcon#about to read 3, iclass 34, count 0 2006.173.23:09:25.61#ibcon#read 3, iclass 34, count 0 2006.173.23:09:25.61#ibcon#about to read 4, iclass 34, count 0 2006.173.23:09:25.61#ibcon#read 4, iclass 34, count 0 2006.173.23:09:25.61#ibcon#about to read 5, iclass 34, count 0 2006.173.23:09:25.61#ibcon#read 5, iclass 34, count 0 2006.173.23:09:25.61#ibcon#about to read 6, iclass 34, count 0 2006.173.23:09:25.61#ibcon#read 6, iclass 34, count 0 2006.173.23:09:25.61#ibcon#end of sib2, iclass 34, count 0 2006.173.23:09:25.61#ibcon#*after write, iclass 34, count 0 2006.173.23:09:25.61#ibcon#*before return 0, iclass 34, count 0 2006.173.23:09:25.61#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.23:09:25.61#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.23:09:25.61#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.23:09:25.61#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.23:09:25.61$vck44/vabw=wide 2006.173.23:09:25.61#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.23:09:25.61#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.23:09:25.61#ibcon#ireg 8 cls_cnt 0 2006.173.23:09:25.61#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.23:09:25.61#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.23:09:25.61#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.23:09:25.61#ibcon#enter wrdev, iclass 36, count 0 2006.173.23:09:25.61#ibcon#first serial, iclass 36, count 0 2006.173.23:09:25.61#ibcon#enter sib2, iclass 36, count 0 2006.173.23:09:25.61#ibcon#flushed, iclass 36, count 0 2006.173.23:09:25.61#ibcon#about to write, iclass 36, count 0 2006.173.23:09:25.61#ibcon#wrote, iclass 36, count 0 2006.173.23:09:25.61#ibcon#about to read 3, iclass 36, count 0 2006.173.23:09:25.63#ibcon#read 3, iclass 36, count 0 2006.173.23:09:25.63#ibcon#about to read 4, iclass 36, count 0 2006.173.23:09:25.63#ibcon#read 4, iclass 36, count 0 2006.173.23:09:25.63#ibcon#about to read 5, iclass 36, count 0 2006.173.23:09:25.63#ibcon#read 5, iclass 36, count 0 2006.173.23:09:25.63#ibcon#about to read 6, iclass 36, count 0 2006.173.23:09:25.63#ibcon#read 6, iclass 36, count 0 2006.173.23:09:25.63#ibcon#end of sib2, iclass 36, count 0 2006.173.23:09:25.63#ibcon#*mode == 0, iclass 36, count 0 2006.173.23:09:25.63#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.23:09:25.63#ibcon#[25=BW32\r\n] 2006.173.23:09:25.63#ibcon#*before write, iclass 36, count 0 2006.173.23:09:25.63#ibcon#enter sib2, iclass 36, count 0 2006.173.23:09:25.63#ibcon#flushed, iclass 36, count 0 2006.173.23:09:25.63#ibcon#about to write, iclass 36, count 0 2006.173.23:09:25.63#ibcon#wrote, iclass 36, count 0 2006.173.23:09:25.63#ibcon#about to read 3, iclass 36, count 0 2006.173.23:09:25.66#ibcon#read 3, iclass 36, count 0 2006.173.23:09:25.66#ibcon#about to read 4, iclass 36, count 0 2006.173.23:09:25.66#ibcon#read 4, iclass 36, count 0 2006.173.23:09:25.66#ibcon#about to read 5, iclass 36, count 0 2006.173.23:09:25.66#ibcon#read 5, iclass 36, count 0 2006.173.23:09:25.66#ibcon#about to read 6, iclass 36, count 0 2006.173.23:09:25.66#ibcon#read 6, iclass 36, count 0 2006.173.23:09:25.66#ibcon#end of sib2, iclass 36, count 0 2006.173.23:09:25.66#ibcon#*after write, iclass 36, count 0 2006.173.23:09:25.66#ibcon#*before return 0, iclass 36, count 0 2006.173.23:09:25.66#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.23:09:25.66#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.23:09:25.66#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.23:09:25.66#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.23:09:25.66$vck44/vbbw=wide 2006.173.23:09:25.66#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.23:09:25.66#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.23:09:25.66#ibcon#ireg 8 cls_cnt 0 2006.173.23:09:25.66#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.23:09:25.73#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.23:09:25.73#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.23:09:25.73#ibcon#enter wrdev, iclass 38, count 0 2006.173.23:09:25.73#ibcon#first serial, iclass 38, count 0 2006.173.23:09:25.73#ibcon#enter sib2, iclass 38, count 0 2006.173.23:09:25.73#ibcon#flushed, iclass 38, count 0 2006.173.23:09:25.73#ibcon#about to write, iclass 38, count 0 2006.173.23:09:25.73#ibcon#wrote, iclass 38, count 0 2006.173.23:09:25.73#ibcon#about to read 3, iclass 38, count 0 2006.173.23:09:25.75#ibcon#read 3, iclass 38, count 0 2006.173.23:09:25.75#ibcon#about to read 4, iclass 38, count 0 2006.173.23:09:25.75#ibcon#read 4, iclass 38, count 0 2006.173.23:09:25.75#ibcon#about to read 5, iclass 38, count 0 2006.173.23:09:25.75#ibcon#read 5, iclass 38, count 0 2006.173.23:09:25.75#ibcon#about to read 6, iclass 38, count 0 2006.173.23:09:25.75#ibcon#read 6, iclass 38, count 0 2006.173.23:09:25.75#ibcon#end of sib2, iclass 38, count 0 2006.173.23:09:25.75#ibcon#*mode == 0, iclass 38, count 0 2006.173.23:09:25.75#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.23:09:25.75#ibcon#[27=BW32\r\n] 2006.173.23:09:25.75#ibcon#*before write, iclass 38, count 0 2006.173.23:09:25.75#ibcon#enter sib2, iclass 38, count 0 2006.173.23:09:25.75#ibcon#flushed, iclass 38, count 0 2006.173.23:09:25.75#ibcon#about to write, iclass 38, count 0 2006.173.23:09:25.75#ibcon#wrote, iclass 38, count 0 2006.173.23:09:25.75#ibcon#about to read 3, iclass 38, count 0 2006.173.23:09:25.78#ibcon#read 3, iclass 38, count 0 2006.173.23:09:25.78#ibcon#about to read 4, iclass 38, count 0 2006.173.23:09:25.78#ibcon#read 4, iclass 38, count 0 2006.173.23:09:25.78#ibcon#about to read 5, iclass 38, count 0 2006.173.23:09:25.78#ibcon#read 5, iclass 38, count 0 2006.173.23:09:25.78#ibcon#about to read 6, iclass 38, count 0 2006.173.23:09:25.78#ibcon#read 6, iclass 38, count 0 2006.173.23:09:25.78#ibcon#end of sib2, iclass 38, count 0 2006.173.23:09:25.78#ibcon#*after write, iclass 38, count 0 2006.173.23:09:25.78#ibcon#*before return 0, iclass 38, count 0 2006.173.23:09:25.78#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.23:09:25.78#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.23:09:25.78#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.23:09:25.78#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.23:09:25.78$setupk4/ifdk4 2006.173.23:09:25.78$ifdk4/lo= 2006.173.23:09:25.78$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.23:09:25.78$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.23:09:25.78$ifdk4/patch= 2006.173.23:09:25.78$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.23:09:25.78$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.23:09:25.78$setupk4/!*+20s 2006.173.23:09:30.66#abcon#<5=/09 0.6 2.0 22.97 901003.2\r\n> 2006.173.23:09:30.68#abcon#{5=INTERFACE CLEAR} 2006.173.23:09:30.74#abcon#[5=S1D000X0/0*\r\n] 2006.173.23:09:40.30$setupk4/"tpicd 2006.173.23:09:40.30$setupk4/echo=off 2006.173.23:09:40.30$setupk4/xlog=off 2006.173.23:09:40.30:!2006.173.23:11:33 2006.173.23:09:50.14#trakl#Source acquired 2006.173.23:09:51.14#flagr#flagr/antenna,acquired 2006.173.23:11:33.00:preob 2006.173.23:11:34.14/onsource/TRACKING 2006.173.23:11:34.14:!2006.173.23:11:43 2006.173.23:11:43.00:"tape 2006.173.23:11:43.00:"st=record 2006.173.23:11:43.00:data_valid=on 2006.173.23:11:43.00:midob 2006.173.23:11:43.14/onsource/TRACKING 2006.173.23:11:43.14/wx/23.03,1003.2,89 2006.173.23:11:43.29/cable/+6.5109E-03 2006.173.23:11:44.38/va/01,07,usb,yes,34,37 2006.173.23:11:44.38/va/02,06,usb,yes,34,35 2006.173.23:11:44.38/va/03,05,usb,yes,43,45 2006.173.23:11:44.38/va/04,06,usb,yes,35,36 2006.173.23:11:44.38/va/05,04,usb,yes,27,28 2006.173.23:11:44.38/va/06,03,usb,yes,38,38 2006.173.23:11:44.38/va/07,04,usb,yes,31,32 2006.173.23:11:44.38/va/08,04,usb,yes,26,32 2006.173.23:11:44.61/valo/01,524.99,yes,locked 2006.173.23:11:44.61/valo/02,534.99,yes,locked 2006.173.23:11:44.61/valo/03,564.99,yes,locked 2006.173.23:11:44.61/valo/04,624.99,yes,locked 2006.173.23:11:44.61/valo/05,734.99,yes,locked 2006.173.23:11:44.61/valo/06,814.99,yes,locked 2006.173.23:11:44.61/valo/07,864.99,yes,locked 2006.173.23:11:44.61/valo/08,884.99,yes,locked 2006.173.23:11:45.70/vb/01,04,usb,yes,29,27 2006.173.23:11:45.70/vb/02,04,usb,yes,31,31 2006.173.23:11:45.70/vb/03,04,usb,yes,28,31 2006.173.23:11:45.70/vb/04,04,usb,yes,32,31 2006.173.23:11:45.70/vb/05,04,usb,yes,25,27 2006.173.23:11:45.70/vb/06,04,usb,yes,29,26 2006.173.23:11:45.70/vb/07,04,usb,yes,29,29 2006.173.23:11:45.70/vb/08,04,usb,yes,27,30 2006.173.23:11:45.93/vblo/01,629.99,yes,locked 2006.173.23:11:45.93/vblo/02,634.99,yes,locked 2006.173.23:11:45.93/vblo/03,649.99,yes,locked 2006.173.23:11:45.93/vblo/04,679.99,yes,locked 2006.173.23:11:45.93/vblo/05,709.99,yes,locked 2006.173.23:11:45.93/vblo/06,719.99,yes,locked 2006.173.23:11:45.93/vblo/07,734.99,yes,locked 2006.173.23:11:45.93/vblo/08,744.99,yes,locked 2006.173.23:11:46.08/vabw/8 2006.173.23:11:46.23/vbbw/8 2006.173.23:11:46.32/xfe/off,on,15.2 2006.173.23:11:46.71/ifatt/23,28,28,28 2006.173.23:11:47.07/fmout-gps/S +3.93E-07 2006.173.23:11:47.11:!2006.173.23:15:13 2006.173.23:15:13.01:data_valid=off 2006.173.23:15:13.01:"et 2006.173.23:15:13.01:!+3s 2006.173.23:15:16.02:"tape 2006.173.23:15:16.02:postob 2006.173.23:15:16.17/cable/+6.5126E-03 2006.173.23:15:16.17/wx/22.99,1003.2,90 2006.173.23:15:16.23/fmout-gps/S +3.95E-07 2006.173.23:15:16.23:scan_name=173-2318,jd0606,570 2006.173.23:15:16.23:source=0133+476,013658.59,475129.1,2000.0,ccw 2006.173.23:15:17.14#flagr#flagr/antenna,new-source 2006.173.23:15:17.14:checkk5 2006.173.23:15:17.54/chk_autoobs//k5ts1/ autoobs is running! 2006.173.23:15:17.94/chk_autoobs//k5ts2/ autoobs is running! 2006.173.23:15:18.36/chk_autoobs//k5ts3/ autoobs is running! 2006.173.23:15:18.75/chk_autoobs//k5ts4/ autoobs is running! 2006.173.23:15:19.14/chk_obsdata//k5ts1/T1732311??a.dat file size is correct (nominal:840MB, actual:836MB). 2006.173.23:15:19.54/chk_obsdata//k5ts2/T1732311??b.dat file size is correct (nominal:840MB, actual:836MB). 2006.173.23:15:19.91/chk_obsdata//k5ts3/T1732311??c.dat file size is correct (nominal:840MB, actual:836MB). 2006.173.23:15:20.32/chk_obsdata//k5ts4/T1732311??d.dat file size is correct (nominal:840MB, actual:836MB). 2006.173.23:15:21.03/k5log//k5ts1_log_newline 2006.173.23:15:21.73/k5log//k5ts2_log_newline 2006.173.23:15:22.42/k5log//k5ts3_log_newline 2006.173.23:15:23.13/k5log//k5ts4_log_newline 2006.173.23:15:23.16/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.23:15:23.16:setupk4=1 2006.173.23:15:23.16$setupk4/echo=on 2006.173.23:15:23.16$setupk4/pcalon 2006.173.23:15:23.16$pcalon/"no phase cal control is implemented here 2006.173.23:15:23.16$setupk4/"tpicd=stop 2006.173.23:15:23.16$setupk4/"rec=synch_on 2006.173.23:15:23.16$setupk4/"rec_mode=128 2006.173.23:15:23.16$setupk4/!* 2006.173.23:15:23.16$setupk4/recpk4 2006.173.23:15:23.16$recpk4/recpatch= 2006.173.23:15:23.16$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.23:15:23.16$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.23:15:23.16$setupk4/vck44 2006.173.23:15:23.16$vck44/valo=1,524.99 2006.173.23:15:23.16#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.23:15:23.16#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.23:15:23.16#ibcon#ireg 17 cls_cnt 0 2006.173.23:15:23.16#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.23:15:23.16#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.23:15:23.16#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.23:15:23.16#ibcon#enter wrdev, iclass 39, count 0 2006.173.23:15:23.16#ibcon#first serial, iclass 39, count 0 2006.173.23:15:23.16#ibcon#enter sib2, iclass 39, count 0 2006.173.23:15:23.16#ibcon#flushed, iclass 39, count 0 2006.173.23:15:23.16#ibcon#about to write, iclass 39, count 0 2006.173.23:15:23.16#ibcon#wrote, iclass 39, count 0 2006.173.23:15:23.16#ibcon#about to read 3, iclass 39, count 0 2006.173.23:15:23.18#ibcon#read 3, iclass 39, count 0 2006.173.23:15:23.18#ibcon#about to read 4, iclass 39, count 0 2006.173.23:15:23.18#ibcon#read 4, iclass 39, count 0 2006.173.23:15:23.18#ibcon#about to read 5, iclass 39, count 0 2006.173.23:15:23.18#ibcon#read 5, iclass 39, count 0 2006.173.23:15:23.18#ibcon#about to read 6, iclass 39, count 0 2006.173.23:15:23.18#ibcon#read 6, iclass 39, count 0 2006.173.23:15:23.18#ibcon#end of sib2, iclass 39, count 0 2006.173.23:15:23.18#ibcon#*mode == 0, iclass 39, count 0 2006.173.23:15:23.18#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.23:15:23.18#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.23:15:23.18#ibcon#*before write, iclass 39, count 0 2006.173.23:15:23.18#ibcon#enter sib2, iclass 39, count 0 2006.173.23:15:23.18#ibcon#flushed, iclass 39, count 0 2006.173.23:15:23.18#ibcon#about to write, iclass 39, count 0 2006.173.23:15:23.18#ibcon#wrote, iclass 39, count 0 2006.173.23:15:23.18#ibcon#about to read 3, iclass 39, count 0 2006.173.23:15:23.23#ibcon#read 3, iclass 39, count 0 2006.173.23:15:23.23#ibcon#about to read 4, iclass 39, count 0 2006.173.23:15:23.23#ibcon#read 4, iclass 39, count 0 2006.173.23:15:23.23#ibcon#about to read 5, iclass 39, count 0 2006.173.23:15:23.23#ibcon#read 5, iclass 39, count 0 2006.173.23:15:23.23#ibcon#about to read 6, iclass 39, count 0 2006.173.23:15:23.23#ibcon#read 6, iclass 39, count 0 2006.173.23:15:23.23#ibcon#end of sib2, iclass 39, count 0 2006.173.23:15:23.23#ibcon#*after write, iclass 39, count 0 2006.173.23:15:23.23#ibcon#*before return 0, iclass 39, count 0 2006.173.23:15:23.23#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.23:15:23.23#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.23:15:23.23#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.23:15:23.23#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.23:15:23.23$vck44/va=1,7 2006.173.23:15:23.23#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.23:15:23.23#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.23:15:23.23#ibcon#ireg 11 cls_cnt 2 2006.173.23:15:23.23#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.23:15:23.23#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.23:15:23.23#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.23:15:23.23#ibcon#enter wrdev, iclass 3, count 2 2006.173.23:15:23.23#ibcon#first serial, iclass 3, count 2 2006.173.23:15:23.23#ibcon#enter sib2, iclass 3, count 2 2006.173.23:15:23.23#ibcon#flushed, iclass 3, count 2 2006.173.23:15:23.23#ibcon#about to write, iclass 3, count 2 2006.173.23:15:23.23#ibcon#wrote, iclass 3, count 2 2006.173.23:15:23.23#ibcon#about to read 3, iclass 3, count 2 2006.173.23:15:23.25#ibcon#read 3, iclass 3, count 2 2006.173.23:15:23.25#ibcon#about to read 4, iclass 3, count 2 2006.173.23:15:23.25#ibcon#read 4, iclass 3, count 2 2006.173.23:15:23.25#ibcon#about to read 5, iclass 3, count 2 2006.173.23:15:23.25#ibcon#read 5, iclass 3, count 2 2006.173.23:15:23.25#ibcon#about to read 6, iclass 3, count 2 2006.173.23:15:23.25#ibcon#read 6, iclass 3, count 2 2006.173.23:15:23.25#ibcon#end of sib2, iclass 3, count 2 2006.173.23:15:23.25#ibcon#*mode == 0, iclass 3, count 2 2006.173.23:15:23.25#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.23:15:23.25#ibcon#[25=AT01-07\r\n] 2006.173.23:15:23.25#ibcon#*before write, iclass 3, count 2 2006.173.23:15:23.25#ibcon#enter sib2, iclass 3, count 2 2006.173.23:15:23.25#ibcon#flushed, iclass 3, count 2 2006.173.23:15:23.25#ibcon#about to write, iclass 3, count 2 2006.173.23:15:23.25#ibcon#wrote, iclass 3, count 2 2006.173.23:15:23.25#ibcon#about to read 3, iclass 3, count 2 2006.173.23:15:23.28#ibcon#read 3, iclass 3, count 2 2006.173.23:15:23.28#ibcon#about to read 4, iclass 3, count 2 2006.173.23:15:23.28#ibcon#read 4, iclass 3, count 2 2006.173.23:15:23.28#ibcon#about to read 5, iclass 3, count 2 2006.173.23:15:23.28#ibcon#read 5, iclass 3, count 2 2006.173.23:15:23.28#ibcon#about to read 6, iclass 3, count 2 2006.173.23:15:23.28#ibcon#read 6, iclass 3, count 2 2006.173.23:15:23.28#ibcon#end of sib2, iclass 3, count 2 2006.173.23:15:23.28#ibcon#*after write, iclass 3, count 2 2006.173.23:15:23.28#ibcon#*before return 0, iclass 3, count 2 2006.173.23:15:23.28#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.23:15:23.28#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.23:15:23.28#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.23:15:23.28#ibcon#ireg 7 cls_cnt 0 2006.173.23:15:23.28#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.23:15:23.40#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.23:15:23.40#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.23:15:23.40#ibcon#enter wrdev, iclass 3, count 0 2006.173.23:15:23.40#ibcon#first serial, iclass 3, count 0 2006.173.23:15:23.40#ibcon#enter sib2, iclass 3, count 0 2006.173.23:15:23.40#ibcon#flushed, iclass 3, count 0 2006.173.23:15:23.40#ibcon#about to write, iclass 3, count 0 2006.173.23:15:23.40#ibcon#wrote, iclass 3, count 0 2006.173.23:15:23.40#ibcon#about to read 3, iclass 3, count 0 2006.173.23:15:23.42#ibcon#read 3, iclass 3, count 0 2006.173.23:15:23.42#ibcon#about to read 4, iclass 3, count 0 2006.173.23:15:23.42#ibcon#read 4, iclass 3, count 0 2006.173.23:15:23.42#ibcon#about to read 5, iclass 3, count 0 2006.173.23:15:23.42#ibcon#read 5, iclass 3, count 0 2006.173.23:15:23.42#ibcon#about to read 6, iclass 3, count 0 2006.173.23:15:23.42#ibcon#read 6, iclass 3, count 0 2006.173.23:15:23.42#ibcon#end of sib2, iclass 3, count 0 2006.173.23:15:23.42#ibcon#*mode == 0, iclass 3, count 0 2006.173.23:15:23.42#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.23:15:23.42#ibcon#[25=USB\r\n] 2006.173.23:15:23.42#ibcon#*before write, iclass 3, count 0 2006.173.23:15:23.42#ibcon#enter sib2, iclass 3, count 0 2006.173.23:15:23.42#ibcon#flushed, iclass 3, count 0 2006.173.23:15:23.42#ibcon#about to write, iclass 3, count 0 2006.173.23:15:23.42#ibcon#wrote, iclass 3, count 0 2006.173.23:15:23.42#ibcon#about to read 3, iclass 3, count 0 2006.173.23:15:23.45#ibcon#read 3, iclass 3, count 0 2006.173.23:15:23.45#ibcon#about to read 4, iclass 3, count 0 2006.173.23:15:23.45#ibcon#read 4, iclass 3, count 0 2006.173.23:15:23.45#ibcon#about to read 5, iclass 3, count 0 2006.173.23:15:23.45#ibcon#read 5, iclass 3, count 0 2006.173.23:15:23.45#ibcon#about to read 6, iclass 3, count 0 2006.173.23:15:23.45#ibcon#read 6, iclass 3, count 0 2006.173.23:15:23.45#ibcon#end of sib2, iclass 3, count 0 2006.173.23:15:23.45#ibcon#*after write, iclass 3, count 0 2006.173.23:15:23.45#ibcon#*before return 0, iclass 3, count 0 2006.173.23:15:23.45#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.23:15:23.45#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.23:15:23.45#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.23:15:23.45#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.23:15:23.45$vck44/valo=2,534.99 2006.173.23:15:23.45#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.23:15:23.45#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.23:15:23.45#ibcon#ireg 17 cls_cnt 0 2006.173.23:15:23.45#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.23:15:23.45#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.23:15:23.45#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.23:15:23.45#ibcon#enter wrdev, iclass 5, count 0 2006.173.23:15:23.45#ibcon#first serial, iclass 5, count 0 2006.173.23:15:23.45#ibcon#enter sib2, iclass 5, count 0 2006.173.23:15:23.45#ibcon#flushed, iclass 5, count 0 2006.173.23:15:23.45#ibcon#about to write, iclass 5, count 0 2006.173.23:15:23.45#ibcon#wrote, iclass 5, count 0 2006.173.23:15:23.45#ibcon#about to read 3, iclass 5, count 0 2006.173.23:15:23.47#ibcon#read 3, iclass 5, count 0 2006.173.23:15:23.47#ibcon#about to read 4, iclass 5, count 0 2006.173.23:15:23.47#ibcon#read 4, iclass 5, count 0 2006.173.23:15:23.47#ibcon#about to read 5, iclass 5, count 0 2006.173.23:15:23.47#ibcon#read 5, iclass 5, count 0 2006.173.23:15:23.47#ibcon#about to read 6, iclass 5, count 0 2006.173.23:15:23.47#ibcon#read 6, iclass 5, count 0 2006.173.23:15:23.47#ibcon#end of sib2, iclass 5, count 0 2006.173.23:15:23.47#ibcon#*mode == 0, iclass 5, count 0 2006.173.23:15:23.47#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.23:15:23.47#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.23:15:23.47#ibcon#*before write, iclass 5, count 0 2006.173.23:15:23.47#ibcon#enter sib2, iclass 5, count 0 2006.173.23:15:23.47#ibcon#flushed, iclass 5, count 0 2006.173.23:15:23.47#ibcon#about to write, iclass 5, count 0 2006.173.23:15:23.47#ibcon#wrote, iclass 5, count 0 2006.173.23:15:23.47#ibcon#about to read 3, iclass 5, count 0 2006.173.23:15:23.51#ibcon#read 3, iclass 5, count 0 2006.173.23:15:23.51#ibcon#about to read 4, iclass 5, count 0 2006.173.23:15:23.51#ibcon#read 4, iclass 5, count 0 2006.173.23:15:23.51#ibcon#about to read 5, iclass 5, count 0 2006.173.23:15:23.51#ibcon#read 5, iclass 5, count 0 2006.173.23:15:23.51#ibcon#about to read 6, iclass 5, count 0 2006.173.23:15:23.51#ibcon#read 6, iclass 5, count 0 2006.173.23:15:23.51#ibcon#end of sib2, iclass 5, count 0 2006.173.23:15:23.51#ibcon#*after write, iclass 5, count 0 2006.173.23:15:23.51#ibcon#*before return 0, iclass 5, count 0 2006.173.23:15:23.51#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.23:15:23.51#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.23:15:23.51#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.23:15:23.51#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.23:15:23.51$vck44/va=2,6 2006.173.23:15:23.51#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.173.23:15:23.51#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.173.23:15:23.51#ibcon#ireg 11 cls_cnt 2 2006.173.23:15:23.51#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.23:15:23.57#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.23:15:23.57#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.23:15:23.57#ibcon#enter wrdev, iclass 7, count 2 2006.173.23:15:23.57#ibcon#first serial, iclass 7, count 2 2006.173.23:15:23.57#ibcon#enter sib2, iclass 7, count 2 2006.173.23:15:23.57#ibcon#flushed, iclass 7, count 2 2006.173.23:15:23.57#ibcon#about to write, iclass 7, count 2 2006.173.23:15:23.57#ibcon#wrote, iclass 7, count 2 2006.173.23:15:23.57#ibcon#about to read 3, iclass 7, count 2 2006.173.23:15:23.59#ibcon#read 3, iclass 7, count 2 2006.173.23:15:23.59#ibcon#about to read 4, iclass 7, count 2 2006.173.23:15:23.59#ibcon#read 4, iclass 7, count 2 2006.173.23:15:23.59#ibcon#about to read 5, iclass 7, count 2 2006.173.23:15:23.59#ibcon#read 5, iclass 7, count 2 2006.173.23:15:23.59#ibcon#about to read 6, iclass 7, count 2 2006.173.23:15:23.59#ibcon#read 6, iclass 7, count 2 2006.173.23:15:23.59#ibcon#end of sib2, iclass 7, count 2 2006.173.23:15:23.59#ibcon#*mode == 0, iclass 7, count 2 2006.173.23:15:23.59#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.173.23:15:23.59#ibcon#[25=AT02-06\r\n] 2006.173.23:15:23.59#ibcon#*before write, iclass 7, count 2 2006.173.23:15:23.59#ibcon#enter sib2, iclass 7, count 2 2006.173.23:15:23.59#ibcon#flushed, iclass 7, count 2 2006.173.23:15:23.59#ibcon#about to write, iclass 7, count 2 2006.173.23:15:23.59#ibcon#wrote, iclass 7, count 2 2006.173.23:15:23.59#ibcon#about to read 3, iclass 7, count 2 2006.173.23:15:23.62#ibcon#read 3, iclass 7, count 2 2006.173.23:15:23.62#ibcon#about to read 4, iclass 7, count 2 2006.173.23:15:23.62#ibcon#read 4, iclass 7, count 2 2006.173.23:15:23.62#ibcon#about to read 5, iclass 7, count 2 2006.173.23:15:23.62#ibcon#read 5, iclass 7, count 2 2006.173.23:15:23.62#ibcon#about to read 6, iclass 7, count 2 2006.173.23:15:23.62#ibcon#read 6, iclass 7, count 2 2006.173.23:15:23.62#ibcon#end of sib2, iclass 7, count 2 2006.173.23:15:23.62#ibcon#*after write, iclass 7, count 2 2006.173.23:15:23.62#ibcon#*before return 0, iclass 7, count 2 2006.173.23:15:23.62#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.23:15:23.62#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.173.23:15:23.62#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.173.23:15:23.62#ibcon#ireg 7 cls_cnt 0 2006.173.23:15:23.62#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.23:15:23.74#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.23:15:23.74#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.23:15:23.74#ibcon#enter wrdev, iclass 7, count 0 2006.173.23:15:23.74#ibcon#first serial, iclass 7, count 0 2006.173.23:15:23.74#ibcon#enter sib2, iclass 7, count 0 2006.173.23:15:23.74#ibcon#flushed, iclass 7, count 0 2006.173.23:15:23.74#ibcon#about to write, iclass 7, count 0 2006.173.23:15:23.74#ibcon#wrote, iclass 7, count 0 2006.173.23:15:23.74#ibcon#about to read 3, iclass 7, count 0 2006.173.23:15:23.76#ibcon#read 3, iclass 7, count 0 2006.173.23:15:23.76#ibcon#about to read 4, iclass 7, count 0 2006.173.23:15:23.76#ibcon#read 4, iclass 7, count 0 2006.173.23:15:23.76#ibcon#about to read 5, iclass 7, count 0 2006.173.23:15:23.76#ibcon#read 5, iclass 7, count 0 2006.173.23:15:23.76#ibcon#about to read 6, iclass 7, count 0 2006.173.23:15:23.76#ibcon#read 6, iclass 7, count 0 2006.173.23:15:23.76#ibcon#end of sib2, iclass 7, count 0 2006.173.23:15:23.76#ibcon#*mode == 0, iclass 7, count 0 2006.173.23:15:23.76#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.23:15:23.76#ibcon#[25=USB\r\n] 2006.173.23:15:23.76#ibcon#*before write, iclass 7, count 0 2006.173.23:15:23.76#ibcon#enter sib2, iclass 7, count 0 2006.173.23:15:23.76#ibcon#flushed, iclass 7, count 0 2006.173.23:15:23.76#ibcon#about to write, iclass 7, count 0 2006.173.23:15:23.76#ibcon#wrote, iclass 7, count 0 2006.173.23:15:23.76#ibcon#about to read 3, iclass 7, count 0 2006.173.23:15:23.79#ibcon#read 3, iclass 7, count 0 2006.173.23:15:23.79#ibcon#about to read 4, iclass 7, count 0 2006.173.23:15:23.79#ibcon#read 4, iclass 7, count 0 2006.173.23:15:23.79#ibcon#about to read 5, iclass 7, count 0 2006.173.23:15:23.79#ibcon#read 5, iclass 7, count 0 2006.173.23:15:23.79#ibcon#about to read 6, iclass 7, count 0 2006.173.23:15:23.79#ibcon#read 6, iclass 7, count 0 2006.173.23:15:23.79#ibcon#end of sib2, iclass 7, count 0 2006.173.23:15:23.79#ibcon#*after write, iclass 7, count 0 2006.173.23:15:23.79#ibcon#*before return 0, iclass 7, count 0 2006.173.23:15:23.79#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.23:15:23.79#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.173.23:15:23.79#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.23:15:23.79#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.23:15:23.79$vck44/valo=3,564.99 2006.173.23:15:23.79#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.23:15:23.79#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.23:15:23.79#ibcon#ireg 17 cls_cnt 0 2006.173.23:15:23.79#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.23:15:23.79#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.23:15:23.79#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.23:15:23.79#ibcon#enter wrdev, iclass 11, count 0 2006.173.23:15:23.79#ibcon#first serial, iclass 11, count 0 2006.173.23:15:23.79#ibcon#enter sib2, iclass 11, count 0 2006.173.23:15:23.79#ibcon#flushed, iclass 11, count 0 2006.173.23:15:23.79#ibcon#about to write, iclass 11, count 0 2006.173.23:15:23.79#ibcon#wrote, iclass 11, count 0 2006.173.23:15:23.79#ibcon#about to read 3, iclass 11, count 0 2006.173.23:15:23.81#ibcon#read 3, iclass 11, count 0 2006.173.23:15:23.81#ibcon#about to read 4, iclass 11, count 0 2006.173.23:15:23.81#ibcon#read 4, iclass 11, count 0 2006.173.23:15:23.81#ibcon#about to read 5, iclass 11, count 0 2006.173.23:15:23.81#ibcon#read 5, iclass 11, count 0 2006.173.23:15:23.81#ibcon#about to read 6, iclass 11, count 0 2006.173.23:15:23.81#ibcon#read 6, iclass 11, count 0 2006.173.23:15:23.81#ibcon#end of sib2, iclass 11, count 0 2006.173.23:15:23.81#ibcon#*mode == 0, iclass 11, count 0 2006.173.23:15:23.81#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.23:15:23.81#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.23:15:23.81#ibcon#*before write, iclass 11, count 0 2006.173.23:15:23.81#ibcon#enter sib2, iclass 11, count 0 2006.173.23:15:23.81#ibcon#flushed, iclass 11, count 0 2006.173.23:15:23.81#ibcon#about to write, iclass 11, count 0 2006.173.23:15:23.81#ibcon#wrote, iclass 11, count 0 2006.173.23:15:23.81#ibcon#about to read 3, iclass 11, count 0 2006.173.23:15:23.85#ibcon#read 3, iclass 11, count 0 2006.173.23:15:23.85#ibcon#about to read 4, iclass 11, count 0 2006.173.23:15:23.85#ibcon#read 4, iclass 11, count 0 2006.173.23:15:23.85#ibcon#about to read 5, iclass 11, count 0 2006.173.23:15:23.85#ibcon#read 5, iclass 11, count 0 2006.173.23:15:23.85#ibcon#about to read 6, iclass 11, count 0 2006.173.23:15:23.85#ibcon#read 6, iclass 11, count 0 2006.173.23:15:23.85#ibcon#end of sib2, iclass 11, count 0 2006.173.23:15:23.85#ibcon#*after write, iclass 11, count 0 2006.173.23:15:23.85#ibcon#*before return 0, iclass 11, count 0 2006.173.23:15:23.85#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.23:15:23.85#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.23:15:23.85#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.23:15:23.85#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.23:15:23.85$vck44/va=3,5 2006.173.23:15:23.85#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.173.23:15:23.85#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.173.23:15:23.85#ibcon#ireg 11 cls_cnt 2 2006.173.23:15:23.85#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.23:15:23.91#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.23:15:23.91#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.23:15:23.91#ibcon#enter wrdev, iclass 13, count 2 2006.173.23:15:23.91#ibcon#first serial, iclass 13, count 2 2006.173.23:15:23.91#ibcon#enter sib2, iclass 13, count 2 2006.173.23:15:23.91#ibcon#flushed, iclass 13, count 2 2006.173.23:15:23.91#ibcon#about to write, iclass 13, count 2 2006.173.23:15:23.91#ibcon#wrote, iclass 13, count 2 2006.173.23:15:23.91#ibcon#about to read 3, iclass 13, count 2 2006.173.23:15:23.93#ibcon#read 3, iclass 13, count 2 2006.173.23:15:23.93#ibcon#about to read 4, iclass 13, count 2 2006.173.23:15:23.93#ibcon#read 4, iclass 13, count 2 2006.173.23:15:23.93#ibcon#about to read 5, iclass 13, count 2 2006.173.23:15:23.93#ibcon#read 5, iclass 13, count 2 2006.173.23:15:23.93#ibcon#about to read 6, iclass 13, count 2 2006.173.23:15:23.93#ibcon#read 6, iclass 13, count 2 2006.173.23:15:23.93#ibcon#end of sib2, iclass 13, count 2 2006.173.23:15:23.93#ibcon#*mode == 0, iclass 13, count 2 2006.173.23:15:23.93#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.173.23:15:23.93#ibcon#[25=AT03-05\r\n] 2006.173.23:15:23.93#ibcon#*before write, iclass 13, count 2 2006.173.23:15:23.93#ibcon#enter sib2, iclass 13, count 2 2006.173.23:15:23.93#ibcon#flushed, iclass 13, count 2 2006.173.23:15:23.93#ibcon#about to write, iclass 13, count 2 2006.173.23:15:23.93#ibcon#wrote, iclass 13, count 2 2006.173.23:15:23.93#ibcon#about to read 3, iclass 13, count 2 2006.173.23:15:23.96#ibcon#read 3, iclass 13, count 2 2006.173.23:15:23.96#ibcon#about to read 4, iclass 13, count 2 2006.173.23:15:23.96#ibcon#read 4, iclass 13, count 2 2006.173.23:15:23.96#ibcon#about to read 5, iclass 13, count 2 2006.173.23:15:23.96#ibcon#read 5, iclass 13, count 2 2006.173.23:15:23.96#ibcon#about to read 6, iclass 13, count 2 2006.173.23:15:23.96#ibcon#read 6, iclass 13, count 2 2006.173.23:15:23.96#ibcon#end of sib2, iclass 13, count 2 2006.173.23:15:23.96#ibcon#*after write, iclass 13, count 2 2006.173.23:15:23.96#ibcon#*before return 0, iclass 13, count 2 2006.173.23:15:23.96#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.23:15:23.96#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.173.23:15:23.96#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.173.23:15:23.96#ibcon#ireg 7 cls_cnt 0 2006.173.23:15:23.96#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.23:15:24.08#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.23:15:24.08#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.23:15:24.08#ibcon#enter wrdev, iclass 13, count 0 2006.173.23:15:24.08#ibcon#first serial, iclass 13, count 0 2006.173.23:15:24.08#ibcon#enter sib2, iclass 13, count 0 2006.173.23:15:24.08#ibcon#flushed, iclass 13, count 0 2006.173.23:15:24.08#ibcon#about to write, iclass 13, count 0 2006.173.23:15:24.08#ibcon#wrote, iclass 13, count 0 2006.173.23:15:24.08#ibcon#about to read 3, iclass 13, count 0 2006.173.23:15:24.10#ibcon#read 3, iclass 13, count 0 2006.173.23:15:24.10#ibcon#about to read 4, iclass 13, count 0 2006.173.23:15:24.10#ibcon#read 4, iclass 13, count 0 2006.173.23:15:24.10#ibcon#about to read 5, iclass 13, count 0 2006.173.23:15:24.10#ibcon#read 5, iclass 13, count 0 2006.173.23:15:24.10#ibcon#about to read 6, iclass 13, count 0 2006.173.23:15:24.10#ibcon#read 6, iclass 13, count 0 2006.173.23:15:24.10#ibcon#end of sib2, iclass 13, count 0 2006.173.23:15:24.10#ibcon#*mode == 0, iclass 13, count 0 2006.173.23:15:24.10#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.23:15:24.10#ibcon#[25=USB\r\n] 2006.173.23:15:24.10#ibcon#*before write, iclass 13, count 0 2006.173.23:15:24.10#ibcon#enter sib2, iclass 13, count 0 2006.173.23:15:24.10#ibcon#flushed, iclass 13, count 0 2006.173.23:15:24.10#ibcon#about to write, iclass 13, count 0 2006.173.23:15:24.10#ibcon#wrote, iclass 13, count 0 2006.173.23:15:24.10#ibcon#about to read 3, iclass 13, count 0 2006.173.23:15:24.13#ibcon#read 3, iclass 13, count 0 2006.173.23:15:24.13#ibcon#about to read 4, iclass 13, count 0 2006.173.23:15:24.13#ibcon#read 4, iclass 13, count 0 2006.173.23:15:24.13#ibcon#about to read 5, iclass 13, count 0 2006.173.23:15:24.13#ibcon#read 5, iclass 13, count 0 2006.173.23:15:24.13#ibcon#about to read 6, iclass 13, count 0 2006.173.23:15:24.13#ibcon#read 6, iclass 13, count 0 2006.173.23:15:24.13#ibcon#end of sib2, iclass 13, count 0 2006.173.23:15:24.13#ibcon#*after write, iclass 13, count 0 2006.173.23:15:24.13#ibcon#*before return 0, iclass 13, count 0 2006.173.23:15:24.13#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.23:15:24.13#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.173.23:15:24.13#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.23:15:24.13#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.23:15:24.13$vck44/valo=4,624.99 2006.173.23:15:24.13#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.23:15:24.13#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.23:15:24.13#ibcon#ireg 17 cls_cnt 0 2006.173.23:15:24.13#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.23:15:24.13#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.23:15:24.13#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.23:15:24.13#ibcon#enter wrdev, iclass 15, count 0 2006.173.23:15:24.13#ibcon#first serial, iclass 15, count 0 2006.173.23:15:24.13#ibcon#enter sib2, iclass 15, count 0 2006.173.23:15:24.13#ibcon#flushed, iclass 15, count 0 2006.173.23:15:24.13#ibcon#about to write, iclass 15, count 0 2006.173.23:15:24.13#ibcon#wrote, iclass 15, count 0 2006.173.23:15:24.13#ibcon#about to read 3, iclass 15, count 0 2006.173.23:15:24.15#ibcon#read 3, iclass 15, count 0 2006.173.23:15:24.15#ibcon#about to read 4, iclass 15, count 0 2006.173.23:15:24.15#ibcon#read 4, iclass 15, count 0 2006.173.23:15:24.15#ibcon#about to read 5, iclass 15, count 0 2006.173.23:15:24.15#ibcon#read 5, iclass 15, count 0 2006.173.23:15:24.15#ibcon#about to read 6, iclass 15, count 0 2006.173.23:15:24.15#ibcon#read 6, iclass 15, count 0 2006.173.23:15:24.15#ibcon#end of sib2, iclass 15, count 0 2006.173.23:15:24.15#ibcon#*mode == 0, iclass 15, count 0 2006.173.23:15:24.15#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.23:15:24.15#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.23:15:24.15#ibcon#*before write, iclass 15, count 0 2006.173.23:15:24.15#ibcon#enter sib2, iclass 15, count 0 2006.173.23:15:24.15#ibcon#flushed, iclass 15, count 0 2006.173.23:15:24.15#ibcon#about to write, iclass 15, count 0 2006.173.23:15:24.15#ibcon#wrote, iclass 15, count 0 2006.173.23:15:24.15#ibcon#about to read 3, iclass 15, count 0 2006.173.23:15:24.19#ibcon#read 3, iclass 15, count 0 2006.173.23:15:24.19#ibcon#about to read 4, iclass 15, count 0 2006.173.23:15:24.19#ibcon#read 4, iclass 15, count 0 2006.173.23:15:24.19#ibcon#about to read 5, iclass 15, count 0 2006.173.23:15:24.19#ibcon#read 5, iclass 15, count 0 2006.173.23:15:24.19#ibcon#about to read 6, iclass 15, count 0 2006.173.23:15:24.19#ibcon#read 6, iclass 15, count 0 2006.173.23:15:24.19#ibcon#end of sib2, iclass 15, count 0 2006.173.23:15:24.19#ibcon#*after write, iclass 15, count 0 2006.173.23:15:24.19#ibcon#*before return 0, iclass 15, count 0 2006.173.23:15:24.19#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.23:15:24.19#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.23:15:24.19#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.23:15:24.19#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.23:15:24.19$vck44/va=4,6 2006.173.23:15:24.19#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.23:15:24.19#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.23:15:24.19#ibcon#ireg 11 cls_cnt 2 2006.173.23:15:24.19#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.23:15:24.25#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.23:15:24.25#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.23:15:24.25#ibcon#enter wrdev, iclass 17, count 2 2006.173.23:15:24.25#ibcon#first serial, iclass 17, count 2 2006.173.23:15:24.25#ibcon#enter sib2, iclass 17, count 2 2006.173.23:15:24.25#ibcon#flushed, iclass 17, count 2 2006.173.23:15:24.25#ibcon#about to write, iclass 17, count 2 2006.173.23:15:24.25#ibcon#wrote, iclass 17, count 2 2006.173.23:15:24.25#ibcon#about to read 3, iclass 17, count 2 2006.173.23:15:24.27#ibcon#read 3, iclass 17, count 2 2006.173.23:15:24.27#ibcon#about to read 4, iclass 17, count 2 2006.173.23:15:24.27#ibcon#read 4, iclass 17, count 2 2006.173.23:15:24.27#ibcon#about to read 5, iclass 17, count 2 2006.173.23:15:24.27#ibcon#read 5, iclass 17, count 2 2006.173.23:15:24.27#ibcon#about to read 6, iclass 17, count 2 2006.173.23:15:24.27#ibcon#read 6, iclass 17, count 2 2006.173.23:15:24.27#ibcon#end of sib2, iclass 17, count 2 2006.173.23:15:24.27#ibcon#*mode == 0, iclass 17, count 2 2006.173.23:15:24.27#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.23:15:24.27#ibcon#[25=AT04-06\r\n] 2006.173.23:15:24.27#ibcon#*before write, iclass 17, count 2 2006.173.23:15:24.27#ibcon#enter sib2, iclass 17, count 2 2006.173.23:15:24.27#ibcon#flushed, iclass 17, count 2 2006.173.23:15:24.27#ibcon#about to write, iclass 17, count 2 2006.173.23:15:24.27#ibcon#wrote, iclass 17, count 2 2006.173.23:15:24.27#ibcon#about to read 3, iclass 17, count 2 2006.173.23:15:24.30#ibcon#read 3, iclass 17, count 2 2006.173.23:15:24.30#ibcon#about to read 4, iclass 17, count 2 2006.173.23:15:24.30#ibcon#read 4, iclass 17, count 2 2006.173.23:15:24.30#ibcon#about to read 5, iclass 17, count 2 2006.173.23:15:24.30#ibcon#read 5, iclass 17, count 2 2006.173.23:15:24.30#ibcon#about to read 6, iclass 17, count 2 2006.173.23:15:24.30#ibcon#read 6, iclass 17, count 2 2006.173.23:15:24.30#ibcon#end of sib2, iclass 17, count 2 2006.173.23:15:24.30#ibcon#*after write, iclass 17, count 2 2006.173.23:15:24.30#ibcon#*before return 0, iclass 17, count 2 2006.173.23:15:24.30#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.23:15:24.30#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.23:15:24.30#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.23:15:24.30#ibcon#ireg 7 cls_cnt 0 2006.173.23:15:24.30#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.23:15:24.42#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.23:15:24.42#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.23:15:24.42#ibcon#enter wrdev, iclass 17, count 0 2006.173.23:15:24.42#ibcon#first serial, iclass 17, count 0 2006.173.23:15:24.42#ibcon#enter sib2, iclass 17, count 0 2006.173.23:15:24.42#ibcon#flushed, iclass 17, count 0 2006.173.23:15:24.42#ibcon#about to write, iclass 17, count 0 2006.173.23:15:24.42#ibcon#wrote, iclass 17, count 0 2006.173.23:15:24.42#ibcon#about to read 3, iclass 17, count 0 2006.173.23:15:24.44#ibcon#read 3, iclass 17, count 0 2006.173.23:15:24.44#ibcon#about to read 4, iclass 17, count 0 2006.173.23:15:24.44#ibcon#read 4, iclass 17, count 0 2006.173.23:15:24.44#ibcon#about to read 5, iclass 17, count 0 2006.173.23:15:24.44#ibcon#read 5, iclass 17, count 0 2006.173.23:15:24.44#ibcon#about to read 6, iclass 17, count 0 2006.173.23:15:24.44#ibcon#read 6, iclass 17, count 0 2006.173.23:15:24.44#ibcon#end of sib2, iclass 17, count 0 2006.173.23:15:24.44#ibcon#*mode == 0, iclass 17, count 0 2006.173.23:15:24.44#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.23:15:24.44#ibcon#[25=USB\r\n] 2006.173.23:15:24.44#ibcon#*before write, iclass 17, count 0 2006.173.23:15:24.44#ibcon#enter sib2, iclass 17, count 0 2006.173.23:15:24.44#ibcon#flushed, iclass 17, count 0 2006.173.23:15:24.44#ibcon#about to write, iclass 17, count 0 2006.173.23:15:24.44#ibcon#wrote, iclass 17, count 0 2006.173.23:15:24.44#ibcon#about to read 3, iclass 17, count 0 2006.173.23:15:24.47#ibcon#read 3, iclass 17, count 0 2006.173.23:15:24.47#ibcon#about to read 4, iclass 17, count 0 2006.173.23:15:24.47#ibcon#read 4, iclass 17, count 0 2006.173.23:15:24.47#ibcon#about to read 5, iclass 17, count 0 2006.173.23:15:24.47#ibcon#read 5, iclass 17, count 0 2006.173.23:15:24.47#ibcon#about to read 6, iclass 17, count 0 2006.173.23:15:24.47#ibcon#read 6, iclass 17, count 0 2006.173.23:15:24.47#ibcon#end of sib2, iclass 17, count 0 2006.173.23:15:24.47#ibcon#*after write, iclass 17, count 0 2006.173.23:15:24.47#ibcon#*before return 0, iclass 17, count 0 2006.173.23:15:24.47#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.23:15:24.47#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.23:15:24.47#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.23:15:24.47#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.23:15:24.47$vck44/valo=5,734.99 2006.173.23:15:24.47#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.23:15:24.47#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.23:15:24.47#ibcon#ireg 17 cls_cnt 0 2006.173.23:15:24.47#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.23:15:24.47#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.23:15:24.47#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.23:15:24.47#ibcon#enter wrdev, iclass 19, count 0 2006.173.23:15:24.47#ibcon#first serial, iclass 19, count 0 2006.173.23:15:24.47#ibcon#enter sib2, iclass 19, count 0 2006.173.23:15:24.47#ibcon#flushed, iclass 19, count 0 2006.173.23:15:24.47#ibcon#about to write, iclass 19, count 0 2006.173.23:15:24.47#ibcon#wrote, iclass 19, count 0 2006.173.23:15:24.47#ibcon#about to read 3, iclass 19, count 0 2006.173.23:15:24.49#ibcon#read 3, iclass 19, count 0 2006.173.23:15:24.49#ibcon#about to read 4, iclass 19, count 0 2006.173.23:15:24.49#ibcon#read 4, iclass 19, count 0 2006.173.23:15:24.49#ibcon#about to read 5, iclass 19, count 0 2006.173.23:15:24.49#ibcon#read 5, iclass 19, count 0 2006.173.23:15:24.49#ibcon#about to read 6, iclass 19, count 0 2006.173.23:15:24.49#ibcon#read 6, iclass 19, count 0 2006.173.23:15:24.49#ibcon#end of sib2, iclass 19, count 0 2006.173.23:15:24.49#ibcon#*mode == 0, iclass 19, count 0 2006.173.23:15:24.49#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.23:15:24.49#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.23:15:24.49#ibcon#*before write, iclass 19, count 0 2006.173.23:15:24.49#ibcon#enter sib2, iclass 19, count 0 2006.173.23:15:24.49#ibcon#flushed, iclass 19, count 0 2006.173.23:15:24.49#ibcon#about to write, iclass 19, count 0 2006.173.23:15:24.49#ibcon#wrote, iclass 19, count 0 2006.173.23:15:24.49#ibcon#about to read 3, iclass 19, count 0 2006.173.23:15:24.53#ibcon#read 3, iclass 19, count 0 2006.173.23:15:24.53#ibcon#about to read 4, iclass 19, count 0 2006.173.23:15:24.53#ibcon#read 4, iclass 19, count 0 2006.173.23:15:24.53#ibcon#about to read 5, iclass 19, count 0 2006.173.23:15:24.53#ibcon#read 5, iclass 19, count 0 2006.173.23:15:24.53#ibcon#about to read 6, iclass 19, count 0 2006.173.23:15:24.53#ibcon#read 6, iclass 19, count 0 2006.173.23:15:24.53#ibcon#end of sib2, iclass 19, count 0 2006.173.23:15:24.53#ibcon#*after write, iclass 19, count 0 2006.173.23:15:24.53#ibcon#*before return 0, iclass 19, count 0 2006.173.23:15:24.53#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.23:15:24.53#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.23:15:24.53#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.23:15:24.53#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.23:15:24.53$vck44/va=5,4 2006.173.23:15:24.53#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.23:15:24.53#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.23:15:24.53#ibcon#ireg 11 cls_cnt 2 2006.173.23:15:24.53#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.23:15:24.59#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.23:15:24.59#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.23:15:24.59#ibcon#enter wrdev, iclass 21, count 2 2006.173.23:15:24.59#ibcon#first serial, iclass 21, count 2 2006.173.23:15:24.59#ibcon#enter sib2, iclass 21, count 2 2006.173.23:15:24.59#ibcon#flushed, iclass 21, count 2 2006.173.23:15:24.59#ibcon#about to write, iclass 21, count 2 2006.173.23:15:24.59#ibcon#wrote, iclass 21, count 2 2006.173.23:15:24.59#ibcon#about to read 3, iclass 21, count 2 2006.173.23:15:24.61#ibcon#read 3, iclass 21, count 2 2006.173.23:15:24.61#ibcon#about to read 4, iclass 21, count 2 2006.173.23:15:24.61#ibcon#read 4, iclass 21, count 2 2006.173.23:15:24.61#ibcon#about to read 5, iclass 21, count 2 2006.173.23:15:24.61#ibcon#read 5, iclass 21, count 2 2006.173.23:15:24.61#ibcon#about to read 6, iclass 21, count 2 2006.173.23:15:24.61#ibcon#read 6, iclass 21, count 2 2006.173.23:15:24.61#ibcon#end of sib2, iclass 21, count 2 2006.173.23:15:24.61#ibcon#*mode == 0, iclass 21, count 2 2006.173.23:15:24.61#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.23:15:24.61#ibcon#[25=AT05-04\r\n] 2006.173.23:15:24.61#ibcon#*before write, iclass 21, count 2 2006.173.23:15:24.61#ibcon#enter sib2, iclass 21, count 2 2006.173.23:15:24.61#ibcon#flushed, iclass 21, count 2 2006.173.23:15:24.61#ibcon#about to write, iclass 21, count 2 2006.173.23:15:24.61#ibcon#wrote, iclass 21, count 2 2006.173.23:15:24.61#ibcon#about to read 3, iclass 21, count 2 2006.173.23:15:24.64#ibcon#read 3, iclass 21, count 2 2006.173.23:15:24.64#ibcon#about to read 4, iclass 21, count 2 2006.173.23:15:24.64#ibcon#read 4, iclass 21, count 2 2006.173.23:15:24.64#ibcon#about to read 5, iclass 21, count 2 2006.173.23:15:24.64#ibcon#read 5, iclass 21, count 2 2006.173.23:15:24.64#ibcon#about to read 6, iclass 21, count 2 2006.173.23:15:24.64#ibcon#read 6, iclass 21, count 2 2006.173.23:15:24.64#ibcon#end of sib2, iclass 21, count 2 2006.173.23:15:24.64#ibcon#*after write, iclass 21, count 2 2006.173.23:15:24.64#ibcon#*before return 0, iclass 21, count 2 2006.173.23:15:24.64#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.23:15:24.64#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.23:15:24.64#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.23:15:24.64#ibcon#ireg 7 cls_cnt 0 2006.173.23:15:24.64#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.23:15:24.76#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.23:15:24.76#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.23:15:24.76#ibcon#enter wrdev, iclass 21, count 0 2006.173.23:15:24.76#ibcon#first serial, iclass 21, count 0 2006.173.23:15:24.76#ibcon#enter sib2, iclass 21, count 0 2006.173.23:15:24.76#ibcon#flushed, iclass 21, count 0 2006.173.23:15:24.76#ibcon#about to write, iclass 21, count 0 2006.173.23:15:24.76#ibcon#wrote, iclass 21, count 0 2006.173.23:15:24.76#ibcon#about to read 3, iclass 21, count 0 2006.173.23:15:24.78#ibcon#read 3, iclass 21, count 0 2006.173.23:15:24.78#ibcon#about to read 4, iclass 21, count 0 2006.173.23:15:24.78#ibcon#read 4, iclass 21, count 0 2006.173.23:15:24.78#ibcon#about to read 5, iclass 21, count 0 2006.173.23:15:24.78#ibcon#read 5, iclass 21, count 0 2006.173.23:15:24.78#ibcon#about to read 6, iclass 21, count 0 2006.173.23:15:24.78#ibcon#read 6, iclass 21, count 0 2006.173.23:15:24.78#ibcon#end of sib2, iclass 21, count 0 2006.173.23:15:24.78#ibcon#*mode == 0, iclass 21, count 0 2006.173.23:15:24.78#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.23:15:24.78#ibcon#[25=USB\r\n] 2006.173.23:15:24.78#ibcon#*before write, iclass 21, count 0 2006.173.23:15:24.78#ibcon#enter sib2, iclass 21, count 0 2006.173.23:15:24.78#ibcon#flushed, iclass 21, count 0 2006.173.23:15:24.78#ibcon#about to write, iclass 21, count 0 2006.173.23:15:24.78#ibcon#wrote, iclass 21, count 0 2006.173.23:15:24.78#ibcon#about to read 3, iclass 21, count 0 2006.173.23:15:24.81#ibcon#read 3, iclass 21, count 0 2006.173.23:15:24.81#ibcon#about to read 4, iclass 21, count 0 2006.173.23:15:24.81#ibcon#read 4, iclass 21, count 0 2006.173.23:15:24.81#ibcon#about to read 5, iclass 21, count 0 2006.173.23:15:24.81#ibcon#read 5, iclass 21, count 0 2006.173.23:15:24.81#ibcon#about to read 6, iclass 21, count 0 2006.173.23:15:24.81#ibcon#read 6, iclass 21, count 0 2006.173.23:15:24.81#ibcon#end of sib2, iclass 21, count 0 2006.173.23:15:24.81#ibcon#*after write, iclass 21, count 0 2006.173.23:15:24.81#ibcon#*before return 0, iclass 21, count 0 2006.173.23:15:24.81#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.23:15:24.81#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.23:15:24.81#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.23:15:24.81#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.23:15:24.81$vck44/valo=6,814.99 2006.173.23:15:24.81#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.23:15:24.81#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.23:15:24.81#ibcon#ireg 17 cls_cnt 0 2006.173.23:15:24.81#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.23:15:24.81#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.23:15:24.81#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.23:15:24.81#ibcon#enter wrdev, iclass 23, count 0 2006.173.23:15:24.81#ibcon#first serial, iclass 23, count 0 2006.173.23:15:24.81#ibcon#enter sib2, iclass 23, count 0 2006.173.23:15:24.81#ibcon#flushed, iclass 23, count 0 2006.173.23:15:24.81#ibcon#about to write, iclass 23, count 0 2006.173.23:15:24.81#ibcon#wrote, iclass 23, count 0 2006.173.23:15:24.81#ibcon#about to read 3, iclass 23, count 0 2006.173.23:15:24.83#ibcon#read 3, iclass 23, count 0 2006.173.23:15:24.83#ibcon#about to read 4, iclass 23, count 0 2006.173.23:15:24.83#ibcon#read 4, iclass 23, count 0 2006.173.23:15:24.83#ibcon#about to read 5, iclass 23, count 0 2006.173.23:15:24.83#ibcon#read 5, iclass 23, count 0 2006.173.23:15:24.83#ibcon#about to read 6, iclass 23, count 0 2006.173.23:15:24.83#ibcon#read 6, iclass 23, count 0 2006.173.23:15:24.83#ibcon#end of sib2, iclass 23, count 0 2006.173.23:15:24.83#ibcon#*mode == 0, iclass 23, count 0 2006.173.23:15:24.83#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.23:15:24.83#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.23:15:24.83#ibcon#*before write, iclass 23, count 0 2006.173.23:15:24.83#ibcon#enter sib2, iclass 23, count 0 2006.173.23:15:24.83#ibcon#flushed, iclass 23, count 0 2006.173.23:15:24.83#ibcon#about to write, iclass 23, count 0 2006.173.23:15:24.83#ibcon#wrote, iclass 23, count 0 2006.173.23:15:24.83#ibcon#about to read 3, iclass 23, count 0 2006.173.23:15:24.87#ibcon#read 3, iclass 23, count 0 2006.173.23:15:24.87#ibcon#about to read 4, iclass 23, count 0 2006.173.23:15:24.87#ibcon#read 4, iclass 23, count 0 2006.173.23:15:24.87#ibcon#about to read 5, iclass 23, count 0 2006.173.23:15:24.87#ibcon#read 5, iclass 23, count 0 2006.173.23:15:24.87#ibcon#about to read 6, iclass 23, count 0 2006.173.23:15:24.87#ibcon#read 6, iclass 23, count 0 2006.173.23:15:24.87#ibcon#end of sib2, iclass 23, count 0 2006.173.23:15:24.87#ibcon#*after write, iclass 23, count 0 2006.173.23:15:24.87#ibcon#*before return 0, iclass 23, count 0 2006.173.23:15:24.87#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.23:15:24.87#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.23:15:24.87#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.23:15:24.87#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.23:15:24.87$vck44/va=6,3 2006.173.23:15:24.87#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.23:15:24.87#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.23:15:24.87#ibcon#ireg 11 cls_cnt 2 2006.173.23:15:24.87#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.23:15:24.93#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.23:15:24.93#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.23:15:24.93#ibcon#enter wrdev, iclass 25, count 2 2006.173.23:15:24.93#ibcon#first serial, iclass 25, count 2 2006.173.23:15:24.93#ibcon#enter sib2, iclass 25, count 2 2006.173.23:15:24.93#ibcon#flushed, iclass 25, count 2 2006.173.23:15:24.93#ibcon#about to write, iclass 25, count 2 2006.173.23:15:24.93#ibcon#wrote, iclass 25, count 2 2006.173.23:15:24.93#ibcon#about to read 3, iclass 25, count 2 2006.173.23:15:24.95#ibcon#read 3, iclass 25, count 2 2006.173.23:15:24.95#ibcon#about to read 4, iclass 25, count 2 2006.173.23:15:24.95#ibcon#read 4, iclass 25, count 2 2006.173.23:15:24.95#ibcon#about to read 5, iclass 25, count 2 2006.173.23:15:24.95#ibcon#read 5, iclass 25, count 2 2006.173.23:15:24.95#ibcon#about to read 6, iclass 25, count 2 2006.173.23:15:24.95#ibcon#read 6, iclass 25, count 2 2006.173.23:15:24.95#ibcon#end of sib2, iclass 25, count 2 2006.173.23:15:24.95#ibcon#*mode == 0, iclass 25, count 2 2006.173.23:15:24.95#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.23:15:24.95#ibcon#[25=AT06-03\r\n] 2006.173.23:15:24.95#ibcon#*before write, iclass 25, count 2 2006.173.23:15:24.95#ibcon#enter sib2, iclass 25, count 2 2006.173.23:15:24.95#ibcon#flushed, iclass 25, count 2 2006.173.23:15:24.95#ibcon#about to write, iclass 25, count 2 2006.173.23:15:24.95#ibcon#wrote, iclass 25, count 2 2006.173.23:15:24.95#ibcon#about to read 3, iclass 25, count 2 2006.173.23:15:24.98#ibcon#read 3, iclass 25, count 2 2006.173.23:15:24.98#ibcon#about to read 4, iclass 25, count 2 2006.173.23:15:24.98#ibcon#read 4, iclass 25, count 2 2006.173.23:15:24.98#ibcon#about to read 5, iclass 25, count 2 2006.173.23:15:24.98#ibcon#read 5, iclass 25, count 2 2006.173.23:15:24.98#ibcon#about to read 6, iclass 25, count 2 2006.173.23:15:24.98#ibcon#read 6, iclass 25, count 2 2006.173.23:15:24.98#ibcon#end of sib2, iclass 25, count 2 2006.173.23:15:24.98#ibcon#*after write, iclass 25, count 2 2006.173.23:15:24.98#ibcon#*before return 0, iclass 25, count 2 2006.173.23:15:24.98#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.23:15:24.98#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.23:15:24.98#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.23:15:24.98#ibcon#ireg 7 cls_cnt 0 2006.173.23:15:24.98#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.23:15:25.10#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.23:15:25.10#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.23:15:25.10#ibcon#enter wrdev, iclass 25, count 0 2006.173.23:15:25.10#ibcon#first serial, iclass 25, count 0 2006.173.23:15:25.10#ibcon#enter sib2, iclass 25, count 0 2006.173.23:15:25.10#ibcon#flushed, iclass 25, count 0 2006.173.23:15:25.10#ibcon#about to write, iclass 25, count 0 2006.173.23:15:25.10#ibcon#wrote, iclass 25, count 0 2006.173.23:15:25.10#ibcon#about to read 3, iclass 25, count 0 2006.173.23:15:25.12#ibcon#read 3, iclass 25, count 0 2006.173.23:15:25.12#ibcon#about to read 4, iclass 25, count 0 2006.173.23:15:25.12#ibcon#read 4, iclass 25, count 0 2006.173.23:15:25.12#ibcon#about to read 5, iclass 25, count 0 2006.173.23:15:25.12#ibcon#read 5, iclass 25, count 0 2006.173.23:15:25.12#ibcon#about to read 6, iclass 25, count 0 2006.173.23:15:25.12#ibcon#read 6, iclass 25, count 0 2006.173.23:15:25.12#ibcon#end of sib2, iclass 25, count 0 2006.173.23:15:25.12#ibcon#*mode == 0, iclass 25, count 0 2006.173.23:15:25.12#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.23:15:25.12#ibcon#[25=USB\r\n] 2006.173.23:15:25.12#ibcon#*before write, iclass 25, count 0 2006.173.23:15:25.12#ibcon#enter sib2, iclass 25, count 0 2006.173.23:15:25.12#ibcon#flushed, iclass 25, count 0 2006.173.23:15:25.12#ibcon#about to write, iclass 25, count 0 2006.173.23:15:25.12#ibcon#wrote, iclass 25, count 0 2006.173.23:15:25.12#ibcon#about to read 3, iclass 25, count 0 2006.173.23:15:25.15#ibcon#read 3, iclass 25, count 0 2006.173.23:15:25.15#ibcon#about to read 4, iclass 25, count 0 2006.173.23:15:25.15#ibcon#read 4, iclass 25, count 0 2006.173.23:15:25.15#ibcon#about to read 5, iclass 25, count 0 2006.173.23:15:25.15#ibcon#read 5, iclass 25, count 0 2006.173.23:15:25.15#ibcon#about to read 6, iclass 25, count 0 2006.173.23:15:25.15#ibcon#read 6, iclass 25, count 0 2006.173.23:15:25.15#ibcon#end of sib2, iclass 25, count 0 2006.173.23:15:25.15#ibcon#*after write, iclass 25, count 0 2006.173.23:15:25.15#ibcon#*before return 0, iclass 25, count 0 2006.173.23:15:25.15#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.23:15:25.15#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.23:15:25.15#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.23:15:25.15#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.23:15:25.15$vck44/valo=7,864.99 2006.173.23:15:25.15#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.23:15:25.15#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.23:15:25.15#ibcon#ireg 17 cls_cnt 0 2006.173.23:15:25.15#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.23:15:25.15#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.23:15:25.15#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.23:15:25.15#ibcon#enter wrdev, iclass 27, count 0 2006.173.23:15:25.15#ibcon#first serial, iclass 27, count 0 2006.173.23:15:25.15#ibcon#enter sib2, iclass 27, count 0 2006.173.23:15:25.15#ibcon#flushed, iclass 27, count 0 2006.173.23:15:25.15#ibcon#about to write, iclass 27, count 0 2006.173.23:15:25.15#ibcon#wrote, iclass 27, count 0 2006.173.23:15:25.15#ibcon#about to read 3, iclass 27, count 0 2006.173.23:15:25.17#ibcon#read 3, iclass 27, count 0 2006.173.23:15:25.17#ibcon#about to read 4, iclass 27, count 0 2006.173.23:15:25.17#ibcon#read 4, iclass 27, count 0 2006.173.23:15:25.17#ibcon#about to read 5, iclass 27, count 0 2006.173.23:15:25.17#ibcon#read 5, iclass 27, count 0 2006.173.23:15:25.17#ibcon#about to read 6, iclass 27, count 0 2006.173.23:15:25.17#ibcon#read 6, iclass 27, count 0 2006.173.23:15:25.17#ibcon#end of sib2, iclass 27, count 0 2006.173.23:15:25.17#ibcon#*mode == 0, iclass 27, count 0 2006.173.23:15:25.17#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.23:15:25.17#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.23:15:25.17#ibcon#*before write, iclass 27, count 0 2006.173.23:15:25.17#ibcon#enter sib2, iclass 27, count 0 2006.173.23:15:25.17#ibcon#flushed, iclass 27, count 0 2006.173.23:15:25.17#ibcon#about to write, iclass 27, count 0 2006.173.23:15:25.17#ibcon#wrote, iclass 27, count 0 2006.173.23:15:25.17#ibcon#about to read 3, iclass 27, count 0 2006.173.23:15:25.21#ibcon#read 3, iclass 27, count 0 2006.173.23:15:25.21#ibcon#about to read 4, iclass 27, count 0 2006.173.23:15:25.21#ibcon#read 4, iclass 27, count 0 2006.173.23:15:25.21#ibcon#about to read 5, iclass 27, count 0 2006.173.23:15:25.21#ibcon#read 5, iclass 27, count 0 2006.173.23:15:25.21#ibcon#about to read 6, iclass 27, count 0 2006.173.23:15:25.21#ibcon#read 6, iclass 27, count 0 2006.173.23:15:25.21#ibcon#end of sib2, iclass 27, count 0 2006.173.23:15:25.21#ibcon#*after write, iclass 27, count 0 2006.173.23:15:25.21#ibcon#*before return 0, iclass 27, count 0 2006.173.23:15:25.21#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.23:15:25.21#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.23:15:25.21#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.23:15:25.21#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.23:15:25.21$vck44/va=7,4 2006.173.23:15:25.21#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.23:15:25.21#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.23:15:25.21#ibcon#ireg 11 cls_cnt 2 2006.173.23:15:25.21#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.23:15:25.27#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.23:15:25.27#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.23:15:25.27#ibcon#enter wrdev, iclass 29, count 2 2006.173.23:15:25.27#ibcon#first serial, iclass 29, count 2 2006.173.23:15:25.27#ibcon#enter sib2, iclass 29, count 2 2006.173.23:15:25.27#ibcon#flushed, iclass 29, count 2 2006.173.23:15:25.27#ibcon#about to write, iclass 29, count 2 2006.173.23:15:25.27#ibcon#wrote, iclass 29, count 2 2006.173.23:15:25.27#ibcon#about to read 3, iclass 29, count 2 2006.173.23:15:25.29#ibcon#read 3, iclass 29, count 2 2006.173.23:15:25.29#ibcon#about to read 4, iclass 29, count 2 2006.173.23:15:25.29#ibcon#read 4, iclass 29, count 2 2006.173.23:15:25.29#ibcon#about to read 5, iclass 29, count 2 2006.173.23:15:25.29#ibcon#read 5, iclass 29, count 2 2006.173.23:15:25.29#ibcon#about to read 6, iclass 29, count 2 2006.173.23:15:25.29#ibcon#read 6, iclass 29, count 2 2006.173.23:15:25.29#ibcon#end of sib2, iclass 29, count 2 2006.173.23:15:25.29#ibcon#*mode == 0, iclass 29, count 2 2006.173.23:15:25.29#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.23:15:25.29#ibcon#[25=AT07-04\r\n] 2006.173.23:15:25.29#ibcon#*before write, iclass 29, count 2 2006.173.23:15:25.29#ibcon#enter sib2, iclass 29, count 2 2006.173.23:15:25.29#ibcon#flushed, iclass 29, count 2 2006.173.23:15:25.29#ibcon#about to write, iclass 29, count 2 2006.173.23:15:25.29#ibcon#wrote, iclass 29, count 2 2006.173.23:15:25.29#ibcon#about to read 3, iclass 29, count 2 2006.173.23:15:25.32#ibcon#read 3, iclass 29, count 2 2006.173.23:15:25.32#ibcon#about to read 4, iclass 29, count 2 2006.173.23:15:25.32#ibcon#read 4, iclass 29, count 2 2006.173.23:15:25.32#ibcon#about to read 5, iclass 29, count 2 2006.173.23:15:25.32#ibcon#read 5, iclass 29, count 2 2006.173.23:15:25.32#ibcon#about to read 6, iclass 29, count 2 2006.173.23:15:25.32#ibcon#read 6, iclass 29, count 2 2006.173.23:15:25.32#ibcon#end of sib2, iclass 29, count 2 2006.173.23:15:25.32#ibcon#*after write, iclass 29, count 2 2006.173.23:15:25.32#ibcon#*before return 0, iclass 29, count 2 2006.173.23:15:25.32#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.23:15:25.32#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.23:15:25.32#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.23:15:25.32#ibcon#ireg 7 cls_cnt 0 2006.173.23:15:25.32#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.23:15:25.44#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.23:15:25.44#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.23:15:25.44#ibcon#enter wrdev, iclass 29, count 0 2006.173.23:15:25.44#ibcon#first serial, iclass 29, count 0 2006.173.23:15:25.44#ibcon#enter sib2, iclass 29, count 0 2006.173.23:15:25.44#ibcon#flushed, iclass 29, count 0 2006.173.23:15:25.44#ibcon#about to write, iclass 29, count 0 2006.173.23:15:25.44#ibcon#wrote, iclass 29, count 0 2006.173.23:15:25.44#ibcon#about to read 3, iclass 29, count 0 2006.173.23:15:25.46#ibcon#read 3, iclass 29, count 0 2006.173.23:15:25.46#ibcon#about to read 4, iclass 29, count 0 2006.173.23:15:25.46#ibcon#read 4, iclass 29, count 0 2006.173.23:15:25.46#ibcon#about to read 5, iclass 29, count 0 2006.173.23:15:25.46#ibcon#read 5, iclass 29, count 0 2006.173.23:15:25.46#ibcon#about to read 6, iclass 29, count 0 2006.173.23:15:25.46#ibcon#read 6, iclass 29, count 0 2006.173.23:15:25.46#ibcon#end of sib2, iclass 29, count 0 2006.173.23:15:25.46#ibcon#*mode == 0, iclass 29, count 0 2006.173.23:15:25.46#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.23:15:25.46#ibcon#[25=USB\r\n] 2006.173.23:15:25.46#ibcon#*before write, iclass 29, count 0 2006.173.23:15:25.46#ibcon#enter sib2, iclass 29, count 0 2006.173.23:15:25.46#ibcon#flushed, iclass 29, count 0 2006.173.23:15:25.46#ibcon#about to write, iclass 29, count 0 2006.173.23:15:25.46#ibcon#wrote, iclass 29, count 0 2006.173.23:15:25.46#ibcon#about to read 3, iclass 29, count 0 2006.173.23:15:25.49#ibcon#read 3, iclass 29, count 0 2006.173.23:15:25.49#ibcon#about to read 4, iclass 29, count 0 2006.173.23:15:25.49#ibcon#read 4, iclass 29, count 0 2006.173.23:15:25.49#ibcon#about to read 5, iclass 29, count 0 2006.173.23:15:25.49#ibcon#read 5, iclass 29, count 0 2006.173.23:15:25.49#ibcon#about to read 6, iclass 29, count 0 2006.173.23:15:25.49#ibcon#read 6, iclass 29, count 0 2006.173.23:15:25.49#ibcon#end of sib2, iclass 29, count 0 2006.173.23:15:25.49#ibcon#*after write, iclass 29, count 0 2006.173.23:15:25.49#ibcon#*before return 0, iclass 29, count 0 2006.173.23:15:25.49#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.23:15:25.49#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.23:15:25.49#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.23:15:25.49#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.23:15:25.49$vck44/valo=8,884.99 2006.173.23:15:25.49#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.23:15:25.49#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.23:15:25.49#ibcon#ireg 17 cls_cnt 0 2006.173.23:15:25.49#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.23:15:25.49#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.23:15:25.49#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.23:15:25.49#ibcon#enter wrdev, iclass 31, count 0 2006.173.23:15:25.49#ibcon#first serial, iclass 31, count 0 2006.173.23:15:25.49#ibcon#enter sib2, iclass 31, count 0 2006.173.23:15:25.49#ibcon#flushed, iclass 31, count 0 2006.173.23:15:25.49#ibcon#about to write, iclass 31, count 0 2006.173.23:15:25.49#ibcon#wrote, iclass 31, count 0 2006.173.23:15:25.49#ibcon#about to read 3, iclass 31, count 0 2006.173.23:15:25.51#ibcon#read 3, iclass 31, count 0 2006.173.23:15:25.51#ibcon#about to read 4, iclass 31, count 0 2006.173.23:15:25.51#ibcon#read 4, iclass 31, count 0 2006.173.23:15:25.51#ibcon#about to read 5, iclass 31, count 0 2006.173.23:15:25.51#ibcon#read 5, iclass 31, count 0 2006.173.23:15:25.51#ibcon#about to read 6, iclass 31, count 0 2006.173.23:15:25.51#ibcon#read 6, iclass 31, count 0 2006.173.23:15:25.51#ibcon#end of sib2, iclass 31, count 0 2006.173.23:15:25.51#ibcon#*mode == 0, iclass 31, count 0 2006.173.23:15:25.51#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.23:15:25.51#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.23:15:25.51#ibcon#*before write, iclass 31, count 0 2006.173.23:15:25.51#ibcon#enter sib2, iclass 31, count 0 2006.173.23:15:25.51#ibcon#flushed, iclass 31, count 0 2006.173.23:15:25.51#ibcon#about to write, iclass 31, count 0 2006.173.23:15:25.51#ibcon#wrote, iclass 31, count 0 2006.173.23:15:25.51#ibcon#about to read 3, iclass 31, count 0 2006.173.23:15:25.55#ibcon#read 3, iclass 31, count 0 2006.173.23:15:25.55#ibcon#about to read 4, iclass 31, count 0 2006.173.23:15:25.55#ibcon#read 4, iclass 31, count 0 2006.173.23:15:25.55#ibcon#about to read 5, iclass 31, count 0 2006.173.23:15:25.55#ibcon#read 5, iclass 31, count 0 2006.173.23:15:25.55#ibcon#about to read 6, iclass 31, count 0 2006.173.23:15:25.55#ibcon#read 6, iclass 31, count 0 2006.173.23:15:25.55#ibcon#end of sib2, iclass 31, count 0 2006.173.23:15:25.55#ibcon#*after write, iclass 31, count 0 2006.173.23:15:25.55#ibcon#*before return 0, iclass 31, count 0 2006.173.23:15:25.55#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.23:15:25.55#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.23:15:25.55#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.23:15:25.55#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.23:15:25.55$vck44/va=8,4 2006.173.23:15:25.55#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.173.23:15:25.55#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.173.23:15:25.55#ibcon#ireg 11 cls_cnt 2 2006.173.23:15:25.55#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.23:15:25.61#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.23:15:25.61#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.23:15:25.61#ibcon#enter wrdev, iclass 33, count 2 2006.173.23:15:25.61#ibcon#first serial, iclass 33, count 2 2006.173.23:15:25.61#ibcon#enter sib2, iclass 33, count 2 2006.173.23:15:25.61#ibcon#flushed, iclass 33, count 2 2006.173.23:15:25.61#ibcon#about to write, iclass 33, count 2 2006.173.23:15:25.61#ibcon#wrote, iclass 33, count 2 2006.173.23:15:25.61#ibcon#about to read 3, iclass 33, count 2 2006.173.23:15:25.63#ibcon#read 3, iclass 33, count 2 2006.173.23:15:25.63#ibcon#about to read 4, iclass 33, count 2 2006.173.23:15:25.63#ibcon#read 4, iclass 33, count 2 2006.173.23:15:25.63#ibcon#about to read 5, iclass 33, count 2 2006.173.23:15:25.63#ibcon#read 5, iclass 33, count 2 2006.173.23:15:25.63#ibcon#about to read 6, iclass 33, count 2 2006.173.23:15:25.63#ibcon#read 6, iclass 33, count 2 2006.173.23:15:25.63#ibcon#end of sib2, iclass 33, count 2 2006.173.23:15:25.63#ibcon#*mode == 0, iclass 33, count 2 2006.173.23:15:25.63#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.173.23:15:25.63#ibcon#[25=AT08-04\r\n] 2006.173.23:15:25.63#ibcon#*before write, iclass 33, count 2 2006.173.23:15:25.63#ibcon#enter sib2, iclass 33, count 2 2006.173.23:15:25.63#ibcon#flushed, iclass 33, count 2 2006.173.23:15:25.63#ibcon#about to write, iclass 33, count 2 2006.173.23:15:25.63#ibcon#wrote, iclass 33, count 2 2006.173.23:15:25.63#ibcon#about to read 3, iclass 33, count 2 2006.173.23:15:25.66#ibcon#read 3, iclass 33, count 2 2006.173.23:15:25.66#ibcon#about to read 4, iclass 33, count 2 2006.173.23:15:25.66#ibcon#read 4, iclass 33, count 2 2006.173.23:15:25.66#ibcon#about to read 5, iclass 33, count 2 2006.173.23:15:25.66#ibcon#read 5, iclass 33, count 2 2006.173.23:15:25.66#ibcon#about to read 6, iclass 33, count 2 2006.173.23:15:25.66#ibcon#read 6, iclass 33, count 2 2006.173.23:15:25.66#ibcon#end of sib2, iclass 33, count 2 2006.173.23:15:25.66#ibcon#*after write, iclass 33, count 2 2006.173.23:15:25.66#ibcon#*before return 0, iclass 33, count 2 2006.173.23:15:25.66#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.23:15:25.66#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.173.23:15:25.66#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.173.23:15:25.66#ibcon#ireg 7 cls_cnt 0 2006.173.23:15:25.66#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.23:15:25.78#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.23:15:25.78#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.23:15:25.78#ibcon#enter wrdev, iclass 33, count 0 2006.173.23:15:25.78#ibcon#first serial, iclass 33, count 0 2006.173.23:15:25.78#ibcon#enter sib2, iclass 33, count 0 2006.173.23:15:25.78#ibcon#flushed, iclass 33, count 0 2006.173.23:15:25.78#ibcon#about to write, iclass 33, count 0 2006.173.23:15:25.78#ibcon#wrote, iclass 33, count 0 2006.173.23:15:25.78#ibcon#about to read 3, iclass 33, count 0 2006.173.23:15:25.80#ibcon#read 3, iclass 33, count 0 2006.173.23:15:25.80#ibcon#about to read 4, iclass 33, count 0 2006.173.23:15:25.80#ibcon#read 4, iclass 33, count 0 2006.173.23:15:25.80#ibcon#about to read 5, iclass 33, count 0 2006.173.23:15:25.80#ibcon#read 5, iclass 33, count 0 2006.173.23:15:25.80#ibcon#about to read 6, iclass 33, count 0 2006.173.23:15:25.80#ibcon#read 6, iclass 33, count 0 2006.173.23:15:25.80#ibcon#end of sib2, iclass 33, count 0 2006.173.23:15:25.80#ibcon#*mode == 0, iclass 33, count 0 2006.173.23:15:25.80#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.23:15:25.80#ibcon#[25=USB\r\n] 2006.173.23:15:25.80#ibcon#*before write, iclass 33, count 0 2006.173.23:15:25.80#ibcon#enter sib2, iclass 33, count 0 2006.173.23:15:25.80#ibcon#flushed, iclass 33, count 0 2006.173.23:15:25.80#ibcon#about to write, iclass 33, count 0 2006.173.23:15:25.80#ibcon#wrote, iclass 33, count 0 2006.173.23:15:25.80#ibcon#about to read 3, iclass 33, count 0 2006.173.23:15:25.83#ibcon#read 3, iclass 33, count 0 2006.173.23:15:25.83#ibcon#about to read 4, iclass 33, count 0 2006.173.23:15:25.83#ibcon#read 4, iclass 33, count 0 2006.173.23:15:25.83#ibcon#about to read 5, iclass 33, count 0 2006.173.23:15:25.83#ibcon#read 5, iclass 33, count 0 2006.173.23:15:25.83#ibcon#about to read 6, iclass 33, count 0 2006.173.23:15:25.83#ibcon#read 6, iclass 33, count 0 2006.173.23:15:25.83#ibcon#end of sib2, iclass 33, count 0 2006.173.23:15:25.83#ibcon#*after write, iclass 33, count 0 2006.173.23:15:25.83#ibcon#*before return 0, iclass 33, count 0 2006.173.23:15:25.83#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.23:15:25.83#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.173.23:15:25.83#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.23:15:25.83#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.23:15:25.83$vck44/vblo=1,629.99 2006.173.23:15:25.83#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.23:15:25.83#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.23:15:25.83#ibcon#ireg 17 cls_cnt 0 2006.173.23:15:25.83#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.23:15:25.83#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.23:15:25.83#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.23:15:25.83#ibcon#enter wrdev, iclass 35, count 0 2006.173.23:15:25.83#ibcon#first serial, iclass 35, count 0 2006.173.23:15:25.83#ibcon#enter sib2, iclass 35, count 0 2006.173.23:15:25.83#ibcon#flushed, iclass 35, count 0 2006.173.23:15:25.83#ibcon#about to write, iclass 35, count 0 2006.173.23:15:25.83#ibcon#wrote, iclass 35, count 0 2006.173.23:15:25.83#ibcon#about to read 3, iclass 35, count 0 2006.173.23:15:25.85#ibcon#read 3, iclass 35, count 0 2006.173.23:15:25.85#ibcon#about to read 4, iclass 35, count 0 2006.173.23:15:25.85#ibcon#read 4, iclass 35, count 0 2006.173.23:15:25.85#ibcon#about to read 5, iclass 35, count 0 2006.173.23:15:25.85#ibcon#read 5, iclass 35, count 0 2006.173.23:15:25.85#ibcon#about to read 6, iclass 35, count 0 2006.173.23:15:25.85#ibcon#read 6, iclass 35, count 0 2006.173.23:15:25.85#ibcon#end of sib2, iclass 35, count 0 2006.173.23:15:25.85#ibcon#*mode == 0, iclass 35, count 0 2006.173.23:15:25.85#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.23:15:25.85#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.23:15:25.85#ibcon#*before write, iclass 35, count 0 2006.173.23:15:25.85#ibcon#enter sib2, iclass 35, count 0 2006.173.23:15:25.85#ibcon#flushed, iclass 35, count 0 2006.173.23:15:25.85#ibcon#about to write, iclass 35, count 0 2006.173.23:15:25.85#ibcon#wrote, iclass 35, count 0 2006.173.23:15:25.85#ibcon#about to read 3, iclass 35, count 0 2006.173.23:15:25.89#ibcon#read 3, iclass 35, count 0 2006.173.23:15:25.89#ibcon#about to read 4, iclass 35, count 0 2006.173.23:15:25.89#ibcon#read 4, iclass 35, count 0 2006.173.23:15:25.89#ibcon#about to read 5, iclass 35, count 0 2006.173.23:15:25.89#ibcon#read 5, iclass 35, count 0 2006.173.23:15:25.89#ibcon#about to read 6, iclass 35, count 0 2006.173.23:15:25.89#ibcon#read 6, iclass 35, count 0 2006.173.23:15:25.89#ibcon#end of sib2, iclass 35, count 0 2006.173.23:15:25.89#ibcon#*after write, iclass 35, count 0 2006.173.23:15:25.89#ibcon#*before return 0, iclass 35, count 0 2006.173.23:15:25.89#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.23:15:25.89#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.23:15:25.89#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.23:15:25.89#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.23:15:25.89$vck44/vb=1,4 2006.173.23:15:25.89#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.173.23:15:25.89#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.173.23:15:25.89#ibcon#ireg 11 cls_cnt 2 2006.173.23:15:25.89#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.23:15:25.89#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.23:15:25.89#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.23:15:25.89#ibcon#enter wrdev, iclass 37, count 2 2006.173.23:15:25.89#ibcon#first serial, iclass 37, count 2 2006.173.23:15:25.89#ibcon#enter sib2, iclass 37, count 2 2006.173.23:15:25.89#ibcon#flushed, iclass 37, count 2 2006.173.23:15:25.89#ibcon#about to write, iclass 37, count 2 2006.173.23:15:25.89#ibcon#wrote, iclass 37, count 2 2006.173.23:15:25.89#ibcon#about to read 3, iclass 37, count 2 2006.173.23:15:25.91#ibcon#read 3, iclass 37, count 2 2006.173.23:15:25.91#ibcon#about to read 4, iclass 37, count 2 2006.173.23:15:25.91#ibcon#read 4, iclass 37, count 2 2006.173.23:15:25.91#ibcon#about to read 5, iclass 37, count 2 2006.173.23:15:25.91#ibcon#read 5, iclass 37, count 2 2006.173.23:15:25.91#ibcon#about to read 6, iclass 37, count 2 2006.173.23:15:25.91#ibcon#read 6, iclass 37, count 2 2006.173.23:15:25.91#ibcon#end of sib2, iclass 37, count 2 2006.173.23:15:25.91#ibcon#*mode == 0, iclass 37, count 2 2006.173.23:15:25.91#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.173.23:15:25.91#ibcon#[27=AT01-04\r\n] 2006.173.23:15:25.91#ibcon#*before write, iclass 37, count 2 2006.173.23:15:25.91#ibcon#enter sib2, iclass 37, count 2 2006.173.23:15:25.91#ibcon#flushed, iclass 37, count 2 2006.173.23:15:25.91#ibcon#about to write, iclass 37, count 2 2006.173.23:15:25.91#ibcon#wrote, iclass 37, count 2 2006.173.23:15:25.91#ibcon#about to read 3, iclass 37, count 2 2006.173.23:15:25.94#ibcon#read 3, iclass 37, count 2 2006.173.23:15:25.94#ibcon#about to read 4, iclass 37, count 2 2006.173.23:15:25.94#ibcon#read 4, iclass 37, count 2 2006.173.23:15:25.94#ibcon#about to read 5, iclass 37, count 2 2006.173.23:15:25.94#ibcon#read 5, iclass 37, count 2 2006.173.23:15:25.94#ibcon#about to read 6, iclass 37, count 2 2006.173.23:15:25.94#ibcon#read 6, iclass 37, count 2 2006.173.23:15:25.94#ibcon#end of sib2, iclass 37, count 2 2006.173.23:15:25.94#ibcon#*after write, iclass 37, count 2 2006.173.23:15:25.94#ibcon#*before return 0, iclass 37, count 2 2006.173.23:15:25.94#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.23:15:25.94#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.173.23:15:25.94#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.173.23:15:25.94#ibcon#ireg 7 cls_cnt 0 2006.173.23:15:25.94#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.23:15:26.06#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.23:15:26.06#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.23:15:26.06#ibcon#enter wrdev, iclass 37, count 0 2006.173.23:15:26.06#ibcon#first serial, iclass 37, count 0 2006.173.23:15:26.06#ibcon#enter sib2, iclass 37, count 0 2006.173.23:15:26.06#ibcon#flushed, iclass 37, count 0 2006.173.23:15:26.06#ibcon#about to write, iclass 37, count 0 2006.173.23:15:26.06#ibcon#wrote, iclass 37, count 0 2006.173.23:15:26.06#ibcon#about to read 3, iclass 37, count 0 2006.173.23:15:26.08#ibcon#read 3, iclass 37, count 0 2006.173.23:15:26.08#ibcon#about to read 4, iclass 37, count 0 2006.173.23:15:26.08#ibcon#read 4, iclass 37, count 0 2006.173.23:15:26.08#ibcon#about to read 5, iclass 37, count 0 2006.173.23:15:26.08#ibcon#read 5, iclass 37, count 0 2006.173.23:15:26.08#ibcon#about to read 6, iclass 37, count 0 2006.173.23:15:26.08#ibcon#read 6, iclass 37, count 0 2006.173.23:15:26.08#ibcon#end of sib2, iclass 37, count 0 2006.173.23:15:26.08#ibcon#*mode == 0, iclass 37, count 0 2006.173.23:15:26.08#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.23:15:26.08#ibcon#[27=USB\r\n] 2006.173.23:15:26.08#ibcon#*before write, iclass 37, count 0 2006.173.23:15:26.08#ibcon#enter sib2, iclass 37, count 0 2006.173.23:15:26.08#ibcon#flushed, iclass 37, count 0 2006.173.23:15:26.08#ibcon#about to write, iclass 37, count 0 2006.173.23:15:26.08#ibcon#wrote, iclass 37, count 0 2006.173.23:15:26.08#ibcon#about to read 3, iclass 37, count 0 2006.173.23:15:26.11#ibcon#read 3, iclass 37, count 0 2006.173.23:15:26.11#ibcon#about to read 4, iclass 37, count 0 2006.173.23:15:26.11#ibcon#read 4, iclass 37, count 0 2006.173.23:15:26.11#ibcon#about to read 5, iclass 37, count 0 2006.173.23:15:26.11#ibcon#read 5, iclass 37, count 0 2006.173.23:15:26.11#ibcon#about to read 6, iclass 37, count 0 2006.173.23:15:26.11#ibcon#read 6, iclass 37, count 0 2006.173.23:15:26.11#ibcon#end of sib2, iclass 37, count 0 2006.173.23:15:26.11#ibcon#*after write, iclass 37, count 0 2006.173.23:15:26.11#ibcon#*before return 0, iclass 37, count 0 2006.173.23:15:26.11#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.23:15:26.11#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.173.23:15:26.11#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.23:15:26.11#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.23:15:26.11$vck44/vblo=2,634.99 2006.173.23:15:26.11#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.23:15:26.11#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.23:15:26.11#ibcon#ireg 17 cls_cnt 0 2006.173.23:15:26.11#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.23:15:26.11#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.23:15:26.11#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.23:15:26.11#ibcon#enter wrdev, iclass 39, count 0 2006.173.23:15:26.11#ibcon#first serial, iclass 39, count 0 2006.173.23:15:26.11#ibcon#enter sib2, iclass 39, count 0 2006.173.23:15:26.11#ibcon#flushed, iclass 39, count 0 2006.173.23:15:26.11#ibcon#about to write, iclass 39, count 0 2006.173.23:15:26.11#ibcon#wrote, iclass 39, count 0 2006.173.23:15:26.11#ibcon#about to read 3, iclass 39, count 0 2006.173.23:15:26.13#ibcon#read 3, iclass 39, count 0 2006.173.23:15:26.13#ibcon#about to read 4, iclass 39, count 0 2006.173.23:15:26.13#ibcon#read 4, iclass 39, count 0 2006.173.23:15:26.13#ibcon#about to read 5, iclass 39, count 0 2006.173.23:15:26.13#ibcon#read 5, iclass 39, count 0 2006.173.23:15:26.13#ibcon#about to read 6, iclass 39, count 0 2006.173.23:15:26.13#ibcon#read 6, iclass 39, count 0 2006.173.23:15:26.13#ibcon#end of sib2, iclass 39, count 0 2006.173.23:15:26.13#ibcon#*mode == 0, iclass 39, count 0 2006.173.23:15:26.13#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.23:15:26.13#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.23:15:26.13#ibcon#*before write, iclass 39, count 0 2006.173.23:15:26.13#ibcon#enter sib2, iclass 39, count 0 2006.173.23:15:26.13#ibcon#flushed, iclass 39, count 0 2006.173.23:15:26.13#ibcon#about to write, iclass 39, count 0 2006.173.23:15:26.13#ibcon#wrote, iclass 39, count 0 2006.173.23:15:26.13#ibcon#about to read 3, iclass 39, count 0 2006.173.23:15:26.17#ibcon#read 3, iclass 39, count 0 2006.173.23:15:26.17#ibcon#about to read 4, iclass 39, count 0 2006.173.23:15:26.17#ibcon#read 4, iclass 39, count 0 2006.173.23:15:26.17#ibcon#about to read 5, iclass 39, count 0 2006.173.23:15:26.17#ibcon#read 5, iclass 39, count 0 2006.173.23:15:26.17#ibcon#about to read 6, iclass 39, count 0 2006.173.23:15:26.17#ibcon#read 6, iclass 39, count 0 2006.173.23:15:26.17#ibcon#end of sib2, iclass 39, count 0 2006.173.23:15:26.17#ibcon#*after write, iclass 39, count 0 2006.173.23:15:26.17#ibcon#*before return 0, iclass 39, count 0 2006.173.23:15:26.17#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.23:15:26.17#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.23:15:26.17#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.23:15:26.17#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.23:15:26.17$vck44/vb=2,4 2006.173.23:15:26.17#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.23:15:26.17#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.23:15:26.17#ibcon#ireg 11 cls_cnt 2 2006.173.23:15:26.17#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.23:15:26.23#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.23:15:26.23#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.23:15:26.23#ibcon#enter wrdev, iclass 3, count 2 2006.173.23:15:26.23#ibcon#first serial, iclass 3, count 2 2006.173.23:15:26.23#ibcon#enter sib2, iclass 3, count 2 2006.173.23:15:26.23#ibcon#flushed, iclass 3, count 2 2006.173.23:15:26.23#ibcon#about to write, iclass 3, count 2 2006.173.23:15:26.23#ibcon#wrote, iclass 3, count 2 2006.173.23:15:26.23#ibcon#about to read 3, iclass 3, count 2 2006.173.23:15:26.25#ibcon#read 3, iclass 3, count 2 2006.173.23:15:26.25#ibcon#about to read 4, iclass 3, count 2 2006.173.23:15:26.25#ibcon#read 4, iclass 3, count 2 2006.173.23:15:26.25#ibcon#about to read 5, iclass 3, count 2 2006.173.23:15:26.25#ibcon#read 5, iclass 3, count 2 2006.173.23:15:26.25#ibcon#about to read 6, iclass 3, count 2 2006.173.23:15:26.25#ibcon#read 6, iclass 3, count 2 2006.173.23:15:26.25#ibcon#end of sib2, iclass 3, count 2 2006.173.23:15:26.25#ibcon#*mode == 0, iclass 3, count 2 2006.173.23:15:26.25#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.23:15:26.25#ibcon#[27=AT02-04\r\n] 2006.173.23:15:26.25#ibcon#*before write, iclass 3, count 2 2006.173.23:15:26.25#ibcon#enter sib2, iclass 3, count 2 2006.173.23:15:26.25#ibcon#flushed, iclass 3, count 2 2006.173.23:15:26.25#ibcon#about to write, iclass 3, count 2 2006.173.23:15:26.25#ibcon#wrote, iclass 3, count 2 2006.173.23:15:26.25#ibcon#about to read 3, iclass 3, count 2 2006.173.23:15:26.28#ibcon#read 3, iclass 3, count 2 2006.173.23:15:26.28#ibcon#about to read 4, iclass 3, count 2 2006.173.23:15:26.28#ibcon#read 4, iclass 3, count 2 2006.173.23:15:26.28#ibcon#about to read 5, iclass 3, count 2 2006.173.23:15:26.28#ibcon#read 5, iclass 3, count 2 2006.173.23:15:26.28#ibcon#about to read 6, iclass 3, count 2 2006.173.23:15:26.28#ibcon#read 6, iclass 3, count 2 2006.173.23:15:26.28#ibcon#end of sib2, iclass 3, count 2 2006.173.23:15:26.28#ibcon#*after write, iclass 3, count 2 2006.173.23:15:26.28#ibcon#*before return 0, iclass 3, count 2 2006.173.23:15:26.28#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.23:15:26.28#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.23:15:26.28#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.23:15:26.28#ibcon#ireg 7 cls_cnt 0 2006.173.23:15:26.28#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.23:15:26.40#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.23:15:26.40#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.23:15:26.40#ibcon#enter wrdev, iclass 3, count 0 2006.173.23:15:26.40#ibcon#first serial, iclass 3, count 0 2006.173.23:15:26.40#ibcon#enter sib2, iclass 3, count 0 2006.173.23:15:26.40#ibcon#flushed, iclass 3, count 0 2006.173.23:15:26.40#ibcon#about to write, iclass 3, count 0 2006.173.23:15:26.40#ibcon#wrote, iclass 3, count 0 2006.173.23:15:26.40#ibcon#about to read 3, iclass 3, count 0 2006.173.23:15:26.42#ibcon#read 3, iclass 3, count 0 2006.173.23:15:26.42#ibcon#about to read 4, iclass 3, count 0 2006.173.23:15:26.42#ibcon#read 4, iclass 3, count 0 2006.173.23:15:26.42#ibcon#about to read 5, iclass 3, count 0 2006.173.23:15:26.42#ibcon#read 5, iclass 3, count 0 2006.173.23:15:26.42#ibcon#about to read 6, iclass 3, count 0 2006.173.23:15:26.42#ibcon#read 6, iclass 3, count 0 2006.173.23:15:26.42#ibcon#end of sib2, iclass 3, count 0 2006.173.23:15:26.42#ibcon#*mode == 0, iclass 3, count 0 2006.173.23:15:26.42#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.23:15:26.42#ibcon#[27=USB\r\n] 2006.173.23:15:26.42#ibcon#*before write, iclass 3, count 0 2006.173.23:15:26.42#ibcon#enter sib2, iclass 3, count 0 2006.173.23:15:26.42#ibcon#flushed, iclass 3, count 0 2006.173.23:15:26.42#ibcon#about to write, iclass 3, count 0 2006.173.23:15:26.42#ibcon#wrote, iclass 3, count 0 2006.173.23:15:26.42#ibcon#about to read 3, iclass 3, count 0 2006.173.23:15:26.45#ibcon#read 3, iclass 3, count 0 2006.173.23:15:26.45#ibcon#about to read 4, iclass 3, count 0 2006.173.23:15:26.45#ibcon#read 4, iclass 3, count 0 2006.173.23:15:26.45#ibcon#about to read 5, iclass 3, count 0 2006.173.23:15:26.45#ibcon#read 5, iclass 3, count 0 2006.173.23:15:26.45#ibcon#about to read 6, iclass 3, count 0 2006.173.23:15:26.45#ibcon#read 6, iclass 3, count 0 2006.173.23:15:26.45#ibcon#end of sib2, iclass 3, count 0 2006.173.23:15:26.45#ibcon#*after write, iclass 3, count 0 2006.173.23:15:26.45#ibcon#*before return 0, iclass 3, count 0 2006.173.23:15:26.45#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.23:15:26.45#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.23:15:26.45#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.23:15:26.45#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.23:15:26.45$vck44/vblo=3,649.99 2006.173.23:15:26.45#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.23:15:26.45#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.23:15:26.45#ibcon#ireg 17 cls_cnt 0 2006.173.23:15:26.45#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.23:15:26.45#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.23:15:26.45#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.23:15:26.45#ibcon#enter wrdev, iclass 5, count 0 2006.173.23:15:26.45#ibcon#first serial, iclass 5, count 0 2006.173.23:15:26.45#ibcon#enter sib2, iclass 5, count 0 2006.173.23:15:26.45#ibcon#flushed, iclass 5, count 0 2006.173.23:15:26.45#ibcon#about to write, iclass 5, count 0 2006.173.23:15:26.45#ibcon#wrote, iclass 5, count 0 2006.173.23:15:26.45#ibcon#about to read 3, iclass 5, count 0 2006.173.23:15:26.47#ibcon#read 3, iclass 5, count 0 2006.173.23:15:26.47#ibcon#about to read 4, iclass 5, count 0 2006.173.23:15:26.47#ibcon#read 4, iclass 5, count 0 2006.173.23:15:26.47#ibcon#about to read 5, iclass 5, count 0 2006.173.23:15:26.47#ibcon#read 5, iclass 5, count 0 2006.173.23:15:26.47#ibcon#about to read 6, iclass 5, count 0 2006.173.23:15:26.47#ibcon#read 6, iclass 5, count 0 2006.173.23:15:26.47#ibcon#end of sib2, iclass 5, count 0 2006.173.23:15:26.47#ibcon#*mode == 0, iclass 5, count 0 2006.173.23:15:26.47#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.23:15:26.47#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.23:15:26.47#ibcon#*before write, iclass 5, count 0 2006.173.23:15:26.47#ibcon#enter sib2, iclass 5, count 0 2006.173.23:15:26.47#ibcon#flushed, iclass 5, count 0 2006.173.23:15:26.47#ibcon#about to write, iclass 5, count 0 2006.173.23:15:26.47#ibcon#wrote, iclass 5, count 0 2006.173.23:15:26.47#ibcon#about to read 3, iclass 5, count 0 2006.173.23:15:26.51#ibcon#read 3, iclass 5, count 0 2006.173.23:15:26.51#ibcon#about to read 4, iclass 5, count 0 2006.173.23:15:26.51#ibcon#read 4, iclass 5, count 0 2006.173.23:15:26.51#ibcon#about to read 5, iclass 5, count 0 2006.173.23:15:26.51#ibcon#read 5, iclass 5, count 0 2006.173.23:15:26.51#ibcon#about to read 6, iclass 5, count 0 2006.173.23:15:26.51#ibcon#read 6, iclass 5, count 0 2006.173.23:15:26.51#ibcon#end of sib2, iclass 5, count 0 2006.173.23:15:26.51#ibcon#*after write, iclass 5, count 0 2006.173.23:15:26.51#ibcon#*before return 0, iclass 5, count 0 2006.173.23:15:26.51#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.23:15:26.51#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.23:15:26.51#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.23:15:26.51#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.23:15:26.51$vck44/vb=3,4 2006.173.23:15:26.51#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.173.23:15:26.51#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.173.23:15:26.51#ibcon#ireg 11 cls_cnt 2 2006.173.23:15:26.51#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.23:15:26.57#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.23:15:26.57#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.23:15:26.57#ibcon#enter wrdev, iclass 7, count 2 2006.173.23:15:26.57#ibcon#first serial, iclass 7, count 2 2006.173.23:15:26.57#ibcon#enter sib2, iclass 7, count 2 2006.173.23:15:26.57#ibcon#flushed, iclass 7, count 2 2006.173.23:15:26.57#ibcon#about to write, iclass 7, count 2 2006.173.23:15:26.57#ibcon#wrote, iclass 7, count 2 2006.173.23:15:26.57#ibcon#about to read 3, iclass 7, count 2 2006.173.23:15:26.59#ibcon#read 3, iclass 7, count 2 2006.173.23:15:26.59#ibcon#about to read 4, iclass 7, count 2 2006.173.23:15:26.59#ibcon#read 4, iclass 7, count 2 2006.173.23:15:26.59#ibcon#about to read 5, iclass 7, count 2 2006.173.23:15:26.59#ibcon#read 5, iclass 7, count 2 2006.173.23:15:26.59#ibcon#about to read 6, iclass 7, count 2 2006.173.23:15:26.59#ibcon#read 6, iclass 7, count 2 2006.173.23:15:26.59#ibcon#end of sib2, iclass 7, count 2 2006.173.23:15:26.59#ibcon#*mode == 0, iclass 7, count 2 2006.173.23:15:26.59#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.173.23:15:26.59#ibcon#[27=AT03-04\r\n] 2006.173.23:15:26.59#ibcon#*before write, iclass 7, count 2 2006.173.23:15:26.59#ibcon#enter sib2, iclass 7, count 2 2006.173.23:15:26.59#ibcon#flushed, iclass 7, count 2 2006.173.23:15:26.59#ibcon#about to write, iclass 7, count 2 2006.173.23:15:26.59#ibcon#wrote, iclass 7, count 2 2006.173.23:15:26.59#ibcon#about to read 3, iclass 7, count 2 2006.173.23:15:26.62#ibcon#read 3, iclass 7, count 2 2006.173.23:15:26.62#ibcon#about to read 4, iclass 7, count 2 2006.173.23:15:26.62#ibcon#read 4, iclass 7, count 2 2006.173.23:15:26.62#ibcon#about to read 5, iclass 7, count 2 2006.173.23:15:26.62#ibcon#read 5, iclass 7, count 2 2006.173.23:15:26.62#ibcon#about to read 6, iclass 7, count 2 2006.173.23:15:26.62#ibcon#read 6, iclass 7, count 2 2006.173.23:15:26.62#ibcon#end of sib2, iclass 7, count 2 2006.173.23:15:26.62#ibcon#*after write, iclass 7, count 2 2006.173.23:15:26.62#ibcon#*before return 0, iclass 7, count 2 2006.173.23:15:26.62#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.23:15:26.62#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.173.23:15:26.62#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.173.23:15:26.62#ibcon#ireg 7 cls_cnt 0 2006.173.23:15:26.62#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.23:15:26.70#abcon#<5=/10 1.0 2.0 22.98 901003.2\r\n> 2006.173.23:15:26.72#abcon#{5=INTERFACE CLEAR} 2006.173.23:15:26.74#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.23:15:26.74#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.23:15:26.74#ibcon#enter wrdev, iclass 7, count 0 2006.173.23:15:26.74#ibcon#first serial, iclass 7, count 0 2006.173.23:15:26.74#ibcon#enter sib2, iclass 7, count 0 2006.173.23:15:26.74#ibcon#flushed, iclass 7, count 0 2006.173.23:15:26.74#ibcon#about to write, iclass 7, count 0 2006.173.23:15:26.74#ibcon#wrote, iclass 7, count 0 2006.173.23:15:26.74#ibcon#about to read 3, iclass 7, count 0 2006.173.23:15:26.76#ibcon#read 3, iclass 7, count 0 2006.173.23:15:26.76#ibcon#about to read 4, iclass 7, count 0 2006.173.23:15:26.76#ibcon#read 4, iclass 7, count 0 2006.173.23:15:26.76#ibcon#about to read 5, iclass 7, count 0 2006.173.23:15:26.76#ibcon#read 5, iclass 7, count 0 2006.173.23:15:26.76#ibcon#about to read 6, iclass 7, count 0 2006.173.23:15:26.76#ibcon#read 6, iclass 7, count 0 2006.173.23:15:26.76#ibcon#end of sib2, iclass 7, count 0 2006.173.23:15:26.76#ibcon#*mode == 0, iclass 7, count 0 2006.173.23:15:26.76#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.23:15:26.76#ibcon#[27=USB\r\n] 2006.173.23:15:26.76#ibcon#*before write, iclass 7, count 0 2006.173.23:15:26.76#ibcon#enter sib2, iclass 7, count 0 2006.173.23:15:26.76#ibcon#flushed, iclass 7, count 0 2006.173.23:15:26.76#ibcon#about to write, iclass 7, count 0 2006.173.23:15:26.76#ibcon#wrote, iclass 7, count 0 2006.173.23:15:26.76#ibcon#about to read 3, iclass 7, count 0 2006.173.23:15:26.78#abcon#[5=S1D000X0/0*\r\n] 2006.173.23:15:26.79#ibcon#read 3, iclass 7, count 0 2006.173.23:15:26.79#ibcon#about to read 4, iclass 7, count 0 2006.173.23:15:26.79#ibcon#read 4, iclass 7, count 0 2006.173.23:15:26.79#ibcon#about to read 5, iclass 7, count 0 2006.173.23:15:26.79#ibcon#read 5, iclass 7, count 0 2006.173.23:15:26.79#ibcon#about to read 6, iclass 7, count 0 2006.173.23:15:26.79#ibcon#read 6, iclass 7, count 0 2006.173.23:15:26.79#ibcon#end of sib2, iclass 7, count 0 2006.173.23:15:26.79#ibcon#*after write, iclass 7, count 0 2006.173.23:15:26.79#ibcon#*before return 0, iclass 7, count 0 2006.173.23:15:26.79#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.23:15:26.79#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.173.23:15:26.79#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.23:15:26.79#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.23:15:26.79$vck44/vblo=4,679.99 2006.173.23:15:26.79#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.23:15:26.79#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.23:15:26.79#ibcon#ireg 17 cls_cnt 0 2006.173.23:15:26.79#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.23:15:26.79#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.23:15:26.79#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.23:15:26.79#ibcon#enter wrdev, iclass 15, count 0 2006.173.23:15:26.79#ibcon#first serial, iclass 15, count 0 2006.173.23:15:26.79#ibcon#enter sib2, iclass 15, count 0 2006.173.23:15:26.79#ibcon#flushed, iclass 15, count 0 2006.173.23:15:26.79#ibcon#about to write, iclass 15, count 0 2006.173.23:15:26.79#ibcon#wrote, iclass 15, count 0 2006.173.23:15:26.79#ibcon#about to read 3, iclass 15, count 0 2006.173.23:15:26.81#ibcon#read 3, iclass 15, count 0 2006.173.23:15:26.81#ibcon#about to read 4, iclass 15, count 0 2006.173.23:15:26.81#ibcon#read 4, iclass 15, count 0 2006.173.23:15:26.81#ibcon#about to read 5, iclass 15, count 0 2006.173.23:15:26.81#ibcon#read 5, iclass 15, count 0 2006.173.23:15:26.81#ibcon#about to read 6, iclass 15, count 0 2006.173.23:15:26.81#ibcon#read 6, iclass 15, count 0 2006.173.23:15:26.81#ibcon#end of sib2, iclass 15, count 0 2006.173.23:15:26.81#ibcon#*mode == 0, iclass 15, count 0 2006.173.23:15:26.81#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.23:15:26.81#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.23:15:26.81#ibcon#*before write, iclass 15, count 0 2006.173.23:15:26.81#ibcon#enter sib2, iclass 15, count 0 2006.173.23:15:26.81#ibcon#flushed, iclass 15, count 0 2006.173.23:15:26.81#ibcon#about to write, iclass 15, count 0 2006.173.23:15:26.81#ibcon#wrote, iclass 15, count 0 2006.173.23:15:26.81#ibcon#about to read 3, iclass 15, count 0 2006.173.23:15:26.85#ibcon#read 3, iclass 15, count 0 2006.173.23:15:26.85#ibcon#about to read 4, iclass 15, count 0 2006.173.23:15:26.85#ibcon#read 4, iclass 15, count 0 2006.173.23:15:26.85#ibcon#about to read 5, iclass 15, count 0 2006.173.23:15:26.85#ibcon#read 5, iclass 15, count 0 2006.173.23:15:26.85#ibcon#about to read 6, iclass 15, count 0 2006.173.23:15:26.85#ibcon#read 6, iclass 15, count 0 2006.173.23:15:26.85#ibcon#end of sib2, iclass 15, count 0 2006.173.23:15:26.85#ibcon#*after write, iclass 15, count 0 2006.173.23:15:26.85#ibcon#*before return 0, iclass 15, count 0 2006.173.23:15:26.85#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.23:15:26.85#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.23:15:26.85#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.23:15:26.85#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.23:15:26.85$vck44/vb=4,4 2006.173.23:15:26.85#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.23:15:26.85#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.23:15:26.85#ibcon#ireg 11 cls_cnt 2 2006.173.23:15:26.85#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.23:15:26.91#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.23:15:26.91#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.23:15:26.91#ibcon#enter wrdev, iclass 17, count 2 2006.173.23:15:26.91#ibcon#first serial, iclass 17, count 2 2006.173.23:15:26.91#ibcon#enter sib2, iclass 17, count 2 2006.173.23:15:26.91#ibcon#flushed, iclass 17, count 2 2006.173.23:15:26.91#ibcon#about to write, iclass 17, count 2 2006.173.23:15:26.91#ibcon#wrote, iclass 17, count 2 2006.173.23:15:26.91#ibcon#about to read 3, iclass 17, count 2 2006.173.23:15:26.93#ibcon#read 3, iclass 17, count 2 2006.173.23:15:26.93#ibcon#about to read 4, iclass 17, count 2 2006.173.23:15:26.93#ibcon#read 4, iclass 17, count 2 2006.173.23:15:26.93#ibcon#about to read 5, iclass 17, count 2 2006.173.23:15:26.93#ibcon#read 5, iclass 17, count 2 2006.173.23:15:26.93#ibcon#about to read 6, iclass 17, count 2 2006.173.23:15:26.93#ibcon#read 6, iclass 17, count 2 2006.173.23:15:26.93#ibcon#end of sib2, iclass 17, count 2 2006.173.23:15:26.93#ibcon#*mode == 0, iclass 17, count 2 2006.173.23:15:26.93#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.23:15:26.93#ibcon#[27=AT04-04\r\n] 2006.173.23:15:26.93#ibcon#*before write, iclass 17, count 2 2006.173.23:15:26.93#ibcon#enter sib2, iclass 17, count 2 2006.173.23:15:26.93#ibcon#flushed, iclass 17, count 2 2006.173.23:15:26.93#ibcon#about to write, iclass 17, count 2 2006.173.23:15:26.93#ibcon#wrote, iclass 17, count 2 2006.173.23:15:26.93#ibcon#about to read 3, iclass 17, count 2 2006.173.23:15:26.96#ibcon#read 3, iclass 17, count 2 2006.173.23:15:26.96#ibcon#about to read 4, iclass 17, count 2 2006.173.23:15:26.96#ibcon#read 4, iclass 17, count 2 2006.173.23:15:26.96#ibcon#about to read 5, iclass 17, count 2 2006.173.23:15:26.96#ibcon#read 5, iclass 17, count 2 2006.173.23:15:26.96#ibcon#about to read 6, iclass 17, count 2 2006.173.23:15:26.96#ibcon#read 6, iclass 17, count 2 2006.173.23:15:26.96#ibcon#end of sib2, iclass 17, count 2 2006.173.23:15:26.96#ibcon#*after write, iclass 17, count 2 2006.173.23:15:26.96#ibcon#*before return 0, iclass 17, count 2 2006.173.23:15:26.96#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.23:15:26.96#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.23:15:26.96#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.23:15:26.96#ibcon#ireg 7 cls_cnt 0 2006.173.23:15:26.96#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.23:15:27.08#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.23:15:27.08#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.23:15:27.08#ibcon#enter wrdev, iclass 17, count 0 2006.173.23:15:27.08#ibcon#first serial, iclass 17, count 0 2006.173.23:15:27.08#ibcon#enter sib2, iclass 17, count 0 2006.173.23:15:27.08#ibcon#flushed, iclass 17, count 0 2006.173.23:15:27.08#ibcon#about to write, iclass 17, count 0 2006.173.23:15:27.08#ibcon#wrote, iclass 17, count 0 2006.173.23:15:27.08#ibcon#about to read 3, iclass 17, count 0 2006.173.23:15:27.10#ibcon#read 3, iclass 17, count 0 2006.173.23:15:27.10#ibcon#about to read 4, iclass 17, count 0 2006.173.23:15:27.10#ibcon#read 4, iclass 17, count 0 2006.173.23:15:27.10#ibcon#about to read 5, iclass 17, count 0 2006.173.23:15:27.10#ibcon#read 5, iclass 17, count 0 2006.173.23:15:27.10#ibcon#about to read 6, iclass 17, count 0 2006.173.23:15:27.10#ibcon#read 6, iclass 17, count 0 2006.173.23:15:27.10#ibcon#end of sib2, iclass 17, count 0 2006.173.23:15:27.10#ibcon#*mode == 0, iclass 17, count 0 2006.173.23:15:27.10#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.23:15:27.10#ibcon#[27=USB\r\n] 2006.173.23:15:27.10#ibcon#*before write, iclass 17, count 0 2006.173.23:15:27.10#ibcon#enter sib2, iclass 17, count 0 2006.173.23:15:27.10#ibcon#flushed, iclass 17, count 0 2006.173.23:15:27.10#ibcon#about to write, iclass 17, count 0 2006.173.23:15:27.10#ibcon#wrote, iclass 17, count 0 2006.173.23:15:27.10#ibcon#about to read 3, iclass 17, count 0 2006.173.23:15:27.13#ibcon#read 3, iclass 17, count 0 2006.173.23:15:27.13#ibcon#about to read 4, iclass 17, count 0 2006.173.23:15:27.13#ibcon#read 4, iclass 17, count 0 2006.173.23:15:27.13#ibcon#about to read 5, iclass 17, count 0 2006.173.23:15:27.13#ibcon#read 5, iclass 17, count 0 2006.173.23:15:27.13#ibcon#about to read 6, iclass 17, count 0 2006.173.23:15:27.13#ibcon#read 6, iclass 17, count 0 2006.173.23:15:27.13#ibcon#end of sib2, iclass 17, count 0 2006.173.23:15:27.13#ibcon#*after write, iclass 17, count 0 2006.173.23:15:27.13#ibcon#*before return 0, iclass 17, count 0 2006.173.23:15:27.13#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.23:15:27.13#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.23:15:27.13#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.23:15:27.13#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.23:15:27.13$vck44/vblo=5,709.99 2006.173.23:15:27.13#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.23:15:27.13#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.23:15:27.13#ibcon#ireg 17 cls_cnt 0 2006.173.23:15:27.13#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.23:15:27.13#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.23:15:27.13#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.23:15:27.13#ibcon#enter wrdev, iclass 19, count 0 2006.173.23:15:27.13#ibcon#first serial, iclass 19, count 0 2006.173.23:15:27.13#ibcon#enter sib2, iclass 19, count 0 2006.173.23:15:27.13#ibcon#flushed, iclass 19, count 0 2006.173.23:15:27.13#ibcon#about to write, iclass 19, count 0 2006.173.23:15:27.13#ibcon#wrote, iclass 19, count 0 2006.173.23:15:27.13#ibcon#about to read 3, iclass 19, count 0 2006.173.23:15:27.15#ibcon#read 3, iclass 19, count 0 2006.173.23:15:27.15#ibcon#about to read 4, iclass 19, count 0 2006.173.23:15:27.15#ibcon#read 4, iclass 19, count 0 2006.173.23:15:27.15#ibcon#about to read 5, iclass 19, count 0 2006.173.23:15:27.15#ibcon#read 5, iclass 19, count 0 2006.173.23:15:27.15#ibcon#about to read 6, iclass 19, count 0 2006.173.23:15:27.15#ibcon#read 6, iclass 19, count 0 2006.173.23:15:27.15#ibcon#end of sib2, iclass 19, count 0 2006.173.23:15:27.15#ibcon#*mode == 0, iclass 19, count 0 2006.173.23:15:27.15#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.23:15:27.15#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.23:15:27.15#ibcon#*before write, iclass 19, count 0 2006.173.23:15:27.15#ibcon#enter sib2, iclass 19, count 0 2006.173.23:15:27.15#ibcon#flushed, iclass 19, count 0 2006.173.23:15:27.15#ibcon#about to write, iclass 19, count 0 2006.173.23:15:27.15#ibcon#wrote, iclass 19, count 0 2006.173.23:15:27.15#ibcon#about to read 3, iclass 19, count 0 2006.173.23:15:27.19#ibcon#read 3, iclass 19, count 0 2006.173.23:15:27.19#ibcon#about to read 4, iclass 19, count 0 2006.173.23:15:27.19#ibcon#read 4, iclass 19, count 0 2006.173.23:15:27.19#ibcon#about to read 5, iclass 19, count 0 2006.173.23:15:27.19#ibcon#read 5, iclass 19, count 0 2006.173.23:15:27.19#ibcon#about to read 6, iclass 19, count 0 2006.173.23:15:27.19#ibcon#read 6, iclass 19, count 0 2006.173.23:15:27.19#ibcon#end of sib2, iclass 19, count 0 2006.173.23:15:27.19#ibcon#*after write, iclass 19, count 0 2006.173.23:15:27.19#ibcon#*before return 0, iclass 19, count 0 2006.173.23:15:27.19#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.23:15:27.19#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.23:15:27.19#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.23:15:27.19#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.23:15:27.19$vck44/vb=5,4 2006.173.23:15:27.19#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.23:15:27.19#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.23:15:27.19#ibcon#ireg 11 cls_cnt 2 2006.173.23:15:27.19#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.23:15:27.25#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.23:15:27.25#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.23:15:27.25#ibcon#enter wrdev, iclass 21, count 2 2006.173.23:15:27.25#ibcon#first serial, iclass 21, count 2 2006.173.23:15:27.25#ibcon#enter sib2, iclass 21, count 2 2006.173.23:15:27.25#ibcon#flushed, iclass 21, count 2 2006.173.23:15:27.25#ibcon#about to write, iclass 21, count 2 2006.173.23:15:27.25#ibcon#wrote, iclass 21, count 2 2006.173.23:15:27.25#ibcon#about to read 3, iclass 21, count 2 2006.173.23:15:27.27#ibcon#read 3, iclass 21, count 2 2006.173.23:15:27.27#ibcon#about to read 4, iclass 21, count 2 2006.173.23:15:27.27#ibcon#read 4, iclass 21, count 2 2006.173.23:15:27.27#ibcon#about to read 5, iclass 21, count 2 2006.173.23:15:27.27#ibcon#read 5, iclass 21, count 2 2006.173.23:15:27.27#ibcon#about to read 6, iclass 21, count 2 2006.173.23:15:27.27#ibcon#read 6, iclass 21, count 2 2006.173.23:15:27.27#ibcon#end of sib2, iclass 21, count 2 2006.173.23:15:27.27#ibcon#*mode == 0, iclass 21, count 2 2006.173.23:15:27.27#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.23:15:27.27#ibcon#[27=AT05-04\r\n] 2006.173.23:15:27.27#ibcon#*before write, iclass 21, count 2 2006.173.23:15:27.27#ibcon#enter sib2, iclass 21, count 2 2006.173.23:15:27.27#ibcon#flushed, iclass 21, count 2 2006.173.23:15:27.27#ibcon#about to write, iclass 21, count 2 2006.173.23:15:27.27#ibcon#wrote, iclass 21, count 2 2006.173.23:15:27.27#ibcon#about to read 3, iclass 21, count 2 2006.173.23:15:27.30#ibcon#read 3, iclass 21, count 2 2006.173.23:15:27.30#ibcon#about to read 4, iclass 21, count 2 2006.173.23:15:27.30#ibcon#read 4, iclass 21, count 2 2006.173.23:15:27.30#ibcon#about to read 5, iclass 21, count 2 2006.173.23:15:27.30#ibcon#read 5, iclass 21, count 2 2006.173.23:15:27.30#ibcon#about to read 6, iclass 21, count 2 2006.173.23:15:27.30#ibcon#read 6, iclass 21, count 2 2006.173.23:15:27.30#ibcon#end of sib2, iclass 21, count 2 2006.173.23:15:27.30#ibcon#*after write, iclass 21, count 2 2006.173.23:15:27.30#ibcon#*before return 0, iclass 21, count 2 2006.173.23:15:27.30#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.23:15:27.30#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.23:15:27.30#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.23:15:27.30#ibcon#ireg 7 cls_cnt 0 2006.173.23:15:27.30#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.23:15:27.42#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.23:15:27.42#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.23:15:27.42#ibcon#enter wrdev, iclass 21, count 0 2006.173.23:15:27.42#ibcon#first serial, iclass 21, count 0 2006.173.23:15:27.42#ibcon#enter sib2, iclass 21, count 0 2006.173.23:15:27.42#ibcon#flushed, iclass 21, count 0 2006.173.23:15:27.42#ibcon#about to write, iclass 21, count 0 2006.173.23:15:27.42#ibcon#wrote, iclass 21, count 0 2006.173.23:15:27.42#ibcon#about to read 3, iclass 21, count 0 2006.173.23:15:27.44#ibcon#read 3, iclass 21, count 0 2006.173.23:15:27.44#ibcon#about to read 4, iclass 21, count 0 2006.173.23:15:27.44#ibcon#read 4, iclass 21, count 0 2006.173.23:15:27.44#ibcon#about to read 5, iclass 21, count 0 2006.173.23:15:27.44#ibcon#read 5, iclass 21, count 0 2006.173.23:15:27.44#ibcon#about to read 6, iclass 21, count 0 2006.173.23:15:27.44#ibcon#read 6, iclass 21, count 0 2006.173.23:15:27.44#ibcon#end of sib2, iclass 21, count 0 2006.173.23:15:27.44#ibcon#*mode == 0, iclass 21, count 0 2006.173.23:15:27.44#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.23:15:27.44#ibcon#[27=USB\r\n] 2006.173.23:15:27.44#ibcon#*before write, iclass 21, count 0 2006.173.23:15:27.44#ibcon#enter sib2, iclass 21, count 0 2006.173.23:15:27.44#ibcon#flushed, iclass 21, count 0 2006.173.23:15:27.44#ibcon#about to write, iclass 21, count 0 2006.173.23:15:27.44#ibcon#wrote, iclass 21, count 0 2006.173.23:15:27.44#ibcon#about to read 3, iclass 21, count 0 2006.173.23:15:27.47#ibcon#read 3, iclass 21, count 0 2006.173.23:15:27.47#ibcon#about to read 4, iclass 21, count 0 2006.173.23:15:27.47#ibcon#read 4, iclass 21, count 0 2006.173.23:15:27.47#ibcon#about to read 5, iclass 21, count 0 2006.173.23:15:27.47#ibcon#read 5, iclass 21, count 0 2006.173.23:15:27.47#ibcon#about to read 6, iclass 21, count 0 2006.173.23:15:27.47#ibcon#read 6, iclass 21, count 0 2006.173.23:15:27.47#ibcon#end of sib2, iclass 21, count 0 2006.173.23:15:27.47#ibcon#*after write, iclass 21, count 0 2006.173.23:15:27.47#ibcon#*before return 0, iclass 21, count 0 2006.173.23:15:27.47#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.23:15:27.47#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.23:15:27.47#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.23:15:27.47#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.23:15:27.47$vck44/vblo=6,719.99 2006.173.23:15:27.47#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.23:15:27.47#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.23:15:27.47#ibcon#ireg 17 cls_cnt 0 2006.173.23:15:27.47#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.23:15:27.47#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.23:15:27.47#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.23:15:27.47#ibcon#enter wrdev, iclass 23, count 0 2006.173.23:15:27.47#ibcon#first serial, iclass 23, count 0 2006.173.23:15:27.47#ibcon#enter sib2, iclass 23, count 0 2006.173.23:15:27.47#ibcon#flushed, iclass 23, count 0 2006.173.23:15:27.47#ibcon#about to write, iclass 23, count 0 2006.173.23:15:27.47#ibcon#wrote, iclass 23, count 0 2006.173.23:15:27.47#ibcon#about to read 3, iclass 23, count 0 2006.173.23:15:27.49#ibcon#read 3, iclass 23, count 0 2006.173.23:15:27.49#ibcon#about to read 4, iclass 23, count 0 2006.173.23:15:27.49#ibcon#read 4, iclass 23, count 0 2006.173.23:15:27.49#ibcon#about to read 5, iclass 23, count 0 2006.173.23:15:27.49#ibcon#read 5, iclass 23, count 0 2006.173.23:15:27.49#ibcon#about to read 6, iclass 23, count 0 2006.173.23:15:27.49#ibcon#read 6, iclass 23, count 0 2006.173.23:15:27.49#ibcon#end of sib2, iclass 23, count 0 2006.173.23:15:27.49#ibcon#*mode == 0, iclass 23, count 0 2006.173.23:15:27.49#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.23:15:27.49#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.23:15:27.49#ibcon#*before write, iclass 23, count 0 2006.173.23:15:27.49#ibcon#enter sib2, iclass 23, count 0 2006.173.23:15:27.49#ibcon#flushed, iclass 23, count 0 2006.173.23:15:27.49#ibcon#about to write, iclass 23, count 0 2006.173.23:15:27.49#ibcon#wrote, iclass 23, count 0 2006.173.23:15:27.49#ibcon#about to read 3, iclass 23, count 0 2006.173.23:15:27.53#ibcon#read 3, iclass 23, count 0 2006.173.23:15:27.53#ibcon#about to read 4, iclass 23, count 0 2006.173.23:15:27.53#ibcon#read 4, iclass 23, count 0 2006.173.23:15:27.53#ibcon#about to read 5, iclass 23, count 0 2006.173.23:15:27.53#ibcon#read 5, iclass 23, count 0 2006.173.23:15:27.53#ibcon#about to read 6, iclass 23, count 0 2006.173.23:15:27.53#ibcon#read 6, iclass 23, count 0 2006.173.23:15:27.53#ibcon#end of sib2, iclass 23, count 0 2006.173.23:15:27.53#ibcon#*after write, iclass 23, count 0 2006.173.23:15:27.53#ibcon#*before return 0, iclass 23, count 0 2006.173.23:15:27.53#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.23:15:27.53#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.23:15:27.53#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.23:15:27.53#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.23:15:27.53$vck44/vb=6,4 2006.173.23:15:27.53#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.23:15:27.53#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.23:15:27.53#ibcon#ireg 11 cls_cnt 2 2006.173.23:15:27.53#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.23:15:27.59#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.23:15:27.59#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.23:15:27.59#ibcon#enter wrdev, iclass 25, count 2 2006.173.23:15:27.59#ibcon#first serial, iclass 25, count 2 2006.173.23:15:27.59#ibcon#enter sib2, iclass 25, count 2 2006.173.23:15:27.59#ibcon#flushed, iclass 25, count 2 2006.173.23:15:27.59#ibcon#about to write, iclass 25, count 2 2006.173.23:15:27.59#ibcon#wrote, iclass 25, count 2 2006.173.23:15:27.59#ibcon#about to read 3, iclass 25, count 2 2006.173.23:15:27.61#ibcon#read 3, iclass 25, count 2 2006.173.23:15:27.61#ibcon#about to read 4, iclass 25, count 2 2006.173.23:15:27.61#ibcon#read 4, iclass 25, count 2 2006.173.23:15:27.61#ibcon#about to read 5, iclass 25, count 2 2006.173.23:15:27.61#ibcon#read 5, iclass 25, count 2 2006.173.23:15:27.61#ibcon#about to read 6, iclass 25, count 2 2006.173.23:15:27.61#ibcon#read 6, iclass 25, count 2 2006.173.23:15:27.61#ibcon#end of sib2, iclass 25, count 2 2006.173.23:15:27.61#ibcon#*mode == 0, iclass 25, count 2 2006.173.23:15:27.61#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.23:15:27.61#ibcon#[27=AT06-04\r\n] 2006.173.23:15:27.61#ibcon#*before write, iclass 25, count 2 2006.173.23:15:27.61#ibcon#enter sib2, iclass 25, count 2 2006.173.23:15:27.61#ibcon#flushed, iclass 25, count 2 2006.173.23:15:27.61#ibcon#about to write, iclass 25, count 2 2006.173.23:15:27.61#ibcon#wrote, iclass 25, count 2 2006.173.23:15:27.61#ibcon#about to read 3, iclass 25, count 2 2006.173.23:15:27.64#ibcon#read 3, iclass 25, count 2 2006.173.23:15:27.64#ibcon#about to read 4, iclass 25, count 2 2006.173.23:15:27.64#ibcon#read 4, iclass 25, count 2 2006.173.23:15:27.64#ibcon#about to read 5, iclass 25, count 2 2006.173.23:15:27.64#ibcon#read 5, iclass 25, count 2 2006.173.23:15:27.64#ibcon#about to read 6, iclass 25, count 2 2006.173.23:15:27.64#ibcon#read 6, iclass 25, count 2 2006.173.23:15:27.64#ibcon#end of sib2, iclass 25, count 2 2006.173.23:15:27.64#ibcon#*after write, iclass 25, count 2 2006.173.23:15:27.64#ibcon#*before return 0, iclass 25, count 2 2006.173.23:15:27.64#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.23:15:27.64#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.23:15:27.64#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.23:15:27.64#ibcon#ireg 7 cls_cnt 0 2006.173.23:15:27.64#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.23:15:27.76#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.23:15:27.76#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.23:15:27.76#ibcon#enter wrdev, iclass 25, count 0 2006.173.23:15:27.76#ibcon#first serial, iclass 25, count 0 2006.173.23:15:27.76#ibcon#enter sib2, iclass 25, count 0 2006.173.23:15:27.76#ibcon#flushed, iclass 25, count 0 2006.173.23:15:27.76#ibcon#about to write, iclass 25, count 0 2006.173.23:15:27.76#ibcon#wrote, iclass 25, count 0 2006.173.23:15:27.76#ibcon#about to read 3, iclass 25, count 0 2006.173.23:15:27.78#ibcon#read 3, iclass 25, count 0 2006.173.23:15:27.78#ibcon#about to read 4, iclass 25, count 0 2006.173.23:15:27.78#ibcon#read 4, iclass 25, count 0 2006.173.23:15:27.78#ibcon#about to read 5, iclass 25, count 0 2006.173.23:15:27.78#ibcon#read 5, iclass 25, count 0 2006.173.23:15:27.78#ibcon#about to read 6, iclass 25, count 0 2006.173.23:15:27.78#ibcon#read 6, iclass 25, count 0 2006.173.23:15:27.78#ibcon#end of sib2, iclass 25, count 0 2006.173.23:15:27.78#ibcon#*mode == 0, iclass 25, count 0 2006.173.23:15:27.78#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.23:15:27.78#ibcon#[27=USB\r\n] 2006.173.23:15:27.78#ibcon#*before write, iclass 25, count 0 2006.173.23:15:27.78#ibcon#enter sib2, iclass 25, count 0 2006.173.23:15:27.78#ibcon#flushed, iclass 25, count 0 2006.173.23:15:27.78#ibcon#about to write, iclass 25, count 0 2006.173.23:15:27.78#ibcon#wrote, iclass 25, count 0 2006.173.23:15:27.78#ibcon#about to read 3, iclass 25, count 0 2006.173.23:15:27.81#ibcon#read 3, iclass 25, count 0 2006.173.23:15:27.81#ibcon#about to read 4, iclass 25, count 0 2006.173.23:15:27.81#ibcon#read 4, iclass 25, count 0 2006.173.23:15:27.81#ibcon#about to read 5, iclass 25, count 0 2006.173.23:15:27.81#ibcon#read 5, iclass 25, count 0 2006.173.23:15:27.81#ibcon#about to read 6, iclass 25, count 0 2006.173.23:15:27.81#ibcon#read 6, iclass 25, count 0 2006.173.23:15:27.81#ibcon#end of sib2, iclass 25, count 0 2006.173.23:15:27.81#ibcon#*after write, iclass 25, count 0 2006.173.23:15:27.81#ibcon#*before return 0, iclass 25, count 0 2006.173.23:15:27.81#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.23:15:27.81#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.23:15:27.81#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.23:15:27.81#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.23:15:27.81$vck44/vblo=7,734.99 2006.173.23:15:27.81#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.23:15:27.81#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.23:15:27.81#ibcon#ireg 17 cls_cnt 0 2006.173.23:15:27.81#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.23:15:27.81#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.23:15:27.81#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.23:15:27.81#ibcon#enter wrdev, iclass 27, count 0 2006.173.23:15:27.81#ibcon#first serial, iclass 27, count 0 2006.173.23:15:27.81#ibcon#enter sib2, iclass 27, count 0 2006.173.23:15:27.81#ibcon#flushed, iclass 27, count 0 2006.173.23:15:27.81#ibcon#about to write, iclass 27, count 0 2006.173.23:15:27.81#ibcon#wrote, iclass 27, count 0 2006.173.23:15:27.81#ibcon#about to read 3, iclass 27, count 0 2006.173.23:15:27.83#ibcon#read 3, iclass 27, count 0 2006.173.23:15:27.83#ibcon#about to read 4, iclass 27, count 0 2006.173.23:15:27.83#ibcon#read 4, iclass 27, count 0 2006.173.23:15:27.83#ibcon#about to read 5, iclass 27, count 0 2006.173.23:15:27.83#ibcon#read 5, iclass 27, count 0 2006.173.23:15:27.83#ibcon#about to read 6, iclass 27, count 0 2006.173.23:15:27.83#ibcon#read 6, iclass 27, count 0 2006.173.23:15:27.83#ibcon#end of sib2, iclass 27, count 0 2006.173.23:15:27.83#ibcon#*mode == 0, iclass 27, count 0 2006.173.23:15:27.83#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.23:15:27.83#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.23:15:27.83#ibcon#*before write, iclass 27, count 0 2006.173.23:15:27.83#ibcon#enter sib2, iclass 27, count 0 2006.173.23:15:27.83#ibcon#flushed, iclass 27, count 0 2006.173.23:15:27.83#ibcon#about to write, iclass 27, count 0 2006.173.23:15:27.83#ibcon#wrote, iclass 27, count 0 2006.173.23:15:27.83#ibcon#about to read 3, iclass 27, count 0 2006.173.23:15:27.87#ibcon#read 3, iclass 27, count 0 2006.173.23:15:27.87#ibcon#about to read 4, iclass 27, count 0 2006.173.23:15:27.87#ibcon#read 4, iclass 27, count 0 2006.173.23:15:27.87#ibcon#about to read 5, iclass 27, count 0 2006.173.23:15:27.87#ibcon#read 5, iclass 27, count 0 2006.173.23:15:27.87#ibcon#about to read 6, iclass 27, count 0 2006.173.23:15:27.87#ibcon#read 6, iclass 27, count 0 2006.173.23:15:27.87#ibcon#end of sib2, iclass 27, count 0 2006.173.23:15:27.87#ibcon#*after write, iclass 27, count 0 2006.173.23:15:27.87#ibcon#*before return 0, iclass 27, count 0 2006.173.23:15:27.87#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.23:15:27.87#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.23:15:27.87#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.23:15:27.87#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.23:15:27.87$vck44/vb=7,4 2006.173.23:15:27.87#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.23:15:27.87#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.23:15:27.87#ibcon#ireg 11 cls_cnt 2 2006.173.23:15:27.87#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.23:15:27.93#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.23:15:27.93#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.23:15:27.93#ibcon#enter wrdev, iclass 29, count 2 2006.173.23:15:27.93#ibcon#first serial, iclass 29, count 2 2006.173.23:15:27.93#ibcon#enter sib2, iclass 29, count 2 2006.173.23:15:27.93#ibcon#flushed, iclass 29, count 2 2006.173.23:15:27.93#ibcon#about to write, iclass 29, count 2 2006.173.23:15:27.93#ibcon#wrote, iclass 29, count 2 2006.173.23:15:27.93#ibcon#about to read 3, iclass 29, count 2 2006.173.23:15:27.95#ibcon#read 3, iclass 29, count 2 2006.173.23:15:27.95#ibcon#about to read 4, iclass 29, count 2 2006.173.23:15:27.95#ibcon#read 4, iclass 29, count 2 2006.173.23:15:27.95#ibcon#about to read 5, iclass 29, count 2 2006.173.23:15:27.95#ibcon#read 5, iclass 29, count 2 2006.173.23:15:27.95#ibcon#about to read 6, iclass 29, count 2 2006.173.23:15:27.95#ibcon#read 6, iclass 29, count 2 2006.173.23:15:27.95#ibcon#end of sib2, iclass 29, count 2 2006.173.23:15:27.95#ibcon#*mode == 0, iclass 29, count 2 2006.173.23:15:27.95#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.23:15:27.95#ibcon#[27=AT07-04\r\n] 2006.173.23:15:27.95#ibcon#*before write, iclass 29, count 2 2006.173.23:15:27.95#ibcon#enter sib2, iclass 29, count 2 2006.173.23:15:27.95#ibcon#flushed, iclass 29, count 2 2006.173.23:15:27.95#ibcon#about to write, iclass 29, count 2 2006.173.23:15:27.95#ibcon#wrote, iclass 29, count 2 2006.173.23:15:27.95#ibcon#about to read 3, iclass 29, count 2 2006.173.23:15:27.98#ibcon#read 3, iclass 29, count 2 2006.173.23:15:27.98#ibcon#about to read 4, iclass 29, count 2 2006.173.23:15:27.98#ibcon#read 4, iclass 29, count 2 2006.173.23:15:27.98#ibcon#about to read 5, iclass 29, count 2 2006.173.23:15:27.98#ibcon#read 5, iclass 29, count 2 2006.173.23:15:27.98#ibcon#about to read 6, iclass 29, count 2 2006.173.23:15:27.98#ibcon#read 6, iclass 29, count 2 2006.173.23:15:27.98#ibcon#end of sib2, iclass 29, count 2 2006.173.23:15:27.98#ibcon#*after write, iclass 29, count 2 2006.173.23:15:27.98#ibcon#*before return 0, iclass 29, count 2 2006.173.23:15:27.98#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.23:15:27.98#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.23:15:27.98#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.23:15:27.98#ibcon#ireg 7 cls_cnt 0 2006.173.23:15:27.98#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.23:15:28.10#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.23:15:28.10#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.23:15:28.10#ibcon#enter wrdev, iclass 29, count 0 2006.173.23:15:28.10#ibcon#first serial, iclass 29, count 0 2006.173.23:15:28.10#ibcon#enter sib2, iclass 29, count 0 2006.173.23:15:28.10#ibcon#flushed, iclass 29, count 0 2006.173.23:15:28.10#ibcon#about to write, iclass 29, count 0 2006.173.23:15:28.10#ibcon#wrote, iclass 29, count 0 2006.173.23:15:28.10#ibcon#about to read 3, iclass 29, count 0 2006.173.23:15:28.12#ibcon#read 3, iclass 29, count 0 2006.173.23:15:28.12#ibcon#about to read 4, iclass 29, count 0 2006.173.23:15:28.12#ibcon#read 4, iclass 29, count 0 2006.173.23:15:28.12#ibcon#about to read 5, iclass 29, count 0 2006.173.23:15:28.12#ibcon#read 5, iclass 29, count 0 2006.173.23:15:28.12#ibcon#about to read 6, iclass 29, count 0 2006.173.23:15:28.12#ibcon#read 6, iclass 29, count 0 2006.173.23:15:28.12#ibcon#end of sib2, iclass 29, count 0 2006.173.23:15:28.12#ibcon#*mode == 0, iclass 29, count 0 2006.173.23:15:28.12#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.23:15:28.12#ibcon#[27=USB\r\n] 2006.173.23:15:28.12#ibcon#*before write, iclass 29, count 0 2006.173.23:15:28.12#ibcon#enter sib2, iclass 29, count 0 2006.173.23:15:28.12#ibcon#flushed, iclass 29, count 0 2006.173.23:15:28.12#ibcon#about to write, iclass 29, count 0 2006.173.23:15:28.12#ibcon#wrote, iclass 29, count 0 2006.173.23:15:28.12#ibcon#about to read 3, iclass 29, count 0 2006.173.23:15:28.15#ibcon#read 3, iclass 29, count 0 2006.173.23:15:28.15#ibcon#about to read 4, iclass 29, count 0 2006.173.23:15:28.15#ibcon#read 4, iclass 29, count 0 2006.173.23:15:28.15#ibcon#about to read 5, iclass 29, count 0 2006.173.23:15:28.15#ibcon#read 5, iclass 29, count 0 2006.173.23:15:28.15#ibcon#about to read 6, iclass 29, count 0 2006.173.23:15:28.15#ibcon#read 6, iclass 29, count 0 2006.173.23:15:28.15#ibcon#end of sib2, iclass 29, count 0 2006.173.23:15:28.15#ibcon#*after write, iclass 29, count 0 2006.173.23:15:28.15#ibcon#*before return 0, iclass 29, count 0 2006.173.23:15:28.15#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.23:15:28.15#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.23:15:28.15#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.23:15:28.15#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.23:15:28.15$vck44/vblo=8,744.99 2006.173.23:15:28.15#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.23:15:28.15#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.23:15:28.15#ibcon#ireg 17 cls_cnt 0 2006.173.23:15:28.15#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.23:15:28.15#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.23:15:28.15#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.23:15:28.15#ibcon#enter wrdev, iclass 31, count 0 2006.173.23:15:28.15#ibcon#first serial, iclass 31, count 0 2006.173.23:15:28.15#ibcon#enter sib2, iclass 31, count 0 2006.173.23:15:28.15#ibcon#flushed, iclass 31, count 0 2006.173.23:15:28.15#ibcon#about to write, iclass 31, count 0 2006.173.23:15:28.15#ibcon#wrote, iclass 31, count 0 2006.173.23:15:28.15#ibcon#about to read 3, iclass 31, count 0 2006.173.23:15:28.17#ibcon#read 3, iclass 31, count 0 2006.173.23:15:28.17#ibcon#about to read 4, iclass 31, count 0 2006.173.23:15:28.17#ibcon#read 4, iclass 31, count 0 2006.173.23:15:28.17#ibcon#about to read 5, iclass 31, count 0 2006.173.23:15:28.17#ibcon#read 5, iclass 31, count 0 2006.173.23:15:28.17#ibcon#about to read 6, iclass 31, count 0 2006.173.23:15:28.17#ibcon#read 6, iclass 31, count 0 2006.173.23:15:28.17#ibcon#end of sib2, iclass 31, count 0 2006.173.23:15:28.17#ibcon#*mode == 0, iclass 31, count 0 2006.173.23:15:28.17#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.23:15:28.17#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.23:15:28.17#ibcon#*before write, iclass 31, count 0 2006.173.23:15:28.17#ibcon#enter sib2, iclass 31, count 0 2006.173.23:15:28.17#ibcon#flushed, iclass 31, count 0 2006.173.23:15:28.17#ibcon#about to write, iclass 31, count 0 2006.173.23:15:28.17#ibcon#wrote, iclass 31, count 0 2006.173.23:15:28.17#ibcon#about to read 3, iclass 31, count 0 2006.173.23:15:28.21#ibcon#read 3, iclass 31, count 0 2006.173.23:15:28.21#ibcon#about to read 4, iclass 31, count 0 2006.173.23:15:28.21#ibcon#read 4, iclass 31, count 0 2006.173.23:15:28.21#ibcon#about to read 5, iclass 31, count 0 2006.173.23:15:28.21#ibcon#read 5, iclass 31, count 0 2006.173.23:15:28.21#ibcon#about to read 6, iclass 31, count 0 2006.173.23:15:28.21#ibcon#read 6, iclass 31, count 0 2006.173.23:15:28.21#ibcon#end of sib2, iclass 31, count 0 2006.173.23:15:28.21#ibcon#*after write, iclass 31, count 0 2006.173.23:15:28.21#ibcon#*before return 0, iclass 31, count 0 2006.173.23:15:28.21#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.23:15:28.21#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.23:15:28.21#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.23:15:28.21#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.23:15:28.21$vck44/vb=8,4 2006.173.23:15:28.21#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.173.23:15:28.21#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.173.23:15:28.21#ibcon#ireg 11 cls_cnt 2 2006.173.23:15:28.21#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.23:15:28.27#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.23:15:28.27#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.23:15:28.27#ibcon#enter wrdev, iclass 33, count 2 2006.173.23:15:28.27#ibcon#first serial, iclass 33, count 2 2006.173.23:15:28.27#ibcon#enter sib2, iclass 33, count 2 2006.173.23:15:28.27#ibcon#flushed, iclass 33, count 2 2006.173.23:15:28.27#ibcon#about to write, iclass 33, count 2 2006.173.23:15:28.27#ibcon#wrote, iclass 33, count 2 2006.173.23:15:28.27#ibcon#about to read 3, iclass 33, count 2 2006.173.23:15:28.29#ibcon#read 3, iclass 33, count 2 2006.173.23:15:28.29#ibcon#about to read 4, iclass 33, count 2 2006.173.23:15:28.29#ibcon#read 4, iclass 33, count 2 2006.173.23:15:28.29#ibcon#about to read 5, iclass 33, count 2 2006.173.23:15:28.29#ibcon#read 5, iclass 33, count 2 2006.173.23:15:28.29#ibcon#about to read 6, iclass 33, count 2 2006.173.23:15:28.29#ibcon#read 6, iclass 33, count 2 2006.173.23:15:28.29#ibcon#end of sib2, iclass 33, count 2 2006.173.23:15:28.29#ibcon#*mode == 0, iclass 33, count 2 2006.173.23:15:28.29#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.173.23:15:28.29#ibcon#[27=AT08-04\r\n] 2006.173.23:15:28.29#ibcon#*before write, iclass 33, count 2 2006.173.23:15:28.29#ibcon#enter sib2, iclass 33, count 2 2006.173.23:15:28.29#ibcon#flushed, iclass 33, count 2 2006.173.23:15:28.29#ibcon#about to write, iclass 33, count 2 2006.173.23:15:28.29#ibcon#wrote, iclass 33, count 2 2006.173.23:15:28.29#ibcon#about to read 3, iclass 33, count 2 2006.173.23:15:28.32#ibcon#read 3, iclass 33, count 2 2006.173.23:15:28.32#ibcon#about to read 4, iclass 33, count 2 2006.173.23:15:28.32#ibcon#read 4, iclass 33, count 2 2006.173.23:15:28.32#ibcon#about to read 5, iclass 33, count 2 2006.173.23:15:28.32#ibcon#read 5, iclass 33, count 2 2006.173.23:15:28.32#ibcon#about to read 6, iclass 33, count 2 2006.173.23:15:28.32#ibcon#read 6, iclass 33, count 2 2006.173.23:15:28.32#ibcon#end of sib2, iclass 33, count 2 2006.173.23:15:28.32#ibcon#*after write, iclass 33, count 2 2006.173.23:15:28.32#ibcon#*before return 0, iclass 33, count 2 2006.173.23:15:28.32#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.23:15:28.32#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.173.23:15:28.32#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.173.23:15:28.32#ibcon#ireg 7 cls_cnt 0 2006.173.23:15:28.32#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.23:15:28.44#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.23:15:28.44#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.23:15:28.44#ibcon#enter wrdev, iclass 33, count 0 2006.173.23:15:28.44#ibcon#first serial, iclass 33, count 0 2006.173.23:15:28.44#ibcon#enter sib2, iclass 33, count 0 2006.173.23:15:28.44#ibcon#flushed, iclass 33, count 0 2006.173.23:15:28.44#ibcon#about to write, iclass 33, count 0 2006.173.23:15:28.44#ibcon#wrote, iclass 33, count 0 2006.173.23:15:28.44#ibcon#about to read 3, iclass 33, count 0 2006.173.23:15:28.46#ibcon#read 3, iclass 33, count 0 2006.173.23:15:28.46#ibcon#about to read 4, iclass 33, count 0 2006.173.23:15:28.46#ibcon#read 4, iclass 33, count 0 2006.173.23:15:28.46#ibcon#about to read 5, iclass 33, count 0 2006.173.23:15:28.46#ibcon#read 5, iclass 33, count 0 2006.173.23:15:28.46#ibcon#about to read 6, iclass 33, count 0 2006.173.23:15:28.46#ibcon#read 6, iclass 33, count 0 2006.173.23:15:28.46#ibcon#end of sib2, iclass 33, count 0 2006.173.23:15:28.46#ibcon#*mode == 0, iclass 33, count 0 2006.173.23:15:28.46#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.23:15:28.46#ibcon#[27=USB\r\n] 2006.173.23:15:28.46#ibcon#*before write, iclass 33, count 0 2006.173.23:15:28.46#ibcon#enter sib2, iclass 33, count 0 2006.173.23:15:28.46#ibcon#flushed, iclass 33, count 0 2006.173.23:15:28.46#ibcon#about to write, iclass 33, count 0 2006.173.23:15:28.46#ibcon#wrote, iclass 33, count 0 2006.173.23:15:28.46#ibcon#about to read 3, iclass 33, count 0 2006.173.23:15:28.49#ibcon#read 3, iclass 33, count 0 2006.173.23:15:28.49#ibcon#about to read 4, iclass 33, count 0 2006.173.23:15:28.49#ibcon#read 4, iclass 33, count 0 2006.173.23:15:28.49#ibcon#about to read 5, iclass 33, count 0 2006.173.23:15:28.49#ibcon#read 5, iclass 33, count 0 2006.173.23:15:28.49#ibcon#about to read 6, iclass 33, count 0 2006.173.23:15:28.49#ibcon#read 6, iclass 33, count 0 2006.173.23:15:28.49#ibcon#end of sib2, iclass 33, count 0 2006.173.23:15:28.49#ibcon#*after write, iclass 33, count 0 2006.173.23:15:28.49#ibcon#*before return 0, iclass 33, count 0 2006.173.23:15:28.49#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.23:15:28.49#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.173.23:15:28.49#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.23:15:28.49#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.23:15:28.49$vck44/vabw=wide 2006.173.23:15:28.49#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.23:15:28.49#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.23:15:28.49#ibcon#ireg 8 cls_cnt 0 2006.173.23:15:28.49#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.23:15:28.49#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.23:15:28.49#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.23:15:28.49#ibcon#enter wrdev, iclass 35, count 0 2006.173.23:15:28.49#ibcon#first serial, iclass 35, count 0 2006.173.23:15:28.49#ibcon#enter sib2, iclass 35, count 0 2006.173.23:15:28.49#ibcon#flushed, iclass 35, count 0 2006.173.23:15:28.49#ibcon#about to write, iclass 35, count 0 2006.173.23:15:28.49#ibcon#wrote, iclass 35, count 0 2006.173.23:15:28.49#ibcon#about to read 3, iclass 35, count 0 2006.173.23:15:28.51#ibcon#read 3, iclass 35, count 0 2006.173.23:15:28.51#ibcon#about to read 4, iclass 35, count 0 2006.173.23:15:28.51#ibcon#read 4, iclass 35, count 0 2006.173.23:15:28.51#ibcon#about to read 5, iclass 35, count 0 2006.173.23:15:28.51#ibcon#read 5, iclass 35, count 0 2006.173.23:15:28.51#ibcon#about to read 6, iclass 35, count 0 2006.173.23:15:28.51#ibcon#read 6, iclass 35, count 0 2006.173.23:15:28.51#ibcon#end of sib2, iclass 35, count 0 2006.173.23:15:28.51#ibcon#*mode == 0, iclass 35, count 0 2006.173.23:15:28.51#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.23:15:28.51#ibcon#[25=BW32\r\n] 2006.173.23:15:28.51#ibcon#*before write, iclass 35, count 0 2006.173.23:15:28.51#ibcon#enter sib2, iclass 35, count 0 2006.173.23:15:28.51#ibcon#flushed, iclass 35, count 0 2006.173.23:15:28.51#ibcon#about to write, iclass 35, count 0 2006.173.23:15:28.51#ibcon#wrote, iclass 35, count 0 2006.173.23:15:28.51#ibcon#about to read 3, iclass 35, count 0 2006.173.23:15:28.54#ibcon#read 3, iclass 35, count 0 2006.173.23:15:28.54#ibcon#about to read 4, iclass 35, count 0 2006.173.23:15:28.54#ibcon#read 4, iclass 35, count 0 2006.173.23:15:28.54#ibcon#about to read 5, iclass 35, count 0 2006.173.23:15:28.54#ibcon#read 5, iclass 35, count 0 2006.173.23:15:28.54#ibcon#about to read 6, iclass 35, count 0 2006.173.23:15:28.54#ibcon#read 6, iclass 35, count 0 2006.173.23:15:28.54#ibcon#end of sib2, iclass 35, count 0 2006.173.23:15:28.54#ibcon#*after write, iclass 35, count 0 2006.173.23:15:28.54#ibcon#*before return 0, iclass 35, count 0 2006.173.23:15:28.54#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.23:15:28.54#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.23:15:28.54#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.23:15:28.54#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.23:15:28.54$vck44/vbbw=wide 2006.173.23:15:28.54#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.23:15:28.54#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.23:15:28.54#ibcon#ireg 8 cls_cnt 0 2006.173.23:15:28.54#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.23:15:28.61#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.23:15:28.61#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.23:15:28.61#ibcon#enter wrdev, iclass 37, count 0 2006.173.23:15:28.61#ibcon#first serial, iclass 37, count 0 2006.173.23:15:28.61#ibcon#enter sib2, iclass 37, count 0 2006.173.23:15:28.61#ibcon#flushed, iclass 37, count 0 2006.173.23:15:28.61#ibcon#about to write, iclass 37, count 0 2006.173.23:15:28.61#ibcon#wrote, iclass 37, count 0 2006.173.23:15:28.61#ibcon#about to read 3, iclass 37, count 0 2006.173.23:15:28.63#ibcon#read 3, iclass 37, count 0 2006.173.23:15:28.63#ibcon#about to read 4, iclass 37, count 0 2006.173.23:15:28.63#ibcon#read 4, iclass 37, count 0 2006.173.23:15:28.63#ibcon#about to read 5, iclass 37, count 0 2006.173.23:15:28.63#ibcon#read 5, iclass 37, count 0 2006.173.23:15:28.63#ibcon#about to read 6, iclass 37, count 0 2006.173.23:15:28.63#ibcon#read 6, iclass 37, count 0 2006.173.23:15:28.63#ibcon#end of sib2, iclass 37, count 0 2006.173.23:15:28.63#ibcon#*mode == 0, iclass 37, count 0 2006.173.23:15:28.63#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.23:15:28.63#ibcon#[27=BW32\r\n] 2006.173.23:15:28.63#ibcon#*before write, iclass 37, count 0 2006.173.23:15:28.63#ibcon#enter sib2, iclass 37, count 0 2006.173.23:15:28.63#ibcon#flushed, iclass 37, count 0 2006.173.23:15:28.63#ibcon#about to write, iclass 37, count 0 2006.173.23:15:28.63#ibcon#wrote, iclass 37, count 0 2006.173.23:15:28.63#ibcon#about to read 3, iclass 37, count 0 2006.173.23:15:28.66#ibcon#read 3, iclass 37, count 0 2006.173.23:15:28.66#ibcon#about to read 4, iclass 37, count 0 2006.173.23:15:28.66#ibcon#read 4, iclass 37, count 0 2006.173.23:15:28.66#ibcon#about to read 5, iclass 37, count 0 2006.173.23:15:28.66#ibcon#read 5, iclass 37, count 0 2006.173.23:15:28.66#ibcon#about to read 6, iclass 37, count 0 2006.173.23:15:28.66#ibcon#read 6, iclass 37, count 0 2006.173.23:15:28.66#ibcon#end of sib2, iclass 37, count 0 2006.173.23:15:28.66#ibcon#*after write, iclass 37, count 0 2006.173.23:15:28.66#ibcon#*before return 0, iclass 37, count 0 2006.173.23:15:28.66#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.23:15:28.66#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.23:15:28.66#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.23:15:28.66#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.23:15:28.66$setupk4/ifdk4 2006.173.23:15:28.66$ifdk4/lo= 2006.173.23:15:28.66$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.23:15:28.66$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.23:15:28.66$ifdk4/patch= 2006.173.23:15:28.66$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.23:15:28.66$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.23:15:28.66$setupk4/!*+20s 2006.173.23:15:31.13#trakl#Source acquired 2006.173.23:15:31.13#flagr#flagr/antenna,acquired 2006.173.23:15:36.87#abcon#<5=/10 1.0 2.0 22.98 901003.2\r\n> 2006.173.23:15:36.89#abcon#{5=INTERFACE CLEAR} 2006.173.23:15:36.95#abcon#[5=S1D000X0/0*\r\n] 2006.173.23:15:43.17$setupk4/"tpicd 2006.173.23:15:43.17$setupk4/echo=off 2006.173.23:15:43.17$setupk4/xlog=off 2006.173.23:15:43.17:!2006.173.23:18:19 2006.173.23:18:19.00:preob 2006.173.23:18:20.14/onsource/TRACKING 2006.173.23:18:20.14:!2006.173.23:18:29 2006.173.23:18:29.00:"tape 2006.173.23:18:29.00:"st=record 2006.173.23:18:29.00:data_valid=on 2006.173.23:18:29.00:midob 2006.173.23:18:29.14/onsource/TRACKING 2006.173.23:18:29.14/wx/22.99,1003.2,91 2006.173.23:18:29.25/cable/+6.5119E-03 2006.173.23:18:30.34/va/01,07,usb,yes,34,37 2006.173.23:18:30.34/va/02,06,usb,yes,34,35 2006.173.23:18:30.34/va/03,05,usb,yes,43,45 2006.173.23:18:30.34/va/04,06,usb,yes,34,36 2006.173.23:18:30.34/va/05,04,usb,yes,27,27 2006.173.23:18:30.34/va/06,03,usb,yes,38,38 2006.173.23:18:30.34/va/07,04,usb,yes,31,32 2006.173.23:18:30.34/va/08,04,usb,yes,26,31 2006.173.23:18:30.57/valo/01,524.99,yes,locked 2006.173.23:18:30.57/valo/02,534.99,yes,locked 2006.173.23:18:30.57/valo/03,564.99,yes,locked 2006.173.23:18:30.57/valo/04,624.99,yes,locked 2006.173.23:18:30.57/valo/05,734.99,yes,locked 2006.173.23:18:30.57/valo/06,814.99,yes,locked 2006.173.23:18:30.57/valo/07,864.99,yes,locked 2006.173.23:18:30.57/valo/08,884.99,yes,locked 2006.173.23:18:31.66/vb/01,04,usb,yes,29,27 2006.173.23:18:31.66/vb/02,04,usb,yes,31,31 2006.173.23:18:31.66/vb/03,04,usb,yes,28,31 2006.173.23:18:31.66/vb/04,04,usb,yes,32,31 2006.173.23:18:31.66/vb/05,04,usb,yes,25,27 2006.173.23:18:31.66/vb/06,04,usb,yes,29,26 2006.173.23:18:31.66/vb/07,04,usb,yes,29,29 2006.173.23:18:31.66/vb/08,04,usb,yes,27,30 2006.173.23:18:31.89/vblo/01,629.99,yes,locked 2006.173.23:18:31.89/vblo/02,634.99,yes,locked 2006.173.23:18:31.89/vblo/03,649.99,yes,locked 2006.173.23:18:31.89/vblo/04,679.99,yes,locked 2006.173.23:18:31.89/vblo/05,709.99,yes,locked 2006.173.23:18:31.89/vblo/06,719.99,yes,locked 2006.173.23:18:31.89/vblo/07,734.99,yes,locked 2006.173.23:18:31.89/vblo/08,744.99,yes,locked 2006.173.23:18:32.04/vabw/8 2006.173.23:18:32.19/vbbw/8 2006.173.23:18:32.33/xfe/off,on,15.0 2006.173.23:18:32.71/ifatt/23,28,28,28 2006.173.23:18:33.07/fmout-gps/S +3.95E-07 2006.173.23:18:33.11:!2006.173.23:27:59 2006.173.23:27:59.00:data_valid=off 2006.173.23:27:59.00:"et 2006.173.23:27:59.00:!+3s 2006.173.23:28:02.01:"tape 2006.173.23:28:02.01:postob 2006.173.23:28:02.13/cable/+6.5104E-03 2006.173.23:28:02.13/wx/23.28,1003.3,88 2006.173.23:28:03.07/fmout-gps/S +3.97E-07 2006.173.23:28:03.07:scan_name=173-2332,jd0606,40 2006.173.23:28:03.07:source=2134+00,213638.59,004154.2,2000.0,ccw 2006.173.23:28:03.14#flagr#flagr/antenna,new-source 2006.173.23:28:04.14:checkk5 2006.173.23:28:04.53/chk_autoobs//k5ts1/ autoobs is running! 2006.173.23:28:04.93/chk_autoobs//k5ts2/ autoobs is running! 2006.173.23:28:05.35/chk_autoobs//k5ts3/ autoobs is running! 2006.173.23:28:05.75/chk_autoobs//k5ts4/ autoobs is running! 2006.173.23:28:06.44/chk_obsdata//k5ts1/T1732318??a.dat file size is correct (nominal:2280MB, actual:2280MB). 2006.173.23:28:07.15/chk_obsdata//k5ts2/T1732318??b.dat file size is correct (nominal:2280MB, actual:2280MB). 2006.173.23:28:07.85/chk_obsdata//k5ts3/T1732318??c.dat file size is correct (nominal:2280MB, actual:2280MB). 2006.173.23:28:08.57/chk_obsdata//k5ts4/T1732318??d.dat file size is correct (nominal:2280MB, actual:2280MB). 2006.173.23:28:09.30/k5log//k5ts1_log_newline 2006.173.23:28:10.02/k5log//k5ts2_log_newline 2006.173.23:28:10.71/k5log//k5ts3_log_newline 2006.173.23:28:11.41/k5log//k5ts4_log_newline 2006.173.23:28:11.44/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.23:28:11.44:setupk4=1 2006.173.23:28:11.44$setupk4/echo=on 2006.173.23:28:11.44$setupk4/pcalon 2006.173.23:28:11.44$pcalon/"no phase cal control is implemented here 2006.173.23:28:11.44$setupk4/"tpicd=stop 2006.173.23:28:11.44$setupk4/"rec=synch_on 2006.173.23:28:11.44$setupk4/"rec_mode=128 2006.173.23:28:11.44$setupk4/!* 2006.173.23:28:11.44$setupk4/recpk4 2006.173.23:28:11.44$recpk4/recpatch= 2006.173.23:28:11.45$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.23:28:11.45$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.23:28:11.45$setupk4/vck44 2006.173.23:28:11.45$vck44/valo=1,524.99 2006.173.23:28:11.45#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.23:28:11.45#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.23:28:11.45#ibcon#ireg 17 cls_cnt 0 2006.173.23:28:11.45#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.23:28:11.45#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.23:28:11.45#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.23:28:11.45#ibcon#enter wrdev, iclass 18, count 0 2006.173.23:28:11.45#ibcon#first serial, iclass 18, count 0 2006.173.23:28:11.45#ibcon#enter sib2, iclass 18, count 0 2006.173.23:28:11.45#ibcon#flushed, iclass 18, count 0 2006.173.23:28:11.45#ibcon#about to write, iclass 18, count 0 2006.173.23:28:11.45#ibcon#wrote, iclass 18, count 0 2006.173.23:28:11.45#ibcon#about to read 3, iclass 18, count 0 2006.173.23:28:11.46#ibcon#read 3, iclass 18, count 0 2006.173.23:28:11.46#ibcon#about to read 4, iclass 18, count 0 2006.173.23:28:11.46#ibcon#read 4, iclass 18, count 0 2006.173.23:28:11.46#ibcon#about to read 5, iclass 18, count 0 2006.173.23:28:11.46#ibcon#read 5, iclass 18, count 0 2006.173.23:28:11.46#ibcon#about to read 6, iclass 18, count 0 2006.173.23:28:11.46#ibcon#read 6, iclass 18, count 0 2006.173.23:28:11.46#ibcon#end of sib2, iclass 18, count 0 2006.173.23:28:11.46#ibcon#*mode == 0, iclass 18, count 0 2006.173.23:28:11.46#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.23:28:11.46#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.23:28:11.46#ibcon#*before write, iclass 18, count 0 2006.173.23:28:11.46#ibcon#enter sib2, iclass 18, count 0 2006.173.23:28:11.46#ibcon#flushed, iclass 18, count 0 2006.173.23:28:11.46#ibcon#about to write, iclass 18, count 0 2006.173.23:28:11.46#ibcon#wrote, iclass 18, count 0 2006.173.23:28:11.46#ibcon#about to read 3, iclass 18, count 0 2006.173.23:28:11.51#ibcon#read 3, iclass 18, count 0 2006.173.23:28:11.51#ibcon#about to read 4, iclass 18, count 0 2006.173.23:28:11.51#ibcon#read 4, iclass 18, count 0 2006.173.23:28:11.51#ibcon#about to read 5, iclass 18, count 0 2006.173.23:28:11.51#ibcon#read 5, iclass 18, count 0 2006.173.23:28:11.51#ibcon#about to read 6, iclass 18, count 0 2006.173.23:28:11.51#ibcon#read 6, iclass 18, count 0 2006.173.23:28:11.51#ibcon#end of sib2, iclass 18, count 0 2006.173.23:28:11.51#ibcon#*after write, iclass 18, count 0 2006.173.23:28:11.51#ibcon#*before return 0, iclass 18, count 0 2006.173.23:28:11.51#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.23:28:11.51#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.23:28:11.51#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.23:28:11.51#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.23:28:11.51$vck44/va=1,7 2006.173.23:28:11.51#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.23:28:11.51#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.23:28:11.51#ibcon#ireg 11 cls_cnt 2 2006.173.23:28:11.51#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.23:28:11.51#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.23:28:11.51#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.23:28:11.51#ibcon#enter wrdev, iclass 20, count 2 2006.173.23:28:11.51#ibcon#first serial, iclass 20, count 2 2006.173.23:28:11.51#ibcon#enter sib2, iclass 20, count 2 2006.173.23:28:11.51#ibcon#flushed, iclass 20, count 2 2006.173.23:28:11.51#ibcon#about to write, iclass 20, count 2 2006.173.23:28:11.51#ibcon#wrote, iclass 20, count 2 2006.173.23:28:11.51#ibcon#about to read 3, iclass 20, count 2 2006.173.23:28:11.53#ibcon#read 3, iclass 20, count 2 2006.173.23:28:11.53#ibcon#about to read 4, iclass 20, count 2 2006.173.23:28:11.53#ibcon#read 4, iclass 20, count 2 2006.173.23:28:11.53#ibcon#about to read 5, iclass 20, count 2 2006.173.23:28:11.53#ibcon#read 5, iclass 20, count 2 2006.173.23:28:11.53#ibcon#about to read 6, iclass 20, count 2 2006.173.23:28:11.53#ibcon#read 6, iclass 20, count 2 2006.173.23:28:11.53#ibcon#end of sib2, iclass 20, count 2 2006.173.23:28:11.53#ibcon#*mode == 0, iclass 20, count 2 2006.173.23:28:11.53#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.23:28:11.53#ibcon#[25=AT01-07\r\n] 2006.173.23:28:11.53#ibcon#*before write, iclass 20, count 2 2006.173.23:28:11.53#ibcon#enter sib2, iclass 20, count 2 2006.173.23:28:11.53#ibcon#flushed, iclass 20, count 2 2006.173.23:28:11.53#ibcon#about to write, iclass 20, count 2 2006.173.23:28:11.53#ibcon#wrote, iclass 20, count 2 2006.173.23:28:11.53#ibcon#about to read 3, iclass 20, count 2 2006.173.23:28:11.56#ibcon#read 3, iclass 20, count 2 2006.173.23:28:11.56#ibcon#about to read 4, iclass 20, count 2 2006.173.23:28:11.56#ibcon#read 4, iclass 20, count 2 2006.173.23:28:11.56#ibcon#about to read 5, iclass 20, count 2 2006.173.23:28:11.56#ibcon#read 5, iclass 20, count 2 2006.173.23:28:11.56#ibcon#about to read 6, iclass 20, count 2 2006.173.23:28:11.56#ibcon#read 6, iclass 20, count 2 2006.173.23:28:11.56#ibcon#end of sib2, iclass 20, count 2 2006.173.23:28:11.56#ibcon#*after write, iclass 20, count 2 2006.173.23:28:11.56#ibcon#*before return 0, iclass 20, count 2 2006.173.23:28:11.56#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.23:28:11.56#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.23:28:11.56#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.23:28:11.56#ibcon#ireg 7 cls_cnt 0 2006.173.23:28:11.56#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.23:28:11.68#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.23:28:11.68#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.23:28:11.68#ibcon#enter wrdev, iclass 20, count 0 2006.173.23:28:11.68#ibcon#first serial, iclass 20, count 0 2006.173.23:28:11.68#ibcon#enter sib2, iclass 20, count 0 2006.173.23:28:11.68#ibcon#flushed, iclass 20, count 0 2006.173.23:28:11.68#ibcon#about to write, iclass 20, count 0 2006.173.23:28:11.68#ibcon#wrote, iclass 20, count 0 2006.173.23:28:11.68#ibcon#about to read 3, iclass 20, count 0 2006.173.23:28:11.70#ibcon#read 3, iclass 20, count 0 2006.173.23:28:11.70#ibcon#about to read 4, iclass 20, count 0 2006.173.23:28:11.70#ibcon#read 4, iclass 20, count 0 2006.173.23:28:11.70#ibcon#about to read 5, iclass 20, count 0 2006.173.23:28:11.70#ibcon#read 5, iclass 20, count 0 2006.173.23:28:11.70#ibcon#about to read 6, iclass 20, count 0 2006.173.23:28:11.70#ibcon#read 6, iclass 20, count 0 2006.173.23:28:11.70#ibcon#end of sib2, iclass 20, count 0 2006.173.23:28:11.70#ibcon#*mode == 0, iclass 20, count 0 2006.173.23:28:11.70#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.23:28:11.70#ibcon#[25=USB\r\n] 2006.173.23:28:11.70#ibcon#*before write, iclass 20, count 0 2006.173.23:28:11.70#ibcon#enter sib2, iclass 20, count 0 2006.173.23:28:11.70#ibcon#flushed, iclass 20, count 0 2006.173.23:28:11.70#ibcon#about to write, iclass 20, count 0 2006.173.23:28:11.70#ibcon#wrote, iclass 20, count 0 2006.173.23:28:11.70#ibcon#about to read 3, iclass 20, count 0 2006.173.23:28:11.73#ibcon#read 3, iclass 20, count 0 2006.173.23:28:11.73#ibcon#about to read 4, iclass 20, count 0 2006.173.23:28:11.73#ibcon#read 4, iclass 20, count 0 2006.173.23:28:11.73#ibcon#about to read 5, iclass 20, count 0 2006.173.23:28:11.73#ibcon#read 5, iclass 20, count 0 2006.173.23:28:11.73#ibcon#about to read 6, iclass 20, count 0 2006.173.23:28:11.73#ibcon#read 6, iclass 20, count 0 2006.173.23:28:11.73#ibcon#end of sib2, iclass 20, count 0 2006.173.23:28:11.73#ibcon#*after write, iclass 20, count 0 2006.173.23:28:11.73#ibcon#*before return 0, iclass 20, count 0 2006.173.23:28:11.73#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.23:28:11.73#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.23:28:11.73#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.23:28:11.73#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.23:28:11.73$vck44/valo=2,534.99 2006.173.23:28:11.73#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.23:28:11.73#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.23:28:11.73#ibcon#ireg 17 cls_cnt 0 2006.173.23:28:11.73#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.23:28:11.73#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.23:28:11.73#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.23:28:11.73#ibcon#enter wrdev, iclass 22, count 0 2006.173.23:28:11.73#ibcon#first serial, iclass 22, count 0 2006.173.23:28:11.73#ibcon#enter sib2, iclass 22, count 0 2006.173.23:28:11.73#ibcon#flushed, iclass 22, count 0 2006.173.23:28:11.73#ibcon#about to write, iclass 22, count 0 2006.173.23:28:11.73#ibcon#wrote, iclass 22, count 0 2006.173.23:28:11.73#ibcon#about to read 3, iclass 22, count 0 2006.173.23:28:11.75#ibcon#read 3, iclass 22, count 0 2006.173.23:28:11.75#ibcon#about to read 4, iclass 22, count 0 2006.173.23:28:11.75#ibcon#read 4, iclass 22, count 0 2006.173.23:28:11.75#ibcon#about to read 5, iclass 22, count 0 2006.173.23:28:11.75#ibcon#read 5, iclass 22, count 0 2006.173.23:28:11.75#ibcon#about to read 6, iclass 22, count 0 2006.173.23:28:11.75#ibcon#read 6, iclass 22, count 0 2006.173.23:28:11.75#ibcon#end of sib2, iclass 22, count 0 2006.173.23:28:11.75#ibcon#*mode == 0, iclass 22, count 0 2006.173.23:28:11.75#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.23:28:11.75#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.23:28:11.75#ibcon#*before write, iclass 22, count 0 2006.173.23:28:11.75#ibcon#enter sib2, iclass 22, count 0 2006.173.23:28:11.75#ibcon#flushed, iclass 22, count 0 2006.173.23:28:11.75#ibcon#about to write, iclass 22, count 0 2006.173.23:28:11.75#ibcon#wrote, iclass 22, count 0 2006.173.23:28:11.75#ibcon#about to read 3, iclass 22, count 0 2006.173.23:28:11.79#ibcon#read 3, iclass 22, count 0 2006.173.23:28:11.79#ibcon#about to read 4, iclass 22, count 0 2006.173.23:28:11.79#ibcon#read 4, iclass 22, count 0 2006.173.23:28:11.79#ibcon#about to read 5, iclass 22, count 0 2006.173.23:28:11.79#ibcon#read 5, iclass 22, count 0 2006.173.23:28:11.79#ibcon#about to read 6, iclass 22, count 0 2006.173.23:28:11.79#ibcon#read 6, iclass 22, count 0 2006.173.23:28:11.79#ibcon#end of sib2, iclass 22, count 0 2006.173.23:28:11.79#ibcon#*after write, iclass 22, count 0 2006.173.23:28:11.79#ibcon#*before return 0, iclass 22, count 0 2006.173.23:28:11.79#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.23:28:11.79#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.23:28:11.79#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.23:28:11.79#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.23:28:11.79$vck44/va=2,6 2006.173.23:28:11.79#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.23:28:11.79#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.23:28:11.79#ibcon#ireg 11 cls_cnt 2 2006.173.23:28:11.79#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.23:28:11.85#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.23:28:11.85#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.23:28:11.85#ibcon#enter wrdev, iclass 24, count 2 2006.173.23:28:11.85#ibcon#first serial, iclass 24, count 2 2006.173.23:28:11.85#ibcon#enter sib2, iclass 24, count 2 2006.173.23:28:11.85#ibcon#flushed, iclass 24, count 2 2006.173.23:28:11.85#ibcon#about to write, iclass 24, count 2 2006.173.23:28:11.85#ibcon#wrote, iclass 24, count 2 2006.173.23:28:11.85#ibcon#about to read 3, iclass 24, count 2 2006.173.23:28:11.87#ibcon#read 3, iclass 24, count 2 2006.173.23:28:11.87#ibcon#about to read 4, iclass 24, count 2 2006.173.23:28:11.87#ibcon#read 4, iclass 24, count 2 2006.173.23:28:11.87#ibcon#about to read 5, iclass 24, count 2 2006.173.23:28:11.87#ibcon#read 5, iclass 24, count 2 2006.173.23:28:11.87#ibcon#about to read 6, iclass 24, count 2 2006.173.23:28:11.87#ibcon#read 6, iclass 24, count 2 2006.173.23:28:11.87#ibcon#end of sib2, iclass 24, count 2 2006.173.23:28:11.87#ibcon#*mode == 0, iclass 24, count 2 2006.173.23:28:11.87#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.23:28:11.87#ibcon#[25=AT02-06\r\n] 2006.173.23:28:11.87#ibcon#*before write, iclass 24, count 2 2006.173.23:28:11.87#ibcon#enter sib2, iclass 24, count 2 2006.173.23:28:11.87#ibcon#flushed, iclass 24, count 2 2006.173.23:28:11.87#ibcon#about to write, iclass 24, count 2 2006.173.23:28:11.87#ibcon#wrote, iclass 24, count 2 2006.173.23:28:11.87#ibcon#about to read 3, iclass 24, count 2 2006.173.23:28:11.90#ibcon#read 3, iclass 24, count 2 2006.173.23:28:11.90#ibcon#about to read 4, iclass 24, count 2 2006.173.23:28:11.90#ibcon#read 4, iclass 24, count 2 2006.173.23:28:11.90#ibcon#about to read 5, iclass 24, count 2 2006.173.23:28:11.90#ibcon#read 5, iclass 24, count 2 2006.173.23:28:11.90#ibcon#about to read 6, iclass 24, count 2 2006.173.23:28:11.90#ibcon#read 6, iclass 24, count 2 2006.173.23:28:11.90#ibcon#end of sib2, iclass 24, count 2 2006.173.23:28:11.90#ibcon#*after write, iclass 24, count 2 2006.173.23:28:11.90#ibcon#*before return 0, iclass 24, count 2 2006.173.23:28:11.90#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.23:28:11.90#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.23:28:11.90#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.23:28:11.90#ibcon#ireg 7 cls_cnt 0 2006.173.23:28:11.90#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.23:28:12.02#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.23:28:12.02#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.23:28:12.02#ibcon#enter wrdev, iclass 24, count 0 2006.173.23:28:12.02#ibcon#first serial, iclass 24, count 0 2006.173.23:28:12.02#ibcon#enter sib2, iclass 24, count 0 2006.173.23:28:12.02#ibcon#flushed, iclass 24, count 0 2006.173.23:28:12.02#ibcon#about to write, iclass 24, count 0 2006.173.23:28:12.02#ibcon#wrote, iclass 24, count 0 2006.173.23:28:12.02#ibcon#about to read 3, iclass 24, count 0 2006.173.23:28:12.04#ibcon#read 3, iclass 24, count 0 2006.173.23:28:12.04#ibcon#about to read 4, iclass 24, count 0 2006.173.23:28:12.04#ibcon#read 4, iclass 24, count 0 2006.173.23:28:12.04#ibcon#about to read 5, iclass 24, count 0 2006.173.23:28:12.04#ibcon#read 5, iclass 24, count 0 2006.173.23:28:12.04#ibcon#about to read 6, iclass 24, count 0 2006.173.23:28:12.04#ibcon#read 6, iclass 24, count 0 2006.173.23:28:12.04#ibcon#end of sib2, iclass 24, count 0 2006.173.23:28:12.04#ibcon#*mode == 0, iclass 24, count 0 2006.173.23:28:12.04#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.23:28:12.04#ibcon#[25=USB\r\n] 2006.173.23:28:12.04#ibcon#*before write, iclass 24, count 0 2006.173.23:28:12.04#ibcon#enter sib2, iclass 24, count 0 2006.173.23:28:12.04#ibcon#flushed, iclass 24, count 0 2006.173.23:28:12.04#ibcon#about to write, iclass 24, count 0 2006.173.23:28:12.04#ibcon#wrote, iclass 24, count 0 2006.173.23:28:12.04#ibcon#about to read 3, iclass 24, count 0 2006.173.23:28:12.07#ibcon#read 3, iclass 24, count 0 2006.173.23:28:12.07#ibcon#about to read 4, iclass 24, count 0 2006.173.23:28:12.07#ibcon#read 4, iclass 24, count 0 2006.173.23:28:12.07#ibcon#about to read 5, iclass 24, count 0 2006.173.23:28:12.07#ibcon#read 5, iclass 24, count 0 2006.173.23:28:12.07#ibcon#about to read 6, iclass 24, count 0 2006.173.23:28:12.07#ibcon#read 6, iclass 24, count 0 2006.173.23:28:12.07#ibcon#end of sib2, iclass 24, count 0 2006.173.23:28:12.07#ibcon#*after write, iclass 24, count 0 2006.173.23:28:12.07#ibcon#*before return 0, iclass 24, count 0 2006.173.23:28:12.07#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.23:28:12.07#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.23:28:12.07#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.23:28:12.07#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.23:28:12.07$vck44/valo=3,564.99 2006.173.23:28:12.07#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.23:28:12.07#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.23:28:12.07#ibcon#ireg 17 cls_cnt 0 2006.173.23:28:12.07#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.23:28:12.07#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.23:28:12.07#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.23:28:12.07#ibcon#enter wrdev, iclass 26, count 0 2006.173.23:28:12.07#ibcon#first serial, iclass 26, count 0 2006.173.23:28:12.07#ibcon#enter sib2, iclass 26, count 0 2006.173.23:28:12.07#ibcon#flushed, iclass 26, count 0 2006.173.23:28:12.07#ibcon#about to write, iclass 26, count 0 2006.173.23:28:12.07#ibcon#wrote, iclass 26, count 0 2006.173.23:28:12.07#ibcon#about to read 3, iclass 26, count 0 2006.173.23:28:12.09#ibcon#read 3, iclass 26, count 0 2006.173.23:28:12.09#ibcon#about to read 4, iclass 26, count 0 2006.173.23:28:12.09#ibcon#read 4, iclass 26, count 0 2006.173.23:28:12.09#ibcon#about to read 5, iclass 26, count 0 2006.173.23:28:12.09#ibcon#read 5, iclass 26, count 0 2006.173.23:28:12.09#ibcon#about to read 6, iclass 26, count 0 2006.173.23:28:12.09#ibcon#read 6, iclass 26, count 0 2006.173.23:28:12.09#ibcon#end of sib2, iclass 26, count 0 2006.173.23:28:12.09#ibcon#*mode == 0, iclass 26, count 0 2006.173.23:28:12.09#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.23:28:12.09#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.23:28:12.09#ibcon#*before write, iclass 26, count 0 2006.173.23:28:12.09#ibcon#enter sib2, iclass 26, count 0 2006.173.23:28:12.09#ibcon#flushed, iclass 26, count 0 2006.173.23:28:12.09#ibcon#about to write, iclass 26, count 0 2006.173.23:28:12.09#ibcon#wrote, iclass 26, count 0 2006.173.23:28:12.09#ibcon#about to read 3, iclass 26, count 0 2006.173.23:28:12.13#ibcon#read 3, iclass 26, count 0 2006.173.23:28:12.13#ibcon#about to read 4, iclass 26, count 0 2006.173.23:28:12.13#ibcon#read 4, iclass 26, count 0 2006.173.23:28:12.13#ibcon#about to read 5, iclass 26, count 0 2006.173.23:28:12.13#ibcon#read 5, iclass 26, count 0 2006.173.23:28:12.13#ibcon#about to read 6, iclass 26, count 0 2006.173.23:28:12.13#ibcon#read 6, iclass 26, count 0 2006.173.23:28:12.13#ibcon#end of sib2, iclass 26, count 0 2006.173.23:28:12.13#ibcon#*after write, iclass 26, count 0 2006.173.23:28:12.13#ibcon#*before return 0, iclass 26, count 0 2006.173.23:28:12.13#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.23:28:12.13#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.23:28:12.13#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.23:28:12.13#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.23:28:12.13$vck44/va=3,5 2006.173.23:28:12.13#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.23:28:12.13#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.23:28:12.13#ibcon#ireg 11 cls_cnt 2 2006.173.23:28:12.13#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.23:28:12.19#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.23:28:12.19#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.23:28:12.19#ibcon#enter wrdev, iclass 28, count 2 2006.173.23:28:12.19#ibcon#first serial, iclass 28, count 2 2006.173.23:28:12.19#ibcon#enter sib2, iclass 28, count 2 2006.173.23:28:12.19#ibcon#flushed, iclass 28, count 2 2006.173.23:28:12.19#ibcon#about to write, iclass 28, count 2 2006.173.23:28:12.19#ibcon#wrote, iclass 28, count 2 2006.173.23:28:12.19#ibcon#about to read 3, iclass 28, count 2 2006.173.23:28:12.21#ibcon#read 3, iclass 28, count 2 2006.173.23:28:12.21#ibcon#about to read 4, iclass 28, count 2 2006.173.23:28:12.21#ibcon#read 4, iclass 28, count 2 2006.173.23:28:12.21#ibcon#about to read 5, iclass 28, count 2 2006.173.23:28:12.21#ibcon#read 5, iclass 28, count 2 2006.173.23:28:12.21#ibcon#about to read 6, iclass 28, count 2 2006.173.23:28:12.21#ibcon#read 6, iclass 28, count 2 2006.173.23:28:12.21#ibcon#end of sib2, iclass 28, count 2 2006.173.23:28:12.21#ibcon#*mode == 0, iclass 28, count 2 2006.173.23:28:12.21#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.23:28:12.21#ibcon#[25=AT03-05\r\n] 2006.173.23:28:12.21#ibcon#*before write, iclass 28, count 2 2006.173.23:28:12.21#ibcon#enter sib2, iclass 28, count 2 2006.173.23:28:12.21#ibcon#flushed, iclass 28, count 2 2006.173.23:28:12.21#ibcon#about to write, iclass 28, count 2 2006.173.23:28:12.21#ibcon#wrote, iclass 28, count 2 2006.173.23:28:12.21#ibcon#about to read 3, iclass 28, count 2 2006.173.23:28:12.24#ibcon#read 3, iclass 28, count 2 2006.173.23:28:12.24#ibcon#about to read 4, iclass 28, count 2 2006.173.23:28:12.24#ibcon#read 4, iclass 28, count 2 2006.173.23:28:12.24#ibcon#about to read 5, iclass 28, count 2 2006.173.23:28:12.24#ibcon#read 5, iclass 28, count 2 2006.173.23:28:12.24#ibcon#about to read 6, iclass 28, count 2 2006.173.23:28:12.24#ibcon#read 6, iclass 28, count 2 2006.173.23:28:12.24#ibcon#end of sib2, iclass 28, count 2 2006.173.23:28:12.24#ibcon#*after write, iclass 28, count 2 2006.173.23:28:12.24#ibcon#*before return 0, iclass 28, count 2 2006.173.23:28:12.24#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.23:28:12.24#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.23:28:12.24#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.23:28:12.24#ibcon#ireg 7 cls_cnt 0 2006.173.23:28:12.24#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.23:28:12.36#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.23:28:12.36#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.23:28:12.36#ibcon#enter wrdev, iclass 28, count 0 2006.173.23:28:12.36#ibcon#first serial, iclass 28, count 0 2006.173.23:28:12.36#ibcon#enter sib2, iclass 28, count 0 2006.173.23:28:12.36#ibcon#flushed, iclass 28, count 0 2006.173.23:28:12.36#ibcon#about to write, iclass 28, count 0 2006.173.23:28:12.36#ibcon#wrote, iclass 28, count 0 2006.173.23:28:12.36#ibcon#about to read 3, iclass 28, count 0 2006.173.23:28:12.38#ibcon#read 3, iclass 28, count 0 2006.173.23:28:12.38#ibcon#about to read 4, iclass 28, count 0 2006.173.23:28:12.38#ibcon#read 4, iclass 28, count 0 2006.173.23:28:12.38#ibcon#about to read 5, iclass 28, count 0 2006.173.23:28:12.38#ibcon#read 5, iclass 28, count 0 2006.173.23:28:12.38#ibcon#about to read 6, iclass 28, count 0 2006.173.23:28:12.38#ibcon#read 6, iclass 28, count 0 2006.173.23:28:12.38#ibcon#end of sib2, iclass 28, count 0 2006.173.23:28:12.38#ibcon#*mode == 0, iclass 28, count 0 2006.173.23:28:12.38#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.23:28:12.38#ibcon#[25=USB\r\n] 2006.173.23:28:12.38#ibcon#*before write, iclass 28, count 0 2006.173.23:28:12.38#ibcon#enter sib2, iclass 28, count 0 2006.173.23:28:12.38#ibcon#flushed, iclass 28, count 0 2006.173.23:28:12.38#ibcon#about to write, iclass 28, count 0 2006.173.23:28:12.38#ibcon#wrote, iclass 28, count 0 2006.173.23:28:12.38#ibcon#about to read 3, iclass 28, count 0 2006.173.23:28:12.41#ibcon#read 3, iclass 28, count 0 2006.173.23:28:12.41#ibcon#about to read 4, iclass 28, count 0 2006.173.23:28:12.41#ibcon#read 4, iclass 28, count 0 2006.173.23:28:12.41#ibcon#about to read 5, iclass 28, count 0 2006.173.23:28:12.41#ibcon#read 5, iclass 28, count 0 2006.173.23:28:12.41#ibcon#about to read 6, iclass 28, count 0 2006.173.23:28:12.41#ibcon#read 6, iclass 28, count 0 2006.173.23:28:12.41#ibcon#end of sib2, iclass 28, count 0 2006.173.23:28:12.41#ibcon#*after write, iclass 28, count 0 2006.173.23:28:12.41#ibcon#*before return 0, iclass 28, count 0 2006.173.23:28:12.41#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.23:28:12.41#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.23:28:12.41#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.23:28:12.41#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.23:28:12.41$vck44/valo=4,624.99 2006.173.23:28:12.41#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.23:28:12.41#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.23:28:12.41#ibcon#ireg 17 cls_cnt 0 2006.173.23:28:12.41#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.23:28:12.41#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.23:28:12.41#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.23:28:12.41#ibcon#enter wrdev, iclass 30, count 0 2006.173.23:28:12.41#ibcon#first serial, iclass 30, count 0 2006.173.23:28:12.41#ibcon#enter sib2, iclass 30, count 0 2006.173.23:28:12.41#ibcon#flushed, iclass 30, count 0 2006.173.23:28:12.41#ibcon#about to write, iclass 30, count 0 2006.173.23:28:12.41#ibcon#wrote, iclass 30, count 0 2006.173.23:28:12.41#ibcon#about to read 3, iclass 30, count 0 2006.173.23:28:12.43#ibcon#read 3, iclass 30, count 0 2006.173.23:28:12.43#ibcon#about to read 4, iclass 30, count 0 2006.173.23:28:12.43#ibcon#read 4, iclass 30, count 0 2006.173.23:28:12.43#ibcon#about to read 5, iclass 30, count 0 2006.173.23:28:12.43#ibcon#read 5, iclass 30, count 0 2006.173.23:28:12.43#ibcon#about to read 6, iclass 30, count 0 2006.173.23:28:12.43#ibcon#read 6, iclass 30, count 0 2006.173.23:28:12.43#ibcon#end of sib2, iclass 30, count 0 2006.173.23:28:12.43#ibcon#*mode == 0, iclass 30, count 0 2006.173.23:28:12.43#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.23:28:12.43#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.23:28:12.43#ibcon#*before write, iclass 30, count 0 2006.173.23:28:12.43#ibcon#enter sib2, iclass 30, count 0 2006.173.23:28:12.43#ibcon#flushed, iclass 30, count 0 2006.173.23:28:12.43#ibcon#about to write, iclass 30, count 0 2006.173.23:28:12.43#ibcon#wrote, iclass 30, count 0 2006.173.23:28:12.43#ibcon#about to read 3, iclass 30, count 0 2006.173.23:28:12.47#ibcon#read 3, iclass 30, count 0 2006.173.23:28:12.47#ibcon#about to read 4, iclass 30, count 0 2006.173.23:28:12.47#ibcon#read 4, iclass 30, count 0 2006.173.23:28:12.47#ibcon#about to read 5, iclass 30, count 0 2006.173.23:28:12.47#ibcon#read 5, iclass 30, count 0 2006.173.23:28:12.47#ibcon#about to read 6, iclass 30, count 0 2006.173.23:28:12.47#ibcon#read 6, iclass 30, count 0 2006.173.23:28:12.47#ibcon#end of sib2, iclass 30, count 0 2006.173.23:28:12.47#ibcon#*after write, iclass 30, count 0 2006.173.23:28:12.47#ibcon#*before return 0, iclass 30, count 0 2006.173.23:28:12.47#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.23:28:12.47#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.23:28:12.47#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.23:28:12.47#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.23:28:12.47$vck44/va=4,6 2006.173.23:28:12.47#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.173.23:28:12.47#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.173.23:28:12.47#ibcon#ireg 11 cls_cnt 2 2006.173.23:28:12.47#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.23:28:12.53#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.23:28:12.53#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.23:28:12.53#ibcon#enter wrdev, iclass 32, count 2 2006.173.23:28:12.53#ibcon#first serial, iclass 32, count 2 2006.173.23:28:12.53#ibcon#enter sib2, iclass 32, count 2 2006.173.23:28:12.53#ibcon#flushed, iclass 32, count 2 2006.173.23:28:12.53#ibcon#about to write, iclass 32, count 2 2006.173.23:28:12.53#ibcon#wrote, iclass 32, count 2 2006.173.23:28:12.53#ibcon#about to read 3, iclass 32, count 2 2006.173.23:28:12.55#ibcon#read 3, iclass 32, count 2 2006.173.23:28:12.55#ibcon#about to read 4, iclass 32, count 2 2006.173.23:28:12.55#ibcon#read 4, iclass 32, count 2 2006.173.23:28:12.55#ibcon#about to read 5, iclass 32, count 2 2006.173.23:28:12.55#ibcon#read 5, iclass 32, count 2 2006.173.23:28:12.55#ibcon#about to read 6, iclass 32, count 2 2006.173.23:28:12.55#ibcon#read 6, iclass 32, count 2 2006.173.23:28:12.55#ibcon#end of sib2, iclass 32, count 2 2006.173.23:28:12.55#ibcon#*mode == 0, iclass 32, count 2 2006.173.23:28:12.55#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.173.23:28:12.55#ibcon#[25=AT04-06\r\n] 2006.173.23:28:12.55#ibcon#*before write, iclass 32, count 2 2006.173.23:28:12.55#ibcon#enter sib2, iclass 32, count 2 2006.173.23:28:12.55#ibcon#flushed, iclass 32, count 2 2006.173.23:28:12.55#ibcon#about to write, iclass 32, count 2 2006.173.23:28:12.55#ibcon#wrote, iclass 32, count 2 2006.173.23:28:12.55#ibcon#about to read 3, iclass 32, count 2 2006.173.23:28:12.58#ibcon#read 3, iclass 32, count 2 2006.173.23:28:12.58#ibcon#about to read 4, iclass 32, count 2 2006.173.23:28:12.58#ibcon#read 4, iclass 32, count 2 2006.173.23:28:12.58#ibcon#about to read 5, iclass 32, count 2 2006.173.23:28:12.58#ibcon#read 5, iclass 32, count 2 2006.173.23:28:12.58#ibcon#about to read 6, iclass 32, count 2 2006.173.23:28:12.58#ibcon#read 6, iclass 32, count 2 2006.173.23:28:12.58#ibcon#end of sib2, iclass 32, count 2 2006.173.23:28:12.58#ibcon#*after write, iclass 32, count 2 2006.173.23:28:12.58#ibcon#*before return 0, iclass 32, count 2 2006.173.23:28:12.58#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.23:28:12.58#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.173.23:28:12.58#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.173.23:28:12.58#ibcon#ireg 7 cls_cnt 0 2006.173.23:28:12.58#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.23:28:12.70#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.23:28:12.70#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.23:28:12.70#ibcon#enter wrdev, iclass 32, count 0 2006.173.23:28:12.70#ibcon#first serial, iclass 32, count 0 2006.173.23:28:12.70#ibcon#enter sib2, iclass 32, count 0 2006.173.23:28:12.70#ibcon#flushed, iclass 32, count 0 2006.173.23:28:12.70#ibcon#about to write, iclass 32, count 0 2006.173.23:28:12.70#ibcon#wrote, iclass 32, count 0 2006.173.23:28:12.70#ibcon#about to read 3, iclass 32, count 0 2006.173.23:28:12.72#ibcon#read 3, iclass 32, count 0 2006.173.23:28:12.72#ibcon#about to read 4, iclass 32, count 0 2006.173.23:28:12.72#ibcon#read 4, iclass 32, count 0 2006.173.23:28:12.72#ibcon#about to read 5, iclass 32, count 0 2006.173.23:28:12.72#ibcon#read 5, iclass 32, count 0 2006.173.23:28:12.72#ibcon#about to read 6, iclass 32, count 0 2006.173.23:28:12.72#ibcon#read 6, iclass 32, count 0 2006.173.23:28:12.72#ibcon#end of sib2, iclass 32, count 0 2006.173.23:28:12.72#ibcon#*mode == 0, iclass 32, count 0 2006.173.23:28:12.72#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.23:28:12.72#ibcon#[25=USB\r\n] 2006.173.23:28:12.72#ibcon#*before write, iclass 32, count 0 2006.173.23:28:12.72#ibcon#enter sib2, iclass 32, count 0 2006.173.23:28:12.72#ibcon#flushed, iclass 32, count 0 2006.173.23:28:12.72#ibcon#about to write, iclass 32, count 0 2006.173.23:28:12.72#ibcon#wrote, iclass 32, count 0 2006.173.23:28:12.72#ibcon#about to read 3, iclass 32, count 0 2006.173.23:28:12.75#ibcon#read 3, iclass 32, count 0 2006.173.23:28:12.75#ibcon#about to read 4, iclass 32, count 0 2006.173.23:28:12.75#ibcon#read 4, iclass 32, count 0 2006.173.23:28:12.75#ibcon#about to read 5, iclass 32, count 0 2006.173.23:28:12.75#ibcon#read 5, iclass 32, count 0 2006.173.23:28:12.75#ibcon#about to read 6, iclass 32, count 0 2006.173.23:28:12.75#ibcon#read 6, iclass 32, count 0 2006.173.23:28:12.75#ibcon#end of sib2, iclass 32, count 0 2006.173.23:28:12.75#ibcon#*after write, iclass 32, count 0 2006.173.23:28:12.75#ibcon#*before return 0, iclass 32, count 0 2006.173.23:28:12.75#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.23:28:12.75#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.173.23:28:12.75#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.23:28:12.75#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.23:28:12.75$vck44/valo=5,734.99 2006.173.23:28:12.75#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.23:28:12.75#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.23:28:12.75#ibcon#ireg 17 cls_cnt 0 2006.173.23:28:12.75#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.23:28:12.75#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.23:28:12.75#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.23:28:12.75#ibcon#enter wrdev, iclass 34, count 0 2006.173.23:28:12.75#ibcon#first serial, iclass 34, count 0 2006.173.23:28:12.75#ibcon#enter sib2, iclass 34, count 0 2006.173.23:28:12.75#ibcon#flushed, iclass 34, count 0 2006.173.23:28:12.75#ibcon#about to write, iclass 34, count 0 2006.173.23:28:12.75#ibcon#wrote, iclass 34, count 0 2006.173.23:28:12.75#ibcon#about to read 3, iclass 34, count 0 2006.173.23:28:12.77#ibcon#read 3, iclass 34, count 0 2006.173.23:28:12.77#ibcon#about to read 4, iclass 34, count 0 2006.173.23:28:12.77#ibcon#read 4, iclass 34, count 0 2006.173.23:28:12.77#ibcon#about to read 5, iclass 34, count 0 2006.173.23:28:12.77#ibcon#read 5, iclass 34, count 0 2006.173.23:28:12.77#ibcon#about to read 6, iclass 34, count 0 2006.173.23:28:12.77#ibcon#read 6, iclass 34, count 0 2006.173.23:28:12.77#ibcon#end of sib2, iclass 34, count 0 2006.173.23:28:12.77#ibcon#*mode == 0, iclass 34, count 0 2006.173.23:28:12.77#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.23:28:12.77#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.23:28:12.77#ibcon#*before write, iclass 34, count 0 2006.173.23:28:12.77#ibcon#enter sib2, iclass 34, count 0 2006.173.23:28:12.77#ibcon#flushed, iclass 34, count 0 2006.173.23:28:12.77#ibcon#about to write, iclass 34, count 0 2006.173.23:28:12.77#ibcon#wrote, iclass 34, count 0 2006.173.23:28:12.77#ibcon#about to read 3, iclass 34, count 0 2006.173.23:28:12.81#ibcon#read 3, iclass 34, count 0 2006.173.23:28:12.81#ibcon#about to read 4, iclass 34, count 0 2006.173.23:28:12.81#ibcon#read 4, iclass 34, count 0 2006.173.23:28:12.81#ibcon#about to read 5, iclass 34, count 0 2006.173.23:28:12.81#ibcon#read 5, iclass 34, count 0 2006.173.23:28:12.81#ibcon#about to read 6, iclass 34, count 0 2006.173.23:28:12.81#ibcon#read 6, iclass 34, count 0 2006.173.23:28:12.81#ibcon#end of sib2, iclass 34, count 0 2006.173.23:28:12.81#ibcon#*after write, iclass 34, count 0 2006.173.23:28:12.81#ibcon#*before return 0, iclass 34, count 0 2006.173.23:28:12.81#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.23:28:12.81#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.23:28:12.81#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.23:28:12.81#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.23:28:12.81$vck44/va=5,4 2006.173.23:28:12.81#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.23:28:12.81#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.23:28:12.81#ibcon#ireg 11 cls_cnt 2 2006.173.23:28:12.81#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.23:28:12.87#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.23:28:12.87#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.23:28:12.87#ibcon#enter wrdev, iclass 36, count 2 2006.173.23:28:12.87#ibcon#first serial, iclass 36, count 2 2006.173.23:28:12.87#ibcon#enter sib2, iclass 36, count 2 2006.173.23:28:12.87#ibcon#flushed, iclass 36, count 2 2006.173.23:28:12.87#ibcon#about to write, iclass 36, count 2 2006.173.23:28:12.87#ibcon#wrote, iclass 36, count 2 2006.173.23:28:12.87#ibcon#about to read 3, iclass 36, count 2 2006.173.23:28:12.89#ibcon#read 3, iclass 36, count 2 2006.173.23:28:12.89#ibcon#about to read 4, iclass 36, count 2 2006.173.23:28:12.89#ibcon#read 4, iclass 36, count 2 2006.173.23:28:12.89#ibcon#about to read 5, iclass 36, count 2 2006.173.23:28:12.89#ibcon#read 5, iclass 36, count 2 2006.173.23:28:12.89#ibcon#about to read 6, iclass 36, count 2 2006.173.23:28:12.89#ibcon#read 6, iclass 36, count 2 2006.173.23:28:12.89#ibcon#end of sib2, iclass 36, count 2 2006.173.23:28:12.89#ibcon#*mode == 0, iclass 36, count 2 2006.173.23:28:12.89#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.23:28:12.89#ibcon#[25=AT05-04\r\n] 2006.173.23:28:12.89#ibcon#*before write, iclass 36, count 2 2006.173.23:28:12.89#ibcon#enter sib2, iclass 36, count 2 2006.173.23:28:12.89#ibcon#flushed, iclass 36, count 2 2006.173.23:28:12.89#ibcon#about to write, iclass 36, count 2 2006.173.23:28:12.89#ibcon#wrote, iclass 36, count 2 2006.173.23:28:12.89#ibcon#about to read 3, iclass 36, count 2 2006.173.23:28:12.92#ibcon#read 3, iclass 36, count 2 2006.173.23:28:12.92#ibcon#about to read 4, iclass 36, count 2 2006.173.23:28:12.92#ibcon#read 4, iclass 36, count 2 2006.173.23:28:12.92#ibcon#about to read 5, iclass 36, count 2 2006.173.23:28:12.92#ibcon#read 5, iclass 36, count 2 2006.173.23:28:12.92#ibcon#about to read 6, iclass 36, count 2 2006.173.23:28:12.92#ibcon#read 6, iclass 36, count 2 2006.173.23:28:12.92#ibcon#end of sib2, iclass 36, count 2 2006.173.23:28:12.92#ibcon#*after write, iclass 36, count 2 2006.173.23:28:12.92#ibcon#*before return 0, iclass 36, count 2 2006.173.23:28:12.92#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.23:28:12.92#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.23:28:12.92#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.23:28:12.92#ibcon#ireg 7 cls_cnt 0 2006.173.23:28:12.92#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.23:28:13.04#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.23:28:13.04#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.23:28:13.04#ibcon#enter wrdev, iclass 36, count 0 2006.173.23:28:13.04#ibcon#first serial, iclass 36, count 0 2006.173.23:28:13.04#ibcon#enter sib2, iclass 36, count 0 2006.173.23:28:13.04#ibcon#flushed, iclass 36, count 0 2006.173.23:28:13.04#ibcon#about to write, iclass 36, count 0 2006.173.23:28:13.04#ibcon#wrote, iclass 36, count 0 2006.173.23:28:13.04#ibcon#about to read 3, iclass 36, count 0 2006.173.23:28:13.06#ibcon#read 3, iclass 36, count 0 2006.173.23:28:13.06#ibcon#about to read 4, iclass 36, count 0 2006.173.23:28:13.06#ibcon#read 4, iclass 36, count 0 2006.173.23:28:13.06#ibcon#about to read 5, iclass 36, count 0 2006.173.23:28:13.06#ibcon#read 5, iclass 36, count 0 2006.173.23:28:13.06#ibcon#about to read 6, iclass 36, count 0 2006.173.23:28:13.06#ibcon#read 6, iclass 36, count 0 2006.173.23:28:13.06#ibcon#end of sib2, iclass 36, count 0 2006.173.23:28:13.06#ibcon#*mode == 0, iclass 36, count 0 2006.173.23:28:13.06#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.23:28:13.06#ibcon#[25=USB\r\n] 2006.173.23:28:13.06#ibcon#*before write, iclass 36, count 0 2006.173.23:28:13.06#ibcon#enter sib2, iclass 36, count 0 2006.173.23:28:13.06#ibcon#flushed, iclass 36, count 0 2006.173.23:28:13.06#ibcon#about to write, iclass 36, count 0 2006.173.23:28:13.06#ibcon#wrote, iclass 36, count 0 2006.173.23:28:13.06#ibcon#about to read 3, iclass 36, count 0 2006.173.23:28:13.09#ibcon#read 3, iclass 36, count 0 2006.173.23:28:13.09#ibcon#about to read 4, iclass 36, count 0 2006.173.23:28:13.09#ibcon#read 4, iclass 36, count 0 2006.173.23:28:13.09#ibcon#about to read 5, iclass 36, count 0 2006.173.23:28:13.09#ibcon#read 5, iclass 36, count 0 2006.173.23:28:13.09#ibcon#about to read 6, iclass 36, count 0 2006.173.23:28:13.09#ibcon#read 6, iclass 36, count 0 2006.173.23:28:13.09#ibcon#end of sib2, iclass 36, count 0 2006.173.23:28:13.09#ibcon#*after write, iclass 36, count 0 2006.173.23:28:13.09#ibcon#*before return 0, iclass 36, count 0 2006.173.23:28:13.09#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.23:28:13.09#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.23:28:13.09#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.23:28:13.09#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.23:28:13.09$vck44/valo=6,814.99 2006.173.23:28:13.09#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.23:28:13.09#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.23:28:13.09#ibcon#ireg 17 cls_cnt 0 2006.173.23:28:13.09#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.23:28:13.09#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.23:28:13.09#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.23:28:13.09#ibcon#enter wrdev, iclass 38, count 0 2006.173.23:28:13.09#ibcon#first serial, iclass 38, count 0 2006.173.23:28:13.09#ibcon#enter sib2, iclass 38, count 0 2006.173.23:28:13.09#ibcon#flushed, iclass 38, count 0 2006.173.23:28:13.09#ibcon#about to write, iclass 38, count 0 2006.173.23:28:13.09#ibcon#wrote, iclass 38, count 0 2006.173.23:28:13.09#ibcon#about to read 3, iclass 38, count 0 2006.173.23:28:13.11#ibcon#read 3, iclass 38, count 0 2006.173.23:28:13.11#ibcon#about to read 4, iclass 38, count 0 2006.173.23:28:13.11#ibcon#read 4, iclass 38, count 0 2006.173.23:28:13.11#ibcon#about to read 5, iclass 38, count 0 2006.173.23:28:13.11#ibcon#read 5, iclass 38, count 0 2006.173.23:28:13.11#ibcon#about to read 6, iclass 38, count 0 2006.173.23:28:13.11#ibcon#read 6, iclass 38, count 0 2006.173.23:28:13.11#ibcon#end of sib2, iclass 38, count 0 2006.173.23:28:13.11#ibcon#*mode == 0, iclass 38, count 0 2006.173.23:28:13.11#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.23:28:13.11#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.23:28:13.11#ibcon#*before write, iclass 38, count 0 2006.173.23:28:13.11#ibcon#enter sib2, iclass 38, count 0 2006.173.23:28:13.11#ibcon#flushed, iclass 38, count 0 2006.173.23:28:13.11#ibcon#about to write, iclass 38, count 0 2006.173.23:28:13.11#ibcon#wrote, iclass 38, count 0 2006.173.23:28:13.11#ibcon#about to read 3, iclass 38, count 0 2006.173.23:28:13.15#ibcon#read 3, iclass 38, count 0 2006.173.23:28:13.15#ibcon#about to read 4, iclass 38, count 0 2006.173.23:28:13.15#ibcon#read 4, iclass 38, count 0 2006.173.23:28:13.15#ibcon#about to read 5, iclass 38, count 0 2006.173.23:28:13.15#ibcon#read 5, iclass 38, count 0 2006.173.23:28:13.15#ibcon#about to read 6, iclass 38, count 0 2006.173.23:28:13.15#ibcon#read 6, iclass 38, count 0 2006.173.23:28:13.15#ibcon#end of sib2, iclass 38, count 0 2006.173.23:28:13.15#ibcon#*after write, iclass 38, count 0 2006.173.23:28:13.15#ibcon#*before return 0, iclass 38, count 0 2006.173.23:28:13.15#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.23:28:13.15#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.23:28:13.15#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.23:28:13.15#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.23:28:13.15$vck44/va=6,3 2006.173.23:28:13.15#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.23:28:13.15#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.23:28:13.15#ibcon#ireg 11 cls_cnt 2 2006.173.23:28:13.15#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.23:28:13.21#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.23:28:13.21#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.23:28:13.21#ibcon#enter wrdev, iclass 40, count 2 2006.173.23:28:13.21#ibcon#first serial, iclass 40, count 2 2006.173.23:28:13.21#ibcon#enter sib2, iclass 40, count 2 2006.173.23:28:13.21#ibcon#flushed, iclass 40, count 2 2006.173.23:28:13.21#ibcon#about to write, iclass 40, count 2 2006.173.23:28:13.21#ibcon#wrote, iclass 40, count 2 2006.173.23:28:13.21#ibcon#about to read 3, iclass 40, count 2 2006.173.23:28:13.23#ibcon#read 3, iclass 40, count 2 2006.173.23:28:13.23#ibcon#about to read 4, iclass 40, count 2 2006.173.23:28:13.23#ibcon#read 4, iclass 40, count 2 2006.173.23:28:13.23#ibcon#about to read 5, iclass 40, count 2 2006.173.23:28:13.23#ibcon#read 5, iclass 40, count 2 2006.173.23:28:13.23#ibcon#about to read 6, iclass 40, count 2 2006.173.23:28:13.23#ibcon#read 6, iclass 40, count 2 2006.173.23:28:13.23#ibcon#end of sib2, iclass 40, count 2 2006.173.23:28:13.23#ibcon#*mode == 0, iclass 40, count 2 2006.173.23:28:13.23#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.23:28:13.23#ibcon#[25=AT06-03\r\n] 2006.173.23:28:13.23#ibcon#*before write, iclass 40, count 2 2006.173.23:28:13.23#ibcon#enter sib2, iclass 40, count 2 2006.173.23:28:13.23#ibcon#flushed, iclass 40, count 2 2006.173.23:28:13.23#ibcon#about to write, iclass 40, count 2 2006.173.23:28:13.23#ibcon#wrote, iclass 40, count 2 2006.173.23:28:13.23#ibcon#about to read 3, iclass 40, count 2 2006.173.23:28:13.26#ibcon#read 3, iclass 40, count 2 2006.173.23:28:13.26#ibcon#about to read 4, iclass 40, count 2 2006.173.23:28:13.26#ibcon#read 4, iclass 40, count 2 2006.173.23:28:13.26#ibcon#about to read 5, iclass 40, count 2 2006.173.23:28:13.26#ibcon#read 5, iclass 40, count 2 2006.173.23:28:13.26#ibcon#about to read 6, iclass 40, count 2 2006.173.23:28:13.26#ibcon#read 6, iclass 40, count 2 2006.173.23:28:13.26#ibcon#end of sib2, iclass 40, count 2 2006.173.23:28:13.26#ibcon#*after write, iclass 40, count 2 2006.173.23:28:13.26#ibcon#*before return 0, iclass 40, count 2 2006.173.23:28:13.26#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.23:28:13.26#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.23:28:13.26#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.23:28:13.26#ibcon#ireg 7 cls_cnt 0 2006.173.23:28:13.26#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.23:28:13.38#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.23:28:13.38#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.23:28:13.38#ibcon#enter wrdev, iclass 40, count 0 2006.173.23:28:13.38#ibcon#first serial, iclass 40, count 0 2006.173.23:28:13.38#ibcon#enter sib2, iclass 40, count 0 2006.173.23:28:13.38#ibcon#flushed, iclass 40, count 0 2006.173.23:28:13.38#ibcon#about to write, iclass 40, count 0 2006.173.23:28:13.38#ibcon#wrote, iclass 40, count 0 2006.173.23:28:13.38#ibcon#about to read 3, iclass 40, count 0 2006.173.23:28:13.40#ibcon#read 3, iclass 40, count 0 2006.173.23:28:13.40#ibcon#about to read 4, iclass 40, count 0 2006.173.23:28:13.40#ibcon#read 4, iclass 40, count 0 2006.173.23:28:13.40#ibcon#about to read 5, iclass 40, count 0 2006.173.23:28:13.40#ibcon#read 5, iclass 40, count 0 2006.173.23:28:13.40#ibcon#about to read 6, iclass 40, count 0 2006.173.23:28:13.40#ibcon#read 6, iclass 40, count 0 2006.173.23:28:13.40#ibcon#end of sib2, iclass 40, count 0 2006.173.23:28:13.40#ibcon#*mode == 0, iclass 40, count 0 2006.173.23:28:13.40#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.23:28:13.40#ibcon#[25=USB\r\n] 2006.173.23:28:13.40#ibcon#*before write, iclass 40, count 0 2006.173.23:28:13.40#ibcon#enter sib2, iclass 40, count 0 2006.173.23:28:13.40#ibcon#flushed, iclass 40, count 0 2006.173.23:28:13.40#ibcon#about to write, iclass 40, count 0 2006.173.23:28:13.40#ibcon#wrote, iclass 40, count 0 2006.173.23:28:13.40#ibcon#about to read 3, iclass 40, count 0 2006.173.23:28:13.43#ibcon#read 3, iclass 40, count 0 2006.173.23:28:13.43#ibcon#about to read 4, iclass 40, count 0 2006.173.23:28:13.43#ibcon#read 4, iclass 40, count 0 2006.173.23:28:13.43#ibcon#about to read 5, iclass 40, count 0 2006.173.23:28:13.43#ibcon#read 5, iclass 40, count 0 2006.173.23:28:13.43#ibcon#about to read 6, iclass 40, count 0 2006.173.23:28:13.43#ibcon#read 6, iclass 40, count 0 2006.173.23:28:13.43#ibcon#end of sib2, iclass 40, count 0 2006.173.23:28:13.43#ibcon#*after write, iclass 40, count 0 2006.173.23:28:13.43#ibcon#*before return 0, iclass 40, count 0 2006.173.23:28:13.43#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.23:28:13.43#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.23:28:13.43#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.23:28:13.43#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.23:28:13.43$vck44/valo=7,864.99 2006.173.23:28:13.43#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.23:28:13.43#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.23:28:13.43#ibcon#ireg 17 cls_cnt 0 2006.173.23:28:13.43#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.23:28:13.43#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.23:28:13.43#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.23:28:13.43#ibcon#enter wrdev, iclass 4, count 0 2006.173.23:28:13.43#ibcon#first serial, iclass 4, count 0 2006.173.23:28:13.43#ibcon#enter sib2, iclass 4, count 0 2006.173.23:28:13.43#ibcon#flushed, iclass 4, count 0 2006.173.23:28:13.43#ibcon#about to write, iclass 4, count 0 2006.173.23:28:13.43#ibcon#wrote, iclass 4, count 0 2006.173.23:28:13.43#ibcon#about to read 3, iclass 4, count 0 2006.173.23:28:13.45#ibcon#read 3, iclass 4, count 0 2006.173.23:28:13.45#ibcon#about to read 4, iclass 4, count 0 2006.173.23:28:13.45#ibcon#read 4, iclass 4, count 0 2006.173.23:28:13.45#ibcon#about to read 5, iclass 4, count 0 2006.173.23:28:13.45#ibcon#read 5, iclass 4, count 0 2006.173.23:28:13.45#ibcon#about to read 6, iclass 4, count 0 2006.173.23:28:13.45#ibcon#read 6, iclass 4, count 0 2006.173.23:28:13.45#ibcon#end of sib2, iclass 4, count 0 2006.173.23:28:13.45#ibcon#*mode == 0, iclass 4, count 0 2006.173.23:28:13.45#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.23:28:13.45#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.23:28:13.45#ibcon#*before write, iclass 4, count 0 2006.173.23:28:13.45#ibcon#enter sib2, iclass 4, count 0 2006.173.23:28:13.45#ibcon#flushed, iclass 4, count 0 2006.173.23:28:13.45#ibcon#about to write, iclass 4, count 0 2006.173.23:28:13.45#ibcon#wrote, iclass 4, count 0 2006.173.23:28:13.45#ibcon#about to read 3, iclass 4, count 0 2006.173.23:28:13.49#ibcon#read 3, iclass 4, count 0 2006.173.23:28:13.49#ibcon#about to read 4, iclass 4, count 0 2006.173.23:28:13.49#ibcon#read 4, iclass 4, count 0 2006.173.23:28:13.49#ibcon#about to read 5, iclass 4, count 0 2006.173.23:28:13.49#ibcon#read 5, iclass 4, count 0 2006.173.23:28:13.49#ibcon#about to read 6, iclass 4, count 0 2006.173.23:28:13.49#ibcon#read 6, iclass 4, count 0 2006.173.23:28:13.49#ibcon#end of sib2, iclass 4, count 0 2006.173.23:28:13.49#ibcon#*after write, iclass 4, count 0 2006.173.23:28:13.49#ibcon#*before return 0, iclass 4, count 0 2006.173.23:28:13.49#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.23:28:13.49#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.23:28:13.49#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.23:28:13.49#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.23:28:13.49$vck44/va=7,4 2006.173.23:28:13.49#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.23:28:13.49#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.23:28:13.49#ibcon#ireg 11 cls_cnt 2 2006.173.23:28:13.49#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.23:28:13.55#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.23:28:13.55#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.23:28:13.55#ibcon#enter wrdev, iclass 6, count 2 2006.173.23:28:13.55#ibcon#first serial, iclass 6, count 2 2006.173.23:28:13.55#ibcon#enter sib2, iclass 6, count 2 2006.173.23:28:13.55#ibcon#flushed, iclass 6, count 2 2006.173.23:28:13.55#ibcon#about to write, iclass 6, count 2 2006.173.23:28:13.55#ibcon#wrote, iclass 6, count 2 2006.173.23:28:13.55#ibcon#about to read 3, iclass 6, count 2 2006.173.23:28:13.57#ibcon#read 3, iclass 6, count 2 2006.173.23:28:13.57#ibcon#about to read 4, iclass 6, count 2 2006.173.23:28:13.57#ibcon#read 4, iclass 6, count 2 2006.173.23:28:13.57#ibcon#about to read 5, iclass 6, count 2 2006.173.23:28:13.57#ibcon#read 5, iclass 6, count 2 2006.173.23:28:13.57#ibcon#about to read 6, iclass 6, count 2 2006.173.23:28:13.57#ibcon#read 6, iclass 6, count 2 2006.173.23:28:13.57#ibcon#end of sib2, iclass 6, count 2 2006.173.23:28:13.57#ibcon#*mode == 0, iclass 6, count 2 2006.173.23:28:13.57#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.23:28:13.57#ibcon#[25=AT07-04\r\n] 2006.173.23:28:13.57#ibcon#*before write, iclass 6, count 2 2006.173.23:28:13.57#ibcon#enter sib2, iclass 6, count 2 2006.173.23:28:13.57#ibcon#flushed, iclass 6, count 2 2006.173.23:28:13.57#ibcon#about to write, iclass 6, count 2 2006.173.23:28:13.57#ibcon#wrote, iclass 6, count 2 2006.173.23:28:13.57#ibcon#about to read 3, iclass 6, count 2 2006.173.23:28:13.60#ibcon#read 3, iclass 6, count 2 2006.173.23:28:13.60#ibcon#about to read 4, iclass 6, count 2 2006.173.23:28:13.60#ibcon#read 4, iclass 6, count 2 2006.173.23:28:13.60#ibcon#about to read 5, iclass 6, count 2 2006.173.23:28:13.60#ibcon#read 5, iclass 6, count 2 2006.173.23:28:13.60#ibcon#about to read 6, iclass 6, count 2 2006.173.23:28:13.60#ibcon#read 6, iclass 6, count 2 2006.173.23:28:13.60#ibcon#end of sib2, iclass 6, count 2 2006.173.23:28:13.60#ibcon#*after write, iclass 6, count 2 2006.173.23:28:13.60#ibcon#*before return 0, iclass 6, count 2 2006.173.23:28:13.60#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.23:28:13.60#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.23:28:13.60#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.23:28:13.60#ibcon#ireg 7 cls_cnt 0 2006.173.23:28:13.60#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.23:28:13.72#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.23:28:13.72#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.23:28:13.72#ibcon#enter wrdev, iclass 6, count 0 2006.173.23:28:13.72#ibcon#first serial, iclass 6, count 0 2006.173.23:28:13.72#ibcon#enter sib2, iclass 6, count 0 2006.173.23:28:13.72#ibcon#flushed, iclass 6, count 0 2006.173.23:28:13.72#ibcon#about to write, iclass 6, count 0 2006.173.23:28:13.72#ibcon#wrote, iclass 6, count 0 2006.173.23:28:13.72#ibcon#about to read 3, iclass 6, count 0 2006.173.23:28:13.74#ibcon#read 3, iclass 6, count 0 2006.173.23:28:13.74#ibcon#about to read 4, iclass 6, count 0 2006.173.23:28:13.74#ibcon#read 4, iclass 6, count 0 2006.173.23:28:13.74#ibcon#about to read 5, iclass 6, count 0 2006.173.23:28:13.74#ibcon#read 5, iclass 6, count 0 2006.173.23:28:13.74#ibcon#about to read 6, iclass 6, count 0 2006.173.23:28:13.74#ibcon#read 6, iclass 6, count 0 2006.173.23:28:13.74#ibcon#end of sib2, iclass 6, count 0 2006.173.23:28:13.74#ibcon#*mode == 0, iclass 6, count 0 2006.173.23:28:13.74#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.23:28:13.74#ibcon#[25=USB\r\n] 2006.173.23:28:13.74#ibcon#*before write, iclass 6, count 0 2006.173.23:28:13.74#ibcon#enter sib2, iclass 6, count 0 2006.173.23:28:13.74#ibcon#flushed, iclass 6, count 0 2006.173.23:28:13.74#ibcon#about to write, iclass 6, count 0 2006.173.23:28:13.74#ibcon#wrote, iclass 6, count 0 2006.173.23:28:13.74#ibcon#about to read 3, iclass 6, count 0 2006.173.23:28:13.77#ibcon#read 3, iclass 6, count 0 2006.173.23:28:13.77#ibcon#about to read 4, iclass 6, count 0 2006.173.23:28:13.77#ibcon#read 4, iclass 6, count 0 2006.173.23:28:13.77#ibcon#about to read 5, iclass 6, count 0 2006.173.23:28:13.77#ibcon#read 5, iclass 6, count 0 2006.173.23:28:13.77#ibcon#about to read 6, iclass 6, count 0 2006.173.23:28:13.77#ibcon#read 6, iclass 6, count 0 2006.173.23:28:13.77#ibcon#end of sib2, iclass 6, count 0 2006.173.23:28:13.77#ibcon#*after write, iclass 6, count 0 2006.173.23:28:13.77#ibcon#*before return 0, iclass 6, count 0 2006.173.23:28:13.77#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.23:28:13.77#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.23:28:13.77#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.23:28:13.77#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.23:28:13.77$vck44/valo=8,884.99 2006.173.23:28:13.77#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.23:28:13.77#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.23:28:13.77#ibcon#ireg 17 cls_cnt 0 2006.173.23:28:13.77#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.23:28:13.77#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.23:28:13.77#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.23:28:13.77#ibcon#enter wrdev, iclass 10, count 0 2006.173.23:28:13.77#ibcon#first serial, iclass 10, count 0 2006.173.23:28:13.77#ibcon#enter sib2, iclass 10, count 0 2006.173.23:28:13.77#ibcon#flushed, iclass 10, count 0 2006.173.23:28:13.77#ibcon#about to write, iclass 10, count 0 2006.173.23:28:13.77#ibcon#wrote, iclass 10, count 0 2006.173.23:28:13.77#ibcon#about to read 3, iclass 10, count 0 2006.173.23:28:13.79#ibcon#read 3, iclass 10, count 0 2006.173.23:28:13.79#ibcon#about to read 4, iclass 10, count 0 2006.173.23:28:13.79#ibcon#read 4, iclass 10, count 0 2006.173.23:28:13.79#ibcon#about to read 5, iclass 10, count 0 2006.173.23:28:13.79#ibcon#read 5, iclass 10, count 0 2006.173.23:28:13.79#ibcon#about to read 6, iclass 10, count 0 2006.173.23:28:13.79#ibcon#read 6, iclass 10, count 0 2006.173.23:28:13.79#ibcon#end of sib2, iclass 10, count 0 2006.173.23:28:13.79#ibcon#*mode == 0, iclass 10, count 0 2006.173.23:28:13.79#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.23:28:13.79#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.23:28:13.79#ibcon#*before write, iclass 10, count 0 2006.173.23:28:13.79#ibcon#enter sib2, iclass 10, count 0 2006.173.23:28:13.79#ibcon#flushed, iclass 10, count 0 2006.173.23:28:13.79#ibcon#about to write, iclass 10, count 0 2006.173.23:28:13.79#ibcon#wrote, iclass 10, count 0 2006.173.23:28:13.79#ibcon#about to read 3, iclass 10, count 0 2006.173.23:28:13.83#ibcon#read 3, iclass 10, count 0 2006.173.23:28:13.83#ibcon#about to read 4, iclass 10, count 0 2006.173.23:28:13.83#ibcon#read 4, iclass 10, count 0 2006.173.23:28:13.83#ibcon#about to read 5, iclass 10, count 0 2006.173.23:28:13.83#ibcon#read 5, iclass 10, count 0 2006.173.23:28:13.83#ibcon#about to read 6, iclass 10, count 0 2006.173.23:28:13.83#ibcon#read 6, iclass 10, count 0 2006.173.23:28:13.83#ibcon#end of sib2, iclass 10, count 0 2006.173.23:28:13.83#ibcon#*after write, iclass 10, count 0 2006.173.23:28:13.83#ibcon#*before return 0, iclass 10, count 0 2006.173.23:28:13.83#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.23:28:13.83#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.23:28:13.83#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.23:28:13.83#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.23:28:13.83$vck44/va=8,4 2006.173.23:28:13.83#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.23:28:13.83#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.23:28:13.83#ibcon#ireg 11 cls_cnt 2 2006.173.23:28:13.83#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.23:28:13.89#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.23:28:13.89#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.23:28:13.89#ibcon#enter wrdev, iclass 12, count 2 2006.173.23:28:13.89#ibcon#first serial, iclass 12, count 2 2006.173.23:28:13.89#ibcon#enter sib2, iclass 12, count 2 2006.173.23:28:13.89#ibcon#flushed, iclass 12, count 2 2006.173.23:28:13.89#ibcon#about to write, iclass 12, count 2 2006.173.23:28:13.89#ibcon#wrote, iclass 12, count 2 2006.173.23:28:13.89#ibcon#about to read 3, iclass 12, count 2 2006.173.23:28:13.91#ibcon#read 3, iclass 12, count 2 2006.173.23:28:13.91#ibcon#about to read 4, iclass 12, count 2 2006.173.23:28:13.91#ibcon#read 4, iclass 12, count 2 2006.173.23:28:13.91#ibcon#about to read 5, iclass 12, count 2 2006.173.23:28:13.91#ibcon#read 5, iclass 12, count 2 2006.173.23:28:13.91#ibcon#about to read 6, iclass 12, count 2 2006.173.23:28:13.91#ibcon#read 6, iclass 12, count 2 2006.173.23:28:13.91#ibcon#end of sib2, iclass 12, count 2 2006.173.23:28:13.91#ibcon#*mode == 0, iclass 12, count 2 2006.173.23:28:13.91#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.23:28:13.91#ibcon#[25=AT08-04\r\n] 2006.173.23:28:13.91#ibcon#*before write, iclass 12, count 2 2006.173.23:28:13.91#ibcon#enter sib2, iclass 12, count 2 2006.173.23:28:13.91#ibcon#flushed, iclass 12, count 2 2006.173.23:28:13.91#ibcon#about to write, iclass 12, count 2 2006.173.23:28:13.91#ibcon#wrote, iclass 12, count 2 2006.173.23:28:13.91#ibcon#about to read 3, iclass 12, count 2 2006.173.23:28:13.94#ibcon#read 3, iclass 12, count 2 2006.173.23:28:13.94#ibcon#about to read 4, iclass 12, count 2 2006.173.23:28:13.94#ibcon#read 4, iclass 12, count 2 2006.173.23:28:13.94#ibcon#about to read 5, iclass 12, count 2 2006.173.23:28:13.94#ibcon#read 5, iclass 12, count 2 2006.173.23:28:13.94#ibcon#about to read 6, iclass 12, count 2 2006.173.23:28:13.94#ibcon#read 6, iclass 12, count 2 2006.173.23:28:13.94#ibcon#end of sib2, iclass 12, count 2 2006.173.23:28:13.94#ibcon#*after write, iclass 12, count 2 2006.173.23:28:13.94#ibcon#*before return 0, iclass 12, count 2 2006.173.23:28:13.94#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.23:28:13.94#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.23:28:13.94#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.23:28:13.94#ibcon#ireg 7 cls_cnt 0 2006.173.23:28:13.94#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.23:28:14.06#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.23:28:14.06#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.23:28:14.06#ibcon#enter wrdev, iclass 12, count 0 2006.173.23:28:14.06#ibcon#first serial, iclass 12, count 0 2006.173.23:28:14.06#ibcon#enter sib2, iclass 12, count 0 2006.173.23:28:14.06#ibcon#flushed, iclass 12, count 0 2006.173.23:28:14.06#ibcon#about to write, iclass 12, count 0 2006.173.23:28:14.06#ibcon#wrote, iclass 12, count 0 2006.173.23:28:14.06#ibcon#about to read 3, iclass 12, count 0 2006.173.23:28:14.08#ibcon#read 3, iclass 12, count 0 2006.173.23:28:14.08#ibcon#about to read 4, iclass 12, count 0 2006.173.23:28:14.08#ibcon#read 4, iclass 12, count 0 2006.173.23:28:14.08#ibcon#about to read 5, iclass 12, count 0 2006.173.23:28:14.08#ibcon#read 5, iclass 12, count 0 2006.173.23:28:14.08#ibcon#about to read 6, iclass 12, count 0 2006.173.23:28:14.08#ibcon#read 6, iclass 12, count 0 2006.173.23:28:14.08#ibcon#end of sib2, iclass 12, count 0 2006.173.23:28:14.08#ibcon#*mode == 0, iclass 12, count 0 2006.173.23:28:14.08#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.23:28:14.08#ibcon#[25=USB\r\n] 2006.173.23:28:14.08#ibcon#*before write, iclass 12, count 0 2006.173.23:28:14.08#ibcon#enter sib2, iclass 12, count 0 2006.173.23:28:14.08#ibcon#flushed, iclass 12, count 0 2006.173.23:28:14.08#ibcon#about to write, iclass 12, count 0 2006.173.23:28:14.08#ibcon#wrote, iclass 12, count 0 2006.173.23:28:14.08#ibcon#about to read 3, iclass 12, count 0 2006.173.23:28:14.11#ibcon#read 3, iclass 12, count 0 2006.173.23:28:14.11#ibcon#about to read 4, iclass 12, count 0 2006.173.23:28:14.11#ibcon#read 4, iclass 12, count 0 2006.173.23:28:14.11#ibcon#about to read 5, iclass 12, count 0 2006.173.23:28:14.11#ibcon#read 5, iclass 12, count 0 2006.173.23:28:14.11#ibcon#about to read 6, iclass 12, count 0 2006.173.23:28:14.11#ibcon#read 6, iclass 12, count 0 2006.173.23:28:14.11#ibcon#end of sib2, iclass 12, count 0 2006.173.23:28:14.11#ibcon#*after write, iclass 12, count 0 2006.173.23:28:14.11#ibcon#*before return 0, iclass 12, count 0 2006.173.23:28:14.11#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.23:28:14.11#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.23:28:14.11#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.23:28:14.11#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.23:28:14.11$vck44/vblo=1,629.99 2006.173.23:28:14.11#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.23:28:14.11#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.23:28:14.11#ibcon#ireg 17 cls_cnt 0 2006.173.23:28:14.11#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.23:28:14.11#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.23:28:14.11#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.23:28:14.11#ibcon#enter wrdev, iclass 14, count 0 2006.173.23:28:14.11#ibcon#first serial, iclass 14, count 0 2006.173.23:28:14.11#ibcon#enter sib2, iclass 14, count 0 2006.173.23:28:14.11#ibcon#flushed, iclass 14, count 0 2006.173.23:28:14.11#ibcon#about to write, iclass 14, count 0 2006.173.23:28:14.11#ibcon#wrote, iclass 14, count 0 2006.173.23:28:14.11#ibcon#about to read 3, iclass 14, count 0 2006.173.23:28:14.13#ibcon#read 3, iclass 14, count 0 2006.173.23:28:14.13#ibcon#about to read 4, iclass 14, count 0 2006.173.23:28:14.13#ibcon#read 4, iclass 14, count 0 2006.173.23:28:14.13#ibcon#about to read 5, iclass 14, count 0 2006.173.23:28:14.13#ibcon#read 5, iclass 14, count 0 2006.173.23:28:14.13#ibcon#about to read 6, iclass 14, count 0 2006.173.23:28:14.13#ibcon#read 6, iclass 14, count 0 2006.173.23:28:14.13#ibcon#end of sib2, iclass 14, count 0 2006.173.23:28:14.13#ibcon#*mode == 0, iclass 14, count 0 2006.173.23:28:14.13#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.23:28:14.13#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.23:28:14.13#ibcon#*before write, iclass 14, count 0 2006.173.23:28:14.13#ibcon#enter sib2, iclass 14, count 0 2006.173.23:28:14.13#ibcon#flushed, iclass 14, count 0 2006.173.23:28:14.13#ibcon#about to write, iclass 14, count 0 2006.173.23:28:14.13#ibcon#wrote, iclass 14, count 0 2006.173.23:28:14.13#ibcon#about to read 3, iclass 14, count 0 2006.173.23:28:14.17#ibcon#read 3, iclass 14, count 0 2006.173.23:28:14.17#ibcon#about to read 4, iclass 14, count 0 2006.173.23:28:14.17#ibcon#read 4, iclass 14, count 0 2006.173.23:28:14.17#ibcon#about to read 5, iclass 14, count 0 2006.173.23:28:14.17#ibcon#read 5, iclass 14, count 0 2006.173.23:28:14.17#ibcon#about to read 6, iclass 14, count 0 2006.173.23:28:14.17#ibcon#read 6, iclass 14, count 0 2006.173.23:28:14.17#ibcon#end of sib2, iclass 14, count 0 2006.173.23:28:14.17#ibcon#*after write, iclass 14, count 0 2006.173.23:28:14.17#ibcon#*before return 0, iclass 14, count 0 2006.173.23:28:14.17#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.23:28:14.17#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.23:28:14.17#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.23:28:14.17#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.23:28:14.17$vck44/vb=1,4 2006.173.23:28:14.17#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.23:28:14.17#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.23:28:14.17#ibcon#ireg 11 cls_cnt 2 2006.173.23:28:14.17#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.23:28:14.17#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.23:28:14.17#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.23:28:14.17#ibcon#enter wrdev, iclass 16, count 2 2006.173.23:28:14.17#ibcon#first serial, iclass 16, count 2 2006.173.23:28:14.17#ibcon#enter sib2, iclass 16, count 2 2006.173.23:28:14.17#ibcon#flushed, iclass 16, count 2 2006.173.23:28:14.17#ibcon#about to write, iclass 16, count 2 2006.173.23:28:14.17#ibcon#wrote, iclass 16, count 2 2006.173.23:28:14.17#ibcon#about to read 3, iclass 16, count 2 2006.173.23:28:14.19#ibcon#read 3, iclass 16, count 2 2006.173.23:28:14.19#ibcon#about to read 4, iclass 16, count 2 2006.173.23:28:14.19#ibcon#read 4, iclass 16, count 2 2006.173.23:28:14.19#ibcon#about to read 5, iclass 16, count 2 2006.173.23:28:14.19#ibcon#read 5, iclass 16, count 2 2006.173.23:28:14.19#ibcon#about to read 6, iclass 16, count 2 2006.173.23:28:14.19#ibcon#read 6, iclass 16, count 2 2006.173.23:28:14.19#ibcon#end of sib2, iclass 16, count 2 2006.173.23:28:14.19#ibcon#*mode == 0, iclass 16, count 2 2006.173.23:28:14.19#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.23:28:14.19#ibcon#[27=AT01-04\r\n] 2006.173.23:28:14.19#ibcon#*before write, iclass 16, count 2 2006.173.23:28:14.19#ibcon#enter sib2, iclass 16, count 2 2006.173.23:28:14.19#ibcon#flushed, iclass 16, count 2 2006.173.23:28:14.19#ibcon#about to write, iclass 16, count 2 2006.173.23:28:14.19#ibcon#wrote, iclass 16, count 2 2006.173.23:28:14.19#ibcon#about to read 3, iclass 16, count 2 2006.173.23:28:14.22#ibcon#read 3, iclass 16, count 2 2006.173.23:28:14.22#ibcon#about to read 4, iclass 16, count 2 2006.173.23:28:14.22#ibcon#read 4, iclass 16, count 2 2006.173.23:28:14.22#ibcon#about to read 5, iclass 16, count 2 2006.173.23:28:14.22#ibcon#read 5, iclass 16, count 2 2006.173.23:28:14.22#ibcon#about to read 6, iclass 16, count 2 2006.173.23:28:14.22#ibcon#read 6, iclass 16, count 2 2006.173.23:28:14.22#ibcon#end of sib2, iclass 16, count 2 2006.173.23:28:14.22#ibcon#*after write, iclass 16, count 2 2006.173.23:28:14.22#ibcon#*before return 0, iclass 16, count 2 2006.173.23:28:14.22#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.23:28:14.22#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.23:28:14.22#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.23:28:14.22#ibcon#ireg 7 cls_cnt 0 2006.173.23:28:14.22#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.23:28:14.34#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.23:28:14.34#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.23:28:14.34#ibcon#enter wrdev, iclass 16, count 0 2006.173.23:28:14.34#ibcon#first serial, iclass 16, count 0 2006.173.23:28:14.34#ibcon#enter sib2, iclass 16, count 0 2006.173.23:28:14.34#ibcon#flushed, iclass 16, count 0 2006.173.23:28:14.34#ibcon#about to write, iclass 16, count 0 2006.173.23:28:14.34#ibcon#wrote, iclass 16, count 0 2006.173.23:28:14.34#ibcon#about to read 3, iclass 16, count 0 2006.173.23:28:14.36#ibcon#read 3, iclass 16, count 0 2006.173.23:28:14.36#ibcon#about to read 4, iclass 16, count 0 2006.173.23:28:14.36#ibcon#read 4, iclass 16, count 0 2006.173.23:28:14.36#ibcon#about to read 5, iclass 16, count 0 2006.173.23:28:14.36#ibcon#read 5, iclass 16, count 0 2006.173.23:28:14.36#ibcon#about to read 6, iclass 16, count 0 2006.173.23:28:14.36#ibcon#read 6, iclass 16, count 0 2006.173.23:28:14.36#ibcon#end of sib2, iclass 16, count 0 2006.173.23:28:14.36#ibcon#*mode == 0, iclass 16, count 0 2006.173.23:28:14.36#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.23:28:14.36#ibcon#[27=USB\r\n] 2006.173.23:28:14.36#ibcon#*before write, iclass 16, count 0 2006.173.23:28:14.36#ibcon#enter sib2, iclass 16, count 0 2006.173.23:28:14.36#ibcon#flushed, iclass 16, count 0 2006.173.23:28:14.36#ibcon#about to write, iclass 16, count 0 2006.173.23:28:14.36#ibcon#wrote, iclass 16, count 0 2006.173.23:28:14.36#ibcon#about to read 3, iclass 16, count 0 2006.173.23:28:14.39#ibcon#read 3, iclass 16, count 0 2006.173.23:28:14.39#ibcon#about to read 4, iclass 16, count 0 2006.173.23:28:14.39#ibcon#read 4, iclass 16, count 0 2006.173.23:28:14.39#ibcon#about to read 5, iclass 16, count 0 2006.173.23:28:14.39#ibcon#read 5, iclass 16, count 0 2006.173.23:28:14.39#ibcon#about to read 6, iclass 16, count 0 2006.173.23:28:14.39#ibcon#read 6, iclass 16, count 0 2006.173.23:28:14.39#ibcon#end of sib2, iclass 16, count 0 2006.173.23:28:14.39#ibcon#*after write, iclass 16, count 0 2006.173.23:28:14.39#ibcon#*before return 0, iclass 16, count 0 2006.173.23:28:14.39#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.23:28:14.39#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.23:28:14.39#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.23:28:14.39#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.23:28:14.39$vck44/vblo=2,634.99 2006.173.23:28:14.39#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.23:28:14.39#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.23:28:14.39#ibcon#ireg 17 cls_cnt 0 2006.173.23:28:14.39#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.23:28:14.39#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.23:28:14.39#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.23:28:14.39#ibcon#enter wrdev, iclass 18, count 0 2006.173.23:28:14.39#ibcon#first serial, iclass 18, count 0 2006.173.23:28:14.39#ibcon#enter sib2, iclass 18, count 0 2006.173.23:28:14.39#ibcon#flushed, iclass 18, count 0 2006.173.23:28:14.39#ibcon#about to write, iclass 18, count 0 2006.173.23:28:14.39#ibcon#wrote, iclass 18, count 0 2006.173.23:28:14.39#ibcon#about to read 3, iclass 18, count 0 2006.173.23:28:14.41#ibcon#read 3, iclass 18, count 0 2006.173.23:28:14.41#ibcon#about to read 4, iclass 18, count 0 2006.173.23:28:14.41#ibcon#read 4, iclass 18, count 0 2006.173.23:28:14.41#ibcon#about to read 5, iclass 18, count 0 2006.173.23:28:14.41#ibcon#read 5, iclass 18, count 0 2006.173.23:28:14.41#ibcon#about to read 6, iclass 18, count 0 2006.173.23:28:14.41#ibcon#read 6, iclass 18, count 0 2006.173.23:28:14.41#ibcon#end of sib2, iclass 18, count 0 2006.173.23:28:14.41#ibcon#*mode == 0, iclass 18, count 0 2006.173.23:28:14.41#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.23:28:14.41#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.23:28:14.41#ibcon#*before write, iclass 18, count 0 2006.173.23:28:14.41#ibcon#enter sib2, iclass 18, count 0 2006.173.23:28:14.41#ibcon#flushed, iclass 18, count 0 2006.173.23:28:14.41#ibcon#about to write, iclass 18, count 0 2006.173.23:28:14.41#ibcon#wrote, iclass 18, count 0 2006.173.23:28:14.41#ibcon#about to read 3, iclass 18, count 0 2006.173.23:28:14.45#ibcon#read 3, iclass 18, count 0 2006.173.23:28:14.45#ibcon#about to read 4, iclass 18, count 0 2006.173.23:28:14.45#ibcon#read 4, iclass 18, count 0 2006.173.23:28:14.45#ibcon#about to read 5, iclass 18, count 0 2006.173.23:28:14.45#ibcon#read 5, iclass 18, count 0 2006.173.23:28:14.45#ibcon#about to read 6, iclass 18, count 0 2006.173.23:28:14.45#ibcon#read 6, iclass 18, count 0 2006.173.23:28:14.45#ibcon#end of sib2, iclass 18, count 0 2006.173.23:28:14.45#ibcon#*after write, iclass 18, count 0 2006.173.23:28:14.45#ibcon#*before return 0, iclass 18, count 0 2006.173.23:28:14.45#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.23:28:14.45#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.23:28:14.45#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.23:28:14.45#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.23:28:14.45$vck44/vb=2,4 2006.173.23:28:14.45#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.23:28:14.45#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.23:28:14.45#ibcon#ireg 11 cls_cnt 2 2006.173.23:28:14.45#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.23:28:14.51#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.23:28:14.51#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.23:28:14.51#ibcon#enter wrdev, iclass 20, count 2 2006.173.23:28:14.51#ibcon#first serial, iclass 20, count 2 2006.173.23:28:14.51#ibcon#enter sib2, iclass 20, count 2 2006.173.23:28:14.51#ibcon#flushed, iclass 20, count 2 2006.173.23:28:14.51#ibcon#about to write, iclass 20, count 2 2006.173.23:28:14.51#ibcon#wrote, iclass 20, count 2 2006.173.23:28:14.51#ibcon#about to read 3, iclass 20, count 2 2006.173.23:28:14.53#ibcon#read 3, iclass 20, count 2 2006.173.23:28:14.53#ibcon#about to read 4, iclass 20, count 2 2006.173.23:28:14.53#ibcon#read 4, iclass 20, count 2 2006.173.23:28:14.53#ibcon#about to read 5, iclass 20, count 2 2006.173.23:28:14.53#ibcon#read 5, iclass 20, count 2 2006.173.23:28:14.53#ibcon#about to read 6, iclass 20, count 2 2006.173.23:28:14.53#ibcon#read 6, iclass 20, count 2 2006.173.23:28:14.53#ibcon#end of sib2, iclass 20, count 2 2006.173.23:28:14.53#ibcon#*mode == 0, iclass 20, count 2 2006.173.23:28:14.53#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.23:28:14.53#ibcon#[27=AT02-04\r\n] 2006.173.23:28:14.53#ibcon#*before write, iclass 20, count 2 2006.173.23:28:14.53#ibcon#enter sib2, iclass 20, count 2 2006.173.23:28:14.53#ibcon#flushed, iclass 20, count 2 2006.173.23:28:14.53#ibcon#about to write, iclass 20, count 2 2006.173.23:28:14.53#ibcon#wrote, iclass 20, count 2 2006.173.23:28:14.53#ibcon#about to read 3, iclass 20, count 2 2006.173.23:28:14.56#ibcon#read 3, iclass 20, count 2 2006.173.23:28:14.56#ibcon#about to read 4, iclass 20, count 2 2006.173.23:28:14.56#ibcon#read 4, iclass 20, count 2 2006.173.23:28:14.56#ibcon#about to read 5, iclass 20, count 2 2006.173.23:28:14.56#ibcon#read 5, iclass 20, count 2 2006.173.23:28:14.56#ibcon#about to read 6, iclass 20, count 2 2006.173.23:28:14.56#ibcon#read 6, iclass 20, count 2 2006.173.23:28:14.56#ibcon#end of sib2, iclass 20, count 2 2006.173.23:28:14.56#ibcon#*after write, iclass 20, count 2 2006.173.23:28:14.56#ibcon#*before return 0, iclass 20, count 2 2006.173.23:28:14.56#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.23:28:14.56#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.23:28:14.56#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.23:28:14.56#ibcon#ireg 7 cls_cnt 0 2006.173.23:28:14.56#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.23:28:14.68#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.23:28:14.68#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.23:28:14.68#ibcon#enter wrdev, iclass 20, count 0 2006.173.23:28:14.68#ibcon#first serial, iclass 20, count 0 2006.173.23:28:14.68#ibcon#enter sib2, iclass 20, count 0 2006.173.23:28:14.68#ibcon#flushed, iclass 20, count 0 2006.173.23:28:14.68#ibcon#about to write, iclass 20, count 0 2006.173.23:28:14.68#ibcon#wrote, iclass 20, count 0 2006.173.23:28:14.68#ibcon#about to read 3, iclass 20, count 0 2006.173.23:28:14.70#ibcon#read 3, iclass 20, count 0 2006.173.23:28:14.70#ibcon#about to read 4, iclass 20, count 0 2006.173.23:28:14.70#ibcon#read 4, iclass 20, count 0 2006.173.23:28:14.70#ibcon#about to read 5, iclass 20, count 0 2006.173.23:28:14.70#ibcon#read 5, iclass 20, count 0 2006.173.23:28:14.70#ibcon#about to read 6, iclass 20, count 0 2006.173.23:28:14.70#ibcon#read 6, iclass 20, count 0 2006.173.23:28:14.70#ibcon#end of sib2, iclass 20, count 0 2006.173.23:28:14.70#ibcon#*mode == 0, iclass 20, count 0 2006.173.23:28:14.70#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.23:28:14.70#ibcon#[27=USB\r\n] 2006.173.23:28:14.70#ibcon#*before write, iclass 20, count 0 2006.173.23:28:14.70#ibcon#enter sib2, iclass 20, count 0 2006.173.23:28:14.70#ibcon#flushed, iclass 20, count 0 2006.173.23:28:14.70#ibcon#about to write, iclass 20, count 0 2006.173.23:28:14.70#ibcon#wrote, iclass 20, count 0 2006.173.23:28:14.70#ibcon#about to read 3, iclass 20, count 0 2006.173.23:28:14.73#ibcon#read 3, iclass 20, count 0 2006.173.23:28:14.73#ibcon#about to read 4, iclass 20, count 0 2006.173.23:28:14.73#ibcon#read 4, iclass 20, count 0 2006.173.23:28:14.73#ibcon#about to read 5, iclass 20, count 0 2006.173.23:28:14.73#ibcon#read 5, iclass 20, count 0 2006.173.23:28:14.73#ibcon#about to read 6, iclass 20, count 0 2006.173.23:28:14.73#ibcon#read 6, iclass 20, count 0 2006.173.23:28:14.73#ibcon#end of sib2, iclass 20, count 0 2006.173.23:28:14.73#ibcon#*after write, iclass 20, count 0 2006.173.23:28:14.73#ibcon#*before return 0, iclass 20, count 0 2006.173.23:28:14.73#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.23:28:14.73#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.23:28:14.73#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.23:28:14.73#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.23:28:14.73$vck44/vblo=3,649.99 2006.173.23:28:14.73#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.23:28:14.73#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.23:28:14.73#ibcon#ireg 17 cls_cnt 0 2006.173.23:28:14.73#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.23:28:14.73#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.23:28:14.73#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.23:28:14.73#ibcon#enter wrdev, iclass 22, count 0 2006.173.23:28:14.73#ibcon#first serial, iclass 22, count 0 2006.173.23:28:14.73#ibcon#enter sib2, iclass 22, count 0 2006.173.23:28:14.73#ibcon#flushed, iclass 22, count 0 2006.173.23:28:14.73#ibcon#about to write, iclass 22, count 0 2006.173.23:28:14.73#ibcon#wrote, iclass 22, count 0 2006.173.23:28:14.73#ibcon#about to read 3, iclass 22, count 0 2006.173.23:28:14.75#ibcon#read 3, iclass 22, count 0 2006.173.23:28:14.75#ibcon#about to read 4, iclass 22, count 0 2006.173.23:28:14.75#ibcon#read 4, iclass 22, count 0 2006.173.23:28:14.75#ibcon#about to read 5, iclass 22, count 0 2006.173.23:28:14.75#ibcon#read 5, iclass 22, count 0 2006.173.23:28:14.75#ibcon#about to read 6, iclass 22, count 0 2006.173.23:28:14.75#ibcon#read 6, iclass 22, count 0 2006.173.23:28:14.75#ibcon#end of sib2, iclass 22, count 0 2006.173.23:28:14.75#ibcon#*mode == 0, iclass 22, count 0 2006.173.23:28:14.75#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.23:28:14.75#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.23:28:14.75#ibcon#*before write, iclass 22, count 0 2006.173.23:28:14.75#ibcon#enter sib2, iclass 22, count 0 2006.173.23:28:14.75#ibcon#flushed, iclass 22, count 0 2006.173.23:28:14.75#ibcon#about to write, iclass 22, count 0 2006.173.23:28:14.75#ibcon#wrote, iclass 22, count 0 2006.173.23:28:14.75#ibcon#about to read 3, iclass 22, count 0 2006.173.23:28:14.79#ibcon#read 3, iclass 22, count 0 2006.173.23:28:14.79#ibcon#about to read 4, iclass 22, count 0 2006.173.23:28:14.79#ibcon#read 4, iclass 22, count 0 2006.173.23:28:14.79#ibcon#about to read 5, iclass 22, count 0 2006.173.23:28:14.79#ibcon#read 5, iclass 22, count 0 2006.173.23:28:14.79#ibcon#about to read 6, iclass 22, count 0 2006.173.23:28:14.79#ibcon#read 6, iclass 22, count 0 2006.173.23:28:14.79#ibcon#end of sib2, iclass 22, count 0 2006.173.23:28:14.79#ibcon#*after write, iclass 22, count 0 2006.173.23:28:14.79#ibcon#*before return 0, iclass 22, count 0 2006.173.23:28:14.79#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.23:28:14.79#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.23:28:14.79#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.23:28:14.79#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.23:28:14.79$vck44/vb=3,4 2006.173.23:28:14.79#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.23:28:14.79#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.23:28:14.79#ibcon#ireg 11 cls_cnt 2 2006.173.23:28:14.79#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.23:28:14.85#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.23:28:14.85#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.23:28:14.85#ibcon#enter wrdev, iclass 24, count 2 2006.173.23:28:14.85#ibcon#first serial, iclass 24, count 2 2006.173.23:28:14.85#ibcon#enter sib2, iclass 24, count 2 2006.173.23:28:14.85#ibcon#flushed, iclass 24, count 2 2006.173.23:28:14.85#ibcon#about to write, iclass 24, count 2 2006.173.23:28:14.85#ibcon#wrote, iclass 24, count 2 2006.173.23:28:14.85#ibcon#about to read 3, iclass 24, count 2 2006.173.23:28:14.87#ibcon#read 3, iclass 24, count 2 2006.173.23:28:14.87#ibcon#about to read 4, iclass 24, count 2 2006.173.23:28:14.87#ibcon#read 4, iclass 24, count 2 2006.173.23:28:14.87#ibcon#about to read 5, iclass 24, count 2 2006.173.23:28:14.87#ibcon#read 5, iclass 24, count 2 2006.173.23:28:14.87#ibcon#about to read 6, iclass 24, count 2 2006.173.23:28:14.87#ibcon#read 6, iclass 24, count 2 2006.173.23:28:14.87#ibcon#end of sib2, iclass 24, count 2 2006.173.23:28:14.87#ibcon#*mode == 0, iclass 24, count 2 2006.173.23:28:14.87#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.23:28:14.87#ibcon#[27=AT03-04\r\n] 2006.173.23:28:14.87#ibcon#*before write, iclass 24, count 2 2006.173.23:28:14.87#ibcon#enter sib2, iclass 24, count 2 2006.173.23:28:14.87#ibcon#flushed, iclass 24, count 2 2006.173.23:28:14.87#ibcon#about to write, iclass 24, count 2 2006.173.23:28:14.87#ibcon#wrote, iclass 24, count 2 2006.173.23:28:14.87#ibcon#about to read 3, iclass 24, count 2 2006.173.23:28:14.90#ibcon#read 3, iclass 24, count 2 2006.173.23:28:14.90#ibcon#about to read 4, iclass 24, count 2 2006.173.23:28:14.90#ibcon#read 4, iclass 24, count 2 2006.173.23:28:14.90#ibcon#about to read 5, iclass 24, count 2 2006.173.23:28:14.90#ibcon#read 5, iclass 24, count 2 2006.173.23:28:14.90#ibcon#about to read 6, iclass 24, count 2 2006.173.23:28:14.90#ibcon#read 6, iclass 24, count 2 2006.173.23:28:14.90#ibcon#end of sib2, iclass 24, count 2 2006.173.23:28:14.90#ibcon#*after write, iclass 24, count 2 2006.173.23:28:14.90#ibcon#*before return 0, iclass 24, count 2 2006.173.23:28:14.90#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.23:28:14.90#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.23:28:14.90#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.23:28:14.90#ibcon#ireg 7 cls_cnt 0 2006.173.23:28:14.90#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.23:28:15.02#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.23:28:15.02#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.23:28:15.02#ibcon#enter wrdev, iclass 24, count 0 2006.173.23:28:15.02#ibcon#first serial, iclass 24, count 0 2006.173.23:28:15.02#ibcon#enter sib2, iclass 24, count 0 2006.173.23:28:15.02#ibcon#flushed, iclass 24, count 0 2006.173.23:28:15.02#ibcon#about to write, iclass 24, count 0 2006.173.23:28:15.02#ibcon#wrote, iclass 24, count 0 2006.173.23:28:15.02#ibcon#about to read 3, iclass 24, count 0 2006.173.23:28:15.04#ibcon#read 3, iclass 24, count 0 2006.173.23:28:15.04#ibcon#about to read 4, iclass 24, count 0 2006.173.23:28:15.04#ibcon#read 4, iclass 24, count 0 2006.173.23:28:15.04#ibcon#about to read 5, iclass 24, count 0 2006.173.23:28:15.04#ibcon#read 5, iclass 24, count 0 2006.173.23:28:15.04#ibcon#about to read 6, iclass 24, count 0 2006.173.23:28:15.04#ibcon#read 6, iclass 24, count 0 2006.173.23:28:15.04#ibcon#end of sib2, iclass 24, count 0 2006.173.23:28:15.04#ibcon#*mode == 0, iclass 24, count 0 2006.173.23:28:15.04#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.23:28:15.04#ibcon#[27=USB\r\n] 2006.173.23:28:15.04#ibcon#*before write, iclass 24, count 0 2006.173.23:28:15.04#ibcon#enter sib2, iclass 24, count 0 2006.173.23:28:15.04#ibcon#flushed, iclass 24, count 0 2006.173.23:28:15.04#ibcon#about to write, iclass 24, count 0 2006.173.23:28:15.04#ibcon#wrote, iclass 24, count 0 2006.173.23:28:15.04#ibcon#about to read 3, iclass 24, count 0 2006.173.23:28:15.07#ibcon#read 3, iclass 24, count 0 2006.173.23:28:15.07#ibcon#about to read 4, iclass 24, count 0 2006.173.23:28:15.07#ibcon#read 4, iclass 24, count 0 2006.173.23:28:15.07#ibcon#about to read 5, iclass 24, count 0 2006.173.23:28:15.07#ibcon#read 5, iclass 24, count 0 2006.173.23:28:15.07#ibcon#about to read 6, iclass 24, count 0 2006.173.23:28:15.07#ibcon#read 6, iclass 24, count 0 2006.173.23:28:15.07#ibcon#end of sib2, iclass 24, count 0 2006.173.23:28:15.07#ibcon#*after write, iclass 24, count 0 2006.173.23:28:15.07#ibcon#*before return 0, iclass 24, count 0 2006.173.23:28:15.07#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.23:28:15.07#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.23:28:15.07#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.23:28:15.07#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.23:28:15.07$vck44/vblo=4,679.99 2006.173.23:28:15.07#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.23:28:15.07#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.23:28:15.07#ibcon#ireg 17 cls_cnt 0 2006.173.23:28:15.07#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.23:28:15.07#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.23:28:15.07#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.23:28:15.07#ibcon#enter wrdev, iclass 26, count 0 2006.173.23:28:15.07#ibcon#first serial, iclass 26, count 0 2006.173.23:28:15.07#ibcon#enter sib2, iclass 26, count 0 2006.173.23:28:15.07#ibcon#flushed, iclass 26, count 0 2006.173.23:28:15.07#ibcon#about to write, iclass 26, count 0 2006.173.23:28:15.07#ibcon#wrote, iclass 26, count 0 2006.173.23:28:15.07#ibcon#about to read 3, iclass 26, count 0 2006.173.23:28:15.09#ibcon#read 3, iclass 26, count 0 2006.173.23:28:15.09#ibcon#about to read 4, iclass 26, count 0 2006.173.23:28:15.09#ibcon#read 4, iclass 26, count 0 2006.173.23:28:15.09#ibcon#about to read 5, iclass 26, count 0 2006.173.23:28:15.09#ibcon#read 5, iclass 26, count 0 2006.173.23:28:15.09#ibcon#about to read 6, iclass 26, count 0 2006.173.23:28:15.09#ibcon#read 6, iclass 26, count 0 2006.173.23:28:15.09#ibcon#end of sib2, iclass 26, count 0 2006.173.23:28:15.09#ibcon#*mode == 0, iclass 26, count 0 2006.173.23:28:15.09#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.23:28:15.09#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.23:28:15.09#ibcon#*before write, iclass 26, count 0 2006.173.23:28:15.09#ibcon#enter sib2, iclass 26, count 0 2006.173.23:28:15.09#ibcon#flushed, iclass 26, count 0 2006.173.23:28:15.09#ibcon#about to write, iclass 26, count 0 2006.173.23:28:15.09#ibcon#wrote, iclass 26, count 0 2006.173.23:28:15.09#ibcon#about to read 3, iclass 26, count 0 2006.173.23:28:15.13#ibcon#read 3, iclass 26, count 0 2006.173.23:28:15.13#ibcon#about to read 4, iclass 26, count 0 2006.173.23:28:15.13#ibcon#read 4, iclass 26, count 0 2006.173.23:28:15.13#ibcon#about to read 5, iclass 26, count 0 2006.173.23:28:15.13#ibcon#read 5, iclass 26, count 0 2006.173.23:28:15.13#ibcon#about to read 6, iclass 26, count 0 2006.173.23:28:15.13#ibcon#read 6, iclass 26, count 0 2006.173.23:28:15.13#ibcon#end of sib2, iclass 26, count 0 2006.173.23:28:15.13#ibcon#*after write, iclass 26, count 0 2006.173.23:28:15.13#ibcon#*before return 0, iclass 26, count 0 2006.173.23:28:15.13#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.23:28:15.13#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.23:28:15.13#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.23:28:15.13#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.23:28:15.13$vck44/vb=4,4 2006.173.23:28:15.13#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.23:28:15.13#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.23:28:15.13#ibcon#ireg 11 cls_cnt 2 2006.173.23:28:15.13#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.23:28:15.19#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.23:28:15.19#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.23:28:15.19#ibcon#enter wrdev, iclass 28, count 2 2006.173.23:28:15.19#ibcon#first serial, iclass 28, count 2 2006.173.23:28:15.19#ibcon#enter sib2, iclass 28, count 2 2006.173.23:28:15.19#ibcon#flushed, iclass 28, count 2 2006.173.23:28:15.19#ibcon#about to write, iclass 28, count 2 2006.173.23:28:15.19#ibcon#wrote, iclass 28, count 2 2006.173.23:28:15.19#ibcon#about to read 3, iclass 28, count 2 2006.173.23:28:15.21#ibcon#read 3, iclass 28, count 2 2006.173.23:28:15.21#ibcon#about to read 4, iclass 28, count 2 2006.173.23:28:15.21#ibcon#read 4, iclass 28, count 2 2006.173.23:28:15.21#ibcon#about to read 5, iclass 28, count 2 2006.173.23:28:15.21#ibcon#read 5, iclass 28, count 2 2006.173.23:28:15.21#ibcon#about to read 6, iclass 28, count 2 2006.173.23:28:15.21#ibcon#read 6, iclass 28, count 2 2006.173.23:28:15.21#ibcon#end of sib2, iclass 28, count 2 2006.173.23:28:15.21#ibcon#*mode == 0, iclass 28, count 2 2006.173.23:28:15.21#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.23:28:15.21#ibcon#[27=AT04-04\r\n] 2006.173.23:28:15.21#ibcon#*before write, iclass 28, count 2 2006.173.23:28:15.21#ibcon#enter sib2, iclass 28, count 2 2006.173.23:28:15.21#ibcon#flushed, iclass 28, count 2 2006.173.23:28:15.21#ibcon#about to write, iclass 28, count 2 2006.173.23:28:15.21#ibcon#wrote, iclass 28, count 2 2006.173.23:28:15.21#ibcon#about to read 3, iclass 28, count 2 2006.173.23:28:15.24#ibcon#read 3, iclass 28, count 2 2006.173.23:28:15.24#ibcon#about to read 4, iclass 28, count 2 2006.173.23:28:15.24#ibcon#read 4, iclass 28, count 2 2006.173.23:28:15.24#ibcon#about to read 5, iclass 28, count 2 2006.173.23:28:15.24#ibcon#read 5, iclass 28, count 2 2006.173.23:28:15.24#ibcon#about to read 6, iclass 28, count 2 2006.173.23:28:15.24#ibcon#read 6, iclass 28, count 2 2006.173.23:28:15.24#ibcon#end of sib2, iclass 28, count 2 2006.173.23:28:15.24#ibcon#*after write, iclass 28, count 2 2006.173.23:28:15.24#ibcon#*before return 0, iclass 28, count 2 2006.173.23:28:15.24#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.23:28:15.24#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.23:28:15.24#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.23:28:15.24#ibcon#ireg 7 cls_cnt 0 2006.173.23:28:15.24#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.23:28:15.36#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.23:28:15.36#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.23:28:15.36#ibcon#enter wrdev, iclass 28, count 0 2006.173.23:28:15.36#ibcon#first serial, iclass 28, count 0 2006.173.23:28:15.36#ibcon#enter sib2, iclass 28, count 0 2006.173.23:28:15.36#ibcon#flushed, iclass 28, count 0 2006.173.23:28:15.36#ibcon#about to write, iclass 28, count 0 2006.173.23:28:15.36#ibcon#wrote, iclass 28, count 0 2006.173.23:28:15.36#ibcon#about to read 3, iclass 28, count 0 2006.173.23:28:15.38#ibcon#read 3, iclass 28, count 0 2006.173.23:28:15.38#ibcon#about to read 4, iclass 28, count 0 2006.173.23:28:15.38#ibcon#read 4, iclass 28, count 0 2006.173.23:28:15.38#ibcon#about to read 5, iclass 28, count 0 2006.173.23:28:15.38#ibcon#read 5, iclass 28, count 0 2006.173.23:28:15.38#ibcon#about to read 6, iclass 28, count 0 2006.173.23:28:15.38#ibcon#read 6, iclass 28, count 0 2006.173.23:28:15.38#ibcon#end of sib2, iclass 28, count 0 2006.173.23:28:15.38#ibcon#*mode == 0, iclass 28, count 0 2006.173.23:28:15.38#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.23:28:15.38#ibcon#[27=USB\r\n] 2006.173.23:28:15.38#ibcon#*before write, iclass 28, count 0 2006.173.23:28:15.38#ibcon#enter sib2, iclass 28, count 0 2006.173.23:28:15.38#ibcon#flushed, iclass 28, count 0 2006.173.23:28:15.38#ibcon#about to write, iclass 28, count 0 2006.173.23:28:15.38#ibcon#wrote, iclass 28, count 0 2006.173.23:28:15.38#ibcon#about to read 3, iclass 28, count 0 2006.173.23:28:15.41#ibcon#read 3, iclass 28, count 0 2006.173.23:28:15.41#ibcon#about to read 4, iclass 28, count 0 2006.173.23:28:15.41#ibcon#read 4, iclass 28, count 0 2006.173.23:28:15.41#ibcon#about to read 5, iclass 28, count 0 2006.173.23:28:15.41#ibcon#read 5, iclass 28, count 0 2006.173.23:28:15.41#ibcon#about to read 6, iclass 28, count 0 2006.173.23:28:15.41#ibcon#read 6, iclass 28, count 0 2006.173.23:28:15.41#ibcon#end of sib2, iclass 28, count 0 2006.173.23:28:15.41#ibcon#*after write, iclass 28, count 0 2006.173.23:28:15.41#ibcon#*before return 0, iclass 28, count 0 2006.173.23:28:15.41#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.23:28:15.41#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.23:28:15.41#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.23:28:15.41#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.23:28:15.41$vck44/vblo=5,709.99 2006.173.23:28:15.41#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.23:28:15.41#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.23:28:15.41#ibcon#ireg 17 cls_cnt 0 2006.173.23:28:15.41#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.23:28:15.41#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.23:28:15.41#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.23:28:15.41#ibcon#enter wrdev, iclass 30, count 0 2006.173.23:28:15.41#ibcon#first serial, iclass 30, count 0 2006.173.23:28:15.41#ibcon#enter sib2, iclass 30, count 0 2006.173.23:28:15.41#ibcon#flushed, iclass 30, count 0 2006.173.23:28:15.41#ibcon#about to write, iclass 30, count 0 2006.173.23:28:15.41#ibcon#wrote, iclass 30, count 0 2006.173.23:28:15.41#ibcon#about to read 3, iclass 30, count 0 2006.173.23:28:15.43#ibcon#read 3, iclass 30, count 0 2006.173.23:28:15.43#ibcon#about to read 4, iclass 30, count 0 2006.173.23:28:15.43#ibcon#read 4, iclass 30, count 0 2006.173.23:28:15.43#ibcon#about to read 5, iclass 30, count 0 2006.173.23:28:15.43#ibcon#read 5, iclass 30, count 0 2006.173.23:28:15.43#ibcon#about to read 6, iclass 30, count 0 2006.173.23:28:15.43#ibcon#read 6, iclass 30, count 0 2006.173.23:28:15.43#ibcon#end of sib2, iclass 30, count 0 2006.173.23:28:15.43#ibcon#*mode == 0, iclass 30, count 0 2006.173.23:28:15.43#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.23:28:15.43#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.23:28:15.43#ibcon#*before write, iclass 30, count 0 2006.173.23:28:15.43#ibcon#enter sib2, iclass 30, count 0 2006.173.23:28:15.43#ibcon#flushed, iclass 30, count 0 2006.173.23:28:15.43#ibcon#about to write, iclass 30, count 0 2006.173.23:28:15.43#ibcon#wrote, iclass 30, count 0 2006.173.23:28:15.43#ibcon#about to read 3, iclass 30, count 0 2006.173.23:28:15.47#ibcon#read 3, iclass 30, count 0 2006.173.23:28:15.47#ibcon#about to read 4, iclass 30, count 0 2006.173.23:28:15.47#ibcon#read 4, iclass 30, count 0 2006.173.23:28:15.47#ibcon#about to read 5, iclass 30, count 0 2006.173.23:28:15.47#ibcon#read 5, iclass 30, count 0 2006.173.23:28:15.47#ibcon#about to read 6, iclass 30, count 0 2006.173.23:28:15.47#ibcon#read 6, iclass 30, count 0 2006.173.23:28:15.47#ibcon#end of sib2, iclass 30, count 0 2006.173.23:28:15.47#ibcon#*after write, iclass 30, count 0 2006.173.23:28:15.47#ibcon#*before return 0, iclass 30, count 0 2006.173.23:28:15.47#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.23:28:15.47#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.23:28:15.47#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.23:28:15.47#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.23:28:15.47$vck44/vb=5,4 2006.173.23:28:15.47#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.173.23:28:15.47#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.173.23:28:15.47#ibcon#ireg 11 cls_cnt 2 2006.173.23:28:15.47#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.23:28:15.53#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.23:28:15.53#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.23:28:15.53#ibcon#enter wrdev, iclass 32, count 2 2006.173.23:28:15.53#ibcon#first serial, iclass 32, count 2 2006.173.23:28:15.53#ibcon#enter sib2, iclass 32, count 2 2006.173.23:28:15.53#ibcon#flushed, iclass 32, count 2 2006.173.23:28:15.53#ibcon#about to write, iclass 32, count 2 2006.173.23:28:15.53#ibcon#wrote, iclass 32, count 2 2006.173.23:28:15.53#ibcon#about to read 3, iclass 32, count 2 2006.173.23:28:15.55#ibcon#read 3, iclass 32, count 2 2006.173.23:28:15.55#ibcon#about to read 4, iclass 32, count 2 2006.173.23:28:15.55#ibcon#read 4, iclass 32, count 2 2006.173.23:28:15.55#ibcon#about to read 5, iclass 32, count 2 2006.173.23:28:15.55#ibcon#read 5, iclass 32, count 2 2006.173.23:28:15.55#ibcon#about to read 6, iclass 32, count 2 2006.173.23:28:15.55#ibcon#read 6, iclass 32, count 2 2006.173.23:28:15.55#ibcon#end of sib2, iclass 32, count 2 2006.173.23:28:15.55#ibcon#*mode == 0, iclass 32, count 2 2006.173.23:28:15.55#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.173.23:28:15.55#ibcon#[27=AT05-04\r\n] 2006.173.23:28:15.55#ibcon#*before write, iclass 32, count 2 2006.173.23:28:15.55#ibcon#enter sib2, iclass 32, count 2 2006.173.23:28:15.55#ibcon#flushed, iclass 32, count 2 2006.173.23:28:15.55#ibcon#about to write, iclass 32, count 2 2006.173.23:28:15.55#ibcon#wrote, iclass 32, count 2 2006.173.23:28:15.55#ibcon#about to read 3, iclass 32, count 2 2006.173.23:28:15.58#ibcon#read 3, iclass 32, count 2 2006.173.23:28:15.58#ibcon#about to read 4, iclass 32, count 2 2006.173.23:28:15.58#ibcon#read 4, iclass 32, count 2 2006.173.23:28:15.58#ibcon#about to read 5, iclass 32, count 2 2006.173.23:28:15.58#ibcon#read 5, iclass 32, count 2 2006.173.23:28:15.58#ibcon#about to read 6, iclass 32, count 2 2006.173.23:28:15.58#ibcon#read 6, iclass 32, count 2 2006.173.23:28:15.58#ibcon#end of sib2, iclass 32, count 2 2006.173.23:28:15.58#ibcon#*after write, iclass 32, count 2 2006.173.23:28:15.58#ibcon#*before return 0, iclass 32, count 2 2006.173.23:28:15.58#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.23:28:15.58#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.173.23:28:15.58#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.173.23:28:15.58#ibcon#ireg 7 cls_cnt 0 2006.173.23:28:15.58#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.23:28:15.70#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.23:28:15.70#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.23:28:15.70#ibcon#enter wrdev, iclass 32, count 0 2006.173.23:28:15.70#ibcon#first serial, iclass 32, count 0 2006.173.23:28:15.70#ibcon#enter sib2, iclass 32, count 0 2006.173.23:28:15.70#ibcon#flushed, iclass 32, count 0 2006.173.23:28:15.70#ibcon#about to write, iclass 32, count 0 2006.173.23:28:15.70#ibcon#wrote, iclass 32, count 0 2006.173.23:28:15.70#ibcon#about to read 3, iclass 32, count 0 2006.173.23:28:15.72#ibcon#read 3, iclass 32, count 0 2006.173.23:28:15.72#ibcon#about to read 4, iclass 32, count 0 2006.173.23:28:15.72#ibcon#read 4, iclass 32, count 0 2006.173.23:28:15.72#ibcon#about to read 5, iclass 32, count 0 2006.173.23:28:15.72#ibcon#read 5, iclass 32, count 0 2006.173.23:28:15.72#ibcon#about to read 6, iclass 32, count 0 2006.173.23:28:15.72#ibcon#read 6, iclass 32, count 0 2006.173.23:28:15.72#ibcon#end of sib2, iclass 32, count 0 2006.173.23:28:15.72#ibcon#*mode == 0, iclass 32, count 0 2006.173.23:28:15.72#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.23:28:15.72#ibcon#[27=USB\r\n] 2006.173.23:28:15.72#ibcon#*before write, iclass 32, count 0 2006.173.23:28:15.72#ibcon#enter sib2, iclass 32, count 0 2006.173.23:28:15.72#ibcon#flushed, iclass 32, count 0 2006.173.23:28:15.72#ibcon#about to write, iclass 32, count 0 2006.173.23:28:15.72#ibcon#wrote, iclass 32, count 0 2006.173.23:28:15.72#ibcon#about to read 3, iclass 32, count 0 2006.173.23:28:15.75#ibcon#read 3, iclass 32, count 0 2006.173.23:28:15.75#ibcon#about to read 4, iclass 32, count 0 2006.173.23:28:15.75#ibcon#read 4, iclass 32, count 0 2006.173.23:28:15.75#ibcon#about to read 5, iclass 32, count 0 2006.173.23:28:15.75#ibcon#read 5, iclass 32, count 0 2006.173.23:28:15.75#ibcon#about to read 6, iclass 32, count 0 2006.173.23:28:15.75#ibcon#read 6, iclass 32, count 0 2006.173.23:28:15.75#ibcon#end of sib2, iclass 32, count 0 2006.173.23:28:15.75#ibcon#*after write, iclass 32, count 0 2006.173.23:28:15.75#ibcon#*before return 0, iclass 32, count 0 2006.173.23:28:15.75#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.23:28:15.75#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.173.23:28:15.75#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.23:28:15.75#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.23:28:15.75$vck44/vblo=6,719.99 2006.173.23:28:15.75#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.23:28:15.75#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.23:28:15.75#ibcon#ireg 17 cls_cnt 0 2006.173.23:28:15.75#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.23:28:15.75#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.23:28:15.75#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.23:28:15.75#ibcon#enter wrdev, iclass 34, count 0 2006.173.23:28:15.75#ibcon#first serial, iclass 34, count 0 2006.173.23:28:15.75#ibcon#enter sib2, iclass 34, count 0 2006.173.23:28:15.75#ibcon#flushed, iclass 34, count 0 2006.173.23:28:15.75#ibcon#about to write, iclass 34, count 0 2006.173.23:28:15.75#ibcon#wrote, iclass 34, count 0 2006.173.23:28:15.75#ibcon#about to read 3, iclass 34, count 0 2006.173.23:28:15.77#ibcon#read 3, iclass 34, count 0 2006.173.23:28:15.77#ibcon#about to read 4, iclass 34, count 0 2006.173.23:28:15.77#ibcon#read 4, iclass 34, count 0 2006.173.23:28:15.77#ibcon#about to read 5, iclass 34, count 0 2006.173.23:28:15.77#ibcon#read 5, iclass 34, count 0 2006.173.23:28:15.77#ibcon#about to read 6, iclass 34, count 0 2006.173.23:28:15.77#ibcon#read 6, iclass 34, count 0 2006.173.23:28:15.77#ibcon#end of sib2, iclass 34, count 0 2006.173.23:28:15.77#ibcon#*mode == 0, iclass 34, count 0 2006.173.23:28:15.77#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.23:28:15.77#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.23:28:15.77#ibcon#*before write, iclass 34, count 0 2006.173.23:28:15.77#ibcon#enter sib2, iclass 34, count 0 2006.173.23:28:15.77#ibcon#flushed, iclass 34, count 0 2006.173.23:28:15.77#ibcon#about to write, iclass 34, count 0 2006.173.23:28:15.77#ibcon#wrote, iclass 34, count 0 2006.173.23:28:15.77#ibcon#about to read 3, iclass 34, count 0 2006.173.23:28:15.81#ibcon#read 3, iclass 34, count 0 2006.173.23:28:15.81#ibcon#about to read 4, iclass 34, count 0 2006.173.23:28:15.81#ibcon#read 4, iclass 34, count 0 2006.173.23:28:15.81#ibcon#about to read 5, iclass 34, count 0 2006.173.23:28:15.81#ibcon#read 5, iclass 34, count 0 2006.173.23:28:15.81#ibcon#about to read 6, iclass 34, count 0 2006.173.23:28:15.81#ibcon#read 6, iclass 34, count 0 2006.173.23:28:15.81#ibcon#end of sib2, iclass 34, count 0 2006.173.23:28:15.81#ibcon#*after write, iclass 34, count 0 2006.173.23:28:15.81#ibcon#*before return 0, iclass 34, count 0 2006.173.23:28:15.81#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.23:28:15.81#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.23:28:15.81#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.23:28:15.81#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.23:28:15.81$vck44/vb=6,4 2006.173.23:28:15.81#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.23:28:15.81#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.23:28:15.81#ibcon#ireg 11 cls_cnt 2 2006.173.23:28:15.81#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.23:28:15.87#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.23:28:15.87#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.23:28:15.87#ibcon#enter wrdev, iclass 36, count 2 2006.173.23:28:15.87#ibcon#first serial, iclass 36, count 2 2006.173.23:28:15.87#ibcon#enter sib2, iclass 36, count 2 2006.173.23:28:15.87#ibcon#flushed, iclass 36, count 2 2006.173.23:28:15.87#ibcon#about to write, iclass 36, count 2 2006.173.23:28:15.87#ibcon#wrote, iclass 36, count 2 2006.173.23:28:15.87#ibcon#about to read 3, iclass 36, count 2 2006.173.23:28:15.89#ibcon#read 3, iclass 36, count 2 2006.173.23:28:15.89#ibcon#about to read 4, iclass 36, count 2 2006.173.23:28:15.89#ibcon#read 4, iclass 36, count 2 2006.173.23:28:15.89#ibcon#about to read 5, iclass 36, count 2 2006.173.23:28:15.89#ibcon#read 5, iclass 36, count 2 2006.173.23:28:15.89#ibcon#about to read 6, iclass 36, count 2 2006.173.23:28:15.89#ibcon#read 6, iclass 36, count 2 2006.173.23:28:15.89#ibcon#end of sib2, iclass 36, count 2 2006.173.23:28:15.89#ibcon#*mode == 0, iclass 36, count 2 2006.173.23:28:15.89#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.23:28:15.89#ibcon#[27=AT06-04\r\n] 2006.173.23:28:15.89#ibcon#*before write, iclass 36, count 2 2006.173.23:28:15.89#ibcon#enter sib2, iclass 36, count 2 2006.173.23:28:15.89#ibcon#flushed, iclass 36, count 2 2006.173.23:28:15.89#ibcon#about to write, iclass 36, count 2 2006.173.23:28:15.89#ibcon#wrote, iclass 36, count 2 2006.173.23:28:15.89#ibcon#about to read 3, iclass 36, count 2 2006.173.23:28:15.92#ibcon#read 3, iclass 36, count 2 2006.173.23:28:15.92#ibcon#about to read 4, iclass 36, count 2 2006.173.23:28:15.92#ibcon#read 4, iclass 36, count 2 2006.173.23:28:15.92#ibcon#about to read 5, iclass 36, count 2 2006.173.23:28:15.92#ibcon#read 5, iclass 36, count 2 2006.173.23:28:15.92#ibcon#about to read 6, iclass 36, count 2 2006.173.23:28:15.92#ibcon#read 6, iclass 36, count 2 2006.173.23:28:15.92#ibcon#end of sib2, iclass 36, count 2 2006.173.23:28:15.92#ibcon#*after write, iclass 36, count 2 2006.173.23:28:15.92#ibcon#*before return 0, iclass 36, count 2 2006.173.23:28:15.92#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.23:28:15.92#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.23:28:15.92#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.23:28:15.92#ibcon#ireg 7 cls_cnt 0 2006.173.23:28:15.92#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.23:28:16.04#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.23:28:16.04#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.23:28:16.04#ibcon#enter wrdev, iclass 36, count 0 2006.173.23:28:16.04#ibcon#first serial, iclass 36, count 0 2006.173.23:28:16.04#ibcon#enter sib2, iclass 36, count 0 2006.173.23:28:16.04#ibcon#flushed, iclass 36, count 0 2006.173.23:28:16.04#ibcon#about to write, iclass 36, count 0 2006.173.23:28:16.04#ibcon#wrote, iclass 36, count 0 2006.173.23:28:16.04#ibcon#about to read 3, iclass 36, count 0 2006.173.23:28:16.06#ibcon#read 3, iclass 36, count 0 2006.173.23:28:16.06#ibcon#about to read 4, iclass 36, count 0 2006.173.23:28:16.06#ibcon#read 4, iclass 36, count 0 2006.173.23:28:16.06#ibcon#about to read 5, iclass 36, count 0 2006.173.23:28:16.06#ibcon#read 5, iclass 36, count 0 2006.173.23:28:16.06#ibcon#about to read 6, iclass 36, count 0 2006.173.23:28:16.06#ibcon#read 6, iclass 36, count 0 2006.173.23:28:16.06#ibcon#end of sib2, iclass 36, count 0 2006.173.23:28:16.06#ibcon#*mode == 0, iclass 36, count 0 2006.173.23:28:16.06#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.23:28:16.06#ibcon#[27=USB\r\n] 2006.173.23:28:16.06#ibcon#*before write, iclass 36, count 0 2006.173.23:28:16.06#ibcon#enter sib2, iclass 36, count 0 2006.173.23:28:16.06#ibcon#flushed, iclass 36, count 0 2006.173.23:28:16.06#ibcon#about to write, iclass 36, count 0 2006.173.23:28:16.06#ibcon#wrote, iclass 36, count 0 2006.173.23:28:16.06#ibcon#about to read 3, iclass 36, count 0 2006.173.23:28:16.09#ibcon#read 3, iclass 36, count 0 2006.173.23:28:16.09#ibcon#about to read 4, iclass 36, count 0 2006.173.23:28:16.09#ibcon#read 4, iclass 36, count 0 2006.173.23:28:16.09#ibcon#about to read 5, iclass 36, count 0 2006.173.23:28:16.09#ibcon#read 5, iclass 36, count 0 2006.173.23:28:16.09#ibcon#about to read 6, iclass 36, count 0 2006.173.23:28:16.09#ibcon#read 6, iclass 36, count 0 2006.173.23:28:16.09#ibcon#end of sib2, iclass 36, count 0 2006.173.23:28:16.09#ibcon#*after write, iclass 36, count 0 2006.173.23:28:16.09#ibcon#*before return 0, iclass 36, count 0 2006.173.23:28:16.09#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.23:28:16.09#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.23:28:16.09#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.23:28:16.09#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.23:28:16.09$vck44/vblo=7,734.99 2006.173.23:28:16.09#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.23:28:16.09#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.23:28:16.09#ibcon#ireg 17 cls_cnt 0 2006.173.23:28:16.09#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.23:28:16.09#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.23:28:16.09#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.23:28:16.09#ibcon#enter wrdev, iclass 38, count 0 2006.173.23:28:16.09#ibcon#first serial, iclass 38, count 0 2006.173.23:28:16.09#ibcon#enter sib2, iclass 38, count 0 2006.173.23:28:16.09#ibcon#flushed, iclass 38, count 0 2006.173.23:28:16.09#ibcon#about to write, iclass 38, count 0 2006.173.23:28:16.09#ibcon#wrote, iclass 38, count 0 2006.173.23:28:16.09#ibcon#about to read 3, iclass 38, count 0 2006.173.23:28:16.11#ibcon#read 3, iclass 38, count 0 2006.173.23:28:16.11#ibcon#about to read 4, iclass 38, count 0 2006.173.23:28:16.11#ibcon#read 4, iclass 38, count 0 2006.173.23:28:16.11#ibcon#about to read 5, iclass 38, count 0 2006.173.23:28:16.11#ibcon#read 5, iclass 38, count 0 2006.173.23:28:16.11#ibcon#about to read 6, iclass 38, count 0 2006.173.23:28:16.11#ibcon#read 6, iclass 38, count 0 2006.173.23:28:16.11#ibcon#end of sib2, iclass 38, count 0 2006.173.23:28:16.11#ibcon#*mode == 0, iclass 38, count 0 2006.173.23:28:16.11#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.23:28:16.11#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.23:28:16.11#ibcon#*before write, iclass 38, count 0 2006.173.23:28:16.11#ibcon#enter sib2, iclass 38, count 0 2006.173.23:28:16.11#ibcon#flushed, iclass 38, count 0 2006.173.23:28:16.11#ibcon#about to write, iclass 38, count 0 2006.173.23:28:16.11#ibcon#wrote, iclass 38, count 0 2006.173.23:28:16.11#ibcon#about to read 3, iclass 38, count 0 2006.173.23:28:16.15#ibcon#read 3, iclass 38, count 0 2006.173.23:28:16.15#ibcon#about to read 4, iclass 38, count 0 2006.173.23:28:16.15#ibcon#read 4, iclass 38, count 0 2006.173.23:28:16.15#ibcon#about to read 5, iclass 38, count 0 2006.173.23:28:16.15#ibcon#read 5, iclass 38, count 0 2006.173.23:28:16.15#ibcon#about to read 6, iclass 38, count 0 2006.173.23:28:16.15#ibcon#read 6, iclass 38, count 0 2006.173.23:28:16.15#ibcon#end of sib2, iclass 38, count 0 2006.173.23:28:16.15#ibcon#*after write, iclass 38, count 0 2006.173.23:28:16.15#ibcon#*before return 0, iclass 38, count 0 2006.173.23:28:16.15#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.23:28:16.15#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.23:28:16.15#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.23:28:16.15#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.23:28:16.15$vck44/vb=7,4 2006.173.23:28:16.15#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.23:28:16.15#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.23:28:16.15#ibcon#ireg 11 cls_cnt 2 2006.173.23:28:16.15#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.23:28:16.21#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.23:28:16.21#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.23:28:16.21#ibcon#enter wrdev, iclass 40, count 2 2006.173.23:28:16.21#ibcon#first serial, iclass 40, count 2 2006.173.23:28:16.21#ibcon#enter sib2, iclass 40, count 2 2006.173.23:28:16.21#ibcon#flushed, iclass 40, count 2 2006.173.23:28:16.21#ibcon#about to write, iclass 40, count 2 2006.173.23:28:16.21#ibcon#wrote, iclass 40, count 2 2006.173.23:28:16.21#ibcon#about to read 3, iclass 40, count 2 2006.173.23:28:16.23#ibcon#read 3, iclass 40, count 2 2006.173.23:28:16.23#ibcon#about to read 4, iclass 40, count 2 2006.173.23:28:16.23#ibcon#read 4, iclass 40, count 2 2006.173.23:28:16.23#ibcon#about to read 5, iclass 40, count 2 2006.173.23:28:16.23#ibcon#read 5, iclass 40, count 2 2006.173.23:28:16.23#ibcon#about to read 6, iclass 40, count 2 2006.173.23:28:16.23#ibcon#read 6, iclass 40, count 2 2006.173.23:28:16.23#ibcon#end of sib2, iclass 40, count 2 2006.173.23:28:16.23#ibcon#*mode == 0, iclass 40, count 2 2006.173.23:28:16.23#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.23:28:16.23#ibcon#[27=AT07-04\r\n] 2006.173.23:28:16.23#ibcon#*before write, iclass 40, count 2 2006.173.23:28:16.23#ibcon#enter sib2, iclass 40, count 2 2006.173.23:28:16.23#ibcon#flushed, iclass 40, count 2 2006.173.23:28:16.23#ibcon#about to write, iclass 40, count 2 2006.173.23:28:16.23#ibcon#wrote, iclass 40, count 2 2006.173.23:28:16.23#ibcon#about to read 3, iclass 40, count 2 2006.173.23:28:16.26#ibcon#read 3, iclass 40, count 2 2006.173.23:28:16.26#ibcon#about to read 4, iclass 40, count 2 2006.173.23:28:16.26#ibcon#read 4, iclass 40, count 2 2006.173.23:28:16.26#ibcon#about to read 5, iclass 40, count 2 2006.173.23:28:16.26#ibcon#read 5, iclass 40, count 2 2006.173.23:28:16.26#ibcon#about to read 6, iclass 40, count 2 2006.173.23:28:16.26#ibcon#read 6, iclass 40, count 2 2006.173.23:28:16.26#ibcon#end of sib2, iclass 40, count 2 2006.173.23:28:16.26#ibcon#*after write, iclass 40, count 2 2006.173.23:28:16.26#ibcon#*before return 0, iclass 40, count 2 2006.173.23:28:16.26#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.23:28:16.26#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.23:28:16.26#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.23:28:16.26#ibcon#ireg 7 cls_cnt 0 2006.173.23:28:16.26#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.23:28:16.38#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.23:28:16.38#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.23:28:16.38#ibcon#enter wrdev, iclass 40, count 0 2006.173.23:28:16.38#ibcon#first serial, iclass 40, count 0 2006.173.23:28:16.38#ibcon#enter sib2, iclass 40, count 0 2006.173.23:28:16.38#ibcon#flushed, iclass 40, count 0 2006.173.23:28:16.38#ibcon#about to write, iclass 40, count 0 2006.173.23:28:16.38#ibcon#wrote, iclass 40, count 0 2006.173.23:28:16.38#ibcon#about to read 3, iclass 40, count 0 2006.173.23:28:16.40#ibcon#read 3, iclass 40, count 0 2006.173.23:28:16.40#ibcon#about to read 4, iclass 40, count 0 2006.173.23:28:16.40#ibcon#read 4, iclass 40, count 0 2006.173.23:28:16.40#ibcon#about to read 5, iclass 40, count 0 2006.173.23:28:16.40#ibcon#read 5, iclass 40, count 0 2006.173.23:28:16.40#ibcon#about to read 6, iclass 40, count 0 2006.173.23:28:16.40#ibcon#read 6, iclass 40, count 0 2006.173.23:28:16.40#ibcon#end of sib2, iclass 40, count 0 2006.173.23:28:16.40#ibcon#*mode == 0, iclass 40, count 0 2006.173.23:28:16.40#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.23:28:16.40#ibcon#[27=USB\r\n] 2006.173.23:28:16.40#ibcon#*before write, iclass 40, count 0 2006.173.23:28:16.40#ibcon#enter sib2, iclass 40, count 0 2006.173.23:28:16.40#ibcon#flushed, iclass 40, count 0 2006.173.23:28:16.40#ibcon#about to write, iclass 40, count 0 2006.173.23:28:16.40#ibcon#wrote, iclass 40, count 0 2006.173.23:28:16.40#ibcon#about to read 3, iclass 40, count 0 2006.173.23:28:16.43#ibcon#read 3, iclass 40, count 0 2006.173.23:28:16.43#ibcon#about to read 4, iclass 40, count 0 2006.173.23:28:16.43#ibcon#read 4, iclass 40, count 0 2006.173.23:28:16.43#ibcon#about to read 5, iclass 40, count 0 2006.173.23:28:16.43#ibcon#read 5, iclass 40, count 0 2006.173.23:28:16.43#ibcon#about to read 6, iclass 40, count 0 2006.173.23:28:16.43#ibcon#read 6, iclass 40, count 0 2006.173.23:28:16.43#ibcon#end of sib2, iclass 40, count 0 2006.173.23:28:16.43#ibcon#*after write, iclass 40, count 0 2006.173.23:28:16.43#ibcon#*before return 0, iclass 40, count 0 2006.173.23:28:16.43#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.23:28:16.43#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.23:28:16.43#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.23:28:16.43#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.23:28:16.43$vck44/vblo=8,744.99 2006.173.23:28:16.43#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.23:28:16.43#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.23:28:16.43#ibcon#ireg 17 cls_cnt 0 2006.173.23:28:16.43#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.23:28:16.43#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.23:28:16.43#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.23:28:16.43#ibcon#enter wrdev, iclass 4, count 0 2006.173.23:28:16.43#ibcon#first serial, iclass 4, count 0 2006.173.23:28:16.43#ibcon#enter sib2, iclass 4, count 0 2006.173.23:28:16.43#ibcon#flushed, iclass 4, count 0 2006.173.23:28:16.43#ibcon#about to write, iclass 4, count 0 2006.173.23:28:16.43#ibcon#wrote, iclass 4, count 0 2006.173.23:28:16.43#ibcon#about to read 3, iclass 4, count 0 2006.173.23:28:16.45#ibcon#read 3, iclass 4, count 0 2006.173.23:28:16.45#ibcon#about to read 4, iclass 4, count 0 2006.173.23:28:16.45#ibcon#read 4, iclass 4, count 0 2006.173.23:28:16.45#ibcon#about to read 5, iclass 4, count 0 2006.173.23:28:16.45#ibcon#read 5, iclass 4, count 0 2006.173.23:28:16.45#ibcon#about to read 6, iclass 4, count 0 2006.173.23:28:16.45#ibcon#read 6, iclass 4, count 0 2006.173.23:28:16.45#ibcon#end of sib2, iclass 4, count 0 2006.173.23:28:16.45#ibcon#*mode == 0, iclass 4, count 0 2006.173.23:28:16.45#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.23:28:16.45#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.23:28:16.45#ibcon#*before write, iclass 4, count 0 2006.173.23:28:16.45#ibcon#enter sib2, iclass 4, count 0 2006.173.23:28:16.45#ibcon#flushed, iclass 4, count 0 2006.173.23:28:16.45#ibcon#about to write, iclass 4, count 0 2006.173.23:28:16.45#ibcon#wrote, iclass 4, count 0 2006.173.23:28:16.45#ibcon#about to read 3, iclass 4, count 0 2006.173.23:28:16.49#ibcon#read 3, iclass 4, count 0 2006.173.23:28:16.49#ibcon#about to read 4, iclass 4, count 0 2006.173.23:28:16.49#ibcon#read 4, iclass 4, count 0 2006.173.23:28:16.49#ibcon#about to read 5, iclass 4, count 0 2006.173.23:28:16.49#ibcon#read 5, iclass 4, count 0 2006.173.23:28:16.49#ibcon#about to read 6, iclass 4, count 0 2006.173.23:28:16.49#ibcon#read 6, iclass 4, count 0 2006.173.23:28:16.49#ibcon#end of sib2, iclass 4, count 0 2006.173.23:28:16.49#ibcon#*after write, iclass 4, count 0 2006.173.23:28:16.49#ibcon#*before return 0, iclass 4, count 0 2006.173.23:28:16.49#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.23:28:16.49#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.23:28:16.49#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.23:28:16.49#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.23:28:16.49$vck44/vb=8,4 2006.173.23:28:16.49#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.23:28:16.49#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.23:28:16.49#ibcon#ireg 11 cls_cnt 2 2006.173.23:28:16.49#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.23:28:16.55#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.23:28:16.55#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.23:28:16.55#ibcon#enter wrdev, iclass 6, count 2 2006.173.23:28:16.55#ibcon#first serial, iclass 6, count 2 2006.173.23:28:16.55#ibcon#enter sib2, iclass 6, count 2 2006.173.23:28:16.55#ibcon#flushed, iclass 6, count 2 2006.173.23:28:16.55#ibcon#about to write, iclass 6, count 2 2006.173.23:28:16.55#ibcon#wrote, iclass 6, count 2 2006.173.23:28:16.55#ibcon#about to read 3, iclass 6, count 2 2006.173.23:28:16.57#ibcon#read 3, iclass 6, count 2 2006.173.23:28:16.57#ibcon#about to read 4, iclass 6, count 2 2006.173.23:28:16.57#ibcon#read 4, iclass 6, count 2 2006.173.23:28:16.57#ibcon#about to read 5, iclass 6, count 2 2006.173.23:28:16.57#ibcon#read 5, iclass 6, count 2 2006.173.23:28:16.57#ibcon#about to read 6, iclass 6, count 2 2006.173.23:28:16.57#ibcon#read 6, iclass 6, count 2 2006.173.23:28:16.57#ibcon#end of sib2, iclass 6, count 2 2006.173.23:28:16.57#ibcon#*mode == 0, iclass 6, count 2 2006.173.23:28:16.57#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.23:28:16.57#ibcon#[27=AT08-04\r\n] 2006.173.23:28:16.57#ibcon#*before write, iclass 6, count 2 2006.173.23:28:16.57#ibcon#enter sib2, iclass 6, count 2 2006.173.23:28:16.57#ibcon#flushed, iclass 6, count 2 2006.173.23:28:16.57#ibcon#about to write, iclass 6, count 2 2006.173.23:28:16.57#ibcon#wrote, iclass 6, count 2 2006.173.23:28:16.57#ibcon#about to read 3, iclass 6, count 2 2006.173.23:28:16.60#ibcon#read 3, iclass 6, count 2 2006.173.23:28:16.60#ibcon#about to read 4, iclass 6, count 2 2006.173.23:28:16.60#ibcon#read 4, iclass 6, count 2 2006.173.23:28:16.60#ibcon#about to read 5, iclass 6, count 2 2006.173.23:28:16.60#ibcon#read 5, iclass 6, count 2 2006.173.23:28:16.60#ibcon#about to read 6, iclass 6, count 2 2006.173.23:28:16.60#ibcon#read 6, iclass 6, count 2 2006.173.23:28:16.60#ibcon#end of sib2, iclass 6, count 2 2006.173.23:28:16.60#ibcon#*after write, iclass 6, count 2 2006.173.23:28:16.60#ibcon#*before return 0, iclass 6, count 2 2006.173.23:28:16.60#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.23:28:16.60#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.23:28:16.60#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.23:28:16.60#ibcon#ireg 7 cls_cnt 0 2006.173.23:28:16.60#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.23:28:16.72#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.23:28:16.72#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.23:28:16.72#ibcon#enter wrdev, iclass 6, count 0 2006.173.23:28:16.72#ibcon#first serial, iclass 6, count 0 2006.173.23:28:16.72#ibcon#enter sib2, iclass 6, count 0 2006.173.23:28:16.72#ibcon#flushed, iclass 6, count 0 2006.173.23:28:16.72#ibcon#about to write, iclass 6, count 0 2006.173.23:28:16.72#ibcon#wrote, iclass 6, count 0 2006.173.23:28:16.72#ibcon#about to read 3, iclass 6, count 0 2006.173.23:28:16.74#ibcon#read 3, iclass 6, count 0 2006.173.23:28:16.74#ibcon#about to read 4, iclass 6, count 0 2006.173.23:28:16.74#ibcon#read 4, iclass 6, count 0 2006.173.23:28:16.74#ibcon#about to read 5, iclass 6, count 0 2006.173.23:28:16.74#ibcon#read 5, iclass 6, count 0 2006.173.23:28:16.74#ibcon#about to read 6, iclass 6, count 0 2006.173.23:28:16.74#ibcon#read 6, iclass 6, count 0 2006.173.23:28:16.74#ibcon#end of sib2, iclass 6, count 0 2006.173.23:28:16.74#ibcon#*mode == 0, iclass 6, count 0 2006.173.23:28:16.74#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.23:28:16.74#ibcon#[27=USB\r\n] 2006.173.23:28:16.74#ibcon#*before write, iclass 6, count 0 2006.173.23:28:16.74#ibcon#enter sib2, iclass 6, count 0 2006.173.23:28:16.74#ibcon#flushed, iclass 6, count 0 2006.173.23:28:16.74#ibcon#about to write, iclass 6, count 0 2006.173.23:28:16.74#ibcon#wrote, iclass 6, count 0 2006.173.23:28:16.74#ibcon#about to read 3, iclass 6, count 0 2006.173.23:28:16.77#ibcon#read 3, iclass 6, count 0 2006.173.23:28:16.77#ibcon#about to read 4, iclass 6, count 0 2006.173.23:28:16.77#ibcon#read 4, iclass 6, count 0 2006.173.23:28:16.77#ibcon#about to read 5, iclass 6, count 0 2006.173.23:28:16.77#ibcon#read 5, iclass 6, count 0 2006.173.23:28:16.77#ibcon#about to read 6, iclass 6, count 0 2006.173.23:28:16.77#ibcon#read 6, iclass 6, count 0 2006.173.23:28:16.77#ibcon#end of sib2, iclass 6, count 0 2006.173.23:28:16.77#ibcon#*after write, iclass 6, count 0 2006.173.23:28:16.77#ibcon#*before return 0, iclass 6, count 0 2006.173.23:28:16.77#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.23:28:16.77#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.23:28:16.77#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.23:28:16.77#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.23:28:16.77$vck44/vabw=wide 2006.173.23:28:16.77#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.23:28:16.77#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.23:28:16.77#ibcon#ireg 8 cls_cnt 0 2006.173.23:28:16.77#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.23:28:16.77#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.23:28:16.77#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.23:28:16.77#ibcon#enter wrdev, iclass 10, count 0 2006.173.23:28:16.77#ibcon#first serial, iclass 10, count 0 2006.173.23:28:16.77#ibcon#enter sib2, iclass 10, count 0 2006.173.23:28:16.77#ibcon#flushed, iclass 10, count 0 2006.173.23:28:16.77#ibcon#about to write, iclass 10, count 0 2006.173.23:28:16.77#ibcon#wrote, iclass 10, count 0 2006.173.23:28:16.77#ibcon#about to read 3, iclass 10, count 0 2006.173.23:28:16.79#ibcon#read 3, iclass 10, count 0 2006.173.23:28:16.79#ibcon#about to read 4, iclass 10, count 0 2006.173.23:28:16.79#ibcon#read 4, iclass 10, count 0 2006.173.23:28:16.79#ibcon#about to read 5, iclass 10, count 0 2006.173.23:28:16.79#ibcon#read 5, iclass 10, count 0 2006.173.23:28:16.79#ibcon#about to read 6, iclass 10, count 0 2006.173.23:28:16.79#ibcon#read 6, iclass 10, count 0 2006.173.23:28:16.79#ibcon#end of sib2, iclass 10, count 0 2006.173.23:28:16.79#ibcon#*mode == 0, iclass 10, count 0 2006.173.23:28:16.79#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.23:28:16.79#ibcon#[25=BW32\r\n] 2006.173.23:28:16.79#ibcon#*before write, iclass 10, count 0 2006.173.23:28:16.79#ibcon#enter sib2, iclass 10, count 0 2006.173.23:28:16.79#ibcon#flushed, iclass 10, count 0 2006.173.23:28:16.79#ibcon#about to write, iclass 10, count 0 2006.173.23:28:16.79#ibcon#wrote, iclass 10, count 0 2006.173.23:28:16.79#ibcon#about to read 3, iclass 10, count 0 2006.173.23:28:16.82#ibcon#read 3, iclass 10, count 0 2006.173.23:28:16.82#ibcon#about to read 4, iclass 10, count 0 2006.173.23:28:16.82#ibcon#read 4, iclass 10, count 0 2006.173.23:28:16.82#ibcon#about to read 5, iclass 10, count 0 2006.173.23:28:16.82#ibcon#read 5, iclass 10, count 0 2006.173.23:28:16.82#ibcon#about to read 6, iclass 10, count 0 2006.173.23:28:16.82#ibcon#read 6, iclass 10, count 0 2006.173.23:28:16.82#ibcon#end of sib2, iclass 10, count 0 2006.173.23:28:16.82#ibcon#*after write, iclass 10, count 0 2006.173.23:28:16.82#ibcon#*before return 0, iclass 10, count 0 2006.173.23:28:16.82#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.23:28:16.82#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.23:28:16.82#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.23:28:16.82#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.23:28:16.82$vck44/vbbw=wide 2006.173.23:28:16.82#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.23:28:16.82#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.23:28:16.82#ibcon#ireg 8 cls_cnt 0 2006.173.23:28:16.82#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.23:28:16.89#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.23:28:16.89#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.23:28:16.89#ibcon#enter wrdev, iclass 12, count 0 2006.173.23:28:16.89#ibcon#first serial, iclass 12, count 0 2006.173.23:28:16.89#ibcon#enter sib2, iclass 12, count 0 2006.173.23:28:16.89#ibcon#flushed, iclass 12, count 0 2006.173.23:28:16.89#ibcon#about to write, iclass 12, count 0 2006.173.23:28:16.89#ibcon#wrote, iclass 12, count 0 2006.173.23:28:16.89#ibcon#about to read 3, iclass 12, count 0 2006.173.23:28:16.91#ibcon#read 3, iclass 12, count 0 2006.173.23:28:16.91#ibcon#about to read 4, iclass 12, count 0 2006.173.23:28:16.91#ibcon#read 4, iclass 12, count 0 2006.173.23:28:16.91#ibcon#about to read 5, iclass 12, count 0 2006.173.23:28:16.91#ibcon#read 5, iclass 12, count 0 2006.173.23:28:16.91#ibcon#about to read 6, iclass 12, count 0 2006.173.23:28:16.91#ibcon#read 6, iclass 12, count 0 2006.173.23:28:16.91#ibcon#end of sib2, iclass 12, count 0 2006.173.23:28:16.91#ibcon#*mode == 0, iclass 12, count 0 2006.173.23:28:16.91#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.23:28:16.91#ibcon#[27=BW32\r\n] 2006.173.23:28:16.91#ibcon#*before write, iclass 12, count 0 2006.173.23:28:16.91#ibcon#enter sib2, iclass 12, count 0 2006.173.23:28:16.91#ibcon#flushed, iclass 12, count 0 2006.173.23:28:16.91#ibcon#about to write, iclass 12, count 0 2006.173.23:28:16.91#ibcon#wrote, iclass 12, count 0 2006.173.23:28:16.91#ibcon#about to read 3, iclass 12, count 0 2006.173.23:28:16.94#ibcon#read 3, iclass 12, count 0 2006.173.23:28:16.94#ibcon#about to read 4, iclass 12, count 0 2006.173.23:28:16.94#ibcon#read 4, iclass 12, count 0 2006.173.23:28:16.94#ibcon#about to read 5, iclass 12, count 0 2006.173.23:28:16.94#ibcon#read 5, iclass 12, count 0 2006.173.23:28:16.94#ibcon#about to read 6, iclass 12, count 0 2006.173.23:28:16.94#ibcon#read 6, iclass 12, count 0 2006.173.23:28:16.94#ibcon#end of sib2, iclass 12, count 0 2006.173.23:28:16.94#ibcon#*after write, iclass 12, count 0 2006.173.23:28:16.94#ibcon#*before return 0, iclass 12, count 0 2006.173.23:28:16.94#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.23:28:16.94#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.23:28:16.94#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.23:28:16.94#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.23:28:16.94$setupk4/ifdk4 2006.173.23:28:16.94$ifdk4/lo= 2006.173.23:28:16.94$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.23:28:16.94$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.23:28:16.94$ifdk4/patch= 2006.173.23:28:16.94$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.23:28:16.94$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.23:28:16.94$setupk4/!*+20s 2006.173.23:28:19.81#abcon#<5=/12 0.8 2.0 23.28 871003.3\r\n> 2006.173.23:28:19.83#abcon#{5=INTERFACE CLEAR} 2006.173.23:28:19.89#abcon#[5=S1D000X0/0*\r\n] 2006.173.23:28:29.98#abcon#<5=/12 0.8 2.0 23.28 881003.3\r\n> 2006.173.23:28:30.00#abcon#{5=INTERFACE CLEAR} 2006.173.23:28:30.06#abcon#[5=S1D000X0/0*\r\n] 2006.173.23:28:31.45$setupk4/"tpicd 2006.173.23:28:31.45$setupk4/echo=off 2006.173.23:28:31.45$setupk4/xlog=off 2006.173.23:28:31.45:!2006.173.23:31:59 2006.173.23:28:36.14#trakl#Source acquired 2006.173.23:28:36.14#flagr#flagr/antenna,acquired 2006.173.23:31:59.00:preob 2006.173.23:31:59.14/onsource/TRACKING 2006.173.23:31:59.14:!2006.173.23:32:09 2006.173.23:32:09.00:"tape 2006.173.23:32:09.00:"st=record 2006.173.23:32:09.00:data_valid=on 2006.173.23:32:09.00:midob 2006.173.23:32:09.14/onsource/TRACKING 2006.173.23:32:09.14/wx/23.45,1003.2,89 2006.173.23:32:09.26/cable/+6.5114E-03 2006.173.23:32:10.35/va/01,07,usb,yes,42,45 2006.173.23:32:10.35/va/02,06,usb,yes,42,43 2006.173.23:32:10.35/va/03,05,usb,yes,53,55 2006.173.23:32:10.35/va/04,06,usb,yes,43,45 2006.173.23:32:10.35/va/05,04,usb,yes,34,35 2006.173.23:32:10.35/va/06,03,usb,yes,47,47 2006.173.23:32:10.35/va/07,04,usb,yes,38,40 2006.173.23:32:10.35/va/08,04,usb,yes,33,39 2006.173.23:32:10.58/valo/01,524.99,yes,locked 2006.173.23:32:10.58/valo/02,534.99,yes,locked 2006.173.23:32:10.58/valo/03,564.99,yes,locked 2006.173.23:32:10.58/valo/04,624.99,yes,locked 2006.173.23:32:10.58/valo/05,734.99,yes,locked 2006.173.23:32:10.58/valo/06,814.99,yes,locked 2006.173.23:32:10.58/valo/07,864.99,yes,locked 2006.173.23:32:10.58/valo/08,884.99,yes,locked 2006.173.23:32:11.67/vb/01,04,usb,yes,31,34 2006.173.23:32:11.67/vb/02,04,usb,yes,34,43 2006.173.23:32:11.67/vb/03,04,usb,yes,30,34 2006.173.23:32:11.67/vb/04,04,usb,yes,35,34 2006.173.23:32:11.67/vb/05,04,usb,yes,27,30 2006.173.23:32:11.67/vb/06,04,usb,yes,32,28 2006.173.23:32:11.67/vb/07,04,usb,yes,32,32 2006.173.23:32:11.67/vb/08,04,usb,yes,29,33 2006.173.23:32:11.90/vblo/01,629.99,yes,locked 2006.173.23:32:11.90/vblo/02,634.99,yes,locked 2006.173.23:32:11.90/vblo/03,649.99,yes,locked 2006.173.23:32:11.90/vblo/04,679.99,yes,locked 2006.173.23:32:11.90/vblo/05,709.99,yes,locked 2006.173.23:32:11.90/vblo/06,719.99,yes,locked 2006.173.23:32:11.90/vblo/07,734.99,yes,locked 2006.173.23:32:11.90/vblo/08,744.99,yes,locked 2006.173.23:32:12.05/vabw/8 2006.173.23:32:12.20/vbbw/8 2006.173.23:32:12.29/xfe/off,on,15.0 2006.173.23:32:12.68/ifatt/23,28,28,28 2006.173.23:32:13.07/fmout-gps/S +3.95E-07 2006.173.23:32:13.11:!2006.173.23:32:49 2006.173.23:32:49.00:data_valid=off 2006.173.23:32:49.00:"et 2006.173.23:32:49.00:!+3s 2006.173.23:32:52.01:"tape 2006.173.23:32:52.01:postob 2006.173.23:32:52.21/cable/+6.5098E-03 2006.173.23:32:52.21/wx/23.46,1003.2,87 2006.173.23:32:53.08/fmout-gps/S +3.94E-07 2006.173.23:32:53.08:scan_name=173-2333,jd0606,140 2006.173.23:32:53.08:source=2201+315,220314.98,314538.3,2000.0,ccw 2006.173.23:32:54.13#flagr#flagr/antenna,new-source 2006.173.23:32:54.13:checkk5 2006.173.23:32:54.49/chk_autoobs//k5ts1/ autoobs is running! 2006.173.23:32:54.89/chk_autoobs//k5ts2/ autoobs is running! 2006.173.23:32:55.31/chk_autoobs//k5ts3/ autoobs is running! 2006.173.23:32:55.69/chk_autoobs//k5ts4/ autoobs is running! 2006.173.23:32:56.07/chk_obsdata//k5ts1/T1732332??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.23:32:56.48/chk_obsdata//k5ts2/T1732332??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.23:32:56.88/chk_obsdata//k5ts3/T1732332??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.23:32:57.32/chk_obsdata//k5ts4/T1732332??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.173.23:32:58.04/k5log//k5ts1_log_newline 2006.173.23:32:58.74/k5log//k5ts2_log_newline 2006.173.23:32:59.43/k5log//k5ts3_log_newline 2006.173.23:33:00.14/k5log//k5ts4_log_newline 2006.173.23:33:00.16/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.23:33:00.16:setupk4=1 2006.173.23:33:00.16$setupk4/echo=on 2006.173.23:33:00.16$setupk4/pcalon 2006.173.23:33:00.16$pcalon/"no phase cal control is implemented here 2006.173.23:33:00.16$setupk4/"tpicd=stop 2006.173.23:33:00.16$setupk4/"rec=synch_on 2006.173.23:33:00.16$setupk4/"rec_mode=128 2006.173.23:33:00.16$setupk4/!* 2006.173.23:33:00.16$setupk4/recpk4 2006.173.23:33:00.16$recpk4/recpatch= 2006.173.23:33:00.17$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.23:33:00.17$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.23:33:00.17$setupk4/vck44 2006.173.23:33:00.17$vck44/valo=1,524.99 2006.173.23:33:00.17#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.23:33:00.17#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.23:33:00.17#ibcon#ireg 17 cls_cnt 0 2006.173.23:33:00.17#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.23:33:00.17#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.23:33:00.17#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.23:33:00.17#ibcon#enter wrdev, iclass 21, count 0 2006.173.23:33:00.17#ibcon#first serial, iclass 21, count 0 2006.173.23:33:00.17#ibcon#enter sib2, iclass 21, count 0 2006.173.23:33:00.17#ibcon#flushed, iclass 21, count 0 2006.173.23:33:00.17#ibcon#about to write, iclass 21, count 0 2006.173.23:33:00.17#ibcon#wrote, iclass 21, count 0 2006.173.23:33:00.17#ibcon#about to read 3, iclass 21, count 0 2006.173.23:33:00.19#ibcon#read 3, iclass 21, count 0 2006.173.23:33:00.19#ibcon#about to read 4, iclass 21, count 0 2006.173.23:33:00.19#ibcon#read 4, iclass 21, count 0 2006.173.23:33:00.19#ibcon#about to read 5, iclass 21, count 0 2006.173.23:33:00.19#ibcon#read 5, iclass 21, count 0 2006.173.23:33:00.19#ibcon#about to read 6, iclass 21, count 0 2006.173.23:33:00.19#ibcon#read 6, iclass 21, count 0 2006.173.23:33:00.19#ibcon#end of sib2, iclass 21, count 0 2006.173.23:33:00.19#ibcon#*mode == 0, iclass 21, count 0 2006.173.23:33:00.19#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.23:33:00.19#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.23:33:00.19#ibcon#*before write, iclass 21, count 0 2006.173.23:33:00.19#ibcon#enter sib2, iclass 21, count 0 2006.173.23:33:00.19#ibcon#flushed, iclass 21, count 0 2006.173.23:33:00.19#ibcon#about to write, iclass 21, count 0 2006.173.23:33:00.19#ibcon#wrote, iclass 21, count 0 2006.173.23:33:00.19#ibcon#about to read 3, iclass 21, count 0 2006.173.23:33:00.24#ibcon#read 3, iclass 21, count 0 2006.173.23:33:00.24#ibcon#about to read 4, iclass 21, count 0 2006.173.23:33:00.24#ibcon#read 4, iclass 21, count 0 2006.173.23:33:00.24#ibcon#about to read 5, iclass 21, count 0 2006.173.23:33:00.24#ibcon#read 5, iclass 21, count 0 2006.173.23:33:00.24#ibcon#about to read 6, iclass 21, count 0 2006.173.23:33:00.24#ibcon#read 6, iclass 21, count 0 2006.173.23:33:00.24#ibcon#end of sib2, iclass 21, count 0 2006.173.23:33:00.24#ibcon#*after write, iclass 21, count 0 2006.173.23:33:00.24#ibcon#*before return 0, iclass 21, count 0 2006.173.23:33:00.24#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.23:33:00.24#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.23:33:00.24#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.23:33:00.24#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.23:33:00.24$vck44/va=1,7 2006.173.23:33:00.24#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.23:33:00.24#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.23:33:00.24#ibcon#ireg 11 cls_cnt 2 2006.173.23:33:00.24#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.23:33:00.24#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.23:33:00.24#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.23:33:00.24#ibcon#enter wrdev, iclass 23, count 2 2006.173.23:33:00.24#ibcon#first serial, iclass 23, count 2 2006.173.23:33:00.24#ibcon#enter sib2, iclass 23, count 2 2006.173.23:33:00.24#ibcon#flushed, iclass 23, count 2 2006.173.23:33:00.24#ibcon#about to write, iclass 23, count 2 2006.173.23:33:00.24#ibcon#wrote, iclass 23, count 2 2006.173.23:33:00.24#ibcon#about to read 3, iclass 23, count 2 2006.173.23:33:00.26#ibcon#read 3, iclass 23, count 2 2006.173.23:33:00.26#ibcon#about to read 4, iclass 23, count 2 2006.173.23:33:00.26#ibcon#read 4, iclass 23, count 2 2006.173.23:33:00.26#ibcon#about to read 5, iclass 23, count 2 2006.173.23:33:00.26#ibcon#read 5, iclass 23, count 2 2006.173.23:33:00.26#ibcon#about to read 6, iclass 23, count 2 2006.173.23:33:00.26#ibcon#read 6, iclass 23, count 2 2006.173.23:33:00.26#ibcon#end of sib2, iclass 23, count 2 2006.173.23:33:00.26#ibcon#*mode == 0, iclass 23, count 2 2006.173.23:33:00.26#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.23:33:00.26#ibcon#[25=AT01-07\r\n] 2006.173.23:33:00.26#ibcon#*before write, iclass 23, count 2 2006.173.23:33:00.26#ibcon#enter sib2, iclass 23, count 2 2006.173.23:33:00.26#ibcon#flushed, iclass 23, count 2 2006.173.23:33:00.26#ibcon#about to write, iclass 23, count 2 2006.173.23:33:00.26#ibcon#wrote, iclass 23, count 2 2006.173.23:33:00.26#ibcon#about to read 3, iclass 23, count 2 2006.173.23:33:00.29#ibcon#read 3, iclass 23, count 2 2006.173.23:33:00.29#ibcon#about to read 4, iclass 23, count 2 2006.173.23:33:00.29#ibcon#read 4, iclass 23, count 2 2006.173.23:33:00.29#ibcon#about to read 5, iclass 23, count 2 2006.173.23:33:00.29#ibcon#read 5, iclass 23, count 2 2006.173.23:33:00.29#ibcon#about to read 6, iclass 23, count 2 2006.173.23:33:00.29#ibcon#read 6, iclass 23, count 2 2006.173.23:33:00.29#ibcon#end of sib2, iclass 23, count 2 2006.173.23:33:00.29#ibcon#*after write, iclass 23, count 2 2006.173.23:33:00.29#ibcon#*before return 0, iclass 23, count 2 2006.173.23:33:00.29#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.23:33:00.29#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.23:33:00.29#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.23:33:00.29#ibcon#ireg 7 cls_cnt 0 2006.173.23:33:00.29#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.23:33:00.41#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.23:33:00.41#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.23:33:00.41#ibcon#enter wrdev, iclass 23, count 0 2006.173.23:33:00.41#ibcon#first serial, iclass 23, count 0 2006.173.23:33:00.41#ibcon#enter sib2, iclass 23, count 0 2006.173.23:33:00.41#ibcon#flushed, iclass 23, count 0 2006.173.23:33:00.41#ibcon#about to write, iclass 23, count 0 2006.173.23:33:00.41#ibcon#wrote, iclass 23, count 0 2006.173.23:33:00.41#ibcon#about to read 3, iclass 23, count 0 2006.173.23:33:00.43#ibcon#read 3, iclass 23, count 0 2006.173.23:33:00.43#ibcon#about to read 4, iclass 23, count 0 2006.173.23:33:00.43#ibcon#read 4, iclass 23, count 0 2006.173.23:33:00.43#ibcon#about to read 5, iclass 23, count 0 2006.173.23:33:00.43#ibcon#read 5, iclass 23, count 0 2006.173.23:33:00.43#ibcon#about to read 6, iclass 23, count 0 2006.173.23:33:00.43#ibcon#read 6, iclass 23, count 0 2006.173.23:33:00.43#ibcon#end of sib2, iclass 23, count 0 2006.173.23:33:00.43#ibcon#*mode == 0, iclass 23, count 0 2006.173.23:33:00.43#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.23:33:00.43#ibcon#[25=USB\r\n] 2006.173.23:33:00.43#ibcon#*before write, iclass 23, count 0 2006.173.23:33:00.43#ibcon#enter sib2, iclass 23, count 0 2006.173.23:33:00.43#ibcon#flushed, iclass 23, count 0 2006.173.23:33:00.43#ibcon#about to write, iclass 23, count 0 2006.173.23:33:00.43#ibcon#wrote, iclass 23, count 0 2006.173.23:33:00.43#ibcon#about to read 3, iclass 23, count 0 2006.173.23:33:00.46#ibcon#read 3, iclass 23, count 0 2006.173.23:33:00.46#ibcon#about to read 4, iclass 23, count 0 2006.173.23:33:00.46#ibcon#read 4, iclass 23, count 0 2006.173.23:33:00.46#ibcon#about to read 5, iclass 23, count 0 2006.173.23:33:00.46#ibcon#read 5, iclass 23, count 0 2006.173.23:33:00.46#ibcon#about to read 6, iclass 23, count 0 2006.173.23:33:00.46#ibcon#read 6, iclass 23, count 0 2006.173.23:33:00.46#ibcon#end of sib2, iclass 23, count 0 2006.173.23:33:00.46#ibcon#*after write, iclass 23, count 0 2006.173.23:33:00.46#ibcon#*before return 0, iclass 23, count 0 2006.173.23:33:00.46#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.23:33:00.46#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.23:33:00.46#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.23:33:00.46#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.23:33:00.46$vck44/valo=2,534.99 2006.173.23:33:00.46#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.23:33:00.46#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.23:33:00.46#ibcon#ireg 17 cls_cnt 0 2006.173.23:33:00.46#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.23:33:00.46#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.23:33:00.46#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.23:33:00.46#ibcon#enter wrdev, iclass 25, count 0 2006.173.23:33:00.46#ibcon#first serial, iclass 25, count 0 2006.173.23:33:00.46#ibcon#enter sib2, iclass 25, count 0 2006.173.23:33:00.46#ibcon#flushed, iclass 25, count 0 2006.173.23:33:00.46#ibcon#about to write, iclass 25, count 0 2006.173.23:33:00.46#ibcon#wrote, iclass 25, count 0 2006.173.23:33:00.46#ibcon#about to read 3, iclass 25, count 0 2006.173.23:33:00.48#ibcon#read 3, iclass 25, count 0 2006.173.23:33:00.48#ibcon#about to read 4, iclass 25, count 0 2006.173.23:33:00.48#ibcon#read 4, iclass 25, count 0 2006.173.23:33:00.48#ibcon#about to read 5, iclass 25, count 0 2006.173.23:33:00.48#ibcon#read 5, iclass 25, count 0 2006.173.23:33:00.48#ibcon#about to read 6, iclass 25, count 0 2006.173.23:33:00.48#ibcon#read 6, iclass 25, count 0 2006.173.23:33:00.48#ibcon#end of sib2, iclass 25, count 0 2006.173.23:33:00.48#ibcon#*mode == 0, iclass 25, count 0 2006.173.23:33:00.48#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.23:33:00.48#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.23:33:00.48#ibcon#*before write, iclass 25, count 0 2006.173.23:33:00.48#ibcon#enter sib2, iclass 25, count 0 2006.173.23:33:00.48#ibcon#flushed, iclass 25, count 0 2006.173.23:33:00.48#ibcon#about to write, iclass 25, count 0 2006.173.23:33:00.48#ibcon#wrote, iclass 25, count 0 2006.173.23:33:00.48#ibcon#about to read 3, iclass 25, count 0 2006.173.23:33:00.52#ibcon#read 3, iclass 25, count 0 2006.173.23:33:00.52#ibcon#about to read 4, iclass 25, count 0 2006.173.23:33:00.52#ibcon#read 4, iclass 25, count 0 2006.173.23:33:00.52#ibcon#about to read 5, iclass 25, count 0 2006.173.23:33:00.52#ibcon#read 5, iclass 25, count 0 2006.173.23:33:00.52#ibcon#about to read 6, iclass 25, count 0 2006.173.23:33:00.52#ibcon#read 6, iclass 25, count 0 2006.173.23:33:00.52#ibcon#end of sib2, iclass 25, count 0 2006.173.23:33:00.52#ibcon#*after write, iclass 25, count 0 2006.173.23:33:00.52#ibcon#*before return 0, iclass 25, count 0 2006.173.23:33:00.52#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.23:33:00.52#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.23:33:00.52#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.23:33:00.52#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.23:33:00.52$vck44/va=2,6 2006.173.23:33:00.52#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.23:33:00.52#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.23:33:00.52#ibcon#ireg 11 cls_cnt 2 2006.173.23:33:00.52#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.23:33:00.58#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.23:33:00.58#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.23:33:00.58#ibcon#enter wrdev, iclass 27, count 2 2006.173.23:33:00.58#ibcon#first serial, iclass 27, count 2 2006.173.23:33:00.58#ibcon#enter sib2, iclass 27, count 2 2006.173.23:33:00.58#ibcon#flushed, iclass 27, count 2 2006.173.23:33:00.58#ibcon#about to write, iclass 27, count 2 2006.173.23:33:00.58#ibcon#wrote, iclass 27, count 2 2006.173.23:33:00.58#ibcon#about to read 3, iclass 27, count 2 2006.173.23:33:00.60#ibcon#read 3, iclass 27, count 2 2006.173.23:33:00.60#ibcon#about to read 4, iclass 27, count 2 2006.173.23:33:00.60#ibcon#read 4, iclass 27, count 2 2006.173.23:33:00.60#ibcon#about to read 5, iclass 27, count 2 2006.173.23:33:00.60#ibcon#read 5, iclass 27, count 2 2006.173.23:33:00.60#ibcon#about to read 6, iclass 27, count 2 2006.173.23:33:00.60#ibcon#read 6, iclass 27, count 2 2006.173.23:33:00.60#ibcon#end of sib2, iclass 27, count 2 2006.173.23:33:00.60#ibcon#*mode == 0, iclass 27, count 2 2006.173.23:33:00.60#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.23:33:00.60#ibcon#[25=AT02-06\r\n] 2006.173.23:33:00.60#ibcon#*before write, iclass 27, count 2 2006.173.23:33:00.60#ibcon#enter sib2, iclass 27, count 2 2006.173.23:33:00.60#ibcon#flushed, iclass 27, count 2 2006.173.23:33:00.60#ibcon#about to write, iclass 27, count 2 2006.173.23:33:00.60#ibcon#wrote, iclass 27, count 2 2006.173.23:33:00.60#ibcon#about to read 3, iclass 27, count 2 2006.173.23:33:00.63#ibcon#read 3, iclass 27, count 2 2006.173.23:33:00.63#ibcon#about to read 4, iclass 27, count 2 2006.173.23:33:00.63#ibcon#read 4, iclass 27, count 2 2006.173.23:33:00.63#ibcon#about to read 5, iclass 27, count 2 2006.173.23:33:00.63#ibcon#read 5, iclass 27, count 2 2006.173.23:33:00.63#ibcon#about to read 6, iclass 27, count 2 2006.173.23:33:00.63#ibcon#read 6, iclass 27, count 2 2006.173.23:33:00.63#ibcon#end of sib2, iclass 27, count 2 2006.173.23:33:00.63#ibcon#*after write, iclass 27, count 2 2006.173.23:33:00.63#ibcon#*before return 0, iclass 27, count 2 2006.173.23:33:00.63#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.23:33:00.63#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.23:33:00.63#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.23:33:00.63#ibcon#ireg 7 cls_cnt 0 2006.173.23:33:00.63#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.23:33:00.75#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.23:33:00.75#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.23:33:00.75#ibcon#enter wrdev, iclass 27, count 0 2006.173.23:33:00.75#ibcon#first serial, iclass 27, count 0 2006.173.23:33:00.75#ibcon#enter sib2, iclass 27, count 0 2006.173.23:33:00.75#ibcon#flushed, iclass 27, count 0 2006.173.23:33:00.75#ibcon#about to write, iclass 27, count 0 2006.173.23:33:00.75#ibcon#wrote, iclass 27, count 0 2006.173.23:33:00.75#ibcon#about to read 3, iclass 27, count 0 2006.173.23:33:00.77#ibcon#read 3, iclass 27, count 0 2006.173.23:33:00.77#ibcon#about to read 4, iclass 27, count 0 2006.173.23:33:00.77#ibcon#read 4, iclass 27, count 0 2006.173.23:33:00.77#ibcon#about to read 5, iclass 27, count 0 2006.173.23:33:00.77#ibcon#read 5, iclass 27, count 0 2006.173.23:33:00.77#ibcon#about to read 6, iclass 27, count 0 2006.173.23:33:00.77#ibcon#read 6, iclass 27, count 0 2006.173.23:33:00.77#ibcon#end of sib2, iclass 27, count 0 2006.173.23:33:00.77#ibcon#*mode == 0, iclass 27, count 0 2006.173.23:33:00.77#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.23:33:00.77#ibcon#[25=USB\r\n] 2006.173.23:33:00.77#ibcon#*before write, iclass 27, count 0 2006.173.23:33:00.77#ibcon#enter sib2, iclass 27, count 0 2006.173.23:33:00.77#ibcon#flushed, iclass 27, count 0 2006.173.23:33:00.77#ibcon#about to write, iclass 27, count 0 2006.173.23:33:00.77#ibcon#wrote, iclass 27, count 0 2006.173.23:33:00.77#ibcon#about to read 3, iclass 27, count 0 2006.173.23:33:00.80#ibcon#read 3, iclass 27, count 0 2006.173.23:33:00.80#ibcon#about to read 4, iclass 27, count 0 2006.173.23:33:00.80#ibcon#read 4, iclass 27, count 0 2006.173.23:33:00.80#ibcon#about to read 5, iclass 27, count 0 2006.173.23:33:00.80#ibcon#read 5, iclass 27, count 0 2006.173.23:33:00.80#ibcon#about to read 6, iclass 27, count 0 2006.173.23:33:00.80#ibcon#read 6, iclass 27, count 0 2006.173.23:33:00.80#ibcon#end of sib2, iclass 27, count 0 2006.173.23:33:00.80#ibcon#*after write, iclass 27, count 0 2006.173.23:33:00.80#ibcon#*before return 0, iclass 27, count 0 2006.173.23:33:00.80#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.23:33:00.80#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.23:33:00.80#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.23:33:00.80#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.23:33:00.80$vck44/valo=3,564.99 2006.173.23:33:00.80#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.23:33:00.80#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.23:33:00.80#ibcon#ireg 17 cls_cnt 0 2006.173.23:33:00.80#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.23:33:00.80#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.23:33:00.80#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.23:33:00.80#ibcon#enter wrdev, iclass 29, count 0 2006.173.23:33:00.80#ibcon#first serial, iclass 29, count 0 2006.173.23:33:00.80#ibcon#enter sib2, iclass 29, count 0 2006.173.23:33:00.80#ibcon#flushed, iclass 29, count 0 2006.173.23:33:00.80#ibcon#about to write, iclass 29, count 0 2006.173.23:33:00.80#ibcon#wrote, iclass 29, count 0 2006.173.23:33:00.80#ibcon#about to read 3, iclass 29, count 0 2006.173.23:33:00.82#ibcon#read 3, iclass 29, count 0 2006.173.23:33:00.82#ibcon#about to read 4, iclass 29, count 0 2006.173.23:33:00.82#ibcon#read 4, iclass 29, count 0 2006.173.23:33:00.82#ibcon#about to read 5, iclass 29, count 0 2006.173.23:33:00.82#ibcon#read 5, iclass 29, count 0 2006.173.23:33:00.82#ibcon#about to read 6, iclass 29, count 0 2006.173.23:33:00.82#ibcon#read 6, iclass 29, count 0 2006.173.23:33:00.82#ibcon#end of sib2, iclass 29, count 0 2006.173.23:33:00.82#ibcon#*mode == 0, iclass 29, count 0 2006.173.23:33:00.82#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.23:33:00.82#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.23:33:00.82#ibcon#*before write, iclass 29, count 0 2006.173.23:33:00.82#ibcon#enter sib2, iclass 29, count 0 2006.173.23:33:00.82#ibcon#flushed, iclass 29, count 0 2006.173.23:33:00.82#ibcon#about to write, iclass 29, count 0 2006.173.23:33:00.82#ibcon#wrote, iclass 29, count 0 2006.173.23:33:00.82#ibcon#about to read 3, iclass 29, count 0 2006.173.23:33:00.86#ibcon#read 3, iclass 29, count 0 2006.173.23:33:00.86#ibcon#about to read 4, iclass 29, count 0 2006.173.23:33:00.86#ibcon#read 4, iclass 29, count 0 2006.173.23:33:00.86#ibcon#about to read 5, iclass 29, count 0 2006.173.23:33:00.86#ibcon#read 5, iclass 29, count 0 2006.173.23:33:00.86#ibcon#about to read 6, iclass 29, count 0 2006.173.23:33:00.86#ibcon#read 6, iclass 29, count 0 2006.173.23:33:00.86#ibcon#end of sib2, iclass 29, count 0 2006.173.23:33:00.86#ibcon#*after write, iclass 29, count 0 2006.173.23:33:00.86#ibcon#*before return 0, iclass 29, count 0 2006.173.23:33:00.86#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.23:33:00.86#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.23:33:00.86#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.23:33:00.86#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.23:33:00.86$vck44/va=3,5 2006.173.23:33:00.86#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.23:33:00.86#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.23:33:00.86#ibcon#ireg 11 cls_cnt 2 2006.173.23:33:00.86#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.23:33:00.92#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.23:33:00.92#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.23:33:00.92#ibcon#enter wrdev, iclass 31, count 2 2006.173.23:33:00.92#ibcon#first serial, iclass 31, count 2 2006.173.23:33:00.92#ibcon#enter sib2, iclass 31, count 2 2006.173.23:33:00.92#ibcon#flushed, iclass 31, count 2 2006.173.23:33:00.92#ibcon#about to write, iclass 31, count 2 2006.173.23:33:00.92#ibcon#wrote, iclass 31, count 2 2006.173.23:33:00.92#ibcon#about to read 3, iclass 31, count 2 2006.173.23:33:00.94#ibcon#read 3, iclass 31, count 2 2006.173.23:33:00.94#ibcon#about to read 4, iclass 31, count 2 2006.173.23:33:00.94#ibcon#read 4, iclass 31, count 2 2006.173.23:33:00.94#ibcon#about to read 5, iclass 31, count 2 2006.173.23:33:00.94#ibcon#read 5, iclass 31, count 2 2006.173.23:33:00.94#ibcon#about to read 6, iclass 31, count 2 2006.173.23:33:00.94#ibcon#read 6, iclass 31, count 2 2006.173.23:33:00.94#ibcon#end of sib2, iclass 31, count 2 2006.173.23:33:00.94#ibcon#*mode == 0, iclass 31, count 2 2006.173.23:33:00.94#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.23:33:00.94#ibcon#[25=AT03-05\r\n] 2006.173.23:33:00.94#ibcon#*before write, iclass 31, count 2 2006.173.23:33:00.94#ibcon#enter sib2, iclass 31, count 2 2006.173.23:33:00.94#ibcon#flushed, iclass 31, count 2 2006.173.23:33:00.94#ibcon#about to write, iclass 31, count 2 2006.173.23:33:00.94#ibcon#wrote, iclass 31, count 2 2006.173.23:33:00.94#ibcon#about to read 3, iclass 31, count 2 2006.173.23:33:00.97#ibcon#read 3, iclass 31, count 2 2006.173.23:33:00.97#ibcon#about to read 4, iclass 31, count 2 2006.173.23:33:00.97#ibcon#read 4, iclass 31, count 2 2006.173.23:33:00.97#ibcon#about to read 5, iclass 31, count 2 2006.173.23:33:00.97#ibcon#read 5, iclass 31, count 2 2006.173.23:33:00.97#ibcon#about to read 6, iclass 31, count 2 2006.173.23:33:00.97#ibcon#read 6, iclass 31, count 2 2006.173.23:33:00.97#ibcon#end of sib2, iclass 31, count 2 2006.173.23:33:00.97#ibcon#*after write, iclass 31, count 2 2006.173.23:33:00.97#ibcon#*before return 0, iclass 31, count 2 2006.173.23:33:00.97#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.23:33:00.97#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.23:33:00.97#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.23:33:00.97#ibcon#ireg 7 cls_cnt 0 2006.173.23:33:00.97#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.23:33:01.09#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.23:33:01.09#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.23:33:01.09#ibcon#enter wrdev, iclass 31, count 0 2006.173.23:33:01.09#ibcon#first serial, iclass 31, count 0 2006.173.23:33:01.09#ibcon#enter sib2, iclass 31, count 0 2006.173.23:33:01.09#ibcon#flushed, iclass 31, count 0 2006.173.23:33:01.09#ibcon#about to write, iclass 31, count 0 2006.173.23:33:01.09#ibcon#wrote, iclass 31, count 0 2006.173.23:33:01.09#ibcon#about to read 3, iclass 31, count 0 2006.173.23:33:01.11#ibcon#read 3, iclass 31, count 0 2006.173.23:33:01.11#ibcon#about to read 4, iclass 31, count 0 2006.173.23:33:01.11#ibcon#read 4, iclass 31, count 0 2006.173.23:33:01.11#ibcon#about to read 5, iclass 31, count 0 2006.173.23:33:01.11#ibcon#read 5, iclass 31, count 0 2006.173.23:33:01.11#ibcon#about to read 6, iclass 31, count 0 2006.173.23:33:01.11#ibcon#read 6, iclass 31, count 0 2006.173.23:33:01.11#ibcon#end of sib2, iclass 31, count 0 2006.173.23:33:01.11#ibcon#*mode == 0, iclass 31, count 0 2006.173.23:33:01.11#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.23:33:01.11#ibcon#[25=USB\r\n] 2006.173.23:33:01.11#ibcon#*before write, iclass 31, count 0 2006.173.23:33:01.11#ibcon#enter sib2, iclass 31, count 0 2006.173.23:33:01.11#ibcon#flushed, iclass 31, count 0 2006.173.23:33:01.11#ibcon#about to write, iclass 31, count 0 2006.173.23:33:01.11#ibcon#wrote, iclass 31, count 0 2006.173.23:33:01.11#ibcon#about to read 3, iclass 31, count 0 2006.173.23:33:01.14#ibcon#read 3, iclass 31, count 0 2006.173.23:33:01.14#ibcon#about to read 4, iclass 31, count 0 2006.173.23:33:01.14#ibcon#read 4, iclass 31, count 0 2006.173.23:33:01.14#ibcon#about to read 5, iclass 31, count 0 2006.173.23:33:01.14#ibcon#read 5, iclass 31, count 0 2006.173.23:33:01.14#ibcon#about to read 6, iclass 31, count 0 2006.173.23:33:01.14#ibcon#read 6, iclass 31, count 0 2006.173.23:33:01.14#ibcon#end of sib2, iclass 31, count 0 2006.173.23:33:01.14#ibcon#*after write, iclass 31, count 0 2006.173.23:33:01.14#ibcon#*before return 0, iclass 31, count 0 2006.173.23:33:01.14#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.23:33:01.14#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.23:33:01.14#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.23:33:01.14#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.23:33:01.14$vck44/valo=4,624.99 2006.173.23:33:01.14#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.23:33:01.14#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.23:33:01.14#ibcon#ireg 17 cls_cnt 0 2006.173.23:33:01.14#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.23:33:01.14#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.23:33:01.14#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.23:33:01.14#ibcon#enter wrdev, iclass 33, count 0 2006.173.23:33:01.14#ibcon#first serial, iclass 33, count 0 2006.173.23:33:01.14#ibcon#enter sib2, iclass 33, count 0 2006.173.23:33:01.14#ibcon#flushed, iclass 33, count 0 2006.173.23:33:01.14#ibcon#about to write, iclass 33, count 0 2006.173.23:33:01.14#ibcon#wrote, iclass 33, count 0 2006.173.23:33:01.14#ibcon#about to read 3, iclass 33, count 0 2006.173.23:33:01.16#ibcon#read 3, iclass 33, count 0 2006.173.23:33:01.16#ibcon#about to read 4, iclass 33, count 0 2006.173.23:33:01.16#ibcon#read 4, iclass 33, count 0 2006.173.23:33:01.16#ibcon#about to read 5, iclass 33, count 0 2006.173.23:33:01.16#ibcon#read 5, iclass 33, count 0 2006.173.23:33:01.16#ibcon#about to read 6, iclass 33, count 0 2006.173.23:33:01.16#ibcon#read 6, iclass 33, count 0 2006.173.23:33:01.16#ibcon#end of sib2, iclass 33, count 0 2006.173.23:33:01.16#ibcon#*mode == 0, iclass 33, count 0 2006.173.23:33:01.16#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.23:33:01.16#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.23:33:01.16#ibcon#*before write, iclass 33, count 0 2006.173.23:33:01.16#ibcon#enter sib2, iclass 33, count 0 2006.173.23:33:01.16#ibcon#flushed, iclass 33, count 0 2006.173.23:33:01.16#ibcon#about to write, iclass 33, count 0 2006.173.23:33:01.16#ibcon#wrote, iclass 33, count 0 2006.173.23:33:01.16#ibcon#about to read 3, iclass 33, count 0 2006.173.23:33:01.20#ibcon#read 3, iclass 33, count 0 2006.173.23:33:01.20#ibcon#about to read 4, iclass 33, count 0 2006.173.23:33:01.20#ibcon#read 4, iclass 33, count 0 2006.173.23:33:01.20#ibcon#about to read 5, iclass 33, count 0 2006.173.23:33:01.20#ibcon#read 5, iclass 33, count 0 2006.173.23:33:01.20#ibcon#about to read 6, iclass 33, count 0 2006.173.23:33:01.20#ibcon#read 6, iclass 33, count 0 2006.173.23:33:01.20#ibcon#end of sib2, iclass 33, count 0 2006.173.23:33:01.20#ibcon#*after write, iclass 33, count 0 2006.173.23:33:01.20#ibcon#*before return 0, iclass 33, count 0 2006.173.23:33:01.20#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.23:33:01.20#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.23:33:01.20#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.23:33:01.20#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.23:33:01.20$vck44/va=4,6 2006.173.23:33:01.20#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.23:33:01.20#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.23:33:01.20#ibcon#ireg 11 cls_cnt 2 2006.173.23:33:01.20#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.23:33:01.26#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.23:33:01.26#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.23:33:01.26#ibcon#enter wrdev, iclass 35, count 2 2006.173.23:33:01.26#ibcon#first serial, iclass 35, count 2 2006.173.23:33:01.26#ibcon#enter sib2, iclass 35, count 2 2006.173.23:33:01.26#ibcon#flushed, iclass 35, count 2 2006.173.23:33:01.26#ibcon#about to write, iclass 35, count 2 2006.173.23:33:01.26#ibcon#wrote, iclass 35, count 2 2006.173.23:33:01.26#ibcon#about to read 3, iclass 35, count 2 2006.173.23:33:01.28#ibcon#read 3, iclass 35, count 2 2006.173.23:33:01.28#ibcon#about to read 4, iclass 35, count 2 2006.173.23:33:01.28#ibcon#read 4, iclass 35, count 2 2006.173.23:33:01.28#ibcon#about to read 5, iclass 35, count 2 2006.173.23:33:01.28#ibcon#read 5, iclass 35, count 2 2006.173.23:33:01.28#ibcon#about to read 6, iclass 35, count 2 2006.173.23:33:01.28#ibcon#read 6, iclass 35, count 2 2006.173.23:33:01.28#ibcon#end of sib2, iclass 35, count 2 2006.173.23:33:01.28#ibcon#*mode == 0, iclass 35, count 2 2006.173.23:33:01.28#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.23:33:01.28#ibcon#[25=AT04-06\r\n] 2006.173.23:33:01.28#ibcon#*before write, iclass 35, count 2 2006.173.23:33:01.28#ibcon#enter sib2, iclass 35, count 2 2006.173.23:33:01.28#ibcon#flushed, iclass 35, count 2 2006.173.23:33:01.28#ibcon#about to write, iclass 35, count 2 2006.173.23:33:01.28#ibcon#wrote, iclass 35, count 2 2006.173.23:33:01.28#ibcon#about to read 3, iclass 35, count 2 2006.173.23:33:01.31#ibcon#read 3, iclass 35, count 2 2006.173.23:33:01.31#ibcon#about to read 4, iclass 35, count 2 2006.173.23:33:01.31#ibcon#read 4, iclass 35, count 2 2006.173.23:33:01.31#ibcon#about to read 5, iclass 35, count 2 2006.173.23:33:01.31#ibcon#read 5, iclass 35, count 2 2006.173.23:33:01.31#ibcon#about to read 6, iclass 35, count 2 2006.173.23:33:01.31#ibcon#read 6, iclass 35, count 2 2006.173.23:33:01.31#ibcon#end of sib2, iclass 35, count 2 2006.173.23:33:01.31#ibcon#*after write, iclass 35, count 2 2006.173.23:33:01.31#ibcon#*before return 0, iclass 35, count 2 2006.173.23:33:01.31#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.23:33:01.31#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.23:33:01.31#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.23:33:01.31#ibcon#ireg 7 cls_cnt 0 2006.173.23:33:01.31#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.23:33:01.43#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.23:33:01.43#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.23:33:01.43#ibcon#enter wrdev, iclass 35, count 0 2006.173.23:33:01.43#ibcon#first serial, iclass 35, count 0 2006.173.23:33:01.43#ibcon#enter sib2, iclass 35, count 0 2006.173.23:33:01.43#ibcon#flushed, iclass 35, count 0 2006.173.23:33:01.43#ibcon#about to write, iclass 35, count 0 2006.173.23:33:01.43#ibcon#wrote, iclass 35, count 0 2006.173.23:33:01.43#ibcon#about to read 3, iclass 35, count 0 2006.173.23:33:01.45#ibcon#read 3, iclass 35, count 0 2006.173.23:33:01.45#ibcon#about to read 4, iclass 35, count 0 2006.173.23:33:01.45#ibcon#read 4, iclass 35, count 0 2006.173.23:33:01.45#ibcon#about to read 5, iclass 35, count 0 2006.173.23:33:01.45#ibcon#read 5, iclass 35, count 0 2006.173.23:33:01.45#ibcon#about to read 6, iclass 35, count 0 2006.173.23:33:01.45#ibcon#read 6, iclass 35, count 0 2006.173.23:33:01.45#ibcon#end of sib2, iclass 35, count 0 2006.173.23:33:01.45#ibcon#*mode == 0, iclass 35, count 0 2006.173.23:33:01.45#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.23:33:01.45#ibcon#[25=USB\r\n] 2006.173.23:33:01.45#ibcon#*before write, iclass 35, count 0 2006.173.23:33:01.45#ibcon#enter sib2, iclass 35, count 0 2006.173.23:33:01.45#ibcon#flushed, iclass 35, count 0 2006.173.23:33:01.45#ibcon#about to write, iclass 35, count 0 2006.173.23:33:01.45#ibcon#wrote, iclass 35, count 0 2006.173.23:33:01.45#ibcon#about to read 3, iclass 35, count 0 2006.173.23:33:01.48#ibcon#read 3, iclass 35, count 0 2006.173.23:33:01.48#ibcon#about to read 4, iclass 35, count 0 2006.173.23:33:01.48#ibcon#read 4, iclass 35, count 0 2006.173.23:33:01.48#ibcon#about to read 5, iclass 35, count 0 2006.173.23:33:01.48#ibcon#read 5, iclass 35, count 0 2006.173.23:33:01.48#ibcon#about to read 6, iclass 35, count 0 2006.173.23:33:01.48#ibcon#read 6, iclass 35, count 0 2006.173.23:33:01.48#ibcon#end of sib2, iclass 35, count 0 2006.173.23:33:01.48#ibcon#*after write, iclass 35, count 0 2006.173.23:33:01.48#ibcon#*before return 0, iclass 35, count 0 2006.173.23:33:01.48#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.23:33:01.48#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.23:33:01.48#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.23:33:01.48#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.23:33:01.48$vck44/valo=5,734.99 2006.173.23:33:01.48#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.23:33:01.48#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.23:33:01.48#ibcon#ireg 17 cls_cnt 0 2006.173.23:33:01.48#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.23:33:01.48#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.23:33:01.48#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.23:33:01.48#ibcon#enter wrdev, iclass 37, count 0 2006.173.23:33:01.48#ibcon#first serial, iclass 37, count 0 2006.173.23:33:01.48#ibcon#enter sib2, iclass 37, count 0 2006.173.23:33:01.48#ibcon#flushed, iclass 37, count 0 2006.173.23:33:01.48#ibcon#about to write, iclass 37, count 0 2006.173.23:33:01.48#ibcon#wrote, iclass 37, count 0 2006.173.23:33:01.48#ibcon#about to read 3, iclass 37, count 0 2006.173.23:33:01.50#ibcon#read 3, iclass 37, count 0 2006.173.23:33:01.50#ibcon#about to read 4, iclass 37, count 0 2006.173.23:33:01.50#ibcon#read 4, iclass 37, count 0 2006.173.23:33:01.50#ibcon#about to read 5, iclass 37, count 0 2006.173.23:33:01.50#ibcon#read 5, iclass 37, count 0 2006.173.23:33:01.50#ibcon#about to read 6, iclass 37, count 0 2006.173.23:33:01.50#ibcon#read 6, iclass 37, count 0 2006.173.23:33:01.50#ibcon#end of sib2, iclass 37, count 0 2006.173.23:33:01.50#ibcon#*mode == 0, iclass 37, count 0 2006.173.23:33:01.50#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.23:33:01.50#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.23:33:01.50#ibcon#*before write, iclass 37, count 0 2006.173.23:33:01.50#ibcon#enter sib2, iclass 37, count 0 2006.173.23:33:01.50#ibcon#flushed, iclass 37, count 0 2006.173.23:33:01.50#ibcon#about to write, iclass 37, count 0 2006.173.23:33:01.50#ibcon#wrote, iclass 37, count 0 2006.173.23:33:01.50#ibcon#about to read 3, iclass 37, count 0 2006.173.23:33:01.54#ibcon#read 3, iclass 37, count 0 2006.173.23:33:01.54#ibcon#about to read 4, iclass 37, count 0 2006.173.23:33:01.54#ibcon#read 4, iclass 37, count 0 2006.173.23:33:01.54#ibcon#about to read 5, iclass 37, count 0 2006.173.23:33:01.54#ibcon#read 5, iclass 37, count 0 2006.173.23:33:01.54#ibcon#about to read 6, iclass 37, count 0 2006.173.23:33:01.54#ibcon#read 6, iclass 37, count 0 2006.173.23:33:01.54#ibcon#end of sib2, iclass 37, count 0 2006.173.23:33:01.54#ibcon#*after write, iclass 37, count 0 2006.173.23:33:01.54#ibcon#*before return 0, iclass 37, count 0 2006.173.23:33:01.54#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.23:33:01.54#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.23:33:01.54#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.23:33:01.54#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.23:33:01.54$vck44/va=5,4 2006.173.23:33:01.54#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.23:33:01.54#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.23:33:01.54#ibcon#ireg 11 cls_cnt 2 2006.173.23:33:01.54#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.23:33:01.60#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.23:33:01.60#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.23:33:01.60#ibcon#enter wrdev, iclass 39, count 2 2006.173.23:33:01.60#ibcon#first serial, iclass 39, count 2 2006.173.23:33:01.60#ibcon#enter sib2, iclass 39, count 2 2006.173.23:33:01.60#ibcon#flushed, iclass 39, count 2 2006.173.23:33:01.60#ibcon#about to write, iclass 39, count 2 2006.173.23:33:01.60#ibcon#wrote, iclass 39, count 2 2006.173.23:33:01.60#ibcon#about to read 3, iclass 39, count 2 2006.173.23:33:01.62#ibcon#read 3, iclass 39, count 2 2006.173.23:33:01.62#ibcon#about to read 4, iclass 39, count 2 2006.173.23:33:01.62#ibcon#read 4, iclass 39, count 2 2006.173.23:33:01.62#ibcon#about to read 5, iclass 39, count 2 2006.173.23:33:01.62#ibcon#read 5, iclass 39, count 2 2006.173.23:33:01.62#ibcon#about to read 6, iclass 39, count 2 2006.173.23:33:01.62#ibcon#read 6, iclass 39, count 2 2006.173.23:33:01.62#ibcon#end of sib2, iclass 39, count 2 2006.173.23:33:01.62#ibcon#*mode == 0, iclass 39, count 2 2006.173.23:33:01.62#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.23:33:01.62#ibcon#[25=AT05-04\r\n] 2006.173.23:33:01.62#ibcon#*before write, iclass 39, count 2 2006.173.23:33:01.62#ibcon#enter sib2, iclass 39, count 2 2006.173.23:33:01.62#ibcon#flushed, iclass 39, count 2 2006.173.23:33:01.62#ibcon#about to write, iclass 39, count 2 2006.173.23:33:01.62#ibcon#wrote, iclass 39, count 2 2006.173.23:33:01.62#ibcon#about to read 3, iclass 39, count 2 2006.173.23:33:01.65#ibcon#read 3, iclass 39, count 2 2006.173.23:33:01.65#ibcon#about to read 4, iclass 39, count 2 2006.173.23:33:01.65#ibcon#read 4, iclass 39, count 2 2006.173.23:33:01.65#ibcon#about to read 5, iclass 39, count 2 2006.173.23:33:01.65#ibcon#read 5, iclass 39, count 2 2006.173.23:33:01.65#ibcon#about to read 6, iclass 39, count 2 2006.173.23:33:01.65#ibcon#read 6, iclass 39, count 2 2006.173.23:33:01.65#ibcon#end of sib2, iclass 39, count 2 2006.173.23:33:01.65#ibcon#*after write, iclass 39, count 2 2006.173.23:33:01.65#ibcon#*before return 0, iclass 39, count 2 2006.173.23:33:01.65#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.23:33:01.65#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.23:33:01.65#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.23:33:01.65#ibcon#ireg 7 cls_cnt 0 2006.173.23:33:01.65#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.23:33:01.77#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.23:33:01.77#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.23:33:01.77#ibcon#enter wrdev, iclass 39, count 0 2006.173.23:33:01.77#ibcon#first serial, iclass 39, count 0 2006.173.23:33:01.77#ibcon#enter sib2, iclass 39, count 0 2006.173.23:33:01.77#ibcon#flushed, iclass 39, count 0 2006.173.23:33:01.77#ibcon#about to write, iclass 39, count 0 2006.173.23:33:01.77#ibcon#wrote, iclass 39, count 0 2006.173.23:33:01.77#ibcon#about to read 3, iclass 39, count 0 2006.173.23:33:01.79#ibcon#read 3, iclass 39, count 0 2006.173.23:33:01.79#ibcon#about to read 4, iclass 39, count 0 2006.173.23:33:01.79#ibcon#read 4, iclass 39, count 0 2006.173.23:33:01.79#ibcon#about to read 5, iclass 39, count 0 2006.173.23:33:01.79#ibcon#read 5, iclass 39, count 0 2006.173.23:33:01.79#ibcon#about to read 6, iclass 39, count 0 2006.173.23:33:01.79#ibcon#read 6, iclass 39, count 0 2006.173.23:33:01.79#ibcon#end of sib2, iclass 39, count 0 2006.173.23:33:01.79#ibcon#*mode == 0, iclass 39, count 0 2006.173.23:33:01.79#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.23:33:01.79#ibcon#[25=USB\r\n] 2006.173.23:33:01.79#ibcon#*before write, iclass 39, count 0 2006.173.23:33:01.79#ibcon#enter sib2, iclass 39, count 0 2006.173.23:33:01.79#ibcon#flushed, iclass 39, count 0 2006.173.23:33:01.79#ibcon#about to write, iclass 39, count 0 2006.173.23:33:01.79#ibcon#wrote, iclass 39, count 0 2006.173.23:33:01.79#ibcon#about to read 3, iclass 39, count 0 2006.173.23:33:01.82#ibcon#read 3, iclass 39, count 0 2006.173.23:33:01.82#ibcon#about to read 4, iclass 39, count 0 2006.173.23:33:01.82#ibcon#read 4, iclass 39, count 0 2006.173.23:33:01.82#ibcon#about to read 5, iclass 39, count 0 2006.173.23:33:01.82#ibcon#read 5, iclass 39, count 0 2006.173.23:33:01.82#ibcon#about to read 6, iclass 39, count 0 2006.173.23:33:01.82#ibcon#read 6, iclass 39, count 0 2006.173.23:33:01.82#ibcon#end of sib2, iclass 39, count 0 2006.173.23:33:01.82#ibcon#*after write, iclass 39, count 0 2006.173.23:33:01.82#ibcon#*before return 0, iclass 39, count 0 2006.173.23:33:01.82#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.23:33:01.82#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.23:33:01.82#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.23:33:01.82#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.23:33:01.82$vck44/valo=6,814.99 2006.173.23:33:01.82#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.23:33:01.82#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.23:33:01.82#ibcon#ireg 17 cls_cnt 0 2006.173.23:33:01.82#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.23:33:01.82#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.23:33:01.82#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.23:33:01.82#ibcon#enter wrdev, iclass 3, count 0 2006.173.23:33:01.82#ibcon#first serial, iclass 3, count 0 2006.173.23:33:01.82#ibcon#enter sib2, iclass 3, count 0 2006.173.23:33:01.82#ibcon#flushed, iclass 3, count 0 2006.173.23:33:01.82#ibcon#about to write, iclass 3, count 0 2006.173.23:33:01.82#ibcon#wrote, iclass 3, count 0 2006.173.23:33:01.82#ibcon#about to read 3, iclass 3, count 0 2006.173.23:33:01.84#ibcon#read 3, iclass 3, count 0 2006.173.23:33:01.84#ibcon#about to read 4, iclass 3, count 0 2006.173.23:33:01.84#ibcon#read 4, iclass 3, count 0 2006.173.23:33:01.84#ibcon#about to read 5, iclass 3, count 0 2006.173.23:33:01.84#ibcon#read 5, iclass 3, count 0 2006.173.23:33:01.84#ibcon#about to read 6, iclass 3, count 0 2006.173.23:33:01.84#ibcon#read 6, iclass 3, count 0 2006.173.23:33:01.84#ibcon#end of sib2, iclass 3, count 0 2006.173.23:33:01.84#ibcon#*mode == 0, iclass 3, count 0 2006.173.23:33:01.84#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.23:33:01.84#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.23:33:01.84#ibcon#*before write, iclass 3, count 0 2006.173.23:33:01.84#ibcon#enter sib2, iclass 3, count 0 2006.173.23:33:01.84#ibcon#flushed, iclass 3, count 0 2006.173.23:33:01.84#ibcon#about to write, iclass 3, count 0 2006.173.23:33:01.84#ibcon#wrote, iclass 3, count 0 2006.173.23:33:01.84#ibcon#about to read 3, iclass 3, count 0 2006.173.23:33:01.88#ibcon#read 3, iclass 3, count 0 2006.173.23:33:01.88#ibcon#about to read 4, iclass 3, count 0 2006.173.23:33:01.88#ibcon#read 4, iclass 3, count 0 2006.173.23:33:01.88#ibcon#about to read 5, iclass 3, count 0 2006.173.23:33:01.88#ibcon#read 5, iclass 3, count 0 2006.173.23:33:01.88#ibcon#about to read 6, iclass 3, count 0 2006.173.23:33:01.88#ibcon#read 6, iclass 3, count 0 2006.173.23:33:01.88#ibcon#end of sib2, iclass 3, count 0 2006.173.23:33:01.88#ibcon#*after write, iclass 3, count 0 2006.173.23:33:01.88#ibcon#*before return 0, iclass 3, count 0 2006.173.23:33:01.88#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.23:33:01.88#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.23:33:01.88#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.23:33:01.88#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.23:33:01.88$vck44/va=6,3 2006.173.23:33:01.88#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.23:33:01.88#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.23:33:01.88#ibcon#ireg 11 cls_cnt 2 2006.173.23:33:01.88#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.23:33:01.94#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.23:33:01.94#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.23:33:01.94#ibcon#enter wrdev, iclass 5, count 2 2006.173.23:33:01.94#ibcon#first serial, iclass 5, count 2 2006.173.23:33:01.94#ibcon#enter sib2, iclass 5, count 2 2006.173.23:33:01.94#ibcon#flushed, iclass 5, count 2 2006.173.23:33:01.94#ibcon#about to write, iclass 5, count 2 2006.173.23:33:01.94#ibcon#wrote, iclass 5, count 2 2006.173.23:33:01.94#ibcon#about to read 3, iclass 5, count 2 2006.173.23:33:01.96#ibcon#read 3, iclass 5, count 2 2006.173.23:33:01.96#ibcon#about to read 4, iclass 5, count 2 2006.173.23:33:01.96#ibcon#read 4, iclass 5, count 2 2006.173.23:33:01.96#ibcon#about to read 5, iclass 5, count 2 2006.173.23:33:01.96#ibcon#read 5, iclass 5, count 2 2006.173.23:33:01.96#ibcon#about to read 6, iclass 5, count 2 2006.173.23:33:01.96#ibcon#read 6, iclass 5, count 2 2006.173.23:33:01.96#ibcon#end of sib2, iclass 5, count 2 2006.173.23:33:01.96#ibcon#*mode == 0, iclass 5, count 2 2006.173.23:33:01.96#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.23:33:01.96#ibcon#[25=AT06-03\r\n] 2006.173.23:33:01.96#ibcon#*before write, iclass 5, count 2 2006.173.23:33:01.96#ibcon#enter sib2, iclass 5, count 2 2006.173.23:33:01.96#ibcon#flushed, iclass 5, count 2 2006.173.23:33:01.96#ibcon#about to write, iclass 5, count 2 2006.173.23:33:01.96#ibcon#wrote, iclass 5, count 2 2006.173.23:33:01.96#ibcon#about to read 3, iclass 5, count 2 2006.173.23:33:01.99#ibcon#read 3, iclass 5, count 2 2006.173.23:33:01.99#ibcon#about to read 4, iclass 5, count 2 2006.173.23:33:01.99#ibcon#read 4, iclass 5, count 2 2006.173.23:33:01.99#ibcon#about to read 5, iclass 5, count 2 2006.173.23:33:01.99#ibcon#read 5, iclass 5, count 2 2006.173.23:33:01.99#ibcon#about to read 6, iclass 5, count 2 2006.173.23:33:01.99#ibcon#read 6, iclass 5, count 2 2006.173.23:33:01.99#ibcon#end of sib2, iclass 5, count 2 2006.173.23:33:01.99#ibcon#*after write, iclass 5, count 2 2006.173.23:33:01.99#ibcon#*before return 0, iclass 5, count 2 2006.173.23:33:01.99#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.23:33:01.99#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.23:33:01.99#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.23:33:01.99#ibcon#ireg 7 cls_cnt 0 2006.173.23:33:01.99#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.23:33:02.11#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.23:33:02.11#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.23:33:02.11#ibcon#enter wrdev, iclass 5, count 0 2006.173.23:33:02.11#ibcon#first serial, iclass 5, count 0 2006.173.23:33:02.11#ibcon#enter sib2, iclass 5, count 0 2006.173.23:33:02.11#ibcon#flushed, iclass 5, count 0 2006.173.23:33:02.11#ibcon#about to write, iclass 5, count 0 2006.173.23:33:02.11#ibcon#wrote, iclass 5, count 0 2006.173.23:33:02.11#ibcon#about to read 3, iclass 5, count 0 2006.173.23:33:02.13#ibcon#read 3, iclass 5, count 0 2006.173.23:33:02.13#ibcon#about to read 4, iclass 5, count 0 2006.173.23:33:02.13#ibcon#read 4, iclass 5, count 0 2006.173.23:33:02.13#ibcon#about to read 5, iclass 5, count 0 2006.173.23:33:02.13#ibcon#read 5, iclass 5, count 0 2006.173.23:33:02.13#ibcon#about to read 6, iclass 5, count 0 2006.173.23:33:02.13#ibcon#read 6, iclass 5, count 0 2006.173.23:33:02.13#ibcon#end of sib2, iclass 5, count 0 2006.173.23:33:02.13#ibcon#*mode == 0, iclass 5, count 0 2006.173.23:33:02.13#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.23:33:02.13#ibcon#[25=USB\r\n] 2006.173.23:33:02.13#ibcon#*before write, iclass 5, count 0 2006.173.23:33:02.13#ibcon#enter sib2, iclass 5, count 0 2006.173.23:33:02.13#ibcon#flushed, iclass 5, count 0 2006.173.23:33:02.13#ibcon#about to write, iclass 5, count 0 2006.173.23:33:02.13#ibcon#wrote, iclass 5, count 0 2006.173.23:33:02.13#ibcon#about to read 3, iclass 5, count 0 2006.173.23:33:02.16#ibcon#read 3, iclass 5, count 0 2006.173.23:33:02.16#ibcon#about to read 4, iclass 5, count 0 2006.173.23:33:02.16#ibcon#read 4, iclass 5, count 0 2006.173.23:33:02.16#ibcon#about to read 5, iclass 5, count 0 2006.173.23:33:02.16#ibcon#read 5, iclass 5, count 0 2006.173.23:33:02.16#ibcon#about to read 6, iclass 5, count 0 2006.173.23:33:02.16#ibcon#read 6, iclass 5, count 0 2006.173.23:33:02.16#ibcon#end of sib2, iclass 5, count 0 2006.173.23:33:02.16#ibcon#*after write, iclass 5, count 0 2006.173.23:33:02.16#ibcon#*before return 0, iclass 5, count 0 2006.173.23:33:02.16#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.23:33:02.16#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.23:33:02.16#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.23:33:02.16#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.23:33:02.16$vck44/valo=7,864.99 2006.173.23:33:02.16#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.23:33:02.16#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.23:33:02.16#ibcon#ireg 17 cls_cnt 0 2006.173.23:33:02.16#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.23:33:02.16#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.23:33:02.16#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.23:33:02.16#ibcon#enter wrdev, iclass 7, count 0 2006.173.23:33:02.16#ibcon#first serial, iclass 7, count 0 2006.173.23:33:02.16#ibcon#enter sib2, iclass 7, count 0 2006.173.23:33:02.16#ibcon#flushed, iclass 7, count 0 2006.173.23:33:02.16#ibcon#about to write, iclass 7, count 0 2006.173.23:33:02.16#ibcon#wrote, iclass 7, count 0 2006.173.23:33:02.16#ibcon#about to read 3, iclass 7, count 0 2006.173.23:33:02.18#ibcon#read 3, iclass 7, count 0 2006.173.23:33:02.18#ibcon#about to read 4, iclass 7, count 0 2006.173.23:33:02.18#ibcon#read 4, iclass 7, count 0 2006.173.23:33:02.18#ibcon#about to read 5, iclass 7, count 0 2006.173.23:33:02.18#ibcon#read 5, iclass 7, count 0 2006.173.23:33:02.18#ibcon#about to read 6, iclass 7, count 0 2006.173.23:33:02.18#ibcon#read 6, iclass 7, count 0 2006.173.23:33:02.18#ibcon#end of sib2, iclass 7, count 0 2006.173.23:33:02.18#ibcon#*mode == 0, iclass 7, count 0 2006.173.23:33:02.18#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.23:33:02.18#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.23:33:02.18#ibcon#*before write, iclass 7, count 0 2006.173.23:33:02.18#ibcon#enter sib2, iclass 7, count 0 2006.173.23:33:02.18#ibcon#flushed, iclass 7, count 0 2006.173.23:33:02.18#ibcon#about to write, iclass 7, count 0 2006.173.23:33:02.18#ibcon#wrote, iclass 7, count 0 2006.173.23:33:02.18#ibcon#about to read 3, iclass 7, count 0 2006.173.23:33:02.22#ibcon#read 3, iclass 7, count 0 2006.173.23:33:02.22#ibcon#about to read 4, iclass 7, count 0 2006.173.23:33:02.22#ibcon#read 4, iclass 7, count 0 2006.173.23:33:02.22#ibcon#about to read 5, iclass 7, count 0 2006.173.23:33:02.22#ibcon#read 5, iclass 7, count 0 2006.173.23:33:02.22#ibcon#about to read 6, iclass 7, count 0 2006.173.23:33:02.22#ibcon#read 6, iclass 7, count 0 2006.173.23:33:02.22#ibcon#end of sib2, iclass 7, count 0 2006.173.23:33:02.22#ibcon#*after write, iclass 7, count 0 2006.173.23:33:02.22#ibcon#*before return 0, iclass 7, count 0 2006.173.23:33:02.22#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.23:33:02.22#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.23:33:02.22#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.23:33:02.22#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.23:33:02.22$vck44/va=7,4 2006.173.23:33:02.22#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.23:33:02.22#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.23:33:02.22#ibcon#ireg 11 cls_cnt 2 2006.173.23:33:02.22#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.23:33:02.28#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.23:33:02.28#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.23:33:02.28#ibcon#enter wrdev, iclass 11, count 2 2006.173.23:33:02.28#ibcon#first serial, iclass 11, count 2 2006.173.23:33:02.28#ibcon#enter sib2, iclass 11, count 2 2006.173.23:33:02.28#ibcon#flushed, iclass 11, count 2 2006.173.23:33:02.28#ibcon#about to write, iclass 11, count 2 2006.173.23:33:02.28#ibcon#wrote, iclass 11, count 2 2006.173.23:33:02.28#ibcon#about to read 3, iclass 11, count 2 2006.173.23:33:02.30#ibcon#read 3, iclass 11, count 2 2006.173.23:33:02.30#ibcon#about to read 4, iclass 11, count 2 2006.173.23:33:02.30#ibcon#read 4, iclass 11, count 2 2006.173.23:33:02.30#ibcon#about to read 5, iclass 11, count 2 2006.173.23:33:02.30#ibcon#read 5, iclass 11, count 2 2006.173.23:33:02.30#ibcon#about to read 6, iclass 11, count 2 2006.173.23:33:02.30#ibcon#read 6, iclass 11, count 2 2006.173.23:33:02.30#ibcon#end of sib2, iclass 11, count 2 2006.173.23:33:02.30#ibcon#*mode == 0, iclass 11, count 2 2006.173.23:33:02.30#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.23:33:02.30#ibcon#[25=AT07-04\r\n] 2006.173.23:33:02.30#ibcon#*before write, iclass 11, count 2 2006.173.23:33:02.30#ibcon#enter sib2, iclass 11, count 2 2006.173.23:33:02.30#ibcon#flushed, iclass 11, count 2 2006.173.23:33:02.30#ibcon#about to write, iclass 11, count 2 2006.173.23:33:02.30#ibcon#wrote, iclass 11, count 2 2006.173.23:33:02.30#ibcon#about to read 3, iclass 11, count 2 2006.173.23:33:02.33#ibcon#read 3, iclass 11, count 2 2006.173.23:33:02.33#ibcon#about to read 4, iclass 11, count 2 2006.173.23:33:02.33#ibcon#read 4, iclass 11, count 2 2006.173.23:33:02.33#ibcon#about to read 5, iclass 11, count 2 2006.173.23:33:02.33#ibcon#read 5, iclass 11, count 2 2006.173.23:33:02.33#ibcon#about to read 6, iclass 11, count 2 2006.173.23:33:02.33#ibcon#read 6, iclass 11, count 2 2006.173.23:33:02.33#ibcon#end of sib2, iclass 11, count 2 2006.173.23:33:02.33#ibcon#*after write, iclass 11, count 2 2006.173.23:33:02.33#ibcon#*before return 0, iclass 11, count 2 2006.173.23:33:02.33#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.23:33:02.33#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.23:33:02.33#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.23:33:02.33#ibcon#ireg 7 cls_cnt 0 2006.173.23:33:02.33#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.23:33:02.45#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.23:33:02.45#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.23:33:02.45#ibcon#enter wrdev, iclass 11, count 0 2006.173.23:33:02.45#ibcon#first serial, iclass 11, count 0 2006.173.23:33:02.45#ibcon#enter sib2, iclass 11, count 0 2006.173.23:33:02.45#ibcon#flushed, iclass 11, count 0 2006.173.23:33:02.45#ibcon#about to write, iclass 11, count 0 2006.173.23:33:02.45#ibcon#wrote, iclass 11, count 0 2006.173.23:33:02.45#ibcon#about to read 3, iclass 11, count 0 2006.173.23:33:02.47#ibcon#read 3, iclass 11, count 0 2006.173.23:33:02.47#ibcon#about to read 4, iclass 11, count 0 2006.173.23:33:02.47#ibcon#read 4, iclass 11, count 0 2006.173.23:33:02.47#ibcon#about to read 5, iclass 11, count 0 2006.173.23:33:02.47#ibcon#read 5, iclass 11, count 0 2006.173.23:33:02.47#ibcon#about to read 6, iclass 11, count 0 2006.173.23:33:02.47#ibcon#read 6, iclass 11, count 0 2006.173.23:33:02.47#ibcon#end of sib2, iclass 11, count 0 2006.173.23:33:02.47#ibcon#*mode == 0, iclass 11, count 0 2006.173.23:33:02.47#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.23:33:02.47#ibcon#[25=USB\r\n] 2006.173.23:33:02.47#ibcon#*before write, iclass 11, count 0 2006.173.23:33:02.47#ibcon#enter sib2, iclass 11, count 0 2006.173.23:33:02.47#ibcon#flushed, iclass 11, count 0 2006.173.23:33:02.47#ibcon#about to write, iclass 11, count 0 2006.173.23:33:02.47#ibcon#wrote, iclass 11, count 0 2006.173.23:33:02.47#ibcon#about to read 3, iclass 11, count 0 2006.173.23:33:02.50#ibcon#read 3, iclass 11, count 0 2006.173.23:33:02.50#ibcon#about to read 4, iclass 11, count 0 2006.173.23:33:02.50#ibcon#read 4, iclass 11, count 0 2006.173.23:33:02.50#ibcon#about to read 5, iclass 11, count 0 2006.173.23:33:02.50#ibcon#read 5, iclass 11, count 0 2006.173.23:33:02.50#ibcon#about to read 6, iclass 11, count 0 2006.173.23:33:02.50#ibcon#read 6, iclass 11, count 0 2006.173.23:33:02.50#ibcon#end of sib2, iclass 11, count 0 2006.173.23:33:02.50#ibcon#*after write, iclass 11, count 0 2006.173.23:33:02.50#ibcon#*before return 0, iclass 11, count 0 2006.173.23:33:02.50#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.23:33:02.50#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.23:33:02.50#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.23:33:02.50#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.23:33:02.50$vck44/valo=8,884.99 2006.173.23:33:02.50#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.23:33:02.50#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.23:33:02.50#ibcon#ireg 17 cls_cnt 0 2006.173.23:33:02.50#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.23:33:02.50#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.23:33:02.50#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.23:33:02.50#ibcon#enter wrdev, iclass 13, count 0 2006.173.23:33:02.50#ibcon#first serial, iclass 13, count 0 2006.173.23:33:02.50#ibcon#enter sib2, iclass 13, count 0 2006.173.23:33:02.50#ibcon#flushed, iclass 13, count 0 2006.173.23:33:02.50#ibcon#about to write, iclass 13, count 0 2006.173.23:33:02.50#ibcon#wrote, iclass 13, count 0 2006.173.23:33:02.50#ibcon#about to read 3, iclass 13, count 0 2006.173.23:33:02.52#ibcon#read 3, iclass 13, count 0 2006.173.23:33:02.52#ibcon#about to read 4, iclass 13, count 0 2006.173.23:33:02.52#ibcon#read 4, iclass 13, count 0 2006.173.23:33:02.52#ibcon#about to read 5, iclass 13, count 0 2006.173.23:33:02.52#ibcon#read 5, iclass 13, count 0 2006.173.23:33:02.52#ibcon#about to read 6, iclass 13, count 0 2006.173.23:33:02.52#ibcon#read 6, iclass 13, count 0 2006.173.23:33:02.52#ibcon#end of sib2, iclass 13, count 0 2006.173.23:33:02.52#ibcon#*mode == 0, iclass 13, count 0 2006.173.23:33:02.52#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.23:33:02.52#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.23:33:02.52#ibcon#*before write, iclass 13, count 0 2006.173.23:33:02.52#ibcon#enter sib2, iclass 13, count 0 2006.173.23:33:02.52#ibcon#flushed, iclass 13, count 0 2006.173.23:33:02.52#ibcon#about to write, iclass 13, count 0 2006.173.23:33:02.52#ibcon#wrote, iclass 13, count 0 2006.173.23:33:02.52#ibcon#about to read 3, iclass 13, count 0 2006.173.23:33:02.56#ibcon#read 3, iclass 13, count 0 2006.173.23:33:02.56#ibcon#about to read 4, iclass 13, count 0 2006.173.23:33:02.56#ibcon#read 4, iclass 13, count 0 2006.173.23:33:02.56#ibcon#about to read 5, iclass 13, count 0 2006.173.23:33:02.56#ibcon#read 5, iclass 13, count 0 2006.173.23:33:02.56#ibcon#about to read 6, iclass 13, count 0 2006.173.23:33:02.56#ibcon#read 6, iclass 13, count 0 2006.173.23:33:02.56#ibcon#end of sib2, iclass 13, count 0 2006.173.23:33:02.56#ibcon#*after write, iclass 13, count 0 2006.173.23:33:02.56#ibcon#*before return 0, iclass 13, count 0 2006.173.23:33:02.56#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.23:33:02.56#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.23:33:02.56#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.23:33:02.56#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.23:33:02.56$vck44/va=8,4 2006.173.23:33:02.56#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.23:33:02.56#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.23:33:02.56#ibcon#ireg 11 cls_cnt 2 2006.173.23:33:02.56#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.23:33:02.62#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.23:33:02.62#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.23:33:02.62#ibcon#enter wrdev, iclass 15, count 2 2006.173.23:33:02.62#ibcon#first serial, iclass 15, count 2 2006.173.23:33:02.62#ibcon#enter sib2, iclass 15, count 2 2006.173.23:33:02.62#ibcon#flushed, iclass 15, count 2 2006.173.23:33:02.62#ibcon#about to write, iclass 15, count 2 2006.173.23:33:02.62#ibcon#wrote, iclass 15, count 2 2006.173.23:33:02.62#ibcon#about to read 3, iclass 15, count 2 2006.173.23:33:02.64#ibcon#read 3, iclass 15, count 2 2006.173.23:33:02.64#ibcon#about to read 4, iclass 15, count 2 2006.173.23:33:02.64#ibcon#read 4, iclass 15, count 2 2006.173.23:33:02.64#ibcon#about to read 5, iclass 15, count 2 2006.173.23:33:02.64#ibcon#read 5, iclass 15, count 2 2006.173.23:33:02.64#ibcon#about to read 6, iclass 15, count 2 2006.173.23:33:02.64#ibcon#read 6, iclass 15, count 2 2006.173.23:33:02.64#ibcon#end of sib2, iclass 15, count 2 2006.173.23:33:02.64#ibcon#*mode == 0, iclass 15, count 2 2006.173.23:33:02.64#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.23:33:02.64#ibcon#[25=AT08-04\r\n] 2006.173.23:33:02.64#ibcon#*before write, iclass 15, count 2 2006.173.23:33:02.64#ibcon#enter sib2, iclass 15, count 2 2006.173.23:33:02.64#ibcon#flushed, iclass 15, count 2 2006.173.23:33:02.64#ibcon#about to write, iclass 15, count 2 2006.173.23:33:02.64#ibcon#wrote, iclass 15, count 2 2006.173.23:33:02.64#ibcon#about to read 3, iclass 15, count 2 2006.173.23:33:02.67#ibcon#read 3, iclass 15, count 2 2006.173.23:33:02.67#ibcon#about to read 4, iclass 15, count 2 2006.173.23:33:02.67#ibcon#read 4, iclass 15, count 2 2006.173.23:33:02.67#ibcon#about to read 5, iclass 15, count 2 2006.173.23:33:02.67#ibcon#read 5, iclass 15, count 2 2006.173.23:33:02.67#ibcon#about to read 6, iclass 15, count 2 2006.173.23:33:02.67#ibcon#read 6, iclass 15, count 2 2006.173.23:33:02.67#ibcon#end of sib2, iclass 15, count 2 2006.173.23:33:02.67#ibcon#*after write, iclass 15, count 2 2006.173.23:33:02.67#ibcon#*before return 0, iclass 15, count 2 2006.173.23:33:02.67#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.23:33:02.67#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.23:33:02.67#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.23:33:02.67#ibcon#ireg 7 cls_cnt 0 2006.173.23:33:02.67#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.23:33:02.79#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.23:33:02.79#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.23:33:02.79#ibcon#enter wrdev, iclass 15, count 0 2006.173.23:33:02.79#ibcon#first serial, iclass 15, count 0 2006.173.23:33:02.79#ibcon#enter sib2, iclass 15, count 0 2006.173.23:33:02.79#ibcon#flushed, iclass 15, count 0 2006.173.23:33:02.79#ibcon#about to write, iclass 15, count 0 2006.173.23:33:02.79#ibcon#wrote, iclass 15, count 0 2006.173.23:33:02.79#ibcon#about to read 3, iclass 15, count 0 2006.173.23:33:02.81#ibcon#read 3, iclass 15, count 0 2006.173.23:33:02.81#ibcon#about to read 4, iclass 15, count 0 2006.173.23:33:02.81#ibcon#read 4, iclass 15, count 0 2006.173.23:33:02.81#ibcon#about to read 5, iclass 15, count 0 2006.173.23:33:02.81#ibcon#read 5, iclass 15, count 0 2006.173.23:33:02.81#ibcon#about to read 6, iclass 15, count 0 2006.173.23:33:02.81#ibcon#read 6, iclass 15, count 0 2006.173.23:33:02.81#ibcon#end of sib2, iclass 15, count 0 2006.173.23:33:02.81#ibcon#*mode == 0, iclass 15, count 0 2006.173.23:33:02.81#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.23:33:02.81#ibcon#[25=USB\r\n] 2006.173.23:33:02.81#ibcon#*before write, iclass 15, count 0 2006.173.23:33:02.81#ibcon#enter sib2, iclass 15, count 0 2006.173.23:33:02.81#ibcon#flushed, iclass 15, count 0 2006.173.23:33:02.81#ibcon#about to write, iclass 15, count 0 2006.173.23:33:02.81#ibcon#wrote, iclass 15, count 0 2006.173.23:33:02.81#ibcon#about to read 3, iclass 15, count 0 2006.173.23:33:02.84#ibcon#read 3, iclass 15, count 0 2006.173.23:33:02.84#ibcon#about to read 4, iclass 15, count 0 2006.173.23:33:02.84#ibcon#read 4, iclass 15, count 0 2006.173.23:33:02.84#ibcon#about to read 5, iclass 15, count 0 2006.173.23:33:02.84#ibcon#read 5, iclass 15, count 0 2006.173.23:33:02.84#ibcon#about to read 6, iclass 15, count 0 2006.173.23:33:02.84#ibcon#read 6, iclass 15, count 0 2006.173.23:33:02.84#ibcon#end of sib2, iclass 15, count 0 2006.173.23:33:02.84#ibcon#*after write, iclass 15, count 0 2006.173.23:33:02.84#ibcon#*before return 0, iclass 15, count 0 2006.173.23:33:02.84#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.23:33:02.84#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.23:33:02.84#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.23:33:02.84#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.23:33:02.84$vck44/vblo=1,629.99 2006.173.23:33:02.84#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.23:33:02.84#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.23:33:02.84#ibcon#ireg 17 cls_cnt 0 2006.173.23:33:02.84#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.23:33:02.84#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.23:33:02.84#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.23:33:02.84#ibcon#enter wrdev, iclass 17, count 0 2006.173.23:33:02.84#ibcon#first serial, iclass 17, count 0 2006.173.23:33:02.84#ibcon#enter sib2, iclass 17, count 0 2006.173.23:33:02.84#ibcon#flushed, iclass 17, count 0 2006.173.23:33:02.84#ibcon#about to write, iclass 17, count 0 2006.173.23:33:02.84#ibcon#wrote, iclass 17, count 0 2006.173.23:33:02.84#ibcon#about to read 3, iclass 17, count 0 2006.173.23:33:02.86#ibcon#read 3, iclass 17, count 0 2006.173.23:33:02.86#ibcon#about to read 4, iclass 17, count 0 2006.173.23:33:02.86#ibcon#read 4, iclass 17, count 0 2006.173.23:33:02.86#ibcon#about to read 5, iclass 17, count 0 2006.173.23:33:02.86#ibcon#read 5, iclass 17, count 0 2006.173.23:33:02.86#ibcon#about to read 6, iclass 17, count 0 2006.173.23:33:02.86#ibcon#read 6, iclass 17, count 0 2006.173.23:33:02.86#ibcon#end of sib2, iclass 17, count 0 2006.173.23:33:02.86#ibcon#*mode == 0, iclass 17, count 0 2006.173.23:33:02.86#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.23:33:02.86#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.23:33:02.86#ibcon#*before write, iclass 17, count 0 2006.173.23:33:02.86#ibcon#enter sib2, iclass 17, count 0 2006.173.23:33:02.86#ibcon#flushed, iclass 17, count 0 2006.173.23:33:02.86#ibcon#about to write, iclass 17, count 0 2006.173.23:33:02.86#ibcon#wrote, iclass 17, count 0 2006.173.23:33:02.86#ibcon#about to read 3, iclass 17, count 0 2006.173.23:33:02.90#ibcon#read 3, iclass 17, count 0 2006.173.23:33:02.90#ibcon#about to read 4, iclass 17, count 0 2006.173.23:33:02.90#ibcon#read 4, iclass 17, count 0 2006.173.23:33:02.90#ibcon#about to read 5, iclass 17, count 0 2006.173.23:33:02.90#ibcon#read 5, iclass 17, count 0 2006.173.23:33:02.90#ibcon#about to read 6, iclass 17, count 0 2006.173.23:33:02.90#ibcon#read 6, iclass 17, count 0 2006.173.23:33:02.90#ibcon#end of sib2, iclass 17, count 0 2006.173.23:33:02.90#ibcon#*after write, iclass 17, count 0 2006.173.23:33:02.90#ibcon#*before return 0, iclass 17, count 0 2006.173.23:33:02.90#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.23:33:02.90#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.23:33:02.90#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.23:33:02.90#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.23:33:02.90$vck44/vb=1,4 2006.173.23:33:02.90#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.23:33:02.90#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.23:33:02.90#ibcon#ireg 11 cls_cnt 2 2006.173.23:33:02.90#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.23:33:02.90#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.23:33:02.90#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.23:33:02.90#ibcon#enter wrdev, iclass 19, count 2 2006.173.23:33:02.90#ibcon#first serial, iclass 19, count 2 2006.173.23:33:02.90#ibcon#enter sib2, iclass 19, count 2 2006.173.23:33:02.90#ibcon#flushed, iclass 19, count 2 2006.173.23:33:02.90#ibcon#about to write, iclass 19, count 2 2006.173.23:33:02.90#ibcon#wrote, iclass 19, count 2 2006.173.23:33:02.90#ibcon#about to read 3, iclass 19, count 2 2006.173.23:33:02.92#ibcon#read 3, iclass 19, count 2 2006.173.23:33:02.92#ibcon#about to read 4, iclass 19, count 2 2006.173.23:33:02.92#ibcon#read 4, iclass 19, count 2 2006.173.23:33:02.92#ibcon#about to read 5, iclass 19, count 2 2006.173.23:33:02.92#ibcon#read 5, iclass 19, count 2 2006.173.23:33:02.92#ibcon#about to read 6, iclass 19, count 2 2006.173.23:33:02.92#ibcon#read 6, iclass 19, count 2 2006.173.23:33:02.92#ibcon#end of sib2, iclass 19, count 2 2006.173.23:33:02.92#ibcon#*mode == 0, iclass 19, count 2 2006.173.23:33:02.92#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.23:33:02.92#ibcon#[27=AT01-04\r\n] 2006.173.23:33:02.92#ibcon#*before write, iclass 19, count 2 2006.173.23:33:02.92#ibcon#enter sib2, iclass 19, count 2 2006.173.23:33:02.92#ibcon#flushed, iclass 19, count 2 2006.173.23:33:02.92#ibcon#about to write, iclass 19, count 2 2006.173.23:33:02.92#ibcon#wrote, iclass 19, count 2 2006.173.23:33:02.92#ibcon#about to read 3, iclass 19, count 2 2006.173.23:33:02.95#ibcon#read 3, iclass 19, count 2 2006.173.23:33:02.95#ibcon#about to read 4, iclass 19, count 2 2006.173.23:33:02.95#ibcon#read 4, iclass 19, count 2 2006.173.23:33:02.95#ibcon#about to read 5, iclass 19, count 2 2006.173.23:33:02.95#ibcon#read 5, iclass 19, count 2 2006.173.23:33:02.95#ibcon#about to read 6, iclass 19, count 2 2006.173.23:33:02.95#ibcon#read 6, iclass 19, count 2 2006.173.23:33:02.95#ibcon#end of sib2, iclass 19, count 2 2006.173.23:33:02.95#ibcon#*after write, iclass 19, count 2 2006.173.23:33:02.95#ibcon#*before return 0, iclass 19, count 2 2006.173.23:33:02.95#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.23:33:02.95#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.23:33:02.95#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.23:33:02.95#ibcon#ireg 7 cls_cnt 0 2006.173.23:33:02.95#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.23:33:03.07#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.23:33:03.07#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.23:33:03.07#ibcon#enter wrdev, iclass 19, count 0 2006.173.23:33:03.07#ibcon#first serial, iclass 19, count 0 2006.173.23:33:03.07#ibcon#enter sib2, iclass 19, count 0 2006.173.23:33:03.07#ibcon#flushed, iclass 19, count 0 2006.173.23:33:03.07#ibcon#about to write, iclass 19, count 0 2006.173.23:33:03.07#ibcon#wrote, iclass 19, count 0 2006.173.23:33:03.07#ibcon#about to read 3, iclass 19, count 0 2006.173.23:33:03.09#ibcon#read 3, iclass 19, count 0 2006.173.23:33:03.09#ibcon#about to read 4, iclass 19, count 0 2006.173.23:33:03.09#ibcon#read 4, iclass 19, count 0 2006.173.23:33:03.09#ibcon#about to read 5, iclass 19, count 0 2006.173.23:33:03.09#ibcon#read 5, iclass 19, count 0 2006.173.23:33:03.09#ibcon#about to read 6, iclass 19, count 0 2006.173.23:33:03.09#ibcon#read 6, iclass 19, count 0 2006.173.23:33:03.09#ibcon#end of sib2, iclass 19, count 0 2006.173.23:33:03.09#ibcon#*mode == 0, iclass 19, count 0 2006.173.23:33:03.09#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.23:33:03.09#ibcon#[27=USB\r\n] 2006.173.23:33:03.09#ibcon#*before write, iclass 19, count 0 2006.173.23:33:03.09#ibcon#enter sib2, iclass 19, count 0 2006.173.23:33:03.09#ibcon#flushed, iclass 19, count 0 2006.173.23:33:03.09#ibcon#about to write, iclass 19, count 0 2006.173.23:33:03.09#ibcon#wrote, iclass 19, count 0 2006.173.23:33:03.09#ibcon#about to read 3, iclass 19, count 0 2006.173.23:33:03.12#ibcon#read 3, iclass 19, count 0 2006.173.23:33:03.12#ibcon#about to read 4, iclass 19, count 0 2006.173.23:33:03.12#ibcon#read 4, iclass 19, count 0 2006.173.23:33:03.12#ibcon#about to read 5, iclass 19, count 0 2006.173.23:33:03.12#ibcon#read 5, iclass 19, count 0 2006.173.23:33:03.12#ibcon#about to read 6, iclass 19, count 0 2006.173.23:33:03.12#ibcon#read 6, iclass 19, count 0 2006.173.23:33:03.12#ibcon#end of sib2, iclass 19, count 0 2006.173.23:33:03.12#ibcon#*after write, iclass 19, count 0 2006.173.23:33:03.12#ibcon#*before return 0, iclass 19, count 0 2006.173.23:33:03.12#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.23:33:03.12#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.23:33:03.12#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.23:33:03.12#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.23:33:03.12$vck44/vblo=2,634.99 2006.173.23:33:03.12#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.23:33:03.12#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.23:33:03.12#ibcon#ireg 17 cls_cnt 0 2006.173.23:33:03.12#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.23:33:03.12#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.23:33:03.12#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.23:33:03.12#ibcon#enter wrdev, iclass 21, count 0 2006.173.23:33:03.12#ibcon#first serial, iclass 21, count 0 2006.173.23:33:03.12#ibcon#enter sib2, iclass 21, count 0 2006.173.23:33:03.12#ibcon#flushed, iclass 21, count 0 2006.173.23:33:03.12#ibcon#about to write, iclass 21, count 0 2006.173.23:33:03.12#ibcon#wrote, iclass 21, count 0 2006.173.23:33:03.12#ibcon#about to read 3, iclass 21, count 0 2006.173.23:33:03.14#ibcon#read 3, iclass 21, count 0 2006.173.23:33:03.14#ibcon#about to read 4, iclass 21, count 0 2006.173.23:33:03.14#ibcon#read 4, iclass 21, count 0 2006.173.23:33:03.14#ibcon#about to read 5, iclass 21, count 0 2006.173.23:33:03.14#ibcon#read 5, iclass 21, count 0 2006.173.23:33:03.14#ibcon#about to read 6, iclass 21, count 0 2006.173.23:33:03.14#ibcon#read 6, iclass 21, count 0 2006.173.23:33:03.14#ibcon#end of sib2, iclass 21, count 0 2006.173.23:33:03.14#ibcon#*mode == 0, iclass 21, count 0 2006.173.23:33:03.14#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.23:33:03.14#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.23:33:03.14#ibcon#*before write, iclass 21, count 0 2006.173.23:33:03.14#ibcon#enter sib2, iclass 21, count 0 2006.173.23:33:03.14#ibcon#flushed, iclass 21, count 0 2006.173.23:33:03.14#ibcon#about to write, iclass 21, count 0 2006.173.23:33:03.14#ibcon#wrote, iclass 21, count 0 2006.173.23:33:03.14#ibcon#about to read 3, iclass 21, count 0 2006.173.23:33:03.18#ibcon#read 3, iclass 21, count 0 2006.173.23:33:03.18#ibcon#about to read 4, iclass 21, count 0 2006.173.23:33:03.18#ibcon#read 4, iclass 21, count 0 2006.173.23:33:03.18#ibcon#about to read 5, iclass 21, count 0 2006.173.23:33:03.18#ibcon#read 5, iclass 21, count 0 2006.173.23:33:03.18#ibcon#about to read 6, iclass 21, count 0 2006.173.23:33:03.18#ibcon#read 6, iclass 21, count 0 2006.173.23:33:03.18#ibcon#end of sib2, iclass 21, count 0 2006.173.23:33:03.18#ibcon#*after write, iclass 21, count 0 2006.173.23:33:03.18#ibcon#*before return 0, iclass 21, count 0 2006.173.23:33:03.18#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.23:33:03.18#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.23:33:03.18#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.23:33:03.18#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.23:33:03.18$vck44/vb=2,4 2006.173.23:33:03.18#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.23:33:03.18#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.23:33:03.18#ibcon#ireg 11 cls_cnt 2 2006.173.23:33:03.18#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.23:33:03.24#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.23:33:03.24#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.23:33:03.24#ibcon#enter wrdev, iclass 23, count 2 2006.173.23:33:03.24#ibcon#first serial, iclass 23, count 2 2006.173.23:33:03.24#ibcon#enter sib2, iclass 23, count 2 2006.173.23:33:03.24#ibcon#flushed, iclass 23, count 2 2006.173.23:33:03.24#ibcon#about to write, iclass 23, count 2 2006.173.23:33:03.24#ibcon#wrote, iclass 23, count 2 2006.173.23:33:03.24#ibcon#about to read 3, iclass 23, count 2 2006.173.23:33:03.26#ibcon#read 3, iclass 23, count 2 2006.173.23:33:03.26#ibcon#about to read 4, iclass 23, count 2 2006.173.23:33:03.26#ibcon#read 4, iclass 23, count 2 2006.173.23:33:03.26#ibcon#about to read 5, iclass 23, count 2 2006.173.23:33:03.26#ibcon#read 5, iclass 23, count 2 2006.173.23:33:03.26#ibcon#about to read 6, iclass 23, count 2 2006.173.23:33:03.26#ibcon#read 6, iclass 23, count 2 2006.173.23:33:03.26#ibcon#end of sib2, iclass 23, count 2 2006.173.23:33:03.26#ibcon#*mode == 0, iclass 23, count 2 2006.173.23:33:03.26#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.23:33:03.26#ibcon#[27=AT02-04\r\n] 2006.173.23:33:03.26#ibcon#*before write, iclass 23, count 2 2006.173.23:33:03.26#ibcon#enter sib2, iclass 23, count 2 2006.173.23:33:03.26#ibcon#flushed, iclass 23, count 2 2006.173.23:33:03.26#ibcon#about to write, iclass 23, count 2 2006.173.23:33:03.26#ibcon#wrote, iclass 23, count 2 2006.173.23:33:03.26#ibcon#about to read 3, iclass 23, count 2 2006.173.23:33:03.29#ibcon#read 3, iclass 23, count 2 2006.173.23:33:03.29#ibcon#about to read 4, iclass 23, count 2 2006.173.23:33:03.29#ibcon#read 4, iclass 23, count 2 2006.173.23:33:03.29#ibcon#about to read 5, iclass 23, count 2 2006.173.23:33:03.29#ibcon#read 5, iclass 23, count 2 2006.173.23:33:03.29#ibcon#about to read 6, iclass 23, count 2 2006.173.23:33:03.29#ibcon#read 6, iclass 23, count 2 2006.173.23:33:03.29#ibcon#end of sib2, iclass 23, count 2 2006.173.23:33:03.29#ibcon#*after write, iclass 23, count 2 2006.173.23:33:03.29#ibcon#*before return 0, iclass 23, count 2 2006.173.23:33:03.29#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.23:33:03.29#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.23:33:03.29#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.23:33:03.29#ibcon#ireg 7 cls_cnt 0 2006.173.23:33:03.29#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.23:33:03.41#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.23:33:03.41#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.23:33:03.41#ibcon#enter wrdev, iclass 23, count 0 2006.173.23:33:03.41#ibcon#first serial, iclass 23, count 0 2006.173.23:33:03.41#ibcon#enter sib2, iclass 23, count 0 2006.173.23:33:03.41#ibcon#flushed, iclass 23, count 0 2006.173.23:33:03.41#ibcon#about to write, iclass 23, count 0 2006.173.23:33:03.41#ibcon#wrote, iclass 23, count 0 2006.173.23:33:03.41#ibcon#about to read 3, iclass 23, count 0 2006.173.23:33:03.43#ibcon#read 3, iclass 23, count 0 2006.173.23:33:03.43#ibcon#about to read 4, iclass 23, count 0 2006.173.23:33:03.43#ibcon#read 4, iclass 23, count 0 2006.173.23:33:03.43#ibcon#about to read 5, iclass 23, count 0 2006.173.23:33:03.43#ibcon#read 5, iclass 23, count 0 2006.173.23:33:03.43#ibcon#about to read 6, iclass 23, count 0 2006.173.23:33:03.43#ibcon#read 6, iclass 23, count 0 2006.173.23:33:03.43#ibcon#end of sib2, iclass 23, count 0 2006.173.23:33:03.43#ibcon#*mode == 0, iclass 23, count 0 2006.173.23:33:03.43#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.23:33:03.43#ibcon#[27=USB\r\n] 2006.173.23:33:03.43#ibcon#*before write, iclass 23, count 0 2006.173.23:33:03.43#ibcon#enter sib2, iclass 23, count 0 2006.173.23:33:03.43#ibcon#flushed, iclass 23, count 0 2006.173.23:33:03.43#ibcon#about to write, iclass 23, count 0 2006.173.23:33:03.43#ibcon#wrote, iclass 23, count 0 2006.173.23:33:03.43#ibcon#about to read 3, iclass 23, count 0 2006.173.23:33:03.46#ibcon#read 3, iclass 23, count 0 2006.173.23:33:03.46#ibcon#about to read 4, iclass 23, count 0 2006.173.23:33:03.46#ibcon#read 4, iclass 23, count 0 2006.173.23:33:03.46#ibcon#about to read 5, iclass 23, count 0 2006.173.23:33:03.46#ibcon#read 5, iclass 23, count 0 2006.173.23:33:03.46#ibcon#about to read 6, iclass 23, count 0 2006.173.23:33:03.46#ibcon#read 6, iclass 23, count 0 2006.173.23:33:03.46#ibcon#end of sib2, iclass 23, count 0 2006.173.23:33:03.46#ibcon#*after write, iclass 23, count 0 2006.173.23:33:03.46#ibcon#*before return 0, iclass 23, count 0 2006.173.23:33:03.46#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.23:33:03.46#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.23:33:03.46#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.23:33:03.46#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.23:33:03.46$vck44/vblo=3,649.99 2006.173.23:33:03.46#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.23:33:03.46#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.23:33:03.46#ibcon#ireg 17 cls_cnt 0 2006.173.23:33:03.46#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.23:33:03.46#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.23:33:03.46#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.23:33:03.46#ibcon#enter wrdev, iclass 25, count 0 2006.173.23:33:03.46#ibcon#first serial, iclass 25, count 0 2006.173.23:33:03.46#ibcon#enter sib2, iclass 25, count 0 2006.173.23:33:03.46#ibcon#flushed, iclass 25, count 0 2006.173.23:33:03.46#ibcon#about to write, iclass 25, count 0 2006.173.23:33:03.46#ibcon#wrote, iclass 25, count 0 2006.173.23:33:03.46#ibcon#about to read 3, iclass 25, count 0 2006.173.23:33:03.48#ibcon#read 3, iclass 25, count 0 2006.173.23:33:03.48#ibcon#about to read 4, iclass 25, count 0 2006.173.23:33:03.48#ibcon#read 4, iclass 25, count 0 2006.173.23:33:03.48#ibcon#about to read 5, iclass 25, count 0 2006.173.23:33:03.48#ibcon#read 5, iclass 25, count 0 2006.173.23:33:03.48#ibcon#about to read 6, iclass 25, count 0 2006.173.23:33:03.48#ibcon#read 6, iclass 25, count 0 2006.173.23:33:03.48#ibcon#end of sib2, iclass 25, count 0 2006.173.23:33:03.48#ibcon#*mode == 0, iclass 25, count 0 2006.173.23:33:03.48#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.23:33:03.48#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.23:33:03.48#ibcon#*before write, iclass 25, count 0 2006.173.23:33:03.48#ibcon#enter sib2, iclass 25, count 0 2006.173.23:33:03.48#ibcon#flushed, iclass 25, count 0 2006.173.23:33:03.48#ibcon#about to write, iclass 25, count 0 2006.173.23:33:03.48#ibcon#wrote, iclass 25, count 0 2006.173.23:33:03.48#ibcon#about to read 3, iclass 25, count 0 2006.173.23:33:03.52#ibcon#read 3, iclass 25, count 0 2006.173.23:33:03.52#ibcon#about to read 4, iclass 25, count 0 2006.173.23:33:03.52#ibcon#read 4, iclass 25, count 0 2006.173.23:33:03.52#ibcon#about to read 5, iclass 25, count 0 2006.173.23:33:03.52#ibcon#read 5, iclass 25, count 0 2006.173.23:33:03.52#ibcon#about to read 6, iclass 25, count 0 2006.173.23:33:03.52#ibcon#read 6, iclass 25, count 0 2006.173.23:33:03.52#ibcon#end of sib2, iclass 25, count 0 2006.173.23:33:03.52#ibcon#*after write, iclass 25, count 0 2006.173.23:33:03.52#ibcon#*before return 0, iclass 25, count 0 2006.173.23:33:03.52#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.23:33:03.52#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.23:33:03.52#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.23:33:03.52#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.23:33:03.52$vck44/vb=3,4 2006.173.23:33:03.52#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.23:33:03.52#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.23:33:03.52#ibcon#ireg 11 cls_cnt 2 2006.173.23:33:03.52#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.23:33:03.58#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.23:33:03.58#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.23:33:03.58#ibcon#enter wrdev, iclass 27, count 2 2006.173.23:33:03.58#ibcon#first serial, iclass 27, count 2 2006.173.23:33:03.58#ibcon#enter sib2, iclass 27, count 2 2006.173.23:33:03.58#ibcon#flushed, iclass 27, count 2 2006.173.23:33:03.58#ibcon#about to write, iclass 27, count 2 2006.173.23:33:03.58#ibcon#wrote, iclass 27, count 2 2006.173.23:33:03.58#ibcon#about to read 3, iclass 27, count 2 2006.173.23:33:03.60#ibcon#read 3, iclass 27, count 2 2006.173.23:33:03.60#ibcon#about to read 4, iclass 27, count 2 2006.173.23:33:03.60#ibcon#read 4, iclass 27, count 2 2006.173.23:33:03.60#ibcon#about to read 5, iclass 27, count 2 2006.173.23:33:03.60#ibcon#read 5, iclass 27, count 2 2006.173.23:33:03.60#ibcon#about to read 6, iclass 27, count 2 2006.173.23:33:03.60#ibcon#read 6, iclass 27, count 2 2006.173.23:33:03.60#ibcon#end of sib2, iclass 27, count 2 2006.173.23:33:03.60#ibcon#*mode == 0, iclass 27, count 2 2006.173.23:33:03.60#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.23:33:03.60#ibcon#[27=AT03-04\r\n] 2006.173.23:33:03.60#ibcon#*before write, iclass 27, count 2 2006.173.23:33:03.60#ibcon#enter sib2, iclass 27, count 2 2006.173.23:33:03.60#ibcon#flushed, iclass 27, count 2 2006.173.23:33:03.60#ibcon#about to write, iclass 27, count 2 2006.173.23:33:03.60#ibcon#wrote, iclass 27, count 2 2006.173.23:33:03.60#ibcon#about to read 3, iclass 27, count 2 2006.173.23:33:03.63#ibcon#read 3, iclass 27, count 2 2006.173.23:33:03.63#ibcon#about to read 4, iclass 27, count 2 2006.173.23:33:03.63#ibcon#read 4, iclass 27, count 2 2006.173.23:33:03.63#ibcon#about to read 5, iclass 27, count 2 2006.173.23:33:03.63#ibcon#read 5, iclass 27, count 2 2006.173.23:33:03.63#ibcon#about to read 6, iclass 27, count 2 2006.173.23:33:03.63#ibcon#read 6, iclass 27, count 2 2006.173.23:33:03.63#ibcon#end of sib2, iclass 27, count 2 2006.173.23:33:03.63#ibcon#*after write, iclass 27, count 2 2006.173.23:33:03.63#ibcon#*before return 0, iclass 27, count 2 2006.173.23:33:03.63#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.23:33:03.63#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.23:33:03.63#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.23:33:03.63#ibcon#ireg 7 cls_cnt 0 2006.173.23:33:03.63#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.23:33:03.75#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.23:33:03.75#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.23:33:03.75#ibcon#enter wrdev, iclass 27, count 0 2006.173.23:33:03.75#ibcon#first serial, iclass 27, count 0 2006.173.23:33:03.75#ibcon#enter sib2, iclass 27, count 0 2006.173.23:33:03.75#ibcon#flushed, iclass 27, count 0 2006.173.23:33:03.75#ibcon#about to write, iclass 27, count 0 2006.173.23:33:03.75#ibcon#wrote, iclass 27, count 0 2006.173.23:33:03.75#ibcon#about to read 3, iclass 27, count 0 2006.173.23:33:03.77#ibcon#read 3, iclass 27, count 0 2006.173.23:33:03.77#ibcon#about to read 4, iclass 27, count 0 2006.173.23:33:03.77#ibcon#read 4, iclass 27, count 0 2006.173.23:33:03.77#ibcon#about to read 5, iclass 27, count 0 2006.173.23:33:03.77#ibcon#read 5, iclass 27, count 0 2006.173.23:33:03.77#ibcon#about to read 6, iclass 27, count 0 2006.173.23:33:03.77#ibcon#read 6, iclass 27, count 0 2006.173.23:33:03.77#ibcon#end of sib2, iclass 27, count 0 2006.173.23:33:03.77#ibcon#*mode == 0, iclass 27, count 0 2006.173.23:33:03.77#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.23:33:03.77#ibcon#[27=USB\r\n] 2006.173.23:33:03.77#ibcon#*before write, iclass 27, count 0 2006.173.23:33:03.77#ibcon#enter sib2, iclass 27, count 0 2006.173.23:33:03.77#ibcon#flushed, iclass 27, count 0 2006.173.23:33:03.77#ibcon#about to write, iclass 27, count 0 2006.173.23:33:03.77#ibcon#wrote, iclass 27, count 0 2006.173.23:33:03.77#ibcon#about to read 3, iclass 27, count 0 2006.173.23:33:03.80#ibcon#read 3, iclass 27, count 0 2006.173.23:33:03.80#ibcon#about to read 4, iclass 27, count 0 2006.173.23:33:03.80#ibcon#read 4, iclass 27, count 0 2006.173.23:33:03.80#ibcon#about to read 5, iclass 27, count 0 2006.173.23:33:03.80#ibcon#read 5, iclass 27, count 0 2006.173.23:33:03.80#ibcon#about to read 6, iclass 27, count 0 2006.173.23:33:03.80#ibcon#read 6, iclass 27, count 0 2006.173.23:33:03.80#ibcon#end of sib2, iclass 27, count 0 2006.173.23:33:03.80#ibcon#*after write, iclass 27, count 0 2006.173.23:33:03.80#ibcon#*before return 0, iclass 27, count 0 2006.173.23:33:03.80#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.23:33:03.80#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.23:33:03.80#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.23:33:03.80#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.23:33:03.80$vck44/vblo=4,679.99 2006.173.23:33:03.80#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.23:33:03.80#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.23:33:03.80#ibcon#ireg 17 cls_cnt 0 2006.173.23:33:03.80#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.23:33:03.80#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.23:33:03.80#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.23:33:03.80#ibcon#enter wrdev, iclass 29, count 0 2006.173.23:33:03.80#ibcon#first serial, iclass 29, count 0 2006.173.23:33:03.80#ibcon#enter sib2, iclass 29, count 0 2006.173.23:33:03.80#ibcon#flushed, iclass 29, count 0 2006.173.23:33:03.80#ibcon#about to write, iclass 29, count 0 2006.173.23:33:03.80#ibcon#wrote, iclass 29, count 0 2006.173.23:33:03.80#ibcon#about to read 3, iclass 29, count 0 2006.173.23:33:03.82#ibcon#read 3, iclass 29, count 0 2006.173.23:33:03.82#ibcon#about to read 4, iclass 29, count 0 2006.173.23:33:03.82#ibcon#read 4, iclass 29, count 0 2006.173.23:33:03.82#ibcon#about to read 5, iclass 29, count 0 2006.173.23:33:03.82#ibcon#read 5, iclass 29, count 0 2006.173.23:33:03.82#ibcon#about to read 6, iclass 29, count 0 2006.173.23:33:03.82#ibcon#read 6, iclass 29, count 0 2006.173.23:33:03.82#ibcon#end of sib2, iclass 29, count 0 2006.173.23:33:03.82#ibcon#*mode == 0, iclass 29, count 0 2006.173.23:33:03.82#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.23:33:03.82#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.23:33:03.82#ibcon#*before write, iclass 29, count 0 2006.173.23:33:03.82#ibcon#enter sib2, iclass 29, count 0 2006.173.23:33:03.82#ibcon#flushed, iclass 29, count 0 2006.173.23:33:03.82#ibcon#about to write, iclass 29, count 0 2006.173.23:33:03.82#ibcon#wrote, iclass 29, count 0 2006.173.23:33:03.82#ibcon#about to read 3, iclass 29, count 0 2006.173.23:33:03.86#ibcon#read 3, iclass 29, count 0 2006.173.23:33:03.86#ibcon#about to read 4, iclass 29, count 0 2006.173.23:33:03.86#ibcon#read 4, iclass 29, count 0 2006.173.23:33:03.86#ibcon#about to read 5, iclass 29, count 0 2006.173.23:33:03.86#ibcon#read 5, iclass 29, count 0 2006.173.23:33:03.86#ibcon#about to read 6, iclass 29, count 0 2006.173.23:33:03.86#ibcon#read 6, iclass 29, count 0 2006.173.23:33:03.86#ibcon#end of sib2, iclass 29, count 0 2006.173.23:33:03.86#ibcon#*after write, iclass 29, count 0 2006.173.23:33:03.86#ibcon#*before return 0, iclass 29, count 0 2006.173.23:33:03.86#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.23:33:03.86#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.23:33:03.86#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.23:33:03.86#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.23:33:03.86$vck44/vb=4,4 2006.173.23:33:03.86#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.23:33:03.86#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.23:33:03.86#ibcon#ireg 11 cls_cnt 2 2006.173.23:33:03.86#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.23:33:03.92#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.23:33:03.92#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.23:33:03.92#ibcon#enter wrdev, iclass 31, count 2 2006.173.23:33:03.92#ibcon#first serial, iclass 31, count 2 2006.173.23:33:03.92#ibcon#enter sib2, iclass 31, count 2 2006.173.23:33:03.92#ibcon#flushed, iclass 31, count 2 2006.173.23:33:03.92#ibcon#about to write, iclass 31, count 2 2006.173.23:33:03.92#ibcon#wrote, iclass 31, count 2 2006.173.23:33:03.92#ibcon#about to read 3, iclass 31, count 2 2006.173.23:33:03.94#ibcon#read 3, iclass 31, count 2 2006.173.23:33:03.94#ibcon#about to read 4, iclass 31, count 2 2006.173.23:33:03.94#ibcon#read 4, iclass 31, count 2 2006.173.23:33:03.94#ibcon#about to read 5, iclass 31, count 2 2006.173.23:33:03.94#ibcon#read 5, iclass 31, count 2 2006.173.23:33:03.94#ibcon#about to read 6, iclass 31, count 2 2006.173.23:33:03.94#ibcon#read 6, iclass 31, count 2 2006.173.23:33:03.94#ibcon#end of sib2, iclass 31, count 2 2006.173.23:33:03.94#ibcon#*mode == 0, iclass 31, count 2 2006.173.23:33:03.94#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.23:33:03.94#ibcon#[27=AT04-04\r\n] 2006.173.23:33:03.94#ibcon#*before write, iclass 31, count 2 2006.173.23:33:03.94#ibcon#enter sib2, iclass 31, count 2 2006.173.23:33:03.94#ibcon#flushed, iclass 31, count 2 2006.173.23:33:03.94#ibcon#about to write, iclass 31, count 2 2006.173.23:33:03.94#ibcon#wrote, iclass 31, count 2 2006.173.23:33:03.94#ibcon#about to read 3, iclass 31, count 2 2006.173.23:33:03.97#ibcon#read 3, iclass 31, count 2 2006.173.23:33:03.97#ibcon#about to read 4, iclass 31, count 2 2006.173.23:33:03.97#ibcon#read 4, iclass 31, count 2 2006.173.23:33:03.97#ibcon#about to read 5, iclass 31, count 2 2006.173.23:33:03.97#ibcon#read 5, iclass 31, count 2 2006.173.23:33:03.97#ibcon#about to read 6, iclass 31, count 2 2006.173.23:33:03.97#ibcon#read 6, iclass 31, count 2 2006.173.23:33:03.97#ibcon#end of sib2, iclass 31, count 2 2006.173.23:33:03.97#ibcon#*after write, iclass 31, count 2 2006.173.23:33:03.97#ibcon#*before return 0, iclass 31, count 2 2006.173.23:33:03.97#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.23:33:03.97#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.23:33:03.97#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.23:33:03.97#ibcon#ireg 7 cls_cnt 0 2006.173.23:33:03.97#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.23:33:04.09#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.23:33:04.09#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.23:33:04.09#ibcon#enter wrdev, iclass 31, count 0 2006.173.23:33:04.09#ibcon#first serial, iclass 31, count 0 2006.173.23:33:04.09#ibcon#enter sib2, iclass 31, count 0 2006.173.23:33:04.09#ibcon#flushed, iclass 31, count 0 2006.173.23:33:04.09#ibcon#about to write, iclass 31, count 0 2006.173.23:33:04.09#ibcon#wrote, iclass 31, count 0 2006.173.23:33:04.09#ibcon#about to read 3, iclass 31, count 0 2006.173.23:33:04.11#ibcon#read 3, iclass 31, count 0 2006.173.23:33:04.11#ibcon#about to read 4, iclass 31, count 0 2006.173.23:33:04.11#ibcon#read 4, iclass 31, count 0 2006.173.23:33:04.11#ibcon#about to read 5, iclass 31, count 0 2006.173.23:33:04.11#ibcon#read 5, iclass 31, count 0 2006.173.23:33:04.11#ibcon#about to read 6, iclass 31, count 0 2006.173.23:33:04.11#ibcon#read 6, iclass 31, count 0 2006.173.23:33:04.11#ibcon#end of sib2, iclass 31, count 0 2006.173.23:33:04.11#ibcon#*mode == 0, iclass 31, count 0 2006.173.23:33:04.11#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.23:33:04.11#ibcon#[27=USB\r\n] 2006.173.23:33:04.11#ibcon#*before write, iclass 31, count 0 2006.173.23:33:04.11#ibcon#enter sib2, iclass 31, count 0 2006.173.23:33:04.11#ibcon#flushed, iclass 31, count 0 2006.173.23:33:04.11#ibcon#about to write, iclass 31, count 0 2006.173.23:33:04.11#ibcon#wrote, iclass 31, count 0 2006.173.23:33:04.11#ibcon#about to read 3, iclass 31, count 0 2006.173.23:33:04.14#ibcon#read 3, iclass 31, count 0 2006.173.23:33:04.14#ibcon#about to read 4, iclass 31, count 0 2006.173.23:33:04.14#ibcon#read 4, iclass 31, count 0 2006.173.23:33:04.14#ibcon#about to read 5, iclass 31, count 0 2006.173.23:33:04.14#ibcon#read 5, iclass 31, count 0 2006.173.23:33:04.14#ibcon#about to read 6, iclass 31, count 0 2006.173.23:33:04.14#ibcon#read 6, iclass 31, count 0 2006.173.23:33:04.14#ibcon#end of sib2, iclass 31, count 0 2006.173.23:33:04.14#ibcon#*after write, iclass 31, count 0 2006.173.23:33:04.14#ibcon#*before return 0, iclass 31, count 0 2006.173.23:33:04.14#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.23:33:04.14#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.23:33:04.14#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.23:33:04.14#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.23:33:04.14$vck44/vblo=5,709.99 2006.173.23:33:04.14#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.23:33:04.14#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.23:33:04.14#ibcon#ireg 17 cls_cnt 0 2006.173.23:33:04.14#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.23:33:04.14#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.23:33:04.14#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.23:33:04.14#ibcon#enter wrdev, iclass 33, count 0 2006.173.23:33:04.14#ibcon#first serial, iclass 33, count 0 2006.173.23:33:04.14#ibcon#enter sib2, iclass 33, count 0 2006.173.23:33:04.14#ibcon#flushed, iclass 33, count 0 2006.173.23:33:04.14#ibcon#about to write, iclass 33, count 0 2006.173.23:33:04.14#ibcon#wrote, iclass 33, count 0 2006.173.23:33:04.14#ibcon#about to read 3, iclass 33, count 0 2006.173.23:33:04.16#ibcon#read 3, iclass 33, count 0 2006.173.23:33:04.16#ibcon#about to read 4, iclass 33, count 0 2006.173.23:33:04.16#ibcon#read 4, iclass 33, count 0 2006.173.23:33:04.16#ibcon#about to read 5, iclass 33, count 0 2006.173.23:33:04.16#ibcon#read 5, iclass 33, count 0 2006.173.23:33:04.16#ibcon#about to read 6, iclass 33, count 0 2006.173.23:33:04.16#ibcon#read 6, iclass 33, count 0 2006.173.23:33:04.16#ibcon#end of sib2, iclass 33, count 0 2006.173.23:33:04.16#ibcon#*mode == 0, iclass 33, count 0 2006.173.23:33:04.16#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.23:33:04.16#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.23:33:04.16#ibcon#*before write, iclass 33, count 0 2006.173.23:33:04.16#ibcon#enter sib2, iclass 33, count 0 2006.173.23:33:04.16#ibcon#flushed, iclass 33, count 0 2006.173.23:33:04.16#ibcon#about to write, iclass 33, count 0 2006.173.23:33:04.16#ibcon#wrote, iclass 33, count 0 2006.173.23:33:04.16#ibcon#about to read 3, iclass 33, count 0 2006.173.23:33:04.20#ibcon#read 3, iclass 33, count 0 2006.173.23:33:04.20#ibcon#about to read 4, iclass 33, count 0 2006.173.23:33:04.20#ibcon#read 4, iclass 33, count 0 2006.173.23:33:04.20#ibcon#about to read 5, iclass 33, count 0 2006.173.23:33:04.20#ibcon#read 5, iclass 33, count 0 2006.173.23:33:04.20#ibcon#about to read 6, iclass 33, count 0 2006.173.23:33:04.20#ibcon#read 6, iclass 33, count 0 2006.173.23:33:04.20#ibcon#end of sib2, iclass 33, count 0 2006.173.23:33:04.20#ibcon#*after write, iclass 33, count 0 2006.173.23:33:04.20#ibcon#*before return 0, iclass 33, count 0 2006.173.23:33:04.20#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.23:33:04.20#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.23:33:04.20#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.23:33:04.20#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.23:33:04.20$vck44/vb=5,4 2006.173.23:33:04.20#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.23:33:04.20#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.23:33:04.20#ibcon#ireg 11 cls_cnt 2 2006.173.23:33:04.20#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.23:33:04.26#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.23:33:04.26#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.23:33:04.26#ibcon#enter wrdev, iclass 35, count 2 2006.173.23:33:04.26#ibcon#first serial, iclass 35, count 2 2006.173.23:33:04.26#ibcon#enter sib2, iclass 35, count 2 2006.173.23:33:04.26#ibcon#flushed, iclass 35, count 2 2006.173.23:33:04.26#ibcon#about to write, iclass 35, count 2 2006.173.23:33:04.26#ibcon#wrote, iclass 35, count 2 2006.173.23:33:04.26#ibcon#about to read 3, iclass 35, count 2 2006.173.23:33:04.28#ibcon#read 3, iclass 35, count 2 2006.173.23:33:04.28#ibcon#about to read 4, iclass 35, count 2 2006.173.23:33:04.28#ibcon#read 4, iclass 35, count 2 2006.173.23:33:04.28#ibcon#about to read 5, iclass 35, count 2 2006.173.23:33:04.28#ibcon#read 5, iclass 35, count 2 2006.173.23:33:04.28#ibcon#about to read 6, iclass 35, count 2 2006.173.23:33:04.28#ibcon#read 6, iclass 35, count 2 2006.173.23:33:04.28#ibcon#end of sib2, iclass 35, count 2 2006.173.23:33:04.28#ibcon#*mode == 0, iclass 35, count 2 2006.173.23:33:04.28#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.23:33:04.28#ibcon#[27=AT05-04\r\n] 2006.173.23:33:04.28#ibcon#*before write, iclass 35, count 2 2006.173.23:33:04.28#ibcon#enter sib2, iclass 35, count 2 2006.173.23:33:04.28#ibcon#flushed, iclass 35, count 2 2006.173.23:33:04.28#ibcon#about to write, iclass 35, count 2 2006.173.23:33:04.28#ibcon#wrote, iclass 35, count 2 2006.173.23:33:04.28#ibcon#about to read 3, iclass 35, count 2 2006.173.23:33:04.31#ibcon#read 3, iclass 35, count 2 2006.173.23:33:04.31#ibcon#about to read 4, iclass 35, count 2 2006.173.23:33:04.31#ibcon#read 4, iclass 35, count 2 2006.173.23:33:04.31#ibcon#about to read 5, iclass 35, count 2 2006.173.23:33:04.31#ibcon#read 5, iclass 35, count 2 2006.173.23:33:04.31#ibcon#about to read 6, iclass 35, count 2 2006.173.23:33:04.31#ibcon#read 6, iclass 35, count 2 2006.173.23:33:04.31#ibcon#end of sib2, iclass 35, count 2 2006.173.23:33:04.31#ibcon#*after write, iclass 35, count 2 2006.173.23:33:04.31#ibcon#*before return 0, iclass 35, count 2 2006.173.23:33:04.31#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.23:33:04.31#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.23:33:04.31#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.23:33:04.31#ibcon#ireg 7 cls_cnt 0 2006.173.23:33:04.31#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.23:33:04.43#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.23:33:04.43#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.23:33:04.43#ibcon#enter wrdev, iclass 35, count 0 2006.173.23:33:04.43#ibcon#first serial, iclass 35, count 0 2006.173.23:33:04.43#ibcon#enter sib2, iclass 35, count 0 2006.173.23:33:04.43#ibcon#flushed, iclass 35, count 0 2006.173.23:33:04.43#ibcon#about to write, iclass 35, count 0 2006.173.23:33:04.43#ibcon#wrote, iclass 35, count 0 2006.173.23:33:04.43#ibcon#about to read 3, iclass 35, count 0 2006.173.23:33:04.45#ibcon#read 3, iclass 35, count 0 2006.173.23:33:04.45#ibcon#about to read 4, iclass 35, count 0 2006.173.23:33:04.45#ibcon#read 4, iclass 35, count 0 2006.173.23:33:04.45#ibcon#about to read 5, iclass 35, count 0 2006.173.23:33:04.45#ibcon#read 5, iclass 35, count 0 2006.173.23:33:04.45#ibcon#about to read 6, iclass 35, count 0 2006.173.23:33:04.45#ibcon#read 6, iclass 35, count 0 2006.173.23:33:04.45#ibcon#end of sib2, iclass 35, count 0 2006.173.23:33:04.45#ibcon#*mode == 0, iclass 35, count 0 2006.173.23:33:04.45#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.23:33:04.45#ibcon#[27=USB\r\n] 2006.173.23:33:04.45#ibcon#*before write, iclass 35, count 0 2006.173.23:33:04.45#ibcon#enter sib2, iclass 35, count 0 2006.173.23:33:04.45#ibcon#flushed, iclass 35, count 0 2006.173.23:33:04.45#ibcon#about to write, iclass 35, count 0 2006.173.23:33:04.45#ibcon#wrote, iclass 35, count 0 2006.173.23:33:04.45#ibcon#about to read 3, iclass 35, count 0 2006.173.23:33:04.48#ibcon#read 3, iclass 35, count 0 2006.173.23:33:04.48#ibcon#about to read 4, iclass 35, count 0 2006.173.23:33:04.48#ibcon#read 4, iclass 35, count 0 2006.173.23:33:04.48#ibcon#about to read 5, iclass 35, count 0 2006.173.23:33:04.48#ibcon#read 5, iclass 35, count 0 2006.173.23:33:04.48#ibcon#about to read 6, iclass 35, count 0 2006.173.23:33:04.48#ibcon#read 6, iclass 35, count 0 2006.173.23:33:04.48#ibcon#end of sib2, iclass 35, count 0 2006.173.23:33:04.48#ibcon#*after write, iclass 35, count 0 2006.173.23:33:04.48#ibcon#*before return 0, iclass 35, count 0 2006.173.23:33:04.48#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.23:33:04.48#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.23:33:04.48#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.23:33:04.48#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.23:33:04.48$vck44/vblo=6,719.99 2006.173.23:33:04.48#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.23:33:04.48#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.23:33:04.48#ibcon#ireg 17 cls_cnt 0 2006.173.23:33:04.48#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.23:33:04.48#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.23:33:04.48#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.23:33:04.48#ibcon#enter wrdev, iclass 37, count 0 2006.173.23:33:04.48#ibcon#first serial, iclass 37, count 0 2006.173.23:33:04.48#ibcon#enter sib2, iclass 37, count 0 2006.173.23:33:04.48#ibcon#flushed, iclass 37, count 0 2006.173.23:33:04.48#ibcon#about to write, iclass 37, count 0 2006.173.23:33:04.48#ibcon#wrote, iclass 37, count 0 2006.173.23:33:04.48#ibcon#about to read 3, iclass 37, count 0 2006.173.23:33:04.50#ibcon#read 3, iclass 37, count 0 2006.173.23:33:04.50#ibcon#about to read 4, iclass 37, count 0 2006.173.23:33:04.50#ibcon#read 4, iclass 37, count 0 2006.173.23:33:04.50#ibcon#about to read 5, iclass 37, count 0 2006.173.23:33:04.50#ibcon#read 5, iclass 37, count 0 2006.173.23:33:04.50#ibcon#about to read 6, iclass 37, count 0 2006.173.23:33:04.50#ibcon#read 6, iclass 37, count 0 2006.173.23:33:04.50#ibcon#end of sib2, iclass 37, count 0 2006.173.23:33:04.50#ibcon#*mode == 0, iclass 37, count 0 2006.173.23:33:04.50#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.23:33:04.50#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.23:33:04.50#ibcon#*before write, iclass 37, count 0 2006.173.23:33:04.50#ibcon#enter sib2, iclass 37, count 0 2006.173.23:33:04.50#ibcon#flushed, iclass 37, count 0 2006.173.23:33:04.50#ibcon#about to write, iclass 37, count 0 2006.173.23:33:04.50#ibcon#wrote, iclass 37, count 0 2006.173.23:33:04.50#ibcon#about to read 3, iclass 37, count 0 2006.173.23:33:04.54#ibcon#read 3, iclass 37, count 0 2006.173.23:33:04.54#ibcon#about to read 4, iclass 37, count 0 2006.173.23:33:04.54#ibcon#read 4, iclass 37, count 0 2006.173.23:33:04.54#ibcon#about to read 5, iclass 37, count 0 2006.173.23:33:04.54#ibcon#read 5, iclass 37, count 0 2006.173.23:33:04.54#ibcon#about to read 6, iclass 37, count 0 2006.173.23:33:04.54#ibcon#read 6, iclass 37, count 0 2006.173.23:33:04.54#ibcon#end of sib2, iclass 37, count 0 2006.173.23:33:04.54#ibcon#*after write, iclass 37, count 0 2006.173.23:33:04.54#ibcon#*before return 0, iclass 37, count 0 2006.173.23:33:04.54#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.23:33:04.54#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.23:33:04.54#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.23:33:04.54#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.23:33:04.54$vck44/vb=6,4 2006.173.23:33:04.54#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.23:33:04.54#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.23:33:04.54#ibcon#ireg 11 cls_cnt 2 2006.173.23:33:04.54#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.23:33:04.60#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.23:33:04.60#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.23:33:04.60#ibcon#enter wrdev, iclass 39, count 2 2006.173.23:33:04.60#ibcon#first serial, iclass 39, count 2 2006.173.23:33:04.60#ibcon#enter sib2, iclass 39, count 2 2006.173.23:33:04.60#ibcon#flushed, iclass 39, count 2 2006.173.23:33:04.60#ibcon#about to write, iclass 39, count 2 2006.173.23:33:04.60#ibcon#wrote, iclass 39, count 2 2006.173.23:33:04.60#ibcon#about to read 3, iclass 39, count 2 2006.173.23:33:04.62#ibcon#read 3, iclass 39, count 2 2006.173.23:33:04.62#ibcon#about to read 4, iclass 39, count 2 2006.173.23:33:04.62#ibcon#read 4, iclass 39, count 2 2006.173.23:33:04.62#ibcon#about to read 5, iclass 39, count 2 2006.173.23:33:04.62#ibcon#read 5, iclass 39, count 2 2006.173.23:33:04.62#ibcon#about to read 6, iclass 39, count 2 2006.173.23:33:04.62#ibcon#read 6, iclass 39, count 2 2006.173.23:33:04.62#ibcon#end of sib2, iclass 39, count 2 2006.173.23:33:04.62#ibcon#*mode == 0, iclass 39, count 2 2006.173.23:33:04.62#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.23:33:04.62#ibcon#[27=AT06-04\r\n] 2006.173.23:33:04.62#ibcon#*before write, iclass 39, count 2 2006.173.23:33:04.62#ibcon#enter sib2, iclass 39, count 2 2006.173.23:33:04.62#ibcon#flushed, iclass 39, count 2 2006.173.23:33:04.62#ibcon#about to write, iclass 39, count 2 2006.173.23:33:04.62#ibcon#wrote, iclass 39, count 2 2006.173.23:33:04.62#ibcon#about to read 3, iclass 39, count 2 2006.173.23:33:04.65#ibcon#read 3, iclass 39, count 2 2006.173.23:33:04.65#ibcon#about to read 4, iclass 39, count 2 2006.173.23:33:04.65#ibcon#read 4, iclass 39, count 2 2006.173.23:33:04.65#ibcon#about to read 5, iclass 39, count 2 2006.173.23:33:04.65#ibcon#read 5, iclass 39, count 2 2006.173.23:33:04.65#ibcon#about to read 6, iclass 39, count 2 2006.173.23:33:04.65#ibcon#read 6, iclass 39, count 2 2006.173.23:33:04.65#ibcon#end of sib2, iclass 39, count 2 2006.173.23:33:04.65#ibcon#*after write, iclass 39, count 2 2006.173.23:33:04.65#ibcon#*before return 0, iclass 39, count 2 2006.173.23:33:04.65#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.23:33:04.65#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.23:33:04.65#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.23:33:04.65#ibcon#ireg 7 cls_cnt 0 2006.173.23:33:04.65#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.23:33:04.66#abcon#<5=/12 0.8 2.2 23.47 881003.2\r\n> 2006.173.23:33:04.68#abcon#{5=INTERFACE CLEAR} 2006.173.23:33:04.74#abcon#[5=S1D000X0/0*\r\n] 2006.173.23:33:04.77#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.23:33:04.77#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.23:33:04.77#ibcon#enter wrdev, iclass 39, count 0 2006.173.23:33:04.77#ibcon#first serial, iclass 39, count 0 2006.173.23:33:04.77#ibcon#enter sib2, iclass 39, count 0 2006.173.23:33:04.77#ibcon#flushed, iclass 39, count 0 2006.173.23:33:04.77#ibcon#about to write, iclass 39, count 0 2006.173.23:33:04.77#ibcon#wrote, iclass 39, count 0 2006.173.23:33:04.77#ibcon#about to read 3, iclass 39, count 0 2006.173.23:33:04.79#ibcon#read 3, iclass 39, count 0 2006.173.23:33:04.79#ibcon#about to read 4, iclass 39, count 0 2006.173.23:33:04.79#ibcon#read 4, iclass 39, count 0 2006.173.23:33:04.79#ibcon#about to read 5, iclass 39, count 0 2006.173.23:33:04.79#ibcon#read 5, iclass 39, count 0 2006.173.23:33:04.79#ibcon#about to read 6, iclass 39, count 0 2006.173.23:33:04.79#ibcon#read 6, iclass 39, count 0 2006.173.23:33:04.79#ibcon#end of sib2, iclass 39, count 0 2006.173.23:33:04.79#ibcon#*mode == 0, iclass 39, count 0 2006.173.23:33:04.79#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.23:33:04.79#ibcon#[27=USB\r\n] 2006.173.23:33:04.79#ibcon#*before write, iclass 39, count 0 2006.173.23:33:04.79#ibcon#enter sib2, iclass 39, count 0 2006.173.23:33:04.79#ibcon#flushed, iclass 39, count 0 2006.173.23:33:04.79#ibcon#about to write, iclass 39, count 0 2006.173.23:33:04.79#ibcon#wrote, iclass 39, count 0 2006.173.23:33:04.79#ibcon#about to read 3, iclass 39, count 0 2006.173.23:33:04.82#ibcon#read 3, iclass 39, count 0 2006.173.23:33:04.82#ibcon#about to read 4, iclass 39, count 0 2006.173.23:33:04.82#ibcon#read 4, iclass 39, count 0 2006.173.23:33:04.82#ibcon#about to read 5, iclass 39, count 0 2006.173.23:33:04.82#ibcon#read 5, iclass 39, count 0 2006.173.23:33:04.82#ibcon#about to read 6, iclass 39, count 0 2006.173.23:33:04.82#ibcon#read 6, iclass 39, count 0 2006.173.23:33:04.82#ibcon#end of sib2, iclass 39, count 0 2006.173.23:33:04.82#ibcon#*after write, iclass 39, count 0 2006.173.23:33:04.82#ibcon#*before return 0, iclass 39, count 0 2006.173.23:33:04.82#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.23:33:04.82#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.23:33:04.82#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.23:33:04.82#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.23:33:04.82$vck44/vblo=7,734.99 2006.173.23:33:04.82#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.23:33:04.82#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.23:33:04.82#ibcon#ireg 17 cls_cnt 0 2006.173.23:33:04.82#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.23:33:04.82#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.23:33:04.82#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.23:33:04.82#ibcon#enter wrdev, iclass 7, count 0 2006.173.23:33:04.82#ibcon#first serial, iclass 7, count 0 2006.173.23:33:04.82#ibcon#enter sib2, iclass 7, count 0 2006.173.23:33:04.82#ibcon#flushed, iclass 7, count 0 2006.173.23:33:04.82#ibcon#about to write, iclass 7, count 0 2006.173.23:33:04.82#ibcon#wrote, iclass 7, count 0 2006.173.23:33:04.82#ibcon#about to read 3, iclass 7, count 0 2006.173.23:33:04.84#ibcon#read 3, iclass 7, count 0 2006.173.23:33:04.84#ibcon#about to read 4, iclass 7, count 0 2006.173.23:33:04.84#ibcon#read 4, iclass 7, count 0 2006.173.23:33:04.84#ibcon#about to read 5, iclass 7, count 0 2006.173.23:33:04.84#ibcon#read 5, iclass 7, count 0 2006.173.23:33:04.84#ibcon#about to read 6, iclass 7, count 0 2006.173.23:33:04.84#ibcon#read 6, iclass 7, count 0 2006.173.23:33:04.84#ibcon#end of sib2, iclass 7, count 0 2006.173.23:33:04.84#ibcon#*mode == 0, iclass 7, count 0 2006.173.23:33:04.84#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.23:33:04.84#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.23:33:04.84#ibcon#*before write, iclass 7, count 0 2006.173.23:33:04.84#ibcon#enter sib2, iclass 7, count 0 2006.173.23:33:04.84#ibcon#flushed, iclass 7, count 0 2006.173.23:33:04.84#ibcon#about to write, iclass 7, count 0 2006.173.23:33:04.84#ibcon#wrote, iclass 7, count 0 2006.173.23:33:04.84#ibcon#about to read 3, iclass 7, count 0 2006.173.23:33:04.88#ibcon#read 3, iclass 7, count 0 2006.173.23:33:04.88#ibcon#about to read 4, iclass 7, count 0 2006.173.23:33:04.88#ibcon#read 4, iclass 7, count 0 2006.173.23:33:04.88#ibcon#about to read 5, iclass 7, count 0 2006.173.23:33:04.88#ibcon#read 5, iclass 7, count 0 2006.173.23:33:04.88#ibcon#about to read 6, iclass 7, count 0 2006.173.23:33:04.88#ibcon#read 6, iclass 7, count 0 2006.173.23:33:04.88#ibcon#end of sib2, iclass 7, count 0 2006.173.23:33:04.88#ibcon#*after write, iclass 7, count 0 2006.173.23:33:04.88#ibcon#*before return 0, iclass 7, count 0 2006.173.23:33:04.88#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.23:33:04.88#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.23:33:04.88#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.23:33:04.88#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.23:33:04.88$vck44/vb=7,4 2006.173.23:33:04.88#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.23:33:04.88#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.23:33:04.88#ibcon#ireg 11 cls_cnt 2 2006.173.23:33:04.88#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.23:33:04.94#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.23:33:04.94#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.23:33:04.94#ibcon#enter wrdev, iclass 11, count 2 2006.173.23:33:04.94#ibcon#first serial, iclass 11, count 2 2006.173.23:33:04.94#ibcon#enter sib2, iclass 11, count 2 2006.173.23:33:04.94#ibcon#flushed, iclass 11, count 2 2006.173.23:33:04.94#ibcon#about to write, iclass 11, count 2 2006.173.23:33:04.94#ibcon#wrote, iclass 11, count 2 2006.173.23:33:04.94#ibcon#about to read 3, iclass 11, count 2 2006.173.23:33:04.96#ibcon#read 3, iclass 11, count 2 2006.173.23:33:04.96#ibcon#about to read 4, iclass 11, count 2 2006.173.23:33:04.96#ibcon#read 4, iclass 11, count 2 2006.173.23:33:04.96#ibcon#about to read 5, iclass 11, count 2 2006.173.23:33:04.96#ibcon#read 5, iclass 11, count 2 2006.173.23:33:04.96#ibcon#about to read 6, iclass 11, count 2 2006.173.23:33:04.96#ibcon#read 6, iclass 11, count 2 2006.173.23:33:04.96#ibcon#end of sib2, iclass 11, count 2 2006.173.23:33:04.96#ibcon#*mode == 0, iclass 11, count 2 2006.173.23:33:04.96#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.23:33:04.96#ibcon#[27=AT07-04\r\n] 2006.173.23:33:04.96#ibcon#*before write, iclass 11, count 2 2006.173.23:33:04.96#ibcon#enter sib2, iclass 11, count 2 2006.173.23:33:04.96#ibcon#flushed, iclass 11, count 2 2006.173.23:33:04.96#ibcon#about to write, iclass 11, count 2 2006.173.23:33:04.96#ibcon#wrote, iclass 11, count 2 2006.173.23:33:04.96#ibcon#about to read 3, iclass 11, count 2 2006.173.23:33:04.99#ibcon#read 3, iclass 11, count 2 2006.173.23:33:04.99#ibcon#about to read 4, iclass 11, count 2 2006.173.23:33:04.99#ibcon#read 4, iclass 11, count 2 2006.173.23:33:04.99#ibcon#about to read 5, iclass 11, count 2 2006.173.23:33:04.99#ibcon#read 5, iclass 11, count 2 2006.173.23:33:04.99#ibcon#about to read 6, iclass 11, count 2 2006.173.23:33:04.99#ibcon#read 6, iclass 11, count 2 2006.173.23:33:04.99#ibcon#end of sib2, iclass 11, count 2 2006.173.23:33:04.99#ibcon#*after write, iclass 11, count 2 2006.173.23:33:04.99#ibcon#*before return 0, iclass 11, count 2 2006.173.23:33:04.99#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.23:33:04.99#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.23:33:04.99#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.23:33:04.99#ibcon#ireg 7 cls_cnt 0 2006.173.23:33:04.99#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.23:33:05.11#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.23:33:05.11#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.23:33:05.11#ibcon#enter wrdev, iclass 11, count 0 2006.173.23:33:05.11#ibcon#first serial, iclass 11, count 0 2006.173.23:33:05.11#ibcon#enter sib2, iclass 11, count 0 2006.173.23:33:05.11#ibcon#flushed, iclass 11, count 0 2006.173.23:33:05.11#ibcon#about to write, iclass 11, count 0 2006.173.23:33:05.11#ibcon#wrote, iclass 11, count 0 2006.173.23:33:05.11#ibcon#about to read 3, iclass 11, count 0 2006.173.23:33:05.13#ibcon#read 3, iclass 11, count 0 2006.173.23:33:05.13#ibcon#about to read 4, iclass 11, count 0 2006.173.23:33:05.13#ibcon#read 4, iclass 11, count 0 2006.173.23:33:05.13#ibcon#about to read 5, iclass 11, count 0 2006.173.23:33:05.13#ibcon#read 5, iclass 11, count 0 2006.173.23:33:05.13#ibcon#about to read 6, iclass 11, count 0 2006.173.23:33:05.13#ibcon#read 6, iclass 11, count 0 2006.173.23:33:05.13#ibcon#end of sib2, iclass 11, count 0 2006.173.23:33:05.13#ibcon#*mode == 0, iclass 11, count 0 2006.173.23:33:05.13#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.23:33:05.13#ibcon#[27=USB\r\n] 2006.173.23:33:05.13#ibcon#*before write, iclass 11, count 0 2006.173.23:33:05.13#ibcon#enter sib2, iclass 11, count 0 2006.173.23:33:05.13#ibcon#flushed, iclass 11, count 0 2006.173.23:33:05.13#ibcon#about to write, iclass 11, count 0 2006.173.23:33:05.13#ibcon#wrote, iclass 11, count 0 2006.173.23:33:05.13#ibcon#about to read 3, iclass 11, count 0 2006.173.23:33:05.16#ibcon#read 3, iclass 11, count 0 2006.173.23:33:05.16#ibcon#about to read 4, iclass 11, count 0 2006.173.23:33:05.16#ibcon#read 4, iclass 11, count 0 2006.173.23:33:05.16#ibcon#about to read 5, iclass 11, count 0 2006.173.23:33:05.16#ibcon#read 5, iclass 11, count 0 2006.173.23:33:05.16#ibcon#about to read 6, iclass 11, count 0 2006.173.23:33:05.16#ibcon#read 6, iclass 11, count 0 2006.173.23:33:05.16#ibcon#end of sib2, iclass 11, count 0 2006.173.23:33:05.16#ibcon#*after write, iclass 11, count 0 2006.173.23:33:05.16#ibcon#*before return 0, iclass 11, count 0 2006.173.23:33:05.16#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.23:33:05.16#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.23:33:05.16#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.23:33:05.16#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.23:33:05.16$vck44/vblo=8,744.99 2006.173.23:33:05.16#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.23:33:05.16#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.23:33:05.16#ibcon#ireg 17 cls_cnt 0 2006.173.23:33:05.16#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.23:33:05.16#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.23:33:05.16#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.23:33:05.16#ibcon#enter wrdev, iclass 13, count 0 2006.173.23:33:05.16#ibcon#first serial, iclass 13, count 0 2006.173.23:33:05.16#ibcon#enter sib2, iclass 13, count 0 2006.173.23:33:05.16#ibcon#flushed, iclass 13, count 0 2006.173.23:33:05.16#ibcon#about to write, iclass 13, count 0 2006.173.23:33:05.16#ibcon#wrote, iclass 13, count 0 2006.173.23:33:05.16#ibcon#about to read 3, iclass 13, count 0 2006.173.23:33:05.18#ibcon#read 3, iclass 13, count 0 2006.173.23:33:05.18#ibcon#about to read 4, iclass 13, count 0 2006.173.23:33:05.18#ibcon#read 4, iclass 13, count 0 2006.173.23:33:05.18#ibcon#about to read 5, iclass 13, count 0 2006.173.23:33:05.18#ibcon#read 5, iclass 13, count 0 2006.173.23:33:05.18#ibcon#about to read 6, iclass 13, count 0 2006.173.23:33:05.18#ibcon#read 6, iclass 13, count 0 2006.173.23:33:05.18#ibcon#end of sib2, iclass 13, count 0 2006.173.23:33:05.18#ibcon#*mode == 0, iclass 13, count 0 2006.173.23:33:05.18#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.23:33:05.18#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.23:33:05.18#ibcon#*before write, iclass 13, count 0 2006.173.23:33:05.18#ibcon#enter sib2, iclass 13, count 0 2006.173.23:33:05.18#ibcon#flushed, iclass 13, count 0 2006.173.23:33:05.18#ibcon#about to write, iclass 13, count 0 2006.173.23:33:05.18#ibcon#wrote, iclass 13, count 0 2006.173.23:33:05.18#ibcon#about to read 3, iclass 13, count 0 2006.173.23:33:05.22#ibcon#read 3, iclass 13, count 0 2006.173.23:33:05.22#ibcon#about to read 4, iclass 13, count 0 2006.173.23:33:05.22#ibcon#read 4, iclass 13, count 0 2006.173.23:33:05.22#ibcon#about to read 5, iclass 13, count 0 2006.173.23:33:05.22#ibcon#read 5, iclass 13, count 0 2006.173.23:33:05.22#ibcon#about to read 6, iclass 13, count 0 2006.173.23:33:05.22#ibcon#read 6, iclass 13, count 0 2006.173.23:33:05.22#ibcon#end of sib2, iclass 13, count 0 2006.173.23:33:05.22#ibcon#*after write, iclass 13, count 0 2006.173.23:33:05.22#ibcon#*before return 0, iclass 13, count 0 2006.173.23:33:05.22#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.23:33:05.22#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.23:33:05.22#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.23:33:05.22#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.23:33:05.22$vck44/vb=8,4 2006.173.23:33:05.22#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.23:33:05.22#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.23:33:05.22#ibcon#ireg 11 cls_cnt 2 2006.173.23:33:05.22#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.23:33:05.28#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.23:33:05.28#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.23:33:05.28#ibcon#enter wrdev, iclass 15, count 2 2006.173.23:33:05.28#ibcon#first serial, iclass 15, count 2 2006.173.23:33:05.28#ibcon#enter sib2, iclass 15, count 2 2006.173.23:33:05.28#ibcon#flushed, iclass 15, count 2 2006.173.23:33:05.28#ibcon#about to write, iclass 15, count 2 2006.173.23:33:05.28#ibcon#wrote, iclass 15, count 2 2006.173.23:33:05.28#ibcon#about to read 3, iclass 15, count 2 2006.173.23:33:05.30#ibcon#read 3, iclass 15, count 2 2006.173.23:33:05.30#ibcon#about to read 4, iclass 15, count 2 2006.173.23:33:05.30#ibcon#read 4, iclass 15, count 2 2006.173.23:33:05.30#ibcon#about to read 5, iclass 15, count 2 2006.173.23:33:05.30#ibcon#read 5, iclass 15, count 2 2006.173.23:33:05.30#ibcon#about to read 6, iclass 15, count 2 2006.173.23:33:05.30#ibcon#read 6, iclass 15, count 2 2006.173.23:33:05.30#ibcon#end of sib2, iclass 15, count 2 2006.173.23:33:05.30#ibcon#*mode == 0, iclass 15, count 2 2006.173.23:33:05.30#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.23:33:05.30#ibcon#[27=AT08-04\r\n] 2006.173.23:33:05.30#ibcon#*before write, iclass 15, count 2 2006.173.23:33:05.30#ibcon#enter sib2, iclass 15, count 2 2006.173.23:33:05.30#ibcon#flushed, iclass 15, count 2 2006.173.23:33:05.30#ibcon#about to write, iclass 15, count 2 2006.173.23:33:05.30#ibcon#wrote, iclass 15, count 2 2006.173.23:33:05.30#ibcon#about to read 3, iclass 15, count 2 2006.173.23:33:05.33#ibcon#read 3, iclass 15, count 2 2006.173.23:33:05.33#ibcon#about to read 4, iclass 15, count 2 2006.173.23:33:05.33#ibcon#read 4, iclass 15, count 2 2006.173.23:33:05.33#ibcon#about to read 5, iclass 15, count 2 2006.173.23:33:05.33#ibcon#read 5, iclass 15, count 2 2006.173.23:33:05.33#ibcon#about to read 6, iclass 15, count 2 2006.173.23:33:05.33#ibcon#read 6, iclass 15, count 2 2006.173.23:33:05.33#ibcon#end of sib2, iclass 15, count 2 2006.173.23:33:05.33#ibcon#*after write, iclass 15, count 2 2006.173.23:33:05.33#ibcon#*before return 0, iclass 15, count 2 2006.173.23:33:05.33#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.23:33:05.33#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.23:33:05.33#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.23:33:05.33#ibcon#ireg 7 cls_cnt 0 2006.173.23:33:05.33#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.23:33:05.45#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.23:33:05.45#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.23:33:05.45#ibcon#enter wrdev, iclass 15, count 0 2006.173.23:33:05.45#ibcon#first serial, iclass 15, count 0 2006.173.23:33:05.45#ibcon#enter sib2, iclass 15, count 0 2006.173.23:33:05.45#ibcon#flushed, iclass 15, count 0 2006.173.23:33:05.45#ibcon#about to write, iclass 15, count 0 2006.173.23:33:05.45#ibcon#wrote, iclass 15, count 0 2006.173.23:33:05.45#ibcon#about to read 3, iclass 15, count 0 2006.173.23:33:05.47#ibcon#read 3, iclass 15, count 0 2006.173.23:33:05.47#ibcon#about to read 4, iclass 15, count 0 2006.173.23:33:05.47#ibcon#read 4, iclass 15, count 0 2006.173.23:33:05.47#ibcon#about to read 5, iclass 15, count 0 2006.173.23:33:05.47#ibcon#read 5, iclass 15, count 0 2006.173.23:33:05.47#ibcon#about to read 6, iclass 15, count 0 2006.173.23:33:05.47#ibcon#read 6, iclass 15, count 0 2006.173.23:33:05.47#ibcon#end of sib2, iclass 15, count 0 2006.173.23:33:05.47#ibcon#*mode == 0, iclass 15, count 0 2006.173.23:33:05.47#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.23:33:05.47#ibcon#[27=USB\r\n] 2006.173.23:33:05.47#ibcon#*before write, iclass 15, count 0 2006.173.23:33:05.47#ibcon#enter sib2, iclass 15, count 0 2006.173.23:33:05.47#ibcon#flushed, iclass 15, count 0 2006.173.23:33:05.47#ibcon#about to write, iclass 15, count 0 2006.173.23:33:05.47#ibcon#wrote, iclass 15, count 0 2006.173.23:33:05.47#ibcon#about to read 3, iclass 15, count 0 2006.173.23:33:05.50#ibcon#read 3, iclass 15, count 0 2006.173.23:33:05.50#ibcon#about to read 4, iclass 15, count 0 2006.173.23:33:05.50#ibcon#read 4, iclass 15, count 0 2006.173.23:33:05.50#ibcon#about to read 5, iclass 15, count 0 2006.173.23:33:05.50#ibcon#read 5, iclass 15, count 0 2006.173.23:33:05.50#ibcon#about to read 6, iclass 15, count 0 2006.173.23:33:05.50#ibcon#read 6, iclass 15, count 0 2006.173.23:33:05.50#ibcon#end of sib2, iclass 15, count 0 2006.173.23:33:05.50#ibcon#*after write, iclass 15, count 0 2006.173.23:33:05.50#ibcon#*before return 0, iclass 15, count 0 2006.173.23:33:05.50#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.23:33:05.50#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.23:33:05.50#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.23:33:05.50#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.23:33:05.50$vck44/vabw=wide 2006.173.23:33:05.50#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.23:33:05.50#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.23:33:05.50#ibcon#ireg 8 cls_cnt 0 2006.173.23:33:05.50#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.23:33:05.50#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.23:33:05.50#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.23:33:05.50#ibcon#enter wrdev, iclass 17, count 0 2006.173.23:33:05.50#ibcon#first serial, iclass 17, count 0 2006.173.23:33:05.50#ibcon#enter sib2, iclass 17, count 0 2006.173.23:33:05.50#ibcon#flushed, iclass 17, count 0 2006.173.23:33:05.50#ibcon#about to write, iclass 17, count 0 2006.173.23:33:05.50#ibcon#wrote, iclass 17, count 0 2006.173.23:33:05.50#ibcon#about to read 3, iclass 17, count 0 2006.173.23:33:05.52#ibcon#read 3, iclass 17, count 0 2006.173.23:33:05.52#ibcon#about to read 4, iclass 17, count 0 2006.173.23:33:05.52#ibcon#read 4, iclass 17, count 0 2006.173.23:33:05.52#ibcon#about to read 5, iclass 17, count 0 2006.173.23:33:05.52#ibcon#read 5, iclass 17, count 0 2006.173.23:33:05.52#ibcon#about to read 6, iclass 17, count 0 2006.173.23:33:05.52#ibcon#read 6, iclass 17, count 0 2006.173.23:33:05.52#ibcon#end of sib2, iclass 17, count 0 2006.173.23:33:05.52#ibcon#*mode == 0, iclass 17, count 0 2006.173.23:33:05.52#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.23:33:05.52#ibcon#[25=BW32\r\n] 2006.173.23:33:05.52#ibcon#*before write, iclass 17, count 0 2006.173.23:33:05.52#ibcon#enter sib2, iclass 17, count 0 2006.173.23:33:05.52#ibcon#flushed, iclass 17, count 0 2006.173.23:33:05.52#ibcon#about to write, iclass 17, count 0 2006.173.23:33:05.52#ibcon#wrote, iclass 17, count 0 2006.173.23:33:05.52#ibcon#about to read 3, iclass 17, count 0 2006.173.23:33:05.55#ibcon#read 3, iclass 17, count 0 2006.173.23:33:05.55#ibcon#about to read 4, iclass 17, count 0 2006.173.23:33:05.55#ibcon#read 4, iclass 17, count 0 2006.173.23:33:05.55#ibcon#about to read 5, iclass 17, count 0 2006.173.23:33:05.55#ibcon#read 5, iclass 17, count 0 2006.173.23:33:05.55#ibcon#about to read 6, iclass 17, count 0 2006.173.23:33:05.55#ibcon#read 6, iclass 17, count 0 2006.173.23:33:05.55#ibcon#end of sib2, iclass 17, count 0 2006.173.23:33:05.55#ibcon#*after write, iclass 17, count 0 2006.173.23:33:05.55#ibcon#*before return 0, iclass 17, count 0 2006.173.23:33:05.55#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.23:33:05.55#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.23:33:05.55#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.23:33:05.55#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.23:33:05.55$vck44/vbbw=wide 2006.173.23:33:05.55#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.23:33:05.55#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.23:33:05.55#ibcon#ireg 8 cls_cnt 0 2006.173.23:33:05.55#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.23:33:05.62#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.23:33:05.62#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.23:33:05.62#ibcon#enter wrdev, iclass 19, count 0 2006.173.23:33:05.62#ibcon#first serial, iclass 19, count 0 2006.173.23:33:05.62#ibcon#enter sib2, iclass 19, count 0 2006.173.23:33:05.62#ibcon#flushed, iclass 19, count 0 2006.173.23:33:05.62#ibcon#about to write, iclass 19, count 0 2006.173.23:33:05.62#ibcon#wrote, iclass 19, count 0 2006.173.23:33:05.62#ibcon#about to read 3, iclass 19, count 0 2006.173.23:33:05.64#ibcon#read 3, iclass 19, count 0 2006.173.23:33:05.64#ibcon#about to read 4, iclass 19, count 0 2006.173.23:33:05.64#ibcon#read 4, iclass 19, count 0 2006.173.23:33:05.64#ibcon#about to read 5, iclass 19, count 0 2006.173.23:33:05.64#ibcon#read 5, iclass 19, count 0 2006.173.23:33:05.64#ibcon#about to read 6, iclass 19, count 0 2006.173.23:33:05.64#ibcon#read 6, iclass 19, count 0 2006.173.23:33:05.64#ibcon#end of sib2, iclass 19, count 0 2006.173.23:33:05.64#ibcon#*mode == 0, iclass 19, count 0 2006.173.23:33:05.64#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.23:33:05.64#ibcon#[27=BW32\r\n] 2006.173.23:33:05.64#ibcon#*before write, iclass 19, count 0 2006.173.23:33:05.64#ibcon#enter sib2, iclass 19, count 0 2006.173.23:33:05.64#ibcon#flushed, iclass 19, count 0 2006.173.23:33:05.64#ibcon#about to write, iclass 19, count 0 2006.173.23:33:05.64#ibcon#wrote, iclass 19, count 0 2006.173.23:33:05.64#ibcon#about to read 3, iclass 19, count 0 2006.173.23:33:05.67#ibcon#read 3, iclass 19, count 0 2006.173.23:33:05.67#ibcon#about to read 4, iclass 19, count 0 2006.173.23:33:05.67#ibcon#read 4, iclass 19, count 0 2006.173.23:33:05.67#ibcon#about to read 5, iclass 19, count 0 2006.173.23:33:05.67#ibcon#read 5, iclass 19, count 0 2006.173.23:33:05.67#ibcon#about to read 6, iclass 19, count 0 2006.173.23:33:05.67#ibcon#read 6, iclass 19, count 0 2006.173.23:33:05.67#ibcon#end of sib2, iclass 19, count 0 2006.173.23:33:05.67#ibcon#*after write, iclass 19, count 0 2006.173.23:33:05.67#ibcon#*before return 0, iclass 19, count 0 2006.173.23:33:05.67#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.23:33:05.67#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.23:33:05.67#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.23:33:05.67#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.23:33:05.67$setupk4/ifdk4 2006.173.23:33:05.67$ifdk4/lo= 2006.173.23:33:05.67$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.23:33:05.67$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.23:33:05.67$ifdk4/patch= 2006.173.23:33:05.67$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.23:33:05.67$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.23:33:05.67$setupk4/!*+20s 2006.173.23:33:12.13#trakl#Source acquired 2006.173.23:33:13.13#flagr#flagr/antenna,acquired 2006.173.23:33:14.83#abcon#<5=/12 0.8 2.1 23.47 881003.2\r\n> 2006.173.23:33:14.85#abcon#{5=INTERFACE CLEAR} 2006.173.23:33:14.91#abcon#[5=S1D000X0/0*\r\n] 2006.173.23:33:20.17$setupk4/"tpicd 2006.173.23:33:20.17$setupk4/echo=off 2006.173.23:33:20.17$setupk4/xlog=off 2006.173.23:33:20.17:!2006.173.23:33:45 2006.173.23:33:45.00:preob 2006.173.23:33:45.13/onsource/TRACKING 2006.173.23:33:45.13:!2006.173.23:33:55 2006.173.23:33:55.00:"tape 2006.173.23:33:55.00:"st=record 2006.173.23:33:55.00:data_valid=on 2006.173.23:33:55.00:midob 2006.173.23:33:55.13/onsource/TRACKING 2006.173.23:33:55.13/wx/23.48,1003.2,88 2006.173.23:33:55.20/cable/+6.5110E-03 2006.173.23:33:56.29/va/01,07,usb,yes,35,38 2006.173.23:33:56.29/va/02,06,usb,yes,35,36 2006.173.23:33:56.29/va/03,05,usb,yes,45,47 2006.173.23:33:56.29/va/04,06,usb,yes,36,38 2006.173.23:33:56.29/va/05,04,usb,yes,28,29 2006.173.23:33:56.29/va/06,03,usb,yes,39,39 2006.173.23:33:56.29/va/07,04,usb,yes,32,33 2006.173.23:33:56.29/va/08,04,usb,yes,27,33 2006.173.23:33:56.52/valo/01,524.99,yes,locked 2006.173.23:33:56.52/valo/02,534.99,yes,locked 2006.173.23:33:56.52/valo/03,564.99,yes,locked 2006.173.23:33:56.52/valo/04,624.99,yes,locked 2006.173.23:33:56.52/valo/05,734.99,yes,locked 2006.173.23:33:56.52/valo/06,814.99,yes,locked 2006.173.23:33:56.52/valo/07,864.99,yes,locked 2006.173.23:33:56.52/valo/08,884.99,yes,locked 2006.173.23:33:57.61/vb/01,04,usb,yes,29,27 2006.173.23:33:57.61/vb/02,04,usb,yes,32,32 2006.173.23:33:57.61/vb/03,04,usb,yes,29,32 2006.173.23:33:57.61/vb/04,04,usb,yes,33,32 2006.173.23:33:57.61/vb/05,04,usb,yes,26,28 2006.173.23:33:57.61/vb/06,04,usb,yes,30,26 2006.173.23:33:57.61/vb/07,04,usb,yes,30,30 2006.173.23:33:57.61/vb/08,04,usb,yes,27,31 2006.173.23:33:57.84/vblo/01,629.99,yes,locked 2006.173.23:33:57.84/vblo/02,634.99,yes,locked 2006.173.23:33:57.84/vblo/03,649.99,yes,locked 2006.173.23:33:57.84/vblo/04,679.99,yes,locked 2006.173.23:33:57.84/vblo/05,709.99,yes,locked 2006.173.23:33:57.84/vblo/06,719.99,yes,locked 2006.173.23:33:57.84/vblo/07,734.99,yes,locked 2006.173.23:33:57.84/vblo/08,744.99,yes,locked 2006.173.23:33:57.99/vabw/8 2006.173.23:33:58.14/vbbw/8 2006.173.23:33:58.23/xfe/off,on,15.0 2006.173.23:33:58.62/ifatt/23,28,28,28 2006.173.23:33:59.08/fmout-gps/S +3.94E-07 2006.173.23:33:59.12:!2006.173.23:36:15 2006.173.23:36:15.00:data_valid=off 2006.173.23:36:15.00:"et 2006.173.23:36:15.00:!+3s 2006.173.23:36:18.02:"tape 2006.173.23:36:18.02:postob 2006.173.23:36:18.10/cable/+6.5115E-03 2006.173.23:36:18.10/wx/23.49,1003.2,87 2006.173.23:36:19.08/fmout-gps/S +3.93E-07 2006.173.23:36:19.08:scan_name=173-2343,jd0606,110 2006.173.23:36:19.08:source=2136+141,213901.31,142336.0,2000.0,ccw 2006.173.23:36:20.14#flagr#flagr/antenna,new-source 2006.173.23:36:20.14:checkk5 2006.173.23:36:20.55/chk_autoobs//k5ts1/ autoobs is running! 2006.173.23:36:20.95/chk_autoobs//k5ts2/ autoobs is running! 2006.173.23:36:21.35/chk_autoobs//k5ts3/ autoobs is running! 2006.173.23:36:21.74/chk_autoobs//k5ts4/ autoobs is running! 2006.173.23:36:22.13/chk_obsdata//k5ts1/T1732333??a.dat file size is correct (nominal:560MB, actual:556MB). 2006.173.23:36:22.53/chk_obsdata//k5ts2/T1732333??b.dat file size is correct (nominal:560MB, actual:556MB). 2006.173.23:36:22.92/chk_obsdata//k5ts3/T1732333??c.dat file size is correct (nominal:560MB, actual:556MB). 2006.173.23:36:23.35/chk_obsdata//k5ts4/T1732333??d.dat file size is correct (nominal:560MB, actual:556MB). 2006.173.23:36:24.07/k5log//k5ts1_log_newline 2006.173.23:36:24.78/k5log//k5ts2_log_newline 2006.173.23:36:25.49/k5log//k5ts3_log_newline 2006.173.23:36:26.21/k5log//k5ts4_log_newline 2006.173.23:36:26.23/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.23:36:26.23:setupk4=1 2006.173.23:36:26.23$setupk4/echo=on 2006.173.23:36:26.23$setupk4/pcalon 2006.173.23:36:26.23$pcalon/"no phase cal control is implemented here 2006.173.23:36:26.23$setupk4/"tpicd=stop 2006.173.23:36:26.23$setupk4/"rec=synch_on 2006.173.23:36:26.23$setupk4/"rec_mode=128 2006.173.23:36:26.23$setupk4/!* 2006.173.23:36:26.23$setupk4/recpk4 2006.173.23:36:26.23$recpk4/recpatch= 2006.173.23:36:26.24$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.23:36:26.24$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.23:36:26.24$setupk4/vck44 2006.173.23:36:26.24$vck44/valo=1,524.99 2006.173.23:36:26.24#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.23:36:26.24#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.23:36:26.24#ibcon#ireg 17 cls_cnt 0 2006.173.23:36:26.24#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.23:36:26.24#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.23:36:26.24#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.23:36:26.24#ibcon#enter wrdev, iclass 28, count 0 2006.173.23:36:26.24#ibcon#first serial, iclass 28, count 0 2006.173.23:36:26.24#ibcon#enter sib2, iclass 28, count 0 2006.173.23:36:26.24#ibcon#flushed, iclass 28, count 0 2006.173.23:36:26.24#ibcon#about to write, iclass 28, count 0 2006.173.23:36:26.24#ibcon#wrote, iclass 28, count 0 2006.173.23:36:26.24#ibcon#about to read 3, iclass 28, count 0 2006.173.23:36:26.26#ibcon#read 3, iclass 28, count 0 2006.173.23:36:26.26#ibcon#about to read 4, iclass 28, count 0 2006.173.23:36:26.26#ibcon#read 4, iclass 28, count 0 2006.173.23:36:26.26#ibcon#about to read 5, iclass 28, count 0 2006.173.23:36:26.26#ibcon#read 5, iclass 28, count 0 2006.173.23:36:26.26#ibcon#about to read 6, iclass 28, count 0 2006.173.23:36:26.26#ibcon#read 6, iclass 28, count 0 2006.173.23:36:26.26#ibcon#end of sib2, iclass 28, count 0 2006.173.23:36:26.26#ibcon#*mode == 0, iclass 28, count 0 2006.173.23:36:26.26#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.23:36:26.26#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.23:36:26.26#ibcon#*before write, iclass 28, count 0 2006.173.23:36:26.26#ibcon#enter sib2, iclass 28, count 0 2006.173.23:36:26.26#ibcon#flushed, iclass 28, count 0 2006.173.23:36:26.26#ibcon#about to write, iclass 28, count 0 2006.173.23:36:26.26#ibcon#wrote, iclass 28, count 0 2006.173.23:36:26.26#ibcon#about to read 3, iclass 28, count 0 2006.173.23:36:26.31#ibcon#read 3, iclass 28, count 0 2006.173.23:36:26.31#ibcon#about to read 4, iclass 28, count 0 2006.173.23:36:26.31#ibcon#read 4, iclass 28, count 0 2006.173.23:36:26.31#ibcon#about to read 5, iclass 28, count 0 2006.173.23:36:26.31#ibcon#read 5, iclass 28, count 0 2006.173.23:36:26.31#ibcon#about to read 6, iclass 28, count 0 2006.173.23:36:26.31#ibcon#read 6, iclass 28, count 0 2006.173.23:36:26.31#ibcon#end of sib2, iclass 28, count 0 2006.173.23:36:26.31#ibcon#*after write, iclass 28, count 0 2006.173.23:36:26.31#ibcon#*before return 0, iclass 28, count 0 2006.173.23:36:26.31#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.23:36:26.31#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.23:36:26.31#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.23:36:26.31#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.23:36:26.31$vck44/va=1,7 2006.173.23:36:26.31#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.23:36:26.31#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.23:36:26.31#ibcon#ireg 11 cls_cnt 2 2006.173.23:36:26.31#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.23:36:26.31#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.23:36:26.31#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.23:36:26.31#ibcon#enter wrdev, iclass 30, count 2 2006.173.23:36:26.31#ibcon#first serial, iclass 30, count 2 2006.173.23:36:26.31#ibcon#enter sib2, iclass 30, count 2 2006.173.23:36:26.31#ibcon#flushed, iclass 30, count 2 2006.173.23:36:26.31#ibcon#about to write, iclass 30, count 2 2006.173.23:36:26.31#ibcon#wrote, iclass 30, count 2 2006.173.23:36:26.31#ibcon#about to read 3, iclass 30, count 2 2006.173.23:36:26.33#ibcon#read 3, iclass 30, count 2 2006.173.23:36:26.33#ibcon#about to read 4, iclass 30, count 2 2006.173.23:36:26.33#ibcon#read 4, iclass 30, count 2 2006.173.23:36:26.33#ibcon#about to read 5, iclass 30, count 2 2006.173.23:36:26.33#ibcon#read 5, iclass 30, count 2 2006.173.23:36:26.33#ibcon#about to read 6, iclass 30, count 2 2006.173.23:36:26.33#ibcon#read 6, iclass 30, count 2 2006.173.23:36:26.33#ibcon#end of sib2, iclass 30, count 2 2006.173.23:36:26.33#ibcon#*mode == 0, iclass 30, count 2 2006.173.23:36:26.33#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.23:36:26.33#ibcon#[25=AT01-07\r\n] 2006.173.23:36:26.33#ibcon#*before write, iclass 30, count 2 2006.173.23:36:26.33#ibcon#enter sib2, iclass 30, count 2 2006.173.23:36:26.33#ibcon#flushed, iclass 30, count 2 2006.173.23:36:26.33#ibcon#about to write, iclass 30, count 2 2006.173.23:36:26.33#ibcon#wrote, iclass 30, count 2 2006.173.23:36:26.33#ibcon#about to read 3, iclass 30, count 2 2006.173.23:36:26.36#ibcon#read 3, iclass 30, count 2 2006.173.23:36:26.36#ibcon#about to read 4, iclass 30, count 2 2006.173.23:36:26.36#ibcon#read 4, iclass 30, count 2 2006.173.23:36:26.36#ibcon#about to read 5, iclass 30, count 2 2006.173.23:36:26.36#ibcon#read 5, iclass 30, count 2 2006.173.23:36:26.36#ibcon#about to read 6, iclass 30, count 2 2006.173.23:36:26.36#ibcon#read 6, iclass 30, count 2 2006.173.23:36:26.36#ibcon#end of sib2, iclass 30, count 2 2006.173.23:36:26.36#ibcon#*after write, iclass 30, count 2 2006.173.23:36:26.36#ibcon#*before return 0, iclass 30, count 2 2006.173.23:36:26.36#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.23:36:26.36#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.23:36:26.36#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.23:36:26.36#ibcon#ireg 7 cls_cnt 0 2006.173.23:36:26.36#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.23:36:26.48#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.23:36:26.48#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.23:36:26.48#ibcon#enter wrdev, iclass 30, count 0 2006.173.23:36:26.48#ibcon#first serial, iclass 30, count 0 2006.173.23:36:26.48#ibcon#enter sib2, iclass 30, count 0 2006.173.23:36:26.48#ibcon#flushed, iclass 30, count 0 2006.173.23:36:26.48#ibcon#about to write, iclass 30, count 0 2006.173.23:36:26.48#ibcon#wrote, iclass 30, count 0 2006.173.23:36:26.48#ibcon#about to read 3, iclass 30, count 0 2006.173.23:36:26.50#ibcon#read 3, iclass 30, count 0 2006.173.23:36:26.50#ibcon#about to read 4, iclass 30, count 0 2006.173.23:36:26.50#ibcon#read 4, iclass 30, count 0 2006.173.23:36:26.50#ibcon#about to read 5, iclass 30, count 0 2006.173.23:36:26.50#ibcon#read 5, iclass 30, count 0 2006.173.23:36:26.50#ibcon#about to read 6, iclass 30, count 0 2006.173.23:36:26.50#ibcon#read 6, iclass 30, count 0 2006.173.23:36:26.50#ibcon#end of sib2, iclass 30, count 0 2006.173.23:36:26.50#ibcon#*mode == 0, iclass 30, count 0 2006.173.23:36:26.50#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.23:36:26.50#ibcon#[25=USB\r\n] 2006.173.23:36:26.50#ibcon#*before write, iclass 30, count 0 2006.173.23:36:26.50#ibcon#enter sib2, iclass 30, count 0 2006.173.23:36:26.50#ibcon#flushed, iclass 30, count 0 2006.173.23:36:26.50#ibcon#about to write, iclass 30, count 0 2006.173.23:36:26.50#ibcon#wrote, iclass 30, count 0 2006.173.23:36:26.50#ibcon#about to read 3, iclass 30, count 0 2006.173.23:36:26.53#ibcon#read 3, iclass 30, count 0 2006.173.23:36:26.53#ibcon#about to read 4, iclass 30, count 0 2006.173.23:36:26.53#ibcon#read 4, iclass 30, count 0 2006.173.23:36:26.53#ibcon#about to read 5, iclass 30, count 0 2006.173.23:36:26.53#ibcon#read 5, iclass 30, count 0 2006.173.23:36:26.53#ibcon#about to read 6, iclass 30, count 0 2006.173.23:36:26.53#ibcon#read 6, iclass 30, count 0 2006.173.23:36:26.53#ibcon#end of sib2, iclass 30, count 0 2006.173.23:36:26.53#ibcon#*after write, iclass 30, count 0 2006.173.23:36:26.53#ibcon#*before return 0, iclass 30, count 0 2006.173.23:36:26.53#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.23:36:26.53#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.23:36:26.53#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.23:36:26.53#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.23:36:26.53$vck44/valo=2,534.99 2006.173.23:36:26.53#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.23:36:26.53#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.23:36:26.53#ibcon#ireg 17 cls_cnt 0 2006.173.23:36:26.53#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.23:36:26.53#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.23:36:26.53#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.23:36:26.53#ibcon#enter wrdev, iclass 32, count 0 2006.173.23:36:26.53#ibcon#first serial, iclass 32, count 0 2006.173.23:36:26.53#ibcon#enter sib2, iclass 32, count 0 2006.173.23:36:26.53#ibcon#flushed, iclass 32, count 0 2006.173.23:36:26.53#ibcon#about to write, iclass 32, count 0 2006.173.23:36:26.53#ibcon#wrote, iclass 32, count 0 2006.173.23:36:26.53#ibcon#about to read 3, iclass 32, count 0 2006.173.23:36:26.55#ibcon#read 3, iclass 32, count 0 2006.173.23:36:26.55#ibcon#about to read 4, iclass 32, count 0 2006.173.23:36:26.55#ibcon#read 4, iclass 32, count 0 2006.173.23:36:26.55#ibcon#about to read 5, iclass 32, count 0 2006.173.23:36:26.55#ibcon#read 5, iclass 32, count 0 2006.173.23:36:26.55#ibcon#about to read 6, iclass 32, count 0 2006.173.23:36:26.55#ibcon#read 6, iclass 32, count 0 2006.173.23:36:26.55#ibcon#end of sib2, iclass 32, count 0 2006.173.23:36:26.55#ibcon#*mode == 0, iclass 32, count 0 2006.173.23:36:26.55#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.23:36:26.55#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.23:36:26.55#ibcon#*before write, iclass 32, count 0 2006.173.23:36:26.55#ibcon#enter sib2, iclass 32, count 0 2006.173.23:36:26.55#ibcon#flushed, iclass 32, count 0 2006.173.23:36:26.55#ibcon#about to write, iclass 32, count 0 2006.173.23:36:26.55#ibcon#wrote, iclass 32, count 0 2006.173.23:36:26.55#ibcon#about to read 3, iclass 32, count 0 2006.173.23:36:26.59#ibcon#read 3, iclass 32, count 0 2006.173.23:36:26.59#ibcon#about to read 4, iclass 32, count 0 2006.173.23:36:26.59#ibcon#read 4, iclass 32, count 0 2006.173.23:36:26.59#ibcon#about to read 5, iclass 32, count 0 2006.173.23:36:26.59#ibcon#read 5, iclass 32, count 0 2006.173.23:36:26.59#ibcon#about to read 6, iclass 32, count 0 2006.173.23:36:26.59#ibcon#read 6, iclass 32, count 0 2006.173.23:36:26.59#ibcon#end of sib2, iclass 32, count 0 2006.173.23:36:26.59#ibcon#*after write, iclass 32, count 0 2006.173.23:36:26.59#ibcon#*before return 0, iclass 32, count 0 2006.173.23:36:26.59#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.23:36:26.59#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.23:36:26.59#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.23:36:26.59#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.23:36:26.59$vck44/va=2,6 2006.173.23:36:26.59#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.23:36:26.59#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.23:36:26.59#ibcon#ireg 11 cls_cnt 2 2006.173.23:36:26.59#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.23:36:26.65#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.23:36:26.65#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.23:36:26.65#ibcon#enter wrdev, iclass 34, count 2 2006.173.23:36:26.65#ibcon#first serial, iclass 34, count 2 2006.173.23:36:26.65#ibcon#enter sib2, iclass 34, count 2 2006.173.23:36:26.65#ibcon#flushed, iclass 34, count 2 2006.173.23:36:26.65#ibcon#about to write, iclass 34, count 2 2006.173.23:36:26.65#ibcon#wrote, iclass 34, count 2 2006.173.23:36:26.65#ibcon#about to read 3, iclass 34, count 2 2006.173.23:36:26.67#ibcon#read 3, iclass 34, count 2 2006.173.23:36:26.67#ibcon#about to read 4, iclass 34, count 2 2006.173.23:36:26.67#ibcon#read 4, iclass 34, count 2 2006.173.23:36:26.67#ibcon#about to read 5, iclass 34, count 2 2006.173.23:36:26.67#ibcon#read 5, iclass 34, count 2 2006.173.23:36:26.67#ibcon#about to read 6, iclass 34, count 2 2006.173.23:36:26.67#ibcon#read 6, iclass 34, count 2 2006.173.23:36:26.67#ibcon#end of sib2, iclass 34, count 2 2006.173.23:36:26.67#ibcon#*mode == 0, iclass 34, count 2 2006.173.23:36:26.67#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.23:36:26.67#ibcon#[25=AT02-06\r\n] 2006.173.23:36:26.67#ibcon#*before write, iclass 34, count 2 2006.173.23:36:26.67#ibcon#enter sib2, iclass 34, count 2 2006.173.23:36:26.67#ibcon#flushed, iclass 34, count 2 2006.173.23:36:26.67#ibcon#about to write, iclass 34, count 2 2006.173.23:36:26.67#ibcon#wrote, iclass 34, count 2 2006.173.23:36:26.67#ibcon#about to read 3, iclass 34, count 2 2006.173.23:36:26.70#ibcon#read 3, iclass 34, count 2 2006.173.23:36:26.70#ibcon#about to read 4, iclass 34, count 2 2006.173.23:36:26.70#ibcon#read 4, iclass 34, count 2 2006.173.23:36:26.70#ibcon#about to read 5, iclass 34, count 2 2006.173.23:36:26.70#ibcon#read 5, iclass 34, count 2 2006.173.23:36:26.70#ibcon#about to read 6, iclass 34, count 2 2006.173.23:36:26.70#ibcon#read 6, iclass 34, count 2 2006.173.23:36:26.70#ibcon#end of sib2, iclass 34, count 2 2006.173.23:36:26.70#ibcon#*after write, iclass 34, count 2 2006.173.23:36:26.70#ibcon#*before return 0, iclass 34, count 2 2006.173.23:36:26.70#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.23:36:26.70#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.23:36:26.70#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.23:36:26.70#ibcon#ireg 7 cls_cnt 0 2006.173.23:36:26.70#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.23:36:26.82#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.23:36:26.82#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.23:36:26.82#ibcon#enter wrdev, iclass 34, count 0 2006.173.23:36:26.82#ibcon#first serial, iclass 34, count 0 2006.173.23:36:26.82#ibcon#enter sib2, iclass 34, count 0 2006.173.23:36:26.82#ibcon#flushed, iclass 34, count 0 2006.173.23:36:26.82#ibcon#about to write, iclass 34, count 0 2006.173.23:36:26.82#ibcon#wrote, iclass 34, count 0 2006.173.23:36:26.82#ibcon#about to read 3, iclass 34, count 0 2006.173.23:36:26.84#ibcon#read 3, iclass 34, count 0 2006.173.23:36:26.84#ibcon#about to read 4, iclass 34, count 0 2006.173.23:36:26.84#ibcon#read 4, iclass 34, count 0 2006.173.23:36:26.84#ibcon#about to read 5, iclass 34, count 0 2006.173.23:36:26.84#ibcon#read 5, iclass 34, count 0 2006.173.23:36:26.84#ibcon#about to read 6, iclass 34, count 0 2006.173.23:36:26.84#ibcon#read 6, iclass 34, count 0 2006.173.23:36:26.84#ibcon#end of sib2, iclass 34, count 0 2006.173.23:36:26.84#ibcon#*mode == 0, iclass 34, count 0 2006.173.23:36:26.84#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.23:36:26.84#ibcon#[25=USB\r\n] 2006.173.23:36:26.84#ibcon#*before write, iclass 34, count 0 2006.173.23:36:26.84#ibcon#enter sib2, iclass 34, count 0 2006.173.23:36:26.84#ibcon#flushed, iclass 34, count 0 2006.173.23:36:26.84#ibcon#about to write, iclass 34, count 0 2006.173.23:36:26.84#ibcon#wrote, iclass 34, count 0 2006.173.23:36:26.84#ibcon#about to read 3, iclass 34, count 0 2006.173.23:36:26.87#ibcon#read 3, iclass 34, count 0 2006.173.23:36:26.87#ibcon#about to read 4, iclass 34, count 0 2006.173.23:36:26.87#ibcon#read 4, iclass 34, count 0 2006.173.23:36:26.87#ibcon#about to read 5, iclass 34, count 0 2006.173.23:36:26.87#ibcon#read 5, iclass 34, count 0 2006.173.23:36:26.87#ibcon#about to read 6, iclass 34, count 0 2006.173.23:36:26.87#ibcon#read 6, iclass 34, count 0 2006.173.23:36:26.87#ibcon#end of sib2, iclass 34, count 0 2006.173.23:36:26.87#ibcon#*after write, iclass 34, count 0 2006.173.23:36:26.87#ibcon#*before return 0, iclass 34, count 0 2006.173.23:36:26.87#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.23:36:26.87#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.23:36:26.87#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.23:36:26.87#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.23:36:26.87$vck44/valo=3,564.99 2006.173.23:36:26.87#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.23:36:26.87#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.23:36:26.87#ibcon#ireg 17 cls_cnt 0 2006.173.23:36:26.87#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.23:36:26.87#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.23:36:26.87#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.23:36:26.87#ibcon#enter wrdev, iclass 36, count 0 2006.173.23:36:26.87#ibcon#first serial, iclass 36, count 0 2006.173.23:36:26.87#ibcon#enter sib2, iclass 36, count 0 2006.173.23:36:26.87#ibcon#flushed, iclass 36, count 0 2006.173.23:36:26.87#ibcon#about to write, iclass 36, count 0 2006.173.23:36:26.87#ibcon#wrote, iclass 36, count 0 2006.173.23:36:26.87#ibcon#about to read 3, iclass 36, count 0 2006.173.23:36:26.89#ibcon#read 3, iclass 36, count 0 2006.173.23:36:26.89#ibcon#about to read 4, iclass 36, count 0 2006.173.23:36:26.89#ibcon#read 4, iclass 36, count 0 2006.173.23:36:26.89#ibcon#about to read 5, iclass 36, count 0 2006.173.23:36:26.89#ibcon#read 5, iclass 36, count 0 2006.173.23:36:26.89#ibcon#about to read 6, iclass 36, count 0 2006.173.23:36:26.89#ibcon#read 6, iclass 36, count 0 2006.173.23:36:26.89#ibcon#end of sib2, iclass 36, count 0 2006.173.23:36:26.89#ibcon#*mode == 0, iclass 36, count 0 2006.173.23:36:26.89#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.23:36:26.89#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.23:36:26.89#ibcon#*before write, iclass 36, count 0 2006.173.23:36:26.89#ibcon#enter sib2, iclass 36, count 0 2006.173.23:36:26.89#ibcon#flushed, iclass 36, count 0 2006.173.23:36:26.89#ibcon#about to write, iclass 36, count 0 2006.173.23:36:26.89#ibcon#wrote, iclass 36, count 0 2006.173.23:36:26.89#ibcon#about to read 3, iclass 36, count 0 2006.173.23:36:26.93#ibcon#read 3, iclass 36, count 0 2006.173.23:36:26.93#ibcon#about to read 4, iclass 36, count 0 2006.173.23:36:26.93#ibcon#read 4, iclass 36, count 0 2006.173.23:36:26.93#ibcon#about to read 5, iclass 36, count 0 2006.173.23:36:26.93#ibcon#read 5, iclass 36, count 0 2006.173.23:36:26.93#ibcon#about to read 6, iclass 36, count 0 2006.173.23:36:26.93#ibcon#read 6, iclass 36, count 0 2006.173.23:36:26.93#ibcon#end of sib2, iclass 36, count 0 2006.173.23:36:26.93#ibcon#*after write, iclass 36, count 0 2006.173.23:36:26.93#ibcon#*before return 0, iclass 36, count 0 2006.173.23:36:26.93#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.23:36:26.93#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.23:36:26.93#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.23:36:26.93#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.23:36:26.93$vck44/va=3,5 2006.173.23:36:26.93#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.23:36:26.93#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.23:36:26.93#ibcon#ireg 11 cls_cnt 2 2006.173.23:36:26.93#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.23:36:26.99#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.23:36:26.99#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.23:36:26.99#ibcon#enter wrdev, iclass 38, count 2 2006.173.23:36:26.99#ibcon#first serial, iclass 38, count 2 2006.173.23:36:26.99#ibcon#enter sib2, iclass 38, count 2 2006.173.23:36:26.99#ibcon#flushed, iclass 38, count 2 2006.173.23:36:26.99#ibcon#about to write, iclass 38, count 2 2006.173.23:36:26.99#ibcon#wrote, iclass 38, count 2 2006.173.23:36:26.99#ibcon#about to read 3, iclass 38, count 2 2006.173.23:36:27.01#ibcon#read 3, iclass 38, count 2 2006.173.23:36:27.01#ibcon#about to read 4, iclass 38, count 2 2006.173.23:36:27.01#ibcon#read 4, iclass 38, count 2 2006.173.23:36:27.01#ibcon#about to read 5, iclass 38, count 2 2006.173.23:36:27.01#ibcon#read 5, iclass 38, count 2 2006.173.23:36:27.01#ibcon#about to read 6, iclass 38, count 2 2006.173.23:36:27.01#ibcon#read 6, iclass 38, count 2 2006.173.23:36:27.01#ibcon#end of sib2, iclass 38, count 2 2006.173.23:36:27.01#ibcon#*mode == 0, iclass 38, count 2 2006.173.23:36:27.01#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.23:36:27.01#ibcon#[25=AT03-05\r\n] 2006.173.23:36:27.01#ibcon#*before write, iclass 38, count 2 2006.173.23:36:27.01#ibcon#enter sib2, iclass 38, count 2 2006.173.23:36:27.01#ibcon#flushed, iclass 38, count 2 2006.173.23:36:27.01#ibcon#about to write, iclass 38, count 2 2006.173.23:36:27.01#ibcon#wrote, iclass 38, count 2 2006.173.23:36:27.01#ibcon#about to read 3, iclass 38, count 2 2006.173.23:36:27.04#ibcon#read 3, iclass 38, count 2 2006.173.23:36:27.04#ibcon#about to read 4, iclass 38, count 2 2006.173.23:36:27.04#ibcon#read 4, iclass 38, count 2 2006.173.23:36:27.04#ibcon#about to read 5, iclass 38, count 2 2006.173.23:36:27.04#ibcon#read 5, iclass 38, count 2 2006.173.23:36:27.04#ibcon#about to read 6, iclass 38, count 2 2006.173.23:36:27.04#ibcon#read 6, iclass 38, count 2 2006.173.23:36:27.04#ibcon#end of sib2, iclass 38, count 2 2006.173.23:36:27.04#ibcon#*after write, iclass 38, count 2 2006.173.23:36:27.04#ibcon#*before return 0, iclass 38, count 2 2006.173.23:36:27.04#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.23:36:27.04#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.23:36:27.04#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.23:36:27.04#ibcon#ireg 7 cls_cnt 0 2006.173.23:36:27.04#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.23:36:27.16#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.23:36:27.16#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.23:36:27.16#ibcon#enter wrdev, iclass 38, count 0 2006.173.23:36:27.16#ibcon#first serial, iclass 38, count 0 2006.173.23:36:27.16#ibcon#enter sib2, iclass 38, count 0 2006.173.23:36:27.16#ibcon#flushed, iclass 38, count 0 2006.173.23:36:27.16#ibcon#about to write, iclass 38, count 0 2006.173.23:36:27.16#ibcon#wrote, iclass 38, count 0 2006.173.23:36:27.16#ibcon#about to read 3, iclass 38, count 0 2006.173.23:36:27.18#ibcon#read 3, iclass 38, count 0 2006.173.23:36:27.18#ibcon#about to read 4, iclass 38, count 0 2006.173.23:36:27.18#ibcon#read 4, iclass 38, count 0 2006.173.23:36:27.18#ibcon#about to read 5, iclass 38, count 0 2006.173.23:36:27.18#ibcon#read 5, iclass 38, count 0 2006.173.23:36:27.18#ibcon#about to read 6, iclass 38, count 0 2006.173.23:36:27.18#ibcon#read 6, iclass 38, count 0 2006.173.23:36:27.18#ibcon#end of sib2, iclass 38, count 0 2006.173.23:36:27.18#ibcon#*mode == 0, iclass 38, count 0 2006.173.23:36:27.18#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.23:36:27.18#ibcon#[25=USB\r\n] 2006.173.23:36:27.18#ibcon#*before write, iclass 38, count 0 2006.173.23:36:27.18#ibcon#enter sib2, iclass 38, count 0 2006.173.23:36:27.18#ibcon#flushed, iclass 38, count 0 2006.173.23:36:27.18#ibcon#about to write, iclass 38, count 0 2006.173.23:36:27.18#ibcon#wrote, iclass 38, count 0 2006.173.23:36:27.18#ibcon#about to read 3, iclass 38, count 0 2006.173.23:36:27.21#ibcon#read 3, iclass 38, count 0 2006.173.23:36:27.21#ibcon#about to read 4, iclass 38, count 0 2006.173.23:36:27.21#ibcon#read 4, iclass 38, count 0 2006.173.23:36:27.21#ibcon#about to read 5, iclass 38, count 0 2006.173.23:36:27.21#ibcon#read 5, iclass 38, count 0 2006.173.23:36:27.21#ibcon#about to read 6, iclass 38, count 0 2006.173.23:36:27.21#ibcon#read 6, iclass 38, count 0 2006.173.23:36:27.21#ibcon#end of sib2, iclass 38, count 0 2006.173.23:36:27.21#ibcon#*after write, iclass 38, count 0 2006.173.23:36:27.21#ibcon#*before return 0, iclass 38, count 0 2006.173.23:36:27.21#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.23:36:27.21#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.23:36:27.21#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.23:36:27.21#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.23:36:27.21$vck44/valo=4,624.99 2006.173.23:36:27.21#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.23:36:27.21#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.23:36:27.21#ibcon#ireg 17 cls_cnt 0 2006.173.23:36:27.21#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.23:36:27.21#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.23:36:27.21#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.23:36:27.21#ibcon#enter wrdev, iclass 40, count 0 2006.173.23:36:27.21#ibcon#first serial, iclass 40, count 0 2006.173.23:36:27.21#ibcon#enter sib2, iclass 40, count 0 2006.173.23:36:27.21#ibcon#flushed, iclass 40, count 0 2006.173.23:36:27.21#ibcon#about to write, iclass 40, count 0 2006.173.23:36:27.21#ibcon#wrote, iclass 40, count 0 2006.173.23:36:27.21#ibcon#about to read 3, iclass 40, count 0 2006.173.23:36:27.23#ibcon#read 3, iclass 40, count 0 2006.173.23:36:27.23#ibcon#about to read 4, iclass 40, count 0 2006.173.23:36:27.23#ibcon#read 4, iclass 40, count 0 2006.173.23:36:27.23#ibcon#about to read 5, iclass 40, count 0 2006.173.23:36:27.23#ibcon#read 5, iclass 40, count 0 2006.173.23:36:27.23#ibcon#about to read 6, iclass 40, count 0 2006.173.23:36:27.23#ibcon#read 6, iclass 40, count 0 2006.173.23:36:27.23#ibcon#end of sib2, iclass 40, count 0 2006.173.23:36:27.23#ibcon#*mode == 0, iclass 40, count 0 2006.173.23:36:27.23#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.23:36:27.23#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.23:36:27.23#ibcon#*before write, iclass 40, count 0 2006.173.23:36:27.23#ibcon#enter sib2, iclass 40, count 0 2006.173.23:36:27.23#ibcon#flushed, iclass 40, count 0 2006.173.23:36:27.23#ibcon#about to write, iclass 40, count 0 2006.173.23:36:27.23#ibcon#wrote, iclass 40, count 0 2006.173.23:36:27.23#ibcon#about to read 3, iclass 40, count 0 2006.173.23:36:27.27#ibcon#read 3, iclass 40, count 0 2006.173.23:36:27.27#ibcon#about to read 4, iclass 40, count 0 2006.173.23:36:27.27#ibcon#read 4, iclass 40, count 0 2006.173.23:36:27.27#ibcon#about to read 5, iclass 40, count 0 2006.173.23:36:27.27#ibcon#read 5, iclass 40, count 0 2006.173.23:36:27.27#ibcon#about to read 6, iclass 40, count 0 2006.173.23:36:27.27#ibcon#read 6, iclass 40, count 0 2006.173.23:36:27.27#ibcon#end of sib2, iclass 40, count 0 2006.173.23:36:27.27#ibcon#*after write, iclass 40, count 0 2006.173.23:36:27.27#ibcon#*before return 0, iclass 40, count 0 2006.173.23:36:27.27#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.23:36:27.27#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.23:36:27.27#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.23:36:27.27#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.23:36:27.27$vck44/va=4,6 2006.173.23:36:27.27#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.23:36:27.27#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.23:36:27.27#ibcon#ireg 11 cls_cnt 2 2006.173.23:36:27.27#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.23:36:27.33#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.23:36:27.33#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.23:36:27.33#ibcon#enter wrdev, iclass 4, count 2 2006.173.23:36:27.33#ibcon#first serial, iclass 4, count 2 2006.173.23:36:27.33#ibcon#enter sib2, iclass 4, count 2 2006.173.23:36:27.33#ibcon#flushed, iclass 4, count 2 2006.173.23:36:27.33#ibcon#about to write, iclass 4, count 2 2006.173.23:36:27.33#ibcon#wrote, iclass 4, count 2 2006.173.23:36:27.33#ibcon#about to read 3, iclass 4, count 2 2006.173.23:36:27.35#ibcon#read 3, iclass 4, count 2 2006.173.23:36:27.35#ibcon#about to read 4, iclass 4, count 2 2006.173.23:36:27.35#ibcon#read 4, iclass 4, count 2 2006.173.23:36:27.35#ibcon#about to read 5, iclass 4, count 2 2006.173.23:36:27.35#ibcon#read 5, iclass 4, count 2 2006.173.23:36:27.35#ibcon#about to read 6, iclass 4, count 2 2006.173.23:36:27.35#ibcon#read 6, iclass 4, count 2 2006.173.23:36:27.35#ibcon#end of sib2, iclass 4, count 2 2006.173.23:36:27.35#ibcon#*mode == 0, iclass 4, count 2 2006.173.23:36:27.35#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.23:36:27.35#ibcon#[25=AT04-06\r\n] 2006.173.23:36:27.35#ibcon#*before write, iclass 4, count 2 2006.173.23:36:27.35#ibcon#enter sib2, iclass 4, count 2 2006.173.23:36:27.35#ibcon#flushed, iclass 4, count 2 2006.173.23:36:27.35#ibcon#about to write, iclass 4, count 2 2006.173.23:36:27.35#ibcon#wrote, iclass 4, count 2 2006.173.23:36:27.35#ibcon#about to read 3, iclass 4, count 2 2006.173.23:36:27.38#ibcon#read 3, iclass 4, count 2 2006.173.23:36:27.38#ibcon#about to read 4, iclass 4, count 2 2006.173.23:36:27.38#ibcon#read 4, iclass 4, count 2 2006.173.23:36:27.38#ibcon#about to read 5, iclass 4, count 2 2006.173.23:36:27.38#ibcon#read 5, iclass 4, count 2 2006.173.23:36:27.38#ibcon#about to read 6, iclass 4, count 2 2006.173.23:36:27.38#ibcon#read 6, iclass 4, count 2 2006.173.23:36:27.38#ibcon#end of sib2, iclass 4, count 2 2006.173.23:36:27.38#ibcon#*after write, iclass 4, count 2 2006.173.23:36:27.38#ibcon#*before return 0, iclass 4, count 2 2006.173.23:36:27.38#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.23:36:27.38#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.23:36:27.38#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.23:36:27.38#ibcon#ireg 7 cls_cnt 0 2006.173.23:36:27.38#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.23:36:27.50#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.23:36:27.50#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.23:36:27.50#ibcon#enter wrdev, iclass 4, count 0 2006.173.23:36:27.50#ibcon#first serial, iclass 4, count 0 2006.173.23:36:27.50#ibcon#enter sib2, iclass 4, count 0 2006.173.23:36:27.50#ibcon#flushed, iclass 4, count 0 2006.173.23:36:27.50#ibcon#about to write, iclass 4, count 0 2006.173.23:36:27.50#ibcon#wrote, iclass 4, count 0 2006.173.23:36:27.50#ibcon#about to read 3, iclass 4, count 0 2006.173.23:36:27.52#ibcon#read 3, iclass 4, count 0 2006.173.23:36:27.52#ibcon#about to read 4, iclass 4, count 0 2006.173.23:36:27.52#ibcon#read 4, iclass 4, count 0 2006.173.23:36:27.52#ibcon#about to read 5, iclass 4, count 0 2006.173.23:36:27.52#ibcon#read 5, iclass 4, count 0 2006.173.23:36:27.52#ibcon#about to read 6, iclass 4, count 0 2006.173.23:36:27.52#ibcon#read 6, iclass 4, count 0 2006.173.23:36:27.52#ibcon#end of sib2, iclass 4, count 0 2006.173.23:36:27.52#ibcon#*mode == 0, iclass 4, count 0 2006.173.23:36:27.52#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.23:36:27.52#ibcon#[25=USB\r\n] 2006.173.23:36:27.52#ibcon#*before write, iclass 4, count 0 2006.173.23:36:27.52#ibcon#enter sib2, iclass 4, count 0 2006.173.23:36:27.52#ibcon#flushed, iclass 4, count 0 2006.173.23:36:27.52#ibcon#about to write, iclass 4, count 0 2006.173.23:36:27.52#ibcon#wrote, iclass 4, count 0 2006.173.23:36:27.52#ibcon#about to read 3, iclass 4, count 0 2006.173.23:36:27.55#ibcon#read 3, iclass 4, count 0 2006.173.23:36:27.55#ibcon#about to read 4, iclass 4, count 0 2006.173.23:36:27.55#ibcon#read 4, iclass 4, count 0 2006.173.23:36:27.55#ibcon#about to read 5, iclass 4, count 0 2006.173.23:36:27.55#ibcon#read 5, iclass 4, count 0 2006.173.23:36:27.55#ibcon#about to read 6, iclass 4, count 0 2006.173.23:36:27.55#ibcon#read 6, iclass 4, count 0 2006.173.23:36:27.55#ibcon#end of sib2, iclass 4, count 0 2006.173.23:36:27.55#ibcon#*after write, iclass 4, count 0 2006.173.23:36:27.55#ibcon#*before return 0, iclass 4, count 0 2006.173.23:36:27.55#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.23:36:27.55#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.23:36:27.55#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.23:36:27.55#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.23:36:27.55$vck44/valo=5,734.99 2006.173.23:36:27.55#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.23:36:27.55#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.23:36:27.55#ibcon#ireg 17 cls_cnt 0 2006.173.23:36:27.55#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.23:36:27.55#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.23:36:27.55#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.23:36:27.55#ibcon#enter wrdev, iclass 6, count 0 2006.173.23:36:27.55#ibcon#first serial, iclass 6, count 0 2006.173.23:36:27.55#ibcon#enter sib2, iclass 6, count 0 2006.173.23:36:27.55#ibcon#flushed, iclass 6, count 0 2006.173.23:36:27.55#ibcon#about to write, iclass 6, count 0 2006.173.23:36:27.55#ibcon#wrote, iclass 6, count 0 2006.173.23:36:27.55#ibcon#about to read 3, iclass 6, count 0 2006.173.23:36:27.57#ibcon#read 3, iclass 6, count 0 2006.173.23:36:27.57#ibcon#about to read 4, iclass 6, count 0 2006.173.23:36:27.57#ibcon#read 4, iclass 6, count 0 2006.173.23:36:27.57#ibcon#about to read 5, iclass 6, count 0 2006.173.23:36:27.57#ibcon#read 5, iclass 6, count 0 2006.173.23:36:27.57#ibcon#about to read 6, iclass 6, count 0 2006.173.23:36:27.57#ibcon#read 6, iclass 6, count 0 2006.173.23:36:27.57#ibcon#end of sib2, iclass 6, count 0 2006.173.23:36:27.57#ibcon#*mode == 0, iclass 6, count 0 2006.173.23:36:27.57#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.23:36:27.57#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.23:36:27.57#ibcon#*before write, iclass 6, count 0 2006.173.23:36:27.57#ibcon#enter sib2, iclass 6, count 0 2006.173.23:36:27.57#ibcon#flushed, iclass 6, count 0 2006.173.23:36:27.57#ibcon#about to write, iclass 6, count 0 2006.173.23:36:27.57#ibcon#wrote, iclass 6, count 0 2006.173.23:36:27.57#ibcon#about to read 3, iclass 6, count 0 2006.173.23:36:27.61#ibcon#read 3, iclass 6, count 0 2006.173.23:36:27.61#ibcon#about to read 4, iclass 6, count 0 2006.173.23:36:27.61#ibcon#read 4, iclass 6, count 0 2006.173.23:36:27.61#ibcon#about to read 5, iclass 6, count 0 2006.173.23:36:27.61#ibcon#read 5, iclass 6, count 0 2006.173.23:36:27.61#ibcon#about to read 6, iclass 6, count 0 2006.173.23:36:27.61#ibcon#read 6, iclass 6, count 0 2006.173.23:36:27.61#ibcon#end of sib2, iclass 6, count 0 2006.173.23:36:27.61#ibcon#*after write, iclass 6, count 0 2006.173.23:36:27.61#ibcon#*before return 0, iclass 6, count 0 2006.173.23:36:27.61#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.23:36:27.61#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.23:36:27.61#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.23:36:27.61#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.23:36:27.61$vck44/va=5,4 2006.173.23:36:27.61#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.23:36:27.61#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.23:36:27.61#ibcon#ireg 11 cls_cnt 2 2006.173.23:36:27.61#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.23:36:27.67#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.23:36:27.67#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.23:36:27.67#ibcon#enter wrdev, iclass 10, count 2 2006.173.23:36:27.67#ibcon#first serial, iclass 10, count 2 2006.173.23:36:27.67#ibcon#enter sib2, iclass 10, count 2 2006.173.23:36:27.67#ibcon#flushed, iclass 10, count 2 2006.173.23:36:27.67#ibcon#about to write, iclass 10, count 2 2006.173.23:36:27.67#ibcon#wrote, iclass 10, count 2 2006.173.23:36:27.67#ibcon#about to read 3, iclass 10, count 2 2006.173.23:36:27.69#ibcon#read 3, iclass 10, count 2 2006.173.23:36:27.69#ibcon#about to read 4, iclass 10, count 2 2006.173.23:36:27.69#ibcon#read 4, iclass 10, count 2 2006.173.23:36:27.69#ibcon#about to read 5, iclass 10, count 2 2006.173.23:36:27.69#ibcon#read 5, iclass 10, count 2 2006.173.23:36:27.69#ibcon#about to read 6, iclass 10, count 2 2006.173.23:36:27.69#ibcon#read 6, iclass 10, count 2 2006.173.23:36:27.69#ibcon#end of sib2, iclass 10, count 2 2006.173.23:36:27.69#ibcon#*mode == 0, iclass 10, count 2 2006.173.23:36:27.69#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.23:36:27.69#ibcon#[25=AT05-04\r\n] 2006.173.23:36:27.69#ibcon#*before write, iclass 10, count 2 2006.173.23:36:27.69#ibcon#enter sib2, iclass 10, count 2 2006.173.23:36:27.69#ibcon#flushed, iclass 10, count 2 2006.173.23:36:27.69#ibcon#about to write, iclass 10, count 2 2006.173.23:36:27.69#ibcon#wrote, iclass 10, count 2 2006.173.23:36:27.69#ibcon#about to read 3, iclass 10, count 2 2006.173.23:36:27.72#ibcon#read 3, iclass 10, count 2 2006.173.23:36:27.72#ibcon#about to read 4, iclass 10, count 2 2006.173.23:36:27.72#ibcon#read 4, iclass 10, count 2 2006.173.23:36:27.72#ibcon#about to read 5, iclass 10, count 2 2006.173.23:36:27.72#ibcon#read 5, iclass 10, count 2 2006.173.23:36:27.72#ibcon#about to read 6, iclass 10, count 2 2006.173.23:36:27.72#ibcon#read 6, iclass 10, count 2 2006.173.23:36:27.72#ibcon#end of sib2, iclass 10, count 2 2006.173.23:36:27.72#ibcon#*after write, iclass 10, count 2 2006.173.23:36:27.72#ibcon#*before return 0, iclass 10, count 2 2006.173.23:36:27.72#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.23:36:27.72#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.23:36:27.72#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.23:36:27.72#ibcon#ireg 7 cls_cnt 0 2006.173.23:36:27.72#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.23:36:27.84#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.23:36:27.84#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.23:36:27.84#ibcon#enter wrdev, iclass 10, count 0 2006.173.23:36:27.84#ibcon#first serial, iclass 10, count 0 2006.173.23:36:27.84#ibcon#enter sib2, iclass 10, count 0 2006.173.23:36:27.84#ibcon#flushed, iclass 10, count 0 2006.173.23:36:27.84#ibcon#about to write, iclass 10, count 0 2006.173.23:36:27.84#ibcon#wrote, iclass 10, count 0 2006.173.23:36:27.84#ibcon#about to read 3, iclass 10, count 0 2006.173.23:36:27.86#ibcon#read 3, iclass 10, count 0 2006.173.23:36:27.86#ibcon#about to read 4, iclass 10, count 0 2006.173.23:36:27.86#ibcon#read 4, iclass 10, count 0 2006.173.23:36:27.86#ibcon#about to read 5, iclass 10, count 0 2006.173.23:36:27.86#ibcon#read 5, iclass 10, count 0 2006.173.23:36:27.86#ibcon#about to read 6, iclass 10, count 0 2006.173.23:36:27.86#ibcon#read 6, iclass 10, count 0 2006.173.23:36:27.86#ibcon#end of sib2, iclass 10, count 0 2006.173.23:36:27.86#ibcon#*mode == 0, iclass 10, count 0 2006.173.23:36:27.86#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.23:36:27.86#ibcon#[25=USB\r\n] 2006.173.23:36:27.86#ibcon#*before write, iclass 10, count 0 2006.173.23:36:27.86#ibcon#enter sib2, iclass 10, count 0 2006.173.23:36:27.86#ibcon#flushed, iclass 10, count 0 2006.173.23:36:27.86#ibcon#about to write, iclass 10, count 0 2006.173.23:36:27.86#ibcon#wrote, iclass 10, count 0 2006.173.23:36:27.86#ibcon#about to read 3, iclass 10, count 0 2006.173.23:36:27.89#ibcon#read 3, iclass 10, count 0 2006.173.23:36:27.89#ibcon#about to read 4, iclass 10, count 0 2006.173.23:36:27.89#ibcon#read 4, iclass 10, count 0 2006.173.23:36:27.89#ibcon#about to read 5, iclass 10, count 0 2006.173.23:36:27.89#ibcon#read 5, iclass 10, count 0 2006.173.23:36:27.89#ibcon#about to read 6, iclass 10, count 0 2006.173.23:36:27.89#ibcon#read 6, iclass 10, count 0 2006.173.23:36:27.89#ibcon#end of sib2, iclass 10, count 0 2006.173.23:36:27.89#ibcon#*after write, iclass 10, count 0 2006.173.23:36:27.89#ibcon#*before return 0, iclass 10, count 0 2006.173.23:36:27.89#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.23:36:27.89#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.23:36:27.89#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.23:36:27.89#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.23:36:27.89$vck44/valo=6,814.99 2006.173.23:36:27.89#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.23:36:27.89#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.23:36:27.89#ibcon#ireg 17 cls_cnt 0 2006.173.23:36:27.89#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.23:36:27.89#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.23:36:27.89#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.23:36:27.89#ibcon#enter wrdev, iclass 12, count 0 2006.173.23:36:27.89#ibcon#first serial, iclass 12, count 0 2006.173.23:36:27.89#ibcon#enter sib2, iclass 12, count 0 2006.173.23:36:27.89#ibcon#flushed, iclass 12, count 0 2006.173.23:36:27.89#ibcon#about to write, iclass 12, count 0 2006.173.23:36:27.89#ibcon#wrote, iclass 12, count 0 2006.173.23:36:27.89#ibcon#about to read 3, iclass 12, count 0 2006.173.23:36:27.91#ibcon#read 3, iclass 12, count 0 2006.173.23:36:27.91#ibcon#about to read 4, iclass 12, count 0 2006.173.23:36:27.91#ibcon#read 4, iclass 12, count 0 2006.173.23:36:27.91#ibcon#about to read 5, iclass 12, count 0 2006.173.23:36:27.91#ibcon#read 5, iclass 12, count 0 2006.173.23:36:27.91#ibcon#about to read 6, iclass 12, count 0 2006.173.23:36:27.91#ibcon#read 6, iclass 12, count 0 2006.173.23:36:27.91#ibcon#end of sib2, iclass 12, count 0 2006.173.23:36:27.91#ibcon#*mode == 0, iclass 12, count 0 2006.173.23:36:27.91#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.23:36:27.91#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.23:36:27.91#ibcon#*before write, iclass 12, count 0 2006.173.23:36:27.91#ibcon#enter sib2, iclass 12, count 0 2006.173.23:36:27.91#ibcon#flushed, iclass 12, count 0 2006.173.23:36:27.91#ibcon#about to write, iclass 12, count 0 2006.173.23:36:27.91#ibcon#wrote, iclass 12, count 0 2006.173.23:36:27.91#ibcon#about to read 3, iclass 12, count 0 2006.173.23:36:27.95#ibcon#read 3, iclass 12, count 0 2006.173.23:36:27.95#ibcon#about to read 4, iclass 12, count 0 2006.173.23:36:27.95#ibcon#read 4, iclass 12, count 0 2006.173.23:36:27.95#ibcon#about to read 5, iclass 12, count 0 2006.173.23:36:27.95#ibcon#read 5, iclass 12, count 0 2006.173.23:36:27.95#ibcon#about to read 6, iclass 12, count 0 2006.173.23:36:27.95#ibcon#read 6, iclass 12, count 0 2006.173.23:36:27.95#ibcon#end of sib2, iclass 12, count 0 2006.173.23:36:27.95#ibcon#*after write, iclass 12, count 0 2006.173.23:36:27.95#ibcon#*before return 0, iclass 12, count 0 2006.173.23:36:27.95#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.23:36:27.95#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.23:36:27.95#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.23:36:27.95#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.23:36:27.95$vck44/va=6,3 2006.173.23:36:27.95#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.23:36:27.95#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.23:36:27.95#ibcon#ireg 11 cls_cnt 2 2006.173.23:36:27.95#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.23:36:28.01#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.23:36:28.01#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.23:36:28.01#ibcon#enter wrdev, iclass 14, count 2 2006.173.23:36:28.01#ibcon#first serial, iclass 14, count 2 2006.173.23:36:28.01#ibcon#enter sib2, iclass 14, count 2 2006.173.23:36:28.01#ibcon#flushed, iclass 14, count 2 2006.173.23:36:28.01#ibcon#about to write, iclass 14, count 2 2006.173.23:36:28.01#ibcon#wrote, iclass 14, count 2 2006.173.23:36:28.01#ibcon#about to read 3, iclass 14, count 2 2006.173.23:36:28.03#ibcon#read 3, iclass 14, count 2 2006.173.23:36:28.03#ibcon#about to read 4, iclass 14, count 2 2006.173.23:36:28.03#ibcon#read 4, iclass 14, count 2 2006.173.23:36:28.03#ibcon#about to read 5, iclass 14, count 2 2006.173.23:36:28.03#ibcon#read 5, iclass 14, count 2 2006.173.23:36:28.03#ibcon#about to read 6, iclass 14, count 2 2006.173.23:36:28.03#ibcon#read 6, iclass 14, count 2 2006.173.23:36:28.03#ibcon#end of sib2, iclass 14, count 2 2006.173.23:36:28.03#ibcon#*mode == 0, iclass 14, count 2 2006.173.23:36:28.03#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.23:36:28.03#ibcon#[25=AT06-03\r\n] 2006.173.23:36:28.03#ibcon#*before write, iclass 14, count 2 2006.173.23:36:28.03#ibcon#enter sib2, iclass 14, count 2 2006.173.23:36:28.03#ibcon#flushed, iclass 14, count 2 2006.173.23:36:28.03#ibcon#about to write, iclass 14, count 2 2006.173.23:36:28.03#ibcon#wrote, iclass 14, count 2 2006.173.23:36:28.03#ibcon#about to read 3, iclass 14, count 2 2006.173.23:36:28.06#ibcon#read 3, iclass 14, count 2 2006.173.23:36:28.06#ibcon#about to read 4, iclass 14, count 2 2006.173.23:36:28.06#ibcon#read 4, iclass 14, count 2 2006.173.23:36:28.06#ibcon#about to read 5, iclass 14, count 2 2006.173.23:36:28.06#ibcon#read 5, iclass 14, count 2 2006.173.23:36:28.06#ibcon#about to read 6, iclass 14, count 2 2006.173.23:36:28.06#ibcon#read 6, iclass 14, count 2 2006.173.23:36:28.06#ibcon#end of sib2, iclass 14, count 2 2006.173.23:36:28.06#ibcon#*after write, iclass 14, count 2 2006.173.23:36:28.06#ibcon#*before return 0, iclass 14, count 2 2006.173.23:36:28.06#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.23:36:28.06#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.23:36:28.06#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.23:36:28.06#ibcon#ireg 7 cls_cnt 0 2006.173.23:36:28.06#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.23:36:28.12#abcon#<5=/13 0.8 2.2 23.49 871003.2\r\n> 2006.173.23:36:28.14#abcon#{5=INTERFACE CLEAR} 2006.173.23:36:28.18#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.23:36:28.18#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.23:36:28.18#ibcon#enter wrdev, iclass 14, count 0 2006.173.23:36:28.18#ibcon#first serial, iclass 14, count 0 2006.173.23:36:28.18#ibcon#enter sib2, iclass 14, count 0 2006.173.23:36:28.18#ibcon#flushed, iclass 14, count 0 2006.173.23:36:28.18#ibcon#about to write, iclass 14, count 0 2006.173.23:36:28.18#ibcon#wrote, iclass 14, count 0 2006.173.23:36:28.18#ibcon#about to read 3, iclass 14, count 0 2006.173.23:36:28.20#ibcon#read 3, iclass 14, count 0 2006.173.23:36:28.20#ibcon#about to read 4, iclass 14, count 0 2006.173.23:36:28.20#ibcon#read 4, iclass 14, count 0 2006.173.23:36:28.20#ibcon#about to read 5, iclass 14, count 0 2006.173.23:36:28.20#ibcon#read 5, iclass 14, count 0 2006.173.23:36:28.20#ibcon#about to read 6, iclass 14, count 0 2006.173.23:36:28.20#ibcon#read 6, iclass 14, count 0 2006.173.23:36:28.20#ibcon#end of sib2, iclass 14, count 0 2006.173.23:36:28.20#ibcon#*mode == 0, iclass 14, count 0 2006.173.23:36:28.20#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.23:36:28.20#ibcon#[25=USB\r\n] 2006.173.23:36:28.20#ibcon#*before write, iclass 14, count 0 2006.173.23:36:28.20#ibcon#enter sib2, iclass 14, count 0 2006.173.23:36:28.20#ibcon#flushed, iclass 14, count 0 2006.173.23:36:28.20#ibcon#about to write, iclass 14, count 0 2006.173.23:36:28.20#ibcon#wrote, iclass 14, count 0 2006.173.23:36:28.20#ibcon#about to read 3, iclass 14, count 0 2006.173.23:36:28.20#abcon#[5=S1D000X0/0*\r\n] 2006.173.23:36:28.23#ibcon#read 3, iclass 14, count 0 2006.173.23:36:28.23#ibcon#about to read 4, iclass 14, count 0 2006.173.23:36:28.23#ibcon#read 4, iclass 14, count 0 2006.173.23:36:28.23#ibcon#about to read 5, iclass 14, count 0 2006.173.23:36:28.23#ibcon#read 5, iclass 14, count 0 2006.173.23:36:28.23#ibcon#about to read 6, iclass 14, count 0 2006.173.23:36:28.23#ibcon#read 6, iclass 14, count 0 2006.173.23:36:28.23#ibcon#end of sib2, iclass 14, count 0 2006.173.23:36:28.23#ibcon#*after write, iclass 14, count 0 2006.173.23:36:28.23#ibcon#*before return 0, iclass 14, count 0 2006.173.23:36:28.23#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.23:36:28.23#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.23:36:28.23#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.23:36:28.23#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.23:36:28.23$vck44/valo=7,864.99 2006.173.23:36:28.23#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.23:36:28.23#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.23:36:28.23#ibcon#ireg 17 cls_cnt 0 2006.173.23:36:28.23#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.23:36:28.23#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.23:36:28.23#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.23:36:28.23#ibcon#enter wrdev, iclass 20, count 0 2006.173.23:36:28.23#ibcon#first serial, iclass 20, count 0 2006.173.23:36:28.23#ibcon#enter sib2, iclass 20, count 0 2006.173.23:36:28.23#ibcon#flushed, iclass 20, count 0 2006.173.23:36:28.23#ibcon#about to write, iclass 20, count 0 2006.173.23:36:28.23#ibcon#wrote, iclass 20, count 0 2006.173.23:36:28.23#ibcon#about to read 3, iclass 20, count 0 2006.173.23:36:28.25#ibcon#read 3, iclass 20, count 0 2006.173.23:36:28.25#ibcon#about to read 4, iclass 20, count 0 2006.173.23:36:28.25#ibcon#read 4, iclass 20, count 0 2006.173.23:36:28.25#ibcon#about to read 5, iclass 20, count 0 2006.173.23:36:28.25#ibcon#read 5, iclass 20, count 0 2006.173.23:36:28.25#ibcon#about to read 6, iclass 20, count 0 2006.173.23:36:28.25#ibcon#read 6, iclass 20, count 0 2006.173.23:36:28.25#ibcon#end of sib2, iclass 20, count 0 2006.173.23:36:28.25#ibcon#*mode == 0, iclass 20, count 0 2006.173.23:36:28.25#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.23:36:28.25#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.23:36:28.25#ibcon#*before write, iclass 20, count 0 2006.173.23:36:28.25#ibcon#enter sib2, iclass 20, count 0 2006.173.23:36:28.25#ibcon#flushed, iclass 20, count 0 2006.173.23:36:28.25#ibcon#about to write, iclass 20, count 0 2006.173.23:36:28.25#ibcon#wrote, iclass 20, count 0 2006.173.23:36:28.25#ibcon#about to read 3, iclass 20, count 0 2006.173.23:36:28.29#ibcon#read 3, iclass 20, count 0 2006.173.23:36:28.29#ibcon#about to read 4, iclass 20, count 0 2006.173.23:36:28.29#ibcon#read 4, iclass 20, count 0 2006.173.23:36:28.29#ibcon#about to read 5, iclass 20, count 0 2006.173.23:36:28.29#ibcon#read 5, iclass 20, count 0 2006.173.23:36:28.29#ibcon#about to read 6, iclass 20, count 0 2006.173.23:36:28.29#ibcon#read 6, iclass 20, count 0 2006.173.23:36:28.29#ibcon#end of sib2, iclass 20, count 0 2006.173.23:36:28.29#ibcon#*after write, iclass 20, count 0 2006.173.23:36:28.29#ibcon#*before return 0, iclass 20, count 0 2006.173.23:36:28.29#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.23:36:28.29#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.23:36:28.29#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.23:36:28.29#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.23:36:28.29$vck44/va=7,4 2006.173.23:36:28.29#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.23:36:28.29#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.23:36:28.29#ibcon#ireg 11 cls_cnt 2 2006.173.23:36:28.29#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.23:36:28.35#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.23:36:28.35#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.23:36:28.35#ibcon#enter wrdev, iclass 22, count 2 2006.173.23:36:28.35#ibcon#first serial, iclass 22, count 2 2006.173.23:36:28.35#ibcon#enter sib2, iclass 22, count 2 2006.173.23:36:28.35#ibcon#flushed, iclass 22, count 2 2006.173.23:36:28.35#ibcon#about to write, iclass 22, count 2 2006.173.23:36:28.35#ibcon#wrote, iclass 22, count 2 2006.173.23:36:28.35#ibcon#about to read 3, iclass 22, count 2 2006.173.23:36:28.37#ibcon#read 3, iclass 22, count 2 2006.173.23:36:28.37#ibcon#about to read 4, iclass 22, count 2 2006.173.23:36:28.37#ibcon#read 4, iclass 22, count 2 2006.173.23:36:28.37#ibcon#about to read 5, iclass 22, count 2 2006.173.23:36:28.37#ibcon#read 5, iclass 22, count 2 2006.173.23:36:28.37#ibcon#about to read 6, iclass 22, count 2 2006.173.23:36:28.37#ibcon#read 6, iclass 22, count 2 2006.173.23:36:28.37#ibcon#end of sib2, iclass 22, count 2 2006.173.23:36:28.37#ibcon#*mode == 0, iclass 22, count 2 2006.173.23:36:28.37#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.23:36:28.37#ibcon#[25=AT07-04\r\n] 2006.173.23:36:28.37#ibcon#*before write, iclass 22, count 2 2006.173.23:36:28.37#ibcon#enter sib2, iclass 22, count 2 2006.173.23:36:28.37#ibcon#flushed, iclass 22, count 2 2006.173.23:36:28.37#ibcon#about to write, iclass 22, count 2 2006.173.23:36:28.37#ibcon#wrote, iclass 22, count 2 2006.173.23:36:28.37#ibcon#about to read 3, iclass 22, count 2 2006.173.23:36:28.40#ibcon#read 3, iclass 22, count 2 2006.173.23:36:28.40#ibcon#about to read 4, iclass 22, count 2 2006.173.23:36:28.40#ibcon#read 4, iclass 22, count 2 2006.173.23:36:28.40#ibcon#about to read 5, iclass 22, count 2 2006.173.23:36:28.40#ibcon#read 5, iclass 22, count 2 2006.173.23:36:28.40#ibcon#about to read 6, iclass 22, count 2 2006.173.23:36:28.40#ibcon#read 6, iclass 22, count 2 2006.173.23:36:28.40#ibcon#end of sib2, iclass 22, count 2 2006.173.23:36:28.40#ibcon#*after write, iclass 22, count 2 2006.173.23:36:28.40#ibcon#*before return 0, iclass 22, count 2 2006.173.23:36:28.40#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.23:36:28.40#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.23:36:28.40#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.23:36:28.40#ibcon#ireg 7 cls_cnt 0 2006.173.23:36:28.40#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.23:36:28.52#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.23:36:28.52#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.23:36:28.52#ibcon#enter wrdev, iclass 22, count 0 2006.173.23:36:28.52#ibcon#first serial, iclass 22, count 0 2006.173.23:36:28.52#ibcon#enter sib2, iclass 22, count 0 2006.173.23:36:28.52#ibcon#flushed, iclass 22, count 0 2006.173.23:36:28.52#ibcon#about to write, iclass 22, count 0 2006.173.23:36:28.52#ibcon#wrote, iclass 22, count 0 2006.173.23:36:28.52#ibcon#about to read 3, iclass 22, count 0 2006.173.23:36:28.54#ibcon#read 3, iclass 22, count 0 2006.173.23:36:28.54#ibcon#about to read 4, iclass 22, count 0 2006.173.23:36:28.54#ibcon#read 4, iclass 22, count 0 2006.173.23:36:28.54#ibcon#about to read 5, iclass 22, count 0 2006.173.23:36:28.54#ibcon#read 5, iclass 22, count 0 2006.173.23:36:28.54#ibcon#about to read 6, iclass 22, count 0 2006.173.23:36:28.54#ibcon#read 6, iclass 22, count 0 2006.173.23:36:28.54#ibcon#end of sib2, iclass 22, count 0 2006.173.23:36:28.54#ibcon#*mode == 0, iclass 22, count 0 2006.173.23:36:28.54#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.23:36:28.54#ibcon#[25=USB\r\n] 2006.173.23:36:28.54#ibcon#*before write, iclass 22, count 0 2006.173.23:36:28.54#ibcon#enter sib2, iclass 22, count 0 2006.173.23:36:28.54#ibcon#flushed, iclass 22, count 0 2006.173.23:36:28.54#ibcon#about to write, iclass 22, count 0 2006.173.23:36:28.54#ibcon#wrote, iclass 22, count 0 2006.173.23:36:28.54#ibcon#about to read 3, iclass 22, count 0 2006.173.23:36:28.57#ibcon#read 3, iclass 22, count 0 2006.173.23:36:28.57#ibcon#about to read 4, iclass 22, count 0 2006.173.23:36:28.57#ibcon#read 4, iclass 22, count 0 2006.173.23:36:28.57#ibcon#about to read 5, iclass 22, count 0 2006.173.23:36:28.57#ibcon#read 5, iclass 22, count 0 2006.173.23:36:28.57#ibcon#about to read 6, iclass 22, count 0 2006.173.23:36:28.57#ibcon#read 6, iclass 22, count 0 2006.173.23:36:28.57#ibcon#end of sib2, iclass 22, count 0 2006.173.23:36:28.57#ibcon#*after write, iclass 22, count 0 2006.173.23:36:28.57#ibcon#*before return 0, iclass 22, count 0 2006.173.23:36:28.57#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.23:36:28.57#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.23:36:28.57#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.23:36:28.57#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.23:36:28.57$vck44/valo=8,884.99 2006.173.23:36:28.57#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.23:36:28.57#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.23:36:28.57#ibcon#ireg 17 cls_cnt 0 2006.173.23:36:28.57#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.23:36:28.57#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.23:36:28.57#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.23:36:28.57#ibcon#enter wrdev, iclass 24, count 0 2006.173.23:36:28.57#ibcon#first serial, iclass 24, count 0 2006.173.23:36:28.57#ibcon#enter sib2, iclass 24, count 0 2006.173.23:36:28.57#ibcon#flushed, iclass 24, count 0 2006.173.23:36:28.57#ibcon#about to write, iclass 24, count 0 2006.173.23:36:28.57#ibcon#wrote, iclass 24, count 0 2006.173.23:36:28.57#ibcon#about to read 3, iclass 24, count 0 2006.173.23:36:28.59#ibcon#read 3, iclass 24, count 0 2006.173.23:36:28.59#ibcon#about to read 4, iclass 24, count 0 2006.173.23:36:28.59#ibcon#read 4, iclass 24, count 0 2006.173.23:36:28.59#ibcon#about to read 5, iclass 24, count 0 2006.173.23:36:28.59#ibcon#read 5, iclass 24, count 0 2006.173.23:36:28.59#ibcon#about to read 6, iclass 24, count 0 2006.173.23:36:28.59#ibcon#read 6, iclass 24, count 0 2006.173.23:36:28.59#ibcon#end of sib2, iclass 24, count 0 2006.173.23:36:28.59#ibcon#*mode == 0, iclass 24, count 0 2006.173.23:36:28.59#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.23:36:28.59#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.23:36:28.59#ibcon#*before write, iclass 24, count 0 2006.173.23:36:28.59#ibcon#enter sib2, iclass 24, count 0 2006.173.23:36:28.59#ibcon#flushed, iclass 24, count 0 2006.173.23:36:28.59#ibcon#about to write, iclass 24, count 0 2006.173.23:36:28.59#ibcon#wrote, iclass 24, count 0 2006.173.23:36:28.59#ibcon#about to read 3, iclass 24, count 0 2006.173.23:36:28.63#ibcon#read 3, iclass 24, count 0 2006.173.23:36:28.63#ibcon#about to read 4, iclass 24, count 0 2006.173.23:36:28.63#ibcon#read 4, iclass 24, count 0 2006.173.23:36:28.63#ibcon#about to read 5, iclass 24, count 0 2006.173.23:36:28.63#ibcon#read 5, iclass 24, count 0 2006.173.23:36:28.63#ibcon#about to read 6, iclass 24, count 0 2006.173.23:36:28.63#ibcon#read 6, iclass 24, count 0 2006.173.23:36:28.63#ibcon#end of sib2, iclass 24, count 0 2006.173.23:36:28.63#ibcon#*after write, iclass 24, count 0 2006.173.23:36:28.63#ibcon#*before return 0, iclass 24, count 0 2006.173.23:36:28.63#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.23:36:28.63#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.23:36:28.63#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.23:36:28.63#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.23:36:28.63$vck44/va=8,4 2006.173.23:36:28.63#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.173.23:36:28.63#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.173.23:36:28.63#ibcon#ireg 11 cls_cnt 2 2006.173.23:36:28.63#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.23:36:28.69#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.173.23:36:28.69#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.23:36:28.69#ibcon#enter wrdev, iclass 26, count 2 2006.173.23:36:28.69#ibcon#first serial, iclass 26, count 2 2006.173.23:36:28.69#ibcon#enter sib2, iclass 26, count 2 2006.173.23:36:28.69#ibcon#flushed, iclass 26, count 2 2006.173.23:36:28.69#ibcon#about to write, iclass 26, count 2 2006.173.23:36:28.69#ibcon#wrote, iclass 26, count 2 2006.173.23:36:28.69#ibcon#about to read 3, iclass 26, count 2 2006.173.23:36:28.71#ibcon#read 3, iclass 26, count 2 2006.173.23:36:28.71#ibcon#about to read 4, iclass 26, count 2 2006.173.23:36:28.71#ibcon#read 4, iclass 26, count 2 2006.173.23:36:28.71#ibcon#about to read 5, iclass 26, count 2 2006.173.23:36:28.71#ibcon#read 5, iclass 26, count 2 2006.173.23:36:28.71#ibcon#about to read 6, iclass 26, count 2 2006.173.23:36:28.71#ibcon#read 6, iclass 26, count 2 2006.173.23:36:28.71#ibcon#end of sib2, iclass 26, count 2 2006.173.23:36:28.71#ibcon#*mode == 0, iclass 26, count 2 2006.173.23:36:28.71#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.173.23:36:28.71#ibcon#[25=AT08-04\r\n] 2006.173.23:36:28.71#ibcon#*before write, iclass 26, count 2 2006.173.23:36:28.71#ibcon#enter sib2, iclass 26, count 2 2006.173.23:36:28.71#ibcon#flushed, iclass 26, count 2 2006.173.23:36:28.71#ibcon#about to write, iclass 26, count 2 2006.173.23:36:28.71#ibcon#wrote, iclass 26, count 2 2006.173.23:36:28.71#ibcon#about to read 3, iclass 26, count 2 2006.173.23:36:28.74#ibcon#read 3, iclass 26, count 2 2006.173.23:36:28.74#ibcon#about to read 4, iclass 26, count 2 2006.173.23:36:28.74#ibcon#read 4, iclass 26, count 2 2006.173.23:36:28.74#ibcon#about to read 5, iclass 26, count 2 2006.173.23:36:28.74#ibcon#read 5, iclass 26, count 2 2006.173.23:36:28.74#ibcon#about to read 6, iclass 26, count 2 2006.173.23:36:28.74#ibcon#read 6, iclass 26, count 2 2006.173.23:36:28.74#ibcon#end of sib2, iclass 26, count 2 2006.173.23:36:28.74#ibcon#*after write, iclass 26, count 2 2006.173.23:36:28.74#ibcon#*before return 0, iclass 26, count 2 2006.173.23:36:28.74#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.173.23:36:28.74#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.173.23:36:28.74#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.173.23:36:28.74#ibcon#ireg 7 cls_cnt 0 2006.173.23:36:28.74#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.23:36:28.86#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.173.23:36:28.86#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.23:36:28.86#ibcon#enter wrdev, iclass 26, count 0 2006.173.23:36:28.86#ibcon#first serial, iclass 26, count 0 2006.173.23:36:28.86#ibcon#enter sib2, iclass 26, count 0 2006.173.23:36:28.86#ibcon#flushed, iclass 26, count 0 2006.173.23:36:28.86#ibcon#about to write, iclass 26, count 0 2006.173.23:36:28.86#ibcon#wrote, iclass 26, count 0 2006.173.23:36:28.86#ibcon#about to read 3, iclass 26, count 0 2006.173.23:36:28.88#ibcon#read 3, iclass 26, count 0 2006.173.23:36:28.88#ibcon#about to read 4, iclass 26, count 0 2006.173.23:36:28.88#ibcon#read 4, iclass 26, count 0 2006.173.23:36:28.88#ibcon#about to read 5, iclass 26, count 0 2006.173.23:36:28.88#ibcon#read 5, iclass 26, count 0 2006.173.23:36:28.88#ibcon#about to read 6, iclass 26, count 0 2006.173.23:36:28.88#ibcon#read 6, iclass 26, count 0 2006.173.23:36:28.88#ibcon#end of sib2, iclass 26, count 0 2006.173.23:36:28.88#ibcon#*mode == 0, iclass 26, count 0 2006.173.23:36:28.88#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.23:36:28.88#ibcon#[25=USB\r\n] 2006.173.23:36:28.88#ibcon#*before write, iclass 26, count 0 2006.173.23:36:28.88#ibcon#enter sib2, iclass 26, count 0 2006.173.23:36:28.88#ibcon#flushed, iclass 26, count 0 2006.173.23:36:28.88#ibcon#about to write, iclass 26, count 0 2006.173.23:36:28.88#ibcon#wrote, iclass 26, count 0 2006.173.23:36:28.88#ibcon#about to read 3, iclass 26, count 0 2006.173.23:36:28.91#ibcon#read 3, iclass 26, count 0 2006.173.23:36:28.91#ibcon#about to read 4, iclass 26, count 0 2006.173.23:36:28.91#ibcon#read 4, iclass 26, count 0 2006.173.23:36:28.91#ibcon#about to read 5, iclass 26, count 0 2006.173.23:36:28.91#ibcon#read 5, iclass 26, count 0 2006.173.23:36:28.91#ibcon#about to read 6, iclass 26, count 0 2006.173.23:36:28.91#ibcon#read 6, iclass 26, count 0 2006.173.23:36:28.91#ibcon#end of sib2, iclass 26, count 0 2006.173.23:36:28.91#ibcon#*after write, iclass 26, count 0 2006.173.23:36:28.91#ibcon#*before return 0, iclass 26, count 0 2006.173.23:36:28.91#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.173.23:36:28.91#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.173.23:36:28.91#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.23:36:28.91#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.23:36:28.91$vck44/vblo=1,629.99 2006.173.23:36:28.91#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.173.23:36:28.91#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.173.23:36:28.91#ibcon#ireg 17 cls_cnt 0 2006.173.23:36:28.91#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.23:36:28.91#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.173.23:36:28.91#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.23:36:28.91#ibcon#enter wrdev, iclass 28, count 0 2006.173.23:36:28.91#ibcon#first serial, iclass 28, count 0 2006.173.23:36:28.91#ibcon#enter sib2, iclass 28, count 0 2006.173.23:36:28.91#ibcon#flushed, iclass 28, count 0 2006.173.23:36:28.91#ibcon#about to write, iclass 28, count 0 2006.173.23:36:28.91#ibcon#wrote, iclass 28, count 0 2006.173.23:36:28.91#ibcon#about to read 3, iclass 28, count 0 2006.173.23:36:28.93#ibcon#read 3, iclass 28, count 0 2006.173.23:36:28.93#ibcon#about to read 4, iclass 28, count 0 2006.173.23:36:28.93#ibcon#read 4, iclass 28, count 0 2006.173.23:36:28.93#ibcon#about to read 5, iclass 28, count 0 2006.173.23:36:28.93#ibcon#read 5, iclass 28, count 0 2006.173.23:36:28.93#ibcon#about to read 6, iclass 28, count 0 2006.173.23:36:28.93#ibcon#read 6, iclass 28, count 0 2006.173.23:36:28.93#ibcon#end of sib2, iclass 28, count 0 2006.173.23:36:28.93#ibcon#*mode == 0, iclass 28, count 0 2006.173.23:36:28.93#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.23:36:28.93#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.23:36:28.93#ibcon#*before write, iclass 28, count 0 2006.173.23:36:28.93#ibcon#enter sib2, iclass 28, count 0 2006.173.23:36:28.93#ibcon#flushed, iclass 28, count 0 2006.173.23:36:28.93#ibcon#about to write, iclass 28, count 0 2006.173.23:36:28.93#ibcon#wrote, iclass 28, count 0 2006.173.23:36:28.93#ibcon#about to read 3, iclass 28, count 0 2006.173.23:36:28.97#ibcon#read 3, iclass 28, count 0 2006.173.23:36:28.97#ibcon#about to read 4, iclass 28, count 0 2006.173.23:36:28.97#ibcon#read 4, iclass 28, count 0 2006.173.23:36:28.97#ibcon#about to read 5, iclass 28, count 0 2006.173.23:36:28.97#ibcon#read 5, iclass 28, count 0 2006.173.23:36:28.97#ibcon#about to read 6, iclass 28, count 0 2006.173.23:36:28.97#ibcon#read 6, iclass 28, count 0 2006.173.23:36:28.97#ibcon#end of sib2, iclass 28, count 0 2006.173.23:36:28.97#ibcon#*after write, iclass 28, count 0 2006.173.23:36:28.97#ibcon#*before return 0, iclass 28, count 0 2006.173.23:36:28.97#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.173.23:36:28.97#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.173.23:36:28.97#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.23:36:28.97#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.23:36:28.97$vck44/vb=1,4 2006.173.23:36:28.97#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.173.23:36:28.97#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.173.23:36:28.97#ibcon#ireg 11 cls_cnt 2 2006.173.23:36:28.97#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.23:36:28.97#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.173.23:36:28.97#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.23:36:28.97#ibcon#enter wrdev, iclass 30, count 2 2006.173.23:36:28.97#ibcon#first serial, iclass 30, count 2 2006.173.23:36:28.97#ibcon#enter sib2, iclass 30, count 2 2006.173.23:36:28.97#ibcon#flushed, iclass 30, count 2 2006.173.23:36:28.97#ibcon#about to write, iclass 30, count 2 2006.173.23:36:28.97#ibcon#wrote, iclass 30, count 2 2006.173.23:36:28.97#ibcon#about to read 3, iclass 30, count 2 2006.173.23:36:28.99#ibcon#read 3, iclass 30, count 2 2006.173.23:36:28.99#ibcon#about to read 4, iclass 30, count 2 2006.173.23:36:28.99#ibcon#read 4, iclass 30, count 2 2006.173.23:36:28.99#ibcon#about to read 5, iclass 30, count 2 2006.173.23:36:28.99#ibcon#read 5, iclass 30, count 2 2006.173.23:36:28.99#ibcon#about to read 6, iclass 30, count 2 2006.173.23:36:28.99#ibcon#read 6, iclass 30, count 2 2006.173.23:36:28.99#ibcon#end of sib2, iclass 30, count 2 2006.173.23:36:28.99#ibcon#*mode == 0, iclass 30, count 2 2006.173.23:36:28.99#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.173.23:36:28.99#ibcon#[27=AT01-04\r\n] 2006.173.23:36:28.99#ibcon#*before write, iclass 30, count 2 2006.173.23:36:28.99#ibcon#enter sib2, iclass 30, count 2 2006.173.23:36:28.99#ibcon#flushed, iclass 30, count 2 2006.173.23:36:28.99#ibcon#about to write, iclass 30, count 2 2006.173.23:36:28.99#ibcon#wrote, iclass 30, count 2 2006.173.23:36:28.99#ibcon#about to read 3, iclass 30, count 2 2006.173.23:36:29.02#ibcon#read 3, iclass 30, count 2 2006.173.23:36:29.02#ibcon#about to read 4, iclass 30, count 2 2006.173.23:36:29.02#ibcon#read 4, iclass 30, count 2 2006.173.23:36:29.02#ibcon#about to read 5, iclass 30, count 2 2006.173.23:36:29.02#ibcon#read 5, iclass 30, count 2 2006.173.23:36:29.02#ibcon#about to read 6, iclass 30, count 2 2006.173.23:36:29.02#ibcon#read 6, iclass 30, count 2 2006.173.23:36:29.02#ibcon#end of sib2, iclass 30, count 2 2006.173.23:36:29.02#ibcon#*after write, iclass 30, count 2 2006.173.23:36:29.02#ibcon#*before return 0, iclass 30, count 2 2006.173.23:36:29.02#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.173.23:36:29.02#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.173.23:36:29.02#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.173.23:36:29.02#ibcon#ireg 7 cls_cnt 0 2006.173.23:36:29.02#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.23:36:29.14#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.173.23:36:29.14#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.23:36:29.14#ibcon#enter wrdev, iclass 30, count 0 2006.173.23:36:29.14#ibcon#first serial, iclass 30, count 0 2006.173.23:36:29.14#ibcon#enter sib2, iclass 30, count 0 2006.173.23:36:29.14#ibcon#flushed, iclass 30, count 0 2006.173.23:36:29.14#ibcon#about to write, iclass 30, count 0 2006.173.23:36:29.14#ibcon#wrote, iclass 30, count 0 2006.173.23:36:29.14#ibcon#about to read 3, iclass 30, count 0 2006.173.23:36:29.16#ibcon#read 3, iclass 30, count 0 2006.173.23:36:29.16#ibcon#about to read 4, iclass 30, count 0 2006.173.23:36:29.16#ibcon#read 4, iclass 30, count 0 2006.173.23:36:29.16#ibcon#about to read 5, iclass 30, count 0 2006.173.23:36:29.16#ibcon#read 5, iclass 30, count 0 2006.173.23:36:29.16#ibcon#about to read 6, iclass 30, count 0 2006.173.23:36:29.16#ibcon#read 6, iclass 30, count 0 2006.173.23:36:29.16#ibcon#end of sib2, iclass 30, count 0 2006.173.23:36:29.16#ibcon#*mode == 0, iclass 30, count 0 2006.173.23:36:29.16#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.23:36:29.16#ibcon#[27=USB\r\n] 2006.173.23:36:29.16#ibcon#*before write, iclass 30, count 0 2006.173.23:36:29.16#ibcon#enter sib2, iclass 30, count 0 2006.173.23:36:29.16#ibcon#flushed, iclass 30, count 0 2006.173.23:36:29.16#ibcon#about to write, iclass 30, count 0 2006.173.23:36:29.16#ibcon#wrote, iclass 30, count 0 2006.173.23:36:29.16#ibcon#about to read 3, iclass 30, count 0 2006.173.23:36:29.19#ibcon#read 3, iclass 30, count 0 2006.173.23:36:29.19#ibcon#about to read 4, iclass 30, count 0 2006.173.23:36:29.19#ibcon#read 4, iclass 30, count 0 2006.173.23:36:29.19#ibcon#about to read 5, iclass 30, count 0 2006.173.23:36:29.19#ibcon#read 5, iclass 30, count 0 2006.173.23:36:29.19#ibcon#about to read 6, iclass 30, count 0 2006.173.23:36:29.19#ibcon#read 6, iclass 30, count 0 2006.173.23:36:29.19#ibcon#end of sib2, iclass 30, count 0 2006.173.23:36:29.19#ibcon#*after write, iclass 30, count 0 2006.173.23:36:29.19#ibcon#*before return 0, iclass 30, count 0 2006.173.23:36:29.19#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.173.23:36:29.19#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.173.23:36:29.19#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.23:36:29.19#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.23:36:29.19$vck44/vblo=2,634.99 2006.173.23:36:29.19#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.173.23:36:29.19#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.173.23:36:29.19#ibcon#ireg 17 cls_cnt 0 2006.173.23:36:29.19#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.23:36:29.19#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.173.23:36:29.19#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.23:36:29.19#ibcon#enter wrdev, iclass 32, count 0 2006.173.23:36:29.19#ibcon#first serial, iclass 32, count 0 2006.173.23:36:29.19#ibcon#enter sib2, iclass 32, count 0 2006.173.23:36:29.19#ibcon#flushed, iclass 32, count 0 2006.173.23:36:29.19#ibcon#about to write, iclass 32, count 0 2006.173.23:36:29.19#ibcon#wrote, iclass 32, count 0 2006.173.23:36:29.19#ibcon#about to read 3, iclass 32, count 0 2006.173.23:36:29.21#ibcon#read 3, iclass 32, count 0 2006.173.23:36:29.21#ibcon#about to read 4, iclass 32, count 0 2006.173.23:36:29.21#ibcon#read 4, iclass 32, count 0 2006.173.23:36:29.21#ibcon#about to read 5, iclass 32, count 0 2006.173.23:36:29.21#ibcon#read 5, iclass 32, count 0 2006.173.23:36:29.21#ibcon#about to read 6, iclass 32, count 0 2006.173.23:36:29.21#ibcon#read 6, iclass 32, count 0 2006.173.23:36:29.21#ibcon#end of sib2, iclass 32, count 0 2006.173.23:36:29.21#ibcon#*mode == 0, iclass 32, count 0 2006.173.23:36:29.21#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.23:36:29.21#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.23:36:29.21#ibcon#*before write, iclass 32, count 0 2006.173.23:36:29.21#ibcon#enter sib2, iclass 32, count 0 2006.173.23:36:29.21#ibcon#flushed, iclass 32, count 0 2006.173.23:36:29.21#ibcon#about to write, iclass 32, count 0 2006.173.23:36:29.21#ibcon#wrote, iclass 32, count 0 2006.173.23:36:29.21#ibcon#about to read 3, iclass 32, count 0 2006.173.23:36:29.25#ibcon#read 3, iclass 32, count 0 2006.173.23:36:29.25#ibcon#about to read 4, iclass 32, count 0 2006.173.23:36:29.25#ibcon#read 4, iclass 32, count 0 2006.173.23:36:29.25#ibcon#about to read 5, iclass 32, count 0 2006.173.23:36:29.25#ibcon#read 5, iclass 32, count 0 2006.173.23:36:29.25#ibcon#about to read 6, iclass 32, count 0 2006.173.23:36:29.25#ibcon#read 6, iclass 32, count 0 2006.173.23:36:29.25#ibcon#end of sib2, iclass 32, count 0 2006.173.23:36:29.25#ibcon#*after write, iclass 32, count 0 2006.173.23:36:29.25#ibcon#*before return 0, iclass 32, count 0 2006.173.23:36:29.25#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.173.23:36:29.25#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.173.23:36:29.25#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.23:36:29.25#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.23:36:29.25$vck44/vb=2,4 2006.173.23:36:29.25#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.173.23:36:29.25#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.173.23:36:29.25#ibcon#ireg 11 cls_cnt 2 2006.173.23:36:29.25#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.23:36:29.31#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.173.23:36:29.31#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.23:36:29.31#ibcon#enter wrdev, iclass 34, count 2 2006.173.23:36:29.31#ibcon#first serial, iclass 34, count 2 2006.173.23:36:29.31#ibcon#enter sib2, iclass 34, count 2 2006.173.23:36:29.31#ibcon#flushed, iclass 34, count 2 2006.173.23:36:29.31#ibcon#about to write, iclass 34, count 2 2006.173.23:36:29.31#ibcon#wrote, iclass 34, count 2 2006.173.23:36:29.31#ibcon#about to read 3, iclass 34, count 2 2006.173.23:36:29.33#ibcon#read 3, iclass 34, count 2 2006.173.23:36:29.33#ibcon#about to read 4, iclass 34, count 2 2006.173.23:36:29.33#ibcon#read 4, iclass 34, count 2 2006.173.23:36:29.33#ibcon#about to read 5, iclass 34, count 2 2006.173.23:36:29.33#ibcon#read 5, iclass 34, count 2 2006.173.23:36:29.33#ibcon#about to read 6, iclass 34, count 2 2006.173.23:36:29.33#ibcon#read 6, iclass 34, count 2 2006.173.23:36:29.33#ibcon#end of sib2, iclass 34, count 2 2006.173.23:36:29.33#ibcon#*mode == 0, iclass 34, count 2 2006.173.23:36:29.33#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.173.23:36:29.33#ibcon#[27=AT02-04\r\n] 2006.173.23:36:29.33#ibcon#*before write, iclass 34, count 2 2006.173.23:36:29.33#ibcon#enter sib2, iclass 34, count 2 2006.173.23:36:29.33#ibcon#flushed, iclass 34, count 2 2006.173.23:36:29.33#ibcon#about to write, iclass 34, count 2 2006.173.23:36:29.33#ibcon#wrote, iclass 34, count 2 2006.173.23:36:29.33#ibcon#about to read 3, iclass 34, count 2 2006.173.23:36:29.36#ibcon#read 3, iclass 34, count 2 2006.173.23:36:29.36#ibcon#about to read 4, iclass 34, count 2 2006.173.23:36:29.36#ibcon#read 4, iclass 34, count 2 2006.173.23:36:29.36#ibcon#about to read 5, iclass 34, count 2 2006.173.23:36:29.36#ibcon#read 5, iclass 34, count 2 2006.173.23:36:29.36#ibcon#about to read 6, iclass 34, count 2 2006.173.23:36:29.36#ibcon#read 6, iclass 34, count 2 2006.173.23:36:29.36#ibcon#end of sib2, iclass 34, count 2 2006.173.23:36:29.36#ibcon#*after write, iclass 34, count 2 2006.173.23:36:29.36#ibcon#*before return 0, iclass 34, count 2 2006.173.23:36:29.36#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.173.23:36:29.36#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.173.23:36:29.36#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.173.23:36:29.36#ibcon#ireg 7 cls_cnt 0 2006.173.23:36:29.36#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.23:36:29.48#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.173.23:36:29.48#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.23:36:29.48#ibcon#enter wrdev, iclass 34, count 0 2006.173.23:36:29.48#ibcon#first serial, iclass 34, count 0 2006.173.23:36:29.48#ibcon#enter sib2, iclass 34, count 0 2006.173.23:36:29.48#ibcon#flushed, iclass 34, count 0 2006.173.23:36:29.48#ibcon#about to write, iclass 34, count 0 2006.173.23:36:29.48#ibcon#wrote, iclass 34, count 0 2006.173.23:36:29.48#ibcon#about to read 3, iclass 34, count 0 2006.173.23:36:29.50#ibcon#read 3, iclass 34, count 0 2006.173.23:36:29.50#ibcon#about to read 4, iclass 34, count 0 2006.173.23:36:29.50#ibcon#read 4, iclass 34, count 0 2006.173.23:36:29.50#ibcon#about to read 5, iclass 34, count 0 2006.173.23:36:29.50#ibcon#read 5, iclass 34, count 0 2006.173.23:36:29.50#ibcon#about to read 6, iclass 34, count 0 2006.173.23:36:29.50#ibcon#read 6, iclass 34, count 0 2006.173.23:36:29.50#ibcon#end of sib2, iclass 34, count 0 2006.173.23:36:29.50#ibcon#*mode == 0, iclass 34, count 0 2006.173.23:36:29.50#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.23:36:29.50#ibcon#[27=USB\r\n] 2006.173.23:36:29.50#ibcon#*before write, iclass 34, count 0 2006.173.23:36:29.50#ibcon#enter sib2, iclass 34, count 0 2006.173.23:36:29.50#ibcon#flushed, iclass 34, count 0 2006.173.23:36:29.50#ibcon#about to write, iclass 34, count 0 2006.173.23:36:29.50#ibcon#wrote, iclass 34, count 0 2006.173.23:36:29.50#ibcon#about to read 3, iclass 34, count 0 2006.173.23:36:29.53#ibcon#read 3, iclass 34, count 0 2006.173.23:36:29.53#ibcon#about to read 4, iclass 34, count 0 2006.173.23:36:29.53#ibcon#read 4, iclass 34, count 0 2006.173.23:36:29.53#ibcon#about to read 5, iclass 34, count 0 2006.173.23:36:29.53#ibcon#read 5, iclass 34, count 0 2006.173.23:36:29.53#ibcon#about to read 6, iclass 34, count 0 2006.173.23:36:29.53#ibcon#read 6, iclass 34, count 0 2006.173.23:36:29.53#ibcon#end of sib2, iclass 34, count 0 2006.173.23:36:29.53#ibcon#*after write, iclass 34, count 0 2006.173.23:36:29.53#ibcon#*before return 0, iclass 34, count 0 2006.173.23:36:29.53#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.173.23:36:29.53#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.173.23:36:29.53#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.23:36:29.53#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.23:36:29.53$vck44/vblo=3,649.99 2006.173.23:36:29.53#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.173.23:36:29.53#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.173.23:36:29.53#ibcon#ireg 17 cls_cnt 0 2006.173.23:36:29.53#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.23:36:29.53#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.173.23:36:29.53#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.23:36:29.53#ibcon#enter wrdev, iclass 36, count 0 2006.173.23:36:29.53#ibcon#first serial, iclass 36, count 0 2006.173.23:36:29.53#ibcon#enter sib2, iclass 36, count 0 2006.173.23:36:29.53#ibcon#flushed, iclass 36, count 0 2006.173.23:36:29.53#ibcon#about to write, iclass 36, count 0 2006.173.23:36:29.53#ibcon#wrote, iclass 36, count 0 2006.173.23:36:29.53#ibcon#about to read 3, iclass 36, count 0 2006.173.23:36:29.55#ibcon#read 3, iclass 36, count 0 2006.173.23:36:29.55#ibcon#about to read 4, iclass 36, count 0 2006.173.23:36:29.55#ibcon#read 4, iclass 36, count 0 2006.173.23:36:29.55#ibcon#about to read 5, iclass 36, count 0 2006.173.23:36:29.55#ibcon#read 5, iclass 36, count 0 2006.173.23:36:29.55#ibcon#about to read 6, iclass 36, count 0 2006.173.23:36:29.55#ibcon#read 6, iclass 36, count 0 2006.173.23:36:29.55#ibcon#end of sib2, iclass 36, count 0 2006.173.23:36:29.55#ibcon#*mode == 0, iclass 36, count 0 2006.173.23:36:29.55#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.23:36:29.55#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.23:36:29.55#ibcon#*before write, iclass 36, count 0 2006.173.23:36:29.55#ibcon#enter sib2, iclass 36, count 0 2006.173.23:36:29.55#ibcon#flushed, iclass 36, count 0 2006.173.23:36:29.55#ibcon#about to write, iclass 36, count 0 2006.173.23:36:29.55#ibcon#wrote, iclass 36, count 0 2006.173.23:36:29.55#ibcon#about to read 3, iclass 36, count 0 2006.173.23:36:29.59#ibcon#read 3, iclass 36, count 0 2006.173.23:36:29.59#ibcon#about to read 4, iclass 36, count 0 2006.173.23:36:29.59#ibcon#read 4, iclass 36, count 0 2006.173.23:36:29.59#ibcon#about to read 5, iclass 36, count 0 2006.173.23:36:29.59#ibcon#read 5, iclass 36, count 0 2006.173.23:36:29.59#ibcon#about to read 6, iclass 36, count 0 2006.173.23:36:29.59#ibcon#read 6, iclass 36, count 0 2006.173.23:36:29.59#ibcon#end of sib2, iclass 36, count 0 2006.173.23:36:29.59#ibcon#*after write, iclass 36, count 0 2006.173.23:36:29.59#ibcon#*before return 0, iclass 36, count 0 2006.173.23:36:29.59#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.173.23:36:29.59#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.173.23:36:29.59#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.23:36:29.59#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.23:36:29.59$vck44/vb=3,4 2006.173.23:36:29.59#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.173.23:36:29.59#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.173.23:36:29.59#ibcon#ireg 11 cls_cnt 2 2006.173.23:36:29.59#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.23:36:29.65#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.173.23:36:29.65#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.23:36:29.65#ibcon#enter wrdev, iclass 38, count 2 2006.173.23:36:29.65#ibcon#first serial, iclass 38, count 2 2006.173.23:36:29.65#ibcon#enter sib2, iclass 38, count 2 2006.173.23:36:29.65#ibcon#flushed, iclass 38, count 2 2006.173.23:36:29.65#ibcon#about to write, iclass 38, count 2 2006.173.23:36:29.65#ibcon#wrote, iclass 38, count 2 2006.173.23:36:29.65#ibcon#about to read 3, iclass 38, count 2 2006.173.23:36:29.67#ibcon#read 3, iclass 38, count 2 2006.173.23:36:29.67#ibcon#about to read 4, iclass 38, count 2 2006.173.23:36:29.67#ibcon#read 4, iclass 38, count 2 2006.173.23:36:29.67#ibcon#about to read 5, iclass 38, count 2 2006.173.23:36:29.67#ibcon#read 5, iclass 38, count 2 2006.173.23:36:29.67#ibcon#about to read 6, iclass 38, count 2 2006.173.23:36:29.67#ibcon#read 6, iclass 38, count 2 2006.173.23:36:29.67#ibcon#end of sib2, iclass 38, count 2 2006.173.23:36:29.67#ibcon#*mode == 0, iclass 38, count 2 2006.173.23:36:29.67#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.173.23:36:29.67#ibcon#[27=AT03-04\r\n] 2006.173.23:36:29.67#ibcon#*before write, iclass 38, count 2 2006.173.23:36:29.67#ibcon#enter sib2, iclass 38, count 2 2006.173.23:36:29.67#ibcon#flushed, iclass 38, count 2 2006.173.23:36:29.67#ibcon#about to write, iclass 38, count 2 2006.173.23:36:29.67#ibcon#wrote, iclass 38, count 2 2006.173.23:36:29.67#ibcon#about to read 3, iclass 38, count 2 2006.173.23:36:29.70#ibcon#read 3, iclass 38, count 2 2006.173.23:36:29.70#ibcon#about to read 4, iclass 38, count 2 2006.173.23:36:29.70#ibcon#read 4, iclass 38, count 2 2006.173.23:36:29.70#ibcon#about to read 5, iclass 38, count 2 2006.173.23:36:29.70#ibcon#read 5, iclass 38, count 2 2006.173.23:36:29.70#ibcon#about to read 6, iclass 38, count 2 2006.173.23:36:29.70#ibcon#read 6, iclass 38, count 2 2006.173.23:36:29.70#ibcon#end of sib2, iclass 38, count 2 2006.173.23:36:29.70#ibcon#*after write, iclass 38, count 2 2006.173.23:36:29.70#ibcon#*before return 0, iclass 38, count 2 2006.173.23:36:29.70#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.173.23:36:29.70#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.173.23:36:29.70#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.173.23:36:29.70#ibcon#ireg 7 cls_cnt 0 2006.173.23:36:29.70#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.23:36:29.82#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.173.23:36:29.82#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.23:36:29.82#ibcon#enter wrdev, iclass 38, count 0 2006.173.23:36:29.82#ibcon#first serial, iclass 38, count 0 2006.173.23:36:29.82#ibcon#enter sib2, iclass 38, count 0 2006.173.23:36:29.82#ibcon#flushed, iclass 38, count 0 2006.173.23:36:29.82#ibcon#about to write, iclass 38, count 0 2006.173.23:36:29.82#ibcon#wrote, iclass 38, count 0 2006.173.23:36:29.82#ibcon#about to read 3, iclass 38, count 0 2006.173.23:36:29.84#ibcon#read 3, iclass 38, count 0 2006.173.23:36:29.84#ibcon#about to read 4, iclass 38, count 0 2006.173.23:36:29.84#ibcon#read 4, iclass 38, count 0 2006.173.23:36:29.84#ibcon#about to read 5, iclass 38, count 0 2006.173.23:36:29.84#ibcon#read 5, iclass 38, count 0 2006.173.23:36:29.84#ibcon#about to read 6, iclass 38, count 0 2006.173.23:36:29.84#ibcon#read 6, iclass 38, count 0 2006.173.23:36:29.84#ibcon#end of sib2, iclass 38, count 0 2006.173.23:36:29.84#ibcon#*mode == 0, iclass 38, count 0 2006.173.23:36:29.84#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.23:36:29.84#ibcon#[27=USB\r\n] 2006.173.23:36:29.84#ibcon#*before write, iclass 38, count 0 2006.173.23:36:29.84#ibcon#enter sib2, iclass 38, count 0 2006.173.23:36:29.84#ibcon#flushed, iclass 38, count 0 2006.173.23:36:29.84#ibcon#about to write, iclass 38, count 0 2006.173.23:36:29.84#ibcon#wrote, iclass 38, count 0 2006.173.23:36:29.84#ibcon#about to read 3, iclass 38, count 0 2006.173.23:36:29.87#ibcon#read 3, iclass 38, count 0 2006.173.23:36:29.87#ibcon#about to read 4, iclass 38, count 0 2006.173.23:36:29.87#ibcon#read 4, iclass 38, count 0 2006.173.23:36:29.87#ibcon#about to read 5, iclass 38, count 0 2006.173.23:36:29.87#ibcon#read 5, iclass 38, count 0 2006.173.23:36:29.87#ibcon#about to read 6, iclass 38, count 0 2006.173.23:36:29.87#ibcon#read 6, iclass 38, count 0 2006.173.23:36:29.87#ibcon#end of sib2, iclass 38, count 0 2006.173.23:36:29.87#ibcon#*after write, iclass 38, count 0 2006.173.23:36:29.87#ibcon#*before return 0, iclass 38, count 0 2006.173.23:36:29.87#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.173.23:36:29.87#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.173.23:36:29.87#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.23:36:29.87#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.23:36:29.87$vck44/vblo=4,679.99 2006.173.23:36:29.87#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.23:36:29.87#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.23:36:29.87#ibcon#ireg 17 cls_cnt 0 2006.173.23:36:29.87#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.23:36:29.87#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.23:36:29.87#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.23:36:29.87#ibcon#enter wrdev, iclass 40, count 0 2006.173.23:36:29.87#ibcon#first serial, iclass 40, count 0 2006.173.23:36:29.87#ibcon#enter sib2, iclass 40, count 0 2006.173.23:36:29.87#ibcon#flushed, iclass 40, count 0 2006.173.23:36:29.87#ibcon#about to write, iclass 40, count 0 2006.173.23:36:29.87#ibcon#wrote, iclass 40, count 0 2006.173.23:36:29.87#ibcon#about to read 3, iclass 40, count 0 2006.173.23:36:29.89#ibcon#read 3, iclass 40, count 0 2006.173.23:36:29.89#ibcon#about to read 4, iclass 40, count 0 2006.173.23:36:29.89#ibcon#read 4, iclass 40, count 0 2006.173.23:36:29.89#ibcon#about to read 5, iclass 40, count 0 2006.173.23:36:29.89#ibcon#read 5, iclass 40, count 0 2006.173.23:36:29.89#ibcon#about to read 6, iclass 40, count 0 2006.173.23:36:29.89#ibcon#read 6, iclass 40, count 0 2006.173.23:36:29.89#ibcon#end of sib2, iclass 40, count 0 2006.173.23:36:29.89#ibcon#*mode == 0, iclass 40, count 0 2006.173.23:36:29.89#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.23:36:29.89#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.23:36:29.89#ibcon#*before write, iclass 40, count 0 2006.173.23:36:29.89#ibcon#enter sib2, iclass 40, count 0 2006.173.23:36:29.89#ibcon#flushed, iclass 40, count 0 2006.173.23:36:29.89#ibcon#about to write, iclass 40, count 0 2006.173.23:36:29.89#ibcon#wrote, iclass 40, count 0 2006.173.23:36:29.89#ibcon#about to read 3, iclass 40, count 0 2006.173.23:36:29.93#ibcon#read 3, iclass 40, count 0 2006.173.23:36:29.93#ibcon#about to read 4, iclass 40, count 0 2006.173.23:36:29.93#ibcon#read 4, iclass 40, count 0 2006.173.23:36:29.93#ibcon#about to read 5, iclass 40, count 0 2006.173.23:36:29.93#ibcon#read 5, iclass 40, count 0 2006.173.23:36:29.93#ibcon#about to read 6, iclass 40, count 0 2006.173.23:36:29.93#ibcon#read 6, iclass 40, count 0 2006.173.23:36:29.93#ibcon#end of sib2, iclass 40, count 0 2006.173.23:36:29.93#ibcon#*after write, iclass 40, count 0 2006.173.23:36:29.93#ibcon#*before return 0, iclass 40, count 0 2006.173.23:36:29.93#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.23:36:29.93#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.23:36:29.93#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.23:36:29.93#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.23:36:29.93$vck44/vb=4,4 2006.173.23:36:29.93#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.173.23:36:29.93#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.173.23:36:29.93#ibcon#ireg 11 cls_cnt 2 2006.173.23:36:29.93#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.23:36:29.99#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.173.23:36:29.99#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.23:36:29.99#ibcon#enter wrdev, iclass 4, count 2 2006.173.23:36:29.99#ibcon#first serial, iclass 4, count 2 2006.173.23:36:29.99#ibcon#enter sib2, iclass 4, count 2 2006.173.23:36:29.99#ibcon#flushed, iclass 4, count 2 2006.173.23:36:29.99#ibcon#about to write, iclass 4, count 2 2006.173.23:36:29.99#ibcon#wrote, iclass 4, count 2 2006.173.23:36:29.99#ibcon#about to read 3, iclass 4, count 2 2006.173.23:36:30.01#ibcon#read 3, iclass 4, count 2 2006.173.23:36:30.01#ibcon#about to read 4, iclass 4, count 2 2006.173.23:36:30.01#ibcon#read 4, iclass 4, count 2 2006.173.23:36:30.01#ibcon#about to read 5, iclass 4, count 2 2006.173.23:36:30.01#ibcon#read 5, iclass 4, count 2 2006.173.23:36:30.01#ibcon#about to read 6, iclass 4, count 2 2006.173.23:36:30.01#ibcon#read 6, iclass 4, count 2 2006.173.23:36:30.01#ibcon#end of sib2, iclass 4, count 2 2006.173.23:36:30.01#ibcon#*mode == 0, iclass 4, count 2 2006.173.23:36:30.01#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.173.23:36:30.01#ibcon#[27=AT04-04\r\n] 2006.173.23:36:30.01#ibcon#*before write, iclass 4, count 2 2006.173.23:36:30.01#ibcon#enter sib2, iclass 4, count 2 2006.173.23:36:30.01#ibcon#flushed, iclass 4, count 2 2006.173.23:36:30.01#ibcon#about to write, iclass 4, count 2 2006.173.23:36:30.01#ibcon#wrote, iclass 4, count 2 2006.173.23:36:30.01#ibcon#about to read 3, iclass 4, count 2 2006.173.23:36:30.04#ibcon#read 3, iclass 4, count 2 2006.173.23:36:30.04#ibcon#about to read 4, iclass 4, count 2 2006.173.23:36:30.04#ibcon#read 4, iclass 4, count 2 2006.173.23:36:30.04#ibcon#about to read 5, iclass 4, count 2 2006.173.23:36:30.04#ibcon#read 5, iclass 4, count 2 2006.173.23:36:30.04#ibcon#about to read 6, iclass 4, count 2 2006.173.23:36:30.04#ibcon#read 6, iclass 4, count 2 2006.173.23:36:30.04#ibcon#end of sib2, iclass 4, count 2 2006.173.23:36:30.04#ibcon#*after write, iclass 4, count 2 2006.173.23:36:30.04#ibcon#*before return 0, iclass 4, count 2 2006.173.23:36:30.04#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.173.23:36:30.04#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.173.23:36:30.04#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.173.23:36:30.04#ibcon#ireg 7 cls_cnt 0 2006.173.23:36:30.04#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.23:36:30.16#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.173.23:36:30.16#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.23:36:30.16#ibcon#enter wrdev, iclass 4, count 0 2006.173.23:36:30.16#ibcon#first serial, iclass 4, count 0 2006.173.23:36:30.16#ibcon#enter sib2, iclass 4, count 0 2006.173.23:36:30.16#ibcon#flushed, iclass 4, count 0 2006.173.23:36:30.16#ibcon#about to write, iclass 4, count 0 2006.173.23:36:30.16#ibcon#wrote, iclass 4, count 0 2006.173.23:36:30.16#ibcon#about to read 3, iclass 4, count 0 2006.173.23:36:30.18#ibcon#read 3, iclass 4, count 0 2006.173.23:36:30.18#ibcon#about to read 4, iclass 4, count 0 2006.173.23:36:30.18#ibcon#read 4, iclass 4, count 0 2006.173.23:36:30.18#ibcon#about to read 5, iclass 4, count 0 2006.173.23:36:30.18#ibcon#read 5, iclass 4, count 0 2006.173.23:36:30.18#ibcon#about to read 6, iclass 4, count 0 2006.173.23:36:30.18#ibcon#read 6, iclass 4, count 0 2006.173.23:36:30.18#ibcon#end of sib2, iclass 4, count 0 2006.173.23:36:30.18#ibcon#*mode == 0, iclass 4, count 0 2006.173.23:36:30.18#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.23:36:30.18#ibcon#[27=USB\r\n] 2006.173.23:36:30.18#ibcon#*before write, iclass 4, count 0 2006.173.23:36:30.18#ibcon#enter sib2, iclass 4, count 0 2006.173.23:36:30.18#ibcon#flushed, iclass 4, count 0 2006.173.23:36:30.18#ibcon#about to write, iclass 4, count 0 2006.173.23:36:30.18#ibcon#wrote, iclass 4, count 0 2006.173.23:36:30.18#ibcon#about to read 3, iclass 4, count 0 2006.173.23:36:30.21#ibcon#read 3, iclass 4, count 0 2006.173.23:36:30.21#ibcon#about to read 4, iclass 4, count 0 2006.173.23:36:30.21#ibcon#read 4, iclass 4, count 0 2006.173.23:36:30.21#ibcon#about to read 5, iclass 4, count 0 2006.173.23:36:30.21#ibcon#read 5, iclass 4, count 0 2006.173.23:36:30.21#ibcon#about to read 6, iclass 4, count 0 2006.173.23:36:30.21#ibcon#read 6, iclass 4, count 0 2006.173.23:36:30.21#ibcon#end of sib2, iclass 4, count 0 2006.173.23:36:30.21#ibcon#*after write, iclass 4, count 0 2006.173.23:36:30.21#ibcon#*before return 0, iclass 4, count 0 2006.173.23:36:30.21#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.173.23:36:30.21#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.173.23:36:30.21#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.23:36:30.21#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.23:36:30.21$vck44/vblo=5,709.99 2006.173.23:36:30.21#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.173.23:36:30.21#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.173.23:36:30.21#ibcon#ireg 17 cls_cnt 0 2006.173.23:36:30.21#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.23:36:30.21#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.173.23:36:30.21#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.23:36:30.21#ibcon#enter wrdev, iclass 6, count 0 2006.173.23:36:30.21#ibcon#first serial, iclass 6, count 0 2006.173.23:36:30.21#ibcon#enter sib2, iclass 6, count 0 2006.173.23:36:30.21#ibcon#flushed, iclass 6, count 0 2006.173.23:36:30.21#ibcon#about to write, iclass 6, count 0 2006.173.23:36:30.21#ibcon#wrote, iclass 6, count 0 2006.173.23:36:30.21#ibcon#about to read 3, iclass 6, count 0 2006.173.23:36:30.23#ibcon#read 3, iclass 6, count 0 2006.173.23:36:30.23#ibcon#about to read 4, iclass 6, count 0 2006.173.23:36:30.23#ibcon#read 4, iclass 6, count 0 2006.173.23:36:30.23#ibcon#about to read 5, iclass 6, count 0 2006.173.23:36:30.23#ibcon#read 5, iclass 6, count 0 2006.173.23:36:30.23#ibcon#about to read 6, iclass 6, count 0 2006.173.23:36:30.23#ibcon#read 6, iclass 6, count 0 2006.173.23:36:30.23#ibcon#end of sib2, iclass 6, count 0 2006.173.23:36:30.23#ibcon#*mode == 0, iclass 6, count 0 2006.173.23:36:30.23#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.23:36:30.23#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.23:36:30.23#ibcon#*before write, iclass 6, count 0 2006.173.23:36:30.23#ibcon#enter sib2, iclass 6, count 0 2006.173.23:36:30.23#ibcon#flushed, iclass 6, count 0 2006.173.23:36:30.23#ibcon#about to write, iclass 6, count 0 2006.173.23:36:30.23#ibcon#wrote, iclass 6, count 0 2006.173.23:36:30.23#ibcon#about to read 3, iclass 6, count 0 2006.173.23:36:30.27#ibcon#read 3, iclass 6, count 0 2006.173.23:36:30.27#ibcon#about to read 4, iclass 6, count 0 2006.173.23:36:30.27#ibcon#read 4, iclass 6, count 0 2006.173.23:36:30.27#ibcon#about to read 5, iclass 6, count 0 2006.173.23:36:30.27#ibcon#read 5, iclass 6, count 0 2006.173.23:36:30.27#ibcon#about to read 6, iclass 6, count 0 2006.173.23:36:30.27#ibcon#read 6, iclass 6, count 0 2006.173.23:36:30.27#ibcon#end of sib2, iclass 6, count 0 2006.173.23:36:30.27#ibcon#*after write, iclass 6, count 0 2006.173.23:36:30.27#ibcon#*before return 0, iclass 6, count 0 2006.173.23:36:30.27#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.173.23:36:30.27#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.173.23:36:30.27#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.23:36:30.27#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.23:36:30.27$vck44/vb=5,4 2006.173.23:36:30.27#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.173.23:36:30.27#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.173.23:36:30.27#ibcon#ireg 11 cls_cnt 2 2006.173.23:36:30.27#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.23:36:30.33#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.173.23:36:30.33#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.23:36:30.33#ibcon#enter wrdev, iclass 10, count 2 2006.173.23:36:30.33#ibcon#first serial, iclass 10, count 2 2006.173.23:36:30.33#ibcon#enter sib2, iclass 10, count 2 2006.173.23:36:30.33#ibcon#flushed, iclass 10, count 2 2006.173.23:36:30.33#ibcon#about to write, iclass 10, count 2 2006.173.23:36:30.33#ibcon#wrote, iclass 10, count 2 2006.173.23:36:30.33#ibcon#about to read 3, iclass 10, count 2 2006.173.23:36:30.35#ibcon#read 3, iclass 10, count 2 2006.173.23:36:30.35#ibcon#about to read 4, iclass 10, count 2 2006.173.23:36:30.35#ibcon#read 4, iclass 10, count 2 2006.173.23:36:30.35#ibcon#about to read 5, iclass 10, count 2 2006.173.23:36:30.35#ibcon#read 5, iclass 10, count 2 2006.173.23:36:30.35#ibcon#about to read 6, iclass 10, count 2 2006.173.23:36:30.35#ibcon#read 6, iclass 10, count 2 2006.173.23:36:30.35#ibcon#end of sib2, iclass 10, count 2 2006.173.23:36:30.35#ibcon#*mode == 0, iclass 10, count 2 2006.173.23:36:30.35#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.173.23:36:30.35#ibcon#[27=AT05-04\r\n] 2006.173.23:36:30.35#ibcon#*before write, iclass 10, count 2 2006.173.23:36:30.35#ibcon#enter sib2, iclass 10, count 2 2006.173.23:36:30.35#ibcon#flushed, iclass 10, count 2 2006.173.23:36:30.35#ibcon#about to write, iclass 10, count 2 2006.173.23:36:30.35#ibcon#wrote, iclass 10, count 2 2006.173.23:36:30.35#ibcon#about to read 3, iclass 10, count 2 2006.173.23:36:30.38#ibcon#read 3, iclass 10, count 2 2006.173.23:36:30.38#ibcon#about to read 4, iclass 10, count 2 2006.173.23:36:30.38#ibcon#read 4, iclass 10, count 2 2006.173.23:36:30.38#ibcon#about to read 5, iclass 10, count 2 2006.173.23:36:30.38#ibcon#read 5, iclass 10, count 2 2006.173.23:36:30.38#ibcon#about to read 6, iclass 10, count 2 2006.173.23:36:30.38#ibcon#read 6, iclass 10, count 2 2006.173.23:36:30.38#ibcon#end of sib2, iclass 10, count 2 2006.173.23:36:30.38#ibcon#*after write, iclass 10, count 2 2006.173.23:36:30.38#ibcon#*before return 0, iclass 10, count 2 2006.173.23:36:30.38#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.173.23:36:30.38#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.173.23:36:30.38#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.173.23:36:30.38#ibcon#ireg 7 cls_cnt 0 2006.173.23:36:30.38#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.23:36:30.50#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.173.23:36:30.50#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.23:36:30.50#ibcon#enter wrdev, iclass 10, count 0 2006.173.23:36:30.50#ibcon#first serial, iclass 10, count 0 2006.173.23:36:30.50#ibcon#enter sib2, iclass 10, count 0 2006.173.23:36:30.50#ibcon#flushed, iclass 10, count 0 2006.173.23:36:30.50#ibcon#about to write, iclass 10, count 0 2006.173.23:36:30.50#ibcon#wrote, iclass 10, count 0 2006.173.23:36:30.50#ibcon#about to read 3, iclass 10, count 0 2006.173.23:36:30.52#ibcon#read 3, iclass 10, count 0 2006.173.23:36:30.52#ibcon#about to read 4, iclass 10, count 0 2006.173.23:36:30.52#ibcon#read 4, iclass 10, count 0 2006.173.23:36:30.52#ibcon#about to read 5, iclass 10, count 0 2006.173.23:36:30.52#ibcon#read 5, iclass 10, count 0 2006.173.23:36:30.52#ibcon#about to read 6, iclass 10, count 0 2006.173.23:36:30.52#ibcon#read 6, iclass 10, count 0 2006.173.23:36:30.52#ibcon#end of sib2, iclass 10, count 0 2006.173.23:36:30.52#ibcon#*mode == 0, iclass 10, count 0 2006.173.23:36:30.52#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.23:36:30.52#ibcon#[27=USB\r\n] 2006.173.23:36:30.52#ibcon#*before write, iclass 10, count 0 2006.173.23:36:30.52#ibcon#enter sib2, iclass 10, count 0 2006.173.23:36:30.52#ibcon#flushed, iclass 10, count 0 2006.173.23:36:30.52#ibcon#about to write, iclass 10, count 0 2006.173.23:36:30.52#ibcon#wrote, iclass 10, count 0 2006.173.23:36:30.52#ibcon#about to read 3, iclass 10, count 0 2006.173.23:36:30.55#ibcon#read 3, iclass 10, count 0 2006.173.23:36:30.55#ibcon#about to read 4, iclass 10, count 0 2006.173.23:36:30.55#ibcon#read 4, iclass 10, count 0 2006.173.23:36:30.55#ibcon#about to read 5, iclass 10, count 0 2006.173.23:36:30.55#ibcon#read 5, iclass 10, count 0 2006.173.23:36:30.55#ibcon#about to read 6, iclass 10, count 0 2006.173.23:36:30.55#ibcon#read 6, iclass 10, count 0 2006.173.23:36:30.55#ibcon#end of sib2, iclass 10, count 0 2006.173.23:36:30.55#ibcon#*after write, iclass 10, count 0 2006.173.23:36:30.55#ibcon#*before return 0, iclass 10, count 0 2006.173.23:36:30.55#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.173.23:36:30.55#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.173.23:36:30.55#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.23:36:30.55#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.23:36:30.55$vck44/vblo=6,719.99 2006.173.23:36:30.55#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.173.23:36:30.55#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.173.23:36:30.55#ibcon#ireg 17 cls_cnt 0 2006.173.23:36:30.55#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.23:36:30.55#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.173.23:36:30.55#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.23:36:30.55#ibcon#enter wrdev, iclass 12, count 0 2006.173.23:36:30.55#ibcon#first serial, iclass 12, count 0 2006.173.23:36:30.55#ibcon#enter sib2, iclass 12, count 0 2006.173.23:36:30.55#ibcon#flushed, iclass 12, count 0 2006.173.23:36:30.55#ibcon#about to write, iclass 12, count 0 2006.173.23:36:30.55#ibcon#wrote, iclass 12, count 0 2006.173.23:36:30.55#ibcon#about to read 3, iclass 12, count 0 2006.173.23:36:30.57#ibcon#read 3, iclass 12, count 0 2006.173.23:36:30.57#ibcon#about to read 4, iclass 12, count 0 2006.173.23:36:30.57#ibcon#read 4, iclass 12, count 0 2006.173.23:36:30.57#ibcon#about to read 5, iclass 12, count 0 2006.173.23:36:30.57#ibcon#read 5, iclass 12, count 0 2006.173.23:36:30.57#ibcon#about to read 6, iclass 12, count 0 2006.173.23:36:30.57#ibcon#read 6, iclass 12, count 0 2006.173.23:36:30.57#ibcon#end of sib2, iclass 12, count 0 2006.173.23:36:30.57#ibcon#*mode == 0, iclass 12, count 0 2006.173.23:36:30.57#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.23:36:30.57#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.23:36:30.57#ibcon#*before write, iclass 12, count 0 2006.173.23:36:30.57#ibcon#enter sib2, iclass 12, count 0 2006.173.23:36:30.57#ibcon#flushed, iclass 12, count 0 2006.173.23:36:30.57#ibcon#about to write, iclass 12, count 0 2006.173.23:36:30.57#ibcon#wrote, iclass 12, count 0 2006.173.23:36:30.57#ibcon#about to read 3, iclass 12, count 0 2006.173.23:36:30.61#ibcon#read 3, iclass 12, count 0 2006.173.23:36:30.61#ibcon#about to read 4, iclass 12, count 0 2006.173.23:36:30.61#ibcon#read 4, iclass 12, count 0 2006.173.23:36:30.61#ibcon#about to read 5, iclass 12, count 0 2006.173.23:36:30.61#ibcon#read 5, iclass 12, count 0 2006.173.23:36:30.61#ibcon#about to read 6, iclass 12, count 0 2006.173.23:36:30.61#ibcon#read 6, iclass 12, count 0 2006.173.23:36:30.61#ibcon#end of sib2, iclass 12, count 0 2006.173.23:36:30.61#ibcon#*after write, iclass 12, count 0 2006.173.23:36:30.61#ibcon#*before return 0, iclass 12, count 0 2006.173.23:36:30.61#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.173.23:36:30.61#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.173.23:36:30.61#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.23:36:30.61#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.23:36:30.61$vck44/vb=6,4 2006.173.23:36:30.61#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.173.23:36:30.61#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.173.23:36:30.61#ibcon#ireg 11 cls_cnt 2 2006.173.23:36:30.61#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.23:36:30.67#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.173.23:36:30.67#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.23:36:30.67#ibcon#enter wrdev, iclass 14, count 2 2006.173.23:36:30.67#ibcon#first serial, iclass 14, count 2 2006.173.23:36:30.67#ibcon#enter sib2, iclass 14, count 2 2006.173.23:36:30.67#ibcon#flushed, iclass 14, count 2 2006.173.23:36:30.67#ibcon#about to write, iclass 14, count 2 2006.173.23:36:30.67#ibcon#wrote, iclass 14, count 2 2006.173.23:36:30.67#ibcon#about to read 3, iclass 14, count 2 2006.173.23:36:30.69#ibcon#read 3, iclass 14, count 2 2006.173.23:36:30.69#ibcon#about to read 4, iclass 14, count 2 2006.173.23:36:30.69#ibcon#read 4, iclass 14, count 2 2006.173.23:36:30.69#ibcon#about to read 5, iclass 14, count 2 2006.173.23:36:30.69#ibcon#read 5, iclass 14, count 2 2006.173.23:36:30.69#ibcon#about to read 6, iclass 14, count 2 2006.173.23:36:30.69#ibcon#read 6, iclass 14, count 2 2006.173.23:36:30.69#ibcon#end of sib2, iclass 14, count 2 2006.173.23:36:30.69#ibcon#*mode == 0, iclass 14, count 2 2006.173.23:36:30.69#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.173.23:36:30.69#ibcon#[27=AT06-04\r\n] 2006.173.23:36:30.69#ibcon#*before write, iclass 14, count 2 2006.173.23:36:30.69#ibcon#enter sib2, iclass 14, count 2 2006.173.23:36:30.69#ibcon#flushed, iclass 14, count 2 2006.173.23:36:30.69#ibcon#about to write, iclass 14, count 2 2006.173.23:36:30.69#ibcon#wrote, iclass 14, count 2 2006.173.23:36:30.69#ibcon#about to read 3, iclass 14, count 2 2006.173.23:36:30.72#ibcon#read 3, iclass 14, count 2 2006.173.23:36:30.72#ibcon#about to read 4, iclass 14, count 2 2006.173.23:36:30.72#ibcon#read 4, iclass 14, count 2 2006.173.23:36:30.72#ibcon#about to read 5, iclass 14, count 2 2006.173.23:36:30.72#ibcon#read 5, iclass 14, count 2 2006.173.23:36:30.72#ibcon#about to read 6, iclass 14, count 2 2006.173.23:36:30.72#ibcon#read 6, iclass 14, count 2 2006.173.23:36:30.72#ibcon#end of sib2, iclass 14, count 2 2006.173.23:36:30.72#ibcon#*after write, iclass 14, count 2 2006.173.23:36:30.72#ibcon#*before return 0, iclass 14, count 2 2006.173.23:36:30.72#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.173.23:36:30.72#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.173.23:36:30.72#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.173.23:36:30.72#ibcon#ireg 7 cls_cnt 0 2006.173.23:36:30.72#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.23:36:30.84#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.173.23:36:30.84#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.23:36:30.84#ibcon#enter wrdev, iclass 14, count 0 2006.173.23:36:30.84#ibcon#first serial, iclass 14, count 0 2006.173.23:36:30.84#ibcon#enter sib2, iclass 14, count 0 2006.173.23:36:30.84#ibcon#flushed, iclass 14, count 0 2006.173.23:36:30.84#ibcon#about to write, iclass 14, count 0 2006.173.23:36:30.84#ibcon#wrote, iclass 14, count 0 2006.173.23:36:30.84#ibcon#about to read 3, iclass 14, count 0 2006.173.23:36:30.86#ibcon#read 3, iclass 14, count 0 2006.173.23:36:30.86#ibcon#about to read 4, iclass 14, count 0 2006.173.23:36:30.86#ibcon#read 4, iclass 14, count 0 2006.173.23:36:30.86#ibcon#about to read 5, iclass 14, count 0 2006.173.23:36:30.86#ibcon#read 5, iclass 14, count 0 2006.173.23:36:30.86#ibcon#about to read 6, iclass 14, count 0 2006.173.23:36:30.86#ibcon#read 6, iclass 14, count 0 2006.173.23:36:30.86#ibcon#end of sib2, iclass 14, count 0 2006.173.23:36:30.86#ibcon#*mode == 0, iclass 14, count 0 2006.173.23:36:30.86#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.23:36:30.86#ibcon#[27=USB\r\n] 2006.173.23:36:30.86#ibcon#*before write, iclass 14, count 0 2006.173.23:36:30.86#ibcon#enter sib2, iclass 14, count 0 2006.173.23:36:30.86#ibcon#flushed, iclass 14, count 0 2006.173.23:36:30.86#ibcon#about to write, iclass 14, count 0 2006.173.23:36:30.86#ibcon#wrote, iclass 14, count 0 2006.173.23:36:30.86#ibcon#about to read 3, iclass 14, count 0 2006.173.23:36:30.89#ibcon#read 3, iclass 14, count 0 2006.173.23:36:30.89#ibcon#about to read 4, iclass 14, count 0 2006.173.23:36:30.89#ibcon#read 4, iclass 14, count 0 2006.173.23:36:30.89#ibcon#about to read 5, iclass 14, count 0 2006.173.23:36:30.89#ibcon#read 5, iclass 14, count 0 2006.173.23:36:30.89#ibcon#about to read 6, iclass 14, count 0 2006.173.23:36:30.89#ibcon#read 6, iclass 14, count 0 2006.173.23:36:30.89#ibcon#end of sib2, iclass 14, count 0 2006.173.23:36:30.89#ibcon#*after write, iclass 14, count 0 2006.173.23:36:30.89#ibcon#*before return 0, iclass 14, count 0 2006.173.23:36:30.89#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.173.23:36:30.89#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.173.23:36:30.89#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.23:36:30.89#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.23:36:30.89$vck44/vblo=7,734.99 2006.173.23:36:30.89#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.173.23:36:30.89#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.173.23:36:30.89#ibcon#ireg 17 cls_cnt 0 2006.173.23:36:30.89#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.23:36:30.89#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.173.23:36:30.89#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.23:36:30.89#ibcon#enter wrdev, iclass 16, count 0 2006.173.23:36:30.89#ibcon#first serial, iclass 16, count 0 2006.173.23:36:30.89#ibcon#enter sib2, iclass 16, count 0 2006.173.23:36:30.89#ibcon#flushed, iclass 16, count 0 2006.173.23:36:30.89#ibcon#about to write, iclass 16, count 0 2006.173.23:36:30.89#ibcon#wrote, iclass 16, count 0 2006.173.23:36:30.89#ibcon#about to read 3, iclass 16, count 0 2006.173.23:36:30.91#ibcon#read 3, iclass 16, count 0 2006.173.23:36:30.91#ibcon#about to read 4, iclass 16, count 0 2006.173.23:36:30.91#ibcon#read 4, iclass 16, count 0 2006.173.23:36:30.91#ibcon#about to read 5, iclass 16, count 0 2006.173.23:36:30.91#ibcon#read 5, iclass 16, count 0 2006.173.23:36:30.91#ibcon#about to read 6, iclass 16, count 0 2006.173.23:36:30.91#ibcon#read 6, iclass 16, count 0 2006.173.23:36:30.91#ibcon#end of sib2, iclass 16, count 0 2006.173.23:36:30.91#ibcon#*mode == 0, iclass 16, count 0 2006.173.23:36:30.91#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.23:36:30.91#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.23:36:30.91#ibcon#*before write, iclass 16, count 0 2006.173.23:36:30.91#ibcon#enter sib2, iclass 16, count 0 2006.173.23:36:30.91#ibcon#flushed, iclass 16, count 0 2006.173.23:36:30.91#ibcon#about to write, iclass 16, count 0 2006.173.23:36:30.91#ibcon#wrote, iclass 16, count 0 2006.173.23:36:30.91#ibcon#about to read 3, iclass 16, count 0 2006.173.23:36:30.95#ibcon#read 3, iclass 16, count 0 2006.173.23:36:30.95#ibcon#about to read 4, iclass 16, count 0 2006.173.23:36:30.95#ibcon#read 4, iclass 16, count 0 2006.173.23:36:30.95#ibcon#about to read 5, iclass 16, count 0 2006.173.23:36:30.95#ibcon#read 5, iclass 16, count 0 2006.173.23:36:30.95#ibcon#about to read 6, iclass 16, count 0 2006.173.23:36:30.95#ibcon#read 6, iclass 16, count 0 2006.173.23:36:30.95#ibcon#end of sib2, iclass 16, count 0 2006.173.23:36:30.95#ibcon#*after write, iclass 16, count 0 2006.173.23:36:30.95#ibcon#*before return 0, iclass 16, count 0 2006.173.23:36:30.95#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.173.23:36:30.95#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.173.23:36:30.95#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.23:36:30.95#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.23:36:30.95$vck44/vb=7,4 2006.173.23:36:30.95#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.173.23:36:30.95#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.173.23:36:30.95#ibcon#ireg 11 cls_cnt 2 2006.173.23:36:30.95#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.23:36:31.01#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.173.23:36:31.01#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.23:36:31.01#ibcon#enter wrdev, iclass 18, count 2 2006.173.23:36:31.01#ibcon#first serial, iclass 18, count 2 2006.173.23:36:31.01#ibcon#enter sib2, iclass 18, count 2 2006.173.23:36:31.01#ibcon#flushed, iclass 18, count 2 2006.173.23:36:31.01#ibcon#about to write, iclass 18, count 2 2006.173.23:36:31.01#ibcon#wrote, iclass 18, count 2 2006.173.23:36:31.01#ibcon#about to read 3, iclass 18, count 2 2006.173.23:36:31.03#ibcon#read 3, iclass 18, count 2 2006.173.23:36:31.03#ibcon#about to read 4, iclass 18, count 2 2006.173.23:36:31.03#ibcon#read 4, iclass 18, count 2 2006.173.23:36:31.03#ibcon#about to read 5, iclass 18, count 2 2006.173.23:36:31.03#ibcon#read 5, iclass 18, count 2 2006.173.23:36:31.03#ibcon#about to read 6, iclass 18, count 2 2006.173.23:36:31.03#ibcon#read 6, iclass 18, count 2 2006.173.23:36:31.03#ibcon#end of sib2, iclass 18, count 2 2006.173.23:36:31.03#ibcon#*mode == 0, iclass 18, count 2 2006.173.23:36:31.03#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.173.23:36:31.03#ibcon#[27=AT07-04\r\n] 2006.173.23:36:31.03#ibcon#*before write, iclass 18, count 2 2006.173.23:36:31.03#ibcon#enter sib2, iclass 18, count 2 2006.173.23:36:31.03#ibcon#flushed, iclass 18, count 2 2006.173.23:36:31.03#ibcon#about to write, iclass 18, count 2 2006.173.23:36:31.03#ibcon#wrote, iclass 18, count 2 2006.173.23:36:31.03#ibcon#about to read 3, iclass 18, count 2 2006.173.23:36:31.06#ibcon#read 3, iclass 18, count 2 2006.173.23:36:31.06#ibcon#about to read 4, iclass 18, count 2 2006.173.23:36:31.06#ibcon#read 4, iclass 18, count 2 2006.173.23:36:31.06#ibcon#about to read 5, iclass 18, count 2 2006.173.23:36:31.06#ibcon#read 5, iclass 18, count 2 2006.173.23:36:31.06#ibcon#about to read 6, iclass 18, count 2 2006.173.23:36:31.06#ibcon#read 6, iclass 18, count 2 2006.173.23:36:31.06#ibcon#end of sib2, iclass 18, count 2 2006.173.23:36:31.06#ibcon#*after write, iclass 18, count 2 2006.173.23:36:31.06#ibcon#*before return 0, iclass 18, count 2 2006.173.23:36:31.06#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.173.23:36:31.06#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.173.23:36:31.06#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.173.23:36:31.06#ibcon#ireg 7 cls_cnt 0 2006.173.23:36:31.06#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.23:36:31.18#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.173.23:36:31.18#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.23:36:31.18#ibcon#enter wrdev, iclass 18, count 0 2006.173.23:36:31.18#ibcon#first serial, iclass 18, count 0 2006.173.23:36:31.18#ibcon#enter sib2, iclass 18, count 0 2006.173.23:36:31.18#ibcon#flushed, iclass 18, count 0 2006.173.23:36:31.18#ibcon#about to write, iclass 18, count 0 2006.173.23:36:31.18#ibcon#wrote, iclass 18, count 0 2006.173.23:36:31.18#ibcon#about to read 3, iclass 18, count 0 2006.173.23:36:31.20#ibcon#read 3, iclass 18, count 0 2006.173.23:36:31.20#ibcon#about to read 4, iclass 18, count 0 2006.173.23:36:31.20#ibcon#read 4, iclass 18, count 0 2006.173.23:36:31.20#ibcon#about to read 5, iclass 18, count 0 2006.173.23:36:31.20#ibcon#read 5, iclass 18, count 0 2006.173.23:36:31.20#ibcon#about to read 6, iclass 18, count 0 2006.173.23:36:31.20#ibcon#read 6, iclass 18, count 0 2006.173.23:36:31.20#ibcon#end of sib2, iclass 18, count 0 2006.173.23:36:31.20#ibcon#*mode == 0, iclass 18, count 0 2006.173.23:36:31.20#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.23:36:31.20#ibcon#[27=USB\r\n] 2006.173.23:36:31.20#ibcon#*before write, iclass 18, count 0 2006.173.23:36:31.20#ibcon#enter sib2, iclass 18, count 0 2006.173.23:36:31.20#ibcon#flushed, iclass 18, count 0 2006.173.23:36:31.20#ibcon#about to write, iclass 18, count 0 2006.173.23:36:31.20#ibcon#wrote, iclass 18, count 0 2006.173.23:36:31.20#ibcon#about to read 3, iclass 18, count 0 2006.173.23:36:31.23#ibcon#read 3, iclass 18, count 0 2006.173.23:36:31.23#ibcon#about to read 4, iclass 18, count 0 2006.173.23:36:31.23#ibcon#read 4, iclass 18, count 0 2006.173.23:36:31.23#ibcon#about to read 5, iclass 18, count 0 2006.173.23:36:31.23#ibcon#read 5, iclass 18, count 0 2006.173.23:36:31.23#ibcon#about to read 6, iclass 18, count 0 2006.173.23:36:31.23#ibcon#read 6, iclass 18, count 0 2006.173.23:36:31.23#ibcon#end of sib2, iclass 18, count 0 2006.173.23:36:31.23#ibcon#*after write, iclass 18, count 0 2006.173.23:36:31.23#ibcon#*before return 0, iclass 18, count 0 2006.173.23:36:31.23#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.173.23:36:31.23#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.173.23:36:31.23#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.23:36:31.23#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.23:36:31.23$vck44/vblo=8,744.99 2006.173.23:36:31.23#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.173.23:36:31.23#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.173.23:36:31.23#ibcon#ireg 17 cls_cnt 0 2006.173.23:36:31.23#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.23:36:31.23#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.173.23:36:31.23#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.23:36:31.23#ibcon#enter wrdev, iclass 20, count 0 2006.173.23:36:31.23#ibcon#first serial, iclass 20, count 0 2006.173.23:36:31.23#ibcon#enter sib2, iclass 20, count 0 2006.173.23:36:31.23#ibcon#flushed, iclass 20, count 0 2006.173.23:36:31.23#ibcon#about to write, iclass 20, count 0 2006.173.23:36:31.23#ibcon#wrote, iclass 20, count 0 2006.173.23:36:31.23#ibcon#about to read 3, iclass 20, count 0 2006.173.23:36:31.25#ibcon#read 3, iclass 20, count 0 2006.173.23:36:31.25#ibcon#about to read 4, iclass 20, count 0 2006.173.23:36:31.25#ibcon#read 4, iclass 20, count 0 2006.173.23:36:31.25#ibcon#about to read 5, iclass 20, count 0 2006.173.23:36:31.25#ibcon#read 5, iclass 20, count 0 2006.173.23:36:31.25#ibcon#about to read 6, iclass 20, count 0 2006.173.23:36:31.25#ibcon#read 6, iclass 20, count 0 2006.173.23:36:31.25#ibcon#end of sib2, iclass 20, count 0 2006.173.23:36:31.25#ibcon#*mode == 0, iclass 20, count 0 2006.173.23:36:31.25#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.23:36:31.25#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.23:36:31.25#ibcon#*before write, iclass 20, count 0 2006.173.23:36:31.25#ibcon#enter sib2, iclass 20, count 0 2006.173.23:36:31.25#ibcon#flushed, iclass 20, count 0 2006.173.23:36:31.25#ibcon#about to write, iclass 20, count 0 2006.173.23:36:31.25#ibcon#wrote, iclass 20, count 0 2006.173.23:36:31.25#ibcon#about to read 3, iclass 20, count 0 2006.173.23:36:31.29#ibcon#read 3, iclass 20, count 0 2006.173.23:36:31.29#ibcon#about to read 4, iclass 20, count 0 2006.173.23:36:31.29#ibcon#read 4, iclass 20, count 0 2006.173.23:36:31.29#ibcon#about to read 5, iclass 20, count 0 2006.173.23:36:31.29#ibcon#read 5, iclass 20, count 0 2006.173.23:36:31.29#ibcon#about to read 6, iclass 20, count 0 2006.173.23:36:31.29#ibcon#read 6, iclass 20, count 0 2006.173.23:36:31.29#ibcon#end of sib2, iclass 20, count 0 2006.173.23:36:31.29#ibcon#*after write, iclass 20, count 0 2006.173.23:36:31.29#ibcon#*before return 0, iclass 20, count 0 2006.173.23:36:31.29#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.173.23:36:31.29#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.173.23:36:31.29#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.23:36:31.29#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.23:36:31.29$vck44/vb=8,4 2006.173.23:36:31.29#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.173.23:36:31.29#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.173.23:36:31.29#ibcon#ireg 11 cls_cnt 2 2006.173.23:36:31.29#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.23:36:31.35#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.173.23:36:31.35#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.23:36:31.35#ibcon#enter wrdev, iclass 22, count 2 2006.173.23:36:31.35#ibcon#first serial, iclass 22, count 2 2006.173.23:36:31.35#ibcon#enter sib2, iclass 22, count 2 2006.173.23:36:31.35#ibcon#flushed, iclass 22, count 2 2006.173.23:36:31.35#ibcon#about to write, iclass 22, count 2 2006.173.23:36:31.35#ibcon#wrote, iclass 22, count 2 2006.173.23:36:31.35#ibcon#about to read 3, iclass 22, count 2 2006.173.23:36:31.37#ibcon#read 3, iclass 22, count 2 2006.173.23:36:31.37#ibcon#about to read 4, iclass 22, count 2 2006.173.23:36:31.37#ibcon#read 4, iclass 22, count 2 2006.173.23:36:31.37#ibcon#about to read 5, iclass 22, count 2 2006.173.23:36:31.37#ibcon#read 5, iclass 22, count 2 2006.173.23:36:31.37#ibcon#about to read 6, iclass 22, count 2 2006.173.23:36:31.37#ibcon#read 6, iclass 22, count 2 2006.173.23:36:31.37#ibcon#end of sib2, iclass 22, count 2 2006.173.23:36:31.37#ibcon#*mode == 0, iclass 22, count 2 2006.173.23:36:31.37#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.173.23:36:31.37#ibcon#[27=AT08-04\r\n] 2006.173.23:36:31.37#ibcon#*before write, iclass 22, count 2 2006.173.23:36:31.37#ibcon#enter sib2, iclass 22, count 2 2006.173.23:36:31.37#ibcon#flushed, iclass 22, count 2 2006.173.23:36:31.37#ibcon#about to write, iclass 22, count 2 2006.173.23:36:31.37#ibcon#wrote, iclass 22, count 2 2006.173.23:36:31.37#ibcon#about to read 3, iclass 22, count 2 2006.173.23:36:31.40#ibcon#read 3, iclass 22, count 2 2006.173.23:36:31.40#ibcon#about to read 4, iclass 22, count 2 2006.173.23:36:31.40#ibcon#read 4, iclass 22, count 2 2006.173.23:36:31.40#ibcon#about to read 5, iclass 22, count 2 2006.173.23:36:31.40#ibcon#read 5, iclass 22, count 2 2006.173.23:36:31.40#ibcon#about to read 6, iclass 22, count 2 2006.173.23:36:31.40#ibcon#read 6, iclass 22, count 2 2006.173.23:36:31.40#ibcon#end of sib2, iclass 22, count 2 2006.173.23:36:31.40#ibcon#*after write, iclass 22, count 2 2006.173.23:36:31.40#ibcon#*before return 0, iclass 22, count 2 2006.173.23:36:31.40#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.173.23:36:31.40#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.173.23:36:31.40#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.173.23:36:31.40#ibcon#ireg 7 cls_cnt 0 2006.173.23:36:31.40#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.23:36:31.52#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.173.23:36:31.52#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.23:36:31.52#ibcon#enter wrdev, iclass 22, count 0 2006.173.23:36:31.52#ibcon#first serial, iclass 22, count 0 2006.173.23:36:31.52#ibcon#enter sib2, iclass 22, count 0 2006.173.23:36:31.52#ibcon#flushed, iclass 22, count 0 2006.173.23:36:31.52#ibcon#about to write, iclass 22, count 0 2006.173.23:36:31.52#ibcon#wrote, iclass 22, count 0 2006.173.23:36:31.52#ibcon#about to read 3, iclass 22, count 0 2006.173.23:36:31.54#ibcon#read 3, iclass 22, count 0 2006.173.23:36:31.54#ibcon#about to read 4, iclass 22, count 0 2006.173.23:36:31.54#ibcon#read 4, iclass 22, count 0 2006.173.23:36:31.54#ibcon#about to read 5, iclass 22, count 0 2006.173.23:36:31.54#ibcon#read 5, iclass 22, count 0 2006.173.23:36:31.54#ibcon#about to read 6, iclass 22, count 0 2006.173.23:36:31.54#ibcon#read 6, iclass 22, count 0 2006.173.23:36:31.54#ibcon#end of sib2, iclass 22, count 0 2006.173.23:36:31.54#ibcon#*mode == 0, iclass 22, count 0 2006.173.23:36:31.54#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.23:36:31.54#ibcon#[27=USB\r\n] 2006.173.23:36:31.54#ibcon#*before write, iclass 22, count 0 2006.173.23:36:31.54#ibcon#enter sib2, iclass 22, count 0 2006.173.23:36:31.54#ibcon#flushed, iclass 22, count 0 2006.173.23:36:31.54#ibcon#about to write, iclass 22, count 0 2006.173.23:36:31.54#ibcon#wrote, iclass 22, count 0 2006.173.23:36:31.54#ibcon#about to read 3, iclass 22, count 0 2006.173.23:36:31.57#ibcon#read 3, iclass 22, count 0 2006.173.23:36:31.57#ibcon#about to read 4, iclass 22, count 0 2006.173.23:36:31.57#ibcon#read 4, iclass 22, count 0 2006.173.23:36:31.57#ibcon#about to read 5, iclass 22, count 0 2006.173.23:36:31.57#ibcon#read 5, iclass 22, count 0 2006.173.23:36:31.57#ibcon#about to read 6, iclass 22, count 0 2006.173.23:36:31.57#ibcon#read 6, iclass 22, count 0 2006.173.23:36:31.57#ibcon#end of sib2, iclass 22, count 0 2006.173.23:36:31.57#ibcon#*after write, iclass 22, count 0 2006.173.23:36:31.57#ibcon#*before return 0, iclass 22, count 0 2006.173.23:36:31.57#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.173.23:36:31.57#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.173.23:36:31.57#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.23:36:31.57#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.23:36:31.57$vck44/vabw=wide 2006.173.23:36:31.57#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.173.23:36:31.57#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.173.23:36:31.57#ibcon#ireg 8 cls_cnt 0 2006.173.23:36:31.57#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.23:36:31.57#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.173.23:36:31.57#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.23:36:31.57#ibcon#enter wrdev, iclass 24, count 0 2006.173.23:36:31.57#ibcon#first serial, iclass 24, count 0 2006.173.23:36:31.57#ibcon#enter sib2, iclass 24, count 0 2006.173.23:36:31.57#ibcon#flushed, iclass 24, count 0 2006.173.23:36:31.57#ibcon#about to write, iclass 24, count 0 2006.173.23:36:31.57#ibcon#wrote, iclass 24, count 0 2006.173.23:36:31.57#ibcon#about to read 3, iclass 24, count 0 2006.173.23:36:31.59#ibcon#read 3, iclass 24, count 0 2006.173.23:36:31.59#ibcon#about to read 4, iclass 24, count 0 2006.173.23:36:31.59#ibcon#read 4, iclass 24, count 0 2006.173.23:36:31.59#ibcon#about to read 5, iclass 24, count 0 2006.173.23:36:31.59#ibcon#read 5, iclass 24, count 0 2006.173.23:36:31.59#ibcon#about to read 6, iclass 24, count 0 2006.173.23:36:31.59#ibcon#read 6, iclass 24, count 0 2006.173.23:36:31.59#ibcon#end of sib2, iclass 24, count 0 2006.173.23:36:31.59#ibcon#*mode == 0, iclass 24, count 0 2006.173.23:36:31.59#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.23:36:31.59#ibcon#[25=BW32\r\n] 2006.173.23:36:31.59#ibcon#*before write, iclass 24, count 0 2006.173.23:36:31.59#ibcon#enter sib2, iclass 24, count 0 2006.173.23:36:31.59#ibcon#flushed, iclass 24, count 0 2006.173.23:36:31.59#ibcon#about to write, iclass 24, count 0 2006.173.23:36:31.59#ibcon#wrote, iclass 24, count 0 2006.173.23:36:31.59#ibcon#about to read 3, iclass 24, count 0 2006.173.23:36:31.62#ibcon#read 3, iclass 24, count 0 2006.173.23:36:31.62#ibcon#about to read 4, iclass 24, count 0 2006.173.23:36:31.62#ibcon#read 4, iclass 24, count 0 2006.173.23:36:31.62#ibcon#about to read 5, iclass 24, count 0 2006.173.23:36:31.62#ibcon#read 5, iclass 24, count 0 2006.173.23:36:31.62#ibcon#about to read 6, iclass 24, count 0 2006.173.23:36:31.62#ibcon#read 6, iclass 24, count 0 2006.173.23:36:31.62#ibcon#end of sib2, iclass 24, count 0 2006.173.23:36:31.62#ibcon#*after write, iclass 24, count 0 2006.173.23:36:31.62#ibcon#*before return 0, iclass 24, count 0 2006.173.23:36:31.62#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.173.23:36:31.62#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.173.23:36:31.62#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.23:36:31.62#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.23:36:31.62$vck44/vbbw=wide 2006.173.23:36:31.62#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.23:36:31.62#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.23:36:31.62#ibcon#ireg 8 cls_cnt 0 2006.173.23:36:31.62#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.23:36:31.69#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.23:36:31.69#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.23:36:31.69#ibcon#enter wrdev, iclass 26, count 0 2006.173.23:36:31.69#ibcon#first serial, iclass 26, count 0 2006.173.23:36:31.69#ibcon#enter sib2, iclass 26, count 0 2006.173.23:36:31.69#ibcon#flushed, iclass 26, count 0 2006.173.23:36:31.69#ibcon#about to write, iclass 26, count 0 2006.173.23:36:31.69#ibcon#wrote, iclass 26, count 0 2006.173.23:36:31.69#ibcon#about to read 3, iclass 26, count 0 2006.173.23:36:31.71#ibcon#read 3, iclass 26, count 0 2006.173.23:36:31.71#ibcon#about to read 4, iclass 26, count 0 2006.173.23:36:31.71#ibcon#read 4, iclass 26, count 0 2006.173.23:36:31.71#ibcon#about to read 5, iclass 26, count 0 2006.173.23:36:31.71#ibcon#read 5, iclass 26, count 0 2006.173.23:36:31.71#ibcon#about to read 6, iclass 26, count 0 2006.173.23:36:31.71#ibcon#read 6, iclass 26, count 0 2006.173.23:36:31.71#ibcon#end of sib2, iclass 26, count 0 2006.173.23:36:31.71#ibcon#*mode == 0, iclass 26, count 0 2006.173.23:36:31.71#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.23:36:31.71#ibcon#[27=BW32\r\n] 2006.173.23:36:31.71#ibcon#*before write, iclass 26, count 0 2006.173.23:36:31.71#ibcon#enter sib2, iclass 26, count 0 2006.173.23:36:31.71#ibcon#flushed, iclass 26, count 0 2006.173.23:36:31.71#ibcon#about to write, iclass 26, count 0 2006.173.23:36:31.71#ibcon#wrote, iclass 26, count 0 2006.173.23:36:31.71#ibcon#about to read 3, iclass 26, count 0 2006.173.23:36:31.74#ibcon#read 3, iclass 26, count 0 2006.173.23:36:31.74#ibcon#about to read 4, iclass 26, count 0 2006.173.23:36:31.74#ibcon#read 4, iclass 26, count 0 2006.173.23:36:31.74#ibcon#about to read 5, iclass 26, count 0 2006.173.23:36:31.74#ibcon#read 5, iclass 26, count 0 2006.173.23:36:31.74#ibcon#about to read 6, iclass 26, count 0 2006.173.23:36:31.74#ibcon#read 6, iclass 26, count 0 2006.173.23:36:31.74#ibcon#end of sib2, iclass 26, count 0 2006.173.23:36:31.74#ibcon#*after write, iclass 26, count 0 2006.173.23:36:31.74#ibcon#*before return 0, iclass 26, count 0 2006.173.23:36:31.74#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.23:36:31.74#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.23:36:31.74#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.23:36:31.74#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.23:36:31.74$setupk4/ifdk4 2006.173.23:36:31.74$ifdk4/lo= 2006.173.23:36:31.74$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.23:36:31.74$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.23:36:31.74$ifdk4/patch= 2006.173.23:36:31.74$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.23:36:31.74$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.23:36:31.74$setupk4/!*+20s 2006.173.23:36:37.14#trakl#Source acquired 2006.173.23:36:37.14#flagr#flagr/antenna,acquired 2006.173.23:36:38.29#abcon#<5=/13 0.8 2.1 23.50 871003.2\r\n> 2006.173.23:36:38.31#abcon#{5=INTERFACE CLEAR} 2006.173.23:36:38.37#abcon#[5=S1D000X0/0*\r\n] 2006.173.23:36:46.24$setupk4/"tpicd 2006.173.23:36:46.24$setupk4/echo=off 2006.173.23:36:46.24$setupk4/xlog=off 2006.173.23:36:46.24:!2006.173.23:42:51 2006.173.23:42:51.00:preob 2006.173.23:42:51.14/onsource/TRACKING 2006.173.23:42:51.15:!2006.173.23:43:01 2006.173.23:43:01.01:"tape 2006.173.23:43:01.01:"st=record 2006.173.23:43:01.01:data_valid=on 2006.173.23:43:01.02:midob 2006.173.23:43:02.14/onsource/TRACKING 2006.173.23:43:02.15/wx/23.64,1003.2,85 2006.173.23:43:02.31/cable/+6.5109E-03 2006.173.23:43:03.40/va/01,07,usb,yes,38,41 2006.173.23:43:03.40/va/02,06,usb,yes,38,39 2006.173.23:43:03.40/va/03,05,usb,yes,48,50 2006.173.23:43:03.40/va/04,06,usb,yes,39,41 2006.173.23:43:03.40/va/05,04,usb,yes,31,31 2006.173.23:43:03.40/va/06,03,usb,yes,43,43 2006.173.23:43:03.40/va/07,04,usb,yes,35,36 2006.173.23:43:03.40/va/08,04,usb,yes,30,35 2006.173.23:43:03.63/valo/01,524.99,yes,locked 2006.173.23:43:03.63/valo/02,534.99,yes,locked 2006.173.23:43:03.63/valo/03,564.99,yes,locked 2006.173.23:43:03.63/valo/04,624.99,yes,locked 2006.173.23:43:03.63/valo/05,734.99,yes,locked 2006.173.23:43:03.63/valo/06,814.99,yes,locked 2006.173.23:43:03.63/valo/07,864.99,yes,locked 2006.173.23:43:03.63/valo/08,884.99,yes,locked 2006.173.23:43:04.72/vb/01,04,usb,yes,30,28 2006.173.23:43:04.72/vb/02,04,usb,yes,32,32 2006.173.23:43:04.72/vb/03,04,usb,yes,29,32 2006.173.23:43:04.72/vb/04,04,usb,yes,34,33 2006.173.23:43:04.72/vb/05,04,usb,yes,26,29 2006.173.23:43:04.72/vb/06,04,usb,yes,31,27 2006.173.23:43:04.72/vb/07,04,usb,yes,31,30 2006.173.23:43:04.72/vb/08,04,usb,yes,28,31 2006.173.23:43:04.96/vblo/01,629.99,yes,locked 2006.173.23:43:04.96/vblo/02,634.99,yes,locked 2006.173.23:43:04.96/vblo/03,649.99,yes,locked 2006.173.23:43:04.96/vblo/04,679.99,yes,locked 2006.173.23:43:04.96/vblo/05,709.99,yes,locked 2006.173.23:43:04.96/vblo/06,719.99,yes,locked 2006.173.23:43:04.96/vblo/07,734.99,yes,locked 2006.173.23:43:04.96/vblo/08,744.99,yes,locked 2006.173.23:43:05.11/vabw/8 2006.173.23:43:05.26/vbbw/8 2006.173.23:43:05.35/xfe/off,on,15.2 2006.173.23:43:05.72/ifatt/23,28,28,28 2006.173.23:43:06.07/fmout-gps/S +3.88E-07 2006.173.23:43:06.12:!2006.173.23:44:51 2006.173.23:44:51.01:data_valid=off 2006.173.23:44:51.02:"et 2006.173.23:44:51.02:!+3s 2006.173.23:44:54.03:"tape 2006.173.23:44:54.04:postob 2006.173.23:44:54.20/cable/+6.5097E-03 2006.173.23:44:54.21/wx/23.68,1003.2,85 2006.173.23:44:54.26/fmout-gps/S +3.91E-07 2006.173.23:44:54.27:scan_name=173-2350,jd0606,80 2006.173.23:44:54.27:source=0727-115,073019.11,-114112.6,2000.0,ccw 2006.173.23:44:56.14#flagr#flagr/antenna,new-source 2006.173.23:44:56.14:checkk5 2006.173.23:44:56.50/chk_autoobs//k5ts1/ autoobs is running! 2006.173.23:44:56.90/chk_autoobs//k5ts2/ autoobs is running! 2006.173.23:44:57.31/chk_autoobs//k5ts3/ autoobs is running! 2006.173.23:44:57.70/chk_autoobs//k5ts4/ autoobs is running! 2006.173.23:44:58.10/chk_obsdata//k5ts1/T1732343??a.dat file size is correct (nominal:440MB, actual:436MB). 2006.173.23:44:58.48/chk_obsdata//k5ts2/T1732343??b.dat file size is correct (nominal:440MB, actual:436MB). 2006.173.23:44:58.89/chk_obsdata//k5ts3/T1732343??c.dat file size is correct (nominal:440MB, actual:436MB). 2006.173.23:44:59.32/chk_obsdata//k5ts4/T1732343??d.dat file size is correct (nominal:440MB, actual:436MB). 2006.173.23:45:00.04/k5log//k5ts1_log_newline 2006.173.23:45:00.73/k5log//k5ts2_log_newline 2006.173.23:45:01.45/k5log//k5ts3_log_newline 2006.173.23:45:02.15/k5log//k5ts4_log_newline 2006.173.23:45:02.17/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.23:45:02.17:setupk4=1 2006.173.23:45:02.17$setupk4/echo=on 2006.173.23:45:02.17$setupk4/pcalon 2006.173.23:45:02.17$pcalon/"no phase cal control is implemented here 2006.173.23:45:02.17$setupk4/"tpicd=stop 2006.173.23:45:02.17$setupk4/"rec=synch_on 2006.173.23:45:02.17$setupk4/"rec_mode=128 2006.173.23:45:02.17$setupk4/!* 2006.173.23:45:02.17$setupk4/recpk4 2006.173.23:45:02.17$recpk4/recpatch= 2006.173.23:45:02.18$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.23:45:02.18$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.23:45:02.18$setupk4/vck44 2006.173.23:45:02.18$vck44/valo=1,524.99 2006.173.23:45:02.18#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.23:45:02.18#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.23:45:02.18#ibcon#ireg 17 cls_cnt 0 2006.173.23:45:02.18#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.23:45:02.18#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.23:45:02.18#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.23:45:02.18#ibcon#enter wrdev, iclass 15, count 0 2006.173.23:45:02.18#ibcon#first serial, iclass 15, count 0 2006.173.23:45:02.18#ibcon#enter sib2, iclass 15, count 0 2006.173.23:45:02.18#ibcon#flushed, iclass 15, count 0 2006.173.23:45:02.18#ibcon#about to write, iclass 15, count 0 2006.173.23:45:02.18#ibcon#wrote, iclass 15, count 0 2006.173.23:45:02.18#ibcon#about to read 3, iclass 15, count 0 2006.173.23:45:02.19#ibcon#read 3, iclass 15, count 0 2006.173.23:45:02.19#ibcon#about to read 4, iclass 15, count 0 2006.173.23:45:02.19#ibcon#read 4, iclass 15, count 0 2006.173.23:45:02.19#ibcon#about to read 5, iclass 15, count 0 2006.173.23:45:02.19#ibcon#read 5, iclass 15, count 0 2006.173.23:45:02.19#ibcon#about to read 6, iclass 15, count 0 2006.173.23:45:02.19#ibcon#read 6, iclass 15, count 0 2006.173.23:45:02.19#ibcon#end of sib2, iclass 15, count 0 2006.173.23:45:02.19#ibcon#*mode == 0, iclass 15, count 0 2006.173.23:45:02.19#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.23:45:02.19#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.23:45:02.19#ibcon#*before write, iclass 15, count 0 2006.173.23:45:02.19#ibcon#enter sib2, iclass 15, count 0 2006.173.23:45:02.19#ibcon#flushed, iclass 15, count 0 2006.173.23:45:02.19#ibcon#about to write, iclass 15, count 0 2006.173.23:45:02.19#ibcon#wrote, iclass 15, count 0 2006.173.23:45:02.19#ibcon#about to read 3, iclass 15, count 0 2006.173.23:45:02.24#ibcon#read 3, iclass 15, count 0 2006.173.23:45:02.24#ibcon#about to read 4, iclass 15, count 0 2006.173.23:45:02.24#ibcon#read 4, iclass 15, count 0 2006.173.23:45:02.24#ibcon#about to read 5, iclass 15, count 0 2006.173.23:45:02.24#ibcon#read 5, iclass 15, count 0 2006.173.23:45:02.24#ibcon#about to read 6, iclass 15, count 0 2006.173.23:45:02.24#ibcon#read 6, iclass 15, count 0 2006.173.23:45:02.24#ibcon#end of sib2, iclass 15, count 0 2006.173.23:45:02.24#ibcon#*after write, iclass 15, count 0 2006.173.23:45:02.24#ibcon#*before return 0, iclass 15, count 0 2006.173.23:45:02.24#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.23:45:02.24#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.23:45:02.24#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.23:45:02.24#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.23:45:02.24$vck44/va=1,7 2006.173.23:45:02.24#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.23:45:02.24#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.23:45:02.24#ibcon#ireg 11 cls_cnt 2 2006.173.23:45:02.24#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.23:45:02.24#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.23:45:02.24#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.23:45:02.24#ibcon#enter wrdev, iclass 17, count 2 2006.173.23:45:02.24#ibcon#first serial, iclass 17, count 2 2006.173.23:45:02.24#ibcon#enter sib2, iclass 17, count 2 2006.173.23:45:02.24#ibcon#flushed, iclass 17, count 2 2006.173.23:45:02.24#ibcon#about to write, iclass 17, count 2 2006.173.23:45:02.24#ibcon#wrote, iclass 17, count 2 2006.173.23:45:02.24#ibcon#about to read 3, iclass 17, count 2 2006.173.23:45:02.26#ibcon#read 3, iclass 17, count 2 2006.173.23:45:02.26#ibcon#about to read 4, iclass 17, count 2 2006.173.23:45:02.26#ibcon#read 4, iclass 17, count 2 2006.173.23:45:02.26#ibcon#about to read 5, iclass 17, count 2 2006.173.23:45:02.26#ibcon#read 5, iclass 17, count 2 2006.173.23:45:02.26#ibcon#about to read 6, iclass 17, count 2 2006.173.23:45:02.26#ibcon#read 6, iclass 17, count 2 2006.173.23:45:02.26#ibcon#end of sib2, iclass 17, count 2 2006.173.23:45:02.26#ibcon#*mode == 0, iclass 17, count 2 2006.173.23:45:02.26#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.23:45:02.26#ibcon#[25=AT01-07\r\n] 2006.173.23:45:02.26#ibcon#*before write, iclass 17, count 2 2006.173.23:45:02.26#ibcon#enter sib2, iclass 17, count 2 2006.173.23:45:02.26#ibcon#flushed, iclass 17, count 2 2006.173.23:45:02.26#ibcon#about to write, iclass 17, count 2 2006.173.23:45:02.26#ibcon#wrote, iclass 17, count 2 2006.173.23:45:02.26#ibcon#about to read 3, iclass 17, count 2 2006.173.23:45:02.29#ibcon#read 3, iclass 17, count 2 2006.173.23:45:02.29#ibcon#about to read 4, iclass 17, count 2 2006.173.23:45:02.29#ibcon#read 4, iclass 17, count 2 2006.173.23:45:02.29#ibcon#about to read 5, iclass 17, count 2 2006.173.23:45:02.29#ibcon#read 5, iclass 17, count 2 2006.173.23:45:02.29#ibcon#about to read 6, iclass 17, count 2 2006.173.23:45:02.29#ibcon#read 6, iclass 17, count 2 2006.173.23:45:02.29#ibcon#end of sib2, iclass 17, count 2 2006.173.23:45:02.29#ibcon#*after write, iclass 17, count 2 2006.173.23:45:02.29#ibcon#*before return 0, iclass 17, count 2 2006.173.23:45:02.29#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.23:45:02.29#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.23:45:02.29#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.23:45:02.29#ibcon#ireg 7 cls_cnt 0 2006.173.23:45:02.29#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.23:45:02.41#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.23:45:02.41#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.23:45:02.41#ibcon#enter wrdev, iclass 17, count 0 2006.173.23:45:02.41#ibcon#first serial, iclass 17, count 0 2006.173.23:45:02.41#ibcon#enter sib2, iclass 17, count 0 2006.173.23:45:02.41#ibcon#flushed, iclass 17, count 0 2006.173.23:45:02.41#ibcon#about to write, iclass 17, count 0 2006.173.23:45:02.41#ibcon#wrote, iclass 17, count 0 2006.173.23:45:02.41#ibcon#about to read 3, iclass 17, count 0 2006.173.23:45:02.43#ibcon#read 3, iclass 17, count 0 2006.173.23:45:02.43#ibcon#about to read 4, iclass 17, count 0 2006.173.23:45:02.43#ibcon#read 4, iclass 17, count 0 2006.173.23:45:02.43#ibcon#about to read 5, iclass 17, count 0 2006.173.23:45:02.43#ibcon#read 5, iclass 17, count 0 2006.173.23:45:02.43#ibcon#about to read 6, iclass 17, count 0 2006.173.23:45:02.43#ibcon#read 6, iclass 17, count 0 2006.173.23:45:02.43#ibcon#end of sib2, iclass 17, count 0 2006.173.23:45:02.43#ibcon#*mode == 0, iclass 17, count 0 2006.173.23:45:02.43#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.23:45:02.43#ibcon#[25=USB\r\n] 2006.173.23:45:02.43#ibcon#*before write, iclass 17, count 0 2006.173.23:45:02.43#ibcon#enter sib2, iclass 17, count 0 2006.173.23:45:02.43#ibcon#flushed, iclass 17, count 0 2006.173.23:45:02.43#ibcon#about to write, iclass 17, count 0 2006.173.23:45:02.43#ibcon#wrote, iclass 17, count 0 2006.173.23:45:02.43#ibcon#about to read 3, iclass 17, count 0 2006.173.23:45:02.46#ibcon#read 3, iclass 17, count 0 2006.173.23:45:02.46#ibcon#about to read 4, iclass 17, count 0 2006.173.23:45:02.46#ibcon#read 4, iclass 17, count 0 2006.173.23:45:02.46#ibcon#about to read 5, iclass 17, count 0 2006.173.23:45:02.46#ibcon#read 5, iclass 17, count 0 2006.173.23:45:02.46#ibcon#about to read 6, iclass 17, count 0 2006.173.23:45:02.46#ibcon#read 6, iclass 17, count 0 2006.173.23:45:02.46#ibcon#end of sib2, iclass 17, count 0 2006.173.23:45:02.46#ibcon#*after write, iclass 17, count 0 2006.173.23:45:02.46#ibcon#*before return 0, iclass 17, count 0 2006.173.23:45:02.46#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.23:45:02.46#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.23:45:02.46#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.23:45:02.46#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.23:45:02.46$vck44/valo=2,534.99 2006.173.23:45:02.46#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.23:45:02.46#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.23:45:02.46#ibcon#ireg 17 cls_cnt 0 2006.173.23:45:02.46#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.23:45:02.46#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.23:45:02.46#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.23:45:02.46#ibcon#enter wrdev, iclass 19, count 0 2006.173.23:45:02.46#ibcon#first serial, iclass 19, count 0 2006.173.23:45:02.46#ibcon#enter sib2, iclass 19, count 0 2006.173.23:45:02.46#ibcon#flushed, iclass 19, count 0 2006.173.23:45:02.46#ibcon#about to write, iclass 19, count 0 2006.173.23:45:02.46#ibcon#wrote, iclass 19, count 0 2006.173.23:45:02.46#ibcon#about to read 3, iclass 19, count 0 2006.173.23:45:02.48#ibcon#read 3, iclass 19, count 0 2006.173.23:45:02.48#ibcon#about to read 4, iclass 19, count 0 2006.173.23:45:02.48#ibcon#read 4, iclass 19, count 0 2006.173.23:45:02.48#ibcon#about to read 5, iclass 19, count 0 2006.173.23:45:02.48#ibcon#read 5, iclass 19, count 0 2006.173.23:45:02.48#ibcon#about to read 6, iclass 19, count 0 2006.173.23:45:02.48#ibcon#read 6, iclass 19, count 0 2006.173.23:45:02.48#ibcon#end of sib2, iclass 19, count 0 2006.173.23:45:02.48#ibcon#*mode == 0, iclass 19, count 0 2006.173.23:45:02.48#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.23:45:02.48#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.23:45:02.48#ibcon#*before write, iclass 19, count 0 2006.173.23:45:02.48#ibcon#enter sib2, iclass 19, count 0 2006.173.23:45:02.48#ibcon#flushed, iclass 19, count 0 2006.173.23:45:02.48#ibcon#about to write, iclass 19, count 0 2006.173.23:45:02.48#ibcon#wrote, iclass 19, count 0 2006.173.23:45:02.48#ibcon#about to read 3, iclass 19, count 0 2006.173.23:45:02.52#ibcon#read 3, iclass 19, count 0 2006.173.23:45:02.52#ibcon#about to read 4, iclass 19, count 0 2006.173.23:45:02.52#ibcon#read 4, iclass 19, count 0 2006.173.23:45:02.52#ibcon#about to read 5, iclass 19, count 0 2006.173.23:45:02.52#ibcon#read 5, iclass 19, count 0 2006.173.23:45:02.52#ibcon#about to read 6, iclass 19, count 0 2006.173.23:45:02.52#ibcon#read 6, iclass 19, count 0 2006.173.23:45:02.52#ibcon#end of sib2, iclass 19, count 0 2006.173.23:45:02.52#ibcon#*after write, iclass 19, count 0 2006.173.23:45:02.52#ibcon#*before return 0, iclass 19, count 0 2006.173.23:45:02.52#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.23:45:02.52#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.23:45:02.52#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.23:45:02.52#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.23:45:02.52$vck44/va=2,6 2006.173.23:45:02.52#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.23:45:02.52#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.23:45:02.52#ibcon#ireg 11 cls_cnt 2 2006.173.23:45:02.52#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.23:45:02.58#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.23:45:02.58#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.23:45:02.58#ibcon#enter wrdev, iclass 21, count 2 2006.173.23:45:02.58#ibcon#first serial, iclass 21, count 2 2006.173.23:45:02.58#ibcon#enter sib2, iclass 21, count 2 2006.173.23:45:02.58#ibcon#flushed, iclass 21, count 2 2006.173.23:45:02.58#ibcon#about to write, iclass 21, count 2 2006.173.23:45:02.58#ibcon#wrote, iclass 21, count 2 2006.173.23:45:02.58#ibcon#about to read 3, iclass 21, count 2 2006.173.23:45:02.60#ibcon#read 3, iclass 21, count 2 2006.173.23:45:02.60#ibcon#about to read 4, iclass 21, count 2 2006.173.23:45:02.60#ibcon#read 4, iclass 21, count 2 2006.173.23:45:02.60#ibcon#about to read 5, iclass 21, count 2 2006.173.23:45:02.60#ibcon#read 5, iclass 21, count 2 2006.173.23:45:02.60#ibcon#about to read 6, iclass 21, count 2 2006.173.23:45:02.60#ibcon#read 6, iclass 21, count 2 2006.173.23:45:02.60#ibcon#end of sib2, iclass 21, count 2 2006.173.23:45:02.60#ibcon#*mode == 0, iclass 21, count 2 2006.173.23:45:02.60#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.23:45:02.60#ibcon#[25=AT02-06\r\n] 2006.173.23:45:02.60#ibcon#*before write, iclass 21, count 2 2006.173.23:45:02.60#ibcon#enter sib2, iclass 21, count 2 2006.173.23:45:02.60#ibcon#flushed, iclass 21, count 2 2006.173.23:45:02.60#ibcon#about to write, iclass 21, count 2 2006.173.23:45:02.60#ibcon#wrote, iclass 21, count 2 2006.173.23:45:02.60#ibcon#about to read 3, iclass 21, count 2 2006.173.23:45:02.63#ibcon#read 3, iclass 21, count 2 2006.173.23:45:02.63#ibcon#about to read 4, iclass 21, count 2 2006.173.23:45:02.63#ibcon#read 4, iclass 21, count 2 2006.173.23:45:02.63#ibcon#about to read 5, iclass 21, count 2 2006.173.23:45:02.63#ibcon#read 5, iclass 21, count 2 2006.173.23:45:02.63#ibcon#about to read 6, iclass 21, count 2 2006.173.23:45:02.63#ibcon#read 6, iclass 21, count 2 2006.173.23:45:02.63#ibcon#end of sib2, iclass 21, count 2 2006.173.23:45:02.63#ibcon#*after write, iclass 21, count 2 2006.173.23:45:02.63#ibcon#*before return 0, iclass 21, count 2 2006.173.23:45:02.63#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.23:45:02.63#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.23:45:02.63#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.23:45:02.63#ibcon#ireg 7 cls_cnt 0 2006.173.23:45:02.63#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.23:45:02.75#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.23:45:02.75#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.23:45:02.75#ibcon#enter wrdev, iclass 21, count 0 2006.173.23:45:02.75#ibcon#first serial, iclass 21, count 0 2006.173.23:45:02.75#ibcon#enter sib2, iclass 21, count 0 2006.173.23:45:02.75#ibcon#flushed, iclass 21, count 0 2006.173.23:45:02.75#ibcon#about to write, iclass 21, count 0 2006.173.23:45:02.75#ibcon#wrote, iclass 21, count 0 2006.173.23:45:02.75#ibcon#about to read 3, iclass 21, count 0 2006.173.23:45:02.77#ibcon#read 3, iclass 21, count 0 2006.173.23:45:02.77#ibcon#about to read 4, iclass 21, count 0 2006.173.23:45:02.77#ibcon#read 4, iclass 21, count 0 2006.173.23:45:02.77#ibcon#about to read 5, iclass 21, count 0 2006.173.23:45:02.77#ibcon#read 5, iclass 21, count 0 2006.173.23:45:02.77#ibcon#about to read 6, iclass 21, count 0 2006.173.23:45:02.77#ibcon#read 6, iclass 21, count 0 2006.173.23:45:02.77#ibcon#end of sib2, iclass 21, count 0 2006.173.23:45:02.77#ibcon#*mode == 0, iclass 21, count 0 2006.173.23:45:02.77#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.23:45:02.77#ibcon#[25=USB\r\n] 2006.173.23:45:02.77#ibcon#*before write, iclass 21, count 0 2006.173.23:45:02.77#ibcon#enter sib2, iclass 21, count 0 2006.173.23:45:02.77#ibcon#flushed, iclass 21, count 0 2006.173.23:45:02.77#ibcon#about to write, iclass 21, count 0 2006.173.23:45:02.77#ibcon#wrote, iclass 21, count 0 2006.173.23:45:02.77#ibcon#about to read 3, iclass 21, count 0 2006.173.23:45:02.80#ibcon#read 3, iclass 21, count 0 2006.173.23:45:02.80#ibcon#about to read 4, iclass 21, count 0 2006.173.23:45:02.80#ibcon#read 4, iclass 21, count 0 2006.173.23:45:02.80#ibcon#about to read 5, iclass 21, count 0 2006.173.23:45:02.80#ibcon#read 5, iclass 21, count 0 2006.173.23:45:02.80#ibcon#about to read 6, iclass 21, count 0 2006.173.23:45:02.80#ibcon#read 6, iclass 21, count 0 2006.173.23:45:02.80#ibcon#end of sib2, iclass 21, count 0 2006.173.23:45:02.80#ibcon#*after write, iclass 21, count 0 2006.173.23:45:02.80#ibcon#*before return 0, iclass 21, count 0 2006.173.23:45:02.80#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.23:45:02.80#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.23:45:02.80#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.23:45:02.80#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.23:45:02.80$vck44/valo=3,564.99 2006.173.23:45:02.80#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.23:45:02.80#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.23:45:02.80#ibcon#ireg 17 cls_cnt 0 2006.173.23:45:02.80#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.23:45:02.80#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.23:45:02.80#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.23:45:02.80#ibcon#enter wrdev, iclass 23, count 0 2006.173.23:45:02.80#ibcon#first serial, iclass 23, count 0 2006.173.23:45:02.80#ibcon#enter sib2, iclass 23, count 0 2006.173.23:45:02.80#ibcon#flushed, iclass 23, count 0 2006.173.23:45:02.80#ibcon#about to write, iclass 23, count 0 2006.173.23:45:02.80#ibcon#wrote, iclass 23, count 0 2006.173.23:45:02.80#ibcon#about to read 3, iclass 23, count 0 2006.173.23:45:02.82#ibcon#read 3, iclass 23, count 0 2006.173.23:45:02.82#ibcon#about to read 4, iclass 23, count 0 2006.173.23:45:02.82#ibcon#read 4, iclass 23, count 0 2006.173.23:45:02.82#ibcon#about to read 5, iclass 23, count 0 2006.173.23:45:02.82#ibcon#read 5, iclass 23, count 0 2006.173.23:45:02.82#ibcon#about to read 6, iclass 23, count 0 2006.173.23:45:02.82#ibcon#read 6, iclass 23, count 0 2006.173.23:45:02.82#ibcon#end of sib2, iclass 23, count 0 2006.173.23:45:02.82#ibcon#*mode == 0, iclass 23, count 0 2006.173.23:45:02.82#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.23:45:02.82#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.23:45:02.82#ibcon#*before write, iclass 23, count 0 2006.173.23:45:02.82#ibcon#enter sib2, iclass 23, count 0 2006.173.23:45:02.82#ibcon#flushed, iclass 23, count 0 2006.173.23:45:02.82#ibcon#about to write, iclass 23, count 0 2006.173.23:45:02.82#ibcon#wrote, iclass 23, count 0 2006.173.23:45:02.82#ibcon#about to read 3, iclass 23, count 0 2006.173.23:45:02.86#ibcon#read 3, iclass 23, count 0 2006.173.23:45:02.86#ibcon#about to read 4, iclass 23, count 0 2006.173.23:45:02.86#ibcon#read 4, iclass 23, count 0 2006.173.23:45:02.86#ibcon#about to read 5, iclass 23, count 0 2006.173.23:45:02.86#ibcon#read 5, iclass 23, count 0 2006.173.23:45:02.86#ibcon#about to read 6, iclass 23, count 0 2006.173.23:45:02.86#ibcon#read 6, iclass 23, count 0 2006.173.23:45:02.86#ibcon#end of sib2, iclass 23, count 0 2006.173.23:45:02.86#ibcon#*after write, iclass 23, count 0 2006.173.23:45:02.86#ibcon#*before return 0, iclass 23, count 0 2006.173.23:45:02.86#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.23:45:02.86#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.23:45:02.86#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.23:45:02.86#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.23:45:02.86$vck44/va=3,5 2006.173.23:45:02.86#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.23:45:02.86#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.23:45:02.86#ibcon#ireg 11 cls_cnt 2 2006.173.23:45:02.86#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.23:45:02.92#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.23:45:02.92#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.23:45:02.92#ibcon#enter wrdev, iclass 25, count 2 2006.173.23:45:02.92#ibcon#first serial, iclass 25, count 2 2006.173.23:45:02.92#ibcon#enter sib2, iclass 25, count 2 2006.173.23:45:02.92#ibcon#flushed, iclass 25, count 2 2006.173.23:45:02.92#ibcon#about to write, iclass 25, count 2 2006.173.23:45:02.92#ibcon#wrote, iclass 25, count 2 2006.173.23:45:02.92#ibcon#about to read 3, iclass 25, count 2 2006.173.23:45:02.94#ibcon#read 3, iclass 25, count 2 2006.173.23:45:02.94#ibcon#about to read 4, iclass 25, count 2 2006.173.23:45:02.94#ibcon#read 4, iclass 25, count 2 2006.173.23:45:02.94#ibcon#about to read 5, iclass 25, count 2 2006.173.23:45:02.94#ibcon#read 5, iclass 25, count 2 2006.173.23:45:02.94#ibcon#about to read 6, iclass 25, count 2 2006.173.23:45:02.94#ibcon#read 6, iclass 25, count 2 2006.173.23:45:02.94#ibcon#end of sib2, iclass 25, count 2 2006.173.23:45:02.94#ibcon#*mode == 0, iclass 25, count 2 2006.173.23:45:02.94#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.23:45:02.94#ibcon#[25=AT03-05\r\n] 2006.173.23:45:02.94#ibcon#*before write, iclass 25, count 2 2006.173.23:45:02.94#ibcon#enter sib2, iclass 25, count 2 2006.173.23:45:02.94#ibcon#flushed, iclass 25, count 2 2006.173.23:45:02.94#ibcon#about to write, iclass 25, count 2 2006.173.23:45:02.94#ibcon#wrote, iclass 25, count 2 2006.173.23:45:02.94#ibcon#about to read 3, iclass 25, count 2 2006.173.23:45:02.97#ibcon#read 3, iclass 25, count 2 2006.173.23:45:02.97#ibcon#about to read 4, iclass 25, count 2 2006.173.23:45:02.97#ibcon#read 4, iclass 25, count 2 2006.173.23:45:02.97#ibcon#about to read 5, iclass 25, count 2 2006.173.23:45:02.97#ibcon#read 5, iclass 25, count 2 2006.173.23:45:02.97#ibcon#about to read 6, iclass 25, count 2 2006.173.23:45:02.97#ibcon#read 6, iclass 25, count 2 2006.173.23:45:02.97#ibcon#end of sib2, iclass 25, count 2 2006.173.23:45:02.97#ibcon#*after write, iclass 25, count 2 2006.173.23:45:02.97#ibcon#*before return 0, iclass 25, count 2 2006.173.23:45:02.97#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.23:45:02.97#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.23:45:02.97#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.23:45:02.97#ibcon#ireg 7 cls_cnt 0 2006.173.23:45:02.97#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.23:45:03.09#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.23:45:03.09#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.23:45:03.09#ibcon#enter wrdev, iclass 25, count 0 2006.173.23:45:03.09#ibcon#first serial, iclass 25, count 0 2006.173.23:45:03.09#ibcon#enter sib2, iclass 25, count 0 2006.173.23:45:03.09#ibcon#flushed, iclass 25, count 0 2006.173.23:45:03.09#ibcon#about to write, iclass 25, count 0 2006.173.23:45:03.09#ibcon#wrote, iclass 25, count 0 2006.173.23:45:03.09#ibcon#about to read 3, iclass 25, count 0 2006.173.23:45:03.11#ibcon#read 3, iclass 25, count 0 2006.173.23:45:03.11#ibcon#about to read 4, iclass 25, count 0 2006.173.23:45:03.11#ibcon#read 4, iclass 25, count 0 2006.173.23:45:03.11#ibcon#about to read 5, iclass 25, count 0 2006.173.23:45:03.11#ibcon#read 5, iclass 25, count 0 2006.173.23:45:03.11#ibcon#about to read 6, iclass 25, count 0 2006.173.23:45:03.11#ibcon#read 6, iclass 25, count 0 2006.173.23:45:03.11#ibcon#end of sib2, iclass 25, count 0 2006.173.23:45:03.11#ibcon#*mode == 0, iclass 25, count 0 2006.173.23:45:03.11#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.23:45:03.11#ibcon#[25=USB\r\n] 2006.173.23:45:03.11#ibcon#*before write, iclass 25, count 0 2006.173.23:45:03.11#ibcon#enter sib2, iclass 25, count 0 2006.173.23:45:03.11#ibcon#flushed, iclass 25, count 0 2006.173.23:45:03.11#ibcon#about to write, iclass 25, count 0 2006.173.23:45:03.11#ibcon#wrote, iclass 25, count 0 2006.173.23:45:03.11#ibcon#about to read 3, iclass 25, count 0 2006.173.23:45:03.14#ibcon#read 3, iclass 25, count 0 2006.173.23:45:03.14#ibcon#about to read 4, iclass 25, count 0 2006.173.23:45:03.14#ibcon#read 4, iclass 25, count 0 2006.173.23:45:03.14#ibcon#about to read 5, iclass 25, count 0 2006.173.23:45:03.14#ibcon#read 5, iclass 25, count 0 2006.173.23:45:03.14#ibcon#about to read 6, iclass 25, count 0 2006.173.23:45:03.14#ibcon#read 6, iclass 25, count 0 2006.173.23:45:03.14#ibcon#end of sib2, iclass 25, count 0 2006.173.23:45:03.14#ibcon#*after write, iclass 25, count 0 2006.173.23:45:03.14#ibcon#*before return 0, iclass 25, count 0 2006.173.23:45:03.14#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.23:45:03.14#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.23:45:03.14#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.23:45:03.14#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.23:45:03.14$vck44/valo=4,624.99 2006.173.23:45:03.14#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.23:45:03.14#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.23:45:03.14#ibcon#ireg 17 cls_cnt 0 2006.173.23:45:03.14#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.23:45:03.14#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.23:45:03.14#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.23:45:03.14#ibcon#enter wrdev, iclass 27, count 0 2006.173.23:45:03.14#ibcon#first serial, iclass 27, count 0 2006.173.23:45:03.14#ibcon#enter sib2, iclass 27, count 0 2006.173.23:45:03.14#ibcon#flushed, iclass 27, count 0 2006.173.23:45:03.14#ibcon#about to write, iclass 27, count 0 2006.173.23:45:03.14#ibcon#wrote, iclass 27, count 0 2006.173.23:45:03.14#ibcon#about to read 3, iclass 27, count 0 2006.173.23:45:03.16#ibcon#read 3, iclass 27, count 0 2006.173.23:45:03.16#ibcon#about to read 4, iclass 27, count 0 2006.173.23:45:03.16#ibcon#read 4, iclass 27, count 0 2006.173.23:45:03.16#ibcon#about to read 5, iclass 27, count 0 2006.173.23:45:03.16#ibcon#read 5, iclass 27, count 0 2006.173.23:45:03.16#ibcon#about to read 6, iclass 27, count 0 2006.173.23:45:03.16#ibcon#read 6, iclass 27, count 0 2006.173.23:45:03.16#ibcon#end of sib2, iclass 27, count 0 2006.173.23:45:03.16#ibcon#*mode == 0, iclass 27, count 0 2006.173.23:45:03.16#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.23:45:03.16#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.23:45:03.16#ibcon#*before write, iclass 27, count 0 2006.173.23:45:03.16#ibcon#enter sib2, iclass 27, count 0 2006.173.23:45:03.16#ibcon#flushed, iclass 27, count 0 2006.173.23:45:03.16#ibcon#about to write, iclass 27, count 0 2006.173.23:45:03.16#ibcon#wrote, iclass 27, count 0 2006.173.23:45:03.16#ibcon#about to read 3, iclass 27, count 0 2006.173.23:45:03.20#ibcon#read 3, iclass 27, count 0 2006.173.23:45:03.20#ibcon#about to read 4, iclass 27, count 0 2006.173.23:45:03.20#ibcon#read 4, iclass 27, count 0 2006.173.23:45:03.20#ibcon#about to read 5, iclass 27, count 0 2006.173.23:45:03.20#ibcon#read 5, iclass 27, count 0 2006.173.23:45:03.20#ibcon#about to read 6, iclass 27, count 0 2006.173.23:45:03.20#ibcon#read 6, iclass 27, count 0 2006.173.23:45:03.20#ibcon#end of sib2, iclass 27, count 0 2006.173.23:45:03.20#ibcon#*after write, iclass 27, count 0 2006.173.23:45:03.20#ibcon#*before return 0, iclass 27, count 0 2006.173.23:45:03.20#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.23:45:03.20#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.23:45:03.20#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.23:45:03.20#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.23:45:03.20$vck44/va=4,6 2006.173.23:45:03.20#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.23:45:03.20#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.23:45:03.20#ibcon#ireg 11 cls_cnt 2 2006.173.23:45:03.20#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.23:45:03.26#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.23:45:03.26#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.23:45:03.26#ibcon#enter wrdev, iclass 29, count 2 2006.173.23:45:03.26#ibcon#first serial, iclass 29, count 2 2006.173.23:45:03.26#ibcon#enter sib2, iclass 29, count 2 2006.173.23:45:03.26#ibcon#flushed, iclass 29, count 2 2006.173.23:45:03.26#ibcon#about to write, iclass 29, count 2 2006.173.23:45:03.26#ibcon#wrote, iclass 29, count 2 2006.173.23:45:03.26#ibcon#about to read 3, iclass 29, count 2 2006.173.23:45:03.28#ibcon#read 3, iclass 29, count 2 2006.173.23:45:03.28#ibcon#about to read 4, iclass 29, count 2 2006.173.23:45:03.28#ibcon#read 4, iclass 29, count 2 2006.173.23:45:03.28#ibcon#about to read 5, iclass 29, count 2 2006.173.23:45:03.28#ibcon#read 5, iclass 29, count 2 2006.173.23:45:03.28#ibcon#about to read 6, iclass 29, count 2 2006.173.23:45:03.28#ibcon#read 6, iclass 29, count 2 2006.173.23:45:03.28#ibcon#end of sib2, iclass 29, count 2 2006.173.23:45:03.28#ibcon#*mode == 0, iclass 29, count 2 2006.173.23:45:03.28#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.23:45:03.28#ibcon#[25=AT04-06\r\n] 2006.173.23:45:03.28#ibcon#*before write, iclass 29, count 2 2006.173.23:45:03.28#ibcon#enter sib2, iclass 29, count 2 2006.173.23:45:03.28#ibcon#flushed, iclass 29, count 2 2006.173.23:45:03.28#ibcon#about to write, iclass 29, count 2 2006.173.23:45:03.28#ibcon#wrote, iclass 29, count 2 2006.173.23:45:03.28#ibcon#about to read 3, iclass 29, count 2 2006.173.23:45:03.31#ibcon#read 3, iclass 29, count 2 2006.173.23:45:03.31#ibcon#about to read 4, iclass 29, count 2 2006.173.23:45:03.31#ibcon#read 4, iclass 29, count 2 2006.173.23:45:03.31#ibcon#about to read 5, iclass 29, count 2 2006.173.23:45:03.31#ibcon#read 5, iclass 29, count 2 2006.173.23:45:03.31#ibcon#about to read 6, iclass 29, count 2 2006.173.23:45:03.31#ibcon#read 6, iclass 29, count 2 2006.173.23:45:03.31#ibcon#end of sib2, iclass 29, count 2 2006.173.23:45:03.31#ibcon#*after write, iclass 29, count 2 2006.173.23:45:03.31#ibcon#*before return 0, iclass 29, count 2 2006.173.23:45:03.31#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.23:45:03.31#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.23:45:03.31#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.23:45:03.31#ibcon#ireg 7 cls_cnt 0 2006.173.23:45:03.31#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.23:45:03.43#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.23:45:03.43#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.23:45:03.43#ibcon#enter wrdev, iclass 29, count 0 2006.173.23:45:03.43#ibcon#first serial, iclass 29, count 0 2006.173.23:45:03.43#ibcon#enter sib2, iclass 29, count 0 2006.173.23:45:03.43#ibcon#flushed, iclass 29, count 0 2006.173.23:45:03.43#ibcon#about to write, iclass 29, count 0 2006.173.23:45:03.43#ibcon#wrote, iclass 29, count 0 2006.173.23:45:03.43#ibcon#about to read 3, iclass 29, count 0 2006.173.23:45:03.45#ibcon#read 3, iclass 29, count 0 2006.173.23:45:03.45#ibcon#about to read 4, iclass 29, count 0 2006.173.23:45:03.45#ibcon#read 4, iclass 29, count 0 2006.173.23:45:03.45#ibcon#about to read 5, iclass 29, count 0 2006.173.23:45:03.45#ibcon#read 5, iclass 29, count 0 2006.173.23:45:03.45#ibcon#about to read 6, iclass 29, count 0 2006.173.23:45:03.45#ibcon#read 6, iclass 29, count 0 2006.173.23:45:03.45#ibcon#end of sib2, iclass 29, count 0 2006.173.23:45:03.45#ibcon#*mode == 0, iclass 29, count 0 2006.173.23:45:03.45#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.23:45:03.45#ibcon#[25=USB\r\n] 2006.173.23:45:03.45#ibcon#*before write, iclass 29, count 0 2006.173.23:45:03.45#ibcon#enter sib2, iclass 29, count 0 2006.173.23:45:03.45#ibcon#flushed, iclass 29, count 0 2006.173.23:45:03.45#ibcon#about to write, iclass 29, count 0 2006.173.23:45:03.45#ibcon#wrote, iclass 29, count 0 2006.173.23:45:03.45#ibcon#about to read 3, iclass 29, count 0 2006.173.23:45:03.48#ibcon#read 3, iclass 29, count 0 2006.173.23:45:03.48#ibcon#about to read 4, iclass 29, count 0 2006.173.23:45:03.48#ibcon#read 4, iclass 29, count 0 2006.173.23:45:03.48#ibcon#about to read 5, iclass 29, count 0 2006.173.23:45:03.48#ibcon#read 5, iclass 29, count 0 2006.173.23:45:03.48#ibcon#about to read 6, iclass 29, count 0 2006.173.23:45:03.48#ibcon#read 6, iclass 29, count 0 2006.173.23:45:03.48#ibcon#end of sib2, iclass 29, count 0 2006.173.23:45:03.48#ibcon#*after write, iclass 29, count 0 2006.173.23:45:03.48#ibcon#*before return 0, iclass 29, count 0 2006.173.23:45:03.48#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.23:45:03.48#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.23:45:03.48#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.23:45:03.48#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.23:45:03.48$vck44/valo=5,734.99 2006.173.23:45:03.48#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.23:45:03.48#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.23:45:03.48#ibcon#ireg 17 cls_cnt 0 2006.173.23:45:03.48#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.23:45:03.48#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.23:45:03.48#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.23:45:03.48#ibcon#enter wrdev, iclass 31, count 0 2006.173.23:45:03.48#ibcon#first serial, iclass 31, count 0 2006.173.23:45:03.48#ibcon#enter sib2, iclass 31, count 0 2006.173.23:45:03.48#ibcon#flushed, iclass 31, count 0 2006.173.23:45:03.48#ibcon#about to write, iclass 31, count 0 2006.173.23:45:03.48#ibcon#wrote, iclass 31, count 0 2006.173.23:45:03.48#ibcon#about to read 3, iclass 31, count 0 2006.173.23:45:03.50#ibcon#read 3, iclass 31, count 0 2006.173.23:45:03.50#ibcon#about to read 4, iclass 31, count 0 2006.173.23:45:03.50#ibcon#read 4, iclass 31, count 0 2006.173.23:45:03.50#ibcon#about to read 5, iclass 31, count 0 2006.173.23:45:03.50#ibcon#read 5, iclass 31, count 0 2006.173.23:45:03.50#ibcon#about to read 6, iclass 31, count 0 2006.173.23:45:03.50#ibcon#read 6, iclass 31, count 0 2006.173.23:45:03.50#ibcon#end of sib2, iclass 31, count 0 2006.173.23:45:03.50#ibcon#*mode == 0, iclass 31, count 0 2006.173.23:45:03.50#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.23:45:03.50#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.23:45:03.50#ibcon#*before write, iclass 31, count 0 2006.173.23:45:03.50#ibcon#enter sib2, iclass 31, count 0 2006.173.23:45:03.50#ibcon#flushed, iclass 31, count 0 2006.173.23:45:03.50#ibcon#about to write, iclass 31, count 0 2006.173.23:45:03.50#ibcon#wrote, iclass 31, count 0 2006.173.23:45:03.50#ibcon#about to read 3, iclass 31, count 0 2006.173.23:45:03.54#ibcon#read 3, iclass 31, count 0 2006.173.23:45:03.54#ibcon#about to read 4, iclass 31, count 0 2006.173.23:45:03.54#ibcon#read 4, iclass 31, count 0 2006.173.23:45:03.54#ibcon#about to read 5, iclass 31, count 0 2006.173.23:45:03.54#ibcon#read 5, iclass 31, count 0 2006.173.23:45:03.54#ibcon#about to read 6, iclass 31, count 0 2006.173.23:45:03.54#ibcon#read 6, iclass 31, count 0 2006.173.23:45:03.54#ibcon#end of sib2, iclass 31, count 0 2006.173.23:45:03.54#ibcon#*after write, iclass 31, count 0 2006.173.23:45:03.54#ibcon#*before return 0, iclass 31, count 0 2006.173.23:45:03.54#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.23:45:03.54#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.23:45:03.54#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.23:45:03.54#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.23:45:03.54$vck44/va=5,4 2006.173.23:45:03.54#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.173.23:45:03.54#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.173.23:45:03.54#ibcon#ireg 11 cls_cnt 2 2006.173.23:45:03.54#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.23:45:03.60#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.23:45:03.60#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.23:45:03.60#ibcon#enter wrdev, iclass 33, count 2 2006.173.23:45:03.60#ibcon#first serial, iclass 33, count 2 2006.173.23:45:03.60#ibcon#enter sib2, iclass 33, count 2 2006.173.23:45:03.60#ibcon#flushed, iclass 33, count 2 2006.173.23:45:03.60#ibcon#about to write, iclass 33, count 2 2006.173.23:45:03.60#ibcon#wrote, iclass 33, count 2 2006.173.23:45:03.60#ibcon#about to read 3, iclass 33, count 2 2006.173.23:45:03.62#ibcon#read 3, iclass 33, count 2 2006.173.23:45:03.62#ibcon#about to read 4, iclass 33, count 2 2006.173.23:45:03.62#ibcon#read 4, iclass 33, count 2 2006.173.23:45:03.62#ibcon#about to read 5, iclass 33, count 2 2006.173.23:45:03.62#ibcon#read 5, iclass 33, count 2 2006.173.23:45:03.62#ibcon#about to read 6, iclass 33, count 2 2006.173.23:45:03.62#ibcon#read 6, iclass 33, count 2 2006.173.23:45:03.62#ibcon#end of sib2, iclass 33, count 2 2006.173.23:45:03.62#ibcon#*mode == 0, iclass 33, count 2 2006.173.23:45:03.62#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.173.23:45:03.62#ibcon#[25=AT05-04\r\n] 2006.173.23:45:03.62#ibcon#*before write, iclass 33, count 2 2006.173.23:45:03.62#ibcon#enter sib2, iclass 33, count 2 2006.173.23:45:03.62#ibcon#flushed, iclass 33, count 2 2006.173.23:45:03.62#ibcon#about to write, iclass 33, count 2 2006.173.23:45:03.62#ibcon#wrote, iclass 33, count 2 2006.173.23:45:03.62#ibcon#about to read 3, iclass 33, count 2 2006.173.23:45:03.65#ibcon#read 3, iclass 33, count 2 2006.173.23:45:03.65#ibcon#about to read 4, iclass 33, count 2 2006.173.23:45:03.65#ibcon#read 4, iclass 33, count 2 2006.173.23:45:03.65#ibcon#about to read 5, iclass 33, count 2 2006.173.23:45:03.65#ibcon#read 5, iclass 33, count 2 2006.173.23:45:03.65#ibcon#about to read 6, iclass 33, count 2 2006.173.23:45:03.65#ibcon#read 6, iclass 33, count 2 2006.173.23:45:03.65#ibcon#end of sib2, iclass 33, count 2 2006.173.23:45:03.65#ibcon#*after write, iclass 33, count 2 2006.173.23:45:03.65#ibcon#*before return 0, iclass 33, count 2 2006.173.23:45:03.65#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.23:45:03.65#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.173.23:45:03.65#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.173.23:45:03.65#ibcon#ireg 7 cls_cnt 0 2006.173.23:45:03.65#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.23:45:03.77#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.23:45:03.77#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.23:45:03.77#ibcon#enter wrdev, iclass 33, count 0 2006.173.23:45:03.77#ibcon#first serial, iclass 33, count 0 2006.173.23:45:03.77#ibcon#enter sib2, iclass 33, count 0 2006.173.23:45:03.77#ibcon#flushed, iclass 33, count 0 2006.173.23:45:03.77#ibcon#about to write, iclass 33, count 0 2006.173.23:45:03.77#ibcon#wrote, iclass 33, count 0 2006.173.23:45:03.77#ibcon#about to read 3, iclass 33, count 0 2006.173.23:45:03.79#ibcon#read 3, iclass 33, count 0 2006.173.23:45:03.79#ibcon#about to read 4, iclass 33, count 0 2006.173.23:45:03.79#ibcon#read 4, iclass 33, count 0 2006.173.23:45:03.79#ibcon#about to read 5, iclass 33, count 0 2006.173.23:45:03.79#ibcon#read 5, iclass 33, count 0 2006.173.23:45:03.79#ibcon#about to read 6, iclass 33, count 0 2006.173.23:45:03.79#ibcon#read 6, iclass 33, count 0 2006.173.23:45:03.79#ibcon#end of sib2, iclass 33, count 0 2006.173.23:45:03.79#ibcon#*mode == 0, iclass 33, count 0 2006.173.23:45:03.79#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.23:45:03.79#ibcon#[25=USB\r\n] 2006.173.23:45:03.79#ibcon#*before write, iclass 33, count 0 2006.173.23:45:03.79#ibcon#enter sib2, iclass 33, count 0 2006.173.23:45:03.79#ibcon#flushed, iclass 33, count 0 2006.173.23:45:03.79#ibcon#about to write, iclass 33, count 0 2006.173.23:45:03.79#ibcon#wrote, iclass 33, count 0 2006.173.23:45:03.79#ibcon#about to read 3, iclass 33, count 0 2006.173.23:45:03.82#ibcon#read 3, iclass 33, count 0 2006.173.23:45:03.82#ibcon#about to read 4, iclass 33, count 0 2006.173.23:45:03.82#ibcon#read 4, iclass 33, count 0 2006.173.23:45:03.82#ibcon#about to read 5, iclass 33, count 0 2006.173.23:45:03.82#ibcon#read 5, iclass 33, count 0 2006.173.23:45:03.82#ibcon#about to read 6, iclass 33, count 0 2006.173.23:45:03.82#ibcon#read 6, iclass 33, count 0 2006.173.23:45:03.82#ibcon#end of sib2, iclass 33, count 0 2006.173.23:45:03.82#ibcon#*after write, iclass 33, count 0 2006.173.23:45:03.82#ibcon#*before return 0, iclass 33, count 0 2006.173.23:45:03.82#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.23:45:03.82#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.173.23:45:03.82#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.23:45:03.82#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.23:45:03.82$vck44/valo=6,814.99 2006.173.23:45:03.82#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.173.23:45:03.82#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.173.23:45:03.82#ibcon#ireg 17 cls_cnt 0 2006.173.23:45:03.82#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.23:45:03.82#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.173.23:45:03.82#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.23:45:03.82#ibcon#enter wrdev, iclass 35, count 0 2006.173.23:45:03.82#ibcon#first serial, iclass 35, count 0 2006.173.23:45:03.82#ibcon#enter sib2, iclass 35, count 0 2006.173.23:45:03.82#ibcon#flushed, iclass 35, count 0 2006.173.23:45:03.82#ibcon#about to write, iclass 35, count 0 2006.173.23:45:03.82#ibcon#wrote, iclass 35, count 0 2006.173.23:45:03.82#ibcon#about to read 3, iclass 35, count 0 2006.173.23:45:03.84#ibcon#read 3, iclass 35, count 0 2006.173.23:45:03.84#ibcon#about to read 4, iclass 35, count 0 2006.173.23:45:03.84#ibcon#read 4, iclass 35, count 0 2006.173.23:45:03.84#ibcon#about to read 5, iclass 35, count 0 2006.173.23:45:03.84#ibcon#read 5, iclass 35, count 0 2006.173.23:45:03.84#ibcon#about to read 6, iclass 35, count 0 2006.173.23:45:03.84#ibcon#read 6, iclass 35, count 0 2006.173.23:45:03.84#ibcon#end of sib2, iclass 35, count 0 2006.173.23:45:03.84#ibcon#*mode == 0, iclass 35, count 0 2006.173.23:45:03.84#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.23:45:03.84#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.23:45:03.84#ibcon#*before write, iclass 35, count 0 2006.173.23:45:03.84#ibcon#enter sib2, iclass 35, count 0 2006.173.23:45:03.84#ibcon#flushed, iclass 35, count 0 2006.173.23:45:03.84#ibcon#about to write, iclass 35, count 0 2006.173.23:45:03.84#ibcon#wrote, iclass 35, count 0 2006.173.23:45:03.84#ibcon#about to read 3, iclass 35, count 0 2006.173.23:45:03.88#ibcon#read 3, iclass 35, count 0 2006.173.23:45:03.88#ibcon#about to read 4, iclass 35, count 0 2006.173.23:45:03.88#ibcon#read 4, iclass 35, count 0 2006.173.23:45:03.88#ibcon#about to read 5, iclass 35, count 0 2006.173.23:45:03.88#ibcon#read 5, iclass 35, count 0 2006.173.23:45:03.88#ibcon#about to read 6, iclass 35, count 0 2006.173.23:45:03.88#ibcon#read 6, iclass 35, count 0 2006.173.23:45:03.88#ibcon#end of sib2, iclass 35, count 0 2006.173.23:45:03.88#ibcon#*after write, iclass 35, count 0 2006.173.23:45:03.88#ibcon#*before return 0, iclass 35, count 0 2006.173.23:45:03.88#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.173.23:45:03.88#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.173.23:45:03.88#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.23:45:03.88#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.23:45:03.88$vck44/va=6,3 2006.173.23:45:03.88#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.173.23:45:03.88#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.173.23:45:03.88#ibcon#ireg 11 cls_cnt 2 2006.173.23:45:03.88#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.23:45:03.94#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.173.23:45:03.94#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.23:45:03.94#ibcon#enter wrdev, iclass 37, count 2 2006.173.23:45:03.94#ibcon#first serial, iclass 37, count 2 2006.173.23:45:03.94#ibcon#enter sib2, iclass 37, count 2 2006.173.23:45:03.94#ibcon#flushed, iclass 37, count 2 2006.173.23:45:03.94#ibcon#about to write, iclass 37, count 2 2006.173.23:45:03.94#ibcon#wrote, iclass 37, count 2 2006.173.23:45:03.94#ibcon#about to read 3, iclass 37, count 2 2006.173.23:45:03.96#ibcon#read 3, iclass 37, count 2 2006.173.23:45:03.96#ibcon#about to read 4, iclass 37, count 2 2006.173.23:45:03.96#ibcon#read 4, iclass 37, count 2 2006.173.23:45:03.96#ibcon#about to read 5, iclass 37, count 2 2006.173.23:45:03.96#ibcon#read 5, iclass 37, count 2 2006.173.23:45:03.96#ibcon#about to read 6, iclass 37, count 2 2006.173.23:45:03.96#ibcon#read 6, iclass 37, count 2 2006.173.23:45:03.96#ibcon#end of sib2, iclass 37, count 2 2006.173.23:45:03.96#ibcon#*mode == 0, iclass 37, count 2 2006.173.23:45:03.96#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.173.23:45:03.96#ibcon#[25=AT06-03\r\n] 2006.173.23:45:03.96#ibcon#*before write, iclass 37, count 2 2006.173.23:45:03.96#ibcon#enter sib2, iclass 37, count 2 2006.173.23:45:03.96#ibcon#flushed, iclass 37, count 2 2006.173.23:45:03.96#ibcon#about to write, iclass 37, count 2 2006.173.23:45:03.96#ibcon#wrote, iclass 37, count 2 2006.173.23:45:03.96#ibcon#about to read 3, iclass 37, count 2 2006.173.23:45:03.99#ibcon#read 3, iclass 37, count 2 2006.173.23:45:03.99#ibcon#about to read 4, iclass 37, count 2 2006.173.23:45:03.99#ibcon#read 4, iclass 37, count 2 2006.173.23:45:03.99#ibcon#about to read 5, iclass 37, count 2 2006.173.23:45:03.99#ibcon#read 5, iclass 37, count 2 2006.173.23:45:03.99#ibcon#about to read 6, iclass 37, count 2 2006.173.23:45:03.99#ibcon#read 6, iclass 37, count 2 2006.173.23:45:03.99#ibcon#end of sib2, iclass 37, count 2 2006.173.23:45:03.99#ibcon#*after write, iclass 37, count 2 2006.173.23:45:03.99#ibcon#*before return 0, iclass 37, count 2 2006.173.23:45:03.99#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.173.23:45:03.99#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.173.23:45:03.99#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.173.23:45:03.99#ibcon#ireg 7 cls_cnt 0 2006.173.23:45:03.99#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.23:45:04.11#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.173.23:45:04.11#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.23:45:04.11#ibcon#enter wrdev, iclass 37, count 0 2006.173.23:45:04.11#ibcon#first serial, iclass 37, count 0 2006.173.23:45:04.11#ibcon#enter sib2, iclass 37, count 0 2006.173.23:45:04.11#ibcon#flushed, iclass 37, count 0 2006.173.23:45:04.11#ibcon#about to write, iclass 37, count 0 2006.173.23:45:04.11#ibcon#wrote, iclass 37, count 0 2006.173.23:45:04.11#ibcon#about to read 3, iclass 37, count 0 2006.173.23:45:04.13#ibcon#read 3, iclass 37, count 0 2006.173.23:45:04.13#ibcon#about to read 4, iclass 37, count 0 2006.173.23:45:04.13#ibcon#read 4, iclass 37, count 0 2006.173.23:45:04.13#ibcon#about to read 5, iclass 37, count 0 2006.173.23:45:04.13#ibcon#read 5, iclass 37, count 0 2006.173.23:45:04.13#ibcon#about to read 6, iclass 37, count 0 2006.173.23:45:04.13#ibcon#read 6, iclass 37, count 0 2006.173.23:45:04.13#ibcon#end of sib2, iclass 37, count 0 2006.173.23:45:04.13#ibcon#*mode == 0, iclass 37, count 0 2006.173.23:45:04.13#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.23:45:04.13#ibcon#[25=USB\r\n] 2006.173.23:45:04.13#ibcon#*before write, iclass 37, count 0 2006.173.23:45:04.13#ibcon#enter sib2, iclass 37, count 0 2006.173.23:45:04.13#ibcon#flushed, iclass 37, count 0 2006.173.23:45:04.13#ibcon#about to write, iclass 37, count 0 2006.173.23:45:04.13#ibcon#wrote, iclass 37, count 0 2006.173.23:45:04.13#ibcon#about to read 3, iclass 37, count 0 2006.173.23:45:04.16#ibcon#read 3, iclass 37, count 0 2006.173.23:45:04.16#ibcon#about to read 4, iclass 37, count 0 2006.173.23:45:04.16#ibcon#read 4, iclass 37, count 0 2006.173.23:45:04.16#ibcon#about to read 5, iclass 37, count 0 2006.173.23:45:04.16#ibcon#read 5, iclass 37, count 0 2006.173.23:45:04.16#ibcon#about to read 6, iclass 37, count 0 2006.173.23:45:04.16#ibcon#read 6, iclass 37, count 0 2006.173.23:45:04.16#ibcon#end of sib2, iclass 37, count 0 2006.173.23:45:04.16#ibcon#*after write, iclass 37, count 0 2006.173.23:45:04.16#ibcon#*before return 0, iclass 37, count 0 2006.173.23:45:04.16#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.173.23:45:04.16#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.173.23:45:04.16#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.23:45:04.16#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.23:45:04.16$vck44/valo=7,864.99 2006.173.23:45:04.16#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.173.23:45:04.16#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.173.23:45:04.16#ibcon#ireg 17 cls_cnt 0 2006.173.23:45:04.16#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.23:45:04.16#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.173.23:45:04.16#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.23:45:04.16#ibcon#enter wrdev, iclass 39, count 0 2006.173.23:45:04.16#ibcon#first serial, iclass 39, count 0 2006.173.23:45:04.16#ibcon#enter sib2, iclass 39, count 0 2006.173.23:45:04.16#ibcon#flushed, iclass 39, count 0 2006.173.23:45:04.16#ibcon#about to write, iclass 39, count 0 2006.173.23:45:04.16#ibcon#wrote, iclass 39, count 0 2006.173.23:45:04.16#ibcon#about to read 3, iclass 39, count 0 2006.173.23:45:04.18#ibcon#read 3, iclass 39, count 0 2006.173.23:45:04.18#ibcon#about to read 4, iclass 39, count 0 2006.173.23:45:04.18#ibcon#read 4, iclass 39, count 0 2006.173.23:45:04.18#ibcon#about to read 5, iclass 39, count 0 2006.173.23:45:04.18#ibcon#read 5, iclass 39, count 0 2006.173.23:45:04.18#ibcon#about to read 6, iclass 39, count 0 2006.173.23:45:04.18#ibcon#read 6, iclass 39, count 0 2006.173.23:45:04.18#ibcon#end of sib2, iclass 39, count 0 2006.173.23:45:04.18#ibcon#*mode == 0, iclass 39, count 0 2006.173.23:45:04.18#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.23:45:04.18#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.23:45:04.18#ibcon#*before write, iclass 39, count 0 2006.173.23:45:04.18#ibcon#enter sib2, iclass 39, count 0 2006.173.23:45:04.18#ibcon#flushed, iclass 39, count 0 2006.173.23:45:04.18#ibcon#about to write, iclass 39, count 0 2006.173.23:45:04.18#ibcon#wrote, iclass 39, count 0 2006.173.23:45:04.18#ibcon#about to read 3, iclass 39, count 0 2006.173.23:45:04.22#ibcon#read 3, iclass 39, count 0 2006.173.23:45:04.22#ibcon#about to read 4, iclass 39, count 0 2006.173.23:45:04.22#ibcon#read 4, iclass 39, count 0 2006.173.23:45:04.22#ibcon#about to read 5, iclass 39, count 0 2006.173.23:45:04.22#ibcon#read 5, iclass 39, count 0 2006.173.23:45:04.22#ibcon#about to read 6, iclass 39, count 0 2006.173.23:45:04.22#ibcon#read 6, iclass 39, count 0 2006.173.23:45:04.22#ibcon#end of sib2, iclass 39, count 0 2006.173.23:45:04.22#ibcon#*after write, iclass 39, count 0 2006.173.23:45:04.22#ibcon#*before return 0, iclass 39, count 0 2006.173.23:45:04.22#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.173.23:45:04.22#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.173.23:45:04.22#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.23:45:04.22#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.23:45:04.22$vck44/va=7,4 2006.173.23:45:04.22#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.23:45:04.22#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.23:45:04.22#ibcon#ireg 11 cls_cnt 2 2006.173.23:45:04.22#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.23:45:04.28#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.23:45:04.28#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.23:45:04.28#ibcon#enter wrdev, iclass 3, count 2 2006.173.23:45:04.28#ibcon#first serial, iclass 3, count 2 2006.173.23:45:04.28#ibcon#enter sib2, iclass 3, count 2 2006.173.23:45:04.28#ibcon#flushed, iclass 3, count 2 2006.173.23:45:04.28#ibcon#about to write, iclass 3, count 2 2006.173.23:45:04.28#ibcon#wrote, iclass 3, count 2 2006.173.23:45:04.28#ibcon#about to read 3, iclass 3, count 2 2006.173.23:45:04.30#ibcon#read 3, iclass 3, count 2 2006.173.23:45:04.30#ibcon#about to read 4, iclass 3, count 2 2006.173.23:45:04.30#ibcon#read 4, iclass 3, count 2 2006.173.23:45:04.30#ibcon#about to read 5, iclass 3, count 2 2006.173.23:45:04.30#ibcon#read 5, iclass 3, count 2 2006.173.23:45:04.30#ibcon#about to read 6, iclass 3, count 2 2006.173.23:45:04.30#ibcon#read 6, iclass 3, count 2 2006.173.23:45:04.30#ibcon#end of sib2, iclass 3, count 2 2006.173.23:45:04.30#ibcon#*mode == 0, iclass 3, count 2 2006.173.23:45:04.30#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.23:45:04.30#ibcon#[25=AT07-04\r\n] 2006.173.23:45:04.30#ibcon#*before write, iclass 3, count 2 2006.173.23:45:04.30#ibcon#enter sib2, iclass 3, count 2 2006.173.23:45:04.30#ibcon#flushed, iclass 3, count 2 2006.173.23:45:04.30#ibcon#about to write, iclass 3, count 2 2006.173.23:45:04.30#ibcon#wrote, iclass 3, count 2 2006.173.23:45:04.30#ibcon#about to read 3, iclass 3, count 2 2006.173.23:45:04.33#ibcon#read 3, iclass 3, count 2 2006.173.23:45:04.33#ibcon#about to read 4, iclass 3, count 2 2006.173.23:45:04.33#ibcon#read 4, iclass 3, count 2 2006.173.23:45:04.33#ibcon#about to read 5, iclass 3, count 2 2006.173.23:45:04.33#ibcon#read 5, iclass 3, count 2 2006.173.23:45:04.33#ibcon#about to read 6, iclass 3, count 2 2006.173.23:45:04.33#ibcon#read 6, iclass 3, count 2 2006.173.23:45:04.33#ibcon#end of sib2, iclass 3, count 2 2006.173.23:45:04.33#ibcon#*after write, iclass 3, count 2 2006.173.23:45:04.33#ibcon#*before return 0, iclass 3, count 2 2006.173.23:45:04.33#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.23:45:04.33#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.23:45:04.33#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.23:45:04.33#ibcon#ireg 7 cls_cnt 0 2006.173.23:45:04.33#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.23:45:04.45#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.23:45:04.45#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.23:45:04.45#ibcon#enter wrdev, iclass 3, count 0 2006.173.23:45:04.45#ibcon#first serial, iclass 3, count 0 2006.173.23:45:04.45#ibcon#enter sib2, iclass 3, count 0 2006.173.23:45:04.45#ibcon#flushed, iclass 3, count 0 2006.173.23:45:04.45#ibcon#about to write, iclass 3, count 0 2006.173.23:45:04.45#ibcon#wrote, iclass 3, count 0 2006.173.23:45:04.45#ibcon#about to read 3, iclass 3, count 0 2006.173.23:45:04.47#ibcon#read 3, iclass 3, count 0 2006.173.23:45:04.47#ibcon#about to read 4, iclass 3, count 0 2006.173.23:45:04.47#ibcon#read 4, iclass 3, count 0 2006.173.23:45:04.47#ibcon#about to read 5, iclass 3, count 0 2006.173.23:45:04.47#ibcon#read 5, iclass 3, count 0 2006.173.23:45:04.47#ibcon#about to read 6, iclass 3, count 0 2006.173.23:45:04.47#ibcon#read 6, iclass 3, count 0 2006.173.23:45:04.47#ibcon#end of sib2, iclass 3, count 0 2006.173.23:45:04.47#ibcon#*mode == 0, iclass 3, count 0 2006.173.23:45:04.47#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.23:45:04.47#ibcon#[25=USB\r\n] 2006.173.23:45:04.47#ibcon#*before write, iclass 3, count 0 2006.173.23:45:04.47#ibcon#enter sib2, iclass 3, count 0 2006.173.23:45:04.47#ibcon#flushed, iclass 3, count 0 2006.173.23:45:04.47#ibcon#about to write, iclass 3, count 0 2006.173.23:45:04.47#ibcon#wrote, iclass 3, count 0 2006.173.23:45:04.47#ibcon#about to read 3, iclass 3, count 0 2006.173.23:45:04.50#ibcon#read 3, iclass 3, count 0 2006.173.23:45:04.50#ibcon#about to read 4, iclass 3, count 0 2006.173.23:45:04.50#ibcon#read 4, iclass 3, count 0 2006.173.23:45:04.50#ibcon#about to read 5, iclass 3, count 0 2006.173.23:45:04.50#ibcon#read 5, iclass 3, count 0 2006.173.23:45:04.50#ibcon#about to read 6, iclass 3, count 0 2006.173.23:45:04.50#ibcon#read 6, iclass 3, count 0 2006.173.23:45:04.50#ibcon#end of sib2, iclass 3, count 0 2006.173.23:45:04.50#ibcon#*after write, iclass 3, count 0 2006.173.23:45:04.50#ibcon#*before return 0, iclass 3, count 0 2006.173.23:45:04.50#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.23:45:04.50#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.23:45:04.50#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.23:45:04.50#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.23:45:04.50$vck44/valo=8,884.99 2006.173.23:45:04.50#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.23:45:04.50#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.23:45:04.50#ibcon#ireg 17 cls_cnt 0 2006.173.23:45:04.50#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.23:45:04.50#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.23:45:04.50#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.23:45:04.50#ibcon#enter wrdev, iclass 5, count 0 2006.173.23:45:04.50#ibcon#first serial, iclass 5, count 0 2006.173.23:45:04.50#ibcon#enter sib2, iclass 5, count 0 2006.173.23:45:04.50#ibcon#flushed, iclass 5, count 0 2006.173.23:45:04.50#ibcon#about to write, iclass 5, count 0 2006.173.23:45:04.50#ibcon#wrote, iclass 5, count 0 2006.173.23:45:04.50#ibcon#about to read 3, iclass 5, count 0 2006.173.23:45:04.52#ibcon#read 3, iclass 5, count 0 2006.173.23:45:04.52#ibcon#about to read 4, iclass 5, count 0 2006.173.23:45:04.52#ibcon#read 4, iclass 5, count 0 2006.173.23:45:04.52#ibcon#about to read 5, iclass 5, count 0 2006.173.23:45:04.52#ibcon#read 5, iclass 5, count 0 2006.173.23:45:04.52#ibcon#about to read 6, iclass 5, count 0 2006.173.23:45:04.52#ibcon#read 6, iclass 5, count 0 2006.173.23:45:04.52#ibcon#end of sib2, iclass 5, count 0 2006.173.23:45:04.52#ibcon#*mode == 0, iclass 5, count 0 2006.173.23:45:04.52#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.23:45:04.52#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.23:45:04.52#ibcon#*before write, iclass 5, count 0 2006.173.23:45:04.52#ibcon#enter sib2, iclass 5, count 0 2006.173.23:45:04.52#ibcon#flushed, iclass 5, count 0 2006.173.23:45:04.52#ibcon#about to write, iclass 5, count 0 2006.173.23:45:04.52#ibcon#wrote, iclass 5, count 0 2006.173.23:45:04.52#ibcon#about to read 3, iclass 5, count 0 2006.173.23:45:04.56#ibcon#read 3, iclass 5, count 0 2006.173.23:45:04.56#ibcon#about to read 4, iclass 5, count 0 2006.173.23:45:04.56#ibcon#read 4, iclass 5, count 0 2006.173.23:45:04.56#ibcon#about to read 5, iclass 5, count 0 2006.173.23:45:04.56#ibcon#read 5, iclass 5, count 0 2006.173.23:45:04.56#ibcon#about to read 6, iclass 5, count 0 2006.173.23:45:04.56#ibcon#read 6, iclass 5, count 0 2006.173.23:45:04.56#ibcon#end of sib2, iclass 5, count 0 2006.173.23:45:04.56#ibcon#*after write, iclass 5, count 0 2006.173.23:45:04.56#ibcon#*before return 0, iclass 5, count 0 2006.173.23:45:04.56#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.23:45:04.56#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.23:45:04.56#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.23:45:04.56#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.23:45:04.56$vck44/va=8,4 2006.173.23:45:04.56#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.173.23:45:04.56#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.173.23:45:04.56#ibcon#ireg 11 cls_cnt 2 2006.173.23:45:04.56#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.23:45:04.62#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.23:45:04.62#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.23:45:04.62#ibcon#enter wrdev, iclass 7, count 2 2006.173.23:45:04.62#ibcon#first serial, iclass 7, count 2 2006.173.23:45:04.62#ibcon#enter sib2, iclass 7, count 2 2006.173.23:45:04.62#ibcon#flushed, iclass 7, count 2 2006.173.23:45:04.62#ibcon#about to write, iclass 7, count 2 2006.173.23:45:04.62#ibcon#wrote, iclass 7, count 2 2006.173.23:45:04.62#ibcon#about to read 3, iclass 7, count 2 2006.173.23:45:04.64#ibcon#read 3, iclass 7, count 2 2006.173.23:45:04.64#ibcon#about to read 4, iclass 7, count 2 2006.173.23:45:04.64#ibcon#read 4, iclass 7, count 2 2006.173.23:45:04.64#ibcon#about to read 5, iclass 7, count 2 2006.173.23:45:04.64#ibcon#read 5, iclass 7, count 2 2006.173.23:45:04.64#ibcon#about to read 6, iclass 7, count 2 2006.173.23:45:04.64#ibcon#read 6, iclass 7, count 2 2006.173.23:45:04.64#ibcon#end of sib2, iclass 7, count 2 2006.173.23:45:04.64#ibcon#*mode == 0, iclass 7, count 2 2006.173.23:45:04.64#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.173.23:45:04.64#ibcon#[25=AT08-04\r\n] 2006.173.23:45:04.64#ibcon#*before write, iclass 7, count 2 2006.173.23:45:04.64#ibcon#enter sib2, iclass 7, count 2 2006.173.23:45:04.64#ibcon#flushed, iclass 7, count 2 2006.173.23:45:04.64#ibcon#about to write, iclass 7, count 2 2006.173.23:45:04.64#ibcon#wrote, iclass 7, count 2 2006.173.23:45:04.64#ibcon#about to read 3, iclass 7, count 2 2006.173.23:45:04.67#ibcon#read 3, iclass 7, count 2 2006.173.23:45:04.67#ibcon#about to read 4, iclass 7, count 2 2006.173.23:45:04.67#ibcon#read 4, iclass 7, count 2 2006.173.23:45:04.67#ibcon#about to read 5, iclass 7, count 2 2006.173.23:45:04.67#ibcon#read 5, iclass 7, count 2 2006.173.23:45:04.67#ibcon#about to read 6, iclass 7, count 2 2006.173.23:45:04.67#ibcon#read 6, iclass 7, count 2 2006.173.23:45:04.67#ibcon#end of sib2, iclass 7, count 2 2006.173.23:45:04.67#ibcon#*after write, iclass 7, count 2 2006.173.23:45:04.67#ibcon#*before return 0, iclass 7, count 2 2006.173.23:45:04.67#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.23:45:04.67#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.173.23:45:04.67#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.173.23:45:04.67#ibcon#ireg 7 cls_cnt 0 2006.173.23:45:04.67#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.23:45:04.79#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.23:45:04.79#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.23:45:04.79#ibcon#enter wrdev, iclass 7, count 0 2006.173.23:45:04.79#ibcon#first serial, iclass 7, count 0 2006.173.23:45:04.79#ibcon#enter sib2, iclass 7, count 0 2006.173.23:45:04.79#ibcon#flushed, iclass 7, count 0 2006.173.23:45:04.79#ibcon#about to write, iclass 7, count 0 2006.173.23:45:04.79#ibcon#wrote, iclass 7, count 0 2006.173.23:45:04.79#ibcon#about to read 3, iclass 7, count 0 2006.173.23:45:04.81#ibcon#read 3, iclass 7, count 0 2006.173.23:45:04.81#ibcon#about to read 4, iclass 7, count 0 2006.173.23:45:04.81#ibcon#read 4, iclass 7, count 0 2006.173.23:45:04.81#ibcon#about to read 5, iclass 7, count 0 2006.173.23:45:04.81#ibcon#read 5, iclass 7, count 0 2006.173.23:45:04.81#ibcon#about to read 6, iclass 7, count 0 2006.173.23:45:04.81#ibcon#read 6, iclass 7, count 0 2006.173.23:45:04.81#ibcon#end of sib2, iclass 7, count 0 2006.173.23:45:04.81#ibcon#*mode == 0, iclass 7, count 0 2006.173.23:45:04.81#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.23:45:04.81#ibcon#[25=USB\r\n] 2006.173.23:45:04.81#ibcon#*before write, iclass 7, count 0 2006.173.23:45:04.81#ibcon#enter sib2, iclass 7, count 0 2006.173.23:45:04.81#ibcon#flushed, iclass 7, count 0 2006.173.23:45:04.81#ibcon#about to write, iclass 7, count 0 2006.173.23:45:04.81#ibcon#wrote, iclass 7, count 0 2006.173.23:45:04.81#ibcon#about to read 3, iclass 7, count 0 2006.173.23:45:04.84#ibcon#read 3, iclass 7, count 0 2006.173.23:45:04.84#ibcon#about to read 4, iclass 7, count 0 2006.173.23:45:04.84#ibcon#read 4, iclass 7, count 0 2006.173.23:45:04.84#ibcon#about to read 5, iclass 7, count 0 2006.173.23:45:04.84#ibcon#read 5, iclass 7, count 0 2006.173.23:45:04.84#ibcon#about to read 6, iclass 7, count 0 2006.173.23:45:04.84#ibcon#read 6, iclass 7, count 0 2006.173.23:45:04.84#ibcon#end of sib2, iclass 7, count 0 2006.173.23:45:04.84#ibcon#*after write, iclass 7, count 0 2006.173.23:45:04.84#ibcon#*before return 0, iclass 7, count 0 2006.173.23:45:04.84#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.23:45:04.84#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.173.23:45:04.84#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.23:45:04.84#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.23:45:04.84$vck44/vblo=1,629.99 2006.173.23:45:04.84#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.23:45:04.84#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.23:45:04.84#ibcon#ireg 17 cls_cnt 0 2006.173.23:45:04.84#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.23:45:04.84#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.23:45:04.84#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.23:45:04.84#ibcon#enter wrdev, iclass 11, count 0 2006.173.23:45:04.84#ibcon#first serial, iclass 11, count 0 2006.173.23:45:04.84#ibcon#enter sib2, iclass 11, count 0 2006.173.23:45:04.84#ibcon#flushed, iclass 11, count 0 2006.173.23:45:04.84#ibcon#about to write, iclass 11, count 0 2006.173.23:45:04.84#ibcon#wrote, iclass 11, count 0 2006.173.23:45:04.84#ibcon#about to read 3, iclass 11, count 0 2006.173.23:45:04.86#ibcon#read 3, iclass 11, count 0 2006.173.23:45:04.86#ibcon#about to read 4, iclass 11, count 0 2006.173.23:45:04.86#ibcon#read 4, iclass 11, count 0 2006.173.23:45:04.86#ibcon#about to read 5, iclass 11, count 0 2006.173.23:45:04.86#ibcon#read 5, iclass 11, count 0 2006.173.23:45:04.86#ibcon#about to read 6, iclass 11, count 0 2006.173.23:45:04.86#ibcon#read 6, iclass 11, count 0 2006.173.23:45:04.86#ibcon#end of sib2, iclass 11, count 0 2006.173.23:45:04.86#ibcon#*mode == 0, iclass 11, count 0 2006.173.23:45:04.86#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.23:45:04.86#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.23:45:04.86#ibcon#*before write, iclass 11, count 0 2006.173.23:45:04.86#ibcon#enter sib2, iclass 11, count 0 2006.173.23:45:04.86#ibcon#flushed, iclass 11, count 0 2006.173.23:45:04.86#ibcon#about to write, iclass 11, count 0 2006.173.23:45:04.86#ibcon#wrote, iclass 11, count 0 2006.173.23:45:04.86#ibcon#about to read 3, iclass 11, count 0 2006.173.23:45:04.90#ibcon#read 3, iclass 11, count 0 2006.173.23:45:04.90#ibcon#about to read 4, iclass 11, count 0 2006.173.23:45:04.90#ibcon#read 4, iclass 11, count 0 2006.173.23:45:04.90#ibcon#about to read 5, iclass 11, count 0 2006.173.23:45:04.90#ibcon#read 5, iclass 11, count 0 2006.173.23:45:04.90#ibcon#about to read 6, iclass 11, count 0 2006.173.23:45:04.90#ibcon#read 6, iclass 11, count 0 2006.173.23:45:04.90#ibcon#end of sib2, iclass 11, count 0 2006.173.23:45:04.90#ibcon#*after write, iclass 11, count 0 2006.173.23:45:04.90#ibcon#*before return 0, iclass 11, count 0 2006.173.23:45:04.90#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.23:45:04.90#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.23:45:04.90#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.23:45:04.90#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.23:45:04.90$vck44/vb=1,4 2006.173.23:45:04.90#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.173.23:45:04.90#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.173.23:45:04.90#ibcon#ireg 11 cls_cnt 2 2006.173.23:45:04.90#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.23:45:04.90#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.173.23:45:04.90#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.23:45:04.90#ibcon#enter wrdev, iclass 13, count 2 2006.173.23:45:04.90#ibcon#first serial, iclass 13, count 2 2006.173.23:45:04.90#ibcon#enter sib2, iclass 13, count 2 2006.173.23:45:04.90#ibcon#flushed, iclass 13, count 2 2006.173.23:45:04.90#ibcon#about to write, iclass 13, count 2 2006.173.23:45:04.90#ibcon#wrote, iclass 13, count 2 2006.173.23:45:04.90#ibcon#about to read 3, iclass 13, count 2 2006.173.23:45:04.92#ibcon#read 3, iclass 13, count 2 2006.173.23:45:04.92#ibcon#about to read 4, iclass 13, count 2 2006.173.23:45:04.92#ibcon#read 4, iclass 13, count 2 2006.173.23:45:04.92#ibcon#about to read 5, iclass 13, count 2 2006.173.23:45:04.92#ibcon#read 5, iclass 13, count 2 2006.173.23:45:04.92#ibcon#about to read 6, iclass 13, count 2 2006.173.23:45:04.92#ibcon#read 6, iclass 13, count 2 2006.173.23:45:04.92#ibcon#end of sib2, iclass 13, count 2 2006.173.23:45:04.92#ibcon#*mode == 0, iclass 13, count 2 2006.173.23:45:04.92#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.173.23:45:04.92#ibcon#[27=AT01-04\r\n] 2006.173.23:45:04.92#ibcon#*before write, iclass 13, count 2 2006.173.23:45:04.92#ibcon#enter sib2, iclass 13, count 2 2006.173.23:45:04.92#ibcon#flushed, iclass 13, count 2 2006.173.23:45:04.92#ibcon#about to write, iclass 13, count 2 2006.173.23:45:04.92#ibcon#wrote, iclass 13, count 2 2006.173.23:45:04.92#ibcon#about to read 3, iclass 13, count 2 2006.173.23:45:04.95#ibcon#read 3, iclass 13, count 2 2006.173.23:45:04.95#ibcon#about to read 4, iclass 13, count 2 2006.173.23:45:04.95#ibcon#read 4, iclass 13, count 2 2006.173.23:45:04.95#ibcon#about to read 5, iclass 13, count 2 2006.173.23:45:04.95#ibcon#read 5, iclass 13, count 2 2006.173.23:45:04.95#ibcon#about to read 6, iclass 13, count 2 2006.173.23:45:04.95#ibcon#read 6, iclass 13, count 2 2006.173.23:45:04.95#ibcon#end of sib2, iclass 13, count 2 2006.173.23:45:04.95#ibcon#*after write, iclass 13, count 2 2006.173.23:45:04.95#ibcon#*before return 0, iclass 13, count 2 2006.173.23:45:04.95#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.173.23:45:04.95#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.173.23:45:04.95#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.173.23:45:04.95#ibcon#ireg 7 cls_cnt 0 2006.173.23:45:04.95#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.23:45:05.07#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.173.23:45:05.07#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.23:45:05.07#ibcon#enter wrdev, iclass 13, count 0 2006.173.23:45:05.07#ibcon#first serial, iclass 13, count 0 2006.173.23:45:05.07#ibcon#enter sib2, iclass 13, count 0 2006.173.23:45:05.07#ibcon#flushed, iclass 13, count 0 2006.173.23:45:05.07#ibcon#about to write, iclass 13, count 0 2006.173.23:45:05.07#ibcon#wrote, iclass 13, count 0 2006.173.23:45:05.07#ibcon#about to read 3, iclass 13, count 0 2006.173.23:45:05.09#ibcon#read 3, iclass 13, count 0 2006.173.23:45:05.09#ibcon#about to read 4, iclass 13, count 0 2006.173.23:45:05.09#ibcon#read 4, iclass 13, count 0 2006.173.23:45:05.09#ibcon#about to read 5, iclass 13, count 0 2006.173.23:45:05.09#ibcon#read 5, iclass 13, count 0 2006.173.23:45:05.09#ibcon#about to read 6, iclass 13, count 0 2006.173.23:45:05.09#ibcon#read 6, iclass 13, count 0 2006.173.23:45:05.09#ibcon#end of sib2, iclass 13, count 0 2006.173.23:45:05.09#ibcon#*mode == 0, iclass 13, count 0 2006.173.23:45:05.09#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.23:45:05.09#ibcon#[27=USB\r\n] 2006.173.23:45:05.09#ibcon#*before write, iclass 13, count 0 2006.173.23:45:05.09#ibcon#enter sib2, iclass 13, count 0 2006.173.23:45:05.09#ibcon#flushed, iclass 13, count 0 2006.173.23:45:05.09#ibcon#about to write, iclass 13, count 0 2006.173.23:45:05.09#ibcon#wrote, iclass 13, count 0 2006.173.23:45:05.09#ibcon#about to read 3, iclass 13, count 0 2006.173.23:45:05.12#ibcon#read 3, iclass 13, count 0 2006.173.23:45:05.12#ibcon#about to read 4, iclass 13, count 0 2006.173.23:45:05.12#ibcon#read 4, iclass 13, count 0 2006.173.23:45:05.12#ibcon#about to read 5, iclass 13, count 0 2006.173.23:45:05.12#ibcon#read 5, iclass 13, count 0 2006.173.23:45:05.12#ibcon#about to read 6, iclass 13, count 0 2006.173.23:45:05.12#ibcon#read 6, iclass 13, count 0 2006.173.23:45:05.12#ibcon#end of sib2, iclass 13, count 0 2006.173.23:45:05.12#ibcon#*after write, iclass 13, count 0 2006.173.23:45:05.12#ibcon#*before return 0, iclass 13, count 0 2006.173.23:45:05.12#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.173.23:45:05.12#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.173.23:45:05.12#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.23:45:05.12#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.23:45:05.12$vck44/vblo=2,634.99 2006.173.23:45:05.12#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.23:45:05.12#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.23:45:05.12#ibcon#ireg 17 cls_cnt 0 2006.173.23:45:05.12#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.23:45:05.12#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.23:45:05.12#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.23:45:05.12#ibcon#enter wrdev, iclass 15, count 0 2006.173.23:45:05.12#ibcon#first serial, iclass 15, count 0 2006.173.23:45:05.12#ibcon#enter sib2, iclass 15, count 0 2006.173.23:45:05.12#ibcon#flushed, iclass 15, count 0 2006.173.23:45:05.12#ibcon#about to write, iclass 15, count 0 2006.173.23:45:05.12#ibcon#wrote, iclass 15, count 0 2006.173.23:45:05.12#ibcon#about to read 3, iclass 15, count 0 2006.173.23:45:05.14#ibcon#read 3, iclass 15, count 0 2006.173.23:45:05.14#ibcon#about to read 4, iclass 15, count 0 2006.173.23:45:05.14#ibcon#read 4, iclass 15, count 0 2006.173.23:45:05.14#ibcon#about to read 5, iclass 15, count 0 2006.173.23:45:05.14#ibcon#read 5, iclass 15, count 0 2006.173.23:45:05.14#ibcon#about to read 6, iclass 15, count 0 2006.173.23:45:05.14#ibcon#read 6, iclass 15, count 0 2006.173.23:45:05.14#ibcon#end of sib2, iclass 15, count 0 2006.173.23:45:05.14#ibcon#*mode == 0, iclass 15, count 0 2006.173.23:45:05.14#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.23:45:05.14#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.23:45:05.14#ibcon#*before write, iclass 15, count 0 2006.173.23:45:05.14#ibcon#enter sib2, iclass 15, count 0 2006.173.23:45:05.14#ibcon#flushed, iclass 15, count 0 2006.173.23:45:05.14#ibcon#about to write, iclass 15, count 0 2006.173.23:45:05.14#ibcon#wrote, iclass 15, count 0 2006.173.23:45:05.14#ibcon#about to read 3, iclass 15, count 0 2006.173.23:45:05.18#ibcon#read 3, iclass 15, count 0 2006.173.23:45:05.18#ibcon#about to read 4, iclass 15, count 0 2006.173.23:45:05.18#ibcon#read 4, iclass 15, count 0 2006.173.23:45:05.18#ibcon#about to read 5, iclass 15, count 0 2006.173.23:45:05.18#ibcon#read 5, iclass 15, count 0 2006.173.23:45:05.18#ibcon#about to read 6, iclass 15, count 0 2006.173.23:45:05.18#ibcon#read 6, iclass 15, count 0 2006.173.23:45:05.18#ibcon#end of sib2, iclass 15, count 0 2006.173.23:45:05.18#ibcon#*after write, iclass 15, count 0 2006.173.23:45:05.18#ibcon#*before return 0, iclass 15, count 0 2006.173.23:45:05.18#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.23:45:05.18#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.23:45:05.18#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.23:45:05.18#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.23:45:05.18$vck44/vb=2,4 2006.173.23:45:05.18#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.173.23:45:05.18#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.173.23:45:05.18#ibcon#ireg 11 cls_cnt 2 2006.173.23:45:05.18#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.23:45:05.24#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.173.23:45:05.24#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.23:45:05.24#ibcon#enter wrdev, iclass 17, count 2 2006.173.23:45:05.24#ibcon#first serial, iclass 17, count 2 2006.173.23:45:05.24#ibcon#enter sib2, iclass 17, count 2 2006.173.23:45:05.24#ibcon#flushed, iclass 17, count 2 2006.173.23:45:05.24#ibcon#about to write, iclass 17, count 2 2006.173.23:45:05.24#ibcon#wrote, iclass 17, count 2 2006.173.23:45:05.24#ibcon#about to read 3, iclass 17, count 2 2006.173.23:45:05.26#ibcon#read 3, iclass 17, count 2 2006.173.23:45:05.26#ibcon#about to read 4, iclass 17, count 2 2006.173.23:45:05.26#ibcon#read 4, iclass 17, count 2 2006.173.23:45:05.26#ibcon#about to read 5, iclass 17, count 2 2006.173.23:45:05.26#ibcon#read 5, iclass 17, count 2 2006.173.23:45:05.26#ibcon#about to read 6, iclass 17, count 2 2006.173.23:45:05.26#ibcon#read 6, iclass 17, count 2 2006.173.23:45:05.26#ibcon#end of sib2, iclass 17, count 2 2006.173.23:45:05.26#ibcon#*mode == 0, iclass 17, count 2 2006.173.23:45:05.26#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.173.23:45:05.26#ibcon#[27=AT02-04\r\n] 2006.173.23:45:05.26#ibcon#*before write, iclass 17, count 2 2006.173.23:45:05.26#ibcon#enter sib2, iclass 17, count 2 2006.173.23:45:05.26#ibcon#flushed, iclass 17, count 2 2006.173.23:45:05.26#ibcon#about to write, iclass 17, count 2 2006.173.23:45:05.26#ibcon#wrote, iclass 17, count 2 2006.173.23:45:05.26#ibcon#about to read 3, iclass 17, count 2 2006.173.23:45:05.29#ibcon#read 3, iclass 17, count 2 2006.173.23:45:05.29#ibcon#about to read 4, iclass 17, count 2 2006.173.23:45:05.29#ibcon#read 4, iclass 17, count 2 2006.173.23:45:05.29#ibcon#about to read 5, iclass 17, count 2 2006.173.23:45:05.29#ibcon#read 5, iclass 17, count 2 2006.173.23:45:05.29#ibcon#about to read 6, iclass 17, count 2 2006.173.23:45:05.29#ibcon#read 6, iclass 17, count 2 2006.173.23:45:05.29#ibcon#end of sib2, iclass 17, count 2 2006.173.23:45:05.29#ibcon#*after write, iclass 17, count 2 2006.173.23:45:05.29#ibcon#*before return 0, iclass 17, count 2 2006.173.23:45:05.29#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.173.23:45:05.29#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.173.23:45:05.29#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.173.23:45:05.29#ibcon#ireg 7 cls_cnt 0 2006.173.23:45:05.29#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.23:45:05.41#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.173.23:45:05.41#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.23:45:05.41#ibcon#enter wrdev, iclass 17, count 0 2006.173.23:45:05.41#ibcon#first serial, iclass 17, count 0 2006.173.23:45:05.41#ibcon#enter sib2, iclass 17, count 0 2006.173.23:45:05.41#ibcon#flushed, iclass 17, count 0 2006.173.23:45:05.41#ibcon#about to write, iclass 17, count 0 2006.173.23:45:05.41#ibcon#wrote, iclass 17, count 0 2006.173.23:45:05.41#ibcon#about to read 3, iclass 17, count 0 2006.173.23:45:05.43#ibcon#read 3, iclass 17, count 0 2006.173.23:45:05.43#ibcon#about to read 4, iclass 17, count 0 2006.173.23:45:05.43#ibcon#read 4, iclass 17, count 0 2006.173.23:45:05.43#ibcon#about to read 5, iclass 17, count 0 2006.173.23:45:05.43#ibcon#read 5, iclass 17, count 0 2006.173.23:45:05.43#ibcon#about to read 6, iclass 17, count 0 2006.173.23:45:05.43#ibcon#read 6, iclass 17, count 0 2006.173.23:45:05.43#ibcon#end of sib2, iclass 17, count 0 2006.173.23:45:05.43#ibcon#*mode == 0, iclass 17, count 0 2006.173.23:45:05.43#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.23:45:05.43#ibcon#[27=USB\r\n] 2006.173.23:45:05.43#ibcon#*before write, iclass 17, count 0 2006.173.23:45:05.43#ibcon#enter sib2, iclass 17, count 0 2006.173.23:45:05.43#ibcon#flushed, iclass 17, count 0 2006.173.23:45:05.43#ibcon#about to write, iclass 17, count 0 2006.173.23:45:05.43#ibcon#wrote, iclass 17, count 0 2006.173.23:45:05.43#ibcon#about to read 3, iclass 17, count 0 2006.173.23:45:05.46#ibcon#read 3, iclass 17, count 0 2006.173.23:45:05.46#ibcon#about to read 4, iclass 17, count 0 2006.173.23:45:05.46#ibcon#read 4, iclass 17, count 0 2006.173.23:45:05.46#ibcon#about to read 5, iclass 17, count 0 2006.173.23:45:05.46#ibcon#read 5, iclass 17, count 0 2006.173.23:45:05.46#ibcon#about to read 6, iclass 17, count 0 2006.173.23:45:05.46#ibcon#read 6, iclass 17, count 0 2006.173.23:45:05.46#ibcon#end of sib2, iclass 17, count 0 2006.173.23:45:05.46#ibcon#*after write, iclass 17, count 0 2006.173.23:45:05.46#ibcon#*before return 0, iclass 17, count 0 2006.173.23:45:05.46#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.173.23:45:05.46#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.173.23:45:05.46#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.23:45:05.46#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.23:45:05.46$vck44/vblo=3,649.99 2006.173.23:45:05.46#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.173.23:45:05.46#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.173.23:45:05.46#ibcon#ireg 17 cls_cnt 0 2006.173.23:45:05.46#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.23:45:05.46#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.173.23:45:05.46#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.23:45:05.46#ibcon#enter wrdev, iclass 19, count 0 2006.173.23:45:05.46#ibcon#first serial, iclass 19, count 0 2006.173.23:45:05.46#ibcon#enter sib2, iclass 19, count 0 2006.173.23:45:05.46#ibcon#flushed, iclass 19, count 0 2006.173.23:45:05.46#ibcon#about to write, iclass 19, count 0 2006.173.23:45:05.46#ibcon#wrote, iclass 19, count 0 2006.173.23:45:05.46#ibcon#about to read 3, iclass 19, count 0 2006.173.23:45:05.48#ibcon#read 3, iclass 19, count 0 2006.173.23:45:05.48#ibcon#about to read 4, iclass 19, count 0 2006.173.23:45:05.48#ibcon#read 4, iclass 19, count 0 2006.173.23:45:05.48#ibcon#about to read 5, iclass 19, count 0 2006.173.23:45:05.48#ibcon#read 5, iclass 19, count 0 2006.173.23:45:05.48#ibcon#about to read 6, iclass 19, count 0 2006.173.23:45:05.48#ibcon#read 6, iclass 19, count 0 2006.173.23:45:05.48#ibcon#end of sib2, iclass 19, count 0 2006.173.23:45:05.48#ibcon#*mode == 0, iclass 19, count 0 2006.173.23:45:05.48#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.23:45:05.48#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.23:45:05.48#ibcon#*before write, iclass 19, count 0 2006.173.23:45:05.48#ibcon#enter sib2, iclass 19, count 0 2006.173.23:45:05.48#ibcon#flushed, iclass 19, count 0 2006.173.23:45:05.48#ibcon#about to write, iclass 19, count 0 2006.173.23:45:05.48#ibcon#wrote, iclass 19, count 0 2006.173.23:45:05.48#ibcon#about to read 3, iclass 19, count 0 2006.173.23:45:05.52#ibcon#read 3, iclass 19, count 0 2006.173.23:45:05.52#ibcon#about to read 4, iclass 19, count 0 2006.173.23:45:05.52#ibcon#read 4, iclass 19, count 0 2006.173.23:45:05.52#ibcon#about to read 5, iclass 19, count 0 2006.173.23:45:05.52#ibcon#read 5, iclass 19, count 0 2006.173.23:45:05.52#ibcon#about to read 6, iclass 19, count 0 2006.173.23:45:05.52#ibcon#read 6, iclass 19, count 0 2006.173.23:45:05.52#ibcon#end of sib2, iclass 19, count 0 2006.173.23:45:05.52#ibcon#*after write, iclass 19, count 0 2006.173.23:45:05.52#ibcon#*before return 0, iclass 19, count 0 2006.173.23:45:05.52#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.173.23:45:05.52#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.173.23:45:05.52#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.23:45:05.52#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.23:45:05.52$vck44/vb=3,4 2006.173.23:45:05.52#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.173.23:45:05.52#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.173.23:45:05.52#ibcon#ireg 11 cls_cnt 2 2006.173.23:45:05.52#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.23:45:05.58#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.173.23:45:05.58#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.23:45:05.58#ibcon#enter wrdev, iclass 21, count 2 2006.173.23:45:05.58#ibcon#first serial, iclass 21, count 2 2006.173.23:45:05.58#ibcon#enter sib2, iclass 21, count 2 2006.173.23:45:05.58#ibcon#flushed, iclass 21, count 2 2006.173.23:45:05.58#ibcon#about to write, iclass 21, count 2 2006.173.23:45:05.58#ibcon#wrote, iclass 21, count 2 2006.173.23:45:05.58#ibcon#about to read 3, iclass 21, count 2 2006.173.23:45:05.60#ibcon#read 3, iclass 21, count 2 2006.173.23:45:05.60#ibcon#about to read 4, iclass 21, count 2 2006.173.23:45:05.60#ibcon#read 4, iclass 21, count 2 2006.173.23:45:05.60#ibcon#about to read 5, iclass 21, count 2 2006.173.23:45:05.60#ibcon#read 5, iclass 21, count 2 2006.173.23:45:05.60#ibcon#about to read 6, iclass 21, count 2 2006.173.23:45:05.60#ibcon#read 6, iclass 21, count 2 2006.173.23:45:05.60#ibcon#end of sib2, iclass 21, count 2 2006.173.23:45:05.60#ibcon#*mode == 0, iclass 21, count 2 2006.173.23:45:05.60#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.173.23:45:05.60#ibcon#[27=AT03-04\r\n] 2006.173.23:45:05.60#ibcon#*before write, iclass 21, count 2 2006.173.23:45:05.60#ibcon#enter sib2, iclass 21, count 2 2006.173.23:45:05.60#ibcon#flushed, iclass 21, count 2 2006.173.23:45:05.60#ibcon#about to write, iclass 21, count 2 2006.173.23:45:05.60#ibcon#wrote, iclass 21, count 2 2006.173.23:45:05.60#ibcon#about to read 3, iclass 21, count 2 2006.173.23:45:05.63#ibcon#read 3, iclass 21, count 2 2006.173.23:45:05.63#ibcon#about to read 4, iclass 21, count 2 2006.173.23:45:05.63#ibcon#read 4, iclass 21, count 2 2006.173.23:45:05.63#ibcon#about to read 5, iclass 21, count 2 2006.173.23:45:05.63#ibcon#read 5, iclass 21, count 2 2006.173.23:45:05.63#ibcon#about to read 6, iclass 21, count 2 2006.173.23:45:05.63#ibcon#read 6, iclass 21, count 2 2006.173.23:45:05.63#ibcon#end of sib2, iclass 21, count 2 2006.173.23:45:05.63#ibcon#*after write, iclass 21, count 2 2006.173.23:45:05.63#ibcon#*before return 0, iclass 21, count 2 2006.173.23:45:05.63#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.173.23:45:05.63#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.173.23:45:05.63#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.173.23:45:05.63#ibcon#ireg 7 cls_cnt 0 2006.173.23:45:05.63#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.23:45:05.75#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.173.23:45:05.75#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.23:45:05.75#ibcon#enter wrdev, iclass 21, count 0 2006.173.23:45:05.75#ibcon#first serial, iclass 21, count 0 2006.173.23:45:05.75#ibcon#enter sib2, iclass 21, count 0 2006.173.23:45:05.75#ibcon#flushed, iclass 21, count 0 2006.173.23:45:05.75#ibcon#about to write, iclass 21, count 0 2006.173.23:45:05.75#ibcon#wrote, iclass 21, count 0 2006.173.23:45:05.75#ibcon#about to read 3, iclass 21, count 0 2006.173.23:45:05.77#ibcon#read 3, iclass 21, count 0 2006.173.23:45:05.77#ibcon#about to read 4, iclass 21, count 0 2006.173.23:45:05.77#ibcon#read 4, iclass 21, count 0 2006.173.23:45:05.77#ibcon#about to read 5, iclass 21, count 0 2006.173.23:45:05.77#ibcon#read 5, iclass 21, count 0 2006.173.23:45:05.77#ibcon#about to read 6, iclass 21, count 0 2006.173.23:45:05.77#ibcon#read 6, iclass 21, count 0 2006.173.23:45:05.77#ibcon#end of sib2, iclass 21, count 0 2006.173.23:45:05.77#ibcon#*mode == 0, iclass 21, count 0 2006.173.23:45:05.77#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.23:45:05.77#ibcon#[27=USB\r\n] 2006.173.23:45:05.77#ibcon#*before write, iclass 21, count 0 2006.173.23:45:05.77#ibcon#enter sib2, iclass 21, count 0 2006.173.23:45:05.77#ibcon#flushed, iclass 21, count 0 2006.173.23:45:05.77#ibcon#about to write, iclass 21, count 0 2006.173.23:45:05.77#ibcon#wrote, iclass 21, count 0 2006.173.23:45:05.77#ibcon#about to read 3, iclass 21, count 0 2006.173.23:45:05.80#ibcon#read 3, iclass 21, count 0 2006.173.23:45:05.80#ibcon#about to read 4, iclass 21, count 0 2006.173.23:45:05.80#ibcon#read 4, iclass 21, count 0 2006.173.23:45:05.80#ibcon#about to read 5, iclass 21, count 0 2006.173.23:45:05.80#ibcon#read 5, iclass 21, count 0 2006.173.23:45:05.80#ibcon#about to read 6, iclass 21, count 0 2006.173.23:45:05.80#ibcon#read 6, iclass 21, count 0 2006.173.23:45:05.80#ibcon#end of sib2, iclass 21, count 0 2006.173.23:45:05.80#ibcon#*after write, iclass 21, count 0 2006.173.23:45:05.80#ibcon#*before return 0, iclass 21, count 0 2006.173.23:45:05.80#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.173.23:45:05.80#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.173.23:45:05.80#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.23:45:05.80#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.23:45:05.80$vck44/vblo=4,679.99 2006.173.23:45:05.80#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.173.23:45:05.80#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.173.23:45:05.80#ibcon#ireg 17 cls_cnt 0 2006.173.23:45:05.80#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.23:45:05.80#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.173.23:45:05.80#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.23:45:05.80#ibcon#enter wrdev, iclass 23, count 0 2006.173.23:45:05.80#ibcon#first serial, iclass 23, count 0 2006.173.23:45:05.80#ibcon#enter sib2, iclass 23, count 0 2006.173.23:45:05.80#ibcon#flushed, iclass 23, count 0 2006.173.23:45:05.80#ibcon#about to write, iclass 23, count 0 2006.173.23:45:05.80#ibcon#wrote, iclass 23, count 0 2006.173.23:45:05.80#ibcon#about to read 3, iclass 23, count 0 2006.173.23:45:05.82#ibcon#read 3, iclass 23, count 0 2006.173.23:45:05.82#ibcon#about to read 4, iclass 23, count 0 2006.173.23:45:05.82#ibcon#read 4, iclass 23, count 0 2006.173.23:45:05.82#ibcon#about to read 5, iclass 23, count 0 2006.173.23:45:05.82#ibcon#read 5, iclass 23, count 0 2006.173.23:45:05.82#ibcon#about to read 6, iclass 23, count 0 2006.173.23:45:05.82#ibcon#read 6, iclass 23, count 0 2006.173.23:45:05.82#ibcon#end of sib2, iclass 23, count 0 2006.173.23:45:05.82#ibcon#*mode == 0, iclass 23, count 0 2006.173.23:45:05.82#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.23:45:05.82#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.23:45:05.82#ibcon#*before write, iclass 23, count 0 2006.173.23:45:05.82#ibcon#enter sib2, iclass 23, count 0 2006.173.23:45:05.82#ibcon#flushed, iclass 23, count 0 2006.173.23:45:05.82#ibcon#about to write, iclass 23, count 0 2006.173.23:45:05.82#ibcon#wrote, iclass 23, count 0 2006.173.23:45:05.82#ibcon#about to read 3, iclass 23, count 0 2006.173.23:45:05.86#ibcon#read 3, iclass 23, count 0 2006.173.23:45:05.86#ibcon#about to read 4, iclass 23, count 0 2006.173.23:45:05.86#ibcon#read 4, iclass 23, count 0 2006.173.23:45:05.86#ibcon#about to read 5, iclass 23, count 0 2006.173.23:45:05.86#ibcon#read 5, iclass 23, count 0 2006.173.23:45:05.86#ibcon#about to read 6, iclass 23, count 0 2006.173.23:45:05.86#ibcon#read 6, iclass 23, count 0 2006.173.23:45:05.86#ibcon#end of sib2, iclass 23, count 0 2006.173.23:45:05.86#ibcon#*after write, iclass 23, count 0 2006.173.23:45:05.86#ibcon#*before return 0, iclass 23, count 0 2006.173.23:45:05.86#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.173.23:45:05.86#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.173.23:45:05.86#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.23:45:05.86#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.23:45:05.86$vck44/vb=4,4 2006.173.23:45:05.86#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.173.23:45:05.86#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.173.23:45:05.86#ibcon#ireg 11 cls_cnt 2 2006.173.23:45:05.86#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.23:45:05.92#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.173.23:45:05.92#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.23:45:05.92#ibcon#enter wrdev, iclass 25, count 2 2006.173.23:45:05.92#ibcon#first serial, iclass 25, count 2 2006.173.23:45:05.92#ibcon#enter sib2, iclass 25, count 2 2006.173.23:45:05.92#ibcon#flushed, iclass 25, count 2 2006.173.23:45:05.92#ibcon#about to write, iclass 25, count 2 2006.173.23:45:05.92#ibcon#wrote, iclass 25, count 2 2006.173.23:45:05.92#ibcon#about to read 3, iclass 25, count 2 2006.173.23:45:05.94#ibcon#read 3, iclass 25, count 2 2006.173.23:45:05.94#ibcon#about to read 4, iclass 25, count 2 2006.173.23:45:05.94#ibcon#read 4, iclass 25, count 2 2006.173.23:45:05.94#ibcon#about to read 5, iclass 25, count 2 2006.173.23:45:05.94#ibcon#read 5, iclass 25, count 2 2006.173.23:45:05.94#ibcon#about to read 6, iclass 25, count 2 2006.173.23:45:05.94#ibcon#read 6, iclass 25, count 2 2006.173.23:45:05.94#ibcon#end of sib2, iclass 25, count 2 2006.173.23:45:05.94#ibcon#*mode == 0, iclass 25, count 2 2006.173.23:45:05.94#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.173.23:45:05.94#ibcon#[27=AT04-04\r\n] 2006.173.23:45:05.94#ibcon#*before write, iclass 25, count 2 2006.173.23:45:05.94#ibcon#enter sib2, iclass 25, count 2 2006.173.23:45:05.94#ibcon#flushed, iclass 25, count 2 2006.173.23:45:05.94#ibcon#about to write, iclass 25, count 2 2006.173.23:45:05.94#ibcon#wrote, iclass 25, count 2 2006.173.23:45:05.94#ibcon#about to read 3, iclass 25, count 2 2006.173.23:45:05.97#ibcon#read 3, iclass 25, count 2 2006.173.23:45:05.97#ibcon#about to read 4, iclass 25, count 2 2006.173.23:45:05.97#ibcon#read 4, iclass 25, count 2 2006.173.23:45:05.97#ibcon#about to read 5, iclass 25, count 2 2006.173.23:45:05.97#ibcon#read 5, iclass 25, count 2 2006.173.23:45:05.97#ibcon#about to read 6, iclass 25, count 2 2006.173.23:45:05.97#ibcon#read 6, iclass 25, count 2 2006.173.23:45:05.97#ibcon#end of sib2, iclass 25, count 2 2006.173.23:45:05.97#ibcon#*after write, iclass 25, count 2 2006.173.23:45:05.97#ibcon#*before return 0, iclass 25, count 2 2006.173.23:45:05.97#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.173.23:45:05.97#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.173.23:45:05.97#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.173.23:45:05.97#ibcon#ireg 7 cls_cnt 0 2006.173.23:45:05.97#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.23:45:06.09#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.173.23:45:06.09#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.23:45:06.09#ibcon#enter wrdev, iclass 25, count 0 2006.173.23:45:06.09#ibcon#first serial, iclass 25, count 0 2006.173.23:45:06.09#ibcon#enter sib2, iclass 25, count 0 2006.173.23:45:06.09#ibcon#flushed, iclass 25, count 0 2006.173.23:45:06.09#ibcon#about to write, iclass 25, count 0 2006.173.23:45:06.09#ibcon#wrote, iclass 25, count 0 2006.173.23:45:06.09#ibcon#about to read 3, iclass 25, count 0 2006.173.23:45:06.11#ibcon#read 3, iclass 25, count 0 2006.173.23:45:06.11#ibcon#about to read 4, iclass 25, count 0 2006.173.23:45:06.11#ibcon#read 4, iclass 25, count 0 2006.173.23:45:06.11#ibcon#about to read 5, iclass 25, count 0 2006.173.23:45:06.11#ibcon#read 5, iclass 25, count 0 2006.173.23:45:06.11#ibcon#about to read 6, iclass 25, count 0 2006.173.23:45:06.11#ibcon#read 6, iclass 25, count 0 2006.173.23:45:06.11#ibcon#end of sib2, iclass 25, count 0 2006.173.23:45:06.11#ibcon#*mode == 0, iclass 25, count 0 2006.173.23:45:06.11#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.23:45:06.11#ibcon#[27=USB\r\n] 2006.173.23:45:06.11#ibcon#*before write, iclass 25, count 0 2006.173.23:45:06.11#ibcon#enter sib2, iclass 25, count 0 2006.173.23:45:06.11#ibcon#flushed, iclass 25, count 0 2006.173.23:45:06.11#ibcon#about to write, iclass 25, count 0 2006.173.23:45:06.11#ibcon#wrote, iclass 25, count 0 2006.173.23:45:06.11#ibcon#about to read 3, iclass 25, count 0 2006.173.23:45:06.14#ibcon#read 3, iclass 25, count 0 2006.173.23:45:06.14#ibcon#about to read 4, iclass 25, count 0 2006.173.23:45:06.14#ibcon#read 4, iclass 25, count 0 2006.173.23:45:06.14#ibcon#about to read 5, iclass 25, count 0 2006.173.23:45:06.14#ibcon#read 5, iclass 25, count 0 2006.173.23:45:06.14#ibcon#about to read 6, iclass 25, count 0 2006.173.23:45:06.14#ibcon#read 6, iclass 25, count 0 2006.173.23:45:06.14#ibcon#end of sib2, iclass 25, count 0 2006.173.23:45:06.14#ibcon#*after write, iclass 25, count 0 2006.173.23:45:06.14#ibcon#*before return 0, iclass 25, count 0 2006.173.23:45:06.14#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.173.23:45:06.14#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.173.23:45:06.14#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.23:45:06.14#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.23:45:06.14$vck44/vblo=5,709.99 2006.173.23:45:06.14#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.173.23:45:06.14#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.173.23:45:06.14#ibcon#ireg 17 cls_cnt 0 2006.173.23:45:06.14#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.23:45:06.14#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.173.23:45:06.14#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.23:45:06.14#ibcon#enter wrdev, iclass 27, count 0 2006.173.23:45:06.14#ibcon#first serial, iclass 27, count 0 2006.173.23:45:06.14#ibcon#enter sib2, iclass 27, count 0 2006.173.23:45:06.14#ibcon#flushed, iclass 27, count 0 2006.173.23:45:06.14#ibcon#about to write, iclass 27, count 0 2006.173.23:45:06.14#ibcon#wrote, iclass 27, count 0 2006.173.23:45:06.14#ibcon#about to read 3, iclass 27, count 0 2006.173.23:45:06.16#ibcon#read 3, iclass 27, count 0 2006.173.23:45:06.16#ibcon#about to read 4, iclass 27, count 0 2006.173.23:45:06.16#ibcon#read 4, iclass 27, count 0 2006.173.23:45:06.16#ibcon#about to read 5, iclass 27, count 0 2006.173.23:45:06.16#ibcon#read 5, iclass 27, count 0 2006.173.23:45:06.16#ibcon#about to read 6, iclass 27, count 0 2006.173.23:45:06.16#ibcon#read 6, iclass 27, count 0 2006.173.23:45:06.16#ibcon#end of sib2, iclass 27, count 0 2006.173.23:45:06.16#ibcon#*mode == 0, iclass 27, count 0 2006.173.23:45:06.16#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.23:45:06.16#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.23:45:06.16#ibcon#*before write, iclass 27, count 0 2006.173.23:45:06.16#ibcon#enter sib2, iclass 27, count 0 2006.173.23:45:06.16#ibcon#flushed, iclass 27, count 0 2006.173.23:45:06.16#ibcon#about to write, iclass 27, count 0 2006.173.23:45:06.16#ibcon#wrote, iclass 27, count 0 2006.173.23:45:06.16#ibcon#about to read 3, iclass 27, count 0 2006.173.23:45:06.20#ibcon#read 3, iclass 27, count 0 2006.173.23:45:06.20#ibcon#about to read 4, iclass 27, count 0 2006.173.23:45:06.20#ibcon#read 4, iclass 27, count 0 2006.173.23:45:06.20#ibcon#about to read 5, iclass 27, count 0 2006.173.23:45:06.20#ibcon#read 5, iclass 27, count 0 2006.173.23:45:06.20#ibcon#about to read 6, iclass 27, count 0 2006.173.23:45:06.20#ibcon#read 6, iclass 27, count 0 2006.173.23:45:06.20#ibcon#end of sib2, iclass 27, count 0 2006.173.23:45:06.20#ibcon#*after write, iclass 27, count 0 2006.173.23:45:06.20#ibcon#*before return 0, iclass 27, count 0 2006.173.23:45:06.20#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.173.23:45:06.20#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.173.23:45:06.20#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.23:45:06.20#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.23:45:06.20$vck44/vb=5,4 2006.173.23:45:06.20#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.173.23:45:06.20#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.173.23:45:06.20#ibcon#ireg 11 cls_cnt 2 2006.173.23:45:06.20#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.23:45:06.26#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.173.23:45:06.26#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.23:45:06.26#ibcon#enter wrdev, iclass 29, count 2 2006.173.23:45:06.26#ibcon#first serial, iclass 29, count 2 2006.173.23:45:06.26#ibcon#enter sib2, iclass 29, count 2 2006.173.23:45:06.26#ibcon#flushed, iclass 29, count 2 2006.173.23:45:06.26#ibcon#about to write, iclass 29, count 2 2006.173.23:45:06.26#ibcon#wrote, iclass 29, count 2 2006.173.23:45:06.26#ibcon#about to read 3, iclass 29, count 2 2006.173.23:45:06.28#ibcon#read 3, iclass 29, count 2 2006.173.23:45:06.28#ibcon#about to read 4, iclass 29, count 2 2006.173.23:45:06.28#ibcon#read 4, iclass 29, count 2 2006.173.23:45:06.28#ibcon#about to read 5, iclass 29, count 2 2006.173.23:45:06.28#ibcon#read 5, iclass 29, count 2 2006.173.23:45:06.28#ibcon#about to read 6, iclass 29, count 2 2006.173.23:45:06.28#ibcon#read 6, iclass 29, count 2 2006.173.23:45:06.28#ibcon#end of sib2, iclass 29, count 2 2006.173.23:45:06.28#ibcon#*mode == 0, iclass 29, count 2 2006.173.23:45:06.28#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.173.23:45:06.28#ibcon#[27=AT05-04\r\n] 2006.173.23:45:06.28#ibcon#*before write, iclass 29, count 2 2006.173.23:45:06.28#ibcon#enter sib2, iclass 29, count 2 2006.173.23:45:06.28#ibcon#flushed, iclass 29, count 2 2006.173.23:45:06.28#ibcon#about to write, iclass 29, count 2 2006.173.23:45:06.28#ibcon#wrote, iclass 29, count 2 2006.173.23:45:06.28#ibcon#about to read 3, iclass 29, count 2 2006.173.23:45:06.31#ibcon#read 3, iclass 29, count 2 2006.173.23:45:06.31#ibcon#about to read 4, iclass 29, count 2 2006.173.23:45:06.31#ibcon#read 4, iclass 29, count 2 2006.173.23:45:06.31#ibcon#about to read 5, iclass 29, count 2 2006.173.23:45:06.31#ibcon#read 5, iclass 29, count 2 2006.173.23:45:06.31#ibcon#about to read 6, iclass 29, count 2 2006.173.23:45:06.31#ibcon#read 6, iclass 29, count 2 2006.173.23:45:06.31#ibcon#end of sib2, iclass 29, count 2 2006.173.23:45:06.31#ibcon#*after write, iclass 29, count 2 2006.173.23:45:06.31#ibcon#*before return 0, iclass 29, count 2 2006.173.23:45:06.31#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.173.23:45:06.31#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.173.23:45:06.31#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.173.23:45:06.31#ibcon#ireg 7 cls_cnt 0 2006.173.23:45:06.31#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.23:45:06.43#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.173.23:45:06.43#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.23:45:06.43#ibcon#enter wrdev, iclass 29, count 0 2006.173.23:45:06.43#ibcon#first serial, iclass 29, count 0 2006.173.23:45:06.43#ibcon#enter sib2, iclass 29, count 0 2006.173.23:45:06.43#ibcon#flushed, iclass 29, count 0 2006.173.23:45:06.43#ibcon#about to write, iclass 29, count 0 2006.173.23:45:06.43#ibcon#wrote, iclass 29, count 0 2006.173.23:45:06.43#ibcon#about to read 3, iclass 29, count 0 2006.173.23:45:06.45#ibcon#read 3, iclass 29, count 0 2006.173.23:45:06.45#ibcon#about to read 4, iclass 29, count 0 2006.173.23:45:06.45#ibcon#read 4, iclass 29, count 0 2006.173.23:45:06.45#ibcon#about to read 5, iclass 29, count 0 2006.173.23:45:06.45#ibcon#read 5, iclass 29, count 0 2006.173.23:45:06.45#ibcon#about to read 6, iclass 29, count 0 2006.173.23:45:06.45#ibcon#read 6, iclass 29, count 0 2006.173.23:45:06.45#ibcon#end of sib2, iclass 29, count 0 2006.173.23:45:06.45#ibcon#*mode == 0, iclass 29, count 0 2006.173.23:45:06.45#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.23:45:06.45#ibcon#[27=USB\r\n] 2006.173.23:45:06.45#ibcon#*before write, iclass 29, count 0 2006.173.23:45:06.45#ibcon#enter sib2, iclass 29, count 0 2006.173.23:45:06.45#ibcon#flushed, iclass 29, count 0 2006.173.23:45:06.45#ibcon#about to write, iclass 29, count 0 2006.173.23:45:06.45#ibcon#wrote, iclass 29, count 0 2006.173.23:45:06.45#ibcon#about to read 3, iclass 29, count 0 2006.173.23:45:06.48#ibcon#read 3, iclass 29, count 0 2006.173.23:45:06.48#ibcon#about to read 4, iclass 29, count 0 2006.173.23:45:06.48#ibcon#read 4, iclass 29, count 0 2006.173.23:45:06.48#ibcon#about to read 5, iclass 29, count 0 2006.173.23:45:06.48#ibcon#read 5, iclass 29, count 0 2006.173.23:45:06.48#ibcon#about to read 6, iclass 29, count 0 2006.173.23:45:06.48#ibcon#read 6, iclass 29, count 0 2006.173.23:45:06.48#ibcon#end of sib2, iclass 29, count 0 2006.173.23:45:06.48#ibcon#*after write, iclass 29, count 0 2006.173.23:45:06.48#ibcon#*before return 0, iclass 29, count 0 2006.173.23:45:06.48#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.173.23:45:06.48#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.173.23:45:06.48#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.23:45:06.48#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.23:45:06.48$vck44/vblo=6,719.99 2006.173.23:45:06.48#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.173.23:45:06.48#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.173.23:45:06.48#ibcon#ireg 17 cls_cnt 0 2006.173.23:45:06.48#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.23:45:06.48#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.173.23:45:06.48#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.23:45:06.48#ibcon#enter wrdev, iclass 31, count 0 2006.173.23:45:06.48#ibcon#first serial, iclass 31, count 0 2006.173.23:45:06.48#ibcon#enter sib2, iclass 31, count 0 2006.173.23:45:06.48#ibcon#flushed, iclass 31, count 0 2006.173.23:45:06.48#ibcon#about to write, iclass 31, count 0 2006.173.23:45:06.48#ibcon#wrote, iclass 31, count 0 2006.173.23:45:06.48#ibcon#about to read 3, iclass 31, count 0 2006.173.23:45:06.50#ibcon#read 3, iclass 31, count 0 2006.173.23:45:06.50#ibcon#about to read 4, iclass 31, count 0 2006.173.23:45:06.50#ibcon#read 4, iclass 31, count 0 2006.173.23:45:06.50#ibcon#about to read 5, iclass 31, count 0 2006.173.23:45:06.50#ibcon#read 5, iclass 31, count 0 2006.173.23:45:06.50#ibcon#about to read 6, iclass 31, count 0 2006.173.23:45:06.50#ibcon#read 6, iclass 31, count 0 2006.173.23:45:06.50#ibcon#end of sib2, iclass 31, count 0 2006.173.23:45:06.50#ibcon#*mode == 0, iclass 31, count 0 2006.173.23:45:06.50#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.23:45:06.50#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.23:45:06.50#ibcon#*before write, iclass 31, count 0 2006.173.23:45:06.50#ibcon#enter sib2, iclass 31, count 0 2006.173.23:45:06.50#ibcon#flushed, iclass 31, count 0 2006.173.23:45:06.50#ibcon#about to write, iclass 31, count 0 2006.173.23:45:06.50#ibcon#wrote, iclass 31, count 0 2006.173.23:45:06.50#ibcon#about to read 3, iclass 31, count 0 2006.173.23:45:06.54#ibcon#read 3, iclass 31, count 0 2006.173.23:45:06.54#ibcon#about to read 4, iclass 31, count 0 2006.173.23:45:06.54#ibcon#read 4, iclass 31, count 0 2006.173.23:45:06.54#ibcon#about to read 5, iclass 31, count 0 2006.173.23:45:06.54#ibcon#read 5, iclass 31, count 0 2006.173.23:45:06.54#ibcon#about to read 6, iclass 31, count 0 2006.173.23:45:06.54#ibcon#read 6, iclass 31, count 0 2006.173.23:45:06.54#ibcon#end of sib2, iclass 31, count 0 2006.173.23:45:06.54#ibcon#*after write, iclass 31, count 0 2006.173.23:45:06.54#ibcon#*before return 0, iclass 31, count 0 2006.173.23:45:06.54#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.173.23:45:06.54#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.173.23:45:06.54#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.23:45:06.54#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.23:45:06.54$vck44/vb=6,4 2006.173.23:45:06.54#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.173.23:45:06.54#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.173.23:45:06.54#ibcon#ireg 11 cls_cnt 2 2006.173.23:45:06.54#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.23:45:06.60#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.173.23:45:06.60#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.23:45:06.60#ibcon#enter wrdev, iclass 33, count 2 2006.173.23:45:06.60#ibcon#first serial, iclass 33, count 2 2006.173.23:45:06.60#ibcon#enter sib2, iclass 33, count 2 2006.173.23:45:06.60#ibcon#flushed, iclass 33, count 2 2006.173.23:45:06.60#ibcon#about to write, iclass 33, count 2 2006.173.23:45:06.60#ibcon#wrote, iclass 33, count 2 2006.173.23:45:06.60#ibcon#about to read 3, iclass 33, count 2 2006.173.23:45:06.62#ibcon#read 3, iclass 33, count 2 2006.173.23:45:06.62#ibcon#about to read 4, iclass 33, count 2 2006.173.23:45:06.62#ibcon#read 4, iclass 33, count 2 2006.173.23:45:06.62#ibcon#about to read 5, iclass 33, count 2 2006.173.23:45:06.62#ibcon#read 5, iclass 33, count 2 2006.173.23:45:06.62#ibcon#about to read 6, iclass 33, count 2 2006.173.23:45:06.62#ibcon#read 6, iclass 33, count 2 2006.173.23:45:06.62#ibcon#end of sib2, iclass 33, count 2 2006.173.23:45:06.62#ibcon#*mode == 0, iclass 33, count 2 2006.173.23:45:06.62#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.173.23:45:06.62#ibcon#[27=AT06-04\r\n] 2006.173.23:45:06.62#ibcon#*before write, iclass 33, count 2 2006.173.23:45:06.62#ibcon#enter sib2, iclass 33, count 2 2006.173.23:45:06.62#ibcon#flushed, iclass 33, count 2 2006.173.23:45:06.62#ibcon#about to write, iclass 33, count 2 2006.173.23:45:06.62#ibcon#wrote, iclass 33, count 2 2006.173.23:45:06.62#ibcon#about to read 3, iclass 33, count 2 2006.173.23:45:06.65#ibcon#read 3, iclass 33, count 2 2006.173.23:45:06.65#ibcon#about to read 4, iclass 33, count 2 2006.173.23:45:06.65#ibcon#read 4, iclass 33, count 2 2006.173.23:45:06.65#ibcon#about to read 5, iclass 33, count 2 2006.173.23:45:06.65#ibcon#read 5, iclass 33, count 2 2006.173.23:45:06.65#ibcon#about to read 6, iclass 33, count 2 2006.173.23:45:06.65#ibcon#read 6, iclass 33, count 2 2006.173.23:45:06.65#ibcon#end of sib2, iclass 33, count 2 2006.173.23:45:06.65#ibcon#*after write, iclass 33, count 2 2006.173.23:45:06.65#ibcon#*before return 0, iclass 33, count 2 2006.173.23:45:06.65#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.173.23:45:06.65#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.173.23:45:06.65#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.173.23:45:06.65#ibcon#ireg 7 cls_cnt 0 2006.173.23:45:06.65#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.23:45:06.77#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.173.23:45:06.77#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.23:45:06.77#ibcon#enter wrdev, iclass 33, count 0 2006.173.23:45:06.77#ibcon#first serial, iclass 33, count 0 2006.173.23:45:06.77#ibcon#enter sib2, iclass 33, count 0 2006.173.23:45:06.77#ibcon#flushed, iclass 33, count 0 2006.173.23:45:06.77#ibcon#about to write, iclass 33, count 0 2006.173.23:45:06.77#ibcon#wrote, iclass 33, count 0 2006.173.23:45:06.77#ibcon#about to read 3, iclass 33, count 0 2006.173.23:45:06.78#abcon#<5=/15 0.6 1.7 23.68 851003.2\r\n> 2006.173.23:45:06.79#ibcon#read 3, iclass 33, count 0 2006.173.23:45:06.79#ibcon#about to read 4, iclass 33, count 0 2006.173.23:45:06.79#ibcon#read 4, iclass 33, count 0 2006.173.23:45:06.79#ibcon#about to read 5, iclass 33, count 0 2006.173.23:45:06.79#ibcon#read 5, iclass 33, count 0 2006.173.23:45:06.79#ibcon#about to read 6, iclass 33, count 0 2006.173.23:45:06.79#ibcon#read 6, iclass 33, count 0 2006.173.23:45:06.79#ibcon#end of sib2, iclass 33, count 0 2006.173.23:45:06.79#ibcon#*mode == 0, iclass 33, count 0 2006.173.23:45:06.79#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.23:45:06.79#ibcon#[27=USB\r\n] 2006.173.23:45:06.79#ibcon#*before write, iclass 33, count 0 2006.173.23:45:06.79#ibcon#enter sib2, iclass 33, count 0 2006.173.23:45:06.79#ibcon#flushed, iclass 33, count 0 2006.173.23:45:06.79#ibcon#about to write, iclass 33, count 0 2006.173.23:45:06.79#ibcon#wrote, iclass 33, count 0 2006.173.23:45:06.79#ibcon#about to read 3, iclass 33, count 0 2006.173.23:45:06.80#abcon#{5=INTERFACE CLEAR} 2006.173.23:45:06.82#ibcon#read 3, iclass 33, count 0 2006.173.23:45:06.82#ibcon#about to read 4, iclass 33, count 0 2006.173.23:45:06.82#ibcon#read 4, iclass 33, count 0 2006.173.23:45:06.82#ibcon#about to read 5, iclass 33, count 0 2006.173.23:45:06.82#ibcon#read 5, iclass 33, count 0 2006.173.23:45:06.82#ibcon#about to read 6, iclass 33, count 0 2006.173.23:45:06.82#ibcon#read 6, iclass 33, count 0 2006.173.23:45:06.82#ibcon#end of sib2, iclass 33, count 0 2006.173.23:45:06.82#ibcon#*after write, iclass 33, count 0 2006.173.23:45:06.82#ibcon#*before return 0, iclass 33, count 0 2006.173.23:45:06.82#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.173.23:45:06.82#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.173.23:45:06.82#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.23:45:06.82#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.23:45:06.82$vck44/vblo=7,734.99 2006.173.23:45:06.82#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.23:45:06.82#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.23:45:06.82#ibcon#ireg 17 cls_cnt 0 2006.173.23:45:06.82#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.23:45:06.82#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.23:45:06.82#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.23:45:06.82#ibcon#enter wrdev, iclass 38, count 0 2006.173.23:45:06.82#ibcon#first serial, iclass 38, count 0 2006.173.23:45:06.82#ibcon#enter sib2, iclass 38, count 0 2006.173.23:45:06.82#ibcon#flushed, iclass 38, count 0 2006.173.23:45:06.82#ibcon#about to write, iclass 38, count 0 2006.173.23:45:06.82#ibcon#wrote, iclass 38, count 0 2006.173.23:45:06.82#ibcon#about to read 3, iclass 38, count 0 2006.173.23:45:06.84#ibcon#read 3, iclass 38, count 0 2006.173.23:45:06.84#ibcon#about to read 4, iclass 38, count 0 2006.173.23:45:06.84#ibcon#read 4, iclass 38, count 0 2006.173.23:45:06.84#ibcon#about to read 5, iclass 38, count 0 2006.173.23:45:06.84#ibcon#read 5, iclass 38, count 0 2006.173.23:45:06.84#ibcon#about to read 6, iclass 38, count 0 2006.173.23:45:06.84#ibcon#read 6, iclass 38, count 0 2006.173.23:45:06.84#ibcon#end of sib2, iclass 38, count 0 2006.173.23:45:06.84#ibcon#*mode == 0, iclass 38, count 0 2006.173.23:45:06.84#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.23:45:06.84#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.23:45:06.84#ibcon#*before write, iclass 38, count 0 2006.173.23:45:06.84#ibcon#enter sib2, iclass 38, count 0 2006.173.23:45:06.84#ibcon#flushed, iclass 38, count 0 2006.173.23:45:06.84#ibcon#about to write, iclass 38, count 0 2006.173.23:45:06.84#ibcon#wrote, iclass 38, count 0 2006.173.23:45:06.84#ibcon#about to read 3, iclass 38, count 0 2006.173.23:45:06.86#abcon#[5=S1D000X0/0*\r\n] 2006.173.23:45:06.88#ibcon#read 3, iclass 38, count 0 2006.173.23:45:06.88#ibcon#about to read 4, iclass 38, count 0 2006.173.23:45:06.88#ibcon#read 4, iclass 38, count 0 2006.173.23:45:06.88#ibcon#about to read 5, iclass 38, count 0 2006.173.23:45:06.88#ibcon#read 5, iclass 38, count 0 2006.173.23:45:06.88#ibcon#about to read 6, iclass 38, count 0 2006.173.23:45:06.88#ibcon#read 6, iclass 38, count 0 2006.173.23:45:06.88#ibcon#end of sib2, iclass 38, count 0 2006.173.23:45:06.88#ibcon#*after write, iclass 38, count 0 2006.173.23:45:06.88#ibcon#*before return 0, iclass 38, count 0 2006.173.23:45:06.88#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.23:45:06.88#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.23:45:06.88#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.23:45:06.88#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.23:45:06.88$vck44/vb=7,4 2006.173.23:45:06.88#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.173.23:45:06.88#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.173.23:45:06.88#ibcon#ireg 11 cls_cnt 2 2006.173.23:45:06.88#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.23:45:06.94#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.173.23:45:06.94#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.23:45:06.94#ibcon#enter wrdev, iclass 3, count 2 2006.173.23:45:06.94#ibcon#first serial, iclass 3, count 2 2006.173.23:45:06.94#ibcon#enter sib2, iclass 3, count 2 2006.173.23:45:06.94#ibcon#flushed, iclass 3, count 2 2006.173.23:45:06.94#ibcon#about to write, iclass 3, count 2 2006.173.23:45:06.94#ibcon#wrote, iclass 3, count 2 2006.173.23:45:06.94#ibcon#about to read 3, iclass 3, count 2 2006.173.23:45:06.96#ibcon#read 3, iclass 3, count 2 2006.173.23:45:06.96#ibcon#about to read 4, iclass 3, count 2 2006.173.23:45:06.96#ibcon#read 4, iclass 3, count 2 2006.173.23:45:06.96#ibcon#about to read 5, iclass 3, count 2 2006.173.23:45:06.96#ibcon#read 5, iclass 3, count 2 2006.173.23:45:06.96#ibcon#about to read 6, iclass 3, count 2 2006.173.23:45:06.96#ibcon#read 6, iclass 3, count 2 2006.173.23:45:06.96#ibcon#end of sib2, iclass 3, count 2 2006.173.23:45:06.96#ibcon#*mode == 0, iclass 3, count 2 2006.173.23:45:06.96#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.173.23:45:06.96#ibcon#[27=AT07-04\r\n] 2006.173.23:45:06.96#ibcon#*before write, iclass 3, count 2 2006.173.23:45:06.96#ibcon#enter sib2, iclass 3, count 2 2006.173.23:45:06.96#ibcon#flushed, iclass 3, count 2 2006.173.23:45:06.96#ibcon#about to write, iclass 3, count 2 2006.173.23:45:06.96#ibcon#wrote, iclass 3, count 2 2006.173.23:45:06.96#ibcon#about to read 3, iclass 3, count 2 2006.173.23:45:06.99#ibcon#read 3, iclass 3, count 2 2006.173.23:45:06.99#ibcon#about to read 4, iclass 3, count 2 2006.173.23:45:06.99#ibcon#read 4, iclass 3, count 2 2006.173.23:45:06.99#ibcon#about to read 5, iclass 3, count 2 2006.173.23:45:06.99#ibcon#read 5, iclass 3, count 2 2006.173.23:45:06.99#ibcon#about to read 6, iclass 3, count 2 2006.173.23:45:06.99#ibcon#read 6, iclass 3, count 2 2006.173.23:45:06.99#ibcon#end of sib2, iclass 3, count 2 2006.173.23:45:06.99#ibcon#*after write, iclass 3, count 2 2006.173.23:45:06.99#ibcon#*before return 0, iclass 3, count 2 2006.173.23:45:06.99#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.173.23:45:06.99#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.173.23:45:06.99#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.173.23:45:06.99#ibcon#ireg 7 cls_cnt 0 2006.173.23:45:06.99#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.23:45:07.11#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.173.23:45:07.11#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.23:45:07.11#ibcon#enter wrdev, iclass 3, count 0 2006.173.23:45:07.11#ibcon#first serial, iclass 3, count 0 2006.173.23:45:07.11#ibcon#enter sib2, iclass 3, count 0 2006.173.23:45:07.11#ibcon#flushed, iclass 3, count 0 2006.173.23:45:07.11#ibcon#about to write, iclass 3, count 0 2006.173.23:45:07.11#ibcon#wrote, iclass 3, count 0 2006.173.23:45:07.11#ibcon#about to read 3, iclass 3, count 0 2006.173.23:45:07.13#ibcon#read 3, iclass 3, count 0 2006.173.23:45:07.13#ibcon#about to read 4, iclass 3, count 0 2006.173.23:45:07.13#ibcon#read 4, iclass 3, count 0 2006.173.23:45:07.13#ibcon#about to read 5, iclass 3, count 0 2006.173.23:45:07.13#ibcon#read 5, iclass 3, count 0 2006.173.23:45:07.13#ibcon#about to read 6, iclass 3, count 0 2006.173.23:45:07.13#ibcon#read 6, iclass 3, count 0 2006.173.23:45:07.13#ibcon#end of sib2, iclass 3, count 0 2006.173.23:45:07.13#ibcon#*mode == 0, iclass 3, count 0 2006.173.23:45:07.13#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.23:45:07.13#ibcon#[27=USB\r\n] 2006.173.23:45:07.13#ibcon#*before write, iclass 3, count 0 2006.173.23:45:07.13#ibcon#enter sib2, iclass 3, count 0 2006.173.23:45:07.13#ibcon#flushed, iclass 3, count 0 2006.173.23:45:07.13#ibcon#about to write, iclass 3, count 0 2006.173.23:45:07.13#ibcon#wrote, iclass 3, count 0 2006.173.23:45:07.13#ibcon#about to read 3, iclass 3, count 0 2006.173.23:45:07.16#ibcon#read 3, iclass 3, count 0 2006.173.23:45:07.16#ibcon#about to read 4, iclass 3, count 0 2006.173.23:45:07.16#ibcon#read 4, iclass 3, count 0 2006.173.23:45:07.16#ibcon#about to read 5, iclass 3, count 0 2006.173.23:45:07.16#ibcon#read 5, iclass 3, count 0 2006.173.23:45:07.16#ibcon#about to read 6, iclass 3, count 0 2006.173.23:45:07.16#ibcon#read 6, iclass 3, count 0 2006.173.23:45:07.16#ibcon#end of sib2, iclass 3, count 0 2006.173.23:45:07.16#ibcon#*after write, iclass 3, count 0 2006.173.23:45:07.16#ibcon#*before return 0, iclass 3, count 0 2006.173.23:45:07.16#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.173.23:45:07.16#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.173.23:45:07.16#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.23:45:07.16#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.23:45:07.16$vck44/vblo=8,744.99 2006.173.23:45:07.16#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.173.23:45:07.16#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.173.23:45:07.16#ibcon#ireg 17 cls_cnt 0 2006.173.23:45:07.16#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.23:45:07.16#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.173.23:45:07.16#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.23:45:07.16#ibcon#enter wrdev, iclass 5, count 0 2006.173.23:45:07.16#ibcon#first serial, iclass 5, count 0 2006.173.23:45:07.16#ibcon#enter sib2, iclass 5, count 0 2006.173.23:45:07.16#ibcon#flushed, iclass 5, count 0 2006.173.23:45:07.16#ibcon#about to write, iclass 5, count 0 2006.173.23:45:07.16#ibcon#wrote, iclass 5, count 0 2006.173.23:45:07.16#ibcon#about to read 3, iclass 5, count 0 2006.173.23:45:07.18#ibcon#read 3, iclass 5, count 0 2006.173.23:45:07.18#ibcon#about to read 4, iclass 5, count 0 2006.173.23:45:07.18#ibcon#read 4, iclass 5, count 0 2006.173.23:45:07.18#ibcon#about to read 5, iclass 5, count 0 2006.173.23:45:07.18#ibcon#read 5, iclass 5, count 0 2006.173.23:45:07.18#ibcon#about to read 6, iclass 5, count 0 2006.173.23:45:07.18#ibcon#read 6, iclass 5, count 0 2006.173.23:45:07.18#ibcon#end of sib2, iclass 5, count 0 2006.173.23:45:07.18#ibcon#*mode == 0, iclass 5, count 0 2006.173.23:45:07.18#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.23:45:07.18#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.23:45:07.18#ibcon#*before write, iclass 5, count 0 2006.173.23:45:07.18#ibcon#enter sib2, iclass 5, count 0 2006.173.23:45:07.18#ibcon#flushed, iclass 5, count 0 2006.173.23:45:07.18#ibcon#about to write, iclass 5, count 0 2006.173.23:45:07.18#ibcon#wrote, iclass 5, count 0 2006.173.23:45:07.18#ibcon#about to read 3, iclass 5, count 0 2006.173.23:45:07.22#ibcon#read 3, iclass 5, count 0 2006.173.23:45:07.22#ibcon#about to read 4, iclass 5, count 0 2006.173.23:45:07.22#ibcon#read 4, iclass 5, count 0 2006.173.23:45:07.22#ibcon#about to read 5, iclass 5, count 0 2006.173.23:45:07.22#ibcon#read 5, iclass 5, count 0 2006.173.23:45:07.22#ibcon#about to read 6, iclass 5, count 0 2006.173.23:45:07.22#ibcon#read 6, iclass 5, count 0 2006.173.23:45:07.22#ibcon#end of sib2, iclass 5, count 0 2006.173.23:45:07.22#ibcon#*after write, iclass 5, count 0 2006.173.23:45:07.22#ibcon#*before return 0, iclass 5, count 0 2006.173.23:45:07.22#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.173.23:45:07.22#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.173.23:45:07.22#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.23:45:07.22#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.23:45:07.22$vck44/vb=8,4 2006.173.23:45:07.22#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.173.23:45:07.22#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.173.23:45:07.22#ibcon#ireg 11 cls_cnt 2 2006.173.23:45:07.22#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.23:45:07.28#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.173.23:45:07.28#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.23:45:07.28#ibcon#enter wrdev, iclass 7, count 2 2006.173.23:45:07.28#ibcon#first serial, iclass 7, count 2 2006.173.23:45:07.28#ibcon#enter sib2, iclass 7, count 2 2006.173.23:45:07.28#ibcon#flushed, iclass 7, count 2 2006.173.23:45:07.28#ibcon#about to write, iclass 7, count 2 2006.173.23:45:07.28#ibcon#wrote, iclass 7, count 2 2006.173.23:45:07.28#ibcon#about to read 3, iclass 7, count 2 2006.173.23:45:07.30#ibcon#read 3, iclass 7, count 2 2006.173.23:45:07.30#ibcon#about to read 4, iclass 7, count 2 2006.173.23:45:07.30#ibcon#read 4, iclass 7, count 2 2006.173.23:45:07.30#ibcon#about to read 5, iclass 7, count 2 2006.173.23:45:07.30#ibcon#read 5, iclass 7, count 2 2006.173.23:45:07.30#ibcon#about to read 6, iclass 7, count 2 2006.173.23:45:07.30#ibcon#read 6, iclass 7, count 2 2006.173.23:45:07.30#ibcon#end of sib2, iclass 7, count 2 2006.173.23:45:07.30#ibcon#*mode == 0, iclass 7, count 2 2006.173.23:45:07.30#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.173.23:45:07.30#ibcon#[27=AT08-04\r\n] 2006.173.23:45:07.30#ibcon#*before write, iclass 7, count 2 2006.173.23:45:07.30#ibcon#enter sib2, iclass 7, count 2 2006.173.23:45:07.30#ibcon#flushed, iclass 7, count 2 2006.173.23:45:07.30#ibcon#about to write, iclass 7, count 2 2006.173.23:45:07.30#ibcon#wrote, iclass 7, count 2 2006.173.23:45:07.30#ibcon#about to read 3, iclass 7, count 2 2006.173.23:45:07.33#ibcon#read 3, iclass 7, count 2 2006.173.23:45:07.33#ibcon#about to read 4, iclass 7, count 2 2006.173.23:45:07.33#ibcon#read 4, iclass 7, count 2 2006.173.23:45:07.33#ibcon#about to read 5, iclass 7, count 2 2006.173.23:45:07.33#ibcon#read 5, iclass 7, count 2 2006.173.23:45:07.33#ibcon#about to read 6, iclass 7, count 2 2006.173.23:45:07.33#ibcon#read 6, iclass 7, count 2 2006.173.23:45:07.33#ibcon#end of sib2, iclass 7, count 2 2006.173.23:45:07.33#ibcon#*after write, iclass 7, count 2 2006.173.23:45:07.33#ibcon#*before return 0, iclass 7, count 2 2006.173.23:45:07.33#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.173.23:45:07.33#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.173.23:45:07.33#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.173.23:45:07.33#ibcon#ireg 7 cls_cnt 0 2006.173.23:45:07.33#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.23:45:07.45#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.173.23:45:07.45#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.23:45:07.45#ibcon#enter wrdev, iclass 7, count 0 2006.173.23:45:07.45#ibcon#first serial, iclass 7, count 0 2006.173.23:45:07.45#ibcon#enter sib2, iclass 7, count 0 2006.173.23:45:07.45#ibcon#flushed, iclass 7, count 0 2006.173.23:45:07.45#ibcon#about to write, iclass 7, count 0 2006.173.23:45:07.45#ibcon#wrote, iclass 7, count 0 2006.173.23:45:07.45#ibcon#about to read 3, iclass 7, count 0 2006.173.23:45:07.47#ibcon#read 3, iclass 7, count 0 2006.173.23:45:07.47#ibcon#about to read 4, iclass 7, count 0 2006.173.23:45:07.47#ibcon#read 4, iclass 7, count 0 2006.173.23:45:07.47#ibcon#about to read 5, iclass 7, count 0 2006.173.23:45:07.47#ibcon#read 5, iclass 7, count 0 2006.173.23:45:07.47#ibcon#about to read 6, iclass 7, count 0 2006.173.23:45:07.47#ibcon#read 6, iclass 7, count 0 2006.173.23:45:07.47#ibcon#end of sib2, iclass 7, count 0 2006.173.23:45:07.47#ibcon#*mode == 0, iclass 7, count 0 2006.173.23:45:07.47#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.23:45:07.47#ibcon#[27=USB\r\n] 2006.173.23:45:07.47#ibcon#*before write, iclass 7, count 0 2006.173.23:45:07.47#ibcon#enter sib2, iclass 7, count 0 2006.173.23:45:07.47#ibcon#flushed, iclass 7, count 0 2006.173.23:45:07.47#ibcon#about to write, iclass 7, count 0 2006.173.23:45:07.47#ibcon#wrote, iclass 7, count 0 2006.173.23:45:07.47#ibcon#about to read 3, iclass 7, count 0 2006.173.23:45:07.50#ibcon#read 3, iclass 7, count 0 2006.173.23:45:07.50#ibcon#about to read 4, iclass 7, count 0 2006.173.23:45:07.50#ibcon#read 4, iclass 7, count 0 2006.173.23:45:07.50#ibcon#about to read 5, iclass 7, count 0 2006.173.23:45:07.50#ibcon#read 5, iclass 7, count 0 2006.173.23:45:07.50#ibcon#about to read 6, iclass 7, count 0 2006.173.23:45:07.50#ibcon#read 6, iclass 7, count 0 2006.173.23:45:07.50#ibcon#end of sib2, iclass 7, count 0 2006.173.23:45:07.50#ibcon#*after write, iclass 7, count 0 2006.173.23:45:07.50#ibcon#*before return 0, iclass 7, count 0 2006.173.23:45:07.50#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.173.23:45:07.50#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.173.23:45:07.50#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.23:45:07.50#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.23:45:07.50$vck44/vabw=wide 2006.173.23:45:07.50#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.173.23:45:07.50#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.173.23:45:07.50#ibcon#ireg 8 cls_cnt 0 2006.173.23:45:07.50#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.23:45:07.50#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.173.23:45:07.50#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.23:45:07.50#ibcon#enter wrdev, iclass 11, count 0 2006.173.23:45:07.50#ibcon#first serial, iclass 11, count 0 2006.173.23:45:07.50#ibcon#enter sib2, iclass 11, count 0 2006.173.23:45:07.50#ibcon#flushed, iclass 11, count 0 2006.173.23:45:07.50#ibcon#about to write, iclass 11, count 0 2006.173.23:45:07.50#ibcon#wrote, iclass 11, count 0 2006.173.23:45:07.50#ibcon#about to read 3, iclass 11, count 0 2006.173.23:45:07.52#ibcon#read 3, iclass 11, count 0 2006.173.23:45:07.52#ibcon#about to read 4, iclass 11, count 0 2006.173.23:45:07.52#ibcon#read 4, iclass 11, count 0 2006.173.23:45:07.52#ibcon#about to read 5, iclass 11, count 0 2006.173.23:45:07.52#ibcon#read 5, iclass 11, count 0 2006.173.23:45:07.52#ibcon#about to read 6, iclass 11, count 0 2006.173.23:45:07.52#ibcon#read 6, iclass 11, count 0 2006.173.23:45:07.52#ibcon#end of sib2, iclass 11, count 0 2006.173.23:45:07.52#ibcon#*mode == 0, iclass 11, count 0 2006.173.23:45:07.52#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.23:45:07.52#ibcon#[25=BW32\r\n] 2006.173.23:45:07.52#ibcon#*before write, iclass 11, count 0 2006.173.23:45:07.52#ibcon#enter sib2, iclass 11, count 0 2006.173.23:45:07.52#ibcon#flushed, iclass 11, count 0 2006.173.23:45:07.52#ibcon#about to write, iclass 11, count 0 2006.173.23:45:07.52#ibcon#wrote, iclass 11, count 0 2006.173.23:45:07.52#ibcon#about to read 3, iclass 11, count 0 2006.173.23:45:07.55#ibcon#read 3, iclass 11, count 0 2006.173.23:45:07.55#ibcon#about to read 4, iclass 11, count 0 2006.173.23:45:07.55#ibcon#read 4, iclass 11, count 0 2006.173.23:45:07.55#ibcon#about to read 5, iclass 11, count 0 2006.173.23:45:07.55#ibcon#read 5, iclass 11, count 0 2006.173.23:45:07.55#ibcon#about to read 6, iclass 11, count 0 2006.173.23:45:07.55#ibcon#read 6, iclass 11, count 0 2006.173.23:45:07.55#ibcon#end of sib2, iclass 11, count 0 2006.173.23:45:07.55#ibcon#*after write, iclass 11, count 0 2006.173.23:45:07.55#ibcon#*before return 0, iclass 11, count 0 2006.173.23:45:07.55#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.173.23:45:07.55#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.173.23:45:07.55#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.23:45:07.55#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.23:45:07.55$vck44/vbbw=wide 2006.173.23:45:07.55#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.23:45:07.55#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.23:45:07.55#ibcon#ireg 8 cls_cnt 0 2006.173.23:45:07.55#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.23:45:07.62#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.23:45:07.62#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.23:45:07.62#ibcon#enter wrdev, iclass 13, count 0 2006.173.23:45:07.62#ibcon#first serial, iclass 13, count 0 2006.173.23:45:07.62#ibcon#enter sib2, iclass 13, count 0 2006.173.23:45:07.62#ibcon#flushed, iclass 13, count 0 2006.173.23:45:07.62#ibcon#about to write, iclass 13, count 0 2006.173.23:45:07.62#ibcon#wrote, iclass 13, count 0 2006.173.23:45:07.62#ibcon#about to read 3, iclass 13, count 0 2006.173.23:45:07.64#ibcon#read 3, iclass 13, count 0 2006.173.23:45:07.64#ibcon#about to read 4, iclass 13, count 0 2006.173.23:45:07.64#ibcon#read 4, iclass 13, count 0 2006.173.23:45:07.64#ibcon#about to read 5, iclass 13, count 0 2006.173.23:45:07.64#ibcon#read 5, iclass 13, count 0 2006.173.23:45:07.64#ibcon#about to read 6, iclass 13, count 0 2006.173.23:45:07.64#ibcon#read 6, iclass 13, count 0 2006.173.23:45:07.64#ibcon#end of sib2, iclass 13, count 0 2006.173.23:45:07.64#ibcon#*mode == 0, iclass 13, count 0 2006.173.23:45:07.64#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.23:45:07.64#ibcon#[27=BW32\r\n] 2006.173.23:45:07.64#ibcon#*before write, iclass 13, count 0 2006.173.23:45:07.64#ibcon#enter sib2, iclass 13, count 0 2006.173.23:45:07.64#ibcon#flushed, iclass 13, count 0 2006.173.23:45:07.64#ibcon#about to write, iclass 13, count 0 2006.173.23:45:07.64#ibcon#wrote, iclass 13, count 0 2006.173.23:45:07.64#ibcon#about to read 3, iclass 13, count 0 2006.173.23:45:07.67#ibcon#read 3, iclass 13, count 0 2006.173.23:45:07.67#ibcon#about to read 4, iclass 13, count 0 2006.173.23:45:07.67#ibcon#read 4, iclass 13, count 0 2006.173.23:45:07.67#ibcon#about to read 5, iclass 13, count 0 2006.173.23:45:07.67#ibcon#read 5, iclass 13, count 0 2006.173.23:45:07.67#ibcon#about to read 6, iclass 13, count 0 2006.173.23:45:07.67#ibcon#read 6, iclass 13, count 0 2006.173.23:45:07.67#ibcon#end of sib2, iclass 13, count 0 2006.173.23:45:07.67#ibcon#*after write, iclass 13, count 0 2006.173.23:45:07.67#ibcon#*before return 0, iclass 13, count 0 2006.173.23:45:07.67#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.23:45:07.67#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.23:45:07.67#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.23:45:07.67#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.23:45:07.67$setupk4/ifdk4 2006.173.23:45:07.67$ifdk4/lo= 2006.173.23:45:07.67$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.23:45:07.67$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.23:45:07.67$ifdk4/patch= 2006.173.23:45:07.68$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.23:45:07.68$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.23:45:07.68$setupk4/!*+20s 2006.173.23:45:16.95#abcon#<5=/15 0.6 1.7 23.69 861003.2\r\n> 2006.173.23:45:16.97#abcon#{5=INTERFACE CLEAR} 2006.173.23:45:17.03#abcon#[5=S1D000X0/0*\r\n] 2006.173.23:45:22.19$setupk4/"tpicd 2006.173.23:45:22.19$setupk4/echo=off 2006.173.23:45:22.19$setupk4/xlog=off 2006.173.23:45:22.19:!2006.173.23:50:47 2006.173.23:45:56.14#trakl#Source acquired 2006.173.23:45:57.14#flagr#flagr/antenna,acquired 2006.173.23:50:47.00:preob 2006.173.23:50:47.13/onsource/TRACKING 2006.173.23:50:47.13:!2006.173.23:50:57 2006.173.23:50:57.00:"tape 2006.173.23:50:57.00:"st=record 2006.173.23:50:57.00:data_valid=on 2006.173.23:50:57.00:midob 2006.173.23:50:57.13/onsource/TRACKING 2006.173.23:50:57.13/wx/23.85,1003.3,83 2006.173.23:50:57.36/cable/+6.5076E-03 2006.173.23:50:58.45/va/01,07,usb,yes,39,42 2006.173.23:50:58.45/va/02,06,usb,yes,39,39 2006.173.23:50:58.45/va/03,05,usb,yes,49,51 2006.173.23:50:58.45/va/04,06,usb,yes,39,41 2006.173.23:50:58.45/va/05,04,usb,yes,31,32 2006.173.23:50:58.45/va/06,03,usb,yes,43,43 2006.173.23:50:58.45/va/07,04,usb,yes,35,36 2006.173.23:50:58.45/va/08,04,usb,yes,30,36 2006.173.23:50:58.68/valo/01,524.99,yes,locked 2006.173.23:50:58.68/valo/02,534.99,yes,locked 2006.173.23:50:58.68/valo/03,564.99,yes,locked 2006.173.23:50:58.68/valo/04,624.99,yes,locked 2006.173.23:50:58.68/valo/05,734.99,yes,locked 2006.173.23:50:58.68/valo/06,814.99,yes,locked 2006.173.23:50:58.68/valo/07,864.99,yes,locked 2006.173.23:50:58.68/valo/08,884.99,yes,locked 2006.173.23:50:59.77/vb/01,04,usb,yes,31,29 2006.173.23:50:59.77/vb/02,04,usb,yes,33,33 2006.173.23:50:59.77/vb/03,04,usb,yes,30,33 2006.173.23:50:59.77/vb/04,04,usb,yes,35,34 2006.173.23:50:59.77/vb/05,04,usb,yes,27,30 2006.173.23:50:59.77/vb/06,04,usb,yes,32,28 2006.173.23:50:59.77/vb/07,04,usb,yes,32,31 2006.173.23:50:59.77/vb/08,04,usb,yes,29,33 2006.173.23:51:00.00/vblo/01,629.99,yes,locked 2006.173.23:51:00.00/vblo/02,634.99,yes,locked 2006.173.23:51:00.00/vblo/03,649.99,yes,locked 2006.173.23:51:00.00/vblo/04,679.99,yes,locked 2006.173.23:51:00.00/vblo/05,709.99,yes,locked 2006.173.23:51:00.00/vblo/06,719.99,yes,locked 2006.173.23:51:00.00/vblo/07,734.99,yes,locked 2006.173.23:51:00.00/vblo/08,744.99,yes,locked 2006.173.23:51:00.15/vabw/8 2006.173.23:51:00.30/vbbw/8 2006.173.23:51:00.41/xfe/off,on,14.5 2006.173.23:51:00.79/ifatt/23,28,28,28 2006.173.23:51:01.08/fmout-gps/S +3.95E-07 2006.173.23:51:01.13:!2006.173.23:52:17 2006.173.23:52:17.01:data_valid=off 2006.173.23:52:17.02:"et 2006.173.23:52:17.02:!+3s 2006.173.23:52:20.03:"tape 2006.173.23:52:20.04:postob 2006.173.23:52:20.11/cable/+6.5092E-03 2006.173.23:52:20.12/wx/23.87,1003.4,82 2006.173.23:52:20.17/fmout-gps/S +3.96E-07 2006.173.23:52:20.17:scan_name=173-2356,jd0606,50 2006.173.23:52:20.17:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.173.23:52:21.14#flagr#flagr/antenna,new-source 2006.173.23:52:21.15:checkk5 2006.173.23:52:21.55/chk_autoobs//k5ts1/ autoobs is running! 2006.173.23:52:21.94/chk_autoobs//k5ts2/ autoobs is running! 2006.173.23:52:22.34/chk_autoobs//k5ts3/ autoobs is running! 2006.173.23:52:22.75/chk_autoobs//k5ts4/ autoobs is running! 2006.173.23:52:23.12/chk_obsdata//k5ts1/T1732350??a.dat file size is correct (nominal:320MB, actual:320MB). 2006.173.23:52:23.53/chk_obsdata//k5ts2/T1732350??b.dat file size is correct (nominal:320MB, actual:320MB). 2006.173.23:52:23.92/chk_obsdata//k5ts3/T1732350??c.dat file size is correct (nominal:320MB, actual:320MB). 2006.173.23:52:24.31/chk_obsdata//k5ts4/T1732350??d.dat file size is correct (nominal:320MB, actual:320MB). 2006.173.23:52:25.03/k5log//k5ts1_log_newline 2006.173.23:52:25.72/k5log//k5ts2_log_newline 2006.173.23:52:26.44/k5log//k5ts3_log_newline 2006.173.23:52:27.14/k5log//k5ts4_log_newline 2006.173.23:52:27.16/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.23:52:27.16:setupk4=1 2006.173.23:52:27.16$setupk4/echo=on 2006.173.23:52:27.16$setupk4/pcalon 2006.173.23:52:27.16$pcalon/"no phase cal control is implemented here 2006.173.23:52:27.16$setupk4/"tpicd=stop 2006.173.23:52:27.16$setupk4/"rec=synch_on 2006.173.23:52:27.16$setupk4/"rec_mode=128 2006.173.23:52:27.16$setupk4/!* 2006.173.23:52:27.16$setupk4/recpk4 2006.173.23:52:27.16$recpk4/recpatch= 2006.173.23:52:27.17$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.23:52:27.17$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.23:52:27.17$setupk4/vck44 2006.173.23:52:27.17$vck44/valo=1,524.99 2006.173.23:52:27.17#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.23:52:27.17#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.23:52:27.17#ibcon#ireg 17 cls_cnt 0 2006.173.23:52:27.17#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.23:52:27.17#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.23:52:27.17#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.23:52:27.17#ibcon#enter wrdev, iclass 10, count 0 2006.173.23:52:27.17#ibcon#first serial, iclass 10, count 0 2006.173.23:52:27.17#ibcon#enter sib2, iclass 10, count 0 2006.173.23:52:27.17#ibcon#flushed, iclass 10, count 0 2006.173.23:52:27.17#ibcon#about to write, iclass 10, count 0 2006.173.23:52:27.17#ibcon#wrote, iclass 10, count 0 2006.173.23:52:27.17#ibcon#about to read 3, iclass 10, count 0 2006.173.23:52:27.18#ibcon#read 3, iclass 10, count 0 2006.173.23:52:27.18#ibcon#about to read 4, iclass 10, count 0 2006.173.23:52:27.18#ibcon#read 4, iclass 10, count 0 2006.173.23:52:27.18#ibcon#about to read 5, iclass 10, count 0 2006.173.23:52:27.18#ibcon#read 5, iclass 10, count 0 2006.173.23:52:27.18#ibcon#about to read 6, iclass 10, count 0 2006.173.23:52:27.18#ibcon#read 6, iclass 10, count 0 2006.173.23:52:27.18#ibcon#end of sib2, iclass 10, count 0 2006.173.23:52:27.18#ibcon#*mode == 0, iclass 10, count 0 2006.173.23:52:27.18#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.23:52:27.18#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.23:52:27.18#ibcon#*before write, iclass 10, count 0 2006.173.23:52:27.18#ibcon#enter sib2, iclass 10, count 0 2006.173.23:52:27.18#ibcon#flushed, iclass 10, count 0 2006.173.23:52:27.18#ibcon#about to write, iclass 10, count 0 2006.173.23:52:27.18#ibcon#wrote, iclass 10, count 0 2006.173.23:52:27.18#ibcon#about to read 3, iclass 10, count 0 2006.173.23:52:27.23#ibcon#read 3, iclass 10, count 0 2006.173.23:52:27.23#ibcon#about to read 4, iclass 10, count 0 2006.173.23:52:27.23#ibcon#read 4, iclass 10, count 0 2006.173.23:52:27.23#ibcon#about to read 5, iclass 10, count 0 2006.173.23:52:27.23#ibcon#read 5, iclass 10, count 0 2006.173.23:52:27.23#ibcon#about to read 6, iclass 10, count 0 2006.173.23:52:27.23#ibcon#read 6, iclass 10, count 0 2006.173.23:52:27.23#ibcon#end of sib2, iclass 10, count 0 2006.173.23:52:27.23#ibcon#*after write, iclass 10, count 0 2006.173.23:52:27.23#ibcon#*before return 0, iclass 10, count 0 2006.173.23:52:27.23#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.23:52:27.23#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.23:52:27.23#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.23:52:27.23#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.23:52:27.23$vck44/va=1,7 2006.173.23:52:27.23#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.23:52:27.23#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.23:52:27.23#ibcon#ireg 11 cls_cnt 2 2006.173.23:52:27.23#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.23:52:27.23#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.23:52:27.23#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.23:52:27.23#ibcon#enter wrdev, iclass 12, count 2 2006.173.23:52:27.23#ibcon#first serial, iclass 12, count 2 2006.173.23:52:27.23#ibcon#enter sib2, iclass 12, count 2 2006.173.23:52:27.23#ibcon#flushed, iclass 12, count 2 2006.173.23:52:27.23#ibcon#about to write, iclass 12, count 2 2006.173.23:52:27.23#ibcon#wrote, iclass 12, count 2 2006.173.23:52:27.23#ibcon#about to read 3, iclass 12, count 2 2006.173.23:52:27.25#ibcon#read 3, iclass 12, count 2 2006.173.23:52:27.25#ibcon#about to read 4, iclass 12, count 2 2006.173.23:52:27.25#ibcon#read 4, iclass 12, count 2 2006.173.23:52:27.25#ibcon#about to read 5, iclass 12, count 2 2006.173.23:52:27.25#ibcon#read 5, iclass 12, count 2 2006.173.23:52:27.25#ibcon#about to read 6, iclass 12, count 2 2006.173.23:52:27.25#ibcon#read 6, iclass 12, count 2 2006.173.23:52:27.25#ibcon#end of sib2, iclass 12, count 2 2006.173.23:52:27.25#ibcon#*mode == 0, iclass 12, count 2 2006.173.23:52:27.25#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.23:52:27.25#ibcon#[25=AT01-07\r\n] 2006.173.23:52:27.25#ibcon#*before write, iclass 12, count 2 2006.173.23:52:27.25#ibcon#enter sib2, iclass 12, count 2 2006.173.23:52:27.25#ibcon#flushed, iclass 12, count 2 2006.173.23:52:27.25#ibcon#about to write, iclass 12, count 2 2006.173.23:52:27.25#ibcon#wrote, iclass 12, count 2 2006.173.23:52:27.25#ibcon#about to read 3, iclass 12, count 2 2006.173.23:52:27.28#ibcon#read 3, iclass 12, count 2 2006.173.23:52:27.28#ibcon#about to read 4, iclass 12, count 2 2006.173.23:52:27.28#ibcon#read 4, iclass 12, count 2 2006.173.23:52:27.28#ibcon#about to read 5, iclass 12, count 2 2006.173.23:52:27.28#ibcon#read 5, iclass 12, count 2 2006.173.23:52:27.28#ibcon#about to read 6, iclass 12, count 2 2006.173.23:52:27.28#ibcon#read 6, iclass 12, count 2 2006.173.23:52:27.28#ibcon#end of sib2, iclass 12, count 2 2006.173.23:52:27.28#ibcon#*after write, iclass 12, count 2 2006.173.23:52:27.28#ibcon#*before return 0, iclass 12, count 2 2006.173.23:52:27.28#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.23:52:27.28#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.23:52:27.28#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.23:52:27.28#ibcon#ireg 7 cls_cnt 0 2006.173.23:52:27.28#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.23:52:27.40#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.23:52:27.40#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.23:52:27.40#ibcon#enter wrdev, iclass 12, count 0 2006.173.23:52:27.40#ibcon#first serial, iclass 12, count 0 2006.173.23:52:27.40#ibcon#enter sib2, iclass 12, count 0 2006.173.23:52:27.40#ibcon#flushed, iclass 12, count 0 2006.173.23:52:27.40#ibcon#about to write, iclass 12, count 0 2006.173.23:52:27.40#ibcon#wrote, iclass 12, count 0 2006.173.23:52:27.40#ibcon#about to read 3, iclass 12, count 0 2006.173.23:52:27.42#ibcon#read 3, iclass 12, count 0 2006.173.23:52:27.42#ibcon#about to read 4, iclass 12, count 0 2006.173.23:52:27.42#ibcon#read 4, iclass 12, count 0 2006.173.23:52:27.42#ibcon#about to read 5, iclass 12, count 0 2006.173.23:52:27.42#ibcon#read 5, iclass 12, count 0 2006.173.23:52:27.42#ibcon#about to read 6, iclass 12, count 0 2006.173.23:52:27.42#ibcon#read 6, iclass 12, count 0 2006.173.23:52:27.42#ibcon#end of sib2, iclass 12, count 0 2006.173.23:52:27.42#ibcon#*mode == 0, iclass 12, count 0 2006.173.23:52:27.42#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.23:52:27.42#ibcon#[25=USB\r\n] 2006.173.23:52:27.42#ibcon#*before write, iclass 12, count 0 2006.173.23:52:27.42#ibcon#enter sib2, iclass 12, count 0 2006.173.23:52:27.42#ibcon#flushed, iclass 12, count 0 2006.173.23:52:27.42#ibcon#about to write, iclass 12, count 0 2006.173.23:52:27.42#ibcon#wrote, iclass 12, count 0 2006.173.23:52:27.42#ibcon#about to read 3, iclass 12, count 0 2006.173.23:52:27.45#ibcon#read 3, iclass 12, count 0 2006.173.23:52:27.45#ibcon#about to read 4, iclass 12, count 0 2006.173.23:52:27.45#ibcon#read 4, iclass 12, count 0 2006.173.23:52:27.45#ibcon#about to read 5, iclass 12, count 0 2006.173.23:52:27.45#ibcon#read 5, iclass 12, count 0 2006.173.23:52:27.45#ibcon#about to read 6, iclass 12, count 0 2006.173.23:52:27.45#ibcon#read 6, iclass 12, count 0 2006.173.23:52:27.45#ibcon#end of sib2, iclass 12, count 0 2006.173.23:52:27.45#ibcon#*after write, iclass 12, count 0 2006.173.23:52:27.45#ibcon#*before return 0, iclass 12, count 0 2006.173.23:52:27.45#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.23:52:27.45#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.23:52:27.45#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.23:52:27.45#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.23:52:27.45$vck44/valo=2,534.99 2006.173.23:52:27.45#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.23:52:27.45#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.23:52:27.45#ibcon#ireg 17 cls_cnt 0 2006.173.23:52:27.45#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.23:52:27.45#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.23:52:27.45#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.23:52:27.45#ibcon#enter wrdev, iclass 14, count 0 2006.173.23:52:27.45#ibcon#first serial, iclass 14, count 0 2006.173.23:52:27.45#ibcon#enter sib2, iclass 14, count 0 2006.173.23:52:27.45#ibcon#flushed, iclass 14, count 0 2006.173.23:52:27.45#ibcon#about to write, iclass 14, count 0 2006.173.23:52:27.45#ibcon#wrote, iclass 14, count 0 2006.173.23:52:27.45#ibcon#about to read 3, iclass 14, count 0 2006.173.23:52:27.47#ibcon#read 3, iclass 14, count 0 2006.173.23:52:27.47#ibcon#about to read 4, iclass 14, count 0 2006.173.23:52:27.47#ibcon#read 4, iclass 14, count 0 2006.173.23:52:27.47#ibcon#about to read 5, iclass 14, count 0 2006.173.23:52:27.47#ibcon#read 5, iclass 14, count 0 2006.173.23:52:27.47#ibcon#about to read 6, iclass 14, count 0 2006.173.23:52:27.47#ibcon#read 6, iclass 14, count 0 2006.173.23:52:27.47#ibcon#end of sib2, iclass 14, count 0 2006.173.23:52:27.47#ibcon#*mode == 0, iclass 14, count 0 2006.173.23:52:27.47#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.23:52:27.47#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.23:52:27.47#ibcon#*before write, iclass 14, count 0 2006.173.23:52:27.47#ibcon#enter sib2, iclass 14, count 0 2006.173.23:52:27.47#ibcon#flushed, iclass 14, count 0 2006.173.23:52:27.47#ibcon#about to write, iclass 14, count 0 2006.173.23:52:27.47#ibcon#wrote, iclass 14, count 0 2006.173.23:52:27.47#ibcon#about to read 3, iclass 14, count 0 2006.173.23:52:27.51#ibcon#read 3, iclass 14, count 0 2006.173.23:52:27.51#ibcon#about to read 4, iclass 14, count 0 2006.173.23:52:27.51#ibcon#read 4, iclass 14, count 0 2006.173.23:52:27.51#ibcon#about to read 5, iclass 14, count 0 2006.173.23:52:27.51#ibcon#read 5, iclass 14, count 0 2006.173.23:52:27.51#ibcon#about to read 6, iclass 14, count 0 2006.173.23:52:27.51#ibcon#read 6, iclass 14, count 0 2006.173.23:52:27.51#ibcon#end of sib2, iclass 14, count 0 2006.173.23:52:27.51#ibcon#*after write, iclass 14, count 0 2006.173.23:52:27.51#ibcon#*before return 0, iclass 14, count 0 2006.173.23:52:27.51#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.23:52:27.51#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.23:52:27.51#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.23:52:27.51#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.23:52:27.51$vck44/va=2,6 2006.173.23:52:27.51#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.23:52:27.51#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.23:52:27.51#ibcon#ireg 11 cls_cnt 2 2006.173.23:52:27.51#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.23:52:27.57#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.23:52:27.57#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.23:52:27.57#ibcon#enter wrdev, iclass 16, count 2 2006.173.23:52:27.57#ibcon#first serial, iclass 16, count 2 2006.173.23:52:27.57#ibcon#enter sib2, iclass 16, count 2 2006.173.23:52:27.57#ibcon#flushed, iclass 16, count 2 2006.173.23:52:27.57#ibcon#about to write, iclass 16, count 2 2006.173.23:52:27.57#ibcon#wrote, iclass 16, count 2 2006.173.23:52:27.57#ibcon#about to read 3, iclass 16, count 2 2006.173.23:52:27.59#ibcon#read 3, iclass 16, count 2 2006.173.23:52:27.59#ibcon#about to read 4, iclass 16, count 2 2006.173.23:52:27.59#ibcon#read 4, iclass 16, count 2 2006.173.23:52:27.59#ibcon#about to read 5, iclass 16, count 2 2006.173.23:52:27.59#ibcon#read 5, iclass 16, count 2 2006.173.23:52:27.59#ibcon#about to read 6, iclass 16, count 2 2006.173.23:52:27.59#ibcon#read 6, iclass 16, count 2 2006.173.23:52:27.59#ibcon#end of sib2, iclass 16, count 2 2006.173.23:52:27.59#ibcon#*mode == 0, iclass 16, count 2 2006.173.23:52:27.59#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.23:52:27.59#ibcon#[25=AT02-06\r\n] 2006.173.23:52:27.59#ibcon#*before write, iclass 16, count 2 2006.173.23:52:27.59#ibcon#enter sib2, iclass 16, count 2 2006.173.23:52:27.59#ibcon#flushed, iclass 16, count 2 2006.173.23:52:27.59#ibcon#about to write, iclass 16, count 2 2006.173.23:52:27.59#ibcon#wrote, iclass 16, count 2 2006.173.23:52:27.59#ibcon#about to read 3, iclass 16, count 2 2006.173.23:52:27.62#ibcon#read 3, iclass 16, count 2 2006.173.23:52:27.62#ibcon#about to read 4, iclass 16, count 2 2006.173.23:52:27.62#ibcon#read 4, iclass 16, count 2 2006.173.23:52:27.62#ibcon#about to read 5, iclass 16, count 2 2006.173.23:52:27.62#ibcon#read 5, iclass 16, count 2 2006.173.23:52:27.62#ibcon#about to read 6, iclass 16, count 2 2006.173.23:52:27.62#ibcon#read 6, iclass 16, count 2 2006.173.23:52:27.62#ibcon#end of sib2, iclass 16, count 2 2006.173.23:52:27.62#ibcon#*after write, iclass 16, count 2 2006.173.23:52:27.62#ibcon#*before return 0, iclass 16, count 2 2006.173.23:52:27.62#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.23:52:27.62#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.23:52:27.62#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.23:52:27.62#ibcon#ireg 7 cls_cnt 0 2006.173.23:52:27.62#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.23:52:27.74#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.23:52:27.74#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.23:52:27.74#ibcon#enter wrdev, iclass 16, count 0 2006.173.23:52:27.74#ibcon#first serial, iclass 16, count 0 2006.173.23:52:27.74#ibcon#enter sib2, iclass 16, count 0 2006.173.23:52:27.74#ibcon#flushed, iclass 16, count 0 2006.173.23:52:27.74#ibcon#about to write, iclass 16, count 0 2006.173.23:52:27.74#ibcon#wrote, iclass 16, count 0 2006.173.23:52:27.74#ibcon#about to read 3, iclass 16, count 0 2006.173.23:52:27.76#ibcon#read 3, iclass 16, count 0 2006.173.23:52:27.76#ibcon#about to read 4, iclass 16, count 0 2006.173.23:52:27.76#ibcon#read 4, iclass 16, count 0 2006.173.23:52:27.76#ibcon#about to read 5, iclass 16, count 0 2006.173.23:52:27.76#ibcon#read 5, iclass 16, count 0 2006.173.23:52:27.76#ibcon#about to read 6, iclass 16, count 0 2006.173.23:52:27.76#ibcon#read 6, iclass 16, count 0 2006.173.23:52:27.76#ibcon#end of sib2, iclass 16, count 0 2006.173.23:52:27.76#ibcon#*mode == 0, iclass 16, count 0 2006.173.23:52:27.76#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.23:52:27.76#ibcon#[25=USB\r\n] 2006.173.23:52:27.76#ibcon#*before write, iclass 16, count 0 2006.173.23:52:27.76#ibcon#enter sib2, iclass 16, count 0 2006.173.23:52:27.76#ibcon#flushed, iclass 16, count 0 2006.173.23:52:27.76#ibcon#about to write, iclass 16, count 0 2006.173.23:52:27.76#ibcon#wrote, iclass 16, count 0 2006.173.23:52:27.76#ibcon#about to read 3, iclass 16, count 0 2006.173.23:52:27.79#ibcon#read 3, iclass 16, count 0 2006.173.23:52:27.79#ibcon#about to read 4, iclass 16, count 0 2006.173.23:52:27.79#ibcon#read 4, iclass 16, count 0 2006.173.23:52:27.79#ibcon#about to read 5, iclass 16, count 0 2006.173.23:52:27.79#ibcon#read 5, iclass 16, count 0 2006.173.23:52:27.79#ibcon#about to read 6, iclass 16, count 0 2006.173.23:52:27.79#ibcon#read 6, iclass 16, count 0 2006.173.23:52:27.79#ibcon#end of sib2, iclass 16, count 0 2006.173.23:52:27.79#ibcon#*after write, iclass 16, count 0 2006.173.23:52:27.79#ibcon#*before return 0, iclass 16, count 0 2006.173.23:52:27.79#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.23:52:27.79#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.23:52:27.79#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.23:52:27.79#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.23:52:27.79$vck44/valo=3,564.99 2006.173.23:52:27.79#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.23:52:27.79#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.23:52:27.79#ibcon#ireg 17 cls_cnt 0 2006.173.23:52:27.79#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.23:52:27.79#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.23:52:27.79#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.23:52:27.79#ibcon#enter wrdev, iclass 18, count 0 2006.173.23:52:27.79#ibcon#first serial, iclass 18, count 0 2006.173.23:52:27.79#ibcon#enter sib2, iclass 18, count 0 2006.173.23:52:27.79#ibcon#flushed, iclass 18, count 0 2006.173.23:52:27.79#ibcon#about to write, iclass 18, count 0 2006.173.23:52:27.79#ibcon#wrote, iclass 18, count 0 2006.173.23:52:27.79#ibcon#about to read 3, iclass 18, count 0 2006.173.23:52:27.81#ibcon#read 3, iclass 18, count 0 2006.173.23:52:27.81#ibcon#about to read 4, iclass 18, count 0 2006.173.23:52:27.81#ibcon#read 4, iclass 18, count 0 2006.173.23:52:27.81#ibcon#about to read 5, iclass 18, count 0 2006.173.23:52:27.81#ibcon#read 5, iclass 18, count 0 2006.173.23:52:27.81#ibcon#about to read 6, iclass 18, count 0 2006.173.23:52:27.81#ibcon#read 6, iclass 18, count 0 2006.173.23:52:27.81#ibcon#end of sib2, iclass 18, count 0 2006.173.23:52:27.81#ibcon#*mode == 0, iclass 18, count 0 2006.173.23:52:27.81#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.23:52:27.81#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.23:52:27.81#ibcon#*before write, iclass 18, count 0 2006.173.23:52:27.81#ibcon#enter sib2, iclass 18, count 0 2006.173.23:52:27.81#ibcon#flushed, iclass 18, count 0 2006.173.23:52:27.81#ibcon#about to write, iclass 18, count 0 2006.173.23:52:27.81#ibcon#wrote, iclass 18, count 0 2006.173.23:52:27.81#ibcon#about to read 3, iclass 18, count 0 2006.173.23:52:27.85#ibcon#read 3, iclass 18, count 0 2006.173.23:52:27.85#ibcon#about to read 4, iclass 18, count 0 2006.173.23:52:27.85#ibcon#read 4, iclass 18, count 0 2006.173.23:52:27.85#ibcon#about to read 5, iclass 18, count 0 2006.173.23:52:27.85#ibcon#read 5, iclass 18, count 0 2006.173.23:52:27.85#ibcon#about to read 6, iclass 18, count 0 2006.173.23:52:27.85#ibcon#read 6, iclass 18, count 0 2006.173.23:52:27.85#ibcon#end of sib2, iclass 18, count 0 2006.173.23:52:27.85#ibcon#*after write, iclass 18, count 0 2006.173.23:52:27.85#ibcon#*before return 0, iclass 18, count 0 2006.173.23:52:27.85#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.23:52:27.85#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.23:52:27.85#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.23:52:27.85#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.23:52:27.85$vck44/va=3,5 2006.173.23:52:27.85#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.23:52:27.85#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.23:52:27.85#ibcon#ireg 11 cls_cnt 2 2006.173.23:52:27.85#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.23:52:27.91#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.23:52:27.91#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.23:52:27.91#ibcon#enter wrdev, iclass 20, count 2 2006.173.23:52:27.91#ibcon#first serial, iclass 20, count 2 2006.173.23:52:27.91#ibcon#enter sib2, iclass 20, count 2 2006.173.23:52:27.91#ibcon#flushed, iclass 20, count 2 2006.173.23:52:27.91#ibcon#about to write, iclass 20, count 2 2006.173.23:52:27.91#ibcon#wrote, iclass 20, count 2 2006.173.23:52:27.91#ibcon#about to read 3, iclass 20, count 2 2006.173.23:52:27.93#ibcon#read 3, iclass 20, count 2 2006.173.23:52:27.93#ibcon#about to read 4, iclass 20, count 2 2006.173.23:52:27.93#ibcon#read 4, iclass 20, count 2 2006.173.23:52:27.93#ibcon#about to read 5, iclass 20, count 2 2006.173.23:52:27.93#ibcon#read 5, iclass 20, count 2 2006.173.23:52:27.93#ibcon#about to read 6, iclass 20, count 2 2006.173.23:52:27.93#ibcon#read 6, iclass 20, count 2 2006.173.23:52:27.93#ibcon#end of sib2, iclass 20, count 2 2006.173.23:52:27.93#ibcon#*mode == 0, iclass 20, count 2 2006.173.23:52:27.93#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.23:52:27.93#ibcon#[25=AT03-05\r\n] 2006.173.23:52:27.93#ibcon#*before write, iclass 20, count 2 2006.173.23:52:27.93#ibcon#enter sib2, iclass 20, count 2 2006.173.23:52:27.93#ibcon#flushed, iclass 20, count 2 2006.173.23:52:27.93#ibcon#about to write, iclass 20, count 2 2006.173.23:52:27.93#ibcon#wrote, iclass 20, count 2 2006.173.23:52:27.93#ibcon#about to read 3, iclass 20, count 2 2006.173.23:52:27.96#ibcon#read 3, iclass 20, count 2 2006.173.23:52:27.96#ibcon#about to read 4, iclass 20, count 2 2006.173.23:52:27.96#ibcon#read 4, iclass 20, count 2 2006.173.23:52:27.96#ibcon#about to read 5, iclass 20, count 2 2006.173.23:52:27.96#ibcon#read 5, iclass 20, count 2 2006.173.23:52:27.96#ibcon#about to read 6, iclass 20, count 2 2006.173.23:52:27.96#ibcon#read 6, iclass 20, count 2 2006.173.23:52:27.96#ibcon#end of sib2, iclass 20, count 2 2006.173.23:52:27.96#ibcon#*after write, iclass 20, count 2 2006.173.23:52:27.96#ibcon#*before return 0, iclass 20, count 2 2006.173.23:52:27.96#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.23:52:27.96#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.23:52:27.96#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.23:52:27.96#ibcon#ireg 7 cls_cnt 0 2006.173.23:52:27.96#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.23:52:28.08#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.23:52:28.08#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.23:52:28.08#ibcon#enter wrdev, iclass 20, count 0 2006.173.23:52:28.08#ibcon#first serial, iclass 20, count 0 2006.173.23:52:28.08#ibcon#enter sib2, iclass 20, count 0 2006.173.23:52:28.08#ibcon#flushed, iclass 20, count 0 2006.173.23:52:28.08#ibcon#about to write, iclass 20, count 0 2006.173.23:52:28.08#ibcon#wrote, iclass 20, count 0 2006.173.23:52:28.08#ibcon#about to read 3, iclass 20, count 0 2006.173.23:52:28.10#ibcon#read 3, iclass 20, count 0 2006.173.23:52:28.10#ibcon#about to read 4, iclass 20, count 0 2006.173.23:52:28.10#ibcon#read 4, iclass 20, count 0 2006.173.23:52:28.10#ibcon#about to read 5, iclass 20, count 0 2006.173.23:52:28.10#ibcon#read 5, iclass 20, count 0 2006.173.23:52:28.10#ibcon#about to read 6, iclass 20, count 0 2006.173.23:52:28.10#ibcon#read 6, iclass 20, count 0 2006.173.23:52:28.10#ibcon#end of sib2, iclass 20, count 0 2006.173.23:52:28.10#ibcon#*mode == 0, iclass 20, count 0 2006.173.23:52:28.10#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.23:52:28.10#ibcon#[25=USB\r\n] 2006.173.23:52:28.10#ibcon#*before write, iclass 20, count 0 2006.173.23:52:28.10#ibcon#enter sib2, iclass 20, count 0 2006.173.23:52:28.10#ibcon#flushed, iclass 20, count 0 2006.173.23:52:28.10#ibcon#about to write, iclass 20, count 0 2006.173.23:52:28.10#ibcon#wrote, iclass 20, count 0 2006.173.23:52:28.10#ibcon#about to read 3, iclass 20, count 0 2006.173.23:52:28.13#ibcon#read 3, iclass 20, count 0 2006.173.23:52:28.13#ibcon#about to read 4, iclass 20, count 0 2006.173.23:52:28.13#ibcon#read 4, iclass 20, count 0 2006.173.23:52:28.13#ibcon#about to read 5, iclass 20, count 0 2006.173.23:52:28.13#ibcon#read 5, iclass 20, count 0 2006.173.23:52:28.13#ibcon#about to read 6, iclass 20, count 0 2006.173.23:52:28.13#ibcon#read 6, iclass 20, count 0 2006.173.23:52:28.13#ibcon#end of sib2, iclass 20, count 0 2006.173.23:52:28.13#ibcon#*after write, iclass 20, count 0 2006.173.23:52:28.13#ibcon#*before return 0, iclass 20, count 0 2006.173.23:52:28.13#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.23:52:28.13#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.23:52:28.13#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.23:52:28.13#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.23:52:28.13$vck44/valo=4,624.99 2006.173.23:52:28.13#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.23:52:28.13#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.23:52:28.13#ibcon#ireg 17 cls_cnt 0 2006.173.23:52:28.13#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.23:52:28.13#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.23:52:28.13#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.23:52:28.13#ibcon#enter wrdev, iclass 22, count 0 2006.173.23:52:28.13#ibcon#first serial, iclass 22, count 0 2006.173.23:52:28.13#ibcon#enter sib2, iclass 22, count 0 2006.173.23:52:28.13#ibcon#flushed, iclass 22, count 0 2006.173.23:52:28.13#ibcon#about to write, iclass 22, count 0 2006.173.23:52:28.13#ibcon#wrote, iclass 22, count 0 2006.173.23:52:28.13#ibcon#about to read 3, iclass 22, count 0 2006.173.23:52:28.15#ibcon#read 3, iclass 22, count 0 2006.173.23:52:28.15#ibcon#about to read 4, iclass 22, count 0 2006.173.23:52:28.15#ibcon#read 4, iclass 22, count 0 2006.173.23:52:28.15#ibcon#about to read 5, iclass 22, count 0 2006.173.23:52:28.15#ibcon#read 5, iclass 22, count 0 2006.173.23:52:28.15#ibcon#about to read 6, iclass 22, count 0 2006.173.23:52:28.15#ibcon#read 6, iclass 22, count 0 2006.173.23:52:28.15#ibcon#end of sib2, iclass 22, count 0 2006.173.23:52:28.15#ibcon#*mode == 0, iclass 22, count 0 2006.173.23:52:28.15#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.23:52:28.15#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.23:52:28.15#ibcon#*before write, iclass 22, count 0 2006.173.23:52:28.15#ibcon#enter sib2, iclass 22, count 0 2006.173.23:52:28.15#ibcon#flushed, iclass 22, count 0 2006.173.23:52:28.15#ibcon#about to write, iclass 22, count 0 2006.173.23:52:28.15#ibcon#wrote, iclass 22, count 0 2006.173.23:52:28.15#ibcon#about to read 3, iclass 22, count 0 2006.173.23:52:28.19#ibcon#read 3, iclass 22, count 0 2006.173.23:52:28.19#ibcon#about to read 4, iclass 22, count 0 2006.173.23:52:28.19#ibcon#read 4, iclass 22, count 0 2006.173.23:52:28.19#ibcon#about to read 5, iclass 22, count 0 2006.173.23:52:28.19#ibcon#read 5, iclass 22, count 0 2006.173.23:52:28.19#ibcon#about to read 6, iclass 22, count 0 2006.173.23:52:28.19#ibcon#read 6, iclass 22, count 0 2006.173.23:52:28.19#ibcon#end of sib2, iclass 22, count 0 2006.173.23:52:28.19#ibcon#*after write, iclass 22, count 0 2006.173.23:52:28.19#ibcon#*before return 0, iclass 22, count 0 2006.173.23:52:28.19#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.23:52:28.19#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.23:52:28.19#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.23:52:28.19#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.23:52:28.19$vck44/va=4,6 2006.173.23:52:28.19#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.23:52:28.19#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.23:52:28.19#ibcon#ireg 11 cls_cnt 2 2006.173.23:52:28.19#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.23:52:28.25#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.23:52:28.25#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.23:52:28.25#ibcon#enter wrdev, iclass 24, count 2 2006.173.23:52:28.25#ibcon#first serial, iclass 24, count 2 2006.173.23:52:28.25#ibcon#enter sib2, iclass 24, count 2 2006.173.23:52:28.25#ibcon#flushed, iclass 24, count 2 2006.173.23:52:28.25#ibcon#about to write, iclass 24, count 2 2006.173.23:52:28.25#ibcon#wrote, iclass 24, count 2 2006.173.23:52:28.25#ibcon#about to read 3, iclass 24, count 2 2006.173.23:52:28.27#ibcon#read 3, iclass 24, count 2 2006.173.23:52:28.27#ibcon#about to read 4, iclass 24, count 2 2006.173.23:52:28.27#ibcon#read 4, iclass 24, count 2 2006.173.23:52:28.27#ibcon#about to read 5, iclass 24, count 2 2006.173.23:52:28.27#ibcon#read 5, iclass 24, count 2 2006.173.23:52:28.27#ibcon#about to read 6, iclass 24, count 2 2006.173.23:52:28.27#ibcon#read 6, iclass 24, count 2 2006.173.23:52:28.27#ibcon#end of sib2, iclass 24, count 2 2006.173.23:52:28.27#ibcon#*mode == 0, iclass 24, count 2 2006.173.23:52:28.27#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.23:52:28.27#ibcon#[25=AT04-06\r\n] 2006.173.23:52:28.27#ibcon#*before write, iclass 24, count 2 2006.173.23:52:28.27#ibcon#enter sib2, iclass 24, count 2 2006.173.23:52:28.27#ibcon#flushed, iclass 24, count 2 2006.173.23:52:28.27#ibcon#about to write, iclass 24, count 2 2006.173.23:52:28.27#ibcon#wrote, iclass 24, count 2 2006.173.23:52:28.27#ibcon#about to read 3, iclass 24, count 2 2006.173.23:52:28.30#ibcon#read 3, iclass 24, count 2 2006.173.23:52:28.30#ibcon#about to read 4, iclass 24, count 2 2006.173.23:52:28.30#ibcon#read 4, iclass 24, count 2 2006.173.23:52:28.30#ibcon#about to read 5, iclass 24, count 2 2006.173.23:52:28.30#ibcon#read 5, iclass 24, count 2 2006.173.23:52:28.30#ibcon#about to read 6, iclass 24, count 2 2006.173.23:52:28.30#ibcon#read 6, iclass 24, count 2 2006.173.23:52:28.30#ibcon#end of sib2, iclass 24, count 2 2006.173.23:52:28.30#ibcon#*after write, iclass 24, count 2 2006.173.23:52:28.30#ibcon#*before return 0, iclass 24, count 2 2006.173.23:52:28.30#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.23:52:28.30#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.23:52:28.30#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.23:52:28.30#ibcon#ireg 7 cls_cnt 0 2006.173.23:52:28.30#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.23:52:28.42#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.23:52:28.42#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.23:52:28.42#ibcon#enter wrdev, iclass 24, count 0 2006.173.23:52:28.42#ibcon#first serial, iclass 24, count 0 2006.173.23:52:28.42#ibcon#enter sib2, iclass 24, count 0 2006.173.23:52:28.42#ibcon#flushed, iclass 24, count 0 2006.173.23:52:28.42#ibcon#about to write, iclass 24, count 0 2006.173.23:52:28.42#ibcon#wrote, iclass 24, count 0 2006.173.23:52:28.42#ibcon#about to read 3, iclass 24, count 0 2006.173.23:52:28.44#ibcon#read 3, iclass 24, count 0 2006.173.23:52:28.44#ibcon#about to read 4, iclass 24, count 0 2006.173.23:52:28.44#ibcon#read 4, iclass 24, count 0 2006.173.23:52:28.44#ibcon#about to read 5, iclass 24, count 0 2006.173.23:52:28.44#ibcon#read 5, iclass 24, count 0 2006.173.23:52:28.44#ibcon#about to read 6, iclass 24, count 0 2006.173.23:52:28.44#ibcon#read 6, iclass 24, count 0 2006.173.23:52:28.44#ibcon#end of sib2, iclass 24, count 0 2006.173.23:52:28.44#ibcon#*mode == 0, iclass 24, count 0 2006.173.23:52:28.44#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.23:52:28.44#ibcon#[25=USB\r\n] 2006.173.23:52:28.44#ibcon#*before write, iclass 24, count 0 2006.173.23:52:28.44#ibcon#enter sib2, iclass 24, count 0 2006.173.23:52:28.44#ibcon#flushed, iclass 24, count 0 2006.173.23:52:28.44#ibcon#about to write, iclass 24, count 0 2006.173.23:52:28.44#ibcon#wrote, iclass 24, count 0 2006.173.23:52:28.44#ibcon#about to read 3, iclass 24, count 0 2006.173.23:52:28.47#ibcon#read 3, iclass 24, count 0 2006.173.23:52:28.47#ibcon#about to read 4, iclass 24, count 0 2006.173.23:52:28.47#ibcon#read 4, iclass 24, count 0 2006.173.23:52:28.47#ibcon#about to read 5, iclass 24, count 0 2006.173.23:52:28.47#ibcon#read 5, iclass 24, count 0 2006.173.23:52:28.47#ibcon#about to read 6, iclass 24, count 0 2006.173.23:52:28.47#ibcon#read 6, iclass 24, count 0 2006.173.23:52:28.47#ibcon#end of sib2, iclass 24, count 0 2006.173.23:52:28.47#ibcon#*after write, iclass 24, count 0 2006.173.23:52:28.47#ibcon#*before return 0, iclass 24, count 0 2006.173.23:52:28.47#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.23:52:28.47#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.23:52:28.47#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.23:52:28.47#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.23:52:28.47$vck44/valo=5,734.99 2006.173.23:52:28.47#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.23:52:28.47#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.23:52:28.47#ibcon#ireg 17 cls_cnt 0 2006.173.23:52:28.47#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.23:52:28.47#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.23:52:28.47#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.23:52:28.47#ibcon#enter wrdev, iclass 26, count 0 2006.173.23:52:28.47#ibcon#first serial, iclass 26, count 0 2006.173.23:52:28.47#ibcon#enter sib2, iclass 26, count 0 2006.173.23:52:28.47#ibcon#flushed, iclass 26, count 0 2006.173.23:52:28.47#ibcon#about to write, iclass 26, count 0 2006.173.23:52:28.47#ibcon#wrote, iclass 26, count 0 2006.173.23:52:28.47#ibcon#about to read 3, iclass 26, count 0 2006.173.23:52:28.49#ibcon#read 3, iclass 26, count 0 2006.173.23:52:28.49#ibcon#about to read 4, iclass 26, count 0 2006.173.23:52:28.49#ibcon#read 4, iclass 26, count 0 2006.173.23:52:28.49#ibcon#about to read 5, iclass 26, count 0 2006.173.23:52:28.49#ibcon#read 5, iclass 26, count 0 2006.173.23:52:28.49#ibcon#about to read 6, iclass 26, count 0 2006.173.23:52:28.49#ibcon#read 6, iclass 26, count 0 2006.173.23:52:28.49#ibcon#end of sib2, iclass 26, count 0 2006.173.23:52:28.49#ibcon#*mode == 0, iclass 26, count 0 2006.173.23:52:28.49#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.23:52:28.49#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.23:52:28.49#ibcon#*before write, iclass 26, count 0 2006.173.23:52:28.49#ibcon#enter sib2, iclass 26, count 0 2006.173.23:52:28.49#ibcon#flushed, iclass 26, count 0 2006.173.23:52:28.49#ibcon#about to write, iclass 26, count 0 2006.173.23:52:28.49#ibcon#wrote, iclass 26, count 0 2006.173.23:52:28.49#ibcon#about to read 3, iclass 26, count 0 2006.173.23:52:28.53#ibcon#read 3, iclass 26, count 0 2006.173.23:52:28.53#ibcon#about to read 4, iclass 26, count 0 2006.173.23:52:28.53#ibcon#read 4, iclass 26, count 0 2006.173.23:52:28.53#ibcon#about to read 5, iclass 26, count 0 2006.173.23:52:28.53#ibcon#read 5, iclass 26, count 0 2006.173.23:52:28.53#ibcon#about to read 6, iclass 26, count 0 2006.173.23:52:28.53#ibcon#read 6, iclass 26, count 0 2006.173.23:52:28.53#ibcon#end of sib2, iclass 26, count 0 2006.173.23:52:28.53#ibcon#*after write, iclass 26, count 0 2006.173.23:52:28.53#ibcon#*before return 0, iclass 26, count 0 2006.173.23:52:28.53#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.23:52:28.53#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.23:52:28.53#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.23:52:28.53#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.23:52:28.53$vck44/va=5,4 2006.173.23:52:28.53#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.23:52:28.53#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.23:52:28.53#ibcon#ireg 11 cls_cnt 2 2006.173.23:52:28.53#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.23:52:28.59#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.23:52:28.59#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.23:52:28.59#ibcon#enter wrdev, iclass 28, count 2 2006.173.23:52:28.59#ibcon#first serial, iclass 28, count 2 2006.173.23:52:28.59#ibcon#enter sib2, iclass 28, count 2 2006.173.23:52:28.59#ibcon#flushed, iclass 28, count 2 2006.173.23:52:28.59#ibcon#about to write, iclass 28, count 2 2006.173.23:52:28.59#ibcon#wrote, iclass 28, count 2 2006.173.23:52:28.59#ibcon#about to read 3, iclass 28, count 2 2006.173.23:52:28.61#ibcon#read 3, iclass 28, count 2 2006.173.23:52:28.61#ibcon#about to read 4, iclass 28, count 2 2006.173.23:52:28.61#ibcon#read 4, iclass 28, count 2 2006.173.23:52:28.61#ibcon#about to read 5, iclass 28, count 2 2006.173.23:52:28.61#ibcon#read 5, iclass 28, count 2 2006.173.23:52:28.61#ibcon#about to read 6, iclass 28, count 2 2006.173.23:52:28.61#ibcon#read 6, iclass 28, count 2 2006.173.23:52:28.61#ibcon#end of sib2, iclass 28, count 2 2006.173.23:52:28.61#ibcon#*mode == 0, iclass 28, count 2 2006.173.23:52:28.61#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.23:52:28.61#ibcon#[25=AT05-04\r\n] 2006.173.23:52:28.61#ibcon#*before write, iclass 28, count 2 2006.173.23:52:28.61#ibcon#enter sib2, iclass 28, count 2 2006.173.23:52:28.61#ibcon#flushed, iclass 28, count 2 2006.173.23:52:28.61#ibcon#about to write, iclass 28, count 2 2006.173.23:52:28.61#ibcon#wrote, iclass 28, count 2 2006.173.23:52:28.61#ibcon#about to read 3, iclass 28, count 2 2006.173.23:52:28.64#ibcon#read 3, iclass 28, count 2 2006.173.23:52:28.64#ibcon#about to read 4, iclass 28, count 2 2006.173.23:52:28.64#ibcon#read 4, iclass 28, count 2 2006.173.23:52:28.64#ibcon#about to read 5, iclass 28, count 2 2006.173.23:52:28.64#ibcon#read 5, iclass 28, count 2 2006.173.23:52:28.64#ibcon#about to read 6, iclass 28, count 2 2006.173.23:52:28.64#ibcon#read 6, iclass 28, count 2 2006.173.23:52:28.64#ibcon#end of sib2, iclass 28, count 2 2006.173.23:52:28.64#ibcon#*after write, iclass 28, count 2 2006.173.23:52:28.64#ibcon#*before return 0, iclass 28, count 2 2006.173.23:52:28.64#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.23:52:28.64#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.23:52:28.64#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.23:52:28.64#ibcon#ireg 7 cls_cnt 0 2006.173.23:52:28.64#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.23:52:28.76#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.23:52:28.76#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.23:52:28.76#ibcon#enter wrdev, iclass 28, count 0 2006.173.23:52:28.76#ibcon#first serial, iclass 28, count 0 2006.173.23:52:28.76#ibcon#enter sib2, iclass 28, count 0 2006.173.23:52:28.76#ibcon#flushed, iclass 28, count 0 2006.173.23:52:28.76#ibcon#about to write, iclass 28, count 0 2006.173.23:52:28.76#ibcon#wrote, iclass 28, count 0 2006.173.23:52:28.76#ibcon#about to read 3, iclass 28, count 0 2006.173.23:52:28.78#ibcon#read 3, iclass 28, count 0 2006.173.23:52:28.78#ibcon#about to read 4, iclass 28, count 0 2006.173.23:52:28.78#ibcon#read 4, iclass 28, count 0 2006.173.23:52:28.78#ibcon#about to read 5, iclass 28, count 0 2006.173.23:52:28.78#ibcon#read 5, iclass 28, count 0 2006.173.23:52:28.78#ibcon#about to read 6, iclass 28, count 0 2006.173.23:52:28.78#ibcon#read 6, iclass 28, count 0 2006.173.23:52:28.78#ibcon#end of sib2, iclass 28, count 0 2006.173.23:52:28.78#ibcon#*mode == 0, iclass 28, count 0 2006.173.23:52:28.78#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.23:52:28.78#ibcon#[25=USB\r\n] 2006.173.23:52:28.78#ibcon#*before write, iclass 28, count 0 2006.173.23:52:28.78#ibcon#enter sib2, iclass 28, count 0 2006.173.23:52:28.78#ibcon#flushed, iclass 28, count 0 2006.173.23:52:28.78#ibcon#about to write, iclass 28, count 0 2006.173.23:52:28.78#ibcon#wrote, iclass 28, count 0 2006.173.23:52:28.78#ibcon#about to read 3, iclass 28, count 0 2006.173.23:52:28.81#ibcon#read 3, iclass 28, count 0 2006.173.23:52:28.81#ibcon#about to read 4, iclass 28, count 0 2006.173.23:52:28.81#ibcon#read 4, iclass 28, count 0 2006.173.23:52:28.81#ibcon#about to read 5, iclass 28, count 0 2006.173.23:52:28.81#ibcon#read 5, iclass 28, count 0 2006.173.23:52:28.81#ibcon#about to read 6, iclass 28, count 0 2006.173.23:52:28.81#ibcon#read 6, iclass 28, count 0 2006.173.23:52:28.81#ibcon#end of sib2, iclass 28, count 0 2006.173.23:52:28.81#ibcon#*after write, iclass 28, count 0 2006.173.23:52:28.81#ibcon#*before return 0, iclass 28, count 0 2006.173.23:52:28.81#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.23:52:28.81#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.23:52:28.81#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.23:52:28.81#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.23:52:28.81$vck44/valo=6,814.99 2006.173.23:52:28.81#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.23:52:28.81#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.23:52:28.81#ibcon#ireg 17 cls_cnt 0 2006.173.23:52:28.81#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.23:52:28.81#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.23:52:28.81#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.23:52:28.81#ibcon#enter wrdev, iclass 30, count 0 2006.173.23:52:28.81#ibcon#first serial, iclass 30, count 0 2006.173.23:52:28.81#ibcon#enter sib2, iclass 30, count 0 2006.173.23:52:28.81#ibcon#flushed, iclass 30, count 0 2006.173.23:52:28.81#ibcon#about to write, iclass 30, count 0 2006.173.23:52:28.81#ibcon#wrote, iclass 30, count 0 2006.173.23:52:28.81#ibcon#about to read 3, iclass 30, count 0 2006.173.23:52:28.83#ibcon#read 3, iclass 30, count 0 2006.173.23:52:28.83#ibcon#about to read 4, iclass 30, count 0 2006.173.23:52:28.83#ibcon#read 4, iclass 30, count 0 2006.173.23:52:28.83#ibcon#about to read 5, iclass 30, count 0 2006.173.23:52:28.83#ibcon#read 5, iclass 30, count 0 2006.173.23:52:28.83#ibcon#about to read 6, iclass 30, count 0 2006.173.23:52:28.83#ibcon#read 6, iclass 30, count 0 2006.173.23:52:28.83#ibcon#end of sib2, iclass 30, count 0 2006.173.23:52:28.83#ibcon#*mode == 0, iclass 30, count 0 2006.173.23:52:28.83#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.23:52:28.83#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.23:52:28.83#ibcon#*before write, iclass 30, count 0 2006.173.23:52:28.83#ibcon#enter sib2, iclass 30, count 0 2006.173.23:52:28.83#ibcon#flushed, iclass 30, count 0 2006.173.23:52:28.83#ibcon#about to write, iclass 30, count 0 2006.173.23:52:28.83#ibcon#wrote, iclass 30, count 0 2006.173.23:52:28.83#ibcon#about to read 3, iclass 30, count 0 2006.173.23:52:28.87#ibcon#read 3, iclass 30, count 0 2006.173.23:52:28.87#ibcon#about to read 4, iclass 30, count 0 2006.173.23:52:28.87#ibcon#read 4, iclass 30, count 0 2006.173.23:52:28.87#ibcon#about to read 5, iclass 30, count 0 2006.173.23:52:28.87#ibcon#read 5, iclass 30, count 0 2006.173.23:52:28.87#ibcon#about to read 6, iclass 30, count 0 2006.173.23:52:28.87#ibcon#read 6, iclass 30, count 0 2006.173.23:52:28.87#ibcon#end of sib2, iclass 30, count 0 2006.173.23:52:28.87#ibcon#*after write, iclass 30, count 0 2006.173.23:52:28.87#ibcon#*before return 0, iclass 30, count 0 2006.173.23:52:28.87#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.23:52:28.87#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.23:52:28.87#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.23:52:28.87#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.23:52:28.87$vck44/va=6,3 2006.173.23:52:28.87#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.173.23:52:28.87#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.173.23:52:28.87#ibcon#ireg 11 cls_cnt 2 2006.173.23:52:28.87#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.23:52:28.93#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.23:52:28.93#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.23:52:28.93#ibcon#enter wrdev, iclass 32, count 2 2006.173.23:52:28.93#ibcon#first serial, iclass 32, count 2 2006.173.23:52:28.93#ibcon#enter sib2, iclass 32, count 2 2006.173.23:52:28.93#ibcon#flushed, iclass 32, count 2 2006.173.23:52:28.93#ibcon#about to write, iclass 32, count 2 2006.173.23:52:28.93#ibcon#wrote, iclass 32, count 2 2006.173.23:52:28.93#ibcon#about to read 3, iclass 32, count 2 2006.173.23:52:28.95#ibcon#read 3, iclass 32, count 2 2006.173.23:52:28.95#ibcon#about to read 4, iclass 32, count 2 2006.173.23:52:28.95#ibcon#read 4, iclass 32, count 2 2006.173.23:52:28.95#ibcon#about to read 5, iclass 32, count 2 2006.173.23:52:28.95#ibcon#read 5, iclass 32, count 2 2006.173.23:52:28.95#ibcon#about to read 6, iclass 32, count 2 2006.173.23:52:28.95#ibcon#read 6, iclass 32, count 2 2006.173.23:52:28.95#ibcon#end of sib2, iclass 32, count 2 2006.173.23:52:28.95#ibcon#*mode == 0, iclass 32, count 2 2006.173.23:52:28.95#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.173.23:52:28.95#ibcon#[25=AT06-03\r\n] 2006.173.23:52:28.95#ibcon#*before write, iclass 32, count 2 2006.173.23:52:28.95#ibcon#enter sib2, iclass 32, count 2 2006.173.23:52:28.95#ibcon#flushed, iclass 32, count 2 2006.173.23:52:28.95#ibcon#about to write, iclass 32, count 2 2006.173.23:52:28.95#ibcon#wrote, iclass 32, count 2 2006.173.23:52:28.95#ibcon#about to read 3, iclass 32, count 2 2006.173.23:52:28.98#ibcon#read 3, iclass 32, count 2 2006.173.23:52:28.98#ibcon#about to read 4, iclass 32, count 2 2006.173.23:52:28.98#ibcon#read 4, iclass 32, count 2 2006.173.23:52:28.98#ibcon#about to read 5, iclass 32, count 2 2006.173.23:52:28.98#ibcon#read 5, iclass 32, count 2 2006.173.23:52:28.98#ibcon#about to read 6, iclass 32, count 2 2006.173.23:52:28.98#ibcon#read 6, iclass 32, count 2 2006.173.23:52:28.98#ibcon#end of sib2, iclass 32, count 2 2006.173.23:52:28.98#ibcon#*after write, iclass 32, count 2 2006.173.23:52:28.98#ibcon#*before return 0, iclass 32, count 2 2006.173.23:52:28.98#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.23:52:28.98#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.173.23:52:28.98#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.173.23:52:28.98#ibcon#ireg 7 cls_cnt 0 2006.173.23:52:28.98#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.23:52:29.10#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.23:52:29.10#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.23:52:29.10#ibcon#enter wrdev, iclass 32, count 0 2006.173.23:52:29.10#ibcon#first serial, iclass 32, count 0 2006.173.23:52:29.10#ibcon#enter sib2, iclass 32, count 0 2006.173.23:52:29.10#ibcon#flushed, iclass 32, count 0 2006.173.23:52:29.10#ibcon#about to write, iclass 32, count 0 2006.173.23:52:29.10#ibcon#wrote, iclass 32, count 0 2006.173.23:52:29.10#ibcon#about to read 3, iclass 32, count 0 2006.173.23:52:29.12#ibcon#read 3, iclass 32, count 0 2006.173.23:52:29.12#ibcon#about to read 4, iclass 32, count 0 2006.173.23:52:29.12#ibcon#read 4, iclass 32, count 0 2006.173.23:52:29.12#ibcon#about to read 5, iclass 32, count 0 2006.173.23:52:29.12#ibcon#read 5, iclass 32, count 0 2006.173.23:52:29.12#ibcon#about to read 6, iclass 32, count 0 2006.173.23:52:29.12#ibcon#read 6, iclass 32, count 0 2006.173.23:52:29.12#ibcon#end of sib2, iclass 32, count 0 2006.173.23:52:29.12#ibcon#*mode == 0, iclass 32, count 0 2006.173.23:52:29.12#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.23:52:29.12#ibcon#[25=USB\r\n] 2006.173.23:52:29.12#ibcon#*before write, iclass 32, count 0 2006.173.23:52:29.12#ibcon#enter sib2, iclass 32, count 0 2006.173.23:52:29.12#ibcon#flushed, iclass 32, count 0 2006.173.23:52:29.12#ibcon#about to write, iclass 32, count 0 2006.173.23:52:29.12#ibcon#wrote, iclass 32, count 0 2006.173.23:52:29.12#ibcon#about to read 3, iclass 32, count 0 2006.173.23:52:29.15#ibcon#read 3, iclass 32, count 0 2006.173.23:52:29.15#ibcon#about to read 4, iclass 32, count 0 2006.173.23:52:29.15#ibcon#read 4, iclass 32, count 0 2006.173.23:52:29.15#ibcon#about to read 5, iclass 32, count 0 2006.173.23:52:29.15#ibcon#read 5, iclass 32, count 0 2006.173.23:52:29.15#ibcon#about to read 6, iclass 32, count 0 2006.173.23:52:29.15#ibcon#read 6, iclass 32, count 0 2006.173.23:52:29.15#ibcon#end of sib2, iclass 32, count 0 2006.173.23:52:29.15#ibcon#*after write, iclass 32, count 0 2006.173.23:52:29.15#ibcon#*before return 0, iclass 32, count 0 2006.173.23:52:29.15#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.23:52:29.15#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.173.23:52:29.15#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.23:52:29.15#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.23:52:29.15$vck44/valo=7,864.99 2006.173.23:52:29.15#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.23:52:29.15#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.23:52:29.15#ibcon#ireg 17 cls_cnt 0 2006.173.23:52:29.15#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.23:52:29.15#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.23:52:29.15#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.23:52:29.15#ibcon#enter wrdev, iclass 34, count 0 2006.173.23:52:29.15#ibcon#first serial, iclass 34, count 0 2006.173.23:52:29.15#ibcon#enter sib2, iclass 34, count 0 2006.173.23:52:29.15#ibcon#flushed, iclass 34, count 0 2006.173.23:52:29.15#ibcon#about to write, iclass 34, count 0 2006.173.23:52:29.15#ibcon#wrote, iclass 34, count 0 2006.173.23:52:29.15#ibcon#about to read 3, iclass 34, count 0 2006.173.23:52:29.17#ibcon#read 3, iclass 34, count 0 2006.173.23:52:29.17#ibcon#about to read 4, iclass 34, count 0 2006.173.23:52:29.17#ibcon#read 4, iclass 34, count 0 2006.173.23:52:29.17#ibcon#about to read 5, iclass 34, count 0 2006.173.23:52:29.17#ibcon#read 5, iclass 34, count 0 2006.173.23:52:29.17#ibcon#about to read 6, iclass 34, count 0 2006.173.23:52:29.17#ibcon#read 6, iclass 34, count 0 2006.173.23:52:29.17#ibcon#end of sib2, iclass 34, count 0 2006.173.23:52:29.17#ibcon#*mode == 0, iclass 34, count 0 2006.173.23:52:29.17#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.23:52:29.17#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.23:52:29.17#ibcon#*before write, iclass 34, count 0 2006.173.23:52:29.17#ibcon#enter sib2, iclass 34, count 0 2006.173.23:52:29.17#ibcon#flushed, iclass 34, count 0 2006.173.23:52:29.17#ibcon#about to write, iclass 34, count 0 2006.173.23:52:29.17#ibcon#wrote, iclass 34, count 0 2006.173.23:52:29.17#ibcon#about to read 3, iclass 34, count 0 2006.173.23:52:29.21#ibcon#read 3, iclass 34, count 0 2006.173.23:52:29.21#ibcon#about to read 4, iclass 34, count 0 2006.173.23:52:29.21#ibcon#read 4, iclass 34, count 0 2006.173.23:52:29.21#ibcon#about to read 5, iclass 34, count 0 2006.173.23:52:29.21#ibcon#read 5, iclass 34, count 0 2006.173.23:52:29.21#ibcon#about to read 6, iclass 34, count 0 2006.173.23:52:29.21#ibcon#read 6, iclass 34, count 0 2006.173.23:52:29.21#ibcon#end of sib2, iclass 34, count 0 2006.173.23:52:29.21#ibcon#*after write, iclass 34, count 0 2006.173.23:52:29.21#ibcon#*before return 0, iclass 34, count 0 2006.173.23:52:29.21#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.23:52:29.21#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.23:52:29.21#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.23:52:29.21#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.23:52:29.21$vck44/va=7,4 2006.173.23:52:29.21#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.23:52:29.21#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.23:52:29.21#ibcon#ireg 11 cls_cnt 2 2006.173.23:52:29.21#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.23:52:29.27#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.23:52:29.27#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.23:52:29.27#ibcon#enter wrdev, iclass 36, count 2 2006.173.23:52:29.27#ibcon#first serial, iclass 36, count 2 2006.173.23:52:29.27#ibcon#enter sib2, iclass 36, count 2 2006.173.23:52:29.27#ibcon#flushed, iclass 36, count 2 2006.173.23:52:29.27#ibcon#about to write, iclass 36, count 2 2006.173.23:52:29.27#ibcon#wrote, iclass 36, count 2 2006.173.23:52:29.27#ibcon#about to read 3, iclass 36, count 2 2006.173.23:52:29.29#ibcon#read 3, iclass 36, count 2 2006.173.23:52:29.29#ibcon#about to read 4, iclass 36, count 2 2006.173.23:52:29.29#ibcon#read 4, iclass 36, count 2 2006.173.23:52:29.29#ibcon#about to read 5, iclass 36, count 2 2006.173.23:52:29.29#ibcon#read 5, iclass 36, count 2 2006.173.23:52:29.29#ibcon#about to read 6, iclass 36, count 2 2006.173.23:52:29.29#ibcon#read 6, iclass 36, count 2 2006.173.23:52:29.29#ibcon#end of sib2, iclass 36, count 2 2006.173.23:52:29.29#ibcon#*mode == 0, iclass 36, count 2 2006.173.23:52:29.29#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.23:52:29.29#ibcon#[25=AT07-04\r\n] 2006.173.23:52:29.29#ibcon#*before write, iclass 36, count 2 2006.173.23:52:29.29#ibcon#enter sib2, iclass 36, count 2 2006.173.23:52:29.29#ibcon#flushed, iclass 36, count 2 2006.173.23:52:29.29#ibcon#about to write, iclass 36, count 2 2006.173.23:52:29.29#ibcon#wrote, iclass 36, count 2 2006.173.23:52:29.29#ibcon#about to read 3, iclass 36, count 2 2006.173.23:52:29.32#ibcon#read 3, iclass 36, count 2 2006.173.23:52:29.32#ibcon#about to read 4, iclass 36, count 2 2006.173.23:52:29.32#ibcon#read 4, iclass 36, count 2 2006.173.23:52:29.32#ibcon#about to read 5, iclass 36, count 2 2006.173.23:52:29.32#ibcon#read 5, iclass 36, count 2 2006.173.23:52:29.32#ibcon#about to read 6, iclass 36, count 2 2006.173.23:52:29.32#ibcon#read 6, iclass 36, count 2 2006.173.23:52:29.32#ibcon#end of sib2, iclass 36, count 2 2006.173.23:52:29.32#ibcon#*after write, iclass 36, count 2 2006.173.23:52:29.32#ibcon#*before return 0, iclass 36, count 2 2006.173.23:52:29.32#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.23:52:29.32#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.23:52:29.32#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.23:52:29.32#ibcon#ireg 7 cls_cnt 0 2006.173.23:52:29.32#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.23:52:29.44#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.23:52:29.44#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.23:52:29.44#ibcon#enter wrdev, iclass 36, count 0 2006.173.23:52:29.44#ibcon#first serial, iclass 36, count 0 2006.173.23:52:29.44#ibcon#enter sib2, iclass 36, count 0 2006.173.23:52:29.44#ibcon#flushed, iclass 36, count 0 2006.173.23:52:29.44#ibcon#about to write, iclass 36, count 0 2006.173.23:52:29.44#ibcon#wrote, iclass 36, count 0 2006.173.23:52:29.44#ibcon#about to read 3, iclass 36, count 0 2006.173.23:52:29.46#ibcon#read 3, iclass 36, count 0 2006.173.23:52:29.46#ibcon#about to read 4, iclass 36, count 0 2006.173.23:52:29.46#ibcon#read 4, iclass 36, count 0 2006.173.23:52:29.46#ibcon#about to read 5, iclass 36, count 0 2006.173.23:52:29.46#ibcon#read 5, iclass 36, count 0 2006.173.23:52:29.46#ibcon#about to read 6, iclass 36, count 0 2006.173.23:52:29.46#ibcon#read 6, iclass 36, count 0 2006.173.23:52:29.46#ibcon#end of sib2, iclass 36, count 0 2006.173.23:52:29.46#ibcon#*mode == 0, iclass 36, count 0 2006.173.23:52:29.46#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.23:52:29.46#ibcon#[25=USB\r\n] 2006.173.23:52:29.46#ibcon#*before write, iclass 36, count 0 2006.173.23:52:29.46#ibcon#enter sib2, iclass 36, count 0 2006.173.23:52:29.46#ibcon#flushed, iclass 36, count 0 2006.173.23:52:29.46#ibcon#about to write, iclass 36, count 0 2006.173.23:52:29.46#ibcon#wrote, iclass 36, count 0 2006.173.23:52:29.46#ibcon#about to read 3, iclass 36, count 0 2006.173.23:52:29.49#ibcon#read 3, iclass 36, count 0 2006.173.23:52:29.49#ibcon#about to read 4, iclass 36, count 0 2006.173.23:52:29.49#ibcon#read 4, iclass 36, count 0 2006.173.23:52:29.49#ibcon#about to read 5, iclass 36, count 0 2006.173.23:52:29.49#ibcon#read 5, iclass 36, count 0 2006.173.23:52:29.49#ibcon#about to read 6, iclass 36, count 0 2006.173.23:52:29.49#ibcon#read 6, iclass 36, count 0 2006.173.23:52:29.49#ibcon#end of sib2, iclass 36, count 0 2006.173.23:52:29.49#ibcon#*after write, iclass 36, count 0 2006.173.23:52:29.49#ibcon#*before return 0, iclass 36, count 0 2006.173.23:52:29.49#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.23:52:29.49#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.23:52:29.49#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.23:52:29.49#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.23:52:29.49$vck44/valo=8,884.99 2006.173.23:52:29.49#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.23:52:29.49#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.23:52:29.49#ibcon#ireg 17 cls_cnt 0 2006.173.23:52:29.49#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.23:52:29.49#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.23:52:29.49#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.23:52:29.49#ibcon#enter wrdev, iclass 38, count 0 2006.173.23:52:29.49#ibcon#first serial, iclass 38, count 0 2006.173.23:52:29.49#ibcon#enter sib2, iclass 38, count 0 2006.173.23:52:29.49#ibcon#flushed, iclass 38, count 0 2006.173.23:52:29.49#ibcon#about to write, iclass 38, count 0 2006.173.23:52:29.49#ibcon#wrote, iclass 38, count 0 2006.173.23:52:29.49#ibcon#about to read 3, iclass 38, count 0 2006.173.23:52:29.51#ibcon#read 3, iclass 38, count 0 2006.173.23:52:29.51#ibcon#about to read 4, iclass 38, count 0 2006.173.23:52:29.51#ibcon#read 4, iclass 38, count 0 2006.173.23:52:29.51#ibcon#about to read 5, iclass 38, count 0 2006.173.23:52:29.51#ibcon#read 5, iclass 38, count 0 2006.173.23:52:29.51#ibcon#about to read 6, iclass 38, count 0 2006.173.23:52:29.51#ibcon#read 6, iclass 38, count 0 2006.173.23:52:29.51#ibcon#end of sib2, iclass 38, count 0 2006.173.23:52:29.51#ibcon#*mode == 0, iclass 38, count 0 2006.173.23:52:29.51#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.23:52:29.51#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.23:52:29.51#ibcon#*before write, iclass 38, count 0 2006.173.23:52:29.51#ibcon#enter sib2, iclass 38, count 0 2006.173.23:52:29.51#ibcon#flushed, iclass 38, count 0 2006.173.23:52:29.51#ibcon#about to write, iclass 38, count 0 2006.173.23:52:29.51#ibcon#wrote, iclass 38, count 0 2006.173.23:52:29.51#ibcon#about to read 3, iclass 38, count 0 2006.173.23:52:29.55#ibcon#read 3, iclass 38, count 0 2006.173.23:52:29.55#ibcon#about to read 4, iclass 38, count 0 2006.173.23:52:29.55#ibcon#read 4, iclass 38, count 0 2006.173.23:52:29.55#ibcon#about to read 5, iclass 38, count 0 2006.173.23:52:29.55#ibcon#read 5, iclass 38, count 0 2006.173.23:52:29.55#ibcon#about to read 6, iclass 38, count 0 2006.173.23:52:29.55#ibcon#read 6, iclass 38, count 0 2006.173.23:52:29.55#ibcon#end of sib2, iclass 38, count 0 2006.173.23:52:29.55#ibcon#*after write, iclass 38, count 0 2006.173.23:52:29.55#ibcon#*before return 0, iclass 38, count 0 2006.173.23:52:29.55#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.23:52:29.55#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.23:52:29.55#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.23:52:29.55#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.23:52:29.55$vck44/va=8,4 2006.173.23:52:29.55#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.173.23:52:29.55#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.173.23:52:29.55#ibcon#ireg 11 cls_cnt 2 2006.173.23:52:29.55#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.23:52:29.61#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.173.23:52:29.61#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.23:52:29.61#ibcon#enter wrdev, iclass 40, count 2 2006.173.23:52:29.61#ibcon#first serial, iclass 40, count 2 2006.173.23:52:29.61#ibcon#enter sib2, iclass 40, count 2 2006.173.23:52:29.61#ibcon#flushed, iclass 40, count 2 2006.173.23:52:29.61#ibcon#about to write, iclass 40, count 2 2006.173.23:52:29.61#ibcon#wrote, iclass 40, count 2 2006.173.23:52:29.61#ibcon#about to read 3, iclass 40, count 2 2006.173.23:52:29.63#ibcon#read 3, iclass 40, count 2 2006.173.23:52:29.63#ibcon#about to read 4, iclass 40, count 2 2006.173.23:52:29.63#ibcon#read 4, iclass 40, count 2 2006.173.23:52:29.63#ibcon#about to read 5, iclass 40, count 2 2006.173.23:52:29.63#ibcon#read 5, iclass 40, count 2 2006.173.23:52:29.63#ibcon#about to read 6, iclass 40, count 2 2006.173.23:52:29.63#ibcon#read 6, iclass 40, count 2 2006.173.23:52:29.63#ibcon#end of sib2, iclass 40, count 2 2006.173.23:52:29.63#ibcon#*mode == 0, iclass 40, count 2 2006.173.23:52:29.63#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.173.23:52:29.63#ibcon#[25=AT08-04\r\n] 2006.173.23:52:29.63#ibcon#*before write, iclass 40, count 2 2006.173.23:52:29.63#ibcon#enter sib2, iclass 40, count 2 2006.173.23:52:29.63#ibcon#flushed, iclass 40, count 2 2006.173.23:52:29.63#ibcon#about to write, iclass 40, count 2 2006.173.23:52:29.63#ibcon#wrote, iclass 40, count 2 2006.173.23:52:29.63#ibcon#about to read 3, iclass 40, count 2 2006.173.23:52:29.66#ibcon#read 3, iclass 40, count 2 2006.173.23:52:29.66#ibcon#about to read 4, iclass 40, count 2 2006.173.23:52:29.66#ibcon#read 4, iclass 40, count 2 2006.173.23:52:29.66#ibcon#about to read 5, iclass 40, count 2 2006.173.23:52:29.66#ibcon#read 5, iclass 40, count 2 2006.173.23:52:29.66#ibcon#about to read 6, iclass 40, count 2 2006.173.23:52:29.66#ibcon#read 6, iclass 40, count 2 2006.173.23:52:29.66#ibcon#end of sib2, iclass 40, count 2 2006.173.23:52:29.66#ibcon#*after write, iclass 40, count 2 2006.173.23:52:29.66#ibcon#*before return 0, iclass 40, count 2 2006.173.23:52:29.66#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.173.23:52:29.66#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.173.23:52:29.66#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.173.23:52:29.66#ibcon#ireg 7 cls_cnt 0 2006.173.23:52:29.66#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.23:52:29.78#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.173.23:52:29.78#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.23:52:29.78#ibcon#enter wrdev, iclass 40, count 0 2006.173.23:52:29.78#ibcon#first serial, iclass 40, count 0 2006.173.23:52:29.78#ibcon#enter sib2, iclass 40, count 0 2006.173.23:52:29.78#ibcon#flushed, iclass 40, count 0 2006.173.23:52:29.78#ibcon#about to write, iclass 40, count 0 2006.173.23:52:29.78#ibcon#wrote, iclass 40, count 0 2006.173.23:52:29.78#ibcon#about to read 3, iclass 40, count 0 2006.173.23:52:29.80#ibcon#read 3, iclass 40, count 0 2006.173.23:52:29.80#ibcon#about to read 4, iclass 40, count 0 2006.173.23:52:29.80#ibcon#read 4, iclass 40, count 0 2006.173.23:52:29.80#ibcon#about to read 5, iclass 40, count 0 2006.173.23:52:29.80#ibcon#read 5, iclass 40, count 0 2006.173.23:52:29.80#ibcon#about to read 6, iclass 40, count 0 2006.173.23:52:29.80#ibcon#read 6, iclass 40, count 0 2006.173.23:52:29.80#ibcon#end of sib2, iclass 40, count 0 2006.173.23:52:29.80#ibcon#*mode == 0, iclass 40, count 0 2006.173.23:52:29.80#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.23:52:29.80#ibcon#[25=USB\r\n] 2006.173.23:52:29.80#ibcon#*before write, iclass 40, count 0 2006.173.23:52:29.80#ibcon#enter sib2, iclass 40, count 0 2006.173.23:52:29.80#ibcon#flushed, iclass 40, count 0 2006.173.23:52:29.80#ibcon#about to write, iclass 40, count 0 2006.173.23:52:29.80#ibcon#wrote, iclass 40, count 0 2006.173.23:52:29.80#ibcon#about to read 3, iclass 40, count 0 2006.173.23:52:29.83#ibcon#read 3, iclass 40, count 0 2006.173.23:52:29.83#ibcon#about to read 4, iclass 40, count 0 2006.173.23:52:29.83#ibcon#read 4, iclass 40, count 0 2006.173.23:52:29.83#ibcon#about to read 5, iclass 40, count 0 2006.173.23:52:29.83#ibcon#read 5, iclass 40, count 0 2006.173.23:52:29.83#ibcon#about to read 6, iclass 40, count 0 2006.173.23:52:29.83#ibcon#read 6, iclass 40, count 0 2006.173.23:52:29.83#ibcon#end of sib2, iclass 40, count 0 2006.173.23:52:29.83#ibcon#*after write, iclass 40, count 0 2006.173.23:52:29.83#ibcon#*before return 0, iclass 40, count 0 2006.173.23:52:29.83#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.173.23:52:29.83#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.173.23:52:29.83#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.23:52:29.83#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.23:52:29.83$vck44/vblo=1,629.99 2006.173.23:52:29.83#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.173.23:52:29.83#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.173.23:52:29.83#ibcon#ireg 17 cls_cnt 0 2006.173.23:52:29.83#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.23:52:29.83#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.173.23:52:29.83#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.23:52:29.83#ibcon#enter wrdev, iclass 4, count 0 2006.173.23:52:29.83#ibcon#first serial, iclass 4, count 0 2006.173.23:52:29.83#ibcon#enter sib2, iclass 4, count 0 2006.173.23:52:29.83#ibcon#flushed, iclass 4, count 0 2006.173.23:52:29.83#ibcon#about to write, iclass 4, count 0 2006.173.23:52:29.83#ibcon#wrote, iclass 4, count 0 2006.173.23:52:29.83#ibcon#about to read 3, iclass 4, count 0 2006.173.23:52:29.85#ibcon#read 3, iclass 4, count 0 2006.173.23:52:29.85#ibcon#about to read 4, iclass 4, count 0 2006.173.23:52:29.85#ibcon#read 4, iclass 4, count 0 2006.173.23:52:29.85#ibcon#about to read 5, iclass 4, count 0 2006.173.23:52:29.85#ibcon#read 5, iclass 4, count 0 2006.173.23:52:29.85#ibcon#about to read 6, iclass 4, count 0 2006.173.23:52:29.85#ibcon#read 6, iclass 4, count 0 2006.173.23:52:29.85#ibcon#end of sib2, iclass 4, count 0 2006.173.23:52:29.85#ibcon#*mode == 0, iclass 4, count 0 2006.173.23:52:29.85#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.173.23:52:29.85#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.23:52:29.85#ibcon#*before write, iclass 4, count 0 2006.173.23:52:29.85#ibcon#enter sib2, iclass 4, count 0 2006.173.23:52:29.85#ibcon#flushed, iclass 4, count 0 2006.173.23:52:29.85#ibcon#about to write, iclass 4, count 0 2006.173.23:52:29.85#ibcon#wrote, iclass 4, count 0 2006.173.23:52:29.85#ibcon#about to read 3, iclass 4, count 0 2006.173.23:52:29.89#ibcon#read 3, iclass 4, count 0 2006.173.23:52:29.89#ibcon#about to read 4, iclass 4, count 0 2006.173.23:52:29.89#ibcon#read 4, iclass 4, count 0 2006.173.23:52:29.89#ibcon#about to read 5, iclass 4, count 0 2006.173.23:52:29.89#ibcon#read 5, iclass 4, count 0 2006.173.23:52:29.89#ibcon#about to read 6, iclass 4, count 0 2006.173.23:52:29.89#ibcon#read 6, iclass 4, count 0 2006.173.23:52:29.89#ibcon#end of sib2, iclass 4, count 0 2006.173.23:52:29.89#ibcon#*after write, iclass 4, count 0 2006.173.23:52:29.89#ibcon#*before return 0, iclass 4, count 0 2006.173.23:52:29.89#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.173.23:52:29.89#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.173.23:52:29.89#ibcon#about to clear, iclass 4 cls_cnt 0 2006.173.23:52:29.89#ibcon#cleared, iclass 4 cls_cnt 0 2006.173.23:52:29.89$vck44/vb=1,4 2006.173.23:52:29.89#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.173.23:52:29.89#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.173.23:52:29.89#ibcon#ireg 11 cls_cnt 2 2006.173.23:52:29.89#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.23:52:29.89#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.173.23:52:29.89#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.23:52:29.89#ibcon#enter wrdev, iclass 6, count 2 2006.173.23:52:29.89#ibcon#first serial, iclass 6, count 2 2006.173.23:52:29.89#ibcon#enter sib2, iclass 6, count 2 2006.173.23:52:29.89#ibcon#flushed, iclass 6, count 2 2006.173.23:52:29.89#ibcon#about to write, iclass 6, count 2 2006.173.23:52:29.89#ibcon#wrote, iclass 6, count 2 2006.173.23:52:29.89#ibcon#about to read 3, iclass 6, count 2 2006.173.23:52:29.91#ibcon#read 3, iclass 6, count 2 2006.173.23:52:29.91#ibcon#about to read 4, iclass 6, count 2 2006.173.23:52:29.91#ibcon#read 4, iclass 6, count 2 2006.173.23:52:29.91#ibcon#about to read 5, iclass 6, count 2 2006.173.23:52:29.91#ibcon#read 5, iclass 6, count 2 2006.173.23:52:29.91#ibcon#about to read 6, iclass 6, count 2 2006.173.23:52:29.91#ibcon#read 6, iclass 6, count 2 2006.173.23:52:29.91#ibcon#end of sib2, iclass 6, count 2 2006.173.23:52:29.91#ibcon#*mode == 0, iclass 6, count 2 2006.173.23:52:29.91#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.173.23:52:29.91#ibcon#[27=AT01-04\r\n] 2006.173.23:52:29.91#ibcon#*before write, iclass 6, count 2 2006.173.23:52:29.91#ibcon#enter sib2, iclass 6, count 2 2006.173.23:52:29.91#ibcon#flushed, iclass 6, count 2 2006.173.23:52:29.91#ibcon#about to write, iclass 6, count 2 2006.173.23:52:29.91#ibcon#wrote, iclass 6, count 2 2006.173.23:52:29.91#ibcon#about to read 3, iclass 6, count 2 2006.173.23:52:29.94#ibcon#read 3, iclass 6, count 2 2006.173.23:52:29.94#ibcon#about to read 4, iclass 6, count 2 2006.173.23:52:29.94#ibcon#read 4, iclass 6, count 2 2006.173.23:52:29.94#ibcon#about to read 5, iclass 6, count 2 2006.173.23:52:29.94#ibcon#read 5, iclass 6, count 2 2006.173.23:52:29.94#ibcon#about to read 6, iclass 6, count 2 2006.173.23:52:29.94#ibcon#read 6, iclass 6, count 2 2006.173.23:52:29.94#ibcon#end of sib2, iclass 6, count 2 2006.173.23:52:29.94#ibcon#*after write, iclass 6, count 2 2006.173.23:52:29.94#ibcon#*before return 0, iclass 6, count 2 2006.173.23:52:29.94#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.173.23:52:29.94#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.173.23:52:29.94#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.173.23:52:29.94#ibcon#ireg 7 cls_cnt 0 2006.173.23:52:29.94#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.23:52:30.06#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.173.23:52:30.06#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.23:52:30.06#ibcon#enter wrdev, iclass 6, count 0 2006.173.23:52:30.06#ibcon#first serial, iclass 6, count 0 2006.173.23:52:30.06#ibcon#enter sib2, iclass 6, count 0 2006.173.23:52:30.06#ibcon#flushed, iclass 6, count 0 2006.173.23:52:30.06#ibcon#about to write, iclass 6, count 0 2006.173.23:52:30.06#ibcon#wrote, iclass 6, count 0 2006.173.23:52:30.06#ibcon#about to read 3, iclass 6, count 0 2006.173.23:52:30.08#ibcon#read 3, iclass 6, count 0 2006.173.23:52:30.08#ibcon#about to read 4, iclass 6, count 0 2006.173.23:52:30.08#ibcon#read 4, iclass 6, count 0 2006.173.23:52:30.08#ibcon#about to read 5, iclass 6, count 0 2006.173.23:52:30.08#ibcon#read 5, iclass 6, count 0 2006.173.23:52:30.08#ibcon#about to read 6, iclass 6, count 0 2006.173.23:52:30.08#ibcon#read 6, iclass 6, count 0 2006.173.23:52:30.08#ibcon#end of sib2, iclass 6, count 0 2006.173.23:52:30.08#ibcon#*mode == 0, iclass 6, count 0 2006.173.23:52:30.08#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.173.23:52:30.08#ibcon#[27=USB\r\n] 2006.173.23:52:30.08#ibcon#*before write, iclass 6, count 0 2006.173.23:52:30.08#ibcon#enter sib2, iclass 6, count 0 2006.173.23:52:30.08#ibcon#flushed, iclass 6, count 0 2006.173.23:52:30.08#ibcon#about to write, iclass 6, count 0 2006.173.23:52:30.08#ibcon#wrote, iclass 6, count 0 2006.173.23:52:30.08#ibcon#about to read 3, iclass 6, count 0 2006.173.23:52:30.11#ibcon#read 3, iclass 6, count 0 2006.173.23:52:30.11#ibcon#about to read 4, iclass 6, count 0 2006.173.23:52:30.11#ibcon#read 4, iclass 6, count 0 2006.173.23:52:30.11#ibcon#about to read 5, iclass 6, count 0 2006.173.23:52:30.11#ibcon#read 5, iclass 6, count 0 2006.173.23:52:30.11#ibcon#about to read 6, iclass 6, count 0 2006.173.23:52:30.11#ibcon#read 6, iclass 6, count 0 2006.173.23:52:30.11#ibcon#end of sib2, iclass 6, count 0 2006.173.23:52:30.11#ibcon#*after write, iclass 6, count 0 2006.173.23:52:30.11#ibcon#*before return 0, iclass 6, count 0 2006.173.23:52:30.11#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.173.23:52:30.11#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.173.23:52:30.11#ibcon#about to clear, iclass 6 cls_cnt 0 2006.173.23:52:30.11#ibcon#cleared, iclass 6 cls_cnt 0 2006.173.23:52:30.11$vck44/vblo=2,634.99 2006.173.23:52:30.11#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.173.23:52:30.11#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.173.23:52:30.11#ibcon#ireg 17 cls_cnt 0 2006.173.23:52:30.11#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.23:52:30.11#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.173.23:52:30.11#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.23:52:30.11#ibcon#enter wrdev, iclass 10, count 0 2006.173.23:52:30.11#ibcon#first serial, iclass 10, count 0 2006.173.23:52:30.11#ibcon#enter sib2, iclass 10, count 0 2006.173.23:52:30.11#ibcon#flushed, iclass 10, count 0 2006.173.23:52:30.11#ibcon#about to write, iclass 10, count 0 2006.173.23:52:30.11#ibcon#wrote, iclass 10, count 0 2006.173.23:52:30.11#ibcon#about to read 3, iclass 10, count 0 2006.173.23:52:30.13#ibcon#read 3, iclass 10, count 0 2006.173.23:52:30.13#ibcon#about to read 4, iclass 10, count 0 2006.173.23:52:30.13#ibcon#read 4, iclass 10, count 0 2006.173.23:52:30.13#ibcon#about to read 5, iclass 10, count 0 2006.173.23:52:30.13#ibcon#read 5, iclass 10, count 0 2006.173.23:52:30.13#ibcon#about to read 6, iclass 10, count 0 2006.173.23:52:30.13#ibcon#read 6, iclass 10, count 0 2006.173.23:52:30.13#ibcon#end of sib2, iclass 10, count 0 2006.173.23:52:30.13#ibcon#*mode == 0, iclass 10, count 0 2006.173.23:52:30.13#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.173.23:52:30.13#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.23:52:30.13#ibcon#*before write, iclass 10, count 0 2006.173.23:52:30.13#ibcon#enter sib2, iclass 10, count 0 2006.173.23:52:30.13#ibcon#flushed, iclass 10, count 0 2006.173.23:52:30.13#ibcon#about to write, iclass 10, count 0 2006.173.23:52:30.13#ibcon#wrote, iclass 10, count 0 2006.173.23:52:30.13#ibcon#about to read 3, iclass 10, count 0 2006.173.23:52:30.17#ibcon#read 3, iclass 10, count 0 2006.173.23:52:30.17#ibcon#about to read 4, iclass 10, count 0 2006.173.23:52:30.17#ibcon#read 4, iclass 10, count 0 2006.173.23:52:30.17#ibcon#about to read 5, iclass 10, count 0 2006.173.23:52:30.17#ibcon#read 5, iclass 10, count 0 2006.173.23:52:30.17#ibcon#about to read 6, iclass 10, count 0 2006.173.23:52:30.17#ibcon#read 6, iclass 10, count 0 2006.173.23:52:30.17#ibcon#end of sib2, iclass 10, count 0 2006.173.23:52:30.17#ibcon#*after write, iclass 10, count 0 2006.173.23:52:30.17#ibcon#*before return 0, iclass 10, count 0 2006.173.23:52:30.17#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.173.23:52:30.17#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.173.23:52:30.17#ibcon#about to clear, iclass 10 cls_cnt 0 2006.173.23:52:30.17#ibcon#cleared, iclass 10 cls_cnt 0 2006.173.23:52:30.17$vck44/vb=2,4 2006.173.23:52:30.17#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.173.23:52:30.17#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.173.23:52:30.17#ibcon#ireg 11 cls_cnt 2 2006.173.23:52:30.17#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.23:52:30.23#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.173.23:52:30.23#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.23:52:30.23#ibcon#enter wrdev, iclass 12, count 2 2006.173.23:52:30.23#ibcon#first serial, iclass 12, count 2 2006.173.23:52:30.23#ibcon#enter sib2, iclass 12, count 2 2006.173.23:52:30.23#ibcon#flushed, iclass 12, count 2 2006.173.23:52:30.23#ibcon#about to write, iclass 12, count 2 2006.173.23:52:30.23#ibcon#wrote, iclass 12, count 2 2006.173.23:52:30.23#ibcon#about to read 3, iclass 12, count 2 2006.173.23:52:30.25#ibcon#read 3, iclass 12, count 2 2006.173.23:52:30.25#ibcon#about to read 4, iclass 12, count 2 2006.173.23:52:30.25#ibcon#read 4, iclass 12, count 2 2006.173.23:52:30.25#ibcon#about to read 5, iclass 12, count 2 2006.173.23:52:30.25#ibcon#read 5, iclass 12, count 2 2006.173.23:52:30.25#ibcon#about to read 6, iclass 12, count 2 2006.173.23:52:30.25#ibcon#read 6, iclass 12, count 2 2006.173.23:52:30.25#ibcon#end of sib2, iclass 12, count 2 2006.173.23:52:30.25#ibcon#*mode == 0, iclass 12, count 2 2006.173.23:52:30.25#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.173.23:52:30.25#ibcon#[27=AT02-04\r\n] 2006.173.23:52:30.25#ibcon#*before write, iclass 12, count 2 2006.173.23:52:30.25#ibcon#enter sib2, iclass 12, count 2 2006.173.23:52:30.25#ibcon#flushed, iclass 12, count 2 2006.173.23:52:30.25#ibcon#about to write, iclass 12, count 2 2006.173.23:52:30.25#ibcon#wrote, iclass 12, count 2 2006.173.23:52:30.25#ibcon#about to read 3, iclass 12, count 2 2006.173.23:52:30.28#ibcon#read 3, iclass 12, count 2 2006.173.23:52:30.28#ibcon#about to read 4, iclass 12, count 2 2006.173.23:52:30.28#ibcon#read 4, iclass 12, count 2 2006.173.23:52:30.28#ibcon#about to read 5, iclass 12, count 2 2006.173.23:52:30.28#ibcon#read 5, iclass 12, count 2 2006.173.23:52:30.28#ibcon#about to read 6, iclass 12, count 2 2006.173.23:52:30.28#ibcon#read 6, iclass 12, count 2 2006.173.23:52:30.28#ibcon#end of sib2, iclass 12, count 2 2006.173.23:52:30.28#ibcon#*after write, iclass 12, count 2 2006.173.23:52:30.28#ibcon#*before return 0, iclass 12, count 2 2006.173.23:52:30.28#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.173.23:52:30.28#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.173.23:52:30.28#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.173.23:52:30.28#ibcon#ireg 7 cls_cnt 0 2006.173.23:52:30.28#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.23:52:30.40#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.173.23:52:30.40#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.23:52:30.40#ibcon#enter wrdev, iclass 12, count 0 2006.173.23:52:30.40#ibcon#first serial, iclass 12, count 0 2006.173.23:52:30.40#ibcon#enter sib2, iclass 12, count 0 2006.173.23:52:30.40#ibcon#flushed, iclass 12, count 0 2006.173.23:52:30.40#ibcon#about to write, iclass 12, count 0 2006.173.23:52:30.40#ibcon#wrote, iclass 12, count 0 2006.173.23:52:30.40#ibcon#about to read 3, iclass 12, count 0 2006.173.23:52:30.42#ibcon#read 3, iclass 12, count 0 2006.173.23:52:30.42#ibcon#about to read 4, iclass 12, count 0 2006.173.23:52:30.42#ibcon#read 4, iclass 12, count 0 2006.173.23:52:30.42#ibcon#about to read 5, iclass 12, count 0 2006.173.23:52:30.42#ibcon#read 5, iclass 12, count 0 2006.173.23:52:30.42#ibcon#about to read 6, iclass 12, count 0 2006.173.23:52:30.42#ibcon#read 6, iclass 12, count 0 2006.173.23:52:30.42#ibcon#end of sib2, iclass 12, count 0 2006.173.23:52:30.42#ibcon#*mode == 0, iclass 12, count 0 2006.173.23:52:30.42#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.173.23:52:30.42#ibcon#[27=USB\r\n] 2006.173.23:52:30.42#ibcon#*before write, iclass 12, count 0 2006.173.23:52:30.42#ibcon#enter sib2, iclass 12, count 0 2006.173.23:52:30.42#ibcon#flushed, iclass 12, count 0 2006.173.23:52:30.42#ibcon#about to write, iclass 12, count 0 2006.173.23:52:30.42#ibcon#wrote, iclass 12, count 0 2006.173.23:52:30.42#ibcon#about to read 3, iclass 12, count 0 2006.173.23:52:30.45#ibcon#read 3, iclass 12, count 0 2006.173.23:52:30.45#ibcon#about to read 4, iclass 12, count 0 2006.173.23:52:30.45#ibcon#read 4, iclass 12, count 0 2006.173.23:52:30.45#ibcon#about to read 5, iclass 12, count 0 2006.173.23:52:30.45#ibcon#read 5, iclass 12, count 0 2006.173.23:52:30.45#ibcon#about to read 6, iclass 12, count 0 2006.173.23:52:30.45#ibcon#read 6, iclass 12, count 0 2006.173.23:52:30.45#ibcon#end of sib2, iclass 12, count 0 2006.173.23:52:30.45#ibcon#*after write, iclass 12, count 0 2006.173.23:52:30.45#ibcon#*before return 0, iclass 12, count 0 2006.173.23:52:30.45#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.173.23:52:30.45#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.173.23:52:30.45#ibcon#about to clear, iclass 12 cls_cnt 0 2006.173.23:52:30.45#ibcon#cleared, iclass 12 cls_cnt 0 2006.173.23:52:30.45$vck44/vblo=3,649.99 2006.173.23:52:30.45#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.173.23:52:30.45#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.173.23:52:30.45#ibcon#ireg 17 cls_cnt 0 2006.173.23:52:30.45#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.23:52:30.45#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.173.23:52:30.45#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.23:52:30.45#ibcon#enter wrdev, iclass 14, count 0 2006.173.23:52:30.45#ibcon#first serial, iclass 14, count 0 2006.173.23:52:30.45#ibcon#enter sib2, iclass 14, count 0 2006.173.23:52:30.45#ibcon#flushed, iclass 14, count 0 2006.173.23:52:30.45#ibcon#about to write, iclass 14, count 0 2006.173.23:52:30.45#ibcon#wrote, iclass 14, count 0 2006.173.23:52:30.45#ibcon#about to read 3, iclass 14, count 0 2006.173.23:52:30.47#ibcon#read 3, iclass 14, count 0 2006.173.23:52:30.47#ibcon#about to read 4, iclass 14, count 0 2006.173.23:52:30.47#ibcon#read 4, iclass 14, count 0 2006.173.23:52:30.47#ibcon#about to read 5, iclass 14, count 0 2006.173.23:52:30.47#ibcon#read 5, iclass 14, count 0 2006.173.23:52:30.47#ibcon#about to read 6, iclass 14, count 0 2006.173.23:52:30.47#ibcon#read 6, iclass 14, count 0 2006.173.23:52:30.47#ibcon#end of sib2, iclass 14, count 0 2006.173.23:52:30.47#ibcon#*mode == 0, iclass 14, count 0 2006.173.23:52:30.47#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.173.23:52:30.47#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.23:52:30.47#ibcon#*before write, iclass 14, count 0 2006.173.23:52:30.47#ibcon#enter sib2, iclass 14, count 0 2006.173.23:52:30.47#ibcon#flushed, iclass 14, count 0 2006.173.23:52:30.47#ibcon#about to write, iclass 14, count 0 2006.173.23:52:30.47#ibcon#wrote, iclass 14, count 0 2006.173.23:52:30.47#ibcon#about to read 3, iclass 14, count 0 2006.173.23:52:30.51#ibcon#read 3, iclass 14, count 0 2006.173.23:52:30.51#ibcon#about to read 4, iclass 14, count 0 2006.173.23:52:30.51#ibcon#read 4, iclass 14, count 0 2006.173.23:52:30.51#ibcon#about to read 5, iclass 14, count 0 2006.173.23:52:30.51#ibcon#read 5, iclass 14, count 0 2006.173.23:52:30.51#ibcon#about to read 6, iclass 14, count 0 2006.173.23:52:30.51#ibcon#read 6, iclass 14, count 0 2006.173.23:52:30.51#ibcon#end of sib2, iclass 14, count 0 2006.173.23:52:30.51#ibcon#*after write, iclass 14, count 0 2006.173.23:52:30.51#ibcon#*before return 0, iclass 14, count 0 2006.173.23:52:30.51#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.173.23:52:30.51#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.173.23:52:30.51#ibcon#about to clear, iclass 14 cls_cnt 0 2006.173.23:52:30.51#ibcon#cleared, iclass 14 cls_cnt 0 2006.173.23:52:30.51$vck44/vb=3,4 2006.173.23:52:30.51#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.173.23:52:30.51#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.173.23:52:30.51#ibcon#ireg 11 cls_cnt 2 2006.173.23:52:30.51#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.23:52:30.57#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.173.23:52:30.57#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.23:52:30.57#ibcon#enter wrdev, iclass 16, count 2 2006.173.23:52:30.57#ibcon#first serial, iclass 16, count 2 2006.173.23:52:30.57#ibcon#enter sib2, iclass 16, count 2 2006.173.23:52:30.57#ibcon#flushed, iclass 16, count 2 2006.173.23:52:30.57#ibcon#about to write, iclass 16, count 2 2006.173.23:52:30.57#ibcon#wrote, iclass 16, count 2 2006.173.23:52:30.57#ibcon#about to read 3, iclass 16, count 2 2006.173.23:52:30.59#ibcon#read 3, iclass 16, count 2 2006.173.23:52:30.59#ibcon#about to read 4, iclass 16, count 2 2006.173.23:52:30.59#ibcon#read 4, iclass 16, count 2 2006.173.23:52:30.59#ibcon#about to read 5, iclass 16, count 2 2006.173.23:52:30.59#ibcon#read 5, iclass 16, count 2 2006.173.23:52:30.59#ibcon#about to read 6, iclass 16, count 2 2006.173.23:52:30.59#ibcon#read 6, iclass 16, count 2 2006.173.23:52:30.59#ibcon#end of sib2, iclass 16, count 2 2006.173.23:52:30.59#ibcon#*mode == 0, iclass 16, count 2 2006.173.23:52:30.59#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.173.23:52:30.59#ibcon#[27=AT03-04\r\n] 2006.173.23:52:30.59#ibcon#*before write, iclass 16, count 2 2006.173.23:52:30.59#ibcon#enter sib2, iclass 16, count 2 2006.173.23:52:30.59#ibcon#flushed, iclass 16, count 2 2006.173.23:52:30.59#ibcon#about to write, iclass 16, count 2 2006.173.23:52:30.59#ibcon#wrote, iclass 16, count 2 2006.173.23:52:30.59#ibcon#about to read 3, iclass 16, count 2 2006.173.23:52:30.62#ibcon#read 3, iclass 16, count 2 2006.173.23:52:30.62#ibcon#about to read 4, iclass 16, count 2 2006.173.23:52:30.62#ibcon#read 4, iclass 16, count 2 2006.173.23:52:30.62#ibcon#about to read 5, iclass 16, count 2 2006.173.23:52:30.62#ibcon#read 5, iclass 16, count 2 2006.173.23:52:30.62#ibcon#about to read 6, iclass 16, count 2 2006.173.23:52:30.62#ibcon#read 6, iclass 16, count 2 2006.173.23:52:30.62#ibcon#end of sib2, iclass 16, count 2 2006.173.23:52:30.62#ibcon#*after write, iclass 16, count 2 2006.173.23:52:30.62#ibcon#*before return 0, iclass 16, count 2 2006.173.23:52:30.62#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.173.23:52:30.62#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.173.23:52:30.62#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.173.23:52:30.62#ibcon#ireg 7 cls_cnt 0 2006.173.23:52:30.62#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.23:52:30.74#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.173.23:52:30.74#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.23:52:30.74#ibcon#enter wrdev, iclass 16, count 0 2006.173.23:52:30.74#ibcon#first serial, iclass 16, count 0 2006.173.23:52:30.74#ibcon#enter sib2, iclass 16, count 0 2006.173.23:52:30.74#ibcon#flushed, iclass 16, count 0 2006.173.23:52:30.74#ibcon#about to write, iclass 16, count 0 2006.173.23:52:30.74#ibcon#wrote, iclass 16, count 0 2006.173.23:52:30.74#ibcon#about to read 3, iclass 16, count 0 2006.173.23:52:30.76#ibcon#read 3, iclass 16, count 0 2006.173.23:52:30.76#ibcon#about to read 4, iclass 16, count 0 2006.173.23:52:30.76#ibcon#read 4, iclass 16, count 0 2006.173.23:52:30.76#ibcon#about to read 5, iclass 16, count 0 2006.173.23:52:30.76#ibcon#read 5, iclass 16, count 0 2006.173.23:52:30.76#ibcon#about to read 6, iclass 16, count 0 2006.173.23:52:30.76#ibcon#read 6, iclass 16, count 0 2006.173.23:52:30.76#ibcon#end of sib2, iclass 16, count 0 2006.173.23:52:30.76#ibcon#*mode == 0, iclass 16, count 0 2006.173.23:52:30.76#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.173.23:52:30.76#ibcon#[27=USB\r\n] 2006.173.23:52:30.76#ibcon#*before write, iclass 16, count 0 2006.173.23:52:30.76#ibcon#enter sib2, iclass 16, count 0 2006.173.23:52:30.76#ibcon#flushed, iclass 16, count 0 2006.173.23:52:30.76#ibcon#about to write, iclass 16, count 0 2006.173.23:52:30.76#ibcon#wrote, iclass 16, count 0 2006.173.23:52:30.76#ibcon#about to read 3, iclass 16, count 0 2006.173.23:52:30.79#ibcon#read 3, iclass 16, count 0 2006.173.23:52:30.79#ibcon#about to read 4, iclass 16, count 0 2006.173.23:52:30.79#ibcon#read 4, iclass 16, count 0 2006.173.23:52:30.79#ibcon#about to read 5, iclass 16, count 0 2006.173.23:52:30.79#ibcon#read 5, iclass 16, count 0 2006.173.23:52:30.79#ibcon#about to read 6, iclass 16, count 0 2006.173.23:52:30.79#ibcon#read 6, iclass 16, count 0 2006.173.23:52:30.79#ibcon#end of sib2, iclass 16, count 0 2006.173.23:52:30.79#ibcon#*after write, iclass 16, count 0 2006.173.23:52:30.79#ibcon#*before return 0, iclass 16, count 0 2006.173.23:52:30.79#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.173.23:52:30.79#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.173.23:52:30.79#ibcon#about to clear, iclass 16 cls_cnt 0 2006.173.23:52:30.79#ibcon#cleared, iclass 16 cls_cnt 0 2006.173.23:52:30.79$vck44/vblo=4,679.99 2006.173.23:52:30.79#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.173.23:52:30.79#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.173.23:52:30.79#ibcon#ireg 17 cls_cnt 0 2006.173.23:52:30.79#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.23:52:30.79#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.173.23:52:30.79#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.23:52:30.79#ibcon#enter wrdev, iclass 18, count 0 2006.173.23:52:30.79#ibcon#first serial, iclass 18, count 0 2006.173.23:52:30.79#ibcon#enter sib2, iclass 18, count 0 2006.173.23:52:30.79#ibcon#flushed, iclass 18, count 0 2006.173.23:52:30.79#ibcon#about to write, iclass 18, count 0 2006.173.23:52:30.79#ibcon#wrote, iclass 18, count 0 2006.173.23:52:30.79#ibcon#about to read 3, iclass 18, count 0 2006.173.23:52:30.81#ibcon#read 3, iclass 18, count 0 2006.173.23:52:30.81#ibcon#about to read 4, iclass 18, count 0 2006.173.23:52:30.81#ibcon#read 4, iclass 18, count 0 2006.173.23:52:30.81#ibcon#about to read 5, iclass 18, count 0 2006.173.23:52:30.81#ibcon#read 5, iclass 18, count 0 2006.173.23:52:30.81#ibcon#about to read 6, iclass 18, count 0 2006.173.23:52:30.81#ibcon#read 6, iclass 18, count 0 2006.173.23:52:30.81#ibcon#end of sib2, iclass 18, count 0 2006.173.23:52:30.81#ibcon#*mode == 0, iclass 18, count 0 2006.173.23:52:30.81#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.173.23:52:30.81#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.23:52:30.81#ibcon#*before write, iclass 18, count 0 2006.173.23:52:30.81#ibcon#enter sib2, iclass 18, count 0 2006.173.23:52:30.81#ibcon#flushed, iclass 18, count 0 2006.173.23:52:30.81#ibcon#about to write, iclass 18, count 0 2006.173.23:52:30.81#ibcon#wrote, iclass 18, count 0 2006.173.23:52:30.81#ibcon#about to read 3, iclass 18, count 0 2006.173.23:52:30.85#ibcon#read 3, iclass 18, count 0 2006.173.23:52:30.85#ibcon#about to read 4, iclass 18, count 0 2006.173.23:52:30.85#ibcon#read 4, iclass 18, count 0 2006.173.23:52:30.85#ibcon#about to read 5, iclass 18, count 0 2006.173.23:52:30.85#ibcon#read 5, iclass 18, count 0 2006.173.23:52:30.85#ibcon#about to read 6, iclass 18, count 0 2006.173.23:52:30.85#ibcon#read 6, iclass 18, count 0 2006.173.23:52:30.85#ibcon#end of sib2, iclass 18, count 0 2006.173.23:52:30.85#ibcon#*after write, iclass 18, count 0 2006.173.23:52:30.85#ibcon#*before return 0, iclass 18, count 0 2006.173.23:52:30.85#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.173.23:52:30.85#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.173.23:52:30.85#ibcon#about to clear, iclass 18 cls_cnt 0 2006.173.23:52:30.85#ibcon#cleared, iclass 18 cls_cnt 0 2006.173.23:52:30.85$vck44/vb=4,4 2006.173.23:52:30.85#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.173.23:52:30.85#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.173.23:52:30.85#ibcon#ireg 11 cls_cnt 2 2006.173.23:52:30.85#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.23:52:30.91#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.173.23:52:30.91#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.23:52:30.91#ibcon#enter wrdev, iclass 20, count 2 2006.173.23:52:30.91#ibcon#first serial, iclass 20, count 2 2006.173.23:52:30.91#ibcon#enter sib2, iclass 20, count 2 2006.173.23:52:30.91#ibcon#flushed, iclass 20, count 2 2006.173.23:52:30.91#ibcon#about to write, iclass 20, count 2 2006.173.23:52:30.91#ibcon#wrote, iclass 20, count 2 2006.173.23:52:30.91#ibcon#about to read 3, iclass 20, count 2 2006.173.23:52:30.93#ibcon#read 3, iclass 20, count 2 2006.173.23:52:30.93#ibcon#about to read 4, iclass 20, count 2 2006.173.23:52:30.93#ibcon#read 4, iclass 20, count 2 2006.173.23:52:30.93#ibcon#about to read 5, iclass 20, count 2 2006.173.23:52:30.93#ibcon#read 5, iclass 20, count 2 2006.173.23:52:30.93#ibcon#about to read 6, iclass 20, count 2 2006.173.23:52:30.93#ibcon#read 6, iclass 20, count 2 2006.173.23:52:30.93#ibcon#end of sib2, iclass 20, count 2 2006.173.23:52:30.93#ibcon#*mode == 0, iclass 20, count 2 2006.173.23:52:30.93#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.173.23:52:30.93#ibcon#[27=AT04-04\r\n] 2006.173.23:52:30.93#ibcon#*before write, iclass 20, count 2 2006.173.23:52:30.93#ibcon#enter sib2, iclass 20, count 2 2006.173.23:52:30.93#ibcon#flushed, iclass 20, count 2 2006.173.23:52:30.93#ibcon#about to write, iclass 20, count 2 2006.173.23:52:30.93#ibcon#wrote, iclass 20, count 2 2006.173.23:52:30.93#ibcon#about to read 3, iclass 20, count 2 2006.173.23:52:30.96#ibcon#read 3, iclass 20, count 2 2006.173.23:52:30.96#ibcon#about to read 4, iclass 20, count 2 2006.173.23:52:30.96#ibcon#read 4, iclass 20, count 2 2006.173.23:52:30.96#ibcon#about to read 5, iclass 20, count 2 2006.173.23:52:30.96#ibcon#read 5, iclass 20, count 2 2006.173.23:52:30.96#ibcon#about to read 6, iclass 20, count 2 2006.173.23:52:30.96#ibcon#read 6, iclass 20, count 2 2006.173.23:52:30.96#ibcon#end of sib2, iclass 20, count 2 2006.173.23:52:30.96#ibcon#*after write, iclass 20, count 2 2006.173.23:52:30.96#ibcon#*before return 0, iclass 20, count 2 2006.173.23:52:30.96#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.173.23:52:30.96#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.173.23:52:30.96#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.173.23:52:30.96#ibcon#ireg 7 cls_cnt 0 2006.173.23:52:30.96#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.23:52:31.08#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.173.23:52:31.08#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.23:52:31.08#ibcon#enter wrdev, iclass 20, count 0 2006.173.23:52:31.08#ibcon#first serial, iclass 20, count 0 2006.173.23:52:31.08#ibcon#enter sib2, iclass 20, count 0 2006.173.23:52:31.08#ibcon#flushed, iclass 20, count 0 2006.173.23:52:31.08#ibcon#about to write, iclass 20, count 0 2006.173.23:52:31.08#ibcon#wrote, iclass 20, count 0 2006.173.23:52:31.08#ibcon#about to read 3, iclass 20, count 0 2006.173.23:52:31.10#ibcon#read 3, iclass 20, count 0 2006.173.23:52:31.10#ibcon#about to read 4, iclass 20, count 0 2006.173.23:52:31.10#ibcon#read 4, iclass 20, count 0 2006.173.23:52:31.10#ibcon#about to read 5, iclass 20, count 0 2006.173.23:52:31.10#ibcon#read 5, iclass 20, count 0 2006.173.23:52:31.10#ibcon#about to read 6, iclass 20, count 0 2006.173.23:52:31.10#ibcon#read 6, iclass 20, count 0 2006.173.23:52:31.10#ibcon#end of sib2, iclass 20, count 0 2006.173.23:52:31.10#ibcon#*mode == 0, iclass 20, count 0 2006.173.23:52:31.10#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.173.23:52:31.10#ibcon#[27=USB\r\n] 2006.173.23:52:31.10#ibcon#*before write, iclass 20, count 0 2006.173.23:52:31.10#ibcon#enter sib2, iclass 20, count 0 2006.173.23:52:31.10#ibcon#flushed, iclass 20, count 0 2006.173.23:52:31.10#ibcon#about to write, iclass 20, count 0 2006.173.23:52:31.10#ibcon#wrote, iclass 20, count 0 2006.173.23:52:31.10#ibcon#about to read 3, iclass 20, count 0 2006.173.23:52:31.13#ibcon#read 3, iclass 20, count 0 2006.173.23:52:31.13#ibcon#about to read 4, iclass 20, count 0 2006.173.23:52:31.13#ibcon#read 4, iclass 20, count 0 2006.173.23:52:31.13#ibcon#about to read 5, iclass 20, count 0 2006.173.23:52:31.13#ibcon#read 5, iclass 20, count 0 2006.173.23:52:31.13#ibcon#about to read 6, iclass 20, count 0 2006.173.23:52:31.13#ibcon#read 6, iclass 20, count 0 2006.173.23:52:31.13#ibcon#end of sib2, iclass 20, count 0 2006.173.23:52:31.13#ibcon#*after write, iclass 20, count 0 2006.173.23:52:31.13#ibcon#*before return 0, iclass 20, count 0 2006.173.23:52:31.13#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.173.23:52:31.13#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.173.23:52:31.13#ibcon#about to clear, iclass 20 cls_cnt 0 2006.173.23:52:31.13#ibcon#cleared, iclass 20 cls_cnt 0 2006.173.23:52:31.13$vck44/vblo=5,709.99 2006.173.23:52:31.13#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.173.23:52:31.13#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.173.23:52:31.13#ibcon#ireg 17 cls_cnt 0 2006.173.23:52:31.13#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.23:52:31.13#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.173.23:52:31.13#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.23:52:31.13#ibcon#enter wrdev, iclass 22, count 0 2006.173.23:52:31.13#ibcon#first serial, iclass 22, count 0 2006.173.23:52:31.13#ibcon#enter sib2, iclass 22, count 0 2006.173.23:52:31.13#ibcon#flushed, iclass 22, count 0 2006.173.23:52:31.13#ibcon#about to write, iclass 22, count 0 2006.173.23:52:31.13#ibcon#wrote, iclass 22, count 0 2006.173.23:52:31.13#ibcon#about to read 3, iclass 22, count 0 2006.173.23:52:31.15#ibcon#read 3, iclass 22, count 0 2006.173.23:52:31.15#ibcon#about to read 4, iclass 22, count 0 2006.173.23:52:31.15#ibcon#read 4, iclass 22, count 0 2006.173.23:52:31.15#ibcon#about to read 5, iclass 22, count 0 2006.173.23:52:31.15#ibcon#read 5, iclass 22, count 0 2006.173.23:52:31.15#ibcon#about to read 6, iclass 22, count 0 2006.173.23:52:31.15#ibcon#read 6, iclass 22, count 0 2006.173.23:52:31.15#ibcon#end of sib2, iclass 22, count 0 2006.173.23:52:31.15#ibcon#*mode == 0, iclass 22, count 0 2006.173.23:52:31.15#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.173.23:52:31.15#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.23:52:31.15#ibcon#*before write, iclass 22, count 0 2006.173.23:52:31.15#ibcon#enter sib2, iclass 22, count 0 2006.173.23:52:31.15#ibcon#flushed, iclass 22, count 0 2006.173.23:52:31.15#ibcon#about to write, iclass 22, count 0 2006.173.23:52:31.15#ibcon#wrote, iclass 22, count 0 2006.173.23:52:31.15#ibcon#about to read 3, iclass 22, count 0 2006.173.23:52:31.19#ibcon#read 3, iclass 22, count 0 2006.173.23:52:31.19#ibcon#about to read 4, iclass 22, count 0 2006.173.23:52:31.19#ibcon#read 4, iclass 22, count 0 2006.173.23:52:31.19#ibcon#about to read 5, iclass 22, count 0 2006.173.23:52:31.19#ibcon#read 5, iclass 22, count 0 2006.173.23:52:31.19#ibcon#about to read 6, iclass 22, count 0 2006.173.23:52:31.19#ibcon#read 6, iclass 22, count 0 2006.173.23:52:31.19#ibcon#end of sib2, iclass 22, count 0 2006.173.23:52:31.19#ibcon#*after write, iclass 22, count 0 2006.173.23:52:31.19#ibcon#*before return 0, iclass 22, count 0 2006.173.23:52:31.19#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.173.23:52:31.19#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.173.23:52:31.19#ibcon#about to clear, iclass 22 cls_cnt 0 2006.173.23:52:31.19#ibcon#cleared, iclass 22 cls_cnt 0 2006.173.23:52:31.19$vck44/vb=5,4 2006.173.23:52:31.19#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.173.23:52:31.19#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.173.23:52:31.19#ibcon#ireg 11 cls_cnt 2 2006.173.23:52:31.19#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.23:52:31.25#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.173.23:52:31.25#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.23:52:31.25#ibcon#enter wrdev, iclass 24, count 2 2006.173.23:52:31.25#ibcon#first serial, iclass 24, count 2 2006.173.23:52:31.25#ibcon#enter sib2, iclass 24, count 2 2006.173.23:52:31.25#ibcon#flushed, iclass 24, count 2 2006.173.23:52:31.25#ibcon#about to write, iclass 24, count 2 2006.173.23:52:31.25#ibcon#wrote, iclass 24, count 2 2006.173.23:52:31.25#ibcon#about to read 3, iclass 24, count 2 2006.173.23:52:31.27#ibcon#read 3, iclass 24, count 2 2006.173.23:52:31.27#ibcon#about to read 4, iclass 24, count 2 2006.173.23:52:31.27#ibcon#read 4, iclass 24, count 2 2006.173.23:52:31.27#ibcon#about to read 5, iclass 24, count 2 2006.173.23:52:31.27#ibcon#read 5, iclass 24, count 2 2006.173.23:52:31.27#ibcon#about to read 6, iclass 24, count 2 2006.173.23:52:31.27#ibcon#read 6, iclass 24, count 2 2006.173.23:52:31.27#ibcon#end of sib2, iclass 24, count 2 2006.173.23:52:31.27#ibcon#*mode == 0, iclass 24, count 2 2006.173.23:52:31.27#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.173.23:52:31.27#ibcon#[27=AT05-04\r\n] 2006.173.23:52:31.27#ibcon#*before write, iclass 24, count 2 2006.173.23:52:31.27#ibcon#enter sib2, iclass 24, count 2 2006.173.23:52:31.27#ibcon#flushed, iclass 24, count 2 2006.173.23:52:31.27#ibcon#about to write, iclass 24, count 2 2006.173.23:52:31.27#ibcon#wrote, iclass 24, count 2 2006.173.23:52:31.27#ibcon#about to read 3, iclass 24, count 2 2006.173.23:52:31.30#ibcon#read 3, iclass 24, count 2 2006.173.23:52:31.30#ibcon#about to read 4, iclass 24, count 2 2006.173.23:52:31.30#ibcon#read 4, iclass 24, count 2 2006.173.23:52:31.30#ibcon#about to read 5, iclass 24, count 2 2006.173.23:52:31.30#ibcon#read 5, iclass 24, count 2 2006.173.23:52:31.30#ibcon#about to read 6, iclass 24, count 2 2006.173.23:52:31.30#ibcon#read 6, iclass 24, count 2 2006.173.23:52:31.30#ibcon#end of sib2, iclass 24, count 2 2006.173.23:52:31.30#ibcon#*after write, iclass 24, count 2 2006.173.23:52:31.30#ibcon#*before return 0, iclass 24, count 2 2006.173.23:52:31.30#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.173.23:52:31.30#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.173.23:52:31.30#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.173.23:52:31.30#ibcon#ireg 7 cls_cnt 0 2006.173.23:52:31.30#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.23:52:31.42#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.173.23:52:31.42#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.23:52:31.42#ibcon#enter wrdev, iclass 24, count 0 2006.173.23:52:31.42#ibcon#first serial, iclass 24, count 0 2006.173.23:52:31.42#ibcon#enter sib2, iclass 24, count 0 2006.173.23:52:31.42#ibcon#flushed, iclass 24, count 0 2006.173.23:52:31.42#ibcon#about to write, iclass 24, count 0 2006.173.23:52:31.42#ibcon#wrote, iclass 24, count 0 2006.173.23:52:31.42#ibcon#about to read 3, iclass 24, count 0 2006.173.23:52:31.44#ibcon#read 3, iclass 24, count 0 2006.173.23:52:31.44#ibcon#about to read 4, iclass 24, count 0 2006.173.23:52:31.44#ibcon#read 4, iclass 24, count 0 2006.173.23:52:31.44#ibcon#about to read 5, iclass 24, count 0 2006.173.23:52:31.44#ibcon#read 5, iclass 24, count 0 2006.173.23:52:31.44#ibcon#about to read 6, iclass 24, count 0 2006.173.23:52:31.44#ibcon#read 6, iclass 24, count 0 2006.173.23:52:31.44#ibcon#end of sib2, iclass 24, count 0 2006.173.23:52:31.44#ibcon#*mode == 0, iclass 24, count 0 2006.173.23:52:31.44#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.173.23:52:31.44#ibcon#[27=USB\r\n] 2006.173.23:52:31.44#ibcon#*before write, iclass 24, count 0 2006.173.23:52:31.44#ibcon#enter sib2, iclass 24, count 0 2006.173.23:52:31.44#ibcon#flushed, iclass 24, count 0 2006.173.23:52:31.44#ibcon#about to write, iclass 24, count 0 2006.173.23:52:31.44#ibcon#wrote, iclass 24, count 0 2006.173.23:52:31.44#ibcon#about to read 3, iclass 24, count 0 2006.173.23:52:31.47#ibcon#read 3, iclass 24, count 0 2006.173.23:52:31.47#ibcon#about to read 4, iclass 24, count 0 2006.173.23:52:31.47#ibcon#read 4, iclass 24, count 0 2006.173.23:52:31.47#ibcon#about to read 5, iclass 24, count 0 2006.173.23:52:31.47#ibcon#read 5, iclass 24, count 0 2006.173.23:52:31.47#ibcon#about to read 6, iclass 24, count 0 2006.173.23:52:31.47#ibcon#read 6, iclass 24, count 0 2006.173.23:52:31.47#ibcon#end of sib2, iclass 24, count 0 2006.173.23:52:31.47#ibcon#*after write, iclass 24, count 0 2006.173.23:52:31.47#ibcon#*before return 0, iclass 24, count 0 2006.173.23:52:31.47#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.173.23:52:31.47#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.173.23:52:31.47#ibcon#about to clear, iclass 24 cls_cnt 0 2006.173.23:52:31.47#ibcon#cleared, iclass 24 cls_cnt 0 2006.173.23:52:31.47$vck44/vblo=6,719.99 2006.173.23:52:31.47#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.173.23:52:31.47#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.173.23:52:31.47#ibcon#ireg 17 cls_cnt 0 2006.173.23:52:31.47#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.23:52:31.47#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.173.23:52:31.47#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.23:52:31.47#ibcon#enter wrdev, iclass 26, count 0 2006.173.23:52:31.47#ibcon#first serial, iclass 26, count 0 2006.173.23:52:31.47#ibcon#enter sib2, iclass 26, count 0 2006.173.23:52:31.47#ibcon#flushed, iclass 26, count 0 2006.173.23:52:31.47#ibcon#about to write, iclass 26, count 0 2006.173.23:52:31.47#ibcon#wrote, iclass 26, count 0 2006.173.23:52:31.47#ibcon#about to read 3, iclass 26, count 0 2006.173.23:52:31.49#ibcon#read 3, iclass 26, count 0 2006.173.23:52:31.49#ibcon#about to read 4, iclass 26, count 0 2006.173.23:52:31.49#ibcon#read 4, iclass 26, count 0 2006.173.23:52:31.49#ibcon#about to read 5, iclass 26, count 0 2006.173.23:52:31.49#ibcon#read 5, iclass 26, count 0 2006.173.23:52:31.49#ibcon#about to read 6, iclass 26, count 0 2006.173.23:52:31.49#ibcon#read 6, iclass 26, count 0 2006.173.23:52:31.49#ibcon#end of sib2, iclass 26, count 0 2006.173.23:52:31.49#ibcon#*mode == 0, iclass 26, count 0 2006.173.23:52:31.49#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.173.23:52:31.49#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.23:52:31.49#ibcon#*before write, iclass 26, count 0 2006.173.23:52:31.49#ibcon#enter sib2, iclass 26, count 0 2006.173.23:52:31.49#ibcon#flushed, iclass 26, count 0 2006.173.23:52:31.49#ibcon#about to write, iclass 26, count 0 2006.173.23:52:31.49#ibcon#wrote, iclass 26, count 0 2006.173.23:52:31.49#ibcon#about to read 3, iclass 26, count 0 2006.173.23:52:31.53#ibcon#read 3, iclass 26, count 0 2006.173.23:52:31.53#ibcon#about to read 4, iclass 26, count 0 2006.173.23:52:31.53#ibcon#read 4, iclass 26, count 0 2006.173.23:52:31.53#ibcon#about to read 5, iclass 26, count 0 2006.173.23:52:31.53#ibcon#read 5, iclass 26, count 0 2006.173.23:52:31.53#ibcon#about to read 6, iclass 26, count 0 2006.173.23:52:31.53#ibcon#read 6, iclass 26, count 0 2006.173.23:52:31.53#ibcon#end of sib2, iclass 26, count 0 2006.173.23:52:31.53#ibcon#*after write, iclass 26, count 0 2006.173.23:52:31.53#ibcon#*before return 0, iclass 26, count 0 2006.173.23:52:31.53#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.173.23:52:31.53#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.173.23:52:31.53#ibcon#about to clear, iclass 26 cls_cnt 0 2006.173.23:52:31.53#ibcon#cleared, iclass 26 cls_cnt 0 2006.173.23:52:31.53$vck44/vb=6,4 2006.173.23:52:31.53#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.173.23:52:31.53#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.173.23:52:31.53#ibcon#ireg 11 cls_cnt 2 2006.173.23:52:31.53#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.23:52:31.59#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.173.23:52:31.59#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.23:52:31.59#ibcon#enter wrdev, iclass 28, count 2 2006.173.23:52:31.59#ibcon#first serial, iclass 28, count 2 2006.173.23:52:31.59#ibcon#enter sib2, iclass 28, count 2 2006.173.23:52:31.59#ibcon#flushed, iclass 28, count 2 2006.173.23:52:31.59#ibcon#about to write, iclass 28, count 2 2006.173.23:52:31.59#ibcon#wrote, iclass 28, count 2 2006.173.23:52:31.59#ibcon#about to read 3, iclass 28, count 2 2006.173.23:52:31.61#ibcon#read 3, iclass 28, count 2 2006.173.23:52:31.61#ibcon#about to read 4, iclass 28, count 2 2006.173.23:52:31.61#ibcon#read 4, iclass 28, count 2 2006.173.23:52:31.61#ibcon#about to read 5, iclass 28, count 2 2006.173.23:52:31.61#ibcon#read 5, iclass 28, count 2 2006.173.23:52:31.61#ibcon#about to read 6, iclass 28, count 2 2006.173.23:52:31.61#ibcon#read 6, iclass 28, count 2 2006.173.23:52:31.61#ibcon#end of sib2, iclass 28, count 2 2006.173.23:52:31.61#ibcon#*mode == 0, iclass 28, count 2 2006.173.23:52:31.61#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.173.23:52:31.61#ibcon#[27=AT06-04\r\n] 2006.173.23:52:31.61#ibcon#*before write, iclass 28, count 2 2006.173.23:52:31.61#ibcon#enter sib2, iclass 28, count 2 2006.173.23:52:31.61#ibcon#flushed, iclass 28, count 2 2006.173.23:52:31.61#ibcon#about to write, iclass 28, count 2 2006.173.23:52:31.61#ibcon#wrote, iclass 28, count 2 2006.173.23:52:31.61#ibcon#about to read 3, iclass 28, count 2 2006.173.23:52:31.64#ibcon#read 3, iclass 28, count 2 2006.173.23:52:31.64#ibcon#about to read 4, iclass 28, count 2 2006.173.23:52:31.64#ibcon#read 4, iclass 28, count 2 2006.173.23:52:31.64#ibcon#about to read 5, iclass 28, count 2 2006.173.23:52:31.64#ibcon#read 5, iclass 28, count 2 2006.173.23:52:31.64#ibcon#about to read 6, iclass 28, count 2 2006.173.23:52:31.64#ibcon#read 6, iclass 28, count 2 2006.173.23:52:31.64#ibcon#end of sib2, iclass 28, count 2 2006.173.23:52:31.64#ibcon#*after write, iclass 28, count 2 2006.173.23:52:31.64#ibcon#*before return 0, iclass 28, count 2 2006.173.23:52:31.64#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.173.23:52:31.64#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.173.23:52:31.64#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.173.23:52:31.64#ibcon#ireg 7 cls_cnt 0 2006.173.23:52:31.64#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.23:52:31.76#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.173.23:52:31.76#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.23:52:31.76#ibcon#enter wrdev, iclass 28, count 0 2006.173.23:52:31.76#ibcon#first serial, iclass 28, count 0 2006.173.23:52:31.76#ibcon#enter sib2, iclass 28, count 0 2006.173.23:52:31.76#ibcon#flushed, iclass 28, count 0 2006.173.23:52:31.76#ibcon#about to write, iclass 28, count 0 2006.173.23:52:31.76#ibcon#wrote, iclass 28, count 0 2006.173.23:52:31.76#ibcon#about to read 3, iclass 28, count 0 2006.173.23:52:31.78#ibcon#read 3, iclass 28, count 0 2006.173.23:52:31.78#ibcon#about to read 4, iclass 28, count 0 2006.173.23:52:31.78#ibcon#read 4, iclass 28, count 0 2006.173.23:52:31.78#ibcon#about to read 5, iclass 28, count 0 2006.173.23:52:31.78#ibcon#read 5, iclass 28, count 0 2006.173.23:52:31.78#ibcon#about to read 6, iclass 28, count 0 2006.173.23:52:31.78#ibcon#read 6, iclass 28, count 0 2006.173.23:52:31.78#ibcon#end of sib2, iclass 28, count 0 2006.173.23:52:31.78#ibcon#*mode == 0, iclass 28, count 0 2006.173.23:52:31.78#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.173.23:52:31.78#ibcon#[27=USB\r\n] 2006.173.23:52:31.78#ibcon#*before write, iclass 28, count 0 2006.173.23:52:31.78#ibcon#enter sib2, iclass 28, count 0 2006.173.23:52:31.78#ibcon#flushed, iclass 28, count 0 2006.173.23:52:31.78#ibcon#about to write, iclass 28, count 0 2006.173.23:52:31.78#ibcon#wrote, iclass 28, count 0 2006.173.23:52:31.78#ibcon#about to read 3, iclass 28, count 0 2006.173.23:52:31.81#ibcon#read 3, iclass 28, count 0 2006.173.23:52:31.81#ibcon#about to read 4, iclass 28, count 0 2006.173.23:52:31.81#ibcon#read 4, iclass 28, count 0 2006.173.23:52:31.81#ibcon#about to read 5, iclass 28, count 0 2006.173.23:52:31.81#ibcon#read 5, iclass 28, count 0 2006.173.23:52:31.81#ibcon#about to read 6, iclass 28, count 0 2006.173.23:52:31.81#ibcon#read 6, iclass 28, count 0 2006.173.23:52:31.81#ibcon#end of sib2, iclass 28, count 0 2006.173.23:52:31.81#ibcon#*after write, iclass 28, count 0 2006.173.23:52:31.81#ibcon#*before return 0, iclass 28, count 0 2006.173.23:52:31.81#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.173.23:52:31.81#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.173.23:52:31.81#ibcon#about to clear, iclass 28 cls_cnt 0 2006.173.23:52:31.81#ibcon#cleared, iclass 28 cls_cnt 0 2006.173.23:52:31.81$vck44/vblo=7,734.99 2006.173.23:52:31.81#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.173.23:52:31.81#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.173.23:52:31.81#ibcon#ireg 17 cls_cnt 0 2006.173.23:52:31.81#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.23:52:31.81#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.173.23:52:31.81#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.23:52:31.81#ibcon#enter wrdev, iclass 30, count 0 2006.173.23:52:31.81#ibcon#first serial, iclass 30, count 0 2006.173.23:52:31.81#ibcon#enter sib2, iclass 30, count 0 2006.173.23:52:31.81#ibcon#flushed, iclass 30, count 0 2006.173.23:52:31.81#ibcon#about to write, iclass 30, count 0 2006.173.23:52:31.81#ibcon#wrote, iclass 30, count 0 2006.173.23:52:31.81#ibcon#about to read 3, iclass 30, count 0 2006.173.23:52:31.83#ibcon#read 3, iclass 30, count 0 2006.173.23:52:31.83#ibcon#about to read 4, iclass 30, count 0 2006.173.23:52:31.83#ibcon#read 4, iclass 30, count 0 2006.173.23:52:31.83#ibcon#about to read 5, iclass 30, count 0 2006.173.23:52:31.83#ibcon#read 5, iclass 30, count 0 2006.173.23:52:31.83#ibcon#about to read 6, iclass 30, count 0 2006.173.23:52:31.83#ibcon#read 6, iclass 30, count 0 2006.173.23:52:31.83#ibcon#end of sib2, iclass 30, count 0 2006.173.23:52:31.83#ibcon#*mode == 0, iclass 30, count 0 2006.173.23:52:31.83#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.173.23:52:31.83#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.23:52:31.83#ibcon#*before write, iclass 30, count 0 2006.173.23:52:31.83#ibcon#enter sib2, iclass 30, count 0 2006.173.23:52:31.83#ibcon#flushed, iclass 30, count 0 2006.173.23:52:31.83#ibcon#about to write, iclass 30, count 0 2006.173.23:52:31.83#ibcon#wrote, iclass 30, count 0 2006.173.23:52:31.83#ibcon#about to read 3, iclass 30, count 0 2006.173.23:52:31.87#ibcon#read 3, iclass 30, count 0 2006.173.23:52:31.87#ibcon#about to read 4, iclass 30, count 0 2006.173.23:52:31.87#ibcon#read 4, iclass 30, count 0 2006.173.23:52:31.87#ibcon#about to read 5, iclass 30, count 0 2006.173.23:52:31.87#ibcon#read 5, iclass 30, count 0 2006.173.23:52:31.87#ibcon#about to read 6, iclass 30, count 0 2006.173.23:52:31.87#ibcon#read 6, iclass 30, count 0 2006.173.23:52:31.87#ibcon#end of sib2, iclass 30, count 0 2006.173.23:52:31.87#ibcon#*after write, iclass 30, count 0 2006.173.23:52:31.87#ibcon#*before return 0, iclass 30, count 0 2006.173.23:52:31.87#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.173.23:52:31.87#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.173.23:52:31.87#ibcon#about to clear, iclass 30 cls_cnt 0 2006.173.23:52:31.87#ibcon#cleared, iclass 30 cls_cnt 0 2006.173.23:52:31.87$vck44/vb=7,4 2006.173.23:52:31.87#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.173.23:52:31.87#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.173.23:52:31.87#ibcon#ireg 11 cls_cnt 2 2006.173.23:52:31.87#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.23:52:31.93#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.173.23:52:31.93#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.23:52:31.93#ibcon#enter wrdev, iclass 32, count 2 2006.173.23:52:31.93#ibcon#first serial, iclass 32, count 2 2006.173.23:52:31.93#ibcon#enter sib2, iclass 32, count 2 2006.173.23:52:31.93#ibcon#flushed, iclass 32, count 2 2006.173.23:52:31.93#ibcon#about to write, iclass 32, count 2 2006.173.23:52:31.93#ibcon#wrote, iclass 32, count 2 2006.173.23:52:31.93#ibcon#about to read 3, iclass 32, count 2 2006.173.23:52:31.95#ibcon#read 3, iclass 32, count 2 2006.173.23:52:31.95#ibcon#about to read 4, iclass 32, count 2 2006.173.23:52:31.95#ibcon#read 4, iclass 32, count 2 2006.173.23:52:31.95#ibcon#about to read 5, iclass 32, count 2 2006.173.23:52:31.95#ibcon#read 5, iclass 32, count 2 2006.173.23:52:31.95#ibcon#about to read 6, iclass 32, count 2 2006.173.23:52:31.95#ibcon#read 6, iclass 32, count 2 2006.173.23:52:31.95#ibcon#end of sib2, iclass 32, count 2 2006.173.23:52:31.95#ibcon#*mode == 0, iclass 32, count 2 2006.173.23:52:31.95#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.173.23:52:31.95#ibcon#[27=AT07-04\r\n] 2006.173.23:52:31.95#ibcon#*before write, iclass 32, count 2 2006.173.23:52:31.95#ibcon#enter sib2, iclass 32, count 2 2006.173.23:52:31.95#ibcon#flushed, iclass 32, count 2 2006.173.23:52:31.95#ibcon#about to write, iclass 32, count 2 2006.173.23:52:31.95#ibcon#wrote, iclass 32, count 2 2006.173.23:52:31.95#ibcon#about to read 3, iclass 32, count 2 2006.173.23:52:31.98#ibcon#read 3, iclass 32, count 2 2006.173.23:52:31.98#ibcon#about to read 4, iclass 32, count 2 2006.173.23:52:31.98#ibcon#read 4, iclass 32, count 2 2006.173.23:52:31.98#ibcon#about to read 5, iclass 32, count 2 2006.173.23:52:31.98#ibcon#read 5, iclass 32, count 2 2006.173.23:52:31.98#ibcon#about to read 6, iclass 32, count 2 2006.173.23:52:31.98#ibcon#read 6, iclass 32, count 2 2006.173.23:52:31.98#ibcon#end of sib2, iclass 32, count 2 2006.173.23:52:31.98#ibcon#*after write, iclass 32, count 2 2006.173.23:52:31.98#ibcon#*before return 0, iclass 32, count 2 2006.173.23:52:31.98#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.173.23:52:31.98#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.173.23:52:31.98#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.173.23:52:31.98#ibcon#ireg 7 cls_cnt 0 2006.173.23:52:31.98#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.23:52:32.10#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.173.23:52:32.10#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.23:52:32.10#ibcon#enter wrdev, iclass 32, count 0 2006.173.23:52:32.10#ibcon#first serial, iclass 32, count 0 2006.173.23:52:32.10#ibcon#enter sib2, iclass 32, count 0 2006.173.23:52:32.10#ibcon#flushed, iclass 32, count 0 2006.173.23:52:32.10#ibcon#about to write, iclass 32, count 0 2006.173.23:52:32.10#ibcon#wrote, iclass 32, count 0 2006.173.23:52:32.10#ibcon#about to read 3, iclass 32, count 0 2006.173.23:52:32.12#ibcon#read 3, iclass 32, count 0 2006.173.23:52:32.12#ibcon#about to read 4, iclass 32, count 0 2006.173.23:52:32.12#ibcon#read 4, iclass 32, count 0 2006.173.23:52:32.12#ibcon#about to read 5, iclass 32, count 0 2006.173.23:52:32.12#ibcon#read 5, iclass 32, count 0 2006.173.23:52:32.12#ibcon#about to read 6, iclass 32, count 0 2006.173.23:52:32.12#ibcon#read 6, iclass 32, count 0 2006.173.23:52:32.12#ibcon#end of sib2, iclass 32, count 0 2006.173.23:52:32.12#ibcon#*mode == 0, iclass 32, count 0 2006.173.23:52:32.12#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.173.23:52:32.12#ibcon#[27=USB\r\n] 2006.173.23:52:32.12#ibcon#*before write, iclass 32, count 0 2006.173.23:52:32.12#ibcon#enter sib2, iclass 32, count 0 2006.173.23:52:32.12#ibcon#flushed, iclass 32, count 0 2006.173.23:52:32.12#ibcon#about to write, iclass 32, count 0 2006.173.23:52:32.12#ibcon#wrote, iclass 32, count 0 2006.173.23:52:32.12#ibcon#about to read 3, iclass 32, count 0 2006.173.23:52:32.15#ibcon#read 3, iclass 32, count 0 2006.173.23:52:32.15#ibcon#about to read 4, iclass 32, count 0 2006.173.23:52:32.15#ibcon#read 4, iclass 32, count 0 2006.173.23:52:32.15#ibcon#about to read 5, iclass 32, count 0 2006.173.23:52:32.15#ibcon#read 5, iclass 32, count 0 2006.173.23:52:32.15#ibcon#about to read 6, iclass 32, count 0 2006.173.23:52:32.15#ibcon#read 6, iclass 32, count 0 2006.173.23:52:32.15#ibcon#end of sib2, iclass 32, count 0 2006.173.23:52:32.15#ibcon#*after write, iclass 32, count 0 2006.173.23:52:32.15#ibcon#*before return 0, iclass 32, count 0 2006.173.23:52:32.15#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.173.23:52:32.15#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.173.23:52:32.15#ibcon#about to clear, iclass 32 cls_cnt 0 2006.173.23:52:32.15#ibcon#cleared, iclass 32 cls_cnt 0 2006.173.23:52:32.15$vck44/vblo=8,744.99 2006.173.23:52:32.15#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.173.23:52:32.15#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.173.23:52:32.15#ibcon#ireg 17 cls_cnt 0 2006.173.23:52:32.15#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.23:52:32.15#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.173.23:52:32.15#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.23:52:32.15#ibcon#enter wrdev, iclass 34, count 0 2006.173.23:52:32.15#ibcon#first serial, iclass 34, count 0 2006.173.23:52:32.15#ibcon#enter sib2, iclass 34, count 0 2006.173.23:52:32.15#ibcon#flushed, iclass 34, count 0 2006.173.23:52:32.15#ibcon#about to write, iclass 34, count 0 2006.173.23:52:32.15#ibcon#wrote, iclass 34, count 0 2006.173.23:52:32.15#ibcon#about to read 3, iclass 34, count 0 2006.173.23:52:32.17#ibcon#read 3, iclass 34, count 0 2006.173.23:52:32.17#ibcon#about to read 4, iclass 34, count 0 2006.173.23:52:32.17#ibcon#read 4, iclass 34, count 0 2006.173.23:52:32.17#ibcon#about to read 5, iclass 34, count 0 2006.173.23:52:32.17#ibcon#read 5, iclass 34, count 0 2006.173.23:52:32.17#ibcon#about to read 6, iclass 34, count 0 2006.173.23:52:32.17#ibcon#read 6, iclass 34, count 0 2006.173.23:52:32.17#ibcon#end of sib2, iclass 34, count 0 2006.173.23:52:32.17#ibcon#*mode == 0, iclass 34, count 0 2006.173.23:52:32.17#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.173.23:52:32.17#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.23:52:32.17#ibcon#*before write, iclass 34, count 0 2006.173.23:52:32.17#ibcon#enter sib2, iclass 34, count 0 2006.173.23:52:32.17#ibcon#flushed, iclass 34, count 0 2006.173.23:52:32.17#ibcon#about to write, iclass 34, count 0 2006.173.23:52:32.17#ibcon#wrote, iclass 34, count 0 2006.173.23:52:32.17#ibcon#about to read 3, iclass 34, count 0 2006.173.23:52:32.21#ibcon#read 3, iclass 34, count 0 2006.173.23:52:32.21#ibcon#about to read 4, iclass 34, count 0 2006.173.23:52:32.21#ibcon#read 4, iclass 34, count 0 2006.173.23:52:32.21#ibcon#about to read 5, iclass 34, count 0 2006.173.23:52:32.21#ibcon#read 5, iclass 34, count 0 2006.173.23:52:32.21#ibcon#about to read 6, iclass 34, count 0 2006.173.23:52:32.21#ibcon#read 6, iclass 34, count 0 2006.173.23:52:32.21#ibcon#end of sib2, iclass 34, count 0 2006.173.23:52:32.21#ibcon#*after write, iclass 34, count 0 2006.173.23:52:32.21#ibcon#*before return 0, iclass 34, count 0 2006.173.23:52:32.21#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.173.23:52:32.21#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.173.23:52:32.21#ibcon#about to clear, iclass 34 cls_cnt 0 2006.173.23:52:32.21#ibcon#cleared, iclass 34 cls_cnt 0 2006.173.23:52:32.21$vck44/vb=8,4 2006.173.23:52:32.21#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.173.23:52:32.21#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.173.23:52:32.21#ibcon#ireg 11 cls_cnt 2 2006.173.23:52:32.21#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.23:52:32.27#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.173.23:52:32.27#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.23:52:32.27#ibcon#enter wrdev, iclass 36, count 2 2006.173.23:52:32.27#ibcon#first serial, iclass 36, count 2 2006.173.23:52:32.27#ibcon#enter sib2, iclass 36, count 2 2006.173.23:52:32.27#ibcon#flushed, iclass 36, count 2 2006.173.23:52:32.27#ibcon#about to write, iclass 36, count 2 2006.173.23:52:32.27#ibcon#wrote, iclass 36, count 2 2006.173.23:52:32.27#ibcon#about to read 3, iclass 36, count 2 2006.173.23:52:32.29#ibcon#read 3, iclass 36, count 2 2006.173.23:52:32.29#ibcon#about to read 4, iclass 36, count 2 2006.173.23:52:32.29#ibcon#read 4, iclass 36, count 2 2006.173.23:52:32.29#ibcon#about to read 5, iclass 36, count 2 2006.173.23:52:32.29#ibcon#read 5, iclass 36, count 2 2006.173.23:52:32.29#ibcon#about to read 6, iclass 36, count 2 2006.173.23:52:32.29#ibcon#read 6, iclass 36, count 2 2006.173.23:52:32.29#ibcon#end of sib2, iclass 36, count 2 2006.173.23:52:32.29#ibcon#*mode == 0, iclass 36, count 2 2006.173.23:52:32.29#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.173.23:52:32.29#ibcon#[27=AT08-04\r\n] 2006.173.23:52:32.29#ibcon#*before write, iclass 36, count 2 2006.173.23:52:32.29#ibcon#enter sib2, iclass 36, count 2 2006.173.23:52:32.29#ibcon#flushed, iclass 36, count 2 2006.173.23:52:32.29#ibcon#about to write, iclass 36, count 2 2006.173.23:52:32.29#ibcon#wrote, iclass 36, count 2 2006.173.23:52:32.29#ibcon#about to read 3, iclass 36, count 2 2006.173.23:52:32.32#ibcon#read 3, iclass 36, count 2 2006.173.23:52:32.32#ibcon#about to read 4, iclass 36, count 2 2006.173.23:52:32.32#ibcon#read 4, iclass 36, count 2 2006.173.23:52:32.32#ibcon#about to read 5, iclass 36, count 2 2006.173.23:52:32.32#ibcon#read 5, iclass 36, count 2 2006.173.23:52:32.32#ibcon#about to read 6, iclass 36, count 2 2006.173.23:52:32.32#ibcon#read 6, iclass 36, count 2 2006.173.23:52:32.32#ibcon#end of sib2, iclass 36, count 2 2006.173.23:52:32.32#ibcon#*after write, iclass 36, count 2 2006.173.23:52:32.32#ibcon#*before return 0, iclass 36, count 2 2006.173.23:52:32.32#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.173.23:52:32.32#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.173.23:52:32.32#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.173.23:52:32.32#ibcon#ireg 7 cls_cnt 0 2006.173.23:52:32.32#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.23:52:32.44#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.173.23:52:32.44#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.23:52:32.44#ibcon#enter wrdev, iclass 36, count 0 2006.173.23:52:32.44#ibcon#first serial, iclass 36, count 0 2006.173.23:52:32.44#ibcon#enter sib2, iclass 36, count 0 2006.173.23:52:32.44#ibcon#flushed, iclass 36, count 0 2006.173.23:52:32.44#ibcon#about to write, iclass 36, count 0 2006.173.23:52:32.44#ibcon#wrote, iclass 36, count 0 2006.173.23:52:32.44#ibcon#about to read 3, iclass 36, count 0 2006.173.23:52:32.46#ibcon#read 3, iclass 36, count 0 2006.173.23:52:32.46#ibcon#about to read 4, iclass 36, count 0 2006.173.23:52:32.46#ibcon#read 4, iclass 36, count 0 2006.173.23:52:32.46#ibcon#about to read 5, iclass 36, count 0 2006.173.23:52:32.46#ibcon#read 5, iclass 36, count 0 2006.173.23:52:32.46#ibcon#about to read 6, iclass 36, count 0 2006.173.23:52:32.46#ibcon#read 6, iclass 36, count 0 2006.173.23:52:32.46#ibcon#end of sib2, iclass 36, count 0 2006.173.23:52:32.46#ibcon#*mode == 0, iclass 36, count 0 2006.173.23:52:32.46#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.173.23:52:32.46#ibcon#[27=USB\r\n] 2006.173.23:52:32.46#ibcon#*before write, iclass 36, count 0 2006.173.23:52:32.46#ibcon#enter sib2, iclass 36, count 0 2006.173.23:52:32.46#ibcon#flushed, iclass 36, count 0 2006.173.23:52:32.46#ibcon#about to write, iclass 36, count 0 2006.173.23:52:32.46#ibcon#wrote, iclass 36, count 0 2006.173.23:52:32.46#ibcon#about to read 3, iclass 36, count 0 2006.173.23:52:32.49#ibcon#read 3, iclass 36, count 0 2006.173.23:52:32.49#ibcon#about to read 4, iclass 36, count 0 2006.173.23:52:32.49#ibcon#read 4, iclass 36, count 0 2006.173.23:52:32.49#ibcon#about to read 5, iclass 36, count 0 2006.173.23:52:32.49#ibcon#read 5, iclass 36, count 0 2006.173.23:52:32.49#ibcon#about to read 6, iclass 36, count 0 2006.173.23:52:32.49#ibcon#read 6, iclass 36, count 0 2006.173.23:52:32.49#ibcon#end of sib2, iclass 36, count 0 2006.173.23:52:32.49#ibcon#*after write, iclass 36, count 0 2006.173.23:52:32.49#ibcon#*before return 0, iclass 36, count 0 2006.173.23:52:32.49#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.173.23:52:32.49#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.173.23:52:32.49#ibcon#about to clear, iclass 36 cls_cnt 0 2006.173.23:52:32.49#ibcon#cleared, iclass 36 cls_cnt 0 2006.173.23:52:32.49$vck44/vabw=wide 2006.173.23:52:32.49#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.173.23:52:32.49#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.173.23:52:32.49#ibcon#ireg 8 cls_cnt 0 2006.173.23:52:32.49#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.23:52:32.49#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.173.23:52:32.49#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.23:52:32.49#ibcon#enter wrdev, iclass 38, count 0 2006.173.23:52:32.49#ibcon#first serial, iclass 38, count 0 2006.173.23:52:32.49#ibcon#enter sib2, iclass 38, count 0 2006.173.23:52:32.49#ibcon#flushed, iclass 38, count 0 2006.173.23:52:32.49#ibcon#about to write, iclass 38, count 0 2006.173.23:52:32.49#ibcon#wrote, iclass 38, count 0 2006.173.23:52:32.49#ibcon#about to read 3, iclass 38, count 0 2006.173.23:52:32.51#ibcon#read 3, iclass 38, count 0 2006.173.23:52:32.51#ibcon#about to read 4, iclass 38, count 0 2006.173.23:52:32.51#ibcon#read 4, iclass 38, count 0 2006.173.23:52:32.51#ibcon#about to read 5, iclass 38, count 0 2006.173.23:52:32.51#ibcon#read 5, iclass 38, count 0 2006.173.23:52:32.51#ibcon#about to read 6, iclass 38, count 0 2006.173.23:52:32.51#ibcon#read 6, iclass 38, count 0 2006.173.23:52:32.51#ibcon#end of sib2, iclass 38, count 0 2006.173.23:52:32.51#ibcon#*mode == 0, iclass 38, count 0 2006.173.23:52:32.51#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.173.23:52:32.51#ibcon#[25=BW32\r\n] 2006.173.23:52:32.51#ibcon#*before write, iclass 38, count 0 2006.173.23:52:32.51#ibcon#enter sib2, iclass 38, count 0 2006.173.23:52:32.51#ibcon#flushed, iclass 38, count 0 2006.173.23:52:32.51#ibcon#about to write, iclass 38, count 0 2006.173.23:52:32.51#ibcon#wrote, iclass 38, count 0 2006.173.23:52:32.51#ibcon#about to read 3, iclass 38, count 0 2006.173.23:52:32.54#ibcon#read 3, iclass 38, count 0 2006.173.23:52:32.54#ibcon#about to read 4, iclass 38, count 0 2006.173.23:52:32.54#ibcon#read 4, iclass 38, count 0 2006.173.23:52:32.54#ibcon#about to read 5, iclass 38, count 0 2006.173.23:52:32.54#ibcon#read 5, iclass 38, count 0 2006.173.23:52:32.54#ibcon#about to read 6, iclass 38, count 0 2006.173.23:52:32.54#ibcon#read 6, iclass 38, count 0 2006.173.23:52:32.54#ibcon#end of sib2, iclass 38, count 0 2006.173.23:52:32.54#ibcon#*after write, iclass 38, count 0 2006.173.23:52:32.54#ibcon#*before return 0, iclass 38, count 0 2006.173.23:52:32.54#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.173.23:52:32.54#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.173.23:52:32.54#ibcon#about to clear, iclass 38 cls_cnt 0 2006.173.23:52:32.54#ibcon#cleared, iclass 38 cls_cnt 0 2006.173.23:52:32.54$vck44/vbbw=wide 2006.173.23:52:32.54#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.173.23:52:32.54#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.173.23:52:32.54#ibcon#ireg 8 cls_cnt 0 2006.173.23:52:32.54#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.23:52:32.61#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.173.23:52:32.61#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.23:52:32.61#ibcon#enter wrdev, iclass 40, count 0 2006.173.23:52:32.61#ibcon#first serial, iclass 40, count 0 2006.173.23:52:32.61#ibcon#enter sib2, iclass 40, count 0 2006.173.23:52:32.61#ibcon#flushed, iclass 40, count 0 2006.173.23:52:32.61#ibcon#about to write, iclass 40, count 0 2006.173.23:52:32.61#ibcon#wrote, iclass 40, count 0 2006.173.23:52:32.61#ibcon#about to read 3, iclass 40, count 0 2006.173.23:52:32.63#ibcon#read 3, iclass 40, count 0 2006.173.23:52:32.63#ibcon#about to read 4, iclass 40, count 0 2006.173.23:52:32.63#ibcon#read 4, iclass 40, count 0 2006.173.23:52:32.63#ibcon#about to read 5, iclass 40, count 0 2006.173.23:52:32.63#ibcon#read 5, iclass 40, count 0 2006.173.23:52:32.63#ibcon#about to read 6, iclass 40, count 0 2006.173.23:52:32.63#ibcon#read 6, iclass 40, count 0 2006.173.23:52:32.63#ibcon#end of sib2, iclass 40, count 0 2006.173.23:52:32.63#ibcon#*mode == 0, iclass 40, count 0 2006.173.23:52:32.63#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.173.23:52:32.63#ibcon#[27=BW32\r\n] 2006.173.23:52:32.63#ibcon#*before write, iclass 40, count 0 2006.173.23:52:32.63#ibcon#enter sib2, iclass 40, count 0 2006.173.23:52:32.63#ibcon#flushed, iclass 40, count 0 2006.173.23:52:32.63#ibcon#about to write, iclass 40, count 0 2006.173.23:52:32.63#ibcon#wrote, iclass 40, count 0 2006.173.23:52:32.63#ibcon#about to read 3, iclass 40, count 0 2006.173.23:52:32.66#ibcon#read 3, iclass 40, count 0 2006.173.23:52:32.66#ibcon#about to read 4, iclass 40, count 0 2006.173.23:52:32.66#ibcon#read 4, iclass 40, count 0 2006.173.23:52:32.66#ibcon#about to read 5, iclass 40, count 0 2006.173.23:52:32.66#ibcon#read 5, iclass 40, count 0 2006.173.23:52:32.66#ibcon#about to read 6, iclass 40, count 0 2006.173.23:52:32.66#ibcon#read 6, iclass 40, count 0 2006.173.23:52:32.66#ibcon#end of sib2, iclass 40, count 0 2006.173.23:52:32.66#ibcon#*after write, iclass 40, count 0 2006.173.23:52:32.66#ibcon#*before return 0, iclass 40, count 0 2006.173.23:52:32.66#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.173.23:52:32.66#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.173.23:52:32.66#ibcon#about to clear, iclass 40 cls_cnt 0 2006.173.23:52:32.66#ibcon#cleared, iclass 40 cls_cnt 0 2006.173.23:52:32.66$setupk4/ifdk4 2006.173.23:52:32.66$ifdk4/lo= 2006.173.23:52:32.66$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.23:52:32.66$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.23:52:32.66$ifdk4/patch= 2006.173.23:52:32.66$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.23:52:32.66$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.23:52:32.66$setupk4/!*+20s 2006.173.23:52:34.50#abcon#<5=/12 0.6 1.3 23.87 821003.4\r\n> 2006.173.23:52:34.52#abcon#{5=INTERFACE CLEAR} 2006.173.23:52:34.58#abcon#[5=S1D000X0/0*\r\n] 2006.173.23:52:44.67#abcon#<5=/12 0.6 1.3 23.88 811003.4\r\n> 2006.173.23:52:44.69#abcon#{5=INTERFACE CLEAR} 2006.173.23:52:44.75#abcon#[5=S1D000X0/0*\r\n] 2006.173.23:52:46.14#trakl#Source acquired 2006.173.23:52:46.14#flagr#flagr/antenna,acquired 2006.173.23:52:47.17$setupk4/"tpicd 2006.173.23:52:47.17$setupk4/echo=off 2006.173.23:52:47.17$setupk4/xlog=off 2006.173.23:52:47.17:!2006.173.23:56:23 2006.173.23:56:23.00:preob 2006.173.23:56:23.14/onsource/TRACKING 2006.173.23:56:23.14:!2006.173.23:56:33 2006.173.23:56:33.00:"tape 2006.173.23:56:33.00:"st=record 2006.173.23:56:33.00:data_valid=on 2006.173.23:56:33.00:midob 2006.173.23:56:34.14/onsource/TRACKING 2006.173.23:56:34.14/wx/23.99,1003.4,82 2006.173.23:56:34.28/cable/+6.5085E-03 2006.173.23:56:35.37/va/01,07,usb,yes,34,37 2006.173.23:56:35.37/va/02,06,usb,yes,34,35 2006.173.23:56:35.37/va/03,05,usb,yes,43,45 2006.173.23:56:35.37/va/04,06,usb,yes,35,37 2006.173.23:56:35.37/va/05,04,usb,yes,27,28 2006.173.23:56:35.37/va/06,03,usb,yes,38,38 2006.173.23:56:35.37/va/07,04,usb,yes,31,32 2006.173.23:56:35.37/va/08,04,usb,yes,26,32 2006.173.23:56:35.60/valo/01,524.99,yes,locked 2006.173.23:56:35.60/valo/02,534.99,yes,locked 2006.173.23:56:35.60/valo/03,564.99,yes,locked 2006.173.23:56:35.60/valo/04,624.99,yes,locked 2006.173.23:56:35.60/valo/05,734.99,yes,locked 2006.173.23:56:35.60/valo/06,814.99,yes,locked 2006.173.23:56:35.60/valo/07,864.99,yes,locked 2006.173.23:56:35.60/valo/08,884.99,yes,locked 2006.173.23:56:36.69/vb/01,04,usb,yes,29,27 2006.173.23:56:36.69/vb/02,04,usb,yes,31,31 2006.173.23:56:36.69/vb/03,04,usb,yes,28,31 2006.173.23:56:36.69/vb/04,04,usb,yes,33,31 2006.173.23:56:36.69/vb/05,04,usb,yes,25,28 2006.173.23:56:36.69/vb/06,04,usb,yes,30,26 2006.173.23:56:36.69/vb/07,04,usb,yes,29,29 2006.173.23:56:36.69/vb/08,04,usb,yes,27,30 2006.173.23:56:36.92/vblo/01,629.99,yes,locked 2006.173.23:56:36.92/vblo/02,634.99,yes,locked 2006.173.23:56:36.92/vblo/03,649.99,yes,locked 2006.173.23:56:36.92/vblo/04,679.99,yes,locked 2006.173.23:56:36.92/vblo/05,709.99,yes,locked 2006.173.23:56:36.92/vblo/06,719.99,yes,locked 2006.173.23:56:36.92/vblo/07,734.99,yes,locked 2006.173.23:56:36.92/vblo/08,744.99,yes,locked 2006.173.23:56:37.07/vabw/8 2006.173.23:56:37.22/vbbw/8 2006.173.23:56:37.31/xfe/off,on,15.0 2006.173.23:56:37.69/ifatt/23,28,28,28 2006.173.23:56:38.08/fmout-gps/S +3.96E-07 2006.173.23:56:38.12:!2006.173.23:57:23 2006.173.23:57:23.00:data_valid=off 2006.173.23:57:23.00:"et 2006.173.23:57:23.00:!+3s 2006.173.23:57:26.01:"tape 2006.173.23:57:26.01:postob 2006.173.23:57:26.08/cable/+6.5087E-03 2006.173.23:57:26.08/wx/24.01,1003.4,83 2006.173.23:57:27.08/fmout-gps/S +3.95E-07 2006.173.23:57:27.08:scan_name=173-2359,jd0606,200 2006.173.23:57:27.08:source=0642+449,064632.03,445116.6,2000.0,ccw 2006.173.23:57:28.13#flagr#flagr/antenna,new-source 2006.173.23:57:28.13:checkk5 2006.173.23:57:28.49/chk_autoobs//k5ts1/ autoobs is running! 2006.173.23:57:28.88/chk_autoobs//k5ts2/ autoobs is running! 2006.173.23:57:29.28/chk_autoobs//k5ts3/ autoobs is running! 2006.173.23:57:29.67/chk_autoobs//k5ts4/ autoobs is running! 2006.173.23:57:30.06/chk_obsdata//k5ts1/T1732356??a.dat file size is correct (nominal:200MB, actual:196MB). 2006.173.23:57:30.49/chk_obsdata//k5ts2/T1732356??b.dat file size is correct (nominal:200MB, actual:196MB). 2006.173.23:57:30.88/chk_obsdata//k5ts3/T1732356??c.dat file size is correct (nominal:200MB, actual:196MB). 2006.173.23:57:31.30/chk_obsdata//k5ts4/T1732356??d.dat file size is correct (nominal:200MB, actual:196MB). 2006.173.23:57:32.02/k5log//k5ts1_log_newline 2006.173.23:57:32.72/k5log//k5ts2_log_newline 2006.173.23:57:33.43/k5log//k5ts3_log_newline 2006.173.23:57:34.13/k5log//k5ts4_log_newline 2006.173.23:57:34.16/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.173.23:57:34.16:setupk4=1 2006.173.23:57:34.16$setupk4/echo=on 2006.173.23:57:34.16$setupk4/pcalon 2006.173.23:57:34.16$pcalon/"no phase cal control is implemented here 2006.173.23:57:34.16$setupk4/"tpicd=stop 2006.173.23:57:34.16$setupk4/"rec=synch_on 2006.173.23:57:34.16$setupk4/"rec_mode=128 2006.173.23:57:34.16$setupk4/!* 2006.173.23:57:34.16$setupk4/recpk4 2006.173.23:57:34.16$recpk4/recpatch= 2006.173.23:57:34.16$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.173.23:57:34.16$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.173.23:57:34.16$setupk4/vck44 2006.173.23:57:34.16$vck44/valo=1,524.99 2006.173.23:57:34.16#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.23:57:34.16#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.23:57:34.16#ibcon#ireg 17 cls_cnt 0 2006.173.23:57:34.16#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.23:57:34.16#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.23:57:34.16#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.23:57:34.16#ibcon#enter wrdev, iclass 21, count 0 2006.173.23:57:34.16#ibcon#first serial, iclass 21, count 0 2006.173.23:57:34.16#ibcon#enter sib2, iclass 21, count 0 2006.173.23:57:34.16#ibcon#flushed, iclass 21, count 0 2006.173.23:57:34.16#ibcon#about to write, iclass 21, count 0 2006.173.23:57:34.16#ibcon#wrote, iclass 21, count 0 2006.173.23:57:34.16#ibcon#about to read 3, iclass 21, count 0 2006.173.23:57:34.18#ibcon#read 3, iclass 21, count 0 2006.173.23:57:34.18#ibcon#about to read 4, iclass 21, count 0 2006.173.23:57:34.18#ibcon#read 4, iclass 21, count 0 2006.173.23:57:34.18#ibcon#about to read 5, iclass 21, count 0 2006.173.23:57:34.18#ibcon#read 5, iclass 21, count 0 2006.173.23:57:34.18#ibcon#about to read 6, iclass 21, count 0 2006.173.23:57:34.18#ibcon#read 6, iclass 21, count 0 2006.173.23:57:34.18#ibcon#end of sib2, iclass 21, count 0 2006.173.23:57:34.18#ibcon#*mode == 0, iclass 21, count 0 2006.173.23:57:34.18#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.23:57:34.18#ibcon#[26=FRQ=01,524.99\r\n] 2006.173.23:57:34.18#ibcon#*before write, iclass 21, count 0 2006.173.23:57:34.18#ibcon#enter sib2, iclass 21, count 0 2006.173.23:57:34.18#ibcon#flushed, iclass 21, count 0 2006.173.23:57:34.18#ibcon#about to write, iclass 21, count 0 2006.173.23:57:34.18#ibcon#wrote, iclass 21, count 0 2006.173.23:57:34.18#ibcon#about to read 3, iclass 21, count 0 2006.173.23:57:34.23#ibcon#read 3, iclass 21, count 0 2006.173.23:57:34.23#ibcon#about to read 4, iclass 21, count 0 2006.173.23:57:34.23#ibcon#read 4, iclass 21, count 0 2006.173.23:57:34.23#ibcon#about to read 5, iclass 21, count 0 2006.173.23:57:34.23#ibcon#read 5, iclass 21, count 0 2006.173.23:57:34.23#ibcon#about to read 6, iclass 21, count 0 2006.173.23:57:34.23#ibcon#read 6, iclass 21, count 0 2006.173.23:57:34.23#ibcon#end of sib2, iclass 21, count 0 2006.173.23:57:34.23#ibcon#*after write, iclass 21, count 0 2006.173.23:57:34.23#ibcon#*before return 0, iclass 21, count 0 2006.173.23:57:34.23#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.23:57:34.23#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.23:57:34.23#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.23:57:34.23#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.23:57:34.23$vck44/va=1,7 2006.173.23:57:34.23#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.23:57:34.23#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.23:57:34.23#ibcon#ireg 11 cls_cnt 2 2006.173.23:57:34.23#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.23:57:34.23#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.23:57:34.23#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.23:57:34.23#ibcon#enter wrdev, iclass 23, count 2 2006.173.23:57:34.23#ibcon#first serial, iclass 23, count 2 2006.173.23:57:34.23#ibcon#enter sib2, iclass 23, count 2 2006.173.23:57:34.23#ibcon#flushed, iclass 23, count 2 2006.173.23:57:34.23#ibcon#about to write, iclass 23, count 2 2006.173.23:57:34.23#ibcon#wrote, iclass 23, count 2 2006.173.23:57:34.23#ibcon#about to read 3, iclass 23, count 2 2006.173.23:57:34.25#ibcon#read 3, iclass 23, count 2 2006.173.23:57:34.25#ibcon#about to read 4, iclass 23, count 2 2006.173.23:57:34.25#ibcon#read 4, iclass 23, count 2 2006.173.23:57:34.25#ibcon#about to read 5, iclass 23, count 2 2006.173.23:57:34.25#ibcon#read 5, iclass 23, count 2 2006.173.23:57:34.25#ibcon#about to read 6, iclass 23, count 2 2006.173.23:57:34.25#ibcon#read 6, iclass 23, count 2 2006.173.23:57:34.25#ibcon#end of sib2, iclass 23, count 2 2006.173.23:57:34.25#ibcon#*mode == 0, iclass 23, count 2 2006.173.23:57:34.25#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.23:57:34.25#ibcon#[25=AT01-07\r\n] 2006.173.23:57:34.25#ibcon#*before write, iclass 23, count 2 2006.173.23:57:34.25#ibcon#enter sib2, iclass 23, count 2 2006.173.23:57:34.25#ibcon#flushed, iclass 23, count 2 2006.173.23:57:34.25#ibcon#about to write, iclass 23, count 2 2006.173.23:57:34.25#ibcon#wrote, iclass 23, count 2 2006.173.23:57:34.25#ibcon#about to read 3, iclass 23, count 2 2006.173.23:57:34.28#ibcon#read 3, iclass 23, count 2 2006.173.23:57:34.28#ibcon#about to read 4, iclass 23, count 2 2006.173.23:57:34.28#ibcon#read 4, iclass 23, count 2 2006.173.23:57:34.28#ibcon#about to read 5, iclass 23, count 2 2006.173.23:57:34.28#ibcon#read 5, iclass 23, count 2 2006.173.23:57:34.28#ibcon#about to read 6, iclass 23, count 2 2006.173.23:57:34.28#ibcon#read 6, iclass 23, count 2 2006.173.23:57:34.28#ibcon#end of sib2, iclass 23, count 2 2006.173.23:57:34.28#ibcon#*after write, iclass 23, count 2 2006.173.23:57:34.28#ibcon#*before return 0, iclass 23, count 2 2006.173.23:57:34.28#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.23:57:34.28#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.23:57:34.28#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.23:57:34.28#ibcon#ireg 7 cls_cnt 0 2006.173.23:57:34.28#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.23:57:34.40#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.23:57:34.40#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.23:57:34.40#ibcon#enter wrdev, iclass 23, count 0 2006.173.23:57:34.40#ibcon#first serial, iclass 23, count 0 2006.173.23:57:34.40#ibcon#enter sib2, iclass 23, count 0 2006.173.23:57:34.40#ibcon#flushed, iclass 23, count 0 2006.173.23:57:34.40#ibcon#about to write, iclass 23, count 0 2006.173.23:57:34.40#ibcon#wrote, iclass 23, count 0 2006.173.23:57:34.40#ibcon#about to read 3, iclass 23, count 0 2006.173.23:57:34.42#ibcon#read 3, iclass 23, count 0 2006.173.23:57:34.42#ibcon#about to read 4, iclass 23, count 0 2006.173.23:57:34.42#ibcon#read 4, iclass 23, count 0 2006.173.23:57:34.42#ibcon#about to read 5, iclass 23, count 0 2006.173.23:57:34.42#ibcon#read 5, iclass 23, count 0 2006.173.23:57:34.42#ibcon#about to read 6, iclass 23, count 0 2006.173.23:57:34.42#ibcon#read 6, iclass 23, count 0 2006.173.23:57:34.42#ibcon#end of sib2, iclass 23, count 0 2006.173.23:57:34.42#ibcon#*mode == 0, iclass 23, count 0 2006.173.23:57:34.42#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.23:57:34.42#ibcon#[25=USB\r\n] 2006.173.23:57:34.42#ibcon#*before write, iclass 23, count 0 2006.173.23:57:34.42#ibcon#enter sib2, iclass 23, count 0 2006.173.23:57:34.42#ibcon#flushed, iclass 23, count 0 2006.173.23:57:34.42#ibcon#about to write, iclass 23, count 0 2006.173.23:57:34.42#ibcon#wrote, iclass 23, count 0 2006.173.23:57:34.42#ibcon#about to read 3, iclass 23, count 0 2006.173.23:57:34.45#ibcon#read 3, iclass 23, count 0 2006.173.23:57:34.45#ibcon#about to read 4, iclass 23, count 0 2006.173.23:57:34.45#ibcon#read 4, iclass 23, count 0 2006.173.23:57:34.45#ibcon#about to read 5, iclass 23, count 0 2006.173.23:57:34.45#ibcon#read 5, iclass 23, count 0 2006.173.23:57:34.45#ibcon#about to read 6, iclass 23, count 0 2006.173.23:57:34.45#ibcon#read 6, iclass 23, count 0 2006.173.23:57:34.45#ibcon#end of sib2, iclass 23, count 0 2006.173.23:57:34.45#ibcon#*after write, iclass 23, count 0 2006.173.23:57:34.45#ibcon#*before return 0, iclass 23, count 0 2006.173.23:57:34.45#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.23:57:34.45#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.23:57:34.45#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.23:57:34.45#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.23:57:34.45$vck44/valo=2,534.99 2006.173.23:57:34.45#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.23:57:34.45#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.23:57:34.45#ibcon#ireg 17 cls_cnt 0 2006.173.23:57:34.45#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.23:57:34.45#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.23:57:34.45#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.23:57:34.45#ibcon#enter wrdev, iclass 25, count 0 2006.173.23:57:34.45#ibcon#first serial, iclass 25, count 0 2006.173.23:57:34.45#ibcon#enter sib2, iclass 25, count 0 2006.173.23:57:34.45#ibcon#flushed, iclass 25, count 0 2006.173.23:57:34.45#ibcon#about to write, iclass 25, count 0 2006.173.23:57:34.45#ibcon#wrote, iclass 25, count 0 2006.173.23:57:34.45#ibcon#about to read 3, iclass 25, count 0 2006.173.23:57:34.47#ibcon#read 3, iclass 25, count 0 2006.173.23:57:34.47#ibcon#about to read 4, iclass 25, count 0 2006.173.23:57:34.47#ibcon#read 4, iclass 25, count 0 2006.173.23:57:34.47#ibcon#about to read 5, iclass 25, count 0 2006.173.23:57:34.47#ibcon#read 5, iclass 25, count 0 2006.173.23:57:34.47#ibcon#about to read 6, iclass 25, count 0 2006.173.23:57:34.47#ibcon#read 6, iclass 25, count 0 2006.173.23:57:34.47#ibcon#end of sib2, iclass 25, count 0 2006.173.23:57:34.47#ibcon#*mode == 0, iclass 25, count 0 2006.173.23:57:34.47#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.23:57:34.47#ibcon#[26=FRQ=02,534.99\r\n] 2006.173.23:57:34.47#ibcon#*before write, iclass 25, count 0 2006.173.23:57:34.47#ibcon#enter sib2, iclass 25, count 0 2006.173.23:57:34.47#ibcon#flushed, iclass 25, count 0 2006.173.23:57:34.47#ibcon#about to write, iclass 25, count 0 2006.173.23:57:34.47#ibcon#wrote, iclass 25, count 0 2006.173.23:57:34.47#ibcon#about to read 3, iclass 25, count 0 2006.173.23:57:34.51#ibcon#read 3, iclass 25, count 0 2006.173.23:57:34.51#ibcon#about to read 4, iclass 25, count 0 2006.173.23:57:34.51#ibcon#read 4, iclass 25, count 0 2006.173.23:57:34.51#ibcon#about to read 5, iclass 25, count 0 2006.173.23:57:34.51#ibcon#read 5, iclass 25, count 0 2006.173.23:57:34.51#ibcon#about to read 6, iclass 25, count 0 2006.173.23:57:34.51#ibcon#read 6, iclass 25, count 0 2006.173.23:57:34.51#ibcon#end of sib2, iclass 25, count 0 2006.173.23:57:34.51#ibcon#*after write, iclass 25, count 0 2006.173.23:57:34.51#ibcon#*before return 0, iclass 25, count 0 2006.173.23:57:34.51#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.23:57:34.51#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.23:57:34.51#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.23:57:34.51#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.23:57:34.51$vck44/va=2,6 2006.173.23:57:34.51#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.23:57:34.51#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.23:57:34.51#ibcon#ireg 11 cls_cnt 2 2006.173.23:57:34.51#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.23:57:34.57#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.23:57:34.57#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.23:57:34.57#ibcon#enter wrdev, iclass 27, count 2 2006.173.23:57:34.57#ibcon#first serial, iclass 27, count 2 2006.173.23:57:34.57#ibcon#enter sib2, iclass 27, count 2 2006.173.23:57:34.57#ibcon#flushed, iclass 27, count 2 2006.173.23:57:34.57#ibcon#about to write, iclass 27, count 2 2006.173.23:57:34.57#ibcon#wrote, iclass 27, count 2 2006.173.23:57:34.57#ibcon#about to read 3, iclass 27, count 2 2006.173.23:57:34.59#ibcon#read 3, iclass 27, count 2 2006.173.23:57:34.59#ibcon#about to read 4, iclass 27, count 2 2006.173.23:57:34.59#ibcon#read 4, iclass 27, count 2 2006.173.23:57:34.59#ibcon#about to read 5, iclass 27, count 2 2006.173.23:57:34.59#ibcon#read 5, iclass 27, count 2 2006.173.23:57:34.59#ibcon#about to read 6, iclass 27, count 2 2006.173.23:57:34.59#ibcon#read 6, iclass 27, count 2 2006.173.23:57:34.59#ibcon#end of sib2, iclass 27, count 2 2006.173.23:57:34.59#ibcon#*mode == 0, iclass 27, count 2 2006.173.23:57:34.59#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.23:57:34.59#ibcon#[25=AT02-06\r\n] 2006.173.23:57:34.59#ibcon#*before write, iclass 27, count 2 2006.173.23:57:34.59#ibcon#enter sib2, iclass 27, count 2 2006.173.23:57:34.59#ibcon#flushed, iclass 27, count 2 2006.173.23:57:34.59#ibcon#about to write, iclass 27, count 2 2006.173.23:57:34.59#ibcon#wrote, iclass 27, count 2 2006.173.23:57:34.59#ibcon#about to read 3, iclass 27, count 2 2006.173.23:57:34.62#ibcon#read 3, iclass 27, count 2 2006.173.23:57:34.62#ibcon#about to read 4, iclass 27, count 2 2006.173.23:57:34.62#ibcon#read 4, iclass 27, count 2 2006.173.23:57:34.62#ibcon#about to read 5, iclass 27, count 2 2006.173.23:57:34.62#ibcon#read 5, iclass 27, count 2 2006.173.23:57:34.62#ibcon#about to read 6, iclass 27, count 2 2006.173.23:57:34.62#ibcon#read 6, iclass 27, count 2 2006.173.23:57:34.62#ibcon#end of sib2, iclass 27, count 2 2006.173.23:57:34.62#ibcon#*after write, iclass 27, count 2 2006.173.23:57:34.62#ibcon#*before return 0, iclass 27, count 2 2006.173.23:57:34.62#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.23:57:34.62#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.23:57:34.62#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.23:57:34.62#ibcon#ireg 7 cls_cnt 0 2006.173.23:57:34.62#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.23:57:34.74#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.23:57:34.74#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.23:57:34.74#ibcon#enter wrdev, iclass 27, count 0 2006.173.23:57:34.74#ibcon#first serial, iclass 27, count 0 2006.173.23:57:34.74#ibcon#enter sib2, iclass 27, count 0 2006.173.23:57:34.74#ibcon#flushed, iclass 27, count 0 2006.173.23:57:34.74#ibcon#about to write, iclass 27, count 0 2006.173.23:57:34.74#ibcon#wrote, iclass 27, count 0 2006.173.23:57:34.74#ibcon#about to read 3, iclass 27, count 0 2006.173.23:57:34.76#ibcon#read 3, iclass 27, count 0 2006.173.23:57:34.76#ibcon#about to read 4, iclass 27, count 0 2006.173.23:57:34.76#ibcon#read 4, iclass 27, count 0 2006.173.23:57:34.76#ibcon#about to read 5, iclass 27, count 0 2006.173.23:57:34.76#ibcon#read 5, iclass 27, count 0 2006.173.23:57:34.76#ibcon#about to read 6, iclass 27, count 0 2006.173.23:57:34.76#ibcon#read 6, iclass 27, count 0 2006.173.23:57:34.76#ibcon#end of sib2, iclass 27, count 0 2006.173.23:57:34.76#ibcon#*mode == 0, iclass 27, count 0 2006.173.23:57:34.76#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.23:57:34.76#ibcon#[25=USB\r\n] 2006.173.23:57:34.76#ibcon#*before write, iclass 27, count 0 2006.173.23:57:34.76#ibcon#enter sib2, iclass 27, count 0 2006.173.23:57:34.76#ibcon#flushed, iclass 27, count 0 2006.173.23:57:34.76#ibcon#about to write, iclass 27, count 0 2006.173.23:57:34.76#ibcon#wrote, iclass 27, count 0 2006.173.23:57:34.76#ibcon#about to read 3, iclass 27, count 0 2006.173.23:57:34.79#ibcon#read 3, iclass 27, count 0 2006.173.23:57:34.79#ibcon#about to read 4, iclass 27, count 0 2006.173.23:57:34.79#ibcon#read 4, iclass 27, count 0 2006.173.23:57:34.79#ibcon#about to read 5, iclass 27, count 0 2006.173.23:57:34.79#ibcon#read 5, iclass 27, count 0 2006.173.23:57:34.79#ibcon#about to read 6, iclass 27, count 0 2006.173.23:57:34.79#ibcon#read 6, iclass 27, count 0 2006.173.23:57:34.79#ibcon#end of sib2, iclass 27, count 0 2006.173.23:57:34.79#ibcon#*after write, iclass 27, count 0 2006.173.23:57:34.79#ibcon#*before return 0, iclass 27, count 0 2006.173.23:57:34.79#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.23:57:34.79#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.23:57:34.79#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.23:57:34.79#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.23:57:34.79$vck44/valo=3,564.99 2006.173.23:57:34.79#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.23:57:34.79#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.23:57:34.79#ibcon#ireg 17 cls_cnt 0 2006.173.23:57:34.79#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.23:57:34.79#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.23:57:34.79#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.23:57:34.79#ibcon#enter wrdev, iclass 29, count 0 2006.173.23:57:34.79#ibcon#first serial, iclass 29, count 0 2006.173.23:57:34.79#ibcon#enter sib2, iclass 29, count 0 2006.173.23:57:34.79#ibcon#flushed, iclass 29, count 0 2006.173.23:57:34.79#ibcon#about to write, iclass 29, count 0 2006.173.23:57:34.79#ibcon#wrote, iclass 29, count 0 2006.173.23:57:34.79#ibcon#about to read 3, iclass 29, count 0 2006.173.23:57:34.81#ibcon#read 3, iclass 29, count 0 2006.173.23:57:34.81#ibcon#about to read 4, iclass 29, count 0 2006.173.23:57:34.81#ibcon#read 4, iclass 29, count 0 2006.173.23:57:34.81#ibcon#about to read 5, iclass 29, count 0 2006.173.23:57:34.81#ibcon#read 5, iclass 29, count 0 2006.173.23:57:34.81#ibcon#about to read 6, iclass 29, count 0 2006.173.23:57:34.81#ibcon#read 6, iclass 29, count 0 2006.173.23:57:34.81#ibcon#end of sib2, iclass 29, count 0 2006.173.23:57:34.81#ibcon#*mode == 0, iclass 29, count 0 2006.173.23:57:34.81#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.23:57:34.81#ibcon#[26=FRQ=03,564.99\r\n] 2006.173.23:57:34.81#ibcon#*before write, iclass 29, count 0 2006.173.23:57:34.81#ibcon#enter sib2, iclass 29, count 0 2006.173.23:57:34.81#ibcon#flushed, iclass 29, count 0 2006.173.23:57:34.81#ibcon#about to write, iclass 29, count 0 2006.173.23:57:34.81#ibcon#wrote, iclass 29, count 0 2006.173.23:57:34.81#ibcon#about to read 3, iclass 29, count 0 2006.173.23:57:34.85#ibcon#read 3, iclass 29, count 0 2006.173.23:57:34.85#ibcon#about to read 4, iclass 29, count 0 2006.173.23:57:34.85#ibcon#read 4, iclass 29, count 0 2006.173.23:57:34.85#ibcon#about to read 5, iclass 29, count 0 2006.173.23:57:34.85#ibcon#read 5, iclass 29, count 0 2006.173.23:57:34.85#ibcon#about to read 6, iclass 29, count 0 2006.173.23:57:34.85#ibcon#read 6, iclass 29, count 0 2006.173.23:57:34.85#ibcon#end of sib2, iclass 29, count 0 2006.173.23:57:34.85#ibcon#*after write, iclass 29, count 0 2006.173.23:57:34.85#ibcon#*before return 0, iclass 29, count 0 2006.173.23:57:34.85#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.23:57:34.85#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.23:57:34.85#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.23:57:34.85#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.23:57:34.85$vck44/va=3,5 2006.173.23:57:34.85#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.23:57:34.85#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.23:57:34.85#ibcon#ireg 11 cls_cnt 2 2006.173.23:57:34.85#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.23:57:34.91#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.23:57:34.91#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.23:57:34.91#ibcon#enter wrdev, iclass 31, count 2 2006.173.23:57:34.91#ibcon#first serial, iclass 31, count 2 2006.173.23:57:34.91#ibcon#enter sib2, iclass 31, count 2 2006.173.23:57:34.91#ibcon#flushed, iclass 31, count 2 2006.173.23:57:34.91#ibcon#about to write, iclass 31, count 2 2006.173.23:57:34.91#ibcon#wrote, iclass 31, count 2 2006.173.23:57:34.91#ibcon#about to read 3, iclass 31, count 2 2006.173.23:57:34.93#ibcon#read 3, iclass 31, count 2 2006.173.23:57:34.93#ibcon#about to read 4, iclass 31, count 2 2006.173.23:57:34.93#ibcon#read 4, iclass 31, count 2 2006.173.23:57:34.93#ibcon#about to read 5, iclass 31, count 2 2006.173.23:57:34.93#ibcon#read 5, iclass 31, count 2 2006.173.23:57:34.93#ibcon#about to read 6, iclass 31, count 2 2006.173.23:57:34.93#ibcon#read 6, iclass 31, count 2 2006.173.23:57:34.93#ibcon#end of sib2, iclass 31, count 2 2006.173.23:57:34.93#ibcon#*mode == 0, iclass 31, count 2 2006.173.23:57:34.93#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.23:57:34.93#ibcon#[25=AT03-05\r\n] 2006.173.23:57:34.93#ibcon#*before write, iclass 31, count 2 2006.173.23:57:34.93#ibcon#enter sib2, iclass 31, count 2 2006.173.23:57:34.93#ibcon#flushed, iclass 31, count 2 2006.173.23:57:34.93#ibcon#about to write, iclass 31, count 2 2006.173.23:57:34.93#ibcon#wrote, iclass 31, count 2 2006.173.23:57:34.93#ibcon#about to read 3, iclass 31, count 2 2006.173.23:57:34.96#ibcon#read 3, iclass 31, count 2 2006.173.23:57:34.96#ibcon#about to read 4, iclass 31, count 2 2006.173.23:57:34.96#ibcon#read 4, iclass 31, count 2 2006.173.23:57:34.96#ibcon#about to read 5, iclass 31, count 2 2006.173.23:57:34.96#ibcon#read 5, iclass 31, count 2 2006.173.23:57:34.96#ibcon#about to read 6, iclass 31, count 2 2006.173.23:57:34.96#ibcon#read 6, iclass 31, count 2 2006.173.23:57:34.96#ibcon#end of sib2, iclass 31, count 2 2006.173.23:57:34.96#ibcon#*after write, iclass 31, count 2 2006.173.23:57:34.96#ibcon#*before return 0, iclass 31, count 2 2006.173.23:57:34.96#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.23:57:34.96#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.23:57:34.96#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.23:57:34.96#ibcon#ireg 7 cls_cnt 0 2006.173.23:57:34.96#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.23:57:35.08#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.23:57:35.08#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.23:57:35.08#ibcon#enter wrdev, iclass 31, count 0 2006.173.23:57:35.08#ibcon#first serial, iclass 31, count 0 2006.173.23:57:35.08#ibcon#enter sib2, iclass 31, count 0 2006.173.23:57:35.08#ibcon#flushed, iclass 31, count 0 2006.173.23:57:35.08#ibcon#about to write, iclass 31, count 0 2006.173.23:57:35.08#ibcon#wrote, iclass 31, count 0 2006.173.23:57:35.08#ibcon#about to read 3, iclass 31, count 0 2006.173.23:57:35.10#ibcon#read 3, iclass 31, count 0 2006.173.23:57:35.10#ibcon#about to read 4, iclass 31, count 0 2006.173.23:57:35.10#ibcon#read 4, iclass 31, count 0 2006.173.23:57:35.10#ibcon#about to read 5, iclass 31, count 0 2006.173.23:57:35.10#ibcon#read 5, iclass 31, count 0 2006.173.23:57:35.10#ibcon#about to read 6, iclass 31, count 0 2006.173.23:57:35.10#ibcon#read 6, iclass 31, count 0 2006.173.23:57:35.10#ibcon#end of sib2, iclass 31, count 0 2006.173.23:57:35.10#ibcon#*mode == 0, iclass 31, count 0 2006.173.23:57:35.10#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.23:57:35.10#ibcon#[25=USB\r\n] 2006.173.23:57:35.10#ibcon#*before write, iclass 31, count 0 2006.173.23:57:35.10#ibcon#enter sib2, iclass 31, count 0 2006.173.23:57:35.10#ibcon#flushed, iclass 31, count 0 2006.173.23:57:35.10#ibcon#about to write, iclass 31, count 0 2006.173.23:57:35.10#ibcon#wrote, iclass 31, count 0 2006.173.23:57:35.10#ibcon#about to read 3, iclass 31, count 0 2006.173.23:57:35.13#ibcon#read 3, iclass 31, count 0 2006.173.23:57:35.13#ibcon#about to read 4, iclass 31, count 0 2006.173.23:57:35.13#ibcon#read 4, iclass 31, count 0 2006.173.23:57:35.13#ibcon#about to read 5, iclass 31, count 0 2006.173.23:57:35.13#ibcon#read 5, iclass 31, count 0 2006.173.23:57:35.13#ibcon#about to read 6, iclass 31, count 0 2006.173.23:57:35.13#ibcon#read 6, iclass 31, count 0 2006.173.23:57:35.13#ibcon#end of sib2, iclass 31, count 0 2006.173.23:57:35.13#ibcon#*after write, iclass 31, count 0 2006.173.23:57:35.13#ibcon#*before return 0, iclass 31, count 0 2006.173.23:57:35.13#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.23:57:35.13#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.23:57:35.13#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.23:57:35.13#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.23:57:35.13$vck44/valo=4,624.99 2006.173.23:57:35.13#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.23:57:35.13#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.23:57:35.13#ibcon#ireg 17 cls_cnt 0 2006.173.23:57:35.13#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.23:57:35.13#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.23:57:35.13#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.23:57:35.13#ibcon#enter wrdev, iclass 33, count 0 2006.173.23:57:35.13#ibcon#first serial, iclass 33, count 0 2006.173.23:57:35.13#ibcon#enter sib2, iclass 33, count 0 2006.173.23:57:35.13#ibcon#flushed, iclass 33, count 0 2006.173.23:57:35.13#ibcon#about to write, iclass 33, count 0 2006.173.23:57:35.13#ibcon#wrote, iclass 33, count 0 2006.173.23:57:35.13#ibcon#about to read 3, iclass 33, count 0 2006.173.23:57:35.15#ibcon#read 3, iclass 33, count 0 2006.173.23:57:35.15#ibcon#about to read 4, iclass 33, count 0 2006.173.23:57:35.15#ibcon#read 4, iclass 33, count 0 2006.173.23:57:35.15#ibcon#about to read 5, iclass 33, count 0 2006.173.23:57:35.15#ibcon#read 5, iclass 33, count 0 2006.173.23:57:35.15#ibcon#about to read 6, iclass 33, count 0 2006.173.23:57:35.15#ibcon#read 6, iclass 33, count 0 2006.173.23:57:35.15#ibcon#end of sib2, iclass 33, count 0 2006.173.23:57:35.15#ibcon#*mode == 0, iclass 33, count 0 2006.173.23:57:35.15#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.23:57:35.15#ibcon#[26=FRQ=04,624.99\r\n] 2006.173.23:57:35.15#ibcon#*before write, iclass 33, count 0 2006.173.23:57:35.15#ibcon#enter sib2, iclass 33, count 0 2006.173.23:57:35.15#ibcon#flushed, iclass 33, count 0 2006.173.23:57:35.15#ibcon#about to write, iclass 33, count 0 2006.173.23:57:35.15#ibcon#wrote, iclass 33, count 0 2006.173.23:57:35.15#ibcon#about to read 3, iclass 33, count 0 2006.173.23:57:35.19#ibcon#read 3, iclass 33, count 0 2006.173.23:57:35.19#ibcon#about to read 4, iclass 33, count 0 2006.173.23:57:35.19#ibcon#read 4, iclass 33, count 0 2006.173.23:57:35.19#ibcon#about to read 5, iclass 33, count 0 2006.173.23:57:35.19#ibcon#read 5, iclass 33, count 0 2006.173.23:57:35.19#ibcon#about to read 6, iclass 33, count 0 2006.173.23:57:35.19#ibcon#read 6, iclass 33, count 0 2006.173.23:57:35.19#ibcon#end of sib2, iclass 33, count 0 2006.173.23:57:35.19#ibcon#*after write, iclass 33, count 0 2006.173.23:57:35.19#ibcon#*before return 0, iclass 33, count 0 2006.173.23:57:35.19#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.23:57:35.19#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.23:57:35.19#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.23:57:35.19#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.23:57:35.19$vck44/va=4,6 2006.173.23:57:35.19#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.23:57:35.19#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.23:57:35.19#ibcon#ireg 11 cls_cnt 2 2006.173.23:57:35.19#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.23:57:35.25#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.23:57:35.25#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.23:57:35.25#ibcon#enter wrdev, iclass 35, count 2 2006.173.23:57:35.25#ibcon#first serial, iclass 35, count 2 2006.173.23:57:35.25#ibcon#enter sib2, iclass 35, count 2 2006.173.23:57:35.25#ibcon#flushed, iclass 35, count 2 2006.173.23:57:35.25#ibcon#about to write, iclass 35, count 2 2006.173.23:57:35.25#ibcon#wrote, iclass 35, count 2 2006.173.23:57:35.25#ibcon#about to read 3, iclass 35, count 2 2006.173.23:57:35.27#ibcon#read 3, iclass 35, count 2 2006.173.23:57:35.27#ibcon#about to read 4, iclass 35, count 2 2006.173.23:57:35.27#ibcon#read 4, iclass 35, count 2 2006.173.23:57:35.27#ibcon#about to read 5, iclass 35, count 2 2006.173.23:57:35.27#ibcon#read 5, iclass 35, count 2 2006.173.23:57:35.27#ibcon#about to read 6, iclass 35, count 2 2006.173.23:57:35.27#ibcon#read 6, iclass 35, count 2 2006.173.23:57:35.27#ibcon#end of sib2, iclass 35, count 2 2006.173.23:57:35.27#ibcon#*mode == 0, iclass 35, count 2 2006.173.23:57:35.27#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.23:57:35.27#ibcon#[25=AT04-06\r\n] 2006.173.23:57:35.27#ibcon#*before write, iclass 35, count 2 2006.173.23:57:35.27#ibcon#enter sib2, iclass 35, count 2 2006.173.23:57:35.27#ibcon#flushed, iclass 35, count 2 2006.173.23:57:35.27#ibcon#about to write, iclass 35, count 2 2006.173.23:57:35.27#ibcon#wrote, iclass 35, count 2 2006.173.23:57:35.27#ibcon#about to read 3, iclass 35, count 2 2006.173.23:57:35.30#ibcon#read 3, iclass 35, count 2 2006.173.23:57:35.30#ibcon#about to read 4, iclass 35, count 2 2006.173.23:57:35.30#ibcon#read 4, iclass 35, count 2 2006.173.23:57:35.30#ibcon#about to read 5, iclass 35, count 2 2006.173.23:57:35.30#ibcon#read 5, iclass 35, count 2 2006.173.23:57:35.30#ibcon#about to read 6, iclass 35, count 2 2006.173.23:57:35.30#ibcon#read 6, iclass 35, count 2 2006.173.23:57:35.30#ibcon#end of sib2, iclass 35, count 2 2006.173.23:57:35.30#ibcon#*after write, iclass 35, count 2 2006.173.23:57:35.30#ibcon#*before return 0, iclass 35, count 2 2006.173.23:57:35.30#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.23:57:35.30#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.23:57:35.30#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.23:57:35.30#ibcon#ireg 7 cls_cnt 0 2006.173.23:57:35.30#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.23:57:35.42#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.23:57:35.42#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.23:57:35.42#ibcon#enter wrdev, iclass 35, count 0 2006.173.23:57:35.42#ibcon#first serial, iclass 35, count 0 2006.173.23:57:35.42#ibcon#enter sib2, iclass 35, count 0 2006.173.23:57:35.42#ibcon#flushed, iclass 35, count 0 2006.173.23:57:35.42#ibcon#about to write, iclass 35, count 0 2006.173.23:57:35.42#ibcon#wrote, iclass 35, count 0 2006.173.23:57:35.42#ibcon#about to read 3, iclass 35, count 0 2006.173.23:57:35.44#ibcon#read 3, iclass 35, count 0 2006.173.23:57:35.44#ibcon#about to read 4, iclass 35, count 0 2006.173.23:57:35.44#ibcon#read 4, iclass 35, count 0 2006.173.23:57:35.44#ibcon#about to read 5, iclass 35, count 0 2006.173.23:57:35.44#ibcon#read 5, iclass 35, count 0 2006.173.23:57:35.44#ibcon#about to read 6, iclass 35, count 0 2006.173.23:57:35.44#ibcon#read 6, iclass 35, count 0 2006.173.23:57:35.44#ibcon#end of sib2, iclass 35, count 0 2006.173.23:57:35.44#ibcon#*mode == 0, iclass 35, count 0 2006.173.23:57:35.44#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.23:57:35.44#ibcon#[25=USB\r\n] 2006.173.23:57:35.44#ibcon#*before write, iclass 35, count 0 2006.173.23:57:35.44#ibcon#enter sib2, iclass 35, count 0 2006.173.23:57:35.44#ibcon#flushed, iclass 35, count 0 2006.173.23:57:35.44#ibcon#about to write, iclass 35, count 0 2006.173.23:57:35.44#ibcon#wrote, iclass 35, count 0 2006.173.23:57:35.44#ibcon#about to read 3, iclass 35, count 0 2006.173.23:57:35.47#ibcon#read 3, iclass 35, count 0 2006.173.23:57:35.47#ibcon#about to read 4, iclass 35, count 0 2006.173.23:57:35.47#ibcon#read 4, iclass 35, count 0 2006.173.23:57:35.47#ibcon#about to read 5, iclass 35, count 0 2006.173.23:57:35.47#ibcon#read 5, iclass 35, count 0 2006.173.23:57:35.47#ibcon#about to read 6, iclass 35, count 0 2006.173.23:57:35.47#ibcon#read 6, iclass 35, count 0 2006.173.23:57:35.47#ibcon#end of sib2, iclass 35, count 0 2006.173.23:57:35.47#ibcon#*after write, iclass 35, count 0 2006.173.23:57:35.47#ibcon#*before return 0, iclass 35, count 0 2006.173.23:57:35.47#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.23:57:35.47#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.23:57:35.47#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.23:57:35.47#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.23:57:35.47$vck44/valo=5,734.99 2006.173.23:57:35.47#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.23:57:35.47#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.23:57:35.47#ibcon#ireg 17 cls_cnt 0 2006.173.23:57:35.47#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.23:57:35.47#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.23:57:35.47#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.23:57:35.47#ibcon#enter wrdev, iclass 37, count 0 2006.173.23:57:35.47#ibcon#first serial, iclass 37, count 0 2006.173.23:57:35.47#ibcon#enter sib2, iclass 37, count 0 2006.173.23:57:35.47#ibcon#flushed, iclass 37, count 0 2006.173.23:57:35.47#ibcon#about to write, iclass 37, count 0 2006.173.23:57:35.47#ibcon#wrote, iclass 37, count 0 2006.173.23:57:35.47#ibcon#about to read 3, iclass 37, count 0 2006.173.23:57:35.49#ibcon#read 3, iclass 37, count 0 2006.173.23:57:35.49#ibcon#about to read 4, iclass 37, count 0 2006.173.23:57:35.49#ibcon#read 4, iclass 37, count 0 2006.173.23:57:35.49#ibcon#about to read 5, iclass 37, count 0 2006.173.23:57:35.49#ibcon#read 5, iclass 37, count 0 2006.173.23:57:35.49#ibcon#about to read 6, iclass 37, count 0 2006.173.23:57:35.49#ibcon#read 6, iclass 37, count 0 2006.173.23:57:35.49#ibcon#end of sib2, iclass 37, count 0 2006.173.23:57:35.49#ibcon#*mode == 0, iclass 37, count 0 2006.173.23:57:35.49#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.23:57:35.49#ibcon#[26=FRQ=05,734.99\r\n] 2006.173.23:57:35.49#ibcon#*before write, iclass 37, count 0 2006.173.23:57:35.49#ibcon#enter sib2, iclass 37, count 0 2006.173.23:57:35.49#ibcon#flushed, iclass 37, count 0 2006.173.23:57:35.49#ibcon#about to write, iclass 37, count 0 2006.173.23:57:35.49#ibcon#wrote, iclass 37, count 0 2006.173.23:57:35.49#ibcon#about to read 3, iclass 37, count 0 2006.173.23:57:35.53#ibcon#read 3, iclass 37, count 0 2006.173.23:57:35.53#ibcon#about to read 4, iclass 37, count 0 2006.173.23:57:35.53#ibcon#read 4, iclass 37, count 0 2006.173.23:57:35.53#ibcon#about to read 5, iclass 37, count 0 2006.173.23:57:35.53#ibcon#read 5, iclass 37, count 0 2006.173.23:57:35.53#ibcon#about to read 6, iclass 37, count 0 2006.173.23:57:35.53#ibcon#read 6, iclass 37, count 0 2006.173.23:57:35.53#ibcon#end of sib2, iclass 37, count 0 2006.173.23:57:35.53#ibcon#*after write, iclass 37, count 0 2006.173.23:57:35.53#ibcon#*before return 0, iclass 37, count 0 2006.173.23:57:35.53#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.23:57:35.53#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.23:57:35.53#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.23:57:35.53#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.23:57:35.53$vck44/va=5,4 2006.173.23:57:35.53#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.23:57:35.53#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.23:57:35.53#ibcon#ireg 11 cls_cnt 2 2006.173.23:57:35.53#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.23:57:35.59#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.23:57:35.59#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.23:57:35.59#ibcon#enter wrdev, iclass 39, count 2 2006.173.23:57:35.59#ibcon#first serial, iclass 39, count 2 2006.173.23:57:35.59#ibcon#enter sib2, iclass 39, count 2 2006.173.23:57:35.59#ibcon#flushed, iclass 39, count 2 2006.173.23:57:35.59#ibcon#about to write, iclass 39, count 2 2006.173.23:57:35.59#ibcon#wrote, iclass 39, count 2 2006.173.23:57:35.59#ibcon#about to read 3, iclass 39, count 2 2006.173.23:57:35.61#ibcon#read 3, iclass 39, count 2 2006.173.23:57:35.61#ibcon#about to read 4, iclass 39, count 2 2006.173.23:57:35.61#ibcon#read 4, iclass 39, count 2 2006.173.23:57:35.61#ibcon#about to read 5, iclass 39, count 2 2006.173.23:57:35.61#ibcon#read 5, iclass 39, count 2 2006.173.23:57:35.61#ibcon#about to read 6, iclass 39, count 2 2006.173.23:57:35.61#ibcon#read 6, iclass 39, count 2 2006.173.23:57:35.61#ibcon#end of sib2, iclass 39, count 2 2006.173.23:57:35.61#ibcon#*mode == 0, iclass 39, count 2 2006.173.23:57:35.61#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.23:57:35.61#ibcon#[25=AT05-04\r\n] 2006.173.23:57:35.61#ibcon#*before write, iclass 39, count 2 2006.173.23:57:35.61#ibcon#enter sib2, iclass 39, count 2 2006.173.23:57:35.61#ibcon#flushed, iclass 39, count 2 2006.173.23:57:35.61#ibcon#about to write, iclass 39, count 2 2006.173.23:57:35.61#ibcon#wrote, iclass 39, count 2 2006.173.23:57:35.61#ibcon#about to read 3, iclass 39, count 2 2006.173.23:57:35.64#ibcon#read 3, iclass 39, count 2 2006.173.23:57:35.64#ibcon#about to read 4, iclass 39, count 2 2006.173.23:57:35.64#ibcon#read 4, iclass 39, count 2 2006.173.23:57:35.64#ibcon#about to read 5, iclass 39, count 2 2006.173.23:57:35.64#ibcon#read 5, iclass 39, count 2 2006.173.23:57:35.64#ibcon#about to read 6, iclass 39, count 2 2006.173.23:57:35.64#ibcon#read 6, iclass 39, count 2 2006.173.23:57:35.64#ibcon#end of sib2, iclass 39, count 2 2006.173.23:57:35.64#ibcon#*after write, iclass 39, count 2 2006.173.23:57:35.64#ibcon#*before return 0, iclass 39, count 2 2006.173.23:57:35.64#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.23:57:35.64#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.23:57:35.64#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.23:57:35.64#ibcon#ireg 7 cls_cnt 0 2006.173.23:57:35.64#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.23:57:35.76#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.23:57:35.76#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.23:57:35.76#ibcon#enter wrdev, iclass 39, count 0 2006.173.23:57:35.76#ibcon#first serial, iclass 39, count 0 2006.173.23:57:35.76#ibcon#enter sib2, iclass 39, count 0 2006.173.23:57:35.76#ibcon#flushed, iclass 39, count 0 2006.173.23:57:35.76#ibcon#about to write, iclass 39, count 0 2006.173.23:57:35.76#ibcon#wrote, iclass 39, count 0 2006.173.23:57:35.76#ibcon#about to read 3, iclass 39, count 0 2006.173.23:57:35.78#ibcon#read 3, iclass 39, count 0 2006.173.23:57:35.78#ibcon#about to read 4, iclass 39, count 0 2006.173.23:57:35.78#ibcon#read 4, iclass 39, count 0 2006.173.23:57:35.78#ibcon#about to read 5, iclass 39, count 0 2006.173.23:57:35.78#ibcon#read 5, iclass 39, count 0 2006.173.23:57:35.78#ibcon#about to read 6, iclass 39, count 0 2006.173.23:57:35.78#ibcon#read 6, iclass 39, count 0 2006.173.23:57:35.78#ibcon#end of sib2, iclass 39, count 0 2006.173.23:57:35.78#ibcon#*mode == 0, iclass 39, count 0 2006.173.23:57:35.78#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.23:57:35.78#ibcon#[25=USB\r\n] 2006.173.23:57:35.78#ibcon#*before write, iclass 39, count 0 2006.173.23:57:35.78#ibcon#enter sib2, iclass 39, count 0 2006.173.23:57:35.78#ibcon#flushed, iclass 39, count 0 2006.173.23:57:35.78#ibcon#about to write, iclass 39, count 0 2006.173.23:57:35.78#ibcon#wrote, iclass 39, count 0 2006.173.23:57:35.78#ibcon#about to read 3, iclass 39, count 0 2006.173.23:57:35.81#ibcon#read 3, iclass 39, count 0 2006.173.23:57:35.81#ibcon#about to read 4, iclass 39, count 0 2006.173.23:57:35.81#ibcon#read 4, iclass 39, count 0 2006.173.23:57:35.81#ibcon#about to read 5, iclass 39, count 0 2006.173.23:57:35.81#ibcon#read 5, iclass 39, count 0 2006.173.23:57:35.81#ibcon#about to read 6, iclass 39, count 0 2006.173.23:57:35.81#ibcon#read 6, iclass 39, count 0 2006.173.23:57:35.81#ibcon#end of sib2, iclass 39, count 0 2006.173.23:57:35.81#ibcon#*after write, iclass 39, count 0 2006.173.23:57:35.81#ibcon#*before return 0, iclass 39, count 0 2006.173.23:57:35.81#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.23:57:35.81#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.23:57:35.81#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.23:57:35.81#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.23:57:35.81$vck44/valo=6,814.99 2006.173.23:57:35.81#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.23:57:35.81#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.23:57:35.81#ibcon#ireg 17 cls_cnt 0 2006.173.23:57:35.81#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.23:57:35.81#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.23:57:35.81#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.23:57:35.81#ibcon#enter wrdev, iclass 3, count 0 2006.173.23:57:35.81#ibcon#first serial, iclass 3, count 0 2006.173.23:57:35.81#ibcon#enter sib2, iclass 3, count 0 2006.173.23:57:35.81#ibcon#flushed, iclass 3, count 0 2006.173.23:57:35.81#ibcon#about to write, iclass 3, count 0 2006.173.23:57:35.81#ibcon#wrote, iclass 3, count 0 2006.173.23:57:35.81#ibcon#about to read 3, iclass 3, count 0 2006.173.23:57:35.83#ibcon#read 3, iclass 3, count 0 2006.173.23:57:35.83#ibcon#about to read 4, iclass 3, count 0 2006.173.23:57:35.83#ibcon#read 4, iclass 3, count 0 2006.173.23:57:35.83#ibcon#about to read 5, iclass 3, count 0 2006.173.23:57:35.83#ibcon#read 5, iclass 3, count 0 2006.173.23:57:35.83#ibcon#about to read 6, iclass 3, count 0 2006.173.23:57:35.83#ibcon#read 6, iclass 3, count 0 2006.173.23:57:35.83#ibcon#end of sib2, iclass 3, count 0 2006.173.23:57:35.83#ibcon#*mode == 0, iclass 3, count 0 2006.173.23:57:35.83#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.23:57:35.83#ibcon#[26=FRQ=06,814.99\r\n] 2006.173.23:57:35.83#ibcon#*before write, iclass 3, count 0 2006.173.23:57:35.83#ibcon#enter sib2, iclass 3, count 0 2006.173.23:57:35.83#ibcon#flushed, iclass 3, count 0 2006.173.23:57:35.83#ibcon#about to write, iclass 3, count 0 2006.173.23:57:35.83#ibcon#wrote, iclass 3, count 0 2006.173.23:57:35.83#ibcon#about to read 3, iclass 3, count 0 2006.173.23:57:35.87#ibcon#read 3, iclass 3, count 0 2006.173.23:57:35.87#ibcon#about to read 4, iclass 3, count 0 2006.173.23:57:35.87#ibcon#read 4, iclass 3, count 0 2006.173.23:57:35.87#ibcon#about to read 5, iclass 3, count 0 2006.173.23:57:35.87#ibcon#read 5, iclass 3, count 0 2006.173.23:57:35.87#ibcon#about to read 6, iclass 3, count 0 2006.173.23:57:35.87#ibcon#read 6, iclass 3, count 0 2006.173.23:57:35.87#ibcon#end of sib2, iclass 3, count 0 2006.173.23:57:35.87#ibcon#*after write, iclass 3, count 0 2006.173.23:57:35.87#ibcon#*before return 0, iclass 3, count 0 2006.173.23:57:35.87#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.23:57:35.87#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.23:57:35.87#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.23:57:35.87#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.23:57:35.87$vck44/va=6,3 2006.173.23:57:35.87#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.23:57:35.87#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.23:57:35.87#ibcon#ireg 11 cls_cnt 2 2006.173.23:57:35.87#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.23:57:35.93#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.23:57:35.93#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.23:57:35.93#ibcon#enter wrdev, iclass 5, count 2 2006.173.23:57:35.93#ibcon#first serial, iclass 5, count 2 2006.173.23:57:35.93#ibcon#enter sib2, iclass 5, count 2 2006.173.23:57:35.93#ibcon#flushed, iclass 5, count 2 2006.173.23:57:35.93#ibcon#about to write, iclass 5, count 2 2006.173.23:57:35.93#ibcon#wrote, iclass 5, count 2 2006.173.23:57:35.93#ibcon#about to read 3, iclass 5, count 2 2006.173.23:57:35.95#ibcon#read 3, iclass 5, count 2 2006.173.23:57:35.95#ibcon#about to read 4, iclass 5, count 2 2006.173.23:57:35.95#ibcon#read 4, iclass 5, count 2 2006.173.23:57:35.95#ibcon#about to read 5, iclass 5, count 2 2006.173.23:57:35.95#ibcon#read 5, iclass 5, count 2 2006.173.23:57:35.95#ibcon#about to read 6, iclass 5, count 2 2006.173.23:57:35.95#ibcon#read 6, iclass 5, count 2 2006.173.23:57:35.95#ibcon#end of sib2, iclass 5, count 2 2006.173.23:57:35.95#ibcon#*mode == 0, iclass 5, count 2 2006.173.23:57:35.95#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.23:57:35.95#ibcon#[25=AT06-03\r\n] 2006.173.23:57:35.95#ibcon#*before write, iclass 5, count 2 2006.173.23:57:35.95#ibcon#enter sib2, iclass 5, count 2 2006.173.23:57:35.95#ibcon#flushed, iclass 5, count 2 2006.173.23:57:35.95#ibcon#about to write, iclass 5, count 2 2006.173.23:57:35.95#ibcon#wrote, iclass 5, count 2 2006.173.23:57:35.95#ibcon#about to read 3, iclass 5, count 2 2006.173.23:57:35.98#ibcon#read 3, iclass 5, count 2 2006.173.23:57:35.98#ibcon#about to read 4, iclass 5, count 2 2006.173.23:57:35.98#ibcon#read 4, iclass 5, count 2 2006.173.23:57:35.98#ibcon#about to read 5, iclass 5, count 2 2006.173.23:57:35.98#ibcon#read 5, iclass 5, count 2 2006.173.23:57:35.98#ibcon#about to read 6, iclass 5, count 2 2006.173.23:57:35.98#ibcon#read 6, iclass 5, count 2 2006.173.23:57:35.98#ibcon#end of sib2, iclass 5, count 2 2006.173.23:57:35.98#ibcon#*after write, iclass 5, count 2 2006.173.23:57:35.98#ibcon#*before return 0, iclass 5, count 2 2006.173.23:57:35.98#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.23:57:35.98#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.23:57:35.98#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.23:57:35.98#ibcon#ireg 7 cls_cnt 0 2006.173.23:57:35.98#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.23:57:36.10#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.23:57:36.10#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.23:57:36.10#ibcon#enter wrdev, iclass 5, count 0 2006.173.23:57:36.10#ibcon#first serial, iclass 5, count 0 2006.173.23:57:36.10#ibcon#enter sib2, iclass 5, count 0 2006.173.23:57:36.10#ibcon#flushed, iclass 5, count 0 2006.173.23:57:36.10#ibcon#about to write, iclass 5, count 0 2006.173.23:57:36.10#ibcon#wrote, iclass 5, count 0 2006.173.23:57:36.10#ibcon#about to read 3, iclass 5, count 0 2006.173.23:57:36.12#ibcon#read 3, iclass 5, count 0 2006.173.23:57:36.12#ibcon#about to read 4, iclass 5, count 0 2006.173.23:57:36.12#ibcon#read 4, iclass 5, count 0 2006.173.23:57:36.12#ibcon#about to read 5, iclass 5, count 0 2006.173.23:57:36.12#ibcon#read 5, iclass 5, count 0 2006.173.23:57:36.12#ibcon#about to read 6, iclass 5, count 0 2006.173.23:57:36.12#ibcon#read 6, iclass 5, count 0 2006.173.23:57:36.12#ibcon#end of sib2, iclass 5, count 0 2006.173.23:57:36.12#ibcon#*mode == 0, iclass 5, count 0 2006.173.23:57:36.12#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.23:57:36.12#ibcon#[25=USB\r\n] 2006.173.23:57:36.12#ibcon#*before write, iclass 5, count 0 2006.173.23:57:36.12#ibcon#enter sib2, iclass 5, count 0 2006.173.23:57:36.12#ibcon#flushed, iclass 5, count 0 2006.173.23:57:36.12#ibcon#about to write, iclass 5, count 0 2006.173.23:57:36.12#ibcon#wrote, iclass 5, count 0 2006.173.23:57:36.12#ibcon#about to read 3, iclass 5, count 0 2006.173.23:57:36.15#ibcon#read 3, iclass 5, count 0 2006.173.23:57:36.15#ibcon#about to read 4, iclass 5, count 0 2006.173.23:57:36.15#ibcon#read 4, iclass 5, count 0 2006.173.23:57:36.15#ibcon#about to read 5, iclass 5, count 0 2006.173.23:57:36.15#ibcon#read 5, iclass 5, count 0 2006.173.23:57:36.15#ibcon#about to read 6, iclass 5, count 0 2006.173.23:57:36.15#ibcon#read 6, iclass 5, count 0 2006.173.23:57:36.15#ibcon#end of sib2, iclass 5, count 0 2006.173.23:57:36.15#ibcon#*after write, iclass 5, count 0 2006.173.23:57:36.15#ibcon#*before return 0, iclass 5, count 0 2006.173.23:57:36.15#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.23:57:36.15#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.23:57:36.15#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.23:57:36.15#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.23:57:36.15$vck44/valo=7,864.99 2006.173.23:57:36.15#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.23:57:36.15#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.23:57:36.15#ibcon#ireg 17 cls_cnt 0 2006.173.23:57:36.15#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.23:57:36.15#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.23:57:36.15#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.23:57:36.15#ibcon#enter wrdev, iclass 7, count 0 2006.173.23:57:36.15#ibcon#first serial, iclass 7, count 0 2006.173.23:57:36.15#ibcon#enter sib2, iclass 7, count 0 2006.173.23:57:36.15#ibcon#flushed, iclass 7, count 0 2006.173.23:57:36.15#ibcon#about to write, iclass 7, count 0 2006.173.23:57:36.15#ibcon#wrote, iclass 7, count 0 2006.173.23:57:36.15#ibcon#about to read 3, iclass 7, count 0 2006.173.23:57:36.17#ibcon#read 3, iclass 7, count 0 2006.173.23:57:36.17#ibcon#about to read 4, iclass 7, count 0 2006.173.23:57:36.17#ibcon#read 4, iclass 7, count 0 2006.173.23:57:36.17#ibcon#about to read 5, iclass 7, count 0 2006.173.23:57:36.17#ibcon#read 5, iclass 7, count 0 2006.173.23:57:36.17#ibcon#about to read 6, iclass 7, count 0 2006.173.23:57:36.17#ibcon#read 6, iclass 7, count 0 2006.173.23:57:36.17#ibcon#end of sib2, iclass 7, count 0 2006.173.23:57:36.17#ibcon#*mode == 0, iclass 7, count 0 2006.173.23:57:36.17#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.23:57:36.17#ibcon#[26=FRQ=07,864.99\r\n] 2006.173.23:57:36.17#ibcon#*before write, iclass 7, count 0 2006.173.23:57:36.17#ibcon#enter sib2, iclass 7, count 0 2006.173.23:57:36.17#ibcon#flushed, iclass 7, count 0 2006.173.23:57:36.17#ibcon#about to write, iclass 7, count 0 2006.173.23:57:36.17#ibcon#wrote, iclass 7, count 0 2006.173.23:57:36.17#ibcon#about to read 3, iclass 7, count 0 2006.173.23:57:36.21#ibcon#read 3, iclass 7, count 0 2006.173.23:57:36.21#ibcon#about to read 4, iclass 7, count 0 2006.173.23:57:36.21#ibcon#read 4, iclass 7, count 0 2006.173.23:57:36.21#ibcon#about to read 5, iclass 7, count 0 2006.173.23:57:36.21#ibcon#read 5, iclass 7, count 0 2006.173.23:57:36.21#ibcon#about to read 6, iclass 7, count 0 2006.173.23:57:36.21#ibcon#read 6, iclass 7, count 0 2006.173.23:57:36.21#ibcon#end of sib2, iclass 7, count 0 2006.173.23:57:36.21#ibcon#*after write, iclass 7, count 0 2006.173.23:57:36.21#ibcon#*before return 0, iclass 7, count 0 2006.173.23:57:36.21#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.23:57:36.21#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.23:57:36.21#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.23:57:36.21#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.23:57:36.21$vck44/va=7,4 2006.173.23:57:36.21#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.23:57:36.21#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.23:57:36.21#ibcon#ireg 11 cls_cnt 2 2006.173.23:57:36.21#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.23:57:36.27#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.23:57:36.27#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.23:57:36.27#ibcon#enter wrdev, iclass 11, count 2 2006.173.23:57:36.27#ibcon#first serial, iclass 11, count 2 2006.173.23:57:36.27#ibcon#enter sib2, iclass 11, count 2 2006.173.23:57:36.27#ibcon#flushed, iclass 11, count 2 2006.173.23:57:36.27#ibcon#about to write, iclass 11, count 2 2006.173.23:57:36.27#ibcon#wrote, iclass 11, count 2 2006.173.23:57:36.27#ibcon#about to read 3, iclass 11, count 2 2006.173.23:57:36.29#ibcon#read 3, iclass 11, count 2 2006.173.23:57:36.29#ibcon#about to read 4, iclass 11, count 2 2006.173.23:57:36.29#ibcon#read 4, iclass 11, count 2 2006.173.23:57:36.29#ibcon#about to read 5, iclass 11, count 2 2006.173.23:57:36.29#ibcon#read 5, iclass 11, count 2 2006.173.23:57:36.29#ibcon#about to read 6, iclass 11, count 2 2006.173.23:57:36.29#ibcon#read 6, iclass 11, count 2 2006.173.23:57:36.29#ibcon#end of sib2, iclass 11, count 2 2006.173.23:57:36.29#ibcon#*mode == 0, iclass 11, count 2 2006.173.23:57:36.29#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.23:57:36.29#ibcon#[25=AT07-04\r\n] 2006.173.23:57:36.29#ibcon#*before write, iclass 11, count 2 2006.173.23:57:36.29#ibcon#enter sib2, iclass 11, count 2 2006.173.23:57:36.29#ibcon#flushed, iclass 11, count 2 2006.173.23:57:36.29#ibcon#about to write, iclass 11, count 2 2006.173.23:57:36.29#ibcon#wrote, iclass 11, count 2 2006.173.23:57:36.29#ibcon#about to read 3, iclass 11, count 2 2006.173.23:57:36.32#ibcon#read 3, iclass 11, count 2 2006.173.23:57:36.32#ibcon#about to read 4, iclass 11, count 2 2006.173.23:57:36.32#ibcon#read 4, iclass 11, count 2 2006.173.23:57:36.32#ibcon#about to read 5, iclass 11, count 2 2006.173.23:57:36.32#ibcon#read 5, iclass 11, count 2 2006.173.23:57:36.32#ibcon#about to read 6, iclass 11, count 2 2006.173.23:57:36.32#ibcon#read 6, iclass 11, count 2 2006.173.23:57:36.32#ibcon#end of sib2, iclass 11, count 2 2006.173.23:57:36.32#ibcon#*after write, iclass 11, count 2 2006.173.23:57:36.32#ibcon#*before return 0, iclass 11, count 2 2006.173.23:57:36.32#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.23:57:36.32#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.23:57:36.32#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.23:57:36.32#ibcon#ireg 7 cls_cnt 0 2006.173.23:57:36.32#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.23:57:36.44#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.23:57:36.44#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.23:57:36.44#ibcon#enter wrdev, iclass 11, count 0 2006.173.23:57:36.44#ibcon#first serial, iclass 11, count 0 2006.173.23:57:36.44#ibcon#enter sib2, iclass 11, count 0 2006.173.23:57:36.44#ibcon#flushed, iclass 11, count 0 2006.173.23:57:36.44#ibcon#about to write, iclass 11, count 0 2006.173.23:57:36.44#ibcon#wrote, iclass 11, count 0 2006.173.23:57:36.44#ibcon#about to read 3, iclass 11, count 0 2006.173.23:57:36.46#ibcon#read 3, iclass 11, count 0 2006.173.23:57:36.46#ibcon#about to read 4, iclass 11, count 0 2006.173.23:57:36.46#ibcon#read 4, iclass 11, count 0 2006.173.23:57:36.46#ibcon#about to read 5, iclass 11, count 0 2006.173.23:57:36.46#ibcon#read 5, iclass 11, count 0 2006.173.23:57:36.46#ibcon#about to read 6, iclass 11, count 0 2006.173.23:57:36.46#ibcon#read 6, iclass 11, count 0 2006.173.23:57:36.46#ibcon#end of sib2, iclass 11, count 0 2006.173.23:57:36.46#ibcon#*mode == 0, iclass 11, count 0 2006.173.23:57:36.46#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.23:57:36.46#ibcon#[25=USB\r\n] 2006.173.23:57:36.46#ibcon#*before write, iclass 11, count 0 2006.173.23:57:36.46#ibcon#enter sib2, iclass 11, count 0 2006.173.23:57:36.46#ibcon#flushed, iclass 11, count 0 2006.173.23:57:36.46#ibcon#about to write, iclass 11, count 0 2006.173.23:57:36.46#ibcon#wrote, iclass 11, count 0 2006.173.23:57:36.46#ibcon#about to read 3, iclass 11, count 0 2006.173.23:57:36.49#ibcon#read 3, iclass 11, count 0 2006.173.23:57:36.49#ibcon#about to read 4, iclass 11, count 0 2006.173.23:57:36.49#ibcon#read 4, iclass 11, count 0 2006.173.23:57:36.49#ibcon#about to read 5, iclass 11, count 0 2006.173.23:57:36.49#ibcon#read 5, iclass 11, count 0 2006.173.23:57:36.49#ibcon#about to read 6, iclass 11, count 0 2006.173.23:57:36.49#ibcon#read 6, iclass 11, count 0 2006.173.23:57:36.49#ibcon#end of sib2, iclass 11, count 0 2006.173.23:57:36.49#ibcon#*after write, iclass 11, count 0 2006.173.23:57:36.49#ibcon#*before return 0, iclass 11, count 0 2006.173.23:57:36.49#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.23:57:36.49#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.23:57:36.49#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.23:57:36.49#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.23:57:36.49$vck44/valo=8,884.99 2006.173.23:57:36.49#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.23:57:36.49#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.23:57:36.49#ibcon#ireg 17 cls_cnt 0 2006.173.23:57:36.49#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.23:57:36.49#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.23:57:36.49#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.23:57:36.49#ibcon#enter wrdev, iclass 13, count 0 2006.173.23:57:36.49#ibcon#first serial, iclass 13, count 0 2006.173.23:57:36.49#ibcon#enter sib2, iclass 13, count 0 2006.173.23:57:36.49#ibcon#flushed, iclass 13, count 0 2006.173.23:57:36.49#ibcon#about to write, iclass 13, count 0 2006.173.23:57:36.49#ibcon#wrote, iclass 13, count 0 2006.173.23:57:36.49#ibcon#about to read 3, iclass 13, count 0 2006.173.23:57:36.51#ibcon#read 3, iclass 13, count 0 2006.173.23:57:36.51#ibcon#about to read 4, iclass 13, count 0 2006.173.23:57:36.51#ibcon#read 4, iclass 13, count 0 2006.173.23:57:36.51#ibcon#about to read 5, iclass 13, count 0 2006.173.23:57:36.51#ibcon#read 5, iclass 13, count 0 2006.173.23:57:36.51#ibcon#about to read 6, iclass 13, count 0 2006.173.23:57:36.51#ibcon#read 6, iclass 13, count 0 2006.173.23:57:36.51#ibcon#end of sib2, iclass 13, count 0 2006.173.23:57:36.51#ibcon#*mode == 0, iclass 13, count 0 2006.173.23:57:36.51#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.23:57:36.51#ibcon#[26=FRQ=08,884.99\r\n] 2006.173.23:57:36.51#ibcon#*before write, iclass 13, count 0 2006.173.23:57:36.51#ibcon#enter sib2, iclass 13, count 0 2006.173.23:57:36.51#ibcon#flushed, iclass 13, count 0 2006.173.23:57:36.51#ibcon#about to write, iclass 13, count 0 2006.173.23:57:36.51#ibcon#wrote, iclass 13, count 0 2006.173.23:57:36.51#ibcon#about to read 3, iclass 13, count 0 2006.173.23:57:36.55#ibcon#read 3, iclass 13, count 0 2006.173.23:57:36.55#ibcon#about to read 4, iclass 13, count 0 2006.173.23:57:36.55#ibcon#read 4, iclass 13, count 0 2006.173.23:57:36.55#ibcon#about to read 5, iclass 13, count 0 2006.173.23:57:36.55#ibcon#read 5, iclass 13, count 0 2006.173.23:57:36.55#ibcon#about to read 6, iclass 13, count 0 2006.173.23:57:36.55#ibcon#read 6, iclass 13, count 0 2006.173.23:57:36.55#ibcon#end of sib2, iclass 13, count 0 2006.173.23:57:36.55#ibcon#*after write, iclass 13, count 0 2006.173.23:57:36.55#ibcon#*before return 0, iclass 13, count 0 2006.173.23:57:36.55#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.23:57:36.55#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.23:57:36.55#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.23:57:36.55#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.23:57:36.55$vck44/va=8,4 2006.173.23:57:36.55#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.173.23:57:36.55#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.173.23:57:36.55#ibcon#ireg 11 cls_cnt 2 2006.173.23:57:36.55#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.23:57:36.61#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.173.23:57:36.61#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.23:57:36.61#ibcon#enter wrdev, iclass 15, count 2 2006.173.23:57:36.61#ibcon#first serial, iclass 15, count 2 2006.173.23:57:36.61#ibcon#enter sib2, iclass 15, count 2 2006.173.23:57:36.61#ibcon#flushed, iclass 15, count 2 2006.173.23:57:36.61#ibcon#about to write, iclass 15, count 2 2006.173.23:57:36.61#ibcon#wrote, iclass 15, count 2 2006.173.23:57:36.61#ibcon#about to read 3, iclass 15, count 2 2006.173.23:57:36.63#ibcon#read 3, iclass 15, count 2 2006.173.23:57:36.63#ibcon#about to read 4, iclass 15, count 2 2006.173.23:57:36.63#ibcon#read 4, iclass 15, count 2 2006.173.23:57:36.63#ibcon#about to read 5, iclass 15, count 2 2006.173.23:57:36.63#ibcon#read 5, iclass 15, count 2 2006.173.23:57:36.63#ibcon#about to read 6, iclass 15, count 2 2006.173.23:57:36.63#ibcon#read 6, iclass 15, count 2 2006.173.23:57:36.63#ibcon#end of sib2, iclass 15, count 2 2006.173.23:57:36.63#ibcon#*mode == 0, iclass 15, count 2 2006.173.23:57:36.63#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.173.23:57:36.63#ibcon#[25=AT08-04\r\n] 2006.173.23:57:36.63#ibcon#*before write, iclass 15, count 2 2006.173.23:57:36.63#ibcon#enter sib2, iclass 15, count 2 2006.173.23:57:36.63#ibcon#flushed, iclass 15, count 2 2006.173.23:57:36.63#ibcon#about to write, iclass 15, count 2 2006.173.23:57:36.63#ibcon#wrote, iclass 15, count 2 2006.173.23:57:36.63#ibcon#about to read 3, iclass 15, count 2 2006.173.23:57:36.66#ibcon#read 3, iclass 15, count 2 2006.173.23:57:36.66#ibcon#about to read 4, iclass 15, count 2 2006.173.23:57:36.66#ibcon#read 4, iclass 15, count 2 2006.173.23:57:36.66#ibcon#about to read 5, iclass 15, count 2 2006.173.23:57:36.66#ibcon#read 5, iclass 15, count 2 2006.173.23:57:36.66#ibcon#about to read 6, iclass 15, count 2 2006.173.23:57:36.66#ibcon#read 6, iclass 15, count 2 2006.173.23:57:36.66#ibcon#end of sib2, iclass 15, count 2 2006.173.23:57:36.66#ibcon#*after write, iclass 15, count 2 2006.173.23:57:36.66#ibcon#*before return 0, iclass 15, count 2 2006.173.23:57:36.66#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.173.23:57:36.66#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.173.23:57:36.66#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.173.23:57:36.66#ibcon#ireg 7 cls_cnt 0 2006.173.23:57:36.66#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.23:57:36.78#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.173.23:57:36.78#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.23:57:36.78#ibcon#enter wrdev, iclass 15, count 0 2006.173.23:57:36.78#ibcon#first serial, iclass 15, count 0 2006.173.23:57:36.78#ibcon#enter sib2, iclass 15, count 0 2006.173.23:57:36.78#ibcon#flushed, iclass 15, count 0 2006.173.23:57:36.78#ibcon#about to write, iclass 15, count 0 2006.173.23:57:36.78#ibcon#wrote, iclass 15, count 0 2006.173.23:57:36.78#ibcon#about to read 3, iclass 15, count 0 2006.173.23:57:36.80#ibcon#read 3, iclass 15, count 0 2006.173.23:57:36.80#ibcon#about to read 4, iclass 15, count 0 2006.173.23:57:36.80#ibcon#read 4, iclass 15, count 0 2006.173.23:57:36.80#ibcon#about to read 5, iclass 15, count 0 2006.173.23:57:36.80#ibcon#read 5, iclass 15, count 0 2006.173.23:57:36.80#ibcon#about to read 6, iclass 15, count 0 2006.173.23:57:36.80#ibcon#read 6, iclass 15, count 0 2006.173.23:57:36.80#ibcon#end of sib2, iclass 15, count 0 2006.173.23:57:36.80#ibcon#*mode == 0, iclass 15, count 0 2006.173.23:57:36.80#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.23:57:36.80#ibcon#[25=USB\r\n] 2006.173.23:57:36.80#ibcon#*before write, iclass 15, count 0 2006.173.23:57:36.80#ibcon#enter sib2, iclass 15, count 0 2006.173.23:57:36.80#ibcon#flushed, iclass 15, count 0 2006.173.23:57:36.80#ibcon#about to write, iclass 15, count 0 2006.173.23:57:36.80#ibcon#wrote, iclass 15, count 0 2006.173.23:57:36.80#ibcon#about to read 3, iclass 15, count 0 2006.173.23:57:36.83#ibcon#read 3, iclass 15, count 0 2006.173.23:57:36.83#ibcon#about to read 4, iclass 15, count 0 2006.173.23:57:36.83#ibcon#read 4, iclass 15, count 0 2006.173.23:57:36.83#ibcon#about to read 5, iclass 15, count 0 2006.173.23:57:36.83#ibcon#read 5, iclass 15, count 0 2006.173.23:57:36.83#ibcon#about to read 6, iclass 15, count 0 2006.173.23:57:36.83#ibcon#read 6, iclass 15, count 0 2006.173.23:57:36.83#ibcon#end of sib2, iclass 15, count 0 2006.173.23:57:36.83#ibcon#*after write, iclass 15, count 0 2006.173.23:57:36.83#ibcon#*before return 0, iclass 15, count 0 2006.173.23:57:36.83#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.173.23:57:36.83#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.173.23:57:36.83#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.23:57:36.83#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.23:57:36.83$vck44/vblo=1,629.99 2006.173.23:57:36.83#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.173.23:57:36.83#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.173.23:57:36.83#ibcon#ireg 17 cls_cnt 0 2006.173.23:57:36.83#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.23:57:36.83#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.173.23:57:36.83#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.23:57:36.83#ibcon#enter wrdev, iclass 17, count 0 2006.173.23:57:36.83#ibcon#first serial, iclass 17, count 0 2006.173.23:57:36.83#ibcon#enter sib2, iclass 17, count 0 2006.173.23:57:36.83#ibcon#flushed, iclass 17, count 0 2006.173.23:57:36.83#ibcon#about to write, iclass 17, count 0 2006.173.23:57:36.83#ibcon#wrote, iclass 17, count 0 2006.173.23:57:36.83#ibcon#about to read 3, iclass 17, count 0 2006.173.23:57:36.85#ibcon#read 3, iclass 17, count 0 2006.173.23:57:36.85#ibcon#about to read 4, iclass 17, count 0 2006.173.23:57:36.85#ibcon#read 4, iclass 17, count 0 2006.173.23:57:36.85#ibcon#about to read 5, iclass 17, count 0 2006.173.23:57:36.85#ibcon#read 5, iclass 17, count 0 2006.173.23:57:36.85#ibcon#about to read 6, iclass 17, count 0 2006.173.23:57:36.85#ibcon#read 6, iclass 17, count 0 2006.173.23:57:36.85#ibcon#end of sib2, iclass 17, count 0 2006.173.23:57:36.85#ibcon#*mode == 0, iclass 17, count 0 2006.173.23:57:36.85#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.173.23:57:36.85#ibcon#[28=FRQ=01,629.99\r\n] 2006.173.23:57:36.85#ibcon#*before write, iclass 17, count 0 2006.173.23:57:36.85#ibcon#enter sib2, iclass 17, count 0 2006.173.23:57:36.85#ibcon#flushed, iclass 17, count 0 2006.173.23:57:36.85#ibcon#about to write, iclass 17, count 0 2006.173.23:57:36.85#ibcon#wrote, iclass 17, count 0 2006.173.23:57:36.85#ibcon#about to read 3, iclass 17, count 0 2006.173.23:57:36.89#ibcon#read 3, iclass 17, count 0 2006.173.23:57:36.89#ibcon#about to read 4, iclass 17, count 0 2006.173.23:57:36.89#ibcon#read 4, iclass 17, count 0 2006.173.23:57:36.89#ibcon#about to read 5, iclass 17, count 0 2006.173.23:57:36.89#ibcon#read 5, iclass 17, count 0 2006.173.23:57:36.89#ibcon#about to read 6, iclass 17, count 0 2006.173.23:57:36.89#ibcon#read 6, iclass 17, count 0 2006.173.23:57:36.89#ibcon#end of sib2, iclass 17, count 0 2006.173.23:57:36.89#ibcon#*after write, iclass 17, count 0 2006.173.23:57:36.89#ibcon#*before return 0, iclass 17, count 0 2006.173.23:57:36.89#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.173.23:57:36.89#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.173.23:57:36.89#ibcon#about to clear, iclass 17 cls_cnt 0 2006.173.23:57:36.89#ibcon#cleared, iclass 17 cls_cnt 0 2006.173.23:57:36.89$vck44/vb=1,4 2006.173.23:57:36.89#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.173.23:57:36.89#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.173.23:57:36.89#ibcon#ireg 11 cls_cnt 2 2006.173.23:57:36.89#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.23:57:36.89#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.173.23:57:36.89#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.23:57:36.89#ibcon#enter wrdev, iclass 19, count 2 2006.173.23:57:36.89#ibcon#first serial, iclass 19, count 2 2006.173.23:57:36.89#ibcon#enter sib2, iclass 19, count 2 2006.173.23:57:36.89#ibcon#flushed, iclass 19, count 2 2006.173.23:57:36.89#ibcon#about to write, iclass 19, count 2 2006.173.23:57:36.89#ibcon#wrote, iclass 19, count 2 2006.173.23:57:36.89#ibcon#about to read 3, iclass 19, count 2 2006.173.23:57:36.91#ibcon#read 3, iclass 19, count 2 2006.173.23:57:36.91#ibcon#about to read 4, iclass 19, count 2 2006.173.23:57:36.91#ibcon#read 4, iclass 19, count 2 2006.173.23:57:36.91#ibcon#about to read 5, iclass 19, count 2 2006.173.23:57:36.91#ibcon#read 5, iclass 19, count 2 2006.173.23:57:36.91#ibcon#about to read 6, iclass 19, count 2 2006.173.23:57:36.91#ibcon#read 6, iclass 19, count 2 2006.173.23:57:36.91#ibcon#end of sib2, iclass 19, count 2 2006.173.23:57:36.91#ibcon#*mode == 0, iclass 19, count 2 2006.173.23:57:36.91#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.173.23:57:36.91#ibcon#[27=AT01-04\r\n] 2006.173.23:57:36.91#ibcon#*before write, iclass 19, count 2 2006.173.23:57:36.91#ibcon#enter sib2, iclass 19, count 2 2006.173.23:57:36.91#ibcon#flushed, iclass 19, count 2 2006.173.23:57:36.91#ibcon#about to write, iclass 19, count 2 2006.173.23:57:36.91#ibcon#wrote, iclass 19, count 2 2006.173.23:57:36.91#ibcon#about to read 3, iclass 19, count 2 2006.173.23:57:36.94#ibcon#read 3, iclass 19, count 2 2006.173.23:57:36.94#ibcon#about to read 4, iclass 19, count 2 2006.173.23:57:36.94#ibcon#read 4, iclass 19, count 2 2006.173.23:57:36.94#ibcon#about to read 5, iclass 19, count 2 2006.173.23:57:36.94#ibcon#read 5, iclass 19, count 2 2006.173.23:57:36.94#ibcon#about to read 6, iclass 19, count 2 2006.173.23:57:36.94#ibcon#read 6, iclass 19, count 2 2006.173.23:57:36.94#ibcon#end of sib2, iclass 19, count 2 2006.173.23:57:36.94#ibcon#*after write, iclass 19, count 2 2006.173.23:57:36.94#ibcon#*before return 0, iclass 19, count 2 2006.173.23:57:36.94#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.173.23:57:36.94#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.173.23:57:36.94#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.173.23:57:36.94#ibcon#ireg 7 cls_cnt 0 2006.173.23:57:36.94#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.23:57:37.06#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.173.23:57:37.06#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.23:57:37.06#ibcon#enter wrdev, iclass 19, count 0 2006.173.23:57:37.06#ibcon#first serial, iclass 19, count 0 2006.173.23:57:37.06#ibcon#enter sib2, iclass 19, count 0 2006.173.23:57:37.06#ibcon#flushed, iclass 19, count 0 2006.173.23:57:37.06#ibcon#about to write, iclass 19, count 0 2006.173.23:57:37.06#ibcon#wrote, iclass 19, count 0 2006.173.23:57:37.06#ibcon#about to read 3, iclass 19, count 0 2006.173.23:57:37.08#ibcon#read 3, iclass 19, count 0 2006.173.23:57:37.08#ibcon#about to read 4, iclass 19, count 0 2006.173.23:57:37.08#ibcon#read 4, iclass 19, count 0 2006.173.23:57:37.08#ibcon#about to read 5, iclass 19, count 0 2006.173.23:57:37.08#ibcon#read 5, iclass 19, count 0 2006.173.23:57:37.08#ibcon#about to read 6, iclass 19, count 0 2006.173.23:57:37.08#ibcon#read 6, iclass 19, count 0 2006.173.23:57:37.08#ibcon#end of sib2, iclass 19, count 0 2006.173.23:57:37.08#ibcon#*mode == 0, iclass 19, count 0 2006.173.23:57:37.08#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.173.23:57:37.08#ibcon#[27=USB\r\n] 2006.173.23:57:37.08#ibcon#*before write, iclass 19, count 0 2006.173.23:57:37.08#ibcon#enter sib2, iclass 19, count 0 2006.173.23:57:37.08#ibcon#flushed, iclass 19, count 0 2006.173.23:57:37.08#ibcon#about to write, iclass 19, count 0 2006.173.23:57:37.08#ibcon#wrote, iclass 19, count 0 2006.173.23:57:37.08#ibcon#about to read 3, iclass 19, count 0 2006.173.23:57:37.11#ibcon#read 3, iclass 19, count 0 2006.173.23:57:37.11#ibcon#about to read 4, iclass 19, count 0 2006.173.23:57:37.11#ibcon#read 4, iclass 19, count 0 2006.173.23:57:37.11#ibcon#about to read 5, iclass 19, count 0 2006.173.23:57:37.11#ibcon#read 5, iclass 19, count 0 2006.173.23:57:37.11#ibcon#about to read 6, iclass 19, count 0 2006.173.23:57:37.11#ibcon#read 6, iclass 19, count 0 2006.173.23:57:37.11#ibcon#end of sib2, iclass 19, count 0 2006.173.23:57:37.11#ibcon#*after write, iclass 19, count 0 2006.173.23:57:37.11#ibcon#*before return 0, iclass 19, count 0 2006.173.23:57:37.11#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.173.23:57:37.11#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.173.23:57:37.11#ibcon#about to clear, iclass 19 cls_cnt 0 2006.173.23:57:37.11#ibcon#cleared, iclass 19 cls_cnt 0 2006.173.23:57:37.11$vck44/vblo=2,634.99 2006.173.23:57:37.11#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.173.23:57:37.11#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.173.23:57:37.11#ibcon#ireg 17 cls_cnt 0 2006.173.23:57:37.11#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.23:57:37.11#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.173.23:57:37.11#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.23:57:37.11#ibcon#enter wrdev, iclass 21, count 0 2006.173.23:57:37.11#ibcon#first serial, iclass 21, count 0 2006.173.23:57:37.11#ibcon#enter sib2, iclass 21, count 0 2006.173.23:57:37.11#ibcon#flushed, iclass 21, count 0 2006.173.23:57:37.11#ibcon#about to write, iclass 21, count 0 2006.173.23:57:37.11#ibcon#wrote, iclass 21, count 0 2006.173.23:57:37.11#ibcon#about to read 3, iclass 21, count 0 2006.173.23:57:37.13#ibcon#read 3, iclass 21, count 0 2006.173.23:57:37.13#ibcon#about to read 4, iclass 21, count 0 2006.173.23:57:37.13#ibcon#read 4, iclass 21, count 0 2006.173.23:57:37.13#ibcon#about to read 5, iclass 21, count 0 2006.173.23:57:37.13#ibcon#read 5, iclass 21, count 0 2006.173.23:57:37.13#ibcon#about to read 6, iclass 21, count 0 2006.173.23:57:37.13#ibcon#read 6, iclass 21, count 0 2006.173.23:57:37.13#ibcon#end of sib2, iclass 21, count 0 2006.173.23:57:37.13#ibcon#*mode == 0, iclass 21, count 0 2006.173.23:57:37.13#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.173.23:57:37.13#ibcon#[28=FRQ=02,634.99\r\n] 2006.173.23:57:37.13#ibcon#*before write, iclass 21, count 0 2006.173.23:57:37.13#ibcon#enter sib2, iclass 21, count 0 2006.173.23:57:37.13#ibcon#flushed, iclass 21, count 0 2006.173.23:57:37.13#ibcon#about to write, iclass 21, count 0 2006.173.23:57:37.13#ibcon#wrote, iclass 21, count 0 2006.173.23:57:37.13#ibcon#about to read 3, iclass 21, count 0 2006.173.23:57:37.17#ibcon#read 3, iclass 21, count 0 2006.173.23:57:37.17#ibcon#about to read 4, iclass 21, count 0 2006.173.23:57:37.17#ibcon#read 4, iclass 21, count 0 2006.173.23:57:37.17#ibcon#about to read 5, iclass 21, count 0 2006.173.23:57:37.17#ibcon#read 5, iclass 21, count 0 2006.173.23:57:37.17#ibcon#about to read 6, iclass 21, count 0 2006.173.23:57:37.17#ibcon#read 6, iclass 21, count 0 2006.173.23:57:37.17#ibcon#end of sib2, iclass 21, count 0 2006.173.23:57:37.17#ibcon#*after write, iclass 21, count 0 2006.173.23:57:37.17#ibcon#*before return 0, iclass 21, count 0 2006.173.23:57:37.17#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.173.23:57:37.17#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.173.23:57:37.17#ibcon#about to clear, iclass 21 cls_cnt 0 2006.173.23:57:37.17#ibcon#cleared, iclass 21 cls_cnt 0 2006.173.23:57:37.17$vck44/vb=2,4 2006.173.23:57:37.17#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.173.23:57:37.17#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.173.23:57:37.17#ibcon#ireg 11 cls_cnt 2 2006.173.23:57:37.17#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.23:57:37.23#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.173.23:57:37.23#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.23:57:37.23#ibcon#enter wrdev, iclass 23, count 2 2006.173.23:57:37.23#ibcon#first serial, iclass 23, count 2 2006.173.23:57:37.23#ibcon#enter sib2, iclass 23, count 2 2006.173.23:57:37.23#ibcon#flushed, iclass 23, count 2 2006.173.23:57:37.23#ibcon#about to write, iclass 23, count 2 2006.173.23:57:37.23#ibcon#wrote, iclass 23, count 2 2006.173.23:57:37.23#ibcon#about to read 3, iclass 23, count 2 2006.173.23:57:37.25#ibcon#read 3, iclass 23, count 2 2006.173.23:57:37.25#ibcon#about to read 4, iclass 23, count 2 2006.173.23:57:37.25#ibcon#read 4, iclass 23, count 2 2006.173.23:57:37.25#ibcon#about to read 5, iclass 23, count 2 2006.173.23:57:37.25#ibcon#read 5, iclass 23, count 2 2006.173.23:57:37.25#ibcon#about to read 6, iclass 23, count 2 2006.173.23:57:37.25#ibcon#read 6, iclass 23, count 2 2006.173.23:57:37.25#ibcon#end of sib2, iclass 23, count 2 2006.173.23:57:37.25#ibcon#*mode == 0, iclass 23, count 2 2006.173.23:57:37.25#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.173.23:57:37.25#ibcon#[27=AT02-04\r\n] 2006.173.23:57:37.25#ibcon#*before write, iclass 23, count 2 2006.173.23:57:37.25#ibcon#enter sib2, iclass 23, count 2 2006.173.23:57:37.25#ibcon#flushed, iclass 23, count 2 2006.173.23:57:37.25#ibcon#about to write, iclass 23, count 2 2006.173.23:57:37.25#ibcon#wrote, iclass 23, count 2 2006.173.23:57:37.25#ibcon#about to read 3, iclass 23, count 2 2006.173.23:57:37.28#ibcon#read 3, iclass 23, count 2 2006.173.23:57:37.28#ibcon#about to read 4, iclass 23, count 2 2006.173.23:57:37.28#ibcon#read 4, iclass 23, count 2 2006.173.23:57:37.28#ibcon#about to read 5, iclass 23, count 2 2006.173.23:57:37.28#ibcon#read 5, iclass 23, count 2 2006.173.23:57:37.28#ibcon#about to read 6, iclass 23, count 2 2006.173.23:57:37.28#ibcon#read 6, iclass 23, count 2 2006.173.23:57:37.28#ibcon#end of sib2, iclass 23, count 2 2006.173.23:57:37.28#ibcon#*after write, iclass 23, count 2 2006.173.23:57:37.28#ibcon#*before return 0, iclass 23, count 2 2006.173.23:57:37.28#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.173.23:57:37.28#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.173.23:57:37.28#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.173.23:57:37.28#ibcon#ireg 7 cls_cnt 0 2006.173.23:57:37.28#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.23:57:37.40#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.173.23:57:37.40#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.23:57:37.40#ibcon#enter wrdev, iclass 23, count 0 2006.173.23:57:37.40#ibcon#first serial, iclass 23, count 0 2006.173.23:57:37.40#ibcon#enter sib2, iclass 23, count 0 2006.173.23:57:37.40#ibcon#flushed, iclass 23, count 0 2006.173.23:57:37.40#ibcon#about to write, iclass 23, count 0 2006.173.23:57:37.40#ibcon#wrote, iclass 23, count 0 2006.173.23:57:37.40#ibcon#about to read 3, iclass 23, count 0 2006.173.23:57:37.42#ibcon#read 3, iclass 23, count 0 2006.173.23:57:37.42#ibcon#about to read 4, iclass 23, count 0 2006.173.23:57:37.42#ibcon#read 4, iclass 23, count 0 2006.173.23:57:37.42#ibcon#about to read 5, iclass 23, count 0 2006.173.23:57:37.42#ibcon#read 5, iclass 23, count 0 2006.173.23:57:37.42#ibcon#about to read 6, iclass 23, count 0 2006.173.23:57:37.42#ibcon#read 6, iclass 23, count 0 2006.173.23:57:37.42#ibcon#end of sib2, iclass 23, count 0 2006.173.23:57:37.42#ibcon#*mode == 0, iclass 23, count 0 2006.173.23:57:37.42#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.173.23:57:37.42#ibcon#[27=USB\r\n] 2006.173.23:57:37.42#ibcon#*before write, iclass 23, count 0 2006.173.23:57:37.42#ibcon#enter sib2, iclass 23, count 0 2006.173.23:57:37.42#ibcon#flushed, iclass 23, count 0 2006.173.23:57:37.42#ibcon#about to write, iclass 23, count 0 2006.173.23:57:37.42#ibcon#wrote, iclass 23, count 0 2006.173.23:57:37.42#ibcon#about to read 3, iclass 23, count 0 2006.173.23:57:37.45#ibcon#read 3, iclass 23, count 0 2006.173.23:57:37.45#ibcon#about to read 4, iclass 23, count 0 2006.173.23:57:37.45#ibcon#read 4, iclass 23, count 0 2006.173.23:57:37.45#ibcon#about to read 5, iclass 23, count 0 2006.173.23:57:37.45#ibcon#read 5, iclass 23, count 0 2006.173.23:57:37.45#ibcon#about to read 6, iclass 23, count 0 2006.173.23:57:37.45#ibcon#read 6, iclass 23, count 0 2006.173.23:57:37.45#ibcon#end of sib2, iclass 23, count 0 2006.173.23:57:37.45#ibcon#*after write, iclass 23, count 0 2006.173.23:57:37.45#ibcon#*before return 0, iclass 23, count 0 2006.173.23:57:37.45#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.173.23:57:37.45#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.173.23:57:37.45#ibcon#about to clear, iclass 23 cls_cnt 0 2006.173.23:57:37.45#ibcon#cleared, iclass 23 cls_cnt 0 2006.173.23:57:37.45$vck44/vblo=3,649.99 2006.173.23:57:37.45#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.173.23:57:37.45#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.173.23:57:37.45#ibcon#ireg 17 cls_cnt 0 2006.173.23:57:37.45#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.23:57:37.45#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.173.23:57:37.45#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.23:57:37.45#ibcon#enter wrdev, iclass 25, count 0 2006.173.23:57:37.45#ibcon#first serial, iclass 25, count 0 2006.173.23:57:37.45#ibcon#enter sib2, iclass 25, count 0 2006.173.23:57:37.45#ibcon#flushed, iclass 25, count 0 2006.173.23:57:37.45#ibcon#about to write, iclass 25, count 0 2006.173.23:57:37.45#ibcon#wrote, iclass 25, count 0 2006.173.23:57:37.45#ibcon#about to read 3, iclass 25, count 0 2006.173.23:57:37.47#ibcon#read 3, iclass 25, count 0 2006.173.23:57:37.47#ibcon#about to read 4, iclass 25, count 0 2006.173.23:57:37.47#ibcon#read 4, iclass 25, count 0 2006.173.23:57:37.47#ibcon#about to read 5, iclass 25, count 0 2006.173.23:57:37.47#ibcon#read 5, iclass 25, count 0 2006.173.23:57:37.47#ibcon#about to read 6, iclass 25, count 0 2006.173.23:57:37.47#ibcon#read 6, iclass 25, count 0 2006.173.23:57:37.47#ibcon#end of sib2, iclass 25, count 0 2006.173.23:57:37.47#ibcon#*mode == 0, iclass 25, count 0 2006.173.23:57:37.47#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.173.23:57:37.47#ibcon#[28=FRQ=03,649.99\r\n] 2006.173.23:57:37.47#ibcon#*before write, iclass 25, count 0 2006.173.23:57:37.47#ibcon#enter sib2, iclass 25, count 0 2006.173.23:57:37.47#ibcon#flushed, iclass 25, count 0 2006.173.23:57:37.47#ibcon#about to write, iclass 25, count 0 2006.173.23:57:37.47#ibcon#wrote, iclass 25, count 0 2006.173.23:57:37.47#ibcon#about to read 3, iclass 25, count 0 2006.173.23:57:37.51#ibcon#read 3, iclass 25, count 0 2006.173.23:57:37.51#ibcon#about to read 4, iclass 25, count 0 2006.173.23:57:37.51#ibcon#read 4, iclass 25, count 0 2006.173.23:57:37.51#ibcon#about to read 5, iclass 25, count 0 2006.173.23:57:37.51#ibcon#read 5, iclass 25, count 0 2006.173.23:57:37.51#ibcon#about to read 6, iclass 25, count 0 2006.173.23:57:37.51#ibcon#read 6, iclass 25, count 0 2006.173.23:57:37.51#ibcon#end of sib2, iclass 25, count 0 2006.173.23:57:37.51#ibcon#*after write, iclass 25, count 0 2006.173.23:57:37.51#ibcon#*before return 0, iclass 25, count 0 2006.173.23:57:37.51#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.173.23:57:37.51#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.173.23:57:37.51#ibcon#about to clear, iclass 25 cls_cnt 0 2006.173.23:57:37.51#ibcon#cleared, iclass 25 cls_cnt 0 2006.173.23:57:37.51$vck44/vb=3,4 2006.173.23:57:37.51#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.173.23:57:37.51#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.173.23:57:37.51#ibcon#ireg 11 cls_cnt 2 2006.173.23:57:37.51#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.23:57:37.57#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.173.23:57:37.57#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.23:57:37.57#ibcon#enter wrdev, iclass 27, count 2 2006.173.23:57:37.57#ibcon#first serial, iclass 27, count 2 2006.173.23:57:37.57#ibcon#enter sib2, iclass 27, count 2 2006.173.23:57:37.57#ibcon#flushed, iclass 27, count 2 2006.173.23:57:37.57#ibcon#about to write, iclass 27, count 2 2006.173.23:57:37.57#ibcon#wrote, iclass 27, count 2 2006.173.23:57:37.57#ibcon#about to read 3, iclass 27, count 2 2006.173.23:57:37.59#ibcon#read 3, iclass 27, count 2 2006.173.23:57:37.59#ibcon#about to read 4, iclass 27, count 2 2006.173.23:57:37.59#ibcon#read 4, iclass 27, count 2 2006.173.23:57:37.59#ibcon#about to read 5, iclass 27, count 2 2006.173.23:57:37.59#ibcon#read 5, iclass 27, count 2 2006.173.23:57:37.59#ibcon#about to read 6, iclass 27, count 2 2006.173.23:57:37.59#ibcon#read 6, iclass 27, count 2 2006.173.23:57:37.59#ibcon#end of sib2, iclass 27, count 2 2006.173.23:57:37.59#ibcon#*mode == 0, iclass 27, count 2 2006.173.23:57:37.59#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.173.23:57:37.59#ibcon#[27=AT03-04\r\n] 2006.173.23:57:37.59#ibcon#*before write, iclass 27, count 2 2006.173.23:57:37.59#ibcon#enter sib2, iclass 27, count 2 2006.173.23:57:37.59#ibcon#flushed, iclass 27, count 2 2006.173.23:57:37.59#ibcon#about to write, iclass 27, count 2 2006.173.23:57:37.59#ibcon#wrote, iclass 27, count 2 2006.173.23:57:37.59#ibcon#about to read 3, iclass 27, count 2 2006.173.23:57:37.62#ibcon#read 3, iclass 27, count 2 2006.173.23:57:37.62#ibcon#about to read 4, iclass 27, count 2 2006.173.23:57:37.62#ibcon#read 4, iclass 27, count 2 2006.173.23:57:37.62#ibcon#about to read 5, iclass 27, count 2 2006.173.23:57:37.62#ibcon#read 5, iclass 27, count 2 2006.173.23:57:37.62#ibcon#about to read 6, iclass 27, count 2 2006.173.23:57:37.62#ibcon#read 6, iclass 27, count 2 2006.173.23:57:37.62#ibcon#end of sib2, iclass 27, count 2 2006.173.23:57:37.62#ibcon#*after write, iclass 27, count 2 2006.173.23:57:37.62#ibcon#*before return 0, iclass 27, count 2 2006.173.23:57:37.62#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.173.23:57:37.62#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.173.23:57:37.62#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.173.23:57:37.62#ibcon#ireg 7 cls_cnt 0 2006.173.23:57:37.62#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.23:57:37.74#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.173.23:57:37.74#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.23:57:37.74#ibcon#enter wrdev, iclass 27, count 0 2006.173.23:57:37.74#ibcon#first serial, iclass 27, count 0 2006.173.23:57:37.74#ibcon#enter sib2, iclass 27, count 0 2006.173.23:57:37.74#ibcon#flushed, iclass 27, count 0 2006.173.23:57:37.74#ibcon#about to write, iclass 27, count 0 2006.173.23:57:37.74#ibcon#wrote, iclass 27, count 0 2006.173.23:57:37.74#ibcon#about to read 3, iclass 27, count 0 2006.173.23:57:37.76#ibcon#read 3, iclass 27, count 0 2006.173.23:57:37.76#ibcon#about to read 4, iclass 27, count 0 2006.173.23:57:37.76#ibcon#read 4, iclass 27, count 0 2006.173.23:57:37.76#ibcon#about to read 5, iclass 27, count 0 2006.173.23:57:37.76#ibcon#read 5, iclass 27, count 0 2006.173.23:57:37.76#ibcon#about to read 6, iclass 27, count 0 2006.173.23:57:37.76#ibcon#read 6, iclass 27, count 0 2006.173.23:57:37.76#ibcon#end of sib2, iclass 27, count 0 2006.173.23:57:37.76#ibcon#*mode == 0, iclass 27, count 0 2006.173.23:57:37.76#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.173.23:57:37.76#ibcon#[27=USB\r\n] 2006.173.23:57:37.76#ibcon#*before write, iclass 27, count 0 2006.173.23:57:37.76#ibcon#enter sib2, iclass 27, count 0 2006.173.23:57:37.76#ibcon#flushed, iclass 27, count 0 2006.173.23:57:37.76#ibcon#about to write, iclass 27, count 0 2006.173.23:57:37.76#ibcon#wrote, iclass 27, count 0 2006.173.23:57:37.76#ibcon#about to read 3, iclass 27, count 0 2006.173.23:57:37.79#ibcon#read 3, iclass 27, count 0 2006.173.23:57:37.79#ibcon#about to read 4, iclass 27, count 0 2006.173.23:57:37.79#ibcon#read 4, iclass 27, count 0 2006.173.23:57:37.79#ibcon#about to read 5, iclass 27, count 0 2006.173.23:57:37.79#ibcon#read 5, iclass 27, count 0 2006.173.23:57:37.79#ibcon#about to read 6, iclass 27, count 0 2006.173.23:57:37.79#ibcon#read 6, iclass 27, count 0 2006.173.23:57:37.79#ibcon#end of sib2, iclass 27, count 0 2006.173.23:57:37.79#ibcon#*after write, iclass 27, count 0 2006.173.23:57:37.79#ibcon#*before return 0, iclass 27, count 0 2006.173.23:57:37.79#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.173.23:57:37.79#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.173.23:57:37.79#ibcon#about to clear, iclass 27 cls_cnt 0 2006.173.23:57:37.79#ibcon#cleared, iclass 27 cls_cnt 0 2006.173.23:57:37.79$vck44/vblo=4,679.99 2006.173.23:57:37.79#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.173.23:57:37.79#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.173.23:57:37.79#ibcon#ireg 17 cls_cnt 0 2006.173.23:57:37.79#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.23:57:37.79#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.173.23:57:37.79#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.23:57:37.79#ibcon#enter wrdev, iclass 29, count 0 2006.173.23:57:37.79#ibcon#first serial, iclass 29, count 0 2006.173.23:57:37.79#ibcon#enter sib2, iclass 29, count 0 2006.173.23:57:37.79#ibcon#flushed, iclass 29, count 0 2006.173.23:57:37.79#ibcon#about to write, iclass 29, count 0 2006.173.23:57:37.79#ibcon#wrote, iclass 29, count 0 2006.173.23:57:37.79#ibcon#about to read 3, iclass 29, count 0 2006.173.23:57:37.81#ibcon#read 3, iclass 29, count 0 2006.173.23:57:37.81#ibcon#about to read 4, iclass 29, count 0 2006.173.23:57:37.81#ibcon#read 4, iclass 29, count 0 2006.173.23:57:37.81#ibcon#about to read 5, iclass 29, count 0 2006.173.23:57:37.81#ibcon#read 5, iclass 29, count 0 2006.173.23:57:37.81#ibcon#about to read 6, iclass 29, count 0 2006.173.23:57:37.81#ibcon#read 6, iclass 29, count 0 2006.173.23:57:37.81#ibcon#end of sib2, iclass 29, count 0 2006.173.23:57:37.81#ibcon#*mode == 0, iclass 29, count 0 2006.173.23:57:37.81#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.173.23:57:37.81#ibcon#[28=FRQ=04,679.99\r\n] 2006.173.23:57:37.81#ibcon#*before write, iclass 29, count 0 2006.173.23:57:37.81#ibcon#enter sib2, iclass 29, count 0 2006.173.23:57:37.81#ibcon#flushed, iclass 29, count 0 2006.173.23:57:37.81#ibcon#about to write, iclass 29, count 0 2006.173.23:57:37.81#ibcon#wrote, iclass 29, count 0 2006.173.23:57:37.81#ibcon#about to read 3, iclass 29, count 0 2006.173.23:57:37.85#ibcon#read 3, iclass 29, count 0 2006.173.23:57:37.85#ibcon#about to read 4, iclass 29, count 0 2006.173.23:57:37.85#ibcon#read 4, iclass 29, count 0 2006.173.23:57:37.85#ibcon#about to read 5, iclass 29, count 0 2006.173.23:57:37.85#ibcon#read 5, iclass 29, count 0 2006.173.23:57:37.85#ibcon#about to read 6, iclass 29, count 0 2006.173.23:57:37.85#ibcon#read 6, iclass 29, count 0 2006.173.23:57:37.85#ibcon#end of sib2, iclass 29, count 0 2006.173.23:57:37.85#ibcon#*after write, iclass 29, count 0 2006.173.23:57:37.85#ibcon#*before return 0, iclass 29, count 0 2006.173.23:57:37.85#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.173.23:57:37.85#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.173.23:57:37.85#ibcon#about to clear, iclass 29 cls_cnt 0 2006.173.23:57:37.85#ibcon#cleared, iclass 29 cls_cnt 0 2006.173.23:57:37.85$vck44/vb=4,4 2006.173.23:57:37.85#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.173.23:57:37.85#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.173.23:57:37.85#ibcon#ireg 11 cls_cnt 2 2006.173.23:57:37.85#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.23:57:37.91#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.173.23:57:37.91#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.23:57:37.91#ibcon#enter wrdev, iclass 31, count 2 2006.173.23:57:37.91#ibcon#first serial, iclass 31, count 2 2006.173.23:57:37.91#ibcon#enter sib2, iclass 31, count 2 2006.173.23:57:37.91#ibcon#flushed, iclass 31, count 2 2006.173.23:57:37.91#ibcon#about to write, iclass 31, count 2 2006.173.23:57:37.91#ibcon#wrote, iclass 31, count 2 2006.173.23:57:37.91#ibcon#about to read 3, iclass 31, count 2 2006.173.23:57:37.93#ibcon#read 3, iclass 31, count 2 2006.173.23:57:37.93#ibcon#about to read 4, iclass 31, count 2 2006.173.23:57:37.93#ibcon#read 4, iclass 31, count 2 2006.173.23:57:37.93#ibcon#about to read 5, iclass 31, count 2 2006.173.23:57:37.93#ibcon#read 5, iclass 31, count 2 2006.173.23:57:37.93#ibcon#about to read 6, iclass 31, count 2 2006.173.23:57:37.93#ibcon#read 6, iclass 31, count 2 2006.173.23:57:37.93#ibcon#end of sib2, iclass 31, count 2 2006.173.23:57:37.93#ibcon#*mode == 0, iclass 31, count 2 2006.173.23:57:37.93#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.173.23:57:37.93#ibcon#[27=AT04-04\r\n] 2006.173.23:57:37.93#ibcon#*before write, iclass 31, count 2 2006.173.23:57:37.93#ibcon#enter sib2, iclass 31, count 2 2006.173.23:57:37.93#ibcon#flushed, iclass 31, count 2 2006.173.23:57:37.93#ibcon#about to write, iclass 31, count 2 2006.173.23:57:37.93#ibcon#wrote, iclass 31, count 2 2006.173.23:57:37.93#ibcon#about to read 3, iclass 31, count 2 2006.173.23:57:37.96#ibcon#read 3, iclass 31, count 2 2006.173.23:57:37.96#ibcon#about to read 4, iclass 31, count 2 2006.173.23:57:37.96#ibcon#read 4, iclass 31, count 2 2006.173.23:57:37.96#ibcon#about to read 5, iclass 31, count 2 2006.173.23:57:37.96#ibcon#read 5, iclass 31, count 2 2006.173.23:57:37.96#ibcon#about to read 6, iclass 31, count 2 2006.173.23:57:37.96#ibcon#read 6, iclass 31, count 2 2006.173.23:57:37.96#ibcon#end of sib2, iclass 31, count 2 2006.173.23:57:37.96#ibcon#*after write, iclass 31, count 2 2006.173.23:57:37.96#ibcon#*before return 0, iclass 31, count 2 2006.173.23:57:37.96#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.173.23:57:37.96#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.173.23:57:37.96#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.173.23:57:37.96#ibcon#ireg 7 cls_cnt 0 2006.173.23:57:37.96#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.23:57:38.08#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.173.23:57:38.08#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.23:57:38.08#ibcon#enter wrdev, iclass 31, count 0 2006.173.23:57:38.08#ibcon#first serial, iclass 31, count 0 2006.173.23:57:38.08#ibcon#enter sib2, iclass 31, count 0 2006.173.23:57:38.08#ibcon#flushed, iclass 31, count 0 2006.173.23:57:38.08#ibcon#about to write, iclass 31, count 0 2006.173.23:57:38.08#ibcon#wrote, iclass 31, count 0 2006.173.23:57:38.08#ibcon#about to read 3, iclass 31, count 0 2006.173.23:57:38.10#ibcon#read 3, iclass 31, count 0 2006.173.23:57:38.10#ibcon#about to read 4, iclass 31, count 0 2006.173.23:57:38.10#ibcon#read 4, iclass 31, count 0 2006.173.23:57:38.10#ibcon#about to read 5, iclass 31, count 0 2006.173.23:57:38.10#ibcon#read 5, iclass 31, count 0 2006.173.23:57:38.10#ibcon#about to read 6, iclass 31, count 0 2006.173.23:57:38.10#ibcon#read 6, iclass 31, count 0 2006.173.23:57:38.10#ibcon#end of sib2, iclass 31, count 0 2006.173.23:57:38.10#ibcon#*mode == 0, iclass 31, count 0 2006.173.23:57:38.10#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.173.23:57:38.10#ibcon#[27=USB\r\n] 2006.173.23:57:38.10#ibcon#*before write, iclass 31, count 0 2006.173.23:57:38.10#ibcon#enter sib2, iclass 31, count 0 2006.173.23:57:38.10#ibcon#flushed, iclass 31, count 0 2006.173.23:57:38.10#ibcon#about to write, iclass 31, count 0 2006.173.23:57:38.10#ibcon#wrote, iclass 31, count 0 2006.173.23:57:38.10#ibcon#about to read 3, iclass 31, count 0 2006.173.23:57:38.13#ibcon#read 3, iclass 31, count 0 2006.173.23:57:38.13#ibcon#about to read 4, iclass 31, count 0 2006.173.23:57:38.13#ibcon#read 4, iclass 31, count 0 2006.173.23:57:38.13#ibcon#about to read 5, iclass 31, count 0 2006.173.23:57:38.13#ibcon#read 5, iclass 31, count 0 2006.173.23:57:38.13#ibcon#about to read 6, iclass 31, count 0 2006.173.23:57:38.13#ibcon#read 6, iclass 31, count 0 2006.173.23:57:38.13#ibcon#end of sib2, iclass 31, count 0 2006.173.23:57:38.13#ibcon#*after write, iclass 31, count 0 2006.173.23:57:38.13#ibcon#*before return 0, iclass 31, count 0 2006.173.23:57:38.13#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.173.23:57:38.13#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.173.23:57:38.13#ibcon#about to clear, iclass 31 cls_cnt 0 2006.173.23:57:38.13#ibcon#cleared, iclass 31 cls_cnt 0 2006.173.23:57:38.13$vck44/vblo=5,709.99 2006.173.23:57:38.13#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.173.23:57:38.13#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.173.23:57:38.13#ibcon#ireg 17 cls_cnt 0 2006.173.23:57:38.13#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.23:57:38.13#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.173.23:57:38.13#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.23:57:38.13#ibcon#enter wrdev, iclass 33, count 0 2006.173.23:57:38.13#ibcon#first serial, iclass 33, count 0 2006.173.23:57:38.13#ibcon#enter sib2, iclass 33, count 0 2006.173.23:57:38.13#ibcon#flushed, iclass 33, count 0 2006.173.23:57:38.13#ibcon#about to write, iclass 33, count 0 2006.173.23:57:38.13#ibcon#wrote, iclass 33, count 0 2006.173.23:57:38.13#ibcon#about to read 3, iclass 33, count 0 2006.173.23:57:38.15#ibcon#read 3, iclass 33, count 0 2006.173.23:57:38.15#ibcon#about to read 4, iclass 33, count 0 2006.173.23:57:38.15#ibcon#read 4, iclass 33, count 0 2006.173.23:57:38.15#ibcon#about to read 5, iclass 33, count 0 2006.173.23:57:38.15#ibcon#read 5, iclass 33, count 0 2006.173.23:57:38.15#ibcon#about to read 6, iclass 33, count 0 2006.173.23:57:38.15#ibcon#read 6, iclass 33, count 0 2006.173.23:57:38.15#ibcon#end of sib2, iclass 33, count 0 2006.173.23:57:38.15#ibcon#*mode == 0, iclass 33, count 0 2006.173.23:57:38.15#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.173.23:57:38.15#ibcon#[28=FRQ=05,709.99\r\n] 2006.173.23:57:38.15#ibcon#*before write, iclass 33, count 0 2006.173.23:57:38.15#ibcon#enter sib2, iclass 33, count 0 2006.173.23:57:38.15#ibcon#flushed, iclass 33, count 0 2006.173.23:57:38.15#ibcon#about to write, iclass 33, count 0 2006.173.23:57:38.15#ibcon#wrote, iclass 33, count 0 2006.173.23:57:38.15#ibcon#about to read 3, iclass 33, count 0 2006.173.23:57:38.19#ibcon#read 3, iclass 33, count 0 2006.173.23:57:38.19#ibcon#about to read 4, iclass 33, count 0 2006.173.23:57:38.19#ibcon#read 4, iclass 33, count 0 2006.173.23:57:38.19#ibcon#about to read 5, iclass 33, count 0 2006.173.23:57:38.19#ibcon#read 5, iclass 33, count 0 2006.173.23:57:38.19#ibcon#about to read 6, iclass 33, count 0 2006.173.23:57:38.19#ibcon#read 6, iclass 33, count 0 2006.173.23:57:38.19#ibcon#end of sib2, iclass 33, count 0 2006.173.23:57:38.19#ibcon#*after write, iclass 33, count 0 2006.173.23:57:38.19#ibcon#*before return 0, iclass 33, count 0 2006.173.23:57:38.19#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.173.23:57:38.19#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.173.23:57:38.19#ibcon#about to clear, iclass 33 cls_cnt 0 2006.173.23:57:38.19#ibcon#cleared, iclass 33 cls_cnt 0 2006.173.23:57:38.19$vck44/vb=5,4 2006.173.23:57:38.19#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.173.23:57:38.19#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.173.23:57:38.19#ibcon#ireg 11 cls_cnt 2 2006.173.23:57:38.19#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.23:57:38.25#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.173.23:57:38.25#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.23:57:38.25#ibcon#enter wrdev, iclass 35, count 2 2006.173.23:57:38.25#ibcon#first serial, iclass 35, count 2 2006.173.23:57:38.25#ibcon#enter sib2, iclass 35, count 2 2006.173.23:57:38.25#ibcon#flushed, iclass 35, count 2 2006.173.23:57:38.25#ibcon#about to write, iclass 35, count 2 2006.173.23:57:38.25#ibcon#wrote, iclass 35, count 2 2006.173.23:57:38.25#ibcon#about to read 3, iclass 35, count 2 2006.173.23:57:38.27#ibcon#read 3, iclass 35, count 2 2006.173.23:57:38.27#ibcon#about to read 4, iclass 35, count 2 2006.173.23:57:38.27#ibcon#read 4, iclass 35, count 2 2006.173.23:57:38.27#ibcon#about to read 5, iclass 35, count 2 2006.173.23:57:38.27#ibcon#read 5, iclass 35, count 2 2006.173.23:57:38.27#ibcon#about to read 6, iclass 35, count 2 2006.173.23:57:38.27#ibcon#read 6, iclass 35, count 2 2006.173.23:57:38.27#ibcon#end of sib2, iclass 35, count 2 2006.173.23:57:38.27#ibcon#*mode == 0, iclass 35, count 2 2006.173.23:57:38.27#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.173.23:57:38.27#ibcon#[27=AT05-04\r\n] 2006.173.23:57:38.27#ibcon#*before write, iclass 35, count 2 2006.173.23:57:38.27#ibcon#enter sib2, iclass 35, count 2 2006.173.23:57:38.27#ibcon#flushed, iclass 35, count 2 2006.173.23:57:38.27#ibcon#about to write, iclass 35, count 2 2006.173.23:57:38.27#ibcon#wrote, iclass 35, count 2 2006.173.23:57:38.27#ibcon#about to read 3, iclass 35, count 2 2006.173.23:57:38.30#ibcon#read 3, iclass 35, count 2 2006.173.23:57:38.30#ibcon#about to read 4, iclass 35, count 2 2006.173.23:57:38.30#ibcon#read 4, iclass 35, count 2 2006.173.23:57:38.30#ibcon#about to read 5, iclass 35, count 2 2006.173.23:57:38.30#ibcon#read 5, iclass 35, count 2 2006.173.23:57:38.30#ibcon#about to read 6, iclass 35, count 2 2006.173.23:57:38.30#ibcon#read 6, iclass 35, count 2 2006.173.23:57:38.30#ibcon#end of sib2, iclass 35, count 2 2006.173.23:57:38.30#ibcon#*after write, iclass 35, count 2 2006.173.23:57:38.30#ibcon#*before return 0, iclass 35, count 2 2006.173.23:57:38.30#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.173.23:57:38.30#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.173.23:57:38.30#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.173.23:57:38.30#ibcon#ireg 7 cls_cnt 0 2006.173.23:57:38.30#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.23:57:38.42#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.173.23:57:38.42#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.23:57:38.42#ibcon#enter wrdev, iclass 35, count 0 2006.173.23:57:38.42#ibcon#first serial, iclass 35, count 0 2006.173.23:57:38.42#ibcon#enter sib2, iclass 35, count 0 2006.173.23:57:38.42#ibcon#flushed, iclass 35, count 0 2006.173.23:57:38.42#ibcon#about to write, iclass 35, count 0 2006.173.23:57:38.42#ibcon#wrote, iclass 35, count 0 2006.173.23:57:38.42#ibcon#about to read 3, iclass 35, count 0 2006.173.23:57:38.44#ibcon#read 3, iclass 35, count 0 2006.173.23:57:38.44#ibcon#about to read 4, iclass 35, count 0 2006.173.23:57:38.44#ibcon#read 4, iclass 35, count 0 2006.173.23:57:38.44#ibcon#about to read 5, iclass 35, count 0 2006.173.23:57:38.44#ibcon#read 5, iclass 35, count 0 2006.173.23:57:38.44#ibcon#about to read 6, iclass 35, count 0 2006.173.23:57:38.44#ibcon#read 6, iclass 35, count 0 2006.173.23:57:38.44#ibcon#end of sib2, iclass 35, count 0 2006.173.23:57:38.44#ibcon#*mode == 0, iclass 35, count 0 2006.173.23:57:38.44#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.173.23:57:38.44#ibcon#[27=USB\r\n] 2006.173.23:57:38.44#ibcon#*before write, iclass 35, count 0 2006.173.23:57:38.44#ibcon#enter sib2, iclass 35, count 0 2006.173.23:57:38.44#ibcon#flushed, iclass 35, count 0 2006.173.23:57:38.44#ibcon#about to write, iclass 35, count 0 2006.173.23:57:38.44#ibcon#wrote, iclass 35, count 0 2006.173.23:57:38.44#ibcon#about to read 3, iclass 35, count 0 2006.173.23:57:38.47#ibcon#read 3, iclass 35, count 0 2006.173.23:57:38.47#ibcon#about to read 4, iclass 35, count 0 2006.173.23:57:38.47#ibcon#read 4, iclass 35, count 0 2006.173.23:57:38.47#ibcon#about to read 5, iclass 35, count 0 2006.173.23:57:38.47#ibcon#read 5, iclass 35, count 0 2006.173.23:57:38.47#ibcon#about to read 6, iclass 35, count 0 2006.173.23:57:38.47#ibcon#read 6, iclass 35, count 0 2006.173.23:57:38.47#ibcon#end of sib2, iclass 35, count 0 2006.173.23:57:38.47#ibcon#*after write, iclass 35, count 0 2006.173.23:57:38.47#ibcon#*before return 0, iclass 35, count 0 2006.173.23:57:38.47#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.173.23:57:38.47#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.173.23:57:38.47#ibcon#about to clear, iclass 35 cls_cnt 0 2006.173.23:57:38.47#ibcon#cleared, iclass 35 cls_cnt 0 2006.173.23:57:38.47$vck44/vblo=6,719.99 2006.173.23:57:38.47#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.173.23:57:38.47#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.173.23:57:38.47#ibcon#ireg 17 cls_cnt 0 2006.173.23:57:38.47#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.23:57:38.47#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.173.23:57:38.47#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.23:57:38.47#ibcon#enter wrdev, iclass 37, count 0 2006.173.23:57:38.47#ibcon#first serial, iclass 37, count 0 2006.173.23:57:38.47#ibcon#enter sib2, iclass 37, count 0 2006.173.23:57:38.47#ibcon#flushed, iclass 37, count 0 2006.173.23:57:38.47#ibcon#about to write, iclass 37, count 0 2006.173.23:57:38.47#ibcon#wrote, iclass 37, count 0 2006.173.23:57:38.47#ibcon#about to read 3, iclass 37, count 0 2006.173.23:57:38.49#ibcon#read 3, iclass 37, count 0 2006.173.23:57:38.49#ibcon#about to read 4, iclass 37, count 0 2006.173.23:57:38.49#ibcon#read 4, iclass 37, count 0 2006.173.23:57:38.49#ibcon#about to read 5, iclass 37, count 0 2006.173.23:57:38.49#ibcon#read 5, iclass 37, count 0 2006.173.23:57:38.49#ibcon#about to read 6, iclass 37, count 0 2006.173.23:57:38.49#ibcon#read 6, iclass 37, count 0 2006.173.23:57:38.49#ibcon#end of sib2, iclass 37, count 0 2006.173.23:57:38.49#ibcon#*mode == 0, iclass 37, count 0 2006.173.23:57:38.49#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.173.23:57:38.49#ibcon#[28=FRQ=06,719.99\r\n] 2006.173.23:57:38.49#ibcon#*before write, iclass 37, count 0 2006.173.23:57:38.49#ibcon#enter sib2, iclass 37, count 0 2006.173.23:57:38.49#ibcon#flushed, iclass 37, count 0 2006.173.23:57:38.49#ibcon#about to write, iclass 37, count 0 2006.173.23:57:38.49#ibcon#wrote, iclass 37, count 0 2006.173.23:57:38.49#ibcon#about to read 3, iclass 37, count 0 2006.173.23:57:38.53#ibcon#read 3, iclass 37, count 0 2006.173.23:57:38.53#ibcon#about to read 4, iclass 37, count 0 2006.173.23:57:38.53#ibcon#read 4, iclass 37, count 0 2006.173.23:57:38.53#ibcon#about to read 5, iclass 37, count 0 2006.173.23:57:38.53#ibcon#read 5, iclass 37, count 0 2006.173.23:57:38.53#ibcon#about to read 6, iclass 37, count 0 2006.173.23:57:38.53#ibcon#read 6, iclass 37, count 0 2006.173.23:57:38.53#ibcon#end of sib2, iclass 37, count 0 2006.173.23:57:38.53#ibcon#*after write, iclass 37, count 0 2006.173.23:57:38.53#ibcon#*before return 0, iclass 37, count 0 2006.173.23:57:38.53#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.173.23:57:38.53#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.173.23:57:38.53#ibcon#about to clear, iclass 37 cls_cnt 0 2006.173.23:57:38.53#ibcon#cleared, iclass 37 cls_cnt 0 2006.173.23:57:38.53$vck44/vb=6,4 2006.173.23:57:38.53#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.173.23:57:38.53#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.173.23:57:38.53#ibcon#ireg 11 cls_cnt 2 2006.173.23:57:38.53#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.23:57:38.59#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.173.23:57:38.59#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.23:57:38.59#ibcon#enter wrdev, iclass 39, count 2 2006.173.23:57:38.59#ibcon#first serial, iclass 39, count 2 2006.173.23:57:38.59#ibcon#enter sib2, iclass 39, count 2 2006.173.23:57:38.59#ibcon#flushed, iclass 39, count 2 2006.173.23:57:38.59#ibcon#about to write, iclass 39, count 2 2006.173.23:57:38.59#ibcon#wrote, iclass 39, count 2 2006.173.23:57:38.59#ibcon#about to read 3, iclass 39, count 2 2006.173.23:57:38.61#ibcon#read 3, iclass 39, count 2 2006.173.23:57:38.61#ibcon#about to read 4, iclass 39, count 2 2006.173.23:57:38.61#ibcon#read 4, iclass 39, count 2 2006.173.23:57:38.61#ibcon#about to read 5, iclass 39, count 2 2006.173.23:57:38.61#ibcon#read 5, iclass 39, count 2 2006.173.23:57:38.61#ibcon#about to read 6, iclass 39, count 2 2006.173.23:57:38.61#ibcon#read 6, iclass 39, count 2 2006.173.23:57:38.61#ibcon#end of sib2, iclass 39, count 2 2006.173.23:57:38.61#ibcon#*mode == 0, iclass 39, count 2 2006.173.23:57:38.61#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.173.23:57:38.61#ibcon#[27=AT06-04\r\n] 2006.173.23:57:38.61#ibcon#*before write, iclass 39, count 2 2006.173.23:57:38.61#ibcon#enter sib2, iclass 39, count 2 2006.173.23:57:38.61#ibcon#flushed, iclass 39, count 2 2006.173.23:57:38.61#ibcon#about to write, iclass 39, count 2 2006.173.23:57:38.61#ibcon#wrote, iclass 39, count 2 2006.173.23:57:38.61#ibcon#about to read 3, iclass 39, count 2 2006.173.23:57:38.64#ibcon#read 3, iclass 39, count 2 2006.173.23:57:38.64#ibcon#about to read 4, iclass 39, count 2 2006.173.23:57:38.64#ibcon#read 4, iclass 39, count 2 2006.173.23:57:38.64#ibcon#about to read 5, iclass 39, count 2 2006.173.23:57:38.64#ibcon#read 5, iclass 39, count 2 2006.173.23:57:38.64#ibcon#about to read 6, iclass 39, count 2 2006.173.23:57:38.64#ibcon#read 6, iclass 39, count 2 2006.173.23:57:38.64#ibcon#end of sib2, iclass 39, count 2 2006.173.23:57:38.64#ibcon#*after write, iclass 39, count 2 2006.173.23:57:38.64#ibcon#*before return 0, iclass 39, count 2 2006.173.23:57:38.64#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.173.23:57:38.64#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.173.23:57:38.64#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.173.23:57:38.64#ibcon#ireg 7 cls_cnt 0 2006.173.23:57:38.64#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.23:57:38.76#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.173.23:57:38.76#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.23:57:38.76#ibcon#enter wrdev, iclass 39, count 0 2006.173.23:57:38.76#ibcon#first serial, iclass 39, count 0 2006.173.23:57:38.76#ibcon#enter sib2, iclass 39, count 0 2006.173.23:57:38.76#ibcon#flushed, iclass 39, count 0 2006.173.23:57:38.76#ibcon#about to write, iclass 39, count 0 2006.173.23:57:38.76#ibcon#wrote, iclass 39, count 0 2006.173.23:57:38.76#ibcon#about to read 3, iclass 39, count 0 2006.173.23:57:38.78#ibcon#read 3, iclass 39, count 0 2006.173.23:57:38.78#ibcon#about to read 4, iclass 39, count 0 2006.173.23:57:38.78#ibcon#read 4, iclass 39, count 0 2006.173.23:57:38.78#ibcon#about to read 5, iclass 39, count 0 2006.173.23:57:38.78#ibcon#read 5, iclass 39, count 0 2006.173.23:57:38.78#ibcon#about to read 6, iclass 39, count 0 2006.173.23:57:38.78#ibcon#read 6, iclass 39, count 0 2006.173.23:57:38.78#ibcon#end of sib2, iclass 39, count 0 2006.173.23:57:38.78#ibcon#*mode == 0, iclass 39, count 0 2006.173.23:57:38.78#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.173.23:57:38.78#ibcon#[27=USB\r\n] 2006.173.23:57:38.78#ibcon#*before write, iclass 39, count 0 2006.173.23:57:38.78#ibcon#enter sib2, iclass 39, count 0 2006.173.23:57:38.78#ibcon#flushed, iclass 39, count 0 2006.173.23:57:38.78#ibcon#about to write, iclass 39, count 0 2006.173.23:57:38.78#ibcon#wrote, iclass 39, count 0 2006.173.23:57:38.78#ibcon#about to read 3, iclass 39, count 0 2006.173.23:57:38.81#ibcon#read 3, iclass 39, count 0 2006.173.23:57:38.81#ibcon#about to read 4, iclass 39, count 0 2006.173.23:57:38.81#ibcon#read 4, iclass 39, count 0 2006.173.23:57:38.81#ibcon#about to read 5, iclass 39, count 0 2006.173.23:57:38.81#ibcon#read 5, iclass 39, count 0 2006.173.23:57:38.81#ibcon#about to read 6, iclass 39, count 0 2006.173.23:57:38.81#ibcon#read 6, iclass 39, count 0 2006.173.23:57:38.81#ibcon#end of sib2, iclass 39, count 0 2006.173.23:57:38.81#ibcon#*after write, iclass 39, count 0 2006.173.23:57:38.81#ibcon#*before return 0, iclass 39, count 0 2006.173.23:57:38.81#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.173.23:57:38.81#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.173.23:57:38.81#ibcon#about to clear, iclass 39 cls_cnt 0 2006.173.23:57:38.81#ibcon#cleared, iclass 39 cls_cnt 0 2006.173.23:57:38.81$vck44/vblo=7,734.99 2006.173.23:57:38.81#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.173.23:57:38.81#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.173.23:57:38.81#ibcon#ireg 17 cls_cnt 0 2006.173.23:57:38.81#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.23:57:38.81#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.173.23:57:38.81#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.23:57:38.81#ibcon#enter wrdev, iclass 3, count 0 2006.173.23:57:38.81#ibcon#first serial, iclass 3, count 0 2006.173.23:57:38.81#ibcon#enter sib2, iclass 3, count 0 2006.173.23:57:38.81#ibcon#flushed, iclass 3, count 0 2006.173.23:57:38.81#ibcon#about to write, iclass 3, count 0 2006.173.23:57:38.81#ibcon#wrote, iclass 3, count 0 2006.173.23:57:38.81#ibcon#about to read 3, iclass 3, count 0 2006.173.23:57:38.83#ibcon#read 3, iclass 3, count 0 2006.173.23:57:38.83#ibcon#about to read 4, iclass 3, count 0 2006.173.23:57:38.83#ibcon#read 4, iclass 3, count 0 2006.173.23:57:38.83#ibcon#about to read 5, iclass 3, count 0 2006.173.23:57:38.83#ibcon#read 5, iclass 3, count 0 2006.173.23:57:38.83#ibcon#about to read 6, iclass 3, count 0 2006.173.23:57:38.83#ibcon#read 6, iclass 3, count 0 2006.173.23:57:38.83#ibcon#end of sib2, iclass 3, count 0 2006.173.23:57:38.83#ibcon#*mode == 0, iclass 3, count 0 2006.173.23:57:38.83#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.173.23:57:38.83#ibcon#[28=FRQ=07,734.99\r\n] 2006.173.23:57:38.83#ibcon#*before write, iclass 3, count 0 2006.173.23:57:38.83#ibcon#enter sib2, iclass 3, count 0 2006.173.23:57:38.83#ibcon#flushed, iclass 3, count 0 2006.173.23:57:38.83#ibcon#about to write, iclass 3, count 0 2006.173.23:57:38.83#ibcon#wrote, iclass 3, count 0 2006.173.23:57:38.83#ibcon#about to read 3, iclass 3, count 0 2006.173.23:57:38.87#ibcon#read 3, iclass 3, count 0 2006.173.23:57:38.87#ibcon#about to read 4, iclass 3, count 0 2006.173.23:57:38.87#ibcon#read 4, iclass 3, count 0 2006.173.23:57:38.87#ibcon#about to read 5, iclass 3, count 0 2006.173.23:57:38.87#ibcon#read 5, iclass 3, count 0 2006.173.23:57:38.87#ibcon#about to read 6, iclass 3, count 0 2006.173.23:57:38.87#ibcon#read 6, iclass 3, count 0 2006.173.23:57:38.87#ibcon#end of sib2, iclass 3, count 0 2006.173.23:57:38.87#ibcon#*after write, iclass 3, count 0 2006.173.23:57:38.87#ibcon#*before return 0, iclass 3, count 0 2006.173.23:57:38.87#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.173.23:57:38.87#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.173.23:57:38.87#ibcon#about to clear, iclass 3 cls_cnt 0 2006.173.23:57:38.87#ibcon#cleared, iclass 3 cls_cnt 0 2006.173.23:57:38.87$vck44/vb=7,4 2006.173.23:57:38.87#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.173.23:57:38.87#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.173.23:57:38.87#ibcon#ireg 11 cls_cnt 2 2006.173.23:57:38.87#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.23:57:38.93#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.173.23:57:38.93#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.23:57:38.93#ibcon#enter wrdev, iclass 5, count 2 2006.173.23:57:38.93#ibcon#first serial, iclass 5, count 2 2006.173.23:57:38.93#ibcon#enter sib2, iclass 5, count 2 2006.173.23:57:38.93#ibcon#flushed, iclass 5, count 2 2006.173.23:57:38.93#ibcon#about to write, iclass 5, count 2 2006.173.23:57:38.93#ibcon#wrote, iclass 5, count 2 2006.173.23:57:38.93#ibcon#about to read 3, iclass 5, count 2 2006.173.23:57:38.95#ibcon#read 3, iclass 5, count 2 2006.173.23:57:38.95#ibcon#about to read 4, iclass 5, count 2 2006.173.23:57:38.95#ibcon#read 4, iclass 5, count 2 2006.173.23:57:38.95#ibcon#about to read 5, iclass 5, count 2 2006.173.23:57:38.95#ibcon#read 5, iclass 5, count 2 2006.173.23:57:38.95#ibcon#about to read 6, iclass 5, count 2 2006.173.23:57:38.95#ibcon#read 6, iclass 5, count 2 2006.173.23:57:38.95#ibcon#end of sib2, iclass 5, count 2 2006.173.23:57:38.95#ibcon#*mode == 0, iclass 5, count 2 2006.173.23:57:38.95#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.173.23:57:38.95#ibcon#[27=AT07-04\r\n] 2006.173.23:57:38.95#ibcon#*before write, iclass 5, count 2 2006.173.23:57:38.95#ibcon#enter sib2, iclass 5, count 2 2006.173.23:57:38.95#ibcon#flushed, iclass 5, count 2 2006.173.23:57:38.95#ibcon#about to write, iclass 5, count 2 2006.173.23:57:38.95#ibcon#wrote, iclass 5, count 2 2006.173.23:57:38.95#ibcon#about to read 3, iclass 5, count 2 2006.173.23:57:38.98#ibcon#read 3, iclass 5, count 2 2006.173.23:57:38.98#ibcon#about to read 4, iclass 5, count 2 2006.173.23:57:38.98#ibcon#read 4, iclass 5, count 2 2006.173.23:57:38.98#ibcon#about to read 5, iclass 5, count 2 2006.173.23:57:38.98#ibcon#read 5, iclass 5, count 2 2006.173.23:57:38.98#ibcon#about to read 6, iclass 5, count 2 2006.173.23:57:38.98#ibcon#read 6, iclass 5, count 2 2006.173.23:57:38.98#ibcon#end of sib2, iclass 5, count 2 2006.173.23:57:38.98#ibcon#*after write, iclass 5, count 2 2006.173.23:57:38.98#ibcon#*before return 0, iclass 5, count 2 2006.173.23:57:38.98#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.173.23:57:38.98#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.173.23:57:38.98#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.173.23:57:38.98#ibcon#ireg 7 cls_cnt 0 2006.173.23:57:38.98#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.23:57:39.10#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.173.23:57:39.10#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.23:57:39.10#ibcon#enter wrdev, iclass 5, count 0 2006.173.23:57:39.10#ibcon#first serial, iclass 5, count 0 2006.173.23:57:39.10#ibcon#enter sib2, iclass 5, count 0 2006.173.23:57:39.10#ibcon#flushed, iclass 5, count 0 2006.173.23:57:39.10#ibcon#about to write, iclass 5, count 0 2006.173.23:57:39.10#ibcon#wrote, iclass 5, count 0 2006.173.23:57:39.10#ibcon#about to read 3, iclass 5, count 0 2006.173.23:57:39.12#ibcon#read 3, iclass 5, count 0 2006.173.23:57:39.12#ibcon#about to read 4, iclass 5, count 0 2006.173.23:57:39.12#ibcon#read 4, iclass 5, count 0 2006.173.23:57:39.12#ibcon#about to read 5, iclass 5, count 0 2006.173.23:57:39.12#ibcon#read 5, iclass 5, count 0 2006.173.23:57:39.12#ibcon#about to read 6, iclass 5, count 0 2006.173.23:57:39.12#ibcon#read 6, iclass 5, count 0 2006.173.23:57:39.12#ibcon#end of sib2, iclass 5, count 0 2006.173.23:57:39.12#ibcon#*mode == 0, iclass 5, count 0 2006.173.23:57:39.12#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.173.23:57:39.12#ibcon#[27=USB\r\n] 2006.173.23:57:39.12#ibcon#*before write, iclass 5, count 0 2006.173.23:57:39.12#ibcon#enter sib2, iclass 5, count 0 2006.173.23:57:39.12#ibcon#flushed, iclass 5, count 0 2006.173.23:57:39.12#ibcon#about to write, iclass 5, count 0 2006.173.23:57:39.12#ibcon#wrote, iclass 5, count 0 2006.173.23:57:39.12#ibcon#about to read 3, iclass 5, count 0 2006.173.23:57:39.15#ibcon#read 3, iclass 5, count 0 2006.173.23:57:39.15#ibcon#about to read 4, iclass 5, count 0 2006.173.23:57:39.15#ibcon#read 4, iclass 5, count 0 2006.173.23:57:39.15#ibcon#about to read 5, iclass 5, count 0 2006.173.23:57:39.15#ibcon#read 5, iclass 5, count 0 2006.173.23:57:39.15#ibcon#about to read 6, iclass 5, count 0 2006.173.23:57:39.15#ibcon#read 6, iclass 5, count 0 2006.173.23:57:39.15#ibcon#end of sib2, iclass 5, count 0 2006.173.23:57:39.15#ibcon#*after write, iclass 5, count 0 2006.173.23:57:39.15#ibcon#*before return 0, iclass 5, count 0 2006.173.23:57:39.15#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.173.23:57:39.15#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.173.23:57:39.15#ibcon#about to clear, iclass 5 cls_cnt 0 2006.173.23:57:39.15#ibcon#cleared, iclass 5 cls_cnt 0 2006.173.23:57:39.15$vck44/vblo=8,744.99 2006.173.23:57:39.15#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.173.23:57:39.15#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.173.23:57:39.15#ibcon#ireg 17 cls_cnt 0 2006.173.23:57:39.15#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.23:57:39.15#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.173.23:57:39.15#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.23:57:39.15#ibcon#enter wrdev, iclass 7, count 0 2006.173.23:57:39.15#ibcon#first serial, iclass 7, count 0 2006.173.23:57:39.15#ibcon#enter sib2, iclass 7, count 0 2006.173.23:57:39.15#ibcon#flushed, iclass 7, count 0 2006.173.23:57:39.15#ibcon#about to write, iclass 7, count 0 2006.173.23:57:39.15#ibcon#wrote, iclass 7, count 0 2006.173.23:57:39.15#ibcon#about to read 3, iclass 7, count 0 2006.173.23:57:39.17#ibcon#read 3, iclass 7, count 0 2006.173.23:57:39.17#ibcon#about to read 4, iclass 7, count 0 2006.173.23:57:39.17#ibcon#read 4, iclass 7, count 0 2006.173.23:57:39.17#ibcon#about to read 5, iclass 7, count 0 2006.173.23:57:39.17#ibcon#read 5, iclass 7, count 0 2006.173.23:57:39.17#ibcon#about to read 6, iclass 7, count 0 2006.173.23:57:39.17#ibcon#read 6, iclass 7, count 0 2006.173.23:57:39.17#ibcon#end of sib2, iclass 7, count 0 2006.173.23:57:39.17#ibcon#*mode == 0, iclass 7, count 0 2006.173.23:57:39.17#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.173.23:57:39.17#ibcon#[28=FRQ=08,744.99\r\n] 2006.173.23:57:39.17#ibcon#*before write, iclass 7, count 0 2006.173.23:57:39.17#ibcon#enter sib2, iclass 7, count 0 2006.173.23:57:39.17#ibcon#flushed, iclass 7, count 0 2006.173.23:57:39.17#ibcon#about to write, iclass 7, count 0 2006.173.23:57:39.17#ibcon#wrote, iclass 7, count 0 2006.173.23:57:39.17#ibcon#about to read 3, iclass 7, count 0 2006.173.23:57:39.21#ibcon#read 3, iclass 7, count 0 2006.173.23:57:39.21#ibcon#about to read 4, iclass 7, count 0 2006.173.23:57:39.21#ibcon#read 4, iclass 7, count 0 2006.173.23:57:39.21#ibcon#about to read 5, iclass 7, count 0 2006.173.23:57:39.21#ibcon#read 5, iclass 7, count 0 2006.173.23:57:39.21#ibcon#about to read 6, iclass 7, count 0 2006.173.23:57:39.21#ibcon#read 6, iclass 7, count 0 2006.173.23:57:39.21#ibcon#end of sib2, iclass 7, count 0 2006.173.23:57:39.21#ibcon#*after write, iclass 7, count 0 2006.173.23:57:39.21#ibcon#*before return 0, iclass 7, count 0 2006.173.23:57:39.21#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.173.23:57:39.21#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.173.23:57:39.21#ibcon#about to clear, iclass 7 cls_cnt 0 2006.173.23:57:39.21#ibcon#cleared, iclass 7 cls_cnt 0 2006.173.23:57:39.21$vck44/vb=8,4 2006.173.23:57:39.21#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.173.23:57:39.21#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.173.23:57:39.21#ibcon#ireg 11 cls_cnt 2 2006.173.23:57:39.21#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.23:57:39.27#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.173.23:57:39.27#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.23:57:39.27#ibcon#enter wrdev, iclass 11, count 2 2006.173.23:57:39.27#ibcon#first serial, iclass 11, count 2 2006.173.23:57:39.27#ibcon#enter sib2, iclass 11, count 2 2006.173.23:57:39.27#ibcon#flushed, iclass 11, count 2 2006.173.23:57:39.27#ibcon#about to write, iclass 11, count 2 2006.173.23:57:39.27#ibcon#wrote, iclass 11, count 2 2006.173.23:57:39.27#ibcon#about to read 3, iclass 11, count 2 2006.173.23:57:39.29#ibcon#read 3, iclass 11, count 2 2006.173.23:57:39.29#ibcon#about to read 4, iclass 11, count 2 2006.173.23:57:39.29#ibcon#read 4, iclass 11, count 2 2006.173.23:57:39.29#ibcon#about to read 5, iclass 11, count 2 2006.173.23:57:39.29#ibcon#read 5, iclass 11, count 2 2006.173.23:57:39.29#ibcon#about to read 6, iclass 11, count 2 2006.173.23:57:39.29#ibcon#read 6, iclass 11, count 2 2006.173.23:57:39.29#ibcon#end of sib2, iclass 11, count 2 2006.173.23:57:39.29#ibcon#*mode == 0, iclass 11, count 2 2006.173.23:57:39.29#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.173.23:57:39.29#ibcon#[27=AT08-04\r\n] 2006.173.23:57:39.29#ibcon#*before write, iclass 11, count 2 2006.173.23:57:39.29#ibcon#enter sib2, iclass 11, count 2 2006.173.23:57:39.29#ibcon#flushed, iclass 11, count 2 2006.173.23:57:39.29#ibcon#about to write, iclass 11, count 2 2006.173.23:57:39.29#ibcon#wrote, iclass 11, count 2 2006.173.23:57:39.29#ibcon#about to read 3, iclass 11, count 2 2006.173.23:57:39.32#ibcon#read 3, iclass 11, count 2 2006.173.23:57:39.32#ibcon#about to read 4, iclass 11, count 2 2006.173.23:57:39.32#ibcon#read 4, iclass 11, count 2 2006.173.23:57:39.32#ibcon#about to read 5, iclass 11, count 2 2006.173.23:57:39.32#ibcon#read 5, iclass 11, count 2 2006.173.23:57:39.32#ibcon#about to read 6, iclass 11, count 2 2006.173.23:57:39.32#ibcon#read 6, iclass 11, count 2 2006.173.23:57:39.32#ibcon#end of sib2, iclass 11, count 2 2006.173.23:57:39.32#ibcon#*after write, iclass 11, count 2 2006.173.23:57:39.32#ibcon#*before return 0, iclass 11, count 2 2006.173.23:57:39.32#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.173.23:57:39.32#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.173.23:57:39.32#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.173.23:57:39.32#ibcon#ireg 7 cls_cnt 0 2006.173.23:57:39.32#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.23:57:39.44#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.173.23:57:39.44#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.23:57:39.44#ibcon#enter wrdev, iclass 11, count 0 2006.173.23:57:39.44#ibcon#first serial, iclass 11, count 0 2006.173.23:57:39.44#ibcon#enter sib2, iclass 11, count 0 2006.173.23:57:39.44#ibcon#flushed, iclass 11, count 0 2006.173.23:57:39.44#ibcon#about to write, iclass 11, count 0 2006.173.23:57:39.44#ibcon#wrote, iclass 11, count 0 2006.173.23:57:39.44#ibcon#about to read 3, iclass 11, count 0 2006.173.23:57:39.46#ibcon#read 3, iclass 11, count 0 2006.173.23:57:39.46#ibcon#about to read 4, iclass 11, count 0 2006.173.23:57:39.46#ibcon#read 4, iclass 11, count 0 2006.173.23:57:39.46#ibcon#about to read 5, iclass 11, count 0 2006.173.23:57:39.46#ibcon#read 5, iclass 11, count 0 2006.173.23:57:39.46#ibcon#about to read 6, iclass 11, count 0 2006.173.23:57:39.46#ibcon#read 6, iclass 11, count 0 2006.173.23:57:39.46#ibcon#end of sib2, iclass 11, count 0 2006.173.23:57:39.46#ibcon#*mode == 0, iclass 11, count 0 2006.173.23:57:39.46#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.173.23:57:39.46#ibcon#[27=USB\r\n] 2006.173.23:57:39.46#ibcon#*before write, iclass 11, count 0 2006.173.23:57:39.46#ibcon#enter sib2, iclass 11, count 0 2006.173.23:57:39.46#ibcon#flushed, iclass 11, count 0 2006.173.23:57:39.46#ibcon#about to write, iclass 11, count 0 2006.173.23:57:39.46#ibcon#wrote, iclass 11, count 0 2006.173.23:57:39.46#ibcon#about to read 3, iclass 11, count 0 2006.173.23:57:39.49#ibcon#read 3, iclass 11, count 0 2006.173.23:57:39.49#ibcon#about to read 4, iclass 11, count 0 2006.173.23:57:39.49#ibcon#read 4, iclass 11, count 0 2006.173.23:57:39.49#ibcon#about to read 5, iclass 11, count 0 2006.173.23:57:39.49#ibcon#read 5, iclass 11, count 0 2006.173.23:57:39.49#ibcon#about to read 6, iclass 11, count 0 2006.173.23:57:39.49#ibcon#read 6, iclass 11, count 0 2006.173.23:57:39.49#ibcon#end of sib2, iclass 11, count 0 2006.173.23:57:39.49#ibcon#*after write, iclass 11, count 0 2006.173.23:57:39.49#ibcon#*before return 0, iclass 11, count 0 2006.173.23:57:39.49#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.173.23:57:39.49#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.173.23:57:39.49#ibcon#about to clear, iclass 11 cls_cnt 0 2006.173.23:57:39.49#ibcon#cleared, iclass 11 cls_cnt 0 2006.173.23:57:39.49$vck44/vabw=wide 2006.173.23:57:39.49#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.173.23:57:39.49#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.173.23:57:39.49#ibcon#ireg 8 cls_cnt 0 2006.173.23:57:39.49#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.23:57:39.49#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.173.23:57:39.49#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.23:57:39.49#ibcon#enter wrdev, iclass 13, count 0 2006.173.23:57:39.49#ibcon#first serial, iclass 13, count 0 2006.173.23:57:39.49#ibcon#enter sib2, iclass 13, count 0 2006.173.23:57:39.49#ibcon#flushed, iclass 13, count 0 2006.173.23:57:39.49#ibcon#about to write, iclass 13, count 0 2006.173.23:57:39.49#ibcon#wrote, iclass 13, count 0 2006.173.23:57:39.49#ibcon#about to read 3, iclass 13, count 0 2006.173.23:57:39.51#ibcon#read 3, iclass 13, count 0 2006.173.23:57:39.51#ibcon#about to read 4, iclass 13, count 0 2006.173.23:57:39.51#ibcon#read 4, iclass 13, count 0 2006.173.23:57:39.51#ibcon#about to read 5, iclass 13, count 0 2006.173.23:57:39.51#ibcon#read 5, iclass 13, count 0 2006.173.23:57:39.51#ibcon#about to read 6, iclass 13, count 0 2006.173.23:57:39.51#ibcon#read 6, iclass 13, count 0 2006.173.23:57:39.51#ibcon#end of sib2, iclass 13, count 0 2006.173.23:57:39.51#ibcon#*mode == 0, iclass 13, count 0 2006.173.23:57:39.51#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.173.23:57:39.51#ibcon#[25=BW32\r\n] 2006.173.23:57:39.51#ibcon#*before write, iclass 13, count 0 2006.173.23:57:39.51#ibcon#enter sib2, iclass 13, count 0 2006.173.23:57:39.51#ibcon#flushed, iclass 13, count 0 2006.173.23:57:39.51#ibcon#about to write, iclass 13, count 0 2006.173.23:57:39.51#ibcon#wrote, iclass 13, count 0 2006.173.23:57:39.51#ibcon#about to read 3, iclass 13, count 0 2006.173.23:57:39.54#ibcon#read 3, iclass 13, count 0 2006.173.23:57:39.54#ibcon#about to read 4, iclass 13, count 0 2006.173.23:57:39.54#ibcon#read 4, iclass 13, count 0 2006.173.23:57:39.54#ibcon#about to read 5, iclass 13, count 0 2006.173.23:57:39.54#ibcon#read 5, iclass 13, count 0 2006.173.23:57:39.54#ibcon#about to read 6, iclass 13, count 0 2006.173.23:57:39.54#ibcon#read 6, iclass 13, count 0 2006.173.23:57:39.54#ibcon#end of sib2, iclass 13, count 0 2006.173.23:57:39.54#ibcon#*after write, iclass 13, count 0 2006.173.23:57:39.54#ibcon#*before return 0, iclass 13, count 0 2006.173.23:57:39.54#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.173.23:57:39.54#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.173.23:57:39.54#ibcon#about to clear, iclass 13 cls_cnt 0 2006.173.23:57:39.54#ibcon#cleared, iclass 13 cls_cnt 0 2006.173.23:57:39.54$vck44/vbbw=wide 2006.173.23:57:39.54#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.173.23:57:39.54#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.173.23:57:39.54#ibcon#ireg 8 cls_cnt 0 2006.173.23:57:39.54#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.23:57:39.61#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.173.23:57:39.61#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.23:57:39.61#ibcon#enter wrdev, iclass 15, count 0 2006.173.23:57:39.61#ibcon#first serial, iclass 15, count 0 2006.173.23:57:39.61#ibcon#enter sib2, iclass 15, count 0 2006.173.23:57:39.61#ibcon#flushed, iclass 15, count 0 2006.173.23:57:39.61#ibcon#about to write, iclass 15, count 0 2006.173.23:57:39.61#ibcon#wrote, iclass 15, count 0 2006.173.23:57:39.61#ibcon#about to read 3, iclass 15, count 0 2006.173.23:57:39.63#ibcon#read 3, iclass 15, count 0 2006.173.23:57:39.63#ibcon#about to read 4, iclass 15, count 0 2006.173.23:57:39.63#ibcon#read 4, iclass 15, count 0 2006.173.23:57:39.63#ibcon#about to read 5, iclass 15, count 0 2006.173.23:57:39.63#ibcon#read 5, iclass 15, count 0 2006.173.23:57:39.63#ibcon#about to read 6, iclass 15, count 0 2006.173.23:57:39.63#ibcon#read 6, iclass 15, count 0 2006.173.23:57:39.63#ibcon#end of sib2, iclass 15, count 0 2006.173.23:57:39.63#ibcon#*mode == 0, iclass 15, count 0 2006.173.23:57:39.63#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.173.23:57:39.63#ibcon#[27=BW32\r\n] 2006.173.23:57:39.63#ibcon#*before write, iclass 15, count 0 2006.173.23:57:39.63#ibcon#enter sib2, iclass 15, count 0 2006.173.23:57:39.63#ibcon#flushed, iclass 15, count 0 2006.173.23:57:39.63#ibcon#about to write, iclass 15, count 0 2006.173.23:57:39.63#ibcon#wrote, iclass 15, count 0 2006.173.23:57:39.63#ibcon#about to read 3, iclass 15, count 0 2006.173.23:57:39.66#ibcon#read 3, iclass 15, count 0 2006.173.23:57:39.66#ibcon#about to read 4, iclass 15, count 0 2006.173.23:57:39.66#ibcon#read 4, iclass 15, count 0 2006.173.23:57:39.66#ibcon#about to read 5, iclass 15, count 0 2006.173.23:57:39.66#ibcon#read 5, iclass 15, count 0 2006.173.23:57:39.66#ibcon#about to read 6, iclass 15, count 0 2006.173.23:57:39.66#ibcon#read 6, iclass 15, count 0 2006.173.23:57:39.66#ibcon#end of sib2, iclass 15, count 0 2006.173.23:57:39.66#ibcon#*after write, iclass 15, count 0 2006.173.23:57:39.66#ibcon#*before return 0, iclass 15, count 0 2006.173.23:57:39.66#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.173.23:57:39.66#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.173.23:57:39.66#ibcon#about to clear, iclass 15 cls_cnt 0 2006.173.23:57:39.66#ibcon#cleared, iclass 15 cls_cnt 0 2006.173.23:57:39.66$setupk4/ifdk4 2006.173.23:57:39.66$ifdk4/lo= 2006.173.23:57:39.66$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.173.23:57:39.66$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.173.23:57:39.66$ifdk4/patch= 2006.173.23:57:39.66$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.173.23:57:39.66$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.173.23:57:39.66$setupk4/!*+20s 2006.173.23:57:39.81#abcon#<5=/10 0.8 2.4 24.02 831003.4\r\n> 2006.173.23:57:39.83#abcon#{5=INTERFACE CLEAR} 2006.173.23:57:39.89#abcon#[5=S1D000X0/0*\r\n] 2006.173.23:57:45.13#trakl#Source acquired 2006.173.23:57:47.13#flagr#flagr/antenna,acquired 2006.173.23:57:49.98#abcon#<5=/10 0.8 2.4 24.03 841003.4\r\n> 2006.173.23:57:50.00#abcon#{5=INTERFACE CLEAR} 2006.173.23:57:50.06#abcon#[5=S1D000X0/0*\r\n] 2006.173.23:57:54.17$setupk4/"tpicd 2006.173.23:57:54.17$setupk4/echo=off 2006.173.23:57:54.17$setupk4/xlog=off 2006.173.23:57:54.17:!2006.173.23:59:29 2006.173.23:59:29.00:preob 2006.173.23:59:30.13/onsource/TRACKING 2006.173.23:59:30.13:!2006.173.23:59:39 2006.173.23:59:39.00:"tape 2006.173.23:59:39.00:"st=record 2006.173.23:59:39.00:data_valid=on 2006.173.23:59:39.00:midob 2006.173.23:59:39.14/onsource/TRACKING 2006.173.23:59:39.14/wx/24.12,1003.4,84 2006.173.23:59:39.21/cable/+6.5091E-03 2006.173.23:59:40.30/va/01,07,usb,yes,34,37 2006.173.23:59:40.30/va/02,06,usb,yes,34,35 2006.173.23:59:40.30/va/03,05,usb,yes,44,45 2006.173.23:59:40.30/va/04,06,usb,yes,35,37 2006.173.23:59:40.30/va/05,04,usb,yes,27,28 2006.173.23:59:40.30/va/06,03,usb,yes,38,38 2006.173.23:59:40.30/va/07,04,usb,yes,31,32 2006.173.23:59:40.30/va/08,04,usb,yes,26,32 2006.173.23:59:40.53/valo/01,524.99,yes,locked 2006.173.23:59:40.53/valo/02,534.99,yes,locked 2006.173.23:59:40.53/valo/03,564.99,yes,locked 2006.173.23:59:40.53/valo/04,624.99,yes,locked 2006.173.23:59:40.53/valo/05,734.99,yes,locked 2006.173.23:59:40.53/valo/06,814.99,yes,locked 2006.173.23:59:40.53/valo/07,864.99,yes,locked 2006.173.23:59:40.53/valo/08,884.99,yes,locked 2006.173.23:59:41.62/vb/01,04,usb,yes,29,27 2006.173.23:59:41.62/vb/02,04,usb,yes,31,31 2006.173.23:59:41.62/vb/03,04,usb,yes,28,31 2006.173.23:59:41.62/vb/04,04,usb,yes,32,31 2006.173.23:59:41.62/vb/05,04,usb,yes,25,27 2006.173.23:59:41.62/vb/06,04,usb,yes,29,26 2006.173.23:59:41.62/vb/07,04,usb,yes,29,29 2006.173.23:59:41.62/vb/08,04,usb,yes,27,30 2006.173.23:59:41.86/vblo/01,629.99,yes,locked 2006.173.23:59:41.86/vblo/02,634.99,yes,locked 2006.173.23:59:41.86/vblo/03,649.99,yes,locked 2006.173.23:59:41.86/vblo/04,679.99,yes,locked 2006.173.23:59:41.86/vblo/05,709.99,yes,locked 2006.173.23:59:41.86/vblo/06,719.99,yes,locked 2006.173.23:59:41.86/vblo/07,734.99,yes,locked 2006.173.23:59:41.86/vblo/08,744.99,yes,locked 2006.173.23:59:42.01/vabw/8 2006.173.23:59:42.16/vbbw/8 2006.173.23:59:42.25/xfe/off,on,15.7 2006.173.23:59:42.63/ifatt/23,28,28,28 2006.173.23:59:43.07/fmout-gps/S +3.96E-07 2006.173.23:59:43.11:!2006.174.00:02:59 2006.174.00:02:59.01:data_valid=off 2006.174.00:02:59.01:"et 2006.174.00:02:59.01:!+3s 2006.174.00:03:02.02:"tape 2006.174.00:03:02.02:postob 2006.174.00:03:02.12/cable/+6.5066E-03 2006.174.00:03:02.12/wx/24.21,1003.4,83 2006.174.00:03:02.18/fmout-gps/S +3.96E-07 2006.174.00:03:02.18:scan_name=174-0006,jd0606,230 2006.174.00:03:02.18:source=cta26,033930.94,-014635.8,2000.0,ccw 2006.174.00:03:03.14#flagr#flagr/antenna,new-source 2006.174.00:03:03.14:checkk5 2006.174.00:03:03.55/chk_autoobs//k5ts1/ autoobs is running! 2006.174.00:03:03.95/chk_autoobs//k5ts2/ autoobs is running! 2006.174.00:03:04.36/chk_autoobs//k5ts3/ autoobs is running! 2006.174.00:03:04.74/chk_autoobs//k5ts4/ autoobs is running! 2006.174.00:03:05.13/chk_obsdata//k5ts1/T1732359??a.dat file size is correct (nominal:800MB, actual:796MB). 2006.174.00:03:05.51/chk_obsdata//k5ts2/T1732359??b.dat file size is correct (nominal:800MB, actual:796MB). 2006.174.00:03:05.91/chk_obsdata//k5ts3/T1732359??c.dat file size is correct (nominal:800MB, actual:796MB). 2006.174.00:03:06.34/chk_obsdata//k5ts4/T1732359??d.dat file size is correct (nominal:800MB, actual:796MB). 2006.174.00:03:07.06/k5log//k5ts1_log_newline 2006.174.00:03:07.77/k5log//k5ts2_log_newline 2006.174.00:03:08.48/k5log//k5ts3_log_newline 2006.174.00:03:09.20/k5log//k5ts4_log_newline 2006.174.00:03:09.23/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.174.00:03:09.23:setupk4=1 2006.174.00:03:09.23$setupk4/echo=on 2006.174.00:03:09.23$setupk4/pcalon 2006.174.00:03:09.23$pcalon/"no phase cal control is implemented here 2006.174.00:03:09.23$setupk4/"tpicd=stop 2006.174.00:03:09.23$setupk4/"rec=synch_on 2006.174.00:03:09.23$setupk4/"rec_mode=128 2006.174.00:03:09.23$setupk4/!* 2006.174.00:03:09.23$setupk4/recpk4 2006.174.00:03:09.23$recpk4/recpatch= 2006.174.00:03:09.24$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.174.00:03:09.24$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.174.00:03:09.24$setupk4/vck44 2006.174.00:03:09.24$vck44/valo=1,524.99 2006.174.00:03:09.24#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.174.00:03:09.24#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.174.00:03:09.24#ibcon#ireg 17 cls_cnt 0 2006.174.00:03:09.24#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.174.00:03:09.24#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.174.00:03:09.24#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.174.00:03:09.24#ibcon#enter wrdev, iclass 6, count 0 2006.174.00:03:09.24#ibcon#first serial, iclass 6, count 0 2006.174.00:03:09.24#ibcon#enter sib2, iclass 6, count 0 2006.174.00:03:09.24#ibcon#flushed, iclass 6, count 0 2006.174.00:03:09.24#ibcon#about to write, iclass 6, count 0 2006.174.00:03:09.24#ibcon#wrote, iclass 6, count 0 2006.174.00:03:09.24#ibcon#about to read 3, iclass 6, count 0 2006.174.00:03:09.26#ibcon#read 3, iclass 6, count 0 2006.174.00:03:09.26#ibcon#about to read 4, iclass 6, count 0 2006.174.00:03:09.26#ibcon#read 4, iclass 6, count 0 2006.174.00:03:09.26#ibcon#about to read 5, iclass 6, count 0 2006.174.00:03:09.26#ibcon#read 5, iclass 6, count 0 2006.174.00:03:09.26#ibcon#about to read 6, iclass 6, count 0 2006.174.00:03:09.26#ibcon#read 6, iclass 6, count 0 2006.174.00:03:09.26#ibcon#end of sib2, iclass 6, count 0 2006.174.00:03:09.26#ibcon#*mode == 0, iclass 6, count 0 2006.174.00:03:09.26#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.174.00:03:09.26#ibcon#[26=FRQ=01,524.99\r\n] 2006.174.00:03:09.26#ibcon#*before write, iclass 6, count 0 2006.174.00:03:09.26#ibcon#enter sib2, iclass 6, count 0 2006.174.00:03:09.26#ibcon#flushed, iclass 6, count 0 2006.174.00:03:09.26#ibcon#about to write, iclass 6, count 0 2006.174.00:03:09.26#ibcon#wrote, iclass 6, count 0 2006.174.00:03:09.26#ibcon#about to read 3, iclass 6, count 0 2006.174.00:03:09.31#ibcon#read 3, iclass 6, count 0 2006.174.00:03:09.31#ibcon#about to read 4, iclass 6, count 0 2006.174.00:03:09.31#ibcon#read 4, iclass 6, count 0 2006.174.00:03:09.31#ibcon#about to read 5, iclass 6, count 0 2006.174.00:03:09.31#ibcon#read 5, iclass 6, count 0 2006.174.00:03:09.31#ibcon#about to read 6, iclass 6, count 0 2006.174.00:03:09.31#ibcon#read 6, iclass 6, count 0 2006.174.00:03:09.31#ibcon#end of sib2, iclass 6, count 0 2006.174.00:03:09.31#ibcon#*after write, iclass 6, count 0 2006.174.00:03:09.31#ibcon#*before return 0, iclass 6, count 0 2006.174.00:03:09.31#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.174.00:03:09.31#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.174.00:03:09.31#ibcon#about to clear, iclass 6 cls_cnt 0 2006.174.00:03:09.31#ibcon#cleared, iclass 6 cls_cnt 0 2006.174.00:03:09.31$vck44/va=1,7 2006.174.00:03:09.31#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.174.00:03:09.31#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.174.00:03:09.31#ibcon#ireg 11 cls_cnt 2 2006.174.00:03:09.31#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.174.00:03:09.31#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.174.00:03:09.31#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.174.00:03:09.31#ibcon#enter wrdev, iclass 10, count 2 2006.174.00:03:09.31#ibcon#first serial, iclass 10, count 2 2006.174.00:03:09.31#ibcon#enter sib2, iclass 10, count 2 2006.174.00:03:09.31#ibcon#flushed, iclass 10, count 2 2006.174.00:03:09.31#ibcon#about to write, iclass 10, count 2 2006.174.00:03:09.31#ibcon#wrote, iclass 10, count 2 2006.174.00:03:09.31#ibcon#about to read 3, iclass 10, count 2 2006.174.00:03:09.33#ibcon#read 3, iclass 10, count 2 2006.174.00:03:09.33#ibcon#about to read 4, iclass 10, count 2 2006.174.00:03:09.33#ibcon#read 4, iclass 10, count 2 2006.174.00:03:09.33#ibcon#about to read 5, iclass 10, count 2 2006.174.00:03:09.33#ibcon#read 5, iclass 10, count 2 2006.174.00:03:09.33#ibcon#about to read 6, iclass 10, count 2 2006.174.00:03:09.33#ibcon#read 6, iclass 10, count 2 2006.174.00:03:09.33#ibcon#end of sib2, iclass 10, count 2 2006.174.00:03:09.33#ibcon#*mode == 0, iclass 10, count 2 2006.174.00:03:09.33#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.174.00:03:09.33#ibcon#[25=AT01-07\r\n] 2006.174.00:03:09.33#ibcon#*before write, iclass 10, count 2 2006.174.00:03:09.33#ibcon#enter sib2, iclass 10, count 2 2006.174.00:03:09.33#ibcon#flushed, iclass 10, count 2 2006.174.00:03:09.33#ibcon#about to write, iclass 10, count 2 2006.174.00:03:09.33#ibcon#wrote, iclass 10, count 2 2006.174.00:03:09.33#ibcon#about to read 3, iclass 10, count 2 2006.174.00:03:09.36#ibcon#read 3, iclass 10, count 2 2006.174.00:03:09.36#ibcon#about to read 4, iclass 10, count 2 2006.174.00:03:09.36#ibcon#read 4, iclass 10, count 2 2006.174.00:03:09.36#ibcon#about to read 5, iclass 10, count 2 2006.174.00:03:09.36#ibcon#read 5, iclass 10, count 2 2006.174.00:03:09.36#ibcon#about to read 6, iclass 10, count 2 2006.174.00:03:09.36#ibcon#read 6, iclass 10, count 2 2006.174.00:03:09.36#ibcon#end of sib2, iclass 10, count 2 2006.174.00:03:09.36#ibcon#*after write, iclass 10, count 2 2006.174.00:03:09.36#ibcon#*before return 0, iclass 10, count 2 2006.174.00:03:09.36#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.174.00:03:09.36#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.174.00:03:09.36#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.174.00:03:09.36#ibcon#ireg 7 cls_cnt 0 2006.174.00:03:09.36#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.174.00:03:09.48#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.174.00:03:09.48#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.174.00:03:09.48#ibcon#enter wrdev, iclass 10, count 0 2006.174.00:03:09.48#ibcon#first serial, iclass 10, count 0 2006.174.00:03:09.48#ibcon#enter sib2, iclass 10, count 0 2006.174.00:03:09.48#ibcon#flushed, iclass 10, count 0 2006.174.00:03:09.48#ibcon#about to write, iclass 10, count 0 2006.174.00:03:09.48#ibcon#wrote, iclass 10, count 0 2006.174.00:03:09.48#ibcon#about to read 3, iclass 10, count 0 2006.174.00:03:09.50#ibcon#read 3, iclass 10, count 0 2006.174.00:03:09.50#ibcon#about to read 4, iclass 10, count 0 2006.174.00:03:09.50#ibcon#read 4, iclass 10, count 0 2006.174.00:03:09.50#ibcon#about to read 5, iclass 10, count 0 2006.174.00:03:09.50#ibcon#read 5, iclass 10, count 0 2006.174.00:03:09.50#ibcon#about to read 6, iclass 10, count 0 2006.174.00:03:09.50#ibcon#read 6, iclass 10, count 0 2006.174.00:03:09.50#ibcon#end of sib2, iclass 10, count 0 2006.174.00:03:09.50#ibcon#*mode == 0, iclass 10, count 0 2006.174.00:03:09.50#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.174.00:03:09.50#ibcon#[25=USB\r\n] 2006.174.00:03:09.50#ibcon#*before write, iclass 10, count 0 2006.174.00:03:09.50#ibcon#enter sib2, iclass 10, count 0 2006.174.00:03:09.50#ibcon#flushed, iclass 10, count 0 2006.174.00:03:09.50#ibcon#about to write, iclass 10, count 0 2006.174.00:03:09.50#ibcon#wrote, iclass 10, count 0 2006.174.00:03:09.50#ibcon#about to read 3, iclass 10, count 0 2006.174.00:03:09.53#ibcon#read 3, iclass 10, count 0 2006.174.00:03:09.53#ibcon#about to read 4, iclass 10, count 0 2006.174.00:03:09.53#ibcon#read 4, iclass 10, count 0 2006.174.00:03:09.53#ibcon#about to read 5, iclass 10, count 0 2006.174.00:03:09.53#ibcon#read 5, iclass 10, count 0 2006.174.00:03:09.53#ibcon#about to read 6, iclass 10, count 0 2006.174.00:03:09.53#ibcon#read 6, iclass 10, count 0 2006.174.00:03:09.53#ibcon#end of sib2, iclass 10, count 0 2006.174.00:03:09.53#ibcon#*after write, iclass 10, count 0 2006.174.00:03:09.53#ibcon#*before return 0, iclass 10, count 0 2006.174.00:03:09.53#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.174.00:03:09.53#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.174.00:03:09.53#ibcon#about to clear, iclass 10 cls_cnt 0 2006.174.00:03:09.53#ibcon#cleared, iclass 10 cls_cnt 0 2006.174.00:03:09.53$vck44/valo=2,534.99 2006.174.00:03:09.53#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.174.00:03:09.53#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.174.00:03:09.53#ibcon#ireg 17 cls_cnt 0 2006.174.00:03:09.53#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.174.00:03:09.53#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.174.00:03:09.53#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.174.00:03:09.53#ibcon#enter wrdev, iclass 12, count 0 2006.174.00:03:09.53#ibcon#first serial, iclass 12, count 0 2006.174.00:03:09.53#ibcon#enter sib2, iclass 12, count 0 2006.174.00:03:09.53#ibcon#flushed, iclass 12, count 0 2006.174.00:03:09.53#ibcon#about to write, iclass 12, count 0 2006.174.00:03:09.53#ibcon#wrote, iclass 12, count 0 2006.174.00:03:09.53#ibcon#about to read 3, iclass 12, count 0 2006.174.00:03:09.55#ibcon#read 3, iclass 12, count 0 2006.174.00:03:09.55#ibcon#about to read 4, iclass 12, count 0 2006.174.00:03:09.55#ibcon#read 4, iclass 12, count 0 2006.174.00:03:09.55#ibcon#about to read 5, iclass 12, count 0 2006.174.00:03:09.55#ibcon#read 5, iclass 12, count 0 2006.174.00:03:09.55#ibcon#about to read 6, iclass 12, count 0 2006.174.00:03:09.55#ibcon#read 6, iclass 12, count 0 2006.174.00:03:09.55#ibcon#end of sib2, iclass 12, count 0 2006.174.00:03:09.55#ibcon#*mode == 0, iclass 12, count 0 2006.174.00:03:09.55#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.174.00:03:09.55#ibcon#[26=FRQ=02,534.99\r\n] 2006.174.00:03:09.55#ibcon#*before write, iclass 12, count 0 2006.174.00:03:09.55#ibcon#enter sib2, iclass 12, count 0 2006.174.00:03:09.55#ibcon#flushed, iclass 12, count 0 2006.174.00:03:09.55#ibcon#about to write, iclass 12, count 0 2006.174.00:03:09.55#ibcon#wrote, iclass 12, count 0 2006.174.00:03:09.55#ibcon#about to read 3, iclass 12, count 0 2006.174.00:03:09.59#ibcon#read 3, iclass 12, count 0 2006.174.00:03:09.59#ibcon#about to read 4, iclass 12, count 0 2006.174.00:03:09.59#ibcon#read 4, iclass 12, count 0 2006.174.00:03:09.59#ibcon#about to read 5, iclass 12, count 0 2006.174.00:03:09.59#ibcon#read 5, iclass 12, count 0 2006.174.00:03:09.59#ibcon#about to read 6, iclass 12, count 0 2006.174.00:03:09.59#ibcon#read 6, iclass 12, count 0 2006.174.00:03:09.59#ibcon#end of sib2, iclass 12, count 0 2006.174.00:03:09.59#ibcon#*after write, iclass 12, count 0 2006.174.00:03:09.59#ibcon#*before return 0, iclass 12, count 0 2006.174.00:03:09.59#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.174.00:03:09.59#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.174.00:03:09.59#ibcon#about to clear, iclass 12 cls_cnt 0 2006.174.00:03:09.59#ibcon#cleared, iclass 12 cls_cnt 0 2006.174.00:03:09.59$vck44/va=2,6 2006.174.00:03:09.59#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.174.00:03:09.59#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.174.00:03:09.59#ibcon#ireg 11 cls_cnt 2 2006.174.00:03:09.59#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.174.00:03:09.65#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.174.00:03:09.65#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.174.00:03:09.65#ibcon#enter wrdev, iclass 14, count 2 2006.174.00:03:09.65#ibcon#first serial, iclass 14, count 2 2006.174.00:03:09.65#ibcon#enter sib2, iclass 14, count 2 2006.174.00:03:09.65#ibcon#flushed, iclass 14, count 2 2006.174.00:03:09.65#ibcon#about to write, iclass 14, count 2 2006.174.00:03:09.65#ibcon#wrote, iclass 14, count 2 2006.174.00:03:09.65#ibcon#about to read 3, iclass 14, count 2 2006.174.00:03:09.67#ibcon#read 3, iclass 14, count 2 2006.174.00:03:09.67#ibcon#about to read 4, iclass 14, count 2 2006.174.00:03:09.67#ibcon#read 4, iclass 14, count 2 2006.174.00:03:09.67#ibcon#about to read 5, iclass 14, count 2 2006.174.00:03:09.67#ibcon#read 5, iclass 14, count 2 2006.174.00:03:09.67#ibcon#about to read 6, iclass 14, count 2 2006.174.00:03:09.67#ibcon#read 6, iclass 14, count 2 2006.174.00:03:09.67#ibcon#end of sib2, iclass 14, count 2 2006.174.00:03:09.67#ibcon#*mode == 0, iclass 14, count 2 2006.174.00:03:09.67#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.174.00:03:09.67#ibcon#[25=AT02-06\r\n] 2006.174.00:03:09.67#ibcon#*before write, iclass 14, count 2 2006.174.00:03:09.67#ibcon#enter sib2, iclass 14, count 2 2006.174.00:03:09.67#ibcon#flushed, iclass 14, count 2 2006.174.00:03:09.67#ibcon#about to write, iclass 14, count 2 2006.174.00:03:09.67#ibcon#wrote, iclass 14, count 2 2006.174.00:03:09.67#ibcon#about to read 3, iclass 14, count 2 2006.174.00:03:09.70#ibcon#read 3, iclass 14, count 2 2006.174.00:03:09.70#ibcon#about to read 4, iclass 14, count 2 2006.174.00:03:09.70#ibcon#read 4, iclass 14, count 2 2006.174.00:03:09.70#ibcon#about to read 5, iclass 14, count 2 2006.174.00:03:09.70#ibcon#read 5, iclass 14, count 2 2006.174.00:03:09.70#ibcon#about to read 6, iclass 14, count 2 2006.174.00:03:09.70#ibcon#read 6, iclass 14, count 2 2006.174.00:03:09.70#ibcon#end of sib2, iclass 14, count 2 2006.174.00:03:09.70#ibcon#*after write, iclass 14, count 2 2006.174.00:03:09.70#ibcon#*before return 0, iclass 14, count 2 2006.174.00:03:09.70#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.174.00:03:09.70#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.174.00:03:09.70#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.174.00:03:09.70#ibcon#ireg 7 cls_cnt 0 2006.174.00:03:09.70#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.174.00:03:09.82#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.174.00:03:09.82#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.174.00:03:09.82#ibcon#enter wrdev, iclass 14, count 0 2006.174.00:03:09.82#ibcon#first serial, iclass 14, count 0 2006.174.00:03:09.82#ibcon#enter sib2, iclass 14, count 0 2006.174.00:03:09.82#ibcon#flushed, iclass 14, count 0 2006.174.00:03:09.82#ibcon#about to write, iclass 14, count 0 2006.174.00:03:09.82#ibcon#wrote, iclass 14, count 0 2006.174.00:03:09.82#ibcon#about to read 3, iclass 14, count 0 2006.174.00:03:09.84#ibcon#read 3, iclass 14, count 0 2006.174.00:03:09.84#ibcon#about to read 4, iclass 14, count 0 2006.174.00:03:09.84#ibcon#read 4, iclass 14, count 0 2006.174.00:03:09.84#ibcon#about to read 5, iclass 14, count 0 2006.174.00:03:09.84#ibcon#read 5, iclass 14, count 0 2006.174.00:03:09.84#ibcon#about to read 6, iclass 14, count 0 2006.174.00:03:09.84#ibcon#read 6, iclass 14, count 0 2006.174.00:03:09.84#ibcon#end of sib2, iclass 14, count 0 2006.174.00:03:09.84#ibcon#*mode == 0, iclass 14, count 0 2006.174.00:03:09.84#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.174.00:03:09.84#ibcon#[25=USB\r\n] 2006.174.00:03:09.84#ibcon#*before write, iclass 14, count 0 2006.174.00:03:09.84#ibcon#enter sib2, iclass 14, count 0 2006.174.00:03:09.84#ibcon#flushed, iclass 14, count 0 2006.174.00:03:09.84#ibcon#about to write, iclass 14, count 0 2006.174.00:03:09.84#ibcon#wrote, iclass 14, count 0 2006.174.00:03:09.84#ibcon#about to read 3, iclass 14, count 0 2006.174.00:03:09.87#ibcon#read 3, iclass 14, count 0 2006.174.00:03:09.87#ibcon#about to read 4, iclass 14, count 0 2006.174.00:03:09.87#ibcon#read 4, iclass 14, count 0 2006.174.00:03:09.87#ibcon#about to read 5, iclass 14, count 0 2006.174.00:03:09.87#ibcon#read 5, iclass 14, count 0 2006.174.00:03:09.87#ibcon#about to read 6, iclass 14, count 0 2006.174.00:03:09.87#ibcon#read 6, iclass 14, count 0 2006.174.00:03:09.87#ibcon#end of sib2, iclass 14, count 0 2006.174.00:03:09.87#ibcon#*after write, iclass 14, count 0 2006.174.00:03:09.87#ibcon#*before return 0, iclass 14, count 0 2006.174.00:03:09.87#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.174.00:03:09.87#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.174.00:03:09.87#ibcon#about to clear, iclass 14 cls_cnt 0 2006.174.00:03:09.87#ibcon#cleared, iclass 14 cls_cnt 0 2006.174.00:03:09.87$vck44/valo=3,564.99 2006.174.00:03:09.87#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.174.00:03:09.87#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.174.00:03:09.87#ibcon#ireg 17 cls_cnt 0 2006.174.00:03:09.87#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.174.00:03:09.87#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.174.00:03:09.87#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.174.00:03:09.87#ibcon#enter wrdev, iclass 16, count 0 2006.174.00:03:09.87#ibcon#first serial, iclass 16, count 0 2006.174.00:03:09.87#ibcon#enter sib2, iclass 16, count 0 2006.174.00:03:09.87#ibcon#flushed, iclass 16, count 0 2006.174.00:03:09.87#ibcon#about to write, iclass 16, count 0 2006.174.00:03:09.87#ibcon#wrote, iclass 16, count 0 2006.174.00:03:09.87#ibcon#about to read 3, iclass 16, count 0 2006.174.00:03:09.89#ibcon#read 3, iclass 16, count 0 2006.174.00:03:09.89#ibcon#about to read 4, iclass 16, count 0 2006.174.00:03:09.89#ibcon#read 4, iclass 16, count 0 2006.174.00:03:09.89#ibcon#about to read 5, iclass 16, count 0 2006.174.00:03:09.89#ibcon#read 5, iclass 16, count 0 2006.174.00:03:09.89#ibcon#about to read 6, iclass 16, count 0 2006.174.00:03:09.89#ibcon#read 6, iclass 16, count 0 2006.174.00:03:09.89#ibcon#end of sib2, iclass 16, count 0 2006.174.00:03:09.89#ibcon#*mode == 0, iclass 16, count 0 2006.174.00:03:09.89#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.174.00:03:09.89#ibcon#[26=FRQ=03,564.99\r\n] 2006.174.00:03:09.89#ibcon#*before write, iclass 16, count 0 2006.174.00:03:09.89#ibcon#enter sib2, iclass 16, count 0 2006.174.00:03:09.89#ibcon#flushed, iclass 16, count 0 2006.174.00:03:09.89#ibcon#about to write, iclass 16, count 0 2006.174.00:03:09.89#ibcon#wrote, iclass 16, count 0 2006.174.00:03:09.89#ibcon#about to read 3, iclass 16, count 0 2006.174.00:03:09.93#ibcon#read 3, iclass 16, count 0 2006.174.00:03:09.93#ibcon#about to read 4, iclass 16, count 0 2006.174.00:03:09.93#ibcon#read 4, iclass 16, count 0 2006.174.00:03:09.93#ibcon#about to read 5, iclass 16, count 0 2006.174.00:03:09.93#ibcon#read 5, iclass 16, count 0 2006.174.00:03:09.93#ibcon#about to read 6, iclass 16, count 0 2006.174.00:03:09.93#ibcon#read 6, iclass 16, count 0 2006.174.00:03:09.93#ibcon#end of sib2, iclass 16, count 0 2006.174.00:03:09.93#ibcon#*after write, iclass 16, count 0 2006.174.00:03:09.93#ibcon#*before return 0, iclass 16, count 0 2006.174.00:03:09.93#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.174.00:03:09.93#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.174.00:03:09.93#ibcon#about to clear, iclass 16 cls_cnt 0 2006.174.00:03:09.93#ibcon#cleared, iclass 16 cls_cnt 0 2006.174.00:03:09.93$vck44/va=3,5 2006.174.00:03:09.93#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.174.00:03:09.93#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.174.00:03:09.93#ibcon#ireg 11 cls_cnt 2 2006.174.00:03:09.93#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.174.00:03:09.99#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.174.00:03:09.99#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.174.00:03:09.99#ibcon#enter wrdev, iclass 18, count 2 2006.174.00:03:09.99#ibcon#first serial, iclass 18, count 2 2006.174.00:03:09.99#ibcon#enter sib2, iclass 18, count 2 2006.174.00:03:09.99#ibcon#flushed, iclass 18, count 2 2006.174.00:03:09.99#ibcon#about to write, iclass 18, count 2 2006.174.00:03:09.99#ibcon#wrote, iclass 18, count 2 2006.174.00:03:09.99#ibcon#about to read 3, iclass 18, count 2 2006.174.00:03:10.01#ibcon#read 3, iclass 18, count 2 2006.174.00:03:10.01#ibcon#about to read 4, iclass 18, count 2 2006.174.00:03:10.01#ibcon#read 4, iclass 18, count 2 2006.174.00:03:10.01#ibcon#about to read 5, iclass 18, count 2 2006.174.00:03:10.01#ibcon#read 5, iclass 18, count 2 2006.174.00:03:10.01#ibcon#about to read 6, iclass 18, count 2 2006.174.00:03:10.01#ibcon#read 6, iclass 18, count 2 2006.174.00:03:10.01#ibcon#end of sib2, iclass 18, count 2 2006.174.00:03:10.01#ibcon#*mode == 0, iclass 18, count 2 2006.174.00:03:10.01#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.174.00:03:10.01#ibcon#[25=AT03-05\r\n] 2006.174.00:03:10.01#ibcon#*before write, iclass 18, count 2 2006.174.00:03:10.01#ibcon#enter sib2, iclass 18, count 2 2006.174.00:03:10.01#ibcon#flushed, iclass 18, count 2 2006.174.00:03:10.01#ibcon#about to write, iclass 18, count 2 2006.174.00:03:10.01#ibcon#wrote, iclass 18, count 2 2006.174.00:03:10.01#ibcon#about to read 3, iclass 18, count 2 2006.174.00:03:10.04#ibcon#read 3, iclass 18, count 2 2006.174.00:03:10.04#ibcon#about to read 4, iclass 18, count 2 2006.174.00:03:10.04#ibcon#read 4, iclass 18, count 2 2006.174.00:03:10.04#ibcon#about to read 5, iclass 18, count 2 2006.174.00:03:10.04#ibcon#read 5, iclass 18, count 2 2006.174.00:03:10.04#ibcon#about to read 6, iclass 18, count 2 2006.174.00:03:10.04#ibcon#read 6, iclass 18, count 2 2006.174.00:03:10.04#ibcon#end of sib2, iclass 18, count 2 2006.174.00:03:10.04#ibcon#*after write, iclass 18, count 2 2006.174.00:03:10.04#ibcon#*before return 0, iclass 18, count 2 2006.174.00:03:10.04#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.174.00:03:10.04#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.174.00:03:10.04#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.174.00:03:10.04#ibcon#ireg 7 cls_cnt 0 2006.174.00:03:10.04#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.174.00:03:10.16#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.174.00:03:10.16#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.174.00:03:10.16#ibcon#enter wrdev, iclass 18, count 0 2006.174.00:03:10.16#ibcon#first serial, iclass 18, count 0 2006.174.00:03:10.16#ibcon#enter sib2, iclass 18, count 0 2006.174.00:03:10.16#ibcon#flushed, iclass 18, count 0 2006.174.00:03:10.16#ibcon#about to write, iclass 18, count 0 2006.174.00:03:10.16#ibcon#wrote, iclass 18, count 0 2006.174.00:03:10.16#ibcon#about to read 3, iclass 18, count 0 2006.174.00:03:10.18#ibcon#read 3, iclass 18, count 0 2006.174.00:03:10.18#ibcon#about to read 4, iclass 18, count 0 2006.174.00:03:10.18#ibcon#read 4, iclass 18, count 0 2006.174.00:03:10.18#ibcon#about to read 5, iclass 18, count 0 2006.174.00:03:10.18#ibcon#read 5, iclass 18, count 0 2006.174.00:03:10.18#ibcon#about to read 6, iclass 18, count 0 2006.174.00:03:10.18#ibcon#read 6, iclass 18, count 0 2006.174.00:03:10.18#ibcon#end of sib2, iclass 18, count 0 2006.174.00:03:10.18#ibcon#*mode == 0, iclass 18, count 0 2006.174.00:03:10.18#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.174.00:03:10.18#ibcon#[25=USB\r\n] 2006.174.00:03:10.18#ibcon#*before write, iclass 18, count 0 2006.174.00:03:10.18#ibcon#enter sib2, iclass 18, count 0 2006.174.00:03:10.18#ibcon#flushed, iclass 18, count 0 2006.174.00:03:10.18#ibcon#about to write, iclass 18, count 0 2006.174.00:03:10.18#ibcon#wrote, iclass 18, count 0 2006.174.00:03:10.18#ibcon#about to read 3, iclass 18, count 0 2006.174.00:03:10.21#ibcon#read 3, iclass 18, count 0 2006.174.00:03:10.21#ibcon#about to read 4, iclass 18, count 0 2006.174.00:03:10.21#ibcon#read 4, iclass 18, count 0 2006.174.00:03:10.21#ibcon#about to read 5, iclass 18, count 0 2006.174.00:03:10.21#ibcon#read 5, iclass 18, count 0 2006.174.00:03:10.21#ibcon#about to read 6, iclass 18, count 0 2006.174.00:03:10.21#ibcon#read 6, iclass 18, count 0 2006.174.00:03:10.21#ibcon#end of sib2, iclass 18, count 0 2006.174.00:03:10.21#ibcon#*after write, iclass 18, count 0 2006.174.00:03:10.21#ibcon#*before return 0, iclass 18, count 0 2006.174.00:03:10.21#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.174.00:03:10.21#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.174.00:03:10.21#ibcon#about to clear, iclass 18 cls_cnt 0 2006.174.00:03:10.21#ibcon#cleared, iclass 18 cls_cnt 0 2006.174.00:03:10.21$vck44/valo=4,624.99 2006.174.00:03:10.21#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.174.00:03:10.21#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.174.00:03:10.21#ibcon#ireg 17 cls_cnt 0 2006.174.00:03:10.21#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.174.00:03:10.21#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.174.00:03:10.21#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.174.00:03:10.21#ibcon#enter wrdev, iclass 20, count 0 2006.174.00:03:10.21#ibcon#first serial, iclass 20, count 0 2006.174.00:03:10.21#ibcon#enter sib2, iclass 20, count 0 2006.174.00:03:10.21#ibcon#flushed, iclass 20, count 0 2006.174.00:03:10.21#ibcon#about to write, iclass 20, count 0 2006.174.00:03:10.21#ibcon#wrote, iclass 20, count 0 2006.174.00:03:10.21#ibcon#about to read 3, iclass 20, count 0 2006.174.00:03:10.23#ibcon#read 3, iclass 20, count 0 2006.174.00:03:10.23#ibcon#about to read 4, iclass 20, count 0 2006.174.00:03:10.23#ibcon#read 4, iclass 20, count 0 2006.174.00:03:10.23#ibcon#about to read 5, iclass 20, count 0 2006.174.00:03:10.23#ibcon#read 5, iclass 20, count 0 2006.174.00:03:10.23#ibcon#about to read 6, iclass 20, count 0 2006.174.00:03:10.23#ibcon#read 6, iclass 20, count 0 2006.174.00:03:10.23#ibcon#end of sib2, iclass 20, count 0 2006.174.00:03:10.23#ibcon#*mode == 0, iclass 20, count 0 2006.174.00:03:10.23#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.174.00:03:10.23#ibcon#[26=FRQ=04,624.99\r\n] 2006.174.00:03:10.23#ibcon#*before write, iclass 20, count 0 2006.174.00:03:10.23#ibcon#enter sib2, iclass 20, count 0 2006.174.00:03:10.23#ibcon#flushed, iclass 20, count 0 2006.174.00:03:10.23#ibcon#about to write, iclass 20, count 0 2006.174.00:03:10.23#ibcon#wrote, iclass 20, count 0 2006.174.00:03:10.23#ibcon#about to read 3, iclass 20, count 0 2006.174.00:03:10.27#ibcon#read 3, iclass 20, count 0 2006.174.00:03:10.27#ibcon#about to read 4, iclass 20, count 0 2006.174.00:03:10.27#ibcon#read 4, iclass 20, count 0 2006.174.00:03:10.27#ibcon#about to read 5, iclass 20, count 0 2006.174.00:03:10.27#ibcon#read 5, iclass 20, count 0 2006.174.00:03:10.27#ibcon#about to read 6, iclass 20, count 0 2006.174.00:03:10.27#ibcon#read 6, iclass 20, count 0 2006.174.00:03:10.27#ibcon#end of sib2, iclass 20, count 0 2006.174.00:03:10.27#ibcon#*after write, iclass 20, count 0 2006.174.00:03:10.27#ibcon#*before return 0, iclass 20, count 0 2006.174.00:03:10.27#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.174.00:03:10.27#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.174.00:03:10.27#ibcon#about to clear, iclass 20 cls_cnt 0 2006.174.00:03:10.27#ibcon#cleared, iclass 20 cls_cnt 0 2006.174.00:03:10.27$vck44/va=4,6 2006.174.00:03:10.27#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.174.00:03:10.27#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.174.00:03:10.27#ibcon#ireg 11 cls_cnt 2 2006.174.00:03:10.27#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.174.00:03:10.33#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.174.00:03:10.33#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.174.00:03:10.33#ibcon#enter wrdev, iclass 22, count 2 2006.174.00:03:10.33#ibcon#first serial, iclass 22, count 2 2006.174.00:03:10.33#ibcon#enter sib2, iclass 22, count 2 2006.174.00:03:10.33#ibcon#flushed, iclass 22, count 2 2006.174.00:03:10.33#ibcon#about to write, iclass 22, count 2 2006.174.00:03:10.33#ibcon#wrote, iclass 22, count 2 2006.174.00:03:10.33#ibcon#about to read 3, iclass 22, count 2 2006.174.00:03:10.35#ibcon#read 3, iclass 22, count 2 2006.174.00:03:10.35#ibcon#about to read 4, iclass 22, count 2 2006.174.00:03:10.35#ibcon#read 4, iclass 22, count 2 2006.174.00:03:10.35#ibcon#about to read 5, iclass 22, count 2 2006.174.00:03:10.35#ibcon#read 5, iclass 22, count 2 2006.174.00:03:10.35#ibcon#about to read 6, iclass 22, count 2 2006.174.00:03:10.35#ibcon#read 6, iclass 22, count 2 2006.174.00:03:10.35#ibcon#end of sib2, iclass 22, count 2 2006.174.00:03:10.35#ibcon#*mode == 0, iclass 22, count 2 2006.174.00:03:10.35#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.174.00:03:10.35#ibcon#[25=AT04-06\r\n] 2006.174.00:03:10.35#ibcon#*before write, iclass 22, count 2 2006.174.00:03:10.35#ibcon#enter sib2, iclass 22, count 2 2006.174.00:03:10.35#ibcon#flushed, iclass 22, count 2 2006.174.00:03:10.35#ibcon#about to write, iclass 22, count 2 2006.174.00:03:10.35#ibcon#wrote, iclass 22, count 2 2006.174.00:03:10.35#ibcon#about to read 3, iclass 22, count 2 2006.174.00:03:10.38#ibcon#read 3, iclass 22, count 2 2006.174.00:03:10.38#ibcon#about to read 4, iclass 22, count 2 2006.174.00:03:10.38#ibcon#read 4, iclass 22, count 2 2006.174.00:03:10.38#ibcon#about to read 5, iclass 22, count 2 2006.174.00:03:10.38#ibcon#read 5, iclass 22, count 2 2006.174.00:03:10.38#ibcon#about to read 6, iclass 22, count 2 2006.174.00:03:10.38#ibcon#read 6, iclass 22, count 2 2006.174.00:03:10.38#ibcon#end of sib2, iclass 22, count 2 2006.174.00:03:10.38#ibcon#*after write, iclass 22, count 2 2006.174.00:03:10.38#ibcon#*before return 0, iclass 22, count 2 2006.174.00:03:10.38#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.174.00:03:10.38#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.174.00:03:10.38#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.174.00:03:10.38#ibcon#ireg 7 cls_cnt 0 2006.174.00:03:10.38#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.174.00:03:10.50#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.174.00:03:10.50#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.174.00:03:10.50#ibcon#enter wrdev, iclass 22, count 0 2006.174.00:03:10.50#ibcon#first serial, iclass 22, count 0 2006.174.00:03:10.50#ibcon#enter sib2, iclass 22, count 0 2006.174.00:03:10.50#ibcon#flushed, iclass 22, count 0 2006.174.00:03:10.50#ibcon#about to write, iclass 22, count 0 2006.174.00:03:10.50#ibcon#wrote, iclass 22, count 0 2006.174.00:03:10.50#ibcon#about to read 3, iclass 22, count 0 2006.174.00:03:10.52#ibcon#read 3, iclass 22, count 0 2006.174.00:03:10.52#ibcon#about to read 4, iclass 22, count 0 2006.174.00:03:10.52#ibcon#read 4, iclass 22, count 0 2006.174.00:03:10.52#ibcon#about to read 5, iclass 22, count 0 2006.174.00:03:10.52#ibcon#read 5, iclass 22, count 0 2006.174.00:03:10.52#ibcon#about to read 6, iclass 22, count 0 2006.174.00:03:10.52#ibcon#read 6, iclass 22, count 0 2006.174.00:03:10.52#ibcon#end of sib2, iclass 22, count 0 2006.174.00:03:10.52#ibcon#*mode == 0, iclass 22, count 0 2006.174.00:03:10.52#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.174.00:03:10.52#ibcon#[25=USB\r\n] 2006.174.00:03:10.52#ibcon#*before write, iclass 22, count 0 2006.174.00:03:10.52#ibcon#enter sib2, iclass 22, count 0 2006.174.00:03:10.52#ibcon#flushed, iclass 22, count 0 2006.174.00:03:10.52#ibcon#about to write, iclass 22, count 0 2006.174.00:03:10.52#ibcon#wrote, iclass 22, count 0 2006.174.00:03:10.52#ibcon#about to read 3, iclass 22, count 0 2006.174.00:03:10.55#ibcon#read 3, iclass 22, count 0 2006.174.00:03:10.55#ibcon#about to read 4, iclass 22, count 0 2006.174.00:03:10.55#ibcon#read 4, iclass 22, count 0 2006.174.00:03:10.55#ibcon#about to read 5, iclass 22, count 0 2006.174.00:03:10.55#ibcon#read 5, iclass 22, count 0 2006.174.00:03:10.55#ibcon#about to read 6, iclass 22, count 0 2006.174.00:03:10.55#ibcon#read 6, iclass 22, count 0 2006.174.00:03:10.55#ibcon#end of sib2, iclass 22, count 0 2006.174.00:03:10.55#ibcon#*after write, iclass 22, count 0 2006.174.00:03:10.55#ibcon#*before return 0, iclass 22, count 0 2006.174.00:03:10.55#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.174.00:03:10.55#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.174.00:03:10.55#ibcon#about to clear, iclass 22 cls_cnt 0 2006.174.00:03:10.55#ibcon#cleared, iclass 22 cls_cnt 0 2006.174.00:03:10.55$vck44/valo=5,734.99 2006.174.00:03:10.55#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.174.00:03:10.55#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.174.00:03:10.55#ibcon#ireg 17 cls_cnt 0 2006.174.00:03:10.55#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.174.00:03:10.55#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.174.00:03:10.55#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.174.00:03:10.55#ibcon#enter wrdev, iclass 24, count 0 2006.174.00:03:10.55#ibcon#first serial, iclass 24, count 0 2006.174.00:03:10.55#ibcon#enter sib2, iclass 24, count 0 2006.174.00:03:10.55#ibcon#flushed, iclass 24, count 0 2006.174.00:03:10.55#ibcon#about to write, iclass 24, count 0 2006.174.00:03:10.55#ibcon#wrote, iclass 24, count 0 2006.174.00:03:10.55#ibcon#about to read 3, iclass 24, count 0 2006.174.00:03:10.57#ibcon#read 3, iclass 24, count 0 2006.174.00:03:10.57#ibcon#about to read 4, iclass 24, count 0 2006.174.00:03:10.57#ibcon#read 4, iclass 24, count 0 2006.174.00:03:10.57#ibcon#about to read 5, iclass 24, count 0 2006.174.00:03:10.57#ibcon#read 5, iclass 24, count 0 2006.174.00:03:10.57#ibcon#about to read 6, iclass 24, count 0 2006.174.00:03:10.57#ibcon#read 6, iclass 24, count 0 2006.174.00:03:10.57#ibcon#end of sib2, iclass 24, count 0 2006.174.00:03:10.57#ibcon#*mode == 0, iclass 24, count 0 2006.174.00:03:10.57#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.174.00:03:10.57#ibcon#[26=FRQ=05,734.99\r\n] 2006.174.00:03:10.57#ibcon#*before write, iclass 24, count 0 2006.174.00:03:10.57#ibcon#enter sib2, iclass 24, count 0 2006.174.00:03:10.57#ibcon#flushed, iclass 24, count 0 2006.174.00:03:10.57#ibcon#about to write, iclass 24, count 0 2006.174.00:03:10.57#ibcon#wrote, iclass 24, count 0 2006.174.00:03:10.57#ibcon#about to read 3, iclass 24, count 0 2006.174.00:03:10.61#ibcon#read 3, iclass 24, count 0 2006.174.00:03:10.61#ibcon#about to read 4, iclass 24, count 0 2006.174.00:03:10.61#ibcon#read 4, iclass 24, count 0 2006.174.00:03:10.61#ibcon#about to read 5, iclass 24, count 0 2006.174.00:03:10.61#ibcon#read 5, iclass 24, count 0 2006.174.00:03:10.61#ibcon#about to read 6, iclass 24, count 0 2006.174.00:03:10.61#ibcon#read 6, iclass 24, count 0 2006.174.00:03:10.61#ibcon#end of sib2, iclass 24, count 0 2006.174.00:03:10.61#ibcon#*after write, iclass 24, count 0 2006.174.00:03:10.61#ibcon#*before return 0, iclass 24, count 0 2006.174.00:03:10.61#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.174.00:03:10.61#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.174.00:03:10.61#ibcon#about to clear, iclass 24 cls_cnt 0 2006.174.00:03:10.61#ibcon#cleared, iclass 24 cls_cnt 0 2006.174.00:03:10.61$vck44/va=5,4 2006.174.00:03:10.61#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.174.00:03:10.61#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.174.00:03:10.61#ibcon#ireg 11 cls_cnt 2 2006.174.00:03:10.61#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.174.00:03:10.67#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.174.00:03:10.67#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.174.00:03:10.67#ibcon#enter wrdev, iclass 26, count 2 2006.174.00:03:10.67#ibcon#first serial, iclass 26, count 2 2006.174.00:03:10.67#ibcon#enter sib2, iclass 26, count 2 2006.174.00:03:10.67#ibcon#flushed, iclass 26, count 2 2006.174.00:03:10.67#ibcon#about to write, iclass 26, count 2 2006.174.00:03:10.67#ibcon#wrote, iclass 26, count 2 2006.174.00:03:10.67#ibcon#about to read 3, iclass 26, count 2 2006.174.00:03:10.69#ibcon#read 3, iclass 26, count 2 2006.174.00:03:10.69#ibcon#about to read 4, iclass 26, count 2 2006.174.00:03:10.69#ibcon#read 4, iclass 26, count 2 2006.174.00:03:10.69#ibcon#about to read 5, iclass 26, count 2 2006.174.00:03:10.69#ibcon#read 5, iclass 26, count 2 2006.174.00:03:10.69#ibcon#about to read 6, iclass 26, count 2 2006.174.00:03:10.69#ibcon#read 6, iclass 26, count 2 2006.174.00:03:10.69#ibcon#end of sib2, iclass 26, count 2 2006.174.00:03:10.69#ibcon#*mode == 0, iclass 26, count 2 2006.174.00:03:10.69#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.174.00:03:10.69#ibcon#[25=AT05-04\r\n] 2006.174.00:03:10.69#ibcon#*before write, iclass 26, count 2 2006.174.00:03:10.69#ibcon#enter sib2, iclass 26, count 2 2006.174.00:03:10.69#ibcon#flushed, iclass 26, count 2 2006.174.00:03:10.69#ibcon#about to write, iclass 26, count 2 2006.174.00:03:10.69#ibcon#wrote, iclass 26, count 2 2006.174.00:03:10.69#ibcon#about to read 3, iclass 26, count 2 2006.174.00:03:10.72#ibcon#read 3, iclass 26, count 2 2006.174.00:03:10.72#ibcon#about to read 4, iclass 26, count 2 2006.174.00:03:10.72#ibcon#read 4, iclass 26, count 2 2006.174.00:03:10.72#ibcon#about to read 5, iclass 26, count 2 2006.174.00:03:10.72#ibcon#read 5, iclass 26, count 2 2006.174.00:03:10.72#ibcon#about to read 6, iclass 26, count 2 2006.174.00:03:10.72#ibcon#read 6, iclass 26, count 2 2006.174.00:03:10.72#ibcon#end of sib2, iclass 26, count 2 2006.174.00:03:10.72#ibcon#*after write, iclass 26, count 2 2006.174.00:03:10.72#ibcon#*before return 0, iclass 26, count 2 2006.174.00:03:10.72#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.174.00:03:10.72#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.174.00:03:10.72#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.174.00:03:10.72#ibcon#ireg 7 cls_cnt 0 2006.174.00:03:10.72#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.174.00:03:10.84#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.174.00:03:10.84#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.174.00:03:10.84#ibcon#enter wrdev, iclass 26, count 0 2006.174.00:03:10.84#ibcon#first serial, iclass 26, count 0 2006.174.00:03:10.84#ibcon#enter sib2, iclass 26, count 0 2006.174.00:03:10.84#ibcon#flushed, iclass 26, count 0 2006.174.00:03:10.84#ibcon#about to write, iclass 26, count 0 2006.174.00:03:10.84#ibcon#wrote, iclass 26, count 0 2006.174.00:03:10.84#ibcon#about to read 3, iclass 26, count 0 2006.174.00:03:10.86#ibcon#read 3, iclass 26, count 0 2006.174.00:03:10.86#ibcon#about to read 4, iclass 26, count 0 2006.174.00:03:10.86#ibcon#read 4, iclass 26, count 0 2006.174.00:03:10.86#ibcon#about to read 5, iclass 26, count 0 2006.174.00:03:10.86#ibcon#read 5, iclass 26, count 0 2006.174.00:03:10.86#ibcon#about to read 6, iclass 26, count 0 2006.174.00:03:10.86#ibcon#read 6, iclass 26, count 0 2006.174.00:03:10.86#ibcon#end of sib2, iclass 26, count 0 2006.174.00:03:10.86#ibcon#*mode == 0, iclass 26, count 0 2006.174.00:03:10.86#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.174.00:03:10.86#ibcon#[25=USB\r\n] 2006.174.00:03:10.86#ibcon#*before write, iclass 26, count 0 2006.174.00:03:10.86#ibcon#enter sib2, iclass 26, count 0 2006.174.00:03:10.86#ibcon#flushed, iclass 26, count 0 2006.174.00:03:10.86#ibcon#about to write, iclass 26, count 0 2006.174.00:03:10.86#ibcon#wrote, iclass 26, count 0 2006.174.00:03:10.86#ibcon#about to read 3, iclass 26, count 0 2006.174.00:03:10.89#ibcon#read 3, iclass 26, count 0 2006.174.00:03:10.89#ibcon#about to read 4, iclass 26, count 0 2006.174.00:03:10.89#ibcon#read 4, iclass 26, count 0 2006.174.00:03:10.89#ibcon#about to read 5, iclass 26, count 0 2006.174.00:03:10.89#ibcon#read 5, iclass 26, count 0 2006.174.00:03:10.89#ibcon#about to read 6, iclass 26, count 0 2006.174.00:03:10.89#ibcon#read 6, iclass 26, count 0 2006.174.00:03:10.89#ibcon#end of sib2, iclass 26, count 0 2006.174.00:03:10.89#ibcon#*after write, iclass 26, count 0 2006.174.00:03:10.89#ibcon#*before return 0, iclass 26, count 0 2006.174.00:03:10.89#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.174.00:03:10.89#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.174.00:03:10.89#ibcon#about to clear, iclass 26 cls_cnt 0 2006.174.00:03:10.89#ibcon#cleared, iclass 26 cls_cnt 0 2006.174.00:03:10.89$vck44/valo=6,814.99 2006.174.00:03:10.89#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.174.00:03:10.89#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.174.00:03:10.89#ibcon#ireg 17 cls_cnt 0 2006.174.00:03:10.89#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.174.00:03:10.89#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.174.00:03:10.89#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.174.00:03:10.89#ibcon#enter wrdev, iclass 28, count 0 2006.174.00:03:10.89#ibcon#first serial, iclass 28, count 0 2006.174.00:03:10.89#ibcon#enter sib2, iclass 28, count 0 2006.174.00:03:10.89#ibcon#flushed, iclass 28, count 0 2006.174.00:03:10.89#ibcon#about to write, iclass 28, count 0 2006.174.00:03:10.89#ibcon#wrote, iclass 28, count 0 2006.174.00:03:10.89#ibcon#about to read 3, iclass 28, count 0 2006.174.00:03:10.91#ibcon#read 3, iclass 28, count 0 2006.174.00:03:10.91#ibcon#about to read 4, iclass 28, count 0 2006.174.00:03:10.91#ibcon#read 4, iclass 28, count 0 2006.174.00:03:10.91#ibcon#about to read 5, iclass 28, count 0 2006.174.00:03:10.91#ibcon#read 5, iclass 28, count 0 2006.174.00:03:10.91#ibcon#about to read 6, iclass 28, count 0 2006.174.00:03:10.91#ibcon#read 6, iclass 28, count 0 2006.174.00:03:10.91#ibcon#end of sib2, iclass 28, count 0 2006.174.00:03:10.91#ibcon#*mode == 0, iclass 28, count 0 2006.174.00:03:10.91#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.174.00:03:10.91#ibcon#[26=FRQ=06,814.99\r\n] 2006.174.00:03:10.91#ibcon#*before write, iclass 28, count 0 2006.174.00:03:10.91#ibcon#enter sib2, iclass 28, count 0 2006.174.00:03:10.91#ibcon#flushed, iclass 28, count 0 2006.174.00:03:10.91#ibcon#about to write, iclass 28, count 0 2006.174.00:03:10.91#ibcon#wrote, iclass 28, count 0 2006.174.00:03:10.91#ibcon#about to read 3, iclass 28, count 0 2006.174.00:03:10.95#ibcon#read 3, iclass 28, count 0 2006.174.00:03:10.95#ibcon#about to read 4, iclass 28, count 0 2006.174.00:03:10.95#ibcon#read 4, iclass 28, count 0 2006.174.00:03:10.95#ibcon#about to read 5, iclass 28, count 0 2006.174.00:03:10.95#ibcon#read 5, iclass 28, count 0 2006.174.00:03:10.95#ibcon#about to read 6, iclass 28, count 0 2006.174.00:03:10.95#ibcon#read 6, iclass 28, count 0 2006.174.00:03:10.95#ibcon#end of sib2, iclass 28, count 0 2006.174.00:03:10.95#ibcon#*after write, iclass 28, count 0 2006.174.00:03:10.95#ibcon#*before return 0, iclass 28, count 0 2006.174.00:03:10.95#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.174.00:03:10.95#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.174.00:03:10.95#ibcon#about to clear, iclass 28 cls_cnt 0 2006.174.00:03:10.95#ibcon#cleared, iclass 28 cls_cnt 0 2006.174.00:03:10.95$vck44/va=6,3 2006.174.00:03:10.95#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.174.00:03:10.95#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.174.00:03:10.95#ibcon#ireg 11 cls_cnt 2 2006.174.00:03:10.95#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.174.00:03:11.01#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.174.00:03:11.01#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.174.00:03:11.01#ibcon#enter wrdev, iclass 30, count 2 2006.174.00:03:11.01#ibcon#first serial, iclass 30, count 2 2006.174.00:03:11.01#ibcon#enter sib2, iclass 30, count 2 2006.174.00:03:11.01#ibcon#flushed, iclass 30, count 2 2006.174.00:03:11.01#ibcon#about to write, iclass 30, count 2 2006.174.00:03:11.01#ibcon#wrote, iclass 30, count 2 2006.174.00:03:11.01#ibcon#about to read 3, iclass 30, count 2 2006.174.00:03:11.03#ibcon#read 3, iclass 30, count 2 2006.174.00:03:11.03#ibcon#about to read 4, iclass 30, count 2 2006.174.00:03:11.03#ibcon#read 4, iclass 30, count 2 2006.174.00:03:11.03#ibcon#about to read 5, iclass 30, count 2 2006.174.00:03:11.03#ibcon#read 5, iclass 30, count 2 2006.174.00:03:11.03#ibcon#about to read 6, iclass 30, count 2 2006.174.00:03:11.03#ibcon#read 6, iclass 30, count 2 2006.174.00:03:11.03#ibcon#end of sib2, iclass 30, count 2 2006.174.00:03:11.03#ibcon#*mode == 0, iclass 30, count 2 2006.174.00:03:11.03#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.174.00:03:11.03#ibcon#[25=AT06-03\r\n] 2006.174.00:03:11.03#ibcon#*before write, iclass 30, count 2 2006.174.00:03:11.03#ibcon#enter sib2, iclass 30, count 2 2006.174.00:03:11.03#ibcon#flushed, iclass 30, count 2 2006.174.00:03:11.03#ibcon#about to write, iclass 30, count 2 2006.174.00:03:11.03#ibcon#wrote, iclass 30, count 2 2006.174.00:03:11.03#ibcon#about to read 3, iclass 30, count 2 2006.174.00:03:11.06#ibcon#read 3, iclass 30, count 2 2006.174.00:03:11.06#ibcon#about to read 4, iclass 30, count 2 2006.174.00:03:11.06#ibcon#read 4, iclass 30, count 2 2006.174.00:03:11.06#ibcon#about to read 5, iclass 30, count 2 2006.174.00:03:11.06#ibcon#read 5, iclass 30, count 2 2006.174.00:03:11.06#ibcon#about to read 6, iclass 30, count 2 2006.174.00:03:11.06#ibcon#read 6, iclass 30, count 2 2006.174.00:03:11.06#ibcon#end of sib2, iclass 30, count 2 2006.174.00:03:11.06#ibcon#*after write, iclass 30, count 2 2006.174.00:03:11.06#ibcon#*before return 0, iclass 30, count 2 2006.174.00:03:11.06#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.174.00:03:11.06#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.174.00:03:11.06#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.174.00:03:11.06#ibcon#ireg 7 cls_cnt 0 2006.174.00:03:11.06#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.174.00:03:11.18#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.174.00:03:11.18#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.174.00:03:11.18#ibcon#enter wrdev, iclass 30, count 0 2006.174.00:03:11.18#ibcon#first serial, iclass 30, count 0 2006.174.00:03:11.18#ibcon#enter sib2, iclass 30, count 0 2006.174.00:03:11.18#ibcon#flushed, iclass 30, count 0 2006.174.00:03:11.18#ibcon#about to write, iclass 30, count 0 2006.174.00:03:11.18#ibcon#wrote, iclass 30, count 0 2006.174.00:03:11.18#ibcon#about to read 3, iclass 30, count 0 2006.174.00:03:11.20#ibcon#read 3, iclass 30, count 0 2006.174.00:03:11.20#ibcon#about to read 4, iclass 30, count 0 2006.174.00:03:11.20#ibcon#read 4, iclass 30, count 0 2006.174.00:03:11.20#ibcon#about to read 5, iclass 30, count 0 2006.174.00:03:11.20#ibcon#read 5, iclass 30, count 0 2006.174.00:03:11.20#ibcon#about to read 6, iclass 30, count 0 2006.174.00:03:11.20#ibcon#read 6, iclass 30, count 0 2006.174.00:03:11.20#ibcon#end of sib2, iclass 30, count 0 2006.174.00:03:11.20#ibcon#*mode == 0, iclass 30, count 0 2006.174.00:03:11.20#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.174.00:03:11.20#ibcon#[25=USB\r\n] 2006.174.00:03:11.20#ibcon#*before write, iclass 30, count 0 2006.174.00:03:11.20#ibcon#enter sib2, iclass 30, count 0 2006.174.00:03:11.20#ibcon#flushed, iclass 30, count 0 2006.174.00:03:11.20#ibcon#about to write, iclass 30, count 0 2006.174.00:03:11.20#ibcon#wrote, iclass 30, count 0 2006.174.00:03:11.20#ibcon#about to read 3, iclass 30, count 0 2006.174.00:03:11.23#ibcon#read 3, iclass 30, count 0 2006.174.00:03:11.23#ibcon#about to read 4, iclass 30, count 0 2006.174.00:03:11.23#ibcon#read 4, iclass 30, count 0 2006.174.00:03:11.23#ibcon#about to read 5, iclass 30, count 0 2006.174.00:03:11.23#ibcon#read 5, iclass 30, count 0 2006.174.00:03:11.23#ibcon#about to read 6, iclass 30, count 0 2006.174.00:03:11.23#ibcon#read 6, iclass 30, count 0 2006.174.00:03:11.23#ibcon#end of sib2, iclass 30, count 0 2006.174.00:03:11.23#ibcon#*after write, iclass 30, count 0 2006.174.00:03:11.23#ibcon#*before return 0, iclass 30, count 0 2006.174.00:03:11.23#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.174.00:03:11.23#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.174.00:03:11.23#ibcon#about to clear, iclass 30 cls_cnt 0 2006.174.00:03:11.23#ibcon#cleared, iclass 30 cls_cnt 0 2006.174.00:03:11.23$vck44/valo=7,864.99 2006.174.00:03:11.23#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.174.00:03:11.23#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.174.00:03:11.23#ibcon#ireg 17 cls_cnt 0 2006.174.00:03:11.23#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.174.00:03:11.23#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.174.00:03:11.23#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.174.00:03:11.23#ibcon#enter wrdev, iclass 32, count 0 2006.174.00:03:11.23#ibcon#first serial, iclass 32, count 0 2006.174.00:03:11.23#ibcon#enter sib2, iclass 32, count 0 2006.174.00:03:11.23#ibcon#flushed, iclass 32, count 0 2006.174.00:03:11.23#ibcon#about to write, iclass 32, count 0 2006.174.00:03:11.23#ibcon#wrote, iclass 32, count 0 2006.174.00:03:11.23#ibcon#about to read 3, iclass 32, count 0 2006.174.00:03:11.25#ibcon#read 3, iclass 32, count 0 2006.174.00:03:11.25#ibcon#about to read 4, iclass 32, count 0 2006.174.00:03:11.25#ibcon#read 4, iclass 32, count 0 2006.174.00:03:11.25#ibcon#about to read 5, iclass 32, count 0 2006.174.00:03:11.25#ibcon#read 5, iclass 32, count 0 2006.174.00:03:11.25#ibcon#about to read 6, iclass 32, count 0 2006.174.00:03:11.25#ibcon#read 6, iclass 32, count 0 2006.174.00:03:11.25#ibcon#end of sib2, iclass 32, count 0 2006.174.00:03:11.25#ibcon#*mode == 0, iclass 32, count 0 2006.174.00:03:11.25#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.174.00:03:11.25#ibcon#[26=FRQ=07,864.99\r\n] 2006.174.00:03:11.25#ibcon#*before write, iclass 32, count 0 2006.174.00:03:11.25#ibcon#enter sib2, iclass 32, count 0 2006.174.00:03:11.25#ibcon#flushed, iclass 32, count 0 2006.174.00:03:11.25#ibcon#about to write, iclass 32, count 0 2006.174.00:03:11.25#ibcon#wrote, iclass 32, count 0 2006.174.00:03:11.25#ibcon#about to read 3, iclass 32, count 0 2006.174.00:03:11.29#ibcon#read 3, iclass 32, count 0 2006.174.00:03:11.29#ibcon#about to read 4, iclass 32, count 0 2006.174.00:03:11.29#ibcon#read 4, iclass 32, count 0 2006.174.00:03:11.29#ibcon#about to read 5, iclass 32, count 0 2006.174.00:03:11.29#ibcon#read 5, iclass 32, count 0 2006.174.00:03:11.29#ibcon#about to read 6, iclass 32, count 0 2006.174.00:03:11.29#ibcon#read 6, iclass 32, count 0 2006.174.00:03:11.29#ibcon#end of sib2, iclass 32, count 0 2006.174.00:03:11.29#ibcon#*after write, iclass 32, count 0 2006.174.00:03:11.29#ibcon#*before return 0, iclass 32, count 0 2006.174.00:03:11.29#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.174.00:03:11.29#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.174.00:03:11.29#ibcon#about to clear, iclass 32 cls_cnt 0 2006.174.00:03:11.29#ibcon#cleared, iclass 32 cls_cnt 0 2006.174.00:03:11.29$vck44/va=7,4 2006.174.00:03:11.29#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.174.00:03:11.29#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.174.00:03:11.29#ibcon#ireg 11 cls_cnt 2 2006.174.00:03:11.29#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.174.00:03:11.35#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.174.00:03:11.35#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.174.00:03:11.35#ibcon#enter wrdev, iclass 34, count 2 2006.174.00:03:11.35#ibcon#first serial, iclass 34, count 2 2006.174.00:03:11.35#ibcon#enter sib2, iclass 34, count 2 2006.174.00:03:11.35#ibcon#flushed, iclass 34, count 2 2006.174.00:03:11.35#ibcon#about to write, iclass 34, count 2 2006.174.00:03:11.35#ibcon#wrote, iclass 34, count 2 2006.174.00:03:11.35#ibcon#about to read 3, iclass 34, count 2 2006.174.00:03:11.37#ibcon#read 3, iclass 34, count 2 2006.174.00:03:11.37#ibcon#about to read 4, iclass 34, count 2 2006.174.00:03:11.37#ibcon#read 4, iclass 34, count 2 2006.174.00:03:11.37#ibcon#about to read 5, iclass 34, count 2 2006.174.00:03:11.37#ibcon#read 5, iclass 34, count 2 2006.174.00:03:11.37#ibcon#about to read 6, iclass 34, count 2 2006.174.00:03:11.37#ibcon#read 6, iclass 34, count 2 2006.174.00:03:11.37#ibcon#end of sib2, iclass 34, count 2 2006.174.00:03:11.37#ibcon#*mode == 0, iclass 34, count 2 2006.174.00:03:11.37#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.174.00:03:11.37#ibcon#[25=AT07-04\r\n] 2006.174.00:03:11.37#ibcon#*before write, iclass 34, count 2 2006.174.00:03:11.37#ibcon#enter sib2, iclass 34, count 2 2006.174.00:03:11.37#ibcon#flushed, iclass 34, count 2 2006.174.00:03:11.37#ibcon#about to write, iclass 34, count 2 2006.174.00:03:11.37#ibcon#wrote, iclass 34, count 2 2006.174.00:03:11.37#ibcon#about to read 3, iclass 34, count 2 2006.174.00:03:11.40#ibcon#read 3, iclass 34, count 2 2006.174.00:03:11.40#ibcon#about to read 4, iclass 34, count 2 2006.174.00:03:11.40#ibcon#read 4, iclass 34, count 2 2006.174.00:03:11.40#ibcon#about to read 5, iclass 34, count 2 2006.174.00:03:11.40#ibcon#read 5, iclass 34, count 2 2006.174.00:03:11.40#ibcon#about to read 6, iclass 34, count 2 2006.174.00:03:11.40#ibcon#read 6, iclass 34, count 2 2006.174.00:03:11.40#ibcon#end of sib2, iclass 34, count 2 2006.174.00:03:11.40#ibcon#*after write, iclass 34, count 2 2006.174.00:03:11.40#ibcon#*before return 0, iclass 34, count 2 2006.174.00:03:11.40#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.174.00:03:11.40#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.174.00:03:11.40#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.174.00:03:11.40#ibcon#ireg 7 cls_cnt 0 2006.174.00:03:11.40#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.174.00:03:11.52#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.174.00:03:11.52#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.174.00:03:11.52#ibcon#enter wrdev, iclass 34, count 0 2006.174.00:03:11.52#ibcon#first serial, iclass 34, count 0 2006.174.00:03:11.52#ibcon#enter sib2, iclass 34, count 0 2006.174.00:03:11.52#ibcon#flushed, iclass 34, count 0 2006.174.00:03:11.52#ibcon#about to write, iclass 34, count 0 2006.174.00:03:11.52#ibcon#wrote, iclass 34, count 0 2006.174.00:03:11.52#ibcon#about to read 3, iclass 34, count 0 2006.174.00:03:11.54#ibcon#read 3, iclass 34, count 0 2006.174.00:03:11.54#ibcon#about to read 4, iclass 34, count 0 2006.174.00:03:11.54#ibcon#read 4, iclass 34, count 0 2006.174.00:03:11.54#ibcon#about to read 5, iclass 34, count 0 2006.174.00:03:11.54#ibcon#read 5, iclass 34, count 0 2006.174.00:03:11.54#ibcon#about to read 6, iclass 34, count 0 2006.174.00:03:11.54#ibcon#read 6, iclass 34, count 0 2006.174.00:03:11.54#ibcon#end of sib2, iclass 34, count 0 2006.174.00:03:11.54#ibcon#*mode == 0, iclass 34, count 0 2006.174.00:03:11.54#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.174.00:03:11.54#ibcon#[25=USB\r\n] 2006.174.00:03:11.54#ibcon#*before write, iclass 34, count 0 2006.174.00:03:11.54#ibcon#enter sib2, iclass 34, count 0 2006.174.00:03:11.54#ibcon#flushed, iclass 34, count 0 2006.174.00:03:11.54#ibcon#about to write, iclass 34, count 0 2006.174.00:03:11.54#ibcon#wrote, iclass 34, count 0 2006.174.00:03:11.54#ibcon#about to read 3, iclass 34, count 0 2006.174.00:03:11.57#ibcon#read 3, iclass 34, count 0 2006.174.00:03:11.57#ibcon#about to read 4, iclass 34, count 0 2006.174.00:03:11.57#ibcon#read 4, iclass 34, count 0 2006.174.00:03:11.57#ibcon#about to read 5, iclass 34, count 0 2006.174.00:03:11.57#ibcon#read 5, iclass 34, count 0 2006.174.00:03:11.57#ibcon#about to read 6, iclass 34, count 0 2006.174.00:03:11.57#ibcon#read 6, iclass 34, count 0 2006.174.00:03:11.57#ibcon#end of sib2, iclass 34, count 0 2006.174.00:03:11.57#ibcon#*after write, iclass 34, count 0 2006.174.00:03:11.57#ibcon#*before return 0, iclass 34, count 0 2006.174.00:03:11.57#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.174.00:03:11.57#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.174.00:03:11.57#ibcon#about to clear, iclass 34 cls_cnt 0 2006.174.00:03:11.57#ibcon#cleared, iclass 34 cls_cnt 0 2006.174.00:03:11.57$vck44/valo=8,884.99 2006.174.00:03:11.57#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.174.00:03:11.57#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.174.00:03:11.57#ibcon#ireg 17 cls_cnt 0 2006.174.00:03:11.57#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.174.00:03:11.57#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.174.00:03:11.57#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.174.00:03:11.57#ibcon#enter wrdev, iclass 36, count 0 2006.174.00:03:11.57#ibcon#first serial, iclass 36, count 0 2006.174.00:03:11.57#ibcon#enter sib2, iclass 36, count 0 2006.174.00:03:11.57#ibcon#flushed, iclass 36, count 0 2006.174.00:03:11.57#ibcon#about to write, iclass 36, count 0 2006.174.00:03:11.57#ibcon#wrote, iclass 36, count 0 2006.174.00:03:11.57#ibcon#about to read 3, iclass 36, count 0 2006.174.00:03:11.59#ibcon#read 3, iclass 36, count 0 2006.174.00:03:11.59#ibcon#about to read 4, iclass 36, count 0 2006.174.00:03:11.59#ibcon#read 4, iclass 36, count 0 2006.174.00:03:11.59#ibcon#about to read 5, iclass 36, count 0 2006.174.00:03:11.59#ibcon#read 5, iclass 36, count 0 2006.174.00:03:11.59#ibcon#about to read 6, iclass 36, count 0 2006.174.00:03:11.59#ibcon#read 6, iclass 36, count 0 2006.174.00:03:11.59#ibcon#end of sib2, iclass 36, count 0 2006.174.00:03:11.59#ibcon#*mode == 0, iclass 36, count 0 2006.174.00:03:11.59#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.174.00:03:11.59#ibcon#[26=FRQ=08,884.99\r\n] 2006.174.00:03:11.59#ibcon#*before write, iclass 36, count 0 2006.174.00:03:11.59#ibcon#enter sib2, iclass 36, count 0 2006.174.00:03:11.59#ibcon#flushed, iclass 36, count 0 2006.174.00:03:11.59#ibcon#about to write, iclass 36, count 0 2006.174.00:03:11.59#ibcon#wrote, iclass 36, count 0 2006.174.00:03:11.59#ibcon#about to read 3, iclass 36, count 0 2006.174.00:03:11.63#ibcon#read 3, iclass 36, count 0 2006.174.00:03:11.63#ibcon#about to read 4, iclass 36, count 0 2006.174.00:03:11.63#ibcon#read 4, iclass 36, count 0 2006.174.00:03:11.63#ibcon#about to read 5, iclass 36, count 0 2006.174.00:03:11.63#ibcon#read 5, iclass 36, count 0 2006.174.00:03:11.63#ibcon#about to read 6, iclass 36, count 0 2006.174.00:03:11.63#ibcon#read 6, iclass 36, count 0 2006.174.00:03:11.63#ibcon#end of sib2, iclass 36, count 0 2006.174.00:03:11.63#ibcon#*after write, iclass 36, count 0 2006.174.00:03:11.63#ibcon#*before return 0, iclass 36, count 0 2006.174.00:03:11.63#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.174.00:03:11.63#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.174.00:03:11.63#ibcon#about to clear, iclass 36 cls_cnt 0 2006.174.00:03:11.63#ibcon#cleared, iclass 36 cls_cnt 0 2006.174.00:03:11.63$vck44/va=8,4 2006.174.00:03:11.63#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.174.00:03:11.63#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.174.00:03:11.63#ibcon#ireg 11 cls_cnt 2 2006.174.00:03:11.63#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.174.00:03:11.69#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.174.00:03:11.69#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.174.00:03:11.69#ibcon#enter wrdev, iclass 38, count 2 2006.174.00:03:11.69#ibcon#first serial, iclass 38, count 2 2006.174.00:03:11.69#ibcon#enter sib2, iclass 38, count 2 2006.174.00:03:11.69#ibcon#flushed, iclass 38, count 2 2006.174.00:03:11.69#ibcon#about to write, iclass 38, count 2 2006.174.00:03:11.69#ibcon#wrote, iclass 38, count 2 2006.174.00:03:11.69#ibcon#about to read 3, iclass 38, count 2 2006.174.00:03:11.71#ibcon#read 3, iclass 38, count 2 2006.174.00:03:11.71#ibcon#about to read 4, iclass 38, count 2 2006.174.00:03:11.71#ibcon#read 4, iclass 38, count 2 2006.174.00:03:11.71#ibcon#about to read 5, iclass 38, count 2 2006.174.00:03:11.71#ibcon#read 5, iclass 38, count 2 2006.174.00:03:11.71#ibcon#about to read 6, iclass 38, count 2 2006.174.00:03:11.71#ibcon#read 6, iclass 38, count 2 2006.174.00:03:11.71#ibcon#end of sib2, iclass 38, count 2 2006.174.00:03:11.71#ibcon#*mode == 0, iclass 38, count 2 2006.174.00:03:11.71#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.174.00:03:11.71#ibcon#[25=AT08-04\r\n] 2006.174.00:03:11.71#ibcon#*before write, iclass 38, count 2 2006.174.00:03:11.71#ibcon#enter sib2, iclass 38, count 2 2006.174.00:03:11.71#ibcon#flushed, iclass 38, count 2 2006.174.00:03:11.71#ibcon#about to write, iclass 38, count 2 2006.174.00:03:11.71#ibcon#wrote, iclass 38, count 2 2006.174.00:03:11.71#ibcon#about to read 3, iclass 38, count 2 2006.174.00:03:11.74#ibcon#read 3, iclass 38, count 2 2006.174.00:03:11.74#ibcon#about to read 4, iclass 38, count 2 2006.174.00:03:11.74#ibcon#read 4, iclass 38, count 2 2006.174.00:03:11.74#ibcon#about to read 5, iclass 38, count 2 2006.174.00:03:11.74#ibcon#read 5, iclass 38, count 2 2006.174.00:03:11.74#ibcon#about to read 6, iclass 38, count 2 2006.174.00:03:11.74#ibcon#read 6, iclass 38, count 2 2006.174.00:03:11.74#ibcon#end of sib2, iclass 38, count 2 2006.174.00:03:11.74#ibcon#*after write, iclass 38, count 2 2006.174.00:03:11.74#ibcon#*before return 0, iclass 38, count 2 2006.174.00:03:11.74#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.174.00:03:11.74#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.174.00:03:11.74#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.174.00:03:11.74#ibcon#ireg 7 cls_cnt 0 2006.174.00:03:11.74#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.174.00:03:11.86#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.174.00:03:11.86#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.174.00:03:11.86#ibcon#enter wrdev, iclass 38, count 0 2006.174.00:03:11.86#ibcon#first serial, iclass 38, count 0 2006.174.00:03:11.86#ibcon#enter sib2, iclass 38, count 0 2006.174.00:03:11.86#ibcon#flushed, iclass 38, count 0 2006.174.00:03:11.86#ibcon#about to write, iclass 38, count 0 2006.174.00:03:11.86#ibcon#wrote, iclass 38, count 0 2006.174.00:03:11.86#ibcon#about to read 3, iclass 38, count 0 2006.174.00:03:11.88#ibcon#read 3, iclass 38, count 0 2006.174.00:03:11.88#ibcon#about to read 4, iclass 38, count 0 2006.174.00:03:11.88#ibcon#read 4, iclass 38, count 0 2006.174.00:03:11.88#ibcon#about to read 5, iclass 38, count 0 2006.174.00:03:11.88#ibcon#read 5, iclass 38, count 0 2006.174.00:03:11.88#ibcon#about to read 6, iclass 38, count 0 2006.174.00:03:11.88#ibcon#read 6, iclass 38, count 0 2006.174.00:03:11.88#ibcon#end of sib2, iclass 38, count 0 2006.174.00:03:11.88#ibcon#*mode == 0, iclass 38, count 0 2006.174.00:03:11.88#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.174.00:03:11.88#ibcon#[25=USB\r\n] 2006.174.00:03:11.88#ibcon#*before write, iclass 38, count 0 2006.174.00:03:11.88#ibcon#enter sib2, iclass 38, count 0 2006.174.00:03:11.88#ibcon#flushed, iclass 38, count 0 2006.174.00:03:11.88#ibcon#about to write, iclass 38, count 0 2006.174.00:03:11.88#ibcon#wrote, iclass 38, count 0 2006.174.00:03:11.88#ibcon#about to read 3, iclass 38, count 0 2006.174.00:03:11.91#ibcon#read 3, iclass 38, count 0 2006.174.00:03:11.91#ibcon#about to read 4, iclass 38, count 0 2006.174.00:03:11.91#ibcon#read 4, iclass 38, count 0 2006.174.00:03:11.91#ibcon#about to read 5, iclass 38, count 0 2006.174.00:03:11.91#ibcon#read 5, iclass 38, count 0 2006.174.00:03:11.91#ibcon#about to read 6, iclass 38, count 0 2006.174.00:03:11.91#ibcon#read 6, iclass 38, count 0 2006.174.00:03:11.91#ibcon#end of sib2, iclass 38, count 0 2006.174.00:03:11.91#ibcon#*after write, iclass 38, count 0 2006.174.00:03:11.91#ibcon#*before return 0, iclass 38, count 0 2006.174.00:03:11.91#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.174.00:03:11.91#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.174.00:03:11.91#ibcon#about to clear, iclass 38 cls_cnt 0 2006.174.00:03:11.91#ibcon#cleared, iclass 38 cls_cnt 0 2006.174.00:03:11.91$vck44/vblo=1,629.99 2006.174.00:03:11.91#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.174.00:03:11.91#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.174.00:03:11.91#ibcon#ireg 17 cls_cnt 0 2006.174.00:03:11.91#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.174.00:03:11.91#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.174.00:03:11.91#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.174.00:03:11.91#ibcon#enter wrdev, iclass 40, count 0 2006.174.00:03:11.91#ibcon#first serial, iclass 40, count 0 2006.174.00:03:11.91#ibcon#enter sib2, iclass 40, count 0 2006.174.00:03:11.91#ibcon#flushed, iclass 40, count 0 2006.174.00:03:11.91#ibcon#about to write, iclass 40, count 0 2006.174.00:03:11.91#ibcon#wrote, iclass 40, count 0 2006.174.00:03:11.91#ibcon#about to read 3, iclass 40, count 0 2006.174.00:03:11.93#ibcon#read 3, iclass 40, count 0 2006.174.00:03:11.93#ibcon#about to read 4, iclass 40, count 0 2006.174.00:03:11.93#ibcon#read 4, iclass 40, count 0 2006.174.00:03:11.93#ibcon#about to read 5, iclass 40, count 0 2006.174.00:03:11.93#ibcon#read 5, iclass 40, count 0 2006.174.00:03:11.93#ibcon#about to read 6, iclass 40, count 0 2006.174.00:03:11.93#ibcon#read 6, iclass 40, count 0 2006.174.00:03:11.93#ibcon#end of sib2, iclass 40, count 0 2006.174.00:03:11.93#ibcon#*mode == 0, iclass 40, count 0 2006.174.00:03:11.93#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.174.00:03:11.93#ibcon#[28=FRQ=01,629.99\r\n] 2006.174.00:03:11.93#ibcon#*before write, iclass 40, count 0 2006.174.00:03:11.93#ibcon#enter sib2, iclass 40, count 0 2006.174.00:03:11.93#ibcon#flushed, iclass 40, count 0 2006.174.00:03:11.93#ibcon#about to write, iclass 40, count 0 2006.174.00:03:11.93#ibcon#wrote, iclass 40, count 0 2006.174.00:03:11.93#ibcon#about to read 3, iclass 40, count 0 2006.174.00:03:11.97#ibcon#read 3, iclass 40, count 0 2006.174.00:03:11.97#ibcon#about to read 4, iclass 40, count 0 2006.174.00:03:11.97#ibcon#read 4, iclass 40, count 0 2006.174.00:03:11.97#ibcon#about to read 5, iclass 40, count 0 2006.174.00:03:11.97#ibcon#read 5, iclass 40, count 0 2006.174.00:03:11.97#ibcon#about to read 6, iclass 40, count 0 2006.174.00:03:11.97#ibcon#read 6, iclass 40, count 0 2006.174.00:03:11.97#ibcon#end of sib2, iclass 40, count 0 2006.174.00:03:11.97#ibcon#*after write, iclass 40, count 0 2006.174.00:03:11.97#ibcon#*before return 0, iclass 40, count 0 2006.174.00:03:11.97#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.174.00:03:11.97#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.174.00:03:11.97#ibcon#about to clear, iclass 40 cls_cnt 0 2006.174.00:03:11.97#ibcon#cleared, iclass 40 cls_cnt 0 2006.174.00:03:11.97$vck44/vb=1,4 2006.174.00:03:11.97#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.174.00:03:11.97#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.174.00:03:11.97#ibcon#ireg 11 cls_cnt 2 2006.174.00:03:11.97#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.174.00:03:11.97#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.174.00:03:11.97#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.174.00:03:11.97#ibcon#enter wrdev, iclass 4, count 2 2006.174.00:03:11.97#ibcon#first serial, iclass 4, count 2 2006.174.00:03:11.97#ibcon#enter sib2, iclass 4, count 2 2006.174.00:03:11.97#ibcon#flushed, iclass 4, count 2 2006.174.00:03:11.97#ibcon#about to write, iclass 4, count 2 2006.174.00:03:11.97#ibcon#wrote, iclass 4, count 2 2006.174.00:03:11.97#ibcon#about to read 3, iclass 4, count 2 2006.174.00:03:11.99#ibcon#read 3, iclass 4, count 2 2006.174.00:03:11.99#ibcon#about to read 4, iclass 4, count 2 2006.174.00:03:11.99#ibcon#read 4, iclass 4, count 2 2006.174.00:03:11.99#ibcon#about to read 5, iclass 4, count 2 2006.174.00:03:11.99#ibcon#read 5, iclass 4, count 2 2006.174.00:03:11.99#ibcon#about to read 6, iclass 4, count 2 2006.174.00:03:11.99#ibcon#read 6, iclass 4, count 2 2006.174.00:03:11.99#ibcon#end of sib2, iclass 4, count 2 2006.174.00:03:11.99#ibcon#*mode == 0, iclass 4, count 2 2006.174.00:03:11.99#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.174.00:03:11.99#ibcon#[27=AT01-04\r\n] 2006.174.00:03:11.99#ibcon#*before write, iclass 4, count 2 2006.174.00:03:11.99#ibcon#enter sib2, iclass 4, count 2 2006.174.00:03:11.99#ibcon#flushed, iclass 4, count 2 2006.174.00:03:11.99#ibcon#about to write, iclass 4, count 2 2006.174.00:03:11.99#ibcon#wrote, iclass 4, count 2 2006.174.00:03:11.99#ibcon#about to read 3, iclass 4, count 2 2006.174.00:03:12.02#ibcon#read 3, iclass 4, count 2 2006.174.00:03:12.02#ibcon#about to read 4, iclass 4, count 2 2006.174.00:03:12.02#ibcon#read 4, iclass 4, count 2 2006.174.00:03:12.02#ibcon#about to read 5, iclass 4, count 2 2006.174.00:03:12.02#ibcon#read 5, iclass 4, count 2 2006.174.00:03:12.02#ibcon#about to read 6, iclass 4, count 2 2006.174.00:03:12.02#ibcon#read 6, iclass 4, count 2 2006.174.00:03:12.02#ibcon#end of sib2, iclass 4, count 2 2006.174.00:03:12.02#ibcon#*after write, iclass 4, count 2 2006.174.00:03:12.02#ibcon#*before return 0, iclass 4, count 2 2006.174.00:03:12.02#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.174.00:03:12.02#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.174.00:03:12.02#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.174.00:03:12.02#ibcon#ireg 7 cls_cnt 0 2006.174.00:03:12.02#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.174.00:03:12.14#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.174.00:03:12.14#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.174.00:03:12.14#ibcon#enter wrdev, iclass 4, count 0 2006.174.00:03:12.14#ibcon#first serial, iclass 4, count 0 2006.174.00:03:12.14#ibcon#enter sib2, iclass 4, count 0 2006.174.00:03:12.14#ibcon#flushed, iclass 4, count 0 2006.174.00:03:12.14#ibcon#about to write, iclass 4, count 0 2006.174.00:03:12.14#ibcon#wrote, iclass 4, count 0 2006.174.00:03:12.14#ibcon#about to read 3, iclass 4, count 0 2006.174.00:03:12.16#ibcon#read 3, iclass 4, count 0 2006.174.00:03:12.16#ibcon#about to read 4, iclass 4, count 0 2006.174.00:03:12.16#ibcon#read 4, iclass 4, count 0 2006.174.00:03:12.16#ibcon#about to read 5, iclass 4, count 0 2006.174.00:03:12.16#ibcon#read 5, iclass 4, count 0 2006.174.00:03:12.16#ibcon#about to read 6, iclass 4, count 0 2006.174.00:03:12.16#ibcon#read 6, iclass 4, count 0 2006.174.00:03:12.16#ibcon#end of sib2, iclass 4, count 0 2006.174.00:03:12.16#ibcon#*mode == 0, iclass 4, count 0 2006.174.00:03:12.16#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.174.00:03:12.16#ibcon#[27=USB\r\n] 2006.174.00:03:12.16#ibcon#*before write, iclass 4, count 0 2006.174.00:03:12.16#ibcon#enter sib2, iclass 4, count 0 2006.174.00:03:12.16#ibcon#flushed, iclass 4, count 0 2006.174.00:03:12.16#ibcon#about to write, iclass 4, count 0 2006.174.00:03:12.16#ibcon#wrote, iclass 4, count 0 2006.174.00:03:12.16#ibcon#about to read 3, iclass 4, count 0 2006.174.00:03:12.19#ibcon#read 3, iclass 4, count 0 2006.174.00:03:12.19#ibcon#about to read 4, iclass 4, count 0 2006.174.00:03:12.19#ibcon#read 4, iclass 4, count 0 2006.174.00:03:12.19#ibcon#about to read 5, iclass 4, count 0 2006.174.00:03:12.19#ibcon#read 5, iclass 4, count 0 2006.174.00:03:12.19#ibcon#about to read 6, iclass 4, count 0 2006.174.00:03:12.19#ibcon#read 6, iclass 4, count 0 2006.174.00:03:12.19#ibcon#end of sib2, iclass 4, count 0 2006.174.00:03:12.19#ibcon#*after write, iclass 4, count 0 2006.174.00:03:12.19#ibcon#*before return 0, iclass 4, count 0 2006.174.00:03:12.19#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.174.00:03:12.19#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.174.00:03:12.19#ibcon#about to clear, iclass 4 cls_cnt 0 2006.174.00:03:12.19#ibcon#cleared, iclass 4 cls_cnt 0 2006.174.00:03:12.19$vck44/vblo=2,634.99 2006.174.00:03:12.19#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.174.00:03:12.19#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.174.00:03:12.19#ibcon#ireg 17 cls_cnt 0 2006.174.00:03:12.19#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.174.00:03:12.19#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.174.00:03:12.19#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.174.00:03:12.19#ibcon#enter wrdev, iclass 6, count 0 2006.174.00:03:12.19#ibcon#first serial, iclass 6, count 0 2006.174.00:03:12.19#ibcon#enter sib2, iclass 6, count 0 2006.174.00:03:12.19#ibcon#flushed, iclass 6, count 0 2006.174.00:03:12.19#ibcon#about to write, iclass 6, count 0 2006.174.00:03:12.19#ibcon#wrote, iclass 6, count 0 2006.174.00:03:12.19#ibcon#about to read 3, iclass 6, count 0 2006.174.00:03:12.21#ibcon#read 3, iclass 6, count 0 2006.174.00:03:12.21#ibcon#about to read 4, iclass 6, count 0 2006.174.00:03:12.21#ibcon#read 4, iclass 6, count 0 2006.174.00:03:12.21#ibcon#about to read 5, iclass 6, count 0 2006.174.00:03:12.21#ibcon#read 5, iclass 6, count 0 2006.174.00:03:12.21#ibcon#about to read 6, iclass 6, count 0 2006.174.00:03:12.21#ibcon#read 6, iclass 6, count 0 2006.174.00:03:12.21#ibcon#end of sib2, iclass 6, count 0 2006.174.00:03:12.21#ibcon#*mode == 0, iclass 6, count 0 2006.174.00:03:12.21#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.174.00:03:12.21#ibcon#[28=FRQ=02,634.99\r\n] 2006.174.00:03:12.21#ibcon#*before write, iclass 6, count 0 2006.174.00:03:12.21#ibcon#enter sib2, iclass 6, count 0 2006.174.00:03:12.21#ibcon#flushed, iclass 6, count 0 2006.174.00:03:12.21#ibcon#about to write, iclass 6, count 0 2006.174.00:03:12.21#ibcon#wrote, iclass 6, count 0 2006.174.00:03:12.21#ibcon#about to read 3, iclass 6, count 0 2006.174.00:03:12.25#ibcon#read 3, iclass 6, count 0 2006.174.00:03:12.25#ibcon#about to read 4, iclass 6, count 0 2006.174.00:03:12.25#ibcon#read 4, iclass 6, count 0 2006.174.00:03:12.25#ibcon#about to read 5, iclass 6, count 0 2006.174.00:03:12.25#ibcon#read 5, iclass 6, count 0 2006.174.00:03:12.25#ibcon#about to read 6, iclass 6, count 0 2006.174.00:03:12.25#ibcon#read 6, iclass 6, count 0 2006.174.00:03:12.25#ibcon#end of sib2, iclass 6, count 0 2006.174.00:03:12.25#ibcon#*after write, iclass 6, count 0 2006.174.00:03:12.25#ibcon#*before return 0, iclass 6, count 0 2006.174.00:03:12.25#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.174.00:03:12.25#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.174.00:03:12.25#ibcon#about to clear, iclass 6 cls_cnt 0 2006.174.00:03:12.25#ibcon#cleared, iclass 6 cls_cnt 0 2006.174.00:03:12.25$vck44/vb=2,4 2006.174.00:03:12.25#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.174.00:03:12.25#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.174.00:03:12.25#ibcon#ireg 11 cls_cnt 2 2006.174.00:03:12.25#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.174.00:03:12.31#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.174.00:03:12.31#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.174.00:03:12.31#ibcon#enter wrdev, iclass 10, count 2 2006.174.00:03:12.31#ibcon#first serial, iclass 10, count 2 2006.174.00:03:12.31#ibcon#enter sib2, iclass 10, count 2 2006.174.00:03:12.31#ibcon#flushed, iclass 10, count 2 2006.174.00:03:12.31#ibcon#about to write, iclass 10, count 2 2006.174.00:03:12.31#ibcon#wrote, iclass 10, count 2 2006.174.00:03:12.31#ibcon#about to read 3, iclass 10, count 2 2006.174.00:03:12.33#ibcon#read 3, iclass 10, count 2 2006.174.00:03:12.33#ibcon#about to read 4, iclass 10, count 2 2006.174.00:03:12.33#ibcon#read 4, iclass 10, count 2 2006.174.00:03:12.33#ibcon#about to read 5, iclass 10, count 2 2006.174.00:03:12.33#ibcon#read 5, iclass 10, count 2 2006.174.00:03:12.33#ibcon#about to read 6, iclass 10, count 2 2006.174.00:03:12.33#ibcon#read 6, iclass 10, count 2 2006.174.00:03:12.33#ibcon#end of sib2, iclass 10, count 2 2006.174.00:03:12.33#ibcon#*mode == 0, iclass 10, count 2 2006.174.00:03:12.33#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.174.00:03:12.33#ibcon#[27=AT02-04\r\n] 2006.174.00:03:12.33#ibcon#*before write, iclass 10, count 2 2006.174.00:03:12.33#ibcon#enter sib2, iclass 10, count 2 2006.174.00:03:12.33#ibcon#flushed, iclass 10, count 2 2006.174.00:03:12.33#ibcon#about to write, iclass 10, count 2 2006.174.00:03:12.33#ibcon#wrote, iclass 10, count 2 2006.174.00:03:12.33#ibcon#about to read 3, iclass 10, count 2 2006.174.00:03:12.36#ibcon#read 3, iclass 10, count 2 2006.174.00:03:12.36#ibcon#about to read 4, iclass 10, count 2 2006.174.00:03:12.36#ibcon#read 4, iclass 10, count 2 2006.174.00:03:12.36#ibcon#about to read 5, iclass 10, count 2 2006.174.00:03:12.36#ibcon#read 5, iclass 10, count 2 2006.174.00:03:12.36#ibcon#about to read 6, iclass 10, count 2 2006.174.00:03:12.36#ibcon#read 6, iclass 10, count 2 2006.174.00:03:12.36#ibcon#end of sib2, iclass 10, count 2 2006.174.00:03:12.36#ibcon#*after write, iclass 10, count 2 2006.174.00:03:12.36#ibcon#*before return 0, iclass 10, count 2 2006.174.00:03:12.36#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.174.00:03:12.36#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.174.00:03:12.36#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.174.00:03:12.36#ibcon#ireg 7 cls_cnt 0 2006.174.00:03:12.36#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.174.00:03:12.48#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.174.00:03:12.48#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.174.00:03:12.48#ibcon#enter wrdev, iclass 10, count 0 2006.174.00:03:12.48#ibcon#first serial, iclass 10, count 0 2006.174.00:03:12.48#ibcon#enter sib2, iclass 10, count 0 2006.174.00:03:12.48#ibcon#flushed, iclass 10, count 0 2006.174.00:03:12.48#ibcon#about to write, iclass 10, count 0 2006.174.00:03:12.48#ibcon#wrote, iclass 10, count 0 2006.174.00:03:12.48#ibcon#about to read 3, iclass 10, count 0 2006.174.00:03:12.50#ibcon#read 3, iclass 10, count 0 2006.174.00:03:12.50#ibcon#about to read 4, iclass 10, count 0 2006.174.00:03:12.50#ibcon#read 4, iclass 10, count 0 2006.174.00:03:12.50#ibcon#about to read 5, iclass 10, count 0 2006.174.00:03:12.50#ibcon#read 5, iclass 10, count 0 2006.174.00:03:12.50#ibcon#about to read 6, iclass 10, count 0 2006.174.00:03:12.50#ibcon#read 6, iclass 10, count 0 2006.174.00:03:12.50#ibcon#end of sib2, iclass 10, count 0 2006.174.00:03:12.50#ibcon#*mode == 0, iclass 10, count 0 2006.174.00:03:12.50#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.174.00:03:12.50#ibcon#[27=USB\r\n] 2006.174.00:03:12.50#ibcon#*before write, iclass 10, count 0 2006.174.00:03:12.50#ibcon#enter sib2, iclass 10, count 0 2006.174.00:03:12.50#ibcon#flushed, iclass 10, count 0 2006.174.00:03:12.50#ibcon#about to write, iclass 10, count 0 2006.174.00:03:12.50#ibcon#wrote, iclass 10, count 0 2006.174.00:03:12.50#ibcon#about to read 3, iclass 10, count 0 2006.174.00:03:12.53#ibcon#read 3, iclass 10, count 0 2006.174.00:03:12.53#ibcon#about to read 4, iclass 10, count 0 2006.174.00:03:12.53#ibcon#read 4, iclass 10, count 0 2006.174.00:03:12.53#ibcon#about to read 5, iclass 10, count 0 2006.174.00:03:12.53#ibcon#read 5, iclass 10, count 0 2006.174.00:03:12.53#ibcon#about to read 6, iclass 10, count 0 2006.174.00:03:12.53#ibcon#read 6, iclass 10, count 0 2006.174.00:03:12.53#ibcon#end of sib2, iclass 10, count 0 2006.174.00:03:12.53#ibcon#*after write, iclass 10, count 0 2006.174.00:03:12.53#ibcon#*before return 0, iclass 10, count 0 2006.174.00:03:12.53#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.174.00:03:12.53#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.174.00:03:12.53#ibcon#about to clear, iclass 10 cls_cnt 0 2006.174.00:03:12.53#ibcon#cleared, iclass 10 cls_cnt 0 2006.174.00:03:12.53$vck44/vblo=3,649.99 2006.174.00:03:12.53#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.174.00:03:12.53#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.174.00:03:12.53#ibcon#ireg 17 cls_cnt 0 2006.174.00:03:12.53#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.174.00:03:12.53#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.174.00:03:12.53#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.174.00:03:12.53#ibcon#enter wrdev, iclass 12, count 0 2006.174.00:03:12.53#ibcon#first serial, iclass 12, count 0 2006.174.00:03:12.53#ibcon#enter sib2, iclass 12, count 0 2006.174.00:03:12.53#ibcon#flushed, iclass 12, count 0 2006.174.00:03:12.53#ibcon#about to write, iclass 12, count 0 2006.174.00:03:12.53#ibcon#wrote, iclass 12, count 0 2006.174.00:03:12.53#ibcon#about to read 3, iclass 12, count 0 2006.174.00:03:12.55#ibcon#read 3, iclass 12, count 0 2006.174.00:03:12.55#ibcon#about to read 4, iclass 12, count 0 2006.174.00:03:12.55#ibcon#read 4, iclass 12, count 0 2006.174.00:03:12.55#ibcon#about to read 5, iclass 12, count 0 2006.174.00:03:12.55#ibcon#read 5, iclass 12, count 0 2006.174.00:03:12.55#ibcon#about to read 6, iclass 12, count 0 2006.174.00:03:12.55#ibcon#read 6, iclass 12, count 0 2006.174.00:03:12.55#ibcon#end of sib2, iclass 12, count 0 2006.174.00:03:12.55#ibcon#*mode == 0, iclass 12, count 0 2006.174.00:03:12.55#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.174.00:03:12.55#ibcon#[28=FRQ=03,649.99\r\n] 2006.174.00:03:12.55#ibcon#*before write, iclass 12, count 0 2006.174.00:03:12.55#ibcon#enter sib2, iclass 12, count 0 2006.174.00:03:12.55#ibcon#flushed, iclass 12, count 0 2006.174.00:03:12.55#ibcon#about to write, iclass 12, count 0 2006.174.00:03:12.55#ibcon#wrote, iclass 12, count 0 2006.174.00:03:12.55#ibcon#about to read 3, iclass 12, count 0 2006.174.00:03:12.59#ibcon#read 3, iclass 12, count 0 2006.174.00:03:12.59#ibcon#about to read 4, iclass 12, count 0 2006.174.00:03:12.59#ibcon#read 4, iclass 12, count 0 2006.174.00:03:12.59#ibcon#about to read 5, iclass 12, count 0 2006.174.00:03:12.59#ibcon#read 5, iclass 12, count 0 2006.174.00:03:12.59#ibcon#about to read 6, iclass 12, count 0 2006.174.00:03:12.59#ibcon#read 6, iclass 12, count 0 2006.174.00:03:12.59#ibcon#end of sib2, iclass 12, count 0 2006.174.00:03:12.59#ibcon#*after write, iclass 12, count 0 2006.174.00:03:12.59#ibcon#*before return 0, iclass 12, count 0 2006.174.00:03:12.59#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.174.00:03:12.59#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.174.00:03:12.59#ibcon#about to clear, iclass 12 cls_cnt 0 2006.174.00:03:12.59#ibcon#cleared, iclass 12 cls_cnt 0 2006.174.00:03:12.59$vck44/vb=3,4 2006.174.00:03:12.59#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.174.00:03:12.59#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.174.00:03:12.59#ibcon#ireg 11 cls_cnt 2 2006.174.00:03:12.59#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.174.00:03:12.65#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.174.00:03:12.65#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.174.00:03:12.65#ibcon#enter wrdev, iclass 14, count 2 2006.174.00:03:12.65#ibcon#first serial, iclass 14, count 2 2006.174.00:03:12.65#ibcon#enter sib2, iclass 14, count 2 2006.174.00:03:12.65#ibcon#flushed, iclass 14, count 2 2006.174.00:03:12.65#ibcon#about to write, iclass 14, count 2 2006.174.00:03:12.65#ibcon#wrote, iclass 14, count 2 2006.174.00:03:12.65#ibcon#about to read 3, iclass 14, count 2 2006.174.00:03:12.67#ibcon#read 3, iclass 14, count 2 2006.174.00:03:12.67#ibcon#about to read 4, iclass 14, count 2 2006.174.00:03:12.67#ibcon#read 4, iclass 14, count 2 2006.174.00:03:12.67#ibcon#about to read 5, iclass 14, count 2 2006.174.00:03:12.67#ibcon#read 5, iclass 14, count 2 2006.174.00:03:12.67#ibcon#about to read 6, iclass 14, count 2 2006.174.00:03:12.67#ibcon#read 6, iclass 14, count 2 2006.174.00:03:12.67#ibcon#end of sib2, iclass 14, count 2 2006.174.00:03:12.67#ibcon#*mode == 0, iclass 14, count 2 2006.174.00:03:12.67#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.174.00:03:12.67#ibcon#[27=AT03-04\r\n] 2006.174.00:03:12.67#ibcon#*before write, iclass 14, count 2 2006.174.00:03:12.67#ibcon#enter sib2, iclass 14, count 2 2006.174.00:03:12.67#ibcon#flushed, iclass 14, count 2 2006.174.00:03:12.67#ibcon#about to write, iclass 14, count 2 2006.174.00:03:12.67#ibcon#wrote, iclass 14, count 2 2006.174.00:03:12.67#ibcon#about to read 3, iclass 14, count 2 2006.174.00:03:12.70#ibcon#read 3, iclass 14, count 2 2006.174.00:03:12.70#ibcon#about to read 4, iclass 14, count 2 2006.174.00:03:12.70#ibcon#read 4, iclass 14, count 2 2006.174.00:03:12.70#ibcon#about to read 5, iclass 14, count 2 2006.174.00:03:12.70#ibcon#read 5, iclass 14, count 2 2006.174.00:03:12.70#ibcon#about to read 6, iclass 14, count 2 2006.174.00:03:12.70#ibcon#read 6, iclass 14, count 2 2006.174.00:03:12.70#ibcon#end of sib2, iclass 14, count 2 2006.174.00:03:12.70#ibcon#*after write, iclass 14, count 2 2006.174.00:03:12.70#ibcon#*before return 0, iclass 14, count 2 2006.174.00:03:12.70#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.174.00:03:12.70#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.174.00:03:12.70#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.174.00:03:12.70#ibcon#ireg 7 cls_cnt 0 2006.174.00:03:12.70#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.174.00:03:12.82#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.174.00:03:12.82#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.174.00:03:12.82#ibcon#enter wrdev, iclass 14, count 0 2006.174.00:03:12.82#ibcon#first serial, iclass 14, count 0 2006.174.00:03:12.82#ibcon#enter sib2, iclass 14, count 0 2006.174.00:03:12.82#ibcon#flushed, iclass 14, count 0 2006.174.00:03:12.82#ibcon#about to write, iclass 14, count 0 2006.174.00:03:12.82#ibcon#wrote, iclass 14, count 0 2006.174.00:03:12.82#ibcon#about to read 3, iclass 14, count 0 2006.174.00:03:12.84#ibcon#read 3, iclass 14, count 0 2006.174.00:03:12.84#ibcon#about to read 4, iclass 14, count 0 2006.174.00:03:12.84#ibcon#read 4, iclass 14, count 0 2006.174.00:03:12.84#ibcon#about to read 5, iclass 14, count 0 2006.174.00:03:12.84#ibcon#read 5, iclass 14, count 0 2006.174.00:03:12.84#ibcon#about to read 6, iclass 14, count 0 2006.174.00:03:12.84#ibcon#read 6, iclass 14, count 0 2006.174.00:03:12.84#ibcon#end of sib2, iclass 14, count 0 2006.174.00:03:12.84#ibcon#*mode == 0, iclass 14, count 0 2006.174.00:03:12.84#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.174.00:03:12.84#ibcon#[27=USB\r\n] 2006.174.00:03:12.84#ibcon#*before write, iclass 14, count 0 2006.174.00:03:12.84#ibcon#enter sib2, iclass 14, count 0 2006.174.00:03:12.84#ibcon#flushed, iclass 14, count 0 2006.174.00:03:12.84#ibcon#about to write, iclass 14, count 0 2006.174.00:03:12.84#ibcon#wrote, iclass 14, count 0 2006.174.00:03:12.84#ibcon#about to read 3, iclass 14, count 0 2006.174.00:03:12.87#ibcon#read 3, iclass 14, count 0 2006.174.00:03:12.87#ibcon#about to read 4, iclass 14, count 0 2006.174.00:03:12.87#ibcon#read 4, iclass 14, count 0 2006.174.00:03:12.87#ibcon#about to read 5, iclass 14, count 0 2006.174.00:03:12.87#ibcon#read 5, iclass 14, count 0 2006.174.00:03:12.87#ibcon#about to read 6, iclass 14, count 0 2006.174.00:03:12.87#ibcon#read 6, iclass 14, count 0 2006.174.00:03:12.87#ibcon#end of sib2, iclass 14, count 0 2006.174.00:03:12.87#ibcon#*after write, iclass 14, count 0 2006.174.00:03:12.87#ibcon#*before return 0, iclass 14, count 0 2006.174.00:03:12.87#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.174.00:03:12.87#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.174.00:03:12.87#ibcon#about to clear, iclass 14 cls_cnt 0 2006.174.00:03:12.87#ibcon#cleared, iclass 14 cls_cnt 0 2006.174.00:03:12.87$vck44/vblo=4,679.99 2006.174.00:03:12.87#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.174.00:03:12.87#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.174.00:03:12.87#ibcon#ireg 17 cls_cnt 0 2006.174.00:03:12.87#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.174.00:03:12.87#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.174.00:03:12.87#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.174.00:03:12.87#ibcon#enter wrdev, iclass 16, count 0 2006.174.00:03:12.87#ibcon#first serial, iclass 16, count 0 2006.174.00:03:12.87#ibcon#enter sib2, iclass 16, count 0 2006.174.00:03:12.87#ibcon#flushed, iclass 16, count 0 2006.174.00:03:12.87#ibcon#about to write, iclass 16, count 0 2006.174.00:03:12.87#ibcon#wrote, iclass 16, count 0 2006.174.00:03:12.87#ibcon#about to read 3, iclass 16, count 0 2006.174.00:03:12.89#ibcon#read 3, iclass 16, count 0 2006.174.00:03:12.89#ibcon#about to read 4, iclass 16, count 0 2006.174.00:03:12.89#ibcon#read 4, iclass 16, count 0 2006.174.00:03:12.89#ibcon#about to read 5, iclass 16, count 0 2006.174.00:03:12.89#ibcon#read 5, iclass 16, count 0 2006.174.00:03:12.89#ibcon#about to read 6, iclass 16, count 0 2006.174.00:03:12.89#ibcon#read 6, iclass 16, count 0 2006.174.00:03:12.89#ibcon#end of sib2, iclass 16, count 0 2006.174.00:03:12.89#ibcon#*mode == 0, iclass 16, count 0 2006.174.00:03:12.89#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.174.00:03:12.89#ibcon#[28=FRQ=04,679.99\r\n] 2006.174.00:03:12.89#ibcon#*before write, iclass 16, count 0 2006.174.00:03:12.89#ibcon#enter sib2, iclass 16, count 0 2006.174.00:03:12.89#ibcon#flushed, iclass 16, count 0 2006.174.00:03:12.89#ibcon#about to write, iclass 16, count 0 2006.174.00:03:12.89#ibcon#wrote, iclass 16, count 0 2006.174.00:03:12.89#ibcon#about to read 3, iclass 16, count 0 2006.174.00:03:12.93#ibcon#read 3, iclass 16, count 0 2006.174.00:03:12.93#ibcon#about to read 4, iclass 16, count 0 2006.174.00:03:12.93#ibcon#read 4, iclass 16, count 0 2006.174.00:03:12.93#ibcon#about to read 5, iclass 16, count 0 2006.174.00:03:12.93#ibcon#read 5, iclass 16, count 0 2006.174.00:03:12.93#ibcon#about to read 6, iclass 16, count 0 2006.174.00:03:12.93#ibcon#read 6, iclass 16, count 0 2006.174.00:03:12.93#ibcon#end of sib2, iclass 16, count 0 2006.174.00:03:12.93#ibcon#*after write, iclass 16, count 0 2006.174.00:03:12.93#ibcon#*before return 0, iclass 16, count 0 2006.174.00:03:12.93#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.174.00:03:12.93#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.174.00:03:12.93#ibcon#about to clear, iclass 16 cls_cnt 0 2006.174.00:03:12.93#ibcon#cleared, iclass 16 cls_cnt 0 2006.174.00:03:12.93$vck44/vb=4,4 2006.174.00:03:12.93#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.174.00:03:12.93#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.174.00:03:12.93#ibcon#ireg 11 cls_cnt 2 2006.174.00:03:12.93#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.174.00:03:12.99#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.174.00:03:12.99#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.174.00:03:12.99#ibcon#enter wrdev, iclass 18, count 2 2006.174.00:03:12.99#ibcon#first serial, iclass 18, count 2 2006.174.00:03:12.99#ibcon#enter sib2, iclass 18, count 2 2006.174.00:03:12.99#ibcon#flushed, iclass 18, count 2 2006.174.00:03:12.99#ibcon#about to write, iclass 18, count 2 2006.174.00:03:12.99#ibcon#wrote, iclass 18, count 2 2006.174.00:03:12.99#ibcon#about to read 3, iclass 18, count 2 2006.174.00:03:13.01#ibcon#read 3, iclass 18, count 2 2006.174.00:03:13.01#ibcon#about to read 4, iclass 18, count 2 2006.174.00:03:13.01#ibcon#read 4, iclass 18, count 2 2006.174.00:03:13.01#ibcon#about to read 5, iclass 18, count 2 2006.174.00:03:13.01#ibcon#read 5, iclass 18, count 2 2006.174.00:03:13.01#ibcon#about to read 6, iclass 18, count 2 2006.174.00:03:13.01#ibcon#read 6, iclass 18, count 2 2006.174.00:03:13.01#ibcon#end of sib2, iclass 18, count 2 2006.174.00:03:13.01#ibcon#*mode == 0, iclass 18, count 2 2006.174.00:03:13.01#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.174.00:03:13.01#ibcon#[27=AT04-04\r\n] 2006.174.00:03:13.01#ibcon#*before write, iclass 18, count 2 2006.174.00:03:13.01#ibcon#enter sib2, iclass 18, count 2 2006.174.00:03:13.01#ibcon#flushed, iclass 18, count 2 2006.174.00:03:13.01#ibcon#about to write, iclass 18, count 2 2006.174.00:03:13.01#ibcon#wrote, iclass 18, count 2 2006.174.00:03:13.01#ibcon#about to read 3, iclass 18, count 2 2006.174.00:03:13.04#ibcon#read 3, iclass 18, count 2 2006.174.00:03:13.04#ibcon#about to read 4, iclass 18, count 2 2006.174.00:03:13.04#ibcon#read 4, iclass 18, count 2 2006.174.00:03:13.04#ibcon#about to read 5, iclass 18, count 2 2006.174.00:03:13.04#ibcon#read 5, iclass 18, count 2 2006.174.00:03:13.04#ibcon#about to read 6, iclass 18, count 2 2006.174.00:03:13.04#ibcon#read 6, iclass 18, count 2 2006.174.00:03:13.04#ibcon#end of sib2, iclass 18, count 2 2006.174.00:03:13.04#ibcon#*after write, iclass 18, count 2 2006.174.00:03:13.04#ibcon#*before return 0, iclass 18, count 2 2006.174.00:03:13.04#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.174.00:03:13.04#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.174.00:03:13.04#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.174.00:03:13.04#ibcon#ireg 7 cls_cnt 0 2006.174.00:03:13.04#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.174.00:03:13.16#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.174.00:03:13.16#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.174.00:03:13.16#ibcon#enter wrdev, iclass 18, count 0 2006.174.00:03:13.16#ibcon#first serial, iclass 18, count 0 2006.174.00:03:13.16#ibcon#enter sib2, iclass 18, count 0 2006.174.00:03:13.16#ibcon#flushed, iclass 18, count 0 2006.174.00:03:13.16#ibcon#about to write, iclass 18, count 0 2006.174.00:03:13.16#ibcon#wrote, iclass 18, count 0 2006.174.00:03:13.16#ibcon#about to read 3, iclass 18, count 0 2006.174.00:03:13.18#ibcon#read 3, iclass 18, count 0 2006.174.00:03:13.18#ibcon#about to read 4, iclass 18, count 0 2006.174.00:03:13.18#ibcon#read 4, iclass 18, count 0 2006.174.00:03:13.18#ibcon#about to read 5, iclass 18, count 0 2006.174.00:03:13.18#ibcon#read 5, iclass 18, count 0 2006.174.00:03:13.18#ibcon#about to read 6, iclass 18, count 0 2006.174.00:03:13.18#ibcon#read 6, iclass 18, count 0 2006.174.00:03:13.18#ibcon#end of sib2, iclass 18, count 0 2006.174.00:03:13.18#ibcon#*mode == 0, iclass 18, count 0 2006.174.00:03:13.18#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.174.00:03:13.18#ibcon#[27=USB\r\n] 2006.174.00:03:13.18#ibcon#*before write, iclass 18, count 0 2006.174.00:03:13.18#ibcon#enter sib2, iclass 18, count 0 2006.174.00:03:13.18#ibcon#flushed, iclass 18, count 0 2006.174.00:03:13.18#ibcon#about to write, iclass 18, count 0 2006.174.00:03:13.18#ibcon#wrote, iclass 18, count 0 2006.174.00:03:13.18#ibcon#about to read 3, iclass 18, count 0 2006.174.00:03:13.21#ibcon#read 3, iclass 18, count 0 2006.174.00:03:13.21#ibcon#about to read 4, iclass 18, count 0 2006.174.00:03:13.21#ibcon#read 4, iclass 18, count 0 2006.174.00:03:13.21#ibcon#about to read 5, iclass 18, count 0 2006.174.00:03:13.21#ibcon#read 5, iclass 18, count 0 2006.174.00:03:13.21#ibcon#about to read 6, iclass 18, count 0 2006.174.00:03:13.21#ibcon#read 6, iclass 18, count 0 2006.174.00:03:13.21#ibcon#end of sib2, iclass 18, count 0 2006.174.00:03:13.21#ibcon#*after write, iclass 18, count 0 2006.174.00:03:13.21#ibcon#*before return 0, iclass 18, count 0 2006.174.00:03:13.21#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.174.00:03:13.21#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.174.00:03:13.21#ibcon#about to clear, iclass 18 cls_cnt 0 2006.174.00:03:13.21#ibcon#cleared, iclass 18 cls_cnt 0 2006.174.00:03:13.21$vck44/vblo=5,709.99 2006.174.00:03:13.21#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.174.00:03:13.21#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.174.00:03:13.21#ibcon#ireg 17 cls_cnt 0 2006.174.00:03:13.21#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.174.00:03:13.21#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.174.00:03:13.21#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.174.00:03:13.21#ibcon#enter wrdev, iclass 20, count 0 2006.174.00:03:13.21#ibcon#first serial, iclass 20, count 0 2006.174.00:03:13.21#ibcon#enter sib2, iclass 20, count 0 2006.174.00:03:13.21#ibcon#flushed, iclass 20, count 0 2006.174.00:03:13.21#ibcon#about to write, iclass 20, count 0 2006.174.00:03:13.21#ibcon#wrote, iclass 20, count 0 2006.174.00:03:13.21#ibcon#about to read 3, iclass 20, count 0 2006.174.00:03:13.23#ibcon#read 3, iclass 20, count 0 2006.174.00:03:13.23#ibcon#about to read 4, iclass 20, count 0 2006.174.00:03:13.23#ibcon#read 4, iclass 20, count 0 2006.174.00:03:13.23#ibcon#about to read 5, iclass 20, count 0 2006.174.00:03:13.23#ibcon#read 5, iclass 20, count 0 2006.174.00:03:13.23#ibcon#about to read 6, iclass 20, count 0 2006.174.00:03:13.23#ibcon#read 6, iclass 20, count 0 2006.174.00:03:13.23#ibcon#end of sib2, iclass 20, count 0 2006.174.00:03:13.23#ibcon#*mode == 0, iclass 20, count 0 2006.174.00:03:13.23#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.174.00:03:13.23#ibcon#[28=FRQ=05,709.99\r\n] 2006.174.00:03:13.23#ibcon#*before write, iclass 20, count 0 2006.174.00:03:13.23#ibcon#enter sib2, iclass 20, count 0 2006.174.00:03:13.23#ibcon#flushed, iclass 20, count 0 2006.174.00:03:13.23#ibcon#about to write, iclass 20, count 0 2006.174.00:03:13.23#ibcon#wrote, iclass 20, count 0 2006.174.00:03:13.23#ibcon#about to read 3, iclass 20, count 0 2006.174.00:03:13.27#ibcon#read 3, iclass 20, count 0 2006.174.00:03:13.27#ibcon#about to read 4, iclass 20, count 0 2006.174.00:03:13.27#ibcon#read 4, iclass 20, count 0 2006.174.00:03:13.27#ibcon#about to read 5, iclass 20, count 0 2006.174.00:03:13.27#ibcon#read 5, iclass 20, count 0 2006.174.00:03:13.27#ibcon#about to read 6, iclass 20, count 0 2006.174.00:03:13.27#ibcon#read 6, iclass 20, count 0 2006.174.00:03:13.27#ibcon#end of sib2, iclass 20, count 0 2006.174.00:03:13.27#ibcon#*after write, iclass 20, count 0 2006.174.00:03:13.27#ibcon#*before return 0, iclass 20, count 0 2006.174.00:03:13.27#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.174.00:03:13.27#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.174.00:03:13.27#ibcon#about to clear, iclass 20 cls_cnt 0 2006.174.00:03:13.27#ibcon#cleared, iclass 20 cls_cnt 0 2006.174.00:03:13.27$vck44/vb=5,4 2006.174.00:03:13.27#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.174.00:03:13.27#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.174.00:03:13.27#ibcon#ireg 11 cls_cnt 2 2006.174.00:03:13.27#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.174.00:03:13.33#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.174.00:03:13.33#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.174.00:03:13.33#ibcon#enter wrdev, iclass 22, count 2 2006.174.00:03:13.33#ibcon#first serial, iclass 22, count 2 2006.174.00:03:13.33#ibcon#enter sib2, iclass 22, count 2 2006.174.00:03:13.33#ibcon#flushed, iclass 22, count 2 2006.174.00:03:13.33#ibcon#about to write, iclass 22, count 2 2006.174.00:03:13.33#ibcon#wrote, iclass 22, count 2 2006.174.00:03:13.33#ibcon#about to read 3, iclass 22, count 2 2006.174.00:03:13.35#ibcon#read 3, iclass 22, count 2 2006.174.00:03:13.35#ibcon#about to read 4, iclass 22, count 2 2006.174.00:03:13.35#ibcon#read 4, iclass 22, count 2 2006.174.00:03:13.35#ibcon#about to read 5, iclass 22, count 2 2006.174.00:03:13.35#ibcon#read 5, iclass 22, count 2 2006.174.00:03:13.35#ibcon#about to read 6, iclass 22, count 2 2006.174.00:03:13.35#ibcon#read 6, iclass 22, count 2 2006.174.00:03:13.35#ibcon#end of sib2, iclass 22, count 2 2006.174.00:03:13.35#ibcon#*mode == 0, iclass 22, count 2 2006.174.00:03:13.35#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.174.00:03:13.35#ibcon#[27=AT05-04\r\n] 2006.174.00:03:13.35#ibcon#*before write, iclass 22, count 2 2006.174.00:03:13.35#ibcon#enter sib2, iclass 22, count 2 2006.174.00:03:13.35#ibcon#flushed, iclass 22, count 2 2006.174.00:03:13.35#ibcon#about to write, iclass 22, count 2 2006.174.00:03:13.35#ibcon#wrote, iclass 22, count 2 2006.174.00:03:13.35#ibcon#about to read 3, iclass 22, count 2 2006.174.00:03:13.38#ibcon#read 3, iclass 22, count 2 2006.174.00:03:13.38#ibcon#about to read 4, iclass 22, count 2 2006.174.00:03:13.38#ibcon#read 4, iclass 22, count 2 2006.174.00:03:13.38#ibcon#about to read 5, iclass 22, count 2 2006.174.00:03:13.38#ibcon#read 5, iclass 22, count 2 2006.174.00:03:13.38#ibcon#about to read 6, iclass 22, count 2 2006.174.00:03:13.38#ibcon#read 6, iclass 22, count 2 2006.174.00:03:13.38#ibcon#end of sib2, iclass 22, count 2 2006.174.00:03:13.38#ibcon#*after write, iclass 22, count 2 2006.174.00:03:13.38#ibcon#*before return 0, iclass 22, count 2 2006.174.00:03:13.38#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.174.00:03:13.38#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.174.00:03:13.38#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.174.00:03:13.38#ibcon#ireg 7 cls_cnt 0 2006.174.00:03:13.38#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.174.00:03:13.50#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.174.00:03:13.50#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.174.00:03:13.50#ibcon#enter wrdev, iclass 22, count 0 2006.174.00:03:13.50#ibcon#first serial, iclass 22, count 0 2006.174.00:03:13.50#ibcon#enter sib2, iclass 22, count 0 2006.174.00:03:13.50#ibcon#flushed, iclass 22, count 0 2006.174.00:03:13.50#ibcon#about to write, iclass 22, count 0 2006.174.00:03:13.50#ibcon#wrote, iclass 22, count 0 2006.174.00:03:13.50#ibcon#about to read 3, iclass 22, count 0 2006.174.00:03:13.52#ibcon#read 3, iclass 22, count 0 2006.174.00:03:13.52#ibcon#about to read 4, iclass 22, count 0 2006.174.00:03:13.52#ibcon#read 4, iclass 22, count 0 2006.174.00:03:13.52#ibcon#about to read 5, iclass 22, count 0 2006.174.00:03:13.52#ibcon#read 5, iclass 22, count 0 2006.174.00:03:13.52#ibcon#about to read 6, iclass 22, count 0 2006.174.00:03:13.52#ibcon#read 6, iclass 22, count 0 2006.174.00:03:13.52#ibcon#end of sib2, iclass 22, count 0 2006.174.00:03:13.52#ibcon#*mode == 0, iclass 22, count 0 2006.174.00:03:13.52#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.174.00:03:13.52#ibcon#[27=USB\r\n] 2006.174.00:03:13.52#ibcon#*before write, iclass 22, count 0 2006.174.00:03:13.52#ibcon#enter sib2, iclass 22, count 0 2006.174.00:03:13.52#ibcon#flushed, iclass 22, count 0 2006.174.00:03:13.52#ibcon#about to write, iclass 22, count 0 2006.174.00:03:13.52#ibcon#wrote, iclass 22, count 0 2006.174.00:03:13.52#ibcon#about to read 3, iclass 22, count 0 2006.174.00:03:13.55#ibcon#read 3, iclass 22, count 0 2006.174.00:03:13.55#ibcon#about to read 4, iclass 22, count 0 2006.174.00:03:13.55#ibcon#read 4, iclass 22, count 0 2006.174.00:03:13.55#ibcon#about to read 5, iclass 22, count 0 2006.174.00:03:13.55#ibcon#read 5, iclass 22, count 0 2006.174.00:03:13.55#ibcon#about to read 6, iclass 22, count 0 2006.174.00:03:13.55#ibcon#read 6, iclass 22, count 0 2006.174.00:03:13.55#ibcon#end of sib2, iclass 22, count 0 2006.174.00:03:13.55#ibcon#*after write, iclass 22, count 0 2006.174.00:03:13.55#ibcon#*before return 0, iclass 22, count 0 2006.174.00:03:13.55#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.174.00:03:13.55#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.174.00:03:13.55#ibcon#about to clear, iclass 22 cls_cnt 0 2006.174.00:03:13.55#ibcon#cleared, iclass 22 cls_cnt 0 2006.174.00:03:13.55$vck44/vblo=6,719.99 2006.174.00:03:13.55#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.174.00:03:13.55#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.174.00:03:13.55#ibcon#ireg 17 cls_cnt 0 2006.174.00:03:13.55#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.174.00:03:13.55#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.174.00:03:13.55#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.174.00:03:13.55#ibcon#enter wrdev, iclass 24, count 0 2006.174.00:03:13.55#ibcon#first serial, iclass 24, count 0 2006.174.00:03:13.55#ibcon#enter sib2, iclass 24, count 0 2006.174.00:03:13.55#ibcon#flushed, iclass 24, count 0 2006.174.00:03:13.55#ibcon#about to write, iclass 24, count 0 2006.174.00:03:13.55#ibcon#wrote, iclass 24, count 0 2006.174.00:03:13.55#ibcon#about to read 3, iclass 24, count 0 2006.174.00:03:13.57#ibcon#read 3, iclass 24, count 0 2006.174.00:03:13.57#ibcon#about to read 4, iclass 24, count 0 2006.174.00:03:13.57#ibcon#read 4, iclass 24, count 0 2006.174.00:03:13.57#ibcon#about to read 5, iclass 24, count 0 2006.174.00:03:13.57#ibcon#read 5, iclass 24, count 0 2006.174.00:03:13.57#ibcon#about to read 6, iclass 24, count 0 2006.174.00:03:13.57#ibcon#read 6, iclass 24, count 0 2006.174.00:03:13.57#ibcon#end of sib2, iclass 24, count 0 2006.174.00:03:13.57#ibcon#*mode == 0, iclass 24, count 0 2006.174.00:03:13.57#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.174.00:03:13.57#ibcon#[28=FRQ=06,719.99\r\n] 2006.174.00:03:13.57#ibcon#*before write, iclass 24, count 0 2006.174.00:03:13.57#ibcon#enter sib2, iclass 24, count 0 2006.174.00:03:13.57#ibcon#flushed, iclass 24, count 0 2006.174.00:03:13.57#ibcon#about to write, iclass 24, count 0 2006.174.00:03:13.57#ibcon#wrote, iclass 24, count 0 2006.174.00:03:13.57#ibcon#about to read 3, iclass 24, count 0 2006.174.00:03:13.61#ibcon#read 3, iclass 24, count 0 2006.174.00:03:13.61#ibcon#about to read 4, iclass 24, count 0 2006.174.00:03:13.61#ibcon#read 4, iclass 24, count 0 2006.174.00:03:13.61#ibcon#about to read 5, iclass 24, count 0 2006.174.00:03:13.61#ibcon#read 5, iclass 24, count 0 2006.174.00:03:13.61#ibcon#about to read 6, iclass 24, count 0 2006.174.00:03:13.61#ibcon#read 6, iclass 24, count 0 2006.174.00:03:13.61#ibcon#end of sib2, iclass 24, count 0 2006.174.00:03:13.61#ibcon#*after write, iclass 24, count 0 2006.174.00:03:13.61#ibcon#*before return 0, iclass 24, count 0 2006.174.00:03:13.61#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.174.00:03:13.61#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.174.00:03:13.61#ibcon#about to clear, iclass 24 cls_cnt 0 2006.174.00:03:13.61#ibcon#cleared, iclass 24 cls_cnt 0 2006.174.00:03:13.61$vck44/vb=6,4 2006.174.00:03:13.61#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.174.00:03:13.61#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.174.00:03:13.61#ibcon#ireg 11 cls_cnt 2 2006.174.00:03:13.61#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.174.00:03:13.67#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.174.00:03:13.67#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.174.00:03:13.67#ibcon#enter wrdev, iclass 26, count 2 2006.174.00:03:13.67#ibcon#first serial, iclass 26, count 2 2006.174.00:03:13.67#ibcon#enter sib2, iclass 26, count 2 2006.174.00:03:13.67#ibcon#flushed, iclass 26, count 2 2006.174.00:03:13.67#ibcon#about to write, iclass 26, count 2 2006.174.00:03:13.67#ibcon#wrote, iclass 26, count 2 2006.174.00:03:13.67#ibcon#about to read 3, iclass 26, count 2 2006.174.00:03:13.69#ibcon#read 3, iclass 26, count 2 2006.174.00:03:13.69#ibcon#about to read 4, iclass 26, count 2 2006.174.00:03:13.69#ibcon#read 4, iclass 26, count 2 2006.174.00:03:13.69#ibcon#about to read 5, iclass 26, count 2 2006.174.00:03:13.69#ibcon#read 5, iclass 26, count 2 2006.174.00:03:13.69#ibcon#about to read 6, iclass 26, count 2 2006.174.00:03:13.69#ibcon#read 6, iclass 26, count 2 2006.174.00:03:13.69#ibcon#end of sib2, iclass 26, count 2 2006.174.00:03:13.69#ibcon#*mode == 0, iclass 26, count 2 2006.174.00:03:13.69#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.174.00:03:13.69#ibcon#[27=AT06-04\r\n] 2006.174.00:03:13.69#ibcon#*before write, iclass 26, count 2 2006.174.00:03:13.69#ibcon#enter sib2, iclass 26, count 2 2006.174.00:03:13.69#ibcon#flushed, iclass 26, count 2 2006.174.00:03:13.69#ibcon#about to write, iclass 26, count 2 2006.174.00:03:13.69#ibcon#wrote, iclass 26, count 2 2006.174.00:03:13.69#ibcon#about to read 3, iclass 26, count 2 2006.174.00:03:13.72#ibcon#read 3, iclass 26, count 2 2006.174.00:03:13.72#ibcon#about to read 4, iclass 26, count 2 2006.174.00:03:13.72#ibcon#read 4, iclass 26, count 2 2006.174.00:03:13.72#ibcon#about to read 5, iclass 26, count 2 2006.174.00:03:13.72#ibcon#read 5, iclass 26, count 2 2006.174.00:03:13.72#ibcon#about to read 6, iclass 26, count 2 2006.174.00:03:13.72#ibcon#read 6, iclass 26, count 2 2006.174.00:03:13.72#ibcon#end of sib2, iclass 26, count 2 2006.174.00:03:13.72#ibcon#*after write, iclass 26, count 2 2006.174.00:03:13.72#ibcon#*before return 0, iclass 26, count 2 2006.174.00:03:13.72#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.174.00:03:13.72#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.174.00:03:13.72#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.174.00:03:13.72#ibcon#ireg 7 cls_cnt 0 2006.174.00:03:13.72#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.174.00:03:13.84#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.174.00:03:13.84#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.174.00:03:13.84#ibcon#enter wrdev, iclass 26, count 0 2006.174.00:03:13.84#ibcon#first serial, iclass 26, count 0 2006.174.00:03:13.84#ibcon#enter sib2, iclass 26, count 0 2006.174.00:03:13.84#ibcon#flushed, iclass 26, count 0 2006.174.00:03:13.84#ibcon#about to write, iclass 26, count 0 2006.174.00:03:13.84#ibcon#wrote, iclass 26, count 0 2006.174.00:03:13.84#ibcon#about to read 3, iclass 26, count 0 2006.174.00:03:13.86#ibcon#read 3, iclass 26, count 0 2006.174.00:03:13.86#ibcon#about to read 4, iclass 26, count 0 2006.174.00:03:13.86#ibcon#read 4, iclass 26, count 0 2006.174.00:03:13.86#ibcon#about to read 5, iclass 26, count 0 2006.174.00:03:13.86#ibcon#read 5, iclass 26, count 0 2006.174.00:03:13.86#ibcon#about to read 6, iclass 26, count 0 2006.174.00:03:13.86#ibcon#read 6, iclass 26, count 0 2006.174.00:03:13.86#ibcon#end of sib2, iclass 26, count 0 2006.174.00:03:13.86#ibcon#*mode == 0, iclass 26, count 0 2006.174.00:03:13.86#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.174.00:03:13.86#ibcon#[27=USB\r\n] 2006.174.00:03:13.86#ibcon#*before write, iclass 26, count 0 2006.174.00:03:13.86#ibcon#enter sib2, iclass 26, count 0 2006.174.00:03:13.86#ibcon#flushed, iclass 26, count 0 2006.174.00:03:13.86#ibcon#about to write, iclass 26, count 0 2006.174.00:03:13.86#ibcon#wrote, iclass 26, count 0 2006.174.00:03:13.86#ibcon#about to read 3, iclass 26, count 0 2006.174.00:03:13.89#ibcon#read 3, iclass 26, count 0 2006.174.00:03:13.89#ibcon#about to read 4, iclass 26, count 0 2006.174.00:03:13.89#ibcon#read 4, iclass 26, count 0 2006.174.00:03:13.89#ibcon#about to read 5, iclass 26, count 0 2006.174.00:03:13.89#ibcon#read 5, iclass 26, count 0 2006.174.00:03:13.89#ibcon#about to read 6, iclass 26, count 0 2006.174.00:03:13.89#ibcon#read 6, iclass 26, count 0 2006.174.00:03:13.89#ibcon#end of sib2, iclass 26, count 0 2006.174.00:03:13.89#ibcon#*after write, iclass 26, count 0 2006.174.00:03:13.89#ibcon#*before return 0, iclass 26, count 0 2006.174.00:03:13.89#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.174.00:03:13.89#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.174.00:03:13.89#ibcon#about to clear, iclass 26 cls_cnt 0 2006.174.00:03:13.89#ibcon#cleared, iclass 26 cls_cnt 0 2006.174.00:03:13.89$vck44/vblo=7,734.99 2006.174.00:03:13.89#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.174.00:03:13.89#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.174.00:03:13.89#ibcon#ireg 17 cls_cnt 0 2006.174.00:03:13.89#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.174.00:03:13.89#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.174.00:03:13.89#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.174.00:03:13.89#ibcon#enter wrdev, iclass 28, count 0 2006.174.00:03:13.89#ibcon#first serial, iclass 28, count 0 2006.174.00:03:13.89#ibcon#enter sib2, iclass 28, count 0 2006.174.00:03:13.89#ibcon#flushed, iclass 28, count 0 2006.174.00:03:13.89#ibcon#about to write, iclass 28, count 0 2006.174.00:03:13.89#ibcon#wrote, iclass 28, count 0 2006.174.00:03:13.89#ibcon#about to read 3, iclass 28, count 0 2006.174.00:03:13.91#ibcon#read 3, iclass 28, count 0 2006.174.00:03:13.91#ibcon#about to read 4, iclass 28, count 0 2006.174.00:03:13.91#ibcon#read 4, iclass 28, count 0 2006.174.00:03:13.91#ibcon#about to read 5, iclass 28, count 0 2006.174.00:03:13.91#ibcon#read 5, iclass 28, count 0 2006.174.00:03:13.91#ibcon#about to read 6, iclass 28, count 0 2006.174.00:03:13.91#ibcon#read 6, iclass 28, count 0 2006.174.00:03:13.91#ibcon#end of sib2, iclass 28, count 0 2006.174.00:03:13.91#ibcon#*mode == 0, iclass 28, count 0 2006.174.00:03:13.91#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.174.00:03:13.91#ibcon#[28=FRQ=07,734.99\r\n] 2006.174.00:03:13.91#ibcon#*before write, iclass 28, count 0 2006.174.00:03:13.91#ibcon#enter sib2, iclass 28, count 0 2006.174.00:03:13.91#ibcon#flushed, iclass 28, count 0 2006.174.00:03:13.91#ibcon#about to write, iclass 28, count 0 2006.174.00:03:13.91#ibcon#wrote, iclass 28, count 0 2006.174.00:03:13.91#ibcon#about to read 3, iclass 28, count 0 2006.174.00:03:13.95#ibcon#read 3, iclass 28, count 0 2006.174.00:03:13.95#ibcon#about to read 4, iclass 28, count 0 2006.174.00:03:13.95#ibcon#read 4, iclass 28, count 0 2006.174.00:03:13.95#ibcon#about to read 5, iclass 28, count 0 2006.174.00:03:13.95#ibcon#read 5, iclass 28, count 0 2006.174.00:03:13.95#ibcon#about to read 6, iclass 28, count 0 2006.174.00:03:13.95#ibcon#read 6, iclass 28, count 0 2006.174.00:03:13.95#ibcon#end of sib2, iclass 28, count 0 2006.174.00:03:13.95#ibcon#*after write, iclass 28, count 0 2006.174.00:03:13.95#ibcon#*before return 0, iclass 28, count 0 2006.174.00:03:13.95#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.174.00:03:13.95#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.174.00:03:13.95#ibcon#about to clear, iclass 28 cls_cnt 0 2006.174.00:03:13.95#ibcon#cleared, iclass 28 cls_cnt 0 2006.174.00:03:13.95$vck44/vb=7,4 2006.174.00:03:13.95#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.174.00:03:13.95#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.174.00:03:13.95#ibcon#ireg 11 cls_cnt 2 2006.174.00:03:13.95#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.174.00:03:14.01#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.174.00:03:14.01#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.174.00:03:14.01#ibcon#enter wrdev, iclass 30, count 2 2006.174.00:03:14.01#ibcon#first serial, iclass 30, count 2 2006.174.00:03:14.01#ibcon#enter sib2, iclass 30, count 2 2006.174.00:03:14.01#ibcon#flushed, iclass 30, count 2 2006.174.00:03:14.01#ibcon#about to write, iclass 30, count 2 2006.174.00:03:14.01#ibcon#wrote, iclass 30, count 2 2006.174.00:03:14.01#ibcon#about to read 3, iclass 30, count 2 2006.174.00:03:14.03#ibcon#read 3, iclass 30, count 2 2006.174.00:03:14.03#ibcon#about to read 4, iclass 30, count 2 2006.174.00:03:14.03#ibcon#read 4, iclass 30, count 2 2006.174.00:03:14.03#ibcon#about to read 5, iclass 30, count 2 2006.174.00:03:14.03#ibcon#read 5, iclass 30, count 2 2006.174.00:03:14.03#ibcon#about to read 6, iclass 30, count 2 2006.174.00:03:14.03#ibcon#read 6, iclass 30, count 2 2006.174.00:03:14.03#ibcon#end of sib2, iclass 30, count 2 2006.174.00:03:14.03#ibcon#*mode == 0, iclass 30, count 2 2006.174.00:03:14.03#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.174.00:03:14.03#ibcon#[27=AT07-04\r\n] 2006.174.00:03:14.03#ibcon#*before write, iclass 30, count 2 2006.174.00:03:14.03#ibcon#enter sib2, iclass 30, count 2 2006.174.00:03:14.03#ibcon#flushed, iclass 30, count 2 2006.174.00:03:14.03#ibcon#about to write, iclass 30, count 2 2006.174.00:03:14.03#ibcon#wrote, iclass 30, count 2 2006.174.00:03:14.03#ibcon#about to read 3, iclass 30, count 2 2006.174.00:03:14.06#ibcon#read 3, iclass 30, count 2 2006.174.00:03:14.06#ibcon#about to read 4, iclass 30, count 2 2006.174.00:03:14.06#ibcon#read 4, iclass 30, count 2 2006.174.00:03:14.06#ibcon#about to read 5, iclass 30, count 2 2006.174.00:03:14.06#ibcon#read 5, iclass 30, count 2 2006.174.00:03:14.06#ibcon#about to read 6, iclass 30, count 2 2006.174.00:03:14.06#ibcon#read 6, iclass 30, count 2 2006.174.00:03:14.06#ibcon#end of sib2, iclass 30, count 2 2006.174.00:03:14.06#ibcon#*after write, iclass 30, count 2 2006.174.00:03:14.06#ibcon#*before return 0, iclass 30, count 2 2006.174.00:03:14.06#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.174.00:03:14.06#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.174.00:03:14.06#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.174.00:03:14.06#ibcon#ireg 7 cls_cnt 0 2006.174.00:03:14.06#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.174.00:03:14.18#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.174.00:03:14.18#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.174.00:03:14.18#ibcon#enter wrdev, iclass 30, count 0 2006.174.00:03:14.18#ibcon#first serial, iclass 30, count 0 2006.174.00:03:14.18#ibcon#enter sib2, iclass 30, count 0 2006.174.00:03:14.18#ibcon#flushed, iclass 30, count 0 2006.174.00:03:14.18#ibcon#about to write, iclass 30, count 0 2006.174.00:03:14.18#ibcon#wrote, iclass 30, count 0 2006.174.00:03:14.18#ibcon#about to read 3, iclass 30, count 0 2006.174.00:03:14.20#ibcon#read 3, iclass 30, count 0 2006.174.00:03:14.20#ibcon#about to read 4, iclass 30, count 0 2006.174.00:03:14.20#ibcon#read 4, iclass 30, count 0 2006.174.00:03:14.20#ibcon#about to read 5, iclass 30, count 0 2006.174.00:03:14.20#ibcon#read 5, iclass 30, count 0 2006.174.00:03:14.20#ibcon#about to read 6, iclass 30, count 0 2006.174.00:03:14.20#ibcon#read 6, iclass 30, count 0 2006.174.00:03:14.20#ibcon#end of sib2, iclass 30, count 0 2006.174.00:03:14.20#ibcon#*mode == 0, iclass 30, count 0 2006.174.00:03:14.20#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.174.00:03:14.20#ibcon#[27=USB\r\n] 2006.174.00:03:14.20#ibcon#*before write, iclass 30, count 0 2006.174.00:03:14.20#ibcon#enter sib2, iclass 30, count 0 2006.174.00:03:14.20#ibcon#flushed, iclass 30, count 0 2006.174.00:03:14.20#ibcon#about to write, iclass 30, count 0 2006.174.00:03:14.20#ibcon#wrote, iclass 30, count 0 2006.174.00:03:14.20#ibcon#about to read 3, iclass 30, count 0 2006.174.00:03:14.23#ibcon#read 3, iclass 30, count 0 2006.174.00:03:14.23#ibcon#about to read 4, iclass 30, count 0 2006.174.00:03:14.23#ibcon#read 4, iclass 30, count 0 2006.174.00:03:14.23#ibcon#about to read 5, iclass 30, count 0 2006.174.00:03:14.23#ibcon#read 5, iclass 30, count 0 2006.174.00:03:14.23#ibcon#about to read 6, iclass 30, count 0 2006.174.00:03:14.23#ibcon#read 6, iclass 30, count 0 2006.174.00:03:14.23#ibcon#end of sib2, iclass 30, count 0 2006.174.00:03:14.23#ibcon#*after write, iclass 30, count 0 2006.174.00:03:14.23#ibcon#*before return 0, iclass 30, count 0 2006.174.00:03:14.23#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.174.00:03:14.23#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.174.00:03:14.23#ibcon#about to clear, iclass 30 cls_cnt 0 2006.174.00:03:14.23#ibcon#cleared, iclass 30 cls_cnt 0 2006.174.00:03:14.23$vck44/vblo=8,744.99 2006.174.00:03:14.23#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.174.00:03:14.23#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.174.00:03:14.23#ibcon#ireg 17 cls_cnt 0 2006.174.00:03:14.23#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.174.00:03:14.23#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.174.00:03:14.23#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.174.00:03:14.23#ibcon#enter wrdev, iclass 32, count 0 2006.174.00:03:14.23#ibcon#first serial, iclass 32, count 0 2006.174.00:03:14.23#ibcon#enter sib2, iclass 32, count 0 2006.174.00:03:14.23#ibcon#flushed, iclass 32, count 0 2006.174.00:03:14.23#ibcon#about to write, iclass 32, count 0 2006.174.00:03:14.23#ibcon#wrote, iclass 32, count 0 2006.174.00:03:14.23#ibcon#about to read 3, iclass 32, count 0 2006.174.00:03:14.25#ibcon#read 3, iclass 32, count 0 2006.174.00:03:14.25#ibcon#about to read 4, iclass 32, count 0 2006.174.00:03:14.25#ibcon#read 4, iclass 32, count 0 2006.174.00:03:14.25#ibcon#about to read 5, iclass 32, count 0 2006.174.00:03:14.25#ibcon#read 5, iclass 32, count 0 2006.174.00:03:14.25#ibcon#about to read 6, iclass 32, count 0 2006.174.00:03:14.25#ibcon#read 6, iclass 32, count 0 2006.174.00:03:14.25#ibcon#end of sib2, iclass 32, count 0 2006.174.00:03:14.25#ibcon#*mode == 0, iclass 32, count 0 2006.174.00:03:14.25#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.174.00:03:14.25#ibcon#[28=FRQ=08,744.99\r\n] 2006.174.00:03:14.25#ibcon#*before write, iclass 32, count 0 2006.174.00:03:14.25#ibcon#enter sib2, iclass 32, count 0 2006.174.00:03:14.25#ibcon#flushed, iclass 32, count 0 2006.174.00:03:14.25#ibcon#about to write, iclass 32, count 0 2006.174.00:03:14.25#ibcon#wrote, iclass 32, count 0 2006.174.00:03:14.25#ibcon#about to read 3, iclass 32, count 0 2006.174.00:03:14.29#ibcon#read 3, iclass 32, count 0 2006.174.00:03:14.29#ibcon#about to read 4, iclass 32, count 0 2006.174.00:03:14.29#ibcon#read 4, iclass 32, count 0 2006.174.00:03:14.29#ibcon#about to read 5, iclass 32, count 0 2006.174.00:03:14.29#ibcon#read 5, iclass 32, count 0 2006.174.00:03:14.29#ibcon#about to read 6, iclass 32, count 0 2006.174.00:03:14.29#ibcon#read 6, iclass 32, count 0 2006.174.00:03:14.29#ibcon#end of sib2, iclass 32, count 0 2006.174.00:03:14.29#ibcon#*after write, iclass 32, count 0 2006.174.00:03:14.29#ibcon#*before return 0, iclass 32, count 0 2006.174.00:03:14.29#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.174.00:03:14.29#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.174.00:03:14.29#ibcon#about to clear, iclass 32 cls_cnt 0 2006.174.00:03:14.29#ibcon#cleared, iclass 32 cls_cnt 0 2006.174.00:03:14.29$vck44/vb=8,4 2006.174.00:03:14.29#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.174.00:03:14.29#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.174.00:03:14.29#ibcon#ireg 11 cls_cnt 2 2006.174.00:03:14.29#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.174.00:03:14.35#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.174.00:03:14.35#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.174.00:03:14.35#ibcon#enter wrdev, iclass 34, count 2 2006.174.00:03:14.35#ibcon#first serial, iclass 34, count 2 2006.174.00:03:14.35#ibcon#enter sib2, iclass 34, count 2 2006.174.00:03:14.35#ibcon#flushed, iclass 34, count 2 2006.174.00:03:14.35#ibcon#about to write, iclass 34, count 2 2006.174.00:03:14.35#ibcon#wrote, iclass 34, count 2 2006.174.00:03:14.35#ibcon#about to read 3, iclass 34, count 2 2006.174.00:03:14.37#ibcon#read 3, iclass 34, count 2 2006.174.00:03:14.37#ibcon#about to read 4, iclass 34, count 2 2006.174.00:03:14.37#ibcon#read 4, iclass 34, count 2 2006.174.00:03:14.37#ibcon#about to read 5, iclass 34, count 2 2006.174.00:03:14.37#ibcon#read 5, iclass 34, count 2 2006.174.00:03:14.37#ibcon#about to read 6, iclass 34, count 2 2006.174.00:03:14.37#ibcon#read 6, iclass 34, count 2 2006.174.00:03:14.37#ibcon#end of sib2, iclass 34, count 2 2006.174.00:03:14.37#ibcon#*mode == 0, iclass 34, count 2 2006.174.00:03:14.37#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.174.00:03:14.37#ibcon#[27=AT08-04\r\n] 2006.174.00:03:14.37#ibcon#*before write, iclass 34, count 2 2006.174.00:03:14.37#ibcon#enter sib2, iclass 34, count 2 2006.174.00:03:14.37#ibcon#flushed, iclass 34, count 2 2006.174.00:03:14.37#ibcon#about to write, iclass 34, count 2 2006.174.00:03:14.37#ibcon#wrote, iclass 34, count 2 2006.174.00:03:14.37#ibcon#about to read 3, iclass 34, count 2 2006.174.00:03:14.40#ibcon#read 3, iclass 34, count 2 2006.174.00:03:14.40#ibcon#about to read 4, iclass 34, count 2 2006.174.00:03:14.40#ibcon#read 4, iclass 34, count 2 2006.174.00:03:14.40#ibcon#about to read 5, iclass 34, count 2 2006.174.00:03:14.40#ibcon#read 5, iclass 34, count 2 2006.174.00:03:14.40#ibcon#about to read 6, iclass 34, count 2 2006.174.00:03:14.40#ibcon#read 6, iclass 34, count 2 2006.174.00:03:14.40#ibcon#end of sib2, iclass 34, count 2 2006.174.00:03:14.40#ibcon#*after write, iclass 34, count 2 2006.174.00:03:14.40#ibcon#*before return 0, iclass 34, count 2 2006.174.00:03:14.40#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.174.00:03:14.40#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.174.00:03:14.40#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.174.00:03:14.40#ibcon#ireg 7 cls_cnt 0 2006.174.00:03:14.40#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.174.00:03:14.52#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.174.00:03:14.52#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.174.00:03:14.52#ibcon#enter wrdev, iclass 34, count 0 2006.174.00:03:14.52#ibcon#first serial, iclass 34, count 0 2006.174.00:03:14.52#ibcon#enter sib2, iclass 34, count 0 2006.174.00:03:14.52#ibcon#flushed, iclass 34, count 0 2006.174.00:03:14.52#ibcon#about to write, iclass 34, count 0 2006.174.00:03:14.52#ibcon#wrote, iclass 34, count 0 2006.174.00:03:14.52#ibcon#about to read 3, iclass 34, count 0 2006.174.00:03:14.54#ibcon#read 3, iclass 34, count 0 2006.174.00:03:14.54#ibcon#about to read 4, iclass 34, count 0 2006.174.00:03:14.54#ibcon#read 4, iclass 34, count 0 2006.174.00:03:14.54#ibcon#about to read 5, iclass 34, count 0 2006.174.00:03:14.54#ibcon#read 5, iclass 34, count 0 2006.174.00:03:14.54#ibcon#about to read 6, iclass 34, count 0 2006.174.00:03:14.54#ibcon#read 6, iclass 34, count 0 2006.174.00:03:14.54#ibcon#end of sib2, iclass 34, count 0 2006.174.00:03:14.54#ibcon#*mode == 0, iclass 34, count 0 2006.174.00:03:14.54#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.174.00:03:14.54#ibcon#[27=USB\r\n] 2006.174.00:03:14.54#ibcon#*before write, iclass 34, count 0 2006.174.00:03:14.54#ibcon#enter sib2, iclass 34, count 0 2006.174.00:03:14.54#ibcon#flushed, iclass 34, count 0 2006.174.00:03:14.54#ibcon#about to write, iclass 34, count 0 2006.174.00:03:14.54#ibcon#wrote, iclass 34, count 0 2006.174.00:03:14.54#ibcon#about to read 3, iclass 34, count 0 2006.174.00:03:14.57#ibcon#read 3, iclass 34, count 0 2006.174.00:03:14.57#ibcon#about to read 4, iclass 34, count 0 2006.174.00:03:14.57#ibcon#read 4, iclass 34, count 0 2006.174.00:03:14.57#ibcon#about to read 5, iclass 34, count 0 2006.174.00:03:14.57#ibcon#read 5, iclass 34, count 0 2006.174.00:03:14.57#ibcon#about to read 6, iclass 34, count 0 2006.174.00:03:14.57#ibcon#read 6, iclass 34, count 0 2006.174.00:03:14.57#ibcon#end of sib2, iclass 34, count 0 2006.174.00:03:14.57#ibcon#*after write, iclass 34, count 0 2006.174.00:03:14.57#ibcon#*before return 0, iclass 34, count 0 2006.174.00:03:14.57#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.174.00:03:14.57#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.174.00:03:14.57#ibcon#about to clear, iclass 34 cls_cnt 0 2006.174.00:03:14.57#ibcon#cleared, iclass 34 cls_cnt 0 2006.174.00:03:14.57$vck44/vabw=wide 2006.174.00:03:14.57#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.174.00:03:14.57#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.174.00:03:14.57#ibcon#ireg 8 cls_cnt 0 2006.174.00:03:14.57#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.174.00:03:14.57#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.174.00:03:14.57#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.174.00:03:14.57#ibcon#enter wrdev, iclass 36, count 0 2006.174.00:03:14.57#ibcon#first serial, iclass 36, count 0 2006.174.00:03:14.57#ibcon#enter sib2, iclass 36, count 0 2006.174.00:03:14.57#ibcon#flushed, iclass 36, count 0 2006.174.00:03:14.57#ibcon#about to write, iclass 36, count 0 2006.174.00:03:14.57#ibcon#wrote, iclass 36, count 0 2006.174.00:03:14.57#ibcon#about to read 3, iclass 36, count 0 2006.174.00:03:14.59#ibcon#read 3, iclass 36, count 0 2006.174.00:03:14.59#ibcon#about to read 4, iclass 36, count 0 2006.174.00:03:14.59#ibcon#read 4, iclass 36, count 0 2006.174.00:03:14.59#ibcon#about to read 5, iclass 36, count 0 2006.174.00:03:14.59#ibcon#read 5, iclass 36, count 0 2006.174.00:03:14.59#ibcon#about to read 6, iclass 36, count 0 2006.174.00:03:14.59#ibcon#read 6, iclass 36, count 0 2006.174.00:03:14.59#ibcon#end of sib2, iclass 36, count 0 2006.174.00:03:14.59#ibcon#*mode == 0, iclass 36, count 0 2006.174.00:03:14.59#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.174.00:03:14.59#ibcon#[25=BW32\r\n] 2006.174.00:03:14.59#ibcon#*before write, iclass 36, count 0 2006.174.00:03:14.59#ibcon#enter sib2, iclass 36, count 0 2006.174.00:03:14.59#ibcon#flushed, iclass 36, count 0 2006.174.00:03:14.59#ibcon#about to write, iclass 36, count 0 2006.174.00:03:14.59#ibcon#wrote, iclass 36, count 0 2006.174.00:03:14.59#ibcon#about to read 3, iclass 36, count 0 2006.174.00:03:14.62#ibcon#read 3, iclass 36, count 0 2006.174.00:03:14.62#ibcon#about to read 4, iclass 36, count 0 2006.174.00:03:14.62#ibcon#read 4, iclass 36, count 0 2006.174.00:03:14.62#ibcon#about to read 5, iclass 36, count 0 2006.174.00:03:14.62#ibcon#read 5, iclass 36, count 0 2006.174.00:03:14.62#ibcon#about to read 6, iclass 36, count 0 2006.174.00:03:14.62#ibcon#read 6, iclass 36, count 0 2006.174.00:03:14.62#ibcon#end of sib2, iclass 36, count 0 2006.174.00:03:14.62#ibcon#*after write, iclass 36, count 0 2006.174.00:03:14.62#ibcon#*before return 0, iclass 36, count 0 2006.174.00:03:14.62#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.174.00:03:14.62#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.174.00:03:14.62#ibcon#about to clear, iclass 36 cls_cnt 0 2006.174.00:03:14.62#ibcon#cleared, iclass 36 cls_cnt 0 2006.174.00:03:14.62$vck44/vbbw=wide 2006.174.00:03:14.62#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.174.00:03:14.62#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.174.00:03:14.62#ibcon#ireg 8 cls_cnt 0 2006.174.00:03:14.62#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.174.00:03:14.69#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.174.00:03:14.69#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.174.00:03:14.69#ibcon#enter wrdev, iclass 38, count 0 2006.174.00:03:14.69#ibcon#first serial, iclass 38, count 0 2006.174.00:03:14.69#ibcon#enter sib2, iclass 38, count 0 2006.174.00:03:14.69#ibcon#flushed, iclass 38, count 0 2006.174.00:03:14.69#ibcon#about to write, iclass 38, count 0 2006.174.00:03:14.69#ibcon#wrote, iclass 38, count 0 2006.174.00:03:14.69#ibcon#about to read 3, iclass 38, count 0 2006.174.00:03:14.71#ibcon#read 3, iclass 38, count 0 2006.174.00:03:14.71#ibcon#about to read 4, iclass 38, count 0 2006.174.00:03:14.71#ibcon#read 4, iclass 38, count 0 2006.174.00:03:14.71#ibcon#about to read 5, iclass 38, count 0 2006.174.00:03:14.71#ibcon#read 5, iclass 38, count 0 2006.174.00:03:14.71#ibcon#about to read 6, iclass 38, count 0 2006.174.00:03:14.71#ibcon#read 6, iclass 38, count 0 2006.174.00:03:14.71#ibcon#end of sib2, iclass 38, count 0 2006.174.00:03:14.71#ibcon#*mode == 0, iclass 38, count 0 2006.174.00:03:14.71#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.174.00:03:14.71#ibcon#[27=BW32\r\n] 2006.174.00:03:14.71#ibcon#*before write, iclass 38, count 0 2006.174.00:03:14.71#ibcon#enter sib2, iclass 38, count 0 2006.174.00:03:14.71#ibcon#flushed, iclass 38, count 0 2006.174.00:03:14.71#ibcon#about to write, iclass 38, count 0 2006.174.00:03:14.71#ibcon#wrote, iclass 38, count 0 2006.174.00:03:14.71#ibcon#about to read 3, iclass 38, count 0 2006.174.00:03:14.74#ibcon#read 3, iclass 38, count 0 2006.174.00:03:14.74#ibcon#about to read 4, iclass 38, count 0 2006.174.00:03:14.74#ibcon#read 4, iclass 38, count 0 2006.174.00:03:14.74#ibcon#about to read 5, iclass 38, count 0 2006.174.00:03:14.74#ibcon#read 5, iclass 38, count 0 2006.174.00:03:14.74#ibcon#about to read 6, iclass 38, count 0 2006.174.00:03:14.74#ibcon#read 6, iclass 38, count 0 2006.174.00:03:14.74#ibcon#end of sib2, iclass 38, count 0 2006.174.00:03:14.74#ibcon#*after write, iclass 38, count 0 2006.174.00:03:14.74#ibcon#*before return 0, iclass 38, count 0 2006.174.00:03:14.74#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.174.00:03:14.74#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.174.00:03:14.74#ibcon#about to clear, iclass 38 cls_cnt 0 2006.174.00:03:14.74#ibcon#cleared, iclass 38 cls_cnt 0 2006.174.00:03:14.74$setupk4/ifdk4 2006.174.00:03:14.74$ifdk4/lo= 2006.174.00:03:14.74$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.174.00:03:14.74$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.174.00:03:14.74$ifdk4/patch= 2006.174.00:03:14.74$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.174.00:03:14.74$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.174.00:03:14.74$setupk4/!*+20s 2006.174.00:03:15.42#abcon#<5=/11 1.0 2.4 24.20 831003.4\r\n> 2006.174.00:03:15.44#abcon#{5=INTERFACE CLEAR} 2006.174.00:03:15.50#abcon#[5=S1D000X0/0*\r\n] 2006.174.00:03:25.59#abcon#<5=/11 1.0 2.4 24.20 831003.5\r\n> 2006.174.00:03:25.61#abcon#{5=INTERFACE CLEAR} 2006.174.00:03:25.67#abcon#[5=S1D000X0/0*\r\n] 2006.174.00:03:29.24$setupk4/"tpicd 2006.174.00:03:29.24$setupk4/echo=off 2006.174.00:03:29.24$setupk4/xlog=off 2006.174.00:03:29.24:!2006.174.00:06:02 2006.174.00:03:48.14#trakl#Source acquired 2006.174.00:03:49.14#flagr#flagr/antenna,acquired 2006.174.00:06:02.00:preob 2006.174.00:06:02.13/onsource/TRACKING 2006.174.00:06:02.13:!2006.174.00:06:12 2006.174.00:06:12.00:"tape 2006.174.00:06:12.00:"st=record 2006.174.00:06:12.00:data_valid=on 2006.174.00:06:12.00:midob 2006.174.00:06:13.13/onsource/TRACKING 2006.174.00:06:13.13/wx/24.21,1003.4,86 2006.174.00:06:13.28/cable/+6.5064E-03 2006.174.00:06:14.37/va/01,07,usb,yes,34,37 2006.174.00:06:14.37/va/02,06,usb,yes,34,35 2006.174.00:06:14.37/va/03,05,usb,yes,43,45 2006.174.00:06:14.37/va/04,06,usb,yes,35,37 2006.174.00:06:14.37/va/05,04,usb,yes,27,28 2006.174.00:06:14.37/va/06,03,usb,yes,38,38 2006.174.00:06:14.37/va/07,04,usb,yes,31,32 2006.174.00:06:14.37/va/08,04,usb,yes,26,32 2006.174.00:06:14.60/valo/01,524.99,yes,locked 2006.174.00:06:14.60/valo/02,534.99,yes,locked 2006.174.00:06:14.60/valo/03,564.99,yes,locked 2006.174.00:06:14.60/valo/04,624.99,yes,locked 2006.174.00:06:14.60/valo/05,734.99,yes,locked 2006.174.00:06:14.60/valo/06,814.99,yes,locked 2006.174.00:06:14.60/valo/07,864.99,yes,locked 2006.174.00:06:14.60/valo/08,884.99,yes,locked 2006.174.00:06:15.69/vb/01,04,usb,yes,30,27 2006.174.00:06:15.69/vb/02,04,usb,yes,31,32 2006.174.00:06:15.69/vb/03,04,usb,yes,28,31 2006.174.00:06:15.69/vb/04,04,usb,yes,32,31 2006.174.00:06:15.69/vb/05,04,usb,yes,25,27 2006.174.00:06:15.69/vb/06,04,usb,yes,29,26 2006.174.00:06:15.69/vb/07,04,usb,yes,29,29 2006.174.00:06:15.69/vb/08,04,usb,yes,27,30 2006.174.00:06:15.92/vblo/01,629.99,yes,locked 2006.174.00:06:15.92/vblo/02,634.99,yes,locked 2006.174.00:06:15.92/vblo/03,649.99,yes,locked 2006.174.00:06:15.92/vblo/04,679.99,yes,locked 2006.174.00:06:15.92/vblo/05,709.99,yes,locked 2006.174.00:06:15.92/vblo/06,719.99,yes,locked 2006.174.00:06:15.92/vblo/07,734.99,yes,locked 2006.174.00:06:15.92/vblo/08,744.99,yes,locked 2006.174.00:06:16.07/vabw/8 2006.174.00:06:16.22/vbbw/8 2006.174.00:06:16.31/xfe/off,on,14.7 2006.174.00:06:16.70/ifatt/23,28,28,28 2006.174.00:06:17.07/fmout-gps/S +3.96E-07 2006.174.00:06:17.11:!2006.174.00:10:02 2006.174.00:10:02.00:data_valid=off 2006.174.00:10:02.00:"et 2006.174.00:10:02.00:!+3s 2006.174.00:10:05.01:"tape 2006.174.00:10:05.01:postob 2006.174.00:10:05.09/cable/+6.5066E-03 2006.174.00:10:05.09/wx/24.28,1003.5,84 2006.174.00:10:06.07/fmout-gps/S +3.97E-07 2006.174.00:10:06.07:scan_name=174-0025,jd0606,160 2006.174.00:10:06.07:source=2201+315,220314.98,314538.3,2000.0,ccw 2006.174.00:10:07.14#flagr#flagr/antenna,new-source 2006.174.00:10:07.14:checkk5 2006.174.00:10:07.57/chk_autoobs//k5ts1/ autoobs is running! 2006.174.00:10:07.98/chk_autoobs//k5ts2/ autoobs is running! 2006.174.00:10:08.39/chk_autoobs//k5ts3/ autoobs is running! 2006.174.00:10:08.79/chk_autoobs//k5ts4/ autoobs is running! 2006.174.00:10:09.18/chk_obsdata//k5ts1/T1740006??a.dat file size is correct (nominal:920MB, actual:916MB). 2006.174.00:10:09.58/chk_obsdata//k5ts2/T1740006??b.dat file size is correct (nominal:920MB, actual:916MB). 2006.174.00:10:09.98/chk_obsdata//k5ts3/T1740006??c.dat file size is correct (nominal:920MB, actual:916MB). 2006.174.00:10:10.39/chk_obsdata//k5ts4/T1740006??d.dat file size is correct (nominal:920MB, actual:916MB). 2006.174.00:10:11.10/k5log//k5ts1_log_newline 2006.174.00:10:11.80/k5log//k5ts2_log_newline 2006.174.00:10:12.50/k5log//k5ts3_log_newline 2006.174.00:10:13.21/k5log//k5ts4_log_newline 2006.174.00:10:13.23/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.174.00:10:13.23:setupk4=1 2006.174.00:10:13.23$setupk4/echo=on 2006.174.00:10:13.23$setupk4/pcalon 2006.174.00:10:13.23$pcalon/"no phase cal control is implemented here 2006.174.00:10:13.23$setupk4/"tpicd=stop 2006.174.00:10:13.23$setupk4/"rec=synch_on 2006.174.00:10:13.23$setupk4/"rec_mode=128 2006.174.00:10:13.23$setupk4/!* 2006.174.00:10:13.23$setupk4/recpk4 2006.174.00:10:13.23$recpk4/recpatch= 2006.174.00:10:13.24$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.174.00:10:13.24$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.174.00:10:13.24$setupk4/vck44 2006.174.00:10:13.24$vck44/valo=1,524.99 2006.174.00:10:13.24#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.174.00:10:13.24#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.174.00:10:13.24#ibcon#ireg 17 cls_cnt 0 2006.174.00:10:13.24#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.174.00:10:13.24#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.174.00:10:13.24#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.174.00:10:13.24#ibcon#enter wrdev, iclass 31, count 0 2006.174.00:10:13.24#ibcon#first serial, iclass 31, count 0 2006.174.00:10:13.24#ibcon#enter sib2, iclass 31, count 0 2006.174.00:10:13.24#ibcon#flushed, iclass 31, count 0 2006.174.00:10:13.24#ibcon#about to write, iclass 31, count 0 2006.174.00:10:13.24#ibcon#wrote, iclass 31, count 0 2006.174.00:10:13.24#ibcon#about to read 3, iclass 31, count 0 2006.174.00:10:13.26#ibcon#read 3, iclass 31, count 0 2006.174.00:10:13.26#ibcon#about to read 4, iclass 31, count 0 2006.174.00:10:13.26#ibcon#read 4, iclass 31, count 0 2006.174.00:10:13.26#ibcon#about to read 5, iclass 31, count 0 2006.174.00:10:13.26#ibcon#read 5, iclass 31, count 0 2006.174.00:10:13.26#ibcon#about to read 6, iclass 31, count 0 2006.174.00:10:13.26#ibcon#read 6, iclass 31, count 0 2006.174.00:10:13.26#ibcon#end of sib2, iclass 31, count 0 2006.174.00:10:13.26#ibcon#*mode == 0, iclass 31, count 0 2006.174.00:10:13.26#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.174.00:10:13.26#ibcon#[26=FRQ=01,524.99\r\n] 2006.174.00:10:13.26#ibcon#*before write, iclass 31, count 0 2006.174.00:10:13.26#ibcon#enter sib2, iclass 31, count 0 2006.174.00:10:13.26#ibcon#flushed, iclass 31, count 0 2006.174.00:10:13.26#ibcon#about to write, iclass 31, count 0 2006.174.00:10:13.26#ibcon#wrote, iclass 31, count 0 2006.174.00:10:13.26#ibcon#about to read 3, iclass 31, count 0 2006.174.00:10:13.31#ibcon#read 3, iclass 31, count 0 2006.174.00:10:13.31#ibcon#about to read 4, iclass 31, count 0 2006.174.00:10:13.31#ibcon#read 4, iclass 31, count 0 2006.174.00:10:13.31#ibcon#about to read 5, iclass 31, count 0 2006.174.00:10:13.31#ibcon#read 5, iclass 31, count 0 2006.174.00:10:13.31#ibcon#about to read 6, iclass 31, count 0 2006.174.00:10:13.31#ibcon#read 6, iclass 31, count 0 2006.174.00:10:13.31#ibcon#end of sib2, iclass 31, count 0 2006.174.00:10:13.31#ibcon#*after write, iclass 31, count 0 2006.174.00:10:13.31#ibcon#*before return 0, iclass 31, count 0 2006.174.00:10:13.31#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.174.00:10:13.31#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.174.00:10:13.31#ibcon#about to clear, iclass 31 cls_cnt 0 2006.174.00:10:13.31#ibcon#cleared, iclass 31 cls_cnt 0 2006.174.00:10:13.31$vck44/va=1,7 2006.174.00:10:13.31#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.174.00:10:13.31#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.174.00:10:13.31#ibcon#ireg 11 cls_cnt 2 2006.174.00:10:13.31#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.174.00:10:13.31#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.174.00:10:13.31#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.174.00:10:13.31#ibcon#enter wrdev, iclass 33, count 2 2006.174.00:10:13.31#ibcon#first serial, iclass 33, count 2 2006.174.00:10:13.31#ibcon#enter sib2, iclass 33, count 2 2006.174.00:10:13.31#ibcon#flushed, iclass 33, count 2 2006.174.00:10:13.31#ibcon#about to write, iclass 33, count 2 2006.174.00:10:13.31#ibcon#wrote, iclass 33, count 2 2006.174.00:10:13.31#ibcon#about to read 3, iclass 33, count 2 2006.174.00:10:13.33#ibcon#read 3, iclass 33, count 2 2006.174.00:10:13.33#ibcon#about to read 4, iclass 33, count 2 2006.174.00:10:13.33#ibcon#read 4, iclass 33, count 2 2006.174.00:10:13.33#ibcon#about to read 5, iclass 33, count 2 2006.174.00:10:13.33#ibcon#read 5, iclass 33, count 2 2006.174.00:10:13.33#ibcon#about to read 6, iclass 33, count 2 2006.174.00:10:13.33#ibcon#read 6, iclass 33, count 2 2006.174.00:10:13.33#ibcon#end of sib2, iclass 33, count 2 2006.174.00:10:13.33#ibcon#*mode == 0, iclass 33, count 2 2006.174.00:10:13.33#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.174.00:10:13.33#ibcon#[25=AT01-07\r\n] 2006.174.00:10:13.33#ibcon#*before write, iclass 33, count 2 2006.174.00:10:13.33#ibcon#enter sib2, iclass 33, count 2 2006.174.00:10:13.33#ibcon#flushed, iclass 33, count 2 2006.174.00:10:13.33#ibcon#about to write, iclass 33, count 2 2006.174.00:10:13.33#ibcon#wrote, iclass 33, count 2 2006.174.00:10:13.33#ibcon#about to read 3, iclass 33, count 2 2006.174.00:10:13.36#ibcon#read 3, iclass 33, count 2 2006.174.00:10:13.36#ibcon#about to read 4, iclass 33, count 2 2006.174.00:10:13.36#ibcon#read 4, iclass 33, count 2 2006.174.00:10:13.36#ibcon#about to read 5, iclass 33, count 2 2006.174.00:10:13.36#ibcon#read 5, iclass 33, count 2 2006.174.00:10:13.36#ibcon#about to read 6, iclass 33, count 2 2006.174.00:10:13.36#ibcon#read 6, iclass 33, count 2 2006.174.00:10:13.36#ibcon#end of sib2, iclass 33, count 2 2006.174.00:10:13.36#ibcon#*after write, iclass 33, count 2 2006.174.00:10:13.36#ibcon#*before return 0, iclass 33, count 2 2006.174.00:10:13.36#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.174.00:10:13.36#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.174.00:10:13.36#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.174.00:10:13.36#ibcon#ireg 7 cls_cnt 0 2006.174.00:10:13.36#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.174.00:10:13.48#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.174.00:10:13.48#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.174.00:10:13.48#ibcon#enter wrdev, iclass 33, count 0 2006.174.00:10:13.48#ibcon#first serial, iclass 33, count 0 2006.174.00:10:13.48#ibcon#enter sib2, iclass 33, count 0 2006.174.00:10:13.48#ibcon#flushed, iclass 33, count 0 2006.174.00:10:13.48#ibcon#about to write, iclass 33, count 0 2006.174.00:10:13.48#ibcon#wrote, iclass 33, count 0 2006.174.00:10:13.48#ibcon#about to read 3, iclass 33, count 0 2006.174.00:10:13.50#ibcon#read 3, iclass 33, count 0 2006.174.00:10:13.50#ibcon#about to read 4, iclass 33, count 0 2006.174.00:10:13.50#ibcon#read 4, iclass 33, count 0 2006.174.00:10:13.50#ibcon#about to read 5, iclass 33, count 0 2006.174.00:10:13.50#ibcon#read 5, iclass 33, count 0 2006.174.00:10:13.50#ibcon#about to read 6, iclass 33, count 0 2006.174.00:10:13.50#ibcon#read 6, iclass 33, count 0 2006.174.00:10:13.50#ibcon#end of sib2, iclass 33, count 0 2006.174.00:10:13.50#ibcon#*mode == 0, iclass 33, count 0 2006.174.00:10:13.50#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.174.00:10:13.50#ibcon#[25=USB\r\n] 2006.174.00:10:13.50#ibcon#*before write, iclass 33, count 0 2006.174.00:10:13.50#ibcon#enter sib2, iclass 33, count 0 2006.174.00:10:13.50#ibcon#flushed, iclass 33, count 0 2006.174.00:10:13.50#ibcon#about to write, iclass 33, count 0 2006.174.00:10:13.50#ibcon#wrote, iclass 33, count 0 2006.174.00:10:13.50#ibcon#about to read 3, iclass 33, count 0 2006.174.00:10:13.53#ibcon#read 3, iclass 33, count 0 2006.174.00:10:13.53#ibcon#about to read 4, iclass 33, count 0 2006.174.00:10:13.53#ibcon#read 4, iclass 33, count 0 2006.174.00:10:13.53#ibcon#about to read 5, iclass 33, count 0 2006.174.00:10:13.53#ibcon#read 5, iclass 33, count 0 2006.174.00:10:13.53#ibcon#about to read 6, iclass 33, count 0 2006.174.00:10:13.53#ibcon#read 6, iclass 33, count 0 2006.174.00:10:13.53#ibcon#end of sib2, iclass 33, count 0 2006.174.00:10:13.53#ibcon#*after write, iclass 33, count 0 2006.174.00:10:13.53#ibcon#*before return 0, iclass 33, count 0 2006.174.00:10:13.53#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.174.00:10:13.53#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.174.00:10:13.53#ibcon#about to clear, iclass 33 cls_cnt 0 2006.174.00:10:13.53#ibcon#cleared, iclass 33 cls_cnt 0 2006.174.00:10:13.53$vck44/valo=2,534.99 2006.174.00:10:13.53#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.174.00:10:13.53#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.174.00:10:13.53#ibcon#ireg 17 cls_cnt 0 2006.174.00:10:13.53#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.174.00:10:13.53#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.174.00:10:13.53#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.174.00:10:13.53#ibcon#enter wrdev, iclass 35, count 0 2006.174.00:10:13.53#ibcon#first serial, iclass 35, count 0 2006.174.00:10:13.53#ibcon#enter sib2, iclass 35, count 0 2006.174.00:10:13.53#ibcon#flushed, iclass 35, count 0 2006.174.00:10:13.53#ibcon#about to write, iclass 35, count 0 2006.174.00:10:13.53#ibcon#wrote, iclass 35, count 0 2006.174.00:10:13.53#ibcon#about to read 3, iclass 35, count 0 2006.174.00:10:13.55#ibcon#read 3, iclass 35, count 0 2006.174.00:10:13.55#ibcon#about to read 4, iclass 35, count 0 2006.174.00:10:13.55#ibcon#read 4, iclass 35, count 0 2006.174.00:10:13.55#ibcon#about to read 5, iclass 35, count 0 2006.174.00:10:13.55#ibcon#read 5, iclass 35, count 0 2006.174.00:10:13.55#ibcon#about to read 6, iclass 35, count 0 2006.174.00:10:13.55#ibcon#read 6, iclass 35, count 0 2006.174.00:10:13.55#ibcon#end of sib2, iclass 35, count 0 2006.174.00:10:13.55#ibcon#*mode == 0, iclass 35, count 0 2006.174.00:10:13.55#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.174.00:10:13.55#ibcon#[26=FRQ=02,534.99\r\n] 2006.174.00:10:13.55#ibcon#*before write, iclass 35, count 0 2006.174.00:10:13.55#ibcon#enter sib2, iclass 35, count 0 2006.174.00:10:13.55#ibcon#flushed, iclass 35, count 0 2006.174.00:10:13.55#ibcon#about to write, iclass 35, count 0 2006.174.00:10:13.55#ibcon#wrote, iclass 35, count 0 2006.174.00:10:13.55#ibcon#about to read 3, iclass 35, count 0 2006.174.00:10:13.59#ibcon#read 3, iclass 35, count 0 2006.174.00:10:13.59#ibcon#about to read 4, iclass 35, count 0 2006.174.00:10:13.59#ibcon#read 4, iclass 35, count 0 2006.174.00:10:13.59#ibcon#about to read 5, iclass 35, count 0 2006.174.00:10:13.59#ibcon#read 5, iclass 35, count 0 2006.174.00:10:13.59#ibcon#about to read 6, iclass 35, count 0 2006.174.00:10:13.59#ibcon#read 6, iclass 35, count 0 2006.174.00:10:13.59#ibcon#end of sib2, iclass 35, count 0 2006.174.00:10:13.59#ibcon#*after write, iclass 35, count 0 2006.174.00:10:13.59#ibcon#*before return 0, iclass 35, count 0 2006.174.00:10:13.59#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.174.00:10:13.59#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.174.00:10:13.59#ibcon#about to clear, iclass 35 cls_cnt 0 2006.174.00:10:13.59#ibcon#cleared, iclass 35 cls_cnt 0 2006.174.00:10:13.59$vck44/va=2,6 2006.174.00:10:13.59#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.174.00:10:13.59#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.174.00:10:13.59#ibcon#ireg 11 cls_cnt 2 2006.174.00:10:13.59#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.174.00:10:13.65#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.174.00:10:13.65#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.174.00:10:13.65#ibcon#enter wrdev, iclass 37, count 2 2006.174.00:10:13.65#ibcon#first serial, iclass 37, count 2 2006.174.00:10:13.65#ibcon#enter sib2, iclass 37, count 2 2006.174.00:10:13.65#ibcon#flushed, iclass 37, count 2 2006.174.00:10:13.65#ibcon#about to write, iclass 37, count 2 2006.174.00:10:13.65#ibcon#wrote, iclass 37, count 2 2006.174.00:10:13.65#ibcon#about to read 3, iclass 37, count 2 2006.174.00:10:13.67#ibcon#read 3, iclass 37, count 2 2006.174.00:10:13.67#ibcon#about to read 4, iclass 37, count 2 2006.174.00:10:13.67#ibcon#read 4, iclass 37, count 2 2006.174.00:10:13.67#ibcon#about to read 5, iclass 37, count 2 2006.174.00:10:13.67#ibcon#read 5, iclass 37, count 2 2006.174.00:10:13.67#ibcon#about to read 6, iclass 37, count 2 2006.174.00:10:13.67#ibcon#read 6, iclass 37, count 2 2006.174.00:10:13.67#ibcon#end of sib2, iclass 37, count 2 2006.174.00:10:13.67#ibcon#*mode == 0, iclass 37, count 2 2006.174.00:10:13.67#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.174.00:10:13.67#ibcon#[25=AT02-06\r\n] 2006.174.00:10:13.67#ibcon#*before write, iclass 37, count 2 2006.174.00:10:13.67#ibcon#enter sib2, iclass 37, count 2 2006.174.00:10:13.67#ibcon#flushed, iclass 37, count 2 2006.174.00:10:13.67#ibcon#about to write, iclass 37, count 2 2006.174.00:10:13.67#ibcon#wrote, iclass 37, count 2 2006.174.00:10:13.67#ibcon#about to read 3, iclass 37, count 2 2006.174.00:10:13.70#ibcon#read 3, iclass 37, count 2 2006.174.00:10:13.70#ibcon#about to read 4, iclass 37, count 2 2006.174.00:10:13.70#ibcon#read 4, iclass 37, count 2 2006.174.00:10:13.70#ibcon#about to read 5, iclass 37, count 2 2006.174.00:10:13.70#ibcon#read 5, iclass 37, count 2 2006.174.00:10:13.70#ibcon#about to read 6, iclass 37, count 2 2006.174.00:10:13.70#ibcon#read 6, iclass 37, count 2 2006.174.00:10:13.70#ibcon#end of sib2, iclass 37, count 2 2006.174.00:10:13.70#ibcon#*after write, iclass 37, count 2 2006.174.00:10:13.70#ibcon#*before return 0, iclass 37, count 2 2006.174.00:10:13.70#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.174.00:10:13.70#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.174.00:10:13.70#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.174.00:10:13.70#ibcon#ireg 7 cls_cnt 0 2006.174.00:10:13.70#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.174.00:10:13.82#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.174.00:10:13.82#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.174.00:10:13.82#ibcon#enter wrdev, iclass 37, count 0 2006.174.00:10:13.82#ibcon#first serial, iclass 37, count 0 2006.174.00:10:13.82#ibcon#enter sib2, iclass 37, count 0 2006.174.00:10:13.82#ibcon#flushed, iclass 37, count 0 2006.174.00:10:13.82#ibcon#about to write, iclass 37, count 0 2006.174.00:10:13.82#ibcon#wrote, iclass 37, count 0 2006.174.00:10:13.82#ibcon#about to read 3, iclass 37, count 0 2006.174.00:10:13.84#ibcon#read 3, iclass 37, count 0 2006.174.00:10:13.84#ibcon#about to read 4, iclass 37, count 0 2006.174.00:10:13.84#ibcon#read 4, iclass 37, count 0 2006.174.00:10:13.84#ibcon#about to read 5, iclass 37, count 0 2006.174.00:10:13.84#ibcon#read 5, iclass 37, count 0 2006.174.00:10:13.84#ibcon#about to read 6, iclass 37, count 0 2006.174.00:10:13.84#ibcon#read 6, iclass 37, count 0 2006.174.00:10:13.84#ibcon#end of sib2, iclass 37, count 0 2006.174.00:10:13.84#ibcon#*mode == 0, iclass 37, count 0 2006.174.00:10:13.84#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.174.00:10:13.84#ibcon#[25=USB\r\n] 2006.174.00:10:13.84#ibcon#*before write, iclass 37, count 0 2006.174.00:10:13.84#ibcon#enter sib2, iclass 37, count 0 2006.174.00:10:13.84#ibcon#flushed, iclass 37, count 0 2006.174.00:10:13.84#ibcon#about to write, iclass 37, count 0 2006.174.00:10:13.84#ibcon#wrote, iclass 37, count 0 2006.174.00:10:13.84#ibcon#about to read 3, iclass 37, count 0 2006.174.00:10:13.87#ibcon#read 3, iclass 37, count 0 2006.174.00:10:13.87#ibcon#about to read 4, iclass 37, count 0 2006.174.00:10:13.87#ibcon#read 4, iclass 37, count 0 2006.174.00:10:13.87#ibcon#about to read 5, iclass 37, count 0 2006.174.00:10:13.87#ibcon#read 5, iclass 37, count 0 2006.174.00:10:13.87#ibcon#about to read 6, iclass 37, count 0 2006.174.00:10:13.87#ibcon#read 6, iclass 37, count 0 2006.174.00:10:13.87#ibcon#end of sib2, iclass 37, count 0 2006.174.00:10:13.87#ibcon#*after write, iclass 37, count 0 2006.174.00:10:13.87#ibcon#*before return 0, iclass 37, count 0 2006.174.00:10:13.87#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.174.00:10:13.87#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.174.00:10:13.87#ibcon#about to clear, iclass 37 cls_cnt 0 2006.174.00:10:13.87#ibcon#cleared, iclass 37 cls_cnt 0 2006.174.00:10:13.87$vck44/valo=3,564.99 2006.174.00:10:13.87#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.174.00:10:13.87#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.174.00:10:13.87#ibcon#ireg 17 cls_cnt 0 2006.174.00:10:13.87#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.174.00:10:13.87#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.174.00:10:13.87#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.174.00:10:13.87#ibcon#enter wrdev, iclass 39, count 0 2006.174.00:10:13.87#ibcon#first serial, iclass 39, count 0 2006.174.00:10:13.87#ibcon#enter sib2, iclass 39, count 0 2006.174.00:10:13.87#ibcon#flushed, iclass 39, count 0 2006.174.00:10:13.87#ibcon#about to write, iclass 39, count 0 2006.174.00:10:13.87#ibcon#wrote, iclass 39, count 0 2006.174.00:10:13.87#ibcon#about to read 3, iclass 39, count 0 2006.174.00:10:13.89#ibcon#read 3, iclass 39, count 0 2006.174.00:10:13.89#ibcon#about to read 4, iclass 39, count 0 2006.174.00:10:13.89#ibcon#read 4, iclass 39, count 0 2006.174.00:10:13.89#ibcon#about to read 5, iclass 39, count 0 2006.174.00:10:13.89#ibcon#read 5, iclass 39, count 0 2006.174.00:10:13.89#ibcon#about to read 6, iclass 39, count 0 2006.174.00:10:13.89#ibcon#read 6, iclass 39, count 0 2006.174.00:10:13.89#ibcon#end of sib2, iclass 39, count 0 2006.174.00:10:13.89#ibcon#*mode == 0, iclass 39, count 0 2006.174.00:10:13.89#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.174.00:10:13.89#ibcon#[26=FRQ=03,564.99\r\n] 2006.174.00:10:13.89#ibcon#*before write, iclass 39, count 0 2006.174.00:10:13.89#ibcon#enter sib2, iclass 39, count 0 2006.174.00:10:13.89#ibcon#flushed, iclass 39, count 0 2006.174.00:10:13.89#ibcon#about to write, iclass 39, count 0 2006.174.00:10:13.89#ibcon#wrote, iclass 39, count 0 2006.174.00:10:13.89#ibcon#about to read 3, iclass 39, count 0 2006.174.00:10:13.93#ibcon#read 3, iclass 39, count 0 2006.174.00:10:13.93#ibcon#about to read 4, iclass 39, count 0 2006.174.00:10:13.93#ibcon#read 4, iclass 39, count 0 2006.174.00:10:13.93#ibcon#about to read 5, iclass 39, count 0 2006.174.00:10:13.93#ibcon#read 5, iclass 39, count 0 2006.174.00:10:13.93#ibcon#about to read 6, iclass 39, count 0 2006.174.00:10:13.93#ibcon#read 6, iclass 39, count 0 2006.174.00:10:13.93#ibcon#end of sib2, iclass 39, count 0 2006.174.00:10:13.93#ibcon#*after write, iclass 39, count 0 2006.174.00:10:13.93#ibcon#*before return 0, iclass 39, count 0 2006.174.00:10:13.93#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.174.00:10:13.93#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.174.00:10:13.93#ibcon#about to clear, iclass 39 cls_cnt 0 2006.174.00:10:13.93#ibcon#cleared, iclass 39 cls_cnt 0 2006.174.00:10:13.93$vck44/va=3,5 2006.174.00:10:13.93#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.174.00:10:13.93#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.174.00:10:13.93#ibcon#ireg 11 cls_cnt 2 2006.174.00:10:13.93#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.174.00:10:13.99#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.174.00:10:13.99#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.174.00:10:13.99#ibcon#enter wrdev, iclass 3, count 2 2006.174.00:10:13.99#ibcon#first serial, iclass 3, count 2 2006.174.00:10:13.99#ibcon#enter sib2, iclass 3, count 2 2006.174.00:10:13.99#ibcon#flushed, iclass 3, count 2 2006.174.00:10:13.99#ibcon#about to write, iclass 3, count 2 2006.174.00:10:13.99#ibcon#wrote, iclass 3, count 2 2006.174.00:10:13.99#ibcon#about to read 3, iclass 3, count 2 2006.174.00:10:14.01#ibcon#read 3, iclass 3, count 2 2006.174.00:10:14.01#ibcon#about to read 4, iclass 3, count 2 2006.174.00:10:14.01#ibcon#read 4, iclass 3, count 2 2006.174.00:10:14.01#ibcon#about to read 5, iclass 3, count 2 2006.174.00:10:14.01#ibcon#read 5, iclass 3, count 2 2006.174.00:10:14.01#ibcon#about to read 6, iclass 3, count 2 2006.174.00:10:14.01#ibcon#read 6, iclass 3, count 2 2006.174.00:10:14.01#ibcon#end of sib2, iclass 3, count 2 2006.174.00:10:14.01#ibcon#*mode == 0, iclass 3, count 2 2006.174.00:10:14.01#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.174.00:10:14.01#ibcon#[25=AT03-05\r\n] 2006.174.00:10:14.01#ibcon#*before write, iclass 3, count 2 2006.174.00:10:14.01#ibcon#enter sib2, iclass 3, count 2 2006.174.00:10:14.01#ibcon#flushed, iclass 3, count 2 2006.174.00:10:14.01#ibcon#about to write, iclass 3, count 2 2006.174.00:10:14.01#ibcon#wrote, iclass 3, count 2 2006.174.00:10:14.01#ibcon#about to read 3, iclass 3, count 2 2006.174.00:10:14.04#ibcon#read 3, iclass 3, count 2 2006.174.00:10:14.04#ibcon#about to read 4, iclass 3, count 2 2006.174.00:10:14.04#ibcon#read 4, iclass 3, count 2 2006.174.00:10:14.04#ibcon#about to read 5, iclass 3, count 2 2006.174.00:10:14.04#ibcon#read 5, iclass 3, count 2 2006.174.00:10:14.04#ibcon#about to read 6, iclass 3, count 2 2006.174.00:10:14.04#ibcon#read 6, iclass 3, count 2 2006.174.00:10:14.04#ibcon#end of sib2, iclass 3, count 2 2006.174.00:10:14.04#ibcon#*after write, iclass 3, count 2 2006.174.00:10:14.04#ibcon#*before return 0, iclass 3, count 2 2006.174.00:10:14.04#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.174.00:10:14.04#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.174.00:10:14.04#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.174.00:10:14.04#ibcon#ireg 7 cls_cnt 0 2006.174.00:10:14.04#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.174.00:10:14.16#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.174.00:10:14.16#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.174.00:10:14.16#ibcon#enter wrdev, iclass 3, count 0 2006.174.00:10:14.16#ibcon#first serial, iclass 3, count 0 2006.174.00:10:14.16#ibcon#enter sib2, iclass 3, count 0 2006.174.00:10:14.16#ibcon#flushed, iclass 3, count 0 2006.174.00:10:14.16#ibcon#about to write, iclass 3, count 0 2006.174.00:10:14.16#ibcon#wrote, iclass 3, count 0 2006.174.00:10:14.16#ibcon#about to read 3, iclass 3, count 0 2006.174.00:10:14.18#ibcon#read 3, iclass 3, count 0 2006.174.00:10:14.18#ibcon#about to read 4, iclass 3, count 0 2006.174.00:10:14.18#ibcon#read 4, iclass 3, count 0 2006.174.00:10:14.18#ibcon#about to read 5, iclass 3, count 0 2006.174.00:10:14.18#ibcon#read 5, iclass 3, count 0 2006.174.00:10:14.18#ibcon#about to read 6, iclass 3, count 0 2006.174.00:10:14.18#ibcon#read 6, iclass 3, count 0 2006.174.00:10:14.18#ibcon#end of sib2, iclass 3, count 0 2006.174.00:10:14.18#ibcon#*mode == 0, iclass 3, count 0 2006.174.00:10:14.18#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.174.00:10:14.18#ibcon#[25=USB\r\n] 2006.174.00:10:14.18#ibcon#*before write, iclass 3, count 0 2006.174.00:10:14.18#ibcon#enter sib2, iclass 3, count 0 2006.174.00:10:14.18#ibcon#flushed, iclass 3, count 0 2006.174.00:10:14.18#ibcon#about to write, iclass 3, count 0 2006.174.00:10:14.18#ibcon#wrote, iclass 3, count 0 2006.174.00:10:14.18#ibcon#about to read 3, iclass 3, count 0 2006.174.00:10:14.21#ibcon#read 3, iclass 3, count 0 2006.174.00:10:14.21#ibcon#about to read 4, iclass 3, count 0 2006.174.00:10:14.21#ibcon#read 4, iclass 3, count 0 2006.174.00:10:14.21#ibcon#about to read 5, iclass 3, count 0 2006.174.00:10:14.21#ibcon#read 5, iclass 3, count 0 2006.174.00:10:14.21#ibcon#about to read 6, iclass 3, count 0 2006.174.00:10:14.21#ibcon#read 6, iclass 3, count 0 2006.174.00:10:14.21#ibcon#end of sib2, iclass 3, count 0 2006.174.00:10:14.21#ibcon#*after write, iclass 3, count 0 2006.174.00:10:14.21#ibcon#*before return 0, iclass 3, count 0 2006.174.00:10:14.21#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.174.00:10:14.21#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.174.00:10:14.21#ibcon#about to clear, iclass 3 cls_cnt 0 2006.174.00:10:14.21#ibcon#cleared, iclass 3 cls_cnt 0 2006.174.00:10:14.21$vck44/valo=4,624.99 2006.174.00:10:14.21#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.174.00:10:14.21#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.174.00:10:14.21#ibcon#ireg 17 cls_cnt 0 2006.174.00:10:14.21#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.174.00:10:14.21#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.174.00:10:14.21#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.174.00:10:14.21#ibcon#enter wrdev, iclass 5, count 0 2006.174.00:10:14.21#ibcon#first serial, iclass 5, count 0 2006.174.00:10:14.21#ibcon#enter sib2, iclass 5, count 0 2006.174.00:10:14.21#ibcon#flushed, iclass 5, count 0 2006.174.00:10:14.21#ibcon#about to write, iclass 5, count 0 2006.174.00:10:14.21#ibcon#wrote, iclass 5, count 0 2006.174.00:10:14.21#ibcon#about to read 3, iclass 5, count 0 2006.174.00:10:14.23#ibcon#read 3, iclass 5, count 0 2006.174.00:10:14.23#ibcon#about to read 4, iclass 5, count 0 2006.174.00:10:14.23#ibcon#read 4, iclass 5, count 0 2006.174.00:10:14.23#ibcon#about to read 5, iclass 5, count 0 2006.174.00:10:14.23#ibcon#read 5, iclass 5, count 0 2006.174.00:10:14.23#ibcon#about to read 6, iclass 5, count 0 2006.174.00:10:14.23#ibcon#read 6, iclass 5, count 0 2006.174.00:10:14.23#ibcon#end of sib2, iclass 5, count 0 2006.174.00:10:14.23#ibcon#*mode == 0, iclass 5, count 0 2006.174.00:10:14.23#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.174.00:10:14.23#ibcon#[26=FRQ=04,624.99\r\n] 2006.174.00:10:14.23#ibcon#*before write, iclass 5, count 0 2006.174.00:10:14.23#ibcon#enter sib2, iclass 5, count 0 2006.174.00:10:14.23#ibcon#flushed, iclass 5, count 0 2006.174.00:10:14.23#ibcon#about to write, iclass 5, count 0 2006.174.00:10:14.23#ibcon#wrote, iclass 5, count 0 2006.174.00:10:14.23#ibcon#about to read 3, iclass 5, count 0 2006.174.00:10:14.27#ibcon#read 3, iclass 5, count 0 2006.174.00:10:14.27#ibcon#about to read 4, iclass 5, count 0 2006.174.00:10:14.27#ibcon#read 4, iclass 5, count 0 2006.174.00:10:14.27#ibcon#about to read 5, iclass 5, count 0 2006.174.00:10:14.27#ibcon#read 5, iclass 5, count 0 2006.174.00:10:14.27#ibcon#about to read 6, iclass 5, count 0 2006.174.00:10:14.27#ibcon#read 6, iclass 5, count 0 2006.174.00:10:14.27#ibcon#end of sib2, iclass 5, count 0 2006.174.00:10:14.27#ibcon#*after write, iclass 5, count 0 2006.174.00:10:14.27#ibcon#*before return 0, iclass 5, count 0 2006.174.00:10:14.27#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.174.00:10:14.27#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.174.00:10:14.27#ibcon#about to clear, iclass 5 cls_cnt 0 2006.174.00:10:14.27#ibcon#cleared, iclass 5 cls_cnt 0 2006.174.00:10:14.27$vck44/va=4,6 2006.174.00:10:14.27#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.174.00:10:14.27#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.174.00:10:14.27#ibcon#ireg 11 cls_cnt 2 2006.174.00:10:14.27#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.174.00:10:14.33#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.174.00:10:14.33#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.174.00:10:14.33#ibcon#enter wrdev, iclass 7, count 2 2006.174.00:10:14.33#ibcon#first serial, iclass 7, count 2 2006.174.00:10:14.33#ibcon#enter sib2, iclass 7, count 2 2006.174.00:10:14.33#ibcon#flushed, iclass 7, count 2 2006.174.00:10:14.33#ibcon#about to write, iclass 7, count 2 2006.174.00:10:14.33#ibcon#wrote, iclass 7, count 2 2006.174.00:10:14.33#ibcon#about to read 3, iclass 7, count 2 2006.174.00:10:14.35#ibcon#read 3, iclass 7, count 2 2006.174.00:10:14.35#ibcon#about to read 4, iclass 7, count 2 2006.174.00:10:14.35#ibcon#read 4, iclass 7, count 2 2006.174.00:10:14.35#ibcon#about to read 5, iclass 7, count 2 2006.174.00:10:14.35#ibcon#read 5, iclass 7, count 2 2006.174.00:10:14.35#ibcon#about to read 6, iclass 7, count 2 2006.174.00:10:14.35#ibcon#read 6, iclass 7, count 2 2006.174.00:10:14.35#ibcon#end of sib2, iclass 7, count 2 2006.174.00:10:14.35#ibcon#*mode == 0, iclass 7, count 2 2006.174.00:10:14.35#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.174.00:10:14.35#ibcon#[25=AT04-06\r\n] 2006.174.00:10:14.35#ibcon#*before write, iclass 7, count 2 2006.174.00:10:14.35#ibcon#enter sib2, iclass 7, count 2 2006.174.00:10:14.35#ibcon#flushed, iclass 7, count 2 2006.174.00:10:14.35#ibcon#about to write, iclass 7, count 2 2006.174.00:10:14.35#ibcon#wrote, iclass 7, count 2 2006.174.00:10:14.35#ibcon#about to read 3, iclass 7, count 2 2006.174.00:10:14.38#ibcon#read 3, iclass 7, count 2 2006.174.00:10:14.38#ibcon#about to read 4, iclass 7, count 2 2006.174.00:10:14.38#ibcon#read 4, iclass 7, count 2 2006.174.00:10:14.38#ibcon#about to read 5, iclass 7, count 2 2006.174.00:10:14.38#ibcon#read 5, iclass 7, count 2 2006.174.00:10:14.38#ibcon#about to read 6, iclass 7, count 2 2006.174.00:10:14.38#ibcon#read 6, iclass 7, count 2 2006.174.00:10:14.38#ibcon#end of sib2, iclass 7, count 2 2006.174.00:10:14.38#ibcon#*after write, iclass 7, count 2 2006.174.00:10:14.38#ibcon#*before return 0, iclass 7, count 2 2006.174.00:10:14.38#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.174.00:10:14.38#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.174.00:10:14.38#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.174.00:10:14.38#ibcon#ireg 7 cls_cnt 0 2006.174.00:10:14.38#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.174.00:10:14.50#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.174.00:10:14.50#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.174.00:10:14.50#ibcon#enter wrdev, iclass 7, count 0 2006.174.00:10:14.50#ibcon#first serial, iclass 7, count 0 2006.174.00:10:14.50#ibcon#enter sib2, iclass 7, count 0 2006.174.00:10:14.50#ibcon#flushed, iclass 7, count 0 2006.174.00:10:14.50#ibcon#about to write, iclass 7, count 0 2006.174.00:10:14.50#ibcon#wrote, iclass 7, count 0 2006.174.00:10:14.50#ibcon#about to read 3, iclass 7, count 0 2006.174.00:10:14.52#ibcon#read 3, iclass 7, count 0 2006.174.00:10:14.52#ibcon#about to read 4, iclass 7, count 0 2006.174.00:10:14.52#ibcon#read 4, iclass 7, count 0 2006.174.00:10:14.52#ibcon#about to read 5, iclass 7, count 0 2006.174.00:10:14.52#ibcon#read 5, iclass 7, count 0 2006.174.00:10:14.52#ibcon#about to read 6, iclass 7, count 0 2006.174.00:10:14.52#ibcon#read 6, iclass 7, count 0 2006.174.00:10:14.52#ibcon#end of sib2, iclass 7, count 0 2006.174.00:10:14.52#ibcon#*mode == 0, iclass 7, count 0 2006.174.00:10:14.52#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.174.00:10:14.52#ibcon#[25=USB\r\n] 2006.174.00:10:14.52#ibcon#*before write, iclass 7, count 0 2006.174.00:10:14.52#ibcon#enter sib2, iclass 7, count 0 2006.174.00:10:14.52#ibcon#flushed, iclass 7, count 0 2006.174.00:10:14.52#ibcon#about to write, iclass 7, count 0 2006.174.00:10:14.52#ibcon#wrote, iclass 7, count 0 2006.174.00:10:14.52#ibcon#about to read 3, iclass 7, count 0 2006.174.00:10:14.55#ibcon#read 3, iclass 7, count 0 2006.174.00:10:14.55#ibcon#about to read 4, iclass 7, count 0 2006.174.00:10:14.55#ibcon#read 4, iclass 7, count 0 2006.174.00:10:14.55#ibcon#about to read 5, iclass 7, count 0 2006.174.00:10:14.55#ibcon#read 5, iclass 7, count 0 2006.174.00:10:14.55#ibcon#about to read 6, iclass 7, count 0 2006.174.00:10:14.55#ibcon#read 6, iclass 7, count 0 2006.174.00:10:14.55#ibcon#end of sib2, iclass 7, count 0 2006.174.00:10:14.55#ibcon#*after write, iclass 7, count 0 2006.174.00:10:14.55#ibcon#*before return 0, iclass 7, count 0 2006.174.00:10:14.55#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.174.00:10:14.55#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.174.00:10:14.55#ibcon#about to clear, iclass 7 cls_cnt 0 2006.174.00:10:14.55#ibcon#cleared, iclass 7 cls_cnt 0 2006.174.00:10:14.55$vck44/valo=5,734.99 2006.174.00:10:14.55#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.174.00:10:14.55#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.174.00:10:14.55#ibcon#ireg 17 cls_cnt 0 2006.174.00:10:14.55#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.174.00:10:14.55#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.174.00:10:14.55#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.174.00:10:14.55#ibcon#enter wrdev, iclass 11, count 0 2006.174.00:10:14.55#ibcon#first serial, iclass 11, count 0 2006.174.00:10:14.55#ibcon#enter sib2, iclass 11, count 0 2006.174.00:10:14.55#ibcon#flushed, iclass 11, count 0 2006.174.00:10:14.55#ibcon#about to write, iclass 11, count 0 2006.174.00:10:14.55#ibcon#wrote, iclass 11, count 0 2006.174.00:10:14.55#ibcon#about to read 3, iclass 11, count 0 2006.174.00:10:14.57#ibcon#read 3, iclass 11, count 0 2006.174.00:10:14.57#ibcon#about to read 4, iclass 11, count 0 2006.174.00:10:14.57#ibcon#read 4, iclass 11, count 0 2006.174.00:10:14.57#ibcon#about to read 5, iclass 11, count 0 2006.174.00:10:14.57#ibcon#read 5, iclass 11, count 0 2006.174.00:10:14.57#ibcon#about to read 6, iclass 11, count 0 2006.174.00:10:14.57#ibcon#read 6, iclass 11, count 0 2006.174.00:10:14.57#ibcon#end of sib2, iclass 11, count 0 2006.174.00:10:14.57#ibcon#*mode == 0, iclass 11, count 0 2006.174.00:10:14.57#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.174.00:10:14.57#ibcon#[26=FRQ=05,734.99\r\n] 2006.174.00:10:14.57#ibcon#*before write, iclass 11, count 0 2006.174.00:10:14.57#ibcon#enter sib2, iclass 11, count 0 2006.174.00:10:14.57#ibcon#flushed, iclass 11, count 0 2006.174.00:10:14.57#ibcon#about to write, iclass 11, count 0 2006.174.00:10:14.57#ibcon#wrote, iclass 11, count 0 2006.174.00:10:14.57#ibcon#about to read 3, iclass 11, count 0 2006.174.00:10:14.61#ibcon#read 3, iclass 11, count 0 2006.174.00:10:14.61#ibcon#about to read 4, iclass 11, count 0 2006.174.00:10:14.61#ibcon#read 4, iclass 11, count 0 2006.174.00:10:14.61#ibcon#about to read 5, iclass 11, count 0 2006.174.00:10:14.61#ibcon#read 5, iclass 11, count 0 2006.174.00:10:14.61#ibcon#about to read 6, iclass 11, count 0 2006.174.00:10:14.61#ibcon#read 6, iclass 11, count 0 2006.174.00:10:14.61#ibcon#end of sib2, iclass 11, count 0 2006.174.00:10:14.61#ibcon#*after write, iclass 11, count 0 2006.174.00:10:14.61#ibcon#*before return 0, iclass 11, count 0 2006.174.00:10:14.61#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.174.00:10:14.61#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.174.00:10:14.61#ibcon#about to clear, iclass 11 cls_cnt 0 2006.174.00:10:14.61#ibcon#cleared, iclass 11 cls_cnt 0 2006.174.00:10:14.61$vck44/va=5,4 2006.174.00:10:14.61#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.174.00:10:14.61#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.174.00:10:14.61#ibcon#ireg 11 cls_cnt 2 2006.174.00:10:14.61#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.174.00:10:14.67#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.174.00:10:14.67#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.174.00:10:14.67#ibcon#enter wrdev, iclass 13, count 2 2006.174.00:10:14.67#ibcon#first serial, iclass 13, count 2 2006.174.00:10:14.67#ibcon#enter sib2, iclass 13, count 2 2006.174.00:10:14.67#ibcon#flushed, iclass 13, count 2 2006.174.00:10:14.67#ibcon#about to write, iclass 13, count 2 2006.174.00:10:14.67#ibcon#wrote, iclass 13, count 2 2006.174.00:10:14.67#ibcon#about to read 3, iclass 13, count 2 2006.174.00:10:14.69#ibcon#read 3, iclass 13, count 2 2006.174.00:10:14.69#ibcon#about to read 4, iclass 13, count 2 2006.174.00:10:14.69#ibcon#read 4, iclass 13, count 2 2006.174.00:10:14.69#ibcon#about to read 5, iclass 13, count 2 2006.174.00:10:14.69#ibcon#read 5, iclass 13, count 2 2006.174.00:10:14.69#ibcon#about to read 6, iclass 13, count 2 2006.174.00:10:14.69#ibcon#read 6, iclass 13, count 2 2006.174.00:10:14.69#ibcon#end of sib2, iclass 13, count 2 2006.174.00:10:14.69#ibcon#*mode == 0, iclass 13, count 2 2006.174.00:10:14.69#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.174.00:10:14.69#ibcon#[25=AT05-04\r\n] 2006.174.00:10:14.69#ibcon#*before write, iclass 13, count 2 2006.174.00:10:14.69#ibcon#enter sib2, iclass 13, count 2 2006.174.00:10:14.69#ibcon#flushed, iclass 13, count 2 2006.174.00:10:14.69#ibcon#about to write, iclass 13, count 2 2006.174.00:10:14.69#ibcon#wrote, iclass 13, count 2 2006.174.00:10:14.69#ibcon#about to read 3, iclass 13, count 2 2006.174.00:10:14.72#ibcon#read 3, iclass 13, count 2 2006.174.00:10:14.72#ibcon#about to read 4, iclass 13, count 2 2006.174.00:10:14.72#ibcon#read 4, iclass 13, count 2 2006.174.00:10:14.72#ibcon#about to read 5, iclass 13, count 2 2006.174.00:10:14.72#ibcon#read 5, iclass 13, count 2 2006.174.00:10:14.72#ibcon#about to read 6, iclass 13, count 2 2006.174.00:10:14.72#ibcon#read 6, iclass 13, count 2 2006.174.00:10:14.72#ibcon#end of sib2, iclass 13, count 2 2006.174.00:10:14.72#ibcon#*after write, iclass 13, count 2 2006.174.00:10:14.72#ibcon#*before return 0, iclass 13, count 2 2006.174.00:10:14.72#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.174.00:10:14.72#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.174.00:10:14.72#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.174.00:10:14.72#ibcon#ireg 7 cls_cnt 0 2006.174.00:10:14.72#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.174.00:10:14.84#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.174.00:10:14.84#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.174.00:10:14.84#ibcon#enter wrdev, iclass 13, count 0 2006.174.00:10:14.84#ibcon#first serial, iclass 13, count 0 2006.174.00:10:14.84#ibcon#enter sib2, iclass 13, count 0 2006.174.00:10:14.84#ibcon#flushed, iclass 13, count 0 2006.174.00:10:14.84#ibcon#about to write, iclass 13, count 0 2006.174.00:10:14.84#ibcon#wrote, iclass 13, count 0 2006.174.00:10:14.84#ibcon#about to read 3, iclass 13, count 0 2006.174.00:10:14.86#ibcon#read 3, iclass 13, count 0 2006.174.00:10:14.86#ibcon#about to read 4, iclass 13, count 0 2006.174.00:10:14.86#ibcon#read 4, iclass 13, count 0 2006.174.00:10:14.86#ibcon#about to read 5, iclass 13, count 0 2006.174.00:10:14.86#ibcon#read 5, iclass 13, count 0 2006.174.00:10:14.86#ibcon#about to read 6, iclass 13, count 0 2006.174.00:10:14.86#ibcon#read 6, iclass 13, count 0 2006.174.00:10:14.86#ibcon#end of sib2, iclass 13, count 0 2006.174.00:10:14.86#ibcon#*mode == 0, iclass 13, count 0 2006.174.00:10:14.86#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.174.00:10:14.86#ibcon#[25=USB\r\n] 2006.174.00:10:14.86#ibcon#*before write, iclass 13, count 0 2006.174.00:10:14.86#ibcon#enter sib2, iclass 13, count 0 2006.174.00:10:14.86#ibcon#flushed, iclass 13, count 0 2006.174.00:10:14.86#ibcon#about to write, iclass 13, count 0 2006.174.00:10:14.86#ibcon#wrote, iclass 13, count 0 2006.174.00:10:14.86#ibcon#about to read 3, iclass 13, count 0 2006.174.00:10:14.89#ibcon#read 3, iclass 13, count 0 2006.174.00:10:14.89#ibcon#about to read 4, iclass 13, count 0 2006.174.00:10:14.89#ibcon#read 4, iclass 13, count 0 2006.174.00:10:14.89#ibcon#about to read 5, iclass 13, count 0 2006.174.00:10:14.89#ibcon#read 5, iclass 13, count 0 2006.174.00:10:14.89#ibcon#about to read 6, iclass 13, count 0 2006.174.00:10:14.89#ibcon#read 6, iclass 13, count 0 2006.174.00:10:14.89#ibcon#end of sib2, iclass 13, count 0 2006.174.00:10:14.89#ibcon#*after write, iclass 13, count 0 2006.174.00:10:14.89#ibcon#*before return 0, iclass 13, count 0 2006.174.00:10:14.89#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.174.00:10:14.89#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.174.00:10:14.89#ibcon#about to clear, iclass 13 cls_cnt 0 2006.174.00:10:14.89#ibcon#cleared, iclass 13 cls_cnt 0 2006.174.00:10:14.89$vck44/valo=6,814.99 2006.174.00:10:14.89#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.174.00:10:14.89#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.174.00:10:14.89#ibcon#ireg 17 cls_cnt 0 2006.174.00:10:14.89#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.174.00:10:14.89#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.174.00:10:14.89#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.174.00:10:14.89#ibcon#enter wrdev, iclass 15, count 0 2006.174.00:10:14.89#ibcon#first serial, iclass 15, count 0 2006.174.00:10:14.89#ibcon#enter sib2, iclass 15, count 0 2006.174.00:10:14.89#ibcon#flushed, iclass 15, count 0 2006.174.00:10:14.89#ibcon#about to write, iclass 15, count 0 2006.174.00:10:14.89#ibcon#wrote, iclass 15, count 0 2006.174.00:10:14.89#ibcon#about to read 3, iclass 15, count 0 2006.174.00:10:14.91#ibcon#read 3, iclass 15, count 0 2006.174.00:10:14.91#ibcon#about to read 4, iclass 15, count 0 2006.174.00:10:14.91#ibcon#read 4, iclass 15, count 0 2006.174.00:10:14.91#ibcon#about to read 5, iclass 15, count 0 2006.174.00:10:14.91#ibcon#read 5, iclass 15, count 0 2006.174.00:10:14.91#ibcon#about to read 6, iclass 15, count 0 2006.174.00:10:14.91#ibcon#read 6, iclass 15, count 0 2006.174.00:10:14.91#ibcon#end of sib2, iclass 15, count 0 2006.174.00:10:14.91#ibcon#*mode == 0, iclass 15, count 0 2006.174.00:10:14.91#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.174.00:10:14.91#ibcon#[26=FRQ=06,814.99\r\n] 2006.174.00:10:14.91#ibcon#*before write, iclass 15, count 0 2006.174.00:10:14.91#ibcon#enter sib2, iclass 15, count 0 2006.174.00:10:14.91#ibcon#flushed, iclass 15, count 0 2006.174.00:10:14.91#ibcon#about to write, iclass 15, count 0 2006.174.00:10:14.91#ibcon#wrote, iclass 15, count 0 2006.174.00:10:14.91#ibcon#about to read 3, iclass 15, count 0 2006.174.00:10:14.95#ibcon#read 3, iclass 15, count 0 2006.174.00:10:14.95#ibcon#about to read 4, iclass 15, count 0 2006.174.00:10:14.95#ibcon#read 4, iclass 15, count 0 2006.174.00:10:14.95#ibcon#about to read 5, iclass 15, count 0 2006.174.00:10:14.95#ibcon#read 5, iclass 15, count 0 2006.174.00:10:14.95#ibcon#about to read 6, iclass 15, count 0 2006.174.00:10:14.95#ibcon#read 6, iclass 15, count 0 2006.174.00:10:14.95#ibcon#end of sib2, iclass 15, count 0 2006.174.00:10:14.95#ibcon#*after write, iclass 15, count 0 2006.174.00:10:14.95#ibcon#*before return 0, iclass 15, count 0 2006.174.00:10:14.95#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.174.00:10:14.95#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.174.00:10:14.95#ibcon#about to clear, iclass 15 cls_cnt 0 2006.174.00:10:14.95#ibcon#cleared, iclass 15 cls_cnt 0 2006.174.00:10:14.95$vck44/va=6,3 2006.174.00:10:14.95#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.174.00:10:14.95#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.174.00:10:14.95#ibcon#ireg 11 cls_cnt 2 2006.174.00:10:14.95#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.174.00:10:15.01#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.174.00:10:15.01#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.174.00:10:15.01#ibcon#enter wrdev, iclass 17, count 2 2006.174.00:10:15.01#ibcon#first serial, iclass 17, count 2 2006.174.00:10:15.01#ibcon#enter sib2, iclass 17, count 2 2006.174.00:10:15.01#ibcon#flushed, iclass 17, count 2 2006.174.00:10:15.01#ibcon#about to write, iclass 17, count 2 2006.174.00:10:15.01#ibcon#wrote, iclass 17, count 2 2006.174.00:10:15.01#ibcon#about to read 3, iclass 17, count 2 2006.174.00:10:15.03#ibcon#read 3, iclass 17, count 2 2006.174.00:10:15.03#ibcon#about to read 4, iclass 17, count 2 2006.174.00:10:15.03#ibcon#read 4, iclass 17, count 2 2006.174.00:10:15.03#ibcon#about to read 5, iclass 17, count 2 2006.174.00:10:15.03#ibcon#read 5, iclass 17, count 2 2006.174.00:10:15.03#ibcon#about to read 6, iclass 17, count 2 2006.174.00:10:15.03#ibcon#read 6, iclass 17, count 2 2006.174.00:10:15.03#ibcon#end of sib2, iclass 17, count 2 2006.174.00:10:15.03#ibcon#*mode == 0, iclass 17, count 2 2006.174.00:10:15.03#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.174.00:10:15.03#ibcon#[25=AT06-03\r\n] 2006.174.00:10:15.03#ibcon#*before write, iclass 17, count 2 2006.174.00:10:15.03#ibcon#enter sib2, iclass 17, count 2 2006.174.00:10:15.03#ibcon#flushed, iclass 17, count 2 2006.174.00:10:15.03#ibcon#about to write, iclass 17, count 2 2006.174.00:10:15.03#ibcon#wrote, iclass 17, count 2 2006.174.00:10:15.03#ibcon#about to read 3, iclass 17, count 2 2006.174.00:10:15.06#ibcon#read 3, iclass 17, count 2 2006.174.00:10:15.06#ibcon#about to read 4, iclass 17, count 2 2006.174.00:10:15.06#ibcon#read 4, iclass 17, count 2 2006.174.00:10:15.06#ibcon#about to read 5, iclass 17, count 2 2006.174.00:10:15.06#ibcon#read 5, iclass 17, count 2 2006.174.00:10:15.06#ibcon#about to read 6, iclass 17, count 2 2006.174.00:10:15.06#ibcon#read 6, iclass 17, count 2 2006.174.00:10:15.06#ibcon#end of sib2, iclass 17, count 2 2006.174.00:10:15.06#ibcon#*after write, iclass 17, count 2 2006.174.00:10:15.06#ibcon#*before return 0, iclass 17, count 2 2006.174.00:10:15.06#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.174.00:10:15.06#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.174.00:10:15.06#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.174.00:10:15.06#ibcon#ireg 7 cls_cnt 0 2006.174.00:10:15.06#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.174.00:10:15.18#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.174.00:10:15.18#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.174.00:10:15.18#ibcon#enter wrdev, iclass 17, count 0 2006.174.00:10:15.18#ibcon#first serial, iclass 17, count 0 2006.174.00:10:15.18#ibcon#enter sib2, iclass 17, count 0 2006.174.00:10:15.18#ibcon#flushed, iclass 17, count 0 2006.174.00:10:15.18#ibcon#about to write, iclass 17, count 0 2006.174.00:10:15.18#ibcon#wrote, iclass 17, count 0 2006.174.00:10:15.18#ibcon#about to read 3, iclass 17, count 0 2006.174.00:10:15.20#ibcon#read 3, iclass 17, count 0 2006.174.00:10:15.20#ibcon#about to read 4, iclass 17, count 0 2006.174.00:10:15.20#ibcon#read 4, iclass 17, count 0 2006.174.00:10:15.20#ibcon#about to read 5, iclass 17, count 0 2006.174.00:10:15.20#ibcon#read 5, iclass 17, count 0 2006.174.00:10:15.20#ibcon#about to read 6, iclass 17, count 0 2006.174.00:10:15.20#ibcon#read 6, iclass 17, count 0 2006.174.00:10:15.20#ibcon#end of sib2, iclass 17, count 0 2006.174.00:10:15.20#ibcon#*mode == 0, iclass 17, count 0 2006.174.00:10:15.20#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.174.00:10:15.20#ibcon#[25=USB\r\n] 2006.174.00:10:15.20#ibcon#*before write, iclass 17, count 0 2006.174.00:10:15.20#ibcon#enter sib2, iclass 17, count 0 2006.174.00:10:15.20#ibcon#flushed, iclass 17, count 0 2006.174.00:10:15.20#ibcon#about to write, iclass 17, count 0 2006.174.00:10:15.20#ibcon#wrote, iclass 17, count 0 2006.174.00:10:15.20#ibcon#about to read 3, iclass 17, count 0 2006.174.00:10:15.23#ibcon#read 3, iclass 17, count 0 2006.174.00:10:15.23#ibcon#about to read 4, iclass 17, count 0 2006.174.00:10:15.23#ibcon#read 4, iclass 17, count 0 2006.174.00:10:15.23#ibcon#about to read 5, iclass 17, count 0 2006.174.00:10:15.23#ibcon#read 5, iclass 17, count 0 2006.174.00:10:15.23#ibcon#about to read 6, iclass 17, count 0 2006.174.00:10:15.23#ibcon#read 6, iclass 17, count 0 2006.174.00:10:15.23#ibcon#end of sib2, iclass 17, count 0 2006.174.00:10:15.23#ibcon#*after write, iclass 17, count 0 2006.174.00:10:15.23#ibcon#*before return 0, iclass 17, count 0 2006.174.00:10:15.23#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.174.00:10:15.23#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.174.00:10:15.23#ibcon#about to clear, iclass 17 cls_cnt 0 2006.174.00:10:15.23#ibcon#cleared, iclass 17 cls_cnt 0 2006.174.00:10:15.23$vck44/valo=7,864.99 2006.174.00:10:15.23#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.174.00:10:15.23#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.174.00:10:15.23#ibcon#ireg 17 cls_cnt 0 2006.174.00:10:15.23#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.174.00:10:15.23#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.174.00:10:15.23#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.174.00:10:15.23#ibcon#enter wrdev, iclass 19, count 0 2006.174.00:10:15.23#ibcon#first serial, iclass 19, count 0 2006.174.00:10:15.23#ibcon#enter sib2, iclass 19, count 0 2006.174.00:10:15.23#ibcon#flushed, iclass 19, count 0 2006.174.00:10:15.23#ibcon#about to write, iclass 19, count 0 2006.174.00:10:15.23#ibcon#wrote, iclass 19, count 0 2006.174.00:10:15.23#ibcon#about to read 3, iclass 19, count 0 2006.174.00:10:15.25#ibcon#read 3, iclass 19, count 0 2006.174.00:10:15.25#ibcon#about to read 4, iclass 19, count 0 2006.174.00:10:15.25#ibcon#read 4, iclass 19, count 0 2006.174.00:10:15.25#ibcon#about to read 5, iclass 19, count 0 2006.174.00:10:15.25#ibcon#read 5, iclass 19, count 0 2006.174.00:10:15.25#ibcon#about to read 6, iclass 19, count 0 2006.174.00:10:15.25#ibcon#read 6, iclass 19, count 0 2006.174.00:10:15.25#ibcon#end of sib2, iclass 19, count 0 2006.174.00:10:15.25#ibcon#*mode == 0, iclass 19, count 0 2006.174.00:10:15.25#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.174.00:10:15.25#ibcon#[26=FRQ=07,864.99\r\n] 2006.174.00:10:15.25#ibcon#*before write, iclass 19, count 0 2006.174.00:10:15.25#ibcon#enter sib2, iclass 19, count 0 2006.174.00:10:15.25#ibcon#flushed, iclass 19, count 0 2006.174.00:10:15.25#ibcon#about to write, iclass 19, count 0 2006.174.00:10:15.25#ibcon#wrote, iclass 19, count 0 2006.174.00:10:15.25#ibcon#about to read 3, iclass 19, count 0 2006.174.00:10:15.29#ibcon#read 3, iclass 19, count 0 2006.174.00:10:15.29#ibcon#about to read 4, iclass 19, count 0 2006.174.00:10:15.29#ibcon#read 4, iclass 19, count 0 2006.174.00:10:15.29#ibcon#about to read 5, iclass 19, count 0 2006.174.00:10:15.29#ibcon#read 5, iclass 19, count 0 2006.174.00:10:15.29#ibcon#about to read 6, iclass 19, count 0 2006.174.00:10:15.29#ibcon#read 6, iclass 19, count 0 2006.174.00:10:15.29#ibcon#end of sib2, iclass 19, count 0 2006.174.00:10:15.29#ibcon#*after write, iclass 19, count 0 2006.174.00:10:15.29#ibcon#*before return 0, iclass 19, count 0 2006.174.00:10:15.29#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.174.00:10:15.29#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.174.00:10:15.29#ibcon#about to clear, iclass 19 cls_cnt 0 2006.174.00:10:15.29#ibcon#cleared, iclass 19 cls_cnt 0 2006.174.00:10:15.29$vck44/va=7,4 2006.174.00:10:15.29#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.174.00:10:15.29#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.174.00:10:15.29#ibcon#ireg 11 cls_cnt 2 2006.174.00:10:15.29#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.174.00:10:15.35#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.174.00:10:15.35#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.174.00:10:15.35#ibcon#enter wrdev, iclass 21, count 2 2006.174.00:10:15.35#ibcon#first serial, iclass 21, count 2 2006.174.00:10:15.35#ibcon#enter sib2, iclass 21, count 2 2006.174.00:10:15.35#ibcon#flushed, iclass 21, count 2 2006.174.00:10:15.35#ibcon#about to write, iclass 21, count 2 2006.174.00:10:15.35#ibcon#wrote, iclass 21, count 2 2006.174.00:10:15.35#ibcon#about to read 3, iclass 21, count 2 2006.174.00:10:15.37#ibcon#read 3, iclass 21, count 2 2006.174.00:10:15.37#ibcon#about to read 4, iclass 21, count 2 2006.174.00:10:15.37#ibcon#read 4, iclass 21, count 2 2006.174.00:10:15.37#ibcon#about to read 5, iclass 21, count 2 2006.174.00:10:15.37#ibcon#read 5, iclass 21, count 2 2006.174.00:10:15.37#ibcon#about to read 6, iclass 21, count 2 2006.174.00:10:15.37#ibcon#read 6, iclass 21, count 2 2006.174.00:10:15.37#ibcon#end of sib2, iclass 21, count 2 2006.174.00:10:15.37#ibcon#*mode == 0, iclass 21, count 2 2006.174.00:10:15.37#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.174.00:10:15.37#ibcon#[25=AT07-04\r\n] 2006.174.00:10:15.37#ibcon#*before write, iclass 21, count 2 2006.174.00:10:15.37#ibcon#enter sib2, iclass 21, count 2 2006.174.00:10:15.37#ibcon#flushed, iclass 21, count 2 2006.174.00:10:15.37#ibcon#about to write, iclass 21, count 2 2006.174.00:10:15.37#ibcon#wrote, iclass 21, count 2 2006.174.00:10:15.37#ibcon#about to read 3, iclass 21, count 2 2006.174.00:10:15.40#ibcon#read 3, iclass 21, count 2 2006.174.00:10:15.40#ibcon#about to read 4, iclass 21, count 2 2006.174.00:10:15.40#ibcon#read 4, iclass 21, count 2 2006.174.00:10:15.40#ibcon#about to read 5, iclass 21, count 2 2006.174.00:10:15.40#ibcon#read 5, iclass 21, count 2 2006.174.00:10:15.40#ibcon#about to read 6, iclass 21, count 2 2006.174.00:10:15.40#ibcon#read 6, iclass 21, count 2 2006.174.00:10:15.40#ibcon#end of sib2, iclass 21, count 2 2006.174.00:10:15.40#ibcon#*after write, iclass 21, count 2 2006.174.00:10:15.40#ibcon#*before return 0, iclass 21, count 2 2006.174.00:10:15.40#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.174.00:10:15.40#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.174.00:10:15.40#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.174.00:10:15.40#ibcon#ireg 7 cls_cnt 0 2006.174.00:10:15.40#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.174.00:10:15.52#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.174.00:10:15.52#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.174.00:10:15.52#ibcon#enter wrdev, iclass 21, count 0 2006.174.00:10:15.52#ibcon#first serial, iclass 21, count 0 2006.174.00:10:15.52#ibcon#enter sib2, iclass 21, count 0 2006.174.00:10:15.52#ibcon#flushed, iclass 21, count 0 2006.174.00:10:15.52#ibcon#about to write, iclass 21, count 0 2006.174.00:10:15.52#ibcon#wrote, iclass 21, count 0 2006.174.00:10:15.52#ibcon#about to read 3, iclass 21, count 0 2006.174.00:10:15.54#ibcon#read 3, iclass 21, count 0 2006.174.00:10:15.54#ibcon#about to read 4, iclass 21, count 0 2006.174.00:10:15.54#ibcon#read 4, iclass 21, count 0 2006.174.00:10:15.54#ibcon#about to read 5, iclass 21, count 0 2006.174.00:10:15.54#ibcon#read 5, iclass 21, count 0 2006.174.00:10:15.54#ibcon#about to read 6, iclass 21, count 0 2006.174.00:10:15.54#ibcon#read 6, iclass 21, count 0 2006.174.00:10:15.54#ibcon#end of sib2, iclass 21, count 0 2006.174.00:10:15.54#ibcon#*mode == 0, iclass 21, count 0 2006.174.00:10:15.54#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.174.00:10:15.54#ibcon#[25=USB\r\n] 2006.174.00:10:15.54#ibcon#*before write, iclass 21, count 0 2006.174.00:10:15.54#ibcon#enter sib2, iclass 21, count 0 2006.174.00:10:15.54#ibcon#flushed, iclass 21, count 0 2006.174.00:10:15.54#ibcon#about to write, iclass 21, count 0 2006.174.00:10:15.54#ibcon#wrote, iclass 21, count 0 2006.174.00:10:15.54#ibcon#about to read 3, iclass 21, count 0 2006.174.00:10:15.57#ibcon#read 3, iclass 21, count 0 2006.174.00:10:15.57#ibcon#about to read 4, iclass 21, count 0 2006.174.00:10:15.57#ibcon#read 4, iclass 21, count 0 2006.174.00:10:15.57#ibcon#about to read 5, iclass 21, count 0 2006.174.00:10:15.57#ibcon#read 5, iclass 21, count 0 2006.174.00:10:15.57#ibcon#about to read 6, iclass 21, count 0 2006.174.00:10:15.57#ibcon#read 6, iclass 21, count 0 2006.174.00:10:15.57#ibcon#end of sib2, iclass 21, count 0 2006.174.00:10:15.57#ibcon#*after write, iclass 21, count 0 2006.174.00:10:15.57#ibcon#*before return 0, iclass 21, count 0 2006.174.00:10:15.57#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.174.00:10:15.57#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.174.00:10:15.57#ibcon#about to clear, iclass 21 cls_cnt 0 2006.174.00:10:15.57#ibcon#cleared, iclass 21 cls_cnt 0 2006.174.00:10:15.57$vck44/valo=8,884.99 2006.174.00:10:15.57#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.174.00:10:15.57#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.174.00:10:15.57#ibcon#ireg 17 cls_cnt 0 2006.174.00:10:15.57#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.174.00:10:15.57#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.174.00:10:15.57#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.174.00:10:15.57#ibcon#enter wrdev, iclass 23, count 0 2006.174.00:10:15.57#ibcon#first serial, iclass 23, count 0 2006.174.00:10:15.57#ibcon#enter sib2, iclass 23, count 0 2006.174.00:10:15.57#ibcon#flushed, iclass 23, count 0 2006.174.00:10:15.57#ibcon#about to write, iclass 23, count 0 2006.174.00:10:15.57#ibcon#wrote, iclass 23, count 0 2006.174.00:10:15.57#ibcon#about to read 3, iclass 23, count 0 2006.174.00:10:15.59#ibcon#read 3, iclass 23, count 0 2006.174.00:10:15.59#ibcon#about to read 4, iclass 23, count 0 2006.174.00:10:15.59#ibcon#read 4, iclass 23, count 0 2006.174.00:10:15.59#ibcon#about to read 5, iclass 23, count 0 2006.174.00:10:15.59#ibcon#read 5, iclass 23, count 0 2006.174.00:10:15.59#ibcon#about to read 6, iclass 23, count 0 2006.174.00:10:15.59#ibcon#read 6, iclass 23, count 0 2006.174.00:10:15.59#ibcon#end of sib2, iclass 23, count 0 2006.174.00:10:15.59#ibcon#*mode == 0, iclass 23, count 0 2006.174.00:10:15.59#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.174.00:10:15.59#ibcon#[26=FRQ=08,884.99\r\n] 2006.174.00:10:15.59#ibcon#*before write, iclass 23, count 0 2006.174.00:10:15.59#ibcon#enter sib2, iclass 23, count 0 2006.174.00:10:15.59#ibcon#flushed, iclass 23, count 0 2006.174.00:10:15.59#ibcon#about to write, iclass 23, count 0 2006.174.00:10:15.59#ibcon#wrote, iclass 23, count 0 2006.174.00:10:15.59#ibcon#about to read 3, iclass 23, count 0 2006.174.00:10:15.63#ibcon#read 3, iclass 23, count 0 2006.174.00:10:15.63#ibcon#about to read 4, iclass 23, count 0 2006.174.00:10:15.63#ibcon#read 4, iclass 23, count 0 2006.174.00:10:15.63#ibcon#about to read 5, iclass 23, count 0 2006.174.00:10:15.63#ibcon#read 5, iclass 23, count 0 2006.174.00:10:15.63#ibcon#about to read 6, iclass 23, count 0 2006.174.00:10:15.63#ibcon#read 6, iclass 23, count 0 2006.174.00:10:15.63#ibcon#end of sib2, iclass 23, count 0 2006.174.00:10:15.63#ibcon#*after write, iclass 23, count 0 2006.174.00:10:15.63#ibcon#*before return 0, iclass 23, count 0 2006.174.00:10:15.63#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.174.00:10:15.63#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.174.00:10:15.63#ibcon#about to clear, iclass 23 cls_cnt 0 2006.174.00:10:15.63#ibcon#cleared, iclass 23 cls_cnt 0 2006.174.00:10:15.63$vck44/va=8,4 2006.174.00:10:15.63#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.174.00:10:15.63#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.174.00:10:15.63#ibcon#ireg 11 cls_cnt 2 2006.174.00:10:15.63#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.174.00:10:15.69#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.174.00:10:15.69#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.174.00:10:15.69#ibcon#enter wrdev, iclass 25, count 2 2006.174.00:10:15.69#ibcon#first serial, iclass 25, count 2 2006.174.00:10:15.69#ibcon#enter sib2, iclass 25, count 2 2006.174.00:10:15.69#ibcon#flushed, iclass 25, count 2 2006.174.00:10:15.69#ibcon#about to write, iclass 25, count 2 2006.174.00:10:15.69#ibcon#wrote, iclass 25, count 2 2006.174.00:10:15.69#ibcon#about to read 3, iclass 25, count 2 2006.174.00:10:15.71#ibcon#read 3, iclass 25, count 2 2006.174.00:10:15.71#ibcon#about to read 4, iclass 25, count 2 2006.174.00:10:15.71#ibcon#read 4, iclass 25, count 2 2006.174.00:10:15.71#ibcon#about to read 5, iclass 25, count 2 2006.174.00:10:15.71#ibcon#read 5, iclass 25, count 2 2006.174.00:10:15.71#ibcon#about to read 6, iclass 25, count 2 2006.174.00:10:15.71#ibcon#read 6, iclass 25, count 2 2006.174.00:10:15.71#ibcon#end of sib2, iclass 25, count 2 2006.174.00:10:15.71#ibcon#*mode == 0, iclass 25, count 2 2006.174.00:10:15.71#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.174.00:10:15.71#ibcon#[25=AT08-04\r\n] 2006.174.00:10:15.71#ibcon#*before write, iclass 25, count 2 2006.174.00:10:15.71#ibcon#enter sib2, iclass 25, count 2 2006.174.00:10:15.71#ibcon#flushed, iclass 25, count 2 2006.174.00:10:15.71#ibcon#about to write, iclass 25, count 2 2006.174.00:10:15.71#ibcon#wrote, iclass 25, count 2 2006.174.00:10:15.71#ibcon#about to read 3, iclass 25, count 2 2006.174.00:10:15.74#ibcon#read 3, iclass 25, count 2 2006.174.00:10:15.74#ibcon#about to read 4, iclass 25, count 2 2006.174.00:10:15.74#ibcon#read 4, iclass 25, count 2 2006.174.00:10:15.74#ibcon#about to read 5, iclass 25, count 2 2006.174.00:10:15.74#ibcon#read 5, iclass 25, count 2 2006.174.00:10:15.74#ibcon#about to read 6, iclass 25, count 2 2006.174.00:10:15.74#ibcon#read 6, iclass 25, count 2 2006.174.00:10:15.74#ibcon#end of sib2, iclass 25, count 2 2006.174.00:10:15.74#ibcon#*after write, iclass 25, count 2 2006.174.00:10:15.74#ibcon#*before return 0, iclass 25, count 2 2006.174.00:10:15.74#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.174.00:10:15.74#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.174.00:10:15.74#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.174.00:10:15.74#ibcon#ireg 7 cls_cnt 0 2006.174.00:10:15.74#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.174.00:10:15.86#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.174.00:10:15.86#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.174.00:10:15.86#ibcon#enter wrdev, iclass 25, count 0 2006.174.00:10:15.86#ibcon#first serial, iclass 25, count 0 2006.174.00:10:15.86#ibcon#enter sib2, iclass 25, count 0 2006.174.00:10:15.86#ibcon#flushed, iclass 25, count 0 2006.174.00:10:15.86#ibcon#about to write, iclass 25, count 0 2006.174.00:10:15.86#ibcon#wrote, iclass 25, count 0 2006.174.00:10:15.86#ibcon#about to read 3, iclass 25, count 0 2006.174.00:10:15.88#ibcon#read 3, iclass 25, count 0 2006.174.00:10:15.88#ibcon#about to read 4, iclass 25, count 0 2006.174.00:10:15.88#ibcon#read 4, iclass 25, count 0 2006.174.00:10:15.88#ibcon#about to read 5, iclass 25, count 0 2006.174.00:10:15.88#ibcon#read 5, iclass 25, count 0 2006.174.00:10:15.88#ibcon#about to read 6, iclass 25, count 0 2006.174.00:10:15.88#ibcon#read 6, iclass 25, count 0 2006.174.00:10:15.88#ibcon#end of sib2, iclass 25, count 0 2006.174.00:10:15.88#ibcon#*mode == 0, iclass 25, count 0 2006.174.00:10:15.88#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.174.00:10:15.88#ibcon#[25=USB\r\n] 2006.174.00:10:15.88#ibcon#*before write, iclass 25, count 0 2006.174.00:10:15.88#ibcon#enter sib2, iclass 25, count 0 2006.174.00:10:15.88#ibcon#flushed, iclass 25, count 0 2006.174.00:10:15.88#ibcon#about to write, iclass 25, count 0 2006.174.00:10:15.88#ibcon#wrote, iclass 25, count 0 2006.174.00:10:15.88#ibcon#about to read 3, iclass 25, count 0 2006.174.00:10:15.91#ibcon#read 3, iclass 25, count 0 2006.174.00:10:15.91#ibcon#about to read 4, iclass 25, count 0 2006.174.00:10:15.91#ibcon#read 4, iclass 25, count 0 2006.174.00:10:15.91#ibcon#about to read 5, iclass 25, count 0 2006.174.00:10:15.91#ibcon#read 5, iclass 25, count 0 2006.174.00:10:15.91#ibcon#about to read 6, iclass 25, count 0 2006.174.00:10:15.91#ibcon#read 6, iclass 25, count 0 2006.174.00:10:15.91#ibcon#end of sib2, iclass 25, count 0 2006.174.00:10:15.91#ibcon#*after write, iclass 25, count 0 2006.174.00:10:15.91#ibcon#*before return 0, iclass 25, count 0 2006.174.00:10:15.91#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.174.00:10:15.91#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.174.00:10:15.91#ibcon#about to clear, iclass 25 cls_cnt 0 2006.174.00:10:15.91#ibcon#cleared, iclass 25 cls_cnt 0 2006.174.00:10:15.91$vck44/vblo=1,629.99 2006.174.00:10:15.91#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.174.00:10:15.91#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.174.00:10:15.91#ibcon#ireg 17 cls_cnt 0 2006.174.00:10:15.91#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.174.00:10:15.91#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.174.00:10:15.91#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.174.00:10:15.91#ibcon#enter wrdev, iclass 27, count 0 2006.174.00:10:15.91#ibcon#first serial, iclass 27, count 0 2006.174.00:10:15.91#ibcon#enter sib2, iclass 27, count 0 2006.174.00:10:15.91#ibcon#flushed, iclass 27, count 0 2006.174.00:10:15.91#ibcon#about to write, iclass 27, count 0 2006.174.00:10:15.91#ibcon#wrote, iclass 27, count 0 2006.174.00:10:15.91#ibcon#about to read 3, iclass 27, count 0 2006.174.00:10:15.93#ibcon#read 3, iclass 27, count 0 2006.174.00:10:15.93#ibcon#about to read 4, iclass 27, count 0 2006.174.00:10:15.93#ibcon#read 4, iclass 27, count 0 2006.174.00:10:15.93#ibcon#about to read 5, iclass 27, count 0 2006.174.00:10:15.93#ibcon#read 5, iclass 27, count 0 2006.174.00:10:15.93#ibcon#about to read 6, iclass 27, count 0 2006.174.00:10:15.93#ibcon#read 6, iclass 27, count 0 2006.174.00:10:15.93#ibcon#end of sib2, iclass 27, count 0 2006.174.00:10:15.93#ibcon#*mode == 0, iclass 27, count 0 2006.174.00:10:15.93#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.174.00:10:15.93#ibcon#[28=FRQ=01,629.99\r\n] 2006.174.00:10:15.93#ibcon#*before write, iclass 27, count 0 2006.174.00:10:15.93#ibcon#enter sib2, iclass 27, count 0 2006.174.00:10:15.93#ibcon#flushed, iclass 27, count 0 2006.174.00:10:15.93#ibcon#about to write, iclass 27, count 0 2006.174.00:10:15.93#ibcon#wrote, iclass 27, count 0 2006.174.00:10:15.93#ibcon#about to read 3, iclass 27, count 0 2006.174.00:10:15.97#ibcon#read 3, iclass 27, count 0 2006.174.00:10:15.97#ibcon#about to read 4, iclass 27, count 0 2006.174.00:10:15.97#ibcon#read 4, iclass 27, count 0 2006.174.00:10:15.97#ibcon#about to read 5, iclass 27, count 0 2006.174.00:10:15.97#ibcon#read 5, iclass 27, count 0 2006.174.00:10:15.97#ibcon#about to read 6, iclass 27, count 0 2006.174.00:10:15.97#ibcon#read 6, iclass 27, count 0 2006.174.00:10:15.97#ibcon#end of sib2, iclass 27, count 0 2006.174.00:10:15.97#ibcon#*after write, iclass 27, count 0 2006.174.00:10:15.97#ibcon#*before return 0, iclass 27, count 0 2006.174.00:10:15.97#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.174.00:10:15.97#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.174.00:10:15.97#ibcon#about to clear, iclass 27 cls_cnt 0 2006.174.00:10:15.97#ibcon#cleared, iclass 27 cls_cnt 0 2006.174.00:10:15.97$vck44/vb=1,4 2006.174.00:10:15.97#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.174.00:10:15.97#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.174.00:10:15.97#ibcon#ireg 11 cls_cnt 2 2006.174.00:10:15.97#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.174.00:10:15.97#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.174.00:10:15.97#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.174.00:10:15.97#ibcon#enter wrdev, iclass 29, count 2 2006.174.00:10:15.97#ibcon#first serial, iclass 29, count 2 2006.174.00:10:15.97#ibcon#enter sib2, iclass 29, count 2 2006.174.00:10:15.97#ibcon#flushed, iclass 29, count 2 2006.174.00:10:15.97#ibcon#about to write, iclass 29, count 2 2006.174.00:10:15.97#ibcon#wrote, iclass 29, count 2 2006.174.00:10:15.97#ibcon#about to read 3, iclass 29, count 2 2006.174.00:10:15.99#ibcon#read 3, iclass 29, count 2 2006.174.00:10:15.99#ibcon#about to read 4, iclass 29, count 2 2006.174.00:10:15.99#ibcon#read 4, iclass 29, count 2 2006.174.00:10:15.99#ibcon#about to read 5, iclass 29, count 2 2006.174.00:10:15.99#ibcon#read 5, iclass 29, count 2 2006.174.00:10:15.99#ibcon#about to read 6, iclass 29, count 2 2006.174.00:10:15.99#ibcon#read 6, iclass 29, count 2 2006.174.00:10:15.99#ibcon#end of sib2, iclass 29, count 2 2006.174.00:10:15.99#ibcon#*mode == 0, iclass 29, count 2 2006.174.00:10:15.99#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.174.00:10:15.99#ibcon#[27=AT01-04\r\n] 2006.174.00:10:15.99#ibcon#*before write, iclass 29, count 2 2006.174.00:10:15.99#ibcon#enter sib2, iclass 29, count 2 2006.174.00:10:15.99#ibcon#flushed, iclass 29, count 2 2006.174.00:10:15.99#ibcon#about to write, iclass 29, count 2 2006.174.00:10:15.99#ibcon#wrote, iclass 29, count 2 2006.174.00:10:15.99#ibcon#about to read 3, iclass 29, count 2 2006.174.00:10:16.02#ibcon#read 3, iclass 29, count 2 2006.174.00:10:16.02#ibcon#about to read 4, iclass 29, count 2 2006.174.00:10:16.02#ibcon#read 4, iclass 29, count 2 2006.174.00:10:16.02#ibcon#about to read 5, iclass 29, count 2 2006.174.00:10:16.02#ibcon#read 5, iclass 29, count 2 2006.174.00:10:16.02#ibcon#about to read 6, iclass 29, count 2 2006.174.00:10:16.02#ibcon#read 6, iclass 29, count 2 2006.174.00:10:16.02#ibcon#end of sib2, iclass 29, count 2 2006.174.00:10:16.02#ibcon#*after write, iclass 29, count 2 2006.174.00:10:16.02#ibcon#*before return 0, iclass 29, count 2 2006.174.00:10:16.02#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.174.00:10:16.02#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.174.00:10:16.02#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.174.00:10:16.02#ibcon#ireg 7 cls_cnt 0 2006.174.00:10:16.02#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.174.00:10:16.14#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.174.00:10:16.14#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.174.00:10:16.14#ibcon#enter wrdev, iclass 29, count 0 2006.174.00:10:16.14#ibcon#first serial, iclass 29, count 0 2006.174.00:10:16.14#ibcon#enter sib2, iclass 29, count 0 2006.174.00:10:16.14#ibcon#flushed, iclass 29, count 0 2006.174.00:10:16.14#ibcon#about to write, iclass 29, count 0 2006.174.00:10:16.14#ibcon#wrote, iclass 29, count 0 2006.174.00:10:16.14#ibcon#about to read 3, iclass 29, count 0 2006.174.00:10:16.16#ibcon#read 3, iclass 29, count 0 2006.174.00:10:16.16#ibcon#about to read 4, iclass 29, count 0 2006.174.00:10:16.16#ibcon#read 4, iclass 29, count 0 2006.174.00:10:16.16#ibcon#about to read 5, iclass 29, count 0 2006.174.00:10:16.16#ibcon#read 5, iclass 29, count 0 2006.174.00:10:16.16#ibcon#about to read 6, iclass 29, count 0 2006.174.00:10:16.16#ibcon#read 6, iclass 29, count 0 2006.174.00:10:16.16#ibcon#end of sib2, iclass 29, count 0 2006.174.00:10:16.16#ibcon#*mode == 0, iclass 29, count 0 2006.174.00:10:16.16#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.174.00:10:16.16#ibcon#[27=USB\r\n] 2006.174.00:10:16.16#ibcon#*before write, iclass 29, count 0 2006.174.00:10:16.16#ibcon#enter sib2, iclass 29, count 0 2006.174.00:10:16.16#ibcon#flushed, iclass 29, count 0 2006.174.00:10:16.16#ibcon#about to write, iclass 29, count 0 2006.174.00:10:16.16#ibcon#wrote, iclass 29, count 0 2006.174.00:10:16.16#ibcon#about to read 3, iclass 29, count 0 2006.174.00:10:16.19#ibcon#read 3, iclass 29, count 0 2006.174.00:10:16.19#ibcon#about to read 4, iclass 29, count 0 2006.174.00:10:16.19#ibcon#read 4, iclass 29, count 0 2006.174.00:10:16.19#ibcon#about to read 5, iclass 29, count 0 2006.174.00:10:16.19#ibcon#read 5, iclass 29, count 0 2006.174.00:10:16.19#ibcon#about to read 6, iclass 29, count 0 2006.174.00:10:16.19#ibcon#read 6, iclass 29, count 0 2006.174.00:10:16.19#ibcon#end of sib2, iclass 29, count 0 2006.174.00:10:16.19#ibcon#*after write, iclass 29, count 0 2006.174.00:10:16.19#ibcon#*before return 0, iclass 29, count 0 2006.174.00:10:16.19#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.174.00:10:16.19#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.174.00:10:16.19#ibcon#about to clear, iclass 29 cls_cnt 0 2006.174.00:10:16.19#ibcon#cleared, iclass 29 cls_cnt 0 2006.174.00:10:16.19$vck44/vblo=2,634.99 2006.174.00:10:16.19#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.174.00:10:16.19#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.174.00:10:16.19#ibcon#ireg 17 cls_cnt 0 2006.174.00:10:16.19#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.174.00:10:16.19#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.174.00:10:16.19#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.174.00:10:16.19#ibcon#enter wrdev, iclass 31, count 0 2006.174.00:10:16.19#ibcon#first serial, iclass 31, count 0 2006.174.00:10:16.19#ibcon#enter sib2, iclass 31, count 0 2006.174.00:10:16.19#ibcon#flushed, iclass 31, count 0 2006.174.00:10:16.19#ibcon#about to write, iclass 31, count 0 2006.174.00:10:16.19#ibcon#wrote, iclass 31, count 0 2006.174.00:10:16.19#ibcon#about to read 3, iclass 31, count 0 2006.174.00:10:16.21#ibcon#read 3, iclass 31, count 0 2006.174.00:10:16.21#ibcon#about to read 4, iclass 31, count 0 2006.174.00:10:16.21#ibcon#read 4, iclass 31, count 0 2006.174.00:10:16.21#ibcon#about to read 5, iclass 31, count 0 2006.174.00:10:16.21#ibcon#read 5, iclass 31, count 0 2006.174.00:10:16.21#ibcon#about to read 6, iclass 31, count 0 2006.174.00:10:16.21#ibcon#read 6, iclass 31, count 0 2006.174.00:10:16.21#ibcon#end of sib2, iclass 31, count 0 2006.174.00:10:16.21#ibcon#*mode == 0, iclass 31, count 0 2006.174.00:10:16.21#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.174.00:10:16.21#ibcon#[28=FRQ=02,634.99\r\n] 2006.174.00:10:16.21#ibcon#*before write, iclass 31, count 0 2006.174.00:10:16.21#ibcon#enter sib2, iclass 31, count 0 2006.174.00:10:16.21#ibcon#flushed, iclass 31, count 0 2006.174.00:10:16.21#ibcon#about to write, iclass 31, count 0 2006.174.00:10:16.21#ibcon#wrote, iclass 31, count 0 2006.174.00:10:16.21#ibcon#about to read 3, iclass 31, count 0 2006.174.00:10:16.25#ibcon#read 3, iclass 31, count 0 2006.174.00:10:16.25#ibcon#about to read 4, iclass 31, count 0 2006.174.00:10:16.25#ibcon#read 4, iclass 31, count 0 2006.174.00:10:16.25#ibcon#about to read 5, iclass 31, count 0 2006.174.00:10:16.25#ibcon#read 5, iclass 31, count 0 2006.174.00:10:16.25#ibcon#about to read 6, iclass 31, count 0 2006.174.00:10:16.25#ibcon#read 6, iclass 31, count 0 2006.174.00:10:16.25#ibcon#end of sib2, iclass 31, count 0 2006.174.00:10:16.25#ibcon#*after write, iclass 31, count 0 2006.174.00:10:16.25#ibcon#*before return 0, iclass 31, count 0 2006.174.00:10:16.25#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.174.00:10:16.25#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.174.00:10:16.25#ibcon#about to clear, iclass 31 cls_cnt 0 2006.174.00:10:16.25#ibcon#cleared, iclass 31 cls_cnt 0 2006.174.00:10:16.25$vck44/vb=2,4 2006.174.00:10:16.25#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.174.00:10:16.25#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.174.00:10:16.25#ibcon#ireg 11 cls_cnt 2 2006.174.00:10:16.25#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.174.00:10:16.31#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.174.00:10:16.31#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.174.00:10:16.31#ibcon#enter wrdev, iclass 33, count 2 2006.174.00:10:16.31#ibcon#first serial, iclass 33, count 2 2006.174.00:10:16.31#ibcon#enter sib2, iclass 33, count 2 2006.174.00:10:16.31#ibcon#flushed, iclass 33, count 2 2006.174.00:10:16.31#ibcon#about to write, iclass 33, count 2 2006.174.00:10:16.31#ibcon#wrote, iclass 33, count 2 2006.174.00:10:16.31#ibcon#about to read 3, iclass 33, count 2 2006.174.00:10:16.33#ibcon#read 3, iclass 33, count 2 2006.174.00:10:16.33#ibcon#about to read 4, iclass 33, count 2 2006.174.00:10:16.33#ibcon#read 4, iclass 33, count 2 2006.174.00:10:16.33#ibcon#about to read 5, iclass 33, count 2 2006.174.00:10:16.33#ibcon#read 5, iclass 33, count 2 2006.174.00:10:16.33#ibcon#about to read 6, iclass 33, count 2 2006.174.00:10:16.33#ibcon#read 6, iclass 33, count 2 2006.174.00:10:16.33#ibcon#end of sib2, iclass 33, count 2 2006.174.00:10:16.33#ibcon#*mode == 0, iclass 33, count 2 2006.174.00:10:16.33#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.174.00:10:16.33#ibcon#[27=AT02-04\r\n] 2006.174.00:10:16.33#ibcon#*before write, iclass 33, count 2 2006.174.00:10:16.33#ibcon#enter sib2, iclass 33, count 2 2006.174.00:10:16.33#ibcon#flushed, iclass 33, count 2 2006.174.00:10:16.33#ibcon#about to write, iclass 33, count 2 2006.174.00:10:16.33#ibcon#wrote, iclass 33, count 2 2006.174.00:10:16.33#ibcon#about to read 3, iclass 33, count 2 2006.174.00:10:16.36#ibcon#read 3, iclass 33, count 2 2006.174.00:10:16.36#ibcon#about to read 4, iclass 33, count 2 2006.174.00:10:16.36#ibcon#read 4, iclass 33, count 2 2006.174.00:10:16.36#ibcon#about to read 5, iclass 33, count 2 2006.174.00:10:16.36#ibcon#read 5, iclass 33, count 2 2006.174.00:10:16.36#ibcon#about to read 6, iclass 33, count 2 2006.174.00:10:16.36#ibcon#read 6, iclass 33, count 2 2006.174.00:10:16.36#ibcon#end of sib2, iclass 33, count 2 2006.174.00:10:16.36#ibcon#*after write, iclass 33, count 2 2006.174.00:10:16.36#ibcon#*before return 0, iclass 33, count 2 2006.174.00:10:16.36#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.174.00:10:16.36#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.174.00:10:16.36#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.174.00:10:16.36#ibcon#ireg 7 cls_cnt 0 2006.174.00:10:16.36#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.174.00:10:16.48#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.174.00:10:16.48#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.174.00:10:16.48#ibcon#enter wrdev, iclass 33, count 0 2006.174.00:10:16.48#ibcon#first serial, iclass 33, count 0 2006.174.00:10:16.48#ibcon#enter sib2, iclass 33, count 0 2006.174.00:10:16.48#ibcon#flushed, iclass 33, count 0 2006.174.00:10:16.48#ibcon#about to write, iclass 33, count 0 2006.174.00:10:16.48#ibcon#wrote, iclass 33, count 0 2006.174.00:10:16.48#ibcon#about to read 3, iclass 33, count 0 2006.174.00:10:16.50#ibcon#read 3, iclass 33, count 0 2006.174.00:10:16.50#ibcon#about to read 4, iclass 33, count 0 2006.174.00:10:16.50#ibcon#read 4, iclass 33, count 0 2006.174.00:10:16.50#ibcon#about to read 5, iclass 33, count 0 2006.174.00:10:16.50#ibcon#read 5, iclass 33, count 0 2006.174.00:10:16.50#ibcon#about to read 6, iclass 33, count 0 2006.174.00:10:16.50#ibcon#read 6, iclass 33, count 0 2006.174.00:10:16.50#ibcon#end of sib2, iclass 33, count 0 2006.174.00:10:16.50#ibcon#*mode == 0, iclass 33, count 0 2006.174.00:10:16.50#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.174.00:10:16.50#ibcon#[27=USB\r\n] 2006.174.00:10:16.50#ibcon#*before write, iclass 33, count 0 2006.174.00:10:16.50#ibcon#enter sib2, iclass 33, count 0 2006.174.00:10:16.50#ibcon#flushed, iclass 33, count 0 2006.174.00:10:16.50#ibcon#about to write, iclass 33, count 0 2006.174.00:10:16.50#ibcon#wrote, iclass 33, count 0 2006.174.00:10:16.50#ibcon#about to read 3, iclass 33, count 0 2006.174.00:10:16.53#ibcon#read 3, iclass 33, count 0 2006.174.00:10:16.53#ibcon#about to read 4, iclass 33, count 0 2006.174.00:10:16.53#ibcon#read 4, iclass 33, count 0 2006.174.00:10:16.53#ibcon#about to read 5, iclass 33, count 0 2006.174.00:10:16.53#ibcon#read 5, iclass 33, count 0 2006.174.00:10:16.53#ibcon#about to read 6, iclass 33, count 0 2006.174.00:10:16.53#ibcon#read 6, iclass 33, count 0 2006.174.00:10:16.53#ibcon#end of sib2, iclass 33, count 0 2006.174.00:10:16.53#ibcon#*after write, iclass 33, count 0 2006.174.00:10:16.53#ibcon#*before return 0, iclass 33, count 0 2006.174.00:10:16.53#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.174.00:10:16.53#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.174.00:10:16.53#ibcon#about to clear, iclass 33 cls_cnt 0 2006.174.00:10:16.53#ibcon#cleared, iclass 33 cls_cnt 0 2006.174.00:10:16.53$vck44/vblo=3,649.99 2006.174.00:10:16.53#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.174.00:10:16.53#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.174.00:10:16.53#ibcon#ireg 17 cls_cnt 0 2006.174.00:10:16.53#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.174.00:10:16.53#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.174.00:10:16.53#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.174.00:10:16.53#ibcon#enter wrdev, iclass 35, count 0 2006.174.00:10:16.53#ibcon#first serial, iclass 35, count 0 2006.174.00:10:16.53#ibcon#enter sib2, iclass 35, count 0 2006.174.00:10:16.53#ibcon#flushed, iclass 35, count 0 2006.174.00:10:16.53#ibcon#about to write, iclass 35, count 0 2006.174.00:10:16.53#ibcon#wrote, iclass 35, count 0 2006.174.00:10:16.53#ibcon#about to read 3, iclass 35, count 0 2006.174.00:10:16.55#ibcon#read 3, iclass 35, count 0 2006.174.00:10:16.55#ibcon#about to read 4, iclass 35, count 0 2006.174.00:10:16.55#ibcon#read 4, iclass 35, count 0 2006.174.00:10:16.55#ibcon#about to read 5, iclass 35, count 0 2006.174.00:10:16.55#ibcon#read 5, iclass 35, count 0 2006.174.00:10:16.55#ibcon#about to read 6, iclass 35, count 0 2006.174.00:10:16.55#ibcon#read 6, iclass 35, count 0 2006.174.00:10:16.55#ibcon#end of sib2, iclass 35, count 0 2006.174.00:10:16.55#ibcon#*mode == 0, iclass 35, count 0 2006.174.00:10:16.55#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.174.00:10:16.55#ibcon#[28=FRQ=03,649.99\r\n] 2006.174.00:10:16.55#ibcon#*before write, iclass 35, count 0 2006.174.00:10:16.55#ibcon#enter sib2, iclass 35, count 0 2006.174.00:10:16.55#ibcon#flushed, iclass 35, count 0 2006.174.00:10:16.55#ibcon#about to write, iclass 35, count 0 2006.174.00:10:16.55#ibcon#wrote, iclass 35, count 0 2006.174.00:10:16.55#ibcon#about to read 3, iclass 35, count 0 2006.174.00:10:16.59#ibcon#read 3, iclass 35, count 0 2006.174.00:10:16.59#ibcon#about to read 4, iclass 35, count 0 2006.174.00:10:16.59#ibcon#read 4, iclass 35, count 0 2006.174.00:10:16.59#ibcon#about to read 5, iclass 35, count 0 2006.174.00:10:16.59#ibcon#read 5, iclass 35, count 0 2006.174.00:10:16.59#ibcon#about to read 6, iclass 35, count 0 2006.174.00:10:16.59#ibcon#read 6, iclass 35, count 0 2006.174.00:10:16.59#ibcon#end of sib2, iclass 35, count 0 2006.174.00:10:16.59#ibcon#*after write, iclass 35, count 0 2006.174.00:10:16.59#ibcon#*before return 0, iclass 35, count 0 2006.174.00:10:16.59#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.174.00:10:16.59#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.174.00:10:16.59#ibcon#about to clear, iclass 35 cls_cnt 0 2006.174.00:10:16.59#ibcon#cleared, iclass 35 cls_cnt 0 2006.174.00:10:16.59$vck44/vb=3,4 2006.174.00:10:16.59#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.174.00:10:16.59#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.174.00:10:16.59#ibcon#ireg 11 cls_cnt 2 2006.174.00:10:16.59#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.174.00:10:16.65#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.174.00:10:16.65#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.174.00:10:16.65#ibcon#enter wrdev, iclass 37, count 2 2006.174.00:10:16.65#ibcon#first serial, iclass 37, count 2 2006.174.00:10:16.65#ibcon#enter sib2, iclass 37, count 2 2006.174.00:10:16.65#ibcon#flushed, iclass 37, count 2 2006.174.00:10:16.65#ibcon#about to write, iclass 37, count 2 2006.174.00:10:16.65#ibcon#wrote, iclass 37, count 2 2006.174.00:10:16.65#ibcon#about to read 3, iclass 37, count 2 2006.174.00:10:16.67#ibcon#read 3, iclass 37, count 2 2006.174.00:10:16.67#ibcon#about to read 4, iclass 37, count 2 2006.174.00:10:16.67#ibcon#read 4, iclass 37, count 2 2006.174.00:10:16.67#ibcon#about to read 5, iclass 37, count 2 2006.174.00:10:16.67#ibcon#read 5, iclass 37, count 2 2006.174.00:10:16.67#ibcon#about to read 6, iclass 37, count 2 2006.174.00:10:16.67#ibcon#read 6, iclass 37, count 2 2006.174.00:10:16.67#ibcon#end of sib2, iclass 37, count 2 2006.174.00:10:16.67#ibcon#*mode == 0, iclass 37, count 2 2006.174.00:10:16.67#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.174.00:10:16.67#ibcon#[27=AT03-04\r\n] 2006.174.00:10:16.67#ibcon#*before write, iclass 37, count 2 2006.174.00:10:16.67#ibcon#enter sib2, iclass 37, count 2 2006.174.00:10:16.67#ibcon#flushed, iclass 37, count 2 2006.174.00:10:16.67#ibcon#about to write, iclass 37, count 2 2006.174.00:10:16.67#ibcon#wrote, iclass 37, count 2 2006.174.00:10:16.67#ibcon#about to read 3, iclass 37, count 2 2006.174.00:10:16.70#ibcon#read 3, iclass 37, count 2 2006.174.00:10:16.70#ibcon#about to read 4, iclass 37, count 2 2006.174.00:10:16.70#ibcon#read 4, iclass 37, count 2 2006.174.00:10:16.70#ibcon#about to read 5, iclass 37, count 2 2006.174.00:10:16.70#ibcon#read 5, iclass 37, count 2 2006.174.00:10:16.70#ibcon#about to read 6, iclass 37, count 2 2006.174.00:10:16.70#ibcon#read 6, iclass 37, count 2 2006.174.00:10:16.70#ibcon#end of sib2, iclass 37, count 2 2006.174.00:10:16.70#ibcon#*after write, iclass 37, count 2 2006.174.00:10:16.70#ibcon#*before return 0, iclass 37, count 2 2006.174.00:10:16.70#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.174.00:10:16.70#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.174.00:10:16.70#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.174.00:10:16.70#ibcon#ireg 7 cls_cnt 0 2006.174.00:10:16.70#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.174.00:10:16.82#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.174.00:10:16.82#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.174.00:10:16.82#ibcon#enter wrdev, iclass 37, count 0 2006.174.00:10:16.82#ibcon#first serial, iclass 37, count 0 2006.174.00:10:16.82#ibcon#enter sib2, iclass 37, count 0 2006.174.00:10:16.82#ibcon#flushed, iclass 37, count 0 2006.174.00:10:16.82#ibcon#about to write, iclass 37, count 0 2006.174.00:10:16.82#ibcon#wrote, iclass 37, count 0 2006.174.00:10:16.82#ibcon#about to read 3, iclass 37, count 0 2006.174.00:10:16.84#ibcon#read 3, iclass 37, count 0 2006.174.00:10:16.84#ibcon#about to read 4, iclass 37, count 0 2006.174.00:10:16.84#ibcon#read 4, iclass 37, count 0 2006.174.00:10:16.84#ibcon#about to read 5, iclass 37, count 0 2006.174.00:10:16.84#ibcon#read 5, iclass 37, count 0 2006.174.00:10:16.84#ibcon#about to read 6, iclass 37, count 0 2006.174.00:10:16.84#ibcon#read 6, iclass 37, count 0 2006.174.00:10:16.84#ibcon#end of sib2, iclass 37, count 0 2006.174.00:10:16.84#ibcon#*mode == 0, iclass 37, count 0 2006.174.00:10:16.84#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.174.00:10:16.84#ibcon#[27=USB\r\n] 2006.174.00:10:16.84#ibcon#*before write, iclass 37, count 0 2006.174.00:10:16.84#ibcon#enter sib2, iclass 37, count 0 2006.174.00:10:16.84#ibcon#flushed, iclass 37, count 0 2006.174.00:10:16.84#ibcon#about to write, iclass 37, count 0 2006.174.00:10:16.84#ibcon#wrote, iclass 37, count 0 2006.174.00:10:16.84#ibcon#about to read 3, iclass 37, count 0 2006.174.00:10:16.87#ibcon#read 3, iclass 37, count 0 2006.174.00:10:16.87#ibcon#about to read 4, iclass 37, count 0 2006.174.00:10:16.87#ibcon#read 4, iclass 37, count 0 2006.174.00:10:16.87#ibcon#about to read 5, iclass 37, count 0 2006.174.00:10:16.87#ibcon#read 5, iclass 37, count 0 2006.174.00:10:16.87#ibcon#about to read 6, iclass 37, count 0 2006.174.00:10:16.87#ibcon#read 6, iclass 37, count 0 2006.174.00:10:16.87#ibcon#end of sib2, iclass 37, count 0 2006.174.00:10:16.87#ibcon#*after write, iclass 37, count 0 2006.174.00:10:16.87#ibcon#*before return 0, iclass 37, count 0 2006.174.00:10:16.87#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.174.00:10:16.87#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.174.00:10:16.87#ibcon#about to clear, iclass 37 cls_cnt 0 2006.174.00:10:16.87#ibcon#cleared, iclass 37 cls_cnt 0 2006.174.00:10:16.87$vck44/vblo=4,679.99 2006.174.00:10:16.87#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.174.00:10:16.87#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.174.00:10:16.87#ibcon#ireg 17 cls_cnt 0 2006.174.00:10:16.87#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.174.00:10:16.87#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.174.00:10:16.87#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.174.00:10:16.87#ibcon#enter wrdev, iclass 39, count 0 2006.174.00:10:16.87#ibcon#first serial, iclass 39, count 0 2006.174.00:10:16.87#ibcon#enter sib2, iclass 39, count 0 2006.174.00:10:16.87#ibcon#flushed, iclass 39, count 0 2006.174.00:10:16.87#ibcon#about to write, iclass 39, count 0 2006.174.00:10:16.87#ibcon#wrote, iclass 39, count 0 2006.174.00:10:16.87#ibcon#about to read 3, iclass 39, count 0 2006.174.00:10:16.89#ibcon#read 3, iclass 39, count 0 2006.174.00:10:16.89#ibcon#about to read 4, iclass 39, count 0 2006.174.00:10:16.89#ibcon#read 4, iclass 39, count 0 2006.174.00:10:16.89#ibcon#about to read 5, iclass 39, count 0 2006.174.00:10:16.89#ibcon#read 5, iclass 39, count 0 2006.174.00:10:16.89#ibcon#about to read 6, iclass 39, count 0 2006.174.00:10:16.89#ibcon#read 6, iclass 39, count 0 2006.174.00:10:16.89#ibcon#end of sib2, iclass 39, count 0 2006.174.00:10:16.89#ibcon#*mode == 0, iclass 39, count 0 2006.174.00:10:16.89#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.174.00:10:16.89#ibcon#[28=FRQ=04,679.99\r\n] 2006.174.00:10:16.89#ibcon#*before write, iclass 39, count 0 2006.174.00:10:16.89#ibcon#enter sib2, iclass 39, count 0 2006.174.00:10:16.89#ibcon#flushed, iclass 39, count 0 2006.174.00:10:16.89#ibcon#about to write, iclass 39, count 0 2006.174.00:10:16.89#ibcon#wrote, iclass 39, count 0 2006.174.00:10:16.89#ibcon#about to read 3, iclass 39, count 0 2006.174.00:10:16.93#ibcon#read 3, iclass 39, count 0 2006.174.00:10:16.93#ibcon#about to read 4, iclass 39, count 0 2006.174.00:10:16.93#ibcon#read 4, iclass 39, count 0 2006.174.00:10:16.93#ibcon#about to read 5, iclass 39, count 0 2006.174.00:10:16.93#ibcon#read 5, iclass 39, count 0 2006.174.00:10:16.93#ibcon#about to read 6, iclass 39, count 0 2006.174.00:10:16.93#ibcon#read 6, iclass 39, count 0 2006.174.00:10:16.93#ibcon#end of sib2, iclass 39, count 0 2006.174.00:10:16.93#ibcon#*after write, iclass 39, count 0 2006.174.00:10:16.93#ibcon#*before return 0, iclass 39, count 0 2006.174.00:10:16.93#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.174.00:10:16.93#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.174.00:10:16.93#ibcon#about to clear, iclass 39 cls_cnt 0 2006.174.00:10:16.93#ibcon#cleared, iclass 39 cls_cnt 0 2006.174.00:10:16.93$vck44/vb=4,4 2006.174.00:10:16.93#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.174.00:10:16.93#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.174.00:10:16.93#ibcon#ireg 11 cls_cnt 2 2006.174.00:10:16.93#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.174.00:10:16.99#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.174.00:10:16.99#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.174.00:10:16.99#ibcon#enter wrdev, iclass 3, count 2 2006.174.00:10:16.99#ibcon#first serial, iclass 3, count 2 2006.174.00:10:16.99#ibcon#enter sib2, iclass 3, count 2 2006.174.00:10:16.99#ibcon#flushed, iclass 3, count 2 2006.174.00:10:16.99#ibcon#about to write, iclass 3, count 2 2006.174.00:10:16.99#ibcon#wrote, iclass 3, count 2 2006.174.00:10:16.99#ibcon#about to read 3, iclass 3, count 2 2006.174.00:10:17.01#ibcon#read 3, iclass 3, count 2 2006.174.00:10:17.01#ibcon#about to read 4, iclass 3, count 2 2006.174.00:10:17.01#ibcon#read 4, iclass 3, count 2 2006.174.00:10:17.01#ibcon#about to read 5, iclass 3, count 2 2006.174.00:10:17.01#ibcon#read 5, iclass 3, count 2 2006.174.00:10:17.01#ibcon#about to read 6, iclass 3, count 2 2006.174.00:10:17.01#ibcon#read 6, iclass 3, count 2 2006.174.00:10:17.01#ibcon#end of sib2, iclass 3, count 2 2006.174.00:10:17.01#ibcon#*mode == 0, iclass 3, count 2 2006.174.00:10:17.01#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.174.00:10:17.01#ibcon#[27=AT04-04\r\n] 2006.174.00:10:17.01#ibcon#*before write, iclass 3, count 2 2006.174.00:10:17.01#ibcon#enter sib2, iclass 3, count 2 2006.174.00:10:17.01#ibcon#flushed, iclass 3, count 2 2006.174.00:10:17.01#ibcon#about to write, iclass 3, count 2 2006.174.00:10:17.01#ibcon#wrote, iclass 3, count 2 2006.174.00:10:17.01#ibcon#about to read 3, iclass 3, count 2 2006.174.00:10:17.04#ibcon#read 3, iclass 3, count 2 2006.174.00:10:17.04#ibcon#about to read 4, iclass 3, count 2 2006.174.00:10:17.04#ibcon#read 4, iclass 3, count 2 2006.174.00:10:17.04#ibcon#about to read 5, iclass 3, count 2 2006.174.00:10:17.04#ibcon#read 5, iclass 3, count 2 2006.174.00:10:17.04#ibcon#about to read 6, iclass 3, count 2 2006.174.00:10:17.04#ibcon#read 6, iclass 3, count 2 2006.174.00:10:17.04#ibcon#end of sib2, iclass 3, count 2 2006.174.00:10:17.04#ibcon#*after write, iclass 3, count 2 2006.174.00:10:17.04#ibcon#*before return 0, iclass 3, count 2 2006.174.00:10:17.04#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.174.00:10:17.04#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.174.00:10:17.04#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.174.00:10:17.04#ibcon#ireg 7 cls_cnt 0 2006.174.00:10:17.04#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.174.00:10:17.16#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.174.00:10:17.16#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.174.00:10:17.16#ibcon#enter wrdev, iclass 3, count 0 2006.174.00:10:17.16#ibcon#first serial, iclass 3, count 0 2006.174.00:10:17.16#ibcon#enter sib2, iclass 3, count 0 2006.174.00:10:17.16#ibcon#flushed, iclass 3, count 0 2006.174.00:10:17.16#ibcon#about to write, iclass 3, count 0 2006.174.00:10:17.16#ibcon#wrote, iclass 3, count 0 2006.174.00:10:17.16#ibcon#about to read 3, iclass 3, count 0 2006.174.00:10:17.18#ibcon#read 3, iclass 3, count 0 2006.174.00:10:17.18#ibcon#about to read 4, iclass 3, count 0 2006.174.00:10:17.18#ibcon#read 4, iclass 3, count 0 2006.174.00:10:17.18#ibcon#about to read 5, iclass 3, count 0 2006.174.00:10:17.18#ibcon#read 5, iclass 3, count 0 2006.174.00:10:17.18#ibcon#about to read 6, iclass 3, count 0 2006.174.00:10:17.18#ibcon#read 6, iclass 3, count 0 2006.174.00:10:17.18#ibcon#end of sib2, iclass 3, count 0 2006.174.00:10:17.18#ibcon#*mode == 0, iclass 3, count 0 2006.174.00:10:17.18#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.174.00:10:17.18#ibcon#[27=USB\r\n] 2006.174.00:10:17.18#ibcon#*before write, iclass 3, count 0 2006.174.00:10:17.18#ibcon#enter sib2, iclass 3, count 0 2006.174.00:10:17.18#ibcon#flushed, iclass 3, count 0 2006.174.00:10:17.18#ibcon#about to write, iclass 3, count 0 2006.174.00:10:17.18#ibcon#wrote, iclass 3, count 0 2006.174.00:10:17.18#ibcon#about to read 3, iclass 3, count 0 2006.174.00:10:17.21#ibcon#read 3, iclass 3, count 0 2006.174.00:10:17.21#ibcon#about to read 4, iclass 3, count 0 2006.174.00:10:17.21#ibcon#read 4, iclass 3, count 0 2006.174.00:10:17.21#ibcon#about to read 5, iclass 3, count 0 2006.174.00:10:17.21#ibcon#read 5, iclass 3, count 0 2006.174.00:10:17.21#ibcon#about to read 6, iclass 3, count 0 2006.174.00:10:17.21#ibcon#read 6, iclass 3, count 0 2006.174.00:10:17.21#ibcon#end of sib2, iclass 3, count 0 2006.174.00:10:17.21#ibcon#*after write, iclass 3, count 0 2006.174.00:10:17.21#ibcon#*before return 0, iclass 3, count 0 2006.174.00:10:17.21#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.174.00:10:17.21#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.174.00:10:17.21#ibcon#about to clear, iclass 3 cls_cnt 0 2006.174.00:10:17.21#ibcon#cleared, iclass 3 cls_cnt 0 2006.174.00:10:17.21$vck44/vblo=5,709.99 2006.174.00:10:17.21#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.174.00:10:17.21#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.174.00:10:17.21#ibcon#ireg 17 cls_cnt 0 2006.174.00:10:17.21#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.174.00:10:17.21#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.174.00:10:17.21#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.174.00:10:17.21#ibcon#enter wrdev, iclass 5, count 0 2006.174.00:10:17.21#ibcon#first serial, iclass 5, count 0 2006.174.00:10:17.21#ibcon#enter sib2, iclass 5, count 0 2006.174.00:10:17.21#ibcon#flushed, iclass 5, count 0 2006.174.00:10:17.21#ibcon#about to write, iclass 5, count 0 2006.174.00:10:17.21#ibcon#wrote, iclass 5, count 0 2006.174.00:10:17.21#ibcon#about to read 3, iclass 5, count 0 2006.174.00:10:17.23#ibcon#read 3, iclass 5, count 0 2006.174.00:10:17.23#ibcon#about to read 4, iclass 5, count 0 2006.174.00:10:17.23#ibcon#read 4, iclass 5, count 0 2006.174.00:10:17.23#ibcon#about to read 5, iclass 5, count 0 2006.174.00:10:17.23#ibcon#read 5, iclass 5, count 0 2006.174.00:10:17.23#ibcon#about to read 6, iclass 5, count 0 2006.174.00:10:17.23#ibcon#read 6, iclass 5, count 0 2006.174.00:10:17.23#ibcon#end of sib2, iclass 5, count 0 2006.174.00:10:17.23#ibcon#*mode == 0, iclass 5, count 0 2006.174.00:10:17.23#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.174.00:10:17.23#ibcon#[28=FRQ=05,709.99\r\n] 2006.174.00:10:17.23#ibcon#*before write, iclass 5, count 0 2006.174.00:10:17.23#ibcon#enter sib2, iclass 5, count 0 2006.174.00:10:17.23#ibcon#flushed, iclass 5, count 0 2006.174.00:10:17.23#ibcon#about to write, iclass 5, count 0 2006.174.00:10:17.23#ibcon#wrote, iclass 5, count 0 2006.174.00:10:17.23#ibcon#about to read 3, iclass 5, count 0 2006.174.00:10:17.27#ibcon#read 3, iclass 5, count 0 2006.174.00:10:17.27#ibcon#about to read 4, iclass 5, count 0 2006.174.00:10:17.27#ibcon#read 4, iclass 5, count 0 2006.174.00:10:17.27#ibcon#about to read 5, iclass 5, count 0 2006.174.00:10:17.27#ibcon#read 5, iclass 5, count 0 2006.174.00:10:17.27#ibcon#about to read 6, iclass 5, count 0 2006.174.00:10:17.27#ibcon#read 6, iclass 5, count 0 2006.174.00:10:17.27#ibcon#end of sib2, iclass 5, count 0 2006.174.00:10:17.27#ibcon#*after write, iclass 5, count 0 2006.174.00:10:17.27#ibcon#*before return 0, iclass 5, count 0 2006.174.00:10:17.27#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.174.00:10:17.27#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.174.00:10:17.27#ibcon#about to clear, iclass 5 cls_cnt 0 2006.174.00:10:17.27#ibcon#cleared, iclass 5 cls_cnt 0 2006.174.00:10:17.27$vck44/vb=5,4 2006.174.00:10:17.27#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.174.00:10:17.27#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.174.00:10:17.27#ibcon#ireg 11 cls_cnt 2 2006.174.00:10:17.27#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.174.00:10:17.33#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.174.00:10:17.33#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.174.00:10:17.33#ibcon#enter wrdev, iclass 7, count 2 2006.174.00:10:17.33#ibcon#first serial, iclass 7, count 2 2006.174.00:10:17.33#ibcon#enter sib2, iclass 7, count 2 2006.174.00:10:17.33#ibcon#flushed, iclass 7, count 2 2006.174.00:10:17.33#ibcon#about to write, iclass 7, count 2 2006.174.00:10:17.33#ibcon#wrote, iclass 7, count 2 2006.174.00:10:17.33#ibcon#about to read 3, iclass 7, count 2 2006.174.00:10:17.35#ibcon#read 3, iclass 7, count 2 2006.174.00:10:17.35#ibcon#about to read 4, iclass 7, count 2 2006.174.00:10:17.35#ibcon#read 4, iclass 7, count 2 2006.174.00:10:17.35#ibcon#about to read 5, iclass 7, count 2 2006.174.00:10:17.35#ibcon#read 5, iclass 7, count 2 2006.174.00:10:17.35#ibcon#about to read 6, iclass 7, count 2 2006.174.00:10:17.35#ibcon#read 6, iclass 7, count 2 2006.174.00:10:17.35#ibcon#end of sib2, iclass 7, count 2 2006.174.00:10:17.35#ibcon#*mode == 0, iclass 7, count 2 2006.174.00:10:17.35#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.174.00:10:17.35#ibcon#[27=AT05-04\r\n] 2006.174.00:10:17.35#ibcon#*before write, iclass 7, count 2 2006.174.00:10:17.35#ibcon#enter sib2, iclass 7, count 2 2006.174.00:10:17.35#ibcon#flushed, iclass 7, count 2 2006.174.00:10:17.35#ibcon#about to write, iclass 7, count 2 2006.174.00:10:17.35#ibcon#wrote, iclass 7, count 2 2006.174.00:10:17.35#ibcon#about to read 3, iclass 7, count 2 2006.174.00:10:17.38#ibcon#read 3, iclass 7, count 2 2006.174.00:10:17.38#ibcon#about to read 4, iclass 7, count 2 2006.174.00:10:17.38#ibcon#read 4, iclass 7, count 2 2006.174.00:10:17.38#ibcon#about to read 5, iclass 7, count 2 2006.174.00:10:17.38#ibcon#read 5, iclass 7, count 2 2006.174.00:10:17.38#ibcon#about to read 6, iclass 7, count 2 2006.174.00:10:17.38#ibcon#read 6, iclass 7, count 2 2006.174.00:10:17.38#ibcon#end of sib2, iclass 7, count 2 2006.174.00:10:17.38#ibcon#*after write, iclass 7, count 2 2006.174.00:10:17.38#ibcon#*before return 0, iclass 7, count 2 2006.174.00:10:17.38#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.174.00:10:17.38#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.174.00:10:17.38#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.174.00:10:17.38#ibcon#ireg 7 cls_cnt 0 2006.174.00:10:17.38#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.174.00:10:17.50#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.174.00:10:17.50#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.174.00:10:17.50#ibcon#enter wrdev, iclass 7, count 0 2006.174.00:10:17.50#ibcon#first serial, iclass 7, count 0 2006.174.00:10:17.50#ibcon#enter sib2, iclass 7, count 0 2006.174.00:10:17.50#ibcon#flushed, iclass 7, count 0 2006.174.00:10:17.50#ibcon#about to write, iclass 7, count 0 2006.174.00:10:17.50#ibcon#wrote, iclass 7, count 0 2006.174.00:10:17.50#ibcon#about to read 3, iclass 7, count 0 2006.174.00:10:17.52#ibcon#read 3, iclass 7, count 0 2006.174.00:10:17.52#ibcon#about to read 4, iclass 7, count 0 2006.174.00:10:17.52#ibcon#read 4, iclass 7, count 0 2006.174.00:10:17.52#ibcon#about to read 5, iclass 7, count 0 2006.174.00:10:17.52#ibcon#read 5, iclass 7, count 0 2006.174.00:10:17.52#ibcon#about to read 6, iclass 7, count 0 2006.174.00:10:17.52#ibcon#read 6, iclass 7, count 0 2006.174.00:10:17.52#ibcon#end of sib2, iclass 7, count 0 2006.174.00:10:17.52#ibcon#*mode == 0, iclass 7, count 0 2006.174.00:10:17.52#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.174.00:10:17.52#ibcon#[27=USB\r\n] 2006.174.00:10:17.52#ibcon#*before write, iclass 7, count 0 2006.174.00:10:17.52#ibcon#enter sib2, iclass 7, count 0 2006.174.00:10:17.52#ibcon#flushed, iclass 7, count 0 2006.174.00:10:17.52#ibcon#about to write, iclass 7, count 0 2006.174.00:10:17.52#ibcon#wrote, iclass 7, count 0 2006.174.00:10:17.52#ibcon#about to read 3, iclass 7, count 0 2006.174.00:10:17.55#ibcon#read 3, iclass 7, count 0 2006.174.00:10:17.55#ibcon#about to read 4, iclass 7, count 0 2006.174.00:10:17.55#ibcon#read 4, iclass 7, count 0 2006.174.00:10:17.55#ibcon#about to read 5, iclass 7, count 0 2006.174.00:10:17.55#ibcon#read 5, iclass 7, count 0 2006.174.00:10:17.55#ibcon#about to read 6, iclass 7, count 0 2006.174.00:10:17.55#ibcon#read 6, iclass 7, count 0 2006.174.00:10:17.55#ibcon#end of sib2, iclass 7, count 0 2006.174.00:10:17.55#ibcon#*after write, iclass 7, count 0 2006.174.00:10:17.55#ibcon#*before return 0, iclass 7, count 0 2006.174.00:10:17.55#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.174.00:10:17.55#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.174.00:10:17.55#ibcon#about to clear, iclass 7 cls_cnt 0 2006.174.00:10:17.55#ibcon#cleared, iclass 7 cls_cnt 0 2006.174.00:10:17.55$vck44/vblo=6,719.99 2006.174.00:10:17.55#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.174.00:10:17.55#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.174.00:10:17.55#ibcon#ireg 17 cls_cnt 0 2006.174.00:10:17.55#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.174.00:10:17.55#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.174.00:10:17.55#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.174.00:10:17.55#ibcon#enter wrdev, iclass 11, count 0 2006.174.00:10:17.55#ibcon#first serial, iclass 11, count 0 2006.174.00:10:17.55#ibcon#enter sib2, iclass 11, count 0 2006.174.00:10:17.55#ibcon#flushed, iclass 11, count 0 2006.174.00:10:17.55#ibcon#about to write, iclass 11, count 0 2006.174.00:10:17.55#ibcon#wrote, iclass 11, count 0 2006.174.00:10:17.55#ibcon#about to read 3, iclass 11, count 0 2006.174.00:10:17.57#ibcon#read 3, iclass 11, count 0 2006.174.00:10:17.57#ibcon#about to read 4, iclass 11, count 0 2006.174.00:10:17.57#ibcon#read 4, iclass 11, count 0 2006.174.00:10:17.57#ibcon#about to read 5, iclass 11, count 0 2006.174.00:10:17.57#ibcon#read 5, iclass 11, count 0 2006.174.00:10:17.57#ibcon#about to read 6, iclass 11, count 0 2006.174.00:10:17.57#ibcon#read 6, iclass 11, count 0 2006.174.00:10:17.57#ibcon#end of sib2, iclass 11, count 0 2006.174.00:10:17.57#ibcon#*mode == 0, iclass 11, count 0 2006.174.00:10:17.57#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.174.00:10:17.57#ibcon#[28=FRQ=06,719.99\r\n] 2006.174.00:10:17.57#ibcon#*before write, iclass 11, count 0 2006.174.00:10:17.57#ibcon#enter sib2, iclass 11, count 0 2006.174.00:10:17.57#ibcon#flushed, iclass 11, count 0 2006.174.00:10:17.57#ibcon#about to write, iclass 11, count 0 2006.174.00:10:17.57#ibcon#wrote, iclass 11, count 0 2006.174.00:10:17.57#ibcon#about to read 3, iclass 11, count 0 2006.174.00:10:17.61#ibcon#read 3, iclass 11, count 0 2006.174.00:10:17.61#ibcon#about to read 4, iclass 11, count 0 2006.174.00:10:17.61#ibcon#read 4, iclass 11, count 0 2006.174.00:10:17.61#ibcon#about to read 5, iclass 11, count 0 2006.174.00:10:17.61#ibcon#read 5, iclass 11, count 0 2006.174.00:10:17.61#ibcon#about to read 6, iclass 11, count 0 2006.174.00:10:17.61#ibcon#read 6, iclass 11, count 0 2006.174.00:10:17.61#ibcon#end of sib2, iclass 11, count 0 2006.174.00:10:17.61#ibcon#*after write, iclass 11, count 0 2006.174.00:10:17.61#ibcon#*before return 0, iclass 11, count 0 2006.174.00:10:17.61#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.174.00:10:17.61#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.174.00:10:17.61#ibcon#about to clear, iclass 11 cls_cnt 0 2006.174.00:10:17.61#ibcon#cleared, iclass 11 cls_cnt 0 2006.174.00:10:17.61$vck44/vb=6,4 2006.174.00:10:17.61#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.174.00:10:17.61#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.174.00:10:17.61#ibcon#ireg 11 cls_cnt 2 2006.174.00:10:17.61#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.174.00:10:17.67#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.174.00:10:17.67#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.174.00:10:17.67#ibcon#enter wrdev, iclass 13, count 2 2006.174.00:10:17.67#ibcon#first serial, iclass 13, count 2 2006.174.00:10:17.67#ibcon#enter sib2, iclass 13, count 2 2006.174.00:10:17.67#ibcon#flushed, iclass 13, count 2 2006.174.00:10:17.67#ibcon#about to write, iclass 13, count 2 2006.174.00:10:17.67#ibcon#wrote, iclass 13, count 2 2006.174.00:10:17.67#ibcon#about to read 3, iclass 13, count 2 2006.174.00:10:17.69#ibcon#read 3, iclass 13, count 2 2006.174.00:10:17.69#ibcon#about to read 4, iclass 13, count 2 2006.174.00:10:17.69#ibcon#read 4, iclass 13, count 2 2006.174.00:10:17.69#ibcon#about to read 5, iclass 13, count 2 2006.174.00:10:17.69#ibcon#read 5, iclass 13, count 2 2006.174.00:10:17.69#ibcon#about to read 6, iclass 13, count 2 2006.174.00:10:17.69#ibcon#read 6, iclass 13, count 2 2006.174.00:10:17.69#ibcon#end of sib2, iclass 13, count 2 2006.174.00:10:17.69#ibcon#*mode == 0, iclass 13, count 2 2006.174.00:10:17.69#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.174.00:10:17.69#ibcon#[27=AT06-04\r\n] 2006.174.00:10:17.69#ibcon#*before write, iclass 13, count 2 2006.174.00:10:17.69#ibcon#enter sib2, iclass 13, count 2 2006.174.00:10:17.69#ibcon#flushed, iclass 13, count 2 2006.174.00:10:17.69#ibcon#about to write, iclass 13, count 2 2006.174.00:10:17.69#ibcon#wrote, iclass 13, count 2 2006.174.00:10:17.69#ibcon#about to read 3, iclass 13, count 2 2006.174.00:10:17.72#ibcon#read 3, iclass 13, count 2 2006.174.00:10:17.72#ibcon#about to read 4, iclass 13, count 2 2006.174.00:10:17.72#ibcon#read 4, iclass 13, count 2 2006.174.00:10:17.72#ibcon#about to read 5, iclass 13, count 2 2006.174.00:10:17.72#ibcon#read 5, iclass 13, count 2 2006.174.00:10:17.72#ibcon#about to read 6, iclass 13, count 2 2006.174.00:10:17.72#ibcon#read 6, iclass 13, count 2 2006.174.00:10:17.72#ibcon#end of sib2, iclass 13, count 2 2006.174.00:10:17.72#ibcon#*after write, iclass 13, count 2 2006.174.00:10:17.72#ibcon#*before return 0, iclass 13, count 2 2006.174.00:10:17.72#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.174.00:10:17.72#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.174.00:10:17.72#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.174.00:10:17.72#ibcon#ireg 7 cls_cnt 0 2006.174.00:10:17.72#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.174.00:10:17.84#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.174.00:10:17.84#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.174.00:10:17.84#ibcon#enter wrdev, iclass 13, count 0 2006.174.00:10:17.84#ibcon#first serial, iclass 13, count 0 2006.174.00:10:17.84#ibcon#enter sib2, iclass 13, count 0 2006.174.00:10:17.84#ibcon#flushed, iclass 13, count 0 2006.174.00:10:17.84#ibcon#about to write, iclass 13, count 0 2006.174.00:10:17.84#ibcon#wrote, iclass 13, count 0 2006.174.00:10:17.84#ibcon#about to read 3, iclass 13, count 0 2006.174.00:10:17.86#ibcon#read 3, iclass 13, count 0 2006.174.00:10:17.86#ibcon#about to read 4, iclass 13, count 0 2006.174.00:10:17.86#ibcon#read 4, iclass 13, count 0 2006.174.00:10:17.86#ibcon#about to read 5, iclass 13, count 0 2006.174.00:10:17.86#ibcon#read 5, iclass 13, count 0 2006.174.00:10:17.86#ibcon#about to read 6, iclass 13, count 0 2006.174.00:10:17.86#ibcon#read 6, iclass 13, count 0 2006.174.00:10:17.86#ibcon#end of sib2, iclass 13, count 0 2006.174.00:10:17.86#ibcon#*mode == 0, iclass 13, count 0 2006.174.00:10:17.86#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.174.00:10:17.86#ibcon#[27=USB\r\n] 2006.174.00:10:17.86#ibcon#*before write, iclass 13, count 0 2006.174.00:10:17.86#ibcon#enter sib2, iclass 13, count 0 2006.174.00:10:17.86#ibcon#flushed, iclass 13, count 0 2006.174.00:10:17.86#ibcon#about to write, iclass 13, count 0 2006.174.00:10:17.86#ibcon#wrote, iclass 13, count 0 2006.174.00:10:17.86#ibcon#about to read 3, iclass 13, count 0 2006.174.00:10:17.89#ibcon#read 3, iclass 13, count 0 2006.174.00:10:17.89#ibcon#about to read 4, iclass 13, count 0 2006.174.00:10:17.89#ibcon#read 4, iclass 13, count 0 2006.174.00:10:17.89#ibcon#about to read 5, iclass 13, count 0 2006.174.00:10:17.89#ibcon#read 5, iclass 13, count 0 2006.174.00:10:17.89#ibcon#about to read 6, iclass 13, count 0 2006.174.00:10:17.89#ibcon#read 6, iclass 13, count 0 2006.174.00:10:17.89#ibcon#end of sib2, iclass 13, count 0 2006.174.00:10:17.89#ibcon#*after write, iclass 13, count 0 2006.174.00:10:17.89#ibcon#*before return 0, iclass 13, count 0 2006.174.00:10:17.89#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.174.00:10:17.89#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.174.00:10:17.89#ibcon#about to clear, iclass 13 cls_cnt 0 2006.174.00:10:17.89#ibcon#cleared, iclass 13 cls_cnt 0 2006.174.00:10:17.89$vck44/vblo=7,734.99 2006.174.00:10:17.89#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.174.00:10:17.89#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.174.00:10:17.89#ibcon#ireg 17 cls_cnt 0 2006.174.00:10:17.89#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.174.00:10:17.89#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.174.00:10:17.89#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.174.00:10:17.89#ibcon#enter wrdev, iclass 15, count 0 2006.174.00:10:17.89#ibcon#first serial, iclass 15, count 0 2006.174.00:10:17.89#ibcon#enter sib2, iclass 15, count 0 2006.174.00:10:17.89#ibcon#flushed, iclass 15, count 0 2006.174.00:10:17.89#ibcon#about to write, iclass 15, count 0 2006.174.00:10:17.89#ibcon#wrote, iclass 15, count 0 2006.174.00:10:17.89#ibcon#about to read 3, iclass 15, count 0 2006.174.00:10:17.91#ibcon#read 3, iclass 15, count 0 2006.174.00:10:17.91#ibcon#about to read 4, iclass 15, count 0 2006.174.00:10:17.91#ibcon#read 4, iclass 15, count 0 2006.174.00:10:17.91#ibcon#about to read 5, iclass 15, count 0 2006.174.00:10:17.91#ibcon#read 5, iclass 15, count 0 2006.174.00:10:17.91#ibcon#about to read 6, iclass 15, count 0 2006.174.00:10:17.91#ibcon#read 6, iclass 15, count 0 2006.174.00:10:17.91#ibcon#end of sib2, iclass 15, count 0 2006.174.00:10:17.91#ibcon#*mode == 0, iclass 15, count 0 2006.174.00:10:17.91#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.174.00:10:17.91#ibcon#[28=FRQ=07,734.99\r\n] 2006.174.00:10:17.91#ibcon#*before write, iclass 15, count 0 2006.174.00:10:17.91#ibcon#enter sib2, iclass 15, count 0 2006.174.00:10:17.91#ibcon#flushed, iclass 15, count 0 2006.174.00:10:17.91#ibcon#about to write, iclass 15, count 0 2006.174.00:10:17.91#ibcon#wrote, iclass 15, count 0 2006.174.00:10:17.91#ibcon#about to read 3, iclass 15, count 0 2006.174.00:10:17.95#ibcon#read 3, iclass 15, count 0 2006.174.00:10:17.95#ibcon#about to read 4, iclass 15, count 0 2006.174.00:10:17.95#ibcon#read 4, iclass 15, count 0 2006.174.00:10:17.95#ibcon#about to read 5, iclass 15, count 0 2006.174.00:10:17.95#ibcon#read 5, iclass 15, count 0 2006.174.00:10:17.95#ibcon#about to read 6, iclass 15, count 0 2006.174.00:10:17.95#ibcon#read 6, iclass 15, count 0 2006.174.00:10:17.95#ibcon#end of sib2, iclass 15, count 0 2006.174.00:10:17.95#ibcon#*after write, iclass 15, count 0 2006.174.00:10:17.95#ibcon#*before return 0, iclass 15, count 0 2006.174.00:10:17.95#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.174.00:10:17.95#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.174.00:10:17.95#ibcon#about to clear, iclass 15 cls_cnt 0 2006.174.00:10:17.95#ibcon#cleared, iclass 15 cls_cnt 0 2006.174.00:10:17.95$vck44/vb=7,4 2006.174.00:10:17.95#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.174.00:10:17.95#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.174.00:10:17.95#ibcon#ireg 11 cls_cnt 2 2006.174.00:10:17.95#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.174.00:10:18.01#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.174.00:10:18.01#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.174.00:10:18.01#ibcon#enter wrdev, iclass 17, count 2 2006.174.00:10:18.01#ibcon#first serial, iclass 17, count 2 2006.174.00:10:18.01#ibcon#enter sib2, iclass 17, count 2 2006.174.00:10:18.01#ibcon#flushed, iclass 17, count 2 2006.174.00:10:18.01#ibcon#about to write, iclass 17, count 2 2006.174.00:10:18.01#ibcon#wrote, iclass 17, count 2 2006.174.00:10:18.01#ibcon#about to read 3, iclass 17, count 2 2006.174.00:10:18.03#ibcon#read 3, iclass 17, count 2 2006.174.00:10:18.03#ibcon#about to read 4, iclass 17, count 2 2006.174.00:10:18.03#ibcon#read 4, iclass 17, count 2 2006.174.00:10:18.03#ibcon#about to read 5, iclass 17, count 2 2006.174.00:10:18.03#ibcon#read 5, iclass 17, count 2 2006.174.00:10:18.03#ibcon#about to read 6, iclass 17, count 2 2006.174.00:10:18.03#ibcon#read 6, iclass 17, count 2 2006.174.00:10:18.03#ibcon#end of sib2, iclass 17, count 2 2006.174.00:10:18.03#ibcon#*mode == 0, iclass 17, count 2 2006.174.00:10:18.03#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.174.00:10:18.03#ibcon#[27=AT07-04\r\n] 2006.174.00:10:18.03#ibcon#*before write, iclass 17, count 2 2006.174.00:10:18.03#ibcon#enter sib2, iclass 17, count 2 2006.174.00:10:18.03#ibcon#flushed, iclass 17, count 2 2006.174.00:10:18.03#ibcon#about to write, iclass 17, count 2 2006.174.00:10:18.03#ibcon#wrote, iclass 17, count 2 2006.174.00:10:18.03#ibcon#about to read 3, iclass 17, count 2 2006.174.00:10:18.06#ibcon#read 3, iclass 17, count 2 2006.174.00:10:18.06#ibcon#about to read 4, iclass 17, count 2 2006.174.00:10:18.06#ibcon#read 4, iclass 17, count 2 2006.174.00:10:18.06#ibcon#about to read 5, iclass 17, count 2 2006.174.00:10:18.06#ibcon#read 5, iclass 17, count 2 2006.174.00:10:18.06#ibcon#about to read 6, iclass 17, count 2 2006.174.00:10:18.06#ibcon#read 6, iclass 17, count 2 2006.174.00:10:18.06#ibcon#end of sib2, iclass 17, count 2 2006.174.00:10:18.06#ibcon#*after write, iclass 17, count 2 2006.174.00:10:18.06#ibcon#*before return 0, iclass 17, count 2 2006.174.00:10:18.06#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.174.00:10:18.06#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.174.00:10:18.06#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.174.00:10:18.06#ibcon#ireg 7 cls_cnt 0 2006.174.00:10:18.06#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.174.00:10:18.18#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.174.00:10:18.18#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.174.00:10:18.18#ibcon#enter wrdev, iclass 17, count 0 2006.174.00:10:18.18#ibcon#first serial, iclass 17, count 0 2006.174.00:10:18.18#ibcon#enter sib2, iclass 17, count 0 2006.174.00:10:18.18#ibcon#flushed, iclass 17, count 0 2006.174.00:10:18.18#ibcon#about to write, iclass 17, count 0 2006.174.00:10:18.18#ibcon#wrote, iclass 17, count 0 2006.174.00:10:18.18#ibcon#about to read 3, iclass 17, count 0 2006.174.00:10:18.20#ibcon#read 3, iclass 17, count 0 2006.174.00:10:18.20#ibcon#about to read 4, iclass 17, count 0 2006.174.00:10:18.20#ibcon#read 4, iclass 17, count 0 2006.174.00:10:18.20#ibcon#about to read 5, iclass 17, count 0 2006.174.00:10:18.20#ibcon#read 5, iclass 17, count 0 2006.174.00:10:18.20#ibcon#about to read 6, iclass 17, count 0 2006.174.00:10:18.20#ibcon#read 6, iclass 17, count 0 2006.174.00:10:18.20#ibcon#end of sib2, iclass 17, count 0 2006.174.00:10:18.20#ibcon#*mode == 0, iclass 17, count 0 2006.174.00:10:18.20#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.174.00:10:18.20#ibcon#[27=USB\r\n] 2006.174.00:10:18.20#ibcon#*before write, iclass 17, count 0 2006.174.00:10:18.20#ibcon#enter sib2, iclass 17, count 0 2006.174.00:10:18.20#ibcon#flushed, iclass 17, count 0 2006.174.00:10:18.20#ibcon#about to write, iclass 17, count 0 2006.174.00:10:18.20#ibcon#wrote, iclass 17, count 0 2006.174.00:10:18.20#ibcon#about to read 3, iclass 17, count 0 2006.174.00:10:18.23#ibcon#read 3, iclass 17, count 0 2006.174.00:10:18.23#ibcon#about to read 4, iclass 17, count 0 2006.174.00:10:18.23#ibcon#read 4, iclass 17, count 0 2006.174.00:10:18.23#ibcon#about to read 5, iclass 17, count 0 2006.174.00:10:18.23#ibcon#read 5, iclass 17, count 0 2006.174.00:10:18.23#ibcon#about to read 6, iclass 17, count 0 2006.174.00:10:18.23#ibcon#read 6, iclass 17, count 0 2006.174.00:10:18.23#ibcon#end of sib2, iclass 17, count 0 2006.174.00:10:18.23#ibcon#*after write, iclass 17, count 0 2006.174.00:10:18.23#ibcon#*before return 0, iclass 17, count 0 2006.174.00:10:18.23#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.174.00:10:18.23#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.174.00:10:18.23#ibcon#about to clear, iclass 17 cls_cnt 0 2006.174.00:10:18.23#ibcon#cleared, iclass 17 cls_cnt 0 2006.174.00:10:18.23$vck44/vblo=8,744.99 2006.174.00:10:18.23#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.174.00:10:18.23#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.174.00:10:18.23#ibcon#ireg 17 cls_cnt 0 2006.174.00:10:18.23#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.174.00:10:18.23#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.174.00:10:18.23#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.174.00:10:18.23#ibcon#enter wrdev, iclass 19, count 0 2006.174.00:10:18.23#ibcon#first serial, iclass 19, count 0 2006.174.00:10:18.23#ibcon#enter sib2, iclass 19, count 0 2006.174.00:10:18.23#ibcon#flushed, iclass 19, count 0 2006.174.00:10:18.23#ibcon#about to write, iclass 19, count 0 2006.174.00:10:18.23#ibcon#wrote, iclass 19, count 0 2006.174.00:10:18.23#ibcon#about to read 3, iclass 19, count 0 2006.174.00:10:18.25#ibcon#read 3, iclass 19, count 0 2006.174.00:10:18.25#ibcon#about to read 4, iclass 19, count 0 2006.174.00:10:18.25#ibcon#read 4, iclass 19, count 0 2006.174.00:10:18.25#ibcon#about to read 5, iclass 19, count 0 2006.174.00:10:18.25#ibcon#read 5, iclass 19, count 0 2006.174.00:10:18.25#ibcon#about to read 6, iclass 19, count 0 2006.174.00:10:18.25#ibcon#read 6, iclass 19, count 0 2006.174.00:10:18.25#ibcon#end of sib2, iclass 19, count 0 2006.174.00:10:18.25#ibcon#*mode == 0, iclass 19, count 0 2006.174.00:10:18.25#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.174.00:10:18.25#ibcon#[28=FRQ=08,744.99\r\n] 2006.174.00:10:18.25#ibcon#*before write, iclass 19, count 0 2006.174.00:10:18.25#ibcon#enter sib2, iclass 19, count 0 2006.174.00:10:18.25#ibcon#flushed, iclass 19, count 0 2006.174.00:10:18.25#ibcon#about to write, iclass 19, count 0 2006.174.00:10:18.25#ibcon#wrote, iclass 19, count 0 2006.174.00:10:18.25#ibcon#about to read 3, iclass 19, count 0 2006.174.00:10:18.29#ibcon#read 3, iclass 19, count 0 2006.174.00:10:18.29#ibcon#about to read 4, iclass 19, count 0 2006.174.00:10:18.29#ibcon#read 4, iclass 19, count 0 2006.174.00:10:18.29#ibcon#about to read 5, iclass 19, count 0 2006.174.00:10:18.29#ibcon#read 5, iclass 19, count 0 2006.174.00:10:18.29#ibcon#about to read 6, iclass 19, count 0 2006.174.00:10:18.29#ibcon#read 6, iclass 19, count 0 2006.174.00:10:18.29#ibcon#end of sib2, iclass 19, count 0 2006.174.00:10:18.29#ibcon#*after write, iclass 19, count 0 2006.174.00:10:18.29#ibcon#*before return 0, iclass 19, count 0 2006.174.00:10:18.29#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.174.00:10:18.29#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.174.00:10:18.29#ibcon#about to clear, iclass 19 cls_cnt 0 2006.174.00:10:18.29#ibcon#cleared, iclass 19 cls_cnt 0 2006.174.00:10:18.29$vck44/vb=8,4 2006.174.00:10:18.29#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.174.00:10:18.29#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.174.00:10:18.29#ibcon#ireg 11 cls_cnt 2 2006.174.00:10:18.29#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.174.00:10:18.35#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.174.00:10:18.35#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.174.00:10:18.35#ibcon#enter wrdev, iclass 21, count 2 2006.174.00:10:18.35#ibcon#first serial, iclass 21, count 2 2006.174.00:10:18.35#ibcon#enter sib2, iclass 21, count 2 2006.174.00:10:18.35#ibcon#flushed, iclass 21, count 2 2006.174.00:10:18.35#ibcon#about to write, iclass 21, count 2 2006.174.00:10:18.35#ibcon#wrote, iclass 21, count 2 2006.174.00:10:18.35#ibcon#about to read 3, iclass 21, count 2 2006.174.00:10:18.37#ibcon#read 3, iclass 21, count 2 2006.174.00:10:18.37#ibcon#about to read 4, iclass 21, count 2 2006.174.00:10:18.37#ibcon#read 4, iclass 21, count 2 2006.174.00:10:18.37#ibcon#about to read 5, iclass 21, count 2 2006.174.00:10:18.37#ibcon#read 5, iclass 21, count 2 2006.174.00:10:18.37#ibcon#about to read 6, iclass 21, count 2 2006.174.00:10:18.37#ibcon#read 6, iclass 21, count 2 2006.174.00:10:18.37#ibcon#end of sib2, iclass 21, count 2 2006.174.00:10:18.37#ibcon#*mode == 0, iclass 21, count 2 2006.174.00:10:18.37#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.174.00:10:18.37#ibcon#[27=AT08-04\r\n] 2006.174.00:10:18.37#ibcon#*before write, iclass 21, count 2 2006.174.00:10:18.37#ibcon#enter sib2, iclass 21, count 2 2006.174.00:10:18.37#ibcon#flushed, iclass 21, count 2 2006.174.00:10:18.37#ibcon#about to write, iclass 21, count 2 2006.174.00:10:18.37#ibcon#wrote, iclass 21, count 2 2006.174.00:10:18.37#ibcon#about to read 3, iclass 21, count 2 2006.174.00:10:18.40#ibcon#read 3, iclass 21, count 2 2006.174.00:10:18.40#ibcon#about to read 4, iclass 21, count 2 2006.174.00:10:18.40#ibcon#read 4, iclass 21, count 2 2006.174.00:10:18.40#ibcon#about to read 5, iclass 21, count 2 2006.174.00:10:18.40#ibcon#read 5, iclass 21, count 2 2006.174.00:10:18.40#ibcon#about to read 6, iclass 21, count 2 2006.174.00:10:18.40#ibcon#read 6, iclass 21, count 2 2006.174.00:10:18.40#ibcon#end of sib2, iclass 21, count 2 2006.174.00:10:18.40#ibcon#*after write, iclass 21, count 2 2006.174.00:10:18.40#ibcon#*before return 0, iclass 21, count 2 2006.174.00:10:18.40#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.174.00:10:18.40#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.174.00:10:18.40#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.174.00:10:18.40#ibcon#ireg 7 cls_cnt 0 2006.174.00:10:18.40#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.174.00:10:18.52#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.174.00:10:18.52#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.174.00:10:18.52#ibcon#enter wrdev, iclass 21, count 0 2006.174.00:10:18.52#ibcon#first serial, iclass 21, count 0 2006.174.00:10:18.52#ibcon#enter sib2, iclass 21, count 0 2006.174.00:10:18.52#ibcon#flushed, iclass 21, count 0 2006.174.00:10:18.52#ibcon#about to write, iclass 21, count 0 2006.174.00:10:18.52#ibcon#wrote, iclass 21, count 0 2006.174.00:10:18.52#ibcon#about to read 3, iclass 21, count 0 2006.174.00:10:18.54#ibcon#read 3, iclass 21, count 0 2006.174.00:10:18.54#ibcon#about to read 4, iclass 21, count 0 2006.174.00:10:18.54#ibcon#read 4, iclass 21, count 0 2006.174.00:10:18.54#ibcon#about to read 5, iclass 21, count 0 2006.174.00:10:18.54#ibcon#read 5, iclass 21, count 0 2006.174.00:10:18.54#ibcon#about to read 6, iclass 21, count 0 2006.174.00:10:18.54#ibcon#read 6, iclass 21, count 0 2006.174.00:10:18.54#ibcon#end of sib2, iclass 21, count 0 2006.174.00:10:18.54#ibcon#*mode == 0, iclass 21, count 0 2006.174.00:10:18.54#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.174.00:10:18.54#ibcon#[27=USB\r\n] 2006.174.00:10:18.54#ibcon#*before write, iclass 21, count 0 2006.174.00:10:18.54#ibcon#enter sib2, iclass 21, count 0 2006.174.00:10:18.54#ibcon#flushed, iclass 21, count 0 2006.174.00:10:18.54#ibcon#about to write, iclass 21, count 0 2006.174.00:10:18.54#ibcon#wrote, iclass 21, count 0 2006.174.00:10:18.54#ibcon#about to read 3, iclass 21, count 0 2006.174.00:10:18.57#ibcon#read 3, iclass 21, count 0 2006.174.00:10:18.57#ibcon#about to read 4, iclass 21, count 0 2006.174.00:10:18.57#ibcon#read 4, iclass 21, count 0 2006.174.00:10:18.57#ibcon#about to read 5, iclass 21, count 0 2006.174.00:10:18.57#ibcon#read 5, iclass 21, count 0 2006.174.00:10:18.57#ibcon#about to read 6, iclass 21, count 0 2006.174.00:10:18.57#ibcon#read 6, iclass 21, count 0 2006.174.00:10:18.57#ibcon#end of sib2, iclass 21, count 0 2006.174.00:10:18.57#ibcon#*after write, iclass 21, count 0 2006.174.00:10:18.57#ibcon#*before return 0, iclass 21, count 0 2006.174.00:10:18.57#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.174.00:10:18.57#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.174.00:10:18.57#ibcon#about to clear, iclass 21 cls_cnt 0 2006.174.00:10:18.57#ibcon#cleared, iclass 21 cls_cnt 0 2006.174.00:10:18.57$vck44/vabw=wide 2006.174.00:10:18.57#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.174.00:10:18.57#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.174.00:10:18.57#ibcon#ireg 8 cls_cnt 0 2006.174.00:10:18.57#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.174.00:10:18.57#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.174.00:10:18.57#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.174.00:10:18.57#ibcon#enter wrdev, iclass 23, count 0 2006.174.00:10:18.57#ibcon#first serial, iclass 23, count 0 2006.174.00:10:18.57#ibcon#enter sib2, iclass 23, count 0 2006.174.00:10:18.57#ibcon#flushed, iclass 23, count 0 2006.174.00:10:18.57#ibcon#about to write, iclass 23, count 0 2006.174.00:10:18.57#ibcon#wrote, iclass 23, count 0 2006.174.00:10:18.57#ibcon#about to read 3, iclass 23, count 0 2006.174.00:10:18.59#ibcon#read 3, iclass 23, count 0 2006.174.00:10:18.59#ibcon#about to read 4, iclass 23, count 0 2006.174.00:10:18.59#ibcon#read 4, iclass 23, count 0 2006.174.00:10:18.59#ibcon#about to read 5, iclass 23, count 0 2006.174.00:10:18.59#ibcon#read 5, iclass 23, count 0 2006.174.00:10:18.59#ibcon#about to read 6, iclass 23, count 0 2006.174.00:10:18.59#ibcon#read 6, iclass 23, count 0 2006.174.00:10:18.59#ibcon#end of sib2, iclass 23, count 0 2006.174.00:10:18.59#ibcon#*mode == 0, iclass 23, count 0 2006.174.00:10:18.59#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.174.00:10:18.59#ibcon#[25=BW32\r\n] 2006.174.00:10:18.59#ibcon#*before write, iclass 23, count 0 2006.174.00:10:18.59#ibcon#enter sib2, iclass 23, count 0 2006.174.00:10:18.59#ibcon#flushed, iclass 23, count 0 2006.174.00:10:18.59#ibcon#about to write, iclass 23, count 0 2006.174.00:10:18.59#ibcon#wrote, iclass 23, count 0 2006.174.00:10:18.59#ibcon#about to read 3, iclass 23, count 0 2006.174.00:10:18.62#ibcon#read 3, iclass 23, count 0 2006.174.00:10:18.62#ibcon#about to read 4, iclass 23, count 0 2006.174.00:10:18.62#ibcon#read 4, iclass 23, count 0 2006.174.00:10:18.62#ibcon#about to read 5, iclass 23, count 0 2006.174.00:10:18.62#ibcon#read 5, iclass 23, count 0 2006.174.00:10:18.62#ibcon#about to read 6, iclass 23, count 0 2006.174.00:10:18.62#ibcon#read 6, iclass 23, count 0 2006.174.00:10:18.62#ibcon#end of sib2, iclass 23, count 0 2006.174.00:10:18.62#ibcon#*after write, iclass 23, count 0 2006.174.00:10:18.62#ibcon#*before return 0, iclass 23, count 0 2006.174.00:10:18.62#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.174.00:10:18.62#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.174.00:10:18.62#ibcon#about to clear, iclass 23 cls_cnt 0 2006.174.00:10:18.62#ibcon#cleared, iclass 23 cls_cnt 0 2006.174.00:10:18.62$vck44/vbbw=wide 2006.174.00:10:18.62#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.174.00:10:18.62#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.174.00:10:18.62#ibcon#ireg 8 cls_cnt 0 2006.174.00:10:18.62#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.174.00:10:18.69#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.174.00:10:18.69#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.174.00:10:18.69#ibcon#enter wrdev, iclass 25, count 0 2006.174.00:10:18.69#ibcon#first serial, iclass 25, count 0 2006.174.00:10:18.69#ibcon#enter sib2, iclass 25, count 0 2006.174.00:10:18.69#ibcon#flushed, iclass 25, count 0 2006.174.00:10:18.69#ibcon#about to write, iclass 25, count 0 2006.174.00:10:18.69#ibcon#wrote, iclass 25, count 0 2006.174.00:10:18.69#ibcon#about to read 3, iclass 25, count 0 2006.174.00:10:18.71#ibcon#read 3, iclass 25, count 0 2006.174.00:10:18.71#ibcon#about to read 4, iclass 25, count 0 2006.174.00:10:18.71#ibcon#read 4, iclass 25, count 0 2006.174.00:10:18.71#ibcon#about to read 5, iclass 25, count 0 2006.174.00:10:18.71#ibcon#read 5, iclass 25, count 0 2006.174.00:10:18.71#ibcon#about to read 6, iclass 25, count 0 2006.174.00:10:18.71#ibcon#read 6, iclass 25, count 0 2006.174.00:10:18.71#ibcon#end of sib2, iclass 25, count 0 2006.174.00:10:18.71#ibcon#*mode == 0, iclass 25, count 0 2006.174.00:10:18.71#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.174.00:10:18.71#ibcon#[27=BW32\r\n] 2006.174.00:10:18.71#ibcon#*before write, iclass 25, count 0 2006.174.00:10:18.71#ibcon#enter sib2, iclass 25, count 0 2006.174.00:10:18.71#ibcon#flushed, iclass 25, count 0 2006.174.00:10:18.71#ibcon#about to write, iclass 25, count 0 2006.174.00:10:18.71#ibcon#wrote, iclass 25, count 0 2006.174.00:10:18.71#ibcon#about to read 3, iclass 25, count 0 2006.174.00:10:18.74#ibcon#read 3, iclass 25, count 0 2006.174.00:10:18.74#ibcon#about to read 4, iclass 25, count 0 2006.174.00:10:18.74#ibcon#read 4, iclass 25, count 0 2006.174.00:10:18.74#ibcon#about to read 5, iclass 25, count 0 2006.174.00:10:18.74#ibcon#read 5, iclass 25, count 0 2006.174.00:10:18.74#ibcon#about to read 6, iclass 25, count 0 2006.174.00:10:18.74#ibcon#read 6, iclass 25, count 0 2006.174.00:10:18.74#ibcon#end of sib2, iclass 25, count 0 2006.174.00:10:18.74#ibcon#*after write, iclass 25, count 0 2006.174.00:10:18.74#ibcon#*before return 0, iclass 25, count 0 2006.174.00:10:18.74#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.174.00:10:18.74#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.174.00:10:18.74#ibcon#about to clear, iclass 25 cls_cnt 0 2006.174.00:10:18.74#ibcon#cleared, iclass 25 cls_cnt 0 2006.174.00:10:18.74$setupk4/ifdk4 2006.174.00:10:18.74$ifdk4/lo= 2006.174.00:10:18.74$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.174.00:10:18.74$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.174.00:10:18.74$ifdk4/patch= 2006.174.00:10:18.74$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.174.00:10:18.74$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.174.00:10:18.74$setupk4/!*+20s 2006.174.00:10:22.71#abcon#<5=/12 0.7 2.3 24.28 841003.5\r\n> 2006.174.00:10:22.73#abcon#{5=INTERFACE CLEAR} 2006.174.00:10:22.79#abcon#[5=S1D000X0/0*\r\n] 2006.174.00:10:32.88#abcon#<5=/12 0.7 2.3 24.28 831003.5\r\n> 2006.174.00:10:32.90#abcon#{5=INTERFACE CLEAR} 2006.174.00:10:32.96#abcon#[5=S1D000X0/0*\r\n] 2006.174.00:10:33.24$setupk4/"tpicd 2006.174.00:10:33.24$setupk4/echo=off 2006.174.00:10:33.24$setupk4/xlog=off 2006.174.00:10:33.24:!2006.174.00:25:49 2006.174.00:10:52.14#trakl#Source acquired 2006.174.00:10:54.14#flagr#flagr/antenna,acquired 2006.174.00:25:49.00:preob 2006.174.00:25:49.14/onsource/TRACKING 2006.174.00:25:49.14:!2006.174.00:25:59 2006.174.00:25:59.00:"tape 2006.174.00:25:59.00:"st=record 2006.174.00:25:59.00:data_valid=on 2006.174.00:25:59.00:midob 2006.174.00:26:00.14/onsource/TRACKING 2006.174.00:26:00.14/wx/24.42,1003.3,83 2006.174.00:26:00.24/cable/+6.5049E-03 2006.174.00:26:01.33/va/01,07,usb,yes,37,39 2006.174.00:26:01.33/va/02,06,usb,yes,37,37 2006.174.00:26:01.33/va/03,05,usb,yes,46,48 2006.174.00:26:01.33/va/04,06,usb,yes,37,39 2006.174.00:26:01.33/va/05,04,usb,yes,29,30 2006.174.00:26:01.33/va/06,03,usb,yes,41,41 2006.174.00:26:01.33/va/07,04,usb,yes,33,34 2006.174.00:26:01.33/va/08,04,usb,yes,28,34 2006.174.00:26:01.56/valo/01,524.99,yes,locked 2006.174.00:26:01.56/valo/02,534.99,yes,locked 2006.174.00:26:01.56/valo/03,564.99,yes,locked 2006.174.00:26:01.56/valo/04,624.99,yes,locked 2006.174.00:26:01.56/valo/05,734.99,yes,locked 2006.174.00:26:01.56/valo/06,814.99,yes,locked 2006.174.00:26:01.56/valo/07,864.99,yes,locked 2006.174.00:26:01.56/valo/08,884.99,yes,locked 2006.174.00:26:02.65/vb/01,04,usb,yes,30,28 2006.174.00:26:02.65/vb/02,04,usb,yes,33,32 2006.174.00:26:02.65/vb/03,04,usb,yes,30,33 2006.174.00:26:02.65/vb/04,04,usb,yes,34,33 2006.174.00:26:02.65/vb/05,04,usb,yes,26,29 2006.174.00:26:02.65/vb/06,04,usb,yes,31,27 2006.174.00:26:02.65/vb/07,04,usb,yes,31,30 2006.174.00:26:02.65/vb/08,04,usb,yes,28,32 2006.174.00:26:02.88/vblo/01,629.99,yes,locked 2006.174.00:26:02.88/vblo/02,634.99,yes,locked 2006.174.00:26:02.88/vblo/03,649.99,yes,locked 2006.174.00:26:02.88/vblo/04,679.99,yes,locked 2006.174.00:26:02.88/vblo/05,709.99,yes,locked 2006.174.00:26:02.88/vblo/06,719.99,yes,locked 2006.174.00:26:02.88/vblo/07,734.99,yes,locked 2006.174.00:26:02.88/vblo/08,744.99,yes,locked 2006.174.00:26:03.03/vabw/8 2006.174.00:26:03.18/vbbw/8 2006.174.00:26:03.27/xfe/off,on,15.2 2006.174.00:26:03.67/ifatt/23,28,28,28 2006.174.00:26:04.07/fmout-gps/S +3.93E-07 2006.174.00:26:04.12:!2006.174.00:28:39 2006.174.00:28:39.01:data_valid=off 2006.174.00:28:39.02:"et 2006.174.00:28:39.02:!+3s 2006.174.00:28:42.03:"tape 2006.174.00:28:42.04:postob 2006.174.00:28:42.23/cable/+6.5060E-03 2006.174.00:28:42.24/wx/24.46,1003.3,84 2006.174.00:28:42.29/fmout-gps/S +3.92E-07 2006.174.00:28:42.30:scan_name=174-0037,jd0606,220 2006.174.00:28:42.30:source=0059+581,010245.76,582411.1,2000.0,ccw 2006.174.00:28:44.14#flagr#flagr/antenna,new-source 2006.174.00:28:44.15:checkk5 2006.174.00:28:44.57/chk_autoobs//k5ts1/ autoobs is running! 2006.174.00:28:44.97/chk_autoobs//k5ts2/ autoobs is running! 2006.174.00:28:45.38/chk_autoobs//k5ts3/ autoobs is running! 2006.174.00:28:45.78/chk_autoobs//k5ts4/ autoobs is running! 2006.174.00:28:46.17/chk_obsdata//k5ts1/T1740025??a.dat file size is correct (nominal:640MB, actual:640MB). 2006.174.00:28:46.57/chk_obsdata//k5ts2/T1740025??b.dat file size is correct (nominal:640MB, actual:640MB). 2006.174.00:28:46.97/chk_obsdata//k5ts3/T1740025??c.dat file size is correct (nominal:640MB, actual:640MB). 2006.174.00:28:47.38/chk_obsdata//k5ts4/T1740025??d.dat file size is correct (nominal:640MB, actual:640MB). 2006.174.00:28:48.11/k5log//k5ts1_log_newline 2006.174.00:28:48.82/k5log//k5ts2_log_newline 2006.174.00:28:49.53/k5log//k5ts3_log_newline 2006.174.00:28:50.24/k5log//k5ts4_log_newline 2006.174.00:28:50.26/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.174.00:28:50.26:setupk4=1 2006.174.00:28:50.26$setupk4/echo=on 2006.174.00:28:50.26$setupk4/pcalon 2006.174.00:28:50.26$pcalon/"no phase cal control is implemented here 2006.174.00:28:50.26$setupk4/"tpicd=stop 2006.174.00:28:50.26$setupk4/"rec=synch_on 2006.174.00:28:50.26$setupk4/"rec_mode=128 2006.174.00:28:50.26$setupk4/!* 2006.174.00:28:50.26$setupk4/recpk4 2006.174.00:28:50.26$recpk4/recpatch= 2006.174.00:28:50.26$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.174.00:28:50.26$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.174.00:28:50.27$setupk4/vck44 2006.174.00:28:50.27$vck44/valo=1,524.99 2006.174.00:28:50.27#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.174.00:28:50.27#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.174.00:28:50.27#ibcon#ireg 17 cls_cnt 0 2006.174.00:28:50.27#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.174.00:28:50.27#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.174.00:28:50.27#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.174.00:28:50.27#ibcon#enter wrdev, iclass 29, count 0 2006.174.00:28:50.27#ibcon#first serial, iclass 29, count 0 2006.174.00:28:50.27#ibcon#enter sib2, iclass 29, count 0 2006.174.00:28:50.27#ibcon#flushed, iclass 29, count 0 2006.174.00:28:50.27#ibcon#about to write, iclass 29, count 0 2006.174.00:28:50.27#ibcon#wrote, iclass 29, count 0 2006.174.00:28:50.27#ibcon#about to read 3, iclass 29, count 0 2006.174.00:28:50.28#ibcon#read 3, iclass 29, count 0 2006.174.00:28:50.28#ibcon#about to read 4, iclass 29, count 0 2006.174.00:28:50.28#ibcon#read 4, iclass 29, count 0 2006.174.00:28:50.28#ibcon#about to read 5, iclass 29, count 0 2006.174.00:28:50.28#ibcon#read 5, iclass 29, count 0 2006.174.00:28:50.28#ibcon#about to read 6, iclass 29, count 0 2006.174.00:28:50.28#ibcon#read 6, iclass 29, count 0 2006.174.00:28:50.28#ibcon#end of sib2, iclass 29, count 0 2006.174.00:28:50.28#ibcon#*mode == 0, iclass 29, count 0 2006.174.00:28:50.28#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.174.00:28:50.28#ibcon#[26=FRQ=01,524.99\r\n] 2006.174.00:28:50.28#ibcon#*before write, iclass 29, count 0 2006.174.00:28:50.28#ibcon#enter sib2, iclass 29, count 0 2006.174.00:28:50.28#ibcon#flushed, iclass 29, count 0 2006.174.00:28:50.28#ibcon#about to write, iclass 29, count 0 2006.174.00:28:50.28#ibcon#wrote, iclass 29, count 0 2006.174.00:28:50.28#ibcon#about to read 3, iclass 29, count 0 2006.174.00:28:50.33#ibcon#read 3, iclass 29, count 0 2006.174.00:28:50.33#ibcon#about to read 4, iclass 29, count 0 2006.174.00:28:50.33#ibcon#read 4, iclass 29, count 0 2006.174.00:28:50.33#ibcon#about to read 5, iclass 29, count 0 2006.174.00:28:50.33#ibcon#read 5, iclass 29, count 0 2006.174.00:28:50.33#ibcon#about to read 6, iclass 29, count 0 2006.174.00:28:50.33#ibcon#read 6, iclass 29, count 0 2006.174.00:28:50.33#ibcon#end of sib2, iclass 29, count 0 2006.174.00:28:50.33#ibcon#*after write, iclass 29, count 0 2006.174.00:28:50.33#ibcon#*before return 0, iclass 29, count 0 2006.174.00:28:50.33#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.174.00:28:50.33#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.174.00:28:50.33#ibcon#about to clear, iclass 29 cls_cnt 0 2006.174.00:28:50.33#ibcon#cleared, iclass 29 cls_cnt 0 2006.174.00:28:50.33$vck44/va=1,7 2006.174.00:28:50.33#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.174.00:28:50.33#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.174.00:28:50.33#ibcon#ireg 11 cls_cnt 2 2006.174.00:28:50.33#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.174.00:28:50.33#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.174.00:28:50.33#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.174.00:28:50.33#ibcon#enter wrdev, iclass 31, count 2 2006.174.00:28:50.33#ibcon#first serial, iclass 31, count 2 2006.174.00:28:50.33#ibcon#enter sib2, iclass 31, count 2 2006.174.00:28:50.33#ibcon#flushed, iclass 31, count 2 2006.174.00:28:50.33#ibcon#about to write, iclass 31, count 2 2006.174.00:28:50.33#ibcon#wrote, iclass 31, count 2 2006.174.00:28:50.33#ibcon#about to read 3, iclass 31, count 2 2006.174.00:28:50.35#ibcon#read 3, iclass 31, count 2 2006.174.00:28:50.35#ibcon#about to read 4, iclass 31, count 2 2006.174.00:28:50.35#ibcon#read 4, iclass 31, count 2 2006.174.00:28:50.35#ibcon#about to read 5, iclass 31, count 2 2006.174.00:28:50.35#ibcon#read 5, iclass 31, count 2 2006.174.00:28:50.35#ibcon#about to read 6, iclass 31, count 2 2006.174.00:28:50.35#ibcon#read 6, iclass 31, count 2 2006.174.00:28:50.35#ibcon#end of sib2, iclass 31, count 2 2006.174.00:28:50.35#ibcon#*mode == 0, iclass 31, count 2 2006.174.00:28:50.35#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.174.00:28:50.35#ibcon#[25=AT01-07\r\n] 2006.174.00:28:50.35#ibcon#*before write, iclass 31, count 2 2006.174.00:28:50.35#ibcon#enter sib2, iclass 31, count 2 2006.174.00:28:50.35#ibcon#flushed, iclass 31, count 2 2006.174.00:28:50.35#ibcon#about to write, iclass 31, count 2 2006.174.00:28:50.35#ibcon#wrote, iclass 31, count 2 2006.174.00:28:50.35#ibcon#about to read 3, iclass 31, count 2 2006.174.00:28:50.38#ibcon#read 3, iclass 31, count 2 2006.174.00:28:50.38#ibcon#about to read 4, iclass 31, count 2 2006.174.00:28:50.38#ibcon#read 4, iclass 31, count 2 2006.174.00:28:50.38#ibcon#about to read 5, iclass 31, count 2 2006.174.00:28:50.38#ibcon#read 5, iclass 31, count 2 2006.174.00:28:50.38#ibcon#about to read 6, iclass 31, count 2 2006.174.00:28:50.38#ibcon#read 6, iclass 31, count 2 2006.174.00:28:50.38#ibcon#end of sib2, iclass 31, count 2 2006.174.00:28:50.38#ibcon#*after write, iclass 31, count 2 2006.174.00:28:50.38#ibcon#*before return 0, iclass 31, count 2 2006.174.00:28:50.38#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.174.00:28:50.38#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.174.00:28:50.38#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.174.00:28:50.38#ibcon#ireg 7 cls_cnt 0 2006.174.00:28:50.38#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.174.00:28:50.50#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.174.00:28:50.50#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.174.00:28:50.50#ibcon#enter wrdev, iclass 31, count 0 2006.174.00:28:50.50#ibcon#first serial, iclass 31, count 0 2006.174.00:28:50.50#ibcon#enter sib2, iclass 31, count 0 2006.174.00:28:50.50#ibcon#flushed, iclass 31, count 0 2006.174.00:28:50.50#ibcon#about to write, iclass 31, count 0 2006.174.00:28:50.50#ibcon#wrote, iclass 31, count 0 2006.174.00:28:50.50#ibcon#about to read 3, iclass 31, count 0 2006.174.00:28:50.52#ibcon#read 3, iclass 31, count 0 2006.174.00:28:50.52#ibcon#about to read 4, iclass 31, count 0 2006.174.00:28:50.52#ibcon#read 4, iclass 31, count 0 2006.174.00:28:50.52#ibcon#about to read 5, iclass 31, count 0 2006.174.00:28:50.52#ibcon#read 5, iclass 31, count 0 2006.174.00:28:50.52#ibcon#about to read 6, iclass 31, count 0 2006.174.00:28:50.52#ibcon#read 6, iclass 31, count 0 2006.174.00:28:50.52#ibcon#end of sib2, iclass 31, count 0 2006.174.00:28:50.52#ibcon#*mode == 0, iclass 31, count 0 2006.174.00:28:50.52#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.174.00:28:50.52#ibcon#[25=USB\r\n] 2006.174.00:28:50.52#ibcon#*before write, iclass 31, count 0 2006.174.00:28:50.52#ibcon#enter sib2, iclass 31, count 0 2006.174.00:28:50.52#ibcon#flushed, iclass 31, count 0 2006.174.00:28:50.52#ibcon#about to write, iclass 31, count 0 2006.174.00:28:50.52#ibcon#wrote, iclass 31, count 0 2006.174.00:28:50.52#ibcon#about to read 3, iclass 31, count 0 2006.174.00:28:50.55#ibcon#read 3, iclass 31, count 0 2006.174.00:28:50.55#ibcon#about to read 4, iclass 31, count 0 2006.174.00:28:50.55#ibcon#read 4, iclass 31, count 0 2006.174.00:28:50.55#ibcon#about to read 5, iclass 31, count 0 2006.174.00:28:50.55#ibcon#read 5, iclass 31, count 0 2006.174.00:28:50.55#ibcon#about to read 6, iclass 31, count 0 2006.174.00:28:50.55#ibcon#read 6, iclass 31, count 0 2006.174.00:28:50.55#ibcon#end of sib2, iclass 31, count 0 2006.174.00:28:50.55#ibcon#*after write, iclass 31, count 0 2006.174.00:28:50.55#ibcon#*before return 0, iclass 31, count 0 2006.174.00:28:50.55#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.174.00:28:50.55#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.174.00:28:50.55#ibcon#about to clear, iclass 31 cls_cnt 0 2006.174.00:28:50.55#ibcon#cleared, iclass 31 cls_cnt 0 2006.174.00:28:50.55$vck44/valo=2,534.99 2006.174.00:28:50.55#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.174.00:28:50.55#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.174.00:28:50.55#ibcon#ireg 17 cls_cnt 0 2006.174.00:28:50.55#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.174.00:28:50.55#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.174.00:28:50.55#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.174.00:28:50.55#ibcon#enter wrdev, iclass 33, count 0 2006.174.00:28:50.55#ibcon#first serial, iclass 33, count 0 2006.174.00:28:50.55#ibcon#enter sib2, iclass 33, count 0 2006.174.00:28:50.55#ibcon#flushed, iclass 33, count 0 2006.174.00:28:50.55#ibcon#about to write, iclass 33, count 0 2006.174.00:28:50.55#ibcon#wrote, iclass 33, count 0 2006.174.00:28:50.55#ibcon#about to read 3, iclass 33, count 0 2006.174.00:28:50.57#ibcon#read 3, iclass 33, count 0 2006.174.00:28:50.57#ibcon#about to read 4, iclass 33, count 0 2006.174.00:28:50.57#ibcon#read 4, iclass 33, count 0 2006.174.00:28:50.57#ibcon#about to read 5, iclass 33, count 0 2006.174.00:28:50.57#ibcon#read 5, iclass 33, count 0 2006.174.00:28:50.57#ibcon#about to read 6, iclass 33, count 0 2006.174.00:28:50.57#ibcon#read 6, iclass 33, count 0 2006.174.00:28:50.57#ibcon#end of sib2, iclass 33, count 0 2006.174.00:28:50.57#ibcon#*mode == 0, iclass 33, count 0 2006.174.00:28:50.57#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.174.00:28:50.57#ibcon#[26=FRQ=02,534.99\r\n] 2006.174.00:28:50.57#ibcon#*before write, iclass 33, count 0 2006.174.00:28:50.57#ibcon#enter sib2, iclass 33, count 0 2006.174.00:28:50.57#ibcon#flushed, iclass 33, count 0 2006.174.00:28:50.57#ibcon#about to write, iclass 33, count 0 2006.174.00:28:50.57#ibcon#wrote, iclass 33, count 0 2006.174.00:28:50.57#ibcon#about to read 3, iclass 33, count 0 2006.174.00:28:50.61#ibcon#read 3, iclass 33, count 0 2006.174.00:28:50.61#ibcon#about to read 4, iclass 33, count 0 2006.174.00:28:50.61#ibcon#read 4, iclass 33, count 0 2006.174.00:28:50.61#ibcon#about to read 5, iclass 33, count 0 2006.174.00:28:50.61#ibcon#read 5, iclass 33, count 0 2006.174.00:28:50.61#ibcon#about to read 6, iclass 33, count 0 2006.174.00:28:50.61#ibcon#read 6, iclass 33, count 0 2006.174.00:28:50.61#ibcon#end of sib2, iclass 33, count 0 2006.174.00:28:50.61#ibcon#*after write, iclass 33, count 0 2006.174.00:28:50.61#ibcon#*before return 0, iclass 33, count 0 2006.174.00:28:50.61#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.174.00:28:50.61#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.174.00:28:50.61#ibcon#about to clear, iclass 33 cls_cnt 0 2006.174.00:28:50.61#ibcon#cleared, iclass 33 cls_cnt 0 2006.174.00:28:50.61$vck44/va=2,6 2006.174.00:28:50.61#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.174.00:28:50.61#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.174.00:28:50.61#ibcon#ireg 11 cls_cnt 2 2006.174.00:28:50.61#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.174.00:28:50.67#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.174.00:28:50.67#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.174.00:28:50.67#ibcon#enter wrdev, iclass 35, count 2 2006.174.00:28:50.67#ibcon#first serial, iclass 35, count 2 2006.174.00:28:50.67#ibcon#enter sib2, iclass 35, count 2 2006.174.00:28:50.67#ibcon#flushed, iclass 35, count 2 2006.174.00:28:50.67#ibcon#about to write, iclass 35, count 2 2006.174.00:28:50.67#ibcon#wrote, iclass 35, count 2 2006.174.00:28:50.67#ibcon#about to read 3, iclass 35, count 2 2006.174.00:28:50.69#ibcon#read 3, iclass 35, count 2 2006.174.00:28:50.69#ibcon#about to read 4, iclass 35, count 2 2006.174.00:28:50.69#ibcon#read 4, iclass 35, count 2 2006.174.00:28:50.69#ibcon#about to read 5, iclass 35, count 2 2006.174.00:28:50.69#ibcon#read 5, iclass 35, count 2 2006.174.00:28:50.69#ibcon#about to read 6, iclass 35, count 2 2006.174.00:28:50.69#ibcon#read 6, iclass 35, count 2 2006.174.00:28:50.69#ibcon#end of sib2, iclass 35, count 2 2006.174.00:28:50.69#ibcon#*mode == 0, iclass 35, count 2 2006.174.00:28:50.69#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.174.00:28:50.69#ibcon#[25=AT02-06\r\n] 2006.174.00:28:50.69#ibcon#*before write, iclass 35, count 2 2006.174.00:28:50.69#ibcon#enter sib2, iclass 35, count 2 2006.174.00:28:50.69#ibcon#flushed, iclass 35, count 2 2006.174.00:28:50.69#ibcon#about to write, iclass 35, count 2 2006.174.00:28:50.69#ibcon#wrote, iclass 35, count 2 2006.174.00:28:50.69#ibcon#about to read 3, iclass 35, count 2 2006.174.00:28:50.72#ibcon#read 3, iclass 35, count 2 2006.174.00:28:50.72#ibcon#about to read 4, iclass 35, count 2 2006.174.00:28:50.72#ibcon#read 4, iclass 35, count 2 2006.174.00:28:50.72#ibcon#about to read 5, iclass 35, count 2 2006.174.00:28:50.72#ibcon#read 5, iclass 35, count 2 2006.174.00:28:50.72#ibcon#about to read 6, iclass 35, count 2 2006.174.00:28:50.72#ibcon#read 6, iclass 35, count 2 2006.174.00:28:50.72#ibcon#end of sib2, iclass 35, count 2 2006.174.00:28:50.72#ibcon#*after write, iclass 35, count 2 2006.174.00:28:50.72#ibcon#*before return 0, iclass 35, count 2 2006.174.00:28:50.72#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.174.00:28:50.72#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.174.00:28:50.72#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.174.00:28:50.72#ibcon#ireg 7 cls_cnt 0 2006.174.00:28:50.72#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.174.00:28:50.84#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.174.00:28:50.84#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.174.00:28:50.84#ibcon#enter wrdev, iclass 35, count 0 2006.174.00:28:50.84#ibcon#first serial, iclass 35, count 0 2006.174.00:28:50.84#ibcon#enter sib2, iclass 35, count 0 2006.174.00:28:50.84#ibcon#flushed, iclass 35, count 0 2006.174.00:28:50.84#ibcon#about to write, iclass 35, count 0 2006.174.00:28:50.84#ibcon#wrote, iclass 35, count 0 2006.174.00:28:50.84#ibcon#about to read 3, iclass 35, count 0 2006.174.00:28:50.86#ibcon#read 3, iclass 35, count 0 2006.174.00:28:50.86#ibcon#about to read 4, iclass 35, count 0 2006.174.00:28:50.86#ibcon#read 4, iclass 35, count 0 2006.174.00:28:50.86#ibcon#about to read 5, iclass 35, count 0 2006.174.00:28:50.86#ibcon#read 5, iclass 35, count 0 2006.174.00:28:50.86#ibcon#about to read 6, iclass 35, count 0 2006.174.00:28:50.86#ibcon#read 6, iclass 35, count 0 2006.174.00:28:50.86#ibcon#end of sib2, iclass 35, count 0 2006.174.00:28:50.86#ibcon#*mode == 0, iclass 35, count 0 2006.174.00:28:50.86#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.174.00:28:50.86#ibcon#[25=USB\r\n] 2006.174.00:28:50.86#ibcon#*before write, iclass 35, count 0 2006.174.00:28:50.86#ibcon#enter sib2, iclass 35, count 0 2006.174.00:28:50.86#ibcon#flushed, iclass 35, count 0 2006.174.00:28:50.86#ibcon#about to write, iclass 35, count 0 2006.174.00:28:50.86#ibcon#wrote, iclass 35, count 0 2006.174.00:28:50.86#ibcon#about to read 3, iclass 35, count 0 2006.174.00:28:50.89#ibcon#read 3, iclass 35, count 0 2006.174.00:28:50.89#ibcon#about to read 4, iclass 35, count 0 2006.174.00:28:50.89#ibcon#read 4, iclass 35, count 0 2006.174.00:28:50.89#ibcon#about to read 5, iclass 35, count 0 2006.174.00:28:50.89#ibcon#read 5, iclass 35, count 0 2006.174.00:28:50.89#ibcon#about to read 6, iclass 35, count 0 2006.174.00:28:50.89#ibcon#read 6, iclass 35, count 0 2006.174.00:28:50.89#ibcon#end of sib2, iclass 35, count 0 2006.174.00:28:50.89#ibcon#*after write, iclass 35, count 0 2006.174.00:28:50.89#ibcon#*before return 0, iclass 35, count 0 2006.174.00:28:50.89#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.174.00:28:50.89#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.174.00:28:50.89#ibcon#about to clear, iclass 35 cls_cnt 0 2006.174.00:28:50.89#ibcon#cleared, iclass 35 cls_cnt 0 2006.174.00:28:50.89$vck44/valo=3,564.99 2006.174.00:28:50.89#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.174.00:28:50.89#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.174.00:28:50.89#ibcon#ireg 17 cls_cnt 0 2006.174.00:28:50.89#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.174.00:28:50.89#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.174.00:28:50.89#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.174.00:28:50.89#ibcon#enter wrdev, iclass 37, count 0 2006.174.00:28:50.89#ibcon#first serial, iclass 37, count 0 2006.174.00:28:50.89#ibcon#enter sib2, iclass 37, count 0 2006.174.00:28:50.89#ibcon#flushed, iclass 37, count 0 2006.174.00:28:50.89#ibcon#about to write, iclass 37, count 0 2006.174.00:28:50.89#ibcon#wrote, iclass 37, count 0 2006.174.00:28:50.89#ibcon#about to read 3, iclass 37, count 0 2006.174.00:28:50.91#ibcon#read 3, iclass 37, count 0 2006.174.00:28:50.91#ibcon#about to read 4, iclass 37, count 0 2006.174.00:28:50.91#ibcon#read 4, iclass 37, count 0 2006.174.00:28:50.91#ibcon#about to read 5, iclass 37, count 0 2006.174.00:28:50.91#ibcon#read 5, iclass 37, count 0 2006.174.00:28:50.91#ibcon#about to read 6, iclass 37, count 0 2006.174.00:28:50.91#ibcon#read 6, iclass 37, count 0 2006.174.00:28:50.91#ibcon#end of sib2, iclass 37, count 0 2006.174.00:28:50.91#ibcon#*mode == 0, iclass 37, count 0 2006.174.00:28:50.91#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.174.00:28:50.91#ibcon#[26=FRQ=03,564.99\r\n] 2006.174.00:28:50.91#ibcon#*before write, iclass 37, count 0 2006.174.00:28:50.91#ibcon#enter sib2, iclass 37, count 0 2006.174.00:28:50.91#ibcon#flushed, iclass 37, count 0 2006.174.00:28:50.91#ibcon#about to write, iclass 37, count 0 2006.174.00:28:50.91#ibcon#wrote, iclass 37, count 0 2006.174.00:28:50.91#ibcon#about to read 3, iclass 37, count 0 2006.174.00:28:50.95#ibcon#read 3, iclass 37, count 0 2006.174.00:28:50.95#ibcon#about to read 4, iclass 37, count 0 2006.174.00:28:50.95#ibcon#read 4, iclass 37, count 0 2006.174.00:28:50.95#ibcon#about to read 5, iclass 37, count 0 2006.174.00:28:50.95#ibcon#read 5, iclass 37, count 0 2006.174.00:28:50.95#ibcon#about to read 6, iclass 37, count 0 2006.174.00:28:50.95#ibcon#read 6, iclass 37, count 0 2006.174.00:28:50.95#ibcon#end of sib2, iclass 37, count 0 2006.174.00:28:50.95#ibcon#*after write, iclass 37, count 0 2006.174.00:28:50.95#ibcon#*before return 0, iclass 37, count 0 2006.174.00:28:50.95#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.174.00:28:50.95#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.174.00:28:50.95#ibcon#about to clear, iclass 37 cls_cnt 0 2006.174.00:28:50.95#ibcon#cleared, iclass 37 cls_cnt 0 2006.174.00:28:50.95$vck44/va=3,5 2006.174.00:28:50.95#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.174.00:28:50.95#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.174.00:28:50.95#ibcon#ireg 11 cls_cnt 2 2006.174.00:28:50.95#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.174.00:28:51.01#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.174.00:28:51.01#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.174.00:28:51.01#ibcon#enter wrdev, iclass 39, count 2 2006.174.00:28:51.01#ibcon#first serial, iclass 39, count 2 2006.174.00:28:51.01#ibcon#enter sib2, iclass 39, count 2 2006.174.00:28:51.01#ibcon#flushed, iclass 39, count 2 2006.174.00:28:51.01#ibcon#about to write, iclass 39, count 2 2006.174.00:28:51.01#ibcon#wrote, iclass 39, count 2 2006.174.00:28:51.01#ibcon#about to read 3, iclass 39, count 2 2006.174.00:28:51.03#ibcon#read 3, iclass 39, count 2 2006.174.00:28:51.03#ibcon#about to read 4, iclass 39, count 2 2006.174.00:28:51.03#ibcon#read 4, iclass 39, count 2 2006.174.00:28:51.03#ibcon#about to read 5, iclass 39, count 2 2006.174.00:28:51.03#ibcon#read 5, iclass 39, count 2 2006.174.00:28:51.03#ibcon#about to read 6, iclass 39, count 2 2006.174.00:28:51.03#ibcon#read 6, iclass 39, count 2 2006.174.00:28:51.03#ibcon#end of sib2, iclass 39, count 2 2006.174.00:28:51.03#ibcon#*mode == 0, iclass 39, count 2 2006.174.00:28:51.03#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.174.00:28:51.03#ibcon#[25=AT03-05\r\n] 2006.174.00:28:51.03#ibcon#*before write, iclass 39, count 2 2006.174.00:28:51.03#ibcon#enter sib2, iclass 39, count 2 2006.174.00:28:51.03#ibcon#flushed, iclass 39, count 2 2006.174.00:28:51.03#ibcon#about to write, iclass 39, count 2 2006.174.00:28:51.03#ibcon#wrote, iclass 39, count 2 2006.174.00:28:51.03#ibcon#about to read 3, iclass 39, count 2 2006.174.00:28:51.06#ibcon#read 3, iclass 39, count 2 2006.174.00:28:51.06#ibcon#about to read 4, iclass 39, count 2 2006.174.00:28:51.06#ibcon#read 4, iclass 39, count 2 2006.174.00:28:51.06#ibcon#about to read 5, iclass 39, count 2 2006.174.00:28:51.06#ibcon#read 5, iclass 39, count 2 2006.174.00:28:51.06#ibcon#about to read 6, iclass 39, count 2 2006.174.00:28:51.06#ibcon#read 6, iclass 39, count 2 2006.174.00:28:51.06#ibcon#end of sib2, iclass 39, count 2 2006.174.00:28:51.06#ibcon#*after write, iclass 39, count 2 2006.174.00:28:51.06#ibcon#*before return 0, iclass 39, count 2 2006.174.00:28:51.06#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.174.00:28:51.06#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.174.00:28:51.06#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.174.00:28:51.06#ibcon#ireg 7 cls_cnt 0 2006.174.00:28:51.06#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.174.00:28:51.18#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.174.00:28:51.18#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.174.00:28:51.18#ibcon#enter wrdev, iclass 39, count 0 2006.174.00:28:51.18#ibcon#first serial, iclass 39, count 0 2006.174.00:28:51.18#ibcon#enter sib2, iclass 39, count 0 2006.174.00:28:51.18#ibcon#flushed, iclass 39, count 0 2006.174.00:28:51.18#ibcon#about to write, iclass 39, count 0 2006.174.00:28:51.18#ibcon#wrote, iclass 39, count 0 2006.174.00:28:51.18#ibcon#about to read 3, iclass 39, count 0 2006.174.00:28:51.20#ibcon#read 3, iclass 39, count 0 2006.174.00:28:51.20#ibcon#about to read 4, iclass 39, count 0 2006.174.00:28:51.20#ibcon#read 4, iclass 39, count 0 2006.174.00:28:51.20#ibcon#about to read 5, iclass 39, count 0 2006.174.00:28:51.20#ibcon#read 5, iclass 39, count 0 2006.174.00:28:51.20#ibcon#about to read 6, iclass 39, count 0 2006.174.00:28:51.20#ibcon#read 6, iclass 39, count 0 2006.174.00:28:51.20#ibcon#end of sib2, iclass 39, count 0 2006.174.00:28:51.20#ibcon#*mode == 0, iclass 39, count 0 2006.174.00:28:51.20#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.174.00:28:51.20#ibcon#[25=USB\r\n] 2006.174.00:28:51.20#ibcon#*before write, iclass 39, count 0 2006.174.00:28:51.20#ibcon#enter sib2, iclass 39, count 0 2006.174.00:28:51.20#ibcon#flushed, iclass 39, count 0 2006.174.00:28:51.20#ibcon#about to write, iclass 39, count 0 2006.174.00:28:51.20#ibcon#wrote, iclass 39, count 0 2006.174.00:28:51.20#ibcon#about to read 3, iclass 39, count 0 2006.174.00:28:51.23#ibcon#read 3, iclass 39, count 0 2006.174.00:28:51.23#ibcon#about to read 4, iclass 39, count 0 2006.174.00:28:51.23#ibcon#read 4, iclass 39, count 0 2006.174.00:28:51.23#ibcon#about to read 5, iclass 39, count 0 2006.174.00:28:51.23#ibcon#read 5, iclass 39, count 0 2006.174.00:28:51.23#ibcon#about to read 6, iclass 39, count 0 2006.174.00:28:51.23#ibcon#read 6, iclass 39, count 0 2006.174.00:28:51.23#ibcon#end of sib2, iclass 39, count 0 2006.174.00:28:51.23#ibcon#*after write, iclass 39, count 0 2006.174.00:28:51.23#ibcon#*before return 0, iclass 39, count 0 2006.174.00:28:51.23#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.174.00:28:51.23#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.174.00:28:51.23#ibcon#about to clear, iclass 39 cls_cnt 0 2006.174.00:28:51.23#ibcon#cleared, iclass 39 cls_cnt 0 2006.174.00:28:51.23$vck44/valo=4,624.99 2006.174.00:28:51.23#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.174.00:28:51.23#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.174.00:28:51.23#ibcon#ireg 17 cls_cnt 0 2006.174.00:28:51.23#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.174.00:28:51.23#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.174.00:28:51.23#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.174.00:28:51.23#ibcon#enter wrdev, iclass 3, count 0 2006.174.00:28:51.23#ibcon#first serial, iclass 3, count 0 2006.174.00:28:51.23#ibcon#enter sib2, iclass 3, count 0 2006.174.00:28:51.23#ibcon#flushed, iclass 3, count 0 2006.174.00:28:51.23#ibcon#about to write, iclass 3, count 0 2006.174.00:28:51.23#ibcon#wrote, iclass 3, count 0 2006.174.00:28:51.23#ibcon#about to read 3, iclass 3, count 0 2006.174.00:28:51.25#ibcon#read 3, iclass 3, count 0 2006.174.00:28:51.25#ibcon#about to read 4, iclass 3, count 0 2006.174.00:28:51.25#ibcon#read 4, iclass 3, count 0 2006.174.00:28:51.25#ibcon#about to read 5, iclass 3, count 0 2006.174.00:28:51.25#ibcon#read 5, iclass 3, count 0 2006.174.00:28:51.25#ibcon#about to read 6, iclass 3, count 0 2006.174.00:28:51.25#ibcon#read 6, iclass 3, count 0 2006.174.00:28:51.25#ibcon#end of sib2, iclass 3, count 0 2006.174.00:28:51.25#ibcon#*mode == 0, iclass 3, count 0 2006.174.00:28:51.25#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.174.00:28:51.25#ibcon#[26=FRQ=04,624.99\r\n] 2006.174.00:28:51.25#ibcon#*before write, iclass 3, count 0 2006.174.00:28:51.25#ibcon#enter sib2, iclass 3, count 0 2006.174.00:28:51.25#ibcon#flushed, iclass 3, count 0 2006.174.00:28:51.25#ibcon#about to write, iclass 3, count 0 2006.174.00:28:51.25#ibcon#wrote, iclass 3, count 0 2006.174.00:28:51.25#ibcon#about to read 3, iclass 3, count 0 2006.174.00:28:51.29#ibcon#read 3, iclass 3, count 0 2006.174.00:28:51.29#ibcon#about to read 4, iclass 3, count 0 2006.174.00:28:51.29#ibcon#read 4, iclass 3, count 0 2006.174.00:28:51.29#ibcon#about to read 5, iclass 3, count 0 2006.174.00:28:51.29#ibcon#read 5, iclass 3, count 0 2006.174.00:28:51.29#ibcon#about to read 6, iclass 3, count 0 2006.174.00:28:51.29#ibcon#read 6, iclass 3, count 0 2006.174.00:28:51.29#ibcon#end of sib2, iclass 3, count 0 2006.174.00:28:51.29#ibcon#*after write, iclass 3, count 0 2006.174.00:28:51.29#ibcon#*before return 0, iclass 3, count 0 2006.174.00:28:51.29#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.174.00:28:51.29#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.174.00:28:51.29#ibcon#about to clear, iclass 3 cls_cnt 0 2006.174.00:28:51.29#ibcon#cleared, iclass 3 cls_cnt 0 2006.174.00:28:51.29$vck44/va=4,6 2006.174.00:28:51.29#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.174.00:28:51.29#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.174.00:28:51.29#ibcon#ireg 11 cls_cnt 2 2006.174.00:28:51.29#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.174.00:28:51.35#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.174.00:28:51.35#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.174.00:28:51.35#ibcon#enter wrdev, iclass 5, count 2 2006.174.00:28:51.35#ibcon#first serial, iclass 5, count 2 2006.174.00:28:51.35#ibcon#enter sib2, iclass 5, count 2 2006.174.00:28:51.35#ibcon#flushed, iclass 5, count 2 2006.174.00:28:51.35#ibcon#about to write, iclass 5, count 2 2006.174.00:28:51.35#ibcon#wrote, iclass 5, count 2 2006.174.00:28:51.35#ibcon#about to read 3, iclass 5, count 2 2006.174.00:28:51.37#ibcon#read 3, iclass 5, count 2 2006.174.00:28:51.37#ibcon#about to read 4, iclass 5, count 2 2006.174.00:28:51.37#ibcon#read 4, iclass 5, count 2 2006.174.00:28:51.37#ibcon#about to read 5, iclass 5, count 2 2006.174.00:28:51.37#ibcon#read 5, iclass 5, count 2 2006.174.00:28:51.37#ibcon#about to read 6, iclass 5, count 2 2006.174.00:28:51.37#ibcon#read 6, iclass 5, count 2 2006.174.00:28:51.37#ibcon#end of sib2, iclass 5, count 2 2006.174.00:28:51.37#ibcon#*mode == 0, iclass 5, count 2 2006.174.00:28:51.37#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.174.00:28:51.37#ibcon#[25=AT04-06\r\n] 2006.174.00:28:51.37#ibcon#*before write, iclass 5, count 2 2006.174.00:28:51.37#ibcon#enter sib2, iclass 5, count 2 2006.174.00:28:51.37#ibcon#flushed, iclass 5, count 2 2006.174.00:28:51.37#ibcon#about to write, iclass 5, count 2 2006.174.00:28:51.37#ibcon#wrote, iclass 5, count 2 2006.174.00:28:51.37#ibcon#about to read 3, iclass 5, count 2 2006.174.00:28:51.40#ibcon#read 3, iclass 5, count 2 2006.174.00:28:51.40#ibcon#about to read 4, iclass 5, count 2 2006.174.00:28:51.40#ibcon#read 4, iclass 5, count 2 2006.174.00:28:51.40#ibcon#about to read 5, iclass 5, count 2 2006.174.00:28:51.40#ibcon#read 5, iclass 5, count 2 2006.174.00:28:51.40#ibcon#about to read 6, iclass 5, count 2 2006.174.00:28:51.40#ibcon#read 6, iclass 5, count 2 2006.174.00:28:51.40#ibcon#end of sib2, iclass 5, count 2 2006.174.00:28:51.40#ibcon#*after write, iclass 5, count 2 2006.174.00:28:51.40#ibcon#*before return 0, iclass 5, count 2 2006.174.00:28:51.40#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.174.00:28:51.40#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.174.00:28:51.40#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.174.00:28:51.40#ibcon#ireg 7 cls_cnt 0 2006.174.00:28:51.40#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.174.00:28:51.52#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.174.00:28:51.52#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.174.00:28:51.52#ibcon#enter wrdev, iclass 5, count 0 2006.174.00:28:51.52#ibcon#first serial, iclass 5, count 0 2006.174.00:28:51.52#ibcon#enter sib2, iclass 5, count 0 2006.174.00:28:51.52#ibcon#flushed, iclass 5, count 0 2006.174.00:28:51.52#ibcon#about to write, iclass 5, count 0 2006.174.00:28:51.52#ibcon#wrote, iclass 5, count 0 2006.174.00:28:51.52#ibcon#about to read 3, iclass 5, count 0 2006.174.00:28:51.54#ibcon#read 3, iclass 5, count 0 2006.174.00:28:51.54#ibcon#about to read 4, iclass 5, count 0 2006.174.00:28:51.54#ibcon#read 4, iclass 5, count 0 2006.174.00:28:51.54#ibcon#about to read 5, iclass 5, count 0 2006.174.00:28:51.54#ibcon#read 5, iclass 5, count 0 2006.174.00:28:51.54#ibcon#about to read 6, iclass 5, count 0 2006.174.00:28:51.54#ibcon#read 6, iclass 5, count 0 2006.174.00:28:51.54#ibcon#end of sib2, iclass 5, count 0 2006.174.00:28:51.54#ibcon#*mode == 0, iclass 5, count 0 2006.174.00:28:51.54#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.174.00:28:51.54#ibcon#[25=USB\r\n] 2006.174.00:28:51.54#ibcon#*before write, iclass 5, count 0 2006.174.00:28:51.54#ibcon#enter sib2, iclass 5, count 0 2006.174.00:28:51.54#ibcon#flushed, iclass 5, count 0 2006.174.00:28:51.54#ibcon#about to write, iclass 5, count 0 2006.174.00:28:51.54#ibcon#wrote, iclass 5, count 0 2006.174.00:28:51.54#ibcon#about to read 3, iclass 5, count 0 2006.174.00:28:51.57#ibcon#read 3, iclass 5, count 0 2006.174.00:28:51.57#ibcon#about to read 4, iclass 5, count 0 2006.174.00:28:51.57#ibcon#read 4, iclass 5, count 0 2006.174.00:28:51.57#ibcon#about to read 5, iclass 5, count 0 2006.174.00:28:51.57#ibcon#read 5, iclass 5, count 0 2006.174.00:28:51.57#ibcon#about to read 6, iclass 5, count 0 2006.174.00:28:51.57#ibcon#read 6, iclass 5, count 0 2006.174.00:28:51.57#ibcon#end of sib2, iclass 5, count 0 2006.174.00:28:51.57#ibcon#*after write, iclass 5, count 0 2006.174.00:28:51.57#ibcon#*before return 0, iclass 5, count 0 2006.174.00:28:51.57#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.174.00:28:51.57#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.174.00:28:51.57#ibcon#about to clear, iclass 5 cls_cnt 0 2006.174.00:28:51.57#ibcon#cleared, iclass 5 cls_cnt 0 2006.174.00:28:51.57$vck44/valo=5,734.99 2006.174.00:28:51.57#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.174.00:28:51.57#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.174.00:28:51.57#ibcon#ireg 17 cls_cnt 0 2006.174.00:28:51.57#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.174.00:28:51.57#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.174.00:28:51.57#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.174.00:28:51.57#ibcon#enter wrdev, iclass 7, count 0 2006.174.00:28:51.57#ibcon#first serial, iclass 7, count 0 2006.174.00:28:51.57#ibcon#enter sib2, iclass 7, count 0 2006.174.00:28:51.57#ibcon#flushed, iclass 7, count 0 2006.174.00:28:51.57#ibcon#about to write, iclass 7, count 0 2006.174.00:28:51.57#ibcon#wrote, iclass 7, count 0 2006.174.00:28:51.57#ibcon#about to read 3, iclass 7, count 0 2006.174.00:28:51.59#ibcon#read 3, iclass 7, count 0 2006.174.00:28:51.59#ibcon#about to read 4, iclass 7, count 0 2006.174.00:28:51.59#ibcon#read 4, iclass 7, count 0 2006.174.00:28:51.59#ibcon#about to read 5, iclass 7, count 0 2006.174.00:28:51.59#ibcon#read 5, iclass 7, count 0 2006.174.00:28:51.59#ibcon#about to read 6, iclass 7, count 0 2006.174.00:28:51.59#ibcon#read 6, iclass 7, count 0 2006.174.00:28:51.59#ibcon#end of sib2, iclass 7, count 0 2006.174.00:28:51.59#ibcon#*mode == 0, iclass 7, count 0 2006.174.00:28:51.59#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.174.00:28:51.59#ibcon#[26=FRQ=05,734.99\r\n] 2006.174.00:28:51.59#ibcon#*before write, iclass 7, count 0 2006.174.00:28:51.59#ibcon#enter sib2, iclass 7, count 0 2006.174.00:28:51.59#ibcon#flushed, iclass 7, count 0 2006.174.00:28:51.59#ibcon#about to write, iclass 7, count 0 2006.174.00:28:51.59#ibcon#wrote, iclass 7, count 0 2006.174.00:28:51.59#ibcon#about to read 3, iclass 7, count 0 2006.174.00:28:51.63#ibcon#read 3, iclass 7, count 0 2006.174.00:28:51.63#ibcon#about to read 4, iclass 7, count 0 2006.174.00:28:51.63#ibcon#read 4, iclass 7, count 0 2006.174.00:28:51.63#ibcon#about to read 5, iclass 7, count 0 2006.174.00:28:51.63#ibcon#read 5, iclass 7, count 0 2006.174.00:28:51.63#ibcon#about to read 6, iclass 7, count 0 2006.174.00:28:51.63#ibcon#read 6, iclass 7, count 0 2006.174.00:28:51.63#ibcon#end of sib2, iclass 7, count 0 2006.174.00:28:51.63#ibcon#*after write, iclass 7, count 0 2006.174.00:28:51.63#ibcon#*before return 0, iclass 7, count 0 2006.174.00:28:51.63#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.174.00:28:51.63#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.174.00:28:51.63#ibcon#about to clear, iclass 7 cls_cnt 0 2006.174.00:28:51.63#ibcon#cleared, iclass 7 cls_cnt 0 2006.174.00:28:51.63$vck44/va=5,4 2006.174.00:28:51.63#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.174.00:28:51.63#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.174.00:28:51.63#ibcon#ireg 11 cls_cnt 2 2006.174.00:28:51.63#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.174.00:28:51.69#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.174.00:28:51.69#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.174.00:28:51.69#ibcon#enter wrdev, iclass 11, count 2 2006.174.00:28:51.69#ibcon#first serial, iclass 11, count 2 2006.174.00:28:51.69#ibcon#enter sib2, iclass 11, count 2 2006.174.00:28:51.69#ibcon#flushed, iclass 11, count 2 2006.174.00:28:51.69#ibcon#about to write, iclass 11, count 2 2006.174.00:28:51.69#ibcon#wrote, iclass 11, count 2 2006.174.00:28:51.69#ibcon#about to read 3, iclass 11, count 2 2006.174.00:28:51.71#ibcon#read 3, iclass 11, count 2 2006.174.00:28:51.71#ibcon#about to read 4, iclass 11, count 2 2006.174.00:28:51.71#ibcon#read 4, iclass 11, count 2 2006.174.00:28:51.71#ibcon#about to read 5, iclass 11, count 2 2006.174.00:28:51.71#ibcon#read 5, iclass 11, count 2 2006.174.00:28:51.71#ibcon#about to read 6, iclass 11, count 2 2006.174.00:28:51.71#ibcon#read 6, iclass 11, count 2 2006.174.00:28:51.71#ibcon#end of sib2, iclass 11, count 2 2006.174.00:28:51.71#ibcon#*mode == 0, iclass 11, count 2 2006.174.00:28:51.71#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.174.00:28:51.71#ibcon#[25=AT05-04\r\n] 2006.174.00:28:51.71#ibcon#*before write, iclass 11, count 2 2006.174.00:28:51.71#ibcon#enter sib2, iclass 11, count 2 2006.174.00:28:51.71#ibcon#flushed, iclass 11, count 2 2006.174.00:28:51.71#ibcon#about to write, iclass 11, count 2 2006.174.00:28:51.71#ibcon#wrote, iclass 11, count 2 2006.174.00:28:51.71#ibcon#about to read 3, iclass 11, count 2 2006.174.00:28:51.74#ibcon#read 3, iclass 11, count 2 2006.174.00:28:51.74#ibcon#about to read 4, iclass 11, count 2 2006.174.00:28:51.74#ibcon#read 4, iclass 11, count 2 2006.174.00:28:51.74#ibcon#about to read 5, iclass 11, count 2 2006.174.00:28:51.74#ibcon#read 5, iclass 11, count 2 2006.174.00:28:51.74#ibcon#about to read 6, iclass 11, count 2 2006.174.00:28:51.74#ibcon#read 6, iclass 11, count 2 2006.174.00:28:51.74#ibcon#end of sib2, iclass 11, count 2 2006.174.00:28:51.74#ibcon#*after write, iclass 11, count 2 2006.174.00:28:51.74#ibcon#*before return 0, iclass 11, count 2 2006.174.00:28:51.74#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.174.00:28:51.74#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.174.00:28:51.74#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.174.00:28:51.74#ibcon#ireg 7 cls_cnt 0 2006.174.00:28:51.74#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.174.00:28:51.86#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.174.00:28:51.86#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.174.00:28:51.86#ibcon#enter wrdev, iclass 11, count 0 2006.174.00:28:51.86#ibcon#first serial, iclass 11, count 0 2006.174.00:28:51.86#ibcon#enter sib2, iclass 11, count 0 2006.174.00:28:51.86#ibcon#flushed, iclass 11, count 0 2006.174.00:28:51.86#ibcon#about to write, iclass 11, count 0 2006.174.00:28:51.86#ibcon#wrote, iclass 11, count 0 2006.174.00:28:51.86#ibcon#about to read 3, iclass 11, count 0 2006.174.00:28:51.88#ibcon#read 3, iclass 11, count 0 2006.174.00:28:51.88#ibcon#about to read 4, iclass 11, count 0 2006.174.00:28:51.88#ibcon#read 4, iclass 11, count 0 2006.174.00:28:51.88#ibcon#about to read 5, iclass 11, count 0 2006.174.00:28:51.88#ibcon#read 5, iclass 11, count 0 2006.174.00:28:51.88#ibcon#about to read 6, iclass 11, count 0 2006.174.00:28:51.88#ibcon#read 6, iclass 11, count 0 2006.174.00:28:51.88#ibcon#end of sib2, iclass 11, count 0 2006.174.00:28:51.88#ibcon#*mode == 0, iclass 11, count 0 2006.174.00:28:51.88#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.174.00:28:51.88#ibcon#[25=USB\r\n] 2006.174.00:28:51.88#ibcon#*before write, iclass 11, count 0 2006.174.00:28:51.88#ibcon#enter sib2, iclass 11, count 0 2006.174.00:28:51.88#ibcon#flushed, iclass 11, count 0 2006.174.00:28:51.88#ibcon#about to write, iclass 11, count 0 2006.174.00:28:51.88#ibcon#wrote, iclass 11, count 0 2006.174.00:28:51.88#ibcon#about to read 3, iclass 11, count 0 2006.174.00:28:51.91#ibcon#read 3, iclass 11, count 0 2006.174.00:28:51.91#ibcon#about to read 4, iclass 11, count 0 2006.174.00:28:51.91#ibcon#read 4, iclass 11, count 0 2006.174.00:28:51.91#ibcon#about to read 5, iclass 11, count 0 2006.174.00:28:51.91#ibcon#read 5, iclass 11, count 0 2006.174.00:28:51.91#ibcon#about to read 6, iclass 11, count 0 2006.174.00:28:51.91#ibcon#read 6, iclass 11, count 0 2006.174.00:28:51.91#ibcon#end of sib2, iclass 11, count 0 2006.174.00:28:51.91#ibcon#*after write, iclass 11, count 0 2006.174.00:28:51.91#ibcon#*before return 0, iclass 11, count 0 2006.174.00:28:51.91#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.174.00:28:51.91#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.174.00:28:51.91#ibcon#about to clear, iclass 11 cls_cnt 0 2006.174.00:28:51.91#ibcon#cleared, iclass 11 cls_cnt 0 2006.174.00:28:51.91$vck44/valo=6,814.99 2006.174.00:28:51.91#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.174.00:28:51.91#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.174.00:28:51.91#ibcon#ireg 17 cls_cnt 0 2006.174.00:28:51.91#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.174.00:28:51.91#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.174.00:28:51.91#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.174.00:28:51.91#ibcon#enter wrdev, iclass 13, count 0 2006.174.00:28:51.91#ibcon#first serial, iclass 13, count 0 2006.174.00:28:51.91#ibcon#enter sib2, iclass 13, count 0 2006.174.00:28:51.91#ibcon#flushed, iclass 13, count 0 2006.174.00:28:51.91#ibcon#about to write, iclass 13, count 0 2006.174.00:28:51.91#ibcon#wrote, iclass 13, count 0 2006.174.00:28:51.91#ibcon#about to read 3, iclass 13, count 0 2006.174.00:28:51.93#ibcon#read 3, iclass 13, count 0 2006.174.00:28:51.93#ibcon#about to read 4, iclass 13, count 0 2006.174.00:28:51.93#ibcon#read 4, iclass 13, count 0 2006.174.00:28:51.93#ibcon#about to read 5, iclass 13, count 0 2006.174.00:28:51.93#ibcon#read 5, iclass 13, count 0 2006.174.00:28:51.93#ibcon#about to read 6, iclass 13, count 0 2006.174.00:28:51.93#ibcon#read 6, iclass 13, count 0 2006.174.00:28:51.93#ibcon#end of sib2, iclass 13, count 0 2006.174.00:28:51.93#ibcon#*mode == 0, iclass 13, count 0 2006.174.00:28:51.93#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.174.00:28:51.93#ibcon#[26=FRQ=06,814.99\r\n] 2006.174.00:28:51.93#ibcon#*before write, iclass 13, count 0 2006.174.00:28:51.93#ibcon#enter sib2, iclass 13, count 0 2006.174.00:28:51.93#ibcon#flushed, iclass 13, count 0 2006.174.00:28:51.93#ibcon#about to write, iclass 13, count 0 2006.174.00:28:51.93#ibcon#wrote, iclass 13, count 0 2006.174.00:28:51.93#ibcon#about to read 3, iclass 13, count 0 2006.174.00:28:51.97#ibcon#read 3, iclass 13, count 0 2006.174.00:28:51.97#ibcon#about to read 4, iclass 13, count 0 2006.174.00:28:51.97#ibcon#read 4, iclass 13, count 0 2006.174.00:28:51.97#ibcon#about to read 5, iclass 13, count 0 2006.174.00:28:51.97#ibcon#read 5, iclass 13, count 0 2006.174.00:28:51.97#ibcon#about to read 6, iclass 13, count 0 2006.174.00:28:51.97#ibcon#read 6, iclass 13, count 0 2006.174.00:28:51.97#ibcon#end of sib2, iclass 13, count 0 2006.174.00:28:51.97#ibcon#*after write, iclass 13, count 0 2006.174.00:28:51.97#ibcon#*before return 0, iclass 13, count 0 2006.174.00:28:51.97#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.174.00:28:51.97#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.174.00:28:51.97#ibcon#about to clear, iclass 13 cls_cnt 0 2006.174.00:28:51.97#ibcon#cleared, iclass 13 cls_cnt 0 2006.174.00:28:51.97$vck44/va=6,3 2006.174.00:28:51.97#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.174.00:28:51.97#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.174.00:28:51.97#ibcon#ireg 11 cls_cnt 2 2006.174.00:28:51.97#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.174.00:28:52.03#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.174.00:28:52.03#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.174.00:28:52.03#ibcon#enter wrdev, iclass 15, count 2 2006.174.00:28:52.03#ibcon#first serial, iclass 15, count 2 2006.174.00:28:52.03#ibcon#enter sib2, iclass 15, count 2 2006.174.00:28:52.03#ibcon#flushed, iclass 15, count 2 2006.174.00:28:52.03#ibcon#about to write, iclass 15, count 2 2006.174.00:28:52.03#ibcon#wrote, iclass 15, count 2 2006.174.00:28:52.03#ibcon#about to read 3, iclass 15, count 2 2006.174.00:28:52.05#ibcon#read 3, iclass 15, count 2 2006.174.00:28:52.05#ibcon#about to read 4, iclass 15, count 2 2006.174.00:28:52.05#ibcon#read 4, iclass 15, count 2 2006.174.00:28:52.05#ibcon#about to read 5, iclass 15, count 2 2006.174.00:28:52.05#ibcon#read 5, iclass 15, count 2 2006.174.00:28:52.05#ibcon#about to read 6, iclass 15, count 2 2006.174.00:28:52.05#ibcon#read 6, iclass 15, count 2 2006.174.00:28:52.05#ibcon#end of sib2, iclass 15, count 2 2006.174.00:28:52.05#ibcon#*mode == 0, iclass 15, count 2 2006.174.00:28:52.05#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.174.00:28:52.05#ibcon#[25=AT06-03\r\n] 2006.174.00:28:52.05#ibcon#*before write, iclass 15, count 2 2006.174.00:28:52.05#ibcon#enter sib2, iclass 15, count 2 2006.174.00:28:52.05#ibcon#flushed, iclass 15, count 2 2006.174.00:28:52.05#ibcon#about to write, iclass 15, count 2 2006.174.00:28:52.05#ibcon#wrote, iclass 15, count 2 2006.174.00:28:52.05#ibcon#about to read 3, iclass 15, count 2 2006.174.00:28:52.08#ibcon#read 3, iclass 15, count 2 2006.174.00:28:52.08#ibcon#about to read 4, iclass 15, count 2 2006.174.00:28:52.08#ibcon#read 4, iclass 15, count 2 2006.174.00:28:52.08#ibcon#about to read 5, iclass 15, count 2 2006.174.00:28:52.08#ibcon#read 5, iclass 15, count 2 2006.174.00:28:52.08#ibcon#about to read 6, iclass 15, count 2 2006.174.00:28:52.08#ibcon#read 6, iclass 15, count 2 2006.174.00:28:52.08#ibcon#end of sib2, iclass 15, count 2 2006.174.00:28:52.08#ibcon#*after write, iclass 15, count 2 2006.174.00:28:52.08#ibcon#*before return 0, iclass 15, count 2 2006.174.00:28:52.08#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.174.00:28:52.08#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.174.00:28:52.08#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.174.00:28:52.08#ibcon#ireg 7 cls_cnt 0 2006.174.00:28:52.08#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.174.00:28:52.20#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.174.00:28:52.20#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.174.00:28:52.20#ibcon#enter wrdev, iclass 15, count 0 2006.174.00:28:52.20#ibcon#first serial, iclass 15, count 0 2006.174.00:28:52.20#ibcon#enter sib2, iclass 15, count 0 2006.174.00:28:52.20#ibcon#flushed, iclass 15, count 0 2006.174.00:28:52.20#ibcon#about to write, iclass 15, count 0 2006.174.00:28:52.20#ibcon#wrote, iclass 15, count 0 2006.174.00:28:52.20#ibcon#about to read 3, iclass 15, count 0 2006.174.00:28:52.22#ibcon#read 3, iclass 15, count 0 2006.174.00:28:52.22#ibcon#about to read 4, iclass 15, count 0 2006.174.00:28:52.22#ibcon#read 4, iclass 15, count 0 2006.174.00:28:52.22#ibcon#about to read 5, iclass 15, count 0 2006.174.00:28:52.22#ibcon#read 5, iclass 15, count 0 2006.174.00:28:52.22#ibcon#about to read 6, iclass 15, count 0 2006.174.00:28:52.22#ibcon#read 6, iclass 15, count 0 2006.174.00:28:52.22#ibcon#end of sib2, iclass 15, count 0 2006.174.00:28:52.22#ibcon#*mode == 0, iclass 15, count 0 2006.174.00:28:52.22#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.174.00:28:52.22#ibcon#[25=USB\r\n] 2006.174.00:28:52.22#ibcon#*before write, iclass 15, count 0 2006.174.00:28:52.22#ibcon#enter sib2, iclass 15, count 0 2006.174.00:28:52.22#ibcon#flushed, iclass 15, count 0 2006.174.00:28:52.22#ibcon#about to write, iclass 15, count 0 2006.174.00:28:52.22#ibcon#wrote, iclass 15, count 0 2006.174.00:28:52.22#ibcon#about to read 3, iclass 15, count 0 2006.174.00:28:52.25#ibcon#read 3, iclass 15, count 0 2006.174.00:28:52.25#ibcon#about to read 4, iclass 15, count 0 2006.174.00:28:52.25#ibcon#read 4, iclass 15, count 0 2006.174.00:28:52.25#ibcon#about to read 5, iclass 15, count 0 2006.174.00:28:52.25#ibcon#read 5, iclass 15, count 0 2006.174.00:28:52.25#ibcon#about to read 6, iclass 15, count 0 2006.174.00:28:52.25#ibcon#read 6, iclass 15, count 0 2006.174.00:28:52.25#ibcon#end of sib2, iclass 15, count 0 2006.174.00:28:52.25#ibcon#*after write, iclass 15, count 0 2006.174.00:28:52.25#ibcon#*before return 0, iclass 15, count 0 2006.174.00:28:52.25#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.174.00:28:52.25#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.174.00:28:52.25#ibcon#about to clear, iclass 15 cls_cnt 0 2006.174.00:28:52.25#ibcon#cleared, iclass 15 cls_cnt 0 2006.174.00:28:52.25$vck44/valo=7,864.99 2006.174.00:28:52.25#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.174.00:28:52.25#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.174.00:28:52.25#ibcon#ireg 17 cls_cnt 0 2006.174.00:28:52.25#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.174.00:28:52.25#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.174.00:28:52.25#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.174.00:28:52.25#ibcon#enter wrdev, iclass 17, count 0 2006.174.00:28:52.25#ibcon#first serial, iclass 17, count 0 2006.174.00:28:52.25#ibcon#enter sib2, iclass 17, count 0 2006.174.00:28:52.25#ibcon#flushed, iclass 17, count 0 2006.174.00:28:52.25#ibcon#about to write, iclass 17, count 0 2006.174.00:28:52.25#ibcon#wrote, iclass 17, count 0 2006.174.00:28:52.25#ibcon#about to read 3, iclass 17, count 0 2006.174.00:28:52.27#ibcon#read 3, iclass 17, count 0 2006.174.00:28:52.27#ibcon#about to read 4, iclass 17, count 0 2006.174.00:28:52.27#ibcon#read 4, iclass 17, count 0 2006.174.00:28:52.27#ibcon#about to read 5, iclass 17, count 0 2006.174.00:28:52.27#ibcon#read 5, iclass 17, count 0 2006.174.00:28:52.27#ibcon#about to read 6, iclass 17, count 0 2006.174.00:28:52.27#ibcon#read 6, iclass 17, count 0 2006.174.00:28:52.27#ibcon#end of sib2, iclass 17, count 0 2006.174.00:28:52.27#ibcon#*mode == 0, iclass 17, count 0 2006.174.00:28:52.27#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.174.00:28:52.27#ibcon#[26=FRQ=07,864.99\r\n] 2006.174.00:28:52.27#ibcon#*before write, iclass 17, count 0 2006.174.00:28:52.27#ibcon#enter sib2, iclass 17, count 0 2006.174.00:28:52.27#ibcon#flushed, iclass 17, count 0 2006.174.00:28:52.27#ibcon#about to write, iclass 17, count 0 2006.174.00:28:52.27#ibcon#wrote, iclass 17, count 0 2006.174.00:28:52.27#ibcon#about to read 3, iclass 17, count 0 2006.174.00:28:52.31#ibcon#read 3, iclass 17, count 0 2006.174.00:28:52.31#ibcon#about to read 4, iclass 17, count 0 2006.174.00:28:52.31#ibcon#read 4, iclass 17, count 0 2006.174.00:28:52.31#ibcon#about to read 5, iclass 17, count 0 2006.174.00:28:52.31#ibcon#read 5, iclass 17, count 0 2006.174.00:28:52.31#ibcon#about to read 6, iclass 17, count 0 2006.174.00:28:52.31#ibcon#read 6, iclass 17, count 0 2006.174.00:28:52.31#ibcon#end of sib2, iclass 17, count 0 2006.174.00:28:52.31#ibcon#*after write, iclass 17, count 0 2006.174.00:28:52.31#ibcon#*before return 0, iclass 17, count 0 2006.174.00:28:52.31#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.174.00:28:52.31#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.174.00:28:52.31#ibcon#about to clear, iclass 17 cls_cnt 0 2006.174.00:28:52.31#ibcon#cleared, iclass 17 cls_cnt 0 2006.174.00:28:52.31$vck44/va=7,4 2006.174.00:28:52.31#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.174.00:28:52.31#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.174.00:28:52.31#ibcon#ireg 11 cls_cnt 2 2006.174.00:28:52.31#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.174.00:28:52.37#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.174.00:28:52.37#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.174.00:28:52.37#ibcon#enter wrdev, iclass 19, count 2 2006.174.00:28:52.37#ibcon#first serial, iclass 19, count 2 2006.174.00:28:52.37#ibcon#enter sib2, iclass 19, count 2 2006.174.00:28:52.37#ibcon#flushed, iclass 19, count 2 2006.174.00:28:52.37#ibcon#about to write, iclass 19, count 2 2006.174.00:28:52.37#ibcon#wrote, iclass 19, count 2 2006.174.00:28:52.37#ibcon#about to read 3, iclass 19, count 2 2006.174.00:28:52.39#ibcon#read 3, iclass 19, count 2 2006.174.00:28:52.39#ibcon#about to read 4, iclass 19, count 2 2006.174.00:28:52.39#ibcon#read 4, iclass 19, count 2 2006.174.00:28:52.39#ibcon#about to read 5, iclass 19, count 2 2006.174.00:28:52.39#ibcon#read 5, iclass 19, count 2 2006.174.00:28:52.39#ibcon#about to read 6, iclass 19, count 2 2006.174.00:28:52.39#ibcon#read 6, iclass 19, count 2 2006.174.00:28:52.39#ibcon#end of sib2, iclass 19, count 2 2006.174.00:28:52.39#ibcon#*mode == 0, iclass 19, count 2 2006.174.00:28:52.39#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.174.00:28:52.39#ibcon#[25=AT07-04\r\n] 2006.174.00:28:52.39#ibcon#*before write, iclass 19, count 2 2006.174.00:28:52.39#ibcon#enter sib2, iclass 19, count 2 2006.174.00:28:52.39#ibcon#flushed, iclass 19, count 2 2006.174.00:28:52.39#ibcon#about to write, iclass 19, count 2 2006.174.00:28:52.39#ibcon#wrote, iclass 19, count 2 2006.174.00:28:52.39#ibcon#about to read 3, iclass 19, count 2 2006.174.00:28:52.42#ibcon#read 3, iclass 19, count 2 2006.174.00:28:52.42#ibcon#about to read 4, iclass 19, count 2 2006.174.00:28:52.42#ibcon#read 4, iclass 19, count 2 2006.174.00:28:52.42#ibcon#about to read 5, iclass 19, count 2 2006.174.00:28:52.42#ibcon#read 5, iclass 19, count 2 2006.174.00:28:52.42#ibcon#about to read 6, iclass 19, count 2 2006.174.00:28:52.42#ibcon#read 6, iclass 19, count 2 2006.174.00:28:52.42#ibcon#end of sib2, iclass 19, count 2 2006.174.00:28:52.42#ibcon#*after write, iclass 19, count 2 2006.174.00:28:52.42#ibcon#*before return 0, iclass 19, count 2 2006.174.00:28:52.42#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.174.00:28:52.42#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.174.00:28:52.42#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.174.00:28:52.42#ibcon#ireg 7 cls_cnt 0 2006.174.00:28:52.42#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.174.00:28:52.54#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.174.00:28:52.54#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.174.00:28:52.54#ibcon#enter wrdev, iclass 19, count 0 2006.174.00:28:52.54#ibcon#first serial, iclass 19, count 0 2006.174.00:28:52.54#ibcon#enter sib2, iclass 19, count 0 2006.174.00:28:52.54#ibcon#flushed, iclass 19, count 0 2006.174.00:28:52.54#ibcon#about to write, iclass 19, count 0 2006.174.00:28:52.54#ibcon#wrote, iclass 19, count 0 2006.174.00:28:52.54#ibcon#about to read 3, iclass 19, count 0 2006.174.00:28:52.56#ibcon#read 3, iclass 19, count 0 2006.174.00:28:52.56#ibcon#about to read 4, iclass 19, count 0 2006.174.00:28:52.56#ibcon#read 4, iclass 19, count 0 2006.174.00:28:52.56#ibcon#about to read 5, iclass 19, count 0 2006.174.00:28:52.56#ibcon#read 5, iclass 19, count 0 2006.174.00:28:52.56#ibcon#about to read 6, iclass 19, count 0 2006.174.00:28:52.56#ibcon#read 6, iclass 19, count 0 2006.174.00:28:52.56#ibcon#end of sib2, iclass 19, count 0 2006.174.00:28:52.56#ibcon#*mode == 0, iclass 19, count 0 2006.174.00:28:52.56#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.174.00:28:52.56#ibcon#[25=USB\r\n] 2006.174.00:28:52.56#ibcon#*before write, iclass 19, count 0 2006.174.00:28:52.56#ibcon#enter sib2, iclass 19, count 0 2006.174.00:28:52.56#ibcon#flushed, iclass 19, count 0 2006.174.00:28:52.56#ibcon#about to write, iclass 19, count 0 2006.174.00:28:52.56#ibcon#wrote, iclass 19, count 0 2006.174.00:28:52.56#ibcon#about to read 3, iclass 19, count 0 2006.174.00:28:52.59#ibcon#read 3, iclass 19, count 0 2006.174.00:28:52.59#ibcon#about to read 4, iclass 19, count 0 2006.174.00:28:52.59#ibcon#read 4, iclass 19, count 0 2006.174.00:28:52.59#ibcon#about to read 5, iclass 19, count 0 2006.174.00:28:52.59#ibcon#read 5, iclass 19, count 0 2006.174.00:28:52.59#ibcon#about to read 6, iclass 19, count 0 2006.174.00:28:52.59#ibcon#read 6, iclass 19, count 0 2006.174.00:28:52.59#ibcon#end of sib2, iclass 19, count 0 2006.174.00:28:52.59#ibcon#*after write, iclass 19, count 0 2006.174.00:28:52.59#ibcon#*before return 0, iclass 19, count 0 2006.174.00:28:52.59#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.174.00:28:52.59#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.174.00:28:52.59#ibcon#about to clear, iclass 19 cls_cnt 0 2006.174.00:28:52.59#ibcon#cleared, iclass 19 cls_cnt 0 2006.174.00:28:52.59$vck44/valo=8,884.99 2006.174.00:28:52.59#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.174.00:28:52.59#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.174.00:28:52.59#ibcon#ireg 17 cls_cnt 0 2006.174.00:28:52.59#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.174.00:28:52.59#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.174.00:28:52.59#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.174.00:28:52.59#ibcon#enter wrdev, iclass 21, count 0 2006.174.00:28:52.59#ibcon#first serial, iclass 21, count 0 2006.174.00:28:52.59#ibcon#enter sib2, iclass 21, count 0 2006.174.00:28:52.59#ibcon#flushed, iclass 21, count 0 2006.174.00:28:52.59#ibcon#about to write, iclass 21, count 0 2006.174.00:28:52.59#ibcon#wrote, iclass 21, count 0 2006.174.00:28:52.59#ibcon#about to read 3, iclass 21, count 0 2006.174.00:28:52.61#ibcon#read 3, iclass 21, count 0 2006.174.00:28:52.61#ibcon#about to read 4, iclass 21, count 0 2006.174.00:28:52.61#ibcon#read 4, iclass 21, count 0 2006.174.00:28:52.61#ibcon#about to read 5, iclass 21, count 0 2006.174.00:28:52.61#ibcon#read 5, iclass 21, count 0 2006.174.00:28:52.61#ibcon#about to read 6, iclass 21, count 0 2006.174.00:28:52.61#ibcon#read 6, iclass 21, count 0 2006.174.00:28:52.61#ibcon#end of sib2, iclass 21, count 0 2006.174.00:28:52.61#ibcon#*mode == 0, iclass 21, count 0 2006.174.00:28:52.61#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.174.00:28:52.61#ibcon#[26=FRQ=08,884.99\r\n] 2006.174.00:28:52.61#ibcon#*before write, iclass 21, count 0 2006.174.00:28:52.61#ibcon#enter sib2, iclass 21, count 0 2006.174.00:28:52.61#ibcon#flushed, iclass 21, count 0 2006.174.00:28:52.61#ibcon#about to write, iclass 21, count 0 2006.174.00:28:52.61#ibcon#wrote, iclass 21, count 0 2006.174.00:28:52.61#ibcon#about to read 3, iclass 21, count 0 2006.174.00:28:52.65#ibcon#read 3, iclass 21, count 0 2006.174.00:28:52.65#ibcon#about to read 4, iclass 21, count 0 2006.174.00:28:52.65#ibcon#read 4, iclass 21, count 0 2006.174.00:28:52.65#ibcon#about to read 5, iclass 21, count 0 2006.174.00:28:52.65#ibcon#read 5, iclass 21, count 0 2006.174.00:28:52.65#ibcon#about to read 6, iclass 21, count 0 2006.174.00:28:52.65#ibcon#read 6, iclass 21, count 0 2006.174.00:28:52.65#ibcon#end of sib2, iclass 21, count 0 2006.174.00:28:52.65#ibcon#*after write, iclass 21, count 0 2006.174.00:28:52.65#ibcon#*before return 0, iclass 21, count 0 2006.174.00:28:52.65#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.174.00:28:52.65#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.174.00:28:52.65#ibcon#about to clear, iclass 21 cls_cnt 0 2006.174.00:28:52.65#ibcon#cleared, iclass 21 cls_cnt 0 2006.174.00:28:52.65$vck44/va=8,4 2006.174.00:28:52.65#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.174.00:28:52.65#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.174.00:28:52.65#ibcon#ireg 11 cls_cnt 2 2006.174.00:28:52.65#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.174.00:28:52.71#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.174.00:28:52.71#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.174.00:28:52.71#ibcon#enter wrdev, iclass 23, count 2 2006.174.00:28:52.71#ibcon#first serial, iclass 23, count 2 2006.174.00:28:52.71#ibcon#enter sib2, iclass 23, count 2 2006.174.00:28:52.71#ibcon#flushed, iclass 23, count 2 2006.174.00:28:52.71#ibcon#about to write, iclass 23, count 2 2006.174.00:28:52.71#ibcon#wrote, iclass 23, count 2 2006.174.00:28:52.71#ibcon#about to read 3, iclass 23, count 2 2006.174.00:28:52.73#ibcon#read 3, iclass 23, count 2 2006.174.00:28:52.73#ibcon#about to read 4, iclass 23, count 2 2006.174.00:28:52.73#ibcon#read 4, iclass 23, count 2 2006.174.00:28:52.73#ibcon#about to read 5, iclass 23, count 2 2006.174.00:28:52.73#ibcon#read 5, iclass 23, count 2 2006.174.00:28:52.73#ibcon#about to read 6, iclass 23, count 2 2006.174.00:28:52.73#ibcon#read 6, iclass 23, count 2 2006.174.00:28:52.73#ibcon#end of sib2, iclass 23, count 2 2006.174.00:28:52.73#ibcon#*mode == 0, iclass 23, count 2 2006.174.00:28:52.73#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.174.00:28:52.73#ibcon#[25=AT08-04\r\n] 2006.174.00:28:52.73#ibcon#*before write, iclass 23, count 2 2006.174.00:28:52.73#ibcon#enter sib2, iclass 23, count 2 2006.174.00:28:52.73#ibcon#flushed, iclass 23, count 2 2006.174.00:28:52.73#ibcon#about to write, iclass 23, count 2 2006.174.00:28:52.73#ibcon#wrote, iclass 23, count 2 2006.174.00:28:52.73#ibcon#about to read 3, iclass 23, count 2 2006.174.00:28:52.76#ibcon#read 3, iclass 23, count 2 2006.174.00:28:52.76#ibcon#about to read 4, iclass 23, count 2 2006.174.00:28:52.76#ibcon#read 4, iclass 23, count 2 2006.174.00:28:52.76#ibcon#about to read 5, iclass 23, count 2 2006.174.00:28:52.76#ibcon#read 5, iclass 23, count 2 2006.174.00:28:52.76#ibcon#about to read 6, iclass 23, count 2 2006.174.00:28:52.76#ibcon#read 6, iclass 23, count 2 2006.174.00:28:52.76#ibcon#end of sib2, iclass 23, count 2 2006.174.00:28:52.76#ibcon#*after write, iclass 23, count 2 2006.174.00:28:52.76#ibcon#*before return 0, iclass 23, count 2 2006.174.00:28:52.76#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.174.00:28:52.76#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.174.00:28:52.76#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.174.00:28:52.76#ibcon#ireg 7 cls_cnt 0 2006.174.00:28:52.76#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.174.00:28:52.88#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.174.00:28:52.88#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.174.00:28:52.88#ibcon#enter wrdev, iclass 23, count 0 2006.174.00:28:52.88#ibcon#first serial, iclass 23, count 0 2006.174.00:28:52.88#ibcon#enter sib2, iclass 23, count 0 2006.174.00:28:52.88#ibcon#flushed, iclass 23, count 0 2006.174.00:28:52.88#ibcon#about to write, iclass 23, count 0 2006.174.00:28:52.88#ibcon#wrote, iclass 23, count 0 2006.174.00:28:52.88#ibcon#about to read 3, iclass 23, count 0 2006.174.00:28:52.90#ibcon#read 3, iclass 23, count 0 2006.174.00:28:52.90#ibcon#about to read 4, iclass 23, count 0 2006.174.00:28:52.90#ibcon#read 4, iclass 23, count 0 2006.174.00:28:52.90#ibcon#about to read 5, iclass 23, count 0 2006.174.00:28:52.90#ibcon#read 5, iclass 23, count 0 2006.174.00:28:52.90#ibcon#about to read 6, iclass 23, count 0 2006.174.00:28:52.90#ibcon#read 6, iclass 23, count 0 2006.174.00:28:52.90#ibcon#end of sib2, iclass 23, count 0 2006.174.00:28:52.90#ibcon#*mode == 0, iclass 23, count 0 2006.174.00:28:52.90#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.174.00:28:52.90#ibcon#[25=USB\r\n] 2006.174.00:28:52.90#ibcon#*before write, iclass 23, count 0 2006.174.00:28:52.90#ibcon#enter sib2, iclass 23, count 0 2006.174.00:28:52.90#ibcon#flushed, iclass 23, count 0 2006.174.00:28:52.90#ibcon#about to write, iclass 23, count 0 2006.174.00:28:52.90#ibcon#wrote, iclass 23, count 0 2006.174.00:28:52.90#ibcon#about to read 3, iclass 23, count 0 2006.174.00:28:52.93#ibcon#read 3, iclass 23, count 0 2006.174.00:28:52.93#ibcon#about to read 4, iclass 23, count 0 2006.174.00:28:52.93#ibcon#read 4, iclass 23, count 0 2006.174.00:28:52.93#ibcon#about to read 5, iclass 23, count 0 2006.174.00:28:52.93#ibcon#read 5, iclass 23, count 0 2006.174.00:28:52.93#ibcon#about to read 6, iclass 23, count 0 2006.174.00:28:52.93#ibcon#read 6, iclass 23, count 0 2006.174.00:28:52.93#ibcon#end of sib2, iclass 23, count 0 2006.174.00:28:52.93#ibcon#*after write, iclass 23, count 0 2006.174.00:28:52.93#ibcon#*before return 0, iclass 23, count 0 2006.174.00:28:52.93#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.174.00:28:52.93#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.174.00:28:52.93#ibcon#about to clear, iclass 23 cls_cnt 0 2006.174.00:28:52.93#ibcon#cleared, iclass 23 cls_cnt 0 2006.174.00:28:52.93$vck44/vblo=1,629.99 2006.174.00:28:52.93#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.174.00:28:52.93#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.174.00:28:52.93#ibcon#ireg 17 cls_cnt 0 2006.174.00:28:52.93#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.174.00:28:52.93#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.174.00:28:52.93#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.174.00:28:52.93#ibcon#enter wrdev, iclass 25, count 0 2006.174.00:28:52.93#ibcon#first serial, iclass 25, count 0 2006.174.00:28:52.93#ibcon#enter sib2, iclass 25, count 0 2006.174.00:28:52.93#ibcon#flushed, iclass 25, count 0 2006.174.00:28:52.93#ibcon#about to write, iclass 25, count 0 2006.174.00:28:52.93#ibcon#wrote, iclass 25, count 0 2006.174.00:28:52.93#ibcon#about to read 3, iclass 25, count 0 2006.174.00:28:52.95#ibcon#read 3, iclass 25, count 0 2006.174.00:28:52.95#ibcon#about to read 4, iclass 25, count 0 2006.174.00:28:52.95#ibcon#read 4, iclass 25, count 0 2006.174.00:28:52.95#ibcon#about to read 5, iclass 25, count 0 2006.174.00:28:52.95#ibcon#read 5, iclass 25, count 0 2006.174.00:28:52.95#ibcon#about to read 6, iclass 25, count 0 2006.174.00:28:52.95#ibcon#read 6, iclass 25, count 0 2006.174.00:28:52.95#ibcon#end of sib2, iclass 25, count 0 2006.174.00:28:52.95#ibcon#*mode == 0, iclass 25, count 0 2006.174.00:28:52.95#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.174.00:28:52.95#ibcon#[28=FRQ=01,629.99\r\n] 2006.174.00:28:52.95#ibcon#*before write, iclass 25, count 0 2006.174.00:28:52.95#ibcon#enter sib2, iclass 25, count 0 2006.174.00:28:52.95#ibcon#flushed, iclass 25, count 0 2006.174.00:28:52.95#ibcon#about to write, iclass 25, count 0 2006.174.00:28:52.95#ibcon#wrote, iclass 25, count 0 2006.174.00:28:52.95#ibcon#about to read 3, iclass 25, count 0 2006.174.00:28:52.99#ibcon#read 3, iclass 25, count 0 2006.174.00:28:52.99#ibcon#about to read 4, iclass 25, count 0 2006.174.00:28:52.99#ibcon#read 4, iclass 25, count 0 2006.174.00:28:52.99#ibcon#about to read 5, iclass 25, count 0 2006.174.00:28:52.99#ibcon#read 5, iclass 25, count 0 2006.174.00:28:52.99#ibcon#about to read 6, iclass 25, count 0 2006.174.00:28:52.99#ibcon#read 6, iclass 25, count 0 2006.174.00:28:52.99#ibcon#end of sib2, iclass 25, count 0 2006.174.00:28:52.99#ibcon#*after write, iclass 25, count 0 2006.174.00:28:52.99#ibcon#*before return 0, iclass 25, count 0 2006.174.00:28:52.99#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.174.00:28:52.99#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.174.00:28:52.99#ibcon#about to clear, iclass 25 cls_cnt 0 2006.174.00:28:52.99#ibcon#cleared, iclass 25 cls_cnt 0 2006.174.00:28:52.99$vck44/vb=1,4 2006.174.00:28:52.99#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.174.00:28:52.99#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.174.00:28:52.99#ibcon#ireg 11 cls_cnt 2 2006.174.00:28:52.99#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.174.00:28:52.99#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.174.00:28:52.99#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.174.00:28:52.99#ibcon#enter wrdev, iclass 27, count 2 2006.174.00:28:52.99#ibcon#first serial, iclass 27, count 2 2006.174.00:28:52.99#ibcon#enter sib2, iclass 27, count 2 2006.174.00:28:52.99#ibcon#flushed, iclass 27, count 2 2006.174.00:28:52.99#ibcon#about to write, iclass 27, count 2 2006.174.00:28:52.99#ibcon#wrote, iclass 27, count 2 2006.174.00:28:52.99#ibcon#about to read 3, iclass 27, count 2 2006.174.00:28:53.01#ibcon#read 3, iclass 27, count 2 2006.174.00:28:53.01#ibcon#about to read 4, iclass 27, count 2 2006.174.00:28:53.01#ibcon#read 4, iclass 27, count 2 2006.174.00:28:53.01#ibcon#about to read 5, iclass 27, count 2 2006.174.00:28:53.01#ibcon#read 5, iclass 27, count 2 2006.174.00:28:53.01#ibcon#about to read 6, iclass 27, count 2 2006.174.00:28:53.01#ibcon#read 6, iclass 27, count 2 2006.174.00:28:53.01#ibcon#end of sib2, iclass 27, count 2 2006.174.00:28:53.01#ibcon#*mode == 0, iclass 27, count 2 2006.174.00:28:53.01#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.174.00:28:53.01#ibcon#[27=AT01-04\r\n] 2006.174.00:28:53.01#ibcon#*before write, iclass 27, count 2 2006.174.00:28:53.01#ibcon#enter sib2, iclass 27, count 2 2006.174.00:28:53.01#ibcon#flushed, iclass 27, count 2 2006.174.00:28:53.01#ibcon#about to write, iclass 27, count 2 2006.174.00:28:53.01#ibcon#wrote, iclass 27, count 2 2006.174.00:28:53.01#ibcon#about to read 3, iclass 27, count 2 2006.174.00:28:53.04#ibcon#read 3, iclass 27, count 2 2006.174.00:28:53.04#ibcon#about to read 4, iclass 27, count 2 2006.174.00:28:53.04#ibcon#read 4, iclass 27, count 2 2006.174.00:28:53.04#ibcon#about to read 5, iclass 27, count 2 2006.174.00:28:53.04#ibcon#read 5, iclass 27, count 2 2006.174.00:28:53.04#ibcon#about to read 6, iclass 27, count 2 2006.174.00:28:53.04#ibcon#read 6, iclass 27, count 2 2006.174.00:28:53.04#ibcon#end of sib2, iclass 27, count 2 2006.174.00:28:53.04#ibcon#*after write, iclass 27, count 2 2006.174.00:28:53.04#ibcon#*before return 0, iclass 27, count 2 2006.174.00:28:53.04#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.174.00:28:53.04#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.174.00:28:53.04#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.174.00:28:53.04#ibcon#ireg 7 cls_cnt 0 2006.174.00:28:53.04#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.174.00:28:53.16#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.174.00:28:53.16#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.174.00:28:53.16#ibcon#enter wrdev, iclass 27, count 0 2006.174.00:28:53.16#ibcon#first serial, iclass 27, count 0 2006.174.00:28:53.16#ibcon#enter sib2, iclass 27, count 0 2006.174.00:28:53.16#ibcon#flushed, iclass 27, count 0 2006.174.00:28:53.16#ibcon#about to write, iclass 27, count 0 2006.174.00:28:53.16#ibcon#wrote, iclass 27, count 0 2006.174.00:28:53.16#ibcon#about to read 3, iclass 27, count 0 2006.174.00:28:53.18#ibcon#read 3, iclass 27, count 0 2006.174.00:28:53.18#ibcon#about to read 4, iclass 27, count 0 2006.174.00:28:53.18#ibcon#read 4, iclass 27, count 0 2006.174.00:28:53.18#ibcon#about to read 5, iclass 27, count 0 2006.174.00:28:53.18#ibcon#read 5, iclass 27, count 0 2006.174.00:28:53.18#ibcon#about to read 6, iclass 27, count 0 2006.174.00:28:53.18#ibcon#read 6, iclass 27, count 0 2006.174.00:28:53.18#ibcon#end of sib2, iclass 27, count 0 2006.174.00:28:53.18#ibcon#*mode == 0, iclass 27, count 0 2006.174.00:28:53.18#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.174.00:28:53.18#ibcon#[27=USB\r\n] 2006.174.00:28:53.18#ibcon#*before write, iclass 27, count 0 2006.174.00:28:53.18#ibcon#enter sib2, iclass 27, count 0 2006.174.00:28:53.18#ibcon#flushed, iclass 27, count 0 2006.174.00:28:53.18#ibcon#about to write, iclass 27, count 0 2006.174.00:28:53.18#ibcon#wrote, iclass 27, count 0 2006.174.00:28:53.18#ibcon#about to read 3, iclass 27, count 0 2006.174.00:28:53.21#ibcon#read 3, iclass 27, count 0 2006.174.00:28:53.21#ibcon#about to read 4, iclass 27, count 0 2006.174.00:28:53.21#ibcon#read 4, iclass 27, count 0 2006.174.00:28:53.21#ibcon#about to read 5, iclass 27, count 0 2006.174.00:28:53.21#ibcon#read 5, iclass 27, count 0 2006.174.00:28:53.21#ibcon#about to read 6, iclass 27, count 0 2006.174.00:28:53.21#ibcon#read 6, iclass 27, count 0 2006.174.00:28:53.21#ibcon#end of sib2, iclass 27, count 0 2006.174.00:28:53.21#ibcon#*after write, iclass 27, count 0 2006.174.00:28:53.21#ibcon#*before return 0, iclass 27, count 0 2006.174.00:28:53.21#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.174.00:28:53.21#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.174.00:28:53.21#ibcon#about to clear, iclass 27 cls_cnt 0 2006.174.00:28:53.21#ibcon#cleared, iclass 27 cls_cnt 0 2006.174.00:28:53.21$vck44/vblo=2,634.99 2006.174.00:28:53.21#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.174.00:28:53.21#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.174.00:28:53.21#ibcon#ireg 17 cls_cnt 0 2006.174.00:28:53.21#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.174.00:28:53.21#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.174.00:28:53.21#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.174.00:28:53.21#ibcon#enter wrdev, iclass 29, count 0 2006.174.00:28:53.21#ibcon#first serial, iclass 29, count 0 2006.174.00:28:53.21#ibcon#enter sib2, iclass 29, count 0 2006.174.00:28:53.21#ibcon#flushed, iclass 29, count 0 2006.174.00:28:53.21#ibcon#about to write, iclass 29, count 0 2006.174.00:28:53.21#ibcon#wrote, iclass 29, count 0 2006.174.00:28:53.21#ibcon#about to read 3, iclass 29, count 0 2006.174.00:28:53.23#ibcon#read 3, iclass 29, count 0 2006.174.00:28:53.23#ibcon#about to read 4, iclass 29, count 0 2006.174.00:28:53.23#ibcon#read 4, iclass 29, count 0 2006.174.00:28:53.23#ibcon#about to read 5, iclass 29, count 0 2006.174.00:28:53.23#ibcon#read 5, iclass 29, count 0 2006.174.00:28:53.23#ibcon#about to read 6, iclass 29, count 0 2006.174.00:28:53.23#ibcon#read 6, iclass 29, count 0 2006.174.00:28:53.23#ibcon#end of sib2, iclass 29, count 0 2006.174.00:28:53.23#ibcon#*mode == 0, iclass 29, count 0 2006.174.00:28:53.23#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.174.00:28:53.23#ibcon#[28=FRQ=02,634.99\r\n] 2006.174.00:28:53.23#ibcon#*before write, iclass 29, count 0 2006.174.00:28:53.23#ibcon#enter sib2, iclass 29, count 0 2006.174.00:28:53.23#ibcon#flushed, iclass 29, count 0 2006.174.00:28:53.23#ibcon#about to write, iclass 29, count 0 2006.174.00:28:53.23#ibcon#wrote, iclass 29, count 0 2006.174.00:28:53.23#ibcon#about to read 3, iclass 29, count 0 2006.174.00:28:53.27#ibcon#read 3, iclass 29, count 0 2006.174.00:28:53.27#ibcon#about to read 4, iclass 29, count 0 2006.174.00:28:53.27#ibcon#read 4, iclass 29, count 0 2006.174.00:28:53.27#ibcon#about to read 5, iclass 29, count 0 2006.174.00:28:53.27#ibcon#read 5, iclass 29, count 0 2006.174.00:28:53.27#ibcon#about to read 6, iclass 29, count 0 2006.174.00:28:53.27#ibcon#read 6, iclass 29, count 0 2006.174.00:28:53.27#ibcon#end of sib2, iclass 29, count 0 2006.174.00:28:53.27#ibcon#*after write, iclass 29, count 0 2006.174.00:28:53.27#ibcon#*before return 0, iclass 29, count 0 2006.174.00:28:53.27#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.174.00:28:53.27#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.174.00:28:53.27#ibcon#about to clear, iclass 29 cls_cnt 0 2006.174.00:28:53.27#ibcon#cleared, iclass 29 cls_cnt 0 2006.174.00:28:53.27$vck44/vb=2,4 2006.174.00:28:53.27#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.174.00:28:53.27#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.174.00:28:53.27#ibcon#ireg 11 cls_cnt 2 2006.174.00:28:53.27#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.174.00:28:53.33#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.174.00:28:53.33#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.174.00:28:53.33#ibcon#enter wrdev, iclass 31, count 2 2006.174.00:28:53.33#ibcon#first serial, iclass 31, count 2 2006.174.00:28:53.33#ibcon#enter sib2, iclass 31, count 2 2006.174.00:28:53.33#ibcon#flushed, iclass 31, count 2 2006.174.00:28:53.33#ibcon#about to write, iclass 31, count 2 2006.174.00:28:53.33#ibcon#wrote, iclass 31, count 2 2006.174.00:28:53.33#ibcon#about to read 3, iclass 31, count 2 2006.174.00:28:53.35#ibcon#read 3, iclass 31, count 2 2006.174.00:28:53.35#ibcon#about to read 4, iclass 31, count 2 2006.174.00:28:53.35#ibcon#read 4, iclass 31, count 2 2006.174.00:28:53.35#ibcon#about to read 5, iclass 31, count 2 2006.174.00:28:53.35#ibcon#read 5, iclass 31, count 2 2006.174.00:28:53.35#ibcon#about to read 6, iclass 31, count 2 2006.174.00:28:53.35#ibcon#read 6, iclass 31, count 2 2006.174.00:28:53.35#ibcon#end of sib2, iclass 31, count 2 2006.174.00:28:53.35#ibcon#*mode == 0, iclass 31, count 2 2006.174.00:28:53.35#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.174.00:28:53.35#ibcon#[27=AT02-04\r\n] 2006.174.00:28:53.35#ibcon#*before write, iclass 31, count 2 2006.174.00:28:53.35#ibcon#enter sib2, iclass 31, count 2 2006.174.00:28:53.35#ibcon#flushed, iclass 31, count 2 2006.174.00:28:53.35#ibcon#about to write, iclass 31, count 2 2006.174.00:28:53.35#ibcon#wrote, iclass 31, count 2 2006.174.00:28:53.35#ibcon#about to read 3, iclass 31, count 2 2006.174.00:28:53.38#ibcon#read 3, iclass 31, count 2 2006.174.00:28:53.38#ibcon#about to read 4, iclass 31, count 2 2006.174.00:28:53.38#ibcon#read 4, iclass 31, count 2 2006.174.00:28:53.38#ibcon#about to read 5, iclass 31, count 2 2006.174.00:28:53.38#ibcon#read 5, iclass 31, count 2 2006.174.00:28:53.38#ibcon#about to read 6, iclass 31, count 2 2006.174.00:28:53.38#ibcon#read 6, iclass 31, count 2 2006.174.00:28:53.38#ibcon#end of sib2, iclass 31, count 2 2006.174.00:28:53.38#ibcon#*after write, iclass 31, count 2 2006.174.00:28:53.38#ibcon#*before return 0, iclass 31, count 2 2006.174.00:28:53.38#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.174.00:28:53.38#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.174.00:28:53.38#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.174.00:28:53.38#ibcon#ireg 7 cls_cnt 0 2006.174.00:28:53.38#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.174.00:28:53.50#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.174.00:28:53.50#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.174.00:28:53.50#ibcon#enter wrdev, iclass 31, count 0 2006.174.00:28:53.50#ibcon#first serial, iclass 31, count 0 2006.174.00:28:53.50#ibcon#enter sib2, iclass 31, count 0 2006.174.00:28:53.50#ibcon#flushed, iclass 31, count 0 2006.174.00:28:53.50#ibcon#about to write, iclass 31, count 0 2006.174.00:28:53.50#ibcon#wrote, iclass 31, count 0 2006.174.00:28:53.50#ibcon#about to read 3, iclass 31, count 0 2006.174.00:28:53.52#ibcon#read 3, iclass 31, count 0 2006.174.00:28:53.52#ibcon#about to read 4, iclass 31, count 0 2006.174.00:28:53.52#ibcon#read 4, iclass 31, count 0 2006.174.00:28:53.52#ibcon#about to read 5, iclass 31, count 0 2006.174.00:28:53.52#ibcon#read 5, iclass 31, count 0 2006.174.00:28:53.52#ibcon#about to read 6, iclass 31, count 0 2006.174.00:28:53.52#ibcon#read 6, iclass 31, count 0 2006.174.00:28:53.52#ibcon#end of sib2, iclass 31, count 0 2006.174.00:28:53.52#ibcon#*mode == 0, iclass 31, count 0 2006.174.00:28:53.52#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.174.00:28:53.52#ibcon#[27=USB\r\n] 2006.174.00:28:53.52#ibcon#*before write, iclass 31, count 0 2006.174.00:28:53.52#ibcon#enter sib2, iclass 31, count 0 2006.174.00:28:53.52#ibcon#flushed, iclass 31, count 0 2006.174.00:28:53.52#ibcon#about to write, iclass 31, count 0 2006.174.00:28:53.52#ibcon#wrote, iclass 31, count 0 2006.174.00:28:53.52#ibcon#about to read 3, iclass 31, count 0 2006.174.00:28:53.55#ibcon#read 3, iclass 31, count 0 2006.174.00:28:53.55#ibcon#about to read 4, iclass 31, count 0 2006.174.00:28:53.55#ibcon#read 4, iclass 31, count 0 2006.174.00:28:53.55#ibcon#about to read 5, iclass 31, count 0 2006.174.00:28:53.55#ibcon#read 5, iclass 31, count 0 2006.174.00:28:53.55#ibcon#about to read 6, iclass 31, count 0 2006.174.00:28:53.55#ibcon#read 6, iclass 31, count 0 2006.174.00:28:53.55#ibcon#end of sib2, iclass 31, count 0 2006.174.00:28:53.55#ibcon#*after write, iclass 31, count 0 2006.174.00:28:53.55#ibcon#*before return 0, iclass 31, count 0 2006.174.00:28:53.55#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.174.00:28:53.55#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.174.00:28:53.55#ibcon#about to clear, iclass 31 cls_cnt 0 2006.174.00:28:53.55#ibcon#cleared, iclass 31 cls_cnt 0 2006.174.00:28:53.55$vck44/vblo=3,649.99 2006.174.00:28:53.55#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.174.00:28:53.55#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.174.00:28:53.55#ibcon#ireg 17 cls_cnt 0 2006.174.00:28:53.55#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.174.00:28:53.55#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.174.00:28:53.55#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.174.00:28:53.55#ibcon#enter wrdev, iclass 33, count 0 2006.174.00:28:53.55#ibcon#first serial, iclass 33, count 0 2006.174.00:28:53.55#ibcon#enter sib2, iclass 33, count 0 2006.174.00:28:53.55#ibcon#flushed, iclass 33, count 0 2006.174.00:28:53.55#ibcon#about to write, iclass 33, count 0 2006.174.00:28:53.55#ibcon#wrote, iclass 33, count 0 2006.174.00:28:53.55#ibcon#about to read 3, iclass 33, count 0 2006.174.00:28:53.57#ibcon#read 3, iclass 33, count 0 2006.174.00:28:53.57#ibcon#about to read 4, iclass 33, count 0 2006.174.00:28:53.57#ibcon#read 4, iclass 33, count 0 2006.174.00:28:53.57#ibcon#about to read 5, iclass 33, count 0 2006.174.00:28:53.57#ibcon#read 5, iclass 33, count 0 2006.174.00:28:53.57#ibcon#about to read 6, iclass 33, count 0 2006.174.00:28:53.57#ibcon#read 6, iclass 33, count 0 2006.174.00:28:53.57#ibcon#end of sib2, iclass 33, count 0 2006.174.00:28:53.57#ibcon#*mode == 0, iclass 33, count 0 2006.174.00:28:53.57#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.174.00:28:53.57#ibcon#[28=FRQ=03,649.99\r\n] 2006.174.00:28:53.57#ibcon#*before write, iclass 33, count 0 2006.174.00:28:53.57#ibcon#enter sib2, iclass 33, count 0 2006.174.00:28:53.57#ibcon#flushed, iclass 33, count 0 2006.174.00:28:53.57#ibcon#about to write, iclass 33, count 0 2006.174.00:28:53.57#ibcon#wrote, iclass 33, count 0 2006.174.00:28:53.57#ibcon#about to read 3, iclass 33, count 0 2006.174.00:28:53.61#ibcon#read 3, iclass 33, count 0 2006.174.00:28:53.61#ibcon#about to read 4, iclass 33, count 0 2006.174.00:28:53.61#ibcon#read 4, iclass 33, count 0 2006.174.00:28:53.61#ibcon#about to read 5, iclass 33, count 0 2006.174.00:28:53.61#ibcon#read 5, iclass 33, count 0 2006.174.00:28:53.61#ibcon#about to read 6, iclass 33, count 0 2006.174.00:28:53.61#ibcon#read 6, iclass 33, count 0 2006.174.00:28:53.61#ibcon#end of sib2, iclass 33, count 0 2006.174.00:28:53.61#ibcon#*after write, iclass 33, count 0 2006.174.00:28:53.61#ibcon#*before return 0, iclass 33, count 0 2006.174.00:28:53.61#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.174.00:28:53.61#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.174.00:28:53.61#ibcon#about to clear, iclass 33 cls_cnt 0 2006.174.00:28:53.61#ibcon#cleared, iclass 33 cls_cnt 0 2006.174.00:28:53.61$vck44/vb=3,4 2006.174.00:28:53.61#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.174.00:28:53.61#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.174.00:28:53.61#ibcon#ireg 11 cls_cnt 2 2006.174.00:28:53.61#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.174.00:28:53.67#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.174.00:28:53.67#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.174.00:28:53.67#ibcon#enter wrdev, iclass 35, count 2 2006.174.00:28:53.67#ibcon#first serial, iclass 35, count 2 2006.174.00:28:53.67#ibcon#enter sib2, iclass 35, count 2 2006.174.00:28:53.67#ibcon#flushed, iclass 35, count 2 2006.174.00:28:53.67#ibcon#about to write, iclass 35, count 2 2006.174.00:28:53.67#ibcon#wrote, iclass 35, count 2 2006.174.00:28:53.67#ibcon#about to read 3, iclass 35, count 2 2006.174.00:28:53.69#ibcon#read 3, iclass 35, count 2 2006.174.00:28:53.69#ibcon#about to read 4, iclass 35, count 2 2006.174.00:28:53.69#ibcon#read 4, iclass 35, count 2 2006.174.00:28:53.69#ibcon#about to read 5, iclass 35, count 2 2006.174.00:28:53.69#ibcon#read 5, iclass 35, count 2 2006.174.00:28:53.69#ibcon#about to read 6, iclass 35, count 2 2006.174.00:28:53.69#ibcon#read 6, iclass 35, count 2 2006.174.00:28:53.69#ibcon#end of sib2, iclass 35, count 2 2006.174.00:28:53.69#ibcon#*mode == 0, iclass 35, count 2 2006.174.00:28:53.69#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.174.00:28:53.69#ibcon#[27=AT03-04\r\n] 2006.174.00:28:53.69#ibcon#*before write, iclass 35, count 2 2006.174.00:28:53.69#ibcon#enter sib2, iclass 35, count 2 2006.174.00:28:53.69#ibcon#flushed, iclass 35, count 2 2006.174.00:28:53.69#ibcon#about to write, iclass 35, count 2 2006.174.00:28:53.69#ibcon#wrote, iclass 35, count 2 2006.174.00:28:53.69#ibcon#about to read 3, iclass 35, count 2 2006.174.00:28:53.72#ibcon#read 3, iclass 35, count 2 2006.174.00:28:53.72#ibcon#about to read 4, iclass 35, count 2 2006.174.00:28:53.72#ibcon#read 4, iclass 35, count 2 2006.174.00:28:53.72#ibcon#about to read 5, iclass 35, count 2 2006.174.00:28:53.72#ibcon#read 5, iclass 35, count 2 2006.174.00:28:53.72#ibcon#about to read 6, iclass 35, count 2 2006.174.00:28:53.72#ibcon#read 6, iclass 35, count 2 2006.174.00:28:53.72#ibcon#end of sib2, iclass 35, count 2 2006.174.00:28:53.72#ibcon#*after write, iclass 35, count 2 2006.174.00:28:53.72#ibcon#*before return 0, iclass 35, count 2 2006.174.00:28:53.72#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.174.00:28:53.72#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.174.00:28:53.72#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.174.00:28:53.72#ibcon#ireg 7 cls_cnt 0 2006.174.00:28:53.72#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.174.00:28:53.84#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.174.00:28:53.84#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.174.00:28:53.84#ibcon#enter wrdev, iclass 35, count 0 2006.174.00:28:53.84#ibcon#first serial, iclass 35, count 0 2006.174.00:28:53.84#ibcon#enter sib2, iclass 35, count 0 2006.174.00:28:53.84#ibcon#flushed, iclass 35, count 0 2006.174.00:28:53.84#ibcon#about to write, iclass 35, count 0 2006.174.00:28:53.84#ibcon#wrote, iclass 35, count 0 2006.174.00:28:53.84#ibcon#about to read 3, iclass 35, count 0 2006.174.00:28:53.86#ibcon#read 3, iclass 35, count 0 2006.174.00:28:53.86#ibcon#about to read 4, iclass 35, count 0 2006.174.00:28:53.86#ibcon#read 4, iclass 35, count 0 2006.174.00:28:53.86#ibcon#about to read 5, iclass 35, count 0 2006.174.00:28:53.86#ibcon#read 5, iclass 35, count 0 2006.174.00:28:53.86#ibcon#about to read 6, iclass 35, count 0 2006.174.00:28:53.86#ibcon#read 6, iclass 35, count 0 2006.174.00:28:53.86#ibcon#end of sib2, iclass 35, count 0 2006.174.00:28:53.86#ibcon#*mode == 0, iclass 35, count 0 2006.174.00:28:53.86#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.174.00:28:53.86#ibcon#[27=USB\r\n] 2006.174.00:28:53.86#ibcon#*before write, iclass 35, count 0 2006.174.00:28:53.86#ibcon#enter sib2, iclass 35, count 0 2006.174.00:28:53.86#ibcon#flushed, iclass 35, count 0 2006.174.00:28:53.86#ibcon#about to write, iclass 35, count 0 2006.174.00:28:53.86#ibcon#wrote, iclass 35, count 0 2006.174.00:28:53.86#ibcon#about to read 3, iclass 35, count 0 2006.174.00:28:53.89#ibcon#read 3, iclass 35, count 0 2006.174.00:28:53.89#ibcon#about to read 4, iclass 35, count 0 2006.174.00:28:53.89#ibcon#read 4, iclass 35, count 0 2006.174.00:28:53.89#ibcon#about to read 5, iclass 35, count 0 2006.174.00:28:53.89#ibcon#read 5, iclass 35, count 0 2006.174.00:28:53.89#ibcon#about to read 6, iclass 35, count 0 2006.174.00:28:53.89#ibcon#read 6, iclass 35, count 0 2006.174.00:28:53.89#ibcon#end of sib2, iclass 35, count 0 2006.174.00:28:53.89#ibcon#*after write, iclass 35, count 0 2006.174.00:28:53.89#ibcon#*before return 0, iclass 35, count 0 2006.174.00:28:53.89#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.174.00:28:53.89#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.174.00:28:53.89#ibcon#about to clear, iclass 35 cls_cnt 0 2006.174.00:28:53.89#ibcon#cleared, iclass 35 cls_cnt 0 2006.174.00:28:53.89$vck44/vblo=4,679.99 2006.174.00:28:53.89#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.174.00:28:53.89#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.174.00:28:53.89#ibcon#ireg 17 cls_cnt 0 2006.174.00:28:53.89#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.174.00:28:53.89#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.174.00:28:53.89#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.174.00:28:53.89#ibcon#enter wrdev, iclass 37, count 0 2006.174.00:28:53.89#ibcon#first serial, iclass 37, count 0 2006.174.00:28:53.89#ibcon#enter sib2, iclass 37, count 0 2006.174.00:28:53.89#ibcon#flushed, iclass 37, count 0 2006.174.00:28:53.89#ibcon#about to write, iclass 37, count 0 2006.174.00:28:53.89#ibcon#wrote, iclass 37, count 0 2006.174.00:28:53.89#ibcon#about to read 3, iclass 37, count 0 2006.174.00:28:53.91#ibcon#read 3, iclass 37, count 0 2006.174.00:28:53.91#ibcon#about to read 4, iclass 37, count 0 2006.174.00:28:53.91#ibcon#read 4, iclass 37, count 0 2006.174.00:28:53.91#ibcon#about to read 5, iclass 37, count 0 2006.174.00:28:53.91#ibcon#read 5, iclass 37, count 0 2006.174.00:28:53.91#ibcon#about to read 6, iclass 37, count 0 2006.174.00:28:53.91#ibcon#read 6, iclass 37, count 0 2006.174.00:28:53.91#ibcon#end of sib2, iclass 37, count 0 2006.174.00:28:53.91#ibcon#*mode == 0, iclass 37, count 0 2006.174.00:28:53.91#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.174.00:28:53.91#ibcon#[28=FRQ=04,679.99\r\n] 2006.174.00:28:53.91#ibcon#*before write, iclass 37, count 0 2006.174.00:28:53.91#ibcon#enter sib2, iclass 37, count 0 2006.174.00:28:53.91#ibcon#flushed, iclass 37, count 0 2006.174.00:28:53.91#ibcon#about to write, iclass 37, count 0 2006.174.00:28:53.91#ibcon#wrote, iclass 37, count 0 2006.174.00:28:53.91#ibcon#about to read 3, iclass 37, count 0 2006.174.00:28:53.95#ibcon#read 3, iclass 37, count 0 2006.174.00:28:53.95#ibcon#about to read 4, iclass 37, count 0 2006.174.00:28:53.95#ibcon#read 4, iclass 37, count 0 2006.174.00:28:53.95#ibcon#about to read 5, iclass 37, count 0 2006.174.00:28:53.95#ibcon#read 5, iclass 37, count 0 2006.174.00:28:53.95#ibcon#about to read 6, iclass 37, count 0 2006.174.00:28:53.95#ibcon#read 6, iclass 37, count 0 2006.174.00:28:53.95#ibcon#end of sib2, iclass 37, count 0 2006.174.00:28:53.95#ibcon#*after write, iclass 37, count 0 2006.174.00:28:53.95#ibcon#*before return 0, iclass 37, count 0 2006.174.00:28:53.95#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.174.00:28:53.95#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.174.00:28:53.95#ibcon#about to clear, iclass 37 cls_cnt 0 2006.174.00:28:53.95#ibcon#cleared, iclass 37 cls_cnt 0 2006.174.00:28:53.95$vck44/vb=4,4 2006.174.00:28:53.95#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.174.00:28:53.95#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.174.00:28:53.95#ibcon#ireg 11 cls_cnt 2 2006.174.00:28:53.95#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.174.00:28:54.01#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.174.00:28:54.01#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.174.00:28:54.01#ibcon#enter wrdev, iclass 39, count 2 2006.174.00:28:54.01#ibcon#first serial, iclass 39, count 2 2006.174.00:28:54.01#ibcon#enter sib2, iclass 39, count 2 2006.174.00:28:54.01#ibcon#flushed, iclass 39, count 2 2006.174.00:28:54.01#ibcon#about to write, iclass 39, count 2 2006.174.00:28:54.01#ibcon#wrote, iclass 39, count 2 2006.174.00:28:54.01#ibcon#about to read 3, iclass 39, count 2 2006.174.00:28:54.03#ibcon#read 3, iclass 39, count 2 2006.174.00:28:54.03#ibcon#about to read 4, iclass 39, count 2 2006.174.00:28:54.03#ibcon#read 4, iclass 39, count 2 2006.174.00:28:54.03#ibcon#about to read 5, iclass 39, count 2 2006.174.00:28:54.03#ibcon#read 5, iclass 39, count 2 2006.174.00:28:54.03#ibcon#about to read 6, iclass 39, count 2 2006.174.00:28:54.03#ibcon#read 6, iclass 39, count 2 2006.174.00:28:54.03#ibcon#end of sib2, iclass 39, count 2 2006.174.00:28:54.03#ibcon#*mode == 0, iclass 39, count 2 2006.174.00:28:54.03#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.174.00:28:54.03#ibcon#[27=AT04-04\r\n] 2006.174.00:28:54.03#ibcon#*before write, iclass 39, count 2 2006.174.00:28:54.03#ibcon#enter sib2, iclass 39, count 2 2006.174.00:28:54.03#ibcon#flushed, iclass 39, count 2 2006.174.00:28:54.03#ibcon#about to write, iclass 39, count 2 2006.174.00:28:54.03#ibcon#wrote, iclass 39, count 2 2006.174.00:28:54.03#ibcon#about to read 3, iclass 39, count 2 2006.174.00:28:54.06#ibcon#read 3, iclass 39, count 2 2006.174.00:28:54.06#ibcon#about to read 4, iclass 39, count 2 2006.174.00:28:54.06#ibcon#read 4, iclass 39, count 2 2006.174.00:28:54.06#ibcon#about to read 5, iclass 39, count 2 2006.174.00:28:54.06#ibcon#read 5, iclass 39, count 2 2006.174.00:28:54.06#ibcon#about to read 6, iclass 39, count 2 2006.174.00:28:54.06#ibcon#read 6, iclass 39, count 2 2006.174.00:28:54.06#ibcon#end of sib2, iclass 39, count 2 2006.174.00:28:54.06#ibcon#*after write, iclass 39, count 2 2006.174.00:28:54.06#ibcon#*before return 0, iclass 39, count 2 2006.174.00:28:54.06#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.174.00:28:54.06#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.174.00:28:54.06#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.174.00:28:54.06#ibcon#ireg 7 cls_cnt 0 2006.174.00:28:54.06#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.174.00:28:54.18#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.174.00:28:54.18#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.174.00:28:54.18#ibcon#enter wrdev, iclass 39, count 0 2006.174.00:28:54.18#ibcon#first serial, iclass 39, count 0 2006.174.00:28:54.18#ibcon#enter sib2, iclass 39, count 0 2006.174.00:28:54.18#ibcon#flushed, iclass 39, count 0 2006.174.00:28:54.18#ibcon#about to write, iclass 39, count 0 2006.174.00:28:54.18#ibcon#wrote, iclass 39, count 0 2006.174.00:28:54.18#ibcon#about to read 3, iclass 39, count 0 2006.174.00:28:54.20#ibcon#read 3, iclass 39, count 0 2006.174.00:28:54.20#ibcon#about to read 4, iclass 39, count 0 2006.174.00:28:54.20#ibcon#read 4, iclass 39, count 0 2006.174.00:28:54.20#ibcon#about to read 5, iclass 39, count 0 2006.174.00:28:54.20#ibcon#read 5, iclass 39, count 0 2006.174.00:28:54.20#ibcon#about to read 6, iclass 39, count 0 2006.174.00:28:54.20#ibcon#read 6, iclass 39, count 0 2006.174.00:28:54.20#ibcon#end of sib2, iclass 39, count 0 2006.174.00:28:54.20#ibcon#*mode == 0, iclass 39, count 0 2006.174.00:28:54.20#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.174.00:28:54.20#ibcon#[27=USB\r\n] 2006.174.00:28:54.20#ibcon#*before write, iclass 39, count 0 2006.174.00:28:54.20#ibcon#enter sib2, iclass 39, count 0 2006.174.00:28:54.20#ibcon#flushed, iclass 39, count 0 2006.174.00:28:54.20#ibcon#about to write, iclass 39, count 0 2006.174.00:28:54.20#ibcon#wrote, iclass 39, count 0 2006.174.00:28:54.20#ibcon#about to read 3, iclass 39, count 0 2006.174.00:28:54.23#abcon#<5=/10 1.0 2.6 24.47 851003.3\r\n> 2006.174.00:28:54.23#ibcon#read 3, iclass 39, count 0 2006.174.00:28:54.23#ibcon#about to read 4, iclass 39, count 0 2006.174.00:28:54.23#ibcon#read 4, iclass 39, count 0 2006.174.00:28:54.23#ibcon#about to read 5, iclass 39, count 0 2006.174.00:28:54.23#ibcon#read 5, iclass 39, count 0 2006.174.00:28:54.23#ibcon#about to read 6, iclass 39, count 0 2006.174.00:28:54.23#ibcon#read 6, iclass 39, count 0 2006.174.00:28:54.23#ibcon#end of sib2, iclass 39, count 0 2006.174.00:28:54.23#ibcon#*after write, iclass 39, count 0 2006.174.00:28:54.23#ibcon#*before return 0, iclass 39, count 0 2006.174.00:28:54.23#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.174.00:28:54.23#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.174.00:28:54.23#ibcon#about to clear, iclass 39 cls_cnt 0 2006.174.00:28:54.23#ibcon#cleared, iclass 39 cls_cnt 0 2006.174.00:28:54.23$vck44/vblo=5,709.99 2006.174.00:28:54.23#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.174.00:28:54.23#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.174.00:28:54.23#ibcon#ireg 17 cls_cnt 0 2006.174.00:28:54.23#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.174.00:28:54.23#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.174.00:28:54.23#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.174.00:28:54.23#ibcon#enter wrdev, iclass 6, count 0 2006.174.00:28:54.23#ibcon#first serial, iclass 6, count 0 2006.174.00:28:54.23#ibcon#enter sib2, iclass 6, count 0 2006.174.00:28:54.23#ibcon#flushed, iclass 6, count 0 2006.174.00:28:54.23#ibcon#about to write, iclass 6, count 0 2006.174.00:28:54.23#ibcon#wrote, iclass 6, count 0 2006.174.00:28:54.23#ibcon#about to read 3, iclass 6, count 0 2006.174.00:28:54.25#ibcon#read 3, iclass 6, count 0 2006.174.00:28:54.25#ibcon#about to read 4, iclass 6, count 0 2006.174.00:28:54.25#ibcon#read 4, iclass 6, count 0 2006.174.00:28:54.25#ibcon#about to read 5, iclass 6, count 0 2006.174.00:28:54.25#ibcon#read 5, iclass 6, count 0 2006.174.00:28:54.25#ibcon#about to read 6, iclass 6, count 0 2006.174.00:28:54.25#ibcon#read 6, iclass 6, count 0 2006.174.00:28:54.25#ibcon#end of sib2, iclass 6, count 0 2006.174.00:28:54.25#ibcon#*mode == 0, iclass 6, count 0 2006.174.00:28:54.25#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.174.00:28:54.25#ibcon#[28=FRQ=05,709.99\r\n] 2006.174.00:28:54.25#ibcon#*before write, iclass 6, count 0 2006.174.00:28:54.25#ibcon#enter sib2, iclass 6, count 0 2006.174.00:28:54.25#ibcon#flushed, iclass 6, count 0 2006.174.00:28:54.25#ibcon#about to write, iclass 6, count 0 2006.174.00:28:54.25#ibcon#wrote, iclass 6, count 0 2006.174.00:28:54.25#ibcon#about to read 3, iclass 6, count 0 2006.174.00:28:54.25#abcon#{5=INTERFACE CLEAR} 2006.174.00:28:54.29#ibcon#read 3, iclass 6, count 0 2006.174.00:28:54.29#ibcon#about to read 4, iclass 6, count 0 2006.174.00:28:54.29#ibcon#read 4, iclass 6, count 0 2006.174.00:28:54.29#ibcon#about to read 5, iclass 6, count 0 2006.174.00:28:54.29#ibcon#read 5, iclass 6, count 0 2006.174.00:28:54.29#ibcon#about to read 6, iclass 6, count 0 2006.174.00:28:54.29#ibcon#read 6, iclass 6, count 0 2006.174.00:28:54.29#ibcon#end of sib2, iclass 6, count 0 2006.174.00:28:54.29#ibcon#*after write, iclass 6, count 0 2006.174.00:28:54.29#ibcon#*before return 0, iclass 6, count 0 2006.174.00:28:54.29#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.174.00:28:54.29#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.174.00:28:54.29#ibcon#about to clear, iclass 6 cls_cnt 0 2006.174.00:28:54.29#ibcon#cleared, iclass 6 cls_cnt 0 2006.174.00:28:54.29$vck44/vb=5,4 2006.174.00:28:54.29#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.174.00:28:54.29#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.174.00:28:54.29#ibcon#ireg 11 cls_cnt 2 2006.174.00:28:54.29#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.174.00:28:54.31#abcon#[5=S1D000X0/0*\r\n] 2006.174.00:28:54.35#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.174.00:28:54.35#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.174.00:28:54.35#ibcon#enter wrdev, iclass 10, count 2 2006.174.00:28:54.35#ibcon#first serial, iclass 10, count 2 2006.174.00:28:54.35#ibcon#enter sib2, iclass 10, count 2 2006.174.00:28:54.35#ibcon#flushed, iclass 10, count 2 2006.174.00:28:54.35#ibcon#about to write, iclass 10, count 2 2006.174.00:28:54.35#ibcon#wrote, iclass 10, count 2 2006.174.00:28:54.35#ibcon#about to read 3, iclass 10, count 2 2006.174.00:28:54.37#ibcon#read 3, iclass 10, count 2 2006.174.00:28:54.37#ibcon#about to read 4, iclass 10, count 2 2006.174.00:28:54.37#ibcon#read 4, iclass 10, count 2 2006.174.00:28:54.37#ibcon#about to read 5, iclass 10, count 2 2006.174.00:28:54.37#ibcon#read 5, iclass 10, count 2 2006.174.00:28:54.37#ibcon#about to read 6, iclass 10, count 2 2006.174.00:28:54.37#ibcon#read 6, iclass 10, count 2 2006.174.00:28:54.37#ibcon#end of sib2, iclass 10, count 2 2006.174.00:28:54.37#ibcon#*mode == 0, iclass 10, count 2 2006.174.00:28:54.37#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.174.00:28:54.37#ibcon#[27=AT05-04\r\n] 2006.174.00:28:54.37#ibcon#*before write, iclass 10, count 2 2006.174.00:28:54.37#ibcon#enter sib2, iclass 10, count 2 2006.174.00:28:54.37#ibcon#flushed, iclass 10, count 2 2006.174.00:28:54.37#ibcon#about to write, iclass 10, count 2 2006.174.00:28:54.37#ibcon#wrote, iclass 10, count 2 2006.174.00:28:54.37#ibcon#about to read 3, iclass 10, count 2 2006.174.00:28:54.40#ibcon#read 3, iclass 10, count 2 2006.174.00:28:54.40#ibcon#about to read 4, iclass 10, count 2 2006.174.00:28:54.40#ibcon#read 4, iclass 10, count 2 2006.174.00:28:54.40#ibcon#about to read 5, iclass 10, count 2 2006.174.00:28:54.40#ibcon#read 5, iclass 10, count 2 2006.174.00:28:54.40#ibcon#about to read 6, iclass 10, count 2 2006.174.00:28:54.40#ibcon#read 6, iclass 10, count 2 2006.174.00:28:54.40#ibcon#end of sib2, iclass 10, count 2 2006.174.00:28:54.40#ibcon#*after write, iclass 10, count 2 2006.174.00:28:54.40#ibcon#*before return 0, iclass 10, count 2 2006.174.00:28:54.40#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.174.00:28:54.40#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.174.00:28:54.40#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.174.00:28:54.40#ibcon#ireg 7 cls_cnt 0 2006.174.00:28:54.40#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.174.00:28:54.52#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.174.00:28:54.52#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.174.00:28:54.52#ibcon#enter wrdev, iclass 10, count 0 2006.174.00:28:54.52#ibcon#first serial, iclass 10, count 0 2006.174.00:28:54.52#ibcon#enter sib2, iclass 10, count 0 2006.174.00:28:54.52#ibcon#flushed, iclass 10, count 0 2006.174.00:28:54.52#ibcon#about to write, iclass 10, count 0 2006.174.00:28:54.52#ibcon#wrote, iclass 10, count 0 2006.174.00:28:54.52#ibcon#about to read 3, iclass 10, count 0 2006.174.00:28:54.54#ibcon#read 3, iclass 10, count 0 2006.174.00:28:54.54#ibcon#about to read 4, iclass 10, count 0 2006.174.00:28:54.54#ibcon#read 4, iclass 10, count 0 2006.174.00:28:54.54#ibcon#about to read 5, iclass 10, count 0 2006.174.00:28:54.54#ibcon#read 5, iclass 10, count 0 2006.174.00:28:54.54#ibcon#about to read 6, iclass 10, count 0 2006.174.00:28:54.54#ibcon#read 6, iclass 10, count 0 2006.174.00:28:54.54#ibcon#end of sib2, iclass 10, count 0 2006.174.00:28:54.54#ibcon#*mode == 0, iclass 10, count 0 2006.174.00:28:54.54#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.174.00:28:54.54#ibcon#[27=USB\r\n] 2006.174.00:28:54.54#ibcon#*before write, iclass 10, count 0 2006.174.00:28:54.54#ibcon#enter sib2, iclass 10, count 0 2006.174.00:28:54.54#ibcon#flushed, iclass 10, count 0 2006.174.00:28:54.54#ibcon#about to write, iclass 10, count 0 2006.174.00:28:54.54#ibcon#wrote, iclass 10, count 0 2006.174.00:28:54.54#ibcon#about to read 3, iclass 10, count 0 2006.174.00:28:54.57#ibcon#read 3, iclass 10, count 0 2006.174.00:28:54.57#ibcon#about to read 4, iclass 10, count 0 2006.174.00:28:54.57#ibcon#read 4, iclass 10, count 0 2006.174.00:28:54.57#ibcon#about to read 5, iclass 10, count 0 2006.174.00:28:54.57#ibcon#read 5, iclass 10, count 0 2006.174.00:28:54.57#ibcon#about to read 6, iclass 10, count 0 2006.174.00:28:54.57#ibcon#read 6, iclass 10, count 0 2006.174.00:28:54.57#ibcon#end of sib2, iclass 10, count 0 2006.174.00:28:54.57#ibcon#*after write, iclass 10, count 0 2006.174.00:28:54.57#ibcon#*before return 0, iclass 10, count 0 2006.174.00:28:54.57#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.174.00:28:54.57#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.174.00:28:54.57#ibcon#about to clear, iclass 10 cls_cnt 0 2006.174.00:28:54.57#ibcon#cleared, iclass 10 cls_cnt 0 2006.174.00:28:54.57$vck44/vblo=6,719.99 2006.174.00:28:54.57#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.174.00:28:54.57#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.174.00:28:54.57#ibcon#ireg 17 cls_cnt 0 2006.174.00:28:54.57#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.174.00:28:54.57#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.174.00:28:54.57#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.174.00:28:54.57#ibcon#enter wrdev, iclass 13, count 0 2006.174.00:28:54.57#ibcon#first serial, iclass 13, count 0 2006.174.00:28:54.57#ibcon#enter sib2, iclass 13, count 0 2006.174.00:28:54.57#ibcon#flushed, iclass 13, count 0 2006.174.00:28:54.57#ibcon#about to write, iclass 13, count 0 2006.174.00:28:54.57#ibcon#wrote, iclass 13, count 0 2006.174.00:28:54.57#ibcon#about to read 3, iclass 13, count 0 2006.174.00:28:54.59#ibcon#read 3, iclass 13, count 0 2006.174.00:28:54.59#ibcon#about to read 4, iclass 13, count 0 2006.174.00:28:54.59#ibcon#read 4, iclass 13, count 0 2006.174.00:28:54.59#ibcon#about to read 5, iclass 13, count 0 2006.174.00:28:54.59#ibcon#read 5, iclass 13, count 0 2006.174.00:28:54.59#ibcon#about to read 6, iclass 13, count 0 2006.174.00:28:54.59#ibcon#read 6, iclass 13, count 0 2006.174.00:28:54.59#ibcon#end of sib2, iclass 13, count 0 2006.174.00:28:54.59#ibcon#*mode == 0, iclass 13, count 0 2006.174.00:28:54.59#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.174.00:28:54.59#ibcon#[28=FRQ=06,719.99\r\n] 2006.174.00:28:54.59#ibcon#*before write, iclass 13, count 0 2006.174.00:28:54.59#ibcon#enter sib2, iclass 13, count 0 2006.174.00:28:54.59#ibcon#flushed, iclass 13, count 0 2006.174.00:28:54.59#ibcon#about to write, iclass 13, count 0 2006.174.00:28:54.59#ibcon#wrote, iclass 13, count 0 2006.174.00:28:54.59#ibcon#about to read 3, iclass 13, count 0 2006.174.00:28:54.63#ibcon#read 3, iclass 13, count 0 2006.174.00:28:54.63#ibcon#about to read 4, iclass 13, count 0 2006.174.00:28:54.63#ibcon#read 4, iclass 13, count 0 2006.174.00:28:54.63#ibcon#about to read 5, iclass 13, count 0 2006.174.00:28:54.63#ibcon#read 5, iclass 13, count 0 2006.174.00:28:54.63#ibcon#about to read 6, iclass 13, count 0 2006.174.00:28:54.63#ibcon#read 6, iclass 13, count 0 2006.174.00:28:54.63#ibcon#end of sib2, iclass 13, count 0 2006.174.00:28:54.63#ibcon#*after write, iclass 13, count 0 2006.174.00:28:54.63#ibcon#*before return 0, iclass 13, count 0 2006.174.00:28:54.63#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.174.00:28:54.63#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.174.00:28:54.63#ibcon#about to clear, iclass 13 cls_cnt 0 2006.174.00:28:54.63#ibcon#cleared, iclass 13 cls_cnt 0 2006.174.00:28:54.63$vck44/vb=6,4 2006.174.00:28:54.63#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.174.00:28:54.63#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.174.00:28:54.63#ibcon#ireg 11 cls_cnt 2 2006.174.00:28:54.63#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.174.00:28:54.69#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.174.00:28:54.69#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.174.00:28:54.69#ibcon#enter wrdev, iclass 15, count 2 2006.174.00:28:54.69#ibcon#first serial, iclass 15, count 2 2006.174.00:28:54.69#ibcon#enter sib2, iclass 15, count 2 2006.174.00:28:54.69#ibcon#flushed, iclass 15, count 2 2006.174.00:28:54.69#ibcon#about to write, iclass 15, count 2 2006.174.00:28:54.69#ibcon#wrote, iclass 15, count 2 2006.174.00:28:54.69#ibcon#about to read 3, iclass 15, count 2 2006.174.00:28:54.71#ibcon#read 3, iclass 15, count 2 2006.174.00:28:54.71#ibcon#about to read 4, iclass 15, count 2 2006.174.00:28:54.71#ibcon#read 4, iclass 15, count 2 2006.174.00:28:54.71#ibcon#about to read 5, iclass 15, count 2 2006.174.00:28:54.71#ibcon#read 5, iclass 15, count 2 2006.174.00:28:54.71#ibcon#about to read 6, iclass 15, count 2 2006.174.00:28:54.71#ibcon#read 6, iclass 15, count 2 2006.174.00:28:54.71#ibcon#end of sib2, iclass 15, count 2 2006.174.00:28:54.71#ibcon#*mode == 0, iclass 15, count 2 2006.174.00:28:54.71#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.174.00:28:54.71#ibcon#[27=AT06-04\r\n] 2006.174.00:28:54.71#ibcon#*before write, iclass 15, count 2 2006.174.00:28:54.71#ibcon#enter sib2, iclass 15, count 2 2006.174.00:28:54.71#ibcon#flushed, iclass 15, count 2 2006.174.00:28:54.71#ibcon#about to write, iclass 15, count 2 2006.174.00:28:54.71#ibcon#wrote, iclass 15, count 2 2006.174.00:28:54.71#ibcon#about to read 3, iclass 15, count 2 2006.174.00:28:54.74#ibcon#read 3, iclass 15, count 2 2006.174.00:28:54.74#ibcon#about to read 4, iclass 15, count 2 2006.174.00:28:54.74#ibcon#read 4, iclass 15, count 2 2006.174.00:28:54.74#ibcon#about to read 5, iclass 15, count 2 2006.174.00:28:54.74#ibcon#read 5, iclass 15, count 2 2006.174.00:28:54.74#ibcon#about to read 6, iclass 15, count 2 2006.174.00:28:54.74#ibcon#read 6, iclass 15, count 2 2006.174.00:28:54.74#ibcon#end of sib2, iclass 15, count 2 2006.174.00:28:54.74#ibcon#*after write, iclass 15, count 2 2006.174.00:28:54.74#ibcon#*before return 0, iclass 15, count 2 2006.174.00:28:54.74#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.174.00:28:54.74#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.174.00:28:54.74#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.174.00:28:54.74#ibcon#ireg 7 cls_cnt 0 2006.174.00:28:54.74#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.174.00:28:54.86#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.174.00:28:54.86#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.174.00:28:54.86#ibcon#enter wrdev, iclass 15, count 0 2006.174.00:28:54.86#ibcon#first serial, iclass 15, count 0 2006.174.00:28:54.86#ibcon#enter sib2, iclass 15, count 0 2006.174.00:28:54.86#ibcon#flushed, iclass 15, count 0 2006.174.00:28:54.86#ibcon#about to write, iclass 15, count 0 2006.174.00:28:54.86#ibcon#wrote, iclass 15, count 0 2006.174.00:28:54.86#ibcon#about to read 3, iclass 15, count 0 2006.174.00:28:54.88#ibcon#read 3, iclass 15, count 0 2006.174.00:28:54.88#ibcon#about to read 4, iclass 15, count 0 2006.174.00:28:54.88#ibcon#read 4, iclass 15, count 0 2006.174.00:28:54.88#ibcon#about to read 5, iclass 15, count 0 2006.174.00:28:54.88#ibcon#read 5, iclass 15, count 0 2006.174.00:28:54.88#ibcon#about to read 6, iclass 15, count 0 2006.174.00:28:54.88#ibcon#read 6, iclass 15, count 0 2006.174.00:28:54.88#ibcon#end of sib2, iclass 15, count 0 2006.174.00:28:54.88#ibcon#*mode == 0, iclass 15, count 0 2006.174.00:28:54.88#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.174.00:28:54.88#ibcon#[27=USB\r\n] 2006.174.00:28:54.88#ibcon#*before write, iclass 15, count 0 2006.174.00:28:54.88#ibcon#enter sib2, iclass 15, count 0 2006.174.00:28:54.88#ibcon#flushed, iclass 15, count 0 2006.174.00:28:54.88#ibcon#about to write, iclass 15, count 0 2006.174.00:28:54.88#ibcon#wrote, iclass 15, count 0 2006.174.00:28:54.88#ibcon#about to read 3, iclass 15, count 0 2006.174.00:28:54.91#ibcon#read 3, iclass 15, count 0 2006.174.00:28:54.91#ibcon#about to read 4, iclass 15, count 0 2006.174.00:28:54.91#ibcon#read 4, iclass 15, count 0 2006.174.00:28:54.91#ibcon#about to read 5, iclass 15, count 0 2006.174.00:28:54.91#ibcon#read 5, iclass 15, count 0 2006.174.00:28:54.91#ibcon#about to read 6, iclass 15, count 0 2006.174.00:28:54.91#ibcon#read 6, iclass 15, count 0 2006.174.00:28:54.91#ibcon#end of sib2, iclass 15, count 0 2006.174.00:28:54.91#ibcon#*after write, iclass 15, count 0 2006.174.00:28:54.91#ibcon#*before return 0, iclass 15, count 0 2006.174.00:28:54.91#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.174.00:28:54.91#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.174.00:28:54.91#ibcon#about to clear, iclass 15 cls_cnt 0 2006.174.00:28:54.91#ibcon#cleared, iclass 15 cls_cnt 0 2006.174.00:28:54.91$vck44/vblo=7,734.99 2006.174.00:28:54.91#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.174.00:28:54.91#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.174.00:28:54.91#ibcon#ireg 17 cls_cnt 0 2006.174.00:28:54.91#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.174.00:28:54.91#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.174.00:28:54.91#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.174.00:28:54.91#ibcon#enter wrdev, iclass 17, count 0 2006.174.00:28:54.91#ibcon#first serial, iclass 17, count 0 2006.174.00:28:54.91#ibcon#enter sib2, iclass 17, count 0 2006.174.00:28:54.91#ibcon#flushed, iclass 17, count 0 2006.174.00:28:54.91#ibcon#about to write, iclass 17, count 0 2006.174.00:28:54.91#ibcon#wrote, iclass 17, count 0 2006.174.00:28:54.91#ibcon#about to read 3, iclass 17, count 0 2006.174.00:28:54.93#ibcon#read 3, iclass 17, count 0 2006.174.00:28:54.93#ibcon#about to read 4, iclass 17, count 0 2006.174.00:28:54.93#ibcon#read 4, iclass 17, count 0 2006.174.00:28:54.93#ibcon#about to read 5, iclass 17, count 0 2006.174.00:28:54.93#ibcon#read 5, iclass 17, count 0 2006.174.00:28:54.93#ibcon#about to read 6, iclass 17, count 0 2006.174.00:28:54.93#ibcon#read 6, iclass 17, count 0 2006.174.00:28:54.93#ibcon#end of sib2, iclass 17, count 0 2006.174.00:28:54.93#ibcon#*mode == 0, iclass 17, count 0 2006.174.00:28:54.93#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.174.00:28:54.93#ibcon#[28=FRQ=07,734.99\r\n] 2006.174.00:28:54.93#ibcon#*before write, iclass 17, count 0 2006.174.00:28:54.93#ibcon#enter sib2, iclass 17, count 0 2006.174.00:28:54.93#ibcon#flushed, iclass 17, count 0 2006.174.00:28:54.93#ibcon#about to write, iclass 17, count 0 2006.174.00:28:54.93#ibcon#wrote, iclass 17, count 0 2006.174.00:28:54.93#ibcon#about to read 3, iclass 17, count 0 2006.174.00:28:54.97#ibcon#read 3, iclass 17, count 0 2006.174.00:28:54.97#ibcon#about to read 4, iclass 17, count 0 2006.174.00:28:54.97#ibcon#read 4, iclass 17, count 0 2006.174.00:28:54.97#ibcon#about to read 5, iclass 17, count 0 2006.174.00:28:54.97#ibcon#read 5, iclass 17, count 0 2006.174.00:28:54.97#ibcon#about to read 6, iclass 17, count 0 2006.174.00:28:54.97#ibcon#read 6, iclass 17, count 0 2006.174.00:28:54.97#ibcon#end of sib2, iclass 17, count 0 2006.174.00:28:54.97#ibcon#*after write, iclass 17, count 0 2006.174.00:28:54.97#ibcon#*before return 0, iclass 17, count 0 2006.174.00:28:54.97#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.174.00:28:54.97#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.174.00:28:54.97#ibcon#about to clear, iclass 17 cls_cnt 0 2006.174.00:28:54.97#ibcon#cleared, iclass 17 cls_cnt 0 2006.174.00:28:54.97$vck44/vb=7,4 2006.174.00:28:54.97#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.174.00:28:54.97#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.174.00:28:54.97#ibcon#ireg 11 cls_cnt 2 2006.174.00:28:54.97#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.174.00:28:55.03#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.174.00:28:55.03#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.174.00:28:55.03#ibcon#enter wrdev, iclass 19, count 2 2006.174.00:28:55.03#ibcon#first serial, iclass 19, count 2 2006.174.00:28:55.03#ibcon#enter sib2, iclass 19, count 2 2006.174.00:28:55.03#ibcon#flushed, iclass 19, count 2 2006.174.00:28:55.03#ibcon#about to write, iclass 19, count 2 2006.174.00:28:55.03#ibcon#wrote, iclass 19, count 2 2006.174.00:28:55.03#ibcon#about to read 3, iclass 19, count 2 2006.174.00:28:55.05#ibcon#read 3, iclass 19, count 2 2006.174.00:28:55.05#ibcon#about to read 4, iclass 19, count 2 2006.174.00:28:55.05#ibcon#read 4, iclass 19, count 2 2006.174.00:28:55.05#ibcon#about to read 5, iclass 19, count 2 2006.174.00:28:55.05#ibcon#read 5, iclass 19, count 2 2006.174.00:28:55.05#ibcon#about to read 6, iclass 19, count 2 2006.174.00:28:55.05#ibcon#read 6, iclass 19, count 2 2006.174.00:28:55.05#ibcon#end of sib2, iclass 19, count 2 2006.174.00:28:55.05#ibcon#*mode == 0, iclass 19, count 2 2006.174.00:28:55.05#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.174.00:28:55.05#ibcon#[27=AT07-04\r\n] 2006.174.00:28:55.05#ibcon#*before write, iclass 19, count 2 2006.174.00:28:55.05#ibcon#enter sib2, iclass 19, count 2 2006.174.00:28:55.05#ibcon#flushed, iclass 19, count 2 2006.174.00:28:55.05#ibcon#about to write, iclass 19, count 2 2006.174.00:28:55.05#ibcon#wrote, iclass 19, count 2 2006.174.00:28:55.05#ibcon#about to read 3, iclass 19, count 2 2006.174.00:28:55.08#ibcon#read 3, iclass 19, count 2 2006.174.00:28:55.08#ibcon#about to read 4, iclass 19, count 2 2006.174.00:28:55.08#ibcon#read 4, iclass 19, count 2 2006.174.00:28:55.08#ibcon#about to read 5, iclass 19, count 2 2006.174.00:28:55.08#ibcon#read 5, iclass 19, count 2 2006.174.00:28:55.08#ibcon#about to read 6, iclass 19, count 2 2006.174.00:28:55.08#ibcon#read 6, iclass 19, count 2 2006.174.00:28:55.08#ibcon#end of sib2, iclass 19, count 2 2006.174.00:28:55.08#ibcon#*after write, iclass 19, count 2 2006.174.00:28:55.08#ibcon#*before return 0, iclass 19, count 2 2006.174.00:28:55.08#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.174.00:28:55.08#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.174.00:28:55.08#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.174.00:28:55.08#ibcon#ireg 7 cls_cnt 0 2006.174.00:28:55.08#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.174.00:28:55.20#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.174.00:28:55.20#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.174.00:28:55.20#ibcon#enter wrdev, iclass 19, count 0 2006.174.00:28:55.20#ibcon#first serial, iclass 19, count 0 2006.174.00:28:55.20#ibcon#enter sib2, iclass 19, count 0 2006.174.00:28:55.20#ibcon#flushed, iclass 19, count 0 2006.174.00:28:55.20#ibcon#about to write, iclass 19, count 0 2006.174.00:28:55.20#ibcon#wrote, iclass 19, count 0 2006.174.00:28:55.20#ibcon#about to read 3, iclass 19, count 0 2006.174.00:28:55.22#ibcon#read 3, iclass 19, count 0 2006.174.00:28:55.22#ibcon#about to read 4, iclass 19, count 0 2006.174.00:28:55.22#ibcon#read 4, iclass 19, count 0 2006.174.00:28:55.22#ibcon#about to read 5, iclass 19, count 0 2006.174.00:28:55.22#ibcon#read 5, iclass 19, count 0 2006.174.00:28:55.22#ibcon#about to read 6, iclass 19, count 0 2006.174.00:28:55.22#ibcon#read 6, iclass 19, count 0 2006.174.00:28:55.22#ibcon#end of sib2, iclass 19, count 0 2006.174.00:28:55.22#ibcon#*mode == 0, iclass 19, count 0 2006.174.00:28:55.22#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.174.00:28:55.22#ibcon#[27=USB\r\n] 2006.174.00:28:55.22#ibcon#*before write, iclass 19, count 0 2006.174.00:28:55.22#ibcon#enter sib2, iclass 19, count 0 2006.174.00:28:55.22#ibcon#flushed, iclass 19, count 0 2006.174.00:28:55.22#ibcon#about to write, iclass 19, count 0 2006.174.00:28:55.22#ibcon#wrote, iclass 19, count 0 2006.174.00:28:55.22#ibcon#about to read 3, iclass 19, count 0 2006.174.00:28:55.25#ibcon#read 3, iclass 19, count 0 2006.174.00:28:55.25#ibcon#about to read 4, iclass 19, count 0 2006.174.00:28:55.25#ibcon#read 4, iclass 19, count 0 2006.174.00:28:55.25#ibcon#about to read 5, iclass 19, count 0 2006.174.00:28:55.25#ibcon#read 5, iclass 19, count 0 2006.174.00:28:55.25#ibcon#about to read 6, iclass 19, count 0 2006.174.00:28:55.25#ibcon#read 6, iclass 19, count 0 2006.174.00:28:55.25#ibcon#end of sib2, iclass 19, count 0 2006.174.00:28:55.25#ibcon#*after write, iclass 19, count 0 2006.174.00:28:55.25#ibcon#*before return 0, iclass 19, count 0 2006.174.00:28:55.25#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.174.00:28:55.25#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.174.00:28:55.25#ibcon#about to clear, iclass 19 cls_cnt 0 2006.174.00:28:55.25#ibcon#cleared, iclass 19 cls_cnt 0 2006.174.00:28:55.25$vck44/vblo=8,744.99 2006.174.00:28:55.25#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.174.00:28:55.25#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.174.00:28:55.25#ibcon#ireg 17 cls_cnt 0 2006.174.00:28:55.25#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.174.00:28:55.25#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.174.00:28:55.25#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.174.00:28:55.25#ibcon#enter wrdev, iclass 21, count 0 2006.174.00:28:55.25#ibcon#first serial, iclass 21, count 0 2006.174.00:28:55.25#ibcon#enter sib2, iclass 21, count 0 2006.174.00:28:55.25#ibcon#flushed, iclass 21, count 0 2006.174.00:28:55.25#ibcon#about to write, iclass 21, count 0 2006.174.00:28:55.25#ibcon#wrote, iclass 21, count 0 2006.174.00:28:55.25#ibcon#about to read 3, iclass 21, count 0 2006.174.00:28:55.27#ibcon#read 3, iclass 21, count 0 2006.174.00:28:55.27#ibcon#about to read 4, iclass 21, count 0 2006.174.00:28:55.27#ibcon#read 4, iclass 21, count 0 2006.174.00:28:55.27#ibcon#about to read 5, iclass 21, count 0 2006.174.00:28:55.27#ibcon#read 5, iclass 21, count 0 2006.174.00:28:55.27#ibcon#about to read 6, iclass 21, count 0 2006.174.00:28:55.27#ibcon#read 6, iclass 21, count 0 2006.174.00:28:55.27#ibcon#end of sib2, iclass 21, count 0 2006.174.00:28:55.27#ibcon#*mode == 0, iclass 21, count 0 2006.174.00:28:55.27#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.174.00:28:55.27#ibcon#[28=FRQ=08,744.99\r\n] 2006.174.00:28:55.27#ibcon#*before write, iclass 21, count 0 2006.174.00:28:55.27#ibcon#enter sib2, iclass 21, count 0 2006.174.00:28:55.27#ibcon#flushed, iclass 21, count 0 2006.174.00:28:55.27#ibcon#about to write, iclass 21, count 0 2006.174.00:28:55.27#ibcon#wrote, iclass 21, count 0 2006.174.00:28:55.27#ibcon#about to read 3, iclass 21, count 0 2006.174.00:28:55.31#ibcon#read 3, iclass 21, count 0 2006.174.00:28:55.31#ibcon#about to read 4, iclass 21, count 0 2006.174.00:28:55.31#ibcon#read 4, iclass 21, count 0 2006.174.00:28:55.31#ibcon#about to read 5, iclass 21, count 0 2006.174.00:28:55.31#ibcon#read 5, iclass 21, count 0 2006.174.00:28:55.31#ibcon#about to read 6, iclass 21, count 0 2006.174.00:28:55.31#ibcon#read 6, iclass 21, count 0 2006.174.00:28:55.31#ibcon#end of sib2, iclass 21, count 0 2006.174.00:28:55.31#ibcon#*after write, iclass 21, count 0 2006.174.00:28:55.31#ibcon#*before return 0, iclass 21, count 0 2006.174.00:28:55.31#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.174.00:28:55.31#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.174.00:28:55.31#ibcon#about to clear, iclass 21 cls_cnt 0 2006.174.00:28:55.31#ibcon#cleared, iclass 21 cls_cnt 0 2006.174.00:28:55.31$vck44/vb=8,4 2006.174.00:28:55.31#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.174.00:28:55.31#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.174.00:28:55.31#ibcon#ireg 11 cls_cnt 2 2006.174.00:28:55.31#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.174.00:28:55.37#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.174.00:28:55.37#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.174.00:28:55.37#ibcon#enter wrdev, iclass 23, count 2 2006.174.00:28:55.37#ibcon#first serial, iclass 23, count 2 2006.174.00:28:55.37#ibcon#enter sib2, iclass 23, count 2 2006.174.00:28:55.37#ibcon#flushed, iclass 23, count 2 2006.174.00:28:55.37#ibcon#about to write, iclass 23, count 2 2006.174.00:28:55.37#ibcon#wrote, iclass 23, count 2 2006.174.00:28:55.37#ibcon#about to read 3, iclass 23, count 2 2006.174.00:28:55.39#ibcon#read 3, iclass 23, count 2 2006.174.00:28:55.39#ibcon#about to read 4, iclass 23, count 2 2006.174.00:28:55.39#ibcon#read 4, iclass 23, count 2 2006.174.00:28:55.39#ibcon#about to read 5, iclass 23, count 2 2006.174.00:28:55.39#ibcon#read 5, iclass 23, count 2 2006.174.00:28:55.39#ibcon#about to read 6, iclass 23, count 2 2006.174.00:28:55.39#ibcon#read 6, iclass 23, count 2 2006.174.00:28:55.39#ibcon#end of sib2, iclass 23, count 2 2006.174.00:28:55.39#ibcon#*mode == 0, iclass 23, count 2 2006.174.00:28:55.39#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.174.00:28:55.39#ibcon#[27=AT08-04\r\n] 2006.174.00:28:55.39#ibcon#*before write, iclass 23, count 2 2006.174.00:28:55.39#ibcon#enter sib2, iclass 23, count 2 2006.174.00:28:55.39#ibcon#flushed, iclass 23, count 2 2006.174.00:28:55.39#ibcon#about to write, iclass 23, count 2 2006.174.00:28:55.39#ibcon#wrote, iclass 23, count 2 2006.174.00:28:55.39#ibcon#about to read 3, iclass 23, count 2 2006.174.00:28:55.42#ibcon#read 3, iclass 23, count 2 2006.174.00:28:55.42#ibcon#about to read 4, iclass 23, count 2 2006.174.00:28:55.42#ibcon#read 4, iclass 23, count 2 2006.174.00:28:55.42#ibcon#about to read 5, iclass 23, count 2 2006.174.00:28:55.42#ibcon#read 5, iclass 23, count 2 2006.174.00:28:55.42#ibcon#about to read 6, iclass 23, count 2 2006.174.00:28:55.42#ibcon#read 6, iclass 23, count 2 2006.174.00:28:55.42#ibcon#end of sib2, iclass 23, count 2 2006.174.00:28:55.42#ibcon#*after write, iclass 23, count 2 2006.174.00:28:55.42#ibcon#*before return 0, iclass 23, count 2 2006.174.00:28:55.42#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.174.00:28:55.42#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.174.00:28:55.42#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.174.00:28:55.42#ibcon#ireg 7 cls_cnt 0 2006.174.00:28:55.42#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.174.00:28:55.54#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.174.00:28:55.54#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.174.00:28:55.54#ibcon#enter wrdev, iclass 23, count 0 2006.174.00:28:55.54#ibcon#first serial, iclass 23, count 0 2006.174.00:28:55.54#ibcon#enter sib2, iclass 23, count 0 2006.174.00:28:55.54#ibcon#flushed, iclass 23, count 0 2006.174.00:28:55.54#ibcon#about to write, iclass 23, count 0 2006.174.00:28:55.54#ibcon#wrote, iclass 23, count 0 2006.174.00:28:55.54#ibcon#about to read 3, iclass 23, count 0 2006.174.00:28:55.56#ibcon#read 3, iclass 23, count 0 2006.174.00:28:55.56#ibcon#about to read 4, iclass 23, count 0 2006.174.00:28:55.56#ibcon#read 4, iclass 23, count 0 2006.174.00:28:55.56#ibcon#about to read 5, iclass 23, count 0 2006.174.00:28:55.56#ibcon#read 5, iclass 23, count 0 2006.174.00:28:55.56#ibcon#about to read 6, iclass 23, count 0 2006.174.00:28:55.56#ibcon#read 6, iclass 23, count 0 2006.174.00:28:55.56#ibcon#end of sib2, iclass 23, count 0 2006.174.00:28:55.56#ibcon#*mode == 0, iclass 23, count 0 2006.174.00:28:55.56#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.174.00:28:55.56#ibcon#[27=USB\r\n] 2006.174.00:28:55.56#ibcon#*before write, iclass 23, count 0 2006.174.00:28:55.56#ibcon#enter sib2, iclass 23, count 0 2006.174.00:28:55.56#ibcon#flushed, iclass 23, count 0 2006.174.00:28:55.56#ibcon#about to write, iclass 23, count 0 2006.174.00:28:55.56#ibcon#wrote, iclass 23, count 0 2006.174.00:28:55.56#ibcon#about to read 3, iclass 23, count 0 2006.174.00:28:55.59#ibcon#read 3, iclass 23, count 0 2006.174.00:28:55.59#ibcon#about to read 4, iclass 23, count 0 2006.174.00:28:55.59#ibcon#read 4, iclass 23, count 0 2006.174.00:28:55.59#ibcon#about to read 5, iclass 23, count 0 2006.174.00:28:55.59#ibcon#read 5, iclass 23, count 0 2006.174.00:28:55.59#ibcon#about to read 6, iclass 23, count 0 2006.174.00:28:55.59#ibcon#read 6, iclass 23, count 0 2006.174.00:28:55.59#ibcon#end of sib2, iclass 23, count 0 2006.174.00:28:55.59#ibcon#*after write, iclass 23, count 0 2006.174.00:28:55.59#ibcon#*before return 0, iclass 23, count 0 2006.174.00:28:55.59#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.174.00:28:55.59#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.174.00:28:55.59#ibcon#about to clear, iclass 23 cls_cnt 0 2006.174.00:28:55.59#ibcon#cleared, iclass 23 cls_cnt 0 2006.174.00:28:55.59$vck44/vabw=wide 2006.174.00:28:55.59#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.174.00:28:55.59#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.174.00:28:55.59#ibcon#ireg 8 cls_cnt 0 2006.174.00:28:55.59#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.174.00:28:55.59#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.174.00:28:55.59#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.174.00:28:55.59#ibcon#enter wrdev, iclass 25, count 0 2006.174.00:28:55.59#ibcon#first serial, iclass 25, count 0 2006.174.00:28:55.59#ibcon#enter sib2, iclass 25, count 0 2006.174.00:28:55.59#ibcon#flushed, iclass 25, count 0 2006.174.00:28:55.59#ibcon#about to write, iclass 25, count 0 2006.174.00:28:55.59#ibcon#wrote, iclass 25, count 0 2006.174.00:28:55.59#ibcon#about to read 3, iclass 25, count 0 2006.174.00:28:55.61#ibcon#read 3, iclass 25, count 0 2006.174.00:28:55.61#ibcon#about to read 4, iclass 25, count 0 2006.174.00:28:55.61#ibcon#read 4, iclass 25, count 0 2006.174.00:28:55.61#ibcon#about to read 5, iclass 25, count 0 2006.174.00:28:55.61#ibcon#read 5, iclass 25, count 0 2006.174.00:28:55.61#ibcon#about to read 6, iclass 25, count 0 2006.174.00:28:55.61#ibcon#read 6, iclass 25, count 0 2006.174.00:28:55.61#ibcon#end of sib2, iclass 25, count 0 2006.174.00:28:55.61#ibcon#*mode == 0, iclass 25, count 0 2006.174.00:28:55.61#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.174.00:28:55.61#ibcon#[25=BW32\r\n] 2006.174.00:28:55.61#ibcon#*before write, iclass 25, count 0 2006.174.00:28:55.61#ibcon#enter sib2, iclass 25, count 0 2006.174.00:28:55.61#ibcon#flushed, iclass 25, count 0 2006.174.00:28:55.61#ibcon#about to write, iclass 25, count 0 2006.174.00:28:55.61#ibcon#wrote, iclass 25, count 0 2006.174.00:28:55.61#ibcon#about to read 3, iclass 25, count 0 2006.174.00:28:55.64#ibcon#read 3, iclass 25, count 0 2006.174.00:28:55.64#ibcon#about to read 4, iclass 25, count 0 2006.174.00:28:55.64#ibcon#read 4, iclass 25, count 0 2006.174.00:28:55.64#ibcon#about to read 5, iclass 25, count 0 2006.174.00:28:55.64#ibcon#read 5, iclass 25, count 0 2006.174.00:28:55.64#ibcon#about to read 6, iclass 25, count 0 2006.174.00:28:55.64#ibcon#read 6, iclass 25, count 0 2006.174.00:28:55.64#ibcon#end of sib2, iclass 25, count 0 2006.174.00:28:55.64#ibcon#*after write, iclass 25, count 0 2006.174.00:28:55.64#ibcon#*before return 0, iclass 25, count 0 2006.174.00:28:55.64#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.174.00:28:55.64#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.174.00:28:55.64#ibcon#about to clear, iclass 25 cls_cnt 0 2006.174.00:28:55.64#ibcon#cleared, iclass 25 cls_cnt 0 2006.174.00:28:55.64$vck44/vbbw=wide 2006.174.00:28:55.64#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.174.00:28:55.64#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.174.00:28:55.64#ibcon#ireg 8 cls_cnt 0 2006.174.00:28:55.64#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.174.00:28:55.71#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.174.00:28:55.71#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.174.00:28:55.71#ibcon#enter wrdev, iclass 27, count 0 2006.174.00:28:55.71#ibcon#first serial, iclass 27, count 0 2006.174.00:28:55.71#ibcon#enter sib2, iclass 27, count 0 2006.174.00:28:55.71#ibcon#flushed, iclass 27, count 0 2006.174.00:28:55.71#ibcon#about to write, iclass 27, count 0 2006.174.00:28:55.71#ibcon#wrote, iclass 27, count 0 2006.174.00:28:55.71#ibcon#about to read 3, iclass 27, count 0 2006.174.00:28:55.73#ibcon#read 3, iclass 27, count 0 2006.174.00:28:55.73#ibcon#about to read 4, iclass 27, count 0 2006.174.00:28:55.73#ibcon#read 4, iclass 27, count 0 2006.174.00:28:55.73#ibcon#about to read 5, iclass 27, count 0 2006.174.00:28:55.73#ibcon#read 5, iclass 27, count 0 2006.174.00:28:55.73#ibcon#about to read 6, iclass 27, count 0 2006.174.00:28:55.73#ibcon#read 6, iclass 27, count 0 2006.174.00:28:55.73#ibcon#end of sib2, iclass 27, count 0 2006.174.00:28:55.73#ibcon#*mode == 0, iclass 27, count 0 2006.174.00:28:55.73#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.174.00:28:55.73#ibcon#[27=BW32\r\n] 2006.174.00:28:55.73#ibcon#*before write, iclass 27, count 0 2006.174.00:28:55.73#ibcon#enter sib2, iclass 27, count 0 2006.174.00:28:55.73#ibcon#flushed, iclass 27, count 0 2006.174.00:28:55.73#ibcon#about to write, iclass 27, count 0 2006.174.00:28:55.73#ibcon#wrote, iclass 27, count 0 2006.174.00:28:55.73#ibcon#about to read 3, iclass 27, count 0 2006.174.00:28:55.76#ibcon#read 3, iclass 27, count 0 2006.174.00:28:55.76#ibcon#about to read 4, iclass 27, count 0 2006.174.00:28:55.76#ibcon#read 4, iclass 27, count 0 2006.174.00:28:55.76#ibcon#about to read 5, iclass 27, count 0 2006.174.00:28:55.76#ibcon#read 5, iclass 27, count 0 2006.174.00:28:55.76#ibcon#about to read 6, iclass 27, count 0 2006.174.00:28:55.76#ibcon#read 6, iclass 27, count 0 2006.174.00:28:55.76#ibcon#end of sib2, iclass 27, count 0 2006.174.00:28:55.76#ibcon#*after write, iclass 27, count 0 2006.174.00:28:55.76#ibcon#*before return 0, iclass 27, count 0 2006.174.00:28:55.76#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.174.00:28:55.76#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.174.00:28:55.76#ibcon#about to clear, iclass 27 cls_cnt 0 2006.174.00:28:55.76#ibcon#cleared, iclass 27 cls_cnt 0 2006.174.00:28:55.76$setupk4/ifdk4 2006.174.00:28:55.76$ifdk4/lo= 2006.174.00:28:55.76$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.174.00:28:55.76$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.174.00:28:55.76$ifdk4/patch= 2006.174.00:28:55.76$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.174.00:28:55.76$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.174.00:28:55.76$setupk4/!*+20s 2006.174.00:29:04.14#trakl#Source acquired 2006.174.00:29:04.40#abcon#<5=/10 1.0 2.6 24.47 861003.3\r\n> 2006.174.00:29:04.42#abcon#{5=INTERFACE CLEAR} 2006.174.00:29:04.48#abcon#[5=S1D000X0/0*\r\n] 2006.174.00:29:06.14#flagr#flagr/antenna,acquired 2006.174.00:29:10.27$setupk4/"tpicd 2006.174.00:29:10.27$setupk4/echo=off 2006.174.00:29:10.27$setupk4/xlog=off 2006.174.00:29:10.27:!2006.174.00:36:55 2006.174.00:36:55.00:preob 2006.174.00:36:55.14/onsource/TRACKING 2006.174.00:36:55.14:!2006.174.00:37:05 2006.174.00:37:05.00:"tape 2006.174.00:37:05.00:"st=record 2006.174.00:37:05.00:data_valid=on 2006.174.00:37:05.00:midob 2006.174.00:37:06.14/onsource/TRACKING 2006.174.00:37:06.14/wx/24.63,1003.3,85 2006.174.00:37:06.20/cable/+6.5054E-03 2006.174.00:37:07.29/va/01,07,usb,yes,34,37 2006.174.00:37:07.29/va/02,06,usb,yes,34,35 2006.174.00:37:07.29/va/03,05,usb,yes,44,45 2006.174.00:37:07.29/va/04,06,usb,yes,35,37 2006.174.00:37:07.29/va/05,04,usb,yes,27,28 2006.174.00:37:07.29/va/06,03,usb,yes,38,38 2006.174.00:37:07.29/va/07,04,usb,yes,31,32 2006.174.00:37:07.29/va/08,04,usb,yes,26,32 2006.174.00:37:07.52/valo/01,524.99,yes,locked 2006.174.00:37:07.52/valo/02,534.99,yes,locked 2006.174.00:37:07.52/valo/03,564.99,yes,locked 2006.174.00:37:07.52/valo/04,624.99,yes,locked 2006.174.00:37:07.52/valo/05,734.99,yes,locked 2006.174.00:37:07.52/valo/06,814.99,yes,locked 2006.174.00:37:07.52/valo/07,864.99,yes,locked 2006.174.00:37:07.52/valo/08,884.99,yes,locked 2006.174.00:37:08.61/vb/01,04,usb,yes,29,27 2006.174.00:37:08.61/vb/02,04,usb,yes,31,31 2006.174.00:37:08.61/vb/03,04,usb,yes,28,31 2006.174.00:37:08.61/vb/04,04,usb,yes,32,31 2006.174.00:37:08.61/vb/05,04,usb,yes,25,28 2006.174.00:37:08.61/vb/06,04,usb,yes,29,26 2006.174.00:37:08.61/vb/07,04,usb,yes,29,29 2006.174.00:37:08.61/vb/08,04,usb,yes,27,30 2006.174.00:37:08.84/vblo/01,629.99,yes,locked 2006.174.00:37:08.84/vblo/02,634.99,yes,locked 2006.174.00:37:08.84/vblo/03,649.99,yes,locked 2006.174.00:37:08.84/vblo/04,679.99,yes,locked 2006.174.00:37:08.84/vblo/05,709.99,yes,locked 2006.174.00:37:08.84/vblo/06,719.99,yes,locked 2006.174.00:37:08.84/vblo/07,734.99,yes,locked 2006.174.00:37:08.84/vblo/08,744.99,yes,locked 2006.174.00:37:08.99/vabw/8 2006.174.00:37:09.14/vbbw/8 2006.174.00:37:09.23/xfe/off,on,14.7 2006.174.00:37:09.62/ifatt/23,28,28,28 2006.174.00:37:10.07/fmout-gps/S +3.89E-07 2006.174.00:37:10.11:!2006.174.00:40:45 2006.174.00:40:45.01:data_valid=off 2006.174.00:40:45.01:"et 2006.174.00:40:45.02:!+3s 2006.174.00:40:48.03:"tape 2006.174.00:40:48.03:postob 2006.174.00:40:48.12/cable/+6.5031E-03 2006.174.00:40:48.12/wx/24.67,1003.3,83 2006.174.00:40:48.18/fmout-gps/S +3.89E-07 2006.174.00:40:48.18:scan_name=174-0044,jd0606,570 2006.174.00:40:48.19:source=0133+476,013658.59,475129.1,2000.0,ccw 2006.174.00:40:50.13#flagr#flagr/antenna,new-source 2006.174.00:40:50.13:checkk5 2006.174.00:40:50.54/chk_autoobs//k5ts1/ autoobs is running! 2006.174.00:40:50.93/chk_autoobs//k5ts2/ autoobs is running! 2006.174.00:40:51.33/chk_autoobs//k5ts3/ autoobs is running! 2006.174.00:40:51.72/chk_autoobs//k5ts4/ autoobs is running! 2006.174.00:40:52.09/chk_obsdata//k5ts1/T1740037??a.dat file size is correct (nominal:880MB, actual:876MB). 2006.174.00:40:52.49/chk_obsdata//k5ts2/T1740037??b.dat file size is correct (nominal:880MB, actual:876MB). 2006.174.00:40:52.88/chk_obsdata//k5ts3/T1740037??c.dat file size is correct (nominal:880MB, actual:876MB). 2006.174.00:40:53.29/chk_obsdata//k5ts4/T1740037??d.dat file size is correct (nominal:880MB, actual:876MB). 2006.174.00:40:54.01/k5log//k5ts1_log_newline 2006.174.00:40:54.71/k5log//k5ts2_log_newline 2006.174.00:40:55.42/k5log//k5ts3_log_newline 2006.174.00:40:56.12/k5log//k5ts4_log_newline 2006.174.00:40:56.14/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.174.00:40:56.14:setupk4=1 2006.174.00:40:56.14$setupk4/echo=on 2006.174.00:40:56.14$setupk4/pcalon 2006.174.00:40:56.14$pcalon/"no phase cal control is implemented here 2006.174.00:40:56.14$setupk4/"tpicd=stop 2006.174.00:40:56.14$setupk4/"rec=synch_on 2006.174.00:40:56.14$setupk4/"rec_mode=128 2006.174.00:40:56.14$setupk4/!* 2006.174.00:40:56.14$setupk4/recpk4 2006.174.00:40:56.14$recpk4/recpatch= 2006.174.00:40:56.14$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.174.00:40:56.14$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.174.00:40:56.14$setupk4/vck44 2006.174.00:40:56.15$vck44/valo=1,524.99 2006.174.00:40:56.15#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.174.00:40:56.15#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.174.00:40:56.15#ibcon#ireg 17 cls_cnt 0 2006.174.00:40:56.15#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.174.00:40:56.15#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.174.00:40:56.15#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.174.00:40:56.15#ibcon#enter wrdev, iclass 24, count 0 2006.174.00:40:56.15#ibcon#first serial, iclass 24, count 0 2006.174.00:40:56.15#ibcon#enter sib2, iclass 24, count 0 2006.174.00:40:56.15#ibcon#flushed, iclass 24, count 0 2006.174.00:40:56.15#ibcon#about to write, iclass 24, count 0 2006.174.00:40:56.15#ibcon#wrote, iclass 24, count 0 2006.174.00:40:56.15#ibcon#about to read 3, iclass 24, count 0 2006.174.00:40:56.16#ibcon#read 3, iclass 24, count 0 2006.174.00:40:56.16#ibcon#about to read 4, iclass 24, count 0 2006.174.00:40:56.16#ibcon#read 4, iclass 24, count 0 2006.174.00:40:56.16#ibcon#about to read 5, iclass 24, count 0 2006.174.00:40:56.16#ibcon#read 5, iclass 24, count 0 2006.174.00:40:56.16#ibcon#about to read 6, iclass 24, count 0 2006.174.00:40:56.16#ibcon#read 6, iclass 24, count 0 2006.174.00:40:56.16#ibcon#end of sib2, iclass 24, count 0 2006.174.00:40:56.16#ibcon#*mode == 0, iclass 24, count 0 2006.174.00:40:56.16#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.174.00:40:56.16#ibcon#[26=FRQ=01,524.99\r\n] 2006.174.00:40:56.16#ibcon#*before write, iclass 24, count 0 2006.174.00:40:56.16#ibcon#enter sib2, iclass 24, count 0 2006.174.00:40:56.16#ibcon#flushed, iclass 24, count 0 2006.174.00:40:56.16#ibcon#about to write, iclass 24, count 0 2006.174.00:40:56.16#ibcon#wrote, iclass 24, count 0 2006.174.00:40:56.16#ibcon#about to read 3, iclass 24, count 0 2006.174.00:40:56.21#ibcon#read 3, iclass 24, count 0 2006.174.00:40:56.21#ibcon#about to read 4, iclass 24, count 0 2006.174.00:40:56.21#ibcon#read 4, iclass 24, count 0 2006.174.00:40:56.21#ibcon#about to read 5, iclass 24, count 0 2006.174.00:40:56.21#ibcon#read 5, iclass 24, count 0 2006.174.00:40:56.21#ibcon#about to read 6, iclass 24, count 0 2006.174.00:40:56.21#ibcon#read 6, iclass 24, count 0 2006.174.00:40:56.21#ibcon#end of sib2, iclass 24, count 0 2006.174.00:40:56.21#ibcon#*after write, iclass 24, count 0 2006.174.00:40:56.21#ibcon#*before return 0, iclass 24, count 0 2006.174.00:40:56.21#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.174.00:40:56.21#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.174.00:40:56.21#ibcon#about to clear, iclass 24 cls_cnt 0 2006.174.00:40:56.21#ibcon#cleared, iclass 24 cls_cnt 0 2006.174.00:40:56.21$vck44/va=1,7 2006.174.00:40:56.21#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.174.00:40:56.21#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.174.00:40:56.21#ibcon#ireg 11 cls_cnt 2 2006.174.00:40:56.21#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.174.00:40:56.21#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.174.00:40:56.21#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.174.00:40:56.21#ibcon#enter wrdev, iclass 26, count 2 2006.174.00:40:56.21#ibcon#first serial, iclass 26, count 2 2006.174.00:40:56.21#ibcon#enter sib2, iclass 26, count 2 2006.174.00:40:56.21#ibcon#flushed, iclass 26, count 2 2006.174.00:40:56.21#ibcon#about to write, iclass 26, count 2 2006.174.00:40:56.21#ibcon#wrote, iclass 26, count 2 2006.174.00:40:56.21#ibcon#about to read 3, iclass 26, count 2 2006.174.00:40:56.23#ibcon#read 3, iclass 26, count 2 2006.174.00:40:56.23#ibcon#about to read 4, iclass 26, count 2 2006.174.00:40:56.23#ibcon#read 4, iclass 26, count 2 2006.174.00:40:56.23#ibcon#about to read 5, iclass 26, count 2 2006.174.00:40:56.23#ibcon#read 5, iclass 26, count 2 2006.174.00:40:56.23#ibcon#about to read 6, iclass 26, count 2 2006.174.00:40:56.23#ibcon#read 6, iclass 26, count 2 2006.174.00:40:56.23#ibcon#end of sib2, iclass 26, count 2 2006.174.00:40:56.23#ibcon#*mode == 0, iclass 26, count 2 2006.174.00:40:56.23#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.174.00:40:56.23#ibcon#[25=AT01-07\r\n] 2006.174.00:40:56.23#ibcon#*before write, iclass 26, count 2 2006.174.00:40:56.23#ibcon#enter sib2, iclass 26, count 2 2006.174.00:40:56.23#ibcon#flushed, iclass 26, count 2 2006.174.00:40:56.23#ibcon#about to write, iclass 26, count 2 2006.174.00:40:56.23#ibcon#wrote, iclass 26, count 2 2006.174.00:40:56.23#ibcon#about to read 3, iclass 26, count 2 2006.174.00:40:56.26#ibcon#read 3, iclass 26, count 2 2006.174.00:40:56.26#ibcon#about to read 4, iclass 26, count 2 2006.174.00:40:56.26#ibcon#read 4, iclass 26, count 2 2006.174.00:40:56.26#ibcon#about to read 5, iclass 26, count 2 2006.174.00:40:56.26#ibcon#read 5, iclass 26, count 2 2006.174.00:40:56.26#ibcon#about to read 6, iclass 26, count 2 2006.174.00:40:56.26#ibcon#read 6, iclass 26, count 2 2006.174.00:40:56.26#ibcon#end of sib2, iclass 26, count 2 2006.174.00:40:56.26#ibcon#*after write, iclass 26, count 2 2006.174.00:40:56.26#ibcon#*before return 0, iclass 26, count 2 2006.174.00:40:56.26#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.174.00:40:56.26#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.174.00:40:56.26#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.174.00:40:56.26#ibcon#ireg 7 cls_cnt 0 2006.174.00:40:56.26#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.174.00:40:56.38#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.174.00:40:56.38#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.174.00:40:56.38#ibcon#enter wrdev, iclass 26, count 0 2006.174.00:40:56.38#ibcon#first serial, iclass 26, count 0 2006.174.00:40:56.38#ibcon#enter sib2, iclass 26, count 0 2006.174.00:40:56.38#ibcon#flushed, iclass 26, count 0 2006.174.00:40:56.38#ibcon#about to write, iclass 26, count 0 2006.174.00:40:56.38#ibcon#wrote, iclass 26, count 0 2006.174.00:40:56.38#ibcon#about to read 3, iclass 26, count 0 2006.174.00:40:56.40#ibcon#read 3, iclass 26, count 0 2006.174.00:40:56.40#ibcon#about to read 4, iclass 26, count 0 2006.174.00:40:56.40#ibcon#read 4, iclass 26, count 0 2006.174.00:40:56.40#ibcon#about to read 5, iclass 26, count 0 2006.174.00:40:56.40#ibcon#read 5, iclass 26, count 0 2006.174.00:40:56.40#ibcon#about to read 6, iclass 26, count 0 2006.174.00:40:56.40#ibcon#read 6, iclass 26, count 0 2006.174.00:40:56.40#ibcon#end of sib2, iclass 26, count 0 2006.174.00:40:56.40#ibcon#*mode == 0, iclass 26, count 0 2006.174.00:40:56.40#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.174.00:40:56.40#ibcon#[25=USB\r\n] 2006.174.00:40:56.40#ibcon#*before write, iclass 26, count 0 2006.174.00:40:56.40#ibcon#enter sib2, iclass 26, count 0 2006.174.00:40:56.40#ibcon#flushed, iclass 26, count 0 2006.174.00:40:56.40#ibcon#about to write, iclass 26, count 0 2006.174.00:40:56.40#ibcon#wrote, iclass 26, count 0 2006.174.00:40:56.40#ibcon#about to read 3, iclass 26, count 0 2006.174.00:40:56.43#ibcon#read 3, iclass 26, count 0 2006.174.00:40:56.43#ibcon#about to read 4, iclass 26, count 0 2006.174.00:40:56.43#ibcon#read 4, iclass 26, count 0 2006.174.00:40:56.43#ibcon#about to read 5, iclass 26, count 0 2006.174.00:40:56.43#ibcon#read 5, iclass 26, count 0 2006.174.00:40:56.43#ibcon#about to read 6, iclass 26, count 0 2006.174.00:40:56.43#ibcon#read 6, iclass 26, count 0 2006.174.00:40:56.43#ibcon#end of sib2, iclass 26, count 0 2006.174.00:40:56.43#ibcon#*after write, iclass 26, count 0 2006.174.00:40:56.43#ibcon#*before return 0, iclass 26, count 0 2006.174.00:40:56.43#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.174.00:40:56.43#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.174.00:40:56.43#ibcon#about to clear, iclass 26 cls_cnt 0 2006.174.00:40:56.43#ibcon#cleared, iclass 26 cls_cnt 0 2006.174.00:40:56.43$vck44/valo=2,534.99 2006.174.00:40:56.43#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.174.00:40:56.43#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.174.00:40:56.43#ibcon#ireg 17 cls_cnt 0 2006.174.00:40:56.43#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.174.00:40:56.43#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.174.00:40:56.43#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.174.00:40:56.43#ibcon#enter wrdev, iclass 28, count 0 2006.174.00:40:56.43#ibcon#first serial, iclass 28, count 0 2006.174.00:40:56.43#ibcon#enter sib2, iclass 28, count 0 2006.174.00:40:56.43#ibcon#flushed, iclass 28, count 0 2006.174.00:40:56.43#ibcon#about to write, iclass 28, count 0 2006.174.00:40:56.43#ibcon#wrote, iclass 28, count 0 2006.174.00:40:56.43#ibcon#about to read 3, iclass 28, count 0 2006.174.00:40:56.45#ibcon#read 3, iclass 28, count 0 2006.174.00:40:56.45#ibcon#about to read 4, iclass 28, count 0 2006.174.00:40:56.45#ibcon#read 4, iclass 28, count 0 2006.174.00:40:56.45#ibcon#about to read 5, iclass 28, count 0 2006.174.00:40:56.45#ibcon#read 5, iclass 28, count 0 2006.174.00:40:56.45#ibcon#about to read 6, iclass 28, count 0 2006.174.00:40:56.45#ibcon#read 6, iclass 28, count 0 2006.174.00:40:56.45#ibcon#end of sib2, iclass 28, count 0 2006.174.00:40:56.45#ibcon#*mode == 0, iclass 28, count 0 2006.174.00:40:56.45#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.174.00:40:56.45#ibcon#[26=FRQ=02,534.99\r\n] 2006.174.00:40:56.45#ibcon#*before write, iclass 28, count 0 2006.174.00:40:56.45#ibcon#enter sib2, iclass 28, count 0 2006.174.00:40:56.45#ibcon#flushed, iclass 28, count 0 2006.174.00:40:56.45#ibcon#about to write, iclass 28, count 0 2006.174.00:40:56.45#ibcon#wrote, iclass 28, count 0 2006.174.00:40:56.45#ibcon#about to read 3, iclass 28, count 0 2006.174.00:40:56.49#ibcon#read 3, iclass 28, count 0 2006.174.00:40:56.49#ibcon#about to read 4, iclass 28, count 0 2006.174.00:40:56.49#ibcon#read 4, iclass 28, count 0 2006.174.00:40:56.49#ibcon#about to read 5, iclass 28, count 0 2006.174.00:40:56.49#ibcon#read 5, iclass 28, count 0 2006.174.00:40:56.49#ibcon#about to read 6, iclass 28, count 0 2006.174.00:40:56.49#ibcon#read 6, iclass 28, count 0 2006.174.00:40:56.49#ibcon#end of sib2, iclass 28, count 0 2006.174.00:40:56.49#ibcon#*after write, iclass 28, count 0 2006.174.00:40:56.49#ibcon#*before return 0, iclass 28, count 0 2006.174.00:40:56.49#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.174.00:40:56.49#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.174.00:40:56.49#ibcon#about to clear, iclass 28 cls_cnt 0 2006.174.00:40:56.49#ibcon#cleared, iclass 28 cls_cnt 0 2006.174.00:40:56.49$vck44/va=2,6 2006.174.00:40:56.49#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.174.00:40:56.49#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.174.00:40:56.49#ibcon#ireg 11 cls_cnt 2 2006.174.00:40:56.49#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.174.00:40:56.53#abcon#<5=/09 0.8 2.4 24.67 831003.3\r\n> 2006.174.00:40:56.55#abcon#{5=INTERFACE CLEAR} 2006.174.00:40:56.55#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.174.00:40:56.55#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.174.00:40:56.55#ibcon#enter wrdev, iclass 31, count 2 2006.174.00:40:56.55#ibcon#first serial, iclass 31, count 2 2006.174.00:40:56.55#ibcon#enter sib2, iclass 31, count 2 2006.174.00:40:56.55#ibcon#flushed, iclass 31, count 2 2006.174.00:40:56.55#ibcon#about to write, iclass 31, count 2 2006.174.00:40:56.55#ibcon#wrote, iclass 31, count 2 2006.174.00:40:56.55#ibcon#about to read 3, iclass 31, count 2 2006.174.00:40:56.57#ibcon#read 3, iclass 31, count 2 2006.174.00:40:56.57#ibcon#about to read 4, iclass 31, count 2 2006.174.00:40:56.57#ibcon#read 4, iclass 31, count 2 2006.174.00:40:56.57#ibcon#about to read 5, iclass 31, count 2 2006.174.00:40:56.57#ibcon#read 5, iclass 31, count 2 2006.174.00:40:56.57#ibcon#about to read 6, iclass 31, count 2 2006.174.00:40:56.57#ibcon#read 6, iclass 31, count 2 2006.174.00:40:56.57#ibcon#end of sib2, iclass 31, count 2 2006.174.00:40:56.57#ibcon#*mode == 0, iclass 31, count 2 2006.174.00:40:56.57#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.174.00:40:56.57#ibcon#[25=AT02-06\r\n] 2006.174.00:40:56.57#ibcon#*before write, iclass 31, count 2 2006.174.00:40:56.57#ibcon#enter sib2, iclass 31, count 2 2006.174.00:40:56.57#ibcon#flushed, iclass 31, count 2 2006.174.00:40:56.57#ibcon#about to write, iclass 31, count 2 2006.174.00:40:56.57#ibcon#wrote, iclass 31, count 2 2006.174.00:40:56.57#ibcon#about to read 3, iclass 31, count 2 2006.174.00:40:56.60#ibcon#read 3, iclass 31, count 2 2006.174.00:40:56.60#ibcon#about to read 4, iclass 31, count 2 2006.174.00:40:56.60#ibcon#read 4, iclass 31, count 2 2006.174.00:40:56.60#ibcon#about to read 5, iclass 31, count 2 2006.174.00:40:56.60#ibcon#read 5, iclass 31, count 2 2006.174.00:40:56.60#ibcon#about to read 6, iclass 31, count 2 2006.174.00:40:56.60#ibcon#read 6, iclass 31, count 2 2006.174.00:40:56.60#ibcon#end of sib2, iclass 31, count 2 2006.174.00:40:56.60#ibcon#*after write, iclass 31, count 2 2006.174.00:40:56.60#ibcon#*before return 0, iclass 31, count 2 2006.174.00:40:56.60#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.174.00:40:56.60#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.174.00:40:56.60#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.174.00:40:56.60#ibcon#ireg 7 cls_cnt 0 2006.174.00:40:56.60#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.174.00:40:56.61#abcon#[5=S1D000X0/0*\r\n] 2006.174.00:40:56.72#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.174.00:40:56.72#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.174.00:40:56.72#ibcon#enter wrdev, iclass 31, count 0 2006.174.00:40:56.72#ibcon#first serial, iclass 31, count 0 2006.174.00:40:56.72#ibcon#enter sib2, iclass 31, count 0 2006.174.00:40:56.72#ibcon#flushed, iclass 31, count 0 2006.174.00:40:56.72#ibcon#about to write, iclass 31, count 0 2006.174.00:40:56.72#ibcon#wrote, iclass 31, count 0 2006.174.00:40:56.72#ibcon#about to read 3, iclass 31, count 0 2006.174.00:40:56.74#ibcon#read 3, iclass 31, count 0 2006.174.00:40:56.74#ibcon#about to read 4, iclass 31, count 0 2006.174.00:40:56.74#ibcon#read 4, iclass 31, count 0 2006.174.00:40:56.74#ibcon#about to read 5, iclass 31, count 0 2006.174.00:40:56.74#ibcon#read 5, iclass 31, count 0 2006.174.00:40:56.74#ibcon#about to read 6, iclass 31, count 0 2006.174.00:40:56.74#ibcon#read 6, iclass 31, count 0 2006.174.00:40:56.74#ibcon#end of sib2, iclass 31, count 0 2006.174.00:40:56.74#ibcon#*mode == 0, iclass 31, count 0 2006.174.00:40:56.74#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.174.00:40:56.74#ibcon#[25=USB\r\n] 2006.174.00:40:56.74#ibcon#*before write, iclass 31, count 0 2006.174.00:40:56.74#ibcon#enter sib2, iclass 31, count 0 2006.174.00:40:56.74#ibcon#flushed, iclass 31, count 0 2006.174.00:40:56.74#ibcon#about to write, iclass 31, count 0 2006.174.00:40:56.74#ibcon#wrote, iclass 31, count 0 2006.174.00:40:56.74#ibcon#about to read 3, iclass 31, count 0 2006.174.00:40:56.77#ibcon#read 3, iclass 31, count 0 2006.174.00:40:56.77#ibcon#about to read 4, iclass 31, count 0 2006.174.00:40:56.77#ibcon#read 4, iclass 31, count 0 2006.174.00:40:56.77#ibcon#about to read 5, iclass 31, count 0 2006.174.00:40:56.77#ibcon#read 5, iclass 31, count 0 2006.174.00:40:56.77#ibcon#about to read 6, iclass 31, count 0 2006.174.00:40:56.77#ibcon#read 6, iclass 31, count 0 2006.174.00:40:56.77#ibcon#end of sib2, iclass 31, count 0 2006.174.00:40:56.77#ibcon#*after write, iclass 31, count 0 2006.174.00:40:56.77#ibcon#*before return 0, iclass 31, count 0 2006.174.00:40:56.77#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.174.00:40:56.77#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.174.00:40:56.77#ibcon#about to clear, iclass 31 cls_cnt 0 2006.174.00:40:56.77#ibcon#cleared, iclass 31 cls_cnt 0 2006.174.00:40:56.77$vck44/valo=3,564.99 2006.174.00:40:56.77#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.174.00:40:56.77#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.174.00:40:56.77#ibcon#ireg 17 cls_cnt 0 2006.174.00:40:56.77#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.174.00:40:56.77#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.174.00:40:56.77#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.174.00:40:56.77#ibcon#enter wrdev, iclass 36, count 0 2006.174.00:40:56.77#ibcon#first serial, iclass 36, count 0 2006.174.00:40:56.77#ibcon#enter sib2, iclass 36, count 0 2006.174.00:40:56.77#ibcon#flushed, iclass 36, count 0 2006.174.00:40:56.77#ibcon#about to write, iclass 36, count 0 2006.174.00:40:56.77#ibcon#wrote, iclass 36, count 0 2006.174.00:40:56.77#ibcon#about to read 3, iclass 36, count 0 2006.174.00:40:56.79#ibcon#read 3, iclass 36, count 0 2006.174.00:40:56.79#ibcon#about to read 4, iclass 36, count 0 2006.174.00:40:56.79#ibcon#read 4, iclass 36, count 0 2006.174.00:40:56.79#ibcon#about to read 5, iclass 36, count 0 2006.174.00:40:56.79#ibcon#read 5, iclass 36, count 0 2006.174.00:40:56.79#ibcon#about to read 6, iclass 36, count 0 2006.174.00:40:56.79#ibcon#read 6, iclass 36, count 0 2006.174.00:40:56.79#ibcon#end of sib2, iclass 36, count 0 2006.174.00:40:56.79#ibcon#*mode == 0, iclass 36, count 0 2006.174.00:40:56.79#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.174.00:40:56.79#ibcon#[26=FRQ=03,564.99\r\n] 2006.174.00:40:56.79#ibcon#*before write, iclass 36, count 0 2006.174.00:40:56.79#ibcon#enter sib2, iclass 36, count 0 2006.174.00:40:56.79#ibcon#flushed, iclass 36, count 0 2006.174.00:40:56.79#ibcon#about to write, iclass 36, count 0 2006.174.00:40:56.79#ibcon#wrote, iclass 36, count 0 2006.174.00:40:56.79#ibcon#about to read 3, iclass 36, count 0 2006.174.00:40:56.83#ibcon#read 3, iclass 36, count 0 2006.174.00:40:56.83#ibcon#about to read 4, iclass 36, count 0 2006.174.00:40:56.83#ibcon#read 4, iclass 36, count 0 2006.174.00:40:56.83#ibcon#about to read 5, iclass 36, count 0 2006.174.00:40:56.83#ibcon#read 5, iclass 36, count 0 2006.174.00:40:56.83#ibcon#about to read 6, iclass 36, count 0 2006.174.00:40:56.83#ibcon#read 6, iclass 36, count 0 2006.174.00:40:56.83#ibcon#end of sib2, iclass 36, count 0 2006.174.00:40:56.83#ibcon#*after write, iclass 36, count 0 2006.174.00:40:56.83#ibcon#*before return 0, iclass 36, count 0 2006.174.00:40:56.83#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.174.00:40:56.83#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.174.00:40:56.83#ibcon#about to clear, iclass 36 cls_cnt 0 2006.174.00:40:56.83#ibcon#cleared, iclass 36 cls_cnt 0 2006.174.00:40:56.83$vck44/va=3,5 2006.174.00:40:56.83#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.174.00:40:56.83#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.174.00:40:56.83#ibcon#ireg 11 cls_cnt 2 2006.174.00:40:56.83#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.174.00:40:56.89#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.174.00:40:56.89#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.174.00:40:56.89#ibcon#enter wrdev, iclass 38, count 2 2006.174.00:40:56.89#ibcon#first serial, iclass 38, count 2 2006.174.00:40:56.89#ibcon#enter sib2, iclass 38, count 2 2006.174.00:40:56.89#ibcon#flushed, iclass 38, count 2 2006.174.00:40:56.89#ibcon#about to write, iclass 38, count 2 2006.174.00:40:56.89#ibcon#wrote, iclass 38, count 2 2006.174.00:40:56.89#ibcon#about to read 3, iclass 38, count 2 2006.174.00:40:56.91#ibcon#read 3, iclass 38, count 2 2006.174.00:40:56.91#ibcon#about to read 4, iclass 38, count 2 2006.174.00:40:56.91#ibcon#read 4, iclass 38, count 2 2006.174.00:40:56.91#ibcon#about to read 5, iclass 38, count 2 2006.174.00:40:56.91#ibcon#read 5, iclass 38, count 2 2006.174.00:40:56.91#ibcon#about to read 6, iclass 38, count 2 2006.174.00:40:56.91#ibcon#read 6, iclass 38, count 2 2006.174.00:40:56.91#ibcon#end of sib2, iclass 38, count 2 2006.174.00:40:56.91#ibcon#*mode == 0, iclass 38, count 2 2006.174.00:40:56.91#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.174.00:40:56.91#ibcon#[25=AT03-05\r\n] 2006.174.00:40:56.91#ibcon#*before write, iclass 38, count 2 2006.174.00:40:56.91#ibcon#enter sib2, iclass 38, count 2 2006.174.00:40:56.91#ibcon#flushed, iclass 38, count 2 2006.174.00:40:56.91#ibcon#about to write, iclass 38, count 2 2006.174.00:40:56.91#ibcon#wrote, iclass 38, count 2 2006.174.00:40:56.91#ibcon#about to read 3, iclass 38, count 2 2006.174.00:40:56.94#ibcon#read 3, iclass 38, count 2 2006.174.00:40:56.94#ibcon#about to read 4, iclass 38, count 2 2006.174.00:40:56.94#ibcon#read 4, iclass 38, count 2 2006.174.00:40:56.94#ibcon#about to read 5, iclass 38, count 2 2006.174.00:40:56.94#ibcon#read 5, iclass 38, count 2 2006.174.00:40:56.94#ibcon#about to read 6, iclass 38, count 2 2006.174.00:40:56.94#ibcon#read 6, iclass 38, count 2 2006.174.00:40:56.94#ibcon#end of sib2, iclass 38, count 2 2006.174.00:40:56.94#ibcon#*after write, iclass 38, count 2 2006.174.00:40:56.94#ibcon#*before return 0, iclass 38, count 2 2006.174.00:40:56.94#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.174.00:40:56.94#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.174.00:40:56.94#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.174.00:40:56.94#ibcon#ireg 7 cls_cnt 0 2006.174.00:40:56.94#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.174.00:40:57.06#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.174.00:40:57.06#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.174.00:40:57.06#ibcon#enter wrdev, iclass 38, count 0 2006.174.00:40:57.06#ibcon#first serial, iclass 38, count 0 2006.174.00:40:57.06#ibcon#enter sib2, iclass 38, count 0 2006.174.00:40:57.06#ibcon#flushed, iclass 38, count 0 2006.174.00:40:57.06#ibcon#about to write, iclass 38, count 0 2006.174.00:40:57.06#ibcon#wrote, iclass 38, count 0 2006.174.00:40:57.06#ibcon#about to read 3, iclass 38, count 0 2006.174.00:40:57.08#ibcon#read 3, iclass 38, count 0 2006.174.00:40:57.08#ibcon#about to read 4, iclass 38, count 0 2006.174.00:40:57.08#ibcon#read 4, iclass 38, count 0 2006.174.00:40:57.08#ibcon#about to read 5, iclass 38, count 0 2006.174.00:40:57.08#ibcon#read 5, iclass 38, count 0 2006.174.00:40:57.08#ibcon#about to read 6, iclass 38, count 0 2006.174.00:40:57.08#ibcon#read 6, iclass 38, count 0 2006.174.00:40:57.08#ibcon#end of sib2, iclass 38, count 0 2006.174.00:40:57.08#ibcon#*mode == 0, iclass 38, count 0 2006.174.00:40:57.08#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.174.00:40:57.08#ibcon#[25=USB\r\n] 2006.174.00:40:57.08#ibcon#*before write, iclass 38, count 0 2006.174.00:40:57.08#ibcon#enter sib2, iclass 38, count 0 2006.174.00:40:57.08#ibcon#flushed, iclass 38, count 0 2006.174.00:40:57.08#ibcon#about to write, iclass 38, count 0 2006.174.00:40:57.08#ibcon#wrote, iclass 38, count 0 2006.174.00:40:57.08#ibcon#about to read 3, iclass 38, count 0 2006.174.00:40:57.11#ibcon#read 3, iclass 38, count 0 2006.174.00:40:57.11#ibcon#about to read 4, iclass 38, count 0 2006.174.00:40:57.11#ibcon#read 4, iclass 38, count 0 2006.174.00:40:57.11#ibcon#about to read 5, iclass 38, count 0 2006.174.00:40:57.11#ibcon#read 5, iclass 38, count 0 2006.174.00:40:57.11#ibcon#about to read 6, iclass 38, count 0 2006.174.00:40:57.11#ibcon#read 6, iclass 38, count 0 2006.174.00:40:57.11#ibcon#end of sib2, iclass 38, count 0 2006.174.00:40:57.11#ibcon#*after write, iclass 38, count 0 2006.174.00:40:57.11#ibcon#*before return 0, iclass 38, count 0 2006.174.00:40:57.11#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.174.00:40:57.11#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.174.00:40:57.11#ibcon#about to clear, iclass 38 cls_cnt 0 2006.174.00:40:57.11#ibcon#cleared, iclass 38 cls_cnt 0 2006.174.00:40:57.11$vck44/valo=4,624.99 2006.174.00:40:57.11#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.174.00:40:57.11#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.174.00:40:57.11#ibcon#ireg 17 cls_cnt 0 2006.174.00:40:57.11#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.174.00:40:57.11#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.174.00:40:57.11#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.174.00:40:57.11#ibcon#enter wrdev, iclass 40, count 0 2006.174.00:40:57.11#ibcon#first serial, iclass 40, count 0 2006.174.00:40:57.11#ibcon#enter sib2, iclass 40, count 0 2006.174.00:40:57.11#ibcon#flushed, iclass 40, count 0 2006.174.00:40:57.11#ibcon#about to write, iclass 40, count 0 2006.174.00:40:57.11#ibcon#wrote, iclass 40, count 0 2006.174.00:40:57.11#ibcon#about to read 3, iclass 40, count 0 2006.174.00:40:57.13#ibcon#read 3, iclass 40, count 0 2006.174.00:40:57.13#ibcon#about to read 4, iclass 40, count 0 2006.174.00:40:57.13#ibcon#read 4, iclass 40, count 0 2006.174.00:40:57.13#ibcon#about to read 5, iclass 40, count 0 2006.174.00:40:57.13#ibcon#read 5, iclass 40, count 0 2006.174.00:40:57.13#ibcon#about to read 6, iclass 40, count 0 2006.174.00:40:57.13#ibcon#read 6, iclass 40, count 0 2006.174.00:40:57.13#ibcon#end of sib2, iclass 40, count 0 2006.174.00:40:57.13#ibcon#*mode == 0, iclass 40, count 0 2006.174.00:40:57.13#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.174.00:40:57.13#ibcon#[26=FRQ=04,624.99\r\n] 2006.174.00:40:57.13#ibcon#*before write, iclass 40, count 0 2006.174.00:40:57.13#ibcon#enter sib2, iclass 40, count 0 2006.174.00:40:57.13#ibcon#flushed, iclass 40, count 0 2006.174.00:40:57.13#ibcon#about to write, iclass 40, count 0 2006.174.00:40:57.13#ibcon#wrote, iclass 40, count 0 2006.174.00:40:57.13#ibcon#about to read 3, iclass 40, count 0 2006.174.00:40:57.17#ibcon#read 3, iclass 40, count 0 2006.174.00:40:57.17#ibcon#about to read 4, iclass 40, count 0 2006.174.00:40:57.17#ibcon#read 4, iclass 40, count 0 2006.174.00:40:57.17#ibcon#about to read 5, iclass 40, count 0 2006.174.00:40:57.17#ibcon#read 5, iclass 40, count 0 2006.174.00:40:57.17#ibcon#about to read 6, iclass 40, count 0 2006.174.00:40:57.17#ibcon#read 6, iclass 40, count 0 2006.174.00:40:57.17#ibcon#end of sib2, iclass 40, count 0 2006.174.00:40:57.17#ibcon#*after write, iclass 40, count 0 2006.174.00:40:57.17#ibcon#*before return 0, iclass 40, count 0 2006.174.00:40:57.17#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.174.00:40:57.17#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.174.00:40:57.17#ibcon#about to clear, iclass 40 cls_cnt 0 2006.174.00:40:57.17#ibcon#cleared, iclass 40 cls_cnt 0 2006.174.00:40:57.17$vck44/va=4,6 2006.174.00:40:57.17#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.174.00:40:57.17#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.174.00:40:57.17#ibcon#ireg 11 cls_cnt 2 2006.174.00:40:57.17#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.174.00:40:57.23#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.174.00:40:57.23#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.174.00:40:57.23#ibcon#enter wrdev, iclass 4, count 2 2006.174.00:40:57.23#ibcon#first serial, iclass 4, count 2 2006.174.00:40:57.23#ibcon#enter sib2, iclass 4, count 2 2006.174.00:40:57.23#ibcon#flushed, iclass 4, count 2 2006.174.00:40:57.23#ibcon#about to write, iclass 4, count 2 2006.174.00:40:57.23#ibcon#wrote, iclass 4, count 2 2006.174.00:40:57.23#ibcon#about to read 3, iclass 4, count 2 2006.174.00:40:57.25#ibcon#read 3, iclass 4, count 2 2006.174.00:40:57.25#ibcon#about to read 4, iclass 4, count 2 2006.174.00:40:57.25#ibcon#read 4, iclass 4, count 2 2006.174.00:40:57.25#ibcon#about to read 5, iclass 4, count 2 2006.174.00:40:57.25#ibcon#read 5, iclass 4, count 2 2006.174.00:40:57.25#ibcon#about to read 6, iclass 4, count 2 2006.174.00:40:57.25#ibcon#read 6, iclass 4, count 2 2006.174.00:40:57.25#ibcon#end of sib2, iclass 4, count 2 2006.174.00:40:57.25#ibcon#*mode == 0, iclass 4, count 2 2006.174.00:40:57.25#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.174.00:40:57.25#ibcon#[25=AT04-06\r\n] 2006.174.00:40:57.25#ibcon#*before write, iclass 4, count 2 2006.174.00:40:57.25#ibcon#enter sib2, iclass 4, count 2 2006.174.00:40:57.25#ibcon#flushed, iclass 4, count 2 2006.174.00:40:57.25#ibcon#about to write, iclass 4, count 2 2006.174.00:40:57.25#ibcon#wrote, iclass 4, count 2 2006.174.00:40:57.25#ibcon#about to read 3, iclass 4, count 2 2006.174.00:40:57.28#ibcon#read 3, iclass 4, count 2 2006.174.00:40:57.28#ibcon#about to read 4, iclass 4, count 2 2006.174.00:40:57.28#ibcon#read 4, iclass 4, count 2 2006.174.00:40:57.28#ibcon#about to read 5, iclass 4, count 2 2006.174.00:40:57.28#ibcon#read 5, iclass 4, count 2 2006.174.00:40:57.28#ibcon#about to read 6, iclass 4, count 2 2006.174.00:40:57.28#ibcon#read 6, iclass 4, count 2 2006.174.00:40:57.28#ibcon#end of sib2, iclass 4, count 2 2006.174.00:40:57.28#ibcon#*after write, iclass 4, count 2 2006.174.00:40:57.28#ibcon#*before return 0, iclass 4, count 2 2006.174.00:40:57.28#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.174.00:40:57.28#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.174.00:40:57.28#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.174.00:40:57.28#ibcon#ireg 7 cls_cnt 0 2006.174.00:40:57.28#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.174.00:40:57.40#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.174.00:40:57.40#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.174.00:40:57.40#ibcon#enter wrdev, iclass 4, count 0 2006.174.00:40:57.40#ibcon#first serial, iclass 4, count 0 2006.174.00:40:57.40#ibcon#enter sib2, iclass 4, count 0 2006.174.00:40:57.40#ibcon#flushed, iclass 4, count 0 2006.174.00:40:57.40#ibcon#about to write, iclass 4, count 0 2006.174.00:40:57.40#ibcon#wrote, iclass 4, count 0 2006.174.00:40:57.40#ibcon#about to read 3, iclass 4, count 0 2006.174.00:40:57.42#ibcon#read 3, iclass 4, count 0 2006.174.00:40:57.42#ibcon#about to read 4, iclass 4, count 0 2006.174.00:40:57.42#ibcon#read 4, iclass 4, count 0 2006.174.00:40:57.42#ibcon#about to read 5, iclass 4, count 0 2006.174.00:40:57.42#ibcon#read 5, iclass 4, count 0 2006.174.00:40:57.42#ibcon#about to read 6, iclass 4, count 0 2006.174.00:40:57.42#ibcon#read 6, iclass 4, count 0 2006.174.00:40:57.42#ibcon#end of sib2, iclass 4, count 0 2006.174.00:40:57.42#ibcon#*mode == 0, iclass 4, count 0 2006.174.00:40:57.42#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.174.00:40:57.42#ibcon#[25=USB\r\n] 2006.174.00:40:57.42#ibcon#*before write, iclass 4, count 0 2006.174.00:40:57.42#ibcon#enter sib2, iclass 4, count 0 2006.174.00:40:57.42#ibcon#flushed, iclass 4, count 0 2006.174.00:40:57.42#ibcon#about to write, iclass 4, count 0 2006.174.00:40:57.42#ibcon#wrote, iclass 4, count 0 2006.174.00:40:57.42#ibcon#about to read 3, iclass 4, count 0 2006.174.00:40:57.45#ibcon#read 3, iclass 4, count 0 2006.174.00:40:57.45#ibcon#about to read 4, iclass 4, count 0 2006.174.00:40:57.45#ibcon#read 4, iclass 4, count 0 2006.174.00:40:57.45#ibcon#about to read 5, iclass 4, count 0 2006.174.00:40:57.45#ibcon#read 5, iclass 4, count 0 2006.174.00:40:57.45#ibcon#about to read 6, iclass 4, count 0 2006.174.00:40:57.45#ibcon#read 6, iclass 4, count 0 2006.174.00:40:57.45#ibcon#end of sib2, iclass 4, count 0 2006.174.00:40:57.45#ibcon#*after write, iclass 4, count 0 2006.174.00:40:57.45#ibcon#*before return 0, iclass 4, count 0 2006.174.00:40:57.45#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.174.00:40:57.45#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.174.00:40:57.45#ibcon#about to clear, iclass 4 cls_cnt 0 2006.174.00:40:57.45#ibcon#cleared, iclass 4 cls_cnt 0 2006.174.00:40:57.45$vck44/valo=5,734.99 2006.174.00:40:57.45#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.174.00:40:57.45#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.174.00:40:57.45#ibcon#ireg 17 cls_cnt 0 2006.174.00:40:57.45#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.174.00:40:57.45#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.174.00:40:57.45#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.174.00:40:57.45#ibcon#enter wrdev, iclass 6, count 0 2006.174.00:40:57.45#ibcon#first serial, iclass 6, count 0 2006.174.00:40:57.45#ibcon#enter sib2, iclass 6, count 0 2006.174.00:40:57.45#ibcon#flushed, iclass 6, count 0 2006.174.00:40:57.45#ibcon#about to write, iclass 6, count 0 2006.174.00:40:57.45#ibcon#wrote, iclass 6, count 0 2006.174.00:40:57.45#ibcon#about to read 3, iclass 6, count 0 2006.174.00:40:57.47#ibcon#read 3, iclass 6, count 0 2006.174.00:40:57.47#ibcon#about to read 4, iclass 6, count 0 2006.174.00:40:57.47#ibcon#read 4, iclass 6, count 0 2006.174.00:40:57.47#ibcon#about to read 5, iclass 6, count 0 2006.174.00:40:57.47#ibcon#read 5, iclass 6, count 0 2006.174.00:40:57.47#ibcon#about to read 6, iclass 6, count 0 2006.174.00:40:57.47#ibcon#read 6, iclass 6, count 0 2006.174.00:40:57.47#ibcon#end of sib2, iclass 6, count 0 2006.174.00:40:57.47#ibcon#*mode == 0, iclass 6, count 0 2006.174.00:40:57.47#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.174.00:40:57.47#ibcon#[26=FRQ=05,734.99\r\n] 2006.174.00:40:57.47#ibcon#*before write, iclass 6, count 0 2006.174.00:40:57.47#ibcon#enter sib2, iclass 6, count 0 2006.174.00:40:57.47#ibcon#flushed, iclass 6, count 0 2006.174.00:40:57.47#ibcon#about to write, iclass 6, count 0 2006.174.00:40:57.47#ibcon#wrote, iclass 6, count 0 2006.174.00:40:57.47#ibcon#about to read 3, iclass 6, count 0 2006.174.00:40:57.51#ibcon#read 3, iclass 6, count 0 2006.174.00:40:57.51#ibcon#about to read 4, iclass 6, count 0 2006.174.00:40:57.51#ibcon#read 4, iclass 6, count 0 2006.174.00:40:57.51#ibcon#about to read 5, iclass 6, count 0 2006.174.00:40:57.51#ibcon#read 5, iclass 6, count 0 2006.174.00:40:57.51#ibcon#about to read 6, iclass 6, count 0 2006.174.00:40:57.51#ibcon#read 6, iclass 6, count 0 2006.174.00:40:57.51#ibcon#end of sib2, iclass 6, count 0 2006.174.00:40:57.51#ibcon#*after write, iclass 6, count 0 2006.174.00:40:57.51#ibcon#*before return 0, iclass 6, count 0 2006.174.00:40:57.51#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.174.00:40:57.51#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.174.00:40:57.51#ibcon#about to clear, iclass 6 cls_cnt 0 2006.174.00:40:57.51#ibcon#cleared, iclass 6 cls_cnt 0 2006.174.00:40:57.51$vck44/va=5,4 2006.174.00:40:57.51#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.174.00:40:57.51#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.174.00:40:57.51#ibcon#ireg 11 cls_cnt 2 2006.174.00:40:57.51#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.174.00:40:57.57#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.174.00:40:57.57#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.174.00:40:57.57#ibcon#enter wrdev, iclass 10, count 2 2006.174.00:40:57.57#ibcon#first serial, iclass 10, count 2 2006.174.00:40:57.57#ibcon#enter sib2, iclass 10, count 2 2006.174.00:40:57.57#ibcon#flushed, iclass 10, count 2 2006.174.00:40:57.57#ibcon#about to write, iclass 10, count 2 2006.174.00:40:57.57#ibcon#wrote, iclass 10, count 2 2006.174.00:40:57.57#ibcon#about to read 3, iclass 10, count 2 2006.174.00:40:57.59#ibcon#read 3, iclass 10, count 2 2006.174.00:40:57.59#ibcon#about to read 4, iclass 10, count 2 2006.174.00:40:57.59#ibcon#read 4, iclass 10, count 2 2006.174.00:40:57.59#ibcon#about to read 5, iclass 10, count 2 2006.174.00:40:57.59#ibcon#read 5, iclass 10, count 2 2006.174.00:40:57.59#ibcon#about to read 6, iclass 10, count 2 2006.174.00:40:57.59#ibcon#read 6, iclass 10, count 2 2006.174.00:40:57.59#ibcon#end of sib2, iclass 10, count 2 2006.174.00:40:57.59#ibcon#*mode == 0, iclass 10, count 2 2006.174.00:40:57.59#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.174.00:40:57.59#ibcon#[25=AT05-04\r\n] 2006.174.00:40:57.59#ibcon#*before write, iclass 10, count 2 2006.174.00:40:57.59#ibcon#enter sib2, iclass 10, count 2 2006.174.00:40:57.59#ibcon#flushed, iclass 10, count 2 2006.174.00:40:57.59#ibcon#about to write, iclass 10, count 2 2006.174.00:40:57.59#ibcon#wrote, iclass 10, count 2 2006.174.00:40:57.59#ibcon#about to read 3, iclass 10, count 2 2006.174.00:40:57.62#ibcon#read 3, iclass 10, count 2 2006.174.00:40:57.62#ibcon#about to read 4, iclass 10, count 2 2006.174.00:40:57.62#ibcon#read 4, iclass 10, count 2 2006.174.00:40:57.62#ibcon#about to read 5, iclass 10, count 2 2006.174.00:40:57.62#ibcon#read 5, iclass 10, count 2 2006.174.00:40:57.62#ibcon#about to read 6, iclass 10, count 2 2006.174.00:40:57.62#ibcon#read 6, iclass 10, count 2 2006.174.00:40:57.62#ibcon#end of sib2, iclass 10, count 2 2006.174.00:40:57.62#ibcon#*after write, iclass 10, count 2 2006.174.00:40:57.62#ibcon#*before return 0, iclass 10, count 2 2006.174.00:40:57.62#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.174.00:40:57.62#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.174.00:40:57.62#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.174.00:40:57.62#ibcon#ireg 7 cls_cnt 0 2006.174.00:40:57.62#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.174.00:40:57.74#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.174.00:40:57.74#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.174.00:40:57.74#ibcon#enter wrdev, iclass 10, count 0 2006.174.00:40:57.74#ibcon#first serial, iclass 10, count 0 2006.174.00:40:57.74#ibcon#enter sib2, iclass 10, count 0 2006.174.00:40:57.74#ibcon#flushed, iclass 10, count 0 2006.174.00:40:57.74#ibcon#about to write, iclass 10, count 0 2006.174.00:40:57.74#ibcon#wrote, iclass 10, count 0 2006.174.00:40:57.74#ibcon#about to read 3, iclass 10, count 0 2006.174.00:40:57.76#ibcon#read 3, iclass 10, count 0 2006.174.00:40:57.76#ibcon#about to read 4, iclass 10, count 0 2006.174.00:40:57.76#ibcon#read 4, iclass 10, count 0 2006.174.00:40:57.76#ibcon#about to read 5, iclass 10, count 0 2006.174.00:40:57.76#ibcon#read 5, iclass 10, count 0 2006.174.00:40:57.76#ibcon#about to read 6, iclass 10, count 0 2006.174.00:40:57.76#ibcon#read 6, iclass 10, count 0 2006.174.00:40:57.76#ibcon#end of sib2, iclass 10, count 0 2006.174.00:40:57.76#ibcon#*mode == 0, iclass 10, count 0 2006.174.00:40:57.76#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.174.00:40:57.76#ibcon#[25=USB\r\n] 2006.174.00:40:57.76#ibcon#*before write, iclass 10, count 0 2006.174.00:40:57.76#ibcon#enter sib2, iclass 10, count 0 2006.174.00:40:57.76#ibcon#flushed, iclass 10, count 0 2006.174.00:40:57.76#ibcon#about to write, iclass 10, count 0 2006.174.00:40:57.76#ibcon#wrote, iclass 10, count 0 2006.174.00:40:57.76#ibcon#about to read 3, iclass 10, count 0 2006.174.00:40:57.79#ibcon#read 3, iclass 10, count 0 2006.174.00:40:57.79#ibcon#about to read 4, iclass 10, count 0 2006.174.00:40:57.79#ibcon#read 4, iclass 10, count 0 2006.174.00:40:57.79#ibcon#about to read 5, iclass 10, count 0 2006.174.00:40:57.79#ibcon#read 5, iclass 10, count 0 2006.174.00:40:57.79#ibcon#about to read 6, iclass 10, count 0 2006.174.00:40:57.79#ibcon#read 6, iclass 10, count 0 2006.174.00:40:57.79#ibcon#end of sib2, iclass 10, count 0 2006.174.00:40:57.79#ibcon#*after write, iclass 10, count 0 2006.174.00:40:57.79#ibcon#*before return 0, iclass 10, count 0 2006.174.00:40:57.79#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.174.00:40:57.79#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.174.00:40:57.79#ibcon#about to clear, iclass 10 cls_cnt 0 2006.174.00:40:57.79#ibcon#cleared, iclass 10 cls_cnt 0 2006.174.00:40:57.79$vck44/valo=6,814.99 2006.174.00:40:57.79#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.174.00:40:57.79#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.174.00:40:57.79#ibcon#ireg 17 cls_cnt 0 2006.174.00:40:57.79#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.174.00:40:57.79#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.174.00:40:57.79#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.174.00:40:57.79#ibcon#enter wrdev, iclass 12, count 0 2006.174.00:40:57.79#ibcon#first serial, iclass 12, count 0 2006.174.00:40:57.79#ibcon#enter sib2, iclass 12, count 0 2006.174.00:40:57.79#ibcon#flushed, iclass 12, count 0 2006.174.00:40:57.79#ibcon#about to write, iclass 12, count 0 2006.174.00:40:57.79#ibcon#wrote, iclass 12, count 0 2006.174.00:40:57.79#ibcon#about to read 3, iclass 12, count 0 2006.174.00:40:57.81#ibcon#read 3, iclass 12, count 0 2006.174.00:40:57.81#ibcon#about to read 4, iclass 12, count 0 2006.174.00:40:57.81#ibcon#read 4, iclass 12, count 0 2006.174.00:40:57.81#ibcon#about to read 5, iclass 12, count 0 2006.174.00:40:57.81#ibcon#read 5, iclass 12, count 0 2006.174.00:40:57.81#ibcon#about to read 6, iclass 12, count 0 2006.174.00:40:57.81#ibcon#read 6, iclass 12, count 0 2006.174.00:40:57.81#ibcon#end of sib2, iclass 12, count 0 2006.174.00:40:57.81#ibcon#*mode == 0, iclass 12, count 0 2006.174.00:40:57.81#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.174.00:40:57.81#ibcon#[26=FRQ=06,814.99\r\n] 2006.174.00:40:57.81#ibcon#*before write, iclass 12, count 0 2006.174.00:40:57.81#ibcon#enter sib2, iclass 12, count 0 2006.174.00:40:57.81#ibcon#flushed, iclass 12, count 0 2006.174.00:40:57.81#ibcon#about to write, iclass 12, count 0 2006.174.00:40:57.81#ibcon#wrote, iclass 12, count 0 2006.174.00:40:57.81#ibcon#about to read 3, iclass 12, count 0 2006.174.00:40:57.85#ibcon#read 3, iclass 12, count 0 2006.174.00:40:57.85#ibcon#about to read 4, iclass 12, count 0 2006.174.00:40:57.85#ibcon#read 4, iclass 12, count 0 2006.174.00:40:57.85#ibcon#about to read 5, iclass 12, count 0 2006.174.00:40:57.85#ibcon#read 5, iclass 12, count 0 2006.174.00:40:57.85#ibcon#about to read 6, iclass 12, count 0 2006.174.00:40:57.85#ibcon#read 6, iclass 12, count 0 2006.174.00:40:57.85#ibcon#end of sib2, iclass 12, count 0 2006.174.00:40:57.85#ibcon#*after write, iclass 12, count 0 2006.174.00:40:57.85#ibcon#*before return 0, iclass 12, count 0 2006.174.00:40:57.85#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.174.00:40:57.85#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.174.00:40:57.85#ibcon#about to clear, iclass 12 cls_cnt 0 2006.174.00:40:57.85#ibcon#cleared, iclass 12 cls_cnt 0 2006.174.00:40:57.85$vck44/va=6,3 2006.174.00:40:57.85#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.174.00:40:57.85#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.174.00:40:57.85#ibcon#ireg 11 cls_cnt 2 2006.174.00:40:57.85#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.174.00:40:57.91#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.174.00:40:57.91#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.174.00:40:57.91#ibcon#enter wrdev, iclass 14, count 2 2006.174.00:40:57.91#ibcon#first serial, iclass 14, count 2 2006.174.00:40:57.91#ibcon#enter sib2, iclass 14, count 2 2006.174.00:40:57.91#ibcon#flushed, iclass 14, count 2 2006.174.00:40:57.91#ibcon#about to write, iclass 14, count 2 2006.174.00:40:57.91#ibcon#wrote, iclass 14, count 2 2006.174.00:40:57.91#ibcon#about to read 3, iclass 14, count 2 2006.174.00:40:57.93#ibcon#read 3, iclass 14, count 2 2006.174.00:40:57.93#ibcon#about to read 4, iclass 14, count 2 2006.174.00:40:57.93#ibcon#read 4, iclass 14, count 2 2006.174.00:40:57.93#ibcon#about to read 5, iclass 14, count 2 2006.174.00:40:57.93#ibcon#read 5, iclass 14, count 2 2006.174.00:40:57.93#ibcon#about to read 6, iclass 14, count 2 2006.174.00:40:57.93#ibcon#read 6, iclass 14, count 2 2006.174.00:40:57.93#ibcon#end of sib2, iclass 14, count 2 2006.174.00:40:57.93#ibcon#*mode == 0, iclass 14, count 2 2006.174.00:40:57.93#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.174.00:40:57.93#ibcon#[25=AT06-03\r\n] 2006.174.00:40:57.93#ibcon#*before write, iclass 14, count 2 2006.174.00:40:57.93#ibcon#enter sib2, iclass 14, count 2 2006.174.00:40:57.93#ibcon#flushed, iclass 14, count 2 2006.174.00:40:57.93#ibcon#about to write, iclass 14, count 2 2006.174.00:40:57.93#ibcon#wrote, iclass 14, count 2 2006.174.00:40:57.93#ibcon#about to read 3, iclass 14, count 2 2006.174.00:40:57.96#ibcon#read 3, iclass 14, count 2 2006.174.00:40:57.96#ibcon#about to read 4, iclass 14, count 2 2006.174.00:40:57.96#ibcon#read 4, iclass 14, count 2 2006.174.00:40:57.96#ibcon#about to read 5, iclass 14, count 2 2006.174.00:40:57.96#ibcon#read 5, iclass 14, count 2 2006.174.00:40:57.96#ibcon#about to read 6, iclass 14, count 2 2006.174.00:40:57.96#ibcon#read 6, iclass 14, count 2 2006.174.00:40:57.96#ibcon#end of sib2, iclass 14, count 2 2006.174.00:40:57.96#ibcon#*after write, iclass 14, count 2 2006.174.00:40:57.96#ibcon#*before return 0, iclass 14, count 2 2006.174.00:40:57.96#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.174.00:40:57.96#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.174.00:40:57.96#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.174.00:40:57.96#ibcon#ireg 7 cls_cnt 0 2006.174.00:40:57.96#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.174.00:40:58.08#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.174.00:40:58.08#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.174.00:40:58.08#ibcon#enter wrdev, iclass 14, count 0 2006.174.00:40:58.08#ibcon#first serial, iclass 14, count 0 2006.174.00:40:58.08#ibcon#enter sib2, iclass 14, count 0 2006.174.00:40:58.08#ibcon#flushed, iclass 14, count 0 2006.174.00:40:58.08#ibcon#about to write, iclass 14, count 0 2006.174.00:40:58.08#ibcon#wrote, iclass 14, count 0 2006.174.00:40:58.08#ibcon#about to read 3, iclass 14, count 0 2006.174.00:40:58.10#ibcon#read 3, iclass 14, count 0 2006.174.00:40:58.10#ibcon#about to read 4, iclass 14, count 0 2006.174.00:40:58.10#ibcon#read 4, iclass 14, count 0 2006.174.00:40:58.10#ibcon#about to read 5, iclass 14, count 0 2006.174.00:40:58.10#ibcon#read 5, iclass 14, count 0 2006.174.00:40:58.10#ibcon#about to read 6, iclass 14, count 0 2006.174.00:40:58.10#ibcon#read 6, iclass 14, count 0 2006.174.00:40:58.10#ibcon#end of sib2, iclass 14, count 0 2006.174.00:40:58.10#ibcon#*mode == 0, iclass 14, count 0 2006.174.00:40:58.10#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.174.00:40:58.10#ibcon#[25=USB\r\n] 2006.174.00:40:58.10#ibcon#*before write, iclass 14, count 0 2006.174.00:40:58.10#ibcon#enter sib2, iclass 14, count 0 2006.174.00:40:58.10#ibcon#flushed, iclass 14, count 0 2006.174.00:40:58.10#ibcon#about to write, iclass 14, count 0 2006.174.00:40:58.10#ibcon#wrote, iclass 14, count 0 2006.174.00:40:58.10#ibcon#about to read 3, iclass 14, count 0 2006.174.00:40:58.13#ibcon#read 3, iclass 14, count 0 2006.174.00:40:58.13#ibcon#about to read 4, iclass 14, count 0 2006.174.00:40:58.13#ibcon#read 4, iclass 14, count 0 2006.174.00:40:58.13#ibcon#about to read 5, iclass 14, count 0 2006.174.00:40:58.13#ibcon#read 5, iclass 14, count 0 2006.174.00:40:58.13#ibcon#about to read 6, iclass 14, count 0 2006.174.00:40:58.13#ibcon#read 6, iclass 14, count 0 2006.174.00:40:58.13#ibcon#end of sib2, iclass 14, count 0 2006.174.00:40:58.13#ibcon#*after write, iclass 14, count 0 2006.174.00:40:58.13#ibcon#*before return 0, iclass 14, count 0 2006.174.00:40:58.13#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.174.00:40:58.13#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.174.00:40:58.13#ibcon#about to clear, iclass 14 cls_cnt 0 2006.174.00:40:58.13#ibcon#cleared, iclass 14 cls_cnt 0 2006.174.00:40:58.13$vck44/valo=7,864.99 2006.174.00:40:58.13#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.174.00:40:58.13#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.174.00:40:58.13#ibcon#ireg 17 cls_cnt 0 2006.174.00:40:58.13#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.174.00:40:58.13#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.174.00:40:58.13#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.174.00:40:58.13#ibcon#enter wrdev, iclass 16, count 0 2006.174.00:40:58.13#ibcon#first serial, iclass 16, count 0 2006.174.00:40:58.13#ibcon#enter sib2, iclass 16, count 0 2006.174.00:40:58.13#ibcon#flushed, iclass 16, count 0 2006.174.00:40:58.13#ibcon#about to write, iclass 16, count 0 2006.174.00:40:58.13#ibcon#wrote, iclass 16, count 0 2006.174.00:40:58.13#ibcon#about to read 3, iclass 16, count 0 2006.174.00:40:58.15#ibcon#read 3, iclass 16, count 0 2006.174.00:40:58.15#ibcon#about to read 4, iclass 16, count 0 2006.174.00:40:58.15#ibcon#read 4, iclass 16, count 0 2006.174.00:40:58.15#ibcon#about to read 5, iclass 16, count 0 2006.174.00:40:58.15#ibcon#read 5, iclass 16, count 0 2006.174.00:40:58.15#ibcon#about to read 6, iclass 16, count 0 2006.174.00:40:58.15#ibcon#read 6, iclass 16, count 0 2006.174.00:40:58.15#ibcon#end of sib2, iclass 16, count 0 2006.174.00:40:58.15#ibcon#*mode == 0, iclass 16, count 0 2006.174.00:40:58.15#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.174.00:40:58.15#ibcon#[26=FRQ=07,864.99\r\n] 2006.174.00:40:58.15#ibcon#*before write, iclass 16, count 0 2006.174.00:40:58.15#ibcon#enter sib2, iclass 16, count 0 2006.174.00:40:58.15#ibcon#flushed, iclass 16, count 0 2006.174.00:40:58.15#ibcon#about to write, iclass 16, count 0 2006.174.00:40:58.15#ibcon#wrote, iclass 16, count 0 2006.174.00:40:58.15#ibcon#about to read 3, iclass 16, count 0 2006.174.00:40:58.19#ibcon#read 3, iclass 16, count 0 2006.174.00:40:58.19#ibcon#about to read 4, iclass 16, count 0 2006.174.00:40:58.19#ibcon#read 4, iclass 16, count 0 2006.174.00:40:58.19#ibcon#about to read 5, iclass 16, count 0 2006.174.00:40:58.19#ibcon#read 5, iclass 16, count 0 2006.174.00:40:58.19#ibcon#about to read 6, iclass 16, count 0 2006.174.00:40:58.19#ibcon#read 6, iclass 16, count 0 2006.174.00:40:58.19#ibcon#end of sib2, iclass 16, count 0 2006.174.00:40:58.19#ibcon#*after write, iclass 16, count 0 2006.174.00:40:58.19#ibcon#*before return 0, iclass 16, count 0 2006.174.00:40:58.19#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.174.00:40:58.19#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.174.00:40:58.19#ibcon#about to clear, iclass 16 cls_cnt 0 2006.174.00:40:58.19#ibcon#cleared, iclass 16 cls_cnt 0 2006.174.00:40:58.19$vck44/va=7,4 2006.174.00:40:58.19#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.174.00:40:58.19#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.174.00:40:58.19#ibcon#ireg 11 cls_cnt 2 2006.174.00:40:58.19#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.174.00:40:58.25#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.174.00:40:58.25#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.174.00:40:58.25#ibcon#enter wrdev, iclass 18, count 2 2006.174.00:40:58.25#ibcon#first serial, iclass 18, count 2 2006.174.00:40:58.25#ibcon#enter sib2, iclass 18, count 2 2006.174.00:40:58.25#ibcon#flushed, iclass 18, count 2 2006.174.00:40:58.25#ibcon#about to write, iclass 18, count 2 2006.174.00:40:58.25#ibcon#wrote, iclass 18, count 2 2006.174.00:40:58.25#ibcon#about to read 3, iclass 18, count 2 2006.174.00:40:58.27#ibcon#read 3, iclass 18, count 2 2006.174.00:40:58.27#ibcon#about to read 4, iclass 18, count 2 2006.174.00:40:58.27#ibcon#read 4, iclass 18, count 2 2006.174.00:40:58.27#ibcon#about to read 5, iclass 18, count 2 2006.174.00:40:58.27#ibcon#read 5, iclass 18, count 2 2006.174.00:40:58.27#ibcon#about to read 6, iclass 18, count 2 2006.174.00:40:58.27#ibcon#read 6, iclass 18, count 2 2006.174.00:40:58.27#ibcon#end of sib2, iclass 18, count 2 2006.174.00:40:58.27#ibcon#*mode == 0, iclass 18, count 2 2006.174.00:40:58.27#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.174.00:40:58.27#ibcon#[25=AT07-04\r\n] 2006.174.00:40:58.27#ibcon#*before write, iclass 18, count 2 2006.174.00:40:58.27#ibcon#enter sib2, iclass 18, count 2 2006.174.00:40:58.27#ibcon#flushed, iclass 18, count 2 2006.174.00:40:58.27#ibcon#about to write, iclass 18, count 2 2006.174.00:40:58.27#ibcon#wrote, iclass 18, count 2 2006.174.00:40:58.27#ibcon#about to read 3, iclass 18, count 2 2006.174.00:40:58.30#ibcon#read 3, iclass 18, count 2 2006.174.00:40:58.30#ibcon#about to read 4, iclass 18, count 2 2006.174.00:40:58.30#ibcon#read 4, iclass 18, count 2 2006.174.00:40:58.30#ibcon#about to read 5, iclass 18, count 2 2006.174.00:40:58.30#ibcon#read 5, iclass 18, count 2 2006.174.00:40:58.30#ibcon#about to read 6, iclass 18, count 2 2006.174.00:40:58.30#ibcon#read 6, iclass 18, count 2 2006.174.00:40:58.30#ibcon#end of sib2, iclass 18, count 2 2006.174.00:40:58.30#ibcon#*after write, iclass 18, count 2 2006.174.00:40:58.30#ibcon#*before return 0, iclass 18, count 2 2006.174.00:40:58.30#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.174.00:40:58.30#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.174.00:40:58.30#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.174.00:40:58.30#ibcon#ireg 7 cls_cnt 0 2006.174.00:40:58.30#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.174.00:40:58.42#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.174.00:40:58.42#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.174.00:40:58.42#ibcon#enter wrdev, iclass 18, count 0 2006.174.00:40:58.42#ibcon#first serial, iclass 18, count 0 2006.174.00:40:58.42#ibcon#enter sib2, iclass 18, count 0 2006.174.00:40:58.42#ibcon#flushed, iclass 18, count 0 2006.174.00:40:58.42#ibcon#about to write, iclass 18, count 0 2006.174.00:40:58.42#ibcon#wrote, iclass 18, count 0 2006.174.00:40:58.42#ibcon#about to read 3, iclass 18, count 0 2006.174.00:40:58.44#ibcon#read 3, iclass 18, count 0 2006.174.00:40:58.44#ibcon#about to read 4, iclass 18, count 0 2006.174.00:40:58.44#ibcon#read 4, iclass 18, count 0 2006.174.00:40:58.44#ibcon#about to read 5, iclass 18, count 0 2006.174.00:40:58.44#ibcon#read 5, iclass 18, count 0 2006.174.00:40:58.44#ibcon#about to read 6, iclass 18, count 0 2006.174.00:40:58.44#ibcon#read 6, iclass 18, count 0 2006.174.00:40:58.44#ibcon#end of sib2, iclass 18, count 0 2006.174.00:40:58.44#ibcon#*mode == 0, iclass 18, count 0 2006.174.00:40:58.44#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.174.00:40:58.44#ibcon#[25=USB\r\n] 2006.174.00:40:58.44#ibcon#*before write, iclass 18, count 0 2006.174.00:40:58.44#ibcon#enter sib2, iclass 18, count 0 2006.174.00:40:58.44#ibcon#flushed, iclass 18, count 0 2006.174.00:40:58.44#ibcon#about to write, iclass 18, count 0 2006.174.00:40:58.44#ibcon#wrote, iclass 18, count 0 2006.174.00:40:58.44#ibcon#about to read 3, iclass 18, count 0 2006.174.00:40:58.47#ibcon#read 3, iclass 18, count 0 2006.174.00:40:58.47#ibcon#about to read 4, iclass 18, count 0 2006.174.00:40:58.47#ibcon#read 4, iclass 18, count 0 2006.174.00:40:58.47#ibcon#about to read 5, iclass 18, count 0 2006.174.00:40:58.47#ibcon#read 5, iclass 18, count 0 2006.174.00:40:58.47#ibcon#about to read 6, iclass 18, count 0 2006.174.00:40:58.47#ibcon#read 6, iclass 18, count 0 2006.174.00:40:58.47#ibcon#end of sib2, iclass 18, count 0 2006.174.00:40:58.47#ibcon#*after write, iclass 18, count 0 2006.174.00:40:58.47#ibcon#*before return 0, iclass 18, count 0 2006.174.00:40:58.47#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.174.00:40:58.47#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.174.00:40:58.47#ibcon#about to clear, iclass 18 cls_cnt 0 2006.174.00:40:58.47#ibcon#cleared, iclass 18 cls_cnt 0 2006.174.00:40:58.47$vck44/valo=8,884.99 2006.174.00:40:58.47#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.174.00:40:58.47#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.174.00:40:58.47#ibcon#ireg 17 cls_cnt 0 2006.174.00:40:58.47#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.174.00:40:58.47#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.174.00:40:58.47#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.174.00:40:58.47#ibcon#enter wrdev, iclass 20, count 0 2006.174.00:40:58.47#ibcon#first serial, iclass 20, count 0 2006.174.00:40:58.47#ibcon#enter sib2, iclass 20, count 0 2006.174.00:40:58.47#ibcon#flushed, iclass 20, count 0 2006.174.00:40:58.47#ibcon#about to write, iclass 20, count 0 2006.174.00:40:58.47#ibcon#wrote, iclass 20, count 0 2006.174.00:40:58.47#ibcon#about to read 3, iclass 20, count 0 2006.174.00:40:58.49#ibcon#read 3, iclass 20, count 0 2006.174.00:40:58.49#ibcon#about to read 4, iclass 20, count 0 2006.174.00:40:58.49#ibcon#read 4, iclass 20, count 0 2006.174.00:40:58.49#ibcon#about to read 5, iclass 20, count 0 2006.174.00:40:58.49#ibcon#read 5, iclass 20, count 0 2006.174.00:40:58.49#ibcon#about to read 6, iclass 20, count 0 2006.174.00:40:58.49#ibcon#read 6, iclass 20, count 0 2006.174.00:40:58.49#ibcon#end of sib2, iclass 20, count 0 2006.174.00:40:58.49#ibcon#*mode == 0, iclass 20, count 0 2006.174.00:40:58.49#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.174.00:40:58.49#ibcon#[26=FRQ=08,884.99\r\n] 2006.174.00:40:58.49#ibcon#*before write, iclass 20, count 0 2006.174.00:40:58.49#ibcon#enter sib2, iclass 20, count 0 2006.174.00:40:58.49#ibcon#flushed, iclass 20, count 0 2006.174.00:40:58.49#ibcon#about to write, iclass 20, count 0 2006.174.00:40:58.49#ibcon#wrote, iclass 20, count 0 2006.174.00:40:58.49#ibcon#about to read 3, iclass 20, count 0 2006.174.00:40:58.53#ibcon#read 3, iclass 20, count 0 2006.174.00:40:58.53#ibcon#about to read 4, iclass 20, count 0 2006.174.00:40:58.53#ibcon#read 4, iclass 20, count 0 2006.174.00:40:58.53#ibcon#about to read 5, iclass 20, count 0 2006.174.00:40:58.53#ibcon#read 5, iclass 20, count 0 2006.174.00:40:58.53#ibcon#about to read 6, iclass 20, count 0 2006.174.00:40:58.53#ibcon#read 6, iclass 20, count 0 2006.174.00:40:58.53#ibcon#end of sib2, iclass 20, count 0 2006.174.00:40:58.53#ibcon#*after write, iclass 20, count 0 2006.174.00:40:58.53#ibcon#*before return 0, iclass 20, count 0 2006.174.00:40:58.53#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.174.00:40:58.53#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.174.00:40:58.53#ibcon#about to clear, iclass 20 cls_cnt 0 2006.174.00:40:58.53#ibcon#cleared, iclass 20 cls_cnt 0 2006.174.00:40:58.53$vck44/va=8,4 2006.174.00:40:58.53#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.174.00:40:58.53#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.174.00:40:58.53#ibcon#ireg 11 cls_cnt 2 2006.174.00:40:58.53#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.174.00:40:58.59#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.174.00:40:58.59#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.174.00:40:58.59#ibcon#enter wrdev, iclass 22, count 2 2006.174.00:40:58.59#ibcon#first serial, iclass 22, count 2 2006.174.00:40:58.59#ibcon#enter sib2, iclass 22, count 2 2006.174.00:40:58.59#ibcon#flushed, iclass 22, count 2 2006.174.00:40:58.59#ibcon#about to write, iclass 22, count 2 2006.174.00:40:58.59#ibcon#wrote, iclass 22, count 2 2006.174.00:40:58.59#ibcon#about to read 3, iclass 22, count 2 2006.174.00:40:58.61#ibcon#read 3, iclass 22, count 2 2006.174.00:40:58.61#ibcon#about to read 4, iclass 22, count 2 2006.174.00:40:58.61#ibcon#read 4, iclass 22, count 2 2006.174.00:40:58.61#ibcon#about to read 5, iclass 22, count 2 2006.174.00:40:58.61#ibcon#read 5, iclass 22, count 2 2006.174.00:40:58.61#ibcon#about to read 6, iclass 22, count 2 2006.174.00:40:58.61#ibcon#read 6, iclass 22, count 2 2006.174.00:40:58.61#ibcon#end of sib2, iclass 22, count 2 2006.174.00:40:58.61#ibcon#*mode == 0, iclass 22, count 2 2006.174.00:40:58.61#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.174.00:40:58.61#ibcon#[25=AT08-04\r\n] 2006.174.00:40:58.61#ibcon#*before write, iclass 22, count 2 2006.174.00:40:58.61#ibcon#enter sib2, iclass 22, count 2 2006.174.00:40:58.61#ibcon#flushed, iclass 22, count 2 2006.174.00:40:58.61#ibcon#about to write, iclass 22, count 2 2006.174.00:40:58.61#ibcon#wrote, iclass 22, count 2 2006.174.00:40:58.61#ibcon#about to read 3, iclass 22, count 2 2006.174.00:40:58.64#ibcon#read 3, iclass 22, count 2 2006.174.00:40:58.64#ibcon#about to read 4, iclass 22, count 2 2006.174.00:40:58.64#ibcon#read 4, iclass 22, count 2 2006.174.00:40:58.64#ibcon#about to read 5, iclass 22, count 2 2006.174.00:40:58.64#ibcon#read 5, iclass 22, count 2 2006.174.00:40:58.64#ibcon#about to read 6, iclass 22, count 2 2006.174.00:40:58.64#ibcon#read 6, iclass 22, count 2 2006.174.00:40:58.64#ibcon#end of sib2, iclass 22, count 2 2006.174.00:40:58.64#ibcon#*after write, iclass 22, count 2 2006.174.00:40:58.64#ibcon#*before return 0, iclass 22, count 2 2006.174.00:40:58.64#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.174.00:40:58.64#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.174.00:40:58.64#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.174.00:40:58.64#ibcon#ireg 7 cls_cnt 0 2006.174.00:40:58.64#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.174.00:40:58.76#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.174.00:40:58.76#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.174.00:40:58.76#ibcon#enter wrdev, iclass 22, count 0 2006.174.00:40:58.76#ibcon#first serial, iclass 22, count 0 2006.174.00:40:58.76#ibcon#enter sib2, iclass 22, count 0 2006.174.00:40:58.76#ibcon#flushed, iclass 22, count 0 2006.174.00:40:58.76#ibcon#about to write, iclass 22, count 0 2006.174.00:40:58.76#ibcon#wrote, iclass 22, count 0 2006.174.00:40:58.76#ibcon#about to read 3, iclass 22, count 0 2006.174.00:40:58.78#ibcon#read 3, iclass 22, count 0 2006.174.00:40:58.78#ibcon#about to read 4, iclass 22, count 0 2006.174.00:40:58.78#ibcon#read 4, iclass 22, count 0 2006.174.00:40:58.78#ibcon#about to read 5, iclass 22, count 0 2006.174.00:40:58.78#ibcon#read 5, iclass 22, count 0 2006.174.00:40:58.78#ibcon#about to read 6, iclass 22, count 0 2006.174.00:40:58.78#ibcon#read 6, iclass 22, count 0 2006.174.00:40:58.78#ibcon#end of sib2, iclass 22, count 0 2006.174.00:40:58.78#ibcon#*mode == 0, iclass 22, count 0 2006.174.00:40:58.78#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.174.00:40:58.78#ibcon#[25=USB\r\n] 2006.174.00:40:58.78#ibcon#*before write, iclass 22, count 0 2006.174.00:40:58.78#ibcon#enter sib2, iclass 22, count 0 2006.174.00:40:58.78#ibcon#flushed, iclass 22, count 0 2006.174.00:40:58.78#ibcon#about to write, iclass 22, count 0 2006.174.00:40:58.78#ibcon#wrote, iclass 22, count 0 2006.174.00:40:58.78#ibcon#about to read 3, iclass 22, count 0 2006.174.00:40:58.81#ibcon#read 3, iclass 22, count 0 2006.174.00:40:58.81#ibcon#about to read 4, iclass 22, count 0 2006.174.00:40:58.81#ibcon#read 4, iclass 22, count 0 2006.174.00:40:58.81#ibcon#about to read 5, iclass 22, count 0 2006.174.00:40:58.81#ibcon#read 5, iclass 22, count 0 2006.174.00:40:58.81#ibcon#about to read 6, iclass 22, count 0 2006.174.00:40:58.81#ibcon#read 6, iclass 22, count 0 2006.174.00:40:58.81#ibcon#end of sib2, iclass 22, count 0 2006.174.00:40:58.81#ibcon#*after write, iclass 22, count 0 2006.174.00:40:58.81#ibcon#*before return 0, iclass 22, count 0 2006.174.00:40:58.81#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.174.00:40:58.81#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.174.00:40:58.81#ibcon#about to clear, iclass 22 cls_cnt 0 2006.174.00:40:58.81#ibcon#cleared, iclass 22 cls_cnt 0 2006.174.00:40:58.81$vck44/vblo=1,629.99 2006.174.00:40:58.81#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.174.00:40:58.81#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.174.00:40:58.81#ibcon#ireg 17 cls_cnt 0 2006.174.00:40:58.81#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.174.00:40:58.81#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.174.00:40:58.81#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.174.00:40:58.81#ibcon#enter wrdev, iclass 24, count 0 2006.174.00:40:58.81#ibcon#first serial, iclass 24, count 0 2006.174.00:40:58.81#ibcon#enter sib2, iclass 24, count 0 2006.174.00:40:58.81#ibcon#flushed, iclass 24, count 0 2006.174.00:40:58.81#ibcon#about to write, iclass 24, count 0 2006.174.00:40:58.81#ibcon#wrote, iclass 24, count 0 2006.174.00:40:58.81#ibcon#about to read 3, iclass 24, count 0 2006.174.00:40:58.83#ibcon#read 3, iclass 24, count 0 2006.174.00:40:58.83#ibcon#about to read 4, iclass 24, count 0 2006.174.00:40:58.83#ibcon#read 4, iclass 24, count 0 2006.174.00:40:58.83#ibcon#about to read 5, iclass 24, count 0 2006.174.00:40:58.83#ibcon#read 5, iclass 24, count 0 2006.174.00:40:58.83#ibcon#about to read 6, iclass 24, count 0 2006.174.00:40:58.83#ibcon#read 6, iclass 24, count 0 2006.174.00:40:58.83#ibcon#end of sib2, iclass 24, count 0 2006.174.00:40:58.83#ibcon#*mode == 0, iclass 24, count 0 2006.174.00:40:58.83#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.174.00:40:58.83#ibcon#[28=FRQ=01,629.99\r\n] 2006.174.00:40:58.83#ibcon#*before write, iclass 24, count 0 2006.174.00:40:58.83#ibcon#enter sib2, iclass 24, count 0 2006.174.00:40:58.83#ibcon#flushed, iclass 24, count 0 2006.174.00:40:58.83#ibcon#about to write, iclass 24, count 0 2006.174.00:40:58.83#ibcon#wrote, iclass 24, count 0 2006.174.00:40:58.83#ibcon#about to read 3, iclass 24, count 0 2006.174.00:40:58.87#ibcon#read 3, iclass 24, count 0 2006.174.00:40:58.87#ibcon#about to read 4, iclass 24, count 0 2006.174.00:40:58.87#ibcon#read 4, iclass 24, count 0 2006.174.00:40:58.87#ibcon#about to read 5, iclass 24, count 0 2006.174.00:40:58.87#ibcon#read 5, iclass 24, count 0 2006.174.00:40:58.87#ibcon#about to read 6, iclass 24, count 0 2006.174.00:40:58.87#ibcon#read 6, iclass 24, count 0 2006.174.00:40:58.87#ibcon#end of sib2, iclass 24, count 0 2006.174.00:40:58.87#ibcon#*after write, iclass 24, count 0 2006.174.00:40:58.87#ibcon#*before return 0, iclass 24, count 0 2006.174.00:40:58.87#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.174.00:40:58.87#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.174.00:40:58.87#ibcon#about to clear, iclass 24 cls_cnt 0 2006.174.00:40:58.87#ibcon#cleared, iclass 24 cls_cnt 0 2006.174.00:40:58.87$vck44/vb=1,4 2006.174.00:40:58.87#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.174.00:40:58.87#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.174.00:40:58.87#ibcon#ireg 11 cls_cnt 2 2006.174.00:40:58.87#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.174.00:40:58.87#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.174.00:40:58.87#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.174.00:40:58.87#ibcon#enter wrdev, iclass 26, count 2 2006.174.00:40:58.87#ibcon#first serial, iclass 26, count 2 2006.174.00:40:58.87#ibcon#enter sib2, iclass 26, count 2 2006.174.00:40:58.87#ibcon#flushed, iclass 26, count 2 2006.174.00:40:58.87#ibcon#about to write, iclass 26, count 2 2006.174.00:40:58.87#ibcon#wrote, iclass 26, count 2 2006.174.00:40:58.87#ibcon#about to read 3, iclass 26, count 2 2006.174.00:40:58.89#ibcon#read 3, iclass 26, count 2 2006.174.00:40:58.89#ibcon#about to read 4, iclass 26, count 2 2006.174.00:40:58.89#ibcon#read 4, iclass 26, count 2 2006.174.00:40:58.89#ibcon#about to read 5, iclass 26, count 2 2006.174.00:40:58.89#ibcon#read 5, iclass 26, count 2 2006.174.00:40:58.89#ibcon#about to read 6, iclass 26, count 2 2006.174.00:40:58.89#ibcon#read 6, iclass 26, count 2 2006.174.00:40:58.89#ibcon#end of sib2, iclass 26, count 2 2006.174.00:40:58.89#ibcon#*mode == 0, iclass 26, count 2 2006.174.00:40:58.89#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.174.00:40:58.89#ibcon#[27=AT01-04\r\n] 2006.174.00:40:58.89#ibcon#*before write, iclass 26, count 2 2006.174.00:40:58.89#ibcon#enter sib2, iclass 26, count 2 2006.174.00:40:58.89#ibcon#flushed, iclass 26, count 2 2006.174.00:40:58.89#ibcon#about to write, iclass 26, count 2 2006.174.00:40:58.89#ibcon#wrote, iclass 26, count 2 2006.174.00:40:58.89#ibcon#about to read 3, iclass 26, count 2 2006.174.00:40:58.92#ibcon#read 3, iclass 26, count 2 2006.174.00:40:58.92#ibcon#about to read 4, iclass 26, count 2 2006.174.00:40:58.92#ibcon#read 4, iclass 26, count 2 2006.174.00:40:58.92#ibcon#about to read 5, iclass 26, count 2 2006.174.00:40:58.92#ibcon#read 5, iclass 26, count 2 2006.174.00:40:58.92#ibcon#about to read 6, iclass 26, count 2 2006.174.00:40:58.92#ibcon#read 6, iclass 26, count 2 2006.174.00:40:58.92#ibcon#end of sib2, iclass 26, count 2 2006.174.00:40:58.92#ibcon#*after write, iclass 26, count 2 2006.174.00:40:58.92#ibcon#*before return 0, iclass 26, count 2 2006.174.00:40:58.92#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.174.00:40:58.92#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.174.00:40:58.92#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.174.00:40:58.92#ibcon#ireg 7 cls_cnt 0 2006.174.00:40:58.92#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.174.00:40:59.04#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.174.00:40:59.04#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.174.00:40:59.04#ibcon#enter wrdev, iclass 26, count 0 2006.174.00:40:59.04#ibcon#first serial, iclass 26, count 0 2006.174.00:40:59.04#ibcon#enter sib2, iclass 26, count 0 2006.174.00:40:59.04#ibcon#flushed, iclass 26, count 0 2006.174.00:40:59.04#ibcon#about to write, iclass 26, count 0 2006.174.00:40:59.04#ibcon#wrote, iclass 26, count 0 2006.174.00:40:59.04#ibcon#about to read 3, iclass 26, count 0 2006.174.00:40:59.06#ibcon#read 3, iclass 26, count 0 2006.174.00:40:59.06#ibcon#about to read 4, iclass 26, count 0 2006.174.00:40:59.06#ibcon#read 4, iclass 26, count 0 2006.174.00:40:59.06#ibcon#about to read 5, iclass 26, count 0 2006.174.00:40:59.06#ibcon#read 5, iclass 26, count 0 2006.174.00:40:59.06#ibcon#about to read 6, iclass 26, count 0 2006.174.00:40:59.06#ibcon#read 6, iclass 26, count 0 2006.174.00:40:59.06#ibcon#end of sib2, iclass 26, count 0 2006.174.00:40:59.06#ibcon#*mode == 0, iclass 26, count 0 2006.174.00:40:59.06#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.174.00:40:59.06#ibcon#[27=USB\r\n] 2006.174.00:40:59.06#ibcon#*before write, iclass 26, count 0 2006.174.00:40:59.06#ibcon#enter sib2, iclass 26, count 0 2006.174.00:40:59.06#ibcon#flushed, iclass 26, count 0 2006.174.00:40:59.06#ibcon#about to write, iclass 26, count 0 2006.174.00:40:59.06#ibcon#wrote, iclass 26, count 0 2006.174.00:40:59.06#ibcon#about to read 3, iclass 26, count 0 2006.174.00:40:59.09#ibcon#read 3, iclass 26, count 0 2006.174.00:40:59.09#ibcon#about to read 4, iclass 26, count 0 2006.174.00:40:59.09#ibcon#read 4, iclass 26, count 0 2006.174.00:40:59.09#ibcon#about to read 5, iclass 26, count 0 2006.174.00:40:59.09#ibcon#read 5, iclass 26, count 0 2006.174.00:40:59.09#ibcon#about to read 6, iclass 26, count 0 2006.174.00:40:59.09#ibcon#read 6, iclass 26, count 0 2006.174.00:40:59.09#ibcon#end of sib2, iclass 26, count 0 2006.174.00:40:59.09#ibcon#*after write, iclass 26, count 0 2006.174.00:40:59.09#ibcon#*before return 0, iclass 26, count 0 2006.174.00:40:59.09#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.174.00:40:59.09#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.174.00:40:59.09#ibcon#about to clear, iclass 26 cls_cnt 0 2006.174.00:40:59.09#ibcon#cleared, iclass 26 cls_cnt 0 2006.174.00:40:59.09$vck44/vblo=2,634.99 2006.174.00:40:59.09#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.174.00:40:59.09#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.174.00:40:59.09#ibcon#ireg 17 cls_cnt 0 2006.174.00:40:59.09#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.174.00:40:59.09#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.174.00:40:59.09#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.174.00:40:59.09#ibcon#enter wrdev, iclass 28, count 0 2006.174.00:40:59.09#ibcon#first serial, iclass 28, count 0 2006.174.00:40:59.09#ibcon#enter sib2, iclass 28, count 0 2006.174.00:40:59.09#ibcon#flushed, iclass 28, count 0 2006.174.00:40:59.09#ibcon#about to write, iclass 28, count 0 2006.174.00:40:59.09#ibcon#wrote, iclass 28, count 0 2006.174.00:40:59.09#ibcon#about to read 3, iclass 28, count 0 2006.174.00:40:59.11#ibcon#read 3, iclass 28, count 0 2006.174.00:40:59.11#ibcon#about to read 4, iclass 28, count 0 2006.174.00:40:59.11#ibcon#read 4, iclass 28, count 0 2006.174.00:40:59.11#ibcon#about to read 5, iclass 28, count 0 2006.174.00:40:59.11#ibcon#read 5, iclass 28, count 0 2006.174.00:40:59.11#ibcon#about to read 6, iclass 28, count 0 2006.174.00:40:59.11#ibcon#read 6, iclass 28, count 0 2006.174.00:40:59.11#ibcon#end of sib2, iclass 28, count 0 2006.174.00:40:59.11#ibcon#*mode == 0, iclass 28, count 0 2006.174.00:40:59.11#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.174.00:40:59.11#ibcon#[28=FRQ=02,634.99\r\n] 2006.174.00:40:59.11#ibcon#*before write, iclass 28, count 0 2006.174.00:40:59.11#ibcon#enter sib2, iclass 28, count 0 2006.174.00:40:59.11#ibcon#flushed, iclass 28, count 0 2006.174.00:40:59.11#ibcon#about to write, iclass 28, count 0 2006.174.00:40:59.11#ibcon#wrote, iclass 28, count 0 2006.174.00:40:59.11#ibcon#about to read 3, iclass 28, count 0 2006.174.00:40:59.15#ibcon#read 3, iclass 28, count 0 2006.174.00:40:59.15#ibcon#about to read 4, iclass 28, count 0 2006.174.00:40:59.15#ibcon#read 4, iclass 28, count 0 2006.174.00:40:59.15#ibcon#about to read 5, iclass 28, count 0 2006.174.00:40:59.15#ibcon#read 5, iclass 28, count 0 2006.174.00:40:59.15#ibcon#about to read 6, iclass 28, count 0 2006.174.00:40:59.15#ibcon#read 6, iclass 28, count 0 2006.174.00:40:59.15#ibcon#end of sib2, iclass 28, count 0 2006.174.00:40:59.15#ibcon#*after write, iclass 28, count 0 2006.174.00:40:59.15#ibcon#*before return 0, iclass 28, count 0 2006.174.00:40:59.15#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.174.00:40:59.15#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.174.00:40:59.15#ibcon#about to clear, iclass 28 cls_cnt 0 2006.174.00:40:59.15#ibcon#cleared, iclass 28 cls_cnt 0 2006.174.00:40:59.15$vck44/vb=2,4 2006.174.00:40:59.15#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.174.00:40:59.15#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.174.00:40:59.15#ibcon#ireg 11 cls_cnt 2 2006.174.00:40:59.15#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.174.00:40:59.21#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.174.00:40:59.21#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.174.00:40:59.21#ibcon#enter wrdev, iclass 30, count 2 2006.174.00:40:59.21#ibcon#first serial, iclass 30, count 2 2006.174.00:40:59.21#ibcon#enter sib2, iclass 30, count 2 2006.174.00:40:59.21#ibcon#flushed, iclass 30, count 2 2006.174.00:40:59.21#ibcon#about to write, iclass 30, count 2 2006.174.00:40:59.21#ibcon#wrote, iclass 30, count 2 2006.174.00:40:59.21#ibcon#about to read 3, iclass 30, count 2 2006.174.00:40:59.23#ibcon#read 3, iclass 30, count 2 2006.174.00:40:59.23#ibcon#about to read 4, iclass 30, count 2 2006.174.00:40:59.23#ibcon#read 4, iclass 30, count 2 2006.174.00:40:59.23#ibcon#about to read 5, iclass 30, count 2 2006.174.00:40:59.23#ibcon#read 5, iclass 30, count 2 2006.174.00:40:59.23#ibcon#about to read 6, iclass 30, count 2 2006.174.00:40:59.23#ibcon#read 6, iclass 30, count 2 2006.174.00:40:59.23#ibcon#end of sib2, iclass 30, count 2 2006.174.00:40:59.23#ibcon#*mode == 0, iclass 30, count 2 2006.174.00:40:59.23#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.174.00:40:59.23#ibcon#[27=AT02-04\r\n] 2006.174.00:40:59.23#ibcon#*before write, iclass 30, count 2 2006.174.00:40:59.23#ibcon#enter sib2, iclass 30, count 2 2006.174.00:40:59.23#ibcon#flushed, iclass 30, count 2 2006.174.00:40:59.23#ibcon#about to write, iclass 30, count 2 2006.174.00:40:59.23#ibcon#wrote, iclass 30, count 2 2006.174.00:40:59.23#ibcon#about to read 3, iclass 30, count 2 2006.174.00:40:59.26#ibcon#read 3, iclass 30, count 2 2006.174.00:40:59.26#ibcon#about to read 4, iclass 30, count 2 2006.174.00:40:59.26#ibcon#read 4, iclass 30, count 2 2006.174.00:40:59.26#ibcon#about to read 5, iclass 30, count 2 2006.174.00:40:59.26#ibcon#read 5, iclass 30, count 2 2006.174.00:40:59.26#ibcon#about to read 6, iclass 30, count 2 2006.174.00:40:59.26#ibcon#read 6, iclass 30, count 2 2006.174.00:40:59.26#ibcon#end of sib2, iclass 30, count 2 2006.174.00:40:59.26#ibcon#*after write, iclass 30, count 2 2006.174.00:40:59.26#ibcon#*before return 0, iclass 30, count 2 2006.174.00:40:59.26#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.174.00:40:59.26#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.174.00:40:59.26#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.174.00:40:59.26#ibcon#ireg 7 cls_cnt 0 2006.174.00:40:59.26#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.174.00:40:59.38#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.174.00:40:59.38#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.174.00:40:59.38#ibcon#enter wrdev, iclass 30, count 0 2006.174.00:40:59.38#ibcon#first serial, iclass 30, count 0 2006.174.00:40:59.38#ibcon#enter sib2, iclass 30, count 0 2006.174.00:40:59.38#ibcon#flushed, iclass 30, count 0 2006.174.00:40:59.38#ibcon#about to write, iclass 30, count 0 2006.174.00:40:59.38#ibcon#wrote, iclass 30, count 0 2006.174.00:40:59.38#ibcon#about to read 3, iclass 30, count 0 2006.174.00:40:59.40#ibcon#read 3, iclass 30, count 0 2006.174.00:40:59.40#ibcon#about to read 4, iclass 30, count 0 2006.174.00:40:59.40#ibcon#read 4, iclass 30, count 0 2006.174.00:40:59.40#ibcon#about to read 5, iclass 30, count 0 2006.174.00:40:59.40#ibcon#read 5, iclass 30, count 0 2006.174.00:40:59.40#ibcon#about to read 6, iclass 30, count 0 2006.174.00:40:59.40#ibcon#read 6, iclass 30, count 0 2006.174.00:40:59.40#ibcon#end of sib2, iclass 30, count 0 2006.174.00:40:59.40#ibcon#*mode == 0, iclass 30, count 0 2006.174.00:40:59.40#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.174.00:40:59.40#ibcon#[27=USB\r\n] 2006.174.00:40:59.40#ibcon#*before write, iclass 30, count 0 2006.174.00:40:59.40#ibcon#enter sib2, iclass 30, count 0 2006.174.00:40:59.40#ibcon#flushed, iclass 30, count 0 2006.174.00:40:59.40#ibcon#about to write, iclass 30, count 0 2006.174.00:40:59.40#ibcon#wrote, iclass 30, count 0 2006.174.00:40:59.40#ibcon#about to read 3, iclass 30, count 0 2006.174.00:40:59.43#ibcon#read 3, iclass 30, count 0 2006.174.00:40:59.43#ibcon#about to read 4, iclass 30, count 0 2006.174.00:40:59.43#ibcon#read 4, iclass 30, count 0 2006.174.00:40:59.43#ibcon#about to read 5, iclass 30, count 0 2006.174.00:40:59.43#ibcon#read 5, iclass 30, count 0 2006.174.00:40:59.43#ibcon#about to read 6, iclass 30, count 0 2006.174.00:40:59.43#ibcon#read 6, iclass 30, count 0 2006.174.00:40:59.43#ibcon#end of sib2, iclass 30, count 0 2006.174.00:40:59.43#ibcon#*after write, iclass 30, count 0 2006.174.00:40:59.43#ibcon#*before return 0, iclass 30, count 0 2006.174.00:40:59.43#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.174.00:40:59.43#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.174.00:40:59.43#ibcon#about to clear, iclass 30 cls_cnt 0 2006.174.00:40:59.43#ibcon#cleared, iclass 30 cls_cnt 0 2006.174.00:40:59.43$vck44/vblo=3,649.99 2006.174.00:40:59.43#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.174.00:40:59.43#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.174.00:40:59.43#ibcon#ireg 17 cls_cnt 0 2006.174.00:40:59.43#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.174.00:40:59.43#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.174.00:40:59.43#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.174.00:40:59.43#ibcon#enter wrdev, iclass 32, count 0 2006.174.00:40:59.43#ibcon#first serial, iclass 32, count 0 2006.174.00:40:59.43#ibcon#enter sib2, iclass 32, count 0 2006.174.00:40:59.43#ibcon#flushed, iclass 32, count 0 2006.174.00:40:59.43#ibcon#about to write, iclass 32, count 0 2006.174.00:40:59.43#ibcon#wrote, iclass 32, count 0 2006.174.00:40:59.43#ibcon#about to read 3, iclass 32, count 0 2006.174.00:40:59.45#ibcon#read 3, iclass 32, count 0 2006.174.00:40:59.45#ibcon#about to read 4, iclass 32, count 0 2006.174.00:40:59.45#ibcon#read 4, iclass 32, count 0 2006.174.00:40:59.45#ibcon#about to read 5, iclass 32, count 0 2006.174.00:40:59.45#ibcon#read 5, iclass 32, count 0 2006.174.00:40:59.45#ibcon#about to read 6, iclass 32, count 0 2006.174.00:40:59.45#ibcon#read 6, iclass 32, count 0 2006.174.00:40:59.45#ibcon#end of sib2, iclass 32, count 0 2006.174.00:40:59.45#ibcon#*mode == 0, iclass 32, count 0 2006.174.00:40:59.45#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.174.00:40:59.45#ibcon#[28=FRQ=03,649.99\r\n] 2006.174.00:40:59.45#ibcon#*before write, iclass 32, count 0 2006.174.00:40:59.45#ibcon#enter sib2, iclass 32, count 0 2006.174.00:40:59.45#ibcon#flushed, iclass 32, count 0 2006.174.00:40:59.45#ibcon#about to write, iclass 32, count 0 2006.174.00:40:59.45#ibcon#wrote, iclass 32, count 0 2006.174.00:40:59.45#ibcon#about to read 3, iclass 32, count 0 2006.174.00:40:59.49#ibcon#read 3, iclass 32, count 0 2006.174.00:40:59.49#ibcon#about to read 4, iclass 32, count 0 2006.174.00:40:59.49#ibcon#read 4, iclass 32, count 0 2006.174.00:40:59.49#ibcon#about to read 5, iclass 32, count 0 2006.174.00:40:59.49#ibcon#read 5, iclass 32, count 0 2006.174.00:40:59.49#ibcon#about to read 6, iclass 32, count 0 2006.174.00:40:59.49#ibcon#read 6, iclass 32, count 0 2006.174.00:40:59.49#ibcon#end of sib2, iclass 32, count 0 2006.174.00:40:59.49#ibcon#*after write, iclass 32, count 0 2006.174.00:40:59.49#ibcon#*before return 0, iclass 32, count 0 2006.174.00:40:59.49#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.174.00:40:59.49#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.174.00:40:59.49#ibcon#about to clear, iclass 32 cls_cnt 0 2006.174.00:40:59.49#ibcon#cleared, iclass 32 cls_cnt 0 2006.174.00:40:59.49$vck44/vb=3,4 2006.174.00:40:59.49#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.174.00:40:59.49#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.174.00:40:59.49#ibcon#ireg 11 cls_cnt 2 2006.174.00:40:59.49#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.174.00:40:59.55#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.174.00:40:59.55#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.174.00:40:59.55#ibcon#enter wrdev, iclass 34, count 2 2006.174.00:40:59.55#ibcon#first serial, iclass 34, count 2 2006.174.00:40:59.55#ibcon#enter sib2, iclass 34, count 2 2006.174.00:40:59.55#ibcon#flushed, iclass 34, count 2 2006.174.00:40:59.55#ibcon#about to write, iclass 34, count 2 2006.174.00:40:59.55#ibcon#wrote, iclass 34, count 2 2006.174.00:40:59.55#ibcon#about to read 3, iclass 34, count 2 2006.174.00:40:59.57#ibcon#read 3, iclass 34, count 2 2006.174.00:40:59.57#ibcon#about to read 4, iclass 34, count 2 2006.174.00:40:59.57#ibcon#read 4, iclass 34, count 2 2006.174.00:40:59.57#ibcon#about to read 5, iclass 34, count 2 2006.174.00:40:59.57#ibcon#read 5, iclass 34, count 2 2006.174.00:40:59.57#ibcon#about to read 6, iclass 34, count 2 2006.174.00:40:59.57#ibcon#read 6, iclass 34, count 2 2006.174.00:40:59.57#ibcon#end of sib2, iclass 34, count 2 2006.174.00:40:59.57#ibcon#*mode == 0, iclass 34, count 2 2006.174.00:40:59.57#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.174.00:40:59.57#ibcon#[27=AT03-04\r\n] 2006.174.00:40:59.57#ibcon#*before write, iclass 34, count 2 2006.174.00:40:59.57#ibcon#enter sib2, iclass 34, count 2 2006.174.00:40:59.57#ibcon#flushed, iclass 34, count 2 2006.174.00:40:59.57#ibcon#about to write, iclass 34, count 2 2006.174.00:40:59.57#ibcon#wrote, iclass 34, count 2 2006.174.00:40:59.57#ibcon#about to read 3, iclass 34, count 2 2006.174.00:40:59.60#ibcon#read 3, iclass 34, count 2 2006.174.00:40:59.60#ibcon#about to read 4, iclass 34, count 2 2006.174.00:40:59.60#ibcon#read 4, iclass 34, count 2 2006.174.00:40:59.60#ibcon#about to read 5, iclass 34, count 2 2006.174.00:40:59.60#ibcon#read 5, iclass 34, count 2 2006.174.00:40:59.60#ibcon#about to read 6, iclass 34, count 2 2006.174.00:40:59.60#ibcon#read 6, iclass 34, count 2 2006.174.00:40:59.60#ibcon#end of sib2, iclass 34, count 2 2006.174.00:40:59.60#ibcon#*after write, iclass 34, count 2 2006.174.00:40:59.60#ibcon#*before return 0, iclass 34, count 2 2006.174.00:40:59.60#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.174.00:40:59.60#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.174.00:40:59.60#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.174.00:40:59.60#ibcon#ireg 7 cls_cnt 0 2006.174.00:40:59.60#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.174.00:40:59.72#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.174.00:40:59.72#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.174.00:40:59.72#ibcon#enter wrdev, iclass 34, count 0 2006.174.00:40:59.72#ibcon#first serial, iclass 34, count 0 2006.174.00:40:59.72#ibcon#enter sib2, iclass 34, count 0 2006.174.00:40:59.72#ibcon#flushed, iclass 34, count 0 2006.174.00:40:59.72#ibcon#about to write, iclass 34, count 0 2006.174.00:40:59.72#ibcon#wrote, iclass 34, count 0 2006.174.00:40:59.72#ibcon#about to read 3, iclass 34, count 0 2006.174.00:40:59.74#ibcon#read 3, iclass 34, count 0 2006.174.00:40:59.74#ibcon#about to read 4, iclass 34, count 0 2006.174.00:40:59.74#ibcon#read 4, iclass 34, count 0 2006.174.00:40:59.74#ibcon#about to read 5, iclass 34, count 0 2006.174.00:40:59.74#ibcon#read 5, iclass 34, count 0 2006.174.00:40:59.74#ibcon#about to read 6, iclass 34, count 0 2006.174.00:40:59.74#ibcon#read 6, iclass 34, count 0 2006.174.00:40:59.74#ibcon#end of sib2, iclass 34, count 0 2006.174.00:40:59.74#ibcon#*mode == 0, iclass 34, count 0 2006.174.00:40:59.74#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.174.00:40:59.74#ibcon#[27=USB\r\n] 2006.174.00:40:59.74#ibcon#*before write, iclass 34, count 0 2006.174.00:40:59.74#ibcon#enter sib2, iclass 34, count 0 2006.174.00:40:59.74#ibcon#flushed, iclass 34, count 0 2006.174.00:40:59.74#ibcon#about to write, iclass 34, count 0 2006.174.00:40:59.74#ibcon#wrote, iclass 34, count 0 2006.174.00:40:59.74#ibcon#about to read 3, iclass 34, count 0 2006.174.00:40:59.77#ibcon#read 3, iclass 34, count 0 2006.174.00:40:59.77#ibcon#about to read 4, iclass 34, count 0 2006.174.00:40:59.77#ibcon#read 4, iclass 34, count 0 2006.174.00:40:59.77#ibcon#about to read 5, iclass 34, count 0 2006.174.00:40:59.77#ibcon#read 5, iclass 34, count 0 2006.174.00:40:59.77#ibcon#about to read 6, iclass 34, count 0 2006.174.00:40:59.77#ibcon#read 6, iclass 34, count 0 2006.174.00:40:59.77#ibcon#end of sib2, iclass 34, count 0 2006.174.00:40:59.77#ibcon#*after write, iclass 34, count 0 2006.174.00:40:59.77#ibcon#*before return 0, iclass 34, count 0 2006.174.00:40:59.77#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.174.00:40:59.77#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.174.00:40:59.77#ibcon#about to clear, iclass 34 cls_cnt 0 2006.174.00:40:59.77#ibcon#cleared, iclass 34 cls_cnt 0 2006.174.00:40:59.77$vck44/vblo=4,679.99 2006.174.00:40:59.77#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.174.00:40:59.77#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.174.00:40:59.77#ibcon#ireg 17 cls_cnt 0 2006.174.00:40:59.77#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.174.00:40:59.77#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.174.00:40:59.77#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.174.00:40:59.77#ibcon#enter wrdev, iclass 36, count 0 2006.174.00:40:59.77#ibcon#first serial, iclass 36, count 0 2006.174.00:40:59.77#ibcon#enter sib2, iclass 36, count 0 2006.174.00:40:59.77#ibcon#flushed, iclass 36, count 0 2006.174.00:40:59.77#ibcon#about to write, iclass 36, count 0 2006.174.00:40:59.77#ibcon#wrote, iclass 36, count 0 2006.174.00:40:59.77#ibcon#about to read 3, iclass 36, count 0 2006.174.00:40:59.79#ibcon#read 3, iclass 36, count 0 2006.174.00:40:59.79#ibcon#about to read 4, iclass 36, count 0 2006.174.00:40:59.79#ibcon#read 4, iclass 36, count 0 2006.174.00:40:59.79#ibcon#about to read 5, iclass 36, count 0 2006.174.00:40:59.79#ibcon#read 5, iclass 36, count 0 2006.174.00:40:59.79#ibcon#about to read 6, iclass 36, count 0 2006.174.00:40:59.79#ibcon#read 6, iclass 36, count 0 2006.174.00:40:59.79#ibcon#end of sib2, iclass 36, count 0 2006.174.00:40:59.79#ibcon#*mode == 0, iclass 36, count 0 2006.174.00:40:59.79#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.174.00:40:59.79#ibcon#[28=FRQ=04,679.99\r\n] 2006.174.00:40:59.79#ibcon#*before write, iclass 36, count 0 2006.174.00:40:59.79#ibcon#enter sib2, iclass 36, count 0 2006.174.00:40:59.79#ibcon#flushed, iclass 36, count 0 2006.174.00:40:59.79#ibcon#about to write, iclass 36, count 0 2006.174.00:40:59.79#ibcon#wrote, iclass 36, count 0 2006.174.00:40:59.79#ibcon#about to read 3, iclass 36, count 0 2006.174.00:40:59.83#ibcon#read 3, iclass 36, count 0 2006.174.00:40:59.83#ibcon#about to read 4, iclass 36, count 0 2006.174.00:40:59.83#ibcon#read 4, iclass 36, count 0 2006.174.00:40:59.83#ibcon#about to read 5, iclass 36, count 0 2006.174.00:40:59.83#ibcon#read 5, iclass 36, count 0 2006.174.00:40:59.83#ibcon#about to read 6, iclass 36, count 0 2006.174.00:40:59.83#ibcon#read 6, iclass 36, count 0 2006.174.00:40:59.83#ibcon#end of sib2, iclass 36, count 0 2006.174.00:40:59.83#ibcon#*after write, iclass 36, count 0 2006.174.00:40:59.83#ibcon#*before return 0, iclass 36, count 0 2006.174.00:40:59.83#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.174.00:40:59.83#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.174.00:40:59.83#ibcon#about to clear, iclass 36 cls_cnt 0 2006.174.00:40:59.83#ibcon#cleared, iclass 36 cls_cnt 0 2006.174.00:40:59.83$vck44/vb=4,4 2006.174.00:40:59.83#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.174.00:40:59.83#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.174.00:40:59.83#ibcon#ireg 11 cls_cnt 2 2006.174.00:40:59.83#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.174.00:40:59.89#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.174.00:40:59.89#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.174.00:40:59.89#ibcon#enter wrdev, iclass 38, count 2 2006.174.00:40:59.89#ibcon#first serial, iclass 38, count 2 2006.174.00:40:59.89#ibcon#enter sib2, iclass 38, count 2 2006.174.00:40:59.89#ibcon#flushed, iclass 38, count 2 2006.174.00:40:59.89#ibcon#about to write, iclass 38, count 2 2006.174.00:40:59.89#ibcon#wrote, iclass 38, count 2 2006.174.00:40:59.89#ibcon#about to read 3, iclass 38, count 2 2006.174.00:40:59.91#ibcon#read 3, iclass 38, count 2 2006.174.00:40:59.91#ibcon#about to read 4, iclass 38, count 2 2006.174.00:40:59.91#ibcon#read 4, iclass 38, count 2 2006.174.00:40:59.91#ibcon#about to read 5, iclass 38, count 2 2006.174.00:40:59.91#ibcon#read 5, iclass 38, count 2 2006.174.00:40:59.91#ibcon#about to read 6, iclass 38, count 2 2006.174.00:40:59.91#ibcon#read 6, iclass 38, count 2 2006.174.00:40:59.91#ibcon#end of sib2, iclass 38, count 2 2006.174.00:40:59.91#ibcon#*mode == 0, iclass 38, count 2 2006.174.00:40:59.91#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.174.00:40:59.91#ibcon#[27=AT04-04\r\n] 2006.174.00:40:59.91#ibcon#*before write, iclass 38, count 2 2006.174.00:40:59.91#ibcon#enter sib2, iclass 38, count 2 2006.174.00:40:59.91#ibcon#flushed, iclass 38, count 2 2006.174.00:40:59.91#ibcon#about to write, iclass 38, count 2 2006.174.00:40:59.91#ibcon#wrote, iclass 38, count 2 2006.174.00:40:59.91#ibcon#about to read 3, iclass 38, count 2 2006.174.00:40:59.94#ibcon#read 3, iclass 38, count 2 2006.174.00:40:59.94#ibcon#about to read 4, iclass 38, count 2 2006.174.00:40:59.94#ibcon#read 4, iclass 38, count 2 2006.174.00:40:59.94#ibcon#about to read 5, iclass 38, count 2 2006.174.00:40:59.94#ibcon#read 5, iclass 38, count 2 2006.174.00:40:59.94#ibcon#about to read 6, iclass 38, count 2 2006.174.00:40:59.94#ibcon#read 6, iclass 38, count 2 2006.174.00:40:59.94#ibcon#end of sib2, iclass 38, count 2 2006.174.00:40:59.94#ibcon#*after write, iclass 38, count 2 2006.174.00:40:59.94#ibcon#*before return 0, iclass 38, count 2 2006.174.00:40:59.94#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.174.00:40:59.94#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.174.00:40:59.94#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.174.00:40:59.94#ibcon#ireg 7 cls_cnt 0 2006.174.00:40:59.94#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.174.00:41:00.06#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.174.00:41:00.06#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.174.00:41:00.06#ibcon#enter wrdev, iclass 38, count 0 2006.174.00:41:00.06#ibcon#first serial, iclass 38, count 0 2006.174.00:41:00.06#ibcon#enter sib2, iclass 38, count 0 2006.174.00:41:00.06#ibcon#flushed, iclass 38, count 0 2006.174.00:41:00.06#ibcon#about to write, iclass 38, count 0 2006.174.00:41:00.06#ibcon#wrote, iclass 38, count 0 2006.174.00:41:00.06#ibcon#about to read 3, iclass 38, count 0 2006.174.00:41:00.08#ibcon#read 3, iclass 38, count 0 2006.174.00:41:00.08#ibcon#about to read 4, iclass 38, count 0 2006.174.00:41:00.08#ibcon#read 4, iclass 38, count 0 2006.174.00:41:00.08#ibcon#about to read 5, iclass 38, count 0 2006.174.00:41:00.08#ibcon#read 5, iclass 38, count 0 2006.174.00:41:00.08#ibcon#about to read 6, iclass 38, count 0 2006.174.00:41:00.08#ibcon#read 6, iclass 38, count 0 2006.174.00:41:00.08#ibcon#end of sib2, iclass 38, count 0 2006.174.00:41:00.08#ibcon#*mode == 0, iclass 38, count 0 2006.174.00:41:00.08#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.174.00:41:00.08#ibcon#[27=USB\r\n] 2006.174.00:41:00.08#ibcon#*before write, iclass 38, count 0 2006.174.00:41:00.08#ibcon#enter sib2, iclass 38, count 0 2006.174.00:41:00.08#ibcon#flushed, iclass 38, count 0 2006.174.00:41:00.08#ibcon#about to write, iclass 38, count 0 2006.174.00:41:00.08#ibcon#wrote, iclass 38, count 0 2006.174.00:41:00.08#ibcon#about to read 3, iclass 38, count 0 2006.174.00:41:00.11#ibcon#read 3, iclass 38, count 0 2006.174.00:41:00.11#ibcon#about to read 4, iclass 38, count 0 2006.174.00:41:00.11#ibcon#read 4, iclass 38, count 0 2006.174.00:41:00.11#ibcon#about to read 5, iclass 38, count 0 2006.174.00:41:00.11#ibcon#read 5, iclass 38, count 0 2006.174.00:41:00.11#ibcon#about to read 6, iclass 38, count 0 2006.174.00:41:00.11#ibcon#read 6, iclass 38, count 0 2006.174.00:41:00.11#ibcon#end of sib2, iclass 38, count 0 2006.174.00:41:00.11#ibcon#*after write, iclass 38, count 0 2006.174.00:41:00.11#ibcon#*before return 0, iclass 38, count 0 2006.174.00:41:00.11#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.174.00:41:00.11#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.174.00:41:00.11#ibcon#about to clear, iclass 38 cls_cnt 0 2006.174.00:41:00.11#ibcon#cleared, iclass 38 cls_cnt 0 2006.174.00:41:00.11$vck44/vblo=5,709.99 2006.174.00:41:00.11#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.174.00:41:00.11#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.174.00:41:00.11#ibcon#ireg 17 cls_cnt 0 2006.174.00:41:00.11#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.174.00:41:00.11#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.174.00:41:00.11#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.174.00:41:00.11#ibcon#enter wrdev, iclass 40, count 0 2006.174.00:41:00.11#ibcon#first serial, iclass 40, count 0 2006.174.00:41:00.11#ibcon#enter sib2, iclass 40, count 0 2006.174.00:41:00.11#ibcon#flushed, iclass 40, count 0 2006.174.00:41:00.11#ibcon#about to write, iclass 40, count 0 2006.174.00:41:00.11#ibcon#wrote, iclass 40, count 0 2006.174.00:41:00.11#ibcon#about to read 3, iclass 40, count 0 2006.174.00:41:00.13#ibcon#read 3, iclass 40, count 0 2006.174.00:41:00.13#ibcon#about to read 4, iclass 40, count 0 2006.174.00:41:00.13#ibcon#read 4, iclass 40, count 0 2006.174.00:41:00.13#ibcon#about to read 5, iclass 40, count 0 2006.174.00:41:00.13#ibcon#read 5, iclass 40, count 0 2006.174.00:41:00.13#ibcon#about to read 6, iclass 40, count 0 2006.174.00:41:00.13#ibcon#read 6, iclass 40, count 0 2006.174.00:41:00.13#ibcon#end of sib2, iclass 40, count 0 2006.174.00:41:00.13#ibcon#*mode == 0, iclass 40, count 0 2006.174.00:41:00.13#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.174.00:41:00.13#ibcon#[28=FRQ=05,709.99\r\n] 2006.174.00:41:00.13#ibcon#*before write, iclass 40, count 0 2006.174.00:41:00.13#ibcon#enter sib2, iclass 40, count 0 2006.174.00:41:00.13#ibcon#flushed, iclass 40, count 0 2006.174.00:41:00.13#ibcon#about to write, iclass 40, count 0 2006.174.00:41:00.13#ibcon#wrote, iclass 40, count 0 2006.174.00:41:00.13#ibcon#about to read 3, iclass 40, count 0 2006.174.00:41:00.17#ibcon#read 3, iclass 40, count 0 2006.174.00:41:00.17#ibcon#about to read 4, iclass 40, count 0 2006.174.00:41:00.17#ibcon#read 4, iclass 40, count 0 2006.174.00:41:00.17#ibcon#about to read 5, iclass 40, count 0 2006.174.00:41:00.17#ibcon#read 5, iclass 40, count 0 2006.174.00:41:00.17#ibcon#about to read 6, iclass 40, count 0 2006.174.00:41:00.17#ibcon#read 6, iclass 40, count 0 2006.174.00:41:00.17#ibcon#end of sib2, iclass 40, count 0 2006.174.00:41:00.17#ibcon#*after write, iclass 40, count 0 2006.174.00:41:00.17#ibcon#*before return 0, iclass 40, count 0 2006.174.00:41:00.17#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.174.00:41:00.17#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.174.00:41:00.17#ibcon#about to clear, iclass 40 cls_cnt 0 2006.174.00:41:00.17#ibcon#cleared, iclass 40 cls_cnt 0 2006.174.00:41:00.17$vck44/vb=5,4 2006.174.00:41:00.17#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.174.00:41:00.17#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.174.00:41:00.17#ibcon#ireg 11 cls_cnt 2 2006.174.00:41:00.17#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.174.00:41:00.23#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.174.00:41:00.23#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.174.00:41:00.23#ibcon#enter wrdev, iclass 4, count 2 2006.174.00:41:00.23#ibcon#first serial, iclass 4, count 2 2006.174.00:41:00.23#ibcon#enter sib2, iclass 4, count 2 2006.174.00:41:00.23#ibcon#flushed, iclass 4, count 2 2006.174.00:41:00.23#ibcon#about to write, iclass 4, count 2 2006.174.00:41:00.23#ibcon#wrote, iclass 4, count 2 2006.174.00:41:00.23#ibcon#about to read 3, iclass 4, count 2 2006.174.00:41:00.25#ibcon#read 3, iclass 4, count 2 2006.174.00:41:00.25#ibcon#about to read 4, iclass 4, count 2 2006.174.00:41:00.25#ibcon#read 4, iclass 4, count 2 2006.174.00:41:00.25#ibcon#about to read 5, iclass 4, count 2 2006.174.00:41:00.25#ibcon#read 5, iclass 4, count 2 2006.174.00:41:00.25#ibcon#about to read 6, iclass 4, count 2 2006.174.00:41:00.25#ibcon#read 6, iclass 4, count 2 2006.174.00:41:00.25#ibcon#end of sib2, iclass 4, count 2 2006.174.00:41:00.25#ibcon#*mode == 0, iclass 4, count 2 2006.174.00:41:00.25#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.174.00:41:00.25#ibcon#[27=AT05-04\r\n] 2006.174.00:41:00.25#ibcon#*before write, iclass 4, count 2 2006.174.00:41:00.25#ibcon#enter sib2, iclass 4, count 2 2006.174.00:41:00.25#ibcon#flushed, iclass 4, count 2 2006.174.00:41:00.25#ibcon#about to write, iclass 4, count 2 2006.174.00:41:00.25#ibcon#wrote, iclass 4, count 2 2006.174.00:41:00.25#ibcon#about to read 3, iclass 4, count 2 2006.174.00:41:00.28#ibcon#read 3, iclass 4, count 2 2006.174.00:41:00.28#ibcon#about to read 4, iclass 4, count 2 2006.174.00:41:00.28#ibcon#read 4, iclass 4, count 2 2006.174.00:41:00.28#ibcon#about to read 5, iclass 4, count 2 2006.174.00:41:00.28#ibcon#read 5, iclass 4, count 2 2006.174.00:41:00.28#ibcon#about to read 6, iclass 4, count 2 2006.174.00:41:00.28#ibcon#read 6, iclass 4, count 2 2006.174.00:41:00.28#ibcon#end of sib2, iclass 4, count 2 2006.174.00:41:00.28#ibcon#*after write, iclass 4, count 2 2006.174.00:41:00.28#ibcon#*before return 0, iclass 4, count 2 2006.174.00:41:00.28#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.174.00:41:00.28#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.174.00:41:00.28#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.174.00:41:00.28#ibcon#ireg 7 cls_cnt 0 2006.174.00:41:00.28#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.174.00:41:00.40#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.174.00:41:00.40#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.174.00:41:00.40#ibcon#enter wrdev, iclass 4, count 0 2006.174.00:41:00.40#ibcon#first serial, iclass 4, count 0 2006.174.00:41:00.40#ibcon#enter sib2, iclass 4, count 0 2006.174.00:41:00.40#ibcon#flushed, iclass 4, count 0 2006.174.00:41:00.40#ibcon#about to write, iclass 4, count 0 2006.174.00:41:00.40#ibcon#wrote, iclass 4, count 0 2006.174.00:41:00.40#ibcon#about to read 3, iclass 4, count 0 2006.174.00:41:00.42#ibcon#read 3, iclass 4, count 0 2006.174.00:41:00.42#ibcon#about to read 4, iclass 4, count 0 2006.174.00:41:00.42#ibcon#read 4, iclass 4, count 0 2006.174.00:41:00.42#ibcon#about to read 5, iclass 4, count 0 2006.174.00:41:00.42#ibcon#read 5, iclass 4, count 0 2006.174.00:41:00.42#ibcon#about to read 6, iclass 4, count 0 2006.174.00:41:00.42#ibcon#read 6, iclass 4, count 0 2006.174.00:41:00.42#ibcon#end of sib2, iclass 4, count 0 2006.174.00:41:00.42#ibcon#*mode == 0, iclass 4, count 0 2006.174.00:41:00.42#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.174.00:41:00.42#ibcon#[27=USB\r\n] 2006.174.00:41:00.42#ibcon#*before write, iclass 4, count 0 2006.174.00:41:00.42#ibcon#enter sib2, iclass 4, count 0 2006.174.00:41:00.42#ibcon#flushed, iclass 4, count 0 2006.174.00:41:00.42#ibcon#about to write, iclass 4, count 0 2006.174.00:41:00.42#ibcon#wrote, iclass 4, count 0 2006.174.00:41:00.42#ibcon#about to read 3, iclass 4, count 0 2006.174.00:41:00.45#ibcon#read 3, iclass 4, count 0 2006.174.00:41:00.45#ibcon#about to read 4, iclass 4, count 0 2006.174.00:41:00.45#ibcon#read 4, iclass 4, count 0 2006.174.00:41:00.45#ibcon#about to read 5, iclass 4, count 0 2006.174.00:41:00.45#ibcon#read 5, iclass 4, count 0 2006.174.00:41:00.45#ibcon#about to read 6, iclass 4, count 0 2006.174.00:41:00.45#ibcon#read 6, iclass 4, count 0 2006.174.00:41:00.45#ibcon#end of sib2, iclass 4, count 0 2006.174.00:41:00.45#ibcon#*after write, iclass 4, count 0 2006.174.00:41:00.45#ibcon#*before return 0, iclass 4, count 0 2006.174.00:41:00.45#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.174.00:41:00.45#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.174.00:41:00.45#ibcon#about to clear, iclass 4 cls_cnt 0 2006.174.00:41:00.45#ibcon#cleared, iclass 4 cls_cnt 0 2006.174.00:41:00.45$vck44/vblo=6,719.99 2006.174.00:41:00.45#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.174.00:41:00.45#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.174.00:41:00.45#ibcon#ireg 17 cls_cnt 0 2006.174.00:41:00.45#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.174.00:41:00.45#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.174.00:41:00.45#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.174.00:41:00.45#ibcon#enter wrdev, iclass 6, count 0 2006.174.00:41:00.45#ibcon#first serial, iclass 6, count 0 2006.174.00:41:00.45#ibcon#enter sib2, iclass 6, count 0 2006.174.00:41:00.45#ibcon#flushed, iclass 6, count 0 2006.174.00:41:00.45#ibcon#about to write, iclass 6, count 0 2006.174.00:41:00.45#ibcon#wrote, iclass 6, count 0 2006.174.00:41:00.45#ibcon#about to read 3, iclass 6, count 0 2006.174.00:41:00.47#ibcon#read 3, iclass 6, count 0 2006.174.00:41:00.47#ibcon#about to read 4, iclass 6, count 0 2006.174.00:41:00.47#ibcon#read 4, iclass 6, count 0 2006.174.00:41:00.47#ibcon#about to read 5, iclass 6, count 0 2006.174.00:41:00.47#ibcon#read 5, iclass 6, count 0 2006.174.00:41:00.47#ibcon#about to read 6, iclass 6, count 0 2006.174.00:41:00.47#ibcon#read 6, iclass 6, count 0 2006.174.00:41:00.47#ibcon#end of sib2, iclass 6, count 0 2006.174.00:41:00.47#ibcon#*mode == 0, iclass 6, count 0 2006.174.00:41:00.47#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.174.00:41:00.47#ibcon#[28=FRQ=06,719.99\r\n] 2006.174.00:41:00.47#ibcon#*before write, iclass 6, count 0 2006.174.00:41:00.47#ibcon#enter sib2, iclass 6, count 0 2006.174.00:41:00.47#ibcon#flushed, iclass 6, count 0 2006.174.00:41:00.47#ibcon#about to write, iclass 6, count 0 2006.174.00:41:00.47#ibcon#wrote, iclass 6, count 0 2006.174.00:41:00.47#ibcon#about to read 3, iclass 6, count 0 2006.174.00:41:00.51#ibcon#read 3, iclass 6, count 0 2006.174.00:41:00.51#ibcon#about to read 4, iclass 6, count 0 2006.174.00:41:00.51#ibcon#read 4, iclass 6, count 0 2006.174.00:41:00.51#ibcon#about to read 5, iclass 6, count 0 2006.174.00:41:00.51#ibcon#read 5, iclass 6, count 0 2006.174.00:41:00.51#ibcon#about to read 6, iclass 6, count 0 2006.174.00:41:00.51#ibcon#read 6, iclass 6, count 0 2006.174.00:41:00.51#ibcon#end of sib2, iclass 6, count 0 2006.174.00:41:00.51#ibcon#*after write, iclass 6, count 0 2006.174.00:41:00.51#ibcon#*before return 0, iclass 6, count 0 2006.174.00:41:00.51#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.174.00:41:00.51#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.174.00:41:00.51#ibcon#about to clear, iclass 6 cls_cnt 0 2006.174.00:41:00.51#ibcon#cleared, iclass 6 cls_cnt 0 2006.174.00:41:00.51$vck44/vb=6,4 2006.174.00:41:00.51#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.174.00:41:00.51#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.174.00:41:00.51#ibcon#ireg 11 cls_cnt 2 2006.174.00:41:00.51#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.174.00:41:00.57#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.174.00:41:00.57#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.174.00:41:00.57#ibcon#enter wrdev, iclass 10, count 2 2006.174.00:41:00.57#ibcon#first serial, iclass 10, count 2 2006.174.00:41:00.57#ibcon#enter sib2, iclass 10, count 2 2006.174.00:41:00.57#ibcon#flushed, iclass 10, count 2 2006.174.00:41:00.57#ibcon#about to write, iclass 10, count 2 2006.174.00:41:00.57#ibcon#wrote, iclass 10, count 2 2006.174.00:41:00.57#ibcon#about to read 3, iclass 10, count 2 2006.174.00:41:00.59#ibcon#read 3, iclass 10, count 2 2006.174.00:41:00.59#ibcon#about to read 4, iclass 10, count 2 2006.174.00:41:00.59#ibcon#read 4, iclass 10, count 2 2006.174.00:41:00.59#ibcon#about to read 5, iclass 10, count 2 2006.174.00:41:00.59#ibcon#read 5, iclass 10, count 2 2006.174.00:41:00.59#ibcon#about to read 6, iclass 10, count 2 2006.174.00:41:00.59#ibcon#read 6, iclass 10, count 2 2006.174.00:41:00.59#ibcon#end of sib2, iclass 10, count 2 2006.174.00:41:00.59#ibcon#*mode == 0, iclass 10, count 2 2006.174.00:41:00.59#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.174.00:41:00.59#ibcon#[27=AT06-04\r\n] 2006.174.00:41:00.59#ibcon#*before write, iclass 10, count 2 2006.174.00:41:00.59#ibcon#enter sib2, iclass 10, count 2 2006.174.00:41:00.59#ibcon#flushed, iclass 10, count 2 2006.174.00:41:00.59#ibcon#about to write, iclass 10, count 2 2006.174.00:41:00.59#ibcon#wrote, iclass 10, count 2 2006.174.00:41:00.59#ibcon#about to read 3, iclass 10, count 2 2006.174.00:41:00.62#ibcon#read 3, iclass 10, count 2 2006.174.00:41:00.62#ibcon#about to read 4, iclass 10, count 2 2006.174.00:41:00.62#ibcon#read 4, iclass 10, count 2 2006.174.00:41:00.62#ibcon#about to read 5, iclass 10, count 2 2006.174.00:41:00.62#ibcon#read 5, iclass 10, count 2 2006.174.00:41:00.62#ibcon#about to read 6, iclass 10, count 2 2006.174.00:41:00.62#ibcon#read 6, iclass 10, count 2 2006.174.00:41:00.62#ibcon#end of sib2, iclass 10, count 2 2006.174.00:41:00.62#ibcon#*after write, iclass 10, count 2 2006.174.00:41:00.62#ibcon#*before return 0, iclass 10, count 2 2006.174.00:41:00.62#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.174.00:41:00.62#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.174.00:41:00.62#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.174.00:41:00.62#ibcon#ireg 7 cls_cnt 0 2006.174.00:41:00.62#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.174.00:41:00.74#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.174.00:41:00.74#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.174.00:41:00.74#ibcon#enter wrdev, iclass 10, count 0 2006.174.00:41:00.74#ibcon#first serial, iclass 10, count 0 2006.174.00:41:00.74#ibcon#enter sib2, iclass 10, count 0 2006.174.00:41:00.74#ibcon#flushed, iclass 10, count 0 2006.174.00:41:00.74#ibcon#about to write, iclass 10, count 0 2006.174.00:41:00.74#ibcon#wrote, iclass 10, count 0 2006.174.00:41:00.74#ibcon#about to read 3, iclass 10, count 0 2006.174.00:41:00.76#ibcon#read 3, iclass 10, count 0 2006.174.00:41:00.76#ibcon#about to read 4, iclass 10, count 0 2006.174.00:41:00.76#ibcon#read 4, iclass 10, count 0 2006.174.00:41:00.76#ibcon#about to read 5, iclass 10, count 0 2006.174.00:41:00.76#ibcon#read 5, iclass 10, count 0 2006.174.00:41:00.76#ibcon#about to read 6, iclass 10, count 0 2006.174.00:41:00.76#ibcon#read 6, iclass 10, count 0 2006.174.00:41:00.76#ibcon#end of sib2, iclass 10, count 0 2006.174.00:41:00.76#ibcon#*mode == 0, iclass 10, count 0 2006.174.00:41:00.76#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.174.00:41:00.76#ibcon#[27=USB\r\n] 2006.174.00:41:00.76#ibcon#*before write, iclass 10, count 0 2006.174.00:41:00.76#ibcon#enter sib2, iclass 10, count 0 2006.174.00:41:00.76#ibcon#flushed, iclass 10, count 0 2006.174.00:41:00.76#ibcon#about to write, iclass 10, count 0 2006.174.00:41:00.76#ibcon#wrote, iclass 10, count 0 2006.174.00:41:00.76#ibcon#about to read 3, iclass 10, count 0 2006.174.00:41:00.79#ibcon#read 3, iclass 10, count 0 2006.174.00:41:00.79#ibcon#about to read 4, iclass 10, count 0 2006.174.00:41:00.79#ibcon#read 4, iclass 10, count 0 2006.174.00:41:00.79#ibcon#about to read 5, iclass 10, count 0 2006.174.00:41:00.79#ibcon#read 5, iclass 10, count 0 2006.174.00:41:00.79#ibcon#about to read 6, iclass 10, count 0 2006.174.00:41:00.79#ibcon#read 6, iclass 10, count 0 2006.174.00:41:00.79#ibcon#end of sib2, iclass 10, count 0 2006.174.00:41:00.79#ibcon#*after write, iclass 10, count 0 2006.174.00:41:00.79#ibcon#*before return 0, iclass 10, count 0 2006.174.00:41:00.79#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.174.00:41:00.79#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.174.00:41:00.79#ibcon#about to clear, iclass 10 cls_cnt 0 2006.174.00:41:00.79#ibcon#cleared, iclass 10 cls_cnt 0 2006.174.00:41:00.79$vck44/vblo=7,734.99 2006.174.00:41:00.79#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.174.00:41:00.79#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.174.00:41:00.79#ibcon#ireg 17 cls_cnt 0 2006.174.00:41:00.79#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.174.00:41:00.79#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.174.00:41:00.79#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.174.00:41:00.79#ibcon#enter wrdev, iclass 12, count 0 2006.174.00:41:00.79#ibcon#first serial, iclass 12, count 0 2006.174.00:41:00.79#ibcon#enter sib2, iclass 12, count 0 2006.174.00:41:00.79#ibcon#flushed, iclass 12, count 0 2006.174.00:41:00.79#ibcon#about to write, iclass 12, count 0 2006.174.00:41:00.79#ibcon#wrote, iclass 12, count 0 2006.174.00:41:00.79#ibcon#about to read 3, iclass 12, count 0 2006.174.00:41:00.81#ibcon#read 3, iclass 12, count 0 2006.174.00:41:00.81#ibcon#about to read 4, iclass 12, count 0 2006.174.00:41:00.81#ibcon#read 4, iclass 12, count 0 2006.174.00:41:00.81#ibcon#about to read 5, iclass 12, count 0 2006.174.00:41:00.81#ibcon#read 5, iclass 12, count 0 2006.174.00:41:00.81#ibcon#about to read 6, iclass 12, count 0 2006.174.00:41:00.81#ibcon#read 6, iclass 12, count 0 2006.174.00:41:00.81#ibcon#end of sib2, iclass 12, count 0 2006.174.00:41:00.81#ibcon#*mode == 0, iclass 12, count 0 2006.174.00:41:00.81#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.174.00:41:00.81#ibcon#[28=FRQ=07,734.99\r\n] 2006.174.00:41:00.81#ibcon#*before write, iclass 12, count 0 2006.174.00:41:00.81#ibcon#enter sib2, iclass 12, count 0 2006.174.00:41:00.81#ibcon#flushed, iclass 12, count 0 2006.174.00:41:00.81#ibcon#about to write, iclass 12, count 0 2006.174.00:41:00.81#ibcon#wrote, iclass 12, count 0 2006.174.00:41:00.81#ibcon#about to read 3, iclass 12, count 0 2006.174.00:41:00.85#ibcon#read 3, iclass 12, count 0 2006.174.00:41:00.85#ibcon#about to read 4, iclass 12, count 0 2006.174.00:41:00.85#ibcon#read 4, iclass 12, count 0 2006.174.00:41:00.85#ibcon#about to read 5, iclass 12, count 0 2006.174.00:41:00.85#ibcon#read 5, iclass 12, count 0 2006.174.00:41:00.85#ibcon#about to read 6, iclass 12, count 0 2006.174.00:41:00.85#ibcon#read 6, iclass 12, count 0 2006.174.00:41:00.85#ibcon#end of sib2, iclass 12, count 0 2006.174.00:41:00.85#ibcon#*after write, iclass 12, count 0 2006.174.00:41:00.85#ibcon#*before return 0, iclass 12, count 0 2006.174.00:41:00.85#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.174.00:41:00.85#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.174.00:41:00.85#ibcon#about to clear, iclass 12 cls_cnt 0 2006.174.00:41:00.85#ibcon#cleared, iclass 12 cls_cnt 0 2006.174.00:41:00.85$vck44/vb=7,4 2006.174.00:41:00.85#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.174.00:41:00.85#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.174.00:41:00.85#ibcon#ireg 11 cls_cnt 2 2006.174.00:41:00.85#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.174.00:41:00.91#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.174.00:41:00.91#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.174.00:41:00.91#ibcon#enter wrdev, iclass 14, count 2 2006.174.00:41:00.91#ibcon#first serial, iclass 14, count 2 2006.174.00:41:00.91#ibcon#enter sib2, iclass 14, count 2 2006.174.00:41:00.91#ibcon#flushed, iclass 14, count 2 2006.174.00:41:00.91#ibcon#about to write, iclass 14, count 2 2006.174.00:41:00.91#ibcon#wrote, iclass 14, count 2 2006.174.00:41:00.91#ibcon#about to read 3, iclass 14, count 2 2006.174.00:41:00.93#ibcon#read 3, iclass 14, count 2 2006.174.00:41:00.93#ibcon#about to read 4, iclass 14, count 2 2006.174.00:41:00.93#ibcon#read 4, iclass 14, count 2 2006.174.00:41:00.93#ibcon#about to read 5, iclass 14, count 2 2006.174.00:41:00.93#ibcon#read 5, iclass 14, count 2 2006.174.00:41:00.93#ibcon#about to read 6, iclass 14, count 2 2006.174.00:41:00.93#ibcon#read 6, iclass 14, count 2 2006.174.00:41:00.93#ibcon#end of sib2, iclass 14, count 2 2006.174.00:41:00.93#ibcon#*mode == 0, iclass 14, count 2 2006.174.00:41:00.93#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.174.00:41:00.93#ibcon#[27=AT07-04\r\n] 2006.174.00:41:00.93#ibcon#*before write, iclass 14, count 2 2006.174.00:41:00.93#ibcon#enter sib2, iclass 14, count 2 2006.174.00:41:00.93#ibcon#flushed, iclass 14, count 2 2006.174.00:41:00.93#ibcon#about to write, iclass 14, count 2 2006.174.00:41:00.93#ibcon#wrote, iclass 14, count 2 2006.174.00:41:00.93#ibcon#about to read 3, iclass 14, count 2 2006.174.00:41:00.96#ibcon#read 3, iclass 14, count 2 2006.174.00:41:00.96#ibcon#about to read 4, iclass 14, count 2 2006.174.00:41:00.96#ibcon#read 4, iclass 14, count 2 2006.174.00:41:00.96#ibcon#about to read 5, iclass 14, count 2 2006.174.00:41:00.96#ibcon#read 5, iclass 14, count 2 2006.174.00:41:00.96#ibcon#about to read 6, iclass 14, count 2 2006.174.00:41:00.96#ibcon#read 6, iclass 14, count 2 2006.174.00:41:00.96#ibcon#end of sib2, iclass 14, count 2 2006.174.00:41:00.96#ibcon#*after write, iclass 14, count 2 2006.174.00:41:00.96#ibcon#*before return 0, iclass 14, count 2 2006.174.00:41:00.96#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.174.00:41:00.96#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.174.00:41:00.96#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.174.00:41:00.96#ibcon#ireg 7 cls_cnt 0 2006.174.00:41:00.96#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.174.00:41:01.08#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.174.00:41:01.08#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.174.00:41:01.08#ibcon#enter wrdev, iclass 14, count 0 2006.174.00:41:01.08#ibcon#first serial, iclass 14, count 0 2006.174.00:41:01.08#ibcon#enter sib2, iclass 14, count 0 2006.174.00:41:01.08#ibcon#flushed, iclass 14, count 0 2006.174.00:41:01.08#ibcon#about to write, iclass 14, count 0 2006.174.00:41:01.08#ibcon#wrote, iclass 14, count 0 2006.174.00:41:01.08#ibcon#about to read 3, iclass 14, count 0 2006.174.00:41:01.10#ibcon#read 3, iclass 14, count 0 2006.174.00:41:01.10#ibcon#about to read 4, iclass 14, count 0 2006.174.00:41:01.10#ibcon#read 4, iclass 14, count 0 2006.174.00:41:01.10#ibcon#about to read 5, iclass 14, count 0 2006.174.00:41:01.10#ibcon#read 5, iclass 14, count 0 2006.174.00:41:01.10#ibcon#about to read 6, iclass 14, count 0 2006.174.00:41:01.10#ibcon#read 6, iclass 14, count 0 2006.174.00:41:01.10#ibcon#end of sib2, iclass 14, count 0 2006.174.00:41:01.10#ibcon#*mode == 0, iclass 14, count 0 2006.174.00:41:01.10#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.174.00:41:01.10#ibcon#[27=USB\r\n] 2006.174.00:41:01.10#ibcon#*before write, iclass 14, count 0 2006.174.00:41:01.10#ibcon#enter sib2, iclass 14, count 0 2006.174.00:41:01.10#ibcon#flushed, iclass 14, count 0 2006.174.00:41:01.10#ibcon#about to write, iclass 14, count 0 2006.174.00:41:01.10#ibcon#wrote, iclass 14, count 0 2006.174.00:41:01.10#ibcon#about to read 3, iclass 14, count 0 2006.174.00:41:01.13#ibcon#read 3, iclass 14, count 0 2006.174.00:41:01.13#ibcon#about to read 4, iclass 14, count 0 2006.174.00:41:01.13#ibcon#read 4, iclass 14, count 0 2006.174.00:41:01.13#ibcon#about to read 5, iclass 14, count 0 2006.174.00:41:01.13#ibcon#read 5, iclass 14, count 0 2006.174.00:41:01.13#ibcon#about to read 6, iclass 14, count 0 2006.174.00:41:01.13#ibcon#read 6, iclass 14, count 0 2006.174.00:41:01.13#ibcon#end of sib2, iclass 14, count 0 2006.174.00:41:01.13#ibcon#*after write, iclass 14, count 0 2006.174.00:41:01.13#ibcon#*before return 0, iclass 14, count 0 2006.174.00:41:01.13#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.174.00:41:01.13#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.174.00:41:01.13#ibcon#about to clear, iclass 14 cls_cnt 0 2006.174.00:41:01.13#ibcon#cleared, iclass 14 cls_cnt 0 2006.174.00:41:01.13$vck44/vblo=8,744.99 2006.174.00:41:01.13#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.174.00:41:01.13#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.174.00:41:01.13#ibcon#ireg 17 cls_cnt 0 2006.174.00:41:01.13#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.174.00:41:01.13#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.174.00:41:01.13#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.174.00:41:01.13#ibcon#enter wrdev, iclass 16, count 0 2006.174.00:41:01.13#ibcon#first serial, iclass 16, count 0 2006.174.00:41:01.13#ibcon#enter sib2, iclass 16, count 0 2006.174.00:41:01.13#ibcon#flushed, iclass 16, count 0 2006.174.00:41:01.13#ibcon#about to write, iclass 16, count 0 2006.174.00:41:01.13#ibcon#wrote, iclass 16, count 0 2006.174.00:41:01.13#ibcon#about to read 3, iclass 16, count 0 2006.174.00:41:01.15#ibcon#read 3, iclass 16, count 0 2006.174.00:41:01.15#ibcon#about to read 4, iclass 16, count 0 2006.174.00:41:01.15#ibcon#read 4, iclass 16, count 0 2006.174.00:41:01.15#ibcon#about to read 5, iclass 16, count 0 2006.174.00:41:01.15#ibcon#read 5, iclass 16, count 0 2006.174.00:41:01.15#ibcon#about to read 6, iclass 16, count 0 2006.174.00:41:01.15#ibcon#read 6, iclass 16, count 0 2006.174.00:41:01.15#ibcon#end of sib2, iclass 16, count 0 2006.174.00:41:01.15#ibcon#*mode == 0, iclass 16, count 0 2006.174.00:41:01.15#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.174.00:41:01.15#ibcon#[28=FRQ=08,744.99\r\n] 2006.174.00:41:01.15#ibcon#*before write, iclass 16, count 0 2006.174.00:41:01.15#ibcon#enter sib2, iclass 16, count 0 2006.174.00:41:01.15#ibcon#flushed, iclass 16, count 0 2006.174.00:41:01.15#ibcon#about to write, iclass 16, count 0 2006.174.00:41:01.15#ibcon#wrote, iclass 16, count 0 2006.174.00:41:01.15#ibcon#about to read 3, iclass 16, count 0 2006.174.00:41:01.19#ibcon#read 3, iclass 16, count 0 2006.174.00:41:01.19#ibcon#about to read 4, iclass 16, count 0 2006.174.00:41:01.19#ibcon#read 4, iclass 16, count 0 2006.174.00:41:01.19#ibcon#about to read 5, iclass 16, count 0 2006.174.00:41:01.19#ibcon#read 5, iclass 16, count 0 2006.174.00:41:01.19#ibcon#about to read 6, iclass 16, count 0 2006.174.00:41:01.19#ibcon#read 6, iclass 16, count 0 2006.174.00:41:01.19#ibcon#end of sib2, iclass 16, count 0 2006.174.00:41:01.19#ibcon#*after write, iclass 16, count 0 2006.174.00:41:01.19#ibcon#*before return 0, iclass 16, count 0 2006.174.00:41:01.19#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.174.00:41:01.19#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.174.00:41:01.19#ibcon#about to clear, iclass 16 cls_cnt 0 2006.174.00:41:01.19#ibcon#cleared, iclass 16 cls_cnt 0 2006.174.00:41:01.19$vck44/vb=8,4 2006.174.00:41:01.19#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.174.00:41:01.19#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.174.00:41:01.19#ibcon#ireg 11 cls_cnt 2 2006.174.00:41:01.19#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.174.00:41:01.25#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.174.00:41:01.25#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.174.00:41:01.25#ibcon#enter wrdev, iclass 18, count 2 2006.174.00:41:01.25#ibcon#first serial, iclass 18, count 2 2006.174.00:41:01.25#ibcon#enter sib2, iclass 18, count 2 2006.174.00:41:01.25#ibcon#flushed, iclass 18, count 2 2006.174.00:41:01.25#ibcon#about to write, iclass 18, count 2 2006.174.00:41:01.25#ibcon#wrote, iclass 18, count 2 2006.174.00:41:01.25#ibcon#about to read 3, iclass 18, count 2 2006.174.00:41:01.27#ibcon#read 3, iclass 18, count 2 2006.174.00:41:01.27#ibcon#about to read 4, iclass 18, count 2 2006.174.00:41:01.27#ibcon#read 4, iclass 18, count 2 2006.174.00:41:01.27#ibcon#about to read 5, iclass 18, count 2 2006.174.00:41:01.27#ibcon#read 5, iclass 18, count 2 2006.174.00:41:01.27#ibcon#about to read 6, iclass 18, count 2 2006.174.00:41:01.27#ibcon#read 6, iclass 18, count 2 2006.174.00:41:01.27#ibcon#end of sib2, iclass 18, count 2 2006.174.00:41:01.27#ibcon#*mode == 0, iclass 18, count 2 2006.174.00:41:01.27#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.174.00:41:01.27#ibcon#[27=AT08-04\r\n] 2006.174.00:41:01.27#ibcon#*before write, iclass 18, count 2 2006.174.00:41:01.27#ibcon#enter sib2, iclass 18, count 2 2006.174.00:41:01.27#ibcon#flushed, iclass 18, count 2 2006.174.00:41:01.27#ibcon#about to write, iclass 18, count 2 2006.174.00:41:01.27#ibcon#wrote, iclass 18, count 2 2006.174.00:41:01.27#ibcon#about to read 3, iclass 18, count 2 2006.174.00:41:01.30#ibcon#read 3, iclass 18, count 2 2006.174.00:41:01.30#ibcon#about to read 4, iclass 18, count 2 2006.174.00:41:01.30#ibcon#read 4, iclass 18, count 2 2006.174.00:41:01.30#ibcon#about to read 5, iclass 18, count 2 2006.174.00:41:01.30#ibcon#read 5, iclass 18, count 2 2006.174.00:41:01.30#ibcon#about to read 6, iclass 18, count 2 2006.174.00:41:01.30#ibcon#read 6, iclass 18, count 2 2006.174.00:41:01.30#ibcon#end of sib2, iclass 18, count 2 2006.174.00:41:01.30#ibcon#*after write, iclass 18, count 2 2006.174.00:41:01.30#ibcon#*before return 0, iclass 18, count 2 2006.174.00:41:01.30#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.174.00:41:01.30#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.174.00:41:01.30#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.174.00:41:01.30#ibcon#ireg 7 cls_cnt 0 2006.174.00:41:01.30#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.174.00:41:01.42#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.174.00:41:01.42#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.174.00:41:01.42#ibcon#enter wrdev, iclass 18, count 0 2006.174.00:41:01.42#ibcon#first serial, iclass 18, count 0 2006.174.00:41:01.42#ibcon#enter sib2, iclass 18, count 0 2006.174.00:41:01.42#ibcon#flushed, iclass 18, count 0 2006.174.00:41:01.42#ibcon#about to write, iclass 18, count 0 2006.174.00:41:01.42#ibcon#wrote, iclass 18, count 0 2006.174.00:41:01.42#ibcon#about to read 3, iclass 18, count 0 2006.174.00:41:01.44#ibcon#read 3, iclass 18, count 0 2006.174.00:41:01.44#ibcon#about to read 4, iclass 18, count 0 2006.174.00:41:01.44#ibcon#read 4, iclass 18, count 0 2006.174.00:41:01.44#ibcon#about to read 5, iclass 18, count 0 2006.174.00:41:01.44#ibcon#read 5, iclass 18, count 0 2006.174.00:41:01.44#ibcon#about to read 6, iclass 18, count 0 2006.174.00:41:01.44#ibcon#read 6, iclass 18, count 0 2006.174.00:41:01.44#ibcon#end of sib2, iclass 18, count 0 2006.174.00:41:01.44#ibcon#*mode == 0, iclass 18, count 0 2006.174.00:41:01.44#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.174.00:41:01.44#ibcon#[27=USB\r\n] 2006.174.00:41:01.44#ibcon#*before write, iclass 18, count 0 2006.174.00:41:01.44#ibcon#enter sib2, iclass 18, count 0 2006.174.00:41:01.44#ibcon#flushed, iclass 18, count 0 2006.174.00:41:01.44#ibcon#about to write, iclass 18, count 0 2006.174.00:41:01.44#ibcon#wrote, iclass 18, count 0 2006.174.00:41:01.44#ibcon#about to read 3, iclass 18, count 0 2006.174.00:41:01.47#ibcon#read 3, iclass 18, count 0 2006.174.00:41:01.47#ibcon#about to read 4, iclass 18, count 0 2006.174.00:41:01.47#ibcon#read 4, iclass 18, count 0 2006.174.00:41:01.47#ibcon#about to read 5, iclass 18, count 0 2006.174.00:41:01.47#ibcon#read 5, iclass 18, count 0 2006.174.00:41:01.47#ibcon#about to read 6, iclass 18, count 0 2006.174.00:41:01.47#ibcon#read 6, iclass 18, count 0 2006.174.00:41:01.47#ibcon#end of sib2, iclass 18, count 0 2006.174.00:41:01.47#ibcon#*after write, iclass 18, count 0 2006.174.00:41:01.47#ibcon#*before return 0, iclass 18, count 0 2006.174.00:41:01.47#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.174.00:41:01.47#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.174.00:41:01.47#ibcon#about to clear, iclass 18 cls_cnt 0 2006.174.00:41:01.47#ibcon#cleared, iclass 18 cls_cnt 0 2006.174.00:41:01.47$vck44/vabw=wide 2006.174.00:41:01.47#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.174.00:41:01.47#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.174.00:41:01.47#ibcon#ireg 8 cls_cnt 0 2006.174.00:41:01.47#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.174.00:41:01.47#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.174.00:41:01.47#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.174.00:41:01.47#ibcon#enter wrdev, iclass 20, count 0 2006.174.00:41:01.47#ibcon#first serial, iclass 20, count 0 2006.174.00:41:01.47#ibcon#enter sib2, iclass 20, count 0 2006.174.00:41:01.47#ibcon#flushed, iclass 20, count 0 2006.174.00:41:01.47#ibcon#about to write, iclass 20, count 0 2006.174.00:41:01.47#ibcon#wrote, iclass 20, count 0 2006.174.00:41:01.47#ibcon#about to read 3, iclass 20, count 0 2006.174.00:41:01.49#ibcon#read 3, iclass 20, count 0 2006.174.00:41:01.49#ibcon#about to read 4, iclass 20, count 0 2006.174.00:41:01.49#ibcon#read 4, iclass 20, count 0 2006.174.00:41:01.49#ibcon#about to read 5, iclass 20, count 0 2006.174.00:41:01.49#ibcon#read 5, iclass 20, count 0 2006.174.00:41:01.49#ibcon#about to read 6, iclass 20, count 0 2006.174.00:41:01.49#ibcon#read 6, iclass 20, count 0 2006.174.00:41:01.49#ibcon#end of sib2, iclass 20, count 0 2006.174.00:41:01.49#ibcon#*mode == 0, iclass 20, count 0 2006.174.00:41:01.49#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.174.00:41:01.49#ibcon#[25=BW32\r\n] 2006.174.00:41:01.49#ibcon#*before write, iclass 20, count 0 2006.174.00:41:01.49#ibcon#enter sib2, iclass 20, count 0 2006.174.00:41:01.49#ibcon#flushed, iclass 20, count 0 2006.174.00:41:01.49#ibcon#about to write, iclass 20, count 0 2006.174.00:41:01.49#ibcon#wrote, iclass 20, count 0 2006.174.00:41:01.49#ibcon#about to read 3, iclass 20, count 0 2006.174.00:41:01.52#ibcon#read 3, iclass 20, count 0 2006.174.00:41:01.52#ibcon#about to read 4, iclass 20, count 0 2006.174.00:41:01.52#ibcon#read 4, iclass 20, count 0 2006.174.00:41:01.52#ibcon#about to read 5, iclass 20, count 0 2006.174.00:41:01.52#ibcon#read 5, iclass 20, count 0 2006.174.00:41:01.52#ibcon#about to read 6, iclass 20, count 0 2006.174.00:41:01.52#ibcon#read 6, iclass 20, count 0 2006.174.00:41:01.52#ibcon#end of sib2, iclass 20, count 0 2006.174.00:41:01.52#ibcon#*after write, iclass 20, count 0 2006.174.00:41:01.52#ibcon#*before return 0, iclass 20, count 0 2006.174.00:41:01.52#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.174.00:41:01.52#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.174.00:41:01.52#ibcon#about to clear, iclass 20 cls_cnt 0 2006.174.00:41:01.52#ibcon#cleared, iclass 20 cls_cnt 0 2006.174.00:41:01.52$vck44/vbbw=wide 2006.174.00:41:01.52#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.174.00:41:01.52#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.174.00:41:01.52#ibcon#ireg 8 cls_cnt 0 2006.174.00:41:01.52#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.174.00:41:01.59#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.174.00:41:01.59#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.174.00:41:01.59#ibcon#enter wrdev, iclass 22, count 0 2006.174.00:41:01.59#ibcon#first serial, iclass 22, count 0 2006.174.00:41:01.59#ibcon#enter sib2, iclass 22, count 0 2006.174.00:41:01.59#ibcon#flushed, iclass 22, count 0 2006.174.00:41:01.59#ibcon#about to write, iclass 22, count 0 2006.174.00:41:01.59#ibcon#wrote, iclass 22, count 0 2006.174.00:41:01.59#ibcon#about to read 3, iclass 22, count 0 2006.174.00:41:01.61#ibcon#read 3, iclass 22, count 0 2006.174.00:41:01.61#ibcon#about to read 4, iclass 22, count 0 2006.174.00:41:01.61#ibcon#read 4, iclass 22, count 0 2006.174.00:41:01.61#ibcon#about to read 5, iclass 22, count 0 2006.174.00:41:01.61#ibcon#read 5, iclass 22, count 0 2006.174.00:41:01.61#ibcon#about to read 6, iclass 22, count 0 2006.174.00:41:01.61#ibcon#read 6, iclass 22, count 0 2006.174.00:41:01.61#ibcon#end of sib2, iclass 22, count 0 2006.174.00:41:01.61#ibcon#*mode == 0, iclass 22, count 0 2006.174.00:41:01.61#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.174.00:41:01.61#ibcon#[27=BW32\r\n] 2006.174.00:41:01.61#ibcon#*before write, iclass 22, count 0 2006.174.00:41:01.61#ibcon#enter sib2, iclass 22, count 0 2006.174.00:41:01.61#ibcon#flushed, iclass 22, count 0 2006.174.00:41:01.61#ibcon#about to write, iclass 22, count 0 2006.174.00:41:01.61#ibcon#wrote, iclass 22, count 0 2006.174.00:41:01.61#ibcon#about to read 3, iclass 22, count 0 2006.174.00:41:01.64#ibcon#read 3, iclass 22, count 0 2006.174.00:41:01.64#ibcon#about to read 4, iclass 22, count 0 2006.174.00:41:01.64#ibcon#read 4, iclass 22, count 0 2006.174.00:41:01.64#ibcon#about to read 5, iclass 22, count 0 2006.174.00:41:01.64#ibcon#read 5, iclass 22, count 0 2006.174.00:41:01.64#ibcon#about to read 6, iclass 22, count 0 2006.174.00:41:01.64#ibcon#read 6, iclass 22, count 0 2006.174.00:41:01.64#ibcon#end of sib2, iclass 22, count 0 2006.174.00:41:01.64#ibcon#*after write, iclass 22, count 0 2006.174.00:41:01.64#ibcon#*before return 0, iclass 22, count 0 2006.174.00:41:01.64#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.174.00:41:01.64#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.174.00:41:01.64#ibcon#about to clear, iclass 22 cls_cnt 0 2006.174.00:41:01.64#ibcon#cleared, iclass 22 cls_cnt 0 2006.174.00:41:01.64$setupk4/ifdk4 2006.174.00:41:01.64$ifdk4/lo= 2006.174.00:41:01.64$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.174.00:41:01.64$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.174.00:41:01.64$ifdk4/patch= 2006.174.00:41:01.64$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.174.00:41:01.64$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.174.00:41:01.64$setupk4/!*+20s 2006.174.00:41:05.13#trakl#Source acquired 2006.174.00:41:06.13#flagr#flagr/antenna,acquired 2006.174.00:41:06.70#abcon#<5=/09 0.8 2.4 24.67 851003.3\r\n> 2006.174.00:41:06.72#abcon#{5=INTERFACE CLEAR} 2006.174.00:41:06.78#abcon#[5=S1D000X0/0*\r\n] 2006.174.00:41:16.15$setupk4/"tpicd 2006.174.00:41:16.15$setupk4/echo=off 2006.174.00:41:16.15$setupk4/xlog=off 2006.174.00:41:16.15:!2006.174.00:43:51 2006.174.00:43:51.00:preob 2006.174.00:43:52.14/onsource/TRACKING 2006.174.00:43:52.14:!2006.174.00:44:01 2006.174.00:44:01.00:"tape 2006.174.00:44:01.00:"st=record 2006.174.00:44:01.00:data_valid=on 2006.174.00:44:01.00:midob 2006.174.00:44:01.14/onsource/TRACKING 2006.174.00:44:01.14/wx/24.73,1003.4,83 2006.174.00:44:01.21/cable/+6.5049E-03 2006.174.00:44:02.30/va/01,07,usb,yes,34,37 2006.174.00:44:02.30/va/02,06,usb,yes,34,35 2006.174.00:44:02.30/va/03,05,usb,yes,43,45 2006.174.00:44:02.30/va/04,06,usb,yes,34,36 2006.174.00:44:02.30/va/05,04,usb,yes,27,28 2006.174.00:44:02.30/va/06,03,usb,yes,38,38 2006.174.00:44:02.30/va/07,04,usb,yes,31,32 2006.174.00:44:02.30/va/08,04,usb,yes,26,32 2006.174.00:44:02.53/valo/01,524.99,yes,locked 2006.174.00:44:02.53/valo/02,534.99,yes,locked 2006.174.00:44:02.53/valo/03,564.99,yes,locked 2006.174.00:44:02.53/valo/04,624.99,yes,locked 2006.174.00:44:02.53/valo/05,734.99,yes,locked 2006.174.00:44:02.53/valo/06,814.99,yes,locked 2006.174.00:44:02.53/valo/07,864.99,yes,locked 2006.174.00:44:02.53/valo/08,884.99,yes,locked 2006.174.00:44:03.62/vb/01,04,usb,yes,29,27 2006.174.00:44:03.62/vb/02,04,usb,yes,31,31 2006.174.00:44:03.62/vb/03,04,usb,yes,28,31 2006.174.00:44:03.62/vb/04,04,usb,yes,32,31 2006.174.00:44:03.62/vb/05,04,usb,yes,25,27 2006.174.00:44:03.62/vb/06,04,usb,yes,29,26 2006.174.00:44:03.62/vb/07,04,usb,yes,29,29 2006.174.00:44:03.62/vb/08,04,usb,yes,27,30 2006.174.00:44:03.85/vblo/01,629.99,yes,locked 2006.174.00:44:03.85/vblo/02,634.99,yes,locked 2006.174.00:44:03.85/vblo/03,649.99,yes,locked 2006.174.00:44:03.85/vblo/04,679.99,yes,locked 2006.174.00:44:03.85/vblo/05,709.99,yes,locked 2006.174.00:44:03.85/vblo/06,719.99,yes,locked 2006.174.00:44:03.85/vblo/07,734.99,yes,locked 2006.174.00:44:03.85/vblo/08,744.99,yes,locked 2006.174.00:44:04.00/vabw/8 2006.174.00:44:04.15/vbbw/8 2006.174.00:44:04.24/xfe/off,on,14.2 2006.174.00:44:04.62/ifatt/23,28,28,28 2006.174.00:44:05.07/fmout-gps/S +3.86E-07 2006.174.00:44:05.11:!2006.174.00:53:31 2006.174.00:53:31.00:data_valid=off 2006.174.00:53:31.00:"et 2006.174.00:53:31.00:!+3s 2006.174.00:53:34.01:"tape 2006.174.00:53:34.01:postob 2006.174.00:53:34.18/cable/+6.5052E-03 2006.174.00:53:34.18/wx/24.91,1003.4,81 2006.174.00:53:35.08/fmout-gps/S +3.82E-07 2006.174.00:53:35.08:scan_name=174-0057,jd0606,230 2006.174.00:53:35.08:source=cta26,033930.94,-014635.8,2000.0,ccw 2006.174.00:53:35.14#flagr#flagr/antenna,new-source 2006.174.00:53:36.14:checkk5 2006.174.00:53:36.54/chk_autoobs//k5ts1/ autoobs is running! 2006.174.00:53:36.92/chk_autoobs//k5ts2/ autoobs is running! 2006.174.00:53:37.34/chk_autoobs//k5ts3/ autoobs is running! 2006.174.00:53:37.73/chk_autoobs//k5ts4/ autoobs is running! 2006.174.00:53:38.44/chk_obsdata//k5ts1/T1740044??a.dat file size is correct (nominal:2280MB, actual:2280MB). 2006.174.00:53:39.14/chk_obsdata//k5ts2/T1740044??b.dat file size is correct (nominal:2280MB, actual:2280MB). 2006.174.00:53:39.86/chk_obsdata//k5ts3/T1740044??c.dat file size is correct (nominal:2280MB, actual:2280MB). 2006.174.00:53:40.58/chk_obsdata//k5ts4/T1740044??d.dat file size is correct (nominal:2280MB, actual:2280MB). 2006.174.00:53:41.31/k5log//k5ts1_log_newline 2006.174.00:53:42.01/k5log//k5ts2_log_newline 2006.174.00:53:42.72/k5log//k5ts3_log_newline 2006.174.00:53:43.43/k5log//k5ts4_log_newline 2006.174.00:53:43.45/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.174.00:53:43.45:setupk4=1 2006.174.00:53:43.45$setupk4/echo=on 2006.174.00:53:43.45$setupk4/pcalon 2006.174.00:53:43.45$pcalon/"no phase cal control is implemented here 2006.174.00:53:43.45$setupk4/"tpicd=stop 2006.174.00:53:43.45$setupk4/"rec=synch_on 2006.174.00:53:43.45$setupk4/"rec_mode=128 2006.174.00:53:43.45$setupk4/!* 2006.174.00:53:43.45$setupk4/recpk4 2006.174.00:53:43.45$recpk4/recpatch= 2006.174.00:53:43.46$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.174.00:53:43.46$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.174.00:53:43.46$setupk4/vck44 2006.174.00:53:43.46$vck44/valo=1,524.99 2006.174.00:53:43.46#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.174.00:53:43.46#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.174.00:53:43.46#ibcon#ireg 17 cls_cnt 0 2006.174.00:53:43.46#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.174.00:53:43.46#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.174.00:53:43.46#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.174.00:53:43.46#ibcon#enter wrdev, iclass 34, count 0 2006.174.00:53:43.46#ibcon#first serial, iclass 34, count 0 2006.174.00:53:43.46#ibcon#enter sib2, iclass 34, count 0 2006.174.00:53:43.46#ibcon#flushed, iclass 34, count 0 2006.174.00:53:43.46#ibcon#about to write, iclass 34, count 0 2006.174.00:53:43.46#ibcon#wrote, iclass 34, count 0 2006.174.00:53:43.46#ibcon#about to read 3, iclass 34, count 0 2006.174.00:53:43.48#ibcon#read 3, iclass 34, count 0 2006.174.00:53:43.48#ibcon#about to read 4, iclass 34, count 0 2006.174.00:53:43.48#ibcon#read 4, iclass 34, count 0 2006.174.00:53:43.48#ibcon#about to read 5, iclass 34, count 0 2006.174.00:53:43.48#ibcon#read 5, iclass 34, count 0 2006.174.00:53:43.48#ibcon#about to read 6, iclass 34, count 0 2006.174.00:53:43.48#ibcon#read 6, iclass 34, count 0 2006.174.00:53:43.48#ibcon#end of sib2, iclass 34, count 0 2006.174.00:53:43.48#ibcon#*mode == 0, iclass 34, count 0 2006.174.00:53:43.48#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.174.00:53:43.48#ibcon#[26=FRQ=01,524.99\r\n] 2006.174.00:53:43.48#ibcon#*before write, iclass 34, count 0 2006.174.00:53:43.48#ibcon#enter sib2, iclass 34, count 0 2006.174.00:53:43.48#ibcon#flushed, iclass 34, count 0 2006.174.00:53:43.48#ibcon#about to write, iclass 34, count 0 2006.174.00:53:43.48#ibcon#wrote, iclass 34, count 0 2006.174.00:53:43.48#ibcon#about to read 3, iclass 34, count 0 2006.174.00:53:43.53#ibcon#read 3, iclass 34, count 0 2006.174.00:53:43.53#ibcon#about to read 4, iclass 34, count 0 2006.174.00:53:43.53#ibcon#read 4, iclass 34, count 0 2006.174.00:53:43.53#ibcon#about to read 5, iclass 34, count 0 2006.174.00:53:43.53#ibcon#read 5, iclass 34, count 0 2006.174.00:53:43.53#ibcon#about to read 6, iclass 34, count 0 2006.174.00:53:43.53#ibcon#read 6, iclass 34, count 0 2006.174.00:53:43.53#ibcon#end of sib2, iclass 34, count 0 2006.174.00:53:43.53#ibcon#*after write, iclass 34, count 0 2006.174.00:53:43.53#ibcon#*before return 0, iclass 34, count 0 2006.174.00:53:43.53#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.174.00:53:43.53#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.174.00:53:43.53#ibcon#about to clear, iclass 34 cls_cnt 0 2006.174.00:53:43.53#ibcon#cleared, iclass 34 cls_cnt 0 2006.174.00:53:43.53$vck44/va=1,7 2006.174.00:53:43.53#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.174.00:53:43.53#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.174.00:53:43.53#ibcon#ireg 11 cls_cnt 2 2006.174.00:53:43.53#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.174.00:53:43.53#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.174.00:53:43.53#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.174.00:53:43.53#ibcon#enter wrdev, iclass 36, count 2 2006.174.00:53:43.53#ibcon#first serial, iclass 36, count 2 2006.174.00:53:43.53#ibcon#enter sib2, iclass 36, count 2 2006.174.00:53:43.53#ibcon#flushed, iclass 36, count 2 2006.174.00:53:43.53#ibcon#about to write, iclass 36, count 2 2006.174.00:53:43.53#ibcon#wrote, iclass 36, count 2 2006.174.00:53:43.53#ibcon#about to read 3, iclass 36, count 2 2006.174.00:53:43.55#ibcon#read 3, iclass 36, count 2 2006.174.00:53:43.55#ibcon#about to read 4, iclass 36, count 2 2006.174.00:53:43.55#ibcon#read 4, iclass 36, count 2 2006.174.00:53:43.55#ibcon#about to read 5, iclass 36, count 2 2006.174.00:53:43.55#ibcon#read 5, iclass 36, count 2 2006.174.00:53:43.55#ibcon#about to read 6, iclass 36, count 2 2006.174.00:53:43.55#ibcon#read 6, iclass 36, count 2 2006.174.00:53:43.55#ibcon#end of sib2, iclass 36, count 2 2006.174.00:53:43.55#ibcon#*mode == 0, iclass 36, count 2 2006.174.00:53:43.55#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.174.00:53:43.55#ibcon#[25=AT01-07\r\n] 2006.174.00:53:43.55#ibcon#*before write, iclass 36, count 2 2006.174.00:53:43.55#ibcon#enter sib2, iclass 36, count 2 2006.174.00:53:43.55#ibcon#flushed, iclass 36, count 2 2006.174.00:53:43.55#ibcon#about to write, iclass 36, count 2 2006.174.00:53:43.55#ibcon#wrote, iclass 36, count 2 2006.174.00:53:43.55#ibcon#about to read 3, iclass 36, count 2 2006.174.00:53:43.58#ibcon#read 3, iclass 36, count 2 2006.174.00:53:43.58#ibcon#about to read 4, iclass 36, count 2 2006.174.00:53:43.58#ibcon#read 4, iclass 36, count 2 2006.174.00:53:43.58#ibcon#about to read 5, iclass 36, count 2 2006.174.00:53:43.58#ibcon#read 5, iclass 36, count 2 2006.174.00:53:43.58#ibcon#about to read 6, iclass 36, count 2 2006.174.00:53:43.58#ibcon#read 6, iclass 36, count 2 2006.174.00:53:43.58#ibcon#end of sib2, iclass 36, count 2 2006.174.00:53:43.58#ibcon#*after write, iclass 36, count 2 2006.174.00:53:43.58#ibcon#*before return 0, iclass 36, count 2 2006.174.00:53:43.58#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.174.00:53:43.58#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.174.00:53:43.58#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.174.00:53:43.58#ibcon#ireg 7 cls_cnt 0 2006.174.00:53:43.58#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.174.00:53:43.70#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.174.00:53:43.70#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.174.00:53:43.70#ibcon#enter wrdev, iclass 36, count 0 2006.174.00:53:43.70#ibcon#first serial, iclass 36, count 0 2006.174.00:53:43.70#ibcon#enter sib2, iclass 36, count 0 2006.174.00:53:43.70#ibcon#flushed, iclass 36, count 0 2006.174.00:53:43.70#ibcon#about to write, iclass 36, count 0 2006.174.00:53:43.70#ibcon#wrote, iclass 36, count 0 2006.174.00:53:43.70#ibcon#about to read 3, iclass 36, count 0 2006.174.00:53:43.72#ibcon#read 3, iclass 36, count 0 2006.174.00:53:43.72#ibcon#about to read 4, iclass 36, count 0 2006.174.00:53:43.72#ibcon#read 4, iclass 36, count 0 2006.174.00:53:43.72#ibcon#about to read 5, iclass 36, count 0 2006.174.00:53:43.72#ibcon#read 5, iclass 36, count 0 2006.174.00:53:43.72#ibcon#about to read 6, iclass 36, count 0 2006.174.00:53:43.72#ibcon#read 6, iclass 36, count 0 2006.174.00:53:43.72#ibcon#end of sib2, iclass 36, count 0 2006.174.00:53:43.72#ibcon#*mode == 0, iclass 36, count 0 2006.174.00:53:43.72#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.174.00:53:43.72#ibcon#[25=USB\r\n] 2006.174.00:53:43.72#ibcon#*before write, iclass 36, count 0 2006.174.00:53:43.72#ibcon#enter sib2, iclass 36, count 0 2006.174.00:53:43.72#ibcon#flushed, iclass 36, count 0 2006.174.00:53:43.72#ibcon#about to write, iclass 36, count 0 2006.174.00:53:43.72#ibcon#wrote, iclass 36, count 0 2006.174.00:53:43.72#ibcon#about to read 3, iclass 36, count 0 2006.174.00:53:43.75#ibcon#read 3, iclass 36, count 0 2006.174.00:53:43.75#ibcon#about to read 4, iclass 36, count 0 2006.174.00:53:43.75#ibcon#read 4, iclass 36, count 0 2006.174.00:53:43.75#ibcon#about to read 5, iclass 36, count 0 2006.174.00:53:43.75#ibcon#read 5, iclass 36, count 0 2006.174.00:53:43.75#ibcon#about to read 6, iclass 36, count 0 2006.174.00:53:43.75#ibcon#read 6, iclass 36, count 0 2006.174.00:53:43.75#ibcon#end of sib2, iclass 36, count 0 2006.174.00:53:43.75#ibcon#*after write, iclass 36, count 0 2006.174.00:53:43.75#ibcon#*before return 0, iclass 36, count 0 2006.174.00:53:43.75#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.174.00:53:43.75#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.174.00:53:43.75#ibcon#about to clear, iclass 36 cls_cnt 0 2006.174.00:53:43.75#ibcon#cleared, iclass 36 cls_cnt 0 2006.174.00:53:43.75$vck44/valo=2,534.99 2006.174.00:53:43.75#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.174.00:53:43.75#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.174.00:53:43.75#ibcon#ireg 17 cls_cnt 0 2006.174.00:53:43.75#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.174.00:53:43.75#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.174.00:53:43.75#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.174.00:53:43.75#ibcon#enter wrdev, iclass 38, count 0 2006.174.00:53:43.75#ibcon#first serial, iclass 38, count 0 2006.174.00:53:43.75#ibcon#enter sib2, iclass 38, count 0 2006.174.00:53:43.75#ibcon#flushed, iclass 38, count 0 2006.174.00:53:43.75#ibcon#about to write, iclass 38, count 0 2006.174.00:53:43.75#ibcon#wrote, iclass 38, count 0 2006.174.00:53:43.75#ibcon#about to read 3, iclass 38, count 0 2006.174.00:53:43.77#ibcon#read 3, iclass 38, count 0 2006.174.00:53:43.77#ibcon#about to read 4, iclass 38, count 0 2006.174.00:53:43.77#ibcon#read 4, iclass 38, count 0 2006.174.00:53:43.77#ibcon#about to read 5, iclass 38, count 0 2006.174.00:53:43.77#ibcon#read 5, iclass 38, count 0 2006.174.00:53:43.77#ibcon#about to read 6, iclass 38, count 0 2006.174.00:53:43.77#ibcon#read 6, iclass 38, count 0 2006.174.00:53:43.77#ibcon#end of sib2, iclass 38, count 0 2006.174.00:53:43.77#ibcon#*mode == 0, iclass 38, count 0 2006.174.00:53:43.77#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.174.00:53:43.77#ibcon#[26=FRQ=02,534.99\r\n] 2006.174.00:53:43.77#ibcon#*before write, iclass 38, count 0 2006.174.00:53:43.77#ibcon#enter sib2, iclass 38, count 0 2006.174.00:53:43.77#ibcon#flushed, iclass 38, count 0 2006.174.00:53:43.77#ibcon#about to write, iclass 38, count 0 2006.174.00:53:43.77#ibcon#wrote, iclass 38, count 0 2006.174.00:53:43.77#ibcon#about to read 3, iclass 38, count 0 2006.174.00:53:43.81#ibcon#read 3, iclass 38, count 0 2006.174.00:53:43.81#ibcon#about to read 4, iclass 38, count 0 2006.174.00:53:43.81#ibcon#read 4, iclass 38, count 0 2006.174.00:53:43.81#ibcon#about to read 5, iclass 38, count 0 2006.174.00:53:43.81#ibcon#read 5, iclass 38, count 0 2006.174.00:53:43.81#ibcon#about to read 6, iclass 38, count 0 2006.174.00:53:43.81#ibcon#read 6, iclass 38, count 0 2006.174.00:53:43.81#ibcon#end of sib2, iclass 38, count 0 2006.174.00:53:43.81#ibcon#*after write, iclass 38, count 0 2006.174.00:53:43.81#ibcon#*before return 0, iclass 38, count 0 2006.174.00:53:43.81#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.174.00:53:43.81#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.174.00:53:43.81#ibcon#about to clear, iclass 38 cls_cnt 0 2006.174.00:53:43.81#ibcon#cleared, iclass 38 cls_cnt 0 2006.174.00:53:43.81$vck44/va=2,6 2006.174.00:53:43.81#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.174.00:53:43.81#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.174.00:53:43.81#ibcon#ireg 11 cls_cnt 2 2006.174.00:53:43.81#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.174.00:53:43.87#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.174.00:53:43.87#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.174.00:53:43.87#ibcon#enter wrdev, iclass 40, count 2 2006.174.00:53:43.87#ibcon#first serial, iclass 40, count 2 2006.174.00:53:43.87#ibcon#enter sib2, iclass 40, count 2 2006.174.00:53:43.87#ibcon#flushed, iclass 40, count 2 2006.174.00:53:43.87#ibcon#about to write, iclass 40, count 2 2006.174.00:53:43.87#ibcon#wrote, iclass 40, count 2 2006.174.00:53:43.87#ibcon#about to read 3, iclass 40, count 2 2006.174.00:53:43.89#ibcon#read 3, iclass 40, count 2 2006.174.00:53:43.89#ibcon#about to read 4, iclass 40, count 2 2006.174.00:53:43.89#ibcon#read 4, iclass 40, count 2 2006.174.00:53:43.89#ibcon#about to read 5, iclass 40, count 2 2006.174.00:53:43.89#ibcon#read 5, iclass 40, count 2 2006.174.00:53:43.89#ibcon#about to read 6, iclass 40, count 2 2006.174.00:53:43.89#ibcon#read 6, iclass 40, count 2 2006.174.00:53:43.89#ibcon#end of sib2, iclass 40, count 2 2006.174.00:53:43.89#ibcon#*mode == 0, iclass 40, count 2 2006.174.00:53:43.89#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.174.00:53:43.89#ibcon#[25=AT02-06\r\n] 2006.174.00:53:43.89#ibcon#*before write, iclass 40, count 2 2006.174.00:53:43.89#ibcon#enter sib2, iclass 40, count 2 2006.174.00:53:43.89#ibcon#flushed, iclass 40, count 2 2006.174.00:53:43.89#ibcon#about to write, iclass 40, count 2 2006.174.00:53:43.89#ibcon#wrote, iclass 40, count 2 2006.174.00:53:43.89#ibcon#about to read 3, iclass 40, count 2 2006.174.00:53:43.92#ibcon#read 3, iclass 40, count 2 2006.174.00:53:43.92#ibcon#about to read 4, iclass 40, count 2 2006.174.00:53:43.92#ibcon#read 4, iclass 40, count 2 2006.174.00:53:43.92#ibcon#about to read 5, iclass 40, count 2 2006.174.00:53:43.92#ibcon#read 5, iclass 40, count 2 2006.174.00:53:43.92#ibcon#about to read 6, iclass 40, count 2 2006.174.00:53:43.92#ibcon#read 6, iclass 40, count 2 2006.174.00:53:43.92#ibcon#end of sib2, iclass 40, count 2 2006.174.00:53:43.92#ibcon#*after write, iclass 40, count 2 2006.174.00:53:43.92#ibcon#*before return 0, iclass 40, count 2 2006.174.00:53:43.92#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.174.00:53:43.92#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.174.00:53:43.92#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.174.00:53:43.92#ibcon#ireg 7 cls_cnt 0 2006.174.00:53:43.92#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.174.00:53:44.04#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.174.00:53:44.04#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.174.00:53:44.04#ibcon#enter wrdev, iclass 40, count 0 2006.174.00:53:44.04#ibcon#first serial, iclass 40, count 0 2006.174.00:53:44.04#ibcon#enter sib2, iclass 40, count 0 2006.174.00:53:44.04#ibcon#flushed, iclass 40, count 0 2006.174.00:53:44.04#ibcon#about to write, iclass 40, count 0 2006.174.00:53:44.04#ibcon#wrote, iclass 40, count 0 2006.174.00:53:44.04#ibcon#about to read 3, iclass 40, count 0 2006.174.00:53:44.06#ibcon#read 3, iclass 40, count 0 2006.174.00:53:44.06#ibcon#about to read 4, iclass 40, count 0 2006.174.00:53:44.06#ibcon#read 4, iclass 40, count 0 2006.174.00:53:44.06#ibcon#about to read 5, iclass 40, count 0 2006.174.00:53:44.06#ibcon#read 5, iclass 40, count 0 2006.174.00:53:44.06#ibcon#about to read 6, iclass 40, count 0 2006.174.00:53:44.06#ibcon#read 6, iclass 40, count 0 2006.174.00:53:44.06#ibcon#end of sib2, iclass 40, count 0 2006.174.00:53:44.06#ibcon#*mode == 0, iclass 40, count 0 2006.174.00:53:44.06#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.174.00:53:44.06#ibcon#[25=USB\r\n] 2006.174.00:53:44.06#ibcon#*before write, iclass 40, count 0 2006.174.00:53:44.06#ibcon#enter sib2, iclass 40, count 0 2006.174.00:53:44.06#ibcon#flushed, iclass 40, count 0 2006.174.00:53:44.06#ibcon#about to write, iclass 40, count 0 2006.174.00:53:44.06#ibcon#wrote, iclass 40, count 0 2006.174.00:53:44.06#ibcon#about to read 3, iclass 40, count 0 2006.174.00:53:44.09#ibcon#read 3, iclass 40, count 0 2006.174.00:53:44.09#ibcon#about to read 4, iclass 40, count 0 2006.174.00:53:44.09#ibcon#read 4, iclass 40, count 0 2006.174.00:53:44.09#ibcon#about to read 5, iclass 40, count 0 2006.174.00:53:44.09#ibcon#read 5, iclass 40, count 0 2006.174.00:53:44.09#ibcon#about to read 6, iclass 40, count 0 2006.174.00:53:44.09#ibcon#read 6, iclass 40, count 0 2006.174.00:53:44.09#ibcon#end of sib2, iclass 40, count 0 2006.174.00:53:44.09#ibcon#*after write, iclass 40, count 0 2006.174.00:53:44.09#ibcon#*before return 0, iclass 40, count 0 2006.174.00:53:44.09#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.174.00:53:44.09#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.174.00:53:44.09#ibcon#about to clear, iclass 40 cls_cnt 0 2006.174.00:53:44.09#ibcon#cleared, iclass 40 cls_cnt 0 2006.174.00:53:44.09$vck44/valo=3,564.99 2006.174.00:53:44.09#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.174.00:53:44.09#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.174.00:53:44.09#ibcon#ireg 17 cls_cnt 0 2006.174.00:53:44.09#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.174.00:53:44.09#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.174.00:53:44.09#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.174.00:53:44.09#ibcon#enter wrdev, iclass 4, count 0 2006.174.00:53:44.09#ibcon#first serial, iclass 4, count 0 2006.174.00:53:44.09#ibcon#enter sib2, iclass 4, count 0 2006.174.00:53:44.09#ibcon#flushed, iclass 4, count 0 2006.174.00:53:44.09#ibcon#about to write, iclass 4, count 0 2006.174.00:53:44.09#ibcon#wrote, iclass 4, count 0 2006.174.00:53:44.09#ibcon#about to read 3, iclass 4, count 0 2006.174.00:53:44.11#ibcon#read 3, iclass 4, count 0 2006.174.00:53:44.11#ibcon#about to read 4, iclass 4, count 0 2006.174.00:53:44.11#ibcon#read 4, iclass 4, count 0 2006.174.00:53:44.11#ibcon#about to read 5, iclass 4, count 0 2006.174.00:53:44.11#ibcon#read 5, iclass 4, count 0 2006.174.00:53:44.11#ibcon#about to read 6, iclass 4, count 0 2006.174.00:53:44.11#ibcon#read 6, iclass 4, count 0 2006.174.00:53:44.11#ibcon#end of sib2, iclass 4, count 0 2006.174.00:53:44.11#ibcon#*mode == 0, iclass 4, count 0 2006.174.00:53:44.11#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.174.00:53:44.11#ibcon#[26=FRQ=03,564.99\r\n] 2006.174.00:53:44.11#ibcon#*before write, iclass 4, count 0 2006.174.00:53:44.11#ibcon#enter sib2, iclass 4, count 0 2006.174.00:53:44.11#ibcon#flushed, iclass 4, count 0 2006.174.00:53:44.11#ibcon#about to write, iclass 4, count 0 2006.174.00:53:44.11#ibcon#wrote, iclass 4, count 0 2006.174.00:53:44.11#ibcon#about to read 3, iclass 4, count 0 2006.174.00:53:44.15#ibcon#read 3, iclass 4, count 0 2006.174.00:53:44.15#ibcon#about to read 4, iclass 4, count 0 2006.174.00:53:44.15#ibcon#read 4, iclass 4, count 0 2006.174.00:53:44.15#ibcon#about to read 5, iclass 4, count 0 2006.174.00:53:44.15#ibcon#read 5, iclass 4, count 0 2006.174.00:53:44.15#ibcon#about to read 6, iclass 4, count 0 2006.174.00:53:44.15#ibcon#read 6, iclass 4, count 0 2006.174.00:53:44.15#ibcon#end of sib2, iclass 4, count 0 2006.174.00:53:44.15#ibcon#*after write, iclass 4, count 0 2006.174.00:53:44.15#ibcon#*before return 0, iclass 4, count 0 2006.174.00:53:44.15#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.174.00:53:44.15#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.174.00:53:44.15#ibcon#about to clear, iclass 4 cls_cnt 0 2006.174.00:53:44.15#ibcon#cleared, iclass 4 cls_cnt 0 2006.174.00:53:44.15$vck44/va=3,5 2006.174.00:53:44.15#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.174.00:53:44.15#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.174.00:53:44.15#ibcon#ireg 11 cls_cnt 2 2006.174.00:53:44.15#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.174.00:53:44.21#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.174.00:53:44.21#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.174.00:53:44.21#ibcon#enter wrdev, iclass 6, count 2 2006.174.00:53:44.21#ibcon#first serial, iclass 6, count 2 2006.174.00:53:44.21#ibcon#enter sib2, iclass 6, count 2 2006.174.00:53:44.21#ibcon#flushed, iclass 6, count 2 2006.174.00:53:44.21#ibcon#about to write, iclass 6, count 2 2006.174.00:53:44.21#ibcon#wrote, iclass 6, count 2 2006.174.00:53:44.21#ibcon#about to read 3, iclass 6, count 2 2006.174.00:53:44.23#ibcon#read 3, iclass 6, count 2 2006.174.00:53:44.23#ibcon#about to read 4, iclass 6, count 2 2006.174.00:53:44.23#ibcon#read 4, iclass 6, count 2 2006.174.00:53:44.23#ibcon#about to read 5, iclass 6, count 2 2006.174.00:53:44.23#ibcon#read 5, iclass 6, count 2 2006.174.00:53:44.23#ibcon#about to read 6, iclass 6, count 2 2006.174.00:53:44.23#ibcon#read 6, iclass 6, count 2 2006.174.00:53:44.23#ibcon#end of sib2, iclass 6, count 2 2006.174.00:53:44.23#ibcon#*mode == 0, iclass 6, count 2 2006.174.00:53:44.23#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.174.00:53:44.23#ibcon#[25=AT03-05\r\n] 2006.174.00:53:44.23#ibcon#*before write, iclass 6, count 2 2006.174.00:53:44.23#ibcon#enter sib2, iclass 6, count 2 2006.174.00:53:44.23#ibcon#flushed, iclass 6, count 2 2006.174.00:53:44.23#ibcon#about to write, iclass 6, count 2 2006.174.00:53:44.23#ibcon#wrote, iclass 6, count 2 2006.174.00:53:44.23#ibcon#about to read 3, iclass 6, count 2 2006.174.00:53:44.26#ibcon#read 3, iclass 6, count 2 2006.174.00:53:44.26#ibcon#about to read 4, iclass 6, count 2 2006.174.00:53:44.26#ibcon#read 4, iclass 6, count 2 2006.174.00:53:44.26#ibcon#about to read 5, iclass 6, count 2 2006.174.00:53:44.26#ibcon#read 5, iclass 6, count 2 2006.174.00:53:44.26#ibcon#about to read 6, iclass 6, count 2 2006.174.00:53:44.26#ibcon#read 6, iclass 6, count 2 2006.174.00:53:44.26#ibcon#end of sib2, iclass 6, count 2 2006.174.00:53:44.26#ibcon#*after write, iclass 6, count 2 2006.174.00:53:44.26#ibcon#*before return 0, iclass 6, count 2 2006.174.00:53:44.26#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.174.00:53:44.26#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.174.00:53:44.26#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.174.00:53:44.26#ibcon#ireg 7 cls_cnt 0 2006.174.00:53:44.26#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.174.00:53:44.38#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.174.00:53:44.38#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.174.00:53:44.38#ibcon#enter wrdev, iclass 6, count 0 2006.174.00:53:44.38#ibcon#first serial, iclass 6, count 0 2006.174.00:53:44.38#ibcon#enter sib2, iclass 6, count 0 2006.174.00:53:44.38#ibcon#flushed, iclass 6, count 0 2006.174.00:53:44.38#ibcon#about to write, iclass 6, count 0 2006.174.00:53:44.38#ibcon#wrote, iclass 6, count 0 2006.174.00:53:44.38#ibcon#about to read 3, iclass 6, count 0 2006.174.00:53:44.40#ibcon#read 3, iclass 6, count 0 2006.174.00:53:44.40#ibcon#about to read 4, iclass 6, count 0 2006.174.00:53:44.40#ibcon#read 4, iclass 6, count 0 2006.174.00:53:44.40#ibcon#about to read 5, iclass 6, count 0 2006.174.00:53:44.40#ibcon#read 5, iclass 6, count 0 2006.174.00:53:44.40#ibcon#about to read 6, iclass 6, count 0 2006.174.00:53:44.40#ibcon#read 6, iclass 6, count 0 2006.174.00:53:44.40#ibcon#end of sib2, iclass 6, count 0 2006.174.00:53:44.40#ibcon#*mode == 0, iclass 6, count 0 2006.174.00:53:44.40#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.174.00:53:44.40#ibcon#[25=USB\r\n] 2006.174.00:53:44.40#ibcon#*before write, iclass 6, count 0 2006.174.00:53:44.40#ibcon#enter sib2, iclass 6, count 0 2006.174.00:53:44.40#ibcon#flushed, iclass 6, count 0 2006.174.00:53:44.40#ibcon#about to write, iclass 6, count 0 2006.174.00:53:44.40#ibcon#wrote, iclass 6, count 0 2006.174.00:53:44.40#ibcon#about to read 3, iclass 6, count 0 2006.174.00:53:44.43#ibcon#read 3, iclass 6, count 0 2006.174.00:53:44.43#ibcon#about to read 4, iclass 6, count 0 2006.174.00:53:44.43#ibcon#read 4, iclass 6, count 0 2006.174.00:53:44.43#ibcon#about to read 5, iclass 6, count 0 2006.174.00:53:44.43#ibcon#read 5, iclass 6, count 0 2006.174.00:53:44.43#ibcon#about to read 6, iclass 6, count 0 2006.174.00:53:44.43#ibcon#read 6, iclass 6, count 0 2006.174.00:53:44.43#ibcon#end of sib2, iclass 6, count 0 2006.174.00:53:44.43#ibcon#*after write, iclass 6, count 0 2006.174.00:53:44.43#ibcon#*before return 0, iclass 6, count 0 2006.174.00:53:44.43#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.174.00:53:44.43#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.174.00:53:44.43#ibcon#about to clear, iclass 6 cls_cnt 0 2006.174.00:53:44.43#ibcon#cleared, iclass 6 cls_cnt 0 2006.174.00:53:44.43$vck44/valo=4,624.99 2006.174.00:53:44.43#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.174.00:53:44.43#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.174.00:53:44.43#ibcon#ireg 17 cls_cnt 0 2006.174.00:53:44.43#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.174.00:53:44.43#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.174.00:53:44.43#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.174.00:53:44.43#ibcon#enter wrdev, iclass 10, count 0 2006.174.00:53:44.43#ibcon#first serial, iclass 10, count 0 2006.174.00:53:44.43#ibcon#enter sib2, iclass 10, count 0 2006.174.00:53:44.43#ibcon#flushed, iclass 10, count 0 2006.174.00:53:44.43#ibcon#about to write, iclass 10, count 0 2006.174.00:53:44.43#ibcon#wrote, iclass 10, count 0 2006.174.00:53:44.43#ibcon#about to read 3, iclass 10, count 0 2006.174.00:53:44.45#ibcon#read 3, iclass 10, count 0 2006.174.00:53:44.45#ibcon#about to read 4, iclass 10, count 0 2006.174.00:53:44.45#ibcon#read 4, iclass 10, count 0 2006.174.00:53:44.45#ibcon#about to read 5, iclass 10, count 0 2006.174.00:53:44.45#ibcon#read 5, iclass 10, count 0 2006.174.00:53:44.45#ibcon#about to read 6, iclass 10, count 0 2006.174.00:53:44.45#ibcon#read 6, iclass 10, count 0 2006.174.00:53:44.45#ibcon#end of sib2, iclass 10, count 0 2006.174.00:53:44.45#ibcon#*mode == 0, iclass 10, count 0 2006.174.00:53:44.45#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.174.00:53:44.45#ibcon#[26=FRQ=04,624.99\r\n] 2006.174.00:53:44.45#ibcon#*before write, iclass 10, count 0 2006.174.00:53:44.45#ibcon#enter sib2, iclass 10, count 0 2006.174.00:53:44.45#ibcon#flushed, iclass 10, count 0 2006.174.00:53:44.45#ibcon#about to write, iclass 10, count 0 2006.174.00:53:44.45#ibcon#wrote, iclass 10, count 0 2006.174.00:53:44.45#ibcon#about to read 3, iclass 10, count 0 2006.174.00:53:44.49#ibcon#read 3, iclass 10, count 0 2006.174.00:53:44.49#ibcon#about to read 4, iclass 10, count 0 2006.174.00:53:44.49#ibcon#read 4, iclass 10, count 0 2006.174.00:53:44.49#ibcon#about to read 5, iclass 10, count 0 2006.174.00:53:44.49#ibcon#read 5, iclass 10, count 0 2006.174.00:53:44.49#ibcon#about to read 6, iclass 10, count 0 2006.174.00:53:44.49#ibcon#read 6, iclass 10, count 0 2006.174.00:53:44.49#ibcon#end of sib2, iclass 10, count 0 2006.174.00:53:44.49#ibcon#*after write, iclass 10, count 0 2006.174.00:53:44.49#ibcon#*before return 0, iclass 10, count 0 2006.174.00:53:44.49#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.174.00:53:44.49#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.174.00:53:44.49#ibcon#about to clear, iclass 10 cls_cnt 0 2006.174.00:53:44.49#ibcon#cleared, iclass 10 cls_cnt 0 2006.174.00:53:44.49$vck44/va=4,6 2006.174.00:53:44.49#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.174.00:53:44.49#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.174.00:53:44.49#ibcon#ireg 11 cls_cnt 2 2006.174.00:53:44.49#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.174.00:53:44.55#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.174.00:53:44.55#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.174.00:53:44.55#ibcon#enter wrdev, iclass 12, count 2 2006.174.00:53:44.55#ibcon#first serial, iclass 12, count 2 2006.174.00:53:44.55#ibcon#enter sib2, iclass 12, count 2 2006.174.00:53:44.55#ibcon#flushed, iclass 12, count 2 2006.174.00:53:44.55#ibcon#about to write, iclass 12, count 2 2006.174.00:53:44.55#ibcon#wrote, iclass 12, count 2 2006.174.00:53:44.55#ibcon#about to read 3, iclass 12, count 2 2006.174.00:53:44.57#ibcon#read 3, iclass 12, count 2 2006.174.00:53:44.57#ibcon#about to read 4, iclass 12, count 2 2006.174.00:53:44.57#ibcon#read 4, iclass 12, count 2 2006.174.00:53:44.57#ibcon#about to read 5, iclass 12, count 2 2006.174.00:53:44.57#ibcon#read 5, iclass 12, count 2 2006.174.00:53:44.57#ibcon#about to read 6, iclass 12, count 2 2006.174.00:53:44.57#ibcon#read 6, iclass 12, count 2 2006.174.00:53:44.57#ibcon#end of sib2, iclass 12, count 2 2006.174.00:53:44.57#ibcon#*mode == 0, iclass 12, count 2 2006.174.00:53:44.57#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.174.00:53:44.57#ibcon#[25=AT04-06\r\n] 2006.174.00:53:44.57#ibcon#*before write, iclass 12, count 2 2006.174.00:53:44.57#ibcon#enter sib2, iclass 12, count 2 2006.174.00:53:44.57#ibcon#flushed, iclass 12, count 2 2006.174.00:53:44.57#ibcon#about to write, iclass 12, count 2 2006.174.00:53:44.57#ibcon#wrote, iclass 12, count 2 2006.174.00:53:44.57#ibcon#about to read 3, iclass 12, count 2 2006.174.00:53:44.60#ibcon#read 3, iclass 12, count 2 2006.174.00:53:44.60#ibcon#about to read 4, iclass 12, count 2 2006.174.00:53:44.60#ibcon#read 4, iclass 12, count 2 2006.174.00:53:44.60#ibcon#about to read 5, iclass 12, count 2 2006.174.00:53:44.60#ibcon#read 5, iclass 12, count 2 2006.174.00:53:44.60#ibcon#about to read 6, iclass 12, count 2 2006.174.00:53:44.60#ibcon#read 6, iclass 12, count 2 2006.174.00:53:44.60#ibcon#end of sib2, iclass 12, count 2 2006.174.00:53:44.60#ibcon#*after write, iclass 12, count 2 2006.174.00:53:44.60#ibcon#*before return 0, iclass 12, count 2 2006.174.00:53:44.60#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.174.00:53:44.60#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.174.00:53:44.60#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.174.00:53:44.60#ibcon#ireg 7 cls_cnt 0 2006.174.00:53:44.60#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.174.00:53:44.72#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.174.00:53:44.72#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.174.00:53:44.72#ibcon#enter wrdev, iclass 12, count 0 2006.174.00:53:44.72#ibcon#first serial, iclass 12, count 0 2006.174.00:53:44.72#ibcon#enter sib2, iclass 12, count 0 2006.174.00:53:44.72#ibcon#flushed, iclass 12, count 0 2006.174.00:53:44.72#ibcon#about to write, iclass 12, count 0 2006.174.00:53:44.72#ibcon#wrote, iclass 12, count 0 2006.174.00:53:44.72#ibcon#about to read 3, iclass 12, count 0 2006.174.00:53:44.74#ibcon#read 3, iclass 12, count 0 2006.174.00:53:44.74#ibcon#about to read 4, iclass 12, count 0 2006.174.00:53:44.74#ibcon#read 4, iclass 12, count 0 2006.174.00:53:44.74#ibcon#about to read 5, iclass 12, count 0 2006.174.00:53:44.74#ibcon#read 5, iclass 12, count 0 2006.174.00:53:44.74#ibcon#about to read 6, iclass 12, count 0 2006.174.00:53:44.74#ibcon#read 6, iclass 12, count 0 2006.174.00:53:44.74#ibcon#end of sib2, iclass 12, count 0 2006.174.00:53:44.74#ibcon#*mode == 0, iclass 12, count 0 2006.174.00:53:44.74#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.174.00:53:44.74#ibcon#[25=USB\r\n] 2006.174.00:53:44.74#ibcon#*before write, iclass 12, count 0 2006.174.00:53:44.74#ibcon#enter sib2, iclass 12, count 0 2006.174.00:53:44.74#ibcon#flushed, iclass 12, count 0 2006.174.00:53:44.74#ibcon#about to write, iclass 12, count 0 2006.174.00:53:44.74#ibcon#wrote, iclass 12, count 0 2006.174.00:53:44.74#ibcon#about to read 3, iclass 12, count 0 2006.174.00:53:44.77#ibcon#read 3, iclass 12, count 0 2006.174.00:53:44.77#ibcon#about to read 4, iclass 12, count 0 2006.174.00:53:44.77#ibcon#read 4, iclass 12, count 0 2006.174.00:53:44.77#ibcon#about to read 5, iclass 12, count 0 2006.174.00:53:44.77#ibcon#read 5, iclass 12, count 0 2006.174.00:53:44.77#ibcon#about to read 6, iclass 12, count 0 2006.174.00:53:44.77#ibcon#read 6, iclass 12, count 0 2006.174.00:53:44.77#ibcon#end of sib2, iclass 12, count 0 2006.174.00:53:44.77#ibcon#*after write, iclass 12, count 0 2006.174.00:53:44.77#ibcon#*before return 0, iclass 12, count 0 2006.174.00:53:44.77#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.174.00:53:44.77#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.174.00:53:44.77#ibcon#about to clear, iclass 12 cls_cnt 0 2006.174.00:53:44.77#ibcon#cleared, iclass 12 cls_cnt 0 2006.174.00:53:44.77$vck44/valo=5,734.99 2006.174.00:53:44.77#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.174.00:53:44.77#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.174.00:53:44.77#ibcon#ireg 17 cls_cnt 0 2006.174.00:53:44.77#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.174.00:53:44.77#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.174.00:53:44.77#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.174.00:53:44.77#ibcon#enter wrdev, iclass 14, count 0 2006.174.00:53:44.77#ibcon#first serial, iclass 14, count 0 2006.174.00:53:44.77#ibcon#enter sib2, iclass 14, count 0 2006.174.00:53:44.77#ibcon#flushed, iclass 14, count 0 2006.174.00:53:44.77#ibcon#about to write, iclass 14, count 0 2006.174.00:53:44.77#ibcon#wrote, iclass 14, count 0 2006.174.00:53:44.77#ibcon#about to read 3, iclass 14, count 0 2006.174.00:53:44.79#ibcon#read 3, iclass 14, count 0 2006.174.00:53:44.79#ibcon#about to read 4, iclass 14, count 0 2006.174.00:53:44.79#ibcon#read 4, iclass 14, count 0 2006.174.00:53:44.79#ibcon#about to read 5, iclass 14, count 0 2006.174.00:53:44.79#ibcon#read 5, iclass 14, count 0 2006.174.00:53:44.79#ibcon#about to read 6, iclass 14, count 0 2006.174.00:53:44.79#ibcon#read 6, iclass 14, count 0 2006.174.00:53:44.79#ibcon#end of sib2, iclass 14, count 0 2006.174.00:53:44.79#ibcon#*mode == 0, iclass 14, count 0 2006.174.00:53:44.79#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.174.00:53:44.79#ibcon#[26=FRQ=05,734.99\r\n] 2006.174.00:53:44.79#ibcon#*before write, iclass 14, count 0 2006.174.00:53:44.79#ibcon#enter sib2, iclass 14, count 0 2006.174.00:53:44.79#ibcon#flushed, iclass 14, count 0 2006.174.00:53:44.79#ibcon#about to write, iclass 14, count 0 2006.174.00:53:44.79#ibcon#wrote, iclass 14, count 0 2006.174.00:53:44.79#ibcon#about to read 3, iclass 14, count 0 2006.174.00:53:44.83#ibcon#read 3, iclass 14, count 0 2006.174.00:53:44.83#ibcon#about to read 4, iclass 14, count 0 2006.174.00:53:44.83#ibcon#read 4, iclass 14, count 0 2006.174.00:53:44.83#ibcon#about to read 5, iclass 14, count 0 2006.174.00:53:44.83#ibcon#read 5, iclass 14, count 0 2006.174.00:53:44.83#ibcon#about to read 6, iclass 14, count 0 2006.174.00:53:44.83#ibcon#read 6, iclass 14, count 0 2006.174.00:53:44.83#ibcon#end of sib2, iclass 14, count 0 2006.174.00:53:44.83#ibcon#*after write, iclass 14, count 0 2006.174.00:53:44.83#ibcon#*before return 0, iclass 14, count 0 2006.174.00:53:44.83#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.174.00:53:44.83#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.174.00:53:44.83#ibcon#about to clear, iclass 14 cls_cnt 0 2006.174.00:53:44.83#ibcon#cleared, iclass 14 cls_cnt 0 2006.174.00:53:44.83$vck44/va=5,4 2006.174.00:53:44.83#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.174.00:53:44.83#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.174.00:53:44.83#ibcon#ireg 11 cls_cnt 2 2006.174.00:53:44.83#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.174.00:53:44.89#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.174.00:53:44.89#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.174.00:53:44.89#ibcon#enter wrdev, iclass 16, count 2 2006.174.00:53:44.89#ibcon#first serial, iclass 16, count 2 2006.174.00:53:44.89#ibcon#enter sib2, iclass 16, count 2 2006.174.00:53:44.89#ibcon#flushed, iclass 16, count 2 2006.174.00:53:44.89#ibcon#about to write, iclass 16, count 2 2006.174.00:53:44.89#ibcon#wrote, iclass 16, count 2 2006.174.00:53:44.89#ibcon#about to read 3, iclass 16, count 2 2006.174.00:53:44.91#ibcon#read 3, iclass 16, count 2 2006.174.00:53:44.91#ibcon#about to read 4, iclass 16, count 2 2006.174.00:53:44.91#ibcon#read 4, iclass 16, count 2 2006.174.00:53:44.91#ibcon#about to read 5, iclass 16, count 2 2006.174.00:53:44.91#ibcon#read 5, iclass 16, count 2 2006.174.00:53:44.91#ibcon#about to read 6, iclass 16, count 2 2006.174.00:53:44.91#ibcon#read 6, iclass 16, count 2 2006.174.00:53:44.91#ibcon#end of sib2, iclass 16, count 2 2006.174.00:53:44.91#ibcon#*mode == 0, iclass 16, count 2 2006.174.00:53:44.91#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.174.00:53:44.91#ibcon#[25=AT05-04\r\n] 2006.174.00:53:44.91#ibcon#*before write, iclass 16, count 2 2006.174.00:53:44.91#ibcon#enter sib2, iclass 16, count 2 2006.174.00:53:44.91#ibcon#flushed, iclass 16, count 2 2006.174.00:53:44.91#ibcon#about to write, iclass 16, count 2 2006.174.00:53:44.91#ibcon#wrote, iclass 16, count 2 2006.174.00:53:44.91#ibcon#about to read 3, iclass 16, count 2 2006.174.00:53:44.94#ibcon#read 3, iclass 16, count 2 2006.174.00:53:44.94#ibcon#about to read 4, iclass 16, count 2 2006.174.00:53:44.94#ibcon#read 4, iclass 16, count 2 2006.174.00:53:44.94#ibcon#about to read 5, iclass 16, count 2 2006.174.00:53:44.94#ibcon#read 5, iclass 16, count 2 2006.174.00:53:44.94#ibcon#about to read 6, iclass 16, count 2 2006.174.00:53:44.94#ibcon#read 6, iclass 16, count 2 2006.174.00:53:44.94#ibcon#end of sib2, iclass 16, count 2 2006.174.00:53:44.94#ibcon#*after write, iclass 16, count 2 2006.174.00:53:44.94#ibcon#*before return 0, iclass 16, count 2 2006.174.00:53:44.94#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.174.00:53:44.94#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.174.00:53:44.94#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.174.00:53:44.94#ibcon#ireg 7 cls_cnt 0 2006.174.00:53:44.94#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.174.00:53:45.06#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.174.00:53:45.06#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.174.00:53:45.06#ibcon#enter wrdev, iclass 16, count 0 2006.174.00:53:45.06#ibcon#first serial, iclass 16, count 0 2006.174.00:53:45.06#ibcon#enter sib2, iclass 16, count 0 2006.174.00:53:45.06#ibcon#flushed, iclass 16, count 0 2006.174.00:53:45.06#ibcon#about to write, iclass 16, count 0 2006.174.00:53:45.06#ibcon#wrote, iclass 16, count 0 2006.174.00:53:45.06#ibcon#about to read 3, iclass 16, count 0 2006.174.00:53:45.08#ibcon#read 3, iclass 16, count 0 2006.174.00:53:45.08#ibcon#about to read 4, iclass 16, count 0 2006.174.00:53:45.08#ibcon#read 4, iclass 16, count 0 2006.174.00:53:45.08#ibcon#about to read 5, iclass 16, count 0 2006.174.00:53:45.08#ibcon#read 5, iclass 16, count 0 2006.174.00:53:45.08#ibcon#about to read 6, iclass 16, count 0 2006.174.00:53:45.08#ibcon#read 6, iclass 16, count 0 2006.174.00:53:45.08#ibcon#end of sib2, iclass 16, count 0 2006.174.00:53:45.08#ibcon#*mode == 0, iclass 16, count 0 2006.174.00:53:45.08#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.174.00:53:45.08#ibcon#[25=USB\r\n] 2006.174.00:53:45.08#ibcon#*before write, iclass 16, count 0 2006.174.00:53:45.08#ibcon#enter sib2, iclass 16, count 0 2006.174.00:53:45.08#ibcon#flushed, iclass 16, count 0 2006.174.00:53:45.08#ibcon#about to write, iclass 16, count 0 2006.174.00:53:45.08#ibcon#wrote, iclass 16, count 0 2006.174.00:53:45.08#ibcon#about to read 3, iclass 16, count 0 2006.174.00:53:45.11#ibcon#read 3, iclass 16, count 0 2006.174.00:53:45.11#ibcon#about to read 4, iclass 16, count 0 2006.174.00:53:45.11#ibcon#read 4, iclass 16, count 0 2006.174.00:53:45.11#ibcon#about to read 5, iclass 16, count 0 2006.174.00:53:45.11#ibcon#read 5, iclass 16, count 0 2006.174.00:53:45.11#ibcon#about to read 6, iclass 16, count 0 2006.174.00:53:45.11#ibcon#read 6, iclass 16, count 0 2006.174.00:53:45.11#ibcon#end of sib2, iclass 16, count 0 2006.174.00:53:45.11#ibcon#*after write, iclass 16, count 0 2006.174.00:53:45.11#ibcon#*before return 0, iclass 16, count 0 2006.174.00:53:45.11#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.174.00:53:45.11#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.174.00:53:45.11#ibcon#about to clear, iclass 16 cls_cnt 0 2006.174.00:53:45.11#ibcon#cleared, iclass 16 cls_cnt 0 2006.174.00:53:45.11$vck44/valo=6,814.99 2006.174.00:53:45.11#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.174.00:53:45.11#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.174.00:53:45.11#ibcon#ireg 17 cls_cnt 0 2006.174.00:53:45.11#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.174.00:53:45.11#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.174.00:53:45.11#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.174.00:53:45.11#ibcon#enter wrdev, iclass 18, count 0 2006.174.00:53:45.11#ibcon#first serial, iclass 18, count 0 2006.174.00:53:45.11#ibcon#enter sib2, iclass 18, count 0 2006.174.00:53:45.11#ibcon#flushed, iclass 18, count 0 2006.174.00:53:45.11#ibcon#about to write, iclass 18, count 0 2006.174.00:53:45.11#ibcon#wrote, iclass 18, count 0 2006.174.00:53:45.11#ibcon#about to read 3, iclass 18, count 0 2006.174.00:53:45.13#ibcon#read 3, iclass 18, count 0 2006.174.00:53:45.13#ibcon#about to read 4, iclass 18, count 0 2006.174.00:53:45.13#ibcon#read 4, iclass 18, count 0 2006.174.00:53:45.13#ibcon#about to read 5, iclass 18, count 0 2006.174.00:53:45.13#ibcon#read 5, iclass 18, count 0 2006.174.00:53:45.13#ibcon#about to read 6, iclass 18, count 0 2006.174.00:53:45.13#ibcon#read 6, iclass 18, count 0 2006.174.00:53:45.13#ibcon#end of sib2, iclass 18, count 0 2006.174.00:53:45.13#ibcon#*mode == 0, iclass 18, count 0 2006.174.00:53:45.13#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.174.00:53:45.13#ibcon#[26=FRQ=06,814.99\r\n] 2006.174.00:53:45.13#ibcon#*before write, iclass 18, count 0 2006.174.00:53:45.13#ibcon#enter sib2, iclass 18, count 0 2006.174.00:53:45.13#ibcon#flushed, iclass 18, count 0 2006.174.00:53:45.13#ibcon#about to write, iclass 18, count 0 2006.174.00:53:45.13#ibcon#wrote, iclass 18, count 0 2006.174.00:53:45.13#ibcon#about to read 3, iclass 18, count 0 2006.174.00:53:45.17#ibcon#read 3, iclass 18, count 0 2006.174.00:53:45.17#ibcon#about to read 4, iclass 18, count 0 2006.174.00:53:45.17#ibcon#read 4, iclass 18, count 0 2006.174.00:53:45.17#ibcon#about to read 5, iclass 18, count 0 2006.174.00:53:45.17#ibcon#read 5, iclass 18, count 0 2006.174.00:53:45.17#ibcon#about to read 6, iclass 18, count 0 2006.174.00:53:45.17#ibcon#read 6, iclass 18, count 0 2006.174.00:53:45.17#ibcon#end of sib2, iclass 18, count 0 2006.174.00:53:45.17#ibcon#*after write, iclass 18, count 0 2006.174.00:53:45.17#ibcon#*before return 0, iclass 18, count 0 2006.174.00:53:45.17#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.174.00:53:45.17#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.174.00:53:45.17#ibcon#about to clear, iclass 18 cls_cnt 0 2006.174.00:53:45.17#ibcon#cleared, iclass 18 cls_cnt 0 2006.174.00:53:45.17$vck44/va=6,3 2006.174.00:53:45.17#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.174.00:53:45.17#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.174.00:53:45.17#ibcon#ireg 11 cls_cnt 2 2006.174.00:53:45.17#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.174.00:53:45.23#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.174.00:53:45.23#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.174.00:53:45.23#ibcon#enter wrdev, iclass 20, count 2 2006.174.00:53:45.23#ibcon#first serial, iclass 20, count 2 2006.174.00:53:45.23#ibcon#enter sib2, iclass 20, count 2 2006.174.00:53:45.23#ibcon#flushed, iclass 20, count 2 2006.174.00:53:45.23#ibcon#about to write, iclass 20, count 2 2006.174.00:53:45.23#ibcon#wrote, iclass 20, count 2 2006.174.00:53:45.23#ibcon#about to read 3, iclass 20, count 2 2006.174.00:53:45.25#ibcon#read 3, iclass 20, count 2 2006.174.00:53:45.25#ibcon#about to read 4, iclass 20, count 2 2006.174.00:53:45.25#ibcon#read 4, iclass 20, count 2 2006.174.00:53:45.25#ibcon#about to read 5, iclass 20, count 2 2006.174.00:53:45.25#ibcon#read 5, iclass 20, count 2 2006.174.00:53:45.25#ibcon#about to read 6, iclass 20, count 2 2006.174.00:53:45.25#ibcon#read 6, iclass 20, count 2 2006.174.00:53:45.25#ibcon#end of sib2, iclass 20, count 2 2006.174.00:53:45.25#ibcon#*mode == 0, iclass 20, count 2 2006.174.00:53:45.25#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.174.00:53:45.25#ibcon#[25=AT06-03\r\n] 2006.174.00:53:45.25#ibcon#*before write, iclass 20, count 2 2006.174.00:53:45.25#ibcon#enter sib2, iclass 20, count 2 2006.174.00:53:45.25#ibcon#flushed, iclass 20, count 2 2006.174.00:53:45.25#ibcon#about to write, iclass 20, count 2 2006.174.00:53:45.25#ibcon#wrote, iclass 20, count 2 2006.174.00:53:45.25#ibcon#about to read 3, iclass 20, count 2 2006.174.00:53:45.28#ibcon#read 3, iclass 20, count 2 2006.174.00:53:45.28#ibcon#about to read 4, iclass 20, count 2 2006.174.00:53:45.28#ibcon#read 4, iclass 20, count 2 2006.174.00:53:45.28#ibcon#about to read 5, iclass 20, count 2 2006.174.00:53:45.28#ibcon#read 5, iclass 20, count 2 2006.174.00:53:45.28#ibcon#about to read 6, iclass 20, count 2 2006.174.00:53:45.28#ibcon#read 6, iclass 20, count 2 2006.174.00:53:45.28#ibcon#end of sib2, iclass 20, count 2 2006.174.00:53:45.28#ibcon#*after write, iclass 20, count 2 2006.174.00:53:45.28#ibcon#*before return 0, iclass 20, count 2 2006.174.00:53:45.28#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.174.00:53:45.28#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.174.00:53:45.28#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.174.00:53:45.28#ibcon#ireg 7 cls_cnt 0 2006.174.00:53:45.28#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.174.00:53:45.40#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.174.00:53:45.40#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.174.00:53:45.40#ibcon#enter wrdev, iclass 20, count 0 2006.174.00:53:45.40#ibcon#first serial, iclass 20, count 0 2006.174.00:53:45.40#ibcon#enter sib2, iclass 20, count 0 2006.174.00:53:45.40#ibcon#flushed, iclass 20, count 0 2006.174.00:53:45.40#ibcon#about to write, iclass 20, count 0 2006.174.00:53:45.40#ibcon#wrote, iclass 20, count 0 2006.174.00:53:45.40#ibcon#about to read 3, iclass 20, count 0 2006.174.00:53:45.42#ibcon#read 3, iclass 20, count 0 2006.174.00:53:45.42#ibcon#about to read 4, iclass 20, count 0 2006.174.00:53:45.42#ibcon#read 4, iclass 20, count 0 2006.174.00:53:45.42#ibcon#about to read 5, iclass 20, count 0 2006.174.00:53:45.42#ibcon#read 5, iclass 20, count 0 2006.174.00:53:45.42#ibcon#about to read 6, iclass 20, count 0 2006.174.00:53:45.42#ibcon#read 6, iclass 20, count 0 2006.174.00:53:45.42#ibcon#end of sib2, iclass 20, count 0 2006.174.00:53:45.42#ibcon#*mode == 0, iclass 20, count 0 2006.174.00:53:45.42#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.174.00:53:45.42#ibcon#[25=USB\r\n] 2006.174.00:53:45.42#ibcon#*before write, iclass 20, count 0 2006.174.00:53:45.42#ibcon#enter sib2, iclass 20, count 0 2006.174.00:53:45.42#ibcon#flushed, iclass 20, count 0 2006.174.00:53:45.42#ibcon#about to write, iclass 20, count 0 2006.174.00:53:45.42#ibcon#wrote, iclass 20, count 0 2006.174.00:53:45.42#ibcon#about to read 3, iclass 20, count 0 2006.174.00:53:45.45#ibcon#read 3, iclass 20, count 0 2006.174.00:53:45.45#ibcon#about to read 4, iclass 20, count 0 2006.174.00:53:45.45#ibcon#read 4, iclass 20, count 0 2006.174.00:53:45.45#ibcon#about to read 5, iclass 20, count 0 2006.174.00:53:45.45#ibcon#read 5, iclass 20, count 0 2006.174.00:53:45.45#ibcon#about to read 6, iclass 20, count 0 2006.174.00:53:45.45#ibcon#read 6, iclass 20, count 0 2006.174.00:53:45.45#ibcon#end of sib2, iclass 20, count 0 2006.174.00:53:45.45#ibcon#*after write, iclass 20, count 0 2006.174.00:53:45.45#ibcon#*before return 0, iclass 20, count 0 2006.174.00:53:45.45#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.174.00:53:45.45#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.174.00:53:45.45#ibcon#about to clear, iclass 20 cls_cnt 0 2006.174.00:53:45.45#ibcon#cleared, iclass 20 cls_cnt 0 2006.174.00:53:45.45$vck44/valo=7,864.99 2006.174.00:53:45.45#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.174.00:53:45.45#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.174.00:53:45.45#ibcon#ireg 17 cls_cnt 0 2006.174.00:53:45.45#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.174.00:53:45.45#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.174.00:53:45.45#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.174.00:53:45.45#ibcon#enter wrdev, iclass 22, count 0 2006.174.00:53:45.45#ibcon#first serial, iclass 22, count 0 2006.174.00:53:45.45#ibcon#enter sib2, iclass 22, count 0 2006.174.00:53:45.45#ibcon#flushed, iclass 22, count 0 2006.174.00:53:45.45#ibcon#about to write, iclass 22, count 0 2006.174.00:53:45.45#ibcon#wrote, iclass 22, count 0 2006.174.00:53:45.45#ibcon#about to read 3, iclass 22, count 0 2006.174.00:53:45.47#ibcon#read 3, iclass 22, count 0 2006.174.00:53:45.47#ibcon#about to read 4, iclass 22, count 0 2006.174.00:53:45.47#ibcon#read 4, iclass 22, count 0 2006.174.00:53:45.47#ibcon#about to read 5, iclass 22, count 0 2006.174.00:53:45.47#ibcon#read 5, iclass 22, count 0 2006.174.00:53:45.47#ibcon#about to read 6, iclass 22, count 0 2006.174.00:53:45.47#ibcon#read 6, iclass 22, count 0 2006.174.00:53:45.47#ibcon#end of sib2, iclass 22, count 0 2006.174.00:53:45.47#ibcon#*mode == 0, iclass 22, count 0 2006.174.00:53:45.47#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.174.00:53:45.47#ibcon#[26=FRQ=07,864.99\r\n] 2006.174.00:53:45.47#ibcon#*before write, iclass 22, count 0 2006.174.00:53:45.47#ibcon#enter sib2, iclass 22, count 0 2006.174.00:53:45.47#ibcon#flushed, iclass 22, count 0 2006.174.00:53:45.47#ibcon#about to write, iclass 22, count 0 2006.174.00:53:45.47#ibcon#wrote, iclass 22, count 0 2006.174.00:53:45.47#ibcon#about to read 3, iclass 22, count 0 2006.174.00:53:45.51#ibcon#read 3, iclass 22, count 0 2006.174.00:53:45.51#ibcon#about to read 4, iclass 22, count 0 2006.174.00:53:45.51#ibcon#read 4, iclass 22, count 0 2006.174.00:53:45.51#ibcon#about to read 5, iclass 22, count 0 2006.174.00:53:45.51#ibcon#read 5, iclass 22, count 0 2006.174.00:53:45.51#ibcon#about to read 6, iclass 22, count 0 2006.174.00:53:45.51#ibcon#read 6, iclass 22, count 0 2006.174.00:53:45.51#ibcon#end of sib2, iclass 22, count 0 2006.174.00:53:45.51#ibcon#*after write, iclass 22, count 0 2006.174.00:53:45.51#ibcon#*before return 0, iclass 22, count 0 2006.174.00:53:45.51#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.174.00:53:45.51#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.174.00:53:45.51#ibcon#about to clear, iclass 22 cls_cnt 0 2006.174.00:53:45.51#ibcon#cleared, iclass 22 cls_cnt 0 2006.174.00:53:45.51$vck44/va=7,4 2006.174.00:53:45.51#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.174.00:53:45.51#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.174.00:53:45.51#ibcon#ireg 11 cls_cnt 2 2006.174.00:53:45.51#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.174.00:53:45.57#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.174.00:53:45.57#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.174.00:53:45.57#ibcon#enter wrdev, iclass 24, count 2 2006.174.00:53:45.57#ibcon#first serial, iclass 24, count 2 2006.174.00:53:45.57#ibcon#enter sib2, iclass 24, count 2 2006.174.00:53:45.57#ibcon#flushed, iclass 24, count 2 2006.174.00:53:45.57#ibcon#about to write, iclass 24, count 2 2006.174.00:53:45.57#ibcon#wrote, iclass 24, count 2 2006.174.00:53:45.57#ibcon#about to read 3, iclass 24, count 2 2006.174.00:53:45.59#ibcon#read 3, iclass 24, count 2 2006.174.00:53:45.59#ibcon#about to read 4, iclass 24, count 2 2006.174.00:53:45.59#ibcon#read 4, iclass 24, count 2 2006.174.00:53:45.59#ibcon#about to read 5, iclass 24, count 2 2006.174.00:53:45.59#ibcon#read 5, iclass 24, count 2 2006.174.00:53:45.59#ibcon#about to read 6, iclass 24, count 2 2006.174.00:53:45.59#ibcon#read 6, iclass 24, count 2 2006.174.00:53:45.59#ibcon#end of sib2, iclass 24, count 2 2006.174.00:53:45.59#ibcon#*mode == 0, iclass 24, count 2 2006.174.00:53:45.59#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.174.00:53:45.59#ibcon#[25=AT07-04\r\n] 2006.174.00:53:45.59#ibcon#*before write, iclass 24, count 2 2006.174.00:53:45.59#ibcon#enter sib2, iclass 24, count 2 2006.174.00:53:45.59#ibcon#flushed, iclass 24, count 2 2006.174.00:53:45.59#ibcon#about to write, iclass 24, count 2 2006.174.00:53:45.59#ibcon#wrote, iclass 24, count 2 2006.174.00:53:45.59#ibcon#about to read 3, iclass 24, count 2 2006.174.00:53:45.62#ibcon#read 3, iclass 24, count 2 2006.174.00:53:45.62#ibcon#about to read 4, iclass 24, count 2 2006.174.00:53:45.62#ibcon#read 4, iclass 24, count 2 2006.174.00:53:45.62#ibcon#about to read 5, iclass 24, count 2 2006.174.00:53:45.62#ibcon#read 5, iclass 24, count 2 2006.174.00:53:45.62#ibcon#about to read 6, iclass 24, count 2 2006.174.00:53:45.62#ibcon#read 6, iclass 24, count 2 2006.174.00:53:45.62#ibcon#end of sib2, iclass 24, count 2 2006.174.00:53:45.62#ibcon#*after write, iclass 24, count 2 2006.174.00:53:45.62#ibcon#*before return 0, iclass 24, count 2 2006.174.00:53:45.62#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.174.00:53:45.62#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.174.00:53:45.62#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.174.00:53:45.62#ibcon#ireg 7 cls_cnt 0 2006.174.00:53:45.62#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.174.00:53:45.74#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.174.00:53:45.74#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.174.00:53:45.74#ibcon#enter wrdev, iclass 24, count 0 2006.174.00:53:45.74#ibcon#first serial, iclass 24, count 0 2006.174.00:53:45.74#ibcon#enter sib2, iclass 24, count 0 2006.174.00:53:45.74#ibcon#flushed, iclass 24, count 0 2006.174.00:53:45.74#ibcon#about to write, iclass 24, count 0 2006.174.00:53:45.74#ibcon#wrote, iclass 24, count 0 2006.174.00:53:45.74#ibcon#about to read 3, iclass 24, count 0 2006.174.00:53:45.76#ibcon#read 3, iclass 24, count 0 2006.174.00:53:45.76#ibcon#about to read 4, iclass 24, count 0 2006.174.00:53:45.76#ibcon#read 4, iclass 24, count 0 2006.174.00:53:45.76#ibcon#about to read 5, iclass 24, count 0 2006.174.00:53:45.76#ibcon#read 5, iclass 24, count 0 2006.174.00:53:45.76#ibcon#about to read 6, iclass 24, count 0 2006.174.00:53:45.76#ibcon#read 6, iclass 24, count 0 2006.174.00:53:45.76#ibcon#end of sib2, iclass 24, count 0 2006.174.00:53:45.76#ibcon#*mode == 0, iclass 24, count 0 2006.174.00:53:45.76#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.174.00:53:45.76#ibcon#[25=USB\r\n] 2006.174.00:53:45.76#ibcon#*before write, iclass 24, count 0 2006.174.00:53:45.76#ibcon#enter sib2, iclass 24, count 0 2006.174.00:53:45.76#ibcon#flushed, iclass 24, count 0 2006.174.00:53:45.76#ibcon#about to write, iclass 24, count 0 2006.174.00:53:45.76#ibcon#wrote, iclass 24, count 0 2006.174.00:53:45.76#ibcon#about to read 3, iclass 24, count 0 2006.174.00:53:45.79#ibcon#read 3, iclass 24, count 0 2006.174.00:53:45.79#ibcon#about to read 4, iclass 24, count 0 2006.174.00:53:45.79#ibcon#read 4, iclass 24, count 0 2006.174.00:53:45.79#ibcon#about to read 5, iclass 24, count 0 2006.174.00:53:45.79#ibcon#read 5, iclass 24, count 0 2006.174.00:53:45.79#ibcon#about to read 6, iclass 24, count 0 2006.174.00:53:45.79#ibcon#read 6, iclass 24, count 0 2006.174.00:53:45.79#ibcon#end of sib2, iclass 24, count 0 2006.174.00:53:45.79#ibcon#*after write, iclass 24, count 0 2006.174.00:53:45.79#ibcon#*before return 0, iclass 24, count 0 2006.174.00:53:45.79#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.174.00:53:45.79#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.174.00:53:45.79#ibcon#about to clear, iclass 24 cls_cnt 0 2006.174.00:53:45.79#ibcon#cleared, iclass 24 cls_cnt 0 2006.174.00:53:45.79$vck44/valo=8,884.99 2006.174.00:53:45.79#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.174.00:53:45.79#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.174.00:53:45.79#ibcon#ireg 17 cls_cnt 0 2006.174.00:53:45.79#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.174.00:53:45.79#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.174.00:53:45.79#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.174.00:53:45.79#ibcon#enter wrdev, iclass 26, count 0 2006.174.00:53:45.79#ibcon#first serial, iclass 26, count 0 2006.174.00:53:45.79#ibcon#enter sib2, iclass 26, count 0 2006.174.00:53:45.79#ibcon#flushed, iclass 26, count 0 2006.174.00:53:45.79#ibcon#about to write, iclass 26, count 0 2006.174.00:53:45.79#ibcon#wrote, iclass 26, count 0 2006.174.00:53:45.79#ibcon#about to read 3, iclass 26, count 0 2006.174.00:53:45.81#ibcon#read 3, iclass 26, count 0 2006.174.00:53:45.81#ibcon#about to read 4, iclass 26, count 0 2006.174.00:53:45.81#ibcon#read 4, iclass 26, count 0 2006.174.00:53:45.81#ibcon#about to read 5, iclass 26, count 0 2006.174.00:53:45.81#ibcon#read 5, iclass 26, count 0 2006.174.00:53:45.81#ibcon#about to read 6, iclass 26, count 0 2006.174.00:53:45.81#ibcon#read 6, iclass 26, count 0 2006.174.00:53:45.81#ibcon#end of sib2, iclass 26, count 0 2006.174.00:53:45.81#ibcon#*mode == 0, iclass 26, count 0 2006.174.00:53:45.81#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.174.00:53:45.81#ibcon#[26=FRQ=08,884.99\r\n] 2006.174.00:53:45.81#ibcon#*before write, iclass 26, count 0 2006.174.00:53:45.81#ibcon#enter sib2, iclass 26, count 0 2006.174.00:53:45.81#ibcon#flushed, iclass 26, count 0 2006.174.00:53:45.81#ibcon#about to write, iclass 26, count 0 2006.174.00:53:45.81#ibcon#wrote, iclass 26, count 0 2006.174.00:53:45.81#ibcon#about to read 3, iclass 26, count 0 2006.174.00:53:45.85#ibcon#read 3, iclass 26, count 0 2006.174.00:53:45.85#ibcon#about to read 4, iclass 26, count 0 2006.174.00:53:45.85#ibcon#read 4, iclass 26, count 0 2006.174.00:53:45.85#ibcon#about to read 5, iclass 26, count 0 2006.174.00:53:45.85#ibcon#read 5, iclass 26, count 0 2006.174.00:53:45.85#ibcon#about to read 6, iclass 26, count 0 2006.174.00:53:45.85#ibcon#read 6, iclass 26, count 0 2006.174.00:53:45.85#ibcon#end of sib2, iclass 26, count 0 2006.174.00:53:45.85#ibcon#*after write, iclass 26, count 0 2006.174.00:53:45.85#ibcon#*before return 0, iclass 26, count 0 2006.174.00:53:45.85#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.174.00:53:45.85#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.174.00:53:45.85#ibcon#about to clear, iclass 26 cls_cnt 0 2006.174.00:53:45.85#ibcon#cleared, iclass 26 cls_cnt 0 2006.174.00:53:45.85$vck44/va=8,4 2006.174.00:53:45.85#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.174.00:53:45.85#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.174.00:53:45.85#ibcon#ireg 11 cls_cnt 2 2006.174.00:53:45.85#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.174.00:53:45.91#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.174.00:53:45.91#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.174.00:53:45.91#ibcon#enter wrdev, iclass 28, count 2 2006.174.00:53:45.91#ibcon#first serial, iclass 28, count 2 2006.174.00:53:45.91#ibcon#enter sib2, iclass 28, count 2 2006.174.00:53:45.91#ibcon#flushed, iclass 28, count 2 2006.174.00:53:45.91#ibcon#about to write, iclass 28, count 2 2006.174.00:53:45.91#ibcon#wrote, iclass 28, count 2 2006.174.00:53:45.91#ibcon#about to read 3, iclass 28, count 2 2006.174.00:53:45.93#ibcon#read 3, iclass 28, count 2 2006.174.00:53:45.93#ibcon#about to read 4, iclass 28, count 2 2006.174.00:53:45.93#ibcon#read 4, iclass 28, count 2 2006.174.00:53:45.93#ibcon#about to read 5, iclass 28, count 2 2006.174.00:53:45.93#ibcon#read 5, iclass 28, count 2 2006.174.00:53:45.93#ibcon#about to read 6, iclass 28, count 2 2006.174.00:53:45.93#ibcon#read 6, iclass 28, count 2 2006.174.00:53:45.93#ibcon#end of sib2, iclass 28, count 2 2006.174.00:53:45.93#ibcon#*mode == 0, iclass 28, count 2 2006.174.00:53:45.93#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.174.00:53:45.93#ibcon#[25=AT08-04\r\n] 2006.174.00:53:45.93#ibcon#*before write, iclass 28, count 2 2006.174.00:53:45.93#ibcon#enter sib2, iclass 28, count 2 2006.174.00:53:45.93#ibcon#flushed, iclass 28, count 2 2006.174.00:53:45.93#ibcon#about to write, iclass 28, count 2 2006.174.00:53:45.93#ibcon#wrote, iclass 28, count 2 2006.174.00:53:45.93#ibcon#about to read 3, iclass 28, count 2 2006.174.00:53:45.96#ibcon#read 3, iclass 28, count 2 2006.174.00:53:45.96#ibcon#about to read 4, iclass 28, count 2 2006.174.00:53:45.96#ibcon#read 4, iclass 28, count 2 2006.174.00:53:45.96#ibcon#about to read 5, iclass 28, count 2 2006.174.00:53:45.96#ibcon#read 5, iclass 28, count 2 2006.174.00:53:45.96#ibcon#about to read 6, iclass 28, count 2 2006.174.00:53:45.96#ibcon#read 6, iclass 28, count 2 2006.174.00:53:45.96#ibcon#end of sib2, iclass 28, count 2 2006.174.00:53:45.96#ibcon#*after write, iclass 28, count 2 2006.174.00:53:45.96#ibcon#*before return 0, iclass 28, count 2 2006.174.00:53:45.96#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.174.00:53:45.96#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.174.00:53:45.96#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.174.00:53:45.96#ibcon#ireg 7 cls_cnt 0 2006.174.00:53:45.96#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.174.00:53:46.08#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.174.00:53:46.08#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.174.00:53:46.08#ibcon#enter wrdev, iclass 28, count 0 2006.174.00:53:46.08#ibcon#first serial, iclass 28, count 0 2006.174.00:53:46.08#ibcon#enter sib2, iclass 28, count 0 2006.174.00:53:46.08#ibcon#flushed, iclass 28, count 0 2006.174.00:53:46.08#ibcon#about to write, iclass 28, count 0 2006.174.00:53:46.08#ibcon#wrote, iclass 28, count 0 2006.174.00:53:46.08#ibcon#about to read 3, iclass 28, count 0 2006.174.00:53:46.10#ibcon#read 3, iclass 28, count 0 2006.174.00:53:46.10#ibcon#about to read 4, iclass 28, count 0 2006.174.00:53:46.10#ibcon#read 4, iclass 28, count 0 2006.174.00:53:46.10#ibcon#about to read 5, iclass 28, count 0 2006.174.00:53:46.10#ibcon#read 5, iclass 28, count 0 2006.174.00:53:46.10#ibcon#about to read 6, iclass 28, count 0 2006.174.00:53:46.10#ibcon#read 6, iclass 28, count 0 2006.174.00:53:46.10#ibcon#end of sib2, iclass 28, count 0 2006.174.00:53:46.10#ibcon#*mode == 0, iclass 28, count 0 2006.174.00:53:46.10#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.174.00:53:46.10#ibcon#[25=USB\r\n] 2006.174.00:53:46.10#ibcon#*before write, iclass 28, count 0 2006.174.00:53:46.10#ibcon#enter sib2, iclass 28, count 0 2006.174.00:53:46.10#ibcon#flushed, iclass 28, count 0 2006.174.00:53:46.10#ibcon#about to write, iclass 28, count 0 2006.174.00:53:46.10#ibcon#wrote, iclass 28, count 0 2006.174.00:53:46.10#ibcon#about to read 3, iclass 28, count 0 2006.174.00:53:46.13#ibcon#read 3, iclass 28, count 0 2006.174.00:53:46.13#ibcon#about to read 4, iclass 28, count 0 2006.174.00:53:46.13#ibcon#read 4, iclass 28, count 0 2006.174.00:53:46.13#ibcon#about to read 5, iclass 28, count 0 2006.174.00:53:46.13#ibcon#read 5, iclass 28, count 0 2006.174.00:53:46.13#ibcon#about to read 6, iclass 28, count 0 2006.174.00:53:46.13#ibcon#read 6, iclass 28, count 0 2006.174.00:53:46.13#ibcon#end of sib2, iclass 28, count 0 2006.174.00:53:46.13#ibcon#*after write, iclass 28, count 0 2006.174.00:53:46.13#ibcon#*before return 0, iclass 28, count 0 2006.174.00:53:46.13#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.174.00:53:46.13#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.174.00:53:46.13#ibcon#about to clear, iclass 28 cls_cnt 0 2006.174.00:53:46.13#ibcon#cleared, iclass 28 cls_cnt 0 2006.174.00:53:46.13$vck44/vblo=1,629.99 2006.174.00:53:46.13#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.174.00:53:46.13#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.174.00:53:46.13#ibcon#ireg 17 cls_cnt 0 2006.174.00:53:46.13#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.174.00:53:46.13#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.174.00:53:46.13#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.174.00:53:46.13#ibcon#enter wrdev, iclass 30, count 0 2006.174.00:53:46.13#ibcon#first serial, iclass 30, count 0 2006.174.00:53:46.13#ibcon#enter sib2, iclass 30, count 0 2006.174.00:53:46.13#ibcon#flushed, iclass 30, count 0 2006.174.00:53:46.13#ibcon#about to write, iclass 30, count 0 2006.174.00:53:46.13#ibcon#wrote, iclass 30, count 0 2006.174.00:53:46.13#ibcon#about to read 3, iclass 30, count 0 2006.174.00:53:46.15#ibcon#read 3, iclass 30, count 0 2006.174.00:53:46.15#ibcon#about to read 4, iclass 30, count 0 2006.174.00:53:46.15#ibcon#read 4, iclass 30, count 0 2006.174.00:53:46.15#ibcon#about to read 5, iclass 30, count 0 2006.174.00:53:46.15#ibcon#read 5, iclass 30, count 0 2006.174.00:53:46.15#ibcon#about to read 6, iclass 30, count 0 2006.174.00:53:46.15#ibcon#read 6, iclass 30, count 0 2006.174.00:53:46.15#ibcon#end of sib2, iclass 30, count 0 2006.174.00:53:46.15#ibcon#*mode == 0, iclass 30, count 0 2006.174.00:53:46.15#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.174.00:53:46.15#ibcon#[28=FRQ=01,629.99\r\n] 2006.174.00:53:46.15#ibcon#*before write, iclass 30, count 0 2006.174.00:53:46.15#ibcon#enter sib2, iclass 30, count 0 2006.174.00:53:46.15#ibcon#flushed, iclass 30, count 0 2006.174.00:53:46.15#ibcon#about to write, iclass 30, count 0 2006.174.00:53:46.15#ibcon#wrote, iclass 30, count 0 2006.174.00:53:46.15#ibcon#about to read 3, iclass 30, count 0 2006.174.00:53:46.19#ibcon#read 3, iclass 30, count 0 2006.174.00:53:46.19#ibcon#about to read 4, iclass 30, count 0 2006.174.00:53:46.19#ibcon#read 4, iclass 30, count 0 2006.174.00:53:46.19#ibcon#about to read 5, iclass 30, count 0 2006.174.00:53:46.19#ibcon#read 5, iclass 30, count 0 2006.174.00:53:46.19#ibcon#about to read 6, iclass 30, count 0 2006.174.00:53:46.19#ibcon#read 6, iclass 30, count 0 2006.174.00:53:46.19#ibcon#end of sib2, iclass 30, count 0 2006.174.00:53:46.19#ibcon#*after write, iclass 30, count 0 2006.174.00:53:46.19#ibcon#*before return 0, iclass 30, count 0 2006.174.00:53:46.19#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.174.00:53:46.19#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.174.00:53:46.19#ibcon#about to clear, iclass 30 cls_cnt 0 2006.174.00:53:46.19#ibcon#cleared, iclass 30 cls_cnt 0 2006.174.00:53:46.19$vck44/vb=1,4 2006.174.00:53:46.19#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.174.00:53:46.19#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.174.00:53:46.19#ibcon#ireg 11 cls_cnt 2 2006.174.00:53:46.19#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.174.00:53:46.19#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.174.00:53:46.19#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.174.00:53:46.19#ibcon#enter wrdev, iclass 32, count 2 2006.174.00:53:46.19#ibcon#first serial, iclass 32, count 2 2006.174.00:53:46.19#ibcon#enter sib2, iclass 32, count 2 2006.174.00:53:46.19#ibcon#flushed, iclass 32, count 2 2006.174.00:53:46.19#ibcon#about to write, iclass 32, count 2 2006.174.00:53:46.19#ibcon#wrote, iclass 32, count 2 2006.174.00:53:46.19#ibcon#about to read 3, iclass 32, count 2 2006.174.00:53:46.21#ibcon#read 3, iclass 32, count 2 2006.174.00:53:46.21#ibcon#about to read 4, iclass 32, count 2 2006.174.00:53:46.21#ibcon#read 4, iclass 32, count 2 2006.174.00:53:46.21#ibcon#about to read 5, iclass 32, count 2 2006.174.00:53:46.21#ibcon#read 5, iclass 32, count 2 2006.174.00:53:46.21#ibcon#about to read 6, iclass 32, count 2 2006.174.00:53:46.21#ibcon#read 6, iclass 32, count 2 2006.174.00:53:46.21#ibcon#end of sib2, iclass 32, count 2 2006.174.00:53:46.21#ibcon#*mode == 0, iclass 32, count 2 2006.174.00:53:46.21#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.174.00:53:46.21#ibcon#[27=AT01-04\r\n] 2006.174.00:53:46.21#ibcon#*before write, iclass 32, count 2 2006.174.00:53:46.21#ibcon#enter sib2, iclass 32, count 2 2006.174.00:53:46.21#ibcon#flushed, iclass 32, count 2 2006.174.00:53:46.21#ibcon#about to write, iclass 32, count 2 2006.174.00:53:46.21#ibcon#wrote, iclass 32, count 2 2006.174.00:53:46.21#ibcon#about to read 3, iclass 32, count 2 2006.174.00:53:46.24#ibcon#read 3, iclass 32, count 2 2006.174.00:53:46.24#ibcon#about to read 4, iclass 32, count 2 2006.174.00:53:46.24#ibcon#read 4, iclass 32, count 2 2006.174.00:53:46.24#ibcon#about to read 5, iclass 32, count 2 2006.174.00:53:46.24#ibcon#read 5, iclass 32, count 2 2006.174.00:53:46.24#ibcon#about to read 6, iclass 32, count 2 2006.174.00:53:46.24#ibcon#read 6, iclass 32, count 2 2006.174.00:53:46.24#ibcon#end of sib2, iclass 32, count 2 2006.174.00:53:46.24#ibcon#*after write, iclass 32, count 2 2006.174.00:53:46.24#ibcon#*before return 0, iclass 32, count 2 2006.174.00:53:46.24#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.174.00:53:46.24#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.174.00:53:46.24#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.174.00:53:46.24#ibcon#ireg 7 cls_cnt 0 2006.174.00:53:46.24#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.174.00:53:46.36#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.174.00:53:46.36#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.174.00:53:46.36#ibcon#enter wrdev, iclass 32, count 0 2006.174.00:53:46.36#ibcon#first serial, iclass 32, count 0 2006.174.00:53:46.36#ibcon#enter sib2, iclass 32, count 0 2006.174.00:53:46.36#ibcon#flushed, iclass 32, count 0 2006.174.00:53:46.36#ibcon#about to write, iclass 32, count 0 2006.174.00:53:46.36#ibcon#wrote, iclass 32, count 0 2006.174.00:53:46.36#ibcon#about to read 3, iclass 32, count 0 2006.174.00:53:46.38#ibcon#read 3, iclass 32, count 0 2006.174.00:53:46.38#ibcon#about to read 4, iclass 32, count 0 2006.174.00:53:46.38#ibcon#read 4, iclass 32, count 0 2006.174.00:53:46.38#ibcon#about to read 5, iclass 32, count 0 2006.174.00:53:46.38#ibcon#read 5, iclass 32, count 0 2006.174.00:53:46.38#ibcon#about to read 6, iclass 32, count 0 2006.174.00:53:46.38#ibcon#read 6, iclass 32, count 0 2006.174.00:53:46.38#ibcon#end of sib2, iclass 32, count 0 2006.174.00:53:46.38#ibcon#*mode == 0, iclass 32, count 0 2006.174.00:53:46.38#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.174.00:53:46.38#ibcon#[27=USB\r\n] 2006.174.00:53:46.38#ibcon#*before write, iclass 32, count 0 2006.174.00:53:46.38#ibcon#enter sib2, iclass 32, count 0 2006.174.00:53:46.38#ibcon#flushed, iclass 32, count 0 2006.174.00:53:46.38#ibcon#about to write, iclass 32, count 0 2006.174.00:53:46.38#ibcon#wrote, iclass 32, count 0 2006.174.00:53:46.38#ibcon#about to read 3, iclass 32, count 0 2006.174.00:53:46.41#ibcon#read 3, iclass 32, count 0 2006.174.00:53:46.41#ibcon#about to read 4, iclass 32, count 0 2006.174.00:53:46.41#ibcon#read 4, iclass 32, count 0 2006.174.00:53:46.41#ibcon#about to read 5, iclass 32, count 0 2006.174.00:53:46.41#ibcon#read 5, iclass 32, count 0 2006.174.00:53:46.41#ibcon#about to read 6, iclass 32, count 0 2006.174.00:53:46.41#ibcon#read 6, iclass 32, count 0 2006.174.00:53:46.41#ibcon#end of sib2, iclass 32, count 0 2006.174.00:53:46.41#ibcon#*after write, iclass 32, count 0 2006.174.00:53:46.41#ibcon#*before return 0, iclass 32, count 0 2006.174.00:53:46.41#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.174.00:53:46.41#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.174.00:53:46.41#ibcon#about to clear, iclass 32 cls_cnt 0 2006.174.00:53:46.41#ibcon#cleared, iclass 32 cls_cnt 0 2006.174.00:53:46.41$vck44/vblo=2,634.99 2006.174.00:53:46.41#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.174.00:53:46.41#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.174.00:53:46.41#ibcon#ireg 17 cls_cnt 0 2006.174.00:53:46.41#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.174.00:53:46.41#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.174.00:53:46.41#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.174.00:53:46.41#ibcon#enter wrdev, iclass 34, count 0 2006.174.00:53:46.41#ibcon#first serial, iclass 34, count 0 2006.174.00:53:46.41#ibcon#enter sib2, iclass 34, count 0 2006.174.00:53:46.41#ibcon#flushed, iclass 34, count 0 2006.174.00:53:46.41#ibcon#about to write, iclass 34, count 0 2006.174.00:53:46.41#ibcon#wrote, iclass 34, count 0 2006.174.00:53:46.41#ibcon#about to read 3, iclass 34, count 0 2006.174.00:53:46.43#ibcon#read 3, iclass 34, count 0 2006.174.00:53:46.43#ibcon#about to read 4, iclass 34, count 0 2006.174.00:53:46.43#ibcon#read 4, iclass 34, count 0 2006.174.00:53:46.43#ibcon#about to read 5, iclass 34, count 0 2006.174.00:53:46.43#ibcon#read 5, iclass 34, count 0 2006.174.00:53:46.43#ibcon#about to read 6, iclass 34, count 0 2006.174.00:53:46.43#ibcon#read 6, iclass 34, count 0 2006.174.00:53:46.43#ibcon#end of sib2, iclass 34, count 0 2006.174.00:53:46.43#ibcon#*mode == 0, iclass 34, count 0 2006.174.00:53:46.43#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.174.00:53:46.43#ibcon#[28=FRQ=02,634.99\r\n] 2006.174.00:53:46.43#ibcon#*before write, iclass 34, count 0 2006.174.00:53:46.43#ibcon#enter sib2, iclass 34, count 0 2006.174.00:53:46.43#ibcon#flushed, iclass 34, count 0 2006.174.00:53:46.43#ibcon#about to write, iclass 34, count 0 2006.174.00:53:46.43#ibcon#wrote, iclass 34, count 0 2006.174.00:53:46.43#ibcon#about to read 3, iclass 34, count 0 2006.174.00:53:46.47#ibcon#read 3, iclass 34, count 0 2006.174.00:53:46.47#ibcon#about to read 4, iclass 34, count 0 2006.174.00:53:46.47#ibcon#read 4, iclass 34, count 0 2006.174.00:53:46.47#ibcon#about to read 5, iclass 34, count 0 2006.174.00:53:46.47#ibcon#read 5, iclass 34, count 0 2006.174.00:53:46.47#ibcon#about to read 6, iclass 34, count 0 2006.174.00:53:46.47#ibcon#read 6, iclass 34, count 0 2006.174.00:53:46.47#ibcon#end of sib2, iclass 34, count 0 2006.174.00:53:46.47#ibcon#*after write, iclass 34, count 0 2006.174.00:53:46.47#ibcon#*before return 0, iclass 34, count 0 2006.174.00:53:46.47#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.174.00:53:46.47#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.174.00:53:46.47#ibcon#about to clear, iclass 34 cls_cnt 0 2006.174.00:53:46.47#ibcon#cleared, iclass 34 cls_cnt 0 2006.174.00:53:46.47$vck44/vb=2,4 2006.174.00:53:46.47#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.174.00:53:46.47#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.174.00:53:46.47#ibcon#ireg 11 cls_cnt 2 2006.174.00:53:46.47#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.174.00:53:46.53#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.174.00:53:46.53#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.174.00:53:46.53#ibcon#enter wrdev, iclass 36, count 2 2006.174.00:53:46.53#ibcon#first serial, iclass 36, count 2 2006.174.00:53:46.53#ibcon#enter sib2, iclass 36, count 2 2006.174.00:53:46.53#ibcon#flushed, iclass 36, count 2 2006.174.00:53:46.53#ibcon#about to write, iclass 36, count 2 2006.174.00:53:46.53#ibcon#wrote, iclass 36, count 2 2006.174.00:53:46.53#ibcon#about to read 3, iclass 36, count 2 2006.174.00:53:46.55#ibcon#read 3, iclass 36, count 2 2006.174.00:53:46.55#ibcon#about to read 4, iclass 36, count 2 2006.174.00:53:46.55#ibcon#read 4, iclass 36, count 2 2006.174.00:53:46.55#ibcon#about to read 5, iclass 36, count 2 2006.174.00:53:46.55#ibcon#read 5, iclass 36, count 2 2006.174.00:53:46.55#ibcon#about to read 6, iclass 36, count 2 2006.174.00:53:46.55#ibcon#read 6, iclass 36, count 2 2006.174.00:53:46.55#ibcon#end of sib2, iclass 36, count 2 2006.174.00:53:46.55#ibcon#*mode == 0, iclass 36, count 2 2006.174.00:53:46.55#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.174.00:53:46.55#ibcon#[27=AT02-04\r\n] 2006.174.00:53:46.55#ibcon#*before write, iclass 36, count 2 2006.174.00:53:46.55#ibcon#enter sib2, iclass 36, count 2 2006.174.00:53:46.55#ibcon#flushed, iclass 36, count 2 2006.174.00:53:46.55#ibcon#about to write, iclass 36, count 2 2006.174.00:53:46.55#ibcon#wrote, iclass 36, count 2 2006.174.00:53:46.55#ibcon#about to read 3, iclass 36, count 2 2006.174.00:53:46.58#ibcon#read 3, iclass 36, count 2 2006.174.00:53:46.58#ibcon#about to read 4, iclass 36, count 2 2006.174.00:53:46.58#ibcon#read 4, iclass 36, count 2 2006.174.00:53:46.58#ibcon#about to read 5, iclass 36, count 2 2006.174.00:53:46.58#ibcon#read 5, iclass 36, count 2 2006.174.00:53:46.58#ibcon#about to read 6, iclass 36, count 2 2006.174.00:53:46.58#ibcon#read 6, iclass 36, count 2 2006.174.00:53:46.58#ibcon#end of sib2, iclass 36, count 2 2006.174.00:53:46.58#ibcon#*after write, iclass 36, count 2 2006.174.00:53:46.58#ibcon#*before return 0, iclass 36, count 2 2006.174.00:53:46.58#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.174.00:53:46.58#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.174.00:53:46.58#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.174.00:53:46.58#ibcon#ireg 7 cls_cnt 0 2006.174.00:53:46.58#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.174.00:53:46.70#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.174.00:53:46.70#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.174.00:53:46.70#ibcon#enter wrdev, iclass 36, count 0 2006.174.00:53:46.70#ibcon#first serial, iclass 36, count 0 2006.174.00:53:46.70#ibcon#enter sib2, iclass 36, count 0 2006.174.00:53:46.70#ibcon#flushed, iclass 36, count 0 2006.174.00:53:46.70#ibcon#about to write, iclass 36, count 0 2006.174.00:53:46.70#ibcon#wrote, iclass 36, count 0 2006.174.00:53:46.70#ibcon#about to read 3, iclass 36, count 0 2006.174.00:53:46.72#ibcon#read 3, iclass 36, count 0 2006.174.00:53:46.72#ibcon#about to read 4, iclass 36, count 0 2006.174.00:53:46.72#ibcon#read 4, iclass 36, count 0 2006.174.00:53:46.72#ibcon#about to read 5, iclass 36, count 0 2006.174.00:53:46.72#ibcon#read 5, iclass 36, count 0 2006.174.00:53:46.72#ibcon#about to read 6, iclass 36, count 0 2006.174.00:53:46.72#ibcon#read 6, iclass 36, count 0 2006.174.00:53:46.72#ibcon#end of sib2, iclass 36, count 0 2006.174.00:53:46.72#ibcon#*mode == 0, iclass 36, count 0 2006.174.00:53:46.72#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.174.00:53:46.72#ibcon#[27=USB\r\n] 2006.174.00:53:46.72#ibcon#*before write, iclass 36, count 0 2006.174.00:53:46.72#ibcon#enter sib2, iclass 36, count 0 2006.174.00:53:46.72#ibcon#flushed, iclass 36, count 0 2006.174.00:53:46.72#ibcon#about to write, iclass 36, count 0 2006.174.00:53:46.72#ibcon#wrote, iclass 36, count 0 2006.174.00:53:46.72#ibcon#about to read 3, iclass 36, count 0 2006.174.00:53:46.75#ibcon#read 3, iclass 36, count 0 2006.174.00:53:46.75#ibcon#about to read 4, iclass 36, count 0 2006.174.00:53:46.75#ibcon#read 4, iclass 36, count 0 2006.174.00:53:46.75#ibcon#about to read 5, iclass 36, count 0 2006.174.00:53:46.75#ibcon#read 5, iclass 36, count 0 2006.174.00:53:46.75#ibcon#about to read 6, iclass 36, count 0 2006.174.00:53:46.75#ibcon#read 6, iclass 36, count 0 2006.174.00:53:46.75#ibcon#end of sib2, iclass 36, count 0 2006.174.00:53:46.75#ibcon#*after write, iclass 36, count 0 2006.174.00:53:46.75#ibcon#*before return 0, iclass 36, count 0 2006.174.00:53:46.75#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.174.00:53:46.75#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.174.00:53:46.75#ibcon#about to clear, iclass 36 cls_cnt 0 2006.174.00:53:46.75#ibcon#cleared, iclass 36 cls_cnt 0 2006.174.00:53:46.75$vck44/vblo=3,649.99 2006.174.00:53:46.75#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.174.00:53:46.75#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.174.00:53:46.75#ibcon#ireg 17 cls_cnt 0 2006.174.00:53:46.75#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.174.00:53:46.75#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.174.00:53:46.75#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.174.00:53:46.75#ibcon#enter wrdev, iclass 38, count 0 2006.174.00:53:46.75#ibcon#first serial, iclass 38, count 0 2006.174.00:53:46.75#ibcon#enter sib2, iclass 38, count 0 2006.174.00:53:46.75#ibcon#flushed, iclass 38, count 0 2006.174.00:53:46.75#ibcon#about to write, iclass 38, count 0 2006.174.00:53:46.75#ibcon#wrote, iclass 38, count 0 2006.174.00:53:46.75#ibcon#about to read 3, iclass 38, count 0 2006.174.00:53:46.77#ibcon#read 3, iclass 38, count 0 2006.174.00:53:46.77#ibcon#about to read 4, iclass 38, count 0 2006.174.00:53:46.77#ibcon#read 4, iclass 38, count 0 2006.174.00:53:46.77#ibcon#about to read 5, iclass 38, count 0 2006.174.00:53:46.77#ibcon#read 5, iclass 38, count 0 2006.174.00:53:46.77#ibcon#about to read 6, iclass 38, count 0 2006.174.00:53:46.77#ibcon#read 6, iclass 38, count 0 2006.174.00:53:46.77#ibcon#end of sib2, iclass 38, count 0 2006.174.00:53:46.77#ibcon#*mode == 0, iclass 38, count 0 2006.174.00:53:46.77#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.174.00:53:46.77#ibcon#[28=FRQ=03,649.99\r\n] 2006.174.00:53:46.77#ibcon#*before write, iclass 38, count 0 2006.174.00:53:46.77#ibcon#enter sib2, iclass 38, count 0 2006.174.00:53:46.77#ibcon#flushed, iclass 38, count 0 2006.174.00:53:46.77#ibcon#about to write, iclass 38, count 0 2006.174.00:53:46.77#ibcon#wrote, iclass 38, count 0 2006.174.00:53:46.77#ibcon#about to read 3, iclass 38, count 0 2006.174.00:53:46.81#ibcon#read 3, iclass 38, count 0 2006.174.00:53:46.81#ibcon#about to read 4, iclass 38, count 0 2006.174.00:53:46.81#ibcon#read 4, iclass 38, count 0 2006.174.00:53:46.81#ibcon#about to read 5, iclass 38, count 0 2006.174.00:53:46.81#ibcon#read 5, iclass 38, count 0 2006.174.00:53:46.81#ibcon#about to read 6, iclass 38, count 0 2006.174.00:53:46.81#ibcon#read 6, iclass 38, count 0 2006.174.00:53:46.81#ibcon#end of sib2, iclass 38, count 0 2006.174.00:53:46.81#ibcon#*after write, iclass 38, count 0 2006.174.00:53:46.81#ibcon#*before return 0, iclass 38, count 0 2006.174.00:53:46.81#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.174.00:53:46.81#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.174.00:53:46.81#ibcon#about to clear, iclass 38 cls_cnt 0 2006.174.00:53:46.81#ibcon#cleared, iclass 38 cls_cnt 0 2006.174.00:53:46.81$vck44/vb=3,4 2006.174.00:53:46.81#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.174.00:53:46.81#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.174.00:53:46.81#ibcon#ireg 11 cls_cnt 2 2006.174.00:53:46.81#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.174.00:53:46.87#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.174.00:53:46.87#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.174.00:53:46.87#ibcon#enter wrdev, iclass 40, count 2 2006.174.00:53:46.87#ibcon#first serial, iclass 40, count 2 2006.174.00:53:46.87#ibcon#enter sib2, iclass 40, count 2 2006.174.00:53:46.87#ibcon#flushed, iclass 40, count 2 2006.174.00:53:46.87#ibcon#about to write, iclass 40, count 2 2006.174.00:53:46.87#ibcon#wrote, iclass 40, count 2 2006.174.00:53:46.87#ibcon#about to read 3, iclass 40, count 2 2006.174.00:53:46.89#ibcon#read 3, iclass 40, count 2 2006.174.00:53:46.89#ibcon#about to read 4, iclass 40, count 2 2006.174.00:53:46.89#ibcon#read 4, iclass 40, count 2 2006.174.00:53:46.89#ibcon#about to read 5, iclass 40, count 2 2006.174.00:53:46.89#ibcon#read 5, iclass 40, count 2 2006.174.00:53:46.89#ibcon#about to read 6, iclass 40, count 2 2006.174.00:53:46.89#ibcon#read 6, iclass 40, count 2 2006.174.00:53:46.89#ibcon#end of sib2, iclass 40, count 2 2006.174.00:53:46.89#ibcon#*mode == 0, iclass 40, count 2 2006.174.00:53:46.89#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.174.00:53:46.89#ibcon#[27=AT03-04\r\n] 2006.174.00:53:46.89#ibcon#*before write, iclass 40, count 2 2006.174.00:53:46.89#ibcon#enter sib2, iclass 40, count 2 2006.174.00:53:46.89#ibcon#flushed, iclass 40, count 2 2006.174.00:53:46.89#ibcon#about to write, iclass 40, count 2 2006.174.00:53:46.89#ibcon#wrote, iclass 40, count 2 2006.174.00:53:46.89#ibcon#about to read 3, iclass 40, count 2 2006.174.00:53:46.92#ibcon#read 3, iclass 40, count 2 2006.174.00:53:46.92#ibcon#about to read 4, iclass 40, count 2 2006.174.00:53:46.92#ibcon#read 4, iclass 40, count 2 2006.174.00:53:46.92#ibcon#about to read 5, iclass 40, count 2 2006.174.00:53:46.92#ibcon#read 5, iclass 40, count 2 2006.174.00:53:46.92#ibcon#about to read 6, iclass 40, count 2 2006.174.00:53:46.92#ibcon#read 6, iclass 40, count 2 2006.174.00:53:46.92#ibcon#end of sib2, iclass 40, count 2 2006.174.00:53:46.92#ibcon#*after write, iclass 40, count 2 2006.174.00:53:46.92#ibcon#*before return 0, iclass 40, count 2 2006.174.00:53:46.92#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.174.00:53:46.92#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.174.00:53:46.92#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.174.00:53:46.92#ibcon#ireg 7 cls_cnt 0 2006.174.00:53:46.92#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.174.00:53:47.04#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.174.00:53:47.04#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.174.00:53:47.04#ibcon#enter wrdev, iclass 40, count 0 2006.174.00:53:47.04#ibcon#first serial, iclass 40, count 0 2006.174.00:53:47.04#ibcon#enter sib2, iclass 40, count 0 2006.174.00:53:47.04#ibcon#flushed, iclass 40, count 0 2006.174.00:53:47.04#ibcon#about to write, iclass 40, count 0 2006.174.00:53:47.04#ibcon#wrote, iclass 40, count 0 2006.174.00:53:47.04#ibcon#about to read 3, iclass 40, count 0 2006.174.00:53:47.06#ibcon#read 3, iclass 40, count 0 2006.174.00:53:47.06#ibcon#about to read 4, iclass 40, count 0 2006.174.00:53:47.06#ibcon#read 4, iclass 40, count 0 2006.174.00:53:47.06#ibcon#about to read 5, iclass 40, count 0 2006.174.00:53:47.06#ibcon#read 5, iclass 40, count 0 2006.174.00:53:47.06#ibcon#about to read 6, iclass 40, count 0 2006.174.00:53:47.06#ibcon#read 6, iclass 40, count 0 2006.174.00:53:47.06#ibcon#end of sib2, iclass 40, count 0 2006.174.00:53:47.06#ibcon#*mode == 0, iclass 40, count 0 2006.174.00:53:47.06#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.174.00:53:47.06#ibcon#[27=USB\r\n] 2006.174.00:53:47.06#ibcon#*before write, iclass 40, count 0 2006.174.00:53:47.06#ibcon#enter sib2, iclass 40, count 0 2006.174.00:53:47.06#ibcon#flushed, iclass 40, count 0 2006.174.00:53:47.06#ibcon#about to write, iclass 40, count 0 2006.174.00:53:47.06#ibcon#wrote, iclass 40, count 0 2006.174.00:53:47.06#ibcon#about to read 3, iclass 40, count 0 2006.174.00:53:47.09#ibcon#read 3, iclass 40, count 0 2006.174.00:53:47.09#ibcon#about to read 4, iclass 40, count 0 2006.174.00:53:47.09#ibcon#read 4, iclass 40, count 0 2006.174.00:53:47.09#ibcon#about to read 5, iclass 40, count 0 2006.174.00:53:47.09#ibcon#read 5, iclass 40, count 0 2006.174.00:53:47.09#ibcon#about to read 6, iclass 40, count 0 2006.174.00:53:47.09#ibcon#read 6, iclass 40, count 0 2006.174.00:53:47.09#ibcon#end of sib2, iclass 40, count 0 2006.174.00:53:47.09#ibcon#*after write, iclass 40, count 0 2006.174.00:53:47.09#ibcon#*before return 0, iclass 40, count 0 2006.174.00:53:47.09#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.174.00:53:47.09#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.174.00:53:47.09#ibcon#about to clear, iclass 40 cls_cnt 0 2006.174.00:53:47.09#ibcon#cleared, iclass 40 cls_cnt 0 2006.174.00:53:47.09$vck44/vblo=4,679.99 2006.174.00:53:47.09#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.174.00:53:47.09#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.174.00:53:47.09#ibcon#ireg 17 cls_cnt 0 2006.174.00:53:47.09#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.174.00:53:47.09#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.174.00:53:47.09#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.174.00:53:47.09#ibcon#enter wrdev, iclass 4, count 0 2006.174.00:53:47.09#ibcon#first serial, iclass 4, count 0 2006.174.00:53:47.09#ibcon#enter sib2, iclass 4, count 0 2006.174.00:53:47.09#ibcon#flushed, iclass 4, count 0 2006.174.00:53:47.09#ibcon#about to write, iclass 4, count 0 2006.174.00:53:47.09#ibcon#wrote, iclass 4, count 0 2006.174.00:53:47.09#ibcon#about to read 3, iclass 4, count 0 2006.174.00:53:47.11#ibcon#read 3, iclass 4, count 0 2006.174.00:53:47.11#ibcon#about to read 4, iclass 4, count 0 2006.174.00:53:47.11#ibcon#read 4, iclass 4, count 0 2006.174.00:53:47.11#ibcon#about to read 5, iclass 4, count 0 2006.174.00:53:47.11#ibcon#read 5, iclass 4, count 0 2006.174.00:53:47.11#ibcon#about to read 6, iclass 4, count 0 2006.174.00:53:47.11#ibcon#read 6, iclass 4, count 0 2006.174.00:53:47.11#ibcon#end of sib2, iclass 4, count 0 2006.174.00:53:47.11#ibcon#*mode == 0, iclass 4, count 0 2006.174.00:53:47.11#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.174.00:53:47.11#ibcon#[28=FRQ=04,679.99\r\n] 2006.174.00:53:47.11#ibcon#*before write, iclass 4, count 0 2006.174.00:53:47.11#ibcon#enter sib2, iclass 4, count 0 2006.174.00:53:47.11#ibcon#flushed, iclass 4, count 0 2006.174.00:53:47.11#ibcon#about to write, iclass 4, count 0 2006.174.00:53:47.11#ibcon#wrote, iclass 4, count 0 2006.174.00:53:47.11#ibcon#about to read 3, iclass 4, count 0 2006.174.00:53:47.15#ibcon#read 3, iclass 4, count 0 2006.174.00:53:47.15#ibcon#about to read 4, iclass 4, count 0 2006.174.00:53:47.15#ibcon#read 4, iclass 4, count 0 2006.174.00:53:47.15#ibcon#about to read 5, iclass 4, count 0 2006.174.00:53:47.15#ibcon#read 5, iclass 4, count 0 2006.174.00:53:47.15#ibcon#about to read 6, iclass 4, count 0 2006.174.00:53:47.15#ibcon#read 6, iclass 4, count 0 2006.174.00:53:47.15#ibcon#end of sib2, iclass 4, count 0 2006.174.00:53:47.15#ibcon#*after write, iclass 4, count 0 2006.174.00:53:47.15#ibcon#*before return 0, iclass 4, count 0 2006.174.00:53:47.15#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.174.00:53:47.15#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.174.00:53:47.15#ibcon#about to clear, iclass 4 cls_cnt 0 2006.174.00:53:47.15#ibcon#cleared, iclass 4 cls_cnt 0 2006.174.00:53:47.15$vck44/vb=4,4 2006.174.00:53:47.15#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.174.00:53:47.15#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.174.00:53:47.15#ibcon#ireg 11 cls_cnt 2 2006.174.00:53:47.15#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.174.00:53:47.21#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.174.00:53:47.21#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.174.00:53:47.21#ibcon#enter wrdev, iclass 6, count 2 2006.174.00:53:47.21#ibcon#first serial, iclass 6, count 2 2006.174.00:53:47.21#ibcon#enter sib2, iclass 6, count 2 2006.174.00:53:47.21#ibcon#flushed, iclass 6, count 2 2006.174.00:53:47.21#ibcon#about to write, iclass 6, count 2 2006.174.00:53:47.21#ibcon#wrote, iclass 6, count 2 2006.174.00:53:47.21#ibcon#about to read 3, iclass 6, count 2 2006.174.00:53:47.23#ibcon#read 3, iclass 6, count 2 2006.174.00:53:47.23#ibcon#about to read 4, iclass 6, count 2 2006.174.00:53:47.23#ibcon#read 4, iclass 6, count 2 2006.174.00:53:47.23#ibcon#about to read 5, iclass 6, count 2 2006.174.00:53:47.23#ibcon#read 5, iclass 6, count 2 2006.174.00:53:47.23#ibcon#about to read 6, iclass 6, count 2 2006.174.00:53:47.23#ibcon#read 6, iclass 6, count 2 2006.174.00:53:47.23#ibcon#end of sib2, iclass 6, count 2 2006.174.00:53:47.23#ibcon#*mode == 0, iclass 6, count 2 2006.174.00:53:47.23#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.174.00:53:47.23#ibcon#[27=AT04-04\r\n] 2006.174.00:53:47.23#ibcon#*before write, iclass 6, count 2 2006.174.00:53:47.23#ibcon#enter sib2, iclass 6, count 2 2006.174.00:53:47.23#ibcon#flushed, iclass 6, count 2 2006.174.00:53:47.23#ibcon#about to write, iclass 6, count 2 2006.174.00:53:47.23#ibcon#wrote, iclass 6, count 2 2006.174.00:53:47.23#ibcon#about to read 3, iclass 6, count 2 2006.174.00:53:47.26#ibcon#read 3, iclass 6, count 2 2006.174.00:53:47.26#ibcon#about to read 4, iclass 6, count 2 2006.174.00:53:47.26#ibcon#read 4, iclass 6, count 2 2006.174.00:53:47.26#ibcon#about to read 5, iclass 6, count 2 2006.174.00:53:47.26#ibcon#read 5, iclass 6, count 2 2006.174.00:53:47.26#ibcon#about to read 6, iclass 6, count 2 2006.174.00:53:47.26#ibcon#read 6, iclass 6, count 2 2006.174.00:53:47.26#ibcon#end of sib2, iclass 6, count 2 2006.174.00:53:47.26#ibcon#*after write, iclass 6, count 2 2006.174.00:53:47.26#ibcon#*before return 0, iclass 6, count 2 2006.174.00:53:47.26#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.174.00:53:47.26#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.174.00:53:47.26#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.174.00:53:47.26#ibcon#ireg 7 cls_cnt 0 2006.174.00:53:47.26#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.174.00:53:47.38#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.174.00:53:47.38#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.174.00:53:47.38#ibcon#enter wrdev, iclass 6, count 0 2006.174.00:53:47.38#ibcon#first serial, iclass 6, count 0 2006.174.00:53:47.38#ibcon#enter sib2, iclass 6, count 0 2006.174.00:53:47.38#ibcon#flushed, iclass 6, count 0 2006.174.00:53:47.38#ibcon#about to write, iclass 6, count 0 2006.174.00:53:47.38#ibcon#wrote, iclass 6, count 0 2006.174.00:53:47.38#ibcon#about to read 3, iclass 6, count 0 2006.174.00:53:47.40#ibcon#read 3, iclass 6, count 0 2006.174.00:53:47.40#ibcon#about to read 4, iclass 6, count 0 2006.174.00:53:47.40#ibcon#read 4, iclass 6, count 0 2006.174.00:53:47.40#ibcon#about to read 5, iclass 6, count 0 2006.174.00:53:47.40#ibcon#read 5, iclass 6, count 0 2006.174.00:53:47.40#ibcon#about to read 6, iclass 6, count 0 2006.174.00:53:47.40#ibcon#read 6, iclass 6, count 0 2006.174.00:53:47.40#ibcon#end of sib2, iclass 6, count 0 2006.174.00:53:47.40#ibcon#*mode == 0, iclass 6, count 0 2006.174.00:53:47.40#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.174.00:53:47.40#ibcon#[27=USB\r\n] 2006.174.00:53:47.40#ibcon#*before write, iclass 6, count 0 2006.174.00:53:47.40#ibcon#enter sib2, iclass 6, count 0 2006.174.00:53:47.40#ibcon#flushed, iclass 6, count 0 2006.174.00:53:47.40#ibcon#about to write, iclass 6, count 0 2006.174.00:53:47.40#ibcon#wrote, iclass 6, count 0 2006.174.00:53:47.40#ibcon#about to read 3, iclass 6, count 0 2006.174.00:53:47.43#ibcon#read 3, iclass 6, count 0 2006.174.00:53:47.43#ibcon#about to read 4, iclass 6, count 0 2006.174.00:53:47.43#ibcon#read 4, iclass 6, count 0 2006.174.00:53:47.43#ibcon#about to read 5, iclass 6, count 0 2006.174.00:53:47.43#ibcon#read 5, iclass 6, count 0 2006.174.00:53:47.43#ibcon#about to read 6, iclass 6, count 0 2006.174.00:53:47.43#ibcon#read 6, iclass 6, count 0 2006.174.00:53:47.43#ibcon#end of sib2, iclass 6, count 0 2006.174.00:53:47.43#ibcon#*after write, iclass 6, count 0 2006.174.00:53:47.43#ibcon#*before return 0, iclass 6, count 0 2006.174.00:53:47.43#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.174.00:53:47.43#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.174.00:53:47.43#ibcon#about to clear, iclass 6 cls_cnt 0 2006.174.00:53:47.43#ibcon#cleared, iclass 6 cls_cnt 0 2006.174.00:53:47.43$vck44/vblo=5,709.99 2006.174.00:53:47.43#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.174.00:53:47.43#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.174.00:53:47.43#ibcon#ireg 17 cls_cnt 0 2006.174.00:53:47.43#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.174.00:53:47.43#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.174.00:53:47.43#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.174.00:53:47.43#ibcon#enter wrdev, iclass 10, count 0 2006.174.00:53:47.43#ibcon#first serial, iclass 10, count 0 2006.174.00:53:47.43#ibcon#enter sib2, iclass 10, count 0 2006.174.00:53:47.43#ibcon#flushed, iclass 10, count 0 2006.174.00:53:47.43#ibcon#about to write, iclass 10, count 0 2006.174.00:53:47.43#ibcon#wrote, iclass 10, count 0 2006.174.00:53:47.43#ibcon#about to read 3, iclass 10, count 0 2006.174.00:53:47.45#ibcon#read 3, iclass 10, count 0 2006.174.00:53:47.45#ibcon#about to read 4, iclass 10, count 0 2006.174.00:53:47.45#ibcon#read 4, iclass 10, count 0 2006.174.00:53:47.45#ibcon#about to read 5, iclass 10, count 0 2006.174.00:53:47.45#ibcon#read 5, iclass 10, count 0 2006.174.00:53:47.45#ibcon#about to read 6, iclass 10, count 0 2006.174.00:53:47.45#ibcon#read 6, iclass 10, count 0 2006.174.00:53:47.45#ibcon#end of sib2, iclass 10, count 0 2006.174.00:53:47.45#ibcon#*mode == 0, iclass 10, count 0 2006.174.00:53:47.45#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.174.00:53:47.45#ibcon#[28=FRQ=05,709.99\r\n] 2006.174.00:53:47.45#ibcon#*before write, iclass 10, count 0 2006.174.00:53:47.45#ibcon#enter sib2, iclass 10, count 0 2006.174.00:53:47.45#ibcon#flushed, iclass 10, count 0 2006.174.00:53:47.45#ibcon#about to write, iclass 10, count 0 2006.174.00:53:47.45#ibcon#wrote, iclass 10, count 0 2006.174.00:53:47.45#ibcon#about to read 3, iclass 10, count 0 2006.174.00:53:47.49#ibcon#read 3, iclass 10, count 0 2006.174.00:53:47.49#ibcon#about to read 4, iclass 10, count 0 2006.174.00:53:47.49#ibcon#read 4, iclass 10, count 0 2006.174.00:53:47.49#ibcon#about to read 5, iclass 10, count 0 2006.174.00:53:47.49#ibcon#read 5, iclass 10, count 0 2006.174.00:53:47.49#ibcon#about to read 6, iclass 10, count 0 2006.174.00:53:47.49#ibcon#read 6, iclass 10, count 0 2006.174.00:53:47.49#ibcon#end of sib2, iclass 10, count 0 2006.174.00:53:47.49#ibcon#*after write, iclass 10, count 0 2006.174.00:53:47.49#ibcon#*before return 0, iclass 10, count 0 2006.174.00:53:47.49#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.174.00:53:47.49#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.174.00:53:47.49#ibcon#about to clear, iclass 10 cls_cnt 0 2006.174.00:53:47.49#ibcon#cleared, iclass 10 cls_cnt 0 2006.174.00:53:47.49$vck44/vb=5,4 2006.174.00:53:47.49#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.174.00:53:47.49#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.174.00:53:47.49#ibcon#ireg 11 cls_cnt 2 2006.174.00:53:47.49#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.174.00:53:47.55#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.174.00:53:47.55#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.174.00:53:47.55#ibcon#enter wrdev, iclass 12, count 2 2006.174.00:53:47.55#ibcon#first serial, iclass 12, count 2 2006.174.00:53:47.55#ibcon#enter sib2, iclass 12, count 2 2006.174.00:53:47.55#ibcon#flushed, iclass 12, count 2 2006.174.00:53:47.55#ibcon#about to write, iclass 12, count 2 2006.174.00:53:47.55#ibcon#wrote, iclass 12, count 2 2006.174.00:53:47.55#ibcon#about to read 3, iclass 12, count 2 2006.174.00:53:47.57#ibcon#read 3, iclass 12, count 2 2006.174.00:53:47.57#ibcon#about to read 4, iclass 12, count 2 2006.174.00:53:47.57#ibcon#read 4, iclass 12, count 2 2006.174.00:53:47.57#ibcon#about to read 5, iclass 12, count 2 2006.174.00:53:47.57#ibcon#read 5, iclass 12, count 2 2006.174.00:53:47.57#ibcon#about to read 6, iclass 12, count 2 2006.174.00:53:47.57#ibcon#read 6, iclass 12, count 2 2006.174.00:53:47.57#ibcon#end of sib2, iclass 12, count 2 2006.174.00:53:47.57#ibcon#*mode == 0, iclass 12, count 2 2006.174.00:53:47.57#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.174.00:53:47.57#ibcon#[27=AT05-04\r\n] 2006.174.00:53:47.57#ibcon#*before write, iclass 12, count 2 2006.174.00:53:47.57#ibcon#enter sib2, iclass 12, count 2 2006.174.00:53:47.57#ibcon#flushed, iclass 12, count 2 2006.174.00:53:47.57#ibcon#about to write, iclass 12, count 2 2006.174.00:53:47.57#ibcon#wrote, iclass 12, count 2 2006.174.00:53:47.57#ibcon#about to read 3, iclass 12, count 2 2006.174.00:53:47.60#ibcon#read 3, iclass 12, count 2 2006.174.00:53:47.60#ibcon#about to read 4, iclass 12, count 2 2006.174.00:53:47.60#ibcon#read 4, iclass 12, count 2 2006.174.00:53:47.60#ibcon#about to read 5, iclass 12, count 2 2006.174.00:53:47.60#ibcon#read 5, iclass 12, count 2 2006.174.00:53:47.60#ibcon#about to read 6, iclass 12, count 2 2006.174.00:53:47.60#ibcon#read 6, iclass 12, count 2 2006.174.00:53:47.60#ibcon#end of sib2, iclass 12, count 2 2006.174.00:53:47.60#ibcon#*after write, iclass 12, count 2 2006.174.00:53:47.60#ibcon#*before return 0, iclass 12, count 2 2006.174.00:53:47.60#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.174.00:53:47.60#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.174.00:53:47.60#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.174.00:53:47.60#ibcon#ireg 7 cls_cnt 0 2006.174.00:53:47.60#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.174.00:53:47.72#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.174.00:53:47.72#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.174.00:53:47.72#ibcon#enter wrdev, iclass 12, count 0 2006.174.00:53:47.72#ibcon#first serial, iclass 12, count 0 2006.174.00:53:47.72#ibcon#enter sib2, iclass 12, count 0 2006.174.00:53:47.72#ibcon#flushed, iclass 12, count 0 2006.174.00:53:47.72#ibcon#about to write, iclass 12, count 0 2006.174.00:53:47.72#ibcon#wrote, iclass 12, count 0 2006.174.00:53:47.72#ibcon#about to read 3, iclass 12, count 0 2006.174.00:53:47.74#ibcon#read 3, iclass 12, count 0 2006.174.00:53:47.74#ibcon#about to read 4, iclass 12, count 0 2006.174.00:53:47.74#ibcon#read 4, iclass 12, count 0 2006.174.00:53:47.74#ibcon#about to read 5, iclass 12, count 0 2006.174.00:53:47.74#ibcon#read 5, iclass 12, count 0 2006.174.00:53:47.74#ibcon#about to read 6, iclass 12, count 0 2006.174.00:53:47.74#ibcon#read 6, iclass 12, count 0 2006.174.00:53:47.74#ibcon#end of sib2, iclass 12, count 0 2006.174.00:53:47.74#ibcon#*mode == 0, iclass 12, count 0 2006.174.00:53:47.74#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.174.00:53:47.74#ibcon#[27=USB\r\n] 2006.174.00:53:47.74#ibcon#*before write, iclass 12, count 0 2006.174.00:53:47.74#ibcon#enter sib2, iclass 12, count 0 2006.174.00:53:47.74#ibcon#flushed, iclass 12, count 0 2006.174.00:53:47.74#ibcon#about to write, iclass 12, count 0 2006.174.00:53:47.74#ibcon#wrote, iclass 12, count 0 2006.174.00:53:47.74#ibcon#about to read 3, iclass 12, count 0 2006.174.00:53:47.77#ibcon#read 3, iclass 12, count 0 2006.174.00:53:47.77#ibcon#about to read 4, iclass 12, count 0 2006.174.00:53:47.77#ibcon#read 4, iclass 12, count 0 2006.174.00:53:47.77#ibcon#about to read 5, iclass 12, count 0 2006.174.00:53:47.77#ibcon#read 5, iclass 12, count 0 2006.174.00:53:47.77#ibcon#about to read 6, iclass 12, count 0 2006.174.00:53:47.77#ibcon#read 6, iclass 12, count 0 2006.174.00:53:47.77#ibcon#end of sib2, iclass 12, count 0 2006.174.00:53:47.77#ibcon#*after write, iclass 12, count 0 2006.174.00:53:47.77#ibcon#*before return 0, iclass 12, count 0 2006.174.00:53:47.77#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.174.00:53:47.77#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.174.00:53:47.77#ibcon#about to clear, iclass 12 cls_cnt 0 2006.174.00:53:47.77#ibcon#cleared, iclass 12 cls_cnt 0 2006.174.00:53:47.77$vck44/vblo=6,719.99 2006.174.00:53:47.77#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.174.00:53:47.77#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.174.00:53:47.77#ibcon#ireg 17 cls_cnt 0 2006.174.00:53:47.77#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.174.00:53:47.77#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.174.00:53:47.77#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.174.00:53:47.77#ibcon#enter wrdev, iclass 14, count 0 2006.174.00:53:47.77#ibcon#first serial, iclass 14, count 0 2006.174.00:53:47.77#ibcon#enter sib2, iclass 14, count 0 2006.174.00:53:47.77#ibcon#flushed, iclass 14, count 0 2006.174.00:53:47.77#ibcon#about to write, iclass 14, count 0 2006.174.00:53:47.77#ibcon#wrote, iclass 14, count 0 2006.174.00:53:47.77#ibcon#about to read 3, iclass 14, count 0 2006.174.00:53:47.79#ibcon#read 3, iclass 14, count 0 2006.174.00:53:47.79#ibcon#about to read 4, iclass 14, count 0 2006.174.00:53:47.79#ibcon#read 4, iclass 14, count 0 2006.174.00:53:47.79#ibcon#about to read 5, iclass 14, count 0 2006.174.00:53:47.79#ibcon#read 5, iclass 14, count 0 2006.174.00:53:47.79#ibcon#about to read 6, iclass 14, count 0 2006.174.00:53:47.79#ibcon#read 6, iclass 14, count 0 2006.174.00:53:47.79#ibcon#end of sib2, iclass 14, count 0 2006.174.00:53:47.79#ibcon#*mode == 0, iclass 14, count 0 2006.174.00:53:47.79#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.174.00:53:47.79#ibcon#[28=FRQ=06,719.99\r\n] 2006.174.00:53:47.79#ibcon#*before write, iclass 14, count 0 2006.174.00:53:47.79#ibcon#enter sib2, iclass 14, count 0 2006.174.00:53:47.79#ibcon#flushed, iclass 14, count 0 2006.174.00:53:47.79#ibcon#about to write, iclass 14, count 0 2006.174.00:53:47.79#ibcon#wrote, iclass 14, count 0 2006.174.00:53:47.79#ibcon#about to read 3, iclass 14, count 0 2006.174.00:53:47.83#ibcon#read 3, iclass 14, count 0 2006.174.00:53:47.83#ibcon#about to read 4, iclass 14, count 0 2006.174.00:53:47.83#ibcon#read 4, iclass 14, count 0 2006.174.00:53:47.83#ibcon#about to read 5, iclass 14, count 0 2006.174.00:53:47.83#ibcon#read 5, iclass 14, count 0 2006.174.00:53:47.83#ibcon#about to read 6, iclass 14, count 0 2006.174.00:53:47.83#ibcon#read 6, iclass 14, count 0 2006.174.00:53:47.83#ibcon#end of sib2, iclass 14, count 0 2006.174.00:53:47.83#ibcon#*after write, iclass 14, count 0 2006.174.00:53:47.83#ibcon#*before return 0, iclass 14, count 0 2006.174.00:53:47.83#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.174.00:53:47.83#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.174.00:53:47.83#ibcon#about to clear, iclass 14 cls_cnt 0 2006.174.00:53:47.83#ibcon#cleared, iclass 14 cls_cnt 0 2006.174.00:53:47.83$vck44/vb=6,4 2006.174.00:53:47.83#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.174.00:53:47.83#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.174.00:53:47.83#ibcon#ireg 11 cls_cnt 2 2006.174.00:53:47.83#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.174.00:53:47.89#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.174.00:53:47.89#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.174.00:53:47.89#ibcon#enter wrdev, iclass 16, count 2 2006.174.00:53:47.89#ibcon#first serial, iclass 16, count 2 2006.174.00:53:47.89#ibcon#enter sib2, iclass 16, count 2 2006.174.00:53:47.89#ibcon#flushed, iclass 16, count 2 2006.174.00:53:47.89#ibcon#about to write, iclass 16, count 2 2006.174.00:53:47.89#ibcon#wrote, iclass 16, count 2 2006.174.00:53:47.89#ibcon#about to read 3, iclass 16, count 2 2006.174.00:53:47.91#ibcon#read 3, iclass 16, count 2 2006.174.00:53:47.91#ibcon#about to read 4, iclass 16, count 2 2006.174.00:53:47.91#ibcon#read 4, iclass 16, count 2 2006.174.00:53:47.91#ibcon#about to read 5, iclass 16, count 2 2006.174.00:53:47.91#ibcon#read 5, iclass 16, count 2 2006.174.00:53:47.91#ibcon#about to read 6, iclass 16, count 2 2006.174.00:53:47.91#ibcon#read 6, iclass 16, count 2 2006.174.00:53:47.91#ibcon#end of sib2, iclass 16, count 2 2006.174.00:53:47.91#ibcon#*mode == 0, iclass 16, count 2 2006.174.00:53:47.91#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.174.00:53:47.91#ibcon#[27=AT06-04\r\n] 2006.174.00:53:47.91#ibcon#*before write, iclass 16, count 2 2006.174.00:53:47.91#ibcon#enter sib2, iclass 16, count 2 2006.174.00:53:47.91#ibcon#flushed, iclass 16, count 2 2006.174.00:53:47.91#ibcon#about to write, iclass 16, count 2 2006.174.00:53:47.91#ibcon#wrote, iclass 16, count 2 2006.174.00:53:47.91#ibcon#about to read 3, iclass 16, count 2 2006.174.00:53:47.94#ibcon#read 3, iclass 16, count 2 2006.174.00:53:47.94#ibcon#about to read 4, iclass 16, count 2 2006.174.00:53:47.94#ibcon#read 4, iclass 16, count 2 2006.174.00:53:47.94#ibcon#about to read 5, iclass 16, count 2 2006.174.00:53:47.94#ibcon#read 5, iclass 16, count 2 2006.174.00:53:47.94#ibcon#about to read 6, iclass 16, count 2 2006.174.00:53:47.94#ibcon#read 6, iclass 16, count 2 2006.174.00:53:47.94#ibcon#end of sib2, iclass 16, count 2 2006.174.00:53:47.94#ibcon#*after write, iclass 16, count 2 2006.174.00:53:47.94#ibcon#*before return 0, iclass 16, count 2 2006.174.00:53:47.94#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.174.00:53:47.94#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.174.00:53:47.94#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.174.00:53:47.94#ibcon#ireg 7 cls_cnt 0 2006.174.00:53:47.94#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.174.00:53:48.06#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.174.00:53:48.06#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.174.00:53:48.06#ibcon#enter wrdev, iclass 16, count 0 2006.174.00:53:48.06#ibcon#first serial, iclass 16, count 0 2006.174.00:53:48.06#ibcon#enter sib2, iclass 16, count 0 2006.174.00:53:48.06#ibcon#flushed, iclass 16, count 0 2006.174.00:53:48.06#ibcon#about to write, iclass 16, count 0 2006.174.00:53:48.06#ibcon#wrote, iclass 16, count 0 2006.174.00:53:48.06#ibcon#about to read 3, iclass 16, count 0 2006.174.00:53:48.08#ibcon#read 3, iclass 16, count 0 2006.174.00:53:48.08#ibcon#about to read 4, iclass 16, count 0 2006.174.00:53:48.08#ibcon#read 4, iclass 16, count 0 2006.174.00:53:48.08#ibcon#about to read 5, iclass 16, count 0 2006.174.00:53:48.08#ibcon#read 5, iclass 16, count 0 2006.174.00:53:48.08#ibcon#about to read 6, iclass 16, count 0 2006.174.00:53:48.08#ibcon#read 6, iclass 16, count 0 2006.174.00:53:48.08#ibcon#end of sib2, iclass 16, count 0 2006.174.00:53:48.08#ibcon#*mode == 0, iclass 16, count 0 2006.174.00:53:48.08#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.174.00:53:48.08#ibcon#[27=USB\r\n] 2006.174.00:53:48.08#ibcon#*before write, iclass 16, count 0 2006.174.00:53:48.08#ibcon#enter sib2, iclass 16, count 0 2006.174.00:53:48.08#ibcon#flushed, iclass 16, count 0 2006.174.00:53:48.08#ibcon#about to write, iclass 16, count 0 2006.174.00:53:48.08#ibcon#wrote, iclass 16, count 0 2006.174.00:53:48.08#ibcon#about to read 3, iclass 16, count 0 2006.174.00:53:48.11#ibcon#read 3, iclass 16, count 0 2006.174.00:53:48.11#ibcon#about to read 4, iclass 16, count 0 2006.174.00:53:48.11#ibcon#read 4, iclass 16, count 0 2006.174.00:53:48.11#ibcon#about to read 5, iclass 16, count 0 2006.174.00:53:48.11#ibcon#read 5, iclass 16, count 0 2006.174.00:53:48.11#ibcon#about to read 6, iclass 16, count 0 2006.174.00:53:48.11#ibcon#read 6, iclass 16, count 0 2006.174.00:53:48.11#ibcon#end of sib2, iclass 16, count 0 2006.174.00:53:48.11#ibcon#*after write, iclass 16, count 0 2006.174.00:53:48.11#ibcon#*before return 0, iclass 16, count 0 2006.174.00:53:48.11#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.174.00:53:48.11#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.174.00:53:48.11#ibcon#about to clear, iclass 16 cls_cnt 0 2006.174.00:53:48.11#ibcon#cleared, iclass 16 cls_cnt 0 2006.174.00:53:48.11$vck44/vblo=7,734.99 2006.174.00:53:48.11#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.174.00:53:48.11#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.174.00:53:48.11#ibcon#ireg 17 cls_cnt 0 2006.174.00:53:48.11#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.174.00:53:48.11#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.174.00:53:48.11#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.174.00:53:48.11#ibcon#enter wrdev, iclass 18, count 0 2006.174.00:53:48.11#ibcon#first serial, iclass 18, count 0 2006.174.00:53:48.11#ibcon#enter sib2, iclass 18, count 0 2006.174.00:53:48.11#ibcon#flushed, iclass 18, count 0 2006.174.00:53:48.11#ibcon#about to write, iclass 18, count 0 2006.174.00:53:48.11#ibcon#wrote, iclass 18, count 0 2006.174.00:53:48.11#ibcon#about to read 3, iclass 18, count 0 2006.174.00:53:48.13#ibcon#read 3, iclass 18, count 0 2006.174.00:53:48.13#ibcon#about to read 4, iclass 18, count 0 2006.174.00:53:48.13#ibcon#read 4, iclass 18, count 0 2006.174.00:53:48.13#ibcon#about to read 5, iclass 18, count 0 2006.174.00:53:48.13#ibcon#read 5, iclass 18, count 0 2006.174.00:53:48.13#ibcon#about to read 6, iclass 18, count 0 2006.174.00:53:48.13#ibcon#read 6, iclass 18, count 0 2006.174.00:53:48.13#ibcon#end of sib2, iclass 18, count 0 2006.174.00:53:48.13#ibcon#*mode == 0, iclass 18, count 0 2006.174.00:53:48.13#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.174.00:53:48.13#ibcon#[28=FRQ=07,734.99\r\n] 2006.174.00:53:48.13#ibcon#*before write, iclass 18, count 0 2006.174.00:53:48.13#ibcon#enter sib2, iclass 18, count 0 2006.174.00:53:48.13#ibcon#flushed, iclass 18, count 0 2006.174.00:53:48.13#ibcon#about to write, iclass 18, count 0 2006.174.00:53:48.13#ibcon#wrote, iclass 18, count 0 2006.174.00:53:48.13#ibcon#about to read 3, iclass 18, count 0 2006.174.00:53:48.17#ibcon#read 3, iclass 18, count 0 2006.174.00:53:48.17#ibcon#about to read 4, iclass 18, count 0 2006.174.00:53:48.17#ibcon#read 4, iclass 18, count 0 2006.174.00:53:48.17#ibcon#about to read 5, iclass 18, count 0 2006.174.00:53:48.17#ibcon#read 5, iclass 18, count 0 2006.174.00:53:48.17#ibcon#about to read 6, iclass 18, count 0 2006.174.00:53:48.17#ibcon#read 6, iclass 18, count 0 2006.174.00:53:48.17#ibcon#end of sib2, iclass 18, count 0 2006.174.00:53:48.17#ibcon#*after write, iclass 18, count 0 2006.174.00:53:48.17#ibcon#*before return 0, iclass 18, count 0 2006.174.00:53:48.17#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.174.00:53:48.17#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.174.00:53:48.17#ibcon#about to clear, iclass 18 cls_cnt 0 2006.174.00:53:48.17#ibcon#cleared, iclass 18 cls_cnt 0 2006.174.00:53:48.17$vck44/vb=7,4 2006.174.00:53:48.17#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.174.00:53:48.17#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.174.00:53:48.17#ibcon#ireg 11 cls_cnt 2 2006.174.00:53:48.17#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.174.00:53:48.23#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.174.00:53:48.23#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.174.00:53:48.23#ibcon#enter wrdev, iclass 20, count 2 2006.174.00:53:48.23#ibcon#first serial, iclass 20, count 2 2006.174.00:53:48.23#ibcon#enter sib2, iclass 20, count 2 2006.174.00:53:48.23#ibcon#flushed, iclass 20, count 2 2006.174.00:53:48.23#ibcon#about to write, iclass 20, count 2 2006.174.00:53:48.23#ibcon#wrote, iclass 20, count 2 2006.174.00:53:48.23#ibcon#about to read 3, iclass 20, count 2 2006.174.00:53:48.25#ibcon#read 3, iclass 20, count 2 2006.174.00:53:48.25#ibcon#about to read 4, iclass 20, count 2 2006.174.00:53:48.25#ibcon#read 4, iclass 20, count 2 2006.174.00:53:48.25#ibcon#about to read 5, iclass 20, count 2 2006.174.00:53:48.25#ibcon#read 5, iclass 20, count 2 2006.174.00:53:48.25#ibcon#about to read 6, iclass 20, count 2 2006.174.00:53:48.25#ibcon#read 6, iclass 20, count 2 2006.174.00:53:48.25#ibcon#end of sib2, iclass 20, count 2 2006.174.00:53:48.25#ibcon#*mode == 0, iclass 20, count 2 2006.174.00:53:48.25#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.174.00:53:48.25#ibcon#[27=AT07-04\r\n] 2006.174.00:53:48.25#ibcon#*before write, iclass 20, count 2 2006.174.00:53:48.25#ibcon#enter sib2, iclass 20, count 2 2006.174.00:53:48.25#ibcon#flushed, iclass 20, count 2 2006.174.00:53:48.25#ibcon#about to write, iclass 20, count 2 2006.174.00:53:48.25#ibcon#wrote, iclass 20, count 2 2006.174.00:53:48.25#ibcon#about to read 3, iclass 20, count 2 2006.174.00:53:48.28#ibcon#read 3, iclass 20, count 2 2006.174.00:53:48.28#ibcon#about to read 4, iclass 20, count 2 2006.174.00:53:48.28#ibcon#read 4, iclass 20, count 2 2006.174.00:53:48.28#ibcon#about to read 5, iclass 20, count 2 2006.174.00:53:48.28#ibcon#read 5, iclass 20, count 2 2006.174.00:53:48.28#ibcon#about to read 6, iclass 20, count 2 2006.174.00:53:48.28#ibcon#read 6, iclass 20, count 2 2006.174.00:53:48.28#ibcon#end of sib2, iclass 20, count 2 2006.174.00:53:48.28#ibcon#*after write, iclass 20, count 2 2006.174.00:53:48.28#ibcon#*before return 0, iclass 20, count 2 2006.174.00:53:48.28#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.174.00:53:48.28#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.174.00:53:48.28#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.174.00:53:48.28#ibcon#ireg 7 cls_cnt 0 2006.174.00:53:48.28#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.174.00:53:48.40#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.174.00:53:48.40#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.174.00:53:48.40#ibcon#enter wrdev, iclass 20, count 0 2006.174.00:53:48.40#ibcon#first serial, iclass 20, count 0 2006.174.00:53:48.40#ibcon#enter sib2, iclass 20, count 0 2006.174.00:53:48.40#ibcon#flushed, iclass 20, count 0 2006.174.00:53:48.40#ibcon#about to write, iclass 20, count 0 2006.174.00:53:48.40#ibcon#wrote, iclass 20, count 0 2006.174.00:53:48.40#ibcon#about to read 3, iclass 20, count 0 2006.174.00:53:48.42#ibcon#read 3, iclass 20, count 0 2006.174.00:53:48.42#ibcon#about to read 4, iclass 20, count 0 2006.174.00:53:48.42#ibcon#read 4, iclass 20, count 0 2006.174.00:53:48.42#ibcon#about to read 5, iclass 20, count 0 2006.174.00:53:48.42#ibcon#read 5, iclass 20, count 0 2006.174.00:53:48.42#ibcon#about to read 6, iclass 20, count 0 2006.174.00:53:48.42#ibcon#read 6, iclass 20, count 0 2006.174.00:53:48.42#ibcon#end of sib2, iclass 20, count 0 2006.174.00:53:48.42#ibcon#*mode == 0, iclass 20, count 0 2006.174.00:53:48.42#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.174.00:53:48.42#ibcon#[27=USB\r\n] 2006.174.00:53:48.42#ibcon#*before write, iclass 20, count 0 2006.174.00:53:48.42#ibcon#enter sib2, iclass 20, count 0 2006.174.00:53:48.42#ibcon#flushed, iclass 20, count 0 2006.174.00:53:48.42#ibcon#about to write, iclass 20, count 0 2006.174.00:53:48.42#ibcon#wrote, iclass 20, count 0 2006.174.00:53:48.42#ibcon#about to read 3, iclass 20, count 0 2006.174.00:53:48.45#ibcon#read 3, iclass 20, count 0 2006.174.00:53:48.45#ibcon#about to read 4, iclass 20, count 0 2006.174.00:53:48.45#ibcon#read 4, iclass 20, count 0 2006.174.00:53:48.45#ibcon#about to read 5, iclass 20, count 0 2006.174.00:53:48.45#ibcon#read 5, iclass 20, count 0 2006.174.00:53:48.45#ibcon#about to read 6, iclass 20, count 0 2006.174.00:53:48.45#ibcon#read 6, iclass 20, count 0 2006.174.00:53:48.45#ibcon#end of sib2, iclass 20, count 0 2006.174.00:53:48.45#ibcon#*after write, iclass 20, count 0 2006.174.00:53:48.45#ibcon#*before return 0, iclass 20, count 0 2006.174.00:53:48.45#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.174.00:53:48.45#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.174.00:53:48.45#ibcon#about to clear, iclass 20 cls_cnt 0 2006.174.00:53:48.45#ibcon#cleared, iclass 20 cls_cnt 0 2006.174.00:53:48.45$vck44/vblo=8,744.99 2006.174.00:53:48.45#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.174.00:53:48.45#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.174.00:53:48.45#ibcon#ireg 17 cls_cnt 0 2006.174.00:53:48.45#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.174.00:53:48.45#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.174.00:53:48.45#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.174.00:53:48.45#ibcon#enter wrdev, iclass 22, count 0 2006.174.00:53:48.45#ibcon#first serial, iclass 22, count 0 2006.174.00:53:48.45#ibcon#enter sib2, iclass 22, count 0 2006.174.00:53:48.45#ibcon#flushed, iclass 22, count 0 2006.174.00:53:48.45#ibcon#about to write, iclass 22, count 0 2006.174.00:53:48.45#ibcon#wrote, iclass 22, count 0 2006.174.00:53:48.45#ibcon#about to read 3, iclass 22, count 0 2006.174.00:53:48.47#ibcon#read 3, iclass 22, count 0 2006.174.00:53:48.47#ibcon#about to read 4, iclass 22, count 0 2006.174.00:53:48.47#ibcon#read 4, iclass 22, count 0 2006.174.00:53:48.47#ibcon#about to read 5, iclass 22, count 0 2006.174.00:53:48.47#ibcon#read 5, iclass 22, count 0 2006.174.00:53:48.47#ibcon#about to read 6, iclass 22, count 0 2006.174.00:53:48.47#ibcon#read 6, iclass 22, count 0 2006.174.00:53:48.47#ibcon#end of sib2, iclass 22, count 0 2006.174.00:53:48.47#ibcon#*mode == 0, iclass 22, count 0 2006.174.00:53:48.47#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.174.00:53:48.47#ibcon#[28=FRQ=08,744.99\r\n] 2006.174.00:53:48.47#ibcon#*before write, iclass 22, count 0 2006.174.00:53:48.47#ibcon#enter sib2, iclass 22, count 0 2006.174.00:53:48.47#ibcon#flushed, iclass 22, count 0 2006.174.00:53:48.47#ibcon#about to write, iclass 22, count 0 2006.174.00:53:48.47#ibcon#wrote, iclass 22, count 0 2006.174.00:53:48.47#ibcon#about to read 3, iclass 22, count 0 2006.174.00:53:48.51#ibcon#read 3, iclass 22, count 0 2006.174.00:53:48.51#ibcon#about to read 4, iclass 22, count 0 2006.174.00:53:48.51#ibcon#read 4, iclass 22, count 0 2006.174.00:53:48.51#ibcon#about to read 5, iclass 22, count 0 2006.174.00:53:48.51#ibcon#read 5, iclass 22, count 0 2006.174.00:53:48.51#ibcon#about to read 6, iclass 22, count 0 2006.174.00:53:48.51#ibcon#read 6, iclass 22, count 0 2006.174.00:53:48.51#ibcon#end of sib2, iclass 22, count 0 2006.174.00:53:48.51#ibcon#*after write, iclass 22, count 0 2006.174.00:53:48.51#ibcon#*before return 0, iclass 22, count 0 2006.174.00:53:48.51#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.174.00:53:48.51#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.174.00:53:48.51#ibcon#about to clear, iclass 22 cls_cnt 0 2006.174.00:53:48.51#ibcon#cleared, iclass 22 cls_cnt 0 2006.174.00:53:48.51$vck44/vb=8,4 2006.174.00:53:48.51#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.174.00:53:48.51#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.174.00:53:48.51#ibcon#ireg 11 cls_cnt 2 2006.174.00:53:48.51#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.174.00:53:48.57#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.174.00:53:48.57#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.174.00:53:48.57#ibcon#enter wrdev, iclass 24, count 2 2006.174.00:53:48.57#ibcon#first serial, iclass 24, count 2 2006.174.00:53:48.57#ibcon#enter sib2, iclass 24, count 2 2006.174.00:53:48.57#ibcon#flushed, iclass 24, count 2 2006.174.00:53:48.57#ibcon#about to write, iclass 24, count 2 2006.174.00:53:48.57#ibcon#wrote, iclass 24, count 2 2006.174.00:53:48.57#ibcon#about to read 3, iclass 24, count 2 2006.174.00:53:48.59#ibcon#read 3, iclass 24, count 2 2006.174.00:53:48.59#ibcon#about to read 4, iclass 24, count 2 2006.174.00:53:48.59#ibcon#read 4, iclass 24, count 2 2006.174.00:53:48.59#ibcon#about to read 5, iclass 24, count 2 2006.174.00:53:48.59#ibcon#read 5, iclass 24, count 2 2006.174.00:53:48.59#ibcon#about to read 6, iclass 24, count 2 2006.174.00:53:48.59#ibcon#read 6, iclass 24, count 2 2006.174.00:53:48.59#ibcon#end of sib2, iclass 24, count 2 2006.174.00:53:48.59#ibcon#*mode == 0, iclass 24, count 2 2006.174.00:53:48.59#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.174.00:53:48.59#ibcon#[27=AT08-04\r\n] 2006.174.00:53:48.59#ibcon#*before write, iclass 24, count 2 2006.174.00:53:48.59#ibcon#enter sib2, iclass 24, count 2 2006.174.00:53:48.59#ibcon#flushed, iclass 24, count 2 2006.174.00:53:48.59#ibcon#about to write, iclass 24, count 2 2006.174.00:53:48.59#ibcon#wrote, iclass 24, count 2 2006.174.00:53:48.59#ibcon#about to read 3, iclass 24, count 2 2006.174.00:53:48.62#ibcon#read 3, iclass 24, count 2 2006.174.00:53:48.62#ibcon#about to read 4, iclass 24, count 2 2006.174.00:53:48.62#ibcon#read 4, iclass 24, count 2 2006.174.00:53:48.62#ibcon#about to read 5, iclass 24, count 2 2006.174.00:53:48.62#ibcon#read 5, iclass 24, count 2 2006.174.00:53:48.62#ibcon#about to read 6, iclass 24, count 2 2006.174.00:53:48.62#ibcon#read 6, iclass 24, count 2 2006.174.00:53:48.62#ibcon#end of sib2, iclass 24, count 2 2006.174.00:53:48.62#ibcon#*after write, iclass 24, count 2 2006.174.00:53:48.62#ibcon#*before return 0, iclass 24, count 2 2006.174.00:53:48.62#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.174.00:53:48.62#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.174.00:53:48.62#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.174.00:53:48.62#ibcon#ireg 7 cls_cnt 0 2006.174.00:53:48.62#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.174.00:53:48.74#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.174.00:53:48.74#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.174.00:53:48.74#ibcon#enter wrdev, iclass 24, count 0 2006.174.00:53:48.74#ibcon#first serial, iclass 24, count 0 2006.174.00:53:48.74#ibcon#enter sib2, iclass 24, count 0 2006.174.00:53:48.74#ibcon#flushed, iclass 24, count 0 2006.174.00:53:48.74#ibcon#about to write, iclass 24, count 0 2006.174.00:53:48.74#ibcon#wrote, iclass 24, count 0 2006.174.00:53:48.74#ibcon#about to read 3, iclass 24, count 0 2006.174.00:53:48.76#ibcon#read 3, iclass 24, count 0 2006.174.00:53:48.76#ibcon#about to read 4, iclass 24, count 0 2006.174.00:53:48.76#ibcon#read 4, iclass 24, count 0 2006.174.00:53:48.76#ibcon#about to read 5, iclass 24, count 0 2006.174.00:53:48.76#ibcon#read 5, iclass 24, count 0 2006.174.00:53:48.76#ibcon#about to read 6, iclass 24, count 0 2006.174.00:53:48.76#ibcon#read 6, iclass 24, count 0 2006.174.00:53:48.76#ibcon#end of sib2, iclass 24, count 0 2006.174.00:53:48.76#ibcon#*mode == 0, iclass 24, count 0 2006.174.00:53:48.76#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.174.00:53:48.76#ibcon#[27=USB\r\n] 2006.174.00:53:48.76#ibcon#*before write, iclass 24, count 0 2006.174.00:53:48.76#ibcon#enter sib2, iclass 24, count 0 2006.174.00:53:48.76#ibcon#flushed, iclass 24, count 0 2006.174.00:53:48.76#ibcon#about to write, iclass 24, count 0 2006.174.00:53:48.76#ibcon#wrote, iclass 24, count 0 2006.174.00:53:48.76#ibcon#about to read 3, iclass 24, count 0 2006.174.00:53:48.79#ibcon#read 3, iclass 24, count 0 2006.174.00:53:48.79#ibcon#about to read 4, iclass 24, count 0 2006.174.00:53:48.79#ibcon#read 4, iclass 24, count 0 2006.174.00:53:48.79#ibcon#about to read 5, iclass 24, count 0 2006.174.00:53:48.79#ibcon#read 5, iclass 24, count 0 2006.174.00:53:48.79#ibcon#about to read 6, iclass 24, count 0 2006.174.00:53:48.79#ibcon#read 6, iclass 24, count 0 2006.174.00:53:48.79#ibcon#end of sib2, iclass 24, count 0 2006.174.00:53:48.79#ibcon#*after write, iclass 24, count 0 2006.174.00:53:48.79#ibcon#*before return 0, iclass 24, count 0 2006.174.00:53:48.79#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.174.00:53:48.79#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.174.00:53:48.79#ibcon#about to clear, iclass 24 cls_cnt 0 2006.174.00:53:48.79#ibcon#cleared, iclass 24 cls_cnt 0 2006.174.00:53:48.79$vck44/vabw=wide 2006.174.00:53:48.79#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.174.00:53:48.79#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.174.00:53:48.79#ibcon#ireg 8 cls_cnt 0 2006.174.00:53:48.79#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.174.00:53:48.79#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.174.00:53:48.79#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.174.00:53:48.79#ibcon#enter wrdev, iclass 26, count 0 2006.174.00:53:48.79#ibcon#first serial, iclass 26, count 0 2006.174.00:53:48.79#ibcon#enter sib2, iclass 26, count 0 2006.174.00:53:48.79#ibcon#flushed, iclass 26, count 0 2006.174.00:53:48.79#ibcon#about to write, iclass 26, count 0 2006.174.00:53:48.79#ibcon#wrote, iclass 26, count 0 2006.174.00:53:48.79#ibcon#about to read 3, iclass 26, count 0 2006.174.00:53:48.81#ibcon#read 3, iclass 26, count 0 2006.174.00:53:48.81#ibcon#about to read 4, iclass 26, count 0 2006.174.00:53:48.81#ibcon#read 4, iclass 26, count 0 2006.174.00:53:48.81#ibcon#about to read 5, iclass 26, count 0 2006.174.00:53:48.81#ibcon#read 5, iclass 26, count 0 2006.174.00:53:48.81#ibcon#about to read 6, iclass 26, count 0 2006.174.00:53:48.81#ibcon#read 6, iclass 26, count 0 2006.174.00:53:48.81#ibcon#end of sib2, iclass 26, count 0 2006.174.00:53:48.81#ibcon#*mode == 0, iclass 26, count 0 2006.174.00:53:48.81#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.174.00:53:48.81#ibcon#[25=BW32\r\n] 2006.174.00:53:48.81#ibcon#*before write, iclass 26, count 0 2006.174.00:53:48.81#ibcon#enter sib2, iclass 26, count 0 2006.174.00:53:48.81#ibcon#flushed, iclass 26, count 0 2006.174.00:53:48.81#ibcon#about to write, iclass 26, count 0 2006.174.00:53:48.81#ibcon#wrote, iclass 26, count 0 2006.174.00:53:48.81#ibcon#about to read 3, iclass 26, count 0 2006.174.00:53:48.84#ibcon#read 3, iclass 26, count 0 2006.174.00:53:48.84#ibcon#about to read 4, iclass 26, count 0 2006.174.00:53:48.84#ibcon#read 4, iclass 26, count 0 2006.174.00:53:48.84#ibcon#about to read 5, iclass 26, count 0 2006.174.00:53:48.84#ibcon#read 5, iclass 26, count 0 2006.174.00:53:48.84#ibcon#about to read 6, iclass 26, count 0 2006.174.00:53:48.84#ibcon#read 6, iclass 26, count 0 2006.174.00:53:48.84#ibcon#end of sib2, iclass 26, count 0 2006.174.00:53:48.84#ibcon#*after write, iclass 26, count 0 2006.174.00:53:48.84#ibcon#*before return 0, iclass 26, count 0 2006.174.00:53:48.84#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.174.00:53:48.84#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.174.00:53:48.84#ibcon#about to clear, iclass 26 cls_cnt 0 2006.174.00:53:48.84#ibcon#cleared, iclass 26 cls_cnt 0 2006.174.00:53:48.84$vck44/vbbw=wide 2006.174.00:53:48.84#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.174.00:53:48.84#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.174.00:53:48.84#ibcon#ireg 8 cls_cnt 0 2006.174.00:53:48.84#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.174.00:53:48.91#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.174.00:53:48.91#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.174.00:53:48.91#ibcon#enter wrdev, iclass 28, count 0 2006.174.00:53:48.91#ibcon#first serial, iclass 28, count 0 2006.174.00:53:48.91#ibcon#enter sib2, iclass 28, count 0 2006.174.00:53:48.91#ibcon#flushed, iclass 28, count 0 2006.174.00:53:48.91#ibcon#about to write, iclass 28, count 0 2006.174.00:53:48.91#ibcon#wrote, iclass 28, count 0 2006.174.00:53:48.91#ibcon#about to read 3, iclass 28, count 0 2006.174.00:53:48.93#ibcon#read 3, iclass 28, count 0 2006.174.00:53:48.93#ibcon#about to read 4, iclass 28, count 0 2006.174.00:53:48.93#ibcon#read 4, iclass 28, count 0 2006.174.00:53:48.93#ibcon#about to read 5, iclass 28, count 0 2006.174.00:53:48.93#ibcon#read 5, iclass 28, count 0 2006.174.00:53:48.93#ibcon#about to read 6, iclass 28, count 0 2006.174.00:53:48.93#ibcon#read 6, iclass 28, count 0 2006.174.00:53:48.93#ibcon#end of sib2, iclass 28, count 0 2006.174.00:53:48.93#ibcon#*mode == 0, iclass 28, count 0 2006.174.00:53:48.93#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.174.00:53:48.93#ibcon#[27=BW32\r\n] 2006.174.00:53:48.93#ibcon#*before write, iclass 28, count 0 2006.174.00:53:48.93#ibcon#enter sib2, iclass 28, count 0 2006.174.00:53:48.93#ibcon#flushed, iclass 28, count 0 2006.174.00:53:48.93#ibcon#about to write, iclass 28, count 0 2006.174.00:53:48.93#ibcon#wrote, iclass 28, count 0 2006.174.00:53:48.93#ibcon#about to read 3, iclass 28, count 0 2006.174.00:53:48.96#ibcon#read 3, iclass 28, count 0 2006.174.00:53:48.96#ibcon#about to read 4, iclass 28, count 0 2006.174.00:53:48.96#ibcon#read 4, iclass 28, count 0 2006.174.00:53:48.96#ibcon#about to read 5, iclass 28, count 0 2006.174.00:53:48.96#ibcon#read 5, iclass 28, count 0 2006.174.00:53:48.96#ibcon#about to read 6, iclass 28, count 0 2006.174.00:53:48.96#ibcon#read 6, iclass 28, count 0 2006.174.00:53:48.96#ibcon#end of sib2, iclass 28, count 0 2006.174.00:53:48.96#ibcon#*after write, iclass 28, count 0 2006.174.00:53:48.96#ibcon#*before return 0, iclass 28, count 0 2006.174.00:53:48.96#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.174.00:53:48.96#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.174.00:53:48.96#ibcon#about to clear, iclass 28 cls_cnt 0 2006.174.00:53:48.96#ibcon#cleared, iclass 28 cls_cnt 0 2006.174.00:53:48.96$setupk4/ifdk4 2006.174.00:53:48.96$ifdk4/lo= 2006.174.00:53:48.96$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.174.00:53:48.96$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.174.00:53:48.96$ifdk4/patch= 2006.174.00:53:48.96$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.174.00:53:48.96$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.174.00:53:48.96$setupk4/!*+20s 2006.174.00:53:52.45#abcon#<5=/10 1.1 2.8 24.92 821003.4\r\n> 2006.174.00:53:52.47#abcon#{5=INTERFACE CLEAR} 2006.174.00:53:52.53#abcon#[5=S1D000X0/0*\r\n] 2006.174.00:54:02.62#abcon#<5=/10 1.1 2.8 24.92 821003.4\r\n> 2006.174.00:54:02.64#abcon#{5=INTERFACE CLEAR} 2006.174.00:54:02.70#abcon#[5=S1D000X0/0*\r\n] 2006.174.00:54:03.46$setupk4/"tpicd 2006.174.00:54:03.46$setupk4/echo=off 2006.174.00:54:03.46$setupk4/xlog=off 2006.174.00:54:03.46:!2006.174.00:57:49 2006.174.00:54:19.14#trakl#Source acquired 2006.174.00:54:20.14#flagr#flagr/antenna,acquired 2006.174.00:57:49.02:preob 2006.174.00:57:50.14/onsource/TRACKING 2006.174.00:57:50.14:!2006.174.00:57:59 2006.174.00:57:59.02:"tape 2006.174.00:57:59.02:"st=record 2006.174.00:57:59.02:data_valid=on 2006.174.00:57:59.02:midob 2006.174.00:58:00.14/onsource/TRACKING 2006.174.00:58:00.14/wx/25.07,1003.5,81 2006.174.00:58:00.20/cable/+6.5035E-03 2006.174.00:58:01.29/va/01,07,usb,yes,34,37 2006.174.00:58:01.29/va/02,06,usb,yes,34,35 2006.174.00:58:01.29/va/03,05,usb,yes,43,45 2006.174.00:58:01.29/va/04,06,usb,yes,35,37 2006.174.00:58:01.29/va/05,04,usb,yes,27,28 2006.174.00:58:01.29/va/06,03,usb,yes,38,38 2006.174.00:58:01.29/va/07,04,usb,yes,31,32 2006.174.00:58:01.29/va/08,04,usb,yes,26,32 2006.174.00:58:01.52/valo/01,524.99,yes,locked 2006.174.00:58:01.52/valo/02,534.99,yes,locked 2006.174.00:58:01.52/valo/03,564.99,yes,locked 2006.174.00:58:01.52/valo/04,624.99,yes,locked 2006.174.00:58:01.52/valo/05,734.99,yes,locked 2006.174.00:58:01.52/valo/06,814.99,yes,locked 2006.174.00:58:01.52/valo/07,864.99,yes,locked 2006.174.00:58:01.52/valo/08,884.99,yes,locked 2006.174.00:58:02.61/vb/01,04,usb,yes,29,27 2006.174.00:58:02.61/vb/02,04,usb,yes,31,31 2006.174.00:58:02.61/vb/03,04,usb,yes,28,31 2006.174.00:58:02.61/vb/04,04,usb,yes,32,31 2006.174.00:58:02.61/vb/05,04,usb,yes,25,28 2006.174.00:58:02.61/vb/06,04,usb,yes,30,26 2006.174.00:58:02.61/vb/07,04,usb,yes,29,29 2006.174.00:58:02.61/vb/08,04,usb,yes,27,30 2006.174.00:58:02.84/vblo/01,629.99,yes,locked 2006.174.00:58:02.84/vblo/02,634.99,yes,locked 2006.174.00:58:02.84/vblo/03,649.99,yes,locked 2006.174.00:58:02.84/vblo/04,679.99,yes,locked 2006.174.00:58:02.84/vblo/05,709.99,yes,locked 2006.174.00:58:02.84/vblo/06,719.99,yes,locked 2006.174.00:58:02.84/vblo/07,734.99,yes,locked 2006.174.00:58:02.84/vblo/08,744.99,yes,locked 2006.174.00:58:02.99/vabw/8 2006.174.00:58:03.14/vbbw/8 2006.174.00:58:03.23/xfe/off,on,15.2 2006.174.00:58:03.62/ifatt/23,28,28,28 2006.174.00:58:04.07/fmout-gps/S +3.85E-07 2006.174.00:58:04.12:!2006.174.01:01:49 2006.174.01:01:49.01:data_valid=off 2006.174.01:01:49.01:"et 2006.174.01:01:49.01:!+3s 2006.174.01:01:52.02:"tape 2006.174.01:01:52.02:postob 2006.174.01:01:52.11/cable/+6.5050E-03 2006.174.01:01:52.11/wx/25.20,1003.5,82 2006.174.01:01:52.17/fmout-gps/S +3.85E-07 2006.174.01:01:52.17:scan_name=174-0111,jd0606,60 2006.174.01:01:52.17:source=0727-115,073019.11,-114112.6,2000.0,ccw 2006.174.01:01:54.14#flagr#flagr/antenna,new-source 2006.174.01:01:54.14:checkk5 2006.174.01:01:54.50/chk_autoobs//k5ts1/ autoobs is running! 2006.174.01:01:54.92/chk_autoobs//k5ts2/ autoobs is running! 2006.174.01:01:55.32/chk_autoobs//k5ts3/ autoobs is running! 2006.174.01:01:55.72/chk_autoobs//k5ts4/ autoobs is running! 2006.174.01:01:56.10/chk_obsdata//k5ts1/T1740057??a.dat file size is correct (nominal:920MB, actual:916MB). 2006.174.01:01:56.51/chk_obsdata//k5ts2/T1740057??b.dat file size is correct (nominal:920MB, actual:916MB). 2006.174.01:01:56.90/chk_obsdata//k5ts3/T1740057??c.dat file size is correct (nominal:920MB, actual:916MB). 2006.174.01:01:57.30/chk_obsdata//k5ts4/T1740057??d.dat file size is correct (nominal:920MB, actual:916MB). 2006.174.01:01:58.02/k5log//k5ts1_log_newline 2006.174.01:01:58.73/k5log//k5ts2_log_newline 2006.174.01:01:59.44/k5log//k5ts3_log_newline 2006.174.01:02:00.14/k5log//k5ts4_log_newline 2006.174.01:02:00.17/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.174.01:02:00.17:setupk4=1 2006.174.01:02:00.17$setupk4/echo=on 2006.174.01:02:00.17$setupk4/pcalon 2006.174.01:02:00.17$pcalon/"no phase cal control is implemented here 2006.174.01:02:00.17$setupk4/"tpicd=stop 2006.174.01:02:00.17$setupk4/"rec=synch_on 2006.174.01:02:00.17$setupk4/"rec_mode=128 2006.174.01:02:00.17$setupk4/!* 2006.174.01:02:00.17$setupk4/recpk4 2006.174.01:02:00.17$recpk4/recpatch= 2006.174.01:02:00.17$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.174.01:02:00.17$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.174.01:02:00.17$setupk4/vck44 2006.174.01:02:00.17$vck44/valo=1,524.99 2006.174.01:02:00.17#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.174.01:02:00.17#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.174.01:02:00.17#ibcon#ireg 17 cls_cnt 0 2006.174.01:02:00.17#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.174.01:02:00.17#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.174.01:02:00.17#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.174.01:02:00.17#ibcon#enter wrdev, iclass 7, count 0 2006.174.01:02:00.17#ibcon#first serial, iclass 7, count 0 2006.174.01:02:00.17#ibcon#enter sib2, iclass 7, count 0 2006.174.01:02:00.17#ibcon#flushed, iclass 7, count 0 2006.174.01:02:00.17#ibcon#about to write, iclass 7, count 0 2006.174.01:02:00.17#ibcon#wrote, iclass 7, count 0 2006.174.01:02:00.17#ibcon#about to read 3, iclass 7, count 0 2006.174.01:02:00.18#ibcon#read 3, iclass 7, count 0 2006.174.01:02:00.18#ibcon#about to read 4, iclass 7, count 0 2006.174.01:02:00.18#ibcon#read 4, iclass 7, count 0 2006.174.01:02:00.18#ibcon#about to read 5, iclass 7, count 0 2006.174.01:02:00.18#ibcon#read 5, iclass 7, count 0 2006.174.01:02:00.18#ibcon#about to read 6, iclass 7, count 0 2006.174.01:02:00.18#ibcon#read 6, iclass 7, count 0 2006.174.01:02:00.18#ibcon#end of sib2, iclass 7, count 0 2006.174.01:02:00.18#ibcon#*mode == 0, iclass 7, count 0 2006.174.01:02:00.18#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.174.01:02:00.18#ibcon#[26=FRQ=01,524.99\r\n] 2006.174.01:02:00.18#ibcon#*before write, iclass 7, count 0 2006.174.01:02:00.18#ibcon#enter sib2, iclass 7, count 0 2006.174.01:02:00.18#ibcon#flushed, iclass 7, count 0 2006.174.01:02:00.18#ibcon#about to write, iclass 7, count 0 2006.174.01:02:00.18#ibcon#wrote, iclass 7, count 0 2006.174.01:02:00.18#ibcon#about to read 3, iclass 7, count 0 2006.174.01:02:00.23#ibcon#read 3, iclass 7, count 0 2006.174.01:02:00.23#ibcon#about to read 4, iclass 7, count 0 2006.174.01:02:00.23#ibcon#read 4, iclass 7, count 0 2006.174.01:02:00.23#ibcon#about to read 5, iclass 7, count 0 2006.174.01:02:00.23#ibcon#read 5, iclass 7, count 0 2006.174.01:02:00.23#ibcon#about to read 6, iclass 7, count 0 2006.174.01:02:00.23#ibcon#read 6, iclass 7, count 0 2006.174.01:02:00.23#ibcon#end of sib2, iclass 7, count 0 2006.174.01:02:00.23#ibcon#*after write, iclass 7, count 0 2006.174.01:02:00.23#ibcon#*before return 0, iclass 7, count 0 2006.174.01:02:00.23#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.174.01:02:00.23#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.174.01:02:00.23#ibcon#about to clear, iclass 7 cls_cnt 0 2006.174.01:02:00.23#ibcon#cleared, iclass 7 cls_cnt 0 2006.174.01:02:00.23$vck44/va=1,7 2006.174.01:02:00.23#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.174.01:02:00.23#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.174.01:02:00.23#ibcon#ireg 11 cls_cnt 2 2006.174.01:02:00.23#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.174.01:02:00.23#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.174.01:02:00.23#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.174.01:02:00.23#ibcon#enter wrdev, iclass 11, count 2 2006.174.01:02:00.23#ibcon#first serial, iclass 11, count 2 2006.174.01:02:00.23#ibcon#enter sib2, iclass 11, count 2 2006.174.01:02:00.23#ibcon#flushed, iclass 11, count 2 2006.174.01:02:00.23#ibcon#about to write, iclass 11, count 2 2006.174.01:02:00.23#ibcon#wrote, iclass 11, count 2 2006.174.01:02:00.23#ibcon#about to read 3, iclass 11, count 2 2006.174.01:02:00.25#ibcon#read 3, iclass 11, count 2 2006.174.01:02:00.25#ibcon#about to read 4, iclass 11, count 2 2006.174.01:02:00.25#ibcon#read 4, iclass 11, count 2 2006.174.01:02:00.25#ibcon#about to read 5, iclass 11, count 2 2006.174.01:02:00.25#ibcon#read 5, iclass 11, count 2 2006.174.01:02:00.25#ibcon#about to read 6, iclass 11, count 2 2006.174.01:02:00.25#ibcon#read 6, iclass 11, count 2 2006.174.01:02:00.25#ibcon#end of sib2, iclass 11, count 2 2006.174.01:02:00.25#ibcon#*mode == 0, iclass 11, count 2 2006.174.01:02:00.25#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.174.01:02:00.25#ibcon#[25=AT01-07\r\n] 2006.174.01:02:00.25#ibcon#*before write, iclass 11, count 2 2006.174.01:02:00.25#ibcon#enter sib2, iclass 11, count 2 2006.174.01:02:00.25#ibcon#flushed, iclass 11, count 2 2006.174.01:02:00.25#ibcon#about to write, iclass 11, count 2 2006.174.01:02:00.25#ibcon#wrote, iclass 11, count 2 2006.174.01:02:00.25#ibcon#about to read 3, iclass 11, count 2 2006.174.01:02:00.28#ibcon#read 3, iclass 11, count 2 2006.174.01:02:00.28#ibcon#about to read 4, iclass 11, count 2 2006.174.01:02:00.28#ibcon#read 4, iclass 11, count 2 2006.174.01:02:00.28#ibcon#about to read 5, iclass 11, count 2 2006.174.01:02:00.28#ibcon#read 5, iclass 11, count 2 2006.174.01:02:00.28#ibcon#about to read 6, iclass 11, count 2 2006.174.01:02:00.28#ibcon#read 6, iclass 11, count 2 2006.174.01:02:00.28#ibcon#end of sib2, iclass 11, count 2 2006.174.01:02:00.28#ibcon#*after write, iclass 11, count 2 2006.174.01:02:00.28#ibcon#*before return 0, iclass 11, count 2 2006.174.01:02:00.28#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.174.01:02:00.28#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.174.01:02:00.28#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.174.01:02:00.28#ibcon#ireg 7 cls_cnt 0 2006.174.01:02:00.28#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.174.01:02:00.40#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.174.01:02:00.40#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.174.01:02:00.40#ibcon#enter wrdev, iclass 11, count 0 2006.174.01:02:00.40#ibcon#first serial, iclass 11, count 0 2006.174.01:02:00.40#ibcon#enter sib2, iclass 11, count 0 2006.174.01:02:00.40#ibcon#flushed, iclass 11, count 0 2006.174.01:02:00.40#ibcon#about to write, iclass 11, count 0 2006.174.01:02:00.40#ibcon#wrote, iclass 11, count 0 2006.174.01:02:00.40#ibcon#about to read 3, iclass 11, count 0 2006.174.01:02:00.42#ibcon#read 3, iclass 11, count 0 2006.174.01:02:00.42#ibcon#about to read 4, iclass 11, count 0 2006.174.01:02:00.42#ibcon#read 4, iclass 11, count 0 2006.174.01:02:00.42#ibcon#about to read 5, iclass 11, count 0 2006.174.01:02:00.42#ibcon#read 5, iclass 11, count 0 2006.174.01:02:00.42#ibcon#about to read 6, iclass 11, count 0 2006.174.01:02:00.42#ibcon#read 6, iclass 11, count 0 2006.174.01:02:00.42#ibcon#end of sib2, iclass 11, count 0 2006.174.01:02:00.42#ibcon#*mode == 0, iclass 11, count 0 2006.174.01:02:00.42#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.174.01:02:00.42#ibcon#[25=USB\r\n] 2006.174.01:02:00.42#ibcon#*before write, iclass 11, count 0 2006.174.01:02:00.42#ibcon#enter sib2, iclass 11, count 0 2006.174.01:02:00.42#ibcon#flushed, iclass 11, count 0 2006.174.01:02:00.42#ibcon#about to write, iclass 11, count 0 2006.174.01:02:00.42#ibcon#wrote, iclass 11, count 0 2006.174.01:02:00.42#ibcon#about to read 3, iclass 11, count 0 2006.174.01:02:00.45#ibcon#read 3, iclass 11, count 0 2006.174.01:02:00.45#ibcon#about to read 4, iclass 11, count 0 2006.174.01:02:00.45#ibcon#read 4, iclass 11, count 0 2006.174.01:02:00.45#ibcon#about to read 5, iclass 11, count 0 2006.174.01:02:00.45#ibcon#read 5, iclass 11, count 0 2006.174.01:02:00.45#ibcon#about to read 6, iclass 11, count 0 2006.174.01:02:00.45#ibcon#read 6, iclass 11, count 0 2006.174.01:02:00.45#ibcon#end of sib2, iclass 11, count 0 2006.174.01:02:00.45#ibcon#*after write, iclass 11, count 0 2006.174.01:02:00.45#ibcon#*before return 0, iclass 11, count 0 2006.174.01:02:00.45#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.174.01:02:00.45#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.174.01:02:00.45#ibcon#about to clear, iclass 11 cls_cnt 0 2006.174.01:02:00.45#ibcon#cleared, iclass 11 cls_cnt 0 2006.174.01:02:00.45$vck44/valo=2,534.99 2006.174.01:02:00.45#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.174.01:02:00.45#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.174.01:02:00.45#ibcon#ireg 17 cls_cnt 0 2006.174.01:02:00.45#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.174.01:02:00.45#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.174.01:02:00.45#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.174.01:02:00.45#ibcon#enter wrdev, iclass 13, count 0 2006.174.01:02:00.45#ibcon#first serial, iclass 13, count 0 2006.174.01:02:00.45#ibcon#enter sib2, iclass 13, count 0 2006.174.01:02:00.45#ibcon#flushed, iclass 13, count 0 2006.174.01:02:00.45#ibcon#about to write, iclass 13, count 0 2006.174.01:02:00.45#ibcon#wrote, iclass 13, count 0 2006.174.01:02:00.45#ibcon#about to read 3, iclass 13, count 0 2006.174.01:02:00.47#ibcon#read 3, iclass 13, count 0 2006.174.01:02:00.47#ibcon#about to read 4, iclass 13, count 0 2006.174.01:02:00.47#ibcon#read 4, iclass 13, count 0 2006.174.01:02:00.47#ibcon#about to read 5, iclass 13, count 0 2006.174.01:02:00.47#ibcon#read 5, iclass 13, count 0 2006.174.01:02:00.47#ibcon#about to read 6, iclass 13, count 0 2006.174.01:02:00.47#ibcon#read 6, iclass 13, count 0 2006.174.01:02:00.47#ibcon#end of sib2, iclass 13, count 0 2006.174.01:02:00.47#ibcon#*mode == 0, iclass 13, count 0 2006.174.01:02:00.47#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.174.01:02:00.47#ibcon#[26=FRQ=02,534.99\r\n] 2006.174.01:02:00.47#ibcon#*before write, iclass 13, count 0 2006.174.01:02:00.47#ibcon#enter sib2, iclass 13, count 0 2006.174.01:02:00.47#ibcon#flushed, iclass 13, count 0 2006.174.01:02:00.47#ibcon#about to write, iclass 13, count 0 2006.174.01:02:00.47#ibcon#wrote, iclass 13, count 0 2006.174.01:02:00.47#ibcon#about to read 3, iclass 13, count 0 2006.174.01:02:00.51#ibcon#read 3, iclass 13, count 0 2006.174.01:02:00.51#ibcon#about to read 4, iclass 13, count 0 2006.174.01:02:00.51#ibcon#read 4, iclass 13, count 0 2006.174.01:02:00.51#ibcon#about to read 5, iclass 13, count 0 2006.174.01:02:00.51#ibcon#read 5, iclass 13, count 0 2006.174.01:02:00.51#ibcon#about to read 6, iclass 13, count 0 2006.174.01:02:00.51#ibcon#read 6, iclass 13, count 0 2006.174.01:02:00.51#ibcon#end of sib2, iclass 13, count 0 2006.174.01:02:00.51#ibcon#*after write, iclass 13, count 0 2006.174.01:02:00.51#ibcon#*before return 0, iclass 13, count 0 2006.174.01:02:00.51#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.174.01:02:00.51#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.174.01:02:00.51#ibcon#about to clear, iclass 13 cls_cnt 0 2006.174.01:02:00.51#ibcon#cleared, iclass 13 cls_cnt 0 2006.174.01:02:00.51$vck44/va=2,6 2006.174.01:02:00.51#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.174.01:02:00.51#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.174.01:02:00.51#ibcon#ireg 11 cls_cnt 2 2006.174.01:02:00.51#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.174.01:02:00.57#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.174.01:02:00.57#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.174.01:02:00.57#ibcon#enter wrdev, iclass 15, count 2 2006.174.01:02:00.57#ibcon#first serial, iclass 15, count 2 2006.174.01:02:00.57#ibcon#enter sib2, iclass 15, count 2 2006.174.01:02:00.57#ibcon#flushed, iclass 15, count 2 2006.174.01:02:00.57#ibcon#about to write, iclass 15, count 2 2006.174.01:02:00.57#ibcon#wrote, iclass 15, count 2 2006.174.01:02:00.57#ibcon#about to read 3, iclass 15, count 2 2006.174.01:02:00.59#ibcon#read 3, iclass 15, count 2 2006.174.01:02:00.59#ibcon#about to read 4, iclass 15, count 2 2006.174.01:02:00.59#ibcon#read 4, iclass 15, count 2 2006.174.01:02:00.59#ibcon#about to read 5, iclass 15, count 2 2006.174.01:02:00.59#ibcon#read 5, iclass 15, count 2 2006.174.01:02:00.59#ibcon#about to read 6, iclass 15, count 2 2006.174.01:02:00.59#ibcon#read 6, iclass 15, count 2 2006.174.01:02:00.59#ibcon#end of sib2, iclass 15, count 2 2006.174.01:02:00.59#ibcon#*mode == 0, iclass 15, count 2 2006.174.01:02:00.59#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.174.01:02:00.59#ibcon#[25=AT02-06\r\n] 2006.174.01:02:00.59#ibcon#*before write, iclass 15, count 2 2006.174.01:02:00.59#ibcon#enter sib2, iclass 15, count 2 2006.174.01:02:00.59#ibcon#flushed, iclass 15, count 2 2006.174.01:02:00.59#ibcon#about to write, iclass 15, count 2 2006.174.01:02:00.59#ibcon#wrote, iclass 15, count 2 2006.174.01:02:00.59#ibcon#about to read 3, iclass 15, count 2 2006.174.01:02:00.62#ibcon#read 3, iclass 15, count 2 2006.174.01:02:00.62#ibcon#about to read 4, iclass 15, count 2 2006.174.01:02:00.62#ibcon#read 4, iclass 15, count 2 2006.174.01:02:00.62#ibcon#about to read 5, iclass 15, count 2 2006.174.01:02:00.62#ibcon#read 5, iclass 15, count 2 2006.174.01:02:00.62#ibcon#about to read 6, iclass 15, count 2 2006.174.01:02:00.62#ibcon#read 6, iclass 15, count 2 2006.174.01:02:00.62#ibcon#end of sib2, iclass 15, count 2 2006.174.01:02:00.62#ibcon#*after write, iclass 15, count 2 2006.174.01:02:00.62#ibcon#*before return 0, iclass 15, count 2 2006.174.01:02:00.62#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.174.01:02:00.62#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.174.01:02:00.62#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.174.01:02:00.62#ibcon#ireg 7 cls_cnt 0 2006.174.01:02:00.62#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.174.01:02:00.74#abcon#<5=/08 0.8 2.3 25.20 821003.5\r\n> 2006.174.01:02:00.74#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.174.01:02:00.74#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.174.01:02:00.74#ibcon#enter wrdev, iclass 15, count 0 2006.174.01:02:00.74#ibcon#first serial, iclass 15, count 0 2006.174.01:02:00.74#ibcon#enter sib2, iclass 15, count 0 2006.174.01:02:00.74#ibcon#flushed, iclass 15, count 0 2006.174.01:02:00.74#ibcon#about to write, iclass 15, count 0 2006.174.01:02:00.74#ibcon#wrote, iclass 15, count 0 2006.174.01:02:00.74#ibcon#about to read 3, iclass 15, count 0 2006.174.01:02:00.76#ibcon#read 3, iclass 15, count 0 2006.174.01:02:00.76#ibcon#about to read 4, iclass 15, count 0 2006.174.01:02:00.76#ibcon#read 4, iclass 15, count 0 2006.174.01:02:00.76#ibcon#about to read 5, iclass 15, count 0 2006.174.01:02:00.76#ibcon#read 5, iclass 15, count 0 2006.174.01:02:00.76#ibcon#about to read 6, iclass 15, count 0 2006.174.01:02:00.76#ibcon#read 6, iclass 15, count 0 2006.174.01:02:00.76#ibcon#end of sib2, iclass 15, count 0 2006.174.01:02:00.76#ibcon#*mode == 0, iclass 15, count 0 2006.174.01:02:00.76#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.174.01:02:00.76#ibcon#[25=USB\r\n] 2006.174.01:02:00.76#ibcon#*before write, iclass 15, count 0 2006.174.01:02:00.76#ibcon#enter sib2, iclass 15, count 0 2006.174.01:02:00.76#ibcon#flushed, iclass 15, count 0 2006.174.01:02:00.76#ibcon#about to write, iclass 15, count 0 2006.174.01:02:00.76#ibcon#wrote, iclass 15, count 0 2006.174.01:02:00.76#ibcon#about to read 3, iclass 15, count 0 2006.174.01:02:00.76#abcon#{5=INTERFACE CLEAR} 2006.174.01:02:00.79#ibcon#read 3, iclass 15, count 0 2006.174.01:02:00.79#ibcon#about to read 4, iclass 15, count 0 2006.174.01:02:00.79#ibcon#read 4, iclass 15, count 0 2006.174.01:02:00.79#ibcon#about to read 5, iclass 15, count 0 2006.174.01:02:00.79#ibcon#read 5, iclass 15, count 0 2006.174.01:02:00.79#ibcon#about to read 6, iclass 15, count 0 2006.174.01:02:00.79#ibcon#read 6, iclass 15, count 0 2006.174.01:02:00.79#ibcon#end of sib2, iclass 15, count 0 2006.174.01:02:00.79#ibcon#*after write, iclass 15, count 0 2006.174.01:02:00.79#ibcon#*before return 0, iclass 15, count 0 2006.174.01:02:00.79#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.174.01:02:00.79#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.174.01:02:00.79#ibcon#about to clear, iclass 15 cls_cnt 0 2006.174.01:02:00.79#ibcon#cleared, iclass 15 cls_cnt 0 2006.174.01:02:00.79$vck44/valo=3,564.99 2006.174.01:02:00.79#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.174.01:02:00.79#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.174.01:02:00.79#ibcon#ireg 17 cls_cnt 0 2006.174.01:02:00.79#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.174.01:02:00.79#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.174.01:02:00.79#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.174.01:02:00.79#ibcon#enter wrdev, iclass 20, count 0 2006.174.01:02:00.79#ibcon#first serial, iclass 20, count 0 2006.174.01:02:00.79#ibcon#enter sib2, iclass 20, count 0 2006.174.01:02:00.79#ibcon#flushed, iclass 20, count 0 2006.174.01:02:00.79#ibcon#about to write, iclass 20, count 0 2006.174.01:02:00.79#ibcon#wrote, iclass 20, count 0 2006.174.01:02:00.79#ibcon#about to read 3, iclass 20, count 0 2006.174.01:02:00.81#ibcon#read 3, iclass 20, count 0 2006.174.01:02:00.81#ibcon#about to read 4, iclass 20, count 0 2006.174.01:02:00.81#ibcon#read 4, iclass 20, count 0 2006.174.01:02:00.81#ibcon#about to read 5, iclass 20, count 0 2006.174.01:02:00.81#ibcon#read 5, iclass 20, count 0 2006.174.01:02:00.81#ibcon#about to read 6, iclass 20, count 0 2006.174.01:02:00.81#ibcon#read 6, iclass 20, count 0 2006.174.01:02:00.81#ibcon#end of sib2, iclass 20, count 0 2006.174.01:02:00.81#ibcon#*mode == 0, iclass 20, count 0 2006.174.01:02:00.81#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.174.01:02:00.81#ibcon#[26=FRQ=03,564.99\r\n] 2006.174.01:02:00.81#ibcon#*before write, iclass 20, count 0 2006.174.01:02:00.81#ibcon#enter sib2, iclass 20, count 0 2006.174.01:02:00.81#ibcon#flushed, iclass 20, count 0 2006.174.01:02:00.81#ibcon#about to write, iclass 20, count 0 2006.174.01:02:00.81#ibcon#wrote, iclass 20, count 0 2006.174.01:02:00.81#ibcon#about to read 3, iclass 20, count 0 2006.174.01:02:00.82#abcon#[5=S1D000X0/0*\r\n] 2006.174.01:02:00.85#ibcon#read 3, iclass 20, count 0 2006.174.01:02:00.85#ibcon#about to read 4, iclass 20, count 0 2006.174.01:02:00.85#ibcon#read 4, iclass 20, count 0 2006.174.01:02:00.85#ibcon#about to read 5, iclass 20, count 0 2006.174.01:02:00.85#ibcon#read 5, iclass 20, count 0 2006.174.01:02:00.85#ibcon#about to read 6, iclass 20, count 0 2006.174.01:02:00.85#ibcon#read 6, iclass 20, count 0 2006.174.01:02:00.85#ibcon#end of sib2, iclass 20, count 0 2006.174.01:02:00.85#ibcon#*after write, iclass 20, count 0 2006.174.01:02:00.85#ibcon#*before return 0, iclass 20, count 0 2006.174.01:02:00.85#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.174.01:02:00.85#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.174.01:02:00.85#ibcon#about to clear, iclass 20 cls_cnt 0 2006.174.01:02:00.85#ibcon#cleared, iclass 20 cls_cnt 0 2006.174.01:02:00.85$vck44/va=3,5 2006.174.01:02:00.85#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.174.01:02:00.85#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.174.01:02:00.85#ibcon#ireg 11 cls_cnt 2 2006.174.01:02:00.85#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.174.01:02:00.91#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.174.01:02:00.91#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.174.01:02:00.91#ibcon#enter wrdev, iclass 23, count 2 2006.174.01:02:00.91#ibcon#first serial, iclass 23, count 2 2006.174.01:02:00.91#ibcon#enter sib2, iclass 23, count 2 2006.174.01:02:00.91#ibcon#flushed, iclass 23, count 2 2006.174.01:02:00.91#ibcon#about to write, iclass 23, count 2 2006.174.01:02:00.91#ibcon#wrote, iclass 23, count 2 2006.174.01:02:00.91#ibcon#about to read 3, iclass 23, count 2 2006.174.01:02:00.93#ibcon#read 3, iclass 23, count 2 2006.174.01:02:00.93#ibcon#about to read 4, iclass 23, count 2 2006.174.01:02:00.93#ibcon#read 4, iclass 23, count 2 2006.174.01:02:00.93#ibcon#about to read 5, iclass 23, count 2 2006.174.01:02:00.93#ibcon#read 5, iclass 23, count 2 2006.174.01:02:00.93#ibcon#about to read 6, iclass 23, count 2 2006.174.01:02:00.93#ibcon#read 6, iclass 23, count 2 2006.174.01:02:00.93#ibcon#end of sib2, iclass 23, count 2 2006.174.01:02:00.93#ibcon#*mode == 0, iclass 23, count 2 2006.174.01:02:00.93#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.174.01:02:00.93#ibcon#[25=AT03-05\r\n] 2006.174.01:02:00.93#ibcon#*before write, iclass 23, count 2 2006.174.01:02:00.93#ibcon#enter sib2, iclass 23, count 2 2006.174.01:02:00.93#ibcon#flushed, iclass 23, count 2 2006.174.01:02:00.93#ibcon#about to write, iclass 23, count 2 2006.174.01:02:00.93#ibcon#wrote, iclass 23, count 2 2006.174.01:02:00.93#ibcon#about to read 3, iclass 23, count 2 2006.174.01:02:00.96#ibcon#read 3, iclass 23, count 2 2006.174.01:02:00.96#ibcon#about to read 4, iclass 23, count 2 2006.174.01:02:00.96#ibcon#read 4, iclass 23, count 2 2006.174.01:02:00.96#ibcon#about to read 5, iclass 23, count 2 2006.174.01:02:00.96#ibcon#read 5, iclass 23, count 2 2006.174.01:02:00.96#ibcon#about to read 6, iclass 23, count 2 2006.174.01:02:00.96#ibcon#read 6, iclass 23, count 2 2006.174.01:02:00.96#ibcon#end of sib2, iclass 23, count 2 2006.174.01:02:00.96#ibcon#*after write, iclass 23, count 2 2006.174.01:02:00.96#ibcon#*before return 0, iclass 23, count 2 2006.174.01:02:00.96#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.174.01:02:00.96#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.174.01:02:00.96#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.174.01:02:00.96#ibcon#ireg 7 cls_cnt 0 2006.174.01:02:00.96#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.174.01:02:01.08#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.174.01:02:01.08#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.174.01:02:01.08#ibcon#enter wrdev, iclass 23, count 0 2006.174.01:02:01.08#ibcon#first serial, iclass 23, count 0 2006.174.01:02:01.08#ibcon#enter sib2, iclass 23, count 0 2006.174.01:02:01.08#ibcon#flushed, iclass 23, count 0 2006.174.01:02:01.08#ibcon#about to write, iclass 23, count 0 2006.174.01:02:01.08#ibcon#wrote, iclass 23, count 0 2006.174.01:02:01.08#ibcon#about to read 3, iclass 23, count 0 2006.174.01:02:01.10#ibcon#read 3, iclass 23, count 0 2006.174.01:02:01.10#ibcon#about to read 4, iclass 23, count 0 2006.174.01:02:01.10#ibcon#read 4, iclass 23, count 0 2006.174.01:02:01.10#ibcon#about to read 5, iclass 23, count 0 2006.174.01:02:01.10#ibcon#read 5, iclass 23, count 0 2006.174.01:02:01.10#ibcon#about to read 6, iclass 23, count 0 2006.174.01:02:01.10#ibcon#read 6, iclass 23, count 0 2006.174.01:02:01.10#ibcon#end of sib2, iclass 23, count 0 2006.174.01:02:01.10#ibcon#*mode == 0, iclass 23, count 0 2006.174.01:02:01.10#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.174.01:02:01.10#ibcon#[25=USB\r\n] 2006.174.01:02:01.10#ibcon#*before write, iclass 23, count 0 2006.174.01:02:01.10#ibcon#enter sib2, iclass 23, count 0 2006.174.01:02:01.10#ibcon#flushed, iclass 23, count 0 2006.174.01:02:01.10#ibcon#about to write, iclass 23, count 0 2006.174.01:02:01.10#ibcon#wrote, iclass 23, count 0 2006.174.01:02:01.10#ibcon#about to read 3, iclass 23, count 0 2006.174.01:02:01.13#ibcon#read 3, iclass 23, count 0 2006.174.01:02:01.13#ibcon#about to read 4, iclass 23, count 0 2006.174.01:02:01.13#ibcon#read 4, iclass 23, count 0 2006.174.01:02:01.13#ibcon#about to read 5, iclass 23, count 0 2006.174.01:02:01.13#ibcon#read 5, iclass 23, count 0 2006.174.01:02:01.13#ibcon#about to read 6, iclass 23, count 0 2006.174.01:02:01.13#ibcon#read 6, iclass 23, count 0 2006.174.01:02:01.13#ibcon#end of sib2, iclass 23, count 0 2006.174.01:02:01.13#ibcon#*after write, iclass 23, count 0 2006.174.01:02:01.13#ibcon#*before return 0, iclass 23, count 0 2006.174.01:02:01.13#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.174.01:02:01.13#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.174.01:02:01.13#ibcon#about to clear, iclass 23 cls_cnt 0 2006.174.01:02:01.13#ibcon#cleared, iclass 23 cls_cnt 0 2006.174.01:02:01.13$vck44/valo=4,624.99 2006.174.01:02:01.13#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.174.01:02:01.13#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.174.01:02:01.13#ibcon#ireg 17 cls_cnt 0 2006.174.01:02:01.13#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.174.01:02:01.13#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.174.01:02:01.13#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.174.01:02:01.13#ibcon#enter wrdev, iclass 25, count 0 2006.174.01:02:01.13#ibcon#first serial, iclass 25, count 0 2006.174.01:02:01.13#ibcon#enter sib2, iclass 25, count 0 2006.174.01:02:01.13#ibcon#flushed, iclass 25, count 0 2006.174.01:02:01.13#ibcon#about to write, iclass 25, count 0 2006.174.01:02:01.13#ibcon#wrote, iclass 25, count 0 2006.174.01:02:01.13#ibcon#about to read 3, iclass 25, count 0 2006.174.01:02:01.15#ibcon#read 3, iclass 25, count 0 2006.174.01:02:01.15#ibcon#about to read 4, iclass 25, count 0 2006.174.01:02:01.15#ibcon#read 4, iclass 25, count 0 2006.174.01:02:01.15#ibcon#about to read 5, iclass 25, count 0 2006.174.01:02:01.15#ibcon#read 5, iclass 25, count 0 2006.174.01:02:01.15#ibcon#about to read 6, iclass 25, count 0 2006.174.01:02:01.15#ibcon#read 6, iclass 25, count 0 2006.174.01:02:01.15#ibcon#end of sib2, iclass 25, count 0 2006.174.01:02:01.15#ibcon#*mode == 0, iclass 25, count 0 2006.174.01:02:01.15#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.174.01:02:01.15#ibcon#[26=FRQ=04,624.99\r\n] 2006.174.01:02:01.15#ibcon#*before write, iclass 25, count 0 2006.174.01:02:01.15#ibcon#enter sib2, iclass 25, count 0 2006.174.01:02:01.15#ibcon#flushed, iclass 25, count 0 2006.174.01:02:01.15#ibcon#about to write, iclass 25, count 0 2006.174.01:02:01.15#ibcon#wrote, iclass 25, count 0 2006.174.01:02:01.15#ibcon#about to read 3, iclass 25, count 0 2006.174.01:02:01.19#ibcon#read 3, iclass 25, count 0 2006.174.01:02:01.19#ibcon#about to read 4, iclass 25, count 0 2006.174.01:02:01.19#ibcon#read 4, iclass 25, count 0 2006.174.01:02:01.19#ibcon#about to read 5, iclass 25, count 0 2006.174.01:02:01.19#ibcon#read 5, iclass 25, count 0 2006.174.01:02:01.19#ibcon#about to read 6, iclass 25, count 0 2006.174.01:02:01.19#ibcon#read 6, iclass 25, count 0 2006.174.01:02:01.19#ibcon#end of sib2, iclass 25, count 0 2006.174.01:02:01.19#ibcon#*after write, iclass 25, count 0 2006.174.01:02:01.19#ibcon#*before return 0, iclass 25, count 0 2006.174.01:02:01.19#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.174.01:02:01.19#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.174.01:02:01.19#ibcon#about to clear, iclass 25 cls_cnt 0 2006.174.01:02:01.19#ibcon#cleared, iclass 25 cls_cnt 0 2006.174.01:02:01.19$vck44/va=4,6 2006.174.01:02:01.19#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.174.01:02:01.19#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.174.01:02:01.19#ibcon#ireg 11 cls_cnt 2 2006.174.01:02:01.19#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.174.01:02:01.25#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.174.01:02:01.25#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.174.01:02:01.25#ibcon#enter wrdev, iclass 27, count 2 2006.174.01:02:01.25#ibcon#first serial, iclass 27, count 2 2006.174.01:02:01.25#ibcon#enter sib2, iclass 27, count 2 2006.174.01:02:01.25#ibcon#flushed, iclass 27, count 2 2006.174.01:02:01.25#ibcon#about to write, iclass 27, count 2 2006.174.01:02:01.25#ibcon#wrote, iclass 27, count 2 2006.174.01:02:01.25#ibcon#about to read 3, iclass 27, count 2 2006.174.01:02:01.27#ibcon#read 3, iclass 27, count 2 2006.174.01:02:01.27#ibcon#about to read 4, iclass 27, count 2 2006.174.01:02:01.27#ibcon#read 4, iclass 27, count 2 2006.174.01:02:01.27#ibcon#about to read 5, iclass 27, count 2 2006.174.01:02:01.27#ibcon#read 5, iclass 27, count 2 2006.174.01:02:01.27#ibcon#about to read 6, iclass 27, count 2 2006.174.01:02:01.27#ibcon#read 6, iclass 27, count 2 2006.174.01:02:01.27#ibcon#end of sib2, iclass 27, count 2 2006.174.01:02:01.27#ibcon#*mode == 0, iclass 27, count 2 2006.174.01:02:01.27#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.174.01:02:01.27#ibcon#[25=AT04-06\r\n] 2006.174.01:02:01.27#ibcon#*before write, iclass 27, count 2 2006.174.01:02:01.27#ibcon#enter sib2, iclass 27, count 2 2006.174.01:02:01.27#ibcon#flushed, iclass 27, count 2 2006.174.01:02:01.27#ibcon#about to write, iclass 27, count 2 2006.174.01:02:01.27#ibcon#wrote, iclass 27, count 2 2006.174.01:02:01.27#ibcon#about to read 3, iclass 27, count 2 2006.174.01:02:01.30#ibcon#read 3, iclass 27, count 2 2006.174.01:02:01.30#ibcon#about to read 4, iclass 27, count 2 2006.174.01:02:01.30#ibcon#read 4, iclass 27, count 2 2006.174.01:02:01.30#ibcon#about to read 5, iclass 27, count 2 2006.174.01:02:01.30#ibcon#read 5, iclass 27, count 2 2006.174.01:02:01.30#ibcon#about to read 6, iclass 27, count 2 2006.174.01:02:01.30#ibcon#read 6, iclass 27, count 2 2006.174.01:02:01.30#ibcon#end of sib2, iclass 27, count 2 2006.174.01:02:01.30#ibcon#*after write, iclass 27, count 2 2006.174.01:02:01.30#ibcon#*before return 0, iclass 27, count 2 2006.174.01:02:01.30#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.174.01:02:01.30#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.174.01:02:01.30#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.174.01:02:01.30#ibcon#ireg 7 cls_cnt 0 2006.174.01:02:01.30#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.174.01:02:01.42#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.174.01:02:01.42#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.174.01:02:01.42#ibcon#enter wrdev, iclass 27, count 0 2006.174.01:02:01.42#ibcon#first serial, iclass 27, count 0 2006.174.01:02:01.42#ibcon#enter sib2, iclass 27, count 0 2006.174.01:02:01.42#ibcon#flushed, iclass 27, count 0 2006.174.01:02:01.42#ibcon#about to write, iclass 27, count 0 2006.174.01:02:01.42#ibcon#wrote, iclass 27, count 0 2006.174.01:02:01.42#ibcon#about to read 3, iclass 27, count 0 2006.174.01:02:01.44#ibcon#read 3, iclass 27, count 0 2006.174.01:02:01.44#ibcon#about to read 4, iclass 27, count 0 2006.174.01:02:01.44#ibcon#read 4, iclass 27, count 0 2006.174.01:02:01.44#ibcon#about to read 5, iclass 27, count 0 2006.174.01:02:01.44#ibcon#read 5, iclass 27, count 0 2006.174.01:02:01.44#ibcon#about to read 6, iclass 27, count 0 2006.174.01:02:01.44#ibcon#read 6, iclass 27, count 0 2006.174.01:02:01.44#ibcon#end of sib2, iclass 27, count 0 2006.174.01:02:01.44#ibcon#*mode == 0, iclass 27, count 0 2006.174.01:02:01.44#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.174.01:02:01.44#ibcon#[25=USB\r\n] 2006.174.01:02:01.44#ibcon#*before write, iclass 27, count 0 2006.174.01:02:01.44#ibcon#enter sib2, iclass 27, count 0 2006.174.01:02:01.44#ibcon#flushed, iclass 27, count 0 2006.174.01:02:01.44#ibcon#about to write, iclass 27, count 0 2006.174.01:02:01.44#ibcon#wrote, iclass 27, count 0 2006.174.01:02:01.44#ibcon#about to read 3, iclass 27, count 0 2006.174.01:02:01.47#ibcon#read 3, iclass 27, count 0 2006.174.01:02:01.47#ibcon#about to read 4, iclass 27, count 0 2006.174.01:02:01.47#ibcon#read 4, iclass 27, count 0 2006.174.01:02:01.47#ibcon#about to read 5, iclass 27, count 0 2006.174.01:02:01.47#ibcon#read 5, iclass 27, count 0 2006.174.01:02:01.47#ibcon#about to read 6, iclass 27, count 0 2006.174.01:02:01.47#ibcon#read 6, iclass 27, count 0 2006.174.01:02:01.47#ibcon#end of sib2, iclass 27, count 0 2006.174.01:02:01.47#ibcon#*after write, iclass 27, count 0 2006.174.01:02:01.47#ibcon#*before return 0, iclass 27, count 0 2006.174.01:02:01.47#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.174.01:02:01.47#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.174.01:02:01.47#ibcon#about to clear, iclass 27 cls_cnt 0 2006.174.01:02:01.47#ibcon#cleared, iclass 27 cls_cnt 0 2006.174.01:02:01.47$vck44/valo=5,734.99 2006.174.01:02:01.47#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.174.01:02:01.47#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.174.01:02:01.47#ibcon#ireg 17 cls_cnt 0 2006.174.01:02:01.47#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.174.01:02:01.47#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.174.01:02:01.47#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.174.01:02:01.47#ibcon#enter wrdev, iclass 29, count 0 2006.174.01:02:01.47#ibcon#first serial, iclass 29, count 0 2006.174.01:02:01.47#ibcon#enter sib2, iclass 29, count 0 2006.174.01:02:01.47#ibcon#flushed, iclass 29, count 0 2006.174.01:02:01.47#ibcon#about to write, iclass 29, count 0 2006.174.01:02:01.47#ibcon#wrote, iclass 29, count 0 2006.174.01:02:01.47#ibcon#about to read 3, iclass 29, count 0 2006.174.01:02:01.49#ibcon#read 3, iclass 29, count 0 2006.174.01:02:01.49#ibcon#about to read 4, iclass 29, count 0 2006.174.01:02:01.49#ibcon#read 4, iclass 29, count 0 2006.174.01:02:01.49#ibcon#about to read 5, iclass 29, count 0 2006.174.01:02:01.49#ibcon#read 5, iclass 29, count 0 2006.174.01:02:01.49#ibcon#about to read 6, iclass 29, count 0 2006.174.01:02:01.49#ibcon#read 6, iclass 29, count 0 2006.174.01:02:01.49#ibcon#end of sib2, iclass 29, count 0 2006.174.01:02:01.49#ibcon#*mode == 0, iclass 29, count 0 2006.174.01:02:01.49#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.174.01:02:01.49#ibcon#[26=FRQ=05,734.99\r\n] 2006.174.01:02:01.49#ibcon#*before write, iclass 29, count 0 2006.174.01:02:01.49#ibcon#enter sib2, iclass 29, count 0 2006.174.01:02:01.49#ibcon#flushed, iclass 29, count 0 2006.174.01:02:01.49#ibcon#about to write, iclass 29, count 0 2006.174.01:02:01.49#ibcon#wrote, iclass 29, count 0 2006.174.01:02:01.49#ibcon#about to read 3, iclass 29, count 0 2006.174.01:02:01.53#ibcon#read 3, iclass 29, count 0 2006.174.01:02:01.53#ibcon#about to read 4, iclass 29, count 0 2006.174.01:02:01.53#ibcon#read 4, iclass 29, count 0 2006.174.01:02:01.53#ibcon#about to read 5, iclass 29, count 0 2006.174.01:02:01.53#ibcon#read 5, iclass 29, count 0 2006.174.01:02:01.53#ibcon#about to read 6, iclass 29, count 0 2006.174.01:02:01.53#ibcon#read 6, iclass 29, count 0 2006.174.01:02:01.53#ibcon#end of sib2, iclass 29, count 0 2006.174.01:02:01.53#ibcon#*after write, iclass 29, count 0 2006.174.01:02:01.53#ibcon#*before return 0, iclass 29, count 0 2006.174.01:02:01.53#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.174.01:02:01.53#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.174.01:02:01.53#ibcon#about to clear, iclass 29 cls_cnt 0 2006.174.01:02:01.53#ibcon#cleared, iclass 29 cls_cnt 0 2006.174.01:02:01.53$vck44/va=5,4 2006.174.01:02:01.53#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.174.01:02:01.53#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.174.01:02:01.53#ibcon#ireg 11 cls_cnt 2 2006.174.01:02:01.53#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.174.01:02:01.59#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.174.01:02:01.59#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.174.01:02:01.59#ibcon#enter wrdev, iclass 31, count 2 2006.174.01:02:01.59#ibcon#first serial, iclass 31, count 2 2006.174.01:02:01.59#ibcon#enter sib2, iclass 31, count 2 2006.174.01:02:01.59#ibcon#flushed, iclass 31, count 2 2006.174.01:02:01.59#ibcon#about to write, iclass 31, count 2 2006.174.01:02:01.59#ibcon#wrote, iclass 31, count 2 2006.174.01:02:01.59#ibcon#about to read 3, iclass 31, count 2 2006.174.01:02:01.61#ibcon#read 3, iclass 31, count 2 2006.174.01:02:01.61#ibcon#about to read 4, iclass 31, count 2 2006.174.01:02:01.61#ibcon#read 4, iclass 31, count 2 2006.174.01:02:01.61#ibcon#about to read 5, iclass 31, count 2 2006.174.01:02:01.61#ibcon#read 5, iclass 31, count 2 2006.174.01:02:01.61#ibcon#about to read 6, iclass 31, count 2 2006.174.01:02:01.61#ibcon#read 6, iclass 31, count 2 2006.174.01:02:01.61#ibcon#end of sib2, iclass 31, count 2 2006.174.01:02:01.61#ibcon#*mode == 0, iclass 31, count 2 2006.174.01:02:01.61#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.174.01:02:01.61#ibcon#[25=AT05-04\r\n] 2006.174.01:02:01.61#ibcon#*before write, iclass 31, count 2 2006.174.01:02:01.61#ibcon#enter sib2, iclass 31, count 2 2006.174.01:02:01.61#ibcon#flushed, iclass 31, count 2 2006.174.01:02:01.61#ibcon#about to write, iclass 31, count 2 2006.174.01:02:01.61#ibcon#wrote, iclass 31, count 2 2006.174.01:02:01.61#ibcon#about to read 3, iclass 31, count 2 2006.174.01:02:01.64#ibcon#read 3, iclass 31, count 2 2006.174.01:02:01.64#ibcon#about to read 4, iclass 31, count 2 2006.174.01:02:01.64#ibcon#read 4, iclass 31, count 2 2006.174.01:02:01.64#ibcon#about to read 5, iclass 31, count 2 2006.174.01:02:01.64#ibcon#read 5, iclass 31, count 2 2006.174.01:02:01.64#ibcon#about to read 6, iclass 31, count 2 2006.174.01:02:01.64#ibcon#read 6, iclass 31, count 2 2006.174.01:02:01.64#ibcon#end of sib2, iclass 31, count 2 2006.174.01:02:01.64#ibcon#*after write, iclass 31, count 2 2006.174.01:02:01.64#ibcon#*before return 0, iclass 31, count 2 2006.174.01:02:01.64#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.174.01:02:01.64#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.174.01:02:01.64#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.174.01:02:01.64#ibcon#ireg 7 cls_cnt 0 2006.174.01:02:01.64#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.174.01:02:01.76#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.174.01:02:01.76#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.174.01:02:01.76#ibcon#enter wrdev, iclass 31, count 0 2006.174.01:02:01.76#ibcon#first serial, iclass 31, count 0 2006.174.01:02:01.76#ibcon#enter sib2, iclass 31, count 0 2006.174.01:02:01.76#ibcon#flushed, iclass 31, count 0 2006.174.01:02:01.76#ibcon#about to write, iclass 31, count 0 2006.174.01:02:01.76#ibcon#wrote, iclass 31, count 0 2006.174.01:02:01.76#ibcon#about to read 3, iclass 31, count 0 2006.174.01:02:01.78#ibcon#read 3, iclass 31, count 0 2006.174.01:02:01.78#ibcon#about to read 4, iclass 31, count 0 2006.174.01:02:01.78#ibcon#read 4, iclass 31, count 0 2006.174.01:02:01.78#ibcon#about to read 5, iclass 31, count 0 2006.174.01:02:01.78#ibcon#read 5, iclass 31, count 0 2006.174.01:02:01.78#ibcon#about to read 6, iclass 31, count 0 2006.174.01:02:01.78#ibcon#read 6, iclass 31, count 0 2006.174.01:02:01.78#ibcon#end of sib2, iclass 31, count 0 2006.174.01:02:01.78#ibcon#*mode == 0, iclass 31, count 0 2006.174.01:02:01.78#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.174.01:02:01.78#ibcon#[25=USB\r\n] 2006.174.01:02:01.78#ibcon#*before write, iclass 31, count 0 2006.174.01:02:01.78#ibcon#enter sib2, iclass 31, count 0 2006.174.01:02:01.78#ibcon#flushed, iclass 31, count 0 2006.174.01:02:01.78#ibcon#about to write, iclass 31, count 0 2006.174.01:02:01.78#ibcon#wrote, iclass 31, count 0 2006.174.01:02:01.78#ibcon#about to read 3, iclass 31, count 0 2006.174.01:02:01.81#ibcon#read 3, iclass 31, count 0 2006.174.01:02:01.81#ibcon#about to read 4, iclass 31, count 0 2006.174.01:02:01.81#ibcon#read 4, iclass 31, count 0 2006.174.01:02:01.81#ibcon#about to read 5, iclass 31, count 0 2006.174.01:02:01.81#ibcon#read 5, iclass 31, count 0 2006.174.01:02:01.81#ibcon#about to read 6, iclass 31, count 0 2006.174.01:02:01.81#ibcon#read 6, iclass 31, count 0 2006.174.01:02:01.81#ibcon#end of sib2, iclass 31, count 0 2006.174.01:02:01.81#ibcon#*after write, iclass 31, count 0 2006.174.01:02:01.81#ibcon#*before return 0, iclass 31, count 0 2006.174.01:02:01.81#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.174.01:02:01.81#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.174.01:02:01.81#ibcon#about to clear, iclass 31 cls_cnt 0 2006.174.01:02:01.81#ibcon#cleared, iclass 31 cls_cnt 0 2006.174.01:02:01.81$vck44/valo=6,814.99 2006.174.01:02:01.81#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.174.01:02:01.81#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.174.01:02:01.81#ibcon#ireg 17 cls_cnt 0 2006.174.01:02:01.81#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.174.01:02:01.81#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.174.01:02:01.81#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.174.01:02:01.81#ibcon#enter wrdev, iclass 33, count 0 2006.174.01:02:01.81#ibcon#first serial, iclass 33, count 0 2006.174.01:02:01.81#ibcon#enter sib2, iclass 33, count 0 2006.174.01:02:01.81#ibcon#flushed, iclass 33, count 0 2006.174.01:02:01.81#ibcon#about to write, iclass 33, count 0 2006.174.01:02:01.81#ibcon#wrote, iclass 33, count 0 2006.174.01:02:01.81#ibcon#about to read 3, iclass 33, count 0 2006.174.01:02:01.83#ibcon#read 3, iclass 33, count 0 2006.174.01:02:01.83#ibcon#about to read 4, iclass 33, count 0 2006.174.01:02:01.83#ibcon#read 4, iclass 33, count 0 2006.174.01:02:01.83#ibcon#about to read 5, iclass 33, count 0 2006.174.01:02:01.83#ibcon#read 5, iclass 33, count 0 2006.174.01:02:01.83#ibcon#about to read 6, iclass 33, count 0 2006.174.01:02:01.83#ibcon#read 6, iclass 33, count 0 2006.174.01:02:01.83#ibcon#end of sib2, iclass 33, count 0 2006.174.01:02:01.83#ibcon#*mode == 0, iclass 33, count 0 2006.174.01:02:01.83#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.174.01:02:01.83#ibcon#[26=FRQ=06,814.99\r\n] 2006.174.01:02:01.83#ibcon#*before write, iclass 33, count 0 2006.174.01:02:01.83#ibcon#enter sib2, iclass 33, count 0 2006.174.01:02:01.83#ibcon#flushed, iclass 33, count 0 2006.174.01:02:01.83#ibcon#about to write, iclass 33, count 0 2006.174.01:02:01.83#ibcon#wrote, iclass 33, count 0 2006.174.01:02:01.83#ibcon#about to read 3, iclass 33, count 0 2006.174.01:02:01.87#ibcon#read 3, iclass 33, count 0 2006.174.01:02:01.87#ibcon#about to read 4, iclass 33, count 0 2006.174.01:02:01.87#ibcon#read 4, iclass 33, count 0 2006.174.01:02:01.87#ibcon#about to read 5, iclass 33, count 0 2006.174.01:02:01.87#ibcon#read 5, iclass 33, count 0 2006.174.01:02:01.87#ibcon#about to read 6, iclass 33, count 0 2006.174.01:02:01.87#ibcon#read 6, iclass 33, count 0 2006.174.01:02:01.87#ibcon#end of sib2, iclass 33, count 0 2006.174.01:02:01.87#ibcon#*after write, iclass 33, count 0 2006.174.01:02:01.87#ibcon#*before return 0, iclass 33, count 0 2006.174.01:02:01.87#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.174.01:02:01.87#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.174.01:02:01.87#ibcon#about to clear, iclass 33 cls_cnt 0 2006.174.01:02:01.87#ibcon#cleared, iclass 33 cls_cnt 0 2006.174.01:02:01.87$vck44/va=6,3 2006.174.01:02:01.87#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.174.01:02:01.87#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.174.01:02:01.87#ibcon#ireg 11 cls_cnt 2 2006.174.01:02:01.87#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.174.01:02:01.93#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.174.01:02:01.93#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.174.01:02:01.93#ibcon#enter wrdev, iclass 35, count 2 2006.174.01:02:01.93#ibcon#first serial, iclass 35, count 2 2006.174.01:02:01.93#ibcon#enter sib2, iclass 35, count 2 2006.174.01:02:01.93#ibcon#flushed, iclass 35, count 2 2006.174.01:02:01.93#ibcon#about to write, iclass 35, count 2 2006.174.01:02:01.93#ibcon#wrote, iclass 35, count 2 2006.174.01:02:01.93#ibcon#about to read 3, iclass 35, count 2 2006.174.01:02:01.95#ibcon#read 3, iclass 35, count 2 2006.174.01:02:01.95#ibcon#about to read 4, iclass 35, count 2 2006.174.01:02:01.95#ibcon#read 4, iclass 35, count 2 2006.174.01:02:01.95#ibcon#about to read 5, iclass 35, count 2 2006.174.01:02:01.95#ibcon#read 5, iclass 35, count 2 2006.174.01:02:01.95#ibcon#about to read 6, iclass 35, count 2 2006.174.01:02:01.95#ibcon#read 6, iclass 35, count 2 2006.174.01:02:01.95#ibcon#end of sib2, iclass 35, count 2 2006.174.01:02:01.95#ibcon#*mode == 0, iclass 35, count 2 2006.174.01:02:01.95#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.174.01:02:01.95#ibcon#[25=AT06-03\r\n] 2006.174.01:02:01.95#ibcon#*before write, iclass 35, count 2 2006.174.01:02:01.95#ibcon#enter sib2, iclass 35, count 2 2006.174.01:02:01.95#ibcon#flushed, iclass 35, count 2 2006.174.01:02:01.95#ibcon#about to write, iclass 35, count 2 2006.174.01:02:01.95#ibcon#wrote, iclass 35, count 2 2006.174.01:02:01.95#ibcon#about to read 3, iclass 35, count 2 2006.174.01:02:01.98#ibcon#read 3, iclass 35, count 2 2006.174.01:02:01.98#ibcon#about to read 4, iclass 35, count 2 2006.174.01:02:01.98#ibcon#read 4, iclass 35, count 2 2006.174.01:02:01.98#ibcon#about to read 5, iclass 35, count 2 2006.174.01:02:01.98#ibcon#read 5, iclass 35, count 2 2006.174.01:02:01.98#ibcon#about to read 6, iclass 35, count 2 2006.174.01:02:01.98#ibcon#read 6, iclass 35, count 2 2006.174.01:02:01.98#ibcon#end of sib2, iclass 35, count 2 2006.174.01:02:01.98#ibcon#*after write, iclass 35, count 2 2006.174.01:02:01.98#ibcon#*before return 0, iclass 35, count 2 2006.174.01:02:01.98#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.174.01:02:01.98#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.174.01:02:01.98#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.174.01:02:01.98#ibcon#ireg 7 cls_cnt 0 2006.174.01:02:01.98#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.174.01:02:02.10#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.174.01:02:02.10#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.174.01:02:02.10#ibcon#enter wrdev, iclass 35, count 0 2006.174.01:02:02.10#ibcon#first serial, iclass 35, count 0 2006.174.01:02:02.10#ibcon#enter sib2, iclass 35, count 0 2006.174.01:02:02.10#ibcon#flushed, iclass 35, count 0 2006.174.01:02:02.10#ibcon#about to write, iclass 35, count 0 2006.174.01:02:02.10#ibcon#wrote, iclass 35, count 0 2006.174.01:02:02.10#ibcon#about to read 3, iclass 35, count 0 2006.174.01:02:02.12#ibcon#read 3, iclass 35, count 0 2006.174.01:02:02.12#ibcon#about to read 4, iclass 35, count 0 2006.174.01:02:02.12#ibcon#read 4, iclass 35, count 0 2006.174.01:02:02.12#ibcon#about to read 5, iclass 35, count 0 2006.174.01:02:02.12#ibcon#read 5, iclass 35, count 0 2006.174.01:02:02.12#ibcon#about to read 6, iclass 35, count 0 2006.174.01:02:02.12#ibcon#read 6, iclass 35, count 0 2006.174.01:02:02.12#ibcon#end of sib2, iclass 35, count 0 2006.174.01:02:02.12#ibcon#*mode == 0, iclass 35, count 0 2006.174.01:02:02.12#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.174.01:02:02.12#ibcon#[25=USB\r\n] 2006.174.01:02:02.12#ibcon#*before write, iclass 35, count 0 2006.174.01:02:02.12#ibcon#enter sib2, iclass 35, count 0 2006.174.01:02:02.12#ibcon#flushed, iclass 35, count 0 2006.174.01:02:02.12#ibcon#about to write, iclass 35, count 0 2006.174.01:02:02.12#ibcon#wrote, iclass 35, count 0 2006.174.01:02:02.12#ibcon#about to read 3, iclass 35, count 0 2006.174.01:02:02.15#ibcon#read 3, iclass 35, count 0 2006.174.01:02:02.15#ibcon#about to read 4, iclass 35, count 0 2006.174.01:02:02.15#ibcon#read 4, iclass 35, count 0 2006.174.01:02:02.15#ibcon#about to read 5, iclass 35, count 0 2006.174.01:02:02.15#ibcon#read 5, iclass 35, count 0 2006.174.01:02:02.15#ibcon#about to read 6, iclass 35, count 0 2006.174.01:02:02.15#ibcon#read 6, iclass 35, count 0 2006.174.01:02:02.15#ibcon#end of sib2, iclass 35, count 0 2006.174.01:02:02.15#ibcon#*after write, iclass 35, count 0 2006.174.01:02:02.15#ibcon#*before return 0, iclass 35, count 0 2006.174.01:02:02.15#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.174.01:02:02.15#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.174.01:02:02.15#ibcon#about to clear, iclass 35 cls_cnt 0 2006.174.01:02:02.15#ibcon#cleared, iclass 35 cls_cnt 0 2006.174.01:02:02.15$vck44/valo=7,864.99 2006.174.01:02:02.15#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.174.01:02:02.15#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.174.01:02:02.15#ibcon#ireg 17 cls_cnt 0 2006.174.01:02:02.15#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.174.01:02:02.15#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.174.01:02:02.15#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.174.01:02:02.15#ibcon#enter wrdev, iclass 37, count 0 2006.174.01:02:02.15#ibcon#first serial, iclass 37, count 0 2006.174.01:02:02.15#ibcon#enter sib2, iclass 37, count 0 2006.174.01:02:02.15#ibcon#flushed, iclass 37, count 0 2006.174.01:02:02.15#ibcon#about to write, iclass 37, count 0 2006.174.01:02:02.15#ibcon#wrote, iclass 37, count 0 2006.174.01:02:02.15#ibcon#about to read 3, iclass 37, count 0 2006.174.01:02:02.17#ibcon#read 3, iclass 37, count 0 2006.174.01:02:02.17#ibcon#about to read 4, iclass 37, count 0 2006.174.01:02:02.17#ibcon#read 4, iclass 37, count 0 2006.174.01:02:02.17#ibcon#about to read 5, iclass 37, count 0 2006.174.01:02:02.17#ibcon#read 5, iclass 37, count 0 2006.174.01:02:02.17#ibcon#about to read 6, iclass 37, count 0 2006.174.01:02:02.17#ibcon#read 6, iclass 37, count 0 2006.174.01:02:02.17#ibcon#end of sib2, iclass 37, count 0 2006.174.01:02:02.17#ibcon#*mode == 0, iclass 37, count 0 2006.174.01:02:02.17#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.174.01:02:02.17#ibcon#[26=FRQ=07,864.99\r\n] 2006.174.01:02:02.17#ibcon#*before write, iclass 37, count 0 2006.174.01:02:02.17#ibcon#enter sib2, iclass 37, count 0 2006.174.01:02:02.17#ibcon#flushed, iclass 37, count 0 2006.174.01:02:02.17#ibcon#about to write, iclass 37, count 0 2006.174.01:02:02.17#ibcon#wrote, iclass 37, count 0 2006.174.01:02:02.17#ibcon#about to read 3, iclass 37, count 0 2006.174.01:02:02.21#ibcon#read 3, iclass 37, count 0 2006.174.01:02:02.21#ibcon#about to read 4, iclass 37, count 0 2006.174.01:02:02.21#ibcon#read 4, iclass 37, count 0 2006.174.01:02:02.21#ibcon#about to read 5, iclass 37, count 0 2006.174.01:02:02.21#ibcon#read 5, iclass 37, count 0 2006.174.01:02:02.21#ibcon#about to read 6, iclass 37, count 0 2006.174.01:02:02.21#ibcon#read 6, iclass 37, count 0 2006.174.01:02:02.21#ibcon#end of sib2, iclass 37, count 0 2006.174.01:02:02.21#ibcon#*after write, iclass 37, count 0 2006.174.01:02:02.21#ibcon#*before return 0, iclass 37, count 0 2006.174.01:02:02.21#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.174.01:02:02.21#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.174.01:02:02.21#ibcon#about to clear, iclass 37 cls_cnt 0 2006.174.01:02:02.21#ibcon#cleared, iclass 37 cls_cnt 0 2006.174.01:02:02.21$vck44/va=7,4 2006.174.01:02:02.21#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.174.01:02:02.21#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.174.01:02:02.21#ibcon#ireg 11 cls_cnt 2 2006.174.01:02:02.21#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.174.01:02:02.27#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.174.01:02:02.27#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.174.01:02:02.27#ibcon#enter wrdev, iclass 39, count 2 2006.174.01:02:02.27#ibcon#first serial, iclass 39, count 2 2006.174.01:02:02.27#ibcon#enter sib2, iclass 39, count 2 2006.174.01:02:02.27#ibcon#flushed, iclass 39, count 2 2006.174.01:02:02.27#ibcon#about to write, iclass 39, count 2 2006.174.01:02:02.27#ibcon#wrote, iclass 39, count 2 2006.174.01:02:02.27#ibcon#about to read 3, iclass 39, count 2 2006.174.01:02:02.29#ibcon#read 3, iclass 39, count 2 2006.174.01:02:02.29#ibcon#about to read 4, iclass 39, count 2 2006.174.01:02:02.29#ibcon#read 4, iclass 39, count 2 2006.174.01:02:02.29#ibcon#about to read 5, iclass 39, count 2 2006.174.01:02:02.29#ibcon#read 5, iclass 39, count 2 2006.174.01:02:02.29#ibcon#about to read 6, iclass 39, count 2 2006.174.01:02:02.29#ibcon#read 6, iclass 39, count 2 2006.174.01:02:02.29#ibcon#end of sib2, iclass 39, count 2 2006.174.01:02:02.29#ibcon#*mode == 0, iclass 39, count 2 2006.174.01:02:02.29#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.174.01:02:02.29#ibcon#[25=AT07-04\r\n] 2006.174.01:02:02.29#ibcon#*before write, iclass 39, count 2 2006.174.01:02:02.29#ibcon#enter sib2, iclass 39, count 2 2006.174.01:02:02.29#ibcon#flushed, iclass 39, count 2 2006.174.01:02:02.29#ibcon#about to write, iclass 39, count 2 2006.174.01:02:02.29#ibcon#wrote, iclass 39, count 2 2006.174.01:02:02.29#ibcon#about to read 3, iclass 39, count 2 2006.174.01:02:02.32#ibcon#read 3, iclass 39, count 2 2006.174.01:02:02.32#ibcon#about to read 4, iclass 39, count 2 2006.174.01:02:02.32#ibcon#read 4, iclass 39, count 2 2006.174.01:02:02.32#ibcon#about to read 5, iclass 39, count 2 2006.174.01:02:02.32#ibcon#read 5, iclass 39, count 2 2006.174.01:02:02.32#ibcon#about to read 6, iclass 39, count 2 2006.174.01:02:02.32#ibcon#read 6, iclass 39, count 2 2006.174.01:02:02.32#ibcon#end of sib2, iclass 39, count 2 2006.174.01:02:02.32#ibcon#*after write, iclass 39, count 2 2006.174.01:02:02.32#ibcon#*before return 0, iclass 39, count 2 2006.174.01:02:02.32#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.174.01:02:02.32#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.174.01:02:02.32#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.174.01:02:02.32#ibcon#ireg 7 cls_cnt 0 2006.174.01:02:02.32#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.174.01:02:02.44#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.174.01:02:02.44#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.174.01:02:02.44#ibcon#enter wrdev, iclass 39, count 0 2006.174.01:02:02.44#ibcon#first serial, iclass 39, count 0 2006.174.01:02:02.44#ibcon#enter sib2, iclass 39, count 0 2006.174.01:02:02.44#ibcon#flushed, iclass 39, count 0 2006.174.01:02:02.44#ibcon#about to write, iclass 39, count 0 2006.174.01:02:02.44#ibcon#wrote, iclass 39, count 0 2006.174.01:02:02.44#ibcon#about to read 3, iclass 39, count 0 2006.174.01:02:02.46#ibcon#read 3, iclass 39, count 0 2006.174.01:02:02.46#ibcon#about to read 4, iclass 39, count 0 2006.174.01:02:02.46#ibcon#read 4, iclass 39, count 0 2006.174.01:02:02.46#ibcon#about to read 5, iclass 39, count 0 2006.174.01:02:02.46#ibcon#read 5, iclass 39, count 0 2006.174.01:02:02.46#ibcon#about to read 6, iclass 39, count 0 2006.174.01:02:02.46#ibcon#read 6, iclass 39, count 0 2006.174.01:02:02.46#ibcon#end of sib2, iclass 39, count 0 2006.174.01:02:02.46#ibcon#*mode == 0, iclass 39, count 0 2006.174.01:02:02.46#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.174.01:02:02.46#ibcon#[25=USB\r\n] 2006.174.01:02:02.46#ibcon#*before write, iclass 39, count 0 2006.174.01:02:02.46#ibcon#enter sib2, iclass 39, count 0 2006.174.01:02:02.46#ibcon#flushed, iclass 39, count 0 2006.174.01:02:02.46#ibcon#about to write, iclass 39, count 0 2006.174.01:02:02.46#ibcon#wrote, iclass 39, count 0 2006.174.01:02:02.46#ibcon#about to read 3, iclass 39, count 0 2006.174.01:02:02.49#ibcon#read 3, iclass 39, count 0 2006.174.01:02:02.49#ibcon#about to read 4, iclass 39, count 0 2006.174.01:02:02.49#ibcon#read 4, iclass 39, count 0 2006.174.01:02:02.49#ibcon#about to read 5, iclass 39, count 0 2006.174.01:02:02.49#ibcon#read 5, iclass 39, count 0 2006.174.01:02:02.49#ibcon#about to read 6, iclass 39, count 0 2006.174.01:02:02.49#ibcon#read 6, iclass 39, count 0 2006.174.01:02:02.49#ibcon#end of sib2, iclass 39, count 0 2006.174.01:02:02.49#ibcon#*after write, iclass 39, count 0 2006.174.01:02:02.49#ibcon#*before return 0, iclass 39, count 0 2006.174.01:02:02.49#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.174.01:02:02.49#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.174.01:02:02.49#ibcon#about to clear, iclass 39 cls_cnt 0 2006.174.01:02:02.49#ibcon#cleared, iclass 39 cls_cnt 0 2006.174.01:02:02.49$vck44/valo=8,884.99 2006.174.01:02:02.49#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.174.01:02:02.49#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.174.01:02:02.49#ibcon#ireg 17 cls_cnt 0 2006.174.01:02:02.49#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.174.01:02:02.49#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.174.01:02:02.49#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.174.01:02:02.49#ibcon#enter wrdev, iclass 3, count 0 2006.174.01:02:02.49#ibcon#first serial, iclass 3, count 0 2006.174.01:02:02.49#ibcon#enter sib2, iclass 3, count 0 2006.174.01:02:02.49#ibcon#flushed, iclass 3, count 0 2006.174.01:02:02.49#ibcon#about to write, iclass 3, count 0 2006.174.01:02:02.49#ibcon#wrote, iclass 3, count 0 2006.174.01:02:02.49#ibcon#about to read 3, iclass 3, count 0 2006.174.01:02:02.51#ibcon#read 3, iclass 3, count 0 2006.174.01:02:02.51#ibcon#about to read 4, iclass 3, count 0 2006.174.01:02:02.51#ibcon#read 4, iclass 3, count 0 2006.174.01:02:02.51#ibcon#about to read 5, iclass 3, count 0 2006.174.01:02:02.51#ibcon#read 5, iclass 3, count 0 2006.174.01:02:02.51#ibcon#about to read 6, iclass 3, count 0 2006.174.01:02:02.51#ibcon#read 6, iclass 3, count 0 2006.174.01:02:02.51#ibcon#end of sib2, iclass 3, count 0 2006.174.01:02:02.51#ibcon#*mode == 0, iclass 3, count 0 2006.174.01:02:02.51#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.174.01:02:02.51#ibcon#[26=FRQ=08,884.99\r\n] 2006.174.01:02:02.51#ibcon#*before write, iclass 3, count 0 2006.174.01:02:02.51#ibcon#enter sib2, iclass 3, count 0 2006.174.01:02:02.51#ibcon#flushed, iclass 3, count 0 2006.174.01:02:02.51#ibcon#about to write, iclass 3, count 0 2006.174.01:02:02.51#ibcon#wrote, iclass 3, count 0 2006.174.01:02:02.51#ibcon#about to read 3, iclass 3, count 0 2006.174.01:02:02.55#ibcon#read 3, iclass 3, count 0 2006.174.01:02:02.55#ibcon#about to read 4, iclass 3, count 0 2006.174.01:02:02.55#ibcon#read 4, iclass 3, count 0 2006.174.01:02:02.55#ibcon#about to read 5, iclass 3, count 0 2006.174.01:02:02.55#ibcon#read 5, iclass 3, count 0 2006.174.01:02:02.55#ibcon#about to read 6, iclass 3, count 0 2006.174.01:02:02.55#ibcon#read 6, iclass 3, count 0 2006.174.01:02:02.55#ibcon#end of sib2, iclass 3, count 0 2006.174.01:02:02.55#ibcon#*after write, iclass 3, count 0 2006.174.01:02:02.55#ibcon#*before return 0, iclass 3, count 0 2006.174.01:02:02.55#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.174.01:02:02.55#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.174.01:02:02.55#ibcon#about to clear, iclass 3 cls_cnt 0 2006.174.01:02:02.55#ibcon#cleared, iclass 3 cls_cnt 0 2006.174.01:02:02.55$vck44/va=8,4 2006.174.01:02:02.55#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.174.01:02:02.55#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.174.01:02:02.55#ibcon#ireg 11 cls_cnt 2 2006.174.01:02:02.55#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.174.01:02:02.61#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.174.01:02:02.61#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.174.01:02:02.61#ibcon#enter wrdev, iclass 5, count 2 2006.174.01:02:02.61#ibcon#first serial, iclass 5, count 2 2006.174.01:02:02.61#ibcon#enter sib2, iclass 5, count 2 2006.174.01:02:02.61#ibcon#flushed, iclass 5, count 2 2006.174.01:02:02.61#ibcon#about to write, iclass 5, count 2 2006.174.01:02:02.61#ibcon#wrote, iclass 5, count 2 2006.174.01:02:02.61#ibcon#about to read 3, iclass 5, count 2 2006.174.01:02:02.63#ibcon#read 3, iclass 5, count 2 2006.174.01:02:02.63#ibcon#about to read 4, iclass 5, count 2 2006.174.01:02:02.63#ibcon#read 4, iclass 5, count 2 2006.174.01:02:02.63#ibcon#about to read 5, iclass 5, count 2 2006.174.01:02:02.63#ibcon#read 5, iclass 5, count 2 2006.174.01:02:02.63#ibcon#about to read 6, iclass 5, count 2 2006.174.01:02:02.63#ibcon#read 6, iclass 5, count 2 2006.174.01:02:02.63#ibcon#end of sib2, iclass 5, count 2 2006.174.01:02:02.63#ibcon#*mode == 0, iclass 5, count 2 2006.174.01:02:02.63#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.174.01:02:02.63#ibcon#[25=AT08-04\r\n] 2006.174.01:02:02.63#ibcon#*before write, iclass 5, count 2 2006.174.01:02:02.63#ibcon#enter sib2, iclass 5, count 2 2006.174.01:02:02.63#ibcon#flushed, iclass 5, count 2 2006.174.01:02:02.63#ibcon#about to write, iclass 5, count 2 2006.174.01:02:02.63#ibcon#wrote, iclass 5, count 2 2006.174.01:02:02.63#ibcon#about to read 3, iclass 5, count 2 2006.174.01:02:02.66#ibcon#read 3, iclass 5, count 2 2006.174.01:02:02.66#ibcon#about to read 4, iclass 5, count 2 2006.174.01:02:02.66#ibcon#read 4, iclass 5, count 2 2006.174.01:02:02.66#ibcon#about to read 5, iclass 5, count 2 2006.174.01:02:02.66#ibcon#read 5, iclass 5, count 2 2006.174.01:02:02.66#ibcon#about to read 6, iclass 5, count 2 2006.174.01:02:02.66#ibcon#read 6, iclass 5, count 2 2006.174.01:02:02.66#ibcon#end of sib2, iclass 5, count 2 2006.174.01:02:02.66#ibcon#*after write, iclass 5, count 2 2006.174.01:02:02.66#ibcon#*before return 0, iclass 5, count 2 2006.174.01:02:02.66#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.174.01:02:02.66#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.174.01:02:02.66#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.174.01:02:02.66#ibcon#ireg 7 cls_cnt 0 2006.174.01:02:02.66#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.174.01:02:02.78#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.174.01:02:02.78#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.174.01:02:02.78#ibcon#enter wrdev, iclass 5, count 0 2006.174.01:02:02.78#ibcon#first serial, iclass 5, count 0 2006.174.01:02:02.78#ibcon#enter sib2, iclass 5, count 0 2006.174.01:02:02.78#ibcon#flushed, iclass 5, count 0 2006.174.01:02:02.78#ibcon#about to write, iclass 5, count 0 2006.174.01:02:02.78#ibcon#wrote, iclass 5, count 0 2006.174.01:02:02.78#ibcon#about to read 3, iclass 5, count 0 2006.174.01:02:02.80#ibcon#read 3, iclass 5, count 0 2006.174.01:02:02.80#ibcon#about to read 4, iclass 5, count 0 2006.174.01:02:02.80#ibcon#read 4, iclass 5, count 0 2006.174.01:02:02.80#ibcon#about to read 5, iclass 5, count 0 2006.174.01:02:02.80#ibcon#read 5, iclass 5, count 0 2006.174.01:02:02.80#ibcon#about to read 6, iclass 5, count 0 2006.174.01:02:02.80#ibcon#read 6, iclass 5, count 0 2006.174.01:02:02.80#ibcon#end of sib2, iclass 5, count 0 2006.174.01:02:02.80#ibcon#*mode == 0, iclass 5, count 0 2006.174.01:02:02.80#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.174.01:02:02.80#ibcon#[25=USB\r\n] 2006.174.01:02:02.80#ibcon#*before write, iclass 5, count 0 2006.174.01:02:02.80#ibcon#enter sib2, iclass 5, count 0 2006.174.01:02:02.80#ibcon#flushed, iclass 5, count 0 2006.174.01:02:02.80#ibcon#about to write, iclass 5, count 0 2006.174.01:02:02.80#ibcon#wrote, iclass 5, count 0 2006.174.01:02:02.80#ibcon#about to read 3, iclass 5, count 0 2006.174.01:02:02.83#ibcon#read 3, iclass 5, count 0 2006.174.01:02:02.83#ibcon#about to read 4, iclass 5, count 0 2006.174.01:02:02.83#ibcon#read 4, iclass 5, count 0 2006.174.01:02:02.83#ibcon#about to read 5, iclass 5, count 0 2006.174.01:02:02.83#ibcon#read 5, iclass 5, count 0 2006.174.01:02:02.83#ibcon#about to read 6, iclass 5, count 0 2006.174.01:02:02.83#ibcon#read 6, iclass 5, count 0 2006.174.01:02:02.83#ibcon#end of sib2, iclass 5, count 0 2006.174.01:02:02.83#ibcon#*after write, iclass 5, count 0 2006.174.01:02:02.83#ibcon#*before return 0, iclass 5, count 0 2006.174.01:02:02.83#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.174.01:02:02.83#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.174.01:02:02.83#ibcon#about to clear, iclass 5 cls_cnt 0 2006.174.01:02:02.83#ibcon#cleared, iclass 5 cls_cnt 0 2006.174.01:02:02.83$vck44/vblo=1,629.99 2006.174.01:02:02.83#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.174.01:02:02.83#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.174.01:02:02.83#ibcon#ireg 17 cls_cnt 0 2006.174.01:02:02.83#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.174.01:02:02.83#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.174.01:02:02.83#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.174.01:02:02.83#ibcon#enter wrdev, iclass 7, count 0 2006.174.01:02:02.83#ibcon#first serial, iclass 7, count 0 2006.174.01:02:02.83#ibcon#enter sib2, iclass 7, count 0 2006.174.01:02:02.83#ibcon#flushed, iclass 7, count 0 2006.174.01:02:02.83#ibcon#about to write, iclass 7, count 0 2006.174.01:02:02.83#ibcon#wrote, iclass 7, count 0 2006.174.01:02:02.83#ibcon#about to read 3, iclass 7, count 0 2006.174.01:02:02.85#ibcon#read 3, iclass 7, count 0 2006.174.01:02:02.85#ibcon#about to read 4, iclass 7, count 0 2006.174.01:02:02.85#ibcon#read 4, iclass 7, count 0 2006.174.01:02:02.85#ibcon#about to read 5, iclass 7, count 0 2006.174.01:02:02.85#ibcon#read 5, iclass 7, count 0 2006.174.01:02:02.85#ibcon#about to read 6, iclass 7, count 0 2006.174.01:02:02.85#ibcon#read 6, iclass 7, count 0 2006.174.01:02:02.85#ibcon#end of sib2, iclass 7, count 0 2006.174.01:02:02.85#ibcon#*mode == 0, iclass 7, count 0 2006.174.01:02:02.85#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.174.01:02:02.85#ibcon#[28=FRQ=01,629.99\r\n] 2006.174.01:02:02.85#ibcon#*before write, iclass 7, count 0 2006.174.01:02:02.85#ibcon#enter sib2, iclass 7, count 0 2006.174.01:02:02.85#ibcon#flushed, iclass 7, count 0 2006.174.01:02:02.85#ibcon#about to write, iclass 7, count 0 2006.174.01:02:02.85#ibcon#wrote, iclass 7, count 0 2006.174.01:02:02.85#ibcon#about to read 3, iclass 7, count 0 2006.174.01:02:02.89#ibcon#read 3, iclass 7, count 0 2006.174.01:02:02.89#ibcon#about to read 4, iclass 7, count 0 2006.174.01:02:02.89#ibcon#read 4, iclass 7, count 0 2006.174.01:02:02.89#ibcon#about to read 5, iclass 7, count 0 2006.174.01:02:02.89#ibcon#read 5, iclass 7, count 0 2006.174.01:02:02.89#ibcon#about to read 6, iclass 7, count 0 2006.174.01:02:02.89#ibcon#read 6, iclass 7, count 0 2006.174.01:02:02.89#ibcon#end of sib2, iclass 7, count 0 2006.174.01:02:02.89#ibcon#*after write, iclass 7, count 0 2006.174.01:02:02.89#ibcon#*before return 0, iclass 7, count 0 2006.174.01:02:02.89#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.174.01:02:02.89#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.174.01:02:02.89#ibcon#about to clear, iclass 7 cls_cnt 0 2006.174.01:02:02.89#ibcon#cleared, iclass 7 cls_cnt 0 2006.174.01:02:02.89$vck44/vb=1,4 2006.174.01:02:02.89#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.174.01:02:02.89#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.174.01:02:02.89#ibcon#ireg 11 cls_cnt 2 2006.174.01:02:02.89#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.174.01:02:02.89#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.174.01:02:02.89#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.174.01:02:02.89#ibcon#enter wrdev, iclass 11, count 2 2006.174.01:02:02.89#ibcon#first serial, iclass 11, count 2 2006.174.01:02:02.89#ibcon#enter sib2, iclass 11, count 2 2006.174.01:02:02.89#ibcon#flushed, iclass 11, count 2 2006.174.01:02:02.89#ibcon#about to write, iclass 11, count 2 2006.174.01:02:02.89#ibcon#wrote, iclass 11, count 2 2006.174.01:02:02.89#ibcon#about to read 3, iclass 11, count 2 2006.174.01:02:02.91#ibcon#read 3, iclass 11, count 2 2006.174.01:02:02.91#ibcon#about to read 4, iclass 11, count 2 2006.174.01:02:02.91#ibcon#read 4, iclass 11, count 2 2006.174.01:02:02.91#ibcon#about to read 5, iclass 11, count 2 2006.174.01:02:02.91#ibcon#read 5, iclass 11, count 2 2006.174.01:02:02.91#ibcon#about to read 6, iclass 11, count 2 2006.174.01:02:02.91#ibcon#read 6, iclass 11, count 2 2006.174.01:02:02.91#ibcon#end of sib2, iclass 11, count 2 2006.174.01:02:02.91#ibcon#*mode == 0, iclass 11, count 2 2006.174.01:02:02.91#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.174.01:02:02.91#ibcon#[27=AT01-04\r\n] 2006.174.01:02:02.91#ibcon#*before write, iclass 11, count 2 2006.174.01:02:02.91#ibcon#enter sib2, iclass 11, count 2 2006.174.01:02:02.91#ibcon#flushed, iclass 11, count 2 2006.174.01:02:02.91#ibcon#about to write, iclass 11, count 2 2006.174.01:02:02.91#ibcon#wrote, iclass 11, count 2 2006.174.01:02:02.91#ibcon#about to read 3, iclass 11, count 2 2006.174.01:02:02.94#ibcon#read 3, iclass 11, count 2 2006.174.01:02:02.94#ibcon#about to read 4, iclass 11, count 2 2006.174.01:02:02.94#ibcon#read 4, iclass 11, count 2 2006.174.01:02:02.94#ibcon#about to read 5, iclass 11, count 2 2006.174.01:02:02.94#ibcon#read 5, iclass 11, count 2 2006.174.01:02:02.94#ibcon#about to read 6, iclass 11, count 2 2006.174.01:02:02.94#ibcon#read 6, iclass 11, count 2 2006.174.01:02:02.94#ibcon#end of sib2, iclass 11, count 2 2006.174.01:02:02.94#ibcon#*after write, iclass 11, count 2 2006.174.01:02:02.94#ibcon#*before return 0, iclass 11, count 2 2006.174.01:02:02.94#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.174.01:02:02.94#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.174.01:02:02.94#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.174.01:02:02.94#ibcon#ireg 7 cls_cnt 0 2006.174.01:02:02.94#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.174.01:02:03.06#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.174.01:02:03.06#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.174.01:02:03.06#ibcon#enter wrdev, iclass 11, count 0 2006.174.01:02:03.06#ibcon#first serial, iclass 11, count 0 2006.174.01:02:03.06#ibcon#enter sib2, iclass 11, count 0 2006.174.01:02:03.06#ibcon#flushed, iclass 11, count 0 2006.174.01:02:03.06#ibcon#about to write, iclass 11, count 0 2006.174.01:02:03.06#ibcon#wrote, iclass 11, count 0 2006.174.01:02:03.06#ibcon#about to read 3, iclass 11, count 0 2006.174.01:02:03.08#ibcon#read 3, iclass 11, count 0 2006.174.01:02:03.08#ibcon#about to read 4, iclass 11, count 0 2006.174.01:02:03.08#ibcon#read 4, iclass 11, count 0 2006.174.01:02:03.08#ibcon#about to read 5, iclass 11, count 0 2006.174.01:02:03.08#ibcon#read 5, iclass 11, count 0 2006.174.01:02:03.08#ibcon#about to read 6, iclass 11, count 0 2006.174.01:02:03.08#ibcon#read 6, iclass 11, count 0 2006.174.01:02:03.08#ibcon#end of sib2, iclass 11, count 0 2006.174.01:02:03.08#ibcon#*mode == 0, iclass 11, count 0 2006.174.01:02:03.08#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.174.01:02:03.08#ibcon#[27=USB\r\n] 2006.174.01:02:03.08#ibcon#*before write, iclass 11, count 0 2006.174.01:02:03.08#ibcon#enter sib2, iclass 11, count 0 2006.174.01:02:03.08#ibcon#flushed, iclass 11, count 0 2006.174.01:02:03.08#ibcon#about to write, iclass 11, count 0 2006.174.01:02:03.08#ibcon#wrote, iclass 11, count 0 2006.174.01:02:03.08#ibcon#about to read 3, iclass 11, count 0 2006.174.01:02:03.11#ibcon#read 3, iclass 11, count 0 2006.174.01:02:03.11#ibcon#about to read 4, iclass 11, count 0 2006.174.01:02:03.11#ibcon#read 4, iclass 11, count 0 2006.174.01:02:03.11#ibcon#about to read 5, iclass 11, count 0 2006.174.01:02:03.11#ibcon#read 5, iclass 11, count 0 2006.174.01:02:03.11#ibcon#about to read 6, iclass 11, count 0 2006.174.01:02:03.11#ibcon#read 6, iclass 11, count 0 2006.174.01:02:03.11#ibcon#end of sib2, iclass 11, count 0 2006.174.01:02:03.11#ibcon#*after write, iclass 11, count 0 2006.174.01:02:03.11#ibcon#*before return 0, iclass 11, count 0 2006.174.01:02:03.11#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.174.01:02:03.11#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.174.01:02:03.11#ibcon#about to clear, iclass 11 cls_cnt 0 2006.174.01:02:03.11#ibcon#cleared, iclass 11 cls_cnt 0 2006.174.01:02:03.11$vck44/vblo=2,634.99 2006.174.01:02:03.11#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.174.01:02:03.11#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.174.01:02:03.11#ibcon#ireg 17 cls_cnt 0 2006.174.01:02:03.11#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.174.01:02:03.11#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.174.01:02:03.11#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.174.01:02:03.11#ibcon#enter wrdev, iclass 13, count 0 2006.174.01:02:03.11#ibcon#first serial, iclass 13, count 0 2006.174.01:02:03.11#ibcon#enter sib2, iclass 13, count 0 2006.174.01:02:03.11#ibcon#flushed, iclass 13, count 0 2006.174.01:02:03.11#ibcon#about to write, iclass 13, count 0 2006.174.01:02:03.11#ibcon#wrote, iclass 13, count 0 2006.174.01:02:03.11#ibcon#about to read 3, iclass 13, count 0 2006.174.01:02:03.13#ibcon#read 3, iclass 13, count 0 2006.174.01:02:03.13#ibcon#about to read 4, iclass 13, count 0 2006.174.01:02:03.13#ibcon#read 4, iclass 13, count 0 2006.174.01:02:03.13#ibcon#about to read 5, iclass 13, count 0 2006.174.01:02:03.13#ibcon#read 5, iclass 13, count 0 2006.174.01:02:03.13#ibcon#about to read 6, iclass 13, count 0 2006.174.01:02:03.13#ibcon#read 6, iclass 13, count 0 2006.174.01:02:03.13#ibcon#end of sib2, iclass 13, count 0 2006.174.01:02:03.13#ibcon#*mode == 0, iclass 13, count 0 2006.174.01:02:03.13#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.174.01:02:03.13#ibcon#[28=FRQ=02,634.99\r\n] 2006.174.01:02:03.13#ibcon#*before write, iclass 13, count 0 2006.174.01:02:03.13#ibcon#enter sib2, iclass 13, count 0 2006.174.01:02:03.13#ibcon#flushed, iclass 13, count 0 2006.174.01:02:03.13#ibcon#about to write, iclass 13, count 0 2006.174.01:02:03.13#ibcon#wrote, iclass 13, count 0 2006.174.01:02:03.13#ibcon#about to read 3, iclass 13, count 0 2006.174.01:02:03.17#ibcon#read 3, iclass 13, count 0 2006.174.01:02:03.17#ibcon#about to read 4, iclass 13, count 0 2006.174.01:02:03.17#ibcon#read 4, iclass 13, count 0 2006.174.01:02:03.17#ibcon#about to read 5, iclass 13, count 0 2006.174.01:02:03.17#ibcon#read 5, iclass 13, count 0 2006.174.01:02:03.17#ibcon#about to read 6, iclass 13, count 0 2006.174.01:02:03.17#ibcon#read 6, iclass 13, count 0 2006.174.01:02:03.17#ibcon#end of sib2, iclass 13, count 0 2006.174.01:02:03.17#ibcon#*after write, iclass 13, count 0 2006.174.01:02:03.17#ibcon#*before return 0, iclass 13, count 0 2006.174.01:02:03.17#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.174.01:02:03.17#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.174.01:02:03.17#ibcon#about to clear, iclass 13 cls_cnt 0 2006.174.01:02:03.17#ibcon#cleared, iclass 13 cls_cnt 0 2006.174.01:02:03.17$vck44/vb=2,4 2006.174.01:02:03.17#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.174.01:02:03.17#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.174.01:02:03.17#ibcon#ireg 11 cls_cnt 2 2006.174.01:02:03.17#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.174.01:02:03.23#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.174.01:02:03.23#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.174.01:02:03.23#ibcon#enter wrdev, iclass 15, count 2 2006.174.01:02:03.23#ibcon#first serial, iclass 15, count 2 2006.174.01:02:03.23#ibcon#enter sib2, iclass 15, count 2 2006.174.01:02:03.23#ibcon#flushed, iclass 15, count 2 2006.174.01:02:03.23#ibcon#about to write, iclass 15, count 2 2006.174.01:02:03.23#ibcon#wrote, iclass 15, count 2 2006.174.01:02:03.23#ibcon#about to read 3, iclass 15, count 2 2006.174.01:02:03.25#ibcon#read 3, iclass 15, count 2 2006.174.01:02:03.25#ibcon#about to read 4, iclass 15, count 2 2006.174.01:02:03.25#ibcon#read 4, iclass 15, count 2 2006.174.01:02:03.25#ibcon#about to read 5, iclass 15, count 2 2006.174.01:02:03.25#ibcon#read 5, iclass 15, count 2 2006.174.01:02:03.25#ibcon#about to read 6, iclass 15, count 2 2006.174.01:02:03.25#ibcon#read 6, iclass 15, count 2 2006.174.01:02:03.25#ibcon#end of sib2, iclass 15, count 2 2006.174.01:02:03.25#ibcon#*mode == 0, iclass 15, count 2 2006.174.01:02:03.25#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.174.01:02:03.25#ibcon#[27=AT02-04\r\n] 2006.174.01:02:03.25#ibcon#*before write, iclass 15, count 2 2006.174.01:02:03.25#ibcon#enter sib2, iclass 15, count 2 2006.174.01:02:03.25#ibcon#flushed, iclass 15, count 2 2006.174.01:02:03.25#ibcon#about to write, iclass 15, count 2 2006.174.01:02:03.25#ibcon#wrote, iclass 15, count 2 2006.174.01:02:03.25#ibcon#about to read 3, iclass 15, count 2 2006.174.01:02:03.28#ibcon#read 3, iclass 15, count 2 2006.174.01:02:03.28#ibcon#about to read 4, iclass 15, count 2 2006.174.01:02:03.28#ibcon#read 4, iclass 15, count 2 2006.174.01:02:03.28#ibcon#about to read 5, iclass 15, count 2 2006.174.01:02:03.28#ibcon#read 5, iclass 15, count 2 2006.174.01:02:03.28#ibcon#about to read 6, iclass 15, count 2 2006.174.01:02:03.28#ibcon#read 6, iclass 15, count 2 2006.174.01:02:03.28#ibcon#end of sib2, iclass 15, count 2 2006.174.01:02:03.28#ibcon#*after write, iclass 15, count 2 2006.174.01:02:03.28#ibcon#*before return 0, iclass 15, count 2 2006.174.01:02:03.28#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.174.01:02:03.28#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.174.01:02:03.28#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.174.01:02:03.28#ibcon#ireg 7 cls_cnt 0 2006.174.01:02:03.28#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.174.01:02:03.40#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.174.01:02:03.40#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.174.01:02:03.40#ibcon#enter wrdev, iclass 15, count 0 2006.174.01:02:03.40#ibcon#first serial, iclass 15, count 0 2006.174.01:02:03.40#ibcon#enter sib2, iclass 15, count 0 2006.174.01:02:03.40#ibcon#flushed, iclass 15, count 0 2006.174.01:02:03.40#ibcon#about to write, iclass 15, count 0 2006.174.01:02:03.40#ibcon#wrote, iclass 15, count 0 2006.174.01:02:03.40#ibcon#about to read 3, iclass 15, count 0 2006.174.01:02:03.42#ibcon#read 3, iclass 15, count 0 2006.174.01:02:03.42#ibcon#about to read 4, iclass 15, count 0 2006.174.01:02:03.42#ibcon#read 4, iclass 15, count 0 2006.174.01:02:03.42#ibcon#about to read 5, iclass 15, count 0 2006.174.01:02:03.42#ibcon#read 5, iclass 15, count 0 2006.174.01:02:03.42#ibcon#about to read 6, iclass 15, count 0 2006.174.01:02:03.42#ibcon#read 6, iclass 15, count 0 2006.174.01:02:03.42#ibcon#end of sib2, iclass 15, count 0 2006.174.01:02:03.42#ibcon#*mode == 0, iclass 15, count 0 2006.174.01:02:03.42#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.174.01:02:03.42#ibcon#[27=USB\r\n] 2006.174.01:02:03.42#ibcon#*before write, iclass 15, count 0 2006.174.01:02:03.42#ibcon#enter sib2, iclass 15, count 0 2006.174.01:02:03.42#ibcon#flushed, iclass 15, count 0 2006.174.01:02:03.42#ibcon#about to write, iclass 15, count 0 2006.174.01:02:03.42#ibcon#wrote, iclass 15, count 0 2006.174.01:02:03.42#ibcon#about to read 3, iclass 15, count 0 2006.174.01:02:03.45#ibcon#read 3, iclass 15, count 0 2006.174.01:02:03.45#ibcon#about to read 4, iclass 15, count 0 2006.174.01:02:03.45#ibcon#read 4, iclass 15, count 0 2006.174.01:02:03.45#ibcon#about to read 5, iclass 15, count 0 2006.174.01:02:03.45#ibcon#read 5, iclass 15, count 0 2006.174.01:02:03.45#ibcon#about to read 6, iclass 15, count 0 2006.174.01:02:03.45#ibcon#read 6, iclass 15, count 0 2006.174.01:02:03.45#ibcon#end of sib2, iclass 15, count 0 2006.174.01:02:03.45#ibcon#*after write, iclass 15, count 0 2006.174.01:02:03.45#ibcon#*before return 0, iclass 15, count 0 2006.174.01:02:03.45#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.174.01:02:03.45#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.174.01:02:03.45#ibcon#about to clear, iclass 15 cls_cnt 0 2006.174.01:02:03.45#ibcon#cleared, iclass 15 cls_cnt 0 2006.174.01:02:03.45$vck44/vblo=3,649.99 2006.174.01:02:03.45#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.174.01:02:03.45#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.174.01:02:03.45#ibcon#ireg 17 cls_cnt 0 2006.174.01:02:03.45#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.174.01:02:03.45#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.174.01:02:03.45#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.174.01:02:03.45#ibcon#enter wrdev, iclass 17, count 0 2006.174.01:02:03.45#ibcon#first serial, iclass 17, count 0 2006.174.01:02:03.45#ibcon#enter sib2, iclass 17, count 0 2006.174.01:02:03.45#ibcon#flushed, iclass 17, count 0 2006.174.01:02:03.45#ibcon#about to write, iclass 17, count 0 2006.174.01:02:03.45#ibcon#wrote, iclass 17, count 0 2006.174.01:02:03.45#ibcon#about to read 3, iclass 17, count 0 2006.174.01:02:03.47#ibcon#read 3, iclass 17, count 0 2006.174.01:02:03.47#ibcon#about to read 4, iclass 17, count 0 2006.174.01:02:03.47#ibcon#read 4, iclass 17, count 0 2006.174.01:02:03.47#ibcon#about to read 5, iclass 17, count 0 2006.174.01:02:03.47#ibcon#read 5, iclass 17, count 0 2006.174.01:02:03.47#ibcon#about to read 6, iclass 17, count 0 2006.174.01:02:03.47#ibcon#read 6, iclass 17, count 0 2006.174.01:02:03.47#ibcon#end of sib2, iclass 17, count 0 2006.174.01:02:03.47#ibcon#*mode == 0, iclass 17, count 0 2006.174.01:02:03.47#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.174.01:02:03.47#ibcon#[28=FRQ=03,649.99\r\n] 2006.174.01:02:03.47#ibcon#*before write, iclass 17, count 0 2006.174.01:02:03.47#ibcon#enter sib2, iclass 17, count 0 2006.174.01:02:03.47#ibcon#flushed, iclass 17, count 0 2006.174.01:02:03.47#ibcon#about to write, iclass 17, count 0 2006.174.01:02:03.47#ibcon#wrote, iclass 17, count 0 2006.174.01:02:03.47#ibcon#about to read 3, iclass 17, count 0 2006.174.01:02:03.51#ibcon#read 3, iclass 17, count 0 2006.174.01:02:03.51#ibcon#about to read 4, iclass 17, count 0 2006.174.01:02:03.51#ibcon#read 4, iclass 17, count 0 2006.174.01:02:03.51#ibcon#about to read 5, iclass 17, count 0 2006.174.01:02:03.51#ibcon#read 5, iclass 17, count 0 2006.174.01:02:03.51#ibcon#about to read 6, iclass 17, count 0 2006.174.01:02:03.51#ibcon#read 6, iclass 17, count 0 2006.174.01:02:03.51#ibcon#end of sib2, iclass 17, count 0 2006.174.01:02:03.51#ibcon#*after write, iclass 17, count 0 2006.174.01:02:03.51#ibcon#*before return 0, iclass 17, count 0 2006.174.01:02:03.51#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.174.01:02:03.51#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.174.01:02:03.51#ibcon#about to clear, iclass 17 cls_cnt 0 2006.174.01:02:03.51#ibcon#cleared, iclass 17 cls_cnt 0 2006.174.01:02:03.51$vck44/vb=3,4 2006.174.01:02:03.51#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.174.01:02:03.51#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.174.01:02:03.51#ibcon#ireg 11 cls_cnt 2 2006.174.01:02:03.51#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.174.01:02:03.57#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.174.01:02:03.57#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.174.01:02:03.57#ibcon#enter wrdev, iclass 19, count 2 2006.174.01:02:03.57#ibcon#first serial, iclass 19, count 2 2006.174.01:02:03.57#ibcon#enter sib2, iclass 19, count 2 2006.174.01:02:03.57#ibcon#flushed, iclass 19, count 2 2006.174.01:02:03.57#ibcon#about to write, iclass 19, count 2 2006.174.01:02:03.57#ibcon#wrote, iclass 19, count 2 2006.174.01:02:03.57#ibcon#about to read 3, iclass 19, count 2 2006.174.01:02:03.59#ibcon#read 3, iclass 19, count 2 2006.174.01:02:03.59#ibcon#about to read 4, iclass 19, count 2 2006.174.01:02:03.59#ibcon#read 4, iclass 19, count 2 2006.174.01:02:03.59#ibcon#about to read 5, iclass 19, count 2 2006.174.01:02:03.59#ibcon#read 5, iclass 19, count 2 2006.174.01:02:03.59#ibcon#about to read 6, iclass 19, count 2 2006.174.01:02:03.59#ibcon#read 6, iclass 19, count 2 2006.174.01:02:03.59#ibcon#end of sib2, iclass 19, count 2 2006.174.01:02:03.59#ibcon#*mode == 0, iclass 19, count 2 2006.174.01:02:03.59#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.174.01:02:03.59#ibcon#[27=AT03-04\r\n] 2006.174.01:02:03.59#ibcon#*before write, iclass 19, count 2 2006.174.01:02:03.59#ibcon#enter sib2, iclass 19, count 2 2006.174.01:02:03.59#ibcon#flushed, iclass 19, count 2 2006.174.01:02:03.59#ibcon#about to write, iclass 19, count 2 2006.174.01:02:03.59#ibcon#wrote, iclass 19, count 2 2006.174.01:02:03.59#ibcon#about to read 3, iclass 19, count 2 2006.174.01:02:03.62#ibcon#read 3, iclass 19, count 2 2006.174.01:02:03.62#ibcon#about to read 4, iclass 19, count 2 2006.174.01:02:03.62#ibcon#read 4, iclass 19, count 2 2006.174.01:02:03.62#ibcon#about to read 5, iclass 19, count 2 2006.174.01:02:03.62#ibcon#read 5, iclass 19, count 2 2006.174.01:02:03.62#ibcon#about to read 6, iclass 19, count 2 2006.174.01:02:03.62#ibcon#read 6, iclass 19, count 2 2006.174.01:02:03.62#ibcon#end of sib2, iclass 19, count 2 2006.174.01:02:03.62#ibcon#*after write, iclass 19, count 2 2006.174.01:02:03.62#ibcon#*before return 0, iclass 19, count 2 2006.174.01:02:03.62#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.174.01:02:03.62#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.174.01:02:03.62#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.174.01:02:03.62#ibcon#ireg 7 cls_cnt 0 2006.174.01:02:03.62#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.174.01:02:03.74#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.174.01:02:03.74#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.174.01:02:03.74#ibcon#enter wrdev, iclass 19, count 0 2006.174.01:02:03.74#ibcon#first serial, iclass 19, count 0 2006.174.01:02:03.74#ibcon#enter sib2, iclass 19, count 0 2006.174.01:02:03.74#ibcon#flushed, iclass 19, count 0 2006.174.01:02:03.74#ibcon#about to write, iclass 19, count 0 2006.174.01:02:03.74#ibcon#wrote, iclass 19, count 0 2006.174.01:02:03.74#ibcon#about to read 3, iclass 19, count 0 2006.174.01:02:03.76#ibcon#read 3, iclass 19, count 0 2006.174.01:02:03.76#ibcon#about to read 4, iclass 19, count 0 2006.174.01:02:03.76#ibcon#read 4, iclass 19, count 0 2006.174.01:02:03.76#ibcon#about to read 5, iclass 19, count 0 2006.174.01:02:03.76#ibcon#read 5, iclass 19, count 0 2006.174.01:02:03.76#ibcon#about to read 6, iclass 19, count 0 2006.174.01:02:03.76#ibcon#read 6, iclass 19, count 0 2006.174.01:02:03.76#ibcon#end of sib2, iclass 19, count 0 2006.174.01:02:03.76#ibcon#*mode == 0, iclass 19, count 0 2006.174.01:02:03.76#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.174.01:02:03.76#ibcon#[27=USB\r\n] 2006.174.01:02:03.76#ibcon#*before write, iclass 19, count 0 2006.174.01:02:03.76#ibcon#enter sib2, iclass 19, count 0 2006.174.01:02:03.76#ibcon#flushed, iclass 19, count 0 2006.174.01:02:03.76#ibcon#about to write, iclass 19, count 0 2006.174.01:02:03.76#ibcon#wrote, iclass 19, count 0 2006.174.01:02:03.76#ibcon#about to read 3, iclass 19, count 0 2006.174.01:02:03.79#ibcon#read 3, iclass 19, count 0 2006.174.01:02:03.79#ibcon#about to read 4, iclass 19, count 0 2006.174.01:02:03.79#ibcon#read 4, iclass 19, count 0 2006.174.01:02:03.79#ibcon#about to read 5, iclass 19, count 0 2006.174.01:02:03.79#ibcon#read 5, iclass 19, count 0 2006.174.01:02:03.79#ibcon#about to read 6, iclass 19, count 0 2006.174.01:02:03.79#ibcon#read 6, iclass 19, count 0 2006.174.01:02:03.79#ibcon#end of sib2, iclass 19, count 0 2006.174.01:02:03.79#ibcon#*after write, iclass 19, count 0 2006.174.01:02:03.79#ibcon#*before return 0, iclass 19, count 0 2006.174.01:02:03.79#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.174.01:02:03.79#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.174.01:02:03.79#ibcon#about to clear, iclass 19 cls_cnt 0 2006.174.01:02:03.79#ibcon#cleared, iclass 19 cls_cnt 0 2006.174.01:02:03.79$vck44/vblo=4,679.99 2006.174.01:02:03.79#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.174.01:02:03.79#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.174.01:02:03.79#ibcon#ireg 17 cls_cnt 0 2006.174.01:02:03.79#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.174.01:02:03.79#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.174.01:02:03.79#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.174.01:02:03.79#ibcon#enter wrdev, iclass 21, count 0 2006.174.01:02:03.79#ibcon#first serial, iclass 21, count 0 2006.174.01:02:03.79#ibcon#enter sib2, iclass 21, count 0 2006.174.01:02:03.79#ibcon#flushed, iclass 21, count 0 2006.174.01:02:03.79#ibcon#about to write, iclass 21, count 0 2006.174.01:02:03.79#ibcon#wrote, iclass 21, count 0 2006.174.01:02:03.79#ibcon#about to read 3, iclass 21, count 0 2006.174.01:02:03.81#ibcon#read 3, iclass 21, count 0 2006.174.01:02:03.81#ibcon#about to read 4, iclass 21, count 0 2006.174.01:02:03.81#ibcon#read 4, iclass 21, count 0 2006.174.01:02:03.81#ibcon#about to read 5, iclass 21, count 0 2006.174.01:02:03.81#ibcon#read 5, iclass 21, count 0 2006.174.01:02:03.81#ibcon#about to read 6, iclass 21, count 0 2006.174.01:02:03.81#ibcon#read 6, iclass 21, count 0 2006.174.01:02:03.81#ibcon#end of sib2, iclass 21, count 0 2006.174.01:02:03.81#ibcon#*mode == 0, iclass 21, count 0 2006.174.01:02:03.81#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.174.01:02:03.81#ibcon#[28=FRQ=04,679.99\r\n] 2006.174.01:02:03.81#ibcon#*before write, iclass 21, count 0 2006.174.01:02:03.81#ibcon#enter sib2, iclass 21, count 0 2006.174.01:02:03.81#ibcon#flushed, iclass 21, count 0 2006.174.01:02:03.81#ibcon#about to write, iclass 21, count 0 2006.174.01:02:03.81#ibcon#wrote, iclass 21, count 0 2006.174.01:02:03.81#ibcon#about to read 3, iclass 21, count 0 2006.174.01:02:03.85#ibcon#read 3, iclass 21, count 0 2006.174.01:02:03.85#ibcon#about to read 4, iclass 21, count 0 2006.174.01:02:03.85#ibcon#read 4, iclass 21, count 0 2006.174.01:02:03.85#ibcon#about to read 5, iclass 21, count 0 2006.174.01:02:03.85#ibcon#read 5, iclass 21, count 0 2006.174.01:02:03.85#ibcon#about to read 6, iclass 21, count 0 2006.174.01:02:03.85#ibcon#read 6, iclass 21, count 0 2006.174.01:02:03.85#ibcon#end of sib2, iclass 21, count 0 2006.174.01:02:03.85#ibcon#*after write, iclass 21, count 0 2006.174.01:02:03.85#ibcon#*before return 0, iclass 21, count 0 2006.174.01:02:03.85#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.174.01:02:03.85#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.174.01:02:03.85#ibcon#about to clear, iclass 21 cls_cnt 0 2006.174.01:02:03.85#ibcon#cleared, iclass 21 cls_cnt 0 2006.174.01:02:03.85$vck44/vb=4,4 2006.174.01:02:03.85#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.174.01:02:03.85#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.174.01:02:03.85#ibcon#ireg 11 cls_cnt 2 2006.174.01:02:03.85#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.174.01:02:03.91#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.174.01:02:03.91#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.174.01:02:03.91#ibcon#enter wrdev, iclass 23, count 2 2006.174.01:02:03.91#ibcon#first serial, iclass 23, count 2 2006.174.01:02:03.91#ibcon#enter sib2, iclass 23, count 2 2006.174.01:02:03.91#ibcon#flushed, iclass 23, count 2 2006.174.01:02:03.91#ibcon#about to write, iclass 23, count 2 2006.174.01:02:03.91#ibcon#wrote, iclass 23, count 2 2006.174.01:02:03.91#ibcon#about to read 3, iclass 23, count 2 2006.174.01:02:03.93#ibcon#read 3, iclass 23, count 2 2006.174.01:02:03.93#ibcon#about to read 4, iclass 23, count 2 2006.174.01:02:03.93#ibcon#read 4, iclass 23, count 2 2006.174.01:02:03.93#ibcon#about to read 5, iclass 23, count 2 2006.174.01:02:03.93#ibcon#read 5, iclass 23, count 2 2006.174.01:02:03.93#ibcon#about to read 6, iclass 23, count 2 2006.174.01:02:03.93#ibcon#read 6, iclass 23, count 2 2006.174.01:02:03.93#ibcon#end of sib2, iclass 23, count 2 2006.174.01:02:03.93#ibcon#*mode == 0, iclass 23, count 2 2006.174.01:02:03.93#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.174.01:02:03.93#ibcon#[27=AT04-04\r\n] 2006.174.01:02:03.93#ibcon#*before write, iclass 23, count 2 2006.174.01:02:03.93#ibcon#enter sib2, iclass 23, count 2 2006.174.01:02:03.93#ibcon#flushed, iclass 23, count 2 2006.174.01:02:03.93#ibcon#about to write, iclass 23, count 2 2006.174.01:02:03.93#ibcon#wrote, iclass 23, count 2 2006.174.01:02:03.93#ibcon#about to read 3, iclass 23, count 2 2006.174.01:02:03.96#ibcon#read 3, iclass 23, count 2 2006.174.01:02:03.96#ibcon#about to read 4, iclass 23, count 2 2006.174.01:02:03.96#ibcon#read 4, iclass 23, count 2 2006.174.01:02:03.96#ibcon#about to read 5, iclass 23, count 2 2006.174.01:02:03.96#ibcon#read 5, iclass 23, count 2 2006.174.01:02:03.96#ibcon#about to read 6, iclass 23, count 2 2006.174.01:02:03.96#ibcon#read 6, iclass 23, count 2 2006.174.01:02:03.96#ibcon#end of sib2, iclass 23, count 2 2006.174.01:02:03.96#ibcon#*after write, iclass 23, count 2 2006.174.01:02:03.96#ibcon#*before return 0, iclass 23, count 2 2006.174.01:02:03.96#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.174.01:02:03.96#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.174.01:02:03.96#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.174.01:02:03.96#ibcon#ireg 7 cls_cnt 0 2006.174.01:02:03.96#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.174.01:02:04.08#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.174.01:02:04.08#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.174.01:02:04.08#ibcon#enter wrdev, iclass 23, count 0 2006.174.01:02:04.08#ibcon#first serial, iclass 23, count 0 2006.174.01:02:04.08#ibcon#enter sib2, iclass 23, count 0 2006.174.01:02:04.08#ibcon#flushed, iclass 23, count 0 2006.174.01:02:04.08#ibcon#about to write, iclass 23, count 0 2006.174.01:02:04.08#ibcon#wrote, iclass 23, count 0 2006.174.01:02:04.08#ibcon#about to read 3, iclass 23, count 0 2006.174.01:02:04.10#ibcon#read 3, iclass 23, count 0 2006.174.01:02:04.10#ibcon#about to read 4, iclass 23, count 0 2006.174.01:02:04.10#ibcon#read 4, iclass 23, count 0 2006.174.01:02:04.10#ibcon#about to read 5, iclass 23, count 0 2006.174.01:02:04.10#ibcon#read 5, iclass 23, count 0 2006.174.01:02:04.10#ibcon#about to read 6, iclass 23, count 0 2006.174.01:02:04.10#ibcon#read 6, iclass 23, count 0 2006.174.01:02:04.10#ibcon#end of sib2, iclass 23, count 0 2006.174.01:02:04.10#ibcon#*mode == 0, iclass 23, count 0 2006.174.01:02:04.10#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.174.01:02:04.10#ibcon#[27=USB\r\n] 2006.174.01:02:04.10#ibcon#*before write, iclass 23, count 0 2006.174.01:02:04.10#ibcon#enter sib2, iclass 23, count 0 2006.174.01:02:04.10#ibcon#flushed, iclass 23, count 0 2006.174.01:02:04.10#ibcon#about to write, iclass 23, count 0 2006.174.01:02:04.10#ibcon#wrote, iclass 23, count 0 2006.174.01:02:04.10#ibcon#about to read 3, iclass 23, count 0 2006.174.01:02:04.13#ibcon#read 3, iclass 23, count 0 2006.174.01:02:04.13#ibcon#about to read 4, iclass 23, count 0 2006.174.01:02:04.13#ibcon#read 4, iclass 23, count 0 2006.174.01:02:04.13#ibcon#about to read 5, iclass 23, count 0 2006.174.01:02:04.13#ibcon#read 5, iclass 23, count 0 2006.174.01:02:04.13#ibcon#about to read 6, iclass 23, count 0 2006.174.01:02:04.13#ibcon#read 6, iclass 23, count 0 2006.174.01:02:04.13#ibcon#end of sib2, iclass 23, count 0 2006.174.01:02:04.13#ibcon#*after write, iclass 23, count 0 2006.174.01:02:04.13#ibcon#*before return 0, iclass 23, count 0 2006.174.01:02:04.13#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.174.01:02:04.13#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.174.01:02:04.13#ibcon#about to clear, iclass 23 cls_cnt 0 2006.174.01:02:04.13#ibcon#cleared, iclass 23 cls_cnt 0 2006.174.01:02:04.13$vck44/vblo=5,709.99 2006.174.01:02:04.13#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.174.01:02:04.13#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.174.01:02:04.13#ibcon#ireg 17 cls_cnt 0 2006.174.01:02:04.13#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.174.01:02:04.13#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.174.01:02:04.13#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.174.01:02:04.13#ibcon#enter wrdev, iclass 25, count 0 2006.174.01:02:04.13#ibcon#first serial, iclass 25, count 0 2006.174.01:02:04.13#ibcon#enter sib2, iclass 25, count 0 2006.174.01:02:04.13#ibcon#flushed, iclass 25, count 0 2006.174.01:02:04.13#ibcon#about to write, iclass 25, count 0 2006.174.01:02:04.13#ibcon#wrote, iclass 25, count 0 2006.174.01:02:04.13#ibcon#about to read 3, iclass 25, count 0 2006.174.01:02:04.15#ibcon#read 3, iclass 25, count 0 2006.174.01:02:04.15#ibcon#about to read 4, iclass 25, count 0 2006.174.01:02:04.15#ibcon#read 4, iclass 25, count 0 2006.174.01:02:04.15#ibcon#about to read 5, iclass 25, count 0 2006.174.01:02:04.15#ibcon#read 5, iclass 25, count 0 2006.174.01:02:04.15#ibcon#about to read 6, iclass 25, count 0 2006.174.01:02:04.15#ibcon#read 6, iclass 25, count 0 2006.174.01:02:04.15#ibcon#end of sib2, iclass 25, count 0 2006.174.01:02:04.15#ibcon#*mode == 0, iclass 25, count 0 2006.174.01:02:04.15#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.174.01:02:04.15#ibcon#[28=FRQ=05,709.99\r\n] 2006.174.01:02:04.15#ibcon#*before write, iclass 25, count 0 2006.174.01:02:04.15#ibcon#enter sib2, iclass 25, count 0 2006.174.01:02:04.15#ibcon#flushed, iclass 25, count 0 2006.174.01:02:04.15#ibcon#about to write, iclass 25, count 0 2006.174.01:02:04.15#ibcon#wrote, iclass 25, count 0 2006.174.01:02:04.15#ibcon#about to read 3, iclass 25, count 0 2006.174.01:02:04.19#ibcon#read 3, iclass 25, count 0 2006.174.01:02:04.19#ibcon#about to read 4, iclass 25, count 0 2006.174.01:02:04.19#ibcon#read 4, iclass 25, count 0 2006.174.01:02:04.19#ibcon#about to read 5, iclass 25, count 0 2006.174.01:02:04.19#ibcon#read 5, iclass 25, count 0 2006.174.01:02:04.19#ibcon#about to read 6, iclass 25, count 0 2006.174.01:02:04.19#ibcon#read 6, iclass 25, count 0 2006.174.01:02:04.19#ibcon#end of sib2, iclass 25, count 0 2006.174.01:02:04.19#ibcon#*after write, iclass 25, count 0 2006.174.01:02:04.19#ibcon#*before return 0, iclass 25, count 0 2006.174.01:02:04.19#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.174.01:02:04.19#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.174.01:02:04.19#ibcon#about to clear, iclass 25 cls_cnt 0 2006.174.01:02:04.19#ibcon#cleared, iclass 25 cls_cnt 0 2006.174.01:02:04.19$vck44/vb=5,4 2006.174.01:02:04.19#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.174.01:02:04.19#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.174.01:02:04.19#ibcon#ireg 11 cls_cnt 2 2006.174.01:02:04.19#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.174.01:02:04.25#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.174.01:02:04.25#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.174.01:02:04.25#ibcon#enter wrdev, iclass 27, count 2 2006.174.01:02:04.25#ibcon#first serial, iclass 27, count 2 2006.174.01:02:04.25#ibcon#enter sib2, iclass 27, count 2 2006.174.01:02:04.25#ibcon#flushed, iclass 27, count 2 2006.174.01:02:04.25#ibcon#about to write, iclass 27, count 2 2006.174.01:02:04.25#ibcon#wrote, iclass 27, count 2 2006.174.01:02:04.25#ibcon#about to read 3, iclass 27, count 2 2006.174.01:02:04.27#ibcon#read 3, iclass 27, count 2 2006.174.01:02:04.27#ibcon#about to read 4, iclass 27, count 2 2006.174.01:02:04.27#ibcon#read 4, iclass 27, count 2 2006.174.01:02:04.27#ibcon#about to read 5, iclass 27, count 2 2006.174.01:02:04.27#ibcon#read 5, iclass 27, count 2 2006.174.01:02:04.27#ibcon#about to read 6, iclass 27, count 2 2006.174.01:02:04.27#ibcon#read 6, iclass 27, count 2 2006.174.01:02:04.27#ibcon#end of sib2, iclass 27, count 2 2006.174.01:02:04.27#ibcon#*mode == 0, iclass 27, count 2 2006.174.01:02:04.27#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.174.01:02:04.27#ibcon#[27=AT05-04\r\n] 2006.174.01:02:04.27#ibcon#*before write, iclass 27, count 2 2006.174.01:02:04.27#ibcon#enter sib2, iclass 27, count 2 2006.174.01:02:04.27#ibcon#flushed, iclass 27, count 2 2006.174.01:02:04.27#ibcon#about to write, iclass 27, count 2 2006.174.01:02:04.27#ibcon#wrote, iclass 27, count 2 2006.174.01:02:04.27#ibcon#about to read 3, iclass 27, count 2 2006.174.01:02:04.30#ibcon#read 3, iclass 27, count 2 2006.174.01:02:04.30#ibcon#about to read 4, iclass 27, count 2 2006.174.01:02:04.30#ibcon#read 4, iclass 27, count 2 2006.174.01:02:04.30#ibcon#about to read 5, iclass 27, count 2 2006.174.01:02:04.30#ibcon#read 5, iclass 27, count 2 2006.174.01:02:04.30#ibcon#about to read 6, iclass 27, count 2 2006.174.01:02:04.30#ibcon#read 6, iclass 27, count 2 2006.174.01:02:04.30#ibcon#end of sib2, iclass 27, count 2 2006.174.01:02:04.30#ibcon#*after write, iclass 27, count 2 2006.174.01:02:04.30#ibcon#*before return 0, iclass 27, count 2 2006.174.01:02:04.30#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.174.01:02:04.30#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.174.01:02:04.30#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.174.01:02:04.30#ibcon#ireg 7 cls_cnt 0 2006.174.01:02:04.30#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.174.01:02:04.42#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.174.01:02:04.42#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.174.01:02:04.42#ibcon#enter wrdev, iclass 27, count 0 2006.174.01:02:04.42#ibcon#first serial, iclass 27, count 0 2006.174.01:02:04.42#ibcon#enter sib2, iclass 27, count 0 2006.174.01:02:04.42#ibcon#flushed, iclass 27, count 0 2006.174.01:02:04.42#ibcon#about to write, iclass 27, count 0 2006.174.01:02:04.42#ibcon#wrote, iclass 27, count 0 2006.174.01:02:04.42#ibcon#about to read 3, iclass 27, count 0 2006.174.01:02:04.44#ibcon#read 3, iclass 27, count 0 2006.174.01:02:04.44#ibcon#about to read 4, iclass 27, count 0 2006.174.01:02:04.44#ibcon#read 4, iclass 27, count 0 2006.174.01:02:04.44#ibcon#about to read 5, iclass 27, count 0 2006.174.01:02:04.44#ibcon#read 5, iclass 27, count 0 2006.174.01:02:04.44#ibcon#about to read 6, iclass 27, count 0 2006.174.01:02:04.44#ibcon#read 6, iclass 27, count 0 2006.174.01:02:04.44#ibcon#end of sib2, iclass 27, count 0 2006.174.01:02:04.44#ibcon#*mode == 0, iclass 27, count 0 2006.174.01:02:04.44#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.174.01:02:04.44#ibcon#[27=USB\r\n] 2006.174.01:02:04.44#ibcon#*before write, iclass 27, count 0 2006.174.01:02:04.44#ibcon#enter sib2, iclass 27, count 0 2006.174.01:02:04.44#ibcon#flushed, iclass 27, count 0 2006.174.01:02:04.44#ibcon#about to write, iclass 27, count 0 2006.174.01:02:04.44#ibcon#wrote, iclass 27, count 0 2006.174.01:02:04.44#ibcon#about to read 3, iclass 27, count 0 2006.174.01:02:04.47#ibcon#read 3, iclass 27, count 0 2006.174.01:02:04.47#ibcon#about to read 4, iclass 27, count 0 2006.174.01:02:04.47#ibcon#read 4, iclass 27, count 0 2006.174.01:02:04.47#ibcon#about to read 5, iclass 27, count 0 2006.174.01:02:04.47#ibcon#read 5, iclass 27, count 0 2006.174.01:02:04.47#ibcon#about to read 6, iclass 27, count 0 2006.174.01:02:04.47#ibcon#read 6, iclass 27, count 0 2006.174.01:02:04.47#ibcon#end of sib2, iclass 27, count 0 2006.174.01:02:04.47#ibcon#*after write, iclass 27, count 0 2006.174.01:02:04.47#ibcon#*before return 0, iclass 27, count 0 2006.174.01:02:04.47#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.174.01:02:04.47#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.174.01:02:04.47#ibcon#about to clear, iclass 27 cls_cnt 0 2006.174.01:02:04.47#ibcon#cleared, iclass 27 cls_cnt 0 2006.174.01:02:04.47$vck44/vblo=6,719.99 2006.174.01:02:04.47#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.174.01:02:04.47#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.174.01:02:04.47#ibcon#ireg 17 cls_cnt 0 2006.174.01:02:04.47#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.174.01:02:04.47#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.174.01:02:04.47#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.174.01:02:04.47#ibcon#enter wrdev, iclass 29, count 0 2006.174.01:02:04.47#ibcon#first serial, iclass 29, count 0 2006.174.01:02:04.47#ibcon#enter sib2, iclass 29, count 0 2006.174.01:02:04.47#ibcon#flushed, iclass 29, count 0 2006.174.01:02:04.47#ibcon#about to write, iclass 29, count 0 2006.174.01:02:04.47#ibcon#wrote, iclass 29, count 0 2006.174.01:02:04.47#ibcon#about to read 3, iclass 29, count 0 2006.174.01:02:04.49#ibcon#read 3, iclass 29, count 0 2006.174.01:02:04.49#ibcon#about to read 4, iclass 29, count 0 2006.174.01:02:04.49#ibcon#read 4, iclass 29, count 0 2006.174.01:02:04.49#ibcon#about to read 5, iclass 29, count 0 2006.174.01:02:04.49#ibcon#read 5, iclass 29, count 0 2006.174.01:02:04.49#ibcon#about to read 6, iclass 29, count 0 2006.174.01:02:04.49#ibcon#read 6, iclass 29, count 0 2006.174.01:02:04.49#ibcon#end of sib2, iclass 29, count 0 2006.174.01:02:04.49#ibcon#*mode == 0, iclass 29, count 0 2006.174.01:02:04.49#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.174.01:02:04.49#ibcon#[28=FRQ=06,719.99\r\n] 2006.174.01:02:04.49#ibcon#*before write, iclass 29, count 0 2006.174.01:02:04.49#ibcon#enter sib2, iclass 29, count 0 2006.174.01:02:04.49#ibcon#flushed, iclass 29, count 0 2006.174.01:02:04.49#ibcon#about to write, iclass 29, count 0 2006.174.01:02:04.49#ibcon#wrote, iclass 29, count 0 2006.174.01:02:04.49#ibcon#about to read 3, iclass 29, count 0 2006.174.01:02:04.53#ibcon#read 3, iclass 29, count 0 2006.174.01:02:04.53#ibcon#about to read 4, iclass 29, count 0 2006.174.01:02:04.53#ibcon#read 4, iclass 29, count 0 2006.174.01:02:04.53#ibcon#about to read 5, iclass 29, count 0 2006.174.01:02:04.53#ibcon#read 5, iclass 29, count 0 2006.174.01:02:04.53#ibcon#about to read 6, iclass 29, count 0 2006.174.01:02:04.53#ibcon#read 6, iclass 29, count 0 2006.174.01:02:04.53#ibcon#end of sib2, iclass 29, count 0 2006.174.01:02:04.53#ibcon#*after write, iclass 29, count 0 2006.174.01:02:04.53#ibcon#*before return 0, iclass 29, count 0 2006.174.01:02:04.53#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.174.01:02:04.53#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.174.01:02:04.53#ibcon#about to clear, iclass 29 cls_cnt 0 2006.174.01:02:04.53#ibcon#cleared, iclass 29 cls_cnt 0 2006.174.01:02:04.53$vck44/vb=6,4 2006.174.01:02:04.53#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.174.01:02:04.53#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.174.01:02:04.53#ibcon#ireg 11 cls_cnt 2 2006.174.01:02:04.53#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.174.01:02:04.59#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.174.01:02:04.59#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.174.01:02:04.59#ibcon#enter wrdev, iclass 31, count 2 2006.174.01:02:04.59#ibcon#first serial, iclass 31, count 2 2006.174.01:02:04.59#ibcon#enter sib2, iclass 31, count 2 2006.174.01:02:04.59#ibcon#flushed, iclass 31, count 2 2006.174.01:02:04.59#ibcon#about to write, iclass 31, count 2 2006.174.01:02:04.59#ibcon#wrote, iclass 31, count 2 2006.174.01:02:04.59#ibcon#about to read 3, iclass 31, count 2 2006.174.01:02:04.61#ibcon#read 3, iclass 31, count 2 2006.174.01:02:04.61#ibcon#about to read 4, iclass 31, count 2 2006.174.01:02:04.61#ibcon#read 4, iclass 31, count 2 2006.174.01:02:04.61#ibcon#about to read 5, iclass 31, count 2 2006.174.01:02:04.61#ibcon#read 5, iclass 31, count 2 2006.174.01:02:04.61#ibcon#about to read 6, iclass 31, count 2 2006.174.01:02:04.61#ibcon#read 6, iclass 31, count 2 2006.174.01:02:04.61#ibcon#end of sib2, iclass 31, count 2 2006.174.01:02:04.61#ibcon#*mode == 0, iclass 31, count 2 2006.174.01:02:04.61#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.174.01:02:04.61#ibcon#[27=AT06-04\r\n] 2006.174.01:02:04.61#ibcon#*before write, iclass 31, count 2 2006.174.01:02:04.61#ibcon#enter sib2, iclass 31, count 2 2006.174.01:02:04.61#ibcon#flushed, iclass 31, count 2 2006.174.01:02:04.61#ibcon#about to write, iclass 31, count 2 2006.174.01:02:04.61#ibcon#wrote, iclass 31, count 2 2006.174.01:02:04.61#ibcon#about to read 3, iclass 31, count 2 2006.174.01:02:04.64#ibcon#read 3, iclass 31, count 2 2006.174.01:02:04.64#ibcon#about to read 4, iclass 31, count 2 2006.174.01:02:04.64#ibcon#read 4, iclass 31, count 2 2006.174.01:02:04.64#ibcon#about to read 5, iclass 31, count 2 2006.174.01:02:04.64#ibcon#read 5, iclass 31, count 2 2006.174.01:02:04.64#ibcon#about to read 6, iclass 31, count 2 2006.174.01:02:04.64#ibcon#read 6, iclass 31, count 2 2006.174.01:02:04.64#ibcon#end of sib2, iclass 31, count 2 2006.174.01:02:04.64#ibcon#*after write, iclass 31, count 2 2006.174.01:02:04.64#ibcon#*before return 0, iclass 31, count 2 2006.174.01:02:04.64#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.174.01:02:04.64#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.174.01:02:04.64#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.174.01:02:04.64#ibcon#ireg 7 cls_cnt 0 2006.174.01:02:04.64#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.174.01:02:04.76#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.174.01:02:04.76#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.174.01:02:04.76#ibcon#enter wrdev, iclass 31, count 0 2006.174.01:02:04.76#ibcon#first serial, iclass 31, count 0 2006.174.01:02:04.76#ibcon#enter sib2, iclass 31, count 0 2006.174.01:02:04.76#ibcon#flushed, iclass 31, count 0 2006.174.01:02:04.76#ibcon#about to write, iclass 31, count 0 2006.174.01:02:04.76#ibcon#wrote, iclass 31, count 0 2006.174.01:02:04.76#ibcon#about to read 3, iclass 31, count 0 2006.174.01:02:04.78#ibcon#read 3, iclass 31, count 0 2006.174.01:02:04.78#ibcon#about to read 4, iclass 31, count 0 2006.174.01:02:04.78#ibcon#read 4, iclass 31, count 0 2006.174.01:02:04.78#ibcon#about to read 5, iclass 31, count 0 2006.174.01:02:04.78#ibcon#read 5, iclass 31, count 0 2006.174.01:02:04.78#ibcon#about to read 6, iclass 31, count 0 2006.174.01:02:04.78#ibcon#read 6, iclass 31, count 0 2006.174.01:02:04.78#ibcon#end of sib2, iclass 31, count 0 2006.174.01:02:04.78#ibcon#*mode == 0, iclass 31, count 0 2006.174.01:02:04.78#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.174.01:02:04.78#ibcon#[27=USB\r\n] 2006.174.01:02:04.78#ibcon#*before write, iclass 31, count 0 2006.174.01:02:04.78#ibcon#enter sib2, iclass 31, count 0 2006.174.01:02:04.78#ibcon#flushed, iclass 31, count 0 2006.174.01:02:04.78#ibcon#about to write, iclass 31, count 0 2006.174.01:02:04.78#ibcon#wrote, iclass 31, count 0 2006.174.01:02:04.78#ibcon#about to read 3, iclass 31, count 0 2006.174.01:02:04.81#ibcon#read 3, iclass 31, count 0 2006.174.01:02:04.81#ibcon#about to read 4, iclass 31, count 0 2006.174.01:02:04.81#ibcon#read 4, iclass 31, count 0 2006.174.01:02:04.81#ibcon#about to read 5, iclass 31, count 0 2006.174.01:02:04.81#ibcon#read 5, iclass 31, count 0 2006.174.01:02:04.81#ibcon#about to read 6, iclass 31, count 0 2006.174.01:02:04.81#ibcon#read 6, iclass 31, count 0 2006.174.01:02:04.81#ibcon#end of sib2, iclass 31, count 0 2006.174.01:02:04.81#ibcon#*after write, iclass 31, count 0 2006.174.01:02:04.81#ibcon#*before return 0, iclass 31, count 0 2006.174.01:02:04.81#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.174.01:02:04.81#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.174.01:02:04.81#ibcon#about to clear, iclass 31 cls_cnt 0 2006.174.01:02:04.81#ibcon#cleared, iclass 31 cls_cnt 0 2006.174.01:02:04.81$vck44/vblo=7,734.99 2006.174.01:02:04.81#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.174.01:02:04.81#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.174.01:02:04.81#ibcon#ireg 17 cls_cnt 0 2006.174.01:02:04.81#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.174.01:02:04.81#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.174.01:02:04.81#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.174.01:02:04.81#ibcon#enter wrdev, iclass 33, count 0 2006.174.01:02:04.81#ibcon#first serial, iclass 33, count 0 2006.174.01:02:04.81#ibcon#enter sib2, iclass 33, count 0 2006.174.01:02:04.81#ibcon#flushed, iclass 33, count 0 2006.174.01:02:04.81#ibcon#about to write, iclass 33, count 0 2006.174.01:02:04.81#ibcon#wrote, iclass 33, count 0 2006.174.01:02:04.81#ibcon#about to read 3, iclass 33, count 0 2006.174.01:02:04.83#ibcon#read 3, iclass 33, count 0 2006.174.01:02:04.83#ibcon#about to read 4, iclass 33, count 0 2006.174.01:02:04.83#ibcon#read 4, iclass 33, count 0 2006.174.01:02:04.83#ibcon#about to read 5, iclass 33, count 0 2006.174.01:02:04.83#ibcon#read 5, iclass 33, count 0 2006.174.01:02:04.83#ibcon#about to read 6, iclass 33, count 0 2006.174.01:02:04.83#ibcon#read 6, iclass 33, count 0 2006.174.01:02:04.83#ibcon#end of sib2, iclass 33, count 0 2006.174.01:02:04.83#ibcon#*mode == 0, iclass 33, count 0 2006.174.01:02:04.83#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.174.01:02:04.83#ibcon#[28=FRQ=07,734.99\r\n] 2006.174.01:02:04.83#ibcon#*before write, iclass 33, count 0 2006.174.01:02:04.83#ibcon#enter sib2, iclass 33, count 0 2006.174.01:02:04.83#ibcon#flushed, iclass 33, count 0 2006.174.01:02:04.83#ibcon#about to write, iclass 33, count 0 2006.174.01:02:04.83#ibcon#wrote, iclass 33, count 0 2006.174.01:02:04.83#ibcon#about to read 3, iclass 33, count 0 2006.174.01:02:04.87#ibcon#read 3, iclass 33, count 0 2006.174.01:02:04.87#ibcon#about to read 4, iclass 33, count 0 2006.174.01:02:04.87#ibcon#read 4, iclass 33, count 0 2006.174.01:02:04.87#ibcon#about to read 5, iclass 33, count 0 2006.174.01:02:04.87#ibcon#read 5, iclass 33, count 0 2006.174.01:02:04.87#ibcon#about to read 6, iclass 33, count 0 2006.174.01:02:04.87#ibcon#read 6, iclass 33, count 0 2006.174.01:02:04.87#ibcon#end of sib2, iclass 33, count 0 2006.174.01:02:04.87#ibcon#*after write, iclass 33, count 0 2006.174.01:02:04.87#ibcon#*before return 0, iclass 33, count 0 2006.174.01:02:04.87#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.174.01:02:04.87#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.174.01:02:04.87#ibcon#about to clear, iclass 33 cls_cnt 0 2006.174.01:02:04.87#ibcon#cleared, iclass 33 cls_cnt 0 2006.174.01:02:04.87$vck44/vb=7,4 2006.174.01:02:04.87#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.174.01:02:04.87#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.174.01:02:04.87#ibcon#ireg 11 cls_cnt 2 2006.174.01:02:04.87#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.174.01:02:04.93#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.174.01:02:04.93#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.174.01:02:04.93#ibcon#enter wrdev, iclass 35, count 2 2006.174.01:02:04.93#ibcon#first serial, iclass 35, count 2 2006.174.01:02:04.93#ibcon#enter sib2, iclass 35, count 2 2006.174.01:02:04.93#ibcon#flushed, iclass 35, count 2 2006.174.01:02:04.93#ibcon#about to write, iclass 35, count 2 2006.174.01:02:04.93#ibcon#wrote, iclass 35, count 2 2006.174.01:02:04.93#ibcon#about to read 3, iclass 35, count 2 2006.174.01:02:04.95#ibcon#read 3, iclass 35, count 2 2006.174.01:02:04.95#ibcon#about to read 4, iclass 35, count 2 2006.174.01:02:04.95#ibcon#read 4, iclass 35, count 2 2006.174.01:02:04.95#ibcon#about to read 5, iclass 35, count 2 2006.174.01:02:04.95#ibcon#read 5, iclass 35, count 2 2006.174.01:02:04.95#ibcon#about to read 6, iclass 35, count 2 2006.174.01:02:04.95#ibcon#read 6, iclass 35, count 2 2006.174.01:02:04.95#ibcon#end of sib2, iclass 35, count 2 2006.174.01:02:04.95#ibcon#*mode == 0, iclass 35, count 2 2006.174.01:02:04.95#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.174.01:02:04.95#ibcon#[27=AT07-04\r\n] 2006.174.01:02:04.95#ibcon#*before write, iclass 35, count 2 2006.174.01:02:04.95#ibcon#enter sib2, iclass 35, count 2 2006.174.01:02:04.95#ibcon#flushed, iclass 35, count 2 2006.174.01:02:04.95#ibcon#about to write, iclass 35, count 2 2006.174.01:02:04.95#ibcon#wrote, iclass 35, count 2 2006.174.01:02:04.95#ibcon#about to read 3, iclass 35, count 2 2006.174.01:02:04.98#ibcon#read 3, iclass 35, count 2 2006.174.01:02:04.98#ibcon#about to read 4, iclass 35, count 2 2006.174.01:02:04.98#ibcon#read 4, iclass 35, count 2 2006.174.01:02:04.98#ibcon#about to read 5, iclass 35, count 2 2006.174.01:02:04.98#ibcon#read 5, iclass 35, count 2 2006.174.01:02:04.98#ibcon#about to read 6, iclass 35, count 2 2006.174.01:02:04.98#ibcon#read 6, iclass 35, count 2 2006.174.01:02:04.98#ibcon#end of sib2, iclass 35, count 2 2006.174.01:02:04.98#ibcon#*after write, iclass 35, count 2 2006.174.01:02:04.98#ibcon#*before return 0, iclass 35, count 2 2006.174.01:02:04.98#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.174.01:02:04.98#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.174.01:02:04.98#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.174.01:02:04.98#ibcon#ireg 7 cls_cnt 0 2006.174.01:02:04.98#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.174.01:02:05.10#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.174.01:02:05.10#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.174.01:02:05.10#ibcon#enter wrdev, iclass 35, count 0 2006.174.01:02:05.10#ibcon#first serial, iclass 35, count 0 2006.174.01:02:05.10#ibcon#enter sib2, iclass 35, count 0 2006.174.01:02:05.10#ibcon#flushed, iclass 35, count 0 2006.174.01:02:05.10#ibcon#about to write, iclass 35, count 0 2006.174.01:02:05.10#ibcon#wrote, iclass 35, count 0 2006.174.01:02:05.10#ibcon#about to read 3, iclass 35, count 0 2006.174.01:02:05.12#ibcon#read 3, iclass 35, count 0 2006.174.01:02:05.12#ibcon#about to read 4, iclass 35, count 0 2006.174.01:02:05.12#ibcon#read 4, iclass 35, count 0 2006.174.01:02:05.12#ibcon#about to read 5, iclass 35, count 0 2006.174.01:02:05.12#ibcon#read 5, iclass 35, count 0 2006.174.01:02:05.12#ibcon#about to read 6, iclass 35, count 0 2006.174.01:02:05.12#ibcon#read 6, iclass 35, count 0 2006.174.01:02:05.12#ibcon#end of sib2, iclass 35, count 0 2006.174.01:02:05.12#ibcon#*mode == 0, iclass 35, count 0 2006.174.01:02:05.12#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.174.01:02:05.12#ibcon#[27=USB\r\n] 2006.174.01:02:05.12#ibcon#*before write, iclass 35, count 0 2006.174.01:02:05.12#ibcon#enter sib2, iclass 35, count 0 2006.174.01:02:05.12#ibcon#flushed, iclass 35, count 0 2006.174.01:02:05.12#ibcon#about to write, iclass 35, count 0 2006.174.01:02:05.12#ibcon#wrote, iclass 35, count 0 2006.174.01:02:05.12#ibcon#about to read 3, iclass 35, count 0 2006.174.01:02:05.15#ibcon#read 3, iclass 35, count 0 2006.174.01:02:05.15#ibcon#about to read 4, iclass 35, count 0 2006.174.01:02:05.15#ibcon#read 4, iclass 35, count 0 2006.174.01:02:05.15#ibcon#about to read 5, iclass 35, count 0 2006.174.01:02:05.15#ibcon#read 5, iclass 35, count 0 2006.174.01:02:05.15#ibcon#about to read 6, iclass 35, count 0 2006.174.01:02:05.15#ibcon#read 6, iclass 35, count 0 2006.174.01:02:05.15#ibcon#end of sib2, iclass 35, count 0 2006.174.01:02:05.15#ibcon#*after write, iclass 35, count 0 2006.174.01:02:05.15#ibcon#*before return 0, iclass 35, count 0 2006.174.01:02:05.15#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.174.01:02:05.15#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.174.01:02:05.15#ibcon#about to clear, iclass 35 cls_cnt 0 2006.174.01:02:05.15#ibcon#cleared, iclass 35 cls_cnt 0 2006.174.01:02:05.15$vck44/vblo=8,744.99 2006.174.01:02:05.15#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.174.01:02:05.15#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.174.01:02:05.15#ibcon#ireg 17 cls_cnt 0 2006.174.01:02:05.15#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.174.01:02:05.15#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.174.01:02:05.15#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.174.01:02:05.15#ibcon#enter wrdev, iclass 37, count 0 2006.174.01:02:05.15#ibcon#first serial, iclass 37, count 0 2006.174.01:02:05.15#ibcon#enter sib2, iclass 37, count 0 2006.174.01:02:05.15#ibcon#flushed, iclass 37, count 0 2006.174.01:02:05.15#ibcon#about to write, iclass 37, count 0 2006.174.01:02:05.15#ibcon#wrote, iclass 37, count 0 2006.174.01:02:05.15#ibcon#about to read 3, iclass 37, count 0 2006.174.01:02:05.17#ibcon#read 3, iclass 37, count 0 2006.174.01:02:05.17#ibcon#about to read 4, iclass 37, count 0 2006.174.01:02:05.17#ibcon#read 4, iclass 37, count 0 2006.174.01:02:05.17#ibcon#about to read 5, iclass 37, count 0 2006.174.01:02:05.17#ibcon#read 5, iclass 37, count 0 2006.174.01:02:05.17#ibcon#about to read 6, iclass 37, count 0 2006.174.01:02:05.17#ibcon#read 6, iclass 37, count 0 2006.174.01:02:05.17#ibcon#end of sib2, iclass 37, count 0 2006.174.01:02:05.17#ibcon#*mode == 0, iclass 37, count 0 2006.174.01:02:05.17#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.174.01:02:05.17#ibcon#[28=FRQ=08,744.99\r\n] 2006.174.01:02:05.17#ibcon#*before write, iclass 37, count 0 2006.174.01:02:05.17#ibcon#enter sib2, iclass 37, count 0 2006.174.01:02:05.17#ibcon#flushed, iclass 37, count 0 2006.174.01:02:05.17#ibcon#about to write, iclass 37, count 0 2006.174.01:02:05.17#ibcon#wrote, iclass 37, count 0 2006.174.01:02:05.17#ibcon#about to read 3, iclass 37, count 0 2006.174.01:02:05.21#ibcon#read 3, iclass 37, count 0 2006.174.01:02:05.21#ibcon#about to read 4, iclass 37, count 0 2006.174.01:02:05.21#ibcon#read 4, iclass 37, count 0 2006.174.01:02:05.21#ibcon#about to read 5, iclass 37, count 0 2006.174.01:02:05.21#ibcon#read 5, iclass 37, count 0 2006.174.01:02:05.21#ibcon#about to read 6, iclass 37, count 0 2006.174.01:02:05.21#ibcon#read 6, iclass 37, count 0 2006.174.01:02:05.21#ibcon#end of sib2, iclass 37, count 0 2006.174.01:02:05.21#ibcon#*after write, iclass 37, count 0 2006.174.01:02:05.21#ibcon#*before return 0, iclass 37, count 0 2006.174.01:02:05.21#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.174.01:02:05.21#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.174.01:02:05.21#ibcon#about to clear, iclass 37 cls_cnt 0 2006.174.01:02:05.21#ibcon#cleared, iclass 37 cls_cnt 0 2006.174.01:02:05.21$vck44/vb=8,4 2006.174.01:02:05.21#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.174.01:02:05.21#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.174.01:02:05.21#ibcon#ireg 11 cls_cnt 2 2006.174.01:02:05.21#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.174.01:02:05.27#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.174.01:02:05.27#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.174.01:02:05.27#ibcon#enter wrdev, iclass 39, count 2 2006.174.01:02:05.27#ibcon#first serial, iclass 39, count 2 2006.174.01:02:05.27#ibcon#enter sib2, iclass 39, count 2 2006.174.01:02:05.27#ibcon#flushed, iclass 39, count 2 2006.174.01:02:05.27#ibcon#about to write, iclass 39, count 2 2006.174.01:02:05.27#ibcon#wrote, iclass 39, count 2 2006.174.01:02:05.27#ibcon#about to read 3, iclass 39, count 2 2006.174.01:02:05.29#ibcon#read 3, iclass 39, count 2 2006.174.01:02:05.29#ibcon#about to read 4, iclass 39, count 2 2006.174.01:02:05.29#ibcon#read 4, iclass 39, count 2 2006.174.01:02:05.29#ibcon#about to read 5, iclass 39, count 2 2006.174.01:02:05.29#ibcon#read 5, iclass 39, count 2 2006.174.01:02:05.29#ibcon#about to read 6, iclass 39, count 2 2006.174.01:02:05.29#ibcon#read 6, iclass 39, count 2 2006.174.01:02:05.29#ibcon#end of sib2, iclass 39, count 2 2006.174.01:02:05.29#ibcon#*mode == 0, iclass 39, count 2 2006.174.01:02:05.29#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.174.01:02:05.29#ibcon#[27=AT08-04\r\n] 2006.174.01:02:05.29#ibcon#*before write, iclass 39, count 2 2006.174.01:02:05.29#ibcon#enter sib2, iclass 39, count 2 2006.174.01:02:05.29#ibcon#flushed, iclass 39, count 2 2006.174.01:02:05.29#ibcon#about to write, iclass 39, count 2 2006.174.01:02:05.29#ibcon#wrote, iclass 39, count 2 2006.174.01:02:05.29#ibcon#about to read 3, iclass 39, count 2 2006.174.01:02:05.32#ibcon#read 3, iclass 39, count 2 2006.174.01:02:05.32#ibcon#about to read 4, iclass 39, count 2 2006.174.01:02:05.32#ibcon#read 4, iclass 39, count 2 2006.174.01:02:05.32#ibcon#about to read 5, iclass 39, count 2 2006.174.01:02:05.32#ibcon#read 5, iclass 39, count 2 2006.174.01:02:05.32#ibcon#about to read 6, iclass 39, count 2 2006.174.01:02:05.32#ibcon#read 6, iclass 39, count 2 2006.174.01:02:05.32#ibcon#end of sib2, iclass 39, count 2 2006.174.01:02:05.32#ibcon#*after write, iclass 39, count 2 2006.174.01:02:05.32#ibcon#*before return 0, iclass 39, count 2 2006.174.01:02:05.32#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.174.01:02:05.32#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.174.01:02:05.32#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.174.01:02:05.32#ibcon#ireg 7 cls_cnt 0 2006.174.01:02:05.32#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.174.01:02:05.44#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.174.01:02:05.44#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.174.01:02:05.44#ibcon#enter wrdev, iclass 39, count 0 2006.174.01:02:05.44#ibcon#first serial, iclass 39, count 0 2006.174.01:02:05.44#ibcon#enter sib2, iclass 39, count 0 2006.174.01:02:05.44#ibcon#flushed, iclass 39, count 0 2006.174.01:02:05.44#ibcon#about to write, iclass 39, count 0 2006.174.01:02:05.44#ibcon#wrote, iclass 39, count 0 2006.174.01:02:05.44#ibcon#about to read 3, iclass 39, count 0 2006.174.01:02:05.46#ibcon#read 3, iclass 39, count 0 2006.174.01:02:05.46#ibcon#about to read 4, iclass 39, count 0 2006.174.01:02:05.46#ibcon#read 4, iclass 39, count 0 2006.174.01:02:05.46#ibcon#about to read 5, iclass 39, count 0 2006.174.01:02:05.46#ibcon#read 5, iclass 39, count 0 2006.174.01:02:05.46#ibcon#about to read 6, iclass 39, count 0 2006.174.01:02:05.46#ibcon#read 6, iclass 39, count 0 2006.174.01:02:05.46#ibcon#end of sib2, iclass 39, count 0 2006.174.01:02:05.46#ibcon#*mode == 0, iclass 39, count 0 2006.174.01:02:05.46#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.174.01:02:05.46#ibcon#[27=USB\r\n] 2006.174.01:02:05.46#ibcon#*before write, iclass 39, count 0 2006.174.01:02:05.46#ibcon#enter sib2, iclass 39, count 0 2006.174.01:02:05.46#ibcon#flushed, iclass 39, count 0 2006.174.01:02:05.46#ibcon#about to write, iclass 39, count 0 2006.174.01:02:05.46#ibcon#wrote, iclass 39, count 0 2006.174.01:02:05.46#ibcon#about to read 3, iclass 39, count 0 2006.174.01:02:05.49#ibcon#read 3, iclass 39, count 0 2006.174.01:02:05.49#ibcon#about to read 4, iclass 39, count 0 2006.174.01:02:05.49#ibcon#read 4, iclass 39, count 0 2006.174.01:02:05.49#ibcon#about to read 5, iclass 39, count 0 2006.174.01:02:05.49#ibcon#read 5, iclass 39, count 0 2006.174.01:02:05.49#ibcon#about to read 6, iclass 39, count 0 2006.174.01:02:05.49#ibcon#read 6, iclass 39, count 0 2006.174.01:02:05.49#ibcon#end of sib2, iclass 39, count 0 2006.174.01:02:05.49#ibcon#*after write, iclass 39, count 0 2006.174.01:02:05.49#ibcon#*before return 0, iclass 39, count 0 2006.174.01:02:05.49#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.174.01:02:05.49#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.174.01:02:05.49#ibcon#about to clear, iclass 39 cls_cnt 0 2006.174.01:02:05.49#ibcon#cleared, iclass 39 cls_cnt 0 2006.174.01:02:05.49$vck44/vabw=wide 2006.174.01:02:05.49#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.174.01:02:05.49#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.174.01:02:05.49#ibcon#ireg 8 cls_cnt 0 2006.174.01:02:05.49#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.174.01:02:05.49#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.174.01:02:05.49#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.174.01:02:05.49#ibcon#enter wrdev, iclass 3, count 0 2006.174.01:02:05.49#ibcon#first serial, iclass 3, count 0 2006.174.01:02:05.49#ibcon#enter sib2, iclass 3, count 0 2006.174.01:02:05.49#ibcon#flushed, iclass 3, count 0 2006.174.01:02:05.49#ibcon#about to write, iclass 3, count 0 2006.174.01:02:05.49#ibcon#wrote, iclass 3, count 0 2006.174.01:02:05.49#ibcon#about to read 3, iclass 3, count 0 2006.174.01:02:05.51#ibcon#read 3, iclass 3, count 0 2006.174.01:02:05.51#ibcon#about to read 4, iclass 3, count 0 2006.174.01:02:05.51#ibcon#read 4, iclass 3, count 0 2006.174.01:02:05.51#ibcon#about to read 5, iclass 3, count 0 2006.174.01:02:05.51#ibcon#read 5, iclass 3, count 0 2006.174.01:02:05.51#ibcon#about to read 6, iclass 3, count 0 2006.174.01:02:05.51#ibcon#read 6, iclass 3, count 0 2006.174.01:02:05.51#ibcon#end of sib2, iclass 3, count 0 2006.174.01:02:05.51#ibcon#*mode == 0, iclass 3, count 0 2006.174.01:02:05.51#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.174.01:02:05.51#ibcon#[25=BW32\r\n] 2006.174.01:02:05.51#ibcon#*before write, iclass 3, count 0 2006.174.01:02:05.51#ibcon#enter sib2, iclass 3, count 0 2006.174.01:02:05.51#ibcon#flushed, iclass 3, count 0 2006.174.01:02:05.51#ibcon#about to write, iclass 3, count 0 2006.174.01:02:05.51#ibcon#wrote, iclass 3, count 0 2006.174.01:02:05.51#ibcon#about to read 3, iclass 3, count 0 2006.174.01:02:05.54#ibcon#read 3, iclass 3, count 0 2006.174.01:02:05.54#ibcon#about to read 4, iclass 3, count 0 2006.174.01:02:05.54#ibcon#read 4, iclass 3, count 0 2006.174.01:02:05.54#ibcon#about to read 5, iclass 3, count 0 2006.174.01:02:05.54#ibcon#read 5, iclass 3, count 0 2006.174.01:02:05.54#ibcon#about to read 6, iclass 3, count 0 2006.174.01:02:05.54#ibcon#read 6, iclass 3, count 0 2006.174.01:02:05.54#ibcon#end of sib2, iclass 3, count 0 2006.174.01:02:05.54#ibcon#*after write, iclass 3, count 0 2006.174.01:02:05.54#ibcon#*before return 0, iclass 3, count 0 2006.174.01:02:05.54#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.174.01:02:05.54#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.174.01:02:05.54#ibcon#about to clear, iclass 3 cls_cnt 0 2006.174.01:02:05.54#ibcon#cleared, iclass 3 cls_cnt 0 2006.174.01:02:05.54$vck44/vbbw=wide 2006.174.01:02:05.54#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.174.01:02:05.54#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.174.01:02:05.54#ibcon#ireg 8 cls_cnt 0 2006.174.01:02:05.54#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.174.01:02:05.61#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.174.01:02:05.61#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.174.01:02:05.61#ibcon#enter wrdev, iclass 5, count 0 2006.174.01:02:05.61#ibcon#first serial, iclass 5, count 0 2006.174.01:02:05.61#ibcon#enter sib2, iclass 5, count 0 2006.174.01:02:05.61#ibcon#flushed, iclass 5, count 0 2006.174.01:02:05.61#ibcon#about to write, iclass 5, count 0 2006.174.01:02:05.61#ibcon#wrote, iclass 5, count 0 2006.174.01:02:05.61#ibcon#about to read 3, iclass 5, count 0 2006.174.01:02:05.63#ibcon#read 3, iclass 5, count 0 2006.174.01:02:05.63#ibcon#about to read 4, iclass 5, count 0 2006.174.01:02:05.63#ibcon#read 4, iclass 5, count 0 2006.174.01:02:05.63#ibcon#about to read 5, iclass 5, count 0 2006.174.01:02:05.63#ibcon#read 5, iclass 5, count 0 2006.174.01:02:05.63#ibcon#about to read 6, iclass 5, count 0 2006.174.01:02:05.63#ibcon#read 6, iclass 5, count 0 2006.174.01:02:05.63#ibcon#end of sib2, iclass 5, count 0 2006.174.01:02:05.63#ibcon#*mode == 0, iclass 5, count 0 2006.174.01:02:05.63#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.174.01:02:05.63#ibcon#[27=BW32\r\n] 2006.174.01:02:05.63#ibcon#*before write, iclass 5, count 0 2006.174.01:02:05.63#ibcon#enter sib2, iclass 5, count 0 2006.174.01:02:05.63#ibcon#flushed, iclass 5, count 0 2006.174.01:02:05.63#ibcon#about to write, iclass 5, count 0 2006.174.01:02:05.63#ibcon#wrote, iclass 5, count 0 2006.174.01:02:05.63#ibcon#about to read 3, iclass 5, count 0 2006.174.01:02:05.66#ibcon#read 3, iclass 5, count 0 2006.174.01:02:05.66#ibcon#about to read 4, iclass 5, count 0 2006.174.01:02:05.66#ibcon#read 4, iclass 5, count 0 2006.174.01:02:05.66#ibcon#about to read 5, iclass 5, count 0 2006.174.01:02:05.66#ibcon#read 5, iclass 5, count 0 2006.174.01:02:05.66#ibcon#about to read 6, iclass 5, count 0 2006.174.01:02:05.66#ibcon#read 6, iclass 5, count 0 2006.174.01:02:05.66#ibcon#end of sib2, iclass 5, count 0 2006.174.01:02:05.66#ibcon#*after write, iclass 5, count 0 2006.174.01:02:05.66#ibcon#*before return 0, iclass 5, count 0 2006.174.01:02:05.66#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.174.01:02:05.66#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.174.01:02:05.66#ibcon#about to clear, iclass 5 cls_cnt 0 2006.174.01:02:05.66#ibcon#cleared, iclass 5 cls_cnt 0 2006.174.01:02:05.66$setupk4/ifdk4 2006.174.01:02:05.66$ifdk4/lo= 2006.174.01:02:05.66$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.174.01:02:05.66$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.174.01:02:05.66$ifdk4/patch= 2006.174.01:02:05.66$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.174.01:02:05.67$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.174.01:02:05.67$setupk4/!*+20s 2006.174.01:02:10.91#abcon#<5=/08 0.9 2.3 25.21 831003.4\r\n> 2006.174.01:02:10.93#abcon#{5=INTERFACE CLEAR} 2006.174.01:02:10.99#abcon#[5=S1D000X0/0*\r\n] 2006.174.01:02:20.19$setupk4/"tpicd 2006.174.01:02:20.19$setupk4/echo=off 2006.174.01:02:20.19$setupk4/xlog=off 2006.174.01:02:20.19:!2006.174.01:11:31 2006.174.01:02:27.14#trakl#Source acquired 2006.174.01:02:28.14#flagr#flagr/antenna,acquired 2006.174.01:11:31.00:preob 2006.174.01:11:32.14/onsource/TRACKING 2006.174.01:11:32.14:!2006.174.01:11:41 2006.174.01:11:41.00:"tape 2006.174.01:11:41.00:"st=record 2006.174.01:11:41.00:data_valid=on 2006.174.01:11:41.01:midob 2006.174.01:11:42.14/onsource/TRACKING 2006.174.01:11:42.14/wx/25.46,1003.3,80 2006.174.01:11:42.24/cable/+6.5008E-03 2006.174.01:11:43.33/va/01,07,usb,yes,36,38 2006.174.01:11:43.33/va/02,06,usb,yes,36,36 2006.174.01:11:43.33/va/03,05,usb,yes,45,47 2006.174.01:11:43.33/va/04,06,usb,yes,36,38 2006.174.01:11:43.33/va/05,04,usb,yes,28,29 2006.174.01:11:43.33/va/06,03,usb,yes,40,40 2006.174.01:11:43.33/va/07,04,usb,yes,32,33 2006.174.01:11:43.33/va/08,04,usb,yes,27,33 2006.174.01:11:43.56/valo/01,524.99,yes,locked 2006.174.01:11:43.56/valo/02,534.99,yes,locked 2006.174.01:11:43.56/valo/03,564.99,yes,locked 2006.174.01:11:43.56/valo/04,624.99,yes,locked 2006.174.01:11:43.56/valo/05,734.99,yes,locked 2006.174.01:11:43.56/valo/06,814.99,yes,locked 2006.174.01:11:43.56/valo/07,864.99,yes,locked 2006.174.01:11:43.56/valo/08,884.99,yes,locked 2006.174.01:11:44.65/vb/01,04,usb,yes,30,28 2006.174.01:11:44.65/vb/02,04,usb,yes,32,32 2006.174.01:11:44.65/vb/03,04,usb,yes,29,32 2006.174.01:11:44.65/vb/04,04,usb,yes,33,32 2006.174.01:11:44.65/vb/05,04,usb,yes,26,28 2006.174.01:11:44.65/vb/06,04,usb,yes,30,27 2006.174.01:11:44.65/vb/07,04,usb,yes,30,30 2006.174.01:11:44.65/vb/08,04,usb,yes,28,31 2006.174.01:11:44.89/vblo/01,629.99,yes,locked 2006.174.01:11:44.89/vblo/02,634.99,yes,locked 2006.174.01:11:44.89/vblo/03,649.99,yes,locked 2006.174.01:11:44.89/vblo/04,679.99,yes,locked 2006.174.01:11:44.89/vblo/05,709.99,yes,locked 2006.174.01:11:44.89/vblo/06,719.99,yes,locked 2006.174.01:11:44.89/vblo/07,734.99,yes,locked 2006.174.01:11:44.89/vblo/08,744.99,yes,locked 2006.174.01:11:45.04/vabw/8 2006.174.01:11:45.19/vbbw/8 2006.174.01:11:45.28/xfe/off,on,15.2 2006.174.01:11:45.65/ifatt/23,28,28,28 2006.174.01:11:46.07/fmout-gps/S +3.82E-07 2006.174.01:11:46.12:!2006.174.01:12:41 2006.174.01:12:41.01:data_valid=off 2006.174.01:12:41.02:"et 2006.174.01:12:41.02:!+3s 2006.174.01:12:44.03:"tape 2006.174.01:12:44.03:postob 2006.174.01:12:44.17/cable/+6.5016E-03 2006.174.01:12:44.18/wx/25.47,1003.3,82 2006.174.01:12:44.23/fmout-gps/S +3.81E-07 2006.174.01:12:44.24:scan_name=174-0115,jd0606,230 2006.174.01:12:44.24:source=1044+719,104827.62,714335.9,2000.0,ccw 2006.174.01:12:45.14#flagr#flagr/antenna,new-source 2006.174.01:12:45.15:checkk5 2006.174.01:12:45.57/chk_autoobs//k5ts1/ autoobs is running! 2006.174.01:12:45.96/chk_autoobs//k5ts2/ autoobs is running! 2006.174.01:12:46.37/chk_autoobs//k5ts3/ autoobs is running! 2006.174.01:12:46.77/chk_autoobs//k5ts4/ autoobs is running! 2006.174.01:12:47.16/chk_obsdata//k5ts1/T1740111??a.dat file size is correct (nominal:240MB, actual:236MB). 2006.174.01:12:47.60/chk_obsdata//k5ts2/T1740111??b.dat file size is correct (nominal:240MB, actual:236MB). 2006.174.01:12:48.01/chk_obsdata//k5ts3/T1740111??c.dat file size is correct (nominal:240MB, actual:236MB). 2006.174.01:12:48.41/chk_obsdata//k5ts4/T1740111??d.dat file size is correct (nominal:240MB, actual:236MB). 2006.174.01:12:49.15/k5log//k5ts1_log_newline 2006.174.01:12:49.86/k5log//k5ts2_log_newline 2006.174.01:12:50.58/k5log//k5ts3_log_newline 2006.174.01:12:51.29/k5log//k5ts4_log_newline 2006.174.01:12:51.32/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.174.01:12:51.32:setupk4=1 2006.174.01:12:51.32$setupk4/echo=on 2006.174.01:12:51.32$setupk4/pcalon 2006.174.01:12:51.32$pcalon/"no phase cal control is implemented here 2006.174.01:12:51.32$setupk4/"tpicd=stop 2006.174.01:12:51.32$setupk4/"rec=synch_on 2006.174.01:12:51.32$setupk4/"rec_mode=128 2006.174.01:12:51.32$setupk4/!* 2006.174.01:12:51.32$setupk4/recpk4 2006.174.01:12:51.32$recpk4/recpatch= 2006.174.01:12:51.32$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.174.01:12:51.32$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.174.01:12:51.32$setupk4/vck44 2006.174.01:12:51.32$vck44/valo=1,524.99 2006.174.01:12:51.32#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.174.01:12:51.32#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.174.01:12:51.32#ibcon#ireg 17 cls_cnt 0 2006.174.01:12:51.32#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.174.01:12:51.32#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.174.01:12:51.32#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.174.01:12:51.32#ibcon#enter wrdev, iclass 12, count 0 2006.174.01:12:51.32#ibcon#first serial, iclass 12, count 0 2006.174.01:12:51.32#ibcon#enter sib2, iclass 12, count 0 2006.174.01:12:51.32#ibcon#flushed, iclass 12, count 0 2006.174.01:12:51.32#ibcon#about to write, iclass 12, count 0 2006.174.01:12:51.32#ibcon#wrote, iclass 12, count 0 2006.174.01:12:51.32#ibcon#about to read 3, iclass 12, count 0 2006.174.01:12:51.34#ibcon#read 3, iclass 12, count 0 2006.174.01:12:51.34#ibcon#about to read 4, iclass 12, count 0 2006.174.01:12:51.34#ibcon#read 4, iclass 12, count 0 2006.174.01:12:51.34#ibcon#about to read 5, iclass 12, count 0 2006.174.01:12:51.34#ibcon#read 5, iclass 12, count 0 2006.174.01:12:51.34#ibcon#about to read 6, iclass 12, count 0 2006.174.01:12:51.34#ibcon#read 6, iclass 12, count 0 2006.174.01:12:51.34#ibcon#end of sib2, iclass 12, count 0 2006.174.01:12:51.34#ibcon#*mode == 0, iclass 12, count 0 2006.174.01:12:51.34#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.174.01:12:51.34#ibcon#[26=FRQ=01,524.99\r\n] 2006.174.01:12:51.34#ibcon#*before write, iclass 12, count 0 2006.174.01:12:51.34#ibcon#enter sib2, iclass 12, count 0 2006.174.01:12:51.34#ibcon#flushed, iclass 12, count 0 2006.174.01:12:51.34#ibcon#about to write, iclass 12, count 0 2006.174.01:12:51.34#ibcon#wrote, iclass 12, count 0 2006.174.01:12:51.34#ibcon#about to read 3, iclass 12, count 0 2006.174.01:12:51.39#ibcon#read 3, iclass 12, count 0 2006.174.01:12:51.39#ibcon#about to read 4, iclass 12, count 0 2006.174.01:12:51.39#ibcon#read 4, iclass 12, count 0 2006.174.01:12:51.39#ibcon#about to read 5, iclass 12, count 0 2006.174.01:12:51.39#ibcon#read 5, iclass 12, count 0 2006.174.01:12:51.39#ibcon#about to read 6, iclass 12, count 0 2006.174.01:12:51.39#ibcon#read 6, iclass 12, count 0 2006.174.01:12:51.39#ibcon#end of sib2, iclass 12, count 0 2006.174.01:12:51.39#ibcon#*after write, iclass 12, count 0 2006.174.01:12:51.39#ibcon#*before return 0, iclass 12, count 0 2006.174.01:12:51.39#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.174.01:12:51.39#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.174.01:12:51.39#ibcon#about to clear, iclass 12 cls_cnt 0 2006.174.01:12:51.39#ibcon#cleared, iclass 12 cls_cnt 0 2006.174.01:12:51.39$vck44/va=1,7 2006.174.01:12:51.39#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.174.01:12:51.39#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.174.01:12:51.39#ibcon#ireg 11 cls_cnt 2 2006.174.01:12:51.39#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.174.01:12:51.39#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.174.01:12:51.39#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.174.01:12:51.39#ibcon#enter wrdev, iclass 14, count 2 2006.174.01:12:51.39#ibcon#first serial, iclass 14, count 2 2006.174.01:12:51.39#ibcon#enter sib2, iclass 14, count 2 2006.174.01:12:51.39#ibcon#flushed, iclass 14, count 2 2006.174.01:12:51.39#ibcon#about to write, iclass 14, count 2 2006.174.01:12:51.39#ibcon#wrote, iclass 14, count 2 2006.174.01:12:51.39#ibcon#about to read 3, iclass 14, count 2 2006.174.01:12:51.41#ibcon#read 3, iclass 14, count 2 2006.174.01:12:51.41#ibcon#about to read 4, iclass 14, count 2 2006.174.01:12:51.41#ibcon#read 4, iclass 14, count 2 2006.174.01:12:51.41#ibcon#about to read 5, iclass 14, count 2 2006.174.01:12:51.41#ibcon#read 5, iclass 14, count 2 2006.174.01:12:51.41#ibcon#about to read 6, iclass 14, count 2 2006.174.01:12:51.41#ibcon#read 6, iclass 14, count 2 2006.174.01:12:51.41#ibcon#end of sib2, iclass 14, count 2 2006.174.01:12:51.41#ibcon#*mode == 0, iclass 14, count 2 2006.174.01:12:51.41#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.174.01:12:51.41#ibcon#[25=AT01-07\r\n] 2006.174.01:12:51.41#ibcon#*before write, iclass 14, count 2 2006.174.01:12:51.41#ibcon#enter sib2, iclass 14, count 2 2006.174.01:12:51.41#ibcon#flushed, iclass 14, count 2 2006.174.01:12:51.41#ibcon#about to write, iclass 14, count 2 2006.174.01:12:51.41#ibcon#wrote, iclass 14, count 2 2006.174.01:12:51.41#ibcon#about to read 3, iclass 14, count 2 2006.174.01:12:51.44#ibcon#read 3, iclass 14, count 2 2006.174.01:12:51.44#ibcon#about to read 4, iclass 14, count 2 2006.174.01:12:51.44#ibcon#read 4, iclass 14, count 2 2006.174.01:12:51.44#ibcon#about to read 5, iclass 14, count 2 2006.174.01:12:51.44#ibcon#read 5, iclass 14, count 2 2006.174.01:12:51.44#ibcon#about to read 6, iclass 14, count 2 2006.174.01:12:51.44#ibcon#read 6, iclass 14, count 2 2006.174.01:12:51.44#ibcon#end of sib2, iclass 14, count 2 2006.174.01:12:51.44#ibcon#*after write, iclass 14, count 2 2006.174.01:12:51.44#ibcon#*before return 0, iclass 14, count 2 2006.174.01:12:51.44#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.174.01:12:51.44#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.174.01:12:51.44#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.174.01:12:51.44#ibcon#ireg 7 cls_cnt 0 2006.174.01:12:51.44#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.174.01:12:51.56#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.174.01:12:51.56#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.174.01:12:51.56#ibcon#enter wrdev, iclass 14, count 0 2006.174.01:12:51.56#ibcon#first serial, iclass 14, count 0 2006.174.01:12:51.56#ibcon#enter sib2, iclass 14, count 0 2006.174.01:12:51.56#ibcon#flushed, iclass 14, count 0 2006.174.01:12:51.56#ibcon#about to write, iclass 14, count 0 2006.174.01:12:51.56#ibcon#wrote, iclass 14, count 0 2006.174.01:12:51.56#ibcon#about to read 3, iclass 14, count 0 2006.174.01:12:51.58#ibcon#read 3, iclass 14, count 0 2006.174.01:12:51.58#ibcon#about to read 4, iclass 14, count 0 2006.174.01:12:51.58#ibcon#read 4, iclass 14, count 0 2006.174.01:12:51.58#ibcon#about to read 5, iclass 14, count 0 2006.174.01:12:51.58#ibcon#read 5, iclass 14, count 0 2006.174.01:12:51.58#ibcon#about to read 6, iclass 14, count 0 2006.174.01:12:51.58#ibcon#read 6, iclass 14, count 0 2006.174.01:12:51.58#ibcon#end of sib2, iclass 14, count 0 2006.174.01:12:51.58#ibcon#*mode == 0, iclass 14, count 0 2006.174.01:12:51.58#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.174.01:12:51.58#ibcon#[25=USB\r\n] 2006.174.01:12:51.58#ibcon#*before write, iclass 14, count 0 2006.174.01:12:51.58#ibcon#enter sib2, iclass 14, count 0 2006.174.01:12:51.58#ibcon#flushed, iclass 14, count 0 2006.174.01:12:51.58#ibcon#about to write, iclass 14, count 0 2006.174.01:12:51.58#ibcon#wrote, iclass 14, count 0 2006.174.01:12:51.58#ibcon#about to read 3, iclass 14, count 0 2006.174.01:12:51.61#ibcon#read 3, iclass 14, count 0 2006.174.01:12:51.61#ibcon#about to read 4, iclass 14, count 0 2006.174.01:12:51.61#ibcon#read 4, iclass 14, count 0 2006.174.01:12:51.61#ibcon#about to read 5, iclass 14, count 0 2006.174.01:12:51.61#ibcon#read 5, iclass 14, count 0 2006.174.01:12:51.61#ibcon#about to read 6, iclass 14, count 0 2006.174.01:12:51.61#ibcon#read 6, iclass 14, count 0 2006.174.01:12:51.61#ibcon#end of sib2, iclass 14, count 0 2006.174.01:12:51.61#ibcon#*after write, iclass 14, count 0 2006.174.01:12:51.61#ibcon#*before return 0, iclass 14, count 0 2006.174.01:12:51.61#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.174.01:12:51.61#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.174.01:12:51.61#ibcon#about to clear, iclass 14 cls_cnt 0 2006.174.01:12:51.61#ibcon#cleared, iclass 14 cls_cnt 0 2006.174.01:12:51.61$vck44/valo=2,534.99 2006.174.01:12:51.61#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.174.01:12:51.61#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.174.01:12:51.61#ibcon#ireg 17 cls_cnt 0 2006.174.01:12:51.61#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.174.01:12:51.61#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.174.01:12:51.61#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.174.01:12:51.61#ibcon#enter wrdev, iclass 16, count 0 2006.174.01:12:51.61#ibcon#first serial, iclass 16, count 0 2006.174.01:12:51.61#ibcon#enter sib2, iclass 16, count 0 2006.174.01:12:51.61#ibcon#flushed, iclass 16, count 0 2006.174.01:12:51.61#ibcon#about to write, iclass 16, count 0 2006.174.01:12:51.61#ibcon#wrote, iclass 16, count 0 2006.174.01:12:51.61#ibcon#about to read 3, iclass 16, count 0 2006.174.01:12:51.63#ibcon#read 3, iclass 16, count 0 2006.174.01:12:51.63#ibcon#about to read 4, iclass 16, count 0 2006.174.01:12:51.63#ibcon#read 4, iclass 16, count 0 2006.174.01:12:51.63#ibcon#about to read 5, iclass 16, count 0 2006.174.01:12:51.63#ibcon#read 5, iclass 16, count 0 2006.174.01:12:51.63#ibcon#about to read 6, iclass 16, count 0 2006.174.01:12:51.63#ibcon#read 6, iclass 16, count 0 2006.174.01:12:51.63#ibcon#end of sib2, iclass 16, count 0 2006.174.01:12:51.63#ibcon#*mode == 0, iclass 16, count 0 2006.174.01:12:51.63#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.174.01:12:51.63#ibcon#[26=FRQ=02,534.99\r\n] 2006.174.01:12:51.63#ibcon#*before write, iclass 16, count 0 2006.174.01:12:51.63#ibcon#enter sib2, iclass 16, count 0 2006.174.01:12:51.63#ibcon#flushed, iclass 16, count 0 2006.174.01:12:51.63#ibcon#about to write, iclass 16, count 0 2006.174.01:12:51.63#ibcon#wrote, iclass 16, count 0 2006.174.01:12:51.63#ibcon#about to read 3, iclass 16, count 0 2006.174.01:12:51.67#ibcon#read 3, iclass 16, count 0 2006.174.01:12:51.67#ibcon#about to read 4, iclass 16, count 0 2006.174.01:12:51.67#ibcon#read 4, iclass 16, count 0 2006.174.01:12:51.67#ibcon#about to read 5, iclass 16, count 0 2006.174.01:12:51.67#ibcon#read 5, iclass 16, count 0 2006.174.01:12:51.67#ibcon#about to read 6, iclass 16, count 0 2006.174.01:12:51.67#ibcon#read 6, iclass 16, count 0 2006.174.01:12:51.67#ibcon#end of sib2, iclass 16, count 0 2006.174.01:12:51.67#ibcon#*after write, iclass 16, count 0 2006.174.01:12:51.67#ibcon#*before return 0, iclass 16, count 0 2006.174.01:12:51.67#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.174.01:12:51.67#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.174.01:12:51.67#ibcon#about to clear, iclass 16 cls_cnt 0 2006.174.01:12:51.67#ibcon#cleared, iclass 16 cls_cnt 0 2006.174.01:12:51.67$vck44/va=2,6 2006.174.01:12:51.67#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.174.01:12:51.67#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.174.01:12:51.67#ibcon#ireg 11 cls_cnt 2 2006.174.01:12:51.67#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.174.01:12:51.73#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.174.01:12:51.73#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.174.01:12:51.73#ibcon#enter wrdev, iclass 18, count 2 2006.174.01:12:51.73#ibcon#first serial, iclass 18, count 2 2006.174.01:12:51.73#ibcon#enter sib2, iclass 18, count 2 2006.174.01:12:51.73#ibcon#flushed, iclass 18, count 2 2006.174.01:12:51.73#ibcon#about to write, iclass 18, count 2 2006.174.01:12:51.73#ibcon#wrote, iclass 18, count 2 2006.174.01:12:51.73#ibcon#about to read 3, iclass 18, count 2 2006.174.01:12:51.75#ibcon#read 3, iclass 18, count 2 2006.174.01:12:51.75#ibcon#about to read 4, iclass 18, count 2 2006.174.01:12:51.75#ibcon#read 4, iclass 18, count 2 2006.174.01:12:51.75#ibcon#about to read 5, iclass 18, count 2 2006.174.01:12:51.75#ibcon#read 5, iclass 18, count 2 2006.174.01:12:51.75#ibcon#about to read 6, iclass 18, count 2 2006.174.01:12:51.75#ibcon#read 6, iclass 18, count 2 2006.174.01:12:51.75#ibcon#end of sib2, iclass 18, count 2 2006.174.01:12:51.75#ibcon#*mode == 0, iclass 18, count 2 2006.174.01:12:51.75#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.174.01:12:51.75#ibcon#[25=AT02-06\r\n] 2006.174.01:12:51.75#ibcon#*before write, iclass 18, count 2 2006.174.01:12:51.75#ibcon#enter sib2, iclass 18, count 2 2006.174.01:12:51.75#ibcon#flushed, iclass 18, count 2 2006.174.01:12:51.75#ibcon#about to write, iclass 18, count 2 2006.174.01:12:51.75#ibcon#wrote, iclass 18, count 2 2006.174.01:12:51.75#ibcon#about to read 3, iclass 18, count 2 2006.174.01:12:51.78#ibcon#read 3, iclass 18, count 2 2006.174.01:12:51.78#ibcon#about to read 4, iclass 18, count 2 2006.174.01:12:51.78#ibcon#read 4, iclass 18, count 2 2006.174.01:12:51.78#ibcon#about to read 5, iclass 18, count 2 2006.174.01:12:51.78#ibcon#read 5, iclass 18, count 2 2006.174.01:12:51.78#ibcon#about to read 6, iclass 18, count 2 2006.174.01:12:51.78#ibcon#read 6, iclass 18, count 2 2006.174.01:12:51.78#ibcon#end of sib2, iclass 18, count 2 2006.174.01:12:51.78#ibcon#*after write, iclass 18, count 2 2006.174.01:12:51.78#ibcon#*before return 0, iclass 18, count 2 2006.174.01:12:51.78#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.174.01:12:51.78#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.174.01:12:51.78#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.174.01:12:51.78#ibcon#ireg 7 cls_cnt 0 2006.174.01:12:51.78#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.174.01:12:51.85#abcon#<5=/07 0.7 1.6 25.48 821003.3\r\n> 2006.174.01:12:51.87#abcon#{5=INTERFACE CLEAR} 2006.174.01:12:51.90#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.174.01:12:51.90#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.174.01:12:51.90#ibcon#enter wrdev, iclass 18, count 0 2006.174.01:12:51.90#ibcon#first serial, iclass 18, count 0 2006.174.01:12:51.90#ibcon#enter sib2, iclass 18, count 0 2006.174.01:12:51.90#ibcon#flushed, iclass 18, count 0 2006.174.01:12:51.90#ibcon#about to write, iclass 18, count 0 2006.174.01:12:51.90#ibcon#wrote, iclass 18, count 0 2006.174.01:12:51.90#ibcon#about to read 3, iclass 18, count 0 2006.174.01:12:51.92#ibcon#read 3, iclass 18, count 0 2006.174.01:12:51.92#ibcon#about to read 4, iclass 18, count 0 2006.174.01:12:51.92#ibcon#read 4, iclass 18, count 0 2006.174.01:12:51.92#ibcon#about to read 5, iclass 18, count 0 2006.174.01:12:51.92#ibcon#read 5, iclass 18, count 0 2006.174.01:12:51.92#ibcon#about to read 6, iclass 18, count 0 2006.174.01:12:51.92#ibcon#read 6, iclass 18, count 0 2006.174.01:12:51.92#ibcon#end of sib2, iclass 18, count 0 2006.174.01:12:51.92#ibcon#*mode == 0, iclass 18, count 0 2006.174.01:12:51.92#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.174.01:12:51.92#ibcon#[25=USB\r\n] 2006.174.01:12:51.92#ibcon#*before write, iclass 18, count 0 2006.174.01:12:51.92#ibcon#enter sib2, iclass 18, count 0 2006.174.01:12:51.92#ibcon#flushed, iclass 18, count 0 2006.174.01:12:51.92#ibcon#about to write, iclass 18, count 0 2006.174.01:12:51.92#ibcon#wrote, iclass 18, count 0 2006.174.01:12:51.92#ibcon#about to read 3, iclass 18, count 0 2006.174.01:12:51.93#abcon#[5=S1D000X0/0*\r\n] 2006.174.01:12:51.95#ibcon#read 3, iclass 18, count 0 2006.174.01:12:51.95#ibcon#about to read 4, iclass 18, count 0 2006.174.01:12:51.95#ibcon#read 4, iclass 18, count 0 2006.174.01:12:51.95#ibcon#about to read 5, iclass 18, count 0 2006.174.01:12:51.95#ibcon#read 5, iclass 18, count 0 2006.174.01:12:51.95#ibcon#about to read 6, iclass 18, count 0 2006.174.01:12:51.95#ibcon#read 6, iclass 18, count 0 2006.174.01:12:51.95#ibcon#end of sib2, iclass 18, count 0 2006.174.01:12:51.95#ibcon#*after write, iclass 18, count 0 2006.174.01:12:51.95#ibcon#*before return 0, iclass 18, count 0 2006.174.01:12:51.95#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.174.01:12:51.95#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.174.01:12:51.95#ibcon#about to clear, iclass 18 cls_cnt 0 2006.174.01:12:51.95#ibcon#cleared, iclass 18 cls_cnt 0 2006.174.01:12:51.95$vck44/valo=3,564.99 2006.174.01:12:51.95#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.174.01:12:51.95#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.174.01:12:51.95#ibcon#ireg 17 cls_cnt 0 2006.174.01:12:51.95#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.174.01:12:51.95#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.174.01:12:51.95#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.174.01:12:51.95#ibcon#enter wrdev, iclass 24, count 0 2006.174.01:12:51.95#ibcon#first serial, iclass 24, count 0 2006.174.01:12:51.95#ibcon#enter sib2, iclass 24, count 0 2006.174.01:12:51.95#ibcon#flushed, iclass 24, count 0 2006.174.01:12:51.95#ibcon#about to write, iclass 24, count 0 2006.174.01:12:51.95#ibcon#wrote, iclass 24, count 0 2006.174.01:12:51.95#ibcon#about to read 3, iclass 24, count 0 2006.174.01:12:51.97#ibcon#read 3, iclass 24, count 0 2006.174.01:12:51.97#ibcon#about to read 4, iclass 24, count 0 2006.174.01:12:51.97#ibcon#read 4, iclass 24, count 0 2006.174.01:12:51.97#ibcon#about to read 5, iclass 24, count 0 2006.174.01:12:51.97#ibcon#read 5, iclass 24, count 0 2006.174.01:12:51.97#ibcon#about to read 6, iclass 24, count 0 2006.174.01:12:51.97#ibcon#read 6, iclass 24, count 0 2006.174.01:12:51.97#ibcon#end of sib2, iclass 24, count 0 2006.174.01:12:51.97#ibcon#*mode == 0, iclass 24, count 0 2006.174.01:12:51.97#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.174.01:12:51.97#ibcon#[26=FRQ=03,564.99\r\n] 2006.174.01:12:51.97#ibcon#*before write, iclass 24, count 0 2006.174.01:12:51.97#ibcon#enter sib2, iclass 24, count 0 2006.174.01:12:51.97#ibcon#flushed, iclass 24, count 0 2006.174.01:12:51.97#ibcon#about to write, iclass 24, count 0 2006.174.01:12:51.97#ibcon#wrote, iclass 24, count 0 2006.174.01:12:51.97#ibcon#about to read 3, iclass 24, count 0 2006.174.01:12:52.01#ibcon#read 3, iclass 24, count 0 2006.174.01:12:52.01#ibcon#about to read 4, iclass 24, count 0 2006.174.01:12:52.01#ibcon#read 4, iclass 24, count 0 2006.174.01:12:52.01#ibcon#about to read 5, iclass 24, count 0 2006.174.01:12:52.01#ibcon#read 5, iclass 24, count 0 2006.174.01:12:52.01#ibcon#about to read 6, iclass 24, count 0 2006.174.01:12:52.01#ibcon#read 6, iclass 24, count 0 2006.174.01:12:52.01#ibcon#end of sib2, iclass 24, count 0 2006.174.01:12:52.01#ibcon#*after write, iclass 24, count 0 2006.174.01:12:52.01#ibcon#*before return 0, iclass 24, count 0 2006.174.01:12:52.01#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.174.01:12:52.01#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.174.01:12:52.01#ibcon#about to clear, iclass 24 cls_cnt 0 2006.174.01:12:52.01#ibcon#cleared, iclass 24 cls_cnt 0 2006.174.01:12:52.01$vck44/va=3,5 2006.174.01:12:52.01#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.174.01:12:52.01#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.174.01:12:52.01#ibcon#ireg 11 cls_cnt 2 2006.174.01:12:52.01#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.174.01:12:52.07#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.174.01:12:52.07#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.174.01:12:52.07#ibcon#enter wrdev, iclass 26, count 2 2006.174.01:12:52.07#ibcon#first serial, iclass 26, count 2 2006.174.01:12:52.07#ibcon#enter sib2, iclass 26, count 2 2006.174.01:12:52.07#ibcon#flushed, iclass 26, count 2 2006.174.01:12:52.07#ibcon#about to write, iclass 26, count 2 2006.174.01:12:52.07#ibcon#wrote, iclass 26, count 2 2006.174.01:12:52.07#ibcon#about to read 3, iclass 26, count 2 2006.174.01:12:52.09#ibcon#read 3, iclass 26, count 2 2006.174.01:12:52.09#ibcon#about to read 4, iclass 26, count 2 2006.174.01:12:52.09#ibcon#read 4, iclass 26, count 2 2006.174.01:12:52.09#ibcon#about to read 5, iclass 26, count 2 2006.174.01:12:52.09#ibcon#read 5, iclass 26, count 2 2006.174.01:12:52.09#ibcon#about to read 6, iclass 26, count 2 2006.174.01:12:52.09#ibcon#read 6, iclass 26, count 2 2006.174.01:12:52.09#ibcon#end of sib2, iclass 26, count 2 2006.174.01:12:52.09#ibcon#*mode == 0, iclass 26, count 2 2006.174.01:12:52.09#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.174.01:12:52.09#ibcon#[25=AT03-05\r\n] 2006.174.01:12:52.09#ibcon#*before write, iclass 26, count 2 2006.174.01:12:52.09#ibcon#enter sib2, iclass 26, count 2 2006.174.01:12:52.09#ibcon#flushed, iclass 26, count 2 2006.174.01:12:52.09#ibcon#about to write, iclass 26, count 2 2006.174.01:12:52.09#ibcon#wrote, iclass 26, count 2 2006.174.01:12:52.09#ibcon#about to read 3, iclass 26, count 2 2006.174.01:12:52.12#ibcon#read 3, iclass 26, count 2 2006.174.01:12:52.12#ibcon#about to read 4, iclass 26, count 2 2006.174.01:12:52.12#ibcon#read 4, iclass 26, count 2 2006.174.01:12:52.12#ibcon#about to read 5, iclass 26, count 2 2006.174.01:12:52.12#ibcon#read 5, iclass 26, count 2 2006.174.01:12:52.12#ibcon#about to read 6, iclass 26, count 2 2006.174.01:12:52.12#ibcon#read 6, iclass 26, count 2 2006.174.01:12:52.12#ibcon#end of sib2, iclass 26, count 2 2006.174.01:12:52.12#ibcon#*after write, iclass 26, count 2 2006.174.01:12:52.12#ibcon#*before return 0, iclass 26, count 2 2006.174.01:12:52.12#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.174.01:12:52.12#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.174.01:12:52.12#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.174.01:12:52.12#ibcon#ireg 7 cls_cnt 0 2006.174.01:12:52.12#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.174.01:12:52.24#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.174.01:12:52.24#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.174.01:12:52.24#ibcon#enter wrdev, iclass 26, count 0 2006.174.01:12:52.24#ibcon#first serial, iclass 26, count 0 2006.174.01:12:52.24#ibcon#enter sib2, iclass 26, count 0 2006.174.01:12:52.24#ibcon#flushed, iclass 26, count 0 2006.174.01:12:52.24#ibcon#about to write, iclass 26, count 0 2006.174.01:12:52.24#ibcon#wrote, iclass 26, count 0 2006.174.01:12:52.24#ibcon#about to read 3, iclass 26, count 0 2006.174.01:12:52.26#ibcon#read 3, iclass 26, count 0 2006.174.01:12:52.26#ibcon#about to read 4, iclass 26, count 0 2006.174.01:12:52.26#ibcon#read 4, iclass 26, count 0 2006.174.01:12:52.26#ibcon#about to read 5, iclass 26, count 0 2006.174.01:12:52.26#ibcon#read 5, iclass 26, count 0 2006.174.01:12:52.26#ibcon#about to read 6, iclass 26, count 0 2006.174.01:12:52.26#ibcon#read 6, iclass 26, count 0 2006.174.01:12:52.26#ibcon#end of sib2, iclass 26, count 0 2006.174.01:12:52.26#ibcon#*mode == 0, iclass 26, count 0 2006.174.01:12:52.26#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.174.01:12:52.26#ibcon#[25=USB\r\n] 2006.174.01:12:52.26#ibcon#*before write, iclass 26, count 0 2006.174.01:12:52.26#ibcon#enter sib2, iclass 26, count 0 2006.174.01:12:52.26#ibcon#flushed, iclass 26, count 0 2006.174.01:12:52.26#ibcon#about to write, iclass 26, count 0 2006.174.01:12:52.26#ibcon#wrote, iclass 26, count 0 2006.174.01:12:52.26#ibcon#about to read 3, iclass 26, count 0 2006.174.01:12:52.29#ibcon#read 3, iclass 26, count 0 2006.174.01:12:52.29#ibcon#about to read 4, iclass 26, count 0 2006.174.01:12:52.29#ibcon#read 4, iclass 26, count 0 2006.174.01:12:52.29#ibcon#about to read 5, iclass 26, count 0 2006.174.01:12:52.29#ibcon#read 5, iclass 26, count 0 2006.174.01:12:52.29#ibcon#about to read 6, iclass 26, count 0 2006.174.01:12:52.29#ibcon#read 6, iclass 26, count 0 2006.174.01:12:52.29#ibcon#end of sib2, iclass 26, count 0 2006.174.01:12:52.29#ibcon#*after write, iclass 26, count 0 2006.174.01:12:52.29#ibcon#*before return 0, iclass 26, count 0 2006.174.01:12:52.29#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.174.01:12:52.29#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.174.01:12:52.29#ibcon#about to clear, iclass 26 cls_cnt 0 2006.174.01:12:52.29#ibcon#cleared, iclass 26 cls_cnt 0 2006.174.01:12:52.29$vck44/valo=4,624.99 2006.174.01:12:52.29#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.174.01:12:52.29#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.174.01:12:52.29#ibcon#ireg 17 cls_cnt 0 2006.174.01:12:52.29#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.174.01:12:52.29#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.174.01:12:52.29#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.174.01:12:52.29#ibcon#enter wrdev, iclass 28, count 0 2006.174.01:12:52.29#ibcon#first serial, iclass 28, count 0 2006.174.01:12:52.29#ibcon#enter sib2, iclass 28, count 0 2006.174.01:12:52.29#ibcon#flushed, iclass 28, count 0 2006.174.01:12:52.29#ibcon#about to write, iclass 28, count 0 2006.174.01:12:52.29#ibcon#wrote, iclass 28, count 0 2006.174.01:12:52.29#ibcon#about to read 3, iclass 28, count 0 2006.174.01:12:52.31#ibcon#read 3, iclass 28, count 0 2006.174.01:12:52.31#ibcon#about to read 4, iclass 28, count 0 2006.174.01:12:52.31#ibcon#read 4, iclass 28, count 0 2006.174.01:12:52.31#ibcon#about to read 5, iclass 28, count 0 2006.174.01:12:52.31#ibcon#read 5, iclass 28, count 0 2006.174.01:12:52.31#ibcon#about to read 6, iclass 28, count 0 2006.174.01:12:52.31#ibcon#read 6, iclass 28, count 0 2006.174.01:12:52.31#ibcon#end of sib2, iclass 28, count 0 2006.174.01:12:52.31#ibcon#*mode == 0, iclass 28, count 0 2006.174.01:12:52.31#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.174.01:12:52.31#ibcon#[26=FRQ=04,624.99\r\n] 2006.174.01:12:52.31#ibcon#*before write, iclass 28, count 0 2006.174.01:12:52.31#ibcon#enter sib2, iclass 28, count 0 2006.174.01:12:52.31#ibcon#flushed, iclass 28, count 0 2006.174.01:12:52.31#ibcon#about to write, iclass 28, count 0 2006.174.01:12:52.31#ibcon#wrote, iclass 28, count 0 2006.174.01:12:52.31#ibcon#about to read 3, iclass 28, count 0 2006.174.01:12:52.35#ibcon#read 3, iclass 28, count 0 2006.174.01:12:52.35#ibcon#about to read 4, iclass 28, count 0 2006.174.01:12:52.35#ibcon#read 4, iclass 28, count 0 2006.174.01:12:52.35#ibcon#about to read 5, iclass 28, count 0 2006.174.01:12:52.35#ibcon#read 5, iclass 28, count 0 2006.174.01:12:52.35#ibcon#about to read 6, iclass 28, count 0 2006.174.01:12:52.35#ibcon#read 6, iclass 28, count 0 2006.174.01:12:52.35#ibcon#end of sib2, iclass 28, count 0 2006.174.01:12:52.35#ibcon#*after write, iclass 28, count 0 2006.174.01:12:52.35#ibcon#*before return 0, iclass 28, count 0 2006.174.01:12:52.35#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.174.01:12:52.35#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.174.01:12:52.35#ibcon#about to clear, iclass 28 cls_cnt 0 2006.174.01:12:52.35#ibcon#cleared, iclass 28 cls_cnt 0 2006.174.01:12:52.35$vck44/va=4,6 2006.174.01:12:52.35#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.174.01:12:52.35#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.174.01:12:52.35#ibcon#ireg 11 cls_cnt 2 2006.174.01:12:52.35#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.174.01:12:52.41#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.174.01:12:52.41#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.174.01:12:52.41#ibcon#enter wrdev, iclass 30, count 2 2006.174.01:12:52.41#ibcon#first serial, iclass 30, count 2 2006.174.01:12:52.41#ibcon#enter sib2, iclass 30, count 2 2006.174.01:12:52.41#ibcon#flushed, iclass 30, count 2 2006.174.01:12:52.41#ibcon#about to write, iclass 30, count 2 2006.174.01:12:52.41#ibcon#wrote, iclass 30, count 2 2006.174.01:12:52.41#ibcon#about to read 3, iclass 30, count 2 2006.174.01:12:52.43#ibcon#read 3, iclass 30, count 2 2006.174.01:12:52.43#ibcon#about to read 4, iclass 30, count 2 2006.174.01:12:52.43#ibcon#read 4, iclass 30, count 2 2006.174.01:12:52.43#ibcon#about to read 5, iclass 30, count 2 2006.174.01:12:52.43#ibcon#read 5, iclass 30, count 2 2006.174.01:12:52.43#ibcon#about to read 6, iclass 30, count 2 2006.174.01:12:52.43#ibcon#read 6, iclass 30, count 2 2006.174.01:12:52.43#ibcon#end of sib2, iclass 30, count 2 2006.174.01:12:52.43#ibcon#*mode == 0, iclass 30, count 2 2006.174.01:12:52.43#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.174.01:12:52.43#ibcon#[25=AT04-06\r\n] 2006.174.01:12:52.43#ibcon#*before write, iclass 30, count 2 2006.174.01:12:52.43#ibcon#enter sib2, iclass 30, count 2 2006.174.01:12:52.43#ibcon#flushed, iclass 30, count 2 2006.174.01:12:52.43#ibcon#about to write, iclass 30, count 2 2006.174.01:12:52.43#ibcon#wrote, iclass 30, count 2 2006.174.01:12:52.43#ibcon#about to read 3, iclass 30, count 2 2006.174.01:12:52.46#ibcon#read 3, iclass 30, count 2 2006.174.01:12:52.46#ibcon#about to read 4, iclass 30, count 2 2006.174.01:12:52.46#ibcon#read 4, iclass 30, count 2 2006.174.01:12:52.46#ibcon#about to read 5, iclass 30, count 2 2006.174.01:12:52.46#ibcon#read 5, iclass 30, count 2 2006.174.01:12:52.46#ibcon#about to read 6, iclass 30, count 2 2006.174.01:12:52.46#ibcon#read 6, iclass 30, count 2 2006.174.01:12:52.46#ibcon#end of sib2, iclass 30, count 2 2006.174.01:12:52.46#ibcon#*after write, iclass 30, count 2 2006.174.01:12:52.46#ibcon#*before return 0, iclass 30, count 2 2006.174.01:12:52.46#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.174.01:12:52.46#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.174.01:12:52.46#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.174.01:12:52.46#ibcon#ireg 7 cls_cnt 0 2006.174.01:12:52.46#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.174.01:12:52.58#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.174.01:12:52.58#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.174.01:12:52.58#ibcon#enter wrdev, iclass 30, count 0 2006.174.01:12:52.58#ibcon#first serial, iclass 30, count 0 2006.174.01:12:52.58#ibcon#enter sib2, iclass 30, count 0 2006.174.01:12:52.58#ibcon#flushed, iclass 30, count 0 2006.174.01:12:52.58#ibcon#about to write, iclass 30, count 0 2006.174.01:12:52.58#ibcon#wrote, iclass 30, count 0 2006.174.01:12:52.58#ibcon#about to read 3, iclass 30, count 0 2006.174.01:12:52.60#ibcon#read 3, iclass 30, count 0 2006.174.01:12:52.60#ibcon#about to read 4, iclass 30, count 0 2006.174.01:12:52.60#ibcon#read 4, iclass 30, count 0 2006.174.01:12:52.60#ibcon#about to read 5, iclass 30, count 0 2006.174.01:12:52.60#ibcon#read 5, iclass 30, count 0 2006.174.01:12:52.60#ibcon#about to read 6, iclass 30, count 0 2006.174.01:12:52.60#ibcon#read 6, iclass 30, count 0 2006.174.01:12:52.60#ibcon#end of sib2, iclass 30, count 0 2006.174.01:12:52.60#ibcon#*mode == 0, iclass 30, count 0 2006.174.01:12:52.60#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.174.01:12:52.60#ibcon#[25=USB\r\n] 2006.174.01:12:52.60#ibcon#*before write, iclass 30, count 0 2006.174.01:12:52.60#ibcon#enter sib2, iclass 30, count 0 2006.174.01:12:52.60#ibcon#flushed, iclass 30, count 0 2006.174.01:12:52.60#ibcon#about to write, iclass 30, count 0 2006.174.01:12:52.60#ibcon#wrote, iclass 30, count 0 2006.174.01:12:52.60#ibcon#about to read 3, iclass 30, count 0 2006.174.01:12:52.63#ibcon#read 3, iclass 30, count 0 2006.174.01:12:52.63#ibcon#about to read 4, iclass 30, count 0 2006.174.01:12:52.63#ibcon#read 4, iclass 30, count 0 2006.174.01:12:52.63#ibcon#about to read 5, iclass 30, count 0 2006.174.01:12:52.63#ibcon#read 5, iclass 30, count 0 2006.174.01:12:52.63#ibcon#about to read 6, iclass 30, count 0 2006.174.01:12:52.63#ibcon#read 6, iclass 30, count 0 2006.174.01:12:52.63#ibcon#end of sib2, iclass 30, count 0 2006.174.01:12:52.63#ibcon#*after write, iclass 30, count 0 2006.174.01:12:52.63#ibcon#*before return 0, iclass 30, count 0 2006.174.01:12:52.63#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.174.01:12:52.63#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.174.01:12:52.63#ibcon#about to clear, iclass 30 cls_cnt 0 2006.174.01:12:52.63#ibcon#cleared, iclass 30 cls_cnt 0 2006.174.01:12:52.63$vck44/valo=5,734.99 2006.174.01:12:52.63#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.174.01:12:52.63#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.174.01:12:52.63#ibcon#ireg 17 cls_cnt 0 2006.174.01:12:52.63#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.174.01:12:52.63#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.174.01:12:52.63#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.174.01:12:52.63#ibcon#enter wrdev, iclass 32, count 0 2006.174.01:12:52.63#ibcon#first serial, iclass 32, count 0 2006.174.01:12:52.63#ibcon#enter sib2, iclass 32, count 0 2006.174.01:12:52.63#ibcon#flushed, iclass 32, count 0 2006.174.01:12:52.63#ibcon#about to write, iclass 32, count 0 2006.174.01:12:52.63#ibcon#wrote, iclass 32, count 0 2006.174.01:12:52.63#ibcon#about to read 3, iclass 32, count 0 2006.174.01:12:52.65#ibcon#read 3, iclass 32, count 0 2006.174.01:12:52.65#ibcon#about to read 4, iclass 32, count 0 2006.174.01:12:52.65#ibcon#read 4, iclass 32, count 0 2006.174.01:12:52.65#ibcon#about to read 5, iclass 32, count 0 2006.174.01:12:52.65#ibcon#read 5, iclass 32, count 0 2006.174.01:12:52.65#ibcon#about to read 6, iclass 32, count 0 2006.174.01:12:52.65#ibcon#read 6, iclass 32, count 0 2006.174.01:12:52.65#ibcon#end of sib2, iclass 32, count 0 2006.174.01:12:52.65#ibcon#*mode == 0, iclass 32, count 0 2006.174.01:12:52.65#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.174.01:12:52.65#ibcon#[26=FRQ=05,734.99\r\n] 2006.174.01:12:52.65#ibcon#*before write, iclass 32, count 0 2006.174.01:12:52.65#ibcon#enter sib2, iclass 32, count 0 2006.174.01:12:52.65#ibcon#flushed, iclass 32, count 0 2006.174.01:12:52.65#ibcon#about to write, iclass 32, count 0 2006.174.01:12:52.65#ibcon#wrote, iclass 32, count 0 2006.174.01:12:52.65#ibcon#about to read 3, iclass 32, count 0 2006.174.01:12:52.69#ibcon#read 3, iclass 32, count 0 2006.174.01:12:52.69#ibcon#about to read 4, iclass 32, count 0 2006.174.01:12:52.69#ibcon#read 4, iclass 32, count 0 2006.174.01:12:52.69#ibcon#about to read 5, iclass 32, count 0 2006.174.01:12:52.69#ibcon#read 5, iclass 32, count 0 2006.174.01:12:52.69#ibcon#about to read 6, iclass 32, count 0 2006.174.01:12:52.69#ibcon#read 6, iclass 32, count 0 2006.174.01:12:52.69#ibcon#end of sib2, iclass 32, count 0 2006.174.01:12:52.69#ibcon#*after write, iclass 32, count 0 2006.174.01:12:52.69#ibcon#*before return 0, iclass 32, count 0 2006.174.01:12:52.69#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.174.01:12:52.69#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.174.01:12:52.69#ibcon#about to clear, iclass 32 cls_cnt 0 2006.174.01:12:52.69#ibcon#cleared, iclass 32 cls_cnt 0 2006.174.01:12:52.69$vck44/va=5,4 2006.174.01:12:52.69#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.174.01:12:52.69#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.174.01:12:52.69#ibcon#ireg 11 cls_cnt 2 2006.174.01:12:52.69#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.174.01:12:52.75#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.174.01:12:52.75#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.174.01:12:52.75#ibcon#enter wrdev, iclass 34, count 2 2006.174.01:12:52.75#ibcon#first serial, iclass 34, count 2 2006.174.01:12:52.75#ibcon#enter sib2, iclass 34, count 2 2006.174.01:12:52.75#ibcon#flushed, iclass 34, count 2 2006.174.01:12:52.75#ibcon#about to write, iclass 34, count 2 2006.174.01:12:52.75#ibcon#wrote, iclass 34, count 2 2006.174.01:12:52.75#ibcon#about to read 3, iclass 34, count 2 2006.174.01:12:52.77#ibcon#read 3, iclass 34, count 2 2006.174.01:12:52.77#ibcon#about to read 4, iclass 34, count 2 2006.174.01:12:52.77#ibcon#read 4, iclass 34, count 2 2006.174.01:12:52.77#ibcon#about to read 5, iclass 34, count 2 2006.174.01:12:52.77#ibcon#read 5, iclass 34, count 2 2006.174.01:12:52.77#ibcon#about to read 6, iclass 34, count 2 2006.174.01:12:52.77#ibcon#read 6, iclass 34, count 2 2006.174.01:12:52.77#ibcon#end of sib2, iclass 34, count 2 2006.174.01:12:52.77#ibcon#*mode == 0, iclass 34, count 2 2006.174.01:12:52.77#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.174.01:12:52.77#ibcon#[25=AT05-04\r\n] 2006.174.01:12:52.77#ibcon#*before write, iclass 34, count 2 2006.174.01:12:52.77#ibcon#enter sib2, iclass 34, count 2 2006.174.01:12:52.77#ibcon#flushed, iclass 34, count 2 2006.174.01:12:52.77#ibcon#about to write, iclass 34, count 2 2006.174.01:12:52.77#ibcon#wrote, iclass 34, count 2 2006.174.01:12:52.77#ibcon#about to read 3, iclass 34, count 2 2006.174.01:12:52.80#ibcon#read 3, iclass 34, count 2 2006.174.01:12:52.80#ibcon#about to read 4, iclass 34, count 2 2006.174.01:12:52.80#ibcon#read 4, iclass 34, count 2 2006.174.01:12:52.80#ibcon#about to read 5, iclass 34, count 2 2006.174.01:12:52.80#ibcon#read 5, iclass 34, count 2 2006.174.01:12:52.80#ibcon#about to read 6, iclass 34, count 2 2006.174.01:12:52.80#ibcon#read 6, iclass 34, count 2 2006.174.01:12:52.80#ibcon#end of sib2, iclass 34, count 2 2006.174.01:12:52.80#ibcon#*after write, iclass 34, count 2 2006.174.01:12:52.80#ibcon#*before return 0, iclass 34, count 2 2006.174.01:12:52.80#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.174.01:12:52.80#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.174.01:12:52.80#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.174.01:12:52.80#ibcon#ireg 7 cls_cnt 0 2006.174.01:12:52.80#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.174.01:12:52.92#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.174.01:12:52.92#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.174.01:12:52.92#ibcon#enter wrdev, iclass 34, count 0 2006.174.01:12:52.92#ibcon#first serial, iclass 34, count 0 2006.174.01:12:52.92#ibcon#enter sib2, iclass 34, count 0 2006.174.01:12:52.92#ibcon#flushed, iclass 34, count 0 2006.174.01:12:52.92#ibcon#about to write, iclass 34, count 0 2006.174.01:12:52.92#ibcon#wrote, iclass 34, count 0 2006.174.01:12:52.92#ibcon#about to read 3, iclass 34, count 0 2006.174.01:12:52.94#ibcon#read 3, iclass 34, count 0 2006.174.01:12:52.94#ibcon#about to read 4, iclass 34, count 0 2006.174.01:12:52.94#ibcon#read 4, iclass 34, count 0 2006.174.01:12:52.94#ibcon#about to read 5, iclass 34, count 0 2006.174.01:12:52.94#ibcon#read 5, iclass 34, count 0 2006.174.01:12:52.94#ibcon#about to read 6, iclass 34, count 0 2006.174.01:12:52.94#ibcon#read 6, iclass 34, count 0 2006.174.01:12:52.94#ibcon#end of sib2, iclass 34, count 0 2006.174.01:12:52.94#ibcon#*mode == 0, iclass 34, count 0 2006.174.01:12:52.94#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.174.01:12:52.94#ibcon#[25=USB\r\n] 2006.174.01:12:52.94#ibcon#*before write, iclass 34, count 0 2006.174.01:12:52.94#ibcon#enter sib2, iclass 34, count 0 2006.174.01:12:52.94#ibcon#flushed, iclass 34, count 0 2006.174.01:12:52.94#ibcon#about to write, iclass 34, count 0 2006.174.01:12:52.94#ibcon#wrote, iclass 34, count 0 2006.174.01:12:52.94#ibcon#about to read 3, iclass 34, count 0 2006.174.01:12:52.97#ibcon#read 3, iclass 34, count 0 2006.174.01:12:52.97#ibcon#about to read 4, iclass 34, count 0 2006.174.01:12:52.97#ibcon#read 4, iclass 34, count 0 2006.174.01:12:52.97#ibcon#about to read 5, iclass 34, count 0 2006.174.01:12:52.97#ibcon#read 5, iclass 34, count 0 2006.174.01:12:52.97#ibcon#about to read 6, iclass 34, count 0 2006.174.01:12:52.97#ibcon#read 6, iclass 34, count 0 2006.174.01:12:52.97#ibcon#end of sib2, iclass 34, count 0 2006.174.01:12:52.97#ibcon#*after write, iclass 34, count 0 2006.174.01:12:52.97#ibcon#*before return 0, iclass 34, count 0 2006.174.01:12:52.97#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.174.01:12:52.97#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.174.01:12:52.97#ibcon#about to clear, iclass 34 cls_cnt 0 2006.174.01:12:52.97#ibcon#cleared, iclass 34 cls_cnt 0 2006.174.01:12:52.97$vck44/valo=6,814.99 2006.174.01:12:52.97#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.174.01:12:52.97#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.174.01:12:52.97#ibcon#ireg 17 cls_cnt 0 2006.174.01:12:52.97#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.174.01:12:52.97#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.174.01:12:52.97#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.174.01:12:52.97#ibcon#enter wrdev, iclass 36, count 0 2006.174.01:12:52.97#ibcon#first serial, iclass 36, count 0 2006.174.01:12:52.97#ibcon#enter sib2, iclass 36, count 0 2006.174.01:12:52.97#ibcon#flushed, iclass 36, count 0 2006.174.01:12:52.97#ibcon#about to write, iclass 36, count 0 2006.174.01:12:52.97#ibcon#wrote, iclass 36, count 0 2006.174.01:12:52.97#ibcon#about to read 3, iclass 36, count 0 2006.174.01:12:52.99#ibcon#read 3, iclass 36, count 0 2006.174.01:12:52.99#ibcon#about to read 4, iclass 36, count 0 2006.174.01:12:52.99#ibcon#read 4, iclass 36, count 0 2006.174.01:12:52.99#ibcon#about to read 5, iclass 36, count 0 2006.174.01:12:52.99#ibcon#read 5, iclass 36, count 0 2006.174.01:12:52.99#ibcon#about to read 6, iclass 36, count 0 2006.174.01:12:52.99#ibcon#read 6, iclass 36, count 0 2006.174.01:12:52.99#ibcon#end of sib2, iclass 36, count 0 2006.174.01:12:52.99#ibcon#*mode == 0, iclass 36, count 0 2006.174.01:12:52.99#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.174.01:12:52.99#ibcon#[26=FRQ=06,814.99\r\n] 2006.174.01:12:52.99#ibcon#*before write, iclass 36, count 0 2006.174.01:12:52.99#ibcon#enter sib2, iclass 36, count 0 2006.174.01:12:52.99#ibcon#flushed, iclass 36, count 0 2006.174.01:12:52.99#ibcon#about to write, iclass 36, count 0 2006.174.01:12:52.99#ibcon#wrote, iclass 36, count 0 2006.174.01:12:52.99#ibcon#about to read 3, iclass 36, count 0 2006.174.01:12:53.03#ibcon#read 3, iclass 36, count 0 2006.174.01:12:53.03#ibcon#about to read 4, iclass 36, count 0 2006.174.01:12:53.03#ibcon#read 4, iclass 36, count 0 2006.174.01:12:53.03#ibcon#about to read 5, iclass 36, count 0 2006.174.01:12:53.03#ibcon#read 5, iclass 36, count 0 2006.174.01:12:53.03#ibcon#about to read 6, iclass 36, count 0 2006.174.01:12:53.03#ibcon#read 6, iclass 36, count 0 2006.174.01:12:53.03#ibcon#end of sib2, iclass 36, count 0 2006.174.01:12:53.03#ibcon#*after write, iclass 36, count 0 2006.174.01:12:53.03#ibcon#*before return 0, iclass 36, count 0 2006.174.01:12:53.03#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.174.01:12:53.03#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.174.01:12:53.03#ibcon#about to clear, iclass 36 cls_cnt 0 2006.174.01:12:53.03#ibcon#cleared, iclass 36 cls_cnt 0 2006.174.01:12:53.03$vck44/va=6,3 2006.174.01:12:53.03#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.174.01:12:53.03#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.174.01:12:53.03#ibcon#ireg 11 cls_cnt 2 2006.174.01:12:53.03#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.174.01:12:53.09#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.174.01:12:53.09#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.174.01:12:53.09#ibcon#enter wrdev, iclass 38, count 2 2006.174.01:12:53.09#ibcon#first serial, iclass 38, count 2 2006.174.01:12:53.09#ibcon#enter sib2, iclass 38, count 2 2006.174.01:12:53.09#ibcon#flushed, iclass 38, count 2 2006.174.01:12:53.09#ibcon#about to write, iclass 38, count 2 2006.174.01:12:53.09#ibcon#wrote, iclass 38, count 2 2006.174.01:12:53.09#ibcon#about to read 3, iclass 38, count 2 2006.174.01:12:53.11#ibcon#read 3, iclass 38, count 2 2006.174.01:12:53.11#ibcon#about to read 4, iclass 38, count 2 2006.174.01:12:53.11#ibcon#read 4, iclass 38, count 2 2006.174.01:12:53.11#ibcon#about to read 5, iclass 38, count 2 2006.174.01:12:53.11#ibcon#read 5, iclass 38, count 2 2006.174.01:12:53.11#ibcon#about to read 6, iclass 38, count 2 2006.174.01:12:53.11#ibcon#read 6, iclass 38, count 2 2006.174.01:12:53.11#ibcon#end of sib2, iclass 38, count 2 2006.174.01:12:53.11#ibcon#*mode == 0, iclass 38, count 2 2006.174.01:12:53.11#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.174.01:12:53.11#ibcon#[25=AT06-03\r\n] 2006.174.01:12:53.11#ibcon#*before write, iclass 38, count 2 2006.174.01:12:53.11#ibcon#enter sib2, iclass 38, count 2 2006.174.01:12:53.11#ibcon#flushed, iclass 38, count 2 2006.174.01:12:53.11#ibcon#about to write, iclass 38, count 2 2006.174.01:12:53.11#ibcon#wrote, iclass 38, count 2 2006.174.01:12:53.11#ibcon#about to read 3, iclass 38, count 2 2006.174.01:12:53.14#ibcon#read 3, iclass 38, count 2 2006.174.01:12:53.14#ibcon#about to read 4, iclass 38, count 2 2006.174.01:12:53.14#ibcon#read 4, iclass 38, count 2 2006.174.01:12:53.14#ibcon#about to read 5, iclass 38, count 2 2006.174.01:12:53.14#ibcon#read 5, iclass 38, count 2 2006.174.01:12:53.14#ibcon#about to read 6, iclass 38, count 2 2006.174.01:12:53.14#ibcon#read 6, iclass 38, count 2 2006.174.01:12:53.14#ibcon#end of sib2, iclass 38, count 2 2006.174.01:12:53.14#ibcon#*after write, iclass 38, count 2 2006.174.01:12:53.14#ibcon#*before return 0, iclass 38, count 2 2006.174.01:12:53.14#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.174.01:12:53.14#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.174.01:12:53.14#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.174.01:12:53.14#ibcon#ireg 7 cls_cnt 0 2006.174.01:12:53.14#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.174.01:12:53.26#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.174.01:12:53.26#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.174.01:12:53.26#ibcon#enter wrdev, iclass 38, count 0 2006.174.01:12:53.26#ibcon#first serial, iclass 38, count 0 2006.174.01:12:53.26#ibcon#enter sib2, iclass 38, count 0 2006.174.01:12:53.26#ibcon#flushed, iclass 38, count 0 2006.174.01:12:53.26#ibcon#about to write, iclass 38, count 0 2006.174.01:12:53.26#ibcon#wrote, iclass 38, count 0 2006.174.01:12:53.26#ibcon#about to read 3, iclass 38, count 0 2006.174.01:12:53.28#ibcon#read 3, iclass 38, count 0 2006.174.01:12:53.28#ibcon#about to read 4, iclass 38, count 0 2006.174.01:12:53.28#ibcon#read 4, iclass 38, count 0 2006.174.01:12:53.28#ibcon#about to read 5, iclass 38, count 0 2006.174.01:12:53.28#ibcon#read 5, iclass 38, count 0 2006.174.01:12:53.28#ibcon#about to read 6, iclass 38, count 0 2006.174.01:12:53.28#ibcon#read 6, iclass 38, count 0 2006.174.01:12:53.28#ibcon#end of sib2, iclass 38, count 0 2006.174.01:12:53.28#ibcon#*mode == 0, iclass 38, count 0 2006.174.01:12:53.28#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.174.01:12:53.28#ibcon#[25=USB\r\n] 2006.174.01:12:53.28#ibcon#*before write, iclass 38, count 0 2006.174.01:12:53.28#ibcon#enter sib2, iclass 38, count 0 2006.174.01:12:53.28#ibcon#flushed, iclass 38, count 0 2006.174.01:12:53.28#ibcon#about to write, iclass 38, count 0 2006.174.01:12:53.28#ibcon#wrote, iclass 38, count 0 2006.174.01:12:53.28#ibcon#about to read 3, iclass 38, count 0 2006.174.01:12:53.31#ibcon#read 3, iclass 38, count 0 2006.174.01:12:53.31#ibcon#about to read 4, iclass 38, count 0 2006.174.01:12:53.31#ibcon#read 4, iclass 38, count 0 2006.174.01:12:53.31#ibcon#about to read 5, iclass 38, count 0 2006.174.01:12:53.31#ibcon#read 5, iclass 38, count 0 2006.174.01:12:53.31#ibcon#about to read 6, iclass 38, count 0 2006.174.01:12:53.31#ibcon#read 6, iclass 38, count 0 2006.174.01:12:53.31#ibcon#end of sib2, iclass 38, count 0 2006.174.01:12:53.31#ibcon#*after write, iclass 38, count 0 2006.174.01:12:53.31#ibcon#*before return 0, iclass 38, count 0 2006.174.01:12:53.31#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.174.01:12:53.31#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.174.01:12:53.31#ibcon#about to clear, iclass 38 cls_cnt 0 2006.174.01:12:53.31#ibcon#cleared, iclass 38 cls_cnt 0 2006.174.01:12:53.31$vck44/valo=7,864.99 2006.174.01:12:53.31#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.174.01:12:53.31#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.174.01:12:53.31#ibcon#ireg 17 cls_cnt 0 2006.174.01:12:53.31#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.174.01:12:53.31#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.174.01:12:53.31#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.174.01:12:53.31#ibcon#enter wrdev, iclass 40, count 0 2006.174.01:12:53.31#ibcon#first serial, iclass 40, count 0 2006.174.01:12:53.31#ibcon#enter sib2, iclass 40, count 0 2006.174.01:12:53.31#ibcon#flushed, iclass 40, count 0 2006.174.01:12:53.31#ibcon#about to write, iclass 40, count 0 2006.174.01:12:53.31#ibcon#wrote, iclass 40, count 0 2006.174.01:12:53.31#ibcon#about to read 3, iclass 40, count 0 2006.174.01:12:53.33#ibcon#read 3, iclass 40, count 0 2006.174.01:12:53.33#ibcon#about to read 4, iclass 40, count 0 2006.174.01:12:53.33#ibcon#read 4, iclass 40, count 0 2006.174.01:12:53.33#ibcon#about to read 5, iclass 40, count 0 2006.174.01:12:53.33#ibcon#read 5, iclass 40, count 0 2006.174.01:12:53.33#ibcon#about to read 6, iclass 40, count 0 2006.174.01:12:53.33#ibcon#read 6, iclass 40, count 0 2006.174.01:12:53.33#ibcon#end of sib2, iclass 40, count 0 2006.174.01:12:53.33#ibcon#*mode == 0, iclass 40, count 0 2006.174.01:12:53.33#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.174.01:12:53.33#ibcon#[26=FRQ=07,864.99\r\n] 2006.174.01:12:53.33#ibcon#*before write, iclass 40, count 0 2006.174.01:12:53.33#ibcon#enter sib2, iclass 40, count 0 2006.174.01:12:53.33#ibcon#flushed, iclass 40, count 0 2006.174.01:12:53.33#ibcon#about to write, iclass 40, count 0 2006.174.01:12:53.33#ibcon#wrote, iclass 40, count 0 2006.174.01:12:53.33#ibcon#about to read 3, iclass 40, count 0 2006.174.01:12:53.37#ibcon#read 3, iclass 40, count 0 2006.174.01:12:53.37#ibcon#about to read 4, iclass 40, count 0 2006.174.01:12:53.37#ibcon#read 4, iclass 40, count 0 2006.174.01:12:53.37#ibcon#about to read 5, iclass 40, count 0 2006.174.01:12:53.37#ibcon#read 5, iclass 40, count 0 2006.174.01:12:53.37#ibcon#about to read 6, iclass 40, count 0 2006.174.01:12:53.37#ibcon#read 6, iclass 40, count 0 2006.174.01:12:53.37#ibcon#end of sib2, iclass 40, count 0 2006.174.01:12:53.37#ibcon#*after write, iclass 40, count 0 2006.174.01:12:53.37#ibcon#*before return 0, iclass 40, count 0 2006.174.01:12:53.37#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.174.01:12:53.37#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.174.01:12:53.37#ibcon#about to clear, iclass 40 cls_cnt 0 2006.174.01:12:53.37#ibcon#cleared, iclass 40 cls_cnt 0 2006.174.01:12:53.37$vck44/va=7,4 2006.174.01:12:53.37#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.174.01:12:53.37#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.174.01:12:53.37#ibcon#ireg 11 cls_cnt 2 2006.174.01:12:53.37#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.174.01:12:53.43#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.174.01:12:53.43#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.174.01:12:53.43#ibcon#enter wrdev, iclass 4, count 2 2006.174.01:12:53.43#ibcon#first serial, iclass 4, count 2 2006.174.01:12:53.43#ibcon#enter sib2, iclass 4, count 2 2006.174.01:12:53.43#ibcon#flushed, iclass 4, count 2 2006.174.01:12:53.43#ibcon#about to write, iclass 4, count 2 2006.174.01:12:53.43#ibcon#wrote, iclass 4, count 2 2006.174.01:12:53.43#ibcon#about to read 3, iclass 4, count 2 2006.174.01:12:53.45#ibcon#read 3, iclass 4, count 2 2006.174.01:12:53.45#ibcon#about to read 4, iclass 4, count 2 2006.174.01:12:53.45#ibcon#read 4, iclass 4, count 2 2006.174.01:12:53.45#ibcon#about to read 5, iclass 4, count 2 2006.174.01:12:53.45#ibcon#read 5, iclass 4, count 2 2006.174.01:12:53.45#ibcon#about to read 6, iclass 4, count 2 2006.174.01:12:53.45#ibcon#read 6, iclass 4, count 2 2006.174.01:12:53.45#ibcon#end of sib2, iclass 4, count 2 2006.174.01:12:53.45#ibcon#*mode == 0, iclass 4, count 2 2006.174.01:12:53.45#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.174.01:12:53.45#ibcon#[25=AT07-04\r\n] 2006.174.01:12:53.45#ibcon#*before write, iclass 4, count 2 2006.174.01:12:53.45#ibcon#enter sib2, iclass 4, count 2 2006.174.01:12:53.45#ibcon#flushed, iclass 4, count 2 2006.174.01:12:53.45#ibcon#about to write, iclass 4, count 2 2006.174.01:12:53.45#ibcon#wrote, iclass 4, count 2 2006.174.01:12:53.45#ibcon#about to read 3, iclass 4, count 2 2006.174.01:12:53.48#ibcon#read 3, iclass 4, count 2 2006.174.01:12:53.48#ibcon#about to read 4, iclass 4, count 2 2006.174.01:12:53.48#ibcon#read 4, iclass 4, count 2 2006.174.01:12:53.48#ibcon#about to read 5, iclass 4, count 2 2006.174.01:12:53.48#ibcon#read 5, iclass 4, count 2 2006.174.01:12:53.48#ibcon#about to read 6, iclass 4, count 2 2006.174.01:12:53.48#ibcon#read 6, iclass 4, count 2 2006.174.01:12:53.48#ibcon#end of sib2, iclass 4, count 2 2006.174.01:12:53.48#ibcon#*after write, iclass 4, count 2 2006.174.01:12:53.48#ibcon#*before return 0, iclass 4, count 2 2006.174.01:12:53.48#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.174.01:12:53.48#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.174.01:12:53.48#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.174.01:12:53.48#ibcon#ireg 7 cls_cnt 0 2006.174.01:12:53.48#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.174.01:12:53.60#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.174.01:12:53.60#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.174.01:12:53.60#ibcon#enter wrdev, iclass 4, count 0 2006.174.01:12:53.60#ibcon#first serial, iclass 4, count 0 2006.174.01:12:53.60#ibcon#enter sib2, iclass 4, count 0 2006.174.01:12:53.60#ibcon#flushed, iclass 4, count 0 2006.174.01:12:53.60#ibcon#about to write, iclass 4, count 0 2006.174.01:12:53.60#ibcon#wrote, iclass 4, count 0 2006.174.01:12:53.60#ibcon#about to read 3, iclass 4, count 0 2006.174.01:12:53.62#ibcon#read 3, iclass 4, count 0 2006.174.01:12:53.62#ibcon#about to read 4, iclass 4, count 0 2006.174.01:12:53.62#ibcon#read 4, iclass 4, count 0 2006.174.01:12:53.62#ibcon#about to read 5, iclass 4, count 0 2006.174.01:12:53.62#ibcon#read 5, iclass 4, count 0 2006.174.01:12:53.62#ibcon#about to read 6, iclass 4, count 0 2006.174.01:12:53.62#ibcon#read 6, iclass 4, count 0 2006.174.01:12:53.62#ibcon#end of sib2, iclass 4, count 0 2006.174.01:12:53.62#ibcon#*mode == 0, iclass 4, count 0 2006.174.01:12:53.62#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.174.01:12:53.62#ibcon#[25=USB\r\n] 2006.174.01:12:53.62#ibcon#*before write, iclass 4, count 0 2006.174.01:12:53.62#ibcon#enter sib2, iclass 4, count 0 2006.174.01:12:53.62#ibcon#flushed, iclass 4, count 0 2006.174.01:12:53.62#ibcon#about to write, iclass 4, count 0 2006.174.01:12:53.62#ibcon#wrote, iclass 4, count 0 2006.174.01:12:53.62#ibcon#about to read 3, iclass 4, count 0 2006.174.01:12:53.65#ibcon#read 3, iclass 4, count 0 2006.174.01:12:53.65#ibcon#about to read 4, iclass 4, count 0 2006.174.01:12:53.65#ibcon#read 4, iclass 4, count 0 2006.174.01:12:53.65#ibcon#about to read 5, iclass 4, count 0 2006.174.01:12:53.65#ibcon#read 5, iclass 4, count 0 2006.174.01:12:53.65#ibcon#about to read 6, iclass 4, count 0 2006.174.01:12:53.65#ibcon#read 6, iclass 4, count 0 2006.174.01:12:53.65#ibcon#end of sib2, iclass 4, count 0 2006.174.01:12:53.65#ibcon#*after write, iclass 4, count 0 2006.174.01:12:53.65#ibcon#*before return 0, iclass 4, count 0 2006.174.01:12:53.65#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.174.01:12:53.65#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.174.01:12:53.65#ibcon#about to clear, iclass 4 cls_cnt 0 2006.174.01:12:53.65#ibcon#cleared, iclass 4 cls_cnt 0 2006.174.01:12:53.65$vck44/valo=8,884.99 2006.174.01:12:53.65#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.174.01:12:53.65#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.174.01:12:53.65#ibcon#ireg 17 cls_cnt 0 2006.174.01:12:53.65#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.174.01:12:53.65#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.174.01:12:53.65#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.174.01:12:53.65#ibcon#enter wrdev, iclass 6, count 0 2006.174.01:12:53.65#ibcon#first serial, iclass 6, count 0 2006.174.01:12:53.65#ibcon#enter sib2, iclass 6, count 0 2006.174.01:12:53.65#ibcon#flushed, iclass 6, count 0 2006.174.01:12:53.65#ibcon#about to write, iclass 6, count 0 2006.174.01:12:53.65#ibcon#wrote, iclass 6, count 0 2006.174.01:12:53.65#ibcon#about to read 3, iclass 6, count 0 2006.174.01:12:53.67#ibcon#read 3, iclass 6, count 0 2006.174.01:12:53.67#ibcon#about to read 4, iclass 6, count 0 2006.174.01:12:53.67#ibcon#read 4, iclass 6, count 0 2006.174.01:12:53.67#ibcon#about to read 5, iclass 6, count 0 2006.174.01:12:53.67#ibcon#read 5, iclass 6, count 0 2006.174.01:12:53.67#ibcon#about to read 6, iclass 6, count 0 2006.174.01:12:53.67#ibcon#read 6, iclass 6, count 0 2006.174.01:12:53.67#ibcon#end of sib2, iclass 6, count 0 2006.174.01:12:53.67#ibcon#*mode == 0, iclass 6, count 0 2006.174.01:12:53.67#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.174.01:12:53.67#ibcon#[26=FRQ=08,884.99\r\n] 2006.174.01:12:53.67#ibcon#*before write, iclass 6, count 0 2006.174.01:12:53.67#ibcon#enter sib2, iclass 6, count 0 2006.174.01:12:53.67#ibcon#flushed, iclass 6, count 0 2006.174.01:12:53.67#ibcon#about to write, iclass 6, count 0 2006.174.01:12:53.67#ibcon#wrote, iclass 6, count 0 2006.174.01:12:53.67#ibcon#about to read 3, iclass 6, count 0 2006.174.01:12:53.71#ibcon#read 3, iclass 6, count 0 2006.174.01:12:53.71#ibcon#about to read 4, iclass 6, count 0 2006.174.01:12:53.71#ibcon#read 4, iclass 6, count 0 2006.174.01:12:53.71#ibcon#about to read 5, iclass 6, count 0 2006.174.01:12:53.71#ibcon#read 5, iclass 6, count 0 2006.174.01:12:53.71#ibcon#about to read 6, iclass 6, count 0 2006.174.01:12:53.71#ibcon#read 6, iclass 6, count 0 2006.174.01:12:53.71#ibcon#end of sib2, iclass 6, count 0 2006.174.01:12:53.71#ibcon#*after write, iclass 6, count 0 2006.174.01:12:53.71#ibcon#*before return 0, iclass 6, count 0 2006.174.01:12:53.71#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.174.01:12:53.71#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.174.01:12:53.71#ibcon#about to clear, iclass 6 cls_cnt 0 2006.174.01:12:53.71#ibcon#cleared, iclass 6 cls_cnt 0 2006.174.01:12:53.71$vck44/va=8,4 2006.174.01:12:53.71#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.174.01:12:53.71#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.174.01:12:53.71#ibcon#ireg 11 cls_cnt 2 2006.174.01:12:53.71#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.174.01:12:53.77#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.174.01:12:53.77#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.174.01:12:53.77#ibcon#enter wrdev, iclass 10, count 2 2006.174.01:12:53.77#ibcon#first serial, iclass 10, count 2 2006.174.01:12:53.77#ibcon#enter sib2, iclass 10, count 2 2006.174.01:12:53.77#ibcon#flushed, iclass 10, count 2 2006.174.01:12:53.77#ibcon#about to write, iclass 10, count 2 2006.174.01:12:53.77#ibcon#wrote, iclass 10, count 2 2006.174.01:12:53.77#ibcon#about to read 3, iclass 10, count 2 2006.174.01:12:53.79#ibcon#read 3, iclass 10, count 2 2006.174.01:12:53.79#ibcon#about to read 4, iclass 10, count 2 2006.174.01:12:53.79#ibcon#read 4, iclass 10, count 2 2006.174.01:12:53.79#ibcon#about to read 5, iclass 10, count 2 2006.174.01:12:53.79#ibcon#read 5, iclass 10, count 2 2006.174.01:12:53.79#ibcon#about to read 6, iclass 10, count 2 2006.174.01:12:53.79#ibcon#read 6, iclass 10, count 2 2006.174.01:12:53.79#ibcon#end of sib2, iclass 10, count 2 2006.174.01:12:53.79#ibcon#*mode == 0, iclass 10, count 2 2006.174.01:12:53.79#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.174.01:12:53.79#ibcon#[25=AT08-04\r\n] 2006.174.01:12:53.79#ibcon#*before write, iclass 10, count 2 2006.174.01:12:53.79#ibcon#enter sib2, iclass 10, count 2 2006.174.01:12:53.79#ibcon#flushed, iclass 10, count 2 2006.174.01:12:53.79#ibcon#about to write, iclass 10, count 2 2006.174.01:12:53.79#ibcon#wrote, iclass 10, count 2 2006.174.01:12:53.79#ibcon#about to read 3, iclass 10, count 2 2006.174.01:12:53.82#ibcon#read 3, iclass 10, count 2 2006.174.01:12:53.82#ibcon#about to read 4, iclass 10, count 2 2006.174.01:12:53.82#ibcon#read 4, iclass 10, count 2 2006.174.01:12:53.82#ibcon#about to read 5, iclass 10, count 2 2006.174.01:12:53.82#ibcon#read 5, iclass 10, count 2 2006.174.01:12:53.82#ibcon#about to read 6, iclass 10, count 2 2006.174.01:12:53.82#ibcon#read 6, iclass 10, count 2 2006.174.01:12:53.82#ibcon#end of sib2, iclass 10, count 2 2006.174.01:12:53.82#ibcon#*after write, iclass 10, count 2 2006.174.01:12:53.82#ibcon#*before return 0, iclass 10, count 2 2006.174.01:12:53.82#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.174.01:12:53.82#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.174.01:12:53.82#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.174.01:12:53.82#ibcon#ireg 7 cls_cnt 0 2006.174.01:12:53.82#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.174.01:12:53.94#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.174.01:12:53.94#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.174.01:12:53.94#ibcon#enter wrdev, iclass 10, count 0 2006.174.01:12:53.94#ibcon#first serial, iclass 10, count 0 2006.174.01:12:53.94#ibcon#enter sib2, iclass 10, count 0 2006.174.01:12:53.94#ibcon#flushed, iclass 10, count 0 2006.174.01:12:53.94#ibcon#about to write, iclass 10, count 0 2006.174.01:12:53.94#ibcon#wrote, iclass 10, count 0 2006.174.01:12:53.94#ibcon#about to read 3, iclass 10, count 0 2006.174.01:12:53.96#ibcon#read 3, iclass 10, count 0 2006.174.01:12:53.96#ibcon#about to read 4, iclass 10, count 0 2006.174.01:12:53.96#ibcon#read 4, iclass 10, count 0 2006.174.01:12:53.96#ibcon#about to read 5, iclass 10, count 0 2006.174.01:12:53.96#ibcon#read 5, iclass 10, count 0 2006.174.01:12:53.96#ibcon#about to read 6, iclass 10, count 0 2006.174.01:12:53.96#ibcon#read 6, iclass 10, count 0 2006.174.01:12:53.96#ibcon#end of sib2, iclass 10, count 0 2006.174.01:12:53.96#ibcon#*mode == 0, iclass 10, count 0 2006.174.01:12:53.96#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.174.01:12:53.96#ibcon#[25=USB\r\n] 2006.174.01:12:53.96#ibcon#*before write, iclass 10, count 0 2006.174.01:12:53.96#ibcon#enter sib2, iclass 10, count 0 2006.174.01:12:53.96#ibcon#flushed, iclass 10, count 0 2006.174.01:12:53.96#ibcon#about to write, iclass 10, count 0 2006.174.01:12:53.96#ibcon#wrote, iclass 10, count 0 2006.174.01:12:53.96#ibcon#about to read 3, iclass 10, count 0 2006.174.01:12:53.99#ibcon#read 3, iclass 10, count 0 2006.174.01:12:53.99#ibcon#about to read 4, iclass 10, count 0 2006.174.01:12:53.99#ibcon#read 4, iclass 10, count 0 2006.174.01:12:53.99#ibcon#about to read 5, iclass 10, count 0 2006.174.01:12:53.99#ibcon#read 5, iclass 10, count 0 2006.174.01:12:53.99#ibcon#about to read 6, iclass 10, count 0 2006.174.01:12:53.99#ibcon#read 6, iclass 10, count 0 2006.174.01:12:53.99#ibcon#end of sib2, iclass 10, count 0 2006.174.01:12:53.99#ibcon#*after write, iclass 10, count 0 2006.174.01:12:53.99#ibcon#*before return 0, iclass 10, count 0 2006.174.01:12:53.99#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.174.01:12:53.99#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.174.01:12:53.99#ibcon#about to clear, iclass 10 cls_cnt 0 2006.174.01:12:53.99#ibcon#cleared, iclass 10 cls_cnt 0 2006.174.01:12:53.99$vck44/vblo=1,629.99 2006.174.01:12:53.99#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.174.01:12:53.99#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.174.01:12:53.99#ibcon#ireg 17 cls_cnt 0 2006.174.01:12:53.99#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.174.01:12:53.99#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.174.01:12:53.99#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.174.01:12:53.99#ibcon#enter wrdev, iclass 12, count 0 2006.174.01:12:53.99#ibcon#first serial, iclass 12, count 0 2006.174.01:12:53.99#ibcon#enter sib2, iclass 12, count 0 2006.174.01:12:53.99#ibcon#flushed, iclass 12, count 0 2006.174.01:12:53.99#ibcon#about to write, iclass 12, count 0 2006.174.01:12:53.99#ibcon#wrote, iclass 12, count 0 2006.174.01:12:53.99#ibcon#about to read 3, iclass 12, count 0 2006.174.01:12:54.01#ibcon#read 3, iclass 12, count 0 2006.174.01:12:54.01#ibcon#about to read 4, iclass 12, count 0 2006.174.01:12:54.01#ibcon#read 4, iclass 12, count 0 2006.174.01:12:54.01#ibcon#about to read 5, iclass 12, count 0 2006.174.01:12:54.01#ibcon#read 5, iclass 12, count 0 2006.174.01:12:54.01#ibcon#about to read 6, iclass 12, count 0 2006.174.01:12:54.01#ibcon#read 6, iclass 12, count 0 2006.174.01:12:54.01#ibcon#end of sib2, iclass 12, count 0 2006.174.01:12:54.01#ibcon#*mode == 0, iclass 12, count 0 2006.174.01:12:54.01#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.174.01:12:54.01#ibcon#[28=FRQ=01,629.99\r\n] 2006.174.01:12:54.01#ibcon#*before write, iclass 12, count 0 2006.174.01:12:54.01#ibcon#enter sib2, iclass 12, count 0 2006.174.01:12:54.01#ibcon#flushed, iclass 12, count 0 2006.174.01:12:54.01#ibcon#about to write, iclass 12, count 0 2006.174.01:12:54.01#ibcon#wrote, iclass 12, count 0 2006.174.01:12:54.01#ibcon#about to read 3, iclass 12, count 0 2006.174.01:12:54.05#ibcon#read 3, iclass 12, count 0 2006.174.01:12:54.05#ibcon#about to read 4, iclass 12, count 0 2006.174.01:12:54.05#ibcon#read 4, iclass 12, count 0 2006.174.01:12:54.05#ibcon#about to read 5, iclass 12, count 0 2006.174.01:12:54.05#ibcon#read 5, iclass 12, count 0 2006.174.01:12:54.05#ibcon#about to read 6, iclass 12, count 0 2006.174.01:12:54.05#ibcon#read 6, iclass 12, count 0 2006.174.01:12:54.05#ibcon#end of sib2, iclass 12, count 0 2006.174.01:12:54.05#ibcon#*after write, iclass 12, count 0 2006.174.01:12:54.05#ibcon#*before return 0, iclass 12, count 0 2006.174.01:12:54.05#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.174.01:12:54.05#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.174.01:12:54.05#ibcon#about to clear, iclass 12 cls_cnt 0 2006.174.01:12:54.05#ibcon#cleared, iclass 12 cls_cnt 0 2006.174.01:12:54.05$vck44/vb=1,4 2006.174.01:12:54.05#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.174.01:12:54.05#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.174.01:12:54.05#ibcon#ireg 11 cls_cnt 2 2006.174.01:12:54.05#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.174.01:12:54.05#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.174.01:12:54.05#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.174.01:12:54.05#ibcon#enter wrdev, iclass 14, count 2 2006.174.01:12:54.05#ibcon#first serial, iclass 14, count 2 2006.174.01:12:54.05#ibcon#enter sib2, iclass 14, count 2 2006.174.01:12:54.05#ibcon#flushed, iclass 14, count 2 2006.174.01:12:54.05#ibcon#about to write, iclass 14, count 2 2006.174.01:12:54.05#ibcon#wrote, iclass 14, count 2 2006.174.01:12:54.05#ibcon#about to read 3, iclass 14, count 2 2006.174.01:12:54.07#ibcon#read 3, iclass 14, count 2 2006.174.01:12:54.07#ibcon#about to read 4, iclass 14, count 2 2006.174.01:12:54.07#ibcon#read 4, iclass 14, count 2 2006.174.01:12:54.07#ibcon#about to read 5, iclass 14, count 2 2006.174.01:12:54.07#ibcon#read 5, iclass 14, count 2 2006.174.01:12:54.07#ibcon#about to read 6, iclass 14, count 2 2006.174.01:12:54.07#ibcon#read 6, iclass 14, count 2 2006.174.01:12:54.07#ibcon#end of sib2, iclass 14, count 2 2006.174.01:12:54.07#ibcon#*mode == 0, iclass 14, count 2 2006.174.01:12:54.07#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.174.01:12:54.07#ibcon#[27=AT01-04\r\n] 2006.174.01:12:54.07#ibcon#*before write, iclass 14, count 2 2006.174.01:12:54.07#ibcon#enter sib2, iclass 14, count 2 2006.174.01:12:54.07#ibcon#flushed, iclass 14, count 2 2006.174.01:12:54.07#ibcon#about to write, iclass 14, count 2 2006.174.01:12:54.07#ibcon#wrote, iclass 14, count 2 2006.174.01:12:54.07#ibcon#about to read 3, iclass 14, count 2 2006.174.01:12:54.10#ibcon#read 3, iclass 14, count 2 2006.174.01:12:54.10#ibcon#about to read 4, iclass 14, count 2 2006.174.01:12:54.10#ibcon#read 4, iclass 14, count 2 2006.174.01:12:54.10#ibcon#about to read 5, iclass 14, count 2 2006.174.01:12:54.10#ibcon#read 5, iclass 14, count 2 2006.174.01:12:54.10#ibcon#about to read 6, iclass 14, count 2 2006.174.01:12:54.10#ibcon#read 6, iclass 14, count 2 2006.174.01:12:54.10#ibcon#end of sib2, iclass 14, count 2 2006.174.01:12:54.10#ibcon#*after write, iclass 14, count 2 2006.174.01:12:54.10#ibcon#*before return 0, iclass 14, count 2 2006.174.01:12:54.10#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.174.01:12:54.10#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.174.01:12:54.10#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.174.01:12:54.10#ibcon#ireg 7 cls_cnt 0 2006.174.01:12:54.10#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.174.01:12:54.22#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.174.01:12:54.22#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.174.01:12:54.22#ibcon#enter wrdev, iclass 14, count 0 2006.174.01:12:54.22#ibcon#first serial, iclass 14, count 0 2006.174.01:12:54.22#ibcon#enter sib2, iclass 14, count 0 2006.174.01:12:54.22#ibcon#flushed, iclass 14, count 0 2006.174.01:12:54.22#ibcon#about to write, iclass 14, count 0 2006.174.01:12:54.22#ibcon#wrote, iclass 14, count 0 2006.174.01:12:54.22#ibcon#about to read 3, iclass 14, count 0 2006.174.01:12:54.24#ibcon#read 3, iclass 14, count 0 2006.174.01:12:54.24#ibcon#about to read 4, iclass 14, count 0 2006.174.01:12:54.24#ibcon#read 4, iclass 14, count 0 2006.174.01:12:54.24#ibcon#about to read 5, iclass 14, count 0 2006.174.01:12:54.24#ibcon#read 5, iclass 14, count 0 2006.174.01:12:54.24#ibcon#about to read 6, iclass 14, count 0 2006.174.01:12:54.24#ibcon#read 6, iclass 14, count 0 2006.174.01:12:54.24#ibcon#end of sib2, iclass 14, count 0 2006.174.01:12:54.24#ibcon#*mode == 0, iclass 14, count 0 2006.174.01:12:54.24#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.174.01:12:54.24#ibcon#[27=USB\r\n] 2006.174.01:12:54.24#ibcon#*before write, iclass 14, count 0 2006.174.01:12:54.24#ibcon#enter sib2, iclass 14, count 0 2006.174.01:12:54.24#ibcon#flushed, iclass 14, count 0 2006.174.01:12:54.24#ibcon#about to write, iclass 14, count 0 2006.174.01:12:54.24#ibcon#wrote, iclass 14, count 0 2006.174.01:12:54.24#ibcon#about to read 3, iclass 14, count 0 2006.174.01:12:54.27#ibcon#read 3, iclass 14, count 0 2006.174.01:12:54.27#ibcon#about to read 4, iclass 14, count 0 2006.174.01:12:54.27#ibcon#read 4, iclass 14, count 0 2006.174.01:12:54.27#ibcon#about to read 5, iclass 14, count 0 2006.174.01:12:54.27#ibcon#read 5, iclass 14, count 0 2006.174.01:12:54.27#ibcon#about to read 6, iclass 14, count 0 2006.174.01:12:54.27#ibcon#read 6, iclass 14, count 0 2006.174.01:12:54.27#ibcon#end of sib2, iclass 14, count 0 2006.174.01:12:54.27#ibcon#*after write, iclass 14, count 0 2006.174.01:12:54.27#ibcon#*before return 0, iclass 14, count 0 2006.174.01:12:54.27#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.174.01:12:54.27#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.174.01:12:54.27#ibcon#about to clear, iclass 14 cls_cnt 0 2006.174.01:12:54.27#ibcon#cleared, iclass 14 cls_cnt 0 2006.174.01:12:54.27$vck44/vblo=2,634.99 2006.174.01:12:54.27#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.174.01:12:54.27#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.174.01:12:54.27#ibcon#ireg 17 cls_cnt 0 2006.174.01:12:54.27#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.174.01:12:54.27#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.174.01:12:54.27#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.174.01:12:54.27#ibcon#enter wrdev, iclass 16, count 0 2006.174.01:12:54.27#ibcon#first serial, iclass 16, count 0 2006.174.01:12:54.27#ibcon#enter sib2, iclass 16, count 0 2006.174.01:12:54.27#ibcon#flushed, iclass 16, count 0 2006.174.01:12:54.27#ibcon#about to write, iclass 16, count 0 2006.174.01:12:54.27#ibcon#wrote, iclass 16, count 0 2006.174.01:12:54.27#ibcon#about to read 3, iclass 16, count 0 2006.174.01:12:54.29#ibcon#read 3, iclass 16, count 0 2006.174.01:12:54.29#ibcon#about to read 4, iclass 16, count 0 2006.174.01:12:54.29#ibcon#read 4, iclass 16, count 0 2006.174.01:12:54.29#ibcon#about to read 5, iclass 16, count 0 2006.174.01:12:54.29#ibcon#read 5, iclass 16, count 0 2006.174.01:12:54.29#ibcon#about to read 6, iclass 16, count 0 2006.174.01:12:54.29#ibcon#read 6, iclass 16, count 0 2006.174.01:12:54.29#ibcon#end of sib2, iclass 16, count 0 2006.174.01:12:54.29#ibcon#*mode == 0, iclass 16, count 0 2006.174.01:12:54.29#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.174.01:12:54.29#ibcon#[28=FRQ=02,634.99\r\n] 2006.174.01:12:54.29#ibcon#*before write, iclass 16, count 0 2006.174.01:12:54.29#ibcon#enter sib2, iclass 16, count 0 2006.174.01:12:54.29#ibcon#flushed, iclass 16, count 0 2006.174.01:12:54.29#ibcon#about to write, iclass 16, count 0 2006.174.01:12:54.29#ibcon#wrote, iclass 16, count 0 2006.174.01:12:54.29#ibcon#about to read 3, iclass 16, count 0 2006.174.01:12:54.33#ibcon#read 3, iclass 16, count 0 2006.174.01:12:54.33#ibcon#about to read 4, iclass 16, count 0 2006.174.01:12:54.33#ibcon#read 4, iclass 16, count 0 2006.174.01:12:54.33#ibcon#about to read 5, iclass 16, count 0 2006.174.01:12:54.33#ibcon#read 5, iclass 16, count 0 2006.174.01:12:54.33#ibcon#about to read 6, iclass 16, count 0 2006.174.01:12:54.33#ibcon#read 6, iclass 16, count 0 2006.174.01:12:54.33#ibcon#end of sib2, iclass 16, count 0 2006.174.01:12:54.33#ibcon#*after write, iclass 16, count 0 2006.174.01:12:54.33#ibcon#*before return 0, iclass 16, count 0 2006.174.01:12:54.33#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.174.01:12:54.33#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.174.01:12:54.33#ibcon#about to clear, iclass 16 cls_cnt 0 2006.174.01:12:54.33#ibcon#cleared, iclass 16 cls_cnt 0 2006.174.01:12:54.33$vck44/vb=2,4 2006.174.01:12:54.33#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.174.01:12:54.33#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.174.01:12:54.33#ibcon#ireg 11 cls_cnt 2 2006.174.01:12:54.33#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.174.01:12:54.39#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.174.01:12:54.39#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.174.01:12:54.39#ibcon#enter wrdev, iclass 18, count 2 2006.174.01:12:54.39#ibcon#first serial, iclass 18, count 2 2006.174.01:12:54.39#ibcon#enter sib2, iclass 18, count 2 2006.174.01:12:54.39#ibcon#flushed, iclass 18, count 2 2006.174.01:12:54.39#ibcon#about to write, iclass 18, count 2 2006.174.01:12:54.39#ibcon#wrote, iclass 18, count 2 2006.174.01:12:54.39#ibcon#about to read 3, iclass 18, count 2 2006.174.01:12:54.41#ibcon#read 3, iclass 18, count 2 2006.174.01:12:54.41#ibcon#about to read 4, iclass 18, count 2 2006.174.01:12:54.41#ibcon#read 4, iclass 18, count 2 2006.174.01:12:54.41#ibcon#about to read 5, iclass 18, count 2 2006.174.01:12:54.41#ibcon#read 5, iclass 18, count 2 2006.174.01:12:54.41#ibcon#about to read 6, iclass 18, count 2 2006.174.01:12:54.41#ibcon#read 6, iclass 18, count 2 2006.174.01:12:54.41#ibcon#end of sib2, iclass 18, count 2 2006.174.01:12:54.41#ibcon#*mode == 0, iclass 18, count 2 2006.174.01:12:54.41#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.174.01:12:54.41#ibcon#[27=AT02-04\r\n] 2006.174.01:12:54.41#ibcon#*before write, iclass 18, count 2 2006.174.01:12:54.41#ibcon#enter sib2, iclass 18, count 2 2006.174.01:12:54.41#ibcon#flushed, iclass 18, count 2 2006.174.01:12:54.41#ibcon#about to write, iclass 18, count 2 2006.174.01:12:54.41#ibcon#wrote, iclass 18, count 2 2006.174.01:12:54.41#ibcon#about to read 3, iclass 18, count 2 2006.174.01:12:54.44#ibcon#read 3, iclass 18, count 2 2006.174.01:12:54.44#ibcon#about to read 4, iclass 18, count 2 2006.174.01:12:54.44#ibcon#read 4, iclass 18, count 2 2006.174.01:12:54.44#ibcon#about to read 5, iclass 18, count 2 2006.174.01:12:54.44#ibcon#read 5, iclass 18, count 2 2006.174.01:12:54.44#ibcon#about to read 6, iclass 18, count 2 2006.174.01:12:54.44#ibcon#read 6, iclass 18, count 2 2006.174.01:12:54.44#ibcon#end of sib2, iclass 18, count 2 2006.174.01:12:54.44#ibcon#*after write, iclass 18, count 2 2006.174.01:12:54.44#ibcon#*before return 0, iclass 18, count 2 2006.174.01:12:54.44#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.174.01:12:54.44#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.174.01:12:54.44#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.174.01:12:54.44#ibcon#ireg 7 cls_cnt 0 2006.174.01:12:54.44#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.174.01:12:54.56#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.174.01:12:54.56#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.174.01:12:54.56#ibcon#enter wrdev, iclass 18, count 0 2006.174.01:12:54.56#ibcon#first serial, iclass 18, count 0 2006.174.01:12:54.56#ibcon#enter sib2, iclass 18, count 0 2006.174.01:12:54.56#ibcon#flushed, iclass 18, count 0 2006.174.01:12:54.56#ibcon#about to write, iclass 18, count 0 2006.174.01:12:54.56#ibcon#wrote, iclass 18, count 0 2006.174.01:12:54.56#ibcon#about to read 3, iclass 18, count 0 2006.174.01:12:54.58#ibcon#read 3, iclass 18, count 0 2006.174.01:12:54.58#ibcon#about to read 4, iclass 18, count 0 2006.174.01:12:54.58#ibcon#read 4, iclass 18, count 0 2006.174.01:12:54.58#ibcon#about to read 5, iclass 18, count 0 2006.174.01:12:54.58#ibcon#read 5, iclass 18, count 0 2006.174.01:12:54.58#ibcon#about to read 6, iclass 18, count 0 2006.174.01:12:54.58#ibcon#read 6, iclass 18, count 0 2006.174.01:12:54.58#ibcon#end of sib2, iclass 18, count 0 2006.174.01:12:54.58#ibcon#*mode == 0, iclass 18, count 0 2006.174.01:12:54.58#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.174.01:12:54.58#ibcon#[27=USB\r\n] 2006.174.01:12:54.58#ibcon#*before write, iclass 18, count 0 2006.174.01:12:54.58#ibcon#enter sib2, iclass 18, count 0 2006.174.01:12:54.58#ibcon#flushed, iclass 18, count 0 2006.174.01:12:54.58#ibcon#about to write, iclass 18, count 0 2006.174.01:12:54.58#ibcon#wrote, iclass 18, count 0 2006.174.01:12:54.58#ibcon#about to read 3, iclass 18, count 0 2006.174.01:12:54.61#ibcon#read 3, iclass 18, count 0 2006.174.01:12:54.61#ibcon#about to read 4, iclass 18, count 0 2006.174.01:12:54.61#ibcon#read 4, iclass 18, count 0 2006.174.01:12:54.61#ibcon#about to read 5, iclass 18, count 0 2006.174.01:12:54.61#ibcon#read 5, iclass 18, count 0 2006.174.01:12:54.61#ibcon#about to read 6, iclass 18, count 0 2006.174.01:12:54.61#ibcon#read 6, iclass 18, count 0 2006.174.01:12:54.61#ibcon#end of sib2, iclass 18, count 0 2006.174.01:12:54.61#ibcon#*after write, iclass 18, count 0 2006.174.01:12:54.61#ibcon#*before return 0, iclass 18, count 0 2006.174.01:12:54.61#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.174.01:12:54.61#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.174.01:12:54.61#ibcon#about to clear, iclass 18 cls_cnt 0 2006.174.01:12:54.61#ibcon#cleared, iclass 18 cls_cnt 0 2006.174.01:12:54.61$vck44/vblo=3,649.99 2006.174.01:12:54.61#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.174.01:12:54.61#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.174.01:12:54.61#ibcon#ireg 17 cls_cnt 0 2006.174.01:12:54.61#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.174.01:12:54.61#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.174.01:12:54.61#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.174.01:12:54.61#ibcon#enter wrdev, iclass 20, count 0 2006.174.01:12:54.61#ibcon#first serial, iclass 20, count 0 2006.174.01:12:54.61#ibcon#enter sib2, iclass 20, count 0 2006.174.01:12:54.61#ibcon#flushed, iclass 20, count 0 2006.174.01:12:54.61#ibcon#about to write, iclass 20, count 0 2006.174.01:12:54.61#ibcon#wrote, iclass 20, count 0 2006.174.01:12:54.61#ibcon#about to read 3, iclass 20, count 0 2006.174.01:12:54.63#ibcon#read 3, iclass 20, count 0 2006.174.01:12:54.63#ibcon#about to read 4, iclass 20, count 0 2006.174.01:12:54.63#ibcon#read 4, iclass 20, count 0 2006.174.01:12:54.63#ibcon#about to read 5, iclass 20, count 0 2006.174.01:12:54.63#ibcon#read 5, iclass 20, count 0 2006.174.01:12:54.63#ibcon#about to read 6, iclass 20, count 0 2006.174.01:12:54.63#ibcon#read 6, iclass 20, count 0 2006.174.01:12:54.63#ibcon#end of sib2, iclass 20, count 0 2006.174.01:12:54.63#ibcon#*mode == 0, iclass 20, count 0 2006.174.01:12:54.63#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.174.01:12:54.63#ibcon#[28=FRQ=03,649.99\r\n] 2006.174.01:12:54.63#ibcon#*before write, iclass 20, count 0 2006.174.01:12:54.63#ibcon#enter sib2, iclass 20, count 0 2006.174.01:12:54.63#ibcon#flushed, iclass 20, count 0 2006.174.01:12:54.63#ibcon#about to write, iclass 20, count 0 2006.174.01:12:54.63#ibcon#wrote, iclass 20, count 0 2006.174.01:12:54.63#ibcon#about to read 3, iclass 20, count 0 2006.174.01:12:54.67#ibcon#read 3, iclass 20, count 0 2006.174.01:12:54.67#ibcon#about to read 4, iclass 20, count 0 2006.174.01:12:54.67#ibcon#read 4, iclass 20, count 0 2006.174.01:12:54.67#ibcon#about to read 5, iclass 20, count 0 2006.174.01:12:54.67#ibcon#read 5, iclass 20, count 0 2006.174.01:12:54.67#ibcon#about to read 6, iclass 20, count 0 2006.174.01:12:54.67#ibcon#read 6, iclass 20, count 0 2006.174.01:12:54.67#ibcon#end of sib2, iclass 20, count 0 2006.174.01:12:54.67#ibcon#*after write, iclass 20, count 0 2006.174.01:12:54.67#ibcon#*before return 0, iclass 20, count 0 2006.174.01:12:54.67#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.174.01:12:54.67#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.174.01:12:54.67#ibcon#about to clear, iclass 20 cls_cnt 0 2006.174.01:12:54.67#ibcon#cleared, iclass 20 cls_cnt 0 2006.174.01:12:54.67$vck44/vb=3,4 2006.174.01:12:54.67#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.174.01:12:54.67#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.174.01:12:54.67#ibcon#ireg 11 cls_cnt 2 2006.174.01:12:54.67#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.174.01:12:54.73#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.174.01:12:54.73#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.174.01:12:54.73#ibcon#enter wrdev, iclass 22, count 2 2006.174.01:12:54.73#ibcon#first serial, iclass 22, count 2 2006.174.01:12:54.73#ibcon#enter sib2, iclass 22, count 2 2006.174.01:12:54.73#ibcon#flushed, iclass 22, count 2 2006.174.01:12:54.73#ibcon#about to write, iclass 22, count 2 2006.174.01:12:54.73#ibcon#wrote, iclass 22, count 2 2006.174.01:12:54.73#ibcon#about to read 3, iclass 22, count 2 2006.174.01:12:54.75#ibcon#read 3, iclass 22, count 2 2006.174.01:12:54.75#ibcon#about to read 4, iclass 22, count 2 2006.174.01:12:54.75#ibcon#read 4, iclass 22, count 2 2006.174.01:12:54.75#ibcon#about to read 5, iclass 22, count 2 2006.174.01:12:54.75#ibcon#read 5, iclass 22, count 2 2006.174.01:12:54.75#ibcon#about to read 6, iclass 22, count 2 2006.174.01:12:54.75#ibcon#read 6, iclass 22, count 2 2006.174.01:12:54.75#ibcon#end of sib2, iclass 22, count 2 2006.174.01:12:54.75#ibcon#*mode == 0, iclass 22, count 2 2006.174.01:12:54.75#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.174.01:12:54.75#ibcon#[27=AT03-04\r\n] 2006.174.01:12:54.75#ibcon#*before write, iclass 22, count 2 2006.174.01:12:54.75#ibcon#enter sib2, iclass 22, count 2 2006.174.01:12:54.75#ibcon#flushed, iclass 22, count 2 2006.174.01:12:54.75#ibcon#about to write, iclass 22, count 2 2006.174.01:12:54.75#ibcon#wrote, iclass 22, count 2 2006.174.01:12:54.75#ibcon#about to read 3, iclass 22, count 2 2006.174.01:12:54.78#ibcon#read 3, iclass 22, count 2 2006.174.01:12:54.78#ibcon#about to read 4, iclass 22, count 2 2006.174.01:12:54.78#ibcon#read 4, iclass 22, count 2 2006.174.01:12:54.78#ibcon#about to read 5, iclass 22, count 2 2006.174.01:12:54.78#ibcon#read 5, iclass 22, count 2 2006.174.01:12:54.78#ibcon#about to read 6, iclass 22, count 2 2006.174.01:12:54.78#ibcon#read 6, iclass 22, count 2 2006.174.01:12:54.78#ibcon#end of sib2, iclass 22, count 2 2006.174.01:12:54.78#ibcon#*after write, iclass 22, count 2 2006.174.01:12:54.78#ibcon#*before return 0, iclass 22, count 2 2006.174.01:12:54.78#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.174.01:12:54.78#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.174.01:12:54.78#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.174.01:12:54.78#ibcon#ireg 7 cls_cnt 0 2006.174.01:12:54.78#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.174.01:12:54.90#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.174.01:12:54.90#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.174.01:12:54.90#ibcon#enter wrdev, iclass 22, count 0 2006.174.01:12:54.90#ibcon#first serial, iclass 22, count 0 2006.174.01:12:54.90#ibcon#enter sib2, iclass 22, count 0 2006.174.01:12:54.90#ibcon#flushed, iclass 22, count 0 2006.174.01:12:54.90#ibcon#about to write, iclass 22, count 0 2006.174.01:12:54.90#ibcon#wrote, iclass 22, count 0 2006.174.01:12:54.90#ibcon#about to read 3, iclass 22, count 0 2006.174.01:12:54.92#ibcon#read 3, iclass 22, count 0 2006.174.01:12:54.92#ibcon#about to read 4, iclass 22, count 0 2006.174.01:12:54.92#ibcon#read 4, iclass 22, count 0 2006.174.01:12:54.92#ibcon#about to read 5, iclass 22, count 0 2006.174.01:12:54.92#ibcon#read 5, iclass 22, count 0 2006.174.01:12:54.92#ibcon#about to read 6, iclass 22, count 0 2006.174.01:12:54.92#ibcon#read 6, iclass 22, count 0 2006.174.01:12:54.92#ibcon#end of sib2, iclass 22, count 0 2006.174.01:12:54.92#ibcon#*mode == 0, iclass 22, count 0 2006.174.01:12:54.92#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.174.01:12:54.92#ibcon#[27=USB\r\n] 2006.174.01:12:54.92#ibcon#*before write, iclass 22, count 0 2006.174.01:12:54.92#ibcon#enter sib2, iclass 22, count 0 2006.174.01:12:54.92#ibcon#flushed, iclass 22, count 0 2006.174.01:12:54.92#ibcon#about to write, iclass 22, count 0 2006.174.01:12:54.92#ibcon#wrote, iclass 22, count 0 2006.174.01:12:54.92#ibcon#about to read 3, iclass 22, count 0 2006.174.01:12:54.95#ibcon#read 3, iclass 22, count 0 2006.174.01:12:54.95#ibcon#about to read 4, iclass 22, count 0 2006.174.01:12:54.95#ibcon#read 4, iclass 22, count 0 2006.174.01:12:54.95#ibcon#about to read 5, iclass 22, count 0 2006.174.01:12:54.95#ibcon#read 5, iclass 22, count 0 2006.174.01:12:54.95#ibcon#about to read 6, iclass 22, count 0 2006.174.01:12:54.95#ibcon#read 6, iclass 22, count 0 2006.174.01:12:54.95#ibcon#end of sib2, iclass 22, count 0 2006.174.01:12:54.95#ibcon#*after write, iclass 22, count 0 2006.174.01:12:54.95#ibcon#*before return 0, iclass 22, count 0 2006.174.01:12:54.95#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.174.01:12:54.95#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.174.01:12:54.95#ibcon#about to clear, iclass 22 cls_cnt 0 2006.174.01:12:54.95#ibcon#cleared, iclass 22 cls_cnt 0 2006.174.01:12:54.95$vck44/vblo=4,679.99 2006.174.01:12:54.95#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.174.01:12:54.95#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.174.01:12:54.95#ibcon#ireg 17 cls_cnt 0 2006.174.01:12:54.95#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.174.01:12:54.95#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.174.01:12:54.95#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.174.01:12:54.95#ibcon#enter wrdev, iclass 24, count 0 2006.174.01:12:54.95#ibcon#first serial, iclass 24, count 0 2006.174.01:12:54.95#ibcon#enter sib2, iclass 24, count 0 2006.174.01:12:54.95#ibcon#flushed, iclass 24, count 0 2006.174.01:12:54.95#ibcon#about to write, iclass 24, count 0 2006.174.01:12:54.95#ibcon#wrote, iclass 24, count 0 2006.174.01:12:54.95#ibcon#about to read 3, iclass 24, count 0 2006.174.01:12:54.97#ibcon#read 3, iclass 24, count 0 2006.174.01:12:54.97#ibcon#about to read 4, iclass 24, count 0 2006.174.01:12:54.97#ibcon#read 4, iclass 24, count 0 2006.174.01:12:54.97#ibcon#about to read 5, iclass 24, count 0 2006.174.01:12:54.97#ibcon#read 5, iclass 24, count 0 2006.174.01:12:54.97#ibcon#about to read 6, iclass 24, count 0 2006.174.01:12:54.97#ibcon#read 6, iclass 24, count 0 2006.174.01:12:54.97#ibcon#end of sib2, iclass 24, count 0 2006.174.01:12:54.97#ibcon#*mode == 0, iclass 24, count 0 2006.174.01:12:54.97#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.174.01:12:54.97#ibcon#[28=FRQ=04,679.99\r\n] 2006.174.01:12:54.97#ibcon#*before write, iclass 24, count 0 2006.174.01:12:54.97#ibcon#enter sib2, iclass 24, count 0 2006.174.01:12:54.97#ibcon#flushed, iclass 24, count 0 2006.174.01:12:54.97#ibcon#about to write, iclass 24, count 0 2006.174.01:12:54.97#ibcon#wrote, iclass 24, count 0 2006.174.01:12:54.97#ibcon#about to read 3, iclass 24, count 0 2006.174.01:12:55.01#ibcon#read 3, iclass 24, count 0 2006.174.01:12:55.01#ibcon#about to read 4, iclass 24, count 0 2006.174.01:12:55.01#ibcon#read 4, iclass 24, count 0 2006.174.01:12:55.01#ibcon#about to read 5, iclass 24, count 0 2006.174.01:12:55.01#ibcon#read 5, iclass 24, count 0 2006.174.01:12:55.01#ibcon#about to read 6, iclass 24, count 0 2006.174.01:12:55.01#ibcon#read 6, iclass 24, count 0 2006.174.01:12:55.01#ibcon#end of sib2, iclass 24, count 0 2006.174.01:12:55.01#ibcon#*after write, iclass 24, count 0 2006.174.01:12:55.01#ibcon#*before return 0, iclass 24, count 0 2006.174.01:12:55.01#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.174.01:12:55.01#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.174.01:12:55.01#ibcon#about to clear, iclass 24 cls_cnt 0 2006.174.01:12:55.01#ibcon#cleared, iclass 24 cls_cnt 0 2006.174.01:12:55.01$vck44/vb=4,4 2006.174.01:12:55.01#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.174.01:12:55.01#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.174.01:12:55.01#ibcon#ireg 11 cls_cnt 2 2006.174.01:12:55.01#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.174.01:12:55.07#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.174.01:12:55.07#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.174.01:12:55.07#ibcon#enter wrdev, iclass 26, count 2 2006.174.01:12:55.07#ibcon#first serial, iclass 26, count 2 2006.174.01:12:55.07#ibcon#enter sib2, iclass 26, count 2 2006.174.01:12:55.07#ibcon#flushed, iclass 26, count 2 2006.174.01:12:55.07#ibcon#about to write, iclass 26, count 2 2006.174.01:12:55.07#ibcon#wrote, iclass 26, count 2 2006.174.01:12:55.07#ibcon#about to read 3, iclass 26, count 2 2006.174.01:12:55.09#ibcon#read 3, iclass 26, count 2 2006.174.01:12:55.09#ibcon#about to read 4, iclass 26, count 2 2006.174.01:12:55.09#ibcon#read 4, iclass 26, count 2 2006.174.01:12:55.09#ibcon#about to read 5, iclass 26, count 2 2006.174.01:12:55.09#ibcon#read 5, iclass 26, count 2 2006.174.01:12:55.09#ibcon#about to read 6, iclass 26, count 2 2006.174.01:12:55.09#ibcon#read 6, iclass 26, count 2 2006.174.01:12:55.09#ibcon#end of sib2, iclass 26, count 2 2006.174.01:12:55.09#ibcon#*mode == 0, iclass 26, count 2 2006.174.01:12:55.09#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.174.01:12:55.09#ibcon#[27=AT04-04\r\n] 2006.174.01:12:55.09#ibcon#*before write, iclass 26, count 2 2006.174.01:12:55.09#ibcon#enter sib2, iclass 26, count 2 2006.174.01:12:55.09#ibcon#flushed, iclass 26, count 2 2006.174.01:12:55.09#ibcon#about to write, iclass 26, count 2 2006.174.01:12:55.09#ibcon#wrote, iclass 26, count 2 2006.174.01:12:55.09#ibcon#about to read 3, iclass 26, count 2 2006.174.01:12:55.12#ibcon#read 3, iclass 26, count 2 2006.174.01:12:55.12#ibcon#about to read 4, iclass 26, count 2 2006.174.01:12:55.12#ibcon#read 4, iclass 26, count 2 2006.174.01:12:55.12#ibcon#about to read 5, iclass 26, count 2 2006.174.01:12:55.12#ibcon#read 5, iclass 26, count 2 2006.174.01:12:55.12#ibcon#about to read 6, iclass 26, count 2 2006.174.01:12:55.12#ibcon#read 6, iclass 26, count 2 2006.174.01:12:55.12#ibcon#end of sib2, iclass 26, count 2 2006.174.01:12:55.12#ibcon#*after write, iclass 26, count 2 2006.174.01:12:55.12#ibcon#*before return 0, iclass 26, count 2 2006.174.01:12:55.12#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.174.01:12:55.12#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.174.01:12:55.12#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.174.01:12:55.12#ibcon#ireg 7 cls_cnt 0 2006.174.01:12:55.12#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.174.01:12:55.24#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.174.01:12:55.24#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.174.01:12:55.24#ibcon#enter wrdev, iclass 26, count 0 2006.174.01:12:55.24#ibcon#first serial, iclass 26, count 0 2006.174.01:12:55.24#ibcon#enter sib2, iclass 26, count 0 2006.174.01:12:55.24#ibcon#flushed, iclass 26, count 0 2006.174.01:12:55.24#ibcon#about to write, iclass 26, count 0 2006.174.01:12:55.24#ibcon#wrote, iclass 26, count 0 2006.174.01:12:55.24#ibcon#about to read 3, iclass 26, count 0 2006.174.01:12:55.26#ibcon#read 3, iclass 26, count 0 2006.174.01:12:55.26#ibcon#about to read 4, iclass 26, count 0 2006.174.01:12:55.26#ibcon#read 4, iclass 26, count 0 2006.174.01:12:55.26#ibcon#about to read 5, iclass 26, count 0 2006.174.01:12:55.26#ibcon#read 5, iclass 26, count 0 2006.174.01:12:55.26#ibcon#about to read 6, iclass 26, count 0 2006.174.01:12:55.26#ibcon#read 6, iclass 26, count 0 2006.174.01:12:55.26#ibcon#end of sib2, iclass 26, count 0 2006.174.01:12:55.26#ibcon#*mode == 0, iclass 26, count 0 2006.174.01:12:55.26#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.174.01:12:55.26#ibcon#[27=USB\r\n] 2006.174.01:12:55.26#ibcon#*before write, iclass 26, count 0 2006.174.01:12:55.26#ibcon#enter sib2, iclass 26, count 0 2006.174.01:12:55.26#ibcon#flushed, iclass 26, count 0 2006.174.01:12:55.26#ibcon#about to write, iclass 26, count 0 2006.174.01:12:55.26#ibcon#wrote, iclass 26, count 0 2006.174.01:12:55.26#ibcon#about to read 3, iclass 26, count 0 2006.174.01:12:55.29#ibcon#read 3, iclass 26, count 0 2006.174.01:12:55.29#ibcon#about to read 4, iclass 26, count 0 2006.174.01:12:55.29#ibcon#read 4, iclass 26, count 0 2006.174.01:12:55.29#ibcon#about to read 5, iclass 26, count 0 2006.174.01:12:55.29#ibcon#read 5, iclass 26, count 0 2006.174.01:12:55.29#ibcon#about to read 6, iclass 26, count 0 2006.174.01:12:55.29#ibcon#read 6, iclass 26, count 0 2006.174.01:12:55.29#ibcon#end of sib2, iclass 26, count 0 2006.174.01:12:55.29#ibcon#*after write, iclass 26, count 0 2006.174.01:12:55.29#ibcon#*before return 0, iclass 26, count 0 2006.174.01:12:55.29#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.174.01:12:55.29#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.174.01:12:55.29#ibcon#about to clear, iclass 26 cls_cnt 0 2006.174.01:12:55.29#ibcon#cleared, iclass 26 cls_cnt 0 2006.174.01:12:55.29$vck44/vblo=5,709.99 2006.174.01:12:55.29#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.174.01:12:55.29#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.174.01:12:55.29#ibcon#ireg 17 cls_cnt 0 2006.174.01:12:55.29#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.174.01:12:55.29#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.174.01:12:55.29#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.174.01:12:55.29#ibcon#enter wrdev, iclass 28, count 0 2006.174.01:12:55.29#ibcon#first serial, iclass 28, count 0 2006.174.01:12:55.29#ibcon#enter sib2, iclass 28, count 0 2006.174.01:12:55.29#ibcon#flushed, iclass 28, count 0 2006.174.01:12:55.29#ibcon#about to write, iclass 28, count 0 2006.174.01:12:55.29#ibcon#wrote, iclass 28, count 0 2006.174.01:12:55.29#ibcon#about to read 3, iclass 28, count 0 2006.174.01:12:55.31#ibcon#read 3, iclass 28, count 0 2006.174.01:12:55.31#ibcon#about to read 4, iclass 28, count 0 2006.174.01:12:55.31#ibcon#read 4, iclass 28, count 0 2006.174.01:12:55.31#ibcon#about to read 5, iclass 28, count 0 2006.174.01:12:55.31#ibcon#read 5, iclass 28, count 0 2006.174.01:12:55.31#ibcon#about to read 6, iclass 28, count 0 2006.174.01:12:55.31#ibcon#read 6, iclass 28, count 0 2006.174.01:12:55.31#ibcon#end of sib2, iclass 28, count 0 2006.174.01:12:55.31#ibcon#*mode == 0, iclass 28, count 0 2006.174.01:12:55.31#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.174.01:12:55.31#ibcon#[28=FRQ=05,709.99\r\n] 2006.174.01:12:55.31#ibcon#*before write, iclass 28, count 0 2006.174.01:12:55.31#ibcon#enter sib2, iclass 28, count 0 2006.174.01:12:55.31#ibcon#flushed, iclass 28, count 0 2006.174.01:12:55.31#ibcon#about to write, iclass 28, count 0 2006.174.01:12:55.31#ibcon#wrote, iclass 28, count 0 2006.174.01:12:55.31#ibcon#about to read 3, iclass 28, count 0 2006.174.01:12:55.35#ibcon#read 3, iclass 28, count 0 2006.174.01:12:55.35#ibcon#about to read 4, iclass 28, count 0 2006.174.01:12:55.35#ibcon#read 4, iclass 28, count 0 2006.174.01:12:55.35#ibcon#about to read 5, iclass 28, count 0 2006.174.01:12:55.35#ibcon#read 5, iclass 28, count 0 2006.174.01:12:55.35#ibcon#about to read 6, iclass 28, count 0 2006.174.01:12:55.35#ibcon#read 6, iclass 28, count 0 2006.174.01:12:55.35#ibcon#end of sib2, iclass 28, count 0 2006.174.01:12:55.35#ibcon#*after write, iclass 28, count 0 2006.174.01:12:55.35#ibcon#*before return 0, iclass 28, count 0 2006.174.01:12:55.35#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.174.01:12:55.35#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.174.01:12:55.35#ibcon#about to clear, iclass 28 cls_cnt 0 2006.174.01:12:55.35#ibcon#cleared, iclass 28 cls_cnt 0 2006.174.01:12:55.35$vck44/vb=5,4 2006.174.01:12:55.35#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.174.01:12:55.35#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.174.01:12:55.35#ibcon#ireg 11 cls_cnt 2 2006.174.01:12:55.35#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.174.01:12:55.41#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.174.01:12:55.41#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.174.01:12:55.41#ibcon#enter wrdev, iclass 30, count 2 2006.174.01:12:55.41#ibcon#first serial, iclass 30, count 2 2006.174.01:12:55.41#ibcon#enter sib2, iclass 30, count 2 2006.174.01:12:55.41#ibcon#flushed, iclass 30, count 2 2006.174.01:12:55.41#ibcon#about to write, iclass 30, count 2 2006.174.01:12:55.41#ibcon#wrote, iclass 30, count 2 2006.174.01:12:55.41#ibcon#about to read 3, iclass 30, count 2 2006.174.01:12:55.43#ibcon#read 3, iclass 30, count 2 2006.174.01:12:55.43#ibcon#about to read 4, iclass 30, count 2 2006.174.01:12:55.43#ibcon#read 4, iclass 30, count 2 2006.174.01:12:55.43#ibcon#about to read 5, iclass 30, count 2 2006.174.01:12:55.43#ibcon#read 5, iclass 30, count 2 2006.174.01:12:55.43#ibcon#about to read 6, iclass 30, count 2 2006.174.01:12:55.43#ibcon#read 6, iclass 30, count 2 2006.174.01:12:55.43#ibcon#end of sib2, iclass 30, count 2 2006.174.01:12:55.43#ibcon#*mode == 0, iclass 30, count 2 2006.174.01:12:55.43#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.174.01:12:55.43#ibcon#[27=AT05-04\r\n] 2006.174.01:12:55.43#ibcon#*before write, iclass 30, count 2 2006.174.01:12:55.43#ibcon#enter sib2, iclass 30, count 2 2006.174.01:12:55.43#ibcon#flushed, iclass 30, count 2 2006.174.01:12:55.43#ibcon#about to write, iclass 30, count 2 2006.174.01:12:55.43#ibcon#wrote, iclass 30, count 2 2006.174.01:12:55.43#ibcon#about to read 3, iclass 30, count 2 2006.174.01:12:55.46#ibcon#read 3, iclass 30, count 2 2006.174.01:12:55.46#ibcon#about to read 4, iclass 30, count 2 2006.174.01:12:55.46#ibcon#read 4, iclass 30, count 2 2006.174.01:12:55.46#ibcon#about to read 5, iclass 30, count 2 2006.174.01:12:55.46#ibcon#read 5, iclass 30, count 2 2006.174.01:12:55.46#ibcon#about to read 6, iclass 30, count 2 2006.174.01:12:55.46#ibcon#read 6, iclass 30, count 2 2006.174.01:12:55.46#ibcon#end of sib2, iclass 30, count 2 2006.174.01:12:55.46#ibcon#*after write, iclass 30, count 2 2006.174.01:12:55.46#ibcon#*before return 0, iclass 30, count 2 2006.174.01:12:55.46#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.174.01:12:55.46#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.174.01:12:55.46#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.174.01:12:55.46#ibcon#ireg 7 cls_cnt 0 2006.174.01:12:55.46#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.174.01:12:55.58#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.174.01:12:55.58#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.174.01:12:55.58#ibcon#enter wrdev, iclass 30, count 0 2006.174.01:12:55.58#ibcon#first serial, iclass 30, count 0 2006.174.01:12:55.58#ibcon#enter sib2, iclass 30, count 0 2006.174.01:12:55.58#ibcon#flushed, iclass 30, count 0 2006.174.01:12:55.58#ibcon#about to write, iclass 30, count 0 2006.174.01:12:55.58#ibcon#wrote, iclass 30, count 0 2006.174.01:12:55.58#ibcon#about to read 3, iclass 30, count 0 2006.174.01:12:55.60#ibcon#read 3, iclass 30, count 0 2006.174.01:12:55.60#ibcon#about to read 4, iclass 30, count 0 2006.174.01:12:55.60#ibcon#read 4, iclass 30, count 0 2006.174.01:12:55.60#ibcon#about to read 5, iclass 30, count 0 2006.174.01:12:55.60#ibcon#read 5, iclass 30, count 0 2006.174.01:12:55.60#ibcon#about to read 6, iclass 30, count 0 2006.174.01:12:55.60#ibcon#read 6, iclass 30, count 0 2006.174.01:12:55.60#ibcon#end of sib2, iclass 30, count 0 2006.174.01:12:55.60#ibcon#*mode == 0, iclass 30, count 0 2006.174.01:12:55.60#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.174.01:12:55.60#ibcon#[27=USB\r\n] 2006.174.01:12:55.60#ibcon#*before write, iclass 30, count 0 2006.174.01:12:55.60#ibcon#enter sib2, iclass 30, count 0 2006.174.01:12:55.60#ibcon#flushed, iclass 30, count 0 2006.174.01:12:55.60#ibcon#about to write, iclass 30, count 0 2006.174.01:12:55.60#ibcon#wrote, iclass 30, count 0 2006.174.01:12:55.60#ibcon#about to read 3, iclass 30, count 0 2006.174.01:12:55.63#ibcon#read 3, iclass 30, count 0 2006.174.01:12:55.63#ibcon#about to read 4, iclass 30, count 0 2006.174.01:12:55.63#ibcon#read 4, iclass 30, count 0 2006.174.01:12:55.63#ibcon#about to read 5, iclass 30, count 0 2006.174.01:12:55.63#ibcon#read 5, iclass 30, count 0 2006.174.01:12:55.63#ibcon#about to read 6, iclass 30, count 0 2006.174.01:12:55.63#ibcon#read 6, iclass 30, count 0 2006.174.01:12:55.63#ibcon#end of sib2, iclass 30, count 0 2006.174.01:12:55.63#ibcon#*after write, iclass 30, count 0 2006.174.01:12:55.63#ibcon#*before return 0, iclass 30, count 0 2006.174.01:12:55.63#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.174.01:12:55.63#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.174.01:12:55.63#ibcon#about to clear, iclass 30 cls_cnt 0 2006.174.01:12:55.63#ibcon#cleared, iclass 30 cls_cnt 0 2006.174.01:12:55.63$vck44/vblo=6,719.99 2006.174.01:12:55.63#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.174.01:12:55.63#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.174.01:12:55.63#ibcon#ireg 17 cls_cnt 0 2006.174.01:12:55.63#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.174.01:12:55.63#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.174.01:12:55.63#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.174.01:12:55.63#ibcon#enter wrdev, iclass 32, count 0 2006.174.01:12:55.63#ibcon#first serial, iclass 32, count 0 2006.174.01:12:55.63#ibcon#enter sib2, iclass 32, count 0 2006.174.01:12:55.63#ibcon#flushed, iclass 32, count 0 2006.174.01:12:55.63#ibcon#about to write, iclass 32, count 0 2006.174.01:12:55.63#ibcon#wrote, iclass 32, count 0 2006.174.01:12:55.63#ibcon#about to read 3, iclass 32, count 0 2006.174.01:12:55.65#ibcon#read 3, iclass 32, count 0 2006.174.01:12:55.65#ibcon#about to read 4, iclass 32, count 0 2006.174.01:12:55.65#ibcon#read 4, iclass 32, count 0 2006.174.01:12:55.65#ibcon#about to read 5, iclass 32, count 0 2006.174.01:12:55.65#ibcon#read 5, iclass 32, count 0 2006.174.01:12:55.65#ibcon#about to read 6, iclass 32, count 0 2006.174.01:12:55.65#ibcon#read 6, iclass 32, count 0 2006.174.01:12:55.65#ibcon#end of sib2, iclass 32, count 0 2006.174.01:12:55.65#ibcon#*mode == 0, iclass 32, count 0 2006.174.01:12:55.65#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.174.01:12:55.65#ibcon#[28=FRQ=06,719.99\r\n] 2006.174.01:12:55.65#ibcon#*before write, iclass 32, count 0 2006.174.01:12:55.65#ibcon#enter sib2, iclass 32, count 0 2006.174.01:12:55.65#ibcon#flushed, iclass 32, count 0 2006.174.01:12:55.65#ibcon#about to write, iclass 32, count 0 2006.174.01:12:55.65#ibcon#wrote, iclass 32, count 0 2006.174.01:12:55.65#ibcon#about to read 3, iclass 32, count 0 2006.174.01:12:55.69#ibcon#read 3, iclass 32, count 0 2006.174.01:12:55.69#ibcon#about to read 4, iclass 32, count 0 2006.174.01:12:55.69#ibcon#read 4, iclass 32, count 0 2006.174.01:12:55.69#ibcon#about to read 5, iclass 32, count 0 2006.174.01:12:55.69#ibcon#read 5, iclass 32, count 0 2006.174.01:12:55.69#ibcon#about to read 6, iclass 32, count 0 2006.174.01:12:55.69#ibcon#read 6, iclass 32, count 0 2006.174.01:12:55.69#ibcon#end of sib2, iclass 32, count 0 2006.174.01:12:55.69#ibcon#*after write, iclass 32, count 0 2006.174.01:12:55.69#ibcon#*before return 0, iclass 32, count 0 2006.174.01:12:55.69#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.174.01:12:55.69#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.174.01:12:55.69#ibcon#about to clear, iclass 32 cls_cnt 0 2006.174.01:12:55.69#ibcon#cleared, iclass 32 cls_cnt 0 2006.174.01:12:55.69$vck44/vb=6,4 2006.174.01:12:55.69#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.174.01:12:55.69#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.174.01:12:55.69#ibcon#ireg 11 cls_cnt 2 2006.174.01:12:55.69#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.174.01:12:55.75#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.174.01:12:55.75#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.174.01:12:55.75#ibcon#enter wrdev, iclass 34, count 2 2006.174.01:12:55.75#ibcon#first serial, iclass 34, count 2 2006.174.01:12:55.75#ibcon#enter sib2, iclass 34, count 2 2006.174.01:12:55.75#ibcon#flushed, iclass 34, count 2 2006.174.01:12:55.75#ibcon#about to write, iclass 34, count 2 2006.174.01:12:55.75#ibcon#wrote, iclass 34, count 2 2006.174.01:12:55.75#ibcon#about to read 3, iclass 34, count 2 2006.174.01:12:55.77#ibcon#read 3, iclass 34, count 2 2006.174.01:12:55.77#ibcon#about to read 4, iclass 34, count 2 2006.174.01:12:55.77#ibcon#read 4, iclass 34, count 2 2006.174.01:12:55.77#ibcon#about to read 5, iclass 34, count 2 2006.174.01:12:55.77#ibcon#read 5, iclass 34, count 2 2006.174.01:12:55.77#ibcon#about to read 6, iclass 34, count 2 2006.174.01:12:55.77#ibcon#read 6, iclass 34, count 2 2006.174.01:12:55.77#ibcon#end of sib2, iclass 34, count 2 2006.174.01:12:55.77#ibcon#*mode == 0, iclass 34, count 2 2006.174.01:12:55.77#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.174.01:12:55.77#ibcon#[27=AT06-04\r\n] 2006.174.01:12:55.77#ibcon#*before write, iclass 34, count 2 2006.174.01:12:55.77#ibcon#enter sib2, iclass 34, count 2 2006.174.01:12:55.77#ibcon#flushed, iclass 34, count 2 2006.174.01:12:55.77#ibcon#about to write, iclass 34, count 2 2006.174.01:12:55.77#ibcon#wrote, iclass 34, count 2 2006.174.01:12:55.77#ibcon#about to read 3, iclass 34, count 2 2006.174.01:12:55.80#ibcon#read 3, iclass 34, count 2 2006.174.01:12:55.80#ibcon#about to read 4, iclass 34, count 2 2006.174.01:12:55.80#ibcon#read 4, iclass 34, count 2 2006.174.01:12:55.80#ibcon#about to read 5, iclass 34, count 2 2006.174.01:12:55.80#ibcon#read 5, iclass 34, count 2 2006.174.01:12:55.80#ibcon#about to read 6, iclass 34, count 2 2006.174.01:12:55.80#ibcon#read 6, iclass 34, count 2 2006.174.01:12:55.80#ibcon#end of sib2, iclass 34, count 2 2006.174.01:12:55.80#ibcon#*after write, iclass 34, count 2 2006.174.01:12:55.80#ibcon#*before return 0, iclass 34, count 2 2006.174.01:12:55.80#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.174.01:12:55.80#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.174.01:12:55.80#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.174.01:12:55.80#ibcon#ireg 7 cls_cnt 0 2006.174.01:12:55.80#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.174.01:12:55.92#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.174.01:12:55.92#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.174.01:12:55.92#ibcon#enter wrdev, iclass 34, count 0 2006.174.01:12:55.92#ibcon#first serial, iclass 34, count 0 2006.174.01:12:55.92#ibcon#enter sib2, iclass 34, count 0 2006.174.01:12:55.92#ibcon#flushed, iclass 34, count 0 2006.174.01:12:55.92#ibcon#about to write, iclass 34, count 0 2006.174.01:12:55.92#ibcon#wrote, iclass 34, count 0 2006.174.01:12:55.92#ibcon#about to read 3, iclass 34, count 0 2006.174.01:12:55.94#ibcon#read 3, iclass 34, count 0 2006.174.01:12:55.94#ibcon#about to read 4, iclass 34, count 0 2006.174.01:12:55.94#ibcon#read 4, iclass 34, count 0 2006.174.01:12:55.94#ibcon#about to read 5, iclass 34, count 0 2006.174.01:12:55.94#ibcon#read 5, iclass 34, count 0 2006.174.01:12:55.94#ibcon#about to read 6, iclass 34, count 0 2006.174.01:12:55.94#ibcon#read 6, iclass 34, count 0 2006.174.01:12:55.94#ibcon#end of sib2, iclass 34, count 0 2006.174.01:12:55.94#ibcon#*mode == 0, iclass 34, count 0 2006.174.01:12:55.94#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.174.01:12:55.94#ibcon#[27=USB\r\n] 2006.174.01:12:55.94#ibcon#*before write, iclass 34, count 0 2006.174.01:12:55.94#ibcon#enter sib2, iclass 34, count 0 2006.174.01:12:55.94#ibcon#flushed, iclass 34, count 0 2006.174.01:12:55.94#ibcon#about to write, iclass 34, count 0 2006.174.01:12:55.94#ibcon#wrote, iclass 34, count 0 2006.174.01:12:55.94#ibcon#about to read 3, iclass 34, count 0 2006.174.01:12:55.97#ibcon#read 3, iclass 34, count 0 2006.174.01:12:55.97#ibcon#about to read 4, iclass 34, count 0 2006.174.01:12:55.97#ibcon#read 4, iclass 34, count 0 2006.174.01:12:55.97#ibcon#about to read 5, iclass 34, count 0 2006.174.01:12:55.97#ibcon#read 5, iclass 34, count 0 2006.174.01:12:55.97#ibcon#about to read 6, iclass 34, count 0 2006.174.01:12:55.97#ibcon#read 6, iclass 34, count 0 2006.174.01:12:55.97#ibcon#end of sib2, iclass 34, count 0 2006.174.01:12:55.97#ibcon#*after write, iclass 34, count 0 2006.174.01:12:55.97#ibcon#*before return 0, iclass 34, count 0 2006.174.01:12:55.97#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.174.01:12:55.97#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.174.01:12:55.97#ibcon#about to clear, iclass 34 cls_cnt 0 2006.174.01:12:55.97#ibcon#cleared, iclass 34 cls_cnt 0 2006.174.01:12:55.97$vck44/vblo=7,734.99 2006.174.01:12:55.97#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.174.01:12:55.97#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.174.01:12:55.97#ibcon#ireg 17 cls_cnt 0 2006.174.01:12:55.97#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.174.01:12:55.97#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.174.01:12:55.97#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.174.01:12:55.97#ibcon#enter wrdev, iclass 36, count 0 2006.174.01:12:55.97#ibcon#first serial, iclass 36, count 0 2006.174.01:12:55.97#ibcon#enter sib2, iclass 36, count 0 2006.174.01:12:55.97#ibcon#flushed, iclass 36, count 0 2006.174.01:12:55.97#ibcon#about to write, iclass 36, count 0 2006.174.01:12:55.97#ibcon#wrote, iclass 36, count 0 2006.174.01:12:55.97#ibcon#about to read 3, iclass 36, count 0 2006.174.01:12:55.99#ibcon#read 3, iclass 36, count 0 2006.174.01:12:55.99#ibcon#about to read 4, iclass 36, count 0 2006.174.01:12:55.99#ibcon#read 4, iclass 36, count 0 2006.174.01:12:55.99#ibcon#about to read 5, iclass 36, count 0 2006.174.01:12:55.99#ibcon#read 5, iclass 36, count 0 2006.174.01:12:55.99#ibcon#about to read 6, iclass 36, count 0 2006.174.01:12:55.99#ibcon#read 6, iclass 36, count 0 2006.174.01:12:55.99#ibcon#end of sib2, iclass 36, count 0 2006.174.01:12:55.99#ibcon#*mode == 0, iclass 36, count 0 2006.174.01:12:55.99#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.174.01:12:55.99#ibcon#[28=FRQ=07,734.99\r\n] 2006.174.01:12:55.99#ibcon#*before write, iclass 36, count 0 2006.174.01:12:55.99#ibcon#enter sib2, iclass 36, count 0 2006.174.01:12:55.99#ibcon#flushed, iclass 36, count 0 2006.174.01:12:55.99#ibcon#about to write, iclass 36, count 0 2006.174.01:12:55.99#ibcon#wrote, iclass 36, count 0 2006.174.01:12:55.99#ibcon#about to read 3, iclass 36, count 0 2006.174.01:12:56.03#ibcon#read 3, iclass 36, count 0 2006.174.01:12:56.03#ibcon#about to read 4, iclass 36, count 0 2006.174.01:12:56.03#ibcon#read 4, iclass 36, count 0 2006.174.01:12:56.03#ibcon#about to read 5, iclass 36, count 0 2006.174.01:12:56.03#ibcon#read 5, iclass 36, count 0 2006.174.01:12:56.03#ibcon#about to read 6, iclass 36, count 0 2006.174.01:12:56.03#ibcon#read 6, iclass 36, count 0 2006.174.01:12:56.03#ibcon#end of sib2, iclass 36, count 0 2006.174.01:12:56.03#ibcon#*after write, iclass 36, count 0 2006.174.01:12:56.03#ibcon#*before return 0, iclass 36, count 0 2006.174.01:12:56.03#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.174.01:12:56.03#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.174.01:12:56.03#ibcon#about to clear, iclass 36 cls_cnt 0 2006.174.01:12:56.03#ibcon#cleared, iclass 36 cls_cnt 0 2006.174.01:12:56.03$vck44/vb=7,4 2006.174.01:12:56.03#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.174.01:12:56.03#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.174.01:12:56.03#ibcon#ireg 11 cls_cnt 2 2006.174.01:12:56.03#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.174.01:12:56.09#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.174.01:12:56.09#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.174.01:12:56.09#ibcon#enter wrdev, iclass 38, count 2 2006.174.01:12:56.09#ibcon#first serial, iclass 38, count 2 2006.174.01:12:56.09#ibcon#enter sib2, iclass 38, count 2 2006.174.01:12:56.09#ibcon#flushed, iclass 38, count 2 2006.174.01:12:56.09#ibcon#about to write, iclass 38, count 2 2006.174.01:12:56.09#ibcon#wrote, iclass 38, count 2 2006.174.01:12:56.09#ibcon#about to read 3, iclass 38, count 2 2006.174.01:12:56.11#ibcon#read 3, iclass 38, count 2 2006.174.01:12:56.11#ibcon#about to read 4, iclass 38, count 2 2006.174.01:12:56.11#ibcon#read 4, iclass 38, count 2 2006.174.01:12:56.11#ibcon#about to read 5, iclass 38, count 2 2006.174.01:12:56.11#ibcon#read 5, iclass 38, count 2 2006.174.01:12:56.11#ibcon#about to read 6, iclass 38, count 2 2006.174.01:12:56.11#ibcon#read 6, iclass 38, count 2 2006.174.01:12:56.11#ibcon#end of sib2, iclass 38, count 2 2006.174.01:12:56.11#ibcon#*mode == 0, iclass 38, count 2 2006.174.01:12:56.11#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.174.01:12:56.11#ibcon#[27=AT07-04\r\n] 2006.174.01:12:56.11#ibcon#*before write, iclass 38, count 2 2006.174.01:12:56.11#ibcon#enter sib2, iclass 38, count 2 2006.174.01:12:56.11#ibcon#flushed, iclass 38, count 2 2006.174.01:12:56.11#ibcon#about to write, iclass 38, count 2 2006.174.01:12:56.11#ibcon#wrote, iclass 38, count 2 2006.174.01:12:56.11#ibcon#about to read 3, iclass 38, count 2 2006.174.01:12:56.14#ibcon#read 3, iclass 38, count 2 2006.174.01:12:56.14#ibcon#about to read 4, iclass 38, count 2 2006.174.01:12:56.14#ibcon#read 4, iclass 38, count 2 2006.174.01:12:56.14#ibcon#about to read 5, iclass 38, count 2 2006.174.01:12:56.14#ibcon#read 5, iclass 38, count 2 2006.174.01:12:56.14#ibcon#about to read 6, iclass 38, count 2 2006.174.01:12:56.14#ibcon#read 6, iclass 38, count 2 2006.174.01:12:56.14#ibcon#end of sib2, iclass 38, count 2 2006.174.01:12:56.14#ibcon#*after write, iclass 38, count 2 2006.174.01:12:56.14#ibcon#*before return 0, iclass 38, count 2 2006.174.01:12:56.14#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.174.01:12:56.14#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.174.01:12:56.14#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.174.01:12:56.14#ibcon#ireg 7 cls_cnt 0 2006.174.01:12:56.14#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.174.01:12:56.26#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.174.01:12:56.26#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.174.01:12:56.26#ibcon#enter wrdev, iclass 38, count 0 2006.174.01:12:56.26#ibcon#first serial, iclass 38, count 0 2006.174.01:12:56.26#ibcon#enter sib2, iclass 38, count 0 2006.174.01:12:56.26#ibcon#flushed, iclass 38, count 0 2006.174.01:12:56.26#ibcon#about to write, iclass 38, count 0 2006.174.01:12:56.26#ibcon#wrote, iclass 38, count 0 2006.174.01:12:56.26#ibcon#about to read 3, iclass 38, count 0 2006.174.01:12:56.28#ibcon#read 3, iclass 38, count 0 2006.174.01:12:56.28#ibcon#about to read 4, iclass 38, count 0 2006.174.01:12:56.28#ibcon#read 4, iclass 38, count 0 2006.174.01:12:56.28#ibcon#about to read 5, iclass 38, count 0 2006.174.01:12:56.28#ibcon#read 5, iclass 38, count 0 2006.174.01:12:56.28#ibcon#about to read 6, iclass 38, count 0 2006.174.01:12:56.28#ibcon#read 6, iclass 38, count 0 2006.174.01:12:56.28#ibcon#end of sib2, iclass 38, count 0 2006.174.01:12:56.28#ibcon#*mode == 0, iclass 38, count 0 2006.174.01:12:56.28#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.174.01:12:56.28#ibcon#[27=USB\r\n] 2006.174.01:12:56.28#ibcon#*before write, iclass 38, count 0 2006.174.01:12:56.28#ibcon#enter sib2, iclass 38, count 0 2006.174.01:12:56.28#ibcon#flushed, iclass 38, count 0 2006.174.01:12:56.28#ibcon#about to write, iclass 38, count 0 2006.174.01:12:56.28#ibcon#wrote, iclass 38, count 0 2006.174.01:12:56.28#ibcon#about to read 3, iclass 38, count 0 2006.174.01:12:56.31#ibcon#read 3, iclass 38, count 0 2006.174.01:12:56.31#ibcon#about to read 4, iclass 38, count 0 2006.174.01:12:56.31#ibcon#read 4, iclass 38, count 0 2006.174.01:12:56.31#ibcon#about to read 5, iclass 38, count 0 2006.174.01:12:56.31#ibcon#read 5, iclass 38, count 0 2006.174.01:12:56.31#ibcon#about to read 6, iclass 38, count 0 2006.174.01:12:56.31#ibcon#read 6, iclass 38, count 0 2006.174.01:12:56.31#ibcon#end of sib2, iclass 38, count 0 2006.174.01:12:56.31#ibcon#*after write, iclass 38, count 0 2006.174.01:12:56.31#ibcon#*before return 0, iclass 38, count 0 2006.174.01:12:56.31#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.174.01:12:56.31#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.174.01:12:56.31#ibcon#about to clear, iclass 38 cls_cnt 0 2006.174.01:12:56.31#ibcon#cleared, iclass 38 cls_cnt 0 2006.174.01:12:56.31$vck44/vblo=8,744.99 2006.174.01:12:56.31#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.174.01:12:56.31#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.174.01:12:56.31#ibcon#ireg 17 cls_cnt 0 2006.174.01:12:56.31#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.174.01:12:56.31#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.174.01:12:56.31#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.174.01:12:56.31#ibcon#enter wrdev, iclass 40, count 0 2006.174.01:12:56.31#ibcon#first serial, iclass 40, count 0 2006.174.01:12:56.31#ibcon#enter sib2, iclass 40, count 0 2006.174.01:12:56.31#ibcon#flushed, iclass 40, count 0 2006.174.01:12:56.31#ibcon#about to write, iclass 40, count 0 2006.174.01:12:56.31#ibcon#wrote, iclass 40, count 0 2006.174.01:12:56.31#ibcon#about to read 3, iclass 40, count 0 2006.174.01:12:56.33#ibcon#read 3, iclass 40, count 0 2006.174.01:12:56.33#ibcon#about to read 4, iclass 40, count 0 2006.174.01:12:56.33#ibcon#read 4, iclass 40, count 0 2006.174.01:12:56.33#ibcon#about to read 5, iclass 40, count 0 2006.174.01:12:56.33#ibcon#read 5, iclass 40, count 0 2006.174.01:12:56.33#ibcon#about to read 6, iclass 40, count 0 2006.174.01:12:56.33#ibcon#read 6, iclass 40, count 0 2006.174.01:12:56.33#ibcon#end of sib2, iclass 40, count 0 2006.174.01:12:56.33#ibcon#*mode == 0, iclass 40, count 0 2006.174.01:12:56.33#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.174.01:12:56.33#ibcon#[28=FRQ=08,744.99\r\n] 2006.174.01:12:56.33#ibcon#*before write, iclass 40, count 0 2006.174.01:12:56.33#ibcon#enter sib2, iclass 40, count 0 2006.174.01:12:56.33#ibcon#flushed, iclass 40, count 0 2006.174.01:12:56.33#ibcon#about to write, iclass 40, count 0 2006.174.01:12:56.33#ibcon#wrote, iclass 40, count 0 2006.174.01:12:56.33#ibcon#about to read 3, iclass 40, count 0 2006.174.01:12:56.37#ibcon#read 3, iclass 40, count 0 2006.174.01:12:56.37#ibcon#about to read 4, iclass 40, count 0 2006.174.01:12:56.37#ibcon#read 4, iclass 40, count 0 2006.174.01:12:56.37#ibcon#about to read 5, iclass 40, count 0 2006.174.01:12:56.37#ibcon#read 5, iclass 40, count 0 2006.174.01:12:56.37#ibcon#about to read 6, iclass 40, count 0 2006.174.01:12:56.37#ibcon#read 6, iclass 40, count 0 2006.174.01:12:56.37#ibcon#end of sib2, iclass 40, count 0 2006.174.01:12:56.37#ibcon#*after write, iclass 40, count 0 2006.174.01:12:56.37#ibcon#*before return 0, iclass 40, count 0 2006.174.01:12:56.37#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.174.01:12:56.37#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.174.01:12:56.37#ibcon#about to clear, iclass 40 cls_cnt 0 2006.174.01:12:56.37#ibcon#cleared, iclass 40 cls_cnt 0 2006.174.01:12:56.37$vck44/vb=8,4 2006.174.01:12:56.37#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.174.01:12:56.37#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.174.01:12:56.37#ibcon#ireg 11 cls_cnt 2 2006.174.01:12:56.37#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.174.01:12:56.43#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.174.01:12:56.43#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.174.01:12:56.43#ibcon#enter wrdev, iclass 4, count 2 2006.174.01:12:56.43#ibcon#first serial, iclass 4, count 2 2006.174.01:12:56.43#ibcon#enter sib2, iclass 4, count 2 2006.174.01:12:56.43#ibcon#flushed, iclass 4, count 2 2006.174.01:12:56.43#ibcon#about to write, iclass 4, count 2 2006.174.01:12:56.43#ibcon#wrote, iclass 4, count 2 2006.174.01:12:56.43#ibcon#about to read 3, iclass 4, count 2 2006.174.01:12:56.45#ibcon#read 3, iclass 4, count 2 2006.174.01:12:56.45#ibcon#about to read 4, iclass 4, count 2 2006.174.01:12:56.45#ibcon#read 4, iclass 4, count 2 2006.174.01:12:56.45#ibcon#about to read 5, iclass 4, count 2 2006.174.01:12:56.45#ibcon#read 5, iclass 4, count 2 2006.174.01:12:56.45#ibcon#about to read 6, iclass 4, count 2 2006.174.01:12:56.45#ibcon#read 6, iclass 4, count 2 2006.174.01:12:56.45#ibcon#end of sib2, iclass 4, count 2 2006.174.01:12:56.45#ibcon#*mode == 0, iclass 4, count 2 2006.174.01:12:56.45#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.174.01:12:56.45#ibcon#[27=AT08-04\r\n] 2006.174.01:12:56.45#ibcon#*before write, iclass 4, count 2 2006.174.01:12:56.45#ibcon#enter sib2, iclass 4, count 2 2006.174.01:12:56.45#ibcon#flushed, iclass 4, count 2 2006.174.01:12:56.45#ibcon#about to write, iclass 4, count 2 2006.174.01:12:56.45#ibcon#wrote, iclass 4, count 2 2006.174.01:12:56.45#ibcon#about to read 3, iclass 4, count 2 2006.174.01:12:56.48#ibcon#read 3, iclass 4, count 2 2006.174.01:12:56.48#ibcon#about to read 4, iclass 4, count 2 2006.174.01:12:56.48#ibcon#read 4, iclass 4, count 2 2006.174.01:12:56.48#ibcon#about to read 5, iclass 4, count 2 2006.174.01:12:56.48#ibcon#read 5, iclass 4, count 2 2006.174.01:12:56.48#ibcon#about to read 6, iclass 4, count 2 2006.174.01:12:56.48#ibcon#read 6, iclass 4, count 2 2006.174.01:12:56.48#ibcon#end of sib2, iclass 4, count 2 2006.174.01:12:56.48#ibcon#*after write, iclass 4, count 2 2006.174.01:12:56.48#ibcon#*before return 0, iclass 4, count 2 2006.174.01:12:56.48#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.174.01:12:56.48#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.174.01:12:56.48#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.174.01:12:56.48#ibcon#ireg 7 cls_cnt 0 2006.174.01:12:56.48#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.174.01:12:56.60#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.174.01:12:56.60#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.174.01:12:56.60#ibcon#enter wrdev, iclass 4, count 0 2006.174.01:12:56.60#ibcon#first serial, iclass 4, count 0 2006.174.01:12:56.60#ibcon#enter sib2, iclass 4, count 0 2006.174.01:12:56.60#ibcon#flushed, iclass 4, count 0 2006.174.01:12:56.60#ibcon#about to write, iclass 4, count 0 2006.174.01:12:56.60#ibcon#wrote, iclass 4, count 0 2006.174.01:12:56.60#ibcon#about to read 3, iclass 4, count 0 2006.174.01:12:56.62#ibcon#read 3, iclass 4, count 0 2006.174.01:12:56.62#ibcon#about to read 4, iclass 4, count 0 2006.174.01:12:56.62#ibcon#read 4, iclass 4, count 0 2006.174.01:12:56.62#ibcon#about to read 5, iclass 4, count 0 2006.174.01:12:56.62#ibcon#read 5, iclass 4, count 0 2006.174.01:12:56.62#ibcon#about to read 6, iclass 4, count 0 2006.174.01:12:56.62#ibcon#read 6, iclass 4, count 0 2006.174.01:12:56.62#ibcon#end of sib2, iclass 4, count 0 2006.174.01:12:56.62#ibcon#*mode == 0, iclass 4, count 0 2006.174.01:12:56.62#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.174.01:12:56.62#ibcon#[27=USB\r\n] 2006.174.01:12:56.62#ibcon#*before write, iclass 4, count 0 2006.174.01:12:56.62#ibcon#enter sib2, iclass 4, count 0 2006.174.01:12:56.62#ibcon#flushed, iclass 4, count 0 2006.174.01:12:56.62#ibcon#about to write, iclass 4, count 0 2006.174.01:12:56.62#ibcon#wrote, iclass 4, count 0 2006.174.01:12:56.62#ibcon#about to read 3, iclass 4, count 0 2006.174.01:12:56.65#ibcon#read 3, iclass 4, count 0 2006.174.01:12:56.65#ibcon#about to read 4, iclass 4, count 0 2006.174.01:12:56.65#ibcon#read 4, iclass 4, count 0 2006.174.01:12:56.65#ibcon#about to read 5, iclass 4, count 0 2006.174.01:12:56.65#ibcon#read 5, iclass 4, count 0 2006.174.01:12:56.65#ibcon#about to read 6, iclass 4, count 0 2006.174.01:12:56.65#ibcon#read 6, iclass 4, count 0 2006.174.01:12:56.65#ibcon#end of sib2, iclass 4, count 0 2006.174.01:12:56.65#ibcon#*after write, iclass 4, count 0 2006.174.01:12:56.65#ibcon#*before return 0, iclass 4, count 0 2006.174.01:12:56.65#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.174.01:12:56.65#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.174.01:12:56.65#ibcon#about to clear, iclass 4 cls_cnt 0 2006.174.01:12:56.65#ibcon#cleared, iclass 4 cls_cnt 0 2006.174.01:12:56.65$vck44/vabw=wide 2006.174.01:12:56.65#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.174.01:12:56.65#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.174.01:12:56.65#ibcon#ireg 8 cls_cnt 0 2006.174.01:12:56.65#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.174.01:12:56.65#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.174.01:12:56.65#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.174.01:12:56.65#ibcon#enter wrdev, iclass 6, count 0 2006.174.01:12:56.65#ibcon#first serial, iclass 6, count 0 2006.174.01:12:56.65#ibcon#enter sib2, iclass 6, count 0 2006.174.01:12:56.65#ibcon#flushed, iclass 6, count 0 2006.174.01:12:56.65#ibcon#about to write, iclass 6, count 0 2006.174.01:12:56.65#ibcon#wrote, iclass 6, count 0 2006.174.01:12:56.65#ibcon#about to read 3, iclass 6, count 0 2006.174.01:12:56.67#ibcon#read 3, iclass 6, count 0 2006.174.01:12:56.67#ibcon#about to read 4, iclass 6, count 0 2006.174.01:12:56.67#ibcon#read 4, iclass 6, count 0 2006.174.01:12:56.67#ibcon#about to read 5, iclass 6, count 0 2006.174.01:12:56.67#ibcon#read 5, iclass 6, count 0 2006.174.01:12:56.67#ibcon#about to read 6, iclass 6, count 0 2006.174.01:12:56.67#ibcon#read 6, iclass 6, count 0 2006.174.01:12:56.67#ibcon#end of sib2, iclass 6, count 0 2006.174.01:12:56.67#ibcon#*mode == 0, iclass 6, count 0 2006.174.01:12:56.67#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.174.01:12:56.67#ibcon#[25=BW32\r\n] 2006.174.01:12:56.67#ibcon#*before write, iclass 6, count 0 2006.174.01:12:56.67#ibcon#enter sib2, iclass 6, count 0 2006.174.01:12:56.67#ibcon#flushed, iclass 6, count 0 2006.174.01:12:56.67#ibcon#about to write, iclass 6, count 0 2006.174.01:12:56.67#ibcon#wrote, iclass 6, count 0 2006.174.01:12:56.67#ibcon#about to read 3, iclass 6, count 0 2006.174.01:12:56.70#ibcon#read 3, iclass 6, count 0 2006.174.01:12:56.70#ibcon#about to read 4, iclass 6, count 0 2006.174.01:12:56.70#ibcon#read 4, iclass 6, count 0 2006.174.01:12:56.70#ibcon#about to read 5, iclass 6, count 0 2006.174.01:12:56.70#ibcon#read 5, iclass 6, count 0 2006.174.01:12:56.70#ibcon#about to read 6, iclass 6, count 0 2006.174.01:12:56.70#ibcon#read 6, iclass 6, count 0 2006.174.01:12:56.70#ibcon#end of sib2, iclass 6, count 0 2006.174.01:12:56.70#ibcon#*after write, iclass 6, count 0 2006.174.01:12:56.70#ibcon#*before return 0, iclass 6, count 0 2006.174.01:12:56.70#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.174.01:12:56.70#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.174.01:12:56.70#ibcon#about to clear, iclass 6 cls_cnt 0 2006.174.01:12:56.70#ibcon#cleared, iclass 6 cls_cnt 0 2006.174.01:12:56.70$vck44/vbbw=wide 2006.174.01:12:56.70#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.174.01:12:56.70#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.174.01:12:56.70#ibcon#ireg 8 cls_cnt 0 2006.174.01:12:56.70#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.174.01:12:56.77#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.174.01:12:56.77#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.174.01:12:56.77#ibcon#enter wrdev, iclass 10, count 0 2006.174.01:12:56.77#ibcon#first serial, iclass 10, count 0 2006.174.01:12:56.77#ibcon#enter sib2, iclass 10, count 0 2006.174.01:12:56.77#ibcon#flushed, iclass 10, count 0 2006.174.01:12:56.77#ibcon#about to write, iclass 10, count 0 2006.174.01:12:56.77#ibcon#wrote, iclass 10, count 0 2006.174.01:12:56.77#ibcon#about to read 3, iclass 10, count 0 2006.174.01:12:56.79#ibcon#read 3, iclass 10, count 0 2006.174.01:12:56.79#ibcon#about to read 4, iclass 10, count 0 2006.174.01:12:56.79#ibcon#read 4, iclass 10, count 0 2006.174.01:12:56.79#ibcon#about to read 5, iclass 10, count 0 2006.174.01:12:56.79#ibcon#read 5, iclass 10, count 0 2006.174.01:12:56.79#ibcon#about to read 6, iclass 10, count 0 2006.174.01:12:56.79#ibcon#read 6, iclass 10, count 0 2006.174.01:12:56.79#ibcon#end of sib2, iclass 10, count 0 2006.174.01:12:56.79#ibcon#*mode == 0, iclass 10, count 0 2006.174.01:12:56.79#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.174.01:12:56.79#ibcon#[27=BW32\r\n] 2006.174.01:12:56.79#ibcon#*before write, iclass 10, count 0 2006.174.01:12:56.79#ibcon#enter sib2, iclass 10, count 0 2006.174.01:12:56.79#ibcon#flushed, iclass 10, count 0 2006.174.01:12:56.79#ibcon#about to write, iclass 10, count 0 2006.174.01:12:56.79#ibcon#wrote, iclass 10, count 0 2006.174.01:12:56.79#ibcon#about to read 3, iclass 10, count 0 2006.174.01:12:56.82#ibcon#read 3, iclass 10, count 0 2006.174.01:12:56.82#ibcon#about to read 4, iclass 10, count 0 2006.174.01:12:56.82#ibcon#read 4, iclass 10, count 0 2006.174.01:12:56.82#ibcon#about to read 5, iclass 10, count 0 2006.174.01:12:56.82#ibcon#read 5, iclass 10, count 0 2006.174.01:12:56.82#ibcon#about to read 6, iclass 10, count 0 2006.174.01:12:56.82#ibcon#read 6, iclass 10, count 0 2006.174.01:12:56.82#ibcon#end of sib2, iclass 10, count 0 2006.174.01:12:56.82#ibcon#*after write, iclass 10, count 0 2006.174.01:12:56.82#ibcon#*before return 0, iclass 10, count 0 2006.174.01:12:56.82#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.174.01:12:56.82#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.174.01:12:56.82#ibcon#about to clear, iclass 10 cls_cnt 0 2006.174.01:12:56.82#ibcon#cleared, iclass 10 cls_cnt 0 2006.174.01:12:56.82$setupk4/ifdk4 2006.174.01:12:56.82$ifdk4/lo= 2006.174.01:12:56.82$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.174.01:12:56.82$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.174.01:12:56.82$ifdk4/patch= 2006.174.01:12:56.82$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.174.01:12:56.82$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.174.01:12:56.82$setupk4/!*+20s 2006.174.01:13:02.02#abcon#<5=/07 0.7 1.6 25.48 811003.3\r\n> 2006.174.01:13:02.04#abcon#{5=INTERFACE CLEAR} 2006.174.01:13:02.10#abcon#[5=S1D000X0/0*\r\n] 2006.174.01:13:11.33$setupk4/"tpicd 2006.174.01:13:11.33$setupk4/echo=off 2006.174.01:13:11.33$setupk4/xlog=off 2006.174.01:13:11.33:!2006.174.01:14:58 2006.174.01:13:29.13#trakl#Source acquired 2006.174.01:13:31.13#flagr#flagr/antenna,acquired 2006.174.01:14:58.00:preob 2006.174.01:14:59.13/onsource/TRACKING 2006.174.01:14:59.13:!2006.174.01:15:08 2006.174.01:15:08.00:"tape 2006.174.01:15:08.00:"st=record 2006.174.01:15:08.00:data_valid=on 2006.174.01:15:08.00:midob 2006.174.01:15:08.14/onsource/TRACKING 2006.174.01:15:08.14/wx/25.50,1003.3,80 2006.174.01:15:08.33/cable/+6.5014E-03 2006.174.01:15:09.42/va/01,07,usb,yes,35,38 2006.174.01:15:09.42/va/02,06,usb,yes,35,35 2006.174.01:15:09.42/va/03,05,usb,yes,44,46 2006.174.01:15:09.42/va/04,06,usb,yes,35,37 2006.174.01:15:09.42/va/05,04,usb,yes,28,28 2006.174.01:15:09.42/va/06,03,usb,yes,39,39 2006.174.01:15:09.42/va/07,04,usb,yes,32,33 2006.174.01:15:09.42/va/08,04,usb,yes,27,32 2006.174.01:15:09.65/valo/01,524.99,yes,locked 2006.174.01:15:09.65/valo/02,534.99,yes,locked 2006.174.01:15:09.65/valo/03,564.99,yes,locked 2006.174.01:15:09.65/valo/04,624.99,yes,locked 2006.174.01:15:09.65/valo/05,734.99,yes,locked 2006.174.01:15:09.65/valo/06,814.99,yes,locked 2006.174.01:15:09.65/valo/07,864.99,yes,locked 2006.174.01:15:09.65/valo/08,884.99,yes,locked 2006.174.01:15:10.74/vb/01,04,usb,yes,29,27 2006.174.01:15:10.74/vb/02,04,usb,yes,32,31 2006.174.01:15:10.74/vb/03,04,usb,yes,29,32 2006.174.01:15:10.74/vb/04,04,usb,yes,33,32 2006.174.01:15:10.74/vb/05,04,usb,yes,26,28 2006.174.01:15:10.74/vb/06,04,usb,yes,30,26 2006.174.01:15:10.74/vb/07,04,usb,yes,30,30 2006.174.01:15:10.74/vb/08,04,usb,yes,27,31 2006.174.01:15:10.98/vblo/01,629.99,yes,locked 2006.174.01:15:10.98/vblo/02,634.99,yes,locked 2006.174.01:15:10.98/vblo/03,649.99,yes,locked 2006.174.01:15:10.98/vblo/04,679.99,yes,locked 2006.174.01:15:10.98/vblo/05,709.99,yes,locked 2006.174.01:15:10.98/vblo/06,719.99,yes,locked 2006.174.01:15:10.98/vblo/07,734.99,yes,locked 2006.174.01:15:10.98/vblo/08,744.99,yes,locked 2006.174.01:15:11.13/vabw/8 2006.174.01:15:11.28/vbbw/8 2006.174.01:15:11.37/xfe/off,on,14.5 2006.174.01:15:11.74/ifatt/23,28,28,28 2006.174.01:15:12.08/fmout-gps/S +3.82E-07 2006.174.01:15:12.12:!2006.174.01:18:58 2006.174.01:18:58.01:data_valid=off 2006.174.01:18:58.01:"et 2006.174.01:18:58.01:!+3s 2006.174.01:19:01.02:"tape 2006.174.01:19:01.02:postob 2006.174.01:19:01.12/cable/+6.5023E-03 2006.174.01:19:01.12/wx/25.51,1003.4,82 2006.174.01:19:01.18/fmout-gps/S +3.80E-07 2006.174.01:19:01.18:scan_name=174-0122,jd0606,40 2006.174.01:19:01.18:source=0537-441,053850.36,-440508.9,2000.0,ccw 2006.174.01:19:02.14#flagr#flagr/antenna,new-source 2006.174.01:19:02.14:checkk5 2006.174.01:19:02.54/chk_autoobs//k5ts1/ autoobs is running! 2006.174.01:19:02.94/chk_autoobs//k5ts2/ autoobs is running! 2006.174.01:19:03.35/chk_autoobs//k5ts3/ autoobs is running! 2006.174.01:19:03.76/chk_autoobs//k5ts4/ autoobs is running! 2006.174.01:19:04.16/chk_obsdata//k5ts1/T1740115??a.dat file size is correct (nominal:920MB, actual:916MB). 2006.174.01:19:04.57/chk_obsdata//k5ts2/T1740115??b.dat file size is correct (nominal:920MB, actual:916MB). 2006.174.01:19:04.97/chk_obsdata//k5ts3/T1740115??c.dat file size is correct (nominal:920MB, actual:916MB). 2006.174.01:19:05.38/chk_obsdata//k5ts4/T1740115??d.dat file size is correct (nominal:920MB, actual:916MB). 2006.174.01:19:06.11/k5log//k5ts1_log_newline 2006.174.01:19:06.83/k5log//k5ts2_log_newline 2006.174.01:19:07.53/k5log//k5ts3_log_newline 2006.174.01:19:08.23/k5log//k5ts4_log_newline 2006.174.01:19:08.26/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.174.01:19:08.26:setupk4=1 2006.174.01:19:08.26$setupk4/echo=on 2006.174.01:19:08.26$setupk4/pcalon 2006.174.01:19:08.26$pcalon/"no phase cal control is implemented here 2006.174.01:19:08.26$setupk4/"tpicd=stop 2006.174.01:19:08.26$setupk4/"rec=synch_on 2006.174.01:19:08.26$setupk4/"rec_mode=128 2006.174.01:19:08.26$setupk4/!* 2006.174.01:19:08.26$setupk4/recpk4 2006.174.01:19:08.26$recpk4/recpatch= 2006.174.01:19:08.27$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.174.01:19:08.27$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.174.01:19:08.27$setupk4/vck44 2006.174.01:19:08.27$vck44/valo=1,524.99 2006.174.01:19:08.27#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.174.01:19:08.27#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.174.01:19:08.27#ibcon#ireg 17 cls_cnt 0 2006.174.01:19:08.27#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.174.01:19:08.27#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.174.01:19:08.27#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.174.01:19:08.27#ibcon#enter wrdev, iclass 16, count 0 2006.174.01:19:08.27#ibcon#first serial, iclass 16, count 0 2006.174.01:19:08.27#ibcon#enter sib2, iclass 16, count 0 2006.174.01:19:08.27#ibcon#flushed, iclass 16, count 0 2006.174.01:19:08.27#ibcon#about to write, iclass 16, count 0 2006.174.01:19:08.27#ibcon#wrote, iclass 16, count 0 2006.174.01:19:08.27#ibcon#about to read 3, iclass 16, count 0 2006.174.01:19:08.29#ibcon#read 3, iclass 16, count 0 2006.174.01:19:08.29#ibcon#about to read 4, iclass 16, count 0 2006.174.01:19:08.29#ibcon#read 4, iclass 16, count 0 2006.174.01:19:08.29#ibcon#about to read 5, iclass 16, count 0 2006.174.01:19:08.29#ibcon#read 5, iclass 16, count 0 2006.174.01:19:08.29#ibcon#about to read 6, iclass 16, count 0 2006.174.01:19:08.29#ibcon#read 6, iclass 16, count 0 2006.174.01:19:08.29#ibcon#end of sib2, iclass 16, count 0 2006.174.01:19:08.29#ibcon#*mode == 0, iclass 16, count 0 2006.174.01:19:08.29#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.174.01:19:08.29#ibcon#[26=FRQ=01,524.99\r\n] 2006.174.01:19:08.29#ibcon#*before write, iclass 16, count 0 2006.174.01:19:08.29#ibcon#enter sib2, iclass 16, count 0 2006.174.01:19:08.29#ibcon#flushed, iclass 16, count 0 2006.174.01:19:08.29#ibcon#about to write, iclass 16, count 0 2006.174.01:19:08.29#ibcon#wrote, iclass 16, count 0 2006.174.01:19:08.29#ibcon#about to read 3, iclass 16, count 0 2006.174.01:19:08.30#abcon#{5=INTERFACE CLEAR} 2006.174.01:19:08.34#ibcon#read 3, iclass 16, count 0 2006.174.01:19:08.34#ibcon#about to read 4, iclass 16, count 0 2006.174.01:19:08.34#ibcon#read 4, iclass 16, count 0 2006.174.01:19:08.34#ibcon#about to read 5, iclass 16, count 0 2006.174.01:19:08.34#ibcon#read 5, iclass 16, count 0 2006.174.01:19:08.34#ibcon#about to read 6, iclass 16, count 0 2006.174.01:19:08.34#ibcon#read 6, iclass 16, count 0 2006.174.01:19:08.34#ibcon#end of sib2, iclass 16, count 0 2006.174.01:19:08.34#ibcon#*after write, iclass 16, count 0 2006.174.01:19:08.34#ibcon#*before return 0, iclass 16, count 0 2006.174.01:19:08.34#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.174.01:19:08.34#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.174.01:19:08.34#ibcon#about to clear, iclass 16 cls_cnt 0 2006.174.01:19:08.34#ibcon#cleared, iclass 16 cls_cnt 0 2006.174.01:19:08.34$vck44/va=1,7 2006.174.01:19:08.34#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.174.01:19:08.34#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.174.01:19:08.34#ibcon#ireg 11 cls_cnt 2 2006.174.01:19:08.34#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.174.01:19:08.34#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.174.01:19:08.34#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.174.01:19:08.34#ibcon#enter wrdev, iclass 21, count 2 2006.174.01:19:08.34#ibcon#first serial, iclass 21, count 2 2006.174.01:19:08.34#ibcon#enter sib2, iclass 21, count 2 2006.174.01:19:08.34#ibcon#flushed, iclass 21, count 2 2006.174.01:19:08.34#ibcon#about to write, iclass 21, count 2 2006.174.01:19:08.34#ibcon#wrote, iclass 21, count 2 2006.174.01:19:08.34#ibcon#about to read 3, iclass 21, count 2 2006.174.01:19:08.36#abcon#[5=S1D000X0/0*\r\n] 2006.174.01:19:08.36#ibcon#read 3, iclass 21, count 2 2006.174.01:19:08.36#ibcon#about to read 4, iclass 21, count 2 2006.174.01:19:08.36#ibcon#read 4, iclass 21, count 2 2006.174.01:19:08.36#ibcon#about to read 5, iclass 21, count 2 2006.174.01:19:08.36#ibcon#read 5, iclass 21, count 2 2006.174.01:19:08.36#ibcon#about to read 6, iclass 21, count 2 2006.174.01:19:08.36#ibcon#read 6, iclass 21, count 2 2006.174.01:19:08.36#ibcon#end of sib2, iclass 21, count 2 2006.174.01:19:08.36#ibcon#*mode == 0, iclass 21, count 2 2006.174.01:19:08.36#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.174.01:19:08.36#ibcon#[25=AT01-07\r\n] 2006.174.01:19:08.36#ibcon#*before write, iclass 21, count 2 2006.174.01:19:08.36#ibcon#enter sib2, iclass 21, count 2 2006.174.01:19:08.36#ibcon#flushed, iclass 21, count 2 2006.174.01:19:08.36#ibcon#about to write, iclass 21, count 2 2006.174.01:19:08.36#ibcon#wrote, iclass 21, count 2 2006.174.01:19:08.36#ibcon#about to read 3, iclass 21, count 2 2006.174.01:19:08.39#ibcon#read 3, iclass 21, count 2 2006.174.01:19:08.39#ibcon#about to read 4, iclass 21, count 2 2006.174.01:19:08.39#ibcon#read 4, iclass 21, count 2 2006.174.01:19:08.39#ibcon#about to read 5, iclass 21, count 2 2006.174.01:19:08.39#ibcon#read 5, iclass 21, count 2 2006.174.01:19:08.39#ibcon#about to read 6, iclass 21, count 2 2006.174.01:19:08.39#ibcon#read 6, iclass 21, count 2 2006.174.01:19:08.39#ibcon#end of sib2, iclass 21, count 2 2006.174.01:19:08.39#ibcon#*after write, iclass 21, count 2 2006.174.01:19:08.39#ibcon#*before return 0, iclass 21, count 2 2006.174.01:19:08.39#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.174.01:19:08.39#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.174.01:19:08.39#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.174.01:19:08.39#ibcon#ireg 7 cls_cnt 0 2006.174.01:19:08.39#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.174.01:19:08.51#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.174.01:19:08.51#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.174.01:19:08.51#ibcon#enter wrdev, iclass 21, count 0 2006.174.01:19:08.51#ibcon#first serial, iclass 21, count 0 2006.174.01:19:08.51#ibcon#enter sib2, iclass 21, count 0 2006.174.01:19:08.51#ibcon#flushed, iclass 21, count 0 2006.174.01:19:08.51#ibcon#about to write, iclass 21, count 0 2006.174.01:19:08.51#ibcon#wrote, iclass 21, count 0 2006.174.01:19:08.51#ibcon#about to read 3, iclass 21, count 0 2006.174.01:19:08.53#ibcon#read 3, iclass 21, count 0 2006.174.01:19:08.53#ibcon#about to read 4, iclass 21, count 0 2006.174.01:19:08.53#ibcon#read 4, iclass 21, count 0 2006.174.01:19:08.53#ibcon#about to read 5, iclass 21, count 0 2006.174.01:19:08.53#ibcon#read 5, iclass 21, count 0 2006.174.01:19:08.53#ibcon#about to read 6, iclass 21, count 0 2006.174.01:19:08.53#ibcon#read 6, iclass 21, count 0 2006.174.01:19:08.53#ibcon#end of sib2, iclass 21, count 0 2006.174.01:19:08.53#ibcon#*mode == 0, iclass 21, count 0 2006.174.01:19:08.53#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.174.01:19:08.53#ibcon#[25=USB\r\n] 2006.174.01:19:08.53#ibcon#*before write, iclass 21, count 0 2006.174.01:19:08.53#ibcon#enter sib2, iclass 21, count 0 2006.174.01:19:08.53#ibcon#flushed, iclass 21, count 0 2006.174.01:19:08.53#ibcon#about to write, iclass 21, count 0 2006.174.01:19:08.53#ibcon#wrote, iclass 21, count 0 2006.174.01:19:08.53#ibcon#about to read 3, iclass 21, count 0 2006.174.01:19:08.56#ibcon#read 3, iclass 21, count 0 2006.174.01:19:08.56#ibcon#about to read 4, iclass 21, count 0 2006.174.01:19:08.56#ibcon#read 4, iclass 21, count 0 2006.174.01:19:08.56#ibcon#about to read 5, iclass 21, count 0 2006.174.01:19:08.56#ibcon#read 5, iclass 21, count 0 2006.174.01:19:08.56#ibcon#about to read 6, iclass 21, count 0 2006.174.01:19:08.56#ibcon#read 6, iclass 21, count 0 2006.174.01:19:08.56#ibcon#end of sib2, iclass 21, count 0 2006.174.01:19:08.56#ibcon#*after write, iclass 21, count 0 2006.174.01:19:08.56#ibcon#*before return 0, iclass 21, count 0 2006.174.01:19:08.56#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.174.01:19:08.56#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.174.01:19:08.56#ibcon#about to clear, iclass 21 cls_cnt 0 2006.174.01:19:08.56#ibcon#cleared, iclass 21 cls_cnt 0 2006.174.01:19:08.56$vck44/valo=2,534.99 2006.174.01:19:08.56#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.174.01:19:08.56#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.174.01:19:08.56#ibcon#ireg 17 cls_cnt 0 2006.174.01:19:08.56#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.174.01:19:08.56#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.174.01:19:08.56#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.174.01:19:08.56#ibcon#enter wrdev, iclass 23, count 0 2006.174.01:19:08.56#ibcon#first serial, iclass 23, count 0 2006.174.01:19:08.56#ibcon#enter sib2, iclass 23, count 0 2006.174.01:19:08.56#ibcon#flushed, iclass 23, count 0 2006.174.01:19:08.56#ibcon#about to write, iclass 23, count 0 2006.174.01:19:08.56#ibcon#wrote, iclass 23, count 0 2006.174.01:19:08.56#ibcon#about to read 3, iclass 23, count 0 2006.174.01:19:08.58#ibcon#read 3, iclass 23, count 0 2006.174.01:19:08.58#ibcon#about to read 4, iclass 23, count 0 2006.174.01:19:08.58#ibcon#read 4, iclass 23, count 0 2006.174.01:19:08.58#ibcon#about to read 5, iclass 23, count 0 2006.174.01:19:08.58#ibcon#read 5, iclass 23, count 0 2006.174.01:19:08.58#ibcon#about to read 6, iclass 23, count 0 2006.174.01:19:08.58#ibcon#read 6, iclass 23, count 0 2006.174.01:19:08.58#ibcon#end of sib2, iclass 23, count 0 2006.174.01:19:08.58#ibcon#*mode == 0, iclass 23, count 0 2006.174.01:19:08.58#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.174.01:19:08.58#ibcon#[26=FRQ=02,534.99\r\n] 2006.174.01:19:08.58#ibcon#*before write, iclass 23, count 0 2006.174.01:19:08.58#ibcon#enter sib2, iclass 23, count 0 2006.174.01:19:08.58#ibcon#flushed, iclass 23, count 0 2006.174.01:19:08.58#ibcon#about to write, iclass 23, count 0 2006.174.01:19:08.58#ibcon#wrote, iclass 23, count 0 2006.174.01:19:08.58#ibcon#about to read 3, iclass 23, count 0 2006.174.01:19:08.62#ibcon#read 3, iclass 23, count 0 2006.174.01:19:08.62#ibcon#about to read 4, iclass 23, count 0 2006.174.01:19:08.62#ibcon#read 4, iclass 23, count 0 2006.174.01:19:08.62#ibcon#about to read 5, iclass 23, count 0 2006.174.01:19:08.62#ibcon#read 5, iclass 23, count 0 2006.174.01:19:08.62#ibcon#about to read 6, iclass 23, count 0 2006.174.01:19:08.62#ibcon#read 6, iclass 23, count 0 2006.174.01:19:08.62#ibcon#end of sib2, iclass 23, count 0 2006.174.01:19:08.62#ibcon#*after write, iclass 23, count 0 2006.174.01:19:08.62#ibcon#*before return 0, iclass 23, count 0 2006.174.01:19:08.62#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.174.01:19:08.62#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.174.01:19:08.62#ibcon#about to clear, iclass 23 cls_cnt 0 2006.174.01:19:08.62#ibcon#cleared, iclass 23 cls_cnt 0 2006.174.01:19:08.62$vck44/va=2,6 2006.174.01:19:08.62#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.174.01:19:08.62#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.174.01:19:08.62#ibcon#ireg 11 cls_cnt 2 2006.174.01:19:08.62#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.174.01:19:08.68#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.174.01:19:08.68#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.174.01:19:08.68#ibcon#enter wrdev, iclass 25, count 2 2006.174.01:19:08.68#ibcon#first serial, iclass 25, count 2 2006.174.01:19:08.68#ibcon#enter sib2, iclass 25, count 2 2006.174.01:19:08.68#ibcon#flushed, iclass 25, count 2 2006.174.01:19:08.68#ibcon#about to write, iclass 25, count 2 2006.174.01:19:08.68#ibcon#wrote, iclass 25, count 2 2006.174.01:19:08.68#ibcon#about to read 3, iclass 25, count 2 2006.174.01:19:08.70#ibcon#read 3, iclass 25, count 2 2006.174.01:19:08.70#ibcon#about to read 4, iclass 25, count 2 2006.174.01:19:08.70#ibcon#read 4, iclass 25, count 2 2006.174.01:19:08.70#ibcon#about to read 5, iclass 25, count 2 2006.174.01:19:08.70#ibcon#read 5, iclass 25, count 2 2006.174.01:19:08.70#ibcon#about to read 6, iclass 25, count 2 2006.174.01:19:08.70#ibcon#read 6, iclass 25, count 2 2006.174.01:19:08.70#ibcon#end of sib2, iclass 25, count 2 2006.174.01:19:08.70#ibcon#*mode == 0, iclass 25, count 2 2006.174.01:19:08.70#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.174.01:19:08.70#ibcon#[25=AT02-06\r\n] 2006.174.01:19:08.70#ibcon#*before write, iclass 25, count 2 2006.174.01:19:08.70#ibcon#enter sib2, iclass 25, count 2 2006.174.01:19:08.70#ibcon#flushed, iclass 25, count 2 2006.174.01:19:08.70#ibcon#about to write, iclass 25, count 2 2006.174.01:19:08.70#ibcon#wrote, iclass 25, count 2 2006.174.01:19:08.70#ibcon#about to read 3, iclass 25, count 2 2006.174.01:19:08.73#ibcon#read 3, iclass 25, count 2 2006.174.01:19:08.73#ibcon#about to read 4, iclass 25, count 2 2006.174.01:19:08.73#ibcon#read 4, iclass 25, count 2 2006.174.01:19:08.73#ibcon#about to read 5, iclass 25, count 2 2006.174.01:19:08.73#ibcon#read 5, iclass 25, count 2 2006.174.01:19:08.73#ibcon#about to read 6, iclass 25, count 2 2006.174.01:19:08.73#ibcon#read 6, iclass 25, count 2 2006.174.01:19:08.73#ibcon#end of sib2, iclass 25, count 2 2006.174.01:19:08.73#ibcon#*after write, iclass 25, count 2 2006.174.01:19:08.73#ibcon#*before return 0, iclass 25, count 2 2006.174.01:19:08.73#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.174.01:19:08.73#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.174.01:19:08.73#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.174.01:19:08.73#ibcon#ireg 7 cls_cnt 0 2006.174.01:19:08.73#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.174.01:19:08.85#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.174.01:19:08.85#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.174.01:19:08.85#ibcon#enter wrdev, iclass 25, count 0 2006.174.01:19:08.85#ibcon#first serial, iclass 25, count 0 2006.174.01:19:08.85#ibcon#enter sib2, iclass 25, count 0 2006.174.01:19:08.85#ibcon#flushed, iclass 25, count 0 2006.174.01:19:08.85#ibcon#about to write, iclass 25, count 0 2006.174.01:19:08.85#ibcon#wrote, iclass 25, count 0 2006.174.01:19:08.85#ibcon#about to read 3, iclass 25, count 0 2006.174.01:19:08.87#ibcon#read 3, iclass 25, count 0 2006.174.01:19:08.87#ibcon#about to read 4, iclass 25, count 0 2006.174.01:19:08.87#ibcon#read 4, iclass 25, count 0 2006.174.01:19:08.87#ibcon#about to read 5, iclass 25, count 0 2006.174.01:19:08.87#ibcon#read 5, iclass 25, count 0 2006.174.01:19:08.87#ibcon#about to read 6, iclass 25, count 0 2006.174.01:19:08.87#ibcon#read 6, iclass 25, count 0 2006.174.01:19:08.87#ibcon#end of sib2, iclass 25, count 0 2006.174.01:19:08.87#ibcon#*mode == 0, iclass 25, count 0 2006.174.01:19:08.87#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.174.01:19:08.87#ibcon#[25=USB\r\n] 2006.174.01:19:08.87#ibcon#*before write, iclass 25, count 0 2006.174.01:19:08.87#ibcon#enter sib2, iclass 25, count 0 2006.174.01:19:08.87#ibcon#flushed, iclass 25, count 0 2006.174.01:19:08.87#ibcon#about to write, iclass 25, count 0 2006.174.01:19:08.87#ibcon#wrote, iclass 25, count 0 2006.174.01:19:08.87#ibcon#about to read 3, iclass 25, count 0 2006.174.01:19:08.90#ibcon#read 3, iclass 25, count 0 2006.174.01:19:08.90#ibcon#about to read 4, iclass 25, count 0 2006.174.01:19:08.90#ibcon#read 4, iclass 25, count 0 2006.174.01:19:08.90#ibcon#about to read 5, iclass 25, count 0 2006.174.01:19:08.90#ibcon#read 5, iclass 25, count 0 2006.174.01:19:08.90#ibcon#about to read 6, iclass 25, count 0 2006.174.01:19:08.90#ibcon#read 6, iclass 25, count 0 2006.174.01:19:08.90#ibcon#end of sib2, iclass 25, count 0 2006.174.01:19:08.90#ibcon#*after write, iclass 25, count 0 2006.174.01:19:08.90#ibcon#*before return 0, iclass 25, count 0 2006.174.01:19:08.90#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.174.01:19:08.90#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.174.01:19:08.90#ibcon#about to clear, iclass 25 cls_cnt 0 2006.174.01:19:08.90#ibcon#cleared, iclass 25 cls_cnt 0 2006.174.01:19:08.90$vck44/valo=3,564.99 2006.174.01:19:08.90#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.174.01:19:08.90#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.174.01:19:08.90#ibcon#ireg 17 cls_cnt 0 2006.174.01:19:08.90#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.174.01:19:08.90#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.174.01:19:08.90#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.174.01:19:08.90#ibcon#enter wrdev, iclass 27, count 0 2006.174.01:19:08.90#ibcon#first serial, iclass 27, count 0 2006.174.01:19:08.90#ibcon#enter sib2, iclass 27, count 0 2006.174.01:19:08.90#ibcon#flushed, iclass 27, count 0 2006.174.01:19:08.90#ibcon#about to write, iclass 27, count 0 2006.174.01:19:08.90#ibcon#wrote, iclass 27, count 0 2006.174.01:19:08.90#ibcon#about to read 3, iclass 27, count 0 2006.174.01:19:08.92#ibcon#read 3, iclass 27, count 0 2006.174.01:19:08.92#ibcon#about to read 4, iclass 27, count 0 2006.174.01:19:08.92#ibcon#read 4, iclass 27, count 0 2006.174.01:19:08.92#ibcon#about to read 5, iclass 27, count 0 2006.174.01:19:08.92#ibcon#read 5, iclass 27, count 0 2006.174.01:19:08.92#ibcon#about to read 6, iclass 27, count 0 2006.174.01:19:08.92#ibcon#read 6, iclass 27, count 0 2006.174.01:19:08.92#ibcon#end of sib2, iclass 27, count 0 2006.174.01:19:08.92#ibcon#*mode == 0, iclass 27, count 0 2006.174.01:19:08.92#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.174.01:19:08.92#ibcon#[26=FRQ=03,564.99\r\n] 2006.174.01:19:08.92#ibcon#*before write, iclass 27, count 0 2006.174.01:19:08.92#ibcon#enter sib2, iclass 27, count 0 2006.174.01:19:08.92#ibcon#flushed, iclass 27, count 0 2006.174.01:19:08.92#ibcon#about to write, iclass 27, count 0 2006.174.01:19:08.92#ibcon#wrote, iclass 27, count 0 2006.174.01:19:08.92#ibcon#about to read 3, iclass 27, count 0 2006.174.01:19:08.96#ibcon#read 3, iclass 27, count 0 2006.174.01:19:08.96#ibcon#about to read 4, iclass 27, count 0 2006.174.01:19:08.96#ibcon#read 4, iclass 27, count 0 2006.174.01:19:08.96#ibcon#about to read 5, iclass 27, count 0 2006.174.01:19:08.96#ibcon#read 5, iclass 27, count 0 2006.174.01:19:08.96#ibcon#about to read 6, iclass 27, count 0 2006.174.01:19:08.96#ibcon#read 6, iclass 27, count 0 2006.174.01:19:08.96#ibcon#end of sib2, iclass 27, count 0 2006.174.01:19:08.96#ibcon#*after write, iclass 27, count 0 2006.174.01:19:08.96#ibcon#*before return 0, iclass 27, count 0 2006.174.01:19:08.96#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.174.01:19:08.96#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.174.01:19:08.96#ibcon#about to clear, iclass 27 cls_cnt 0 2006.174.01:19:08.96#ibcon#cleared, iclass 27 cls_cnt 0 2006.174.01:19:08.96$vck44/va=3,5 2006.174.01:19:08.96#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.174.01:19:08.96#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.174.01:19:08.96#ibcon#ireg 11 cls_cnt 2 2006.174.01:19:08.96#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.174.01:19:09.02#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.174.01:19:09.02#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.174.01:19:09.02#ibcon#enter wrdev, iclass 29, count 2 2006.174.01:19:09.02#ibcon#first serial, iclass 29, count 2 2006.174.01:19:09.02#ibcon#enter sib2, iclass 29, count 2 2006.174.01:19:09.02#ibcon#flushed, iclass 29, count 2 2006.174.01:19:09.02#ibcon#about to write, iclass 29, count 2 2006.174.01:19:09.02#ibcon#wrote, iclass 29, count 2 2006.174.01:19:09.02#ibcon#about to read 3, iclass 29, count 2 2006.174.01:19:09.04#ibcon#read 3, iclass 29, count 2 2006.174.01:19:09.04#ibcon#about to read 4, iclass 29, count 2 2006.174.01:19:09.04#ibcon#read 4, iclass 29, count 2 2006.174.01:19:09.04#ibcon#about to read 5, iclass 29, count 2 2006.174.01:19:09.04#ibcon#read 5, iclass 29, count 2 2006.174.01:19:09.04#ibcon#about to read 6, iclass 29, count 2 2006.174.01:19:09.04#ibcon#read 6, iclass 29, count 2 2006.174.01:19:09.04#ibcon#end of sib2, iclass 29, count 2 2006.174.01:19:09.04#ibcon#*mode == 0, iclass 29, count 2 2006.174.01:19:09.04#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.174.01:19:09.04#ibcon#[25=AT03-05\r\n] 2006.174.01:19:09.04#ibcon#*before write, iclass 29, count 2 2006.174.01:19:09.04#ibcon#enter sib2, iclass 29, count 2 2006.174.01:19:09.04#ibcon#flushed, iclass 29, count 2 2006.174.01:19:09.04#ibcon#about to write, iclass 29, count 2 2006.174.01:19:09.04#ibcon#wrote, iclass 29, count 2 2006.174.01:19:09.04#ibcon#about to read 3, iclass 29, count 2 2006.174.01:19:09.07#ibcon#read 3, iclass 29, count 2 2006.174.01:19:09.07#ibcon#about to read 4, iclass 29, count 2 2006.174.01:19:09.07#ibcon#read 4, iclass 29, count 2 2006.174.01:19:09.07#ibcon#about to read 5, iclass 29, count 2 2006.174.01:19:09.07#ibcon#read 5, iclass 29, count 2 2006.174.01:19:09.07#ibcon#about to read 6, iclass 29, count 2 2006.174.01:19:09.07#ibcon#read 6, iclass 29, count 2 2006.174.01:19:09.07#ibcon#end of sib2, iclass 29, count 2 2006.174.01:19:09.07#ibcon#*after write, iclass 29, count 2 2006.174.01:19:09.07#ibcon#*before return 0, iclass 29, count 2 2006.174.01:19:09.07#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.174.01:19:09.07#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.174.01:19:09.07#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.174.01:19:09.07#ibcon#ireg 7 cls_cnt 0 2006.174.01:19:09.07#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.174.01:19:09.19#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.174.01:19:09.19#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.174.01:19:09.19#ibcon#enter wrdev, iclass 29, count 0 2006.174.01:19:09.19#ibcon#first serial, iclass 29, count 0 2006.174.01:19:09.19#ibcon#enter sib2, iclass 29, count 0 2006.174.01:19:09.19#ibcon#flushed, iclass 29, count 0 2006.174.01:19:09.19#ibcon#about to write, iclass 29, count 0 2006.174.01:19:09.19#ibcon#wrote, iclass 29, count 0 2006.174.01:19:09.19#ibcon#about to read 3, iclass 29, count 0 2006.174.01:19:09.21#ibcon#read 3, iclass 29, count 0 2006.174.01:19:09.21#ibcon#about to read 4, iclass 29, count 0 2006.174.01:19:09.21#ibcon#read 4, iclass 29, count 0 2006.174.01:19:09.21#ibcon#about to read 5, iclass 29, count 0 2006.174.01:19:09.21#ibcon#read 5, iclass 29, count 0 2006.174.01:19:09.21#ibcon#about to read 6, iclass 29, count 0 2006.174.01:19:09.21#ibcon#read 6, iclass 29, count 0 2006.174.01:19:09.21#ibcon#end of sib2, iclass 29, count 0 2006.174.01:19:09.21#ibcon#*mode == 0, iclass 29, count 0 2006.174.01:19:09.21#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.174.01:19:09.21#ibcon#[25=USB\r\n] 2006.174.01:19:09.21#ibcon#*before write, iclass 29, count 0 2006.174.01:19:09.21#ibcon#enter sib2, iclass 29, count 0 2006.174.01:19:09.21#ibcon#flushed, iclass 29, count 0 2006.174.01:19:09.21#ibcon#about to write, iclass 29, count 0 2006.174.01:19:09.21#ibcon#wrote, iclass 29, count 0 2006.174.01:19:09.21#ibcon#about to read 3, iclass 29, count 0 2006.174.01:19:09.24#ibcon#read 3, iclass 29, count 0 2006.174.01:19:09.24#ibcon#about to read 4, iclass 29, count 0 2006.174.01:19:09.24#ibcon#read 4, iclass 29, count 0 2006.174.01:19:09.24#ibcon#about to read 5, iclass 29, count 0 2006.174.01:19:09.24#ibcon#read 5, iclass 29, count 0 2006.174.01:19:09.24#ibcon#about to read 6, iclass 29, count 0 2006.174.01:19:09.24#ibcon#read 6, iclass 29, count 0 2006.174.01:19:09.24#ibcon#end of sib2, iclass 29, count 0 2006.174.01:19:09.24#ibcon#*after write, iclass 29, count 0 2006.174.01:19:09.24#ibcon#*before return 0, iclass 29, count 0 2006.174.01:19:09.24#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.174.01:19:09.24#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.174.01:19:09.24#ibcon#about to clear, iclass 29 cls_cnt 0 2006.174.01:19:09.24#ibcon#cleared, iclass 29 cls_cnt 0 2006.174.01:19:09.24$vck44/valo=4,624.99 2006.174.01:19:09.24#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.174.01:19:09.24#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.174.01:19:09.24#ibcon#ireg 17 cls_cnt 0 2006.174.01:19:09.24#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.174.01:19:09.24#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.174.01:19:09.24#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.174.01:19:09.24#ibcon#enter wrdev, iclass 31, count 0 2006.174.01:19:09.24#ibcon#first serial, iclass 31, count 0 2006.174.01:19:09.24#ibcon#enter sib2, iclass 31, count 0 2006.174.01:19:09.24#ibcon#flushed, iclass 31, count 0 2006.174.01:19:09.24#ibcon#about to write, iclass 31, count 0 2006.174.01:19:09.24#ibcon#wrote, iclass 31, count 0 2006.174.01:19:09.24#ibcon#about to read 3, iclass 31, count 0 2006.174.01:19:09.26#ibcon#read 3, iclass 31, count 0 2006.174.01:19:09.26#ibcon#about to read 4, iclass 31, count 0 2006.174.01:19:09.26#ibcon#read 4, iclass 31, count 0 2006.174.01:19:09.26#ibcon#about to read 5, iclass 31, count 0 2006.174.01:19:09.26#ibcon#read 5, iclass 31, count 0 2006.174.01:19:09.26#ibcon#about to read 6, iclass 31, count 0 2006.174.01:19:09.26#ibcon#read 6, iclass 31, count 0 2006.174.01:19:09.26#ibcon#end of sib2, iclass 31, count 0 2006.174.01:19:09.26#ibcon#*mode == 0, iclass 31, count 0 2006.174.01:19:09.26#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.174.01:19:09.26#ibcon#[26=FRQ=04,624.99\r\n] 2006.174.01:19:09.26#ibcon#*before write, iclass 31, count 0 2006.174.01:19:09.26#ibcon#enter sib2, iclass 31, count 0 2006.174.01:19:09.26#ibcon#flushed, iclass 31, count 0 2006.174.01:19:09.26#ibcon#about to write, iclass 31, count 0 2006.174.01:19:09.26#ibcon#wrote, iclass 31, count 0 2006.174.01:19:09.26#ibcon#about to read 3, iclass 31, count 0 2006.174.01:19:09.30#ibcon#read 3, iclass 31, count 0 2006.174.01:19:09.30#ibcon#about to read 4, iclass 31, count 0 2006.174.01:19:09.30#ibcon#read 4, iclass 31, count 0 2006.174.01:19:09.30#ibcon#about to read 5, iclass 31, count 0 2006.174.01:19:09.30#ibcon#read 5, iclass 31, count 0 2006.174.01:19:09.30#ibcon#about to read 6, iclass 31, count 0 2006.174.01:19:09.30#ibcon#read 6, iclass 31, count 0 2006.174.01:19:09.30#ibcon#end of sib2, iclass 31, count 0 2006.174.01:19:09.30#ibcon#*after write, iclass 31, count 0 2006.174.01:19:09.30#ibcon#*before return 0, iclass 31, count 0 2006.174.01:19:09.30#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.174.01:19:09.30#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.174.01:19:09.30#ibcon#about to clear, iclass 31 cls_cnt 0 2006.174.01:19:09.30#ibcon#cleared, iclass 31 cls_cnt 0 2006.174.01:19:09.30$vck44/va=4,6 2006.174.01:19:09.30#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.174.01:19:09.30#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.174.01:19:09.30#ibcon#ireg 11 cls_cnt 2 2006.174.01:19:09.30#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.174.01:19:09.36#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.174.01:19:09.36#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.174.01:19:09.36#ibcon#enter wrdev, iclass 33, count 2 2006.174.01:19:09.36#ibcon#first serial, iclass 33, count 2 2006.174.01:19:09.36#ibcon#enter sib2, iclass 33, count 2 2006.174.01:19:09.36#ibcon#flushed, iclass 33, count 2 2006.174.01:19:09.36#ibcon#about to write, iclass 33, count 2 2006.174.01:19:09.36#ibcon#wrote, iclass 33, count 2 2006.174.01:19:09.36#ibcon#about to read 3, iclass 33, count 2 2006.174.01:19:09.38#ibcon#read 3, iclass 33, count 2 2006.174.01:19:09.38#ibcon#about to read 4, iclass 33, count 2 2006.174.01:19:09.38#ibcon#read 4, iclass 33, count 2 2006.174.01:19:09.38#ibcon#about to read 5, iclass 33, count 2 2006.174.01:19:09.38#ibcon#read 5, iclass 33, count 2 2006.174.01:19:09.38#ibcon#about to read 6, iclass 33, count 2 2006.174.01:19:09.38#ibcon#read 6, iclass 33, count 2 2006.174.01:19:09.38#ibcon#end of sib2, iclass 33, count 2 2006.174.01:19:09.38#ibcon#*mode == 0, iclass 33, count 2 2006.174.01:19:09.38#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.174.01:19:09.38#ibcon#[25=AT04-06\r\n] 2006.174.01:19:09.38#ibcon#*before write, iclass 33, count 2 2006.174.01:19:09.38#ibcon#enter sib2, iclass 33, count 2 2006.174.01:19:09.38#ibcon#flushed, iclass 33, count 2 2006.174.01:19:09.38#ibcon#about to write, iclass 33, count 2 2006.174.01:19:09.38#ibcon#wrote, iclass 33, count 2 2006.174.01:19:09.38#ibcon#about to read 3, iclass 33, count 2 2006.174.01:19:09.41#ibcon#read 3, iclass 33, count 2 2006.174.01:19:09.41#ibcon#about to read 4, iclass 33, count 2 2006.174.01:19:09.41#ibcon#read 4, iclass 33, count 2 2006.174.01:19:09.41#ibcon#about to read 5, iclass 33, count 2 2006.174.01:19:09.41#ibcon#read 5, iclass 33, count 2 2006.174.01:19:09.41#ibcon#about to read 6, iclass 33, count 2 2006.174.01:19:09.41#ibcon#read 6, iclass 33, count 2 2006.174.01:19:09.41#ibcon#end of sib2, iclass 33, count 2 2006.174.01:19:09.41#ibcon#*after write, iclass 33, count 2 2006.174.01:19:09.41#ibcon#*before return 0, iclass 33, count 2 2006.174.01:19:09.41#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.174.01:19:09.41#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.174.01:19:09.41#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.174.01:19:09.41#ibcon#ireg 7 cls_cnt 0 2006.174.01:19:09.41#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.174.01:19:09.53#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.174.01:19:09.53#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.174.01:19:09.53#ibcon#enter wrdev, iclass 33, count 0 2006.174.01:19:09.53#ibcon#first serial, iclass 33, count 0 2006.174.01:19:09.53#ibcon#enter sib2, iclass 33, count 0 2006.174.01:19:09.53#ibcon#flushed, iclass 33, count 0 2006.174.01:19:09.53#ibcon#about to write, iclass 33, count 0 2006.174.01:19:09.53#ibcon#wrote, iclass 33, count 0 2006.174.01:19:09.53#ibcon#about to read 3, iclass 33, count 0 2006.174.01:19:09.55#ibcon#read 3, iclass 33, count 0 2006.174.01:19:09.55#ibcon#about to read 4, iclass 33, count 0 2006.174.01:19:09.55#ibcon#read 4, iclass 33, count 0 2006.174.01:19:09.55#ibcon#about to read 5, iclass 33, count 0 2006.174.01:19:09.55#ibcon#read 5, iclass 33, count 0 2006.174.01:19:09.55#ibcon#about to read 6, iclass 33, count 0 2006.174.01:19:09.55#ibcon#read 6, iclass 33, count 0 2006.174.01:19:09.55#ibcon#end of sib2, iclass 33, count 0 2006.174.01:19:09.55#ibcon#*mode == 0, iclass 33, count 0 2006.174.01:19:09.55#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.174.01:19:09.55#ibcon#[25=USB\r\n] 2006.174.01:19:09.55#ibcon#*before write, iclass 33, count 0 2006.174.01:19:09.55#ibcon#enter sib2, iclass 33, count 0 2006.174.01:19:09.55#ibcon#flushed, iclass 33, count 0 2006.174.01:19:09.55#ibcon#about to write, iclass 33, count 0 2006.174.01:19:09.55#ibcon#wrote, iclass 33, count 0 2006.174.01:19:09.55#ibcon#about to read 3, iclass 33, count 0 2006.174.01:19:09.58#ibcon#read 3, iclass 33, count 0 2006.174.01:19:09.58#ibcon#about to read 4, iclass 33, count 0 2006.174.01:19:09.58#ibcon#read 4, iclass 33, count 0 2006.174.01:19:09.58#ibcon#about to read 5, iclass 33, count 0 2006.174.01:19:09.58#ibcon#read 5, iclass 33, count 0 2006.174.01:19:09.58#ibcon#about to read 6, iclass 33, count 0 2006.174.01:19:09.58#ibcon#read 6, iclass 33, count 0 2006.174.01:19:09.58#ibcon#end of sib2, iclass 33, count 0 2006.174.01:19:09.58#ibcon#*after write, iclass 33, count 0 2006.174.01:19:09.58#ibcon#*before return 0, iclass 33, count 0 2006.174.01:19:09.58#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.174.01:19:09.58#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.174.01:19:09.58#ibcon#about to clear, iclass 33 cls_cnt 0 2006.174.01:19:09.58#ibcon#cleared, iclass 33 cls_cnt 0 2006.174.01:19:09.58$vck44/valo=5,734.99 2006.174.01:19:09.58#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.174.01:19:09.58#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.174.01:19:09.58#ibcon#ireg 17 cls_cnt 0 2006.174.01:19:09.58#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.174.01:19:09.58#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.174.01:19:09.58#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.174.01:19:09.58#ibcon#enter wrdev, iclass 35, count 0 2006.174.01:19:09.58#ibcon#first serial, iclass 35, count 0 2006.174.01:19:09.58#ibcon#enter sib2, iclass 35, count 0 2006.174.01:19:09.58#ibcon#flushed, iclass 35, count 0 2006.174.01:19:09.58#ibcon#about to write, iclass 35, count 0 2006.174.01:19:09.58#ibcon#wrote, iclass 35, count 0 2006.174.01:19:09.58#ibcon#about to read 3, iclass 35, count 0 2006.174.01:19:09.60#ibcon#read 3, iclass 35, count 0 2006.174.01:19:09.60#ibcon#about to read 4, iclass 35, count 0 2006.174.01:19:09.60#ibcon#read 4, iclass 35, count 0 2006.174.01:19:09.60#ibcon#about to read 5, iclass 35, count 0 2006.174.01:19:09.60#ibcon#read 5, iclass 35, count 0 2006.174.01:19:09.60#ibcon#about to read 6, iclass 35, count 0 2006.174.01:19:09.60#ibcon#read 6, iclass 35, count 0 2006.174.01:19:09.60#ibcon#end of sib2, iclass 35, count 0 2006.174.01:19:09.60#ibcon#*mode == 0, iclass 35, count 0 2006.174.01:19:09.60#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.174.01:19:09.60#ibcon#[26=FRQ=05,734.99\r\n] 2006.174.01:19:09.60#ibcon#*before write, iclass 35, count 0 2006.174.01:19:09.60#ibcon#enter sib2, iclass 35, count 0 2006.174.01:19:09.60#ibcon#flushed, iclass 35, count 0 2006.174.01:19:09.60#ibcon#about to write, iclass 35, count 0 2006.174.01:19:09.60#ibcon#wrote, iclass 35, count 0 2006.174.01:19:09.60#ibcon#about to read 3, iclass 35, count 0 2006.174.01:19:09.64#ibcon#read 3, iclass 35, count 0 2006.174.01:19:09.64#ibcon#about to read 4, iclass 35, count 0 2006.174.01:19:09.64#ibcon#read 4, iclass 35, count 0 2006.174.01:19:09.64#ibcon#about to read 5, iclass 35, count 0 2006.174.01:19:09.64#ibcon#read 5, iclass 35, count 0 2006.174.01:19:09.64#ibcon#about to read 6, iclass 35, count 0 2006.174.01:19:09.64#ibcon#read 6, iclass 35, count 0 2006.174.01:19:09.64#ibcon#end of sib2, iclass 35, count 0 2006.174.01:19:09.64#ibcon#*after write, iclass 35, count 0 2006.174.01:19:09.64#ibcon#*before return 0, iclass 35, count 0 2006.174.01:19:09.64#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.174.01:19:09.64#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.174.01:19:09.64#ibcon#about to clear, iclass 35 cls_cnt 0 2006.174.01:19:09.64#ibcon#cleared, iclass 35 cls_cnt 0 2006.174.01:19:09.64$vck44/va=5,4 2006.174.01:19:09.64#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.174.01:19:09.64#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.174.01:19:09.64#ibcon#ireg 11 cls_cnt 2 2006.174.01:19:09.64#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.174.01:19:09.70#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.174.01:19:09.70#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.174.01:19:09.70#ibcon#enter wrdev, iclass 37, count 2 2006.174.01:19:09.70#ibcon#first serial, iclass 37, count 2 2006.174.01:19:09.70#ibcon#enter sib2, iclass 37, count 2 2006.174.01:19:09.70#ibcon#flushed, iclass 37, count 2 2006.174.01:19:09.70#ibcon#about to write, iclass 37, count 2 2006.174.01:19:09.70#ibcon#wrote, iclass 37, count 2 2006.174.01:19:09.70#ibcon#about to read 3, iclass 37, count 2 2006.174.01:19:09.72#ibcon#read 3, iclass 37, count 2 2006.174.01:19:09.72#ibcon#about to read 4, iclass 37, count 2 2006.174.01:19:09.72#ibcon#read 4, iclass 37, count 2 2006.174.01:19:09.72#ibcon#about to read 5, iclass 37, count 2 2006.174.01:19:09.72#ibcon#read 5, iclass 37, count 2 2006.174.01:19:09.72#ibcon#about to read 6, iclass 37, count 2 2006.174.01:19:09.72#ibcon#read 6, iclass 37, count 2 2006.174.01:19:09.72#ibcon#end of sib2, iclass 37, count 2 2006.174.01:19:09.72#ibcon#*mode == 0, iclass 37, count 2 2006.174.01:19:09.72#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.174.01:19:09.72#ibcon#[25=AT05-04\r\n] 2006.174.01:19:09.72#ibcon#*before write, iclass 37, count 2 2006.174.01:19:09.72#ibcon#enter sib2, iclass 37, count 2 2006.174.01:19:09.72#ibcon#flushed, iclass 37, count 2 2006.174.01:19:09.72#ibcon#about to write, iclass 37, count 2 2006.174.01:19:09.72#ibcon#wrote, iclass 37, count 2 2006.174.01:19:09.72#ibcon#about to read 3, iclass 37, count 2 2006.174.01:19:09.75#ibcon#read 3, iclass 37, count 2 2006.174.01:19:09.75#ibcon#about to read 4, iclass 37, count 2 2006.174.01:19:09.75#ibcon#read 4, iclass 37, count 2 2006.174.01:19:09.75#ibcon#about to read 5, iclass 37, count 2 2006.174.01:19:09.75#ibcon#read 5, iclass 37, count 2 2006.174.01:19:09.75#ibcon#about to read 6, iclass 37, count 2 2006.174.01:19:09.75#ibcon#read 6, iclass 37, count 2 2006.174.01:19:09.75#ibcon#end of sib2, iclass 37, count 2 2006.174.01:19:09.75#ibcon#*after write, iclass 37, count 2 2006.174.01:19:09.75#ibcon#*before return 0, iclass 37, count 2 2006.174.01:19:09.75#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.174.01:19:09.75#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.174.01:19:09.75#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.174.01:19:09.75#ibcon#ireg 7 cls_cnt 0 2006.174.01:19:09.75#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.174.01:19:09.87#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.174.01:19:09.87#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.174.01:19:09.87#ibcon#enter wrdev, iclass 37, count 0 2006.174.01:19:09.87#ibcon#first serial, iclass 37, count 0 2006.174.01:19:09.87#ibcon#enter sib2, iclass 37, count 0 2006.174.01:19:09.87#ibcon#flushed, iclass 37, count 0 2006.174.01:19:09.87#ibcon#about to write, iclass 37, count 0 2006.174.01:19:09.87#ibcon#wrote, iclass 37, count 0 2006.174.01:19:09.87#ibcon#about to read 3, iclass 37, count 0 2006.174.01:19:09.89#ibcon#read 3, iclass 37, count 0 2006.174.01:19:09.89#ibcon#about to read 4, iclass 37, count 0 2006.174.01:19:09.89#ibcon#read 4, iclass 37, count 0 2006.174.01:19:09.89#ibcon#about to read 5, iclass 37, count 0 2006.174.01:19:09.89#ibcon#read 5, iclass 37, count 0 2006.174.01:19:09.89#ibcon#about to read 6, iclass 37, count 0 2006.174.01:19:09.89#ibcon#read 6, iclass 37, count 0 2006.174.01:19:09.89#ibcon#end of sib2, iclass 37, count 0 2006.174.01:19:09.89#ibcon#*mode == 0, iclass 37, count 0 2006.174.01:19:09.89#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.174.01:19:09.89#ibcon#[25=USB\r\n] 2006.174.01:19:09.89#ibcon#*before write, iclass 37, count 0 2006.174.01:19:09.89#ibcon#enter sib2, iclass 37, count 0 2006.174.01:19:09.89#ibcon#flushed, iclass 37, count 0 2006.174.01:19:09.89#ibcon#about to write, iclass 37, count 0 2006.174.01:19:09.89#ibcon#wrote, iclass 37, count 0 2006.174.01:19:09.89#ibcon#about to read 3, iclass 37, count 0 2006.174.01:19:09.92#ibcon#read 3, iclass 37, count 0 2006.174.01:19:09.92#ibcon#about to read 4, iclass 37, count 0 2006.174.01:19:09.92#ibcon#read 4, iclass 37, count 0 2006.174.01:19:09.92#ibcon#about to read 5, iclass 37, count 0 2006.174.01:19:09.92#ibcon#read 5, iclass 37, count 0 2006.174.01:19:09.92#ibcon#about to read 6, iclass 37, count 0 2006.174.01:19:09.92#ibcon#read 6, iclass 37, count 0 2006.174.01:19:09.92#ibcon#end of sib2, iclass 37, count 0 2006.174.01:19:09.92#ibcon#*after write, iclass 37, count 0 2006.174.01:19:09.92#ibcon#*before return 0, iclass 37, count 0 2006.174.01:19:09.92#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.174.01:19:09.92#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.174.01:19:09.92#ibcon#about to clear, iclass 37 cls_cnt 0 2006.174.01:19:09.92#ibcon#cleared, iclass 37 cls_cnt 0 2006.174.01:19:09.92$vck44/valo=6,814.99 2006.174.01:19:09.92#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.174.01:19:09.92#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.174.01:19:09.92#ibcon#ireg 17 cls_cnt 0 2006.174.01:19:09.92#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.174.01:19:09.92#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.174.01:19:09.92#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.174.01:19:09.92#ibcon#enter wrdev, iclass 39, count 0 2006.174.01:19:09.92#ibcon#first serial, iclass 39, count 0 2006.174.01:19:09.92#ibcon#enter sib2, iclass 39, count 0 2006.174.01:19:09.92#ibcon#flushed, iclass 39, count 0 2006.174.01:19:09.92#ibcon#about to write, iclass 39, count 0 2006.174.01:19:09.92#ibcon#wrote, iclass 39, count 0 2006.174.01:19:09.92#ibcon#about to read 3, iclass 39, count 0 2006.174.01:19:09.94#ibcon#read 3, iclass 39, count 0 2006.174.01:19:09.94#ibcon#about to read 4, iclass 39, count 0 2006.174.01:19:09.94#ibcon#read 4, iclass 39, count 0 2006.174.01:19:09.94#ibcon#about to read 5, iclass 39, count 0 2006.174.01:19:09.94#ibcon#read 5, iclass 39, count 0 2006.174.01:19:09.94#ibcon#about to read 6, iclass 39, count 0 2006.174.01:19:09.94#ibcon#read 6, iclass 39, count 0 2006.174.01:19:09.94#ibcon#end of sib2, iclass 39, count 0 2006.174.01:19:09.94#ibcon#*mode == 0, iclass 39, count 0 2006.174.01:19:09.94#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.174.01:19:09.94#ibcon#[26=FRQ=06,814.99\r\n] 2006.174.01:19:09.94#ibcon#*before write, iclass 39, count 0 2006.174.01:19:09.94#ibcon#enter sib2, iclass 39, count 0 2006.174.01:19:09.94#ibcon#flushed, iclass 39, count 0 2006.174.01:19:09.94#ibcon#about to write, iclass 39, count 0 2006.174.01:19:09.94#ibcon#wrote, iclass 39, count 0 2006.174.01:19:09.94#ibcon#about to read 3, iclass 39, count 0 2006.174.01:19:09.98#ibcon#read 3, iclass 39, count 0 2006.174.01:19:09.98#ibcon#about to read 4, iclass 39, count 0 2006.174.01:19:09.98#ibcon#read 4, iclass 39, count 0 2006.174.01:19:09.98#ibcon#about to read 5, iclass 39, count 0 2006.174.01:19:09.98#ibcon#read 5, iclass 39, count 0 2006.174.01:19:09.98#ibcon#about to read 6, iclass 39, count 0 2006.174.01:19:09.98#ibcon#read 6, iclass 39, count 0 2006.174.01:19:09.98#ibcon#end of sib2, iclass 39, count 0 2006.174.01:19:09.98#ibcon#*after write, iclass 39, count 0 2006.174.01:19:09.98#ibcon#*before return 0, iclass 39, count 0 2006.174.01:19:09.98#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.174.01:19:09.98#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.174.01:19:09.98#ibcon#about to clear, iclass 39 cls_cnt 0 2006.174.01:19:09.98#ibcon#cleared, iclass 39 cls_cnt 0 2006.174.01:19:09.98$vck44/va=6,3 2006.174.01:19:09.98#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.174.01:19:09.98#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.174.01:19:09.98#ibcon#ireg 11 cls_cnt 2 2006.174.01:19:09.98#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.174.01:19:10.04#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.174.01:19:10.04#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.174.01:19:10.04#ibcon#enter wrdev, iclass 3, count 2 2006.174.01:19:10.04#ibcon#first serial, iclass 3, count 2 2006.174.01:19:10.04#ibcon#enter sib2, iclass 3, count 2 2006.174.01:19:10.04#ibcon#flushed, iclass 3, count 2 2006.174.01:19:10.04#ibcon#about to write, iclass 3, count 2 2006.174.01:19:10.04#ibcon#wrote, iclass 3, count 2 2006.174.01:19:10.04#ibcon#about to read 3, iclass 3, count 2 2006.174.01:19:10.06#ibcon#read 3, iclass 3, count 2 2006.174.01:19:10.06#ibcon#about to read 4, iclass 3, count 2 2006.174.01:19:10.06#ibcon#read 4, iclass 3, count 2 2006.174.01:19:10.06#ibcon#about to read 5, iclass 3, count 2 2006.174.01:19:10.06#ibcon#read 5, iclass 3, count 2 2006.174.01:19:10.06#ibcon#about to read 6, iclass 3, count 2 2006.174.01:19:10.06#ibcon#read 6, iclass 3, count 2 2006.174.01:19:10.06#ibcon#end of sib2, iclass 3, count 2 2006.174.01:19:10.06#ibcon#*mode == 0, iclass 3, count 2 2006.174.01:19:10.06#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.174.01:19:10.06#ibcon#[25=AT06-03\r\n] 2006.174.01:19:10.06#ibcon#*before write, iclass 3, count 2 2006.174.01:19:10.06#ibcon#enter sib2, iclass 3, count 2 2006.174.01:19:10.06#ibcon#flushed, iclass 3, count 2 2006.174.01:19:10.06#ibcon#about to write, iclass 3, count 2 2006.174.01:19:10.06#ibcon#wrote, iclass 3, count 2 2006.174.01:19:10.06#ibcon#about to read 3, iclass 3, count 2 2006.174.01:19:10.09#ibcon#read 3, iclass 3, count 2 2006.174.01:19:10.09#ibcon#about to read 4, iclass 3, count 2 2006.174.01:19:10.09#ibcon#read 4, iclass 3, count 2 2006.174.01:19:10.09#ibcon#about to read 5, iclass 3, count 2 2006.174.01:19:10.09#ibcon#read 5, iclass 3, count 2 2006.174.01:19:10.09#ibcon#about to read 6, iclass 3, count 2 2006.174.01:19:10.09#ibcon#read 6, iclass 3, count 2 2006.174.01:19:10.09#ibcon#end of sib2, iclass 3, count 2 2006.174.01:19:10.09#ibcon#*after write, iclass 3, count 2 2006.174.01:19:10.09#ibcon#*before return 0, iclass 3, count 2 2006.174.01:19:10.09#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.174.01:19:10.09#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.174.01:19:10.09#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.174.01:19:10.09#ibcon#ireg 7 cls_cnt 0 2006.174.01:19:10.09#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.174.01:19:10.21#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.174.01:19:10.21#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.174.01:19:10.21#ibcon#enter wrdev, iclass 3, count 0 2006.174.01:19:10.21#ibcon#first serial, iclass 3, count 0 2006.174.01:19:10.21#ibcon#enter sib2, iclass 3, count 0 2006.174.01:19:10.21#ibcon#flushed, iclass 3, count 0 2006.174.01:19:10.21#ibcon#about to write, iclass 3, count 0 2006.174.01:19:10.21#ibcon#wrote, iclass 3, count 0 2006.174.01:19:10.21#ibcon#about to read 3, iclass 3, count 0 2006.174.01:19:10.23#ibcon#read 3, iclass 3, count 0 2006.174.01:19:10.23#ibcon#about to read 4, iclass 3, count 0 2006.174.01:19:10.23#ibcon#read 4, iclass 3, count 0 2006.174.01:19:10.23#ibcon#about to read 5, iclass 3, count 0 2006.174.01:19:10.23#ibcon#read 5, iclass 3, count 0 2006.174.01:19:10.23#ibcon#about to read 6, iclass 3, count 0 2006.174.01:19:10.23#ibcon#read 6, iclass 3, count 0 2006.174.01:19:10.23#ibcon#end of sib2, iclass 3, count 0 2006.174.01:19:10.23#ibcon#*mode == 0, iclass 3, count 0 2006.174.01:19:10.23#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.174.01:19:10.23#ibcon#[25=USB\r\n] 2006.174.01:19:10.23#ibcon#*before write, iclass 3, count 0 2006.174.01:19:10.23#ibcon#enter sib2, iclass 3, count 0 2006.174.01:19:10.23#ibcon#flushed, iclass 3, count 0 2006.174.01:19:10.23#ibcon#about to write, iclass 3, count 0 2006.174.01:19:10.23#ibcon#wrote, iclass 3, count 0 2006.174.01:19:10.23#ibcon#about to read 3, iclass 3, count 0 2006.174.01:19:10.26#ibcon#read 3, iclass 3, count 0 2006.174.01:19:10.26#ibcon#about to read 4, iclass 3, count 0 2006.174.01:19:10.26#ibcon#read 4, iclass 3, count 0 2006.174.01:19:10.26#ibcon#about to read 5, iclass 3, count 0 2006.174.01:19:10.26#ibcon#read 5, iclass 3, count 0 2006.174.01:19:10.26#ibcon#about to read 6, iclass 3, count 0 2006.174.01:19:10.26#ibcon#read 6, iclass 3, count 0 2006.174.01:19:10.26#ibcon#end of sib2, iclass 3, count 0 2006.174.01:19:10.26#ibcon#*after write, iclass 3, count 0 2006.174.01:19:10.26#ibcon#*before return 0, iclass 3, count 0 2006.174.01:19:10.26#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.174.01:19:10.26#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.174.01:19:10.26#ibcon#about to clear, iclass 3 cls_cnt 0 2006.174.01:19:10.26#ibcon#cleared, iclass 3 cls_cnt 0 2006.174.01:19:10.26$vck44/valo=7,864.99 2006.174.01:19:10.26#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.174.01:19:10.26#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.174.01:19:10.26#ibcon#ireg 17 cls_cnt 0 2006.174.01:19:10.26#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.174.01:19:10.26#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.174.01:19:10.26#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.174.01:19:10.26#ibcon#enter wrdev, iclass 5, count 0 2006.174.01:19:10.26#ibcon#first serial, iclass 5, count 0 2006.174.01:19:10.26#ibcon#enter sib2, iclass 5, count 0 2006.174.01:19:10.26#ibcon#flushed, iclass 5, count 0 2006.174.01:19:10.26#ibcon#about to write, iclass 5, count 0 2006.174.01:19:10.26#ibcon#wrote, iclass 5, count 0 2006.174.01:19:10.26#ibcon#about to read 3, iclass 5, count 0 2006.174.01:19:10.28#ibcon#read 3, iclass 5, count 0 2006.174.01:19:10.28#ibcon#about to read 4, iclass 5, count 0 2006.174.01:19:10.28#ibcon#read 4, iclass 5, count 0 2006.174.01:19:10.28#ibcon#about to read 5, iclass 5, count 0 2006.174.01:19:10.28#ibcon#read 5, iclass 5, count 0 2006.174.01:19:10.28#ibcon#about to read 6, iclass 5, count 0 2006.174.01:19:10.28#ibcon#read 6, iclass 5, count 0 2006.174.01:19:10.28#ibcon#end of sib2, iclass 5, count 0 2006.174.01:19:10.28#ibcon#*mode == 0, iclass 5, count 0 2006.174.01:19:10.28#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.174.01:19:10.28#ibcon#[26=FRQ=07,864.99\r\n] 2006.174.01:19:10.28#ibcon#*before write, iclass 5, count 0 2006.174.01:19:10.28#ibcon#enter sib2, iclass 5, count 0 2006.174.01:19:10.28#ibcon#flushed, iclass 5, count 0 2006.174.01:19:10.28#ibcon#about to write, iclass 5, count 0 2006.174.01:19:10.28#ibcon#wrote, iclass 5, count 0 2006.174.01:19:10.28#ibcon#about to read 3, iclass 5, count 0 2006.174.01:19:10.32#ibcon#read 3, iclass 5, count 0 2006.174.01:19:10.32#ibcon#about to read 4, iclass 5, count 0 2006.174.01:19:10.32#ibcon#read 4, iclass 5, count 0 2006.174.01:19:10.32#ibcon#about to read 5, iclass 5, count 0 2006.174.01:19:10.32#ibcon#read 5, iclass 5, count 0 2006.174.01:19:10.32#ibcon#about to read 6, iclass 5, count 0 2006.174.01:19:10.32#ibcon#read 6, iclass 5, count 0 2006.174.01:19:10.32#ibcon#end of sib2, iclass 5, count 0 2006.174.01:19:10.32#ibcon#*after write, iclass 5, count 0 2006.174.01:19:10.32#ibcon#*before return 0, iclass 5, count 0 2006.174.01:19:10.32#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.174.01:19:10.32#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.174.01:19:10.32#ibcon#about to clear, iclass 5 cls_cnt 0 2006.174.01:19:10.32#ibcon#cleared, iclass 5 cls_cnt 0 2006.174.01:19:10.32$vck44/va=7,4 2006.174.01:19:10.32#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.174.01:19:10.32#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.174.01:19:10.32#ibcon#ireg 11 cls_cnt 2 2006.174.01:19:10.32#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.174.01:19:10.38#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.174.01:19:10.38#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.174.01:19:10.38#ibcon#enter wrdev, iclass 7, count 2 2006.174.01:19:10.38#ibcon#first serial, iclass 7, count 2 2006.174.01:19:10.38#ibcon#enter sib2, iclass 7, count 2 2006.174.01:19:10.38#ibcon#flushed, iclass 7, count 2 2006.174.01:19:10.38#ibcon#about to write, iclass 7, count 2 2006.174.01:19:10.38#ibcon#wrote, iclass 7, count 2 2006.174.01:19:10.38#ibcon#about to read 3, iclass 7, count 2 2006.174.01:19:10.40#ibcon#read 3, iclass 7, count 2 2006.174.01:19:10.40#ibcon#about to read 4, iclass 7, count 2 2006.174.01:19:10.40#ibcon#read 4, iclass 7, count 2 2006.174.01:19:10.40#ibcon#about to read 5, iclass 7, count 2 2006.174.01:19:10.40#ibcon#read 5, iclass 7, count 2 2006.174.01:19:10.40#ibcon#about to read 6, iclass 7, count 2 2006.174.01:19:10.40#ibcon#read 6, iclass 7, count 2 2006.174.01:19:10.40#ibcon#end of sib2, iclass 7, count 2 2006.174.01:19:10.40#ibcon#*mode == 0, iclass 7, count 2 2006.174.01:19:10.40#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.174.01:19:10.40#ibcon#[25=AT07-04\r\n] 2006.174.01:19:10.40#ibcon#*before write, iclass 7, count 2 2006.174.01:19:10.40#ibcon#enter sib2, iclass 7, count 2 2006.174.01:19:10.40#ibcon#flushed, iclass 7, count 2 2006.174.01:19:10.40#ibcon#about to write, iclass 7, count 2 2006.174.01:19:10.40#ibcon#wrote, iclass 7, count 2 2006.174.01:19:10.40#ibcon#about to read 3, iclass 7, count 2 2006.174.01:19:10.43#ibcon#read 3, iclass 7, count 2 2006.174.01:19:10.43#ibcon#about to read 4, iclass 7, count 2 2006.174.01:19:10.43#ibcon#read 4, iclass 7, count 2 2006.174.01:19:10.43#ibcon#about to read 5, iclass 7, count 2 2006.174.01:19:10.43#ibcon#read 5, iclass 7, count 2 2006.174.01:19:10.43#ibcon#about to read 6, iclass 7, count 2 2006.174.01:19:10.43#ibcon#read 6, iclass 7, count 2 2006.174.01:19:10.43#ibcon#end of sib2, iclass 7, count 2 2006.174.01:19:10.43#ibcon#*after write, iclass 7, count 2 2006.174.01:19:10.43#ibcon#*before return 0, iclass 7, count 2 2006.174.01:19:10.43#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.174.01:19:10.43#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.174.01:19:10.43#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.174.01:19:10.43#ibcon#ireg 7 cls_cnt 0 2006.174.01:19:10.43#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.174.01:19:10.55#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.174.01:19:10.55#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.174.01:19:10.55#ibcon#enter wrdev, iclass 7, count 0 2006.174.01:19:10.55#ibcon#first serial, iclass 7, count 0 2006.174.01:19:10.55#ibcon#enter sib2, iclass 7, count 0 2006.174.01:19:10.55#ibcon#flushed, iclass 7, count 0 2006.174.01:19:10.55#ibcon#about to write, iclass 7, count 0 2006.174.01:19:10.55#ibcon#wrote, iclass 7, count 0 2006.174.01:19:10.55#ibcon#about to read 3, iclass 7, count 0 2006.174.01:19:10.57#ibcon#read 3, iclass 7, count 0 2006.174.01:19:10.57#ibcon#about to read 4, iclass 7, count 0 2006.174.01:19:10.57#ibcon#read 4, iclass 7, count 0 2006.174.01:19:10.57#ibcon#about to read 5, iclass 7, count 0 2006.174.01:19:10.57#ibcon#read 5, iclass 7, count 0 2006.174.01:19:10.57#ibcon#about to read 6, iclass 7, count 0 2006.174.01:19:10.57#ibcon#read 6, iclass 7, count 0 2006.174.01:19:10.57#ibcon#end of sib2, iclass 7, count 0 2006.174.01:19:10.57#ibcon#*mode == 0, iclass 7, count 0 2006.174.01:19:10.57#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.174.01:19:10.57#ibcon#[25=USB\r\n] 2006.174.01:19:10.57#ibcon#*before write, iclass 7, count 0 2006.174.01:19:10.57#ibcon#enter sib2, iclass 7, count 0 2006.174.01:19:10.57#ibcon#flushed, iclass 7, count 0 2006.174.01:19:10.57#ibcon#about to write, iclass 7, count 0 2006.174.01:19:10.57#ibcon#wrote, iclass 7, count 0 2006.174.01:19:10.57#ibcon#about to read 3, iclass 7, count 0 2006.174.01:19:10.60#ibcon#read 3, iclass 7, count 0 2006.174.01:19:10.60#ibcon#about to read 4, iclass 7, count 0 2006.174.01:19:10.60#ibcon#read 4, iclass 7, count 0 2006.174.01:19:10.60#ibcon#about to read 5, iclass 7, count 0 2006.174.01:19:10.60#ibcon#read 5, iclass 7, count 0 2006.174.01:19:10.60#ibcon#about to read 6, iclass 7, count 0 2006.174.01:19:10.60#ibcon#read 6, iclass 7, count 0 2006.174.01:19:10.60#ibcon#end of sib2, iclass 7, count 0 2006.174.01:19:10.60#ibcon#*after write, iclass 7, count 0 2006.174.01:19:10.60#ibcon#*before return 0, iclass 7, count 0 2006.174.01:19:10.60#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.174.01:19:10.60#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.174.01:19:10.60#ibcon#about to clear, iclass 7 cls_cnt 0 2006.174.01:19:10.60#ibcon#cleared, iclass 7 cls_cnt 0 2006.174.01:19:10.60$vck44/valo=8,884.99 2006.174.01:19:10.60#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.174.01:19:10.60#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.174.01:19:10.60#ibcon#ireg 17 cls_cnt 0 2006.174.01:19:10.60#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.174.01:19:10.60#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.174.01:19:10.60#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.174.01:19:10.60#ibcon#enter wrdev, iclass 11, count 0 2006.174.01:19:10.60#ibcon#first serial, iclass 11, count 0 2006.174.01:19:10.60#ibcon#enter sib2, iclass 11, count 0 2006.174.01:19:10.60#ibcon#flushed, iclass 11, count 0 2006.174.01:19:10.60#ibcon#about to write, iclass 11, count 0 2006.174.01:19:10.60#ibcon#wrote, iclass 11, count 0 2006.174.01:19:10.60#ibcon#about to read 3, iclass 11, count 0 2006.174.01:19:10.62#ibcon#read 3, iclass 11, count 0 2006.174.01:19:10.62#ibcon#about to read 4, iclass 11, count 0 2006.174.01:19:10.62#ibcon#read 4, iclass 11, count 0 2006.174.01:19:10.62#ibcon#about to read 5, iclass 11, count 0 2006.174.01:19:10.62#ibcon#read 5, iclass 11, count 0 2006.174.01:19:10.62#ibcon#about to read 6, iclass 11, count 0 2006.174.01:19:10.62#ibcon#read 6, iclass 11, count 0 2006.174.01:19:10.62#ibcon#end of sib2, iclass 11, count 0 2006.174.01:19:10.62#ibcon#*mode == 0, iclass 11, count 0 2006.174.01:19:10.62#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.174.01:19:10.62#ibcon#[26=FRQ=08,884.99\r\n] 2006.174.01:19:10.62#ibcon#*before write, iclass 11, count 0 2006.174.01:19:10.62#ibcon#enter sib2, iclass 11, count 0 2006.174.01:19:10.62#ibcon#flushed, iclass 11, count 0 2006.174.01:19:10.62#ibcon#about to write, iclass 11, count 0 2006.174.01:19:10.62#ibcon#wrote, iclass 11, count 0 2006.174.01:19:10.62#ibcon#about to read 3, iclass 11, count 0 2006.174.01:19:10.66#ibcon#read 3, iclass 11, count 0 2006.174.01:19:10.66#ibcon#about to read 4, iclass 11, count 0 2006.174.01:19:10.66#ibcon#read 4, iclass 11, count 0 2006.174.01:19:10.66#ibcon#about to read 5, iclass 11, count 0 2006.174.01:19:10.66#ibcon#read 5, iclass 11, count 0 2006.174.01:19:10.66#ibcon#about to read 6, iclass 11, count 0 2006.174.01:19:10.66#ibcon#read 6, iclass 11, count 0 2006.174.01:19:10.66#ibcon#end of sib2, iclass 11, count 0 2006.174.01:19:10.66#ibcon#*after write, iclass 11, count 0 2006.174.01:19:10.66#ibcon#*before return 0, iclass 11, count 0 2006.174.01:19:10.66#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.174.01:19:10.66#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.174.01:19:10.66#ibcon#about to clear, iclass 11 cls_cnt 0 2006.174.01:19:10.66#ibcon#cleared, iclass 11 cls_cnt 0 2006.174.01:19:10.66$vck44/va=8,4 2006.174.01:19:10.66#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.174.01:19:10.66#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.174.01:19:10.66#ibcon#ireg 11 cls_cnt 2 2006.174.01:19:10.66#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.174.01:19:10.72#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.174.01:19:10.72#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.174.01:19:10.72#ibcon#enter wrdev, iclass 13, count 2 2006.174.01:19:10.72#ibcon#first serial, iclass 13, count 2 2006.174.01:19:10.72#ibcon#enter sib2, iclass 13, count 2 2006.174.01:19:10.72#ibcon#flushed, iclass 13, count 2 2006.174.01:19:10.72#ibcon#about to write, iclass 13, count 2 2006.174.01:19:10.72#ibcon#wrote, iclass 13, count 2 2006.174.01:19:10.72#ibcon#about to read 3, iclass 13, count 2 2006.174.01:19:10.74#ibcon#read 3, iclass 13, count 2 2006.174.01:19:10.74#ibcon#about to read 4, iclass 13, count 2 2006.174.01:19:10.74#ibcon#read 4, iclass 13, count 2 2006.174.01:19:10.74#ibcon#about to read 5, iclass 13, count 2 2006.174.01:19:10.74#ibcon#read 5, iclass 13, count 2 2006.174.01:19:10.74#ibcon#about to read 6, iclass 13, count 2 2006.174.01:19:10.74#ibcon#read 6, iclass 13, count 2 2006.174.01:19:10.74#ibcon#end of sib2, iclass 13, count 2 2006.174.01:19:10.74#ibcon#*mode == 0, iclass 13, count 2 2006.174.01:19:10.74#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.174.01:19:10.74#ibcon#[25=AT08-04\r\n] 2006.174.01:19:10.74#ibcon#*before write, iclass 13, count 2 2006.174.01:19:10.74#ibcon#enter sib2, iclass 13, count 2 2006.174.01:19:10.74#ibcon#flushed, iclass 13, count 2 2006.174.01:19:10.74#ibcon#about to write, iclass 13, count 2 2006.174.01:19:10.74#ibcon#wrote, iclass 13, count 2 2006.174.01:19:10.74#ibcon#about to read 3, iclass 13, count 2 2006.174.01:19:10.77#ibcon#read 3, iclass 13, count 2 2006.174.01:19:10.77#ibcon#about to read 4, iclass 13, count 2 2006.174.01:19:10.77#ibcon#read 4, iclass 13, count 2 2006.174.01:19:10.77#ibcon#about to read 5, iclass 13, count 2 2006.174.01:19:10.77#ibcon#read 5, iclass 13, count 2 2006.174.01:19:10.77#ibcon#about to read 6, iclass 13, count 2 2006.174.01:19:10.77#ibcon#read 6, iclass 13, count 2 2006.174.01:19:10.77#ibcon#end of sib2, iclass 13, count 2 2006.174.01:19:10.77#ibcon#*after write, iclass 13, count 2 2006.174.01:19:10.77#ibcon#*before return 0, iclass 13, count 2 2006.174.01:19:10.77#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.174.01:19:10.77#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.174.01:19:10.77#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.174.01:19:10.77#ibcon#ireg 7 cls_cnt 0 2006.174.01:19:10.77#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.174.01:19:10.89#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.174.01:19:10.89#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.174.01:19:10.89#ibcon#enter wrdev, iclass 13, count 0 2006.174.01:19:10.89#ibcon#first serial, iclass 13, count 0 2006.174.01:19:10.89#ibcon#enter sib2, iclass 13, count 0 2006.174.01:19:10.89#ibcon#flushed, iclass 13, count 0 2006.174.01:19:10.89#ibcon#about to write, iclass 13, count 0 2006.174.01:19:10.89#ibcon#wrote, iclass 13, count 0 2006.174.01:19:10.89#ibcon#about to read 3, iclass 13, count 0 2006.174.01:19:10.91#ibcon#read 3, iclass 13, count 0 2006.174.01:19:10.91#ibcon#about to read 4, iclass 13, count 0 2006.174.01:19:10.91#ibcon#read 4, iclass 13, count 0 2006.174.01:19:10.91#ibcon#about to read 5, iclass 13, count 0 2006.174.01:19:10.91#ibcon#read 5, iclass 13, count 0 2006.174.01:19:10.91#ibcon#about to read 6, iclass 13, count 0 2006.174.01:19:10.91#ibcon#read 6, iclass 13, count 0 2006.174.01:19:10.91#ibcon#end of sib2, iclass 13, count 0 2006.174.01:19:10.91#ibcon#*mode == 0, iclass 13, count 0 2006.174.01:19:10.91#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.174.01:19:10.91#ibcon#[25=USB\r\n] 2006.174.01:19:10.91#ibcon#*before write, iclass 13, count 0 2006.174.01:19:10.91#ibcon#enter sib2, iclass 13, count 0 2006.174.01:19:10.91#ibcon#flushed, iclass 13, count 0 2006.174.01:19:10.91#ibcon#about to write, iclass 13, count 0 2006.174.01:19:10.91#ibcon#wrote, iclass 13, count 0 2006.174.01:19:10.91#ibcon#about to read 3, iclass 13, count 0 2006.174.01:19:10.94#ibcon#read 3, iclass 13, count 0 2006.174.01:19:10.94#ibcon#about to read 4, iclass 13, count 0 2006.174.01:19:10.94#ibcon#read 4, iclass 13, count 0 2006.174.01:19:10.94#ibcon#about to read 5, iclass 13, count 0 2006.174.01:19:10.94#ibcon#read 5, iclass 13, count 0 2006.174.01:19:10.94#ibcon#about to read 6, iclass 13, count 0 2006.174.01:19:10.94#ibcon#read 6, iclass 13, count 0 2006.174.01:19:10.94#ibcon#end of sib2, iclass 13, count 0 2006.174.01:19:10.94#ibcon#*after write, iclass 13, count 0 2006.174.01:19:10.94#ibcon#*before return 0, iclass 13, count 0 2006.174.01:19:10.94#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.174.01:19:10.94#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.174.01:19:10.94#ibcon#about to clear, iclass 13 cls_cnt 0 2006.174.01:19:10.94#ibcon#cleared, iclass 13 cls_cnt 0 2006.174.01:19:10.94$vck44/vblo=1,629.99 2006.174.01:19:10.94#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.174.01:19:10.94#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.174.01:19:10.94#ibcon#ireg 17 cls_cnt 0 2006.174.01:19:10.94#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.174.01:19:10.94#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.174.01:19:10.94#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.174.01:19:10.94#ibcon#enter wrdev, iclass 15, count 0 2006.174.01:19:10.94#ibcon#first serial, iclass 15, count 0 2006.174.01:19:10.94#ibcon#enter sib2, iclass 15, count 0 2006.174.01:19:10.94#ibcon#flushed, iclass 15, count 0 2006.174.01:19:10.94#ibcon#about to write, iclass 15, count 0 2006.174.01:19:10.94#ibcon#wrote, iclass 15, count 0 2006.174.01:19:10.94#ibcon#about to read 3, iclass 15, count 0 2006.174.01:19:10.96#ibcon#read 3, iclass 15, count 0 2006.174.01:19:10.96#ibcon#about to read 4, iclass 15, count 0 2006.174.01:19:10.96#ibcon#read 4, iclass 15, count 0 2006.174.01:19:10.96#ibcon#about to read 5, iclass 15, count 0 2006.174.01:19:10.96#ibcon#read 5, iclass 15, count 0 2006.174.01:19:10.96#ibcon#about to read 6, iclass 15, count 0 2006.174.01:19:10.96#ibcon#read 6, iclass 15, count 0 2006.174.01:19:10.96#ibcon#end of sib2, iclass 15, count 0 2006.174.01:19:10.96#ibcon#*mode == 0, iclass 15, count 0 2006.174.01:19:10.96#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.174.01:19:10.96#ibcon#[28=FRQ=01,629.99\r\n] 2006.174.01:19:10.96#ibcon#*before write, iclass 15, count 0 2006.174.01:19:10.96#ibcon#enter sib2, iclass 15, count 0 2006.174.01:19:10.96#ibcon#flushed, iclass 15, count 0 2006.174.01:19:10.96#ibcon#about to write, iclass 15, count 0 2006.174.01:19:10.96#ibcon#wrote, iclass 15, count 0 2006.174.01:19:10.96#ibcon#about to read 3, iclass 15, count 0 2006.174.01:19:11.00#ibcon#read 3, iclass 15, count 0 2006.174.01:19:11.00#ibcon#about to read 4, iclass 15, count 0 2006.174.01:19:11.00#ibcon#read 4, iclass 15, count 0 2006.174.01:19:11.00#ibcon#about to read 5, iclass 15, count 0 2006.174.01:19:11.00#ibcon#read 5, iclass 15, count 0 2006.174.01:19:11.00#ibcon#about to read 6, iclass 15, count 0 2006.174.01:19:11.00#ibcon#read 6, iclass 15, count 0 2006.174.01:19:11.00#ibcon#end of sib2, iclass 15, count 0 2006.174.01:19:11.00#ibcon#*after write, iclass 15, count 0 2006.174.01:19:11.00#ibcon#*before return 0, iclass 15, count 0 2006.174.01:19:11.00#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.174.01:19:11.00#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.174.01:19:11.00#ibcon#about to clear, iclass 15 cls_cnt 0 2006.174.01:19:11.00#ibcon#cleared, iclass 15 cls_cnt 0 2006.174.01:19:11.00$vck44/vb=1,4 2006.174.01:19:11.00#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.174.01:19:11.00#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.174.01:19:11.00#ibcon#ireg 11 cls_cnt 2 2006.174.01:19:11.00#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.174.01:19:11.00#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.174.01:19:11.00#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.174.01:19:11.00#ibcon#enter wrdev, iclass 17, count 2 2006.174.01:19:11.00#ibcon#first serial, iclass 17, count 2 2006.174.01:19:11.00#ibcon#enter sib2, iclass 17, count 2 2006.174.01:19:11.00#ibcon#flushed, iclass 17, count 2 2006.174.01:19:11.00#ibcon#about to write, iclass 17, count 2 2006.174.01:19:11.00#ibcon#wrote, iclass 17, count 2 2006.174.01:19:11.00#ibcon#about to read 3, iclass 17, count 2 2006.174.01:19:11.02#ibcon#read 3, iclass 17, count 2 2006.174.01:19:11.02#ibcon#about to read 4, iclass 17, count 2 2006.174.01:19:11.02#ibcon#read 4, iclass 17, count 2 2006.174.01:19:11.02#ibcon#about to read 5, iclass 17, count 2 2006.174.01:19:11.02#ibcon#read 5, iclass 17, count 2 2006.174.01:19:11.02#ibcon#about to read 6, iclass 17, count 2 2006.174.01:19:11.02#ibcon#read 6, iclass 17, count 2 2006.174.01:19:11.02#ibcon#end of sib2, iclass 17, count 2 2006.174.01:19:11.02#ibcon#*mode == 0, iclass 17, count 2 2006.174.01:19:11.02#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.174.01:19:11.02#ibcon#[27=AT01-04\r\n] 2006.174.01:19:11.02#ibcon#*before write, iclass 17, count 2 2006.174.01:19:11.02#ibcon#enter sib2, iclass 17, count 2 2006.174.01:19:11.02#ibcon#flushed, iclass 17, count 2 2006.174.01:19:11.02#ibcon#about to write, iclass 17, count 2 2006.174.01:19:11.02#ibcon#wrote, iclass 17, count 2 2006.174.01:19:11.02#ibcon#about to read 3, iclass 17, count 2 2006.174.01:19:11.05#ibcon#read 3, iclass 17, count 2 2006.174.01:19:11.05#ibcon#about to read 4, iclass 17, count 2 2006.174.01:19:11.05#ibcon#read 4, iclass 17, count 2 2006.174.01:19:11.05#ibcon#about to read 5, iclass 17, count 2 2006.174.01:19:11.05#ibcon#read 5, iclass 17, count 2 2006.174.01:19:11.05#ibcon#about to read 6, iclass 17, count 2 2006.174.01:19:11.05#ibcon#read 6, iclass 17, count 2 2006.174.01:19:11.05#ibcon#end of sib2, iclass 17, count 2 2006.174.01:19:11.05#ibcon#*after write, iclass 17, count 2 2006.174.01:19:11.05#ibcon#*before return 0, iclass 17, count 2 2006.174.01:19:11.05#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.174.01:19:11.05#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.174.01:19:11.05#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.174.01:19:11.05#ibcon#ireg 7 cls_cnt 0 2006.174.01:19:11.05#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.174.01:19:11.17#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.174.01:19:11.17#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.174.01:19:11.17#ibcon#enter wrdev, iclass 17, count 0 2006.174.01:19:11.17#ibcon#first serial, iclass 17, count 0 2006.174.01:19:11.17#ibcon#enter sib2, iclass 17, count 0 2006.174.01:19:11.17#ibcon#flushed, iclass 17, count 0 2006.174.01:19:11.17#ibcon#about to write, iclass 17, count 0 2006.174.01:19:11.17#ibcon#wrote, iclass 17, count 0 2006.174.01:19:11.17#ibcon#about to read 3, iclass 17, count 0 2006.174.01:19:11.19#ibcon#read 3, iclass 17, count 0 2006.174.01:19:11.19#ibcon#about to read 4, iclass 17, count 0 2006.174.01:19:11.19#ibcon#read 4, iclass 17, count 0 2006.174.01:19:11.19#ibcon#about to read 5, iclass 17, count 0 2006.174.01:19:11.19#ibcon#read 5, iclass 17, count 0 2006.174.01:19:11.19#ibcon#about to read 6, iclass 17, count 0 2006.174.01:19:11.19#ibcon#read 6, iclass 17, count 0 2006.174.01:19:11.19#ibcon#end of sib2, iclass 17, count 0 2006.174.01:19:11.19#ibcon#*mode == 0, iclass 17, count 0 2006.174.01:19:11.19#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.174.01:19:11.19#ibcon#[27=USB\r\n] 2006.174.01:19:11.19#ibcon#*before write, iclass 17, count 0 2006.174.01:19:11.19#ibcon#enter sib2, iclass 17, count 0 2006.174.01:19:11.19#ibcon#flushed, iclass 17, count 0 2006.174.01:19:11.19#ibcon#about to write, iclass 17, count 0 2006.174.01:19:11.19#ibcon#wrote, iclass 17, count 0 2006.174.01:19:11.19#ibcon#about to read 3, iclass 17, count 0 2006.174.01:19:11.22#ibcon#read 3, iclass 17, count 0 2006.174.01:19:11.22#ibcon#about to read 4, iclass 17, count 0 2006.174.01:19:11.22#ibcon#read 4, iclass 17, count 0 2006.174.01:19:11.22#ibcon#about to read 5, iclass 17, count 0 2006.174.01:19:11.22#ibcon#read 5, iclass 17, count 0 2006.174.01:19:11.22#ibcon#about to read 6, iclass 17, count 0 2006.174.01:19:11.22#ibcon#read 6, iclass 17, count 0 2006.174.01:19:11.22#ibcon#end of sib2, iclass 17, count 0 2006.174.01:19:11.22#ibcon#*after write, iclass 17, count 0 2006.174.01:19:11.22#ibcon#*before return 0, iclass 17, count 0 2006.174.01:19:11.22#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.174.01:19:11.22#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.174.01:19:11.22#ibcon#about to clear, iclass 17 cls_cnt 0 2006.174.01:19:11.22#ibcon#cleared, iclass 17 cls_cnt 0 2006.174.01:19:11.22$vck44/vblo=2,634.99 2006.174.01:19:11.22#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.174.01:19:11.22#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.174.01:19:11.22#ibcon#ireg 17 cls_cnt 0 2006.174.01:19:11.22#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.174.01:19:11.22#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.174.01:19:11.22#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.174.01:19:11.22#ibcon#enter wrdev, iclass 19, count 0 2006.174.01:19:11.22#ibcon#first serial, iclass 19, count 0 2006.174.01:19:11.22#ibcon#enter sib2, iclass 19, count 0 2006.174.01:19:11.22#ibcon#flushed, iclass 19, count 0 2006.174.01:19:11.22#ibcon#about to write, iclass 19, count 0 2006.174.01:19:11.22#ibcon#wrote, iclass 19, count 0 2006.174.01:19:11.22#ibcon#about to read 3, iclass 19, count 0 2006.174.01:19:11.24#ibcon#read 3, iclass 19, count 0 2006.174.01:19:11.24#ibcon#about to read 4, iclass 19, count 0 2006.174.01:19:11.24#ibcon#read 4, iclass 19, count 0 2006.174.01:19:11.24#ibcon#about to read 5, iclass 19, count 0 2006.174.01:19:11.24#ibcon#read 5, iclass 19, count 0 2006.174.01:19:11.24#ibcon#about to read 6, iclass 19, count 0 2006.174.01:19:11.24#ibcon#read 6, iclass 19, count 0 2006.174.01:19:11.24#ibcon#end of sib2, iclass 19, count 0 2006.174.01:19:11.24#ibcon#*mode == 0, iclass 19, count 0 2006.174.01:19:11.24#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.174.01:19:11.24#ibcon#[28=FRQ=02,634.99\r\n] 2006.174.01:19:11.24#ibcon#*before write, iclass 19, count 0 2006.174.01:19:11.24#ibcon#enter sib2, iclass 19, count 0 2006.174.01:19:11.24#ibcon#flushed, iclass 19, count 0 2006.174.01:19:11.24#ibcon#about to write, iclass 19, count 0 2006.174.01:19:11.24#ibcon#wrote, iclass 19, count 0 2006.174.01:19:11.24#ibcon#about to read 3, iclass 19, count 0 2006.174.01:19:11.28#ibcon#read 3, iclass 19, count 0 2006.174.01:19:11.28#ibcon#about to read 4, iclass 19, count 0 2006.174.01:19:11.28#ibcon#read 4, iclass 19, count 0 2006.174.01:19:11.28#ibcon#about to read 5, iclass 19, count 0 2006.174.01:19:11.28#ibcon#read 5, iclass 19, count 0 2006.174.01:19:11.28#ibcon#about to read 6, iclass 19, count 0 2006.174.01:19:11.28#ibcon#read 6, iclass 19, count 0 2006.174.01:19:11.28#ibcon#end of sib2, iclass 19, count 0 2006.174.01:19:11.28#ibcon#*after write, iclass 19, count 0 2006.174.01:19:11.28#ibcon#*before return 0, iclass 19, count 0 2006.174.01:19:11.28#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.174.01:19:11.28#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.174.01:19:11.28#ibcon#about to clear, iclass 19 cls_cnt 0 2006.174.01:19:11.28#ibcon#cleared, iclass 19 cls_cnt 0 2006.174.01:19:11.28$vck44/vb=2,4 2006.174.01:19:11.28#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.174.01:19:11.28#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.174.01:19:11.28#ibcon#ireg 11 cls_cnt 2 2006.174.01:19:11.28#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.174.01:19:11.34#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.174.01:19:11.34#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.174.01:19:11.34#ibcon#enter wrdev, iclass 21, count 2 2006.174.01:19:11.34#ibcon#first serial, iclass 21, count 2 2006.174.01:19:11.34#ibcon#enter sib2, iclass 21, count 2 2006.174.01:19:11.34#ibcon#flushed, iclass 21, count 2 2006.174.01:19:11.34#ibcon#about to write, iclass 21, count 2 2006.174.01:19:11.34#ibcon#wrote, iclass 21, count 2 2006.174.01:19:11.34#ibcon#about to read 3, iclass 21, count 2 2006.174.01:19:11.36#ibcon#read 3, iclass 21, count 2 2006.174.01:19:11.36#ibcon#about to read 4, iclass 21, count 2 2006.174.01:19:11.36#ibcon#read 4, iclass 21, count 2 2006.174.01:19:11.36#ibcon#about to read 5, iclass 21, count 2 2006.174.01:19:11.36#ibcon#read 5, iclass 21, count 2 2006.174.01:19:11.36#ibcon#about to read 6, iclass 21, count 2 2006.174.01:19:11.36#ibcon#read 6, iclass 21, count 2 2006.174.01:19:11.36#ibcon#end of sib2, iclass 21, count 2 2006.174.01:19:11.36#ibcon#*mode == 0, iclass 21, count 2 2006.174.01:19:11.36#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.174.01:19:11.36#ibcon#[27=AT02-04\r\n] 2006.174.01:19:11.36#ibcon#*before write, iclass 21, count 2 2006.174.01:19:11.36#ibcon#enter sib2, iclass 21, count 2 2006.174.01:19:11.36#ibcon#flushed, iclass 21, count 2 2006.174.01:19:11.36#ibcon#about to write, iclass 21, count 2 2006.174.01:19:11.36#ibcon#wrote, iclass 21, count 2 2006.174.01:19:11.36#ibcon#about to read 3, iclass 21, count 2 2006.174.01:19:11.39#ibcon#read 3, iclass 21, count 2 2006.174.01:19:11.39#ibcon#about to read 4, iclass 21, count 2 2006.174.01:19:11.39#ibcon#read 4, iclass 21, count 2 2006.174.01:19:11.39#ibcon#about to read 5, iclass 21, count 2 2006.174.01:19:11.39#ibcon#read 5, iclass 21, count 2 2006.174.01:19:11.39#ibcon#about to read 6, iclass 21, count 2 2006.174.01:19:11.39#ibcon#read 6, iclass 21, count 2 2006.174.01:19:11.39#ibcon#end of sib2, iclass 21, count 2 2006.174.01:19:11.39#ibcon#*after write, iclass 21, count 2 2006.174.01:19:11.39#ibcon#*before return 0, iclass 21, count 2 2006.174.01:19:11.39#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.174.01:19:11.39#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.174.01:19:11.39#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.174.01:19:11.39#ibcon#ireg 7 cls_cnt 0 2006.174.01:19:11.39#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.174.01:19:11.51#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.174.01:19:11.51#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.174.01:19:11.51#ibcon#enter wrdev, iclass 21, count 0 2006.174.01:19:11.51#ibcon#first serial, iclass 21, count 0 2006.174.01:19:11.51#ibcon#enter sib2, iclass 21, count 0 2006.174.01:19:11.51#ibcon#flushed, iclass 21, count 0 2006.174.01:19:11.51#ibcon#about to write, iclass 21, count 0 2006.174.01:19:11.51#ibcon#wrote, iclass 21, count 0 2006.174.01:19:11.51#ibcon#about to read 3, iclass 21, count 0 2006.174.01:19:11.53#ibcon#read 3, iclass 21, count 0 2006.174.01:19:11.53#ibcon#about to read 4, iclass 21, count 0 2006.174.01:19:11.53#ibcon#read 4, iclass 21, count 0 2006.174.01:19:11.53#ibcon#about to read 5, iclass 21, count 0 2006.174.01:19:11.53#ibcon#read 5, iclass 21, count 0 2006.174.01:19:11.53#ibcon#about to read 6, iclass 21, count 0 2006.174.01:19:11.53#ibcon#read 6, iclass 21, count 0 2006.174.01:19:11.53#ibcon#end of sib2, iclass 21, count 0 2006.174.01:19:11.53#ibcon#*mode == 0, iclass 21, count 0 2006.174.01:19:11.53#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.174.01:19:11.53#ibcon#[27=USB\r\n] 2006.174.01:19:11.53#ibcon#*before write, iclass 21, count 0 2006.174.01:19:11.53#ibcon#enter sib2, iclass 21, count 0 2006.174.01:19:11.53#ibcon#flushed, iclass 21, count 0 2006.174.01:19:11.53#ibcon#about to write, iclass 21, count 0 2006.174.01:19:11.53#ibcon#wrote, iclass 21, count 0 2006.174.01:19:11.53#ibcon#about to read 3, iclass 21, count 0 2006.174.01:19:11.56#ibcon#read 3, iclass 21, count 0 2006.174.01:19:11.56#ibcon#about to read 4, iclass 21, count 0 2006.174.01:19:11.56#ibcon#read 4, iclass 21, count 0 2006.174.01:19:11.56#ibcon#about to read 5, iclass 21, count 0 2006.174.01:19:11.56#ibcon#read 5, iclass 21, count 0 2006.174.01:19:11.56#ibcon#about to read 6, iclass 21, count 0 2006.174.01:19:11.56#ibcon#read 6, iclass 21, count 0 2006.174.01:19:11.56#ibcon#end of sib2, iclass 21, count 0 2006.174.01:19:11.56#ibcon#*after write, iclass 21, count 0 2006.174.01:19:11.56#ibcon#*before return 0, iclass 21, count 0 2006.174.01:19:11.56#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.174.01:19:11.56#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.174.01:19:11.56#ibcon#about to clear, iclass 21 cls_cnt 0 2006.174.01:19:11.56#ibcon#cleared, iclass 21 cls_cnt 0 2006.174.01:19:11.56$vck44/vblo=3,649.99 2006.174.01:19:11.56#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.174.01:19:11.56#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.174.01:19:11.56#ibcon#ireg 17 cls_cnt 0 2006.174.01:19:11.56#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.174.01:19:11.56#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.174.01:19:11.56#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.174.01:19:11.56#ibcon#enter wrdev, iclass 23, count 0 2006.174.01:19:11.56#ibcon#first serial, iclass 23, count 0 2006.174.01:19:11.56#ibcon#enter sib2, iclass 23, count 0 2006.174.01:19:11.56#ibcon#flushed, iclass 23, count 0 2006.174.01:19:11.56#ibcon#about to write, iclass 23, count 0 2006.174.01:19:11.56#ibcon#wrote, iclass 23, count 0 2006.174.01:19:11.56#ibcon#about to read 3, iclass 23, count 0 2006.174.01:19:11.58#ibcon#read 3, iclass 23, count 0 2006.174.01:19:11.58#ibcon#about to read 4, iclass 23, count 0 2006.174.01:19:11.58#ibcon#read 4, iclass 23, count 0 2006.174.01:19:11.58#ibcon#about to read 5, iclass 23, count 0 2006.174.01:19:11.58#ibcon#read 5, iclass 23, count 0 2006.174.01:19:11.58#ibcon#about to read 6, iclass 23, count 0 2006.174.01:19:11.58#ibcon#read 6, iclass 23, count 0 2006.174.01:19:11.58#ibcon#end of sib2, iclass 23, count 0 2006.174.01:19:11.58#ibcon#*mode == 0, iclass 23, count 0 2006.174.01:19:11.58#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.174.01:19:11.58#ibcon#[28=FRQ=03,649.99\r\n] 2006.174.01:19:11.58#ibcon#*before write, iclass 23, count 0 2006.174.01:19:11.58#ibcon#enter sib2, iclass 23, count 0 2006.174.01:19:11.58#ibcon#flushed, iclass 23, count 0 2006.174.01:19:11.58#ibcon#about to write, iclass 23, count 0 2006.174.01:19:11.58#ibcon#wrote, iclass 23, count 0 2006.174.01:19:11.58#ibcon#about to read 3, iclass 23, count 0 2006.174.01:19:11.62#ibcon#read 3, iclass 23, count 0 2006.174.01:19:11.62#ibcon#about to read 4, iclass 23, count 0 2006.174.01:19:11.62#ibcon#read 4, iclass 23, count 0 2006.174.01:19:11.62#ibcon#about to read 5, iclass 23, count 0 2006.174.01:19:11.62#ibcon#read 5, iclass 23, count 0 2006.174.01:19:11.62#ibcon#about to read 6, iclass 23, count 0 2006.174.01:19:11.62#ibcon#read 6, iclass 23, count 0 2006.174.01:19:11.62#ibcon#end of sib2, iclass 23, count 0 2006.174.01:19:11.62#ibcon#*after write, iclass 23, count 0 2006.174.01:19:11.62#ibcon#*before return 0, iclass 23, count 0 2006.174.01:19:11.62#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.174.01:19:11.62#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.174.01:19:11.62#ibcon#about to clear, iclass 23 cls_cnt 0 2006.174.01:19:11.62#ibcon#cleared, iclass 23 cls_cnt 0 2006.174.01:19:11.62$vck44/vb=3,4 2006.174.01:19:11.62#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.174.01:19:11.62#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.174.01:19:11.62#ibcon#ireg 11 cls_cnt 2 2006.174.01:19:11.62#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.174.01:19:11.68#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.174.01:19:11.68#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.174.01:19:11.68#ibcon#enter wrdev, iclass 25, count 2 2006.174.01:19:11.68#ibcon#first serial, iclass 25, count 2 2006.174.01:19:11.68#ibcon#enter sib2, iclass 25, count 2 2006.174.01:19:11.68#ibcon#flushed, iclass 25, count 2 2006.174.01:19:11.68#ibcon#about to write, iclass 25, count 2 2006.174.01:19:11.68#ibcon#wrote, iclass 25, count 2 2006.174.01:19:11.68#ibcon#about to read 3, iclass 25, count 2 2006.174.01:19:11.70#ibcon#read 3, iclass 25, count 2 2006.174.01:19:11.70#ibcon#about to read 4, iclass 25, count 2 2006.174.01:19:11.70#ibcon#read 4, iclass 25, count 2 2006.174.01:19:11.70#ibcon#about to read 5, iclass 25, count 2 2006.174.01:19:11.70#ibcon#read 5, iclass 25, count 2 2006.174.01:19:11.70#ibcon#about to read 6, iclass 25, count 2 2006.174.01:19:11.70#ibcon#read 6, iclass 25, count 2 2006.174.01:19:11.70#ibcon#end of sib2, iclass 25, count 2 2006.174.01:19:11.70#ibcon#*mode == 0, iclass 25, count 2 2006.174.01:19:11.70#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.174.01:19:11.70#ibcon#[27=AT03-04\r\n] 2006.174.01:19:11.70#ibcon#*before write, iclass 25, count 2 2006.174.01:19:11.70#ibcon#enter sib2, iclass 25, count 2 2006.174.01:19:11.70#ibcon#flushed, iclass 25, count 2 2006.174.01:19:11.70#ibcon#about to write, iclass 25, count 2 2006.174.01:19:11.70#ibcon#wrote, iclass 25, count 2 2006.174.01:19:11.70#ibcon#about to read 3, iclass 25, count 2 2006.174.01:19:11.73#ibcon#read 3, iclass 25, count 2 2006.174.01:19:11.73#ibcon#about to read 4, iclass 25, count 2 2006.174.01:19:11.73#ibcon#read 4, iclass 25, count 2 2006.174.01:19:11.73#ibcon#about to read 5, iclass 25, count 2 2006.174.01:19:11.73#ibcon#read 5, iclass 25, count 2 2006.174.01:19:11.73#ibcon#about to read 6, iclass 25, count 2 2006.174.01:19:11.73#ibcon#read 6, iclass 25, count 2 2006.174.01:19:11.73#ibcon#end of sib2, iclass 25, count 2 2006.174.01:19:11.73#ibcon#*after write, iclass 25, count 2 2006.174.01:19:11.73#ibcon#*before return 0, iclass 25, count 2 2006.174.01:19:11.73#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.174.01:19:11.73#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.174.01:19:11.73#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.174.01:19:11.73#ibcon#ireg 7 cls_cnt 0 2006.174.01:19:11.73#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.174.01:19:11.85#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.174.01:19:11.85#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.174.01:19:11.85#ibcon#enter wrdev, iclass 25, count 0 2006.174.01:19:11.85#ibcon#first serial, iclass 25, count 0 2006.174.01:19:11.85#ibcon#enter sib2, iclass 25, count 0 2006.174.01:19:11.85#ibcon#flushed, iclass 25, count 0 2006.174.01:19:11.85#ibcon#about to write, iclass 25, count 0 2006.174.01:19:11.85#ibcon#wrote, iclass 25, count 0 2006.174.01:19:11.85#ibcon#about to read 3, iclass 25, count 0 2006.174.01:19:11.87#ibcon#read 3, iclass 25, count 0 2006.174.01:19:11.87#ibcon#about to read 4, iclass 25, count 0 2006.174.01:19:11.87#ibcon#read 4, iclass 25, count 0 2006.174.01:19:11.87#ibcon#about to read 5, iclass 25, count 0 2006.174.01:19:11.87#ibcon#read 5, iclass 25, count 0 2006.174.01:19:11.87#ibcon#about to read 6, iclass 25, count 0 2006.174.01:19:11.87#ibcon#read 6, iclass 25, count 0 2006.174.01:19:11.87#ibcon#end of sib2, iclass 25, count 0 2006.174.01:19:11.87#ibcon#*mode == 0, iclass 25, count 0 2006.174.01:19:11.87#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.174.01:19:11.87#ibcon#[27=USB\r\n] 2006.174.01:19:11.87#ibcon#*before write, iclass 25, count 0 2006.174.01:19:11.87#ibcon#enter sib2, iclass 25, count 0 2006.174.01:19:11.87#ibcon#flushed, iclass 25, count 0 2006.174.01:19:11.87#ibcon#about to write, iclass 25, count 0 2006.174.01:19:11.87#ibcon#wrote, iclass 25, count 0 2006.174.01:19:11.87#ibcon#about to read 3, iclass 25, count 0 2006.174.01:19:11.90#ibcon#read 3, iclass 25, count 0 2006.174.01:19:11.90#ibcon#about to read 4, iclass 25, count 0 2006.174.01:19:11.90#ibcon#read 4, iclass 25, count 0 2006.174.01:19:11.90#ibcon#about to read 5, iclass 25, count 0 2006.174.01:19:11.90#ibcon#read 5, iclass 25, count 0 2006.174.01:19:11.90#ibcon#about to read 6, iclass 25, count 0 2006.174.01:19:11.90#ibcon#read 6, iclass 25, count 0 2006.174.01:19:11.90#ibcon#end of sib2, iclass 25, count 0 2006.174.01:19:11.90#ibcon#*after write, iclass 25, count 0 2006.174.01:19:11.90#ibcon#*before return 0, iclass 25, count 0 2006.174.01:19:11.90#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.174.01:19:11.90#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.174.01:19:11.90#ibcon#about to clear, iclass 25 cls_cnt 0 2006.174.01:19:11.90#ibcon#cleared, iclass 25 cls_cnt 0 2006.174.01:19:11.90$vck44/vblo=4,679.99 2006.174.01:19:11.90#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.174.01:19:11.90#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.174.01:19:11.90#ibcon#ireg 17 cls_cnt 0 2006.174.01:19:11.90#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.174.01:19:11.90#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.174.01:19:11.90#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.174.01:19:11.90#ibcon#enter wrdev, iclass 27, count 0 2006.174.01:19:11.90#ibcon#first serial, iclass 27, count 0 2006.174.01:19:11.90#ibcon#enter sib2, iclass 27, count 0 2006.174.01:19:11.90#ibcon#flushed, iclass 27, count 0 2006.174.01:19:11.90#ibcon#about to write, iclass 27, count 0 2006.174.01:19:11.90#ibcon#wrote, iclass 27, count 0 2006.174.01:19:11.90#ibcon#about to read 3, iclass 27, count 0 2006.174.01:19:11.92#ibcon#read 3, iclass 27, count 0 2006.174.01:19:11.92#ibcon#about to read 4, iclass 27, count 0 2006.174.01:19:11.92#ibcon#read 4, iclass 27, count 0 2006.174.01:19:11.92#ibcon#about to read 5, iclass 27, count 0 2006.174.01:19:11.92#ibcon#read 5, iclass 27, count 0 2006.174.01:19:11.92#ibcon#about to read 6, iclass 27, count 0 2006.174.01:19:11.92#ibcon#read 6, iclass 27, count 0 2006.174.01:19:11.92#ibcon#end of sib2, iclass 27, count 0 2006.174.01:19:11.92#ibcon#*mode == 0, iclass 27, count 0 2006.174.01:19:11.92#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.174.01:19:11.92#ibcon#[28=FRQ=04,679.99\r\n] 2006.174.01:19:11.92#ibcon#*before write, iclass 27, count 0 2006.174.01:19:11.92#ibcon#enter sib2, iclass 27, count 0 2006.174.01:19:11.92#ibcon#flushed, iclass 27, count 0 2006.174.01:19:11.92#ibcon#about to write, iclass 27, count 0 2006.174.01:19:11.92#ibcon#wrote, iclass 27, count 0 2006.174.01:19:11.92#ibcon#about to read 3, iclass 27, count 0 2006.174.01:19:11.96#ibcon#read 3, iclass 27, count 0 2006.174.01:19:11.96#ibcon#about to read 4, iclass 27, count 0 2006.174.01:19:11.96#ibcon#read 4, iclass 27, count 0 2006.174.01:19:11.96#ibcon#about to read 5, iclass 27, count 0 2006.174.01:19:11.96#ibcon#read 5, iclass 27, count 0 2006.174.01:19:11.96#ibcon#about to read 6, iclass 27, count 0 2006.174.01:19:11.96#ibcon#read 6, iclass 27, count 0 2006.174.01:19:11.96#ibcon#end of sib2, iclass 27, count 0 2006.174.01:19:11.96#ibcon#*after write, iclass 27, count 0 2006.174.01:19:11.96#ibcon#*before return 0, iclass 27, count 0 2006.174.01:19:11.96#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.174.01:19:11.96#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.174.01:19:11.96#ibcon#about to clear, iclass 27 cls_cnt 0 2006.174.01:19:11.96#ibcon#cleared, iclass 27 cls_cnt 0 2006.174.01:19:11.96$vck44/vb=4,4 2006.174.01:19:11.96#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.174.01:19:11.96#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.174.01:19:11.96#ibcon#ireg 11 cls_cnt 2 2006.174.01:19:11.96#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.174.01:19:12.02#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.174.01:19:12.02#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.174.01:19:12.02#ibcon#enter wrdev, iclass 29, count 2 2006.174.01:19:12.02#ibcon#first serial, iclass 29, count 2 2006.174.01:19:12.02#ibcon#enter sib2, iclass 29, count 2 2006.174.01:19:12.02#ibcon#flushed, iclass 29, count 2 2006.174.01:19:12.02#ibcon#about to write, iclass 29, count 2 2006.174.01:19:12.02#ibcon#wrote, iclass 29, count 2 2006.174.01:19:12.02#ibcon#about to read 3, iclass 29, count 2 2006.174.01:19:12.04#ibcon#read 3, iclass 29, count 2 2006.174.01:19:12.04#ibcon#about to read 4, iclass 29, count 2 2006.174.01:19:12.04#ibcon#read 4, iclass 29, count 2 2006.174.01:19:12.04#ibcon#about to read 5, iclass 29, count 2 2006.174.01:19:12.04#ibcon#read 5, iclass 29, count 2 2006.174.01:19:12.04#ibcon#about to read 6, iclass 29, count 2 2006.174.01:19:12.04#ibcon#read 6, iclass 29, count 2 2006.174.01:19:12.04#ibcon#end of sib2, iclass 29, count 2 2006.174.01:19:12.04#ibcon#*mode == 0, iclass 29, count 2 2006.174.01:19:12.04#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.174.01:19:12.04#ibcon#[27=AT04-04\r\n] 2006.174.01:19:12.04#ibcon#*before write, iclass 29, count 2 2006.174.01:19:12.04#ibcon#enter sib2, iclass 29, count 2 2006.174.01:19:12.04#ibcon#flushed, iclass 29, count 2 2006.174.01:19:12.04#ibcon#about to write, iclass 29, count 2 2006.174.01:19:12.04#ibcon#wrote, iclass 29, count 2 2006.174.01:19:12.04#ibcon#about to read 3, iclass 29, count 2 2006.174.01:19:12.07#ibcon#read 3, iclass 29, count 2 2006.174.01:19:12.07#ibcon#about to read 4, iclass 29, count 2 2006.174.01:19:12.07#ibcon#read 4, iclass 29, count 2 2006.174.01:19:12.07#ibcon#about to read 5, iclass 29, count 2 2006.174.01:19:12.07#ibcon#read 5, iclass 29, count 2 2006.174.01:19:12.07#ibcon#about to read 6, iclass 29, count 2 2006.174.01:19:12.07#ibcon#read 6, iclass 29, count 2 2006.174.01:19:12.07#ibcon#end of sib2, iclass 29, count 2 2006.174.01:19:12.07#ibcon#*after write, iclass 29, count 2 2006.174.01:19:12.07#ibcon#*before return 0, iclass 29, count 2 2006.174.01:19:12.07#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.174.01:19:12.07#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.174.01:19:12.07#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.174.01:19:12.07#ibcon#ireg 7 cls_cnt 0 2006.174.01:19:12.07#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.174.01:19:12.19#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.174.01:19:12.19#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.174.01:19:12.19#ibcon#enter wrdev, iclass 29, count 0 2006.174.01:19:12.19#ibcon#first serial, iclass 29, count 0 2006.174.01:19:12.19#ibcon#enter sib2, iclass 29, count 0 2006.174.01:19:12.19#ibcon#flushed, iclass 29, count 0 2006.174.01:19:12.19#ibcon#about to write, iclass 29, count 0 2006.174.01:19:12.19#ibcon#wrote, iclass 29, count 0 2006.174.01:19:12.19#ibcon#about to read 3, iclass 29, count 0 2006.174.01:19:12.21#ibcon#read 3, iclass 29, count 0 2006.174.01:19:12.21#ibcon#about to read 4, iclass 29, count 0 2006.174.01:19:12.21#ibcon#read 4, iclass 29, count 0 2006.174.01:19:12.21#ibcon#about to read 5, iclass 29, count 0 2006.174.01:19:12.21#ibcon#read 5, iclass 29, count 0 2006.174.01:19:12.21#ibcon#about to read 6, iclass 29, count 0 2006.174.01:19:12.21#ibcon#read 6, iclass 29, count 0 2006.174.01:19:12.21#ibcon#end of sib2, iclass 29, count 0 2006.174.01:19:12.21#ibcon#*mode == 0, iclass 29, count 0 2006.174.01:19:12.21#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.174.01:19:12.21#ibcon#[27=USB\r\n] 2006.174.01:19:12.21#ibcon#*before write, iclass 29, count 0 2006.174.01:19:12.21#ibcon#enter sib2, iclass 29, count 0 2006.174.01:19:12.21#ibcon#flushed, iclass 29, count 0 2006.174.01:19:12.21#ibcon#about to write, iclass 29, count 0 2006.174.01:19:12.21#ibcon#wrote, iclass 29, count 0 2006.174.01:19:12.21#ibcon#about to read 3, iclass 29, count 0 2006.174.01:19:12.24#ibcon#read 3, iclass 29, count 0 2006.174.01:19:12.24#ibcon#about to read 4, iclass 29, count 0 2006.174.01:19:12.24#ibcon#read 4, iclass 29, count 0 2006.174.01:19:12.24#ibcon#about to read 5, iclass 29, count 0 2006.174.01:19:12.24#ibcon#read 5, iclass 29, count 0 2006.174.01:19:12.24#ibcon#about to read 6, iclass 29, count 0 2006.174.01:19:12.24#ibcon#read 6, iclass 29, count 0 2006.174.01:19:12.24#ibcon#end of sib2, iclass 29, count 0 2006.174.01:19:12.24#ibcon#*after write, iclass 29, count 0 2006.174.01:19:12.24#ibcon#*before return 0, iclass 29, count 0 2006.174.01:19:12.24#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.174.01:19:12.24#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.174.01:19:12.24#ibcon#about to clear, iclass 29 cls_cnt 0 2006.174.01:19:12.24#ibcon#cleared, iclass 29 cls_cnt 0 2006.174.01:19:12.24$vck44/vblo=5,709.99 2006.174.01:19:12.24#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.174.01:19:12.24#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.174.01:19:12.24#ibcon#ireg 17 cls_cnt 0 2006.174.01:19:12.24#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.174.01:19:12.24#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.174.01:19:12.24#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.174.01:19:12.24#ibcon#enter wrdev, iclass 31, count 0 2006.174.01:19:12.24#ibcon#first serial, iclass 31, count 0 2006.174.01:19:12.24#ibcon#enter sib2, iclass 31, count 0 2006.174.01:19:12.24#ibcon#flushed, iclass 31, count 0 2006.174.01:19:12.24#ibcon#about to write, iclass 31, count 0 2006.174.01:19:12.24#ibcon#wrote, iclass 31, count 0 2006.174.01:19:12.24#ibcon#about to read 3, iclass 31, count 0 2006.174.01:19:12.26#ibcon#read 3, iclass 31, count 0 2006.174.01:19:12.26#ibcon#about to read 4, iclass 31, count 0 2006.174.01:19:12.26#ibcon#read 4, iclass 31, count 0 2006.174.01:19:12.26#ibcon#about to read 5, iclass 31, count 0 2006.174.01:19:12.26#ibcon#read 5, iclass 31, count 0 2006.174.01:19:12.26#ibcon#about to read 6, iclass 31, count 0 2006.174.01:19:12.26#ibcon#read 6, iclass 31, count 0 2006.174.01:19:12.26#ibcon#end of sib2, iclass 31, count 0 2006.174.01:19:12.26#ibcon#*mode == 0, iclass 31, count 0 2006.174.01:19:12.26#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.174.01:19:12.26#ibcon#[28=FRQ=05,709.99\r\n] 2006.174.01:19:12.26#ibcon#*before write, iclass 31, count 0 2006.174.01:19:12.26#ibcon#enter sib2, iclass 31, count 0 2006.174.01:19:12.26#ibcon#flushed, iclass 31, count 0 2006.174.01:19:12.26#ibcon#about to write, iclass 31, count 0 2006.174.01:19:12.26#ibcon#wrote, iclass 31, count 0 2006.174.01:19:12.26#ibcon#about to read 3, iclass 31, count 0 2006.174.01:19:12.30#ibcon#read 3, iclass 31, count 0 2006.174.01:19:12.30#ibcon#about to read 4, iclass 31, count 0 2006.174.01:19:12.30#ibcon#read 4, iclass 31, count 0 2006.174.01:19:12.30#ibcon#about to read 5, iclass 31, count 0 2006.174.01:19:12.30#ibcon#read 5, iclass 31, count 0 2006.174.01:19:12.30#ibcon#about to read 6, iclass 31, count 0 2006.174.01:19:12.30#ibcon#read 6, iclass 31, count 0 2006.174.01:19:12.30#ibcon#end of sib2, iclass 31, count 0 2006.174.01:19:12.30#ibcon#*after write, iclass 31, count 0 2006.174.01:19:12.30#ibcon#*before return 0, iclass 31, count 0 2006.174.01:19:12.30#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.174.01:19:12.30#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.174.01:19:12.30#ibcon#about to clear, iclass 31 cls_cnt 0 2006.174.01:19:12.30#ibcon#cleared, iclass 31 cls_cnt 0 2006.174.01:19:12.30$vck44/vb=5,4 2006.174.01:19:12.30#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.174.01:19:12.30#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.174.01:19:12.30#ibcon#ireg 11 cls_cnt 2 2006.174.01:19:12.30#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.174.01:19:12.36#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.174.01:19:12.36#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.174.01:19:12.36#ibcon#enter wrdev, iclass 33, count 2 2006.174.01:19:12.36#ibcon#first serial, iclass 33, count 2 2006.174.01:19:12.36#ibcon#enter sib2, iclass 33, count 2 2006.174.01:19:12.36#ibcon#flushed, iclass 33, count 2 2006.174.01:19:12.36#ibcon#about to write, iclass 33, count 2 2006.174.01:19:12.36#ibcon#wrote, iclass 33, count 2 2006.174.01:19:12.36#ibcon#about to read 3, iclass 33, count 2 2006.174.01:19:12.38#ibcon#read 3, iclass 33, count 2 2006.174.01:19:12.38#ibcon#about to read 4, iclass 33, count 2 2006.174.01:19:12.38#ibcon#read 4, iclass 33, count 2 2006.174.01:19:12.38#ibcon#about to read 5, iclass 33, count 2 2006.174.01:19:12.38#ibcon#read 5, iclass 33, count 2 2006.174.01:19:12.38#ibcon#about to read 6, iclass 33, count 2 2006.174.01:19:12.38#ibcon#read 6, iclass 33, count 2 2006.174.01:19:12.38#ibcon#end of sib2, iclass 33, count 2 2006.174.01:19:12.38#ibcon#*mode == 0, iclass 33, count 2 2006.174.01:19:12.38#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.174.01:19:12.38#ibcon#[27=AT05-04\r\n] 2006.174.01:19:12.38#ibcon#*before write, iclass 33, count 2 2006.174.01:19:12.38#ibcon#enter sib2, iclass 33, count 2 2006.174.01:19:12.38#ibcon#flushed, iclass 33, count 2 2006.174.01:19:12.38#ibcon#about to write, iclass 33, count 2 2006.174.01:19:12.38#ibcon#wrote, iclass 33, count 2 2006.174.01:19:12.38#ibcon#about to read 3, iclass 33, count 2 2006.174.01:19:12.41#ibcon#read 3, iclass 33, count 2 2006.174.01:19:12.41#ibcon#about to read 4, iclass 33, count 2 2006.174.01:19:12.41#ibcon#read 4, iclass 33, count 2 2006.174.01:19:12.41#ibcon#about to read 5, iclass 33, count 2 2006.174.01:19:12.41#ibcon#read 5, iclass 33, count 2 2006.174.01:19:12.41#ibcon#about to read 6, iclass 33, count 2 2006.174.01:19:12.41#ibcon#read 6, iclass 33, count 2 2006.174.01:19:12.41#ibcon#end of sib2, iclass 33, count 2 2006.174.01:19:12.41#ibcon#*after write, iclass 33, count 2 2006.174.01:19:12.41#ibcon#*before return 0, iclass 33, count 2 2006.174.01:19:12.41#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.174.01:19:12.41#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.174.01:19:12.41#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.174.01:19:12.41#ibcon#ireg 7 cls_cnt 0 2006.174.01:19:12.41#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.174.01:19:12.53#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.174.01:19:12.53#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.174.01:19:12.53#ibcon#enter wrdev, iclass 33, count 0 2006.174.01:19:12.53#ibcon#first serial, iclass 33, count 0 2006.174.01:19:12.53#ibcon#enter sib2, iclass 33, count 0 2006.174.01:19:12.53#ibcon#flushed, iclass 33, count 0 2006.174.01:19:12.53#ibcon#about to write, iclass 33, count 0 2006.174.01:19:12.53#ibcon#wrote, iclass 33, count 0 2006.174.01:19:12.53#ibcon#about to read 3, iclass 33, count 0 2006.174.01:19:12.55#ibcon#read 3, iclass 33, count 0 2006.174.01:19:12.55#ibcon#about to read 4, iclass 33, count 0 2006.174.01:19:12.55#ibcon#read 4, iclass 33, count 0 2006.174.01:19:12.55#ibcon#about to read 5, iclass 33, count 0 2006.174.01:19:12.55#ibcon#read 5, iclass 33, count 0 2006.174.01:19:12.55#ibcon#about to read 6, iclass 33, count 0 2006.174.01:19:12.55#ibcon#read 6, iclass 33, count 0 2006.174.01:19:12.55#ibcon#end of sib2, iclass 33, count 0 2006.174.01:19:12.55#ibcon#*mode == 0, iclass 33, count 0 2006.174.01:19:12.55#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.174.01:19:12.55#ibcon#[27=USB\r\n] 2006.174.01:19:12.55#ibcon#*before write, iclass 33, count 0 2006.174.01:19:12.55#ibcon#enter sib2, iclass 33, count 0 2006.174.01:19:12.55#ibcon#flushed, iclass 33, count 0 2006.174.01:19:12.55#ibcon#about to write, iclass 33, count 0 2006.174.01:19:12.55#ibcon#wrote, iclass 33, count 0 2006.174.01:19:12.55#ibcon#about to read 3, iclass 33, count 0 2006.174.01:19:12.58#ibcon#read 3, iclass 33, count 0 2006.174.01:19:12.58#ibcon#about to read 4, iclass 33, count 0 2006.174.01:19:12.58#ibcon#read 4, iclass 33, count 0 2006.174.01:19:12.58#ibcon#about to read 5, iclass 33, count 0 2006.174.01:19:12.58#ibcon#read 5, iclass 33, count 0 2006.174.01:19:12.58#ibcon#about to read 6, iclass 33, count 0 2006.174.01:19:12.58#ibcon#read 6, iclass 33, count 0 2006.174.01:19:12.58#ibcon#end of sib2, iclass 33, count 0 2006.174.01:19:12.58#ibcon#*after write, iclass 33, count 0 2006.174.01:19:12.58#ibcon#*before return 0, iclass 33, count 0 2006.174.01:19:12.58#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.174.01:19:12.58#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.174.01:19:12.58#ibcon#about to clear, iclass 33 cls_cnt 0 2006.174.01:19:12.58#ibcon#cleared, iclass 33 cls_cnt 0 2006.174.01:19:12.58$vck44/vblo=6,719.99 2006.174.01:19:12.58#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.174.01:19:12.58#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.174.01:19:12.58#ibcon#ireg 17 cls_cnt 0 2006.174.01:19:12.58#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.174.01:19:12.58#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.174.01:19:12.58#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.174.01:19:12.58#ibcon#enter wrdev, iclass 35, count 0 2006.174.01:19:12.58#ibcon#first serial, iclass 35, count 0 2006.174.01:19:12.58#ibcon#enter sib2, iclass 35, count 0 2006.174.01:19:12.58#ibcon#flushed, iclass 35, count 0 2006.174.01:19:12.58#ibcon#about to write, iclass 35, count 0 2006.174.01:19:12.58#ibcon#wrote, iclass 35, count 0 2006.174.01:19:12.58#ibcon#about to read 3, iclass 35, count 0 2006.174.01:19:12.60#ibcon#read 3, iclass 35, count 0 2006.174.01:19:12.60#ibcon#about to read 4, iclass 35, count 0 2006.174.01:19:12.60#ibcon#read 4, iclass 35, count 0 2006.174.01:19:12.60#ibcon#about to read 5, iclass 35, count 0 2006.174.01:19:12.60#ibcon#read 5, iclass 35, count 0 2006.174.01:19:12.60#ibcon#about to read 6, iclass 35, count 0 2006.174.01:19:12.60#ibcon#read 6, iclass 35, count 0 2006.174.01:19:12.60#ibcon#end of sib2, iclass 35, count 0 2006.174.01:19:12.60#ibcon#*mode == 0, iclass 35, count 0 2006.174.01:19:12.60#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.174.01:19:12.60#ibcon#[28=FRQ=06,719.99\r\n] 2006.174.01:19:12.60#ibcon#*before write, iclass 35, count 0 2006.174.01:19:12.60#ibcon#enter sib2, iclass 35, count 0 2006.174.01:19:12.60#ibcon#flushed, iclass 35, count 0 2006.174.01:19:12.60#ibcon#about to write, iclass 35, count 0 2006.174.01:19:12.60#ibcon#wrote, iclass 35, count 0 2006.174.01:19:12.60#ibcon#about to read 3, iclass 35, count 0 2006.174.01:19:12.64#ibcon#read 3, iclass 35, count 0 2006.174.01:19:12.64#ibcon#about to read 4, iclass 35, count 0 2006.174.01:19:12.64#ibcon#read 4, iclass 35, count 0 2006.174.01:19:12.64#ibcon#about to read 5, iclass 35, count 0 2006.174.01:19:12.64#ibcon#read 5, iclass 35, count 0 2006.174.01:19:12.64#ibcon#about to read 6, iclass 35, count 0 2006.174.01:19:12.64#ibcon#read 6, iclass 35, count 0 2006.174.01:19:12.64#ibcon#end of sib2, iclass 35, count 0 2006.174.01:19:12.64#ibcon#*after write, iclass 35, count 0 2006.174.01:19:12.64#ibcon#*before return 0, iclass 35, count 0 2006.174.01:19:12.64#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.174.01:19:12.64#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.174.01:19:12.64#ibcon#about to clear, iclass 35 cls_cnt 0 2006.174.01:19:12.64#ibcon#cleared, iclass 35 cls_cnt 0 2006.174.01:19:12.64$vck44/vb=6,4 2006.174.01:19:12.64#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.174.01:19:12.64#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.174.01:19:12.64#ibcon#ireg 11 cls_cnt 2 2006.174.01:19:12.64#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.174.01:19:12.70#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.174.01:19:12.70#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.174.01:19:12.70#ibcon#enter wrdev, iclass 37, count 2 2006.174.01:19:12.70#ibcon#first serial, iclass 37, count 2 2006.174.01:19:12.70#ibcon#enter sib2, iclass 37, count 2 2006.174.01:19:12.70#ibcon#flushed, iclass 37, count 2 2006.174.01:19:12.70#ibcon#about to write, iclass 37, count 2 2006.174.01:19:12.70#ibcon#wrote, iclass 37, count 2 2006.174.01:19:12.70#ibcon#about to read 3, iclass 37, count 2 2006.174.01:19:12.72#ibcon#read 3, iclass 37, count 2 2006.174.01:19:12.72#ibcon#about to read 4, iclass 37, count 2 2006.174.01:19:12.72#ibcon#read 4, iclass 37, count 2 2006.174.01:19:12.72#ibcon#about to read 5, iclass 37, count 2 2006.174.01:19:12.72#ibcon#read 5, iclass 37, count 2 2006.174.01:19:12.72#ibcon#about to read 6, iclass 37, count 2 2006.174.01:19:12.72#ibcon#read 6, iclass 37, count 2 2006.174.01:19:12.72#ibcon#end of sib2, iclass 37, count 2 2006.174.01:19:12.72#ibcon#*mode == 0, iclass 37, count 2 2006.174.01:19:12.72#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.174.01:19:12.72#ibcon#[27=AT06-04\r\n] 2006.174.01:19:12.72#ibcon#*before write, iclass 37, count 2 2006.174.01:19:12.72#ibcon#enter sib2, iclass 37, count 2 2006.174.01:19:12.72#ibcon#flushed, iclass 37, count 2 2006.174.01:19:12.72#ibcon#about to write, iclass 37, count 2 2006.174.01:19:12.72#ibcon#wrote, iclass 37, count 2 2006.174.01:19:12.72#ibcon#about to read 3, iclass 37, count 2 2006.174.01:19:12.75#ibcon#read 3, iclass 37, count 2 2006.174.01:19:12.75#ibcon#about to read 4, iclass 37, count 2 2006.174.01:19:12.75#ibcon#read 4, iclass 37, count 2 2006.174.01:19:12.75#ibcon#about to read 5, iclass 37, count 2 2006.174.01:19:12.75#ibcon#read 5, iclass 37, count 2 2006.174.01:19:12.75#ibcon#about to read 6, iclass 37, count 2 2006.174.01:19:12.75#ibcon#read 6, iclass 37, count 2 2006.174.01:19:12.75#ibcon#end of sib2, iclass 37, count 2 2006.174.01:19:12.75#ibcon#*after write, iclass 37, count 2 2006.174.01:19:12.75#ibcon#*before return 0, iclass 37, count 2 2006.174.01:19:12.75#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.174.01:19:12.75#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.174.01:19:12.75#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.174.01:19:12.75#ibcon#ireg 7 cls_cnt 0 2006.174.01:19:12.75#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.174.01:19:12.87#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.174.01:19:12.87#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.174.01:19:12.87#ibcon#enter wrdev, iclass 37, count 0 2006.174.01:19:12.87#ibcon#first serial, iclass 37, count 0 2006.174.01:19:12.87#ibcon#enter sib2, iclass 37, count 0 2006.174.01:19:12.87#ibcon#flushed, iclass 37, count 0 2006.174.01:19:12.87#ibcon#about to write, iclass 37, count 0 2006.174.01:19:12.87#ibcon#wrote, iclass 37, count 0 2006.174.01:19:12.87#ibcon#about to read 3, iclass 37, count 0 2006.174.01:19:12.89#ibcon#read 3, iclass 37, count 0 2006.174.01:19:12.89#ibcon#about to read 4, iclass 37, count 0 2006.174.01:19:12.89#ibcon#read 4, iclass 37, count 0 2006.174.01:19:12.89#ibcon#about to read 5, iclass 37, count 0 2006.174.01:19:12.89#ibcon#read 5, iclass 37, count 0 2006.174.01:19:12.89#ibcon#about to read 6, iclass 37, count 0 2006.174.01:19:12.89#ibcon#read 6, iclass 37, count 0 2006.174.01:19:12.89#ibcon#end of sib2, iclass 37, count 0 2006.174.01:19:12.89#ibcon#*mode == 0, iclass 37, count 0 2006.174.01:19:12.89#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.174.01:19:12.89#ibcon#[27=USB\r\n] 2006.174.01:19:12.89#ibcon#*before write, iclass 37, count 0 2006.174.01:19:12.89#ibcon#enter sib2, iclass 37, count 0 2006.174.01:19:12.89#ibcon#flushed, iclass 37, count 0 2006.174.01:19:12.89#ibcon#about to write, iclass 37, count 0 2006.174.01:19:12.89#ibcon#wrote, iclass 37, count 0 2006.174.01:19:12.89#ibcon#about to read 3, iclass 37, count 0 2006.174.01:19:12.92#ibcon#read 3, iclass 37, count 0 2006.174.01:19:12.92#ibcon#about to read 4, iclass 37, count 0 2006.174.01:19:12.92#ibcon#read 4, iclass 37, count 0 2006.174.01:19:12.92#ibcon#about to read 5, iclass 37, count 0 2006.174.01:19:12.92#ibcon#read 5, iclass 37, count 0 2006.174.01:19:12.92#ibcon#about to read 6, iclass 37, count 0 2006.174.01:19:12.92#ibcon#read 6, iclass 37, count 0 2006.174.01:19:12.92#ibcon#end of sib2, iclass 37, count 0 2006.174.01:19:12.92#ibcon#*after write, iclass 37, count 0 2006.174.01:19:12.92#ibcon#*before return 0, iclass 37, count 0 2006.174.01:19:12.92#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.174.01:19:12.92#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.174.01:19:12.92#ibcon#about to clear, iclass 37 cls_cnt 0 2006.174.01:19:12.92#ibcon#cleared, iclass 37 cls_cnt 0 2006.174.01:19:12.92$vck44/vblo=7,734.99 2006.174.01:19:12.92#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.174.01:19:12.92#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.174.01:19:12.92#ibcon#ireg 17 cls_cnt 0 2006.174.01:19:12.92#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.174.01:19:12.92#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.174.01:19:12.92#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.174.01:19:12.92#ibcon#enter wrdev, iclass 39, count 0 2006.174.01:19:12.92#ibcon#first serial, iclass 39, count 0 2006.174.01:19:12.92#ibcon#enter sib2, iclass 39, count 0 2006.174.01:19:12.92#ibcon#flushed, iclass 39, count 0 2006.174.01:19:12.92#ibcon#about to write, iclass 39, count 0 2006.174.01:19:12.92#ibcon#wrote, iclass 39, count 0 2006.174.01:19:12.92#ibcon#about to read 3, iclass 39, count 0 2006.174.01:19:12.94#ibcon#read 3, iclass 39, count 0 2006.174.01:19:12.94#ibcon#about to read 4, iclass 39, count 0 2006.174.01:19:12.94#ibcon#read 4, iclass 39, count 0 2006.174.01:19:12.94#ibcon#about to read 5, iclass 39, count 0 2006.174.01:19:12.94#ibcon#read 5, iclass 39, count 0 2006.174.01:19:12.94#ibcon#about to read 6, iclass 39, count 0 2006.174.01:19:12.94#ibcon#read 6, iclass 39, count 0 2006.174.01:19:12.94#ibcon#end of sib2, iclass 39, count 0 2006.174.01:19:12.94#ibcon#*mode == 0, iclass 39, count 0 2006.174.01:19:12.94#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.174.01:19:12.94#ibcon#[28=FRQ=07,734.99\r\n] 2006.174.01:19:12.94#ibcon#*before write, iclass 39, count 0 2006.174.01:19:12.94#ibcon#enter sib2, iclass 39, count 0 2006.174.01:19:12.94#ibcon#flushed, iclass 39, count 0 2006.174.01:19:12.94#ibcon#about to write, iclass 39, count 0 2006.174.01:19:12.94#ibcon#wrote, iclass 39, count 0 2006.174.01:19:12.94#ibcon#about to read 3, iclass 39, count 0 2006.174.01:19:12.98#ibcon#read 3, iclass 39, count 0 2006.174.01:19:12.98#ibcon#about to read 4, iclass 39, count 0 2006.174.01:19:12.98#ibcon#read 4, iclass 39, count 0 2006.174.01:19:12.98#ibcon#about to read 5, iclass 39, count 0 2006.174.01:19:12.98#ibcon#read 5, iclass 39, count 0 2006.174.01:19:12.98#ibcon#about to read 6, iclass 39, count 0 2006.174.01:19:12.98#ibcon#read 6, iclass 39, count 0 2006.174.01:19:12.98#ibcon#end of sib2, iclass 39, count 0 2006.174.01:19:12.98#ibcon#*after write, iclass 39, count 0 2006.174.01:19:12.98#ibcon#*before return 0, iclass 39, count 0 2006.174.01:19:12.98#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.174.01:19:12.98#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.174.01:19:12.98#ibcon#about to clear, iclass 39 cls_cnt 0 2006.174.01:19:12.98#ibcon#cleared, iclass 39 cls_cnt 0 2006.174.01:19:12.98$vck44/vb=7,4 2006.174.01:19:12.98#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.174.01:19:12.98#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.174.01:19:12.98#ibcon#ireg 11 cls_cnt 2 2006.174.01:19:12.98#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.174.01:19:13.04#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.174.01:19:13.04#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.174.01:19:13.04#ibcon#enter wrdev, iclass 3, count 2 2006.174.01:19:13.04#ibcon#first serial, iclass 3, count 2 2006.174.01:19:13.04#ibcon#enter sib2, iclass 3, count 2 2006.174.01:19:13.04#ibcon#flushed, iclass 3, count 2 2006.174.01:19:13.04#ibcon#about to write, iclass 3, count 2 2006.174.01:19:13.04#ibcon#wrote, iclass 3, count 2 2006.174.01:19:13.04#ibcon#about to read 3, iclass 3, count 2 2006.174.01:19:13.06#ibcon#read 3, iclass 3, count 2 2006.174.01:19:13.06#ibcon#about to read 4, iclass 3, count 2 2006.174.01:19:13.06#ibcon#read 4, iclass 3, count 2 2006.174.01:19:13.06#ibcon#about to read 5, iclass 3, count 2 2006.174.01:19:13.06#ibcon#read 5, iclass 3, count 2 2006.174.01:19:13.06#ibcon#about to read 6, iclass 3, count 2 2006.174.01:19:13.06#ibcon#read 6, iclass 3, count 2 2006.174.01:19:13.06#ibcon#end of sib2, iclass 3, count 2 2006.174.01:19:13.06#ibcon#*mode == 0, iclass 3, count 2 2006.174.01:19:13.06#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.174.01:19:13.06#ibcon#[27=AT07-04\r\n] 2006.174.01:19:13.06#ibcon#*before write, iclass 3, count 2 2006.174.01:19:13.06#ibcon#enter sib2, iclass 3, count 2 2006.174.01:19:13.06#ibcon#flushed, iclass 3, count 2 2006.174.01:19:13.06#ibcon#about to write, iclass 3, count 2 2006.174.01:19:13.06#ibcon#wrote, iclass 3, count 2 2006.174.01:19:13.06#ibcon#about to read 3, iclass 3, count 2 2006.174.01:19:13.09#ibcon#read 3, iclass 3, count 2 2006.174.01:19:13.09#ibcon#about to read 4, iclass 3, count 2 2006.174.01:19:13.09#ibcon#read 4, iclass 3, count 2 2006.174.01:19:13.09#ibcon#about to read 5, iclass 3, count 2 2006.174.01:19:13.09#ibcon#read 5, iclass 3, count 2 2006.174.01:19:13.09#ibcon#about to read 6, iclass 3, count 2 2006.174.01:19:13.09#ibcon#read 6, iclass 3, count 2 2006.174.01:19:13.09#ibcon#end of sib2, iclass 3, count 2 2006.174.01:19:13.09#ibcon#*after write, iclass 3, count 2 2006.174.01:19:13.09#ibcon#*before return 0, iclass 3, count 2 2006.174.01:19:13.09#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.174.01:19:13.09#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.174.01:19:13.09#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.174.01:19:13.09#ibcon#ireg 7 cls_cnt 0 2006.174.01:19:13.09#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.174.01:19:13.21#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.174.01:19:13.21#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.174.01:19:13.21#ibcon#enter wrdev, iclass 3, count 0 2006.174.01:19:13.21#ibcon#first serial, iclass 3, count 0 2006.174.01:19:13.21#ibcon#enter sib2, iclass 3, count 0 2006.174.01:19:13.21#ibcon#flushed, iclass 3, count 0 2006.174.01:19:13.21#ibcon#about to write, iclass 3, count 0 2006.174.01:19:13.21#ibcon#wrote, iclass 3, count 0 2006.174.01:19:13.21#ibcon#about to read 3, iclass 3, count 0 2006.174.01:19:13.23#ibcon#read 3, iclass 3, count 0 2006.174.01:19:13.23#ibcon#about to read 4, iclass 3, count 0 2006.174.01:19:13.23#ibcon#read 4, iclass 3, count 0 2006.174.01:19:13.23#ibcon#about to read 5, iclass 3, count 0 2006.174.01:19:13.23#ibcon#read 5, iclass 3, count 0 2006.174.01:19:13.23#ibcon#about to read 6, iclass 3, count 0 2006.174.01:19:13.23#ibcon#read 6, iclass 3, count 0 2006.174.01:19:13.23#ibcon#end of sib2, iclass 3, count 0 2006.174.01:19:13.23#ibcon#*mode == 0, iclass 3, count 0 2006.174.01:19:13.23#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.174.01:19:13.23#ibcon#[27=USB\r\n] 2006.174.01:19:13.23#ibcon#*before write, iclass 3, count 0 2006.174.01:19:13.23#ibcon#enter sib2, iclass 3, count 0 2006.174.01:19:13.23#ibcon#flushed, iclass 3, count 0 2006.174.01:19:13.23#ibcon#about to write, iclass 3, count 0 2006.174.01:19:13.23#ibcon#wrote, iclass 3, count 0 2006.174.01:19:13.23#ibcon#about to read 3, iclass 3, count 0 2006.174.01:19:13.26#ibcon#read 3, iclass 3, count 0 2006.174.01:19:13.26#ibcon#about to read 4, iclass 3, count 0 2006.174.01:19:13.26#ibcon#read 4, iclass 3, count 0 2006.174.01:19:13.26#ibcon#about to read 5, iclass 3, count 0 2006.174.01:19:13.26#ibcon#read 5, iclass 3, count 0 2006.174.01:19:13.26#ibcon#about to read 6, iclass 3, count 0 2006.174.01:19:13.26#ibcon#read 6, iclass 3, count 0 2006.174.01:19:13.26#ibcon#end of sib2, iclass 3, count 0 2006.174.01:19:13.26#ibcon#*after write, iclass 3, count 0 2006.174.01:19:13.26#ibcon#*before return 0, iclass 3, count 0 2006.174.01:19:13.26#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.174.01:19:13.26#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.174.01:19:13.26#ibcon#about to clear, iclass 3 cls_cnt 0 2006.174.01:19:13.26#ibcon#cleared, iclass 3 cls_cnt 0 2006.174.01:19:13.26$vck44/vblo=8,744.99 2006.174.01:19:13.26#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.174.01:19:13.26#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.174.01:19:13.26#ibcon#ireg 17 cls_cnt 0 2006.174.01:19:13.26#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.174.01:19:13.26#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.174.01:19:13.26#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.174.01:19:13.26#ibcon#enter wrdev, iclass 5, count 0 2006.174.01:19:13.26#ibcon#first serial, iclass 5, count 0 2006.174.01:19:13.26#ibcon#enter sib2, iclass 5, count 0 2006.174.01:19:13.26#ibcon#flushed, iclass 5, count 0 2006.174.01:19:13.26#ibcon#about to write, iclass 5, count 0 2006.174.01:19:13.26#ibcon#wrote, iclass 5, count 0 2006.174.01:19:13.26#ibcon#about to read 3, iclass 5, count 0 2006.174.01:19:13.28#ibcon#read 3, iclass 5, count 0 2006.174.01:19:13.28#ibcon#about to read 4, iclass 5, count 0 2006.174.01:19:13.28#ibcon#read 4, iclass 5, count 0 2006.174.01:19:13.28#ibcon#about to read 5, iclass 5, count 0 2006.174.01:19:13.28#ibcon#read 5, iclass 5, count 0 2006.174.01:19:13.28#ibcon#about to read 6, iclass 5, count 0 2006.174.01:19:13.28#ibcon#read 6, iclass 5, count 0 2006.174.01:19:13.28#ibcon#end of sib2, iclass 5, count 0 2006.174.01:19:13.28#ibcon#*mode == 0, iclass 5, count 0 2006.174.01:19:13.28#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.174.01:19:13.28#ibcon#[28=FRQ=08,744.99\r\n] 2006.174.01:19:13.28#ibcon#*before write, iclass 5, count 0 2006.174.01:19:13.28#ibcon#enter sib2, iclass 5, count 0 2006.174.01:19:13.28#ibcon#flushed, iclass 5, count 0 2006.174.01:19:13.28#ibcon#about to write, iclass 5, count 0 2006.174.01:19:13.28#ibcon#wrote, iclass 5, count 0 2006.174.01:19:13.28#ibcon#about to read 3, iclass 5, count 0 2006.174.01:19:13.32#ibcon#read 3, iclass 5, count 0 2006.174.01:19:13.32#ibcon#about to read 4, iclass 5, count 0 2006.174.01:19:13.32#ibcon#read 4, iclass 5, count 0 2006.174.01:19:13.32#ibcon#about to read 5, iclass 5, count 0 2006.174.01:19:13.32#ibcon#read 5, iclass 5, count 0 2006.174.01:19:13.32#ibcon#about to read 6, iclass 5, count 0 2006.174.01:19:13.32#ibcon#read 6, iclass 5, count 0 2006.174.01:19:13.32#ibcon#end of sib2, iclass 5, count 0 2006.174.01:19:13.32#ibcon#*after write, iclass 5, count 0 2006.174.01:19:13.32#ibcon#*before return 0, iclass 5, count 0 2006.174.01:19:13.32#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.174.01:19:13.32#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.174.01:19:13.32#ibcon#about to clear, iclass 5 cls_cnt 0 2006.174.01:19:13.32#ibcon#cleared, iclass 5 cls_cnt 0 2006.174.01:19:13.32$vck44/vb=8,4 2006.174.01:19:13.32#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.174.01:19:13.32#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.174.01:19:13.32#ibcon#ireg 11 cls_cnt 2 2006.174.01:19:13.32#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.174.01:19:13.38#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.174.01:19:13.38#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.174.01:19:13.38#ibcon#enter wrdev, iclass 7, count 2 2006.174.01:19:13.38#ibcon#first serial, iclass 7, count 2 2006.174.01:19:13.38#ibcon#enter sib2, iclass 7, count 2 2006.174.01:19:13.38#ibcon#flushed, iclass 7, count 2 2006.174.01:19:13.38#ibcon#about to write, iclass 7, count 2 2006.174.01:19:13.38#ibcon#wrote, iclass 7, count 2 2006.174.01:19:13.38#ibcon#about to read 3, iclass 7, count 2 2006.174.01:19:13.40#ibcon#read 3, iclass 7, count 2 2006.174.01:19:13.40#ibcon#about to read 4, iclass 7, count 2 2006.174.01:19:13.40#ibcon#read 4, iclass 7, count 2 2006.174.01:19:13.40#ibcon#about to read 5, iclass 7, count 2 2006.174.01:19:13.40#ibcon#read 5, iclass 7, count 2 2006.174.01:19:13.40#ibcon#about to read 6, iclass 7, count 2 2006.174.01:19:13.40#ibcon#read 6, iclass 7, count 2 2006.174.01:19:13.40#ibcon#end of sib2, iclass 7, count 2 2006.174.01:19:13.40#ibcon#*mode == 0, iclass 7, count 2 2006.174.01:19:13.40#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.174.01:19:13.40#ibcon#[27=AT08-04\r\n] 2006.174.01:19:13.40#ibcon#*before write, iclass 7, count 2 2006.174.01:19:13.40#ibcon#enter sib2, iclass 7, count 2 2006.174.01:19:13.40#ibcon#flushed, iclass 7, count 2 2006.174.01:19:13.40#ibcon#about to write, iclass 7, count 2 2006.174.01:19:13.40#ibcon#wrote, iclass 7, count 2 2006.174.01:19:13.40#ibcon#about to read 3, iclass 7, count 2 2006.174.01:19:13.43#ibcon#read 3, iclass 7, count 2 2006.174.01:19:13.43#ibcon#about to read 4, iclass 7, count 2 2006.174.01:19:13.43#ibcon#read 4, iclass 7, count 2 2006.174.01:19:13.43#ibcon#about to read 5, iclass 7, count 2 2006.174.01:19:13.43#ibcon#read 5, iclass 7, count 2 2006.174.01:19:13.43#ibcon#about to read 6, iclass 7, count 2 2006.174.01:19:13.43#ibcon#read 6, iclass 7, count 2 2006.174.01:19:13.43#ibcon#end of sib2, iclass 7, count 2 2006.174.01:19:13.43#ibcon#*after write, iclass 7, count 2 2006.174.01:19:13.43#ibcon#*before return 0, iclass 7, count 2 2006.174.01:19:13.43#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.174.01:19:13.43#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.174.01:19:13.43#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.174.01:19:13.43#ibcon#ireg 7 cls_cnt 0 2006.174.01:19:13.43#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.174.01:19:13.55#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.174.01:19:13.55#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.174.01:19:13.55#ibcon#enter wrdev, iclass 7, count 0 2006.174.01:19:13.55#ibcon#first serial, iclass 7, count 0 2006.174.01:19:13.55#ibcon#enter sib2, iclass 7, count 0 2006.174.01:19:13.55#ibcon#flushed, iclass 7, count 0 2006.174.01:19:13.55#ibcon#about to write, iclass 7, count 0 2006.174.01:19:13.55#ibcon#wrote, iclass 7, count 0 2006.174.01:19:13.55#ibcon#about to read 3, iclass 7, count 0 2006.174.01:19:13.57#ibcon#read 3, iclass 7, count 0 2006.174.01:19:13.57#ibcon#about to read 4, iclass 7, count 0 2006.174.01:19:13.57#ibcon#read 4, iclass 7, count 0 2006.174.01:19:13.57#ibcon#about to read 5, iclass 7, count 0 2006.174.01:19:13.57#ibcon#read 5, iclass 7, count 0 2006.174.01:19:13.57#ibcon#about to read 6, iclass 7, count 0 2006.174.01:19:13.57#ibcon#read 6, iclass 7, count 0 2006.174.01:19:13.57#ibcon#end of sib2, iclass 7, count 0 2006.174.01:19:13.57#ibcon#*mode == 0, iclass 7, count 0 2006.174.01:19:13.57#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.174.01:19:13.57#ibcon#[27=USB\r\n] 2006.174.01:19:13.57#ibcon#*before write, iclass 7, count 0 2006.174.01:19:13.57#ibcon#enter sib2, iclass 7, count 0 2006.174.01:19:13.57#ibcon#flushed, iclass 7, count 0 2006.174.01:19:13.57#ibcon#about to write, iclass 7, count 0 2006.174.01:19:13.57#ibcon#wrote, iclass 7, count 0 2006.174.01:19:13.57#ibcon#about to read 3, iclass 7, count 0 2006.174.01:19:13.60#ibcon#read 3, iclass 7, count 0 2006.174.01:19:13.60#ibcon#about to read 4, iclass 7, count 0 2006.174.01:19:13.60#ibcon#read 4, iclass 7, count 0 2006.174.01:19:13.60#ibcon#about to read 5, iclass 7, count 0 2006.174.01:19:13.60#ibcon#read 5, iclass 7, count 0 2006.174.01:19:13.60#ibcon#about to read 6, iclass 7, count 0 2006.174.01:19:13.60#ibcon#read 6, iclass 7, count 0 2006.174.01:19:13.60#ibcon#end of sib2, iclass 7, count 0 2006.174.01:19:13.60#ibcon#*after write, iclass 7, count 0 2006.174.01:19:13.60#ibcon#*before return 0, iclass 7, count 0 2006.174.01:19:13.60#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.174.01:19:13.60#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.174.01:19:13.60#ibcon#about to clear, iclass 7 cls_cnt 0 2006.174.01:19:13.60#ibcon#cleared, iclass 7 cls_cnt 0 2006.174.01:19:13.60$vck44/vabw=wide 2006.174.01:19:13.60#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.174.01:19:13.60#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.174.01:19:13.60#ibcon#ireg 8 cls_cnt 0 2006.174.01:19:13.60#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.174.01:19:13.60#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.174.01:19:13.60#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.174.01:19:13.60#ibcon#enter wrdev, iclass 11, count 0 2006.174.01:19:13.60#ibcon#first serial, iclass 11, count 0 2006.174.01:19:13.60#ibcon#enter sib2, iclass 11, count 0 2006.174.01:19:13.60#ibcon#flushed, iclass 11, count 0 2006.174.01:19:13.60#ibcon#about to write, iclass 11, count 0 2006.174.01:19:13.60#ibcon#wrote, iclass 11, count 0 2006.174.01:19:13.60#ibcon#about to read 3, iclass 11, count 0 2006.174.01:19:13.62#ibcon#read 3, iclass 11, count 0 2006.174.01:19:13.62#ibcon#about to read 4, iclass 11, count 0 2006.174.01:19:13.62#ibcon#read 4, iclass 11, count 0 2006.174.01:19:13.62#ibcon#about to read 5, iclass 11, count 0 2006.174.01:19:13.62#ibcon#read 5, iclass 11, count 0 2006.174.01:19:13.62#ibcon#about to read 6, iclass 11, count 0 2006.174.01:19:13.62#ibcon#read 6, iclass 11, count 0 2006.174.01:19:13.62#ibcon#end of sib2, iclass 11, count 0 2006.174.01:19:13.62#ibcon#*mode == 0, iclass 11, count 0 2006.174.01:19:13.62#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.174.01:19:13.62#ibcon#[25=BW32\r\n] 2006.174.01:19:13.62#ibcon#*before write, iclass 11, count 0 2006.174.01:19:13.62#ibcon#enter sib2, iclass 11, count 0 2006.174.01:19:13.62#ibcon#flushed, iclass 11, count 0 2006.174.01:19:13.62#ibcon#about to write, iclass 11, count 0 2006.174.01:19:13.62#ibcon#wrote, iclass 11, count 0 2006.174.01:19:13.62#ibcon#about to read 3, iclass 11, count 0 2006.174.01:19:13.65#ibcon#read 3, iclass 11, count 0 2006.174.01:19:13.65#ibcon#about to read 4, iclass 11, count 0 2006.174.01:19:13.65#ibcon#read 4, iclass 11, count 0 2006.174.01:19:13.65#ibcon#about to read 5, iclass 11, count 0 2006.174.01:19:13.65#ibcon#read 5, iclass 11, count 0 2006.174.01:19:13.65#ibcon#about to read 6, iclass 11, count 0 2006.174.01:19:13.65#ibcon#read 6, iclass 11, count 0 2006.174.01:19:13.65#ibcon#end of sib2, iclass 11, count 0 2006.174.01:19:13.65#ibcon#*after write, iclass 11, count 0 2006.174.01:19:13.65#ibcon#*before return 0, iclass 11, count 0 2006.174.01:19:13.65#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.174.01:19:13.65#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.174.01:19:13.65#ibcon#about to clear, iclass 11 cls_cnt 0 2006.174.01:19:13.65#ibcon#cleared, iclass 11 cls_cnt 0 2006.174.01:19:13.65$vck44/vbbw=wide 2006.174.01:19:13.65#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.174.01:19:13.65#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.174.01:19:13.65#ibcon#ireg 8 cls_cnt 0 2006.174.01:19:13.65#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.174.01:19:13.72#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.174.01:19:13.72#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.174.01:19:13.72#ibcon#enter wrdev, iclass 13, count 0 2006.174.01:19:13.72#ibcon#first serial, iclass 13, count 0 2006.174.01:19:13.72#ibcon#enter sib2, iclass 13, count 0 2006.174.01:19:13.72#ibcon#flushed, iclass 13, count 0 2006.174.01:19:13.72#ibcon#about to write, iclass 13, count 0 2006.174.01:19:13.72#ibcon#wrote, iclass 13, count 0 2006.174.01:19:13.72#ibcon#about to read 3, iclass 13, count 0 2006.174.01:19:13.74#ibcon#read 3, iclass 13, count 0 2006.174.01:19:13.74#ibcon#about to read 4, iclass 13, count 0 2006.174.01:19:13.74#ibcon#read 4, iclass 13, count 0 2006.174.01:19:13.74#ibcon#about to read 5, iclass 13, count 0 2006.174.01:19:13.74#ibcon#read 5, iclass 13, count 0 2006.174.01:19:13.74#ibcon#about to read 6, iclass 13, count 0 2006.174.01:19:13.74#ibcon#read 6, iclass 13, count 0 2006.174.01:19:13.74#ibcon#end of sib2, iclass 13, count 0 2006.174.01:19:13.74#ibcon#*mode == 0, iclass 13, count 0 2006.174.01:19:13.74#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.174.01:19:13.74#ibcon#[27=BW32\r\n] 2006.174.01:19:13.74#ibcon#*before write, iclass 13, count 0 2006.174.01:19:13.74#ibcon#enter sib2, iclass 13, count 0 2006.174.01:19:13.74#ibcon#flushed, iclass 13, count 0 2006.174.01:19:13.74#ibcon#about to write, iclass 13, count 0 2006.174.01:19:13.74#ibcon#wrote, iclass 13, count 0 2006.174.01:19:13.74#ibcon#about to read 3, iclass 13, count 0 2006.174.01:19:13.77#ibcon#read 3, iclass 13, count 0 2006.174.01:19:13.77#ibcon#about to read 4, iclass 13, count 0 2006.174.01:19:13.77#ibcon#read 4, iclass 13, count 0 2006.174.01:19:13.77#ibcon#about to read 5, iclass 13, count 0 2006.174.01:19:13.77#ibcon#read 5, iclass 13, count 0 2006.174.01:19:13.77#ibcon#about to read 6, iclass 13, count 0 2006.174.01:19:13.77#ibcon#read 6, iclass 13, count 0 2006.174.01:19:13.77#ibcon#end of sib2, iclass 13, count 0 2006.174.01:19:13.77#ibcon#*after write, iclass 13, count 0 2006.174.01:19:13.77#ibcon#*before return 0, iclass 13, count 0 2006.174.01:19:13.77#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.174.01:19:13.77#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.174.01:19:13.77#ibcon#about to clear, iclass 13 cls_cnt 0 2006.174.01:19:13.77#ibcon#cleared, iclass 13 cls_cnt 0 2006.174.01:19:13.77$setupk4/ifdk4 2006.174.01:19:13.77$ifdk4/lo= 2006.174.01:19:13.77$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.174.01:19:13.77$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.174.01:19:13.77$ifdk4/patch= 2006.174.01:19:13.77$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.174.01:19:13.77$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.174.01:19:13.77$setupk4/!*+20s 2006.174.01:19:18.45#abcon#<5=/06 0.8 1.7 25.51 801003.3\r\n> 2006.174.01:19:18.47#abcon#{5=INTERFACE CLEAR} 2006.174.01:19:18.53#abcon#[5=S1D000X0/0*\r\n] 2006.174.01:19:28.27$setupk4/"tpicd 2006.174.01:19:28.27$setupk4/echo=off 2006.174.01:19:28.27$setupk4/xlog=off 2006.174.01:19:28.27:!2006.174.01:22:49 2006.174.01:19:57.14#trakl#Source acquired 2006.174.01:19:57.14#flagr#flagr/antenna,acquired 2006.174.01:22:49.00:preob 2006.174.01:22:49.13/onsource/TRACKING 2006.174.01:22:49.13:!2006.174.01:22:59 2006.174.01:22:59.00:"tape 2006.174.01:22:59.00:"st=record 2006.174.01:22:59.00:data_valid=on 2006.174.01:22:59.00:midob 2006.174.01:23:00.13/onsource/TRACKING 2006.174.01:23:00.13/wx/25.55,1003.4,81 2006.174.01:23:00.33/cable/+6.4992E-03 2006.174.01:23:01.42/va/01,07,usb,yes,43,46 2006.174.01:23:01.42/va/02,06,usb,yes,42,43 2006.174.01:23:01.42/va/03,05,usb,yes,53,56 2006.174.01:23:01.42/va/04,06,usb,yes,43,45 2006.174.01:23:01.42/va/05,04,usb,yes,34,35 2006.174.01:23:01.42/va/06,03,usb,yes,47,47 2006.174.01:23:01.42/va/07,04,usb,yes,39,40 2006.174.01:23:01.42/va/08,04,usb,yes,33,40 2006.174.01:23:01.65/valo/01,524.99,yes,locked 2006.174.01:23:01.65/valo/02,534.99,yes,locked 2006.174.01:23:01.65/valo/03,564.99,yes,locked 2006.174.01:23:01.65/valo/04,624.99,yes,locked 2006.174.01:23:01.65/valo/05,734.99,yes,locked 2006.174.01:23:01.65/valo/06,814.99,yes,locked 2006.174.01:23:01.65/valo/07,864.99,yes,locked 2006.174.01:23:01.65/valo/08,884.99,yes,locked 2006.174.01:23:02.74/vb/01,04,usb,yes,32,30 2006.174.01:23:02.74/vb/02,04,usb,yes,35,34 2006.174.01:23:02.74/vb/03,04,usb,yes,32,35 2006.174.01:23:02.74/vb/04,04,usb,yes,36,35 2006.174.01:23:02.74/vb/05,04,usb,yes,28,31 2006.174.01:23:02.74/vb/06,04,usb,yes,33,29 2006.174.01:23:02.74/vb/07,04,usb,yes,33,33 2006.174.01:23:02.74/vb/08,04,usb,yes,30,34 2006.174.01:23:02.97/vblo/01,629.99,yes,locked 2006.174.01:23:02.97/vblo/02,634.99,yes,locked 2006.174.01:23:02.97/vblo/03,649.99,yes,locked 2006.174.01:23:02.97/vblo/04,679.99,yes,locked 2006.174.01:23:02.97/vblo/05,709.99,yes,locked 2006.174.01:23:02.97/vblo/06,719.99,yes,locked 2006.174.01:23:02.97/vblo/07,734.99,yes,locked 2006.174.01:23:02.97/vblo/08,744.99,yes,locked 2006.174.01:23:03.12/vabw/8 2006.174.01:23:03.27/vbbw/8 2006.174.01:23:03.42/xfe/off,on,14.7 2006.174.01:23:03.79/ifatt/23,28,28,28 2006.174.01:23:04.07/fmout-gps/S +3.77E-07 2006.174.01:23:04.11:!2006.174.01:23:39 2006.174.01:23:39.01:data_valid=off 2006.174.01:23:39.01:"et 2006.174.01:23:39.02:!+3s 2006.174.01:23:42.03:"tape 2006.174.01:23:42.03:postob 2006.174.01:23:42.25/cable/+6.5015E-03 2006.174.01:23:42.25/wx/25.58,1003.4,80 2006.174.01:23:42.31/fmout-gps/S +3.78E-07 2006.174.01:23:42.31:scan_name=174-0127,jd0606,50 2006.174.01:23:42.32:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.174.01:23:44.14#flagr#flagr/antenna,new-source 2006.174.01:23:44.14:checkk5 2006.174.01:23:44.52/chk_autoobs//k5ts1/ autoobs is running! 2006.174.01:23:44.93/chk_autoobs//k5ts2/ autoobs is running! 2006.174.01:23:45.34/chk_autoobs//k5ts3/ autoobs is running! 2006.174.01:23:45.74/chk_autoobs//k5ts4/ autoobs is running! 2006.174.01:23:46.13/chk_obsdata//k5ts1/T1740122??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.174.01:23:46.53/chk_obsdata//k5ts2/T1740122??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.174.01:23:46.92/chk_obsdata//k5ts3/T1740122??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.174.01:23:47.33/chk_obsdata//k5ts4/T1740122??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.174.01:23:48.05/k5log//k5ts1_log_newline 2006.174.01:23:48.76/k5log//k5ts2_log_newline 2006.174.01:23:49.45/k5log//k5ts3_log_newline 2006.174.01:23:50.16/k5log//k5ts4_log_newline 2006.174.01:23:50.19/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.174.01:23:50.19:setupk4=1 2006.174.01:23:50.19$setupk4/echo=on 2006.174.01:23:50.19$setupk4/pcalon 2006.174.01:23:50.19$pcalon/"no phase cal control is implemented here 2006.174.01:23:50.19$setupk4/"tpicd=stop 2006.174.01:23:50.19$setupk4/"rec=synch_on 2006.174.01:23:50.19$setupk4/"rec_mode=128 2006.174.01:23:50.19$setupk4/!* 2006.174.01:23:50.19$setupk4/recpk4 2006.174.01:23:50.19$recpk4/recpatch= 2006.174.01:23:50.19$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.174.01:23:50.19$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.174.01:23:50.19$setupk4/vck44 2006.174.01:23:50.19$vck44/valo=1,524.99 2006.174.01:23:50.19#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.174.01:23:50.19#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.174.01:23:50.19#ibcon#ireg 17 cls_cnt 0 2006.174.01:23:50.19#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.174.01:23:50.19#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.174.01:23:50.19#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.174.01:23:50.19#ibcon#enter wrdev, iclass 18, count 0 2006.174.01:23:50.19#ibcon#first serial, iclass 18, count 0 2006.174.01:23:50.19#ibcon#enter sib2, iclass 18, count 0 2006.174.01:23:50.19#ibcon#flushed, iclass 18, count 0 2006.174.01:23:50.19#ibcon#about to write, iclass 18, count 0 2006.174.01:23:50.19#ibcon#wrote, iclass 18, count 0 2006.174.01:23:50.19#ibcon#about to read 3, iclass 18, count 0 2006.174.01:23:50.21#ibcon#read 3, iclass 18, count 0 2006.174.01:23:50.21#ibcon#about to read 4, iclass 18, count 0 2006.174.01:23:50.21#ibcon#read 4, iclass 18, count 0 2006.174.01:23:50.21#ibcon#about to read 5, iclass 18, count 0 2006.174.01:23:50.21#ibcon#read 5, iclass 18, count 0 2006.174.01:23:50.21#ibcon#about to read 6, iclass 18, count 0 2006.174.01:23:50.21#ibcon#read 6, iclass 18, count 0 2006.174.01:23:50.21#ibcon#end of sib2, iclass 18, count 0 2006.174.01:23:50.21#ibcon#*mode == 0, iclass 18, count 0 2006.174.01:23:50.21#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.174.01:23:50.21#ibcon#[26=FRQ=01,524.99\r\n] 2006.174.01:23:50.21#ibcon#*before write, iclass 18, count 0 2006.174.01:23:50.21#ibcon#enter sib2, iclass 18, count 0 2006.174.01:23:50.21#ibcon#flushed, iclass 18, count 0 2006.174.01:23:50.21#ibcon#about to write, iclass 18, count 0 2006.174.01:23:50.21#ibcon#wrote, iclass 18, count 0 2006.174.01:23:50.21#ibcon#about to read 3, iclass 18, count 0 2006.174.01:23:50.26#ibcon#read 3, iclass 18, count 0 2006.174.01:23:50.26#ibcon#about to read 4, iclass 18, count 0 2006.174.01:23:50.26#ibcon#read 4, iclass 18, count 0 2006.174.01:23:50.26#ibcon#about to read 5, iclass 18, count 0 2006.174.01:23:50.26#ibcon#read 5, iclass 18, count 0 2006.174.01:23:50.26#ibcon#about to read 6, iclass 18, count 0 2006.174.01:23:50.26#ibcon#read 6, iclass 18, count 0 2006.174.01:23:50.26#ibcon#end of sib2, iclass 18, count 0 2006.174.01:23:50.26#ibcon#*after write, iclass 18, count 0 2006.174.01:23:50.26#ibcon#*before return 0, iclass 18, count 0 2006.174.01:23:50.26#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.174.01:23:50.26#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.174.01:23:50.26#ibcon#about to clear, iclass 18 cls_cnt 0 2006.174.01:23:50.26#ibcon#cleared, iclass 18 cls_cnt 0 2006.174.01:23:50.26$vck44/va=1,7 2006.174.01:23:50.26#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.174.01:23:50.26#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.174.01:23:50.26#ibcon#ireg 11 cls_cnt 2 2006.174.01:23:50.26#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.174.01:23:50.26#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.174.01:23:50.26#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.174.01:23:50.26#ibcon#enter wrdev, iclass 20, count 2 2006.174.01:23:50.26#ibcon#first serial, iclass 20, count 2 2006.174.01:23:50.26#ibcon#enter sib2, iclass 20, count 2 2006.174.01:23:50.26#ibcon#flushed, iclass 20, count 2 2006.174.01:23:50.26#ibcon#about to write, iclass 20, count 2 2006.174.01:23:50.26#ibcon#wrote, iclass 20, count 2 2006.174.01:23:50.26#ibcon#about to read 3, iclass 20, count 2 2006.174.01:23:50.28#ibcon#read 3, iclass 20, count 2 2006.174.01:23:50.28#ibcon#about to read 4, iclass 20, count 2 2006.174.01:23:50.28#ibcon#read 4, iclass 20, count 2 2006.174.01:23:50.28#ibcon#about to read 5, iclass 20, count 2 2006.174.01:23:50.28#ibcon#read 5, iclass 20, count 2 2006.174.01:23:50.28#ibcon#about to read 6, iclass 20, count 2 2006.174.01:23:50.28#ibcon#read 6, iclass 20, count 2 2006.174.01:23:50.28#ibcon#end of sib2, iclass 20, count 2 2006.174.01:23:50.28#ibcon#*mode == 0, iclass 20, count 2 2006.174.01:23:50.28#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.174.01:23:50.28#ibcon#[25=AT01-07\r\n] 2006.174.01:23:50.28#ibcon#*before write, iclass 20, count 2 2006.174.01:23:50.28#ibcon#enter sib2, iclass 20, count 2 2006.174.01:23:50.28#ibcon#flushed, iclass 20, count 2 2006.174.01:23:50.28#ibcon#about to write, iclass 20, count 2 2006.174.01:23:50.28#ibcon#wrote, iclass 20, count 2 2006.174.01:23:50.28#ibcon#about to read 3, iclass 20, count 2 2006.174.01:23:50.31#ibcon#read 3, iclass 20, count 2 2006.174.01:23:50.31#ibcon#about to read 4, iclass 20, count 2 2006.174.01:23:50.31#ibcon#read 4, iclass 20, count 2 2006.174.01:23:50.31#ibcon#about to read 5, iclass 20, count 2 2006.174.01:23:50.31#ibcon#read 5, iclass 20, count 2 2006.174.01:23:50.31#ibcon#about to read 6, iclass 20, count 2 2006.174.01:23:50.31#ibcon#read 6, iclass 20, count 2 2006.174.01:23:50.31#ibcon#end of sib2, iclass 20, count 2 2006.174.01:23:50.31#ibcon#*after write, iclass 20, count 2 2006.174.01:23:50.31#ibcon#*before return 0, iclass 20, count 2 2006.174.01:23:50.31#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.174.01:23:50.31#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.174.01:23:50.31#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.174.01:23:50.31#ibcon#ireg 7 cls_cnt 0 2006.174.01:23:50.31#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.174.01:23:50.43#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.174.01:23:50.43#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.174.01:23:50.43#ibcon#enter wrdev, iclass 20, count 0 2006.174.01:23:50.43#ibcon#first serial, iclass 20, count 0 2006.174.01:23:50.43#ibcon#enter sib2, iclass 20, count 0 2006.174.01:23:50.43#ibcon#flushed, iclass 20, count 0 2006.174.01:23:50.43#ibcon#about to write, iclass 20, count 0 2006.174.01:23:50.43#ibcon#wrote, iclass 20, count 0 2006.174.01:23:50.43#ibcon#about to read 3, iclass 20, count 0 2006.174.01:23:50.45#ibcon#read 3, iclass 20, count 0 2006.174.01:23:50.45#ibcon#about to read 4, iclass 20, count 0 2006.174.01:23:50.45#ibcon#read 4, iclass 20, count 0 2006.174.01:23:50.45#ibcon#about to read 5, iclass 20, count 0 2006.174.01:23:50.45#ibcon#read 5, iclass 20, count 0 2006.174.01:23:50.45#ibcon#about to read 6, iclass 20, count 0 2006.174.01:23:50.45#ibcon#read 6, iclass 20, count 0 2006.174.01:23:50.45#ibcon#end of sib2, iclass 20, count 0 2006.174.01:23:50.45#ibcon#*mode == 0, iclass 20, count 0 2006.174.01:23:50.45#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.174.01:23:50.45#ibcon#[25=USB\r\n] 2006.174.01:23:50.45#ibcon#*before write, iclass 20, count 0 2006.174.01:23:50.45#ibcon#enter sib2, iclass 20, count 0 2006.174.01:23:50.45#ibcon#flushed, iclass 20, count 0 2006.174.01:23:50.45#ibcon#about to write, iclass 20, count 0 2006.174.01:23:50.45#ibcon#wrote, iclass 20, count 0 2006.174.01:23:50.45#ibcon#about to read 3, iclass 20, count 0 2006.174.01:23:50.48#ibcon#read 3, iclass 20, count 0 2006.174.01:23:50.48#ibcon#about to read 4, iclass 20, count 0 2006.174.01:23:50.48#ibcon#read 4, iclass 20, count 0 2006.174.01:23:50.48#ibcon#about to read 5, iclass 20, count 0 2006.174.01:23:50.48#ibcon#read 5, iclass 20, count 0 2006.174.01:23:50.48#ibcon#about to read 6, iclass 20, count 0 2006.174.01:23:50.48#ibcon#read 6, iclass 20, count 0 2006.174.01:23:50.48#ibcon#end of sib2, iclass 20, count 0 2006.174.01:23:50.48#ibcon#*after write, iclass 20, count 0 2006.174.01:23:50.48#ibcon#*before return 0, iclass 20, count 0 2006.174.01:23:50.48#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.174.01:23:50.48#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.174.01:23:50.48#ibcon#about to clear, iclass 20 cls_cnt 0 2006.174.01:23:50.48#ibcon#cleared, iclass 20 cls_cnt 0 2006.174.01:23:50.48$vck44/valo=2,534.99 2006.174.01:23:50.48#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.174.01:23:50.48#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.174.01:23:50.48#ibcon#ireg 17 cls_cnt 0 2006.174.01:23:50.48#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.174.01:23:50.48#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.174.01:23:50.48#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.174.01:23:50.48#ibcon#enter wrdev, iclass 22, count 0 2006.174.01:23:50.48#ibcon#first serial, iclass 22, count 0 2006.174.01:23:50.48#ibcon#enter sib2, iclass 22, count 0 2006.174.01:23:50.48#ibcon#flushed, iclass 22, count 0 2006.174.01:23:50.48#ibcon#about to write, iclass 22, count 0 2006.174.01:23:50.48#ibcon#wrote, iclass 22, count 0 2006.174.01:23:50.48#ibcon#about to read 3, iclass 22, count 0 2006.174.01:23:50.50#ibcon#read 3, iclass 22, count 0 2006.174.01:23:50.50#ibcon#about to read 4, iclass 22, count 0 2006.174.01:23:50.50#ibcon#read 4, iclass 22, count 0 2006.174.01:23:50.50#ibcon#about to read 5, iclass 22, count 0 2006.174.01:23:50.50#ibcon#read 5, iclass 22, count 0 2006.174.01:23:50.50#ibcon#about to read 6, iclass 22, count 0 2006.174.01:23:50.50#ibcon#read 6, iclass 22, count 0 2006.174.01:23:50.50#ibcon#end of sib2, iclass 22, count 0 2006.174.01:23:50.50#ibcon#*mode == 0, iclass 22, count 0 2006.174.01:23:50.50#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.174.01:23:50.50#ibcon#[26=FRQ=02,534.99\r\n] 2006.174.01:23:50.50#ibcon#*before write, iclass 22, count 0 2006.174.01:23:50.50#ibcon#enter sib2, iclass 22, count 0 2006.174.01:23:50.50#ibcon#flushed, iclass 22, count 0 2006.174.01:23:50.50#ibcon#about to write, iclass 22, count 0 2006.174.01:23:50.50#ibcon#wrote, iclass 22, count 0 2006.174.01:23:50.50#ibcon#about to read 3, iclass 22, count 0 2006.174.01:23:50.54#ibcon#read 3, iclass 22, count 0 2006.174.01:23:50.54#ibcon#about to read 4, iclass 22, count 0 2006.174.01:23:50.54#ibcon#read 4, iclass 22, count 0 2006.174.01:23:50.54#ibcon#about to read 5, iclass 22, count 0 2006.174.01:23:50.54#ibcon#read 5, iclass 22, count 0 2006.174.01:23:50.54#ibcon#about to read 6, iclass 22, count 0 2006.174.01:23:50.54#ibcon#read 6, iclass 22, count 0 2006.174.01:23:50.54#ibcon#end of sib2, iclass 22, count 0 2006.174.01:23:50.54#ibcon#*after write, iclass 22, count 0 2006.174.01:23:50.54#ibcon#*before return 0, iclass 22, count 0 2006.174.01:23:50.54#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.174.01:23:50.54#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.174.01:23:50.54#ibcon#about to clear, iclass 22 cls_cnt 0 2006.174.01:23:50.54#ibcon#cleared, iclass 22 cls_cnt 0 2006.174.01:23:50.54$vck44/va=2,6 2006.174.01:23:50.54#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.174.01:23:50.54#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.174.01:23:50.54#ibcon#ireg 11 cls_cnt 2 2006.174.01:23:50.54#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.174.01:23:50.60#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.174.01:23:50.60#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.174.01:23:50.60#ibcon#enter wrdev, iclass 24, count 2 2006.174.01:23:50.60#ibcon#first serial, iclass 24, count 2 2006.174.01:23:50.60#ibcon#enter sib2, iclass 24, count 2 2006.174.01:23:50.60#ibcon#flushed, iclass 24, count 2 2006.174.01:23:50.60#ibcon#about to write, iclass 24, count 2 2006.174.01:23:50.60#ibcon#wrote, iclass 24, count 2 2006.174.01:23:50.60#ibcon#about to read 3, iclass 24, count 2 2006.174.01:23:50.62#ibcon#read 3, iclass 24, count 2 2006.174.01:23:50.62#ibcon#about to read 4, iclass 24, count 2 2006.174.01:23:50.62#ibcon#read 4, iclass 24, count 2 2006.174.01:23:50.62#ibcon#about to read 5, iclass 24, count 2 2006.174.01:23:50.62#ibcon#read 5, iclass 24, count 2 2006.174.01:23:50.62#ibcon#about to read 6, iclass 24, count 2 2006.174.01:23:50.62#ibcon#read 6, iclass 24, count 2 2006.174.01:23:50.62#ibcon#end of sib2, iclass 24, count 2 2006.174.01:23:50.62#ibcon#*mode == 0, iclass 24, count 2 2006.174.01:23:50.62#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.174.01:23:50.62#ibcon#[25=AT02-06\r\n] 2006.174.01:23:50.62#ibcon#*before write, iclass 24, count 2 2006.174.01:23:50.62#ibcon#enter sib2, iclass 24, count 2 2006.174.01:23:50.62#ibcon#flushed, iclass 24, count 2 2006.174.01:23:50.62#ibcon#about to write, iclass 24, count 2 2006.174.01:23:50.62#ibcon#wrote, iclass 24, count 2 2006.174.01:23:50.62#ibcon#about to read 3, iclass 24, count 2 2006.174.01:23:50.65#ibcon#read 3, iclass 24, count 2 2006.174.01:23:50.65#ibcon#about to read 4, iclass 24, count 2 2006.174.01:23:50.65#ibcon#read 4, iclass 24, count 2 2006.174.01:23:50.65#ibcon#about to read 5, iclass 24, count 2 2006.174.01:23:50.65#ibcon#read 5, iclass 24, count 2 2006.174.01:23:50.65#ibcon#about to read 6, iclass 24, count 2 2006.174.01:23:50.65#ibcon#read 6, iclass 24, count 2 2006.174.01:23:50.65#ibcon#end of sib2, iclass 24, count 2 2006.174.01:23:50.65#ibcon#*after write, iclass 24, count 2 2006.174.01:23:50.65#ibcon#*before return 0, iclass 24, count 2 2006.174.01:23:50.65#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.174.01:23:50.65#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.174.01:23:50.65#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.174.01:23:50.65#ibcon#ireg 7 cls_cnt 0 2006.174.01:23:50.65#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.174.01:23:50.77#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.174.01:23:50.77#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.174.01:23:50.77#ibcon#enter wrdev, iclass 24, count 0 2006.174.01:23:50.77#ibcon#first serial, iclass 24, count 0 2006.174.01:23:50.77#ibcon#enter sib2, iclass 24, count 0 2006.174.01:23:50.77#ibcon#flushed, iclass 24, count 0 2006.174.01:23:50.77#ibcon#about to write, iclass 24, count 0 2006.174.01:23:50.77#ibcon#wrote, iclass 24, count 0 2006.174.01:23:50.77#ibcon#about to read 3, iclass 24, count 0 2006.174.01:23:50.79#ibcon#read 3, iclass 24, count 0 2006.174.01:23:50.79#ibcon#about to read 4, iclass 24, count 0 2006.174.01:23:50.79#ibcon#read 4, iclass 24, count 0 2006.174.01:23:50.79#ibcon#about to read 5, iclass 24, count 0 2006.174.01:23:50.79#ibcon#read 5, iclass 24, count 0 2006.174.01:23:50.79#ibcon#about to read 6, iclass 24, count 0 2006.174.01:23:50.79#ibcon#read 6, iclass 24, count 0 2006.174.01:23:50.79#ibcon#end of sib2, iclass 24, count 0 2006.174.01:23:50.79#ibcon#*mode == 0, iclass 24, count 0 2006.174.01:23:50.79#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.174.01:23:50.79#ibcon#[25=USB\r\n] 2006.174.01:23:50.79#ibcon#*before write, iclass 24, count 0 2006.174.01:23:50.79#ibcon#enter sib2, iclass 24, count 0 2006.174.01:23:50.79#ibcon#flushed, iclass 24, count 0 2006.174.01:23:50.79#ibcon#about to write, iclass 24, count 0 2006.174.01:23:50.79#ibcon#wrote, iclass 24, count 0 2006.174.01:23:50.79#ibcon#about to read 3, iclass 24, count 0 2006.174.01:23:50.82#ibcon#read 3, iclass 24, count 0 2006.174.01:23:50.82#ibcon#about to read 4, iclass 24, count 0 2006.174.01:23:50.82#ibcon#read 4, iclass 24, count 0 2006.174.01:23:50.82#ibcon#about to read 5, iclass 24, count 0 2006.174.01:23:50.82#ibcon#read 5, iclass 24, count 0 2006.174.01:23:50.82#ibcon#about to read 6, iclass 24, count 0 2006.174.01:23:50.82#ibcon#read 6, iclass 24, count 0 2006.174.01:23:50.82#ibcon#end of sib2, iclass 24, count 0 2006.174.01:23:50.82#ibcon#*after write, iclass 24, count 0 2006.174.01:23:50.82#ibcon#*before return 0, iclass 24, count 0 2006.174.01:23:50.82#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.174.01:23:50.82#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.174.01:23:50.82#ibcon#about to clear, iclass 24 cls_cnt 0 2006.174.01:23:50.82#ibcon#cleared, iclass 24 cls_cnt 0 2006.174.01:23:50.82$vck44/valo=3,564.99 2006.174.01:23:50.82#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.174.01:23:50.82#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.174.01:23:50.82#ibcon#ireg 17 cls_cnt 0 2006.174.01:23:50.82#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.174.01:23:50.82#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.174.01:23:50.82#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.174.01:23:50.82#ibcon#enter wrdev, iclass 26, count 0 2006.174.01:23:50.82#ibcon#first serial, iclass 26, count 0 2006.174.01:23:50.82#ibcon#enter sib2, iclass 26, count 0 2006.174.01:23:50.82#ibcon#flushed, iclass 26, count 0 2006.174.01:23:50.82#ibcon#about to write, iclass 26, count 0 2006.174.01:23:50.82#ibcon#wrote, iclass 26, count 0 2006.174.01:23:50.82#ibcon#about to read 3, iclass 26, count 0 2006.174.01:23:50.84#ibcon#read 3, iclass 26, count 0 2006.174.01:23:50.84#ibcon#about to read 4, iclass 26, count 0 2006.174.01:23:50.84#ibcon#read 4, iclass 26, count 0 2006.174.01:23:50.84#ibcon#about to read 5, iclass 26, count 0 2006.174.01:23:50.84#ibcon#read 5, iclass 26, count 0 2006.174.01:23:50.84#ibcon#about to read 6, iclass 26, count 0 2006.174.01:23:50.84#ibcon#read 6, iclass 26, count 0 2006.174.01:23:50.84#ibcon#end of sib2, iclass 26, count 0 2006.174.01:23:50.84#ibcon#*mode == 0, iclass 26, count 0 2006.174.01:23:50.84#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.174.01:23:50.84#ibcon#[26=FRQ=03,564.99\r\n] 2006.174.01:23:50.84#ibcon#*before write, iclass 26, count 0 2006.174.01:23:50.84#ibcon#enter sib2, iclass 26, count 0 2006.174.01:23:50.84#ibcon#flushed, iclass 26, count 0 2006.174.01:23:50.84#ibcon#about to write, iclass 26, count 0 2006.174.01:23:50.84#ibcon#wrote, iclass 26, count 0 2006.174.01:23:50.84#ibcon#about to read 3, iclass 26, count 0 2006.174.01:23:50.88#ibcon#read 3, iclass 26, count 0 2006.174.01:23:50.88#ibcon#about to read 4, iclass 26, count 0 2006.174.01:23:50.88#ibcon#read 4, iclass 26, count 0 2006.174.01:23:50.88#ibcon#about to read 5, iclass 26, count 0 2006.174.01:23:50.88#ibcon#read 5, iclass 26, count 0 2006.174.01:23:50.88#ibcon#about to read 6, iclass 26, count 0 2006.174.01:23:50.88#ibcon#read 6, iclass 26, count 0 2006.174.01:23:50.88#ibcon#end of sib2, iclass 26, count 0 2006.174.01:23:50.88#ibcon#*after write, iclass 26, count 0 2006.174.01:23:50.88#ibcon#*before return 0, iclass 26, count 0 2006.174.01:23:50.88#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.174.01:23:50.88#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.174.01:23:50.88#ibcon#about to clear, iclass 26 cls_cnt 0 2006.174.01:23:50.88#ibcon#cleared, iclass 26 cls_cnt 0 2006.174.01:23:50.88$vck44/va=3,5 2006.174.01:23:50.88#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.174.01:23:50.88#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.174.01:23:50.88#ibcon#ireg 11 cls_cnt 2 2006.174.01:23:50.88#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.174.01:23:50.94#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.174.01:23:50.94#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.174.01:23:50.94#ibcon#enter wrdev, iclass 28, count 2 2006.174.01:23:50.94#ibcon#first serial, iclass 28, count 2 2006.174.01:23:50.94#ibcon#enter sib2, iclass 28, count 2 2006.174.01:23:50.94#ibcon#flushed, iclass 28, count 2 2006.174.01:23:50.94#ibcon#about to write, iclass 28, count 2 2006.174.01:23:50.94#ibcon#wrote, iclass 28, count 2 2006.174.01:23:50.94#ibcon#about to read 3, iclass 28, count 2 2006.174.01:23:50.96#ibcon#read 3, iclass 28, count 2 2006.174.01:23:50.96#ibcon#about to read 4, iclass 28, count 2 2006.174.01:23:50.96#ibcon#read 4, iclass 28, count 2 2006.174.01:23:50.96#ibcon#about to read 5, iclass 28, count 2 2006.174.01:23:50.96#ibcon#read 5, iclass 28, count 2 2006.174.01:23:50.96#ibcon#about to read 6, iclass 28, count 2 2006.174.01:23:50.96#ibcon#read 6, iclass 28, count 2 2006.174.01:23:50.96#ibcon#end of sib2, iclass 28, count 2 2006.174.01:23:50.96#ibcon#*mode == 0, iclass 28, count 2 2006.174.01:23:50.96#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.174.01:23:50.96#ibcon#[25=AT03-05\r\n] 2006.174.01:23:50.96#ibcon#*before write, iclass 28, count 2 2006.174.01:23:50.96#ibcon#enter sib2, iclass 28, count 2 2006.174.01:23:50.96#ibcon#flushed, iclass 28, count 2 2006.174.01:23:50.96#ibcon#about to write, iclass 28, count 2 2006.174.01:23:50.96#ibcon#wrote, iclass 28, count 2 2006.174.01:23:50.96#ibcon#about to read 3, iclass 28, count 2 2006.174.01:23:50.99#ibcon#read 3, iclass 28, count 2 2006.174.01:23:50.99#ibcon#about to read 4, iclass 28, count 2 2006.174.01:23:50.99#ibcon#read 4, iclass 28, count 2 2006.174.01:23:50.99#ibcon#about to read 5, iclass 28, count 2 2006.174.01:23:50.99#ibcon#read 5, iclass 28, count 2 2006.174.01:23:50.99#ibcon#about to read 6, iclass 28, count 2 2006.174.01:23:50.99#ibcon#read 6, iclass 28, count 2 2006.174.01:23:50.99#ibcon#end of sib2, iclass 28, count 2 2006.174.01:23:50.99#ibcon#*after write, iclass 28, count 2 2006.174.01:23:50.99#ibcon#*before return 0, iclass 28, count 2 2006.174.01:23:50.99#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.174.01:23:50.99#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.174.01:23:50.99#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.174.01:23:50.99#ibcon#ireg 7 cls_cnt 0 2006.174.01:23:50.99#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.174.01:23:51.11#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.174.01:23:51.11#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.174.01:23:51.11#ibcon#enter wrdev, iclass 28, count 0 2006.174.01:23:51.11#ibcon#first serial, iclass 28, count 0 2006.174.01:23:51.11#ibcon#enter sib2, iclass 28, count 0 2006.174.01:23:51.11#ibcon#flushed, iclass 28, count 0 2006.174.01:23:51.11#ibcon#about to write, iclass 28, count 0 2006.174.01:23:51.11#ibcon#wrote, iclass 28, count 0 2006.174.01:23:51.11#ibcon#about to read 3, iclass 28, count 0 2006.174.01:23:51.13#ibcon#read 3, iclass 28, count 0 2006.174.01:23:51.13#ibcon#about to read 4, iclass 28, count 0 2006.174.01:23:51.13#ibcon#read 4, iclass 28, count 0 2006.174.01:23:51.13#ibcon#about to read 5, iclass 28, count 0 2006.174.01:23:51.13#ibcon#read 5, iclass 28, count 0 2006.174.01:23:51.13#ibcon#about to read 6, iclass 28, count 0 2006.174.01:23:51.13#ibcon#read 6, iclass 28, count 0 2006.174.01:23:51.13#ibcon#end of sib2, iclass 28, count 0 2006.174.01:23:51.13#ibcon#*mode == 0, iclass 28, count 0 2006.174.01:23:51.13#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.174.01:23:51.13#ibcon#[25=USB\r\n] 2006.174.01:23:51.13#ibcon#*before write, iclass 28, count 0 2006.174.01:23:51.13#ibcon#enter sib2, iclass 28, count 0 2006.174.01:23:51.13#ibcon#flushed, iclass 28, count 0 2006.174.01:23:51.13#ibcon#about to write, iclass 28, count 0 2006.174.01:23:51.13#ibcon#wrote, iclass 28, count 0 2006.174.01:23:51.13#ibcon#about to read 3, iclass 28, count 0 2006.174.01:23:51.16#ibcon#read 3, iclass 28, count 0 2006.174.01:23:51.16#ibcon#about to read 4, iclass 28, count 0 2006.174.01:23:51.16#ibcon#read 4, iclass 28, count 0 2006.174.01:23:51.16#ibcon#about to read 5, iclass 28, count 0 2006.174.01:23:51.16#ibcon#read 5, iclass 28, count 0 2006.174.01:23:51.16#ibcon#about to read 6, iclass 28, count 0 2006.174.01:23:51.16#ibcon#read 6, iclass 28, count 0 2006.174.01:23:51.16#ibcon#end of sib2, iclass 28, count 0 2006.174.01:23:51.16#ibcon#*after write, iclass 28, count 0 2006.174.01:23:51.16#ibcon#*before return 0, iclass 28, count 0 2006.174.01:23:51.16#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.174.01:23:51.16#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.174.01:23:51.16#ibcon#about to clear, iclass 28 cls_cnt 0 2006.174.01:23:51.16#ibcon#cleared, iclass 28 cls_cnt 0 2006.174.01:23:51.16$vck44/valo=4,624.99 2006.174.01:23:51.16#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.174.01:23:51.16#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.174.01:23:51.16#ibcon#ireg 17 cls_cnt 0 2006.174.01:23:51.16#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.174.01:23:51.16#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.174.01:23:51.16#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.174.01:23:51.16#ibcon#enter wrdev, iclass 30, count 0 2006.174.01:23:51.16#ibcon#first serial, iclass 30, count 0 2006.174.01:23:51.16#ibcon#enter sib2, iclass 30, count 0 2006.174.01:23:51.16#ibcon#flushed, iclass 30, count 0 2006.174.01:23:51.16#ibcon#about to write, iclass 30, count 0 2006.174.01:23:51.16#ibcon#wrote, iclass 30, count 0 2006.174.01:23:51.16#ibcon#about to read 3, iclass 30, count 0 2006.174.01:23:51.18#ibcon#read 3, iclass 30, count 0 2006.174.01:23:51.18#ibcon#about to read 4, iclass 30, count 0 2006.174.01:23:51.18#ibcon#read 4, iclass 30, count 0 2006.174.01:23:51.18#ibcon#about to read 5, iclass 30, count 0 2006.174.01:23:51.18#ibcon#read 5, iclass 30, count 0 2006.174.01:23:51.18#ibcon#about to read 6, iclass 30, count 0 2006.174.01:23:51.18#ibcon#read 6, iclass 30, count 0 2006.174.01:23:51.18#ibcon#end of sib2, iclass 30, count 0 2006.174.01:23:51.18#ibcon#*mode == 0, iclass 30, count 0 2006.174.01:23:51.18#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.174.01:23:51.18#ibcon#[26=FRQ=04,624.99\r\n] 2006.174.01:23:51.18#ibcon#*before write, iclass 30, count 0 2006.174.01:23:51.18#ibcon#enter sib2, iclass 30, count 0 2006.174.01:23:51.18#ibcon#flushed, iclass 30, count 0 2006.174.01:23:51.18#ibcon#about to write, iclass 30, count 0 2006.174.01:23:51.18#ibcon#wrote, iclass 30, count 0 2006.174.01:23:51.18#ibcon#about to read 3, iclass 30, count 0 2006.174.01:23:51.22#ibcon#read 3, iclass 30, count 0 2006.174.01:23:51.22#ibcon#about to read 4, iclass 30, count 0 2006.174.01:23:51.22#ibcon#read 4, iclass 30, count 0 2006.174.01:23:51.22#ibcon#about to read 5, iclass 30, count 0 2006.174.01:23:51.22#ibcon#read 5, iclass 30, count 0 2006.174.01:23:51.22#ibcon#about to read 6, iclass 30, count 0 2006.174.01:23:51.22#ibcon#read 6, iclass 30, count 0 2006.174.01:23:51.22#ibcon#end of sib2, iclass 30, count 0 2006.174.01:23:51.22#ibcon#*after write, iclass 30, count 0 2006.174.01:23:51.22#ibcon#*before return 0, iclass 30, count 0 2006.174.01:23:51.22#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.174.01:23:51.22#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.174.01:23:51.22#ibcon#about to clear, iclass 30 cls_cnt 0 2006.174.01:23:51.22#ibcon#cleared, iclass 30 cls_cnt 0 2006.174.01:23:51.22$vck44/va=4,6 2006.174.01:23:51.22#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.174.01:23:51.22#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.174.01:23:51.22#ibcon#ireg 11 cls_cnt 2 2006.174.01:23:51.22#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.174.01:23:51.28#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.174.01:23:51.28#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.174.01:23:51.28#ibcon#enter wrdev, iclass 32, count 2 2006.174.01:23:51.28#ibcon#first serial, iclass 32, count 2 2006.174.01:23:51.28#ibcon#enter sib2, iclass 32, count 2 2006.174.01:23:51.28#ibcon#flushed, iclass 32, count 2 2006.174.01:23:51.28#ibcon#about to write, iclass 32, count 2 2006.174.01:23:51.28#ibcon#wrote, iclass 32, count 2 2006.174.01:23:51.28#ibcon#about to read 3, iclass 32, count 2 2006.174.01:23:51.30#ibcon#read 3, iclass 32, count 2 2006.174.01:23:51.30#ibcon#about to read 4, iclass 32, count 2 2006.174.01:23:51.30#ibcon#read 4, iclass 32, count 2 2006.174.01:23:51.30#ibcon#about to read 5, iclass 32, count 2 2006.174.01:23:51.30#ibcon#read 5, iclass 32, count 2 2006.174.01:23:51.30#ibcon#about to read 6, iclass 32, count 2 2006.174.01:23:51.30#ibcon#read 6, iclass 32, count 2 2006.174.01:23:51.30#ibcon#end of sib2, iclass 32, count 2 2006.174.01:23:51.30#ibcon#*mode == 0, iclass 32, count 2 2006.174.01:23:51.30#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.174.01:23:51.30#ibcon#[25=AT04-06\r\n] 2006.174.01:23:51.30#ibcon#*before write, iclass 32, count 2 2006.174.01:23:51.30#ibcon#enter sib2, iclass 32, count 2 2006.174.01:23:51.30#ibcon#flushed, iclass 32, count 2 2006.174.01:23:51.30#ibcon#about to write, iclass 32, count 2 2006.174.01:23:51.30#ibcon#wrote, iclass 32, count 2 2006.174.01:23:51.30#ibcon#about to read 3, iclass 32, count 2 2006.174.01:23:51.33#ibcon#read 3, iclass 32, count 2 2006.174.01:23:51.33#ibcon#about to read 4, iclass 32, count 2 2006.174.01:23:51.33#ibcon#read 4, iclass 32, count 2 2006.174.01:23:51.33#ibcon#about to read 5, iclass 32, count 2 2006.174.01:23:51.33#ibcon#read 5, iclass 32, count 2 2006.174.01:23:51.33#ibcon#about to read 6, iclass 32, count 2 2006.174.01:23:51.33#ibcon#read 6, iclass 32, count 2 2006.174.01:23:51.33#ibcon#end of sib2, iclass 32, count 2 2006.174.01:23:51.33#ibcon#*after write, iclass 32, count 2 2006.174.01:23:51.33#ibcon#*before return 0, iclass 32, count 2 2006.174.01:23:51.33#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.174.01:23:51.33#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.174.01:23:51.33#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.174.01:23:51.33#ibcon#ireg 7 cls_cnt 0 2006.174.01:23:51.33#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.174.01:23:51.45#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.174.01:23:51.45#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.174.01:23:51.45#ibcon#enter wrdev, iclass 32, count 0 2006.174.01:23:51.45#ibcon#first serial, iclass 32, count 0 2006.174.01:23:51.45#ibcon#enter sib2, iclass 32, count 0 2006.174.01:23:51.45#ibcon#flushed, iclass 32, count 0 2006.174.01:23:51.45#ibcon#about to write, iclass 32, count 0 2006.174.01:23:51.45#ibcon#wrote, iclass 32, count 0 2006.174.01:23:51.45#ibcon#about to read 3, iclass 32, count 0 2006.174.01:23:51.47#ibcon#read 3, iclass 32, count 0 2006.174.01:23:51.47#ibcon#about to read 4, iclass 32, count 0 2006.174.01:23:51.47#ibcon#read 4, iclass 32, count 0 2006.174.01:23:51.47#ibcon#about to read 5, iclass 32, count 0 2006.174.01:23:51.47#ibcon#read 5, iclass 32, count 0 2006.174.01:23:51.47#ibcon#about to read 6, iclass 32, count 0 2006.174.01:23:51.47#ibcon#read 6, iclass 32, count 0 2006.174.01:23:51.47#ibcon#end of sib2, iclass 32, count 0 2006.174.01:23:51.47#ibcon#*mode == 0, iclass 32, count 0 2006.174.01:23:51.47#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.174.01:23:51.47#ibcon#[25=USB\r\n] 2006.174.01:23:51.47#ibcon#*before write, iclass 32, count 0 2006.174.01:23:51.47#ibcon#enter sib2, iclass 32, count 0 2006.174.01:23:51.47#ibcon#flushed, iclass 32, count 0 2006.174.01:23:51.47#ibcon#about to write, iclass 32, count 0 2006.174.01:23:51.47#ibcon#wrote, iclass 32, count 0 2006.174.01:23:51.47#ibcon#about to read 3, iclass 32, count 0 2006.174.01:23:51.50#ibcon#read 3, iclass 32, count 0 2006.174.01:23:51.50#ibcon#about to read 4, iclass 32, count 0 2006.174.01:23:51.50#ibcon#read 4, iclass 32, count 0 2006.174.01:23:51.50#ibcon#about to read 5, iclass 32, count 0 2006.174.01:23:51.50#ibcon#read 5, iclass 32, count 0 2006.174.01:23:51.50#ibcon#about to read 6, iclass 32, count 0 2006.174.01:23:51.50#ibcon#read 6, iclass 32, count 0 2006.174.01:23:51.50#ibcon#end of sib2, iclass 32, count 0 2006.174.01:23:51.50#ibcon#*after write, iclass 32, count 0 2006.174.01:23:51.50#ibcon#*before return 0, iclass 32, count 0 2006.174.01:23:51.50#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.174.01:23:51.50#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.174.01:23:51.50#ibcon#about to clear, iclass 32 cls_cnt 0 2006.174.01:23:51.50#ibcon#cleared, iclass 32 cls_cnt 0 2006.174.01:23:51.50$vck44/valo=5,734.99 2006.174.01:23:51.50#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.174.01:23:51.50#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.174.01:23:51.50#ibcon#ireg 17 cls_cnt 0 2006.174.01:23:51.50#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.174.01:23:51.50#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.174.01:23:51.50#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.174.01:23:51.50#ibcon#enter wrdev, iclass 34, count 0 2006.174.01:23:51.50#ibcon#first serial, iclass 34, count 0 2006.174.01:23:51.50#ibcon#enter sib2, iclass 34, count 0 2006.174.01:23:51.50#ibcon#flushed, iclass 34, count 0 2006.174.01:23:51.50#ibcon#about to write, iclass 34, count 0 2006.174.01:23:51.50#ibcon#wrote, iclass 34, count 0 2006.174.01:23:51.50#ibcon#about to read 3, iclass 34, count 0 2006.174.01:23:51.52#ibcon#read 3, iclass 34, count 0 2006.174.01:23:51.52#ibcon#about to read 4, iclass 34, count 0 2006.174.01:23:51.52#ibcon#read 4, iclass 34, count 0 2006.174.01:23:51.52#ibcon#about to read 5, iclass 34, count 0 2006.174.01:23:51.52#ibcon#read 5, iclass 34, count 0 2006.174.01:23:51.52#ibcon#about to read 6, iclass 34, count 0 2006.174.01:23:51.52#ibcon#read 6, iclass 34, count 0 2006.174.01:23:51.52#ibcon#end of sib2, iclass 34, count 0 2006.174.01:23:51.52#ibcon#*mode == 0, iclass 34, count 0 2006.174.01:23:51.52#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.174.01:23:51.52#ibcon#[26=FRQ=05,734.99\r\n] 2006.174.01:23:51.52#ibcon#*before write, iclass 34, count 0 2006.174.01:23:51.52#ibcon#enter sib2, iclass 34, count 0 2006.174.01:23:51.52#ibcon#flushed, iclass 34, count 0 2006.174.01:23:51.52#ibcon#about to write, iclass 34, count 0 2006.174.01:23:51.52#ibcon#wrote, iclass 34, count 0 2006.174.01:23:51.52#ibcon#about to read 3, iclass 34, count 0 2006.174.01:23:51.56#ibcon#read 3, iclass 34, count 0 2006.174.01:23:51.56#ibcon#about to read 4, iclass 34, count 0 2006.174.01:23:51.56#ibcon#read 4, iclass 34, count 0 2006.174.01:23:51.56#ibcon#about to read 5, iclass 34, count 0 2006.174.01:23:51.56#ibcon#read 5, iclass 34, count 0 2006.174.01:23:51.56#ibcon#about to read 6, iclass 34, count 0 2006.174.01:23:51.56#ibcon#read 6, iclass 34, count 0 2006.174.01:23:51.56#ibcon#end of sib2, iclass 34, count 0 2006.174.01:23:51.56#ibcon#*after write, iclass 34, count 0 2006.174.01:23:51.56#ibcon#*before return 0, iclass 34, count 0 2006.174.01:23:51.56#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.174.01:23:51.56#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.174.01:23:51.56#ibcon#about to clear, iclass 34 cls_cnt 0 2006.174.01:23:51.56#ibcon#cleared, iclass 34 cls_cnt 0 2006.174.01:23:51.56$vck44/va=5,4 2006.174.01:23:51.56#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.174.01:23:51.56#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.174.01:23:51.56#ibcon#ireg 11 cls_cnt 2 2006.174.01:23:51.56#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.174.01:23:51.62#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.174.01:23:51.62#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.174.01:23:51.62#ibcon#enter wrdev, iclass 36, count 2 2006.174.01:23:51.62#ibcon#first serial, iclass 36, count 2 2006.174.01:23:51.62#ibcon#enter sib2, iclass 36, count 2 2006.174.01:23:51.62#ibcon#flushed, iclass 36, count 2 2006.174.01:23:51.62#ibcon#about to write, iclass 36, count 2 2006.174.01:23:51.62#ibcon#wrote, iclass 36, count 2 2006.174.01:23:51.62#ibcon#about to read 3, iclass 36, count 2 2006.174.01:23:51.64#ibcon#read 3, iclass 36, count 2 2006.174.01:23:51.64#ibcon#about to read 4, iclass 36, count 2 2006.174.01:23:51.64#ibcon#read 4, iclass 36, count 2 2006.174.01:23:51.64#ibcon#about to read 5, iclass 36, count 2 2006.174.01:23:51.64#ibcon#read 5, iclass 36, count 2 2006.174.01:23:51.64#ibcon#about to read 6, iclass 36, count 2 2006.174.01:23:51.64#ibcon#read 6, iclass 36, count 2 2006.174.01:23:51.64#ibcon#end of sib2, iclass 36, count 2 2006.174.01:23:51.64#ibcon#*mode == 0, iclass 36, count 2 2006.174.01:23:51.64#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.174.01:23:51.64#ibcon#[25=AT05-04\r\n] 2006.174.01:23:51.64#ibcon#*before write, iclass 36, count 2 2006.174.01:23:51.64#ibcon#enter sib2, iclass 36, count 2 2006.174.01:23:51.64#ibcon#flushed, iclass 36, count 2 2006.174.01:23:51.64#ibcon#about to write, iclass 36, count 2 2006.174.01:23:51.64#ibcon#wrote, iclass 36, count 2 2006.174.01:23:51.64#ibcon#about to read 3, iclass 36, count 2 2006.174.01:23:51.67#ibcon#read 3, iclass 36, count 2 2006.174.01:23:51.67#ibcon#about to read 4, iclass 36, count 2 2006.174.01:23:51.67#ibcon#read 4, iclass 36, count 2 2006.174.01:23:51.67#ibcon#about to read 5, iclass 36, count 2 2006.174.01:23:51.67#ibcon#read 5, iclass 36, count 2 2006.174.01:23:51.67#ibcon#about to read 6, iclass 36, count 2 2006.174.01:23:51.67#ibcon#read 6, iclass 36, count 2 2006.174.01:23:51.67#ibcon#end of sib2, iclass 36, count 2 2006.174.01:23:51.67#ibcon#*after write, iclass 36, count 2 2006.174.01:23:51.67#ibcon#*before return 0, iclass 36, count 2 2006.174.01:23:51.67#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.174.01:23:51.67#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.174.01:23:51.67#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.174.01:23:51.67#ibcon#ireg 7 cls_cnt 0 2006.174.01:23:51.67#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.174.01:23:51.79#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.174.01:23:51.79#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.174.01:23:51.79#ibcon#enter wrdev, iclass 36, count 0 2006.174.01:23:51.79#ibcon#first serial, iclass 36, count 0 2006.174.01:23:51.79#ibcon#enter sib2, iclass 36, count 0 2006.174.01:23:51.79#ibcon#flushed, iclass 36, count 0 2006.174.01:23:51.79#ibcon#about to write, iclass 36, count 0 2006.174.01:23:51.79#ibcon#wrote, iclass 36, count 0 2006.174.01:23:51.79#ibcon#about to read 3, iclass 36, count 0 2006.174.01:23:51.81#ibcon#read 3, iclass 36, count 0 2006.174.01:23:51.81#ibcon#about to read 4, iclass 36, count 0 2006.174.01:23:51.81#ibcon#read 4, iclass 36, count 0 2006.174.01:23:51.81#ibcon#about to read 5, iclass 36, count 0 2006.174.01:23:51.81#ibcon#read 5, iclass 36, count 0 2006.174.01:23:51.81#ibcon#about to read 6, iclass 36, count 0 2006.174.01:23:51.81#ibcon#read 6, iclass 36, count 0 2006.174.01:23:51.81#ibcon#end of sib2, iclass 36, count 0 2006.174.01:23:51.81#ibcon#*mode == 0, iclass 36, count 0 2006.174.01:23:51.81#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.174.01:23:51.81#ibcon#[25=USB\r\n] 2006.174.01:23:51.81#ibcon#*before write, iclass 36, count 0 2006.174.01:23:51.81#ibcon#enter sib2, iclass 36, count 0 2006.174.01:23:51.81#ibcon#flushed, iclass 36, count 0 2006.174.01:23:51.81#ibcon#about to write, iclass 36, count 0 2006.174.01:23:51.81#ibcon#wrote, iclass 36, count 0 2006.174.01:23:51.81#ibcon#about to read 3, iclass 36, count 0 2006.174.01:23:51.84#ibcon#read 3, iclass 36, count 0 2006.174.01:23:51.84#ibcon#about to read 4, iclass 36, count 0 2006.174.01:23:51.84#ibcon#read 4, iclass 36, count 0 2006.174.01:23:51.84#ibcon#about to read 5, iclass 36, count 0 2006.174.01:23:51.84#ibcon#read 5, iclass 36, count 0 2006.174.01:23:51.84#ibcon#about to read 6, iclass 36, count 0 2006.174.01:23:51.84#ibcon#read 6, iclass 36, count 0 2006.174.01:23:51.84#ibcon#end of sib2, iclass 36, count 0 2006.174.01:23:51.84#ibcon#*after write, iclass 36, count 0 2006.174.01:23:51.84#ibcon#*before return 0, iclass 36, count 0 2006.174.01:23:51.84#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.174.01:23:51.84#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.174.01:23:51.84#ibcon#about to clear, iclass 36 cls_cnt 0 2006.174.01:23:51.84#ibcon#cleared, iclass 36 cls_cnt 0 2006.174.01:23:51.84$vck44/valo=6,814.99 2006.174.01:23:51.84#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.174.01:23:51.84#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.174.01:23:51.84#ibcon#ireg 17 cls_cnt 0 2006.174.01:23:51.84#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.174.01:23:51.84#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.174.01:23:51.84#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.174.01:23:51.84#ibcon#enter wrdev, iclass 38, count 0 2006.174.01:23:51.84#ibcon#first serial, iclass 38, count 0 2006.174.01:23:51.84#ibcon#enter sib2, iclass 38, count 0 2006.174.01:23:51.84#ibcon#flushed, iclass 38, count 0 2006.174.01:23:51.84#ibcon#about to write, iclass 38, count 0 2006.174.01:23:51.84#ibcon#wrote, iclass 38, count 0 2006.174.01:23:51.84#ibcon#about to read 3, iclass 38, count 0 2006.174.01:23:51.86#ibcon#read 3, iclass 38, count 0 2006.174.01:23:51.86#ibcon#about to read 4, iclass 38, count 0 2006.174.01:23:51.86#ibcon#read 4, iclass 38, count 0 2006.174.01:23:51.86#ibcon#about to read 5, iclass 38, count 0 2006.174.01:23:51.86#ibcon#read 5, iclass 38, count 0 2006.174.01:23:51.86#ibcon#about to read 6, iclass 38, count 0 2006.174.01:23:51.86#ibcon#read 6, iclass 38, count 0 2006.174.01:23:51.86#ibcon#end of sib2, iclass 38, count 0 2006.174.01:23:51.86#ibcon#*mode == 0, iclass 38, count 0 2006.174.01:23:51.86#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.174.01:23:51.86#ibcon#[26=FRQ=06,814.99\r\n] 2006.174.01:23:51.86#ibcon#*before write, iclass 38, count 0 2006.174.01:23:51.86#ibcon#enter sib2, iclass 38, count 0 2006.174.01:23:51.86#ibcon#flushed, iclass 38, count 0 2006.174.01:23:51.86#ibcon#about to write, iclass 38, count 0 2006.174.01:23:51.86#ibcon#wrote, iclass 38, count 0 2006.174.01:23:51.86#ibcon#about to read 3, iclass 38, count 0 2006.174.01:23:51.90#ibcon#read 3, iclass 38, count 0 2006.174.01:23:51.90#ibcon#about to read 4, iclass 38, count 0 2006.174.01:23:51.90#ibcon#read 4, iclass 38, count 0 2006.174.01:23:51.90#ibcon#about to read 5, iclass 38, count 0 2006.174.01:23:51.90#ibcon#read 5, iclass 38, count 0 2006.174.01:23:51.90#ibcon#about to read 6, iclass 38, count 0 2006.174.01:23:51.90#ibcon#read 6, iclass 38, count 0 2006.174.01:23:51.90#ibcon#end of sib2, iclass 38, count 0 2006.174.01:23:51.90#ibcon#*after write, iclass 38, count 0 2006.174.01:23:51.90#ibcon#*before return 0, iclass 38, count 0 2006.174.01:23:51.90#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.174.01:23:51.90#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.174.01:23:51.90#ibcon#about to clear, iclass 38 cls_cnt 0 2006.174.01:23:51.90#ibcon#cleared, iclass 38 cls_cnt 0 2006.174.01:23:51.90$vck44/va=6,3 2006.174.01:23:51.90#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.174.01:23:51.90#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.174.01:23:51.90#ibcon#ireg 11 cls_cnt 2 2006.174.01:23:51.90#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.174.01:23:51.96#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.174.01:23:51.96#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.174.01:23:51.96#ibcon#enter wrdev, iclass 40, count 2 2006.174.01:23:51.96#ibcon#first serial, iclass 40, count 2 2006.174.01:23:51.96#ibcon#enter sib2, iclass 40, count 2 2006.174.01:23:51.96#ibcon#flushed, iclass 40, count 2 2006.174.01:23:51.96#ibcon#about to write, iclass 40, count 2 2006.174.01:23:51.96#ibcon#wrote, iclass 40, count 2 2006.174.01:23:51.96#ibcon#about to read 3, iclass 40, count 2 2006.174.01:23:51.98#ibcon#read 3, iclass 40, count 2 2006.174.01:23:51.98#ibcon#about to read 4, iclass 40, count 2 2006.174.01:23:51.98#ibcon#read 4, iclass 40, count 2 2006.174.01:23:51.98#ibcon#about to read 5, iclass 40, count 2 2006.174.01:23:51.98#ibcon#read 5, iclass 40, count 2 2006.174.01:23:51.98#ibcon#about to read 6, iclass 40, count 2 2006.174.01:23:51.98#ibcon#read 6, iclass 40, count 2 2006.174.01:23:51.98#ibcon#end of sib2, iclass 40, count 2 2006.174.01:23:51.98#ibcon#*mode == 0, iclass 40, count 2 2006.174.01:23:51.98#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.174.01:23:51.98#ibcon#[25=AT06-03\r\n] 2006.174.01:23:51.98#ibcon#*before write, iclass 40, count 2 2006.174.01:23:51.98#ibcon#enter sib2, iclass 40, count 2 2006.174.01:23:51.98#ibcon#flushed, iclass 40, count 2 2006.174.01:23:51.98#ibcon#about to write, iclass 40, count 2 2006.174.01:23:51.98#ibcon#wrote, iclass 40, count 2 2006.174.01:23:51.98#ibcon#about to read 3, iclass 40, count 2 2006.174.01:23:52.01#ibcon#read 3, iclass 40, count 2 2006.174.01:23:52.01#ibcon#about to read 4, iclass 40, count 2 2006.174.01:23:52.01#ibcon#read 4, iclass 40, count 2 2006.174.01:23:52.01#ibcon#about to read 5, iclass 40, count 2 2006.174.01:23:52.01#ibcon#read 5, iclass 40, count 2 2006.174.01:23:52.01#ibcon#about to read 6, iclass 40, count 2 2006.174.01:23:52.01#ibcon#read 6, iclass 40, count 2 2006.174.01:23:52.01#ibcon#end of sib2, iclass 40, count 2 2006.174.01:23:52.01#ibcon#*after write, iclass 40, count 2 2006.174.01:23:52.01#ibcon#*before return 0, iclass 40, count 2 2006.174.01:23:52.01#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.174.01:23:52.01#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.174.01:23:52.01#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.174.01:23:52.01#ibcon#ireg 7 cls_cnt 0 2006.174.01:23:52.01#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.174.01:23:52.13#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.174.01:23:52.13#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.174.01:23:52.13#ibcon#enter wrdev, iclass 40, count 0 2006.174.01:23:52.13#ibcon#first serial, iclass 40, count 0 2006.174.01:23:52.13#ibcon#enter sib2, iclass 40, count 0 2006.174.01:23:52.13#ibcon#flushed, iclass 40, count 0 2006.174.01:23:52.13#ibcon#about to write, iclass 40, count 0 2006.174.01:23:52.13#ibcon#wrote, iclass 40, count 0 2006.174.01:23:52.13#ibcon#about to read 3, iclass 40, count 0 2006.174.01:23:52.15#ibcon#read 3, iclass 40, count 0 2006.174.01:23:52.15#ibcon#about to read 4, iclass 40, count 0 2006.174.01:23:52.15#ibcon#read 4, iclass 40, count 0 2006.174.01:23:52.15#ibcon#about to read 5, iclass 40, count 0 2006.174.01:23:52.15#ibcon#read 5, iclass 40, count 0 2006.174.01:23:52.15#ibcon#about to read 6, iclass 40, count 0 2006.174.01:23:52.15#ibcon#read 6, iclass 40, count 0 2006.174.01:23:52.15#ibcon#end of sib2, iclass 40, count 0 2006.174.01:23:52.15#ibcon#*mode == 0, iclass 40, count 0 2006.174.01:23:52.15#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.174.01:23:52.15#ibcon#[25=USB\r\n] 2006.174.01:23:52.15#ibcon#*before write, iclass 40, count 0 2006.174.01:23:52.15#ibcon#enter sib2, iclass 40, count 0 2006.174.01:23:52.15#ibcon#flushed, iclass 40, count 0 2006.174.01:23:52.15#ibcon#about to write, iclass 40, count 0 2006.174.01:23:52.15#ibcon#wrote, iclass 40, count 0 2006.174.01:23:52.15#ibcon#about to read 3, iclass 40, count 0 2006.174.01:23:52.18#ibcon#read 3, iclass 40, count 0 2006.174.01:23:52.18#ibcon#about to read 4, iclass 40, count 0 2006.174.01:23:52.18#ibcon#read 4, iclass 40, count 0 2006.174.01:23:52.18#ibcon#about to read 5, iclass 40, count 0 2006.174.01:23:52.18#ibcon#read 5, iclass 40, count 0 2006.174.01:23:52.18#ibcon#about to read 6, iclass 40, count 0 2006.174.01:23:52.18#ibcon#read 6, iclass 40, count 0 2006.174.01:23:52.18#ibcon#end of sib2, iclass 40, count 0 2006.174.01:23:52.18#ibcon#*after write, iclass 40, count 0 2006.174.01:23:52.18#ibcon#*before return 0, iclass 40, count 0 2006.174.01:23:52.18#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.174.01:23:52.18#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.174.01:23:52.18#ibcon#about to clear, iclass 40 cls_cnt 0 2006.174.01:23:52.18#ibcon#cleared, iclass 40 cls_cnt 0 2006.174.01:23:52.18$vck44/valo=7,864.99 2006.174.01:23:52.18#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.174.01:23:52.18#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.174.01:23:52.18#ibcon#ireg 17 cls_cnt 0 2006.174.01:23:52.18#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.174.01:23:52.18#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.174.01:23:52.18#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.174.01:23:52.18#ibcon#enter wrdev, iclass 4, count 0 2006.174.01:23:52.18#ibcon#first serial, iclass 4, count 0 2006.174.01:23:52.18#ibcon#enter sib2, iclass 4, count 0 2006.174.01:23:52.18#ibcon#flushed, iclass 4, count 0 2006.174.01:23:52.18#ibcon#about to write, iclass 4, count 0 2006.174.01:23:52.18#ibcon#wrote, iclass 4, count 0 2006.174.01:23:52.18#ibcon#about to read 3, iclass 4, count 0 2006.174.01:23:52.20#ibcon#read 3, iclass 4, count 0 2006.174.01:23:52.20#ibcon#about to read 4, iclass 4, count 0 2006.174.01:23:52.20#ibcon#read 4, iclass 4, count 0 2006.174.01:23:52.20#ibcon#about to read 5, iclass 4, count 0 2006.174.01:23:52.20#ibcon#read 5, iclass 4, count 0 2006.174.01:23:52.20#ibcon#about to read 6, iclass 4, count 0 2006.174.01:23:52.20#ibcon#read 6, iclass 4, count 0 2006.174.01:23:52.20#ibcon#end of sib2, iclass 4, count 0 2006.174.01:23:52.20#ibcon#*mode == 0, iclass 4, count 0 2006.174.01:23:52.20#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.174.01:23:52.20#ibcon#[26=FRQ=07,864.99\r\n] 2006.174.01:23:52.20#ibcon#*before write, iclass 4, count 0 2006.174.01:23:52.20#ibcon#enter sib2, iclass 4, count 0 2006.174.01:23:52.20#ibcon#flushed, iclass 4, count 0 2006.174.01:23:52.20#ibcon#about to write, iclass 4, count 0 2006.174.01:23:52.20#ibcon#wrote, iclass 4, count 0 2006.174.01:23:52.20#ibcon#about to read 3, iclass 4, count 0 2006.174.01:23:52.24#ibcon#read 3, iclass 4, count 0 2006.174.01:23:52.24#ibcon#about to read 4, iclass 4, count 0 2006.174.01:23:52.24#ibcon#read 4, iclass 4, count 0 2006.174.01:23:52.24#ibcon#about to read 5, iclass 4, count 0 2006.174.01:23:52.24#ibcon#read 5, iclass 4, count 0 2006.174.01:23:52.24#ibcon#about to read 6, iclass 4, count 0 2006.174.01:23:52.24#ibcon#read 6, iclass 4, count 0 2006.174.01:23:52.24#ibcon#end of sib2, iclass 4, count 0 2006.174.01:23:52.24#ibcon#*after write, iclass 4, count 0 2006.174.01:23:52.24#ibcon#*before return 0, iclass 4, count 0 2006.174.01:23:52.24#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.174.01:23:52.24#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.174.01:23:52.24#ibcon#about to clear, iclass 4 cls_cnt 0 2006.174.01:23:52.24#ibcon#cleared, iclass 4 cls_cnt 0 2006.174.01:23:52.24$vck44/va=7,4 2006.174.01:23:52.24#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.174.01:23:52.24#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.174.01:23:52.24#ibcon#ireg 11 cls_cnt 2 2006.174.01:23:52.24#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.174.01:23:52.30#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.174.01:23:52.30#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.174.01:23:52.30#ibcon#enter wrdev, iclass 6, count 2 2006.174.01:23:52.30#ibcon#first serial, iclass 6, count 2 2006.174.01:23:52.30#ibcon#enter sib2, iclass 6, count 2 2006.174.01:23:52.30#ibcon#flushed, iclass 6, count 2 2006.174.01:23:52.30#ibcon#about to write, iclass 6, count 2 2006.174.01:23:52.30#ibcon#wrote, iclass 6, count 2 2006.174.01:23:52.30#ibcon#about to read 3, iclass 6, count 2 2006.174.01:23:52.32#ibcon#read 3, iclass 6, count 2 2006.174.01:23:52.32#ibcon#about to read 4, iclass 6, count 2 2006.174.01:23:52.32#ibcon#read 4, iclass 6, count 2 2006.174.01:23:52.32#ibcon#about to read 5, iclass 6, count 2 2006.174.01:23:52.32#ibcon#read 5, iclass 6, count 2 2006.174.01:23:52.32#ibcon#about to read 6, iclass 6, count 2 2006.174.01:23:52.32#ibcon#read 6, iclass 6, count 2 2006.174.01:23:52.32#ibcon#end of sib2, iclass 6, count 2 2006.174.01:23:52.32#ibcon#*mode == 0, iclass 6, count 2 2006.174.01:23:52.32#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.174.01:23:52.32#ibcon#[25=AT07-04\r\n] 2006.174.01:23:52.32#ibcon#*before write, iclass 6, count 2 2006.174.01:23:52.32#ibcon#enter sib2, iclass 6, count 2 2006.174.01:23:52.32#ibcon#flushed, iclass 6, count 2 2006.174.01:23:52.32#ibcon#about to write, iclass 6, count 2 2006.174.01:23:52.32#ibcon#wrote, iclass 6, count 2 2006.174.01:23:52.32#ibcon#about to read 3, iclass 6, count 2 2006.174.01:23:52.35#ibcon#read 3, iclass 6, count 2 2006.174.01:23:52.35#ibcon#about to read 4, iclass 6, count 2 2006.174.01:23:52.35#ibcon#read 4, iclass 6, count 2 2006.174.01:23:52.35#ibcon#about to read 5, iclass 6, count 2 2006.174.01:23:52.35#ibcon#read 5, iclass 6, count 2 2006.174.01:23:52.35#ibcon#about to read 6, iclass 6, count 2 2006.174.01:23:52.35#ibcon#read 6, iclass 6, count 2 2006.174.01:23:52.35#ibcon#end of sib2, iclass 6, count 2 2006.174.01:23:52.35#ibcon#*after write, iclass 6, count 2 2006.174.01:23:52.35#ibcon#*before return 0, iclass 6, count 2 2006.174.01:23:52.35#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.174.01:23:52.35#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.174.01:23:52.35#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.174.01:23:52.35#ibcon#ireg 7 cls_cnt 0 2006.174.01:23:52.35#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.174.01:23:52.47#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.174.01:23:52.47#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.174.01:23:52.47#ibcon#enter wrdev, iclass 6, count 0 2006.174.01:23:52.47#ibcon#first serial, iclass 6, count 0 2006.174.01:23:52.47#ibcon#enter sib2, iclass 6, count 0 2006.174.01:23:52.47#ibcon#flushed, iclass 6, count 0 2006.174.01:23:52.47#ibcon#about to write, iclass 6, count 0 2006.174.01:23:52.47#ibcon#wrote, iclass 6, count 0 2006.174.01:23:52.47#ibcon#about to read 3, iclass 6, count 0 2006.174.01:23:52.49#ibcon#read 3, iclass 6, count 0 2006.174.01:23:52.49#ibcon#about to read 4, iclass 6, count 0 2006.174.01:23:52.49#ibcon#read 4, iclass 6, count 0 2006.174.01:23:52.49#ibcon#about to read 5, iclass 6, count 0 2006.174.01:23:52.49#ibcon#read 5, iclass 6, count 0 2006.174.01:23:52.49#ibcon#about to read 6, iclass 6, count 0 2006.174.01:23:52.49#ibcon#read 6, iclass 6, count 0 2006.174.01:23:52.49#ibcon#end of sib2, iclass 6, count 0 2006.174.01:23:52.49#ibcon#*mode == 0, iclass 6, count 0 2006.174.01:23:52.49#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.174.01:23:52.49#ibcon#[25=USB\r\n] 2006.174.01:23:52.49#ibcon#*before write, iclass 6, count 0 2006.174.01:23:52.49#ibcon#enter sib2, iclass 6, count 0 2006.174.01:23:52.49#ibcon#flushed, iclass 6, count 0 2006.174.01:23:52.49#ibcon#about to write, iclass 6, count 0 2006.174.01:23:52.49#ibcon#wrote, iclass 6, count 0 2006.174.01:23:52.49#ibcon#about to read 3, iclass 6, count 0 2006.174.01:23:52.52#ibcon#read 3, iclass 6, count 0 2006.174.01:23:52.52#ibcon#about to read 4, iclass 6, count 0 2006.174.01:23:52.52#ibcon#read 4, iclass 6, count 0 2006.174.01:23:52.52#ibcon#about to read 5, iclass 6, count 0 2006.174.01:23:52.52#ibcon#read 5, iclass 6, count 0 2006.174.01:23:52.52#ibcon#about to read 6, iclass 6, count 0 2006.174.01:23:52.52#ibcon#read 6, iclass 6, count 0 2006.174.01:23:52.52#ibcon#end of sib2, iclass 6, count 0 2006.174.01:23:52.52#ibcon#*after write, iclass 6, count 0 2006.174.01:23:52.52#ibcon#*before return 0, iclass 6, count 0 2006.174.01:23:52.52#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.174.01:23:52.52#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.174.01:23:52.52#ibcon#about to clear, iclass 6 cls_cnt 0 2006.174.01:23:52.52#ibcon#cleared, iclass 6 cls_cnt 0 2006.174.01:23:52.52$vck44/valo=8,884.99 2006.174.01:23:52.52#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.174.01:23:52.52#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.174.01:23:52.52#ibcon#ireg 17 cls_cnt 0 2006.174.01:23:52.52#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.174.01:23:52.52#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.174.01:23:52.52#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.174.01:23:52.52#ibcon#enter wrdev, iclass 10, count 0 2006.174.01:23:52.52#ibcon#first serial, iclass 10, count 0 2006.174.01:23:52.52#ibcon#enter sib2, iclass 10, count 0 2006.174.01:23:52.52#ibcon#flushed, iclass 10, count 0 2006.174.01:23:52.52#ibcon#about to write, iclass 10, count 0 2006.174.01:23:52.52#ibcon#wrote, iclass 10, count 0 2006.174.01:23:52.52#ibcon#about to read 3, iclass 10, count 0 2006.174.01:23:52.54#ibcon#read 3, iclass 10, count 0 2006.174.01:23:52.54#ibcon#about to read 4, iclass 10, count 0 2006.174.01:23:52.54#ibcon#read 4, iclass 10, count 0 2006.174.01:23:52.54#ibcon#about to read 5, iclass 10, count 0 2006.174.01:23:52.54#ibcon#read 5, iclass 10, count 0 2006.174.01:23:52.54#ibcon#about to read 6, iclass 10, count 0 2006.174.01:23:52.54#ibcon#read 6, iclass 10, count 0 2006.174.01:23:52.54#ibcon#end of sib2, iclass 10, count 0 2006.174.01:23:52.54#ibcon#*mode == 0, iclass 10, count 0 2006.174.01:23:52.54#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.174.01:23:52.54#ibcon#[26=FRQ=08,884.99\r\n] 2006.174.01:23:52.54#ibcon#*before write, iclass 10, count 0 2006.174.01:23:52.54#ibcon#enter sib2, iclass 10, count 0 2006.174.01:23:52.54#ibcon#flushed, iclass 10, count 0 2006.174.01:23:52.54#ibcon#about to write, iclass 10, count 0 2006.174.01:23:52.54#ibcon#wrote, iclass 10, count 0 2006.174.01:23:52.54#ibcon#about to read 3, iclass 10, count 0 2006.174.01:23:52.58#ibcon#read 3, iclass 10, count 0 2006.174.01:23:52.58#ibcon#about to read 4, iclass 10, count 0 2006.174.01:23:52.58#ibcon#read 4, iclass 10, count 0 2006.174.01:23:52.58#ibcon#about to read 5, iclass 10, count 0 2006.174.01:23:52.58#ibcon#read 5, iclass 10, count 0 2006.174.01:23:52.58#ibcon#about to read 6, iclass 10, count 0 2006.174.01:23:52.58#ibcon#read 6, iclass 10, count 0 2006.174.01:23:52.58#ibcon#end of sib2, iclass 10, count 0 2006.174.01:23:52.58#ibcon#*after write, iclass 10, count 0 2006.174.01:23:52.58#ibcon#*before return 0, iclass 10, count 0 2006.174.01:23:52.58#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.174.01:23:52.58#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.174.01:23:52.58#ibcon#about to clear, iclass 10 cls_cnt 0 2006.174.01:23:52.58#ibcon#cleared, iclass 10 cls_cnt 0 2006.174.01:23:52.58$vck44/va=8,4 2006.174.01:23:52.58#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.174.01:23:52.58#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.174.01:23:52.58#ibcon#ireg 11 cls_cnt 2 2006.174.01:23:52.58#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.174.01:23:52.64#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.174.01:23:52.64#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.174.01:23:52.64#ibcon#enter wrdev, iclass 12, count 2 2006.174.01:23:52.64#ibcon#first serial, iclass 12, count 2 2006.174.01:23:52.64#ibcon#enter sib2, iclass 12, count 2 2006.174.01:23:52.64#ibcon#flushed, iclass 12, count 2 2006.174.01:23:52.64#ibcon#about to write, iclass 12, count 2 2006.174.01:23:52.64#ibcon#wrote, iclass 12, count 2 2006.174.01:23:52.64#ibcon#about to read 3, iclass 12, count 2 2006.174.01:23:52.66#ibcon#read 3, iclass 12, count 2 2006.174.01:23:52.66#ibcon#about to read 4, iclass 12, count 2 2006.174.01:23:52.66#ibcon#read 4, iclass 12, count 2 2006.174.01:23:52.66#ibcon#about to read 5, iclass 12, count 2 2006.174.01:23:52.66#ibcon#read 5, iclass 12, count 2 2006.174.01:23:52.66#ibcon#about to read 6, iclass 12, count 2 2006.174.01:23:52.66#ibcon#read 6, iclass 12, count 2 2006.174.01:23:52.66#ibcon#end of sib2, iclass 12, count 2 2006.174.01:23:52.66#ibcon#*mode == 0, iclass 12, count 2 2006.174.01:23:52.66#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.174.01:23:52.66#ibcon#[25=AT08-04\r\n] 2006.174.01:23:52.66#ibcon#*before write, iclass 12, count 2 2006.174.01:23:52.66#ibcon#enter sib2, iclass 12, count 2 2006.174.01:23:52.66#ibcon#flushed, iclass 12, count 2 2006.174.01:23:52.66#ibcon#about to write, iclass 12, count 2 2006.174.01:23:52.66#ibcon#wrote, iclass 12, count 2 2006.174.01:23:52.66#ibcon#about to read 3, iclass 12, count 2 2006.174.01:23:52.69#ibcon#read 3, iclass 12, count 2 2006.174.01:23:52.69#ibcon#about to read 4, iclass 12, count 2 2006.174.01:23:52.69#ibcon#read 4, iclass 12, count 2 2006.174.01:23:52.69#ibcon#about to read 5, iclass 12, count 2 2006.174.01:23:52.69#ibcon#read 5, iclass 12, count 2 2006.174.01:23:52.69#ibcon#about to read 6, iclass 12, count 2 2006.174.01:23:52.69#ibcon#read 6, iclass 12, count 2 2006.174.01:23:52.69#ibcon#end of sib2, iclass 12, count 2 2006.174.01:23:52.69#ibcon#*after write, iclass 12, count 2 2006.174.01:23:52.69#ibcon#*before return 0, iclass 12, count 2 2006.174.01:23:52.69#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.174.01:23:52.69#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.174.01:23:52.69#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.174.01:23:52.69#ibcon#ireg 7 cls_cnt 0 2006.174.01:23:52.69#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.174.01:23:52.81#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.174.01:23:52.81#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.174.01:23:52.81#ibcon#enter wrdev, iclass 12, count 0 2006.174.01:23:52.81#ibcon#first serial, iclass 12, count 0 2006.174.01:23:52.81#ibcon#enter sib2, iclass 12, count 0 2006.174.01:23:52.81#ibcon#flushed, iclass 12, count 0 2006.174.01:23:52.81#ibcon#about to write, iclass 12, count 0 2006.174.01:23:52.81#ibcon#wrote, iclass 12, count 0 2006.174.01:23:52.81#ibcon#about to read 3, iclass 12, count 0 2006.174.01:23:52.83#ibcon#read 3, iclass 12, count 0 2006.174.01:23:52.83#ibcon#about to read 4, iclass 12, count 0 2006.174.01:23:52.83#ibcon#read 4, iclass 12, count 0 2006.174.01:23:52.83#ibcon#about to read 5, iclass 12, count 0 2006.174.01:23:52.83#ibcon#read 5, iclass 12, count 0 2006.174.01:23:52.83#ibcon#about to read 6, iclass 12, count 0 2006.174.01:23:52.83#ibcon#read 6, iclass 12, count 0 2006.174.01:23:52.83#ibcon#end of sib2, iclass 12, count 0 2006.174.01:23:52.83#ibcon#*mode == 0, iclass 12, count 0 2006.174.01:23:52.83#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.174.01:23:52.83#ibcon#[25=USB\r\n] 2006.174.01:23:52.83#ibcon#*before write, iclass 12, count 0 2006.174.01:23:52.83#ibcon#enter sib2, iclass 12, count 0 2006.174.01:23:52.83#ibcon#flushed, iclass 12, count 0 2006.174.01:23:52.83#ibcon#about to write, iclass 12, count 0 2006.174.01:23:52.83#ibcon#wrote, iclass 12, count 0 2006.174.01:23:52.83#ibcon#about to read 3, iclass 12, count 0 2006.174.01:23:52.86#ibcon#read 3, iclass 12, count 0 2006.174.01:23:52.86#ibcon#about to read 4, iclass 12, count 0 2006.174.01:23:52.86#ibcon#read 4, iclass 12, count 0 2006.174.01:23:52.86#ibcon#about to read 5, iclass 12, count 0 2006.174.01:23:52.86#ibcon#read 5, iclass 12, count 0 2006.174.01:23:52.86#ibcon#about to read 6, iclass 12, count 0 2006.174.01:23:52.86#ibcon#read 6, iclass 12, count 0 2006.174.01:23:52.86#ibcon#end of sib2, iclass 12, count 0 2006.174.01:23:52.86#ibcon#*after write, iclass 12, count 0 2006.174.01:23:52.86#ibcon#*before return 0, iclass 12, count 0 2006.174.01:23:52.86#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.174.01:23:52.86#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.174.01:23:52.86#ibcon#about to clear, iclass 12 cls_cnt 0 2006.174.01:23:52.86#ibcon#cleared, iclass 12 cls_cnt 0 2006.174.01:23:52.86$vck44/vblo=1,629.99 2006.174.01:23:52.86#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.174.01:23:52.86#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.174.01:23:52.86#ibcon#ireg 17 cls_cnt 0 2006.174.01:23:52.86#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.174.01:23:52.86#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.174.01:23:52.86#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.174.01:23:52.86#ibcon#enter wrdev, iclass 14, count 0 2006.174.01:23:52.86#ibcon#first serial, iclass 14, count 0 2006.174.01:23:52.86#ibcon#enter sib2, iclass 14, count 0 2006.174.01:23:52.86#ibcon#flushed, iclass 14, count 0 2006.174.01:23:52.86#ibcon#about to write, iclass 14, count 0 2006.174.01:23:52.86#ibcon#wrote, iclass 14, count 0 2006.174.01:23:52.86#ibcon#about to read 3, iclass 14, count 0 2006.174.01:23:52.88#ibcon#read 3, iclass 14, count 0 2006.174.01:23:52.88#ibcon#about to read 4, iclass 14, count 0 2006.174.01:23:52.88#ibcon#read 4, iclass 14, count 0 2006.174.01:23:52.88#ibcon#about to read 5, iclass 14, count 0 2006.174.01:23:52.88#ibcon#read 5, iclass 14, count 0 2006.174.01:23:52.88#ibcon#about to read 6, iclass 14, count 0 2006.174.01:23:52.88#ibcon#read 6, iclass 14, count 0 2006.174.01:23:52.88#ibcon#end of sib2, iclass 14, count 0 2006.174.01:23:52.88#ibcon#*mode == 0, iclass 14, count 0 2006.174.01:23:52.88#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.174.01:23:52.88#ibcon#[28=FRQ=01,629.99\r\n] 2006.174.01:23:52.88#ibcon#*before write, iclass 14, count 0 2006.174.01:23:52.88#ibcon#enter sib2, iclass 14, count 0 2006.174.01:23:52.88#ibcon#flushed, iclass 14, count 0 2006.174.01:23:52.88#ibcon#about to write, iclass 14, count 0 2006.174.01:23:52.88#ibcon#wrote, iclass 14, count 0 2006.174.01:23:52.88#ibcon#about to read 3, iclass 14, count 0 2006.174.01:23:52.92#ibcon#read 3, iclass 14, count 0 2006.174.01:23:52.92#ibcon#about to read 4, iclass 14, count 0 2006.174.01:23:52.92#ibcon#read 4, iclass 14, count 0 2006.174.01:23:52.92#ibcon#about to read 5, iclass 14, count 0 2006.174.01:23:52.92#ibcon#read 5, iclass 14, count 0 2006.174.01:23:52.92#ibcon#about to read 6, iclass 14, count 0 2006.174.01:23:52.92#ibcon#read 6, iclass 14, count 0 2006.174.01:23:52.92#ibcon#end of sib2, iclass 14, count 0 2006.174.01:23:52.92#ibcon#*after write, iclass 14, count 0 2006.174.01:23:52.92#ibcon#*before return 0, iclass 14, count 0 2006.174.01:23:52.92#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.174.01:23:52.92#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.174.01:23:52.92#ibcon#about to clear, iclass 14 cls_cnt 0 2006.174.01:23:52.92#ibcon#cleared, iclass 14 cls_cnt 0 2006.174.01:23:52.92$vck44/vb=1,4 2006.174.01:23:52.92#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.174.01:23:52.92#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.174.01:23:52.92#ibcon#ireg 11 cls_cnt 2 2006.174.01:23:52.92#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.174.01:23:52.92#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.174.01:23:52.92#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.174.01:23:52.92#ibcon#enter wrdev, iclass 16, count 2 2006.174.01:23:52.92#ibcon#first serial, iclass 16, count 2 2006.174.01:23:52.92#ibcon#enter sib2, iclass 16, count 2 2006.174.01:23:52.92#ibcon#flushed, iclass 16, count 2 2006.174.01:23:52.92#ibcon#about to write, iclass 16, count 2 2006.174.01:23:52.92#ibcon#wrote, iclass 16, count 2 2006.174.01:23:52.92#ibcon#about to read 3, iclass 16, count 2 2006.174.01:23:52.94#ibcon#read 3, iclass 16, count 2 2006.174.01:23:52.94#ibcon#about to read 4, iclass 16, count 2 2006.174.01:23:52.94#ibcon#read 4, iclass 16, count 2 2006.174.01:23:52.94#ibcon#about to read 5, iclass 16, count 2 2006.174.01:23:52.94#ibcon#read 5, iclass 16, count 2 2006.174.01:23:52.94#ibcon#about to read 6, iclass 16, count 2 2006.174.01:23:52.94#ibcon#read 6, iclass 16, count 2 2006.174.01:23:52.94#ibcon#end of sib2, iclass 16, count 2 2006.174.01:23:52.94#ibcon#*mode == 0, iclass 16, count 2 2006.174.01:23:52.94#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.174.01:23:52.94#ibcon#[27=AT01-04\r\n] 2006.174.01:23:52.94#ibcon#*before write, iclass 16, count 2 2006.174.01:23:52.94#ibcon#enter sib2, iclass 16, count 2 2006.174.01:23:52.94#ibcon#flushed, iclass 16, count 2 2006.174.01:23:52.94#ibcon#about to write, iclass 16, count 2 2006.174.01:23:52.94#ibcon#wrote, iclass 16, count 2 2006.174.01:23:52.94#ibcon#about to read 3, iclass 16, count 2 2006.174.01:23:52.97#ibcon#read 3, iclass 16, count 2 2006.174.01:23:52.97#ibcon#about to read 4, iclass 16, count 2 2006.174.01:23:52.97#ibcon#read 4, iclass 16, count 2 2006.174.01:23:52.97#ibcon#about to read 5, iclass 16, count 2 2006.174.01:23:52.97#ibcon#read 5, iclass 16, count 2 2006.174.01:23:52.97#ibcon#about to read 6, iclass 16, count 2 2006.174.01:23:52.97#ibcon#read 6, iclass 16, count 2 2006.174.01:23:52.97#ibcon#end of sib2, iclass 16, count 2 2006.174.01:23:52.97#ibcon#*after write, iclass 16, count 2 2006.174.01:23:52.97#ibcon#*before return 0, iclass 16, count 2 2006.174.01:23:52.97#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.174.01:23:52.97#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.174.01:23:52.97#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.174.01:23:52.97#ibcon#ireg 7 cls_cnt 0 2006.174.01:23:52.97#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.174.01:23:53.04#abcon#<5=/08 0.8 2.4 25.59 791003.4\r\n> 2006.174.01:23:53.06#abcon#{5=INTERFACE CLEAR} 2006.174.01:23:53.09#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.174.01:23:53.09#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.174.01:23:53.09#ibcon#enter wrdev, iclass 16, count 0 2006.174.01:23:53.09#ibcon#first serial, iclass 16, count 0 2006.174.01:23:53.09#ibcon#enter sib2, iclass 16, count 0 2006.174.01:23:53.09#ibcon#flushed, iclass 16, count 0 2006.174.01:23:53.09#ibcon#about to write, iclass 16, count 0 2006.174.01:23:53.09#ibcon#wrote, iclass 16, count 0 2006.174.01:23:53.09#ibcon#about to read 3, iclass 16, count 0 2006.174.01:23:53.11#ibcon#read 3, iclass 16, count 0 2006.174.01:23:53.11#ibcon#about to read 4, iclass 16, count 0 2006.174.01:23:53.11#ibcon#read 4, iclass 16, count 0 2006.174.01:23:53.11#ibcon#about to read 5, iclass 16, count 0 2006.174.01:23:53.11#ibcon#read 5, iclass 16, count 0 2006.174.01:23:53.11#ibcon#about to read 6, iclass 16, count 0 2006.174.01:23:53.11#ibcon#read 6, iclass 16, count 0 2006.174.01:23:53.11#ibcon#end of sib2, iclass 16, count 0 2006.174.01:23:53.11#ibcon#*mode == 0, iclass 16, count 0 2006.174.01:23:53.11#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.174.01:23:53.11#ibcon#[27=USB\r\n] 2006.174.01:23:53.11#ibcon#*before write, iclass 16, count 0 2006.174.01:23:53.11#ibcon#enter sib2, iclass 16, count 0 2006.174.01:23:53.11#ibcon#flushed, iclass 16, count 0 2006.174.01:23:53.11#ibcon#about to write, iclass 16, count 0 2006.174.01:23:53.11#ibcon#wrote, iclass 16, count 0 2006.174.01:23:53.11#ibcon#about to read 3, iclass 16, count 0 2006.174.01:23:53.12#abcon#[5=S1D000X0/0*\r\n] 2006.174.01:23:53.14#ibcon#read 3, iclass 16, count 0 2006.174.01:23:53.14#ibcon#about to read 4, iclass 16, count 0 2006.174.01:23:53.14#ibcon#read 4, iclass 16, count 0 2006.174.01:23:53.14#ibcon#about to read 5, iclass 16, count 0 2006.174.01:23:53.14#ibcon#read 5, iclass 16, count 0 2006.174.01:23:53.14#ibcon#about to read 6, iclass 16, count 0 2006.174.01:23:53.14#ibcon#read 6, iclass 16, count 0 2006.174.01:23:53.14#ibcon#end of sib2, iclass 16, count 0 2006.174.01:23:53.14#ibcon#*after write, iclass 16, count 0 2006.174.01:23:53.14#ibcon#*before return 0, iclass 16, count 0 2006.174.01:23:53.14#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.174.01:23:53.14#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.174.01:23:53.14#ibcon#about to clear, iclass 16 cls_cnt 0 2006.174.01:23:53.14#ibcon#cleared, iclass 16 cls_cnt 0 2006.174.01:23:53.14$vck44/vblo=2,634.99 2006.174.01:23:53.14#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.174.01:23:53.14#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.174.01:23:53.14#ibcon#ireg 17 cls_cnt 0 2006.174.01:23:53.14#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.174.01:23:53.14#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.174.01:23:53.14#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.174.01:23:53.14#ibcon#enter wrdev, iclass 22, count 0 2006.174.01:23:53.14#ibcon#first serial, iclass 22, count 0 2006.174.01:23:53.14#ibcon#enter sib2, iclass 22, count 0 2006.174.01:23:53.14#ibcon#flushed, iclass 22, count 0 2006.174.01:23:53.14#ibcon#about to write, iclass 22, count 0 2006.174.01:23:53.14#ibcon#wrote, iclass 22, count 0 2006.174.01:23:53.14#ibcon#about to read 3, iclass 22, count 0 2006.174.01:23:53.16#ibcon#read 3, iclass 22, count 0 2006.174.01:23:53.16#ibcon#about to read 4, iclass 22, count 0 2006.174.01:23:53.16#ibcon#read 4, iclass 22, count 0 2006.174.01:23:53.16#ibcon#about to read 5, iclass 22, count 0 2006.174.01:23:53.16#ibcon#read 5, iclass 22, count 0 2006.174.01:23:53.16#ibcon#about to read 6, iclass 22, count 0 2006.174.01:23:53.16#ibcon#read 6, iclass 22, count 0 2006.174.01:23:53.16#ibcon#end of sib2, iclass 22, count 0 2006.174.01:23:53.16#ibcon#*mode == 0, iclass 22, count 0 2006.174.01:23:53.16#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.174.01:23:53.16#ibcon#[28=FRQ=02,634.99\r\n] 2006.174.01:23:53.16#ibcon#*before write, iclass 22, count 0 2006.174.01:23:53.16#ibcon#enter sib2, iclass 22, count 0 2006.174.01:23:53.16#ibcon#flushed, iclass 22, count 0 2006.174.01:23:53.16#ibcon#about to write, iclass 22, count 0 2006.174.01:23:53.16#ibcon#wrote, iclass 22, count 0 2006.174.01:23:53.16#ibcon#about to read 3, iclass 22, count 0 2006.174.01:23:53.20#ibcon#read 3, iclass 22, count 0 2006.174.01:23:53.20#ibcon#about to read 4, iclass 22, count 0 2006.174.01:23:53.20#ibcon#read 4, iclass 22, count 0 2006.174.01:23:53.20#ibcon#about to read 5, iclass 22, count 0 2006.174.01:23:53.20#ibcon#read 5, iclass 22, count 0 2006.174.01:23:53.20#ibcon#about to read 6, iclass 22, count 0 2006.174.01:23:53.20#ibcon#read 6, iclass 22, count 0 2006.174.01:23:53.20#ibcon#end of sib2, iclass 22, count 0 2006.174.01:23:53.20#ibcon#*after write, iclass 22, count 0 2006.174.01:23:53.20#ibcon#*before return 0, iclass 22, count 0 2006.174.01:23:53.20#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.174.01:23:53.20#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.174.01:23:53.20#ibcon#about to clear, iclass 22 cls_cnt 0 2006.174.01:23:53.20#ibcon#cleared, iclass 22 cls_cnt 0 2006.174.01:23:53.20$vck44/vb=2,4 2006.174.01:23:53.20#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.174.01:23:53.20#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.174.01:23:53.20#ibcon#ireg 11 cls_cnt 2 2006.174.01:23:53.20#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.174.01:23:53.26#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.174.01:23:53.26#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.174.01:23:53.26#ibcon#enter wrdev, iclass 24, count 2 2006.174.01:23:53.26#ibcon#first serial, iclass 24, count 2 2006.174.01:23:53.26#ibcon#enter sib2, iclass 24, count 2 2006.174.01:23:53.26#ibcon#flushed, iclass 24, count 2 2006.174.01:23:53.26#ibcon#about to write, iclass 24, count 2 2006.174.01:23:53.26#ibcon#wrote, iclass 24, count 2 2006.174.01:23:53.26#ibcon#about to read 3, iclass 24, count 2 2006.174.01:23:53.28#ibcon#read 3, iclass 24, count 2 2006.174.01:23:53.28#ibcon#about to read 4, iclass 24, count 2 2006.174.01:23:53.28#ibcon#read 4, iclass 24, count 2 2006.174.01:23:53.28#ibcon#about to read 5, iclass 24, count 2 2006.174.01:23:53.28#ibcon#read 5, iclass 24, count 2 2006.174.01:23:53.28#ibcon#about to read 6, iclass 24, count 2 2006.174.01:23:53.28#ibcon#read 6, iclass 24, count 2 2006.174.01:23:53.28#ibcon#end of sib2, iclass 24, count 2 2006.174.01:23:53.28#ibcon#*mode == 0, iclass 24, count 2 2006.174.01:23:53.28#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.174.01:23:53.28#ibcon#[27=AT02-04\r\n] 2006.174.01:23:53.28#ibcon#*before write, iclass 24, count 2 2006.174.01:23:53.28#ibcon#enter sib2, iclass 24, count 2 2006.174.01:23:53.28#ibcon#flushed, iclass 24, count 2 2006.174.01:23:53.28#ibcon#about to write, iclass 24, count 2 2006.174.01:23:53.28#ibcon#wrote, iclass 24, count 2 2006.174.01:23:53.28#ibcon#about to read 3, iclass 24, count 2 2006.174.01:23:53.31#ibcon#read 3, iclass 24, count 2 2006.174.01:23:53.31#ibcon#about to read 4, iclass 24, count 2 2006.174.01:23:53.31#ibcon#read 4, iclass 24, count 2 2006.174.01:23:53.31#ibcon#about to read 5, iclass 24, count 2 2006.174.01:23:53.31#ibcon#read 5, iclass 24, count 2 2006.174.01:23:53.31#ibcon#about to read 6, iclass 24, count 2 2006.174.01:23:53.31#ibcon#read 6, iclass 24, count 2 2006.174.01:23:53.31#ibcon#end of sib2, iclass 24, count 2 2006.174.01:23:53.31#ibcon#*after write, iclass 24, count 2 2006.174.01:23:53.31#ibcon#*before return 0, iclass 24, count 2 2006.174.01:23:53.31#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.174.01:23:53.31#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.174.01:23:53.31#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.174.01:23:53.31#ibcon#ireg 7 cls_cnt 0 2006.174.01:23:53.31#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.174.01:23:53.43#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.174.01:23:53.43#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.174.01:23:53.43#ibcon#enter wrdev, iclass 24, count 0 2006.174.01:23:53.43#ibcon#first serial, iclass 24, count 0 2006.174.01:23:53.43#ibcon#enter sib2, iclass 24, count 0 2006.174.01:23:53.43#ibcon#flushed, iclass 24, count 0 2006.174.01:23:53.43#ibcon#about to write, iclass 24, count 0 2006.174.01:23:53.43#ibcon#wrote, iclass 24, count 0 2006.174.01:23:53.43#ibcon#about to read 3, iclass 24, count 0 2006.174.01:23:53.45#ibcon#read 3, iclass 24, count 0 2006.174.01:23:53.45#ibcon#about to read 4, iclass 24, count 0 2006.174.01:23:53.45#ibcon#read 4, iclass 24, count 0 2006.174.01:23:53.45#ibcon#about to read 5, iclass 24, count 0 2006.174.01:23:53.45#ibcon#read 5, iclass 24, count 0 2006.174.01:23:53.45#ibcon#about to read 6, iclass 24, count 0 2006.174.01:23:53.45#ibcon#read 6, iclass 24, count 0 2006.174.01:23:53.45#ibcon#end of sib2, iclass 24, count 0 2006.174.01:23:53.45#ibcon#*mode == 0, iclass 24, count 0 2006.174.01:23:53.45#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.174.01:23:53.45#ibcon#[27=USB\r\n] 2006.174.01:23:53.45#ibcon#*before write, iclass 24, count 0 2006.174.01:23:53.45#ibcon#enter sib2, iclass 24, count 0 2006.174.01:23:53.45#ibcon#flushed, iclass 24, count 0 2006.174.01:23:53.45#ibcon#about to write, iclass 24, count 0 2006.174.01:23:53.45#ibcon#wrote, iclass 24, count 0 2006.174.01:23:53.45#ibcon#about to read 3, iclass 24, count 0 2006.174.01:23:53.48#ibcon#read 3, iclass 24, count 0 2006.174.01:23:53.48#ibcon#about to read 4, iclass 24, count 0 2006.174.01:23:53.48#ibcon#read 4, iclass 24, count 0 2006.174.01:23:53.48#ibcon#about to read 5, iclass 24, count 0 2006.174.01:23:53.48#ibcon#read 5, iclass 24, count 0 2006.174.01:23:53.48#ibcon#about to read 6, iclass 24, count 0 2006.174.01:23:53.48#ibcon#read 6, iclass 24, count 0 2006.174.01:23:53.48#ibcon#end of sib2, iclass 24, count 0 2006.174.01:23:53.48#ibcon#*after write, iclass 24, count 0 2006.174.01:23:53.48#ibcon#*before return 0, iclass 24, count 0 2006.174.01:23:53.48#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.174.01:23:53.48#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.174.01:23:53.48#ibcon#about to clear, iclass 24 cls_cnt 0 2006.174.01:23:53.48#ibcon#cleared, iclass 24 cls_cnt 0 2006.174.01:23:53.48$vck44/vblo=3,649.99 2006.174.01:23:53.48#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.174.01:23:53.48#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.174.01:23:53.48#ibcon#ireg 17 cls_cnt 0 2006.174.01:23:53.48#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.174.01:23:53.48#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.174.01:23:53.48#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.174.01:23:53.48#ibcon#enter wrdev, iclass 26, count 0 2006.174.01:23:53.48#ibcon#first serial, iclass 26, count 0 2006.174.01:23:53.48#ibcon#enter sib2, iclass 26, count 0 2006.174.01:23:53.48#ibcon#flushed, iclass 26, count 0 2006.174.01:23:53.48#ibcon#about to write, iclass 26, count 0 2006.174.01:23:53.48#ibcon#wrote, iclass 26, count 0 2006.174.01:23:53.48#ibcon#about to read 3, iclass 26, count 0 2006.174.01:23:53.50#ibcon#read 3, iclass 26, count 0 2006.174.01:23:53.50#ibcon#about to read 4, iclass 26, count 0 2006.174.01:23:53.50#ibcon#read 4, iclass 26, count 0 2006.174.01:23:53.50#ibcon#about to read 5, iclass 26, count 0 2006.174.01:23:53.50#ibcon#read 5, iclass 26, count 0 2006.174.01:23:53.50#ibcon#about to read 6, iclass 26, count 0 2006.174.01:23:53.50#ibcon#read 6, iclass 26, count 0 2006.174.01:23:53.50#ibcon#end of sib2, iclass 26, count 0 2006.174.01:23:53.50#ibcon#*mode == 0, iclass 26, count 0 2006.174.01:23:53.50#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.174.01:23:53.50#ibcon#[28=FRQ=03,649.99\r\n] 2006.174.01:23:53.50#ibcon#*before write, iclass 26, count 0 2006.174.01:23:53.50#ibcon#enter sib2, iclass 26, count 0 2006.174.01:23:53.50#ibcon#flushed, iclass 26, count 0 2006.174.01:23:53.50#ibcon#about to write, iclass 26, count 0 2006.174.01:23:53.50#ibcon#wrote, iclass 26, count 0 2006.174.01:23:53.50#ibcon#about to read 3, iclass 26, count 0 2006.174.01:23:53.54#ibcon#read 3, iclass 26, count 0 2006.174.01:23:53.54#ibcon#about to read 4, iclass 26, count 0 2006.174.01:23:53.54#ibcon#read 4, iclass 26, count 0 2006.174.01:23:53.54#ibcon#about to read 5, iclass 26, count 0 2006.174.01:23:53.54#ibcon#read 5, iclass 26, count 0 2006.174.01:23:53.54#ibcon#about to read 6, iclass 26, count 0 2006.174.01:23:53.54#ibcon#read 6, iclass 26, count 0 2006.174.01:23:53.54#ibcon#end of sib2, iclass 26, count 0 2006.174.01:23:53.54#ibcon#*after write, iclass 26, count 0 2006.174.01:23:53.54#ibcon#*before return 0, iclass 26, count 0 2006.174.01:23:53.54#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.174.01:23:53.54#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.174.01:23:53.54#ibcon#about to clear, iclass 26 cls_cnt 0 2006.174.01:23:53.54#ibcon#cleared, iclass 26 cls_cnt 0 2006.174.01:23:53.54$vck44/vb=3,4 2006.174.01:23:53.54#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.174.01:23:53.54#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.174.01:23:53.54#ibcon#ireg 11 cls_cnt 2 2006.174.01:23:53.54#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.174.01:23:53.60#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.174.01:23:53.60#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.174.01:23:53.60#ibcon#enter wrdev, iclass 28, count 2 2006.174.01:23:53.60#ibcon#first serial, iclass 28, count 2 2006.174.01:23:53.60#ibcon#enter sib2, iclass 28, count 2 2006.174.01:23:53.60#ibcon#flushed, iclass 28, count 2 2006.174.01:23:53.60#ibcon#about to write, iclass 28, count 2 2006.174.01:23:53.60#ibcon#wrote, iclass 28, count 2 2006.174.01:23:53.60#ibcon#about to read 3, iclass 28, count 2 2006.174.01:23:53.62#ibcon#read 3, iclass 28, count 2 2006.174.01:23:53.62#ibcon#about to read 4, iclass 28, count 2 2006.174.01:23:53.62#ibcon#read 4, iclass 28, count 2 2006.174.01:23:53.62#ibcon#about to read 5, iclass 28, count 2 2006.174.01:23:53.62#ibcon#read 5, iclass 28, count 2 2006.174.01:23:53.62#ibcon#about to read 6, iclass 28, count 2 2006.174.01:23:53.62#ibcon#read 6, iclass 28, count 2 2006.174.01:23:53.62#ibcon#end of sib2, iclass 28, count 2 2006.174.01:23:53.62#ibcon#*mode == 0, iclass 28, count 2 2006.174.01:23:53.62#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.174.01:23:53.62#ibcon#[27=AT03-04\r\n] 2006.174.01:23:53.62#ibcon#*before write, iclass 28, count 2 2006.174.01:23:53.62#ibcon#enter sib2, iclass 28, count 2 2006.174.01:23:53.62#ibcon#flushed, iclass 28, count 2 2006.174.01:23:53.62#ibcon#about to write, iclass 28, count 2 2006.174.01:23:53.62#ibcon#wrote, iclass 28, count 2 2006.174.01:23:53.62#ibcon#about to read 3, iclass 28, count 2 2006.174.01:23:53.65#ibcon#read 3, iclass 28, count 2 2006.174.01:23:53.65#ibcon#about to read 4, iclass 28, count 2 2006.174.01:23:53.65#ibcon#read 4, iclass 28, count 2 2006.174.01:23:53.65#ibcon#about to read 5, iclass 28, count 2 2006.174.01:23:53.65#ibcon#read 5, iclass 28, count 2 2006.174.01:23:53.65#ibcon#about to read 6, iclass 28, count 2 2006.174.01:23:53.65#ibcon#read 6, iclass 28, count 2 2006.174.01:23:53.65#ibcon#end of sib2, iclass 28, count 2 2006.174.01:23:53.65#ibcon#*after write, iclass 28, count 2 2006.174.01:23:53.65#ibcon#*before return 0, iclass 28, count 2 2006.174.01:23:53.65#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.174.01:23:53.65#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.174.01:23:53.65#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.174.01:23:53.65#ibcon#ireg 7 cls_cnt 0 2006.174.01:23:53.65#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.174.01:23:53.77#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.174.01:23:53.77#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.174.01:23:53.77#ibcon#enter wrdev, iclass 28, count 0 2006.174.01:23:53.77#ibcon#first serial, iclass 28, count 0 2006.174.01:23:53.77#ibcon#enter sib2, iclass 28, count 0 2006.174.01:23:53.77#ibcon#flushed, iclass 28, count 0 2006.174.01:23:53.77#ibcon#about to write, iclass 28, count 0 2006.174.01:23:53.77#ibcon#wrote, iclass 28, count 0 2006.174.01:23:53.77#ibcon#about to read 3, iclass 28, count 0 2006.174.01:23:53.79#ibcon#read 3, iclass 28, count 0 2006.174.01:23:53.79#ibcon#about to read 4, iclass 28, count 0 2006.174.01:23:53.79#ibcon#read 4, iclass 28, count 0 2006.174.01:23:53.79#ibcon#about to read 5, iclass 28, count 0 2006.174.01:23:53.79#ibcon#read 5, iclass 28, count 0 2006.174.01:23:53.79#ibcon#about to read 6, iclass 28, count 0 2006.174.01:23:53.79#ibcon#read 6, iclass 28, count 0 2006.174.01:23:53.79#ibcon#end of sib2, iclass 28, count 0 2006.174.01:23:53.79#ibcon#*mode == 0, iclass 28, count 0 2006.174.01:23:53.79#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.174.01:23:53.79#ibcon#[27=USB\r\n] 2006.174.01:23:53.79#ibcon#*before write, iclass 28, count 0 2006.174.01:23:53.79#ibcon#enter sib2, iclass 28, count 0 2006.174.01:23:53.79#ibcon#flushed, iclass 28, count 0 2006.174.01:23:53.79#ibcon#about to write, iclass 28, count 0 2006.174.01:23:53.79#ibcon#wrote, iclass 28, count 0 2006.174.01:23:53.79#ibcon#about to read 3, iclass 28, count 0 2006.174.01:23:53.82#ibcon#read 3, iclass 28, count 0 2006.174.01:23:53.82#ibcon#about to read 4, iclass 28, count 0 2006.174.01:23:53.82#ibcon#read 4, iclass 28, count 0 2006.174.01:23:53.82#ibcon#about to read 5, iclass 28, count 0 2006.174.01:23:53.82#ibcon#read 5, iclass 28, count 0 2006.174.01:23:53.82#ibcon#about to read 6, iclass 28, count 0 2006.174.01:23:53.82#ibcon#read 6, iclass 28, count 0 2006.174.01:23:53.82#ibcon#end of sib2, iclass 28, count 0 2006.174.01:23:53.82#ibcon#*after write, iclass 28, count 0 2006.174.01:23:53.82#ibcon#*before return 0, iclass 28, count 0 2006.174.01:23:53.82#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.174.01:23:53.82#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.174.01:23:53.82#ibcon#about to clear, iclass 28 cls_cnt 0 2006.174.01:23:53.82#ibcon#cleared, iclass 28 cls_cnt 0 2006.174.01:23:53.82$vck44/vblo=4,679.99 2006.174.01:23:53.82#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.174.01:23:53.82#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.174.01:23:53.82#ibcon#ireg 17 cls_cnt 0 2006.174.01:23:53.82#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.174.01:23:53.82#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.174.01:23:53.82#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.174.01:23:53.82#ibcon#enter wrdev, iclass 30, count 0 2006.174.01:23:53.82#ibcon#first serial, iclass 30, count 0 2006.174.01:23:53.82#ibcon#enter sib2, iclass 30, count 0 2006.174.01:23:53.82#ibcon#flushed, iclass 30, count 0 2006.174.01:23:53.82#ibcon#about to write, iclass 30, count 0 2006.174.01:23:53.82#ibcon#wrote, iclass 30, count 0 2006.174.01:23:53.82#ibcon#about to read 3, iclass 30, count 0 2006.174.01:23:53.84#ibcon#read 3, iclass 30, count 0 2006.174.01:23:53.84#ibcon#about to read 4, iclass 30, count 0 2006.174.01:23:53.84#ibcon#read 4, iclass 30, count 0 2006.174.01:23:53.84#ibcon#about to read 5, iclass 30, count 0 2006.174.01:23:53.84#ibcon#read 5, iclass 30, count 0 2006.174.01:23:53.84#ibcon#about to read 6, iclass 30, count 0 2006.174.01:23:53.84#ibcon#read 6, iclass 30, count 0 2006.174.01:23:53.84#ibcon#end of sib2, iclass 30, count 0 2006.174.01:23:53.84#ibcon#*mode == 0, iclass 30, count 0 2006.174.01:23:53.84#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.174.01:23:53.84#ibcon#[28=FRQ=04,679.99\r\n] 2006.174.01:23:53.84#ibcon#*before write, iclass 30, count 0 2006.174.01:23:53.84#ibcon#enter sib2, iclass 30, count 0 2006.174.01:23:53.84#ibcon#flushed, iclass 30, count 0 2006.174.01:23:53.84#ibcon#about to write, iclass 30, count 0 2006.174.01:23:53.84#ibcon#wrote, iclass 30, count 0 2006.174.01:23:53.84#ibcon#about to read 3, iclass 30, count 0 2006.174.01:23:53.88#ibcon#read 3, iclass 30, count 0 2006.174.01:23:53.88#ibcon#about to read 4, iclass 30, count 0 2006.174.01:23:53.88#ibcon#read 4, iclass 30, count 0 2006.174.01:23:53.88#ibcon#about to read 5, iclass 30, count 0 2006.174.01:23:53.88#ibcon#read 5, iclass 30, count 0 2006.174.01:23:53.88#ibcon#about to read 6, iclass 30, count 0 2006.174.01:23:53.88#ibcon#read 6, iclass 30, count 0 2006.174.01:23:53.88#ibcon#end of sib2, iclass 30, count 0 2006.174.01:23:53.88#ibcon#*after write, iclass 30, count 0 2006.174.01:23:53.88#ibcon#*before return 0, iclass 30, count 0 2006.174.01:23:53.88#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.174.01:23:53.88#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.174.01:23:53.88#ibcon#about to clear, iclass 30 cls_cnt 0 2006.174.01:23:53.88#ibcon#cleared, iclass 30 cls_cnt 0 2006.174.01:23:53.88$vck44/vb=4,4 2006.174.01:23:53.88#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.174.01:23:53.88#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.174.01:23:53.88#ibcon#ireg 11 cls_cnt 2 2006.174.01:23:53.88#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.174.01:23:53.94#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.174.01:23:53.94#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.174.01:23:53.94#ibcon#enter wrdev, iclass 32, count 2 2006.174.01:23:53.94#ibcon#first serial, iclass 32, count 2 2006.174.01:23:53.94#ibcon#enter sib2, iclass 32, count 2 2006.174.01:23:53.94#ibcon#flushed, iclass 32, count 2 2006.174.01:23:53.94#ibcon#about to write, iclass 32, count 2 2006.174.01:23:53.94#ibcon#wrote, iclass 32, count 2 2006.174.01:23:53.94#ibcon#about to read 3, iclass 32, count 2 2006.174.01:23:53.96#ibcon#read 3, iclass 32, count 2 2006.174.01:23:53.96#ibcon#about to read 4, iclass 32, count 2 2006.174.01:23:53.96#ibcon#read 4, iclass 32, count 2 2006.174.01:23:53.96#ibcon#about to read 5, iclass 32, count 2 2006.174.01:23:53.96#ibcon#read 5, iclass 32, count 2 2006.174.01:23:53.96#ibcon#about to read 6, iclass 32, count 2 2006.174.01:23:53.96#ibcon#read 6, iclass 32, count 2 2006.174.01:23:53.96#ibcon#end of sib2, iclass 32, count 2 2006.174.01:23:53.96#ibcon#*mode == 0, iclass 32, count 2 2006.174.01:23:53.96#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.174.01:23:53.96#ibcon#[27=AT04-04\r\n] 2006.174.01:23:53.96#ibcon#*before write, iclass 32, count 2 2006.174.01:23:53.96#ibcon#enter sib2, iclass 32, count 2 2006.174.01:23:53.96#ibcon#flushed, iclass 32, count 2 2006.174.01:23:53.96#ibcon#about to write, iclass 32, count 2 2006.174.01:23:53.96#ibcon#wrote, iclass 32, count 2 2006.174.01:23:53.96#ibcon#about to read 3, iclass 32, count 2 2006.174.01:23:53.99#ibcon#read 3, iclass 32, count 2 2006.174.01:23:53.99#ibcon#about to read 4, iclass 32, count 2 2006.174.01:23:53.99#ibcon#read 4, iclass 32, count 2 2006.174.01:23:53.99#ibcon#about to read 5, iclass 32, count 2 2006.174.01:23:53.99#ibcon#read 5, iclass 32, count 2 2006.174.01:23:53.99#ibcon#about to read 6, iclass 32, count 2 2006.174.01:23:53.99#ibcon#read 6, iclass 32, count 2 2006.174.01:23:53.99#ibcon#end of sib2, iclass 32, count 2 2006.174.01:23:53.99#ibcon#*after write, iclass 32, count 2 2006.174.01:23:53.99#ibcon#*before return 0, iclass 32, count 2 2006.174.01:23:53.99#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.174.01:23:53.99#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.174.01:23:53.99#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.174.01:23:53.99#ibcon#ireg 7 cls_cnt 0 2006.174.01:23:53.99#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.174.01:23:54.11#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.174.01:23:54.11#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.174.01:23:54.11#ibcon#enter wrdev, iclass 32, count 0 2006.174.01:23:54.11#ibcon#first serial, iclass 32, count 0 2006.174.01:23:54.11#ibcon#enter sib2, iclass 32, count 0 2006.174.01:23:54.11#ibcon#flushed, iclass 32, count 0 2006.174.01:23:54.11#ibcon#about to write, iclass 32, count 0 2006.174.01:23:54.11#ibcon#wrote, iclass 32, count 0 2006.174.01:23:54.11#ibcon#about to read 3, iclass 32, count 0 2006.174.01:23:54.13#ibcon#read 3, iclass 32, count 0 2006.174.01:23:54.13#ibcon#about to read 4, iclass 32, count 0 2006.174.01:23:54.13#ibcon#read 4, iclass 32, count 0 2006.174.01:23:54.13#ibcon#about to read 5, iclass 32, count 0 2006.174.01:23:54.13#ibcon#read 5, iclass 32, count 0 2006.174.01:23:54.13#ibcon#about to read 6, iclass 32, count 0 2006.174.01:23:54.13#ibcon#read 6, iclass 32, count 0 2006.174.01:23:54.13#ibcon#end of sib2, iclass 32, count 0 2006.174.01:23:54.13#ibcon#*mode == 0, iclass 32, count 0 2006.174.01:23:54.13#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.174.01:23:54.13#ibcon#[27=USB\r\n] 2006.174.01:23:54.13#ibcon#*before write, iclass 32, count 0 2006.174.01:23:54.13#ibcon#enter sib2, iclass 32, count 0 2006.174.01:23:54.13#ibcon#flushed, iclass 32, count 0 2006.174.01:23:54.13#ibcon#about to write, iclass 32, count 0 2006.174.01:23:54.13#ibcon#wrote, iclass 32, count 0 2006.174.01:23:54.13#ibcon#about to read 3, iclass 32, count 0 2006.174.01:23:54.16#ibcon#read 3, iclass 32, count 0 2006.174.01:23:54.16#ibcon#about to read 4, iclass 32, count 0 2006.174.01:23:54.16#ibcon#read 4, iclass 32, count 0 2006.174.01:23:54.16#ibcon#about to read 5, iclass 32, count 0 2006.174.01:23:54.16#ibcon#read 5, iclass 32, count 0 2006.174.01:23:54.16#ibcon#about to read 6, iclass 32, count 0 2006.174.01:23:54.16#ibcon#read 6, iclass 32, count 0 2006.174.01:23:54.16#ibcon#end of sib2, iclass 32, count 0 2006.174.01:23:54.16#ibcon#*after write, iclass 32, count 0 2006.174.01:23:54.16#ibcon#*before return 0, iclass 32, count 0 2006.174.01:23:54.16#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.174.01:23:54.16#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.174.01:23:54.16#ibcon#about to clear, iclass 32 cls_cnt 0 2006.174.01:23:54.16#ibcon#cleared, iclass 32 cls_cnt 0 2006.174.01:23:54.16$vck44/vblo=5,709.99 2006.174.01:23:54.16#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.174.01:23:54.16#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.174.01:23:54.16#ibcon#ireg 17 cls_cnt 0 2006.174.01:23:54.16#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.174.01:23:54.16#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.174.01:23:54.16#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.174.01:23:54.16#ibcon#enter wrdev, iclass 34, count 0 2006.174.01:23:54.16#ibcon#first serial, iclass 34, count 0 2006.174.01:23:54.16#ibcon#enter sib2, iclass 34, count 0 2006.174.01:23:54.16#ibcon#flushed, iclass 34, count 0 2006.174.01:23:54.16#ibcon#about to write, iclass 34, count 0 2006.174.01:23:54.16#ibcon#wrote, iclass 34, count 0 2006.174.01:23:54.16#ibcon#about to read 3, iclass 34, count 0 2006.174.01:23:54.18#ibcon#read 3, iclass 34, count 0 2006.174.01:23:54.18#ibcon#about to read 4, iclass 34, count 0 2006.174.01:23:54.18#ibcon#read 4, iclass 34, count 0 2006.174.01:23:54.18#ibcon#about to read 5, iclass 34, count 0 2006.174.01:23:54.18#ibcon#read 5, iclass 34, count 0 2006.174.01:23:54.18#ibcon#about to read 6, iclass 34, count 0 2006.174.01:23:54.18#ibcon#read 6, iclass 34, count 0 2006.174.01:23:54.18#ibcon#end of sib2, iclass 34, count 0 2006.174.01:23:54.18#ibcon#*mode == 0, iclass 34, count 0 2006.174.01:23:54.18#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.174.01:23:54.18#ibcon#[28=FRQ=05,709.99\r\n] 2006.174.01:23:54.18#ibcon#*before write, iclass 34, count 0 2006.174.01:23:54.18#ibcon#enter sib2, iclass 34, count 0 2006.174.01:23:54.18#ibcon#flushed, iclass 34, count 0 2006.174.01:23:54.18#ibcon#about to write, iclass 34, count 0 2006.174.01:23:54.18#ibcon#wrote, iclass 34, count 0 2006.174.01:23:54.18#ibcon#about to read 3, iclass 34, count 0 2006.174.01:23:54.22#ibcon#read 3, iclass 34, count 0 2006.174.01:23:54.22#ibcon#about to read 4, iclass 34, count 0 2006.174.01:23:54.22#ibcon#read 4, iclass 34, count 0 2006.174.01:23:54.22#ibcon#about to read 5, iclass 34, count 0 2006.174.01:23:54.22#ibcon#read 5, iclass 34, count 0 2006.174.01:23:54.22#ibcon#about to read 6, iclass 34, count 0 2006.174.01:23:54.22#ibcon#read 6, iclass 34, count 0 2006.174.01:23:54.22#ibcon#end of sib2, iclass 34, count 0 2006.174.01:23:54.22#ibcon#*after write, iclass 34, count 0 2006.174.01:23:54.22#ibcon#*before return 0, iclass 34, count 0 2006.174.01:23:54.22#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.174.01:23:54.22#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.174.01:23:54.22#ibcon#about to clear, iclass 34 cls_cnt 0 2006.174.01:23:54.22#ibcon#cleared, iclass 34 cls_cnt 0 2006.174.01:23:54.22$vck44/vb=5,4 2006.174.01:23:54.22#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.174.01:23:54.22#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.174.01:23:54.22#ibcon#ireg 11 cls_cnt 2 2006.174.01:23:54.22#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.174.01:23:54.28#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.174.01:23:54.28#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.174.01:23:54.28#ibcon#enter wrdev, iclass 36, count 2 2006.174.01:23:54.28#ibcon#first serial, iclass 36, count 2 2006.174.01:23:54.28#ibcon#enter sib2, iclass 36, count 2 2006.174.01:23:54.28#ibcon#flushed, iclass 36, count 2 2006.174.01:23:54.28#ibcon#about to write, iclass 36, count 2 2006.174.01:23:54.28#ibcon#wrote, iclass 36, count 2 2006.174.01:23:54.28#ibcon#about to read 3, iclass 36, count 2 2006.174.01:23:54.30#ibcon#read 3, iclass 36, count 2 2006.174.01:23:54.30#ibcon#about to read 4, iclass 36, count 2 2006.174.01:23:54.30#ibcon#read 4, iclass 36, count 2 2006.174.01:23:54.30#ibcon#about to read 5, iclass 36, count 2 2006.174.01:23:54.30#ibcon#read 5, iclass 36, count 2 2006.174.01:23:54.30#ibcon#about to read 6, iclass 36, count 2 2006.174.01:23:54.30#ibcon#read 6, iclass 36, count 2 2006.174.01:23:54.30#ibcon#end of sib2, iclass 36, count 2 2006.174.01:23:54.30#ibcon#*mode == 0, iclass 36, count 2 2006.174.01:23:54.30#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.174.01:23:54.30#ibcon#[27=AT05-04\r\n] 2006.174.01:23:54.30#ibcon#*before write, iclass 36, count 2 2006.174.01:23:54.30#ibcon#enter sib2, iclass 36, count 2 2006.174.01:23:54.30#ibcon#flushed, iclass 36, count 2 2006.174.01:23:54.30#ibcon#about to write, iclass 36, count 2 2006.174.01:23:54.30#ibcon#wrote, iclass 36, count 2 2006.174.01:23:54.30#ibcon#about to read 3, iclass 36, count 2 2006.174.01:23:54.33#ibcon#read 3, iclass 36, count 2 2006.174.01:23:54.33#ibcon#about to read 4, iclass 36, count 2 2006.174.01:23:54.33#ibcon#read 4, iclass 36, count 2 2006.174.01:23:54.33#ibcon#about to read 5, iclass 36, count 2 2006.174.01:23:54.33#ibcon#read 5, iclass 36, count 2 2006.174.01:23:54.33#ibcon#about to read 6, iclass 36, count 2 2006.174.01:23:54.33#ibcon#read 6, iclass 36, count 2 2006.174.01:23:54.33#ibcon#end of sib2, iclass 36, count 2 2006.174.01:23:54.33#ibcon#*after write, iclass 36, count 2 2006.174.01:23:54.33#ibcon#*before return 0, iclass 36, count 2 2006.174.01:23:54.33#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.174.01:23:54.33#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.174.01:23:54.33#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.174.01:23:54.33#ibcon#ireg 7 cls_cnt 0 2006.174.01:23:54.33#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.174.01:23:54.45#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.174.01:23:54.45#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.174.01:23:54.45#ibcon#enter wrdev, iclass 36, count 0 2006.174.01:23:54.45#ibcon#first serial, iclass 36, count 0 2006.174.01:23:54.45#ibcon#enter sib2, iclass 36, count 0 2006.174.01:23:54.45#ibcon#flushed, iclass 36, count 0 2006.174.01:23:54.45#ibcon#about to write, iclass 36, count 0 2006.174.01:23:54.45#ibcon#wrote, iclass 36, count 0 2006.174.01:23:54.45#ibcon#about to read 3, iclass 36, count 0 2006.174.01:23:54.47#ibcon#read 3, iclass 36, count 0 2006.174.01:23:54.47#ibcon#about to read 4, iclass 36, count 0 2006.174.01:23:54.47#ibcon#read 4, iclass 36, count 0 2006.174.01:23:54.47#ibcon#about to read 5, iclass 36, count 0 2006.174.01:23:54.47#ibcon#read 5, iclass 36, count 0 2006.174.01:23:54.47#ibcon#about to read 6, iclass 36, count 0 2006.174.01:23:54.47#ibcon#read 6, iclass 36, count 0 2006.174.01:23:54.47#ibcon#end of sib2, iclass 36, count 0 2006.174.01:23:54.47#ibcon#*mode == 0, iclass 36, count 0 2006.174.01:23:54.47#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.174.01:23:54.47#ibcon#[27=USB\r\n] 2006.174.01:23:54.47#ibcon#*before write, iclass 36, count 0 2006.174.01:23:54.47#ibcon#enter sib2, iclass 36, count 0 2006.174.01:23:54.47#ibcon#flushed, iclass 36, count 0 2006.174.01:23:54.47#ibcon#about to write, iclass 36, count 0 2006.174.01:23:54.47#ibcon#wrote, iclass 36, count 0 2006.174.01:23:54.47#ibcon#about to read 3, iclass 36, count 0 2006.174.01:23:54.50#ibcon#read 3, iclass 36, count 0 2006.174.01:23:54.50#ibcon#about to read 4, iclass 36, count 0 2006.174.01:23:54.50#ibcon#read 4, iclass 36, count 0 2006.174.01:23:54.50#ibcon#about to read 5, iclass 36, count 0 2006.174.01:23:54.50#ibcon#read 5, iclass 36, count 0 2006.174.01:23:54.50#ibcon#about to read 6, iclass 36, count 0 2006.174.01:23:54.50#ibcon#read 6, iclass 36, count 0 2006.174.01:23:54.50#ibcon#end of sib2, iclass 36, count 0 2006.174.01:23:54.50#ibcon#*after write, iclass 36, count 0 2006.174.01:23:54.50#ibcon#*before return 0, iclass 36, count 0 2006.174.01:23:54.50#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.174.01:23:54.50#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.174.01:23:54.50#ibcon#about to clear, iclass 36 cls_cnt 0 2006.174.01:23:54.50#ibcon#cleared, iclass 36 cls_cnt 0 2006.174.01:23:54.50$vck44/vblo=6,719.99 2006.174.01:23:54.50#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.174.01:23:54.50#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.174.01:23:54.50#ibcon#ireg 17 cls_cnt 0 2006.174.01:23:54.50#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.174.01:23:54.50#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.174.01:23:54.50#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.174.01:23:54.50#ibcon#enter wrdev, iclass 38, count 0 2006.174.01:23:54.50#ibcon#first serial, iclass 38, count 0 2006.174.01:23:54.50#ibcon#enter sib2, iclass 38, count 0 2006.174.01:23:54.50#ibcon#flushed, iclass 38, count 0 2006.174.01:23:54.50#ibcon#about to write, iclass 38, count 0 2006.174.01:23:54.50#ibcon#wrote, iclass 38, count 0 2006.174.01:23:54.50#ibcon#about to read 3, iclass 38, count 0 2006.174.01:23:54.52#ibcon#read 3, iclass 38, count 0 2006.174.01:23:54.52#ibcon#about to read 4, iclass 38, count 0 2006.174.01:23:54.52#ibcon#read 4, iclass 38, count 0 2006.174.01:23:54.52#ibcon#about to read 5, iclass 38, count 0 2006.174.01:23:54.52#ibcon#read 5, iclass 38, count 0 2006.174.01:23:54.52#ibcon#about to read 6, iclass 38, count 0 2006.174.01:23:54.52#ibcon#read 6, iclass 38, count 0 2006.174.01:23:54.52#ibcon#end of sib2, iclass 38, count 0 2006.174.01:23:54.52#ibcon#*mode == 0, iclass 38, count 0 2006.174.01:23:54.52#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.174.01:23:54.52#ibcon#[28=FRQ=06,719.99\r\n] 2006.174.01:23:54.52#ibcon#*before write, iclass 38, count 0 2006.174.01:23:54.52#ibcon#enter sib2, iclass 38, count 0 2006.174.01:23:54.52#ibcon#flushed, iclass 38, count 0 2006.174.01:23:54.52#ibcon#about to write, iclass 38, count 0 2006.174.01:23:54.52#ibcon#wrote, iclass 38, count 0 2006.174.01:23:54.52#ibcon#about to read 3, iclass 38, count 0 2006.174.01:23:54.56#ibcon#read 3, iclass 38, count 0 2006.174.01:23:54.56#ibcon#about to read 4, iclass 38, count 0 2006.174.01:23:54.56#ibcon#read 4, iclass 38, count 0 2006.174.01:23:54.56#ibcon#about to read 5, iclass 38, count 0 2006.174.01:23:54.56#ibcon#read 5, iclass 38, count 0 2006.174.01:23:54.56#ibcon#about to read 6, iclass 38, count 0 2006.174.01:23:54.56#ibcon#read 6, iclass 38, count 0 2006.174.01:23:54.56#ibcon#end of sib2, iclass 38, count 0 2006.174.01:23:54.56#ibcon#*after write, iclass 38, count 0 2006.174.01:23:54.56#ibcon#*before return 0, iclass 38, count 0 2006.174.01:23:54.56#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.174.01:23:54.56#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.174.01:23:54.56#ibcon#about to clear, iclass 38 cls_cnt 0 2006.174.01:23:54.56#ibcon#cleared, iclass 38 cls_cnt 0 2006.174.01:23:54.56$vck44/vb=6,4 2006.174.01:23:54.56#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.174.01:23:54.56#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.174.01:23:54.56#ibcon#ireg 11 cls_cnt 2 2006.174.01:23:54.56#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.174.01:23:54.62#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.174.01:23:54.62#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.174.01:23:54.62#ibcon#enter wrdev, iclass 40, count 2 2006.174.01:23:54.62#ibcon#first serial, iclass 40, count 2 2006.174.01:23:54.62#ibcon#enter sib2, iclass 40, count 2 2006.174.01:23:54.62#ibcon#flushed, iclass 40, count 2 2006.174.01:23:54.62#ibcon#about to write, iclass 40, count 2 2006.174.01:23:54.62#ibcon#wrote, iclass 40, count 2 2006.174.01:23:54.62#ibcon#about to read 3, iclass 40, count 2 2006.174.01:23:54.64#ibcon#read 3, iclass 40, count 2 2006.174.01:23:54.64#ibcon#about to read 4, iclass 40, count 2 2006.174.01:23:54.64#ibcon#read 4, iclass 40, count 2 2006.174.01:23:54.64#ibcon#about to read 5, iclass 40, count 2 2006.174.01:23:54.64#ibcon#read 5, iclass 40, count 2 2006.174.01:23:54.64#ibcon#about to read 6, iclass 40, count 2 2006.174.01:23:54.64#ibcon#read 6, iclass 40, count 2 2006.174.01:23:54.64#ibcon#end of sib2, iclass 40, count 2 2006.174.01:23:54.64#ibcon#*mode == 0, iclass 40, count 2 2006.174.01:23:54.64#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.174.01:23:54.64#ibcon#[27=AT06-04\r\n] 2006.174.01:23:54.64#ibcon#*before write, iclass 40, count 2 2006.174.01:23:54.64#ibcon#enter sib2, iclass 40, count 2 2006.174.01:23:54.64#ibcon#flushed, iclass 40, count 2 2006.174.01:23:54.64#ibcon#about to write, iclass 40, count 2 2006.174.01:23:54.64#ibcon#wrote, iclass 40, count 2 2006.174.01:23:54.64#ibcon#about to read 3, iclass 40, count 2 2006.174.01:23:54.67#ibcon#read 3, iclass 40, count 2 2006.174.01:23:54.67#ibcon#about to read 4, iclass 40, count 2 2006.174.01:23:54.67#ibcon#read 4, iclass 40, count 2 2006.174.01:23:54.67#ibcon#about to read 5, iclass 40, count 2 2006.174.01:23:54.67#ibcon#read 5, iclass 40, count 2 2006.174.01:23:54.67#ibcon#about to read 6, iclass 40, count 2 2006.174.01:23:54.67#ibcon#read 6, iclass 40, count 2 2006.174.01:23:54.67#ibcon#end of sib2, iclass 40, count 2 2006.174.01:23:54.67#ibcon#*after write, iclass 40, count 2 2006.174.01:23:54.67#ibcon#*before return 0, iclass 40, count 2 2006.174.01:23:54.67#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.174.01:23:54.67#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.174.01:23:54.67#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.174.01:23:54.67#ibcon#ireg 7 cls_cnt 0 2006.174.01:23:54.67#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.174.01:23:54.79#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.174.01:23:54.79#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.174.01:23:54.79#ibcon#enter wrdev, iclass 40, count 0 2006.174.01:23:54.79#ibcon#first serial, iclass 40, count 0 2006.174.01:23:54.79#ibcon#enter sib2, iclass 40, count 0 2006.174.01:23:54.79#ibcon#flushed, iclass 40, count 0 2006.174.01:23:54.79#ibcon#about to write, iclass 40, count 0 2006.174.01:23:54.79#ibcon#wrote, iclass 40, count 0 2006.174.01:23:54.79#ibcon#about to read 3, iclass 40, count 0 2006.174.01:23:54.81#ibcon#read 3, iclass 40, count 0 2006.174.01:23:54.81#ibcon#about to read 4, iclass 40, count 0 2006.174.01:23:54.81#ibcon#read 4, iclass 40, count 0 2006.174.01:23:54.81#ibcon#about to read 5, iclass 40, count 0 2006.174.01:23:54.81#ibcon#read 5, iclass 40, count 0 2006.174.01:23:54.81#ibcon#about to read 6, iclass 40, count 0 2006.174.01:23:54.81#ibcon#read 6, iclass 40, count 0 2006.174.01:23:54.81#ibcon#end of sib2, iclass 40, count 0 2006.174.01:23:54.81#ibcon#*mode == 0, iclass 40, count 0 2006.174.01:23:54.81#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.174.01:23:54.81#ibcon#[27=USB\r\n] 2006.174.01:23:54.81#ibcon#*before write, iclass 40, count 0 2006.174.01:23:54.81#ibcon#enter sib2, iclass 40, count 0 2006.174.01:23:54.81#ibcon#flushed, iclass 40, count 0 2006.174.01:23:54.81#ibcon#about to write, iclass 40, count 0 2006.174.01:23:54.81#ibcon#wrote, iclass 40, count 0 2006.174.01:23:54.81#ibcon#about to read 3, iclass 40, count 0 2006.174.01:23:54.84#ibcon#read 3, iclass 40, count 0 2006.174.01:23:54.84#ibcon#about to read 4, iclass 40, count 0 2006.174.01:23:54.84#ibcon#read 4, iclass 40, count 0 2006.174.01:23:54.84#ibcon#about to read 5, iclass 40, count 0 2006.174.01:23:54.84#ibcon#read 5, iclass 40, count 0 2006.174.01:23:54.84#ibcon#about to read 6, iclass 40, count 0 2006.174.01:23:54.84#ibcon#read 6, iclass 40, count 0 2006.174.01:23:54.84#ibcon#end of sib2, iclass 40, count 0 2006.174.01:23:54.84#ibcon#*after write, iclass 40, count 0 2006.174.01:23:54.84#ibcon#*before return 0, iclass 40, count 0 2006.174.01:23:54.84#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.174.01:23:54.84#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.174.01:23:54.84#ibcon#about to clear, iclass 40 cls_cnt 0 2006.174.01:23:54.84#ibcon#cleared, iclass 40 cls_cnt 0 2006.174.01:23:54.84$vck44/vblo=7,734.99 2006.174.01:23:54.84#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.174.01:23:54.84#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.174.01:23:54.84#ibcon#ireg 17 cls_cnt 0 2006.174.01:23:54.84#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.174.01:23:54.84#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.174.01:23:54.84#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.174.01:23:54.84#ibcon#enter wrdev, iclass 4, count 0 2006.174.01:23:54.84#ibcon#first serial, iclass 4, count 0 2006.174.01:23:54.84#ibcon#enter sib2, iclass 4, count 0 2006.174.01:23:54.84#ibcon#flushed, iclass 4, count 0 2006.174.01:23:54.84#ibcon#about to write, iclass 4, count 0 2006.174.01:23:54.84#ibcon#wrote, iclass 4, count 0 2006.174.01:23:54.84#ibcon#about to read 3, iclass 4, count 0 2006.174.01:23:54.86#ibcon#read 3, iclass 4, count 0 2006.174.01:23:54.86#ibcon#about to read 4, iclass 4, count 0 2006.174.01:23:54.86#ibcon#read 4, iclass 4, count 0 2006.174.01:23:54.86#ibcon#about to read 5, iclass 4, count 0 2006.174.01:23:54.86#ibcon#read 5, iclass 4, count 0 2006.174.01:23:54.86#ibcon#about to read 6, iclass 4, count 0 2006.174.01:23:54.86#ibcon#read 6, iclass 4, count 0 2006.174.01:23:54.86#ibcon#end of sib2, iclass 4, count 0 2006.174.01:23:54.86#ibcon#*mode == 0, iclass 4, count 0 2006.174.01:23:54.86#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.174.01:23:54.86#ibcon#[28=FRQ=07,734.99\r\n] 2006.174.01:23:54.86#ibcon#*before write, iclass 4, count 0 2006.174.01:23:54.86#ibcon#enter sib2, iclass 4, count 0 2006.174.01:23:54.86#ibcon#flushed, iclass 4, count 0 2006.174.01:23:54.86#ibcon#about to write, iclass 4, count 0 2006.174.01:23:54.86#ibcon#wrote, iclass 4, count 0 2006.174.01:23:54.86#ibcon#about to read 3, iclass 4, count 0 2006.174.01:23:54.90#ibcon#read 3, iclass 4, count 0 2006.174.01:23:54.90#ibcon#about to read 4, iclass 4, count 0 2006.174.01:23:54.90#ibcon#read 4, iclass 4, count 0 2006.174.01:23:54.90#ibcon#about to read 5, iclass 4, count 0 2006.174.01:23:54.90#ibcon#read 5, iclass 4, count 0 2006.174.01:23:54.90#ibcon#about to read 6, iclass 4, count 0 2006.174.01:23:54.90#ibcon#read 6, iclass 4, count 0 2006.174.01:23:54.90#ibcon#end of sib2, iclass 4, count 0 2006.174.01:23:54.90#ibcon#*after write, iclass 4, count 0 2006.174.01:23:54.90#ibcon#*before return 0, iclass 4, count 0 2006.174.01:23:54.90#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.174.01:23:54.90#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.174.01:23:54.90#ibcon#about to clear, iclass 4 cls_cnt 0 2006.174.01:23:54.90#ibcon#cleared, iclass 4 cls_cnt 0 2006.174.01:23:54.90$vck44/vb=7,4 2006.174.01:23:54.90#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.174.01:23:54.90#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.174.01:23:54.90#ibcon#ireg 11 cls_cnt 2 2006.174.01:23:54.90#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.174.01:23:54.96#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.174.01:23:54.96#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.174.01:23:54.96#ibcon#enter wrdev, iclass 6, count 2 2006.174.01:23:54.96#ibcon#first serial, iclass 6, count 2 2006.174.01:23:54.96#ibcon#enter sib2, iclass 6, count 2 2006.174.01:23:54.96#ibcon#flushed, iclass 6, count 2 2006.174.01:23:54.96#ibcon#about to write, iclass 6, count 2 2006.174.01:23:54.96#ibcon#wrote, iclass 6, count 2 2006.174.01:23:54.96#ibcon#about to read 3, iclass 6, count 2 2006.174.01:23:54.98#ibcon#read 3, iclass 6, count 2 2006.174.01:23:54.98#ibcon#about to read 4, iclass 6, count 2 2006.174.01:23:54.98#ibcon#read 4, iclass 6, count 2 2006.174.01:23:54.98#ibcon#about to read 5, iclass 6, count 2 2006.174.01:23:54.98#ibcon#read 5, iclass 6, count 2 2006.174.01:23:54.98#ibcon#about to read 6, iclass 6, count 2 2006.174.01:23:54.98#ibcon#read 6, iclass 6, count 2 2006.174.01:23:54.98#ibcon#end of sib2, iclass 6, count 2 2006.174.01:23:54.98#ibcon#*mode == 0, iclass 6, count 2 2006.174.01:23:54.98#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.174.01:23:54.98#ibcon#[27=AT07-04\r\n] 2006.174.01:23:54.98#ibcon#*before write, iclass 6, count 2 2006.174.01:23:54.98#ibcon#enter sib2, iclass 6, count 2 2006.174.01:23:54.98#ibcon#flushed, iclass 6, count 2 2006.174.01:23:54.98#ibcon#about to write, iclass 6, count 2 2006.174.01:23:54.98#ibcon#wrote, iclass 6, count 2 2006.174.01:23:54.98#ibcon#about to read 3, iclass 6, count 2 2006.174.01:23:55.01#ibcon#read 3, iclass 6, count 2 2006.174.01:23:55.01#ibcon#about to read 4, iclass 6, count 2 2006.174.01:23:55.01#ibcon#read 4, iclass 6, count 2 2006.174.01:23:55.01#ibcon#about to read 5, iclass 6, count 2 2006.174.01:23:55.01#ibcon#read 5, iclass 6, count 2 2006.174.01:23:55.01#ibcon#about to read 6, iclass 6, count 2 2006.174.01:23:55.01#ibcon#read 6, iclass 6, count 2 2006.174.01:23:55.01#ibcon#end of sib2, iclass 6, count 2 2006.174.01:23:55.01#ibcon#*after write, iclass 6, count 2 2006.174.01:23:55.01#ibcon#*before return 0, iclass 6, count 2 2006.174.01:23:55.01#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.174.01:23:55.01#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.174.01:23:55.01#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.174.01:23:55.01#ibcon#ireg 7 cls_cnt 0 2006.174.01:23:55.01#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.174.01:23:55.13#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.174.01:23:55.13#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.174.01:23:55.13#ibcon#enter wrdev, iclass 6, count 0 2006.174.01:23:55.13#ibcon#first serial, iclass 6, count 0 2006.174.01:23:55.13#ibcon#enter sib2, iclass 6, count 0 2006.174.01:23:55.13#ibcon#flushed, iclass 6, count 0 2006.174.01:23:55.13#ibcon#about to write, iclass 6, count 0 2006.174.01:23:55.13#ibcon#wrote, iclass 6, count 0 2006.174.01:23:55.13#ibcon#about to read 3, iclass 6, count 0 2006.174.01:23:55.15#ibcon#read 3, iclass 6, count 0 2006.174.01:23:55.15#ibcon#about to read 4, iclass 6, count 0 2006.174.01:23:55.15#ibcon#read 4, iclass 6, count 0 2006.174.01:23:55.15#ibcon#about to read 5, iclass 6, count 0 2006.174.01:23:55.15#ibcon#read 5, iclass 6, count 0 2006.174.01:23:55.15#ibcon#about to read 6, iclass 6, count 0 2006.174.01:23:55.15#ibcon#read 6, iclass 6, count 0 2006.174.01:23:55.15#ibcon#end of sib2, iclass 6, count 0 2006.174.01:23:55.15#ibcon#*mode == 0, iclass 6, count 0 2006.174.01:23:55.15#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.174.01:23:55.15#ibcon#[27=USB\r\n] 2006.174.01:23:55.15#ibcon#*before write, iclass 6, count 0 2006.174.01:23:55.15#ibcon#enter sib2, iclass 6, count 0 2006.174.01:23:55.15#ibcon#flushed, iclass 6, count 0 2006.174.01:23:55.15#ibcon#about to write, iclass 6, count 0 2006.174.01:23:55.15#ibcon#wrote, iclass 6, count 0 2006.174.01:23:55.15#ibcon#about to read 3, iclass 6, count 0 2006.174.01:23:55.18#ibcon#read 3, iclass 6, count 0 2006.174.01:23:55.18#ibcon#about to read 4, iclass 6, count 0 2006.174.01:23:55.18#ibcon#read 4, iclass 6, count 0 2006.174.01:23:55.18#ibcon#about to read 5, iclass 6, count 0 2006.174.01:23:55.18#ibcon#read 5, iclass 6, count 0 2006.174.01:23:55.18#ibcon#about to read 6, iclass 6, count 0 2006.174.01:23:55.18#ibcon#read 6, iclass 6, count 0 2006.174.01:23:55.18#ibcon#end of sib2, iclass 6, count 0 2006.174.01:23:55.18#ibcon#*after write, iclass 6, count 0 2006.174.01:23:55.18#ibcon#*before return 0, iclass 6, count 0 2006.174.01:23:55.18#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.174.01:23:55.18#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.174.01:23:55.18#ibcon#about to clear, iclass 6 cls_cnt 0 2006.174.01:23:55.18#ibcon#cleared, iclass 6 cls_cnt 0 2006.174.01:23:55.18$vck44/vblo=8,744.99 2006.174.01:23:55.18#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.174.01:23:55.18#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.174.01:23:55.18#ibcon#ireg 17 cls_cnt 0 2006.174.01:23:55.18#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.174.01:23:55.18#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.174.01:23:55.18#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.174.01:23:55.18#ibcon#enter wrdev, iclass 10, count 0 2006.174.01:23:55.18#ibcon#first serial, iclass 10, count 0 2006.174.01:23:55.18#ibcon#enter sib2, iclass 10, count 0 2006.174.01:23:55.18#ibcon#flushed, iclass 10, count 0 2006.174.01:23:55.18#ibcon#about to write, iclass 10, count 0 2006.174.01:23:55.18#ibcon#wrote, iclass 10, count 0 2006.174.01:23:55.18#ibcon#about to read 3, iclass 10, count 0 2006.174.01:23:55.20#ibcon#read 3, iclass 10, count 0 2006.174.01:23:55.20#ibcon#about to read 4, iclass 10, count 0 2006.174.01:23:55.20#ibcon#read 4, iclass 10, count 0 2006.174.01:23:55.20#ibcon#about to read 5, iclass 10, count 0 2006.174.01:23:55.20#ibcon#read 5, iclass 10, count 0 2006.174.01:23:55.20#ibcon#about to read 6, iclass 10, count 0 2006.174.01:23:55.20#ibcon#read 6, iclass 10, count 0 2006.174.01:23:55.20#ibcon#end of sib2, iclass 10, count 0 2006.174.01:23:55.20#ibcon#*mode == 0, iclass 10, count 0 2006.174.01:23:55.20#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.174.01:23:55.20#ibcon#[28=FRQ=08,744.99\r\n] 2006.174.01:23:55.20#ibcon#*before write, iclass 10, count 0 2006.174.01:23:55.20#ibcon#enter sib2, iclass 10, count 0 2006.174.01:23:55.20#ibcon#flushed, iclass 10, count 0 2006.174.01:23:55.20#ibcon#about to write, iclass 10, count 0 2006.174.01:23:55.20#ibcon#wrote, iclass 10, count 0 2006.174.01:23:55.20#ibcon#about to read 3, iclass 10, count 0 2006.174.01:23:55.24#ibcon#read 3, iclass 10, count 0 2006.174.01:23:55.24#ibcon#about to read 4, iclass 10, count 0 2006.174.01:23:55.24#ibcon#read 4, iclass 10, count 0 2006.174.01:23:55.24#ibcon#about to read 5, iclass 10, count 0 2006.174.01:23:55.24#ibcon#read 5, iclass 10, count 0 2006.174.01:23:55.24#ibcon#about to read 6, iclass 10, count 0 2006.174.01:23:55.24#ibcon#read 6, iclass 10, count 0 2006.174.01:23:55.24#ibcon#end of sib2, iclass 10, count 0 2006.174.01:23:55.24#ibcon#*after write, iclass 10, count 0 2006.174.01:23:55.24#ibcon#*before return 0, iclass 10, count 0 2006.174.01:23:55.24#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.174.01:23:55.24#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.174.01:23:55.24#ibcon#about to clear, iclass 10 cls_cnt 0 2006.174.01:23:55.24#ibcon#cleared, iclass 10 cls_cnt 0 2006.174.01:23:55.24$vck44/vb=8,4 2006.174.01:23:55.24#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.174.01:23:55.24#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.174.01:23:55.24#ibcon#ireg 11 cls_cnt 2 2006.174.01:23:55.24#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.174.01:23:55.30#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.174.01:23:55.30#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.174.01:23:55.30#ibcon#enter wrdev, iclass 12, count 2 2006.174.01:23:55.30#ibcon#first serial, iclass 12, count 2 2006.174.01:23:55.30#ibcon#enter sib2, iclass 12, count 2 2006.174.01:23:55.30#ibcon#flushed, iclass 12, count 2 2006.174.01:23:55.30#ibcon#about to write, iclass 12, count 2 2006.174.01:23:55.30#ibcon#wrote, iclass 12, count 2 2006.174.01:23:55.30#ibcon#about to read 3, iclass 12, count 2 2006.174.01:23:55.32#ibcon#read 3, iclass 12, count 2 2006.174.01:23:55.32#ibcon#about to read 4, iclass 12, count 2 2006.174.01:23:55.32#ibcon#read 4, iclass 12, count 2 2006.174.01:23:55.32#ibcon#about to read 5, iclass 12, count 2 2006.174.01:23:55.32#ibcon#read 5, iclass 12, count 2 2006.174.01:23:55.32#ibcon#about to read 6, iclass 12, count 2 2006.174.01:23:55.32#ibcon#read 6, iclass 12, count 2 2006.174.01:23:55.32#ibcon#end of sib2, iclass 12, count 2 2006.174.01:23:55.32#ibcon#*mode == 0, iclass 12, count 2 2006.174.01:23:55.32#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.174.01:23:55.32#ibcon#[27=AT08-04\r\n] 2006.174.01:23:55.32#ibcon#*before write, iclass 12, count 2 2006.174.01:23:55.32#ibcon#enter sib2, iclass 12, count 2 2006.174.01:23:55.32#ibcon#flushed, iclass 12, count 2 2006.174.01:23:55.32#ibcon#about to write, iclass 12, count 2 2006.174.01:23:55.32#ibcon#wrote, iclass 12, count 2 2006.174.01:23:55.32#ibcon#about to read 3, iclass 12, count 2 2006.174.01:23:55.35#ibcon#read 3, iclass 12, count 2 2006.174.01:23:55.35#ibcon#about to read 4, iclass 12, count 2 2006.174.01:23:55.35#ibcon#read 4, iclass 12, count 2 2006.174.01:23:55.35#ibcon#about to read 5, iclass 12, count 2 2006.174.01:23:55.35#ibcon#read 5, iclass 12, count 2 2006.174.01:23:55.35#ibcon#about to read 6, iclass 12, count 2 2006.174.01:23:55.35#ibcon#read 6, iclass 12, count 2 2006.174.01:23:55.35#ibcon#end of sib2, iclass 12, count 2 2006.174.01:23:55.35#ibcon#*after write, iclass 12, count 2 2006.174.01:23:55.35#ibcon#*before return 0, iclass 12, count 2 2006.174.01:23:55.35#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.174.01:23:55.35#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.174.01:23:55.35#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.174.01:23:55.35#ibcon#ireg 7 cls_cnt 0 2006.174.01:23:55.35#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.174.01:23:55.47#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.174.01:23:55.47#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.174.01:23:55.47#ibcon#enter wrdev, iclass 12, count 0 2006.174.01:23:55.47#ibcon#first serial, iclass 12, count 0 2006.174.01:23:55.47#ibcon#enter sib2, iclass 12, count 0 2006.174.01:23:55.47#ibcon#flushed, iclass 12, count 0 2006.174.01:23:55.47#ibcon#about to write, iclass 12, count 0 2006.174.01:23:55.47#ibcon#wrote, iclass 12, count 0 2006.174.01:23:55.47#ibcon#about to read 3, iclass 12, count 0 2006.174.01:23:55.49#ibcon#read 3, iclass 12, count 0 2006.174.01:23:55.49#ibcon#about to read 4, iclass 12, count 0 2006.174.01:23:55.49#ibcon#read 4, iclass 12, count 0 2006.174.01:23:55.49#ibcon#about to read 5, iclass 12, count 0 2006.174.01:23:55.49#ibcon#read 5, iclass 12, count 0 2006.174.01:23:55.49#ibcon#about to read 6, iclass 12, count 0 2006.174.01:23:55.49#ibcon#read 6, iclass 12, count 0 2006.174.01:23:55.49#ibcon#end of sib2, iclass 12, count 0 2006.174.01:23:55.49#ibcon#*mode == 0, iclass 12, count 0 2006.174.01:23:55.49#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.174.01:23:55.49#ibcon#[27=USB\r\n] 2006.174.01:23:55.49#ibcon#*before write, iclass 12, count 0 2006.174.01:23:55.49#ibcon#enter sib2, iclass 12, count 0 2006.174.01:23:55.49#ibcon#flushed, iclass 12, count 0 2006.174.01:23:55.49#ibcon#about to write, iclass 12, count 0 2006.174.01:23:55.49#ibcon#wrote, iclass 12, count 0 2006.174.01:23:55.49#ibcon#about to read 3, iclass 12, count 0 2006.174.01:23:55.52#ibcon#read 3, iclass 12, count 0 2006.174.01:23:55.52#ibcon#about to read 4, iclass 12, count 0 2006.174.01:23:55.52#ibcon#read 4, iclass 12, count 0 2006.174.01:23:55.52#ibcon#about to read 5, iclass 12, count 0 2006.174.01:23:55.52#ibcon#read 5, iclass 12, count 0 2006.174.01:23:55.52#ibcon#about to read 6, iclass 12, count 0 2006.174.01:23:55.52#ibcon#read 6, iclass 12, count 0 2006.174.01:23:55.52#ibcon#end of sib2, iclass 12, count 0 2006.174.01:23:55.52#ibcon#*after write, iclass 12, count 0 2006.174.01:23:55.52#ibcon#*before return 0, iclass 12, count 0 2006.174.01:23:55.52#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.174.01:23:55.52#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.174.01:23:55.52#ibcon#about to clear, iclass 12 cls_cnt 0 2006.174.01:23:55.52#ibcon#cleared, iclass 12 cls_cnt 0 2006.174.01:23:55.52$vck44/vabw=wide 2006.174.01:23:55.52#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.174.01:23:55.52#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.174.01:23:55.52#ibcon#ireg 8 cls_cnt 0 2006.174.01:23:55.52#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.174.01:23:55.52#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.174.01:23:55.52#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.174.01:23:55.52#ibcon#enter wrdev, iclass 14, count 0 2006.174.01:23:55.52#ibcon#first serial, iclass 14, count 0 2006.174.01:23:55.52#ibcon#enter sib2, iclass 14, count 0 2006.174.01:23:55.52#ibcon#flushed, iclass 14, count 0 2006.174.01:23:55.52#ibcon#about to write, iclass 14, count 0 2006.174.01:23:55.52#ibcon#wrote, iclass 14, count 0 2006.174.01:23:55.52#ibcon#about to read 3, iclass 14, count 0 2006.174.01:23:55.54#ibcon#read 3, iclass 14, count 0 2006.174.01:23:55.54#ibcon#about to read 4, iclass 14, count 0 2006.174.01:23:55.54#ibcon#read 4, iclass 14, count 0 2006.174.01:23:55.54#ibcon#about to read 5, iclass 14, count 0 2006.174.01:23:55.54#ibcon#read 5, iclass 14, count 0 2006.174.01:23:55.54#ibcon#about to read 6, iclass 14, count 0 2006.174.01:23:55.54#ibcon#read 6, iclass 14, count 0 2006.174.01:23:55.54#ibcon#end of sib2, iclass 14, count 0 2006.174.01:23:55.54#ibcon#*mode == 0, iclass 14, count 0 2006.174.01:23:55.54#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.174.01:23:55.54#ibcon#[25=BW32\r\n] 2006.174.01:23:55.54#ibcon#*before write, iclass 14, count 0 2006.174.01:23:55.54#ibcon#enter sib2, iclass 14, count 0 2006.174.01:23:55.54#ibcon#flushed, iclass 14, count 0 2006.174.01:23:55.54#ibcon#about to write, iclass 14, count 0 2006.174.01:23:55.54#ibcon#wrote, iclass 14, count 0 2006.174.01:23:55.54#ibcon#about to read 3, iclass 14, count 0 2006.174.01:23:55.57#ibcon#read 3, iclass 14, count 0 2006.174.01:23:55.57#ibcon#about to read 4, iclass 14, count 0 2006.174.01:23:55.57#ibcon#read 4, iclass 14, count 0 2006.174.01:23:55.57#ibcon#about to read 5, iclass 14, count 0 2006.174.01:23:55.57#ibcon#read 5, iclass 14, count 0 2006.174.01:23:55.57#ibcon#about to read 6, iclass 14, count 0 2006.174.01:23:55.57#ibcon#read 6, iclass 14, count 0 2006.174.01:23:55.57#ibcon#end of sib2, iclass 14, count 0 2006.174.01:23:55.57#ibcon#*after write, iclass 14, count 0 2006.174.01:23:55.57#ibcon#*before return 0, iclass 14, count 0 2006.174.01:23:55.57#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.174.01:23:55.57#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.174.01:23:55.57#ibcon#about to clear, iclass 14 cls_cnt 0 2006.174.01:23:55.57#ibcon#cleared, iclass 14 cls_cnt 0 2006.174.01:23:55.57$vck44/vbbw=wide 2006.174.01:23:55.57#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.174.01:23:55.57#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.174.01:23:55.57#ibcon#ireg 8 cls_cnt 0 2006.174.01:23:55.57#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.174.01:23:55.64#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.174.01:23:55.64#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.174.01:23:55.64#ibcon#enter wrdev, iclass 16, count 0 2006.174.01:23:55.64#ibcon#first serial, iclass 16, count 0 2006.174.01:23:55.64#ibcon#enter sib2, iclass 16, count 0 2006.174.01:23:55.64#ibcon#flushed, iclass 16, count 0 2006.174.01:23:55.64#ibcon#about to write, iclass 16, count 0 2006.174.01:23:55.64#ibcon#wrote, iclass 16, count 0 2006.174.01:23:55.64#ibcon#about to read 3, iclass 16, count 0 2006.174.01:23:55.66#ibcon#read 3, iclass 16, count 0 2006.174.01:23:55.66#ibcon#about to read 4, iclass 16, count 0 2006.174.01:23:55.66#ibcon#read 4, iclass 16, count 0 2006.174.01:23:55.66#ibcon#about to read 5, iclass 16, count 0 2006.174.01:23:55.66#ibcon#read 5, iclass 16, count 0 2006.174.01:23:55.66#ibcon#about to read 6, iclass 16, count 0 2006.174.01:23:55.66#ibcon#read 6, iclass 16, count 0 2006.174.01:23:55.66#ibcon#end of sib2, iclass 16, count 0 2006.174.01:23:55.66#ibcon#*mode == 0, iclass 16, count 0 2006.174.01:23:55.66#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.174.01:23:55.66#ibcon#[27=BW32\r\n] 2006.174.01:23:55.66#ibcon#*before write, iclass 16, count 0 2006.174.01:23:55.66#ibcon#enter sib2, iclass 16, count 0 2006.174.01:23:55.66#ibcon#flushed, iclass 16, count 0 2006.174.01:23:55.66#ibcon#about to write, iclass 16, count 0 2006.174.01:23:55.66#ibcon#wrote, iclass 16, count 0 2006.174.01:23:55.66#ibcon#about to read 3, iclass 16, count 0 2006.174.01:23:55.69#ibcon#read 3, iclass 16, count 0 2006.174.01:23:55.69#ibcon#about to read 4, iclass 16, count 0 2006.174.01:23:55.69#ibcon#read 4, iclass 16, count 0 2006.174.01:23:55.69#ibcon#about to read 5, iclass 16, count 0 2006.174.01:23:55.69#ibcon#read 5, iclass 16, count 0 2006.174.01:23:55.69#ibcon#about to read 6, iclass 16, count 0 2006.174.01:23:55.69#ibcon#read 6, iclass 16, count 0 2006.174.01:23:55.69#ibcon#end of sib2, iclass 16, count 0 2006.174.01:23:55.69#ibcon#*after write, iclass 16, count 0 2006.174.01:23:55.69#ibcon#*before return 0, iclass 16, count 0 2006.174.01:23:55.69#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.174.01:23:55.69#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.174.01:23:55.69#ibcon#about to clear, iclass 16 cls_cnt 0 2006.174.01:23:55.69#ibcon#cleared, iclass 16 cls_cnt 0 2006.174.01:23:55.69$setupk4/ifdk4 2006.174.01:23:55.69$ifdk4/lo= 2006.174.01:23:55.69$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.174.01:23:55.69$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.174.01:23:55.69$ifdk4/patch= 2006.174.01:23:55.69$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.174.01:23:55.69$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.174.01:23:55.69$setupk4/!*+20s 2006.174.01:24:03.21#abcon#<5=/08 0.8 2.4 25.60 791003.4\r\n> 2006.174.01:24:03.23#abcon#{5=INTERFACE CLEAR} 2006.174.01:24:03.29#abcon#[5=S1D000X0/0*\r\n] 2006.174.01:24:10.20$setupk4/"tpicd 2006.174.01:24:10.20$setupk4/echo=off 2006.174.01:24:10.20$setupk4/xlog=off 2006.174.01:24:10.20:!2006.174.01:27:24 2006.174.01:24:25.14#trakl#Source acquired 2006.174.01:24:27.14#flagr#flagr/antenna,acquired 2006.174.01:27:24.00:preob 2006.174.01:27:25.14/onsource/TRACKING 2006.174.01:27:25.14:!2006.174.01:27:34 2006.174.01:27:34.00:"tape 2006.174.01:27:34.00:"st=record 2006.174.01:27:34.00:data_valid=on 2006.174.01:27:34.00:midob 2006.174.01:27:34.14/onsource/TRACKING 2006.174.01:27:34.14/wx/25.72,1003.3,76 2006.174.01:27:34.28/cable/+6.4994E-03 2006.174.01:27:35.37/va/01,07,usb,yes,34,37 2006.174.01:27:35.37/va/02,06,usb,yes,34,35 2006.174.01:27:35.37/va/03,05,usb,yes,43,45 2006.174.01:27:35.37/va/04,06,usb,yes,34,36 2006.174.01:27:35.37/va/05,04,usb,yes,27,28 2006.174.01:27:35.37/va/06,03,usb,yes,38,38 2006.174.01:27:35.37/va/07,04,usb,yes,31,32 2006.174.01:27:35.37/va/08,04,usb,yes,26,32 2006.174.01:27:35.60/valo/01,524.99,yes,locked 2006.174.01:27:35.60/valo/02,534.99,yes,locked 2006.174.01:27:35.60/valo/03,564.99,yes,locked 2006.174.01:27:35.60/valo/04,624.99,yes,locked 2006.174.01:27:35.60/valo/05,734.99,yes,locked 2006.174.01:27:35.60/valo/06,814.99,yes,locked 2006.174.01:27:35.60/valo/07,864.99,yes,locked 2006.174.01:27:35.60/valo/08,884.99,yes,locked 2006.174.01:27:36.69/vb/01,04,usb,yes,29,27 2006.174.01:27:36.69/vb/02,04,usb,yes,31,31 2006.174.01:27:36.69/vb/03,04,usb,yes,28,31 2006.174.01:27:36.69/vb/04,04,usb,yes,32,31 2006.174.01:27:36.69/vb/05,04,usb,yes,25,28 2006.174.01:27:36.69/vb/06,04,usb,yes,30,26 2006.174.01:27:36.69/vb/07,04,usb,yes,29,29 2006.174.01:27:36.69/vb/08,04,usb,yes,27,30 2006.174.01:27:36.93/vblo/01,629.99,yes,locked 2006.174.01:27:36.93/vblo/02,634.99,yes,locked 2006.174.01:27:36.93/vblo/03,649.99,yes,locked 2006.174.01:27:36.93/vblo/04,679.99,yes,locked 2006.174.01:27:36.93/vblo/05,709.99,yes,locked 2006.174.01:27:36.93/vblo/06,719.99,yes,locked 2006.174.01:27:36.93/vblo/07,734.99,yes,locked 2006.174.01:27:36.93/vblo/08,744.99,yes,locked 2006.174.01:27:37.08/vabw/8 2006.174.01:27:37.23/vbbw/8 2006.174.01:27:37.32/xfe/off,on,14.2 2006.174.01:27:37.69/ifatt/23,28,28,28 2006.174.01:27:38.07/fmout-gps/S +3.77E-07 2006.174.01:27:38.11:!2006.174.01:28:24 2006.174.01:28:24.00:data_valid=off 2006.174.01:28:24.00:"et 2006.174.01:28:24.00:!+3s 2006.174.01:28:27.02:"tape 2006.174.01:28:27.02:postob 2006.174.01:28:27.21/cable/+6.5005E-03 2006.174.01:28:27.21/wx/25.73,1003.3,77 2006.174.01:28:28.08/fmout-gps/S +3.77E-07 2006.174.01:28:28.08:scan_name=174-0131,jd0606,260 2006.174.01:28:28.08:source=2201+315,220314.98,314538.3,2000.0,ccw 2006.174.01:28:29.14#flagr#flagr/antenna,new-source 2006.174.01:28:29.14:checkk5 2006.174.01:28:29.57/chk_autoobs//k5ts1/ autoobs is running! 2006.174.01:28:29.97/chk_autoobs//k5ts2/ autoobs is running! 2006.174.01:28:30.37/chk_autoobs//k5ts3/ autoobs is running! 2006.174.01:28:30.77/chk_autoobs//k5ts4/ autoobs is running! 2006.174.01:28:31.15/chk_obsdata//k5ts1/T1740127??a.dat file size is correct (nominal:200MB, actual:200MB). 2006.174.01:28:31.55/chk_obsdata//k5ts2/T1740127??b.dat file size is correct (nominal:200MB, actual:200MB). 2006.174.01:28:31.95/chk_obsdata//k5ts3/T1740127??c.dat file size is correct (nominal:200MB, actual:200MB). 2006.174.01:28:32.34/chk_obsdata//k5ts4/T1740127??d.dat file size is correct (nominal:200MB, actual:200MB). 2006.174.01:28:33.05/k5log//k5ts1_log_newline 2006.174.01:28:33.75/k5log//k5ts2_log_newline 2006.174.01:28:34.47/k5log//k5ts3_log_newline 2006.174.01:28:35.17/k5log//k5ts4_log_newline 2006.174.01:28:35.20/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.174.01:28:35.20:setupk4=1 2006.174.01:28:35.20$setupk4/echo=on 2006.174.01:28:35.20$setupk4/pcalon 2006.174.01:28:35.20$pcalon/"no phase cal control is implemented here 2006.174.01:28:35.20$setupk4/"tpicd=stop 2006.174.01:28:35.20$setupk4/"rec=synch_on 2006.174.01:28:35.20$setupk4/"rec_mode=128 2006.174.01:28:35.20$setupk4/!* 2006.174.01:28:35.20$setupk4/recpk4 2006.174.01:28:35.20$recpk4/recpatch= 2006.174.01:28:35.20$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.174.01:28:35.20$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.174.01:28:35.20$setupk4/vck44 2006.174.01:28:35.20$vck44/valo=1,524.99 2006.174.01:28:35.20#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.174.01:28:35.20#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.174.01:28:35.20#ibcon#ireg 17 cls_cnt 0 2006.174.01:28:35.20#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.174.01:28:35.20#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.174.01:28:35.20#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.174.01:28:35.20#ibcon#enter wrdev, iclass 21, count 0 2006.174.01:28:35.20#ibcon#first serial, iclass 21, count 0 2006.174.01:28:35.20#ibcon#enter sib2, iclass 21, count 0 2006.174.01:28:35.20#ibcon#flushed, iclass 21, count 0 2006.174.01:28:35.20#ibcon#about to write, iclass 21, count 0 2006.174.01:28:35.20#ibcon#wrote, iclass 21, count 0 2006.174.01:28:35.20#ibcon#about to read 3, iclass 21, count 0 2006.174.01:28:35.22#ibcon#read 3, iclass 21, count 0 2006.174.01:28:35.22#ibcon#about to read 4, iclass 21, count 0 2006.174.01:28:35.22#ibcon#read 4, iclass 21, count 0 2006.174.01:28:35.22#ibcon#about to read 5, iclass 21, count 0 2006.174.01:28:35.22#ibcon#read 5, iclass 21, count 0 2006.174.01:28:35.22#ibcon#about to read 6, iclass 21, count 0 2006.174.01:28:35.22#ibcon#read 6, iclass 21, count 0 2006.174.01:28:35.22#ibcon#end of sib2, iclass 21, count 0 2006.174.01:28:35.22#ibcon#*mode == 0, iclass 21, count 0 2006.174.01:28:35.22#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.174.01:28:35.22#ibcon#[26=FRQ=01,524.99\r\n] 2006.174.01:28:35.22#ibcon#*before write, iclass 21, count 0 2006.174.01:28:35.22#ibcon#enter sib2, iclass 21, count 0 2006.174.01:28:35.22#ibcon#flushed, iclass 21, count 0 2006.174.01:28:35.22#ibcon#about to write, iclass 21, count 0 2006.174.01:28:35.22#ibcon#wrote, iclass 21, count 0 2006.174.01:28:35.22#ibcon#about to read 3, iclass 21, count 0 2006.174.01:28:35.27#ibcon#read 3, iclass 21, count 0 2006.174.01:28:35.27#ibcon#about to read 4, iclass 21, count 0 2006.174.01:28:35.27#ibcon#read 4, iclass 21, count 0 2006.174.01:28:35.27#ibcon#about to read 5, iclass 21, count 0 2006.174.01:28:35.27#ibcon#read 5, iclass 21, count 0 2006.174.01:28:35.27#ibcon#about to read 6, iclass 21, count 0 2006.174.01:28:35.27#ibcon#read 6, iclass 21, count 0 2006.174.01:28:35.27#ibcon#end of sib2, iclass 21, count 0 2006.174.01:28:35.27#ibcon#*after write, iclass 21, count 0 2006.174.01:28:35.27#ibcon#*before return 0, iclass 21, count 0 2006.174.01:28:35.27#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.174.01:28:35.27#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.174.01:28:35.27#ibcon#about to clear, iclass 21 cls_cnt 0 2006.174.01:28:35.27#ibcon#cleared, iclass 21 cls_cnt 0 2006.174.01:28:35.27$vck44/va=1,7 2006.174.01:28:35.27#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.174.01:28:35.27#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.174.01:28:35.27#ibcon#ireg 11 cls_cnt 2 2006.174.01:28:35.27#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.174.01:28:35.27#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.174.01:28:35.27#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.174.01:28:35.27#ibcon#enter wrdev, iclass 23, count 2 2006.174.01:28:35.27#ibcon#first serial, iclass 23, count 2 2006.174.01:28:35.27#ibcon#enter sib2, iclass 23, count 2 2006.174.01:28:35.27#ibcon#flushed, iclass 23, count 2 2006.174.01:28:35.27#ibcon#about to write, iclass 23, count 2 2006.174.01:28:35.27#ibcon#wrote, iclass 23, count 2 2006.174.01:28:35.27#ibcon#about to read 3, iclass 23, count 2 2006.174.01:28:35.29#ibcon#read 3, iclass 23, count 2 2006.174.01:28:35.29#ibcon#about to read 4, iclass 23, count 2 2006.174.01:28:35.29#ibcon#read 4, iclass 23, count 2 2006.174.01:28:35.29#ibcon#about to read 5, iclass 23, count 2 2006.174.01:28:35.29#ibcon#read 5, iclass 23, count 2 2006.174.01:28:35.29#ibcon#about to read 6, iclass 23, count 2 2006.174.01:28:35.29#ibcon#read 6, iclass 23, count 2 2006.174.01:28:35.29#ibcon#end of sib2, iclass 23, count 2 2006.174.01:28:35.29#ibcon#*mode == 0, iclass 23, count 2 2006.174.01:28:35.29#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.174.01:28:35.29#ibcon#[25=AT01-07\r\n] 2006.174.01:28:35.29#ibcon#*before write, iclass 23, count 2 2006.174.01:28:35.29#ibcon#enter sib2, iclass 23, count 2 2006.174.01:28:35.29#ibcon#flushed, iclass 23, count 2 2006.174.01:28:35.29#ibcon#about to write, iclass 23, count 2 2006.174.01:28:35.29#ibcon#wrote, iclass 23, count 2 2006.174.01:28:35.29#ibcon#about to read 3, iclass 23, count 2 2006.174.01:28:35.32#ibcon#read 3, iclass 23, count 2 2006.174.01:28:35.32#ibcon#about to read 4, iclass 23, count 2 2006.174.01:28:35.32#ibcon#read 4, iclass 23, count 2 2006.174.01:28:35.32#ibcon#about to read 5, iclass 23, count 2 2006.174.01:28:35.32#ibcon#read 5, iclass 23, count 2 2006.174.01:28:35.32#ibcon#about to read 6, iclass 23, count 2 2006.174.01:28:35.32#ibcon#read 6, iclass 23, count 2 2006.174.01:28:35.32#ibcon#end of sib2, iclass 23, count 2 2006.174.01:28:35.32#ibcon#*after write, iclass 23, count 2 2006.174.01:28:35.32#ibcon#*before return 0, iclass 23, count 2 2006.174.01:28:35.32#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.174.01:28:35.32#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.174.01:28:35.32#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.174.01:28:35.32#ibcon#ireg 7 cls_cnt 0 2006.174.01:28:35.32#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.174.01:28:35.44#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.174.01:28:35.44#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.174.01:28:35.44#ibcon#enter wrdev, iclass 23, count 0 2006.174.01:28:35.44#ibcon#first serial, iclass 23, count 0 2006.174.01:28:35.44#ibcon#enter sib2, iclass 23, count 0 2006.174.01:28:35.44#ibcon#flushed, iclass 23, count 0 2006.174.01:28:35.44#ibcon#about to write, iclass 23, count 0 2006.174.01:28:35.44#ibcon#wrote, iclass 23, count 0 2006.174.01:28:35.44#ibcon#about to read 3, iclass 23, count 0 2006.174.01:28:35.46#ibcon#read 3, iclass 23, count 0 2006.174.01:28:35.46#ibcon#about to read 4, iclass 23, count 0 2006.174.01:28:35.46#ibcon#read 4, iclass 23, count 0 2006.174.01:28:35.46#ibcon#about to read 5, iclass 23, count 0 2006.174.01:28:35.46#ibcon#read 5, iclass 23, count 0 2006.174.01:28:35.46#ibcon#about to read 6, iclass 23, count 0 2006.174.01:28:35.46#ibcon#read 6, iclass 23, count 0 2006.174.01:28:35.46#ibcon#end of sib2, iclass 23, count 0 2006.174.01:28:35.46#ibcon#*mode == 0, iclass 23, count 0 2006.174.01:28:35.46#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.174.01:28:35.46#ibcon#[25=USB\r\n] 2006.174.01:28:35.46#ibcon#*before write, iclass 23, count 0 2006.174.01:28:35.46#ibcon#enter sib2, iclass 23, count 0 2006.174.01:28:35.46#ibcon#flushed, iclass 23, count 0 2006.174.01:28:35.46#ibcon#about to write, iclass 23, count 0 2006.174.01:28:35.46#ibcon#wrote, iclass 23, count 0 2006.174.01:28:35.46#ibcon#about to read 3, iclass 23, count 0 2006.174.01:28:35.49#ibcon#read 3, iclass 23, count 0 2006.174.01:28:35.49#ibcon#about to read 4, iclass 23, count 0 2006.174.01:28:35.49#ibcon#read 4, iclass 23, count 0 2006.174.01:28:35.49#ibcon#about to read 5, iclass 23, count 0 2006.174.01:28:35.49#ibcon#read 5, iclass 23, count 0 2006.174.01:28:35.49#ibcon#about to read 6, iclass 23, count 0 2006.174.01:28:35.49#ibcon#read 6, iclass 23, count 0 2006.174.01:28:35.49#ibcon#end of sib2, iclass 23, count 0 2006.174.01:28:35.49#ibcon#*after write, iclass 23, count 0 2006.174.01:28:35.49#ibcon#*before return 0, iclass 23, count 0 2006.174.01:28:35.49#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.174.01:28:35.49#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.174.01:28:35.49#ibcon#about to clear, iclass 23 cls_cnt 0 2006.174.01:28:35.49#ibcon#cleared, iclass 23 cls_cnt 0 2006.174.01:28:35.49$vck44/valo=2,534.99 2006.174.01:28:35.49#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.174.01:28:35.49#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.174.01:28:35.49#ibcon#ireg 17 cls_cnt 0 2006.174.01:28:35.49#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.174.01:28:35.49#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.174.01:28:35.49#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.174.01:28:35.49#ibcon#enter wrdev, iclass 25, count 0 2006.174.01:28:35.49#ibcon#first serial, iclass 25, count 0 2006.174.01:28:35.49#ibcon#enter sib2, iclass 25, count 0 2006.174.01:28:35.49#ibcon#flushed, iclass 25, count 0 2006.174.01:28:35.49#ibcon#about to write, iclass 25, count 0 2006.174.01:28:35.49#ibcon#wrote, iclass 25, count 0 2006.174.01:28:35.49#ibcon#about to read 3, iclass 25, count 0 2006.174.01:28:35.51#ibcon#read 3, iclass 25, count 0 2006.174.01:28:35.51#ibcon#about to read 4, iclass 25, count 0 2006.174.01:28:35.51#ibcon#read 4, iclass 25, count 0 2006.174.01:28:35.51#ibcon#about to read 5, iclass 25, count 0 2006.174.01:28:35.51#ibcon#read 5, iclass 25, count 0 2006.174.01:28:35.51#ibcon#about to read 6, iclass 25, count 0 2006.174.01:28:35.51#ibcon#read 6, iclass 25, count 0 2006.174.01:28:35.51#ibcon#end of sib2, iclass 25, count 0 2006.174.01:28:35.51#ibcon#*mode == 0, iclass 25, count 0 2006.174.01:28:35.51#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.174.01:28:35.51#ibcon#[26=FRQ=02,534.99\r\n] 2006.174.01:28:35.51#ibcon#*before write, iclass 25, count 0 2006.174.01:28:35.51#ibcon#enter sib2, iclass 25, count 0 2006.174.01:28:35.51#ibcon#flushed, iclass 25, count 0 2006.174.01:28:35.51#ibcon#about to write, iclass 25, count 0 2006.174.01:28:35.51#ibcon#wrote, iclass 25, count 0 2006.174.01:28:35.51#ibcon#about to read 3, iclass 25, count 0 2006.174.01:28:35.55#ibcon#read 3, iclass 25, count 0 2006.174.01:28:35.55#ibcon#about to read 4, iclass 25, count 0 2006.174.01:28:35.55#ibcon#read 4, iclass 25, count 0 2006.174.01:28:35.55#ibcon#about to read 5, iclass 25, count 0 2006.174.01:28:35.55#ibcon#read 5, iclass 25, count 0 2006.174.01:28:35.55#ibcon#about to read 6, iclass 25, count 0 2006.174.01:28:35.55#ibcon#read 6, iclass 25, count 0 2006.174.01:28:35.55#ibcon#end of sib2, iclass 25, count 0 2006.174.01:28:35.55#ibcon#*after write, iclass 25, count 0 2006.174.01:28:35.55#ibcon#*before return 0, iclass 25, count 0 2006.174.01:28:35.55#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.174.01:28:35.55#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.174.01:28:35.55#ibcon#about to clear, iclass 25 cls_cnt 0 2006.174.01:28:35.55#ibcon#cleared, iclass 25 cls_cnt 0 2006.174.01:28:35.55$vck44/va=2,6 2006.174.01:28:35.55#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.174.01:28:35.55#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.174.01:28:35.55#ibcon#ireg 11 cls_cnt 2 2006.174.01:28:35.55#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.174.01:28:35.61#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.174.01:28:35.61#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.174.01:28:35.61#ibcon#enter wrdev, iclass 27, count 2 2006.174.01:28:35.61#ibcon#first serial, iclass 27, count 2 2006.174.01:28:35.61#ibcon#enter sib2, iclass 27, count 2 2006.174.01:28:35.61#ibcon#flushed, iclass 27, count 2 2006.174.01:28:35.61#ibcon#about to write, iclass 27, count 2 2006.174.01:28:35.61#ibcon#wrote, iclass 27, count 2 2006.174.01:28:35.61#ibcon#about to read 3, iclass 27, count 2 2006.174.01:28:35.63#ibcon#read 3, iclass 27, count 2 2006.174.01:28:35.63#ibcon#about to read 4, iclass 27, count 2 2006.174.01:28:35.63#ibcon#read 4, iclass 27, count 2 2006.174.01:28:35.63#ibcon#about to read 5, iclass 27, count 2 2006.174.01:28:35.63#ibcon#read 5, iclass 27, count 2 2006.174.01:28:35.63#ibcon#about to read 6, iclass 27, count 2 2006.174.01:28:35.63#ibcon#read 6, iclass 27, count 2 2006.174.01:28:35.63#ibcon#end of sib2, iclass 27, count 2 2006.174.01:28:35.63#ibcon#*mode == 0, iclass 27, count 2 2006.174.01:28:35.63#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.174.01:28:35.63#ibcon#[25=AT02-06\r\n] 2006.174.01:28:35.63#ibcon#*before write, iclass 27, count 2 2006.174.01:28:35.63#ibcon#enter sib2, iclass 27, count 2 2006.174.01:28:35.63#ibcon#flushed, iclass 27, count 2 2006.174.01:28:35.63#ibcon#about to write, iclass 27, count 2 2006.174.01:28:35.63#ibcon#wrote, iclass 27, count 2 2006.174.01:28:35.63#ibcon#about to read 3, iclass 27, count 2 2006.174.01:28:35.66#ibcon#read 3, iclass 27, count 2 2006.174.01:28:35.66#ibcon#about to read 4, iclass 27, count 2 2006.174.01:28:35.66#ibcon#read 4, iclass 27, count 2 2006.174.01:28:35.66#ibcon#about to read 5, iclass 27, count 2 2006.174.01:28:35.66#ibcon#read 5, iclass 27, count 2 2006.174.01:28:35.66#ibcon#about to read 6, iclass 27, count 2 2006.174.01:28:35.66#ibcon#read 6, iclass 27, count 2 2006.174.01:28:35.66#ibcon#end of sib2, iclass 27, count 2 2006.174.01:28:35.66#ibcon#*after write, iclass 27, count 2 2006.174.01:28:35.66#ibcon#*before return 0, iclass 27, count 2 2006.174.01:28:35.66#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.174.01:28:35.66#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.174.01:28:35.66#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.174.01:28:35.66#ibcon#ireg 7 cls_cnt 0 2006.174.01:28:35.66#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.174.01:28:35.78#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.174.01:28:35.78#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.174.01:28:35.78#ibcon#enter wrdev, iclass 27, count 0 2006.174.01:28:35.78#ibcon#first serial, iclass 27, count 0 2006.174.01:28:35.78#ibcon#enter sib2, iclass 27, count 0 2006.174.01:28:35.78#ibcon#flushed, iclass 27, count 0 2006.174.01:28:35.78#ibcon#about to write, iclass 27, count 0 2006.174.01:28:35.78#ibcon#wrote, iclass 27, count 0 2006.174.01:28:35.78#ibcon#about to read 3, iclass 27, count 0 2006.174.01:28:35.80#ibcon#read 3, iclass 27, count 0 2006.174.01:28:35.80#ibcon#about to read 4, iclass 27, count 0 2006.174.01:28:35.80#ibcon#read 4, iclass 27, count 0 2006.174.01:28:35.80#ibcon#about to read 5, iclass 27, count 0 2006.174.01:28:35.80#ibcon#read 5, iclass 27, count 0 2006.174.01:28:35.80#ibcon#about to read 6, iclass 27, count 0 2006.174.01:28:35.80#ibcon#read 6, iclass 27, count 0 2006.174.01:28:35.80#ibcon#end of sib2, iclass 27, count 0 2006.174.01:28:35.80#ibcon#*mode == 0, iclass 27, count 0 2006.174.01:28:35.80#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.174.01:28:35.80#ibcon#[25=USB\r\n] 2006.174.01:28:35.80#ibcon#*before write, iclass 27, count 0 2006.174.01:28:35.80#ibcon#enter sib2, iclass 27, count 0 2006.174.01:28:35.80#ibcon#flushed, iclass 27, count 0 2006.174.01:28:35.80#ibcon#about to write, iclass 27, count 0 2006.174.01:28:35.80#ibcon#wrote, iclass 27, count 0 2006.174.01:28:35.80#ibcon#about to read 3, iclass 27, count 0 2006.174.01:28:35.83#ibcon#read 3, iclass 27, count 0 2006.174.01:28:35.83#ibcon#about to read 4, iclass 27, count 0 2006.174.01:28:35.83#ibcon#read 4, iclass 27, count 0 2006.174.01:28:35.83#ibcon#about to read 5, iclass 27, count 0 2006.174.01:28:35.83#ibcon#read 5, iclass 27, count 0 2006.174.01:28:35.83#ibcon#about to read 6, iclass 27, count 0 2006.174.01:28:35.83#ibcon#read 6, iclass 27, count 0 2006.174.01:28:35.83#ibcon#end of sib2, iclass 27, count 0 2006.174.01:28:35.83#ibcon#*after write, iclass 27, count 0 2006.174.01:28:35.83#ibcon#*before return 0, iclass 27, count 0 2006.174.01:28:35.83#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.174.01:28:35.83#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.174.01:28:35.83#ibcon#about to clear, iclass 27 cls_cnt 0 2006.174.01:28:35.83#ibcon#cleared, iclass 27 cls_cnt 0 2006.174.01:28:35.83$vck44/valo=3,564.99 2006.174.01:28:35.83#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.174.01:28:35.83#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.174.01:28:35.83#ibcon#ireg 17 cls_cnt 0 2006.174.01:28:35.83#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.174.01:28:35.83#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.174.01:28:35.83#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.174.01:28:35.83#ibcon#enter wrdev, iclass 29, count 0 2006.174.01:28:35.83#ibcon#first serial, iclass 29, count 0 2006.174.01:28:35.83#ibcon#enter sib2, iclass 29, count 0 2006.174.01:28:35.83#ibcon#flushed, iclass 29, count 0 2006.174.01:28:35.83#ibcon#about to write, iclass 29, count 0 2006.174.01:28:35.83#ibcon#wrote, iclass 29, count 0 2006.174.01:28:35.83#ibcon#about to read 3, iclass 29, count 0 2006.174.01:28:35.85#ibcon#read 3, iclass 29, count 0 2006.174.01:28:35.85#ibcon#about to read 4, iclass 29, count 0 2006.174.01:28:35.85#ibcon#read 4, iclass 29, count 0 2006.174.01:28:35.85#ibcon#about to read 5, iclass 29, count 0 2006.174.01:28:35.85#ibcon#read 5, iclass 29, count 0 2006.174.01:28:35.85#ibcon#about to read 6, iclass 29, count 0 2006.174.01:28:35.85#ibcon#read 6, iclass 29, count 0 2006.174.01:28:35.85#ibcon#end of sib2, iclass 29, count 0 2006.174.01:28:35.85#ibcon#*mode == 0, iclass 29, count 0 2006.174.01:28:35.85#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.174.01:28:35.85#ibcon#[26=FRQ=03,564.99\r\n] 2006.174.01:28:35.85#ibcon#*before write, iclass 29, count 0 2006.174.01:28:35.85#ibcon#enter sib2, iclass 29, count 0 2006.174.01:28:35.85#ibcon#flushed, iclass 29, count 0 2006.174.01:28:35.85#ibcon#about to write, iclass 29, count 0 2006.174.01:28:35.85#ibcon#wrote, iclass 29, count 0 2006.174.01:28:35.85#ibcon#about to read 3, iclass 29, count 0 2006.174.01:28:35.89#ibcon#read 3, iclass 29, count 0 2006.174.01:28:35.89#ibcon#about to read 4, iclass 29, count 0 2006.174.01:28:35.89#ibcon#read 4, iclass 29, count 0 2006.174.01:28:35.89#ibcon#about to read 5, iclass 29, count 0 2006.174.01:28:35.89#ibcon#read 5, iclass 29, count 0 2006.174.01:28:35.89#ibcon#about to read 6, iclass 29, count 0 2006.174.01:28:35.89#ibcon#read 6, iclass 29, count 0 2006.174.01:28:35.89#ibcon#end of sib2, iclass 29, count 0 2006.174.01:28:35.89#ibcon#*after write, iclass 29, count 0 2006.174.01:28:35.89#ibcon#*before return 0, iclass 29, count 0 2006.174.01:28:35.89#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.174.01:28:35.89#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.174.01:28:35.89#ibcon#about to clear, iclass 29 cls_cnt 0 2006.174.01:28:35.89#ibcon#cleared, iclass 29 cls_cnt 0 2006.174.01:28:35.89$vck44/va=3,5 2006.174.01:28:35.89#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.174.01:28:35.89#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.174.01:28:35.89#ibcon#ireg 11 cls_cnt 2 2006.174.01:28:35.89#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.174.01:28:35.95#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.174.01:28:35.95#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.174.01:28:35.95#ibcon#enter wrdev, iclass 31, count 2 2006.174.01:28:35.95#ibcon#first serial, iclass 31, count 2 2006.174.01:28:35.95#ibcon#enter sib2, iclass 31, count 2 2006.174.01:28:35.95#ibcon#flushed, iclass 31, count 2 2006.174.01:28:35.95#ibcon#about to write, iclass 31, count 2 2006.174.01:28:35.95#ibcon#wrote, iclass 31, count 2 2006.174.01:28:35.95#ibcon#about to read 3, iclass 31, count 2 2006.174.01:28:35.97#ibcon#read 3, iclass 31, count 2 2006.174.01:28:35.97#ibcon#about to read 4, iclass 31, count 2 2006.174.01:28:35.97#ibcon#read 4, iclass 31, count 2 2006.174.01:28:35.97#ibcon#about to read 5, iclass 31, count 2 2006.174.01:28:35.97#ibcon#read 5, iclass 31, count 2 2006.174.01:28:35.97#ibcon#about to read 6, iclass 31, count 2 2006.174.01:28:35.97#ibcon#read 6, iclass 31, count 2 2006.174.01:28:35.97#ibcon#end of sib2, iclass 31, count 2 2006.174.01:28:35.97#ibcon#*mode == 0, iclass 31, count 2 2006.174.01:28:35.97#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.174.01:28:35.97#ibcon#[25=AT03-05\r\n] 2006.174.01:28:35.97#ibcon#*before write, iclass 31, count 2 2006.174.01:28:35.97#ibcon#enter sib2, iclass 31, count 2 2006.174.01:28:35.97#ibcon#flushed, iclass 31, count 2 2006.174.01:28:35.97#ibcon#about to write, iclass 31, count 2 2006.174.01:28:35.97#ibcon#wrote, iclass 31, count 2 2006.174.01:28:35.97#ibcon#about to read 3, iclass 31, count 2 2006.174.01:28:36.00#ibcon#read 3, iclass 31, count 2 2006.174.01:28:36.00#ibcon#about to read 4, iclass 31, count 2 2006.174.01:28:36.00#ibcon#read 4, iclass 31, count 2 2006.174.01:28:36.00#ibcon#about to read 5, iclass 31, count 2 2006.174.01:28:36.00#ibcon#read 5, iclass 31, count 2 2006.174.01:28:36.00#ibcon#about to read 6, iclass 31, count 2 2006.174.01:28:36.00#ibcon#read 6, iclass 31, count 2 2006.174.01:28:36.00#ibcon#end of sib2, iclass 31, count 2 2006.174.01:28:36.00#ibcon#*after write, iclass 31, count 2 2006.174.01:28:36.00#ibcon#*before return 0, iclass 31, count 2 2006.174.01:28:36.00#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.174.01:28:36.00#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.174.01:28:36.00#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.174.01:28:36.00#ibcon#ireg 7 cls_cnt 0 2006.174.01:28:36.00#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.174.01:28:36.12#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.174.01:28:36.12#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.174.01:28:36.12#ibcon#enter wrdev, iclass 31, count 0 2006.174.01:28:36.12#ibcon#first serial, iclass 31, count 0 2006.174.01:28:36.12#ibcon#enter sib2, iclass 31, count 0 2006.174.01:28:36.12#ibcon#flushed, iclass 31, count 0 2006.174.01:28:36.12#ibcon#about to write, iclass 31, count 0 2006.174.01:28:36.12#ibcon#wrote, iclass 31, count 0 2006.174.01:28:36.12#ibcon#about to read 3, iclass 31, count 0 2006.174.01:28:36.14#ibcon#read 3, iclass 31, count 0 2006.174.01:28:36.14#ibcon#about to read 4, iclass 31, count 0 2006.174.01:28:36.14#ibcon#read 4, iclass 31, count 0 2006.174.01:28:36.14#ibcon#about to read 5, iclass 31, count 0 2006.174.01:28:36.14#ibcon#read 5, iclass 31, count 0 2006.174.01:28:36.14#ibcon#about to read 6, iclass 31, count 0 2006.174.01:28:36.14#ibcon#read 6, iclass 31, count 0 2006.174.01:28:36.14#ibcon#end of sib2, iclass 31, count 0 2006.174.01:28:36.14#ibcon#*mode == 0, iclass 31, count 0 2006.174.01:28:36.14#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.174.01:28:36.14#ibcon#[25=USB\r\n] 2006.174.01:28:36.14#ibcon#*before write, iclass 31, count 0 2006.174.01:28:36.14#ibcon#enter sib2, iclass 31, count 0 2006.174.01:28:36.14#ibcon#flushed, iclass 31, count 0 2006.174.01:28:36.14#ibcon#about to write, iclass 31, count 0 2006.174.01:28:36.14#ibcon#wrote, iclass 31, count 0 2006.174.01:28:36.14#ibcon#about to read 3, iclass 31, count 0 2006.174.01:28:36.17#ibcon#read 3, iclass 31, count 0 2006.174.01:28:36.17#ibcon#about to read 4, iclass 31, count 0 2006.174.01:28:36.17#ibcon#read 4, iclass 31, count 0 2006.174.01:28:36.17#ibcon#about to read 5, iclass 31, count 0 2006.174.01:28:36.17#ibcon#read 5, iclass 31, count 0 2006.174.01:28:36.17#ibcon#about to read 6, iclass 31, count 0 2006.174.01:28:36.17#ibcon#read 6, iclass 31, count 0 2006.174.01:28:36.17#ibcon#end of sib2, iclass 31, count 0 2006.174.01:28:36.17#ibcon#*after write, iclass 31, count 0 2006.174.01:28:36.17#ibcon#*before return 0, iclass 31, count 0 2006.174.01:28:36.17#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.174.01:28:36.17#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.174.01:28:36.17#ibcon#about to clear, iclass 31 cls_cnt 0 2006.174.01:28:36.17#ibcon#cleared, iclass 31 cls_cnt 0 2006.174.01:28:36.17$vck44/valo=4,624.99 2006.174.01:28:36.17#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.174.01:28:36.17#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.174.01:28:36.17#ibcon#ireg 17 cls_cnt 0 2006.174.01:28:36.17#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.174.01:28:36.17#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.174.01:28:36.17#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.174.01:28:36.17#ibcon#enter wrdev, iclass 33, count 0 2006.174.01:28:36.17#ibcon#first serial, iclass 33, count 0 2006.174.01:28:36.17#ibcon#enter sib2, iclass 33, count 0 2006.174.01:28:36.17#ibcon#flushed, iclass 33, count 0 2006.174.01:28:36.17#ibcon#about to write, iclass 33, count 0 2006.174.01:28:36.17#ibcon#wrote, iclass 33, count 0 2006.174.01:28:36.17#ibcon#about to read 3, iclass 33, count 0 2006.174.01:28:36.19#ibcon#read 3, iclass 33, count 0 2006.174.01:28:36.19#ibcon#about to read 4, iclass 33, count 0 2006.174.01:28:36.19#ibcon#read 4, iclass 33, count 0 2006.174.01:28:36.19#ibcon#about to read 5, iclass 33, count 0 2006.174.01:28:36.19#ibcon#read 5, iclass 33, count 0 2006.174.01:28:36.19#ibcon#about to read 6, iclass 33, count 0 2006.174.01:28:36.19#ibcon#read 6, iclass 33, count 0 2006.174.01:28:36.19#ibcon#end of sib2, iclass 33, count 0 2006.174.01:28:36.19#ibcon#*mode == 0, iclass 33, count 0 2006.174.01:28:36.19#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.174.01:28:36.19#ibcon#[26=FRQ=04,624.99\r\n] 2006.174.01:28:36.19#ibcon#*before write, iclass 33, count 0 2006.174.01:28:36.19#ibcon#enter sib2, iclass 33, count 0 2006.174.01:28:36.19#ibcon#flushed, iclass 33, count 0 2006.174.01:28:36.19#ibcon#about to write, iclass 33, count 0 2006.174.01:28:36.19#ibcon#wrote, iclass 33, count 0 2006.174.01:28:36.19#ibcon#about to read 3, iclass 33, count 0 2006.174.01:28:36.23#ibcon#read 3, iclass 33, count 0 2006.174.01:28:36.23#ibcon#about to read 4, iclass 33, count 0 2006.174.01:28:36.23#ibcon#read 4, iclass 33, count 0 2006.174.01:28:36.23#ibcon#about to read 5, iclass 33, count 0 2006.174.01:28:36.23#ibcon#read 5, iclass 33, count 0 2006.174.01:28:36.23#ibcon#about to read 6, iclass 33, count 0 2006.174.01:28:36.23#ibcon#read 6, iclass 33, count 0 2006.174.01:28:36.23#ibcon#end of sib2, iclass 33, count 0 2006.174.01:28:36.23#ibcon#*after write, iclass 33, count 0 2006.174.01:28:36.23#ibcon#*before return 0, iclass 33, count 0 2006.174.01:28:36.23#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.174.01:28:36.23#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.174.01:28:36.23#ibcon#about to clear, iclass 33 cls_cnt 0 2006.174.01:28:36.23#ibcon#cleared, iclass 33 cls_cnt 0 2006.174.01:28:36.23$vck44/va=4,6 2006.174.01:28:36.23#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.174.01:28:36.23#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.174.01:28:36.23#ibcon#ireg 11 cls_cnt 2 2006.174.01:28:36.23#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.174.01:28:36.29#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.174.01:28:36.29#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.174.01:28:36.29#ibcon#enter wrdev, iclass 35, count 2 2006.174.01:28:36.29#ibcon#first serial, iclass 35, count 2 2006.174.01:28:36.29#ibcon#enter sib2, iclass 35, count 2 2006.174.01:28:36.29#ibcon#flushed, iclass 35, count 2 2006.174.01:28:36.29#ibcon#about to write, iclass 35, count 2 2006.174.01:28:36.29#ibcon#wrote, iclass 35, count 2 2006.174.01:28:36.29#ibcon#about to read 3, iclass 35, count 2 2006.174.01:28:36.31#ibcon#read 3, iclass 35, count 2 2006.174.01:28:36.31#ibcon#about to read 4, iclass 35, count 2 2006.174.01:28:36.31#ibcon#read 4, iclass 35, count 2 2006.174.01:28:36.31#ibcon#about to read 5, iclass 35, count 2 2006.174.01:28:36.31#ibcon#read 5, iclass 35, count 2 2006.174.01:28:36.31#ibcon#about to read 6, iclass 35, count 2 2006.174.01:28:36.31#ibcon#read 6, iclass 35, count 2 2006.174.01:28:36.31#ibcon#end of sib2, iclass 35, count 2 2006.174.01:28:36.31#ibcon#*mode == 0, iclass 35, count 2 2006.174.01:28:36.31#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.174.01:28:36.31#ibcon#[25=AT04-06\r\n] 2006.174.01:28:36.31#ibcon#*before write, iclass 35, count 2 2006.174.01:28:36.31#ibcon#enter sib2, iclass 35, count 2 2006.174.01:28:36.31#ibcon#flushed, iclass 35, count 2 2006.174.01:28:36.31#ibcon#about to write, iclass 35, count 2 2006.174.01:28:36.31#ibcon#wrote, iclass 35, count 2 2006.174.01:28:36.31#ibcon#about to read 3, iclass 35, count 2 2006.174.01:28:36.34#ibcon#read 3, iclass 35, count 2 2006.174.01:28:36.34#ibcon#about to read 4, iclass 35, count 2 2006.174.01:28:36.34#ibcon#read 4, iclass 35, count 2 2006.174.01:28:36.34#ibcon#about to read 5, iclass 35, count 2 2006.174.01:28:36.34#ibcon#read 5, iclass 35, count 2 2006.174.01:28:36.34#ibcon#about to read 6, iclass 35, count 2 2006.174.01:28:36.34#ibcon#read 6, iclass 35, count 2 2006.174.01:28:36.34#ibcon#end of sib2, iclass 35, count 2 2006.174.01:28:36.34#ibcon#*after write, iclass 35, count 2 2006.174.01:28:36.34#ibcon#*before return 0, iclass 35, count 2 2006.174.01:28:36.34#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.174.01:28:36.34#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.174.01:28:36.34#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.174.01:28:36.34#ibcon#ireg 7 cls_cnt 0 2006.174.01:28:36.34#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.174.01:28:36.46#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.174.01:28:36.46#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.174.01:28:36.46#ibcon#enter wrdev, iclass 35, count 0 2006.174.01:28:36.46#ibcon#first serial, iclass 35, count 0 2006.174.01:28:36.46#ibcon#enter sib2, iclass 35, count 0 2006.174.01:28:36.46#ibcon#flushed, iclass 35, count 0 2006.174.01:28:36.46#ibcon#about to write, iclass 35, count 0 2006.174.01:28:36.46#ibcon#wrote, iclass 35, count 0 2006.174.01:28:36.46#ibcon#about to read 3, iclass 35, count 0 2006.174.01:28:36.48#ibcon#read 3, iclass 35, count 0 2006.174.01:28:36.48#ibcon#about to read 4, iclass 35, count 0 2006.174.01:28:36.48#ibcon#read 4, iclass 35, count 0 2006.174.01:28:36.48#ibcon#about to read 5, iclass 35, count 0 2006.174.01:28:36.48#ibcon#read 5, iclass 35, count 0 2006.174.01:28:36.48#ibcon#about to read 6, iclass 35, count 0 2006.174.01:28:36.48#ibcon#read 6, iclass 35, count 0 2006.174.01:28:36.48#ibcon#end of sib2, iclass 35, count 0 2006.174.01:28:36.48#ibcon#*mode == 0, iclass 35, count 0 2006.174.01:28:36.48#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.174.01:28:36.48#ibcon#[25=USB\r\n] 2006.174.01:28:36.48#ibcon#*before write, iclass 35, count 0 2006.174.01:28:36.48#ibcon#enter sib2, iclass 35, count 0 2006.174.01:28:36.48#ibcon#flushed, iclass 35, count 0 2006.174.01:28:36.48#ibcon#about to write, iclass 35, count 0 2006.174.01:28:36.48#ibcon#wrote, iclass 35, count 0 2006.174.01:28:36.48#ibcon#about to read 3, iclass 35, count 0 2006.174.01:28:36.51#ibcon#read 3, iclass 35, count 0 2006.174.01:28:36.51#ibcon#about to read 4, iclass 35, count 0 2006.174.01:28:36.51#ibcon#read 4, iclass 35, count 0 2006.174.01:28:36.51#ibcon#about to read 5, iclass 35, count 0 2006.174.01:28:36.51#ibcon#read 5, iclass 35, count 0 2006.174.01:28:36.51#ibcon#about to read 6, iclass 35, count 0 2006.174.01:28:36.51#ibcon#read 6, iclass 35, count 0 2006.174.01:28:36.51#ibcon#end of sib2, iclass 35, count 0 2006.174.01:28:36.51#ibcon#*after write, iclass 35, count 0 2006.174.01:28:36.51#ibcon#*before return 0, iclass 35, count 0 2006.174.01:28:36.51#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.174.01:28:36.51#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.174.01:28:36.51#ibcon#about to clear, iclass 35 cls_cnt 0 2006.174.01:28:36.51#ibcon#cleared, iclass 35 cls_cnt 0 2006.174.01:28:36.51$vck44/valo=5,734.99 2006.174.01:28:36.51#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.174.01:28:36.51#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.174.01:28:36.51#ibcon#ireg 17 cls_cnt 0 2006.174.01:28:36.51#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.174.01:28:36.51#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.174.01:28:36.51#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.174.01:28:36.51#ibcon#enter wrdev, iclass 37, count 0 2006.174.01:28:36.51#ibcon#first serial, iclass 37, count 0 2006.174.01:28:36.51#ibcon#enter sib2, iclass 37, count 0 2006.174.01:28:36.51#ibcon#flushed, iclass 37, count 0 2006.174.01:28:36.51#ibcon#about to write, iclass 37, count 0 2006.174.01:28:36.51#ibcon#wrote, iclass 37, count 0 2006.174.01:28:36.51#ibcon#about to read 3, iclass 37, count 0 2006.174.01:28:36.53#ibcon#read 3, iclass 37, count 0 2006.174.01:28:36.53#ibcon#about to read 4, iclass 37, count 0 2006.174.01:28:36.53#ibcon#read 4, iclass 37, count 0 2006.174.01:28:36.53#ibcon#about to read 5, iclass 37, count 0 2006.174.01:28:36.53#ibcon#read 5, iclass 37, count 0 2006.174.01:28:36.53#ibcon#about to read 6, iclass 37, count 0 2006.174.01:28:36.53#ibcon#read 6, iclass 37, count 0 2006.174.01:28:36.53#ibcon#end of sib2, iclass 37, count 0 2006.174.01:28:36.53#ibcon#*mode == 0, iclass 37, count 0 2006.174.01:28:36.53#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.174.01:28:36.53#ibcon#[26=FRQ=05,734.99\r\n] 2006.174.01:28:36.53#ibcon#*before write, iclass 37, count 0 2006.174.01:28:36.53#ibcon#enter sib2, iclass 37, count 0 2006.174.01:28:36.53#ibcon#flushed, iclass 37, count 0 2006.174.01:28:36.53#ibcon#about to write, iclass 37, count 0 2006.174.01:28:36.53#ibcon#wrote, iclass 37, count 0 2006.174.01:28:36.53#ibcon#about to read 3, iclass 37, count 0 2006.174.01:28:36.57#ibcon#read 3, iclass 37, count 0 2006.174.01:28:36.57#ibcon#about to read 4, iclass 37, count 0 2006.174.01:28:36.57#ibcon#read 4, iclass 37, count 0 2006.174.01:28:36.57#ibcon#about to read 5, iclass 37, count 0 2006.174.01:28:36.57#ibcon#read 5, iclass 37, count 0 2006.174.01:28:36.57#ibcon#about to read 6, iclass 37, count 0 2006.174.01:28:36.57#ibcon#read 6, iclass 37, count 0 2006.174.01:28:36.57#ibcon#end of sib2, iclass 37, count 0 2006.174.01:28:36.57#ibcon#*after write, iclass 37, count 0 2006.174.01:28:36.57#ibcon#*before return 0, iclass 37, count 0 2006.174.01:28:36.57#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.174.01:28:36.57#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.174.01:28:36.57#ibcon#about to clear, iclass 37 cls_cnt 0 2006.174.01:28:36.57#ibcon#cleared, iclass 37 cls_cnt 0 2006.174.01:28:36.57$vck44/va=5,4 2006.174.01:28:36.57#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.174.01:28:36.57#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.174.01:28:36.57#ibcon#ireg 11 cls_cnt 2 2006.174.01:28:36.57#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.174.01:28:36.63#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.174.01:28:36.63#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.174.01:28:36.63#ibcon#enter wrdev, iclass 39, count 2 2006.174.01:28:36.63#ibcon#first serial, iclass 39, count 2 2006.174.01:28:36.63#ibcon#enter sib2, iclass 39, count 2 2006.174.01:28:36.63#ibcon#flushed, iclass 39, count 2 2006.174.01:28:36.63#ibcon#about to write, iclass 39, count 2 2006.174.01:28:36.63#ibcon#wrote, iclass 39, count 2 2006.174.01:28:36.63#ibcon#about to read 3, iclass 39, count 2 2006.174.01:28:36.65#ibcon#read 3, iclass 39, count 2 2006.174.01:28:36.65#ibcon#about to read 4, iclass 39, count 2 2006.174.01:28:36.65#ibcon#read 4, iclass 39, count 2 2006.174.01:28:36.65#ibcon#about to read 5, iclass 39, count 2 2006.174.01:28:36.65#ibcon#read 5, iclass 39, count 2 2006.174.01:28:36.65#ibcon#about to read 6, iclass 39, count 2 2006.174.01:28:36.65#ibcon#read 6, iclass 39, count 2 2006.174.01:28:36.65#ibcon#end of sib2, iclass 39, count 2 2006.174.01:28:36.65#ibcon#*mode == 0, iclass 39, count 2 2006.174.01:28:36.65#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.174.01:28:36.65#ibcon#[25=AT05-04\r\n] 2006.174.01:28:36.65#ibcon#*before write, iclass 39, count 2 2006.174.01:28:36.65#ibcon#enter sib2, iclass 39, count 2 2006.174.01:28:36.65#ibcon#flushed, iclass 39, count 2 2006.174.01:28:36.65#ibcon#about to write, iclass 39, count 2 2006.174.01:28:36.65#ibcon#wrote, iclass 39, count 2 2006.174.01:28:36.65#ibcon#about to read 3, iclass 39, count 2 2006.174.01:28:36.68#ibcon#read 3, iclass 39, count 2 2006.174.01:28:36.68#ibcon#about to read 4, iclass 39, count 2 2006.174.01:28:36.68#ibcon#read 4, iclass 39, count 2 2006.174.01:28:36.68#ibcon#about to read 5, iclass 39, count 2 2006.174.01:28:36.68#ibcon#read 5, iclass 39, count 2 2006.174.01:28:36.68#ibcon#about to read 6, iclass 39, count 2 2006.174.01:28:36.68#ibcon#read 6, iclass 39, count 2 2006.174.01:28:36.68#ibcon#end of sib2, iclass 39, count 2 2006.174.01:28:36.68#ibcon#*after write, iclass 39, count 2 2006.174.01:28:36.68#ibcon#*before return 0, iclass 39, count 2 2006.174.01:28:36.68#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.174.01:28:36.68#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.174.01:28:36.68#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.174.01:28:36.68#ibcon#ireg 7 cls_cnt 0 2006.174.01:28:36.68#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.174.01:28:36.80#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.174.01:28:36.80#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.174.01:28:36.80#ibcon#enter wrdev, iclass 39, count 0 2006.174.01:28:36.80#ibcon#first serial, iclass 39, count 0 2006.174.01:28:36.80#ibcon#enter sib2, iclass 39, count 0 2006.174.01:28:36.80#ibcon#flushed, iclass 39, count 0 2006.174.01:28:36.80#ibcon#about to write, iclass 39, count 0 2006.174.01:28:36.80#ibcon#wrote, iclass 39, count 0 2006.174.01:28:36.80#ibcon#about to read 3, iclass 39, count 0 2006.174.01:28:36.82#ibcon#read 3, iclass 39, count 0 2006.174.01:28:36.82#ibcon#about to read 4, iclass 39, count 0 2006.174.01:28:36.82#ibcon#read 4, iclass 39, count 0 2006.174.01:28:36.82#ibcon#about to read 5, iclass 39, count 0 2006.174.01:28:36.82#ibcon#read 5, iclass 39, count 0 2006.174.01:28:36.82#ibcon#about to read 6, iclass 39, count 0 2006.174.01:28:36.82#ibcon#read 6, iclass 39, count 0 2006.174.01:28:36.82#ibcon#end of sib2, iclass 39, count 0 2006.174.01:28:36.82#ibcon#*mode == 0, iclass 39, count 0 2006.174.01:28:36.82#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.174.01:28:36.82#ibcon#[25=USB\r\n] 2006.174.01:28:36.82#ibcon#*before write, iclass 39, count 0 2006.174.01:28:36.82#ibcon#enter sib2, iclass 39, count 0 2006.174.01:28:36.82#ibcon#flushed, iclass 39, count 0 2006.174.01:28:36.82#ibcon#about to write, iclass 39, count 0 2006.174.01:28:36.82#ibcon#wrote, iclass 39, count 0 2006.174.01:28:36.82#ibcon#about to read 3, iclass 39, count 0 2006.174.01:28:36.85#ibcon#read 3, iclass 39, count 0 2006.174.01:28:36.85#ibcon#about to read 4, iclass 39, count 0 2006.174.01:28:36.85#ibcon#read 4, iclass 39, count 0 2006.174.01:28:36.85#ibcon#about to read 5, iclass 39, count 0 2006.174.01:28:36.85#ibcon#read 5, iclass 39, count 0 2006.174.01:28:36.85#ibcon#about to read 6, iclass 39, count 0 2006.174.01:28:36.85#ibcon#read 6, iclass 39, count 0 2006.174.01:28:36.85#ibcon#end of sib2, iclass 39, count 0 2006.174.01:28:36.85#ibcon#*after write, iclass 39, count 0 2006.174.01:28:36.85#ibcon#*before return 0, iclass 39, count 0 2006.174.01:28:36.85#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.174.01:28:36.85#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.174.01:28:36.85#ibcon#about to clear, iclass 39 cls_cnt 0 2006.174.01:28:36.85#ibcon#cleared, iclass 39 cls_cnt 0 2006.174.01:28:36.85$vck44/valo=6,814.99 2006.174.01:28:36.85#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.174.01:28:36.85#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.174.01:28:36.85#ibcon#ireg 17 cls_cnt 0 2006.174.01:28:36.85#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.174.01:28:36.85#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.174.01:28:36.85#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.174.01:28:36.85#ibcon#enter wrdev, iclass 3, count 0 2006.174.01:28:36.85#ibcon#first serial, iclass 3, count 0 2006.174.01:28:36.85#ibcon#enter sib2, iclass 3, count 0 2006.174.01:28:36.85#ibcon#flushed, iclass 3, count 0 2006.174.01:28:36.85#ibcon#about to write, iclass 3, count 0 2006.174.01:28:36.85#ibcon#wrote, iclass 3, count 0 2006.174.01:28:36.85#ibcon#about to read 3, iclass 3, count 0 2006.174.01:28:36.87#ibcon#read 3, iclass 3, count 0 2006.174.01:28:36.87#ibcon#about to read 4, iclass 3, count 0 2006.174.01:28:36.87#ibcon#read 4, iclass 3, count 0 2006.174.01:28:36.87#ibcon#about to read 5, iclass 3, count 0 2006.174.01:28:36.87#ibcon#read 5, iclass 3, count 0 2006.174.01:28:36.87#ibcon#about to read 6, iclass 3, count 0 2006.174.01:28:36.87#ibcon#read 6, iclass 3, count 0 2006.174.01:28:36.87#ibcon#end of sib2, iclass 3, count 0 2006.174.01:28:36.87#ibcon#*mode == 0, iclass 3, count 0 2006.174.01:28:36.87#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.174.01:28:36.87#ibcon#[26=FRQ=06,814.99\r\n] 2006.174.01:28:36.87#ibcon#*before write, iclass 3, count 0 2006.174.01:28:36.87#ibcon#enter sib2, iclass 3, count 0 2006.174.01:28:36.87#ibcon#flushed, iclass 3, count 0 2006.174.01:28:36.87#ibcon#about to write, iclass 3, count 0 2006.174.01:28:36.87#ibcon#wrote, iclass 3, count 0 2006.174.01:28:36.87#ibcon#about to read 3, iclass 3, count 0 2006.174.01:28:36.91#ibcon#read 3, iclass 3, count 0 2006.174.01:28:36.91#ibcon#about to read 4, iclass 3, count 0 2006.174.01:28:36.91#ibcon#read 4, iclass 3, count 0 2006.174.01:28:36.91#ibcon#about to read 5, iclass 3, count 0 2006.174.01:28:36.91#ibcon#read 5, iclass 3, count 0 2006.174.01:28:36.91#ibcon#about to read 6, iclass 3, count 0 2006.174.01:28:36.91#ibcon#read 6, iclass 3, count 0 2006.174.01:28:36.91#ibcon#end of sib2, iclass 3, count 0 2006.174.01:28:36.91#ibcon#*after write, iclass 3, count 0 2006.174.01:28:36.91#ibcon#*before return 0, iclass 3, count 0 2006.174.01:28:36.91#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.174.01:28:36.91#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.174.01:28:36.91#ibcon#about to clear, iclass 3 cls_cnt 0 2006.174.01:28:36.91#ibcon#cleared, iclass 3 cls_cnt 0 2006.174.01:28:36.91$vck44/va=6,3 2006.174.01:28:36.91#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.174.01:28:36.91#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.174.01:28:36.91#ibcon#ireg 11 cls_cnt 2 2006.174.01:28:36.91#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.174.01:28:36.97#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.174.01:28:36.97#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.174.01:28:36.97#ibcon#enter wrdev, iclass 5, count 2 2006.174.01:28:36.97#ibcon#first serial, iclass 5, count 2 2006.174.01:28:36.97#ibcon#enter sib2, iclass 5, count 2 2006.174.01:28:36.97#ibcon#flushed, iclass 5, count 2 2006.174.01:28:36.97#ibcon#about to write, iclass 5, count 2 2006.174.01:28:36.97#ibcon#wrote, iclass 5, count 2 2006.174.01:28:36.97#ibcon#about to read 3, iclass 5, count 2 2006.174.01:28:36.99#ibcon#read 3, iclass 5, count 2 2006.174.01:28:36.99#ibcon#about to read 4, iclass 5, count 2 2006.174.01:28:36.99#ibcon#read 4, iclass 5, count 2 2006.174.01:28:36.99#ibcon#about to read 5, iclass 5, count 2 2006.174.01:28:36.99#ibcon#read 5, iclass 5, count 2 2006.174.01:28:36.99#ibcon#about to read 6, iclass 5, count 2 2006.174.01:28:36.99#ibcon#read 6, iclass 5, count 2 2006.174.01:28:36.99#ibcon#end of sib2, iclass 5, count 2 2006.174.01:28:36.99#ibcon#*mode == 0, iclass 5, count 2 2006.174.01:28:36.99#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.174.01:28:36.99#ibcon#[25=AT06-03\r\n] 2006.174.01:28:36.99#ibcon#*before write, iclass 5, count 2 2006.174.01:28:36.99#ibcon#enter sib2, iclass 5, count 2 2006.174.01:28:36.99#ibcon#flushed, iclass 5, count 2 2006.174.01:28:36.99#ibcon#about to write, iclass 5, count 2 2006.174.01:28:36.99#ibcon#wrote, iclass 5, count 2 2006.174.01:28:36.99#ibcon#about to read 3, iclass 5, count 2 2006.174.01:28:37.02#ibcon#read 3, iclass 5, count 2 2006.174.01:28:37.02#ibcon#about to read 4, iclass 5, count 2 2006.174.01:28:37.02#ibcon#read 4, iclass 5, count 2 2006.174.01:28:37.02#ibcon#about to read 5, iclass 5, count 2 2006.174.01:28:37.02#ibcon#read 5, iclass 5, count 2 2006.174.01:28:37.02#ibcon#about to read 6, iclass 5, count 2 2006.174.01:28:37.02#ibcon#read 6, iclass 5, count 2 2006.174.01:28:37.02#ibcon#end of sib2, iclass 5, count 2 2006.174.01:28:37.02#ibcon#*after write, iclass 5, count 2 2006.174.01:28:37.02#ibcon#*before return 0, iclass 5, count 2 2006.174.01:28:37.02#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.174.01:28:37.02#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.174.01:28:37.02#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.174.01:28:37.02#ibcon#ireg 7 cls_cnt 0 2006.174.01:28:37.02#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.174.01:28:37.14#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.174.01:28:37.14#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.174.01:28:37.14#ibcon#enter wrdev, iclass 5, count 0 2006.174.01:28:37.14#ibcon#first serial, iclass 5, count 0 2006.174.01:28:37.14#ibcon#enter sib2, iclass 5, count 0 2006.174.01:28:37.14#ibcon#flushed, iclass 5, count 0 2006.174.01:28:37.14#ibcon#about to write, iclass 5, count 0 2006.174.01:28:37.14#ibcon#wrote, iclass 5, count 0 2006.174.01:28:37.14#ibcon#about to read 3, iclass 5, count 0 2006.174.01:28:37.16#ibcon#read 3, iclass 5, count 0 2006.174.01:28:37.16#ibcon#about to read 4, iclass 5, count 0 2006.174.01:28:37.16#ibcon#read 4, iclass 5, count 0 2006.174.01:28:37.16#ibcon#about to read 5, iclass 5, count 0 2006.174.01:28:37.16#ibcon#read 5, iclass 5, count 0 2006.174.01:28:37.16#ibcon#about to read 6, iclass 5, count 0 2006.174.01:28:37.16#ibcon#read 6, iclass 5, count 0 2006.174.01:28:37.16#ibcon#end of sib2, iclass 5, count 0 2006.174.01:28:37.16#ibcon#*mode == 0, iclass 5, count 0 2006.174.01:28:37.16#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.174.01:28:37.16#ibcon#[25=USB\r\n] 2006.174.01:28:37.16#ibcon#*before write, iclass 5, count 0 2006.174.01:28:37.16#ibcon#enter sib2, iclass 5, count 0 2006.174.01:28:37.16#ibcon#flushed, iclass 5, count 0 2006.174.01:28:37.16#ibcon#about to write, iclass 5, count 0 2006.174.01:28:37.16#ibcon#wrote, iclass 5, count 0 2006.174.01:28:37.16#ibcon#about to read 3, iclass 5, count 0 2006.174.01:28:37.19#ibcon#read 3, iclass 5, count 0 2006.174.01:28:37.19#ibcon#about to read 4, iclass 5, count 0 2006.174.01:28:37.19#ibcon#read 4, iclass 5, count 0 2006.174.01:28:37.19#ibcon#about to read 5, iclass 5, count 0 2006.174.01:28:37.19#ibcon#read 5, iclass 5, count 0 2006.174.01:28:37.19#ibcon#about to read 6, iclass 5, count 0 2006.174.01:28:37.19#ibcon#read 6, iclass 5, count 0 2006.174.01:28:37.19#ibcon#end of sib2, iclass 5, count 0 2006.174.01:28:37.19#ibcon#*after write, iclass 5, count 0 2006.174.01:28:37.19#ibcon#*before return 0, iclass 5, count 0 2006.174.01:28:37.19#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.174.01:28:37.19#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.174.01:28:37.19#ibcon#about to clear, iclass 5 cls_cnt 0 2006.174.01:28:37.19#ibcon#cleared, iclass 5 cls_cnt 0 2006.174.01:28:37.19$vck44/valo=7,864.99 2006.174.01:28:37.19#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.174.01:28:37.19#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.174.01:28:37.19#ibcon#ireg 17 cls_cnt 0 2006.174.01:28:37.19#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.174.01:28:37.19#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.174.01:28:37.19#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.174.01:28:37.19#ibcon#enter wrdev, iclass 7, count 0 2006.174.01:28:37.19#ibcon#first serial, iclass 7, count 0 2006.174.01:28:37.19#ibcon#enter sib2, iclass 7, count 0 2006.174.01:28:37.19#ibcon#flushed, iclass 7, count 0 2006.174.01:28:37.19#ibcon#about to write, iclass 7, count 0 2006.174.01:28:37.19#ibcon#wrote, iclass 7, count 0 2006.174.01:28:37.19#ibcon#about to read 3, iclass 7, count 0 2006.174.01:28:37.21#ibcon#read 3, iclass 7, count 0 2006.174.01:28:37.21#ibcon#about to read 4, iclass 7, count 0 2006.174.01:28:37.21#ibcon#read 4, iclass 7, count 0 2006.174.01:28:37.21#ibcon#about to read 5, iclass 7, count 0 2006.174.01:28:37.21#ibcon#read 5, iclass 7, count 0 2006.174.01:28:37.21#ibcon#about to read 6, iclass 7, count 0 2006.174.01:28:37.21#ibcon#read 6, iclass 7, count 0 2006.174.01:28:37.21#ibcon#end of sib2, iclass 7, count 0 2006.174.01:28:37.21#ibcon#*mode == 0, iclass 7, count 0 2006.174.01:28:37.21#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.174.01:28:37.21#ibcon#[26=FRQ=07,864.99\r\n] 2006.174.01:28:37.21#ibcon#*before write, iclass 7, count 0 2006.174.01:28:37.21#ibcon#enter sib2, iclass 7, count 0 2006.174.01:28:37.21#ibcon#flushed, iclass 7, count 0 2006.174.01:28:37.21#ibcon#about to write, iclass 7, count 0 2006.174.01:28:37.21#ibcon#wrote, iclass 7, count 0 2006.174.01:28:37.21#ibcon#about to read 3, iclass 7, count 0 2006.174.01:28:37.25#ibcon#read 3, iclass 7, count 0 2006.174.01:28:37.25#ibcon#about to read 4, iclass 7, count 0 2006.174.01:28:37.25#ibcon#read 4, iclass 7, count 0 2006.174.01:28:37.25#ibcon#about to read 5, iclass 7, count 0 2006.174.01:28:37.25#ibcon#read 5, iclass 7, count 0 2006.174.01:28:37.25#ibcon#about to read 6, iclass 7, count 0 2006.174.01:28:37.25#ibcon#read 6, iclass 7, count 0 2006.174.01:28:37.25#ibcon#end of sib2, iclass 7, count 0 2006.174.01:28:37.25#ibcon#*after write, iclass 7, count 0 2006.174.01:28:37.25#ibcon#*before return 0, iclass 7, count 0 2006.174.01:28:37.25#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.174.01:28:37.25#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.174.01:28:37.25#ibcon#about to clear, iclass 7 cls_cnt 0 2006.174.01:28:37.25#ibcon#cleared, iclass 7 cls_cnt 0 2006.174.01:28:37.25$vck44/va=7,4 2006.174.01:28:37.25#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.174.01:28:37.25#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.174.01:28:37.25#ibcon#ireg 11 cls_cnt 2 2006.174.01:28:37.25#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.174.01:28:37.31#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.174.01:28:37.31#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.174.01:28:37.31#ibcon#enter wrdev, iclass 11, count 2 2006.174.01:28:37.31#ibcon#first serial, iclass 11, count 2 2006.174.01:28:37.31#ibcon#enter sib2, iclass 11, count 2 2006.174.01:28:37.31#ibcon#flushed, iclass 11, count 2 2006.174.01:28:37.31#ibcon#about to write, iclass 11, count 2 2006.174.01:28:37.31#ibcon#wrote, iclass 11, count 2 2006.174.01:28:37.31#ibcon#about to read 3, iclass 11, count 2 2006.174.01:28:37.33#ibcon#read 3, iclass 11, count 2 2006.174.01:28:37.33#ibcon#about to read 4, iclass 11, count 2 2006.174.01:28:37.33#ibcon#read 4, iclass 11, count 2 2006.174.01:28:37.33#ibcon#about to read 5, iclass 11, count 2 2006.174.01:28:37.33#ibcon#read 5, iclass 11, count 2 2006.174.01:28:37.33#ibcon#about to read 6, iclass 11, count 2 2006.174.01:28:37.33#ibcon#read 6, iclass 11, count 2 2006.174.01:28:37.33#ibcon#end of sib2, iclass 11, count 2 2006.174.01:28:37.33#ibcon#*mode == 0, iclass 11, count 2 2006.174.01:28:37.33#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.174.01:28:37.33#ibcon#[25=AT07-04\r\n] 2006.174.01:28:37.33#ibcon#*before write, iclass 11, count 2 2006.174.01:28:37.33#ibcon#enter sib2, iclass 11, count 2 2006.174.01:28:37.33#ibcon#flushed, iclass 11, count 2 2006.174.01:28:37.33#ibcon#about to write, iclass 11, count 2 2006.174.01:28:37.33#ibcon#wrote, iclass 11, count 2 2006.174.01:28:37.33#ibcon#about to read 3, iclass 11, count 2 2006.174.01:28:37.36#ibcon#read 3, iclass 11, count 2 2006.174.01:28:37.36#ibcon#about to read 4, iclass 11, count 2 2006.174.01:28:37.36#ibcon#read 4, iclass 11, count 2 2006.174.01:28:37.36#ibcon#about to read 5, iclass 11, count 2 2006.174.01:28:37.36#ibcon#read 5, iclass 11, count 2 2006.174.01:28:37.36#ibcon#about to read 6, iclass 11, count 2 2006.174.01:28:37.36#ibcon#read 6, iclass 11, count 2 2006.174.01:28:37.36#ibcon#end of sib2, iclass 11, count 2 2006.174.01:28:37.36#ibcon#*after write, iclass 11, count 2 2006.174.01:28:37.36#ibcon#*before return 0, iclass 11, count 2 2006.174.01:28:37.36#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.174.01:28:37.36#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.174.01:28:37.36#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.174.01:28:37.36#ibcon#ireg 7 cls_cnt 0 2006.174.01:28:37.36#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.174.01:28:37.48#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.174.01:28:37.48#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.174.01:28:37.48#ibcon#enter wrdev, iclass 11, count 0 2006.174.01:28:37.48#ibcon#first serial, iclass 11, count 0 2006.174.01:28:37.48#ibcon#enter sib2, iclass 11, count 0 2006.174.01:28:37.48#ibcon#flushed, iclass 11, count 0 2006.174.01:28:37.48#ibcon#about to write, iclass 11, count 0 2006.174.01:28:37.48#ibcon#wrote, iclass 11, count 0 2006.174.01:28:37.48#ibcon#about to read 3, iclass 11, count 0 2006.174.01:28:37.50#ibcon#read 3, iclass 11, count 0 2006.174.01:28:37.50#ibcon#about to read 4, iclass 11, count 0 2006.174.01:28:37.50#ibcon#read 4, iclass 11, count 0 2006.174.01:28:37.50#ibcon#about to read 5, iclass 11, count 0 2006.174.01:28:37.50#ibcon#read 5, iclass 11, count 0 2006.174.01:28:37.50#ibcon#about to read 6, iclass 11, count 0 2006.174.01:28:37.50#ibcon#read 6, iclass 11, count 0 2006.174.01:28:37.50#ibcon#end of sib2, iclass 11, count 0 2006.174.01:28:37.50#ibcon#*mode == 0, iclass 11, count 0 2006.174.01:28:37.50#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.174.01:28:37.50#ibcon#[25=USB\r\n] 2006.174.01:28:37.50#ibcon#*before write, iclass 11, count 0 2006.174.01:28:37.50#ibcon#enter sib2, iclass 11, count 0 2006.174.01:28:37.50#ibcon#flushed, iclass 11, count 0 2006.174.01:28:37.50#ibcon#about to write, iclass 11, count 0 2006.174.01:28:37.50#ibcon#wrote, iclass 11, count 0 2006.174.01:28:37.50#ibcon#about to read 3, iclass 11, count 0 2006.174.01:28:37.53#ibcon#read 3, iclass 11, count 0 2006.174.01:28:37.53#ibcon#about to read 4, iclass 11, count 0 2006.174.01:28:37.53#ibcon#read 4, iclass 11, count 0 2006.174.01:28:37.53#ibcon#about to read 5, iclass 11, count 0 2006.174.01:28:37.53#ibcon#read 5, iclass 11, count 0 2006.174.01:28:37.53#ibcon#about to read 6, iclass 11, count 0 2006.174.01:28:37.53#ibcon#read 6, iclass 11, count 0 2006.174.01:28:37.53#ibcon#end of sib2, iclass 11, count 0 2006.174.01:28:37.53#ibcon#*after write, iclass 11, count 0 2006.174.01:28:37.53#ibcon#*before return 0, iclass 11, count 0 2006.174.01:28:37.53#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.174.01:28:37.53#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.174.01:28:37.53#ibcon#about to clear, iclass 11 cls_cnt 0 2006.174.01:28:37.53#ibcon#cleared, iclass 11 cls_cnt 0 2006.174.01:28:37.53$vck44/valo=8,884.99 2006.174.01:28:37.53#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.174.01:28:37.53#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.174.01:28:37.53#ibcon#ireg 17 cls_cnt 0 2006.174.01:28:37.53#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.174.01:28:37.53#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.174.01:28:37.53#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.174.01:28:37.53#ibcon#enter wrdev, iclass 13, count 0 2006.174.01:28:37.53#ibcon#first serial, iclass 13, count 0 2006.174.01:28:37.53#ibcon#enter sib2, iclass 13, count 0 2006.174.01:28:37.53#ibcon#flushed, iclass 13, count 0 2006.174.01:28:37.53#ibcon#about to write, iclass 13, count 0 2006.174.01:28:37.53#ibcon#wrote, iclass 13, count 0 2006.174.01:28:37.53#ibcon#about to read 3, iclass 13, count 0 2006.174.01:28:37.55#ibcon#read 3, iclass 13, count 0 2006.174.01:28:37.55#ibcon#about to read 4, iclass 13, count 0 2006.174.01:28:37.55#ibcon#read 4, iclass 13, count 0 2006.174.01:28:37.55#ibcon#about to read 5, iclass 13, count 0 2006.174.01:28:37.55#ibcon#read 5, iclass 13, count 0 2006.174.01:28:37.55#ibcon#about to read 6, iclass 13, count 0 2006.174.01:28:37.55#ibcon#read 6, iclass 13, count 0 2006.174.01:28:37.55#ibcon#end of sib2, iclass 13, count 0 2006.174.01:28:37.55#ibcon#*mode == 0, iclass 13, count 0 2006.174.01:28:37.55#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.174.01:28:37.55#ibcon#[26=FRQ=08,884.99\r\n] 2006.174.01:28:37.55#ibcon#*before write, iclass 13, count 0 2006.174.01:28:37.55#ibcon#enter sib2, iclass 13, count 0 2006.174.01:28:37.55#ibcon#flushed, iclass 13, count 0 2006.174.01:28:37.55#ibcon#about to write, iclass 13, count 0 2006.174.01:28:37.55#ibcon#wrote, iclass 13, count 0 2006.174.01:28:37.55#ibcon#about to read 3, iclass 13, count 0 2006.174.01:28:37.59#ibcon#read 3, iclass 13, count 0 2006.174.01:28:37.59#ibcon#about to read 4, iclass 13, count 0 2006.174.01:28:37.59#ibcon#read 4, iclass 13, count 0 2006.174.01:28:37.59#ibcon#about to read 5, iclass 13, count 0 2006.174.01:28:37.59#ibcon#read 5, iclass 13, count 0 2006.174.01:28:37.59#ibcon#about to read 6, iclass 13, count 0 2006.174.01:28:37.59#ibcon#read 6, iclass 13, count 0 2006.174.01:28:37.59#ibcon#end of sib2, iclass 13, count 0 2006.174.01:28:37.59#ibcon#*after write, iclass 13, count 0 2006.174.01:28:37.59#ibcon#*before return 0, iclass 13, count 0 2006.174.01:28:37.59#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.174.01:28:37.59#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.174.01:28:37.59#ibcon#about to clear, iclass 13 cls_cnt 0 2006.174.01:28:37.59#ibcon#cleared, iclass 13 cls_cnt 0 2006.174.01:28:37.59$vck44/va=8,4 2006.174.01:28:37.59#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.174.01:28:37.59#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.174.01:28:37.59#ibcon#ireg 11 cls_cnt 2 2006.174.01:28:37.59#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.174.01:28:37.65#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.174.01:28:37.65#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.174.01:28:37.65#ibcon#enter wrdev, iclass 15, count 2 2006.174.01:28:37.65#ibcon#first serial, iclass 15, count 2 2006.174.01:28:37.65#ibcon#enter sib2, iclass 15, count 2 2006.174.01:28:37.65#ibcon#flushed, iclass 15, count 2 2006.174.01:28:37.65#ibcon#about to write, iclass 15, count 2 2006.174.01:28:37.65#ibcon#wrote, iclass 15, count 2 2006.174.01:28:37.65#ibcon#about to read 3, iclass 15, count 2 2006.174.01:28:37.67#ibcon#read 3, iclass 15, count 2 2006.174.01:28:37.67#ibcon#about to read 4, iclass 15, count 2 2006.174.01:28:37.67#ibcon#read 4, iclass 15, count 2 2006.174.01:28:37.67#ibcon#about to read 5, iclass 15, count 2 2006.174.01:28:37.67#ibcon#read 5, iclass 15, count 2 2006.174.01:28:37.67#ibcon#about to read 6, iclass 15, count 2 2006.174.01:28:37.67#ibcon#read 6, iclass 15, count 2 2006.174.01:28:37.67#ibcon#end of sib2, iclass 15, count 2 2006.174.01:28:37.67#ibcon#*mode == 0, iclass 15, count 2 2006.174.01:28:37.67#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.174.01:28:37.67#ibcon#[25=AT08-04\r\n] 2006.174.01:28:37.67#ibcon#*before write, iclass 15, count 2 2006.174.01:28:37.67#ibcon#enter sib2, iclass 15, count 2 2006.174.01:28:37.67#ibcon#flushed, iclass 15, count 2 2006.174.01:28:37.67#ibcon#about to write, iclass 15, count 2 2006.174.01:28:37.67#ibcon#wrote, iclass 15, count 2 2006.174.01:28:37.67#ibcon#about to read 3, iclass 15, count 2 2006.174.01:28:37.70#ibcon#read 3, iclass 15, count 2 2006.174.01:28:37.70#ibcon#about to read 4, iclass 15, count 2 2006.174.01:28:37.70#ibcon#read 4, iclass 15, count 2 2006.174.01:28:37.70#ibcon#about to read 5, iclass 15, count 2 2006.174.01:28:37.70#ibcon#read 5, iclass 15, count 2 2006.174.01:28:37.70#ibcon#about to read 6, iclass 15, count 2 2006.174.01:28:37.70#ibcon#read 6, iclass 15, count 2 2006.174.01:28:37.70#ibcon#end of sib2, iclass 15, count 2 2006.174.01:28:37.70#ibcon#*after write, iclass 15, count 2 2006.174.01:28:37.70#ibcon#*before return 0, iclass 15, count 2 2006.174.01:28:37.70#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.174.01:28:37.70#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.174.01:28:37.70#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.174.01:28:37.70#ibcon#ireg 7 cls_cnt 0 2006.174.01:28:37.70#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.174.01:28:37.82#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.174.01:28:37.82#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.174.01:28:37.82#ibcon#enter wrdev, iclass 15, count 0 2006.174.01:28:37.82#ibcon#first serial, iclass 15, count 0 2006.174.01:28:37.82#ibcon#enter sib2, iclass 15, count 0 2006.174.01:28:37.82#ibcon#flushed, iclass 15, count 0 2006.174.01:28:37.82#ibcon#about to write, iclass 15, count 0 2006.174.01:28:37.82#ibcon#wrote, iclass 15, count 0 2006.174.01:28:37.82#ibcon#about to read 3, iclass 15, count 0 2006.174.01:28:37.84#ibcon#read 3, iclass 15, count 0 2006.174.01:28:37.84#ibcon#about to read 4, iclass 15, count 0 2006.174.01:28:37.84#ibcon#read 4, iclass 15, count 0 2006.174.01:28:37.84#ibcon#about to read 5, iclass 15, count 0 2006.174.01:28:37.84#ibcon#read 5, iclass 15, count 0 2006.174.01:28:37.84#ibcon#about to read 6, iclass 15, count 0 2006.174.01:28:37.84#ibcon#read 6, iclass 15, count 0 2006.174.01:28:37.84#ibcon#end of sib2, iclass 15, count 0 2006.174.01:28:37.84#ibcon#*mode == 0, iclass 15, count 0 2006.174.01:28:37.84#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.174.01:28:37.84#ibcon#[25=USB\r\n] 2006.174.01:28:37.84#ibcon#*before write, iclass 15, count 0 2006.174.01:28:37.84#ibcon#enter sib2, iclass 15, count 0 2006.174.01:28:37.84#ibcon#flushed, iclass 15, count 0 2006.174.01:28:37.84#ibcon#about to write, iclass 15, count 0 2006.174.01:28:37.84#ibcon#wrote, iclass 15, count 0 2006.174.01:28:37.84#ibcon#about to read 3, iclass 15, count 0 2006.174.01:28:37.87#ibcon#read 3, iclass 15, count 0 2006.174.01:28:37.87#ibcon#about to read 4, iclass 15, count 0 2006.174.01:28:37.87#ibcon#read 4, iclass 15, count 0 2006.174.01:28:37.87#ibcon#about to read 5, iclass 15, count 0 2006.174.01:28:37.87#ibcon#read 5, iclass 15, count 0 2006.174.01:28:37.87#ibcon#about to read 6, iclass 15, count 0 2006.174.01:28:37.87#ibcon#read 6, iclass 15, count 0 2006.174.01:28:37.87#ibcon#end of sib2, iclass 15, count 0 2006.174.01:28:37.87#ibcon#*after write, iclass 15, count 0 2006.174.01:28:37.87#ibcon#*before return 0, iclass 15, count 0 2006.174.01:28:37.87#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.174.01:28:37.87#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.174.01:28:37.87#ibcon#about to clear, iclass 15 cls_cnt 0 2006.174.01:28:37.87#ibcon#cleared, iclass 15 cls_cnt 0 2006.174.01:28:37.87$vck44/vblo=1,629.99 2006.174.01:28:37.87#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.174.01:28:37.87#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.174.01:28:37.87#ibcon#ireg 17 cls_cnt 0 2006.174.01:28:37.87#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.174.01:28:37.87#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.174.01:28:37.87#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.174.01:28:37.87#ibcon#enter wrdev, iclass 18, count 0 2006.174.01:28:37.87#ibcon#first serial, iclass 18, count 0 2006.174.01:28:37.87#ibcon#enter sib2, iclass 18, count 0 2006.174.01:28:37.87#ibcon#flushed, iclass 18, count 0 2006.174.01:28:37.87#ibcon#about to write, iclass 18, count 0 2006.174.01:28:37.87#ibcon#wrote, iclass 18, count 0 2006.174.01:28:37.87#ibcon#about to read 3, iclass 18, count 0 2006.174.01:28:37.89#ibcon#read 3, iclass 18, count 0 2006.174.01:28:37.89#ibcon#about to read 4, iclass 18, count 0 2006.174.01:28:37.89#ibcon#read 4, iclass 18, count 0 2006.174.01:28:37.89#ibcon#about to read 5, iclass 18, count 0 2006.174.01:28:37.89#ibcon#read 5, iclass 18, count 0 2006.174.01:28:37.89#ibcon#about to read 6, iclass 18, count 0 2006.174.01:28:37.89#ibcon#read 6, iclass 18, count 0 2006.174.01:28:37.89#ibcon#end of sib2, iclass 18, count 0 2006.174.01:28:37.89#ibcon#*mode == 0, iclass 18, count 0 2006.174.01:28:37.89#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.174.01:28:37.89#ibcon#[28=FRQ=01,629.99\r\n] 2006.174.01:28:37.89#ibcon#*before write, iclass 18, count 0 2006.174.01:28:37.89#ibcon#enter sib2, iclass 18, count 0 2006.174.01:28:37.89#ibcon#flushed, iclass 18, count 0 2006.174.01:28:37.89#ibcon#about to write, iclass 18, count 0 2006.174.01:28:37.89#ibcon#wrote, iclass 18, count 0 2006.174.01:28:37.89#ibcon#about to read 3, iclass 18, count 0 2006.174.01:28:37.93#ibcon#read 3, iclass 18, count 0 2006.174.01:28:37.93#ibcon#about to read 4, iclass 18, count 0 2006.174.01:28:37.93#ibcon#read 4, iclass 18, count 0 2006.174.01:28:37.93#ibcon#about to read 5, iclass 18, count 0 2006.174.01:28:37.93#ibcon#read 5, iclass 18, count 0 2006.174.01:28:37.93#ibcon#about to read 6, iclass 18, count 0 2006.174.01:28:37.93#ibcon#read 6, iclass 18, count 0 2006.174.01:28:37.93#ibcon#end of sib2, iclass 18, count 0 2006.174.01:28:37.93#ibcon#*after write, iclass 18, count 0 2006.174.01:28:37.93#ibcon#*before return 0, iclass 18, count 0 2006.174.01:28:37.93#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.174.01:28:37.93#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.174.01:28:37.93#ibcon#about to clear, iclass 18 cls_cnt 0 2006.174.01:28:37.93#ibcon#cleared, iclass 18 cls_cnt 0 2006.174.01:28:37.93$vck44/vb=1,4 2006.174.01:28:37.93#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.174.01:28:37.93#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.174.01:28:37.93#ibcon#ireg 11 cls_cnt 2 2006.174.01:28:37.93#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.174.01:28:37.93#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.174.01:28:37.93#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.174.01:28:37.93#ibcon#enter wrdev, iclass 20, count 2 2006.174.01:28:37.93#ibcon#first serial, iclass 20, count 2 2006.174.01:28:37.93#ibcon#enter sib2, iclass 20, count 2 2006.174.01:28:37.93#ibcon#flushed, iclass 20, count 2 2006.174.01:28:37.93#ibcon#about to write, iclass 20, count 2 2006.174.01:28:37.93#ibcon#wrote, iclass 20, count 2 2006.174.01:28:37.93#ibcon#about to read 3, iclass 20, count 2 2006.174.01:28:37.94#abcon#<5=/10 0.7 2.4 25.73 781003.3\r\n> 2006.174.01:28:37.95#ibcon#read 3, iclass 20, count 2 2006.174.01:28:37.95#ibcon#about to read 4, iclass 20, count 2 2006.174.01:28:37.95#ibcon#read 4, iclass 20, count 2 2006.174.01:28:37.95#ibcon#about to read 5, iclass 20, count 2 2006.174.01:28:37.95#ibcon#read 5, iclass 20, count 2 2006.174.01:28:37.95#ibcon#about to read 6, iclass 20, count 2 2006.174.01:28:37.95#ibcon#read 6, iclass 20, count 2 2006.174.01:28:37.95#ibcon#end of sib2, iclass 20, count 2 2006.174.01:28:37.95#ibcon#*mode == 0, iclass 20, count 2 2006.174.01:28:37.95#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.174.01:28:37.95#ibcon#[27=AT01-04\r\n] 2006.174.01:28:37.95#ibcon#*before write, iclass 20, count 2 2006.174.01:28:37.95#ibcon#enter sib2, iclass 20, count 2 2006.174.01:28:37.95#ibcon#flushed, iclass 20, count 2 2006.174.01:28:37.95#ibcon#about to write, iclass 20, count 2 2006.174.01:28:37.95#ibcon#wrote, iclass 20, count 2 2006.174.01:28:37.95#ibcon#about to read 3, iclass 20, count 2 2006.174.01:28:37.96#abcon#{5=INTERFACE CLEAR} 2006.174.01:28:37.98#ibcon#read 3, iclass 20, count 2 2006.174.01:28:37.98#ibcon#about to read 4, iclass 20, count 2 2006.174.01:28:37.98#ibcon#read 4, iclass 20, count 2 2006.174.01:28:37.98#ibcon#about to read 5, iclass 20, count 2 2006.174.01:28:37.98#ibcon#read 5, iclass 20, count 2 2006.174.01:28:37.98#ibcon#about to read 6, iclass 20, count 2 2006.174.01:28:37.98#ibcon#read 6, iclass 20, count 2 2006.174.01:28:37.98#ibcon#end of sib2, iclass 20, count 2 2006.174.01:28:37.98#ibcon#*after write, iclass 20, count 2 2006.174.01:28:37.98#ibcon#*before return 0, iclass 20, count 2 2006.174.01:28:37.98#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.174.01:28:37.98#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.174.01:28:37.98#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.174.01:28:37.98#ibcon#ireg 7 cls_cnt 0 2006.174.01:28:37.98#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.174.01:28:38.02#abcon#[5=S1D000X0/0*\r\n] 2006.174.01:28:38.10#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.174.01:28:38.10#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.174.01:28:38.10#ibcon#enter wrdev, iclass 20, count 0 2006.174.01:28:38.10#ibcon#first serial, iclass 20, count 0 2006.174.01:28:38.10#ibcon#enter sib2, iclass 20, count 0 2006.174.01:28:38.10#ibcon#flushed, iclass 20, count 0 2006.174.01:28:38.10#ibcon#about to write, iclass 20, count 0 2006.174.01:28:38.10#ibcon#wrote, iclass 20, count 0 2006.174.01:28:38.10#ibcon#about to read 3, iclass 20, count 0 2006.174.01:28:38.12#ibcon#read 3, iclass 20, count 0 2006.174.01:28:38.12#ibcon#about to read 4, iclass 20, count 0 2006.174.01:28:38.12#ibcon#read 4, iclass 20, count 0 2006.174.01:28:38.12#ibcon#about to read 5, iclass 20, count 0 2006.174.01:28:38.12#ibcon#read 5, iclass 20, count 0 2006.174.01:28:38.12#ibcon#about to read 6, iclass 20, count 0 2006.174.01:28:38.12#ibcon#read 6, iclass 20, count 0 2006.174.01:28:38.12#ibcon#end of sib2, iclass 20, count 0 2006.174.01:28:38.12#ibcon#*mode == 0, iclass 20, count 0 2006.174.01:28:38.12#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.174.01:28:38.12#ibcon#[27=USB\r\n] 2006.174.01:28:38.12#ibcon#*before write, iclass 20, count 0 2006.174.01:28:38.12#ibcon#enter sib2, iclass 20, count 0 2006.174.01:28:38.12#ibcon#flushed, iclass 20, count 0 2006.174.01:28:38.12#ibcon#about to write, iclass 20, count 0 2006.174.01:28:38.12#ibcon#wrote, iclass 20, count 0 2006.174.01:28:38.12#ibcon#about to read 3, iclass 20, count 0 2006.174.01:28:38.15#ibcon#read 3, iclass 20, count 0 2006.174.01:28:38.15#ibcon#about to read 4, iclass 20, count 0 2006.174.01:28:38.15#ibcon#read 4, iclass 20, count 0 2006.174.01:28:38.15#ibcon#about to read 5, iclass 20, count 0 2006.174.01:28:38.15#ibcon#read 5, iclass 20, count 0 2006.174.01:28:38.15#ibcon#about to read 6, iclass 20, count 0 2006.174.01:28:38.15#ibcon#read 6, iclass 20, count 0 2006.174.01:28:38.15#ibcon#end of sib2, iclass 20, count 0 2006.174.01:28:38.15#ibcon#*after write, iclass 20, count 0 2006.174.01:28:38.15#ibcon#*before return 0, iclass 20, count 0 2006.174.01:28:38.15#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.174.01:28:38.15#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.174.01:28:38.15#ibcon#about to clear, iclass 20 cls_cnt 0 2006.174.01:28:38.15#ibcon#cleared, iclass 20 cls_cnt 0 2006.174.01:28:38.15$vck44/vblo=2,634.99 2006.174.01:28:38.15#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.174.01:28:38.15#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.174.01:28:38.15#ibcon#ireg 17 cls_cnt 0 2006.174.01:28:38.15#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.174.01:28:38.15#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.174.01:28:38.15#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.174.01:28:38.15#ibcon#enter wrdev, iclass 25, count 0 2006.174.01:28:38.15#ibcon#first serial, iclass 25, count 0 2006.174.01:28:38.15#ibcon#enter sib2, iclass 25, count 0 2006.174.01:28:38.15#ibcon#flushed, iclass 25, count 0 2006.174.01:28:38.15#ibcon#about to write, iclass 25, count 0 2006.174.01:28:38.15#ibcon#wrote, iclass 25, count 0 2006.174.01:28:38.15#ibcon#about to read 3, iclass 25, count 0 2006.174.01:28:38.17#ibcon#read 3, iclass 25, count 0 2006.174.01:28:38.17#ibcon#about to read 4, iclass 25, count 0 2006.174.01:28:38.17#ibcon#read 4, iclass 25, count 0 2006.174.01:28:38.17#ibcon#about to read 5, iclass 25, count 0 2006.174.01:28:38.17#ibcon#read 5, iclass 25, count 0 2006.174.01:28:38.17#ibcon#about to read 6, iclass 25, count 0 2006.174.01:28:38.17#ibcon#read 6, iclass 25, count 0 2006.174.01:28:38.17#ibcon#end of sib2, iclass 25, count 0 2006.174.01:28:38.17#ibcon#*mode == 0, iclass 25, count 0 2006.174.01:28:38.17#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.174.01:28:38.17#ibcon#[28=FRQ=02,634.99\r\n] 2006.174.01:28:38.17#ibcon#*before write, iclass 25, count 0 2006.174.01:28:38.17#ibcon#enter sib2, iclass 25, count 0 2006.174.01:28:38.17#ibcon#flushed, iclass 25, count 0 2006.174.01:28:38.17#ibcon#about to write, iclass 25, count 0 2006.174.01:28:38.17#ibcon#wrote, iclass 25, count 0 2006.174.01:28:38.17#ibcon#about to read 3, iclass 25, count 0 2006.174.01:28:38.21#ibcon#read 3, iclass 25, count 0 2006.174.01:28:38.21#ibcon#about to read 4, iclass 25, count 0 2006.174.01:28:38.21#ibcon#read 4, iclass 25, count 0 2006.174.01:28:38.21#ibcon#about to read 5, iclass 25, count 0 2006.174.01:28:38.21#ibcon#read 5, iclass 25, count 0 2006.174.01:28:38.21#ibcon#about to read 6, iclass 25, count 0 2006.174.01:28:38.21#ibcon#read 6, iclass 25, count 0 2006.174.01:28:38.21#ibcon#end of sib2, iclass 25, count 0 2006.174.01:28:38.21#ibcon#*after write, iclass 25, count 0 2006.174.01:28:38.21#ibcon#*before return 0, iclass 25, count 0 2006.174.01:28:38.21#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.174.01:28:38.21#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.174.01:28:38.21#ibcon#about to clear, iclass 25 cls_cnt 0 2006.174.01:28:38.21#ibcon#cleared, iclass 25 cls_cnt 0 2006.174.01:28:38.21$vck44/vb=2,4 2006.174.01:28:38.21#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.174.01:28:38.21#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.174.01:28:38.21#ibcon#ireg 11 cls_cnt 2 2006.174.01:28:38.21#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.174.01:28:38.27#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.174.01:28:38.27#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.174.01:28:38.27#ibcon#enter wrdev, iclass 27, count 2 2006.174.01:28:38.27#ibcon#first serial, iclass 27, count 2 2006.174.01:28:38.27#ibcon#enter sib2, iclass 27, count 2 2006.174.01:28:38.27#ibcon#flushed, iclass 27, count 2 2006.174.01:28:38.27#ibcon#about to write, iclass 27, count 2 2006.174.01:28:38.27#ibcon#wrote, iclass 27, count 2 2006.174.01:28:38.27#ibcon#about to read 3, iclass 27, count 2 2006.174.01:28:38.29#ibcon#read 3, iclass 27, count 2 2006.174.01:28:38.29#ibcon#about to read 4, iclass 27, count 2 2006.174.01:28:38.29#ibcon#read 4, iclass 27, count 2 2006.174.01:28:38.29#ibcon#about to read 5, iclass 27, count 2 2006.174.01:28:38.29#ibcon#read 5, iclass 27, count 2 2006.174.01:28:38.29#ibcon#about to read 6, iclass 27, count 2 2006.174.01:28:38.29#ibcon#read 6, iclass 27, count 2 2006.174.01:28:38.29#ibcon#end of sib2, iclass 27, count 2 2006.174.01:28:38.29#ibcon#*mode == 0, iclass 27, count 2 2006.174.01:28:38.29#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.174.01:28:38.29#ibcon#[27=AT02-04\r\n] 2006.174.01:28:38.29#ibcon#*before write, iclass 27, count 2 2006.174.01:28:38.29#ibcon#enter sib2, iclass 27, count 2 2006.174.01:28:38.29#ibcon#flushed, iclass 27, count 2 2006.174.01:28:38.29#ibcon#about to write, iclass 27, count 2 2006.174.01:28:38.29#ibcon#wrote, iclass 27, count 2 2006.174.01:28:38.29#ibcon#about to read 3, iclass 27, count 2 2006.174.01:28:38.32#ibcon#read 3, iclass 27, count 2 2006.174.01:28:38.32#ibcon#about to read 4, iclass 27, count 2 2006.174.01:28:38.32#ibcon#read 4, iclass 27, count 2 2006.174.01:28:38.32#ibcon#about to read 5, iclass 27, count 2 2006.174.01:28:38.32#ibcon#read 5, iclass 27, count 2 2006.174.01:28:38.32#ibcon#about to read 6, iclass 27, count 2 2006.174.01:28:38.32#ibcon#read 6, iclass 27, count 2 2006.174.01:28:38.32#ibcon#end of sib2, iclass 27, count 2 2006.174.01:28:38.32#ibcon#*after write, iclass 27, count 2 2006.174.01:28:38.32#ibcon#*before return 0, iclass 27, count 2 2006.174.01:28:38.32#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.174.01:28:38.32#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.174.01:28:38.32#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.174.01:28:38.32#ibcon#ireg 7 cls_cnt 0 2006.174.01:28:38.32#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.174.01:28:38.44#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.174.01:28:38.44#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.174.01:28:38.44#ibcon#enter wrdev, iclass 27, count 0 2006.174.01:28:38.44#ibcon#first serial, iclass 27, count 0 2006.174.01:28:38.44#ibcon#enter sib2, iclass 27, count 0 2006.174.01:28:38.44#ibcon#flushed, iclass 27, count 0 2006.174.01:28:38.44#ibcon#about to write, iclass 27, count 0 2006.174.01:28:38.44#ibcon#wrote, iclass 27, count 0 2006.174.01:28:38.44#ibcon#about to read 3, iclass 27, count 0 2006.174.01:28:38.46#ibcon#read 3, iclass 27, count 0 2006.174.01:28:38.46#ibcon#about to read 4, iclass 27, count 0 2006.174.01:28:38.46#ibcon#read 4, iclass 27, count 0 2006.174.01:28:38.46#ibcon#about to read 5, iclass 27, count 0 2006.174.01:28:38.46#ibcon#read 5, iclass 27, count 0 2006.174.01:28:38.46#ibcon#about to read 6, iclass 27, count 0 2006.174.01:28:38.46#ibcon#read 6, iclass 27, count 0 2006.174.01:28:38.46#ibcon#end of sib2, iclass 27, count 0 2006.174.01:28:38.46#ibcon#*mode == 0, iclass 27, count 0 2006.174.01:28:38.46#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.174.01:28:38.46#ibcon#[27=USB\r\n] 2006.174.01:28:38.46#ibcon#*before write, iclass 27, count 0 2006.174.01:28:38.46#ibcon#enter sib2, iclass 27, count 0 2006.174.01:28:38.46#ibcon#flushed, iclass 27, count 0 2006.174.01:28:38.46#ibcon#about to write, iclass 27, count 0 2006.174.01:28:38.46#ibcon#wrote, iclass 27, count 0 2006.174.01:28:38.46#ibcon#about to read 3, iclass 27, count 0 2006.174.01:28:38.49#ibcon#read 3, iclass 27, count 0 2006.174.01:28:38.49#ibcon#about to read 4, iclass 27, count 0 2006.174.01:28:38.49#ibcon#read 4, iclass 27, count 0 2006.174.01:28:38.49#ibcon#about to read 5, iclass 27, count 0 2006.174.01:28:38.49#ibcon#read 5, iclass 27, count 0 2006.174.01:28:38.49#ibcon#about to read 6, iclass 27, count 0 2006.174.01:28:38.49#ibcon#read 6, iclass 27, count 0 2006.174.01:28:38.49#ibcon#end of sib2, iclass 27, count 0 2006.174.01:28:38.49#ibcon#*after write, iclass 27, count 0 2006.174.01:28:38.49#ibcon#*before return 0, iclass 27, count 0 2006.174.01:28:38.49#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.174.01:28:38.49#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.174.01:28:38.49#ibcon#about to clear, iclass 27 cls_cnt 0 2006.174.01:28:38.49#ibcon#cleared, iclass 27 cls_cnt 0 2006.174.01:28:38.49$vck44/vblo=3,649.99 2006.174.01:28:38.49#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.174.01:28:38.49#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.174.01:28:38.49#ibcon#ireg 17 cls_cnt 0 2006.174.01:28:38.49#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.174.01:28:38.49#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.174.01:28:38.49#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.174.01:28:38.49#ibcon#enter wrdev, iclass 29, count 0 2006.174.01:28:38.49#ibcon#first serial, iclass 29, count 0 2006.174.01:28:38.49#ibcon#enter sib2, iclass 29, count 0 2006.174.01:28:38.49#ibcon#flushed, iclass 29, count 0 2006.174.01:28:38.49#ibcon#about to write, iclass 29, count 0 2006.174.01:28:38.49#ibcon#wrote, iclass 29, count 0 2006.174.01:28:38.49#ibcon#about to read 3, iclass 29, count 0 2006.174.01:28:38.51#ibcon#read 3, iclass 29, count 0 2006.174.01:28:38.51#ibcon#about to read 4, iclass 29, count 0 2006.174.01:28:38.51#ibcon#read 4, iclass 29, count 0 2006.174.01:28:38.51#ibcon#about to read 5, iclass 29, count 0 2006.174.01:28:38.51#ibcon#read 5, iclass 29, count 0 2006.174.01:28:38.51#ibcon#about to read 6, iclass 29, count 0 2006.174.01:28:38.51#ibcon#read 6, iclass 29, count 0 2006.174.01:28:38.51#ibcon#end of sib2, iclass 29, count 0 2006.174.01:28:38.51#ibcon#*mode == 0, iclass 29, count 0 2006.174.01:28:38.51#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.174.01:28:38.51#ibcon#[28=FRQ=03,649.99\r\n] 2006.174.01:28:38.51#ibcon#*before write, iclass 29, count 0 2006.174.01:28:38.51#ibcon#enter sib2, iclass 29, count 0 2006.174.01:28:38.51#ibcon#flushed, iclass 29, count 0 2006.174.01:28:38.51#ibcon#about to write, iclass 29, count 0 2006.174.01:28:38.51#ibcon#wrote, iclass 29, count 0 2006.174.01:28:38.51#ibcon#about to read 3, iclass 29, count 0 2006.174.01:28:38.55#ibcon#read 3, iclass 29, count 0 2006.174.01:28:38.55#ibcon#about to read 4, iclass 29, count 0 2006.174.01:28:38.55#ibcon#read 4, iclass 29, count 0 2006.174.01:28:38.55#ibcon#about to read 5, iclass 29, count 0 2006.174.01:28:38.55#ibcon#read 5, iclass 29, count 0 2006.174.01:28:38.55#ibcon#about to read 6, iclass 29, count 0 2006.174.01:28:38.55#ibcon#read 6, iclass 29, count 0 2006.174.01:28:38.55#ibcon#end of sib2, iclass 29, count 0 2006.174.01:28:38.55#ibcon#*after write, iclass 29, count 0 2006.174.01:28:38.55#ibcon#*before return 0, iclass 29, count 0 2006.174.01:28:38.55#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.174.01:28:38.55#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.174.01:28:38.55#ibcon#about to clear, iclass 29 cls_cnt 0 2006.174.01:28:38.55#ibcon#cleared, iclass 29 cls_cnt 0 2006.174.01:28:38.55$vck44/vb=3,4 2006.174.01:28:38.55#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.174.01:28:38.55#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.174.01:28:38.55#ibcon#ireg 11 cls_cnt 2 2006.174.01:28:38.55#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.174.01:28:38.61#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.174.01:28:38.61#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.174.01:28:38.61#ibcon#enter wrdev, iclass 31, count 2 2006.174.01:28:38.61#ibcon#first serial, iclass 31, count 2 2006.174.01:28:38.61#ibcon#enter sib2, iclass 31, count 2 2006.174.01:28:38.61#ibcon#flushed, iclass 31, count 2 2006.174.01:28:38.61#ibcon#about to write, iclass 31, count 2 2006.174.01:28:38.61#ibcon#wrote, iclass 31, count 2 2006.174.01:28:38.61#ibcon#about to read 3, iclass 31, count 2 2006.174.01:28:38.63#ibcon#read 3, iclass 31, count 2 2006.174.01:28:38.63#ibcon#about to read 4, iclass 31, count 2 2006.174.01:28:38.63#ibcon#read 4, iclass 31, count 2 2006.174.01:28:38.63#ibcon#about to read 5, iclass 31, count 2 2006.174.01:28:38.63#ibcon#read 5, iclass 31, count 2 2006.174.01:28:38.63#ibcon#about to read 6, iclass 31, count 2 2006.174.01:28:38.63#ibcon#read 6, iclass 31, count 2 2006.174.01:28:38.63#ibcon#end of sib2, iclass 31, count 2 2006.174.01:28:38.63#ibcon#*mode == 0, iclass 31, count 2 2006.174.01:28:38.63#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.174.01:28:38.63#ibcon#[27=AT03-04\r\n] 2006.174.01:28:38.63#ibcon#*before write, iclass 31, count 2 2006.174.01:28:38.63#ibcon#enter sib2, iclass 31, count 2 2006.174.01:28:38.63#ibcon#flushed, iclass 31, count 2 2006.174.01:28:38.63#ibcon#about to write, iclass 31, count 2 2006.174.01:28:38.63#ibcon#wrote, iclass 31, count 2 2006.174.01:28:38.63#ibcon#about to read 3, iclass 31, count 2 2006.174.01:28:38.66#ibcon#read 3, iclass 31, count 2 2006.174.01:28:38.66#ibcon#about to read 4, iclass 31, count 2 2006.174.01:28:38.66#ibcon#read 4, iclass 31, count 2 2006.174.01:28:38.66#ibcon#about to read 5, iclass 31, count 2 2006.174.01:28:38.66#ibcon#read 5, iclass 31, count 2 2006.174.01:28:38.66#ibcon#about to read 6, iclass 31, count 2 2006.174.01:28:38.66#ibcon#read 6, iclass 31, count 2 2006.174.01:28:38.66#ibcon#end of sib2, iclass 31, count 2 2006.174.01:28:38.66#ibcon#*after write, iclass 31, count 2 2006.174.01:28:38.66#ibcon#*before return 0, iclass 31, count 2 2006.174.01:28:38.66#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.174.01:28:38.66#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.174.01:28:38.66#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.174.01:28:38.66#ibcon#ireg 7 cls_cnt 0 2006.174.01:28:38.66#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.174.01:28:38.78#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.174.01:28:38.78#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.174.01:28:38.78#ibcon#enter wrdev, iclass 31, count 0 2006.174.01:28:38.78#ibcon#first serial, iclass 31, count 0 2006.174.01:28:38.78#ibcon#enter sib2, iclass 31, count 0 2006.174.01:28:38.78#ibcon#flushed, iclass 31, count 0 2006.174.01:28:38.78#ibcon#about to write, iclass 31, count 0 2006.174.01:28:38.78#ibcon#wrote, iclass 31, count 0 2006.174.01:28:38.78#ibcon#about to read 3, iclass 31, count 0 2006.174.01:28:38.80#ibcon#read 3, iclass 31, count 0 2006.174.01:28:38.80#ibcon#about to read 4, iclass 31, count 0 2006.174.01:28:38.80#ibcon#read 4, iclass 31, count 0 2006.174.01:28:38.80#ibcon#about to read 5, iclass 31, count 0 2006.174.01:28:38.80#ibcon#read 5, iclass 31, count 0 2006.174.01:28:38.80#ibcon#about to read 6, iclass 31, count 0 2006.174.01:28:38.80#ibcon#read 6, iclass 31, count 0 2006.174.01:28:38.80#ibcon#end of sib2, iclass 31, count 0 2006.174.01:28:38.80#ibcon#*mode == 0, iclass 31, count 0 2006.174.01:28:38.80#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.174.01:28:38.80#ibcon#[27=USB\r\n] 2006.174.01:28:38.80#ibcon#*before write, iclass 31, count 0 2006.174.01:28:38.80#ibcon#enter sib2, iclass 31, count 0 2006.174.01:28:38.80#ibcon#flushed, iclass 31, count 0 2006.174.01:28:38.80#ibcon#about to write, iclass 31, count 0 2006.174.01:28:38.80#ibcon#wrote, iclass 31, count 0 2006.174.01:28:38.80#ibcon#about to read 3, iclass 31, count 0 2006.174.01:28:38.83#ibcon#read 3, iclass 31, count 0 2006.174.01:28:38.83#ibcon#about to read 4, iclass 31, count 0 2006.174.01:28:38.83#ibcon#read 4, iclass 31, count 0 2006.174.01:28:38.83#ibcon#about to read 5, iclass 31, count 0 2006.174.01:28:38.83#ibcon#read 5, iclass 31, count 0 2006.174.01:28:38.83#ibcon#about to read 6, iclass 31, count 0 2006.174.01:28:38.83#ibcon#read 6, iclass 31, count 0 2006.174.01:28:38.83#ibcon#end of sib2, iclass 31, count 0 2006.174.01:28:38.83#ibcon#*after write, iclass 31, count 0 2006.174.01:28:38.83#ibcon#*before return 0, iclass 31, count 0 2006.174.01:28:38.83#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.174.01:28:38.83#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.174.01:28:38.83#ibcon#about to clear, iclass 31 cls_cnt 0 2006.174.01:28:38.83#ibcon#cleared, iclass 31 cls_cnt 0 2006.174.01:28:38.83$vck44/vblo=4,679.99 2006.174.01:28:38.83#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.174.01:28:38.83#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.174.01:28:38.83#ibcon#ireg 17 cls_cnt 0 2006.174.01:28:38.83#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.174.01:28:38.83#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.174.01:28:38.83#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.174.01:28:38.83#ibcon#enter wrdev, iclass 33, count 0 2006.174.01:28:38.83#ibcon#first serial, iclass 33, count 0 2006.174.01:28:38.83#ibcon#enter sib2, iclass 33, count 0 2006.174.01:28:38.83#ibcon#flushed, iclass 33, count 0 2006.174.01:28:38.83#ibcon#about to write, iclass 33, count 0 2006.174.01:28:38.83#ibcon#wrote, iclass 33, count 0 2006.174.01:28:38.83#ibcon#about to read 3, iclass 33, count 0 2006.174.01:28:38.85#ibcon#read 3, iclass 33, count 0 2006.174.01:28:38.85#ibcon#about to read 4, iclass 33, count 0 2006.174.01:28:38.85#ibcon#read 4, iclass 33, count 0 2006.174.01:28:38.85#ibcon#about to read 5, iclass 33, count 0 2006.174.01:28:38.85#ibcon#read 5, iclass 33, count 0 2006.174.01:28:38.85#ibcon#about to read 6, iclass 33, count 0 2006.174.01:28:38.85#ibcon#read 6, iclass 33, count 0 2006.174.01:28:38.85#ibcon#end of sib2, iclass 33, count 0 2006.174.01:28:38.85#ibcon#*mode == 0, iclass 33, count 0 2006.174.01:28:38.85#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.174.01:28:38.85#ibcon#[28=FRQ=04,679.99\r\n] 2006.174.01:28:38.85#ibcon#*before write, iclass 33, count 0 2006.174.01:28:38.85#ibcon#enter sib2, iclass 33, count 0 2006.174.01:28:38.85#ibcon#flushed, iclass 33, count 0 2006.174.01:28:38.85#ibcon#about to write, iclass 33, count 0 2006.174.01:28:38.85#ibcon#wrote, iclass 33, count 0 2006.174.01:28:38.85#ibcon#about to read 3, iclass 33, count 0 2006.174.01:28:38.89#ibcon#read 3, iclass 33, count 0 2006.174.01:28:38.89#ibcon#about to read 4, iclass 33, count 0 2006.174.01:28:38.89#ibcon#read 4, iclass 33, count 0 2006.174.01:28:38.89#ibcon#about to read 5, iclass 33, count 0 2006.174.01:28:38.89#ibcon#read 5, iclass 33, count 0 2006.174.01:28:38.89#ibcon#about to read 6, iclass 33, count 0 2006.174.01:28:38.89#ibcon#read 6, iclass 33, count 0 2006.174.01:28:38.89#ibcon#end of sib2, iclass 33, count 0 2006.174.01:28:38.89#ibcon#*after write, iclass 33, count 0 2006.174.01:28:38.89#ibcon#*before return 0, iclass 33, count 0 2006.174.01:28:38.89#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.174.01:28:38.89#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.174.01:28:38.89#ibcon#about to clear, iclass 33 cls_cnt 0 2006.174.01:28:38.89#ibcon#cleared, iclass 33 cls_cnt 0 2006.174.01:28:38.89$vck44/vb=4,4 2006.174.01:28:38.89#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.174.01:28:38.89#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.174.01:28:38.89#ibcon#ireg 11 cls_cnt 2 2006.174.01:28:38.89#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.174.01:28:38.95#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.174.01:28:38.95#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.174.01:28:38.95#ibcon#enter wrdev, iclass 35, count 2 2006.174.01:28:38.95#ibcon#first serial, iclass 35, count 2 2006.174.01:28:38.95#ibcon#enter sib2, iclass 35, count 2 2006.174.01:28:38.95#ibcon#flushed, iclass 35, count 2 2006.174.01:28:38.95#ibcon#about to write, iclass 35, count 2 2006.174.01:28:38.95#ibcon#wrote, iclass 35, count 2 2006.174.01:28:38.95#ibcon#about to read 3, iclass 35, count 2 2006.174.01:28:38.97#ibcon#read 3, iclass 35, count 2 2006.174.01:28:38.97#ibcon#about to read 4, iclass 35, count 2 2006.174.01:28:38.97#ibcon#read 4, iclass 35, count 2 2006.174.01:28:38.97#ibcon#about to read 5, iclass 35, count 2 2006.174.01:28:38.97#ibcon#read 5, iclass 35, count 2 2006.174.01:28:38.97#ibcon#about to read 6, iclass 35, count 2 2006.174.01:28:38.97#ibcon#read 6, iclass 35, count 2 2006.174.01:28:38.97#ibcon#end of sib2, iclass 35, count 2 2006.174.01:28:38.97#ibcon#*mode == 0, iclass 35, count 2 2006.174.01:28:38.97#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.174.01:28:38.97#ibcon#[27=AT04-04\r\n] 2006.174.01:28:38.97#ibcon#*before write, iclass 35, count 2 2006.174.01:28:38.97#ibcon#enter sib2, iclass 35, count 2 2006.174.01:28:38.97#ibcon#flushed, iclass 35, count 2 2006.174.01:28:38.97#ibcon#about to write, iclass 35, count 2 2006.174.01:28:38.97#ibcon#wrote, iclass 35, count 2 2006.174.01:28:38.97#ibcon#about to read 3, iclass 35, count 2 2006.174.01:28:39.00#ibcon#read 3, iclass 35, count 2 2006.174.01:28:39.00#ibcon#about to read 4, iclass 35, count 2 2006.174.01:28:39.00#ibcon#read 4, iclass 35, count 2 2006.174.01:28:39.00#ibcon#about to read 5, iclass 35, count 2 2006.174.01:28:39.00#ibcon#read 5, iclass 35, count 2 2006.174.01:28:39.00#ibcon#about to read 6, iclass 35, count 2 2006.174.01:28:39.00#ibcon#read 6, iclass 35, count 2 2006.174.01:28:39.00#ibcon#end of sib2, iclass 35, count 2 2006.174.01:28:39.00#ibcon#*after write, iclass 35, count 2 2006.174.01:28:39.00#ibcon#*before return 0, iclass 35, count 2 2006.174.01:28:39.00#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.174.01:28:39.00#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.174.01:28:39.00#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.174.01:28:39.00#ibcon#ireg 7 cls_cnt 0 2006.174.01:28:39.00#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.174.01:28:39.12#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.174.01:28:39.12#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.174.01:28:39.12#ibcon#enter wrdev, iclass 35, count 0 2006.174.01:28:39.12#ibcon#first serial, iclass 35, count 0 2006.174.01:28:39.12#ibcon#enter sib2, iclass 35, count 0 2006.174.01:28:39.12#ibcon#flushed, iclass 35, count 0 2006.174.01:28:39.12#ibcon#about to write, iclass 35, count 0 2006.174.01:28:39.12#ibcon#wrote, iclass 35, count 0 2006.174.01:28:39.12#ibcon#about to read 3, iclass 35, count 0 2006.174.01:28:39.14#ibcon#read 3, iclass 35, count 0 2006.174.01:28:39.14#ibcon#about to read 4, iclass 35, count 0 2006.174.01:28:39.14#ibcon#read 4, iclass 35, count 0 2006.174.01:28:39.14#ibcon#about to read 5, iclass 35, count 0 2006.174.01:28:39.14#ibcon#read 5, iclass 35, count 0 2006.174.01:28:39.14#ibcon#about to read 6, iclass 35, count 0 2006.174.01:28:39.14#ibcon#read 6, iclass 35, count 0 2006.174.01:28:39.14#ibcon#end of sib2, iclass 35, count 0 2006.174.01:28:39.14#ibcon#*mode == 0, iclass 35, count 0 2006.174.01:28:39.14#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.174.01:28:39.14#ibcon#[27=USB\r\n] 2006.174.01:28:39.14#ibcon#*before write, iclass 35, count 0 2006.174.01:28:39.14#ibcon#enter sib2, iclass 35, count 0 2006.174.01:28:39.14#ibcon#flushed, iclass 35, count 0 2006.174.01:28:39.14#ibcon#about to write, iclass 35, count 0 2006.174.01:28:39.14#ibcon#wrote, iclass 35, count 0 2006.174.01:28:39.14#ibcon#about to read 3, iclass 35, count 0 2006.174.01:28:39.17#ibcon#read 3, iclass 35, count 0 2006.174.01:28:39.17#ibcon#about to read 4, iclass 35, count 0 2006.174.01:28:39.17#ibcon#read 4, iclass 35, count 0 2006.174.01:28:39.17#ibcon#about to read 5, iclass 35, count 0 2006.174.01:28:39.17#ibcon#read 5, iclass 35, count 0 2006.174.01:28:39.17#ibcon#about to read 6, iclass 35, count 0 2006.174.01:28:39.17#ibcon#read 6, iclass 35, count 0 2006.174.01:28:39.17#ibcon#end of sib2, iclass 35, count 0 2006.174.01:28:39.17#ibcon#*after write, iclass 35, count 0 2006.174.01:28:39.17#ibcon#*before return 0, iclass 35, count 0 2006.174.01:28:39.17#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.174.01:28:39.17#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.174.01:28:39.17#ibcon#about to clear, iclass 35 cls_cnt 0 2006.174.01:28:39.17#ibcon#cleared, iclass 35 cls_cnt 0 2006.174.01:28:39.17$vck44/vblo=5,709.99 2006.174.01:28:39.17#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.174.01:28:39.17#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.174.01:28:39.17#ibcon#ireg 17 cls_cnt 0 2006.174.01:28:39.17#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.174.01:28:39.17#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.174.01:28:39.17#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.174.01:28:39.17#ibcon#enter wrdev, iclass 37, count 0 2006.174.01:28:39.17#ibcon#first serial, iclass 37, count 0 2006.174.01:28:39.17#ibcon#enter sib2, iclass 37, count 0 2006.174.01:28:39.17#ibcon#flushed, iclass 37, count 0 2006.174.01:28:39.17#ibcon#about to write, iclass 37, count 0 2006.174.01:28:39.17#ibcon#wrote, iclass 37, count 0 2006.174.01:28:39.17#ibcon#about to read 3, iclass 37, count 0 2006.174.01:28:39.19#ibcon#read 3, iclass 37, count 0 2006.174.01:28:39.19#ibcon#about to read 4, iclass 37, count 0 2006.174.01:28:39.19#ibcon#read 4, iclass 37, count 0 2006.174.01:28:39.19#ibcon#about to read 5, iclass 37, count 0 2006.174.01:28:39.19#ibcon#read 5, iclass 37, count 0 2006.174.01:28:39.19#ibcon#about to read 6, iclass 37, count 0 2006.174.01:28:39.19#ibcon#read 6, iclass 37, count 0 2006.174.01:28:39.19#ibcon#end of sib2, iclass 37, count 0 2006.174.01:28:39.19#ibcon#*mode == 0, iclass 37, count 0 2006.174.01:28:39.19#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.174.01:28:39.19#ibcon#[28=FRQ=05,709.99\r\n] 2006.174.01:28:39.19#ibcon#*before write, iclass 37, count 0 2006.174.01:28:39.19#ibcon#enter sib2, iclass 37, count 0 2006.174.01:28:39.19#ibcon#flushed, iclass 37, count 0 2006.174.01:28:39.19#ibcon#about to write, iclass 37, count 0 2006.174.01:28:39.19#ibcon#wrote, iclass 37, count 0 2006.174.01:28:39.19#ibcon#about to read 3, iclass 37, count 0 2006.174.01:28:39.23#ibcon#read 3, iclass 37, count 0 2006.174.01:28:39.23#ibcon#about to read 4, iclass 37, count 0 2006.174.01:28:39.23#ibcon#read 4, iclass 37, count 0 2006.174.01:28:39.23#ibcon#about to read 5, iclass 37, count 0 2006.174.01:28:39.23#ibcon#read 5, iclass 37, count 0 2006.174.01:28:39.23#ibcon#about to read 6, iclass 37, count 0 2006.174.01:28:39.23#ibcon#read 6, iclass 37, count 0 2006.174.01:28:39.23#ibcon#end of sib2, iclass 37, count 0 2006.174.01:28:39.23#ibcon#*after write, iclass 37, count 0 2006.174.01:28:39.23#ibcon#*before return 0, iclass 37, count 0 2006.174.01:28:39.23#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.174.01:28:39.23#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.174.01:28:39.23#ibcon#about to clear, iclass 37 cls_cnt 0 2006.174.01:28:39.23#ibcon#cleared, iclass 37 cls_cnt 0 2006.174.01:28:39.23$vck44/vb=5,4 2006.174.01:28:39.23#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.174.01:28:39.23#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.174.01:28:39.23#ibcon#ireg 11 cls_cnt 2 2006.174.01:28:39.23#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.174.01:28:39.29#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.174.01:28:39.29#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.174.01:28:39.29#ibcon#enter wrdev, iclass 39, count 2 2006.174.01:28:39.29#ibcon#first serial, iclass 39, count 2 2006.174.01:28:39.29#ibcon#enter sib2, iclass 39, count 2 2006.174.01:28:39.29#ibcon#flushed, iclass 39, count 2 2006.174.01:28:39.29#ibcon#about to write, iclass 39, count 2 2006.174.01:28:39.29#ibcon#wrote, iclass 39, count 2 2006.174.01:28:39.29#ibcon#about to read 3, iclass 39, count 2 2006.174.01:28:39.31#ibcon#read 3, iclass 39, count 2 2006.174.01:28:39.31#ibcon#about to read 4, iclass 39, count 2 2006.174.01:28:39.31#ibcon#read 4, iclass 39, count 2 2006.174.01:28:39.31#ibcon#about to read 5, iclass 39, count 2 2006.174.01:28:39.31#ibcon#read 5, iclass 39, count 2 2006.174.01:28:39.31#ibcon#about to read 6, iclass 39, count 2 2006.174.01:28:39.31#ibcon#read 6, iclass 39, count 2 2006.174.01:28:39.31#ibcon#end of sib2, iclass 39, count 2 2006.174.01:28:39.31#ibcon#*mode == 0, iclass 39, count 2 2006.174.01:28:39.31#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.174.01:28:39.31#ibcon#[27=AT05-04\r\n] 2006.174.01:28:39.31#ibcon#*before write, iclass 39, count 2 2006.174.01:28:39.31#ibcon#enter sib2, iclass 39, count 2 2006.174.01:28:39.31#ibcon#flushed, iclass 39, count 2 2006.174.01:28:39.31#ibcon#about to write, iclass 39, count 2 2006.174.01:28:39.31#ibcon#wrote, iclass 39, count 2 2006.174.01:28:39.31#ibcon#about to read 3, iclass 39, count 2 2006.174.01:28:39.34#ibcon#read 3, iclass 39, count 2 2006.174.01:28:39.34#ibcon#about to read 4, iclass 39, count 2 2006.174.01:28:39.34#ibcon#read 4, iclass 39, count 2 2006.174.01:28:39.34#ibcon#about to read 5, iclass 39, count 2 2006.174.01:28:39.34#ibcon#read 5, iclass 39, count 2 2006.174.01:28:39.34#ibcon#about to read 6, iclass 39, count 2 2006.174.01:28:39.34#ibcon#read 6, iclass 39, count 2 2006.174.01:28:39.34#ibcon#end of sib2, iclass 39, count 2 2006.174.01:28:39.34#ibcon#*after write, iclass 39, count 2 2006.174.01:28:39.34#ibcon#*before return 0, iclass 39, count 2 2006.174.01:28:39.34#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.174.01:28:39.34#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.174.01:28:39.34#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.174.01:28:39.34#ibcon#ireg 7 cls_cnt 0 2006.174.01:28:39.34#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.174.01:28:39.46#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.174.01:28:39.46#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.174.01:28:39.46#ibcon#enter wrdev, iclass 39, count 0 2006.174.01:28:39.46#ibcon#first serial, iclass 39, count 0 2006.174.01:28:39.46#ibcon#enter sib2, iclass 39, count 0 2006.174.01:28:39.46#ibcon#flushed, iclass 39, count 0 2006.174.01:28:39.46#ibcon#about to write, iclass 39, count 0 2006.174.01:28:39.46#ibcon#wrote, iclass 39, count 0 2006.174.01:28:39.46#ibcon#about to read 3, iclass 39, count 0 2006.174.01:28:39.48#ibcon#read 3, iclass 39, count 0 2006.174.01:28:39.48#ibcon#about to read 4, iclass 39, count 0 2006.174.01:28:39.48#ibcon#read 4, iclass 39, count 0 2006.174.01:28:39.48#ibcon#about to read 5, iclass 39, count 0 2006.174.01:28:39.48#ibcon#read 5, iclass 39, count 0 2006.174.01:28:39.48#ibcon#about to read 6, iclass 39, count 0 2006.174.01:28:39.48#ibcon#read 6, iclass 39, count 0 2006.174.01:28:39.48#ibcon#end of sib2, iclass 39, count 0 2006.174.01:28:39.48#ibcon#*mode == 0, iclass 39, count 0 2006.174.01:28:39.48#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.174.01:28:39.48#ibcon#[27=USB\r\n] 2006.174.01:28:39.48#ibcon#*before write, iclass 39, count 0 2006.174.01:28:39.48#ibcon#enter sib2, iclass 39, count 0 2006.174.01:28:39.48#ibcon#flushed, iclass 39, count 0 2006.174.01:28:39.48#ibcon#about to write, iclass 39, count 0 2006.174.01:28:39.48#ibcon#wrote, iclass 39, count 0 2006.174.01:28:39.48#ibcon#about to read 3, iclass 39, count 0 2006.174.01:28:39.51#ibcon#read 3, iclass 39, count 0 2006.174.01:28:39.51#ibcon#about to read 4, iclass 39, count 0 2006.174.01:28:39.51#ibcon#read 4, iclass 39, count 0 2006.174.01:28:39.51#ibcon#about to read 5, iclass 39, count 0 2006.174.01:28:39.51#ibcon#read 5, iclass 39, count 0 2006.174.01:28:39.51#ibcon#about to read 6, iclass 39, count 0 2006.174.01:28:39.51#ibcon#read 6, iclass 39, count 0 2006.174.01:28:39.51#ibcon#end of sib2, iclass 39, count 0 2006.174.01:28:39.51#ibcon#*after write, iclass 39, count 0 2006.174.01:28:39.51#ibcon#*before return 0, iclass 39, count 0 2006.174.01:28:39.51#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.174.01:28:39.51#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.174.01:28:39.51#ibcon#about to clear, iclass 39 cls_cnt 0 2006.174.01:28:39.51#ibcon#cleared, iclass 39 cls_cnt 0 2006.174.01:28:39.51$vck44/vblo=6,719.99 2006.174.01:28:39.51#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.174.01:28:39.51#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.174.01:28:39.51#ibcon#ireg 17 cls_cnt 0 2006.174.01:28:39.51#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.174.01:28:39.51#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.174.01:28:39.51#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.174.01:28:39.51#ibcon#enter wrdev, iclass 3, count 0 2006.174.01:28:39.51#ibcon#first serial, iclass 3, count 0 2006.174.01:28:39.51#ibcon#enter sib2, iclass 3, count 0 2006.174.01:28:39.51#ibcon#flushed, iclass 3, count 0 2006.174.01:28:39.51#ibcon#about to write, iclass 3, count 0 2006.174.01:28:39.51#ibcon#wrote, iclass 3, count 0 2006.174.01:28:39.51#ibcon#about to read 3, iclass 3, count 0 2006.174.01:28:39.53#ibcon#read 3, iclass 3, count 0 2006.174.01:28:39.53#ibcon#about to read 4, iclass 3, count 0 2006.174.01:28:39.53#ibcon#read 4, iclass 3, count 0 2006.174.01:28:39.53#ibcon#about to read 5, iclass 3, count 0 2006.174.01:28:39.53#ibcon#read 5, iclass 3, count 0 2006.174.01:28:39.53#ibcon#about to read 6, iclass 3, count 0 2006.174.01:28:39.53#ibcon#read 6, iclass 3, count 0 2006.174.01:28:39.53#ibcon#end of sib2, iclass 3, count 0 2006.174.01:28:39.53#ibcon#*mode == 0, iclass 3, count 0 2006.174.01:28:39.53#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.174.01:28:39.53#ibcon#[28=FRQ=06,719.99\r\n] 2006.174.01:28:39.53#ibcon#*before write, iclass 3, count 0 2006.174.01:28:39.53#ibcon#enter sib2, iclass 3, count 0 2006.174.01:28:39.53#ibcon#flushed, iclass 3, count 0 2006.174.01:28:39.53#ibcon#about to write, iclass 3, count 0 2006.174.01:28:39.53#ibcon#wrote, iclass 3, count 0 2006.174.01:28:39.53#ibcon#about to read 3, iclass 3, count 0 2006.174.01:28:39.57#ibcon#read 3, iclass 3, count 0 2006.174.01:28:39.57#ibcon#about to read 4, iclass 3, count 0 2006.174.01:28:39.57#ibcon#read 4, iclass 3, count 0 2006.174.01:28:39.57#ibcon#about to read 5, iclass 3, count 0 2006.174.01:28:39.57#ibcon#read 5, iclass 3, count 0 2006.174.01:28:39.57#ibcon#about to read 6, iclass 3, count 0 2006.174.01:28:39.57#ibcon#read 6, iclass 3, count 0 2006.174.01:28:39.57#ibcon#end of sib2, iclass 3, count 0 2006.174.01:28:39.57#ibcon#*after write, iclass 3, count 0 2006.174.01:28:39.57#ibcon#*before return 0, iclass 3, count 0 2006.174.01:28:39.57#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.174.01:28:39.57#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.174.01:28:39.57#ibcon#about to clear, iclass 3 cls_cnt 0 2006.174.01:28:39.57#ibcon#cleared, iclass 3 cls_cnt 0 2006.174.01:28:39.57$vck44/vb=6,4 2006.174.01:28:39.57#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.174.01:28:39.57#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.174.01:28:39.57#ibcon#ireg 11 cls_cnt 2 2006.174.01:28:39.57#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.174.01:28:39.63#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.174.01:28:39.63#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.174.01:28:39.63#ibcon#enter wrdev, iclass 5, count 2 2006.174.01:28:39.63#ibcon#first serial, iclass 5, count 2 2006.174.01:28:39.63#ibcon#enter sib2, iclass 5, count 2 2006.174.01:28:39.63#ibcon#flushed, iclass 5, count 2 2006.174.01:28:39.63#ibcon#about to write, iclass 5, count 2 2006.174.01:28:39.63#ibcon#wrote, iclass 5, count 2 2006.174.01:28:39.63#ibcon#about to read 3, iclass 5, count 2 2006.174.01:28:39.65#ibcon#read 3, iclass 5, count 2 2006.174.01:28:39.65#ibcon#about to read 4, iclass 5, count 2 2006.174.01:28:39.65#ibcon#read 4, iclass 5, count 2 2006.174.01:28:39.65#ibcon#about to read 5, iclass 5, count 2 2006.174.01:28:39.65#ibcon#read 5, iclass 5, count 2 2006.174.01:28:39.65#ibcon#about to read 6, iclass 5, count 2 2006.174.01:28:39.65#ibcon#read 6, iclass 5, count 2 2006.174.01:28:39.65#ibcon#end of sib2, iclass 5, count 2 2006.174.01:28:39.65#ibcon#*mode == 0, iclass 5, count 2 2006.174.01:28:39.65#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.174.01:28:39.65#ibcon#[27=AT06-04\r\n] 2006.174.01:28:39.65#ibcon#*before write, iclass 5, count 2 2006.174.01:28:39.65#ibcon#enter sib2, iclass 5, count 2 2006.174.01:28:39.65#ibcon#flushed, iclass 5, count 2 2006.174.01:28:39.65#ibcon#about to write, iclass 5, count 2 2006.174.01:28:39.65#ibcon#wrote, iclass 5, count 2 2006.174.01:28:39.65#ibcon#about to read 3, iclass 5, count 2 2006.174.01:28:39.68#ibcon#read 3, iclass 5, count 2 2006.174.01:28:39.68#ibcon#about to read 4, iclass 5, count 2 2006.174.01:28:39.68#ibcon#read 4, iclass 5, count 2 2006.174.01:28:39.68#ibcon#about to read 5, iclass 5, count 2 2006.174.01:28:39.68#ibcon#read 5, iclass 5, count 2 2006.174.01:28:39.68#ibcon#about to read 6, iclass 5, count 2 2006.174.01:28:39.68#ibcon#read 6, iclass 5, count 2 2006.174.01:28:39.68#ibcon#end of sib2, iclass 5, count 2 2006.174.01:28:39.68#ibcon#*after write, iclass 5, count 2 2006.174.01:28:39.68#ibcon#*before return 0, iclass 5, count 2 2006.174.01:28:39.68#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.174.01:28:39.68#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.174.01:28:39.68#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.174.01:28:39.68#ibcon#ireg 7 cls_cnt 0 2006.174.01:28:39.68#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.174.01:28:39.80#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.174.01:28:39.80#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.174.01:28:39.80#ibcon#enter wrdev, iclass 5, count 0 2006.174.01:28:39.80#ibcon#first serial, iclass 5, count 0 2006.174.01:28:39.80#ibcon#enter sib2, iclass 5, count 0 2006.174.01:28:39.80#ibcon#flushed, iclass 5, count 0 2006.174.01:28:39.80#ibcon#about to write, iclass 5, count 0 2006.174.01:28:39.80#ibcon#wrote, iclass 5, count 0 2006.174.01:28:39.80#ibcon#about to read 3, iclass 5, count 0 2006.174.01:28:39.82#ibcon#read 3, iclass 5, count 0 2006.174.01:28:39.82#ibcon#about to read 4, iclass 5, count 0 2006.174.01:28:39.82#ibcon#read 4, iclass 5, count 0 2006.174.01:28:39.82#ibcon#about to read 5, iclass 5, count 0 2006.174.01:28:39.82#ibcon#read 5, iclass 5, count 0 2006.174.01:28:39.82#ibcon#about to read 6, iclass 5, count 0 2006.174.01:28:39.82#ibcon#read 6, iclass 5, count 0 2006.174.01:28:39.82#ibcon#end of sib2, iclass 5, count 0 2006.174.01:28:39.82#ibcon#*mode == 0, iclass 5, count 0 2006.174.01:28:39.82#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.174.01:28:39.82#ibcon#[27=USB\r\n] 2006.174.01:28:39.82#ibcon#*before write, iclass 5, count 0 2006.174.01:28:39.82#ibcon#enter sib2, iclass 5, count 0 2006.174.01:28:39.82#ibcon#flushed, iclass 5, count 0 2006.174.01:28:39.82#ibcon#about to write, iclass 5, count 0 2006.174.01:28:39.82#ibcon#wrote, iclass 5, count 0 2006.174.01:28:39.82#ibcon#about to read 3, iclass 5, count 0 2006.174.01:28:39.85#ibcon#read 3, iclass 5, count 0 2006.174.01:28:39.85#ibcon#about to read 4, iclass 5, count 0 2006.174.01:28:39.85#ibcon#read 4, iclass 5, count 0 2006.174.01:28:39.85#ibcon#about to read 5, iclass 5, count 0 2006.174.01:28:39.85#ibcon#read 5, iclass 5, count 0 2006.174.01:28:39.85#ibcon#about to read 6, iclass 5, count 0 2006.174.01:28:39.85#ibcon#read 6, iclass 5, count 0 2006.174.01:28:39.85#ibcon#end of sib2, iclass 5, count 0 2006.174.01:28:39.85#ibcon#*after write, iclass 5, count 0 2006.174.01:28:39.85#ibcon#*before return 0, iclass 5, count 0 2006.174.01:28:39.85#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.174.01:28:39.85#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.174.01:28:39.85#ibcon#about to clear, iclass 5 cls_cnt 0 2006.174.01:28:39.85#ibcon#cleared, iclass 5 cls_cnt 0 2006.174.01:28:39.85$vck44/vblo=7,734.99 2006.174.01:28:39.85#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.174.01:28:39.85#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.174.01:28:39.85#ibcon#ireg 17 cls_cnt 0 2006.174.01:28:39.85#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.174.01:28:39.85#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.174.01:28:39.85#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.174.01:28:39.85#ibcon#enter wrdev, iclass 7, count 0 2006.174.01:28:39.85#ibcon#first serial, iclass 7, count 0 2006.174.01:28:39.85#ibcon#enter sib2, iclass 7, count 0 2006.174.01:28:39.85#ibcon#flushed, iclass 7, count 0 2006.174.01:28:39.85#ibcon#about to write, iclass 7, count 0 2006.174.01:28:39.85#ibcon#wrote, iclass 7, count 0 2006.174.01:28:39.85#ibcon#about to read 3, iclass 7, count 0 2006.174.01:28:39.87#ibcon#read 3, iclass 7, count 0 2006.174.01:28:39.87#ibcon#about to read 4, iclass 7, count 0 2006.174.01:28:39.87#ibcon#read 4, iclass 7, count 0 2006.174.01:28:39.87#ibcon#about to read 5, iclass 7, count 0 2006.174.01:28:39.87#ibcon#read 5, iclass 7, count 0 2006.174.01:28:39.87#ibcon#about to read 6, iclass 7, count 0 2006.174.01:28:39.87#ibcon#read 6, iclass 7, count 0 2006.174.01:28:39.87#ibcon#end of sib2, iclass 7, count 0 2006.174.01:28:39.87#ibcon#*mode == 0, iclass 7, count 0 2006.174.01:28:39.87#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.174.01:28:39.87#ibcon#[28=FRQ=07,734.99\r\n] 2006.174.01:28:39.87#ibcon#*before write, iclass 7, count 0 2006.174.01:28:39.87#ibcon#enter sib2, iclass 7, count 0 2006.174.01:28:39.87#ibcon#flushed, iclass 7, count 0 2006.174.01:28:39.87#ibcon#about to write, iclass 7, count 0 2006.174.01:28:39.87#ibcon#wrote, iclass 7, count 0 2006.174.01:28:39.87#ibcon#about to read 3, iclass 7, count 0 2006.174.01:28:39.91#ibcon#read 3, iclass 7, count 0 2006.174.01:28:39.91#ibcon#about to read 4, iclass 7, count 0 2006.174.01:28:39.91#ibcon#read 4, iclass 7, count 0 2006.174.01:28:39.91#ibcon#about to read 5, iclass 7, count 0 2006.174.01:28:39.91#ibcon#read 5, iclass 7, count 0 2006.174.01:28:39.91#ibcon#about to read 6, iclass 7, count 0 2006.174.01:28:39.91#ibcon#read 6, iclass 7, count 0 2006.174.01:28:39.91#ibcon#end of sib2, iclass 7, count 0 2006.174.01:28:39.91#ibcon#*after write, iclass 7, count 0 2006.174.01:28:39.91#ibcon#*before return 0, iclass 7, count 0 2006.174.01:28:39.91#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.174.01:28:39.91#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.174.01:28:39.91#ibcon#about to clear, iclass 7 cls_cnt 0 2006.174.01:28:39.91#ibcon#cleared, iclass 7 cls_cnt 0 2006.174.01:28:39.91$vck44/vb=7,4 2006.174.01:28:39.91#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.174.01:28:39.91#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.174.01:28:39.91#ibcon#ireg 11 cls_cnt 2 2006.174.01:28:39.91#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.174.01:28:39.97#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.174.01:28:39.97#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.174.01:28:39.97#ibcon#enter wrdev, iclass 11, count 2 2006.174.01:28:39.97#ibcon#first serial, iclass 11, count 2 2006.174.01:28:39.97#ibcon#enter sib2, iclass 11, count 2 2006.174.01:28:39.97#ibcon#flushed, iclass 11, count 2 2006.174.01:28:39.97#ibcon#about to write, iclass 11, count 2 2006.174.01:28:39.97#ibcon#wrote, iclass 11, count 2 2006.174.01:28:39.97#ibcon#about to read 3, iclass 11, count 2 2006.174.01:28:39.99#ibcon#read 3, iclass 11, count 2 2006.174.01:28:39.99#ibcon#about to read 4, iclass 11, count 2 2006.174.01:28:39.99#ibcon#read 4, iclass 11, count 2 2006.174.01:28:39.99#ibcon#about to read 5, iclass 11, count 2 2006.174.01:28:39.99#ibcon#read 5, iclass 11, count 2 2006.174.01:28:39.99#ibcon#about to read 6, iclass 11, count 2 2006.174.01:28:39.99#ibcon#read 6, iclass 11, count 2 2006.174.01:28:39.99#ibcon#end of sib2, iclass 11, count 2 2006.174.01:28:39.99#ibcon#*mode == 0, iclass 11, count 2 2006.174.01:28:39.99#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.174.01:28:39.99#ibcon#[27=AT07-04\r\n] 2006.174.01:28:39.99#ibcon#*before write, iclass 11, count 2 2006.174.01:28:39.99#ibcon#enter sib2, iclass 11, count 2 2006.174.01:28:39.99#ibcon#flushed, iclass 11, count 2 2006.174.01:28:39.99#ibcon#about to write, iclass 11, count 2 2006.174.01:28:39.99#ibcon#wrote, iclass 11, count 2 2006.174.01:28:39.99#ibcon#about to read 3, iclass 11, count 2 2006.174.01:28:40.02#ibcon#read 3, iclass 11, count 2 2006.174.01:28:40.02#ibcon#about to read 4, iclass 11, count 2 2006.174.01:28:40.02#ibcon#read 4, iclass 11, count 2 2006.174.01:28:40.02#ibcon#about to read 5, iclass 11, count 2 2006.174.01:28:40.02#ibcon#read 5, iclass 11, count 2 2006.174.01:28:40.02#ibcon#about to read 6, iclass 11, count 2 2006.174.01:28:40.02#ibcon#read 6, iclass 11, count 2 2006.174.01:28:40.02#ibcon#end of sib2, iclass 11, count 2 2006.174.01:28:40.02#ibcon#*after write, iclass 11, count 2 2006.174.01:28:40.02#ibcon#*before return 0, iclass 11, count 2 2006.174.01:28:40.02#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.174.01:28:40.02#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.174.01:28:40.02#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.174.01:28:40.02#ibcon#ireg 7 cls_cnt 0 2006.174.01:28:40.02#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.174.01:28:40.14#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.174.01:28:40.14#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.174.01:28:40.14#ibcon#enter wrdev, iclass 11, count 0 2006.174.01:28:40.14#ibcon#first serial, iclass 11, count 0 2006.174.01:28:40.14#ibcon#enter sib2, iclass 11, count 0 2006.174.01:28:40.14#ibcon#flushed, iclass 11, count 0 2006.174.01:28:40.14#ibcon#about to write, iclass 11, count 0 2006.174.01:28:40.14#ibcon#wrote, iclass 11, count 0 2006.174.01:28:40.14#ibcon#about to read 3, iclass 11, count 0 2006.174.01:28:40.16#ibcon#read 3, iclass 11, count 0 2006.174.01:28:40.16#ibcon#about to read 4, iclass 11, count 0 2006.174.01:28:40.16#ibcon#read 4, iclass 11, count 0 2006.174.01:28:40.16#ibcon#about to read 5, iclass 11, count 0 2006.174.01:28:40.16#ibcon#read 5, iclass 11, count 0 2006.174.01:28:40.16#ibcon#about to read 6, iclass 11, count 0 2006.174.01:28:40.16#ibcon#read 6, iclass 11, count 0 2006.174.01:28:40.16#ibcon#end of sib2, iclass 11, count 0 2006.174.01:28:40.16#ibcon#*mode == 0, iclass 11, count 0 2006.174.01:28:40.16#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.174.01:28:40.16#ibcon#[27=USB\r\n] 2006.174.01:28:40.16#ibcon#*before write, iclass 11, count 0 2006.174.01:28:40.16#ibcon#enter sib2, iclass 11, count 0 2006.174.01:28:40.16#ibcon#flushed, iclass 11, count 0 2006.174.01:28:40.16#ibcon#about to write, iclass 11, count 0 2006.174.01:28:40.16#ibcon#wrote, iclass 11, count 0 2006.174.01:28:40.16#ibcon#about to read 3, iclass 11, count 0 2006.174.01:28:40.19#ibcon#read 3, iclass 11, count 0 2006.174.01:28:40.19#ibcon#about to read 4, iclass 11, count 0 2006.174.01:28:40.19#ibcon#read 4, iclass 11, count 0 2006.174.01:28:40.19#ibcon#about to read 5, iclass 11, count 0 2006.174.01:28:40.19#ibcon#read 5, iclass 11, count 0 2006.174.01:28:40.19#ibcon#about to read 6, iclass 11, count 0 2006.174.01:28:40.19#ibcon#read 6, iclass 11, count 0 2006.174.01:28:40.19#ibcon#end of sib2, iclass 11, count 0 2006.174.01:28:40.19#ibcon#*after write, iclass 11, count 0 2006.174.01:28:40.19#ibcon#*before return 0, iclass 11, count 0 2006.174.01:28:40.19#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.174.01:28:40.19#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.174.01:28:40.19#ibcon#about to clear, iclass 11 cls_cnt 0 2006.174.01:28:40.19#ibcon#cleared, iclass 11 cls_cnt 0 2006.174.01:28:40.19$vck44/vblo=8,744.99 2006.174.01:28:40.19#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.174.01:28:40.19#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.174.01:28:40.19#ibcon#ireg 17 cls_cnt 0 2006.174.01:28:40.19#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.174.01:28:40.19#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.174.01:28:40.19#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.174.01:28:40.19#ibcon#enter wrdev, iclass 13, count 0 2006.174.01:28:40.19#ibcon#first serial, iclass 13, count 0 2006.174.01:28:40.19#ibcon#enter sib2, iclass 13, count 0 2006.174.01:28:40.19#ibcon#flushed, iclass 13, count 0 2006.174.01:28:40.19#ibcon#about to write, iclass 13, count 0 2006.174.01:28:40.19#ibcon#wrote, iclass 13, count 0 2006.174.01:28:40.19#ibcon#about to read 3, iclass 13, count 0 2006.174.01:28:40.21#ibcon#read 3, iclass 13, count 0 2006.174.01:28:40.21#ibcon#about to read 4, iclass 13, count 0 2006.174.01:28:40.21#ibcon#read 4, iclass 13, count 0 2006.174.01:28:40.21#ibcon#about to read 5, iclass 13, count 0 2006.174.01:28:40.21#ibcon#read 5, iclass 13, count 0 2006.174.01:28:40.21#ibcon#about to read 6, iclass 13, count 0 2006.174.01:28:40.21#ibcon#read 6, iclass 13, count 0 2006.174.01:28:40.21#ibcon#end of sib2, iclass 13, count 0 2006.174.01:28:40.21#ibcon#*mode == 0, iclass 13, count 0 2006.174.01:28:40.21#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.174.01:28:40.21#ibcon#[28=FRQ=08,744.99\r\n] 2006.174.01:28:40.21#ibcon#*before write, iclass 13, count 0 2006.174.01:28:40.21#ibcon#enter sib2, iclass 13, count 0 2006.174.01:28:40.21#ibcon#flushed, iclass 13, count 0 2006.174.01:28:40.21#ibcon#about to write, iclass 13, count 0 2006.174.01:28:40.21#ibcon#wrote, iclass 13, count 0 2006.174.01:28:40.21#ibcon#about to read 3, iclass 13, count 0 2006.174.01:28:40.25#ibcon#read 3, iclass 13, count 0 2006.174.01:28:40.25#ibcon#about to read 4, iclass 13, count 0 2006.174.01:28:40.25#ibcon#read 4, iclass 13, count 0 2006.174.01:28:40.25#ibcon#about to read 5, iclass 13, count 0 2006.174.01:28:40.25#ibcon#read 5, iclass 13, count 0 2006.174.01:28:40.25#ibcon#about to read 6, iclass 13, count 0 2006.174.01:28:40.25#ibcon#read 6, iclass 13, count 0 2006.174.01:28:40.25#ibcon#end of sib2, iclass 13, count 0 2006.174.01:28:40.25#ibcon#*after write, iclass 13, count 0 2006.174.01:28:40.25#ibcon#*before return 0, iclass 13, count 0 2006.174.01:28:40.25#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.174.01:28:40.25#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.174.01:28:40.25#ibcon#about to clear, iclass 13 cls_cnt 0 2006.174.01:28:40.25#ibcon#cleared, iclass 13 cls_cnt 0 2006.174.01:28:40.25$vck44/vb=8,4 2006.174.01:28:40.25#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.174.01:28:40.25#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.174.01:28:40.25#ibcon#ireg 11 cls_cnt 2 2006.174.01:28:40.25#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.174.01:28:40.31#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.174.01:28:40.31#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.174.01:28:40.31#ibcon#enter wrdev, iclass 15, count 2 2006.174.01:28:40.31#ibcon#first serial, iclass 15, count 2 2006.174.01:28:40.31#ibcon#enter sib2, iclass 15, count 2 2006.174.01:28:40.31#ibcon#flushed, iclass 15, count 2 2006.174.01:28:40.31#ibcon#about to write, iclass 15, count 2 2006.174.01:28:40.31#ibcon#wrote, iclass 15, count 2 2006.174.01:28:40.31#ibcon#about to read 3, iclass 15, count 2 2006.174.01:28:40.33#ibcon#read 3, iclass 15, count 2 2006.174.01:28:40.33#ibcon#about to read 4, iclass 15, count 2 2006.174.01:28:40.33#ibcon#read 4, iclass 15, count 2 2006.174.01:28:40.33#ibcon#about to read 5, iclass 15, count 2 2006.174.01:28:40.33#ibcon#read 5, iclass 15, count 2 2006.174.01:28:40.33#ibcon#about to read 6, iclass 15, count 2 2006.174.01:28:40.33#ibcon#read 6, iclass 15, count 2 2006.174.01:28:40.33#ibcon#end of sib2, iclass 15, count 2 2006.174.01:28:40.33#ibcon#*mode == 0, iclass 15, count 2 2006.174.01:28:40.33#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.174.01:28:40.33#ibcon#[27=AT08-04\r\n] 2006.174.01:28:40.33#ibcon#*before write, iclass 15, count 2 2006.174.01:28:40.33#ibcon#enter sib2, iclass 15, count 2 2006.174.01:28:40.33#ibcon#flushed, iclass 15, count 2 2006.174.01:28:40.33#ibcon#about to write, iclass 15, count 2 2006.174.01:28:40.33#ibcon#wrote, iclass 15, count 2 2006.174.01:28:40.33#ibcon#about to read 3, iclass 15, count 2 2006.174.01:28:40.36#ibcon#read 3, iclass 15, count 2 2006.174.01:28:40.36#ibcon#about to read 4, iclass 15, count 2 2006.174.01:28:40.36#ibcon#read 4, iclass 15, count 2 2006.174.01:28:40.36#ibcon#about to read 5, iclass 15, count 2 2006.174.01:28:40.36#ibcon#read 5, iclass 15, count 2 2006.174.01:28:40.36#ibcon#about to read 6, iclass 15, count 2 2006.174.01:28:40.36#ibcon#read 6, iclass 15, count 2 2006.174.01:28:40.36#ibcon#end of sib2, iclass 15, count 2 2006.174.01:28:40.36#ibcon#*after write, iclass 15, count 2 2006.174.01:28:40.36#ibcon#*before return 0, iclass 15, count 2 2006.174.01:28:40.36#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.174.01:28:40.36#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.174.01:28:40.36#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.174.01:28:40.36#ibcon#ireg 7 cls_cnt 0 2006.174.01:28:40.36#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.174.01:28:40.48#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.174.01:28:40.48#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.174.01:28:40.48#ibcon#enter wrdev, iclass 15, count 0 2006.174.01:28:40.48#ibcon#first serial, iclass 15, count 0 2006.174.01:28:40.48#ibcon#enter sib2, iclass 15, count 0 2006.174.01:28:40.48#ibcon#flushed, iclass 15, count 0 2006.174.01:28:40.48#ibcon#about to write, iclass 15, count 0 2006.174.01:28:40.48#ibcon#wrote, iclass 15, count 0 2006.174.01:28:40.48#ibcon#about to read 3, iclass 15, count 0 2006.174.01:28:40.50#ibcon#read 3, iclass 15, count 0 2006.174.01:28:40.50#ibcon#about to read 4, iclass 15, count 0 2006.174.01:28:40.50#ibcon#read 4, iclass 15, count 0 2006.174.01:28:40.50#ibcon#about to read 5, iclass 15, count 0 2006.174.01:28:40.50#ibcon#read 5, iclass 15, count 0 2006.174.01:28:40.50#ibcon#about to read 6, iclass 15, count 0 2006.174.01:28:40.50#ibcon#read 6, iclass 15, count 0 2006.174.01:28:40.50#ibcon#end of sib2, iclass 15, count 0 2006.174.01:28:40.50#ibcon#*mode == 0, iclass 15, count 0 2006.174.01:28:40.50#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.174.01:28:40.50#ibcon#[27=USB\r\n] 2006.174.01:28:40.50#ibcon#*before write, iclass 15, count 0 2006.174.01:28:40.50#ibcon#enter sib2, iclass 15, count 0 2006.174.01:28:40.50#ibcon#flushed, iclass 15, count 0 2006.174.01:28:40.50#ibcon#about to write, iclass 15, count 0 2006.174.01:28:40.50#ibcon#wrote, iclass 15, count 0 2006.174.01:28:40.50#ibcon#about to read 3, iclass 15, count 0 2006.174.01:28:40.53#ibcon#read 3, iclass 15, count 0 2006.174.01:28:40.53#ibcon#about to read 4, iclass 15, count 0 2006.174.01:28:40.53#ibcon#read 4, iclass 15, count 0 2006.174.01:28:40.53#ibcon#about to read 5, iclass 15, count 0 2006.174.01:28:40.53#ibcon#read 5, iclass 15, count 0 2006.174.01:28:40.53#ibcon#about to read 6, iclass 15, count 0 2006.174.01:28:40.53#ibcon#read 6, iclass 15, count 0 2006.174.01:28:40.53#ibcon#end of sib2, iclass 15, count 0 2006.174.01:28:40.53#ibcon#*after write, iclass 15, count 0 2006.174.01:28:40.53#ibcon#*before return 0, iclass 15, count 0 2006.174.01:28:40.53#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.174.01:28:40.53#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.174.01:28:40.53#ibcon#about to clear, iclass 15 cls_cnt 0 2006.174.01:28:40.53#ibcon#cleared, iclass 15 cls_cnt 0 2006.174.01:28:40.53$vck44/vabw=wide 2006.174.01:28:40.53#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.174.01:28:40.53#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.174.01:28:40.53#ibcon#ireg 8 cls_cnt 0 2006.174.01:28:40.53#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.174.01:28:40.53#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.174.01:28:40.53#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.174.01:28:40.53#ibcon#enter wrdev, iclass 17, count 0 2006.174.01:28:40.53#ibcon#first serial, iclass 17, count 0 2006.174.01:28:40.53#ibcon#enter sib2, iclass 17, count 0 2006.174.01:28:40.53#ibcon#flushed, iclass 17, count 0 2006.174.01:28:40.53#ibcon#about to write, iclass 17, count 0 2006.174.01:28:40.53#ibcon#wrote, iclass 17, count 0 2006.174.01:28:40.53#ibcon#about to read 3, iclass 17, count 0 2006.174.01:28:40.55#ibcon#read 3, iclass 17, count 0 2006.174.01:28:40.55#ibcon#about to read 4, iclass 17, count 0 2006.174.01:28:40.55#ibcon#read 4, iclass 17, count 0 2006.174.01:28:40.55#ibcon#about to read 5, iclass 17, count 0 2006.174.01:28:40.55#ibcon#read 5, iclass 17, count 0 2006.174.01:28:40.55#ibcon#about to read 6, iclass 17, count 0 2006.174.01:28:40.55#ibcon#read 6, iclass 17, count 0 2006.174.01:28:40.55#ibcon#end of sib2, iclass 17, count 0 2006.174.01:28:40.55#ibcon#*mode == 0, iclass 17, count 0 2006.174.01:28:40.55#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.174.01:28:40.55#ibcon#[25=BW32\r\n] 2006.174.01:28:40.55#ibcon#*before write, iclass 17, count 0 2006.174.01:28:40.55#ibcon#enter sib2, iclass 17, count 0 2006.174.01:28:40.55#ibcon#flushed, iclass 17, count 0 2006.174.01:28:40.55#ibcon#about to write, iclass 17, count 0 2006.174.01:28:40.55#ibcon#wrote, iclass 17, count 0 2006.174.01:28:40.55#ibcon#about to read 3, iclass 17, count 0 2006.174.01:28:40.58#ibcon#read 3, iclass 17, count 0 2006.174.01:28:40.58#ibcon#about to read 4, iclass 17, count 0 2006.174.01:28:40.58#ibcon#read 4, iclass 17, count 0 2006.174.01:28:40.58#ibcon#about to read 5, iclass 17, count 0 2006.174.01:28:40.58#ibcon#read 5, iclass 17, count 0 2006.174.01:28:40.58#ibcon#about to read 6, iclass 17, count 0 2006.174.01:28:40.58#ibcon#read 6, iclass 17, count 0 2006.174.01:28:40.58#ibcon#end of sib2, iclass 17, count 0 2006.174.01:28:40.58#ibcon#*after write, iclass 17, count 0 2006.174.01:28:40.58#ibcon#*before return 0, iclass 17, count 0 2006.174.01:28:40.58#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.174.01:28:40.58#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.174.01:28:40.58#ibcon#about to clear, iclass 17 cls_cnt 0 2006.174.01:28:40.58#ibcon#cleared, iclass 17 cls_cnt 0 2006.174.01:28:40.58$vck44/vbbw=wide 2006.174.01:28:40.58#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.174.01:28:40.58#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.174.01:28:40.58#ibcon#ireg 8 cls_cnt 0 2006.174.01:28:40.58#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.174.01:28:40.65#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.174.01:28:40.65#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.174.01:28:40.65#ibcon#enter wrdev, iclass 19, count 0 2006.174.01:28:40.65#ibcon#first serial, iclass 19, count 0 2006.174.01:28:40.65#ibcon#enter sib2, iclass 19, count 0 2006.174.01:28:40.65#ibcon#flushed, iclass 19, count 0 2006.174.01:28:40.65#ibcon#about to write, iclass 19, count 0 2006.174.01:28:40.65#ibcon#wrote, iclass 19, count 0 2006.174.01:28:40.65#ibcon#about to read 3, iclass 19, count 0 2006.174.01:28:40.67#ibcon#read 3, iclass 19, count 0 2006.174.01:28:40.67#ibcon#about to read 4, iclass 19, count 0 2006.174.01:28:40.67#ibcon#read 4, iclass 19, count 0 2006.174.01:28:40.67#ibcon#about to read 5, iclass 19, count 0 2006.174.01:28:40.67#ibcon#read 5, iclass 19, count 0 2006.174.01:28:40.67#ibcon#about to read 6, iclass 19, count 0 2006.174.01:28:40.67#ibcon#read 6, iclass 19, count 0 2006.174.01:28:40.67#ibcon#end of sib2, iclass 19, count 0 2006.174.01:28:40.67#ibcon#*mode == 0, iclass 19, count 0 2006.174.01:28:40.67#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.174.01:28:40.67#ibcon#[27=BW32\r\n] 2006.174.01:28:40.67#ibcon#*before write, iclass 19, count 0 2006.174.01:28:40.67#ibcon#enter sib2, iclass 19, count 0 2006.174.01:28:40.67#ibcon#flushed, iclass 19, count 0 2006.174.01:28:40.67#ibcon#about to write, iclass 19, count 0 2006.174.01:28:40.67#ibcon#wrote, iclass 19, count 0 2006.174.01:28:40.67#ibcon#about to read 3, iclass 19, count 0 2006.174.01:28:40.70#ibcon#read 3, iclass 19, count 0 2006.174.01:28:40.70#ibcon#about to read 4, iclass 19, count 0 2006.174.01:28:40.70#ibcon#read 4, iclass 19, count 0 2006.174.01:28:40.70#ibcon#about to read 5, iclass 19, count 0 2006.174.01:28:40.70#ibcon#read 5, iclass 19, count 0 2006.174.01:28:40.70#ibcon#about to read 6, iclass 19, count 0 2006.174.01:28:40.70#ibcon#read 6, iclass 19, count 0 2006.174.01:28:40.70#ibcon#end of sib2, iclass 19, count 0 2006.174.01:28:40.70#ibcon#*after write, iclass 19, count 0 2006.174.01:28:40.70#ibcon#*before return 0, iclass 19, count 0 2006.174.01:28:40.70#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.174.01:28:40.70#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.174.01:28:40.70#ibcon#about to clear, iclass 19 cls_cnt 0 2006.174.01:28:40.70#ibcon#cleared, iclass 19 cls_cnt 0 2006.174.01:28:40.70$setupk4/ifdk4 2006.174.01:28:40.70$ifdk4/lo= 2006.174.01:28:40.70$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.174.01:28:40.70$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.174.01:28:40.70$ifdk4/patch= 2006.174.01:28:40.70$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.174.01:28:40.70$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.174.01:28:40.70$setupk4/!*+20s 2006.174.01:28:48.11#abcon#<5=/10 0.7 2.4 25.74 781003.3\r\n> 2006.174.01:28:48.13#abcon#{5=INTERFACE CLEAR} 2006.174.01:28:48.19#abcon#[5=S1D000X0/0*\r\n] 2006.174.01:28:55.21$setupk4/"tpicd 2006.174.01:28:55.21$setupk4/echo=off 2006.174.01:28:55.21$setupk4/xlog=off 2006.174.01:28:55.21:!2006.174.01:31:43 2006.174.01:29:51.13#trakl#Source acquired 2006.174.01:29:52.13#flagr#flagr/antenna,acquired 2006.174.01:31:43.00:preob 2006.174.01:31:44.13/onsource/TRACKING 2006.174.01:31:44.13:!2006.174.01:31:53 2006.174.01:31:53.00:"tape 2006.174.01:31:53.00:"st=record 2006.174.01:31:53.00:data_valid=on 2006.174.01:31:53.00:midob 2006.174.01:31:53.14/onsource/TRACKING 2006.174.01:31:53.14/wx/25.87,1003.3,77 2006.174.01:31:53.28/cable/+6.5017E-03 2006.174.01:31:54.37/va/01,07,usb,yes,49,52 2006.174.01:31:54.37/va/02,06,usb,yes,48,50 2006.174.01:31:54.37/va/03,05,usb,yes,61,64 2006.174.01:31:54.37/va/04,06,usb,yes,51,53 2006.174.01:31:54.37/va/05,04,usb,yes,40,41 2006.174.01:31:54.37/va/06,03,usb,yes,55,55 2006.174.01:31:54.37/va/07,04,usb,yes,45,47 2006.174.01:31:54.37/va/08,04,usb,yes,39,46 2006.174.01:31:54.60/valo/01,524.99,yes,locked 2006.174.01:31:54.60/valo/02,534.99,yes,locked 2006.174.01:31:54.60/valo/03,564.99,yes,locked 2006.174.01:31:54.60/valo/04,624.99,yes,locked 2006.174.01:31:54.60/valo/05,734.99,yes,locked 2006.174.01:31:54.60/valo/06,814.99,yes,locked 2006.174.01:31:54.60/valo/07,864.99,yes,locked 2006.174.01:31:54.60/valo/08,884.99,yes,locked 2006.174.01:31:55.69/vb/01,04,usb,yes,36,33 2006.174.01:31:55.69/vb/02,04,usb,yes,38,38 2006.174.01:31:55.69/vb/03,04,usb,yes,35,38 2006.174.01:31:55.69/vb/04,04,usb,yes,40,39 2006.174.01:31:55.69/vb/05,04,usb,yes,32,34 2006.174.01:31:55.69/vb/06,04,usb,yes,37,33 2006.174.01:31:55.69/vb/07,04,usb,yes,37,36 2006.174.01:31:55.69/vb/08,04,usb,yes,34,38 2006.174.01:31:55.92/vblo/01,629.99,yes,locked 2006.174.01:31:55.92/vblo/02,634.99,yes,locked 2006.174.01:31:55.92/vblo/03,649.99,yes,locked 2006.174.01:31:55.92/vblo/04,679.99,yes,locked 2006.174.01:31:55.92/vblo/05,709.99,yes,locked 2006.174.01:31:55.92/vblo/06,719.99,yes,locked 2006.174.01:31:55.92/vblo/07,734.99,yes,locked 2006.174.01:31:55.92/vblo/08,744.99,yes,locked 2006.174.01:31:56.07/vabw/8 2006.174.01:31:56.22/vbbw/8 2006.174.01:31:56.31/xfe/off,on,15.2 2006.174.01:31:56.68/ifatt/23,28,28,28 2006.174.01:31:57.08/fmout-gps/S +3.77E-07 2006.174.01:31:57.12:!2006.174.01:36:13 2006.174.01:36:13.02:data_valid=off 2006.174.01:36:13.02:"et 2006.174.01:36:13.02:!+3s 2006.174.01:36:16.04:"tape 2006.174.01:36:16.04:postob 2006.174.01:36:16.20/cable/+6.4995E-03 2006.174.01:36:16.21/wx/26.03,1003.3,77 2006.174.01:36:16.26/fmout-gps/S +3.76E-07 2006.174.01:36:16.27:scan_name=174-0137,jd0606,220 2006.174.01:36:16.27:source=0014+813,001708.47,813508.1,2000.0,ccw 2006.174.01:36:17.15#flagr#flagr/antenna,new-source 2006.174.01:36:17.15:checkk5 2006.174.01:36:17.51/chk_autoobs//k5ts1/ autoobs is running! 2006.174.01:36:17.91/chk_autoobs//k5ts2/ autoobs is running! 2006.174.01:36:18.34/chk_autoobs//k5ts3/ autoobs is running! 2006.174.01:36:18.73/chk_autoobs//k5ts4/ autoobs is running! 2006.174.01:36:19.11/chk_obsdata//k5ts1/T1740131??a.dat file size is correct (nominal:1040MB, actual:1036MB). 2006.174.01:36:19.53/chk_obsdata//k5ts2/T1740131??b.dat file size is correct (nominal:1040MB, actual:1036MB). 2006.174.01:36:19.92/chk_obsdata//k5ts3/T1740131??c.dat file size is correct (nominal:1040MB, actual:1036MB). 2006.174.01:36:20.33/chk_obsdata//k5ts4/T1740131??d.dat file size is correct (nominal:1040MB, actual:1036MB). 2006.174.01:36:21.07/k5log//k5ts1_log_newline 2006.174.01:36:21.79/k5log//k5ts2_log_newline 2006.174.01:36:22.50/k5log//k5ts3_log_newline 2006.174.01:36:23.22/k5log//k5ts4_log_newline 2006.174.01:36:23.24/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.174.01:36:23.24:setupk4=1 2006.174.01:36:23.24$setupk4/echo=on 2006.174.01:36:23.24$setupk4/pcalon 2006.174.01:36:23.24$pcalon/"no phase cal control is implemented here 2006.174.01:36:23.24$setupk4/"tpicd=stop 2006.174.01:36:23.24$setupk4/"rec=synch_on 2006.174.01:36:23.24$setupk4/"rec_mode=128 2006.174.01:36:23.24$setupk4/!* 2006.174.01:36:23.24$setupk4/recpk4 2006.174.01:36:23.24$recpk4/recpatch= 2006.174.01:36:23.25$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.174.01:36:23.25$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.174.01:36:23.25$setupk4/vck44 2006.174.01:36:23.25$vck44/valo=1,524.99 2006.174.01:36:23.25#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.174.01:36:23.25#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.174.01:36:23.25#ibcon#ireg 17 cls_cnt 0 2006.174.01:36:23.25#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.174.01:36:23.25#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.174.01:36:23.25#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.174.01:36:23.25#ibcon#enter wrdev, iclass 24, count 0 2006.174.01:36:23.25#ibcon#first serial, iclass 24, count 0 2006.174.01:36:23.25#ibcon#enter sib2, iclass 24, count 0 2006.174.01:36:23.25#ibcon#flushed, iclass 24, count 0 2006.174.01:36:23.25#ibcon#about to write, iclass 24, count 0 2006.174.01:36:23.25#ibcon#wrote, iclass 24, count 0 2006.174.01:36:23.25#ibcon#about to read 3, iclass 24, count 0 2006.174.01:36:23.26#ibcon#read 3, iclass 24, count 0 2006.174.01:36:23.26#ibcon#about to read 4, iclass 24, count 0 2006.174.01:36:23.26#ibcon#read 4, iclass 24, count 0 2006.174.01:36:23.26#ibcon#about to read 5, iclass 24, count 0 2006.174.01:36:23.26#ibcon#read 5, iclass 24, count 0 2006.174.01:36:23.26#ibcon#about to read 6, iclass 24, count 0 2006.174.01:36:23.26#ibcon#read 6, iclass 24, count 0 2006.174.01:36:23.26#ibcon#end of sib2, iclass 24, count 0 2006.174.01:36:23.26#ibcon#*mode == 0, iclass 24, count 0 2006.174.01:36:23.26#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.174.01:36:23.26#ibcon#[26=FRQ=01,524.99\r\n] 2006.174.01:36:23.26#ibcon#*before write, iclass 24, count 0 2006.174.01:36:23.26#ibcon#enter sib2, iclass 24, count 0 2006.174.01:36:23.26#ibcon#flushed, iclass 24, count 0 2006.174.01:36:23.26#ibcon#about to write, iclass 24, count 0 2006.174.01:36:23.26#ibcon#wrote, iclass 24, count 0 2006.174.01:36:23.26#ibcon#about to read 3, iclass 24, count 0 2006.174.01:36:23.31#ibcon#read 3, iclass 24, count 0 2006.174.01:36:23.31#ibcon#about to read 4, iclass 24, count 0 2006.174.01:36:23.31#ibcon#read 4, iclass 24, count 0 2006.174.01:36:23.31#ibcon#about to read 5, iclass 24, count 0 2006.174.01:36:23.31#ibcon#read 5, iclass 24, count 0 2006.174.01:36:23.31#ibcon#about to read 6, iclass 24, count 0 2006.174.01:36:23.31#ibcon#read 6, iclass 24, count 0 2006.174.01:36:23.31#ibcon#end of sib2, iclass 24, count 0 2006.174.01:36:23.31#ibcon#*after write, iclass 24, count 0 2006.174.01:36:23.31#ibcon#*before return 0, iclass 24, count 0 2006.174.01:36:23.31#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.174.01:36:23.31#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.174.01:36:23.31#ibcon#about to clear, iclass 24 cls_cnt 0 2006.174.01:36:23.31#ibcon#cleared, iclass 24 cls_cnt 0 2006.174.01:36:23.31$vck44/va=1,7 2006.174.01:36:23.31#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.174.01:36:23.31#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.174.01:36:23.31#ibcon#ireg 11 cls_cnt 2 2006.174.01:36:23.31#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.174.01:36:23.32#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.174.01:36:23.32#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.174.01:36:23.32#ibcon#enter wrdev, iclass 26, count 2 2006.174.01:36:23.32#ibcon#first serial, iclass 26, count 2 2006.174.01:36:23.32#ibcon#enter sib2, iclass 26, count 2 2006.174.01:36:23.32#ibcon#flushed, iclass 26, count 2 2006.174.01:36:23.32#ibcon#about to write, iclass 26, count 2 2006.174.01:36:23.32#ibcon#wrote, iclass 26, count 2 2006.174.01:36:23.32#ibcon#about to read 3, iclass 26, count 2 2006.174.01:36:23.33#ibcon#read 3, iclass 26, count 2 2006.174.01:36:23.33#ibcon#about to read 4, iclass 26, count 2 2006.174.01:36:23.33#ibcon#read 4, iclass 26, count 2 2006.174.01:36:23.33#ibcon#about to read 5, iclass 26, count 2 2006.174.01:36:23.33#ibcon#read 5, iclass 26, count 2 2006.174.01:36:23.33#ibcon#about to read 6, iclass 26, count 2 2006.174.01:36:23.33#ibcon#read 6, iclass 26, count 2 2006.174.01:36:23.33#ibcon#end of sib2, iclass 26, count 2 2006.174.01:36:23.33#ibcon#*mode == 0, iclass 26, count 2 2006.174.01:36:23.33#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.174.01:36:23.33#ibcon#[25=AT01-07\r\n] 2006.174.01:36:23.33#ibcon#*before write, iclass 26, count 2 2006.174.01:36:23.33#ibcon#enter sib2, iclass 26, count 2 2006.174.01:36:23.33#ibcon#flushed, iclass 26, count 2 2006.174.01:36:23.33#ibcon#about to write, iclass 26, count 2 2006.174.01:36:23.33#ibcon#wrote, iclass 26, count 2 2006.174.01:36:23.33#ibcon#about to read 3, iclass 26, count 2 2006.174.01:36:23.36#ibcon#read 3, iclass 26, count 2 2006.174.01:36:23.36#ibcon#about to read 4, iclass 26, count 2 2006.174.01:36:23.36#ibcon#read 4, iclass 26, count 2 2006.174.01:36:23.36#ibcon#about to read 5, iclass 26, count 2 2006.174.01:36:23.36#ibcon#read 5, iclass 26, count 2 2006.174.01:36:23.36#ibcon#about to read 6, iclass 26, count 2 2006.174.01:36:23.36#ibcon#read 6, iclass 26, count 2 2006.174.01:36:23.36#ibcon#end of sib2, iclass 26, count 2 2006.174.01:36:23.36#ibcon#*after write, iclass 26, count 2 2006.174.01:36:23.36#ibcon#*before return 0, iclass 26, count 2 2006.174.01:36:23.36#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.174.01:36:23.36#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.174.01:36:23.36#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.174.01:36:23.36#ibcon#ireg 7 cls_cnt 0 2006.174.01:36:23.36#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.174.01:36:23.48#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.174.01:36:23.48#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.174.01:36:23.48#ibcon#enter wrdev, iclass 26, count 0 2006.174.01:36:23.48#ibcon#first serial, iclass 26, count 0 2006.174.01:36:23.48#ibcon#enter sib2, iclass 26, count 0 2006.174.01:36:23.48#ibcon#flushed, iclass 26, count 0 2006.174.01:36:23.48#ibcon#about to write, iclass 26, count 0 2006.174.01:36:23.48#ibcon#wrote, iclass 26, count 0 2006.174.01:36:23.48#ibcon#about to read 3, iclass 26, count 0 2006.174.01:36:23.50#ibcon#read 3, iclass 26, count 0 2006.174.01:36:23.50#ibcon#about to read 4, iclass 26, count 0 2006.174.01:36:23.50#ibcon#read 4, iclass 26, count 0 2006.174.01:36:23.50#ibcon#about to read 5, iclass 26, count 0 2006.174.01:36:23.50#ibcon#read 5, iclass 26, count 0 2006.174.01:36:23.50#ibcon#about to read 6, iclass 26, count 0 2006.174.01:36:23.50#ibcon#read 6, iclass 26, count 0 2006.174.01:36:23.50#ibcon#end of sib2, iclass 26, count 0 2006.174.01:36:23.50#ibcon#*mode == 0, iclass 26, count 0 2006.174.01:36:23.50#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.174.01:36:23.50#ibcon#[25=USB\r\n] 2006.174.01:36:23.50#ibcon#*before write, iclass 26, count 0 2006.174.01:36:23.50#ibcon#enter sib2, iclass 26, count 0 2006.174.01:36:23.50#ibcon#flushed, iclass 26, count 0 2006.174.01:36:23.50#ibcon#about to write, iclass 26, count 0 2006.174.01:36:23.50#ibcon#wrote, iclass 26, count 0 2006.174.01:36:23.50#ibcon#about to read 3, iclass 26, count 0 2006.174.01:36:23.53#ibcon#read 3, iclass 26, count 0 2006.174.01:36:23.53#ibcon#about to read 4, iclass 26, count 0 2006.174.01:36:23.53#ibcon#read 4, iclass 26, count 0 2006.174.01:36:23.53#ibcon#about to read 5, iclass 26, count 0 2006.174.01:36:23.53#ibcon#read 5, iclass 26, count 0 2006.174.01:36:23.53#ibcon#about to read 6, iclass 26, count 0 2006.174.01:36:23.53#ibcon#read 6, iclass 26, count 0 2006.174.01:36:23.53#ibcon#end of sib2, iclass 26, count 0 2006.174.01:36:23.53#ibcon#*after write, iclass 26, count 0 2006.174.01:36:23.53#ibcon#*before return 0, iclass 26, count 0 2006.174.01:36:23.53#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.174.01:36:23.53#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.174.01:36:23.53#ibcon#about to clear, iclass 26 cls_cnt 0 2006.174.01:36:23.53#ibcon#cleared, iclass 26 cls_cnt 0 2006.174.01:36:23.53$vck44/valo=2,534.99 2006.174.01:36:23.53#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.174.01:36:23.53#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.174.01:36:23.53#ibcon#ireg 17 cls_cnt 0 2006.174.01:36:23.53#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.174.01:36:23.54#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.174.01:36:23.54#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.174.01:36:23.54#ibcon#enter wrdev, iclass 28, count 0 2006.174.01:36:23.54#ibcon#first serial, iclass 28, count 0 2006.174.01:36:23.54#ibcon#enter sib2, iclass 28, count 0 2006.174.01:36:23.54#ibcon#flushed, iclass 28, count 0 2006.174.01:36:23.54#ibcon#about to write, iclass 28, count 0 2006.174.01:36:23.54#ibcon#wrote, iclass 28, count 0 2006.174.01:36:23.54#ibcon#about to read 3, iclass 28, count 0 2006.174.01:36:23.55#ibcon#read 3, iclass 28, count 0 2006.174.01:36:23.55#ibcon#about to read 4, iclass 28, count 0 2006.174.01:36:23.55#ibcon#read 4, iclass 28, count 0 2006.174.01:36:23.55#ibcon#about to read 5, iclass 28, count 0 2006.174.01:36:23.55#ibcon#read 5, iclass 28, count 0 2006.174.01:36:23.55#ibcon#about to read 6, iclass 28, count 0 2006.174.01:36:23.55#ibcon#read 6, iclass 28, count 0 2006.174.01:36:23.55#ibcon#end of sib2, iclass 28, count 0 2006.174.01:36:23.55#ibcon#*mode == 0, iclass 28, count 0 2006.174.01:36:23.55#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.174.01:36:23.55#ibcon#[26=FRQ=02,534.99\r\n] 2006.174.01:36:23.55#ibcon#*before write, iclass 28, count 0 2006.174.01:36:23.55#ibcon#enter sib2, iclass 28, count 0 2006.174.01:36:23.55#ibcon#flushed, iclass 28, count 0 2006.174.01:36:23.55#ibcon#about to write, iclass 28, count 0 2006.174.01:36:23.55#ibcon#wrote, iclass 28, count 0 2006.174.01:36:23.55#ibcon#about to read 3, iclass 28, count 0 2006.174.01:36:23.59#ibcon#read 3, iclass 28, count 0 2006.174.01:36:23.59#ibcon#about to read 4, iclass 28, count 0 2006.174.01:36:23.59#ibcon#read 4, iclass 28, count 0 2006.174.01:36:23.59#ibcon#about to read 5, iclass 28, count 0 2006.174.01:36:23.59#ibcon#read 5, iclass 28, count 0 2006.174.01:36:23.59#ibcon#about to read 6, iclass 28, count 0 2006.174.01:36:23.59#ibcon#read 6, iclass 28, count 0 2006.174.01:36:23.59#ibcon#end of sib2, iclass 28, count 0 2006.174.01:36:23.59#ibcon#*after write, iclass 28, count 0 2006.174.01:36:23.59#ibcon#*before return 0, iclass 28, count 0 2006.174.01:36:23.59#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.174.01:36:23.59#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.174.01:36:23.59#ibcon#about to clear, iclass 28 cls_cnt 0 2006.174.01:36:23.59#ibcon#cleared, iclass 28 cls_cnt 0 2006.174.01:36:23.59$vck44/va=2,6 2006.174.01:36:23.59#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.174.01:36:23.59#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.174.01:36:23.59#ibcon#ireg 11 cls_cnt 2 2006.174.01:36:23.60#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.174.01:36:23.64#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.174.01:36:23.64#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.174.01:36:23.64#ibcon#enter wrdev, iclass 30, count 2 2006.174.01:36:23.64#ibcon#first serial, iclass 30, count 2 2006.174.01:36:23.64#ibcon#enter sib2, iclass 30, count 2 2006.174.01:36:23.64#ibcon#flushed, iclass 30, count 2 2006.174.01:36:23.64#ibcon#about to write, iclass 30, count 2 2006.174.01:36:23.64#ibcon#wrote, iclass 30, count 2 2006.174.01:36:23.64#ibcon#about to read 3, iclass 30, count 2 2006.174.01:36:23.66#ibcon#read 3, iclass 30, count 2 2006.174.01:36:23.66#ibcon#about to read 4, iclass 30, count 2 2006.174.01:36:23.66#ibcon#read 4, iclass 30, count 2 2006.174.01:36:23.66#ibcon#about to read 5, iclass 30, count 2 2006.174.01:36:23.66#ibcon#read 5, iclass 30, count 2 2006.174.01:36:23.66#ibcon#about to read 6, iclass 30, count 2 2006.174.01:36:23.66#ibcon#read 6, iclass 30, count 2 2006.174.01:36:23.66#ibcon#end of sib2, iclass 30, count 2 2006.174.01:36:23.66#ibcon#*mode == 0, iclass 30, count 2 2006.174.01:36:23.66#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.174.01:36:23.66#ibcon#[25=AT02-06\r\n] 2006.174.01:36:23.66#ibcon#*before write, iclass 30, count 2 2006.174.01:36:23.66#ibcon#enter sib2, iclass 30, count 2 2006.174.01:36:23.66#ibcon#flushed, iclass 30, count 2 2006.174.01:36:23.66#ibcon#about to write, iclass 30, count 2 2006.174.01:36:23.66#ibcon#wrote, iclass 30, count 2 2006.174.01:36:23.66#ibcon#about to read 3, iclass 30, count 2 2006.174.01:36:23.69#ibcon#read 3, iclass 30, count 2 2006.174.01:36:23.69#ibcon#about to read 4, iclass 30, count 2 2006.174.01:36:23.69#ibcon#read 4, iclass 30, count 2 2006.174.01:36:23.69#ibcon#about to read 5, iclass 30, count 2 2006.174.01:36:23.69#ibcon#read 5, iclass 30, count 2 2006.174.01:36:23.69#ibcon#about to read 6, iclass 30, count 2 2006.174.01:36:23.69#ibcon#read 6, iclass 30, count 2 2006.174.01:36:23.69#ibcon#end of sib2, iclass 30, count 2 2006.174.01:36:23.69#ibcon#*after write, iclass 30, count 2 2006.174.01:36:23.69#ibcon#*before return 0, iclass 30, count 2 2006.174.01:36:23.69#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.174.01:36:23.69#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.174.01:36:23.69#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.174.01:36:23.69#ibcon#ireg 7 cls_cnt 0 2006.174.01:36:23.69#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.174.01:36:23.81#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.174.01:36:23.81#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.174.01:36:23.81#ibcon#enter wrdev, iclass 30, count 0 2006.174.01:36:23.81#ibcon#first serial, iclass 30, count 0 2006.174.01:36:23.81#ibcon#enter sib2, iclass 30, count 0 2006.174.01:36:23.81#ibcon#flushed, iclass 30, count 0 2006.174.01:36:23.81#ibcon#about to write, iclass 30, count 0 2006.174.01:36:23.81#ibcon#wrote, iclass 30, count 0 2006.174.01:36:23.81#ibcon#about to read 3, iclass 30, count 0 2006.174.01:36:23.83#ibcon#read 3, iclass 30, count 0 2006.174.01:36:23.83#ibcon#about to read 4, iclass 30, count 0 2006.174.01:36:23.83#ibcon#read 4, iclass 30, count 0 2006.174.01:36:23.83#ibcon#about to read 5, iclass 30, count 0 2006.174.01:36:23.83#ibcon#read 5, iclass 30, count 0 2006.174.01:36:23.83#ibcon#about to read 6, iclass 30, count 0 2006.174.01:36:23.83#ibcon#read 6, iclass 30, count 0 2006.174.01:36:23.83#ibcon#end of sib2, iclass 30, count 0 2006.174.01:36:23.83#ibcon#*mode == 0, iclass 30, count 0 2006.174.01:36:23.83#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.174.01:36:23.83#ibcon#[25=USB\r\n] 2006.174.01:36:23.83#ibcon#*before write, iclass 30, count 0 2006.174.01:36:23.83#ibcon#enter sib2, iclass 30, count 0 2006.174.01:36:23.83#ibcon#flushed, iclass 30, count 0 2006.174.01:36:23.83#ibcon#about to write, iclass 30, count 0 2006.174.01:36:23.83#ibcon#wrote, iclass 30, count 0 2006.174.01:36:23.83#ibcon#about to read 3, iclass 30, count 0 2006.174.01:36:23.86#ibcon#read 3, iclass 30, count 0 2006.174.01:36:23.86#ibcon#about to read 4, iclass 30, count 0 2006.174.01:36:23.86#ibcon#read 4, iclass 30, count 0 2006.174.01:36:23.86#ibcon#about to read 5, iclass 30, count 0 2006.174.01:36:23.86#ibcon#read 5, iclass 30, count 0 2006.174.01:36:23.86#ibcon#about to read 6, iclass 30, count 0 2006.174.01:36:23.86#ibcon#read 6, iclass 30, count 0 2006.174.01:36:23.86#ibcon#end of sib2, iclass 30, count 0 2006.174.01:36:23.86#ibcon#*after write, iclass 30, count 0 2006.174.01:36:23.86#ibcon#*before return 0, iclass 30, count 0 2006.174.01:36:23.86#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.174.01:36:23.86#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.174.01:36:23.86#ibcon#about to clear, iclass 30 cls_cnt 0 2006.174.01:36:23.86#ibcon#cleared, iclass 30 cls_cnt 0 2006.174.01:36:23.86$vck44/valo=3,564.99 2006.174.01:36:23.86#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.174.01:36:23.86#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.174.01:36:23.86#ibcon#ireg 17 cls_cnt 0 2006.174.01:36:23.86#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.174.01:36:23.86#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.174.01:36:23.87#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.174.01:36:23.87#ibcon#enter wrdev, iclass 32, count 0 2006.174.01:36:23.87#ibcon#first serial, iclass 32, count 0 2006.174.01:36:23.87#ibcon#enter sib2, iclass 32, count 0 2006.174.01:36:23.87#ibcon#flushed, iclass 32, count 0 2006.174.01:36:23.87#ibcon#about to write, iclass 32, count 0 2006.174.01:36:23.87#ibcon#wrote, iclass 32, count 0 2006.174.01:36:23.87#ibcon#about to read 3, iclass 32, count 0 2006.174.01:36:23.88#ibcon#read 3, iclass 32, count 0 2006.174.01:36:23.88#ibcon#about to read 4, iclass 32, count 0 2006.174.01:36:23.88#ibcon#read 4, iclass 32, count 0 2006.174.01:36:23.88#ibcon#about to read 5, iclass 32, count 0 2006.174.01:36:23.88#ibcon#read 5, iclass 32, count 0 2006.174.01:36:23.88#ibcon#about to read 6, iclass 32, count 0 2006.174.01:36:23.88#ibcon#read 6, iclass 32, count 0 2006.174.01:36:23.88#ibcon#end of sib2, iclass 32, count 0 2006.174.01:36:23.88#ibcon#*mode == 0, iclass 32, count 0 2006.174.01:36:23.88#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.174.01:36:23.88#ibcon#[26=FRQ=03,564.99\r\n] 2006.174.01:36:23.88#ibcon#*before write, iclass 32, count 0 2006.174.01:36:23.88#ibcon#enter sib2, iclass 32, count 0 2006.174.01:36:23.88#ibcon#flushed, iclass 32, count 0 2006.174.01:36:23.88#ibcon#about to write, iclass 32, count 0 2006.174.01:36:23.88#ibcon#wrote, iclass 32, count 0 2006.174.01:36:23.88#ibcon#about to read 3, iclass 32, count 0 2006.174.01:36:23.92#ibcon#read 3, iclass 32, count 0 2006.174.01:36:23.92#ibcon#about to read 4, iclass 32, count 0 2006.174.01:36:23.92#ibcon#read 4, iclass 32, count 0 2006.174.01:36:23.92#ibcon#about to read 5, iclass 32, count 0 2006.174.01:36:23.92#ibcon#read 5, iclass 32, count 0 2006.174.01:36:23.92#ibcon#about to read 6, iclass 32, count 0 2006.174.01:36:23.92#ibcon#read 6, iclass 32, count 0 2006.174.01:36:23.92#ibcon#end of sib2, iclass 32, count 0 2006.174.01:36:23.92#ibcon#*after write, iclass 32, count 0 2006.174.01:36:23.92#ibcon#*before return 0, iclass 32, count 0 2006.174.01:36:23.92#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.174.01:36:23.92#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.174.01:36:23.92#ibcon#about to clear, iclass 32 cls_cnt 0 2006.174.01:36:23.92#ibcon#cleared, iclass 32 cls_cnt 0 2006.174.01:36:23.92$vck44/va=3,5 2006.174.01:36:23.92#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.174.01:36:23.92#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.174.01:36:23.92#ibcon#ireg 11 cls_cnt 2 2006.174.01:36:23.92#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.174.01:36:23.98#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.174.01:36:23.98#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.174.01:36:23.98#ibcon#enter wrdev, iclass 34, count 2 2006.174.01:36:23.98#ibcon#first serial, iclass 34, count 2 2006.174.01:36:23.98#ibcon#enter sib2, iclass 34, count 2 2006.174.01:36:23.98#ibcon#flushed, iclass 34, count 2 2006.174.01:36:23.98#ibcon#about to write, iclass 34, count 2 2006.174.01:36:23.98#ibcon#wrote, iclass 34, count 2 2006.174.01:36:23.98#ibcon#about to read 3, iclass 34, count 2 2006.174.01:36:24.00#ibcon#read 3, iclass 34, count 2 2006.174.01:36:24.00#ibcon#about to read 4, iclass 34, count 2 2006.174.01:36:24.00#ibcon#read 4, iclass 34, count 2 2006.174.01:36:24.00#ibcon#about to read 5, iclass 34, count 2 2006.174.01:36:24.00#ibcon#read 5, iclass 34, count 2 2006.174.01:36:24.00#ibcon#about to read 6, iclass 34, count 2 2006.174.01:36:24.00#ibcon#read 6, iclass 34, count 2 2006.174.01:36:24.00#ibcon#end of sib2, iclass 34, count 2 2006.174.01:36:24.00#ibcon#*mode == 0, iclass 34, count 2 2006.174.01:36:24.00#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.174.01:36:24.00#ibcon#[25=AT03-05\r\n] 2006.174.01:36:24.00#ibcon#*before write, iclass 34, count 2 2006.174.01:36:24.00#ibcon#enter sib2, iclass 34, count 2 2006.174.01:36:24.00#ibcon#flushed, iclass 34, count 2 2006.174.01:36:24.00#ibcon#about to write, iclass 34, count 2 2006.174.01:36:24.00#ibcon#wrote, iclass 34, count 2 2006.174.01:36:24.00#ibcon#about to read 3, iclass 34, count 2 2006.174.01:36:24.03#ibcon#read 3, iclass 34, count 2 2006.174.01:36:24.03#ibcon#about to read 4, iclass 34, count 2 2006.174.01:36:24.03#ibcon#read 4, iclass 34, count 2 2006.174.01:36:24.03#ibcon#about to read 5, iclass 34, count 2 2006.174.01:36:24.03#ibcon#read 5, iclass 34, count 2 2006.174.01:36:24.03#ibcon#about to read 6, iclass 34, count 2 2006.174.01:36:24.03#ibcon#read 6, iclass 34, count 2 2006.174.01:36:24.03#ibcon#end of sib2, iclass 34, count 2 2006.174.01:36:24.03#ibcon#*after write, iclass 34, count 2 2006.174.01:36:24.03#ibcon#*before return 0, iclass 34, count 2 2006.174.01:36:24.03#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.174.01:36:24.03#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.174.01:36:24.03#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.174.01:36:24.03#ibcon#ireg 7 cls_cnt 0 2006.174.01:36:24.03#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.174.01:36:24.15#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.174.01:36:24.15#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.174.01:36:24.15#ibcon#enter wrdev, iclass 34, count 0 2006.174.01:36:24.15#ibcon#first serial, iclass 34, count 0 2006.174.01:36:24.15#ibcon#enter sib2, iclass 34, count 0 2006.174.01:36:24.15#ibcon#flushed, iclass 34, count 0 2006.174.01:36:24.15#ibcon#about to write, iclass 34, count 0 2006.174.01:36:24.15#ibcon#wrote, iclass 34, count 0 2006.174.01:36:24.15#ibcon#about to read 3, iclass 34, count 0 2006.174.01:36:24.17#ibcon#read 3, iclass 34, count 0 2006.174.01:36:24.17#ibcon#about to read 4, iclass 34, count 0 2006.174.01:36:24.17#ibcon#read 4, iclass 34, count 0 2006.174.01:36:24.17#ibcon#about to read 5, iclass 34, count 0 2006.174.01:36:24.17#ibcon#read 5, iclass 34, count 0 2006.174.01:36:24.17#ibcon#about to read 6, iclass 34, count 0 2006.174.01:36:24.17#ibcon#read 6, iclass 34, count 0 2006.174.01:36:24.17#ibcon#end of sib2, iclass 34, count 0 2006.174.01:36:24.17#ibcon#*mode == 0, iclass 34, count 0 2006.174.01:36:24.17#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.174.01:36:24.17#ibcon#[25=USB\r\n] 2006.174.01:36:24.17#ibcon#*before write, iclass 34, count 0 2006.174.01:36:24.17#ibcon#enter sib2, iclass 34, count 0 2006.174.01:36:24.17#ibcon#flushed, iclass 34, count 0 2006.174.01:36:24.17#ibcon#about to write, iclass 34, count 0 2006.174.01:36:24.17#ibcon#wrote, iclass 34, count 0 2006.174.01:36:24.17#ibcon#about to read 3, iclass 34, count 0 2006.174.01:36:24.20#ibcon#read 3, iclass 34, count 0 2006.174.01:36:24.20#ibcon#about to read 4, iclass 34, count 0 2006.174.01:36:24.20#ibcon#read 4, iclass 34, count 0 2006.174.01:36:24.20#ibcon#about to read 5, iclass 34, count 0 2006.174.01:36:24.20#ibcon#read 5, iclass 34, count 0 2006.174.01:36:24.20#ibcon#about to read 6, iclass 34, count 0 2006.174.01:36:24.20#ibcon#read 6, iclass 34, count 0 2006.174.01:36:24.20#ibcon#end of sib2, iclass 34, count 0 2006.174.01:36:24.20#ibcon#*after write, iclass 34, count 0 2006.174.01:36:24.20#ibcon#*before return 0, iclass 34, count 0 2006.174.01:36:24.20#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.174.01:36:24.20#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.174.01:36:24.20#ibcon#about to clear, iclass 34 cls_cnt 0 2006.174.01:36:24.20#ibcon#cleared, iclass 34 cls_cnt 0 2006.174.01:36:24.20$vck44/valo=4,624.99 2006.174.01:36:24.21#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.174.01:36:24.21#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.174.01:36:24.21#ibcon#ireg 17 cls_cnt 0 2006.174.01:36:24.21#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.174.01:36:24.21#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.174.01:36:24.21#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.174.01:36:24.21#ibcon#enter wrdev, iclass 36, count 0 2006.174.01:36:24.21#ibcon#first serial, iclass 36, count 0 2006.174.01:36:24.21#ibcon#enter sib2, iclass 36, count 0 2006.174.01:36:24.21#ibcon#flushed, iclass 36, count 0 2006.174.01:36:24.21#ibcon#about to write, iclass 36, count 0 2006.174.01:36:24.21#ibcon#wrote, iclass 36, count 0 2006.174.01:36:24.21#ibcon#about to read 3, iclass 36, count 0 2006.174.01:36:24.22#ibcon#read 3, iclass 36, count 0 2006.174.01:36:24.22#ibcon#about to read 4, iclass 36, count 0 2006.174.01:36:24.22#ibcon#read 4, iclass 36, count 0 2006.174.01:36:24.22#ibcon#about to read 5, iclass 36, count 0 2006.174.01:36:24.22#ibcon#read 5, iclass 36, count 0 2006.174.01:36:24.22#ibcon#about to read 6, iclass 36, count 0 2006.174.01:36:24.22#ibcon#read 6, iclass 36, count 0 2006.174.01:36:24.22#ibcon#end of sib2, iclass 36, count 0 2006.174.01:36:24.22#ibcon#*mode == 0, iclass 36, count 0 2006.174.01:36:24.22#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.174.01:36:24.22#ibcon#[26=FRQ=04,624.99\r\n] 2006.174.01:36:24.22#ibcon#*before write, iclass 36, count 0 2006.174.01:36:24.22#ibcon#enter sib2, iclass 36, count 0 2006.174.01:36:24.22#ibcon#flushed, iclass 36, count 0 2006.174.01:36:24.22#ibcon#about to write, iclass 36, count 0 2006.174.01:36:24.22#ibcon#wrote, iclass 36, count 0 2006.174.01:36:24.22#ibcon#about to read 3, iclass 36, count 0 2006.174.01:36:24.26#ibcon#read 3, iclass 36, count 0 2006.174.01:36:24.26#ibcon#about to read 4, iclass 36, count 0 2006.174.01:36:24.26#ibcon#read 4, iclass 36, count 0 2006.174.01:36:24.26#ibcon#about to read 5, iclass 36, count 0 2006.174.01:36:24.26#ibcon#read 5, iclass 36, count 0 2006.174.01:36:24.26#ibcon#about to read 6, iclass 36, count 0 2006.174.01:36:24.26#ibcon#read 6, iclass 36, count 0 2006.174.01:36:24.26#ibcon#end of sib2, iclass 36, count 0 2006.174.01:36:24.26#ibcon#*after write, iclass 36, count 0 2006.174.01:36:24.26#ibcon#*before return 0, iclass 36, count 0 2006.174.01:36:24.26#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.174.01:36:24.26#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.174.01:36:24.26#ibcon#about to clear, iclass 36 cls_cnt 0 2006.174.01:36:24.26#ibcon#cleared, iclass 36 cls_cnt 0 2006.174.01:36:24.26$vck44/va=4,6 2006.174.01:36:24.26#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.174.01:36:24.26#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.174.01:36:24.26#ibcon#ireg 11 cls_cnt 2 2006.174.01:36:24.27#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.174.01:36:24.31#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.174.01:36:24.31#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.174.01:36:24.31#ibcon#enter wrdev, iclass 38, count 2 2006.174.01:36:24.31#ibcon#first serial, iclass 38, count 2 2006.174.01:36:24.31#ibcon#enter sib2, iclass 38, count 2 2006.174.01:36:24.31#ibcon#flushed, iclass 38, count 2 2006.174.01:36:24.31#ibcon#about to write, iclass 38, count 2 2006.174.01:36:24.31#ibcon#wrote, iclass 38, count 2 2006.174.01:36:24.31#ibcon#about to read 3, iclass 38, count 2 2006.174.01:36:24.33#ibcon#read 3, iclass 38, count 2 2006.174.01:36:24.33#ibcon#about to read 4, iclass 38, count 2 2006.174.01:36:24.33#ibcon#read 4, iclass 38, count 2 2006.174.01:36:24.33#ibcon#about to read 5, iclass 38, count 2 2006.174.01:36:24.33#ibcon#read 5, iclass 38, count 2 2006.174.01:36:24.33#ibcon#about to read 6, iclass 38, count 2 2006.174.01:36:24.33#ibcon#read 6, iclass 38, count 2 2006.174.01:36:24.33#ibcon#end of sib2, iclass 38, count 2 2006.174.01:36:24.33#ibcon#*mode == 0, iclass 38, count 2 2006.174.01:36:24.33#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.174.01:36:24.33#ibcon#[25=AT04-06\r\n] 2006.174.01:36:24.33#ibcon#*before write, iclass 38, count 2 2006.174.01:36:24.33#ibcon#enter sib2, iclass 38, count 2 2006.174.01:36:24.33#ibcon#flushed, iclass 38, count 2 2006.174.01:36:24.33#ibcon#about to write, iclass 38, count 2 2006.174.01:36:24.33#ibcon#wrote, iclass 38, count 2 2006.174.01:36:24.33#ibcon#about to read 3, iclass 38, count 2 2006.174.01:36:24.36#ibcon#read 3, iclass 38, count 2 2006.174.01:36:24.36#ibcon#about to read 4, iclass 38, count 2 2006.174.01:36:24.36#ibcon#read 4, iclass 38, count 2 2006.174.01:36:24.36#ibcon#about to read 5, iclass 38, count 2 2006.174.01:36:24.36#ibcon#read 5, iclass 38, count 2 2006.174.01:36:24.36#ibcon#about to read 6, iclass 38, count 2 2006.174.01:36:24.36#ibcon#read 6, iclass 38, count 2 2006.174.01:36:24.36#ibcon#end of sib2, iclass 38, count 2 2006.174.01:36:24.36#ibcon#*after write, iclass 38, count 2 2006.174.01:36:24.36#ibcon#*before return 0, iclass 38, count 2 2006.174.01:36:24.36#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.174.01:36:24.36#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.174.01:36:24.36#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.174.01:36:24.36#ibcon#ireg 7 cls_cnt 0 2006.174.01:36:24.36#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.174.01:36:24.48#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.174.01:36:24.48#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.174.01:36:24.48#ibcon#enter wrdev, iclass 38, count 0 2006.174.01:36:24.48#ibcon#first serial, iclass 38, count 0 2006.174.01:36:24.48#ibcon#enter sib2, iclass 38, count 0 2006.174.01:36:24.48#ibcon#flushed, iclass 38, count 0 2006.174.01:36:24.48#ibcon#about to write, iclass 38, count 0 2006.174.01:36:24.48#ibcon#wrote, iclass 38, count 0 2006.174.01:36:24.48#ibcon#about to read 3, iclass 38, count 0 2006.174.01:36:24.50#ibcon#read 3, iclass 38, count 0 2006.174.01:36:24.50#ibcon#about to read 4, iclass 38, count 0 2006.174.01:36:24.50#ibcon#read 4, iclass 38, count 0 2006.174.01:36:24.50#ibcon#about to read 5, iclass 38, count 0 2006.174.01:36:24.50#ibcon#read 5, iclass 38, count 0 2006.174.01:36:24.50#ibcon#about to read 6, iclass 38, count 0 2006.174.01:36:24.50#ibcon#read 6, iclass 38, count 0 2006.174.01:36:24.50#ibcon#end of sib2, iclass 38, count 0 2006.174.01:36:24.50#ibcon#*mode == 0, iclass 38, count 0 2006.174.01:36:24.50#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.174.01:36:24.50#ibcon#[25=USB\r\n] 2006.174.01:36:24.50#ibcon#*before write, iclass 38, count 0 2006.174.01:36:24.50#ibcon#enter sib2, iclass 38, count 0 2006.174.01:36:24.50#ibcon#flushed, iclass 38, count 0 2006.174.01:36:24.50#ibcon#about to write, iclass 38, count 0 2006.174.01:36:24.50#ibcon#wrote, iclass 38, count 0 2006.174.01:36:24.50#ibcon#about to read 3, iclass 38, count 0 2006.174.01:36:24.53#ibcon#read 3, iclass 38, count 0 2006.174.01:36:24.53#ibcon#about to read 4, iclass 38, count 0 2006.174.01:36:24.53#ibcon#read 4, iclass 38, count 0 2006.174.01:36:24.53#ibcon#about to read 5, iclass 38, count 0 2006.174.01:36:24.53#ibcon#read 5, iclass 38, count 0 2006.174.01:36:24.53#ibcon#about to read 6, iclass 38, count 0 2006.174.01:36:24.53#ibcon#read 6, iclass 38, count 0 2006.174.01:36:24.53#ibcon#end of sib2, iclass 38, count 0 2006.174.01:36:24.53#ibcon#*after write, iclass 38, count 0 2006.174.01:36:24.53#ibcon#*before return 0, iclass 38, count 0 2006.174.01:36:24.53#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.174.01:36:24.53#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.174.01:36:24.53#ibcon#about to clear, iclass 38 cls_cnt 0 2006.174.01:36:24.53#ibcon#cleared, iclass 38 cls_cnt 0 2006.174.01:36:24.53$vck44/valo=5,734.99 2006.174.01:36:24.53#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.174.01:36:24.53#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.174.01:36:24.53#ibcon#ireg 17 cls_cnt 0 2006.174.01:36:24.53#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.174.01:36:24.54#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.174.01:36:24.54#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.174.01:36:24.54#ibcon#enter wrdev, iclass 40, count 0 2006.174.01:36:24.54#ibcon#first serial, iclass 40, count 0 2006.174.01:36:24.54#ibcon#enter sib2, iclass 40, count 0 2006.174.01:36:24.54#ibcon#flushed, iclass 40, count 0 2006.174.01:36:24.54#ibcon#about to write, iclass 40, count 0 2006.174.01:36:24.54#ibcon#wrote, iclass 40, count 0 2006.174.01:36:24.54#ibcon#about to read 3, iclass 40, count 0 2006.174.01:36:24.55#ibcon#read 3, iclass 40, count 0 2006.174.01:36:24.55#ibcon#about to read 4, iclass 40, count 0 2006.174.01:36:24.55#ibcon#read 4, iclass 40, count 0 2006.174.01:36:24.55#ibcon#about to read 5, iclass 40, count 0 2006.174.01:36:24.55#ibcon#read 5, iclass 40, count 0 2006.174.01:36:24.55#ibcon#about to read 6, iclass 40, count 0 2006.174.01:36:24.55#ibcon#read 6, iclass 40, count 0 2006.174.01:36:24.55#ibcon#end of sib2, iclass 40, count 0 2006.174.01:36:24.55#ibcon#*mode == 0, iclass 40, count 0 2006.174.01:36:24.55#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.174.01:36:24.55#ibcon#[26=FRQ=05,734.99\r\n] 2006.174.01:36:24.55#ibcon#*before write, iclass 40, count 0 2006.174.01:36:24.55#ibcon#enter sib2, iclass 40, count 0 2006.174.01:36:24.55#ibcon#flushed, iclass 40, count 0 2006.174.01:36:24.55#ibcon#about to write, iclass 40, count 0 2006.174.01:36:24.55#ibcon#wrote, iclass 40, count 0 2006.174.01:36:24.55#ibcon#about to read 3, iclass 40, count 0 2006.174.01:36:24.59#ibcon#read 3, iclass 40, count 0 2006.174.01:36:24.59#ibcon#about to read 4, iclass 40, count 0 2006.174.01:36:24.59#ibcon#read 4, iclass 40, count 0 2006.174.01:36:24.59#ibcon#about to read 5, iclass 40, count 0 2006.174.01:36:24.59#ibcon#read 5, iclass 40, count 0 2006.174.01:36:24.59#ibcon#about to read 6, iclass 40, count 0 2006.174.01:36:24.59#ibcon#read 6, iclass 40, count 0 2006.174.01:36:24.59#ibcon#end of sib2, iclass 40, count 0 2006.174.01:36:24.59#ibcon#*after write, iclass 40, count 0 2006.174.01:36:24.59#ibcon#*before return 0, iclass 40, count 0 2006.174.01:36:24.59#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.174.01:36:24.59#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.174.01:36:24.59#ibcon#about to clear, iclass 40 cls_cnt 0 2006.174.01:36:24.59#ibcon#cleared, iclass 40 cls_cnt 0 2006.174.01:36:24.59$vck44/va=5,4 2006.174.01:36:24.59#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.174.01:36:24.59#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.174.01:36:24.59#ibcon#ireg 11 cls_cnt 2 2006.174.01:36:24.59#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.174.01:36:24.65#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.174.01:36:24.65#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.174.01:36:24.65#ibcon#enter wrdev, iclass 4, count 2 2006.174.01:36:24.65#ibcon#first serial, iclass 4, count 2 2006.174.01:36:24.65#ibcon#enter sib2, iclass 4, count 2 2006.174.01:36:24.65#ibcon#flushed, iclass 4, count 2 2006.174.01:36:24.65#ibcon#about to write, iclass 4, count 2 2006.174.01:36:24.65#ibcon#wrote, iclass 4, count 2 2006.174.01:36:24.65#ibcon#about to read 3, iclass 4, count 2 2006.174.01:36:24.67#ibcon#read 3, iclass 4, count 2 2006.174.01:36:24.67#ibcon#about to read 4, iclass 4, count 2 2006.174.01:36:24.67#ibcon#read 4, iclass 4, count 2 2006.174.01:36:24.67#ibcon#about to read 5, iclass 4, count 2 2006.174.01:36:24.67#ibcon#read 5, iclass 4, count 2 2006.174.01:36:24.67#ibcon#about to read 6, iclass 4, count 2 2006.174.01:36:24.67#ibcon#read 6, iclass 4, count 2 2006.174.01:36:24.67#ibcon#end of sib2, iclass 4, count 2 2006.174.01:36:24.67#ibcon#*mode == 0, iclass 4, count 2 2006.174.01:36:24.67#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.174.01:36:24.67#ibcon#[25=AT05-04\r\n] 2006.174.01:36:24.67#ibcon#*before write, iclass 4, count 2 2006.174.01:36:24.67#ibcon#enter sib2, iclass 4, count 2 2006.174.01:36:24.67#ibcon#flushed, iclass 4, count 2 2006.174.01:36:24.67#ibcon#about to write, iclass 4, count 2 2006.174.01:36:24.67#ibcon#wrote, iclass 4, count 2 2006.174.01:36:24.67#ibcon#about to read 3, iclass 4, count 2 2006.174.01:36:24.70#ibcon#read 3, iclass 4, count 2 2006.174.01:36:24.70#ibcon#about to read 4, iclass 4, count 2 2006.174.01:36:24.70#ibcon#read 4, iclass 4, count 2 2006.174.01:36:24.70#ibcon#about to read 5, iclass 4, count 2 2006.174.01:36:24.70#ibcon#read 5, iclass 4, count 2 2006.174.01:36:24.70#ibcon#about to read 6, iclass 4, count 2 2006.174.01:36:24.70#ibcon#read 6, iclass 4, count 2 2006.174.01:36:24.70#ibcon#end of sib2, iclass 4, count 2 2006.174.01:36:24.70#ibcon#*after write, iclass 4, count 2 2006.174.01:36:24.70#ibcon#*before return 0, iclass 4, count 2 2006.174.01:36:24.70#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.174.01:36:24.70#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.174.01:36:24.70#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.174.01:36:24.70#ibcon#ireg 7 cls_cnt 0 2006.174.01:36:24.70#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.174.01:36:24.82#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.174.01:36:24.82#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.174.01:36:24.82#ibcon#enter wrdev, iclass 4, count 0 2006.174.01:36:24.82#ibcon#first serial, iclass 4, count 0 2006.174.01:36:24.82#ibcon#enter sib2, iclass 4, count 0 2006.174.01:36:24.82#ibcon#flushed, iclass 4, count 0 2006.174.01:36:24.82#ibcon#about to write, iclass 4, count 0 2006.174.01:36:24.82#ibcon#wrote, iclass 4, count 0 2006.174.01:36:24.82#ibcon#about to read 3, iclass 4, count 0 2006.174.01:36:24.84#ibcon#read 3, iclass 4, count 0 2006.174.01:36:24.84#ibcon#about to read 4, iclass 4, count 0 2006.174.01:36:24.84#ibcon#read 4, iclass 4, count 0 2006.174.01:36:24.84#ibcon#about to read 5, iclass 4, count 0 2006.174.01:36:24.84#ibcon#read 5, iclass 4, count 0 2006.174.01:36:24.84#ibcon#about to read 6, iclass 4, count 0 2006.174.01:36:24.84#ibcon#read 6, iclass 4, count 0 2006.174.01:36:24.84#ibcon#end of sib2, iclass 4, count 0 2006.174.01:36:24.84#ibcon#*mode == 0, iclass 4, count 0 2006.174.01:36:24.84#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.174.01:36:24.84#ibcon#[25=USB\r\n] 2006.174.01:36:24.84#ibcon#*before write, iclass 4, count 0 2006.174.01:36:24.84#ibcon#enter sib2, iclass 4, count 0 2006.174.01:36:24.84#ibcon#flushed, iclass 4, count 0 2006.174.01:36:24.84#ibcon#about to write, iclass 4, count 0 2006.174.01:36:24.84#ibcon#wrote, iclass 4, count 0 2006.174.01:36:24.84#ibcon#about to read 3, iclass 4, count 0 2006.174.01:36:24.87#ibcon#read 3, iclass 4, count 0 2006.174.01:36:24.87#ibcon#about to read 4, iclass 4, count 0 2006.174.01:36:24.87#ibcon#read 4, iclass 4, count 0 2006.174.01:36:24.87#ibcon#about to read 5, iclass 4, count 0 2006.174.01:36:24.87#ibcon#read 5, iclass 4, count 0 2006.174.01:36:24.87#ibcon#about to read 6, iclass 4, count 0 2006.174.01:36:24.87#ibcon#read 6, iclass 4, count 0 2006.174.01:36:24.87#ibcon#end of sib2, iclass 4, count 0 2006.174.01:36:24.87#ibcon#*after write, iclass 4, count 0 2006.174.01:36:24.87#ibcon#*before return 0, iclass 4, count 0 2006.174.01:36:24.87#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.174.01:36:24.87#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.174.01:36:24.87#ibcon#about to clear, iclass 4 cls_cnt 0 2006.174.01:36:24.87#ibcon#cleared, iclass 4 cls_cnt 0 2006.174.01:36:24.87$vck44/valo=6,814.99 2006.174.01:36:24.87#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.174.01:36:24.87#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.174.01:36:24.87#ibcon#ireg 17 cls_cnt 0 2006.174.01:36:24.87#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.174.01:36:24.87#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.174.01:36:24.88#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.174.01:36:24.88#ibcon#enter wrdev, iclass 6, count 0 2006.174.01:36:24.88#ibcon#first serial, iclass 6, count 0 2006.174.01:36:24.88#ibcon#enter sib2, iclass 6, count 0 2006.174.01:36:24.88#ibcon#flushed, iclass 6, count 0 2006.174.01:36:24.88#ibcon#about to write, iclass 6, count 0 2006.174.01:36:24.88#ibcon#wrote, iclass 6, count 0 2006.174.01:36:24.88#ibcon#about to read 3, iclass 6, count 0 2006.174.01:36:24.89#ibcon#read 3, iclass 6, count 0 2006.174.01:36:24.89#ibcon#about to read 4, iclass 6, count 0 2006.174.01:36:24.89#ibcon#read 4, iclass 6, count 0 2006.174.01:36:24.89#ibcon#about to read 5, iclass 6, count 0 2006.174.01:36:24.89#ibcon#read 5, iclass 6, count 0 2006.174.01:36:24.89#ibcon#about to read 6, iclass 6, count 0 2006.174.01:36:24.89#ibcon#read 6, iclass 6, count 0 2006.174.01:36:24.89#ibcon#end of sib2, iclass 6, count 0 2006.174.01:36:24.89#ibcon#*mode == 0, iclass 6, count 0 2006.174.01:36:24.89#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.174.01:36:24.89#ibcon#[26=FRQ=06,814.99\r\n] 2006.174.01:36:24.89#ibcon#*before write, iclass 6, count 0 2006.174.01:36:24.89#ibcon#enter sib2, iclass 6, count 0 2006.174.01:36:24.89#ibcon#flushed, iclass 6, count 0 2006.174.01:36:24.89#ibcon#about to write, iclass 6, count 0 2006.174.01:36:24.89#ibcon#wrote, iclass 6, count 0 2006.174.01:36:24.89#ibcon#about to read 3, iclass 6, count 0 2006.174.01:36:24.93#ibcon#read 3, iclass 6, count 0 2006.174.01:36:24.93#ibcon#about to read 4, iclass 6, count 0 2006.174.01:36:24.93#ibcon#read 4, iclass 6, count 0 2006.174.01:36:24.93#ibcon#about to read 5, iclass 6, count 0 2006.174.01:36:24.93#ibcon#read 5, iclass 6, count 0 2006.174.01:36:24.93#ibcon#about to read 6, iclass 6, count 0 2006.174.01:36:24.93#ibcon#read 6, iclass 6, count 0 2006.174.01:36:24.93#ibcon#end of sib2, iclass 6, count 0 2006.174.01:36:24.93#ibcon#*after write, iclass 6, count 0 2006.174.01:36:24.93#ibcon#*before return 0, iclass 6, count 0 2006.174.01:36:24.93#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.174.01:36:24.93#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.174.01:36:24.93#ibcon#about to clear, iclass 6 cls_cnt 0 2006.174.01:36:24.93#ibcon#cleared, iclass 6 cls_cnt 0 2006.174.01:36:24.93$vck44/va=6,3 2006.174.01:36:24.93#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.174.01:36:24.93#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.174.01:36:24.93#ibcon#ireg 11 cls_cnt 2 2006.174.01:36:24.93#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.174.01:36:24.99#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.174.01:36:24.99#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.174.01:36:24.99#ibcon#enter wrdev, iclass 10, count 2 2006.174.01:36:24.99#ibcon#first serial, iclass 10, count 2 2006.174.01:36:24.99#ibcon#enter sib2, iclass 10, count 2 2006.174.01:36:24.99#ibcon#flushed, iclass 10, count 2 2006.174.01:36:24.99#ibcon#about to write, iclass 10, count 2 2006.174.01:36:24.99#ibcon#wrote, iclass 10, count 2 2006.174.01:36:24.99#ibcon#about to read 3, iclass 10, count 2 2006.174.01:36:25.01#ibcon#read 3, iclass 10, count 2 2006.174.01:36:25.01#ibcon#about to read 4, iclass 10, count 2 2006.174.01:36:25.01#ibcon#read 4, iclass 10, count 2 2006.174.01:36:25.01#ibcon#about to read 5, iclass 10, count 2 2006.174.01:36:25.01#ibcon#read 5, iclass 10, count 2 2006.174.01:36:25.01#ibcon#about to read 6, iclass 10, count 2 2006.174.01:36:25.01#ibcon#read 6, iclass 10, count 2 2006.174.01:36:25.01#ibcon#end of sib2, iclass 10, count 2 2006.174.01:36:25.01#ibcon#*mode == 0, iclass 10, count 2 2006.174.01:36:25.01#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.174.01:36:25.01#ibcon#[25=AT06-03\r\n] 2006.174.01:36:25.01#ibcon#*before write, iclass 10, count 2 2006.174.01:36:25.01#ibcon#enter sib2, iclass 10, count 2 2006.174.01:36:25.01#ibcon#flushed, iclass 10, count 2 2006.174.01:36:25.01#ibcon#about to write, iclass 10, count 2 2006.174.01:36:25.01#ibcon#wrote, iclass 10, count 2 2006.174.01:36:25.01#ibcon#about to read 3, iclass 10, count 2 2006.174.01:36:25.04#ibcon#read 3, iclass 10, count 2 2006.174.01:36:25.04#ibcon#about to read 4, iclass 10, count 2 2006.174.01:36:25.04#ibcon#read 4, iclass 10, count 2 2006.174.01:36:25.04#ibcon#about to read 5, iclass 10, count 2 2006.174.01:36:25.04#ibcon#read 5, iclass 10, count 2 2006.174.01:36:25.04#ibcon#about to read 6, iclass 10, count 2 2006.174.01:36:25.04#ibcon#read 6, iclass 10, count 2 2006.174.01:36:25.04#ibcon#end of sib2, iclass 10, count 2 2006.174.01:36:25.04#ibcon#*after write, iclass 10, count 2 2006.174.01:36:25.04#ibcon#*before return 0, iclass 10, count 2 2006.174.01:36:25.04#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.174.01:36:25.04#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.174.01:36:25.04#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.174.01:36:25.04#ibcon#ireg 7 cls_cnt 0 2006.174.01:36:25.04#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.174.01:36:25.16#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.174.01:36:25.16#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.174.01:36:25.16#ibcon#enter wrdev, iclass 10, count 0 2006.174.01:36:25.16#ibcon#first serial, iclass 10, count 0 2006.174.01:36:25.16#ibcon#enter sib2, iclass 10, count 0 2006.174.01:36:25.16#ibcon#flushed, iclass 10, count 0 2006.174.01:36:25.16#ibcon#about to write, iclass 10, count 0 2006.174.01:36:25.16#ibcon#wrote, iclass 10, count 0 2006.174.01:36:25.16#ibcon#about to read 3, iclass 10, count 0 2006.174.01:36:25.18#ibcon#read 3, iclass 10, count 0 2006.174.01:36:25.18#ibcon#about to read 4, iclass 10, count 0 2006.174.01:36:25.18#ibcon#read 4, iclass 10, count 0 2006.174.01:36:25.18#ibcon#about to read 5, iclass 10, count 0 2006.174.01:36:25.18#ibcon#read 5, iclass 10, count 0 2006.174.01:36:25.18#ibcon#about to read 6, iclass 10, count 0 2006.174.01:36:25.18#ibcon#read 6, iclass 10, count 0 2006.174.01:36:25.18#ibcon#end of sib2, iclass 10, count 0 2006.174.01:36:25.18#ibcon#*mode == 0, iclass 10, count 0 2006.174.01:36:25.18#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.174.01:36:25.18#ibcon#[25=USB\r\n] 2006.174.01:36:25.18#ibcon#*before write, iclass 10, count 0 2006.174.01:36:25.18#ibcon#enter sib2, iclass 10, count 0 2006.174.01:36:25.18#ibcon#flushed, iclass 10, count 0 2006.174.01:36:25.18#ibcon#about to write, iclass 10, count 0 2006.174.01:36:25.18#ibcon#wrote, iclass 10, count 0 2006.174.01:36:25.18#ibcon#about to read 3, iclass 10, count 0 2006.174.01:36:25.21#ibcon#read 3, iclass 10, count 0 2006.174.01:36:25.21#ibcon#about to read 4, iclass 10, count 0 2006.174.01:36:25.21#ibcon#read 4, iclass 10, count 0 2006.174.01:36:25.21#ibcon#about to read 5, iclass 10, count 0 2006.174.01:36:25.21#ibcon#read 5, iclass 10, count 0 2006.174.01:36:25.21#ibcon#about to read 6, iclass 10, count 0 2006.174.01:36:25.21#ibcon#read 6, iclass 10, count 0 2006.174.01:36:25.21#ibcon#end of sib2, iclass 10, count 0 2006.174.01:36:25.21#ibcon#*after write, iclass 10, count 0 2006.174.01:36:25.21#ibcon#*before return 0, iclass 10, count 0 2006.174.01:36:25.21#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.174.01:36:25.21#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.174.01:36:25.21#ibcon#about to clear, iclass 10 cls_cnt 0 2006.174.01:36:25.21#ibcon#cleared, iclass 10 cls_cnt 0 2006.174.01:36:25.21$vck44/valo=7,864.99 2006.174.01:36:25.21#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.174.01:36:25.22#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.174.01:36:25.22#ibcon#ireg 17 cls_cnt 0 2006.174.01:36:25.22#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.174.01:36:25.22#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.174.01:36:25.22#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.174.01:36:25.22#ibcon#enter wrdev, iclass 12, count 0 2006.174.01:36:25.22#ibcon#first serial, iclass 12, count 0 2006.174.01:36:25.22#ibcon#enter sib2, iclass 12, count 0 2006.174.01:36:25.22#ibcon#flushed, iclass 12, count 0 2006.174.01:36:25.22#ibcon#about to write, iclass 12, count 0 2006.174.01:36:25.22#ibcon#wrote, iclass 12, count 0 2006.174.01:36:25.22#ibcon#about to read 3, iclass 12, count 0 2006.174.01:36:25.23#ibcon#read 3, iclass 12, count 0 2006.174.01:36:25.23#ibcon#about to read 4, iclass 12, count 0 2006.174.01:36:25.23#ibcon#read 4, iclass 12, count 0 2006.174.01:36:25.23#ibcon#about to read 5, iclass 12, count 0 2006.174.01:36:25.23#ibcon#read 5, iclass 12, count 0 2006.174.01:36:25.23#ibcon#about to read 6, iclass 12, count 0 2006.174.01:36:25.23#ibcon#read 6, iclass 12, count 0 2006.174.01:36:25.23#ibcon#end of sib2, iclass 12, count 0 2006.174.01:36:25.23#ibcon#*mode == 0, iclass 12, count 0 2006.174.01:36:25.23#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.174.01:36:25.23#ibcon#[26=FRQ=07,864.99\r\n] 2006.174.01:36:25.23#ibcon#*before write, iclass 12, count 0 2006.174.01:36:25.23#ibcon#enter sib2, iclass 12, count 0 2006.174.01:36:25.23#ibcon#flushed, iclass 12, count 0 2006.174.01:36:25.23#ibcon#about to write, iclass 12, count 0 2006.174.01:36:25.23#ibcon#wrote, iclass 12, count 0 2006.174.01:36:25.23#ibcon#about to read 3, iclass 12, count 0 2006.174.01:36:25.27#ibcon#read 3, iclass 12, count 0 2006.174.01:36:25.27#ibcon#about to read 4, iclass 12, count 0 2006.174.01:36:25.27#ibcon#read 4, iclass 12, count 0 2006.174.01:36:25.27#ibcon#about to read 5, iclass 12, count 0 2006.174.01:36:25.27#ibcon#read 5, iclass 12, count 0 2006.174.01:36:25.27#ibcon#about to read 6, iclass 12, count 0 2006.174.01:36:25.27#ibcon#read 6, iclass 12, count 0 2006.174.01:36:25.27#ibcon#end of sib2, iclass 12, count 0 2006.174.01:36:25.27#ibcon#*after write, iclass 12, count 0 2006.174.01:36:25.27#ibcon#*before return 0, iclass 12, count 0 2006.174.01:36:25.27#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.174.01:36:25.27#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.174.01:36:25.27#ibcon#about to clear, iclass 12 cls_cnt 0 2006.174.01:36:25.27#ibcon#cleared, iclass 12 cls_cnt 0 2006.174.01:36:25.27$vck44/va=7,4 2006.174.01:36:25.27#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.174.01:36:25.27#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.174.01:36:25.27#ibcon#ireg 11 cls_cnt 2 2006.174.01:36:25.27#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.174.01:36:25.33#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.174.01:36:25.33#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.174.01:36:25.33#ibcon#enter wrdev, iclass 14, count 2 2006.174.01:36:25.33#ibcon#first serial, iclass 14, count 2 2006.174.01:36:25.33#ibcon#enter sib2, iclass 14, count 2 2006.174.01:36:25.33#ibcon#flushed, iclass 14, count 2 2006.174.01:36:25.33#ibcon#about to write, iclass 14, count 2 2006.174.01:36:25.33#ibcon#wrote, iclass 14, count 2 2006.174.01:36:25.33#ibcon#about to read 3, iclass 14, count 2 2006.174.01:36:25.35#ibcon#read 3, iclass 14, count 2 2006.174.01:36:25.35#ibcon#about to read 4, iclass 14, count 2 2006.174.01:36:25.35#ibcon#read 4, iclass 14, count 2 2006.174.01:36:25.35#ibcon#about to read 5, iclass 14, count 2 2006.174.01:36:25.35#ibcon#read 5, iclass 14, count 2 2006.174.01:36:25.35#ibcon#about to read 6, iclass 14, count 2 2006.174.01:36:25.35#ibcon#read 6, iclass 14, count 2 2006.174.01:36:25.35#ibcon#end of sib2, iclass 14, count 2 2006.174.01:36:25.35#ibcon#*mode == 0, iclass 14, count 2 2006.174.01:36:25.35#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.174.01:36:25.35#ibcon#[25=AT07-04\r\n] 2006.174.01:36:25.35#ibcon#*before write, iclass 14, count 2 2006.174.01:36:25.35#ibcon#enter sib2, iclass 14, count 2 2006.174.01:36:25.35#ibcon#flushed, iclass 14, count 2 2006.174.01:36:25.35#ibcon#about to write, iclass 14, count 2 2006.174.01:36:25.35#ibcon#wrote, iclass 14, count 2 2006.174.01:36:25.35#ibcon#about to read 3, iclass 14, count 2 2006.174.01:36:25.38#ibcon#read 3, iclass 14, count 2 2006.174.01:36:25.38#ibcon#about to read 4, iclass 14, count 2 2006.174.01:36:25.38#ibcon#read 4, iclass 14, count 2 2006.174.01:36:25.38#ibcon#about to read 5, iclass 14, count 2 2006.174.01:36:25.38#ibcon#read 5, iclass 14, count 2 2006.174.01:36:25.38#ibcon#about to read 6, iclass 14, count 2 2006.174.01:36:25.38#ibcon#read 6, iclass 14, count 2 2006.174.01:36:25.38#ibcon#end of sib2, iclass 14, count 2 2006.174.01:36:25.38#ibcon#*after write, iclass 14, count 2 2006.174.01:36:25.38#ibcon#*before return 0, iclass 14, count 2 2006.174.01:36:25.38#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.174.01:36:25.38#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.174.01:36:25.38#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.174.01:36:25.38#ibcon#ireg 7 cls_cnt 0 2006.174.01:36:25.38#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.174.01:36:25.50#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.174.01:36:25.50#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.174.01:36:25.50#ibcon#enter wrdev, iclass 14, count 0 2006.174.01:36:25.50#ibcon#first serial, iclass 14, count 0 2006.174.01:36:25.50#ibcon#enter sib2, iclass 14, count 0 2006.174.01:36:25.50#ibcon#flushed, iclass 14, count 0 2006.174.01:36:25.50#ibcon#about to write, iclass 14, count 0 2006.174.01:36:25.50#ibcon#wrote, iclass 14, count 0 2006.174.01:36:25.50#ibcon#about to read 3, iclass 14, count 0 2006.174.01:36:25.52#ibcon#read 3, iclass 14, count 0 2006.174.01:36:25.52#ibcon#about to read 4, iclass 14, count 0 2006.174.01:36:25.52#ibcon#read 4, iclass 14, count 0 2006.174.01:36:25.52#ibcon#about to read 5, iclass 14, count 0 2006.174.01:36:25.52#ibcon#read 5, iclass 14, count 0 2006.174.01:36:25.52#ibcon#about to read 6, iclass 14, count 0 2006.174.01:36:25.52#ibcon#read 6, iclass 14, count 0 2006.174.01:36:25.52#ibcon#end of sib2, iclass 14, count 0 2006.174.01:36:25.52#ibcon#*mode == 0, iclass 14, count 0 2006.174.01:36:25.52#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.174.01:36:25.52#ibcon#[25=USB\r\n] 2006.174.01:36:25.52#ibcon#*before write, iclass 14, count 0 2006.174.01:36:25.52#ibcon#enter sib2, iclass 14, count 0 2006.174.01:36:25.52#ibcon#flushed, iclass 14, count 0 2006.174.01:36:25.52#ibcon#about to write, iclass 14, count 0 2006.174.01:36:25.52#ibcon#wrote, iclass 14, count 0 2006.174.01:36:25.52#ibcon#about to read 3, iclass 14, count 0 2006.174.01:36:25.55#ibcon#read 3, iclass 14, count 0 2006.174.01:36:25.55#ibcon#about to read 4, iclass 14, count 0 2006.174.01:36:25.55#ibcon#read 4, iclass 14, count 0 2006.174.01:36:25.55#ibcon#about to read 5, iclass 14, count 0 2006.174.01:36:25.55#ibcon#read 5, iclass 14, count 0 2006.174.01:36:25.55#ibcon#about to read 6, iclass 14, count 0 2006.174.01:36:25.55#ibcon#read 6, iclass 14, count 0 2006.174.01:36:25.55#ibcon#end of sib2, iclass 14, count 0 2006.174.01:36:25.55#ibcon#*after write, iclass 14, count 0 2006.174.01:36:25.55#ibcon#*before return 0, iclass 14, count 0 2006.174.01:36:25.55#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.174.01:36:25.55#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.174.01:36:25.55#ibcon#about to clear, iclass 14 cls_cnt 0 2006.174.01:36:25.55#ibcon#cleared, iclass 14 cls_cnt 0 2006.174.01:36:25.55$vck44/valo=8,884.99 2006.174.01:36:25.55#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.174.01:36:25.55#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.174.01:36:25.55#ibcon#ireg 17 cls_cnt 0 2006.174.01:36:25.55#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.174.01:36:25.55#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.174.01:36:25.55#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.174.01:36:25.56#ibcon#enter wrdev, iclass 16, count 0 2006.174.01:36:25.56#ibcon#first serial, iclass 16, count 0 2006.174.01:36:25.56#ibcon#enter sib2, iclass 16, count 0 2006.174.01:36:25.56#ibcon#flushed, iclass 16, count 0 2006.174.01:36:25.56#ibcon#about to write, iclass 16, count 0 2006.174.01:36:25.56#ibcon#wrote, iclass 16, count 0 2006.174.01:36:25.56#ibcon#about to read 3, iclass 16, count 0 2006.174.01:36:25.57#ibcon#read 3, iclass 16, count 0 2006.174.01:36:25.57#ibcon#about to read 4, iclass 16, count 0 2006.174.01:36:25.57#ibcon#read 4, iclass 16, count 0 2006.174.01:36:25.57#ibcon#about to read 5, iclass 16, count 0 2006.174.01:36:25.57#ibcon#read 5, iclass 16, count 0 2006.174.01:36:25.57#ibcon#about to read 6, iclass 16, count 0 2006.174.01:36:25.57#ibcon#read 6, iclass 16, count 0 2006.174.01:36:25.57#ibcon#end of sib2, iclass 16, count 0 2006.174.01:36:25.57#ibcon#*mode == 0, iclass 16, count 0 2006.174.01:36:25.57#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.174.01:36:25.57#ibcon#[26=FRQ=08,884.99\r\n] 2006.174.01:36:25.57#ibcon#*before write, iclass 16, count 0 2006.174.01:36:25.57#ibcon#enter sib2, iclass 16, count 0 2006.174.01:36:25.57#ibcon#flushed, iclass 16, count 0 2006.174.01:36:25.57#ibcon#about to write, iclass 16, count 0 2006.174.01:36:25.57#ibcon#wrote, iclass 16, count 0 2006.174.01:36:25.57#ibcon#about to read 3, iclass 16, count 0 2006.174.01:36:25.61#ibcon#read 3, iclass 16, count 0 2006.174.01:36:25.61#ibcon#about to read 4, iclass 16, count 0 2006.174.01:36:25.61#ibcon#read 4, iclass 16, count 0 2006.174.01:36:25.61#ibcon#about to read 5, iclass 16, count 0 2006.174.01:36:25.61#ibcon#read 5, iclass 16, count 0 2006.174.01:36:25.61#ibcon#about to read 6, iclass 16, count 0 2006.174.01:36:25.61#ibcon#read 6, iclass 16, count 0 2006.174.01:36:25.61#ibcon#end of sib2, iclass 16, count 0 2006.174.01:36:25.61#ibcon#*after write, iclass 16, count 0 2006.174.01:36:25.61#ibcon#*before return 0, iclass 16, count 0 2006.174.01:36:25.61#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.174.01:36:25.61#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.174.01:36:25.61#ibcon#about to clear, iclass 16 cls_cnt 0 2006.174.01:36:25.61#ibcon#cleared, iclass 16 cls_cnt 0 2006.174.01:36:25.61$vck44/va=8,4 2006.174.01:36:25.61#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.174.01:36:25.61#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.174.01:36:25.61#ibcon#ireg 11 cls_cnt 2 2006.174.01:36:25.61#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.174.01:36:25.67#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.174.01:36:25.67#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.174.01:36:25.67#ibcon#enter wrdev, iclass 18, count 2 2006.174.01:36:25.67#ibcon#first serial, iclass 18, count 2 2006.174.01:36:25.67#ibcon#enter sib2, iclass 18, count 2 2006.174.01:36:25.67#ibcon#flushed, iclass 18, count 2 2006.174.01:36:25.67#ibcon#about to write, iclass 18, count 2 2006.174.01:36:25.67#ibcon#wrote, iclass 18, count 2 2006.174.01:36:25.67#ibcon#about to read 3, iclass 18, count 2 2006.174.01:36:25.69#ibcon#read 3, iclass 18, count 2 2006.174.01:36:25.69#ibcon#about to read 4, iclass 18, count 2 2006.174.01:36:25.69#ibcon#read 4, iclass 18, count 2 2006.174.01:36:25.69#ibcon#about to read 5, iclass 18, count 2 2006.174.01:36:25.69#ibcon#read 5, iclass 18, count 2 2006.174.01:36:25.69#ibcon#about to read 6, iclass 18, count 2 2006.174.01:36:25.69#ibcon#read 6, iclass 18, count 2 2006.174.01:36:25.69#ibcon#end of sib2, iclass 18, count 2 2006.174.01:36:25.69#ibcon#*mode == 0, iclass 18, count 2 2006.174.01:36:25.69#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.174.01:36:25.69#ibcon#[25=AT08-04\r\n] 2006.174.01:36:25.69#ibcon#*before write, iclass 18, count 2 2006.174.01:36:25.69#ibcon#enter sib2, iclass 18, count 2 2006.174.01:36:25.69#ibcon#flushed, iclass 18, count 2 2006.174.01:36:25.69#ibcon#about to write, iclass 18, count 2 2006.174.01:36:25.69#ibcon#wrote, iclass 18, count 2 2006.174.01:36:25.69#ibcon#about to read 3, iclass 18, count 2 2006.174.01:36:25.72#ibcon#read 3, iclass 18, count 2 2006.174.01:36:25.72#ibcon#about to read 4, iclass 18, count 2 2006.174.01:36:25.72#ibcon#read 4, iclass 18, count 2 2006.174.01:36:25.72#ibcon#about to read 5, iclass 18, count 2 2006.174.01:36:25.72#ibcon#read 5, iclass 18, count 2 2006.174.01:36:25.72#ibcon#about to read 6, iclass 18, count 2 2006.174.01:36:25.72#ibcon#read 6, iclass 18, count 2 2006.174.01:36:25.72#ibcon#end of sib2, iclass 18, count 2 2006.174.01:36:25.72#ibcon#*after write, iclass 18, count 2 2006.174.01:36:25.72#ibcon#*before return 0, iclass 18, count 2 2006.174.01:36:25.72#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.174.01:36:25.72#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.174.01:36:25.72#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.174.01:36:25.72#ibcon#ireg 7 cls_cnt 0 2006.174.01:36:25.72#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.174.01:36:25.75#abcon#<5=/09 0.8 2.7 26.03 771003.3\r\n> 2006.174.01:36:25.77#abcon#{5=INTERFACE CLEAR} 2006.174.01:36:25.83#abcon#[5=S1D000X0/0*\r\n] 2006.174.01:36:25.84#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.174.01:36:25.84#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.174.01:36:25.84#ibcon#enter wrdev, iclass 18, count 0 2006.174.01:36:25.84#ibcon#first serial, iclass 18, count 0 2006.174.01:36:25.84#ibcon#enter sib2, iclass 18, count 0 2006.174.01:36:25.84#ibcon#flushed, iclass 18, count 0 2006.174.01:36:25.84#ibcon#about to write, iclass 18, count 0 2006.174.01:36:25.84#ibcon#wrote, iclass 18, count 0 2006.174.01:36:25.84#ibcon#about to read 3, iclass 18, count 0 2006.174.01:36:25.86#ibcon#read 3, iclass 18, count 0 2006.174.01:36:25.86#ibcon#about to read 4, iclass 18, count 0 2006.174.01:36:25.86#ibcon#read 4, iclass 18, count 0 2006.174.01:36:25.86#ibcon#about to read 5, iclass 18, count 0 2006.174.01:36:25.86#ibcon#read 5, iclass 18, count 0 2006.174.01:36:25.86#ibcon#about to read 6, iclass 18, count 0 2006.174.01:36:25.86#ibcon#read 6, iclass 18, count 0 2006.174.01:36:25.86#ibcon#end of sib2, iclass 18, count 0 2006.174.01:36:25.86#ibcon#*mode == 0, iclass 18, count 0 2006.174.01:36:25.86#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.174.01:36:25.86#ibcon#[25=USB\r\n] 2006.174.01:36:25.86#ibcon#*before write, iclass 18, count 0 2006.174.01:36:25.86#ibcon#enter sib2, iclass 18, count 0 2006.174.01:36:25.86#ibcon#flushed, iclass 18, count 0 2006.174.01:36:25.86#ibcon#about to write, iclass 18, count 0 2006.174.01:36:25.86#ibcon#wrote, iclass 18, count 0 2006.174.01:36:25.86#ibcon#about to read 3, iclass 18, count 0 2006.174.01:36:25.89#ibcon#read 3, iclass 18, count 0 2006.174.01:36:25.89#ibcon#about to read 4, iclass 18, count 0 2006.174.01:36:25.89#ibcon#read 4, iclass 18, count 0 2006.174.01:36:25.89#ibcon#about to read 5, iclass 18, count 0 2006.174.01:36:25.89#ibcon#read 5, iclass 18, count 0 2006.174.01:36:25.89#ibcon#about to read 6, iclass 18, count 0 2006.174.01:36:25.89#ibcon#read 6, iclass 18, count 0 2006.174.01:36:25.89#ibcon#end of sib2, iclass 18, count 0 2006.174.01:36:25.89#ibcon#*after write, iclass 18, count 0 2006.174.01:36:25.89#ibcon#*before return 0, iclass 18, count 0 2006.174.01:36:25.89#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.174.01:36:25.89#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.174.01:36:25.89#ibcon#about to clear, iclass 18 cls_cnt 0 2006.174.01:36:25.89#ibcon#cleared, iclass 18 cls_cnt 0 2006.174.01:36:25.89$vck44/vblo=1,629.99 2006.174.01:36:25.89#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.174.01:36:25.89#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.174.01:36:25.89#ibcon#ireg 17 cls_cnt 0 2006.174.01:36:25.89#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.174.01:36:25.90#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.174.01:36:25.90#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.174.01:36:25.90#ibcon#enter wrdev, iclass 24, count 0 2006.174.01:36:25.90#ibcon#first serial, iclass 24, count 0 2006.174.01:36:25.90#ibcon#enter sib2, iclass 24, count 0 2006.174.01:36:25.90#ibcon#flushed, iclass 24, count 0 2006.174.01:36:25.90#ibcon#about to write, iclass 24, count 0 2006.174.01:36:25.90#ibcon#wrote, iclass 24, count 0 2006.174.01:36:25.90#ibcon#about to read 3, iclass 24, count 0 2006.174.01:36:25.91#ibcon#read 3, iclass 24, count 0 2006.174.01:36:25.91#ibcon#about to read 4, iclass 24, count 0 2006.174.01:36:25.91#ibcon#read 4, iclass 24, count 0 2006.174.01:36:25.91#ibcon#about to read 5, iclass 24, count 0 2006.174.01:36:25.91#ibcon#read 5, iclass 24, count 0 2006.174.01:36:25.91#ibcon#about to read 6, iclass 24, count 0 2006.174.01:36:25.91#ibcon#read 6, iclass 24, count 0 2006.174.01:36:25.91#ibcon#end of sib2, iclass 24, count 0 2006.174.01:36:25.91#ibcon#*mode == 0, iclass 24, count 0 2006.174.01:36:25.91#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.174.01:36:25.91#ibcon#[28=FRQ=01,629.99\r\n] 2006.174.01:36:25.91#ibcon#*before write, iclass 24, count 0 2006.174.01:36:25.91#ibcon#enter sib2, iclass 24, count 0 2006.174.01:36:25.91#ibcon#flushed, iclass 24, count 0 2006.174.01:36:25.91#ibcon#about to write, iclass 24, count 0 2006.174.01:36:25.91#ibcon#wrote, iclass 24, count 0 2006.174.01:36:25.91#ibcon#about to read 3, iclass 24, count 0 2006.174.01:36:25.95#ibcon#read 3, iclass 24, count 0 2006.174.01:36:25.95#ibcon#about to read 4, iclass 24, count 0 2006.174.01:36:25.95#ibcon#read 4, iclass 24, count 0 2006.174.01:36:25.95#ibcon#about to read 5, iclass 24, count 0 2006.174.01:36:25.95#ibcon#read 5, iclass 24, count 0 2006.174.01:36:25.95#ibcon#about to read 6, iclass 24, count 0 2006.174.01:36:25.95#ibcon#read 6, iclass 24, count 0 2006.174.01:36:25.95#ibcon#end of sib2, iclass 24, count 0 2006.174.01:36:25.95#ibcon#*after write, iclass 24, count 0 2006.174.01:36:25.95#ibcon#*before return 0, iclass 24, count 0 2006.174.01:36:25.95#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.174.01:36:25.95#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.174.01:36:25.95#ibcon#about to clear, iclass 24 cls_cnt 0 2006.174.01:36:25.95#ibcon#cleared, iclass 24 cls_cnt 0 2006.174.01:36:25.95$vck44/vb=1,4 2006.174.01:36:25.95#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.174.01:36:25.95#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.174.01:36:25.95#ibcon#ireg 11 cls_cnt 2 2006.174.01:36:25.95#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.174.01:36:25.95#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.174.01:36:25.95#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.174.01:36:25.95#ibcon#enter wrdev, iclass 26, count 2 2006.174.01:36:25.95#ibcon#first serial, iclass 26, count 2 2006.174.01:36:25.95#ibcon#enter sib2, iclass 26, count 2 2006.174.01:36:25.96#ibcon#flushed, iclass 26, count 2 2006.174.01:36:25.96#ibcon#about to write, iclass 26, count 2 2006.174.01:36:25.96#ibcon#wrote, iclass 26, count 2 2006.174.01:36:25.96#ibcon#about to read 3, iclass 26, count 2 2006.174.01:36:25.97#ibcon#read 3, iclass 26, count 2 2006.174.01:36:25.97#ibcon#about to read 4, iclass 26, count 2 2006.174.01:36:25.97#ibcon#read 4, iclass 26, count 2 2006.174.01:36:25.97#ibcon#about to read 5, iclass 26, count 2 2006.174.01:36:25.97#ibcon#read 5, iclass 26, count 2 2006.174.01:36:25.97#ibcon#about to read 6, iclass 26, count 2 2006.174.01:36:25.97#ibcon#read 6, iclass 26, count 2 2006.174.01:36:25.97#ibcon#end of sib2, iclass 26, count 2 2006.174.01:36:25.97#ibcon#*mode == 0, iclass 26, count 2 2006.174.01:36:25.97#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.174.01:36:25.97#ibcon#[27=AT01-04\r\n] 2006.174.01:36:25.97#ibcon#*before write, iclass 26, count 2 2006.174.01:36:25.97#ibcon#enter sib2, iclass 26, count 2 2006.174.01:36:25.97#ibcon#flushed, iclass 26, count 2 2006.174.01:36:25.97#ibcon#about to write, iclass 26, count 2 2006.174.01:36:25.97#ibcon#wrote, iclass 26, count 2 2006.174.01:36:25.97#ibcon#about to read 3, iclass 26, count 2 2006.174.01:36:26.00#ibcon#read 3, iclass 26, count 2 2006.174.01:36:26.00#ibcon#about to read 4, iclass 26, count 2 2006.174.01:36:26.00#ibcon#read 4, iclass 26, count 2 2006.174.01:36:26.00#ibcon#about to read 5, iclass 26, count 2 2006.174.01:36:26.00#ibcon#read 5, iclass 26, count 2 2006.174.01:36:26.00#ibcon#about to read 6, iclass 26, count 2 2006.174.01:36:26.00#ibcon#read 6, iclass 26, count 2 2006.174.01:36:26.00#ibcon#end of sib2, iclass 26, count 2 2006.174.01:36:26.00#ibcon#*after write, iclass 26, count 2 2006.174.01:36:26.00#ibcon#*before return 0, iclass 26, count 2 2006.174.01:36:26.00#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.174.01:36:26.00#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.174.01:36:26.00#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.174.01:36:26.00#ibcon#ireg 7 cls_cnt 0 2006.174.01:36:26.00#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.174.01:36:26.12#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.174.01:36:26.12#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.174.01:36:26.12#ibcon#enter wrdev, iclass 26, count 0 2006.174.01:36:26.12#ibcon#first serial, iclass 26, count 0 2006.174.01:36:26.12#ibcon#enter sib2, iclass 26, count 0 2006.174.01:36:26.12#ibcon#flushed, iclass 26, count 0 2006.174.01:36:26.12#ibcon#about to write, iclass 26, count 0 2006.174.01:36:26.12#ibcon#wrote, iclass 26, count 0 2006.174.01:36:26.12#ibcon#about to read 3, iclass 26, count 0 2006.174.01:36:26.14#ibcon#read 3, iclass 26, count 0 2006.174.01:36:26.14#ibcon#about to read 4, iclass 26, count 0 2006.174.01:36:26.14#ibcon#read 4, iclass 26, count 0 2006.174.01:36:26.14#ibcon#about to read 5, iclass 26, count 0 2006.174.01:36:26.14#ibcon#read 5, iclass 26, count 0 2006.174.01:36:26.14#ibcon#about to read 6, iclass 26, count 0 2006.174.01:36:26.14#ibcon#read 6, iclass 26, count 0 2006.174.01:36:26.14#ibcon#end of sib2, iclass 26, count 0 2006.174.01:36:26.14#ibcon#*mode == 0, iclass 26, count 0 2006.174.01:36:26.14#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.174.01:36:26.14#ibcon#[27=USB\r\n] 2006.174.01:36:26.14#ibcon#*before write, iclass 26, count 0 2006.174.01:36:26.14#ibcon#enter sib2, iclass 26, count 0 2006.174.01:36:26.14#ibcon#flushed, iclass 26, count 0 2006.174.01:36:26.14#ibcon#about to write, iclass 26, count 0 2006.174.01:36:26.14#ibcon#wrote, iclass 26, count 0 2006.174.01:36:26.14#ibcon#about to read 3, iclass 26, count 0 2006.174.01:36:26.17#ibcon#read 3, iclass 26, count 0 2006.174.01:36:26.17#ibcon#about to read 4, iclass 26, count 0 2006.174.01:36:26.17#ibcon#read 4, iclass 26, count 0 2006.174.01:36:26.17#ibcon#about to read 5, iclass 26, count 0 2006.174.01:36:26.17#ibcon#read 5, iclass 26, count 0 2006.174.01:36:26.17#ibcon#about to read 6, iclass 26, count 0 2006.174.01:36:26.17#ibcon#read 6, iclass 26, count 0 2006.174.01:36:26.17#ibcon#end of sib2, iclass 26, count 0 2006.174.01:36:26.17#ibcon#*after write, iclass 26, count 0 2006.174.01:36:26.17#ibcon#*before return 0, iclass 26, count 0 2006.174.01:36:26.17#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.174.01:36:26.17#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.174.01:36:26.17#ibcon#about to clear, iclass 26 cls_cnt 0 2006.174.01:36:26.17#ibcon#cleared, iclass 26 cls_cnt 0 2006.174.01:36:26.17$vck44/vblo=2,634.99 2006.174.01:36:26.17#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.174.01:36:26.17#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.174.01:36:26.17#ibcon#ireg 17 cls_cnt 0 2006.174.01:36:26.17#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.174.01:36:26.17#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.174.01:36:26.17#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.174.01:36:26.18#ibcon#enter wrdev, iclass 28, count 0 2006.174.01:36:26.18#ibcon#first serial, iclass 28, count 0 2006.174.01:36:26.18#ibcon#enter sib2, iclass 28, count 0 2006.174.01:36:26.18#ibcon#flushed, iclass 28, count 0 2006.174.01:36:26.18#ibcon#about to write, iclass 28, count 0 2006.174.01:36:26.18#ibcon#wrote, iclass 28, count 0 2006.174.01:36:26.18#ibcon#about to read 3, iclass 28, count 0 2006.174.01:36:26.19#ibcon#read 3, iclass 28, count 0 2006.174.01:36:26.19#ibcon#about to read 4, iclass 28, count 0 2006.174.01:36:26.19#ibcon#read 4, iclass 28, count 0 2006.174.01:36:26.19#ibcon#about to read 5, iclass 28, count 0 2006.174.01:36:26.19#ibcon#read 5, iclass 28, count 0 2006.174.01:36:26.19#ibcon#about to read 6, iclass 28, count 0 2006.174.01:36:26.19#ibcon#read 6, iclass 28, count 0 2006.174.01:36:26.19#ibcon#end of sib2, iclass 28, count 0 2006.174.01:36:26.19#ibcon#*mode == 0, iclass 28, count 0 2006.174.01:36:26.19#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.174.01:36:26.19#ibcon#[28=FRQ=02,634.99\r\n] 2006.174.01:36:26.19#ibcon#*before write, iclass 28, count 0 2006.174.01:36:26.19#ibcon#enter sib2, iclass 28, count 0 2006.174.01:36:26.19#ibcon#flushed, iclass 28, count 0 2006.174.01:36:26.19#ibcon#about to write, iclass 28, count 0 2006.174.01:36:26.19#ibcon#wrote, iclass 28, count 0 2006.174.01:36:26.19#ibcon#about to read 3, iclass 28, count 0 2006.174.01:36:26.23#ibcon#read 3, iclass 28, count 0 2006.174.01:36:26.23#ibcon#about to read 4, iclass 28, count 0 2006.174.01:36:26.23#ibcon#read 4, iclass 28, count 0 2006.174.01:36:26.23#ibcon#about to read 5, iclass 28, count 0 2006.174.01:36:26.23#ibcon#read 5, iclass 28, count 0 2006.174.01:36:26.23#ibcon#about to read 6, iclass 28, count 0 2006.174.01:36:26.23#ibcon#read 6, iclass 28, count 0 2006.174.01:36:26.23#ibcon#end of sib2, iclass 28, count 0 2006.174.01:36:26.23#ibcon#*after write, iclass 28, count 0 2006.174.01:36:26.23#ibcon#*before return 0, iclass 28, count 0 2006.174.01:36:26.23#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.174.01:36:26.23#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.174.01:36:26.23#ibcon#about to clear, iclass 28 cls_cnt 0 2006.174.01:36:26.23#ibcon#cleared, iclass 28 cls_cnt 0 2006.174.01:36:26.23$vck44/vb=2,4 2006.174.01:36:26.23#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.174.01:36:26.23#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.174.01:36:26.23#ibcon#ireg 11 cls_cnt 2 2006.174.01:36:26.23#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.174.01:36:26.29#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.174.01:36:26.29#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.174.01:36:26.29#ibcon#enter wrdev, iclass 30, count 2 2006.174.01:36:26.29#ibcon#first serial, iclass 30, count 2 2006.174.01:36:26.29#ibcon#enter sib2, iclass 30, count 2 2006.174.01:36:26.29#ibcon#flushed, iclass 30, count 2 2006.174.01:36:26.29#ibcon#about to write, iclass 30, count 2 2006.174.01:36:26.29#ibcon#wrote, iclass 30, count 2 2006.174.01:36:26.29#ibcon#about to read 3, iclass 30, count 2 2006.174.01:36:26.31#ibcon#read 3, iclass 30, count 2 2006.174.01:36:26.31#ibcon#about to read 4, iclass 30, count 2 2006.174.01:36:26.31#ibcon#read 4, iclass 30, count 2 2006.174.01:36:26.31#ibcon#about to read 5, iclass 30, count 2 2006.174.01:36:26.31#ibcon#read 5, iclass 30, count 2 2006.174.01:36:26.31#ibcon#about to read 6, iclass 30, count 2 2006.174.01:36:26.31#ibcon#read 6, iclass 30, count 2 2006.174.01:36:26.31#ibcon#end of sib2, iclass 30, count 2 2006.174.01:36:26.31#ibcon#*mode == 0, iclass 30, count 2 2006.174.01:36:26.31#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.174.01:36:26.31#ibcon#[27=AT02-04\r\n] 2006.174.01:36:26.31#ibcon#*before write, iclass 30, count 2 2006.174.01:36:26.31#ibcon#enter sib2, iclass 30, count 2 2006.174.01:36:26.31#ibcon#flushed, iclass 30, count 2 2006.174.01:36:26.31#ibcon#about to write, iclass 30, count 2 2006.174.01:36:26.31#ibcon#wrote, iclass 30, count 2 2006.174.01:36:26.31#ibcon#about to read 3, iclass 30, count 2 2006.174.01:36:26.34#ibcon#read 3, iclass 30, count 2 2006.174.01:36:26.34#ibcon#about to read 4, iclass 30, count 2 2006.174.01:36:26.34#ibcon#read 4, iclass 30, count 2 2006.174.01:36:26.34#ibcon#about to read 5, iclass 30, count 2 2006.174.01:36:26.34#ibcon#read 5, iclass 30, count 2 2006.174.01:36:26.34#ibcon#about to read 6, iclass 30, count 2 2006.174.01:36:26.34#ibcon#read 6, iclass 30, count 2 2006.174.01:36:26.34#ibcon#end of sib2, iclass 30, count 2 2006.174.01:36:26.34#ibcon#*after write, iclass 30, count 2 2006.174.01:36:26.34#ibcon#*before return 0, iclass 30, count 2 2006.174.01:36:26.34#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.174.01:36:26.34#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.174.01:36:26.34#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.174.01:36:26.34#ibcon#ireg 7 cls_cnt 0 2006.174.01:36:26.34#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.174.01:36:26.46#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.174.01:36:26.46#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.174.01:36:26.46#ibcon#enter wrdev, iclass 30, count 0 2006.174.01:36:26.46#ibcon#first serial, iclass 30, count 0 2006.174.01:36:26.46#ibcon#enter sib2, iclass 30, count 0 2006.174.01:36:26.46#ibcon#flushed, iclass 30, count 0 2006.174.01:36:26.46#ibcon#about to write, iclass 30, count 0 2006.174.01:36:26.46#ibcon#wrote, iclass 30, count 0 2006.174.01:36:26.46#ibcon#about to read 3, iclass 30, count 0 2006.174.01:36:26.48#ibcon#read 3, iclass 30, count 0 2006.174.01:36:26.48#ibcon#about to read 4, iclass 30, count 0 2006.174.01:36:26.48#ibcon#read 4, iclass 30, count 0 2006.174.01:36:26.48#ibcon#about to read 5, iclass 30, count 0 2006.174.01:36:26.48#ibcon#read 5, iclass 30, count 0 2006.174.01:36:26.48#ibcon#about to read 6, iclass 30, count 0 2006.174.01:36:26.48#ibcon#read 6, iclass 30, count 0 2006.174.01:36:26.48#ibcon#end of sib2, iclass 30, count 0 2006.174.01:36:26.48#ibcon#*mode == 0, iclass 30, count 0 2006.174.01:36:26.48#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.174.01:36:26.48#ibcon#[27=USB\r\n] 2006.174.01:36:26.48#ibcon#*before write, iclass 30, count 0 2006.174.01:36:26.48#ibcon#enter sib2, iclass 30, count 0 2006.174.01:36:26.48#ibcon#flushed, iclass 30, count 0 2006.174.01:36:26.48#ibcon#about to write, iclass 30, count 0 2006.174.01:36:26.48#ibcon#wrote, iclass 30, count 0 2006.174.01:36:26.48#ibcon#about to read 3, iclass 30, count 0 2006.174.01:36:26.51#ibcon#read 3, iclass 30, count 0 2006.174.01:36:26.51#ibcon#about to read 4, iclass 30, count 0 2006.174.01:36:26.51#ibcon#read 4, iclass 30, count 0 2006.174.01:36:26.51#ibcon#about to read 5, iclass 30, count 0 2006.174.01:36:26.51#ibcon#read 5, iclass 30, count 0 2006.174.01:36:26.51#ibcon#about to read 6, iclass 30, count 0 2006.174.01:36:26.51#ibcon#read 6, iclass 30, count 0 2006.174.01:36:26.51#ibcon#end of sib2, iclass 30, count 0 2006.174.01:36:26.51#ibcon#*after write, iclass 30, count 0 2006.174.01:36:26.51#ibcon#*before return 0, iclass 30, count 0 2006.174.01:36:26.51#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.174.01:36:26.51#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.174.01:36:26.51#ibcon#about to clear, iclass 30 cls_cnt 0 2006.174.01:36:26.51#ibcon#cleared, iclass 30 cls_cnt 0 2006.174.01:36:26.51$vck44/vblo=3,649.99 2006.174.01:36:26.51#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.174.01:36:26.51#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.174.01:36:26.52#ibcon#ireg 17 cls_cnt 0 2006.174.01:36:26.52#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.174.01:36:26.52#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.174.01:36:26.52#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.174.01:36:26.52#ibcon#enter wrdev, iclass 32, count 0 2006.174.01:36:26.52#ibcon#first serial, iclass 32, count 0 2006.174.01:36:26.52#ibcon#enter sib2, iclass 32, count 0 2006.174.01:36:26.52#ibcon#flushed, iclass 32, count 0 2006.174.01:36:26.52#ibcon#about to write, iclass 32, count 0 2006.174.01:36:26.52#ibcon#wrote, iclass 32, count 0 2006.174.01:36:26.52#ibcon#about to read 3, iclass 32, count 0 2006.174.01:36:26.53#ibcon#read 3, iclass 32, count 0 2006.174.01:36:26.53#ibcon#about to read 4, iclass 32, count 0 2006.174.01:36:26.53#ibcon#read 4, iclass 32, count 0 2006.174.01:36:26.53#ibcon#about to read 5, iclass 32, count 0 2006.174.01:36:26.53#ibcon#read 5, iclass 32, count 0 2006.174.01:36:26.53#ibcon#about to read 6, iclass 32, count 0 2006.174.01:36:26.53#ibcon#read 6, iclass 32, count 0 2006.174.01:36:26.53#ibcon#end of sib2, iclass 32, count 0 2006.174.01:36:26.53#ibcon#*mode == 0, iclass 32, count 0 2006.174.01:36:26.53#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.174.01:36:26.53#ibcon#[28=FRQ=03,649.99\r\n] 2006.174.01:36:26.53#ibcon#*before write, iclass 32, count 0 2006.174.01:36:26.53#ibcon#enter sib2, iclass 32, count 0 2006.174.01:36:26.53#ibcon#flushed, iclass 32, count 0 2006.174.01:36:26.53#ibcon#about to write, iclass 32, count 0 2006.174.01:36:26.53#ibcon#wrote, iclass 32, count 0 2006.174.01:36:26.53#ibcon#about to read 3, iclass 32, count 0 2006.174.01:36:26.57#ibcon#read 3, iclass 32, count 0 2006.174.01:36:26.57#ibcon#about to read 4, iclass 32, count 0 2006.174.01:36:26.57#ibcon#read 4, iclass 32, count 0 2006.174.01:36:26.57#ibcon#about to read 5, iclass 32, count 0 2006.174.01:36:26.57#ibcon#read 5, iclass 32, count 0 2006.174.01:36:26.57#ibcon#about to read 6, iclass 32, count 0 2006.174.01:36:26.57#ibcon#read 6, iclass 32, count 0 2006.174.01:36:26.57#ibcon#end of sib2, iclass 32, count 0 2006.174.01:36:26.57#ibcon#*after write, iclass 32, count 0 2006.174.01:36:26.57#ibcon#*before return 0, iclass 32, count 0 2006.174.01:36:26.57#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.174.01:36:26.57#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.174.01:36:26.57#ibcon#about to clear, iclass 32 cls_cnt 0 2006.174.01:36:26.57#ibcon#cleared, iclass 32 cls_cnt 0 2006.174.01:36:26.57$vck44/vb=3,4 2006.174.01:36:26.58#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.174.01:36:26.58#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.174.01:36:26.58#ibcon#ireg 11 cls_cnt 2 2006.174.01:36:26.58#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.174.01:36:26.62#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.174.01:36:26.62#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.174.01:36:26.62#ibcon#enter wrdev, iclass 34, count 2 2006.174.01:36:26.62#ibcon#first serial, iclass 34, count 2 2006.174.01:36:26.62#ibcon#enter sib2, iclass 34, count 2 2006.174.01:36:26.62#ibcon#flushed, iclass 34, count 2 2006.174.01:36:26.62#ibcon#about to write, iclass 34, count 2 2006.174.01:36:26.62#ibcon#wrote, iclass 34, count 2 2006.174.01:36:26.62#ibcon#about to read 3, iclass 34, count 2 2006.174.01:36:26.64#ibcon#read 3, iclass 34, count 2 2006.174.01:36:26.64#ibcon#about to read 4, iclass 34, count 2 2006.174.01:36:26.64#ibcon#read 4, iclass 34, count 2 2006.174.01:36:26.64#ibcon#about to read 5, iclass 34, count 2 2006.174.01:36:26.64#ibcon#read 5, iclass 34, count 2 2006.174.01:36:26.64#ibcon#about to read 6, iclass 34, count 2 2006.174.01:36:26.64#ibcon#read 6, iclass 34, count 2 2006.174.01:36:26.64#ibcon#end of sib2, iclass 34, count 2 2006.174.01:36:26.64#ibcon#*mode == 0, iclass 34, count 2 2006.174.01:36:26.64#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.174.01:36:26.64#ibcon#[27=AT03-04\r\n] 2006.174.01:36:26.64#ibcon#*before write, iclass 34, count 2 2006.174.01:36:26.64#ibcon#enter sib2, iclass 34, count 2 2006.174.01:36:26.64#ibcon#flushed, iclass 34, count 2 2006.174.01:36:26.64#ibcon#about to write, iclass 34, count 2 2006.174.01:36:26.64#ibcon#wrote, iclass 34, count 2 2006.174.01:36:26.64#ibcon#about to read 3, iclass 34, count 2 2006.174.01:36:26.67#ibcon#read 3, iclass 34, count 2 2006.174.01:36:26.67#ibcon#about to read 4, iclass 34, count 2 2006.174.01:36:26.67#ibcon#read 4, iclass 34, count 2 2006.174.01:36:26.67#ibcon#about to read 5, iclass 34, count 2 2006.174.01:36:26.67#ibcon#read 5, iclass 34, count 2 2006.174.01:36:26.67#ibcon#about to read 6, iclass 34, count 2 2006.174.01:36:26.67#ibcon#read 6, iclass 34, count 2 2006.174.01:36:26.67#ibcon#end of sib2, iclass 34, count 2 2006.174.01:36:26.67#ibcon#*after write, iclass 34, count 2 2006.174.01:36:26.67#ibcon#*before return 0, iclass 34, count 2 2006.174.01:36:26.67#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.174.01:36:26.67#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.174.01:36:26.67#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.174.01:36:26.67#ibcon#ireg 7 cls_cnt 0 2006.174.01:36:26.67#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.174.01:36:26.79#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.174.01:36:26.79#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.174.01:36:26.79#ibcon#enter wrdev, iclass 34, count 0 2006.174.01:36:26.79#ibcon#first serial, iclass 34, count 0 2006.174.01:36:26.79#ibcon#enter sib2, iclass 34, count 0 2006.174.01:36:26.79#ibcon#flushed, iclass 34, count 0 2006.174.01:36:26.79#ibcon#about to write, iclass 34, count 0 2006.174.01:36:26.79#ibcon#wrote, iclass 34, count 0 2006.174.01:36:26.79#ibcon#about to read 3, iclass 34, count 0 2006.174.01:36:26.81#ibcon#read 3, iclass 34, count 0 2006.174.01:36:26.81#ibcon#about to read 4, iclass 34, count 0 2006.174.01:36:26.81#ibcon#read 4, iclass 34, count 0 2006.174.01:36:26.81#ibcon#about to read 5, iclass 34, count 0 2006.174.01:36:26.81#ibcon#read 5, iclass 34, count 0 2006.174.01:36:26.81#ibcon#about to read 6, iclass 34, count 0 2006.174.01:36:26.81#ibcon#read 6, iclass 34, count 0 2006.174.01:36:26.81#ibcon#end of sib2, iclass 34, count 0 2006.174.01:36:26.81#ibcon#*mode == 0, iclass 34, count 0 2006.174.01:36:26.81#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.174.01:36:26.81#ibcon#[27=USB\r\n] 2006.174.01:36:26.81#ibcon#*before write, iclass 34, count 0 2006.174.01:36:26.81#ibcon#enter sib2, iclass 34, count 0 2006.174.01:36:26.81#ibcon#flushed, iclass 34, count 0 2006.174.01:36:26.81#ibcon#about to write, iclass 34, count 0 2006.174.01:36:26.81#ibcon#wrote, iclass 34, count 0 2006.174.01:36:26.81#ibcon#about to read 3, iclass 34, count 0 2006.174.01:36:26.84#ibcon#read 3, iclass 34, count 0 2006.174.01:36:26.84#ibcon#about to read 4, iclass 34, count 0 2006.174.01:36:26.84#ibcon#read 4, iclass 34, count 0 2006.174.01:36:26.84#ibcon#about to read 5, iclass 34, count 0 2006.174.01:36:26.84#ibcon#read 5, iclass 34, count 0 2006.174.01:36:26.84#ibcon#about to read 6, iclass 34, count 0 2006.174.01:36:26.84#ibcon#read 6, iclass 34, count 0 2006.174.01:36:26.84#ibcon#end of sib2, iclass 34, count 0 2006.174.01:36:26.84#ibcon#*after write, iclass 34, count 0 2006.174.01:36:26.84#ibcon#*before return 0, iclass 34, count 0 2006.174.01:36:26.84#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.174.01:36:26.84#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.174.01:36:26.84#ibcon#about to clear, iclass 34 cls_cnt 0 2006.174.01:36:26.84#ibcon#cleared, iclass 34 cls_cnt 0 2006.174.01:36:26.84$vck44/vblo=4,679.99 2006.174.01:36:26.84#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.174.01:36:26.84#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.174.01:36:26.84#ibcon#ireg 17 cls_cnt 0 2006.174.01:36:26.84#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.174.01:36:26.84#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.174.01:36:26.84#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.174.01:36:26.84#ibcon#enter wrdev, iclass 36, count 0 2006.174.01:36:26.84#ibcon#first serial, iclass 36, count 0 2006.174.01:36:26.84#ibcon#enter sib2, iclass 36, count 0 2006.174.01:36:26.85#ibcon#flushed, iclass 36, count 0 2006.174.01:36:26.85#ibcon#about to write, iclass 36, count 0 2006.174.01:36:26.85#ibcon#wrote, iclass 36, count 0 2006.174.01:36:26.85#ibcon#about to read 3, iclass 36, count 0 2006.174.01:36:26.86#ibcon#read 3, iclass 36, count 0 2006.174.01:36:26.86#ibcon#about to read 4, iclass 36, count 0 2006.174.01:36:26.86#ibcon#read 4, iclass 36, count 0 2006.174.01:36:26.86#ibcon#about to read 5, iclass 36, count 0 2006.174.01:36:26.86#ibcon#read 5, iclass 36, count 0 2006.174.01:36:26.86#ibcon#about to read 6, iclass 36, count 0 2006.174.01:36:26.86#ibcon#read 6, iclass 36, count 0 2006.174.01:36:26.86#ibcon#end of sib2, iclass 36, count 0 2006.174.01:36:26.86#ibcon#*mode == 0, iclass 36, count 0 2006.174.01:36:26.86#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.174.01:36:26.86#ibcon#[28=FRQ=04,679.99\r\n] 2006.174.01:36:26.86#ibcon#*before write, iclass 36, count 0 2006.174.01:36:26.86#ibcon#enter sib2, iclass 36, count 0 2006.174.01:36:26.86#ibcon#flushed, iclass 36, count 0 2006.174.01:36:26.86#ibcon#about to write, iclass 36, count 0 2006.174.01:36:26.86#ibcon#wrote, iclass 36, count 0 2006.174.01:36:26.86#ibcon#about to read 3, iclass 36, count 0 2006.174.01:36:26.90#ibcon#read 3, iclass 36, count 0 2006.174.01:36:26.90#ibcon#about to read 4, iclass 36, count 0 2006.174.01:36:26.90#ibcon#read 4, iclass 36, count 0 2006.174.01:36:26.90#ibcon#about to read 5, iclass 36, count 0 2006.174.01:36:26.90#ibcon#read 5, iclass 36, count 0 2006.174.01:36:26.90#ibcon#about to read 6, iclass 36, count 0 2006.174.01:36:26.90#ibcon#read 6, iclass 36, count 0 2006.174.01:36:26.90#ibcon#end of sib2, iclass 36, count 0 2006.174.01:36:26.90#ibcon#*after write, iclass 36, count 0 2006.174.01:36:26.90#ibcon#*before return 0, iclass 36, count 0 2006.174.01:36:26.90#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.174.01:36:26.90#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.174.01:36:26.90#ibcon#about to clear, iclass 36 cls_cnt 0 2006.174.01:36:26.90#ibcon#cleared, iclass 36 cls_cnt 0 2006.174.01:36:26.90$vck44/vb=4,4 2006.174.01:36:26.90#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.174.01:36:26.90#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.174.01:36:26.90#ibcon#ireg 11 cls_cnt 2 2006.174.01:36:26.90#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.174.01:36:26.96#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.174.01:36:26.96#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.174.01:36:26.96#ibcon#enter wrdev, iclass 38, count 2 2006.174.01:36:26.96#ibcon#first serial, iclass 38, count 2 2006.174.01:36:26.96#ibcon#enter sib2, iclass 38, count 2 2006.174.01:36:26.96#ibcon#flushed, iclass 38, count 2 2006.174.01:36:26.96#ibcon#about to write, iclass 38, count 2 2006.174.01:36:26.96#ibcon#wrote, iclass 38, count 2 2006.174.01:36:26.96#ibcon#about to read 3, iclass 38, count 2 2006.174.01:36:26.98#ibcon#read 3, iclass 38, count 2 2006.174.01:36:26.98#ibcon#about to read 4, iclass 38, count 2 2006.174.01:36:26.98#ibcon#read 4, iclass 38, count 2 2006.174.01:36:26.98#ibcon#about to read 5, iclass 38, count 2 2006.174.01:36:26.98#ibcon#read 5, iclass 38, count 2 2006.174.01:36:26.98#ibcon#about to read 6, iclass 38, count 2 2006.174.01:36:26.98#ibcon#read 6, iclass 38, count 2 2006.174.01:36:26.98#ibcon#end of sib2, iclass 38, count 2 2006.174.01:36:26.98#ibcon#*mode == 0, iclass 38, count 2 2006.174.01:36:26.98#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.174.01:36:26.98#ibcon#[27=AT04-04\r\n] 2006.174.01:36:26.98#ibcon#*before write, iclass 38, count 2 2006.174.01:36:26.98#ibcon#enter sib2, iclass 38, count 2 2006.174.01:36:26.98#ibcon#flushed, iclass 38, count 2 2006.174.01:36:26.98#ibcon#about to write, iclass 38, count 2 2006.174.01:36:26.98#ibcon#wrote, iclass 38, count 2 2006.174.01:36:26.98#ibcon#about to read 3, iclass 38, count 2 2006.174.01:36:27.01#ibcon#read 3, iclass 38, count 2 2006.174.01:36:27.01#ibcon#about to read 4, iclass 38, count 2 2006.174.01:36:27.01#ibcon#read 4, iclass 38, count 2 2006.174.01:36:27.01#ibcon#about to read 5, iclass 38, count 2 2006.174.01:36:27.01#ibcon#read 5, iclass 38, count 2 2006.174.01:36:27.01#ibcon#about to read 6, iclass 38, count 2 2006.174.01:36:27.01#ibcon#read 6, iclass 38, count 2 2006.174.01:36:27.01#ibcon#end of sib2, iclass 38, count 2 2006.174.01:36:27.01#ibcon#*after write, iclass 38, count 2 2006.174.01:36:27.01#ibcon#*before return 0, iclass 38, count 2 2006.174.01:36:27.01#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.174.01:36:27.01#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.174.01:36:27.01#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.174.01:36:27.01#ibcon#ireg 7 cls_cnt 0 2006.174.01:36:27.01#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.174.01:36:27.13#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.174.01:36:27.13#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.174.01:36:27.13#ibcon#enter wrdev, iclass 38, count 0 2006.174.01:36:27.13#ibcon#first serial, iclass 38, count 0 2006.174.01:36:27.13#ibcon#enter sib2, iclass 38, count 0 2006.174.01:36:27.13#ibcon#flushed, iclass 38, count 0 2006.174.01:36:27.13#ibcon#about to write, iclass 38, count 0 2006.174.01:36:27.13#ibcon#wrote, iclass 38, count 0 2006.174.01:36:27.13#ibcon#about to read 3, iclass 38, count 0 2006.174.01:36:27.15#ibcon#read 3, iclass 38, count 0 2006.174.01:36:27.15#ibcon#about to read 4, iclass 38, count 0 2006.174.01:36:27.15#ibcon#read 4, iclass 38, count 0 2006.174.01:36:27.15#ibcon#about to read 5, iclass 38, count 0 2006.174.01:36:27.15#ibcon#read 5, iclass 38, count 0 2006.174.01:36:27.15#ibcon#about to read 6, iclass 38, count 0 2006.174.01:36:27.15#ibcon#read 6, iclass 38, count 0 2006.174.01:36:27.15#ibcon#end of sib2, iclass 38, count 0 2006.174.01:36:27.15#ibcon#*mode == 0, iclass 38, count 0 2006.174.01:36:27.15#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.174.01:36:27.15#ibcon#[27=USB\r\n] 2006.174.01:36:27.15#ibcon#*before write, iclass 38, count 0 2006.174.01:36:27.15#ibcon#enter sib2, iclass 38, count 0 2006.174.01:36:27.15#ibcon#flushed, iclass 38, count 0 2006.174.01:36:27.15#ibcon#about to write, iclass 38, count 0 2006.174.01:36:27.15#ibcon#wrote, iclass 38, count 0 2006.174.01:36:27.15#ibcon#about to read 3, iclass 38, count 0 2006.174.01:36:27.18#ibcon#read 3, iclass 38, count 0 2006.174.01:36:27.18#ibcon#about to read 4, iclass 38, count 0 2006.174.01:36:27.18#ibcon#read 4, iclass 38, count 0 2006.174.01:36:27.18#ibcon#about to read 5, iclass 38, count 0 2006.174.01:36:27.18#ibcon#read 5, iclass 38, count 0 2006.174.01:36:27.18#ibcon#about to read 6, iclass 38, count 0 2006.174.01:36:27.18#ibcon#read 6, iclass 38, count 0 2006.174.01:36:27.18#ibcon#end of sib2, iclass 38, count 0 2006.174.01:36:27.18#ibcon#*after write, iclass 38, count 0 2006.174.01:36:27.18#ibcon#*before return 0, iclass 38, count 0 2006.174.01:36:27.18#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.174.01:36:27.18#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.174.01:36:27.18#ibcon#about to clear, iclass 38 cls_cnt 0 2006.174.01:36:27.18#ibcon#cleared, iclass 38 cls_cnt 0 2006.174.01:36:27.18$vck44/vblo=5,709.99 2006.174.01:36:27.18#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.174.01:36:27.18#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.174.01:36:27.18#ibcon#ireg 17 cls_cnt 0 2006.174.01:36:27.18#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.174.01:36:27.18#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.174.01:36:27.18#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.174.01:36:27.18#ibcon#enter wrdev, iclass 40, count 0 2006.174.01:36:27.18#ibcon#first serial, iclass 40, count 0 2006.174.01:36:27.19#ibcon#enter sib2, iclass 40, count 0 2006.174.01:36:27.19#ibcon#flushed, iclass 40, count 0 2006.174.01:36:27.19#ibcon#about to write, iclass 40, count 0 2006.174.01:36:27.19#ibcon#wrote, iclass 40, count 0 2006.174.01:36:27.19#ibcon#about to read 3, iclass 40, count 0 2006.174.01:36:27.20#ibcon#read 3, iclass 40, count 0 2006.174.01:36:27.20#ibcon#about to read 4, iclass 40, count 0 2006.174.01:36:27.20#ibcon#read 4, iclass 40, count 0 2006.174.01:36:27.20#ibcon#about to read 5, iclass 40, count 0 2006.174.01:36:27.20#ibcon#read 5, iclass 40, count 0 2006.174.01:36:27.20#ibcon#about to read 6, iclass 40, count 0 2006.174.01:36:27.20#ibcon#read 6, iclass 40, count 0 2006.174.01:36:27.20#ibcon#end of sib2, iclass 40, count 0 2006.174.01:36:27.20#ibcon#*mode == 0, iclass 40, count 0 2006.174.01:36:27.20#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.174.01:36:27.20#ibcon#[28=FRQ=05,709.99\r\n] 2006.174.01:36:27.20#ibcon#*before write, iclass 40, count 0 2006.174.01:36:27.20#ibcon#enter sib2, iclass 40, count 0 2006.174.01:36:27.20#ibcon#flushed, iclass 40, count 0 2006.174.01:36:27.20#ibcon#about to write, iclass 40, count 0 2006.174.01:36:27.20#ibcon#wrote, iclass 40, count 0 2006.174.01:36:27.20#ibcon#about to read 3, iclass 40, count 0 2006.174.01:36:27.24#ibcon#read 3, iclass 40, count 0 2006.174.01:36:27.24#ibcon#about to read 4, iclass 40, count 0 2006.174.01:36:27.24#ibcon#read 4, iclass 40, count 0 2006.174.01:36:27.24#ibcon#about to read 5, iclass 40, count 0 2006.174.01:36:27.24#ibcon#read 5, iclass 40, count 0 2006.174.01:36:27.24#ibcon#about to read 6, iclass 40, count 0 2006.174.01:36:27.24#ibcon#read 6, iclass 40, count 0 2006.174.01:36:27.24#ibcon#end of sib2, iclass 40, count 0 2006.174.01:36:27.24#ibcon#*after write, iclass 40, count 0 2006.174.01:36:27.24#ibcon#*before return 0, iclass 40, count 0 2006.174.01:36:27.24#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.174.01:36:27.24#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.174.01:36:27.24#ibcon#about to clear, iclass 40 cls_cnt 0 2006.174.01:36:27.24#ibcon#cleared, iclass 40 cls_cnt 0 2006.174.01:36:27.24$vck44/vb=5,4 2006.174.01:36:27.24#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.174.01:36:27.24#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.174.01:36:27.24#ibcon#ireg 11 cls_cnt 2 2006.174.01:36:27.24#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.174.01:36:27.30#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.174.01:36:27.30#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.174.01:36:27.30#ibcon#enter wrdev, iclass 4, count 2 2006.174.01:36:27.30#ibcon#first serial, iclass 4, count 2 2006.174.01:36:27.30#ibcon#enter sib2, iclass 4, count 2 2006.174.01:36:27.30#ibcon#flushed, iclass 4, count 2 2006.174.01:36:27.30#ibcon#about to write, iclass 4, count 2 2006.174.01:36:27.30#ibcon#wrote, iclass 4, count 2 2006.174.01:36:27.30#ibcon#about to read 3, iclass 4, count 2 2006.174.01:36:27.32#ibcon#read 3, iclass 4, count 2 2006.174.01:36:27.32#ibcon#about to read 4, iclass 4, count 2 2006.174.01:36:27.32#ibcon#read 4, iclass 4, count 2 2006.174.01:36:27.32#ibcon#about to read 5, iclass 4, count 2 2006.174.01:36:27.32#ibcon#read 5, iclass 4, count 2 2006.174.01:36:27.32#ibcon#about to read 6, iclass 4, count 2 2006.174.01:36:27.32#ibcon#read 6, iclass 4, count 2 2006.174.01:36:27.32#ibcon#end of sib2, iclass 4, count 2 2006.174.01:36:27.32#ibcon#*mode == 0, iclass 4, count 2 2006.174.01:36:27.32#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.174.01:36:27.32#ibcon#[27=AT05-04\r\n] 2006.174.01:36:27.32#ibcon#*before write, iclass 4, count 2 2006.174.01:36:27.32#ibcon#enter sib2, iclass 4, count 2 2006.174.01:36:27.32#ibcon#flushed, iclass 4, count 2 2006.174.01:36:27.32#ibcon#about to write, iclass 4, count 2 2006.174.01:36:27.32#ibcon#wrote, iclass 4, count 2 2006.174.01:36:27.32#ibcon#about to read 3, iclass 4, count 2 2006.174.01:36:27.35#ibcon#read 3, iclass 4, count 2 2006.174.01:36:27.35#ibcon#about to read 4, iclass 4, count 2 2006.174.01:36:27.35#ibcon#read 4, iclass 4, count 2 2006.174.01:36:27.35#ibcon#about to read 5, iclass 4, count 2 2006.174.01:36:27.35#ibcon#read 5, iclass 4, count 2 2006.174.01:36:27.35#ibcon#about to read 6, iclass 4, count 2 2006.174.01:36:27.35#ibcon#read 6, iclass 4, count 2 2006.174.01:36:27.35#ibcon#end of sib2, iclass 4, count 2 2006.174.01:36:27.35#ibcon#*after write, iclass 4, count 2 2006.174.01:36:27.35#ibcon#*before return 0, iclass 4, count 2 2006.174.01:36:27.35#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.174.01:36:27.35#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.174.01:36:27.35#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.174.01:36:27.35#ibcon#ireg 7 cls_cnt 0 2006.174.01:36:27.35#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.174.01:36:27.47#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.174.01:36:27.47#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.174.01:36:27.47#ibcon#enter wrdev, iclass 4, count 0 2006.174.01:36:27.47#ibcon#first serial, iclass 4, count 0 2006.174.01:36:27.47#ibcon#enter sib2, iclass 4, count 0 2006.174.01:36:27.47#ibcon#flushed, iclass 4, count 0 2006.174.01:36:27.47#ibcon#about to write, iclass 4, count 0 2006.174.01:36:27.47#ibcon#wrote, iclass 4, count 0 2006.174.01:36:27.47#ibcon#about to read 3, iclass 4, count 0 2006.174.01:36:27.49#ibcon#read 3, iclass 4, count 0 2006.174.01:36:27.49#ibcon#about to read 4, iclass 4, count 0 2006.174.01:36:27.49#ibcon#read 4, iclass 4, count 0 2006.174.01:36:27.49#ibcon#about to read 5, iclass 4, count 0 2006.174.01:36:27.49#ibcon#read 5, iclass 4, count 0 2006.174.01:36:27.49#ibcon#about to read 6, iclass 4, count 0 2006.174.01:36:27.49#ibcon#read 6, iclass 4, count 0 2006.174.01:36:27.49#ibcon#end of sib2, iclass 4, count 0 2006.174.01:36:27.49#ibcon#*mode == 0, iclass 4, count 0 2006.174.01:36:27.49#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.174.01:36:27.49#ibcon#[27=USB\r\n] 2006.174.01:36:27.49#ibcon#*before write, iclass 4, count 0 2006.174.01:36:27.49#ibcon#enter sib2, iclass 4, count 0 2006.174.01:36:27.49#ibcon#flushed, iclass 4, count 0 2006.174.01:36:27.49#ibcon#about to write, iclass 4, count 0 2006.174.01:36:27.49#ibcon#wrote, iclass 4, count 0 2006.174.01:36:27.49#ibcon#about to read 3, iclass 4, count 0 2006.174.01:36:27.52#ibcon#read 3, iclass 4, count 0 2006.174.01:36:27.52#ibcon#about to read 4, iclass 4, count 0 2006.174.01:36:27.52#ibcon#read 4, iclass 4, count 0 2006.174.01:36:27.52#ibcon#about to read 5, iclass 4, count 0 2006.174.01:36:27.52#ibcon#read 5, iclass 4, count 0 2006.174.01:36:27.52#ibcon#about to read 6, iclass 4, count 0 2006.174.01:36:27.52#ibcon#read 6, iclass 4, count 0 2006.174.01:36:27.52#ibcon#end of sib2, iclass 4, count 0 2006.174.01:36:27.52#ibcon#*after write, iclass 4, count 0 2006.174.01:36:27.52#ibcon#*before return 0, iclass 4, count 0 2006.174.01:36:27.52#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.174.01:36:27.52#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.174.01:36:27.52#ibcon#about to clear, iclass 4 cls_cnt 0 2006.174.01:36:27.52#ibcon#cleared, iclass 4 cls_cnt 0 2006.174.01:36:27.52$vck44/vblo=6,719.99 2006.174.01:36:27.52#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.174.01:36:27.52#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.174.01:36:27.52#ibcon#ireg 17 cls_cnt 0 2006.174.01:36:27.52#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.174.01:36:27.52#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.174.01:36:27.52#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.174.01:36:27.53#ibcon#enter wrdev, iclass 6, count 0 2006.174.01:36:27.53#ibcon#first serial, iclass 6, count 0 2006.174.01:36:27.53#ibcon#enter sib2, iclass 6, count 0 2006.174.01:36:27.53#ibcon#flushed, iclass 6, count 0 2006.174.01:36:27.53#ibcon#about to write, iclass 6, count 0 2006.174.01:36:27.53#ibcon#wrote, iclass 6, count 0 2006.174.01:36:27.53#ibcon#about to read 3, iclass 6, count 0 2006.174.01:36:27.54#ibcon#read 3, iclass 6, count 0 2006.174.01:36:27.54#ibcon#about to read 4, iclass 6, count 0 2006.174.01:36:27.54#ibcon#read 4, iclass 6, count 0 2006.174.01:36:27.54#ibcon#about to read 5, iclass 6, count 0 2006.174.01:36:27.54#ibcon#read 5, iclass 6, count 0 2006.174.01:36:27.54#ibcon#about to read 6, iclass 6, count 0 2006.174.01:36:27.54#ibcon#read 6, iclass 6, count 0 2006.174.01:36:27.54#ibcon#end of sib2, iclass 6, count 0 2006.174.01:36:27.54#ibcon#*mode == 0, iclass 6, count 0 2006.174.01:36:27.54#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.174.01:36:27.54#ibcon#[28=FRQ=06,719.99\r\n] 2006.174.01:36:27.54#ibcon#*before write, iclass 6, count 0 2006.174.01:36:27.54#ibcon#enter sib2, iclass 6, count 0 2006.174.01:36:27.54#ibcon#flushed, iclass 6, count 0 2006.174.01:36:27.54#ibcon#about to write, iclass 6, count 0 2006.174.01:36:27.54#ibcon#wrote, iclass 6, count 0 2006.174.01:36:27.54#ibcon#about to read 3, iclass 6, count 0 2006.174.01:36:27.58#ibcon#read 3, iclass 6, count 0 2006.174.01:36:27.58#ibcon#about to read 4, iclass 6, count 0 2006.174.01:36:27.58#ibcon#read 4, iclass 6, count 0 2006.174.01:36:27.58#ibcon#about to read 5, iclass 6, count 0 2006.174.01:36:27.58#ibcon#read 5, iclass 6, count 0 2006.174.01:36:27.58#ibcon#about to read 6, iclass 6, count 0 2006.174.01:36:27.58#ibcon#read 6, iclass 6, count 0 2006.174.01:36:27.58#ibcon#end of sib2, iclass 6, count 0 2006.174.01:36:27.58#ibcon#*after write, iclass 6, count 0 2006.174.01:36:27.58#ibcon#*before return 0, iclass 6, count 0 2006.174.01:36:27.58#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.174.01:36:27.58#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.174.01:36:27.58#ibcon#about to clear, iclass 6 cls_cnt 0 2006.174.01:36:27.58#ibcon#cleared, iclass 6 cls_cnt 0 2006.174.01:36:27.58$vck44/vb=6,4 2006.174.01:36:27.58#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.174.01:36:27.58#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.174.01:36:27.58#ibcon#ireg 11 cls_cnt 2 2006.174.01:36:27.58#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.174.01:36:27.64#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.174.01:36:27.64#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.174.01:36:27.64#ibcon#enter wrdev, iclass 10, count 2 2006.174.01:36:27.64#ibcon#first serial, iclass 10, count 2 2006.174.01:36:27.64#ibcon#enter sib2, iclass 10, count 2 2006.174.01:36:27.64#ibcon#flushed, iclass 10, count 2 2006.174.01:36:27.64#ibcon#about to write, iclass 10, count 2 2006.174.01:36:27.64#ibcon#wrote, iclass 10, count 2 2006.174.01:36:27.64#ibcon#about to read 3, iclass 10, count 2 2006.174.01:36:27.66#ibcon#read 3, iclass 10, count 2 2006.174.01:36:27.66#ibcon#about to read 4, iclass 10, count 2 2006.174.01:36:27.66#ibcon#read 4, iclass 10, count 2 2006.174.01:36:27.66#ibcon#about to read 5, iclass 10, count 2 2006.174.01:36:27.66#ibcon#read 5, iclass 10, count 2 2006.174.01:36:27.66#ibcon#about to read 6, iclass 10, count 2 2006.174.01:36:27.66#ibcon#read 6, iclass 10, count 2 2006.174.01:36:27.66#ibcon#end of sib2, iclass 10, count 2 2006.174.01:36:27.66#ibcon#*mode == 0, iclass 10, count 2 2006.174.01:36:27.66#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.174.01:36:27.66#ibcon#[27=AT06-04\r\n] 2006.174.01:36:27.66#ibcon#*before write, iclass 10, count 2 2006.174.01:36:27.66#ibcon#enter sib2, iclass 10, count 2 2006.174.01:36:27.66#ibcon#flushed, iclass 10, count 2 2006.174.01:36:27.66#ibcon#about to write, iclass 10, count 2 2006.174.01:36:27.66#ibcon#wrote, iclass 10, count 2 2006.174.01:36:27.66#ibcon#about to read 3, iclass 10, count 2 2006.174.01:36:27.69#ibcon#read 3, iclass 10, count 2 2006.174.01:36:27.69#ibcon#about to read 4, iclass 10, count 2 2006.174.01:36:27.69#ibcon#read 4, iclass 10, count 2 2006.174.01:36:27.69#ibcon#about to read 5, iclass 10, count 2 2006.174.01:36:27.69#ibcon#read 5, iclass 10, count 2 2006.174.01:36:27.69#ibcon#about to read 6, iclass 10, count 2 2006.174.01:36:27.69#ibcon#read 6, iclass 10, count 2 2006.174.01:36:27.69#ibcon#end of sib2, iclass 10, count 2 2006.174.01:36:27.69#ibcon#*after write, iclass 10, count 2 2006.174.01:36:27.69#ibcon#*before return 0, iclass 10, count 2 2006.174.01:36:27.69#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.174.01:36:27.69#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.174.01:36:27.69#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.174.01:36:27.69#ibcon#ireg 7 cls_cnt 0 2006.174.01:36:27.69#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.174.01:36:27.81#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.174.01:36:27.81#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.174.01:36:27.81#ibcon#enter wrdev, iclass 10, count 0 2006.174.01:36:27.81#ibcon#first serial, iclass 10, count 0 2006.174.01:36:27.81#ibcon#enter sib2, iclass 10, count 0 2006.174.01:36:27.81#ibcon#flushed, iclass 10, count 0 2006.174.01:36:27.81#ibcon#about to write, iclass 10, count 0 2006.174.01:36:27.81#ibcon#wrote, iclass 10, count 0 2006.174.01:36:27.81#ibcon#about to read 3, iclass 10, count 0 2006.174.01:36:27.83#ibcon#read 3, iclass 10, count 0 2006.174.01:36:27.83#ibcon#about to read 4, iclass 10, count 0 2006.174.01:36:27.83#ibcon#read 4, iclass 10, count 0 2006.174.01:36:27.83#ibcon#about to read 5, iclass 10, count 0 2006.174.01:36:27.83#ibcon#read 5, iclass 10, count 0 2006.174.01:36:27.83#ibcon#about to read 6, iclass 10, count 0 2006.174.01:36:27.83#ibcon#read 6, iclass 10, count 0 2006.174.01:36:27.83#ibcon#end of sib2, iclass 10, count 0 2006.174.01:36:27.83#ibcon#*mode == 0, iclass 10, count 0 2006.174.01:36:27.83#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.174.01:36:27.83#ibcon#[27=USB\r\n] 2006.174.01:36:27.83#ibcon#*before write, iclass 10, count 0 2006.174.01:36:27.83#ibcon#enter sib2, iclass 10, count 0 2006.174.01:36:27.83#ibcon#flushed, iclass 10, count 0 2006.174.01:36:27.83#ibcon#about to write, iclass 10, count 0 2006.174.01:36:27.83#ibcon#wrote, iclass 10, count 0 2006.174.01:36:27.83#ibcon#about to read 3, iclass 10, count 0 2006.174.01:36:27.86#ibcon#read 3, iclass 10, count 0 2006.174.01:36:27.86#ibcon#about to read 4, iclass 10, count 0 2006.174.01:36:27.86#ibcon#read 4, iclass 10, count 0 2006.174.01:36:27.86#ibcon#about to read 5, iclass 10, count 0 2006.174.01:36:27.86#ibcon#read 5, iclass 10, count 0 2006.174.01:36:27.86#ibcon#about to read 6, iclass 10, count 0 2006.174.01:36:27.86#ibcon#read 6, iclass 10, count 0 2006.174.01:36:27.86#ibcon#end of sib2, iclass 10, count 0 2006.174.01:36:27.86#ibcon#*after write, iclass 10, count 0 2006.174.01:36:27.86#ibcon#*before return 0, iclass 10, count 0 2006.174.01:36:27.86#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.174.01:36:27.86#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.174.01:36:27.86#ibcon#about to clear, iclass 10 cls_cnt 0 2006.174.01:36:27.86#ibcon#cleared, iclass 10 cls_cnt 0 2006.174.01:36:27.86$vck44/vblo=7,734.99 2006.174.01:36:27.86#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.174.01:36:27.86#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.174.01:36:27.86#ibcon#ireg 17 cls_cnt 0 2006.174.01:36:27.86#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.174.01:36:27.86#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.174.01:36:27.86#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.174.01:36:27.87#ibcon#enter wrdev, iclass 12, count 0 2006.174.01:36:27.87#ibcon#first serial, iclass 12, count 0 2006.174.01:36:27.87#ibcon#enter sib2, iclass 12, count 0 2006.174.01:36:27.87#ibcon#flushed, iclass 12, count 0 2006.174.01:36:27.87#ibcon#about to write, iclass 12, count 0 2006.174.01:36:27.87#ibcon#wrote, iclass 12, count 0 2006.174.01:36:27.87#ibcon#about to read 3, iclass 12, count 0 2006.174.01:36:27.88#ibcon#read 3, iclass 12, count 0 2006.174.01:36:27.88#ibcon#about to read 4, iclass 12, count 0 2006.174.01:36:27.88#ibcon#read 4, iclass 12, count 0 2006.174.01:36:27.88#ibcon#about to read 5, iclass 12, count 0 2006.174.01:36:27.88#ibcon#read 5, iclass 12, count 0 2006.174.01:36:27.88#ibcon#about to read 6, iclass 12, count 0 2006.174.01:36:27.88#ibcon#read 6, iclass 12, count 0 2006.174.01:36:27.88#ibcon#end of sib2, iclass 12, count 0 2006.174.01:36:27.88#ibcon#*mode == 0, iclass 12, count 0 2006.174.01:36:27.88#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.174.01:36:27.88#ibcon#[28=FRQ=07,734.99\r\n] 2006.174.01:36:27.88#ibcon#*before write, iclass 12, count 0 2006.174.01:36:27.88#ibcon#enter sib2, iclass 12, count 0 2006.174.01:36:27.88#ibcon#flushed, iclass 12, count 0 2006.174.01:36:27.88#ibcon#about to write, iclass 12, count 0 2006.174.01:36:27.88#ibcon#wrote, iclass 12, count 0 2006.174.01:36:27.88#ibcon#about to read 3, iclass 12, count 0 2006.174.01:36:27.92#ibcon#read 3, iclass 12, count 0 2006.174.01:36:27.92#ibcon#about to read 4, iclass 12, count 0 2006.174.01:36:27.92#ibcon#read 4, iclass 12, count 0 2006.174.01:36:27.92#ibcon#about to read 5, iclass 12, count 0 2006.174.01:36:27.92#ibcon#read 5, iclass 12, count 0 2006.174.01:36:27.92#ibcon#about to read 6, iclass 12, count 0 2006.174.01:36:27.92#ibcon#read 6, iclass 12, count 0 2006.174.01:36:27.92#ibcon#end of sib2, iclass 12, count 0 2006.174.01:36:27.92#ibcon#*after write, iclass 12, count 0 2006.174.01:36:27.92#ibcon#*before return 0, iclass 12, count 0 2006.174.01:36:27.92#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.174.01:36:27.92#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.174.01:36:27.92#ibcon#about to clear, iclass 12 cls_cnt 0 2006.174.01:36:27.92#ibcon#cleared, iclass 12 cls_cnt 0 2006.174.01:36:27.92$vck44/vb=7,4 2006.174.01:36:27.92#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.174.01:36:27.92#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.174.01:36:27.92#ibcon#ireg 11 cls_cnt 2 2006.174.01:36:27.92#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.174.01:36:27.98#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.174.01:36:27.98#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.174.01:36:27.98#ibcon#enter wrdev, iclass 14, count 2 2006.174.01:36:27.98#ibcon#first serial, iclass 14, count 2 2006.174.01:36:27.98#ibcon#enter sib2, iclass 14, count 2 2006.174.01:36:27.98#ibcon#flushed, iclass 14, count 2 2006.174.01:36:27.98#ibcon#about to write, iclass 14, count 2 2006.174.01:36:27.98#ibcon#wrote, iclass 14, count 2 2006.174.01:36:27.98#ibcon#about to read 3, iclass 14, count 2 2006.174.01:36:28.00#ibcon#read 3, iclass 14, count 2 2006.174.01:36:28.00#ibcon#about to read 4, iclass 14, count 2 2006.174.01:36:28.00#ibcon#read 4, iclass 14, count 2 2006.174.01:36:28.00#ibcon#about to read 5, iclass 14, count 2 2006.174.01:36:28.00#ibcon#read 5, iclass 14, count 2 2006.174.01:36:28.00#ibcon#about to read 6, iclass 14, count 2 2006.174.01:36:28.00#ibcon#read 6, iclass 14, count 2 2006.174.01:36:28.00#ibcon#end of sib2, iclass 14, count 2 2006.174.01:36:28.00#ibcon#*mode == 0, iclass 14, count 2 2006.174.01:36:28.00#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.174.01:36:28.00#ibcon#[27=AT07-04\r\n] 2006.174.01:36:28.00#ibcon#*before write, iclass 14, count 2 2006.174.01:36:28.00#ibcon#enter sib2, iclass 14, count 2 2006.174.01:36:28.00#ibcon#flushed, iclass 14, count 2 2006.174.01:36:28.00#ibcon#about to write, iclass 14, count 2 2006.174.01:36:28.00#ibcon#wrote, iclass 14, count 2 2006.174.01:36:28.00#ibcon#about to read 3, iclass 14, count 2 2006.174.01:36:28.03#ibcon#read 3, iclass 14, count 2 2006.174.01:36:28.03#ibcon#about to read 4, iclass 14, count 2 2006.174.01:36:28.03#ibcon#read 4, iclass 14, count 2 2006.174.01:36:28.03#ibcon#about to read 5, iclass 14, count 2 2006.174.01:36:28.03#ibcon#read 5, iclass 14, count 2 2006.174.01:36:28.03#ibcon#about to read 6, iclass 14, count 2 2006.174.01:36:28.03#ibcon#read 6, iclass 14, count 2 2006.174.01:36:28.03#ibcon#end of sib2, iclass 14, count 2 2006.174.01:36:28.03#ibcon#*after write, iclass 14, count 2 2006.174.01:36:28.03#ibcon#*before return 0, iclass 14, count 2 2006.174.01:36:28.03#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.174.01:36:28.03#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.174.01:36:28.03#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.174.01:36:28.03#ibcon#ireg 7 cls_cnt 0 2006.174.01:36:28.03#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.174.01:36:28.15#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.174.01:36:28.15#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.174.01:36:28.15#ibcon#enter wrdev, iclass 14, count 0 2006.174.01:36:28.15#ibcon#first serial, iclass 14, count 0 2006.174.01:36:28.15#ibcon#enter sib2, iclass 14, count 0 2006.174.01:36:28.15#ibcon#flushed, iclass 14, count 0 2006.174.01:36:28.15#ibcon#about to write, iclass 14, count 0 2006.174.01:36:28.15#ibcon#wrote, iclass 14, count 0 2006.174.01:36:28.15#ibcon#about to read 3, iclass 14, count 0 2006.174.01:36:28.17#ibcon#read 3, iclass 14, count 0 2006.174.01:36:28.17#ibcon#about to read 4, iclass 14, count 0 2006.174.01:36:28.17#ibcon#read 4, iclass 14, count 0 2006.174.01:36:28.17#ibcon#about to read 5, iclass 14, count 0 2006.174.01:36:28.17#ibcon#read 5, iclass 14, count 0 2006.174.01:36:28.17#ibcon#about to read 6, iclass 14, count 0 2006.174.01:36:28.17#ibcon#read 6, iclass 14, count 0 2006.174.01:36:28.17#ibcon#end of sib2, iclass 14, count 0 2006.174.01:36:28.17#ibcon#*mode == 0, iclass 14, count 0 2006.174.01:36:28.17#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.174.01:36:28.17#ibcon#[27=USB\r\n] 2006.174.01:36:28.17#ibcon#*before write, iclass 14, count 0 2006.174.01:36:28.17#ibcon#enter sib2, iclass 14, count 0 2006.174.01:36:28.17#ibcon#flushed, iclass 14, count 0 2006.174.01:36:28.17#ibcon#about to write, iclass 14, count 0 2006.174.01:36:28.17#ibcon#wrote, iclass 14, count 0 2006.174.01:36:28.17#ibcon#about to read 3, iclass 14, count 0 2006.174.01:36:28.20#ibcon#read 3, iclass 14, count 0 2006.174.01:36:28.20#ibcon#about to read 4, iclass 14, count 0 2006.174.01:36:28.20#ibcon#read 4, iclass 14, count 0 2006.174.01:36:28.20#ibcon#about to read 5, iclass 14, count 0 2006.174.01:36:28.20#ibcon#read 5, iclass 14, count 0 2006.174.01:36:28.20#ibcon#about to read 6, iclass 14, count 0 2006.174.01:36:28.20#ibcon#read 6, iclass 14, count 0 2006.174.01:36:28.20#ibcon#end of sib2, iclass 14, count 0 2006.174.01:36:28.20#ibcon#*after write, iclass 14, count 0 2006.174.01:36:28.20#ibcon#*before return 0, iclass 14, count 0 2006.174.01:36:28.20#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.174.01:36:28.20#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.174.01:36:28.20#ibcon#about to clear, iclass 14 cls_cnt 0 2006.174.01:36:28.20#ibcon#cleared, iclass 14 cls_cnt 0 2006.174.01:36:28.20$vck44/vblo=8,744.99 2006.174.01:36:28.20#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.174.01:36:28.20#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.174.01:36:28.20#ibcon#ireg 17 cls_cnt 0 2006.174.01:36:28.20#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.174.01:36:28.20#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.174.01:36:28.20#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.174.01:36:28.20#ibcon#enter wrdev, iclass 16, count 0 2006.174.01:36:28.20#ibcon#first serial, iclass 16, count 0 2006.174.01:36:28.20#ibcon#enter sib2, iclass 16, count 0 2006.174.01:36:28.21#ibcon#flushed, iclass 16, count 0 2006.174.01:36:28.21#ibcon#about to write, iclass 16, count 0 2006.174.01:36:28.21#ibcon#wrote, iclass 16, count 0 2006.174.01:36:28.21#ibcon#about to read 3, iclass 16, count 0 2006.174.01:36:28.22#ibcon#read 3, iclass 16, count 0 2006.174.01:36:28.22#ibcon#about to read 4, iclass 16, count 0 2006.174.01:36:28.22#ibcon#read 4, iclass 16, count 0 2006.174.01:36:28.22#ibcon#about to read 5, iclass 16, count 0 2006.174.01:36:28.22#ibcon#read 5, iclass 16, count 0 2006.174.01:36:28.22#ibcon#about to read 6, iclass 16, count 0 2006.174.01:36:28.22#ibcon#read 6, iclass 16, count 0 2006.174.01:36:28.22#ibcon#end of sib2, iclass 16, count 0 2006.174.01:36:28.22#ibcon#*mode == 0, iclass 16, count 0 2006.174.01:36:28.22#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.174.01:36:28.22#ibcon#[28=FRQ=08,744.99\r\n] 2006.174.01:36:28.22#ibcon#*before write, iclass 16, count 0 2006.174.01:36:28.22#ibcon#enter sib2, iclass 16, count 0 2006.174.01:36:28.22#ibcon#flushed, iclass 16, count 0 2006.174.01:36:28.22#ibcon#about to write, iclass 16, count 0 2006.174.01:36:28.22#ibcon#wrote, iclass 16, count 0 2006.174.01:36:28.22#ibcon#about to read 3, iclass 16, count 0 2006.174.01:36:28.26#ibcon#read 3, iclass 16, count 0 2006.174.01:36:28.26#ibcon#about to read 4, iclass 16, count 0 2006.174.01:36:28.26#ibcon#read 4, iclass 16, count 0 2006.174.01:36:28.26#ibcon#about to read 5, iclass 16, count 0 2006.174.01:36:28.26#ibcon#read 5, iclass 16, count 0 2006.174.01:36:28.26#ibcon#about to read 6, iclass 16, count 0 2006.174.01:36:28.26#ibcon#read 6, iclass 16, count 0 2006.174.01:36:28.26#ibcon#end of sib2, iclass 16, count 0 2006.174.01:36:28.26#ibcon#*after write, iclass 16, count 0 2006.174.01:36:28.26#ibcon#*before return 0, iclass 16, count 0 2006.174.01:36:28.26#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.174.01:36:28.26#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.174.01:36:28.26#ibcon#about to clear, iclass 16 cls_cnt 0 2006.174.01:36:28.26#ibcon#cleared, iclass 16 cls_cnt 0 2006.174.01:36:28.26$vck44/vb=8,4 2006.174.01:36:28.26#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.174.01:36:28.26#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.174.01:36:28.26#ibcon#ireg 11 cls_cnt 2 2006.174.01:36:28.26#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.174.01:36:28.32#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.174.01:36:28.32#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.174.01:36:28.32#ibcon#enter wrdev, iclass 18, count 2 2006.174.01:36:28.32#ibcon#first serial, iclass 18, count 2 2006.174.01:36:28.32#ibcon#enter sib2, iclass 18, count 2 2006.174.01:36:28.32#ibcon#flushed, iclass 18, count 2 2006.174.01:36:28.32#ibcon#about to write, iclass 18, count 2 2006.174.01:36:28.32#ibcon#wrote, iclass 18, count 2 2006.174.01:36:28.32#ibcon#about to read 3, iclass 18, count 2 2006.174.01:36:28.34#ibcon#read 3, iclass 18, count 2 2006.174.01:36:28.34#ibcon#about to read 4, iclass 18, count 2 2006.174.01:36:28.34#ibcon#read 4, iclass 18, count 2 2006.174.01:36:28.34#ibcon#about to read 5, iclass 18, count 2 2006.174.01:36:28.34#ibcon#read 5, iclass 18, count 2 2006.174.01:36:28.34#ibcon#about to read 6, iclass 18, count 2 2006.174.01:36:28.34#ibcon#read 6, iclass 18, count 2 2006.174.01:36:28.34#ibcon#end of sib2, iclass 18, count 2 2006.174.01:36:28.34#ibcon#*mode == 0, iclass 18, count 2 2006.174.01:36:28.34#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.174.01:36:28.34#ibcon#[27=AT08-04\r\n] 2006.174.01:36:28.34#ibcon#*before write, iclass 18, count 2 2006.174.01:36:28.34#ibcon#enter sib2, iclass 18, count 2 2006.174.01:36:28.34#ibcon#flushed, iclass 18, count 2 2006.174.01:36:28.34#ibcon#about to write, iclass 18, count 2 2006.174.01:36:28.34#ibcon#wrote, iclass 18, count 2 2006.174.01:36:28.34#ibcon#about to read 3, iclass 18, count 2 2006.174.01:36:28.37#ibcon#read 3, iclass 18, count 2 2006.174.01:36:28.37#ibcon#about to read 4, iclass 18, count 2 2006.174.01:36:28.37#ibcon#read 4, iclass 18, count 2 2006.174.01:36:28.37#ibcon#about to read 5, iclass 18, count 2 2006.174.01:36:28.37#ibcon#read 5, iclass 18, count 2 2006.174.01:36:28.37#ibcon#about to read 6, iclass 18, count 2 2006.174.01:36:28.37#ibcon#read 6, iclass 18, count 2 2006.174.01:36:28.37#ibcon#end of sib2, iclass 18, count 2 2006.174.01:36:28.37#ibcon#*after write, iclass 18, count 2 2006.174.01:36:28.37#ibcon#*before return 0, iclass 18, count 2 2006.174.01:36:28.37#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.174.01:36:28.37#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.174.01:36:28.37#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.174.01:36:28.37#ibcon#ireg 7 cls_cnt 0 2006.174.01:36:28.37#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.174.01:36:28.49#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.174.01:36:28.49#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.174.01:36:28.49#ibcon#enter wrdev, iclass 18, count 0 2006.174.01:36:28.49#ibcon#first serial, iclass 18, count 0 2006.174.01:36:28.49#ibcon#enter sib2, iclass 18, count 0 2006.174.01:36:28.49#ibcon#flushed, iclass 18, count 0 2006.174.01:36:28.49#ibcon#about to write, iclass 18, count 0 2006.174.01:36:28.49#ibcon#wrote, iclass 18, count 0 2006.174.01:36:28.49#ibcon#about to read 3, iclass 18, count 0 2006.174.01:36:28.51#ibcon#read 3, iclass 18, count 0 2006.174.01:36:28.51#ibcon#about to read 4, iclass 18, count 0 2006.174.01:36:28.51#ibcon#read 4, iclass 18, count 0 2006.174.01:36:28.51#ibcon#about to read 5, iclass 18, count 0 2006.174.01:36:28.51#ibcon#read 5, iclass 18, count 0 2006.174.01:36:28.51#ibcon#about to read 6, iclass 18, count 0 2006.174.01:36:28.51#ibcon#read 6, iclass 18, count 0 2006.174.01:36:28.51#ibcon#end of sib2, iclass 18, count 0 2006.174.01:36:28.51#ibcon#*mode == 0, iclass 18, count 0 2006.174.01:36:28.51#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.174.01:36:28.51#ibcon#[27=USB\r\n] 2006.174.01:36:28.51#ibcon#*before write, iclass 18, count 0 2006.174.01:36:28.51#ibcon#enter sib2, iclass 18, count 0 2006.174.01:36:28.51#ibcon#flushed, iclass 18, count 0 2006.174.01:36:28.51#ibcon#about to write, iclass 18, count 0 2006.174.01:36:28.51#ibcon#wrote, iclass 18, count 0 2006.174.01:36:28.51#ibcon#about to read 3, iclass 18, count 0 2006.174.01:36:28.54#ibcon#read 3, iclass 18, count 0 2006.174.01:36:28.54#ibcon#about to read 4, iclass 18, count 0 2006.174.01:36:28.54#ibcon#read 4, iclass 18, count 0 2006.174.01:36:28.54#ibcon#about to read 5, iclass 18, count 0 2006.174.01:36:28.54#ibcon#read 5, iclass 18, count 0 2006.174.01:36:28.54#ibcon#about to read 6, iclass 18, count 0 2006.174.01:36:28.54#ibcon#read 6, iclass 18, count 0 2006.174.01:36:28.54#ibcon#end of sib2, iclass 18, count 0 2006.174.01:36:28.54#ibcon#*after write, iclass 18, count 0 2006.174.01:36:28.54#ibcon#*before return 0, iclass 18, count 0 2006.174.01:36:28.54#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.174.01:36:28.54#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.174.01:36:28.54#ibcon#about to clear, iclass 18 cls_cnt 0 2006.174.01:36:28.54#ibcon#cleared, iclass 18 cls_cnt 0 2006.174.01:36:28.54$vck44/vabw=wide 2006.174.01:36:28.54#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.174.01:36:28.54#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.174.01:36:28.54#ibcon#ireg 8 cls_cnt 0 2006.174.01:36:28.54#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.174.01:36:28.54#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.174.01:36:28.54#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.174.01:36:28.54#ibcon#enter wrdev, iclass 20, count 0 2006.174.01:36:28.54#ibcon#first serial, iclass 20, count 0 2006.174.01:36:28.54#ibcon#enter sib2, iclass 20, count 0 2006.174.01:36:28.54#ibcon#flushed, iclass 20, count 0 2006.174.01:36:28.55#ibcon#about to write, iclass 20, count 0 2006.174.01:36:28.55#ibcon#wrote, iclass 20, count 0 2006.174.01:36:28.55#ibcon#about to read 3, iclass 20, count 0 2006.174.01:36:28.56#ibcon#read 3, iclass 20, count 0 2006.174.01:36:28.56#ibcon#about to read 4, iclass 20, count 0 2006.174.01:36:28.56#ibcon#read 4, iclass 20, count 0 2006.174.01:36:28.56#ibcon#about to read 5, iclass 20, count 0 2006.174.01:36:28.56#ibcon#read 5, iclass 20, count 0 2006.174.01:36:28.56#ibcon#about to read 6, iclass 20, count 0 2006.174.01:36:28.56#ibcon#read 6, iclass 20, count 0 2006.174.01:36:28.56#ibcon#end of sib2, iclass 20, count 0 2006.174.01:36:28.56#ibcon#*mode == 0, iclass 20, count 0 2006.174.01:36:28.56#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.174.01:36:28.56#ibcon#[25=BW32\r\n] 2006.174.01:36:28.56#ibcon#*before write, iclass 20, count 0 2006.174.01:36:28.56#ibcon#enter sib2, iclass 20, count 0 2006.174.01:36:28.56#ibcon#flushed, iclass 20, count 0 2006.174.01:36:28.56#ibcon#about to write, iclass 20, count 0 2006.174.01:36:28.56#ibcon#wrote, iclass 20, count 0 2006.174.01:36:28.56#ibcon#about to read 3, iclass 20, count 0 2006.174.01:36:28.59#ibcon#read 3, iclass 20, count 0 2006.174.01:36:28.59#ibcon#about to read 4, iclass 20, count 0 2006.174.01:36:28.59#ibcon#read 4, iclass 20, count 0 2006.174.01:36:28.59#ibcon#about to read 5, iclass 20, count 0 2006.174.01:36:28.59#ibcon#read 5, iclass 20, count 0 2006.174.01:36:28.59#ibcon#about to read 6, iclass 20, count 0 2006.174.01:36:28.59#ibcon#read 6, iclass 20, count 0 2006.174.01:36:28.59#ibcon#end of sib2, iclass 20, count 0 2006.174.01:36:28.59#ibcon#*after write, iclass 20, count 0 2006.174.01:36:28.59#ibcon#*before return 0, iclass 20, count 0 2006.174.01:36:28.59#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.174.01:36:28.59#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.174.01:36:28.59#ibcon#about to clear, iclass 20 cls_cnt 0 2006.174.01:36:28.59#ibcon#cleared, iclass 20 cls_cnt 0 2006.174.01:36:28.59$vck44/vbbw=wide 2006.174.01:36:28.59#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.174.01:36:28.59#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.174.01:36:28.59#ibcon#ireg 8 cls_cnt 0 2006.174.01:36:28.59#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.174.01:36:28.66#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.174.01:36:28.66#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.174.01:36:28.66#ibcon#enter wrdev, iclass 22, count 0 2006.174.01:36:28.66#ibcon#first serial, iclass 22, count 0 2006.174.01:36:28.66#ibcon#enter sib2, iclass 22, count 0 2006.174.01:36:28.66#ibcon#flushed, iclass 22, count 0 2006.174.01:36:28.66#ibcon#about to write, iclass 22, count 0 2006.174.01:36:28.66#ibcon#wrote, iclass 22, count 0 2006.174.01:36:28.66#ibcon#about to read 3, iclass 22, count 0 2006.174.01:36:28.68#ibcon#read 3, iclass 22, count 0 2006.174.01:36:28.68#ibcon#about to read 4, iclass 22, count 0 2006.174.01:36:28.68#ibcon#read 4, iclass 22, count 0 2006.174.01:36:28.68#ibcon#about to read 5, iclass 22, count 0 2006.174.01:36:28.68#ibcon#read 5, iclass 22, count 0 2006.174.01:36:28.68#ibcon#about to read 6, iclass 22, count 0 2006.174.01:36:28.68#ibcon#read 6, iclass 22, count 0 2006.174.01:36:28.68#ibcon#end of sib2, iclass 22, count 0 2006.174.01:36:28.68#ibcon#*mode == 0, iclass 22, count 0 2006.174.01:36:28.68#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.174.01:36:28.68#ibcon#[27=BW32\r\n] 2006.174.01:36:28.68#ibcon#*before write, iclass 22, count 0 2006.174.01:36:28.68#ibcon#enter sib2, iclass 22, count 0 2006.174.01:36:28.68#ibcon#flushed, iclass 22, count 0 2006.174.01:36:28.68#ibcon#about to write, iclass 22, count 0 2006.174.01:36:28.68#ibcon#wrote, iclass 22, count 0 2006.174.01:36:28.68#ibcon#about to read 3, iclass 22, count 0 2006.174.01:36:28.71#ibcon#read 3, iclass 22, count 0 2006.174.01:36:28.71#ibcon#about to read 4, iclass 22, count 0 2006.174.01:36:28.71#ibcon#read 4, iclass 22, count 0 2006.174.01:36:28.71#ibcon#about to read 5, iclass 22, count 0 2006.174.01:36:28.71#ibcon#read 5, iclass 22, count 0 2006.174.01:36:28.71#ibcon#about to read 6, iclass 22, count 0 2006.174.01:36:28.71#ibcon#read 6, iclass 22, count 0 2006.174.01:36:28.71#ibcon#end of sib2, iclass 22, count 0 2006.174.01:36:28.71#ibcon#*after write, iclass 22, count 0 2006.174.01:36:28.71#ibcon#*before return 0, iclass 22, count 0 2006.174.01:36:28.71#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.174.01:36:28.71#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.174.01:36:28.71#ibcon#about to clear, iclass 22 cls_cnt 0 2006.174.01:36:28.71#ibcon#cleared, iclass 22 cls_cnt 0 2006.174.01:36:28.71$setupk4/ifdk4 2006.174.01:36:28.72$ifdk4/lo= 2006.174.01:36:28.72$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.174.01:36:28.72$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.174.01:36:28.72$ifdk4/patch= 2006.174.01:36:28.72$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.174.01:36:28.72$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.174.01:36:28.72$setupk4/!*+20s 2006.174.01:36:35.92#abcon#<5=/09 0.8 2.7 26.04 771003.3\r\n> 2006.174.01:36:35.94#abcon#{5=INTERFACE CLEAR} 2006.174.01:36:36.00#abcon#[5=S1D000X0/0*\r\n] 2006.174.01:36:41.14#trakl#Source acquired 2006.174.01:36:42.14#flagr#flagr/antenna,acquired 2006.174.01:36:43.26$setupk4/"tpicd 2006.174.01:36:43.26$setupk4/echo=off 2006.174.01:36:43.26$setupk4/xlog=off 2006.174.01:36:43.26:!2006.174.01:36:58 2006.174.01:36:58.00:preob 2006.174.01:36:58.14/onsource/TRACKING 2006.174.01:36:58.15:!2006.174.01:37:08 2006.174.01:37:08.01:"tape 2006.174.01:37:08.01:"st=record 2006.174.01:37:08.01:data_valid=on 2006.174.01:37:08.02:midob 2006.174.01:37:09.14/onsource/TRACKING 2006.174.01:37:09.15/wx/26.07,1003.3,77 2006.174.01:37:09.32/cable/+6.5011E-03 2006.174.01:37:10.41/va/01,07,usb,yes,35,37 2006.174.01:37:10.41/va/02,06,usb,yes,34,35 2006.174.01:37:10.41/va/03,05,usb,yes,44,46 2006.174.01:37:10.41/va/04,06,usb,yes,35,37 2006.174.01:37:10.41/va/05,04,usb,yes,27,28 2006.174.01:37:10.41/va/06,03,usb,yes,39,38 2006.174.01:37:10.41/va/07,04,usb,yes,31,32 2006.174.01:37:10.41/va/08,04,usb,yes,26,32 2006.174.01:37:10.64/valo/01,524.99,yes,locked 2006.174.01:37:10.64/valo/02,534.99,yes,locked 2006.174.01:37:10.64/valo/03,564.99,yes,locked 2006.174.01:37:10.64/valo/04,624.99,yes,locked 2006.174.01:37:10.64/valo/05,734.99,yes,locked 2006.174.01:37:10.64/valo/06,814.99,yes,locked 2006.174.01:37:10.64/valo/07,864.99,yes,locked 2006.174.01:37:10.64/valo/08,884.99,yes,locked 2006.174.01:37:11.73/vb/01,04,usb,yes,29,27 2006.174.01:37:11.73/vb/02,04,usb,yes,31,31 2006.174.01:37:11.73/vb/03,04,usb,yes,28,31 2006.174.01:37:11.73/vb/04,04,usb,yes,33,32 2006.174.01:37:11.73/vb/05,04,usb,yes,25,28 2006.174.01:37:11.73/vb/06,04,usb,yes,30,26 2006.174.01:37:11.73/vb/07,04,usb,yes,30,29 2006.174.01:37:11.73/vb/08,04,usb,yes,27,30 2006.174.01:37:11.96/vblo/01,629.99,yes,locked 2006.174.01:37:11.96/vblo/02,634.99,yes,locked 2006.174.01:37:11.96/vblo/03,649.99,yes,locked 2006.174.01:37:11.96/vblo/04,679.99,yes,locked 2006.174.01:37:11.96/vblo/05,709.99,yes,locked 2006.174.01:37:11.96/vblo/06,719.99,yes,locked 2006.174.01:37:11.96/vblo/07,734.99,yes,locked 2006.174.01:37:11.96/vblo/08,744.99,yes,locked 2006.174.01:37:12.11/vabw/8 2006.174.01:37:12.26/vbbw/8 2006.174.01:37:12.35/xfe/off,on,14.5 2006.174.01:37:12.74/ifatt/23,28,28,28 2006.174.01:37:13.07/fmout-gps/S +3.77E-07 2006.174.01:37:13.12:!2006.174.01:40:48 2006.174.01:40:48.01:data_valid=off 2006.174.01:40:48.01:"et 2006.174.01:40:48.01:!+3s 2006.174.01:40:51.02:"tape 2006.174.01:40:51.02:postob 2006.174.01:40:51.08/cable/+6.5005E-03 2006.174.01:40:51.08/wx/26.14,1003.3,71 2006.174.01:40:51.14/fmout-gps/S +3.77E-07 2006.174.01:40:51.14:scan_name=174-0141,jd0606,784 2006.174.01:40:51.14:source=1418+546,141946.60,542314.8,2000.0,cw 2006.174.01:40:53.14#flagr#flagr/antenna,new-source 2006.174.01:40:53.14:checkk5 2006.174.01:40:53.56/chk_autoobs//k5ts1/ autoobs is running! 2006.174.01:40:53.95/chk_autoobs//k5ts2/ autoobs is running! 2006.174.01:40:54.36/chk_autoobs//k5ts3/ autoobs is running! 2006.174.01:40:54.75/chk_autoobs//k5ts4/ autoobs is running! 2006.174.01:40:55.15/chk_obsdata//k5ts1/T1740137??a.dat file size is correct (nominal:880MB, actual:876MB). 2006.174.01:40:55.55/chk_obsdata//k5ts2/T1740137??b.dat file size is correct (nominal:880MB, actual:876MB). 2006.174.01:40:55.96/chk_obsdata//k5ts3/T1740137??c.dat file size is correct (nominal:880MB, actual:876MB). 2006.174.01:40:56.37/chk_obsdata//k5ts4/T1740137??d.dat file size is correct (nominal:880MB, actual:876MB). 2006.174.01:40:57.08/k5log//k5ts1_log_newline 2006.174.01:40:57.78/k5log//k5ts2_log_newline 2006.174.01:40:58.50/k5log//k5ts3_log_newline 2006.174.01:40:59.21/k5log//k5ts4_log_newline 2006.174.01:40:59.24/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.174.01:40:59.24:setupk4=1 2006.174.01:40:59.24$setupk4/echo=on 2006.174.01:40:59.24$setupk4/pcalon 2006.174.01:40:59.24$pcalon/"no phase cal control is implemented here 2006.174.01:40:59.24$setupk4/"tpicd=stop 2006.174.01:40:59.24$setupk4/"rec=synch_on 2006.174.01:40:59.24$setupk4/"rec_mode=128 2006.174.01:40:59.24$setupk4/!* 2006.174.01:40:59.24$setupk4/recpk4 2006.174.01:40:59.24$recpk4/recpatch= 2006.174.01:40:59.24$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.174.01:40:59.24$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.174.01:40:59.24$setupk4/vck44 2006.174.01:40:59.24$vck44/valo=1,524.99 2006.174.01:40:59.24#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.174.01:40:59.24#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.174.01:40:59.24#ibcon#ireg 17 cls_cnt 0 2006.174.01:40:59.24#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.174.01:40:59.24#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.174.01:40:59.24#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.174.01:40:59.24#ibcon#enter wrdev, iclass 23, count 0 2006.174.01:40:59.24#ibcon#first serial, iclass 23, count 0 2006.174.01:40:59.24#ibcon#enter sib2, iclass 23, count 0 2006.174.01:40:59.24#ibcon#flushed, iclass 23, count 0 2006.174.01:40:59.24#ibcon#about to write, iclass 23, count 0 2006.174.01:40:59.24#ibcon#wrote, iclass 23, count 0 2006.174.01:40:59.24#ibcon#about to read 3, iclass 23, count 0 2006.174.01:40:59.25#ibcon#read 3, iclass 23, count 0 2006.174.01:40:59.25#ibcon#about to read 4, iclass 23, count 0 2006.174.01:40:59.25#ibcon#read 4, iclass 23, count 0 2006.174.01:40:59.25#ibcon#about to read 5, iclass 23, count 0 2006.174.01:40:59.25#ibcon#read 5, iclass 23, count 0 2006.174.01:40:59.25#ibcon#about to read 6, iclass 23, count 0 2006.174.01:40:59.25#ibcon#read 6, iclass 23, count 0 2006.174.01:40:59.25#ibcon#end of sib2, iclass 23, count 0 2006.174.01:40:59.25#ibcon#*mode == 0, iclass 23, count 0 2006.174.01:40:59.25#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.174.01:40:59.25#ibcon#[26=FRQ=01,524.99\r\n] 2006.174.01:40:59.25#ibcon#*before write, iclass 23, count 0 2006.174.01:40:59.25#ibcon#enter sib2, iclass 23, count 0 2006.174.01:40:59.25#ibcon#flushed, iclass 23, count 0 2006.174.01:40:59.25#ibcon#about to write, iclass 23, count 0 2006.174.01:40:59.25#ibcon#wrote, iclass 23, count 0 2006.174.01:40:59.25#ibcon#about to read 3, iclass 23, count 0 2006.174.01:40:59.30#ibcon#read 3, iclass 23, count 0 2006.174.01:40:59.30#ibcon#about to read 4, iclass 23, count 0 2006.174.01:40:59.30#ibcon#read 4, iclass 23, count 0 2006.174.01:40:59.30#ibcon#about to read 5, iclass 23, count 0 2006.174.01:40:59.30#ibcon#read 5, iclass 23, count 0 2006.174.01:40:59.30#ibcon#about to read 6, iclass 23, count 0 2006.174.01:40:59.30#ibcon#read 6, iclass 23, count 0 2006.174.01:40:59.30#ibcon#end of sib2, iclass 23, count 0 2006.174.01:40:59.30#ibcon#*after write, iclass 23, count 0 2006.174.01:40:59.30#ibcon#*before return 0, iclass 23, count 0 2006.174.01:40:59.30#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.174.01:40:59.30#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.174.01:40:59.30#ibcon#about to clear, iclass 23 cls_cnt 0 2006.174.01:40:59.30#ibcon#cleared, iclass 23 cls_cnt 0 2006.174.01:40:59.30$vck44/va=1,7 2006.174.01:40:59.30#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.174.01:40:59.30#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.174.01:40:59.30#ibcon#ireg 11 cls_cnt 2 2006.174.01:40:59.30#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.174.01:40:59.30#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.174.01:40:59.30#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.174.01:40:59.30#ibcon#enter wrdev, iclass 25, count 2 2006.174.01:40:59.30#ibcon#first serial, iclass 25, count 2 2006.174.01:40:59.30#ibcon#enter sib2, iclass 25, count 2 2006.174.01:40:59.30#ibcon#flushed, iclass 25, count 2 2006.174.01:40:59.30#ibcon#about to write, iclass 25, count 2 2006.174.01:40:59.30#ibcon#wrote, iclass 25, count 2 2006.174.01:40:59.30#ibcon#about to read 3, iclass 25, count 2 2006.174.01:40:59.32#ibcon#read 3, iclass 25, count 2 2006.174.01:40:59.32#ibcon#about to read 4, iclass 25, count 2 2006.174.01:40:59.32#ibcon#read 4, iclass 25, count 2 2006.174.01:40:59.32#ibcon#about to read 5, iclass 25, count 2 2006.174.01:40:59.32#ibcon#read 5, iclass 25, count 2 2006.174.01:40:59.32#ibcon#about to read 6, iclass 25, count 2 2006.174.01:40:59.32#ibcon#read 6, iclass 25, count 2 2006.174.01:40:59.32#ibcon#end of sib2, iclass 25, count 2 2006.174.01:40:59.32#ibcon#*mode == 0, iclass 25, count 2 2006.174.01:40:59.32#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.174.01:40:59.32#ibcon#[25=AT01-07\r\n] 2006.174.01:40:59.32#ibcon#*before write, iclass 25, count 2 2006.174.01:40:59.32#ibcon#enter sib2, iclass 25, count 2 2006.174.01:40:59.32#ibcon#flushed, iclass 25, count 2 2006.174.01:40:59.32#ibcon#about to write, iclass 25, count 2 2006.174.01:40:59.32#ibcon#wrote, iclass 25, count 2 2006.174.01:40:59.32#ibcon#about to read 3, iclass 25, count 2 2006.174.01:40:59.35#ibcon#read 3, iclass 25, count 2 2006.174.01:40:59.35#ibcon#about to read 4, iclass 25, count 2 2006.174.01:40:59.35#ibcon#read 4, iclass 25, count 2 2006.174.01:40:59.35#ibcon#about to read 5, iclass 25, count 2 2006.174.01:40:59.35#ibcon#read 5, iclass 25, count 2 2006.174.01:40:59.35#ibcon#about to read 6, iclass 25, count 2 2006.174.01:40:59.35#ibcon#read 6, iclass 25, count 2 2006.174.01:40:59.35#ibcon#end of sib2, iclass 25, count 2 2006.174.01:40:59.35#ibcon#*after write, iclass 25, count 2 2006.174.01:40:59.35#ibcon#*before return 0, iclass 25, count 2 2006.174.01:40:59.35#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.174.01:40:59.35#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.174.01:40:59.35#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.174.01:40:59.35#ibcon#ireg 7 cls_cnt 0 2006.174.01:40:59.35#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.174.01:40:59.47#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.174.01:40:59.47#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.174.01:40:59.47#ibcon#enter wrdev, iclass 25, count 0 2006.174.01:40:59.47#ibcon#first serial, iclass 25, count 0 2006.174.01:40:59.47#ibcon#enter sib2, iclass 25, count 0 2006.174.01:40:59.47#ibcon#flushed, iclass 25, count 0 2006.174.01:40:59.47#ibcon#about to write, iclass 25, count 0 2006.174.01:40:59.47#ibcon#wrote, iclass 25, count 0 2006.174.01:40:59.47#ibcon#about to read 3, iclass 25, count 0 2006.174.01:40:59.49#ibcon#read 3, iclass 25, count 0 2006.174.01:40:59.49#ibcon#about to read 4, iclass 25, count 0 2006.174.01:40:59.49#ibcon#read 4, iclass 25, count 0 2006.174.01:40:59.49#ibcon#about to read 5, iclass 25, count 0 2006.174.01:40:59.49#ibcon#read 5, iclass 25, count 0 2006.174.01:40:59.49#ibcon#about to read 6, iclass 25, count 0 2006.174.01:40:59.49#ibcon#read 6, iclass 25, count 0 2006.174.01:40:59.49#ibcon#end of sib2, iclass 25, count 0 2006.174.01:40:59.49#ibcon#*mode == 0, iclass 25, count 0 2006.174.01:40:59.49#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.174.01:40:59.49#ibcon#[25=USB\r\n] 2006.174.01:40:59.49#ibcon#*before write, iclass 25, count 0 2006.174.01:40:59.49#ibcon#enter sib2, iclass 25, count 0 2006.174.01:40:59.49#ibcon#flushed, iclass 25, count 0 2006.174.01:40:59.49#ibcon#about to write, iclass 25, count 0 2006.174.01:40:59.49#ibcon#wrote, iclass 25, count 0 2006.174.01:40:59.49#ibcon#about to read 3, iclass 25, count 0 2006.174.01:40:59.52#ibcon#read 3, iclass 25, count 0 2006.174.01:40:59.52#ibcon#about to read 4, iclass 25, count 0 2006.174.01:40:59.52#ibcon#read 4, iclass 25, count 0 2006.174.01:40:59.52#ibcon#about to read 5, iclass 25, count 0 2006.174.01:40:59.52#ibcon#read 5, iclass 25, count 0 2006.174.01:40:59.52#ibcon#about to read 6, iclass 25, count 0 2006.174.01:40:59.52#ibcon#read 6, iclass 25, count 0 2006.174.01:40:59.52#ibcon#end of sib2, iclass 25, count 0 2006.174.01:40:59.52#ibcon#*after write, iclass 25, count 0 2006.174.01:40:59.52#ibcon#*before return 0, iclass 25, count 0 2006.174.01:40:59.52#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.174.01:40:59.52#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.174.01:40:59.52#ibcon#about to clear, iclass 25 cls_cnt 0 2006.174.01:40:59.52#ibcon#cleared, iclass 25 cls_cnt 0 2006.174.01:40:59.52$vck44/valo=2,534.99 2006.174.01:40:59.52#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.174.01:40:59.52#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.174.01:40:59.52#ibcon#ireg 17 cls_cnt 0 2006.174.01:40:59.52#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.174.01:40:59.52#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.174.01:40:59.52#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.174.01:40:59.52#ibcon#enter wrdev, iclass 27, count 0 2006.174.01:40:59.52#ibcon#first serial, iclass 27, count 0 2006.174.01:40:59.52#ibcon#enter sib2, iclass 27, count 0 2006.174.01:40:59.52#ibcon#flushed, iclass 27, count 0 2006.174.01:40:59.52#ibcon#about to write, iclass 27, count 0 2006.174.01:40:59.52#ibcon#wrote, iclass 27, count 0 2006.174.01:40:59.52#ibcon#about to read 3, iclass 27, count 0 2006.174.01:40:59.54#ibcon#read 3, iclass 27, count 0 2006.174.01:40:59.54#ibcon#about to read 4, iclass 27, count 0 2006.174.01:40:59.54#ibcon#read 4, iclass 27, count 0 2006.174.01:40:59.54#ibcon#about to read 5, iclass 27, count 0 2006.174.01:40:59.54#ibcon#read 5, iclass 27, count 0 2006.174.01:40:59.54#ibcon#about to read 6, iclass 27, count 0 2006.174.01:40:59.54#ibcon#read 6, iclass 27, count 0 2006.174.01:40:59.54#ibcon#end of sib2, iclass 27, count 0 2006.174.01:40:59.54#ibcon#*mode == 0, iclass 27, count 0 2006.174.01:40:59.54#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.174.01:40:59.54#ibcon#[26=FRQ=02,534.99\r\n] 2006.174.01:40:59.54#ibcon#*before write, iclass 27, count 0 2006.174.01:40:59.54#ibcon#enter sib2, iclass 27, count 0 2006.174.01:40:59.54#ibcon#flushed, iclass 27, count 0 2006.174.01:40:59.54#ibcon#about to write, iclass 27, count 0 2006.174.01:40:59.54#ibcon#wrote, iclass 27, count 0 2006.174.01:40:59.54#ibcon#about to read 3, iclass 27, count 0 2006.174.01:40:59.58#ibcon#read 3, iclass 27, count 0 2006.174.01:40:59.58#ibcon#about to read 4, iclass 27, count 0 2006.174.01:40:59.58#ibcon#read 4, iclass 27, count 0 2006.174.01:40:59.58#ibcon#about to read 5, iclass 27, count 0 2006.174.01:40:59.58#ibcon#read 5, iclass 27, count 0 2006.174.01:40:59.58#ibcon#about to read 6, iclass 27, count 0 2006.174.01:40:59.58#ibcon#read 6, iclass 27, count 0 2006.174.01:40:59.58#ibcon#end of sib2, iclass 27, count 0 2006.174.01:40:59.58#ibcon#*after write, iclass 27, count 0 2006.174.01:40:59.58#ibcon#*before return 0, iclass 27, count 0 2006.174.01:40:59.58#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.174.01:40:59.58#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.174.01:40:59.58#ibcon#about to clear, iclass 27 cls_cnt 0 2006.174.01:40:59.58#ibcon#cleared, iclass 27 cls_cnt 0 2006.174.01:40:59.58$vck44/va=2,6 2006.174.01:40:59.58#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.174.01:40:59.58#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.174.01:40:59.58#ibcon#ireg 11 cls_cnt 2 2006.174.01:40:59.58#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.174.01:40:59.64#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.174.01:40:59.64#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.174.01:40:59.64#ibcon#enter wrdev, iclass 29, count 2 2006.174.01:40:59.64#ibcon#first serial, iclass 29, count 2 2006.174.01:40:59.64#ibcon#enter sib2, iclass 29, count 2 2006.174.01:40:59.64#ibcon#flushed, iclass 29, count 2 2006.174.01:40:59.64#ibcon#about to write, iclass 29, count 2 2006.174.01:40:59.64#ibcon#wrote, iclass 29, count 2 2006.174.01:40:59.64#ibcon#about to read 3, iclass 29, count 2 2006.174.01:40:59.66#ibcon#read 3, iclass 29, count 2 2006.174.01:40:59.66#ibcon#about to read 4, iclass 29, count 2 2006.174.01:40:59.66#ibcon#read 4, iclass 29, count 2 2006.174.01:40:59.66#ibcon#about to read 5, iclass 29, count 2 2006.174.01:40:59.66#ibcon#read 5, iclass 29, count 2 2006.174.01:40:59.66#ibcon#about to read 6, iclass 29, count 2 2006.174.01:40:59.66#ibcon#read 6, iclass 29, count 2 2006.174.01:40:59.66#ibcon#end of sib2, iclass 29, count 2 2006.174.01:40:59.66#ibcon#*mode == 0, iclass 29, count 2 2006.174.01:40:59.66#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.174.01:40:59.66#ibcon#[25=AT02-06\r\n] 2006.174.01:40:59.66#ibcon#*before write, iclass 29, count 2 2006.174.01:40:59.66#ibcon#enter sib2, iclass 29, count 2 2006.174.01:40:59.66#ibcon#flushed, iclass 29, count 2 2006.174.01:40:59.66#ibcon#about to write, iclass 29, count 2 2006.174.01:40:59.66#ibcon#wrote, iclass 29, count 2 2006.174.01:40:59.66#ibcon#about to read 3, iclass 29, count 2 2006.174.01:40:59.69#ibcon#read 3, iclass 29, count 2 2006.174.01:40:59.69#ibcon#about to read 4, iclass 29, count 2 2006.174.01:40:59.69#ibcon#read 4, iclass 29, count 2 2006.174.01:40:59.69#ibcon#about to read 5, iclass 29, count 2 2006.174.01:40:59.69#ibcon#read 5, iclass 29, count 2 2006.174.01:40:59.69#ibcon#about to read 6, iclass 29, count 2 2006.174.01:40:59.69#ibcon#read 6, iclass 29, count 2 2006.174.01:40:59.69#ibcon#end of sib2, iclass 29, count 2 2006.174.01:40:59.69#ibcon#*after write, iclass 29, count 2 2006.174.01:40:59.69#ibcon#*before return 0, iclass 29, count 2 2006.174.01:40:59.69#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.174.01:40:59.69#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.174.01:40:59.69#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.174.01:40:59.69#ibcon#ireg 7 cls_cnt 0 2006.174.01:40:59.69#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.174.01:40:59.81#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.174.01:40:59.81#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.174.01:40:59.81#ibcon#enter wrdev, iclass 29, count 0 2006.174.01:40:59.81#ibcon#first serial, iclass 29, count 0 2006.174.01:40:59.81#ibcon#enter sib2, iclass 29, count 0 2006.174.01:40:59.81#ibcon#flushed, iclass 29, count 0 2006.174.01:40:59.81#ibcon#about to write, iclass 29, count 0 2006.174.01:40:59.81#ibcon#wrote, iclass 29, count 0 2006.174.01:40:59.81#ibcon#about to read 3, iclass 29, count 0 2006.174.01:40:59.83#ibcon#read 3, iclass 29, count 0 2006.174.01:40:59.83#ibcon#about to read 4, iclass 29, count 0 2006.174.01:40:59.83#ibcon#read 4, iclass 29, count 0 2006.174.01:40:59.83#ibcon#about to read 5, iclass 29, count 0 2006.174.01:40:59.83#ibcon#read 5, iclass 29, count 0 2006.174.01:40:59.83#ibcon#about to read 6, iclass 29, count 0 2006.174.01:40:59.83#ibcon#read 6, iclass 29, count 0 2006.174.01:40:59.83#ibcon#end of sib2, iclass 29, count 0 2006.174.01:40:59.83#ibcon#*mode == 0, iclass 29, count 0 2006.174.01:40:59.83#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.174.01:40:59.83#ibcon#[25=USB\r\n] 2006.174.01:40:59.83#ibcon#*before write, iclass 29, count 0 2006.174.01:40:59.83#ibcon#enter sib2, iclass 29, count 0 2006.174.01:40:59.83#ibcon#flushed, iclass 29, count 0 2006.174.01:40:59.83#ibcon#about to write, iclass 29, count 0 2006.174.01:40:59.83#ibcon#wrote, iclass 29, count 0 2006.174.01:40:59.83#ibcon#about to read 3, iclass 29, count 0 2006.174.01:40:59.86#ibcon#read 3, iclass 29, count 0 2006.174.01:40:59.86#ibcon#about to read 4, iclass 29, count 0 2006.174.01:40:59.86#ibcon#read 4, iclass 29, count 0 2006.174.01:40:59.86#ibcon#about to read 5, iclass 29, count 0 2006.174.01:40:59.86#ibcon#read 5, iclass 29, count 0 2006.174.01:40:59.86#ibcon#about to read 6, iclass 29, count 0 2006.174.01:40:59.86#ibcon#read 6, iclass 29, count 0 2006.174.01:40:59.86#ibcon#end of sib2, iclass 29, count 0 2006.174.01:40:59.86#ibcon#*after write, iclass 29, count 0 2006.174.01:40:59.86#ibcon#*before return 0, iclass 29, count 0 2006.174.01:40:59.86#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.174.01:40:59.86#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.174.01:40:59.86#ibcon#about to clear, iclass 29 cls_cnt 0 2006.174.01:40:59.86#ibcon#cleared, iclass 29 cls_cnt 0 2006.174.01:40:59.86$vck44/valo=3,564.99 2006.174.01:40:59.86#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.174.01:40:59.86#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.174.01:40:59.86#ibcon#ireg 17 cls_cnt 0 2006.174.01:40:59.86#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.174.01:40:59.86#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.174.01:40:59.86#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.174.01:40:59.86#ibcon#enter wrdev, iclass 31, count 0 2006.174.01:40:59.86#ibcon#first serial, iclass 31, count 0 2006.174.01:40:59.86#ibcon#enter sib2, iclass 31, count 0 2006.174.01:40:59.86#ibcon#flushed, iclass 31, count 0 2006.174.01:40:59.86#ibcon#about to write, iclass 31, count 0 2006.174.01:40:59.86#ibcon#wrote, iclass 31, count 0 2006.174.01:40:59.86#ibcon#about to read 3, iclass 31, count 0 2006.174.01:40:59.88#ibcon#read 3, iclass 31, count 0 2006.174.01:40:59.88#ibcon#about to read 4, iclass 31, count 0 2006.174.01:40:59.88#ibcon#read 4, iclass 31, count 0 2006.174.01:40:59.88#ibcon#about to read 5, iclass 31, count 0 2006.174.01:40:59.88#ibcon#read 5, iclass 31, count 0 2006.174.01:40:59.88#ibcon#about to read 6, iclass 31, count 0 2006.174.01:40:59.88#ibcon#read 6, iclass 31, count 0 2006.174.01:40:59.88#ibcon#end of sib2, iclass 31, count 0 2006.174.01:40:59.88#ibcon#*mode == 0, iclass 31, count 0 2006.174.01:40:59.88#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.174.01:40:59.88#ibcon#[26=FRQ=03,564.99\r\n] 2006.174.01:40:59.88#ibcon#*before write, iclass 31, count 0 2006.174.01:40:59.88#ibcon#enter sib2, iclass 31, count 0 2006.174.01:40:59.88#ibcon#flushed, iclass 31, count 0 2006.174.01:40:59.88#ibcon#about to write, iclass 31, count 0 2006.174.01:40:59.88#ibcon#wrote, iclass 31, count 0 2006.174.01:40:59.88#ibcon#about to read 3, iclass 31, count 0 2006.174.01:40:59.92#ibcon#read 3, iclass 31, count 0 2006.174.01:40:59.92#ibcon#about to read 4, iclass 31, count 0 2006.174.01:40:59.92#ibcon#read 4, iclass 31, count 0 2006.174.01:40:59.92#ibcon#about to read 5, iclass 31, count 0 2006.174.01:40:59.92#ibcon#read 5, iclass 31, count 0 2006.174.01:40:59.92#ibcon#about to read 6, iclass 31, count 0 2006.174.01:40:59.92#ibcon#read 6, iclass 31, count 0 2006.174.01:40:59.92#ibcon#end of sib2, iclass 31, count 0 2006.174.01:40:59.92#ibcon#*after write, iclass 31, count 0 2006.174.01:40:59.92#ibcon#*before return 0, iclass 31, count 0 2006.174.01:40:59.92#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.174.01:40:59.92#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.174.01:40:59.92#ibcon#about to clear, iclass 31 cls_cnt 0 2006.174.01:40:59.92#ibcon#cleared, iclass 31 cls_cnt 0 2006.174.01:40:59.92$vck44/va=3,5 2006.174.01:40:59.92#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.174.01:40:59.92#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.174.01:40:59.92#ibcon#ireg 11 cls_cnt 2 2006.174.01:40:59.92#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.174.01:40:59.98#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.174.01:40:59.98#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.174.01:40:59.98#ibcon#enter wrdev, iclass 33, count 2 2006.174.01:40:59.98#ibcon#first serial, iclass 33, count 2 2006.174.01:40:59.98#ibcon#enter sib2, iclass 33, count 2 2006.174.01:40:59.98#ibcon#flushed, iclass 33, count 2 2006.174.01:40:59.98#ibcon#about to write, iclass 33, count 2 2006.174.01:40:59.98#ibcon#wrote, iclass 33, count 2 2006.174.01:40:59.98#ibcon#about to read 3, iclass 33, count 2 2006.174.01:41:00.00#ibcon#read 3, iclass 33, count 2 2006.174.01:41:00.00#ibcon#about to read 4, iclass 33, count 2 2006.174.01:41:00.00#ibcon#read 4, iclass 33, count 2 2006.174.01:41:00.00#ibcon#about to read 5, iclass 33, count 2 2006.174.01:41:00.00#ibcon#read 5, iclass 33, count 2 2006.174.01:41:00.00#ibcon#about to read 6, iclass 33, count 2 2006.174.01:41:00.00#ibcon#read 6, iclass 33, count 2 2006.174.01:41:00.00#ibcon#end of sib2, iclass 33, count 2 2006.174.01:41:00.00#ibcon#*mode == 0, iclass 33, count 2 2006.174.01:41:00.00#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.174.01:41:00.00#ibcon#[25=AT03-05\r\n] 2006.174.01:41:00.00#ibcon#*before write, iclass 33, count 2 2006.174.01:41:00.00#ibcon#enter sib2, iclass 33, count 2 2006.174.01:41:00.00#ibcon#flushed, iclass 33, count 2 2006.174.01:41:00.00#ibcon#about to write, iclass 33, count 2 2006.174.01:41:00.00#ibcon#wrote, iclass 33, count 2 2006.174.01:41:00.00#ibcon#about to read 3, iclass 33, count 2 2006.174.01:41:00.03#ibcon#read 3, iclass 33, count 2 2006.174.01:41:00.03#ibcon#about to read 4, iclass 33, count 2 2006.174.01:41:00.03#ibcon#read 4, iclass 33, count 2 2006.174.01:41:00.03#ibcon#about to read 5, iclass 33, count 2 2006.174.01:41:00.03#ibcon#read 5, iclass 33, count 2 2006.174.01:41:00.03#ibcon#about to read 6, iclass 33, count 2 2006.174.01:41:00.03#ibcon#read 6, iclass 33, count 2 2006.174.01:41:00.03#ibcon#end of sib2, iclass 33, count 2 2006.174.01:41:00.03#ibcon#*after write, iclass 33, count 2 2006.174.01:41:00.03#ibcon#*before return 0, iclass 33, count 2 2006.174.01:41:00.03#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.174.01:41:00.03#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.174.01:41:00.03#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.174.01:41:00.03#ibcon#ireg 7 cls_cnt 0 2006.174.01:41:00.03#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.174.01:41:00.15#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.174.01:41:00.15#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.174.01:41:00.15#ibcon#enter wrdev, iclass 33, count 0 2006.174.01:41:00.15#ibcon#first serial, iclass 33, count 0 2006.174.01:41:00.15#ibcon#enter sib2, iclass 33, count 0 2006.174.01:41:00.15#ibcon#flushed, iclass 33, count 0 2006.174.01:41:00.15#ibcon#about to write, iclass 33, count 0 2006.174.01:41:00.15#ibcon#wrote, iclass 33, count 0 2006.174.01:41:00.15#ibcon#about to read 3, iclass 33, count 0 2006.174.01:41:00.17#ibcon#read 3, iclass 33, count 0 2006.174.01:41:00.17#ibcon#about to read 4, iclass 33, count 0 2006.174.01:41:00.17#ibcon#read 4, iclass 33, count 0 2006.174.01:41:00.17#ibcon#about to read 5, iclass 33, count 0 2006.174.01:41:00.17#ibcon#read 5, iclass 33, count 0 2006.174.01:41:00.17#ibcon#about to read 6, iclass 33, count 0 2006.174.01:41:00.17#ibcon#read 6, iclass 33, count 0 2006.174.01:41:00.17#ibcon#end of sib2, iclass 33, count 0 2006.174.01:41:00.17#ibcon#*mode == 0, iclass 33, count 0 2006.174.01:41:00.17#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.174.01:41:00.17#ibcon#[25=USB\r\n] 2006.174.01:41:00.17#ibcon#*before write, iclass 33, count 0 2006.174.01:41:00.17#ibcon#enter sib2, iclass 33, count 0 2006.174.01:41:00.17#ibcon#flushed, iclass 33, count 0 2006.174.01:41:00.17#ibcon#about to write, iclass 33, count 0 2006.174.01:41:00.17#ibcon#wrote, iclass 33, count 0 2006.174.01:41:00.17#ibcon#about to read 3, iclass 33, count 0 2006.174.01:41:00.20#ibcon#read 3, iclass 33, count 0 2006.174.01:41:00.20#ibcon#about to read 4, iclass 33, count 0 2006.174.01:41:00.20#ibcon#read 4, iclass 33, count 0 2006.174.01:41:00.20#ibcon#about to read 5, iclass 33, count 0 2006.174.01:41:00.20#ibcon#read 5, iclass 33, count 0 2006.174.01:41:00.20#ibcon#about to read 6, iclass 33, count 0 2006.174.01:41:00.20#ibcon#read 6, iclass 33, count 0 2006.174.01:41:00.20#ibcon#end of sib2, iclass 33, count 0 2006.174.01:41:00.20#ibcon#*after write, iclass 33, count 0 2006.174.01:41:00.20#ibcon#*before return 0, iclass 33, count 0 2006.174.01:41:00.20#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.174.01:41:00.20#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.174.01:41:00.20#ibcon#about to clear, iclass 33 cls_cnt 0 2006.174.01:41:00.20#ibcon#cleared, iclass 33 cls_cnt 0 2006.174.01:41:00.20$vck44/valo=4,624.99 2006.174.01:41:00.20#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.174.01:41:00.20#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.174.01:41:00.20#ibcon#ireg 17 cls_cnt 0 2006.174.01:41:00.20#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.174.01:41:00.20#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.174.01:41:00.20#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.174.01:41:00.20#ibcon#enter wrdev, iclass 35, count 0 2006.174.01:41:00.20#ibcon#first serial, iclass 35, count 0 2006.174.01:41:00.20#ibcon#enter sib2, iclass 35, count 0 2006.174.01:41:00.20#ibcon#flushed, iclass 35, count 0 2006.174.01:41:00.20#ibcon#about to write, iclass 35, count 0 2006.174.01:41:00.20#ibcon#wrote, iclass 35, count 0 2006.174.01:41:00.20#ibcon#about to read 3, iclass 35, count 0 2006.174.01:41:00.22#ibcon#read 3, iclass 35, count 0 2006.174.01:41:00.22#ibcon#about to read 4, iclass 35, count 0 2006.174.01:41:00.22#ibcon#read 4, iclass 35, count 0 2006.174.01:41:00.22#ibcon#about to read 5, iclass 35, count 0 2006.174.01:41:00.22#ibcon#read 5, iclass 35, count 0 2006.174.01:41:00.22#ibcon#about to read 6, iclass 35, count 0 2006.174.01:41:00.22#ibcon#read 6, iclass 35, count 0 2006.174.01:41:00.22#ibcon#end of sib2, iclass 35, count 0 2006.174.01:41:00.22#ibcon#*mode == 0, iclass 35, count 0 2006.174.01:41:00.22#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.174.01:41:00.22#ibcon#[26=FRQ=04,624.99\r\n] 2006.174.01:41:00.22#ibcon#*before write, iclass 35, count 0 2006.174.01:41:00.22#ibcon#enter sib2, iclass 35, count 0 2006.174.01:41:00.22#ibcon#flushed, iclass 35, count 0 2006.174.01:41:00.22#ibcon#about to write, iclass 35, count 0 2006.174.01:41:00.22#ibcon#wrote, iclass 35, count 0 2006.174.01:41:00.22#ibcon#about to read 3, iclass 35, count 0 2006.174.01:41:00.26#ibcon#read 3, iclass 35, count 0 2006.174.01:41:00.26#ibcon#about to read 4, iclass 35, count 0 2006.174.01:41:00.26#ibcon#read 4, iclass 35, count 0 2006.174.01:41:00.26#ibcon#about to read 5, iclass 35, count 0 2006.174.01:41:00.26#ibcon#read 5, iclass 35, count 0 2006.174.01:41:00.26#ibcon#about to read 6, iclass 35, count 0 2006.174.01:41:00.26#ibcon#read 6, iclass 35, count 0 2006.174.01:41:00.26#ibcon#end of sib2, iclass 35, count 0 2006.174.01:41:00.26#ibcon#*after write, iclass 35, count 0 2006.174.01:41:00.26#ibcon#*before return 0, iclass 35, count 0 2006.174.01:41:00.26#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.174.01:41:00.26#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.174.01:41:00.26#ibcon#about to clear, iclass 35 cls_cnt 0 2006.174.01:41:00.26#ibcon#cleared, iclass 35 cls_cnt 0 2006.174.01:41:00.26$vck44/va=4,6 2006.174.01:41:00.26#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.174.01:41:00.26#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.174.01:41:00.26#ibcon#ireg 11 cls_cnt 2 2006.174.01:41:00.26#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.174.01:41:00.32#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.174.01:41:00.32#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.174.01:41:00.32#ibcon#enter wrdev, iclass 37, count 2 2006.174.01:41:00.32#ibcon#first serial, iclass 37, count 2 2006.174.01:41:00.32#ibcon#enter sib2, iclass 37, count 2 2006.174.01:41:00.32#ibcon#flushed, iclass 37, count 2 2006.174.01:41:00.32#ibcon#about to write, iclass 37, count 2 2006.174.01:41:00.32#ibcon#wrote, iclass 37, count 2 2006.174.01:41:00.32#ibcon#about to read 3, iclass 37, count 2 2006.174.01:41:00.34#ibcon#read 3, iclass 37, count 2 2006.174.01:41:00.34#ibcon#about to read 4, iclass 37, count 2 2006.174.01:41:00.34#ibcon#read 4, iclass 37, count 2 2006.174.01:41:00.34#ibcon#about to read 5, iclass 37, count 2 2006.174.01:41:00.34#ibcon#read 5, iclass 37, count 2 2006.174.01:41:00.34#ibcon#about to read 6, iclass 37, count 2 2006.174.01:41:00.34#ibcon#read 6, iclass 37, count 2 2006.174.01:41:00.34#ibcon#end of sib2, iclass 37, count 2 2006.174.01:41:00.34#ibcon#*mode == 0, iclass 37, count 2 2006.174.01:41:00.34#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.174.01:41:00.34#ibcon#[25=AT04-06\r\n] 2006.174.01:41:00.34#ibcon#*before write, iclass 37, count 2 2006.174.01:41:00.34#ibcon#enter sib2, iclass 37, count 2 2006.174.01:41:00.34#ibcon#flushed, iclass 37, count 2 2006.174.01:41:00.34#ibcon#about to write, iclass 37, count 2 2006.174.01:41:00.34#ibcon#wrote, iclass 37, count 2 2006.174.01:41:00.34#ibcon#about to read 3, iclass 37, count 2 2006.174.01:41:00.37#ibcon#read 3, iclass 37, count 2 2006.174.01:41:00.37#ibcon#about to read 4, iclass 37, count 2 2006.174.01:41:00.37#ibcon#read 4, iclass 37, count 2 2006.174.01:41:00.37#ibcon#about to read 5, iclass 37, count 2 2006.174.01:41:00.37#ibcon#read 5, iclass 37, count 2 2006.174.01:41:00.37#ibcon#about to read 6, iclass 37, count 2 2006.174.01:41:00.37#ibcon#read 6, iclass 37, count 2 2006.174.01:41:00.37#ibcon#end of sib2, iclass 37, count 2 2006.174.01:41:00.37#ibcon#*after write, iclass 37, count 2 2006.174.01:41:00.37#ibcon#*before return 0, iclass 37, count 2 2006.174.01:41:00.37#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.174.01:41:00.37#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.174.01:41:00.37#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.174.01:41:00.37#ibcon#ireg 7 cls_cnt 0 2006.174.01:41:00.37#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.174.01:41:00.48#abcon#<5=/09 1.1 2.7 26.14 711003.3\r\n> 2006.174.01:41:00.49#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.174.01:41:00.49#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.174.01:41:00.49#ibcon#enter wrdev, iclass 37, count 0 2006.174.01:41:00.49#ibcon#first serial, iclass 37, count 0 2006.174.01:41:00.49#ibcon#enter sib2, iclass 37, count 0 2006.174.01:41:00.49#ibcon#flushed, iclass 37, count 0 2006.174.01:41:00.49#ibcon#about to write, iclass 37, count 0 2006.174.01:41:00.49#ibcon#wrote, iclass 37, count 0 2006.174.01:41:00.49#ibcon#about to read 3, iclass 37, count 0 2006.174.01:41:00.50#abcon#{5=INTERFACE CLEAR} 2006.174.01:41:00.51#ibcon#read 3, iclass 37, count 0 2006.174.01:41:00.51#ibcon#about to read 4, iclass 37, count 0 2006.174.01:41:00.51#ibcon#read 4, iclass 37, count 0 2006.174.01:41:00.51#ibcon#about to read 5, iclass 37, count 0 2006.174.01:41:00.51#ibcon#read 5, iclass 37, count 0 2006.174.01:41:00.51#ibcon#about to read 6, iclass 37, count 0 2006.174.01:41:00.51#ibcon#read 6, iclass 37, count 0 2006.174.01:41:00.51#ibcon#end of sib2, iclass 37, count 0 2006.174.01:41:00.51#ibcon#*mode == 0, iclass 37, count 0 2006.174.01:41:00.51#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.174.01:41:00.51#ibcon#[25=USB\r\n] 2006.174.01:41:00.51#ibcon#*before write, iclass 37, count 0 2006.174.01:41:00.51#ibcon#enter sib2, iclass 37, count 0 2006.174.01:41:00.51#ibcon#flushed, iclass 37, count 0 2006.174.01:41:00.51#ibcon#about to write, iclass 37, count 0 2006.174.01:41:00.51#ibcon#wrote, iclass 37, count 0 2006.174.01:41:00.51#ibcon#about to read 3, iclass 37, count 0 2006.174.01:41:00.54#ibcon#read 3, iclass 37, count 0 2006.174.01:41:00.54#ibcon#about to read 4, iclass 37, count 0 2006.174.01:41:00.54#ibcon#read 4, iclass 37, count 0 2006.174.01:41:00.54#ibcon#about to read 5, iclass 37, count 0 2006.174.01:41:00.54#ibcon#read 5, iclass 37, count 0 2006.174.01:41:00.54#ibcon#about to read 6, iclass 37, count 0 2006.174.01:41:00.54#ibcon#read 6, iclass 37, count 0 2006.174.01:41:00.54#ibcon#end of sib2, iclass 37, count 0 2006.174.01:41:00.54#ibcon#*after write, iclass 37, count 0 2006.174.01:41:00.54#ibcon#*before return 0, iclass 37, count 0 2006.174.01:41:00.54#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.174.01:41:00.54#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.174.01:41:00.54#ibcon#about to clear, iclass 37 cls_cnt 0 2006.174.01:41:00.54#ibcon#cleared, iclass 37 cls_cnt 0 2006.174.01:41:00.54$vck44/valo=5,734.99 2006.174.01:41:00.54#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.174.01:41:00.54#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.174.01:41:00.54#ibcon#ireg 17 cls_cnt 0 2006.174.01:41:00.54#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.174.01:41:00.54#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.174.01:41:00.54#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.174.01:41:00.54#ibcon#enter wrdev, iclass 4, count 0 2006.174.01:41:00.54#ibcon#first serial, iclass 4, count 0 2006.174.01:41:00.54#ibcon#enter sib2, iclass 4, count 0 2006.174.01:41:00.54#ibcon#flushed, iclass 4, count 0 2006.174.01:41:00.54#ibcon#about to write, iclass 4, count 0 2006.174.01:41:00.54#ibcon#wrote, iclass 4, count 0 2006.174.01:41:00.54#ibcon#about to read 3, iclass 4, count 0 2006.174.01:41:00.56#ibcon#read 3, iclass 4, count 0 2006.174.01:41:00.56#ibcon#about to read 4, iclass 4, count 0 2006.174.01:41:00.56#ibcon#read 4, iclass 4, count 0 2006.174.01:41:00.56#ibcon#about to read 5, iclass 4, count 0 2006.174.01:41:00.56#ibcon#read 5, iclass 4, count 0 2006.174.01:41:00.56#ibcon#about to read 6, iclass 4, count 0 2006.174.01:41:00.56#ibcon#read 6, iclass 4, count 0 2006.174.01:41:00.56#ibcon#end of sib2, iclass 4, count 0 2006.174.01:41:00.56#ibcon#*mode == 0, iclass 4, count 0 2006.174.01:41:00.56#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.174.01:41:00.56#ibcon#[26=FRQ=05,734.99\r\n] 2006.174.01:41:00.56#ibcon#*before write, iclass 4, count 0 2006.174.01:41:00.56#ibcon#enter sib2, iclass 4, count 0 2006.174.01:41:00.56#ibcon#flushed, iclass 4, count 0 2006.174.01:41:00.56#ibcon#about to write, iclass 4, count 0 2006.174.01:41:00.56#ibcon#wrote, iclass 4, count 0 2006.174.01:41:00.56#ibcon#about to read 3, iclass 4, count 0 2006.174.01:41:00.56#abcon#[5=S1D000X0/0*\r\n] 2006.174.01:41:00.60#ibcon#read 3, iclass 4, count 0 2006.174.01:41:00.60#ibcon#about to read 4, iclass 4, count 0 2006.174.01:41:00.60#ibcon#read 4, iclass 4, count 0 2006.174.01:41:00.60#ibcon#about to read 5, iclass 4, count 0 2006.174.01:41:00.60#ibcon#read 5, iclass 4, count 0 2006.174.01:41:00.60#ibcon#about to read 6, iclass 4, count 0 2006.174.01:41:00.60#ibcon#read 6, iclass 4, count 0 2006.174.01:41:00.60#ibcon#end of sib2, iclass 4, count 0 2006.174.01:41:00.60#ibcon#*after write, iclass 4, count 0 2006.174.01:41:00.60#ibcon#*before return 0, iclass 4, count 0 2006.174.01:41:00.60#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.174.01:41:00.60#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.174.01:41:00.60#ibcon#about to clear, iclass 4 cls_cnt 0 2006.174.01:41:00.60#ibcon#cleared, iclass 4 cls_cnt 0 2006.174.01:41:00.60$vck44/va=5,4 2006.174.01:41:00.60#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.174.01:41:00.60#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.174.01:41:00.60#ibcon#ireg 11 cls_cnt 2 2006.174.01:41:00.60#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.174.01:41:00.66#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.174.01:41:00.66#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.174.01:41:00.66#ibcon#enter wrdev, iclass 7, count 2 2006.174.01:41:00.66#ibcon#first serial, iclass 7, count 2 2006.174.01:41:00.66#ibcon#enter sib2, iclass 7, count 2 2006.174.01:41:00.66#ibcon#flushed, iclass 7, count 2 2006.174.01:41:00.66#ibcon#about to write, iclass 7, count 2 2006.174.01:41:00.66#ibcon#wrote, iclass 7, count 2 2006.174.01:41:00.66#ibcon#about to read 3, iclass 7, count 2 2006.174.01:41:00.68#ibcon#read 3, iclass 7, count 2 2006.174.01:41:00.68#ibcon#about to read 4, iclass 7, count 2 2006.174.01:41:00.68#ibcon#read 4, iclass 7, count 2 2006.174.01:41:00.68#ibcon#about to read 5, iclass 7, count 2 2006.174.01:41:00.68#ibcon#read 5, iclass 7, count 2 2006.174.01:41:00.68#ibcon#about to read 6, iclass 7, count 2 2006.174.01:41:00.68#ibcon#read 6, iclass 7, count 2 2006.174.01:41:00.68#ibcon#end of sib2, iclass 7, count 2 2006.174.01:41:00.68#ibcon#*mode == 0, iclass 7, count 2 2006.174.01:41:00.68#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.174.01:41:00.68#ibcon#[25=AT05-04\r\n] 2006.174.01:41:00.68#ibcon#*before write, iclass 7, count 2 2006.174.01:41:00.68#ibcon#enter sib2, iclass 7, count 2 2006.174.01:41:00.68#ibcon#flushed, iclass 7, count 2 2006.174.01:41:00.68#ibcon#about to write, iclass 7, count 2 2006.174.01:41:00.68#ibcon#wrote, iclass 7, count 2 2006.174.01:41:00.68#ibcon#about to read 3, iclass 7, count 2 2006.174.01:41:00.71#ibcon#read 3, iclass 7, count 2 2006.174.01:41:00.71#ibcon#about to read 4, iclass 7, count 2 2006.174.01:41:00.71#ibcon#read 4, iclass 7, count 2 2006.174.01:41:00.71#ibcon#about to read 5, iclass 7, count 2 2006.174.01:41:00.71#ibcon#read 5, iclass 7, count 2 2006.174.01:41:00.71#ibcon#about to read 6, iclass 7, count 2 2006.174.01:41:00.71#ibcon#read 6, iclass 7, count 2 2006.174.01:41:00.71#ibcon#end of sib2, iclass 7, count 2 2006.174.01:41:00.71#ibcon#*after write, iclass 7, count 2 2006.174.01:41:00.71#ibcon#*before return 0, iclass 7, count 2 2006.174.01:41:00.71#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.174.01:41:00.71#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.174.01:41:00.71#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.174.01:41:00.71#ibcon#ireg 7 cls_cnt 0 2006.174.01:41:00.71#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.174.01:41:00.83#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.174.01:41:00.83#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.174.01:41:00.83#ibcon#enter wrdev, iclass 7, count 0 2006.174.01:41:00.83#ibcon#first serial, iclass 7, count 0 2006.174.01:41:00.83#ibcon#enter sib2, iclass 7, count 0 2006.174.01:41:00.83#ibcon#flushed, iclass 7, count 0 2006.174.01:41:00.83#ibcon#about to write, iclass 7, count 0 2006.174.01:41:00.83#ibcon#wrote, iclass 7, count 0 2006.174.01:41:00.83#ibcon#about to read 3, iclass 7, count 0 2006.174.01:41:00.85#ibcon#read 3, iclass 7, count 0 2006.174.01:41:00.85#ibcon#about to read 4, iclass 7, count 0 2006.174.01:41:00.85#ibcon#read 4, iclass 7, count 0 2006.174.01:41:00.85#ibcon#about to read 5, iclass 7, count 0 2006.174.01:41:00.85#ibcon#read 5, iclass 7, count 0 2006.174.01:41:00.85#ibcon#about to read 6, iclass 7, count 0 2006.174.01:41:00.85#ibcon#read 6, iclass 7, count 0 2006.174.01:41:00.85#ibcon#end of sib2, iclass 7, count 0 2006.174.01:41:00.85#ibcon#*mode == 0, iclass 7, count 0 2006.174.01:41:00.85#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.174.01:41:00.85#ibcon#[25=USB\r\n] 2006.174.01:41:00.85#ibcon#*before write, iclass 7, count 0 2006.174.01:41:00.85#ibcon#enter sib2, iclass 7, count 0 2006.174.01:41:00.85#ibcon#flushed, iclass 7, count 0 2006.174.01:41:00.85#ibcon#about to write, iclass 7, count 0 2006.174.01:41:00.85#ibcon#wrote, iclass 7, count 0 2006.174.01:41:00.85#ibcon#about to read 3, iclass 7, count 0 2006.174.01:41:00.88#ibcon#read 3, iclass 7, count 0 2006.174.01:41:00.88#ibcon#about to read 4, iclass 7, count 0 2006.174.01:41:00.88#ibcon#read 4, iclass 7, count 0 2006.174.01:41:00.88#ibcon#about to read 5, iclass 7, count 0 2006.174.01:41:00.88#ibcon#read 5, iclass 7, count 0 2006.174.01:41:00.88#ibcon#about to read 6, iclass 7, count 0 2006.174.01:41:00.88#ibcon#read 6, iclass 7, count 0 2006.174.01:41:00.88#ibcon#end of sib2, iclass 7, count 0 2006.174.01:41:00.88#ibcon#*after write, iclass 7, count 0 2006.174.01:41:00.88#ibcon#*before return 0, iclass 7, count 0 2006.174.01:41:00.88#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.174.01:41:00.88#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.174.01:41:00.88#ibcon#about to clear, iclass 7 cls_cnt 0 2006.174.01:41:00.88#ibcon#cleared, iclass 7 cls_cnt 0 2006.174.01:41:00.88$vck44/valo=6,814.99 2006.174.01:41:00.88#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.174.01:41:00.88#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.174.01:41:00.88#ibcon#ireg 17 cls_cnt 0 2006.174.01:41:00.88#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.174.01:41:00.88#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.174.01:41:00.88#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.174.01:41:00.88#ibcon#enter wrdev, iclass 11, count 0 2006.174.01:41:00.88#ibcon#first serial, iclass 11, count 0 2006.174.01:41:00.88#ibcon#enter sib2, iclass 11, count 0 2006.174.01:41:00.88#ibcon#flushed, iclass 11, count 0 2006.174.01:41:00.88#ibcon#about to write, iclass 11, count 0 2006.174.01:41:00.88#ibcon#wrote, iclass 11, count 0 2006.174.01:41:00.88#ibcon#about to read 3, iclass 11, count 0 2006.174.01:41:00.90#ibcon#read 3, iclass 11, count 0 2006.174.01:41:00.90#ibcon#about to read 4, iclass 11, count 0 2006.174.01:41:00.90#ibcon#read 4, iclass 11, count 0 2006.174.01:41:00.90#ibcon#about to read 5, iclass 11, count 0 2006.174.01:41:00.90#ibcon#read 5, iclass 11, count 0 2006.174.01:41:00.90#ibcon#about to read 6, iclass 11, count 0 2006.174.01:41:00.90#ibcon#read 6, iclass 11, count 0 2006.174.01:41:00.90#ibcon#end of sib2, iclass 11, count 0 2006.174.01:41:00.90#ibcon#*mode == 0, iclass 11, count 0 2006.174.01:41:00.90#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.174.01:41:00.90#ibcon#[26=FRQ=06,814.99\r\n] 2006.174.01:41:00.90#ibcon#*before write, iclass 11, count 0 2006.174.01:41:00.90#ibcon#enter sib2, iclass 11, count 0 2006.174.01:41:00.90#ibcon#flushed, iclass 11, count 0 2006.174.01:41:00.90#ibcon#about to write, iclass 11, count 0 2006.174.01:41:00.90#ibcon#wrote, iclass 11, count 0 2006.174.01:41:00.90#ibcon#about to read 3, iclass 11, count 0 2006.174.01:41:00.94#ibcon#read 3, iclass 11, count 0 2006.174.01:41:00.94#ibcon#about to read 4, iclass 11, count 0 2006.174.01:41:00.94#ibcon#read 4, iclass 11, count 0 2006.174.01:41:00.94#ibcon#about to read 5, iclass 11, count 0 2006.174.01:41:00.94#ibcon#read 5, iclass 11, count 0 2006.174.01:41:00.94#ibcon#about to read 6, iclass 11, count 0 2006.174.01:41:00.94#ibcon#read 6, iclass 11, count 0 2006.174.01:41:00.94#ibcon#end of sib2, iclass 11, count 0 2006.174.01:41:00.94#ibcon#*after write, iclass 11, count 0 2006.174.01:41:00.94#ibcon#*before return 0, iclass 11, count 0 2006.174.01:41:00.94#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.174.01:41:00.94#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.174.01:41:00.94#ibcon#about to clear, iclass 11 cls_cnt 0 2006.174.01:41:00.94#ibcon#cleared, iclass 11 cls_cnt 0 2006.174.01:41:00.94$vck44/va=6,3 2006.174.01:41:00.94#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.174.01:41:00.94#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.174.01:41:00.94#ibcon#ireg 11 cls_cnt 2 2006.174.01:41:00.94#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.174.01:41:01.00#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.174.01:41:01.00#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.174.01:41:01.00#ibcon#enter wrdev, iclass 13, count 2 2006.174.01:41:01.00#ibcon#first serial, iclass 13, count 2 2006.174.01:41:01.00#ibcon#enter sib2, iclass 13, count 2 2006.174.01:41:01.00#ibcon#flushed, iclass 13, count 2 2006.174.01:41:01.00#ibcon#about to write, iclass 13, count 2 2006.174.01:41:01.00#ibcon#wrote, iclass 13, count 2 2006.174.01:41:01.00#ibcon#about to read 3, iclass 13, count 2 2006.174.01:41:01.02#ibcon#read 3, iclass 13, count 2 2006.174.01:41:01.02#ibcon#about to read 4, iclass 13, count 2 2006.174.01:41:01.02#ibcon#read 4, iclass 13, count 2 2006.174.01:41:01.02#ibcon#about to read 5, iclass 13, count 2 2006.174.01:41:01.02#ibcon#read 5, iclass 13, count 2 2006.174.01:41:01.02#ibcon#about to read 6, iclass 13, count 2 2006.174.01:41:01.02#ibcon#read 6, iclass 13, count 2 2006.174.01:41:01.02#ibcon#end of sib2, iclass 13, count 2 2006.174.01:41:01.02#ibcon#*mode == 0, iclass 13, count 2 2006.174.01:41:01.02#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.174.01:41:01.02#ibcon#[25=AT06-03\r\n] 2006.174.01:41:01.02#ibcon#*before write, iclass 13, count 2 2006.174.01:41:01.02#ibcon#enter sib2, iclass 13, count 2 2006.174.01:41:01.02#ibcon#flushed, iclass 13, count 2 2006.174.01:41:01.02#ibcon#about to write, iclass 13, count 2 2006.174.01:41:01.02#ibcon#wrote, iclass 13, count 2 2006.174.01:41:01.02#ibcon#about to read 3, iclass 13, count 2 2006.174.01:41:01.05#ibcon#read 3, iclass 13, count 2 2006.174.01:41:01.05#ibcon#about to read 4, iclass 13, count 2 2006.174.01:41:01.05#ibcon#read 4, iclass 13, count 2 2006.174.01:41:01.05#ibcon#about to read 5, iclass 13, count 2 2006.174.01:41:01.05#ibcon#read 5, iclass 13, count 2 2006.174.01:41:01.05#ibcon#about to read 6, iclass 13, count 2 2006.174.01:41:01.05#ibcon#read 6, iclass 13, count 2 2006.174.01:41:01.05#ibcon#end of sib2, iclass 13, count 2 2006.174.01:41:01.05#ibcon#*after write, iclass 13, count 2 2006.174.01:41:01.05#ibcon#*before return 0, iclass 13, count 2 2006.174.01:41:01.05#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.174.01:41:01.05#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.174.01:41:01.05#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.174.01:41:01.05#ibcon#ireg 7 cls_cnt 0 2006.174.01:41:01.05#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.174.01:41:01.17#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.174.01:41:01.17#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.174.01:41:01.17#ibcon#enter wrdev, iclass 13, count 0 2006.174.01:41:01.17#ibcon#first serial, iclass 13, count 0 2006.174.01:41:01.17#ibcon#enter sib2, iclass 13, count 0 2006.174.01:41:01.17#ibcon#flushed, iclass 13, count 0 2006.174.01:41:01.17#ibcon#about to write, iclass 13, count 0 2006.174.01:41:01.17#ibcon#wrote, iclass 13, count 0 2006.174.01:41:01.17#ibcon#about to read 3, iclass 13, count 0 2006.174.01:41:01.19#ibcon#read 3, iclass 13, count 0 2006.174.01:41:01.19#ibcon#about to read 4, iclass 13, count 0 2006.174.01:41:01.19#ibcon#read 4, iclass 13, count 0 2006.174.01:41:01.19#ibcon#about to read 5, iclass 13, count 0 2006.174.01:41:01.19#ibcon#read 5, iclass 13, count 0 2006.174.01:41:01.19#ibcon#about to read 6, iclass 13, count 0 2006.174.01:41:01.19#ibcon#read 6, iclass 13, count 0 2006.174.01:41:01.19#ibcon#end of sib2, iclass 13, count 0 2006.174.01:41:01.19#ibcon#*mode == 0, iclass 13, count 0 2006.174.01:41:01.19#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.174.01:41:01.19#ibcon#[25=USB\r\n] 2006.174.01:41:01.19#ibcon#*before write, iclass 13, count 0 2006.174.01:41:01.19#ibcon#enter sib2, iclass 13, count 0 2006.174.01:41:01.19#ibcon#flushed, iclass 13, count 0 2006.174.01:41:01.19#ibcon#about to write, iclass 13, count 0 2006.174.01:41:01.19#ibcon#wrote, iclass 13, count 0 2006.174.01:41:01.19#ibcon#about to read 3, iclass 13, count 0 2006.174.01:41:01.22#ibcon#read 3, iclass 13, count 0 2006.174.01:41:01.22#ibcon#about to read 4, iclass 13, count 0 2006.174.01:41:01.22#ibcon#read 4, iclass 13, count 0 2006.174.01:41:01.22#ibcon#about to read 5, iclass 13, count 0 2006.174.01:41:01.22#ibcon#read 5, iclass 13, count 0 2006.174.01:41:01.22#ibcon#about to read 6, iclass 13, count 0 2006.174.01:41:01.22#ibcon#read 6, iclass 13, count 0 2006.174.01:41:01.22#ibcon#end of sib2, iclass 13, count 0 2006.174.01:41:01.22#ibcon#*after write, iclass 13, count 0 2006.174.01:41:01.22#ibcon#*before return 0, iclass 13, count 0 2006.174.01:41:01.22#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.174.01:41:01.22#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.174.01:41:01.22#ibcon#about to clear, iclass 13 cls_cnt 0 2006.174.01:41:01.22#ibcon#cleared, iclass 13 cls_cnt 0 2006.174.01:41:01.22$vck44/valo=7,864.99 2006.174.01:41:01.22#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.174.01:41:01.22#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.174.01:41:01.22#ibcon#ireg 17 cls_cnt 0 2006.174.01:41:01.22#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.174.01:41:01.22#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.174.01:41:01.22#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.174.01:41:01.22#ibcon#enter wrdev, iclass 15, count 0 2006.174.01:41:01.22#ibcon#first serial, iclass 15, count 0 2006.174.01:41:01.22#ibcon#enter sib2, iclass 15, count 0 2006.174.01:41:01.22#ibcon#flushed, iclass 15, count 0 2006.174.01:41:01.22#ibcon#about to write, iclass 15, count 0 2006.174.01:41:01.22#ibcon#wrote, iclass 15, count 0 2006.174.01:41:01.22#ibcon#about to read 3, iclass 15, count 0 2006.174.01:41:01.24#ibcon#read 3, iclass 15, count 0 2006.174.01:41:01.24#ibcon#about to read 4, iclass 15, count 0 2006.174.01:41:01.24#ibcon#read 4, iclass 15, count 0 2006.174.01:41:01.24#ibcon#about to read 5, iclass 15, count 0 2006.174.01:41:01.24#ibcon#read 5, iclass 15, count 0 2006.174.01:41:01.24#ibcon#about to read 6, iclass 15, count 0 2006.174.01:41:01.24#ibcon#read 6, iclass 15, count 0 2006.174.01:41:01.24#ibcon#end of sib2, iclass 15, count 0 2006.174.01:41:01.24#ibcon#*mode == 0, iclass 15, count 0 2006.174.01:41:01.24#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.174.01:41:01.24#ibcon#[26=FRQ=07,864.99\r\n] 2006.174.01:41:01.24#ibcon#*before write, iclass 15, count 0 2006.174.01:41:01.24#ibcon#enter sib2, iclass 15, count 0 2006.174.01:41:01.24#ibcon#flushed, iclass 15, count 0 2006.174.01:41:01.24#ibcon#about to write, iclass 15, count 0 2006.174.01:41:01.24#ibcon#wrote, iclass 15, count 0 2006.174.01:41:01.24#ibcon#about to read 3, iclass 15, count 0 2006.174.01:41:01.28#ibcon#read 3, iclass 15, count 0 2006.174.01:41:01.28#ibcon#about to read 4, iclass 15, count 0 2006.174.01:41:01.28#ibcon#read 4, iclass 15, count 0 2006.174.01:41:01.28#ibcon#about to read 5, iclass 15, count 0 2006.174.01:41:01.28#ibcon#read 5, iclass 15, count 0 2006.174.01:41:01.28#ibcon#about to read 6, iclass 15, count 0 2006.174.01:41:01.28#ibcon#read 6, iclass 15, count 0 2006.174.01:41:01.28#ibcon#end of sib2, iclass 15, count 0 2006.174.01:41:01.28#ibcon#*after write, iclass 15, count 0 2006.174.01:41:01.28#ibcon#*before return 0, iclass 15, count 0 2006.174.01:41:01.28#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.174.01:41:01.28#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.174.01:41:01.28#ibcon#about to clear, iclass 15 cls_cnt 0 2006.174.01:41:01.28#ibcon#cleared, iclass 15 cls_cnt 0 2006.174.01:41:01.28$vck44/va=7,4 2006.174.01:41:01.28#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.174.01:41:01.28#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.174.01:41:01.28#ibcon#ireg 11 cls_cnt 2 2006.174.01:41:01.28#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.174.01:41:01.34#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.174.01:41:01.34#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.174.01:41:01.34#ibcon#enter wrdev, iclass 17, count 2 2006.174.01:41:01.34#ibcon#first serial, iclass 17, count 2 2006.174.01:41:01.34#ibcon#enter sib2, iclass 17, count 2 2006.174.01:41:01.34#ibcon#flushed, iclass 17, count 2 2006.174.01:41:01.34#ibcon#about to write, iclass 17, count 2 2006.174.01:41:01.34#ibcon#wrote, iclass 17, count 2 2006.174.01:41:01.34#ibcon#about to read 3, iclass 17, count 2 2006.174.01:41:01.36#ibcon#read 3, iclass 17, count 2 2006.174.01:41:01.36#ibcon#about to read 4, iclass 17, count 2 2006.174.01:41:01.36#ibcon#read 4, iclass 17, count 2 2006.174.01:41:01.36#ibcon#about to read 5, iclass 17, count 2 2006.174.01:41:01.36#ibcon#read 5, iclass 17, count 2 2006.174.01:41:01.36#ibcon#about to read 6, iclass 17, count 2 2006.174.01:41:01.36#ibcon#read 6, iclass 17, count 2 2006.174.01:41:01.36#ibcon#end of sib2, iclass 17, count 2 2006.174.01:41:01.36#ibcon#*mode == 0, iclass 17, count 2 2006.174.01:41:01.36#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.174.01:41:01.36#ibcon#[25=AT07-04\r\n] 2006.174.01:41:01.36#ibcon#*before write, iclass 17, count 2 2006.174.01:41:01.36#ibcon#enter sib2, iclass 17, count 2 2006.174.01:41:01.36#ibcon#flushed, iclass 17, count 2 2006.174.01:41:01.36#ibcon#about to write, iclass 17, count 2 2006.174.01:41:01.36#ibcon#wrote, iclass 17, count 2 2006.174.01:41:01.36#ibcon#about to read 3, iclass 17, count 2 2006.174.01:41:01.39#ibcon#read 3, iclass 17, count 2 2006.174.01:41:01.39#ibcon#about to read 4, iclass 17, count 2 2006.174.01:41:01.39#ibcon#read 4, iclass 17, count 2 2006.174.01:41:01.39#ibcon#about to read 5, iclass 17, count 2 2006.174.01:41:01.39#ibcon#read 5, iclass 17, count 2 2006.174.01:41:01.39#ibcon#about to read 6, iclass 17, count 2 2006.174.01:41:01.39#ibcon#read 6, iclass 17, count 2 2006.174.01:41:01.39#ibcon#end of sib2, iclass 17, count 2 2006.174.01:41:01.39#ibcon#*after write, iclass 17, count 2 2006.174.01:41:01.39#ibcon#*before return 0, iclass 17, count 2 2006.174.01:41:01.39#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.174.01:41:01.39#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.174.01:41:01.39#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.174.01:41:01.39#ibcon#ireg 7 cls_cnt 0 2006.174.01:41:01.39#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.174.01:41:01.51#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.174.01:41:01.51#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.174.01:41:01.51#ibcon#enter wrdev, iclass 17, count 0 2006.174.01:41:01.51#ibcon#first serial, iclass 17, count 0 2006.174.01:41:01.51#ibcon#enter sib2, iclass 17, count 0 2006.174.01:41:01.51#ibcon#flushed, iclass 17, count 0 2006.174.01:41:01.51#ibcon#about to write, iclass 17, count 0 2006.174.01:41:01.51#ibcon#wrote, iclass 17, count 0 2006.174.01:41:01.51#ibcon#about to read 3, iclass 17, count 0 2006.174.01:41:01.53#ibcon#read 3, iclass 17, count 0 2006.174.01:41:01.53#ibcon#about to read 4, iclass 17, count 0 2006.174.01:41:01.53#ibcon#read 4, iclass 17, count 0 2006.174.01:41:01.53#ibcon#about to read 5, iclass 17, count 0 2006.174.01:41:01.53#ibcon#read 5, iclass 17, count 0 2006.174.01:41:01.53#ibcon#about to read 6, iclass 17, count 0 2006.174.01:41:01.53#ibcon#read 6, iclass 17, count 0 2006.174.01:41:01.53#ibcon#end of sib2, iclass 17, count 0 2006.174.01:41:01.53#ibcon#*mode == 0, iclass 17, count 0 2006.174.01:41:01.53#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.174.01:41:01.53#ibcon#[25=USB\r\n] 2006.174.01:41:01.53#ibcon#*before write, iclass 17, count 0 2006.174.01:41:01.53#ibcon#enter sib2, iclass 17, count 0 2006.174.01:41:01.53#ibcon#flushed, iclass 17, count 0 2006.174.01:41:01.53#ibcon#about to write, iclass 17, count 0 2006.174.01:41:01.53#ibcon#wrote, iclass 17, count 0 2006.174.01:41:01.53#ibcon#about to read 3, iclass 17, count 0 2006.174.01:41:01.56#ibcon#read 3, iclass 17, count 0 2006.174.01:41:01.56#ibcon#about to read 4, iclass 17, count 0 2006.174.01:41:01.56#ibcon#read 4, iclass 17, count 0 2006.174.01:41:01.56#ibcon#about to read 5, iclass 17, count 0 2006.174.01:41:01.56#ibcon#read 5, iclass 17, count 0 2006.174.01:41:01.56#ibcon#about to read 6, iclass 17, count 0 2006.174.01:41:01.56#ibcon#read 6, iclass 17, count 0 2006.174.01:41:01.56#ibcon#end of sib2, iclass 17, count 0 2006.174.01:41:01.56#ibcon#*after write, iclass 17, count 0 2006.174.01:41:01.56#ibcon#*before return 0, iclass 17, count 0 2006.174.01:41:01.56#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.174.01:41:01.56#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.174.01:41:01.56#ibcon#about to clear, iclass 17 cls_cnt 0 2006.174.01:41:01.56#ibcon#cleared, iclass 17 cls_cnt 0 2006.174.01:41:01.56$vck44/valo=8,884.99 2006.174.01:41:01.56#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.174.01:41:01.56#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.174.01:41:01.56#ibcon#ireg 17 cls_cnt 0 2006.174.01:41:01.56#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.174.01:41:01.56#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.174.01:41:01.56#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.174.01:41:01.56#ibcon#enter wrdev, iclass 19, count 0 2006.174.01:41:01.56#ibcon#first serial, iclass 19, count 0 2006.174.01:41:01.56#ibcon#enter sib2, iclass 19, count 0 2006.174.01:41:01.56#ibcon#flushed, iclass 19, count 0 2006.174.01:41:01.56#ibcon#about to write, iclass 19, count 0 2006.174.01:41:01.56#ibcon#wrote, iclass 19, count 0 2006.174.01:41:01.56#ibcon#about to read 3, iclass 19, count 0 2006.174.01:41:01.58#ibcon#read 3, iclass 19, count 0 2006.174.01:41:01.58#ibcon#about to read 4, iclass 19, count 0 2006.174.01:41:01.58#ibcon#read 4, iclass 19, count 0 2006.174.01:41:01.58#ibcon#about to read 5, iclass 19, count 0 2006.174.01:41:01.58#ibcon#read 5, iclass 19, count 0 2006.174.01:41:01.58#ibcon#about to read 6, iclass 19, count 0 2006.174.01:41:01.58#ibcon#read 6, iclass 19, count 0 2006.174.01:41:01.58#ibcon#end of sib2, iclass 19, count 0 2006.174.01:41:01.58#ibcon#*mode == 0, iclass 19, count 0 2006.174.01:41:01.58#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.174.01:41:01.58#ibcon#[26=FRQ=08,884.99\r\n] 2006.174.01:41:01.58#ibcon#*before write, iclass 19, count 0 2006.174.01:41:01.58#ibcon#enter sib2, iclass 19, count 0 2006.174.01:41:01.58#ibcon#flushed, iclass 19, count 0 2006.174.01:41:01.58#ibcon#about to write, iclass 19, count 0 2006.174.01:41:01.58#ibcon#wrote, iclass 19, count 0 2006.174.01:41:01.58#ibcon#about to read 3, iclass 19, count 0 2006.174.01:41:01.62#ibcon#read 3, iclass 19, count 0 2006.174.01:41:01.62#ibcon#about to read 4, iclass 19, count 0 2006.174.01:41:01.62#ibcon#read 4, iclass 19, count 0 2006.174.01:41:01.62#ibcon#about to read 5, iclass 19, count 0 2006.174.01:41:01.62#ibcon#read 5, iclass 19, count 0 2006.174.01:41:01.62#ibcon#about to read 6, iclass 19, count 0 2006.174.01:41:01.62#ibcon#read 6, iclass 19, count 0 2006.174.01:41:01.62#ibcon#end of sib2, iclass 19, count 0 2006.174.01:41:01.62#ibcon#*after write, iclass 19, count 0 2006.174.01:41:01.62#ibcon#*before return 0, iclass 19, count 0 2006.174.01:41:01.62#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.174.01:41:01.62#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.174.01:41:01.62#ibcon#about to clear, iclass 19 cls_cnt 0 2006.174.01:41:01.62#ibcon#cleared, iclass 19 cls_cnt 0 2006.174.01:41:01.62$vck44/va=8,4 2006.174.01:41:01.62#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.174.01:41:01.62#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.174.01:41:01.62#ibcon#ireg 11 cls_cnt 2 2006.174.01:41:01.62#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.174.01:41:01.68#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.174.01:41:01.68#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.174.01:41:01.68#ibcon#enter wrdev, iclass 21, count 2 2006.174.01:41:01.68#ibcon#first serial, iclass 21, count 2 2006.174.01:41:01.68#ibcon#enter sib2, iclass 21, count 2 2006.174.01:41:01.68#ibcon#flushed, iclass 21, count 2 2006.174.01:41:01.68#ibcon#about to write, iclass 21, count 2 2006.174.01:41:01.68#ibcon#wrote, iclass 21, count 2 2006.174.01:41:01.68#ibcon#about to read 3, iclass 21, count 2 2006.174.01:41:01.70#ibcon#read 3, iclass 21, count 2 2006.174.01:41:01.70#ibcon#about to read 4, iclass 21, count 2 2006.174.01:41:01.70#ibcon#read 4, iclass 21, count 2 2006.174.01:41:01.70#ibcon#about to read 5, iclass 21, count 2 2006.174.01:41:01.70#ibcon#read 5, iclass 21, count 2 2006.174.01:41:01.70#ibcon#about to read 6, iclass 21, count 2 2006.174.01:41:01.70#ibcon#read 6, iclass 21, count 2 2006.174.01:41:01.70#ibcon#end of sib2, iclass 21, count 2 2006.174.01:41:01.70#ibcon#*mode == 0, iclass 21, count 2 2006.174.01:41:01.70#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.174.01:41:01.70#ibcon#[25=AT08-04\r\n] 2006.174.01:41:01.70#ibcon#*before write, iclass 21, count 2 2006.174.01:41:01.70#ibcon#enter sib2, iclass 21, count 2 2006.174.01:41:01.70#ibcon#flushed, iclass 21, count 2 2006.174.01:41:01.70#ibcon#about to write, iclass 21, count 2 2006.174.01:41:01.70#ibcon#wrote, iclass 21, count 2 2006.174.01:41:01.70#ibcon#about to read 3, iclass 21, count 2 2006.174.01:41:01.73#ibcon#read 3, iclass 21, count 2 2006.174.01:41:01.73#ibcon#about to read 4, iclass 21, count 2 2006.174.01:41:01.73#ibcon#read 4, iclass 21, count 2 2006.174.01:41:01.73#ibcon#about to read 5, iclass 21, count 2 2006.174.01:41:01.73#ibcon#read 5, iclass 21, count 2 2006.174.01:41:01.73#ibcon#about to read 6, iclass 21, count 2 2006.174.01:41:01.73#ibcon#read 6, iclass 21, count 2 2006.174.01:41:01.73#ibcon#end of sib2, iclass 21, count 2 2006.174.01:41:01.73#ibcon#*after write, iclass 21, count 2 2006.174.01:41:01.73#ibcon#*before return 0, iclass 21, count 2 2006.174.01:41:01.73#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.174.01:41:01.73#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.174.01:41:01.73#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.174.01:41:01.73#ibcon#ireg 7 cls_cnt 0 2006.174.01:41:01.73#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.174.01:41:01.85#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.174.01:41:01.85#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.174.01:41:01.85#ibcon#enter wrdev, iclass 21, count 0 2006.174.01:41:01.85#ibcon#first serial, iclass 21, count 0 2006.174.01:41:01.85#ibcon#enter sib2, iclass 21, count 0 2006.174.01:41:01.85#ibcon#flushed, iclass 21, count 0 2006.174.01:41:01.85#ibcon#about to write, iclass 21, count 0 2006.174.01:41:01.85#ibcon#wrote, iclass 21, count 0 2006.174.01:41:01.85#ibcon#about to read 3, iclass 21, count 0 2006.174.01:41:01.87#ibcon#read 3, iclass 21, count 0 2006.174.01:41:01.87#ibcon#about to read 4, iclass 21, count 0 2006.174.01:41:01.87#ibcon#read 4, iclass 21, count 0 2006.174.01:41:01.87#ibcon#about to read 5, iclass 21, count 0 2006.174.01:41:01.87#ibcon#read 5, iclass 21, count 0 2006.174.01:41:01.87#ibcon#about to read 6, iclass 21, count 0 2006.174.01:41:01.87#ibcon#read 6, iclass 21, count 0 2006.174.01:41:01.87#ibcon#end of sib2, iclass 21, count 0 2006.174.01:41:01.87#ibcon#*mode == 0, iclass 21, count 0 2006.174.01:41:01.87#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.174.01:41:01.87#ibcon#[25=USB\r\n] 2006.174.01:41:01.87#ibcon#*before write, iclass 21, count 0 2006.174.01:41:01.87#ibcon#enter sib2, iclass 21, count 0 2006.174.01:41:01.87#ibcon#flushed, iclass 21, count 0 2006.174.01:41:01.87#ibcon#about to write, iclass 21, count 0 2006.174.01:41:01.87#ibcon#wrote, iclass 21, count 0 2006.174.01:41:01.87#ibcon#about to read 3, iclass 21, count 0 2006.174.01:41:01.90#ibcon#read 3, iclass 21, count 0 2006.174.01:41:01.90#ibcon#about to read 4, iclass 21, count 0 2006.174.01:41:01.90#ibcon#read 4, iclass 21, count 0 2006.174.01:41:01.90#ibcon#about to read 5, iclass 21, count 0 2006.174.01:41:01.90#ibcon#read 5, iclass 21, count 0 2006.174.01:41:01.90#ibcon#about to read 6, iclass 21, count 0 2006.174.01:41:01.90#ibcon#read 6, iclass 21, count 0 2006.174.01:41:01.90#ibcon#end of sib2, iclass 21, count 0 2006.174.01:41:01.90#ibcon#*after write, iclass 21, count 0 2006.174.01:41:01.90#ibcon#*before return 0, iclass 21, count 0 2006.174.01:41:01.90#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.174.01:41:01.90#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.174.01:41:01.90#ibcon#about to clear, iclass 21 cls_cnt 0 2006.174.01:41:01.90#ibcon#cleared, iclass 21 cls_cnt 0 2006.174.01:41:01.90$vck44/vblo=1,629.99 2006.174.01:41:01.90#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.174.01:41:01.90#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.174.01:41:01.90#ibcon#ireg 17 cls_cnt 0 2006.174.01:41:01.90#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.174.01:41:01.90#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.174.01:41:01.90#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.174.01:41:01.90#ibcon#enter wrdev, iclass 23, count 0 2006.174.01:41:01.90#ibcon#first serial, iclass 23, count 0 2006.174.01:41:01.90#ibcon#enter sib2, iclass 23, count 0 2006.174.01:41:01.90#ibcon#flushed, iclass 23, count 0 2006.174.01:41:01.90#ibcon#about to write, iclass 23, count 0 2006.174.01:41:01.90#ibcon#wrote, iclass 23, count 0 2006.174.01:41:01.90#ibcon#about to read 3, iclass 23, count 0 2006.174.01:41:01.92#ibcon#read 3, iclass 23, count 0 2006.174.01:41:01.92#ibcon#about to read 4, iclass 23, count 0 2006.174.01:41:01.92#ibcon#read 4, iclass 23, count 0 2006.174.01:41:01.92#ibcon#about to read 5, iclass 23, count 0 2006.174.01:41:01.92#ibcon#read 5, iclass 23, count 0 2006.174.01:41:01.92#ibcon#about to read 6, iclass 23, count 0 2006.174.01:41:01.92#ibcon#read 6, iclass 23, count 0 2006.174.01:41:01.92#ibcon#end of sib2, iclass 23, count 0 2006.174.01:41:01.92#ibcon#*mode == 0, iclass 23, count 0 2006.174.01:41:01.92#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.174.01:41:01.92#ibcon#[28=FRQ=01,629.99\r\n] 2006.174.01:41:01.92#ibcon#*before write, iclass 23, count 0 2006.174.01:41:01.92#ibcon#enter sib2, iclass 23, count 0 2006.174.01:41:01.92#ibcon#flushed, iclass 23, count 0 2006.174.01:41:01.92#ibcon#about to write, iclass 23, count 0 2006.174.01:41:01.92#ibcon#wrote, iclass 23, count 0 2006.174.01:41:01.92#ibcon#about to read 3, iclass 23, count 0 2006.174.01:41:01.96#ibcon#read 3, iclass 23, count 0 2006.174.01:41:01.96#ibcon#about to read 4, iclass 23, count 0 2006.174.01:41:01.96#ibcon#read 4, iclass 23, count 0 2006.174.01:41:01.96#ibcon#about to read 5, iclass 23, count 0 2006.174.01:41:01.96#ibcon#read 5, iclass 23, count 0 2006.174.01:41:01.96#ibcon#about to read 6, iclass 23, count 0 2006.174.01:41:01.96#ibcon#read 6, iclass 23, count 0 2006.174.01:41:01.96#ibcon#end of sib2, iclass 23, count 0 2006.174.01:41:01.96#ibcon#*after write, iclass 23, count 0 2006.174.01:41:01.96#ibcon#*before return 0, iclass 23, count 0 2006.174.01:41:01.96#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.174.01:41:01.96#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.174.01:41:01.96#ibcon#about to clear, iclass 23 cls_cnt 0 2006.174.01:41:01.96#ibcon#cleared, iclass 23 cls_cnt 0 2006.174.01:41:01.96$vck44/vb=1,4 2006.174.01:41:01.96#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.174.01:41:01.96#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.174.01:41:01.96#ibcon#ireg 11 cls_cnt 2 2006.174.01:41:01.96#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.174.01:41:01.96#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.174.01:41:01.96#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.174.01:41:01.96#ibcon#enter wrdev, iclass 25, count 2 2006.174.01:41:01.96#ibcon#first serial, iclass 25, count 2 2006.174.01:41:01.96#ibcon#enter sib2, iclass 25, count 2 2006.174.01:41:01.96#ibcon#flushed, iclass 25, count 2 2006.174.01:41:01.96#ibcon#about to write, iclass 25, count 2 2006.174.01:41:01.96#ibcon#wrote, iclass 25, count 2 2006.174.01:41:01.96#ibcon#about to read 3, iclass 25, count 2 2006.174.01:41:01.98#ibcon#read 3, iclass 25, count 2 2006.174.01:41:01.98#ibcon#about to read 4, iclass 25, count 2 2006.174.01:41:01.98#ibcon#read 4, iclass 25, count 2 2006.174.01:41:01.98#ibcon#about to read 5, iclass 25, count 2 2006.174.01:41:01.98#ibcon#read 5, iclass 25, count 2 2006.174.01:41:01.98#ibcon#about to read 6, iclass 25, count 2 2006.174.01:41:01.98#ibcon#read 6, iclass 25, count 2 2006.174.01:41:01.98#ibcon#end of sib2, iclass 25, count 2 2006.174.01:41:01.98#ibcon#*mode == 0, iclass 25, count 2 2006.174.01:41:01.98#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.174.01:41:01.98#ibcon#[27=AT01-04\r\n] 2006.174.01:41:01.98#ibcon#*before write, iclass 25, count 2 2006.174.01:41:01.98#ibcon#enter sib2, iclass 25, count 2 2006.174.01:41:01.98#ibcon#flushed, iclass 25, count 2 2006.174.01:41:01.98#ibcon#about to write, iclass 25, count 2 2006.174.01:41:01.98#ibcon#wrote, iclass 25, count 2 2006.174.01:41:01.98#ibcon#about to read 3, iclass 25, count 2 2006.174.01:41:02.01#ibcon#read 3, iclass 25, count 2 2006.174.01:41:02.01#ibcon#about to read 4, iclass 25, count 2 2006.174.01:41:02.01#ibcon#read 4, iclass 25, count 2 2006.174.01:41:02.01#ibcon#about to read 5, iclass 25, count 2 2006.174.01:41:02.01#ibcon#read 5, iclass 25, count 2 2006.174.01:41:02.01#ibcon#about to read 6, iclass 25, count 2 2006.174.01:41:02.01#ibcon#read 6, iclass 25, count 2 2006.174.01:41:02.01#ibcon#end of sib2, iclass 25, count 2 2006.174.01:41:02.01#ibcon#*after write, iclass 25, count 2 2006.174.01:41:02.01#ibcon#*before return 0, iclass 25, count 2 2006.174.01:41:02.01#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.174.01:41:02.01#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.174.01:41:02.01#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.174.01:41:02.01#ibcon#ireg 7 cls_cnt 0 2006.174.01:41:02.01#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.174.01:41:02.13#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.174.01:41:02.13#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.174.01:41:02.13#ibcon#enter wrdev, iclass 25, count 0 2006.174.01:41:02.13#ibcon#first serial, iclass 25, count 0 2006.174.01:41:02.13#ibcon#enter sib2, iclass 25, count 0 2006.174.01:41:02.13#ibcon#flushed, iclass 25, count 0 2006.174.01:41:02.13#ibcon#about to write, iclass 25, count 0 2006.174.01:41:02.13#ibcon#wrote, iclass 25, count 0 2006.174.01:41:02.13#ibcon#about to read 3, iclass 25, count 0 2006.174.01:41:02.15#ibcon#read 3, iclass 25, count 0 2006.174.01:41:02.15#ibcon#about to read 4, iclass 25, count 0 2006.174.01:41:02.15#ibcon#read 4, iclass 25, count 0 2006.174.01:41:02.15#ibcon#about to read 5, iclass 25, count 0 2006.174.01:41:02.15#ibcon#read 5, iclass 25, count 0 2006.174.01:41:02.15#ibcon#about to read 6, iclass 25, count 0 2006.174.01:41:02.15#ibcon#read 6, iclass 25, count 0 2006.174.01:41:02.15#ibcon#end of sib2, iclass 25, count 0 2006.174.01:41:02.15#ibcon#*mode == 0, iclass 25, count 0 2006.174.01:41:02.15#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.174.01:41:02.15#ibcon#[27=USB\r\n] 2006.174.01:41:02.15#ibcon#*before write, iclass 25, count 0 2006.174.01:41:02.15#ibcon#enter sib2, iclass 25, count 0 2006.174.01:41:02.15#ibcon#flushed, iclass 25, count 0 2006.174.01:41:02.15#ibcon#about to write, iclass 25, count 0 2006.174.01:41:02.15#ibcon#wrote, iclass 25, count 0 2006.174.01:41:02.15#ibcon#about to read 3, iclass 25, count 0 2006.174.01:41:02.18#ibcon#read 3, iclass 25, count 0 2006.174.01:41:02.18#ibcon#about to read 4, iclass 25, count 0 2006.174.01:41:02.18#ibcon#read 4, iclass 25, count 0 2006.174.01:41:02.18#ibcon#about to read 5, iclass 25, count 0 2006.174.01:41:02.18#ibcon#read 5, iclass 25, count 0 2006.174.01:41:02.18#ibcon#about to read 6, iclass 25, count 0 2006.174.01:41:02.18#ibcon#read 6, iclass 25, count 0 2006.174.01:41:02.18#ibcon#end of sib2, iclass 25, count 0 2006.174.01:41:02.18#ibcon#*after write, iclass 25, count 0 2006.174.01:41:02.18#ibcon#*before return 0, iclass 25, count 0 2006.174.01:41:02.18#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.174.01:41:02.18#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.174.01:41:02.18#ibcon#about to clear, iclass 25 cls_cnt 0 2006.174.01:41:02.18#ibcon#cleared, iclass 25 cls_cnt 0 2006.174.01:41:02.18$vck44/vblo=2,634.99 2006.174.01:41:02.18#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.174.01:41:02.18#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.174.01:41:02.18#ibcon#ireg 17 cls_cnt 0 2006.174.01:41:02.18#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.174.01:41:02.18#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.174.01:41:02.18#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.174.01:41:02.18#ibcon#enter wrdev, iclass 27, count 0 2006.174.01:41:02.18#ibcon#first serial, iclass 27, count 0 2006.174.01:41:02.18#ibcon#enter sib2, iclass 27, count 0 2006.174.01:41:02.18#ibcon#flushed, iclass 27, count 0 2006.174.01:41:02.18#ibcon#about to write, iclass 27, count 0 2006.174.01:41:02.18#ibcon#wrote, iclass 27, count 0 2006.174.01:41:02.18#ibcon#about to read 3, iclass 27, count 0 2006.174.01:41:02.20#ibcon#read 3, iclass 27, count 0 2006.174.01:41:02.20#ibcon#about to read 4, iclass 27, count 0 2006.174.01:41:02.20#ibcon#read 4, iclass 27, count 0 2006.174.01:41:02.20#ibcon#about to read 5, iclass 27, count 0 2006.174.01:41:02.20#ibcon#read 5, iclass 27, count 0 2006.174.01:41:02.20#ibcon#about to read 6, iclass 27, count 0 2006.174.01:41:02.20#ibcon#read 6, iclass 27, count 0 2006.174.01:41:02.20#ibcon#end of sib2, iclass 27, count 0 2006.174.01:41:02.20#ibcon#*mode == 0, iclass 27, count 0 2006.174.01:41:02.20#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.174.01:41:02.20#ibcon#[28=FRQ=02,634.99\r\n] 2006.174.01:41:02.20#ibcon#*before write, iclass 27, count 0 2006.174.01:41:02.20#ibcon#enter sib2, iclass 27, count 0 2006.174.01:41:02.20#ibcon#flushed, iclass 27, count 0 2006.174.01:41:02.20#ibcon#about to write, iclass 27, count 0 2006.174.01:41:02.20#ibcon#wrote, iclass 27, count 0 2006.174.01:41:02.20#ibcon#about to read 3, iclass 27, count 0 2006.174.01:41:02.24#ibcon#read 3, iclass 27, count 0 2006.174.01:41:02.24#ibcon#about to read 4, iclass 27, count 0 2006.174.01:41:02.24#ibcon#read 4, iclass 27, count 0 2006.174.01:41:02.24#ibcon#about to read 5, iclass 27, count 0 2006.174.01:41:02.24#ibcon#read 5, iclass 27, count 0 2006.174.01:41:02.24#ibcon#about to read 6, iclass 27, count 0 2006.174.01:41:02.24#ibcon#read 6, iclass 27, count 0 2006.174.01:41:02.24#ibcon#end of sib2, iclass 27, count 0 2006.174.01:41:02.24#ibcon#*after write, iclass 27, count 0 2006.174.01:41:02.24#ibcon#*before return 0, iclass 27, count 0 2006.174.01:41:02.24#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.174.01:41:02.24#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.174.01:41:02.24#ibcon#about to clear, iclass 27 cls_cnt 0 2006.174.01:41:02.24#ibcon#cleared, iclass 27 cls_cnt 0 2006.174.01:41:02.24$vck44/vb=2,4 2006.174.01:41:02.24#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.174.01:41:02.24#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.174.01:41:02.24#ibcon#ireg 11 cls_cnt 2 2006.174.01:41:02.24#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.174.01:41:02.30#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.174.01:41:02.30#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.174.01:41:02.30#ibcon#enter wrdev, iclass 29, count 2 2006.174.01:41:02.30#ibcon#first serial, iclass 29, count 2 2006.174.01:41:02.30#ibcon#enter sib2, iclass 29, count 2 2006.174.01:41:02.30#ibcon#flushed, iclass 29, count 2 2006.174.01:41:02.30#ibcon#about to write, iclass 29, count 2 2006.174.01:41:02.30#ibcon#wrote, iclass 29, count 2 2006.174.01:41:02.30#ibcon#about to read 3, iclass 29, count 2 2006.174.01:41:02.32#ibcon#read 3, iclass 29, count 2 2006.174.01:41:02.32#ibcon#about to read 4, iclass 29, count 2 2006.174.01:41:02.32#ibcon#read 4, iclass 29, count 2 2006.174.01:41:02.32#ibcon#about to read 5, iclass 29, count 2 2006.174.01:41:02.32#ibcon#read 5, iclass 29, count 2 2006.174.01:41:02.32#ibcon#about to read 6, iclass 29, count 2 2006.174.01:41:02.32#ibcon#read 6, iclass 29, count 2 2006.174.01:41:02.32#ibcon#end of sib2, iclass 29, count 2 2006.174.01:41:02.32#ibcon#*mode == 0, iclass 29, count 2 2006.174.01:41:02.32#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.174.01:41:02.32#ibcon#[27=AT02-04\r\n] 2006.174.01:41:02.32#ibcon#*before write, iclass 29, count 2 2006.174.01:41:02.32#ibcon#enter sib2, iclass 29, count 2 2006.174.01:41:02.32#ibcon#flushed, iclass 29, count 2 2006.174.01:41:02.32#ibcon#about to write, iclass 29, count 2 2006.174.01:41:02.32#ibcon#wrote, iclass 29, count 2 2006.174.01:41:02.32#ibcon#about to read 3, iclass 29, count 2 2006.174.01:41:02.35#ibcon#read 3, iclass 29, count 2 2006.174.01:41:02.35#ibcon#about to read 4, iclass 29, count 2 2006.174.01:41:02.35#ibcon#read 4, iclass 29, count 2 2006.174.01:41:02.35#ibcon#about to read 5, iclass 29, count 2 2006.174.01:41:02.35#ibcon#read 5, iclass 29, count 2 2006.174.01:41:02.35#ibcon#about to read 6, iclass 29, count 2 2006.174.01:41:02.35#ibcon#read 6, iclass 29, count 2 2006.174.01:41:02.35#ibcon#end of sib2, iclass 29, count 2 2006.174.01:41:02.35#ibcon#*after write, iclass 29, count 2 2006.174.01:41:02.35#ibcon#*before return 0, iclass 29, count 2 2006.174.01:41:02.35#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.174.01:41:02.35#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.174.01:41:02.35#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.174.01:41:02.35#ibcon#ireg 7 cls_cnt 0 2006.174.01:41:02.35#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.174.01:41:02.47#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.174.01:41:02.47#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.174.01:41:02.47#ibcon#enter wrdev, iclass 29, count 0 2006.174.01:41:02.47#ibcon#first serial, iclass 29, count 0 2006.174.01:41:02.47#ibcon#enter sib2, iclass 29, count 0 2006.174.01:41:02.47#ibcon#flushed, iclass 29, count 0 2006.174.01:41:02.47#ibcon#about to write, iclass 29, count 0 2006.174.01:41:02.47#ibcon#wrote, iclass 29, count 0 2006.174.01:41:02.47#ibcon#about to read 3, iclass 29, count 0 2006.174.01:41:02.49#ibcon#read 3, iclass 29, count 0 2006.174.01:41:02.49#ibcon#about to read 4, iclass 29, count 0 2006.174.01:41:02.49#ibcon#read 4, iclass 29, count 0 2006.174.01:41:02.49#ibcon#about to read 5, iclass 29, count 0 2006.174.01:41:02.49#ibcon#read 5, iclass 29, count 0 2006.174.01:41:02.49#ibcon#about to read 6, iclass 29, count 0 2006.174.01:41:02.49#ibcon#read 6, iclass 29, count 0 2006.174.01:41:02.49#ibcon#end of sib2, iclass 29, count 0 2006.174.01:41:02.49#ibcon#*mode == 0, iclass 29, count 0 2006.174.01:41:02.49#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.174.01:41:02.49#ibcon#[27=USB\r\n] 2006.174.01:41:02.49#ibcon#*before write, iclass 29, count 0 2006.174.01:41:02.49#ibcon#enter sib2, iclass 29, count 0 2006.174.01:41:02.49#ibcon#flushed, iclass 29, count 0 2006.174.01:41:02.49#ibcon#about to write, iclass 29, count 0 2006.174.01:41:02.49#ibcon#wrote, iclass 29, count 0 2006.174.01:41:02.49#ibcon#about to read 3, iclass 29, count 0 2006.174.01:41:02.52#ibcon#read 3, iclass 29, count 0 2006.174.01:41:02.52#ibcon#about to read 4, iclass 29, count 0 2006.174.01:41:02.52#ibcon#read 4, iclass 29, count 0 2006.174.01:41:02.52#ibcon#about to read 5, iclass 29, count 0 2006.174.01:41:02.52#ibcon#read 5, iclass 29, count 0 2006.174.01:41:02.52#ibcon#about to read 6, iclass 29, count 0 2006.174.01:41:02.52#ibcon#read 6, iclass 29, count 0 2006.174.01:41:02.52#ibcon#end of sib2, iclass 29, count 0 2006.174.01:41:02.52#ibcon#*after write, iclass 29, count 0 2006.174.01:41:02.52#ibcon#*before return 0, iclass 29, count 0 2006.174.01:41:02.52#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.174.01:41:02.52#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.174.01:41:02.52#ibcon#about to clear, iclass 29 cls_cnt 0 2006.174.01:41:02.52#ibcon#cleared, iclass 29 cls_cnt 0 2006.174.01:41:02.52$vck44/vblo=3,649.99 2006.174.01:41:02.52#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.174.01:41:02.52#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.174.01:41:02.52#ibcon#ireg 17 cls_cnt 0 2006.174.01:41:02.52#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.174.01:41:02.52#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.174.01:41:02.52#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.174.01:41:02.52#ibcon#enter wrdev, iclass 31, count 0 2006.174.01:41:02.52#ibcon#first serial, iclass 31, count 0 2006.174.01:41:02.52#ibcon#enter sib2, iclass 31, count 0 2006.174.01:41:02.52#ibcon#flushed, iclass 31, count 0 2006.174.01:41:02.52#ibcon#about to write, iclass 31, count 0 2006.174.01:41:02.52#ibcon#wrote, iclass 31, count 0 2006.174.01:41:02.52#ibcon#about to read 3, iclass 31, count 0 2006.174.01:41:02.54#ibcon#read 3, iclass 31, count 0 2006.174.01:41:02.54#ibcon#about to read 4, iclass 31, count 0 2006.174.01:41:02.54#ibcon#read 4, iclass 31, count 0 2006.174.01:41:02.54#ibcon#about to read 5, iclass 31, count 0 2006.174.01:41:02.54#ibcon#read 5, iclass 31, count 0 2006.174.01:41:02.54#ibcon#about to read 6, iclass 31, count 0 2006.174.01:41:02.54#ibcon#read 6, iclass 31, count 0 2006.174.01:41:02.54#ibcon#end of sib2, iclass 31, count 0 2006.174.01:41:02.54#ibcon#*mode == 0, iclass 31, count 0 2006.174.01:41:02.54#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.174.01:41:02.54#ibcon#[28=FRQ=03,649.99\r\n] 2006.174.01:41:02.54#ibcon#*before write, iclass 31, count 0 2006.174.01:41:02.54#ibcon#enter sib2, iclass 31, count 0 2006.174.01:41:02.54#ibcon#flushed, iclass 31, count 0 2006.174.01:41:02.54#ibcon#about to write, iclass 31, count 0 2006.174.01:41:02.54#ibcon#wrote, iclass 31, count 0 2006.174.01:41:02.54#ibcon#about to read 3, iclass 31, count 0 2006.174.01:41:02.58#ibcon#read 3, iclass 31, count 0 2006.174.01:41:02.58#ibcon#about to read 4, iclass 31, count 0 2006.174.01:41:02.58#ibcon#read 4, iclass 31, count 0 2006.174.01:41:02.58#ibcon#about to read 5, iclass 31, count 0 2006.174.01:41:02.58#ibcon#read 5, iclass 31, count 0 2006.174.01:41:02.58#ibcon#about to read 6, iclass 31, count 0 2006.174.01:41:02.58#ibcon#read 6, iclass 31, count 0 2006.174.01:41:02.58#ibcon#end of sib2, iclass 31, count 0 2006.174.01:41:02.58#ibcon#*after write, iclass 31, count 0 2006.174.01:41:02.58#ibcon#*before return 0, iclass 31, count 0 2006.174.01:41:02.58#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.174.01:41:02.58#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.174.01:41:02.58#ibcon#about to clear, iclass 31 cls_cnt 0 2006.174.01:41:02.58#ibcon#cleared, iclass 31 cls_cnt 0 2006.174.01:41:02.58$vck44/vb=3,4 2006.174.01:41:02.58#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.174.01:41:02.58#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.174.01:41:02.58#ibcon#ireg 11 cls_cnt 2 2006.174.01:41:02.58#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.174.01:41:02.64#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.174.01:41:02.64#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.174.01:41:02.64#ibcon#enter wrdev, iclass 33, count 2 2006.174.01:41:02.64#ibcon#first serial, iclass 33, count 2 2006.174.01:41:02.64#ibcon#enter sib2, iclass 33, count 2 2006.174.01:41:02.64#ibcon#flushed, iclass 33, count 2 2006.174.01:41:02.64#ibcon#about to write, iclass 33, count 2 2006.174.01:41:02.64#ibcon#wrote, iclass 33, count 2 2006.174.01:41:02.64#ibcon#about to read 3, iclass 33, count 2 2006.174.01:41:02.70#ibcon#read 3, iclass 33, count 2 2006.174.01:41:02.70#ibcon#about to read 4, iclass 33, count 2 2006.174.01:41:02.70#ibcon#read 4, iclass 33, count 2 2006.174.01:41:02.70#ibcon#about to read 5, iclass 33, count 2 2006.174.01:41:02.70#ibcon#read 5, iclass 33, count 2 2006.174.01:41:02.70#ibcon#about to read 6, iclass 33, count 2 2006.174.01:41:02.70#ibcon#read 6, iclass 33, count 2 2006.174.01:41:02.70#ibcon#end of sib2, iclass 33, count 2 2006.174.01:41:02.70#ibcon#*mode == 0, iclass 33, count 2 2006.174.01:41:02.70#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.174.01:41:02.70#ibcon#[27=AT03-04\r\n] 2006.174.01:41:02.70#ibcon#*before write, iclass 33, count 2 2006.174.01:41:02.70#ibcon#enter sib2, iclass 33, count 2 2006.174.01:41:02.70#ibcon#flushed, iclass 33, count 2 2006.174.01:41:02.70#ibcon#about to write, iclass 33, count 2 2006.174.01:41:02.70#ibcon#wrote, iclass 33, count 2 2006.174.01:41:02.70#ibcon#about to read 3, iclass 33, count 2 2006.174.01:41:02.73#ibcon#read 3, iclass 33, count 2 2006.174.01:41:02.73#ibcon#about to read 4, iclass 33, count 2 2006.174.01:41:02.73#ibcon#read 4, iclass 33, count 2 2006.174.01:41:02.73#ibcon#about to read 5, iclass 33, count 2 2006.174.01:41:02.73#ibcon#read 5, iclass 33, count 2 2006.174.01:41:02.73#ibcon#about to read 6, iclass 33, count 2 2006.174.01:41:02.73#ibcon#read 6, iclass 33, count 2 2006.174.01:41:02.73#ibcon#end of sib2, iclass 33, count 2 2006.174.01:41:02.73#ibcon#*after write, iclass 33, count 2 2006.174.01:41:02.73#ibcon#*before return 0, iclass 33, count 2 2006.174.01:41:02.73#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.174.01:41:02.73#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.174.01:41:02.73#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.174.01:41:02.73#ibcon#ireg 7 cls_cnt 0 2006.174.01:41:02.73#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.174.01:41:02.85#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.174.01:41:02.85#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.174.01:41:02.85#ibcon#enter wrdev, iclass 33, count 0 2006.174.01:41:02.85#ibcon#first serial, iclass 33, count 0 2006.174.01:41:02.85#ibcon#enter sib2, iclass 33, count 0 2006.174.01:41:02.85#ibcon#flushed, iclass 33, count 0 2006.174.01:41:02.85#ibcon#about to write, iclass 33, count 0 2006.174.01:41:02.85#ibcon#wrote, iclass 33, count 0 2006.174.01:41:02.85#ibcon#about to read 3, iclass 33, count 0 2006.174.01:41:02.87#ibcon#read 3, iclass 33, count 0 2006.174.01:41:02.87#ibcon#about to read 4, iclass 33, count 0 2006.174.01:41:02.87#ibcon#read 4, iclass 33, count 0 2006.174.01:41:02.87#ibcon#about to read 5, iclass 33, count 0 2006.174.01:41:02.87#ibcon#read 5, iclass 33, count 0 2006.174.01:41:02.87#ibcon#about to read 6, iclass 33, count 0 2006.174.01:41:02.87#ibcon#read 6, iclass 33, count 0 2006.174.01:41:02.87#ibcon#end of sib2, iclass 33, count 0 2006.174.01:41:02.87#ibcon#*mode == 0, iclass 33, count 0 2006.174.01:41:02.87#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.174.01:41:02.87#ibcon#[27=USB\r\n] 2006.174.01:41:02.87#ibcon#*before write, iclass 33, count 0 2006.174.01:41:02.87#ibcon#enter sib2, iclass 33, count 0 2006.174.01:41:02.87#ibcon#flushed, iclass 33, count 0 2006.174.01:41:02.87#ibcon#about to write, iclass 33, count 0 2006.174.01:41:02.87#ibcon#wrote, iclass 33, count 0 2006.174.01:41:02.87#ibcon#about to read 3, iclass 33, count 0 2006.174.01:41:02.90#ibcon#read 3, iclass 33, count 0 2006.174.01:41:02.90#ibcon#about to read 4, iclass 33, count 0 2006.174.01:41:02.90#ibcon#read 4, iclass 33, count 0 2006.174.01:41:02.90#ibcon#about to read 5, iclass 33, count 0 2006.174.01:41:02.90#ibcon#read 5, iclass 33, count 0 2006.174.01:41:02.90#ibcon#about to read 6, iclass 33, count 0 2006.174.01:41:02.90#ibcon#read 6, iclass 33, count 0 2006.174.01:41:02.90#ibcon#end of sib2, iclass 33, count 0 2006.174.01:41:02.90#ibcon#*after write, iclass 33, count 0 2006.174.01:41:02.90#ibcon#*before return 0, iclass 33, count 0 2006.174.01:41:02.90#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.174.01:41:02.90#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.174.01:41:02.90#ibcon#about to clear, iclass 33 cls_cnt 0 2006.174.01:41:02.90#ibcon#cleared, iclass 33 cls_cnt 0 2006.174.01:41:02.90$vck44/vblo=4,679.99 2006.174.01:41:02.90#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.174.01:41:02.90#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.174.01:41:02.90#ibcon#ireg 17 cls_cnt 0 2006.174.01:41:02.90#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.174.01:41:02.90#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.174.01:41:02.90#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.174.01:41:02.90#ibcon#enter wrdev, iclass 35, count 0 2006.174.01:41:02.90#ibcon#first serial, iclass 35, count 0 2006.174.01:41:02.90#ibcon#enter sib2, iclass 35, count 0 2006.174.01:41:02.90#ibcon#flushed, iclass 35, count 0 2006.174.01:41:02.90#ibcon#about to write, iclass 35, count 0 2006.174.01:41:02.90#ibcon#wrote, iclass 35, count 0 2006.174.01:41:02.90#ibcon#about to read 3, iclass 35, count 0 2006.174.01:41:02.92#ibcon#read 3, iclass 35, count 0 2006.174.01:41:02.92#ibcon#about to read 4, iclass 35, count 0 2006.174.01:41:02.92#ibcon#read 4, iclass 35, count 0 2006.174.01:41:02.92#ibcon#about to read 5, iclass 35, count 0 2006.174.01:41:02.92#ibcon#read 5, iclass 35, count 0 2006.174.01:41:02.92#ibcon#about to read 6, iclass 35, count 0 2006.174.01:41:02.92#ibcon#read 6, iclass 35, count 0 2006.174.01:41:02.92#ibcon#end of sib2, iclass 35, count 0 2006.174.01:41:02.92#ibcon#*mode == 0, iclass 35, count 0 2006.174.01:41:02.92#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.174.01:41:02.92#ibcon#[28=FRQ=04,679.99\r\n] 2006.174.01:41:02.92#ibcon#*before write, iclass 35, count 0 2006.174.01:41:02.92#ibcon#enter sib2, iclass 35, count 0 2006.174.01:41:02.92#ibcon#flushed, iclass 35, count 0 2006.174.01:41:02.92#ibcon#about to write, iclass 35, count 0 2006.174.01:41:02.92#ibcon#wrote, iclass 35, count 0 2006.174.01:41:02.92#ibcon#about to read 3, iclass 35, count 0 2006.174.01:41:02.96#ibcon#read 3, iclass 35, count 0 2006.174.01:41:02.96#ibcon#about to read 4, iclass 35, count 0 2006.174.01:41:02.96#ibcon#read 4, iclass 35, count 0 2006.174.01:41:02.96#ibcon#about to read 5, iclass 35, count 0 2006.174.01:41:02.96#ibcon#read 5, iclass 35, count 0 2006.174.01:41:02.96#ibcon#about to read 6, iclass 35, count 0 2006.174.01:41:02.96#ibcon#read 6, iclass 35, count 0 2006.174.01:41:02.96#ibcon#end of sib2, iclass 35, count 0 2006.174.01:41:02.96#ibcon#*after write, iclass 35, count 0 2006.174.01:41:02.96#ibcon#*before return 0, iclass 35, count 0 2006.174.01:41:02.96#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.174.01:41:02.96#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.174.01:41:02.96#ibcon#about to clear, iclass 35 cls_cnt 0 2006.174.01:41:02.96#ibcon#cleared, iclass 35 cls_cnt 0 2006.174.01:41:02.96$vck44/vb=4,4 2006.174.01:41:02.96#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.174.01:41:02.96#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.174.01:41:02.96#ibcon#ireg 11 cls_cnt 2 2006.174.01:41:02.96#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.174.01:41:03.02#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.174.01:41:03.02#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.174.01:41:03.02#ibcon#enter wrdev, iclass 37, count 2 2006.174.01:41:03.02#ibcon#first serial, iclass 37, count 2 2006.174.01:41:03.02#ibcon#enter sib2, iclass 37, count 2 2006.174.01:41:03.02#ibcon#flushed, iclass 37, count 2 2006.174.01:41:03.02#ibcon#about to write, iclass 37, count 2 2006.174.01:41:03.02#ibcon#wrote, iclass 37, count 2 2006.174.01:41:03.02#ibcon#about to read 3, iclass 37, count 2 2006.174.01:41:03.04#ibcon#read 3, iclass 37, count 2 2006.174.01:41:03.04#ibcon#about to read 4, iclass 37, count 2 2006.174.01:41:03.04#ibcon#read 4, iclass 37, count 2 2006.174.01:41:03.04#ibcon#about to read 5, iclass 37, count 2 2006.174.01:41:03.04#ibcon#read 5, iclass 37, count 2 2006.174.01:41:03.04#ibcon#about to read 6, iclass 37, count 2 2006.174.01:41:03.04#ibcon#read 6, iclass 37, count 2 2006.174.01:41:03.04#ibcon#end of sib2, iclass 37, count 2 2006.174.01:41:03.04#ibcon#*mode == 0, iclass 37, count 2 2006.174.01:41:03.04#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.174.01:41:03.04#ibcon#[27=AT04-04\r\n] 2006.174.01:41:03.04#ibcon#*before write, iclass 37, count 2 2006.174.01:41:03.04#ibcon#enter sib2, iclass 37, count 2 2006.174.01:41:03.04#ibcon#flushed, iclass 37, count 2 2006.174.01:41:03.04#ibcon#about to write, iclass 37, count 2 2006.174.01:41:03.04#ibcon#wrote, iclass 37, count 2 2006.174.01:41:03.04#ibcon#about to read 3, iclass 37, count 2 2006.174.01:41:03.07#ibcon#read 3, iclass 37, count 2 2006.174.01:41:03.07#ibcon#about to read 4, iclass 37, count 2 2006.174.01:41:03.07#ibcon#read 4, iclass 37, count 2 2006.174.01:41:03.07#ibcon#about to read 5, iclass 37, count 2 2006.174.01:41:03.07#ibcon#read 5, iclass 37, count 2 2006.174.01:41:03.07#ibcon#about to read 6, iclass 37, count 2 2006.174.01:41:03.07#ibcon#read 6, iclass 37, count 2 2006.174.01:41:03.07#ibcon#end of sib2, iclass 37, count 2 2006.174.01:41:03.07#ibcon#*after write, iclass 37, count 2 2006.174.01:41:03.07#ibcon#*before return 0, iclass 37, count 2 2006.174.01:41:03.07#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.174.01:41:03.07#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.174.01:41:03.07#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.174.01:41:03.07#ibcon#ireg 7 cls_cnt 0 2006.174.01:41:03.07#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.174.01:41:03.19#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.174.01:41:03.19#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.174.01:41:03.19#ibcon#enter wrdev, iclass 37, count 0 2006.174.01:41:03.19#ibcon#first serial, iclass 37, count 0 2006.174.01:41:03.19#ibcon#enter sib2, iclass 37, count 0 2006.174.01:41:03.19#ibcon#flushed, iclass 37, count 0 2006.174.01:41:03.19#ibcon#about to write, iclass 37, count 0 2006.174.01:41:03.19#ibcon#wrote, iclass 37, count 0 2006.174.01:41:03.19#ibcon#about to read 3, iclass 37, count 0 2006.174.01:41:03.21#ibcon#read 3, iclass 37, count 0 2006.174.01:41:03.21#ibcon#about to read 4, iclass 37, count 0 2006.174.01:41:03.21#ibcon#read 4, iclass 37, count 0 2006.174.01:41:03.21#ibcon#about to read 5, iclass 37, count 0 2006.174.01:41:03.21#ibcon#read 5, iclass 37, count 0 2006.174.01:41:03.21#ibcon#about to read 6, iclass 37, count 0 2006.174.01:41:03.21#ibcon#read 6, iclass 37, count 0 2006.174.01:41:03.21#ibcon#end of sib2, iclass 37, count 0 2006.174.01:41:03.21#ibcon#*mode == 0, iclass 37, count 0 2006.174.01:41:03.21#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.174.01:41:03.21#ibcon#[27=USB\r\n] 2006.174.01:41:03.21#ibcon#*before write, iclass 37, count 0 2006.174.01:41:03.21#ibcon#enter sib2, iclass 37, count 0 2006.174.01:41:03.21#ibcon#flushed, iclass 37, count 0 2006.174.01:41:03.21#ibcon#about to write, iclass 37, count 0 2006.174.01:41:03.21#ibcon#wrote, iclass 37, count 0 2006.174.01:41:03.21#ibcon#about to read 3, iclass 37, count 0 2006.174.01:41:03.24#ibcon#read 3, iclass 37, count 0 2006.174.01:41:03.24#ibcon#about to read 4, iclass 37, count 0 2006.174.01:41:03.24#ibcon#read 4, iclass 37, count 0 2006.174.01:41:03.24#ibcon#about to read 5, iclass 37, count 0 2006.174.01:41:03.24#ibcon#read 5, iclass 37, count 0 2006.174.01:41:03.24#ibcon#about to read 6, iclass 37, count 0 2006.174.01:41:03.24#ibcon#read 6, iclass 37, count 0 2006.174.01:41:03.24#ibcon#end of sib2, iclass 37, count 0 2006.174.01:41:03.24#ibcon#*after write, iclass 37, count 0 2006.174.01:41:03.24#ibcon#*before return 0, iclass 37, count 0 2006.174.01:41:03.24#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.174.01:41:03.24#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.174.01:41:03.24#ibcon#about to clear, iclass 37 cls_cnt 0 2006.174.01:41:03.24#ibcon#cleared, iclass 37 cls_cnt 0 2006.174.01:41:03.24$vck44/vblo=5,709.99 2006.174.01:41:03.24#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.174.01:41:03.24#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.174.01:41:03.24#ibcon#ireg 17 cls_cnt 0 2006.174.01:41:03.24#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.174.01:41:03.24#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.174.01:41:03.24#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.174.01:41:03.24#ibcon#enter wrdev, iclass 39, count 0 2006.174.01:41:03.24#ibcon#first serial, iclass 39, count 0 2006.174.01:41:03.24#ibcon#enter sib2, iclass 39, count 0 2006.174.01:41:03.24#ibcon#flushed, iclass 39, count 0 2006.174.01:41:03.24#ibcon#about to write, iclass 39, count 0 2006.174.01:41:03.24#ibcon#wrote, iclass 39, count 0 2006.174.01:41:03.24#ibcon#about to read 3, iclass 39, count 0 2006.174.01:41:03.26#ibcon#read 3, iclass 39, count 0 2006.174.01:41:03.26#ibcon#about to read 4, iclass 39, count 0 2006.174.01:41:03.26#ibcon#read 4, iclass 39, count 0 2006.174.01:41:03.26#ibcon#about to read 5, iclass 39, count 0 2006.174.01:41:03.26#ibcon#read 5, iclass 39, count 0 2006.174.01:41:03.26#ibcon#about to read 6, iclass 39, count 0 2006.174.01:41:03.26#ibcon#read 6, iclass 39, count 0 2006.174.01:41:03.26#ibcon#end of sib2, iclass 39, count 0 2006.174.01:41:03.26#ibcon#*mode == 0, iclass 39, count 0 2006.174.01:41:03.26#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.174.01:41:03.26#ibcon#[28=FRQ=05,709.99\r\n] 2006.174.01:41:03.26#ibcon#*before write, iclass 39, count 0 2006.174.01:41:03.26#ibcon#enter sib2, iclass 39, count 0 2006.174.01:41:03.26#ibcon#flushed, iclass 39, count 0 2006.174.01:41:03.26#ibcon#about to write, iclass 39, count 0 2006.174.01:41:03.26#ibcon#wrote, iclass 39, count 0 2006.174.01:41:03.26#ibcon#about to read 3, iclass 39, count 0 2006.174.01:41:03.30#ibcon#read 3, iclass 39, count 0 2006.174.01:41:03.30#ibcon#about to read 4, iclass 39, count 0 2006.174.01:41:03.30#ibcon#read 4, iclass 39, count 0 2006.174.01:41:03.30#ibcon#about to read 5, iclass 39, count 0 2006.174.01:41:03.30#ibcon#read 5, iclass 39, count 0 2006.174.01:41:03.30#ibcon#about to read 6, iclass 39, count 0 2006.174.01:41:03.30#ibcon#read 6, iclass 39, count 0 2006.174.01:41:03.30#ibcon#end of sib2, iclass 39, count 0 2006.174.01:41:03.30#ibcon#*after write, iclass 39, count 0 2006.174.01:41:03.30#ibcon#*before return 0, iclass 39, count 0 2006.174.01:41:03.30#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.174.01:41:03.30#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.174.01:41:03.30#ibcon#about to clear, iclass 39 cls_cnt 0 2006.174.01:41:03.30#ibcon#cleared, iclass 39 cls_cnt 0 2006.174.01:41:03.30$vck44/vb=5,4 2006.174.01:41:03.30#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.174.01:41:03.30#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.174.01:41:03.30#ibcon#ireg 11 cls_cnt 2 2006.174.01:41:03.30#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.174.01:41:03.36#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.174.01:41:03.36#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.174.01:41:03.36#ibcon#enter wrdev, iclass 3, count 2 2006.174.01:41:03.36#ibcon#first serial, iclass 3, count 2 2006.174.01:41:03.36#ibcon#enter sib2, iclass 3, count 2 2006.174.01:41:03.36#ibcon#flushed, iclass 3, count 2 2006.174.01:41:03.36#ibcon#about to write, iclass 3, count 2 2006.174.01:41:03.36#ibcon#wrote, iclass 3, count 2 2006.174.01:41:03.36#ibcon#about to read 3, iclass 3, count 2 2006.174.01:41:03.38#ibcon#read 3, iclass 3, count 2 2006.174.01:41:03.38#ibcon#about to read 4, iclass 3, count 2 2006.174.01:41:03.38#ibcon#read 4, iclass 3, count 2 2006.174.01:41:03.38#ibcon#about to read 5, iclass 3, count 2 2006.174.01:41:03.38#ibcon#read 5, iclass 3, count 2 2006.174.01:41:03.38#ibcon#about to read 6, iclass 3, count 2 2006.174.01:41:03.38#ibcon#read 6, iclass 3, count 2 2006.174.01:41:03.38#ibcon#end of sib2, iclass 3, count 2 2006.174.01:41:03.38#ibcon#*mode == 0, iclass 3, count 2 2006.174.01:41:03.38#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.174.01:41:03.38#ibcon#[27=AT05-04\r\n] 2006.174.01:41:03.38#ibcon#*before write, iclass 3, count 2 2006.174.01:41:03.38#ibcon#enter sib2, iclass 3, count 2 2006.174.01:41:03.38#ibcon#flushed, iclass 3, count 2 2006.174.01:41:03.38#ibcon#about to write, iclass 3, count 2 2006.174.01:41:03.38#ibcon#wrote, iclass 3, count 2 2006.174.01:41:03.38#ibcon#about to read 3, iclass 3, count 2 2006.174.01:41:03.41#ibcon#read 3, iclass 3, count 2 2006.174.01:41:03.41#ibcon#about to read 4, iclass 3, count 2 2006.174.01:41:03.41#ibcon#read 4, iclass 3, count 2 2006.174.01:41:03.41#ibcon#about to read 5, iclass 3, count 2 2006.174.01:41:03.41#ibcon#read 5, iclass 3, count 2 2006.174.01:41:03.41#ibcon#about to read 6, iclass 3, count 2 2006.174.01:41:03.41#ibcon#read 6, iclass 3, count 2 2006.174.01:41:03.41#ibcon#end of sib2, iclass 3, count 2 2006.174.01:41:03.41#ibcon#*after write, iclass 3, count 2 2006.174.01:41:03.41#ibcon#*before return 0, iclass 3, count 2 2006.174.01:41:03.41#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.174.01:41:03.41#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.174.01:41:03.41#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.174.01:41:03.41#ibcon#ireg 7 cls_cnt 0 2006.174.01:41:03.41#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.174.01:41:03.53#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.174.01:41:03.53#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.174.01:41:03.53#ibcon#enter wrdev, iclass 3, count 0 2006.174.01:41:03.53#ibcon#first serial, iclass 3, count 0 2006.174.01:41:03.53#ibcon#enter sib2, iclass 3, count 0 2006.174.01:41:03.53#ibcon#flushed, iclass 3, count 0 2006.174.01:41:03.53#ibcon#about to write, iclass 3, count 0 2006.174.01:41:03.53#ibcon#wrote, iclass 3, count 0 2006.174.01:41:03.53#ibcon#about to read 3, iclass 3, count 0 2006.174.01:41:03.55#ibcon#read 3, iclass 3, count 0 2006.174.01:41:03.55#ibcon#about to read 4, iclass 3, count 0 2006.174.01:41:03.55#ibcon#read 4, iclass 3, count 0 2006.174.01:41:03.55#ibcon#about to read 5, iclass 3, count 0 2006.174.01:41:03.55#ibcon#read 5, iclass 3, count 0 2006.174.01:41:03.55#ibcon#about to read 6, iclass 3, count 0 2006.174.01:41:03.55#ibcon#read 6, iclass 3, count 0 2006.174.01:41:03.55#ibcon#end of sib2, iclass 3, count 0 2006.174.01:41:03.55#ibcon#*mode == 0, iclass 3, count 0 2006.174.01:41:03.55#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.174.01:41:03.55#ibcon#[27=USB\r\n] 2006.174.01:41:03.55#ibcon#*before write, iclass 3, count 0 2006.174.01:41:03.55#ibcon#enter sib2, iclass 3, count 0 2006.174.01:41:03.55#ibcon#flushed, iclass 3, count 0 2006.174.01:41:03.55#ibcon#about to write, iclass 3, count 0 2006.174.01:41:03.55#ibcon#wrote, iclass 3, count 0 2006.174.01:41:03.55#ibcon#about to read 3, iclass 3, count 0 2006.174.01:41:03.58#ibcon#read 3, iclass 3, count 0 2006.174.01:41:03.58#ibcon#about to read 4, iclass 3, count 0 2006.174.01:41:03.58#ibcon#read 4, iclass 3, count 0 2006.174.01:41:03.58#ibcon#about to read 5, iclass 3, count 0 2006.174.01:41:03.58#ibcon#read 5, iclass 3, count 0 2006.174.01:41:03.58#ibcon#about to read 6, iclass 3, count 0 2006.174.01:41:03.58#ibcon#read 6, iclass 3, count 0 2006.174.01:41:03.58#ibcon#end of sib2, iclass 3, count 0 2006.174.01:41:03.58#ibcon#*after write, iclass 3, count 0 2006.174.01:41:03.58#ibcon#*before return 0, iclass 3, count 0 2006.174.01:41:03.58#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.174.01:41:03.58#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.174.01:41:03.58#ibcon#about to clear, iclass 3 cls_cnt 0 2006.174.01:41:03.58#ibcon#cleared, iclass 3 cls_cnt 0 2006.174.01:41:03.58$vck44/vblo=6,719.99 2006.174.01:41:03.58#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.174.01:41:03.58#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.174.01:41:03.58#ibcon#ireg 17 cls_cnt 0 2006.174.01:41:03.58#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.174.01:41:03.58#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.174.01:41:03.58#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.174.01:41:03.58#ibcon#enter wrdev, iclass 5, count 0 2006.174.01:41:03.58#ibcon#first serial, iclass 5, count 0 2006.174.01:41:03.58#ibcon#enter sib2, iclass 5, count 0 2006.174.01:41:03.58#ibcon#flushed, iclass 5, count 0 2006.174.01:41:03.58#ibcon#about to write, iclass 5, count 0 2006.174.01:41:03.58#ibcon#wrote, iclass 5, count 0 2006.174.01:41:03.58#ibcon#about to read 3, iclass 5, count 0 2006.174.01:41:03.60#ibcon#read 3, iclass 5, count 0 2006.174.01:41:03.60#ibcon#about to read 4, iclass 5, count 0 2006.174.01:41:03.60#ibcon#read 4, iclass 5, count 0 2006.174.01:41:03.60#ibcon#about to read 5, iclass 5, count 0 2006.174.01:41:03.60#ibcon#read 5, iclass 5, count 0 2006.174.01:41:03.60#ibcon#about to read 6, iclass 5, count 0 2006.174.01:41:03.60#ibcon#read 6, iclass 5, count 0 2006.174.01:41:03.60#ibcon#end of sib2, iclass 5, count 0 2006.174.01:41:03.60#ibcon#*mode == 0, iclass 5, count 0 2006.174.01:41:03.60#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.174.01:41:03.60#ibcon#[28=FRQ=06,719.99\r\n] 2006.174.01:41:03.60#ibcon#*before write, iclass 5, count 0 2006.174.01:41:03.60#ibcon#enter sib2, iclass 5, count 0 2006.174.01:41:03.60#ibcon#flushed, iclass 5, count 0 2006.174.01:41:03.60#ibcon#about to write, iclass 5, count 0 2006.174.01:41:03.60#ibcon#wrote, iclass 5, count 0 2006.174.01:41:03.60#ibcon#about to read 3, iclass 5, count 0 2006.174.01:41:03.64#ibcon#read 3, iclass 5, count 0 2006.174.01:41:03.64#ibcon#about to read 4, iclass 5, count 0 2006.174.01:41:03.64#ibcon#read 4, iclass 5, count 0 2006.174.01:41:03.64#ibcon#about to read 5, iclass 5, count 0 2006.174.01:41:03.64#ibcon#read 5, iclass 5, count 0 2006.174.01:41:03.64#ibcon#about to read 6, iclass 5, count 0 2006.174.01:41:03.64#ibcon#read 6, iclass 5, count 0 2006.174.01:41:03.64#ibcon#end of sib2, iclass 5, count 0 2006.174.01:41:03.64#ibcon#*after write, iclass 5, count 0 2006.174.01:41:03.64#ibcon#*before return 0, iclass 5, count 0 2006.174.01:41:03.64#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.174.01:41:03.64#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.174.01:41:03.64#ibcon#about to clear, iclass 5 cls_cnt 0 2006.174.01:41:03.64#ibcon#cleared, iclass 5 cls_cnt 0 2006.174.01:41:03.64$vck44/vb=6,4 2006.174.01:41:03.64#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.174.01:41:03.64#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.174.01:41:03.64#ibcon#ireg 11 cls_cnt 2 2006.174.01:41:03.64#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.174.01:41:03.70#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.174.01:41:03.70#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.174.01:41:03.70#ibcon#enter wrdev, iclass 7, count 2 2006.174.01:41:03.70#ibcon#first serial, iclass 7, count 2 2006.174.01:41:03.70#ibcon#enter sib2, iclass 7, count 2 2006.174.01:41:03.70#ibcon#flushed, iclass 7, count 2 2006.174.01:41:03.70#ibcon#about to write, iclass 7, count 2 2006.174.01:41:03.70#ibcon#wrote, iclass 7, count 2 2006.174.01:41:03.70#ibcon#about to read 3, iclass 7, count 2 2006.174.01:41:03.72#ibcon#read 3, iclass 7, count 2 2006.174.01:41:03.72#ibcon#about to read 4, iclass 7, count 2 2006.174.01:41:03.72#ibcon#read 4, iclass 7, count 2 2006.174.01:41:03.72#ibcon#about to read 5, iclass 7, count 2 2006.174.01:41:03.72#ibcon#read 5, iclass 7, count 2 2006.174.01:41:03.72#ibcon#about to read 6, iclass 7, count 2 2006.174.01:41:03.72#ibcon#read 6, iclass 7, count 2 2006.174.01:41:03.72#ibcon#end of sib2, iclass 7, count 2 2006.174.01:41:03.72#ibcon#*mode == 0, iclass 7, count 2 2006.174.01:41:03.72#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.174.01:41:03.72#ibcon#[27=AT06-04\r\n] 2006.174.01:41:03.72#ibcon#*before write, iclass 7, count 2 2006.174.01:41:03.72#ibcon#enter sib2, iclass 7, count 2 2006.174.01:41:03.72#ibcon#flushed, iclass 7, count 2 2006.174.01:41:03.72#ibcon#about to write, iclass 7, count 2 2006.174.01:41:03.72#ibcon#wrote, iclass 7, count 2 2006.174.01:41:03.72#ibcon#about to read 3, iclass 7, count 2 2006.174.01:41:03.75#ibcon#read 3, iclass 7, count 2 2006.174.01:41:03.75#ibcon#about to read 4, iclass 7, count 2 2006.174.01:41:03.75#ibcon#read 4, iclass 7, count 2 2006.174.01:41:03.75#ibcon#about to read 5, iclass 7, count 2 2006.174.01:41:03.75#ibcon#read 5, iclass 7, count 2 2006.174.01:41:03.75#ibcon#about to read 6, iclass 7, count 2 2006.174.01:41:03.75#ibcon#read 6, iclass 7, count 2 2006.174.01:41:03.75#ibcon#end of sib2, iclass 7, count 2 2006.174.01:41:03.75#ibcon#*after write, iclass 7, count 2 2006.174.01:41:03.75#ibcon#*before return 0, iclass 7, count 2 2006.174.01:41:03.75#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.174.01:41:03.75#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.174.01:41:03.75#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.174.01:41:03.75#ibcon#ireg 7 cls_cnt 0 2006.174.01:41:03.75#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.174.01:41:03.87#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.174.01:41:03.87#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.174.01:41:03.87#ibcon#enter wrdev, iclass 7, count 0 2006.174.01:41:03.87#ibcon#first serial, iclass 7, count 0 2006.174.01:41:03.87#ibcon#enter sib2, iclass 7, count 0 2006.174.01:41:03.87#ibcon#flushed, iclass 7, count 0 2006.174.01:41:03.87#ibcon#about to write, iclass 7, count 0 2006.174.01:41:03.87#ibcon#wrote, iclass 7, count 0 2006.174.01:41:03.87#ibcon#about to read 3, iclass 7, count 0 2006.174.01:41:03.89#ibcon#read 3, iclass 7, count 0 2006.174.01:41:03.89#ibcon#about to read 4, iclass 7, count 0 2006.174.01:41:03.89#ibcon#read 4, iclass 7, count 0 2006.174.01:41:03.89#ibcon#about to read 5, iclass 7, count 0 2006.174.01:41:03.89#ibcon#read 5, iclass 7, count 0 2006.174.01:41:03.89#ibcon#about to read 6, iclass 7, count 0 2006.174.01:41:03.89#ibcon#read 6, iclass 7, count 0 2006.174.01:41:03.89#ibcon#end of sib2, iclass 7, count 0 2006.174.01:41:03.89#ibcon#*mode == 0, iclass 7, count 0 2006.174.01:41:03.89#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.174.01:41:03.89#ibcon#[27=USB\r\n] 2006.174.01:41:03.89#ibcon#*before write, iclass 7, count 0 2006.174.01:41:03.89#ibcon#enter sib2, iclass 7, count 0 2006.174.01:41:03.89#ibcon#flushed, iclass 7, count 0 2006.174.01:41:03.89#ibcon#about to write, iclass 7, count 0 2006.174.01:41:03.89#ibcon#wrote, iclass 7, count 0 2006.174.01:41:03.89#ibcon#about to read 3, iclass 7, count 0 2006.174.01:41:03.92#ibcon#read 3, iclass 7, count 0 2006.174.01:41:03.92#ibcon#about to read 4, iclass 7, count 0 2006.174.01:41:03.92#ibcon#read 4, iclass 7, count 0 2006.174.01:41:03.92#ibcon#about to read 5, iclass 7, count 0 2006.174.01:41:03.92#ibcon#read 5, iclass 7, count 0 2006.174.01:41:03.92#ibcon#about to read 6, iclass 7, count 0 2006.174.01:41:03.92#ibcon#read 6, iclass 7, count 0 2006.174.01:41:03.92#ibcon#end of sib2, iclass 7, count 0 2006.174.01:41:03.92#ibcon#*after write, iclass 7, count 0 2006.174.01:41:03.92#ibcon#*before return 0, iclass 7, count 0 2006.174.01:41:03.92#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.174.01:41:03.92#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.174.01:41:03.92#ibcon#about to clear, iclass 7 cls_cnt 0 2006.174.01:41:03.92#ibcon#cleared, iclass 7 cls_cnt 0 2006.174.01:41:03.92$vck44/vblo=7,734.99 2006.174.01:41:03.92#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.174.01:41:03.92#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.174.01:41:03.92#ibcon#ireg 17 cls_cnt 0 2006.174.01:41:03.92#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.174.01:41:03.92#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.174.01:41:03.92#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.174.01:41:03.92#ibcon#enter wrdev, iclass 11, count 0 2006.174.01:41:03.92#ibcon#first serial, iclass 11, count 0 2006.174.01:41:03.92#ibcon#enter sib2, iclass 11, count 0 2006.174.01:41:03.92#ibcon#flushed, iclass 11, count 0 2006.174.01:41:03.92#ibcon#about to write, iclass 11, count 0 2006.174.01:41:03.92#ibcon#wrote, iclass 11, count 0 2006.174.01:41:03.92#ibcon#about to read 3, iclass 11, count 0 2006.174.01:41:03.94#ibcon#read 3, iclass 11, count 0 2006.174.01:41:03.94#ibcon#about to read 4, iclass 11, count 0 2006.174.01:41:03.94#ibcon#read 4, iclass 11, count 0 2006.174.01:41:03.94#ibcon#about to read 5, iclass 11, count 0 2006.174.01:41:03.94#ibcon#read 5, iclass 11, count 0 2006.174.01:41:03.94#ibcon#about to read 6, iclass 11, count 0 2006.174.01:41:03.94#ibcon#read 6, iclass 11, count 0 2006.174.01:41:03.94#ibcon#end of sib2, iclass 11, count 0 2006.174.01:41:03.94#ibcon#*mode == 0, iclass 11, count 0 2006.174.01:41:03.94#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.174.01:41:03.94#ibcon#[28=FRQ=07,734.99\r\n] 2006.174.01:41:03.94#ibcon#*before write, iclass 11, count 0 2006.174.01:41:03.94#ibcon#enter sib2, iclass 11, count 0 2006.174.01:41:03.94#ibcon#flushed, iclass 11, count 0 2006.174.01:41:03.94#ibcon#about to write, iclass 11, count 0 2006.174.01:41:03.94#ibcon#wrote, iclass 11, count 0 2006.174.01:41:03.94#ibcon#about to read 3, iclass 11, count 0 2006.174.01:41:03.98#ibcon#read 3, iclass 11, count 0 2006.174.01:41:03.98#ibcon#about to read 4, iclass 11, count 0 2006.174.01:41:03.98#ibcon#read 4, iclass 11, count 0 2006.174.01:41:03.98#ibcon#about to read 5, iclass 11, count 0 2006.174.01:41:03.98#ibcon#read 5, iclass 11, count 0 2006.174.01:41:03.98#ibcon#about to read 6, iclass 11, count 0 2006.174.01:41:03.98#ibcon#read 6, iclass 11, count 0 2006.174.01:41:03.98#ibcon#end of sib2, iclass 11, count 0 2006.174.01:41:03.98#ibcon#*after write, iclass 11, count 0 2006.174.01:41:03.98#ibcon#*before return 0, iclass 11, count 0 2006.174.01:41:03.98#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.174.01:41:03.98#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.174.01:41:03.98#ibcon#about to clear, iclass 11 cls_cnt 0 2006.174.01:41:03.98#ibcon#cleared, iclass 11 cls_cnt 0 2006.174.01:41:03.98$vck44/vb=7,4 2006.174.01:41:03.98#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.174.01:41:03.98#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.174.01:41:03.98#ibcon#ireg 11 cls_cnt 2 2006.174.01:41:03.98#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.174.01:41:04.04#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.174.01:41:04.04#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.174.01:41:04.04#ibcon#enter wrdev, iclass 13, count 2 2006.174.01:41:04.04#ibcon#first serial, iclass 13, count 2 2006.174.01:41:04.04#ibcon#enter sib2, iclass 13, count 2 2006.174.01:41:04.04#ibcon#flushed, iclass 13, count 2 2006.174.01:41:04.04#ibcon#about to write, iclass 13, count 2 2006.174.01:41:04.04#ibcon#wrote, iclass 13, count 2 2006.174.01:41:04.04#ibcon#about to read 3, iclass 13, count 2 2006.174.01:41:04.06#ibcon#read 3, iclass 13, count 2 2006.174.01:41:04.06#ibcon#about to read 4, iclass 13, count 2 2006.174.01:41:04.06#ibcon#read 4, iclass 13, count 2 2006.174.01:41:04.06#ibcon#about to read 5, iclass 13, count 2 2006.174.01:41:04.06#ibcon#read 5, iclass 13, count 2 2006.174.01:41:04.06#ibcon#about to read 6, iclass 13, count 2 2006.174.01:41:04.06#ibcon#read 6, iclass 13, count 2 2006.174.01:41:04.06#ibcon#end of sib2, iclass 13, count 2 2006.174.01:41:04.06#ibcon#*mode == 0, iclass 13, count 2 2006.174.01:41:04.06#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.174.01:41:04.06#ibcon#[27=AT07-04\r\n] 2006.174.01:41:04.06#ibcon#*before write, iclass 13, count 2 2006.174.01:41:04.06#ibcon#enter sib2, iclass 13, count 2 2006.174.01:41:04.06#ibcon#flushed, iclass 13, count 2 2006.174.01:41:04.06#ibcon#about to write, iclass 13, count 2 2006.174.01:41:04.06#ibcon#wrote, iclass 13, count 2 2006.174.01:41:04.06#ibcon#about to read 3, iclass 13, count 2 2006.174.01:41:04.09#ibcon#read 3, iclass 13, count 2 2006.174.01:41:04.09#ibcon#about to read 4, iclass 13, count 2 2006.174.01:41:04.09#ibcon#read 4, iclass 13, count 2 2006.174.01:41:04.09#ibcon#about to read 5, iclass 13, count 2 2006.174.01:41:04.09#ibcon#read 5, iclass 13, count 2 2006.174.01:41:04.09#ibcon#about to read 6, iclass 13, count 2 2006.174.01:41:04.09#ibcon#read 6, iclass 13, count 2 2006.174.01:41:04.09#ibcon#end of sib2, iclass 13, count 2 2006.174.01:41:04.09#ibcon#*after write, iclass 13, count 2 2006.174.01:41:04.09#ibcon#*before return 0, iclass 13, count 2 2006.174.01:41:04.09#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.174.01:41:04.09#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.174.01:41:04.09#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.174.01:41:04.09#ibcon#ireg 7 cls_cnt 0 2006.174.01:41:04.09#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.174.01:41:04.21#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.174.01:41:04.21#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.174.01:41:04.21#ibcon#enter wrdev, iclass 13, count 0 2006.174.01:41:04.21#ibcon#first serial, iclass 13, count 0 2006.174.01:41:04.21#ibcon#enter sib2, iclass 13, count 0 2006.174.01:41:04.21#ibcon#flushed, iclass 13, count 0 2006.174.01:41:04.21#ibcon#about to write, iclass 13, count 0 2006.174.01:41:04.21#ibcon#wrote, iclass 13, count 0 2006.174.01:41:04.21#ibcon#about to read 3, iclass 13, count 0 2006.174.01:41:04.23#ibcon#read 3, iclass 13, count 0 2006.174.01:41:04.23#ibcon#about to read 4, iclass 13, count 0 2006.174.01:41:04.23#ibcon#read 4, iclass 13, count 0 2006.174.01:41:04.23#ibcon#about to read 5, iclass 13, count 0 2006.174.01:41:04.23#ibcon#read 5, iclass 13, count 0 2006.174.01:41:04.23#ibcon#about to read 6, iclass 13, count 0 2006.174.01:41:04.23#ibcon#read 6, iclass 13, count 0 2006.174.01:41:04.23#ibcon#end of sib2, iclass 13, count 0 2006.174.01:41:04.23#ibcon#*mode == 0, iclass 13, count 0 2006.174.01:41:04.23#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.174.01:41:04.23#ibcon#[27=USB\r\n] 2006.174.01:41:04.23#ibcon#*before write, iclass 13, count 0 2006.174.01:41:04.23#ibcon#enter sib2, iclass 13, count 0 2006.174.01:41:04.23#ibcon#flushed, iclass 13, count 0 2006.174.01:41:04.23#ibcon#about to write, iclass 13, count 0 2006.174.01:41:04.23#ibcon#wrote, iclass 13, count 0 2006.174.01:41:04.23#ibcon#about to read 3, iclass 13, count 0 2006.174.01:41:04.26#ibcon#read 3, iclass 13, count 0 2006.174.01:41:04.26#ibcon#about to read 4, iclass 13, count 0 2006.174.01:41:04.26#ibcon#read 4, iclass 13, count 0 2006.174.01:41:04.26#ibcon#about to read 5, iclass 13, count 0 2006.174.01:41:04.26#ibcon#read 5, iclass 13, count 0 2006.174.01:41:04.26#ibcon#about to read 6, iclass 13, count 0 2006.174.01:41:04.26#ibcon#read 6, iclass 13, count 0 2006.174.01:41:04.26#ibcon#end of sib2, iclass 13, count 0 2006.174.01:41:04.26#ibcon#*after write, iclass 13, count 0 2006.174.01:41:04.26#ibcon#*before return 0, iclass 13, count 0 2006.174.01:41:04.26#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.174.01:41:04.26#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.174.01:41:04.26#ibcon#about to clear, iclass 13 cls_cnt 0 2006.174.01:41:04.26#ibcon#cleared, iclass 13 cls_cnt 0 2006.174.01:41:04.26$vck44/vblo=8,744.99 2006.174.01:41:04.26#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.174.01:41:04.26#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.174.01:41:04.26#ibcon#ireg 17 cls_cnt 0 2006.174.01:41:04.26#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.174.01:41:04.26#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.174.01:41:04.26#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.174.01:41:04.26#ibcon#enter wrdev, iclass 15, count 0 2006.174.01:41:04.26#ibcon#first serial, iclass 15, count 0 2006.174.01:41:04.26#ibcon#enter sib2, iclass 15, count 0 2006.174.01:41:04.26#ibcon#flushed, iclass 15, count 0 2006.174.01:41:04.26#ibcon#about to write, iclass 15, count 0 2006.174.01:41:04.26#ibcon#wrote, iclass 15, count 0 2006.174.01:41:04.26#ibcon#about to read 3, iclass 15, count 0 2006.174.01:41:04.28#ibcon#read 3, iclass 15, count 0 2006.174.01:41:04.28#ibcon#about to read 4, iclass 15, count 0 2006.174.01:41:04.28#ibcon#read 4, iclass 15, count 0 2006.174.01:41:04.28#ibcon#about to read 5, iclass 15, count 0 2006.174.01:41:04.28#ibcon#read 5, iclass 15, count 0 2006.174.01:41:04.28#ibcon#about to read 6, iclass 15, count 0 2006.174.01:41:04.28#ibcon#read 6, iclass 15, count 0 2006.174.01:41:04.28#ibcon#end of sib2, iclass 15, count 0 2006.174.01:41:04.28#ibcon#*mode == 0, iclass 15, count 0 2006.174.01:41:04.28#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.174.01:41:04.28#ibcon#[28=FRQ=08,744.99\r\n] 2006.174.01:41:04.28#ibcon#*before write, iclass 15, count 0 2006.174.01:41:04.28#ibcon#enter sib2, iclass 15, count 0 2006.174.01:41:04.28#ibcon#flushed, iclass 15, count 0 2006.174.01:41:04.28#ibcon#about to write, iclass 15, count 0 2006.174.01:41:04.28#ibcon#wrote, iclass 15, count 0 2006.174.01:41:04.28#ibcon#about to read 3, iclass 15, count 0 2006.174.01:41:04.32#ibcon#read 3, iclass 15, count 0 2006.174.01:41:04.32#ibcon#about to read 4, iclass 15, count 0 2006.174.01:41:04.32#ibcon#read 4, iclass 15, count 0 2006.174.01:41:04.32#ibcon#about to read 5, iclass 15, count 0 2006.174.01:41:04.32#ibcon#read 5, iclass 15, count 0 2006.174.01:41:04.32#ibcon#about to read 6, iclass 15, count 0 2006.174.01:41:04.32#ibcon#read 6, iclass 15, count 0 2006.174.01:41:04.32#ibcon#end of sib2, iclass 15, count 0 2006.174.01:41:04.32#ibcon#*after write, iclass 15, count 0 2006.174.01:41:04.32#ibcon#*before return 0, iclass 15, count 0 2006.174.01:41:04.32#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.174.01:41:04.32#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.174.01:41:04.32#ibcon#about to clear, iclass 15 cls_cnt 0 2006.174.01:41:04.32#ibcon#cleared, iclass 15 cls_cnt 0 2006.174.01:41:04.32$vck44/vb=8,4 2006.174.01:41:04.32#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.174.01:41:04.32#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.174.01:41:04.32#ibcon#ireg 11 cls_cnt 2 2006.174.01:41:04.32#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.174.01:41:04.38#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.174.01:41:04.38#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.174.01:41:04.38#ibcon#enter wrdev, iclass 17, count 2 2006.174.01:41:04.38#ibcon#first serial, iclass 17, count 2 2006.174.01:41:04.38#ibcon#enter sib2, iclass 17, count 2 2006.174.01:41:04.38#ibcon#flushed, iclass 17, count 2 2006.174.01:41:04.38#ibcon#about to write, iclass 17, count 2 2006.174.01:41:04.38#ibcon#wrote, iclass 17, count 2 2006.174.01:41:04.38#ibcon#about to read 3, iclass 17, count 2 2006.174.01:41:04.40#ibcon#read 3, iclass 17, count 2 2006.174.01:41:04.40#ibcon#about to read 4, iclass 17, count 2 2006.174.01:41:04.40#ibcon#read 4, iclass 17, count 2 2006.174.01:41:04.40#ibcon#about to read 5, iclass 17, count 2 2006.174.01:41:04.40#ibcon#read 5, iclass 17, count 2 2006.174.01:41:04.40#ibcon#about to read 6, iclass 17, count 2 2006.174.01:41:04.40#ibcon#read 6, iclass 17, count 2 2006.174.01:41:04.40#ibcon#end of sib2, iclass 17, count 2 2006.174.01:41:04.40#ibcon#*mode == 0, iclass 17, count 2 2006.174.01:41:04.40#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.174.01:41:04.40#ibcon#[27=AT08-04\r\n] 2006.174.01:41:04.40#ibcon#*before write, iclass 17, count 2 2006.174.01:41:04.40#ibcon#enter sib2, iclass 17, count 2 2006.174.01:41:04.40#ibcon#flushed, iclass 17, count 2 2006.174.01:41:04.40#ibcon#about to write, iclass 17, count 2 2006.174.01:41:04.40#ibcon#wrote, iclass 17, count 2 2006.174.01:41:04.40#ibcon#about to read 3, iclass 17, count 2 2006.174.01:41:04.43#ibcon#read 3, iclass 17, count 2 2006.174.01:41:04.43#ibcon#about to read 4, iclass 17, count 2 2006.174.01:41:04.43#ibcon#read 4, iclass 17, count 2 2006.174.01:41:04.43#ibcon#about to read 5, iclass 17, count 2 2006.174.01:41:04.43#ibcon#read 5, iclass 17, count 2 2006.174.01:41:04.43#ibcon#about to read 6, iclass 17, count 2 2006.174.01:41:04.43#ibcon#read 6, iclass 17, count 2 2006.174.01:41:04.43#ibcon#end of sib2, iclass 17, count 2 2006.174.01:41:04.43#ibcon#*after write, iclass 17, count 2 2006.174.01:41:04.43#ibcon#*before return 0, iclass 17, count 2 2006.174.01:41:04.43#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.174.01:41:04.43#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.174.01:41:04.43#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.174.01:41:04.43#ibcon#ireg 7 cls_cnt 0 2006.174.01:41:04.43#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.174.01:41:04.55#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.174.01:41:04.55#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.174.01:41:04.55#ibcon#enter wrdev, iclass 17, count 0 2006.174.01:41:04.55#ibcon#first serial, iclass 17, count 0 2006.174.01:41:04.55#ibcon#enter sib2, iclass 17, count 0 2006.174.01:41:04.55#ibcon#flushed, iclass 17, count 0 2006.174.01:41:04.55#ibcon#about to write, iclass 17, count 0 2006.174.01:41:04.55#ibcon#wrote, iclass 17, count 0 2006.174.01:41:04.55#ibcon#about to read 3, iclass 17, count 0 2006.174.01:41:04.57#ibcon#read 3, iclass 17, count 0 2006.174.01:41:04.57#ibcon#about to read 4, iclass 17, count 0 2006.174.01:41:04.57#ibcon#read 4, iclass 17, count 0 2006.174.01:41:04.57#ibcon#about to read 5, iclass 17, count 0 2006.174.01:41:04.57#ibcon#read 5, iclass 17, count 0 2006.174.01:41:04.57#ibcon#about to read 6, iclass 17, count 0 2006.174.01:41:04.57#ibcon#read 6, iclass 17, count 0 2006.174.01:41:04.57#ibcon#end of sib2, iclass 17, count 0 2006.174.01:41:04.57#ibcon#*mode == 0, iclass 17, count 0 2006.174.01:41:04.57#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.174.01:41:04.57#ibcon#[27=USB\r\n] 2006.174.01:41:04.57#ibcon#*before write, iclass 17, count 0 2006.174.01:41:04.57#ibcon#enter sib2, iclass 17, count 0 2006.174.01:41:04.57#ibcon#flushed, iclass 17, count 0 2006.174.01:41:04.57#ibcon#about to write, iclass 17, count 0 2006.174.01:41:04.57#ibcon#wrote, iclass 17, count 0 2006.174.01:41:04.57#ibcon#about to read 3, iclass 17, count 0 2006.174.01:41:04.60#ibcon#read 3, iclass 17, count 0 2006.174.01:41:04.60#ibcon#about to read 4, iclass 17, count 0 2006.174.01:41:04.60#ibcon#read 4, iclass 17, count 0 2006.174.01:41:04.60#ibcon#about to read 5, iclass 17, count 0 2006.174.01:41:04.60#ibcon#read 5, iclass 17, count 0 2006.174.01:41:04.60#ibcon#about to read 6, iclass 17, count 0 2006.174.01:41:04.60#ibcon#read 6, iclass 17, count 0 2006.174.01:41:04.60#ibcon#end of sib2, iclass 17, count 0 2006.174.01:41:04.60#ibcon#*after write, iclass 17, count 0 2006.174.01:41:04.60#ibcon#*before return 0, iclass 17, count 0 2006.174.01:41:04.60#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.174.01:41:04.60#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.174.01:41:04.60#ibcon#about to clear, iclass 17 cls_cnt 0 2006.174.01:41:04.60#ibcon#cleared, iclass 17 cls_cnt 0 2006.174.01:41:04.60$vck44/vabw=wide 2006.174.01:41:04.60#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.174.01:41:04.60#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.174.01:41:04.60#ibcon#ireg 8 cls_cnt 0 2006.174.01:41:04.60#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.174.01:41:04.60#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.174.01:41:04.60#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.174.01:41:04.60#ibcon#enter wrdev, iclass 19, count 0 2006.174.01:41:04.60#ibcon#first serial, iclass 19, count 0 2006.174.01:41:04.60#ibcon#enter sib2, iclass 19, count 0 2006.174.01:41:04.60#ibcon#flushed, iclass 19, count 0 2006.174.01:41:04.60#ibcon#about to write, iclass 19, count 0 2006.174.01:41:04.60#ibcon#wrote, iclass 19, count 0 2006.174.01:41:04.60#ibcon#about to read 3, iclass 19, count 0 2006.174.01:41:04.62#ibcon#read 3, iclass 19, count 0 2006.174.01:41:04.62#ibcon#about to read 4, iclass 19, count 0 2006.174.01:41:04.62#ibcon#read 4, iclass 19, count 0 2006.174.01:41:04.62#ibcon#about to read 5, iclass 19, count 0 2006.174.01:41:04.62#ibcon#read 5, iclass 19, count 0 2006.174.01:41:04.62#ibcon#about to read 6, iclass 19, count 0 2006.174.01:41:04.62#ibcon#read 6, iclass 19, count 0 2006.174.01:41:04.62#ibcon#end of sib2, iclass 19, count 0 2006.174.01:41:04.62#ibcon#*mode == 0, iclass 19, count 0 2006.174.01:41:04.62#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.174.01:41:04.62#ibcon#[25=BW32\r\n] 2006.174.01:41:04.62#ibcon#*before write, iclass 19, count 0 2006.174.01:41:04.62#ibcon#enter sib2, iclass 19, count 0 2006.174.01:41:04.62#ibcon#flushed, iclass 19, count 0 2006.174.01:41:04.62#ibcon#about to write, iclass 19, count 0 2006.174.01:41:04.62#ibcon#wrote, iclass 19, count 0 2006.174.01:41:04.62#ibcon#about to read 3, iclass 19, count 0 2006.174.01:41:04.65#ibcon#read 3, iclass 19, count 0 2006.174.01:41:04.65#ibcon#about to read 4, iclass 19, count 0 2006.174.01:41:04.65#ibcon#read 4, iclass 19, count 0 2006.174.01:41:04.65#ibcon#about to read 5, iclass 19, count 0 2006.174.01:41:04.65#ibcon#read 5, iclass 19, count 0 2006.174.01:41:04.65#ibcon#about to read 6, iclass 19, count 0 2006.174.01:41:04.65#ibcon#read 6, iclass 19, count 0 2006.174.01:41:04.65#ibcon#end of sib2, iclass 19, count 0 2006.174.01:41:04.65#ibcon#*after write, iclass 19, count 0 2006.174.01:41:04.65#ibcon#*before return 0, iclass 19, count 0 2006.174.01:41:04.65#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.174.01:41:04.65#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.174.01:41:04.65#ibcon#about to clear, iclass 19 cls_cnt 0 2006.174.01:41:04.65#ibcon#cleared, iclass 19 cls_cnt 0 2006.174.01:41:04.65$vck44/vbbw=wide 2006.174.01:41:04.65#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.174.01:41:04.65#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.174.01:41:04.65#ibcon#ireg 8 cls_cnt 0 2006.174.01:41:04.65#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.174.01:41:04.72#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.174.01:41:04.72#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.174.01:41:04.72#ibcon#enter wrdev, iclass 21, count 0 2006.174.01:41:04.72#ibcon#first serial, iclass 21, count 0 2006.174.01:41:04.72#ibcon#enter sib2, iclass 21, count 0 2006.174.01:41:04.72#ibcon#flushed, iclass 21, count 0 2006.174.01:41:04.72#ibcon#about to write, iclass 21, count 0 2006.174.01:41:04.72#ibcon#wrote, iclass 21, count 0 2006.174.01:41:04.72#ibcon#about to read 3, iclass 21, count 0 2006.174.01:41:04.74#ibcon#read 3, iclass 21, count 0 2006.174.01:41:04.74#ibcon#about to read 4, iclass 21, count 0 2006.174.01:41:04.74#ibcon#read 4, iclass 21, count 0 2006.174.01:41:04.74#ibcon#about to read 5, iclass 21, count 0 2006.174.01:41:04.74#ibcon#read 5, iclass 21, count 0 2006.174.01:41:04.74#ibcon#about to read 6, iclass 21, count 0 2006.174.01:41:04.74#ibcon#read 6, iclass 21, count 0 2006.174.01:41:04.74#ibcon#end of sib2, iclass 21, count 0 2006.174.01:41:04.74#ibcon#*mode == 0, iclass 21, count 0 2006.174.01:41:04.74#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.174.01:41:04.74#ibcon#[27=BW32\r\n] 2006.174.01:41:04.74#ibcon#*before write, iclass 21, count 0 2006.174.01:41:04.74#ibcon#enter sib2, iclass 21, count 0 2006.174.01:41:04.74#ibcon#flushed, iclass 21, count 0 2006.174.01:41:04.74#ibcon#about to write, iclass 21, count 0 2006.174.01:41:04.74#ibcon#wrote, iclass 21, count 0 2006.174.01:41:04.74#ibcon#about to read 3, iclass 21, count 0 2006.174.01:41:04.77#ibcon#read 3, iclass 21, count 0 2006.174.01:41:04.77#ibcon#about to read 4, iclass 21, count 0 2006.174.01:41:04.77#ibcon#read 4, iclass 21, count 0 2006.174.01:41:04.77#ibcon#about to read 5, iclass 21, count 0 2006.174.01:41:04.77#ibcon#read 5, iclass 21, count 0 2006.174.01:41:04.77#ibcon#about to read 6, iclass 21, count 0 2006.174.01:41:04.77#ibcon#read 6, iclass 21, count 0 2006.174.01:41:04.77#ibcon#end of sib2, iclass 21, count 0 2006.174.01:41:04.77#ibcon#*after write, iclass 21, count 0 2006.174.01:41:04.77#ibcon#*before return 0, iclass 21, count 0 2006.174.01:41:04.77#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.174.01:41:04.77#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.174.01:41:04.77#ibcon#about to clear, iclass 21 cls_cnt 0 2006.174.01:41:04.77#ibcon#cleared, iclass 21 cls_cnt 0 2006.174.01:41:04.77$setupk4/ifdk4 2006.174.01:41:04.77$ifdk4/lo= 2006.174.01:41:04.77$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.174.01:41:04.77$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.174.01:41:04.77$ifdk4/patch= 2006.174.01:41:04.77$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.174.01:41:04.77$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.174.01:41:04.78$setupk4/!*+20s 2006.174.01:41:10.65#abcon#<5=/09 1.1 2.7 26.14 711003.3\r\n> 2006.174.01:41:10.67#abcon#{5=INTERFACE CLEAR} 2006.174.01:41:10.73#abcon#[5=S1D000X0/0*\r\n] 2006.174.01:41:15.14#trakl#Source acquired 2006.174.01:41:15.14#flagr#flagr/antenna,acquired 2006.174.01:41:19.26$setupk4/"tpicd 2006.174.01:41:19.26$setupk4/echo=off 2006.174.01:41:19.26$setupk4/xlog=off 2006.174.01:41:19.26:!2006.174.01:41:24 2006.174.01:41:24.00:preob 2006.174.01:41:25.14/onsource/TRACKING 2006.174.01:41:25.14:!2006.174.01:41:34 2006.174.01:41:34.00:"tape 2006.174.01:41:34.00:"st=record 2006.174.01:41:34.00:data_valid=on 2006.174.01:41:34.00:midob 2006.174.01:41:34.14/onsource/TRACKING 2006.174.01:41:34.14/wx/26.13,1003.3,71 2006.174.01:41:34.28/cable/+6.5008E-03 2006.174.01:41:35.37/va/01,07,usb,yes,44,47 2006.174.01:41:35.37/va/02,06,usb,yes,44,45 2006.174.01:41:35.37/va/03,05,usb,yes,55,57 2006.174.01:41:35.37/va/04,06,usb,yes,45,47 2006.174.01:41:35.37/va/05,04,usb,yes,36,36 2006.174.01:41:35.37/va/06,03,usb,yes,49,49 2006.174.01:41:35.37/va/07,04,usb,yes,40,42 2006.174.01:41:35.37/va/08,04,usb,yes,34,41 2006.174.01:41:35.60/valo/01,524.99,yes,locked 2006.174.01:41:35.60/valo/02,534.99,yes,locked 2006.174.01:41:35.60/valo/03,564.99,yes,locked 2006.174.01:41:35.60/valo/04,624.99,yes,locked 2006.174.01:41:35.60/valo/05,734.99,yes,locked 2006.174.01:41:35.60/valo/06,814.99,yes,locked 2006.174.01:41:35.60/valo/07,864.99,yes,locked 2006.174.01:41:35.60/valo/08,884.99,yes,locked 2006.174.01:41:36.69/vb/01,04,usb,yes,33,60 2006.174.01:41:36.69/vb/02,04,usb,yes,35,60 2006.174.01:41:36.69/vb/03,04,usb,yes,32,39 2006.174.01:41:36.69/vb/04,04,usb,yes,36,35 2006.174.01:41:36.69/vb/05,04,usb,yes,30,32 2006.174.01:41:36.69/vb/06,04,usb,yes,35,31 2006.174.01:41:36.69/vb/07,04,usb,yes,33,33 2006.174.01:41:36.69/vb/08,04,usb,yes,31,35 2006.174.01:41:36.92/vblo/01,629.99,yes,locked 2006.174.01:41:36.92/vblo/02,634.99,yes,locked 2006.174.01:41:36.92/vblo/03,649.99,yes,locked 2006.174.01:41:36.92/vblo/04,679.99,yes,locked 2006.174.01:41:36.92/vblo/05,709.99,yes,locked 2006.174.01:41:36.92/vblo/06,719.99,yes,locked 2006.174.01:41:36.92/vblo/07,734.99,yes,locked 2006.174.01:41:36.92/vblo/08,744.99,yes,locked 2006.174.01:41:37.07/vabw/8 2006.174.01:41:37.22/vbbw/8 2006.174.01:41:37.31/xfe/off,on,15.2 2006.174.01:41:37.69/ifatt/23,28,28,28 2006.174.01:41:38.07/fmout-gps/S +3.78E-07 2006.174.01:41:38.12:!2006.174.01:54:38 2006.174.01:54:38.00:data_valid=off 2006.174.01:54:38.00:"et 2006.174.01:54:38.01:!+3s 2006.174.01:54:41.02:"tape 2006.174.01:54:41.02:postob 2006.174.01:54:41.20/cable/+6.4974E-03 2006.174.01:54:41.20/wx/25.93,1003.3,79 2006.174.01:54:41.26/fmout-gps/S +3.85E-07 2006.174.01:54:41.26:"unlod=1 2006.174.01:54:41.27:"sched_end 2006.174.01:54:41.27:source=azel,0d,88d 2006.174.01:54:43.14#flagr#flagr/antenna,new-source 2006.174.01:54:43.14:checkk5last 2006.174.01:54:43.14&checkk5last/chk_obsdata=1 2006.174.01:54:43.14&checkk5last/chk_obsdata=2 2006.174.01:54:43.14&checkk5last/chk_obsdata=3 2006.174.01:54:43.14&checkk5last/chk_obsdata=4 2006.174.01:54:43.14&checkk5last/k5log=1 2006.174.01:54:43.14&checkk5last/k5log=2 2006.174.01:54:43.14&checkk5last/k5log=3 2006.174.01:54:43.14&checkk5last/k5log=4 2006.174.01:54:43.14&checkk5last/obsinfo 2006.174.01:54:44.03/chk_obsdata//k5ts1/T1740141??a.dat file size is correct (nominal:3136MB, actual:3136MB). 2006.174.01:54:44.74/chk_obsdata//k5ts2/T1740141??b.dat file size is correct (nominal:3136MB, actual:3136MB). 2006.174.01:54:45.44/chk_obsdata//k5ts3/T1740141??c.dat file size is correct (nominal:3136MB, actual:3136MB). 2006.174.01:54:46.16/chk_obsdata//k5ts4/T1740141??d.dat file size is correct (nominal:3136MB, actual:3136MB). 2006.174.01:54:46.86/k5log//k5ts1_log_newline 2006.174.01:54:47.57/k5log//k5ts2_log_newline 2006.174.01:54:48.28/k5log//k5ts3_log_newline 2006.174.01:54:48.98/k5log//k5ts4_log_newline 2006.174.01:54:49.00/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.174.01:54:49.00:sy=cp /usr2/log/jd0606ts.log /usr2/log_backup/ 2006.174.01:54:49.19:proc=s06174ts 2006.174.01:54:49.20:log=s06174ts